Project import generated by Copybara.
GitOrigin-RevId: ceda9993b5e33a3605cf30ca3862478abb29e23f
diff --git a/Kconfig b/Kconfig
index 9278e59..2cc272b 100644
--- a/Kconfig
+++ b/Kconfig
@@ -70,11 +70,11 @@
bool "Select defaults suitable for booting general purpose Linux distributions"
select AUTO_COMPLETE
select CMDLINE_EDITING
- select CMD_BOOTI if ARM64
- select CMD_BOOTZ if ARM && !ARM64
+ select CMD_BOOTI if ARM64 && !AML_DISABLE_DEV_CMDS
+ select CMD_BOOTZ if ARM && !ARM64 && !AML_DISABLE_DEV_CMDS
select CMD_DHCP if CMD_NET
- select CMD_PING if CMD_NET
select CMD_ENV_EXISTS
+ select CMD_EXT2
select CMD_EXT4
select CMD_FAT
select CMD_FS_GENERIC
@@ -275,20 +275,10 @@
SHA256 variant is supported: SHA512 and others are not currently
supported in U-Boot.
-config FIT_FULL_CHECK
- bool "Do a full check of the FIT before using it"
- default y
- help
- Enable this do a full check of the FIT to make sure it is valid. This
- helps to protect against carefully crafted FITs which take advantage
- of bugs or omissions in the code. This includes a bad structure,
- multiple root nodes and the like.
-
config FIT_SIGNATURE
bool "Enable signature verification of FIT uImages"
depends on DM
select HASH
- select FIT_FULL_CHECK
select RSA
help
This option enables signature verification of FIT uImages,
@@ -365,21 +355,11 @@
help
Support printing the content of the fitImage in a verbose manner in SPL.
-config SPL_FIT_FULL_CHECK
- bool "Do a full check of the FIT before using it"
- help
- Enable this do a full check of the FIT to make sure it is valid. This
- helps to protect against carefully crafted FITs which take advantage
- of bugs or omissions in the code. This includes a bad structure,
- multiple root nodes and the like.
-
-
config SPL_FIT_SIGNATURE
bool "Enable signature verification of FIT firmware within SPL"
depends on SPL_DM
select SPL_FIT
select SPL_RSA
- select SPL_FIT_FULL_CHECK
config SPL_LOAD_FIT
bool "Enable SPL loading U-Boot as a FIT"
@@ -541,4 +521,3 @@
source "lib/Kconfig"
source "test/Kconfig"
-
diff --git a/Makefile b/Makefile
index 6dbe24c..6087d06 100644
--- a/Makefile
+++ b/Makefile
@@ -42,16 +42,6 @@
# descending is started. They are now explicitly listed as the
# prepare rule.
-# We use U_BOOT_DATE and U_BOOT_TIME to record u-boot build timestamp.
-# make T=0 or by default to use local time (date) as build timestamp.
-# make T=1 to use latest git commit time as build timestamp.
-ifeq ("$(origin T)", "command line")
- KBUILD_TIME_STAMP = $(T)
-endif
-ifndef KBUILD_TIME_STAMP
- KBUILD_TIME_STAMP = 0
-endif
-
# Beautify output
# ---------------------------------------------------------------------------
#
@@ -131,6 +121,8 @@
# Do we want to locate output files in a separate directory?
ifeq ("$(origin O)", "command line")
KBUILD_OUTPUT := $(O)
+else
+ KBUILD_OUTPUT := build
endif
# That's our default target when none is given on the command line
@@ -228,7 +220,7 @@
buildsrc := $(abspath $(srctree))
buildtree := $(abspath $(CURDIR)/$(KBUILD_OUTPUT))
-export srctree objtree VPATH buildsrc buildtree
+export srctree objtree VPATH buildsrc buildtree KBUILD_OUTPUT
# Make sure CDPATH settings don't interfere
unexport CDPATH
@@ -257,6 +249,9 @@
CROSS_COMPILE ?=
endif
+CROSS_COMPILE ?=/opt/gcc-linaro-7.3.1-2018.05-i686_aarch64-elf/bin/aarch64-elf-
+export CROSS_COMPILE
+
KCONFIG_CONFIG ?= .config
export KCONFIG_CONFIG
@@ -345,7 +340,6 @@
export KBUILD_MODULES KBUILD_BUILTIN
export KBUILD_CHECKSRC KBUILD_SRC KBUILD_EXTMOD
-export BL33_DEBUG
# We need some generic definitions (do not try to remake the file).
scripts/Kbuild.include: ;
@@ -383,14 +377,11 @@
KBUILD_CPPFLAGS := -D__KERNEL__ -D__UBOOT__
-KBUILD_CFLAGS := -Wall -Wstrict-prototypes \
+KBUILD_CFLAGS := -Wall -Wstrict-prototypes -Werror \
-Wno-format-security \
-fno-builtin -ffreestanding $(CSTD_FLAG)
KBUILD_CFLAGS += -fshort-wchar -fno-strict-aliasing
KBUILD_AFLAGS := -D__ASSEMBLY__
-ifeq ($(BL33_DEBUG), 1)
- KBUILD_CFLAGS+=-DBL33_DEBUG_PRINT
-endif
# Don't generate position independent code
KBUILD_CFLAGS += $(call cc-option,-fno-PIE)
@@ -400,7 +391,9 @@
UBOOTRELEASE = $(shell cat include/config/uboot.release 2> /dev/null)
UBOOTVERSION = $(VERSION)$(if $(PATCHLEVEL),.$(PATCHLEVEL)$(if $(SUBLEVEL),.$(SUBLEVEL)))$(EXTRAVERSION)
-export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION
+ACSRELEASE = $(shell cat include/config/acs.release 2> /dev/null)
+
+export VERSION PATCHLEVEL SUBLEVEL UBOOTRELEASE UBOOTVERSION ACSRELEASE
export ARCH CPU BOARD VENDOR SOC CPUDIR BOARDDIR
export CONFIG_SHELL HOSTCC HOSTCFLAGS HOSTLDFLAGS CROSS_COMPILE AS LD CC
export CPP AR NM LDR STRIP OBJCOPY OBJDUMP
@@ -431,6 +424,13 @@
scripts_basic:
$(Q)$(MAKE) $(build)=scripts/basic
$(Q)rm -f .tmp_quiet_recordmcount
+ $(Q)if [ -d $(srctree)/.git/hooks ]; then \
+ if [ ! -f $(srctree)/.git/hooks/pre-commit-old -a -f $(srctree)/.git/hooks/pre-commit ]; then \
+ cp $(srctree)/.git/hooks/pre-commit $(srctree)/.git/hooks/pre-commit-old; \
+ fi; \
+ cp $(srctree)/scripts/amlogic/coding_style/pre-commit $(srctree)/.git/hooks/; \
+ chmod +x $(srctree)/.git/hooks/pre-commit; \
+ fi
# To avoid any implicit rule to kick in, define an empty command.
scripts/basic/%: scripts_basic ;
@@ -457,7 +457,6 @@
version_h := include/generated/version_autogenerated.h
timestamp_h := include/generated/timestamp_autogenerated.h
defaultenv_h := include/generated/defaultenv_autogenerated.h
-timestamp_git_h := include/generated/timestamp_autogenerated.h
no-dot-config-targets := clean clobber mrproper distclean \
help %docs check% coccicheck \
@@ -482,10 +481,6 @@
endif
endif
-ifneq ($(ENABLE_UBOOT_UPDATE),1)
- KBUILD_CFLAGS += -DAML_DISABLE_UPDATE_MODE
-endif
-
ifeq ($(mixed-targets),1)
# ===========================================================================
# We're called with mixed targets (*config and build targets).
@@ -630,7 +625,8 @@
KBUILD_CFLAGS += -O2
endif
-KBUILD_CFLAGS += $(call cc-option,-fno-stack-protector)
+STACK_CFLAGS := $(call cc-option,-fstack-protector-strong)
+KBUILD_CFLAGS += $(STACK_CFLAGS)
KBUILD_CFLAGS += $(call cc-option,-fno-delete-null-pointer-checks)
# change __FILE__ to the relative path from the srctree
@@ -676,10 +672,6 @@
KBUILD_AFLAGS += $(KAFLAGS)
KBUILD_CFLAGS += $(KCFLAGS)
-ifdef BOARD_NAME
-KBUILD_CFLAGS += -DBOARD_NAME='"$(BOARD_NAME)"'
-endif
-
# Use UBOOTINCLUDE when you must reference the include/ directory.
# Needed to be compatible with the O= option
UBOOTINCLUDE := \
@@ -767,7 +759,6 @@
u-boot-init := $(head-y)
u-boot-main := $(libs-y)
-
# Add GCC lib
ifeq ($(CONFIG_USE_PRIVATE_LIBGCC),y)
PLATFORM_LIBGCC = arch/$(ARCH)/lib/lib.a
@@ -1566,10 +1557,17 @@
echo "$(UBOOTVERSION)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))"
endef
+define filechk_acs.release
+ echo "$(BOARD)$$($(CONFIG_SHELL) $(srctree)/scripts/setlocalversion $(srctree))"
+endef
+
# Store (new) UBOOTRELEASE string in include/config/uboot.release
include/config/uboot.release: include/config/auto.conf FORCE
$(call filechk,uboot.release)
+include/config/acs.release: include/config/auto.conf FORCE
+ $(call filechk,acs.release)
+
# Things we need to do before we recursively start building the kernel
# or the modules are listed in "prepare".
@@ -1583,7 +1581,7 @@
# prepare3 is used to check if we are building in a separate output directory,
# and if so do:
# 1) Check that make has not been executed in the kernel src $(srctree)
-prepare3: include/config/uboot.release
+prepare3: include/config/uboot.release include/config/acs.release
ifneq ($(KBUILD_SRC),)
@$(kecho) ' Using $(srctree) as source for U-Boot'
$(Q)if [ -f $(srctree)/.config -o -d $(srctree)/include/config ]; then \
@@ -1620,9 +1618,11 @@
define filechk_version.h
(echo \#define PLAIN_VERSION \"$(UBOOTRELEASE)\"; \
+ echo \#define ACS_VERSION \"$(ACSRELEASE)\"; \
echo \#define U_BOOT_VERSION \"U-Boot \" PLAIN_VERSION; \
echo \#define CONFIG_SYSTEM_AS_ROOT \"${SYSTEMMODE}\"; \
echo \#define CONFIG_AVB2 \"${AVBMODE}\"; \
+ echo \#define CONFIG_CMD_BOOTCTOL_VAB \"${BOOTCTRLMODE}\"; \
echo \#define CC_VERSION_STRING \"$$(LC_ALL=C $(CC) --version | head -n 1)\"; \
echo \#define LD_VERSION_STRING \"$$(LC_ALL=C $(LD) --version | head -n 1)\"; )
endef
@@ -1644,6 +1644,7 @@
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_TZ "%z"'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
+ LC_ALL=C $${DATE} -u -d "$${SOURCE_DATE}" +'#define U_BOOT_DATE_TIME "%y%m%d.%H%M%S"'; \
else \
return 42; \
fi; \
@@ -1653,6 +1654,7 @@
LC_ALL=C date +'#define U_BOOT_TZ "%z"'; \
LC_ALL=C date +'#define U_BOOT_DMI_DATE "%m/%d/%Y"'; \
LC_ALL=C date +'#define U_BOOT_BUILD_DATE 0x%Y%m%d'; \
+ LC_ALL=C date +'#define U_BOOT_DATE_TIME "%y%m%d.%H%M%S"'; \
fi)
endef
@@ -1664,28 +1666,11 @@
xxd -i ; echo ", 0x00" ; )
endef
-define filechk_timestamp_git.h
- (echo \#define U_BOOT_DATE \"$(shell git log -1 --format=%cd --date=format:"%b %d %C%y")\"; \
- echo \#define U_BOOT_TIME \"$(shell git log -1 --format=%cd --date=format:"%T")\"; \
- echo \#define U_BOOT_TZ \"$(shell git log -1 --format=%cd --date=format:"%Z")\"; \
- echo \#define U_BOOT_DMI_DATE \"$(shell git log -1 --format=%cd --date=format:"%m/%d/%Y")\"; \
- echo \#define U_BOOT_BUILD_DATE \"$(shell git log -1 --format=%cd --date=format:"0x%Y%m%d")\";)
-endef
-
-export U_BOOT_TIME_GIT=$(shell git log -1 --format=%cd --date=format:"%T")
-export U_BOOT_DATE_GIT=$(shell git log -1 --format=%cd --date=format:"%b %d %C%y")
-
-$(version_h): include/config/uboot.release FORCE
+$(version_h): include/config/uboot.release include/config/acs.release FORCE
$(call filechk,version.h)
-
-ifeq ($(KBUILD_TIME_STAMP),0)
$(timestamp_h): $(srctree)/Makefile FORCE
$(call filechk,timestamp.h)
-else
-$(timestamp_git_h): $(srctree)/Makefile FORCE
- $(call filechk,timestamp_git.h)
-endif
$(defaultenv_h): $(CONFIG_DEFAULT_ENV_FILE:"%"=%) FORCE
$(call filechk,defaultenv.h)
@@ -1791,13 +1776,13 @@
$(filter-out include, $(shell ls -1 $d 2>/dev/null))))
CLEAN_FILES += include/bmp_logo.h include/bmp_logo_data.h \
- u-boot.* MLO* SPL System.map fit-dtb.blob
+ boot* u-boot* MLO* SPL System.map fit-dtb.blob
# Directories & files removed with 'make mrproper'
MRPROPER_DIRS += include/config include/generated spl tpl \
.tmp_objdiff
MRPROPER_FILES += .config .config.old include/autoconf.mk* include/config.h \
- ctags etags tags
+ ctags etags tags TAGS cscope* GPATH GTAGS GRTAGS GSYMS
# clean - Delete most, but leave enough to build external modules
#
@@ -1853,6 +1838,7 @@
-o -name '*.pyc' \) \
-type f -print | xargs rm -f
@rm -f boards.cfg
+ @rm -rf $(srctree)/build
backup:
F=`basename $(srctree)` ; cd .. ; \
@@ -1906,8 +1892,6 @@
@echo ' 2: warnings which occur quite often but may still be relevant'
@echo ' 3: more obscure warnings, can most likely be ignored'
@echo ' Multiple levels can be combined with W=12 or W=123'
- @echo ' make T=0 [targets] 0 => use local time (date) as build timestamp'
- @echo ' make T=1 [targets] 1 => use latest git commit time as build timestamp'
@echo ''
@echo 'Execute "make" or "make all" to build all targets marked with [*] '
@echo 'For further info see the ./README file'
diff --git a/api/Kconfig b/api/Kconfig
index e418adc..16731d3 100644
--- a/api/Kconfig
+++ b/api/Kconfig
@@ -7,4 +7,3 @@
This option enables the U-Boot API. See api/README for more information.
endmenu
-
diff --git a/arch/Kconfig b/arch/Kconfig
index 11e7713..35e2712 100644
--- a/arch/Kconfig
+++ b/arch/Kconfig
@@ -237,4 +237,3 @@
source "arch/x86/Kconfig"
source "arch/xtensa/Kconfig"
source "arch/riscv/Kconfig"
-
diff --git a/arch/arc/Kconfig b/arch/arc/Kconfig
index 38b6ffe..fa6b344 100644
--- a/arch/arc/Kconfig
+++ b/arch/arc/Kconfig
@@ -171,4 +171,3 @@
source "board/synopsys/iot_devkit/Kconfig"
endmenu
-
diff --git a/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig b/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig
index 1db1262..986ad73 100644
--- a/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig
+++ b/arch/arm/cpu/arm926ejs/lpc32xx/Kconfig
@@ -18,4 +18,3 @@
source "board/work-microwave/work_92105/Kconfig"
endif
-
diff --git a/arch/arm/cpu/armv7/Kconfig b/arch/arm/cpu/armv7/Kconfig
index 4d0dcee..73d57a2 100644
--- a/arch/arm/cpu/armv7/Kconfig
+++ b/arch/arm/cpu/armv7/Kconfig
@@ -59,4 +59,3 @@
required if U-Boot runs in HYP mode.
endif
-
diff --git a/arch/arm/cpu/armv7/ls102xa/Kconfig b/arch/arm/cpu/armv7/ls102xa/Kconfig
index 4ffde9a..5d6a711 100644
--- a/arch/arm/cpu/armv7/ls102xa/Kconfig
+++ b/arch/arm/cpu/armv7/ls102xa/Kconfig
@@ -107,4 +107,3 @@
bool
endmenu
-
diff --git a/arch/arm/cpu/armv7/vf610/Kconfig b/arch/arm/cpu/armv7/vf610/Kconfig
index 764d1fb..13905b5 100644
--- a/arch/arm/cpu/armv7/vf610/Kconfig
+++ b/arch/arm/cpu/armv7/vf610/Kconfig
@@ -34,4 +34,3 @@
source "board/toradex/colibri_vf/Kconfig"
endif
-
diff --git a/arch/arm/cpu/armv8/Kconfig b/arch/arm/cpu/armv8/Kconfig
index d5a9158..1c12bbd 100644
--- a/arch/arm/cpu/armv8/Kconfig
+++ b/arch/arm/cpu/armv8/Kconfig
@@ -95,7 +95,7 @@
config PSCI_RESET
bool "Use PSCI for reset and shutdown"
- default n
+ default y
select ARM_SMCCC if OF_CONTROL
depends on !ARCH_EXYNOS7 && !ARCH_BCM283X && \
!TARGET_LS2080A_SIMU && !TARGET_LS2080AQDS && \
@@ -166,4 +166,3 @@
endif
endif
-
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
index b55b36c..2b086da 100644
--- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
+++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig
@@ -571,4 +571,3 @@
help
Enabling this will make a U-Boot binary that is capable of being
booted via TFA.
-
diff --git a/arch/arm/cpu/armv8/sec_firmware.c b/arch/arm/cpu/armv8/sec_firmware.c
index 3c52495..8dc0ac9 100644
--- a/arch/arm/cpu/armv8/sec_firmware.c
+++ b/arch/arm/cpu/armv8/sec_firmware.c
@@ -310,7 +310,7 @@
return false;
}
- if (fit_check_format(sec_firmware_img, IMAGE_SIZE_INVAL)) {
+ if (!fit_check_format(sec_firmware_img)) {
printf("SEC Firmware: Bad firmware image (bad FIT header)\n");
return false;
}
diff --git a/arch/arm/cpu/armv8/zynqmp/Kconfig b/arch/arm/cpu/armv8/zynqmp/Kconfig
index 91b017a..8a311e1 100644
--- a/arch/arm/cpu/armv8/zynqmp/Kconfig
+++ b/arch/arm/cpu/armv8/zynqmp/Kconfig
@@ -154,4 +154,3 @@
endchoice
endif
-
diff --git a/arch/arm/dts/elaine-b1-panel.dtsi b/arch/arm/dts/elaine-b1-panel.dtsi
deleted file mode 100755
index 5d6b445..0000000
--- a/arch/arm/dts/elaine-b1-panel.dtsi
+++ /dev/null
@@ -1,973 +0,0 @@
-/*
- * arch/arm/dts/elaine-b1-panel.dtsi
- *
- * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-/ {
- lcd{
- compatible = "amlogic, lcd-sm1";
- mode = "tablet";
- status = "okay";
- key_valid = <0>;
- clocks = <&clkc CLKID_MIPI_DSI_HOST
- &clkc CLKID_MIPI_DSI_PHY
- &clkc CLKID_DSI_MEAS_COMP
- &clkc CLKID_VCLK2_ENCL
- &clkc CLKID_VCLK2_VENCL
- &clkc CLKID_GP0_PLL>;
- clock-names = "dsi_host_gate",
- "dsi_phy_gate",
- "dsi_meas",
- "encl_top_gate",
- "encl_int_gate",
- "gp0_pll";
- reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */
- 0x0 0xff644000 0x0 0x200>; /* dsi_phy */
- interrupts = <0 3 1
- 0 56 1>;
- interrupt-names = "vsync","vsync2";
- pinctrl_version = <2>; /* for uboot */
-
- /* power type:
- * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending)
- * power index:
- * (point gpios_index, or extern_index,0xff=invalid)
- * power value:(0=output low, 1=output high, 2=input)
- * power delay:(unit in ms)
- */
- lcd_cpu-gpios = <&gpio GPIOZ_13 GPIO_ACTIVE_HIGH>;
- lcd_cpu_gpio_names = "GPIOZ_13";
-
- boe_fiti9364_7{
- model_name = "TV070WSM_FT9364";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 700 1053 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 95 163>; /*screen_widht, screen_height*/
- lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/
- 2 8 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 44226000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 400 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_always_hs(0=disable,1=enable)*/
- 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 0x04 3 /* check_reg, check_cnt */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <
- 0xff 5 /* delay 5ms */
- 0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <1>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 0 1 0 200
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 5 /* delay 5ms after mipi off */
- 0 0 0 20 /* reset low */
- 0 1 1 100 /* panel power off */
- 0xff 0 0 0>;
- backlight_index = <0>;
- };
-
- inx_fiti9364_7{
- model_name = "P070ACB_FT9364";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 770 1070 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 3 5>; /*screen_widht, screen_height*/
- lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/
- 6 20 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 49434000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 400 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_always_hs(0=disable,1=enable)*/
- 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 0x04 3 /* check_reg, check_cnt */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <
- 0xff 5 /* delay 5ms */
- 0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <2>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 0 1 0 200 /* panel power on */
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 5 /* delay 5ms after mipi off */
- 0 0 0 20 /* reset low */
- 0 1 1 100 /* panel power off */
- 0xff 0 0 0>;
- backlight_index = <0>;
- };
-
- kd_fiti9364_7{
- model_name = "KD070D82_FT9364";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 770 1070 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 3 5>; /*screen_widht, screen_height*/
- lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/
- 6 20 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 49434000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 400 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_always_hs(0=disable,1=enable)*/
- 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 0x04 3 /* check_reg, check_cnt */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <
- 0xff 5 /* delay 5ms */
- 0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <3>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 0 1 0 200 /* panel power on */
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 5 /* delay 5ms after mipi off */
- 0 0 0 20 /* reset low */
- 0 1 1 100 /* panel power off */
- 0xff 0 0 0>;
- backlight_index = <0>;
- };
-
- };
-
- lcd_extern{
- compatible = "amlogic, lcd_extern";
- dev_name = "lcd_extern";
- status = "okay";
- key_valid = <0>;
-
- extern_1{
- index = <1>;
- extern_name = "mipi_default"; // TV070WSM_FT9364
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- cmd_size = <0xff>;
- init_on = <
- 0x23 2 0xE0 0x00
- 0x23 2 0xE1 0x93
- 0x23 2 0xE2 0x65
- 0x23 2 0xE3 0xF8
- 0x23 2 0xE0 0x01
- 0x23 2 0x00 0x00
- 0x23 2 0x01 0x90
- 0x23 2 0x03 0x00
- 0x23 2 0x04 0x90
- 0x23 2 0x17 0x00
- 0x23 2 0x18 0xB0
- 0x23 2 0x19 0x01
- 0x23 2 0x1A 0x00
- 0x23 2 0x1B 0xB0
- 0x23 2 0x1C 0x01
- 0x23 2 0x1F 0x3E
- 0x23 2 0x20 0x2F
- 0x23 2 0x21 0x2F
- 0x23 2 0x22 0x0E
- 0x23 2 0x37 0x69
- 0x23 2 0x38 0x05
- 0x23 2 0x39 0x00
- 0x23 2 0x3A 0x01
- 0x23 2 0x3C 0x90
- 0x23 2 0x3D 0xFF
- 0x23 2 0x3E 0xFF
- 0x23 2 0x3F 0xFF
- 0x23 2 0x40 0x02
- 0x23 2 0x41 0x80
- 0x23 2 0x42 0x99
- 0x23 2 0x43 0x06
- 0x23 2 0x44 0x09
- 0x23 2 0x45 0x3C
- 0x23 2 0x4B 0x04
- 0x23 2 0x55 0x0D
- 0x23 2 0x56 0x01
- 0x23 2 0x57 0x89
- 0x23 2 0x58 0x0A
- 0x23 2 0x59 0x0A
- 0x23 2 0x5A 0x27
- 0x23 2 0x5B 0x15
- 0x23 2 0x5D 0x7C
- 0x23 2 0x5E 0x67
- 0x23 2 0x5F 0x58
- 0x23 2 0x60 0x4C
- 0x23 2 0x61 0x48
- 0x23 2 0x62 0x38
- 0x23 2 0x63 0x3C
- 0x23 2 0x64 0x24
- 0x23 2 0x65 0x3B
- 0x23 2 0x66 0x38
- 0x23 2 0x67 0x36
- 0x23 2 0x68 0x53
- 0x23 2 0x69 0x3F
- 0x23 2 0x6A 0x44
- 0x23 2 0x6B 0x35
- 0x23 2 0x6C 0x2E
- 0x23 2 0x6D 0x1F
- 0x23 2 0x6E 0x0C
- 0x23 2 0x6F 0x00
- 0x23 2 0x70 0x7C
- 0x23 2 0x71 0x67
- 0x23 2 0x72 0x58
- 0x23 2 0x73 0x4C
- 0x23 2 0x74 0x48
- 0x23 2 0x75 0x38
- 0x23 2 0x76 0x3C
- 0x23 2 0x77 0x24
- 0x23 2 0x78 0x3B
- 0x23 2 0x79 0x38
- 0x23 2 0x7A 0x36
- 0x23 2 0x7B 0x53
- 0x23 2 0x7C 0x3F
- 0x23 2 0x7D 0x44
- 0x23 2 0x7E 0x35
- 0x23 2 0x7F 0x2E
- 0x23 2 0x80 0x1F
- 0x23 2 0x81 0x0C
- 0x23 2 0x82 0x00
- 0x23 2 0xE0 0x02
- 0x23 2 0x00 0x45
- 0x23 2 0x01 0x45
- 0x23 2 0x02 0x47
- 0x23 2 0x03 0x47
- 0x23 2 0x04 0x41
- 0x23 2 0x05 0x41
- 0x23 2 0x06 0x1F
- 0x23 2 0x07 0x1F
- 0x23 2 0x08 0x1F
- 0x23 2 0x09 0x1F
- 0x23 2 0x0A 0x1F
- 0x23 2 0x0B 0x1F
- 0x23 2 0x0C 0x1F
- 0x23 2 0x0D 0x1D
- 0x23 2 0x0E 0x1D
- 0x23 2 0x0F 0x1D
- 0x23 2 0x10 0x1F
- 0x23 2 0x11 0x1F
- 0x23 2 0x12 0x1F
- 0x23 2 0x13 0x1F
- 0x23 2 0x14 0x1F
- 0x23 2 0x15 0x1F
- 0x23 2 0x16 0x44
- 0x23 2 0x17 0x44
- 0x23 2 0x18 0x46
- 0x23 2 0x19 0x46
- 0x23 2 0x1A 0x40
- 0x23 2 0x1B 0x40
- 0x23 2 0x1C 0x1F
- 0x23 2 0x1D 0x1F
- 0x23 2 0x1E 0x1F
- 0x23 2 0x1F 0x1F
- 0x23 2 0x20 0x1F
- 0x23 2 0x21 0x1F
- 0x23 2 0x22 0x1F
- 0x23 2 0x23 0x1D
- 0x23 2 0x24 0x1D
- 0x23 2 0x25 0x1D
- 0x23 2 0x26 0x1F
- 0x23 2 0x27 0x1F
- 0x23 2 0x28 0x1F
- 0x23 2 0x29 0x1F
- 0x23 2 0x2A 0x1F
- 0x23 2 0x2B 0x1F
- 0x23 2 0x58 0x40
- 0x23 2 0x59 0x00
- 0x23 2 0x5A 0x00
- 0x23 2 0x5B 0x10
- 0x23 2 0x5C 0x07
- 0x23 2 0x5D 0x20
- 0x23 2 0x5E 0x00
- 0x23 2 0x5F 0x00
- 0x23 2 0x61 0x00
- 0x23 2 0x62 0x00
- 0x23 2 0x63 0x7A
- 0x23 2 0x64 0x7A
- 0x23 2 0x65 0x00
- 0x23 2 0x66 0x00
- 0x23 2 0x67 0x32
- 0x23 2 0x68 0x08
- 0x23 2 0x69 0x7A
- 0x23 2 0x6A 0x7A
- 0x23 2 0x6B 0x00
- 0x23 2 0x6C 0x00
- 0x23 2 0x6D 0x00
- 0x23 2 0x6E 0x00
- 0x23 2 0x6F 0x89
- 0x23 2 0x70 0x00
- 0x23 2 0x71 0x00
- 0x23 2 0x72 0x06
- 0x23 2 0x73 0x7B
- 0x23 2 0x74 0x00
- 0x23 2 0x75 0x07
- 0x23 2 0x76 0x00
- 0x23 2 0x77 0x5D
- 0x23 2 0x78 0x17
- 0x23 2 0x79 0x1F
- 0x23 2 0x7A 0x00
- 0x23 2 0x7B 0x00
- 0x23 2 0x7C 0x00
- 0x23 2 0x7D 0x03
- 0x23 2 0x7E 0x7B
- 0x23 2 0xE0 0x03
- 0x23 2 0xAF 0x20
- 0x23 2 0xE0 0x04
- 0x23 2 0x09 0x11
- 0x23 2 0x0E 0x48
- 0x23 2 0x2B 0x2B
- 0x23 2 0x2E 0x44
- 0x23 2 0x41 0xFF
- 0x23 2 0xE0 0x00
- 0x23 2 0xE6 0x02
- 0x23 2 0xE7 0x0C
- 0x23 2 0x51 0xFF
- 0x23 2 0x53 0x2C
- 0x23 2 0x55 0x00
- 0x05 1 0x11
- 0xFF 125 /* Delay 125ms */
- 0x05 1 0x29
- 0xFF 0xFF /* Ending Flag */
- >;
- init_off = <
- 0xff 5
- 0x05 1 0x28 /* display off */
- 0xff 60 /* delay 60ms */
- 0x05 1 0x10 /* sleep in */
- 0xff 110 /* delay 110ms */
- 0xff 0xff>; /* ending */
- };
-
- extern_2{
- index = <2>;
- extern_name = "mipi_default"; // P070ACB_FT9364
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- cmd_size = <0xff>;
- init_on = <
- 0x23 2 0xE0 0x00 /* Page 0 */
- 0x23 2 0xE1 0x93 /* PASSWORD */
- 0x23 2 0xE2 0x65
- 0x23 2 0xE3 0xF8
- 0x23 2 0x80 0x03 /* DSI 4 lane */
- 0x23 2 0xE0 0x01 /* Page 01 */
- 0x23 2 0x0C 0x74 /* Set PWRIC */
- 0x23 2 0x17 0x00 /* Set Gamma Power */
- 0x23 2 0x18 0xEF /* VGMP=5.1V */
- 0x23 2 0x19 0x00 /* VGSP=0V */
- 0x23 2 0x1A 0x00
- 0x23 2 0x1B 0xEF /* VGMN=-5.1V */
- 0x23 2 0x1C 0x00 /* VGSN=0V */
- 0x23 2 0x1F 0x70 /* VGH_REG=16.2V */
- 0x23 2 0x20 0x2D /* VGL_REG=-12V */
- 0x23 2 0x21 0x2D /* VGL_REG2=-12V */
- 0x23 2 0x22 0x7E /* VGH_REG short to VGH VGL_REG short to VGL */
- 0x23 2 0x26 0xF3 /* VDDD from IOVCC/VCI */
- 0x23 2 0x37 0x09 /* SS=1 BGR=1 */
- 0x23 2 0x38 0x04 /* JDT=100 column inversion */
- 0x23 2 0x39 0x00 /* Source EQ Setting EQ1 */
- 0x23 2 0x3A 0x01 /* Source EQ Setting EQ2 */
- 0x23 2 0x3C 0x90 /* Source EQ Setting EQ3 */
- 0x23 2 0x3D 0xFF /* SET Source OP on time */
- 0x23 2 0x3E 0xFF /* SET Source OP off time */
- 0x23 2 0x3F 0xFF /* SET Source OP off time */
- 0x23 2 0x40 0x02 /* RSO=640 RGB */
- 0x23 2 0x41 0x80 /* LN=512->1024 line */
- 0x23 2 0x42 0x99 /* SLT internal line period */
- 0x23 2 0x43 0x14 /* VFP */
- 0x23 2 0x44 0x19 /* VBP */
- 0x23 2 0x45 0x5A /* HBP */
- 0x23 2 0x4B 0x04
- 0x23 2 0x55 0x02 /* DCDCM=0010 FP7721BX2 */
- 0x23 2 0x56 0x01 /* No auto Ratio function */
- 0x23 2 0x57 0x69 /* VGH_RT=3'b011 2*AVDD-AVEE VGL_RT=3'b010=AVEE+VCL-AVDD VCL_RT=2'b00 0.5*VCIP */
- 0x23 2 0x58 0x0A /* AVDD_S */
- 0x23 2 0x59 0x0A /* VCL = -2.5V */
- 0x23 2 0x5A 0x2E /* VGH = 16.2V */
- 0x23 2 0x5B 0x19 /* VGL = -12V */
- 0x23 2 0x5C 0x15 /* pump clk */
- 0x23 2 0x5D 0x71 /* V255 positive voltage from 4.888V to 4.888V */
- 0x23 2 0x5E 0x65 /* V251 positive voltage from 4.533V to 4.718V */
- 0x23 2 0x5F 0x55 /* V247 positive voltage from 4.349V to 4.491V */
- 0x23 2 0x60 0x49 /* V243 positive voltage from 4.179V to 4.321V */
- 0x23 2 0x61 0x46 /* V235 positive voltage from 3.910V to 4.052V */
- 0x23 2 0x62 0x38 /* V227 positive voltage from 3.726V to 3.853V */
- 0x23 2 0x63 0x3D /* V211 positive voltage from 3.428V to 3.528V */
- 0x23 2 0x64 0x29 /* V191 positive voltage from 3.159V to 3.244V */
- 0x23 2 0x65 0x43 /* V159 positive voltage from 2.805V to 2.876V */
- 0x23 2 0x66 0x42 /* V128 positive voltage from 2.522V to 2.578V */
- 0x23 2 0x67 0x44 /* V96 positive voltage from 2.267V to 2.323V */
- 0x23 2 0x68 0x63 /* V64 positive voltage from 1.941V to 2.026V */
- 0x23 2 0x69 0x53 /* V44 positive voltage from 1.686V to 1.799V */
- 0x23 2 0x6A 0x5B /* V28 positive voltage from 1.431V to 1.516V */
- 0x23 2 0x6B 0x4E /* V20 positive voltage from 1.275V to 1.322V */
- 0x23 2 0x6C 0x4C /* V12 positive voltage from 1.077V to 1.077V */
- 0x23 2 0x6D 0x41 /* V8 positive voltage from 0.949V to 0.921V */
- 0x23 2 0x6E 0x2D /* V4 positive voltage from 0.723V to 0.638V */
- 0x23 2 0x6F 0x23 /* V0 positive voltage from 0.496V to 0.496V */
- 0x23 2 0x70 0x71 /* V255 negative voltage from -4.888V to -4.888V */
- 0x23 2 0x71 0x4C /* V251 negative voltage from -4.179V to -4.363V */
- 0x23 2 0x72 0x3B /* V247 negative voltage from -3.995V to -4.123V */
- 0x23 2 0x73 0x30 /* V243 negative voltage from -3.825V to -3.967V */
- 0x23 2 0x74 0x2D /* V233 negative voltage from -3.556V to -3.698V */
- 0x23 2 0x75 0x1F /* V227 negative voltage from -3.372V to -3.499V */
- 0x23 2 0x76 0x25 /* V211 negative voltage from -3.088V to -3.188V */
- 0x23 2 0x77 0x10 /* V191 negative voltage from -2.805V to -2.890V */
- 0x23 2 0x78 0x2A /* V159 negative voltage from -2.451V to -2.522V */
- 0x23 2 0x79 0x2A /* V128 negative voltage from -2.182V to -2.238V */
- 0x23 2 0x7A 0x2B /* V96 negative voltage from -1.913V to -1.969V */
- 0x23 2 0x7B 0x4A /* V64 negative voltage from -1.587V to -1.672V */
- 0x23 2 0x7C 0x3A /* V44 negative voltage from -1.332V to -1.445V */
- 0x23 2 0x7D 0x43 /* V28 negative voltage from -1.091V to -1.176V */
- 0x23 2 0x7E 0x36 /* V20 negative voltage from -0.935V to -0.992V */
- 0x23 2 0x7F 0x33 /* V12 negative voltage from -0.723V to -0.723V */
- 0x23 2 0x80 0x28 /* V8 negative voltage from -0.595V to -0.567V */
- 0x23 2 0x81 0x14 /* V4 negative voltage from -0.368V to -0.283V */
- 0x23 2 0x82 0x0B /* V0 negative voltage from -0.156V to -0.156V */
- 0x23 2 0xE0 0x02 /* Page2 */
- 0x23 2 0x00 0x53 /* GIP_L Pin mapping RESET_EVEN */
- 0x23 2 0x01 0x55 /* VSSG_EVEN */
- 0x23 2 0x02 0x55 /* VSSA_EVEN */
- 0x23 2 0x03 0x51 /* STV2_EVEN */
- 0x23 2 0x04 0x77 /* VDD2_EVEN */
- 0x23 2 0x05 0x57 /* VDD1_EVEN */
- 0x23 2 0x06 0x1F /* VGL */
- 0x23 2 0x07 0x4F /* CK12 */
- 0x23 2 0x08 0x4D /* CK10 */
- 0x23 2 0x09 0x1F /* VGL */
- 0x23 2 0x0A 0x4B /* CK8 */
- 0x23 2 0x0B 0x49 /* CK6 */
- 0x23 2 0x0C 0x1F /* VGL */
- 0x23 2 0x0D 0x47 /* CK4 */
- 0x23 2 0x0E 0x45 /* CK2 */
- 0x23 2 0x0F 0x41 /* STV1_EVEN */
- 0x23 2 0x10 0x1F /* VGL */
- 0x23 2 0x11 0x1F /* VGL */
- 0x23 2 0x12 0x1F /* VGL */
- 0x23 2 0x13 0x55 /* VGG */
- 0x23 2 0x14 0x1F /* VGL */
- 0x23 2 0x15 0x1F /* VGL */
- 0x23 2 0x16 0x52 /* GIP_R Pin mapping RESET_ODD */
- 0x23 2 0x17 0x55 /* VSSG_ODD */
- 0x23 2 0x18 0x55 /* VSSA_ODD */
- 0x23 2 0x19 0x50 /* STV2_ODD */
- 0x23 2 0x1A 0x77 /* VDD2_ODD */
- 0x23 2 0x1B 0x57 /* VDD1_ODD */
- 0x23 2 0x1C 0x1F /* VGL */
- 0x23 2 0x1D 0x4E /* CK11 */
- 0x23 2 0x1E 0x4C /* CK9 */
- 0x23 2 0x1F 0x1F /* VGL */
- 0x23 2 0x20 0x4A /* CK7 */
- 0x23 2 0x21 0x48 /* CK5 */
- 0x23 2 0x22 0x1F /* VGL */
- 0x23 2 0x23 0x46 /* CK3 */
- 0x23 2 0x24 0x44 /* CK1 */
- 0x23 2 0x25 0x40 /* STV1_ODD */
- 0x23 2 0x26 0x1F /* VGL */
- 0x23 2 0x27 0x1F /* VGL */
- 0x23 2 0x28 0x1F /* VGL */
- 0x23 2 0x29 0x1F /* VGL */
- 0x23 2 0x2A 0x1F /* VGL */
- 0x23 2 0x2B 0x55 /* VGG */
- 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping RESET_EVEN */
- 0x23 2 0x2D 0x15 /* VSSG_EVEN */
- 0x23 2 0x2E 0x15 /* VSSA_EVEN */
- 0x23 2 0x2F 0x00 /* STV2_EVEN */
- 0x23 2 0x30 0x17 /* VDD2_EVEN */
- 0x23 2 0x31 0x17 /* VDD1_EVEN */
- 0x23 2 0x32 0x1F /* VGL */
- 0x23 2 0x33 0x08 /* CK12 */
- 0x23 2 0x34 0x0A /* CK10 */
- 0x23 2 0x35 0x1F /* VGL */
- 0x23 2 0x36 0x0C /* CK8 */
- 0x23 2 0x37 0x0E /* CK6 */
- 0x23 2 0x38 0x1F /* VGL */
- 0x23 2 0x39 0x04 /* CK4 */
- 0x23 2 0x3A 0x06 /* CK2 */
- 0x23 2 0x3B 0x10 /* STV1_EVEN */
- 0x23 2 0x3C 0x1F /* VGL */
- 0x23 2 0x3D 0x1F /* VGL */
- 0x23 2 0x3E 0x1F /* VGL */
- 0x23 2 0x3F 0x15 /* VGG */
- 0x23 2 0x40 0x1F /* VGL */
- 0x23 2 0x41 0x1F /* VGL */
- 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping RESET_ODD */
- 0x23 2 0x43 0x15 /* VSSG_ODD */
- 0x23 2 0x44 0x15 /* VSSA_ODD */
- 0x23 2 0x45 0x01 /* STV2_ODD */
- 0x23 2 0x46 0x37 /* VDD2_ODD */
- 0x23 2 0x47 0x17 /* VDD1_ODD */
- 0x23 2 0x48 0x1F /* VGL */
- 0x23 2 0x49 0x09 /* CK11 */
- 0x23 2 0x4A 0x0B /* CK9 */
- 0x23 2 0x4B 0x1F /* VGL */
- 0x23 2 0x4C 0x0D /* CK7 */
- 0x23 2 0x4D 0x0F /* CK5 */
- 0x23 2 0x4E 0x1F /* VGL */
- 0x23 2 0x4F 0x05 /* CK3 */
- 0x23 2 0x50 0x07 /* CK1 */
- 0x23 2 0x51 0x11 /* STV1_ODD */
- 0x23 2 0x52 0x1F /* VGL */
- 0x23 2 0x53 0x1F /* VGL */
- 0x23 2 0x54 0x1F /* VGL */
- 0x23 2 0x55 0x1F /* VGL */
- 0x23 2 0x56 0x1F /* VGL */
- 0x23 2 0x57 0x15 /* VGG */
- 0x23 2 0x58 0x40 /* GAS OPT=1 for abnormal power off */
- 0x23 2 0x59 0x00 /* INIT_W */
- 0x23 2 0x5A 0x00 /* INIT[7:0] */
- 0x23 2 0x5B 0x10 /* STV_NUM STV_S0[10:8] */
- 0x23 2 0x5C 0x14 /* STV_S0[7:0] */
- 0x23 2 0x5D 0x40 /* STV_W STV_S1 */
- 0x23 2 0x5E 0x01 /* STV_S2 */
- 0x23 2 0x5F 0x02 /* STV_S3 */
- 0x23 2 0x60 0x40 /* ETV_W ETV_S1 */
- 0x23 2 0x61 0x03 /* ETV_S2 */
- 0x23 2 0x62 0x04 /* ETV_S3 */
- 0x23 2 0x63 0x7A /* SETV_ON for STV/ETV on time */
- 0x23 2 0x64 0x7A /* SETV_OFF for STV/ETV off time */
- 0x23 2 0x65 0x74 /* ETV_EN ETV_NUM ETV_S0 */
- 0x23 2 0x66 0x16 /* ETV_S0 */
- 0x23 2 0x67 0xB4 /* CKV0_NUM CKV0_W */
- 0x23 2 0x68 0x16 /* CKV0_S0 */
- 0x23 2 0x69 0x7A /* CKV0_on */
- 0x23 2 0x6A 0x7A /* CKV0_off time */
- 0x23 2 0x6B 0x0C /* CKV0_DUM */
- 0x23 2 0x6C 0x00 /* GIP Line EQ option */
- 0x23 2 0x6D 0x04 /* GIP rising EQ */
- 0x23 2 0x6E 0x04 /* GIP fallig EQ */
- 0x23 2 0x6F 0x88 /* GIP_DR CKV0_CON CKV1_CON */
- 0x23 2 0x70 0x00 /* CKV1_NUM CKV0_W */
- 0x23 2 0x71 0x00 /* CKV1_S0 */
- 0x23 2 0x72 0x06 /* CKV1_on */
- 0x23 2 0x73 0x7B /* CKV1_off time */
- 0x23 2 0x74 0x00 /* CKV1_DUM */
- 0x23 2 0x75 0xBC /* FLM_EN FLM_W */
- 0x23 2 0x76 0x00 /* FLM on time */
- 0x23 2 0x77 0x04 /* VEN_EN VEN_W FLM_NUM FLM_OFF */
- 0x23 2 0x78 0x2C /* FLM_OFF */
- 0x23 2 0x79 0x00 /* VEN_W */
- 0x23 2 0x7A 0x00 /* VEN_S0 */
- 0x23 2 0x7B 0x00 /* VEN_S1 */
- 0x23 2 0x7C 0x00 /* VEN_DUM */
- 0x23 2 0x7D 0x03 /* VEN on time */
- 0x23 2 0x7E 0x7B /* VEN off time */
- 0x23 2 0xE0 0x03 /* Page3 */
- 0x23 2 0xAF 0x20 /* Set CABC */
- 0x23 2 0xE0 0x04 /* Page4 */
- 0x23 2 0x09 0x11 /* Source level at blanking period */
- 0x23 2 0x0E 0x48 /* Source EQ option */
- 0x23 2 0x2B 0x2B /* ESD Protect */
- 0x23 2 0x2E 0x44 /* Special Packet disable */
- 0x23 2 0x41 0xFF /* Set CABC */
- 0x23 2 0xE0 0x00 /* Page0 */
- 0x23 2 0xE6 0x02 /* Enable Watch Dog */
- 0x23 2 0xE7 0x0C /* Watch Dog timer setting */
- 0x23 2 0x51 0xFF /* CABC Option 0x80=50% duty 0xFF=100% */
- 0x23 2 0x53 0x2C
- 0x23 2 0x55 0x00
- 0x05 1 0x11 /* Sleep Out */
- 0xFF 125 /* Delay 125ms */
- 0x05 1 0x29 /* Display On */
- 0xFF 0xFF /* Ending */
- >;
- init_off = <
- 0xff 5
- 0x05 1 0x28 /* display off */
- 0xff 60 /* delay 60ms */
- 0x05 1 0x10 /* sleep in */
- 0xff 110 /* delay 110ms */
- 0xff 0xff>; /* ending */
- };
-
- extern_3{
- index = <3>;
- extern_name = "mipi_default"; // KD070D82_FT9364
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- cmd_size = <0xff>;
- init_on = <
- 0x23 2 0xE0 0x00 /* Register setting change to Page 0 */
- 0x23 2 0xE1 0x93 /* PASSWORD, setting as 93-65-F8 to enable page1-4 command access */
- 0x23 2 0xE2 0x65
- 0x23 2 0xE3 0xF8
- 0x23 2 0x80 0x03 /* Setting DSI lane number, 0x03 is DSI 4 lane */
- 0x23 2 0xE0 0x01 /* Register setting change to Page 1 */
- 0x23 2 0x00 0x00 /* Set VCOM_Forward */
- 0x23 2 0x01 0x9E /* VCOM=0x09F */
- 0x23 2 0x03 0x00 /* Set VCOM_Reverse */
- 0x23 2 0x04 0xAA /* VCOMR=0x0AA, -1.40V */
- 0x23 2 0x0C 0x74 /* Set PWRIC pumping frequency,=8 HCLK, about 512KHz */
- 0x23 2 0x17 0x00 /* Set Gamma Power, VGMP[8]=0, VGSP[8]=0 */
- 0x23 2 0x18 0xEF /* VGMP[8:0]=0x0EF=5.1V */
- 0x23 2 0x19 0x00 /* VGSP[8:0]=0x000=0V */
- 0x23 2 0x1A 0x00 /* VGMN[8]=0, VGSN[8]=0 */
- 0x23 2 0x1B 0xEF /* VGMN[8:0]=0x0EF=-5.1V */
- 0x23 2 0x1C 0x00 /* VGSN[8:0]=0x000=0V */
- 0x23 2 0x1F 0x70 /* VGH_REG=16.2V */
- 0x23 2 0x20 0x2D /* VGL_REG=-12V */
- 0x23 2 0x21 0x2D /* VGL_REG2=-12V */
- 0x23 2 0x22 0x7E /* VGH_REG short to VGH, VGL_REG short to VGL, */
- 0x23 2 0x26 0xF3 /* VDDD from IOVCC&VCI */
- 0x23 2 0x37 0x09 /* SS=1, source scan from S2400 to S1;BGR=1 CF type is (S1,S2,S3) align to (B,G,R) */
- 0x23 2 0x38 0x04 /* JDT=100, display inversion type is column inversion */
- 0x23 2 0x39 0x00 /* Source EQ Setting, EQ1, 0x00=0us */
- 0x23 2 0x3A 0x01 /* Source EQ Setting, EQ2, 0x01 =0.1us */
- 0x23 2 0x3C 0x90 /* Source EQ Setting, EQ3, EQ3 start at 14.4us */
- 0x23 2 0x3D 0xFF /* SET Source OP on time, 0xFF means source op always on */
- 0x23 2 0x3E 0xFF /* SET Source OP off time, 0xFF means source op always on */
- 0x23 2 0x3F 0xFF /* SET Source OP off time, 0xFF means source op always on */
- 0x23 2 0x40 0x02 /* horizontal resolution setting,RSO[2:0]= 0x02 =600RGB, LN[1:0]=2'b00 */
- 0x23 2 0x41 0x80 /* LN[9:0]=0x200=512, vertical resolution is 512*2=1024 line */
- 0x23 2 0x42 0x99 /* SLT, internal line period=0x99->15.3us */
- 0x23 2 0x43 0x14 /* Internal VFP=Ext_VFP=20(0x14) */
- 0x23 2 0x44 0x19 /* Internal _VBP=Ext_VS+Ext_VBP-1=6+20-1=25(0x19) */
- 0x23 2 0x45 0x5A /* Internal_HBP=Ext_HS+Ext_HBP=90(0x5A) */
- 0x23 2 0x55 0x02 /* Seting PWRIC mode, DCDCM=0010-> FP7721BX2 */
- 0x23 2 0x56 0x01 /* No auto Ratio function */
- 0x23 2 0x57 0x69 /* VGH_RT=3'b011,2*AVDD-AVEE,VGL_RT=3'b010=AVEE+VCL-AVDD,VCL_RT=2'b00,0.5*VCIP */
- 0x23 2 0x58 0x0A /* AVDD_S, not use internal AVDD in this model */
- 0x23 2 0x59 0x0A /* VCL = -2.5V */
- 0x23 2 0x5A 0x2E /* VGH = 16.2V */
- 0x23 2 0x5B 0x19 /* VGL = -12V */
- 0x23 2 0x5C 0x15 /* pump clk, VCL_CLK[1:0]=2'b01=HCLK/2=32KHz, VGHVGL_CLK[1:0]=2'b01=HCLK/2=32KHz */
- 0x23 2 0x5D 0x77 /* Gamma voltage setting, VP255-4.793V */
- 0x23 2 0x5E 0x5C /* VP251 */
- 0x23 2 0x5F 0x4D /* VP247 */
- 0x23 2 0x60 0x40 /* VP243 */
- 0x23 2 0x61 0x3D /* VP235 */
- 0x23 2 0x62 0x2F /* VP227 */
- 0x23 2 0x63 0x34 /* VP211 */
- 0x23 2 0x64 0x1F /* VP191 */
- 0x23 2 0x65 0x38 /* VP159 */
- 0x23 2 0x66 0x38 /* VP128 */
- 0x23 2 0x67 0x39 /* VP96 */
- 0x23 2 0x68 0x58 /* VP64 */
- 0x23 2 0x69 0x48 /* VP44 */
- 0x23 2 0x6A 0x51 /* VP28 */
- 0x23 2 0x6B 0x44 /* VP20 */
- 0x23 2 0x6C 0x41 /* VP12 */
- 0x23 2 0x6D 0x35 /* VP8 */
- 0x23 2 0x6E 0x24 /* VP4 */
- 0x23 2 0x6F 0x02 /* VP0 */
- 0x23 2 0x70 0x77 /* VN255 */
- 0x23 2 0x71 0x5C /* VN251 */
- 0x23 2 0x72 0x4D /* VN247 */
- 0x23 2 0x73 0x40 /* VN243 */
- 0x23 2 0x74 0x3D /* VN235 */
- 0x23 2 0x75 0x2F /* VN227 */
- 0x23 2 0x76 0x34 /* VN211 */
- 0x23 2 0x77 0x1F /* VN191 */
- 0x23 2 0x78 0x38 /* VN159 */
- 0x23 2 0x79 0x38 /* VN128 */
- 0x23 2 0x7A 0x39 /* VN96 */
- 0x23 2 0x7B 0x58 /* VN64 */
- 0x23 2 0x7C 0x48 /* VN44 */
- 0x23 2 0x7D 0x51 /* VN28 */
- 0x23 2 0x7E 0x44 /* VN20 */
- 0x23 2 0x7F 0x41 /* VN12 */
- 0x23 2 0x80 0x35 /* VN8 */
- 0x23 2 0x81 0x24 /* VN4 */
- 0x23 2 0x82 0x02 /* VN0 */
- 0x23 2 0xE0 0x02 /* Register setting change to Page 2 */
- 0x23 2 0x00 0x53 /* GIP_L_Forward scan mapping, assign as RESET_EVEN */
- 0x23 2 0x01 0x55 /* assign as VSSG_EVEN */
- 0x23 2 0x02 0x55 /* assign as VSSA_EVEN */
- 0x23 2 0x03 0x51 /* assign as STV2_EVEN */
- 0x23 2 0x04 0x77 /* assign as VDD2_EVEN */
- 0x23 2 0x05 0x57 /* assign as VDD1_EVEN */
- 0x23 2 0x06 0x1F /* assign as VGL */
- 0x23 2 0x07 0x4F /* assign as CK12 */
- 0x23 2 0x08 0x4D /* assign as CK10 */
- 0x23 2 0x09 0x1F /* assign as VGL */
- 0x23 2 0x0A 0x4B /* assign as CK8 */
- 0x23 2 0x0B 0x49 /* assign as CK6 */
- 0x23 2 0x0C 0x1F /* assign as VGL */
- 0x23 2 0x0D 0x47 /* assign as CK4 */
- 0x23 2 0x0E 0x45 /* assign as CK2 */
- 0x23 2 0x0F 0x41 /* assign as STV1_EVEN */
- 0x23 2 0x10 0x1F /* assign as VGL */
- 0x23 2 0x11 0x1F /* assign as VGL */
- 0x23 2 0x12 0x1F /* assign as VGL */
- 0x23 2 0x13 0x55 /* assign as VGG */
- 0x23 2 0x14 0x1F /* assign as VGL */
- 0x23 2 0x15 0x1F /* assign as VGL */
- 0x23 2 0x16 0x52 /* GIP_R_Forward scan mapping, assign as RESET_ODD */
- 0x23 2 0x17 0x55 /* assign as VSSG_ODD */
- 0x23 2 0x18 0x55 /* assign as VSSA_ODD */
- 0x23 2 0x19 0x50 /* assign as STV2_ODD */
- 0x23 2 0x1A 0x77 /* assign as VDD2_ODD */
- 0x23 2 0x1B 0x57 /* assign as VDD1_ODD */
- 0x23 2 0x1C 0x1F /* assign as VGL */
- 0x23 2 0x1D 0x4E /* assign as CK11 */
- 0x23 2 0x1E 0x4C /* assign as CK9 */
- 0x23 2 0x1F 0x1F /* assign as VGL */
- 0x23 2 0x20 0x4A /* assign as CK7 */
- 0x23 2 0x21 0x48 /* assign as CK5 */
- 0x23 2 0x22 0x1F /* assign as VGL */
- 0x23 2 0x23 0x46 /* assign as CK3 */
- 0x23 2 0x24 0x44 /* assign as CK1 */
- 0x23 2 0x25 0x40 /* assign as STV1_ODD */
- 0x23 2 0x26 0x1F /* assign as VGL */
- 0x23 2 0x27 0x1F /* assign as VGL */
- 0x23 2 0x28 0x1F /* assign as VGL */
- 0x23 2 0x29 0x1F /* assign as VGL */
- 0x23 2 0x2A 0x1F /* assign as VGL */
- 0x23 2 0x2B 0x55 /* assign as VGG */
- 0x23 2 0x2C 0x12 /* GIP_L_Reverse Scan mapping, assign as RESET_EVEN */
- 0x23 2 0x2D 0x15 /* assign as VSSG_EVEN */
- 0x23 2 0x2E 0x15 /* assign as VSSA_EVEN */
- 0x23 2 0x2F 0x00 /* assign as STV2_EVEN */
- 0x23 2 0x30 0x17 /* assign as VDD2_EVEN */
- 0x23 2 0x31 0x17 /* assign as VDD1_EVEN */
- 0x23 2 0x32 0x1F /* assign as VGL */
- 0x23 2 0x33 0x08 /* assign as CK12 */
- 0x23 2 0x34 0x0A /* assign as CK10 */
- 0x23 2 0x35 0x1F /* assign as VGL */
- 0x23 2 0x36 0x0C /* assign as CK8 */
- 0x23 2 0x37 0x0E /* assign as CK6 */
- 0x23 2 0x38 0x1F /* assign as VGL */
- 0x23 2 0x39 0x04 /* assign as CK4 */
- 0x23 2 0x3A 0x06 /* assign as CK2 */
- 0x23 2 0x3B 0x10 /* assign as STV1_EVEN */
- 0x23 2 0x3C 0x1F /* assign as VGL */
- 0x23 2 0x3D 0x1F /* assign as VGL */
- 0x23 2 0x3E 0x1F /* assign as VGL */
- 0x23 2 0x3F 0x15 /* assign as VGG */
- 0x23 2 0x40 0x1F /* assign as VGL */
- 0x23 2 0x41 0x1F /* assign as VGL */
- 0x23 2 0x42 0x13 /* GIP_R_Reverse Scan mapping, assign as RESET_ODD */
- 0x23 2 0x43 0x15 /* assign as VSSG_ODD */
- 0x23 2 0x44 0x15 /* assign as VSSA_ODD */
- 0x23 2 0x45 0x01 /* assign as STV2_ODD */
- 0x23 2 0x46 0x17 /* assign as VDD2_ODD */
- 0x23 2 0x47 0x17 /* assign as VDD1_ODD */
- 0x23 2 0x48 0x1F /* assign as VGL */
- 0x23 2 0x49 0x09 /* assign as CK11 */
- 0x23 2 0x4A 0x0B /* assign as CK9 */
- 0x23 2 0x4B 0x1F /* assign as VGL */
- 0x23 2 0x4C 0x0D /* assign as CK7 */
- 0x23 2 0x4D 0x0F /* assign as CK5 */
- 0x23 2 0x4E 0x1F /* assign as VGL */
- 0x23 2 0x4F 0x05 /* assign as CK3 */
- 0x23 2 0x50 0x07 /* assign as CK1 */
- 0x23 2 0x51 0x11 /* assign as STV1_ODD */
- 0x23 2 0x52 0x1F /* assign as VGL */
- 0x23 2 0x53 0x1F /* assign as VGL */
- 0x23 2 0x54 0x1F /* assign as VGL */
- 0x23 2 0x55 0x1F /* assign as VGL */
- 0x23 2 0x56 0x1F /* assign as VGL */
- 0x23 2 0x57 0x15 /* assign as VGG */
- 0x23 2 0x58 0x40 /* GAS OPT=1, When abnormal power off, GIP will pull to VGH */
- 0x23 2 0x59 0x00 /* INIT_W=0, no INIT function in this panel */
- 0x23 2 0x5A 0x00 /* INIT[10:0], no INIT function in this panel */
- 0x23 2 0x5B 0x10 /* STV_NUM,STV_S0[10:8], 2 STV pulses */
- 0x23 2 0x5C 0x14 /* STV_S0[7:0], STV start from 21th hsync after vsync */
- 0x23 2 0x5D 0x40 /* STV_W=4, STV width is 4 Hline; STV1 delay 1 hline with STV0 */
- 0x23 2 0x5E 0x01 /* STV_S2, STV2 delay 2 hline with STV0 */
- 0x23 2 0x5F 0x02 /* STV_S3, STV3 delay 3 hline with STV0 */
- 0x23 2 0x60 0x40 /* ETV_W=4, ETV witdh is 4 hline; ETV1 delay 1 hilne from ETV0 */
- 0x23 2 0x61 0x03 /* ETV_S2, ETV2 delay 4 hline with ETV0 */
- 0x23 2 0x62 0x04 /* ETV_S3, ETV3 delay 5 hline with ETV0 */
- 0x23 2 0x63 0x7A /* SETV_ON for STV/ETV on time, rising at 12.2us after hsync */
- 0x23 2 0x64 0x7A /* SETV_OFF for STV/ETV off time , falling at 12.2us after hsync */
- 0x23 2 0x65 0x74 /* ETV_EN=1, enable ETV function; ETV_NUM=3, using 4 ETV pulse, */
- 0x23 2 0x66 0x16 /* ETV_S0=0x416, EVT start at 1046th hsync fater vaync */
- 0x23 2 0x67 0xB4 /* CKV_NUM=2'b1011, using 12 CKV pulse; CKV0_W=4. CKV width is 4 hline */
- 0x23 2 0x68 0x16 /* CKV0_S0 , CKV start from 23th hsync after vsync */
- 0x23 2 0x69 0x7A /* CKV0_on ,for CKV on time, rising at 12.2us after hsync */
- 0x23 2 0x6A 0x7A /* CKV0_off ,for CKV off time, falling at 12.2us after hsync */
- 0x23 2 0x6B 0x0C /* CKV0_DUM, total CKV pulse number=1024+12=1036 */
- 0x23 2 0x6C 0x00 /* GIP Line EQ option , disable GEQ_Line function */
- 0x23 2 0x6D 0x04 /* GIP rising EQ, period is 0.4us */
- 0x23 2 0x6E 0x04 /* GIP fallig EQ, period is 0.4us */
- 0x23 2 0x6F 0x88 /* GIP_DR; CKV0_CON, no continuous CKV0; CKV1_CON, no continuous CKV1 */
- 0x23 2 0x70 0x00 /* CKV1_NUM, CKV0_W , no CKV group 1 function in this panel, don't care */
- 0x23 2 0x71 0x00 /* CKV1_S0, no CKV group 1 function in this panel, don't care */
- 0x23 2 0x72 0x06 /* CKV1_on , no CKV group 1 function in this panel, don't care */
- 0x23 2 0x73 0x7B /* CKV1_off time, no CKV group 1 function in this panel, don't care */
- 0x23 2 0x74 0x00 /* CKV1_DUM, no CKV group 1 function in this panel, don't care */
- 0x23 2 0x75 0xBC /* FLM_EN, enable FLM function; FLM_W=0x3C, FLM toggle period is 60 frame */
- 0x23 2 0x76 0x00 /* FLM on time , FLM on(rising) at 1st hsync after vsync */
- 0x23 2 0x77 0x04 /* VEN_EN, VEN_W, no VEN function in this panel, don't care */
- 0x23 2 0x78 0x2C /* FLM_OFF, FLM off(falling) at 1068th hsync after vsync */
- 0x23 2 0x79 0x00 /* VEN_W , no VEN function in this panel, don't care */
- 0x23 2 0x7A 0x00 /* VEN_S0 , no VEN function in this panel, don't care */
- 0x23 2 0x7B 0x00 /* VEN_S1 , no VEN function in this panel, don't care */
- 0x23 2 0x7C 0x00 /* VEN_DUM , no VEN function in this panel, don't care */
- 0x23 2 0x7D 0x03 /* VEN on time , no VEN function in this panel, don't care */
- 0x23 2 0x7E 0x7B /* VEN off time , no VEN function in this panel, don't care */
- 0x23 2 0xE0 0x03 /* Register setting change to Page 3 */
- 0x23 2 0xAF 0x20 /* Set CABC, disable CABC TP detect, for CABC pattern change more smooth */
- 0x23 2 0xE0 0x04 /* Register setting change to Page 4 */
- 0x23 2 0x09 0x11 /* Source level at blanking period, sweeping V0 level */
- 0x23 2 0x0E 0x48 /* Source EQ option, EQ to PCAP,NCAP */
- 0x23 2 0x2B 0x2B /* ESD Protect, clock lane op behavior follow data lane, improve ESD performance */
- 0x23 2 0x2E 0x44 /* ESD protect, disable special packet */
- 0x23 2 0x41 0xFF /* Set CABC, for CABC pattern change more smooth */
- 0x23 2 0xE0 0x00 /* Register setting change to Page 0 */
- 0x23 2 0xE6 0x02 /* Enable Watch Dog */
- 0x23 2 0xE7 0x0C /* Watch Dog timer setting, WD alarm time is 12*512osc after hsync stop */
- 0x23 2 0x51 0xFF /* CABC Option, 0x80=50% duty, 0xFF=100% */
- 0x23 2 0x53 0x2C /* enable dimming, BCTRL, BL */
- 0x23 2 0x55 0x00 /* CABC mode, 0x00 is manual mode */
- 0x05 1 0x11 /* SLPOUT */
- 0xFF 125 /* Delay 125ms */
- 0x05 1 0x29 /* Display On */
- 0xFF 0xFF /* Ending */
- >;
- init_off = <
- 0xff 5
- 0x05 1 0x28 /* display off */
- 0xff 60 /* delay 60ms */
- 0x05 1 0x10 /* sleep in */
- 0xff 110 /* delay 110ms */
- 0xff 0xff>; /* ending */
- };
- };
-
- backlight{
- compatible = "amlogic, backlight-g12a";
- status = "okay";
- key_valid = <0>;
- pinctrl-names = "pwm_on","pwm_off";
- pinctrl-0 = <&pwm_f_pins2>;
- pinctrl-1 = <&bl_pwm_off_pins>;
- pinctrl_version = <2>; /* for uboot */
- bl_pwm_config = <&bl_pwm_conf>;
- bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH
- &gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
- bl_gpio_names = "GPIOH_4","GPIOH_5";
-
- /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/
- /* power index:(point gpios_index, 0xff=invalid)
- * power value:(0=output low, 1=output high, 2=input)
- * power delay:(unit in ms)
- */
-
- backlight_0{
- index = <0>;
- bl_name = "backlight_pwm";
- bl_level_default_uboot_kernel = <100 100>;
- bl_level_attr = <255 10 /*max, min*/
- 128 128>; /*mid, mid_mapping*/
- bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */
- bl_power_attr = <0 /*en_gpio_index*/
- 1 0 /*on_value, off_value*/
- 200 200>; /*on_delay(ms), off_delay(ms)*/
- bl_pwm_port = "PWM_F";
- bl_pwm_attr = <0 /*pwm_method*/
- 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/
- 100 25>; /*duty_max(%), duty_min(%)*/
- bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/
- 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/
- bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */
- };
- backlight_1{
- index = <1>;
- bl_name = "bl_extern";
- bl_level_default_uboot_kernel = <100 100>;
- bl_level_attr = <255 10 /*max, min*/
- 128 128>; /*mid, mid_mapping*/
- bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/
- bl_power_attr = <1 /*en_gpio_index*/
- 1 0 /*on_value, off_value*/
- 200 200>; /*on_delay(ms), off_delay(ms)*/
- bl_extern_index = <0>;
- };
- };
- bl_pwm_conf:bl_pwm_conf{
- pwm_channel_0 {
- pwm_port_index = <5>;
- pwms = <&pwm_ef MESON_PWM_1 30040 0>;
- };
- };
-
- bl_extern{
- compatible = "amlogic, bl_extern";
- status = "disabled";
- i2c_bus = "i2c_bus_3";
-
- extern_0{
- index = <0>;
- extern_name = "i2c_lp8556";
- type = <0>; /*0=i2c, 1=spi, 2=mipi*/
- i2c_address = <0x2c>; /*7bit i2c address*/
- dim_max_min = <255 10>;
- };
-
- extern_1{
- index = <1>;
- extern_name = "mipi_lt070me05";
- type = <2>; /*0=i2c, 1=spi, 2=mipi*/
- dim_max_min = <255 10>;
- };
- };
-};/* end of panel */
diff --git a/arch/arm/dts/elaine-bx-panel.dtsi b/arch/arm/dts/elaine-bx-panel.dtsi
deleted file mode 100755
index 8cada5e..0000000
--- a/arch/arm/dts/elaine-bx-panel.dtsi
+++ /dev/null
@@ -1,1313 +0,0 @@
-/*
- * arch/arm/dts/elaine-bx-panel.dtsi
- *
- * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-/ {
- lcd{
- compatible = "amlogic, lcd-sm1";
- mode = "tablet";
- status = "okay";
- key_valid = <0>;
- clocks = <&clkc CLKID_MIPI_DSI_HOST
- &clkc CLKID_MIPI_DSI_PHY
- &clkc CLKID_DSI_MEAS_COMP
- &clkc CLKID_VCLK2_ENCL
- &clkc CLKID_VCLK2_VENCL
- &clkc CLKID_GP0_PLL>;
- clock-names = "dsi_host_gate",
- "dsi_phy_gate",
- "dsi_meas",
- "encl_top_gate",
- "encl_int_gate",
- "gp0_pll";
- reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */
- 0x0 0xff644000 0x0 0x200>; /* dsi_phy */
- interrupts = <0 3 1
- 0 56 1>;
- interrupt-names = "vsync","vsync2";
- pinctrl_version = <2>; /* for uboot */
-
- /* power type:
- * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending)
- * power index:
- * (point gpios_index, or extern_index,0xff=invalid)
- * power value:(0=output low, 1=output high, 2=input)
- * power delay:(unit in ms)
- */
- lcd_cpu-gpios = <&gpio GPIOZ_13 GPIO_ACTIVE_HIGH>;
- lcd_cpu_gpio_names = "GPIOZ_13";
-
- boe_fiti9364_7{
- model_name = "TV070WSM_FT9364";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 700 1053 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 95 163>; /*screen_widht, screen_height*/
- lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/
- 2 8 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 44226000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 400 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_always_hs(0=disable,1=enable)*/
- 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 0x04 3 /* check_reg, check_cnt */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <
- 0xff 5 /* delay 5ms */
- 0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <1>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 0 1 0 200
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 5 /* delay 5ms after mipi off */
- 0 0 0 20 /* reset low */
- 0 1 1 100 /* panel power off */
- 0xff 0 0 0>;
- backlight_index = <0>;
- };
-
- boe_fiti9365_7{
- model_name = "TV070WSM_FT9365";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 700 1053 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 95 163>; /*screen_widht, screen_height*/
- lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/
- 2 8 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 44226000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 400 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_always_hs(0=disable,1=enable)*/
- 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 0x04 3 /* check_reg, check_cnt */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <
- 0xff 5 /* delay 5ms */
- 0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <2>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 0 1 0 200
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 5 /* delay 5ms after mipi off */
- 0 0 0 20 /* reset low */
- 0 1 1 100 /* panel power off */
- 0xff 0 0 0>;
- backlight_index = <0>;
- };
-
- kd_fiti9364_7{
- model_name = "KD070D82_FT9364";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 770 1070 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 3 5>; /*screen_widht, screen_height*/
- lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/
- 6 20 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 49434000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 400 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_always_hs(0=disable,1=enable)*/
- 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 0x04 3 /* check_reg, check_cnt */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <
- 0xff 5 /* delay 5ms */
- 0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <3>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 0 1 0 200 /* panel power on */
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 5 /* delay 5ms after mipi off */
- 0 0 0 20 /* reset low */
- 0 1 1 100 /* panel power off */
- 0xff 0 0 0>;
- backlight_index = <0>;
- };
-
- kd_fiti9365_7{
- model_name = "KD070D82_FT9365";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 770 1070 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 3 5>; /*screen_widht, screen_height*/
- lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/
- 6 20 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 49434000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 400 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_always_hs(0=disable,1=enable)*/
- 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 0x04 3 /* check_reg, check_cnt */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <
- 0xff 5 /* delay 5ms */
- 0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <4>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 0 1 0 200 /* panel power on */
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 5 /* delay 5ms after mipi off */
- 0 0 0 20 /* reset low */
- 0 1 1 100 /* panel power off */
- 0xff 0 0 0>;
- backlight_index = <0>;
- };
-
- boe_sit7703_7{
- model_name = "TV070WSM_ST7703I";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 700 1053 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 95 63>; /*screen_widht, screen_height*/
- lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/
- 2 8 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 44226000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 400 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_always_hs(0=disable,1=enable)*/
- 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10
- 0xf0 3 0 1 100 /* reset high, delay 100ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 220 /* reset high, delay 220ms */
- 0xfc 2 0xda 1 /*check_reg, check_cnt */
- 0xfc 2 0xdb 1 /*check_reg, check_cnt */
- 0xfc 2 0xdc 1 /*check_reg, check_cnt */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <
- 0xff 5 /* delay 5ms */
- 0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <5>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 0 1 0 200 /* panel power on */
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 5 /* delay 5ms after mipi off */
- 0 0 0 20 /* reset low */
- 0 1 1 100 /* panel power off */
- 0xff 0 0 0>;
- backlight_index = <0>;
- };
- };
-
- lcd_extern{
- compatible = "amlogic, lcd_extern";
- dev_name = "lcd_extern";
- status = "okay";
- key_valid = <0>;
-
- extern_1{
- index = <1>;
- extern_name = "mipi_default"; // TV070WSM_FT9364
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- cmd_size = <0xff>;
- init_on = <
- 0x23 2 0xE0 0x00
- 0x23 2 0xE1 0x93
- 0x23 2 0xE2 0x65
- 0x23 2 0xE3 0xF8
- 0x23 2 0xE0 0x01
- 0x23 2 0x00 0x00
- 0x23 2 0x01 0x90
- 0x23 2 0x03 0x00
- 0x23 2 0x04 0x90
- 0x23 2 0x17 0x00
- 0x23 2 0x18 0xB0
- 0x23 2 0x19 0x01
- 0x23 2 0x1A 0x00
- 0x23 2 0x1B 0xB0
- 0x23 2 0x1C 0x01
- 0x23 2 0x1F 0x3E
- 0x23 2 0x20 0x2F
- 0x23 2 0x21 0x2F
- 0x23 2 0x22 0x0E
- 0x23 2 0x37 0x69
- 0x23 2 0x38 0x05
- 0x23 2 0x39 0x00
- 0x23 2 0x3A 0x01
- 0x23 2 0x3C 0x90
- 0x23 2 0x3D 0xFF
- 0x23 2 0x3E 0xFF
- 0x23 2 0x3F 0xFF
- 0x23 2 0x40 0x02
- 0x23 2 0x41 0x80
- 0x23 2 0x42 0x99
- 0x23 2 0x43 0x06
- 0x23 2 0x44 0x09
- 0x23 2 0x45 0x3C
- 0x23 2 0x4B 0x04
- 0x23 2 0x55 0x0D
- 0x23 2 0x56 0x01
- 0x23 2 0x57 0x89
- 0x23 2 0x58 0x0A
- 0x23 2 0x59 0x0A
- 0x23 2 0x5A 0x27
- 0x23 2 0x5B 0x15
- 0x23 2 0x5D 0x7C
- 0x23 2 0x5E 0x67
- 0x23 2 0x5F 0x58
- 0x23 2 0x60 0x4C
- 0x23 2 0x61 0x48
- 0x23 2 0x62 0x38
- 0x23 2 0x63 0x3C
- 0x23 2 0x64 0x24
- 0x23 2 0x65 0x3B
- 0x23 2 0x66 0x38
- 0x23 2 0x67 0x36
- 0x23 2 0x68 0x53
- 0x23 2 0x69 0x3F
- 0x23 2 0x6A 0x44
- 0x23 2 0x6B 0x35
- 0x23 2 0x6C 0x2E
- 0x23 2 0x6D 0x1F
- 0x23 2 0x6E 0x0C
- 0x23 2 0x6F 0x00
- 0x23 2 0x70 0x7C
- 0x23 2 0x71 0x67
- 0x23 2 0x72 0x58
- 0x23 2 0x73 0x4C
- 0x23 2 0x74 0x48
- 0x23 2 0x75 0x38
- 0x23 2 0x76 0x3C
- 0x23 2 0x77 0x24
- 0x23 2 0x78 0x3B
- 0x23 2 0x79 0x38
- 0x23 2 0x7A 0x36
- 0x23 2 0x7B 0x53
- 0x23 2 0x7C 0x3F
- 0x23 2 0x7D 0x44
- 0x23 2 0x7E 0x35
- 0x23 2 0x7F 0x2E
- 0x23 2 0x80 0x1F
- 0x23 2 0x81 0x0C
- 0x23 2 0x82 0x00
- 0x23 2 0xE0 0x02
- 0x23 2 0x00 0x45
- 0x23 2 0x01 0x45
- 0x23 2 0x02 0x47
- 0x23 2 0x03 0x47
- 0x23 2 0x04 0x41
- 0x23 2 0x05 0x41
- 0x23 2 0x06 0x1F
- 0x23 2 0x07 0x1F
- 0x23 2 0x08 0x1F
- 0x23 2 0x09 0x1F
- 0x23 2 0x0A 0x1F
- 0x23 2 0x0B 0x1F
- 0x23 2 0x0C 0x1F
- 0x23 2 0x0D 0x1D
- 0x23 2 0x0E 0x1D
- 0x23 2 0x0F 0x1D
- 0x23 2 0x10 0x1F
- 0x23 2 0x11 0x1F
- 0x23 2 0x12 0x1F
- 0x23 2 0x13 0x1F
- 0x23 2 0x14 0x1F
- 0x23 2 0x15 0x1F
- 0x23 2 0x16 0x44
- 0x23 2 0x17 0x44
- 0x23 2 0x18 0x46
- 0x23 2 0x19 0x46
- 0x23 2 0x1A 0x40
- 0x23 2 0x1B 0x40
- 0x23 2 0x1C 0x1F
- 0x23 2 0x1D 0x1F
- 0x23 2 0x1E 0x1F
- 0x23 2 0x1F 0x1F
- 0x23 2 0x20 0x1F
- 0x23 2 0x21 0x1F
- 0x23 2 0x22 0x1F
- 0x23 2 0x23 0x1D
- 0x23 2 0x24 0x1D
- 0x23 2 0x25 0x1D
- 0x23 2 0x26 0x1F
- 0x23 2 0x27 0x1F
- 0x23 2 0x28 0x1F
- 0x23 2 0x29 0x1F
- 0x23 2 0x2A 0x1F
- 0x23 2 0x2B 0x1F
- 0x23 2 0x58 0x40
- 0x23 2 0x59 0x00
- 0x23 2 0x5A 0x00
- 0x23 2 0x5B 0x10
- 0x23 2 0x5C 0x07
- 0x23 2 0x5D 0x20
- 0x23 2 0x5E 0x00
- 0x23 2 0x5F 0x00
- 0x23 2 0x61 0x00
- 0x23 2 0x62 0x00
- 0x23 2 0x63 0x7A
- 0x23 2 0x64 0x7A
- 0x23 2 0x65 0x00
- 0x23 2 0x66 0x00
- 0x23 2 0x67 0x32
- 0x23 2 0x68 0x08
- 0x23 2 0x69 0x7A
- 0x23 2 0x6A 0x7A
- 0x23 2 0x6B 0x00
- 0x23 2 0x6C 0x00
- 0x23 2 0x6D 0x00
- 0x23 2 0x6E 0x00
- 0x23 2 0x6F 0x89
- 0x23 2 0x70 0x00
- 0x23 2 0x71 0x00
- 0x23 2 0x72 0x06
- 0x23 2 0x73 0x7B
- 0x23 2 0x74 0x00
- 0x23 2 0x75 0x07
- 0x23 2 0x76 0x00
- 0x23 2 0x77 0x5D
- 0x23 2 0x78 0x17
- 0x23 2 0x79 0x1F
- 0x23 2 0x7A 0x00
- 0x23 2 0x7B 0x00
- 0x23 2 0x7C 0x00
- 0x23 2 0x7D 0x03
- 0x23 2 0x7E 0x7B
- 0x23 2 0xE0 0x03
- 0x23 2 0xAF 0x20
- 0x23 2 0xE0 0x04
- 0x23 2 0x09 0x11
- 0x23 2 0x0E 0x48
- 0x23 2 0x2B 0x2B
- 0x23 2 0x2E 0x44
- 0x23 2 0x41 0xFF
- 0x23 2 0xE0 0x00
- 0x23 2 0xE6 0x02
- 0x23 2 0xE7 0x0C
- 0x23 2 0x51 0xFF
- 0x23 2 0x53 0x2C
- 0x23 2 0x55 0x00
- 0x05 1 0x11
- 0xFF 125 /* Delay 125ms */
- 0x05 1 0x29
- 0xFF 0xFF /* Ending Flag */
- >;
- init_off = <
- 0xff 5
- 0x05 1 0x28 /* display off */
- 0xff 60 /* delay 60ms */
- 0x05 1 0x10 /* sleep in */
- 0xff 110 /* delay 110ms */
- 0xff 0xff>; /* ending */
- };
-
- extern_2{
- index = <2>;
- extern_name = "mipi_default"; // TV070WSM_FT9365
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- cmd_size = <0xff>;
- init_on = <
- 0x23 2 0xE0 0x00 /*Page 0*/
- 0x23 2 0xE1 0x93
- 0x23 2 0xE2 0x65
- 0x23 2 0xE3 0xF8
- 0x23 2 0xE0 0x01 /*Page 1*/
- 0x23 2 0x00 0x00
- 0x23 2 0x01 0x90
- 0x23 2 0x03 0x00
- 0x23 2 0x04 0x90
- 0x23 2 0x17 0x00
- 0x23 2 0x18 0xB0
- 0x23 2 0x19 0x01
- 0x23 2 0x1A 0x00
- 0x23 2 0x1B 0xB0
- 0x23 2 0x1C 0x01
- 0x23 2 0x35 0x28 /*Set SAP = 8*/
- 0x23 2 0x37 0x69 /*SET panel_ctrl*/
- 0x23 2 0x38 0x05 /*SET RGBCYC*/
- 0x23 2 0x39 0x00
- 0x23 2 0x3A 0x01
- 0x23 2 0x3C 0x90
- 0x23 2 0x3D 0xFF
- 0x23 2 0x3E 0xFF
- 0x23 2 0x3F 0xFF
- 0x23 2 0x40 0x02 /*SET_TCON*/
- 0x23 2 0x41 0x80
- 0x23 2 0x42 0x99
- 0x23 2 0x43 0x06
- 0x23 2 0x44 0x09
- 0x23 2 0x45 0x3C
- 0x23 2 0x4B 0x04
- 0x23 2 0x55 0x02 /*Power Voltage*/
- 0x23 2 0x56 0x01
- 0x23 2 0x57 0x89
- 0x23 2 0x58 0x0A
- 0x23 2 0x59 0x0A
- 0x23 2 0x5A 0x27
- 0x23 2 0x5B 0x15
- 0x23 2 0x5D 0x7C /*Gamma*/
- 0x23 2 0x5E 0x65
- 0x23 2 0x5F 0x53
- 0x23 2 0x60 0x46
- 0x23 2 0x61 0x41
- 0x23 2 0x62 0x33
- 0x23 2 0x63 0x35
- 0x23 2 0x64 0x1E
- 0x23 2 0x65 0x36
- 0x23 2 0x66 0x34
- 0x23 2 0x67 0x34
- 0x23 2 0x68 0x51
- 0x23 2 0x69 0x3E
- 0x23 2 0x6A 0x44
- 0x23 2 0x6B 0x35
- 0x23 2 0x6C 0x2E
- 0x23 2 0x6D 0x1F
- 0x23 2 0x6E 0x0C
- 0x23 2 0x6F 0x00
- 0x23 2 0x70 0x7C
- 0x23 2 0x71 0x65
- 0x23 2 0x72 0x53
- 0x23 2 0x73 0x46
- 0x23 2 0x74 0x41
- 0x23 2 0x75 0x33
- 0x23 2 0x76 0x35
- 0x23 2 0x77 0x1E
- 0x23 2 0x78 0x36
- 0x23 2 0x79 0x34
- 0x23 2 0x7A 0x34
- 0x23 2 0x7B 0x51
- 0x23 2 0x7C 0x3E
- 0x23 2 0x7D 0x44
- 0x23 2 0x7E 0x35
- 0x23 2 0x7F 0x2E
- 0x23 2 0x80 0x1F
- 0x23 2 0x81 0x0C
- 0x23 2 0x82 0x00
- 0x23 2 0xE0 0x02 /*Page 2*/
- 0x23 2 0x00 0x45 /*GIP_L*/
- 0x23 2 0x01 0x45
- 0x23 2 0x02 0x47
- 0x23 2 0x03 0x47
- 0x23 2 0x04 0x41
- 0x23 2 0x05 0x41
- 0x23 2 0x06 0x1F
- 0x23 2 0x07 0x1F
- 0x23 2 0x08 0x1F
- 0x23 2 0x09 0x1F
- 0x23 2 0x0A 0x1F
- 0x23 2 0x0B 0x1F
- 0x23 2 0x0C 0x1F
- 0x23 2 0x0D 0x1D
- 0x23 2 0x0E 0x1D
- 0x23 2 0x0F 0x1D
- 0x23 2 0x10 0x1F
- 0x23 2 0x11 0x1F
- 0x23 2 0x12 0x1F
- 0x23 2 0x13 0x1F
- 0x23 2 0x14 0x1F
- 0x23 2 0x15 0x1F
- 0x23 2 0x16 0x44 /*GIP_R*/
- 0x23 2 0x17 0x44
- 0x23 2 0x18 0x46
- 0x23 2 0x19 0x46
- 0x23 2 0x1A 0x40
- 0x23 2 0x1B 0x40
- 0x23 2 0x1C 0x1F
- 0x23 2 0x1D 0x1F
- 0x23 2 0x1E 0x1F
- 0x23 2 0x1F 0x1F
- 0x23 2 0x20 0x1F
- 0x23 2 0x21 0x1F
- 0x23 2 0x22 0x1F
- 0x23 2 0x23 0x1D
- 0x23 2 0x24 0x1D
- 0x23 2 0x25 0x1D
- 0x23 2 0x26 0x1F
- 0x23 2 0x27 0x1F
- 0x23 2 0x28 0x1F
- 0x23 2 0x29 0x1F
- 0x23 2 0x2A 0x1F
- 0x23 2 0x2B 0x1F
- 0x23 2 0x58 0x40 /*GIP Timing*/
- 0x23 2 0x59 0x00
- 0x23 2 0x5A 0x00
- 0x23 2 0x5B 0x10
- 0x23 2 0x5C 0x07
- 0x23 2 0x5D 0x20
- 0x23 2 0x5E 0x00
- 0x23 2 0x5F 0x00
- 0x23 2 0x61 0x00
- 0x23 2 0x62 0x00
- 0x23 2 0x63 0x7A
- 0x23 2 0x64 0x7A
- 0x23 2 0x65 0x00
- 0x23 2 0x66 0x00
- 0x23 2 0x67 0x32
- 0x23 2 0x68 0x08
- 0x23 2 0x69 0x7A
- 0x23 2 0x6A 0x7A
- 0x23 2 0x6B 0x00
- 0x23 2 0x6C 0x00
- 0x23 2 0x6D 0x04
- 0x23 2 0x6E 0x04
- 0x23 2 0x6F 0x89
- 0x23 2 0x70 0x00
- 0x23 2 0x71 0x00
- 0x23 2 0x72 0x06
- 0x23 2 0x73 0x7B
- 0x23 2 0x74 0x00
- 0x23 2 0x75 0x07
- 0x23 2 0x76 0x00
- 0x23 2 0x77 0x5D
- 0x23 2 0x78 0x17
- 0x23 2 0x79 0x1F
- 0x23 2 0x7A 0x00
- 0x23 2 0x7B 0x00
- 0x23 2 0x7C 0x00
- 0x23 2 0x7D 0x03
- 0x23 2 0x7E 0x7B
- 0x23 2 0xE0 0x03 /*Page 3*/
- 0x23 2 0xA9 0x02
- 0x23 2 0xAC 0x4D
- 0x23 2 0xE0 0x04 /*Page 4*/
- 0x23 2 0x00 0x0E
- 0x23 2 0x02 0xB3
- 0x23 2 0x09 0x60
- 0x23 2 0x0E 0x48
- 0x23 2 0xE0 0x00 /*Page 0*/
- 0x23 2 0x51 0xFF
- 0x23 2 0x53 0x2C
- 0xFF 5 /*Delay 5ms*/
- 0x05 1 0x11
- 0xFF 125 /*Delay 125ms*/
- 0x05 1 0x29
- 0xFF 20 /*Delay 20ms*/
- 0xFF 0xFF /*Ending Flag*/
- >;
- init_off = <
- 0xff 5
- 0x05 1 0x28 /* display off */
- 0xff 60 /* delay 60ms */
- 0x05 1 0x10 /* sleep in */
- 0xff 110 /* delay 110ms */
- 0xff 0xff>; /* ending */
- };
-
- extern_3{
- index = <3>;
- extern_name = "mipi_default"; // KD070D82_FT9364
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- cmd_size = <0xff>;
- init_on = <
- 0x23 2 0xE0 0x00 /* Register setting change to Page 0 */
- 0x23 2 0xE1 0x93 /* PASSWORD, setting as 93-65-F8 to enable page1-4 command access */
- 0x23 2 0xE2 0x65
- 0x23 2 0xE3 0xF8
- 0x23 2 0x80 0x03 /* Setting DSI lane number, 0x03 is DSI 4 lane */
- 0x23 2 0xE0 0x01 /* Register setting change to Page 1 */
- 0x23 2 0x00 0x00 /* Set VCOM_Forward */
- 0x23 2 0x01 0x9E /* VCOM=0x09F */
- 0x23 2 0x03 0x00 /* Set VCOM_Reverse */
- 0x23 2 0x04 0xAA /* VCOMR=0x0AA, -1.40V */
- 0x23 2 0x0C 0x74 /* Set PWRIC pumping frequency,=8 HCLK, about 512KHz */
- 0x23 2 0x17 0x00 /* Set Gamma Power, VGMP[8]=0, VGSP[8]=0 */
- 0x23 2 0x18 0xEF /* VGMP[8:0]=0x0EF=5.1V */
- 0x23 2 0x19 0x00 /* VGSP[8:0]=0x000=0V */
- 0x23 2 0x1A 0x00 /* VGMN[8]=0, VGSN[8]=0 */
- 0x23 2 0x1B 0xEF /* VGMN[8:0]=0x0EF=-5.1V */
- 0x23 2 0x1C 0x00 /* VGSN[8:0]=0x000=0V */
- 0x23 2 0x1F 0x70 /* VGH_REG=16.2V */
- 0x23 2 0x20 0x2D /* VGL_REG=-12V */
- 0x23 2 0x21 0x2D /* VGL_REG2=-12V */
- 0x23 2 0x22 0x7E /* VGH_REG short to VGH, VGL_REG short to VGL, */
- 0x23 2 0x26 0xF3 /* VDDD from IOVCC&VCI */
- 0x23 2 0x37 0x09 /* SS=1, source scan from S2400 to S1;BGR=1 CF type is (S1,S2,S3) align to (B,G,R) */
- 0x23 2 0x38 0x04 /* JDT=100, display inversion type is column inversion */
- 0x23 2 0x39 0x00 /* Source EQ Setting, EQ1, 0x00=0us */
- 0x23 2 0x3A 0x01 /* Source EQ Setting, EQ2, 0x01 =0.1us */
- 0x23 2 0x3C 0x90 /* Source EQ Setting, EQ3, EQ3 start at 14.4us */
- 0x23 2 0x3D 0xFF /* SET Source OP on time, 0xFF means source op always on */
- 0x23 2 0x3E 0xFF /* SET Source OP off time, 0xFF means source op always on */
- 0x23 2 0x3F 0xFF /* SET Source OP off time, 0xFF means source op always on */
- 0x23 2 0x40 0x02 /* horizontal resolution setting,RSO[2:0]= 0x02 =600RGB, LN[1:0]=2'b00 */
- 0x23 2 0x41 0x80 /* LN[9:0]=0x200=512, vertical resolution is 512*2=1024 line */
- 0x23 2 0x42 0x99 /* SLT, internal line period=0x99->15.3us */
- 0x23 2 0x43 0x14 /* Internal VFP=Ext_VFP=20(0x14) */
- 0x23 2 0x44 0x19 /* Internal _VBP=Ext_VS+Ext_VBP-1=6+20-1=25(0x19) */
- 0x23 2 0x45 0x5A /* Internal_HBP=Ext_HS+Ext_HBP=90(0x5A) */
- 0x23 2 0x55 0x02 /* Seting PWRIC mode, DCDCM=0010-> FP7721BX2 */
- 0x23 2 0x56 0x01 /* No auto Ratio function */
- 0x23 2 0x57 0x69 /* VGH_RT=3'b011,2*AVDD-AVEE,VGL_RT=3'b010=AVEE+VCL-AVDD,VCL_RT=2'b00,0.5*VCIP */
- 0x23 2 0x58 0x0A /* AVDD_S, not use internal AVDD in this model */
- 0x23 2 0x59 0x0A /* VCL = -2.5V */
- 0x23 2 0x5A 0x2E /* VGH = 16.2V */
- 0x23 2 0x5B 0x19 /* VGL = -12V */
- 0x23 2 0x5C 0x15 /* pump clk, VCL_CLK[1:0]=2'b01=HCLK/2=32KHz, VGHVGL_CLK[1:0]=2'b01=HCLK/2=32KHz */
- 0x23 2 0x5D 0x77 /* Gamma voltage setting, VP255-4.793V */
- 0x23 2 0x5E 0x5C /* VP251 */
- 0x23 2 0x5F 0x4D /* VP247 */
- 0x23 2 0x60 0x40 /* VP243 */
- 0x23 2 0x61 0x3D /* VP235 */
- 0x23 2 0x62 0x2F /* VP227 */
- 0x23 2 0x63 0x34 /* VP211 */
- 0x23 2 0x64 0x1F /* VP191 */
- 0x23 2 0x65 0x38 /* VP159 */
- 0x23 2 0x66 0x38 /* VP128 */
- 0x23 2 0x67 0x39 /* VP96 */
- 0x23 2 0x68 0x58 /* VP64 */
- 0x23 2 0x69 0x48 /* VP44 */
- 0x23 2 0x6A 0x51 /* VP28 */
- 0x23 2 0x6B 0x44 /* VP20 */
- 0x23 2 0x6C 0x41 /* VP12 */
- 0x23 2 0x6D 0x35 /* VP8 */
- 0x23 2 0x6E 0x24 /* VP4 */
- 0x23 2 0x6F 0x02 /* VP0 */
- 0x23 2 0x70 0x77 /* VN255 */
- 0x23 2 0x71 0x5C /* VN251 */
- 0x23 2 0x72 0x4D /* VN247 */
- 0x23 2 0x73 0x40 /* VN243 */
- 0x23 2 0x74 0x3D /* VN235 */
- 0x23 2 0x75 0x2F /* VN227 */
- 0x23 2 0x76 0x34 /* VN211 */
- 0x23 2 0x77 0x1F /* VN191 */
- 0x23 2 0x78 0x38 /* VN159 */
- 0x23 2 0x79 0x38 /* VN128 */
- 0x23 2 0x7A 0x39 /* VN96 */
- 0x23 2 0x7B 0x58 /* VN64 */
- 0x23 2 0x7C 0x48 /* VN44 */
- 0x23 2 0x7D 0x51 /* VN28 */
- 0x23 2 0x7E 0x44 /* VN20 */
- 0x23 2 0x7F 0x41 /* VN12 */
- 0x23 2 0x80 0x35 /* VN8 */
- 0x23 2 0x81 0x24 /* VN4 */
- 0x23 2 0x82 0x02 /* VN0 */
- 0x23 2 0xE0 0x02 /* Register setting change to Page 2 */
- 0x23 2 0x00 0x53 /* GIP_L_Forward scan mapping, assign as RESET_EVEN */
- 0x23 2 0x01 0x55 /* assign as VSSG_EVEN */
- 0x23 2 0x02 0x55 /* assign as VSSA_EVEN */
- 0x23 2 0x03 0x51 /* assign as STV2_EVEN */
- 0x23 2 0x04 0x77 /* assign as VDD2_EVEN */
- 0x23 2 0x05 0x57 /* assign as VDD1_EVEN */
- 0x23 2 0x06 0x1F /* assign as VGL */
- 0x23 2 0x07 0x4F /* assign as CK12 */
- 0x23 2 0x08 0x4D /* assign as CK10 */
- 0x23 2 0x09 0x1F /* assign as VGL */
- 0x23 2 0x0A 0x4B /* assign as CK8 */
- 0x23 2 0x0B 0x49 /* assign as CK6 */
- 0x23 2 0x0C 0x1F /* assign as VGL */
- 0x23 2 0x0D 0x47 /* assign as CK4 */
- 0x23 2 0x0E 0x45 /* assign as CK2 */
- 0x23 2 0x0F 0x41 /* assign as STV1_EVEN */
- 0x23 2 0x10 0x1F /* assign as VGL */
- 0x23 2 0x11 0x1F /* assign as VGL */
- 0x23 2 0x12 0x1F /* assign as VGL */
- 0x23 2 0x13 0x55 /* assign as VGG */
- 0x23 2 0x14 0x1F /* assign as VGL */
- 0x23 2 0x15 0x1F /* assign as VGL */
- 0x23 2 0x16 0x52 /* GIP_R_Forward scan mapping, assign as RESET_ODD */
- 0x23 2 0x17 0x55 /* assign as VSSG_ODD */
- 0x23 2 0x18 0x55 /* assign as VSSA_ODD */
- 0x23 2 0x19 0x50 /* assign as STV2_ODD */
- 0x23 2 0x1A 0x77 /* assign as VDD2_ODD */
- 0x23 2 0x1B 0x57 /* assign as VDD1_ODD */
- 0x23 2 0x1C 0x1F /* assign as VGL */
- 0x23 2 0x1D 0x4E /* assign as CK11 */
- 0x23 2 0x1E 0x4C /* assign as CK9 */
- 0x23 2 0x1F 0x1F /* assign as VGL */
- 0x23 2 0x20 0x4A /* assign as CK7 */
- 0x23 2 0x21 0x48 /* assign as CK5 */
- 0x23 2 0x22 0x1F /* assign as VGL */
- 0x23 2 0x23 0x46 /* assign as CK3 */
- 0x23 2 0x24 0x44 /* assign as CK1 */
- 0x23 2 0x25 0x40 /* assign as STV1_ODD */
- 0x23 2 0x26 0x1F /* assign as VGL */
- 0x23 2 0x27 0x1F /* assign as VGL */
- 0x23 2 0x28 0x1F /* assign as VGL */
- 0x23 2 0x29 0x1F /* assign as VGL */
- 0x23 2 0x2A 0x1F /* assign as VGL */
- 0x23 2 0x2B 0x55 /* assign as VGG */
- 0x23 2 0x2C 0x12 /* GIP_L_Reverse Scan mapping, assign as RESET_EVEN */
- 0x23 2 0x2D 0x15 /* assign as VSSG_EVEN */
- 0x23 2 0x2E 0x15 /* assign as VSSA_EVEN */
- 0x23 2 0x2F 0x00 /* assign as STV2_EVEN */
- 0x23 2 0x30 0x17 /* assign as VDD2_EVEN */
- 0x23 2 0x31 0x17 /* assign as VDD1_EVEN */
- 0x23 2 0x32 0x1F /* assign as VGL */
- 0x23 2 0x33 0x08 /* assign as CK12 */
- 0x23 2 0x34 0x0A /* assign as CK10 */
- 0x23 2 0x35 0x1F /* assign as VGL */
- 0x23 2 0x36 0x0C /* assign as CK8 */
- 0x23 2 0x37 0x0E /* assign as CK6 */
- 0x23 2 0x38 0x1F /* assign as VGL */
- 0x23 2 0x39 0x04 /* assign as CK4 */
- 0x23 2 0x3A 0x06 /* assign as CK2 */
- 0x23 2 0x3B 0x10 /* assign as STV1_EVEN */
- 0x23 2 0x3C 0x1F /* assign as VGL */
- 0x23 2 0x3D 0x1F /* assign as VGL */
- 0x23 2 0x3E 0x1F /* assign as VGL */
- 0x23 2 0x3F 0x15 /* assign as VGG */
- 0x23 2 0x40 0x1F /* assign as VGL */
- 0x23 2 0x41 0x1F /* assign as VGL */
- 0x23 2 0x42 0x13 /* GIP_R_Reverse Scan mapping, assign as RESET_ODD */
- 0x23 2 0x43 0x15 /* assign as VSSG_ODD */
- 0x23 2 0x44 0x15 /* assign as VSSA_ODD */
- 0x23 2 0x45 0x01 /* assign as STV2_ODD */
- 0x23 2 0x46 0x17 /* assign as VDD2_ODD */
- 0x23 2 0x47 0x17 /* assign as VDD1_ODD */
- 0x23 2 0x48 0x1F /* assign as VGL */
- 0x23 2 0x49 0x09 /* assign as CK11 */
- 0x23 2 0x4A 0x0B /* assign as CK9 */
- 0x23 2 0x4B 0x1F /* assign as VGL */
- 0x23 2 0x4C 0x0D /* assign as CK7 */
- 0x23 2 0x4D 0x0F /* assign as CK5 */
- 0x23 2 0x4E 0x1F /* assign as VGL */
- 0x23 2 0x4F 0x05 /* assign as CK3 */
- 0x23 2 0x50 0x07 /* assign as CK1 */
- 0x23 2 0x51 0x11 /* assign as STV1_ODD */
- 0x23 2 0x52 0x1F /* assign as VGL */
- 0x23 2 0x53 0x1F /* assign as VGL */
- 0x23 2 0x54 0x1F /* assign as VGL */
- 0x23 2 0x55 0x1F /* assign as VGL */
- 0x23 2 0x56 0x1F /* assign as VGL */
- 0x23 2 0x57 0x15 /* assign as VGG */
- 0x23 2 0x58 0x40 /* GAS OPT=1, When abnormal power off, GIP will pull to VGH */
- 0x23 2 0x59 0x00 /* INIT_W=0, no INIT function in this panel */
- 0x23 2 0x5A 0x00 /* INIT[10:0], no INIT function in this panel */
- 0x23 2 0x5B 0x10 /* STV_NUM,STV_S0[10:8], 2 STV pulses */
- 0x23 2 0x5C 0x14 /* STV_S0[7:0], STV start from 21th hsync after vsync */
- 0x23 2 0x5D 0x40 /* STV_W=4, STV width is 4 Hline; STV1 delay 1 hline with STV0 */
- 0x23 2 0x5E 0x01 /* STV_S2, STV2 delay 2 hline with STV0 */
- 0x23 2 0x5F 0x02 /* STV_S3, STV3 delay 3 hline with STV0 */
- 0x23 2 0x60 0x40 /* ETV_W=4, ETV witdh is 4 hline; ETV1 delay 1 hilne from ETV0 */
- 0x23 2 0x61 0x03 /* ETV_S2, ETV2 delay 4 hline with ETV0 */
- 0x23 2 0x62 0x04 /* ETV_S3, ETV3 delay 5 hline with ETV0 */
- 0x23 2 0x63 0x7A /* SETV_ON for STV/ETV on time, rising at 12.2us after hsync */
- 0x23 2 0x64 0x7A /* SETV_OFF for STV/ETV off time , falling at 12.2us after hsync */
- 0x23 2 0x65 0x74 /* ETV_EN=1, enable ETV function; ETV_NUM=3, using 4 ETV pulse, */
- 0x23 2 0x66 0x16 /* ETV_S0=0x416, EVT start at 1046th hsync fater vaync */
- 0x23 2 0x67 0xB4 /* CKV_NUM=2'b1011, using 12 CKV pulse; CKV0_W=4. CKV width is 4 hline */
- 0x23 2 0x68 0x16 /* CKV0_S0 , CKV start from 23th hsync after vsync */
- 0x23 2 0x69 0x7A /* CKV0_on ,for CKV on time, rising at 12.2us after hsync */
- 0x23 2 0x6A 0x7A /* CKV0_off ,for CKV off time, falling at 12.2us after hsync */
- 0x23 2 0x6B 0x0C /* CKV0_DUM, total CKV pulse number=1024+12=1036 */
- 0x23 2 0x6C 0x00 /* GIP Line EQ option , disable GEQ_Line function */
- 0x23 2 0x6D 0x04 /* GIP rising EQ, period is 0.4us */
- 0x23 2 0x6E 0x04 /* GIP fallig EQ, period is 0.4us */
- 0x23 2 0x6F 0x88 /* GIP_DR; CKV0_CON, no continuous CKV0; CKV1_CON, no continuous CKV1 */
- 0x23 2 0x70 0x00 /* CKV1_NUM, CKV0_W , no CKV group 1 function in this panel, don't care */
- 0x23 2 0x71 0x00 /* CKV1_S0, no CKV group 1 function in this panel, don't care */
- 0x23 2 0x72 0x06 /* CKV1_on , no CKV group 1 function in this panel, don't care */
- 0x23 2 0x73 0x7B /* CKV1_off time, no CKV group 1 function in this panel, don't care */
- 0x23 2 0x74 0x00 /* CKV1_DUM, no CKV group 1 function in this panel, don't care */
- 0x23 2 0x75 0xBC /* FLM_EN, enable FLM function; FLM_W=0x3C, FLM toggle period is 60 frame */
- 0x23 2 0x76 0x00 /* FLM on time , FLM on(rising) at 1st hsync after vsync */
- 0x23 2 0x77 0x04 /* VEN_EN, VEN_W, no VEN function in this panel, don't care */
- 0x23 2 0x78 0x2C /* FLM_OFF, FLM off(falling) at 1068th hsync after vsync */
- 0x23 2 0x79 0x00 /* VEN_W , no VEN function in this panel, don't care */
- 0x23 2 0x7A 0x00 /* VEN_S0 , no VEN function in this panel, don't care */
- 0x23 2 0x7B 0x00 /* VEN_S1 , no VEN function in this panel, don't care */
- 0x23 2 0x7C 0x00 /* VEN_DUM , no VEN function in this panel, don't care */
- 0x23 2 0x7D 0x03 /* VEN on time , no VEN function in this panel, don't care */
- 0x23 2 0x7E 0x7B /* VEN off time , no VEN function in this panel, don't care */
- 0x23 2 0xE0 0x03 /* Register setting change to Page 3 */
- 0x23 2 0xAF 0x20 /* Set CABC, disable CABC TP detect, for CABC pattern change more smooth */
- 0x23 2 0xE0 0x04 /* Register setting change to Page 4 */
- 0x23 2 0x09 0x11 /* Source level at blanking period, sweeping V0 level */
- 0x23 2 0x0E 0x48 /* Source EQ option, EQ to PCAP,NCAP */
- 0x23 2 0x2B 0x2B /* ESD Protect, clock lane op behavior follow data lane, improve ESD performance */
- 0x23 2 0x2E 0x44 /* ESD protect, disable special packet */
- 0x23 2 0x41 0xFF /* Set CABC, for CABC pattern change more smooth */
- 0x23 2 0xE0 0x00 /* Register setting change to Page 0 */
- 0x23 2 0xE6 0x02 /* Enable Watch Dog */
- 0x23 2 0xE7 0x0C /* Watch Dog timer setting, WD alarm time is 12*512osc after hsync stop */
- 0x23 2 0x51 0xFF /* CABC Option, 0x80=50% duty, 0xFF=100% */
- 0x23 2 0x53 0x2C /* enable dimming, BCTRL, BL */
- 0x23 2 0x55 0x00 /* CABC mode, 0x00 is manual mode */
- 0x05 1 0x11 /* SLPOUT */
- 0xFF 125 /* Delay 125ms */
- 0x05 1 0x29 /* Display On */
- 0xFF 0xFF /* Ending */
- >;
- init_off = <
- 0xff 5
- 0x05 1 0x28 /* display off */
- 0xff 60 /* delay 60ms */
- 0x05 1 0x10 /* sleep in */
- 0xff 110 /* delay 110ms */
- 0xff 0xff>; /* ending */
- };
-
- extern_4{
- index = <4>;
- extern_name = "mipi_default"; // KD070D82_FT9365
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- cmd_size = <0xff>;
- init_on = <
- 0x23 2 0xE0 0x00
- 0x23 2 0xE1 0x93
- 0x23 2 0xE2 0x65
- 0x23 2 0xE3 0xF8
- 0x23 2 0x80 0x03
- 0x23 2 0xE0 0x01
- 0x23 2 0x00 0x00
- 0x23 2 0x01 0x9E
- 0x23 2 0x03 0x00
- 0x23 2 0x04 0xAA
- 0x23 2 0x0C 0x74
- 0x23 2 0x17 0x00
- 0x23 2 0x18 0xEF
- 0x23 2 0x19 0x00
- 0x23 2 0x1A 0x00
- 0x23 2 0x1B 0xEF
- 0x23 2 0x1C 0x00
- 0x23 2 0x37 0x09
- 0x23 2 0x38 0x04
- 0x23 2 0x39 0x00
- 0x23 2 0x3A 0x01
- 0x23 2 0x3C 0x90
- 0x23 2 0x3D 0xFF
- 0x23 2 0x3E 0xFF
- 0x23 2 0x3F 0xFF
- 0x23 2 0x40 0x02
- 0x23 2 0x41 0x80
- 0x23 2 0x42 0x99
- 0x23 2 0x43 0x14
- 0x23 2 0x44 0x19
- 0x23 2 0x45 0x5A
- 0x23 2 0x55 0x02
- 0x23 2 0x56 0x01
- 0x23 2 0x57 0x69
- 0x23 2 0x58 0x0A
- 0x23 2 0x59 0x0A
- 0x23 2 0x5A 0x2E
- 0x23 2 0x5B 0x19
- 0x23 2 0x5C 0x15
- 0x23 2 0x5D 0x77
- 0x23 2 0x5E 0x5C
- 0x23 2 0x5F 0x4D
- 0x23 2 0x60 0x40
- 0x23 2 0x61 0x3D
- 0x23 2 0x62 0x2F
- 0x23 2 0x63 0x34
- 0x23 2 0x64 0x1F
- 0x23 2 0x65 0x38
- 0x23 2 0x66 0x38
- 0x23 2 0x67 0x39
- 0x23 2 0x68 0x58
- 0x23 2 0x69 0x48
- 0x23 2 0x6A 0x51
- 0x23 2 0x6B 0x44
- 0x23 2 0x6C 0x41
- 0x23 2 0x6D 0x35
- 0x23 2 0x6E 0x24
- 0x23 2 0x6F 0x02
- 0x23 2 0x70 0x77
- 0x23 2 0x71 0x5C
- 0x23 2 0x72 0x4D
- 0x23 2 0x73 0x40
- 0x23 2 0x74 0x3D
- 0x23 2 0x75 0x2F
- 0x23 2 0x76 0x34
- 0x23 2 0x77 0x1F
- 0x23 2 0x78 0x38
- 0x23 2 0x79 0x38
- 0x23 2 0x7A 0x39
- 0x23 2 0x7B 0x58
- 0x23 2 0x7C 0x48
- 0x23 2 0x7D 0x51
- 0x23 2 0x7E 0x44
- 0x23 2 0x7F 0x41
- 0x23 2 0x80 0x35
- 0x23 2 0x81 0x24
- 0x23 2 0x82 0x02
- 0x23 2 0xE0 0x02
- 0x23 2 0x00 0x53
- 0x23 2 0x01 0x55
- 0x23 2 0x02 0x55
- 0x23 2 0x03 0x51
- 0x23 2 0x04 0x77
- 0x23 2 0x05 0x57
- 0x23 2 0x06 0x1F
- 0x23 2 0x07 0x4F
- 0x23 2 0x08 0x4D
- 0x23 2 0x09 0x1F
- 0x23 2 0x0A 0x4B
- 0x23 2 0x0B 0x49
- 0x23 2 0x0C 0x1F
- 0x23 2 0x0D 0x47
- 0x23 2 0x0E 0x45
- 0x23 2 0x0F 0x41
- 0x23 2 0x10 0x1F
- 0x23 2 0x11 0x1F
- 0x23 2 0x12 0x1F
- 0x23 2 0x13 0x55
- 0x23 2 0x14 0x1F
- 0x23 2 0x15 0x1F
- 0x23 2 0x16 0x52
- 0x23 2 0x17 0x55
- 0x23 2 0x18 0x55
- 0x23 2 0x19 0x50
- 0x23 2 0x1A 0x77
- 0x23 2 0x1B 0x57
- 0x23 2 0x1C 0x1F
- 0x23 2 0x1D 0x4E
- 0x23 2 0x1E 0x4C
- 0x23 2 0x1F 0x1F
- 0x23 2 0x20 0x4A
- 0x23 2 0x21 0x48
- 0x23 2 0x22 0x1F
- 0x23 2 0x23 0x46
- 0x23 2 0x24 0x44
- 0x23 2 0x25 0x40
- 0x23 2 0x26 0x1F
- 0x23 2 0x27 0x1F
- 0x23 2 0x28 0x1F
- 0x23 2 0x29 0x1F
- 0x23 2 0x2A 0x1F
- 0x23 2 0x2B 0x55
- 0x23 2 0x2C 0x12
- 0x23 2 0x2D 0x15
- 0x23 2 0x2E 0x15
- 0x23 2 0x2F 0x00
- 0x23 2 0x30 0x17
- 0x23 2 0x31 0x17
- 0x23 2 0x32 0x1F
- 0x23 2 0x33 0x08
- 0x23 2 0x34 0x0A
- 0x23 2 0x35 0x1F
- 0x23 2 0x36 0x0C
- 0x23 2 0x37 0x0E
- 0x23 2 0x38 0x1F
- 0x23 2 0x39 0x04
- 0x23 2 0x3A 0x06
- 0x23 2 0x3B 0x10
- 0x23 2 0x3C 0x1F
- 0x23 2 0x3D 0x1F
- 0x23 2 0x3E 0x1F
- 0x23 2 0x3F 0x15
- 0x23 2 0x40 0x1F
- 0x23 2 0x41 0x1F
- 0x23 2 0x42 0x13
- 0x23 2 0x43 0x15
- 0x23 2 0x44 0x15
- 0x23 2 0x45 0x01
- 0x23 2 0x46 0x17
- 0x23 2 0x47 0x17
- 0x23 2 0x48 0x1F
- 0x23 2 0x49 0x09
- 0x23 2 0x4A 0x0B
- 0x23 2 0x4B 0x1F
- 0x23 2 0x4C 0x0D
- 0x23 2 0x4D 0x0F
- 0x23 2 0x4E 0x1F
- 0x23 2 0x4F 0x05
- 0x23 2 0x50 0x07
- 0x23 2 0x51 0x11
- 0x23 2 0x52 0x1F
- 0x23 2 0x53 0x1F
- 0x23 2 0x54 0x1F
- 0x23 2 0x55 0x1F
- 0x23 2 0x56 0x1F
- 0x23 2 0x57 0x15
- 0x23 2 0x58 0x40
- 0x23 2 0x59 0x00
- 0x23 2 0x5A 0x00
- 0x23 2 0x5B 0x10
- 0x23 2 0x5C 0x14
- 0x23 2 0x5D 0x40
- 0x23 2 0x5E 0x01
- 0x23 2 0x5F 0x02
- 0x23 2 0x60 0x40
- 0x23 2 0x61 0x03
- 0x23 2 0x62 0x04
- 0x23 2 0x63 0x7A
- 0x23 2 0x64 0x7A
- 0x23 2 0x65 0x74
- 0x23 2 0x66 0x16
- 0x23 2 0x67 0xB4
- 0x23 2 0x68 0x16
- 0x23 2 0x69 0x7A
- 0x23 2 0x6A 0x7A
- 0x23 2 0x6B 0x0C
- 0x23 2 0x6C 0x00
- 0x23 2 0x6D 0x04
- 0x23 2 0x6E 0x04
- 0x23 2 0x6F 0x88
- 0x23 2 0x70 0x00
- 0x23 2 0x71 0x00
- 0x23 2 0x72 0x06
- 0x23 2 0x73 0x7B
- 0x23 2 0x74 0x00
- 0x23 2 0x75 0xBC
- 0x23 2 0x76 0x00
- 0x23 2 0x77 0x04
- 0x23 2 0x78 0x2C
- 0x23 2 0x79 0x00
- 0x23 2 0x7A 0x00
- 0x23 2 0x7B 0x00
- 0x23 2 0x7C 0x00
- 0x23 2 0x7D 0x03
- 0x23 2 0x7E 0x7B
- 0x23 2 0xE0 0x03
- 0x23 2 0xA9 0x02
- 0x23 2 0xAC 0x4D
- 0x23 2 0xE0 0x04
- 0x23 2 0x00 0x0E
- 0x23 2 0x02 0xB3
- 0x23 2 0x09 0x60
- 0x23 2 0x0E 0x48
- 0x23 2 0xE0 0x00
- 0x23 2 0x51 0xFF
- 0x23 2 0x53 0x2C
- 0x23 2 0x55 0x00
- 0x05 1 0x11
- 0xFF 125 /* Delay 125ms */
- 0x23 2 0xE0 0x01
- 0x23 2 0x35 0x24
- 0x23 2 0xE0 0x04
- 0x23 2 0x09 0x61
- 0x23 2 0xE0 0x00
- 0x05 1 0x29
- 0xFF 20 /* Delay 20ms */
- 0x23 2 0x35 0x00
- 0xFF 0xFF /* Ending */
- >;
- init_off = <
- 0xff 5
- 0x05 1 0x28 /* display off */
- 0xff 60 /* delay 60ms */
- 0x05 1 0x10 /* sleep in */
- 0xff 110 /* delay 110ms */
- 0xff 0xff>; /* ending */
- };
-
- extern_5{
- index = <5>;
- extern_name = "mipi_default"; // TV070WSM_ST7703I
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- cmd_size = <0xff>;
- init_on = <
- 0x29 4 0xB9 0xF1 0x12 0x83
- 0x29 4 0xB2 0x88 0x04 0xF0
- 0x29 11 0xB3 0x0C 0x0C 0x28 0x28 0x03 0xFF 0x00 0x00 0x00 0x00
- 0x23 2 0xB4 0xE0
- 0x29 3 0xB5 0x08 0x08
- 0x29 5 0xB8 0x25 0x22 0xF0 0x63
- 0x29 28 0xBA 0x33 0x81 0x05 0xF9 0x0E 0x0E 0x20 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x44 0x25 0x00 0x90 0x0A 0x00 0x00 0x01 0x4F 0x01 0x00 0x00 0x37
- 0x23 2 0xBC 0x47
- 0x29 4 0xBF 0x02 0x11 0x00
- 0x29 10 0xC0 0xFF 0xFF 0x50 0x50 0xA0 0x00 0x12 0xF0 0x00
- 0x29 13 0xC1 0x54 0xC0 0x32 0x32 0x77 0xF1 0xEF 0xEF 0xAE 0xAE 0x9E 0x9E
- 0x29 7 0xC6 0x02 0x00 0xFF 0xFF 0x08 0xFF
- 0x29 7 0xC7 0x10 0x00 0x0A 0x00 0x00 0x07
- 0x23 2 0xCC 0x0B
- 0x29 35 0xE0 0x00 0x09 0x0E 0x27 0x39 0x3F 0x41 0x37 0x06 0x0C 0x0E 0x12 0x14 0x12 0x13 0x10 0x18 0x00 0x09 0x0E 0x27 0x39 0x3F 0x41 0x37 0x06 0x0C 0x0E 0x12 0x14 0x12 0x13 0x10 0x18
- 0x29 35 0xCD 0x07 0x80 0x81 0x84 0x83 0x81 0x84 0x82 0x81 0x82 0x80 0x7F 0x80 0x80 0x80 0x81 0x81 0x80 0x7F 0x7E 0x7F 0x80 0x82 0x84 0x84 0x83 0x84 0x81 0x7E 0x83 0x7E 0x7C 0x80 0x83
- 0x29 34 0xCE 0x80 0x81 0x84 0x83 0x81 0x84 0x82 0x81 0x82 0x80 0x7F 0x80 0x80 0x80 0x81 0x81 0x80 0x7F 0x7E 0x7F 0x80 0x82 0x84 0x84 0x83 0x84 0x81 0x7E 0x83 0x7E 0x7C 0x80 0x83
- 0x29 34 0xCF 0x80 0x81 0x84 0x83 0x81 0x84 0x82 0x81 0x82 0x80 0x7F 0x80 0x80 0x80 0x81 0x81 0x80 0x7F 0x7E 0x7F 0x80 0x82 0x84 0x84 0x83 0x84 0x81 0x7E 0x83 0x7E 0x7C 0x80 0x83
- 0x29 15 0xE3 0x03 0x03 0x03 0x03 0x10 0x10 0x00 0x00 0x00 0x00 0x28 0x00 0xC0 0x10
- 0x29 64 0xE9 0xC2 0x10 0x01 0x00 0x00 0x80 0x81 0x12 0x31 0x23 0x21 0x80 0x80 0x81 0x23 0x24 0x00 0x00 0x30 0x00 0x00 0x00 0x00 0x00 0x30 0x00 0x00 0x00 0x11 0x33 0x11 0x88 0x88 0x88 0x88 0x88 0x88 0x88 0x88 0x00 0x22 0x00 0x88 0x88 0x88 0x88 0x88 0x88 0x88 0x88 0x00 0x00 0x00 0x01 0x0D 0x80 0x81 0x14 0x00 0x00 0x00 0x00 0x00
- 0x29 62 0xEA 0x96 0x0C 0x02 0x02 0x02 0xB4 0x00 0x00 0x00 0x00 0x00 0x00 0x22 0x00 0x00 0x88 0x88 0x88 0x88 0x88 0x88 0x88 0x88 0x11 0x33 0x11 0x88 0x88 0x88 0x88 0x88 0x88 0x88 0x88 0x23 0x07 0x00 0x00 0xD6 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x10 0x00 0x01 0x10 0x00 0x00 0x00
- 0x05 1 0x11
- 0xff 150 /* Delay 150ms */
- 0x05 1 0x29
- 0xff 50 /* Delay 50ms */
- 0xff 0xff /* Ending */
- >;
- init_off = <
- 0xff 5
- 0x05 1 0x28 /* display off */
- 0xff 60 /* delay 60ms */
- 0x05 1 0x10 /* sleep in */
- 0xff 110 /* delay 110ms */
- 0xff 0xff>; /* ending */
- };
- };
-
- backlight{
- compatible = "amlogic, backlight-g12a";
- status = "okay";
- key_valid = <0>;
- pinctrl-names = "pwm_on","pwm_off";
- pinctrl-0 = <&pwm_f_pins2>;
- pinctrl-1 = <&bl_pwm_off_pins>;
- pinctrl_version = <2>; /* for uboot */
- bl_pwm_config = <&bl_pwm_conf>;
- bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH
- &gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
- bl_gpio_names = "GPIOH_4","GPIOH_5";
-
- /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/
- /* power index:(point gpios_index, 0xff=invalid)
- * power value:(0=output low, 1=output high, 2=input)
- * power delay:(unit in ms)
- */
-
- backlight_0{
- index = <0>;
- bl_name = "backlight_pwm";
- bl_level_default_uboot_kernel = <100 100>;
- bl_level_attr = <255 10 /*max, min*/
- 128 128>; /*mid, mid_mapping*/
- bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */
- bl_power_attr = <0 /*en_gpio_index*/
- 1 0 /*on_value, off_value*/
- 200 200>; /*on_delay(ms), off_delay(ms)*/
- bl_pwm_port = "PWM_F";
- bl_pwm_attr = <0 /*pwm_method*/
- 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/
- 100 25>; /*duty_max(%), duty_min(%)*/
- bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/
- 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/
- bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */
- };
- backlight_1{
- index = <1>;
- bl_name = "bl_extern";
- bl_level_default_uboot_kernel = <100 100>;
- bl_level_attr = <255 10 /*max, min*/
- 128 128>; /*mid, mid_mapping*/
- bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/
- bl_power_attr = <1 /*en_gpio_index*/
- 1 0 /*on_value, off_value*/
- 200 200>; /*on_delay(ms), off_delay(ms)*/
- bl_extern_index = <0>;
- };
- };
- bl_pwm_conf:bl_pwm_conf{
- pwm_channel_0 {
- pwm_port_index = <5>;
- pwms = <&pwm_ef MESON_PWM_1 30040 0>;
- };
- };
-
- bl_extern{
- compatible = "amlogic, bl_extern";
- status = "disabled";
- i2c_bus = "i2c_bus_3";
-
- extern_0{
- index = <0>;
- extern_name = "i2c_lp8556";
- type = <0>; /*0=i2c, 1=spi, 2=mipi*/
- i2c_address = <0x2c>; /*7bit i2c address*/
- dim_max_min = <255 10>;
- };
-
- extern_1{
- index = <1>;
- extern_name = "mipi_lt070me05";
- type = <2>; /*0=i2c, 1=spi, 2=mipi*/
- dim_max_min = <255 10>;
- };
- };
-};/* end of panel */
diff --git a/arch/arm/dts/elaine-p0-panel.dtsi b/arch/arm/dts/elaine-p0-panel.dtsi
deleted file mode 100755
index dbbbf62..0000000
--- a/arch/arm/dts/elaine-p0-panel.dtsi
+++ /dev/null
@@ -1,1169 +0,0 @@
-/*
- * arch/arm64/boot/dts/amlogic/estelle-sm1-panel.dtsi
- *
- * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-/ {
- lcd{
- compatible = "amlogic, lcd-sm1";
- mode = "tablet";
- status = "okay";
- key_valid = <0>;
- clocks = <&clkc CLKID_MIPI_DSI_HOST
- &clkc CLKID_MIPI_DSI_PHY
- &clkc CLKID_DSI_MEAS_COMP
- &clkc CLKID_VCLK2_ENCL
- &clkc CLKID_VCLK2_VENCL
- &clkc CLKID_GP0_PLL>;
- clock-names = "dsi_host_gate",
- "dsi_phy_gate",
- "dsi_meas",
- "encl_top_gate",
- "encl_int_gate",
- "gp0_pll";
- reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */
- 0x0 0xff644000 0x0 0x200>; /* dsi_phy */
- interrupts = <0 3 1
- 0 56 1>;
- interrupt-names = "vsync","vsync2";
- pinctrl_version = <2>; /* for uboot */
-
- /* power type:
- * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending)
- * power index:
- * (point gpios_index, or extern_index,0xff=invalid)
- * power value:(0=output low, 1=output high, 2=input)
- * power delay:(unit in ms)
- */
- lcd_cpu-gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
- lcd_cpu_gpio_names = "GPIOH_6";
-
- lcd_1{
- model_name = "TV070WSM";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 700 1053 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 95 163>; /*screen_widht, screen_height*/
- lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/
- 2 8 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 44250000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 360 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_always_hs(0=disable,1=enable)*/
- 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10 /* delay 10 ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 4 3 /* mipi state check */
- 0xff 10 /* delay 10 ms */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <1>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 50
- 0 0 0 100
- 0xff 0 0 0>;
- backlight_index = <0>;
- };
-
- lcd_2{
- model_name = "P070ACB";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 680 1194 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 3 5>; /*screen_widht, screen_height*/
- lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/
- 10 80 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 48715200>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 400 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_always_hs(0=disable,1=enable)*/
- 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10 /* delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 4 3 /* mipi state check */
- 0xff 10 /* delay 10 ms */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <2>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 50
- 0 0 0 100
- 0xff 0 0 0>;
- backlight_index = <1>;
- };
-
- lcd_3{
- model_name = "TV070WSM_FT";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 700 1053 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 95 163>; /*screen_widht, screen_height*/
- lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/
- 2 8 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 48715200>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 400 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_always_hs(0=disable,1=enable)*/
- 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 0x04 3 /* check_reg, check_cnt */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <3>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 0 1 0 200
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 0
- 0 0 0 20
- 0 1 1 100
- 0xff 0 0 0>;
- backlight_index = <0>;
- };
-
- lcd_4{
- model_name = "P070ACB_FT";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 770 1070 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 3 5>; /*screen_widht, screen_height*/
- lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/
- 6 20 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 49434000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 400 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_always_hs(0=disable,1=enable)*/
- 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 0x04 3 /* check_reg, check_cnt */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <4>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 0 1 0 200 /* panel power on */
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 0
- 0 0 0 20 /* reset low */
- 0 1 1 100 /* panel power off */
- 0xff 0 0 0>;
- backlight_index = <0>;
- };
- };
-
- lcd_extern{
- compatible = "amlogic, lcd_extern";
- dev_name = "lcd_extern";
- status = "okay";
- key_valid = <0>;
-
- extern_1{
- index = <1>;
- extern_name = "mipi_default"; //TV070WSM
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- cmd_size = <0xff>;
- init_on = <
- 0xfd 1 100 /* delay */
- 0x15 2 0x62 0x01
- 0x39 5 0xff 0xaa 0x55 0x25 0x01
- 0x15 2 0xfc 0x08
- 0xff 1 /* delay */
- 0x15 2 0xfc 0x00
- 0x39 5 0xff 0xaa 0x55 0x25 0x00
- 0xff 20 /* delay */
- 0x39 6 0xf0 0x55 0xaa 0x52 0x08 0x00
- 0x39 3 0xb1 0x68 0x41
- 0x15 2 0xb5 0x88
- 0x15 2 0xb6 0x0f
- 0x39 5 0xb8 0x01 0x01 0x12 0x01
- 0x39 3 0xbb 0x11 0x11
- 0x39 3 0xbc 0x05 0x05
- 0x15 2 0xc7 0x03
- 0x39 6 0xbd 0x03 0x02 0x19 0x17 0x00
- 0x15 2 0xc8 0x80
- 0x39 6 0xf0 0x55 0xaa 0x52 0x08 0x01
- 0x39 3 0xB2 0x01 0x01
- 0x39 3 0xB3 0x28 0x28
- 0x39 3 0xB4 0x14 0x14
- 0x39 3 0xB8 0x05 0x05
- 0x39 3 0xB9 0x45 0x45
- 0x39 3 0xBA 0x25 0x25
- 0x39 3 0xBC 0x88 0x00
- 0x39 3 0xBD 0x88 0x00
- 0x39 6 0xF0 0x55 0xAA 0x52 0x08 0x02
- 0x15 2 0xEE 0x00
- 0x39 17 0xB0 0x00 0x4B 0x00 0x5C 0x00 0x79 0x00 0x94 0x00 0xA6 0x00 0xD8 0x00 0xF2 0x01 0x19
- 0x39 17 0xB1 0x01 0x39 0x01 0x77 0x01 0xA2 0x01 0xF2 0x02 0x32 0x02 0x34 0x02 0x6D 0x02 0xA2
- 0x39 17 0xB2 0x02 0xC7 0x02 0xF2 0x03 0x18 0x03 0x43 0x03 0x65 0x03 0x86 0x03 0x8F 0x03 0x94
- 0x39 5 0xB3 0x03 0x96 0x03 0x98
- 0x39 17 0xB4 0x00 0x84 0x00 0x91 0x00 0xA4 0x00 0xB6 0x00 0xCA 0x00 0xE9 0x01 0x02 0x01 0x2A
- 0x39 17 0xB5 0x01 0x49 0x01 0x82 0x01 0xAF 0x01 0xF7 0x02 0x36 0x02 0x38 0x02 0x70 0x02 0xA6
- 0x39 17 0xB6 0x02 0xC8 0x02 0xF5 0x03 0x1A 0x03 0x43 0x03 0x62 0x03 0x82 0x03 0x8F 0x03 0x94
- 0x39 5 0xB7 0x03 0x96 0x03 0x98
- 0x39 17 0xB8 0x01 0x22 0x01 0x27 0x01 0x2E 0x01 0x38 0x01 0x40 0x01 0x53 0x01 0x60 0x01 0x7B
- 0x39 17 0xB9 0x01 0x8C 0x01 0xB5 0x01 0xD3 0x02 0x11 0x02 0x49 0x02 0x4A 0x02 0x7F 0x02 0xB1
- 0x39 17 0xBA 0x02 0xD1 0x03 0x00 0x03 0x22 0x03 0x49 0x03 0x60 0x03 0x7A 0x03 0x8B 0x03 0x8F
- 0x39 5 0xBB 0x03 0x93 0x03 0x9A
- 0x39 17 0xBC 0x00 0x37 0x00 0x48 0x00 0x65 0x00 0x80 0x00 0x92 0x00 0xC4 0x00 0xDE 0x01 0x05
- 0x39 17 0xBD 0x01 0x31 0x01 0x6F 0x01 0x9E 0x01 0xEE 0x02 0x32 0x02 0x34 0x02 0x71 0x02 0xA7
- 0x39 17 0xBE 0x02 0xD3 0x02 0xFE 0x03 0x24 0x03 0x4F 0x03 0x71 0x03 0x92 0x03 0x9B 0x03 0xA0
- 0x39 5 0xBF 0x03 0xA6 0x03 0xA8
- 0x39 17 0xC0 0x00 0x70 0x00 0x7D 0x00 0x90 0x00 0xA4 0x00 0xB6 0x00 0xD5 0x00 0xEE 0x01 0x16
- 0x39 17 0xC1 0x01 0x41 0x01 0x7A 0x01 0xAB 0x01 0xF3 0x02 0x36 0x02 0x38 0x02 0x74 0x02 0xAA
- 0x39 17 0xC2 0x02 0xD4 0x03 0x01 0x03 0x26 0x03 0x4F 0x03 0x6E 0x03 0x8E 0x03 0x9B 0x03 0xA0
- 0x39 5 0xC3 0x03 0xA6 0x03 0xA8
- 0x39 17 0xC4 0x01 0x0E 0x01 0x13 0x01 0x1A 0x01 0x24 0x01 0x2C 0x01 0x3F 0x01 0x4C 0x01 0x67
- 0x39 17 0xC5 0x01 0x84 0x01 0xAD 0x01 0xCF 0x02 0x0D 0x02 0x49 0x02 0x4A 0x02 0x83 0x02 0xB5
- 0x39 17 0xC6 0x02 0xDD 0x03 0x0C 0x03 0x2E 0x03 0x55 0x03 0x6B 0x03 0x86 0x03 0x97 0x03 0x9B
- 0x39 5 0xC7 0x03 0xA1 0x03 0xA8
- 0x39 6 0xF0 0x55 0xAA 0x52 0x08 0x04
- 0x39 6 0xB1 0x03 0x02 0x02 0x02 0x00
- 0x39 6 0xF0 0x55 0xAA 0x52 0x08 0x06
- 0x39 3 0xB0 0x11 0x11
- 0x39 3 0xB1 0x13 0x13
- 0x39 3 0xB2 0x03 0x03
- 0x39 3 0xB3 0x34 0x34
- 0x39 3 0xB4 0x34 0x34
- 0x39 3 0xB5 0x34 0x34
- 0x39 3 0xB6 0x34 0x34
- 0x39 3 0xB7 0x34 0x34
- 0x39 3 0xB8 0x34 0x34
- 0x39 3 0xB9 0x34 0x34
- 0x39 3 0xBA 0x34 0x34
- 0x39 3 0xBB 0x34 0x34
- 0x39 3 0xBC 0x34 0x34
- 0x39 3 0xBD 0x34 0x34
- 0x39 3 0xBE 0x34 0x34
- 0x39 3 0xBF 0x34 0x34
- 0x39 3 0xC0 0x34 0x34
- 0x39 3 0xC1 0x02 0x02
- 0x39 3 0xC2 0x12 0x12
- 0x39 3 0xC3 0x10 0x10
- 0x39 3 0xE5 0x34 0x34
- 0x39 6 0xD8 0x00 0x00 0x00 0x00 0x00
- 0x39 6 0xD9 0x00 0x00 0x00 0x00 0x00
- 0x39 6 0xF0 0x55 0xAA 0x52 0x08 0x05
- 0x15 2 0xC0 0x03
- 0x15 2 0xC1 0x02
- 0x39 3 0xC8 0x01 0x20
- 0x15 2 0xE5 0x03
- 0x15 2 0xE6 0x03
- 0x15 2 0xE7 0x03
- 0x15 2 0xE8 0x03
- 0x15 2 0xE9 0x03
- 0x39 5 0xD1 0x03 0x00 0x3D 0x00
- 0x39 6 0xF0 0x55 0xAA 0x52 0x08 0x03
- 0x39 3 0xB0 0x11 0x00
- 0x39 3 0xB1 0x11 0x00
- 0x39 6 0xB2 0x03 0x00 0x00 0x00 0x00
- 0x39 6 0xB3 0x03 0x00 0x00 0x00 0x00
- 0x39 6 0xBA 0x31 0x00 0x00 0x00 0x00
- 0x15 2 0x35 0x00
- 0x15 2 0x51 0xFF
- 0x15 2 0x53 0x2C
- 0x15 2 0x55 0x03
- 0x05 1 0x11
- 0xfd 1 120 /* delay 120ms */
- 0x05 1 0x29
- 0xff 0xff /* ending */
- >;
- init_off = <
- 0x05 1 0x28 /* display off */
- 0xff 10 /* delay 10ms */
- 0x05 1 0x10 /* sleep in */
- 0xff 150 /* delay 150ms */
- 0xff 0xff>; /*ending*/
- };
-
- extern_2{
- index = <2>;
- extern_name = "mipi_default"; //P070ACB
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- cmd_size = <0xff>;
- init_on = <
- 0xfd 1 100 /* delay */
- 0x15 2 0x62 0x01
- 0x29 5 0xFF 0xAA 0x55 0x25 0x01
- 0x23 2 0xFC 0x08
- 0xfd 1 1 /* delay(ms) */
- 0x23 2 0xFC 0x00
-
- 0xfd 1 1 /* delay(ms) */
- 0x23 2 0x6F 0x21
- 0x23 2 0xF7 0x01
- 0xfd 1 1 /* delay(ms) */
- 0x23 2 0x6F 0x21
- 0x23 2 0xF7 0x00
- 0xfd 1 1 /* delay(ms) */
-
- 0x23 2 0x6F 0x1A
- 0x23 2 0xF7 0x05
- 0xfd 1 1 /* delay(ms) */
-
- 0x29 5 0xFF 0xAA 0x55 0x25 0x00
-
- 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00
- 0x29 3 0xB1 0x68 0x41
- 0x23 2 0xB5 0x88
- 0x29 6 0xBD 0x02 0xB0 0x0C 0x14 0x00
- 0x23 2 0xC8 0x80
-
- 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01
- 0x29 3 0xB3 0x2D 0x2D
- 0x29 3 0xB4 0x19 0x19
- 0x23 2 0xB5 0x06
-
- 0x29 3 0xB9 0x36 0x36
- 0x29 3 0xBA 0x26 0x26
- 0x29 3 0xBC 0xA8 0x01
- 0x29 3 0xBD 0xAB 0x01
- 0x23 2 0xC0 0x0C
-
- 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x02
- 0x23 2 0xEE 0x02
- 0x29 7 0xB0 0x00 0x50 0x00 0x52 0x00 0x73
- 0x23 2 0x6F 0x06
- 0x29 7 0xB0 0x00 0x8F 0x00 0xA5 0x00 0xCA
- 0x23 2 0x6F 0x0C
- 0x29 5 0xB0 0x00 0xEA 0x01 0x1B
- 0x29 7 0xB1 0x01 0x42 0x01 0x82 0x01 0xB3
- 0x23 2 0x6F 0x06
- 0x29 7 0xB1 0x02 0x00 0x02 0x41 0x02 0x42
- 0x23 2 0x6F 0x0C
- 0x29 5 0xB1 0x02 0x78 0x02 0xB5
- 0x29 7 0xB2 0x02 0xDA 0x03 0x12 0x03 0x3A
- 0x23 2 0x6F 0x06
- 0x29 7 0xB2 0x03 0x6E 0x03 0x8D 0x03 0xB1
- 0x23 2 0x6F 0x0C
- 0x29 5 0xB2 0x03 0xCA 0x03 0xE8
- 0x29 5 0xB3 0x03 0xF4 0x03 0xFF
-
- 0x29 7 0xBC 0x00 0x05 0x00 0x52 0x00 0x73
- 0x23 2 0x6F 0x06
- 0x29 7 0xBC 0x00 0x8F 0x00 0xA5 0x00 0xCA
- 0x23 2 0x6F 0x0C
- 0x29 5 0xBC 0x00 0xEA 0x01 0x1B
- 0x29 7 0xBD 0x01 0x42 0x01 0x82 0x01 0xB3
- 0x23 2 0x6F 0x06
- 0x29 7 0xBD 0x02 0x00 0x02 0x41 0x02 0x42
- 0x23 2 0x6F 0x0C
- 0x29 5 0xBD 0x02 0x78 0x02 0xB5
- 0x29 7 0xBE 0x02 0xDA 0x03 0x12 0x03 0x3A
- 0x23 2 0x6F 0x06
- 0x29 7 0xBE 0x03 0x6E 0x03 0x8D 0x03 0xB1
- 0x23 2 0x6F 0x0C
- 0x29 5 0xBE 0x03 0xCA 0x03 0xE8
- 0x29 5 0xBF 0x03 0xF4 0x03 0xFF
-
- 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03
- 0x29 6 0xB2 0x05 0x00 0x00 0x00 0x00
- 0x29 6 0xB6 0x05 0x00 0x00 0x00 0x00
- 0x29 6 0xB7 0x05 0x00 0x00 0x00 0x00
- 0x29 6 0xBA 0x57 0x00 0x00 0x00 0x00
- 0x29 6 0xBB 0x57 0x00 0x00 0x00 0x00
- 0x29 5 0xC0 0x00 0x34 0x00 0x00
- 0x29 5 0xC1 0x00 0x00 0x34 0x00
- 0x23 2 0xC4 0x40
-
- 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x05
- 0x29 3 0xB0 0x17 0x06
- 0x29 3 0xB1 0x17 0x06
- 0x29 3 0xB2 0x17 0x06
- 0x29 3 0xB3 0x17 0x06
- 0x29 3 0xB4 0x17 0x06
-
- 0x29 6 0xBD 0x03 0x01 0x03 0x03 0x01
- 0x23 2 0xC0 0x05
- 0x23 2 0xC4 0x82
- 0x23 2 0xC5 0xA2
- 0x29 3 0xC8 0x03 0x30
- 0x29 3 0xC9 0x03 0x31
- 0x29 4 0xCC 0x00 0x00 0x3C
- 0x29 4 0xCD 0x00 0x00 0x3C
- 0x29 6 0xD1 0x00 0x44 0x09 0x00 0x00
- 0x29 6 0xD2 0x00 0x04 0x0B 0x00 0x00
-
- 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x06
- 0x29 3 0xB0 0x0B 0x2D
- 0x29 3 0xB1 0x2D 0x09
- 0x29 3 0xB2 0x2A 0x29
- 0x29 3 0xB3 0x34 0x1B
- 0x29 3 0xB4 0x19 0x17
- 0x29 3 0xB5 0x15 0x13
- 0x29 3 0xB6 0x11 0x01
- 0x29 3 0xB7 0x34 0x34
- 0x29 3 0xB8 0x34 0x2D
- 0x29 3 0xB9 0x2D 0x34
- 0x29 3 0xBA 0x2D 0x2D
- 0x29 3 0xBB 0x34 0x34
- 0x29 3 0xBC 0x34 0x34
- 0x29 3 0xBD 0x00 0x10
- 0x29 3 0xBE 0x12 0x14
- 0x29 3 0xBF 0x16 0x18
-
- 0x29 3 0xC0 0x1A 0x34
- 0x29 3 0xC1 0x29 0x2A
- 0x29 3 0xC2 0x08 0x2D
- 0x29 3 0xC3 0x2D 0x0A
- 0x29 3 0xC4 0x0A 0x2D
- 0x29 3 0xC5 0x2D 0x00
- 0x29 3 0xC6 0x2A 0x29
- 0x29 3 0xC7 0x34 0x14
- 0x29 3 0xC8 0x16 0x18
- 0x29 3 0xC9 0x1A 0x10
- 0x29 3 0xCA 0x12 0x08
- 0x29 3 0xCB 0x34 0x34
- 0x29 3 0xCC 0x34 0x2D
- 0x29 3 0xCD 0x2D 0x34
- 0x29 3 0xCE 0x2D 0x2D
- 0x29 3 0xCF 0x34 0x34
-
- 0x29 3 0xD0 0x34 0x34
- 0x29 3 0xD1 0x09 0x13
- 0x29 3 0xD2 0x11 0x1B
- 0x29 3 0xD3 0x19 0x17
- 0x29 3 0xD4 0x15 0x34
- 0x29 3 0xD5 0x29 0x2A
- 0x29 3 0xD6 0x01 0x2D
- 0x29 3 0xD7 0x2D 0x0B
- 0x29 6 0xD8 0x00 0x00 0x00 0x00 0x00
- 0x29 6 0xD9 0x00 0x00 0x00 0x00 0x00
-
- 0x29 3 0xE5 0x34 0x34
- 0x29 3 0xE6 0x34 0x34
- 0x23 2 0xE7 0x00
- 0x29 3 0xE8 0x34 0x34
- 0x29 3 0xE9 0x34 0x34
- 0x23 2 0xEA 0x00
-
- 0x29 6 0xF0 0x55 0xAA 0x52 0x00 0x00
-
- 0x13 1 0x35
- 0x13 1 0x11
- 0xfd 1 120 /* delay(ms) */
- 0x13 1 0x29
- 0xfd 1 20 /* delay(ms) */
- 0xff 0 /* ending */
- >;
- init_off = <
- 0x05 1 0x28 /* display off */
- 0xff 10 /* delay 10ms */
- 0x05 1 0x10 /* sleep in */
- 0xff 150 /* delay 150ms */
- 0xff 0xff>; /*ending*/
- };
-
- extern_3{
- index = <3>;
- extern_name = "mipi_default"; //TV070WSM_FT
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- cmd_size = <0xff>;
- init_on = <
- 0x23 2 0xE0 0x00
- 0x23 2 0xE1 0x93
- 0x23 2 0xE2 0x65
- 0x23 2 0xE3 0xF8
- 0x23 2 0xE0 0x01
- 0x23 2 0x00 0x00
- 0x23 2 0x01 0x90
- 0x23 2 0x03 0x00
- 0x23 2 0x04 0x90
- 0x23 2 0x17 0x00
- 0x23 2 0x18 0xB0
- 0x23 2 0x19 0x01
- 0x23 2 0x1A 0x00
- 0x23 2 0x1B 0xB0
- 0x23 2 0x1C 0x01
- 0x23 2 0x1F 0x3E
- 0x23 2 0x20 0x2F
- 0x23 2 0x21 0x2F
- 0x23 2 0x22 0x0E
- 0x23 2 0x37 0x69
- 0x23 2 0x38 0x05
- 0x23 2 0x39 0x00
- 0x23 2 0x3A 0x01
- 0x23 2 0x3C 0x90
- 0x23 2 0x3D 0xFF
- 0x23 2 0x3E 0xFF
- 0x23 2 0x3F 0xFF
- 0x23 2 0x40 0x02
- 0x23 2 0x41 0x80
- 0x23 2 0x42 0x99
- 0x23 2 0x43 0x06
- 0x23 2 0x44 0x09
- 0x23 2 0x45 0x3C
- 0x23 2 0x4B 0x04
- 0x23 2 0x55 0x0D
- 0x23 2 0x56 0x01
- 0x23 2 0x57 0x89
- 0x23 2 0x58 0x0A
- 0x23 2 0x59 0x0A
- 0x23 2 0x5A 0x27
- 0x23 2 0x5B 0x15
- 0x23 2 0x5D 0x7C
- 0x23 2 0x5E 0x67
- 0x23 2 0x5F 0x58
- 0x23 2 0x60 0x4C
- 0x23 2 0x61 0x48
- 0x23 2 0x62 0x38
- 0x23 2 0x63 0x3C
- 0x23 2 0x64 0x24
- 0x23 2 0x65 0x3B
- 0x23 2 0x66 0x38
- 0x23 2 0x67 0x36
- 0x23 2 0x68 0x53
- 0x23 2 0x69 0x3F
- 0x23 2 0x6A 0x44
- 0x23 2 0x6B 0x35
- 0x23 2 0x6C 0x2E
- 0x23 2 0x6D 0x1F
- 0x23 2 0x6E 0x0C
- 0x23 2 0x6F 0x00
- 0x23 2 0x70 0x7C
- 0x23 2 0x71 0x67
- 0x23 2 0x72 0x58
- 0x23 2 0x73 0x4C
- 0x23 2 0x74 0x48
- 0x23 2 0x75 0x38
- 0x23 2 0x76 0x3C
- 0x23 2 0x77 0x24
- 0x23 2 0x78 0x3B
- 0x23 2 0x79 0x38
- 0x23 2 0x7A 0x36
- 0x23 2 0x7B 0x53
- 0x23 2 0x7C 0x3F
- 0x23 2 0x7D 0x44
- 0x23 2 0x7E 0x35
- 0x23 2 0x7F 0x2E
- 0x23 2 0x80 0x1F
- 0x23 2 0x81 0x0C
- 0x23 2 0x82 0x00
- 0x23 2 0xE0 0x02
- 0x23 2 0x00 0x45
- 0x23 2 0x01 0x45
- 0x23 2 0x02 0x47
- 0x23 2 0x03 0x47
- 0x23 2 0x04 0x41
- 0x23 2 0x05 0x41
- 0x23 2 0x06 0x1F
- 0x23 2 0x07 0x1F
- 0x23 2 0x08 0x1F
- 0x23 2 0x09 0x1F
- 0x23 2 0x0A 0x1F
- 0x23 2 0x0B 0x1F
- 0x23 2 0x0C 0x1F
- 0x23 2 0x0D 0x1D
- 0x23 2 0x0E 0x1D
- 0x23 2 0x0F 0x1D
- 0x23 2 0x10 0x1F
- 0x23 2 0x11 0x1F
- 0x23 2 0x12 0x1F
- 0x23 2 0x13 0x1F
- 0x23 2 0x14 0x1F
- 0x23 2 0x15 0x1F
- 0x23 2 0x16 0x44
- 0x23 2 0x17 0x44
- 0x23 2 0x18 0x46
- 0x23 2 0x19 0x46
- 0x23 2 0x1A 0x40
- 0x23 2 0x1B 0x40
- 0x23 2 0x1C 0x1F
- 0x23 2 0x1D 0x1F
- 0x23 2 0x1E 0x1F
- 0x23 2 0x1F 0x1F
- 0x23 2 0x20 0x1F
- 0x23 2 0x21 0x1F
- 0x23 2 0x22 0x1F
- 0x23 2 0x23 0x1D
- 0x23 2 0x24 0x1D
- 0x23 2 0x25 0x1D
- 0x23 2 0x26 0x1F
- 0x23 2 0x27 0x1F
- 0x23 2 0x28 0x1F
- 0x23 2 0x29 0x1F
- 0x23 2 0x2A 0x1F
- 0x23 2 0x2B 0x1F
- 0x23 2 0x58 0x40
- 0x23 2 0x59 0x00
- 0x23 2 0x5A 0x00
- 0x23 2 0x5B 0x10
- 0x23 2 0x5C 0x06
- 0x23 2 0x5D 0x20
- 0x23 2 0x5E 0x00
- 0x23 2 0x5F 0x00
- 0x23 2 0x61 0x00
- 0x23 2 0x62 0x00
- 0x23 2 0x63 0x7A
- 0x23 2 0x64 0x7A
- 0x23 2 0x65 0x00
- 0x23 2 0x66 0x00
- 0x23 2 0x67 0x32
- 0x23 2 0x68 0x08
- 0x23 2 0x69 0x7A
- 0x23 2 0x6A 0x7A
- 0x23 2 0x6B 0x00
- 0x23 2 0x6C 0x00
- 0x23 2 0x6D 0x04
- 0x23 2 0x6E 0x04
- 0x23 2 0x6F 0x88
- 0x23 2 0x70 0x00
- 0x23 2 0x71 0x00
- 0x23 2 0x72 0x06
- 0x23 2 0x73 0x7B
- 0x23 2 0x74 0x00
- 0x23 2 0x75 0x07
- 0x23 2 0x76 0x00
- 0x23 2 0x77 0x5D
- 0x23 2 0x78 0x17
- 0x23 2 0x79 0x1F
- 0x23 2 0x7A 0x00
- 0x23 2 0x7B 0x00
- 0x23 2 0x7C 0x00
- 0x23 2 0x7D 0x03
- 0x23 2 0x7E 0x7B
- 0x23 2 0xE0 0x03
- 0x23 2 0xAF 0x20
- 0x23 2 0xE0 0x04
- 0x23 2 0x09 0x11
- 0x23 2 0x0E 0x48
- 0x23 2 0x2B 0x2B
- 0x23 2 0x2E 0x44
- 0x23 2 0x41 0xFF
- 0x23 2 0xE0 0x00
- 0x23 2 0xE6 0x02
- 0x23 2 0xE7 0x0C
- 0x05 1 0x11
- 0xff 120 /* delay 120ms */
-
- 0x23 2 0xE0 0x03
- 0x23 2 0x2B 0x01
- 0x23 2 0x2C 0x00
- 0x23 2 0x30 0x03
- 0x23 2 0x31 0xCC
- 0x23 2 0x32 0x03
- 0x23 2 0x33 0xC9
- 0x23 2 0x34 0x03
- 0x23 2 0x35 0xC0
- 0x23 2 0x36 0x03
- 0x23 2 0x37 0xB3
- 0x23 2 0x38 0x03
- 0x23 2 0x39 0xAB
- 0x23 2 0x3A 0x03
- 0x23 2 0x3B 0x9D
- 0x23 2 0x3C 0x03
- 0x23 2 0x3D 0x8F
- 0x23 2 0x3E 0x03
- 0x23 2 0x3F 0x6D
- 0x23 2 0x40 0x03
- 0x23 2 0x41 0x51
- 0x23 2 0x42 0x03
- 0x23 2 0x43 0x17
- 0x23 2 0x44 0x02
- 0x23 2 0x45 0xD8
- 0x23 2 0x46 0x02
- 0x23 2 0x47 0x60
- 0x23 2 0x48 0x01
- 0x23 2 0x49 0xEB
- 0x23 2 0x4A 0x01
- 0x23 2 0x4B 0xE5
- 0x23 2 0x4C 0x01
- 0x23 2 0x4D 0x6C
- 0x23 2 0x4E 0x00
- 0x23 2 0x4F 0xF2
- 0x23 2 0x50 0x00
- 0x23 2 0x51 0xB4
- 0x23 2 0x52 0x00
- 0x23 2 0x53 0x74
- 0x23 2 0x54 0x00
- 0x23 2 0x55 0x54
- 0x23 2 0x56 0x00
- 0x23 2 0x57 0x34
- 0x23 2 0x58 0x00
- 0x23 2 0x59 0x26
- 0x23 2 0x5A 0x00
- 0x23 2 0x5B 0x18
- 0x23 2 0x5C 0x00
- 0x23 2 0x5D 0x11
- 0x23 2 0x5E 0x00
- 0x23 2 0x5F 0x0A
- 0x23 2 0x60 0x00
- 0x23 2 0x61 0x03
- 0x23 2 0x62 0x00
- 0x23 2 0x63 0x00
- 0x23 2 0x64 0x03
- 0x23 2 0x65 0x9E
- 0x23 2 0x66 0x03
- 0x23 2 0x67 0x9B
- 0x23 2 0x68 0x03
- 0x23 2 0x69 0x94
- 0x23 2 0x6A 0x03
- 0x23 2 0x6B 0x8C
- 0x23 2 0x6C 0x03
- 0x23 2 0x6D 0x85
- 0x23 2 0x6E 0x03
- 0x23 2 0x6F 0x76
- 0x23 2 0x70 0x03
- 0x23 2 0x71 0x67
- 0x23 2 0x72 0x03
- 0x23 2 0x73 0x4B
- 0x23 2 0x74 0x03
- 0x23 2 0x75 0x2E
- 0x23 2 0x76 0x02
- 0x23 2 0x77 0xF7
- 0x23 2 0x78 0x02
- 0x23 2 0x79 0xB8
- 0x23 2 0x7A 0x02
- 0x23 2 0x7B 0x46
- 0x23 2 0x7C 0x01
- 0x23 2 0x7D 0xD6
- 0x23 2 0x7E 0x01
- 0x23 2 0x7F 0xD0
- 0x23 2 0x80 0x01
- 0x23 2 0x81 0x5C
- 0x23 2 0x82 0x00
- 0x23 2 0x83 0xE7
- 0x23 2 0x84 0x00
- 0x23 2 0x85 0xAA
- 0x23 2 0x86 0x00
- 0x23 2 0x87 0x74
- 0x23 2 0x88 0x00
- 0x23 2 0x89 0x5A
- 0x23 2 0x8A 0x00
- 0x23 2 0x8B 0x3C
- 0x23 2 0x8C 0x00
- 0x23 2 0x8D 0x2C
- 0x23 2 0x8E 0x00
- 0x23 2 0x8F 0x1C
- 0x23 2 0x90 0x00
- 0x23 2 0x91 0x14
- 0x23 2 0x92 0x00
- 0x23 2 0x93 0x0C
- 0x23 2 0x94 0x00
- 0x23 2 0x95 0x04
- 0x23 2 0x96 0x00
- 0x23 2 0x97 0x00
- 0x23 2 0xE0 0x00
- 0x05 1 0x29
- 0xff 5
- 0xff 0xff /* ending flag */
- >;
- init_off = <
- 0xff 5
- 0x05 1 0x28 /* display off */
- 0xff 30 /* delay 10ms */
- 0x05 1 0x10 /* sleep in */
- 0xff 10 /* delay 150ms */
- 0xff 0xff>; /*ending*/
- };
-
- extern_4{
- index = <4>;
- extern_name = "mipi_default";/*P070ACB_FT*/
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- cmd_size = <0xff>;
- init_on = <
- 0x23 2 0xE0 0x00 /* Page 0 */
- 0x23 2 0xE1 0x93 /* PASSWORD */
- 0x23 2 0xE2 0x65
- 0x23 2 0xE3 0xF8
- 0x23 2 0x80 0x03
- 0x23 2 0xE0 0x01 /* Page 01 */
- 0x23 2 0x0C 0x74 /* Set PWRIC */
- 0x23 2 0x17 0x00 /* Set Gamma Power */
- 0x23 2 0x18 0xEF /* VGMP=5.1V */
- 0x23 2 0x19 0x00
- 0x23 2 0x1A 0x00
- 0x23 2 0x1B 0xEF /* VGMN=-5.1V */
- 0x23 2 0x1C 0x00
- 0x23 2 0x1F 0x70 /* Set Gate Power */
- 0x23 2 0x20 0x2D
- 0x23 2 0x21 0x2D
- 0x23 2 0x22 0x7E
- 0x23 2 0x26 0xF3 /* VDDD from IOVCC */
- 0x23 2 0x37 0x09 /* SetPanel */
- 0x23 2 0x38 0x04 /* SET RGBCYC */
- 0x23 2 0x39 0x00
- 0x23 2 0x3A 0x01
- 0x23 2 0x3C 0x90
- 0x23 2 0x3D 0xFF
- 0x23 2 0x3E 0xFF
- 0x23 2 0x3F 0xFF
- 0x23 2 0x40 0x02 /* Set TCON */
- 0x23 2 0x41 0x80
- 0x23 2 0x42 0x99
- 0x23 2 0x43 0x14
- 0x23 2 0x44 0x19
- 0x23 2 0x45 0x5A
- 0x23 2 0x4B 0x04
- 0x23 2 0x55 0x02 /* power voltage */
- 0x23 2 0x56 0x01
- 0x23 2 0x57 0x69
- 0x23 2 0x58 0x0A
- 0x23 2 0x59 0x0A
- 0x23 2 0x5A 0x2E /* VGH = 16.2V */
- 0x23 2 0x5B 0x19 /* VGL = -12V */
- 0x23 2 0x5C 0x15
- 0x23 2 0x5D 0x77 /* Gamma */
- 0x23 2 0x5E 0x56
- 0x23 2 0x5F 0x45
- 0x23 2 0x60 0x38
- 0x23 2 0x61 0x35
- 0x23 2 0x62 0x27
- 0x23 2 0x63 0x2D
- 0x23 2 0x64 0x18
- 0x23 2 0x65 0x33
- 0x23 2 0x66 0x34
- 0x23 2 0x67 0x35
- 0x23 2 0x68 0x56
- 0x23 2 0x69 0x45
- 0x23 2 0x6A 0x4F
- 0x23 2 0x6B 0x42
- 0x23 2 0x6C 0x40
- 0x23 2 0x6D 0x34
- 0x23 2 0x6E 0x25
- 0x23 2 0x6F 0x02
- 0x23 2 0x70 0x77
- 0x23 2 0x71 0x56
- 0x23 2 0x72 0x45
- 0x23 2 0x73 0x38
- 0x23 2 0x74 0x35
- 0x23 2 0x75 0x27
- 0x23 2 0x76 0x2D
- 0x23 2 0x77 0x18
- 0x23 2 0x78 0x33
- 0x23 2 0x79 0x34
- 0x23 2 0x7A 0x35
- 0x23 2 0x7B 0x56
- 0x23 2 0x7C 0x45
- 0x23 2 0x7D 0x4F
- 0x23 2 0x7E 0x42
- 0x23 2 0x7F 0x40
- 0x23 2 0x80 0x34
- 0x23 2 0x81 0x25
- 0x23 2 0x82 0x02
- 0x23 2 0xE0 0x02 /* Page2 */
- 0x23 2 0x00 0x53
- /* GIP_L Pin mapping RESET_EVEN */
- 0x23 2 0x01 0x55 /* VSSG_EVEN */
- 0x23 2 0x02 0x55 /* VSSA_EVEN */
- 0x23 2 0x03 0x51 /* STV2_EVEN */
- 0x23 2 0x04 0x77 /* VDD2_EVEN */
- 0x23 2 0x05 0x57 /* VDD1_EVEN */
- 0x23 2 0x06 0x1F
- 0x23 2 0x07 0x4F /* CK12 */
- 0x23 2 0x08 0x4D /* CK10 */
- 0x23 2 0x09 0x1F
- 0x23 2 0x0A 0x4B /* CK8 */
- 0x23 2 0x0B 0x49 /* CK6 */
- 0x23 2 0x0C 0x1F
- 0x23 2 0x0D 0x47 /* CK4 */
- 0x23 2 0x0E 0x45 /* CK2 */
- 0x23 2 0x0F 0x41 /* STV1_EVEN */
- 0x23 2 0x10 0x1F
- 0x23 2 0x11 0x1F
- 0x23 2 0x12 0x1F
- 0x23 2 0x13 0x55 /* VGG */
- 0x23 2 0x14 0x1F
- 0x23 2 0x15 0x1F
- 0x23 2 0x16 0x52
- /* GIP_R Pin mapping RESET_ODD */
- 0x23 2 0x17 0x55 /* VSSG_ODD */
- 0x23 2 0x18 0x55 /* VSSA_ODD */
- 0x23 2 0x19 0x50 /* STV2_ODD */
- 0x23 2 0x1A 0x77 /* VDD2_ODD */
- 0x23 2 0x1B 0x57 /* VDD1_ODD */
- 0x23 2 0x1C 0x1F
- 0x23 2 0x1D 0x4E /* CK11 */
- 0x23 2 0x1E 0x4C /* CK9 */
- 0x23 2 0x1F 0x1F
- 0x23 2 0x20 0x4A /* CK7 */
- 0x23 2 0x21 0x48 /* CK5 */
- 0x23 2 0x22 0x1F
- 0x23 2 0x23 0x46 /* CK3 */
- 0x23 2 0x24 0x44 /* CK1 */
- 0x23 2 0x25 0x40 /* STV1_ODD */
- 0x23 2 0x26 0x1F
- 0x23 2 0x27 0x1F
- 0x23 2 0x28 0x1F
- 0x23 2 0x29 0x1F
- 0x23 2 0x2A 0x1F
- 0x23 2 0x2B 0x55 /* VGG */
- 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping */
- 0x23 2 0x2D 0x15
- 0x23 2 0x2E 0x15
- 0x23 2 0x2F 0x00
- 0x23 2 0x30 0x37
- 0x23 2 0x31 0x17
- 0x23 2 0x32 0x1F
- 0x23 2 0x33 0x08
- 0x23 2 0x34 0x0A
- 0x23 2 0x35 0x1F
- 0x23 2 0x36 0x0C
- 0x23 2 0x37 0x0E
- 0x23 2 0x38 0x1F
- 0x23 2 0x39 0x04
- 0x23 2 0x3A 0x06
- 0x23 2 0x3B 0x10
- 0x23 2 0x3C 0x1F
- 0x23 2 0x3D 0x1F
- 0x23 2 0x3E 0x1F
- 0x23 2 0x3F 0x15
- 0x23 2 0x40 0x1F
- 0x23 2 0x41 0x1F
- 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping */
- 0x23 2 0x43 0x15
- 0x23 2 0x44 0x15
- 0x23 2 0x45 0x01
- 0x23 2 0x46 0x37
- 0x23 2 0x47 0x17
- 0x23 2 0x48 0x1F
- 0x23 2 0x49 0x09
- 0x23 2 0x4A 0x0B
- 0x23 2 0x4B 0x1F
- 0x23 2 0x4C 0x0D
- 0x23 2 0x4D 0x0F
- 0x23 2 0x4E 0x1F
- 0x23 2 0x4F 0x05
- 0x23 2 0x50 0x07
- 0x23 2 0x51 0x11
- 0x23 2 0x52 0x1F
- 0x23 2 0x53 0x1F
- 0x23 2 0x54 0x1F
- 0x23 2 0x55 0x1F
- 0x23 2 0x56 0x1F
- 0x23 2 0x57 0x15
- 0x23 2 0x58 0x40 /* GIP Timing */
- 0x23 2 0x59 0x00
- 0x23 2 0x5A 0x00
- 0x23 2 0x5B 0x10
- 0x23 2 0x5C 0x14
- 0x23 2 0x5D 0x40
- 0x23 2 0x5E 0x01
- 0x23 2 0x5F 0x02
- 0x23 2 0x60 0x40
- 0x23 2 0x61 0x03
- 0x23 2 0x62 0x04
- 0x23 2 0x63 0x7A
- 0x23 2 0x64 0x7A
- 0x23 2 0x65 0x74
- 0x23 2 0x66 0x16
- 0x23 2 0x67 0xB4
- 0x23 2 0x68 0x16
- 0x23 2 0x69 0x7A
- 0x23 2 0x6A 0x7A
- 0x23 2 0x6B 0x0C
- 0x23 2 0x6C 0x00
- 0x23 2 0x6D 0x04
- 0x23 2 0x6E 0x04
- 0x23 2 0x6F 0x88
- 0x23 2 0x70 0x00
- 0x23 2 0x71 0x00
- 0x23 2 0x72 0x06
- 0x23 2 0x73 0x7B
- 0x23 2 0x74 0x00
- 0x23 2 0x75 0xBC
- 0x23 2 0x76 0x00
- 0x23 2 0x77 0x04
- 0x23 2 0x78 0x2C
- 0x23 2 0x79 0x00
- 0x23 2 0x7A 0x00
- 0x23 2 0x7B 0x00
- 0x23 2 0x7C 0x00
- 0x23 2 0x7D 0x03
- 0x23 2 0x7E 0x7B
- 0x23 2 0xE0 0x04 /* Page4 */
- 0x23 2 0x09 0x11 /* Set RGBCYC2 */
- 0x23 2 0x0E 0x48
- 0x23 2 0x2B 0x2B /* ESD Protect */
- 0x23 2 0x2E 0x44
- 0x23 2 0xE0 0x00 /* Page0 */
- 0x23 2 0xE6 0x02 /* Watch dog */
- 0x23 2 0xE7 0x0C
- 0x05 1 0x11 /* sleep out */
- 0xfd 1 120
- 0x05 1 0x29 /* display on */
- 0x05 1 0x35
- 0xfd 1 20 /* delay(ms) */
- 0xFF 0>; /*ending*/
- init_off = <
- 0x05 1 0x28 /* display off */
- 0xff 10 /* delay 10ms */
- 0x05 1 0x10 /* sleep in */
- 0xff 150 /* delay 150ms */
- 0xff 0xff>; /*ending*/
- };
- };
-
- backlight{
- compatible = "amlogic, backlight-g12a";
- status = "okay";
- key_valid = <0>;
- pinctrl-names = "pwm_on","pwm_off";
- pinctrl-0 = <&pwm_f_pins2>;
- pinctrl-1 = <&bl_pwm_off_pins>;
- pinctrl_version = <2>; /* for uboot */
- bl_pwm_config = <&bl_pwm_conf>;
- bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH
- &gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
- bl_gpio_names = "GPIOH_4","GPIOH_5";
-
- /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/
- /* power index:(point gpios_index, 0xff=invalid)
- * power value:(0=output low, 1=output high, 2=input)
- * power delay:(unit in ms)
- */
-
- backlight_0{
- index = <0>;
- bl_name = "backlight_pwm";
- bl_level_default_uboot_kernel = <100 100>;
- bl_level_attr = <255 10 /*max, min*/
- 128 128>; /*mid, mid_mapping*/
- bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */
- bl_power_attr = <0 /*en_gpio_index*/
- 1 0 /*on_value, off_value*/
- 200 200>; /*on_delay(ms), off_delay(ms)*/
- bl_pwm_port = "PWM_F";
- bl_pwm_attr = <0 /*pwm_method*/
- 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/
- 100 25>; /*duty_max(%), duty_min(%)*/
- bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/
- 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/
- bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */
- };
- backlight_1{
- index = <1>;
- bl_name = "bl_extern";
- bl_level_default_uboot_kernel = <100 100>;
- bl_level_attr = <255 10 /*max, min*/
- 128 128>; /*mid, mid_mapping*/
- bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/
- bl_power_attr = <1 /*en_gpio_index*/
- 1 0 /*on_value, off_value*/
- 200 200>; /*on_delay(ms), off_delay(ms)*/
- bl_extern_index = <0>;
- };
- };
- bl_pwm_conf:bl_pwm_conf{
- pwm_channel_0 {
- pwm_port_index = <5>;
- pwms = <&pwm_ef MESON_PWM_1 30040 0>;
- };
- };
-
- bl_extern{
- compatible = "amlogic, bl_extern";
- status = "disabled";
- i2c_bus = "i2c_bus_3";
-
- extern_0{
- index = <0>;
- extern_name = "i2c_lp8556";
- type = <0>; /*0=i2c, 1=spi, 2=mipi*/
- i2c_address = <0x2c>; /*7bit i2c address*/
- dim_max_min = <255 10>;
- };
-
- extern_1{
- index = <1>;
- extern_name = "mipi_lt070me05";
- type = <2>; /*0=i2c, 1=spi, 2=mipi*/
- dim_max_min = <255 10>;
- };
- };
-};/* end of panel */
-
diff --git a/arch/arm/dts/elaine-p1-panel.dtsi b/arch/arm/dts/elaine-p1-panel.dtsi
deleted file mode 100755
index 75f93db..0000000
--- a/arch/arm/dts/elaine-p1-panel.dtsi
+++ /dev/null
@@ -1,973 +0,0 @@
-/*
- * arch/arm/dts/elaine-p1-panel.dtsi
- *
- * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-/ {
- lcd{
- compatible = "amlogic, lcd-sm1";
- mode = "tablet";
- status = "okay";
- key_valid = <0>;
- clocks = <&clkc CLKID_MIPI_DSI_HOST
- &clkc CLKID_MIPI_DSI_PHY
- &clkc CLKID_DSI_MEAS_COMP
- &clkc CLKID_VCLK2_ENCL
- &clkc CLKID_VCLK2_VENCL
- &clkc CLKID_GP0_PLL>;
- clock-names = "dsi_host_gate",
- "dsi_phy_gate",
- "dsi_meas",
- "encl_top_gate",
- "encl_int_gate",
- "gp0_pll";
- reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */
- 0x0 0xff644000 0x0 0x200>; /* dsi_phy */
- interrupts = <0 3 1
- 0 56 1>;
- interrupt-names = "vsync","vsync2";
- pinctrl_version = <2>; /* for uboot */
-
- /* power type:
- * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending)
- * power index:
- * (point gpios_index, or extern_index,0xff=invalid)
- * power value:(0=output low, 1=output high, 2=input)
- * power delay:(unit in ms)
- */
- lcd_cpu-gpios = <&gpio GPIOZ_13 GPIO_ACTIVE_HIGH>;
- lcd_cpu_gpio_names = "GPIOZ_13";
-
- boe_fiti_7{
- model_name = "TV070WSM_FT";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 700 1053 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 95 163>; /*screen_widht, screen_height*/
- lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/
- 2 8 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 44226000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 400 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_always_hs(0=disable,1=enable)*/
- 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 0x04 3 /* check_reg, check_cnt */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <
- 0xff 5 /* delay 5ms */
- 0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <1>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 0 1 0 200
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 5 /* delay 5ms after mipi off */
- 0 0 0 20 /* reset low */
- 0 1 1 100 /* panel power off */
- 0xff 0 0 0>;
- backlight_index = <0>;
- };
-
- inx_fiti_7{
- model_name = "P070ACB_FT";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 770 1070 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 3 5>; /*screen_widht, screen_height*/
- lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/
- 6 20 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 49434000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 400 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_always_hs(0=disable,1=enable)*/
- 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 0x04 3 /* check_reg, check_cnt */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <
- 0xff 5 /* delay 5ms */
- 0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <2>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 0 1 0 200 /* panel power on */
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 5 /* delay 5ms after mipi off */
- 0 0 0 20 /* reset low */
- 0 1 1 100 /* panel power off */
- 0xff 0 0 0>;
- backlight_index = <0>;
- };
-
- kd_fiti_7{
- model_name = "KD070D82_FT";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 770 1070 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 3 5>; /*screen_widht, screen_height*/
- lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/
- 6 20 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 49434000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 400 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_always_hs(0=disable,1=enable)*/
- 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 0x04 3 /* check_reg, check_cnt */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <
- 0xff 5 /* delay 5ms */
- 0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <3>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 0 1 0 200 /* panel power on */
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 5 /* delay 5ms after mipi off */
- 0 0 0 20 /* reset low */
- 0 1 1 100 /* panel power off */
- 0xff 0 0 0>;
- backlight_index = <0>;
- };
-
- };
-
- lcd_extern{
- compatible = "amlogic, lcd_extern";
- dev_name = "lcd_extern";
- status = "okay";
- key_valid = <0>;
-
- extern_1{
- index = <1>;
- extern_name = "mipi_default"; //TV070WSM_FT
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- cmd_size = <0xff>;
- init_on = <
- 0x23 2 0xE0 0x00
- 0x23 2 0xE1 0x93
- 0x23 2 0xE2 0x65
- 0x23 2 0xE3 0xF8
- 0x23 2 0xE0 0x01
- 0x23 2 0x00 0x00
- 0x23 2 0x01 0x90
- 0x23 2 0x03 0x00
- 0x23 2 0x04 0x90
- 0x23 2 0x17 0x00
- 0x23 2 0x18 0xB0
- 0x23 2 0x19 0x01
- 0x23 2 0x1A 0x00
- 0x23 2 0x1B 0xB0
- 0x23 2 0x1C 0x01
- 0x23 2 0x1F 0x3E
- 0x23 2 0x20 0x2F
- 0x23 2 0x21 0x2F
- 0x23 2 0x22 0x0E
- 0x23 2 0x37 0x69
- 0x23 2 0x38 0x05
- 0x23 2 0x39 0x00
- 0x23 2 0x3A 0x01
- 0x23 2 0x3C 0x90
- 0x23 2 0x3D 0xFF
- 0x23 2 0x3E 0xFF
- 0x23 2 0x3F 0xFF
- 0x23 2 0x40 0x02
- 0x23 2 0x41 0x80
- 0x23 2 0x42 0x99
- 0x23 2 0x43 0x06
- 0x23 2 0x44 0x09
- 0x23 2 0x45 0x3C
- 0x23 2 0x4B 0x04
- 0x23 2 0x55 0x0D
- 0x23 2 0x56 0x01
- 0x23 2 0x57 0x89
- 0x23 2 0x58 0x0A
- 0x23 2 0x59 0x0A
- 0x23 2 0x5A 0x27
- 0x23 2 0x5B 0x15
- 0x23 2 0x5D 0x7C
- 0x23 2 0x5E 0x67
- 0x23 2 0x5F 0x58
- 0x23 2 0x60 0x4C
- 0x23 2 0x61 0x48
- 0x23 2 0x62 0x38
- 0x23 2 0x63 0x3C
- 0x23 2 0x64 0x24
- 0x23 2 0x65 0x3B
- 0x23 2 0x66 0x38
- 0x23 2 0x67 0x36
- 0x23 2 0x68 0x53
- 0x23 2 0x69 0x3F
- 0x23 2 0x6A 0x44
- 0x23 2 0x6B 0x35
- 0x23 2 0x6C 0x2E
- 0x23 2 0x6D 0x1F
- 0x23 2 0x6E 0x0C
- 0x23 2 0x6F 0x00
- 0x23 2 0x70 0x7C
- 0x23 2 0x71 0x67
- 0x23 2 0x72 0x58
- 0x23 2 0x73 0x4C
- 0x23 2 0x74 0x48
- 0x23 2 0x75 0x38
- 0x23 2 0x76 0x3C
- 0x23 2 0x77 0x24
- 0x23 2 0x78 0x3B
- 0x23 2 0x79 0x38
- 0x23 2 0x7A 0x36
- 0x23 2 0x7B 0x53
- 0x23 2 0x7C 0x3F
- 0x23 2 0x7D 0x44
- 0x23 2 0x7E 0x35
- 0x23 2 0x7F 0x2E
- 0x23 2 0x80 0x1F
- 0x23 2 0x81 0x0C
- 0x23 2 0x82 0x00
- 0x23 2 0xE0 0x02
- 0x23 2 0x00 0x45
- 0x23 2 0x01 0x45
- 0x23 2 0x02 0x47
- 0x23 2 0x03 0x47
- 0x23 2 0x04 0x41
- 0x23 2 0x05 0x41
- 0x23 2 0x06 0x1F
- 0x23 2 0x07 0x1F
- 0x23 2 0x08 0x1F
- 0x23 2 0x09 0x1F
- 0x23 2 0x0A 0x1F
- 0x23 2 0x0B 0x1F
- 0x23 2 0x0C 0x1F
- 0x23 2 0x0D 0x1D
- 0x23 2 0x0E 0x1D
- 0x23 2 0x0F 0x1D
- 0x23 2 0x10 0x1F
- 0x23 2 0x11 0x1F
- 0x23 2 0x12 0x1F
- 0x23 2 0x13 0x1F
- 0x23 2 0x14 0x1F
- 0x23 2 0x15 0x1F
- 0x23 2 0x16 0x44
- 0x23 2 0x17 0x44
- 0x23 2 0x18 0x46
- 0x23 2 0x19 0x46
- 0x23 2 0x1A 0x40
- 0x23 2 0x1B 0x40
- 0x23 2 0x1C 0x1F
- 0x23 2 0x1D 0x1F
- 0x23 2 0x1E 0x1F
- 0x23 2 0x1F 0x1F
- 0x23 2 0x20 0x1F
- 0x23 2 0x21 0x1F
- 0x23 2 0x22 0x1F
- 0x23 2 0x23 0x1D
- 0x23 2 0x24 0x1D
- 0x23 2 0x25 0x1D
- 0x23 2 0x26 0x1F
- 0x23 2 0x27 0x1F
- 0x23 2 0x28 0x1F
- 0x23 2 0x29 0x1F
- 0x23 2 0x2A 0x1F
- 0x23 2 0x2B 0x1F
- 0x23 2 0x58 0x40
- 0x23 2 0x59 0x00
- 0x23 2 0x5A 0x00
- 0x23 2 0x5B 0x10
- 0x23 2 0x5C 0x07
- 0x23 2 0x5D 0x20
- 0x23 2 0x5E 0x00
- 0x23 2 0x5F 0x00
- 0x23 2 0x61 0x00
- 0x23 2 0x62 0x00
- 0x23 2 0x63 0x7A
- 0x23 2 0x64 0x7A
- 0x23 2 0x65 0x00
- 0x23 2 0x66 0x00
- 0x23 2 0x67 0x32
- 0x23 2 0x68 0x08
- 0x23 2 0x69 0x7A
- 0x23 2 0x6A 0x7A
- 0x23 2 0x6B 0x00
- 0x23 2 0x6C 0x00
- 0x23 2 0x6D 0x00
- 0x23 2 0x6E 0x00
- 0x23 2 0x6F 0x89
- 0x23 2 0x70 0x00
- 0x23 2 0x71 0x00
- 0x23 2 0x72 0x06
- 0x23 2 0x73 0x7B
- 0x23 2 0x74 0x00
- 0x23 2 0x75 0x07
- 0x23 2 0x76 0x00
- 0x23 2 0x77 0x5D
- 0x23 2 0x78 0x17
- 0x23 2 0x79 0x1F
- 0x23 2 0x7A 0x00
- 0x23 2 0x7B 0x00
- 0x23 2 0x7C 0x00
- 0x23 2 0x7D 0x03
- 0x23 2 0x7E 0x7B
- 0x23 2 0xE0 0x03
- 0x23 2 0xAF 0x20
- 0x23 2 0xE0 0x04
- 0x23 2 0x09 0x11
- 0x23 2 0x0E 0x48
- 0x23 2 0x2B 0x2B
- 0x23 2 0x2E 0x44
- 0x23 2 0x41 0xFF
- 0x23 2 0xE0 0x00
- 0x23 2 0xE6 0x02
- 0x23 2 0xE7 0x0C
- 0x23 2 0x51 0xFF
- 0x23 2 0x53 0x2C
- 0x23 2 0x55 0x00
- 0x05 1 0x11
- 0xFF 125 /* Delay 125ms */
- 0x05 1 0x29
- 0xFF 0xFF /* Ending Flag */
- >;
- init_off = <
- 0xff 5
- 0x05 1 0x28 /* display off */
- 0xff 60 /* delay 60ms */
- 0x05 1 0x10 /* sleep in */
- 0xff 110 /* delay 110ms */
- 0xff 0xff>; /* ending */
- };
-
- extern_2{
- index = <2>;
- extern_name = "mipi_default"; /*P070ACB_FT*/
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- cmd_size = <0xff>;
- init_on = <
- 0x23 2 0xE0 0x00 /* Page 0 */
- 0x23 2 0xE1 0x93 /* PASSWORD */
- 0x23 2 0xE2 0x65
- 0x23 2 0xE3 0xF8
- 0x23 2 0x80 0x03 /* DSI 4 lane */
- 0x23 2 0xE0 0x01 /* Page 01 */
- 0x23 2 0x0C 0x74 /* Set PWRIC */
- 0x23 2 0x17 0x00 /* Set Gamma Power */
- 0x23 2 0x18 0xEF /* VGMP=5.1V */
- 0x23 2 0x19 0x00 /* VGSP=0V */
- 0x23 2 0x1A 0x00
- 0x23 2 0x1B 0xEF /* VGMN=-5.1V */
- 0x23 2 0x1C 0x00 /* VGSN=0V */
- 0x23 2 0x1F 0x70 /* VGH_REG=16.2V */
- 0x23 2 0x20 0x2D /* VGL_REG=-12V */
- 0x23 2 0x21 0x2D /* VGL_REG2=-12V */
- 0x23 2 0x22 0x7E /* VGH_REG short to VGH VGL_REG short to VGL */
- 0x23 2 0x26 0xF3 /* VDDD from IOVCC/VCI */
- 0x23 2 0x37 0x09 /* SS=1 BGR=1 */
- 0x23 2 0x38 0x04 /* JDT=100 column inversion */
- 0x23 2 0x39 0x00 /* Source EQ Setting EQ1 */
- 0x23 2 0x3A 0x01 /* Source EQ Setting EQ2 */
- 0x23 2 0x3C 0x90 /* Source EQ Setting EQ3 */
- 0x23 2 0x3D 0xFF /* SET Source OP on time */
- 0x23 2 0x3E 0xFF /* SET Source OP off time */
- 0x23 2 0x3F 0xFF /* SET Source OP off time */
- 0x23 2 0x40 0x02 /* RSO=640 RGB */
- 0x23 2 0x41 0x80 /* LN=512->1024 line */
- 0x23 2 0x42 0x99 /* SLT internal line period */
- 0x23 2 0x43 0x14 /* VFP */
- 0x23 2 0x44 0x19 /* VBP */
- 0x23 2 0x45 0x5A /* HBP */
- 0x23 2 0x4B 0x04
- 0x23 2 0x55 0x02 /* DCDCM=0010 FP7721BX2 */
- 0x23 2 0x56 0x01 /* No auto Ratio function */
- 0x23 2 0x57 0x69 /* VGH_RT=3'b011 2*AVDD-AVEE VGL_RT=3'b010=AVEE+VCL-AVDD VCL_RT=2'b00 0.5*VCIP */
- 0x23 2 0x58 0x0A /* AVDD_S */
- 0x23 2 0x59 0x0A /* VCL = -2.5V */
- 0x23 2 0x5A 0x2E /* VGH = 16.2V */
- 0x23 2 0x5B 0x19 /* VGL = -12V */
- 0x23 2 0x5C 0x15 /* pump clk */
- 0x23 2 0x5D 0x71 /* V255 positive voltage from 4.888V to 4.888V */
- 0x23 2 0x5E 0x65 /* V251 positive voltage from 4.533V to 4.718V */
- 0x23 2 0x5F 0x55 /* V247 positive voltage from 4.349V to 4.491V */
- 0x23 2 0x60 0x49 /* V243 positive voltage from 4.179V to 4.321V */
- 0x23 2 0x61 0x46 /* V235 positive voltage from 3.910V to 4.052V */
- 0x23 2 0x62 0x38 /* V227 positive voltage from 3.726V to 3.853V */
- 0x23 2 0x63 0x3D /* V211 positive voltage from 3.428V to 3.528V */
- 0x23 2 0x64 0x29 /* V191 positive voltage from 3.159V to 3.244V */
- 0x23 2 0x65 0x43 /* V159 positive voltage from 2.805V to 2.876V */
- 0x23 2 0x66 0x42 /* V128 positive voltage from 2.522V to 2.578V */
- 0x23 2 0x67 0x44 /* V96 positive voltage from 2.267V to 2.323V */
- 0x23 2 0x68 0x63 /* V64 positive voltage from 1.941V to 2.026V */
- 0x23 2 0x69 0x53 /* V44 positive voltage from 1.686V to 1.799V */
- 0x23 2 0x6A 0x5B /* V28 positive voltage from 1.431V to 1.516V */
- 0x23 2 0x6B 0x4E /* V20 positive voltage from 1.275V to 1.322V */
- 0x23 2 0x6C 0x4C /* V12 positive voltage from 1.077V to 1.077V */
- 0x23 2 0x6D 0x41 /* V8 positive voltage from 0.949V to 0.921V */
- 0x23 2 0x6E 0x2D /* V4 positive voltage from 0.723V to 0.638V */
- 0x23 2 0x6F 0x23 /* V0 positive voltage from 0.496V to 0.496V */
- 0x23 2 0x70 0x71 /* V255 negative voltage from -4.888V to -4.888V */
- 0x23 2 0x71 0x4C /* V251 negative voltage from -4.179V to -4.363V */
- 0x23 2 0x72 0x3B /* V247 negative voltage from -3.995V to -4.123V */
- 0x23 2 0x73 0x30 /* V243 negative voltage from -3.825V to -3.967V */
- 0x23 2 0x74 0x2D /* V233 negative voltage from -3.556V to -3.698V */
- 0x23 2 0x75 0x1F /* V227 negative voltage from -3.372V to -3.499V */
- 0x23 2 0x76 0x25 /* V211 negative voltage from -3.088V to -3.188V */
- 0x23 2 0x77 0x10 /* V191 negative voltage from -2.805V to -2.890V */
- 0x23 2 0x78 0x2A /* V159 negative voltage from -2.451V to -2.522V */
- 0x23 2 0x79 0x2A /* V128 negative voltage from -2.182V to -2.238V */
- 0x23 2 0x7A 0x2B /* V96 negative voltage from -1.913V to -1.969V */
- 0x23 2 0x7B 0x4A /* V64 negative voltage from -1.587V to -1.672V */
- 0x23 2 0x7C 0x3A /* V44 negative voltage from -1.332V to -1.445V */
- 0x23 2 0x7D 0x43 /* V28 negative voltage from -1.091V to -1.176V */
- 0x23 2 0x7E 0x36 /* V20 negative voltage from -0.935V to -0.992V */
- 0x23 2 0x7F 0x33 /* V12 negative voltage from -0.723V to -0.723V */
- 0x23 2 0x80 0x28 /* V8 negative voltage from -0.595V to -0.567V */
- 0x23 2 0x81 0x14 /* V4 negative voltage from -0.368V to -0.283V */
- 0x23 2 0x82 0x0B /* V0 negative voltage from -0.156V to -0.156V */
- 0x23 2 0xE0 0x02 /* Page2 */
- 0x23 2 0x00 0x53 /* GIP_L Pin mapping RESET_EVEN */
- 0x23 2 0x01 0x55 /* VSSG_EVEN */
- 0x23 2 0x02 0x55 /* VSSA_EVEN */
- 0x23 2 0x03 0x51 /* STV2_EVEN */
- 0x23 2 0x04 0x77 /* VDD2_EVEN */
- 0x23 2 0x05 0x57 /* VDD1_EVEN */
- 0x23 2 0x06 0x1F /* VGL */
- 0x23 2 0x07 0x4F /* CK12 */
- 0x23 2 0x08 0x4D /* CK10 */
- 0x23 2 0x09 0x1F /* VGL */
- 0x23 2 0x0A 0x4B /* CK8 */
- 0x23 2 0x0B 0x49 /* CK6 */
- 0x23 2 0x0C 0x1F /* VGL */
- 0x23 2 0x0D 0x47 /* CK4 */
- 0x23 2 0x0E 0x45 /* CK2 */
- 0x23 2 0x0F 0x41 /* STV1_EVEN */
- 0x23 2 0x10 0x1F /* VGL */
- 0x23 2 0x11 0x1F /* VGL */
- 0x23 2 0x12 0x1F /* VGL */
- 0x23 2 0x13 0x55 /* VGG */
- 0x23 2 0x14 0x1F /* VGL */
- 0x23 2 0x15 0x1F /* VGL */
- 0x23 2 0x16 0x52 /* GIP_R Pin mapping RESET_ODD */
- 0x23 2 0x17 0x55 /* VSSG_ODD */
- 0x23 2 0x18 0x55 /* VSSA_ODD */
- 0x23 2 0x19 0x50 /* STV2_ODD */
- 0x23 2 0x1A 0x77 /* VDD2_ODD */
- 0x23 2 0x1B 0x57 /* VDD1_ODD */
- 0x23 2 0x1C 0x1F /* VGL */
- 0x23 2 0x1D 0x4E /* CK11 */
- 0x23 2 0x1E 0x4C /* CK9 */
- 0x23 2 0x1F 0x1F /* VGL */
- 0x23 2 0x20 0x4A /* CK7 */
- 0x23 2 0x21 0x48 /* CK5 */
- 0x23 2 0x22 0x1F /* VGL */
- 0x23 2 0x23 0x46 /* CK3 */
- 0x23 2 0x24 0x44 /* CK1 */
- 0x23 2 0x25 0x40 /* STV1_ODD */
- 0x23 2 0x26 0x1F /* VGL */
- 0x23 2 0x27 0x1F /* VGL */
- 0x23 2 0x28 0x1F /* VGL */
- 0x23 2 0x29 0x1F /* VGL */
- 0x23 2 0x2A 0x1F /* VGL */
- 0x23 2 0x2B 0x55 /* VGG */
- 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping RESET_EVEN */
- 0x23 2 0x2D 0x15 /* VSSG_EVEN */
- 0x23 2 0x2E 0x15 /* VSSA_EVEN */
- 0x23 2 0x2F 0x00 /* STV2_EVEN */
- 0x23 2 0x30 0x17 /* VDD2_EVEN */
- 0x23 2 0x31 0x17 /* VDD1_EVEN */
- 0x23 2 0x32 0x1F /* VGL */
- 0x23 2 0x33 0x08 /* CK12 */
- 0x23 2 0x34 0x0A /* CK10 */
- 0x23 2 0x35 0x1F /* VGL */
- 0x23 2 0x36 0x0C /* CK8 */
- 0x23 2 0x37 0x0E /* CK6 */
- 0x23 2 0x38 0x1F /* VGL */
- 0x23 2 0x39 0x04 /* CK4 */
- 0x23 2 0x3A 0x06 /* CK2 */
- 0x23 2 0x3B 0x10 /* STV1_EVEN */
- 0x23 2 0x3C 0x1F /* VGL */
- 0x23 2 0x3D 0x1F /* VGL */
- 0x23 2 0x3E 0x1F /* VGL */
- 0x23 2 0x3F 0x15 /* VGG */
- 0x23 2 0x40 0x1F /* VGL */
- 0x23 2 0x41 0x1F /* VGL */
- 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping RESET_ODD */
- 0x23 2 0x43 0x15 /* VSSG_ODD */
- 0x23 2 0x44 0x15 /* VSSA_ODD */
- 0x23 2 0x45 0x01 /* STV2_ODD */
- 0x23 2 0x46 0x37 /* VDD2_ODD */
- 0x23 2 0x47 0x17 /* VDD1_ODD */
- 0x23 2 0x48 0x1F /* VGL */
- 0x23 2 0x49 0x09 /* CK11 */
- 0x23 2 0x4A 0x0B /* CK9 */
- 0x23 2 0x4B 0x1F /* VGL */
- 0x23 2 0x4C 0x0D /* CK7 */
- 0x23 2 0x4D 0x0F /* CK5 */
- 0x23 2 0x4E 0x1F /* VGL */
- 0x23 2 0x4F 0x05 /* CK3 */
- 0x23 2 0x50 0x07 /* CK1 */
- 0x23 2 0x51 0x11 /* STV1_ODD */
- 0x23 2 0x52 0x1F /* VGL */
- 0x23 2 0x53 0x1F /* VGL */
- 0x23 2 0x54 0x1F /* VGL */
- 0x23 2 0x55 0x1F /* VGL */
- 0x23 2 0x56 0x1F /* VGL */
- 0x23 2 0x57 0x15 /* VGG */
- 0x23 2 0x58 0x40 /* GAS OPT=1 for abnormal power off */
- 0x23 2 0x59 0x00 /* INIT_W */
- 0x23 2 0x5A 0x00 /* INIT[7:0] */
- 0x23 2 0x5B 0x10 /* STV_NUM STV_S0[10:8] */
- 0x23 2 0x5C 0x14 /* STV_S0[7:0] */
- 0x23 2 0x5D 0x40 /* STV_W STV_S1 */
- 0x23 2 0x5E 0x01 /* STV_S2 */
- 0x23 2 0x5F 0x02 /* STV_S3 */
- 0x23 2 0x60 0x40 /* ETV_W ETV_S1 */
- 0x23 2 0x61 0x03 /* ETV_S2 */
- 0x23 2 0x62 0x04 /* ETV_S3 */
- 0x23 2 0x63 0x7A /* SETV_ON for STV/ETV on time */
- 0x23 2 0x64 0x7A /* SETV_OFF for STV/ETV off time */
- 0x23 2 0x65 0x74 /* ETV_EN ETV_NUM ETV_S0 */
- 0x23 2 0x66 0x16 /* ETV_S0 */
- 0x23 2 0x67 0xB4 /* CKV0_NUM CKV0_W */
- 0x23 2 0x68 0x16 /* CKV0_S0 */
- 0x23 2 0x69 0x7A /* CKV0_on */
- 0x23 2 0x6A 0x7A /* CKV0_off time */
- 0x23 2 0x6B 0x0C /* CKV0_DUM */
- 0x23 2 0x6C 0x00 /* GIP Line EQ option */
- 0x23 2 0x6D 0x04 /* GIP rising EQ */
- 0x23 2 0x6E 0x04 /* GIP fallig EQ */
- 0x23 2 0x6F 0x88 /* GIP_DR CKV0_CON CKV1_CON */
- 0x23 2 0x70 0x00 /* CKV1_NUM CKV0_W */
- 0x23 2 0x71 0x00 /* CKV1_S0 */
- 0x23 2 0x72 0x06 /* CKV1_on */
- 0x23 2 0x73 0x7B /* CKV1_off time */
- 0x23 2 0x74 0x00 /* CKV1_DUM */
- 0x23 2 0x75 0xBC /* FLM_EN FLM_W */
- 0x23 2 0x76 0x00 /* FLM on time */
- 0x23 2 0x77 0x04 /* VEN_EN VEN_W FLM_NUM FLM_OFF */
- 0x23 2 0x78 0x2C /* FLM_OFF */
- 0x23 2 0x79 0x00 /* VEN_W */
- 0x23 2 0x7A 0x00 /* VEN_S0 */
- 0x23 2 0x7B 0x00 /* VEN_S1 */
- 0x23 2 0x7C 0x00 /* VEN_DUM */
- 0x23 2 0x7D 0x03 /* VEN on time */
- 0x23 2 0x7E 0x7B /* VEN off time */
- 0x23 2 0xE0 0x03 /* Page3 */
- 0x23 2 0xAF 0x20 /* Set CABC */
- 0x23 2 0xE0 0x04 /* Page4 */
- 0x23 2 0x09 0x11 /* Source level at blanking period */
- 0x23 2 0x0E 0x48 /* Source EQ option */
- 0x23 2 0x2B 0x2B /* ESD Protect */
- 0x23 2 0x2E 0x44 /* Special Packet disable */
- 0x23 2 0x41 0xFF /* Set CABC */
- 0x23 2 0xE0 0x00 /* Page0 */
- 0x23 2 0xE6 0x02 /* Enable Watch Dog */
- 0x23 2 0xE7 0x0C /* Watch Dog timer setting */
- 0x23 2 0x51 0xFF /* CABC Option 0x80=50% duty 0xFF=100% */
- 0x23 2 0x53 0x2C
- 0x23 2 0x55 0x00
- 0x05 1 0x11 /* Sleep Out */
- 0xFF 125 /* Delay 125ms */
- 0x05 1 0x29 /* Display On */
- 0xFF 0xFF /* Ending */
- >;
- init_off = <
- 0xff 5
- 0x05 1 0x28 /* display off */
- 0xff 60 /* delay 60ms */
- 0x05 1 0x10 /* sleep in */
- 0xff 110 /* delay 110ms */
- 0xff 0xff>; /* ending */
- };
-
- extern_3{
- index = <3>;
- extern_name = "mipi_default"; /*KD070D82_FT*/
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- cmd_size = <0xff>;
- init_on = <
- 0x23 2 0xE0 0x00 /* Register setting change to Page 0 */
- 0x23 2 0xE1 0x93 /* PASSWORD, setting as 93-65-F8 to enable page1-4 command access */
- 0x23 2 0xE2 0x65
- 0x23 2 0xE3 0xF8
- 0x23 2 0x80 0x03 /* Setting DSI lane number, 0x03 is DSI 4 lane */
- 0x23 2 0xE0 0x01 /* Register setting change to Page 1 */
- 0x23 2 0x00 0x00 /* Set VCOM_Forward */
- 0x23 2 0x01 0x9E /* VCOM=0x09F */
- 0x23 2 0x03 0x00 /* Set VCOM_Reverse */
- 0x23 2 0x04 0xAA /* VCOMR=0x0AA, -1.40V */
- 0x23 2 0x0C 0x74 /* Set PWRIC pumping frequency,=8 HCLK, about 512KHz */
- 0x23 2 0x17 0x00 /* Set Gamma Power, VGMP[8]=0, VGSP[8]=0 */
- 0x23 2 0x18 0xEF /* VGMP[8:0]=0x0EF=5.1V */
- 0x23 2 0x19 0x00 /* VGSP[8:0]=0x000=0V */
- 0x23 2 0x1A 0x00 /* VGMN[8]=0, VGSN[8]=0 */
- 0x23 2 0x1B 0xEF /* VGMN[8:0]=0x0EF=-5.1V */
- 0x23 2 0x1C 0x00 /* VGSN[8:0]=0x000=0V */
- 0x23 2 0x1F 0x70 /* VGH_REG=16.2V */
- 0x23 2 0x20 0x2D /* VGL_REG=-12V */
- 0x23 2 0x21 0x2D /* VGL_REG2=-12V */
- 0x23 2 0x22 0x7E /* VGH_REG short to VGH, VGL_REG short to VGL, */
- 0x23 2 0x26 0xF3 /* VDDD from IOVCC&VCI */
- 0x23 2 0x37 0x09 /* SS=1, source scan from S2400 to S1;BGR=1 CF type is (S1,S2,S3) align to (B,G,R) */
- 0x23 2 0x38 0x04 /* JDT=100, display inversion type is column inversion */
- 0x23 2 0x39 0x00 /* Source EQ Setting, EQ1, 0x00=0us */
- 0x23 2 0x3A 0x01 /* Source EQ Setting, EQ2, 0x01 =0.1us */
- 0x23 2 0x3C 0x90 /* Source EQ Setting, EQ3, EQ3 start at 14.4us */
- 0x23 2 0x3D 0xFF /* SET Source OP on time, 0xFF means source op always on */
- 0x23 2 0x3E 0xFF /* SET Source OP off time, 0xFF means source op always on */
- 0x23 2 0x3F 0xFF /* SET Source OP off time, 0xFF means source op always on */
- 0x23 2 0x40 0x02 /* horizontal resolution setting,RSO[2:0]= 0x02 =600RGB, LN[1:0]=2'b00 */
- 0x23 2 0x41 0x80 /* LN[9:0]=0x200=512, vertical resolution is 512*2=1024 line */
- 0x23 2 0x42 0x99 /* SLT, internal line period=0x99->15.3us */
- 0x23 2 0x43 0x14 /* Internal VFP=Ext_VFP=20(0x14) */
- 0x23 2 0x44 0x19 /* Internal _VBP=Ext_VS+Ext_VBP-1=6+20-1=25(0x19) */
- 0x23 2 0x45 0x5A /* Internal_HBP=Ext_HS+Ext_HBP=90(0x5A) */
- 0x23 2 0x55 0x02 /* Seting PWRIC mode, DCDCM=0010-> FP7721BX2 */
- 0x23 2 0x56 0x01 /* No auto Ratio function */
- 0x23 2 0x57 0x69 /* VGH_RT=3'b011,2*AVDD-AVEE,VGL_RT=3'b010=AVEE+VCL-AVDD,VCL_RT=2'b00,0.5*VCIP */
- 0x23 2 0x58 0x0A /* AVDD_S, not use internal AVDD in this model */
- 0x23 2 0x59 0x0A /* VCL = -2.5V */
- 0x23 2 0x5A 0x2E /* VGH = 16.2V */
- 0x23 2 0x5B 0x19 /* VGL = -12V */
- 0x23 2 0x5C 0x15 /* pump clk, VCL_CLK[1:0]=2'b01=HCLK/2=32KHz, VGHVGL_CLK[1:0]=2'b01=HCLK/2=32KHz */
- 0x23 2 0x5D 0x77 /* Gamma voltage setting, VP255-4.793V */
- 0x23 2 0x5E 0x5C /* VP251 */
- 0x23 2 0x5F 0x4D /* VP247 */
- 0x23 2 0x60 0x40 /* VP243 */
- 0x23 2 0x61 0x3D /* VP235 */
- 0x23 2 0x62 0x2F /* VP227 */
- 0x23 2 0x63 0x34 /* VP211 */
- 0x23 2 0x64 0x1F /* VP191 */
- 0x23 2 0x65 0x38 /* VP159 */
- 0x23 2 0x66 0x38 /* VP128 */
- 0x23 2 0x67 0x39 /* VP96 */
- 0x23 2 0x68 0x58 /* VP64 */
- 0x23 2 0x69 0x48 /* VP44 */
- 0x23 2 0x6A 0x51 /* VP28 */
- 0x23 2 0x6B 0x44 /* VP20 */
- 0x23 2 0x6C 0x41 /* VP12 */
- 0x23 2 0x6D 0x35 /* VP8 */
- 0x23 2 0x6E 0x24 /* VP4 */
- 0x23 2 0x6F 0x02 /* VP0 */
- 0x23 2 0x70 0x77 /* VN255 */
- 0x23 2 0x71 0x5C /* VN251 */
- 0x23 2 0x72 0x4D /* VN247 */
- 0x23 2 0x73 0x40 /* VN243 */
- 0x23 2 0x74 0x3D /* VN235 */
- 0x23 2 0x75 0x2F /* VN227 */
- 0x23 2 0x76 0x34 /* VN211 */
- 0x23 2 0x77 0x1F /* VN191 */
- 0x23 2 0x78 0x38 /* VN159 */
- 0x23 2 0x79 0x38 /* VN128 */
- 0x23 2 0x7A 0x39 /* VN96 */
- 0x23 2 0x7B 0x58 /* VN64 */
- 0x23 2 0x7C 0x48 /* VN44 */
- 0x23 2 0x7D 0x51 /* VN28 */
- 0x23 2 0x7E 0x44 /* VN20 */
- 0x23 2 0x7F 0x41 /* VN12 */
- 0x23 2 0x80 0x35 /* VN8 */
- 0x23 2 0x81 0x24 /* VN4 */
- 0x23 2 0x82 0x02 /* VN0 */
- 0x23 2 0xE0 0x02 /* Register setting change to Page 2 */
- 0x23 2 0x00 0x53 /* GIP_L_Forward scan mapping, assign as RESET_EVEN */
- 0x23 2 0x01 0x55 /* assign as VSSG_EVEN */
- 0x23 2 0x02 0x55 /* assign as VSSA_EVEN */
- 0x23 2 0x03 0x51 /* assign as STV2_EVEN */
- 0x23 2 0x04 0x77 /* assign as VDD2_EVEN */
- 0x23 2 0x05 0x57 /* assign as VDD1_EVEN */
- 0x23 2 0x06 0x1F /* assign as VGL */
- 0x23 2 0x07 0x4F /* assign as CK12 */
- 0x23 2 0x08 0x4D /* assign as CK10 */
- 0x23 2 0x09 0x1F /* assign as VGL */
- 0x23 2 0x0A 0x4B /* assign as CK8 */
- 0x23 2 0x0B 0x49 /* assign as CK6 */
- 0x23 2 0x0C 0x1F /* assign as VGL */
- 0x23 2 0x0D 0x47 /* assign as CK4 */
- 0x23 2 0x0E 0x45 /* assign as CK2 */
- 0x23 2 0x0F 0x41 /* assign as STV1_EVEN */
- 0x23 2 0x10 0x1F /* assign as VGL */
- 0x23 2 0x11 0x1F /* assign as VGL */
- 0x23 2 0x12 0x1F /* assign as VGL */
- 0x23 2 0x13 0x55 /* assign as VGG */
- 0x23 2 0x14 0x1F /* assign as VGL */
- 0x23 2 0x15 0x1F /* assign as VGL */
- 0x23 2 0x16 0x52 /* GIP_R_Forward scan mapping, assign as RESET_ODD */
- 0x23 2 0x17 0x55 /* assign as VSSG_ODD */
- 0x23 2 0x18 0x55 /* assign as VSSA_ODD */
- 0x23 2 0x19 0x50 /* assign as STV2_ODD */
- 0x23 2 0x1A 0x77 /* assign as VDD2_ODD */
- 0x23 2 0x1B 0x57 /* assign as VDD1_ODD */
- 0x23 2 0x1C 0x1F /* assign as VGL */
- 0x23 2 0x1D 0x4E /* assign as CK11 */
- 0x23 2 0x1E 0x4C /* assign as CK9 */
- 0x23 2 0x1F 0x1F /* assign as VGL */
- 0x23 2 0x20 0x4A /* assign as CK7 */
- 0x23 2 0x21 0x48 /* assign as CK5 */
- 0x23 2 0x22 0x1F /* assign as VGL */
- 0x23 2 0x23 0x46 /* assign as CK3 */
- 0x23 2 0x24 0x44 /* assign as CK1 */
- 0x23 2 0x25 0x40 /* assign as STV1_ODD */
- 0x23 2 0x26 0x1F /* assign as VGL */
- 0x23 2 0x27 0x1F /* assign as VGL */
- 0x23 2 0x28 0x1F /* assign as VGL */
- 0x23 2 0x29 0x1F /* assign as VGL */
- 0x23 2 0x2A 0x1F /* assign as VGL */
- 0x23 2 0x2B 0x55 /* assign as VGG */
- 0x23 2 0x2C 0x12 /* GIP_L_Reverse Scan mapping, assign as RESET_EVEN */
- 0x23 2 0x2D 0x15 /* assign as VSSG_EVEN */
- 0x23 2 0x2E 0x15 /* assign as VSSA_EVEN */
- 0x23 2 0x2F 0x00 /* assign as STV2_EVEN */
- 0x23 2 0x30 0x17 /* assign as VDD2_EVEN */
- 0x23 2 0x31 0x17 /* assign as VDD1_EVEN */
- 0x23 2 0x32 0x1F /* assign as VGL */
- 0x23 2 0x33 0x08 /* assign as CK12 */
- 0x23 2 0x34 0x0A /* assign as CK10 */
- 0x23 2 0x35 0x1F /* assign as VGL */
- 0x23 2 0x36 0x0C /* assign as CK8 */
- 0x23 2 0x37 0x0E /* assign as CK6 */
- 0x23 2 0x38 0x1F /* assign as VGL */
- 0x23 2 0x39 0x04 /* assign as CK4 */
- 0x23 2 0x3A 0x06 /* assign as CK2 */
- 0x23 2 0x3B 0x10 /* assign as STV1_EVEN */
- 0x23 2 0x3C 0x1F /* assign as VGL */
- 0x23 2 0x3D 0x1F /* assign as VGL */
- 0x23 2 0x3E 0x1F /* assign as VGL */
- 0x23 2 0x3F 0x15 /* assign as VGG */
- 0x23 2 0x40 0x1F /* assign as VGL */
- 0x23 2 0x41 0x1F /* assign as VGL */
- 0x23 2 0x42 0x13 /* GIP_R_Reverse Scan mapping, assign as RESET_ODD */
- 0x23 2 0x43 0x15 /* assign as VSSG_ODD */
- 0x23 2 0x44 0x15 /* assign as VSSA_ODD */
- 0x23 2 0x45 0x01 /* assign as STV2_ODD */
- 0x23 2 0x46 0x17 /* assign as VDD2_ODD */
- 0x23 2 0x47 0x17 /* assign as VDD1_ODD */
- 0x23 2 0x48 0x1F /* assign as VGL */
- 0x23 2 0x49 0x09 /* assign as CK11 */
- 0x23 2 0x4A 0x0B /* assign as CK9 */
- 0x23 2 0x4B 0x1F /* assign as VGL */
- 0x23 2 0x4C 0x0D /* assign as CK7 */
- 0x23 2 0x4D 0x0F /* assign as CK5 */
- 0x23 2 0x4E 0x1F /* assign as VGL */
- 0x23 2 0x4F 0x05 /* assign as CK3 */
- 0x23 2 0x50 0x07 /* assign as CK1 */
- 0x23 2 0x51 0x11 /* assign as STV1_ODD */
- 0x23 2 0x52 0x1F /* assign as VGL */
- 0x23 2 0x53 0x1F /* assign as VGL */
- 0x23 2 0x54 0x1F /* assign as VGL */
- 0x23 2 0x55 0x1F /* assign as VGL */
- 0x23 2 0x56 0x1F /* assign as VGL */
- 0x23 2 0x57 0x15 /* assign as VGG */
- 0x23 2 0x58 0x40 /* GAS OPT=1, When abnormal power off, GIP will pull to VGH */
- 0x23 2 0x59 0x00 /* INIT_W=0, no INIT function in this panel */
- 0x23 2 0x5A 0x00 /* INIT[10:0], no INIT function in this panel */
- 0x23 2 0x5B 0x10 /* STV_NUM,STV_S0[10:8], 2 STV pulses */
- 0x23 2 0x5C 0x14 /* STV_S0[7:0], STV start from 21th hsync after vsync */
- 0x23 2 0x5D 0x40 /* STV_W=4, STV width is 4 Hline; STV1 delay 1 hline with STV0 */
- 0x23 2 0x5E 0x01 /* STV_S2, STV2 delay 2 hline with STV0 */
- 0x23 2 0x5F 0x02 /* STV_S3, STV3 delay 3 hline with STV0 */
- 0x23 2 0x60 0x40 /* ETV_W=4, ETV witdh is 4 hline; ETV1 delay 1 hilne from ETV0 */
- 0x23 2 0x61 0x03 /* ETV_S2, ETV2 delay 4 hline with ETV0 */
- 0x23 2 0x62 0x04 /* ETV_S3, ETV3 delay 5 hline with ETV0 */
- 0x23 2 0x63 0x7A /* SETV_ON for STV/ETV on time, rising at 12.2us after hsync */
- 0x23 2 0x64 0x7A /* SETV_OFF for STV/ETV off time , falling at 12.2us after hsync */
- 0x23 2 0x65 0x74 /* ETV_EN=1, enable ETV function; ETV_NUM=3, using 4 ETV pulse, */
- 0x23 2 0x66 0x16 /* ETV_S0=0x416, EVT start at 1046th hsync fater vaync */
- 0x23 2 0x67 0xB4 /* CKV_NUM=2'b1011, using 12 CKV pulse; CKV0_W=4. CKV width is 4 hline */
- 0x23 2 0x68 0x16 /* CKV0_S0 , CKV start from 23th hsync after vsync */
- 0x23 2 0x69 0x7A /* CKV0_on ,for CKV on time, rising at 12.2us after hsync */
- 0x23 2 0x6A 0x7A /* CKV0_off ,for CKV off time, falling at 12.2us after hsync */
- 0x23 2 0x6B 0x0C /* CKV0_DUM, total CKV pulse number=1024+12=1036 */
- 0x23 2 0x6C 0x00 /* GIP Line EQ option , disable GEQ_Line function */
- 0x23 2 0x6D 0x04 /* GIP rising EQ, period is 0.4us */
- 0x23 2 0x6E 0x04 /* GIP fallig EQ, period is 0.4us */
- 0x23 2 0x6F 0x88 /* GIP_DR; CKV0_CON, no continuous CKV0; CKV1_CON, no continuous CKV1 */
- 0x23 2 0x70 0x00 /* CKV1_NUM, CKV0_W , no CKV group 1 function in this panel, don't care */
- 0x23 2 0x71 0x00 /* CKV1_S0, no CKV group 1 function in this panel, don't care */
- 0x23 2 0x72 0x06 /* CKV1_on , no CKV group 1 function in this panel, don't care */
- 0x23 2 0x73 0x7B /* CKV1_off time, no CKV group 1 function in this panel, don't care */
- 0x23 2 0x74 0x00 /* CKV1_DUM, no CKV group 1 function in this panel, don't care */
- 0x23 2 0x75 0xBC /* FLM_EN, enable FLM function; FLM_W=0x3C, FLM toggle period is 60 frame */
- 0x23 2 0x76 0x00 /* FLM on time , FLM on(rising) at 1st hsync after vsync */
- 0x23 2 0x77 0x04 /* VEN_EN, VEN_W, no VEN function in this panel, don't care */
- 0x23 2 0x78 0x2C /* FLM_OFF, FLM off(falling) at 1068th hsync after vsync */
- 0x23 2 0x79 0x00 /* VEN_W , no VEN function in this panel, don't care */
- 0x23 2 0x7A 0x00 /* VEN_S0 , no VEN function in this panel, don't care */
- 0x23 2 0x7B 0x00 /* VEN_S1 , no VEN function in this panel, don't care */
- 0x23 2 0x7C 0x00 /* VEN_DUM , no VEN function in this panel, don't care */
- 0x23 2 0x7D 0x03 /* VEN on time , no VEN function in this panel, don't care */
- 0x23 2 0x7E 0x7B /* VEN off time , no VEN function in this panel, don't care */
- 0x23 2 0xE0 0x03 /* Register setting change to Page 3 */
- 0x23 2 0xAF 0x20 /* Set CABC, disable CABC TP detect, for CABC pattern change more smooth */
- 0x23 2 0xE0 0x04 /* Register setting change to Page 4 */
- 0x23 2 0x09 0x11 /* Source level at blanking period, sweeping V0 level */
- 0x23 2 0x0E 0x48 /* Source EQ option, EQ to PCAP,NCAP */
- 0x23 2 0x2B 0x2B /* ESD Protect, clock lane op behavior follow data lane, improve ESD performance */
- 0x23 2 0x2E 0x44 /* ESD protect, disable special packet */
- 0x23 2 0x41 0xFF /* Set CABC, for CABC pattern change more smooth */
- 0x23 2 0xE0 0x00 /* Register setting change to Page 0 */
- 0x23 2 0xE6 0x02 /* Enable Watch Dog */
- 0x23 2 0xE7 0x0C /* Watch Dog timer setting, WD alarm time is 12*512osc after hsync stop */
- 0x23 2 0x51 0xFF /* CABC Option, 0x80=50% duty, 0xFF=100% */
- 0x23 2 0x53 0x2C /* enable dimming, BCTRL, BL */
- 0x23 2 0x55 0x00 /* CABC mode, 0x00 is manual mode */
- 0x05 1 0x11 /* SLPOUT */
- 0xFF 125 /* Delay 125ms */
- 0x05 1 0x29 /* Display On */
- 0xFF 0xFF /* Ending */
- >;
- init_off = <
- 0xff 5
- 0x05 1 0x28 /* display off */
- 0xff 60 /* delay 60ms */
- 0x05 1 0x10 /* sleep in */
- 0xff 110 /* delay 110ms */
- 0xff 0xff>; /* ending */
- };
- };
-
- backlight{
- compatible = "amlogic, backlight-g12a";
- status = "okay";
- key_valid = <0>;
- pinctrl-names = "pwm_on","pwm_off";
- pinctrl-0 = <&pwm_f_pins2>;
- pinctrl-1 = <&bl_pwm_off_pins>;
- pinctrl_version = <2>; /* for uboot */
- bl_pwm_config = <&bl_pwm_conf>;
- bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH
- &gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
- bl_gpio_names = "GPIOH_4","GPIOH_5";
-
- /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/
- /* power index:(point gpios_index, 0xff=invalid)
- * power value:(0=output low, 1=output high, 2=input)
- * power delay:(unit in ms)
- */
-
- backlight_0{
- index = <0>;
- bl_name = "backlight_pwm";
- bl_level_default_uboot_kernel = <100 100>;
- bl_level_attr = <255 10 /*max, min*/
- 128 128>; /*mid, mid_mapping*/
- bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */
- bl_power_attr = <0 /*en_gpio_index*/
- 1 0 /*on_value, off_value*/
- 200 200>; /*on_delay(ms), off_delay(ms)*/
- bl_pwm_port = "PWM_F";
- bl_pwm_attr = <0 /*pwm_method*/
- 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/
- 100 25>; /*duty_max(%), duty_min(%)*/
- bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/
- 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/
- bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */
- };
- backlight_1{
- index = <1>;
- bl_name = "bl_extern";
- bl_level_default_uboot_kernel = <100 100>;
- bl_level_attr = <255 10 /*max, min*/
- 128 128>; /*mid, mid_mapping*/
- bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/
- bl_power_attr = <1 /*en_gpio_index*/
- 1 0 /*on_value, off_value*/
- 200 200>; /*on_delay(ms), off_delay(ms)*/
- bl_extern_index = <0>;
- };
- };
- bl_pwm_conf:bl_pwm_conf{
- pwm_channel_0 {
- pwm_port_index = <5>;
- pwms = <&pwm_ef MESON_PWM_1 30040 0>;
- };
- };
-
- bl_extern{
- compatible = "amlogic, bl_extern";
- status = "disabled";
- i2c_bus = "i2c_bus_3";
-
- extern_0{
- index = <0>;
- extern_name = "i2c_lp8556";
- type = <0>; /*0=i2c, 1=spi, 2=mipi*/
- i2c_address = <0x2c>; /*7bit i2c address*/
- dim_max_min = <255 10>;
- };
-
- extern_1{
- index = <1>;
- extern_name = "mipi_lt070me05";
- type = <2>; /*0=i2c, 1=spi, 2=mipi*/
- dim_max_min = <255 10>;
- };
- };
-};/* end of panel */
diff --git a/arch/arm/dts/elaine-p2-panel.dtsi b/arch/arm/dts/elaine-p2-panel.dtsi
deleted file mode 100755
index 8b7cb25..0000000
--- a/arch/arm/dts/elaine-p2-panel.dtsi
+++ /dev/null
@@ -1,973 +0,0 @@
-/*
- * arch/arm/dts/elaine-p2-panel.dtsi
- *
- * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-/ {
- lcd{
- compatible = "amlogic, lcd-sm1";
- mode = "tablet";
- status = "okay";
- key_valid = <0>;
- clocks = <&clkc CLKID_MIPI_DSI_HOST
- &clkc CLKID_MIPI_DSI_PHY
- &clkc CLKID_DSI_MEAS_COMP
- &clkc CLKID_VCLK2_ENCL
- &clkc CLKID_VCLK2_VENCL
- &clkc CLKID_GP0_PLL>;
- clock-names = "dsi_host_gate",
- "dsi_phy_gate",
- "dsi_meas",
- "encl_top_gate",
- "encl_int_gate",
- "gp0_pll";
- reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */
- 0x0 0xff644000 0x0 0x200>; /* dsi_phy */
- interrupts = <0 3 1
- 0 56 1>;
- interrupt-names = "vsync","vsync2";
- pinctrl_version = <2>; /* for uboot */
-
- /* power type:
- * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending)
- * power index:
- * (point gpios_index, or extern_index,0xff=invalid)
- * power value:(0=output low, 1=output high, 2=input)
- * power delay:(unit in ms)
- */
- lcd_cpu-gpios = <&gpio GPIOZ_13 GPIO_ACTIVE_HIGH>;
- lcd_cpu_gpio_names = "GPIOZ_13";
-
- boe_fiti9364_7{
- model_name = "TV070WSM_FT9364";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 700 1053 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 95 163>; /*screen_widht, screen_height*/
- lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/
- 2 8 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 44226000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 400 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_always_hs(0=disable,1=enable)*/
- 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 0x04 3 /* check_reg, check_cnt */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <
- 0xff 5 /* delay 5ms */
- 0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <1>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 0 1 0 200
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 5 /* delay 5ms after mipi off */
- 0 0 0 20 /* reset low */
- 0 1 1 100 /* panel power off */
- 0xff 0 0 0>;
- backlight_index = <0>;
- };
-
- inx_fiti9364_7{
- model_name = "P070ACB_FT9364";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 770 1070 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 3 5>; /*screen_widht, screen_height*/
- lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/
- 6 20 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 49434000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 400 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_always_hs(0=disable,1=enable)*/
- 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 0x04 3 /* check_reg, check_cnt */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <
- 0xff 5 /* delay 5ms */
- 0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <2>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 0 1 0 200 /* panel power on */
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 5 /* delay 5ms after mipi off */
- 0 0 0 20 /* reset low */
- 0 1 1 100 /* panel power off */
- 0xff 0 0 0>;
- backlight_index = <0>;
- };
-
- kd_fiti9364_7{
- model_name = "KD070D82_FT9364";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 770 1070 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 3 5>; /*screen_widht, screen_height*/
- lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/
- 6 20 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 49434000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 400 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_always_hs(0=disable,1=enable)*/
- 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 0x04 3 /* check_reg, check_cnt */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <
- 0xff 5 /* delay 5ms */
- 0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <3>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 0 1 0 200 /* panel power on */
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 5 /* delay 5ms after mipi off */
- 0 0 0 20 /* reset low */
- 0 1 1 100 /* panel power off */
- 0xff 0 0 0>;
- backlight_index = <0>;
- };
-
- };
-
- lcd_extern{
- compatible = "amlogic, lcd_extern";
- dev_name = "lcd_extern";
- status = "okay";
- key_valid = <0>;
-
- extern_1{
- index = <1>;
- extern_name = "mipi_default"; // TV070WSM_FT9364
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- cmd_size = <0xff>;
- init_on = <
- 0x23 2 0xE0 0x00
- 0x23 2 0xE1 0x93
- 0x23 2 0xE2 0x65
- 0x23 2 0xE3 0xF8
- 0x23 2 0xE0 0x01
- 0x23 2 0x00 0x00
- 0x23 2 0x01 0x90
- 0x23 2 0x03 0x00
- 0x23 2 0x04 0x90
- 0x23 2 0x17 0x00
- 0x23 2 0x18 0xB0
- 0x23 2 0x19 0x01
- 0x23 2 0x1A 0x00
- 0x23 2 0x1B 0xB0
- 0x23 2 0x1C 0x01
- 0x23 2 0x1F 0x3E
- 0x23 2 0x20 0x2F
- 0x23 2 0x21 0x2F
- 0x23 2 0x22 0x0E
- 0x23 2 0x37 0x69
- 0x23 2 0x38 0x05
- 0x23 2 0x39 0x00
- 0x23 2 0x3A 0x01
- 0x23 2 0x3C 0x90
- 0x23 2 0x3D 0xFF
- 0x23 2 0x3E 0xFF
- 0x23 2 0x3F 0xFF
- 0x23 2 0x40 0x02
- 0x23 2 0x41 0x80
- 0x23 2 0x42 0x99
- 0x23 2 0x43 0x06
- 0x23 2 0x44 0x09
- 0x23 2 0x45 0x3C
- 0x23 2 0x4B 0x04
- 0x23 2 0x55 0x0D
- 0x23 2 0x56 0x01
- 0x23 2 0x57 0x89
- 0x23 2 0x58 0x0A
- 0x23 2 0x59 0x0A
- 0x23 2 0x5A 0x27
- 0x23 2 0x5B 0x15
- 0x23 2 0x5D 0x7C
- 0x23 2 0x5E 0x67
- 0x23 2 0x5F 0x58
- 0x23 2 0x60 0x4C
- 0x23 2 0x61 0x48
- 0x23 2 0x62 0x38
- 0x23 2 0x63 0x3C
- 0x23 2 0x64 0x24
- 0x23 2 0x65 0x3B
- 0x23 2 0x66 0x38
- 0x23 2 0x67 0x36
- 0x23 2 0x68 0x53
- 0x23 2 0x69 0x3F
- 0x23 2 0x6A 0x44
- 0x23 2 0x6B 0x35
- 0x23 2 0x6C 0x2E
- 0x23 2 0x6D 0x1F
- 0x23 2 0x6E 0x0C
- 0x23 2 0x6F 0x00
- 0x23 2 0x70 0x7C
- 0x23 2 0x71 0x67
- 0x23 2 0x72 0x58
- 0x23 2 0x73 0x4C
- 0x23 2 0x74 0x48
- 0x23 2 0x75 0x38
- 0x23 2 0x76 0x3C
- 0x23 2 0x77 0x24
- 0x23 2 0x78 0x3B
- 0x23 2 0x79 0x38
- 0x23 2 0x7A 0x36
- 0x23 2 0x7B 0x53
- 0x23 2 0x7C 0x3F
- 0x23 2 0x7D 0x44
- 0x23 2 0x7E 0x35
- 0x23 2 0x7F 0x2E
- 0x23 2 0x80 0x1F
- 0x23 2 0x81 0x0C
- 0x23 2 0x82 0x00
- 0x23 2 0xE0 0x02
- 0x23 2 0x00 0x45
- 0x23 2 0x01 0x45
- 0x23 2 0x02 0x47
- 0x23 2 0x03 0x47
- 0x23 2 0x04 0x41
- 0x23 2 0x05 0x41
- 0x23 2 0x06 0x1F
- 0x23 2 0x07 0x1F
- 0x23 2 0x08 0x1F
- 0x23 2 0x09 0x1F
- 0x23 2 0x0A 0x1F
- 0x23 2 0x0B 0x1F
- 0x23 2 0x0C 0x1F
- 0x23 2 0x0D 0x1D
- 0x23 2 0x0E 0x1D
- 0x23 2 0x0F 0x1D
- 0x23 2 0x10 0x1F
- 0x23 2 0x11 0x1F
- 0x23 2 0x12 0x1F
- 0x23 2 0x13 0x1F
- 0x23 2 0x14 0x1F
- 0x23 2 0x15 0x1F
- 0x23 2 0x16 0x44
- 0x23 2 0x17 0x44
- 0x23 2 0x18 0x46
- 0x23 2 0x19 0x46
- 0x23 2 0x1A 0x40
- 0x23 2 0x1B 0x40
- 0x23 2 0x1C 0x1F
- 0x23 2 0x1D 0x1F
- 0x23 2 0x1E 0x1F
- 0x23 2 0x1F 0x1F
- 0x23 2 0x20 0x1F
- 0x23 2 0x21 0x1F
- 0x23 2 0x22 0x1F
- 0x23 2 0x23 0x1D
- 0x23 2 0x24 0x1D
- 0x23 2 0x25 0x1D
- 0x23 2 0x26 0x1F
- 0x23 2 0x27 0x1F
- 0x23 2 0x28 0x1F
- 0x23 2 0x29 0x1F
- 0x23 2 0x2A 0x1F
- 0x23 2 0x2B 0x1F
- 0x23 2 0x58 0x40
- 0x23 2 0x59 0x00
- 0x23 2 0x5A 0x00
- 0x23 2 0x5B 0x10
- 0x23 2 0x5C 0x07
- 0x23 2 0x5D 0x20
- 0x23 2 0x5E 0x00
- 0x23 2 0x5F 0x00
- 0x23 2 0x61 0x00
- 0x23 2 0x62 0x00
- 0x23 2 0x63 0x7A
- 0x23 2 0x64 0x7A
- 0x23 2 0x65 0x00
- 0x23 2 0x66 0x00
- 0x23 2 0x67 0x32
- 0x23 2 0x68 0x08
- 0x23 2 0x69 0x7A
- 0x23 2 0x6A 0x7A
- 0x23 2 0x6B 0x00
- 0x23 2 0x6C 0x00
- 0x23 2 0x6D 0x00
- 0x23 2 0x6E 0x00
- 0x23 2 0x6F 0x89
- 0x23 2 0x70 0x00
- 0x23 2 0x71 0x00
- 0x23 2 0x72 0x06
- 0x23 2 0x73 0x7B
- 0x23 2 0x74 0x00
- 0x23 2 0x75 0x07
- 0x23 2 0x76 0x00
- 0x23 2 0x77 0x5D
- 0x23 2 0x78 0x17
- 0x23 2 0x79 0x1F
- 0x23 2 0x7A 0x00
- 0x23 2 0x7B 0x00
- 0x23 2 0x7C 0x00
- 0x23 2 0x7D 0x03
- 0x23 2 0x7E 0x7B
- 0x23 2 0xE0 0x03
- 0x23 2 0xAF 0x20
- 0x23 2 0xE0 0x04
- 0x23 2 0x09 0x11
- 0x23 2 0x0E 0x48
- 0x23 2 0x2B 0x2B
- 0x23 2 0x2E 0x44
- 0x23 2 0x41 0xFF
- 0x23 2 0xE0 0x00
- 0x23 2 0xE6 0x02
- 0x23 2 0xE7 0x0C
- 0x23 2 0x51 0xFF
- 0x23 2 0x53 0x2C
- 0x23 2 0x55 0x00
- 0x05 1 0x11
- 0xFF 125 /* Delay 125ms */
- 0x05 1 0x29
- 0xFF 0xFF /* Ending Flag */
- >;
- init_off = <
- 0xff 5
- 0x05 1 0x28 /* display off */
- 0xff 60 /* delay 60ms */
- 0x05 1 0x10 /* sleep in */
- 0xff 110 /* delay 110ms */
- 0xff 0xff>; /* ending */
- };
-
- extern_2{
- index = <2>;
- extern_name = "mipi_default"; // P070ACB_FT9364
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- cmd_size = <0xff>;
- init_on = <
- 0x23 2 0xE0 0x00 /* Page 0 */
- 0x23 2 0xE1 0x93 /* PASSWORD */
- 0x23 2 0xE2 0x65
- 0x23 2 0xE3 0xF8
- 0x23 2 0x80 0x03 /* DSI 4 lane */
- 0x23 2 0xE0 0x01 /* Page 01 */
- 0x23 2 0x0C 0x74 /* Set PWRIC */
- 0x23 2 0x17 0x00 /* Set Gamma Power */
- 0x23 2 0x18 0xEF /* VGMP=5.1V */
- 0x23 2 0x19 0x00 /* VGSP=0V */
- 0x23 2 0x1A 0x00
- 0x23 2 0x1B 0xEF /* VGMN=-5.1V */
- 0x23 2 0x1C 0x00 /* VGSN=0V */
- 0x23 2 0x1F 0x70 /* VGH_REG=16.2V */
- 0x23 2 0x20 0x2D /* VGL_REG=-12V */
- 0x23 2 0x21 0x2D /* VGL_REG2=-12V */
- 0x23 2 0x22 0x7E /* VGH_REG short to VGH VGL_REG short to VGL */
- 0x23 2 0x26 0xF3 /* VDDD from IOVCC/VCI */
- 0x23 2 0x37 0x09 /* SS=1 BGR=1 */
- 0x23 2 0x38 0x04 /* JDT=100 column inversion */
- 0x23 2 0x39 0x00 /* Source EQ Setting EQ1 */
- 0x23 2 0x3A 0x01 /* Source EQ Setting EQ2 */
- 0x23 2 0x3C 0x90 /* Source EQ Setting EQ3 */
- 0x23 2 0x3D 0xFF /* SET Source OP on time */
- 0x23 2 0x3E 0xFF /* SET Source OP off time */
- 0x23 2 0x3F 0xFF /* SET Source OP off time */
- 0x23 2 0x40 0x02 /* RSO=640 RGB */
- 0x23 2 0x41 0x80 /* LN=512->1024 line */
- 0x23 2 0x42 0x99 /* SLT internal line period */
- 0x23 2 0x43 0x14 /* VFP */
- 0x23 2 0x44 0x19 /* VBP */
- 0x23 2 0x45 0x5A /* HBP */
- 0x23 2 0x4B 0x04
- 0x23 2 0x55 0x02 /* DCDCM=0010 FP7721BX2 */
- 0x23 2 0x56 0x01 /* No auto Ratio function */
- 0x23 2 0x57 0x69 /* VGH_RT=3'b011 2*AVDD-AVEE VGL_RT=3'b010=AVEE+VCL-AVDD VCL_RT=2'b00 0.5*VCIP */
- 0x23 2 0x58 0x0A /* AVDD_S */
- 0x23 2 0x59 0x0A /* VCL = -2.5V */
- 0x23 2 0x5A 0x2E /* VGH = 16.2V */
- 0x23 2 0x5B 0x19 /* VGL = -12V */
- 0x23 2 0x5C 0x15 /* pump clk */
- 0x23 2 0x5D 0x71 /* V255 positive voltage from 4.888V to 4.888V */
- 0x23 2 0x5E 0x65 /* V251 positive voltage from 4.533V to 4.718V */
- 0x23 2 0x5F 0x55 /* V247 positive voltage from 4.349V to 4.491V */
- 0x23 2 0x60 0x49 /* V243 positive voltage from 4.179V to 4.321V */
- 0x23 2 0x61 0x46 /* V235 positive voltage from 3.910V to 4.052V */
- 0x23 2 0x62 0x38 /* V227 positive voltage from 3.726V to 3.853V */
- 0x23 2 0x63 0x3D /* V211 positive voltage from 3.428V to 3.528V */
- 0x23 2 0x64 0x29 /* V191 positive voltage from 3.159V to 3.244V */
- 0x23 2 0x65 0x43 /* V159 positive voltage from 2.805V to 2.876V */
- 0x23 2 0x66 0x42 /* V128 positive voltage from 2.522V to 2.578V */
- 0x23 2 0x67 0x44 /* V96 positive voltage from 2.267V to 2.323V */
- 0x23 2 0x68 0x63 /* V64 positive voltage from 1.941V to 2.026V */
- 0x23 2 0x69 0x53 /* V44 positive voltage from 1.686V to 1.799V */
- 0x23 2 0x6A 0x5B /* V28 positive voltage from 1.431V to 1.516V */
- 0x23 2 0x6B 0x4E /* V20 positive voltage from 1.275V to 1.322V */
- 0x23 2 0x6C 0x4C /* V12 positive voltage from 1.077V to 1.077V */
- 0x23 2 0x6D 0x41 /* V8 positive voltage from 0.949V to 0.921V */
- 0x23 2 0x6E 0x2D /* V4 positive voltage from 0.723V to 0.638V */
- 0x23 2 0x6F 0x23 /* V0 positive voltage from 0.496V to 0.496V */
- 0x23 2 0x70 0x71 /* V255 negative voltage from -4.888V to -4.888V */
- 0x23 2 0x71 0x4C /* V251 negative voltage from -4.179V to -4.363V */
- 0x23 2 0x72 0x3B /* V247 negative voltage from -3.995V to -4.123V */
- 0x23 2 0x73 0x30 /* V243 negative voltage from -3.825V to -3.967V */
- 0x23 2 0x74 0x2D /* V233 negative voltage from -3.556V to -3.698V */
- 0x23 2 0x75 0x1F /* V227 negative voltage from -3.372V to -3.499V */
- 0x23 2 0x76 0x25 /* V211 negative voltage from -3.088V to -3.188V */
- 0x23 2 0x77 0x10 /* V191 negative voltage from -2.805V to -2.890V */
- 0x23 2 0x78 0x2A /* V159 negative voltage from -2.451V to -2.522V */
- 0x23 2 0x79 0x2A /* V128 negative voltage from -2.182V to -2.238V */
- 0x23 2 0x7A 0x2B /* V96 negative voltage from -1.913V to -1.969V */
- 0x23 2 0x7B 0x4A /* V64 negative voltage from -1.587V to -1.672V */
- 0x23 2 0x7C 0x3A /* V44 negative voltage from -1.332V to -1.445V */
- 0x23 2 0x7D 0x43 /* V28 negative voltage from -1.091V to -1.176V */
- 0x23 2 0x7E 0x36 /* V20 negative voltage from -0.935V to -0.992V */
- 0x23 2 0x7F 0x33 /* V12 negative voltage from -0.723V to -0.723V */
- 0x23 2 0x80 0x28 /* V8 negative voltage from -0.595V to -0.567V */
- 0x23 2 0x81 0x14 /* V4 negative voltage from -0.368V to -0.283V */
- 0x23 2 0x82 0x0B /* V0 negative voltage from -0.156V to -0.156V */
- 0x23 2 0xE0 0x02 /* Page2 */
- 0x23 2 0x00 0x53 /* GIP_L Pin mapping RESET_EVEN */
- 0x23 2 0x01 0x55 /* VSSG_EVEN */
- 0x23 2 0x02 0x55 /* VSSA_EVEN */
- 0x23 2 0x03 0x51 /* STV2_EVEN */
- 0x23 2 0x04 0x77 /* VDD2_EVEN */
- 0x23 2 0x05 0x57 /* VDD1_EVEN */
- 0x23 2 0x06 0x1F /* VGL */
- 0x23 2 0x07 0x4F /* CK12 */
- 0x23 2 0x08 0x4D /* CK10 */
- 0x23 2 0x09 0x1F /* VGL */
- 0x23 2 0x0A 0x4B /* CK8 */
- 0x23 2 0x0B 0x49 /* CK6 */
- 0x23 2 0x0C 0x1F /* VGL */
- 0x23 2 0x0D 0x47 /* CK4 */
- 0x23 2 0x0E 0x45 /* CK2 */
- 0x23 2 0x0F 0x41 /* STV1_EVEN */
- 0x23 2 0x10 0x1F /* VGL */
- 0x23 2 0x11 0x1F /* VGL */
- 0x23 2 0x12 0x1F /* VGL */
- 0x23 2 0x13 0x55 /* VGG */
- 0x23 2 0x14 0x1F /* VGL */
- 0x23 2 0x15 0x1F /* VGL */
- 0x23 2 0x16 0x52 /* GIP_R Pin mapping RESET_ODD */
- 0x23 2 0x17 0x55 /* VSSG_ODD */
- 0x23 2 0x18 0x55 /* VSSA_ODD */
- 0x23 2 0x19 0x50 /* STV2_ODD */
- 0x23 2 0x1A 0x77 /* VDD2_ODD */
- 0x23 2 0x1B 0x57 /* VDD1_ODD */
- 0x23 2 0x1C 0x1F /* VGL */
- 0x23 2 0x1D 0x4E /* CK11 */
- 0x23 2 0x1E 0x4C /* CK9 */
- 0x23 2 0x1F 0x1F /* VGL */
- 0x23 2 0x20 0x4A /* CK7 */
- 0x23 2 0x21 0x48 /* CK5 */
- 0x23 2 0x22 0x1F /* VGL */
- 0x23 2 0x23 0x46 /* CK3 */
- 0x23 2 0x24 0x44 /* CK1 */
- 0x23 2 0x25 0x40 /* STV1_ODD */
- 0x23 2 0x26 0x1F /* VGL */
- 0x23 2 0x27 0x1F /* VGL */
- 0x23 2 0x28 0x1F /* VGL */
- 0x23 2 0x29 0x1F /* VGL */
- 0x23 2 0x2A 0x1F /* VGL */
- 0x23 2 0x2B 0x55 /* VGG */
- 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping RESET_EVEN */
- 0x23 2 0x2D 0x15 /* VSSG_EVEN */
- 0x23 2 0x2E 0x15 /* VSSA_EVEN */
- 0x23 2 0x2F 0x00 /* STV2_EVEN */
- 0x23 2 0x30 0x17 /* VDD2_EVEN */
- 0x23 2 0x31 0x17 /* VDD1_EVEN */
- 0x23 2 0x32 0x1F /* VGL */
- 0x23 2 0x33 0x08 /* CK12 */
- 0x23 2 0x34 0x0A /* CK10 */
- 0x23 2 0x35 0x1F /* VGL */
- 0x23 2 0x36 0x0C /* CK8 */
- 0x23 2 0x37 0x0E /* CK6 */
- 0x23 2 0x38 0x1F /* VGL */
- 0x23 2 0x39 0x04 /* CK4 */
- 0x23 2 0x3A 0x06 /* CK2 */
- 0x23 2 0x3B 0x10 /* STV1_EVEN */
- 0x23 2 0x3C 0x1F /* VGL */
- 0x23 2 0x3D 0x1F /* VGL */
- 0x23 2 0x3E 0x1F /* VGL */
- 0x23 2 0x3F 0x15 /* VGG */
- 0x23 2 0x40 0x1F /* VGL */
- 0x23 2 0x41 0x1F /* VGL */
- 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping RESET_ODD */
- 0x23 2 0x43 0x15 /* VSSG_ODD */
- 0x23 2 0x44 0x15 /* VSSA_ODD */
- 0x23 2 0x45 0x01 /* STV2_ODD */
- 0x23 2 0x46 0x37 /* VDD2_ODD */
- 0x23 2 0x47 0x17 /* VDD1_ODD */
- 0x23 2 0x48 0x1F /* VGL */
- 0x23 2 0x49 0x09 /* CK11 */
- 0x23 2 0x4A 0x0B /* CK9 */
- 0x23 2 0x4B 0x1F /* VGL */
- 0x23 2 0x4C 0x0D /* CK7 */
- 0x23 2 0x4D 0x0F /* CK5 */
- 0x23 2 0x4E 0x1F /* VGL */
- 0x23 2 0x4F 0x05 /* CK3 */
- 0x23 2 0x50 0x07 /* CK1 */
- 0x23 2 0x51 0x11 /* STV1_ODD */
- 0x23 2 0x52 0x1F /* VGL */
- 0x23 2 0x53 0x1F /* VGL */
- 0x23 2 0x54 0x1F /* VGL */
- 0x23 2 0x55 0x1F /* VGL */
- 0x23 2 0x56 0x1F /* VGL */
- 0x23 2 0x57 0x15 /* VGG */
- 0x23 2 0x58 0x40 /* GAS OPT=1 for abnormal power off */
- 0x23 2 0x59 0x00 /* INIT_W */
- 0x23 2 0x5A 0x00 /* INIT[7:0] */
- 0x23 2 0x5B 0x10 /* STV_NUM STV_S0[10:8] */
- 0x23 2 0x5C 0x14 /* STV_S0[7:0] */
- 0x23 2 0x5D 0x40 /* STV_W STV_S1 */
- 0x23 2 0x5E 0x01 /* STV_S2 */
- 0x23 2 0x5F 0x02 /* STV_S3 */
- 0x23 2 0x60 0x40 /* ETV_W ETV_S1 */
- 0x23 2 0x61 0x03 /* ETV_S2 */
- 0x23 2 0x62 0x04 /* ETV_S3 */
- 0x23 2 0x63 0x7A /* SETV_ON for STV/ETV on time */
- 0x23 2 0x64 0x7A /* SETV_OFF for STV/ETV off time */
- 0x23 2 0x65 0x74 /* ETV_EN ETV_NUM ETV_S0 */
- 0x23 2 0x66 0x16 /* ETV_S0 */
- 0x23 2 0x67 0xB4 /* CKV0_NUM CKV0_W */
- 0x23 2 0x68 0x16 /* CKV0_S0 */
- 0x23 2 0x69 0x7A /* CKV0_on */
- 0x23 2 0x6A 0x7A /* CKV0_off time */
- 0x23 2 0x6B 0x0C /* CKV0_DUM */
- 0x23 2 0x6C 0x00 /* GIP Line EQ option */
- 0x23 2 0x6D 0x04 /* GIP rising EQ */
- 0x23 2 0x6E 0x04 /* GIP fallig EQ */
- 0x23 2 0x6F 0x88 /* GIP_DR CKV0_CON CKV1_CON */
- 0x23 2 0x70 0x00 /* CKV1_NUM CKV0_W */
- 0x23 2 0x71 0x00 /* CKV1_S0 */
- 0x23 2 0x72 0x06 /* CKV1_on */
- 0x23 2 0x73 0x7B /* CKV1_off time */
- 0x23 2 0x74 0x00 /* CKV1_DUM */
- 0x23 2 0x75 0xBC /* FLM_EN FLM_W */
- 0x23 2 0x76 0x00 /* FLM on time */
- 0x23 2 0x77 0x04 /* VEN_EN VEN_W FLM_NUM FLM_OFF */
- 0x23 2 0x78 0x2C /* FLM_OFF */
- 0x23 2 0x79 0x00 /* VEN_W */
- 0x23 2 0x7A 0x00 /* VEN_S0 */
- 0x23 2 0x7B 0x00 /* VEN_S1 */
- 0x23 2 0x7C 0x00 /* VEN_DUM */
- 0x23 2 0x7D 0x03 /* VEN on time */
- 0x23 2 0x7E 0x7B /* VEN off time */
- 0x23 2 0xE0 0x03 /* Page3 */
- 0x23 2 0xAF 0x20 /* Set CABC */
- 0x23 2 0xE0 0x04 /* Page4 */
- 0x23 2 0x09 0x11 /* Source level at blanking period */
- 0x23 2 0x0E 0x48 /* Source EQ option */
- 0x23 2 0x2B 0x2B /* ESD Protect */
- 0x23 2 0x2E 0x44 /* Special Packet disable */
- 0x23 2 0x41 0xFF /* Set CABC */
- 0x23 2 0xE0 0x00 /* Page0 */
- 0x23 2 0xE6 0x02 /* Enable Watch Dog */
- 0x23 2 0xE7 0x0C /* Watch Dog timer setting */
- 0x23 2 0x51 0xFF /* CABC Option 0x80=50% duty 0xFF=100% */
- 0x23 2 0x53 0x2C
- 0x23 2 0x55 0x00
- 0x05 1 0x11 /* Sleep Out */
- 0xFF 125 /* Delay 125ms */
- 0x05 1 0x29 /* Display On */
- 0xFF 0xFF /* Ending */
- >;
- init_off = <
- 0xff 5
- 0x05 1 0x28 /* display off */
- 0xff 60 /* delay 60ms */
- 0x05 1 0x10 /* sleep in */
- 0xff 110 /* delay 110ms */
- 0xff 0xff>; /* ending */
- };
-
- extern_3{
- index = <3>;
- extern_name = "mipi_default"; // KD070D82_FT9364
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- cmd_size = <0xff>;
- init_on = <
- 0x23 2 0xE0 0x00 /* Register setting change to Page 0 */
- 0x23 2 0xE1 0x93 /* PASSWORD, setting as 93-65-F8 to enable page1-4 command access */
- 0x23 2 0xE2 0x65
- 0x23 2 0xE3 0xF8
- 0x23 2 0x80 0x03 /* Setting DSI lane number, 0x03 is DSI 4 lane */
- 0x23 2 0xE0 0x01 /* Register setting change to Page 1 */
- 0x23 2 0x00 0x00 /* Set VCOM_Forward */
- 0x23 2 0x01 0x9E /* VCOM=0x09F */
- 0x23 2 0x03 0x00 /* Set VCOM_Reverse */
- 0x23 2 0x04 0xAA /* VCOMR=0x0AA, -1.40V */
- 0x23 2 0x0C 0x74 /* Set PWRIC pumping frequency,=8 HCLK, about 512KHz */
- 0x23 2 0x17 0x00 /* Set Gamma Power, VGMP[8]=0, VGSP[8]=0 */
- 0x23 2 0x18 0xEF /* VGMP[8:0]=0x0EF=5.1V */
- 0x23 2 0x19 0x00 /* VGSP[8:0]=0x000=0V */
- 0x23 2 0x1A 0x00 /* VGMN[8]=0, VGSN[8]=0 */
- 0x23 2 0x1B 0xEF /* VGMN[8:0]=0x0EF=-5.1V */
- 0x23 2 0x1C 0x00 /* VGSN[8:0]=0x000=0V */
- 0x23 2 0x1F 0x70 /* VGH_REG=16.2V */
- 0x23 2 0x20 0x2D /* VGL_REG=-12V */
- 0x23 2 0x21 0x2D /* VGL_REG2=-12V */
- 0x23 2 0x22 0x7E /* VGH_REG short to VGH, VGL_REG short to VGL, */
- 0x23 2 0x26 0xF3 /* VDDD from IOVCC&VCI */
- 0x23 2 0x37 0x09 /* SS=1, source scan from S2400 to S1;BGR=1 CF type is (S1,S2,S3) align to (B,G,R) */
- 0x23 2 0x38 0x04 /* JDT=100, display inversion type is column inversion */
- 0x23 2 0x39 0x00 /* Source EQ Setting, EQ1, 0x00=0us */
- 0x23 2 0x3A 0x01 /* Source EQ Setting, EQ2, 0x01 =0.1us */
- 0x23 2 0x3C 0x90 /* Source EQ Setting, EQ3, EQ3 start at 14.4us */
- 0x23 2 0x3D 0xFF /* SET Source OP on time, 0xFF means source op always on */
- 0x23 2 0x3E 0xFF /* SET Source OP off time, 0xFF means source op always on */
- 0x23 2 0x3F 0xFF /* SET Source OP off time, 0xFF means source op always on */
- 0x23 2 0x40 0x02 /* horizontal resolution setting,RSO[2:0]= 0x02 =600RGB, LN[1:0]=2'b00 */
- 0x23 2 0x41 0x80 /* LN[9:0]=0x200=512, vertical resolution is 512*2=1024 line */
- 0x23 2 0x42 0x99 /* SLT, internal line period=0x99->15.3us */
- 0x23 2 0x43 0x14 /* Internal VFP=Ext_VFP=20(0x14) */
- 0x23 2 0x44 0x19 /* Internal _VBP=Ext_VS+Ext_VBP-1=6+20-1=25(0x19) */
- 0x23 2 0x45 0x5A /* Internal_HBP=Ext_HS+Ext_HBP=90(0x5A) */
- 0x23 2 0x55 0x02 /* Seting PWRIC mode, DCDCM=0010-> FP7721BX2 */
- 0x23 2 0x56 0x01 /* No auto Ratio function */
- 0x23 2 0x57 0x69 /* VGH_RT=3'b011,2*AVDD-AVEE,VGL_RT=3'b010=AVEE+VCL-AVDD,VCL_RT=2'b00,0.5*VCIP */
- 0x23 2 0x58 0x0A /* AVDD_S, not use internal AVDD in this model */
- 0x23 2 0x59 0x0A /* VCL = -2.5V */
- 0x23 2 0x5A 0x2E /* VGH = 16.2V */
- 0x23 2 0x5B 0x19 /* VGL = -12V */
- 0x23 2 0x5C 0x15 /* pump clk, VCL_CLK[1:0]=2'b01=HCLK/2=32KHz, VGHVGL_CLK[1:0]=2'b01=HCLK/2=32KHz */
- 0x23 2 0x5D 0x77 /* Gamma voltage setting, VP255-4.793V */
- 0x23 2 0x5E 0x5C /* VP251 */
- 0x23 2 0x5F 0x4D /* VP247 */
- 0x23 2 0x60 0x40 /* VP243 */
- 0x23 2 0x61 0x3D /* VP235 */
- 0x23 2 0x62 0x2F /* VP227 */
- 0x23 2 0x63 0x34 /* VP211 */
- 0x23 2 0x64 0x1F /* VP191 */
- 0x23 2 0x65 0x38 /* VP159 */
- 0x23 2 0x66 0x38 /* VP128 */
- 0x23 2 0x67 0x39 /* VP96 */
- 0x23 2 0x68 0x58 /* VP64 */
- 0x23 2 0x69 0x48 /* VP44 */
- 0x23 2 0x6A 0x51 /* VP28 */
- 0x23 2 0x6B 0x44 /* VP20 */
- 0x23 2 0x6C 0x41 /* VP12 */
- 0x23 2 0x6D 0x35 /* VP8 */
- 0x23 2 0x6E 0x24 /* VP4 */
- 0x23 2 0x6F 0x02 /* VP0 */
- 0x23 2 0x70 0x77 /* VN255 */
- 0x23 2 0x71 0x5C /* VN251 */
- 0x23 2 0x72 0x4D /* VN247 */
- 0x23 2 0x73 0x40 /* VN243 */
- 0x23 2 0x74 0x3D /* VN235 */
- 0x23 2 0x75 0x2F /* VN227 */
- 0x23 2 0x76 0x34 /* VN211 */
- 0x23 2 0x77 0x1F /* VN191 */
- 0x23 2 0x78 0x38 /* VN159 */
- 0x23 2 0x79 0x38 /* VN128 */
- 0x23 2 0x7A 0x39 /* VN96 */
- 0x23 2 0x7B 0x58 /* VN64 */
- 0x23 2 0x7C 0x48 /* VN44 */
- 0x23 2 0x7D 0x51 /* VN28 */
- 0x23 2 0x7E 0x44 /* VN20 */
- 0x23 2 0x7F 0x41 /* VN12 */
- 0x23 2 0x80 0x35 /* VN8 */
- 0x23 2 0x81 0x24 /* VN4 */
- 0x23 2 0x82 0x02 /* VN0 */
- 0x23 2 0xE0 0x02 /* Register setting change to Page 2 */
- 0x23 2 0x00 0x53 /* GIP_L_Forward scan mapping, assign as RESET_EVEN */
- 0x23 2 0x01 0x55 /* assign as VSSG_EVEN */
- 0x23 2 0x02 0x55 /* assign as VSSA_EVEN */
- 0x23 2 0x03 0x51 /* assign as STV2_EVEN */
- 0x23 2 0x04 0x77 /* assign as VDD2_EVEN */
- 0x23 2 0x05 0x57 /* assign as VDD1_EVEN */
- 0x23 2 0x06 0x1F /* assign as VGL */
- 0x23 2 0x07 0x4F /* assign as CK12 */
- 0x23 2 0x08 0x4D /* assign as CK10 */
- 0x23 2 0x09 0x1F /* assign as VGL */
- 0x23 2 0x0A 0x4B /* assign as CK8 */
- 0x23 2 0x0B 0x49 /* assign as CK6 */
- 0x23 2 0x0C 0x1F /* assign as VGL */
- 0x23 2 0x0D 0x47 /* assign as CK4 */
- 0x23 2 0x0E 0x45 /* assign as CK2 */
- 0x23 2 0x0F 0x41 /* assign as STV1_EVEN */
- 0x23 2 0x10 0x1F /* assign as VGL */
- 0x23 2 0x11 0x1F /* assign as VGL */
- 0x23 2 0x12 0x1F /* assign as VGL */
- 0x23 2 0x13 0x55 /* assign as VGG */
- 0x23 2 0x14 0x1F /* assign as VGL */
- 0x23 2 0x15 0x1F /* assign as VGL */
- 0x23 2 0x16 0x52 /* GIP_R_Forward scan mapping, assign as RESET_ODD */
- 0x23 2 0x17 0x55 /* assign as VSSG_ODD */
- 0x23 2 0x18 0x55 /* assign as VSSA_ODD */
- 0x23 2 0x19 0x50 /* assign as STV2_ODD */
- 0x23 2 0x1A 0x77 /* assign as VDD2_ODD */
- 0x23 2 0x1B 0x57 /* assign as VDD1_ODD */
- 0x23 2 0x1C 0x1F /* assign as VGL */
- 0x23 2 0x1D 0x4E /* assign as CK11 */
- 0x23 2 0x1E 0x4C /* assign as CK9 */
- 0x23 2 0x1F 0x1F /* assign as VGL */
- 0x23 2 0x20 0x4A /* assign as CK7 */
- 0x23 2 0x21 0x48 /* assign as CK5 */
- 0x23 2 0x22 0x1F /* assign as VGL */
- 0x23 2 0x23 0x46 /* assign as CK3 */
- 0x23 2 0x24 0x44 /* assign as CK1 */
- 0x23 2 0x25 0x40 /* assign as STV1_ODD */
- 0x23 2 0x26 0x1F /* assign as VGL */
- 0x23 2 0x27 0x1F /* assign as VGL */
- 0x23 2 0x28 0x1F /* assign as VGL */
- 0x23 2 0x29 0x1F /* assign as VGL */
- 0x23 2 0x2A 0x1F /* assign as VGL */
- 0x23 2 0x2B 0x55 /* assign as VGG */
- 0x23 2 0x2C 0x12 /* GIP_L_Reverse Scan mapping, assign as RESET_EVEN */
- 0x23 2 0x2D 0x15 /* assign as VSSG_EVEN */
- 0x23 2 0x2E 0x15 /* assign as VSSA_EVEN */
- 0x23 2 0x2F 0x00 /* assign as STV2_EVEN */
- 0x23 2 0x30 0x17 /* assign as VDD2_EVEN */
- 0x23 2 0x31 0x17 /* assign as VDD1_EVEN */
- 0x23 2 0x32 0x1F /* assign as VGL */
- 0x23 2 0x33 0x08 /* assign as CK12 */
- 0x23 2 0x34 0x0A /* assign as CK10 */
- 0x23 2 0x35 0x1F /* assign as VGL */
- 0x23 2 0x36 0x0C /* assign as CK8 */
- 0x23 2 0x37 0x0E /* assign as CK6 */
- 0x23 2 0x38 0x1F /* assign as VGL */
- 0x23 2 0x39 0x04 /* assign as CK4 */
- 0x23 2 0x3A 0x06 /* assign as CK2 */
- 0x23 2 0x3B 0x10 /* assign as STV1_EVEN */
- 0x23 2 0x3C 0x1F /* assign as VGL */
- 0x23 2 0x3D 0x1F /* assign as VGL */
- 0x23 2 0x3E 0x1F /* assign as VGL */
- 0x23 2 0x3F 0x15 /* assign as VGG */
- 0x23 2 0x40 0x1F /* assign as VGL */
- 0x23 2 0x41 0x1F /* assign as VGL */
- 0x23 2 0x42 0x13 /* GIP_R_Reverse Scan mapping, assign as RESET_ODD */
- 0x23 2 0x43 0x15 /* assign as VSSG_ODD */
- 0x23 2 0x44 0x15 /* assign as VSSA_ODD */
- 0x23 2 0x45 0x01 /* assign as STV2_ODD */
- 0x23 2 0x46 0x17 /* assign as VDD2_ODD */
- 0x23 2 0x47 0x17 /* assign as VDD1_ODD */
- 0x23 2 0x48 0x1F /* assign as VGL */
- 0x23 2 0x49 0x09 /* assign as CK11 */
- 0x23 2 0x4A 0x0B /* assign as CK9 */
- 0x23 2 0x4B 0x1F /* assign as VGL */
- 0x23 2 0x4C 0x0D /* assign as CK7 */
- 0x23 2 0x4D 0x0F /* assign as CK5 */
- 0x23 2 0x4E 0x1F /* assign as VGL */
- 0x23 2 0x4F 0x05 /* assign as CK3 */
- 0x23 2 0x50 0x07 /* assign as CK1 */
- 0x23 2 0x51 0x11 /* assign as STV1_ODD */
- 0x23 2 0x52 0x1F /* assign as VGL */
- 0x23 2 0x53 0x1F /* assign as VGL */
- 0x23 2 0x54 0x1F /* assign as VGL */
- 0x23 2 0x55 0x1F /* assign as VGL */
- 0x23 2 0x56 0x1F /* assign as VGL */
- 0x23 2 0x57 0x15 /* assign as VGG */
- 0x23 2 0x58 0x40 /* GAS OPT=1, When abnormal power off, GIP will pull to VGH */
- 0x23 2 0x59 0x00 /* INIT_W=0, no INIT function in this panel */
- 0x23 2 0x5A 0x00 /* INIT[10:0], no INIT function in this panel */
- 0x23 2 0x5B 0x10 /* STV_NUM,STV_S0[10:8], 2 STV pulses */
- 0x23 2 0x5C 0x14 /* STV_S0[7:0], STV start from 21th hsync after vsync */
- 0x23 2 0x5D 0x40 /* STV_W=4, STV width is 4 Hline; STV1 delay 1 hline with STV0 */
- 0x23 2 0x5E 0x01 /* STV_S2, STV2 delay 2 hline with STV0 */
- 0x23 2 0x5F 0x02 /* STV_S3, STV3 delay 3 hline with STV0 */
- 0x23 2 0x60 0x40 /* ETV_W=4, ETV witdh is 4 hline; ETV1 delay 1 hilne from ETV0 */
- 0x23 2 0x61 0x03 /* ETV_S2, ETV2 delay 4 hline with ETV0 */
- 0x23 2 0x62 0x04 /* ETV_S3, ETV3 delay 5 hline with ETV0 */
- 0x23 2 0x63 0x7A /* SETV_ON for STV/ETV on time, rising at 12.2us after hsync */
- 0x23 2 0x64 0x7A /* SETV_OFF for STV/ETV off time , falling at 12.2us after hsync */
- 0x23 2 0x65 0x74 /* ETV_EN=1, enable ETV function; ETV_NUM=3, using 4 ETV pulse, */
- 0x23 2 0x66 0x16 /* ETV_S0=0x416, EVT start at 1046th hsync fater vaync */
- 0x23 2 0x67 0xB4 /* CKV_NUM=2'b1011, using 12 CKV pulse; CKV0_W=4. CKV width is 4 hline */
- 0x23 2 0x68 0x16 /* CKV0_S0 , CKV start from 23th hsync after vsync */
- 0x23 2 0x69 0x7A /* CKV0_on ,for CKV on time, rising at 12.2us after hsync */
- 0x23 2 0x6A 0x7A /* CKV0_off ,for CKV off time, falling at 12.2us after hsync */
- 0x23 2 0x6B 0x0C /* CKV0_DUM, total CKV pulse number=1024+12=1036 */
- 0x23 2 0x6C 0x00 /* GIP Line EQ option , disable GEQ_Line function */
- 0x23 2 0x6D 0x04 /* GIP rising EQ, period is 0.4us */
- 0x23 2 0x6E 0x04 /* GIP fallig EQ, period is 0.4us */
- 0x23 2 0x6F 0x88 /* GIP_DR; CKV0_CON, no continuous CKV0; CKV1_CON, no continuous CKV1 */
- 0x23 2 0x70 0x00 /* CKV1_NUM, CKV0_W , no CKV group 1 function in this panel, don't care */
- 0x23 2 0x71 0x00 /* CKV1_S0, no CKV group 1 function in this panel, don't care */
- 0x23 2 0x72 0x06 /* CKV1_on , no CKV group 1 function in this panel, don't care */
- 0x23 2 0x73 0x7B /* CKV1_off time, no CKV group 1 function in this panel, don't care */
- 0x23 2 0x74 0x00 /* CKV1_DUM, no CKV group 1 function in this panel, don't care */
- 0x23 2 0x75 0xBC /* FLM_EN, enable FLM function; FLM_W=0x3C, FLM toggle period is 60 frame */
- 0x23 2 0x76 0x00 /* FLM on time , FLM on(rising) at 1st hsync after vsync */
- 0x23 2 0x77 0x04 /* VEN_EN, VEN_W, no VEN function in this panel, don't care */
- 0x23 2 0x78 0x2C /* FLM_OFF, FLM off(falling) at 1068th hsync after vsync */
- 0x23 2 0x79 0x00 /* VEN_W , no VEN function in this panel, don't care */
- 0x23 2 0x7A 0x00 /* VEN_S0 , no VEN function in this panel, don't care */
- 0x23 2 0x7B 0x00 /* VEN_S1 , no VEN function in this panel, don't care */
- 0x23 2 0x7C 0x00 /* VEN_DUM , no VEN function in this panel, don't care */
- 0x23 2 0x7D 0x03 /* VEN on time , no VEN function in this panel, don't care */
- 0x23 2 0x7E 0x7B /* VEN off time , no VEN function in this panel, don't care */
- 0x23 2 0xE0 0x03 /* Register setting change to Page 3 */
- 0x23 2 0xAF 0x20 /* Set CABC, disable CABC TP detect, for CABC pattern change more smooth */
- 0x23 2 0xE0 0x04 /* Register setting change to Page 4 */
- 0x23 2 0x09 0x11 /* Source level at blanking period, sweeping V0 level */
- 0x23 2 0x0E 0x48 /* Source EQ option, EQ to PCAP,NCAP */
- 0x23 2 0x2B 0x2B /* ESD Protect, clock lane op behavior follow data lane, improve ESD performance */
- 0x23 2 0x2E 0x44 /* ESD protect, disable special packet */
- 0x23 2 0x41 0xFF /* Set CABC, for CABC pattern change more smooth */
- 0x23 2 0xE0 0x00 /* Register setting change to Page 0 */
- 0x23 2 0xE6 0x02 /* Enable Watch Dog */
- 0x23 2 0xE7 0x0C /* Watch Dog timer setting, WD alarm time is 12*512osc after hsync stop */
- 0x23 2 0x51 0xFF /* CABC Option, 0x80=50% duty, 0xFF=100% */
- 0x23 2 0x53 0x2C /* enable dimming, BCTRL, BL */
- 0x23 2 0x55 0x00 /* CABC mode, 0x00 is manual mode */
- 0x05 1 0x11 /* SLPOUT */
- 0xFF 125 /* Delay 125ms */
- 0x05 1 0x29 /* Display On */
- 0xFF 0xFF /* Ending */
- >;
- init_off = <
- 0xff 5
- 0x05 1 0x28 /* display off */
- 0xff 60 /* delay 60ms */
- 0x05 1 0x10 /* sleep in */
- 0xff 110 /* delay 110ms */
- 0xff 0xff>; /* ending */
- };
- };
-
- backlight{
- compatible = "amlogic, backlight-g12a";
- status = "okay";
- key_valid = <0>;
- pinctrl-names = "pwm_on","pwm_off";
- pinctrl-0 = <&pwm_f_pins2>;
- pinctrl-1 = <&bl_pwm_off_pins>;
- pinctrl_version = <2>; /* for uboot */
- bl_pwm_config = <&bl_pwm_conf>;
- bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH
- &gpio GPIOH_5 GPIO_ACTIVE_HIGH>;
- bl_gpio_names = "GPIOH_4","GPIOH_5";
-
- /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/
- /* power index:(point gpios_index, 0xff=invalid)
- * power value:(0=output low, 1=output high, 2=input)
- * power delay:(unit in ms)
- */
-
- backlight_0{
- index = <0>;
- bl_name = "backlight_pwm";
- bl_level_default_uboot_kernel = <100 100>;
- bl_level_attr = <255 10 /*max, min*/
- 128 128>; /*mid, mid_mapping*/
- bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */
- bl_power_attr = <0 /*en_gpio_index*/
- 1 0 /*on_value, off_value*/
- 200 200>; /*on_delay(ms), off_delay(ms)*/
- bl_pwm_port = "PWM_F";
- bl_pwm_attr = <0 /*pwm_method*/
- 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/
- 100 25>; /*duty_max(%), duty_min(%)*/
- bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/
- 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/
- bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */
- };
- backlight_1{
- index = <1>;
- bl_name = "bl_extern";
- bl_level_default_uboot_kernel = <100 100>;
- bl_level_attr = <255 10 /*max, min*/
- 128 128>; /*mid, mid_mapping*/
- bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/
- bl_power_attr = <1 /*en_gpio_index*/
- 1 0 /*on_value, off_value*/
- 200 200>; /*on_delay(ms), off_delay(ms)*/
- bl_extern_index = <0>;
- };
- };
- bl_pwm_conf:bl_pwm_conf{
- pwm_channel_0 {
- pwm_port_index = <5>;
- pwms = <&pwm_ef MESON_PWM_1 30040 0>;
- };
- };
-
- bl_extern{
- compatible = "amlogic, bl_extern";
- status = "disabled";
- i2c_bus = "i2c_bus_3";
-
- extern_0{
- index = <0>;
- extern_name = "i2c_lp8556";
- type = <0>; /*0=i2c, 1=spi, 2=mipi*/
- i2c_address = <0x2c>; /*7bit i2c address*/
- dim_max_min = <255 10>;
- };
-
- extern_1{
- index = <1>;
- extern_name = "mipi_lt070me05";
- type = <2>; /*0=i2c, 1=spi, 2=mipi*/
- dim_max_min = <255 10>;
- };
- };
-};/* end of panel */
diff --git a/arch/arm/dts/meson-a-series.dtsi b/arch/arm/dts/meson-a-series.dtsi
new file mode 100644
index 0000000..ccdac71
--- /dev/null
+++ b/arch/arm/dts/meson-a-series.dtsi
@@ -0,0 +1,525 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pwm/meson.h>
+#include <dt-bindings/clock/a1-clkc.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 16 MiB reserved for Hardware ROM Firmware */
+ hwrom_reserved: hwrom@0 {
+ reg = <0x0 0x0 0x0 0x1000000>;
+ no-map;
+ };
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@10000000 {
+ reg = <0x0 0x10000000 0x0 0x200000>;
+ no-map;
+ };
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0xbc00000>;
+ alignment = <0x0 0x400000>;
+ linux,cma-default;
+ };
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+
+ firmware {
+ sm: secure-monitor {
+ compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
+ };
+ };
+
+ efuse: efuse {
+ compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sn: sn@14 {
+ reg = <0x14 0x10>;
+ };
+
+ eth_mac: eth_mac@34 {
+ reg = <0x34 0x10>;
+ };
+
+ bid: bid@46 {
+ reg = <0x46 0x30>;
+ };
+ };
+
+ scpi {
+ compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
+ mboxes = <&mailbox 1 &mailbox 2>;
+ shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+
+ scpi_clocks: clocks {
+ compatible = "arm,scpi-clocks";
+
+ scpi_dvfs: scpi_clocks@0 {
+ compatible = "arm,scpi-dvfs-clocks";
+ #clock-cells = <1>;
+ clock-indices = <0>;
+ clock-output-names = "vcpu";
+ };
+ };
+
+ scpi_sensors: sensors {
+ compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@2c001000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xffc01000 0 0x1000>,
+ <0x0 0xffc02000 0 0x2000>,
+ <0x0 0xffc04000 0 0x2000>,
+ <0x0 0xffc06000 0 0x2000>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ };
+
+ sram: sram@fffa0000 {
+ compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram";
+ reg = <0x0 0xfffa0000 0x0 0x48000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0xfffa0000 0x48000>;
+
+ cpu_scp_lpri: scp-shmem@0 {
+ compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
+ reg = <0x47000 0x400>;
+ };
+
+ cpu_scp_hpri: scp-shmem@200 {
+ compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
+ reg = <0x47400 0x400>;
+ };
+ };
+
+ cbus: cbus@fe000000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xfe000000 0x0 0x8000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x8000>;
+
+ uart_a: serial@1c00 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x1c00 0x0 0x14>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ uart_b: serial@2000 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x2000 0x0 0x14>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ pwm_ab: pwm@2400 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0x2400 0x0 0x20>,
+ <0x0 0x08c4 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_cd: pwm@2800 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0x2800 0x0 0x20>,
+ <0x0 0x08c8 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_ef: pwm@5400 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0x5400 0x0 0x20>,
+ <0x0 0x08cc 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ ir: ir@8040 {
+ compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
+ reg = <0x0 0x8040 0x0 0x40>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ reset: reset-controller@1000 {
+ compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
+ reg = <0x0 0x01000 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
+ uart_c: serial@22000 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x22000 0x0 0x18>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ spicc0: spi@3800 {
+ compatible = "amlogic,meson-g12a-spicc";
+ reg = <0x0 0x3800 0x0 0x44>;
+ interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spifc: spi@14000 {
+ compatible = "amlogic,spifc";
+ reg = <0x0 0x14000 0x0 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ spi-flash@0 {
+ reg = <0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ compatible = "spi-flash";
+ status = "okay";
+ };
+ spi-nand@1 {
+ reg = <1>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ compatible = "spi-nand";
+ status = "okay";
+ };
+ };
+
+ watchdog@0f0d0 {
+ compatible = "amlogic,meson-a1-wdt";
+ reg = <0x0 0x0f0d0 0x0 0x10>;
+ clocks = <&xtal>;
+ clock-names = "wdt-clk";
+ };
+
+ jtag {
+ compatible = "amlogic, jtag";
+ status = "okay";
+ select = "disable"; /* disable/jtag-a/swd-a */
+ pinctrl-names="jtag_a_pins", "swd_a_pins";
+ pinctrl-0=<&jtag_a_pins>;
+ pinctrl-1=<&swd_a_pins>;
+ };
+ };
+
+ periphs: periphs@ff634000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xff634000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
+
+ hwrng: rng {
+ compatible = "amlogic,meson-rng";
+ reg = <0x0 0x0 0x0 0x4>;
+ };
+ };
+
+ hiubus: hiubus@ff63c000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xff63c000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>;
+
+ mailbox: mailbox@404 {
+ compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
+ reg = <0 0x404 0 0x4c>;
+ interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
+ <0 209 IRQ_TYPE_EDGE_RISING>,
+ <0 210 IRQ_TYPE_EDGE_RISING>;
+ #mbox-cells = <1>;
+ };
+ };
+
+ clkc: clock-controller@0 {
+ compatible = "amlogic,a1-clkc";
+ #clock-cells = <1>;
+ reg = <0x0 0xfe000800 0x0 0xe4>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ };
+
+ i2c0: i2c@fe001400 {
+ compatible = "amlogic,meson-a1-i2c";
+ reg = <0x0 0xfe001400 0x0 0x24>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_I2C_M_A>;
+ clock-names = "clk_i2c";
+ status = "disabled";
+ };
+
+ i2c1: i2c@fe005c00 {
+ compatible = "amlogic,meson-a1-i2c";
+ reg = <0x0 0xfe005c00 0x0 0x24>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_I2C_M_B>;
+ clock-names = "clk_i2c";
+ status = "disabled";
+ };
+
+ i2c2: i2c@fe006800 {
+ compatible = "amlogic,meson-a1-i2c";
+ reg = <0x0 0xfe006800 0x0 0x24>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_I2C_M_C>;
+ clock-names = "clk_i2c";
+ status = "disabled";
+ };
+
+ i2c3: i2c@fe006c00 {
+ compatible = "amlogic,meson-a1-i2c";
+ reg = <0x0 0xfe006c00 0x0 0x24>;
+ #address-cells = <2>;
+ #size-cells = <0>;
+ clocks = <&clkc CLKID_I2C_M_D>;
+ clock-names = "clk_i2c";
+ status = "disabled";
+ };
+
+ ethmac: ethernet@ff3f0000 {
+ compatible = "amlogic,g12a-eth-dwmac";
+ phy_cntl1 = <0x41054147>;
+ pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>;
+ analog_val = <0x20200000 0x0000c000 0x00000023>;
+ status = "disabled";
+ };
+
+ saradc: adc@ff809000 {
+ compatible = "amlogic,meson-saradc";
+ reg = <0x0 0xfe002c00 0x0 0x48>;
+ status = "disabled";
+ };
+
+ nand: nfc@ffe07800 {
+ compatible = "amlogic,meson-nfc";
+ reg = <0x0 0xFFE07800 0x0 0x200>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ clk_reg = <0 0xFFE07000>;
+ };
+
+ apb: apb@ffe01000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xffe01000 0x0 0x7f000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xffe01000 0x0 0x7f000>;
+
+ sd_emmc_a: mmc@2000 {
+ compatible = "";
+ reg = <0x0 0x2000 0x0 0x800>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ sd_emmc_b: mmc@4000 {
+ compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
+ reg = <0x0 0x4000 0x0 0x800>;
+ interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ sd_emmc_c: mmc@6000 {
+ compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
+ reg = <0x0 0x6000 0x0 0x800>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+ };
+
+ dwc3: dwc3@ff400000 {
+ compatible = "snps,dwc3","synopsys,xhci-dwc3";
+ status = "disable";
+ reg = <0x0 0xff400000 0x0 0x100000>;
+ phys = <&usb2_phy_v2>, <&usb3_phy_v2>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ usb2_phy_v2: usb2phy@fe004420 {
+ compatible = "amlogic, amlogic-new-usb2-v2";
+ status = "disable";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ phy-version = <2>;
+ reg = <0x0 0xfe004420 0x0 0x60
+ 0x0 0xfe000004 0x0 0x100
+ 0x0 0xfe004000 0x0 0x2000
+ 0x0 0xfe0008dc 0x0 0x4>;
+ dwc2_a_reg = <0xff500000>;
+ #phy-cells = <0>;
+ };
+
+ usb3_phy_v2: usb3phy@fe004480 {
+ compatible = "amlogic, amlogic-new-usb3-v2";
+ status = "disable";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ phy-version = <3>;
+ reg = <0x0 0xfe004480 0x0 0x20>;
+ #phy-cells = <0>;
+ };
+
+ };
+};
diff --git a/arch/arm/dts/meson-a1-a113l-ad401.dts b/arch/arm/dts/meson-a1-a113l-ad401.dts
new file mode 100644
index 0000000..54d5bc6
--- /dev/null
+++ b/arch/arm/dts/meson-a1-a113l-ad401.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-a1-a113l-ad401.dtsi"
+#include "meson-a1_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,ad401", "amlogic,a113l", "amlogic,meson-a1";
+ model = "Amlogic Meson A1 AD401 Development Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-a1-a113l-ad401.dtsi b/arch/arm/dts/meson-a1-a113l-ad401.dtsi
new file mode 100644
index 0000000..bb9ff07
--- /dev/null
+++ b/arch/arm/dts/meson-a1-a113l-ad401.dtsi
@@ -0,0 +1,311 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-a1-a113l.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_b;
+ serial1 = &uart_a;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ leds {
+ compatible = "pwm-leds";
+ status = "okay";
+
+ red {
+ label = "led_red";
+ pwms = <&pwm_cd MESON_PWM_0 10000000 0>;
+ max-brightness=<255>;
+ default-brightness=<255>;
+ };
+
+ green {
+ label = "led_green";
+ pwms = <&pwm_ab MESON_PWM_1 10000000 0>;
+ max-brightness=<255>;
+ default-brightness=<255>;
+ };
+
+ blue {
+ label = "led_blue";
+ pwms = <&pwm_ab MESON_PWM_0 10000000 0>;
+ max-brightness=<255>;
+ default-brightness=<255>;
+ };
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /* pinctrl-0 = <&sdio_pins>; */
+ /* pinctrl-names = "default"; */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "disabled";
+ /*pinctrl-0 = <&sd_all_pins>;*/
+ /*pinctrl-names = "default";*/
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+ card_type = <5>;
+
+ /* cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; */
+ /* cd-inverted; */
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "disabled";
+ /* pinctrl-0 = <&emmc_conf_pull_up &emmc_conf_pull_done>; */
+ /* pinctrl-names = "default"; */
+
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ /* mmc-hs200-1_8v; */
+ card_type = <1>;
+
+ core-phase0 = <3>;
+ tx-phase0 = <0>;
+
+ core-phase1 = <3>;
+ tx-phase1 = <0>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ /* pinctrl-names = "default", "nand_all_pins", "nand_cs_only"; */
+ /* pinctrl-0 = <&all_nand_pins>; */
+ /* pinctrl-1 = <&all_nand_pins>; */
+ /* pinctrl-2 = <&nand_cs_pins>; */
+
+ /*
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-on-flash-bbt;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <1024>;
+
+ meson-nand-user-mode = <2>;
+ meson-nand-ran-mode = <1>;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x00200000>;
+ read-only;
+ };
+ partition@200000 {
+ label = "env";
+ reg = <0x00200000 0x00400000>;
+ };
+ partition@600000 {
+ label = "system";
+ reg = <0x00600000 0x00a00000>;
+ };
+ partition@1000000 {
+ label = "rootfs";
+ reg = <0x01000000 0x03000000>;
+ };
+ partition@4000000 {
+ label = "media";
+ reg = <0x04000000 0x8000000>;
+ };
+ };*/
+
+};
+
+&dwc3 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOH_6";
+ /*gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;*/
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_a {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spifc_pins>;
+ max-frequency = <24000000>;
+ max-cs = <2>;
+ /* 512M */
+ clocks = <&clkc CLKID_FCLK_DIV3>,
+ <&clkc CLKID_SPIFC_MUX>,
+ <&clkc CLKID_SPIFC_DIV>,
+ <&clkc CLKID_SPIFC_GATE>,
+ <&clkc CLKID_SPIFC_XTAL_GATE>;
+ clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate";
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins_a>;
+ cs-gpios = <&gpio GPIOA_8 0>;
+};
+
+&pwm_ab {
+ status = "okay";
+ /* set mux pwm_a_pins4 pwm_b_pins2 for led */
+ pinctrl-names="default";
+ pinctrl-0=<&pwm_a_pins4 &pwm_b_pins2>;
+};
+
+&pwm_cd {
+ status = "okay";
+ /* set mux pwm_c_pins3 for led */
+ pinctrl-names="default";
+ pinctrl-0=<&pwm_c_pins3>;
+};
diff --git a/arch/arm/dts/meson-a1-a113l-ad402.dts b/arch/arm/dts/meson-a1-a113l-ad402.dts
new file mode 100644
index 0000000..4b6aaab
--- /dev/null
+++ b/arch/arm/dts/meson-a1-a113l-ad402.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-a1-a113l-ad402.dtsi"
+#include "meson-a1_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,ad402", "amlogic,a113l", "amlogic,meson-a1";
+ model = "Amlogic Meson A1 AD401 Development Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-a1-a113l-ad402.dtsi b/arch/arm/dts/meson-a1-a113l-ad402.dtsi
new file mode 100644
index 0000000..bb9ff07
--- /dev/null
+++ b/arch/arm/dts/meson-a1-a113l-ad402.dtsi
@@ -0,0 +1,311 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-a1-a113l.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_b;
+ serial1 = &uart_a;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ leds {
+ compatible = "pwm-leds";
+ status = "okay";
+
+ red {
+ label = "led_red";
+ pwms = <&pwm_cd MESON_PWM_0 10000000 0>;
+ max-brightness=<255>;
+ default-brightness=<255>;
+ };
+
+ green {
+ label = "led_green";
+ pwms = <&pwm_ab MESON_PWM_1 10000000 0>;
+ max-brightness=<255>;
+ default-brightness=<255>;
+ };
+
+ blue {
+ label = "led_blue";
+ pwms = <&pwm_ab MESON_PWM_0 10000000 0>;
+ max-brightness=<255>;
+ default-brightness=<255>;
+ };
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /* pinctrl-0 = <&sdio_pins>; */
+ /* pinctrl-names = "default"; */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "disabled";
+ /*pinctrl-0 = <&sd_all_pins>;*/
+ /*pinctrl-names = "default";*/
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+ card_type = <5>;
+
+ /* cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; */
+ /* cd-inverted; */
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "disabled";
+ /* pinctrl-0 = <&emmc_conf_pull_up &emmc_conf_pull_done>; */
+ /* pinctrl-names = "default"; */
+
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ /* mmc-hs200-1_8v; */
+ card_type = <1>;
+
+ core-phase0 = <3>;
+ tx-phase0 = <0>;
+
+ core-phase1 = <3>;
+ tx-phase1 = <0>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ /* pinctrl-names = "default", "nand_all_pins", "nand_cs_only"; */
+ /* pinctrl-0 = <&all_nand_pins>; */
+ /* pinctrl-1 = <&all_nand_pins>; */
+ /* pinctrl-2 = <&nand_cs_pins>; */
+
+ /*
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-on-flash-bbt;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <1024>;
+
+ meson-nand-user-mode = <2>;
+ meson-nand-ran-mode = <1>;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x00200000>;
+ read-only;
+ };
+ partition@200000 {
+ label = "env";
+ reg = <0x00200000 0x00400000>;
+ };
+ partition@600000 {
+ label = "system";
+ reg = <0x00600000 0x00a00000>;
+ };
+ partition@1000000 {
+ label = "rootfs";
+ reg = <0x01000000 0x03000000>;
+ };
+ partition@4000000 {
+ label = "media";
+ reg = <0x04000000 0x8000000>;
+ };
+ };*/
+
+};
+
+&dwc3 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOH_6";
+ /*gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;*/
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_a {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spifc_pins>;
+ max-frequency = <24000000>;
+ max-cs = <2>;
+ /* 512M */
+ clocks = <&clkc CLKID_FCLK_DIV3>,
+ <&clkc CLKID_SPIFC_MUX>,
+ <&clkc CLKID_SPIFC_DIV>,
+ <&clkc CLKID_SPIFC_GATE>,
+ <&clkc CLKID_SPIFC_XTAL_GATE>;
+ clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate";
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins_a>;
+ cs-gpios = <&gpio GPIOA_8 0>;
+};
+
+&pwm_ab {
+ status = "okay";
+ /* set mux pwm_a_pins4 pwm_b_pins2 for led */
+ pinctrl-names="default";
+ pinctrl-0=<&pwm_a_pins4 &pwm_b_pins2>;
+};
+
+&pwm_cd {
+ status = "okay";
+ /* set mux pwm_c_pins3 for led */
+ pinctrl-names="default";
+ pinctrl-0=<&pwm_c_pins3>;
+};
diff --git a/arch/arm/dts/meson-a1-a113l-ad409.dts b/arch/arm/dts/meson-a1-a113l-ad409.dts
new file mode 100644
index 0000000..4e2afc5
--- /dev/null
+++ b/arch/arm/dts/meson-a1-a113l-ad409.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-a1-a113l-ad409.dtsi"
+#include "meson-a1_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,ad409", "amlogic,a113l", "amlogic,meson-a1";
+ model = "Amlogic Meson A1 AD409 Development Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-a1-a113l-ad409.dtsi b/arch/arm/dts/meson-a1-a113l-ad409.dtsi
new file mode 100644
index 0000000..338a247
--- /dev/null
+++ b/arch/arm/dts/meson-a1-a113l-ad409.dtsi
@@ -0,0 +1,271 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-a1-a113l.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_b;
+ serial1 = &uart_a;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /* pinctrl-0 = <&sdio_pins>; */
+ /* pinctrl-names = "default"; */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "disabled";
+ /*pinctrl-0 = <&sd_all_pins>;*/
+ /*pinctrl-names = "default";*/
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+ card_type = <5>;
+
+ /* cd-gpios = <&gpio CARD_6 GPIO_ACTIVE_HIGH>; */
+ /* cd-inverted; */
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "disabled";
+ /* pinctrl-0 = <&emmc_conf_pull_up &emmc_conf_pull_done>; */
+ /* pinctrl-names = "default"; */
+
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ /* mmc-hs200-1_8v; */
+ card_type = <1>;
+
+ core-phase0 = <3>;
+ tx-phase0 = <0>;
+
+ core-phase1 = <3>;
+ tx-phase1 = <0>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ /* pinctrl-names = "default", "nand_all_pins", "nand_cs_only"; */
+ /* pinctrl-0 = <&all_nand_pins>; */
+ /* pinctrl-1 = <&all_nand_pins>; */
+ /* pinctrl-2 = <&nand_cs_pins>; */
+
+ /*
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-on-flash-bbt;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <1024>;
+
+ meson-nand-user-mode = <2>;
+ meson-nand-ran-mode = <1>;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x00200000>;
+ read-only;
+ };
+ partition@200000 {
+ label = "env";
+ reg = <0x00200000 0x00400000>;
+ };
+ partition@600000 {
+ label = "system";
+ reg = <0x00600000 0x00a00000>;
+ };
+ partition@1000000 {
+ label = "rootfs";
+ reg = <0x01000000 0x03000000>;
+ };
+ partition@4000000 {
+ label = "media";
+ reg = <0x04000000 0x8000000>;
+ };
+ };*/
+
+};
+
+&dwc3 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOH_6";
+ /*gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;*/
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_a {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spifc_pins>;
+ max-frequency = <24000000>;
+ max-cs = <2>;
+ /* 512M */
+ clocks = <&clkc CLKID_FCLK_DIV3>,
+ <&clkc CLKID_SPIFC_MUX>,
+ <&clkc CLKID_SPIFC_DIV>,
+ <&clkc CLKID_SPIFC_GATE>,
+ <&clkc CLKID_SPIFC_XTAL_GATE>;
+ clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate";
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins_a>;
+ cs-gpios = <&gpio GPIOA_8 0>;
+};
diff --git a/arch/arm/dts/meson-a1-a113l.dtsi b/arch/arm/dts/meson-a1-a113l.dtsi
new file mode 100644
index 0000000..ff78691
--- /dev/null
+++ b/arch/arm/dts/meson-a1-a113l.dtsi
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "meson-a1.dtsi"
+#include "meson-a1-mali.dtsi"
+
+/ {
+ compatible = "amlogic,s905N", "amlogic,meson-a1";
+};
+
+ðmac {
+ phy-mode = "rmii";
+ phy-handle = <&internal_phy>;
+};
diff --git a/arch/arm/dts/meson-a1-mali.dtsi b/arch/arm/dts/meson-a1-mali.dtsi
new file mode 100644
index 0000000..2655b42
--- /dev/null
+++ b/arch/arm/dts/meson-a1-mali.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+&apb {
+ mali: gpu@40000 {
+ compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
+ reg = <0x0 0x40000 0x0 0x40000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp", "gpmmu", "pp", "pmu",
+ "pp0", "ppmmu0", "pp1", "ppmmu1",
+ "pp2", "ppmmu2";
+ /*clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;*/
+ clock-names = "bus", "core";
+
+ /*
+ * Mali clocking is provided by two identical clock paths
+ * MALI_0 and MALI_1 muxed to a single clock by a glitch
+ * free mux to safely change frequency while running.
+ */
+ /*
+ assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+ <&clkc CLKID_MALI_0>,
+ <&clkc CLKID_MALI>; *//* Glitch free mux */
+ /*assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+ <0>, *//* Do Nothing */
+ //<&clkc CLKID_MALI_0>;
+ /*assigned-clock-rates = <0>,*/ /* Do Nothing */
+ /* <666666666>,
+ <0>;*/ /* Do Nothing */
+ };
+};
diff --git a/arch/arm/dts/meson-a1.dtsi b/arch/arm/dts/meson-a1.dtsi
new file mode 100644
index 0000000..36d58cd
--- /dev/null
+++ b/arch/arm/dts/meson-a1.dtsi
@@ -0,0 +1,533 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "meson-a-series.dtsi"
+#include <dt-bindings/gpio/meson-a1-gpio.h>
+#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
+
+/ {
+ compatible = "amlogic,meson-a1";
+
+ vpu {
+ compatible = "amlogic, vpu-g12a";
+ status = "okay";
+ /*clocks = <&clkc CLKID_VAPB_MUX>,
+ * <&clkc CLKID_VPU_INTR>,
+ * <&clkc CLKID_VPU_P0_COMP>,
+ * <&clkc CLKID_VPU_P1_COMP>,
+ * <&clkc CLKID_VPU_MUX>;
+ *clock-names = "vapb_clk",
+ * "vpu_intr_gate",
+ * "vpu_clk0",
+ * "vpu_clk1",
+ * "vpu_clk";
+ */
+ clk_level = <7>;
+ /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
+ /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */
+ };
+
+ meson-fb {
+ status = "okay";
+ logo_addr = "0x7f800000";
+ };
+};
+
+ðmac {
+ reg = <0x0 0xff3f0000 0x0 0x10000
+ 0x0 0xff634540 0x0 0x8>;
+
+// clocks = <&clkc CLKID_ETH_CORE>,
+// <&clkc CLKID_FCLK_DIV2>,
+// <&clkc CLKID_MPLL2>;
+// clock-names = "stmmaceth", "clkin0", "clkin1";
+
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+};
+
+&cbus {
+ pinctrl_periphs: pinctrl@0400 {
+ compatible = "amlogic,meson-a1-periphs-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio: bank@0400 {
+ reg = <0x0 0x0400 0x0 0x003c>,
+ <0x0 0x0480 0x0 0x0118>;
+ reg-names = "mux",
+ "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_periphs 0 0 63>;
+ };
+ };
+};
+
+&periphs {
+
+ eth-phy-mux {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x15c 0x0 0x4>;
+ mux-mask = <0xffffffff>;
+ mdio-parent-bus = <&mdio0>;
+
+ internal_mdio: mdio@e40908ff {
+ reg = <0xe40908ff>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ internal_phy: ethernet-phy@8 {
+ compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
+ reg = <8>;
+ max-speed = <100>;
+ };
+ };
+
+ external_mdio: mdio@2009087f {
+ reg = <0x2009087f>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&saradc {
+ compatible = "amlogic,meson-g12a-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SARADC_MUX>,
+ <&clkc CLKID_SARADC_DIV>,
+ <&clkc CLKID_SAR_ADC_GATE>;
+ clock-names = "xtal", "adc_mux", "adc_div", "adc_gate";
+};
+
+&sd_emmc_a {
+ /*
+ clocks = <&clkc CLKID_SD_EMMC_A>,
+ <&xtal>,
+ <&clkc CLKID_FCLK_DIV2>;
+ clock-names = "core", "clkin0", "clkin1";
+ */
+};
+
+&sd_emmc_b {
+ /*
+ clocks = <&clkc CLKID_FCLK_DIV2>,
+ <&xtal>,
+ <&clkc CLKID_SD_EMMC_B_P0_MUX>,
+ <&clkc CLKID_SD_EMMC_B_P0_DIV>,
+ <&clkc CLKID_SD_EMMC_B_P0_GATE>,
+ <&clkc CLKID_SD_EMMC_B>;
+ clock-names = "clkin", "clkin1", "clkin2", "clkin3", "clkin4", "core";
+ */
+};
+
+&sd_emmc_c {
+ /*
+ clocks = <&clkc CLKID_FCLK_DIV2>,
+ <&xtal>,
+ <&clkc CLKID_SD_EMMC_C_P0_MUX>,
+ <&clkc CLKID_SD_EMMC_C_P0_DIV>,
+ <&clkc CLKID_SD_EMMC_C_P0_GATE>,
+ <&clkc CLKID_SD_EMMC_C>;
+ clock-names = "clkin", "clkin1", "clkin2", "clkin3", "clkin4", "core";
+ */
+};
+
+&nand {
+ /*
+ clocks = <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_SD_EMMC_C_P0_MUX>,
+ <&clkc CLKID_SD_EMMC_C_P0_DIV>,
+ <&clkc CLKID_SD_EMMC_C_P0_GATE>;
+ clock-names = "clkin", "clkin1", "clkin2", "clkin3";*/
+ /*amlogic,mmc-syscon = <&sd_emmc_c>;*/
+};
+
+&spicc0 {
+ clocks = <&clkc CLKID_SPICC_A_DIV>, <&clkc CLKID_SPICC_A_GATE>;
+ clock-names = "async", "async-gate";
+ assigned-clocks = <&clkc CLKID_SPICC_A_MUX>, <&clkc CLKID_SPICC_A_DIV>;
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
+ assigned-clock-rates = <0>, <200000000>;
+ /* =PM_SPICC, no set for power on already */
+ /* pm-id = <22>; */
+};
+
+&pinctrl_periphs {
+ jtag_a_pins:jtag_a_pin {
+ mux {
+ groups = "jtag_a_clk",
+ "jtag_a_tms",
+ "jtag_a_tdi",
+ "jtag_a_tdo";
+ function = "jtag_a";
+ };
+ };
+
+ swd_a_pins:swd_a_pin {
+ mux {
+ groups = "swclk",
+ "swdio";
+ function = "sw";
+ };
+ };
+
+ i2c0_master_pins1:i2c0_pins1 {
+ mux {
+ groups = "i2c_a_scl_f11",
+ "i2c_a_sda_f12";
+ function = "i2c_a";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c0_master_pins2:i2c0_pins2 {
+ mux {
+ groups = "i2c_a_scl_f9",
+ "i2c_a_sda_f10";
+ function = "i2c_a";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c1_master_pins1:i2c1_pins1 {
+ mux {
+ groups = "i2c_b_sda_x",
+ "i2c_b_scl_x";
+ function = "i2c_b";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c1_master_pins2:i2c1_pins2 {
+ mux {
+ groups = "i2c_b_sda_a",
+ "i2c_b_scl_a";
+ function = "i2c_b";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c2_master_pins1:i2c2_pins1 {
+ mux {
+ groups = "i2c_c_scl_x0",
+ "i2c_c_sda_x1";
+ function = "i2c_c";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c2_master_pins2:i2c2_pins2 {
+ mux {
+ groups = "i2c_c_scl_x15",
+ "i2c_c_sda_x16";
+ function = "i2c_c";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c2_master_pins3:i2c2_pins3 {
+ mux {
+ groups = "i2c_c_scl_a4",
+ "i2c_c_sda_a5";
+ function = "i2c_c";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c2_master_pins4:i2c2_pins4 {
+ mux {
+ groups = "i2c_c_scl_a8",
+ "i2c_c_sda_a9";
+ function = "i2c_c";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c3_master_pins1:i2c3_pins1 {
+ mux {
+ groups = "i2c_d_scl_x",
+ "i2c_d_sda_x";
+ function = "i2c_d";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c3_master_pins2:i2c3_pins2 {
+ mux {
+ groups = "i2c_d_scl_f",
+ "i2c_d_sda_f";
+ function = "i2c_d";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ spifc_pins: spifc_pins {
+ mux {
+ groups = "spif_mo",
+ "spif_mi",
+ "spif_clk",
+ "spif_cs",
+ "spif_hold_n",
+ "spif_wp_n";
+ function = "spif";
+ drive-strength = <3>;
+ };
+ };
+
+ spicc0_pins_a: spicc0_pins_a {
+ mux {
+ groups = "spi_a_mosi_a",
+ "spi_a_miso_a",
+ "spi_a_sclk_a";
+ function = "spi_a";
+ drive-strength = <2>;
+ };
+ };
+
+ pwm_a_pins1: pwm_a_pins1 {
+ mux {
+ groups = "pwm_a_x6";
+ function = "pwm_a";
+ };
+ };
+
+ pwm_a_pins2: pwm_a_pins2 {
+ mux {
+ groups = "pwm_a_x7";
+ function = "pwm_a";
+ };
+ };
+
+ pwm_a_pins3: pwm_a_pins3 {
+ mux {
+ groups = "pwm_a_f10";
+ function = "pwm_a";
+ };
+ };
+
+ pwm_a_pins4: pwm_a_pins4 {
+ mux {
+ groups = "pwm_a_f6";
+ function = "pwm_a";
+ };
+ };
+
+ pwm_a_pins5: pwm_a_pins5 {
+ mux {
+ groups = "pwm_a_a";
+ function = "pwm_a";
+ };
+ };
+
+ pwm_b_pins1: pwm_b_pins1 {
+ mux {
+ groups = "pwm_b_x";
+ function = "pwm_b";
+ };
+ };
+
+ pwm_b_pins2: pwm_b_pins2 {
+ mux {
+ groups = "pwm_b_f";
+ function = "pwm_b";
+ };
+ };
+
+ pwm_b_pins3: pwm_b_pins3 {
+ mux {
+ groups = "pwm_b_a";
+ function = "pwm_b";
+ };
+ };
+
+ pwm_c_pins1: pwm_c_pins1 {
+ mux {
+ groups = "pwm_c_x";
+ function = "pwm_c";
+ };
+ };
+
+ pwm_c_pins2: pwm_c_pins2 {
+ mux {
+ groups = "pwm_c_f3";
+ function = "pwm_c";
+ };
+ };
+
+ pwm_c_pins3: pwm_c_pins3 {
+ mux {
+ groups = "pwm_c_f8";
+ function = "pwm_c";
+ };
+ };
+
+ pwm_c_pins3: pwm_c_pins3 {
+ mux {
+ groups = "pwm_c_f8";
+ function = "pwm_c";
+ };
+ };
+
+ pwm_c_pins4: pwm_c_pins4 {
+ mux {
+ groups = "pwm_c_a";
+ function = "pwm_c";
+ };
+ };
+
+ pwm_d_pins1: pwm_d_pins1 {
+ mux {
+ groups = "pwm_d_x15";
+ function = "pwm_d";
+ };
+ };
+
+ pwm_d_pins2: pwm_d_pins2 {
+ mux {
+ groups = "pwm_d_x13";
+ function = "pwm_d";
+ };
+ };
+
+ pwm_d_pins3: pwm_d_pins3 {
+ mux {
+ groups = "pwm_d_x10";
+ function = "pwm_d";
+ };
+ };
+
+ pwm_d_pins4: pwm_d_pins4 {
+ mux {
+ groups = "pwm_d_f";
+ function = "pwm_d";
+ };
+ };
+
+ pwm_e_pins1: pwm_e_pins1 {
+ mux {
+ groups = "pwm_e_p";
+ function = "pwm_e";
+ };
+ };
+
+ pwm_e_pins2: pwm_e_pins2 {
+ mux {
+ groups = "pwm_e_x16";
+ function = "pwm_e";
+ };
+ };
+
+ pwm_e_pins3: pwm_e_pins3 {
+ mux {
+ groups = "pwm_e_x14";
+ function = "pwm_e";
+ };
+ };
+
+ pwm_e_pins4: pwm_e_pins4 {
+ mux {
+ groups = "pwm_e_x2";
+ function = "pwm_e";
+ };
+ };
+
+ pwm_e_pins5: pwm_e_pins5 {
+ mux {
+ groups = "pwm_e_f";
+ function = "pwm_e";
+ };
+ };
+
+ pwm_e_pins6: pwm_e_pins6 {
+ mux {
+ groups = "pwm_e_a";
+ function = "pwm_e";
+ };
+ };
+
+ pwm_f_pins1: pwm_f_pins1 {
+ mux {
+ groups = "pwm_f_b";
+ function = "pwm_f";
+ };
+ };
+
+ pwm_f_pins2: pwm_f_pins2 {
+ mux {
+ groups = "pwm_f_x";
+ function = "pwm_f";
+ };
+ };
+
+ pwm_f_pins3: pwm_f_pins3 {
+ mux {
+ groups = "pwm_f_f4";
+ function = "pwm_f";
+ };
+ };
+
+ pwm_f_pins4: pwm_f_pins4 {
+ mux {
+ groups = "pwm_f_f12";
+ function = "pwm_f";
+ };
+ };
+};
diff --git a/arch/arm/dts/meson-a1_skt-panel.dtsi b/arch/arm/dts/meson-a1_skt-panel.dtsi
new file mode 100644
index 0000000..fbb676c
--- /dev/null
+++ b/arch/arm/dts/meson-a1_skt-panel.dtsi
@@ -0,0 +1,742 @@
+/*
+ * arch/arm64/boot/dts/amlogic/mesong12a_skt-panel.dtsi
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+/ {
+ lcd{
+ compatible = "amlogic, lcd-g12a";
+ mode = "tablet";
+ status = "okay";
+ key_valid = <0>;
+ /*
+ clocks = <&clkc CLKID_MIPI_DSI_HOST
+ &clkc CLKID_MIPI_DSI_PHY
+ &clkc CLKID_DSI_MEAS_COMP
+ &clkc CLKID_VCLK2_ENCL
+ &clkc CLKID_VCLK2_VENCL
+ &clkc CLKID_GP0_PLL>;
+ clock-names = "dsi_host_gate",
+ "dsi_phy_gate",
+ "dsi_meas",
+ "encl_top_gate",
+ "encl_int_gate",
+ "gp0_pll";
+ */
+ reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */
+ 0x0 0xff644000 0x0 0x200>; /* dsi_phy */
+ interrupts = <0 3 1
+ 0 56 1>;
+ interrupt-names = "vsync","vsync2";
+ pinctrl_version = <2>; /* for uboot */
+
+ /* power type:
+ * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending)
+ * power index:
+ * (point gpios_index, or extern_index,0xff=invalid)
+ * power value:(0=output low, 1=output high, 2=input)
+ * power delay:(unit in ms)
+ */
+
+ /*lcd_cpu-gpios = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH
+ &gpio GPIOZ_8 GPIO_ACTIVE_HIGH>;
+ */
+ lcd_cpu_gpio_names = "GPIOZ_9","GPIOZ_8";
+
+ lcd_0{
+ model_name = "B080XAN01";
+ interface = "mipi";
+ basic_setting = <768 1024 /*h_active, v_active*/
+ 948 1140 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 119 159>; /*screen_widht, screen_height*/
+ lcd_timing = <64 56 0 /*hs_width, hs_bp, hs_pol*/
+ 50 30 0>; /*vs_width, vs_bp, vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/
+ 0 /*clk_ss_level */
+ 1 /*clk_auto_generate*/
+ 64843200>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 550 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 1 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <0x05 1 0x11
+ 0xfd 1 20 /*delay(ms)*/
+ 0x05 1 0x29
+ 0xfd 1 20 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ dsi_init_off = <0x05 1 0x28
+ 0xfd 1 10 /*delay(ms)*/
+ 0x05 1 0x10
+ 0xfd 1 10 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ extern_init = <0xff>; /*0xff for invalid*/
+
+ /* power step: type, index, value, delay(ms) */
+ power_on_step = <
+ 0 1 0 100
+ 0 0 0 10
+ 0 0 1 20
+ 2 0 0 0
+ 0xff 0 0 0>; /*ending*/
+ power_off_step = <
+ 2 0 0 50
+ 0 0 0 10
+ 0 1 1 100
+ 0xff 0 0 0>; /*ending*/
+ backlight_index = <0>;
+ };
+
+ lcd_1{
+ model_name = "P070ACB_FT";
+ interface = "mipi";
+ basic_setting = <600 1024 /*h_active, v_active*/
+ 770 1070 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 3 5>; /*screen_widht, screen_height*/
+ lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/
+ 6 20 0>; /*vs_width,vs_bp,vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
+ 0 /*clk_ss_level*/
+ 1 /*clk_auto_generate*/
+ 49434000>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 400 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 0 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <
+ 0xff 10
+ 0xf0 3 0 1 30 /* reset high, delay 30ms */
+ 0xf0 3 0 0 10 /* reset low, delay 10ms */
+ 0xf0 3 0 1 30 /* reset high, delay 30ms */
+ 0xfc 2 0x04 3 /* check_reg, check_cnt */
+ 0xff 0>; /* ending flag */
+ dsi_init_off = <0xff 0>; /* ending flag */
+ /* extern_init: 0xff for invalid */
+ extern_init = <2>;
+ /* power step: type,index,value,delay(ms) */
+ power_on_step = <
+ 0 1 0 200 /* panel power on */
+ 2 0 0 0
+ 0xff 0 0 0>;
+ power_off_step = <
+ 2 0 0 0
+ 0 0 0 20 /* reset low */
+ 0 1 1 100 /* panel power off */
+ 0xff 0 0 0>;
+ backlight_index = <0>;
+ };
+
+ lcd_3{
+ model_name = "TL050FHV02CT";
+ interface = "mipi";
+ basic_setting = <1080 1920 /*h_active, v_active*/
+ 1125 2100 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 65 119>; /*screen_widht, screen_height*/
+ lcd_timing = <5 30 0 /*hs_width,hs_bp,hs_pol*/
+ 44 108 0>; /*vs_width,vs_bp,vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
+ 0 /*clk_ss_level*/
+ 1 /*clk_auto_generate*/
+ 118125000>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 960 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 1 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <0xff 0>; /* ending flag */
+ dsi_init_off = <0xff 0>; /* ending flag */
+ /* extern_init: 0xff for invalid */
+ extern_init = <3>;
+ /* power step: type,index,value,delay(ms) */
+ power_on_step = <
+ 0 1 0 200
+ 0 0 1 20
+ 0 0 0 10
+ 0 0 1 20
+ 2 0 0 0
+ 0xff 0 0 0>;
+ power_off_step = <
+ 2 0 0 0
+ 0 0 0 20
+ 0 1 1 100
+ 0xff 0 0 0>;
+ backlight_index = <0>;
+ };
+
+ lcd_4{
+ model_name = "TL070WSH27";
+ interface = "mipi";
+ basic_setting = <1024 600 /*h_active, v_active*/
+ 1250 630 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 154 86>; /*screen_widht, screen_height*/
+ lcd_timing = <80 100 0 /*hs_width, hs_bp, hs_pol*/
+ 5 20 0>; /*vs_width, vs_bp, vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/
+ 0 /*clk_ss_level */
+ 1 /*clk_auto_generate*/
+ 47250000>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 300 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 1 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <0x05 1 0x11
+ 0xfd 1 20 /*delay(ms)*/
+ 0x05 1 0x29
+ 0xfd 1 20 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ dsi_init_off = <0x05 1 0x28
+ 0xfd 1 10 /*delay(ms)*/
+ 0x05 1 0x10
+ 0xfd 1 10 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ extern_init = <0xff>; /*0xff for invalid*/
+
+ /* power step: type, index, value, delay(ms) */
+ power_on_step = <
+ 0 1 0 100
+ 0 0 0 10
+ 0 0 1 20
+ 2 0 0 0
+ 0xff 0 0 0>; /*ending*/
+ power_off_step = <
+ 2 0 0 50
+ 0 0 0 10
+ 0 1 1 100
+ 0xff 0 0 0>; /*ending*/
+ backlight_index = <0>;
+ };
+ };
+
+ lcd_extern{
+ compatible = "amlogic, lcd_extern";
+ status = "okay";
+ i2c_bus = "i2c_bus_0";
+ key_valid = <0>;
+
+ extern_0{
+ index = <0>;
+ extern_name = "mipi_default";/*default*/
+ status = "okay";
+ type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+ cmd_size = <0xff>;
+ init_on = <
+ 0xfd 1 10
+ 0x05 1 0x11
+ 0xfd 1 120 /* delay 120ms */
+ 0x05 1 0x29
+ 0xff 0>; /*ending*/
+ init_off = <
+ 0x05 1 0x28 /* display off */
+ 0xfd 1 10 /* delay 10ms */
+ 0x05 1 0x10 /* sleep in */
+ 0xfd 1 150 /* delay 150ms */
+ 0xff 0>; /*ending*/
+ };
+
+ extern_2{
+ index = <2>;
+ extern_name = "mipi_default";/*P070ACB_FT*/
+ status = "okay";
+ type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+ cmd_size = <0xff>;
+ init_on = <
+ 0x23 2 0xE0 0x00 /* Page 0 */
+ 0x23 2 0xE1 0x93 /* PASSWORD */
+ 0x23 2 0xE2 0x65
+ 0x23 2 0xE3 0xF8
+ 0x23 2 0x80 0x03
+ 0x23 2 0xE0 0x01 /* Page 01 */
+ 0x23 2 0x0C 0x74 /* Set PWRIC */
+ 0x23 2 0x17 0x00 /* Set Gamma Power */
+ 0x23 2 0x18 0xEF /* VGMP=5.1V */
+ 0x23 2 0x19 0x00
+ 0x23 2 0x1A 0x00
+ 0x23 2 0x1B 0xEF /* VGMN=-5.1V */
+ 0x23 2 0x1C 0x00
+ 0x23 2 0x1F 0x70 /* Set Gate Power */
+ 0x23 2 0x20 0x2D
+ 0x23 2 0x21 0x2D
+ 0x23 2 0x22 0x7E
+ 0x23 2 0x26 0xF3 /* VDDD from IOVCC */
+ 0x23 2 0x37 0x09 /* SetPanel */
+ 0x23 2 0x38 0x04 /* SET RGBCYC */
+ 0x23 2 0x39 0x00
+ 0x23 2 0x3A 0x01
+ 0x23 2 0x3C 0x90
+ 0x23 2 0x3D 0xFF
+ 0x23 2 0x3E 0xFF
+ 0x23 2 0x3F 0xFF
+ 0x23 2 0x40 0x02 /* Set TCON */
+ 0x23 2 0x41 0x80
+ 0x23 2 0x42 0x99
+ 0x23 2 0x43 0x14
+ 0x23 2 0x44 0x19
+ 0x23 2 0x45 0x5A
+ 0x23 2 0x4B 0x04
+ 0x23 2 0x55 0x02 /* power voltage */
+ 0x23 2 0x56 0x01
+ 0x23 2 0x57 0x69
+ 0x23 2 0x58 0x0A
+ 0x23 2 0x59 0x0A
+ 0x23 2 0x5A 0x2E /* VGH = 16.2V */
+ 0x23 2 0x5B 0x19 /* VGL = -12V */
+ 0x23 2 0x5C 0x15
+ 0x23 2 0x5D 0x77 /* Gamma */
+ 0x23 2 0x5E 0x56
+ 0x23 2 0x5F 0x45
+ 0x23 2 0x60 0x38
+ 0x23 2 0x61 0x35
+ 0x23 2 0x62 0x27
+ 0x23 2 0x63 0x2D
+ 0x23 2 0x64 0x18
+ 0x23 2 0x65 0x33
+ 0x23 2 0x66 0x34
+ 0x23 2 0x67 0x35
+ 0x23 2 0x68 0x56
+ 0x23 2 0x69 0x45
+ 0x23 2 0x6A 0x4F
+ 0x23 2 0x6B 0x42
+ 0x23 2 0x6C 0x40
+ 0x23 2 0x6D 0x34
+ 0x23 2 0x6E 0x25
+ 0x23 2 0x6F 0x02
+ 0x23 2 0x70 0x77
+ 0x23 2 0x71 0x56
+ 0x23 2 0x72 0x45
+ 0x23 2 0x73 0x38
+ 0x23 2 0x74 0x35
+ 0x23 2 0x75 0x27
+ 0x23 2 0x76 0x2D
+ 0x23 2 0x77 0x18
+ 0x23 2 0x78 0x33
+ 0x23 2 0x79 0x34
+ 0x23 2 0x7A 0x35
+ 0x23 2 0x7B 0x56
+ 0x23 2 0x7C 0x45
+ 0x23 2 0x7D 0x4F
+ 0x23 2 0x7E 0x42
+ 0x23 2 0x7F 0x40
+ 0x23 2 0x80 0x34
+ 0x23 2 0x81 0x25
+ 0x23 2 0x82 0x02
+ 0x23 2 0xE0 0x02 /* Page2 */
+ 0x23 2 0x00 0x53
+ /* GIP_L Pin mapping RESET_EVEN */
+ 0x23 2 0x01 0x55 /* VSSG_EVEN */
+ 0x23 2 0x02 0x55 /* VSSA_EVEN */
+ 0x23 2 0x03 0x51 /* STV2_EVEN */
+ 0x23 2 0x04 0x77 /* VDD2_EVEN */
+ 0x23 2 0x05 0x57 /* VDD1_EVEN */
+ 0x23 2 0x06 0x1F
+ 0x23 2 0x07 0x4F /* CK12 */
+ 0x23 2 0x08 0x4D /* CK10 */
+ 0x23 2 0x09 0x1F
+ 0x23 2 0x0A 0x4B /* CK8 */
+ 0x23 2 0x0B 0x49 /* CK6 */
+ 0x23 2 0x0C 0x1F
+ 0x23 2 0x0D 0x47 /* CK4 */
+ 0x23 2 0x0E 0x45 /* CK2 */
+ 0x23 2 0x0F 0x41 /* STV1_EVEN */
+ 0x23 2 0x10 0x1F
+ 0x23 2 0x11 0x1F
+ 0x23 2 0x12 0x1F
+ 0x23 2 0x13 0x55 /* VGG */
+ 0x23 2 0x14 0x1F
+ 0x23 2 0x15 0x1F
+ 0x23 2 0x16 0x52
+ /* GIP_R Pin mapping RESET_ODD */
+ 0x23 2 0x17 0x55 /* VSSG_ODD */
+ 0x23 2 0x18 0x55 /* VSSA_ODD */
+ 0x23 2 0x19 0x50 /* STV2_ODD */
+ 0x23 2 0x1A 0x77 /* VDD2_ODD */
+ 0x23 2 0x1B 0x57 /* VDD1_ODD */
+ 0x23 2 0x1C 0x1F
+ 0x23 2 0x1D 0x4E /* CK11 */
+ 0x23 2 0x1E 0x4C /* CK9 */
+ 0x23 2 0x1F 0x1F
+ 0x23 2 0x20 0x4A /* CK7 */
+ 0x23 2 0x21 0x48 /* CK5 */
+ 0x23 2 0x22 0x1F
+ 0x23 2 0x23 0x46 /* CK3 */
+ 0x23 2 0x24 0x44 /* CK1 */
+ 0x23 2 0x25 0x40 /* STV1_ODD */
+ 0x23 2 0x26 0x1F
+ 0x23 2 0x27 0x1F
+ 0x23 2 0x28 0x1F
+ 0x23 2 0x29 0x1F
+ 0x23 2 0x2A 0x1F
+ 0x23 2 0x2B 0x55 /* VGG */
+ 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping */
+ 0x23 2 0x2D 0x15
+ 0x23 2 0x2E 0x15
+ 0x23 2 0x2F 0x00
+ 0x23 2 0x30 0x37
+ 0x23 2 0x31 0x17
+ 0x23 2 0x32 0x1F
+ 0x23 2 0x33 0x08
+ 0x23 2 0x34 0x0A
+ 0x23 2 0x35 0x1F
+ 0x23 2 0x36 0x0C
+ 0x23 2 0x37 0x0E
+ 0x23 2 0x38 0x1F
+ 0x23 2 0x39 0x04
+ 0x23 2 0x3A 0x06
+ 0x23 2 0x3B 0x10
+ 0x23 2 0x3C 0x1F
+ 0x23 2 0x3D 0x1F
+ 0x23 2 0x3E 0x1F
+ 0x23 2 0x3F 0x15
+ 0x23 2 0x40 0x1F
+ 0x23 2 0x41 0x1F
+ 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping */
+ 0x23 2 0x43 0x15
+ 0x23 2 0x44 0x15
+ 0x23 2 0x45 0x01
+ 0x23 2 0x46 0x37
+ 0x23 2 0x47 0x17
+ 0x23 2 0x48 0x1F
+ 0x23 2 0x49 0x09
+ 0x23 2 0x4A 0x0B
+ 0x23 2 0x4B 0x1F
+ 0x23 2 0x4C 0x0D
+ 0x23 2 0x4D 0x0F
+ 0x23 2 0x4E 0x1F
+ 0x23 2 0x4F 0x05
+ 0x23 2 0x50 0x07
+ 0x23 2 0x51 0x11
+ 0x23 2 0x52 0x1F
+ 0x23 2 0x53 0x1F
+ 0x23 2 0x54 0x1F
+ 0x23 2 0x55 0x1F
+ 0x23 2 0x56 0x1F
+ 0x23 2 0x57 0x15
+ 0x23 2 0x58 0x40 /* GIP Timing */
+ 0x23 2 0x59 0x00
+ 0x23 2 0x5A 0x00
+ 0x23 2 0x5B 0x10
+ 0x23 2 0x5C 0x14
+ 0x23 2 0x5D 0x40
+ 0x23 2 0x5E 0x01
+ 0x23 2 0x5F 0x02
+ 0x23 2 0x60 0x40
+ 0x23 2 0x61 0x03
+ 0x23 2 0x62 0x04
+ 0x23 2 0x63 0x7A
+ 0x23 2 0x64 0x7A
+ 0x23 2 0x65 0x74
+ 0x23 2 0x66 0x16
+ 0x23 2 0x67 0xB4
+ 0x23 2 0x68 0x16
+ 0x23 2 0x69 0x7A
+ 0x23 2 0x6A 0x7A
+ 0x23 2 0x6B 0x0C
+ 0x23 2 0x6C 0x00
+ 0x23 2 0x6D 0x04
+ 0x23 2 0x6E 0x04
+ 0x23 2 0x6F 0x88
+ 0x23 2 0x70 0x00
+ 0x23 2 0x71 0x00
+ 0x23 2 0x72 0x06
+ 0x23 2 0x73 0x7B
+ 0x23 2 0x74 0x00
+ 0x23 2 0x75 0xBC
+ 0x23 2 0x76 0x00
+ 0x23 2 0x77 0x04
+ 0x23 2 0x78 0x2C
+ 0x23 2 0x79 0x00
+ 0x23 2 0x7A 0x00
+ 0x23 2 0x7B 0x00
+ 0x23 2 0x7C 0x00
+ 0x23 2 0x7D 0x03
+ 0x23 2 0x7E 0x7B
+ 0x23 2 0xE0 0x04 /* Page4 */
+ 0x23 2 0x09 0x11 /* Set RGBCYC2 */
+ 0x23 2 0x0E 0x48
+ 0x23 2 0x2B 0x2B /* ESD Protect */
+ 0x23 2 0x2E 0x44
+ 0x23 2 0xE0 0x00 /* Page0 */
+ 0x23 2 0xE6 0x02 /* Watch dog */
+ 0x23 2 0xE7 0x0C
+ 0x05 1 0x11 /* sleep out */
+ 0xfd 1 120
+ 0x05 1 0x29 /* display on */
+ 0x05 1 0x35
+ 0xfd 1 20 /* delay(ms) */
+ 0xFF 0>; /*ending*/
+ init_off = <
+ 0x05 1 0x28 /* display off */
+ 0xfd 1 10 /* delay 10ms */
+ 0x05 1 0x10 /* sleep in */
+ 0xfd 1 150 /* delay 150ms */
+ 0xff 0>; /*ending*/
+ };
+
+ extern_3{
+ index = <3>;
+ extern_name = "mipi_default";/*TL050FHV02CT*/
+ status = "okay";
+ type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+ cmd_size = <0xff>;
+ init_on = <
+ 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03
+ 0x29 10 0x90 0x03 0x14 0x09 0x00 0x00
+ 0x00 0x38 0x00 0x00
+ 0x29 10 0x91 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00
+ 0x29 12 0x92 0x40 0x0B 0x0C 0x0D 0x0E
+ 0x00 0x38 0x00 0x10 0x03 0x04
+ 0x29 9 0x94 0x00 0x08 0x0B 0x03 0xD2
+ 0x03 0xD3 0x0C
+ 0x29 17 0x95 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00
+ 0x29 3 0x99 0x00 0x00
+ 0x29 12 0x9A 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x29 7 0x9B 0x01 0x38 0x00 0x00 0x00 0x00
+ 0x29 3 0x9C 0x00 0x00
+ 0x29 9 0x9D 0x10 0x10 0x10 0x10 0x10
+ 0x10 0x00 0x00
+ 0x29 3 0x9E 0x00 0x00
+ 0x29 11 0xA0 0x9F 0x1F 0x08 0x1F 0x0A
+ 0x1F 0x00 0x1F 0x14 0x1F
+ 0x29 11 0xA1 0x15 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA2 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA4 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA5 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x15
+ 0x29 11 0xA6 0x1F 0x14 0x1F 0x01 0x1F
+ 0x0B 0x1F 0x09 0x1F 0x1F
+ 0x29 11 0xA7 0x1F 0x1F 0x0B 0x1F 0x09
+ 0x1F 0x01 0x1F 0x15 0x1F
+ 0x29 11 0xA8 0x14 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA9 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xAB 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xAC 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x14
+ 0x29 11 0xAD 0x1F 0x15 0x1F 0x00 0x1F
+ 0x08 0x1F 0x0A 0x1F 0x1F
+ 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00
+ 0x29 4 0xBC 0x00 0x00 0x00
+ 0x29 5 0xB8 0x01 0xAF 0x8F 0x8F
+ 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01
+ 0x29 17 0xD1 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xD2 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xD3 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xD4 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xD5 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xD6 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xD7 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xD8 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xD9 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xDD 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xDE 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xDF 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xE0 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xE1 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xE2 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xE3 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xE4 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xE5 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xE6 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xE7 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xE8 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xE9 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xEA 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xEB 0x03 0xC5 0x03 0xFF
+ 0x29 4 0xB0 0x05 0x05 0x05
+ 0x29 4 0xB1 0x05 0x05 0x05
+ 0x29 4 0xB3 0x10 0x10 0x10
+ 0x29 4 0xB4 0x06 0x06 0x06
+ 0x29 4 0xB6 0x44 0x44 0x44
+ 0x29 4 0xB7 0x34 0x34 0x34
+ 0x29 4 0xB8 0x34 0x34 0x34
+ 0x29 4 0xB9 0x24 0x24 0x24
+ 0x29 4 0xBA 0x24 0x24 0x24
+ 0x29 4 0xBC 0x00 0x70 0x00
+ 0x29 4 0xBD 0x00 0x70 0x00
+ 0x23 2 0xBE 0x50
+ 0x23 2 0x35 0x00
+ 0x13 1 0x11
+ 0xfd 1 200
+ 0x13 1 0x29
+ 0xfd 1 200
+ 0xFF 0>; /*ending*/
+ init_off = <
+ 0x05 1 0x28 /* display off */
+ 0xfd 1 10 /* delay 10ms */
+ 0x05 1 0x10 /* sleep in */
+ 0xfd 1 150 /* delay 150ms */
+ 0xff 0>; /*ending*/
+ };
+ };
+
+ backlight{
+ compatible = "amlogic, backlight-g12a";
+ status = "okay";
+ key_valid = <0>;
+ pinctrl-names = "pwm_on","pwm_off";
+ /* pinctrl-0 = <&pwm_f_pins2>; */
+ /* pinctrl-1 = <&bl_pwm_off_pins>; */
+ pinctrl_version = <2>; /* for uboot */
+ bl_pwm_config = <&bl_pwm_conf>;
+ /*bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH
+ &gpio GPIOH_5 GPIO_ACTIVE_HIGH>;*/
+ bl_gpio_names = "GPIOH_4","GPIOH_5";
+
+ /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/
+ /* power index:(point gpios_index, 0xff=invalid)
+ * power value:(0=output low, 1=output high, 2=input)
+ * power delay:(unit in ms)
+ */
+
+ backlight_0{
+ index = <0>;
+ bl_name = "backlight_pwm";
+ bl_level_default_uboot_kernel = <100 100>;
+ bl_level_attr = <255 10 /*max, min*/
+ 128 128>; /*mid, mid_mapping*/
+ bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */
+ bl_power_attr = <0 /*en_gpio_index*/
+ 1 0 /*on_value, off_value*/
+ 200 200>; /*on_delay(ms), off_delay(ms)*/
+ bl_pwm_port = "PWM_F";
+ bl_pwm_attr = <0 /*pwm_method*/
+ 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/
+ 100 25>; /*duty_max(%), duty_min(%)*/
+ bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/
+ 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/
+ bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */
+ };
+ backlight_1{
+ index = <1>;
+ bl_name = "bl_extern";
+ bl_level_default_uboot_kernel = <100 100>;
+ bl_level_attr = <255 10 /*max, min*/
+ 128 128>; /*mid, mid_mapping*/
+ bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/
+ bl_power_attr = <1 /*en_gpio_index*/
+ 1 0 /*on_value, off_value*/
+ 200 200>; /*on_delay(ms), off_delay(ms)*/
+ bl_extern_index = <0>;
+ };
+ };
+ bl_pwm_conf:bl_pwm_conf{
+ pwm_channel_0 {
+ pwm_port_index = <5>;
+ pwms = <&pwm_ef MESON_PWM_1 30040 0>;
+ };
+ };
+
+ bl_extern{
+ compatible = "amlogic, bl_extern";
+ status = "disabled";
+ i2c_bus = "i2c_bus_3";
+
+ extern_0{
+ index = <0>;
+ extern_name = "i2c_lp8556";
+ type = <0>; /*0=i2c, 1=spi, 2=mipi*/
+ i2c_address = <0x2c>; /*7bit i2c address*/
+ dim_max_min = <255 10>;
+ };
+
+ extern_1{
+ index = <1>;
+ extern_name = "mipi_lt070me05";
+ type = <2>; /*0=i2c, 1=spi, 2=mipi*/
+ dim_max_min = <255 10>;
+ };
+ };
+};/* end of panel */
+
diff --git a/arch/arm/dts/meson-c-series.dtsi b/arch/arm/dts/meson-c-series.dtsi
new file mode 100644
index 0000000..89b755d
--- /dev/null
+++ b/arch/arm/dts/meson-c-series.dtsi
@@ -0,0 +1,554 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pwm/meson.h>
+#include <dt-bindings/clock/c1-clkc.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 16 MiB reserved for Hardware ROM Firmware */
+ hwrom_reserved: hwrom@0 {
+ reg = <0x0 0x0 0x0 0x1000000>;
+ no-map;
+ };
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@10000000 {
+ reg = <0x0 0x10000000 0x0 0x200000>;
+ no-map;
+ };
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0xbc00000>;
+ alignment = <0x0 0x400000>;
+ linux,cma-default;
+ };
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+
+ firmware {
+ sm: secure-monitor {
+ compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
+ };
+ };
+
+ efuse: efuse {
+ compatible = "amlogic,meson-gx-efuse", "amlogic,meson-gxbb-efuse";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ sn: sn@14 {
+ reg = <0x14 0x10>;
+ };
+
+ eth_mac: eth_mac@34 {
+ reg = <0x34 0x10>;
+ };
+
+ bid: bid@46 {
+ reg = <0x46 0x30>;
+ };
+ };
+
+ scpi {
+ compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
+ mboxes = <&mailbox 1 &mailbox 2>;
+ shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+
+ scpi_clocks: clocks {
+ compatible = "arm,scpi-clocks";
+
+ scpi_dvfs: scpi_clocks@0 {
+ compatible = "arm,scpi-dvfs-clocks";
+ #clock-cells = <1>;
+ clock-indices = <0>;
+ clock-output-names = "vcpu";
+ };
+ };
+
+ scpi_sensors: sensors {
+ compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@2c001000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xffc01000 0 0x1000>,
+ <0x0 0xffc02000 0 0x2000>,
+ <0x0 0xffc04000 0 0x2000>,
+ <0x0 0xffc06000 0 0x2000>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ };
+
+ sram: sram@fffa0000 {
+ compatible = "amlogic,meson-gx-sram", "amlogic,meson-gxbb-sram", "mmio-sram";
+ reg = <0x0 0xfffa0000 0x0 0x48000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0xfffa0000 0x48000>;
+
+ cpu_scp_lpri: scp-shmem@0 {
+ compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
+ reg = <0x47000 0x400>;
+ };
+
+ cpu_scp_hpri: scp-shmem@200 {
+ compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
+ reg = <0x47400 0x400>;
+ };
+ };
+
+ cbus: cbus@fe000000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xfe000000 0x0 0x8000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x8000>;
+
+ uart_a: serial@1c00 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x1c00 0x0 0x14>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ uart_b: serial@2000 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x2000 0x0 0x14>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ pwm_ab: pwm@2400 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0x2400 0x0 0x20>,
+ <0x0 0x08c4 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_cd: pwm@2800 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0x2800 0x0 0x20>,
+ <0x0 0x08c8 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_ef: pwm@5400 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0x5400 0x0 0x20>,
+ <0x0 0x08cc 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_gh: pwm@a400 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0xa400 0x0 0x20>,
+ <0x0 0x0928 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_ij: pwm@a800 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0xa800 0x0 0x20>,
+ <0x0 0x092c 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ ir: ir@8040 {
+ compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
+ reg = <0x0 0x8040 0x0 0x40>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ reset: reset-controller@1000 {
+ compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
+ reg = <0x0 0x01000 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
+ uart_c: serial@22000 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x22000 0x0 0x18>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ spicc0: spi@3800 {
+ compatible = "amlogic,meson-g12a-spicc";
+ reg = <0x0 0x3800 0x0 0x44>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spifc: spi@14000 {
+ compatible = "amlogic,spifc";
+ reg = <0x0 0x14000 0x0 0x80>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ spi-flash@0 {
+ reg = <0>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ compatible = "spi-flash";
+ status = "okay";
+ };
+ spi-nand@1 {
+ reg = <1>;
+ spi-tx-bus-width = <4>;
+ spi-rx-bus-width = <4>;
+ compatible = "spi-nand";
+ status = "okay";
+ };
+ };
+
+ spicc1: spi@3c00 {
+ compatible = "amlogic,meson-g12a-spicc";
+ reg = <0x0 0x3c00 0x0 0x44>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ watchdog@0f0d0 {
+ compatible = "amlogic,meson-a1-wdt";
+ reg = <0x0 0x0f0d0 0x0 0x10>;
+ clocks = <&xtal>;
+ clock-names = "wdt-clk";
+ };
+
+ jtag {
+ compatible = "amlogic, jtag";
+ status = "okay";
+ select = "disable"; /* disable/jtag-a/jtag-b/swd-a */
+ pinctrl-names="jtag_a_pins", "jtag_b_pins", "swd_a_pins";
+ pinctrl-0=<&jtag_a_pins>;
+ pinctrl-1=<&jtag_b_pins>;
+ pinctrl-2=<&swd_a_pins>;
+ };
+ };
+
+ periphs: periphs@ff634000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xff634000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
+
+ hwrng: rng {
+ compatible = "amlogic,meson-rng";
+ reg = <0x0 0x0 0x0 0x4>;
+ };
+ };
+
+ hiubus: hiubus@ff63c000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xff63c000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>;
+
+ mailbox: mailbox@404 {
+ compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
+ reg = <0 0x404 0 0x4c>;
+ interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
+ <0 209 IRQ_TYPE_EDGE_RISING>,
+ <0 210 IRQ_TYPE_EDGE_RISING>;
+ #mbox-cells = <1>;
+ };
+ };
+
+ clkc: clock-controller@0 {
+ compatible = "amlogic,c1-clkc";
+ #clock-cells = <1>;
+ reg = <0x0 0xfe000800 0x0 0xe4>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ };
+
+ i2c0: i2c@fe001400 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe001400 0x0 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@fe005c00 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe005c00 0x0 0x3c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@fe006800 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe006800 0x0 0x3c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@fe006c00 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe006c00 0x0 0x3c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@fe00b000 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe00b000 0x0 0x3c>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ ethmac: ethernet@ff3f0000 {
+ compatible = "amlogic,g12a-eth-dwmac";
+ phy_cntl1 = <0x41054147>;
+ pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>;
+ analog_val = <0x20200000 0x0000c000 0x00000023>;
+ status = "disabled";
+ };
+
+ saradc: adc@ff809000 {
+ compatible = "amlogic,meson-saradc";
+ reg = <0x0 0xfe002c00 0x0 0x48>;
+ status = "disabled";
+ };
+
+ nand: nfc@fe012800 {
+ compatible = "amlogic,meson-nfc";
+ reg = <0x0 0xfe012800 0x0 0x200>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ clk_reg = <0 0xfe012000>;
+ };
+
+ apb: apb@fe000000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xfe000000 0x0 0x1000000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
+
+ sd_emmc_a: sdio {
+ compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
+ reg = <0x0 0x10000 0x0 0x800>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ pinname = "sdio";
+ };
+
+ sd_emmc_b: sd {
+ compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
+ reg = <0x0 0x11000 0x0 0x800>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ pinname = "sd";
+ };
+
+ sd_emmc_c: emmc {
+ compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
+ reg = <0x0 0x12000 0x0 0x800>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ pinname = "emmc";
+ };
+ };
+
+ dwc3: dwc3@ff400000 {
+ compatible = "snps,dwc3","synopsys,xhci-dwc3";
+ status = "disable";
+ reg = <0x0 0xff400000 0x0 0x100000>;
+ phys = <&usb2_phy_v2>, <&usb3_phy_v2>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ usb2_phy_v2: usb2phy@fe004420 {
+ compatible = "amlogic, amlogic-new-usb2-v2";
+ status = "disable";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ phy-version = <2>;
+ reg = <0x0 0xfe004420 0x0 0x60
+ 0x0 0xfe000004 0x0 0x100
+ 0x0 0xfe004000 0x0 0x2000
+ 0x0 0xfe0008dc 0x0 0x4>;
+ dwc2_a_reg = <0xff500000>;
+ #phy-cells = <0>;
+ };
+
+ usb3_phy_v2: usb3phy@fe004480 {
+ compatible = "amlogic, amlogic-new-usb3-v2";
+ status = "disable";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ phy-version = <3>;
+ reg = <0x0 0xfe004480 0x0 0x20>;
+ #phy-cells = <0>;
+ };
+
+ };
+};
diff --git a/arch/arm/dts/meson-c1-c308x-ae400.dts b/arch/arm/dts/meson-c1-c308x-ae400.dts
new file mode 100644
index 0000000..ca74dfc
--- /dev/null
+++ b/arch/arm/dts/meson-c1-c308x-ae400.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-c1-c308x-ae400.dtsi"
+#include "meson-c1_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,ae400", "amlogic,c308x", "amlogic,meson-c1";
+ model = "Amlogic Meson C1 AE400 Reference Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c1-c308x-ae400.dtsi b/arch/arm/dts/meson-c1-c308x-ae400.dtsi
new file mode 100644
index 0000000..a88346f
--- /dev/null
+++ b/arch/arm/dts/meson-c1-c308x-ae400.dtsi
@@ -0,0 +1,251 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-c1-c308x.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_b;
+ serial1 = &uart_a;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_tx_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_tx_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_tx_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&dwc3 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOD_9";
+ gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_a {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spifc_pins>;
+ max-frequency = <24000000>;
+ max-cs = <2>;
+ /* 512M */
+ clocks = <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_SPIFC_MUX>,
+ <&clkc CLKID_SPIFC_DIV>,
+ <&clkc CLKID_SPIFC_GATE>,
+ <&clkc CLKID_SPIFC_XTAL_GATE>;
+ clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate";
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins1>;
+ cs-gpios = <&gpio GPIOA_8 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins1>;
+ cs-gpios = <&gpio GPIOA_14 0>;
+};
diff --git a/arch/arm/dts/meson-c1-c308x-ae401.dts b/arch/arm/dts/meson-c1-c308x-ae401.dts
new file mode 100644
index 0000000..6c5e195
--- /dev/null
+++ b/arch/arm/dts/meson-c1-c308x-ae401.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-c1-c308x-ae401.dtsi"
+#include "meson-c1_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,ae401", "amlogic,c308x", "amlogic,meson-c1";
+ model = "Amlogic Meson C1 AE401 Reference Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c1-c308x-ae401.dtsi b/arch/arm/dts/meson-c1-c308x-ae401.dtsi
new file mode 100644
index 0000000..d742529
--- /dev/null
+++ b/arch/arm/dts/meson-c1-c308x-ae401.dtsi
@@ -0,0 +1,292 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-c1-c308x.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_b;
+ serial1 = &uart_a;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_tx_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ //mmc-hs200-1_8v;
+ max-frequency = <50000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_tx_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_tx_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+
+ /*
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-on-flash-bbt;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <1024>;
+
+ meson-nand-user-mode = <2>;
+ meson-nand-ran-mode = <1>;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x00200000>;
+ read-only;
+ };
+ partition@200000 {
+ label = "env";
+ reg = <0x00200000 0x00400000>;
+ };
+ partition@600000 {
+ label = "system";
+ reg = <0x00600000 0x00a00000>;
+ };
+ partition@1000000 {
+ label = "rootfs";
+ reg = <0x01000000 0x03000000>;
+ };
+ partition@4000000 {
+ label = "media";
+ reg = <0x04000000 0x8000000>;
+ };
+ };*/
+
+};
+
+&dwc3 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOD_9";
+ gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_a {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spifc_pins>;
+ max-frequency = <24000000>;
+ max-cs = <2>;
+ /* 512M */
+ clocks = <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_SPIFC_MUX>,
+ <&clkc CLKID_SPIFC_DIV>,
+ <&clkc CLKID_SPIFC_GATE>,
+ <&clkc CLKID_SPIFC_XTAL_GATE>;
+ clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate";
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins1>;
+ cs-gpios = <&gpio GPIOA_8 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins1>;
+ cs-gpios = <&gpio GPIOA_14 0>;
+};
diff --git a/arch/arm/dts/meson-c1-c308x-ae402.dts b/arch/arm/dts/meson-c1-c308x-ae402.dts
new file mode 100644
index 0000000..2fb0f98
--- /dev/null
+++ b/arch/arm/dts/meson-c1-c308x-ae402.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-c1-c308x-ae402.dtsi"
+#include "meson-c1_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,ae402", "amlogic,c308x", "amlogic,meson-c1";
+ model = "Amlogic Meson C1 AE402 Reference Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c1-c308x-ae402.dtsi b/arch/arm/dts/meson-c1-c308x-ae402.dtsi
new file mode 100644
index 0000000..43c7b60
--- /dev/null
+++ b/arch/arm/dts/meson-c1-c308x-ae402.dtsi
@@ -0,0 +1,292 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-c1-c308x.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_b;
+ serial1 = &uart_a;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x20000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_tx_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ //mmc-hs200-1_8v;
+ max-frequency = <50000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_tx_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_tx_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+
+ /*
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-on-flash-bbt;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <1024>;
+
+ meson-nand-user-mode = <2>;
+ meson-nand-ran-mode = <1>;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x00200000>;
+ read-only;
+ };
+ partition@200000 {
+ label = "env";
+ reg = <0x00200000 0x00400000>;
+ };
+ partition@600000 {
+ label = "system";
+ reg = <0x00600000 0x00a00000>;
+ };
+ partition@1000000 {
+ label = "rootfs";
+ reg = <0x01000000 0x03000000>;
+ };
+ partition@4000000 {
+ label = "media";
+ reg = <0x04000000 0x8000000>;
+ };
+ };*/
+
+};
+
+&dwc3 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOD_9";
+ gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_a {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spifc_pins>;
+ max-frequency = <24000000>;
+ max-cs = <2>;
+ /* 512M */
+ clocks = <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_SPIFC_MUX>,
+ <&clkc CLKID_SPIFC_DIV>,
+ <&clkc CLKID_SPIFC_GATE>,
+ <&clkc CLKID_SPIFC_XTAL_GATE>;
+ clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate";
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins1>;
+ cs-gpios = <&gpio GPIOA_8 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins1>;
+ cs-gpios = <&gpio GPIOA_14 0>;
+};
diff --git a/arch/arm/dts/meson-c1-c308x-ae409.dts b/arch/arm/dts/meson-c1-c308x-ae409.dts
new file mode 100644
index 0000000..ef6479b
--- /dev/null
+++ b/arch/arm/dts/meson-c1-c308x-ae409.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-c1-c308x-ae409.dtsi"
+#include "meson-c1_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,ae409", "amlogic,c308x", "amlogic,meson-c1";
+ model = "Amlogic Meson C1 AE409 Socket Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c1-c308x-ae409.dtsi b/arch/arm/dts/meson-c1-c308x-ae409.dtsi
new file mode 100644
index 0000000..18554d9
--- /dev/null
+++ b/arch/arm/dts/meson-c1-c308x-ae409.dtsi
@@ -0,0 +1,251 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-c1-c308x.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_b;
+ serial1 = &uart_a;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&dwc3 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOD_9";
+ gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_a {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spifc_pins>;
+ max-frequency = <24000000>;
+ max-cs = <2>;
+ /* 512M */
+ clocks = <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_SPIFC_MUX>,
+ <&clkc CLKID_SPIFC_DIV>,
+ <&clkc CLKID_SPIFC_GATE>,
+ <&clkc CLKID_SPIFC_XTAL_GATE>;
+ clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate";
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins1>;
+ cs-gpios = <&gpio GPIOA_8 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins1>;
+ cs-gpios = <&gpio GPIOA_14 0>;
+};
diff --git a/arch/arm/dts/meson-c1-c308x.dtsi b/arch/arm/dts/meson-c1-c308x.dtsi
new file mode 100644
index 0000000..644bb4b
--- /dev/null
+++ b/arch/arm/dts/meson-c1-c308x.dtsi
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "meson-c1.dtsi"
+#include "meson-c1-mali.dtsi"
+
+/ {
+ compatible = "amlogic,c308x", "amlogic,meson-c1";
+};
+
+ðmac {
+ phy-mode = "rmii";
+ phy-handle = <&internal_phy>;
+};
diff --git a/arch/arm/dts/meson-c1-mali.dtsi b/arch/arm/dts/meson-c1-mali.dtsi
new file mode 100644
index 0000000..2655b42
--- /dev/null
+++ b/arch/arm/dts/meson-c1-mali.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+&apb {
+ mali: gpu@40000 {
+ compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
+ reg = <0x0 0x40000 0x0 0x40000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp", "gpmmu", "pp", "pmu",
+ "pp0", "ppmmu0", "pp1", "ppmmu1",
+ "pp2", "ppmmu2";
+ /*clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;*/
+ clock-names = "bus", "core";
+
+ /*
+ * Mali clocking is provided by two identical clock paths
+ * MALI_0 and MALI_1 muxed to a single clock by a glitch
+ * free mux to safely change frequency while running.
+ */
+ /*
+ assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+ <&clkc CLKID_MALI_0>,
+ <&clkc CLKID_MALI>; *//* Glitch free mux */
+ /*assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+ <0>, *//* Do Nothing */
+ //<&clkc CLKID_MALI_0>;
+ /*assigned-clock-rates = <0>,*/ /* Do Nothing */
+ /* <666666666>,
+ <0>;*/ /* Do Nothing */
+ };
+};
diff --git a/arch/arm/dts/meson-c1.dtsi b/arch/arm/dts/meson-c1.dtsi
new file mode 100644
index 0000000..cc3138c
--- /dev/null
+++ b/arch/arm/dts/meson-c1.dtsi
@@ -0,0 +1,711 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "meson-c-series.dtsi"
+#include <dt-bindings/gpio/meson-c1-gpio.h>
+#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
+
+/ {
+ compatible = "amlogic,meson-c1";
+
+ vpu {
+ compatible = "amlogic, vpu-g12a";
+ status = "okay";
+ /*clocks = <&clkc CLKID_VAPB_MUX>,
+ * <&clkc CLKID_VPU_INTR>,
+ * <&clkc CLKID_VPU_P0_COMP>,
+ * <&clkc CLKID_VPU_P1_COMP>,
+ * <&clkc CLKID_VPU_MUX>;
+ *clock-names = "vapb_clk",
+ * "vpu_intr_gate",
+ * "vpu_clk0",
+ * "vpu_clk1",
+ * "vpu_clk";
+ */
+ clk_level = <7>;
+ /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
+ /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */
+ };
+
+ meson-fb {
+ status = "okay";
+ logo_addr = "0x7f800000";
+ };
+};
+
+ðmac {
+ compatible = "amlogic,g12a-eth-dwmac";
+ reg = <0x0 0xff080000 0x0 0x10000
+ 0x0 0xFE009000 0x0 0x8
+ 0x0 0xFE009400 0x0 0xa0>;
+ reg-names = "eth_base", "eth_top", "eth_cfg";
+ phy_cntl1 = <0x41054147>;
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>;
+ analog_val = <0x20200000 0x0000c000 0x00000023>;
+ tx_amp_src = <0xfe005b30>;
+// clocks = <&clkc CLKID_ETH_CORE>,
+// <&clkc CLKID_FCLK_DIV2>,
+// <&clkc CLKID_MPLL2>;
+// clock-names = "stmmaceth", "clkin0", "clkin1";
+
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+};
+
+&cbus {
+ pinctrl_periphs: pinctrl@0400 {
+ compatible = "amlogic,meson-c1-periphs-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio: bank@0400 {
+ reg = <0x0 0x0400 0x0 0x0040>,
+ <0x0 0x0480 0x0 0x01d8>;
+ reg-names = "mux",
+ "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_periphs 0 0 90>;
+ };
+ };
+};
+
+&periphs {
+
+ eth-phy-mux {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x15c 0x0 0x4>;
+ mux-mask = <0xffffffff>;
+ mdio-parent-bus = <&mdio0>;
+
+ internal_mdio: mdio@e40908ff {
+ reg = <0xe40908ff>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ internal_phy: ethernet-phy@8 {
+ compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
+ reg = <8>;
+ max-speed = <100>;
+ };
+ };
+
+ external_mdio: mdio@2009087f {
+ reg = <0x2009087f>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&saradc {
+ compatible = "amlogic,meson-g12a-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SARADC_MUX>,
+ <&clkc CLKID_SARADC_DIV>,
+ <&clkc CLKID_SAR_ADC_GATE>;
+ clock-names = "xtal", "adc_mux", "adc_div", "adc_gate";
+};
+
+&sd_emmc_a {
+ clocks = <&clkc CLKID_SD_EMMC_A_MUX>,
+ <&clkc CLKID_SD_EMMC_A_DIV>,
+ <&clkc CLKID_SD_EMMC_A_GATE>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_SD_EMMC_A_XTAL_GATE>;
+ clock-names = "mux", "div", "gate", "clkin", "xtal";
+};
+
+&sd_emmc_b {
+ clocks = <&clkc CLKID_SD_EMMC_B_MUX>,
+ <&clkc CLKID_SD_EMMC_B_DIV>,
+ <&clkc CLKID_SD_EMMC_B_GATE>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_SD_EMMC_B_XTAL_GATE>;
+ clock-names = "mux", "div", "gate", "clkin", "xtal";
+};
+
+&sd_emmc_c {
+ clocks = <&clkc CLKID_SD_EMMC_C_MUX>,
+ <&clkc CLKID_SD_EMMC_C_DIV>,
+ <&clkc CLKID_SD_EMMC_C_GATE>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_SD_EMMC_C_XTAL_GATE>;
+ clock-names = "mux", "div", "gate", "clkin", "xtal";
+};
+
+&nand {
+ clocks = <&clkc CLKID_SD_EMMC_C_MUX>,
+ <&clkc CLKID_SD_EMMC_C_DIV>,
+ <&clkc CLKID_SD_EMMC_C_GATE>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_SD_EMMC_C_XTAL_GATE>;
+ clock-names = "mux", "div", "gate", "fdiv2", "xtal";
+};
+
+&spicc0 {
+ clocks = <&clkc CLKID_SPICC_A_DIV>, <&clkc CLKID_SPICC_A_GATE>;
+ clock-names = "async", "async-gate";
+ assigned-clocks = <&clkc CLKID_SPICC_A_MUX>, <&clkc CLKID_SPICC_A_DIV>;
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
+ assigned-clock-rates = <0>, <200000000>;
+ /* =PM_SPICC, no set for power on already */
+ /* pm-id = <22>; */
+};
+
+&spicc1 {
+ clocks = <&clkc CLKID_SPICC_B_DIV>, <&clkc CLKID_SPICC_B_GATE>;
+ clock-names = "async", "async-gate";
+ assigned-clocks = <&clkc CLKID_SPICC_B_MUX>, <&clkc CLKID_SPICC_B_DIV>;
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
+ assigned-clock-rates = <0>, <200000000>;
+ /* =PM_SPICC_B, must set to power on */
+ pm-id = <39>;
+};
+
+&pinctrl_periphs {
+ jtag_a_pins:jtag_a_pin {
+ mux {
+ groups = "jtag_a_clk",
+ "jtag_a_tms",
+ "jtag_a_tdi",
+ "jtag_a_tdo";
+ function = "jtag_a";
+ };
+ };
+
+ jtag_b_pins:jtag_b_pin {
+ mux {
+ groups = "jtag_b_clk",
+ "jtag_b_tms",
+ "jtag_b_tdi",
+ "jtag_b_tdo";
+ function = "jtag_b";
+ };
+ };
+
+ swd_a_pins:swd_a_pin {
+ mux {
+ groups = "swclk",
+ "swdio";
+ function = "sw";
+ };
+ };
+
+ /*i2c0 pinmux*/
+ i2c0_master_pins1:i2c0_pins1 {
+ mux {
+ groups = "i2c_a_scl_d",
+ "i2c_a_sda_d";
+ function = "i2c_a";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c0_master_pins2:i2c0_pins2 {
+ mux {
+ groups = "i2c_a_scl_e",
+ "i2c_a_sda_e";
+ function = "i2c_a";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ /* i2c1 pinmux */
+ i2c1_master_pins1:i2c1_pins1 {
+ mux {
+ groups = "i2c_b_scl_x",
+ "i2c_b_sda_x";
+ function = "i2c_b";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c1_master_pins2:i2c1_pins2 {
+ mux {
+ groups = "i2c_b_scl_a",
+ "i2c_b_sda_a";
+ function = "i2c_b";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c1_master_pins3:i2c1_pins3 {
+ mux {
+ groups = "i2c_b_scl_m",
+ "i2c_b_sda_m";
+ function = "i2c_b";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ /* i2c2 pinmux */
+ i2c2_master_pins1:i2c2_pins1 {
+ mux {
+ groups = "i2c_c_scl_x",
+ "i2c_c_sda_x";
+ function = "i2c_c";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c2_master_pins2:i2c2_pins2 {
+ mux {
+ groups = "i2c_c_scl_m",
+ "i2c_c_sda_m";
+ function = "i2c_c";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c2_master_pins3:i2c2_pins3 {
+ mux {
+ groups = "i2c_c_scl_a",
+ "i2c_c_sda_a";
+ function = "i2c_c";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ /* i2c3 pinmux */
+ i2c3_master_pins1:i2c3_pins1 {
+ mux {
+ groups = "i2c_d_scl_x",
+ "i2c_d_sda_x";
+ function = "i2c_d";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c3_master_pins2:i2c3_pins2 {
+ mux {
+ groups = "i2c_d_scl_a",
+ "i2c_d_sda_a";
+ function = "i2c_d";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c3_master_pins3:i2c3_pins3 {
+ mux {
+ groups = "i2c_d_scl_m",
+ "i2c_d_sda_m";
+ function = "i2c_d";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ /* i2c4 pinmux */
+ i2c4_master_pins1:i2c4_pins1 {
+ mux {
+ groups = "i2c_e_scl_c",
+ "i2c_e_sda_c";
+ function = "i2c_e";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c4_master_pins2:i2c4_pins2 {
+ mux {
+ groups = "i2c_e_scl_m",
+ "i2c_e_sda_m";
+ function = "i2c_e";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c4_master_pins3:i2c4_pins3 {
+ mux {
+ groups = "i2c_e_scl_a",
+ "i2c_e_sda_a";
+ function = "i2c_e";
+ bias-pull-up;
+ drive-strength = <3>;
+ };
+ };
+
+ pwm_a_pins1: pwm_a_pins1 {
+ mux {
+ groups = "pwm_a";
+ function = "pwm_a";
+ };
+ };
+
+ pwm_b_pins1: pwm_b_pins1 {
+ mux {
+ groups = "pwm_b";
+ function = "pwm_b";
+ };
+ };
+
+ pwm_c_pins1: pwm_c_pins1 {
+ mux {
+ groups = "pwm_c";
+ function = "pwm_c";
+ };
+ };
+
+ pwm_d_pins1: pwm_d_pins1 {
+ mux {
+ groups = "pwm_d";
+ function = "pwm_d";
+ };
+ };
+
+ pwm_e_pins1: pwm_e_pins1 {
+ mux {
+ groups = "pwm_e";
+ function = "pwm_e";
+ };
+ };
+
+ pwm_f_pins1: pwm_f_pins1 {
+ mux {
+ groups = "pwm_f_d";
+ function = "pwm_f";
+ };
+ };
+
+ pwm_f_pins2: pwm_f_pins2 {
+ mux {
+ groups = "pwm_f_m";
+ function = "pwm_f";
+ };
+ };
+
+ pwm_f_pins3: pwm_f_pins3 {
+ mux {
+ groups = "pwm_f_x";
+ function = "pwm_f";
+ };
+ };
+
+ pwm_g_pins1: pwm_g_pins1 {
+ mux {
+ groups = "pwm_g_d";
+ function = "pwm_g";
+ };
+ };
+
+ pwm_g_pins2: pwm_g_pins2 {
+ mux {
+ groups = "pwm_g_x";
+ function = "pwm_g";
+ };
+ };
+
+ pwm_g_pins3: pwm_g_pins3 {
+ mux {
+ groups = "pwm_g_m";
+ function = "pwm_g";
+ };
+ };
+
+ pwm_g_pins4: pwm_g_pins4 {
+ mux {
+ groups = "pwm_g_a7";
+ function = "pwm_g";
+ };
+ };
+
+ pwm_g_pins5: pwm_g_pins5 {
+ mux {
+ groups = "pwm_g_a1";
+ function = "pwm_g";
+ };
+ };
+
+ pwm_h_pins1: pwm_h_pins1 {
+ mux {
+ groups = "pwm_h_x";
+ function = "pwm_h";
+ };
+ };
+
+ pwm_h_pins2: pwm_h_pins2 {
+ mux {
+ groups = "pwm_h_m";
+ function = "pwm_h";
+ };
+ };
+
+ pwm_h_pins3: pwm_h_pins3 {
+ mux {
+ groups = "pwm_h_a8";
+ function = "pwm_h";
+ };
+ };
+
+ pwm_h_pins4: pwm_h_pins4 {
+ mux {
+ groups = "pwm_h_a2";
+ function = "pwm_h";
+ };
+ };
+
+ pwm_i_pins1: pwm_i_pins1 {
+ mux {
+ groups = "pwm_i_x";
+ function = "pwm_i";
+ };
+ };
+
+ pwm_i_pins2: pwm_i_pins2 {
+ mux {
+ groups = "pwm_i_m";
+ function = "pwm_i";
+ };
+ };
+
+ pwm_i_pins3: pwm_i_pins3 {
+ mux {
+ groups = "pwm_i_a9";
+ function = "pwm_i";
+ };
+ };
+
+ pwm_i_pins4: pwm_i_pins4 {
+ mux {
+ groups = "pwm_i_a3";
+ function = "pwm_i";
+ };
+ };
+
+ pwm_j_pins1: pwm_j_pins1 {
+ mux {
+ groups = "pwm_j_x";
+ function = "pwm_j";
+ };
+ };
+
+ pwm_j_pins2: pwm_j_pins2 {
+ mux {
+ groups = "pwm_j_m";
+ function = "pwm_j";
+ };
+ };
+
+ pwm_j_pins3: pwm_j_pins3 {
+ mux {
+ groups = "pwm_j_a10";
+ function = "pwm_j";
+ };
+ };
+
+ pwm_j_pins4: pwm_j_pins4 {
+ mux {
+ groups = "pwm_j_a4";
+ function = "pwm_j";
+ };
+ };
+
+ emmc_pins: emmc {
+ mux {
+ groups = "emmc_nand_d0",
+ "emmc_nand_d1",
+ "emmc_nand_d2",
+ "emmc_nand_d3",
+ "emmc_nand_d4",
+ "emmc_nand_d5",
+ "emmc_nand_d6",
+ "emmc_nand_d7",
+ "emmc_clk",
+ "emmc_cmd";
+ function = "emmc";
+ bias-pull-up;
+ input-enable;
+ };
+ mux1 {
+ groups = "emmc_nand_ds";
+ function = "emmc";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ emmc_clk_gate_pins: emmc_clk_gate {
+ mux {
+ groups = "emmc_clk";
+ function = "emmc";
+ bias-pull-down;
+ };
+ };
+
+ all_nand_pins: all_nand_pins {
+ mux {
+ groups = "emmc_nand_d0",
+ "emmc_nand_d1",
+ "emmc_nand_d2",
+ "emmc_nand_d3",
+ "emmc_nand_d4",
+ "emmc_nand_d5",
+ "emmc_nand_d6",
+ "emmc_nand_d7",
+ "nand_ce0",
+ "nand_ale",
+ "nand_cle",
+ "nand_wen_clk",
+ "nand_ren_wr";
+ function = "nand";
+ input-enable;
+ };
+ };
+
+ nand_cs_pins: nand_cs {
+ mux {
+ groups = "nand_ce0";
+ function = "nand";
+ };
+ };
+
+ sdcard_pins: sdcard {
+ mux {
+ groups = "sdcard_d0",
+ "sdcard_d1",
+ "sdcard_d2",
+ "sdcard_d3",
+ "sdcard_cmd";
+ function = "sdcard";
+ bias-pull-up;
+ input-enable;
+ drive-strength = <4>;
+ };
+ mux1 {
+ groups ="sdcard_clk";
+ function = "sdcard";
+ bias-pull-up;
+ output-high;
+ drive-strength = <4>;
+ };
+ };
+
+ sdcard_clk_gate_pins: sdcard_clk_gate {
+ mux {
+ groups = "sdcard_clk";
+ function = "sdcard";
+ bias-pull-down;
+ };
+ };
+
+ to_sduart_pins: to_sduart_pins{
+ mux {
+ groups = "uart_b_rx_c", "uart_b_tx_c";
+ function = "uart_b";
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
+ sd_to_uart_pins: sd_to_uart_pins{
+ mux {
+ groups = "uart_b_rx_d", "uart_b_tx_d";
+ function = "uart_b";
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
+ spicc0_pins1: spicc0_pins1 {
+ mux {
+ groups = "spi_a_mosi_a",
+ "spi_a_miso_a",
+ "spi_a_sclk_a";
+ function = "spi_a";
+ drive-strength = <2>;
+ };
+ };
+
+ spicc0_pins2: spicc0_pins2 {
+ mux {
+ groups = "spi_a_mosi_c",
+ "spi_a_miso_c",
+ "spi_a_sclk_c";
+ function = "spi_a";
+ drive-strength = <2>;
+ };
+ };
+
+ spicc1_pins1: spicc1_pins1 {
+ mux {
+ groups = "spi_b_mosi_a",
+ "spi_b_miso_a",
+ "spi_b_sclk_a";
+ function = "spi_b";
+ drive-strength = <2>;
+ };
+ };
+
+ spifc_pins: spifc_pins {
+ mux {
+ groups = "spif_mo",
+ "spif_mi",
+ "spif_clk",
+ "spif_cs",
+ "spif_hold",
+ "spif_wp_n";
+ function = "spif";
+ drive-strength = <3>;
+ };
+ };
+};
diff --git a/arch/arm/dts/meson-c1_skt-panel.dtsi b/arch/arm/dts/meson-c1_skt-panel.dtsi
new file mode 100644
index 0000000..fbb676c
--- /dev/null
+++ b/arch/arm/dts/meson-c1_skt-panel.dtsi
@@ -0,0 +1,742 @@
+/*
+ * arch/arm64/boot/dts/amlogic/mesong12a_skt-panel.dtsi
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+/ {
+ lcd{
+ compatible = "amlogic, lcd-g12a";
+ mode = "tablet";
+ status = "okay";
+ key_valid = <0>;
+ /*
+ clocks = <&clkc CLKID_MIPI_DSI_HOST
+ &clkc CLKID_MIPI_DSI_PHY
+ &clkc CLKID_DSI_MEAS_COMP
+ &clkc CLKID_VCLK2_ENCL
+ &clkc CLKID_VCLK2_VENCL
+ &clkc CLKID_GP0_PLL>;
+ clock-names = "dsi_host_gate",
+ "dsi_phy_gate",
+ "dsi_meas",
+ "encl_top_gate",
+ "encl_int_gate",
+ "gp0_pll";
+ */
+ reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */
+ 0x0 0xff644000 0x0 0x200>; /* dsi_phy */
+ interrupts = <0 3 1
+ 0 56 1>;
+ interrupt-names = "vsync","vsync2";
+ pinctrl_version = <2>; /* for uboot */
+
+ /* power type:
+ * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending)
+ * power index:
+ * (point gpios_index, or extern_index,0xff=invalid)
+ * power value:(0=output low, 1=output high, 2=input)
+ * power delay:(unit in ms)
+ */
+
+ /*lcd_cpu-gpios = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH
+ &gpio GPIOZ_8 GPIO_ACTIVE_HIGH>;
+ */
+ lcd_cpu_gpio_names = "GPIOZ_9","GPIOZ_8";
+
+ lcd_0{
+ model_name = "B080XAN01";
+ interface = "mipi";
+ basic_setting = <768 1024 /*h_active, v_active*/
+ 948 1140 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 119 159>; /*screen_widht, screen_height*/
+ lcd_timing = <64 56 0 /*hs_width, hs_bp, hs_pol*/
+ 50 30 0>; /*vs_width, vs_bp, vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/
+ 0 /*clk_ss_level */
+ 1 /*clk_auto_generate*/
+ 64843200>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 550 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 1 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <0x05 1 0x11
+ 0xfd 1 20 /*delay(ms)*/
+ 0x05 1 0x29
+ 0xfd 1 20 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ dsi_init_off = <0x05 1 0x28
+ 0xfd 1 10 /*delay(ms)*/
+ 0x05 1 0x10
+ 0xfd 1 10 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ extern_init = <0xff>; /*0xff for invalid*/
+
+ /* power step: type, index, value, delay(ms) */
+ power_on_step = <
+ 0 1 0 100
+ 0 0 0 10
+ 0 0 1 20
+ 2 0 0 0
+ 0xff 0 0 0>; /*ending*/
+ power_off_step = <
+ 2 0 0 50
+ 0 0 0 10
+ 0 1 1 100
+ 0xff 0 0 0>; /*ending*/
+ backlight_index = <0>;
+ };
+
+ lcd_1{
+ model_name = "P070ACB_FT";
+ interface = "mipi";
+ basic_setting = <600 1024 /*h_active, v_active*/
+ 770 1070 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 3 5>; /*screen_widht, screen_height*/
+ lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/
+ 6 20 0>; /*vs_width,vs_bp,vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
+ 0 /*clk_ss_level*/
+ 1 /*clk_auto_generate*/
+ 49434000>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 400 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 0 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <
+ 0xff 10
+ 0xf0 3 0 1 30 /* reset high, delay 30ms */
+ 0xf0 3 0 0 10 /* reset low, delay 10ms */
+ 0xf0 3 0 1 30 /* reset high, delay 30ms */
+ 0xfc 2 0x04 3 /* check_reg, check_cnt */
+ 0xff 0>; /* ending flag */
+ dsi_init_off = <0xff 0>; /* ending flag */
+ /* extern_init: 0xff for invalid */
+ extern_init = <2>;
+ /* power step: type,index,value,delay(ms) */
+ power_on_step = <
+ 0 1 0 200 /* panel power on */
+ 2 0 0 0
+ 0xff 0 0 0>;
+ power_off_step = <
+ 2 0 0 0
+ 0 0 0 20 /* reset low */
+ 0 1 1 100 /* panel power off */
+ 0xff 0 0 0>;
+ backlight_index = <0>;
+ };
+
+ lcd_3{
+ model_name = "TL050FHV02CT";
+ interface = "mipi";
+ basic_setting = <1080 1920 /*h_active, v_active*/
+ 1125 2100 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 65 119>; /*screen_widht, screen_height*/
+ lcd_timing = <5 30 0 /*hs_width,hs_bp,hs_pol*/
+ 44 108 0>; /*vs_width,vs_bp,vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
+ 0 /*clk_ss_level*/
+ 1 /*clk_auto_generate*/
+ 118125000>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 960 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 1 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <0xff 0>; /* ending flag */
+ dsi_init_off = <0xff 0>; /* ending flag */
+ /* extern_init: 0xff for invalid */
+ extern_init = <3>;
+ /* power step: type,index,value,delay(ms) */
+ power_on_step = <
+ 0 1 0 200
+ 0 0 1 20
+ 0 0 0 10
+ 0 0 1 20
+ 2 0 0 0
+ 0xff 0 0 0>;
+ power_off_step = <
+ 2 0 0 0
+ 0 0 0 20
+ 0 1 1 100
+ 0xff 0 0 0>;
+ backlight_index = <0>;
+ };
+
+ lcd_4{
+ model_name = "TL070WSH27";
+ interface = "mipi";
+ basic_setting = <1024 600 /*h_active, v_active*/
+ 1250 630 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 154 86>; /*screen_widht, screen_height*/
+ lcd_timing = <80 100 0 /*hs_width, hs_bp, hs_pol*/
+ 5 20 0>; /*vs_width, vs_bp, vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/
+ 0 /*clk_ss_level */
+ 1 /*clk_auto_generate*/
+ 47250000>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 300 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 1 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <0x05 1 0x11
+ 0xfd 1 20 /*delay(ms)*/
+ 0x05 1 0x29
+ 0xfd 1 20 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ dsi_init_off = <0x05 1 0x28
+ 0xfd 1 10 /*delay(ms)*/
+ 0x05 1 0x10
+ 0xfd 1 10 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ extern_init = <0xff>; /*0xff for invalid*/
+
+ /* power step: type, index, value, delay(ms) */
+ power_on_step = <
+ 0 1 0 100
+ 0 0 0 10
+ 0 0 1 20
+ 2 0 0 0
+ 0xff 0 0 0>; /*ending*/
+ power_off_step = <
+ 2 0 0 50
+ 0 0 0 10
+ 0 1 1 100
+ 0xff 0 0 0>; /*ending*/
+ backlight_index = <0>;
+ };
+ };
+
+ lcd_extern{
+ compatible = "amlogic, lcd_extern";
+ status = "okay";
+ i2c_bus = "i2c_bus_0";
+ key_valid = <0>;
+
+ extern_0{
+ index = <0>;
+ extern_name = "mipi_default";/*default*/
+ status = "okay";
+ type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+ cmd_size = <0xff>;
+ init_on = <
+ 0xfd 1 10
+ 0x05 1 0x11
+ 0xfd 1 120 /* delay 120ms */
+ 0x05 1 0x29
+ 0xff 0>; /*ending*/
+ init_off = <
+ 0x05 1 0x28 /* display off */
+ 0xfd 1 10 /* delay 10ms */
+ 0x05 1 0x10 /* sleep in */
+ 0xfd 1 150 /* delay 150ms */
+ 0xff 0>; /*ending*/
+ };
+
+ extern_2{
+ index = <2>;
+ extern_name = "mipi_default";/*P070ACB_FT*/
+ status = "okay";
+ type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+ cmd_size = <0xff>;
+ init_on = <
+ 0x23 2 0xE0 0x00 /* Page 0 */
+ 0x23 2 0xE1 0x93 /* PASSWORD */
+ 0x23 2 0xE2 0x65
+ 0x23 2 0xE3 0xF8
+ 0x23 2 0x80 0x03
+ 0x23 2 0xE0 0x01 /* Page 01 */
+ 0x23 2 0x0C 0x74 /* Set PWRIC */
+ 0x23 2 0x17 0x00 /* Set Gamma Power */
+ 0x23 2 0x18 0xEF /* VGMP=5.1V */
+ 0x23 2 0x19 0x00
+ 0x23 2 0x1A 0x00
+ 0x23 2 0x1B 0xEF /* VGMN=-5.1V */
+ 0x23 2 0x1C 0x00
+ 0x23 2 0x1F 0x70 /* Set Gate Power */
+ 0x23 2 0x20 0x2D
+ 0x23 2 0x21 0x2D
+ 0x23 2 0x22 0x7E
+ 0x23 2 0x26 0xF3 /* VDDD from IOVCC */
+ 0x23 2 0x37 0x09 /* SetPanel */
+ 0x23 2 0x38 0x04 /* SET RGBCYC */
+ 0x23 2 0x39 0x00
+ 0x23 2 0x3A 0x01
+ 0x23 2 0x3C 0x90
+ 0x23 2 0x3D 0xFF
+ 0x23 2 0x3E 0xFF
+ 0x23 2 0x3F 0xFF
+ 0x23 2 0x40 0x02 /* Set TCON */
+ 0x23 2 0x41 0x80
+ 0x23 2 0x42 0x99
+ 0x23 2 0x43 0x14
+ 0x23 2 0x44 0x19
+ 0x23 2 0x45 0x5A
+ 0x23 2 0x4B 0x04
+ 0x23 2 0x55 0x02 /* power voltage */
+ 0x23 2 0x56 0x01
+ 0x23 2 0x57 0x69
+ 0x23 2 0x58 0x0A
+ 0x23 2 0x59 0x0A
+ 0x23 2 0x5A 0x2E /* VGH = 16.2V */
+ 0x23 2 0x5B 0x19 /* VGL = -12V */
+ 0x23 2 0x5C 0x15
+ 0x23 2 0x5D 0x77 /* Gamma */
+ 0x23 2 0x5E 0x56
+ 0x23 2 0x5F 0x45
+ 0x23 2 0x60 0x38
+ 0x23 2 0x61 0x35
+ 0x23 2 0x62 0x27
+ 0x23 2 0x63 0x2D
+ 0x23 2 0x64 0x18
+ 0x23 2 0x65 0x33
+ 0x23 2 0x66 0x34
+ 0x23 2 0x67 0x35
+ 0x23 2 0x68 0x56
+ 0x23 2 0x69 0x45
+ 0x23 2 0x6A 0x4F
+ 0x23 2 0x6B 0x42
+ 0x23 2 0x6C 0x40
+ 0x23 2 0x6D 0x34
+ 0x23 2 0x6E 0x25
+ 0x23 2 0x6F 0x02
+ 0x23 2 0x70 0x77
+ 0x23 2 0x71 0x56
+ 0x23 2 0x72 0x45
+ 0x23 2 0x73 0x38
+ 0x23 2 0x74 0x35
+ 0x23 2 0x75 0x27
+ 0x23 2 0x76 0x2D
+ 0x23 2 0x77 0x18
+ 0x23 2 0x78 0x33
+ 0x23 2 0x79 0x34
+ 0x23 2 0x7A 0x35
+ 0x23 2 0x7B 0x56
+ 0x23 2 0x7C 0x45
+ 0x23 2 0x7D 0x4F
+ 0x23 2 0x7E 0x42
+ 0x23 2 0x7F 0x40
+ 0x23 2 0x80 0x34
+ 0x23 2 0x81 0x25
+ 0x23 2 0x82 0x02
+ 0x23 2 0xE0 0x02 /* Page2 */
+ 0x23 2 0x00 0x53
+ /* GIP_L Pin mapping RESET_EVEN */
+ 0x23 2 0x01 0x55 /* VSSG_EVEN */
+ 0x23 2 0x02 0x55 /* VSSA_EVEN */
+ 0x23 2 0x03 0x51 /* STV2_EVEN */
+ 0x23 2 0x04 0x77 /* VDD2_EVEN */
+ 0x23 2 0x05 0x57 /* VDD1_EVEN */
+ 0x23 2 0x06 0x1F
+ 0x23 2 0x07 0x4F /* CK12 */
+ 0x23 2 0x08 0x4D /* CK10 */
+ 0x23 2 0x09 0x1F
+ 0x23 2 0x0A 0x4B /* CK8 */
+ 0x23 2 0x0B 0x49 /* CK6 */
+ 0x23 2 0x0C 0x1F
+ 0x23 2 0x0D 0x47 /* CK4 */
+ 0x23 2 0x0E 0x45 /* CK2 */
+ 0x23 2 0x0F 0x41 /* STV1_EVEN */
+ 0x23 2 0x10 0x1F
+ 0x23 2 0x11 0x1F
+ 0x23 2 0x12 0x1F
+ 0x23 2 0x13 0x55 /* VGG */
+ 0x23 2 0x14 0x1F
+ 0x23 2 0x15 0x1F
+ 0x23 2 0x16 0x52
+ /* GIP_R Pin mapping RESET_ODD */
+ 0x23 2 0x17 0x55 /* VSSG_ODD */
+ 0x23 2 0x18 0x55 /* VSSA_ODD */
+ 0x23 2 0x19 0x50 /* STV2_ODD */
+ 0x23 2 0x1A 0x77 /* VDD2_ODD */
+ 0x23 2 0x1B 0x57 /* VDD1_ODD */
+ 0x23 2 0x1C 0x1F
+ 0x23 2 0x1D 0x4E /* CK11 */
+ 0x23 2 0x1E 0x4C /* CK9 */
+ 0x23 2 0x1F 0x1F
+ 0x23 2 0x20 0x4A /* CK7 */
+ 0x23 2 0x21 0x48 /* CK5 */
+ 0x23 2 0x22 0x1F
+ 0x23 2 0x23 0x46 /* CK3 */
+ 0x23 2 0x24 0x44 /* CK1 */
+ 0x23 2 0x25 0x40 /* STV1_ODD */
+ 0x23 2 0x26 0x1F
+ 0x23 2 0x27 0x1F
+ 0x23 2 0x28 0x1F
+ 0x23 2 0x29 0x1F
+ 0x23 2 0x2A 0x1F
+ 0x23 2 0x2B 0x55 /* VGG */
+ 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping */
+ 0x23 2 0x2D 0x15
+ 0x23 2 0x2E 0x15
+ 0x23 2 0x2F 0x00
+ 0x23 2 0x30 0x37
+ 0x23 2 0x31 0x17
+ 0x23 2 0x32 0x1F
+ 0x23 2 0x33 0x08
+ 0x23 2 0x34 0x0A
+ 0x23 2 0x35 0x1F
+ 0x23 2 0x36 0x0C
+ 0x23 2 0x37 0x0E
+ 0x23 2 0x38 0x1F
+ 0x23 2 0x39 0x04
+ 0x23 2 0x3A 0x06
+ 0x23 2 0x3B 0x10
+ 0x23 2 0x3C 0x1F
+ 0x23 2 0x3D 0x1F
+ 0x23 2 0x3E 0x1F
+ 0x23 2 0x3F 0x15
+ 0x23 2 0x40 0x1F
+ 0x23 2 0x41 0x1F
+ 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping */
+ 0x23 2 0x43 0x15
+ 0x23 2 0x44 0x15
+ 0x23 2 0x45 0x01
+ 0x23 2 0x46 0x37
+ 0x23 2 0x47 0x17
+ 0x23 2 0x48 0x1F
+ 0x23 2 0x49 0x09
+ 0x23 2 0x4A 0x0B
+ 0x23 2 0x4B 0x1F
+ 0x23 2 0x4C 0x0D
+ 0x23 2 0x4D 0x0F
+ 0x23 2 0x4E 0x1F
+ 0x23 2 0x4F 0x05
+ 0x23 2 0x50 0x07
+ 0x23 2 0x51 0x11
+ 0x23 2 0x52 0x1F
+ 0x23 2 0x53 0x1F
+ 0x23 2 0x54 0x1F
+ 0x23 2 0x55 0x1F
+ 0x23 2 0x56 0x1F
+ 0x23 2 0x57 0x15
+ 0x23 2 0x58 0x40 /* GIP Timing */
+ 0x23 2 0x59 0x00
+ 0x23 2 0x5A 0x00
+ 0x23 2 0x5B 0x10
+ 0x23 2 0x5C 0x14
+ 0x23 2 0x5D 0x40
+ 0x23 2 0x5E 0x01
+ 0x23 2 0x5F 0x02
+ 0x23 2 0x60 0x40
+ 0x23 2 0x61 0x03
+ 0x23 2 0x62 0x04
+ 0x23 2 0x63 0x7A
+ 0x23 2 0x64 0x7A
+ 0x23 2 0x65 0x74
+ 0x23 2 0x66 0x16
+ 0x23 2 0x67 0xB4
+ 0x23 2 0x68 0x16
+ 0x23 2 0x69 0x7A
+ 0x23 2 0x6A 0x7A
+ 0x23 2 0x6B 0x0C
+ 0x23 2 0x6C 0x00
+ 0x23 2 0x6D 0x04
+ 0x23 2 0x6E 0x04
+ 0x23 2 0x6F 0x88
+ 0x23 2 0x70 0x00
+ 0x23 2 0x71 0x00
+ 0x23 2 0x72 0x06
+ 0x23 2 0x73 0x7B
+ 0x23 2 0x74 0x00
+ 0x23 2 0x75 0xBC
+ 0x23 2 0x76 0x00
+ 0x23 2 0x77 0x04
+ 0x23 2 0x78 0x2C
+ 0x23 2 0x79 0x00
+ 0x23 2 0x7A 0x00
+ 0x23 2 0x7B 0x00
+ 0x23 2 0x7C 0x00
+ 0x23 2 0x7D 0x03
+ 0x23 2 0x7E 0x7B
+ 0x23 2 0xE0 0x04 /* Page4 */
+ 0x23 2 0x09 0x11 /* Set RGBCYC2 */
+ 0x23 2 0x0E 0x48
+ 0x23 2 0x2B 0x2B /* ESD Protect */
+ 0x23 2 0x2E 0x44
+ 0x23 2 0xE0 0x00 /* Page0 */
+ 0x23 2 0xE6 0x02 /* Watch dog */
+ 0x23 2 0xE7 0x0C
+ 0x05 1 0x11 /* sleep out */
+ 0xfd 1 120
+ 0x05 1 0x29 /* display on */
+ 0x05 1 0x35
+ 0xfd 1 20 /* delay(ms) */
+ 0xFF 0>; /*ending*/
+ init_off = <
+ 0x05 1 0x28 /* display off */
+ 0xfd 1 10 /* delay 10ms */
+ 0x05 1 0x10 /* sleep in */
+ 0xfd 1 150 /* delay 150ms */
+ 0xff 0>; /*ending*/
+ };
+
+ extern_3{
+ index = <3>;
+ extern_name = "mipi_default";/*TL050FHV02CT*/
+ status = "okay";
+ type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+ cmd_size = <0xff>;
+ init_on = <
+ 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03
+ 0x29 10 0x90 0x03 0x14 0x09 0x00 0x00
+ 0x00 0x38 0x00 0x00
+ 0x29 10 0x91 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00
+ 0x29 12 0x92 0x40 0x0B 0x0C 0x0D 0x0E
+ 0x00 0x38 0x00 0x10 0x03 0x04
+ 0x29 9 0x94 0x00 0x08 0x0B 0x03 0xD2
+ 0x03 0xD3 0x0C
+ 0x29 17 0x95 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00
+ 0x29 3 0x99 0x00 0x00
+ 0x29 12 0x9A 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x29 7 0x9B 0x01 0x38 0x00 0x00 0x00 0x00
+ 0x29 3 0x9C 0x00 0x00
+ 0x29 9 0x9D 0x10 0x10 0x10 0x10 0x10
+ 0x10 0x00 0x00
+ 0x29 3 0x9E 0x00 0x00
+ 0x29 11 0xA0 0x9F 0x1F 0x08 0x1F 0x0A
+ 0x1F 0x00 0x1F 0x14 0x1F
+ 0x29 11 0xA1 0x15 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA2 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA4 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA5 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x15
+ 0x29 11 0xA6 0x1F 0x14 0x1F 0x01 0x1F
+ 0x0B 0x1F 0x09 0x1F 0x1F
+ 0x29 11 0xA7 0x1F 0x1F 0x0B 0x1F 0x09
+ 0x1F 0x01 0x1F 0x15 0x1F
+ 0x29 11 0xA8 0x14 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA9 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xAB 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xAC 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x14
+ 0x29 11 0xAD 0x1F 0x15 0x1F 0x00 0x1F
+ 0x08 0x1F 0x0A 0x1F 0x1F
+ 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00
+ 0x29 4 0xBC 0x00 0x00 0x00
+ 0x29 5 0xB8 0x01 0xAF 0x8F 0x8F
+ 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01
+ 0x29 17 0xD1 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xD2 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xD3 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xD4 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xD5 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xD6 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xD7 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xD8 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xD9 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xDD 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xDE 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xDF 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xE0 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xE1 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xE2 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xE3 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xE4 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xE5 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xE6 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xE7 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xE8 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xE9 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xEA 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xEB 0x03 0xC5 0x03 0xFF
+ 0x29 4 0xB0 0x05 0x05 0x05
+ 0x29 4 0xB1 0x05 0x05 0x05
+ 0x29 4 0xB3 0x10 0x10 0x10
+ 0x29 4 0xB4 0x06 0x06 0x06
+ 0x29 4 0xB6 0x44 0x44 0x44
+ 0x29 4 0xB7 0x34 0x34 0x34
+ 0x29 4 0xB8 0x34 0x34 0x34
+ 0x29 4 0xB9 0x24 0x24 0x24
+ 0x29 4 0xBA 0x24 0x24 0x24
+ 0x29 4 0xBC 0x00 0x70 0x00
+ 0x29 4 0xBD 0x00 0x70 0x00
+ 0x23 2 0xBE 0x50
+ 0x23 2 0x35 0x00
+ 0x13 1 0x11
+ 0xfd 1 200
+ 0x13 1 0x29
+ 0xfd 1 200
+ 0xFF 0>; /*ending*/
+ init_off = <
+ 0x05 1 0x28 /* display off */
+ 0xfd 1 10 /* delay 10ms */
+ 0x05 1 0x10 /* sleep in */
+ 0xfd 1 150 /* delay 150ms */
+ 0xff 0>; /*ending*/
+ };
+ };
+
+ backlight{
+ compatible = "amlogic, backlight-g12a";
+ status = "okay";
+ key_valid = <0>;
+ pinctrl-names = "pwm_on","pwm_off";
+ /* pinctrl-0 = <&pwm_f_pins2>; */
+ /* pinctrl-1 = <&bl_pwm_off_pins>; */
+ pinctrl_version = <2>; /* for uboot */
+ bl_pwm_config = <&bl_pwm_conf>;
+ /*bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH
+ &gpio GPIOH_5 GPIO_ACTIVE_HIGH>;*/
+ bl_gpio_names = "GPIOH_4","GPIOH_5";
+
+ /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/
+ /* power index:(point gpios_index, 0xff=invalid)
+ * power value:(0=output low, 1=output high, 2=input)
+ * power delay:(unit in ms)
+ */
+
+ backlight_0{
+ index = <0>;
+ bl_name = "backlight_pwm";
+ bl_level_default_uboot_kernel = <100 100>;
+ bl_level_attr = <255 10 /*max, min*/
+ 128 128>; /*mid, mid_mapping*/
+ bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */
+ bl_power_attr = <0 /*en_gpio_index*/
+ 1 0 /*on_value, off_value*/
+ 200 200>; /*on_delay(ms), off_delay(ms)*/
+ bl_pwm_port = "PWM_F";
+ bl_pwm_attr = <0 /*pwm_method*/
+ 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/
+ 100 25>; /*duty_max(%), duty_min(%)*/
+ bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/
+ 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/
+ bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */
+ };
+ backlight_1{
+ index = <1>;
+ bl_name = "bl_extern";
+ bl_level_default_uboot_kernel = <100 100>;
+ bl_level_attr = <255 10 /*max, min*/
+ 128 128>; /*mid, mid_mapping*/
+ bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/
+ bl_power_attr = <1 /*en_gpio_index*/
+ 1 0 /*on_value, off_value*/
+ 200 200>; /*on_delay(ms), off_delay(ms)*/
+ bl_extern_index = <0>;
+ };
+ };
+ bl_pwm_conf:bl_pwm_conf{
+ pwm_channel_0 {
+ pwm_port_index = <5>;
+ pwms = <&pwm_ef MESON_PWM_1 30040 0>;
+ };
+ };
+
+ bl_extern{
+ compatible = "amlogic, bl_extern";
+ status = "disabled";
+ i2c_bus = "i2c_bus_3";
+
+ extern_0{
+ index = <0>;
+ extern_name = "i2c_lp8556";
+ type = <0>; /*0=i2c, 1=spi, 2=mipi*/
+ i2c_address = <0x2c>; /*7bit i2c address*/
+ dim_max_min = <255 10>;
+ };
+
+ extern_1{
+ index = <1>;
+ extern_name = "mipi_lt070me05";
+ type = <2>; /*0=i2c, 1=spi, 2=mipi*/
+ dim_max_min = <255 10>;
+ };
+ };
+};/* end of panel */
+
diff --git a/arch/arm/dts/meson-c2-c305x-af400.dts b/arch/arm/dts/meson-c2-c305x-af400.dts
new file mode 100644
index 0000000..69dcdd9
--- /dev/null
+++ b/arch/arm/dts/meson-c2-c305x-af400.dts
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-c2-c305x-af400.dtsi"
+#include "meson-c2_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,af400", "amlogic,c305x", "amlogic,meson-c2";
+ model = "Amlogic Meson C2 AF400 Socket Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <0>;
+ pinctrl-0 = <&external_eth_rmii_pins>;
+ pinctrl-names = "external_eth_rmii_pins";
+ mc_val = <0x1624>;
+};
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c305x-af400.dtsi b/arch/arm/dts/meson-c2-c305x-af400.dtsi
new file mode 100644
index 0000000..f313da1
--- /dev/null
+++ b/arch/arm/dts/meson-c2-c305x-af400.dtsi
@@ -0,0 +1,252 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-c2-c305x.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_b;
+ serial1 = &uart_a;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c_gpio_0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&dwc3 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOD_9";
+ gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_a {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spifc_pins>;
+ max-frequency = <24000000>;
+ max-cs = <2>;
+ /* 512M */
+ clocks = <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_SPIFC_MUX>,
+ <&clkc CLKID_SPIFC_DIV>,
+ <&clkc CLKID_SPIFC_GATE>,
+ <&clkc CLKID_SPIFC_XTAL_GATE>;
+ clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate";
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins1>;
+ cs-gpios = <&gpio GPIOA_8 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins1>;
+ cs-gpios = <&gpio GPIOA_14 0>;
+};
diff --git a/arch/arm/dts/meson-c2-c305x-af401.dts b/arch/arm/dts/meson-c2-c305x-af401.dts
new file mode 100644
index 0000000..707f9c2
--- /dev/null
+++ b/arch/arm/dts/meson-c2-c305x-af401.dts
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-c2-c305x-af401.dtsi"
+#include "meson-c2_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,af401", "amlogic,c305x", "amlogic,meson-c2";
+ model = "Amlogic Meson C2 AF401 Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <0>;
+ pinctrl-0 = <&external_eth_rmii_pins>;
+ pinctrl-names = "external_eth_rmii_pins";
+ mc_val = <0x1624>;
+};
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c305x-af401.dtsi b/arch/arm/dts/meson-c2-c305x-af401.dtsi
new file mode 100644
index 0000000..2857303
--- /dev/null
+++ b/arch/arm/dts/meson-c2-c305x-af401.dtsi
@@ -0,0 +1,251 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-c2-c305x.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_b;
+ serial1 = &uart_a;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x20000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&dwc3 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOD_9";
+ gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_a {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spifc_pins>;
+ max-frequency = <24000000>;
+ max-cs = <2>;
+ /* 512M */
+ clocks = <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_SPIFC_MUX>,
+ <&clkc CLKID_SPIFC_DIV>,
+ <&clkc CLKID_SPIFC_GATE>,
+ <&clkc CLKID_SPIFC_XTAL_GATE>;
+ clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate";
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins1>;
+ cs-gpios = <&gpio GPIOA_8 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins1>;
+ cs-gpios = <&gpio GPIOA_14 0>;
+};
diff --git a/arch/arm/dts/meson-c2-c305x-af402.dts b/arch/arm/dts/meson-c2-c305x-af402.dts
new file mode 100644
index 0000000..d4b56d7
--- /dev/null
+++ b/arch/arm/dts/meson-c2-c305x-af402.dts
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-c2-c305x-af402.dtsi"
+#include "meson-c2_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,af402", "amlogic,c305x", "amlogic,meson-c2";
+ model = "Amlogic Meson C2 AF402 Socket Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <0>;
+ pinctrl-0 = <&external_eth_rmii_pins>;
+ pinctrl-names = "external_eth_rmii_pins";
+ mc_val = <0x1624>;
+};
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c305x-af402.dtsi b/arch/arm/dts/meson-c2-c305x-af402.dtsi
new file mode 100644
index 0000000..ad57a2a
--- /dev/null
+++ b/arch/arm/dts/meson-c2-c305x-af402.dtsi
@@ -0,0 +1,252 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-c2-c305x.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_b;
+ serial1 = &uart_a;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c_gpio_0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&dwc3 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOD_9";
+ gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_a {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spifc_pins>;
+ max-frequency = <96000000>;
+ max-cs = <2>;
+ /* 512M */
+ clocks = <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_SPIFC_MUX>,
+ <&clkc CLKID_SPIFC_DIV>,
+ <&clkc CLKID_SPIFC_GATE>,
+ <&clkc CLKID_SPIFC_XTAL_GATE>;
+ clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate";
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins1>;
+ cs-gpios = <&gpio GPIOA_8 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins1>;
+ cs-gpios = <&gpio GPIOA_14 0>;
+};
diff --git a/arch/arm/dts/meson-c2-c305x-af409.dts b/arch/arm/dts/meson-c2-c305x-af409.dts
new file mode 100644
index 0000000..b0d4fdc
--- /dev/null
+++ b/arch/arm/dts/meson-c2-c305x-af409.dts
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-c2-c305x-af409.dtsi"
+#include "meson-c2_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,af409", "amlogic,c305x", "amlogic,meson-c2";
+ model = "Amlogic Meson C2 AF409 Socket Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <0>;
+ pinctrl-0 = <&external_eth_rmii_pins>;
+ pinctrl-names = "external_eth_rmii_pins";
+ mc_val = <0x1624>;
+};
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c305x-af409.dtsi b/arch/arm/dts/meson-c2-c305x-af409.dtsi
new file mode 100644
index 0000000..f313da1
--- /dev/null
+++ b/arch/arm/dts/meson-c2-c305x-af409.dtsi
@@ -0,0 +1,252 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-c2-c305x.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_b;
+ serial1 = &uart_a;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c_gpio_0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&dwc3 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOD_9";
+ gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_a {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spifc_pins>;
+ max-frequency = <24000000>;
+ max-cs = <2>;
+ /* 512M */
+ clocks = <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_SPIFC_MUX>,
+ <&clkc CLKID_SPIFC_DIV>,
+ <&clkc CLKID_SPIFC_GATE>,
+ <&clkc CLKID_SPIFC_XTAL_GATE>;
+ clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate";
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins1>;
+ cs-gpios = <&gpio GPIOA_8 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins1>;
+ cs-gpios = <&gpio GPIOA_14 0>;
+};
diff --git a/arch/arm/dts/meson-c2-c305x-af419.dts b/arch/arm/dts/meson-c2-c305x-af419.dts
new file mode 100644
index 0000000..3799307
--- /dev/null
+++ b/arch/arm/dts/meson-c2-c305x-af419.dts
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-c2-c305x-af419.dtsi"
+#include "meson-c2_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,af419", "amlogic,c305x", "amlogic,meson-c2";
+ model = "Amlogic Meson C2 AF419 Socket Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <0>;
+ pinctrl-0 = <&external_eth_rmii_pins>;
+ pinctrl-names = "external_eth_rmii_pins";
+ mc_val = <0x1624>;
+};
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2-c305x-af419.dtsi b/arch/arm/dts/meson-c2-c305x-af419.dtsi
new file mode 100644
index 0000000..f313da1
--- /dev/null
+++ b/arch/arm/dts/meson-c2-c305x-af419.dtsi
@@ -0,0 +1,252 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-c2-c305x.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_b;
+ serial1 = &uart_a;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c_gpio_0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&dwc3 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOD_9";
+ gpios = <&gpio GPIOD_9 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_a {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spifc_pins>;
+ max-frequency = <24000000>;
+ max-cs = <2>;
+ /* 512M */
+ clocks = <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_SPIFC_MUX>,
+ <&clkc CLKID_SPIFC_DIV>,
+ <&clkc CLKID_SPIFC_GATE>,
+ <&clkc CLKID_SPIFC_XTAL_GATE>;
+ clock-names = "fclk_source", "spifc_mux", "spifc_div", "spifc_gate", "spifc_xtal_gate";
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins1>;
+ cs-gpios = <&gpio GPIOA_8 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins1>;
+ cs-gpios = <&gpio GPIOA_14 0>;
+};
diff --git a/arch/arm/dts/meson-c2-c305x.dtsi b/arch/arm/dts/meson-c2-c305x.dtsi
new file mode 100644
index 0000000..9668492
--- /dev/null
+++ b/arch/arm/dts/meson-c2-c305x.dtsi
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "meson-c2.dtsi"
+#include "meson-c2-mali.dtsi"
+
+/ {
+ compatible = "amlogic,c305x", "amlogic,meson-c2";
+};
+
+ðmac {
+ phy-mode = "rmii";
+ phy-handle = <&internal_phy>;
+};
diff --git a/arch/arm/dts/meson-c2-mali.dtsi b/arch/arm/dts/meson-c2-mali.dtsi
new file mode 100644
index 0000000..2655b42
--- /dev/null
+++ b/arch/arm/dts/meson-c2-mali.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+&apb {
+ mali: gpu@40000 {
+ compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
+ reg = <0x0 0x40000 0x0 0x40000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp", "gpmmu", "pp", "pmu",
+ "pp0", "ppmmu0", "pp1", "ppmmu1",
+ "pp2", "ppmmu2";
+ /*clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;*/
+ clock-names = "bus", "core";
+
+ /*
+ * Mali clocking is provided by two identical clock paths
+ * MALI_0 and MALI_1 muxed to a single clock by a glitch
+ * free mux to safely change frequency while running.
+ */
+ /*
+ assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+ <&clkc CLKID_MALI_0>,
+ <&clkc CLKID_MALI>; *//* Glitch free mux */
+ /*assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+ <0>, *//* Do Nothing */
+ //<&clkc CLKID_MALI_0>;
+ /*assigned-clock-rates = <0>,*/ /* Do Nothing */
+ /* <666666666>,
+ <0>;*/ /* Do Nothing */
+ };
+};
diff --git a/arch/arm/dts/meson-c2-pxp.dts b/arch/arm/dts/meson-c2-pxp.dts
new file mode 100644
index 0000000..02c94a0
--- /dev/null
+++ b/arch/arm/dts/meson-c2-pxp.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-c2-c305x-af409.dtsi"
+#include "meson-c2_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,af409", "amlogic,c305x", "amlogic,meson-c2";
+ model = "Amlogic Meson C2 AF409 Socket Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-c2.dtsi b/arch/arm/dts/meson-c2.dtsi
new file mode 100644
index 0000000..ea5b4bb
--- /dev/null
+++ b/arch/arm/dts/meson-c2.dtsi
@@ -0,0 +1,776 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "meson-c-series.dtsi"
+#include <dt-bindings/gpio/meson-c2-gpio.h>
+#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
+
+/ {
+ compatible = "amlogic,meson-c2";
+
+ vpu {
+ compatible = "amlogic, vpu-g12a";
+ status = "okay";
+ /*clocks = <&clkc CLKID_VAPB_MUX>,
+ * <&clkc CLKID_VPU_INTR>,
+ * <&clkc CLKID_VPU_P0_COMP>,
+ * <&clkc CLKID_VPU_P1_COMP>,
+ * <&clkc CLKID_VPU_MUX>;
+ *clock-names = "vapb_clk",
+ * "vpu_intr_gate",
+ * "vpu_clk0",
+ * "vpu_clk1",
+ * "vpu_clk";
+ */
+ clk_level = <7>;
+ /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
+ /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */
+ };
+
+ meson-fb {
+ status = "okay";
+ logo_addr = "0x7f800000";
+ };
+};
+
+ðmac {
+ compatible = "amlogic,g12a-eth-dwmac";
+ reg = <0x0 0xff080000 0x0 0x10000
+ 0x0 0xFE009000 0x0 0x8
+ 0x0 0xFE009400 0x0 0xa0>;
+ reg-names = "eth_base", "eth_top", "eth_cfg";
+ phy_cntl1 = <0x41054147>;
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ reset-gpios = <&gpio GPIOX_20 GPIO_ACTIVE_HIGH>;
+ analog_ver = <2>; /*1:c1; 2:c2*/
+ pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>;
+ analog_val = <0x20200000 0x0000c000 0x00000023>;
+ tx_amp_src = <0xfe005b30>;
+// clocks = <&clkc CLKID_ETH_CORE>,
+// <&clkc CLKID_FCLK_DIV2>,
+// <&clkc CLKID_MPLL2>;
+// clock-names = "stmmaceth", "clkin0", "clkin1";
+
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+};
+
+&cbus {
+ pinctrl_periphs: pinctrl@0400 {
+ compatible = "amlogic,meson-c2-periphs-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio: bank@0400 {
+ reg = <0x0 0x0400 0x0 0x0040>,
+ <0x0 0x0480 0x0 0x01d8>;
+ reg-names = "mux",
+ "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_periphs 0 0 90>;
+ };
+ };
+
+ i2c_gpio_0: i2c-gpio-0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "i2c-gpio";
+ status = "okay";
+ gpios = <&gpio GPIOM_12 GPIO_ACTIVE_HIGH>, /* SDA */
+ <&gpio GPIOM_13 GPIO_ACTIVE_HIGH>; /* CLK */
+
+ i2c-gpio,delay-us = <5>;
+ };
+};
+
+&periphs {
+
+ eth-phy-mux {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x15c 0x0 0x4>;
+ mux-mask = <0xffffffff>;
+ mdio-parent-bus = <&mdio0>;
+
+ internal_mdio: mdio@e40908ff {
+ reg = <0xe40908ff>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ internal_phy: ethernet-phy@8 {
+ compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
+ reg = <8>;
+ max-speed = <100>;
+ };
+ };
+
+ external_mdio: mdio@2009087f {
+ reg = <0x2009087f>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&saradc {
+ compatible = "amlogic,meson-c2-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SARADC_MUX>,
+ <&clkc CLKID_SARADC_DIV>,
+ <&clkc CLKID_SAR_ADC_GATE>;
+ clock-names = "xtal", "adc_mux", "adc_div", "adc_gate";
+};
+
+&sd_emmc_a {
+ clocks = <&clkc CLKID_SD_EMMC_A_MUX>,
+ <&clkc CLKID_SD_EMMC_A_DIV>,
+ <&clkc CLKID_SD_EMMC_A_GATE>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_SD_EMMC_A_XTAL_GATE>;
+ clock-names = "mux", "div", "gate", "clkin", "xtal";
+};
+
+&sd_emmc_b {
+ clocks = <&clkc CLKID_SD_EMMC_B_MUX>,
+ <&clkc CLKID_SD_EMMC_B_DIV>,
+ <&clkc CLKID_SD_EMMC_B_GATE>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_SD_EMMC_B_XTAL_GATE>;
+ clock-names = "mux", "div", "gate", "clkin", "xtal";
+};
+
+&sd_emmc_c {
+ clocks = <&clkc CLKID_SD_EMMC_C_MUX>,
+ <&clkc CLKID_SD_EMMC_C_DIV>,
+ <&clkc CLKID_SD_EMMC_C_GATE>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_SD_EMMC_C_XTAL_GATE>;
+ clock-names = "mux", "div", "gate", "clkin", "xtal";
+};
+
+&nand {
+ clocks = <&clkc CLKID_SD_EMMC_C_MUX>,
+ <&clkc CLKID_SD_EMMC_C_DIV>,
+ <&clkc CLKID_SD_EMMC_C_GATE>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_SD_EMMC_C_XTAL_GATE>;
+ clock-names = "mux", "div", "gate", "fdiv2", "xtal";
+};
+
+&spicc0 {
+ clocks = <&clkc CLKID_SPICC_A_DIV>, <&clkc CLKID_SPICC_A_GATE>;
+ clock-names = "async", "async-gate";
+ assigned-clocks = <&clkc CLKID_SPICC_A_MUX>, <&clkc CLKID_SPICC_A_DIV>;
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
+ assigned-clock-rates = <0>, <200000000>;
+ /* =PM_SPICC, no set for power on already */
+ /* pm-id = <22>; */
+};
+
+&spicc1 {
+ clocks = <&clkc CLKID_SPICC_B_DIV>, <&clkc CLKID_SPICC_B_GATE>;
+ clock-names = "async", "async-gate";
+ assigned-clocks = <&clkc CLKID_SPICC_B_MUX>, <&clkc CLKID_SPICC_B_DIV>;
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
+ assigned-clock-rates = <0>, <200000000>;
+ /* =PM_SPICC_B, must set to power on */
+ pm-id = <39>;
+};
+
+&pinctrl_periphs {
+ jtag_a_pins:jtag_a_pin {
+ mux {
+ groups = "jtag_a_clk",
+ "jtag_a_tms",
+ "jtag_a_tdi",
+ "jtag_a_tdo";
+ function = "jtag_a";
+ };
+ };
+
+ jtag_b_pins:jtag_b_pin {
+ mux {
+ groups = "jtag_b_clk",
+ "jtag_b_tms",
+ "jtag_b_tdi",
+ "jtag_b_tdo";
+ function = "jtag_b";
+ };
+ };
+
+ swd_a_pins:swd_a_pin {
+ mux {
+ groups = "swclk",
+ "swdio";
+ function = "sw";
+ };
+ };
+
+ /*i2c0 pinmux*/
+ i2c0_master_pins1:i2c0_pins1 {
+ mux {
+ groups = "i2c_a_scl_d",
+ "i2c_a_sda_d";
+ function = "i2c_a";
+ bias-disable;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c0_master_pins2:i2c0_pins2 {
+ mux {
+ groups = "i2c_a_scl_e",
+ "i2c_a_sda_e";
+ function = "i2c_a";
+ bias-disable;
+ drive-strength = <3>;
+ };
+ };
+
+ /* i2c1 pinmux */
+ i2c1_master_pins2:i2c1_pins2 {
+ mux {
+ groups = "i2c_b_scl_a",
+ "i2c_b_sda_a";
+ function = "i2c_b";
+ bias-disable;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c1_master_pins3:i2c1_pins3 {
+ mux {
+ groups = "i2c_b_scl_m",
+ "i2c_b_sda_m";
+ function = "i2c_b";
+ bias-disable;
+ drive-strength = <3>;
+ };
+ };
+
+ /* i2c2 pinmux */
+ i2c2_master_pins1:i2c2_pins1 {
+ mux {
+ groups = "i2c_c_scl_x",
+ "i2c_c_sda_x";
+ function = "i2c_c";
+ bias-disable;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c2_master_pins2:i2c2_pins2 {
+ mux {
+ groups = "i2c_c_scl_m",
+ "i2c_c_sda_m";
+ function = "i2c_c";
+ bias-disable;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c2_master_pins3:i2c2_pins3 {
+ mux {
+ groups = "i2c_c_scl_a",
+ "i2c_c_sda_a";
+ function = "i2c_c";
+ bias-disable;
+ drive-strength = <3>;
+ };
+ };
+
+ /* i2c3 pinmux */
+ i2c3_master_pins1:i2c3_pins1 {
+ mux {
+ groups = "i2c_d_scl_x",
+ "i2c_d_sda_x";
+ function = "i2c_d";
+ bias-disable;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c3_master_pins2:i2c3_pins2 {
+ mux {
+ groups = "i2c_d_scl_a",
+ "i2c_d_sda_a";
+ function = "i2c_d";
+ bias-disable;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c3_master_pins3:i2c3_pins3 {
+ mux {
+ groups = "i2c_d_scl_m",
+ "i2c_d_sda_m";
+ function = "i2c_d";
+ bias-disable;
+ drive-strength = <3>;
+ };
+ };
+
+ /* i2c4 pinmux */
+ i2c4_master_pins1:i2c4_pins1 {
+ mux {
+ groups = "i2c_e_scl_c",
+ "i2c_e_sda_c";
+ function = "i2c_e";
+ bias-disable;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c4_master_pins2:i2c4_pins2 {
+ mux {
+ groups = "i2c_e_scl_m",
+ "i2c_e_sda_m";
+ function = "i2c_e";
+ bias-disable;
+ drive-strength = <3>;
+ };
+ };
+
+ i2c4_master_pins3:i2c4_pins3 {
+ mux {
+ groups = "i2c_e_scl_a",
+ "i2c_e_sda_a";
+ function = "i2c_e";
+ bias-disable;
+ drive-strength = <3>;
+ };
+ };
+
+ pwm_a_pins1: pwm_a_pins1 {
+ mux {
+ groups = "pwm_a";
+ function = "pwm_a";
+ };
+ };
+
+ pwm_b_pins1: pwm_b_pins1 {
+ mux {
+ groups = "pwm_b";
+ function = "pwm_b";
+ };
+ };
+
+ pwm_c_pins1: pwm_c_pins1 {
+ mux {
+ groups = "pwm_c";
+ function = "pwm_c";
+ };
+ };
+
+ pwm_d_pins1: pwm_d_pins1 {
+ mux {
+ groups = "pwm_d";
+ function = "pwm_d";
+ };
+ };
+
+ pwm_e_pins1: pwm_e_pins1 {
+ mux {
+ groups = "pwm_e";
+ function = "pwm_e";
+ };
+ };
+
+ pwm_f_pins1: pwm_f_pins1 {
+ mux {
+ groups = "pwm_f_d";
+ function = "pwm_f";
+ };
+ };
+
+ pwm_f_pins2: pwm_f_pins2 {
+ mux {
+ groups = "pwm_f_m";
+ function = "pwm_f";
+ };
+ };
+
+ pwm_f_pins3: pwm_f_pins3 {
+ mux {
+ groups = "pwm_f_x";
+ function = "pwm_f";
+ };
+ };
+
+ pwm_g_pins1: pwm_g_pins1 {
+ mux {
+ groups = "pwm_g_d10";
+ function = "pwm_g";
+ };
+ };
+
+ pwm_g_pins2: pwm_g_pins2 {
+ mux {
+ groups = "pwm_g_x";
+ function = "pwm_g";
+ };
+ };
+
+ pwm_g_pins3: pwm_g_pins3 {
+ mux {
+ groups = "pwm_g_m";
+ function = "pwm_g";
+ };
+ };
+
+ pwm_g_pins4: pwm_g_pins4 {
+ mux {
+ groups = "pwm_g_a7";
+ function = "pwm_g";
+ };
+ };
+
+ pwm_g_pins5: pwm_g_pins5 {
+ mux {
+ groups = "pwm_g_a1";
+ function = "pwm_g";
+ };
+ };
+
+ pwm_g_pins6: pwm_g_pins6 {
+ mux {
+ groups = "pwm_g_d12";
+ function = "pwm_g";
+ };
+ };
+
+ pwm_g_pins7: pwm_g_pins7 {
+ mux {
+ groups = "pwm_g_d13";
+ function = "pwm_g";
+ };
+ };
+
+ pwm_h_pins1: pwm_h_pins1 {
+ mux {
+ groups = "pwm_h_x";
+ function = "pwm_h";
+ };
+ };
+
+ pwm_h_pins2: pwm_h_pins2 {
+ mux {
+ groups = "pwm_h_m";
+ function = "pwm_h";
+ };
+ };
+
+ pwm_h_pins3: pwm_h_pins3 {
+ mux {
+ groups = "pwm_h_a8";
+ function = "pwm_h";
+ };
+ };
+
+ pwm_h_pins4: pwm_h_pins4 {
+ mux {
+ groups = "pwm_h_a2";
+ function = "pwm_h";
+ };
+ };
+
+ pwm_h_pins5: pwm_h_pins5 {
+ mux {
+ groups = "pwm_h_d";
+ function = "pwm_h";
+ };
+ };
+
+ pwm_i_pins1: pwm_i_pins1 {
+ mux {
+ groups = "pwm_i_m";
+ function = "pwm_i";
+ };
+ };
+
+ pwm_i_pins2: pwm_i_pins2 {
+ mux {
+ groups = "pwm_i_a9";
+ function = "pwm_i";
+ };
+ };
+
+ pwm_i_pins3: pwm_i_pins3 {
+ mux {
+ groups = "pwm_i_a3";
+ function = "pwm_i";
+ };
+ };
+
+ pwm_i_pins4: pwm_i_pins4 {
+ mux {
+ groups = "pwm_i_d";
+ function = "pwm_i";
+ };
+ };
+
+ pwm_j_pins1: pwm_j_pins1 {
+ mux {
+ groups = "pwm_j_x";
+ function = "pwm_j";
+ };
+ };
+
+ pwm_j_pins2: pwm_j_pins2 {
+ mux {
+ groups = "pwm_j_m";
+ function = "pwm_j";
+ };
+ };
+
+ pwm_j_pins3: pwm_j_pins3 {
+ mux {
+ groups = "pwm_j_a10";
+ function = "pwm_j";
+ };
+ };
+
+ pwm_j_pins4: pwm_j_pins4 {
+ mux {
+ groups = "pwm_j_a4";
+ function = "pwm_j";
+ };
+ };
+
+ emmc_pins: emmc {
+ mux {
+ groups = "emmc_nand_d0",
+ "emmc_nand_d1",
+ "emmc_nand_d2",
+ "emmc_nand_d3",
+ "emmc_nand_d4",
+ "emmc_nand_d5",
+ "emmc_nand_d6",
+ "emmc_nand_d7",
+ "emmc_clk",
+ "emmc_cmd";
+ function = "emmc";
+ bias-pull-up;
+ input-enable;
+ drive-strength = <3>;
+ };
+ mux1 {
+ groups = "emmc_nand_ds";
+ function = "emmc";
+ input-enable;
+ bias-pull-down;
+ drive-strength = <3>;
+ };
+ };
+
+ emmc_clk_gate_pins: emmc_clk_gate {
+ mux {
+ groups = "emmc_clk";
+ function = "emmc";
+ bias-pull-down;
+ drive-strength = <3>;
+ };
+ };
+
+ all_nand_pins: all_nand_pins {
+ mux {
+ groups = "emmc_nand_d0",
+ "emmc_nand_d1",
+ "emmc_nand_d2",
+ "emmc_nand_d3",
+ "emmc_nand_d4",
+ "emmc_nand_d5",
+ "emmc_nand_d6",
+ "emmc_nand_d7",
+ "nand_ce0",
+ "nand_ale",
+ "nand_cle",
+ "nand_wen_clk",
+ "nand_ren_wr";
+ function = "nand";
+ input-enable;
+ drive-strength = <4>;
+ };
+ };
+
+ nand_cs_pins: nand_cs {
+ mux {
+ groups = "nand_ce0";
+ function = "nand";
+ };
+ };
+
+ sdcard_pins: sdcard {
+ mux {
+ groups = "sdcard_d0",
+ "sdcard_d1",
+ "sdcard_d2",
+ "sdcard_d3",
+ "sdcard_cmd";
+ function = "sdcard";
+ bias-pull-up;
+ input-enable;
+ drive-strength = <4>;
+ };
+ mux1 {
+ groups ="sdcard_clk";
+ function = "sdcard";
+ bias-pull-up;
+ output-high;
+ drive-strength = <4>;
+ };
+ };
+
+ sdcard_clk_gate_pins: sdcard_clk_gate {
+ mux {
+ groups = "sdcard_clk";
+ function = "sdcard";
+ bias-pull-down;
+ drive-strength = <4>;
+ };
+ };
+
+ to_sduart_pins: to_sduart_pins{
+ mux {
+ groups = "uart_b_rx_c", "uart_b_tx_c";
+ function = "uart_b";
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
+ sd_to_uart_pins: sd_to_uart_pins{
+ mux {
+ groups = "uart_b_rx_d", "uart_b_tx_d";
+ function = "uart_b";
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
+ spicc0_pins1: spicc0_pins1 {
+ mux {
+ groups = "spi_a_mosi_a",
+ "spi_a_miso_a",
+ "spi_a_sclk_a";
+ function = "spi_a";
+ drive-strength = <2>;
+ };
+ };
+
+ spicc0_pins2: spicc0_pins2 {
+ mux {
+ groups = "spi_a_mosi_c",
+ "spi_a_miso_c",
+ "spi_a_sclk_c";
+ function = "spi_a";
+ drive-strength = <2>;
+ };
+ };
+
+ spicc1_pins1: spicc1_pins1 {
+ mux {
+ groups = "spi_b_mosi_a",
+ "spi_b_miso_a",
+ "spi_b_sclk_a";
+ function = "spi_b";
+ drive-strength = <2>;
+ };
+ };
+
+ spifc_pins: spifc_pins {
+ mux {
+ groups = "spif_mo",
+ "spif_mi",
+ "spif_clk",
+ "spif_cs",
+ "spif_hold",
+ "spif_wp_n";
+ function = "spif";
+ drive-strength = <4>;
+ };
+ };
+ external_eth_rmii_pins: external_eth_rmii_pins {
+ mux {
+ groups = "eth_mdio",
+ "eth_mdc",
+ "eth_rx_clk",
+ "eth_rx_dv",
+ "eth_rxd0",
+ "eth_rxd1",
+ "eth_txen",
+ "eth_txd0",
+ "eth_txd1";
+ function = "eth";
+ drive-strength = <3>;
+ };
+ };
+ external_eth_rgmii_pins: external_eth_rgmii_pins {
+ mux {
+ groups = "eth_mdio",
+ "eth_mdc",
+ "eth_rx_clk",
+ "eth_rx_dv",
+ "eth_rxd0",
+ "eth_rxd1",
+ "eth_rxd2_rgmii",
+ "eth_rxd3_rgmii",
+ "eth_tx_clk",
+ "eth_txen",
+ "eth_txd0",
+ "eth_txd1",
+ "eth_txd2_rgmii",
+ "eth_txd3_rgmii";
+ function = "eth";
+ drive-strength = <3>;
+ };
+ };
+};
diff --git a/arch/arm/dts/meson-c2_skt-panel.dtsi b/arch/arm/dts/meson-c2_skt-panel.dtsi
new file mode 100644
index 0000000..c3ac22e
--- /dev/null
+++ b/arch/arm/dts/meson-c2_skt-panel.dtsi
@@ -0,0 +1,742 @@
+/*
+ * arch/arm64/boot/dts/amlogic/meson-c2__skt-panel.dtsi
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+/ {
+ lcd{
+ compatible = "amlogic, lcd-g12a";
+ mode = "tablet";
+ status = "okay";
+ key_valid = <0>;
+ /*
+ clocks = <&clkc CLKID_MIPI_DSI_HOST
+ &clkc CLKID_MIPI_DSI_PHY
+ &clkc CLKID_DSI_MEAS_COMP
+ &clkc CLKID_VCLK2_ENCL
+ &clkc CLKID_VCLK2_VENCL
+ &clkc CLKID_GP0_PLL>;
+ clock-names = "dsi_host_gate",
+ "dsi_phy_gate",
+ "dsi_meas",
+ "encl_top_gate",
+ "encl_int_gate",
+ "gp0_pll";
+ */
+ reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */
+ 0x0 0xff644000 0x0 0x200>; /* dsi_phy */
+ interrupts = <0 3 1
+ 0 56 1>;
+ interrupt-names = "vsync","vsync2";
+ pinctrl_version = <2>; /* for uboot */
+
+ /* power type:
+ * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending)
+ * power index:
+ * (point gpios_index, or extern_index,0xff=invalid)
+ * power value:(0=output low, 1=output high, 2=input)
+ * power delay:(unit in ms)
+ */
+
+ /*lcd_cpu-gpios = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH
+ &gpio GPIOZ_8 GPIO_ACTIVE_HIGH>;
+ */
+ lcd_cpu_gpio_names = "GPIOZ_9","GPIOZ_8";
+
+ lcd_0{
+ model_name = "B080XAN01";
+ interface = "mipi";
+ basic_setting = <768 1024 /*h_active, v_active*/
+ 948 1140 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 119 159>; /*screen_widht, screen_height*/
+ lcd_timing = <64 56 0 /*hs_width, hs_bp, hs_pol*/
+ 50 30 0>; /*vs_width, vs_bp, vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/
+ 0 /*clk_ss_level */
+ 1 /*clk_auto_generate*/
+ 64843200>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 550 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 1 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <0x05 1 0x11
+ 0xfd 1 20 /*delay(ms)*/
+ 0x05 1 0x29
+ 0xfd 1 20 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ dsi_init_off = <0x05 1 0x28
+ 0xfd 1 10 /*delay(ms)*/
+ 0x05 1 0x10
+ 0xfd 1 10 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ extern_init = <0xff>; /*0xff for invalid*/
+
+ /* power step: type, index, value, delay(ms) */
+ power_on_step = <
+ 0 1 0 100
+ 0 0 0 10
+ 0 0 1 20
+ 2 0 0 0
+ 0xff 0 0 0>; /*ending*/
+ power_off_step = <
+ 2 0 0 50
+ 0 0 0 10
+ 0 1 1 100
+ 0xff 0 0 0>; /*ending*/
+ backlight_index = <0>;
+ };
+
+ lcd_1{
+ model_name = "P070ACB_FT";
+ interface = "mipi";
+ basic_setting = <600 1024 /*h_active, v_active*/
+ 770 1070 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 3 5>; /*screen_widht, screen_height*/
+ lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/
+ 6 20 0>; /*vs_width,vs_bp,vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
+ 0 /*clk_ss_level*/
+ 1 /*clk_auto_generate*/
+ 49434000>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 400 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 0 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <
+ 0xff 10
+ 0xf0 3 0 1 30 /* reset high, delay 30ms */
+ 0xf0 3 0 0 10 /* reset low, delay 10ms */
+ 0xf0 3 0 1 30 /* reset high, delay 30ms */
+ 0xfc 2 0x04 3 /* check_reg, check_cnt */
+ 0xff 0>; /* ending flag */
+ dsi_init_off = <0xff 0>; /* ending flag */
+ /* extern_init: 0xff for invalid */
+ extern_init = <2>;
+ /* power step: type,index,value,delay(ms) */
+ power_on_step = <
+ 0 1 0 200 /* panel power on */
+ 2 0 0 0
+ 0xff 0 0 0>;
+ power_off_step = <
+ 2 0 0 0
+ 0 0 0 20 /* reset low */
+ 0 1 1 100 /* panel power off */
+ 0xff 0 0 0>;
+ backlight_index = <0>;
+ };
+
+ lcd_3{
+ model_name = "TL050FHV02CT";
+ interface = "mipi";
+ basic_setting = <1080 1920 /*h_active, v_active*/
+ 1125 2100 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 65 119>; /*screen_widht, screen_height*/
+ lcd_timing = <5 30 0 /*hs_width,hs_bp,hs_pol*/
+ 44 108 0>; /*vs_width,vs_bp,vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
+ 0 /*clk_ss_level*/
+ 1 /*clk_auto_generate*/
+ 118125000>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 960 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 1 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <0xff 0>; /* ending flag */
+ dsi_init_off = <0xff 0>; /* ending flag */
+ /* extern_init: 0xff for invalid */
+ extern_init = <3>;
+ /* power step: type,index,value,delay(ms) */
+ power_on_step = <
+ 0 1 0 200
+ 0 0 1 20
+ 0 0 0 10
+ 0 0 1 20
+ 2 0 0 0
+ 0xff 0 0 0>;
+ power_off_step = <
+ 2 0 0 0
+ 0 0 0 20
+ 0 1 1 100
+ 0xff 0 0 0>;
+ backlight_index = <0>;
+ };
+
+ lcd_4{
+ model_name = "TL070WSH27";
+ interface = "mipi";
+ basic_setting = <1024 600 /*h_active, v_active*/
+ 1250 630 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 154 86>; /*screen_widht, screen_height*/
+ lcd_timing = <80 100 0 /*hs_width, hs_bp, hs_pol*/
+ 5 20 0>; /*vs_width, vs_bp, vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/
+ 0 /*clk_ss_level */
+ 1 /*clk_auto_generate*/
+ 47250000>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 300 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 1 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <0x05 1 0x11
+ 0xfd 1 20 /*delay(ms)*/
+ 0x05 1 0x29
+ 0xfd 1 20 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ dsi_init_off = <0x05 1 0x28
+ 0xfd 1 10 /*delay(ms)*/
+ 0x05 1 0x10
+ 0xfd 1 10 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ extern_init = <0xff>; /*0xff for invalid*/
+
+ /* power step: type, index, value, delay(ms) */
+ power_on_step = <
+ 0 1 0 100
+ 0 0 0 10
+ 0 0 1 20
+ 2 0 0 0
+ 0xff 0 0 0>; /*ending*/
+ power_off_step = <
+ 2 0 0 50
+ 0 0 0 10
+ 0 1 1 100
+ 0xff 0 0 0>; /*ending*/
+ backlight_index = <0>;
+ };
+ };
+
+ lcd_extern{
+ compatible = "amlogic, lcd_extern";
+ status = "okay";
+ i2c_bus = "i2c_bus_0";
+ key_valid = <0>;
+
+ extern_0{
+ index = <0>;
+ extern_name = "mipi_default";/*default*/
+ status = "okay";
+ type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+ cmd_size = <0xff>;
+ init_on = <
+ 0xfd 1 10
+ 0x05 1 0x11
+ 0xfd 1 120 /* delay 120ms */
+ 0x05 1 0x29
+ 0xff 0>; /*ending*/
+ init_off = <
+ 0x05 1 0x28 /* display off */
+ 0xfd 1 10 /* delay 10ms */
+ 0x05 1 0x10 /* sleep in */
+ 0xfd 1 150 /* delay 150ms */
+ 0xff 0>; /*ending*/
+ };
+
+ extern_2{
+ index = <2>;
+ extern_name = "mipi_default";/*P070ACB_FT*/
+ status = "okay";
+ type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+ cmd_size = <0xff>;
+ init_on = <
+ 0x23 2 0xE0 0x00 /* Page 0 */
+ 0x23 2 0xE1 0x93 /* PASSWORD */
+ 0x23 2 0xE2 0x65
+ 0x23 2 0xE3 0xF8
+ 0x23 2 0x80 0x03
+ 0x23 2 0xE0 0x01 /* Page 01 */
+ 0x23 2 0x0C 0x74 /* Set PWRIC */
+ 0x23 2 0x17 0x00 /* Set Gamma Power */
+ 0x23 2 0x18 0xEF /* VGMP=5.1V */
+ 0x23 2 0x19 0x00
+ 0x23 2 0x1A 0x00
+ 0x23 2 0x1B 0xEF /* VGMN=-5.1V */
+ 0x23 2 0x1C 0x00
+ 0x23 2 0x1F 0x70 /* Set Gate Power */
+ 0x23 2 0x20 0x2D
+ 0x23 2 0x21 0x2D
+ 0x23 2 0x22 0x7E
+ 0x23 2 0x26 0xF3 /* VDDD from IOVCC */
+ 0x23 2 0x37 0x09 /* SetPanel */
+ 0x23 2 0x38 0x04 /* SET RGBCYC */
+ 0x23 2 0x39 0x00
+ 0x23 2 0x3A 0x01
+ 0x23 2 0x3C 0x90
+ 0x23 2 0x3D 0xFF
+ 0x23 2 0x3E 0xFF
+ 0x23 2 0x3F 0xFF
+ 0x23 2 0x40 0x02 /* Set TCON */
+ 0x23 2 0x41 0x80
+ 0x23 2 0x42 0x99
+ 0x23 2 0x43 0x14
+ 0x23 2 0x44 0x19
+ 0x23 2 0x45 0x5A
+ 0x23 2 0x4B 0x04
+ 0x23 2 0x55 0x02 /* power voltage */
+ 0x23 2 0x56 0x01
+ 0x23 2 0x57 0x69
+ 0x23 2 0x58 0x0A
+ 0x23 2 0x59 0x0A
+ 0x23 2 0x5A 0x2E /* VGH = 16.2V */
+ 0x23 2 0x5B 0x19 /* VGL = -12V */
+ 0x23 2 0x5C 0x15
+ 0x23 2 0x5D 0x77 /* Gamma */
+ 0x23 2 0x5E 0x56
+ 0x23 2 0x5F 0x45
+ 0x23 2 0x60 0x38
+ 0x23 2 0x61 0x35
+ 0x23 2 0x62 0x27
+ 0x23 2 0x63 0x2D
+ 0x23 2 0x64 0x18
+ 0x23 2 0x65 0x33
+ 0x23 2 0x66 0x34
+ 0x23 2 0x67 0x35
+ 0x23 2 0x68 0x56
+ 0x23 2 0x69 0x45
+ 0x23 2 0x6A 0x4F
+ 0x23 2 0x6B 0x42
+ 0x23 2 0x6C 0x40
+ 0x23 2 0x6D 0x34
+ 0x23 2 0x6E 0x25
+ 0x23 2 0x6F 0x02
+ 0x23 2 0x70 0x77
+ 0x23 2 0x71 0x56
+ 0x23 2 0x72 0x45
+ 0x23 2 0x73 0x38
+ 0x23 2 0x74 0x35
+ 0x23 2 0x75 0x27
+ 0x23 2 0x76 0x2D
+ 0x23 2 0x77 0x18
+ 0x23 2 0x78 0x33
+ 0x23 2 0x79 0x34
+ 0x23 2 0x7A 0x35
+ 0x23 2 0x7B 0x56
+ 0x23 2 0x7C 0x45
+ 0x23 2 0x7D 0x4F
+ 0x23 2 0x7E 0x42
+ 0x23 2 0x7F 0x40
+ 0x23 2 0x80 0x34
+ 0x23 2 0x81 0x25
+ 0x23 2 0x82 0x02
+ 0x23 2 0xE0 0x02 /* Page2 */
+ 0x23 2 0x00 0x53
+ /* GIP_L Pin mapping RESET_EVEN */
+ 0x23 2 0x01 0x55 /* VSSG_EVEN */
+ 0x23 2 0x02 0x55 /* VSSA_EVEN */
+ 0x23 2 0x03 0x51 /* STV2_EVEN */
+ 0x23 2 0x04 0x77 /* VDD2_EVEN */
+ 0x23 2 0x05 0x57 /* VDD1_EVEN */
+ 0x23 2 0x06 0x1F
+ 0x23 2 0x07 0x4F /* CK12 */
+ 0x23 2 0x08 0x4D /* CK10 */
+ 0x23 2 0x09 0x1F
+ 0x23 2 0x0A 0x4B /* CK8 */
+ 0x23 2 0x0B 0x49 /* CK6 */
+ 0x23 2 0x0C 0x1F
+ 0x23 2 0x0D 0x47 /* CK4 */
+ 0x23 2 0x0E 0x45 /* CK2 */
+ 0x23 2 0x0F 0x41 /* STV1_EVEN */
+ 0x23 2 0x10 0x1F
+ 0x23 2 0x11 0x1F
+ 0x23 2 0x12 0x1F
+ 0x23 2 0x13 0x55 /* VGG */
+ 0x23 2 0x14 0x1F
+ 0x23 2 0x15 0x1F
+ 0x23 2 0x16 0x52
+ /* GIP_R Pin mapping RESET_ODD */
+ 0x23 2 0x17 0x55 /* VSSG_ODD */
+ 0x23 2 0x18 0x55 /* VSSA_ODD */
+ 0x23 2 0x19 0x50 /* STV2_ODD */
+ 0x23 2 0x1A 0x77 /* VDD2_ODD */
+ 0x23 2 0x1B 0x57 /* VDD1_ODD */
+ 0x23 2 0x1C 0x1F
+ 0x23 2 0x1D 0x4E /* CK11 */
+ 0x23 2 0x1E 0x4C /* CK9 */
+ 0x23 2 0x1F 0x1F
+ 0x23 2 0x20 0x4A /* CK7 */
+ 0x23 2 0x21 0x48 /* CK5 */
+ 0x23 2 0x22 0x1F
+ 0x23 2 0x23 0x46 /* CK3 */
+ 0x23 2 0x24 0x44 /* CK1 */
+ 0x23 2 0x25 0x40 /* STV1_ODD */
+ 0x23 2 0x26 0x1F
+ 0x23 2 0x27 0x1F
+ 0x23 2 0x28 0x1F
+ 0x23 2 0x29 0x1F
+ 0x23 2 0x2A 0x1F
+ 0x23 2 0x2B 0x55 /* VGG */
+ 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping */
+ 0x23 2 0x2D 0x15
+ 0x23 2 0x2E 0x15
+ 0x23 2 0x2F 0x00
+ 0x23 2 0x30 0x37
+ 0x23 2 0x31 0x17
+ 0x23 2 0x32 0x1F
+ 0x23 2 0x33 0x08
+ 0x23 2 0x34 0x0A
+ 0x23 2 0x35 0x1F
+ 0x23 2 0x36 0x0C
+ 0x23 2 0x37 0x0E
+ 0x23 2 0x38 0x1F
+ 0x23 2 0x39 0x04
+ 0x23 2 0x3A 0x06
+ 0x23 2 0x3B 0x10
+ 0x23 2 0x3C 0x1F
+ 0x23 2 0x3D 0x1F
+ 0x23 2 0x3E 0x1F
+ 0x23 2 0x3F 0x15
+ 0x23 2 0x40 0x1F
+ 0x23 2 0x41 0x1F
+ 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping */
+ 0x23 2 0x43 0x15
+ 0x23 2 0x44 0x15
+ 0x23 2 0x45 0x01
+ 0x23 2 0x46 0x37
+ 0x23 2 0x47 0x17
+ 0x23 2 0x48 0x1F
+ 0x23 2 0x49 0x09
+ 0x23 2 0x4A 0x0B
+ 0x23 2 0x4B 0x1F
+ 0x23 2 0x4C 0x0D
+ 0x23 2 0x4D 0x0F
+ 0x23 2 0x4E 0x1F
+ 0x23 2 0x4F 0x05
+ 0x23 2 0x50 0x07
+ 0x23 2 0x51 0x11
+ 0x23 2 0x52 0x1F
+ 0x23 2 0x53 0x1F
+ 0x23 2 0x54 0x1F
+ 0x23 2 0x55 0x1F
+ 0x23 2 0x56 0x1F
+ 0x23 2 0x57 0x15
+ 0x23 2 0x58 0x40 /* GIP Timing */
+ 0x23 2 0x59 0x00
+ 0x23 2 0x5A 0x00
+ 0x23 2 0x5B 0x10
+ 0x23 2 0x5C 0x14
+ 0x23 2 0x5D 0x40
+ 0x23 2 0x5E 0x01
+ 0x23 2 0x5F 0x02
+ 0x23 2 0x60 0x40
+ 0x23 2 0x61 0x03
+ 0x23 2 0x62 0x04
+ 0x23 2 0x63 0x7A
+ 0x23 2 0x64 0x7A
+ 0x23 2 0x65 0x74
+ 0x23 2 0x66 0x16
+ 0x23 2 0x67 0xB4
+ 0x23 2 0x68 0x16
+ 0x23 2 0x69 0x7A
+ 0x23 2 0x6A 0x7A
+ 0x23 2 0x6B 0x0C
+ 0x23 2 0x6C 0x00
+ 0x23 2 0x6D 0x04
+ 0x23 2 0x6E 0x04
+ 0x23 2 0x6F 0x88
+ 0x23 2 0x70 0x00
+ 0x23 2 0x71 0x00
+ 0x23 2 0x72 0x06
+ 0x23 2 0x73 0x7B
+ 0x23 2 0x74 0x00
+ 0x23 2 0x75 0xBC
+ 0x23 2 0x76 0x00
+ 0x23 2 0x77 0x04
+ 0x23 2 0x78 0x2C
+ 0x23 2 0x79 0x00
+ 0x23 2 0x7A 0x00
+ 0x23 2 0x7B 0x00
+ 0x23 2 0x7C 0x00
+ 0x23 2 0x7D 0x03
+ 0x23 2 0x7E 0x7B
+ 0x23 2 0xE0 0x04 /* Page4 */
+ 0x23 2 0x09 0x11 /* Set RGBCYC2 */
+ 0x23 2 0x0E 0x48
+ 0x23 2 0x2B 0x2B /* ESD Protect */
+ 0x23 2 0x2E 0x44
+ 0x23 2 0xE0 0x00 /* Page0 */
+ 0x23 2 0xE6 0x02 /* Watch dog */
+ 0x23 2 0xE7 0x0C
+ 0x05 1 0x11 /* sleep out */
+ 0xfd 1 120
+ 0x05 1 0x29 /* display on */
+ 0x05 1 0x35
+ 0xfd 1 20 /* delay(ms) */
+ 0xFF 0>; /*ending*/
+ init_off = <
+ 0x05 1 0x28 /* display off */
+ 0xfd 1 10 /* delay 10ms */
+ 0x05 1 0x10 /* sleep in */
+ 0xfd 1 150 /* delay 150ms */
+ 0xff 0>; /*ending*/
+ };
+
+ extern_3{
+ index = <3>;
+ extern_name = "mipi_default";/*TL050FHV02CT*/
+ status = "okay";
+ type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+ cmd_size = <0xff>;
+ init_on = <
+ 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03
+ 0x29 10 0x90 0x03 0x14 0x09 0x00 0x00
+ 0x00 0x38 0x00 0x00
+ 0x29 10 0x91 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00
+ 0x29 12 0x92 0x40 0x0B 0x0C 0x0D 0x0E
+ 0x00 0x38 0x00 0x10 0x03 0x04
+ 0x29 9 0x94 0x00 0x08 0x0B 0x03 0xD2
+ 0x03 0xD3 0x0C
+ 0x29 17 0x95 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00
+ 0x29 3 0x99 0x00 0x00
+ 0x29 12 0x9A 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x29 7 0x9B 0x01 0x38 0x00 0x00 0x00 0x00
+ 0x29 3 0x9C 0x00 0x00
+ 0x29 9 0x9D 0x10 0x10 0x10 0x10 0x10
+ 0x10 0x00 0x00
+ 0x29 3 0x9E 0x00 0x00
+ 0x29 11 0xA0 0x9F 0x1F 0x08 0x1F 0x0A
+ 0x1F 0x00 0x1F 0x14 0x1F
+ 0x29 11 0xA1 0x15 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA2 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA4 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA5 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x15
+ 0x29 11 0xA6 0x1F 0x14 0x1F 0x01 0x1F
+ 0x0B 0x1F 0x09 0x1F 0x1F
+ 0x29 11 0xA7 0x1F 0x1F 0x0B 0x1F 0x09
+ 0x1F 0x01 0x1F 0x15 0x1F
+ 0x29 11 0xA8 0x14 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA9 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xAB 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xAC 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x14
+ 0x29 11 0xAD 0x1F 0x15 0x1F 0x00 0x1F
+ 0x08 0x1F 0x0A 0x1F 0x1F
+ 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00
+ 0x29 4 0xBC 0x00 0x00 0x00
+ 0x29 5 0xB8 0x01 0xAF 0x8F 0x8F
+ 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01
+ 0x29 17 0xD1 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xD2 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xD3 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xD4 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xD5 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xD6 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xD7 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xD8 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xD9 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xDD 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xDE 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xDF 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xE0 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xE1 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xE2 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xE3 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xE4 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xE5 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xE6 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xE7 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xE8 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xE9 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xEA 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xEB 0x03 0xC5 0x03 0xFF
+ 0x29 4 0xB0 0x05 0x05 0x05
+ 0x29 4 0xB1 0x05 0x05 0x05
+ 0x29 4 0xB3 0x10 0x10 0x10
+ 0x29 4 0xB4 0x06 0x06 0x06
+ 0x29 4 0xB6 0x44 0x44 0x44
+ 0x29 4 0xB7 0x34 0x34 0x34
+ 0x29 4 0xB8 0x34 0x34 0x34
+ 0x29 4 0xB9 0x24 0x24 0x24
+ 0x29 4 0xBA 0x24 0x24 0x24
+ 0x29 4 0xBC 0x00 0x70 0x00
+ 0x29 4 0xBD 0x00 0x70 0x00
+ 0x23 2 0xBE 0x50
+ 0x23 2 0x35 0x00
+ 0x13 1 0x11
+ 0xfd 1 200
+ 0x13 1 0x29
+ 0xfd 1 200
+ 0xFF 0>; /*ending*/
+ init_off = <
+ 0x05 1 0x28 /* display off */
+ 0xfd 1 10 /* delay 10ms */
+ 0x05 1 0x10 /* sleep in */
+ 0xfd 1 150 /* delay 150ms */
+ 0xff 0>; /*ending*/
+ };
+ };
+
+ backlight{
+ compatible = "amlogic, backlight-g12a";
+ status = "okay";
+ key_valid = <0>;
+ pinctrl-names = "pwm_on","pwm_off";
+ /* pinctrl-0 = <&pwm_f_pins2>; */
+ /* pinctrl-1 = <&bl_pwm_off_pins>; */
+ pinctrl_version = <2>; /* for uboot */
+ bl_pwm_config = <&bl_pwm_conf>;
+ /*bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH
+ &gpio GPIOH_5 GPIO_ACTIVE_HIGH>;*/
+ bl_gpio_names = "GPIOH_4","GPIOH_5";
+
+ /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/
+ /* power index:(point gpios_index, 0xff=invalid)
+ * power value:(0=output low, 1=output high, 2=input)
+ * power delay:(unit in ms)
+ */
+
+ backlight_0{
+ index = <0>;
+ bl_name = "backlight_pwm";
+ bl_level_default_uboot_kernel = <100 100>;
+ bl_level_attr = <255 10 /*max, min*/
+ 128 128>; /*mid, mid_mapping*/
+ bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */
+ bl_power_attr = <0 /*en_gpio_index*/
+ 1 0 /*on_value, off_value*/
+ 200 200>; /*on_delay(ms), off_delay(ms)*/
+ bl_pwm_port = "PWM_F";
+ bl_pwm_attr = <0 /*pwm_method*/
+ 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/
+ 100 25>; /*duty_max(%), duty_min(%)*/
+ bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/
+ 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/
+ bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */
+ };
+ backlight_1{
+ index = <1>;
+ bl_name = "bl_extern";
+ bl_level_default_uboot_kernel = <100 100>;
+ bl_level_attr = <255 10 /*max, min*/
+ 128 128>; /*mid, mid_mapping*/
+ bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/
+ bl_power_attr = <1 /*en_gpio_index*/
+ 1 0 /*on_value, off_value*/
+ 200 200>; /*on_delay(ms), off_delay(ms)*/
+ bl_extern_index = <0>;
+ };
+ };
+ bl_pwm_conf:bl_pwm_conf{
+ pwm_channel_0 {
+ pwm_port_index = <5>;
+ pwms = <&pwm_ef MESON_PWM_1 30040 0>;
+ };
+ };
+
+ bl_extern{
+ compatible = "amlogic, bl_extern";
+ status = "disabled";
+ i2c_bus = "i2c_bus_3";
+
+ extern_0{
+ index = <0>;
+ extern_name = "i2c_lp8556";
+ type = <0>; /*0=i2c, 1=spi, 2=mipi*/
+ i2c_address = <0x2c>; /*7bit i2c address*/
+ dim_max_min = <255 10>;
+ };
+
+ extern_1{
+ index = <1>;
+ extern_name = "mipi_lt070me05";
+ type = <2>; /*0=i2c, 1=spi, 2=mipi*/
+ dim_max_min = <255 10>;
+ };
+ };
+};/* end of panel */
+
diff --git a/arch/arm/dts/meson-g12.dtsi b/arch/arm/dts/meson-g12.dtsi
index 52ecf7c..45bb2e9 100644
--- a/arch/arm/dts/meson-g12.dtsi
+++ b/arch/arm/dts/meson-g12.dtsi
@@ -330,14 +330,10 @@
status = "disabled";
spi-flash@0 {
compatible = "spi-flash";
- #address-cells = <1>;
- #size-cells = <0>;
status = "disabled";
};
spi-nand@1 {
compatible = "spi-nand";
- #address-cells = <1>;
- #size-cells = <0>;
status = "disabled";
};
};
@@ -391,12 +387,12 @@
};
};
- aobus: aobus@ff800000 {
+ aobus: aobus@fe000000 {
compatible = "simple-bus";
- reg = <0x0 0xff800000 0x0 0x100000>;
+ reg = <0x0 0xfe000000 0x0 0x100000>;
#address-cells = <2>;
#size-cells = <2>;
- ranges = <0x0 0x0 0x0 0xff800000 0x0 0x100000>;
+ ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x100000>;
clkc_AO: clock-controller@0 {
compatible = "amlogic,g12a-aoclkc";
@@ -404,9 +400,9 @@
#clock-cells = <1>;
};
- uart_AO: serial@3000 {
+ uart_AO: serial@1c00 {
compatible = "amlogic,meson-uart";
- reg = <0x0 0x3000 0x0 0x14>;
+ reg = <0x0 0x1c00 0x0 0x14>;
interrupts = <GIC_SPI 193 IRQ_TYPE_EDGE_RISING>;
clocks = <&xtal>;
status = "disabled";
@@ -507,7 +503,7 @@
};
nand: nfc@ffe07800 {
- compatible = "amlogic,meson-g12a-nfc";
+ compatible = "amlogic,meson-nfc";
reg = <0x0 0xFFE07800 0x0 0x200>;
interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
@@ -521,21 +517,21 @@
#size-cells = <2>;
ranges = <0x0 0x0 0x0 0xffe01000 0x0 0x7f000>;
- sd_emmc_a: mmc@2000 {
+ sd_emmc_a: sdio {
compatible = "";
reg = <0x0 0x2000 0x0 0x800>;
interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
- sd_emmc_b: mmc@4000 {
+ sd_emmc_b: sd {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x4000 0x0 0x800>;
interrupts = <GIC_SPI 190 IRQ_TYPE_EDGE_RISING>;
status = "disabled";
};
- sd_emmc_c: mmc@6000 {
+ sd_emmc_c: emmc {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x6000 0x0 0x800>;
interrupts = <GIC_SPI 191 IRQ_TYPE_EDGE_RISING>;
diff --git a/arch/arm/dts/meson-g12a-s905d2-u200.dtsi b/arch/arm/dts/meson-g12a-s905d2-u200.dtsi
old mode 100644
new mode 100755
index 60b5e01..839642b
--- a/arch/arm/dts/meson-g12a-s905d2-u200.dtsi
+++ b/arch/arm/dts/meson-g12a-s905d2-u200.dtsi
@@ -117,6 +117,7 @@
disable-wp;
pinname = "sdio";
+ card_type = <3>;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&vddao_3v3>;
@@ -135,6 +136,7 @@
disable-wp;
pinname = "sd";
+ card_type = <5>;
init_co_phase = <3>;
init_tx_phase = <0>;
sd_hs_co_phase = <2>;
@@ -142,7 +144,7 @@
sdr104_co_phase = <2>;
sdr104_hs_tx_phase = <0>;
- cd-detect = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
/* cd-inverted; */
vmmc-supply = <&vddao_3v3>;
@@ -165,7 +167,7 @@
mmc-hs200-1_8v;
pinname = "emmc";
-
+ card_type = <1>;
init_co_phase = <3>;
init_tx_phase = <0>;
hs_co_phase = <3>;
@@ -239,11 +241,14 @@
&usb2_phy_v2 {
status = "okay";
portnum = <2>;
+ dwc2_a_reg = <0xff400000>;
};
&usb3_phy_v2 {
status = "okay";
portnum = <0>;
+ gpio-vbus-power = "GPIOH_6";
+ gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
};
&pwm_ef {
diff --git a/arch/arm/dts/meson-g12a-s905d3-elaine-b1.dts b/arch/arm/dts/meson-g12a-s905d3-elaine-b1.dts
deleted file mode 100644
index d178c2f..0000000
--- a/arch/arm/dts/meson-g12a-s905d3-elaine-b1.dts
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2016 Endless Computers, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-#include "meson-g12a-s905d2-u200.dtsi"
-#include "elaine-b1-panel.dtsi"
-
-/ {
- compatible = "amlogic,u200", "amlogic,s905d2", "amlogic,meson-g12a";
- model = "Amlogic Meson G12A (S905D2) U200 Development Board";
-};
-
-/* This UART is brought out to the DB9 connector */
-&uart_AO {
- status = "okay";
-};
-
-&saradc {
- status = "okay";
-};
-
-/* demo for i2c user */
-&i2c2 {
- status= "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_master_pins2>;
-};
-
-&i2c3 {
- status= "okay";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_master_pins2>;
-};
-
-&i2c_AO {
- status= "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&ao_i2c_master_pins1>;
-};
-
-&pinctrl_periphs {
- bl_pwm_off_pins:bl_pwm_off_pin {
- mux {
- groups = "GPIOH_5";
- function = "gpio_periphs";
- output-high;
- };
- };
-}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-g12a-s905d3-elaine-bx.dts b/arch/arm/dts/meson-g12a-s905d3-elaine-bx.dts
deleted file mode 100644
index e292ea7..0000000
--- a/arch/arm/dts/meson-g12a-s905d3-elaine-bx.dts
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2016 Endless Computers, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-#include "meson-g12a-s905d2-u200.dtsi"
-#include "elaine-bx-panel.dtsi"
-
-/ {
- compatible = "amlogic,u200", "amlogic,s905d2", "amlogic,meson-g12a";
- model = "Amlogic Meson G12A (S905D2) U200 Development Board";
-};
-
-/* This UART is brought out to the DB9 connector */
-&uart_AO {
- status = "okay";
-};
-
-&saradc {
- status = "okay";
-};
-
-/* demo for i2c user */
-&i2c2 {
- status= "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_master_pins2>;
-};
-
-&i2c3 {
- status= "okay";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_master_pins2>;
-};
-
-&i2c_AO {
- status= "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&ao_i2c_master_pins1>;
-};
-
-&pinctrl_periphs {
- bl_pwm_off_pins:bl_pwm_off_pin {
- mux {
- groups = "GPIOH_5";
- function = "gpio_periphs";
- output-high;
- };
- };
-}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-g12a-s905d3-elaine-p0.dts b/arch/arm/dts/meson-g12a-s905d3-elaine-p0.dts
deleted file mode 100644
index ab7ec65..0000000
--- a/arch/arm/dts/meson-g12a-s905d3-elaine-p0.dts
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2016 Endless Computers, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-#include "meson-g12a-s905d2-u200.dtsi"
-#include "elaine-p0-panel.dtsi"
-
-/ {
- compatible = "amlogic,u200", "amlogic,s905d2", "amlogic,meson-g12a";
- model = "Amlogic Meson G12A (S905D2) U200 Development Board";
-};
-
-/* This UART is brought out to the DB9 connector */
-&uart_AO {
- status = "okay";
-};
-
-&saradc {
- status = "okay";
-};
-
-/* demo for i2c user */
-&i2c2 {
- status= "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_master_pins2>;
-};
-
-&i2c3 {
- status= "okay";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_master_pins2>;
-};
-
-&i2c_AO {
- status= "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&ao_i2c_master_pins1>;
-};
-
-&pinctrl_periphs {
- bl_pwm_off_pins:bl_pwm_off_pin {
- mux {
- groups = "GPIOH_5";
- function = "gpio_periphs";
- output-high;
- };
- };
-}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-g12a-s905d3-elaine-p1.dts b/arch/arm/dts/meson-g12a-s905d3-elaine-p1.dts
deleted file mode 100644
index f13a466..0000000
--- a/arch/arm/dts/meson-g12a-s905d3-elaine-p1.dts
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2016 Endless Computers, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-#include "meson-g12a-s905d2-u200.dtsi"
-#include "elaine-p1-panel.dtsi"
-
-/ {
- compatible = "amlogic,u200", "amlogic,s905d2", "amlogic,meson-g12a";
- model = "Amlogic Meson G12A (S905D2) U200 Development Board";
-};
-
-/* This UART is brought out to the DB9 connector */
-&uart_AO {
- status = "okay";
-};
-
-&saradc {
- status = "okay";
-};
-
-/* demo for i2c user */
-&i2c2 {
- status= "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_master_pins2>;
-};
-
-&i2c3 {
- status= "okay";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_master_pins2>;
-};
-
-&i2c_AO {
- status= "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&ao_i2c_master_pins1>;
-};
-
-&pinctrl_periphs {
- bl_pwm_off_pins:bl_pwm_off_pin {
- mux {
- groups = "GPIOH_5";
- function = "gpio_periphs";
- output-high;
- };
- };
-}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-g12a-s905d3-elaine-p2.dts b/arch/arm/dts/meson-g12a-s905d3-elaine-p2.dts
deleted file mode 100644
index 128e48e..0000000
--- a/arch/arm/dts/meson-g12a-s905d3-elaine-p2.dts
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2016 Endless Computers, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-#include "meson-g12a-s905d2-u200.dtsi"
-#include "elaine-p2-panel.dtsi"
-
-/ {
- compatible = "amlogic,u200", "amlogic,s905d2", "amlogic,meson-g12a";
- model = "Amlogic Meson G12A (S905D2) U200 Development Board";
-};
-
-/* This UART is brought out to the DB9 connector */
-&uart_AO {
- status = "okay";
-};
-
-&saradc {
- status = "okay";
-};
-
-/* demo for i2c user */
-&i2c2 {
- status= "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_master_pins2>;
-};
-
-&i2c3 {
- status= "okay";
- clock-frequency = <400000>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_master_pins2>;
-};
-
-&i2c_AO {
- status= "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&ao_i2c_master_pins1>;
-};
-
-&pinctrl_periphs {
- bl_pwm_off_pins:bl_pwm_off_pin {
- mux {
- groups = "GPIOH_5";
- function = "gpio_periphs";
- output-high;
- };
- };
-}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-g12a.dtsi b/arch/arm/dts/meson-g12a.dtsi
index 4280551..5f1902b 100644
--- a/arch/arm/dts/meson-g12a.dtsi
+++ b/arch/arm/dts/meson-g12a.dtsi
@@ -69,7 +69,7 @@
meson-fb {
status = "okay";
- logo_addr = "0x5f800000";
+ logo_addr = "0x7f800000";
};
};
@@ -145,7 +145,7 @@
groups = "i2c_ao_sck",
"i2c_ao_sda";
function = "i2c_ao";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -154,7 +154,7 @@
groups = "i2c_ao_sck_e",
"i2c_ao_sda_e";
function = "i2c_ao";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -323,14 +323,14 @@
function = "sdcard";
input-enable;
bias-pull-up;
- drive-strength = <3>;
+ drive-strength = <4>;
};
mux1 {
groups = "sdcard_clk_c";
function = "sdcard";
bias-pull-up;
output-high;
- drive-strength = <3>;
+ drive-strength = <4>;
};
};
@@ -344,14 +344,14 @@
function = "sdcard";
input-enable;
bias-pull-up;
- drive-strength = <3>;
+ drive-strength = <4>;
};
mux1 {
groups = "sdcard_clk_c";
function = "sdcard";
bias-pull-up;
output-high;
- drive-strength = <3>;
+ drive-strength = <4>;
};
};
@@ -362,14 +362,14 @@
function = "sdcard";
input-enable;
bias-pull-up;
- drive-strength = <3>;
+ drive-strength = <4>;
};
mux1 {
groups = "sdcard_clk_c";
function = "sdcard";
bias-pull-up;
output-high;
- drive-strength = <3>;
+ drive-strength = <4>;
};
};
@@ -419,7 +419,7 @@
function = "sdio";
input-enable;
bias-pull-up;
- drive-strength = <3>;
+ drive-strength = <4>;
};
};
@@ -434,7 +434,7 @@
function = "sdio";
input-enable;
bias-pull-up;
- drive-strength = <3>;
+ drive-strength = <4>;
};
};
@@ -444,14 +444,14 @@
function = "gpio_periphs";
input-enable;
bias-pull-up;
- drive-strength = <3>;
+ drive-strength = <4>;
};
mux1 {
groups = "GPIOX_4";
function = "gpio_periphs";
bias-pull-up;
output-high;
- drive-strength = <3>;
+ drive-strength = <4>;
};
};
@@ -465,14 +465,14 @@
function = "gpio_periphs";
input-enable;
bias-pull-up;
- drive-strength = <3>;
+ drive-strength = <4>;
};
mux1 {
groups = "GPIOX_4";
function = "gpio_periphs";
bias-pull-up;
output-high;
- drive-strength = <3>;
+ drive-strength = <4>;
};
};
@@ -532,7 +532,7 @@
groups = "i2c0_sda_c",
"i2c0_sck_c";
function = "i2c0";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -541,7 +541,7 @@
groups = "i2c0_sda_z0",
"i2c0_sck_z1";
function = "i2c0";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -550,7 +550,7 @@
groups = "i2c0_sda_z7",
"i2c0_sck_z8";
function = "i2c0";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -559,7 +559,7 @@
groups = "i2c1_sda_x",
"i2c1_sck_x";
function = "i2c1";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -568,7 +568,7 @@
groups = "i2c1_sda_h2",
"i2c1_sck_h3";
function = "i2c1";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -577,7 +577,7 @@
groups = "i2c1_sda_h6",
"i2c1_sck_h7";
function = "i2c1";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -586,7 +586,7 @@
groups = "i2c2_sda_x",
"i2c2_sck_x";
function = "i2c2";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -595,7 +595,7 @@
groups = "i2c2_sda_z",
"i2c2_sck_z";
function = "i2c2";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -604,7 +604,7 @@
groups = "i2c3_sda_h",
"i2c3_sck_h";
function = "i2c3";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -613,7 +613,7 @@
groups = "i2c3_sda_a",
"i2c3_sck_a";
function = "i2c3";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -700,7 +700,7 @@
"spi0_miso_x",
"spi0_clk_x";
function = "spi0";
- drive-strength = <1>;
+ drive-strength = <2>;
};
};
@@ -710,7 +710,7 @@
"spi0_miso_c",
"spi0_clk_c";
function = "spi0";
- drive-strength = <1>;
+ drive-strength = <2>;
};
};
@@ -720,7 +720,7 @@
"spi1_miso",
"spi1_clk";
function = "spi1";
- drive-strength = <1>;
+ drive-strength = <2>;
};
};
@@ -732,7 +732,7 @@
"nor_hold",
"nor_wp";
function = "nor";
- drive-strength = <3>;
+ drive-strength = <4>;
};
};
@@ -784,7 +784,7 @@
"hdmitx_sck";
function = "hdmitx";
bias-disable;
- drive-strength = <3>;
+ drive-strength = <4>;
};
};
@@ -837,7 +837,7 @@
"eth_txd2_rgmii",
"eth_txd3_rgmii";
function = "eth";
- drive-strength = <3>;
+ drive-strength = <4>;
};
};
};
@@ -916,30 +916,22 @@
<&clkc CLKID_SD_EMMC_C_P0_DIV>,
<&clkc CLKID_SD_EMMC_C_P0_GATE>;
clock-names = "clkin", "clkin1", "clkin2", "clkin3";
- /*amlogic,mmc-syscon = <&sd_emmc_c>;*/
};
-/*
&spicc0 {
- clocks = <&clkc CLKID_SPICC0>,
- <&clkc CLKID_SPICC0_COMP>;
- clock-names = "core", "comp";
+ clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_SPICC0>,
+ <&clkc CLKID_SPICC0_DIV>, <&clkc CLKID_SPICC0_GATE>;
+ clock-names = "core", "core-gate", "async", "async-gate";
+ assigned-clocks = <&clkc CLKID_SPICC0_MUX>, <&clkc CLKID_SPICC0_DIV>;
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
+ assigned-clock-rates = <0>, <200000000>;
};
&spicc1 {
- clocks = <&clkc CLKID_SPICC1>,
- <&clkc CLKID_SPICC1_COMP>;
- clock-names = "core", "comp";
- };
-*/
-
-&usb2_phy_v2 {
- pll-setting-1 = <0x09400414>;
- pll-setting-2 = <0x927E0000>;
- pll-setting-3 = <0xac5f49e5>;
- pll-setting-4 = <0xfe18>;
- pll-setting-5 = <0x8000fff>;
- pll-setting-6 = <0x78000>;
- pll-setting-7 = <0xe0004>;
- pll-setting-8 = <0xe000c>;
+ clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_SPICC1>,
+ <&clkc CLKID_SPICC1_DIV>, <&clkc CLKID_SPICC1_GATE>;
+ clock-names = "core", "core-gate", "async", "async-gate";
+ assigned-clocks = <&clkc CLKID_SPICC1_MUX>, <&clkc CLKID_SPICC1_DIV>;
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
+ assigned-clock-rates = <0>, <200000000>;
};
diff --git a/arch/arm/dts/meson-g12b-a311d-w400.dtsi b/arch/arm/dts/meson-g12b-a311d-w400.dtsi
old mode 100644
new mode 100755
index 28fa8aa..a19771a
--- a/arch/arm/dts/meson-g12b-a311d-w400.dtsi
+++ b/arch/arm/dts/meson-g12b-a311d-w400.dtsi
@@ -117,6 +117,7 @@
disable-wp;
pinname = "sdio";
+ card_type = <3>;
mmc-pwrseq = <&sdio_pwrseq>;
vmmc-supply = <&vddao_3v3>;
@@ -135,6 +136,7 @@
disable-wp;
pinname = "sd";
+ card_type = <5>;
init_co_phase = <2>;
init_tx_phase = <0>;
sd_hs_co_phase = <2>;
@@ -142,7 +144,7 @@
sdr104_co_phase = <2>;
sdr104_hs_tx_phase = <0>;
- cd-detect = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
/* cd-inverted; */
vmmc-supply = <&vddao_3v3>;
@@ -165,6 +167,7 @@
mmc-hs200-1_8v;
pinname = "emmc";
+ card_type = <1>;
init_co_phase = <2>;
init_tx_phase = <0>;
hs_co_phase = <1>;
@@ -188,6 +191,7 @@
&usb2_phy_v2 {
status = "okay";
portnum = <2>;
+ dwc2_a_reg = <0xff400000>;
};
&usb3_phy_v2 {
diff --git a/arch/arm/dts/meson-g12b-t931-newman.dts b/arch/arm/dts/meson-g12b-t931-newman.dts
deleted file mode 100644
index 4a07011..0000000
--- a/arch/arm/dts/meson-g12b-t931-newman.dts
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2016 Endless Computers, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-#include "meson-g12b-t931.dtsi"
-#include "newman-panel.dtsi"
-
-/ {
- compatible = "amlogic,newman", "amlogic,t931", "amlogic,meson-g12b";
- model = "Amlogic Meson G12B (T931) Newman Development Board";
-};
-
-/* This UART is brought out to the DB9 connector */
-&uart_AO {
- status = "okay";
-};
-
-&saradc {
- status = "okay";
-};
-
-/* demo for i2c user */
-&i2c2 {
- status= "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_master_pins2>;
-};
-
-&i2c3 {
- status= "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_master_pins2>;
-};
-
-&i2c_AO {
- status= "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&ao_i2c_master_pins1>;
-};
-
-&pinctrl_periphs {
- bl_pwm_off_pins:bl_pwm_off_pin {
- mux {
- groups = "GPIOH_5";
- function = "gpio_periphs";
- output-high;
- };
- };
-}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-g12b-t931-puddy.dts b/arch/arm/dts/meson-g12b-t931-puddy.dts
deleted file mode 100644
index 37db120..0000000
--- a/arch/arm/dts/meson-g12b-t931-puddy.dts
+++ /dev/null
@@ -1,93 +0,0 @@
-/*
- * Copyright (c) 2016 Endless Computers, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- *
- * This file is dual-licensed: you can use it either under the terms
- * of the GPL or the X11 license, at your option. Note that this dual
- * licensing only applies to this file, and not this project as a
- * whole.
- *
- * a) This library is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of the
- * License, or (at your option) any later version.
- *
- * This library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * Or, alternatively,
- *
- * b) Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use,
- * copy, modify, merge, publish, distribute, sublicense, and/or
- * sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following
- * conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
- * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
- * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
- * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
- * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- */
-
-/dts-v1/;
-
-#include "meson-g12b-t931.dtsi"
-#include "puddy-panel.dtsi"
-
-/ {
- compatible = "amlogic,newman", "amlogic,t931", "amlogic,meson-g12b";
- model = "Amlogic Meson G12B (T931) Newman Development Board";
-};
-
-/* This UART is brought out to the DB9 connector */
-&uart_AO {
- status = "okay";
-};
-
-&saradc {
- status = "okay";
-};
-
-/* demo for i2c user */
-&i2c2 {
- status= "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c2_master_pins2>;
-};
-
-&i2c3 {
- status= "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&i2c3_master_pins2>;
-};
-
-&i2c_AO {
- status= "okay";
- clock-frequency = <100000>;
- pinctrl-names = "default";
- pinctrl-0 = <&ao_i2c_master_pins1>;
-};
-
-&pinctrl_periphs {
- bl_pwm_off_pins:bl_pwm_off_pin {
- mux {
- groups = "GPIOH_5";
- function = "gpio_periphs";
- output-high;
- };
- };
-}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-g12b-t931.dtsi b/arch/arm/dts/meson-g12b-t931.dtsi
deleted file mode 100644
index 16b6166..0000000
--- a/arch/arm/dts/meson-g12b-t931.dtsi
+++ /dev/null
@@ -1,242 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
- * Based on meson-gx-p23x-q20x.dtsi:
- * - Copyright (c) 2016 Endless Computers, Inc.
- * Author: Carlo Caione <carlo@endlessm.com>
- * - Copyright (c) 2016 BayLibre, SAS.
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- */
-
-/* Common DTSI for devices which are based on the P212 reference board. */
-
-#include "meson-g12b.dtsi"
-#include "meson-g12b-mali.dtsi"
-
-/ {
- compatible = "amlogic,t931", "amlogic,meson-g12b";
-};
-
-/ {
- aliases {
- serial0 = &uart_AO;
- serial1 = &uart_A;
- spi0 = &spifc;
- spi1 = &spicc0;
- spi2 = &spicc1;
- i2c0 = &i2c0;
- i2c1 = &i2c1;
- i2c2 = &i2c2;
- i2c3 = &i2c3;
- i2c4 = &i2c_AO;
- };
-
- chosen {
- stdout-path = "serial0:115200n8";
- };
-
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
-
- vddio_boot: regulator-vddio_boot {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_BOOT";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- vddao_3v3: regulator-vddao_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VDDAO_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- vddio_ao18: regulator-vddio_ao18 {
- compatible = "regulator-fixed";
- regulator-name = "VDDIO_AO18";
- regulator-min-microvolt = <1800000>;
- regulator-max-microvolt = <1800000>;
- };
-
- vcc_3v3: regulator-vcc_3v3 {
- compatible = "regulator-fixed";
- regulator-name = "VCC_3V3";
- regulator-min-microvolt = <3300000>;
- regulator-max-microvolt = <3300000>;
- };
-
- emmc_pwrseq: emmc-pwrseq {
- compatible = "mmc-pwrseq-emmc";
- reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
- };
-
- wifi32k: wifi32k {
- compatible = "pwm-clock";
- #clock-cells = <0>;
- clock-frequency = <32768>;
- pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
- };
-
- sdio_pwrseq: sdio-pwrseq {
- compatible = "mmc-pwrseq-simple";
- reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
- clocks = <&wifi32k>;
- clock-names = "ext_clock";
- };
-};
-
-ðmac {
- status = "okay";
- internal_phy = <1>;
- mc_val = <0x4be04>;
- /*mc_val = <0x1621>;*/
-};
-
-&ir {
- status = "disabled";
- //pinctrl-0 = <&remote_input_ao_pins>;
- //pinctrl-names = "default";
-};
-
-&saradc {
- status = "okay";
- vref-supply = <&vddio_ao18>;
-};
-
-/* Wireless SDIO Module */
-&sd_emmc_a {
- status = "disabled";
- //pinctrl-0 = <&sdio_pins>;
- //pinctrl-names = "default";
- #address-cells = <1>;
- #size-cells = <0>;
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <100000000>;
-
- non-removable;
- disable-wp;
-
- pinname = "sdio";
- mmc-pwrseq = <&sdio_pwrseq>;
-
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddio_boot>;
-};
-
-/* SD card */
-&sd_emmc_b {
- status = "okay";
- pinctrl-0 = <&sd_all_pins>;
- pinctrl-names = "default";
-
- bus-width = <4>;
- cap-sd-highspeed;
- max-frequency = <100000000>;
- disable-wp;
-
- pinname = "sd";
- init_co_phase = <2>;
- init_tx_phase = <0>;
- sd_hs_co_phase = <2>;
- sd_hs_tx_phase = <0>;
- sdr104_co_phase = <2>;
- sdr104_hs_tx_phase = <0>;
-
- cd-detect = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
- /* cd-inverted; */
-
- vmmc-supply = <&vddao_3v3>;
- vqmmc-supply = <&vddio_boot>;
-};
-
-/* eMMC */
-&sd_emmc_c {
- status = "okay";
- pinctrl-0 = <&emmc_conf_pull_up &emmc_conf_pull_done>;
- pinctrl-names = "default";
-
- bus-width = <8>;
- cap-sd-highspeed;
- cap-mmc-highspeed;
- max-frequency = <200000000>;
- non-removable;
- disable-wp;
-// mmc-ddr-1_8v;
-// mmc-hs200-1_8v;
-
- pinname = "emmc";
- init_co_phase = <2>;
- init_tx_phase = <0>;
- hs_co_phase = <1>;
- hs_tx_phase = <0>;
- ddr_co_phase = <2>;
- ddr_tx_phase = <0>;
- hs2_co_phase = <2>;
- hs2_tx_phase = <0>;
-
- hw_reset = <&gpio BOOT_12 GPIO_ACTIVE_HIGH>;
-
- mmc-pwrseq = <&emmc_pwrseq>;
- vmmc-supply = <&vcc_3v3>;
- vqmmc-supply = <&vddio_boot>;
-};
-
-&dwc3 {
- status = "okay";
- dr_mode = "host";
-};
-
-&usb2_phy_v2 {
- status = "okay";
- portnum = <2>;
-};
-
-&usb3_phy_v2 {
- status = "okay";
- portnum = <0>;
- gpio-vbus-power = "GPIOH_6";
- gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
-};
-
-&pwm_ef {
- status = "okay";
- //pinctrl-0 = <&pwm_e_pins>;
- pinctrl-names = "default";
-};
-
-/* This is connected to the Bluetooth module: */
-&uart_A {
- status = "okay";
- pinctrl-0 = <&a_uart_pins>;
- pinctrl-names = "default";
- uart-has-rtscts;
-};
-
-&uart_AO {
- status = "okay";
- pinctrl-0 = <&ao_uart_pins>;
- pinctrl-names = "default";
-};
-
-&spifc {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spifc_all_pins>;
- max-frequency = <80000000>;
- max-io = <4>;
- cs-gpios = <&gpio BOOT_14 GPIO_ACTIVE_HIGH>;
- clocks = <&clkc CLKID_CLK81>;
- clock-names = "core";
-};
-
-&spicc1 {
- status = "okay";
- pinctrl-names = "default";
- pinctrl-0 = <&spicc1_pins>;
- cs-gpios = <&gpio GPIOH_6 0>;
-};
diff --git a/arch/arm/dts/meson-g12b.dtsi b/arch/arm/dts/meson-g12b.dtsi
index 92aad7e..f3131ce 100644
--- a/arch/arm/dts/meson-g12b.dtsi
+++ b/arch/arm/dts/meson-g12b.dtsi
@@ -69,7 +69,7 @@
meson-fb {
status = "okay";
- logo_addr = "0x76800000";
+ logo_addr = "0x7f800000";
};
};
@@ -145,7 +145,7 @@
groups = "i2c_ao_sck",
"i2c_ao_sda";
function = "i2c_ao";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -154,7 +154,7 @@
groups = "i2c_ao_sck_e",
"i2c_ao_sda_e";
function = "i2c_ao";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -323,19 +323,18 @@
function = "sdcard";
input-enable;
bias-pull-up;
- drive-strength = <3>;
+ drive-strength = <4>;
};
mux1 {
groups = "sdcard_clk_c";
function = "sdcard";
bias-pull-up;
output-high;
- drive-strength = <3>;
+ drive-strength = <4>;
};
};
sd_all_pins:sd_all_pins {
- /*
mux {
groups = "sdcard_d0_c",
"sdcard_d1_c",
@@ -345,16 +344,15 @@
function = "sdcard";
input-enable;
bias-pull-up;
- drive-strength = <3>;
+ drive-strength = <4>;
};
mux1 {
groups = "sdcard_clk_c";
function = "sdcard";
bias-pull-up;
output-high;
- drive-strength = <3>;
+ drive-strength = <4>;
};
- */
};
sd_1bit_pins:sd_1bit_pins {
@@ -364,14 +362,14 @@
function = "sdcard";
input-enable;
bias-pull-up;
- drive-strength = <3>;
+ drive-strength = <4>;
};
mux1 {
groups = "sdcard_clk_c";
function = "sdcard";
bias-pull-up;
output-high;
- drive-strength = <3>;
+ drive-strength = <4>;
};
};
@@ -421,7 +419,7 @@
function = "sdio";
input-enable;
bias-pull-up;
- drive-strength = <3>;
+ drive-strength = <4>;
};
};
@@ -436,7 +434,7 @@
function = "sdio";
input-enable;
bias-pull-up;
- drive-strength = <3>;
+ drive-strength = <4>;
};
};
@@ -446,14 +444,14 @@
function = "gpio_periphs";
input-enable;
bias-pull-up;
- drive-strength = <3>;
+ drive-strength = <4>;
};
mux1 {
groups = "GPIOX_4";
function = "gpio_periphs";
bias-pull-up;
output-high;
- drive-strength = <3>;
+ drive-strength = <4>;
};
};
@@ -467,14 +465,14 @@
function = "gpio_periphs";
input-enable;
bias-pull-up;
- drive-strength = <3>;
+ drive-strength = <4>;
};
mux1 {
groups = "GPIOX_4";
function = "gpio_periphs";
bias-pull-up;
output-high;
- drive-strength = <3>;
+ drive-strength = <4>;
};
};
@@ -534,7 +532,7 @@
groups = "i2c0_sda_c",
"i2c0_sck_c";
function = "i2c0";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -543,7 +541,7 @@
groups = "i2c0_sda_z0",
"i2c0_sck_z1";
function = "i2c0";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -552,7 +550,7 @@
groups = "i2c0_sda_z7",
"i2c0_sck_z8";
function = "i2c0";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -561,7 +559,7 @@
groups = "i2c1_sda_x",
"i2c1_sck_x";
function = "i2c1";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -570,7 +568,7 @@
groups = "i2c1_sda_h2",
"i2c1_sck_h3";
function = "i2c1";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -579,7 +577,7 @@
groups = "i2c1_sda_h6",
"i2c1_sck_h7";
function = "i2c1";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -588,7 +586,7 @@
groups = "i2c2_sda_x",
"i2c2_sck_x";
function = "i2c2";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -597,7 +595,7 @@
groups = "i2c2_sda_z",
"i2c2_sck_z";
function = "i2c2";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -606,7 +604,7 @@
groups = "i2c3_sda_h",
"i2c3_sck_h";
function = "i2c3";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -615,7 +613,7 @@
groups = "i2c3_sda_a",
"i2c3_sck_a";
function = "i2c3";
- drive-strength = <2>;
+ drive-strength = <3>;
};
};
@@ -712,7 +710,7 @@
"spi0_miso_c",
"spi0_clk_c";
function = "spi0";
- drive-strength = <1>;
+ drive-strength = <2>;
};
};
@@ -722,7 +720,7 @@
"spi1_miso",
"spi1_clk";
function = "spi1";
- drive-strength = <1>;
+ drive-strength = <2>;
};
};
@@ -734,7 +732,7 @@
"nor_hold",
"nor_wp";
function = "nor";
- drive-strength = <1>;
+ drive-strength = <2>;
};
};
@@ -786,7 +784,7 @@
"hdmitx_sck";
function = "hdmitx";
bias-disable;
- drive-strength = <3>;
+ drive-strength = <4>;
};
};
@@ -839,7 +837,7 @@
"eth_txd2_rgmii",
"eth_txd3_rgmii";
function = "eth";
- drive-strength = <3>;
+ drive-strength = <4>;
};
};
};
@@ -912,34 +910,27 @@
};
-/*
&spicc0 {
- clocks = <&clkc CLKID_SPICC0>,
- <&clkc CLKID_SPICC0_COMP>;
- clock-names = "core", "comp";
+ clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_SPICC0>,
+ <&clkc CLKID_SPICC0_DIV>, <&clkc CLKID_SPICC0_GATE>;
+ clock-names = "core", "core-gate", "async", "async-gate";
+ assigned-clocks = <&clkc CLKID_SPICC0_MUX>, <&clkc CLKID_SPICC0_DIV>;
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
+ assigned-clock-rates = <0>, <200000000>;
};
&spicc1 {
- clocks = <&clkc CLKID_SPICC1>,
- <&clkc CLKID_SPICC1_COMP>;
- clock-names = "core", "comp";
- };
-*/
+ clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_SPICC1>,
+ <&clkc CLKID_SPICC1_DIV>, <&clkc CLKID_SPICC1_GATE>;
+ clock-names = "core", "core-gate", "async", "async-gate";
+ assigned-clocks = <&clkc CLKID_SPICC1_MUX>, <&clkc CLKID_SPICC1_DIV>;
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
+ assigned-clock-rates = <0>, <200000000>;
+};
+
/*
&spifc {
clocks = <&clkc CLKID_CLK81>;
clock-names = "core";
};
*/
-&usb2_phy_v2 {
- pll-setting-1 = <0x09400414>;
- pll-setting-2 = <0x927E0000>;
- pll-setting-3 = <0xac5f69e5>;
- pll-setting-4 = <0xfe18>;
- pll-setting-5 = <0xfff>;
- pll-setting-6 = <0x78000>;
- pll-setting-7 = <0xe0004>;
- pll-setting-8 = <0xe000c>;
- disconnect-threshold = <0x3c>;
-};
-
diff --git a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
index d32cf38..5f27542 100644
--- a/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
+++ b/arch/arm/dts/meson-gxl-s905x-khadas-vim.dts
@@ -33,8 +33,6 @@
gpio-keys-polled {
compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
poll-interval = <100>;
button@0 {
diff --git a/arch/arm/dts/meson-gxm-khadas-vim2.dts b/arch/arm/dts/meson-gxm-khadas-vim2.dts
index 313f88f..560fe53 100644
--- a/arch/arm/dts/meson-gxm-khadas-vim2.dts
+++ b/arch/arm/dts/meson-gxm-khadas-vim2.dts
@@ -63,8 +63,6 @@
gpio-keys-polled {
compatible = "gpio-keys-polled";
- #address-cells = <1>;
- #size-cells = <0>;
poll-interval = <100>;
button@0 {
diff --git a/arch/arm/dts/meson-s4-ap201.dts b/arch/arm/dts/meson-s4-ap201.dts
new file mode 100644
index 0000000..553410b
--- /dev/null
+++ b/arch/arm/dts/meson-s4-ap201.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-s4-ap201.dtsi"
+#include "meson-s4_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,s4-ap201", "amlogic,s4-txxx", "amlogic,meson-s4";
+ model = "Amlogic Meson S4 AP201 Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "disabled";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-s4-ap201.dtsi b/arch/arm/dts/meson-s4-ap201.dtsi
new file mode 100644
index 0000000..280a62b
--- /dev/null
+++ b/arch/arm/dts/meson-s4-ap201.dtsi
@@ -0,0 +1,253 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-s4-txxx.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_a;
+ serial1 = &uart_b;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ tee: tee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+};
+
+&vpu {
+ clk_level = <7>;
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "disabled";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ sd_hs_co_phase = <2>;
+ sd_hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&crg {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <2>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOH_6";
+ gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_b {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ cs-gpios = <&gpio GPIOB_13 GPIO_ACTIVE_HIGH>;
+ spi-flash@0 {
+ status = "okay";
+ };
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins1>;
+ //cs-gpios = <&gpio GPIOA_8 0>,
+ // <&gpio GPIOA_9 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins1>;
+ //cs-gpios = <&gpio GPIOA_14 0>;
+};
diff --git a/arch/arm/dts/meson-s4-ap222.dts b/arch/arm/dts/meson-s4-ap222.dts
new file mode 100644
index 0000000..aa22711
--- /dev/null
+++ b/arch/arm/dts/meson-s4-ap222.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-s4-ap222.dtsi"
+#include "meson-s4_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,s4-ap222", "amlogic,s4-txxx", "amlogic,meson-s4";
+ model = "Amlogic Meson S4 AP222 Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "disabled";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-s4-ap222.dtsi b/arch/arm/dts/meson-s4-ap222.dtsi
new file mode 100644
index 0000000..280a62b
--- /dev/null
+++ b/arch/arm/dts/meson-s4-ap222.dtsi
@@ -0,0 +1,253 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-s4-txxx.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_a;
+ serial1 = &uart_b;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ tee: tee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+};
+
+&vpu {
+ clk_level = <7>;
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "disabled";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ sd_hs_co_phase = <2>;
+ sd_hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&crg {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <2>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOH_6";
+ gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_b {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ cs-gpios = <&gpio GPIOB_13 GPIO_ACTIVE_HIGH>;
+ spi-flash@0 {
+ status = "okay";
+ };
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins1>;
+ //cs-gpios = <&gpio GPIOA_8 0>,
+ // <&gpio GPIOA_9 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins1>;
+ //cs-gpios = <&gpio GPIOA_14 0>;
+};
diff --git a/arch/arm/dts/meson-s4-ap229.dts b/arch/arm/dts/meson-s4-ap229.dts
new file mode 100644
index 0000000..8a44c45
--- /dev/null
+++ b/arch/arm/dts/meson-s4-ap229.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-s4-ap229.dtsi"
+#include "meson-s4_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,s4-ap229", "amlogic,s4-txxx", "amlogic,meson-s4";
+ model = "Amlogic Meson S4 AP229 Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "disabled";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-s4-ap229.dtsi b/arch/arm/dts/meson-s4-ap229.dtsi
new file mode 100644
index 0000000..280a62b
--- /dev/null
+++ b/arch/arm/dts/meson-s4-ap229.dtsi
@@ -0,0 +1,253 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-s4-txxx.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_a;
+ serial1 = &uart_b;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ tee: tee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+};
+
+&vpu {
+ clk_level = <7>;
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "disabled";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ sd_hs_co_phase = <2>;
+ sd_hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&crg {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <2>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOH_6";
+ gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_b {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ cs-gpios = <&gpio GPIOB_13 GPIO_ACTIVE_HIGH>;
+ spi-flash@0 {
+ status = "okay";
+ };
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins1>;
+ //cs-gpios = <&gpio GPIOA_8 0>,
+ // <&gpio GPIOA_9 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins1>;
+ //cs-gpios = <&gpio GPIOA_14 0>;
+};
diff --git a/arch/arm/dts/meson-s4-aq222.dts b/arch/arm/dts/meson-s4-aq222.dts
new file mode 100644
index 0000000..7bd7ac2
--- /dev/null
+++ b/arch/arm/dts/meson-s4-aq222.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-s4-aq222.dtsi"
+#include "meson-s4_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,s4-aq222", "amlogic,s4-txxx", "amlogic,meson-s4";
+ model = "Amlogic Meson S4 AQ222 Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "disabled";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-s4-aq222.dtsi b/arch/arm/dts/meson-s4-aq222.dtsi
new file mode 100644
index 0000000..9f7437d
--- /dev/null
+++ b/arch/arm/dts/meson-s4-aq222.dtsi
@@ -0,0 +1,259 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-s4-txxx.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_a;
+ serial1 = &uart_b;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ tee: tee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ amhdmitx {
+ compatible = "amlogic, amhdmitx-s4";
+ status = "okay";
+ res_1080p = <1>;
+ };
+};
+
+&vpu {
+ clk_level = <5>;
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "disabled";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ sd_hs_co_phase = <2>;
+ sd_hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&crg {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <2>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOH_6";
+ gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_b {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ cs-gpios = <&gpio GPIOB_13 GPIO_ACTIVE_HIGH>;
+ spi-flash@0 {
+ status = "okay";
+ };
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins1>;
+ //cs-gpios = <&gpio GPIOA_8 0>,
+ // <&gpio GPIOA_9 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins1>;
+ //cs-gpios = <&gpio GPIOA_14 0>;
+};
diff --git a/arch/arm/dts/meson-s4-aq229.dts b/arch/arm/dts/meson-s4-aq229.dts
new file mode 100644
index 0000000..9bf539f
--- /dev/null
+++ b/arch/arm/dts/meson-s4-aq229.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-s4-aq229.dtsi"
+#include "meson-s4_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,s4-aq229", "amlogic,s4-txxx", "amlogic,meson-s4";
+ model = "Amlogic Meson S4 AQ229 Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "disabled";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-s4-aq229.dtsi b/arch/arm/dts/meson-s4-aq229.dtsi
new file mode 100644
index 0000000..9f7437d
--- /dev/null
+++ b/arch/arm/dts/meson-s4-aq229.dtsi
@@ -0,0 +1,259 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-s4-txxx.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_a;
+ serial1 = &uart_b;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ tee: tee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ amhdmitx {
+ compatible = "amlogic, amhdmitx-s4";
+ status = "okay";
+ res_1080p = <1>;
+ };
+};
+
+&vpu {
+ clk_level = <5>;
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "disabled";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ sd_hs_co_phase = <2>;
+ sd_hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&crg {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <2>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOH_6";
+ gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_b {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ cs-gpios = <&gpio GPIOB_13 GPIO_ACTIVE_HIGH>;
+ spi-flash@0 {
+ status = "okay";
+ };
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins1>;
+ //cs-gpios = <&gpio GPIOA_8 0>,
+ // <&gpio GPIOA_9 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins1>;
+ //cs-gpios = <&gpio GPIOA_14 0>;
+};
diff --git a/arch/arm/dts/meson-s4-mali.dtsi b/arch/arm/dts/meson-s4-mali.dtsi
new file mode 100644
index 0000000..2655b42
--- /dev/null
+++ b/arch/arm/dts/meson-s4-mali.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+&apb {
+ mali: gpu@40000 {
+ compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
+ reg = <0x0 0x40000 0x0 0x40000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp", "gpmmu", "pp", "pmu",
+ "pp0", "ppmmu0", "pp1", "ppmmu1",
+ "pp2", "ppmmu2";
+ /*clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;*/
+ clock-names = "bus", "core";
+
+ /*
+ * Mali clocking is provided by two identical clock paths
+ * MALI_0 and MALI_1 muxed to a single clock by a glitch
+ * free mux to safely change frequency while running.
+ */
+ /*
+ assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+ <&clkc CLKID_MALI_0>,
+ <&clkc CLKID_MALI>; *//* Glitch free mux */
+ /*assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+ <0>, *//* Do Nothing */
+ //<&clkc CLKID_MALI_0>;
+ /*assigned-clock-rates = <0>,*/ /* Do Nothing */
+ /* <666666666>,
+ <0>;*/ /* Do Nothing */
+ };
+};
diff --git a/arch/arm/dts/meson-s4-pxp.dts b/arch/arm/dts/meson-s4-pxp.dts
new file mode 100644
index 0000000..b2b90b4
--- /dev/null
+++ b/arch/arm/dts/meson-s4-pxp.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-s4-pxp.dtsi"
+#include "meson-s4_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,s4-pxp", "amlogic,s4-txxx", "amlogic,meson-s4";
+ model = "Amlogic Meson S4 PXP Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "disabled";
+};
+
+&saradc {
+ status = "disabled";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-s4-pxp.dtsi b/arch/arm/dts/meson-s4-pxp.dtsi
new file mode 100644
index 0000000..e087329
--- /dev/null
+++ b/arch/arm/dts/meson-s4-pxp.dtsi
@@ -0,0 +1,244 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-s4-txxx.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_a;
+ serial1 = &uart_b;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "disabled";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ sd_hs_co_phase = <2>;
+ sd_hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+// mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&crg {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <2>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOH_6";
+ gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_b {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "disabled";
+ //cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>;
+ spi-flash@0 {
+ status = "disabled";
+ };
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins1>;
+ //cs-gpios = <&gpio GPIOA_8 0>,
+ // <&gpio GPIOA_9 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins1>;
+ //cs-gpios = <&gpio GPIOA_14 0>;
+};
diff --git a/arch/arm/dts/meson-s4-series.dtsi b/arch/arm/dts/meson-s4-series.dtsi
new file mode 100644
index 0000000..607e7b7
--- /dev/null
+++ b/arch/arm/dts/meson-s4-series.dtsi
@@ -0,0 +1,511 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pwm/meson.h>
+#include <dt-bindings/clock/s4-clkc.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 16 MiB reserved for Hardware ROM Firmware */
+ hwrom_reserved: hwrom@0 {
+ reg = <0x0 0x0 0x0 0x1000000>;
+ no-map;
+ };
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@10000000 {
+ reg = <0x0 0x10000000 0x0 0x200000>;
+ no-map;
+ };
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0xbc00000>;
+ alignment = <0x0 0x400000>;
+ linux,cma-default;
+ };
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+
+ firmware {
+ sm: secure-monitor {
+ compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
+ };
+ };
+
+ efuse: efuse {
+ compatible = "amlogic,meson-sc2-efuse", "amlogic,meson-sc2-efuse";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ };
+
+ scpi {
+ compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
+ mboxes = <&mailbox 1 &mailbox 2>;
+ shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+
+ scpi_clocks: clocks {
+ compatible = "arm,scpi-clocks";
+
+ scpi_dvfs: scpi_clocks@0 {
+ compatible = "arm,scpi-dvfs-clocks";
+ #clock-cells = <1>;
+ clock-indices = <0>;
+ clock-output-names = "vcpu";
+ };
+ };
+
+ scpi_sensors: sensors {
+ compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@2c001000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xffc01000 0 0x1000>,
+ <0x0 0xffc02000 0 0x2000>,
+ <0x0 0xffc04000 0 0x2000>,
+ <0x0 0xffc06000 0 0x2000>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ };
+
+ sram: sram@f7000000 {
+ compatible = "amlogic,meson-sc2-sram", "amlogic,meson-sc2-sram", "mmio-sram";
+ reg = <0x0 0xf7000000 0x0 0x48000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0xf7000000 0x48000>;
+
+ cpu_scp_lpri: scp-shmem@0 {
+ compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
+ reg = <0x47000 0x400>;
+ };
+
+ cpu_scp_hpri: scp-shmem@200 {
+ compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
+ reg = <0x47400 0x400>;
+ };
+ };
+
+ cbus: cbus@fe070000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xfe070000 0x0 0xF000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xfe070000 0x0 0xF000>;
+
+ uart_a: serial@8000 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x8000 0x0 0x18>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ uart_b: serial@a000 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0xa000 0x0 0x18>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ ir: ir@8040 {
+ compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
+ reg = <0x0 0x8040 0x0 0x40>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ reset: reset-controller@1000 {
+ compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
+ reg = <0x0 0x01000 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
+ uart_c: serial@22000 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x22000 0x0 0x18>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ spicc0: spi@3800 {
+ compatible = "amlogic,meson-g12a-spicc";
+ reg = <0x0 0x3800 0x0 0x44>;
+ interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spicc1: spi@3c00 {
+ compatible = "amlogic,meson-g12a-spicc";
+ reg = <0x0 0x3c00 0x0 0x44>;
+ interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ jtag {
+ compatible = "amlogic, jtag";
+ status = "okay";
+ select = "disable"; /* disable/jtag-a/jtag-b */
+ pinctrl-names="jtag_a_pins", "jtag_b_pins";
+ pinctrl-0=<&jtag_a_pins>;
+ pinctrl-1=<&jtag_b_pins>;
+ };
+ };
+
+ periphs: periphs@ff634000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xff634000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
+
+ hwrng: rng {
+ compatible = "amlogic,meson-rng";
+ reg = <0x0 0x0 0x0 0x4>;
+ };
+ };
+
+ hiubus: hiubus@ff63c000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xff63c000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>;
+
+ mailbox: mailbox@404 {
+ compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
+ reg = <0 0x404 0 0x4c>;
+ interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
+ <0 209 IRQ_TYPE_EDGE_RISING>,
+ <0 210 IRQ_TYPE_EDGE_RISING>;
+ #mbox-cells = <1>;
+ };
+ };
+
+ clkc: clock-controller@0 {
+ compatible = "amlogic,s4-clkc";
+ #clock-cells = <1>;
+ reg = <0x0 0xfe000000 0x0 0x82e8>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ };
+
+ i2c0: i2c@fe066000 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe066000 0x0 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@fe068000 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe068000 0x0 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@fe06a000 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe06a000 0x0 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@fe06c000 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe06c000 0x0 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@fe06e000 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe06e000 0x0 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spifc: spi@fe056000 {
+ compatible = "amlogic,spifc";
+ status = "disabled";
+ reg = <0x0 0xfe056000 0x0 0x80>;
+ /* clocks = <&clkc CLKID_CLK81>; */
+ /* clock-names = "core"; */
+ pinctrl-names = "default";
+ pinctrl-0 = <&spifc_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ status = "disabled";
+ };
+ spi-nand@1 {
+ compatible = "spi-nand";
+ reg = <1>;
+ spi-max-frequency = <20000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ status = "disabled";
+ };
+ };
+
+ ethmac: ethernet@ff3f0000 {
+ compatible = "amlogic,g12a-eth-dwmac";
+ phy_cntl1 = <0x41054147>;
+ pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>;
+ analog_val = <0x20200000 0x0000c000 0x00000023>;
+ status = "disabled";
+ };
+
+ saradc: adc@fe026000 {
+ compatible = "amlogic,meson-saradc";
+ reg = <0x0 0xfe026000 0x0 0x48>;
+ status = "disabled";
+ };
+
+ nand: nfc@fe08c800 {
+ compatible = "amlogic,meson-nfc";
+ reg = <0x0 0xfe08c800 0x0 0x200>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ clk_reg = <0 0xfe08c000>;
+ };
+
+ apb: apb@fe000000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xfe000000 0x0 0x1000000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
+
+ watchdog@2100 {
+ compatible = "amlogic,meson-sc2-wdt";
+ reg = <0x0 0x2100 0x0 0x10>;
+ clocks = <&xtal>;
+ clock-names = "wdt-clk";
+ };
+
+ sd_emmc_a: sdio {
+ compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
+ reg = <0x0 0x88000 0x0 0x800>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ pinname = "sdio";
+ };
+
+ sd_emmc_b: sd {
+ compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
+ reg = <0x0 0x8a000 0x0 0x800>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ pinname = "sd";
+ };
+
+ sd_emmc_c: emmc {
+ compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
+ reg = <0x0 0x8c000 0x0 0x800>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ pinname = "emmc";
+ };
+ };
+
+ crg: crg@fde00000 {
+ compatible = "crg-xhci";
+ status = "disable";
+ reg = <0x0 0xfde00000 0x0 0x100000>;
+ phys = <&usb2_phy_v2>, <&usb3_phy_v2>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ usb2_phy_v2: usb2phy@fe03a000 {
+ compatible = "amlogic, amlogic-new-usb2-v2";
+ status = "disable";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ phy-version = <2>;
+ reg = <0x0 0xfe03a000 0x0 0x80
+ 0x0 0xFE002000 0x0 0x100
+ 0x0 0xfe03c000 0x0 0x2000
+ 0x0 0xfe03e000 0x0 0x2000>;
+ dwc2_a_reg = <0xfdd00000>;
+ #phy-cells = <0>;
+ };
+
+ usb3_phy_v2: usb3phy@fe03a080 {
+ compatible = "amlogic, amlogic-new-usb3-v2";
+ status = "disable";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ phy-version = <3>;
+ reg = <0x0 0xfe03a080 0x0 0x20>;
+ phy-reg = <0xfe03c000>;
+ phy-reg-size = <0x2000>;
+ usb2-phy-reg = <0xfe03a000>;
+ usb2-phy-reg-size = <0x80>;
+ #phy-cells = <0>;
+ };
+ };
+};
diff --git a/arch/arm/dts/meson-s4-t211.dts b/arch/arm/dts/meson-s4-t211.dts
new file mode 100644
index 0000000..9c8ec03
--- /dev/null
+++ b/arch/arm/dts/meson-s4-t211.dts
@@ -0,0 +1,130 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/usb/pd.h>
+#include "meson-s4-t211.dtsi"
+#include "meson-s4_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,s4-t211", "amlogic,s4-txxx", "amlogic,meson-s4";
+ model = "Amlogic Meson S4 T211 Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "disabled";
+};
+
+&saradc {
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+ pinctrl-names="default";
+ pinctrl-0=<&i2c0_pins1>;
+ clock-frequency = <100000>;
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&i2c4 {
+ status = "okay";
+ pinctrl-names="default";
+ pinctrl-0=<&i2c4_pins2>;
+ clock-frequency = <100000>;
+ rt1711h@4e {
+ compatible = "richtek,rt1711h";
+ reg = <0x4e>;
+ label = "rt1711h";
+ gpios = <&gpio GPIOC_7 GPIO_ACTIVE_LOW>;
+
+ usb_con: connector {
+ compatible = "usb-c-connector";
+ label = "USB-C";
+ power-role = "sink";
+ data-role = "dual";
+ /* Only support one sink-pdo instead of many */
+ sink-pdo = <PDO_FIXED(5000, 900, PDO_FIXED_USB_COMM)>;
+ op-sink-microwatt = <4500000>;
+ no-vconn;
+
+ ports {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ port@1 {
+ reg = <1>;
+ };
+ };
+
+ };
+ };
+};
+
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
+
+&fb {
+ logo_addr = "0x3f800000";
+};
diff --git a/arch/arm/dts/meson-s4-t211.dtsi b/arch/arm/dts/meson-s4-t211.dtsi
new file mode 100644
index 0000000..1f45d80
--- /dev/null
+++ b/arch/arm/dts/meson-s4-t211.dtsi
@@ -0,0 +1,255 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-s4-txxx.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_a;
+ serial1 = &uart_b;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ };
+
+ chosen {
+ stdout-path = "serial1:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ tee: tee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+
+ amhdmitx {
+ compatible = "amlogic, amhdmitx-s4";
+ status = "okay";
+ res_1080p = <1>;
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "disabled";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ sd_hs_co_phase = <2>;
+ sd_hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&crg {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <2>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOH_6";
+ gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_b {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "disabled";
+ //cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>;
+ spi-flash@0 {
+ status = "disabled";
+ };
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins1>;
+ //cs-gpios = <&gpio GPIOA_8 0>,
+ // <&gpio GPIOA_9 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins1>;
+ //cs-gpios = <&gpio GPIOA_14 0>;
+};
diff --git a/arch/arm/dts/meson-s4-txxx.dtsi b/arch/arm/dts/meson-s4-txxx.dtsi
new file mode 100644
index 0000000..81d562d
--- /dev/null
+++ b/arch/arm/dts/meson-s4-txxx.dtsi
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "meson-s4.dtsi"
+#include "meson-s4-mali.dtsi"
+
+/ {
+ compatible = "amlogic,txxx", "amlogic,meson-s4";
+};
+
+ðmac {
+ phy-mode = "rmii";
+ phy-handle = <&internal_phy>;
+};
diff --git a/arch/arm/dts/meson-s4.dtsi b/arch/arm/dts/meson-s4.dtsi
new file mode 100644
index 0000000..a7d1644
--- /dev/null
+++ b/arch/arm/dts/meson-s4.dtsi
@@ -0,0 +1,715 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "meson-s4-series.dtsi"
+#include <dt-bindings/gpio/meson-s4-gpio.h>
+#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pwm/meson.h>
+
+/ {
+ compatible = "amlogic,meson-s4";
+
+ vpu: vpu {
+ compatible = "amlogic, vpu-s4";
+ status = "okay";
+ /*clocks = <&clkc CLKID_VAPB_MUX>,
+ * <&clkc CLKID_VPU_INTR>,
+ * <&clkc CLKID_VPU_P0_COMP>,
+ * <&clkc CLKID_VPU_P1_COMP>,
+ * <&clkc CLKID_VPU_MUX>;
+ *clock-names = "vapb_clk",
+ * "vpu_intr_gate",
+ * "vpu_clk0",
+ * "vpu_clk1",
+ * "vpu_clk";
+ */
+ clk_level = <7>;
+ /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
+ /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */
+ };
+
+ fb: fb {
+ status = "okay";
+ logo_addr = "0x5f800000";
+ };
+
+ pinctrl_periphs: pinctrl@fe004000 {
+ compatible = "amlogic,meson-s4-periphs-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio: bank@fe004000 {
+ reg = <0x0 0xfe004000 0x0 0x0064>,
+ <0x0 0xfe0040c0 0x0 0x0220>;
+ reg-names = "mux",
+ "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_periphs 0 0 82>;
+ };
+ };
+
+ i2c_gpio_0: i2c-gpio-0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "i2c-gpio";
+ status = "okay";
+ gpios = <&gpio GPIOH_0 GPIO_ACTIVE_HIGH>, /* SDA */
+ <&gpio GPIOH_1 GPIO_ACTIVE_HIGH>; /* CLK */
+
+ i2c-gpio,delay-us = <5>;
+ is_odpin = <1>;
+ };
+
+ pwm_ab: pwm@fe058000 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0xfe058000 0x0 0x20>,
+ <0x0 0xfe000180 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_cd: pwm@fe05a000 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0xfe05a000 0x0 0x20>,
+ <0x0 0xfe000184 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_ef: pwm@fe05c000 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0xfe05c000 0x0 0x20>,
+ <0x0 0xfe000188 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_gh: pwm@fe05e000 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0xfe05e000 0x0 0x20>,
+ <0x0 0xfe00018c 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_ij: pwm@fe060000 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0xfe060000 0x0 0x20>,
+ <0x0 0xfe000190 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+};
+
+ðmac {
+ compatible = "amlogic,g12a-eth-dwmac";
+ reg = <0x0 0xfdc00000 0x0 0x10000
+ 0x0 0xFE024000 0x0 0x8
+ 0x0 0xFE028000 0x0 0xa0>;
+ reg-names = "eth_base", "eth_top", "eth_cfg";
+ phy_cntl1 = <0x41054147>;
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>;
+ analog_val = <0x20200000 0x0000c000 0x00000023>;
+ chip_num = <3>;
+ //tx_amp_src = <0xfe005b30>;
+// clocks = <&clkc CLKID_ETH_CORE>,
+// <&clkc CLKID_FCLK_DIV2>,
+// <&clkc CLKID_MPLL2>;
+// clock-names = "stmmaceth", "clkin0", "clkin1";
+
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+};
+
+&periphs {
+
+ eth-phy-mux {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x15c 0x0 0x4>;
+ mux-mask = <0xffffffff>;
+ mdio-parent-bus = <&mdio0>;
+
+ internal_mdio: mdio@e40908ff {
+ reg = <0xe40908ff>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ internal_phy: ethernet-phy@8 {
+ compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
+ reg = <8>;
+ max-speed = <100>;
+ };
+ };
+
+ external_mdio: mdio@2009087f {
+ reg = <0x2009087f>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&saradc {
+ compatible = "amlogic,meson-g12a-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SARADC_MUX>,
+ <&clkc CLKID_SARADC_DIV>,
+ <&clkc CLKID_SAR_ADC_GATE>;
+ clock-names = "xtal", "adc_mux", "adc_div", "adc_gate";
+};
+
+&sd_emmc_a {
+ clocks = <&clkc CLKID_SD_EMMC_A_MUX>,
+ <&clkc CLKID_SD_EMMC_A_DIV>,
+ <&clkc CLKID_SD_EMMC_A_GATE>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_XTAL>;
+ clock-names = "mux", "div", "gate", "clkin", "xtal";
+};
+
+&sd_emmc_b {
+ clocks = <&clkc CLKID_SD_EMMC_B_MUX>,
+ <&clkc CLKID_SD_EMMC_B_DIV>,
+ <&clkc CLKID_SD_EMMC_B_GATE>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_XTAL>;
+ clock-names = "mux", "div", "gate", "clkin", "xtal";
+};
+
+&sd_emmc_c {
+ clocks = <&clkc CLKID_SD_EMMC_C_MUX>,
+ <&clkc CLKID_SD_EMMC_C_DIV>,
+ <&clkc CLKID_SD_EMMC_C_GATE>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_XTAL>;
+ clock-names = "mux", "div", "gate", "clkin", "xtal";
+};
+
+&nand {
+ clocks = <&clkc CLKID_SD_EMMC_C_MUX>,
+ <&clkc CLKID_SD_EMMC_C_DIV>,
+ <&clkc CLKID_SD_EMMC_C_GATE>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_XTAL>;
+ clock-names = "mux", "div", "gate", "fdiv2", "xtal";
+};
+
+/*
+&spicc0 {
+ clocks = <&clkc CLKID_SPICC0>,
+ <&clkc CLKID_SPICC0_COMP>;
+ clock-names = "core", "comp";
+};
+
+&spicc1 {
+ clocks = <&clkc CLKID_SPICC1>,
+ <&clkc CLKID_SPICC1_COMP>;
+ clock-names = "core", "comp";
+ };
+*/
+&pinctrl_periphs {
+ i2c0_pins1:i2c0_pins1 {
+ mux {
+ groups = "i2c0_sda",
+ "i2c0_scl";
+ function = "i2c0";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins1:i2c1_pins1 {
+ mux {
+ groups = "i2c1_sda_c",
+ "i2c1_scl_c";
+ function = "i2c1";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins2:i2c1_pins2 {
+ mux {
+ groups = "i2c1_sda_d",
+ "i2c1_scl_d";
+ function = "i2c1";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins3:i2c1_pins3 {
+ mux {
+ groups = "i2c1_sda_h",
+ "i2c1_scl_h";
+ function = "i2c1";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins4:i2c1_pins4 {
+ mux {
+ groups = "i2c1_sda_x",
+ "i2c1_scl_x";
+ function = "i2c1";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c2_pins1:i2c2_pins1 {
+ mux {
+ groups = "i2c2_sda_d",
+ "i2c2_scl_d";
+ function = "i2c2";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c2_pins2:i2c2_pins2 {
+ mux {
+ groups = "i2c2_sda_h8",
+ "i2c2_scl_h9";
+ function = "i2c2";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c2_pins3:i2c2_pins3 {
+ mux {
+ groups = "i2c2_sda_h0",
+ "i2c2_scl_h1";
+ function = "i2c2";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c3_pins1:i2c3_pins1 {
+ mux {
+ groups = "i2c3_sda_x",
+ "i2c3_scl_x";
+ function = "i2c3";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c3_pins2:i2c3_pins2 {
+ mux {
+ groups = "i2c3_sda_z",
+ "i2c3_scl_z";
+ function = "i2c3";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c4_pins1:i2c4_pins1 {
+ mux {
+ groups = "i2c4_sda_c",
+ "i2c4_scl_c";
+ function = "i2c4";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c4_pins2:i2c4_pins2 {
+ mux {
+ groups = "i2c4_sda_d",
+ "i2c4_scl_d";
+ function = "i2c4";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c4_pins3:i2c4_pins3 {
+ mux {
+ groups = "i2c4_sda_z",
+ "i2c4_scl_z";
+ function = "i2c4";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ jtag_a_pins:jtag_a_pin {
+ mux {
+ groups = "jtag_1_clk",
+ "jtag_1_tms",
+ "jtag_1_tdi",
+ "jtag_1_tdo";
+ function = "jtag_1";
+ };
+ };
+
+ jtag_b_pins:jtag_b_pin {
+ mux {
+ groups = "jtag_2_clk",
+ "jtag_2_tms",
+ "jtag_2_tdi",
+ "jtag_2_tdo";
+ function = "jtag_2";
+ };
+ };
+
+ swd_a_pins:swd_a_pin {
+ mux {
+ groups = "swclk",
+ "swdio";
+ function = "sw";
+ };
+ };
+
+ emmc_pins: emmc {
+ mux {
+ groups = "emmc_nand_d0",
+ "emmc_nand_d1",
+ "emmc_nand_d2",
+ "emmc_nand_d3",
+ "emmc_nand_d4",
+ "emmc_nand_d5",
+ "emmc_nand_d6",
+ "emmc_nand_d7",
+ "emmc_clk",
+ "emmc_cmd";
+ function = "emmc";
+ bias-pull-up;
+ input-enable;
+ };
+ mux1 {
+ groups = "emmc_nand_ds";
+ function = "emmc";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ emmc_clk_gate_pins: emmc_clk_gate {
+ mux {
+ groups = "emmc_clk";
+ function = "emmc";
+ bias-pull-down;
+ };
+ };
+
+ all_nand_pins: all_nand_pins {
+ mux {
+ groups = "emmc_nand_d0",
+ "emmc_nand_d1",
+ "emmc_nand_d2",
+ "emmc_nand_d3",
+ "emmc_nand_d4",
+ "emmc_nand_d5",
+ "emmc_nand_d6",
+ "emmc_nand_d7",
+ "nand_ce0",
+ "nand_ale",
+ "nand_cle",
+ "nand_wen_clk",
+ "nand_ren_wr";
+ function = "nand";
+ input-enable;
+ };
+ };
+
+ nand_cs_pins: nand_cs {
+ mux {
+ groups = "nand_ce0";
+ function = "nand";
+ };
+ };
+
+ sdcard_pins: sdcard {
+ mux {
+ groups = "sdcard_d0_c",
+ "sdcard_d1_c",
+ "sdcard_d2_c",
+ "sdcard_d3_c",
+ "sdcard_cmd_c";
+ function = "sdcard";
+ bias-pull-up;
+ input-enable;
+ drive-strength = <4>;
+ };
+ mux1 {
+ groups ="sdcard_clk_c";
+ function = "sdcard";
+ bias-pull-up;
+ output-high;
+ drive-strength = <4>;
+ };
+ };
+
+ sdcard_clk_gate_pins: sdcard_clk_gate {
+ mux {
+ groups = "sdcard_clk_c";
+ function = "sdcard";
+ bias-pull-down;
+ };
+ };
+
+ to_sduart_pins: to_sduart_pins{
+ mux {
+ groups = "uart_b_rx_c", "uart_b_tx_c";
+ function = "uart_b";
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
+ sd_to_uart_pins: sd_to_uart_pins{
+ mux {
+ groups = "uart_b_rx_d", "uart_b_tx_d";
+ function = "uart_b";
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
+ spicc0_pins1: spicc0_pins1 {
+ mux {
+ groups = "spi_a_mosi_a",
+ "spi_a_miso_a",
+ "spi_a_sclk_a";
+ function = "spi_a";
+ drive-strength = <2>;
+ };
+ };
+
+ spicc0_pins2: spicc0_pins2 {
+ mux {
+ groups = "spi_a_mosi_c",
+ "spi_a_miso_c",
+ "spi_a_sclk_c";
+ function = "spi_a";
+ drive-strength = <2>;
+ };
+ };
+
+ spicc1_pins1: spicc1_pins1 {
+ mux {
+ groups = "spi_b_mosi_a",
+ "spi_b_miso_a",
+ "spi_b_sclk_a";
+ function = "spi_b";
+ drive-strength = <2>;
+ };
+ };
+
+ spifc_pins: spifc_pins {
+ mux {
+ groups = "spif_hold",
+ "spif_mo",
+ "spif_mi",
+ //"spif_cs",
+ "spif_clk",
+ "spif_wp";
+ function = "spif";
+ drive-strength = <3>;
+ };
+ };
+
+ pwm_a_pins: pwm_a_pins {
+ mux {
+ groups = "pwm_a_d";
+ function = "pwm_a";
+ };
+ };
+
+ pwm_b_pins1: pwm_b_pins1 {
+ mux {
+ groups = "pwm_b_d";
+ function = "pwm_b";
+ };
+ };
+
+ pwm_b_pins2: pwm_b_pins2 {
+ mux {
+ groups = "pwm_b_x";
+ function = "pwm_b";
+ };
+ };
+
+ pwm_c_pins1: pwm_c_pins1 {
+ mux {
+ groups = "pwm_c_d";
+ function = "pwm_c";
+ };
+ };
+
+ pwm_c_pins2: pwm_c_pins2 {
+ mux {
+ groups = "pwm_c_x";
+ function = "pwm_c";
+ };
+ };
+
+ pwm_d_pins1: pwm_d_pins1 {
+ mux {
+ groups = "pwm_d_d";
+ function = "pwm_d";
+ };
+ };
+
+ pwm_d_pins2: pwm_d_pins2 {
+ mux {
+ groups = "pwm_d_h";
+ function = "pwm_d";
+ };
+ };
+
+ pwm_e_pins1: pwm_e_pins1 {
+ mux {
+ groups = "pwm_e_x";
+ function = "pwm_e";
+ };
+ };
+
+ pwm_e_pins2: pwm_e_pins2 {
+ mux {
+ groups = "pwm_e_z";
+ function = "pwm_e";
+ };
+ };
+
+ pwm_f_pins1: pwm_f_pins1 {
+ mux {
+ groups = "pwm_f_x";
+ function = "pwm_f";
+ };
+ };
+
+ pwm_f_pins2: pwm_f_pins2 {
+ mux {
+ groups = "pwm_f_z";
+ function = "pwm_f";
+ };
+ };
+
+ pwm_g_pins1: pwm_g_pins1 {
+ mux {
+ groups = "pwm_g_d";
+ function = "pwm_g";
+ };
+ };
+
+ pwm_g_pins2: pwm_g_pins2 {
+ mux {
+ groups = "pwm_g_z";
+ function = "pwm_g";
+ };
+ };
+
+ pwm_h_pins: pwm_h_pins {
+ mux {
+ groups = "pwm_h";
+ function = "pwm_h";
+ };
+ };
+
+ pwm_i_pins1: pwm_i_pins1 {
+ mux {
+ groups = "pwm_i_d";
+ function = "pwm_i";
+ };
+ };
+
+ pwm_i_pins2: pwm_i_pins2 {
+ mux {
+ groups = "pwm_i_h";
+ function = "pwm_i";
+ };
+ };
+
+ pwm_j_pins: pwm_j_pins {
+ mux {
+ groups = "pwm_j";
+ function = "pwm_j";
+ };
+ };
+
+ pwm_a_hiz_pins: pwm_a_hiz_pins {
+ mux {
+ groups = "pwm_a_hiz";
+ function = "pwm_a_hiz";
+ };
+ };
+
+ pwm_b_hiz_pins: pwm_b_hiz_pins {
+ mux {
+ groups = "pwm_b_hiz";
+ function = "pwm_b_hiz";
+ };
+ };
+
+ pwm_c_hiz_pins: pwm_c_hiz_pins {
+ mux {
+ groups = "pwm_c_hiz";
+ function = "pwm_b_hiz";
+ };
+ };
+
+ pwm_g_hiz_pins: pwm_g_hiz_pins {
+ mux {
+ groups = "pwm_g_hiz";
+ function = "pwm_g_hiz";
+ };
+ };
+};
diff --git a/arch/arm/dts/meson-s4_skt-panel.dtsi b/arch/arm/dts/meson-s4_skt-panel.dtsi
new file mode 100644
index 0000000..fbb676c
--- /dev/null
+++ b/arch/arm/dts/meson-s4_skt-panel.dtsi
@@ -0,0 +1,742 @@
+/*
+ * arch/arm64/boot/dts/amlogic/mesong12a_skt-panel.dtsi
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+/ {
+ lcd{
+ compatible = "amlogic, lcd-g12a";
+ mode = "tablet";
+ status = "okay";
+ key_valid = <0>;
+ /*
+ clocks = <&clkc CLKID_MIPI_DSI_HOST
+ &clkc CLKID_MIPI_DSI_PHY
+ &clkc CLKID_DSI_MEAS_COMP
+ &clkc CLKID_VCLK2_ENCL
+ &clkc CLKID_VCLK2_VENCL
+ &clkc CLKID_GP0_PLL>;
+ clock-names = "dsi_host_gate",
+ "dsi_phy_gate",
+ "dsi_meas",
+ "encl_top_gate",
+ "encl_int_gate",
+ "gp0_pll";
+ */
+ reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */
+ 0x0 0xff644000 0x0 0x200>; /* dsi_phy */
+ interrupts = <0 3 1
+ 0 56 1>;
+ interrupt-names = "vsync","vsync2";
+ pinctrl_version = <2>; /* for uboot */
+
+ /* power type:
+ * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending)
+ * power index:
+ * (point gpios_index, or extern_index,0xff=invalid)
+ * power value:(0=output low, 1=output high, 2=input)
+ * power delay:(unit in ms)
+ */
+
+ /*lcd_cpu-gpios = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH
+ &gpio GPIOZ_8 GPIO_ACTIVE_HIGH>;
+ */
+ lcd_cpu_gpio_names = "GPIOZ_9","GPIOZ_8";
+
+ lcd_0{
+ model_name = "B080XAN01";
+ interface = "mipi";
+ basic_setting = <768 1024 /*h_active, v_active*/
+ 948 1140 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 119 159>; /*screen_widht, screen_height*/
+ lcd_timing = <64 56 0 /*hs_width, hs_bp, hs_pol*/
+ 50 30 0>; /*vs_width, vs_bp, vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/
+ 0 /*clk_ss_level */
+ 1 /*clk_auto_generate*/
+ 64843200>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 550 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 1 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <0x05 1 0x11
+ 0xfd 1 20 /*delay(ms)*/
+ 0x05 1 0x29
+ 0xfd 1 20 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ dsi_init_off = <0x05 1 0x28
+ 0xfd 1 10 /*delay(ms)*/
+ 0x05 1 0x10
+ 0xfd 1 10 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ extern_init = <0xff>; /*0xff for invalid*/
+
+ /* power step: type, index, value, delay(ms) */
+ power_on_step = <
+ 0 1 0 100
+ 0 0 0 10
+ 0 0 1 20
+ 2 0 0 0
+ 0xff 0 0 0>; /*ending*/
+ power_off_step = <
+ 2 0 0 50
+ 0 0 0 10
+ 0 1 1 100
+ 0xff 0 0 0>; /*ending*/
+ backlight_index = <0>;
+ };
+
+ lcd_1{
+ model_name = "P070ACB_FT";
+ interface = "mipi";
+ basic_setting = <600 1024 /*h_active, v_active*/
+ 770 1070 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 3 5>; /*screen_widht, screen_height*/
+ lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/
+ 6 20 0>; /*vs_width,vs_bp,vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
+ 0 /*clk_ss_level*/
+ 1 /*clk_auto_generate*/
+ 49434000>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 400 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 0 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <
+ 0xff 10
+ 0xf0 3 0 1 30 /* reset high, delay 30ms */
+ 0xf0 3 0 0 10 /* reset low, delay 10ms */
+ 0xf0 3 0 1 30 /* reset high, delay 30ms */
+ 0xfc 2 0x04 3 /* check_reg, check_cnt */
+ 0xff 0>; /* ending flag */
+ dsi_init_off = <0xff 0>; /* ending flag */
+ /* extern_init: 0xff for invalid */
+ extern_init = <2>;
+ /* power step: type,index,value,delay(ms) */
+ power_on_step = <
+ 0 1 0 200 /* panel power on */
+ 2 0 0 0
+ 0xff 0 0 0>;
+ power_off_step = <
+ 2 0 0 0
+ 0 0 0 20 /* reset low */
+ 0 1 1 100 /* panel power off */
+ 0xff 0 0 0>;
+ backlight_index = <0>;
+ };
+
+ lcd_3{
+ model_name = "TL050FHV02CT";
+ interface = "mipi";
+ basic_setting = <1080 1920 /*h_active, v_active*/
+ 1125 2100 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 65 119>; /*screen_widht, screen_height*/
+ lcd_timing = <5 30 0 /*hs_width,hs_bp,hs_pol*/
+ 44 108 0>; /*vs_width,vs_bp,vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
+ 0 /*clk_ss_level*/
+ 1 /*clk_auto_generate*/
+ 118125000>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 960 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 1 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <0xff 0>; /* ending flag */
+ dsi_init_off = <0xff 0>; /* ending flag */
+ /* extern_init: 0xff for invalid */
+ extern_init = <3>;
+ /* power step: type,index,value,delay(ms) */
+ power_on_step = <
+ 0 1 0 200
+ 0 0 1 20
+ 0 0 0 10
+ 0 0 1 20
+ 2 0 0 0
+ 0xff 0 0 0>;
+ power_off_step = <
+ 2 0 0 0
+ 0 0 0 20
+ 0 1 1 100
+ 0xff 0 0 0>;
+ backlight_index = <0>;
+ };
+
+ lcd_4{
+ model_name = "TL070WSH27";
+ interface = "mipi";
+ basic_setting = <1024 600 /*h_active, v_active*/
+ 1250 630 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 154 86>; /*screen_widht, screen_height*/
+ lcd_timing = <80 100 0 /*hs_width, hs_bp, hs_pol*/
+ 5 20 0>; /*vs_width, vs_bp, vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/
+ 0 /*clk_ss_level */
+ 1 /*clk_auto_generate*/
+ 47250000>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 300 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 1 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <0x05 1 0x11
+ 0xfd 1 20 /*delay(ms)*/
+ 0x05 1 0x29
+ 0xfd 1 20 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ dsi_init_off = <0x05 1 0x28
+ 0xfd 1 10 /*delay(ms)*/
+ 0x05 1 0x10
+ 0xfd 1 10 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ extern_init = <0xff>; /*0xff for invalid*/
+
+ /* power step: type, index, value, delay(ms) */
+ power_on_step = <
+ 0 1 0 100
+ 0 0 0 10
+ 0 0 1 20
+ 2 0 0 0
+ 0xff 0 0 0>; /*ending*/
+ power_off_step = <
+ 2 0 0 50
+ 0 0 0 10
+ 0 1 1 100
+ 0xff 0 0 0>; /*ending*/
+ backlight_index = <0>;
+ };
+ };
+
+ lcd_extern{
+ compatible = "amlogic, lcd_extern";
+ status = "okay";
+ i2c_bus = "i2c_bus_0";
+ key_valid = <0>;
+
+ extern_0{
+ index = <0>;
+ extern_name = "mipi_default";/*default*/
+ status = "okay";
+ type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+ cmd_size = <0xff>;
+ init_on = <
+ 0xfd 1 10
+ 0x05 1 0x11
+ 0xfd 1 120 /* delay 120ms */
+ 0x05 1 0x29
+ 0xff 0>; /*ending*/
+ init_off = <
+ 0x05 1 0x28 /* display off */
+ 0xfd 1 10 /* delay 10ms */
+ 0x05 1 0x10 /* sleep in */
+ 0xfd 1 150 /* delay 150ms */
+ 0xff 0>; /*ending*/
+ };
+
+ extern_2{
+ index = <2>;
+ extern_name = "mipi_default";/*P070ACB_FT*/
+ status = "okay";
+ type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+ cmd_size = <0xff>;
+ init_on = <
+ 0x23 2 0xE0 0x00 /* Page 0 */
+ 0x23 2 0xE1 0x93 /* PASSWORD */
+ 0x23 2 0xE2 0x65
+ 0x23 2 0xE3 0xF8
+ 0x23 2 0x80 0x03
+ 0x23 2 0xE0 0x01 /* Page 01 */
+ 0x23 2 0x0C 0x74 /* Set PWRIC */
+ 0x23 2 0x17 0x00 /* Set Gamma Power */
+ 0x23 2 0x18 0xEF /* VGMP=5.1V */
+ 0x23 2 0x19 0x00
+ 0x23 2 0x1A 0x00
+ 0x23 2 0x1B 0xEF /* VGMN=-5.1V */
+ 0x23 2 0x1C 0x00
+ 0x23 2 0x1F 0x70 /* Set Gate Power */
+ 0x23 2 0x20 0x2D
+ 0x23 2 0x21 0x2D
+ 0x23 2 0x22 0x7E
+ 0x23 2 0x26 0xF3 /* VDDD from IOVCC */
+ 0x23 2 0x37 0x09 /* SetPanel */
+ 0x23 2 0x38 0x04 /* SET RGBCYC */
+ 0x23 2 0x39 0x00
+ 0x23 2 0x3A 0x01
+ 0x23 2 0x3C 0x90
+ 0x23 2 0x3D 0xFF
+ 0x23 2 0x3E 0xFF
+ 0x23 2 0x3F 0xFF
+ 0x23 2 0x40 0x02 /* Set TCON */
+ 0x23 2 0x41 0x80
+ 0x23 2 0x42 0x99
+ 0x23 2 0x43 0x14
+ 0x23 2 0x44 0x19
+ 0x23 2 0x45 0x5A
+ 0x23 2 0x4B 0x04
+ 0x23 2 0x55 0x02 /* power voltage */
+ 0x23 2 0x56 0x01
+ 0x23 2 0x57 0x69
+ 0x23 2 0x58 0x0A
+ 0x23 2 0x59 0x0A
+ 0x23 2 0x5A 0x2E /* VGH = 16.2V */
+ 0x23 2 0x5B 0x19 /* VGL = -12V */
+ 0x23 2 0x5C 0x15
+ 0x23 2 0x5D 0x77 /* Gamma */
+ 0x23 2 0x5E 0x56
+ 0x23 2 0x5F 0x45
+ 0x23 2 0x60 0x38
+ 0x23 2 0x61 0x35
+ 0x23 2 0x62 0x27
+ 0x23 2 0x63 0x2D
+ 0x23 2 0x64 0x18
+ 0x23 2 0x65 0x33
+ 0x23 2 0x66 0x34
+ 0x23 2 0x67 0x35
+ 0x23 2 0x68 0x56
+ 0x23 2 0x69 0x45
+ 0x23 2 0x6A 0x4F
+ 0x23 2 0x6B 0x42
+ 0x23 2 0x6C 0x40
+ 0x23 2 0x6D 0x34
+ 0x23 2 0x6E 0x25
+ 0x23 2 0x6F 0x02
+ 0x23 2 0x70 0x77
+ 0x23 2 0x71 0x56
+ 0x23 2 0x72 0x45
+ 0x23 2 0x73 0x38
+ 0x23 2 0x74 0x35
+ 0x23 2 0x75 0x27
+ 0x23 2 0x76 0x2D
+ 0x23 2 0x77 0x18
+ 0x23 2 0x78 0x33
+ 0x23 2 0x79 0x34
+ 0x23 2 0x7A 0x35
+ 0x23 2 0x7B 0x56
+ 0x23 2 0x7C 0x45
+ 0x23 2 0x7D 0x4F
+ 0x23 2 0x7E 0x42
+ 0x23 2 0x7F 0x40
+ 0x23 2 0x80 0x34
+ 0x23 2 0x81 0x25
+ 0x23 2 0x82 0x02
+ 0x23 2 0xE0 0x02 /* Page2 */
+ 0x23 2 0x00 0x53
+ /* GIP_L Pin mapping RESET_EVEN */
+ 0x23 2 0x01 0x55 /* VSSG_EVEN */
+ 0x23 2 0x02 0x55 /* VSSA_EVEN */
+ 0x23 2 0x03 0x51 /* STV2_EVEN */
+ 0x23 2 0x04 0x77 /* VDD2_EVEN */
+ 0x23 2 0x05 0x57 /* VDD1_EVEN */
+ 0x23 2 0x06 0x1F
+ 0x23 2 0x07 0x4F /* CK12 */
+ 0x23 2 0x08 0x4D /* CK10 */
+ 0x23 2 0x09 0x1F
+ 0x23 2 0x0A 0x4B /* CK8 */
+ 0x23 2 0x0B 0x49 /* CK6 */
+ 0x23 2 0x0C 0x1F
+ 0x23 2 0x0D 0x47 /* CK4 */
+ 0x23 2 0x0E 0x45 /* CK2 */
+ 0x23 2 0x0F 0x41 /* STV1_EVEN */
+ 0x23 2 0x10 0x1F
+ 0x23 2 0x11 0x1F
+ 0x23 2 0x12 0x1F
+ 0x23 2 0x13 0x55 /* VGG */
+ 0x23 2 0x14 0x1F
+ 0x23 2 0x15 0x1F
+ 0x23 2 0x16 0x52
+ /* GIP_R Pin mapping RESET_ODD */
+ 0x23 2 0x17 0x55 /* VSSG_ODD */
+ 0x23 2 0x18 0x55 /* VSSA_ODD */
+ 0x23 2 0x19 0x50 /* STV2_ODD */
+ 0x23 2 0x1A 0x77 /* VDD2_ODD */
+ 0x23 2 0x1B 0x57 /* VDD1_ODD */
+ 0x23 2 0x1C 0x1F
+ 0x23 2 0x1D 0x4E /* CK11 */
+ 0x23 2 0x1E 0x4C /* CK9 */
+ 0x23 2 0x1F 0x1F
+ 0x23 2 0x20 0x4A /* CK7 */
+ 0x23 2 0x21 0x48 /* CK5 */
+ 0x23 2 0x22 0x1F
+ 0x23 2 0x23 0x46 /* CK3 */
+ 0x23 2 0x24 0x44 /* CK1 */
+ 0x23 2 0x25 0x40 /* STV1_ODD */
+ 0x23 2 0x26 0x1F
+ 0x23 2 0x27 0x1F
+ 0x23 2 0x28 0x1F
+ 0x23 2 0x29 0x1F
+ 0x23 2 0x2A 0x1F
+ 0x23 2 0x2B 0x55 /* VGG */
+ 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping */
+ 0x23 2 0x2D 0x15
+ 0x23 2 0x2E 0x15
+ 0x23 2 0x2F 0x00
+ 0x23 2 0x30 0x37
+ 0x23 2 0x31 0x17
+ 0x23 2 0x32 0x1F
+ 0x23 2 0x33 0x08
+ 0x23 2 0x34 0x0A
+ 0x23 2 0x35 0x1F
+ 0x23 2 0x36 0x0C
+ 0x23 2 0x37 0x0E
+ 0x23 2 0x38 0x1F
+ 0x23 2 0x39 0x04
+ 0x23 2 0x3A 0x06
+ 0x23 2 0x3B 0x10
+ 0x23 2 0x3C 0x1F
+ 0x23 2 0x3D 0x1F
+ 0x23 2 0x3E 0x1F
+ 0x23 2 0x3F 0x15
+ 0x23 2 0x40 0x1F
+ 0x23 2 0x41 0x1F
+ 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping */
+ 0x23 2 0x43 0x15
+ 0x23 2 0x44 0x15
+ 0x23 2 0x45 0x01
+ 0x23 2 0x46 0x37
+ 0x23 2 0x47 0x17
+ 0x23 2 0x48 0x1F
+ 0x23 2 0x49 0x09
+ 0x23 2 0x4A 0x0B
+ 0x23 2 0x4B 0x1F
+ 0x23 2 0x4C 0x0D
+ 0x23 2 0x4D 0x0F
+ 0x23 2 0x4E 0x1F
+ 0x23 2 0x4F 0x05
+ 0x23 2 0x50 0x07
+ 0x23 2 0x51 0x11
+ 0x23 2 0x52 0x1F
+ 0x23 2 0x53 0x1F
+ 0x23 2 0x54 0x1F
+ 0x23 2 0x55 0x1F
+ 0x23 2 0x56 0x1F
+ 0x23 2 0x57 0x15
+ 0x23 2 0x58 0x40 /* GIP Timing */
+ 0x23 2 0x59 0x00
+ 0x23 2 0x5A 0x00
+ 0x23 2 0x5B 0x10
+ 0x23 2 0x5C 0x14
+ 0x23 2 0x5D 0x40
+ 0x23 2 0x5E 0x01
+ 0x23 2 0x5F 0x02
+ 0x23 2 0x60 0x40
+ 0x23 2 0x61 0x03
+ 0x23 2 0x62 0x04
+ 0x23 2 0x63 0x7A
+ 0x23 2 0x64 0x7A
+ 0x23 2 0x65 0x74
+ 0x23 2 0x66 0x16
+ 0x23 2 0x67 0xB4
+ 0x23 2 0x68 0x16
+ 0x23 2 0x69 0x7A
+ 0x23 2 0x6A 0x7A
+ 0x23 2 0x6B 0x0C
+ 0x23 2 0x6C 0x00
+ 0x23 2 0x6D 0x04
+ 0x23 2 0x6E 0x04
+ 0x23 2 0x6F 0x88
+ 0x23 2 0x70 0x00
+ 0x23 2 0x71 0x00
+ 0x23 2 0x72 0x06
+ 0x23 2 0x73 0x7B
+ 0x23 2 0x74 0x00
+ 0x23 2 0x75 0xBC
+ 0x23 2 0x76 0x00
+ 0x23 2 0x77 0x04
+ 0x23 2 0x78 0x2C
+ 0x23 2 0x79 0x00
+ 0x23 2 0x7A 0x00
+ 0x23 2 0x7B 0x00
+ 0x23 2 0x7C 0x00
+ 0x23 2 0x7D 0x03
+ 0x23 2 0x7E 0x7B
+ 0x23 2 0xE0 0x04 /* Page4 */
+ 0x23 2 0x09 0x11 /* Set RGBCYC2 */
+ 0x23 2 0x0E 0x48
+ 0x23 2 0x2B 0x2B /* ESD Protect */
+ 0x23 2 0x2E 0x44
+ 0x23 2 0xE0 0x00 /* Page0 */
+ 0x23 2 0xE6 0x02 /* Watch dog */
+ 0x23 2 0xE7 0x0C
+ 0x05 1 0x11 /* sleep out */
+ 0xfd 1 120
+ 0x05 1 0x29 /* display on */
+ 0x05 1 0x35
+ 0xfd 1 20 /* delay(ms) */
+ 0xFF 0>; /*ending*/
+ init_off = <
+ 0x05 1 0x28 /* display off */
+ 0xfd 1 10 /* delay 10ms */
+ 0x05 1 0x10 /* sleep in */
+ 0xfd 1 150 /* delay 150ms */
+ 0xff 0>; /*ending*/
+ };
+
+ extern_3{
+ index = <3>;
+ extern_name = "mipi_default";/*TL050FHV02CT*/
+ status = "okay";
+ type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+ cmd_size = <0xff>;
+ init_on = <
+ 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03
+ 0x29 10 0x90 0x03 0x14 0x09 0x00 0x00
+ 0x00 0x38 0x00 0x00
+ 0x29 10 0x91 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00
+ 0x29 12 0x92 0x40 0x0B 0x0C 0x0D 0x0E
+ 0x00 0x38 0x00 0x10 0x03 0x04
+ 0x29 9 0x94 0x00 0x08 0x0B 0x03 0xD2
+ 0x03 0xD3 0x0C
+ 0x29 17 0x95 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00
+ 0x29 3 0x99 0x00 0x00
+ 0x29 12 0x9A 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x29 7 0x9B 0x01 0x38 0x00 0x00 0x00 0x00
+ 0x29 3 0x9C 0x00 0x00
+ 0x29 9 0x9D 0x10 0x10 0x10 0x10 0x10
+ 0x10 0x00 0x00
+ 0x29 3 0x9E 0x00 0x00
+ 0x29 11 0xA0 0x9F 0x1F 0x08 0x1F 0x0A
+ 0x1F 0x00 0x1F 0x14 0x1F
+ 0x29 11 0xA1 0x15 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA2 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA4 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA5 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x15
+ 0x29 11 0xA6 0x1F 0x14 0x1F 0x01 0x1F
+ 0x0B 0x1F 0x09 0x1F 0x1F
+ 0x29 11 0xA7 0x1F 0x1F 0x0B 0x1F 0x09
+ 0x1F 0x01 0x1F 0x15 0x1F
+ 0x29 11 0xA8 0x14 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA9 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xAB 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xAC 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x14
+ 0x29 11 0xAD 0x1F 0x15 0x1F 0x00 0x1F
+ 0x08 0x1F 0x0A 0x1F 0x1F
+ 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00
+ 0x29 4 0xBC 0x00 0x00 0x00
+ 0x29 5 0xB8 0x01 0xAF 0x8F 0x8F
+ 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01
+ 0x29 17 0xD1 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xD2 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xD3 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xD4 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xD5 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xD6 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xD7 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xD8 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xD9 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xDD 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xDE 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xDF 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xE0 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xE1 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xE2 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xE3 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xE4 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xE5 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xE6 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xE7 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xE8 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xE9 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xEA 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xEB 0x03 0xC5 0x03 0xFF
+ 0x29 4 0xB0 0x05 0x05 0x05
+ 0x29 4 0xB1 0x05 0x05 0x05
+ 0x29 4 0xB3 0x10 0x10 0x10
+ 0x29 4 0xB4 0x06 0x06 0x06
+ 0x29 4 0xB6 0x44 0x44 0x44
+ 0x29 4 0xB7 0x34 0x34 0x34
+ 0x29 4 0xB8 0x34 0x34 0x34
+ 0x29 4 0xB9 0x24 0x24 0x24
+ 0x29 4 0xBA 0x24 0x24 0x24
+ 0x29 4 0xBC 0x00 0x70 0x00
+ 0x29 4 0xBD 0x00 0x70 0x00
+ 0x23 2 0xBE 0x50
+ 0x23 2 0x35 0x00
+ 0x13 1 0x11
+ 0xfd 1 200
+ 0x13 1 0x29
+ 0xfd 1 200
+ 0xFF 0>; /*ending*/
+ init_off = <
+ 0x05 1 0x28 /* display off */
+ 0xfd 1 10 /* delay 10ms */
+ 0x05 1 0x10 /* sleep in */
+ 0xfd 1 150 /* delay 150ms */
+ 0xff 0>; /*ending*/
+ };
+ };
+
+ backlight{
+ compatible = "amlogic, backlight-g12a";
+ status = "okay";
+ key_valid = <0>;
+ pinctrl-names = "pwm_on","pwm_off";
+ /* pinctrl-0 = <&pwm_f_pins2>; */
+ /* pinctrl-1 = <&bl_pwm_off_pins>; */
+ pinctrl_version = <2>; /* for uboot */
+ bl_pwm_config = <&bl_pwm_conf>;
+ /*bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH
+ &gpio GPIOH_5 GPIO_ACTIVE_HIGH>;*/
+ bl_gpio_names = "GPIOH_4","GPIOH_5";
+
+ /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/
+ /* power index:(point gpios_index, 0xff=invalid)
+ * power value:(0=output low, 1=output high, 2=input)
+ * power delay:(unit in ms)
+ */
+
+ backlight_0{
+ index = <0>;
+ bl_name = "backlight_pwm";
+ bl_level_default_uboot_kernel = <100 100>;
+ bl_level_attr = <255 10 /*max, min*/
+ 128 128>; /*mid, mid_mapping*/
+ bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */
+ bl_power_attr = <0 /*en_gpio_index*/
+ 1 0 /*on_value, off_value*/
+ 200 200>; /*on_delay(ms), off_delay(ms)*/
+ bl_pwm_port = "PWM_F";
+ bl_pwm_attr = <0 /*pwm_method*/
+ 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/
+ 100 25>; /*duty_max(%), duty_min(%)*/
+ bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/
+ 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/
+ bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */
+ };
+ backlight_1{
+ index = <1>;
+ bl_name = "bl_extern";
+ bl_level_default_uboot_kernel = <100 100>;
+ bl_level_attr = <255 10 /*max, min*/
+ 128 128>; /*mid, mid_mapping*/
+ bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/
+ bl_power_attr = <1 /*en_gpio_index*/
+ 1 0 /*on_value, off_value*/
+ 200 200>; /*on_delay(ms), off_delay(ms)*/
+ bl_extern_index = <0>;
+ };
+ };
+ bl_pwm_conf:bl_pwm_conf{
+ pwm_channel_0 {
+ pwm_port_index = <5>;
+ pwms = <&pwm_ef MESON_PWM_1 30040 0>;
+ };
+ };
+
+ bl_extern{
+ compatible = "amlogic, bl_extern";
+ status = "disabled";
+ i2c_bus = "i2c_bus_3";
+
+ extern_0{
+ index = <0>;
+ extern_name = "i2c_lp8556";
+ type = <0>; /*0=i2c, 1=spi, 2=mipi*/
+ i2c_address = <0x2c>; /*7bit i2c address*/
+ dim_max_min = <255 10>;
+ };
+
+ extern_1{
+ index = <1>;
+ extern_name = "mipi_lt070me05";
+ type = <2>; /*0=i2c, 1=spi, 2=mipi*/
+ dim_max_min = <255 10>;
+ };
+ };
+};/* end of panel */
+
diff --git a/arch/arm/dts/meson-sc2-mali.dtsi b/arch/arm/dts/meson-sc2-mali.dtsi
new file mode 100644
index 0000000..2655b42
--- /dev/null
+++ b/arch/arm/dts/meson-sc2-mali.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+&apb {
+ mali: gpu@40000 {
+ compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
+ reg = <0x0 0x40000 0x0 0x40000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp", "gpmmu", "pp", "pmu",
+ "pp0", "ppmmu0", "pp1", "ppmmu1",
+ "pp2", "ppmmu2";
+ /*clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;*/
+ clock-names = "bus", "core";
+
+ /*
+ * Mali clocking is provided by two identical clock paths
+ * MALI_0 and MALI_1 muxed to a single clock by a glitch
+ * free mux to safely change frequency while running.
+ */
+ /*
+ assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+ <&clkc CLKID_MALI_0>,
+ <&clkc CLKID_MALI>; *//* Glitch free mux */
+ /*assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+ <0>, *//* Do Nothing */
+ //<&clkc CLKID_MALI_0>;
+ /*assigned-clock-rates = <0>,*/ /* Do Nothing */
+ /* <666666666>,
+ <0>;*/ /* Do Nothing */
+ };
+};
diff --git a/arch/arm/dts/meson-sc2-pxp.dts b/arch/arm/dts/meson-sc2-pxp.dts
new file mode 100644
index 0000000..657a17e
--- /dev/null
+++ b/arch/arm/dts/meson-sc2-pxp.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-sc2-pxp.dtsi"
+#include "meson-sc2_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,sc2-pxp", "amlogic,s905c2", "amlogic,meson-sc2";
+ model = "Amlogic Meson SC2 PXP Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-sc2-pxp.dtsi b/arch/arm/dts/meson-sc2-pxp.dtsi
new file mode 100644
index 0000000..adcb3ae
--- /dev/null
+++ b/arch/arm/dts/meson-sc2-pxp.dtsi
@@ -0,0 +1,243 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-sc2-s905x4.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_b;
+ serial1 = &uart_a;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ sd_hs_co_phase = <2>;
+ sd_hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+// mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&dwc3 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <2>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOH_6";
+ gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_a {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "disabled";
+ cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>;
+ spi-flash@0 {
+ status = "disabled";
+ };
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins_x>;
+ cs-gpios = <&gpio GPIOX_10 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins_h>;
+ cs-gpios = <&gpio GPIOH_6 0>;
+};
diff --git a/arch/arm/dts/meson-sc2-s905c2-ah232.dts b/arch/arm/dts/meson-sc2-s905c2-ah232.dts
new file mode 100644
index 0000000..f11b5b1
--- /dev/null
+++ b/arch/arm/dts/meson-sc2-s905c2-ah232.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-sc2-s905c2-ah232.dtsi"
+#include "meson-sc2_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,sc2-s905c2-ah232", "amlogic,s905c2", "amlogic,meson-sc2";
+ model = "Amlogic Meson SC2 S905C2 AH232 Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-sc2-s905c2-ah232.dtsi b/arch/arm/dts/meson-sc2-s905c2-ah232.dtsi
new file mode 100644
index 0000000..f99d931
--- /dev/null
+++ b/arch/arm/dts/meson-sc2-s905c2-ah232.dtsi
@@ -0,0 +1,244 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-sc2-s905c2.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_b;
+ serial1 = &uart_a;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c_gpio_0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ tee: tee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ sd_hs_co_phase = <2>;
+ sd_hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <3>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <3>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&dwc3 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <2>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_a {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>;
+ spi-flash@0 {
+ status = "okay";
+ };
+ spi-nand@1 {
+ status = "okay";
+ };
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins_x>;
+ cs-gpios = <&gpio GPIOX_10 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins_h>;
+ cs-gpios = <&gpio GPIOH_6 0>;
+};
diff --git a/arch/arm/dts/meson-sc2-s905c2.dtsi b/arch/arm/dts/meson-sc2-s905c2.dtsi
new file mode 100644
index 0000000..fc192b6
--- /dev/null
+++ b/arch/arm/dts/meson-sc2-s905c2.dtsi
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "meson-sc2.dtsi"
+#include "meson-sc2-mali.dtsi"
+
+/ {
+ compatible = "amlogic,s905c2", "amlogic,meson-sc2";
+};
+
+ðmac {
+ phy-mode = "rmii";
+ phy-handle = <&internal_phy>;
+};
+
+&ir {
+ status= "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&remote_pins>;
+};
diff --git a/arch/arm/dts/meson-sc2-s905x4-ah212-ddr3.dts b/arch/arm/dts/meson-sc2-s905x4-ah212-ddr3.dts
new file mode 100644
index 0000000..f3dae71
--- /dev/null
+++ b/arch/arm/dts/meson-sc2-s905x4-ah212-ddr3.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-sc2-s905x4-ah212-ddr3.dtsi"
+#include "meson-sc2_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,sc2-s905x4-ah212-dd3", "amlogic,s905x4", "amlogic,meson-sc2";
+ model = "Amlogic Meson SC2 S905X4 AH212 DDR3 Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-sc2-s905x4-ah212-ddr3.dtsi b/arch/arm/dts/meson-sc2-s905x4-ah212-ddr3.dtsi
new file mode 100644
index 0000000..47d358e
--- /dev/null
+++ b/arch/arm/dts/meson-sc2-s905x4-ah212-ddr3.dtsi
@@ -0,0 +1,239 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-sc2-s905x4.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_b;
+ serial1 = &uart_a;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c_gpio_0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ sd_hs_co_phase = <2>;
+ sd_hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <3>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <3>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&dwc3 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <2>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_a {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>;
+ spi-flash@0 {
+ status = "okay";
+ };
+ spi-nand@1 {
+ status = "okay";
+ };
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins_x>;
+ cs-gpios = <&gpio GPIOX_10 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins_h>;
+ cs-gpios = <&gpio GPIOH_6 0>;
+};
diff --git a/arch/arm/dts/meson-sc2-s905x4-ah212.dts b/arch/arm/dts/meson-sc2-s905x4-ah212.dts
new file mode 100644
index 0000000..d0237ae
--- /dev/null
+++ b/arch/arm/dts/meson-sc2-s905x4-ah212.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-sc2-s905x4-ah212.dtsi"
+#include "meson-sc2_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,sc2-s905x4-ah212", "amlogic,s905x4", "amlogic,meson-sc2";
+ model = "Amlogic Meson SC2 S905X4 AH212 Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-sc2-s905x4-ah212.dtsi b/arch/arm/dts/meson-sc2-s905x4-ah212.dtsi
new file mode 100644
index 0000000..ba3f3b5
--- /dev/null
+++ b/arch/arm/dts/meson-sc2-s905x4-ah212.dtsi
@@ -0,0 +1,244 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-sc2-s905x4.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_b;
+ serial1 = &uart_a;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c_gpio_0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ tee: tee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ sd_hs_co_phase = <2>;
+ sd_hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <3>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <3>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&dwc3 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <2>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_a {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>;
+ spi-flash@0 {
+ status = "okay";
+ };
+ spi-nand@1 {
+ status = "okay";
+ };
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins_x>;
+ cs-gpios = <&gpio GPIOX_10 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins_h>;
+ cs-gpios = <&gpio GPIOH_6 0>;
+};
diff --git a/arch/arm/dts/meson-sc2-s905x4-ah219.dts b/arch/arm/dts/meson-sc2-s905x4-ah219.dts
new file mode 100644
index 0000000..87f3efd
--- /dev/null
+++ b/arch/arm/dts/meson-sc2-s905x4-ah219.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-sc2-s905x4-ah219.dtsi"
+#include "meson-sc2_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,sc2-s905x4-ah219", "amlogic,s905x4", "amlogic,meson-sc2";
+ model = "Amlogic Meson SC2 S905X4 AH219 Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-sc2-s905x4-ah219.dtsi b/arch/arm/dts/meson-sc2-s905x4-ah219.dtsi
new file mode 100644
index 0000000..d9197aa
--- /dev/null
+++ b/arch/arm/dts/meson-sc2-s905x4-ah219.dtsi
@@ -0,0 +1,250 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-sc2-s905x4.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_b;
+ serial1 = &uart_a;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c_gpio_0;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ tee: tee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+/*exphy setting*/
+// pinctrl-names = "external_eth_rgmii_pins";
+// pinctrl-0 = <&external_eth_rgmii_pins>;
+// internal_phy = <0>;
+// mc_val = <0x1621>;
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ sd_hs_co_phase = <2>;
+ sd_hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <3>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <3>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&dwc3 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <2>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOH_6";
+ gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_a {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>;
+ spi-flash@0 {
+ status = "okay";
+ };
+ spi-nand@1 {
+ status = "okay";
+ };
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins_x>;
+ cs-gpios = <&gpio GPIOX_10 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins_h>;
+ cs-gpios = <&gpio GPIOH_6 0>;
+};
diff --git a/arch/arm/dts/meson-sc2-s905x4.dtsi b/arch/arm/dts/meson-sc2-s905x4.dtsi
new file mode 100644
index 0000000..ee227fe
--- /dev/null
+++ b/arch/arm/dts/meson-sc2-s905x4.dtsi
@@ -0,0 +1,60 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "meson-sc2.dtsi"
+#include "meson-sc2-mali.dtsi"
+
+/ {
+ compatible = "amlogic,s905x4", "amlogic,meson-sc2";
+};
+
+ðmac {
+ phy-mode = "rmii";
+ phy-handle = <&internal_phy>;
+};
+
+&ir {
+ status= "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&remote_pins>;
+};
diff --git a/arch/arm/dts/meson-sc2-series.dtsi b/arch/arm/dts/meson-sc2-series.dtsi
new file mode 100644
index 0000000..d498ad8
--- /dev/null
+++ b/arch/arm/dts/meson-sc2-series.dtsi
@@ -0,0 +1,513 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pwm/meson.h>
+#include <dt-bindings/clock/sc2-clkc.h>
+#include <dt-bindings/input/meson_rc.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 16 MiB reserved for Hardware ROM Firmware */
+ hwrom_reserved: hwrom@0 {
+ reg = <0x0 0x0 0x0 0x1000000>;
+ no-map;
+ };
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@10000000 {
+ reg = <0x0 0x10000000 0x0 0x200000>;
+ no-map;
+ };
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0xbc00000>;
+ alignment = <0x0 0x400000>;
+ linux,cma-default;
+ };
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+
+ firmware {
+ sm: secure-monitor {
+ compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
+ };
+ };
+
+ efuse: efuse {
+ compatible = "amlogic,meson-sc2-efuse", "amlogic,meson-sc2-efuse";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ };
+
+ scpi {
+ compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
+ mboxes = <&mailbox 1 &mailbox 2>;
+ shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+
+ scpi_clocks: clocks {
+ compatible = "arm,scpi-clocks";
+
+ scpi_dvfs: scpi_clocks@0 {
+ compatible = "arm,scpi-dvfs-clocks";
+ #clock-cells = <1>;
+ clock-indices = <0>;
+ clock-output-names = "vcpu";
+ };
+ };
+
+ scpi_sensors: sensors {
+ compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@2c001000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xffc01000 0 0x1000>,
+ <0x0 0xffc02000 0 0x2000>,
+ <0x0 0xffc04000 0 0x2000>,
+ <0x0 0xffc06000 0 0x2000>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ };
+
+ sram: sram@f7000000 {
+ compatible = "amlogic,meson-sc2-sram", "amlogic,meson-sc2-sram", "mmio-sram";
+ reg = <0x0 0xf7000000 0x0 0x48000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0xf7000000 0x48000>;
+
+ cpu_scp_lpri: scp-shmem@0 {
+ compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
+ reg = <0x47000 0x400>;
+ };
+
+ cpu_scp_hpri: scp-shmem@200 {
+ compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
+ reg = <0x47400 0x400>;
+ };
+ };
+
+ cbus: cbus@fe070000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xfe070000 0x0 0xF000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xfe070000 0x0 0xF000>;
+
+ uart_a: serial@8000 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x8000 0x0 0x18>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ uart_b: serial@a000 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0xa000 0x0 0x18>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ reset: reset-controller@1000 {
+ compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
+ reg = <0x0 0x01000 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
+ uart_c: serial@22000 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x22000 0x0 0x18>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ jtag {
+ compatible = "amlogic, jtag";
+ status = "okay";
+ select = "disable"; /* disable/jtag-a/jtag-b */
+ pinctrl-names="jtag_a_pins", "jtag_b_pins";
+ pinctrl-0=<&jtag_a_pins>;
+ pinctrl-1=<&jtag_b_pins>;
+ };
+ };
+
+ periphs: periphs@ff634000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xff634000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
+
+ hwrng: rng {
+ compatible = "amlogic,meson-rng";
+ reg = <0x0 0x0 0x0 0x4>;
+ };
+ };
+
+ hiubus: hiubus@ff63c000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xff63c000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>;
+
+ mailbox: mailbox@404 {
+ compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
+ reg = <0 0x404 0 0x4c>;
+ interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
+ <0 209 IRQ_TYPE_EDGE_RISING>,
+ <0 210 IRQ_TYPE_EDGE_RISING>;
+ #mbox-cells = <1>;
+ };
+ };
+
+ clkc: clock-controller@0 {
+ compatible = "amlogic,sc2-clkc";
+ #clock-cells = <1>;
+ reg = <0x0 0xfe000000 0x0 0x82e8>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ };
+
+ i2c0: i2c@fe001400 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe066000 0x0 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@fe005c00 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe068000 0x0 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@fe006800 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe06a000 0x0 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@fe006c00 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe06c000 0x0 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@fe06e000 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe06e000 0x0 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spicc0: spi@fe050000 {
+ compatible = "amlogic,meson-g12a-spicc";
+ reg = <0x0 0xfe050000 0x0 0x44>;
+ interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spicc1: spi@fe052000 {
+ compatible = "amlogic,meson-g12a-spicc";
+ reg = <0x0 0xfe052000 0x0 0x44>;
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spifc: spi@fe056000 {
+ compatible = "amlogic,spifc";
+ status = "disabled";
+ reg = <0x0 0xfe056000 0x0 0x80>;
+ /* clocks = <&clkc CLKID_CLK81>; */
+ /* clock-names = "core"; */
+ pinctrl-names = "default";
+ pinctrl-0 = <&spifc_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ status = "disabled";
+ };
+ spi-nand@1 {
+ compatible = "spi-nand";
+ reg = <1>;
+ spi-max-frequency = <20000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ status = "disabled";
+ };
+ };
+
+ ethmac: ethernet@ff3f0000 {
+ compatible = "amlogic,g12a-eth-dwmac";
+ phy_cntl1 = <0x41054147>;
+ pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>;
+ analog_val = <0x20200000 0x0000c000 0x00000023>;
+ status = "disabled";
+ };
+
+ saradc: adc@fe026000 {
+ compatible = "amlogic,meson-saradc";
+ reg = <0x0 0xfe026000 0x0 0x48>;
+ status = "disabled";
+ };
+
+ nand: nfc@fe08c800 {
+ compatible = "amlogic,meson-nfc";
+ reg = <0x0 0xfe08c800 0x0 0x200>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ clk_reg = <0 0xfe08c000>;
+ };
+
+ apb: apb@fe000000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xfe000000 0x0 0x1000000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
+
+ watchdog@2100 {
+ compatible = "amlogic,meson-sc2-wdt";
+ reg = <0x0 0x2100 0x0 0x10>;
+ clocks = <&xtal>;
+ clock-names = "wdt-clk";
+ };
+
+ sd_emmc_a: sdio {
+ compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
+ reg = <0x0 0x88000 0x0 0x800>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ pinname = "sdio";
+ };
+
+ sd_emmc_b: sd {
+ compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
+ reg = <0x0 0x8a000 0x0 0x800>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ pinname = "sd";
+ };
+
+ sd_emmc_c: emmc {
+ compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
+ reg = <0x0 0x8c000 0x0 0x800>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ pinname = "emmc";
+ };
+ };
+
+ dwc3: dwc3@fde00000 {
+ compatible = "snps,dwc3","synopsys,xhci-dwc3";
+ status = "disable";
+ reg = <0x0 0xfde00000 0x0 0x100000>;
+ phys = <&usb2_phy_v2>, <&usb3_phy_v2>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ usb2_phy_v2: usb2phy@fe03a000 {
+ compatible = "amlogic, amlogic-new-usb2-v2";
+ status = "disable";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ phy-version = <2>;
+ reg = <0x0 0xfe03a000 0x0 0x80
+ 0x0 0xFE002000 0x0 0x100
+ 0x0 0xfe03c000 0x0 0x2000
+ 0x0 0xfe03e000 0x0 0x2000>;
+ dwc2_a_reg = <0xfdd00000>;
+ #phy-cells = <0>;
+ };
+
+ usb3_phy_v2: usb3phy@fe03a080 {
+ compatible = "amlogic, amlogic-new-usb3-v2";
+ status = "disable";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ phy-version = <3>;
+ reg = <0x0 0xfe03a080 0x0 0x20>;
+ phy-reg = <0xfe03c000>;
+ phy-reg-size = <0x2000>;
+ usb2-phy-reg = <0xfe03a000>;
+ usb2-phy-reg-size = <0x80>;
+ #phy-cells = <0>;
+ };
+
+ ir: meson-ir {
+ compatible = "amlogic, meson-ir";
+ reg = <0x0 0xfe084040 0x44 0x0>, /*Multi-format IR controller*/
+ <0x0 0xfe084000 0x20 0x0>; /*Legacy IR controller*/
+ protocol = <REMOTE_TYPE_NEC>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm/dts/meson-sc2.dtsi b/arch/arm/dts/meson-sc2.dtsi
new file mode 100644
index 0000000..e7aaaa1
--- /dev/null
+++ b/arch/arm/dts/meson-sc2.dtsi
@@ -0,0 +1,826 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "meson-sc2-series.dtsi"
+#include <dt-bindings/gpio/meson-sc2-gpio.h>
+#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pwm/meson.h>
+
+/ {
+ compatible = "amlogic,meson-sc2";
+
+ vpu {
+ compatible = "amlogic, vpu-g12a";
+ status = "okay";
+ /*clocks = <&clkc CLKID_VAPB_MUX>,
+ * <&clkc CLKID_VPU_INTR>,
+ * <&clkc CLKID_VPU_P0_COMP>,
+ * <&clkc CLKID_VPU_P1_COMP>,
+ * <&clkc CLKID_VPU_MUX>;
+ *clock-names = "vapb_clk",
+ * "vpu_intr_gate",
+ * "vpu_clk0",
+ * "vpu_clk1",
+ * "vpu_clk";
+ */
+ clk_level = <7>;
+ /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
+ /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */
+ };
+
+ fb {
+ status = "okay";
+ logo_addr = "0x7f800000";
+ };
+
+ pinctrl_periphs: pinctrl@fe004000 {
+ compatible = "amlogic,meson-sc2-periphs-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio: bank@fe004000 {
+ reg = <0x0 0xfe004000 0x0 0x004c>,
+ <0x0 0xfe0040c0 0x0 0x0220>;
+ reg-names = "mux",
+ "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_periphs 0 0 87>;
+ };
+ };
+
+ i2c_gpio_0: i2c-gpio-0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "i2c-gpio";
+ status = "okay";
+ gpios = <&gpio GPIOH_0 GPIO_ACTIVE_HIGH>, /* SDA */
+ <&gpio GPIOH_1 GPIO_ACTIVE_HIGH>; /* CLK */
+
+ i2c-gpio,delay-us = <5>;
+ is_odpin = <1>;
+ };
+
+ pwm_ab: pwm@fe058000 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0xfe058000 0x0 0x20>,
+ <0x0 0xfe000180 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_cd: pwm@fe05a000 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0xfe05a000 0x0 0x20>,
+ <0x0 0xfe000184 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_ef: pwm@fe05c000 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0xfe05c000 0x0 0x20>,
+ <0x0 0xfe000188 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_gh: pwm@fe05e000 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0xfe05e000 0x0 0x20>,
+ <0x0 0xfe00018c 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_ij: pwm@fe060000 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0xfe060000 0x0 0x20>,
+ <0x0 0xfe000190 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+};
+
+ðmac {
+ compatible = "amlogic,g12a-eth-dwmac";
+ reg = <0x0 0xfdc00000 0x0 0x10000
+ 0x0 0xFE024000 0x0 0x8
+ 0x0 0xFE028000 0x0 0xa0>;
+ reg-names = "eth_base", "eth_top", "eth_cfg";
+ phy_cntl1 = <0x41054147>;
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ cali_val = <0x80000>;
+ reset-gpios = <&gpio GPIOZ_15 GPIO_ACTIVE_HIGH>;
+ analog_ver = <1>; /*1:c1; 2:c2*/
+ pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>;
+ analog_val = <0x20200000 0x0000c000 0x00000023>;
+ chip_num = <3>;
+ //tx_amp_src = <0xfe005b30>;
+// clocks = <&clkc CLKID_ETH_CORE>,
+// <&clkc CLKID_FCLK_DIV2>,
+// <&clkc CLKID_MPLL2>;
+// clock-names = "stmmaceth", "clkin0", "clkin1";
+
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+};
+
+&periphs {
+
+ eth-phy-mux {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x15c 0x0 0x4>;
+ mux-mask = <0xffffffff>;
+ mdio-parent-bus = <&mdio0>;
+
+ internal_mdio: mdio@e40908ff {
+ reg = <0xe40908ff>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ internal_phy: ethernet-phy@8 {
+ compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
+ reg = <8>;
+ max-speed = <100>;
+ };
+ };
+
+ external_mdio: mdio@2009087f {
+ reg = <0x2009087f>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&saradc {
+ compatible = "amlogic,meson-g12a-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SARADC_MUX>,
+ <&clkc CLKID_SARADC_DIV>,
+ <&clkc CLKID_SAR_ADC_GATE>;
+ clock-names = "xtal", "adc_mux", "adc_div", "adc_gate";
+};
+
+&sd_emmc_a {
+ clocks = <&clkc CLKID_SD_EMMC_A_MUX>,
+ <&clkc CLKID_SD_EMMC_A_DIV>,
+ <&clkc CLKID_SD_EMMC_A_GATE>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_XTAL>;
+ clock-names = "mux", "div", "gate", "clkin", "xtal";
+};
+
+&sd_emmc_b {
+ clocks = <&clkc CLKID_SD_EMMC_B_MUX>,
+ <&clkc CLKID_SD_EMMC_B_DIV>,
+ <&clkc CLKID_SD_EMMC_B_GATE>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_XTAL>;
+ clock-names = "mux", "div", "gate", "clkin", "xtal";
+};
+
+&sd_emmc_c {
+ clocks = <&clkc CLKID_SD_EMMC_C_MUX>,
+ <&clkc CLKID_SD_EMMC_C_DIV>,
+ <&clkc CLKID_SD_EMMC_C_GATE>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_XTAL>;
+ clock-names = "mux", "div", "gate", "clkin", "xtal";
+};
+
+&nand {
+ clocks = <&clkc CLKID_SD_EMMC_C_MUX>,
+ <&clkc CLKID_SD_EMMC_C_DIV>,
+ <&clkc CLKID_SD_EMMC_C_GATE>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_XTAL>;
+ clock-names = "mux", "div", "gate", "fdiv2", "xtal";
+};
+
+&spicc0 {
+ clocks = <&clkc CLKID_SPICC_A_DIV>, <&clkc CLKID_SPICC_A_GATE>;
+ clock-names = "async", "async-gate";
+ assigned-clocks = <&clkc CLKID_SPICC_A_MUX>, <&clkc CLKID_SPICC_A_DIV>;
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
+ assigned-clock-rates = <0>, <200000000>;
+ /* =PM_SPICC, no set for power on already */
+ /* pm-id = <22>; */
+};
+
+&spicc1 {
+ clocks = <&clkc CLKID_SPICC_B_DIV>, <&clkc CLKID_SPICC_B_GATE>;
+ clock-names = "async", "async-gate";
+ assigned-clocks = <&clkc CLKID_SPICC_B_MUX>, <&clkc CLKID_SPICC_B_DIV>;
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
+ assigned-clock-rates = <0>, <200000000>;
+ /* =PM_SPICC_B, no set for power on already */
+ /* pm-id = <39>; */
+};
+
+&pinctrl_periphs {
+ i2c0_master_pins1:i2c0_pins1 {
+ mux {
+ groups = "i2c_a_sda_c",
+ "i2c_a_scl_c";
+ function = "i2c_a";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c0_master_pins2:i2c0_pins2 {
+ mux {
+ groups = "i2c_a_sda_h",
+ "i2c_a_scl_h";
+ function = "i2c_a";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c0_master_pins3:i2c0_pins3 {
+ mux {
+ groups = "i2c_a_sda_z0",
+ "i2c_a_scl_z1";
+ function = "i2c_a";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c0_master_pins4:i2c0_pins4 {
+ mux {
+ groups = "i2c_a_sda_z7",
+ "i2c_a_scl_z8";
+ function = "i2c_a";
+ drive-strength = <3>;
+ bias-disable;
+
+ };
+ };
+
+ i2c1_master_pins1:i2c1_pins1 {
+ mux {
+ groups = "i2c_b_sda_z",
+ "i2c_b_scl_z";
+ function = "i2c_b";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c1_master_pins2:i2c1_pins2 {
+ mux {
+ groups = "i2c_b_sda_x",
+ "i2c_b_scl_x";
+ function = "i2c_b";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c1_master_pins3:i2c1_pins3 {
+ mux {
+ groups = "i2c_b_sda_h2",
+ "i2c_b_scl_h3";
+ function = "i2c_b";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c1_master_pins4:i2c1_pins4 {
+ mux {
+ groups = "i2c_b_sda_h6",
+ "i2c_b_scl_h7";
+ function = "i2c_b";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c2_master_pins1:i2c2_pins1 {
+ mux {
+ groups = "i2c_c_sda_x",
+ "i2c_c_scl_x";
+ function = "i2c_c";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c2_master_pins2:i2c2_pins2 {
+ mux {
+ groups = "i2c_c_sda_z10",
+ "i2c_c_scl_z11";
+ function = "i2c_c";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c2_master_pins3:i2c2_pins3 {
+ mux {
+ groups = "i2c_c_sda_z14",
+ "i2c_c_scl_z15";
+ function = "i2c_c";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c3_master_pins1:i2c3_pins1 {
+ mux {
+ groups = "i2c_d_sda_h",
+ "i2c_d_scl_h";
+ function = "i2c_d";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c3_master_pins2:i2c3_pins2 {
+ mux {
+ groups = "i2c_d_sda_a",
+ "i2c_d_scl_a";
+ function = "i2c_d";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c4_master_pin1:i2c4_pins1 {
+ mux {
+ groups = "i2c_e_sda_d",
+ "i2c_e_scl_d";
+ function = "i2c_e";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c4_master_pin2:i2c4_pins2 {
+ mux {
+ groups = "i2c_e_sda_e",
+ "i2c_e_scl_e";
+ function = "i2c_e";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ jtag_a_pins:jtag_a_pin {
+ mux {
+ groups = "jtag_1_clk",
+ "jtag_1_tms",
+ "jtag_1_tdi",
+ "jtag_1_tdo";
+ function = "jtag_1";
+ };
+ };
+
+ jtag_b_pins:jtag_b_pin {
+ mux {
+ groups = "jtag_2_clk",
+ "jtag_2_tms",
+ "jtag_2_tdi",
+ "jtag_2_tdo";
+ function = "jtag_2";
+ };
+ };
+
+ swd_a_pins:swd_a_pin {
+ mux {
+ groups = "swclk",
+ "swdio";
+ function = "sw";
+ };
+ };
+
+ emmc_pins: emmc {
+ mux {
+ groups = "emmc_nand_d0",
+ "emmc_nand_d1",
+ "emmc_nand_d2",
+ "emmc_nand_d3",
+ "emmc_nand_d4",
+ "emmc_nand_d5",
+ "emmc_nand_d6",
+ "emmc_nand_d7",
+ "emmc_clk",
+ "emmc_cmd";
+ function = "emmc";
+ bias-pull-up;
+ input-enable;
+ };
+ mux1 {
+ groups = "emmc_nand_ds";
+ function = "emmc";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ emmc_clk_gate_pins: emmc_clk_gate {
+ mux {
+ groups = "emmc_clk";
+ function = "emmc";
+ bias-pull-down;
+ };
+ };
+
+ all_nand_pins: all_nand_pins {
+ mux {
+ groups = "emmc_nand_d0",
+ "emmc_nand_d1",
+ "emmc_nand_d2",
+ "emmc_nand_d3",
+ "emmc_nand_d4",
+ "emmc_nand_d5",
+ "emmc_nand_d6",
+ "emmc_nand_d7",
+ "nand_ce0",
+ "nand_ale",
+ "nand_cle",
+ "nand_wen_clk",
+ "nand_ren_wr";
+ function = "nand";
+ input-enable;
+ };
+ };
+
+ nand_cs_pins: nand_cs {
+ mux {
+ groups = "nand_ce0";
+ function = "nand";
+ };
+ };
+
+ sdcard_pins: sdcard {
+ mux {
+ groups = "sdcard_d0_c",
+ "sdcard_d1_c",
+ "sdcard_d2_c",
+ "sdcard_d3_c",
+ "sdcard_cmd_c";
+ function = "sdcard";
+ bias-pull-up;
+ input-enable;
+ drive-strength = <4>;
+ };
+ mux1 {
+ groups ="sdcard_clk_c";
+ function = "sdcard";
+ bias-pull-up;
+ output-high;
+ drive-strength = <4>;
+ };
+ };
+
+ sdcard_clk_gate_pins: sdcard_clk_gate {
+ mux {
+ groups = "sdcard_clk_c";
+ function = "sdcard";
+ bias-pull-down;
+ };
+ };
+
+ to_sduart_pins: to_sduart_pins{
+ mux {
+ groups = "uart_b_rx_c", "uart_b_tx_c";
+ function = "uart_b";
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
+ sd_to_uart_pins: sd_to_uart_pins{
+ mux {
+ groups = "uart_b_rx_d", "uart_b_tx_d";
+ function = "uart_b";
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
+ spicc0_pins_x: spicc0_pins_x {
+ mux {
+ groups = "spi_a_mosi_x",
+ "spi_a_miso_x",
+ //"spi_a_ss0_x",
+ "spi_a_sclk_x";
+ function = "spi_a";
+ drive-strength = <1>;
+ };
+ };
+
+ spicc0_pins_c: spicc0_pins_c {
+ mux {
+ groups = "spi_a_mosi_c",
+ "spi_a_miso_c",
+ //"spi_a_ss0_c",
+ "spi_a_sclk_c";
+ function = "spi_a";
+ drive-strength = <1>;
+ };
+ };
+
+ spicc1_pins_h: spicc1_pins_h {
+ mux {
+ groups = "spi_b_mosi_h",
+ "spi_b_miso_h",
+ //"spi_b_ss0_h",
+ "spi_b_sclk_h";
+ function = "spi_b";
+ drive-strength = <1>;
+ };
+ };
+
+ spifc_pins: spifc_pins {
+ mux {
+ groups = "nor_d",
+ "nor_q",
+ "nor_c",
+ //"nor_cs",
+ "nor_hold",
+ "nor_wp";
+ function = "nor";
+ drive-strength = <3>;
+ };
+ };
+
+ pwm_a_pins1: pwm_a_pins1 {
+ mux {
+ groups = "pwm_a_e";
+ function = "pwm_a";
+ };
+ };
+
+ pwm_a_pins2: pwm_a_pins2 {
+ mux {
+ groups = "pwm_a_x";
+ function = "pwm_a";
+ };
+ };
+
+ pwm_b_pins1: pwm_b_pins1 {
+ mux {
+ groups = "pwm_b_h";
+ function = "pwm_b";
+ };
+ };
+
+ pwm_b_pins2: pwm_b_pins2 {
+ mux {
+ groups = "pwm_b_z0";
+ function = "pwm_b";
+ };
+ };
+
+ pwm_b_pins3: pwm_b_pins3 {
+ mux {
+ groups = "pwm_b_z13";
+ function = "pwm_b";
+ };
+ };
+
+ pwm_b_pins4: pwm_b_pins4 {
+ mux {
+ groups = "pwm_b_x7";
+ function = "pwm_b";
+ };
+ };
+
+ pwm_b_pins5: pwm_b_pins5 {
+ mux {
+ groups = "pwm_b_x19";
+ function = "pwm_b";
+ };
+ };
+
+ pwm_c_pins1: pwm_c_pins1 {
+ mux {
+ groups = "pwm_c_c";
+ function = "pwm_c";
+ };
+ };
+
+ pwm_c_pins2: pwm_c_pins2 {
+ mux {
+ groups = "pwm_c_x";
+ function = "pwm_c";
+ };
+ };
+
+ pwm_c_pins3: pwm_c_pins3 {
+ mux {
+ groups = "pwm_c_z";
+ function = "pwm_c";
+ };
+ };
+
+ pwm_d_pins1: pwm_d_pins1 {
+ mux {
+ groups = "pwm_d_z";
+ function = "pwm_d";
+ };
+ };
+
+ pwm_d_pins2: pwm_d_pins2 {
+ mux {
+ groups = "pwm_d_x3";
+ function = "pwm_d";
+ };
+ };
+
+ pwm_d_pins3: pwm_d_pins3 {
+ mux {
+ groups = "pwm_d_x6";
+ function = "pwm_d";
+ };
+ };
+
+ pwm_e_pins: pwm_e {
+ mux {
+ groups = "pwm_e";
+ function = "pwm_e";
+ };
+ };
+
+ pwm_f_pins1: pwm_f_pins1 {
+ mux {
+ groups = "pwm_f_x";
+ function = "pwm_f";
+ };
+ };
+
+ pwm_f_pins2: pwm_f_pins2 {
+ mux {
+ groups = "pwm_f_h";
+ function = "pwm_f";
+ };
+ };
+
+ pwm_f_pins3: pwm_f_pins3 {
+ mux {
+ groups = "pwm_f_z";
+ function = "pwm_f";
+ };
+ };
+
+ pwm_g_pins1: pwm_g_pins1 {
+ mux {
+ groups = "pwm_g";
+ function = "pwm_g";
+ };
+ };
+
+ pwm_h_pins1: pwm_h_pins1 {
+ mux {
+ groups = "pwm_h";
+ function = "pwm_h";
+ };
+ };
+
+ pwm_i_pins1: pwm_i_pins1 {
+ mux {
+ groups = "pwm_i_d4";
+ function = "pwm_i";
+ };
+ };
+
+ pwm_i_pins2: pwm_i_pins2 {
+ mux {
+ groups = "pwm_i_d6";
+ function = "pwm_i";
+ };
+ };
+
+ pwm_j_pins1: pwm_j_pins1 {
+ mux {
+ groups = "pwm_j_e";
+ function = "pwm_j";
+ };
+ };
+
+ pwm_j_pins2: pwm_j_pins2 {
+ mux {
+ groups = "pwm_j_d5";
+ function = "pwm_j";
+ };
+ };
+
+ pwm_j_pins3: pwm_j_pins3 {
+ mux {
+ groups = "pwm_j_d10";
+ function = "pwm_j";
+ };
+ };
+
+ pwm_i_hiz_pins1: pwm_i_hiz_pins1 {
+ mux {
+ groups = "pwm_i_hiz";
+ function = "pwm_i_hiz";
+ };
+ };
+
+ pwm_g_hiz_pins1: pwm_g_hiz_pins1 {
+ mux {
+ groups = "pwm_g_hiz";
+ function = "pwm_g_hiz";
+ };
+ };
+ external_eth_rmii_pins: external_eth_rmii_pins {
+ mux {
+ groups = "eth_mdio",
+ "eth_mdc",
+ "eth_rgmii_rx_clk",
+ "eth_rx_dv",
+ "eth_rxd0",
+ "eth_rxd1",
+ "eth_txen",
+ "eth_txd0",
+ "eth_txd1";
+ function = "eth";
+ drive-strength = <3>;
+ };
+ };
+ external_eth_rgmii_pins: external_eth_rgmii_pins {
+ mux {
+ groups = "eth_mdio",
+ "eth_mdc",
+ "eth_rgmii_rx_clk",
+ "eth_rx_dv",
+ "eth_rxd0",
+ "eth_rxd1",
+ "eth_rxd2_rgmii",
+ "eth_rxd3_rgmii",
+ "eth_rgmii_tx_clk",
+ "eth_txen",
+ "eth_txd0",
+ "eth_txd1",
+ "eth_txd2_rgmii",
+ "eth_txd3_rgmii";
+ function = "eth";
+ drive-strength = <3>;
+ };
+ };
+
+ remote_pins: remote_pin {
+ mux {
+ groups = "remote_input_d5";
+ function = "remote_input";
+ };
+ };
+};
diff --git a/arch/arm/dts/meson-sc2_skt-panel.dtsi b/arch/arm/dts/meson-sc2_skt-panel.dtsi
new file mode 100644
index 0000000..fbb676c
--- /dev/null
+++ b/arch/arm/dts/meson-sc2_skt-panel.dtsi
@@ -0,0 +1,742 @@
+/*
+ * arch/arm64/boot/dts/amlogic/mesong12a_skt-panel.dtsi
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+/ {
+ lcd{
+ compatible = "amlogic, lcd-g12a";
+ mode = "tablet";
+ status = "okay";
+ key_valid = <0>;
+ /*
+ clocks = <&clkc CLKID_MIPI_DSI_HOST
+ &clkc CLKID_MIPI_DSI_PHY
+ &clkc CLKID_DSI_MEAS_COMP
+ &clkc CLKID_VCLK2_ENCL
+ &clkc CLKID_VCLK2_VENCL
+ &clkc CLKID_GP0_PLL>;
+ clock-names = "dsi_host_gate",
+ "dsi_phy_gate",
+ "dsi_meas",
+ "encl_top_gate",
+ "encl_int_gate",
+ "gp0_pll";
+ */
+ reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */
+ 0x0 0xff644000 0x0 0x200>; /* dsi_phy */
+ interrupts = <0 3 1
+ 0 56 1>;
+ interrupt-names = "vsync","vsync2";
+ pinctrl_version = <2>; /* for uboot */
+
+ /* power type:
+ * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending)
+ * power index:
+ * (point gpios_index, or extern_index,0xff=invalid)
+ * power value:(0=output low, 1=output high, 2=input)
+ * power delay:(unit in ms)
+ */
+
+ /*lcd_cpu-gpios = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH
+ &gpio GPIOZ_8 GPIO_ACTIVE_HIGH>;
+ */
+ lcd_cpu_gpio_names = "GPIOZ_9","GPIOZ_8";
+
+ lcd_0{
+ model_name = "B080XAN01";
+ interface = "mipi";
+ basic_setting = <768 1024 /*h_active, v_active*/
+ 948 1140 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 119 159>; /*screen_widht, screen_height*/
+ lcd_timing = <64 56 0 /*hs_width, hs_bp, hs_pol*/
+ 50 30 0>; /*vs_width, vs_bp, vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/
+ 0 /*clk_ss_level */
+ 1 /*clk_auto_generate*/
+ 64843200>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 550 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 1 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <0x05 1 0x11
+ 0xfd 1 20 /*delay(ms)*/
+ 0x05 1 0x29
+ 0xfd 1 20 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ dsi_init_off = <0x05 1 0x28
+ 0xfd 1 10 /*delay(ms)*/
+ 0x05 1 0x10
+ 0xfd 1 10 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ extern_init = <0xff>; /*0xff for invalid*/
+
+ /* power step: type, index, value, delay(ms) */
+ power_on_step = <
+ 0 1 0 100
+ 0 0 0 10
+ 0 0 1 20
+ 2 0 0 0
+ 0xff 0 0 0>; /*ending*/
+ power_off_step = <
+ 2 0 0 50
+ 0 0 0 10
+ 0 1 1 100
+ 0xff 0 0 0>; /*ending*/
+ backlight_index = <0>;
+ };
+
+ lcd_1{
+ model_name = "P070ACB_FT";
+ interface = "mipi";
+ basic_setting = <600 1024 /*h_active, v_active*/
+ 770 1070 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 3 5>; /*screen_widht, screen_height*/
+ lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/
+ 6 20 0>; /*vs_width,vs_bp,vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
+ 0 /*clk_ss_level*/
+ 1 /*clk_auto_generate*/
+ 49434000>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 400 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 0 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <
+ 0xff 10
+ 0xf0 3 0 1 30 /* reset high, delay 30ms */
+ 0xf0 3 0 0 10 /* reset low, delay 10ms */
+ 0xf0 3 0 1 30 /* reset high, delay 30ms */
+ 0xfc 2 0x04 3 /* check_reg, check_cnt */
+ 0xff 0>; /* ending flag */
+ dsi_init_off = <0xff 0>; /* ending flag */
+ /* extern_init: 0xff for invalid */
+ extern_init = <2>;
+ /* power step: type,index,value,delay(ms) */
+ power_on_step = <
+ 0 1 0 200 /* panel power on */
+ 2 0 0 0
+ 0xff 0 0 0>;
+ power_off_step = <
+ 2 0 0 0
+ 0 0 0 20 /* reset low */
+ 0 1 1 100 /* panel power off */
+ 0xff 0 0 0>;
+ backlight_index = <0>;
+ };
+
+ lcd_3{
+ model_name = "TL050FHV02CT";
+ interface = "mipi";
+ basic_setting = <1080 1920 /*h_active, v_active*/
+ 1125 2100 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 65 119>; /*screen_widht, screen_height*/
+ lcd_timing = <5 30 0 /*hs_width,hs_bp,hs_pol*/
+ 44 108 0>; /*vs_width,vs_bp,vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
+ 0 /*clk_ss_level*/
+ 1 /*clk_auto_generate*/
+ 118125000>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 960 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 1 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <0xff 0>; /* ending flag */
+ dsi_init_off = <0xff 0>; /* ending flag */
+ /* extern_init: 0xff for invalid */
+ extern_init = <3>;
+ /* power step: type,index,value,delay(ms) */
+ power_on_step = <
+ 0 1 0 200
+ 0 0 1 20
+ 0 0 0 10
+ 0 0 1 20
+ 2 0 0 0
+ 0xff 0 0 0>;
+ power_off_step = <
+ 2 0 0 0
+ 0 0 0 20
+ 0 1 1 100
+ 0xff 0 0 0>;
+ backlight_index = <0>;
+ };
+
+ lcd_4{
+ model_name = "TL070WSH27";
+ interface = "mipi";
+ basic_setting = <1024 600 /*h_active, v_active*/
+ 1250 630 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 154 86>; /*screen_widht, screen_height*/
+ lcd_timing = <80 100 0 /*hs_width, hs_bp, hs_pol*/
+ 5 20 0>; /*vs_width, vs_bp, vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/
+ 0 /*clk_ss_level */
+ 1 /*clk_auto_generate*/
+ 47250000>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 300 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 1 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <0x05 1 0x11
+ 0xfd 1 20 /*delay(ms)*/
+ 0x05 1 0x29
+ 0xfd 1 20 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ dsi_init_off = <0x05 1 0x28
+ 0xfd 1 10 /*delay(ms)*/
+ 0x05 1 0x10
+ 0xfd 1 10 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ extern_init = <0xff>; /*0xff for invalid*/
+
+ /* power step: type, index, value, delay(ms) */
+ power_on_step = <
+ 0 1 0 100
+ 0 0 0 10
+ 0 0 1 20
+ 2 0 0 0
+ 0xff 0 0 0>; /*ending*/
+ power_off_step = <
+ 2 0 0 50
+ 0 0 0 10
+ 0 1 1 100
+ 0xff 0 0 0>; /*ending*/
+ backlight_index = <0>;
+ };
+ };
+
+ lcd_extern{
+ compatible = "amlogic, lcd_extern";
+ status = "okay";
+ i2c_bus = "i2c_bus_0";
+ key_valid = <0>;
+
+ extern_0{
+ index = <0>;
+ extern_name = "mipi_default";/*default*/
+ status = "okay";
+ type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+ cmd_size = <0xff>;
+ init_on = <
+ 0xfd 1 10
+ 0x05 1 0x11
+ 0xfd 1 120 /* delay 120ms */
+ 0x05 1 0x29
+ 0xff 0>; /*ending*/
+ init_off = <
+ 0x05 1 0x28 /* display off */
+ 0xfd 1 10 /* delay 10ms */
+ 0x05 1 0x10 /* sleep in */
+ 0xfd 1 150 /* delay 150ms */
+ 0xff 0>; /*ending*/
+ };
+
+ extern_2{
+ index = <2>;
+ extern_name = "mipi_default";/*P070ACB_FT*/
+ status = "okay";
+ type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+ cmd_size = <0xff>;
+ init_on = <
+ 0x23 2 0xE0 0x00 /* Page 0 */
+ 0x23 2 0xE1 0x93 /* PASSWORD */
+ 0x23 2 0xE2 0x65
+ 0x23 2 0xE3 0xF8
+ 0x23 2 0x80 0x03
+ 0x23 2 0xE0 0x01 /* Page 01 */
+ 0x23 2 0x0C 0x74 /* Set PWRIC */
+ 0x23 2 0x17 0x00 /* Set Gamma Power */
+ 0x23 2 0x18 0xEF /* VGMP=5.1V */
+ 0x23 2 0x19 0x00
+ 0x23 2 0x1A 0x00
+ 0x23 2 0x1B 0xEF /* VGMN=-5.1V */
+ 0x23 2 0x1C 0x00
+ 0x23 2 0x1F 0x70 /* Set Gate Power */
+ 0x23 2 0x20 0x2D
+ 0x23 2 0x21 0x2D
+ 0x23 2 0x22 0x7E
+ 0x23 2 0x26 0xF3 /* VDDD from IOVCC */
+ 0x23 2 0x37 0x09 /* SetPanel */
+ 0x23 2 0x38 0x04 /* SET RGBCYC */
+ 0x23 2 0x39 0x00
+ 0x23 2 0x3A 0x01
+ 0x23 2 0x3C 0x90
+ 0x23 2 0x3D 0xFF
+ 0x23 2 0x3E 0xFF
+ 0x23 2 0x3F 0xFF
+ 0x23 2 0x40 0x02 /* Set TCON */
+ 0x23 2 0x41 0x80
+ 0x23 2 0x42 0x99
+ 0x23 2 0x43 0x14
+ 0x23 2 0x44 0x19
+ 0x23 2 0x45 0x5A
+ 0x23 2 0x4B 0x04
+ 0x23 2 0x55 0x02 /* power voltage */
+ 0x23 2 0x56 0x01
+ 0x23 2 0x57 0x69
+ 0x23 2 0x58 0x0A
+ 0x23 2 0x59 0x0A
+ 0x23 2 0x5A 0x2E /* VGH = 16.2V */
+ 0x23 2 0x5B 0x19 /* VGL = -12V */
+ 0x23 2 0x5C 0x15
+ 0x23 2 0x5D 0x77 /* Gamma */
+ 0x23 2 0x5E 0x56
+ 0x23 2 0x5F 0x45
+ 0x23 2 0x60 0x38
+ 0x23 2 0x61 0x35
+ 0x23 2 0x62 0x27
+ 0x23 2 0x63 0x2D
+ 0x23 2 0x64 0x18
+ 0x23 2 0x65 0x33
+ 0x23 2 0x66 0x34
+ 0x23 2 0x67 0x35
+ 0x23 2 0x68 0x56
+ 0x23 2 0x69 0x45
+ 0x23 2 0x6A 0x4F
+ 0x23 2 0x6B 0x42
+ 0x23 2 0x6C 0x40
+ 0x23 2 0x6D 0x34
+ 0x23 2 0x6E 0x25
+ 0x23 2 0x6F 0x02
+ 0x23 2 0x70 0x77
+ 0x23 2 0x71 0x56
+ 0x23 2 0x72 0x45
+ 0x23 2 0x73 0x38
+ 0x23 2 0x74 0x35
+ 0x23 2 0x75 0x27
+ 0x23 2 0x76 0x2D
+ 0x23 2 0x77 0x18
+ 0x23 2 0x78 0x33
+ 0x23 2 0x79 0x34
+ 0x23 2 0x7A 0x35
+ 0x23 2 0x7B 0x56
+ 0x23 2 0x7C 0x45
+ 0x23 2 0x7D 0x4F
+ 0x23 2 0x7E 0x42
+ 0x23 2 0x7F 0x40
+ 0x23 2 0x80 0x34
+ 0x23 2 0x81 0x25
+ 0x23 2 0x82 0x02
+ 0x23 2 0xE0 0x02 /* Page2 */
+ 0x23 2 0x00 0x53
+ /* GIP_L Pin mapping RESET_EVEN */
+ 0x23 2 0x01 0x55 /* VSSG_EVEN */
+ 0x23 2 0x02 0x55 /* VSSA_EVEN */
+ 0x23 2 0x03 0x51 /* STV2_EVEN */
+ 0x23 2 0x04 0x77 /* VDD2_EVEN */
+ 0x23 2 0x05 0x57 /* VDD1_EVEN */
+ 0x23 2 0x06 0x1F
+ 0x23 2 0x07 0x4F /* CK12 */
+ 0x23 2 0x08 0x4D /* CK10 */
+ 0x23 2 0x09 0x1F
+ 0x23 2 0x0A 0x4B /* CK8 */
+ 0x23 2 0x0B 0x49 /* CK6 */
+ 0x23 2 0x0C 0x1F
+ 0x23 2 0x0D 0x47 /* CK4 */
+ 0x23 2 0x0E 0x45 /* CK2 */
+ 0x23 2 0x0F 0x41 /* STV1_EVEN */
+ 0x23 2 0x10 0x1F
+ 0x23 2 0x11 0x1F
+ 0x23 2 0x12 0x1F
+ 0x23 2 0x13 0x55 /* VGG */
+ 0x23 2 0x14 0x1F
+ 0x23 2 0x15 0x1F
+ 0x23 2 0x16 0x52
+ /* GIP_R Pin mapping RESET_ODD */
+ 0x23 2 0x17 0x55 /* VSSG_ODD */
+ 0x23 2 0x18 0x55 /* VSSA_ODD */
+ 0x23 2 0x19 0x50 /* STV2_ODD */
+ 0x23 2 0x1A 0x77 /* VDD2_ODD */
+ 0x23 2 0x1B 0x57 /* VDD1_ODD */
+ 0x23 2 0x1C 0x1F
+ 0x23 2 0x1D 0x4E /* CK11 */
+ 0x23 2 0x1E 0x4C /* CK9 */
+ 0x23 2 0x1F 0x1F
+ 0x23 2 0x20 0x4A /* CK7 */
+ 0x23 2 0x21 0x48 /* CK5 */
+ 0x23 2 0x22 0x1F
+ 0x23 2 0x23 0x46 /* CK3 */
+ 0x23 2 0x24 0x44 /* CK1 */
+ 0x23 2 0x25 0x40 /* STV1_ODD */
+ 0x23 2 0x26 0x1F
+ 0x23 2 0x27 0x1F
+ 0x23 2 0x28 0x1F
+ 0x23 2 0x29 0x1F
+ 0x23 2 0x2A 0x1F
+ 0x23 2 0x2B 0x55 /* VGG */
+ 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping */
+ 0x23 2 0x2D 0x15
+ 0x23 2 0x2E 0x15
+ 0x23 2 0x2F 0x00
+ 0x23 2 0x30 0x37
+ 0x23 2 0x31 0x17
+ 0x23 2 0x32 0x1F
+ 0x23 2 0x33 0x08
+ 0x23 2 0x34 0x0A
+ 0x23 2 0x35 0x1F
+ 0x23 2 0x36 0x0C
+ 0x23 2 0x37 0x0E
+ 0x23 2 0x38 0x1F
+ 0x23 2 0x39 0x04
+ 0x23 2 0x3A 0x06
+ 0x23 2 0x3B 0x10
+ 0x23 2 0x3C 0x1F
+ 0x23 2 0x3D 0x1F
+ 0x23 2 0x3E 0x1F
+ 0x23 2 0x3F 0x15
+ 0x23 2 0x40 0x1F
+ 0x23 2 0x41 0x1F
+ 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping */
+ 0x23 2 0x43 0x15
+ 0x23 2 0x44 0x15
+ 0x23 2 0x45 0x01
+ 0x23 2 0x46 0x37
+ 0x23 2 0x47 0x17
+ 0x23 2 0x48 0x1F
+ 0x23 2 0x49 0x09
+ 0x23 2 0x4A 0x0B
+ 0x23 2 0x4B 0x1F
+ 0x23 2 0x4C 0x0D
+ 0x23 2 0x4D 0x0F
+ 0x23 2 0x4E 0x1F
+ 0x23 2 0x4F 0x05
+ 0x23 2 0x50 0x07
+ 0x23 2 0x51 0x11
+ 0x23 2 0x52 0x1F
+ 0x23 2 0x53 0x1F
+ 0x23 2 0x54 0x1F
+ 0x23 2 0x55 0x1F
+ 0x23 2 0x56 0x1F
+ 0x23 2 0x57 0x15
+ 0x23 2 0x58 0x40 /* GIP Timing */
+ 0x23 2 0x59 0x00
+ 0x23 2 0x5A 0x00
+ 0x23 2 0x5B 0x10
+ 0x23 2 0x5C 0x14
+ 0x23 2 0x5D 0x40
+ 0x23 2 0x5E 0x01
+ 0x23 2 0x5F 0x02
+ 0x23 2 0x60 0x40
+ 0x23 2 0x61 0x03
+ 0x23 2 0x62 0x04
+ 0x23 2 0x63 0x7A
+ 0x23 2 0x64 0x7A
+ 0x23 2 0x65 0x74
+ 0x23 2 0x66 0x16
+ 0x23 2 0x67 0xB4
+ 0x23 2 0x68 0x16
+ 0x23 2 0x69 0x7A
+ 0x23 2 0x6A 0x7A
+ 0x23 2 0x6B 0x0C
+ 0x23 2 0x6C 0x00
+ 0x23 2 0x6D 0x04
+ 0x23 2 0x6E 0x04
+ 0x23 2 0x6F 0x88
+ 0x23 2 0x70 0x00
+ 0x23 2 0x71 0x00
+ 0x23 2 0x72 0x06
+ 0x23 2 0x73 0x7B
+ 0x23 2 0x74 0x00
+ 0x23 2 0x75 0xBC
+ 0x23 2 0x76 0x00
+ 0x23 2 0x77 0x04
+ 0x23 2 0x78 0x2C
+ 0x23 2 0x79 0x00
+ 0x23 2 0x7A 0x00
+ 0x23 2 0x7B 0x00
+ 0x23 2 0x7C 0x00
+ 0x23 2 0x7D 0x03
+ 0x23 2 0x7E 0x7B
+ 0x23 2 0xE0 0x04 /* Page4 */
+ 0x23 2 0x09 0x11 /* Set RGBCYC2 */
+ 0x23 2 0x0E 0x48
+ 0x23 2 0x2B 0x2B /* ESD Protect */
+ 0x23 2 0x2E 0x44
+ 0x23 2 0xE0 0x00 /* Page0 */
+ 0x23 2 0xE6 0x02 /* Watch dog */
+ 0x23 2 0xE7 0x0C
+ 0x05 1 0x11 /* sleep out */
+ 0xfd 1 120
+ 0x05 1 0x29 /* display on */
+ 0x05 1 0x35
+ 0xfd 1 20 /* delay(ms) */
+ 0xFF 0>; /*ending*/
+ init_off = <
+ 0x05 1 0x28 /* display off */
+ 0xfd 1 10 /* delay 10ms */
+ 0x05 1 0x10 /* sleep in */
+ 0xfd 1 150 /* delay 150ms */
+ 0xff 0>; /*ending*/
+ };
+
+ extern_3{
+ index = <3>;
+ extern_name = "mipi_default";/*TL050FHV02CT*/
+ status = "okay";
+ type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+ cmd_size = <0xff>;
+ init_on = <
+ 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03
+ 0x29 10 0x90 0x03 0x14 0x09 0x00 0x00
+ 0x00 0x38 0x00 0x00
+ 0x29 10 0x91 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00
+ 0x29 12 0x92 0x40 0x0B 0x0C 0x0D 0x0E
+ 0x00 0x38 0x00 0x10 0x03 0x04
+ 0x29 9 0x94 0x00 0x08 0x0B 0x03 0xD2
+ 0x03 0xD3 0x0C
+ 0x29 17 0x95 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00
+ 0x29 3 0x99 0x00 0x00
+ 0x29 12 0x9A 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x29 7 0x9B 0x01 0x38 0x00 0x00 0x00 0x00
+ 0x29 3 0x9C 0x00 0x00
+ 0x29 9 0x9D 0x10 0x10 0x10 0x10 0x10
+ 0x10 0x00 0x00
+ 0x29 3 0x9E 0x00 0x00
+ 0x29 11 0xA0 0x9F 0x1F 0x08 0x1F 0x0A
+ 0x1F 0x00 0x1F 0x14 0x1F
+ 0x29 11 0xA1 0x15 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA2 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA4 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA5 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x15
+ 0x29 11 0xA6 0x1F 0x14 0x1F 0x01 0x1F
+ 0x0B 0x1F 0x09 0x1F 0x1F
+ 0x29 11 0xA7 0x1F 0x1F 0x0B 0x1F 0x09
+ 0x1F 0x01 0x1F 0x15 0x1F
+ 0x29 11 0xA8 0x14 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA9 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xAB 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xAC 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x14
+ 0x29 11 0xAD 0x1F 0x15 0x1F 0x00 0x1F
+ 0x08 0x1F 0x0A 0x1F 0x1F
+ 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00
+ 0x29 4 0xBC 0x00 0x00 0x00
+ 0x29 5 0xB8 0x01 0xAF 0x8F 0x8F
+ 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01
+ 0x29 17 0xD1 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xD2 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xD3 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xD4 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xD5 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xD6 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xD7 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xD8 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xD9 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xDD 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xDE 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xDF 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xE0 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xE1 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xE2 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xE3 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xE4 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xE5 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xE6 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xE7 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xE8 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xE9 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xEA 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xEB 0x03 0xC5 0x03 0xFF
+ 0x29 4 0xB0 0x05 0x05 0x05
+ 0x29 4 0xB1 0x05 0x05 0x05
+ 0x29 4 0xB3 0x10 0x10 0x10
+ 0x29 4 0xB4 0x06 0x06 0x06
+ 0x29 4 0xB6 0x44 0x44 0x44
+ 0x29 4 0xB7 0x34 0x34 0x34
+ 0x29 4 0xB8 0x34 0x34 0x34
+ 0x29 4 0xB9 0x24 0x24 0x24
+ 0x29 4 0xBA 0x24 0x24 0x24
+ 0x29 4 0xBC 0x00 0x70 0x00
+ 0x29 4 0xBD 0x00 0x70 0x00
+ 0x23 2 0xBE 0x50
+ 0x23 2 0x35 0x00
+ 0x13 1 0x11
+ 0xfd 1 200
+ 0x13 1 0x29
+ 0xfd 1 200
+ 0xFF 0>; /*ending*/
+ init_off = <
+ 0x05 1 0x28 /* display off */
+ 0xfd 1 10 /* delay 10ms */
+ 0x05 1 0x10 /* sleep in */
+ 0xfd 1 150 /* delay 150ms */
+ 0xff 0>; /*ending*/
+ };
+ };
+
+ backlight{
+ compatible = "amlogic, backlight-g12a";
+ status = "okay";
+ key_valid = <0>;
+ pinctrl-names = "pwm_on","pwm_off";
+ /* pinctrl-0 = <&pwm_f_pins2>; */
+ /* pinctrl-1 = <&bl_pwm_off_pins>; */
+ pinctrl_version = <2>; /* for uboot */
+ bl_pwm_config = <&bl_pwm_conf>;
+ /*bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH
+ &gpio GPIOH_5 GPIO_ACTIVE_HIGH>;*/
+ bl_gpio_names = "GPIOH_4","GPIOH_5";
+
+ /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/
+ /* power index:(point gpios_index, 0xff=invalid)
+ * power value:(0=output low, 1=output high, 2=input)
+ * power delay:(unit in ms)
+ */
+
+ backlight_0{
+ index = <0>;
+ bl_name = "backlight_pwm";
+ bl_level_default_uboot_kernel = <100 100>;
+ bl_level_attr = <255 10 /*max, min*/
+ 128 128>; /*mid, mid_mapping*/
+ bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */
+ bl_power_attr = <0 /*en_gpio_index*/
+ 1 0 /*on_value, off_value*/
+ 200 200>; /*on_delay(ms), off_delay(ms)*/
+ bl_pwm_port = "PWM_F";
+ bl_pwm_attr = <0 /*pwm_method*/
+ 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/
+ 100 25>; /*duty_max(%), duty_min(%)*/
+ bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/
+ 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/
+ bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */
+ };
+ backlight_1{
+ index = <1>;
+ bl_name = "bl_extern";
+ bl_level_default_uboot_kernel = <100 100>;
+ bl_level_attr = <255 10 /*max, min*/
+ 128 128>; /*mid, mid_mapping*/
+ bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/
+ bl_power_attr = <1 /*en_gpio_index*/
+ 1 0 /*on_value, off_value*/
+ 200 200>; /*on_delay(ms), off_delay(ms)*/
+ bl_extern_index = <0>;
+ };
+ };
+ bl_pwm_conf:bl_pwm_conf{
+ pwm_channel_0 {
+ pwm_port_index = <5>;
+ pwms = <&pwm_ef MESON_PWM_1 30040 0>;
+ };
+ };
+
+ bl_extern{
+ compatible = "amlogic, bl_extern";
+ status = "disabled";
+ i2c_bus = "i2c_bus_3";
+
+ extern_0{
+ index = <0>;
+ extern_name = "i2c_lp8556";
+ type = <0>; /*0=i2c, 1=spi, 2=mipi*/
+ i2c_address = <0x2c>; /*7bit i2c address*/
+ dim_max_min = <255 10>;
+ };
+
+ extern_1{
+ index = <1>;
+ extern_name = "mipi_lt070me05";
+ type = <2>; /*0=i2c, 1=spi, 2=mipi*/
+ dim_max_min = <255 10>;
+ };
+ };
+};/* end of panel */
+
diff --git a/arch/arm/dts/meson-sm1-s905d3-ac200.dts b/arch/arm/dts/meson-sm1-s905d3-ac200.dts
new file mode 100644
index 0000000..a891205
--- /dev/null
+++ b/arch/arm/dts/meson-sm1-s905d3-ac200.dts
@@ -0,0 +1,79 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-sm1-s905d3-ac200.dtsi"
+#include "meson-g12a_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,u200", "amlogic,s905d2", "amlogic,meson-g12a";
+ model = "Amlogic Meson G12A (S905D2) U200 Development Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_AO {
+ status = "okay";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3_master_pins2>;
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-sm1-s905d3-ac200.dtsi b/arch/arm/dts/meson-sm1-s905d3-ac200.dtsi
new file mode 100755
index 0000000..839642b
--- /dev/null
+++ b/arch/arm/dts/meson-sm1-s905d3-ac200.dtsi
@@ -0,0 +1,291 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-g12a-s905d2.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_AO;
+ serial1 = &uart_A;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c_AO;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "okay";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /* pinctrl-0 = <&sdio_pins>; */
+ /* pinctrl-names = "default"; */
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+
+ pinname = "sdio";
+ card_type = <3>;
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sd_all_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ pinname = "sd";
+ card_type = <5>;
+ init_co_phase = <3>;
+ init_tx_phase = <0>;
+ sd_hs_co_phase = <2>;
+ sd_hs_tx_phase = <0>;
+ sdr104_co_phase = <2>;
+ sdr104_hs_tx_phase = <0>;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ /* cd-inverted; */
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_conf_pull_up &emmc_conf_pull_done>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-sd-highspeed;
+ cap-mmc-highspeed;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ mmc-hs200-1_8v;
+
+ pinname = "emmc";
+ card_type = <1>;
+ init_co_phase = <3>;
+ init_tx_phase = <0>;
+ hs_co_phase = <3>;
+ hs_tx_phase = <0>;
+ ddr_co_phase = <2>;
+ ddr_tx_phase = <0>;
+ hs2_co_phase = <3>;
+ hs2_tx_phase = <0>;
+
+ hw_reset = <&gpio BOOT_12 GPIO_ACTIVE_HIGH>;
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_all_pins", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&all_nand_pins>;
+ pinctrl-2 = <&nand_cs_pins>;
+
+ /*
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ nand@0 {
+ reg = <0>;
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ nand-on-flash-bbt;
+ nand-ecc-mode = "hw";
+ nand-ecc-strength = <8>;
+ nand-ecc-step-size = <1024>;
+
+ meson-nand-user-mode = <2>;
+ meson-nand-ran-mode = <1>;
+
+ partition@0 {
+ label = "boot";
+ reg = <0x00000000 0x00200000>;
+ read-only;
+ };
+ partition@200000 {
+ label = "env";
+ reg = <0x00200000 0x00400000>;
+ };
+ partition@600000 {
+ label = "system";
+ reg = <0x00600000 0x00a00000>;
+ };
+ partition@1000000 {
+ label = "rootfs";
+ reg = <0x01000000 0x03000000>;
+ };
+ partition@4000000 {
+ label = "media";
+ reg = <0x04000000 0x8000000>;
+ };
+ };*/
+
+};
+
+&dwc3 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <2>;
+ dwc2_a_reg = <0xff400000>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOH_6";
+ gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ pinctrl-names = "default";
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_A {
+ status = "okay";
+ pinctrl-0 = <&a_uart_pins>;
+ pinctrl-names = "default";
+ uart-has-rtscts;
+};
+
+&uart_AO {
+ status = "okay";
+ pinctrl-0 = <&ao_uart_pins>;
+ pinctrl-names = "default";
+};
+
+&spifc {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spifc_all_pins>;
+ max-frequency = <80000000>;
+ max-io = <4>;
+ max-cs = <2>;
+ cs-gpios = <&gpio BOOT_14 GPIO_ACTIVE_HIGH>;
+ clocks = <&clkc CLKID_CLK81>;
+ clock-names = "core";
+};
+
+&spicc1 {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins>;
+ cs-gpios = <&gpio GPIOH_6 0>;
+};
diff --git a/arch/arm/dts/meson-t7-an400-lpddr4x.dts b/arch/arm/dts/meson-t7-an400-lpddr4x.dts
new file mode 100644
index 0000000..1fb3395
--- /dev/null
+++ b/arch/arm/dts/meson-t7-an400-lpddr4x.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-t7-an400-lpddr4x.dtsi"
+#include "meson-t7_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,t7-an400-lpddr4x", "amlogic,t7-txxx", "amlogic,meson-t7";
+ model = "Amlogic Meson T7 PXP Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "disabled";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-t7-an400-lpddr4x.dtsi b/arch/arm/dts/meson-t7-an400-lpddr4x.dtsi
new file mode 100644
index 0000000..8c45dc1
--- /dev/null
+++ b/arch/arm/dts/meson-t7-an400-lpddr4x.dtsi
@@ -0,0 +1,308 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-t7-txxx.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_a;
+ serial1 = &uart_b;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ spi3 = &spicc2;
+ spi4 = &spicc3;
+ spi5 = &spicc4;
+ spi6 = &spicc5;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c_AO_A;
+ i2c7 = &i2c_AO_B;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ tee: tee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "disabled";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ sd_hs_co_phase = <2>;
+ sd_hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&crg {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&crg2 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOM_8";
+ gpios = <&gpio GPIOM_8 GPIO_ACTIVE_HIGH>;
+};
+
+&usb2_phy2_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy2_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOM_9";
+ gpios = <&gpio GPIOM_9 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_b {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ cs-gpios = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>;
+ spi-flash@0 {
+ status = "okay";
+ };
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins>;
+ cs-gpios = <&gpio GPIOT_21 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins_1>;
+ cs-gpios = <&gpio GPIOC_3 0>;
+};
+
+&spicc2 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc2_pins>;
+ cs-gpios = <&gpio GPIOY_3 0>;
+};
+
+&spicc3 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc3_pins>;
+ cs-gpios = <&gpio GPIOT_9 0>;
+ spi-flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <16000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ status = "disabled";
+ };
+};
+
+&spicc4 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc4_pins>;
+ cs-gpios = <&gpio GPIOZ_3 0>;
+};
+
+&spicc5 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc5_pins>;
+ cs-gpios = <&gpio GPIOZ_7 0>;
+};
diff --git a/arch/arm/dts/meson-t7-an400p-lpddr4x.dts b/arch/arm/dts/meson-t7-an400p-lpddr4x.dts
new file mode 100644
index 0000000..708054c
--- /dev/null
+++ b/arch/arm/dts/meson-t7-an400p-lpddr4x.dts
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-t7-an400p-lpddr4x.dtsi"
+#include "meson-t7_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,t7-an400p-lpddr4x", "amlogic,t7-txxx", "amlogic,meson-t7";
+ model = "Amlogic Meson T7 PXP Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "disabled";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&i2c_AO_A {
+ status= "okay";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_ao_pins1>;
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-t7-an400p-lpddr4x.dtsi b/arch/arm/dts/meson-t7-an400p-lpddr4x.dtsi
new file mode 100644
index 0000000..26abb32
--- /dev/null
+++ b/arch/arm/dts/meson-t7-an400p-lpddr4x.dtsi
@@ -0,0 +1,312 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-t7-txxx.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_a;
+ serial1 = &uart_b;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ spi3 = &spicc2;
+ spi4 = &spicc3;
+ spi5 = &spicc4;
+ spi6 = &spicc5;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c_AO_A;
+ i2c7 = &i2c_AO_B;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ tee: tee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+/*exphy setting*/
+// pinctrl-names = "external_eth_rgmii_pins";
+// pinctrl-0 = <&external_eth_rgmii_pins>;
+// internal_phy = <0>;
+// mc_val = <0x1601>;
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "disabled";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ sd_hs_co_phase = <2>;
+ sd_hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&crg {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&crg2 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOM_8";
+ gpios = <&gpio GPIOM_8 GPIO_ACTIVE_HIGH>;
+};
+
+&usb2_phy2_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy2_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOM_9";
+ gpios = <&gpio GPIOM_9 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_b {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ cs-gpios = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>;
+ spi-flash@0 {
+ status = "okay";
+ };
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins>;
+ cs-gpios = <&gpio GPIOT_21 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins_1>;
+ cs-gpios = <&gpio GPIOC_3 0>;
+};
+
+&spicc2 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc2_pins>;
+ cs-gpios = <&gpio GPIOY_3 0>;
+};
+
+&spicc3 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc3_pins>;
+ cs-gpios = <&gpio GPIOT_9 0>;
+ spi-flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <16000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ status = "disabled";
+ };
+};
+
+&spicc4 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc4_pins>;
+ cs-gpios = <&gpio GPIOZ_3 0>;
+};
+
+&spicc5 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc5_pins>;
+ cs-gpios = <&gpio GPIOZ_7 0>;
+};
diff --git a/arch/arm/dts/meson-t7-an408-lpddr4x.dts b/arch/arm/dts/meson-t7-an408-lpddr4x.dts
new file mode 100644
index 0000000..2bc36d3
--- /dev/null
+++ b/arch/arm/dts/meson-t7-an408-lpddr4x.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-t7-an408-lpddr4x.dtsi"
+#include "meson-t7_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,t7-an408-lpddr4x", "amlogic,t7-txxx", "amlogic,meson-t7";
+ model = "Amlogic Meson T7 PXP Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "disabled";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-t7-an408-lpddr4x.dtsi b/arch/arm/dts/meson-t7-an408-lpddr4x.dtsi
new file mode 100644
index 0000000..8c45dc1
--- /dev/null
+++ b/arch/arm/dts/meson-t7-an408-lpddr4x.dtsi
@@ -0,0 +1,308 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-t7-txxx.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_a;
+ serial1 = &uart_b;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ spi3 = &spicc2;
+ spi4 = &spicc3;
+ spi5 = &spicc4;
+ spi6 = &spicc5;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c_AO_A;
+ i2c7 = &i2c_AO_B;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ tee: tee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "disabled";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ sd_hs_co_phase = <2>;
+ sd_hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&crg {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&crg2 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOM_8";
+ gpios = <&gpio GPIOM_8 GPIO_ACTIVE_HIGH>;
+};
+
+&usb2_phy2_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy2_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOM_9";
+ gpios = <&gpio GPIOM_9 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_b {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ cs-gpios = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>;
+ spi-flash@0 {
+ status = "okay";
+ };
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins>;
+ cs-gpios = <&gpio GPIOT_21 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins_1>;
+ cs-gpios = <&gpio GPIOC_3 0>;
+};
+
+&spicc2 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc2_pins>;
+ cs-gpios = <&gpio GPIOY_3 0>;
+};
+
+&spicc3 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc3_pins>;
+ cs-gpios = <&gpio GPIOT_9 0>;
+ spi-flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <16000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ status = "disabled";
+ };
+};
+
+&spicc4 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc4_pins>;
+ cs-gpios = <&gpio GPIOZ_3 0>;
+};
+
+&spicc5 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc5_pins>;
+ cs-gpios = <&gpio GPIOZ_7 0>;
+};
diff --git a/arch/arm/dts/meson-t7-an409-ddr4.dts b/arch/arm/dts/meson-t7-an409-ddr4.dts
new file mode 100644
index 0000000..1e3e0c8
--- /dev/null
+++ b/arch/arm/dts/meson-t7-an409-ddr4.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-t7-an409-ddr4.dtsi"
+#include "meson-t7_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,t7-an409-ddr4", "amlogic,t7-txxx", "amlogic,meson-t7";
+ model = "Amlogic Meson T7 PXP Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "disabled";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-t7-an409-ddr4.dtsi b/arch/arm/dts/meson-t7-an409-ddr4.dtsi
new file mode 100644
index 0000000..8c45dc1
--- /dev/null
+++ b/arch/arm/dts/meson-t7-an409-ddr4.dtsi
@@ -0,0 +1,308 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-t7-txxx.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_a;
+ serial1 = &uart_b;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ spi3 = &spicc2;
+ spi4 = &spicc3;
+ spi5 = &spicc4;
+ spi6 = &spicc5;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c_AO_A;
+ i2c7 = &i2c_AO_B;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ tee: tee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "disabled";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ sd_hs_co_phase = <2>;
+ sd_hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&crg {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&crg2 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOM_8";
+ gpios = <&gpio GPIOM_8 GPIO_ACTIVE_HIGH>;
+};
+
+&usb2_phy2_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy2_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOM_9";
+ gpios = <&gpio GPIOM_9 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_b {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ cs-gpios = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>;
+ spi-flash@0 {
+ status = "okay";
+ };
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins>;
+ cs-gpios = <&gpio GPIOT_21 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins_1>;
+ cs-gpios = <&gpio GPIOC_3 0>;
+};
+
+&spicc2 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc2_pins>;
+ cs-gpios = <&gpio GPIOY_3 0>;
+};
+
+&spicc3 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc3_pins>;
+ cs-gpios = <&gpio GPIOT_9 0>;
+ spi-flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <16000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ status = "disabled";
+ };
+};
+
+&spicc4 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc4_pins>;
+ cs-gpios = <&gpio GPIOZ_3 0>;
+};
+
+&spicc5 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc5_pins>;
+ cs-gpios = <&gpio GPIOZ_7 0>;
+};
diff --git a/arch/arm/dts/meson-t7-an40a1.dts b/arch/arm/dts/meson-t7-an40a1.dts
new file mode 100644
index 0000000..909ccf9
--- /dev/null
+++ b/arch/arm/dts/meson-t7-an40a1.dts
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-t7-an40a1.dtsi"
+#include "meson-t7_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,t7-an40a1", "amlogic,t7-txxx", "amlogic,meson-t7";
+ model = "Amlogic Meson T7 PXP Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "disabled";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&i2c_AO_A {
+ status= "okay";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_ao_pins1>;
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-t7-an40a1.dtsi b/arch/arm/dts/meson-t7-an40a1.dtsi
new file mode 100644
index 0000000..3fb3cb1
--- /dev/null
+++ b/arch/arm/dts/meson-t7-an40a1.dtsi
@@ -0,0 +1,308 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-t7-txxx.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_a;
+ serial1 = &uart_b;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ spi3 = &spicc2;
+ spi4 = &spicc3;
+ spi5 = &spicc4;
+ spi6 = &spicc5;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c_AO_A;
+ i2c7 = &i2c_AO_B;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ tee: tee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "disabled";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ sd_hs_co_phase = <2>;
+ sd_hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&crg {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&crg2 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOM_8";
+ gpios = <&gpio GPIOM_8 GPIO_ACTIVE_HIGH>;
+};
+
+&usb2_phy2_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy2_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOM_9";
+ gpios = <&gpio GPIOM_9 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_b {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "disabled";
+ //cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>;
+ spi-flash@0 {
+ status = "disabled";
+ };
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins>;
+ cs-gpios = <&gpio GPIOT_21 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins_1>;
+ cs-gpios = <&gpio GPIOC_3 0>;
+};
+
+&spicc2 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc2_pins>;
+ cs-gpios = <&gpio GPIOY_3 0>;
+};
+
+&spicc3 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc3_pins>;
+ cs-gpios = <&gpio GPIOT_9 0>;
+ spi-flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <16000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ status = "disabled";
+ };
+};
+
+&spicc4 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc4_pins>;
+ cs-gpios = <&gpio GPIOZ_3 0>;
+};
+
+&spicc5 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc5_pins>;
+ cs-gpios = <&gpio GPIOZ_7 0>;
+};
diff --git a/arch/arm/dts/meson-t7-mali.dtsi b/arch/arm/dts/meson-t7-mali.dtsi
new file mode 100644
index 0000000..2655b42
--- /dev/null
+++ b/arch/arm/dts/meson-t7-mali.dtsi
@@ -0,0 +1,43 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2017 BayLibre SAS
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+&apb {
+ mali: gpu@40000 {
+ compatible = "amlogic,meson-gxbb-mali", "arm,mali-450";
+ reg = <0x0 0x40000 0x0 0x40000>;
+ interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "gp", "gpmmu", "pp", "pmu",
+ "pp0", "ppmmu0", "pp1", "ppmmu1",
+ "pp2", "ppmmu2";
+ /*clocks = <&clkc CLKID_CLK81>, <&clkc CLKID_MALI>;*/
+ clock-names = "bus", "core";
+
+ /*
+ * Mali clocking is provided by two identical clock paths
+ * MALI_0 and MALI_1 muxed to a single clock by a glitch
+ * free mux to safely change frequency while running.
+ */
+ /*
+ assigned-clocks = <&clkc CLKID_MALI_0_SEL>,
+ <&clkc CLKID_MALI_0>,
+ <&clkc CLKID_MALI>; *//* Glitch free mux */
+ /*assigned-clock-parents = <&clkc CLKID_FCLK_DIV3>,
+ <0>, *//* Do Nothing */
+ //<&clkc CLKID_MALI_0>;
+ /*assigned-clock-rates = <0>,*/ /* Do Nothing */
+ /* <666666666>,
+ <0>;*/ /* Do Nothing */
+ };
+};
diff --git a/arch/arm/dts/meson-t7-pxp.dts b/arch/arm/dts/meson-t7-pxp.dts
new file mode 100644
index 0000000..35b7ec0
--- /dev/null
+++ b/arch/arm/dts/meson-t7-pxp.dts
@@ -0,0 +1,83 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-t7-pxp.dtsi"
+#include "meson-t7_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,t7-pxp", "amlogic,t7-txxx", "amlogic,meson-t7";
+ model = "Amlogic Meson T7 PXP Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "disabled";
+};
+
+&saradc {
+ status = "disabled";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-t7-pxp.dtsi b/arch/arm/dts/meson-t7-pxp.dtsi
new file mode 100644
index 0000000..a1142bd
--- /dev/null
+++ b/arch/arm/dts/meson-t7-pxp.dtsi
@@ -0,0 +1,303 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-t7-txxx.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_a;
+ serial1 = &uart_b;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ spi3 = &spicc2;
+ spi4 = &spicc3;
+ spi5 = &spicc4;
+ spi6 = &spicc5;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c_AO_A;
+ i2c7 = &i2c_AO_B;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_9 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "disabled";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ sd_hs_co_phase = <2>;
+ sd_hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+// mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_9 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&crg {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&crg2 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOM_8";
+ gpios = <&gpio GPIOM_8 GPIO_ACTIVE_HIGH>;
+};
+
+&usb2_phy2_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy2_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOM_9";
+ gpios = <&gpio GPIOM_9 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_b {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "disabled";
+ //cs-gpios = <&gpio GPIOB_14 GPIO_ACTIVE_HIGH>;
+ spi-flash@0 {
+ status = "disabled";
+ };
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins>;
+ cs-gpios = <&gpio GPIOT_21 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins_1>;
+ cs-gpios = <&gpio GPIOC_3 0>;
+};
+
+&spicc2 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc2_pins>;
+ cs-gpios = <&gpio GPIOY_3 0>;
+};
+
+&spicc3 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc3_pins>;
+ cs-gpios = <&gpio GPIOT_9 0>;
+ spi-flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <16000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ status = "disabled";
+ };
+};
+
+&spicc4 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc4_pins>;
+ cs-gpios = <&gpio GPIOZ_3 0>;
+};
+
+&spicc5 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc5_pins>;
+ cs-gpios = <&gpio GPIOZ_7 0>;
+};
diff --git a/arch/arm/dts/meson-t7-series.dtsi b/arch/arm/dts/meson-t7-series.dtsi
new file mode 100644
index 0000000..c63a2ed
--- /dev/null
+++ b/arch/arm/dts/meson-t7-series.dtsi
@@ -0,0 +1,601 @@
+/*
+ * Copyright (c) 2016 Andreas Färber
+ *
+ * Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ *
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pwm/meson.h>
+#include <dt-bindings/clock/t7-clkc.h>
+
+/ {
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ reserved-memory {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ /* 16 MiB reserved for Hardware ROM Firmware */
+ hwrom_reserved: hwrom@0 {
+ reg = <0x0 0x0 0x0 0x1000000>;
+ no-map;
+ };
+
+ /* 2 MiB reserved for ARM Trusted Firmware (BL31) */
+ secmon_reserved: secmon@10000000 {
+ reg = <0x0 0x10000000 0x0 0x200000>;
+ no-map;
+ };
+
+ linux,cma {
+ compatible = "shared-dma-pool";
+ reusable;
+ size = <0x0 0xbc00000>;
+ alignment = <0x0 0x400000>;
+ linux,cma-default;
+ };
+ };
+
+ cpus {
+ #address-cells = <0x2>;
+ #size-cells = <0x0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x0>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ cpu1: cpu@1 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x1>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ cpu2: cpu@2 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x2>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ cpu3: cpu@3 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a53", "arm,armv8";
+ reg = <0x0 0x3>;
+ enable-method = "psci";
+ next-level-cache = <&l2>;
+ clocks = <&scpi_dvfs 0>;
+ };
+
+ l2: l2-cache0 {
+ compatible = "cache";
+ };
+ };
+
+ arm-pmu {
+ compatible = "arm,cortex-a53-pmu";
+ interrupts = <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
+ };
+
+ psci {
+ compatible = "arm,psci-0.2";
+ method = "smc";
+ };
+
+ timer {
+ compatible = "arm,armv8-timer";
+ interrupts = <GIC_PPI 13
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 14
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 11
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>,
+ <GIC_PPI 10
+ (GIC_CPU_MASK_RAW(0xff) | IRQ_TYPE_LEVEL_LOW)>;
+ };
+
+ xtal: xtal-clk {
+ compatible = "fixed-clock";
+ clock-frequency = <24000000>;
+ clock-output-names = "xtal";
+ #clock-cells = <0>;
+ };
+
+ firmware {
+ sm: secure-monitor {
+ compatible = "amlogic,meson-gx-sm", "amlogic,meson-gxbb-sm";
+ };
+ };
+
+ efuse: efuse {
+ compatible = "amlogic,meson-sc2-efuse", "amlogic,meson-sc2-efuse";
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ };
+
+ scpi {
+ compatible = "amlogic,meson-gxbb-scpi", "arm,scpi-pre-1.0";
+ mboxes = <&mailbox 1 &mailbox 2>;
+ shmem = <&cpu_scp_lpri &cpu_scp_hpri>;
+
+ scpi_clocks: clocks {
+ compatible = "arm,scpi-clocks";
+
+ scpi_dvfs: scpi_clocks@0 {
+ compatible = "arm,scpi-dvfs-clocks";
+ #clock-cells = <1>;
+ clock-indices = <0>;
+ clock-output-names = "vcpu";
+ };
+ };
+
+ scpi_sensors: sensors {
+ compatible = "amlogic,meson-gxbb-scpi-sensors", "arm,scpi-sensors";
+ #thermal-sensor-cells = <1>;
+ };
+ };
+
+ soc {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gic: interrupt-controller@2c001000 {
+ compatible = "arm,gic-400";
+ reg = <0x0 0xffc01000 0 0x1000>,
+ <0x0 0xffc02000 0 0x2000>,
+ <0x0 0xffc04000 0 0x2000>,
+ <0x0 0xffc06000 0 0x2000>;
+ interrupt-controller;
+ interrupts = <GIC_PPI 9
+ (GIC_CPU_MASK_SIMPLE(8) | IRQ_TYPE_LEVEL_HIGH)>;
+ #interrupt-cells = <3>;
+ #address-cells = <0>;
+ };
+
+ sram: sram@f7000000 {
+ compatible = "amlogic,meson-sc2-sram", "amlogic,meson-sc2-sram", "mmio-sram";
+ reg = <0x0 0xf7000000 0x0 0x48000>;
+
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0x0 0xf7000000 0x48000>;
+
+ cpu_scp_lpri: scp-shmem@0 {
+ compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
+ reg = <0x47000 0x400>;
+ };
+
+ cpu_scp_hpri: scp-shmem@200 {
+ compatible = "amlogic,meson-gx-scp-shmem", "amlogic,meson-gxbb-scp-shmem";
+ reg = <0x47400 0x400>;
+ };
+ };
+
+ cbus: cbus@fe070000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xfe070000 0x0 0xF000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xfe070000 0x0 0xF000>;
+
+ uart_a: serial@8000 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x8000 0x0 0x18>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ uart_b: serial@a000 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0xa000 0x0 0x18>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ ir: ir@8040 {
+ compatible = "amlogic,meson-gx-ir", "amlogic,meson-gxbb-ir";
+ reg = <0x0 0x8040 0x0 0x40>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ };
+
+ reset: reset-controller@1000 {
+ compatible = "amlogic,meson-gx-reset", "amlogic,meson-gxbb-reset";
+ reg = <0x0 0x01000 0x0 0x1000>;
+ #reset-cells = <1>;
+ };
+
+ uart_c: serial@22000 {
+ compatible = "amlogic,meson-uart";
+ reg = <0x0 0x22000 0x0 0x18>;
+ interrupts = <GIC_SPI 93 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&xtal>;
+ status = "disabled";
+ };
+
+ jtag {
+ compatible = "amlogic, jtag";
+ status = "okay";
+ select = "disable"; /* disable/jtag-a/jtag-b */
+ pinctrl-names="jtag_a_pins", "jtag_b_pins";
+ pinctrl-0=<&jtag_a_pins>;
+ pinctrl-1=<&jtag_b_pins>;
+ };
+ };
+
+ periphs: periphs@ff634000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xff634000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xff634000 0x0 0x2000>;
+
+ hwrng: rng {
+ compatible = "amlogic,meson-rng";
+ reg = <0x0 0x0 0x0 0x4>;
+ };
+ };
+
+ hiubus: hiubus@ff63c000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xff63c000 0x0 0x2000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xff63c000 0x0 0x2000>;
+
+ mailbox: mailbox@404 {
+ compatible = "amlogic,meson-gx-mhu", "amlogic,meson-gxbb-mhu";
+ reg = <0 0x404 0 0x4c>;
+ interrupts = <0 208 IRQ_TYPE_EDGE_RISING>,
+ <0 209 IRQ_TYPE_EDGE_RISING>,
+ <0 210 IRQ_TYPE_EDGE_RISING>;
+ #mbox-cells = <1>;
+ };
+ };
+
+ clkc: clock-controller@0 {
+ compatible = "amlogic,t7-clkc";
+ #clock-cells = <1>;
+ reg = <0x0 0xfe000000 0x0 0x82e8>;
+ clocks = <&xtal>;
+ clock-names = "xtal";
+ };
+
+ i2c0: i2c@fe001400 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe066000 0x0 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c1: i2c@fe005c00 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe068000 0x0 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@fe006800 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe06a000 0x0 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@fe006c00 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe06c000 0x0 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@fe06e000 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe06e000 0x0 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c5: i2c@fe070000 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe070000 0x0 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c_AO_A: i2c@fe076000 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe076000 0x0 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c_AO_B: i2c@fe086000 {
+ compatible = "amlogic,meson-i2c";
+ reg = <0x0 0xfe086000 0x0 0x24>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spifc: spi@fe056000 {
+ compatible = "amlogic,spifc";
+ status = "disabled";
+ reg = <0x0 0xfe056000 0x0 0x80>;
+ /* clocks = <&clkc CLKID_CLK81>; */
+ /* clock-names = "core"; */
+ pinctrl-names = "default";
+ pinctrl-0 = <&spifc_pins>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ spi-flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <20000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ status = "disabled";
+ };
+ spi-nand@1 {
+ compatible = "spi-nand";
+ reg = <1>;
+ spi-max-frequency = <20000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ status = "disabled";
+ };
+ };
+
+ ethmac: ethernet@fdc00000 {
+ compatible = "amlogic,g12a-eth-dwmac";
+ phy_cntl1 = <0x41054147>;
+ pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>;
+ analog_val = <0x20200000 0x0000c000 0x00000023>;
+ status = "disabled";
+ };
+
+ saradc: adc@fe026000 {
+ compatible = "amlogic,meson-saradc";
+ reg = <0x0 0xfe026000 0x0 0x48>;
+ status = "disabled";
+ };
+
+ nand: nfc@fe08c800 {
+ compatible = "amlogic,meson-nfc";
+ reg = <0x0 0xfe08c800 0x0 0x200>;
+ interrupts = <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ clk_reg = <0 0xfe08c000>;
+ };
+
+ apb: apb@fe000000 {
+ compatible = "simple-bus";
+ reg = <0x0 0xfe000000 0x0 0x1000000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0x0 0x0 0x0 0xfe000000 0x0 0x1000000>;
+
+ watchdog@2100 {
+ compatible = "amlogic,meson-sc2-wdt";
+ reg = <0x0 0x2100 0x0 0x10>;
+ clocks = <&xtal>;
+ clock-names = "wdt-clk";
+ };
+
+ sd_emmc_a: sdio {
+ compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
+ reg = <0x0 0x88000 0x0 0x800>;
+ interrupts = <GIC_SPI 85 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ pinname = "sdio";
+ };
+
+ sd_emmc_b: sd {
+ compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
+ reg = <0x0 0x8a000 0x0 0x800>;
+ interrupts = <GIC_SPI 86 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ pinname = "sd";
+ };
+
+ sd_emmc_c: emmc {
+ compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
+ reg = <0x0 0x8c000 0x0 0x800>;
+ interrupts = <GIC_SPI 87 IRQ_TYPE_EDGE_RISING>;
+ status = "disabled";
+ pinname = "emmc";
+ source-clock = <1152000000>;
+ };
+
+ spicc0: spi@50000 {
+ compatible = "amlogic,meson-g12a-spicc";
+ reg = <0x0 0x50000 0x0 0x44>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spicc1: spi@52000 {
+ compatible = "amlogic,meson-g12a-spicc";
+ reg = <0x0 0x52000 0x0 0x44>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spicc2: spi@54000 {
+ compatible = "amlogic,meson-g12a-spicc";
+ reg = <0x0 0x54000 0x0 0x44>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spicc3: spi@4a000 {
+ compatible = "amlogic,meson-g12a-spicc";
+ reg = <0x0 0x4a000 0x0 0x44>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spicc4: spi@4c000 {
+ compatible = "amlogic,meson-g12a-spicc";
+ reg = <0x0 0x4c000 0x0 0x44>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ spicc5: spi@4e000 {
+ compatible = "amlogic,meson-g12a-spicc";
+ reg = <0x0 0x4e000 0x0 0x44>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+ };
+
+ crg: crg@fdd00000 {
+ compatible = "crg-xhci";
+ status = "disable";
+ reg = <0x0 0xfdd00000 0x0 0x100000>;
+ phys = <&usb2_phy_v2>, <&usb3_phy_v2>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ crg2: crg@fde00000 {
+ compatible = "crg-xhci";
+ status = "disable";
+ reg = <0x0 0xfde00000 0x0 0x100000>;
+ phys = <&usb2_phy2_v2>, <&usb3_phy2_v2>;
+ phy-names = "usb2-phy", "usb3-phy";
+ };
+
+ usb2_phy_v2: usb2phy@fe03a000 {
+ compatible = "amlogic, amlogic-new-usb2-v2";
+ status = "disable";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ phy-version = <2>;
+ reg = <0x0 0xfe03a000 0x0 0x80
+ 0x0 0xFE002000 0x0 0x100
+ 0x0 0xfe03e000 0x0 0x2000>;
+ dwc2_a_reg = <0xfdd00000>;
+ #phy-cells = <0>;
+ };
+
+ usb3_phy_v2: usb3phy@fe03a080 {
+ compatible = "amlogic, amlogic-new-usb3-v2";
+ status = "disable";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ phy-version = <3>;
+ reg = <0x0 0xfe03a080 0x0 0x20>;
+ phy-reg = <0xfe03c000>;
+ phy-reg-size = <0x2000>;
+ usb2-phy-reg = <0xfe03a000>;
+ usb2-phy-reg-size = <0x80>;
+ #phy-cells = <0>;
+ };
+
+ usb2_phy2_v2: usb2phy2@fe03a000 {
+ compatible = "amlogic, amlogic-new-usb2-v2";
+ status = "disable";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ phy-version = <2>;
+ reg = <0x0 0xfe03a000 0x0 0x80
+ 0x0 0xFE002000 0x0 0x100
+ 0x0 0xfe03c000 0x0 0x2000>;
+ dwc2_a_reg = <0xfdd00000>;
+ #phy-cells = <0>;
+ };
+
+ usb3_phy2_v2: usb3phy2@fe03a080 {
+ compatible = "amlogic, amlogic-new-usb3-v2";
+ status = "disable";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ phy-version = <3>;
+ reg = <0x0 0xfe03a080 0x0 0x20>;
+ phy-reg = <0xfe03c000>;
+ phy-reg-size = <0x2000>;
+ usb2-phy-reg = <0xfe03a000>;
+ usb2-phy-reg-size = <0x80>;
+ #phy-cells = <0>;
+ };
+
+ };
+};
diff --git a/arch/arm/dts/meson-t7-t319.dts b/arch/arm/dts/meson-t7-t319.dts
new file mode 100644
index 0000000..38b4e14
--- /dev/null
+++ b/arch/arm/dts/meson-t7-t319.dts
@@ -0,0 +1,90 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+/dts-v1/;
+
+#include "meson-t7-t319.dtsi"
+#include "meson-t7_skt-panel.dtsi"
+
+/ {
+ compatible = "amlogic,t7-t319", "amlogic,t7-txxx", "amlogic,meson-t7";
+ model = "Amlogic Meson T7 PXP Board";
+};
+
+/* This UART is brought out to the DB9 connector */
+&uart_a {
+ status = "okay";
+};
+
+&uart_b {
+ status = "disabled";
+};
+
+&saradc {
+ status = "okay";
+};
+
+/* demo for i2c user */
+&i2c3 {
+ status= "disabled";
+ clock-frequency = <100000>;
+ /* pinctrl-names = "default";*/
+ /* pinctrl-0 = <&i2c3_master_pins2>;*/
+};
+
+&i2c_AO_A {
+ status= "okay";
+ clock-frequency = <100000>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_ao_pins1>;
+};
+
+&pinctrl_periphs {
+ bl_pwm_off_pins:bl_pwm_off_pin {
+ mux {
+ groups = "GPIOH_5";
+ function = "gpio_periphs";
+ output-high;
+ };
+ };
+}; /* end of pinctrl_periphs */
diff --git a/arch/arm/dts/meson-t7-t319.dtsi b/arch/arm/dts/meson-t7-t319.dtsi
new file mode 100644
index 0000000..8c45dc1
--- /dev/null
+++ b/arch/arm/dts/meson-t7-t319.dtsi
@@ -0,0 +1,308 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2016 Martin Blumenstingl <martin.blumenstingl@googlemail.com>.
+ * Based on meson-gx-p23x-q20x.dtsi:
+ * - Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ * - Copyright (c) 2016 BayLibre, SAS.
+ * Author: Neil Armstrong <narmstrong@baylibre.com>
+ */
+
+/* Common DTSI for devices which are based on the P212 reference board. */
+
+#include "meson-t7-txxx.dtsi"
+
+/ {
+ aliases {
+ serial0 = &uart_a;
+ serial1 = &uart_b;
+ spi0 = &spifc;
+ spi1 = &spicc0;
+ spi2 = &spicc1;
+ spi3 = &spicc2;
+ spi4 = &spicc3;
+ spi5 = &spicc4;
+ spi6 = &spicc5;
+ i2c0 = &i2c0;
+ i2c1 = &i2c1;
+ i2c2 = &i2c2;
+ i2c3 = &i2c3;
+ i2c4 = &i2c4;
+ i2c5 = &i2c5;
+ i2c6 = &i2c_AO_A;
+ i2c7 = &i2c_AO_B;
+ };
+
+ chosen {
+ stdout-path = "serial0:115200n8";
+ };
+
+ memory@0 {
+ device_type = "memory";
+ reg = <0x0 0x0 0x0 0x80000000>;
+ };
+
+ vddio_boot: regulator-vddio_boot {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_BOOT";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vddao_3v3: regulator-vddao_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDAO_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ vddio_ao18: regulator-vddio_ao18 {
+ compatible = "regulator-fixed";
+ regulator-name = "VDDIO_AO18";
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ };
+
+ vcc_3v3: regulator-vcc_3v3 {
+ compatible = "regulator-fixed";
+ regulator-name = "VCC_3V3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ };
+
+ emmc_pwrseq: emmc-pwrseq {
+ compatible = "mmc-pwrseq-emmc";
+ /*reset-gpios = <&gpio BOOT_12 GPIO_ACTIVE_LOW>;*/
+ };
+
+ wifi32k: wifi32k {
+ compatible = "pwm-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ pwms = <&pwm_ef 0 30518 0>; /* PWM_E at 32.768KHz */
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ compatible = "mmc-pwrseq-simple";
+ reset-gpios = <&gpio GPIOX_6 GPIO_ACTIVE_LOW>;
+ clocks = <&wifi32k>;
+ clock-names = "ext_clock";
+ };
+
+ tee: tee {
+ compatible = "linaro,optee-tz";
+ method = "smc";
+ };
+};
+
+ðmac {
+ status = "okay";
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ /*mc_val = <0x1621>;*/
+};
+
+&ir {
+ status = "disabled";
+ /* pinctrl-0 = <&remote_input_ao_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+&saradc {
+ status = "disabled";
+ vref-supply = <&vddio_ao18>;
+};
+
+/* Wireless SDIO Module */
+&sd_emmc_a {
+ status = "disabled";
+ /*pinctrl-0 = <&sdio_pins>;*/
+ /*pinctrl-names = "default";*/
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+
+ non-removable;
+ disable-wp;
+ card_type = <3>;
+
+ mmc-pwrseq = <&sdio_pwrseq>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* SD card */
+&sd_emmc_b {
+ status = "okay";
+ pinctrl-0 = <&sdcard_pins>;
+ pinctrl-1 = <&sdcard_pins &to_sduart_pins>;
+ pinctrl-names = "sd_all_pins", "sd_uart";
+
+ bus-width = <4>;
+ cap-sd-highspeed;
+ max-frequency = <100000000>;
+ disable-wp;
+
+ cd-gpios = <&gpio GPIOC_6 GPIO_ACTIVE_HIGH>;
+ cd-inverted;
+
+ card_type = <5>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ sd_hs_co_phase = <2>;
+ sd_hs_to_phase = <0>;
+
+ vmmc-supply = <&vddao_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* eMMC */
+&sd_emmc_c {
+ status = "okay";
+ pinctrl-0 = <&emmc_pins>;
+ pinctrl-names = "default";
+
+ bus-width = <8>;
+ cap-mmc-highspeed;
+ mmc-hs200-1_8v;
+ max-frequency = <200000000>;
+ non-removable;
+ disable-wp;
+ /* mmc-ddr-1_8v; */
+ card_type = <1>;
+
+ init_co_phase = <2>;
+ init_tx_phase = <0>;
+
+ hs_co_phase = <2>;
+ hs_to_phase = <0>;
+
+ hs2_co_phase = <2>;
+ hs2_to_phase = <0>;
+
+ hw_reset = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>;
+
+ mmc-pwrseq = <&emmc_pwrseq>;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vddio_boot>;
+};
+
+/* nand */
+&nand {
+ status = "okay";
+ pinctrl-names = "default", "nand_cs_only";
+ pinctrl-0 = <&all_nand_pins>;
+ pinctrl-1 = <&nand_cs_pins>;
+};
+
+&crg {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&crg2 {
+ status = "okay";
+ dr_mode = "host";
+};
+
+&usb2_phy_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOM_8";
+ gpios = <&gpio GPIOM_8 GPIO_ACTIVE_HIGH>;
+};
+
+&usb2_phy2_v2 {
+ status = "okay";
+ portnum = <1>;
+};
+
+&usb3_phy2_v2 {
+ status = "okay";
+ portnum = <0>;
+ gpio-vbus-power = "GPIOM_9";
+ gpios = <&gpio GPIOM_9 GPIO_ACTIVE_HIGH>;
+};
+
+&pwm_ef {
+ status = "okay";
+ /* pinctrl-0 = <&pwm_e_pins>; */
+ /* pinctrl-names = "default"; */
+};
+
+/* This is connected to the Bluetooth module: */
+&uart_b {
+ status = "okay";
+ /* pinctrl-0 = <&a_uart_pins>; */
+ /* pinctrl-names = "default"; */
+ uart-has-rtscts;
+};
+
+&spifc {
+ status = "okay";
+ cs-gpios = <&gpio GPIOB_12 GPIO_ACTIVE_HIGH>;
+ spi-flash@0 {
+ status = "okay";
+ };
+};
+
+&spicc0 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc0_pins>;
+ cs-gpios = <&gpio GPIOT_21 0>;
+};
+
+&spicc1 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc1_pins_1>;
+ cs-gpios = <&gpio GPIOC_3 0>;
+};
+
+&spicc2 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc2_pins>;
+ cs-gpios = <&gpio GPIOY_3 0>;
+};
+
+&spicc3 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc3_pins>;
+ cs-gpios = <&gpio GPIOT_9 0>;
+ spi-flash@0 {
+ compatible = "spi-flash";
+ reg = <0>;
+ spi-max-frequency = <16000000>;
+ spi-tx-bus-width = <1>;
+ spi-rx-bus-width = <1>;
+ status = "disabled";
+ };
+};
+
+&spicc4 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc4_pins>;
+ cs-gpios = <&gpio GPIOZ_3 0>;
+};
+
+&spicc5 {
+ status = "disabled";
+ pinctrl-names = "default";
+ pinctrl-0 = <&spicc5_pins>;
+ cs-gpios = <&gpio GPIOZ_7 0>;
+};
diff --git a/arch/arm/dts/meson-t7-txxx.dtsi b/arch/arm/dts/meson-t7-txxx.dtsi
new file mode 100644
index 0000000..a92ec95
--- /dev/null
+++ b/arch/arm/dts/meson-t7-txxx.dtsi
@@ -0,0 +1,54 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "meson-t7.dtsi"
+#include "meson-t7-mali.dtsi"
+
+/ {
+ compatible = "amlogic,txxx", "amlogic,meson-t7";
+};
+
+ðmac {
+ phy-mode = "rmii";
+ phy-handle = <&internal_phy>;
+};
diff --git a/arch/arm/dts/meson-t7.dtsi b/arch/arm/dts/meson-t7.dtsi
new file mode 100644
index 0000000..e36f82d
--- /dev/null
+++ b/arch/arm/dts/meson-t7.dtsi
@@ -0,0 +1,867 @@
+/*
+ * Copyright (c) 2016 Endless Computers, Inc.
+ * Author: Carlo Caione <carlo@endlessm.com>
+ *
+ * This file is dual-licensed: you can use it either under the terms
+ * of the GPL or the X11 license, at your option. Note that this dual
+ * licensing only applies to this file, and not this project as a
+ * whole.
+ *
+ * a) This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; either version 2 of the
+ * License, or (at your option) any later version.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * Or, alternatively,
+ *
+ * b) Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use,
+ * copy, modify, merge, publish, distribute, sublicense, and/or
+ * sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following
+ * conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
+ * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
+ * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
+ * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
+ * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ */
+
+#include "meson-t7-series.dtsi"
+#include <dt-bindings/gpio/meson-t7-gpio.h>
+#include <dt-bindings/reset/amlogic,meson-gxbb-reset.h>
+#include <dt-bindings/pwm/pwm.h>
+#include <dt-bindings/pwm/meson.h>
+
+/ {
+ compatible = "amlogic,meson-t7";
+
+ vpu {
+ compatible = "amlogic, vpu-t7";
+ status = "okay";
+ /*clocks = <&clkc CLKID_VAPB_MUX>,
+ * <&clkc CLKID_VPU_INTR>,
+ * <&clkc CLKID_VPU_P0_COMP>,
+ * <&clkc CLKID_VPU_P1_COMP>,
+ * <&clkc CLKID_VPU_MUX>;
+ *clock-names = "vapb_clk",
+ * "vpu_intr_gate",
+ * "vpu_clk0",
+ * "vpu_clk1",
+ * "vpu_clk";
+ */
+ clk_level = <7>;
+ /* 0: 100.0M 1: 166.7M 2: 200.0M 3: 250.0M */
+ /* 4: 333.3M 5: 400.0M 6: 500.0M 7: 666.7M */
+ };
+
+ fb {
+ status = "okay";
+ logo_addr = "0x7f800000";
+ };
+
+ pinctrl_periphs: pinctrl@fe004000 {
+ compatible = "amlogic,meson-t7-periphs-pinctrl";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+
+ gpio: bank@fe004000 {
+ reg = <0x0 0xfe004000 0x0 0x0064>,
+ <0x0 0xfe0040c0 0x0 0x0220>;
+ reg-names = "mux",
+ "gpio";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pinctrl_periphs 0 0 157>;
+ };
+ };
+
+ i2c_gpio_0: i2c-gpio-0 {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ compatible = "i2c-gpio";
+ status = "okay";
+ gpios = <&gpio GPIOH_0 GPIO_ACTIVE_HIGH>, /* SDA */
+ <&gpio GPIOH_1 GPIO_ACTIVE_HIGH>; /* CLK */
+
+ i2c-gpio,delay-us = <5>;
+ is_odpin = <1>;
+ };
+
+ pwm_ab: pwm@fe058000 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0xfe058000 0x0 0x20>,
+ <0x0 0xfe000180 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_cd: pwm@fe05a000 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0xfe05a000 0x0 0x20>,
+ <0x0 0xfe000184 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwm_ef: pwm@fe05c000 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0xfe05c000 0x0 0x20>,
+ <0x0 0xfe000188 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwmao_ab: pwm@fe05e000 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0xfe05e000 0x0 0x20>,
+ <0x0 0xfe0001a0 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwmao_cd: pwm@fe060000 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0xfe060000 0x0 0x20>,
+ <0x0 0xfe0001a4 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwmao_ef: pwm@fe030000 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0xfe030000 0x0 0x20>,
+ <0x0 0xfe0001a8 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+
+ pwmao_gh: pwm@fe032000 {
+ compatible = "amlogic,meson-v2-pwm";
+ reg = <0x0 0xfe032000 0x0 0x20>,
+ <0x0 0xfe0001ac 0x0 0x04>;
+ #pwm-cells = <3>;
+ status = "disabled";
+ };
+};
+
+ðmac {
+ compatible = "amlogic,t7-eth-dwmac";
+ reg = <0x0 0xfdc00000 0x0 0x10000
+ 0x0 0xFE024000 0x0 0x8
+ 0x0 0xFE028000 0x0 0xa0>;
+ reg-names = "eth_base", "eth_top", "eth_cfg";
+ phy_cntl1 = <0x41054147>;
+ internal_phy = <1>;
+ mc_val = <0x4be04>;
+ cali_val = <0x80000>;
+ reset-gpios = <&gpio GPIOH_7 GPIO_ACTIVE_HIGH>;
+ analog_ver = <1>;
+ pll_val = <0x9c0040a 0x927e0000 0xac5f49e5>;
+ analog_val = <0x20200000 0x0000c000 0x00000023>;
+ chip_num = <3>;
+ //tx_amp_src = <0xfe005b30>;
+// clocks = <&clkc CLKID_ETH_CORE>,
+// <&clkc CLKID_FCLK_DIV2>,
+// <&clkc CLKID_MPLL2>;
+// clock-names = "stmmaceth", "clkin0", "clkin1";
+
+ mdio0: mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ compatible = "snps,dwmac-mdio";
+ };
+};
+
+&periphs {
+
+ eth-phy-mux {
+ compatible = "mdio-mux-mmioreg", "mdio-mux";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x0 0x15c 0x0 0x4>;
+ mux-mask = <0xffffffff>;
+ mdio-parent-bus = <&mdio0>;
+
+ internal_mdio: mdio@e40908ff {
+ reg = <0xe40908ff>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ internal_phy: ethernet-phy@8 {
+ compatible = "ethernet-phy-id0181.4400", "ethernet-phy-ieee802.3-c22";
+ reg = <8>;
+ max-speed = <100>;
+ };
+ };
+
+ external_mdio: mdio@2009087f {
+ reg = <0x2009087f>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ };
+ };
+};
+
+&saradc {
+ compatible = "amlogic,meson-g12a-saradc", "amlogic,meson-saradc";
+ clocks = <&xtal>,
+ <&clkc CLKID_SARADC_MUX>,
+ <&clkc CLKID_SARADC_DIV>,
+ <&clkc CLKID_SAR_ADC_GATE>;
+ clock-names = "xtal", "adc_mux", "adc_div", "adc_gate";
+};
+
+&sd_emmc_a {
+ clocks = <&clkc CLKID_SD_EMMC_A_MUX>,
+ <&clkc CLKID_SD_EMMC_A_DIV>,
+ <&clkc CLKID_SD_EMMC_A_GATE>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_XTAL>;
+ clock-names = "mux", "div", "gate", "clkin", "xtal";
+};
+
+&sd_emmc_b {
+ clocks = <&clkc CLKID_SD_EMMC_B_MUX>,
+ <&clkc CLKID_SD_EMMC_B_DIV>,
+ <&clkc CLKID_SD_EMMC_B_GATE>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_XTAL>;
+ clock-names = "mux", "div", "gate", "clkin", "xtal";
+};
+
+&sd_emmc_c {
+ clocks = <&clkc CLKID_SD_EMMC_C_MUX>,
+ <&clkc CLKID_SD_EMMC_C_DIV>,
+ <&clkc CLKID_SD_EMMC_C_GATE>,
+ <&clkc CLKID_GP0_PLL>,
+ <&clkc CLKID_XTAL>;
+ clock-names = "mux", "div", "gate", "clkin", "xtal";
+};
+
+&nand {
+ clocks = <&clkc CLKID_SD_EMMC_C_MUX>,
+ <&clkc CLKID_SD_EMMC_C_DIV>,
+ <&clkc CLKID_SD_EMMC_C_GATE>,
+ <&clkc CLKID_FCLK_DIV2>,
+ <&clkc CLKID_XTAL>;
+ clock-names = "mux", "div", "gate", "fdiv2", "xtal";
+};
+
+&spicc0 {
+ clocks = <&clkc CLKID_SPICC_A_DIV>, <&clkc CLKID_SPICC_A_GATE>;
+ clock-names = "async", "async-gate";
+ assigned-clocks = <&clkc CLKID_SPICC_A_MUX>, <&clkc CLKID_SPICC_A_DIV>;
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
+ assigned-clock-rates = <0>, <200000000>;
+ /* =PM_SPICC0, must set to power on */
+ pm-id = <42>;
+};
+
+&spicc1 {
+ clocks = <&clkc CLKID_SPICC_B_DIV>, <&clkc CLKID_SPICC_B_GATE>;
+ clock-names = "async", "async-gate";
+ assigned-clocks = <&clkc CLKID_SPICC_B_MUX>, <&clkc CLKID_SPICC_B_DIV>;
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
+ assigned-clock-rates = <0>, <200000000>;
+ /* =PM_SPICC1, must set to power on */
+ pm-id = <43>;
+};
+
+&spicc2 {
+ clocks = <&clkc CLKID_SPICC_C_DIV>, <&clkc CLKID_SPICC_C_GATE>;
+ clock-names = "async", "async-gate";
+ assigned-clocks = <&clkc CLKID_SPICC_C_MUX>, <&clkc CLKID_SPICC_C_DIV>;
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
+ assigned-clock-rates = <0>, <200000000>;
+ /* =PM_SPICC2, must set to power on */
+ pm-id = <44>;
+};
+
+&spicc3 {
+ clocks = <&clkc CLKID_SPICC_D_DIV>, <&clkc CLKID_SPICC_D_GATE>;
+ clock-names = "async", "async-gate";
+ assigned-clocks = <&clkc CLKID_SPICC_D_MUX>, <&clkc CLKID_SPICC_D_DIV>;
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
+ assigned-clock-rates = <0>, <200000000>;
+ /* =PM_SPICC3, must set to power on */
+ pm-id = <45>;
+};
+
+&spicc4 {
+ clocks = <&clkc CLKID_SPICC_E_DIV>, <&clkc CLKID_SPICC_E_GATE>;
+ clock-names = "async", "async-gate";
+ assigned-clocks = <&clkc CLKID_SPICC_E_MUX>, <&clkc CLKID_SPICC_E_DIV>;
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
+ assigned-clock-rates = <0>, <200000000>;
+ /* =PM_SPICC4, must set to power on */
+ pm-id = <46>;
+};
+
+&spicc5 {
+ clocks = <&clkc CLKID_SPICC_F_DIV>, <&clkc CLKID_SPICC_F_GATE>;
+ clock-names = "async", "async-gate";
+ assigned-clocks = <&clkc CLKID_SPICC_F_MUX>, <&clkc CLKID_SPICC_F_DIV>;
+ assigned-clock-parents = <&clkc CLKID_FCLK_DIV2>;
+ assigned-clock-rates = <0>, <200000000>;
+ /* =PM_SPICC5, must set to power on */
+ pm-id = <47>;
+};
+
+&pinctrl_periphs {
+ i2c0_pins1:i2c0_pins1 {
+ mux {
+ groups = "i2c0_sda_t",
+ "i2c0_sck_t";
+ function = "i2c0";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c0_pins2:i2c0_pins2 {
+ mux {
+ groups = "i2c0_sda_h",
+ "i2c0_sck_h";
+ function = "i2c0";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c1_pins1:i2c1_pins1 {
+ mux {
+ groups = "i2c1_sda",
+ "i2c1_sck";
+ function = "i2c1";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c2_pins1:i2c2_pins1 {
+ mux {
+ groups = "i2c2_sda_x",
+ "i2c2_sck_x";
+ function = "i2c2";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c2_pins2:i2c2_pins2 {
+ mux {
+ groups = "i2c2_sda_t",
+ "i2c2_sck_t";
+ function = "i2c2";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c2_pins3:i2c2_pins3 {
+ mux {
+ groups = "i2c2_sda_m",
+ "i2c2_sck_m";
+ function = "i2c2";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c3_pins1:i2c3_pins1 {
+ mux {
+ groups = "i2c3_sda_m",
+ "i2c3_sck_m";
+ function = "i2c3";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c3_pins2:i2c3_pins2 {
+ mux {
+ groups = "i2c3_sda_h",
+ "i2c3_sck_h";
+ function = "i2c3";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c4_pins1:i2c4_pins1 {
+ mux {
+ groups = "i2c4_sda_y",
+ "i2c4_sck_y";
+ function = "i2c4";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c4_pins2:i2c4_pins2 {
+ mux {
+ groups = "i2c4_sda_h",
+ "i2c4_sck_h";
+ function = "i2c4";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c5_pins1:i2c5_pins1 {
+ mux {
+ groups = "i2c5_sda",
+ "i2c5_sck";
+ function = "i2c5";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c0_ao_pins1:i2c0_ao_pins1 {
+ mux {
+ groups = "i2c0_ao_sda_d",
+ "i2c0_ao_sck_d";
+ function = "i2c0_ao";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c0_ao_pins2:i2c0_ao_pins2 {
+ mux {
+ groups = "i2c0_ao_sda_e",
+ "i2c0_ao_sck_e";
+ function = "i2c0_ao";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ i2c1_ao_pins1:i2c1_ao_pins1 {
+ mux {
+ groups = "i2c1_ao_sda",
+ "i2c1_ao_sck";
+ function = "i2c1_ao";
+ drive-strength = <3>;
+ bias-disable;
+ };
+ };
+
+ jtag_a_pins:jtag_a_pin {
+ mux {
+ groups = "jtag_a_clk",
+ "jtag_a_tms",
+ "jtag_a_tdi",
+ "jtag_a_tdo";
+ function = "jtag_a";
+ };
+ };
+
+ jtag_b_pins:jtag_b_pin {
+ mux {
+ groups = "jtag_b_clk",
+ "jtag_b_tms",
+ "jtag_b_tdi",
+ "jtag_b_tdo";
+ function = "jtag_b";
+ };
+ };
+
+ swd_a_pins:swd_a_pin {
+ mux {
+ groups = "swclk",
+ "swdio";
+ function = "sw";
+ };
+ };
+
+ emmc_pins: emmc {
+ mux {
+ groups = "emmc_nand_d0",
+ "emmc_nand_d1",
+ "emmc_nand_d2",
+ "emmc_nand_d3",
+ "emmc_nand_d4",
+ "emmc_nand_d5",
+ "emmc_nand_d6",
+ "emmc_nand_d7",
+ "emmc_clk",
+ "emmc_cmd";
+ function = "emmc";
+ bias-pull-up;
+ input-enable;
+ };
+ mux1 {
+ groups = "emmc_nand_ds";
+ function = "emmc";
+ input-enable;
+ bias-pull-down;
+ };
+ };
+
+ emmc_clk_gate_pins: emmc_clk_gate {
+ mux {
+ groups = "emmc_clk";
+ function = "emmc";
+ bias-pull-down;
+ };
+ };
+
+ all_nand_pins: all_nand_pins {
+ mux {
+ groups = "emmc_nand_d0",
+ "emmc_nand_d1",
+ "emmc_nand_d2",
+ "emmc_nand_d3",
+ "emmc_nand_d4",
+ "emmc_nand_d5",
+ "emmc_nand_d6",
+ "emmc_nand_d7",
+ "nand_ce0",
+ "nand_ale",
+ "nand_cle",
+ "nand_wen_clk",
+ "nand_ren_wr";
+ function = "nand";
+ input-enable;
+ };
+ };
+
+ nand_cs_pins: nand_cs {
+ mux {
+ groups = "nand_ce0";
+ function = "nand";
+ };
+ };
+
+ sdcard_pins: sdcard {
+ mux {
+ groups = "sdcard_d0",
+ "sdcard_d1",
+ "sdcard_d2",
+ "sdcard_d3",
+ "sdcard_cmd";
+ function = "sdcard";
+ bias-pull-up;
+ input-enable;
+ drive-strength = <4>;
+ };
+ mux1 {
+ groups ="sdcard_clk";
+ function = "sdcard";
+ bias-pull-up;
+ output-high;
+ drive-strength = <4>;
+ };
+ };
+
+ sdcard_clk_gate_pins: sdcard_clk_gate {
+ mux {
+ groups = "sdcard_clk";
+ function = "sdcard";
+ bias-pull-down;
+ };
+ };
+
+ to_sduart_pins: to_sduart_pins{
+ mux {
+ groups = "uart_b_rx_c", "uart_b_tx_c";
+ function = "uart_b";
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
+ sd_to_uart_pins: sd_to_uart_pins{
+ mux {
+ groups = "uart_b_rx_d", "uart_b_tx_d";
+ function = "uart_b";
+ bias-pull-up;
+ input-enable;
+ };
+ };
+
+ spicc0_pins: spicc0_pins {
+ mux {
+ groups = "spi0_mosi",
+ "spi0_miso",
+ //"spi0_ss0",used as GPIOT_21
+ "spi0_sclk";
+ function = "spi0";
+ drive-strength = <2>;
+ };
+ };
+
+ spicc1_pins_1: spicc1_pins_1 {
+ mux {
+ groups = "spi1_mosi_c",
+ "spi1_miso_c",
+ //"spi1_ss0_c",used as GPIOC_3
+ "spi1_sclk_c";
+ function = "spi1";
+ drive-strength = <2>;
+ };
+ };
+
+ spicc1_pins_2: spicc1_pins_2 {
+ mux {
+ groups = "spi1_mosi_m",
+ "spi1_miso_m",
+ //"spi1_ss0_m",used as GPIOM_11
+ "spi1_sclk_m";
+ function = "spi1";
+ drive-strength = <2>;
+ };
+ };
+
+ spicc2_pins: spicc2_pins {
+ mux {
+ groups = "spi2_mosi",
+ "spi2_miso",
+ //"spi2_ss0",used as GPIOY_3
+ "spi2_sclk";
+ function = "spi2";
+ drive-strength = <2>;
+ };
+ };
+
+ spicc3_pins: spicc3_pins {
+ mux {
+ groups = "spi3_mosi",
+ "spi3_miso",
+ //"spi3_ss0",used as GPIOT_9
+ "spi3_sclk";
+ function = "spi3";
+ drive-strength = <2>;
+ };
+ };
+
+ spicc4_pins: spicc4_pins {
+ mux {
+ groups = "spi4_mosi",
+ "spi4_miso",
+ //"spi4_ss0",used as GPIOZ_3
+ "spi4_sclk";
+ function = "spi4";
+ drive-strength = <2>;
+ };
+ };
+
+ spicc5_pins: spicc5_pins {
+ mux {
+ groups = "spi5_mosi",
+ "spi5_miso",
+ //"spi5_ss0",used as GPIOZ_7
+ "spi5_sclk";
+ function = "spi5";
+ drive-strength = <2>;
+ };
+ };
+
+ spifc_pins: spifc_pins {
+ mux {
+ groups = "nor_d",
+ "nor_q",
+ "nor_c",
+ "nor_hold",
+ "nor_wp";
+ function = "nor";
+ drive-strength = <3>;
+ };
+ };
+
+ pwm_a_pins: pwm_a_pins {
+ mux {
+ groups = "pwm_a";
+ function = "pwm_a";
+ };
+ };
+
+ pwm_b_pins: pwm_b_pins {
+ mux {
+ groups = "pwm_b";
+ function = "pwm_b";
+ };
+ };
+
+ pwm_c_pins: pwm_c_pins {
+ mux {
+ groups = "pwm_c";
+ function = "pwm_c";
+ };
+ };
+
+ pwm_d_pins: pwm_d_pins {
+ mux {
+ groups = "pwm_d";
+ function = "pwm_d";
+ };
+ };
+
+ pwm_e_pins: pwm_e_pins {
+ mux {
+ groups = "pwm_e";
+ function = "pwm_e";
+ };
+ };
+
+ pwm_f_pins: pwm_f_pins {
+ mux {
+ groups = "pwm_f";
+ function = "pwm_f";
+ };
+ };
+
+ pwm_ao_a_pins: pwm_ao_a_pins {
+ mux {
+ groups = "pwm_ao_a";
+ function = "pwm_ao_a";
+ };
+ };
+
+ pwm_ao_b_pins: pwm_ao_b_pins {
+ mux {
+ groups = "pwm_ao_b";
+ function = "pwm_ao_b";
+ };
+ };
+
+ pwm_ao_c_pins1: pwm_ao_c_pins1 {
+ mux {
+ groups = "pwm_ao_c_d";
+ function = "pwm_ao_c";
+ };
+ };
+
+ pwm_ao_c_pins2: pwm_ao_c_pins2 {
+ mux {
+ groups = "pwm_ao_c_e";
+ function = "pwm_ao_c";
+ };
+ };
+
+ pwm_ao_c_hiz_pins: pwm_ao_c_hiz_pins {
+ mux {
+ groups = "pwm_ao_c_hiz";
+ function = "pwm_ao_c";
+ };
+ };
+
+ pwm_ao_d_pins: pwm_ao_d_pins {
+ mux {
+ groups = "pwm_ao_d";
+ function = "pwm_ao_d";
+ };
+ };
+
+ pwm_ao_e_pins: pwm_ao_e_pins {
+ mux {
+ groups = "pwm_ao_e";
+ function = "pwm_ao_e";
+ };
+ };
+
+ pwm_ao_f_pins: pwm_ao_f_pins {
+ mux {
+ groups = "pwm_ao_f";
+ function = "pwm_ao_f";
+ };
+ };
+
+ pwm_ao_g_pins1: pwm_ao_g_pins1 {
+ mux {
+ groups = "pwm_ao_g_d11";
+ function = "pwm_ao_g";
+ };
+ };
+
+ pwm_ao_g_pins2: pwm_ao_g_pins2 {
+ mux {
+ groups = "pwm_ao_g_d7";
+ function = "pwm_ao_g";
+ };
+ };
+
+ pwm_ao_g_pins3: pwm_ao_g_pins3 {
+ mux {
+ groups = "pwm_ao_g_e";
+ function = "pwm_ao_g";
+ };
+ };
+
+ pwm_ao_g_hiz_pins: pwm_ao_g_hiz_pins {
+ mux {
+ groups = "pwm_ao_g_hiz";
+ function = "pwm_ao_g";
+ };
+ };
+
+ pwm_ao_h_pins1: pwm_ao_h_pins1 {
+ mux {
+ groups = "pwm_ao_h_d5";
+ function = "pwm_ao_h";
+ };
+ };
+
+ pwm_ao_h_pins2: pwm_ao_d_pins2 {
+ mux {
+ groups = "pwm_ao_h_d10";
+ function = "pwm_ao_h";
+ };
+ };
+
+ external_eth_rmii_pins: external_eth_rmii_pins {
+ mux {
+ groups = "eth_mdio",
+ "eth_mdc",
+ "eth_rgmii_rx_clk",
+ "eth_rx_dv",
+ "eth_rxd0",
+ "eth_rxd1",
+ "eth_txen",
+ "eth_txd0",
+ "eth_txd1";
+ function = "eth";
+ drive-strength = <3>;
+ };
+ };
+
+ external_eth_rgmii_pins: external_eth_rgmii_pins {
+ mux {
+ groups = "eth_mdio",
+ "eth_mdc",
+ "eth_rgmii_rx_clk",
+ "eth_rx_dv",
+ "eth_rxd0",
+ "eth_rxd1",
+ "eth_rxd2_rgmii",
+ "eth_rxd3_rgmii",
+ "eth_rgmii_tx_clk",
+ "eth_txen",
+ "eth_txd0",
+ "eth_txd1",
+ "eth_txd2_rgmii",
+ "eth_txd3_rgmii";
+ function = "eth";
+ drive-strength = <3>;
+ };
+ };
+};
diff --git a/arch/arm/dts/meson-t7_skt-panel.dtsi b/arch/arm/dts/meson-t7_skt-panel.dtsi
new file mode 100644
index 0000000..fbb676c
--- /dev/null
+++ b/arch/arm/dts/meson-t7_skt-panel.dtsi
@@ -0,0 +1,742 @@
+/*
+ * arch/arm64/boot/dts/amlogic/mesong12a_skt-panel.dtsi
+ *
+ * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful, but WITHOUT
+ * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
+ * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
+ * more details.
+ *
+ */
+
+/ {
+ lcd{
+ compatible = "amlogic, lcd-g12a";
+ mode = "tablet";
+ status = "okay";
+ key_valid = <0>;
+ /*
+ clocks = <&clkc CLKID_MIPI_DSI_HOST
+ &clkc CLKID_MIPI_DSI_PHY
+ &clkc CLKID_DSI_MEAS_COMP
+ &clkc CLKID_VCLK2_ENCL
+ &clkc CLKID_VCLK2_VENCL
+ &clkc CLKID_GP0_PLL>;
+ clock-names = "dsi_host_gate",
+ "dsi_phy_gate",
+ "dsi_meas",
+ "encl_top_gate",
+ "encl_int_gate",
+ "gp0_pll";
+ */
+ reg = <0x0 0xffd07000 0x0 0x400 /* dsi_host */
+ 0x0 0xff644000 0x0 0x200>; /* dsi_phy */
+ interrupts = <0 3 1
+ 0 56 1>;
+ interrupt-names = "vsync","vsync2";
+ pinctrl_version = <2>; /* for uboot */
+
+ /* power type:
+ * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending)
+ * power index:
+ * (point gpios_index, or extern_index,0xff=invalid)
+ * power value:(0=output low, 1=output high, 2=input)
+ * power delay:(unit in ms)
+ */
+
+ /*lcd_cpu-gpios = <&gpio GPIOZ_9 GPIO_ACTIVE_HIGH
+ &gpio GPIOZ_8 GPIO_ACTIVE_HIGH>;
+ */
+ lcd_cpu_gpio_names = "GPIOZ_9","GPIOZ_8";
+
+ lcd_0{
+ model_name = "B080XAN01";
+ interface = "mipi";
+ basic_setting = <768 1024 /*h_active, v_active*/
+ 948 1140 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 119 159>; /*screen_widht, screen_height*/
+ lcd_timing = <64 56 0 /*hs_width, hs_bp, hs_pol*/
+ 50 30 0>; /*vs_width, vs_bp, vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/
+ 0 /*clk_ss_level */
+ 1 /*clk_auto_generate*/
+ 64843200>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 550 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 1 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <0x05 1 0x11
+ 0xfd 1 20 /*delay(ms)*/
+ 0x05 1 0x29
+ 0xfd 1 20 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ dsi_init_off = <0x05 1 0x28
+ 0xfd 1 10 /*delay(ms)*/
+ 0x05 1 0x10
+ 0xfd 1 10 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ extern_init = <0xff>; /*0xff for invalid*/
+
+ /* power step: type, index, value, delay(ms) */
+ power_on_step = <
+ 0 1 0 100
+ 0 0 0 10
+ 0 0 1 20
+ 2 0 0 0
+ 0xff 0 0 0>; /*ending*/
+ power_off_step = <
+ 2 0 0 50
+ 0 0 0 10
+ 0 1 1 100
+ 0xff 0 0 0>; /*ending*/
+ backlight_index = <0>;
+ };
+
+ lcd_1{
+ model_name = "P070ACB_FT";
+ interface = "mipi";
+ basic_setting = <600 1024 /*h_active, v_active*/
+ 770 1070 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 3 5>; /*screen_widht, screen_height*/
+ lcd_timing = <10 80 0 /*hs_width,hs_bp,hs_pol*/
+ 6 20 0>; /*vs_width,vs_bp,vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
+ 0 /*clk_ss_level*/
+ 1 /*clk_auto_generate*/
+ 49434000>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 400 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 0 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <
+ 0xff 10
+ 0xf0 3 0 1 30 /* reset high, delay 30ms */
+ 0xf0 3 0 0 10 /* reset low, delay 10ms */
+ 0xf0 3 0 1 30 /* reset high, delay 30ms */
+ 0xfc 2 0x04 3 /* check_reg, check_cnt */
+ 0xff 0>; /* ending flag */
+ dsi_init_off = <0xff 0>; /* ending flag */
+ /* extern_init: 0xff for invalid */
+ extern_init = <2>;
+ /* power step: type,index,value,delay(ms) */
+ power_on_step = <
+ 0 1 0 200 /* panel power on */
+ 2 0 0 0
+ 0xff 0 0 0>;
+ power_off_step = <
+ 2 0 0 0
+ 0 0 0 20 /* reset low */
+ 0 1 1 100 /* panel power off */
+ 0xff 0 0 0>;
+ backlight_index = <0>;
+ };
+
+ lcd_3{
+ model_name = "TL050FHV02CT";
+ interface = "mipi";
+ basic_setting = <1080 1920 /*h_active, v_active*/
+ 1125 2100 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 65 119>; /*screen_widht, screen_height*/
+ lcd_timing = <5 30 0 /*hs_width,hs_bp,hs_pol*/
+ 44 108 0>; /*vs_width,vs_bp,vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
+ 0 /*clk_ss_level*/
+ 1 /*clk_auto_generate*/
+ 118125000>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 960 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 1 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <0xff 0>; /* ending flag */
+ dsi_init_off = <0xff 0>; /* ending flag */
+ /* extern_init: 0xff for invalid */
+ extern_init = <3>;
+ /* power step: type,index,value,delay(ms) */
+ power_on_step = <
+ 0 1 0 200
+ 0 0 1 20
+ 0 0 0 10
+ 0 0 1 20
+ 2 0 0 0
+ 0xff 0 0 0>;
+ power_off_step = <
+ 2 0 0 0
+ 0 0 0 20
+ 0 1 1 100
+ 0xff 0 0 0>;
+ backlight_index = <0>;
+ };
+
+ lcd_4{
+ model_name = "TL070WSH27";
+ interface = "mipi";
+ basic_setting = <1024 600 /*h_active, v_active*/
+ 1250 630 /*h_period, v_period*/
+ 8 /*lcd_bits*/
+ 154 86>; /*screen_widht, screen_height*/
+ lcd_timing = <80 100 0 /*hs_width, hs_bp, hs_pol*/
+ 5 20 0>; /*vs_width, vs_bp, vs_pol*/
+ clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/
+ 0 /*clk_ss_level */
+ 1 /*clk_auto_generate*/
+ 47250000>; /*pixel_clk(unit in Hz)*/
+ mipi_attr = <4 /*lane_num*/
+ 300 /*bit_rate_max(MHz)*/
+ 0 /*factor(*100, default 0 for auto)*/
+ 1 /*operation_mode_init(0=video, 1=command)*/
+ 0 /*operation_mode_display(0=video, 1=command)*/
+ 2 /*
+ *video_mode_type
+ *(0=sync_pulse,1=sync_event,2=burst)
+ */
+ 1 /*clk_always_hs(0=disable,1=enable)*/
+ 0>; /*phy_switch(0=auto,1=standard,2=slow)*/
+
+ /* dsi_init: data_type, num, data... */
+ dsi_init_on = <0x05 1 0x11
+ 0xfd 1 20 /*delay(ms)*/
+ 0x05 1 0x29
+ 0xfd 1 20 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ dsi_init_off = <0x05 1 0x28
+ 0xfd 1 10 /*delay(ms)*/
+ 0x05 1 0x10
+ 0xfd 1 10 /*delay(ms)*/
+ 0xff 0>; /*ending*/
+ extern_init = <0xff>; /*0xff for invalid*/
+
+ /* power step: type, index, value, delay(ms) */
+ power_on_step = <
+ 0 1 0 100
+ 0 0 0 10
+ 0 0 1 20
+ 2 0 0 0
+ 0xff 0 0 0>; /*ending*/
+ power_off_step = <
+ 2 0 0 50
+ 0 0 0 10
+ 0 1 1 100
+ 0xff 0 0 0>; /*ending*/
+ backlight_index = <0>;
+ };
+ };
+
+ lcd_extern{
+ compatible = "amlogic, lcd_extern";
+ status = "okay";
+ i2c_bus = "i2c_bus_0";
+ key_valid = <0>;
+
+ extern_0{
+ index = <0>;
+ extern_name = "mipi_default";/*default*/
+ status = "okay";
+ type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+ cmd_size = <0xff>;
+ init_on = <
+ 0xfd 1 10
+ 0x05 1 0x11
+ 0xfd 1 120 /* delay 120ms */
+ 0x05 1 0x29
+ 0xff 0>; /*ending*/
+ init_off = <
+ 0x05 1 0x28 /* display off */
+ 0xfd 1 10 /* delay 10ms */
+ 0x05 1 0x10 /* sleep in */
+ 0xfd 1 150 /* delay 150ms */
+ 0xff 0>; /*ending*/
+ };
+
+ extern_2{
+ index = <2>;
+ extern_name = "mipi_default";/*P070ACB_FT*/
+ status = "okay";
+ type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+ cmd_size = <0xff>;
+ init_on = <
+ 0x23 2 0xE0 0x00 /* Page 0 */
+ 0x23 2 0xE1 0x93 /* PASSWORD */
+ 0x23 2 0xE2 0x65
+ 0x23 2 0xE3 0xF8
+ 0x23 2 0x80 0x03
+ 0x23 2 0xE0 0x01 /* Page 01 */
+ 0x23 2 0x0C 0x74 /* Set PWRIC */
+ 0x23 2 0x17 0x00 /* Set Gamma Power */
+ 0x23 2 0x18 0xEF /* VGMP=5.1V */
+ 0x23 2 0x19 0x00
+ 0x23 2 0x1A 0x00
+ 0x23 2 0x1B 0xEF /* VGMN=-5.1V */
+ 0x23 2 0x1C 0x00
+ 0x23 2 0x1F 0x70 /* Set Gate Power */
+ 0x23 2 0x20 0x2D
+ 0x23 2 0x21 0x2D
+ 0x23 2 0x22 0x7E
+ 0x23 2 0x26 0xF3 /* VDDD from IOVCC */
+ 0x23 2 0x37 0x09 /* SetPanel */
+ 0x23 2 0x38 0x04 /* SET RGBCYC */
+ 0x23 2 0x39 0x00
+ 0x23 2 0x3A 0x01
+ 0x23 2 0x3C 0x90
+ 0x23 2 0x3D 0xFF
+ 0x23 2 0x3E 0xFF
+ 0x23 2 0x3F 0xFF
+ 0x23 2 0x40 0x02 /* Set TCON */
+ 0x23 2 0x41 0x80
+ 0x23 2 0x42 0x99
+ 0x23 2 0x43 0x14
+ 0x23 2 0x44 0x19
+ 0x23 2 0x45 0x5A
+ 0x23 2 0x4B 0x04
+ 0x23 2 0x55 0x02 /* power voltage */
+ 0x23 2 0x56 0x01
+ 0x23 2 0x57 0x69
+ 0x23 2 0x58 0x0A
+ 0x23 2 0x59 0x0A
+ 0x23 2 0x5A 0x2E /* VGH = 16.2V */
+ 0x23 2 0x5B 0x19 /* VGL = -12V */
+ 0x23 2 0x5C 0x15
+ 0x23 2 0x5D 0x77 /* Gamma */
+ 0x23 2 0x5E 0x56
+ 0x23 2 0x5F 0x45
+ 0x23 2 0x60 0x38
+ 0x23 2 0x61 0x35
+ 0x23 2 0x62 0x27
+ 0x23 2 0x63 0x2D
+ 0x23 2 0x64 0x18
+ 0x23 2 0x65 0x33
+ 0x23 2 0x66 0x34
+ 0x23 2 0x67 0x35
+ 0x23 2 0x68 0x56
+ 0x23 2 0x69 0x45
+ 0x23 2 0x6A 0x4F
+ 0x23 2 0x6B 0x42
+ 0x23 2 0x6C 0x40
+ 0x23 2 0x6D 0x34
+ 0x23 2 0x6E 0x25
+ 0x23 2 0x6F 0x02
+ 0x23 2 0x70 0x77
+ 0x23 2 0x71 0x56
+ 0x23 2 0x72 0x45
+ 0x23 2 0x73 0x38
+ 0x23 2 0x74 0x35
+ 0x23 2 0x75 0x27
+ 0x23 2 0x76 0x2D
+ 0x23 2 0x77 0x18
+ 0x23 2 0x78 0x33
+ 0x23 2 0x79 0x34
+ 0x23 2 0x7A 0x35
+ 0x23 2 0x7B 0x56
+ 0x23 2 0x7C 0x45
+ 0x23 2 0x7D 0x4F
+ 0x23 2 0x7E 0x42
+ 0x23 2 0x7F 0x40
+ 0x23 2 0x80 0x34
+ 0x23 2 0x81 0x25
+ 0x23 2 0x82 0x02
+ 0x23 2 0xE0 0x02 /* Page2 */
+ 0x23 2 0x00 0x53
+ /* GIP_L Pin mapping RESET_EVEN */
+ 0x23 2 0x01 0x55 /* VSSG_EVEN */
+ 0x23 2 0x02 0x55 /* VSSA_EVEN */
+ 0x23 2 0x03 0x51 /* STV2_EVEN */
+ 0x23 2 0x04 0x77 /* VDD2_EVEN */
+ 0x23 2 0x05 0x57 /* VDD1_EVEN */
+ 0x23 2 0x06 0x1F
+ 0x23 2 0x07 0x4F /* CK12 */
+ 0x23 2 0x08 0x4D /* CK10 */
+ 0x23 2 0x09 0x1F
+ 0x23 2 0x0A 0x4B /* CK8 */
+ 0x23 2 0x0B 0x49 /* CK6 */
+ 0x23 2 0x0C 0x1F
+ 0x23 2 0x0D 0x47 /* CK4 */
+ 0x23 2 0x0E 0x45 /* CK2 */
+ 0x23 2 0x0F 0x41 /* STV1_EVEN */
+ 0x23 2 0x10 0x1F
+ 0x23 2 0x11 0x1F
+ 0x23 2 0x12 0x1F
+ 0x23 2 0x13 0x55 /* VGG */
+ 0x23 2 0x14 0x1F
+ 0x23 2 0x15 0x1F
+ 0x23 2 0x16 0x52
+ /* GIP_R Pin mapping RESET_ODD */
+ 0x23 2 0x17 0x55 /* VSSG_ODD */
+ 0x23 2 0x18 0x55 /* VSSA_ODD */
+ 0x23 2 0x19 0x50 /* STV2_ODD */
+ 0x23 2 0x1A 0x77 /* VDD2_ODD */
+ 0x23 2 0x1B 0x57 /* VDD1_ODD */
+ 0x23 2 0x1C 0x1F
+ 0x23 2 0x1D 0x4E /* CK11 */
+ 0x23 2 0x1E 0x4C /* CK9 */
+ 0x23 2 0x1F 0x1F
+ 0x23 2 0x20 0x4A /* CK7 */
+ 0x23 2 0x21 0x48 /* CK5 */
+ 0x23 2 0x22 0x1F
+ 0x23 2 0x23 0x46 /* CK3 */
+ 0x23 2 0x24 0x44 /* CK1 */
+ 0x23 2 0x25 0x40 /* STV1_ODD */
+ 0x23 2 0x26 0x1F
+ 0x23 2 0x27 0x1F
+ 0x23 2 0x28 0x1F
+ 0x23 2 0x29 0x1F
+ 0x23 2 0x2A 0x1F
+ 0x23 2 0x2B 0x55 /* VGG */
+ 0x23 2 0x2C 0x12 /* GIP_L_GS Pin mapping */
+ 0x23 2 0x2D 0x15
+ 0x23 2 0x2E 0x15
+ 0x23 2 0x2F 0x00
+ 0x23 2 0x30 0x37
+ 0x23 2 0x31 0x17
+ 0x23 2 0x32 0x1F
+ 0x23 2 0x33 0x08
+ 0x23 2 0x34 0x0A
+ 0x23 2 0x35 0x1F
+ 0x23 2 0x36 0x0C
+ 0x23 2 0x37 0x0E
+ 0x23 2 0x38 0x1F
+ 0x23 2 0x39 0x04
+ 0x23 2 0x3A 0x06
+ 0x23 2 0x3B 0x10
+ 0x23 2 0x3C 0x1F
+ 0x23 2 0x3D 0x1F
+ 0x23 2 0x3E 0x1F
+ 0x23 2 0x3F 0x15
+ 0x23 2 0x40 0x1F
+ 0x23 2 0x41 0x1F
+ 0x23 2 0x42 0x13 /* GIP_R_GS Pin mapping */
+ 0x23 2 0x43 0x15
+ 0x23 2 0x44 0x15
+ 0x23 2 0x45 0x01
+ 0x23 2 0x46 0x37
+ 0x23 2 0x47 0x17
+ 0x23 2 0x48 0x1F
+ 0x23 2 0x49 0x09
+ 0x23 2 0x4A 0x0B
+ 0x23 2 0x4B 0x1F
+ 0x23 2 0x4C 0x0D
+ 0x23 2 0x4D 0x0F
+ 0x23 2 0x4E 0x1F
+ 0x23 2 0x4F 0x05
+ 0x23 2 0x50 0x07
+ 0x23 2 0x51 0x11
+ 0x23 2 0x52 0x1F
+ 0x23 2 0x53 0x1F
+ 0x23 2 0x54 0x1F
+ 0x23 2 0x55 0x1F
+ 0x23 2 0x56 0x1F
+ 0x23 2 0x57 0x15
+ 0x23 2 0x58 0x40 /* GIP Timing */
+ 0x23 2 0x59 0x00
+ 0x23 2 0x5A 0x00
+ 0x23 2 0x5B 0x10
+ 0x23 2 0x5C 0x14
+ 0x23 2 0x5D 0x40
+ 0x23 2 0x5E 0x01
+ 0x23 2 0x5F 0x02
+ 0x23 2 0x60 0x40
+ 0x23 2 0x61 0x03
+ 0x23 2 0x62 0x04
+ 0x23 2 0x63 0x7A
+ 0x23 2 0x64 0x7A
+ 0x23 2 0x65 0x74
+ 0x23 2 0x66 0x16
+ 0x23 2 0x67 0xB4
+ 0x23 2 0x68 0x16
+ 0x23 2 0x69 0x7A
+ 0x23 2 0x6A 0x7A
+ 0x23 2 0x6B 0x0C
+ 0x23 2 0x6C 0x00
+ 0x23 2 0x6D 0x04
+ 0x23 2 0x6E 0x04
+ 0x23 2 0x6F 0x88
+ 0x23 2 0x70 0x00
+ 0x23 2 0x71 0x00
+ 0x23 2 0x72 0x06
+ 0x23 2 0x73 0x7B
+ 0x23 2 0x74 0x00
+ 0x23 2 0x75 0xBC
+ 0x23 2 0x76 0x00
+ 0x23 2 0x77 0x04
+ 0x23 2 0x78 0x2C
+ 0x23 2 0x79 0x00
+ 0x23 2 0x7A 0x00
+ 0x23 2 0x7B 0x00
+ 0x23 2 0x7C 0x00
+ 0x23 2 0x7D 0x03
+ 0x23 2 0x7E 0x7B
+ 0x23 2 0xE0 0x04 /* Page4 */
+ 0x23 2 0x09 0x11 /* Set RGBCYC2 */
+ 0x23 2 0x0E 0x48
+ 0x23 2 0x2B 0x2B /* ESD Protect */
+ 0x23 2 0x2E 0x44
+ 0x23 2 0xE0 0x00 /* Page0 */
+ 0x23 2 0xE6 0x02 /* Watch dog */
+ 0x23 2 0xE7 0x0C
+ 0x05 1 0x11 /* sleep out */
+ 0xfd 1 120
+ 0x05 1 0x29 /* display on */
+ 0x05 1 0x35
+ 0xfd 1 20 /* delay(ms) */
+ 0xFF 0>; /*ending*/
+ init_off = <
+ 0x05 1 0x28 /* display off */
+ 0xfd 1 10 /* delay 10ms */
+ 0x05 1 0x10 /* sleep in */
+ 0xfd 1 150 /* delay 150ms */
+ 0xff 0>; /*ending*/
+ };
+
+ extern_3{
+ index = <3>;
+ extern_name = "mipi_default";/*TL050FHV02CT*/
+ status = "okay";
+ type = <2>; /* 0=i2c, 1=spi, 2=mipi */
+ cmd_size = <0xff>;
+ init_on = <
+ 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03
+ 0x29 10 0x90 0x03 0x14 0x09 0x00 0x00
+ 0x00 0x38 0x00 0x00
+ 0x29 10 0x91 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00
+ 0x29 12 0x92 0x40 0x0B 0x0C 0x0D 0x0E
+ 0x00 0x38 0x00 0x10 0x03 0x04
+ 0x29 9 0x94 0x00 0x08 0x0B 0x03 0xD2
+ 0x03 0xD3 0x0C
+ 0x29 17 0x95 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00
+ 0x29 3 0x99 0x00 0x00
+ 0x29 12 0x9A 0x00 0x00 0x00 0x00 0x00
+ 0x00 0x00 0x00 0x00 0x00 0x00
+ 0x29 7 0x9B 0x01 0x38 0x00 0x00 0x00 0x00
+ 0x29 3 0x9C 0x00 0x00
+ 0x29 9 0x9D 0x10 0x10 0x10 0x10 0x10
+ 0x10 0x00 0x00
+ 0x29 3 0x9E 0x00 0x00
+ 0x29 11 0xA0 0x9F 0x1F 0x08 0x1F 0x0A
+ 0x1F 0x00 0x1F 0x14 0x1F
+ 0x29 11 0xA1 0x15 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA2 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA4 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA5 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x15
+ 0x29 11 0xA6 0x1F 0x14 0x1F 0x01 0x1F
+ 0x0B 0x1F 0x09 0x1F 0x1F
+ 0x29 11 0xA7 0x1F 0x1F 0x0B 0x1F 0x09
+ 0x1F 0x01 0x1F 0x15 0x1F
+ 0x29 11 0xA8 0x14 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xA9 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xAB 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x29 11 0xAC 0x1F 0x1F 0x1F 0x1F 0x1F
+ 0x1F 0x1F 0x1F 0x1F 0x14
+ 0x29 11 0xAD 0x1F 0x15 0x1F 0x00 0x1F
+ 0x08 0x1F 0x0A 0x1F 0x1F
+ 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00
+ 0x29 4 0xBC 0x00 0x00 0x00
+ 0x29 5 0xB8 0x01 0xAF 0x8F 0x8F
+ 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01
+ 0x29 17 0xD1 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xD2 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xD3 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xD4 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xD5 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xD6 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xD7 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xD8 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xD9 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xDD 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xDE 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xDF 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xE0 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xE1 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xE2 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xE3 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xE4 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xE5 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xE6 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xE7 0x03 0xC5 0x03 0xFF
+ 0x29 17 0xE8 0x00 0x00 0x00 0x09 0x00
+ 0x1F 0x00 0x30 0x00 0x3F 0x00 0x5D
+ 0x00 0x79 0x00 0xA7
+ 0x29 17 0xE9 0x00 0xCF 0x01 0x12 0x01
+ 0x49 0x01 0xA1 0x01 0xEB 0x01 0xED
+ 0x02 0x2F 0x02 0x74
+ 0x29 17 0xEA 0x02 0x9F 0x02 0xD5 0x02
+ 0xFB 0x03 0x2C 0x03 0x4B 0x03 0x73
+ 0x03 0x8C 0x03 0xA5
+ 0x29 5 0xEB 0x03 0xC5 0x03 0xFF
+ 0x29 4 0xB0 0x05 0x05 0x05
+ 0x29 4 0xB1 0x05 0x05 0x05
+ 0x29 4 0xB3 0x10 0x10 0x10
+ 0x29 4 0xB4 0x06 0x06 0x06
+ 0x29 4 0xB6 0x44 0x44 0x44
+ 0x29 4 0xB7 0x34 0x34 0x34
+ 0x29 4 0xB8 0x34 0x34 0x34
+ 0x29 4 0xB9 0x24 0x24 0x24
+ 0x29 4 0xBA 0x24 0x24 0x24
+ 0x29 4 0xBC 0x00 0x70 0x00
+ 0x29 4 0xBD 0x00 0x70 0x00
+ 0x23 2 0xBE 0x50
+ 0x23 2 0x35 0x00
+ 0x13 1 0x11
+ 0xfd 1 200
+ 0x13 1 0x29
+ 0xfd 1 200
+ 0xFF 0>; /*ending*/
+ init_off = <
+ 0x05 1 0x28 /* display off */
+ 0xfd 1 10 /* delay 10ms */
+ 0x05 1 0x10 /* sleep in */
+ 0xfd 1 150 /* delay 150ms */
+ 0xff 0>; /*ending*/
+ };
+ };
+
+ backlight{
+ compatible = "amlogic, backlight-g12a";
+ status = "okay";
+ key_valid = <0>;
+ pinctrl-names = "pwm_on","pwm_off";
+ /* pinctrl-0 = <&pwm_f_pins2>; */
+ /* pinctrl-1 = <&bl_pwm_off_pins>; */
+ pinctrl_version = <2>; /* for uboot */
+ bl_pwm_config = <&bl_pwm_conf>;
+ /*bl-gpios = <&gpio GPIOH_4 GPIO_ACTIVE_HIGH
+ &gpio GPIOH_5 GPIO_ACTIVE_HIGH>;*/
+ bl_gpio_names = "GPIOH_4","GPIOH_5";
+
+ /* pwm port: PWM_A, PWM_B, PWM_C, PWM_D, PWM_E, PWM_F, PWM_VS*/
+ /* power index:(point gpios_index, 0xff=invalid)
+ * power value:(0=output low, 1=output high, 2=input)
+ * power delay:(unit in ms)
+ */
+
+ backlight_0{
+ index = <0>;
+ bl_name = "backlight_pwm";
+ bl_level_default_uboot_kernel = <100 100>;
+ bl_level_attr = <255 10 /*max, min*/
+ 128 128>; /*mid, mid_mapping*/
+ bl_ctrl_method = <1>; /* 1=pwm, 2=pwm_combo, 4=extern */
+ bl_power_attr = <0 /*en_gpio_index*/
+ 1 0 /*on_value, off_value*/
+ 200 200>; /*on_delay(ms), off_delay(ms)*/
+ bl_pwm_port = "PWM_F";
+ bl_pwm_attr = <0 /*pwm_method*/
+ 180 /*pwm_freq(pwm:Hz, pwm_vs:multiple of vs)*/
+ 100 25>; /*duty_max(%), duty_min(%)*/
+ bl_pwm_power = <1 1 /*pwm_gpio_index, pwm_gpio_off*/
+ 10 10>; /*pwm_on_delay(ms), pwm_off_delay(ms)*/
+ bl_pwm_en_sequence_reverse = <0>; /* 1 for reverse */
+ };
+ backlight_1{
+ index = <1>;
+ bl_name = "bl_extern";
+ bl_level_default_uboot_kernel = <100 100>;
+ bl_level_attr = <255 10 /*max, min*/
+ 128 128>; /*mid, mid_mapping*/
+ bl_ctrl_method = <4>; /*1=pwm, 2=pwm_combo, 4=extern*/
+ bl_power_attr = <1 /*en_gpio_index*/
+ 1 0 /*on_value, off_value*/
+ 200 200>; /*on_delay(ms), off_delay(ms)*/
+ bl_extern_index = <0>;
+ };
+ };
+ bl_pwm_conf:bl_pwm_conf{
+ pwm_channel_0 {
+ pwm_port_index = <5>;
+ pwms = <&pwm_ef MESON_PWM_1 30040 0>;
+ };
+ };
+
+ bl_extern{
+ compatible = "amlogic, bl_extern";
+ status = "disabled";
+ i2c_bus = "i2c_bus_3";
+
+ extern_0{
+ index = <0>;
+ extern_name = "i2c_lp8556";
+ type = <0>; /*0=i2c, 1=spi, 2=mipi*/
+ i2c_address = <0x2c>; /*7bit i2c address*/
+ dim_max_min = <255 10>;
+ };
+
+ extern_1{
+ index = <1>;
+ extern_name = "mipi_lt070me05";
+ type = <2>; /*0=i2c, 1=spi, 2=mipi*/
+ dim_max_min = <255 10>;
+ };
+ };
+};/* end of panel */
+
diff --git a/arch/arm/dts/newman-panel.dtsi b/arch/arm/dts/newman-panel.dtsi
deleted file mode 100644
index b96a004..0000000
--- a/arch/arm/dts/newman-panel.dtsi
+++ /dev/null
@@ -1,1269 +0,0 @@
-/*
- * arch/arm64/boot/dts/amlogic/newman-panel.dtsi
- *
- * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-/ {
- lcd{
- compatible = "amlogic, lcd-g12a";
- dev_name = "lcd";
- mode = "tablet";
- status = "okay";
- key_valid = <0>;
- clocks = <&clkc CLKID_MIPI_DSI_HOST
- &clkc CLKID_MIPI_DSI_PHY
- &clkc CLKID_DSI_MEAS_COMP
- &clkc CLKID_VCLK2_ENCL
- &clkc CLKID_VCLK2_VENCL>;
- clock-names = "dsi_host_gate",
- "dsi_phy_gate",
- "dsi_meas",
- "encl_top_gate",
- "encl_int_gate";
- reg = <0x0 0xffd07000 0x0 0x400
- 0x0 0xff644000 0x0 0x2000>;
- interrupts = <0 3 1>;
- interrupt-names = "vsync";
- pinctrl_version = <2>; /* for uboot */
-
- /* power type:
- * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending)
- * power index:
- * (point gpios_index, or extern_index,0xff=invalid)
- * power value:(0=output low, 1=output high, 2=input)
- * power delay:(unit in ms)
- */
- lcd_cpu-gpios = <&gpio GPIOH_6 GPIO_ACTIVE_HIGH>;
- lcd_cpu_gpio_names = "GPIOH_6";
-
- lcd_0{
- model_name = "B080XAN01";
- interface = "mipi";
- basic_setting = <768 1024 /*h_active, v_active*/
- 948 1140 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 119 159>; /*screen_width, screen_height*/
- lcd_timing = <64 56 0 /*hs_width, hs_bp, hs_pol*/
- 50 30 0>; /*vs_width, vs_bp, vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clk, 1=htotal, 2=vtotal)*/
- 0 /*clk_ss_level */
- 1 /*clk_auto_generate*/
- 64843200>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 550 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 1 /*clk_lp_continuous(0=stop,1=continue)*/
- 0>; /*phy_stop_wait(0=auto,1=standard,2=slow)*/
-
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <0x05 1 0x11
- 0xff 20 /*delay(ms)*/
- 0x05 1 0x29
- 0xff 20 /*delay(ms)*/
- 0xff 0xff>; /*ending*/
- dsi_init_off = <0x05 1 0x28
- 0xff 10 /*delay(ms)*/
- 0x05 1 0x10
- 0xff 10 /*delay(ms)*/
- 0xff 0xff>; /*ending*/
- extern_init = <0xff>; /*0xff for invalid*/
-
- /* power step: type, index, value, delay(ms) */
- power_on_step = <
- 0 0 0 10
- 0 0 1 20
- 2 0 0 0
- 0xff 0 0 0>; /*ending*/
- power_off_step = <
- 2 0 0 50
- 0 0 0 100
- 0xff 0 0 0>; /*ending*/
- backlight_index = <0>;
- };
-
- lcd_1{
- model_name = "TV070WSM";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 700 1053 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 95 163>; /*screen_width, screen_height*/
- lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/
- 2 8 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 44250000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 360 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_lp_continuous(0=stop,1=continue)*/
- 0>; /*phy_stop_wait(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10 /* delay 10 ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 4 3 /* mipi state check */
- 0xff 10 /* delay 10 ms */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <1>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 50
- 0 0 0 100
- 0xff 0 0 0>;
- backlight_index = <0>;
- };
-
- lcd_2{
- model_name = "P070ACB";
- interface = "mipi";
- basic_setting = <600 1024 /*h_active, v_active*/
- 680 1194 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 3 5>; /*screen_width, screen_height*/
- lcd_timing = <24 36 0 /*hs_width,hs_bp,hs_pol*/
- 10 80 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 48715200>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 400 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_lp_continuous(0=stop,1=continue)*/
- 0>; /*phy_stop_wait(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10 /* delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 4 3 /* mipi state check */
- 0xff 10 /* delay 10 ms */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <2>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 50
- 0 0 0 100
- 0xff 0 0 0>;
- backlight_index = <1>;
- };
- boe_nvtk_10{
- model_name = "TV101WXM";
- interface = "mipi";
- basic_setting = <800 1280 /*h_active, v_active*/
- 900 1312 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 800 1280>; /*screen_width, screen_height*/
- lcd_timing = <24 48 0 /*hs_width,hs_bp,hs_pol*/
- 4 12 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 70950000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 568 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_lp_continuous(0=stop,1=continue)*/
- 0>; /*phy_stop_wait(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10 /* delay 10 ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 4 3 /* mipi state check */
- 0xff 10 /* delay 10 ms */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <5>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 50
- 0 0 0 100
- 0xff 0 0 0>;
- backlight_index = <0>;
- };
- inx_nvtk_10{
- model_name = "G101B158";
- interface = "mipi";
- basic_setting = <800 1280 /*h_active, v_active*/
- 880 1314 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 800 1280>; /*screen_width, screen_height*/
- lcd_timing = <18 18 0 /*hs_width,hs_bp,hs_pol*/
- 4 10 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 69380000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 560 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_lp_continuous(0=stop,1=continue)*/
- 0>; /*phy_stop_wait(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10 /* delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 4 3 /* mipi state check */
- 0xff 10 /* delay 10 ms */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <6>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 50
- 0 0 0 100
- 0xff 0 0 0>;
- backlight_index = <1>;
- };
- boe_fiti_10{
- model_name = "TV101WXM_FT";
- interface = "mipi";
- basic_setting = <800 1280 /*h_active, v_active*/
- 890 1324 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 800 1280>; /*screen_width, screen_height*/
- lcd_timing = <20 50 0 /*hs_width,hs_bp,hs_pol*/
- 4 20 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 70701600>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 566 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_lp_continuous(0=stop,1=continue)*/
- 0>; /*phy_stop_wait(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10 /* delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 4 3 /* mipi state check */
- 0xff 10 /* delay 10 ms */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <7>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 50
- 0 0 0 100
- 0xff 0 0 0>;
- backlight_index = <1>;
- };
- inx_fiti_10{
- model_name = "G101B158_FT";
- interface = "mipi";
- basic_setting = <800 1280 /*h_active, v_active*/
- 890 1324 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 800 1280>; /*screen_width, screen_height*/
- lcd_timing = <24 20 0 /*hs_width,hs_bp,hs_pol*/
- 4 20 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 70701600>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 566 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_lp_continuous(0=stop,1=continue)*/
- 0>; /*phy_stop_wait(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 10 /* delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xf0 3 0 0 10 /* reset low, delay 10ms */
- 0xf0 3 0 1 30 /* reset high, delay 30ms */
- 0xfc 2 4 3 /* mipi state check */
- 0xff 10 /* delay 10 ms */
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <8>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 50
- 0 0 0 100
- 0xff 0 0 0>;
- backlight_index = <1>;
- };
- };
-
- lcd_extern{
- compatible = "amlogic, lcd_extern";
- dev_name = "lcd_extern";
- status = "okay";
- key_valid = <0>;
-
- extern_0{
- index = <0>;
- extern_name = "ext_default";
- status = "disabled";
- type = <0>; /*0=i2c, 1=spi, 2=mipi*/
- i2c_address = <0x37>; /*7bit i2c address*/
- i2c_second_address = <0xff>; /*0xff for none*/
- i2c_bus = "i2c_bus_c";
- cmd_size = <4>;
-
- /* init on/off: (type, value..., delay),
- * must match cmd_size for every group
- * type: 0x00=cmd(bit[3:0]=1 for second_addr),
- * 0xf0=gpio, 0xff=ending
- * value: i2c or spi cmd, or gpio index & level,
- * fill 0x0 for no use
- * delay: unit ms
- */
- init_on = <0x00 0x00 0x00 0x00
- 0x00 0x08 0x01 0x00
- 0x00 0x10 0x3F 0x00
- 0x00 0x11 0x00 0x00
- 0x00 0x12 0x00 0x00
- 0x00 0x13 0xE4 0x00
- 0x00 0x14 0x02 0x00
- 0x00 0x15 0x02 0x00
- 0x00 0x16 0x24 0x00
- 0x00 0x17 0x00 0x00
- 0x00 0x18 0x21 0x00
- 0x00 0x20 0x3F 0x00
- 0x00 0x21 0xFF 0x00
- 0x00 0x22 0x00 0x00
- 0x00 0x23 0x00 0x00
- 0x00 0x24 0x00 0x00
- 0x00 0x25 0x00 0x00
- 0x00 0x26 0xE4 0x00
- 0x00 0x27 0x00 0x00
- 0x00 0x28 0x28 0x00
- 0x00 0x29 0x01 0x00
- 0x00 0x2A 0x00 0x00
- 0x00 0x2B 0x01 0x00
- 0x00 0x2C 0x0E 0x00
- 0x00 0x2D 0x00 0x00
- 0x00 0x2E 0x18 0x00
- 0x00 0x2F 0x02 0x00
- 0x00 0x30 0x02 0x00
- 0x00 0x31 0x00 0x00
- 0x00 0x32 0x63 0x00
- 0x00 0x40 0x00 0x00
- 0x00 0x41 0x00 0x00
- 0x00 0x42 0x00 0x00
- 0x00 0x12 0x00 0x00
- 0x00 0x13 0xE4 0x00
- 0x00 0x14 0x02 0x00
- 0x00 0x15 0x00 0x00
- 0x00 0x16 0x0D 0x00
- 0x00 0x17 0x00 0x00
- 0x00 0x18 0x21 0x00
- 0x00 0x41 0x06 0x00
- 0x00 0x00 0x01 0x00
- 0x00 0x08 0x00 0x00
- 0x00 0x10 0x00 0x00
- 0x00 0x11 0x0F 0x00
- 0xff 0x00 0x00 0x00>; /*ending*/
- init_off = <0x00 0x00 0x01 0x00
- 0x00 0x08 0x00 0x00
- 0x00 0x10 0x00 0x00
- 0x00 0x11 0x0F 0x00
- 0xff 0x00 0x00 0x00>; /*ending*/
- };
-
- extern_1{
- index = <1>;
- extern_name = "mipi_TV070WSM";
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- };
-
- extern_2{
- index = <2>;
- extern_name = "mipi_P070ACB";
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- };
- extern_5{
- /* TV101WXM (boe_nvtk_10) */
- index = <5>;
- extern_name = "mipi_default";
- status = "okay";
- type = <2>; /*0=i2c, 1=spi, 2=mipi*/
- cmd_size = <0xff>;
-
- init_on = <
- 0xFF 120
- 0x29 5 0xFF 0xAA 0x55 0x25 0x01
- 0x23 2 0xFC 0x08
- 0xFF 1
- 0x23 2 0xFC 0x00
- 0x29 5 0xFF 0xAA 0x55 0x25 0x00
- 0xFF 20
- 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x00
- 0x29 3 0xB1 0x68 0x01
- 0x29 5 0xB8 0x01 0x02 0x02 0x02
- 0x23 2 0xB6 0x11
- 0x29 3 0xBB 0x63 0x63
- 0x29 3 0xBC 0x00 0x00
- 0x29 6 0xBD 0x02 0xBB 0x11 0x10 0x00
- 0x23 2 0xC8 0x80
- 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x01
- 0x29 3 0xB3 0x28 0x28
- 0x29 3 0xB4 0x14 0x14
- 0x29 3 0xB9 0x44 0x44
- 0x29 3 0xBA 0x24 0x24
- 0x29 3 0xBC 0x70 0x00
- 0x29 3 0xBD 0x70 0x00
- 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x02
- 0x23 2 0xEE 0x03
- 0x29 17 0xB0 0x01 0x04 0x01 0x08 0x01
- 0x11 0x01 0x19 0x01 0x21 0x01
- 0x30 0x01 0x3D 0x01 0x55
- 0x29 17 0xB1 0x01 0x6B 0x01 0x94 0x01
- 0xB5 0x01 0xED 0x02 0x20 0x02
- 0x22 0x02 0x53 0x02 0x8F
- 0x29 17 0xB2 0x02 0xB4 0x02 0xE5 0x03
- 0x03 0x03 0x30 0x03 0x51 0x03
- 0x76 0x03 0x96 0x03 0xB8
- 0x29 5 0xB3 0x03 0xCF 0x03 0xD2
- 0x29 17 0xB4 0x00 0x00 0x00 0x13 0x00
- 0x31 0x00 0x4B 0x00 0x61 0x00
- 0x87 0x00 0xA7 0x00 0xDB
- 0x29 17 0xB5 0x01 0x04 0x01 0x43 0x01
- 0x76 0x01 0xC9 0x02 0x05 0x02
- 0x06 0x02 0x3F 0x02 0x7D
- 0x29 17 0xB6 0x02 0xA3 0x02 0xD3 0x02
- 0xF6 0x03 0x23 0x03 0x44 0x03
- 0x6C 0x03 0x8A 0x03 0xAE
- 0x29 5 0xB7 0x03 0xCF 0x03 0xD2
- 0x29 17 0xB8 0x00 0x41 0x00 0x4A 0x00
- 0x5D 0x00 0x6D 0x00 0x7E 0x00
- 0x9A 0x00 0xB4 0x00 0xDF
- 0x29 17 0xB9 0x01 0x04 0x01 0x43 0x01
- 0x74 0x01 0xC6 0x02 0x03 0x02
- 0x09 0x02 0x40 0x02 0x7E
- 0x29 17 0xBA 0x02 0xA4 0x02 0xD6 0x02
- 0xF7 0x03 0x25 0x03 0x44 0x03
- 0x6C 0x03 0x88 0x03 0xA8
- 0x29 5 0xBB 0x03 0xD0 0x03 0xD2
- 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x03
- 0x29 3 0xB0 0x00 0x00
- 0x29 3 0xB1 0x00 0x00
- 0x29 6 0xB2 0x05 0x01 0x55 0x00 0x1A
- 0x29 6 0xB3 0x05 0x01 0x55 0x00 0x1A
- 0x29 6 0xBA 0x53 0x01 0x55 0x00 0x3A
- 0x23 2 0xC4 0x60
- 0x23 2 0xC5 0x40
- 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x04
- 0x29 5 0xB1 0x03 0x02 0x05 0x07
- 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x05
- 0x29 6 0xBD 0x01 0x03 0x00 0x00 0x03
- 0x23 2 0xC0 0x09
- 0x23 2 0xC1 0x07
- 0x29 3 0xC8 0x07 0x38
- 0x23 2 0xD0 0x00
- 0x23 2 0xE5 0x03
- 0x23 2 0xE6 0x03
- 0x23 2 0xE9 0x03
- 0x23 2 0xEA 0x03
- 0x29 6 0xF0 0x55 0xAA 0x52 0x08 0x06
- 0x29 3 0xB0 0x2D 0x2D
- 0x29 3 0xB1 0x01 0x01
- 0x29 3 0xB2 0x03 0x03
- 0x29 3 0xB3 0x2E 0x2E
- 0x29 3 0xB4 0x2E 0x2D
- 0x29 3 0xB5 0x2D 0x13
- 0x29 3 0xB6 0x13 0x11
- 0x29 3 0xB7 0x11 0x36
- 0x29 3 0xB8 0x36 0x15
- 0x29 3 0xB9 0x15 0x2E
- 0x29 3 0xBA 0x2E 0x14
- 0x29 3 0xBB 0x14 0x35
- 0x29 3 0xBC 0x35 0x10
- 0x29 3 0xBD 0x10 0x12
- 0x29 3 0xBE 0x12 0x2D
- 0x29 3 0xBF 0x2D 0x2E
- 0x29 3 0xC0 0x2E 0x2E
- 0x29 3 0xC1 0x02 0x02
- 0x29 3 0xC2 0x00 0x00
- 0x29 3 0xC3 0x2D 0x2D
- 0x29 3 0xE5 0x34 0x34
- 0x29 3 0xC4 0x2E 0x2E
- 0x29 3 0xC5 0x02 0x02
- 0x29 3 0xC6 0x00 0x00
- 0x29 3 0xC7 0x2D 0x2D
- 0x29 3 0xC8 0x2E 0x2D
- 0x29 3 0xC9 0x2D 0x14
- 0x29 3 0xCA 0x14 0x35
- 0x29 3 0xCB 0x35 0x10
- 0x29 3 0xCC 0x10 0x12
- 0x29 3 0xCD 0x12 0x2E
- 0x29 3 0xCE 0x2E 0x13
- 0x29 3 0xCF 0x13 0x11
- 0x29 3 0xD0 0x11 0x36
- 0x29 3 0xD1 0x36 0x15
- 0x29 3 0xD2 0x15 0x2D
- 0x29 3 0xD3 0x2D 0x2E
- 0x29 3 0xD4 0x2D 0x2D
- 0x29 3 0xD5 0x01 0x01
- 0x29 3 0xD6 0x03 0x03
- 0x29 3 0xD7 0x2E 0x2E
- 0x29 3 0xE6 0x34 0x34
- 0x29 6 0xD8 0x00 0x00 0x00 0x00 0x00
- 0x29 6 0xD9 0x00 0x00 0x00 0x00 0x00
- 0x29 6 0xF0 0x55 0xAA 0x52 0x00 0x00
- 0x23 2 0x35 0x00
- 0x13 1 0x11
- 0xFF 120
- 0x13 1 0x29
-
- 0xFF 0xFF>; /*ending*/
- init_off = <
- 0XFF 5 /* delay 5ms */
- 0x05 1 0x28 /* display off */
- 0xFF 10 /* delay 10ms */
- 0x05 1 0x10 /* sleep in */
- 0xFF 150 /* delay 150ms */
- 0xFF 0xFF>; /*ending*/
- };
- extern_6{
- /* G101B158 (inx_nvtk_10) */
- index = <6>;
- extern_name = "mipi_G101B158";
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- };
- extern_7{
- /* TV101WXM_FT (boe_fiti_10) */
- index = <7>;
- extern_name = "mipi_default";
- status = "okay";
- type = <2>; /*0=i2c, 1=spi, 2=mipi*/
- cmd_size = <0xff>;
-
- init_on = <
- 0xFF 120
- 0x23 2 0xE0 0x00
- 0x23 2 0xE1 0x93
- 0x23 2 0xE2 0x65
- 0x23 2 0xE3 0xF8
- 0x23 2 0x80 0x03
- 0x23 2 0xE0 0x01
- 0x23 2 0x00 0x00
- 0x23 2 0x01 0x6F
- 0x23 2 0x17 0x00
- 0x23 2 0x18 0xAF
- 0x23 2 0x19 0x01
- 0x23 2 0x1A 0x00
- 0x23 2 0x1B 0xAF
- 0x23 2 0x1C 0x01
- 0x23 2 0x1F 0x3E
- 0x23 2 0x20 0x28
- 0x23 2 0x21 0x28
- 0x23 2 0x22 0x7E
- 0x23 2 0x35 0x26
- 0x23 2 0x37 0x09
- 0x23 2 0x38 0x04
- 0x23 2 0x39 0x00
- 0x23 2 0x3A 0x01
- 0x23 2 0x3C 0x78
- 0x23 2 0x3D 0xFF
- 0x23 2 0x3E 0xFF
- 0x23 2 0x3F 0x7F
- 0x23 2 0x40 0x06
- 0x23 2 0x41 0xA0
- 0x23 2 0x42 0x81
- 0x23 2 0x43 0x08
- 0x23 2 0x44 0x0B
- 0x23 2 0x45 0x28
- 0x23 2 0x55 0x0F
- 0x23 2 0x57 0x69
- 0x23 2 0x59 0x0A
- 0x23 2 0x5A 0x28
- 0x23 2 0x5B 0x14
- 0x23 2 0x5D 0x7F
- 0x23 2 0x5E 0x6A
- 0x23 2 0x5F 0x5A
- 0x23 2 0x60 0x4E
- 0x23 2 0x61 0x4A
- 0x23 2 0x62 0x3A
- 0x23 2 0x63 0x3C
- 0x23 2 0x64 0x23
- 0x23 2 0x65 0x39
- 0x23 2 0x66 0x35
- 0x23 2 0x67 0x34
- 0x23 2 0x68 0x51
- 0x23 2 0x69 0x3E
- 0x23 2 0x6A 0x44
- 0x23 2 0x6B 0x34
- 0x23 2 0x6C 0x2E
- 0x23 2 0x6D 0x21
- 0x23 2 0x6E 0x0E
- 0x23 2 0x6F 0x00
- 0x23 2 0x70 0x7F
- 0x23 2 0x71 0x6A
- 0x23 2 0x72 0x5A
- 0x23 2 0x73 0x4E
- 0x23 2 0x74 0x4A
- 0x23 2 0x75 0x3A
- 0x23 2 0x76 0x3C
- 0x23 2 0x77 0x23
- 0x23 2 0x78 0x39
- 0x23 2 0x79 0x35
- 0x23 2 0x7A 0x34
- 0x23 2 0x7B 0x51
- 0x23 2 0x7C 0x3E
- 0x23 2 0x7D 0x44
- 0x23 2 0x7E 0x34
- 0x23 2 0x7F 0x2E
- 0x23 2 0x80 0x21
- 0x23 2 0x81 0x0E
- 0x23 2 0x82 0x00
- 0x23 2 0xE0 0x02
- 0x23 2 0x00 0x1E
- 0x23 2 0x01 0x1E
- 0x23 2 0x02 0x41
- 0x23 2 0x03 0x41
- 0x23 2 0x04 0x43
- 0x23 2 0x05 0x43
- 0x23 2 0x06 0x1F
- 0x23 2 0x07 0x1F
- 0x23 2 0x08 0x35
- 0x23 2 0x09 0x1F
- 0x23 2 0x0A 0x15
- 0x23 2 0x0B 0x15
- 0x23 2 0x0C 0x1F
- 0x23 2 0x0D 0x47
- 0x23 2 0x0E 0x47
- 0x23 2 0x0F 0x45
- 0x23 2 0x10 0x45
- 0x23 2 0x11 0x4B
- 0x23 2 0x12 0x4B
- 0x23 2 0x13 0x49
- 0x23 2 0x14 0x49
- 0x23 2 0x15 0x1F
- 0x23 2 0x16 0x1E
- 0x23 2 0x17 0x1E
- 0x23 2 0x18 0x40
- 0x23 2 0x19 0x40
- 0x23 2 0x1A 0x42
- 0x23 2 0x1B 0x42
- 0x23 2 0x1C 0x1F
- 0x23 2 0x1D 0x1F
- 0x23 2 0x1E 0x35
- 0x23 2 0x1F 0x1F
- 0x23 2 0x20 0x15
- 0x23 2 0x21 0x15
- 0x23 2 0x22 0x1F
- 0x23 2 0x23 0x46
- 0x23 2 0x24 0x46
- 0x23 2 0x25 0x44
- 0x23 2 0x26 0x44
- 0x23 2 0x27 0x4A
- 0x23 2 0x28 0x4A
- 0x23 2 0x29 0x48
- 0x23 2 0x2A 0x48
- 0x23 2 0x2B 0x1F
- 0x23 2 0x58 0x40
- 0x23 2 0x5B 0x30
- 0x23 2 0x5C 0x0F
- 0x23 2 0x5D 0x30
- 0x23 2 0x5E 0x01
- 0x23 2 0x5F 0x02
- 0x23 2 0x63 0x14
- 0x23 2 0x64 0x6A
- 0x23 2 0x67 0x73
- 0x23 2 0x68 0x11
- 0x23 2 0x69 0x14
- 0x23 2 0x6A 0x6A
- 0x23 2 0x6B 0x08
- 0x23 2 0x6C 0x00
- 0x23 2 0x6D 0x00
- 0x23 2 0x6E 0x00
- 0x23 2 0x6F 0x88
- 0x23 2 0x77 0xDD
- 0x23 2 0x79 0x0E
- 0x23 2 0x7A 0x0F
- 0x23 2 0x7D 0x14
- 0x23 2 0x7E 0x82
- 0x23 2 0xE0 0x04
- 0x23 2 0x09 0x11
- 0x23 2 0x0E 0x48
- 0x23 2 0x2B 0x2B
- 0x23 2 0x2D 0x03
- 0x23 2 0x2E 0x44
- 0x23 2 0xE0 0x00
- 0x23 2 0xE6 0x02
- 0x23 2 0xE7 0x0C
- 0x05 1 0x11
- 0xFF 100
- 0x23 2 0xE0 0x03
- 0x23 2 0x2B 0x01
- 0x23 2 0x2C 0x00
- 0x23 2 0x30 0x03
- 0x23 2 0x31 0xFC
- 0x23 2 0x32 0x03
- 0x23 2 0x33 0xF8
- 0x23 2 0x34 0x03
- 0x23 2 0x35 0xF0
- 0x23 2 0x36 0x03
- 0x23 2 0x37 0xE8
- 0x23 2 0x38 0x03
- 0x23 2 0x39 0xE0
- 0x23 2 0x3A 0x03
- 0x23 2 0x3B 0xD0
- 0x23 2 0x3C 0x03
- 0x23 2 0x3D 0xC0
- 0x23 2 0x3E 0x03
- 0x23 2 0x3F 0xA0
- 0x23 2 0x40 0x03
- 0x23 2 0x41 0x80
- 0x23 2 0x42 0x03
- 0x23 2 0x43 0x40
- 0x23 2 0x44 0x03
- 0x23 2 0x45 0x00
- 0x23 2 0x46 0x02
- 0x23 2 0x47 0x80
- 0x23 2 0x48 0x02
- 0x23 2 0x49 0x00
- 0x23 2 0x4A 0x01
- 0x23 2 0x4B 0xFC
- 0x23 2 0x4C 0x01
- 0x23 2 0x4D 0x7C
- 0x23 2 0x4E 0x00
- 0x23 2 0x4F 0xFC
- 0x23 2 0x50 0x00
- 0x23 2 0x51 0xBC
- 0x23 2 0x52 0x00
- 0x23 2 0x53 0x7C
- 0x23 2 0x54 0x00
- 0x23 2 0x55 0x5C
- 0x23 2 0x56 0x00
- 0x23 2 0x57 0x3C
- 0x23 2 0x58 0x00
- 0x23 2 0x59 0x2C
- 0x23 2 0x5A 0x00
- 0x23 2 0x5B 0x1C
- 0x23 2 0x5C 0x00
- 0x23 2 0x5D 0x14
- 0x23 2 0x5E 0x00
- 0x23 2 0x5F 0x0C
- 0x23 2 0x60 0x00
- 0x23 2 0x61 0x04
- 0x23 2 0x62 0x00
- 0x23 2 0x63 0x00
- 0x23 2 0x64 0x03
- 0x23 2 0x65 0xC9
- 0x23 2 0x66 0x03
- 0x23 2 0x67 0xC6
- 0x23 2 0x68 0x03
- 0x23 2 0x69 0xBE
- 0x23 2 0x6A 0x03
- 0x23 2 0x6B 0xB7
- 0x23 2 0x6C 0x03
- 0x23 2 0x6D 0xB1
- 0x23 2 0x6E 0x03
- 0x23 2 0x6F 0xA3
- 0x23 2 0x70 0x03
- 0x23 2 0x71 0x96
- 0x23 2 0x72 0x03
- 0x23 2 0x73 0x79
- 0x23 2 0x74 0x03
- 0x23 2 0x75 0x5D
- 0x23 2 0x76 0x03
- 0x23 2 0x77 0x26
- 0x23 2 0x78 0x02
- 0x23 2 0x79 0xE9
- 0x23 2 0x7A 0x02
- 0x23 2 0x7B 0x6E
- 0x23 2 0x7C 0x01
- 0x23 2 0x7D 0xF3
- 0x23 2 0x7E 0x01
- 0x23 2 0x7F 0xEF
- 0x23 2 0x80 0x01
- 0x23 2 0x81 0x73
- 0x23 2 0x82 0x00
- 0x23 2 0x83 0xF5
- 0x23 2 0x84 0x00
- 0x23 2 0x85 0xB4
- 0x23 2 0x86 0x00
- 0x23 2 0x87 0x79
- 0x23 2 0x88 0x00
- 0x23 2 0x89 0x5D
- 0x23 2 0x8A 0x00
- 0x23 2 0x8B 0x3C
- 0x23 2 0x8C 0x00
- 0x23 2 0x8D 0x2B
- 0x23 2 0x8E 0x00
- 0x23 2 0x8F 0x1C
- 0x23 2 0x90 0x00
- 0x23 2 0x91 0x14
- 0x23 2 0x92 0x00
- 0x23 2 0x93 0x0C
- 0x23 2 0x94 0x00
- 0x23 2 0x95 0x04
- 0x23 2 0x96 0x00
- 0x23 2 0x97 0x00
- 0x23 2 0xE0 0x00
- 0x05 1 0x29
- 0xFF 0xFF>; /*ending*/
- init_off = <
- 0XFF 5 /* delay 5ms */
- 0x05 1 0x28 /* display off */
- 0xFF 50 /* delay 50ms */
- 0x05 1 0x10 /* sleep in */
- 0xFF 150 /* delay 150ms */
- 0xFF 0xFF>; /*ending*/
- };
- extern_8{
- /* G101B158_FT (inx_fiti_10) */
- index = <8>;
- extern_name = "mipi_default";
- status = "okay";
- type = <2>; /*0=i2c, 1=spi, 2=mipi*/
- cmd_size = <0xff>;
-
- init_on = <
- 0x23 2 0xE0 0x00
- 0x23 2 0xE1 0x93
- 0x23 2 0xE2 0x65
- 0x23 2 0xE3 0xF8
- 0x23 2 0x80 0x03
-
- 0x23 2 0xE0 0x01
- 0x23 2 0x00 0x00
- 0x23 2 0x01 0x5D
- 0x23 2 0x03 0x00
- 0x23 2 0x04 0x64
-
- 0x23 2 0x17 0x00
- 0x23 2 0x18 0xC7
- 0x23 2 0x19 0x01
- 0x23 2 0x1A 0x00
- 0x23 2 0x1B 0xC7
- 0x23 2 0x1C 0x01
-
- 0x23 2 0x1F 0x70
- 0x23 2 0x20 0x2D
- 0x23 2 0x21 0x2D
- 0x23 2 0x22 0x7E
-
- 0x23 2 0x35 0x28
-
- 0x23 2 0x37 0x19
-
- 0x23 2 0x38 0x05
- 0x23 2 0x39 0x00
- 0x23 2 0x3A 0x01
- 0x23 2 0x3C 0x7C
- 0x23 2 0x3D 0xFF
- 0x23 2 0x3E 0xFF
- 0x23 2 0x3F 0x7F
-
- 0x23 2 0x40 0x06
- 0x23 2 0x41 0xA0
- 0x23 2 0x43 0x14
- 0x23 2 0x44 0x17
- 0x23 2 0x45 0x2C
-
- 0x23 2 0x55 0x0F
- 0x23 2 0x57 0x68
- 0x23 2 0x59 0x0A
- 0x23 2 0x5A 0x2E
- 0x23 2 0x5B 0x1A
- 0x23 2 0x5C 0x15
-
- 0x23 2 0x5D 0x7F
- 0x23 2 0x5E 0x61
- 0x23 2 0x5F 0x50
- 0x23 2 0x60 0x43
- 0x23 2 0x61 0x3E
- 0x23 2 0x62 0x2E
- 0x23 2 0x63 0x33
- 0x23 2 0x64 0x1C
- 0x23 2 0x65 0x34
- 0x23 2 0x66 0x33
- 0x23 2 0x67 0x32
- 0x23 2 0x68 0x50
- 0x23 2 0x69 0x3E
- 0x23 2 0x6A 0x46
- 0x23 2 0x6B 0x37
- 0x23 2 0x6C 0x32
- 0x23 2 0x6D 0x24
- 0x23 2 0x6E 0x12
- 0x23 2 0x6F 0x02
- 0x23 2 0x70 0x7F
- 0x23 2 0x71 0x61
- 0x23 2 0x72 0x50
- 0x23 2 0x73 0x43
- 0x23 2 0x74 0x3E
- 0x23 2 0x75 0x2E
- 0x23 2 0x76 0x33
- 0x23 2 0x77 0x1C
- 0x23 2 0x78 0x34
- 0x23 2 0x79 0x33
- 0x23 2 0x7A 0x32
- 0x23 2 0x7B 0x50
- 0x23 2 0x7C 0x3E
- 0x23 2 0x7D 0x46
- 0x23 2 0x7E 0x37
- 0x23 2 0x7F 0x32
- 0x23 2 0x80 0x24
- 0x23 2 0x81 0x12
- 0x23 2 0x82 0x02
-
- 0x23 2 0xE0 0x02
- 0x23 2 0x00 0x52
- 0x23 2 0x01 0x55
- 0x23 2 0x02 0x55
- 0x23 2 0x03 0x50
- 0x23 2 0x04 0x77
- 0x23 2 0x05 0x57
- 0x23 2 0x06 0x55
- 0x23 2 0x07 0x4E
- 0x23 2 0x08 0x4C
- 0x23 2 0x09 0x5F
- 0x23 2 0x0A 0x4A
- 0x23 2 0x0B 0x48
- 0x23 2 0x0C 0x55
- 0x23 2 0x0D 0x46
- 0x23 2 0x0E 0x44
- 0x23 2 0x0F 0x40
- 0x23 2 0x10 0x55
- 0x23 2 0x11 0x55
- 0x23 2 0x12 0x55
- 0x23 2 0x13 0x55
- 0x23 2 0x14 0x55
- 0x23 2 0x15 0x55
-
- 0x23 2 0x16 0x53
- 0x23 2 0x17 0x55
- 0x23 2 0x18 0x55
- 0x23 2 0x19 0x51
- 0x23 2 0x1A 0x77
- 0x23 2 0x1B 0x57
- 0x23 2 0x1C 0x55
- 0x23 2 0x1D 0x4F
- 0x23 2 0x1E 0x4D
- 0x23 2 0x1F 0x5F
- 0x23 2 0x20 0x4B
- 0x23 2 0x21 0x49
- 0x23 2 0x22 0x55
- 0x23 2 0x23 0x47
- 0x23 2 0x24 0x45
- 0x23 2 0x25 0x41
- 0x23 2 0x26 0x55
- 0x23 2 0x27 0x55
- 0x23 2 0x28 0x55
- 0x23 2 0x29 0x55
- 0x23 2 0x2A 0x55
- 0x23 2 0x2B 0x55
-
- 0x23 2 0x2C 0x13
- 0x23 2 0x2D 0x15
- 0x23 2 0x2E 0x15
- 0x23 2 0x2F 0x01
- 0x23 2 0x30 0x37
- 0x23 2 0x31 0x17
- 0x23 2 0x32 0x15
- 0x23 2 0x33 0x0D
- 0x23 2 0x34 0x0F
- 0x23 2 0x35 0x15
- 0x23 2 0x36 0x05
- 0x23 2 0x37 0x07
- 0x23 2 0x38 0x15
- 0x23 2 0x39 0x09
- 0x23 2 0x3A 0x0B
- 0x23 2 0x3B 0x11
- 0x23 2 0x3C 0x15
- 0x23 2 0x3D 0x15
- 0x23 2 0x3E 0x15
- 0x23 2 0x3F 0x15
- 0x23 2 0x40 0x15
- 0x23 2 0x41 0x15
-
- 0x23 2 0x42 0x12
- 0x23 2 0x43 0x15
- 0x23 2 0x44 0x15
- 0x23 2 0x45 0x00
- 0x23 2 0x46 0x37
- 0x23 2 0x47 0x17
- 0x23 2 0x48 0x15
- 0x23 2 0x49 0x0C
- 0x23 2 0x4A 0x0E
- 0x23 2 0x4B 0x15
- 0x23 2 0x4C 0x04
- 0x23 2 0x4D 0x06
- 0x23 2 0x4E 0x15
- 0x23 2 0x4F 0x08
- 0x23 2 0x50 0x0A
- 0x23 2 0x51 0x10
- 0x23 2 0x52 0x15
- 0x23 2 0x53 0x15
- 0x23 2 0x54 0x15
- 0x23 2 0x55 0x15
- 0x23 2 0x56 0x15
- 0x23 2 0x57 0x15
-
- 0x23 2 0x58 0x40
- 0x23 2 0x5B 0x10
- 0x23 2 0x5C 0x12
- 0x23 2 0x5D 0x40
- 0x23 2 0x5E 0x00
- 0x23 2 0x5F 0x00
- 0x23 2 0x60 0x40
- 0x23 2 0x61 0x03
- 0x23 2 0x62 0x04
- 0x23 2 0x63 0x6C
- 0x23 2 0x64 0x6C
- 0x23 2 0x65 0x75
- 0x23 2 0x66 0x14
- 0x23 2 0x67 0xB4
- 0x23 2 0x68 0x14
- 0x23 2 0x69 0x6C
- 0x23 2 0x6A 0x6C
- 0x23 2 0x6B 0x0C
- 0x23 2 0x6D 0x04
- 0x23 2 0x6E 0x00
- 0x23 2 0x6F 0x88
- 0x23 2 0x75 0xBB
- 0x23 2 0x76 0x02
- 0x23 2 0x77 0x00
- 0x23 2 0x78 0x02
-
- 0x23 2 0xE0 0x03
- 0x23 2 0xAF 0x20
-
-
- 0x23 2 0xE0 0x04
- 0x23 2 0x09 0x11
- 0x23 2 0x0E 0x48
- 0x23 2 0x2B 0x2B
- 0x23 2 0x2D 0x03
- 0x23 2 0x2E 0x44
- 0x23 2 0x41 0xFF
-
- 0x23 2 0xE0 0x05
- 0x23 2 0x12 0x72
-
- 0x23 2 0xE0 0x00
- 0x23 2 0xE6 0x02
- 0x23 2 0xE7 0x0C
-
- 0x23 2 0x53 0x2C
-
- 0x05 1 0x11
- 0xff 120
-
- 0x23 2 0xE0 0x03
- 0x23 2 0x2B 0x01
- 0xff 10
- 0x23 2 0x2C 0x01
-
- 0x23 2 0x30 0x03
- 0x23 2 0x31 0xDE
- 0x23 2 0x32 0x03
- 0x23 2 0x33 0xDA
- 0x23 2 0x34 0x03
- 0x23 2 0x35 0xD1
- 0x23 2 0x36 0x03
- 0x23 2 0x37 0xC9
- 0x23 2 0x38 0x03
- 0x23 2 0x39 0xC1
- 0x23 2 0x3A 0x03
- 0x23 2 0x3B 0xB3
- 0x23 2 0x3C 0x03
- 0x23 2 0x3D 0xA4
- 0x23 2 0x3E 0x03
- 0x23 2 0x3F 0x83
- 0x23 2 0x40 0x03
- 0x23 2 0x41 0x62
- 0x23 2 0x42 0x03
- 0x23 2 0x43 0x23
- 0x23 2 0x44 0x02
- 0x23 2 0x45 0xE4
- 0x23 2 0x46 0x02
- 0x23 2 0x47 0x67
- 0x23 2 0x48 0x01
- 0x23 2 0x49 0xEC
- 0x23 2 0x4A 0x01
- 0x23 2 0x4B 0xE8
- 0x23 2 0x4C 0x01
- 0x23 2 0x4D 0x6D
- 0x23 2 0x4E 0x00
- 0x23 2 0x4F 0xF2
- 0x23 2 0x50 0x00
- 0x23 2 0x51 0xB2
- 0x23 2 0x52 0x00
- 0x23 2 0x53 0x76
- 0x23 2 0x54 0x00
- 0x23 2 0x55 0x58
- 0x23 2 0x56 0x00
- 0x23 2 0x57 0x39
- 0x23 2 0x58 0x00
- 0x23 2 0x59 0x2A
- 0x23 2 0x5A 0x00
- 0x23 2 0x5B 0x1B
- 0x23 2 0x5C 0x00
- 0x23 2 0x5D 0x13
- 0x23 2 0x5E 0x00
- 0x23 2 0x5F 0x0B
- 0x23 2 0x60 0x00
- 0x23 2 0x61 0x04
- 0x23 2 0x62 0x00
- 0x23 2 0x63 0x00
-
- 0x23 2 0x64 0x03
- 0x23 2 0x65 0xE7
- 0x23 2 0x66 0x03
- 0x23 2 0x67 0xE4
- 0x23 2 0x68 0x03
- 0x23 2 0x69 0xDD
- 0x23 2 0x6A 0x03
- 0x23 2 0x6B 0xD5
- 0x23 2 0x6C 0x03
- 0x23 2 0x6D 0xCE
- 0x23 2 0x6E 0x03
- 0x23 2 0x6F 0xBF
- 0x23 2 0x70 0x03
- 0x23 2 0x71 0xB2
- 0x23 2 0x72 0x03
- 0x23 2 0x73 0x93
- 0x23 2 0x74 0x03
- 0x23 2 0x75 0x71
- 0x23 2 0x76 0x03
- 0x23 2 0x77 0x33
- 0x23 2 0x78 0x02
- 0x23 2 0x79 0xF4
- 0x23 2 0x7A 0x02
- 0x23 2 0x7B 0x75
- 0x23 2 0x7C 0x01
- 0x23 2 0x7D 0xF7
- 0x23 2 0x7E 0x01
- 0x23 2 0x7F 0xF3
- 0x23 2 0x80 0x01
- 0x23 2 0x81 0x75
- 0x23 2 0x82 0x00
- 0x23 2 0x83 0xF7
- 0x23 2 0x84 0x00
- 0x23 2 0x85 0xB6
- 0x23 2 0x86 0x00
- 0x23 2 0x87 0x7C
- 0x23 2 0x88 0x00
- 0x23 2 0x89 0x5E
- 0x23 2 0x8A 0x00
- 0x23 2 0x8B 0x3F
- 0x23 2 0x8C 0x00
- 0x23 2 0x8D 0x2E
- 0x23 2 0x8E 0x00
- 0x23 2 0x8F 0x1D
- 0x23 2 0x90 0x00
- 0x23 2 0x91 0x15
- 0x23 2 0x92 0x00
- 0x23 2 0x93 0x0C
- 0x23 2 0x94 0x00
- 0x23 2 0x95 0x04
- 0x23 2 0x96 0x00
- 0x23 2 0x97 0x00
-
- 0x23 2 0xE0 0x00
-
- 0x05 1 0x29
- 0xFF 5
- 0xFF 0xFF>; /*ending*/
- init_off = <
- 0XFF 5 /* delay 5ms */
- 0x05 1 0x28 /* display off */
- 0xFF 50 /* delay 50ms */
- 0x05 1 0x10 /* sleep in */
- 0xFF 150 /* delay 150ms */
- 0xFF 0xFF>; /*ending*/
- };
- };
-};/* end of panel */
-
diff --git a/arch/arm/dts/puddy-panel.dtsi b/arch/arm/dts/puddy-panel.dtsi
deleted file mode 100644
index a89cfb7..0000000
--- a/arch/arm/dts/puddy-panel.dtsi
+++ /dev/null
@@ -1,120 +0,0 @@
-/*
- * arch/arm64/boot/dts/amlogic/puddy-panel.dtsi
- *
- * Copyright (C) 2019 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- */
-
-/ {
- lcd{
- compatible = "amlogic, lcd-g12a";
- dev_name = "lcd";
- mode = "tablet";
- status = "okay";
- key_valid = <0>;
- clocks = <&clkc CLKID_MIPI_DSI_HOST
- &clkc CLKID_MIPI_DSI_PHY
- &clkc CLKID_DSI_MEAS_COMP
- &clkc CLKID_VCLK2_ENCL
- &clkc CLKID_VCLK2_VENCL>;
- clock-names = "dsi_host_gate",
- "dsi_phy_gate",
- "dsi_meas",
- "encl_top_gate",
- "encl_int_gate";
- reg = <0x0 0xffd07000 0x0 0x400
- 0x0 0xff644000 0x0 0x2000>;
- interrupts = <0 3 1>;
- interrupt-names = "vsync";
- pinctrl_version = <2>; /* for uboot */
-
- /* power type:
- * (0=cpu_gpio, 1=pmu_gpio, 2=signal,3=extern, 0xff=ending)
- * power index:
- * (point gpios_index, or extern_index,0xff=invalid)
- * power value:(0=output low, 1=output high, 2=input)
- * power delay:(unit in ms)
- */
- lcd_cpu-gpios = <&gpio GPIOZ_11 GPIO_ACTIVE_HIGH>;
- lcd_cpu_gpio_names = "GPIOZ_11";
-
- inx_dzd_8{
- model_name = "P080DZD";
- interface = "mipi";
- basic_setting = <800 1280 /*h_active, v_active*/
- 864 1466 /*h_period, v_period*/
- 8 /*lcd_bits*/
- 800 1280>; /*screen_width, screen_height*/
- lcd_timing = <14 25 0 /*hs_width,hs_bp,hs_pol*/
- 8 32 0>; /*vs_width,vs_bp,vs_pol*/
- clk_attr = <0 /*fr_adj_type(0=clock,1=htotal,2=vtotal)*/
- 0 /*clk_ss_level*/
- 1 /*clk_auto_generate*/
- 76000000>; /*pixel_clk(unit in Hz)*/
- mipi_attr = <4 /*lane_num*/
- 486 /*bit_rate_max(MHz)*/
- 0 /*factor(*100, default 0 for auto)*/
- 1 /*operation_mode_init(0=video, 1=command)*/
- 0 /*operation_mode_display(0=video, 1=command)*/
- 2 /*
- *video_mode_type
- *(0=sync_pulse,1=sync_event,2=burst)
- */
- 0 /*clk_lp_continuous(0=stop,1=continue)*/
- 0>; /*phy_stop_wait(0=auto,1=standard,2=slow)*/
- /* dsi_init: data_type, num, data... */
- dsi_init_on = <
- 0xff 120 /* delay 10ms */
- 0xf0 3 0 1 40 /* reset high, delay 30ms */
- 0xfc 2 4 3 /* mipi state check */
- 0xff 10 /* delay 10 ms */
- 0x05 1 0x11
- 0xff 100
- 0x05 1 0x29
- 0xff 0xff>; /* ending flag */
- dsi_init_off = <
- 0x05 1 0x28
- 0xff 100
- 0x05 1 0x10
- 0xff 100
- 0xf0 3 0 0 100
- 0xff 0xff>; /* ending flag */
- /* extern_init: 0xff for invalid */
- extern_init = <0xff>;
- /* power step: type,index,value,delay(ms) */
- power_on_step = <
- 2 0 0 0
- 0xff 0 0 0>;
- power_off_step = <
- 2 0 0 50
- 0 0 0 100
- 0xff 0 0 0>;
- backlight_index = <1>;
- };
- };
-
- lcd_extern{
- compatible = "amlogic, lcd_extern";
- dev_name = "lcd_extern";
- status = "okay";
- key_valid = <0>;
-
- extern_0{
- index = <2>;
- extern_name = "mipi_P070ACB";
- status = "okay";
- type = <2>; /* 0=i2c, 1=spi, 2=mipi */
- };
- };
-};/* end of panel */
-
diff --git a/arch/arm/dts/s5pc100-pinctrl.dtsi b/arch/arm/dts/s5pc100-pinctrl.dtsi
deleted file mode 100644
index 290f4cf..0000000
--- a/arch/arm/dts/s5pc100-pinctrl.dtsi
+++ /dev/null
@@ -1,181 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * U-Boot additions to enable a generic Exynos GPIO driver
- *
- * Copyright (c) 2014 Google, Inc
- */
-
-/ {
- pinctrl@e0300000 {
- gpa0: gpa0 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpa1: gpa1 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpb: gpb {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpc: gpc {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpd: gpd {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpe0: gpe0 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpe1: gpe1 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpf0: gpf0 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpf1: gpf1 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpf2: gpf2 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpf3: gpf3 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpg0: gpg0 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpg1: gpg1 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpg2: gpg2 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpg3: gpg3 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpi: gpi {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpj0: gpj0 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpj1: gpj1 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpj2: gpj2 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpj3: gpj3 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpj4: gpj4 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpk0: gpk0 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpk1: gpk1 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpk2: gpk2 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpk3: gpk3 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpl0: gpl0 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpl1: gpl1 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpl2: gpl2 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpl3: gpl3 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gpl4: gpl4 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gph0: gph0 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gph1: gph1 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gph2: gph2 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- gph3: gph3 {
- gpio-controller;
- #gpio-cells = <2>;
- };
-
- };
-};
diff --git a/arch/arm/include/asm/arch-a1/acs.h b/arch/arm/include/asm/arch-a1/acs.h
new file mode 100644
index 0000000..e7190ab
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/acs.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __ACS_H
+#define __ACS_H
+
+#ifndef __ASSEMBLY__
+typedef struct acs_setting{
+ char acs_magic[5]; //acs setting magic word, make sure this piece of data was right.
+ unsigned char chip_type; //chip type
+ unsigned short version; //version of acs_setting struct, for PC tool use.
+ unsigned long acs_set_length; //length of current struct.
+
+ //ddr setting part, 16 bytes
+ char ddr_magic[5]; //magic word to indicate that following 12 bytes was ddr setting.
+ unsigned char ddr_set_version; //struct version, for PC tool use.
+ unsigned short ddr_set_length; //length of ddr struct.
+ unsigned long ddr_set_addr; //address of ddr setting.
+
+#if 0
+ char psram_magic[5];
+ unsigned char psram_set_version;
+ unsigned short psram_set_length;
+ unsigned long psram_set_addr;
+#endif
+ char ddr_reg_magic[5];
+ unsigned char ddr_reg_version;
+ unsigned short ddr_reg_length;
+ unsigned long ddr_reg_addr;
+
+ char pll_magic[5];
+ unsigned char pll_set_version;
+ unsigned short pll_set_length;
+ unsigned long pll_set_addr;
+
+ char sto_magic[5];
+ unsigned char sto_set_version;
+ unsigned short sto_set_length;
+ unsigned long sto_set_addr;
+
+ char bl2_regs_magic[5];
+ unsigned char bl2_regs_version;
+ unsigned short bl2_regs_length;
+ unsigned long bl2_regs_addr;
+
+#if 1
+ char psram_magic[5];
+ unsigned char psram_set_version;
+ unsigned short psram_set_length;
+ unsigned long psram_set_addr;
+#endif
+#if 0
+ char rsv_magic[5];
+ unsigned char rsv_set_version;
+ unsigned short rsv_set_length;
+ unsigned long rsv_set_addr;
+#endif
+ char board_id[12];
+ unsigned short ddr_struct_size[12];
+ unsigned long ddr_struct_org_size;
+}__attribute__ ((packed)) acs_set_t;
+
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-a1/bl31_apis.h b/arch/arm/include/asm/arch-a1/bl31_apis.h
new file mode 100644
index 0000000..a0c78a5
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/bl31_apis.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ * Trustzone API
+ *
+ * Copyright (C) 2012 Amlogic, Inc.
+ *
+ * Author: Platform-SH@amlogic.com
+ *
+ */
+
+#ifndef __GXBB_BL31_APIS_H
+#define __GXBB_BL31_APIS_H
+
+#include <asm/arch/io.h>
+
+/*#define SRAM_READ 0x82000010
+#define CORE_RD_REV1 0x82000011
+#define SRAM_ACS_READ 0x82000012
+#define SRAM_ACS_INDIRECT_READ 0x82000013*/
+
+#define GET_SHARE_MEM_INPUT_BASE 0x82000020
+#define GET_SHARE_MEM_OUTPUT_BASE 0x82000021
+#define GET_REBOOT_REASON 0x82000022
+#define GET_SHARE_STORAGE_IN_BASE 0x82000023
+#define GET_SHARE_STORAGE_OUT_BASE 0x82000024
+#define GET_SHARE_STORAGE_BLOCK_BASE 0x82000025
+#define GET_SHARE_STORAGE_MESSAGE_BASE 0x82000026
+#define GET_SHARE_STORAGE_BLOCK_SIZE 0x82000027
+#define SET_STORAGE_INFO 0x82000028
+#define SET_REBOOT_REASON 0x82000049
+
+/* Set Reboot Reason then Reboot*/
+#define PSCI_SYS_REBOOT 0x84000009
+
+/* SECUREOS DEFINITION*/
+/* SMC Identifiers for non-secure world functions */
+#define CALL_TRUSTZONE_HAL_API 0x5
+
+/* EFUSE */
+#define EFUSE_READ 0x82000030
+#define EFUSE_WRITE 0x82000031
+#define EFUSE_WRITE_PATTERN 0x82000032
+#define EFUSE_USER_MAX 0x82000033
+
+#define DEBUG_EFUSE_WRITE_PATTERN 0x820000F0
+#define DEBUG_EFUSE_READ_PATTERN 0x820000F1
+
+/* JTAG*/
+#define JTAG_ON 0x82000040
+#define JTAG_OFF 0x82000041
+
+#define SET_USB_BOOT_FUNC 0x82000043
+ /* USB BOOT FUNC sub command list*/
+ #define CLEAR_USB_BOOT 1
+ #define FORCE_USB_BOOT 2
+ #define RUN_COMD_USB_BOOT 3
+ #define PANIC_DUMP_USB_BOOT 4
+
+#define GET_CHIP_ID 0x82000044
+
+/* tsensor calibration data */
+#define TSENSOR_CALI_SET 0x8200004C
+
+/*oscring efuse value get */
+#define OSCRING_EFUSE_GET 0x8200004D
+/* Security Key*/
+#define SECURITY_KEY_QUERY 0x82000060
+#define SECURITY_KEY_READ 0x82000061
+#define SECURITY_KEY_WRITE 0x82000062
+#define SECURITY_KEY_TELL 0x82000063
+#define SECURITY_KEY_VERIFY 0x82000064
+#define SECURITY_KEY_STATUS 0x82000065
+#define SECURITY_KEY_NOTIFY 0x82000066
+#define SECURITY_KEY_LIST 0x82000067
+#define SECURITY_KEY_REMOVE 0x82000068
+#define SECURITY_KEY_NOTIFY_EX 0x82000069
+#define SECURITY_KEY_SET_ENCTYPE 0x8200006A
+#define SECURITY_KEY_GET_ENCTYPE 0x8200006B
+#define SECURITY_KEY_VERSION 0x8200006C
+
+/*viu probe en*/
+#define VIU_PREOBE_EN 0x82000080
+/*set boot first timeout*/
+#define SET_BOOT_FIRST 0x82000087
+
+/* KEYMASTER */
+#define SET_BOOT_PARAMS 0x82000072
+#define SHA256_DIGEST_SIZE 32
+typedef struct {
+ uint32_t device_locked;
+ uint32_t verified_boot_state;
+ uint8_t verified_boot_key[SHA256_DIGEST_SIZE];
+ uint8_t verified_boot_hash[SHA256_DIGEST_SIZE];
+} keymaster_boot_params;
+
+/* Secure HAL APIs */
+#define TRUSTZONE_HAL_API_SRAM 0x400
+
+/*start hifi4 */
+#define START_HIFI4 0x82000090
+#define DSP_SEC_POWERSET 0x82000092
+
+
+#define SRAM_HAL_API_CHECK_EFUSE 0x403
+struct sram_hal_api_arg {
+ unsigned int cmd;
+ unsigned int req_len;
+ unsigned int res_len;
+ unsigned long req_phy_addr;
+ unsigned long res_phy_addr;
+ unsigned long ret_phy_addr;
+};
+
+#define JTAG_STATE_ON 0
+#define JTAG_STATE_OFF 1
+#define JTAG_M3_AO 0
+#define JTAG_M3_EE 1
+#define JTAG_A53_AO 2
+#define JTAG_A53_EE 3
+#define CLUSTER_BIT 2
+
+
+/////////////////////////////////////////////////////////////////////////////////
+#define AML_DATA_PROCESS (0x820000FF)
+ #define AML_D_P_W_EFUSE_SECURE_BOOT (0x10)
+ #define AML_D_P_W_EFUSE_PASSWORD (0x11)
+ #define AML_D_P_W_EFUSE_CUSTOMER_ID (0x12)
+ #define AML_D_P_W_EFUSE_AMLOGIC (0x20)
+ #define AML_D_P_IMG_DECRYPT (0x40)
+ #define AML_D_P_UPGRADE_CHECK (0x80)
+
+#define GXB_EFUSE_PATTERN_SIZE (0x500)
+#define GXB_IMG_SIZE (24<<20)
+#define GXB_IMG_LOAD_ADDR (0x1080000)
+ #define GXB_IMG_DEC_KNL (1<<0)
+ #define GXB_IMG_DEC_RMD (1<<1)
+ #define GXB_IMG_DEC_DTB (1<<2)
+ #define GXB_IMG_DEC_ALL (GXB_IMG_DEC_KNL|GXB_IMG_DEC_RMD|GXB_IMG_DEC_DTB)
+
+#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+void aml_set_jtag_state(unsigned state, unsigned select);
+unsigned aml_get_reboot_reason(void);
+unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2);
+void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2);
+unsigned long aml_sec_boot_check(unsigned long ,unsigned long ,unsigned long,unsigned long );
+long get_sharemem_info(unsigned long);
+void set_usb_boot_function(unsigned long command);
+void aml_system_off(void);
+
+void bl31_get_chipid(unsigned int *, unsigned int *,
+ unsigned int *, unsigned int *);
+void set_viu_probe_enable(void);
+void wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value);
+void power_set_dsp(unsigned int id, unsigned int powerflag);
+void init_dsp(unsigned int id,unsigned int addr,unsigned int cfg0);
+void set_boot_first_timeout(uint64_t arg0);
+int bl31_get_cornerinfo(uint8_t *outbuf, int size);
+int32_t set_boot_params(const keymaster_boot_params*);
+#endif
diff --git a/arch/arm/include/asm/arch-a1/board_id.h b/arch/arm/include/asm/arch-a1/board_id.h
new file mode 100644
index 0000000..6488771
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/board_id.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+unsigned int get_board_id(void);
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-a1/clk_measure_tab.h b/arch/arm/include/asm/arch-a1/clk_measure_tab.h
new file mode 100644
index 0000000..87a7941
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/clk_measure_tab.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _ARCH_MESON_A1_MEASURE_H_
+#define _ARCH_MESON_A1_MEASURE_H_
+
+static const char* clk_msr_table[] = {
+ [0] = "tdmout_b_sclk",
+ [1] = "tdmout_a_sclk",
+ [2] = "tdmin_lb_sclk",
+ [3] = "tdmin_b_sclk",
+ [4] = "tdmin_a_sclk",
+ [5] = "vad_clk",
+ [6] = "resampleA_clk",
+ [7] = "pdm_sysclk",
+ [8] = "pdm_dclk",
+ [9] = "locker_out_clk",
+ [10] = "locker_in_clk",
+ [11] = "spdifin_clk",
+ [12] = "tdmin_vad_clk",
+ [13] = "au_adc_clk",
+ [14] = "au_dac_clk",
+ [16] = "spicc_a_clk",
+ [17] = "spifc_clk",
+ [18] = "sd_emmc_a_clk",
+ [19] = "dmcx4_clk",
+ [20] = "dmc_clk",
+ [21] = "psram_clk",
+ [22] = "cecb_clk",
+ [23] = "ceca_clk",
+ [24] = "ts_clk",
+ [25] = "pwm_f_clk",
+ [26] = "pwm_e_clk",
+ [27] = "pwm_d_clk",
+ [28] = "pwm_c_clk",
+ [29] = "pwm_b_clk",
+ [30] = "pwm_a_clk",
+ [31] = "saradc_clk",
+ [32] = "usb_bus",
+ [33] = "dsp_b_clk",
+ [34] = "dsu_a_clk",
+ [35] = "axi_clk",
+ [36] = "sys_clk",
+ [40] = "rng_ring_osc0",
+ [41] = "rng_ring_osc1",
+ [42] = "rng_ring_osc2",
+ [43] = "rng_ring_osc3",
+ [44] = "dds_out",
+ [45] = "cpu_clk_div16",
+ [46] = "gpio_msr",
+ [50] = "osc_ring_cpu0",
+ [51] = "osc_ring_cpu1",
+ [54] = "osc_ring_top0",
+ [55] = "osc_ring_top1",
+ [56] = "osc_ring_ddr",
+ [57] = "osc_ring_dmc",
+ [58] = "osc_ring_dspa",
+ [59] = "osc_ring_dspb",
+ [60] = "osc_ring_rama",
+ [61] = "osc_ring_ramb",
+};
+
+unsigned long clk_util_clk_msr(unsigned long clk_mux);
+int clk_msr(int index);
+
+#endif
diff --git a/arch/arm/include/asm/arch-a1/clock.h b/arch/arm/include/asm/arch-a1/clock.h
new file mode 100644
index 0000000..5fb3394
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/clock.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _ARCH_MESON_A1_CLOCK_H_
+#define _ARCH_MESON_A1_CLOCK_H_
+
+/*
+ * Clock controller register address
+ * APB_BASE: APB0_BASE_ADDR = 0xfe000800
+ */
+#define A1_SYS_OSCIN_CTRL 0x0
+#define A1_RTC_BY_OSCIN_CTRL0 0x4
+#define A1_RTC_BY_OSCIN_CTRL1 0x8
+#define A1_RTC_CTRL 0xc
+#define A1_SYS_CLK_CTRL0 0x10
+#define A1_AXI_CLK_CTRL0 0x14
+#define A1_SYS_CLK_EN0 0x1c
+#define A1_SYS_CLK_EN1 0x20
+#define A1_AXI_CLK_EN 0x24
+#define A1_DSPA_CLK_EN 0x28
+#define A1_DSPB_CLK_EN 0x2c
+#define A1_DSPA_CLK_CTRL0 0x30
+#define A1_DSPB_CLK_CTRL0 0x34
+#define A1_CLK12_24_CTRL 0x38
+#define A1_GEN_CLK_CTRL 0x3c
+#define A1_TIMESTAMP_CTRL0 0x40
+#define A1_TIMESTAMP_CTRL1 0x44
+#define A1_TIMESTAMP_CTRL2 0x48
+#define A1_TIMESTAMP_VAL0 0x4c
+#define A1_TIMESTAMP_VAL1 0x50
+#define A1_TIMEBASE_CTRL0 0x54
+#define A1_TIMEBASE_CTRL1 0x58
+#define A1_SAR_ADC_CLK_CTRL 0xc0
+#define A1_PWM_CLK_AB_CTRL 0xc4
+#define A1_PWM_CLK_CD_CTRL 0xc8
+#define A1_PWM_CLK_EF_CTRL 0xcc
+#define A1_SPICC_CLK_CTRL 0xd0
+#define A1_TS_CLK_CTRL 0xd4
+#define A1_SPIFC_CLK_CTRL 0xd8
+#define A1_USB_BUSCLK_CTRL 0xdc
+#define A1_SD_EMMC_CLK_CTRL 0xe0
+#define A1_CECA_CLK_CTRL0 0xe4
+#define A1_CECA_CLK_CTRL1 0xe8
+#define A1_CECB_CLK_CTRL0 0xec
+#define A1_CECB_CLK_CTRL1 0xf0
+#define A1_PSRAM_CLK_CTRL 0xf4
+#define A1_DMC_CLK_CTRL 0xf8
+#define A1_FCLK_DIV1_SEL 0xfc
+#define A1_TST_CTRL 0x100
+
+/*
+ * For PLl register offset
+ * APB_BASE: APB0_BASE_ADDR = 0xfe007c00
+ */
+/*
+ * basic clocks and pll clocks address
+ * are not continuous, add 0x7400 for each clock
+ */
+#define A1_ANACTRL_FIXPLL_CTRL0 (0x80 + 0x7400)
+#define A1_ANACTRL_FIXPLL_CTRL1 (0x84 + 0x7400)
+#define A1_ANACTRL_FIXPLL_CTRL2 (0x88 + 0x7400)
+#define A1_ANACTRL_FIXPLL_CTRL3 (0x8c + 0x7400)
+#define A1_ANACTRL_FIXPLL_CTRL4 (0x90 + 0x7400)
+#define A1_ANACTRL_FIXPLL_STS (0x94 + 0x7400)
+#define A1_ANACTRL_SYSPLL_CTRL0 (0x100 + 0x7400)
+#define A1_ANACTRL_SYSPLL_CTRL1 (0x104 + 0x7400)
+#define A1_ANACTRL_SYSPLL_CTRL2 (0x108 + 0x7400)
+#define A1_ANACTRL_SYSPLL_CTRL3 (0x10c + 0x7400)
+#define A1_ANACTRL_SYSPLL_CTRL4 (0x110 + 0x7400)
+#define A1_ANACTRL_SYSPLL_STS (0x114 + 0x7400)
+#define A1_ANACTRL_HIFIPLL_CTRL0 (0x140 + 0x7400)
+#define A1_ANACTRL_HIFIPLL_CTRL1 (0x144 + 0x7400)
+#define A1_ANACTRL_HIFIPLL_CTRL2 (0x148 + 0x7400)
+#define A1_ANACTRL_HIFIPLL_CTRL3 (0x14c + 0x7400)
+#define A1_ANACTRL_HIFIPLL_CTRL4 (0x150 + 0x7400)
+#define A1_ANACTRL_HIFIPLL_STS (0x154 + 0x7400)
+#define A1_ANACTRL_AUDDDS_CTRL0 (0x180 + 0x7400)
+#define A1_ANACTRL_AUDDDS_CTRL1 (0x184 + 0x7400)
+#define A1_ANACTRL_AUDDDS_CTRL2 (0x188 + 0x7400)
+#define A1_ANACTRL_AUDDDS_CTRL3 (0x18c + 0x7400)
+#define A1_ANACTRL_AUDDDS_CTRL4 (0x190 + 0x7400)
+#define A1_ANACTRL_AUDDDS_STS (0x194 + 0x7400)
+#define A1_ANACTRL_MISCTOP_CTRL0 (0x1c0 + 0x7400)
+#define A1_ANACTRL_POR_CNTL (0x208 + 0x7400)
+
+/*
+ * CPU clok register offset
+ * APB_BASE: APB1_BASE_ADDR = 0xfd000000
+ */
+/* cpu clock will never be used in uboot
+#define CPUCTRL_CLK_CTRL0 0x80
+#define CPUCTRL_CLK_CTRL1 0x84
+*/
+
+#endif
diff --git a/arch/arm/include/asm/arch-a1/core.h b/arch/arm/include/asm/arch-a1/core.h
new file mode 100644
index 0000000..97fd220
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/core.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __CORE_H__
+#define __CORE_H__
+
+int get_core_mpidr(unsigned int cpuid);
+int get_core_idx(unsigned int mpidr);
+int get_core_max(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-a1/cpu.h b/arch/arm/include/asm/arch-a1/cpu.h
new file mode 100644
index 0000000..2a3b929
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/cpu.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+/* #include <config.h> */
+/* #include <asm/plat-cpu.h> */
+/* #include <asm/arch/ddr.h> */
+
+#if 0
+#define CONFIG_AML_MESON 1
+#define CONFIG_AML_MESON_GX 1
+#define CONFIG_AML_MESON_G12A 1
+#endif
+
+/*enable viu probe*/
+#if 0
+#define CONFIG_CMD_VIU_PROBE 1
+#endif
+
+/* for uboot envrionment use */
+/* #define CONFIG_DDR_SIZE 256 */
+
+/* dram */
+#ifdef CONFIG_UBOOT_RUN_IN_SRAM
+#define PHYS_SDRAM_1_BASE 0xFFE00000UL
+#define PHYS_SDRAM_1_SIZE 0x00180000UL
+#else
+#define PHYS_SDRAM_1_BASE 0x00000000UL
+#define PHYS_SDRAM_1_SIZE 0x10000000UL
+#endif
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1_BASE
+
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1_BASE + CONFIG_SYS_TEXT_BASE)
+
+/* console/print buffer */
+#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
+
+/* use "hush" command parser */
+#if 0
+#define CONFIG_SYS_HUSH_PARSER
+#endif
+
+#if 0
+#define CONFIG_DTB_MEM_ADDR 0x1000000
+#endif
+
+#if 0
+#define CONFIG_AML_CUSTOMER_ID (0)
+#endif
+
+#define AML_CUSTOMER_ID (0)
+
+/* #define CONFIG_SILENT_CONSOLE */
+#define CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC
+#define CONFIG_SILENT_U_BOOT_ONLY
+
+/* 2018.03.19 new compress solution, only support BL33 LZ4 compress */
+#define CONFIG_AML_BL33_COMPRESS_ENABLE 1
+
+/* 2018.03.19 G12A only support v3 format for normal & secure boot */
+#define CONFIG_AML_SECURE_BOOT_V3 1
+
+#define NR_CPUS 4
+
+#define CPU_ID_REG SYSCTRL_SEC_STATUS_REG0
+#define PACKAGE_ID_MASK 0xFF
+
+/*A1 SoC has problem to support AES for secure boot, here just disable it*/
+//#define CONFIG_AML_CRYPTO_AES 1
+
+
+/*Flag for enable AES key generate to EFUSE pattern, with this flag only
+AES key will be generated to EFUSE pattern, it can be used for use case
+like the AES key not ready when secure boot enabled for the first time.
+*/
+
+//#define CONFIG_AML_EFUSE_GEN_AES_ONLY 1
+
+#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-a1/cpu_config.h b/arch/arm/include/asm/arch-a1/cpu_config.h
new file mode 100644
index 0000000..45e7e80
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/cpu_config.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _BOOT_ROM_CONFIG_H_
+#define _BOOT_ROM_CONFIG_H_
+
+/***********************************************************
+ * The following constants are GXBB definition
+ **********************************************************/
+#define ROMBOOT_START 0xD9040000
+#define ROM_SIZE (64*1024)
+#define ROMBOOT_END (ROMBOOT_START+ROM_SIZE)
+
+/***********************************************************
+ * AHB-SRAM Total Size 80KB, layout shown as below
+ *
+ * ROMCODE use the top 32KB
+ *
+ * [ 128] 0xD901_3F80 - 0xD901_3FFF Reserved
+ * [ 128] 0xD901_3F00 - 0xD901_3F7F CPUs Boot Entry
+ * [ 256] 0xD901_3E00 - 0xD901_3EFF Debug Info
+ * [ 512] 0xD901_3C00 - 0xD901_3DFF eFuse mirror
+ * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3)
+ * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) *
+ * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) *
+ * [ 26K] 0xD900_C800 - 0xD901_2FFF BL1 Stack, BSS
+ * [ 1K] 0xD900_C400 - 0xD900_C7FF NAND, USB Buffer
+ * [ 1K] 0xD900_C000 - 0xD900_C3FF Reserved
+ *
+ **********************************************************/
+#define RAM_START 0xD9000000
+#define RAM_SIZE (80 * 1024)
+#define BL1_RAM_START (RAM_START + 0xC000)
+#define BL1_RAM_SIZE (32 * 1024)
+#define BL1_RAM_END (BL1_RAM_START + BL1_RAM_SIZE)
+#define BSS_START (BL1_RAM_START + (2 * 1024))
+#define BSS_SIZE (18 * 1024)
+#define _STACK_END (BSS_START + BSS_SIZE + 8*1024)
+#define BL1_EFUSE_MIRROR (BL1_RAM_END - 1024)
+#define P_SHARED_EFUSE_MIRROR (volatile uint32_t *)(BL1_EFUSE_MIRROR)
+#define BL1_DEBUG_BUFFER (BL1_RAM_END - 512)
+#define CPU_BOOT_ENTRY (BL1_DEBUG_BUFFER + 256)
+#define P_SHARED_DEBUG_BUFF (volatile uint32_t *)(BL1_DEBUG_BUFFER)
+#define BL1_SEC_MBX (BL1_RAM_END - 2*1024)
+#define BL1_NAND_BUFF (BL1_RAM_START + 1024)
+#define BL1_USB_BUFF (BL1_NAND_BUFF)
+
+#define MEMORY_LOC RAM_START
+
+#define SRAM_DEBUG_BUFF_SIZE 256
+
+/* BL2 SPL size */
+#define BL2_SIZE (64 * 1024)
+
+//for signature test
+//#define CONFIG_AML_SIG_TEST_BUILD
+
+/* Software SHA2 */
+#define CONFIG_SHA2_SW
+
+/* Hardware SHA2 */
+#define CONFIG_SHA2_HW
+#define SHA2_HW_UPDATE_API
+
+/* Keep timer config in conf.h */
+#define CONFIG_TIMER
+
+/* Bootrom debug info */
+#define CONFIG_DEBUG_INFO
+
+/* Mincrypt RSA library */
+//#define CONFIG_MINCRYPT
+
+/* PolarSSL RSA library */
+#define CONFIG_POLARSSL_RSA
+
+#ifdef CONFIG_POLARSSL_RSA
+#ifndef CONFIG_MALLOC
+#define CONFIG_MALLOC
+#endif /* ! CONFIG_MALLOC */
+#endif /* CONFIG_POLARSSL_RSA */
+
+#endif /* _BOOT_ROM_CONFIG_H_ */
diff --git a/arch/arm/include/asm/arch-a1/cpu_reset.h b/arch/arm/include/asm/arch-a1/cpu_reset.h
new file mode 100644
index 0000000..46f9abf
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/cpu_reset.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _BOOT_ROM_WATCHDOG_H
+#define _BOOT_ROM_WATCHDOG_H
+#include <asm/arch/secure_apb.h>
+
+void reset_system(void);
+
+/* uboot reset interface */
+void reset_cpu(unsigned long flag);
+
+#endif /* _BOOT_ROM_WATCHDOG_H */
diff --git a/arch/arm/include/asm/arch-a1/cpu_sdio.h b/arch/arm/include/asm/arch-a1/cpu_sdio.h
new file mode 100644
index 0000000..46f366a
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/cpu_sdio.h
@@ -0,0 +1,239 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __CPU_SDIO_H__
+#define __CPU_SDIO_H__
+
+#define SD_EMMC_BASE_A 0xFFE03000
+#define SD_EMMC_BASE_B 0xFFE05000
+#define SD_EMMC_BASE_C 0xFFE07000
+
+#define SDIO_PORT_A 0
+#define SDIO_PORT_B 1
+#define SDIO_PORT_C 2
+
+struct sd_emmc_global_regs {
+ volatile uint32_t gclock; // 0x00
+ volatile uint32_t gdelay; // 0x04
+ volatile uint32_t gdelay1; //0x08
+ volatile uint32_t gadjust; // 0x0c
+ volatile uint32_t gcalout; // 0x10
+ volatile uint32_t reserved_14[11]; // 0x14~0x3c
+ volatile uint32_t gstart; // 0x40
+ volatile uint32_t gcfg; // 0x44
+ volatile uint32_t gstatus; // 0x48
+ volatile uint32_t girq_en; // 0x4c
+ volatile uint32_t gcmd_cfg; // 0x50
+ volatile uint32_t gcmd_arg; // 0x54
+ volatile uint32_t gcmd_dat; // 0x58
+ volatile uint32_t gcmd_rsp0; // 0x5c
+ volatile uint32_t gcmd_rsp1; // 0x60
+ volatile uint32_t gcmd_rsp2; // 0x64
+ volatile uint32_t gcmd_rsp3; // 0x68
+ volatile uint32_t reserved_6c; // 0x6c
+ volatile uint32_t gcurr_cfg; // 0x70
+ volatile uint32_t gcurr_arg; // 0x74
+ volatile uint32_t gcurr_dat; // 0x78
+ volatile uint32_t gcurr_rsp; // 0x7c
+ volatile uint32_t gnext_cfg; // 0x80
+ volatile uint32_t gnext_arg; // 0x84
+ volatile uint32_t gnext_dat; // 0x88
+ volatile uint32_t gnext_rsp; // 0x8c
+ volatile uint32_t grxd; // 0x90
+ volatile uint32_t gtxd; // 0x94
+ volatile uint32_t reserved_98[90]; // 0x98~0x1fc
+ volatile uint32_t gdesc[128]; // 0x200
+ volatile uint32_t gping[128]; // 0x400
+ volatile uint32_t gpong[128]; // 0x800
+};
+
+union sd_emmc_setup {
+ uint32_t d32;
+ struct {
+ unsigned bw:3;
+ unsigned fast:1;
+ unsigned par:3;
+ unsigned hcs:1;
+ unsigned sd:1;
+ unsigned sdhc:1;
+ unsigned type:6;
+ unsigned rca:16;
+ } b;
+};
+
+struct sd_emmc_desc_info{
+ uint32_t cmd_info;
+ uint32_t cmd_arg;
+ uint32_t data_addr;
+ uint32_t resp_addr;
+};
+
+struct cmd_cfg{
+ uint32_t length:9;
+ uint32_t block_mode:1;
+ uint32_t r1b:1;
+ uint32_t end_of_chain:1;
+ uint32_t timeout:4;
+ uint32_t no_resp:1;
+ uint32_t no_cmd:1;
+ uint32_t data_io:1;
+ uint32_t data_wr:1;
+ uint32_t resp_nocrc:1;
+ uint32_t resp_128:1;
+ uint32_t resp_num:1;
+ uint32_t data_num:1;
+ uint32_t cmd_index:6;
+ uint32_t error:1;
+ uint32_t owner:1;
+};
+
+struct sd_emmc_status{
+ uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire, for multiple block read, the CRC errors are ORed together.*/
+ uint32_t txd_err:1; /*[8] TX data CRC error, for multiple block write, any one of blocks CRC error. */
+ uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. The owner bit is ¡°0¡±, set cfg_ignore_owner to ignore this error.*/
+ uint32_t resp_err:1; /*[10] Response CRC error.*/
+ uint32_t resp_timeout:1; /*[11] No response received before time limit. The timeout limit is set by cfg_resp_timeout.*/
+ uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. The timeout limit is set by descriptor itself.*/
+ /* Consider the multiple block read/write, set the proper timeout limits.*/
+ uint32_t end_of_chain:1; /*[13] End of Chain IRQ, Normal IRQ. */
+ uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ, Normal IRQ, the descriptor chain execution keeps going on.*/
+ uint32_t irq_sdio:1; /*[15] SDIO device uses DAT[1] to request IRQ. */
+ uint32_t dat_i:8; /*[23:16] Input data signals. */
+ uint32_t cmd_i:1; /*[24] nput response signal. */
+ uint32_t ds:1; /*[25] Input data strobe. */
+ uint32_t bus_fsm:4; /*[29:26] BUS fsm */
+ uint32_t desc_wr_rdy:1; /*[30] Descriptor write back process is done and it is ready for CPU to read.*/
+ uint32_t core_rdy:1; /*[31] desc_busy or sd_emmc_irq or bus_fsm is not idle.*/
+};//__attribute__((__may_alias__));
+
+
+struct sd_emmc_clock{
+ uint32_t div:6; /*[5:0] Clock divider. Frequency = clock source/cfg_div, Maximum divider 63. */
+ /*Clock off: cfg_div==0, the clock is disabled */
+ /*Divider bypass: cfg_div==1, clock source is used as core clock without divider. */
+ uint32_t src:2; /*[7:6] Clock source, 0: Crystal 24MHz, 1: Fix PLL, 850MHz*/
+ /* 2: MPLL, <637MHz, used for 400MHz exactly. 3: different PLL */
+ uint32_t core_phase:2; /*[9:8] Core clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/
+ uint32_t tx_phase:2; /*[11:10] TX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/
+ uint32_t rx_phase:2; /*[13:12] RX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/
+ uint32_t reserved14:2;
+ uint32_t tx_delay:6; /*[21:16] TX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/
+ uint32_t rx_delay:6; /*[27:22] RX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/
+ uint32_t always_on:1; /*[28] 1: Keep clock always on. 0: Clock on/off controlled by activities. */
+ /*Any APB3 access or descriptor execution will keep clock on.*/
+ uint32_t irq_sdio_sleep:1; /*[29] 1: enable IRQ sdio when in sleep mode. */
+ uint32_t irq_sdio_sleep_ds:1;/*[30] 1:enable ds as irq*/
+ uint32_t reserved26:1;
+};
+
+struct sd_emmc_delay{
+ uint32_t dat0:6; /*[3:0] Data 0 delay line. */
+ uint32_t dat1:6; /*[7:4] Data 1 delay line. */
+ uint32_t dat2:6; /*[11:8] Data 2 delay line. */
+ uint32_t dat3:6; /*[15:12] Data 3 delay line. */
+ uint32_t dat4:6; /*[19:16] Data 4 delay line. */
+ uint32_t spare:2;
+};
+
+struct sd_emmc_delay1{
+ uint32_t dat5:6; /*[23:20] Data 5 delay line. */
+ uint32_t dat6:6; /*[27:24] Data 6 delay line. */
+ uint32_t dat7:6; /*[31:28] Data 7 delay line. */
+ uint32_t dat8:6; /*[31:28] Data 7 delay line. */
+ uint32_t dat9:6; /*[31:28] Data 7 delay line. */
+ uint32_t spare:2;
+};
+
+struct sd_emmc_adjust{
+ uint32_t cmd_delay:4; /*[3:0] Command delay line. */
+ uint32_t ds_delay:4; /*[7:4] DS delay line. */
+ uint32_t cali_sel:4; /*[11:8] Select one signal to be tested.*/
+ /*Signals are labeled from 0 to 9 the same as delay lines. */
+ uint32_t cali_enable:1; /*[12] Enable calibration. */
+ uint32_t adj_enable:1; /*[13] Adjust interface timing by resampling the input signals. */
+ uint32_t cali_rise:1; /*[14] 1: test the rising edge. 0: test the falling edge. */
+ uint32_t ds_enable:1; /*[15] Sampling the DAT based on DS in HS400 mode*/
+ uint32_t adj_delay:6; /*[21:16] Resample the input signals when clock index==adj_delay. */
+ uint32_t adj_auto:1; /*[22] Use cali_dut first falling edge to adjust the timing */
+ /*set cali_enable to 1 to use this function*/
+ uint32_t reserved23:9;
+};
+
+
+struct sd_emmc_calout{
+ uint32_t cali_idx:6; /*[5:0] Calibration reading. The event happens at this index. */
+ uint32_t reserved6:1;
+ uint32_t cali_vld:1; /*[7] The reading is valid. */
+ uint32_t cali_setup:8; /*[15:8] Copied from BASE+0x8 [15:8] include cali_sel, cali_enable, adj_enable, cali_rise. */
+ uint32_t reserved16:16;
+};
+
+
+struct sd_emmc_start{
+ uint32_t init:1; /*[0] 1: Read descriptor from internal SRAM, limited to 32 descriptors. */
+ /* 0: Read descriptor from external DDR */
+ uint32_t busy:1; /*[1] 1: Start command chain execution process. 0: Stop */
+ uint32_t addr:30; /*[31:2] Descriptor address, the last 2 bits are 0, 4 bytes aligned. */
+ /* When internal SRAM is used, the valid address range is from 0x200~0x3ff */
+ /* When external DDR is used, the valid address is anywhere in DDR, the length of chain is unlimited.*/
+};//__attribute__((__may_alias__));
+
+
+struct sd_emmc_config{
+ uint32_t bus_width:2; /*[1:0] 0: 1 bit, 1: 4 bits, 2: 8 bits, 3: 2 bits (not supported)*/
+ uint32_t ddr:1; /*[2] 1: DDR mode, 0: SDR mode */
+ uint32_t dc_ugt:1; /*[3] 1: DDR access urgent, 0: DDR access normal. */
+ uint32_t bl_len:4; /*[7:4] Block length 2^cfg_bl_len, because internal buffer size is limited to 512 bytes, the cfg_bl_len <=9. */
+ uint32_t resp_timeout:4; /*[11:8] Wait response till 2^cfg_resp_timeout core clock cycles. Maximum 32768 core cycles. */
+ uint32_t rc_cc:4; /*[15:12] Wait response-command, command-command gap before next command, 2^cfg_rc_cc core clock cycles. */
+ uint32_t out_fall:1; /*[16] DDR mode only. The command and TXD start from rising edge. Set 1 to start from falling edge. */
+ uint32_t blk_gap_ip:1; /*[17] 1: Enable SDIO data block gap interrupt period. 0: Disabled.*/
+ uint32_t spare:1; /*[18] Spare, ??? need check*/
+ uint32_t ignore_owner:1; /*[19] Use this descriptor even if its owner bit is ¡°0¡±.*/
+ uint32_t chk_ds:1; /*[20] Check data strobe in HS400.*/
+ uint32_t cmd_low:1; /*[21] Hold CMD as output Low, eMMC boot mode.*/
+ uint32_t stop_clk:1; /*[22] 1: stop clock. 0: normal clock.*/
+ /*In normal mode, the clock is automatically on/off during reading mode to back off reading in case of*/
+ /*DDR slow response, stop clock is used in voltage switch.*/
+ uint32_t auto_clk:1; /*[23] 1: when BUS is idle and no descriptor is available, turn off clock, to save power.*/
+ /* 0: core clock is always on.*/
+ uint32_t txd_add_err:1; /*[24] TXD add error test*/
+ /*Test feature, should not be used in normal condition.*/
+ /*It will inverted the first CRC bits of the 3rd block.*/
+ /*Block index starts from 0, 1, 2, ¡*/
+ uint32_t txd_retry:1; /*[25] When TXD CRC error, host sends the block again.*/
+ /*The total number of retries of one descriptor is limited to 15, */
+ /*after 15 retries, the TXD_err is set to high.*/
+ uint32_t revd:8; /*[31:26] reved*/
+};//__attribute__((__may_alias__));
+
+
+struct sd_emmc_irq_en{
+ uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire.*/
+ uint32_t txd_err:1; /*[8] TX data CRC error. */
+ uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. */
+ uint32_t resp_err:1; /*[10] Response CRC error.*/
+ uint32_t resp_timeout:1; /*[11] No response received before time limit. */
+ uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. */
+ uint32_t end_of_chain:1; /*[13] End of Chain IRQ. */
+ uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ. */
+ uint32_t irq_sdio:1; /*[15] Enable sdio interrupt. */
+ uint32_t revd:16; /*[31:16] reved*/
+};
+
+struct sd_emmc_data_info{
+ uint32_t cnt:10; /*[9:0] Rxd words received from BUS. Txd words received from DDR.*/
+ uint32_t blk:9; /*[24:16] Rxd Blocks received from BUS. Txd blocks received from DDR.*/
+ uint32_t revd:30; /*[31:17] Reved. */
+};
+
+
+struct sd_emmc_card_info{
+ uint32_t txd_cnt:10; /*[9:0] Txd BUS cycle counter. */
+ uint32_t txd_blk:9; /*[24:16] Txd BUS block counter.*/
+ uint32_t revd:30; /*[31:17] Reved. */
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-a1/ddr.h b/arch/arm/include/asm/arch-a1/ddr.h
new file mode 100644
index 0000000..ad27855
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/ddr.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <io.h>
+#include <stdint.h>
+#include <asm/arch/ddr_define.h>
+
+/* io defines */
+//#define wr_reg(addr, data) (*((volatile uint32_t *)addr))=(uint32_t)(uint64_t)(data)
+//#define rd_reg(addr) (*((volatile uint32_t *)(addr)))
+#define wr_reg(addr, data) writel(data, addr)
+#define rd_reg(addr) readl(addr)
+/*clear [mask] 0 bits in [addr], set these 0 bits with [value] corresponding bits*/
+#define modify_reg(addr, value, mask) wr_reg(addr, ((rd_reg(addr) & (mask)) | (value)))
+#define wait_set(addr, loc) do{}while(0 == (rd_reg(addr) & (1<<loc)));
+#define wait_clr(addr, loc) do{}while(1 == (rd_reg(addr) & (1<<loc)));
+#define wait_equal(addr, data) do{}while(data != (rd_reg(addr)));
+
+/* function defines */
+unsigned int ddr_init(void);
+unsigned int ddr_init_pll(void);
+unsigned int ddr_init_dmc(void);
+unsigned int ddr_init_pctl(void);
+unsigned int hot_boot(void);
+void ddr_print_info(void);
+void ddr_test(void);
+void ddr_pre_init(void);
+void ddr_debug(void);
+
+/* pctl status */
+#define UPCTL_STAT_MASK (7)
+#define UPCTL_STAT_INIT (0)
+#define UPCTL_STAT_CONFIG (1)
+#define UPCTL_STAT_ACCESS (3)
+#define UPCTL_STAT_LOW_POWER (5)
+
+/* pctl cmds */
+#define UPCTL_CMD_INIT (0)
+#define UPCTL_CMD_CONFIG (1)
+#define UPCTL_CMD_GO (2)
+#define UPCTL_CMD_SLEEP (3)
+#define UPCTL_CMD_WAKEUP (4)
+
+/* PUB PIR setting */
+#define PUB_PIR_INIT (1<<0)
+#define PUB_PIR_ZCAL (1<<1)
+#define PUB_PIR_CA (1<<2)
+#define PUB_PIR_PLLINIT (1<<4)
+#define PUB_PIR_DCAL (1<<5)
+#define PUB_PIR_PHYRST (1<<6)
+#define PUB_PIR_DRAMRST (1<<7)
+#define PUB_PIR_DRAMINIT (1<<8)
+#define PUB_PIR_WL (1<<9)
+#define PUB_PIR_QSGATE (1<<10)
+#define PUB_PIR_WLADJ (1<<11)
+#define PUB_PIR_RDDSKW (1<<12)
+#define PUB_PIR_WRDSKW (1<<13)
+#define PUB_PIR_RDEYE (1<<14)
+#define PUB_PIR_WREYE (1<<15)
+#define PUB_PIR_ICPC (1<<16)
+#define PUB_PIR_PLLBYP (1<<17)
+#define PUB_PIR_CTLDINIT (1<<18)
+#define PUB_PIR_RDIMMINIT (1<<19)
+#define PUB_PIR_CLRSR (1<<27)
+#define PUB_PIR_LOCKBYP (1<<28)
+#define PUB_PIR_DCALBYP (1<<29)
+#define PUB_PIR_ZCALBYP (1<<30)
+#define PUB_PIR_INITBYP (1<<31)
+
+/* PHY initialize register (PIR) */
+#define DDR_PIR ((PUB_PIR_ZCAL) |\
+ (PUB_PIR_PLLINIT) |\
+ (PUB_PIR_DCAL) |\
+ (PUB_PIR_PHYRST) |\
+ (PUB_PIR_DRAMRST) |\
+ (PUB_PIR_DRAMINIT) |\
+ (PUB_PIR_WL) |\
+ (PUB_PIR_QSGATE) |\
+ (PUB_PIR_WLADJ) |\
+ (PUB_PIR_RDDSKW) |\
+ (PUB_PIR_WRDSKW) |\
+ (PUB_PIR_RDEYE) |\
+ (PUB_PIR_WREYE) \
+ )
+
+/* PHY general status register (PGSR0) */
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+#define DDR_PGSR0_CHECK() ((rd_reg(DDR0_PUB_PGSR0) != 0xC0000fff) && \
+ (rd_reg(DDR0_PUB_PGSR0) != 0x80000fff))
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define DDR_PGSR0_CHECK()
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define DDR_PGSR0_CHECK()
+#endif
+
+/* other regs */
+#define SCRATCH0 0xC1107D3C
diff --git a/arch/arm/include/asm/arch-a1/ddr_define.h b/arch/arm/include/asm/arch-a1/ddr_define.h
new file mode 100644
index 0000000..2d2697e
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/ddr_define.h
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#define CONFIG_BOARD_ID_MASK 0xFF
+#define CONFIG_DDR_TYPE_DDR3 0
+#define CONFIG_DDR_TYPE_DDR4 1
+#define CONFIG_DDR_TYPE_LPDDR4 2
+#define CONFIG_DDR_TYPE_LPDDR3 3
+#define CONFIG_DDR_TYPE_LPDDR2 4
+#define CONFIG_DDR_TYPE_AUTO 0xf
+
+/* ddr channel defines */
+#define CONFIG_DDR0_16BIT 1
+#define CONFIG_DDR0_RANK0 2
+#define CONFIG_DDR0_RANK01 3
+#define CONFIG_DDR0_16BIT_2 4
+/* CONFIG_DDR_CHL_AUTO mode support RANK0 and RANK0+1 mode auto detect */
+#define CONFIG_DDR_CHL_AUTO 0xF
+#define CONFIG_DDR0_16BIT_CH0 0x1
+#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7
+#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8
+
+#define CFG_DDR_BASE_ADDR 0X0
+#define CFG_DDR_START_OFFSET 0X00000000 //TXLX SKIP 0MB
+
+/* ddr type identifier */
+#define CONFIG_DDR_TIMMING_LPDDR2 0x02
+#define CONFIG_DDR_TIMMING_LPDDR3 0x03
+#define CONFIG_DDR_TIMMING_DDR3_7 0x07
+#define CONFIG_DDR_TIMMING_DDR3_9 0x09
+#define CONFIG_DDR_TIMMING_DDR3_11 0x0B
+#define CONFIG_DDR_TIMMING_DDR3_12 0x0C
+#define CONFIG_DDR_TIMMING_DDR3_13 0x0D
+#define CONFIG_DDR_TIMMING_DDR3_14 0x0E
+
+#define CONFIG_DDR_TIMMING_DDR4_1600 0x0F
+#define CONFIG_DDR_TIMMING_DDR4_1866 0x10
+#define CONFIG_DDR_TIMMING_DDR4_2133 0x11
+#define CONFIG_DDR_TIMMING_DDR4_2400 0x12
+#define CONFIG_DDR_TIMMING_DDR4_2666 0x13
+#define CONFIG_DDR_TIMMING_DDR4_3200 0x14
+
+#define LPDDR_DIE_ROW_COL_R13_C9 0
+#define LPDDR_DIE_ROW_COL_R14_C9 1
+#define LPDDR_DIE_ROW_COL_R14_C10 2
+#define LPDDR_DIE_ROW_COL_R13_C10 3
+#define LPDDR_DIE_ROW_COL_R14_C11 4
+
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE0 0
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE1 1
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE2 2
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE3 3
+
+#define CONFIG_DDR_FUNC_TEST (1<<0)
+
+#define CONFIG_DDR_INIT_RETRY_TOTAL (10)
+#define CONFIG_DDR_PCTL_RETRY_TOTAL (100)
+
+#define DDR_USE_1_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK0) || \
+ (chl_set == CONFIG_DDR0_16BIT))
+#define DDR_USE_2_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK01))
+
+#define DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT 1<<5
+#define DMC_TEST_SLT_ENABLE_DDR_AUTO_WINDOW_TEST 1<<4
+/* DMC_DDR_CTRL defines */
+#define DDR_DDR4_ENABLE (1<<22)
+#define DDR_RANK1_ENABLE (1<<21)
+#define DDR_DDR4_BG_ENABLE (1<<20)
+#define DDR_16BIT_ENABLE (1<<16)
+
+#define DDR_RANK1_SIZE_CTRL (3)
+#define DDR_RANK0_SIZE_CTRL (0)
+
+/* dram cfg magic */
+#define DRAM_CFG_MAGIC 0x2e676663
+
+#define DMC_TEST_SLT_SCAN_FREQUENCY 1
+#define DMC_TEST_SLT_OFFSET_DELAY (1<<1)
+#define DMC_TEST_SLT_ENABLE_DDR_SKIP_TRAINING (1<<6)
+#define DMC_TEST_SLT_ENABLE_DDR_DVFS (1<<7)
+
+/* ddr configs */
+#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+
+#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+#define DDR_RFC_TYPE_LPDDR4_6Gbx1 12
+#define DDR_RFC_TYPE_LPDDR4_8Gbx1 13
+
+#define DDR_ENABLE_FINE_TUNE_FLAG_AC_DELAY (1<<0)
+#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQS (1<<1)
+#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS (1<<2)
+#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ (1<<3)
+#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ (1<<4)
+
+/* lpddr3 defines */
+#ifndef CONFIG_LPDDR_REMAP_SET
+#define CONFIG_LPDDR_REMAP_SET LPDDR_DIE_ROW_COL_R14_C9
+#endif
+
+/* how to add a new ddr function?
+ 1. add CONFIG_DDR_FUNC_XXX in (config).h file
+ 2. add define in this file.
+ 2.1 add
+ #ifndef CONFIG_DDR_FUNC_XXX
+ #define CONFIG_DDR_FUNC_XXX 0
+ #endif
+ 2.2 add
+ #define DDR_FUNC_XXX (CONFIG_FUNC_XXX<<X)
+ 2.3 add DDR_FUNC_XXX |\ in DDR_FUNC
+ 3. add same define and parser in bl2 code
+ */
+/* 2.1, 2,2, 2,3 example */
+/*
+#ifndef CONFIG_CMD_DDR_D2PLL
+#define CONFIG_CMD_DDR_D2PLL 0
+#endif
+#define DDR_FUNC_D2PLL (CONFIG_CMD_DDR_D2PLL<<0)
+#define DDR_FUNC (EXISTING_FUNCTIONS) |\
+ (DDR_FUNC_D2PLL)
+*/
+
+/* d2pll support */
+#ifndef CONFIG_CMD_DDR_D2PLL
+#define CONFIG_CMD_DDR_D2PLL 0
+#endif
+#define DDR_FUNC_D2PLL (CONFIG_CMD_DDR_D2PLL<<0)
+
+/* ddr low power function support */
+#ifndef CONFIG_DDR_LOW_POWER
+#define CONFIG_DDR_LOW_POWER 0
+#endif
+#define DDR_FUNC_LP (CONFIG_DDR_LOW_POWER<<1)
+
+/* ddr zq power down support */
+#ifndef CONFIG_DDR_ZQ_PD
+#define CONFIG_DDR_ZQ_PD 0
+#endif
+#define DDR_FUNC_ZQ_PD (CONFIG_DDR_ZQ_PD<<2)
+
+/* ddr vref function */
+#ifndef CONFIG_DDR_USE_EXT_VREF
+#define CONFIG_DDR_USE_EXT_VREF 0
+#endif
+#define DDR_FUNC_EXT_VREF (CONFIG_DDR_USE_EXT_VREF<<3)
+
+/* ddr4 timing test function */
+#ifndef CONFIG_DDR4_TIMING_TEST
+#define CONFIG_DDR4_TIMING_TEST 0
+#endif
+#define DDR_FUNC_DDR4_TIMING_TEST (CONFIG_DDR4_TIMING_TEST<<4)
+
+/* ddr pll bypass */
+#ifndef CONFIG_DDR_PLL_BYPASS
+#define CONFIG_DDR_PLL_BYPASS 0
+#endif
+#define DDR_FUNC_DDR_PLL_BYPASS (CONFIG_DDR_PLL_BYPASS<<5)
+
+/* ddr rdbi function */
+#ifndef CONFIG_DDR_FUNC_RDBI
+#define CONFIG_DDR_FUNC_RDBI 0
+#endif
+#define DDR_FUNC_RDBI (CONFIG_DDR_FUNC_RDBI<<6)
+
+/* lpddr3 ca trainingi function */
+#ifndef CONFIG_DDR_FUNC_LPDDR3_CA
+#define CONFIG_DDR_FUNC_LPDDR3_CA 0
+#endif
+#define DDR_FUNC_LPDDR3_CA (CONFIG_DDR_FUNC_LPDDR3_CA<<7)
+
+/* print ddr training window */
+#ifndef CONFIG_DDR_FUNC_PRINT_WINDOW
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 0
+#endif
+#define DDR_FUNC_PRINT_WINDOW (CONFIG_DDR_FUNC_PRINT_WINDOW<<8)
+
+
+/* print ddr training window */
+//#ifndef CONFIG_DDR_FULL_TEST
+//#define CONFIG_DDR_FULL_TEST 0
+//#endif
+//#define DDR_FULL_TEST (CONFIG_DDR_FULL_TEST<<10)
+
+/* non-sec region scramble function */
+#ifndef CONFIG_DDR_NONSEC_SCRAMBLE
+#define CONFIG_DDR_NONSEC_SCRAMBLE 0
+#endif
+#define DDR_NONSEC_SCRAMBLE (CONFIG_DDR_NONSEC_SCRAMBLE<<11)
+
+#if(CONFIG_DDR_FUNC_LPDDR3_CA==1)
+#if (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE0)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21)
+#elif (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE1)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (1<<20)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21)
+#elif (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE2)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (1<<21)
+#elif (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE3)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (1<<20)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (1<<21)
+#endif
+#if (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE0)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (0<<22)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (0<<23)
+#elif (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE1)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (1<<22)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (0<<23)
+#elif (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE2)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (0<<22)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (1<<23)
+#elif (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE3)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (1<<22)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (1<<23)
+#endif
+#else /* CONFIG_DDR_FUNC_LPDDR3_CA != 1 */
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (0<<22)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (0<<23)
+#endif /* CONFIG_DDR_FUNC_LPDDR3_CA */
+
+#if(CONFIG_DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP==1)
+#define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP (1<<25)
+#else
+#define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP (0<<25)
+#endif
+#define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1<<30)
+#define DDR_FUNC_CONFIG_DFE_FUNCTION (1<<29)
+#define DDR_FUNC_CONFIG_DDR_DVFS_FUNCTION (1<<28)
+#define DDR_FUNC (DDR_FUNC_D2PLL | \
+ DDR_FUNC_LP | \
+ DDR_FUNC_ZQ_PD | \
+ DDR_FUNC_EXT_VREF | \
+ DDR_FUNC_DDR4_TIMING_TEST | \
+ DDR_FUNC_DDR_PLL_BYPASS | \
+ DDR_FUNC_RDBI | \
+ DDR_FUNC_LPDDR3_CA | \
+ DDR_FUNC_PRINT_WINDOW | \
+ DDR_FULL_TEST | \
+ DDR_NONSEC_SCRAMBLE | \
+ DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0| \
+ DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1| \
+ DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0| \
+ DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1| \
+ DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP | \
+ (1 << 31) \
+ )
+
+
+
+
+/* bl2 reg override stages define */
+#define BL2_INIT_STAGE_0 0
+#define BL2_INIT_STAGE_1 1
+#define BL2_INIT_STAGE_2 2
+#define BL2_INIT_STAGE_3 3
+#define BL2_INIT_STAGE_4 4
+#define BL2_INIT_STAGE_5 5
+#define BL2_INIT_STAGE_6 6
+#define BL2_INIT_STAGE_7 7
+#define BL2_INIT_STAGE_8 8
+#define BL2_INIT_STAGE_9 9
+
+
+/* ddr reg override stages define */
+#define DDR_OVERRIDE_STAGE_DDR3_PRE_INIT 0x10
+#define DDR_OVERRIDE_STAGE_DDR3_DMC_INIT 0x11
+
+#define DDR_OVERRIDE_STAGE_DDR4_PRE_INIT 0x20
+#define DDR_OVERRIDE_STAGE_DDR4_DMC_INIT 0x21
+
+#define DDR_OVERRIDE_STAGE_LPDDR3_PRE_INIT 0x30
+#define DDR_OVERRIDE_STAGE_LPDDR3_DMC_INIT 0x31
+
+#define DDR_OVERRIDE_STAGE_LPDDR4_PRE_INIT 0x40
+#define DDR_OVERRIDE_STAGE_LPDDR4_DMC_INIT 0x41
+
+
+#define DWC_AC_PINMUX_TOTAL 28
+#define DWC_DFI_PINMUX_TOTAL 26
+#define DWC_DQ_PINMUX_TOTAL 32
+
+/* diagnose function defines */
+#define CONFIG_DIAGNOSE_DISABLE 0x0
+#define CONFIG_DIAGNOSE_1D 0x1
+#define CONFIG_DIAGNOSE_2D 0x2
+#define CONFIG_DIAGNOSE_1D_2D 0x3
diff --git a/arch/arm/include/asm/arch-a1/efuse.h b/arch/arm/include/asm/arch-a1/efuse.h
new file mode 100644
index 0000000..4a68e88
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/efuse.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __EFUSE_H
+#define __EFUSE_H
+
+#include <config.h>
+#include <common.h>
+
+/* efuse HAL_API arg */
+struct efuse_hal_api_arg {
+ unsigned int cmd; /* R/W */
+ unsigned int offset;
+ unsigned int size;
+ unsigned long buffer_phy;
+ unsigned long retcnt_phy;
+};
+
+
+#define EFUSE_BYTES 512 /* (EFUSE_BITS/8) */
+
+#define EFUSE_HAL_API_READ 0
+#define EFUSE_HAL_API_WRITE 1
+#define EFUSE_HAL_API_WRITE_PATTERN 2
+#define EFUSE_HAL_API_USER_MAX 3
+
+#define EFUSE_USER_MASK (0x1 << 16)
+#define EFUSE_THERMAL_MASK (0x1 << 17)
+#define EFUSE_THERMAL_VERFLAG_MASK (0x1 << 18)
+#define EFUSE_ENCRYPT_MASK (0x1 << 19)
+
+//#define ASSIST_HW_REV 0x1f53
+
+int efuse_read_usr(char *buf, size_t count, loff_t *ppos);
+int efuse_write_usr(char *buf, size_t count, loff_t *ppos);
+uint32_t efuse_get_max(void);
+ssize_t efuse_read(char *buf, size_t count, loff_t *ppos);
+ssize_t efuse_write(const char *buf, size_t count, loff_t *ppos);
+
+int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg);
+int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg);
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-a1/eth_setup.h b/arch/arm/include/asm/arch-a1/eth_setup.h
new file mode 100644
index 0000000..6e643f6
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/eth_setup.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/io.h>
+
+/*
+ *board configuration interface.
+ * */
+struct eth_clock_conf{
+ int enable;
+ int clock_50MHZ_phase;
+ //add ... as you need.
+};
+
+struct eth_board_socket{
+char *name ;
+int (*eth_clock_configure)(struct eth_clock_conf);
+int (*eth_pinmux_setup)(void);
+int (*eth_hw_reset)(void);
+
+};
+
+
+
+/*
+ *clock define part
+ */
+
+#define ETH_BASE (0xff3f0000)
+#define ETH_PLL_CNTL CBUS_REG_ADDR(0x2050)
+ /* Ethernet ctrl */
+#define ETH_PLL_CNTL_DIVEN (1<<0)
+#define ETH_PLL_CNTL_MACSPD (1<<1)
+#define ETH_PLL_CNTL_DATEND (1<<2)
+#define ETH_PLL_CNTL_DESEND (1<<3)
+
+
+/*
+ please refer following doc for detail
+ @AppNote-M3-ClockTrees.docx
+
+ select clk: -> CBUS_REG(0x1076)
+
+ 7-sys_pll_div2
+ 6-vid2_pll_clk
+ 5-vid_pll_clk
+ 4-aud_pll_clk
+ 3-ddr_pll_clk
+ 2-misc_pll_clk
+ 1-sys_pll_clk
+ 0-XTAL
+
+ clk_freq:800MHz
+ output_clk:50MHz
+ aways,maybe changed for others?
+*/
+
+#define ETH_CLKSRC_XTAL (0)
+#define ETH_CLKSRC_SYS_PLL_CLK (1)
+#define ETH_CLKSRC_MISC_PLL_CLK (2)
+#define ETH_CLKSRC_DDR_PLL_CLK (3)
+#define ETH_CLKSRC_AUD_PLL_CLK (
+#define ETH_CLKSRC_VID_PLL_CLK (5)
+#define ETH_CLKSRC_VID2_PLL_CLK (6)
+#define ETH_CLKSRC_SYS_PLL_DIV2_CLK (7)
+#define CLK_1M (1000000)
+
+typedef union eth_aml_reg0 {
+ /** raw register data */
+ unsigned int d32;
+ /** register bits */
+ struct {
+ unsigned phy_intf_sel:3;
+ unsigned rx_clk_rmii_invert:1;
+ unsigned rgmii_tx_clk_src:1;
+ unsigned rgmii_tx_clk_phase:2;
+ unsigned rgmii_tx_clk_ratio:3;
+ unsigned phy_ref_clk_enable:1;
+ unsigned clk_rmii_i_invert:1;
+ unsigned clk_en:1;
+ unsigned adj_enable:1;
+ unsigned adj_setup:1;
+ unsigned adj_delay:5;
+ unsigned adj_skew:5;
+ unsigned cali_start:1;
+ unsigned cali_rise:1;
+ unsigned cali_sel:3;
+ unsigned rgmii_rx_reuse:1;
+ unsigned eth_urgent:1;
+ } b;
+} eth_aml_reg0_t;
+
+#define ETH_VALIDE_CLKSRC(clk,out_clk) ((clk%out_clk)==0)
+
+int eth_clk_set(int selectclk,unsigned long clk_freq,unsigned long out_clk);
+
diff --git a/arch/arm/include/asm/arch-a1/gpio.h b/arch/arm/include/asm/arch-a1/gpio.h
new file mode 100644
index 0000000..2467368
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/gpio.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_ARCH_MESON_GPIO_H
+#define __ASM_ARCH_MESON_GPIO_H
+
+
+#endif /* __ASM_ARCH_MESON_GPIO_H */
diff --git a/arch/arm/include/asm/arch-a1/i2c.h b/arch/arm/include/asm/arch-a1/i2c.h
new file mode 100644
index 0000000..a93a09d
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/i2c.h
@@ -0,0 +1,280 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AML_MACH_I2C__
+#define __AML_MACH_I2C__
+
+#include <asm/io.h>
+#include <asm/arch/secure_apb.h>
+
+/**
+ * struct i2c_msg - an I2C transaction segment beginning with START
+ * @addr: Slave address, either seven or ten bits. When this is a ten
+ * bit address, I2C_M_TEN must be set in @flags and the adapter
+ * must support I2C_FUNC_10BIT_ADDR.
+ * @flags: I2C_M_RD is handled by all adapters. No other flags may be
+ * provided unless the adapter exported the relevant I2C_FUNC_*
+ * flags through i2c_check_functionality().
+ * @len: Number of data bytes in @buf being read from or written to the
+ * I2C slave address. For read transactions where I2C_M_RECV_LEN
+ * is set, the caller guarantees that this buffer can hold up to
+ * 32 bytes in addition to the initial length byte sent by the
+ * slave (plus, if used, the SMBus PEC); and this value will be
+ * incremented by the number of block data bytes received.
+ * @buf: The buffer into which data is read, or from which it's written.
+ *
+ * An i2c_msg is the low level representation of one segment of an I2C
+ * transaction. It is visible to drivers in the @i2c_transfer() procedure,
+ * to userspace from i2c-dev, and to I2C adapter drivers through the
+ * @i2c_adapter.@master_xfer() method.
+ *
+ * Except when I2C "protocol mangling" is used, all I2C adapters implement
+ * the standard rules for I2C transactions. Each transaction begins with a
+ * START. That is followed by the slave address, and a bit encoding read
+ * versus write. Then follow all the data bytes, possibly including a byte
+ * with SMBus PEC. The transfer terminates with a NAK, or when all those
+ * bytes have been transferred and ACKed. If this is the last message in a
+ * group, it is followed by a STOP. Otherwise it is followed by the next
+ * @i2c_msg transaction segment, beginning with a (repeated) START.
+ *
+ * Alternatively, when the adapter supports I2C_FUNC_PROTOCOL_MANGLING then
+ * passing certain @flags may have changed those standard protocol behaviors.
+ * Those flags are only for use with broken/nonconforming slaves, and with
+ * adapters which are known to support the specific mangling options they
+ * need (one or more of IGNORE_NAK, NO_RD_ACK, NOSTART, and REV_DIR_ADDR).
+ */
+struct i2c_msg {
+ __u16 addr; /* slave address */
+ __u16 flags;
+#define I2C_M_TEN 0x0010 /* this is a ten bit chip address */
+#define I2C_M_RD 0x0001 /* read data, from slave to master */
+#define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_NO_RD_ACK 0x0800 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_RECV_LEN 0x0400 /* length will be first received byte */
+ __u16 len; /* msg length */
+ __u8 *buf; /* pointer to msg data */
+};
+
+#define MESON_I2C_MASTER_AO_START (AO_I2C_M_0_CONTROL_REG)
+//#define MESON_I2C_MASTER_AO_END (0xc810051c+5)
+
+#define MESON_I2C_MASTER_A_START CBUS_REG_ADDR(I2C_M_0_CONTROL_REG)
+#define MESON_I2C_MASTER_A_END (CBUS_REG_ADDR(I2C_M_0_RDATA_REG1+1)-1)
+
+#define MESON_I2C_MASTER_B_START CBUS_REG_ADDR(I2C_M_1_CONTROL_REG)
+#define MESON_I2C_MASTER_B_END (CBUS_REG_ADDR(I2C_M_1_RDATA_REG1+1)-1)
+
+#define MESON_I2C_MASTER_C_START CBUS_REG_ADDR(I2C_M_2_CONTROL_REG)
+#define MESON_I2C_MASTER_C_END (CBUS_REG_ADDR(I2C_M_2_RDATA_REG1+1)-1)
+
+#define MESON_I2C_MASTER_D_START CBUS_REG_ADDR(I2C_M_3_CONTROL_REG)
+#define MESON_I2C_MASTER_D_END (CBUS_REG_ADDR(I2C_M_3_RDATA_REG1+1)-1)
+
+#define MESON_I2C_SLAVE_START CBUS_REG_ADDR(I2C_S_CONTROL_REG)
+#define MESON_I2C_SLAVE_END (CBUS_REG_ADDR(I2C_S_CNTL1_REG+1)-1)
+
+
+#define AML_I2C_MASTER_AO 0
+#define AML_I2C_MASTER_A 1
+#define AML_I2C_MASTER_B 2
+#define AML_I2C_MASTER_C 3
+#define AML_I2C_MASTER_D 4
+
+
+#define AML_I2C_SLAVE_ADDR 0x6c
+
+/*M1 i2c pinmux
+ * I/O I2C_MASTER_A I2C_MASTER_B I2C_SLAVE
+ * GPIO_JTAG_TMS SCK_A REG1[12] SCK_A REG1[13]
+ * GPIO_JTAG_TDI SDA_A REG1[12] SDA_A REG1[13]
+ * GPIO_JTAG_TCK SCK_B REG1[16] SCK_A REG1[17]
+ * GPIO_JTAG_TDO SDA_B REG1[20] SDA_A REG1[21]
+ * GPIOB_0 SCK_B REG2[5] SCK_A REG2[6]
+ * GPIOB_1 SDA_B REG2[2] SDA_A REG2[3]
+ * GPIOB_2 SCK_A REGS[13] SCK_A REG2[14]
+ * GPIOB_3 SDA_A REG2[9] SDA_A REG2[10]
+ * GPIOC_13 SCK_B REG3[28] SCK_A REG3[29]
+ * GPIOC_14 SDA_B REG3[25] SDA_A REG3[26]
+ * GPIOC_21 SCK_A REG7[9] SCK_A REG7[10]
+ * GPIOC_22 SDA_A REG7[6] SDA_A REG7[7]
+ * GPIOE_16 SCK_B REG5[27] SCK_A REG5[28]
+ * GPIOE_17 SDA_B REG5[25] SDA_A REG5[26]
+*/
+
+/*i2c master a*/
+
+
+#define MESON_I2C_MASTER_A_GPIOZ_17_REG (PERIPHS_PIN_MUX_9)
+#define MESON_I2C_MASTER_A_GPIOZ_17_BIT (1<<7)
+#define MESON_I2C_MASTER_A_GPIOZ_18_REG (PERIPHS_PIN_MUX_9)
+#define MESON_I2C_MASTER_A_GPIOZ_18_BIT (1<<8)
+
+#define MESON_I2C_MASTER_A_GPIOW_0_REG (PERIPHS_PIN_MUX_5)
+#define MESON_I2C_MASTER_A_GPIOW_0_BIT (1<<22)
+#define MESON_I2C_MASTER_A_GPIOW_1_REG (PERIPHS_PIN_MUX_5)
+#define MESON_I2C_MASTER_A_GPIOW_1_BIT (1<<23)
+
+/*i2c master b*/
+
+
+#define MESON_I2C_MASTER_B_GPIOH_3_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_B_GPIOH_3_BIT (1<<6)
+#define MESON_I2C_MASTER_B_GPIOH_4_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_B_GPIOH_4_BIT (1<<7)
+
+#define MESON_I2C_MASTER_B_GPIOY_12_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_B_GPIOY_12_BIT (1<<14)
+#define MESON_I2C_MASTER_B_GPIOY_13_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_B_GPIOY_13_BIT (1<<15)
+
+/*i2c master c*/
+#define MESON_I2C_MASTER_C_GPIOY_7_REG (PERIPHS_PIN_MUX_4)
+#define MESON_I2C_MASTER_C_GPIOY_7_BIT (1<<28)
+#define MESON_I2C_MASTER_C_GPIOY_8_REG (PERIPHS_PIN_MUX_4)
+#define MESON_I2C_MASTER_C_GPIOY_8_BIT (1<<29)
+
+#define MESON_I2C_MASTER_C_GPIOX_0_REG (PERIPHS_PIN_MUX_1)
+#define MESON_I2C_MASTER_C_GPIOX_0_BIT (1<<22)
+#define MESON_I2C_MASTER_C_GPIOX_1_REG (PERIPHS_PIN_MUX_1)
+#define MESON_I2C_MASTER_C_GPIOX_1_BIT (1<<23)
+
+/*i2c master d*/
+
+
+#define MESON_I2C_MASTER_D_GPIOY_10_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_D_GPIOY_10_BIT (1<<10)
+#define MESON_I2C_MASTER_D_GPIOY_11_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_D_GPIOY_11_BIT (1<<11)
+
+#define MESON_I2C_MASTER_D_GPIOH_5_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_D_GPIOH_5_BIT (1<<23)
+#define MESON_I2C_MASTER_D_GPIOH_6_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_D_GPIOH_6_BIT (1<<24)
+
+/*i2c master AO*/
+
+
+#define MESON_I2C_MASTER_AO_GPIOAO_4_REG (P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */
+#define MESON_I2C_MASTER_AO_GPIOAO_4_BIT (1<<8)
+#define MESON_I2C_MASTER_AO_GPIOAO_5_REG (P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */
+#define MESON_I2C_MASTER_AO_GPIOAO_5_BIT (1<<9)
+
+/*i2c slave*/
+#define MESON_I2C_SLAVE_JTAG_TMS_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TMS_BIT (1<<13)
+#define MESON_I2C_SLAVE_JTAG_TDI_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TDI_BIT (1<<13)
+
+#define MESON_I2C_SLAVE_GPIOB_2_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_2_BIT (1<<14)
+#define MESON_I2C_SLAVE_GPIOB_3_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_3_BIT (1<<10)
+
+#define MESON_I2C_SLAVE_GPIOC_21_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_7)
+#define MESON_I2C_SLAVE_GPIOC_21_BIT (1<<10)
+#define MESON_I2C_SLAVE_GPIOC_22_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_7)
+#define MESON_I2C_SLAVE_GPIOC_22_BIT (1<<7)
+
+#define MESON_I2C_SLAVE_JTAG_TCK_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TCK_BIT (1<<17)
+#define MESON_I2C_SLAVE_JTAG_TDO_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TDO_BIT (1<<21)
+
+#define MESON_I2C_SLAVE_GPIOB_0_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_0_BIT (1<<6)
+#define MESON_I2C_SLAVE_GPIOB_1_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_1_BIT (1<<3)
+
+#define MESON_I2C_SLAVE_GPIOC_13_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_3)
+#define MESON_I2C_SLAVE_GPIOC_13_BIT (1<<29)
+#define MESON_I2C_SLAVE_GPIOC_14_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_3)
+#define MESON_I2C_SLAVE_GPIOC_14_BIT (1<<26)
+
+#define MESON_I2C_SLAVE_GPIOC_16_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_5)
+#define MESON_I2C_SLAVE_GPIOC_16_BIT (1<<28)
+#define MESON_I2C_SLAVE_GPIOC_17_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_5)
+#define MESON_I2C_SLAVE_GPIOC_17_BIT (1<<26)
+
+
+#define AML_I2C_SPPED_50K 50000
+#define AML_I2C_SPPED_100K 100000
+#define AML_I2C_SPPED_200K 200000
+#define AML_I2C_SPPED_300K 300000
+#define AML_I2C_SPPED_400K 400000
+
+struct aml_pinmux_reg_bit {
+ unsigned long scl_reg;
+ unsigned long sda_reg;
+ unsigned int scl_bit;
+ unsigned int sda_bit;
+};
+
+struct aml_i2c_platform{
+ unsigned int slave_addr;/*7bit addr*/
+ unsigned int wait_count;/*i2c wait ack timeout =
+ wait_count * wait_ack_interval */
+ unsigned int wait_ack_interval;
+ unsigned int wait_read_interval;
+ unsigned int wait_xfer_interval;
+ unsigned int master_no;
+ unsigned int use_pio;/*0: hardware i2c, 1: manual pio i2c*/
+ unsigned int master_i2c_speed;
+
+ /* only need 1 i2c master to comunicate with several devices,
+ * should I prepare 2 master interface to use simultaneously?*/
+ struct resource * resource;
+ struct aml_pinmux_reg_bit master_ao_pinmux;
+ struct aml_pinmux_reg_bit master_a_pinmux;
+ struct aml_pinmux_reg_bit master_b_pinmux;
+ struct aml_pinmux_reg_bit master_c_pinmux;
+ struct aml_pinmux_reg_bit master_d_pinmux;
+
+ struct aml_pinmux_reg_bit slave_reg_bit;
+};
+
+/**************i2c software gpio***************/
+
+#define MESON_I2C_PREG_GPIOC_OE CBUS_REG_ADDR(PREG_FGPIO_EN_N)
+#define MESON_I2C_PREG_GPIOC_OUTLVL CBUS_REG_ADDR(PREG_FGPIO_O)
+#define MESON_I2C_PREG_GPIOC_INLVL CBUS_REG_ADDR(PREG_FGPIO_I)
+
+#define MESON_I2C_PREG_GPIOE_OE CBUS_REG_ADDR(PREG_HGPIO_EN_N)
+#define MESON_I2C_PREG_GPIOE_OUTLVL CBUS_REG_ADDR(PREG_HGPIO_O)
+#define MESON_I2C_PREG_GPIOE_INLVL CBUS_REG_ADDR(PREG_HGPIO_I)
+
+#define MESON_I2C_PREG_GPIOA_OE CBUS_REG_ADDR(PREG_EGPIO_EN_N)
+#define MESON_I2C_PREG_GPIOA_OUTLVL CBUS_REG_ADDR(PREG_EGPIO_O)
+#define MESON_I2C_PREG_GPIOA_INLVL CBUS_REG_ADDR(PREG_EGPIO_I)
+
+struct aml_sw_i2c_pins
+{
+ unsigned int scl_reg_out;
+ unsigned int scl_reg_in;
+ unsigned int scl_bit;
+ unsigned int scl_oe;
+ unsigned int sda_reg_out;
+ unsigned int sda_reg_in;
+ unsigned int sda_bit;
+ unsigned int sda_oe;
+};
+
+
+struct aml_sw_i2c_platform {
+ struct aml_sw_i2c_pins sw_pins;
+
+ /* local settings */
+ int udelay; /* half clock cycle time in us,
+ minimum 2 us for fast-mode I2C,
+ minimum 5 us for standard-mode I2C and SMBus,
+ maximum 50 us for SMBus */
+ int timeout; /* in jiffies */
+};
+
+
+#endif //__AML_MACH_I2C__
+
+
diff --git a/arch/arm/include/asm/arch-a1/io.h b/arch/arm/include/asm/arch-a1/io.h
new file mode 100644
index 0000000..fd3981a
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/io.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __MACH_MESSON_REGS_IO_H
+#define __MACH_MESSON_REGS_IO_H
+
+#ifndef __ASSEMBLY__
+
+#include <asm/io.h>
+#define IO_CBUS_BASE (0xFFD00000L)
+#define IO_AXI_BUS_BASE (0xFFB00000L) /* gpv */
+#define IO_AHB_BUS_BASE (0xFF500000L) /* usb0 */
+#define IO_APB_BUS_BASE (0xFFFC0000L) /* AHB SRAM, sec/sys ahb? txlx_mem_map.xlsx */
+#define IO_APB_HDMI_BUS_BASE (0xFFE00000L) /* */
+#define IO_VPU_BUS_BASE (0xFF900000L) /* VPU */
+
+#define CBUS_REG_OFFSET(reg) ((reg) << 2)
+#define CBUS_REG_ADDR(reg) (IO_CBUS_BASE + CBUS_REG_OFFSET(reg))
+
+#define AXI_REG_OFFSET(reg) ((reg) << 2)
+#define AXI_REG_ADDR(reg) (IO_AXI_BUS_BASE + AXI_REG_OFFSET(reg))
+
+#define AHB_REG_OFFSET(reg) ((reg) << 2)
+#define AHB_REG_ADDR(reg) (IO_AHB_BUS_BASE + AHB_REG_OFFSET(reg))
+
+#define VPU_REG_OFFSET(reg) ((reg) << 2)
+#define VPU_REG_ADDR(reg) (IO_VPU_BUS_BASE + VPU_REG_OFFSET(reg))
+
+
+#define APB_REG_OFFSET(reg) (reg)
+#define APB_REG_ADDR(reg) (IO_APB_BUS_BASE + APB_REG_OFFSET(reg))
+#define APB_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0)
+
+#define APB_HDMI_REG_OFFSET(reg) (reg)
+#define APB_HDMI_REG_ADDR(reg) (IO_APB_HDMI_BUS_BASE + APB_HDMI_REG_OFFSET(reg))
+#define APB_HDMI_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0)
+
+
+#define WRITE_CBUS_REG(reg, val) __raw_writel(val, CBUS_REG_ADDR(reg))
+#define READ_CBUS_REG(reg) (__raw_readl(CBUS_REG_ADDR(reg)))
+#define WRITE_CBUS_REG_BITS(reg, val, start, len) \
+ WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_CBUS_REG_BITS(reg, start, len) \
+ ((READ_CBUS_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)&(~(mask))))
+#define SET_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)|(mask)))
+
+#define WRITE_AXI_REG(reg, val) __raw_writel(val, AXI_REG_ADDR(reg))
+#define READ_AXI_REG(reg) (__raw_readl(AXI_REG_ADDR(reg)))
+#define WRITE_AXI_REG_BITS(reg, val, start, len) \
+ WRITE_AXI_REG(reg, (READ_AXI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_AXI_REG_BITS(reg, start, len) \
+ ((READ_AXI_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)&(~(mask))))
+#define SET_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)|(mask)))
+
+#define WRITE_AHB_REG(reg, val) __raw_writel(val, AHB_REG_ADDR(reg))
+#define READ_AHB_REG(reg) (__raw_readl(AHB_REG_ADDR(reg)))
+#define WRITE_AHB_REG_BITS(reg, val, start, len) \
+ WRITE_AHB_REG(reg, (READ_AHB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_AHB_REG_BITS(reg, start, len) \
+ ((READ_AHB_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)&(~(mask))))
+#define SET_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)|(mask)))
+
+#define WRITE_APB_REG(reg, val) __raw_writel(val, APB_REG_ADDR(reg))
+#define READ_APB_REG(reg) (__raw_readl(APB_REG_ADDR(reg)))
+#define WRITE_APB_REG_BITS(reg, val, start, len) \
+ WRITE_APB_REG(reg, (READ_APB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_APB_REG_BITS(reg, start, len) \
+ ((READ_APB_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)&(~(mask))))
+#define SET_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)|(mask)))
+
+#define WRITE_APB_HDMI_REG(reg, val) __raw_writel(val, APB_HDMI_REG_ADDR(reg))
+#define READ_APB_HDMI_REG(reg) (__raw_readl(APB_HDMI_REG_ADDR(reg)))
+#define WRITE_APB_HDMI_REG_BITS(reg, val, start, len) \
+ WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_APB_HDMI_REG_BITS(reg, start, len) \
+ ((READ_APB_HDMI_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)&(~(mask))))
+#define SET_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)|(mask)))
+
+/* for back compatible alias */
+#define WRITE_MPEG_REG(reg, val) \
+ WRITE_CBUS_REG(reg, val)
+#define READ_MPEG_REG(reg) \
+ READ_CBUS_REG(reg)
+#define WRITE_MPEG_REG_BITS(reg, val, start, len) \
+ WRITE_CBUS_REG_BITS(reg, val, start, len)
+#define READ_MPEG_REG_BITS(reg, start, len) \
+ READ_CBUS_REG_BITS(reg, start, len)
+#define CLEAR_MPEG_REG_MASK(reg, mask) \
+ CLEAR_CBUS_REG_MASK(reg, mask)
+#define SET_MPEG_REG_MASK(reg, mask) \
+ SET_CBUS_REG_MASK(reg, mask)
+#endif
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-a1/mailbox.h b/arch/arm/include/asm/arch-a1/mailbox.h
new file mode 100644
index 0000000..04ae20f
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/mailbox.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+ /*
+ *
+ * Copyright (C) 2012 Amlogic, Inc.
+ *
+ * Author: Platform-SH@amlogic.com
+ *
+ */
+
+#ifndef __GXBB_MAILBOX_H_
+#define __GXBB_MAILBOX_H_
+
+#define SCPI_CMD_SENSOR_VALUE 0x1C
+#define SCPI_CMD_SET_USR_DATA 0x20
+#define SCPI_CMD_OPEN_SCP_LOG 0xC4
+#define SCPI_CMD_THERMAL_CALIB 0xC5
+
+#define SCPI_CMD_USB_BOOT 0xB0
+#define SCPI_CMD_USB_UNBOOT 0xB1
+#define SCPI_CMD_SDCARD_BOOT 0xB2
+#define SCPI_CMD_CLEAR_BOOT 0xB3
+
+#define SCPI_CMD_REV_PWM_DELT 0x42
+
+#define LOW_PRIORITY 0
+#define HIGH_PRIORITY 1
+
+#define P_SHARE_SRAM_BASE 0xfffa0000
+#define SRAM_SIZE 0x48000
+#define MHU_HIGH_SCP_TO_AP_PAYLOAD (SRAM_SIZE - 0xc00)
+#define MHU_HIGH_AP_TO_SCP_PAYLOAD (MHU_HIGH_SCP_TO_AP_PAYLOAD + 0x200)
+#define MHU_LOW_SCP_TO_AP_PAYLOAD (SRAM_SIZE - 0x1000)
+#define MHU_LOW_AP_TO_SCP_PAYLOAD (MHU_LOW_SCP_TO_AP_PAYLOAD + 0x200)
+
+enum scpi_client_id {
+ SCPI_CL_NONE,
+ SCPI_CL_CLOCKS,
+ SCPI_CL_DVFS,
+ SCPI_CL_POWER,
+ SCPI_CL_THERMAL,
+ SCPI_CL_REMOTE,
+ SCPI_CL_LED_TIMER,
+ SCPI_MAX = 0xff,
+};
+
+enum scpi_error_codes {
+ SCPI_SUCCESS = 0, /* Success */
+ SCPI_ERR_PARAM = 1, /* Invalid parameter(s) */
+ SCPI_ERR_ALIGN = 2, /* Invalid alignment */
+ SCPI_ERR_SIZE = 3, /* Invalid size */
+ SCPI_ERR_HANDLER = 4, /* Invalid handler/callback */
+ SCPI_ERR_ACCESS = 5, /* Invalid access/permission denied */
+ SCPI_ERR_RANGE = 6, /* Value out of range */
+ SCPI_ERR_TIMEOUT = 7, /* Timeout has occurred */
+ SCPI_ERR_NOMEM = 8, /* Invalid memory area or pointer */
+ SCPI_ERR_PWRSTATE = 9, /* Invalid power state */
+ SCPI_ERR_SUPPORT = 10, /* Not supported or disabled */
+ SCPI_ERR_DEVICE = 11, /* Device error */
+ SCPI_ERR_MAX
+};
+
+void open_scp_log(unsigned int channel);
+int thermal_calibration(unsigned int type, unsigned int data);
+int thermal_get_value(unsigned int sensor_id, unsigned int *value);
+int send_usr_data(unsigned int clinet_id, unsigned int *val, unsigned int size);
+void send_pwm_delt(int32_t vcck_delt, int32_t ee_delt);
+ #endif
diff --git a/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_ddr3.h b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_ddr3.h
new file mode 100644
index 0000000..c067367
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_ddr3.h
@@ -0,0 +1,637 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief DDR3U_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_DDR3U_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Train vrefDAC0 During Read Deskew
+ // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] = MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] = SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] = SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] = RFU, must be zero (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero)
+ //
+ //
+ //
+ // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] = PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte
+ // 0x0 = All rank populated with all the byte (tyical configuration)
+ //
+ // MsgMisc[7] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware.
+ // Please reference this revision ID when filing support cases with Synopsys.
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Module Type:
+ // 0x01 = DDR3 unbuffered
+ // 0x02 = Reserved
+ // 0x03 = Reserved
+ // 0x04 = Reserved
+ // 0x05 = Reserved
+ //
+ uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7):
+ // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting)
+ uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ // Total number of DQ bits enabled in PHY
+ uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS.
+ //
+ // If the bit is set to 1, the CS is connected to DRAM.
+ // If the bit is set to 0, the CS is not connected to DRAM.
+ //
+ // CsPresent[0] = CS0 is populated with DRAM
+ // CsPresent[1] = CS1 is populated with DRAM
+ // CsPresent[2] = CS2 is populated with DRAM
+ // CsPresent[3] = CS3 is populated with DRAM
+ // CsPresent[7:4] = Reserved (must be programmed to 0)
+ //
+ //
+ uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 0
+ uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 1
+ uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ // Corresponds to CS[3:0]
+ // 1 = Address Mirror.
+ // 0 = No Address Mirror.
+ uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ // Additional mode bits.
+ //
+ // Bit fields:
+ // [0] SlowAccessMode :
+ // 1 = 2T Address Timing.
+ // 0 = 1T Address Timing.
+ // [7-1] RFU, must be zero
+ uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[10] = RFU, must be zero
+ // SequenceCtrl[11] = RFU, must be zero
+ // SequenceCtrl[12] = RFU, must be zero
+ // SequenceCtrl[13] = RFU, must be zero
+ // SequenceCtrl[15-14] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A
+
+
+
+ uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D training in: Rd2D, Wr2D
+ //
+ // Reserved1E[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1E[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR6
+ // 2 = limit to +/-4 %VDDQ from MR6
+ // …
+ // 15 = limit to +/-30% VDDQ from MR6
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A
+ // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset.
+ uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ // Value of DDR mode register MR0 for all ranks for current pstate
+ uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Value of DDR mode register MR1 for all ranks for current pstate
+ uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ // Value of DDR mode register MR2 for all ranks for current pstate
+ uint8_t Reserved64; // Byte offset 0x64, CSR Addr 0x54032, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved65; // Byte offset 0x65, CSR Addr 0x54032, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6E; // Byte offset 0x6e, CSR Addr 0x54037, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6F; // Byte offset 0x6f, CSR Addr 0x54037, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved71; // Byte offset 0x71, CSR Addr 0x54038, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved72; // Byte offset 0x72, CSR Addr 0x54039, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved73; // Byte offset 0x73, CSR Addr 0x54039, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl0; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl2; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl3; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl4; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl5; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl7; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7C; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7D; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A
+
+ uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A
+
+ uint8_t Reserved8A; // Byte offset 0x8a, CSR Addr 0x54045, Direction=N/A
+
+ uint8_t Reserved8B; // Byte offset 0x8b, CSR Addr 0x54045, Direction=N/A
+
+ uint8_t Reserved8C; // Byte offset 0x8c, CSR Addr 0x54046, Direction=N/A
+
+ uint8_t Reserved8D; // Byte offset 0x8d, CSR Addr 0x54046, Direction=N/A
+
+ uint8_t Reserved8E; // Byte offset 0x8e, CSR Addr 0x54047, Direction=N/A
+
+ uint8_t Reserved8F; // Byte offset 0x8f, CSR Addr 0x54047, Direction=N/A
+
+ uint8_t Reserved90; // Byte offset 0x90, CSR Addr 0x54048, Direction=N/A
+
+ uint8_t Reserved91; // Byte offset 0x91, CSR Addr 0x54048, Direction=N/A
+
+ uint8_t Reserved92; // Byte offset 0x92, CSR Addr 0x54049, Direction=N/A
+
+ uint8_t Reserved93; // Byte offset 0x93, CSR Addr 0x54049, Direction=N/A
+
+ uint8_t Reserved94; // Byte offset 0x94, CSR Addr 0x5404a, Direction=N/A
+
+ uint8_t Reserved95; // Byte offset 0x95, CSR Addr 0x5404a, Direction=N/A
+
+ uint8_t Reserved96; // Byte offset 0x96, CSR Addr 0x5404b, Direction=N/A
+
+ uint8_t Reserved97; // Byte offset 0x97, CSR Addr 0x5404b, Direction=N/A
+
+ uint8_t Reserved98; // Byte offset 0x98, CSR Addr 0x5404c, Direction=N/A
+
+ uint8_t Reserved99; // Byte offset 0x99, CSR Addr 0x5404c, Direction=N/A
+
+ uint8_t Reserved9A; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=N/A
+
+ uint8_t Reserved9B; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=N/A
+
+ uint8_t Reserved9C; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=N/A
+
+ uint8_t Reserved9D; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=N/A
+
+ uint8_t Reserved9E; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=N/A
+
+ uint8_t Reserved9F; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=N/A
+
+ uint8_t ReservedA0; // Byte offset 0xa0, CSR Addr 0x54050, Direction=N/A
+
+ uint8_t ReservedA1; // Byte offset 0xa1, CSR Addr 0x54050, Direction=N/A
+
+ uint8_t ReservedA2; // Byte offset 0xa2, CSR Addr 0x54051, Direction=N/A
+
+ uint8_t ReservedA3; // Byte offset 0xa3, CSR Addr 0x54051, Direction=N/A
+
+} __attribute__ ((packed)) PMU_SMB_DDR3U_1D_t;
diff --git a/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_ddr4.h b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_ddr4.h
new file mode 100644
index 0000000..6dfd4d0
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_ddr4.h
@@ -0,0 +1,2380 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief DDR4U_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_DDR4U_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Train vrefDAC0 During Read Deskew
+ // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] = MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] = SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] = SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D.
+ // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field
+ //
+ // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] = PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte
+ // 0x0 = All rank populated with all the byte (tyical configuration)
+ //
+ // MsgMisc[7] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware.
+ // Please reference this revision ID when filing support cases with Synopsys.
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Module Type:
+ // 0x01 = Reserved
+ // 0x02 = DDR4 unbuffered
+ // 0x03 = Reserved
+ // 0x04 = Reserved
+ // 0x05 = Reserved
+ //
+ uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7):
+ // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting)
+ uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ // Total number of DQ bits enabled in PHY
+ uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS.
+ //
+ // If the bit is set to 1, the CS is connected to DRAM.
+ // If the bit is set to 0, the CS is not connected to DRAM.
+ //
+ // CsPresent[0] = CS0 is populated with DRAM
+ // CsPresent[1] = CS1 is populated with DRAM
+ // CsPresent[2] = CS2 is populated with DRAM
+ // CsPresent[3] = CS3 is populated with DRAM
+ // CsPresent[7:4] = Reserved (must be programmed to 0)
+ //
+ //
+ uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 0
+ uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 1
+ uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ // Corresponds to CS[3:0]
+ // 1 = Address Mirror.
+ // 0 = No Address Mirror.
+ uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ // Additional mode bits.
+ //
+ // Bit fields:
+ // [0] SlowAccessMode :
+ // 1 = 2T Address Timing.
+ // 0 = 1T Address Timing.
+ // [7-1] RFU, must be zero
+ uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[10] = Run Reserved
+ // SequenceCtrl[11] = Run Reserved
+ // SequenceCtrl[12] = Run Reserved
+ // SequenceCtrl[13] = Run Reserved
+ // SequenceCtrl[15-14] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A
+
+
+
+ uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D training in: Rd2D, Wr2D
+ //
+ // Reserved1E[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1E[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR6
+ // 2 = limit to +/-4 %VDDQ from MR6
+ // …
+ // 15 = limit to +/-30% VDDQ from MR6
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A
+ // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset.
+ uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ // Value of DDR mode register MR0 for all ranks for current pstate
+ uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Value of DDR mode register MR1 for all ranks for current pstate
+ uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ // Value of DDR mode register MR2 for all ranks for current pstate
+ uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ // Value of DDR mode register MR3 for all ranks for current pstate
+ uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value of DDR mode register MR4 for all ranks for current pstate
+ uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value of DDR mode register MR5 for all ranks for current pstate
+ uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0.
+ uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // X16 device map. Corresponds to CS[3:0].
+ // X16Present[0] = CS0 is populated with X16 devices
+ // X16Present[1] = CS1 is populated with X16 devices
+ // X16Present[2] = CS2 is populated with X16 devices
+ // X16Present[3] = CS3 is populated with X16 devices
+ // X16Present[7:4] = Reserved (must be programmed to 0)
+ //
+ // Ranks may not contain mixed device types.
+ uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // controls timing of chip select signals when DDR4 gear-down mode is active
+ // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs
+ // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode
+ uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM:
+ // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0
+ // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0
+ // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0
+ uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM:
+ // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1
+ // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1
+ // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1
+ uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM:
+ // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2
+ // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2
+ // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2
+ uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM:
+ // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3
+ // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3
+ // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3
+ uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM:
+ // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4
+ // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4
+ // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4
+ uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM:
+ // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5
+ // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5
+ // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5
+ uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM:
+ // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6
+ // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6
+ // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6
+ uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM:
+ // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7
+ // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7
+ // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7
+ uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices.
+ uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices.
+ uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices.
+ uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices.
+ uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices.
+ uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices.
+ uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices.
+ uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices.
+ uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices.
+ uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices.
+ uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices.
+ uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices.
+ uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices.
+ uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices.
+ uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices.
+ uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices.
+ uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices.
+ uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices.
+ uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices.
+ uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices.
+ uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices.
+ uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices.
+ uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices.
+ uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices.
+ uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices.
+ uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices.
+ uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices.
+ uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices.
+ uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices.
+ uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices.
+ uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices.
+ uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices.
+ uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices.
+ uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices.
+ uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices.
+ uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices.
+ uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices.
+ uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices.
+ uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices.
+ uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices.
+ uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A
+
+ uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A
+
+ uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in
+ // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1).
+ // RdDBI is dynamically disabled in certain training steps,
+ // and so the [RdDBI disabled] CAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_CAS_L[0] == 0: use value in MR0
+ // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2]
+ // Other bits are ignored
+ uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In
+ // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1).
+ // 2tCK write prambles are dynamically disabled in certain training steps,
+ // and so the [1tCK write preamble] WCAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_WCAS_L[0] == 0: use value in MR2
+ // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3]
+ // Other bits are ignored
+ uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In
+ // Contains various options for training DDR4 Devices.
+ //
+ // Bit fields:
+ //
+ // D4Misc[7:1] RFU, must be zero
+ //
+ // D4Misc[0] = protect memory reset
+ // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training.
+ // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training
+} __attribute__ ((packed)) PMU_SMB_DDR4U_1D_t;
diff --git a/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_ddr4_2d.h b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_ddr4_2d.h
new file mode 100644
index 0000000..35b1e23
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_ddr4_2d.h
@@ -0,0 +1,2282 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief DDR4U_2D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_DDR4U_2D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Train vrefDAC0 During Read Deskew
+ // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] = MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] = SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] = SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D.
+ // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field
+ //
+ // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] = PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte
+ // 0x0 = All rank populated with all the byte (tyical configuration)
+ //
+ // MsgMisc[7] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware.
+ // Please reference this revision ID when filing support cases with Synopsys.
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Module Type:
+ // 0x01 = Reserved
+ // 0x02 = DDR4 unbuffered
+ // 0x03 = Reserved
+ // 0x04 = Reserved
+ // 0x05 = Reserved
+ //
+ uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7):
+ // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting)
+ uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ // Total number of DQ bits enabled in PHY
+ uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS.
+ //
+ // If the bit is set to 1, the CS is connected to DRAM.
+ // If the bit is set to 0, the CS is not connected to DRAM.
+ //
+ // CsPresent[0] = CS0 is populated with DRAM
+ // CsPresent[1] = CS1 is populated with DRAM
+ // CsPresent[2] = CS2 is populated with DRAM
+ // CsPresent[3] = CS3 is populated with DRAM
+ // CsPresent[7:4] = Reserved (must be programmed to 0)
+ //
+ //
+ uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 0
+ uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 1
+ uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ // Corresponds to CS[3:0]
+ // 1 = Address Mirror.
+ // 0 = No Address Mirror.
+ uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ // Additional mode bits.
+ //
+ // Bit fields:
+ // [0] SlowAccessMode :
+ // 1 = 2T Address Timing.
+ // 0 = 1T Address Timing.
+ // [7-1] RFU, must be zero
+ uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = RFU, must be zero
+ // SequenceCtrl[2] = RFU, must be zero
+ // SequenceCtrl[3] = RFU, must be zero
+ // SequenceCtrl[4] = RFU, must be zero
+ // SequenceCtrl[5] = Run rd2D - 2d read dqs training
+ // SequenceCtrl[6] = Run wr2D - 2d write dq training
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = RFU, must be zero
+ // SequenceCtrl[9] = RFU, must be zero
+ // SequenceCtrl[10] = RFU, must be zero
+ // SequenceCtrl[11] = RFU, must be zero
+ // SequenceCtrl[12] = RFU, must be zero
+ // SequenceCtrl[13] = RFU, must be zero
+ // SequenceCtrl[15-14] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t RX2D_TrainOpt; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In
+ // Bit fields, if 2D read training enabled, then use these additional options:
+ // [0] DFE
+ // 1 = Run rx2D with DFE
+ // 0 = Run rx2D with DFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5-7] RFU, must be zero
+ //
+ uint8_t TX2D_TrainOpt; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Bit fields, if 2D write training is enabled, then use these additional options:
+ // [0] FFE
+ // 1 = Train tx2D with FFE
+ // 0 = Train tx2D with FFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5] FFE Decision Algorithm Control
+ // 1 = FFE chooses the drive strength that maximizes the average eye-area across the entire phy.
+ // 0 = FFE chooses the drive strength that maximizes the smallest eye across the entire phy.
+ // [6-7] RFU, must be zero
+ //
+ uint8_t Share2DVrefResult; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // Bitmap that designates the phy's vref source for every pstate
+ // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock.
+ // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training.
+ uint8_t Delay_Weight2D; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye.
+ uint8_t Voltage_Weight2D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye.
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D training in: Rd2D, Wr2D
+ //
+ // Reserved1E[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1E[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR6
+ // 2 = limit to +/-4 %VDDQ from MR6
+ // …
+ // 15 = limit to +/-30% VDDQ from MR6
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ uint8_t R0_RxClkDly_Margin; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R0_VrefDac_Margin; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R0_TxDqDly_Margin; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R0_DeviceVref_Margin; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved29; // Byte offset 0x29, CSR Addr 0x54014, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2A; // Byte offset 0x2a, CSR Addr 0x54015, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2B; // Byte offset 0x2b, CSR Addr 0x54015, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2C; // Byte offset 0x2c, CSR Addr 0x54016, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2D; // Byte offset 0x2d, CSR Addr 0x54016, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2E; // Byte offset 0x2e, CSR Addr 0x54017, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2F; // Byte offset 0x2f, CSR Addr 0x54017, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved31; // Byte offset 0x31, CSR Addr 0x54018, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved32; // Byte offset 0x32, CSR Addr 0x54019, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t R1_RxClkDly_Margin; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R1_VrefDac_Margin; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R1_TxDqDly_Margin; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R1_DeviceVref_Margin; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved37; // Byte offset 0x37, CSR Addr 0x5401b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved39; // Byte offset 0x39, CSR Addr 0x5401c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3A; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3B; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3D; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3E; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3F; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t R2_RxClkDly_Margin; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R2_VrefDac_Margin; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R2_TxDqDly_Margin; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R2_DeviceVref_Margin; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved48; // Byte offset 0x48, CSR Addr 0x54024, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved49; // Byte offset 0x49, CSR Addr 0x54024, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4A; // Byte offset 0x4a, CSR Addr 0x54025, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t R3_RxClkDly_Margin; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R3_VrefDac_Margin; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R3_TxDqDly_Margin; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R3_DeviceVref_Margin; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved57; // Byte offset 0x57, CSR Addr 0x5402b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved58; // Byte offset 0x58, CSR Addr 0x5402c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved59; // Byte offset 0x59, CSR Addr 0x5402c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5B; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5C; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In
+ // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D.
+ //
+ // Reserved5D[0-3]: bitTimeControl
+ // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point.
+ // 0 = 1 kilobit per point (legacy behavior)
+ // 1 = 2 kilobits per point
+ // 2 = 4 kilobits per point
+ // …
+ // 15 = 32 megabits per point
+ //
+ // Reserved5D[4]: Exhaustive2D
+ // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior)
+ // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point.
+ //
+ // Reserved5D[5:7]: RFU, must be 0
+ uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ // Value of DDR mode register MR0 for all ranks for current pstate
+ uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Value of DDR mode register MR1 for all ranks for current pstate
+ uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ // Value of DDR mode register MR2 for all ranks for current pstate
+ uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ // Value of DDR mode register MR3 for all ranks for current pstate
+ uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value of DDR mode register MR4 for all ranks for current pstate
+ uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value of DDR mode register MR5 for all ranks for current pstate
+ uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0.
+ uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // X16 device map. Corresponds to CS[3:0].
+ // X16Present[0] = CS0 is populated with X16 devices
+ // X16Present[1] = CS1 is populated with X16 devices
+ // X16Present[2] = CS2 is populated with X16 devices
+ // X16Present[3] = CS3 is populated with X16 devices
+ // X16Present[7:4] = Reserved (must be programmed to 0)
+ //
+ // Ranks may not contain mixed device types.
+ uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // controls timing of chip select signals when DDR4 gear-down mode is active
+ // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs
+ // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode
+ uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM:
+ // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0
+ // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0
+ // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0
+ uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM:
+ // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1
+ // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1
+ // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1
+ uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM:
+ // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2
+ // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2
+ // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2
+ uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM:
+ // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3
+ // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3
+ // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3
+ uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM:
+ // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4
+ // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4
+ // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4
+ uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM:
+ // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5
+ // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5
+ // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5
+ uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM:
+ // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6
+ // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6
+ // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6
+ uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM:
+ // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7
+ // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7
+ // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7
+ uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices.
+ uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices.
+ uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices.
+ uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices.
+ uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices.
+ uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices.
+ uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices.
+ uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices.
+ uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices.
+ uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices.
+ uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices.
+ uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices.
+ uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices.
+ uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices.
+ uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices.
+ uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices.
+ uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices.
+ uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices.
+ uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices.
+ uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices.
+ uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices.
+ uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices.
+ uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices.
+ uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices.
+ uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices.
+ uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices.
+ uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices.
+ uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices.
+ uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices.
+ uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices.
+ uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices.
+ uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices.
+ uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices.
+ uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices.
+ uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices.
+ uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices.
+ uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices.
+ uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices.
+ uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices.
+ uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices.
+ uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A
+
+ uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A
+
+ uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in
+ // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1).
+ // RdDBI is dynamically disabled in certain training steps,
+ // and so the [RdDBI disabled] CAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_CAS_L[0] == 0: use value in MR0
+ // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2]
+ // Other bits are ignored
+ uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In
+ // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1).
+ // 2tCK write prambles are dynamically disabled in certain training steps,
+ // and so the [1tCK write preamble] WCAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_WCAS_L[0] == 0: use value in MR2
+ // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3]
+ // Other bits are ignored
+ uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In
+ // Contains various options for training DDR4 Devices.
+ //
+ // Bit fields:
+ //
+ // D4Misc[7:1] RFU, must be zero
+ //
+ // D4Misc[0] = protect memory reset
+ // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training.
+ // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training
+} __attribute__ ((packed)) PMU_SMB_DDR4U_2D_t;
diff --git a/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_lpddr3.h b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_lpddr3.h
new file mode 100644
index 0000000..6850d06
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_lpddr3.h
@@ -0,0 +1,434 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief LPDDR3_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_LPDDR3_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:5] RFU, must be zero
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] RFU, must be zero
+ //
+ // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[7-6] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t Reserved0D; // Byte offset 0x0d, CSR Addr 0x54006, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = RunWrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[10] = RFU, must be zero
+ // SequenceCtrl[11] = RFU, must be zero
+ // SequenceCtrl[12] = Run LPCA - CA Training
+ // SequenceCtrl[13] = RFU, must be zero
+ // SequenceCtrl[14] = RFU, must be zero
+ // SequenceCtrl[15] = RFU, must be zero
+ //
+ uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t DFIMRLMargin; // Byte offset 0x14, CSR Addr 0x5400a, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ //
+ // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system.
+ uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t UseBroadcastMR; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired.
+ //
+ // 0x0 = Use MR<0:17>_A0 for rank 0 channel A
+ // Use MR<0:17>_B0 for rank 0 channel B
+ // Use MR<0:17>_A1 for rank 1 channel A
+ // Use MR<0:17>_B1 for rank 1 channel B
+ //
+ // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks
+ //
+ // This should be set to 1 for all systems.
+ //
+ // Note: If setting this to 0, only mode register settings related to DRAM partial array self-refresh may be different between the ranks and channels. All other mode register settings must be the same for all ranks and channels.
+ uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t LogToPhyByteMap0; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // Physical Byte associated with Channel A logical Byte 0, depending on LogToPhyByteMap0[7] value:
+ // LogToPhyByteMap0[7]==0: Logical Byte 0 map on Physical Byte 0
+ // LogToPhyByteMap0[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap0[6:0]
+ uint8_t LogToPhyByteMap1; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In
+ // Physical Byte associated with Channel A logical Byte 1, depending on LogToPhyByteMap1[7] value:
+ // LogToPhyByteMap1[7]==0: Logical Byte 1 map on Physical Byte 1
+ // LogToPhyByteMap1[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap1[6:0]
+ uint8_t LogToPhyByteMap2; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Physical Byte associated with Channel A logical Byte 2, depending on LogToPhyByteMap2[7] value:
+ // LogToPhyByteMap2[7]==0: Logical Byte 2 map on Physical Byte 2
+ // LogToPhyByteMap2[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap2[6:0]
+ uint8_t LogToPhyByteMap3; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // Physical Byte associated with Channel A logical Byte 3, depending on LogToPhyByteMap3[7] value:
+ // LogToPhyByteMap3[7]==0: Logical Byte 3 map on Physical Byte 3
+ // LogToPhyByteMap3[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap3[6:0]
+ uint8_t LogToPhyByteMap4; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // Physical Byte associated with Channel B logical Byte 0, depending on LogToPhyByteMap4[7] value:
+ // LogToPhyByteMap4[7]==0: Logical Byte 0 map on Physical Byte 4
+ // LogToPhyByteMap4[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap4[6:0]
+ uint8_t LogToPhyByteMap5; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In
+ // Physical Byte associated with Channel B logical Byte 1, depending on LogToPhyByteMap5[7] value:
+ // LogToPhyByteMap5[7]==0: Logical Byte 1 map on Physical Byte 5
+ // LogToPhyByteMap5[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap5[6:0]
+ uint8_t LogToPhyByteMap6; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Physical Byte associated with Channel B logical Byte 2, depending on LogToPhyByteMap6[7] value:
+ // LogToPhyByteMap6[7]==0: Logical Byte 2 map on Physical Byte 6
+ // LogToPhyByteMap6[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap6[6:0]
+ uint8_t LogToPhyByteMap7; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In
+ // Physical Byte associated with Channel B logical Byte 3, depending on LogToPhyByteMap7[7] value:
+ // LogToPhyByteMap7[7]==0: Logical Byte 3 map on Physical Byte 7
+ // LogToPhyByteMap7[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap7[6:0]
+ uint8_t LogToPhyByteMap8; // Byte offset 0x20, CSR Addr 0x54010, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t LogToPhyByteMap9; // Byte offset 0x21, CSR Addr 0x54010, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t EnabledDQsChA; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Total number of DQ bits enabled in PHY Channel A
+ uint8_t CsPresentChA; // Byte offset 0x23, CSR Addr 0x54011, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel A.
+ //
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChA_RR_1_0; // Byte offset 0x24, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RR_0_1; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_1_0; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_0_1; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_A0; // Byte offset 0x31, CSR Addr 0x54018, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0}
+ uint8_t MR2_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0}
+ uint8_t MR3_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0}
+ uint8_t Reserved34; // Byte offset 0x34, CSR Addr 0x5401a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0}
+ uint8_t MR16_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0}
+ uint8_t MR17_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0}
+ uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_A1; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In
+ // Must be programmed the same as MR1_A0
+ uint8_t MR2_A1; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
+ // Must be programmed the same as MR2_A0
+ uint8_t MR3_A1; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
+ // Must be programmed the same as MR3_A0
+ uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_A1; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
+ // Must be programmed the same as MR11_A0
+ uint8_t MR16_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1}
+ uint8_t MR17_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1}
+ uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved41; // Byte offset 0x41, CSR Addr 0x54020, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved42; // Byte offset 0x42, CSR Addr 0x54021, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved43; // Byte offset 0x43, CSR Addr 0x54021, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved44; // Byte offset 0x44, CSR Addr 0x54022, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t EnabledDQsChB; // Byte offset 0x48, CSR Addr 0x54024, Direction=In
+ // Total number of DQ bits enabled in PHY Channel B
+ uint8_t CsPresentChB; // Byte offset 0x49, CSR Addr 0x54024, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel B.
+ //
+ // 0x0 = No chip selects are populated with DRAM
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChB_RR_1_0; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RR_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_1; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs01 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_1; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_1; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_0; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_1_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_0_1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_B0; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In
+ // Must be programmed the same as MR1_A0
+ uint8_t MR2_B0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In
+ // Must be programmed the same as MR2_A0
+ uint8_t MR3_B0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=In
+ // Must be programmed the same as MR3_A0
+ uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_B0; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=In
+ // Must be programmed the same as MR11_A0
+ uint8_t MR16_B0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0}
+ uint8_t MR17_B0; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0}
+ uint8_t Reserved5E; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_B1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=In
+ // Must be programmed the same as MR1_A0
+ uint8_t MR2_B1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Must be programmed the same as MR2_A0
+ uint8_t MR3_B1; // Byte offset 0x61, CSR Addr 0x54030, Direction=In
+ // Must be programmed the same as MR3_A0
+ uint8_t Reserved62; // Byte offset 0x62, CSR Addr 0x54031, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_B1; // Byte offset 0x63, CSR Addr 0x54031, Direction=In
+ // Must be programmed the same as MR11_A0
+ uint8_t MR16_B1; // Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1}
+ uint8_t MR17_B1; // Byte offset 0x65, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1}
+ uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+} __attribute__ ((packed)) PMU_SMB_LPDDR3_1D_t;
diff --git a/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_lpddr4.h b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_lpddr4.h
new file mode 100644
index 0000000..d194621
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_lpddr4.h
@@ -0,0 +1,557 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief LPDDR4_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_LPDDR4_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Quick Rd2D during 1D Training
+ // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] Disable Boot Clock
+ // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended)
+ // 0x0 = Use Boot Frequency Clock
+ //
+ // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[7-6] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.25*VDDQ, set this field to 0x20.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Lp4 specific options for training.
+ //
+ // Bit fields:
+ //
+ // Lp4Misc[0] Enable dfi_reset_n
+ //
+ // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training.
+ // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin.
+ //
+ // 0x1 = Enables dfi_reset_n to control memreset after training.
+ // PHY Internal registers control memreset during training only.
+ // To ensure that no glitches occur on BP_MEMRESET at the end of training,
+ // The MC must drive dfi_reset_n=1'b1 _prior to starting training_
+ //
+ // Lp4Misc[7-1] RFU, must be zero
+ uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D.
+ //
+ // Reserved0E[0:3]: bitTimeControl
+ // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point.
+ // 0 = 288 bits per point (legacy behavior)
+ // 1 = 576 bits per point
+ // 2 = 1.125 kilobits per point
+ // …
+ // 15 = 9 megabits per point
+ //
+ // Reserved0E[4]: Exhaustive2D
+ // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior)
+ // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point.
+ //
+ // Reserved0E[5:7]: RFU, must be 0
+ uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[11-10] = RFU, must be zero
+ // SequenceCtrl[12] = Run LPCA - CA Training
+ // SequenceCtrl[15-13] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ //
+ // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system.
+ uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired.
+ //
+ // 0x0 = Use MR<0:17>_A0 for rank 0 channel A
+ // Use MR<0:17>_B0 for rank 0 channel B
+ // Use MR<0:17>_A1 for rank 1 channel A
+ // Use MR<0:17>_B1 for rank 1 channel B
+ //
+ // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks
+ //
+ // It is recommended in most LPDDR4 system configurations to set this to 1.
+ //
+ // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels.
+ //
+ uint8_t Lp4Quickboot; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In
+ // Enable Quickboot.
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D stages: Rd2D, Wr2D
+ //
+ // Reserved1A[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1A[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR14
+ // 2 = limit to +/-4 %VDDQ from MR14
+ // …
+ // 15 = limit to +/-30% VDDQ from MR14
+ uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // CA training option bit field
+ // [0] CA VREF Training
+ // 1 = Enable CA VREF Training
+ // 0 = Disable CA VREF Training
+ // [1-7] RFU must be zero
+ uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // X8 mode configuration:
+ // 0x0 = x16 configuration for all devices
+ // 0xF = x8 configuration for all devices
+ // All other values are RFU
+ uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+
+
+
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Total number of DQ bits enabled in PHY Channel A
+ uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel A.
+ //
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0}
+ uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0}
+ uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0}
+ uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0}
+ uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0}
+ uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0}
+ uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0}
+ uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0}
+ uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0}
+ uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0}
+ uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0}
+ uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0}
+ uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1}
+ uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1}
+ uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1}
+ uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1}
+ uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1}
+ uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1}
+ uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1}
+ uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1}
+ uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1}
+ uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1}
+ uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1}
+ uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1}
+ uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In
+ // Terminating Rank for CA bus on Channel A
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A
+
+ uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A
+
+ uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A
+
+ uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A
+
+ uint8_t Reserved4F; // Byte offset 0x4f, CSR Addr 0x54027, Direction=N/A
+
+ uint8_t Reserved50; // Byte offset 0x50, CSR Addr 0x54028, Direction=N/A
+
+ uint8_t Reserved51; // Byte offset 0x51, CSR Addr 0x54028, Direction=N/A
+
+ uint8_t Reserved52; // Byte offset 0x52, CSR Addr 0x54029, Direction=N/A
+
+ uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A
+
+ uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A
+
+ uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A
+
+ uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A
+
+ uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In
+ // Total number of DQ bits enabled in PHY Channel B
+ uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel B.
+ //
+ // 0x0 = No chip selects are populated with DRAM
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs01 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0}
+ uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0}
+ uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0}
+ uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0}
+ uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0}
+ uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0}
+ uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0}
+ uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0}
+ uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0}
+ uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0}
+ uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0}
+ uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0}
+ uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1}
+ uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1}
+ uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1}
+ uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1}
+ uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1}
+ uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1}
+ uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1}
+ uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1}
+ uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1}
+ uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1}
+ uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1}
+ uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1}
+ uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In
+ // Terminating Rank for CA bus on Channel B
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A
+
+ uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A
+
+ uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A
+
+ uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A
+
+ uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A
+
+ uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A
+
+} __attribute__ ((packed)) PMU_SMB_LPDDR4_1D_t;
diff --git a/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_lpddr4_2d.h b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_lpddr4_2d.h
new file mode 100644
index 0000000..c6ab3d3
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/mnPmuSramMsgBlock_lpddr4_2d.h
@@ -0,0 +1,557 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief LPDDR4_2D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_LPDDR4_2D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Quick Rd2D during 1D Training
+ // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] Disable Boot Clock
+ // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended)
+ // 0x0 = Use Boot Frequency Clock
+ //
+ // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[7-6] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.25*VDDQ, set this field to 0x20.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Lp4 specific options for training.
+ //
+ // Bit fields:
+ //
+ // Lp4Misc[0] Enable dfi_reset_n
+ //
+ // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training.
+ // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin.
+ //
+ // 0x1 = Enables dfi_reset_n to control memreset after training.
+ // PHY Internal registers control memreset during training only.
+ // To ensure that no glitches occur on BP_MEMRESET at the end of training,
+ // The MC must drive dfi_reset_n=1'b1 _prior to starting training_
+ //
+ // Lp4Misc[7-1] RFU, must be zero
+ uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D.
+ //
+ // Reserved0E[0:3]: bitTimeControl
+ // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point.
+ // 0 = 288 bits per point (legacy behavior)
+ // 1 = 576 bits per point
+ // 2 = 1.125 kilobits per point
+ // …
+ // 15 = 9 megabits per point
+ //
+ // Reserved0E[4]: Exhaustive2D
+ // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior)
+ // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point.
+ //
+ // Reserved0E[5:7]: RFU, must be 0
+ uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = RFU, must be zero
+ // SequenceCtrl[2] = RFU, must be zero
+ // SequenceCtrl[3] = RFU, must be zero
+ // SequenceCtrl[4] = RFU, must be zero
+ // SequenceCtrl[5] = Run rd2D - 2d read dqs training
+ // SequenceCtrl[6] = Run wr2D - 2d write dq training
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = RFU, must be zero
+ // SequenceCtrl[9] = RFU, must be zero
+ // SequenceCtrl[11-10] = RFU, must be zero
+ // SequenceCtrl[12] = RFU, must be zero
+ // SequenceCtrl[15-13] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ //
+ // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system.
+ uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired.
+ //
+ // 0x0 = Use MR<0:17>_A0 for rank 0 channel A
+ // Use MR<0:17>_B0 for rank 0 channel B
+ // Use MR<0:17>_A1 for rank 1 channel A
+ // Use MR<0:17>_B1 for rank 1 channel B
+ //
+ // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks
+ //
+ // It is recommended in most LPDDR4 system configurations to set this to 1.
+ //
+ // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels.
+ //
+ uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A
+
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D stages: Rd2D, Wr2D
+ //
+ // Reserved1A[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1A[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR14
+ // 2 = limit to +/-4 %VDDQ from MR14
+ // …
+ // 15 = limit to +/-30% VDDQ from MR14
+ uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // CA training option bit field
+ // [0] CA VREF Setting
+ // 1 = Set MR12 from internal register
+ // 0 = Set MR12 from message block
+ // [1-7] RFU must be zero
+ uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // X8 mode configuration:
+ // 0x0 = x16 configuration for all devices
+ // 0xF = x8 configuration for all devices
+ // All other values are RFU
+ uint8_t RX2D_TrainOpt; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In
+ // Bit fields, if 2D read training enabled, then use these additional options:
+ // [0] DFE
+ // 1 = Run rx2D with DFE
+ // 0 = Run rx2D with DFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5-7] RFU, must be zero
+ //
+ uint8_t TX2D_TrainOpt; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Bit fields, if 2D write training is enabled, then use these additional options:
+ // [0] FFE
+ // 1 = Train tx2D with FFE
+ // 0 = Train tx2D with FFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5-7] RFU, must be zero
+ //
+ uint8_t Share2DVrefResult; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In
+ // Bitmap that designates the phy's vref source for every pstate
+ // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock.
+ // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training.
+ uint8_t Delay_Weight2D; // Byte offset 0x20, CSR Addr 0x54010, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye.
+ uint8_t Voltage_Weight2D; // Byte offset 0x21, CSR Addr 0x54010, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Total number of DQ bits enabled in PHY Channel A
+ uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel A.
+ //
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0}
+ uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0}
+ uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0}
+ uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0}
+ uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0}
+ uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0}
+ uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0}
+ uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0}
+ uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0}
+ uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0}
+ uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0}
+ uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0}
+ uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1}
+ uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1}
+ uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1}
+ uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1}
+ uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1}
+ uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1}
+ uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1}
+ uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1}
+ uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1}
+ uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1}
+ uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1}
+ uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1}
+ uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In
+ // Terminating Rank for CA bus on Channel A
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A
+
+ uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A
+
+ uint8_t TrainedVREFDQ_A0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // Trained DQ Vref setting for Ch A Rank 0
+ uint8_t TrainedVREFDQ_A1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // Trained DQ Vref setting for Ch A Rank 1
+ uint8_t RxClkDly_Margin_A0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_A0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_A0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_A0; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t RxClkDly_Margin_A1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_A1; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_A1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_A1; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In
+ // Total number of DQ bits enabled in PHY Channel B
+ uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel B.
+ //
+ // 0x0 = No chip selects are populated with DRAM
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs01 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0}
+ uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0}
+ uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0}
+ uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0}
+ uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0}
+ uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0}
+ uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0}
+ uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0}
+ uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0}
+ uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0}
+ uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0}
+ uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0}
+ uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1}
+ uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1}
+ uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1}
+ uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1}
+ uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1}
+ uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1}
+ uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1}
+ uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1}
+ uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1}
+ uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1}
+ uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1}
+ uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1}
+ uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In
+ // Terminating Rank for CA bus on Channel B
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t TrainedVREFDQ_B0; // Byte offset 0x80, CSR Addr 0x54040, Direction=Out
+ // Trained DQ Vref setting for Ch B Rank 0
+ uint8_t TrainedVREFDQ_B1; // Byte offset 0x81, CSR Addr 0x54040, Direction=Out
+ // Trained DQ Vref setting for Ch B Rank 1
+ uint8_t RxClkDly_Margin_B0; // Byte offset 0x82, CSR Addr 0x54041, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_B0; // Byte offset 0x83, CSR Addr 0x54041, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_B0; // Byte offset 0x84, CSR Addr 0x54042, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_B0; // Byte offset 0x85, CSR Addr 0x54042, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t RxClkDly_Margin_B1; // Byte offset 0x86, CSR Addr 0x54043, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_B1; // Byte offset 0x87, CSR Addr 0x54043, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_B1; // Byte offset 0x88, CSR Addr 0x54044, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_B1; // Byte offset 0x89, CSR Addr 0x54044, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+} __attribute__ ((packed)) PMU_SMB_LPDDR4_2D_t;
diff --git a/arch/arm/include/asm/arch-a1/nand.h b/arch/arm/include/asm/arch-a1/nand.h
new file mode 100644
index 0000000..d0a873a
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/nand.h
@@ -0,0 +1,136 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __NAND_H__
+#define __NAND_H__
+#include <asm/arch/cpu_config.h>
+
+#ifndef SD_EMMC_BASE_C
+#define SD_EMMC_BASE_C 0xd0074000
+#endif
+
+#define P_NAND_BASE (SD_EMMC_BASE_C | (1<<11))
+#define P_CLK_CNTL (volatile uint32_t *)(SD_EMMC_BASE_C)
+#define P_NAND_CMD (volatile uint32_t *)(P_NAND_BASE + 0x00)
+#define P_NAND_CFG (volatile uint32_t *)(P_NAND_BASE + 0x04)
+#define P_NAND_DADR (volatile uint32_t *)(P_NAND_BASE + 0x08)
+#define P_NAND_IADR (volatile uint32_t *)(P_NAND_BASE + 0x0c)
+#define P_NAND_BUF (volatile uint32_t *)(P_NAND_BASE + 0x10)
+#define P_NAND_INFO (volatile uint32_t *)(P_NAND_BASE + 0x14)
+#define P_NAND_DC (volatile uint32_t *)(P_NAND_BASE + 0x18)
+#define P_NAND_ADR (volatile uint32_t *)(P_NAND_BASE + 0x1c)
+#define P_NAND_DL (volatile uint32_t *)(P_NAND_BASE + 0x20)
+#define P_NAND_DH (volatile uint32_t *)(P_NAND_BASE + 0x24)
+#define P_NAND_CADR (volatile uint32_t *)(P_NAND_BASE + 0x28)
+#define P_NAND_SADR (volatile uint32_t *)(P_NAND_BASE + 0x2c)
+
+#define CEF (0xf<<10)
+#define CE0 (0xe<<10)
+#define CE1 (0xd<<10)
+#define CE2 (0xb<<10)
+#define CE3 (0x7<<10)
+
+#define IO4 ((0xe<<10)|(1<<18))
+#define IO5 ((0xd<<10)|(1<<18))
+#define IO6 ((0xb<<10)|(1<<18))
+
+#define CLE (0x5<<14)
+#define ALE (0x6<<14)
+#define DWR (0x4<<14)
+#define DRD (0x8<<14)
+#define IDLE (0xc<<14)
+#define RB (1<<20)
+
+#define M2N ((0<<17) | (2<<20) | (1<<19))
+#define N2M ((1<<17) | (2<<20) | (1<<19))
+#define STS ((3<<17) | (2<<20))
+#define ADL ((0<<16) | (3<<20))
+#define ADH ((1<<16) | (3<<20))
+#define AIL ((2<<16) | (3<<20))
+#define AIH ((3<<16) | (3<<20))
+#define ASL ((4<<16) | (3<<20))
+#define ASH ((5<<16) | (3<<20))
+#define SEED ((8<<16) | (3<<20))
+
+// NAND Flash Manufacturer ID Codes
+#define NAND_MFR_TOSHIBA 0x98
+#define NAND_MFR_SAMSUNG 0xec
+#define NAND_MFR_FUJITSU 0x04
+#define NAND_MFR_NATIONAL 0x8f
+#define NAND_MFR_RENESAS 0x07
+#define NAND_MFR_STMICRO 0x20
+#define NAND_MFR_HYNIX 0xad
+#define NAND_MFR_MICRON 0x2c
+#define NAND_MFR_AMD 0x01
+#define NAND_MFR_INTEL 0x89
+#define NAND_MFR_SANDISK 0x45
+#define NAND_MFR_USER 0x100
+#define NAND_MFR_EFUSE 0x101
+#define NAND_MFR_ZETTA 0xba
+
+typedef struct nand_setup {
+ union {
+ uint32_t d32;
+ struct {
+ unsigned cmd:22;
+ unsigned large_page:1; // 22
+ unsigned no_rb:1; // 23 from efuse
+ unsigned a2:1; // 24
+ unsigned reserved25:1; // 25
+ unsigned page_list:1; // 26
+ unsigned sync_mode:2; // 27 from efuse
+ unsigned size:2; // 29 from efuse
+ unsigned active:1; // 31
+ } b;
+ } cfg;
+ uint16_t id;
+ uint16_t max; // id:0x100 user, max:0 disable.
+} nand_setup_t;
+
+typedef struct _nand_cmd{
+ unsigned char type;
+ unsigned char val;
+} nand_cmd_t;
+
+typedef struct _ext_info{
+ uint32_t read_info; //nand_read_info;
+ uint32_t new_type; //new_nand_type;
+ uint32_t page_per_blk; //pages_in_block;
+ uint32_t xlc; //slc=1, mlc=2, tlc=3.
+ uint32_t rsv1[5];
+} ext_info_t;
+
+typedef struct _nand_page0 {
+ nand_setup_t nand_setup; //8
+ unsigned char page_list[16]; //16
+ nand_cmd_t retry_usr[32]; //64 (32 cmd max I/F)
+ ext_info_t ext_info; //64
+} nand_page0_t; //384 bytes max.
+
+//#define NAND_PAGE0_BUF BL1_NAND_BUFF
+#define NAND_PAGE0_BUF (0x1800000)
+#define NAND_PAGE_LIST (NAND_PAGE0_BUF + sizeof(nand_setup_t))
+#define NAND_RETRY_USER (NAND_PAGE_LIST + 16)
+#define NAND_INFO_BUF (NAND_PAGE0_BUF + 512)
+#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1)
+//#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1)
+
+#define ERROR_MOD(mod,num) ((uint32_t)(((mod<<6)|num)))
+#define ERROR_NAND_TIMEOUT ERROR_MOD(2,1) //
+#define ERROR_NAND_ECC ERROR_MOD(2,2) //
+#define ERROR_NAND_MAGIC_WORD ERROR_MOD(2,3) //
+#define ERROR_NAND_INIT_READ ERROR_MOD(2,4) //
+#define ERROR_NAND_BLANK_PAGE ERROR_MOD(2,5) //
+#define ERROR_NAND_UNALIGN_SRC ERROR_MOD(2,6) //
+
+#define NAND_SECTOR_SIZE (512)
+#define NAND_MAX_PAGESIZE (0x4000) //16K
+#define SRC_ALIGN_SIZE (NAND_MAX_PAGESIZE)
+
+#define INFO_BYTE_PER_ECCPAGE (8)
+uint32_t nfio_init(void);
+uint32_t nf_read(uint32_t boot_device, uint32_t src, uint32_t des, uint32_t size);
+#endif /* __NAND_H__ */
+
diff --git a/arch/arm/include/asm/arch-a1/oscring.h b/arch/arm/include/asm/arch-a1/oscring.h
new file mode 100644
index 0000000..ffa5778
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/oscring.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __OSCRING_H__
+#define __OSCRING_H__
+
+#define OSCRING_CTL_REG SYSCTRL_OSC_RING_CTRL0
+#define OSCRING_CTL_DATA 0x55555555 /*0:23*/
+
+#define RING_PWM_VCCK PWMAB_PWM_A
+
+int ring_msr(int index);
+#endif
diff --git a/arch/arm/include/asm/arch-a1/p_register.h b/arch/arm/include/asm/arch-a1/p_register.h
new file mode 100644
index 0000000..24b136d
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/p_register.h
@@ -0,0 +1,4083 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifdef P_REGISTER_H
+#else
+#define P_REGISTER_H
+
+//
+// Reading file: ./REG_LIST_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Reading file: REG_LIST_AUDIO_RTL.h
+//
+//========================================================================
+// AUDIO - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe050000
+// -----------------------------------------------
+#define P_EE_AUDIO_CLK_GATE_EN0 ((volatile uint32_t *)0xfe050000)
+#define P_EE_AUDIO_CLK_GATE_EN1 ((volatile uint32_t *)0xfe050004)
+#define P_EE_AUDIO_MCLK_A_CTRL ((volatile uint32_t *)0xfe050008)
+#define P_EE_AUDIO_MCLK_B_CTRL ((volatile uint32_t *)0xfe05000c)
+#define P_EE_AUDIO_MCLK_C_CTRL ((volatile uint32_t *)0xfe050010)
+#define P_EE_AUDIO_MCLK_D_CTRL ((volatile uint32_t *)0xfe050014)
+#define P_EE_AUDIO_MCLK_E_CTRL ((volatile uint32_t *)0xfe050018)
+#define P_EE_AUDIO_MCLK_F_CTRL ((volatile uint32_t *)0xfe05001c)
+#define P_EE_AUDIO_PAD_CTRL0 ((volatile uint32_t *)0xfe050020)
+#define P_EE_AUDIO_PAD_CTRL1 ((volatile uint32_t *)0xfe050024)
+#define P_EE_AUDIO_SW_RESET0 ((volatile uint32_t *)0xfe050028)
+#define P_EE_AUDIO_SW_RESET1 ((volatile uint32_t *)0xfe05002c)
+#define P_EE_AUDIO_CLK81_CTRL ((volatile uint32_t *)0xfe050030)
+#define P_EE_AUDIO_CLK81_EN ((volatile uint32_t *)0xfe050034)
+#define P_EE_AUDIO_MST_A_SCLK_CTRL0 ((volatile uint32_t *)0xfe050040)
+#define P_EE_AUDIO_MST_A_SCLK_CTRL1 ((volatile uint32_t *)0xfe050044)
+#define P_EE_AUDIO_MST_B_SCLK_CTRL0 ((volatile uint32_t *)0xfe050048)
+#define P_EE_AUDIO_MST_B_SCLK_CTRL1 ((volatile uint32_t *)0xfe05004c)
+#define P_EE_AUDIO_MST_C_SCLK_CTRL0 ((volatile uint32_t *)0xfe050050)
+#define P_EE_AUDIO_MST_C_SCLK_CTRL1 ((volatile uint32_t *)0xfe050054)
+#define P_EE_AUDIO_MST_D_SCLK_CTRL0 ((volatile uint32_t *)0xfe050058)
+#define P_EE_AUDIO_MST_D_SCLK_CTRL1 ((volatile uint32_t *)0xfe05005c)
+#define P_EE_AUDIO_MST_E_SCLK_CTRL0 ((volatile uint32_t *)0xfe050060)
+#define P_EE_AUDIO_MST_E_SCLK_CTRL1 ((volatile uint32_t *)0xfe050064)
+#define P_EE_AUDIO_MST_F_SCLK_CTRL0 ((volatile uint32_t *)0xfe050068)
+#define P_EE_AUDIO_MST_F_SCLK_CTRL1 ((volatile uint32_t *)0xfe05006c)
+#define P_EE_AUDIO_MST_DLY_CTRL0 ((volatile uint32_t *)0xfe050070)
+#define P_EE_AUDIO_MST_DLY_CTRL1 ((volatile uint32_t *)0xfe050074)
+#define P_EE_AUDIO_CLK_TDMIN_A_CTRL ((volatile uint32_t *)0xfe050080)
+#define P_EE_AUDIO_CLK_TDMIN_B_CTRL ((volatile uint32_t *)0xfe050084)
+#define P_EE_AUDIO_CLK_TDMIN_C_CTRL ((volatile uint32_t *)0xfe050088)
+#define P_EE_AUDIO_CLK_TDMIN_LB_CTRL ((volatile uint32_t *)0xfe05008c)
+#define P_EE_AUDIO_CLK_TDMOUT_A_CTRL ((volatile uint32_t *)0xfe050090)
+#define P_EE_AUDIO_CLK_TDMOUT_B_CTRL ((volatile uint32_t *)0xfe050094)
+#define P_EE_AUDIO_CLK_TDMOUT_C_CTRL ((volatile uint32_t *)0xfe050098)
+#define P_EE_AUDIO_CLK_SPDIFIN_CTRL ((volatile uint32_t *)0xfe05009c)
+#define P_EE_AUDIO_CLK_SPDIFOUT_CTRL ((volatile uint32_t *)0xfe0500a0)
+#define P_EE_AUDIO_CLK_RESAMPLEA_CTRL ((volatile uint32_t *)0xfe0500a4)
+#define P_EE_AUDIO_CLK_LOCKER_CTRL ((volatile uint32_t *)0xfe0500a8)
+#define P_EE_AUDIO_CLK_PDMIN_CTRL0 ((volatile uint32_t *)0xfe0500ac)
+#define P_EE_AUDIO_CLK_PDMIN_CTRL1 ((volatile uint32_t *)0xfe0500b0)
+#define P_EE_AUDIO_CLK_SPDIFOUT_B_CTRL ((volatile uint32_t *)0xfe0500b4)
+#define P_EE_AUDIO_CLK_RESAMPLEB_CTRL ((volatile uint32_t *)0xfe0500b8)
+#define P_EE_AUDIO_CLK_SPDIFIN_LB_CTRL ((volatile uint32_t *)0xfe0500bc)
+#define P_EE_AUDIO_CLK_EQDRC_CTRL0 ((volatile uint32_t *)0xfe0500c0)
+#define P_EE_AUDIO_VAD_CLK_CTRL ((volatile uint32_t *)0xfe0500c4)
+#define P_EE_AUDIO_EARCTX_CMDC_CLK_CTRL ((volatile uint32_t *)0xfe0500c8)
+#define P_EE_AUDIO_EARCTX_DMAC_CLK_CTRL ((volatile uint32_t *)0xfe0500cc)
+#define P_EE_AUDIO_EARCRX_CMDC_CLK_CTRL ((volatile uint32_t *)0xfe0500d0)
+#define P_EE_AUDIO_EARCRX_DMAC_CLK_CTRL ((volatile uint32_t *)0xfe0500d4)
+#define P_EE_AUDIO_CLK_LOCKERB_CTRL ((volatile uint32_t *)0xfe0500d8)
+#define P_EE_AUDIO_TODDR_A_CTRL0 ((volatile uint32_t *)0xfe050100)
+#define P_EE_AUDIO_TODDR_A_CTRL1 ((volatile uint32_t *)0xfe050104)
+#define P_EE_AUDIO_TODDR_A_START_ADDR ((volatile uint32_t *)0xfe050108)
+#define P_EE_AUDIO_TODDR_A_FINISH_ADDR ((volatile uint32_t *)0xfe05010c)
+#define P_EE_AUDIO_TODDR_A_INT_ADDR ((volatile uint32_t *)0xfe050110)
+#define P_EE_AUDIO_TODDR_A_STATUS1 ((volatile uint32_t *)0xfe050114)
+#define P_EE_AUDIO_TODDR_A_STATUS2 ((volatile uint32_t *)0xfe050118)
+#define P_EE_AUDIO_TODDR_A_START_ADDRB ((volatile uint32_t *)0xfe05011c)
+#define P_EE_AUDIO_TODDR_A_FINISH_ADDRB ((volatile uint32_t *)0xfe050120)
+#define P_EE_AUDIO_TODDR_A_INIT_ADDR ((volatile uint32_t *)0xfe050124)
+#define P_EE_AUDIO_TODDR_A_CTRL2 ((volatile uint32_t *)0xfe050128)
+#define P_EE_AUDIO_TODDR_B_CTRL0 ((volatile uint32_t *)0xfe050140)
+#define P_EE_AUDIO_TODDR_B_CTRL1 ((volatile uint32_t *)0xfe050144)
+#define P_EE_AUDIO_TODDR_B_START_ADDR ((volatile uint32_t *)0xfe050148)
+#define P_EE_AUDIO_TODDR_B_FINISH_ADDR ((volatile uint32_t *)0xfe05014c)
+#define P_EE_AUDIO_TODDR_B_INT_ADDR ((volatile uint32_t *)0xfe050150)
+#define P_EE_AUDIO_TODDR_B_STATUS1 ((volatile uint32_t *)0xfe050154)
+#define P_EE_AUDIO_TODDR_B_STATUS2 ((volatile uint32_t *)0xfe050158)
+#define P_EE_AUDIO_TODDR_B_START_ADDRB ((volatile uint32_t *)0xfe05015c)
+#define P_EE_AUDIO_TODDR_B_FINISH_ADDRB ((volatile uint32_t *)0xfe050160)
+#define P_EE_AUDIO_TODDR_B_INIT_ADDR ((volatile uint32_t *)0xfe050164)
+#define P_EE_AUDIO_TODDR_B_CTRL2 ((volatile uint32_t *)0xfe050168)
+#define P_EE_AUDIO_TODDR_C_CTRL0 ((volatile uint32_t *)0xfe050180)
+#define P_EE_AUDIO_TODDR_C_CTRL1 ((volatile uint32_t *)0xfe050184)
+#define P_EE_AUDIO_TODDR_C_START_ADDR ((volatile uint32_t *)0xfe050188)
+#define P_EE_AUDIO_TODDR_C_FINISH_ADDR ((volatile uint32_t *)0xfe05018c)
+#define P_EE_AUDIO_TODDR_C_INT_ADDR ((volatile uint32_t *)0xfe050190)
+#define P_EE_AUDIO_TODDR_C_STATUS1 ((volatile uint32_t *)0xfe050194)
+#define P_EE_AUDIO_TODDR_C_STATUS2 ((volatile uint32_t *)0xfe050198)
+#define P_EE_AUDIO_TODDR_C_START_ADDRB ((volatile uint32_t *)0xfe05019c)
+#define P_EE_AUDIO_TODDR_C_FINISH_ADDRB ((volatile uint32_t *)0xfe0501a0)
+#define P_EE_AUDIO_TODDR_C_INIT_ADDR ((volatile uint32_t *)0xfe0501a4)
+#define P_EE_AUDIO_TODDR_C_CTRL2 ((volatile uint32_t *)0xfe0501a8)
+#define P_EE_AUDIO_FRDDR_A_CTRL0 ((volatile uint32_t *)0xfe0501c0)
+#define P_EE_AUDIO_FRDDR_A_CTRL1 ((volatile uint32_t *)0xfe0501c4)
+#define P_EE_AUDIO_FRDDR_A_START_ADDR ((volatile uint32_t *)0xfe0501c8)
+#define P_EE_AUDIO_FRDDR_A_FINISH_ADDR ((volatile uint32_t *)0xfe0501cc)
+#define P_EE_AUDIO_FRDDR_A_INT_ADDR ((volatile uint32_t *)0xfe0501d0)
+#define P_EE_AUDIO_FRDDR_A_STATUS1 ((volatile uint32_t *)0xfe0501d4)
+#define P_EE_AUDIO_FRDDR_A_STATUS2 ((volatile uint32_t *)0xfe0501d8)
+#define P_EE_AUDIO_FRDDR_A_START_ADDRB ((volatile uint32_t *)0xfe0501dc)
+#define P_EE_AUDIO_FRDDR_A_FINISH_ADDRB ((volatile uint32_t *)0xfe0501e0)
+#define P_EE_AUDIO_FRDDR_A_INIT_ADDR ((volatile uint32_t *)0xfe0501e4)
+#define P_EE_AUDIO_FRDDR_A_CTRL2 ((volatile uint32_t *)0xfe0501e8)
+#define P_EE_AUDIO_FRDDR_B_CTRL0 ((volatile uint32_t *)0xfe050200)
+#define P_EE_AUDIO_FRDDR_B_CTRL1 ((volatile uint32_t *)0xfe050204)
+#define P_EE_AUDIO_FRDDR_B_START_ADDR ((volatile uint32_t *)0xfe050208)
+#define P_EE_AUDIO_FRDDR_B_FINISH_ADDR ((volatile uint32_t *)0xfe05020c)
+#define P_EE_AUDIO_FRDDR_B_INT_ADDR ((volatile uint32_t *)0xfe050210)
+#define P_EE_AUDIO_FRDDR_B_STATUS1 ((volatile uint32_t *)0xfe050214)
+#define P_EE_AUDIO_FRDDR_B_STATUS2 ((volatile uint32_t *)0xfe050218)
+#define P_EE_AUDIO_FRDDR_B_START_ADDRB ((volatile uint32_t *)0xfe05021c)
+#define P_EE_AUDIO_FRDDR_B_FINISH_ADDRB ((volatile uint32_t *)0xfe050220)
+#define P_EE_AUDIO_FRDDR_B_INIT_ADDR ((volatile uint32_t *)0xfe050224)
+#define P_EE_AUDIO_FRDDR_B_CTRL2 ((volatile uint32_t *)0xfe050228)
+#define P_EE_AUDIO_FRDDR_C_CTRL0 ((volatile uint32_t *)0xfe050240)
+#define P_EE_AUDIO_FRDDR_C_CTRL1 ((volatile uint32_t *)0xfe050244)
+#define P_EE_AUDIO_FRDDR_C_START_ADDR ((volatile uint32_t *)0xfe050248)
+#define P_EE_AUDIO_FRDDR_C_FINISH_ADDR ((volatile uint32_t *)0xfe05024c)
+#define P_EE_AUDIO_FRDDR_C_INT_ADDR ((volatile uint32_t *)0xfe050250)
+#define P_EE_AUDIO_FRDDR_C_STATUS1 ((volatile uint32_t *)0xfe050254)
+#define P_EE_AUDIO_FRDDR_C_STATUS2 ((volatile uint32_t *)0xfe050258)
+#define P_EE_AUDIO_FRDDR_C_START_ADDRB ((volatile uint32_t *)0xfe05025c)
+#define P_EE_AUDIO_FRDDR_C_FINISH_ADDRB ((volatile uint32_t *)0xfe050260)
+#define P_EE_AUDIO_FRDDR_C_INIT_ADDR ((volatile uint32_t *)0xfe050264)
+#define P_EE_AUDIO_FRDDR_C_CTRL2 ((volatile uint32_t *)0xfe050268)
+#define P_EE_AUDIO_ARB_CTRL ((volatile uint32_t *)0xfe050280)
+#define P_EE_AUDIO_LB_A_CTRL0 ((volatile uint32_t *)0xfe0502c0)
+#define P_EE_AUDIO_LB_A_CTRL1 ((volatile uint32_t *)0xfe0502c4)
+#define P_EE_AUDIO_LB_A_CTRL2 ((volatile uint32_t *)0xfe0502c8)
+#define P_EE_AUDIO_LB_A_CTRL3 ((volatile uint32_t *)0xfe0502cc)
+#define P_EE_AUDIO_LB_A_DAT_CH_ID0 ((volatile uint32_t *)0xfe0502d0)
+#define P_EE_AUDIO_LB_A_DAT_CH_ID1 ((volatile uint32_t *)0xfe0502d4)
+#define P_EE_AUDIO_LB_A_DAT_CH_ID2 ((volatile uint32_t *)0xfe0502d8)
+#define P_EE_AUDIO_LB_A_DAT_CH_ID3 ((volatile uint32_t *)0xfe0502dc)
+#define P_EE_AUDIO_LB_A_LB_CH_ID0 ((volatile uint32_t *)0xfe0502e0)
+#define P_EE_AUDIO_LB_A_LB_CH_ID1 ((volatile uint32_t *)0xfe0502e4)
+#define P_EE_AUDIO_LB_A_LB_CH_ID2 ((volatile uint32_t *)0xfe0502e8)
+#define P_EE_AUDIO_LB_A_LB_CH_ID3 ((volatile uint32_t *)0xfe0502ec)
+#define P_EE_AUDIO_LB_A_STS ((volatile uint32_t *)0xfe0502f0)
+#define P_EE_AUDIO_TDMIN_A_CTRL ((volatile uint32_t *)0xfe050300)
+#define P_EE_AUDIO_TDMIN_A_SWAP0 ((volatile uint32_t *)0xfe050304)
+#define P_EE_AUDIO_TDMIN_A_MASK0 ((volatile uint32_t *)0xfe050308)
+#define P_EE_AUDIO_TDMIN_A_MASK1 ((volatile uint32_t *)0xfe05030c)
+#define P_EE_AUDIO_TDMIN_A_MASK2 ((volatile uint32_t *)0xfe050310)
+#define P_EE_AUDIO_TDMIN_A_MASK3 ((volatile uint32_t *)0xfe050314)
+#define P_EE_AUDIO_TDMIN_A_STAT ((volatile uint32_t *)0xfe050318)
+#define P_EE_AUDIO_TDMIN_A_MUTE_VAL ((volatile uint32_t *)0xfe05031c)
+#define P_EE_AUDIO_TDMIN_A_MUTE0 ((volatile uint32_t *)0xfe050320)
+#define P_EE_AUDIO_TDMIN_A_MUTE1 ((volatile uint32_t *)0xfe050324)
+#define P_EE_AUDIO_TDMIN_A_MUTE2 ((volatile uint32_t *)0xfe050328)
+#define P_EE_AUDIO_TDMIN_A_MUTE3 ((volatile uint32_t *)0xfe05032c)
+#define P_EE_AUDIO_TDMIN_B_CTRL ((volatile uint32_t *)0xfe050340)
+#define P_EE_AUDIO_TDMIN_B_SWAP0 ((volatile uint32_t *)0xfe050344)
+#define P_EE_AUDIO_TDMIN_B_MASK0 ((volatile uint32_t *)0xfe050348)
+#define P_EE_AUDIO_TDMIN_B_MASK1 ((volatile uint32_t *)0xfe05034c)
+#define P_EE_AUDIO_TDMIN_B_MASK2 ((volatile uint32_t *)0xfe050350)
+#define P_EE_AUDIO_TDMIN_B_MASK3 ((volatile uint32_t *)0xfe050354)
+#define P_EE_AUDIO_TDMIN_B_STAT ((volatile uint32_t *)0xfe050358)
+#define P_EE_AUDIO_TDMIN_B_MUTE_VAL ((volatile uint32_t *)0xfe05035c)
+#define P_EE_AUDIO_TDMIN_B_MUTE0 ((volatile uint32_t *)0xfe050360)
+#define P_EE_AUDIO_TDMIN_B_MUTE1 ((volatile uint32_t *)0xfe050364)
+#define P_EE_AUDIO_TDMIN_B_MUTE2 ((volatile uint32_t *)0xfe050368)
+#define P_EE_AUDIO_TDMIN_B_MUTE3 ((volatile uint32_t *)0xfe05036c)
+#define P_EE_AUDIO_TDMIN_C_CTRL ((volatile uint32_t *)0xfe050380)
+#define P_EE_AUDIO_TDMIN_C_SWAP0 ((volatile uint32_t *)0xfe050384)
+#define P_EE_AUDIO_TDMIN_C_MASK0 ((volatile uint32_t *)0xfe050388)
+#define P_EE_AUDIO_TDMIN_C_MASK1 ((volatile uint32_t *)0xfe05038c)
+#define P_EE_AUDIO_TDMIN_C_MASK2 ((volatile uint32_t *)0xfe050390)
+#define P_EE_AUDIO_TDMIN_C_MASK3 ((volatile uint32_t *)0xfe050394)
+#define P_EE_AUDIO_TDMIN_C_STAT ((volatile uint32_t *)0xfe050398)
+#define P_EE_AUDIO_TDMIN_C_MUTE_VAL ((volatile uint32_t *)0xfe05039c)
+#define P_EE_AUDIO_TDMIN_C_MUTE0 ((volatile uint32_t *)0xfe0503a0)
+#define P_EE_AUDIO_TDMIN_C_MUTE1 ((volatile uint32_t *)0xfe0503a4)
+#define P_EE_AUDIO_TDMIN_C_MUTE2 ((volatile uint32_t *)0xfe0503a8)
+#define P_EE_AUDIO_TDMIN_C_MUTE3 ((volatile uint32_t *)0xfe0503ac)
+#define P_EE_AUDIO_TDMIN_LB_CTRL ((volatile uint32_t *)0xfe0503c0)
+#define P_EE_AUDIO_TDMIN_LB_SWAP0 ((volatile uint32_t *)0xfe0503c4)
+#define P_EE_AUDIO_TDMIN_LB_MASK0 ((volatile uint32_t *)0xfe0503c8)
+#define P_EE_AUDIO_TDMIN_LB_MASK1 ((volatile uint32_t *)0xfe0503cc)
+#define P_EE_AUDIO_TDMIN_LB_MASK2 ((volatile uint32_t *)0xfe0503d0)
+#define P_EE_AUDIO_TDMIN_LB_MASK3 ((volatile uint32_t *)0xfe0503d4)
+#define P_EE_AUDIO_TDMIN_LB_STAT ((volatile uint32_t *)0xfe0503d8)
+#define P_EE_AUDIO_TDMIN_LB_MUTE_VAL ((volatile uint32_t *)0xfe0503dc)
+#define P_EE_AUDIO_TDMIN_LB_MUTE0 ((volatile uint32_t *)0xfe0503e0)
+#define P_EE_AUDIO_TDMIN_LB_MUTE1 ((volatile uint32_t *)0xfe0503e4)
+#define P_EE_AUDIO_TDMIN_LB_MUTE2 ((volatile uint32_t *)0xfe0503e8)
+#define P_EE_AUDIO_TDMIN_LB_MUTE3 ((volatile uint32_t *)0xfe0503ec)
+#define P_EE_AUDIO_SPDIFIN_CTRL0 ((volatile uint32_t *)0xfe050400)
+#define P_EE_AUDIO_SPDIFIN_CTRL1 ((volatile uint32_t *)0xfe050404)
+#define P_EE_AUDIO_SPDIFIN_CTRL2 ((volatile uint32_t *)0xfe050408)
+#define P_EE_AUDIO_SPDIFIN_CTRL3 ((volatile uint32_t *)0xfe05040c)
+#define P_EE_AUDIO_SPDIFIN_CTRL4 ((volatile uint32_t *)0xfe050410)
+#define P_EE_AUDIO_SPDIFIN_CTRL5 ((volatile uint32_t *)0xfe050414)
+#define P_EE_AUDIO_SPDIFIN_CTRL6 ((volatile uint32_t *)0xfe050418)
+#define P_EE_AUDIO_SPDIFIN_STAT0 ((volatile uint32_t *)0xfe05041c)
+#define P_EE_AUDIO_SPDIFIN_STAT1 ((volatile uint32_t *)0xfe050420)
+#define P_EE_AUDIO_SPDIFIN_STAT2 ((volatile uint32_t *)0xfe050424)
+#define P_EE_AUDIO_SPDIFIN_MUTE_VAL ((volatile uint32_t *)0xfe050428)
+#define P_EE_AUDIO_RESAMPLEA_CTRL0 ((volatile uint32_t *)0xfe050440)
+#define P_EE_AUDIO_RESAMPLEA_CTRL1 ((volatile uint32_t *)0xfe050444)
+#define P_EE_AUDIO_RESAMPLEA_CTRL2 ((volatile uint32_t *)0xfe050448)
+#define P_EE_AUDIO_RESAMPLEA_CTRL3 ((volatile uint32_t *)0xfe05044c)
+#define P_EE_AUDIO_RESAMPLEA_COEF0 ((volatile uint32_t *)0xfe050450)
+#define P_EE_AUDIO_RESAMPLEA_COEF1 ((volatile uint32_t *)0xfe050454)
+#define P_EE_AUDIO_RESAMPLEA_COEF2 ((volatile uint32_t *)0xfe050458)
+#define P_EE_AUDIO_RESAMPLEA_COEF3 ((volatile uint32_t *)0xfe05045c)
+#define P_EE_AUDIO_RESAMPLEA_COEF4 ((volatile uint32_t *)0xfe050460)
+#define P_EE_AUDIO_RESAMPLEA_STATUS1 ((volatile uint32_t *)0xfe050464)
+#define P_EE_AUDIO_SPDIFOUT_STAT ((volatile uint32_t *)0xfe050480)
+#define P_EE_AUDIO_SPDIFOUT_GAIN0 ((volatile uint32_t *)0xfe050484)
+#define P_EE_AUDIO_SPDIFOUT_GAIN1 ((volatile uint32_t *)0xfe050488)
+#define P_EE_AUDIO_SPDIFOUT_CTRL0 ((volatile uint32_t *)0xfe05048c)
+#define P_EE_AUDIO_SPDIFOUT_CTRL1 ((volatile uint32_t *)0xfe050490)
+#define P_EE_AUDIO_SPDIFOUT_PREAMB ((volatile uint32_t *)0xfe050494)
+#define P_EE_AUDIO_SPDIFOUT_SWAP ((volatile uint32_t *)0xfe050498)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS0 ((volatile uint32_t *)0xfe05049c)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS1 ((volatile uint32_t *)0xfe0504a0)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS2 ((volatile uint32_t *)0xfe0504a4)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS3 ((volatile uint32_t *)0xfe0504a8)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS4 ((volatile uint32_t *)0xfe0504ac)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS5 ((volatile uint32_t *)0xfe0504b0)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS6 ((volatile uint32_t *)0xfe0504b4)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS7 ((volatile uint32_t *)0xfe0504b8)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS8 ((volatile uint32_t *)0xfe0504bc)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS9 ((volatile uint32_t *)0xfe0504c0)
+#define P_EE_AUDIO_SPDIFOUT_CHSTSA ((volatile uint32_t *)0xfe0504c4)
+#define P_EE_AUDIO_SPDIFOUT_CHSTSB ((volatile uint32_t *)0xfe0504c8)
+#define P_EE_AUDIO_SPDIFOUT_MUTE_VAL ((volatile uint32_t *)0xfe0504cc)
+#define P_EE_AUDIO_TDMOUT_A_CTRL0 ((volatile uint32_t *)0xfe050500)
+#define P_EE_AUDIO_TDMOUT_A_CTRL1 ((volatile uint32_t *)0xfe050504)
+#define P_EE_AUDIO_TDMOUT_A_SWAP0 ((volatile uint32_t *)0xfe050508)
+#define P_EE_AUDIO_TDMOUT_A_MASK0 ((volatile uint32_t *)0xfe05050c)
+#define P_EE_AUDIO_TDMOUT_A_MASK1 ((volatile uint32_t *)0xfe050510)
+#define P_EE_AUDIO_TDMOUT_A_MASK2 ((volatile uint32_t *)0xfe050514)
+#define P_EE_AUDIO_TDMOUT_A_MASK3 ((volatile uint32_t *)0xfe050518)
+#define P_EE_AUDIO_TDMOUT_A_STAT ((volatile uint32_t *)0xfe05051c)
+#define P_EE_AUDIO_TDMOUT_A_GAIN0 ((volatile uint32_t *)0xfe050520)
+#define P_EE_AUDIO_TDMOUT_A_GAIN1 ((volatile uint32_t *)0xfe050524)
+#define P_EE_AUDIO_TDMOUT_A_MUTE_VAL ((volatile uint32_t *)0xfe050528)
+#define P_EE_AUDIO_TDMOUT_A_MUTE0 ((volatile uint32_t *)0xfe05052c)
+#define P_EE_AUDIO_TDMOUT_A_MUTE1 ((volatile uint32_t *)0xfe050530)
+#define P_EE_AUDIO_TDMOUT_A_MUTE2 ((volatile uint32_t *)0xfe050534)
+#define P_EE_AUDIO_TDMOUT_A_MUTE3 ((volatile uint32_t *)0xfe050538)
+#define P_EE_AUDIO_TDMOUT_A_MASK_VAL ((volatile uint32_t *)0xfe05053c)
+#define P_EE_AUDIO_TDMOUT_B_CTRL0 ((volatile uint32_t *)0xfe050540)
+#define P_EE_AUDIO_TDMOUT_B_CTRL1 ((volatile uint32_t *)0xfe050544)
+#define P_EE_AUDIO_TDMOUT_B_SWAP0 ((volatile uint32_t *)0xfe050548)
+#define P_EE_AUDIO_TDMOUT_B_MASK0 ((volatile uint32_t *)0xfe05054c)
+#define P_EE_AUDIO_TDMOUT_B_MASK1 ((volatile uint32_t *)0xfe050550)
+#define P_EE_AUDIO_TDMOUT_B_MASK2 ((volatile uint32_t *)0xfe050554)
+#define P_EE_AUDIO_TDMOUT_B_MASK3 ((volatile uint32_t *)0xfe050558)
+#define P_EE_AUDIO_TDMOUT_B_STAT ((volatile uint32_t *)0xfe05055c)
+#define P_EE_AUDIO_TDMOUT_B_GAIN0 ((volatile uint32_t *)0xfe050560)
+#define P_EE_AUDIO_TDMOUT_B_GAIN1 ((volatile uint32_t *)0xfe050564)
+#define P_EE_AUDIO_TDMOUT_B_MUTE_VAL ((volatile uint32_t *)0xfe050568)
+#define P_EE_AUDIO_TDMOUT_B_MUTE0 ((volatile uint32_t *)0xfe05056c)
+#define P_EE_AUDIO_TDMOUT_B_MUTE1 ((volatile uint32_t *)0xfe050570)
+#define P_EE_AUDIO_TDMOUT_B_MUTE2 ((volatile uint32_t *)0xfe050574)
+#define P_EE_AUDIO_TDMOUT_B_MUTE3 ((volatile uint32_t *)0xfe050578)
+#define P_EE_AUDIO_TDMOUT_B_MASK_VAL ((volatile uint32_t *)0xfe05057c)
+#define P_EE_AUDIO_TDMOUT_C_CTRL0 ((volatile uint32_t *)0xfe050580)
+#define P_EE_AUDIO_TDMOUT_C_CTRL1 ((volatile uint32_t *)0xfe050584)
+#define P_EE_AUDIO_TDMOUT_C_SWAP0 ((volatile uint32_t *)0xfe050588)
+#define P_EE_AUDIO_TDMOUT_C_MASK0 ((volatile uint32_t *)0xfe05058c)
+#define P_EE_AUDIO_TDMOUT_C_MASK1 ((volatile uint32_t *)0xfe050590)
+#define P_EE_AUDIO_TDMOUT_C_MASK2 ((volatile uint32_t *)0xfe050594)
+#define P_EE_AUDIO_TDMOUT_C_MASK3 ((volatile uint32_t *)0xfe050598)
+#define P_EE_AUDIO_TDMOUT_C_STAT ((volatile uint32_t *)0xfe05059c)
+#define P_EE_AUDIO_TDMOUT_C_GAIN0 ((volatile uint32_t *)0xfe0505a0)
+#define P_EE_AUDIO_TDMOUT_C_GAIN1 ((volatile uint32_t *)0xfe0505a4)
+#define P_EE_AUDIO_TDMOUT_C_MUTE_VAL ((volatile uint32_t *)0xfe0505a8)
+#define P_EE_AUDIO_TDMOUT_C_MUTE0 ((volatile uint32_t *)0xfe0505ac)
+#define P_EE_AUDIO_TDMOUT_C_MUTE1 ((volatile uint32_t *)0xfe0505b0)
+#define P_EE_AUDIO_TDMOUT_C_MUTE2 ((volatile uint32_t *)0xfe0505b4)
+#define P_EE_AUDIO_TDMOUT_C_MUTE3 ((volatile uint32_t *)0xfe0505b8)
+#define P_EE_AUDIO_TDMOUT_C_MASK_VAL ((volatile uint32_t *)0xfe0505bc)
+//`define EE_AUDIO_POW_DET_CTRL0 10'h180
+//`define EE_AUDIO_POW_DET_CTRL1 10'h181
+//`define EE_AUDIO_POW_DET_TH_HI 10'h182
+//`define EE_AUDIO_POW_DET_TH_LO 10'h183
+//`define EE_AUDIO_POW_DET_VALUE 10'h184
+#define P_EE_AUDIO_SECURITY_CTRL0 ((volatile uint32_t *)0xfe050640)
+#define P_EE_AUDIO_SECURITY_CTRL1 ((volatile uint32_t *)0xfe050644)
+#define P_EE_AUDIO_SPDIFOUT_B_STAT ((volatile uint32_t *)0xfe050680)
+#define P_EE_AUDIO_SPDIFOUT_B_GAIN0 ((volatile uint32_t *)0xfe050684)
+#define P_EE_AUDIO_SPDIFOUT_B_GAIN1 ((volatile uint32_t *)0xfe050688)
+#define P_EE_AUDIO_SPDIFOUT_B_CTRL0 ((volatile uint32_t *)0xfe05068c)
+#define P_EE_AUDIO_SPDIFOUT_B_CTRL1 ((volatile uint32_t *)0xfe050690)
+#define P_EE_AUDIO_SPDIFOUT_B_PREAMB ((volatile uint32_t *)0xfe050694)
+#define P_EE_AUDIO_SPDIFOUT_B_SWAP ((volatile uint32_t *)0xfe050698)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS0 ((volatile uint32_t *)0xfe05069c)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS1 ((volatile uint32_t *)0xfe0506a0)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS2 ((volatile uint32_t *)0xfe0506a4)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS3 ((volatile uint32_t *)0xfe0506a8)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS4 ((volatile uint32_t *)0xfe0506ac)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS5 ((volatile uint32_t *)0xfe0506b0)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS6 ((volatile uint32_t *)0xfe0506b4)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS7 ((volatile uint32_t *)0xfe0506b8)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS8 ((volatile uint32_t *)0xfe0506bc)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS9 ((volatile uint32_t *)0xfe0506c0)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTSA ((volatile uint32_t *)0xfe0506c4)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTSB ((volatile uint32_t *)0xfe0506c8)
+#define P_EE_AUDIO_SPDIFOUT_B_MUTE_VAL ((volatile uint32_t *)0xfe0506cc)
+#define P_EE_AUDIO_TORAM_CTRL0 ((volatile uint32_t *)0xfe050700)
+#define P_EE_AUDIO_TORAM_CTRL1 ((volatile uint32_t *)0xfe050704)
+#define P_EE_AUDIO_TORAM_START_ADDR ((volatile uint32_t *)0xfe050708)
+#define P_EE_AUDIO_TORAM_FINISH_ADDR ((volatile uint32_t *)0xfe05070c)
+#define P_EE_AUDIO_TORAM_INT_ADDR ((volatile uint32_t *)0xfe050710)
+#define P_EE_AUDIO_TORAM_STATUS1 ((volatile uint32_t *)0xfe050714)
+#define P_EE_AUDIO_TORAM_STATUS2 ((volatile uint32_t *)0xfe050718)
+#define P_EE_AUDIO_TORAM_INIT_ADDR ((volatile uint32_t *)0xfe05071c)
+#define P_EE_AUDIO_TOACODEC_CTRL0 ((volatile uint32_t *)0xfe050740)
+#define P_EE_AUDIO_TOHDMITX_CTRL0 ((volatile uint32_t *)0xfe050744)
+#define P_EE_AUDIO_TOVAD_CTRL0 ((volatile uint32_t *)0xfe050748)
+#define P_EE_AUDIO_FRATV_CTRL0 ((volatile uint32_t *)0xfe05074c)
+#define P_EE_AUDIO_RESAMPLEB_CTRL0 ((volatile uint32_t *)0xfe050780)
+#define P_EE_AUDIO_RESAMPLEB_CTRL1 ((volatile uint32_t *)0xfe050784)
+#define P_EE_AUDIO_RESAMPLEB_CTRL2 ((volatile uint32_t *)0xfe050788)
+#define P_EE_AUDIO_RESAMPLEB_CTRL3 ((volatile uint32_t *)0xfe05078c)
+#define P_EE_AUDIO_RESAMPLEB_COEF0 ((volatile uint32_t *)0xfe050790)
+#define P_EE_AUDIO_RESAMPLEB_COEF1 ((volatile uint32_t *)0xfe050794)
+#define P_EE_AUDIO_RESAMPLEB_COEF2 ((volatile uint32_t *)0xfe050798)
+#define P_EE_AUDIO_RESAMPLEB_COEF3 ((volatile uint32_t *)0xfe05079c)
+#define P_EE_AUDIO_RESAMPLEB_COEF4 ((volatile uint32_t *)0xfe0507a0)
+#define P_EE_AUDIO_RESAMPLEB_STATUS1 ((volatile uint32_t *)0xfe0507a4)
+#define P_EE_AUDIO_SPDIFIN_LB_CTRL0 ((volatile uint32_t *)0xfe0507c0)
+#define P_EE_AUDIO_SPDIFIN_LB_CTRL1 ((volatile uint32_t *)0xfe0507c4)
+#define P_EE_AUDIO_SPDIFIN_LB_CTRL6 ((volatile uint32_t *)0xfe0507d8)
+#define P_EE_AUDIO_SPDIFIN_LB_STAT0 ((volatile uint32_t *)0xfe0507dc)
+#define P_EE_AUDIO_SPDIFIN_LB_STAT1 ((volatile uint32_t *)0xfe0507e0)
+#define P_EE_AUDIO_SPDIFIN_LB_MUTE_VAL ((volatile uint32_t *)0xfe0507e8)
+#define P_EE_AUDIO_FRHDMIRX_CTRL0 ((volatile uint32_t *)0xfe050800)
+#define P_EE_AUDIO_FRHDMIRX_CTRL1 ((volatile uint32_t *)0xfe050804)
+#define P_EE_AUDIO_FRHDMIRX_CTRL2 ((volatile uint32_t *)0xfe050808)
+#define P_EE_AUDIO_FRHDMIRX_CTRL3 ((volatile uint32_t *)0xfe05080c)
+#define P_EE_AUDIO_FRHDMIRX_CTRL4 ((volatile uint32_t *)0xfe050810)
+#define P_EE_AUDIO_FRHDMIRX_CTRL5 ((volatile uint32_t *)0xfe050814)
+#define P_EE_AUDIO_FRHDMIRX_STAT0 ((volatile uint32_t *)0xfe050828)
+#define P_EE_AUDIO_FRHDMIRX_STAT1 ((volatile uint32_t *)0xfe05082c)
+#define P_EE_AUDIO_TODDR_D_CTRL0 ((volatile uint32_t *)0xfe050840)
+#define P_EE_AUDIO_TODDR_D_CTRL1 ((volatile uint32_t *)0xfe050844)
+#define P_EE_AUDIO_TODDR_D_START_ADDR ((volatile uint32_t *)0xfe050848)
+#define P_EE_AUDIO_TODDR_D_FINISH_ADDR ((volatile uint32_t *)0xfe05084c)
+#define P_EE_AUDIO_TODDR_D_INT_ADDR ((volatile uint32_t *)0xfe050850)
+#define P_EE_AUDIO_TODDR_D_STATUS1 ((volatile uint32_t *)0xfe050854)
+#define P_EE_AUDIO_TODDR_D_STATUS2 ((volatile uint32_t *)0xfe050858)
+#define P_EE_AUDIO_TODDR_D_START_ADDRB ((volatile uint32_t *)0xfe05085c)
+#define P_EE_AUDIO_TODDR_D_FINISH_ADDRB ((volatile uint32_t *)0xfe050860)
+#define P_EE_AUDIO_TODDR_D_INIT_ADDR ((volatile uint32_t *)0xfe050864)
+#define P_EE_AUDIO_TODDR_D_CTRL2 ((volatile uint32_t *)0xfe050868)
+#define P_EE_AUDIO_FRDDR_D_CTRL0 ((volatile uint32_t *)0xfe050880)
+#define P_EE_AUDIO_FRDDR_D_CTRL1 ((volatile uint32_t *)0xfe050884)
+#define P_EE_AUDIO_FRDDR_D_START_ADDR ((volatile uint32_t *)0xfe050888)
+#define P_EE_AUDIO_FRDDR_D_FINISH_ADDR ((volatile uint32_t *)0xfe05088c)
+#define P_EE_AUDIO_FRDDR_D_INT_ADDR ((volatile uint32_t *)0xfe050890)
+#define P_EE_AUDIO_FRDDR_D_STATUS1 ((volatile uint32_t *)0xfe050894)
+#define P_EE_AUDIO_FRDDR_D_STATUS2 ((volatile uint32_t *)0xfe050898)
+#define P_EE_AUDIO_FRDDR_D_START_ADDRB ((volatile uint32_t *)0xfe05089c)
+#define P_EE_AUDIO_FRDDR_D_FINISH_ADDRB ((volatile uint32_t *)0xfe0508a0)
+#define P_EE_AUDIO_FRDDR_D_INIT_ADDR ((volatile uint32_t *)0xfe0508a4)
+#define P_EE_AUDIO_FRDDR_D_CTRL2 ((volatile uint32_t *)0xfe0508a8)
+#define P_EE_AUDIO_LB_B_CTRL0 ((volatile uint32_t *)0xfe0508c0)
+#define P_EE_AUDIO_LB_B_CTRL1 ((volatile uint32_t *)0xfe0508c4)
+#define P_EE_AUDIO_LB_B_CTRL2 ((volatile uint32_t *)0xfe0508c8)
+#define P_EE_AUDIO_LB_B_CTRL3 ((volatile uint32_t *)0xfe0508cc)
+#define P_EE_AUDIO_LB_B_DAT_CH_ID0 ((volatile uint32_t *)0xfe0508d0)
+#define P_EE_AUDIO_LB_B_DAT_CH_ID1 ((volatile uint32_t *)0xfe0508d4)
+#define P_EE_AUDIO_LB_B_DAT_CH_ID2 ((volatile uint32_t *)0xfe0508d8)
+#define P_EE_AUDIO_LB_B_DAT_CH_ID3 ((volatile uint32_t *)0xfe0508dc)
+#define P_EE_AUDIO_LB_B_LB_CH_ID0 ((volatile uint32_t *)0xfe0508e0)
+#define P_EE_AUDIO_LB_B_LB_CH_ID1 ((volatile uint32_t *)0xfe0508e4)
+#define P_EE_AUDIO_LB_B_LB_CH_ID2 ((volatile uint32_t *)0xfe0508e8)
+#define P_EE_AUDIO_LB_B_LB_CH_ID3 ((volatile uint32_t *)0xfe0508ec)
+#define P_EE_AUDIO_LB_B_STS ((volatile uint32_t *)0xfe0508f0)
+#define P_EE_AUDIO_TODDR_E_CTRL0 ((volatile uint32_t *)0xfe050900)
+#define P_EE_AUDIO_TODDR_E_CTRL1 ((volatile uint32_t *)0xfe050904)
+#define P_EE_AUDIO_TODDR_E_START_ADDR ((volatile uint32_t *)0xfe050908)
+#define P_EE_AUDIO_TODDR_E_FINISH_ADDR ((volatile uint32_t *)0xfe05090c)
+#define P_EE_AUDIO_TODDR_E_INT_ADDR ((volatile uint32_t *)0xfe050910)
+#define P_EE_AUDIO_TODDR_E_STATUS1 ((volatile uint32_t *)0xfe050914)
+#define P_EE_AUDIO_TODDR_E_STATUS2 ((volatile uint32_t *)0xfe050918)
+#define P_EE_AUDIO_TODDR_E_START_ADDRB ((volatile uint32_t *)0xfe05091c)
+#define P_EE_AUDIO_TODDR_E_FINISH_ADDRB ((volatile uint32_t *)0xfe050920)
+#define P_EE_AUDIO_TODDR_E_INIT_ADDR ((volatile uint32_t *)0xfe050924)
+#define P_EE_AUDIO_TODDR_E_CTRL2 ((volatile uint32_t *)0xfe050928)
+#define P_EE_AUDIO_FRDDR_E_CTRL0 ((volatile uint32_t *)0xfe050940)
+#define P_EE_AUDIO_FRDDR_E_CTRL1 ((volatile uint32_t *)0xfe050944)
+#define P_EE_AUDIO_FRDDR_E_START_ADDR ((volatile uint32_t *)0xfe050948)
+#define P_EE_AUDIO_FRDDR_E_FINISH_ADDR ((volatile uint32_t *)0xfe05094c)
+#define P_EE_AUDIO_FRDDR_E_INT_ADDR ((volatile uint32_t *)0xfe050950)
+#define P_EE_AUDIO_FRDDR_E_STATUS1 ((volatile uint32_t *)0xfe050954)
+#define P_EE_AUDIO_FRDDR_E_STATUS2 ((volatile uint32_t *)0xfe050958)
+#define P_EE_AUDIO_FRDDR_E_START_ADDRB ((volatile uint32_t *)0xfe05095c)
+#define P_EE_AUDIO_FRDDR_E_FINISH_ADDRB ((volatile uint32_t *)0xfe050960)
+#define P_EE_AUDIO_FRDDR_E_INIT_ADDR ((volatile uint32_t *)0xfe050964)
+#define P_EE_AUDIO_FRDDR_E_CTRL2 ((volatile uint32_t *)0xfe050968)
+#define P_EE_AUDIO_TDMIN_A_SWAP1 ((volatile uint32_t *)0xfe050980)
+#define P_EE_AUDIO_TDMIN_A_MASK4 ((volatile uint32_t *)0xfe050984)
+#define P_EE_AUDIO_TDMIN_A_MASK5 ((volatile uint32_t *)0xfe050988)
+#define P_EE_AUDIO_TDMIN_A_MASK6 ((volatile uint32_t *)0xfe05098c)
+#define P_EE_AUDIO_TDMIN_A_MASK7 ((volatile uint32_t *)0xfe050990)
+#define P_EE_AUDIO_TDMIN_A_MUTE4 ((volatile uint32_t *)0xfe050994)
+#define P_EE_AUDIO_TDMIN_A_MUTE5 ((volatile uint32_t *)0xfe050998)
+#define P_EE_AUDIO_TDMIN_A_MUTE6 ((volatile uint32_t *)0xfe05099c)
+#define P_EE_AUDIO_TDMIN_A_MUTE7 ((volatile uint32_t *)0xfe0509a0)
+#define P_EE_AUDIO_TDMIN_B_SWAP1 ((volatile uint32_t *)0xfe0509c0)
+#define P_EE_AUDIO_TDMIN_B_MASK4 ((volatile uint32_t *)0xfe0509c4)
+#define P_EE_AUDIO_TDMIN_B_MASK5 ((volatile uint32_t *)0xfe0509c8)
+#define P_EE_AUDIO_TDMIN_B_MASK6 ((volatile uint32_t *)0xfe0509cc)
+#define P_EE_AUDIO_TDMIN_B_MASK7 ((volatile uint32_t *)0xfe0509d0)
+#define P_EE_AUDIO_TDMIN_B_MUTE4 ((volatile uint32_t *)0xfe0509d4)
+#define P_EE_AUDIO_TDMIN_B_MUTE5 ((volatile uint32_t *)0xfe0509d8)
+#define P_EE_AUDIO_TDMIN_B_MUTE6 ((volatile uint32_t *)0xfe0509dc)
+#define P_EE_AUDIO_TDMIN_B_MUTE7 ((volatile uint32_t *)0xfe0509e0)
+#define P_EE_AUDIO_TDMIN_C_SWAP1 ((volatile uint32_t *)0xfe050a00)
+#define P_EE_AUDIO_TDMIN_C_MASK4 ((volatile uint32_t *)0xfe050a04)
+#define P_EE_AUDIO_TDMIN_C_MASK5 ((volatile uint32_t *)0xfe050a08)
+#define P_EE_AUDIO_TDMIN_C_MASK6 ((volatile uint32_t *)0xfe050a0c)
+#define P_EE_AUDIO_TDMIN_C_MASK7 ((volatile uint32_t *)0xfe050a10)
+#define P_EE_AUDIO_TDMIN_C_MUTE4 ((volatile uint32_t *)0xfe050a14)
+#define P_EE_AUDIO_TDMIN_C_MUTE5 ((volatile uint32_t *)0xfe050a18)
+#define P_EE_AUDIO_TDMIN_C_MUTE6 ((volatile uint32_t *)0xfe050a1c)
+#define P_EE_AUDIO_TDMIN_C_MUTE7 ((volatile uint32_t *)0xfe050a20)
+#define P_EE_AUDIO_TDMIN_LB_SWAP1 ((volatile uint32_t *)0xfe050a40)
+#define P_EE_AUDIO_TDMIN_LB_MASK4 ((volatile uint32_t *)0xfe050a44)
+#define P_EE_AUDIO_TDMIN_LB_MASK5 ((volatile uint32_t *)0xfe050a48)
+#define P_EE_AUDIO_TDMIN_LB_MASK6 ((volatile uint32_t *)0xfe050a4c)
+#define P_EE_AUDIO_TDMIN_LB_MASK7 ((volatile uint32_t *)0xfe050a50)
+#define P_EE_AUDIO_TDMIN_LB_MUTE4 ((volatile uint32_t *)0xfe050a54)
+#define P_EE_AUDIO_TDMIN_LB_MUTE5 ((volatile uint32_t *)0xfe050a58)
+#define P_EE_AUDIO_TDMIN_LB_MUTE6 ((volatile uint32_t *)0xfe050a5c)
+#define P_EE_AUDIO_TDMIN_LB_MUTE7 ((volatile uint32_t *)0xfe050a60)
+#define P_EE_AUDIO_TDMOUT_A_CTRL2 ((volatile uint32_t *)0xfe050a80)
+#define P_EE_AUDIO_TDMOUT_A_SWAP1 ((volatile uint32_t *)0xfe050a84)
+#define P_EE_AUDIO_TDMOUT_A_GAIN2 ((volatile uint32_t *)0xfe050a88)
+#define P_EE_AUDIO_TDMOUT_A_GAIN3 ((volatile uint32_t *)0xfe050a8c)
+#define P_EE_AUDIO_TDMOUT_A_MASK4 ((volatile uint32_t *)0xfe050a90)
+#define P_EE_AUDIO_TDMOUT_A_MASK5 ((volatile uint32_t *)0xfe050a94)
+#define P_EE_AUDIO_TDMOUT_A_MASK6 ((volatile uint32_t *)0xfe050a98)
+#define P_EE_AUDIO_TDMOUT_A_MASK7 ((volatile uint32_t *)0xfe050a9c)
+#define P_EE_AUDIO_TDMOUT_A_MUTE4 ((volatile uint32_t *)0xfe050aa0)
+#define P_EE_AUDIO_TDMOUT_A_MUTE5 ((volatile uint32_t *)0xfe050aa4)
+#define P_EE_AUDIO_TDMOUT_A_MUTE6 ((volatile uint32_t *)0xfe050aa8)
+#define P_EE_AUDIO_TDMOUT_A_MUTE7 ((volatile uint32_t *)0xfe050aac)
+#define P_EE_AUDIO_TDMOUT_B_CTRL2 ((volatile uint32_t *)0xfe050ac0)
+#define P_EE_AUDIO_TDMOUT_B_SWAP1 ((volatile uint32_t *)0xfe050ac4)
+#define P_EE_AUDIO_TDMOUT_B_GAIN2 ((volatile uint32_t *)0xfe050ac8)
+#define P_EE_AUDIO_TDMOUT_B_GAIN3 ((volatile uint32_t *)0xfe050acc)
+#define P_EE_AUDIO_TDMOUT_B_MASK4 ((volatile uint32_t *)0xfe050ad0)
+#define P_EE_AUDIO_TDMOUT_B_MASK5 ((volatile uint32_t *)0xfe050ad4)
+#define P_EE_AUDIO_TDMOUT_B_MASK6 ((volatile uint32_t *)0xfe050ad8)
+#define P_EE_AUDIO_TDMOUT_B_MASK7 ((volatile uint32_t *)0xfe050adc)
+#define P_EE_AUDIO_TDMOUT_B_MUTE4 ((volatile uint32_t *)0xfe050ae0)
+#define P_EE_AUDIO_TDMOUT_B_MUTE5 ((volatile uint32_t *)0xfe050ae4)
+#define P_EE_AUDIO_TDMOUT_B_MUTE6 ((volatile uint32_t *)0xfe050ae8)
+#define P_EE_AUDIO_TDMOUT_B_MUTE7 ((volatile uint32_t *)0xfe050aec)
+#define P_EE_AUDIO_TDMOUT_C_CTRL2 ((volatile uint32_t *)0xfe050b00)
+#define P_EE_AUDIO_TDMOUT_C_SWAP1 ((volatile uint32_t *)0xfe050b04)
+#define P_EE_AUDIO_TDMOUT_C_GAIN2 ((volatile uint32_t *)0xfe050b08)
+#define P_EE_AUDIO_TDMOUT_C_GAIN3 ((volatile uint32_t *)0xfe050b0c)
+#define P_EE_AUDIO_TDMOUT_C_MASK4 ((volatile uint32_t *)0xfe050b10)
+#define P_EE_AUDIO_TDMOUT_C_MASK5 ((volatile uint32_t *)0xfe050b14)
+#define P_EE_AUDIO_TDMOUT_C_MASK6 ((volatile uint32_t *)0xfe050b18)
+#define P_EE_AUDIO_TDMOUT_C_MASK7 ((volatile uint32_t *)0xfe050b1c)
+#define P_EE_AUDIO_TDMOUT_C_MUTE4 ((volatile uint32_t *)0xfe050b20)
+#define P_EE_AUDIO_TDMOUT_C_MUTE5 ((volatile uint32_t *)0xfe050b24)
+#define P_EE_AUDIO_TDMOUT_C_MUTE6 ((volatile uint32_t *)0xfe050b28)
+#define P_EE_AUDIO_TDMOUT_C_MUTE7 ((volatile uint32_t *)0xfe050b2c)
+//========================================================================
+// PDM - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051000
+// -----------------------------------------------
+#define P_PDM_CTRL ((volatile uint32_t *)0xfe051000)
+//bit 31: PDM enable.
+//bit 30: invert the PDM_DCLK.
+//bit 29: output mode: 1: 24bits. 0: 32 bits.
+//bit 28: bypass mode. 1: bypass all filter. directly output the PDM input to DDR. 0: normal mode.
+//bit 27~9: not used.
+//bit 16:. PDM Asynchronous FIFO soft reset. write 1 to soft reset AFIFO.
+//bit 15:8 PDM channel reset. 0: to reset each PDM channel. 1: normal mode.
+//bit 7:0. PDM channel enable. each bit for one channel.
+#define P_PDM_HCIC_CTRL1 ((volatile uint32_t *)0xfe051004)
+//bit 31 hcic filter enable. 1 use sinc filter. 0 bypass input to output.
+//bit 29:24. hcic final gain shift parameter.
+//bit 23:16 hcic final gain multiplier.
+//bit 8:4 hcic down sample rate.
+//bit 3:0 hcic stage number. must be between 3 to 9.
+#define P_PDM_HCIC_CTRL2 ((volatile uint32_t *)0xfe051008)
+//Not used.
+#define P_PDM_F1_CTRL ((volatile uint32_t *)0xfe05100c)
+//bit 31 . filter 1 enable.
+//bit 16:15. f1 round mode. 2'b00 : sign bit at bit 49. 28bits output [49:22] round at bit 21. 32bits output [49:18]. 24bits output [49:26]
+// 2'b01 : sign bit at bit 50. 28bits output [50:23] round at bit 22. 32bits output [49:18]. 24bits output [49:26]
+// 2'b10 : sign bit at bit 51. 28bits output [51:24] round at bit 23 32bits output [49:18]. 24bits output [49:26].
+//bit 15:12. filter 1 down sample rate.
+//bit 8:0. filter 1 stage number.
+#define P_PDM_F2_CTRL ((volatile uint32_t *)0xfe051010)
+//bit 31 . filter 2 enable.
+//bit 16:15. f2 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23.
+//bit 15:12. filter 2 down sample rate.
+//bit 8:0. filter 2 stage number.
+#define P_PDM_F3_CTRL ((volatile uint32_t *)0xfe051014)
+//bit 31 . filter 3 enable.
+//bit 16:15. f3 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23.
+//bit 15:12. filter 3 down sample rate.
+//bit 8:0. filter 3 stage number.
+#define P_PDM_HPF_CTRL ((volatile uint32_t *)0xfe051018)
+//bit 31 High pass filter enable.
+//bit 20:16 high pass filter shift steps. 6~19 steps.
+//bit 15:0 high pass filter output factor.
+#define P_PDM_CHAN_CTRL ((volatile uint32_t *)0xfe05101c)
+//bit 31:24. chan3 data sample pointer vs edge of the PDM_DCLK.
+//bit 23:16 chan2 data sample pointer vs edge of the PDM_DCLK.
+//bit 15:8. chan1 data sample pointer vs edge of the PDM_DCLK.
+//bit 7:0 chan0 data sample pointer vs edge of the PDM_DCLK.
+#define P_PDM_CHAN_CTRL1 ((volatile uint32_t *)0xfe051020)
+//bit 31:24. chan7 data sample pointer vs edge of the PDM_DCLK.
+//bit 23:16 chan6 data sample pointer vs edge of the PDM_DCLK.
+//bit 15:8. chan5 data sample pointer vs edge of the PDM_DCLK.
+//bit 7:0 chan4 data sample pointer vs edge of the PDM_DCLK.
+#define P_PDM_COEFF_ADDR ((volatile uint32_t *)0xfe051024)
+// address of the write/read of coeff data.
+#define P_PDM_COEFF_DATA ((volatile uint32_t *)0xfe051028)
+//write/read data to coeff memory.
+#define P_PDM_CLKG_CTRL ((volatile uint32_t *)0xfe05102c)
+// auto clock gating control. 1: disable the clock gating function. the clock will awlays enabled. 0 : use RTL auto clock gating.
+//31:7 not used.
+//bit 6 filt_ctrl module auto clock gating control.
+//bit 5 sinc fifo module auto clock gating control.
+//bit 4 filter module auto clock gating control.
+//bit 3 apb module auto clock gating control.
+//bit 2 coeff memory module auto clock gating control.
+//bit 1 each channel module auto clock gating control.
+//bit 0 cts_pdm_clk auto clock gating control.
+#define P_PDM_STS ((volatile uint32_t *)0xfe051030)
+//bit 1 HPF filter output overflow. means the PCLK is too slow.
+//bit 0 HCIC filter output overflow. means the CTS_PDM_CLK is too slow. can't finished the filter function.
+#define P_PDM_MUTE_VALUE ((volatile uint32_t *)0xfe051034)
+#define P_PDM_MASK_NUM ((volatile uint32_t *)0xfe051038)
+//========================================================================
+// EQ DRC - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe052000
+// -----------------------------------------------
+#define P_AED_COEF_RAM_CNTL ((volatile uint32_t *)0xfe052000)
+#define P_AED_COEF_RAM_DATA ((volatile uint32_t *)0xfe052004)
+#define P_AED_EQ_EN ((volatile uint32_t *)0xfe052008)
+#define P_AED_EQ_TAP_CNTL ((volatile uint32_t *)0xfe05200c)
+#define P_AED_EQ_VOLUME ((volatile uint32_t *)0xfe052010)
+#define P_AED_EQ_VOLUME_SLEW_CNT ((volatile uint32_t *)0xfe052014)
+#define P_AED_MUTE ((volatile uint32_t *)0xfe052018)
+#define P_AED_DRC_CNTL ((volatile uint32_t *)0xfe05201c)
+#define P_AED_DRC_RMS_COEF0 ((volatile uint32_t *)0xfe052020)
+#define P_AED_DRC_RMS_COEF1 ((volatile uint32_t *)0xfe052024)
+#define P_AED_DRC_THD0 ((volatile uint32_t *)0xfe052028)
+#define P_AED_DRC_THD1 ((volatile uint32_t *)0xfe05202c)
+#define P_AED_DRC_THD2 ((volatile uint32_t *)0xfe052030)
+#define P_AED_DRC_THD3 ((volatile uint32_t *)0xfe052034)
+#define P_AED_DRC_THD4 ((volatile uint32_t *)0xfe052038)
+#define P_AED_DRC_K0 ((volatile uint32_t *)0xfe05203c)
+#define P_AED_DRC_K1 ((volatile uint32_t *)0xfe052040)
+#define P_AED_DRC_K2 ((volatile uint32_t *)0xfe052044)
+#define P_AED_DRC_K3 ((volatile uint32_t *)0xfe052048)
+#define P_AED_DRC_K4 ((volatile uint32_t *)0xfe05204c)
+#define P_AED_DRC_K5 ((volatile uint32_t *)0xfe052050)
+#define P_AED_DRC_THD_OUT0 ((volatile uint32_t *)0xfe052054)
+#define P_AED_DRC_THD_OUT1 ((volatile uint32_t *)0xfe052058)
+#define P_AED_DRC_THD_OUT2 ((volatile uint32_t *)0xfe05205c)
+#define P_AED_DRC_THD_OUT3 ((volatile uint32_t *)0xfe052060)
+#define P_AED_DRC_OFFSET ((volatile uint32_t *)0xfe052064)
+#define P_AED_DRC_RELEASE_COEF00 ((volatile uint32_t *)0xfe052068)
+#define P_AED_DRC_RELEASE_COEF01 ((volatile uint32_t *)0xfe05206c)
+#define P_AED_DRC_RELEASE_COEF10 ((volatile uint32_t *)0xfe052070)
+#define P_AED_DRC_RELEASE_COEF11 ((volatile uint32_t *)0xfe052074)
+#define P_AED_DRC_RELEASE_COEF20 ((volatile uint32_t *)0xfe052078)
+#define P_AED_DRC_RELEASE_COEF21 ((volatile uint32_t *)0xfe05207c)
+#define P_AED_DRC_RELEASE_COEF30 ((volatile uint32_t *)0xfe052080)
+#define P_AED_DRC_RELEASE_COEF31 ((volatile uint32_t *)0xfe052084)
+#define P_AED_DRC_RELEASE_COEF40 ((volatile uint32_t *)0xfe052088)
+#define P_AED_DRC_RELEASE_COEF41 ((volatile uint32_t *)0xfe05208c)
+#define P_AED_DRC_RELEASE_COEF50 ((volatile uint32_t *)0xfe052090)
+#define P_AED_DRC_RELEASE_COEF51 ((volatile uint32_t *)0xfe052094)
+#define P_AED_DRC_ATTACK_COEF00 ((volatile uint32_t *)0xfe052098)
+#define P_AED_DRC_ATTACK_COEF01 ((volatile uint32_t *)0xfe05209c)
+#define P_AED_DRC_ATTACK_COEF10 ((volatile uint32_t *)0xfe0520a0)
+#define P_AED_DRC_ATTACK_COEF11 ((volatile uint32_t *)0xfe0520a4)
+#define P_AED_DRC_ATTACK_COEF20 ((volatile uint32_t *)0xfe0520a8)
+#define P_AED_DRC_ATTACK_COEF21 ((volatile uint32_t *)0xfe0520ac)
+#define P_AED_DRC_ATTACK_COEF30 ((volatile uint32_t *)0xfe0520b0)
+#define P_AED_DRC_ATTACK_COEF31 ((volatile uint32_t *)0xfe0520b4)
+#define P_AED_DRC_ATTACK_COEF40 ((volatile uint32_t *)0xfe0520b8)
+#define P_AED_DRC_ATTACK_COEF41 ((volatile uint32_t *)0xfe0520bc)
+#define P_AED_DRC_ATTACK_COEF50 ((volatile uint32_t *)0xfe0520c0)
+#define P_AED_DRC_ATTACK_COEF51 ((volatile uint32_t *)0xfe0520c4)
+#define P_AED_DRC_LOOPBACK_CNTL ((volatile uint32_t *)0xfe0520c8)
+#define P_AED_MDRC_CNTL ((volatile uint32_t *)0xfe0520cc)
+#define P_AED_MDRC_RMS_COEF00 ((volatile uint32_t *)0xfe0520d0)
+#define P_AED_MDRC_RMS_COEF01 ((volatile uint32_t *)0xfe0520d4)
+#define P_AED_MDRC_RELEASE_COEF00 ((volatile uint32_t *)0xfe0520d8)
+#define P_AED_MDRC_RELEASE_COEF01 ((volatile uint32_t *)0xfe0520dc)
+#define P_AED_MDRC_ATTACK_COEF00 ((volatile uint32_t *)0xfe0520e0)
+#define P_AED_MDRC_ATTACK_COEF01 ((volatile uint32_t *)0xfe0520e4)
+#define P_AED_MDRC_THD0 ((volatile uint32_t *)0xfe0520e8)
+#define P_AED_MDRC_K0 ((volatile uint32_t *)0xfe0520ec)
+#define P_AED_MDRC_LOW_GAIN ((volatile uint32_t *)0xfe0520f0)
+#define P_AED_MDRC_OFFSET0 ((volatile uint32_t *)0xfe0520f4)
+#define P_AED_MDRC_RMS_COEF10 ((volatile uint32_t *)0xfe0520f8)
+#define P_AED_MDRC_RMS_COEF11 ((volatile uint32_t *)0xfe0520fc)
+#define P_AED_MDRC_RELEASE_COEF10 ((volatile uint32_t *)0xfe052100)
+#define P_AED_MDRC_RELEASE_COEF11 ((volatile uint32_t *)0xfe052104)
+#define P_AED_MDRC_ATTACK_COEF10 ((volatile uint32_t *)0xfe052108)
+#define P_AED_MDRC_ATTACK_COEF11 ((volatile uint32_t *)0xfe05210c)
+#define P_AED_MDRC_THD1 ((volatile uint32_t *)0xfe052110)
+#define P_AED_MDRC_K1 ((volatile uint32_t *)0xfe052114)
+#define P_AED_MDRC_OFFSET1 ((volatile uint32_t *)0xfe052118)
+#define P_AED_MDRC_MID_GAIN ((volatile uint32_t *)0xfe05211c)
+#define P_AED_MDRC_RMS_COEF20 ((volatile uint32_t *)0xfe052120)
+#define P_AED_MDRC_RMS_COEF21 ((volatile uint32_t *)0xfe052124)
+#define P_AED_MDRC_RELEASE_COEF20 ((volatile uint32_t *)0xfe052128)
+#define P_AED_MDRC_RELEASE_COEF21 ((volatile uint32_t *)0xfe05212c)
+#define P_AED_MDRC_ATTACK_COEF20 ((volatile uint32_t *)0xfe052130)
+#define P_AED_MDRC_ATTACK_COEF21 ((volatile uint32_t *)0xfe052134)
+#define P_AED_MDRC_THD2 ((volatile uint32_t *)0xfe052138)
+#define P_AED_MDRC_K2 ((volatile uint32_t *)0xfe05213c)
+#define P_AED_MDRC_OFFSET2 ((volatile uint32_t *)0xfe052140)
+#define P_AED_MDRC_HIGH_GAIN ((volatile uint32_t *)0xfe052144)
+#define P_AED_ED_CNTL ((volatile uint32_t *)0xfe052148)
+#define P_AED_DC_EN ((volatile uint32_t *)0xfe05214c)
+#define P_AED_ND_LOW_THD ((volatile uint32_t *)0xfe052150)
+#define P_AED_ND_HIGH_THD ((volatile uint32_t *)0xfe052154)
+#define P_AED_ND_CNT_THD ((volatile uint32_t *)0xfe052158)
+#define P_AED_ND_SUM_NUM ((volatile uint32_t *)0xfe05215c)
+#define P_AED_ND_CZ_NUM ((volatile uint32_t *)0xfe052160)
+#define P_AED_ND_SUM_THD0 ((volatile uint32_t *)0xfe052164)
+#define P_AED_ND_SUM_THD1 ((volatile uint32_t *)0xfe052168)
+#define P_AED_ND_CZ_THD0 ((volatile uint32_t *)0xfe05216c)
+#define P_AED_ND_CZ_THD1 ((volatile uint32_t *)0xfe052170)
+#define P_AED_ND_COND_CNTL ((volatile uint32_t *)0xfe052174)
+#define P_AED_ND_RELEASE_COEF0 ((volatile uint32_t *)0xfe052178)
+#define P_AED_ND_RELEASE_COEF1 ((volatile uint32_t *)0xfe05217c)
+#define P_AED_ND_ATTACK_COEF0 ((volatile uint32_t *)0xfe052180)
+#define P_AED_ND_ATTACK_COEF1 ((volatile uint32_t *)0xfe052184)
+#define P_AED_ND_CNTL ((volatile uint32_t *)0xfe052188)
+#define P_AED_MIX0_LL ((volatile uint32_t *)0xfe05218c)
+#define P_AED_MIX0_RL ((volatile uint32_t *)0xfe052190)
+#define P_AED_MIX0_LR ((volatile uint32_t *)0xfe052194)
+#define P_AED_MIX0_RR ((volatile uint32_t *)0xfe052198)
+#define P_AED_CLIP_THD ((volatile uint32_t *)0xfe05219c)
+#define P_AED_CH1_ND_SUM_OUT ((volatile uint32_t *)0xfe0521a0)
+#define P_AED_CH2_ND_SUM_OUT ((volatile uint32_t *)0xfe0521a4)
+#define P_AED_CH1_ND_CZ_OUT ((volatile uint32_t *)0xfe0521a8)
+#define P_AED_CH2_ND_CZ_OUT ((volatile uint32_t *)0xfe0521ac)
+#define P_AED_NOISE_STATUS ((volatile uint32_t *)0xfe0521b0)
+#define P_AED_POW_CURRENT_S0 ((volatile uint32_t *)0xfe0521b4)
+#define P_AED_POW_CURRENT_S1 ((volatile uint32_t *)0xfe0521b8)
+#define P_AED_POW_CURRENT_S2 ((volatile uint32_t *)0xfe0521bc)
+#define P_AED_POW_OUT0 ((volatile uint32_t *)0xfe0521c0)
+#define P_AED_POW_OUT1 ((volatile uint32_t *)0xfe0521c4)
+#define P_AED_POW_OUT2 ((volatile uint32_t *)0xfe0521c8)
+#define P_AED_POW_ADJ_INDEX0 ((volatile uint32_t *)0xfe0521cc)
+#define P_AED_POW_ADJ_INDEX1 ((volatile uint32_t *)0xfe0521d0)
+#define P_AED_POW_ADJ_INDEX2 ((volatile uint32_t *)0xfe0521d4)
+#define P_AED_DRC_GAIN_INDEX0 ((volatile uint32_t *)0xfe0521d8)
+#define P_AED_DRC_GAIN_INDEX1 ((volatile uint32_t *)0xfe0521dc)
+#define P_AED_DRC_GAIN_INDEX2 ((volatile uint32_t *)0xfe0521e0)
+#define P_AED_CH1_VOLUME_STATE ((volatile uint32_t *)0xfe0521e4)
+#define P_AED_CH2_VOLUME_STATE ((volatile uint32_t *)0xfe0521e8)
+#define P_AED_CH1_VOLUME_GAIN ((volatile uint32_t *)0xfe0521ec)
+#define P_AED_CH2_VOLUME_GAIN ((volatile uint32_t *)0xfe0521f0)
+#define P_AED_FULL_POW_CURRENT ((volatile uint32_t *)0xfe0521f4)
+#define P_AED_FULL_POW_OUT ((volatile uint32_t *)0xfe0521f8)
+#define P_AED_FULL_POW_ADJ ((volatile uint32_t *)0xfe0521fc)
+#define P_AED_FULL_DRC_GAIN ((volatile uint32_t *)0xfe052200)
+#define P_AED_MASTER_VOLUME_STATE ((volatile uint32_t *)0xfe052204)
+#define P_AED_MASTER_VOLUME_GAIN ((volatile uint32_t *)0xfe052208)
+#define P_AED_TOP_CTL0 ((volatile uint32_t *)0xfe05220c)
+#define P_AED_TOP_CTL1 ((volatile uint32_t *)0xfe052210)
+#define P_AED_TOP_CTL2 ((volatile uint32_t *)0xfe052214)
+//========================================================================
+// AUDIO locker - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051400
+// -----------------------------------------------
+#define P_AUD_LOCK_EN ((volatile uint32_t *)0xfe051400)
+#define P_AUD_LOCK_SW_RESET ((volatile uint32_t *)0xfe051404)
+#define P_AUD_LOCK_SW_LATCH ((volatile uint32_t *)0xfe051408)
+#define P_AUD_LOCK_HW_LATCH ((volatile uint32_t *)0xfe05140c)
+#define P_AUD_LOCK_REFCLK_SRC ((volatile uint32_t *)0xfe051410)
+#define P_AUD_LOCK_REFCLK_LAT_INT ((volatile uint32_t *)0xfe051414)
+#define P_AUD_LOCK_IMCLK_LAT_INT ((volatile uint32_t *)0xfe051418)
+#define P_AUD_LOCK_OMCLK_LAT_INT ((volatile uint32_t *)0xfe05141c)
+#define P_AUD_LOCK_REFCLK_DS_INT ((volatile uint32_t *)0xfe051420)
+#define P_AUD_LOCK_IMCLK_DS_INT ((volatile uint32_t *)0xfe051424)
+#define P_AUD_LOCK_OMCLK_DS_INT ((volatile uint32_t *)0xfe051428)
+#define P_AUD_LOCK_INT_CLR ((volatile uint32_t *)0xfe05142c)
+#define P_AUD_LOCK_GCLK_CTRL ((volatile uint32_t *)0xfe051430)
+#define P_AUD_LOCK_INT_CTRL ((volatile uint32_t *)0xfe051434)
+#define P_RO_REF2IMCLK_CNT_L ((volatile uint32_t *)0xfe051440)
+#define P_RO_REF2IMCLK_CNT_H ((volatile uint32_t *)0xfe051444)
+#define P_RO_REF2OMCLK_CNT_L ((volatile uint32_t *)0xfe051448)
+#define P_RO_REF2OMCLK_CNT_H ((volatile uint32_t *)0xfe05144c)
+#define P_RO_IMCLK2REF_CNT_L ((volatile uint32_t *)0xfe051450)
+#define P_RO_IMCLK2REF_CNT_H ((volatile uint32_t *)0xfe051454)
+#define P_RO_OMCLK2REF_CNT_L ((volatile uint32_t *)0xfe051458)
+#define P_RO_OMCLK2REF_CNT_H ((volatile uint32_t *)0xfe05145c)
+#define P_RO_REFCLK_PKG_CNT ((volatile uint32_t *)0xfe051460)
+#define P_RO_IMCLK_PKG_CNT ((volatile uint32_t *)0xfe051464)
+#define P_RO_OMCLK_PKG_CNT ((volatile uint32_t *)0xfe051468)
+#define P_RO_AUD_LOCK_INT_STATUS ((volatile uint32_t *)0xfe05146c)
+//========================================================================
+// AUDIO VAD - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051800
+// -----------------------------------------------
+//
+// Reading file: VAD_REG.h
+//
+#define P_VAD_TOP_CTRL0 ((volatile uint32_t *)0xfe051800)
+#define P_VAD_TOP_CTRL1 ((volatile uint32_t *)0xfe051804)
+#define P_VAD_TOP_CTRL2 ((volatile uint32_t *)0xfe051808)
+#define P_VAD_FIR_CTRL ((volatile uint32_t *)0xfe05180c)
+#define P_VAD_FIR_EMP ((volatile uint32_t *)0xfe051810)
+#define P_VAD_FIR_COEF0 ((volatile uint32_t *)0xfe051814)
+#define P_VAD_FIR_COEF1 ((volatile uint32_t *)0xfe051818)
+#define P_VAD_FIR_COEF2 ((volatile uint32_t *)0xfe05181c)
+#define P_VAD_FIR_COEF3 ((volatile uint32_t *)0xfe051820)
+#define P_VAD_FIR_COEF4 ((volatile uint32_t *)0xfe051824)
+#define P_VAD_FIR_COEF5 ((volatile uint32_t *)0xfe051828)
+#define P_VAD_FIR_COEF6 ((volatile uint32_t *)0xfe05182c)
+#define P_VAD_FIR_COEF7 ((volatile uint32_t *)0xfe051830)
+#define P_VAD_FIR_COEF8 ((volatile uint32_t *)0xfe051834)
+#define P_VAD_FIR_COEF9 ((volatile uint32_t *)0xfe051838)
+#define P_VAD_FIR_COEF10 ((volatile uint32_t *)0xfe05183c)
+#define P_VAD_FIR_COEF11 ((volatile uint32_t *)0xfe051840)
+#define P_VAD_FIR_COEF12 ((volatile uint32_t *)0xfe051844)
+#define P_VAD_FRAME_CTRL0 ((volatile uint32_t *)0xfe051848)
+#define P_VAD_FRAME_CTRL1 ((volatile uint32_t *)0xfe05184c)
+#define P_VAD_FRAME_CTRL2 ((volatile uint32_t *)0xfe051850)
+#define P_VAD_CEP_CTRL0 ((volatile uint32_t *)0xfe051854)
+#define P_VAD_CEP_CTRL1 ((volatile uint32_t *)0xfe051858)
+#define P_VAD_CEP_CTRL2 ((volatile uint32_t *)0xfe05185c)
+#define P_VAD_CEP_CTRL3 ((volatile uint32_t *)0xfe051860)
+#define P_VAD_CEP_CTRL4 ((volatile uint32_t *)0xfe051864)
+#define P_VAD_CEP_CTRL5 ((volatile uint32_t *)0xfe051868)
+#define P_VAD_DEC_CTRL ((volatile uint32_t *)0xfe05186c)
+#define P_VAD_TOP_STS0 ((volatile uint32_t *)0xfe051870)
+#define P_VAD_TOP_STS1 ((volatile uint32_t *)0xfe051874)
+#define P_VAD_TOP_STS2 ((volatile uint32_t *)0xfe051878)
+#define P_VAD_FIR_STS0 ((volatile uint32_t *)0xfe05187c)
+#define P_VAD_FIR_STS1 ((volatile uint32_t *)0xfe051880)
+#define P_VAD_POW_STS0 ((volatile uint32_t *)0xfe051884)
+#define P_VAD_POW_STS1 ((volatile uint32_t *)0xfe051888)
+#define P_VAD_POW_STS2 ((volatile uint32_t *)0xfe05188c)
+#define P_VAD_FFT_STS0 ((volatile uint32_t *)0xfe051890)
+#define P_VAD_FFT_STS1 ((volatile uint32_t *)0xfe051894)
+#define P_VAD_SPE_STS0 ((volatile uint32_t *)0xfe051898)
+#define P_VAD_SPE_STS1 ((volatile uint32_t *)0xfe05189c)
+#define P_VAD_SPE_STS2 ((volatile uint32_t *)0xfe0518a0)
+#define P_VAD_SPE_STS3 ((volatile uint32_t *)0xfe0518a4)
+#define P_VAD_DEC_STS0 ((volatile uint32_t *)0xfe0518a8)
+#define P_VAD_DEC_STS1 ((volatile uint32_t *)0xfe0518ac)
+#define P_VAD_LUT_CTRL ((volatile uint32_t *)0xfe0518b0)
+#define P_VAD_LUT_WR ((volatile uint32_t *)0xfe0518b4)
+#define P_VAD_LUT_RD ((volatile uint32_t *)0xfe0518b8)
+#define P_VAD_IN_SEL0 ((volatile uint32_t *)0xfe0518bc)
+#define P_VAD_IN_SEL1 ((volatile uint32_t *)0xfe0518c0)
+#define P_VAD_TO_DDR ((volatile uint32_t *)0xfe0518c4)
+//
+// Closing file: VAD_REG.h
+//
+//========================================================================
+// AUDIO RESAMPLEA - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051c00
+// -----------------------------------------------
+//
+// Reading file: RESAMPLE.h
+//
+#define P_AUDIO_RSAMP_CTRL0 ((volatile uint32_t *)0xfe051c00)
+//Bit 31:3 reserved
+//Bit 2 reg_lock_rst //unsigned , default =0;
+//Bit 1 reg_rsamp_rst //unsigned , default =0;
+//Bit 0 reg_sw_rst //unsigned , default =0;
+#define P_AUDIO_RSAMP_CTRL1 ((volatile uint32_t *)0xfe051c04)
+//Bit 31:26 reserved //unsigned , default =0;
+//Bit 25 reg_rsamp_rst_sel //unsigned , default =0;
+//Bit 24 reg_module_bypas //unsigned , default =0;
+//Bit 23:18 reg_gclk_ctrl //unsigned , default =0;
+//Bit 17:13 reg_in_msb //unsigned , default =23;
+//Bit 12 reg_output_en //unsigned , default =0;
+//Bit 11 reg_rsamp_en //unsigned , default =0;
+//Bit 10 reg_filt_en //unsigned , default =0;
+//Bit 9 reg_post_en //unsigned , default =0;
+//Bit 8 reg_inp_mux_mode //unsigned , default =0;
+//Bit 7:4 reserved //unsigned , default =2;
+//Bit 3:0 reg_inp_mux //unsigned , default =0;
+#define P_AUDIO_RSAMP_CTRL2 ((volatile uint32_t *)0xfe051c08)
+//Bit 31:30 reserved //unsigned , default =0;
+//Bit 29:24 reg_chx_size //unsigned , default =2;
+//Bit 23:18 reserved //unsigned , default =0;
+//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4
+//Bit 15:8 reg_filt_tap //unsigned , default =63;
+//Bit 7:0 reg_intp_tap //unsigned , default =63;
+#define P_AUDIO_RSAMP_PHSINIT ((volatile uint32_t *)0xfe051c0c)
+//Bit 31:28 reserved //unsigned , default = 0;
+//Bit 27:0 reg_init_phs //unsigned , default = 0;
+#define P_AUDIO_RSAMP_PHSSTEP ((volatile uint32_t *)0xfe051c10)
+//Bit 31 reserved //unsigned , default = 0;
+//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000
+#define P_AUDIO_RSAMP_SHIFT ((volatile uint32_t *)0xfe051c14)
+//Bit 31:24 reg_rsft_iir //unsigned , default = 23;
+//Bit 23:16 reg_rsft_blnd //unsigned , default = 21;
+//Bit 15:8 reg_rsft_sinc //unsigned , default = 31;
+//Bit 7:0 reg_rsft_aa //unsigned , default = 31;
+#define P_AUDIO_RSAMP_ADJ_CTRL0 ((volatile uint32_t *)0xfe051c18)
+//Bit 31:3 reserved //unsigned
+//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0;
+//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0;
+//Bit 0 reg_rsamp_adj_en //unsigned , default = 0;
+#define P_AUDIO_RSAMP_ADJ_CTRL1 ((volatile uint32_t *)0xfe051c1c)
+//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8;
+//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768;
+#define P_AUDIO_RSAMP_ADJ_SFT ((volatile uint32_t *)0xfe051c20)
+//Bit 31:30 reserved //unsigned , default = 0;
+//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0;
+//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9;
+//Bit 23:21 reserved //unsigned , default = 0;
+//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1;
+//Bit 15:13 reserved //unsigned , default = 0;
+//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6;
+//Bit 7:6 reserved //unsigned , default = 0;
+//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12;
+#define P_AUDIO_RSAMP_ADJ_IDET_LEN ((volatile uint32_t *)0xfe051c24)
+//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000;
+#define P_AUDIO_RSAMP_ADJ_FORCE ((volatile uint32_t *)0xfe051c28)
+//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8;
+#define P_AUDIO_RSAMP_ADJ_KI_FORCE ((volatile uint32_t *)0xfe051c2c)
+//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0;
+#define P_AUDIO_RSAMP_RO_STATUS ((volatile uint32_t *)0xfe051c40)
+//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]}
+#define P_AUDIO_RSAMP_RO_ADJ_FREQ ((volatile uint32_t *)0xfe051c44)
+//Bit 31:0 ro_rsamp_adj_freq
+#define P_AUDIO_RSAMP_RO_ADJ_DIFF_BAK ((volatile uint32_t *)0xfe051c48)
+//Bit 31:0 ro_det_diff_bak
+#define P_AUDIO_RSAMP_RO_ADJ_DIFF_DLT ((volatile uint32_t *)0xfe051c4c)
+//Bit 31:0 ro_det_diff_dlt
+#define P_AUDIO_RSAMP_RO_ADJ_PHS_ERR ((volatile uint32_t *)0xfe051c50)
+//Bit 31:0 ro_det_phase_err
+#define P_AUDIO_RSAMP_RO_ADJ_KI_OUT ((volatile uint32_t *)0xfe051c54)
+//Bit 31:0 ro_rsamp_ki_out
+#define P_AUDIO_RSAMP_RO_IN_CNT ((volatile uint32_t *)0xfe051c58)
+//Bit 31:0 ro_rsamp_in_cnt
+#define P_AUDIO_RSAMP_RO_OUT_CNT ((volatile uint32_t *)0xfe051c5c)
+//Bit 31:0 ro_rsamp_out_cnt
+#define P_AUDIO_RSAMP_POST_COEF0 ((volatile uint32_t *)0xfe051c80)
+//Bit 31:0 reg_post_coef0 //signed , default = 0;
+#define P_AUDIO_RSAMP_POST_COEF1 ((volatile uint32_t *)0xfe051c84)
+//Bit 31:0 reg_post_coef1 //signed , default = 0;
+#define P_AUDIO_RSAMP_POST_COEF2 ((volatile uint32_t *)0xfe051c88)
+//Bit 31:0 reg_post_coef2 //signed , default = 0;
+#define P_AUDIO_RSAMP_POST_COEF3 ((volatile uint32_t *)0xfe051c8c)
+//Bit 31:0 reg_post_coef3 //signed , default = 0;
+#define P_AUDIO_RSAMP_POST_COEF4 ((volatile uint32_t *)0xfe051c90)
+//Bit 31:0 reg_post_coef4 //signed , default = 0;
+#define P_AUDIO_RSAMP_AA_COEF_ADDR ((volatile uint32_t *)0xfe051cc0)
+//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0;
+#define P_AUDIO_RSAMP_AA_COEF_DATA ((volatile uint32_t *)0xfe051cc4)
+//Bit 31:0 reg_aa_coef_data //signed , default = 0;
+#define P_AUDIO_RSAMP_SINC_COEF_ADDR ((volatile uint32_t *)0xfe051d00)
+//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0;
+#define P_AUDIO_RSAMP_SINC_COEF_DATA ((volatile uint32_t *)0xfe051d04)
+//Bit 31:0 reg_sinc_coef_data //signed , default = 0;
+//
+// Closing file: RESAMPLE.h
+//
+//========================================================================
+// AUDIO TOP_VAD - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe054800
+// -----------------------------------------------
+#define P_EE_AUDIO2_CLK81_CTRL ((volatile uint32_t *)0xfe054800)
+#define P_EE_AUDIO2_CLK81_EN ((volatile uint32_t *)0xfe054804)
+#define P_EE_AUDIO2_SW_RESET0 ((volatile uint32_t *)0xfe054808)
+#define P_EE_AUDIO2_CLK_GATE_EN0 ((volatile uint32_t *)0xfe05480c)
+#define P_EE_AUDIO2_SECURITY_CTRL0 ((volatile uint32_t *)0xfe054810)
+#define P_EE_AUDIO2_MCLK_VAD_CTRL ((volatile uint32_t *)0xfe054840)
+#define P_EE_AUDIO2_VAD_CLK_CTRL ((volatile uint32_t *)0xfe054844)
+#define P_EE_AUDIO2_MST_DLY_CTRL0 ((volatile uint32_t *)0xfe054848)
+#define P_EE_AUDIO2_MST_VAD_SCLK_CTRL0 ((volatile uint32_t *)0xfe05484c)
+#define P_EE_AUDIO2_MST_VAD_SCLK_CTRL1 ((volatile uint32_t *)0xfe054850)
+#define P_EE_AUDIO2_CLK_TDMIN_VAD_CTRL ((volatile uint32_t *)0xfe054854)
+#define P_EE_AUDIO2_CLK_PDMIN_CTRL0 ((volatile uint32_t *)0xfe054858)
+#define P_EE_AUDIO2_CLK_PDMIN_CTRL1 ((volatile uint32_t *)0xfe05485c)
+#define P_EE_AUDIO2_TOVAD_CTRL0 ((volatile uint32_t *)0xfe054880)
+#define P_EE_AUDIO2_TODDR_VAD_CTRL0 ((volatile uint32_t *)0xfe0548c0)
+#define P_EE_AUDIO2_TODDR_VAD_CTRL1 ((volatile uint32_t *)0xfe0548c4)
+#define P_EE_AUDIO2_TODDR_VAD_CTRL2 ((volatile uint32_t *)0xfe0548c8)
+#define P_EE_AUDIO2_TODDR_VAD_START_ADDR ((volatile uint32_t *)0xfe0548cc)
+#define P_EE_AUDIO2_TODDR_VAD_INIT_ADDR ((volatile uint32_t *)0xfe0548d0)
+#define P_EE_AUDIO2_TODDR_VAD_FINISH_ADDR ((volatile uint32_t *)0xfe0548d4)
+#define P_EE_AUDIO2_TODDR_VAD_START_ADDRB ((volatile uint32_t *)0xfe0548d8)
+#define P_EE_AUDIO2_TODDR_VAD_FINISH_ADDRB ((volatile uint32_t *)0xfe0548dc)
+#define P_EE_AUDIO2_TODDR_VAD_INT_ADDR ((volatile uint32_t *)0xfe0548e0)
+#define P_EE_AUDIO2_TODDR_VAD_STATUS1 ((volatile uint32_t *)0xfe0548e4)
+#define P_EE_AUDIO2_TODDR_VAD_STATUS2 ((volatile uint32_t *)0xfe0548e8)
+#define P_EE_AUDIO2_TDMIN_VAD_CTRL ((volatile uint32_t *)0xfe054900)
+#define P_EE_AUDIO2_TDMIN_VAD_SWAP0 ((volatile uint32_t *)0xfe054904)
+#define P_EE_AUDIO2_TDMIN_VAD_SWAP1 ((volatile uint32_t *)0xfe054908)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE_VAL ((volatile uint32_t *)0xfe05490c)
+#define P_EE_AUDIO2_TDMIN_VAD_STAT ((volatile uint32_t *)0xfe054910)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE0 ((volatile uint32_t *)0xfe054940)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE1 ((volatile uint32_t *)0xfe054944)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE2 ((volatile uint32_t *)0xfe054948)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE3 ((volatile uint32_t *)0xfe05494c)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE4 ((volatile uint32_t *)0xfe054950)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE5 ((volatile uint32_t *)0xfe054954)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE6 ((volatile uint32_t *)0xfe054958)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE7 ((volatile uint32_t *)0xfe05495c)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK0 ((volatile uint32_t *)0xfe054960)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK1 ((volatile uint32_t *)0xfe054964)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK2 ((volatile uint32_t *)0xfe054968)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK3 ((volatile uint32_t *)0xfe05496c)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK4 ((volatile uint32_t *)0xfe054970)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK5 ((volatile uint32_t *)0xfe054974)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK6 ((volatile uint32_t *)0xfe054978)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK7 ((volatile uint32_t *)0xfe05497c)
+//
+// Closing file: REG_LIST_AUDIO_RTL.h
+//
+//
+// Reading file: ../spifc/rtl/spifc_reg.vh
+//
+//`ifdef SPIFC_REG_DEFINE
+//`else
+//`define SPIFC_REG_DEFINE
+//`define SPIFC BASE ADDR 32'hfd000400
+// -----------------------------------------------
+// APB_BASE: APB2_BASE_ADDR = 0xfd000400
+// -----------------------------------------------
+//AHB domain regsiter.
+#define P_SPIFC_AHB_CTRL ((volatile uint32_t *)0xfd000400)
+//bit 31 AHB BUS enable. 1 enable ahb request. 0: disable ahb request.
+//bit 30. decerr_en for (AXI->AHB bridge).
+//bit 29. force_incr. for ( AXI->AHB bridge).
+//bit 19. critical word first. CWF_EN. 1: enable. 0 : disable.
+//bit 18:17 RDBUF_SIZE . 00: 64bytes. 01: 32 bytes. 10: 16 bytes. 11: reserved.
+//bit 16 AHB MASTER enable. if enabled, each master use one dedicated HRDATA buffer inside ahb2api model. total 3 HRDATA buffers inside ahb2spi.
+//if disabled the 3 HRDATA buffer will random be used for all masters.
+//bit 14 write 1 to clean the HRDATA buffer 2. read 0 finished clean operation.
+//bit 13 write 1 to clean the HRDATA buffer 1. read 0 finished clean operation.
+//bit 12 write 1 to clean the HRDATA buffer 0. read 0 finished clean operation.
+//bit 11:0. not used.
+#define P_SPIFC_CLK_CTRL ((volatile uint32_t *)0xfd000404)
+//bit 14 asynchronous buffer ahb clock disable. 1 = disable. 0 = enable.
+//bit 13 ahb2spi ahb clock disable. 1 = disable. 0 = enable.
+//bit 12 ahb_arb ahb clock disable. 1 = disable. 0 = enable.
+//bit 10 asynchronous buffer ahb clock auto gating enable. 1 = enable. 0 = disable.
+//bit 9 ahb2spi ahb clock auto gating enable. 1 = enable. 0 = disable.
+//bit 8 ahbarb ahb clock auto gating enable. 1 = enable. 0 = disable.
+//bit 2. asynchronous AHB clock domain software reset. 1 = reset. 0 = normal working mode.
+//bit 1. ahb2spi ahb clock domain software reset. 1 = reset. 0 = normal working mode.
+//bit 0. not used.
+#define P_SPIFC_SEC_CTRL ((volatile uint32_t *)0xfd000408)
+//bit 31. ADDRESS security range enable. 1 = enable; 0: disable.
+//bit 14. range6 enable: 1: enable; 0 : disable.
+//bit 13. range5 enable: 1: enable; 0 : disable.
+//bit 12. range4 enable: 1: enable; 0 : disable.
+//bit 11. range3 enable: 1: enable; 0 : disable.
+//bit 10. range2 enable: 1: enable; 0 : disable.
+//bit 9. range1 enable: 1: enable; 0 : disable.
+//bit 8. range0 enable: 1: enable; 0 : disable.
+//bit 7:4 to control spi clock register security. bit 7 = 1, APB bus can access spi clock domain register. bit 7 == 0 : only PPROT[0] == bit 4, the APB can access spic clock domain register.
+//bit 3:0 to control ahb clock domain register secruity. bit 3 = 1, APB bus can access ahb clock domain register. bit 3 ==0; only PPROT[0] == bit 0, the APB can access ahb clock domain register.
+#define P_SPIFC_RANGE0_STA ((volatile uint32_t *)0xfd000440)
+//bit 28 :6.
+//AHB security range 0 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE0_EDA ((volatile uint32_t *)0xfd000444)
+//bit 28 :6.
+//AHB security range 0 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE0_CTRL ((volatile uint32_t *)0xfd000448)
+// AHB secruity range 0 control.
+//bit 15:8 range 0 access control for DMA access.
+//bit 15 range 0 access control for DMA thread 7
+//bit 14 range 0 access control for DMA Thread 6
+//bit 13 range 0 access control for DMA Thread 5.
+//bit 12 range 0 access control for DMA Thread 4.
+// bit 11. range 0 access control for DMA thread 3
+// bit 10. range 0 access control for DMA Thread 2
+// bit 9. range 0 access control for DMA Thread 1.
+// bit 8. range 0 access control for DMA Thread 0.
+// bit 7. range 0 access control for HMASTER == 7 Not used.
+// bit 6. range 0 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 0 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 0 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 0 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 0 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 0 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 0 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE1_STA ((volatile uint32_t *)0xfd00044c)
+//bit 28 :6.
+//AHB security range 1 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE1_EDA ((volatile uint32_t *)0xfd000450)
+//bit 28 :6.
+//AHB security range 1 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE1_CTRL ((volatile uint32_t *)0xfd000454)
+// AHB secruity range 1 control.
+//bit 15:8 range 1 access control for DMA access.
+//bit 15 range 1 access control for DMA thread 7
+//bit 14 range 1 access control for DMA Thread 6
+//bit 13 range 1 access control for DMA Thread 5.
+//bit 12 range 1 access control for DMA Thread 4.
+// bit 11. range 1 access control for DMA thread 3
+// bit 10. range 1 access control for DMA Thread 2
+// bit 9. range 1 access control for DMA Thread 1.
+// bit 8. range 1 access control for DMA Thread 0.
+// bit 7. range 1 access control for HMASTER == 7 Not used.
+// bit 6. range 1 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 1 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 1 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 1 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 1 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 1 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 1 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE2_STA ((volatile uint32_t *)0xfd000458)
+//bit 28 :6.
+//AHB security range 2 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE2_EDA ((volatile uint32_t *)0xfd00045c)
+//bit 28 :6.
+//AHB security range 2 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE2_CTRL ((volatile uint32_t *)0xfd000460)
+// AHB secruity range 2 control.
+//bit 15:8 range 2 access control for DMA access.
+//bit 15 range 2 access control for DMA thread 7
+//bit 14 range 2 access control for DMA Thread 6
+//bit 13 range 2 access control for DMA Thread 5.
+//bit 12 range 2 access control for DMA Thread 4.
+// bit 11. range 2 access control for DMA thread 3
+// bit 10. range 2 access control for DMA Thread 2
+// bit 9. range 2 access control for DMA Thread 1.
+// bit 8. range 2 access control for DMA Thread 0.
+// bit 7. range 2 access control for HMASTER == 7 Not used.
+// bit 6. range 2 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 2 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 2 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 2 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 2 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 2 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 2 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE3_STA ((volatile uint32_t *)0xfd000464)
+//bit 28 :6.
+//AHB security range 3 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE3_EDA ((volatile uint32_t *)0xfd000468)
+//bit 28 :6.
+//AHB security range 3 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE3_CTRL ((volatile uint32_t *)0xfd00046c)
+// AHB secruity range 3 control.
+//bit 15:8 range 3 access control for DMA access.
+//bit 15 range 3 access control for DMA thread 7
+//bit 14 range 3 access control for DMA Thread 6
+//bit 13 range 3 access control for DMA Thread 5.
+//bit 12 range 3 access control for DMA Thread 4.
+// bit 11. range 3 access control for DMA thread 3
+// bit 10. range 3 access control for DMA Thread 2
+// bit 9. range 3 access control for DMA Thread 1.
+// bit 8. range 3 access control for DMA Thread 0.
+// bit 7. range 3 access control for HMASTER == 7 Not used.
+// bit 6. range 3 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 3 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 3 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 3 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 3 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 3 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 3 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE4_STA ((volatile uint32_t *)0xfd000470)
+//bit 28 :6.
+//AHB security range 4 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE4_EDA ((volatile uint32_t *)0xfd000474)
+//bit 28 :6.
+//AHB security range 4 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE4_CTRL ((volatile uint32_t *)0xfd000478)
+// AHB secruity range 4 control.
+//bit 15:8 range 4 access control for DMA access.
+//bit 15 range 4 access control for DMA thread 7
+//bit 14 range 4 access control for DMA Thread 6
+//bit 13 range 4 access control for DMA Thread 5.
+//bit 12 range 4 access control for DMA Thread 4.
+// bit 11. range 4 access control for DMA thread 3
+// bit 10. range 4 access control for DMA Thread 2
+// bit 9. range 4 access control for DMA Thread 1.
+// bit 8. range 4 access control for DMA Thread 0.
+// bit 7. range 4 access control for HMASTER == 7 Not used.
+// bit 6. range 4 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 4 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 4 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 4 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 4 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 4 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 4 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE5_STA ((volatile uint32_t *)0xfd00047c)
+//bit 28 :6.
+//AHB security range 5 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE5_EDA ((volatile uint32_t *)0xfd000484)
+//bit 28 :6.
+//AHB security range 5 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE5_CTRL ((volatile uint32_t *)0xfd000480)
+// AHB secruity range 5 control.
+//bit 15:8 range 5 access control for DMA access.
+//bit 15 range 5 access control for DMA thread 7
+//bit 14 range 5 access control for DMA Thread 6
+//bit 13 range 5 access control for DMA Thread 5.
+//bit 12 range 5 access control for DMA Thread 4.
+// bit 11. range 5 access control for DMA thread 3
+// bit 10. range 5 access control for DMA Thread 2
+// bit 9. range 5 access control for DMA Thread 1.
+// bit 8. range 5 access control for DMA Thread 0.
+// bit 7. range 5 access control for HMASTER == 7 Not used.
+// bit 6. range 5 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 5 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 5 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 5 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 5 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 5 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 5 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE6_STA ((volatile uint32_t *)0xfd000488)
+//bit 28 :6.
+//AHB security range 6 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE6_EDA ((volatile uint32_t *)0xfd00048c)
+//bit 28 :6.
+//AHB security range 6 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE6_CTRL ((volatile uint32_t *)0xfd000490)
+// AHB secruity range 6 control.
+//bit 15:8 range 6 access control for DMA access.
+//bit 15 range 6 access control for DMA thread 7
+//bit 14 range 6 access control for DMA Thread 6
+//bit 13 range 6 access control for DMA Thread 5.
+//bit 12 range 6 access control for DMA Thread 4.
+// bit 11. range 6 access control for DMA thread 3
+// bit 10. range 6 access control for DMA Thread 2
+// bit 9. range 6 access control for DMA Thread 1.
+// bit 8. range 6 access control for DMA Thread 0.
+// bit 7. range 6 access control for HMASTER == 7 Not used.
+// bit 6. range 6 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 6 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 6 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 6 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 6 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 6 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 6 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE7_CTRL ((volatile uint32_t *)0xfd000494)
+// AHB secruity range 7( default range) control.
+//bit 15:8 range 7 access control for DMA access.
+//bit 15 range 7 access control for DMA thread 7
+//bit 14 range 7 access control for DMA Thread 6
+//bit 13 range 7 access control for DMA Thread 5.
+//bit 12 range 7 access control for DMA Thread 4.
+// bit 11. range 7 access control for DMA thread 3
+// bit 10. range 7 access control for DMA Thread 2
+// bit 9. range 7 access control for DMA Thread 1.
+// bit 8. range 7 access control for DMA Thread 0.
+// bit 7. range 7 access control for HMASTER == 7 Not used.
+// bit 6. range 7 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 7 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 7 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 7 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 7 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 7 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 7 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_AHB_WTCH_CTRL ((volatile uint32_t *)0xfd000498)
+//bit 15:0. ahb bus watch dog timer. if AHB bus not response, the timer over this number, the SPIFC will send back a error response.
+#define P_SPIFC_SEC_VIO0 ((volatile uint32_t *)0xfd00049c)
+//bit 31:0 VIO ADDR
+#define P_SPIFC_SEC_VIO1 ((volatile uint32_t *)0xfd0004a0)
+//bit 31. AHB VIO status. write 1 to clear the error info.
+//bit 6:5 HMASTER.
+//bit 4:2 HPROT.
+//bit 1 HNONSEC.
+//bit 0 HWRITE.
+#define P_SPIFC_AHB_STS ((volatile uint32_t *)0xfd0004a4)
+//bit 31. AHB IDLE. when ahb disabled, to show ahb status. 1, no more ahb request or ahb requent is holded. 0, ahb is still busy.
+//bit 30. AHB data cycle status, when ahb disabled, to show ahb data cycle status. 1, data cycle is holded, 0 : not in data cycle or data cycle is processing.
+//bit 29. AHB bus spi requst status. 1: still waiting for spi data. 0: idle.
+//bit 28:0. not used.
+//SPI cts_spi_clk domain regsiter.
+#define P_SPIFC_USER_CTRL0 ((volatile uint32_t *)0xfd000600)
+//bit 31. user request enable. write 1 to enable. read 0, means user command accepted by the SPI_CTRL.
+//bit 30. user request finish bit. write 0 when enable user request. read 1 means SPI_CTRL finished this user command.
+//bit 0. user data updated. write 0 when enable user request. 1 means there's datas/status read from SPI flash.
+#define P_SPIFC_USER_CTRL1 ((volatile uint32_t *)0xfd000604)
+//bit 31. not used.
+//bit 30. user command cycle enable. 1) enable. 0) don't send command in usr command period.
+//bit 29:28. user command mode. 00 = SPI extend mode. 01 : dual mode. 10: quad mode.
+//bit 27:20. user command code. the code need to send in command period.
+//bit 19. user address cycle enable.
+//bit 18:17 user address mode: 00 = SPI extend mode. 01 : dual mode. 10: quad mode.
+//bit 16:15 user address Byte length 00 = 1 byte. 01 = 2 bytes. 10 = 3 bytes. 11 = 4bytes.
+//bit 14 user datout enable.
+//bit 13 user dataout AES enable. 1: dataout through AES describle. 0 : original data.
+//bit 12 user data output source. 0: from data buffer. 1: from status register.
+//bit 11:10 user dataout mode: 00 SPI extend model. 01 : dual model. 10. quad mode.
+//bit 9:0 User data out bytes num.
+#define P_SPIFC_USER_CTRL2 ((volatile uint32_t *)0xfd000608)
+//bit 31 usr_dummy_en 1: enable dummy cycles. 0 : no dummy cycles.
+//bit 30: 29 usr_dummy_mode 2'b00 = SPI extend mode. 01 dual mode. 10 Quad mode.
+//bit 28:23 user dummy clock cycle number.
+//bit 19:16. user command input/output direction control. 000000: right after the last output.
+// 1: after the first cycle of dummy cycle.
+// .....
+// 4'hf: right before the datin cycle.
+//bit 15:8. data on the dummy cycle after the first byte.
+//bit 7:0 The first bytes data showed on dummy cycle. some flash may need special data for enhance performance mode or XIP mode.
+#define P_SPIFC_USER_CTRL3 ((volatile uint32_t *)0xfd00060c)
+//bit 31 usr_datin_en 1: datain cycle enabled. 0: no datain cycle.
+//bit 30: datin_dest. 1: save the input data to STATUS register. 0 save the input data to data buffer.
+//bit 29: 1: enable datain data AES describle. 0: not use AES.
+//bit 28:27. datin mode. 2'b00 SPI extend mode. 01: dual mode. 10 Quad mode.
+//bit 25:16. user data in data bytes. how many bytes of user datain expected.
+#define P_SPIFC_USER_ADDR ((volatile uint32_t *)0xfd000610)
+//bit 31:0. 32bits user address.
+#define P_SPIFC_AHB_REQ_CTRL ((volatile uint32_t *)0xfd000614)
+//bit 31. AHB request enable.
+//bit 30 AHB cmd_en. command cycle enable.
+//bit 29:28. ahb command mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode.
+//bit 27:20:.AHB command code.
+//bit 19. ahb request address cycle enable.
+//bit 18:17 AHB ADDRESS mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode.
+//bit 16:15 AHB ADDRESS data width. 2'b00: 1byte. 2'b01 : 2bytes. 2'b10: 3bytes. 2'b11 4bytes.
+//bit 13:10 AHB request spi bus input switch time. 0 : after address cycle. 1: the frist dummy cycles. ... 0xf. after dummy cycle.
+//bit 9:8 AHB DATAIN mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode.
+//bit 7 DATA IN AES enable. 1: enable 0: disable.
+//bit 1:0 AHB REQ DATA size. 2'b00: 64bytes. 2'b01: 32 bytes. 2'b10 : 16 bytes. 2'b11: reserved. this bit settign should be same as RDBUF_SIZE setting.
+#define P_SPIFC_AHB_REQ_CTRL1 ((volatile uint32_t *)0xfd000618)
+//bit 31. ahb Dummy enable.
+//bit 30:29. ahb dummy mode.
+//bit 28:23. ahb request dummy clock cycles.
+//bit 15:0. ahb dummy period output data.
+#define P_SPIFC_AHB_REQ_CTRL2 ((volatile uint32_t *)0xfd00061c)
+//bit 1:0 AHB address position. this settign depend on SPIFC_AHB_CTRL register CWF_EN bit and RDBUF_SIZE.
+// if CWF_EN is enabled. these bit should be set to 2'b10 (16BYTE boundary).
+// if CWF_EN is disabled. these bit should be set to same as the RDBUF_SIZE and AHB REQ DATA SIZE.
+//00 : 64byte boundary.
+//01 : 32byte boundary.
+//10 : 16byte boundary.
+//11 : reserved.
+#define P_SPIFC_ACTIMING0 ((volatile uint32_t *)0xfd000620)
+//bit 31:30. tSLCH
+//bit 29:28 tCLSH
+//bit 20:16 tSHWL
+//bit 15:12 tSHSL2
+//bit 11:8 tSHSL1
+//bit 7:0 tWHSL
+#define P_SPIFC_ACTIMING1 ((volatile uint32_t *)0xfd000624)
+//bit 31. D2 pin WP_n function enable.
+//bit 30. D2 Pin value in WP_n fucntion.
+//bit 29. D3 Pin HOLD_n function enable.
+//bit 8. DTR mode. not support.
+//bit 6:4. Clock turn around delay. use it to set the system SPI clock read data delay.
+//bit 3:0. not used.
+#define P_SPIFC_ACTIMING2 ((volatile uint32_t *)0xfd000628)
+//bit 31. spi clock input pin enable. SPIFC controller used this pin as clock to latch the input data.
+//bit [3:0] spi clock input pin delay adjustment.
+//SPI DATA BUFFER. There's a total 512Byte + 64byte(orgnized as 36x128bits) SRAM .
+// since each APB access is 32bits. So we use word address as APB read/write address.
+// But for SPI side we have to use 128bit boundary. That's the first Pragram/read SPI with data buffer must start at data buffer 128bit boundary. that means the SPIFC_USE_DBUF_ADDR last 2 bits must be 0.
+#define P_SPIFC_DBUF_CTRL ((volatile uint32_t *)0xfd000640)
+//bit 31. 1 = write DBUF. 0 : read DBUF.
+//bit 30. 1. = auto update address. 0 don't change address.
+//bit 7:0 DBUF address unit 32bits.
+#define P_SPIFC_DBUF_DATA ((volatile uint32_t *)0xfd000644)
+//bit 31:0. if SPIFC_DBUF_CTRL bit 31 = 1. write to this register will trigger one write to DBUF. and the data will be writen to DBUF.
+#define P_SPIFC_USER_DBUF_ADDR ((volatile uint32_t *)0xfd000648)
+//bit 7:0. the DBUF ADDRESS used to send to or receive from SPI FLASH. the last 2 bits must be 0.
+#define P_SPIFC_FLASH_STATUS ((volatile uint32_t *)0xfd000680)
+#define P_SPIFC_STATUS ((volatile uint32_t *)0xfd000684)
+//bit 1. AES KEY valid. read only 1 : The aes key is ready to use. 0: the aes key is not ready.
+//bit 0. SPI CTRL STATE IDLE. read only. 1 = idle; 0 = busy.
+#define P_SPIFC_CTRL ((volatile uint32_t *)0xfd000688)
+//bit 15:14. mempd for DBUF MEMORY.
+//bit 13 spifc asynchronous buffer clock disable. 1 = disable. 0 = enable.
+//bit 12. spifc controller clock disable. 1 = disable. 0 = enable.
+//bit 9. spifc asynchronous bufer clock auto gate enable. 1 = enable. 0 = disable.
+//bit 8. spifc controller clock auto gate enable. 1 = enable. 0 = disable.
+//bit 2. spifc interface reset. 1 = RESET. 0 = normal working mode.
+//bit 1. spifc asynchronous buffer spi clock side reset. 1 = RESET. 0 : normal working mode.
+//bit 0. spifc controller reset. 1 = RESET. 0 : normal working mode.
+//`endif
+//
+// Closing file: ../spifc/rtl/spifc_reg.vh
+//
+//
+// Reading file: ../psram/rtl/psram_reg.vh
+//
+//`ifdef PSRAM_REG_DEFINE
+//`else
+//`define PSRAM_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007400
+// -----------------------------------------------
+#define P_PSRAM_AXI_INTF_CTRL ((volatile uint32_t *)0xfe007400)
+//bit 3 axi interface soft reset. 1 = reset AXI interface. 0 = normal.
+//bit 2 disable axi interface clock. 1 = disable; 0 = enable.
+//bit 1 axi interface auto clock gating enable. 1 = enable; 0 = disable.
+//bit 0 axi interface AXI request enable. 1 = enable. 0 = disable.
+#define P_PSRAM_DBUF_CTRL ((volatile uint32_t *)0xfe007404)
+//bit 16. MWRITE_EN. 1 : enabel mask write(with DM pin). 0 not enable.
+//bit 15:0 DBUF AGE to write back to PSRAM if DBUF is dirty. but whole DBUF data is not READ to write.(with MWRITE enabled).
+#define P_PSRAM_DBUF_CTRL1 ((volatile uint32_t *)0xfe007408)
+//bit 15:0 DBUF AGE to write back to psram if DBUF is dirty and whole DBUF data is ready to write.
+#define P_PSRAM_APB_CTRL ((volatile uint32_t *)0xfe00740c)
+//7:4 PSRAM PHY register APB secure contrl.
+//bit 7, 1: no secure control. 0 : use bit 4 to match PPROT[0] bit.
+//bit 4. when bit 7 == 0, bit 4 must match PPROT[0] to access.
+//3:0 PCTL_CTRL APB bus control regsiters secure control.
+//bit 3, 1: no secure control. 0 : use bit 0 to match PPROT[0] bit.
+//bit 0. when bit 3 == 0, bit 0 must match PPROT[0] to access.
+#define P_PSRAM_SEC_CTRL ((volatile uint32_t *)0xfe007410)
+//bit 31. ADDRESS security range enable. 1 = enable; 0: disable.
+//if scruity range disabled, but AXI data describle enabled key0 is selected.
+//bit 23 range 7 des key selection 0 : key0; 1: key1;
+//bit 22 range 6 des key selection 0 : key0; 1: key1;
+//bit 21 range 5 des key selection 0 : key0; 1: key1;
+//bit 20 range 4 des key selection 0 : key0; 1: key1;
+//bit 19 range 3 des key selection 0 : key0; 1: key1;
+//bit 18 range 2 des key selection 0 : key0; 1: key1;
+//bit 17 range 1 des key selection 0 : key0; 1: key1;
+//bit 16 range0 des key selection 0 : key0; 1: key1;
+//bit 6. range6 enable: 1: enable; 0 : disable.
+//bit 5. range5 enable: 1: enable; 0 : disable.
+//bit 4. range4 enable: 1: enable; 0 : disable.
+//bit 3. range3 enable: 1: enable; 0 : disable.
+//bit 2. range2 enable: 1: enable; 0 : disable.
+//bit 1. range1 enable: 1: enable; 0 : disable.
+//bit 0. range0 enable: 1: enable; 0 : disable.
+#define P_PSRAM_DES_PADDING ((volatile uint32_t *)0xfe007414)
+//bit 31 :0 Padding, with address together to generate describle 64 bits input.
+#define P_PSRAM_RANGE0_STA ((volatile uint32_t *)0xfe007440)
+//bit 22 :0.
+//AXI security range 0 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE0_EDA ((volatile uint32_t *)0xfe007444)
+//bit 22 :0.
+//AXI security range 0 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE0_CTRL0 ((volatile uint32_t *)0xfe007448)
+// AXI secruity range 0 control.
+#define P_PSRAM_RANGE0_CTRL1 ((volatile uint32_t *)0xfe00744c)
+// AXI secruity range 0 control.
+#define P_PSRAM_RANGE1_STA ((volatile uint32_t *)0xfe007450)
+//bit 22 :0.
+//AXI security range 1 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE1_EDA ((volatile uint32_t *)0xfe007454)
+//bit 22 :0.
+//AXI security range 1 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE1_CTRL0 ((volatile uint32_t *)0xfe007458)
+// AXI secruity range 1 control.
+#define P_PSRAM_RANGE1_CTRL1 ((volatile uint32_t *)0xfe00745c)
+// AXI secruity range 1 control.
+#define P_PSRAM_RANGE2_STA ((volatile uint32_t *)0xfe007460)
+//bit 31 : 6.
+//AXI security range 2 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE2_EDA ((volatile uint32_t *)0xfe007464)
+//bit 31 :6.
+//AXI security range 2 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE2_CTRL0 ((volatile uint32_t *)0xfe007468)
+#define P_PSRAM_RANGE2_CTRL1 ((volatile uint32_t *)0xfe00746c)
+#define P_PSRAM_RANGE3_STA ((volatile uint32_t *)0xfe007470)
+//bit 31 : 6.
+//AXI security range 3 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE3_EDA ((volatile uint32_t *)0xfe007474)
+//bit 31 :6.
+//AXI security range 3 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE3_CTRL0 ((volatile uint32_t *)0xfe007478)
+// AXI secruity range 3 control.
+#define P_PSRAM_RANGE3_CTRL1 ((volatile uint32_t *)0xfe00747c)
+// AXI secruity range 3 control.
+#define P_PSRAM_RANGE4_STA ((volatile uint32_t *)0xfe007480)
+//bit 31 :6.
+//AXI security range 4 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE4_EDA ((volatile uint32_t *)0xfe007484)
+//bit 31 :6.
+//AXI security range 4 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE4_CTRL0 ((volatile uint32_t *)0xfe007488)
+// AXI secruity range 4 control.
+#define P_PSRAM_RANGE4_CTRL1 ((volatile uint32_t *)0xfe00748c)
+#define P_PSRAM_RANGE5_STA ((volatile uint32_t *)0xfe007490)
+//bit 22 :0.
+//AXI security range 5 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE5_EDA ((volatile uint32_t *)0xfe007494)
+//bit 22 :0.
+//AXI security range 5 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE5_CTRL0 ((volatile uint32_t *)0xfe007498)
+// AXI secruity range 5 control.
+#define P_PSRAM_RANGE5_CTRL1 ((volatile uint32_t *)0xfe00749c)
+// AXI secruity range 5 control.
+#define P_PSRAM_RANGE6_STA ((volatile uint32_t *)0xfe0074a0)
+//bit 22 :0.
+//AXI security range 6 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE6_EDA ((volatile uint32_t *)0xfe0074a4)
+//bit 22 :0.
+//AXI security range 6 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE6_CTRL0 ((volatile uint32_t *)0xfe0074a8)
+// AXI secruity range 6 control.
+#define P_PSRAM_RANGE6_CTRL1 ((volatile uint32_t *)0xfe0074ac)
+// AXI secruity range 6 control.
+#define P_PSRAM_RANGE7_CTRL0 ((volatile uint32_t *)0xfe0074b0)
+#define P_PSRAM_RANGE7_CTRL1 ((volatile uint32_t *)0xfe0074b4)
+#define P_PSRAM_VIO_STATUS ((volatile uint32_t *)0xfe0074b8)
+//bit 31: security violation. write 1 to clean security violation status.
+//bit 30. 1 : AXI write violation. 0 : axi read violation.
+//bit 18:16. AXI ARPROT/AWPROT>
+//bit 11:0. AXI violation ID.
+#define P_PSRAM_VIO_ADDR ((volatile uint32_t *)0xfe0074bc)
+//read only
+//31:0 AXI violation address.
+#define P_PSRAM_USER_CTRL0 ((volatile uint32_t *)0xfe007600)
+//bit 31. user request enable. write 1 to enable. read 0, means user command accepted by the SPI_CTRL.
+//bit 30. usr request done. after user command done. this bit set to 1.
+//bit 29. USR COMMAND enable.
+//bit 28. command type0. 1 READ command. 0 write command.
+//bit 27. command type1. 1 for register. 0 : for memory.
+//bit 21~16. USR command clock cycles
+//bit 15~0. USR COMMAND CODE.
+#define P_PSRAM_USER_CTRL1 ((volatile uint32_t *)0xfe007604)
+//bit 31. USR_ADDR_EN
+//bit 30:29. USR_ADDR_DW
+//bit 28~20. USR address clock cycle number.
+//bit 19:16 USR data output/input switch postion
+//bit 15. USR DUMMY ENABLE
+//bit 13~8. USR DUMMY clock cycles.
+//bit 5:0 USR data DQS read enable postion.
+#define P_PSRAM_USER_CTRL2 ((volatile uint32_t *)0xfe007608)
+//bit 31 usr des key selection. 1 : key 1; 0 : key 0.
+//bit 30. usr check latency. for Winbond PSRAM data read/write, DQS input indentify the latency is doubled or not.
+//bit 29. usr data des enable.
+//bit 28 usr datain enable.
+//bit 27. usr datain destination. 1 : write to CFG_STS register. 0 : write to DATA REGISTERs.
+//bit 26~16 usr data in clock cycle number.
+//bit 15. usr datout enable.
+//bit 14. usr data out source 1 : from CFG_STS register. 0 from DATA register.
+//bit 13~11. not used.
+//bit 10~0. usr dataout clock cycles.
+#define P_PSRAM_USER_CTRL3 ((volatile uint32_t *)0xfe00760c)
+//bit 17:16. which cycle to ask phy to check read/write latency at PSRAM SEND COMMOND stage.
+//since PSRAM send command stage only 3 clock cycle. So this number only can chose 0, 1, 2.
+//bit 15:0. user dummy data when output in dummy cycle.
+#define P_PSRAM_USER_ADDR ((volatile uint32_t *)0xfe007610)
+//bit 31:0. 32bits user address.
+#define P_PSRAM_AXI_REQ_CTRL0 ((volatile uint32_t *)0xfe007614)
+//bit 31. AXI request enable.
+//bit 30 AXI cmd_en. command cycle enable.
+//bit 29:24. AXI request command cycle clock numbers.
+//bit 22. AXI request address cycle enable.
+//bit 21:16. AXI request address cycle clock number.
+//bit 15:14. AXI address cycle data width.
+//bit 13:12. at which clock cycle to send signal to phy to check latency flag for WINBOND PSRAM flexible latency.
+//since PSRAM send command stage only 3 clock cycle. So this number only can chose 0, 1, 2.
+//bit 6 // AXI Write dummy enable.
+//bit 5:0 // axi write dummy clock cycle number.
+#define P_PSRAM_AXI_REQ_CTRL1 ((volatile uint32_t *)0xfe007618)
+//bit 31:16. AXI request psram READ command code.
+//bit 15:0. AXI request psram write command code.
+#define P_PSRAM_AXI_REQ_CTRL2 ((volatile uint32_t *)0xfe00761c)
+//bit 31. AXI read request Dummy enable.
+//bit 30. Check latency enable for WINBOND PSRAM flexible latency.
+//bit 27:22. clock cycles in dummy stage to eanble PSRAM PHY reading logic.
+//bit 21:16. axi_read dummy clock cycles number.
+//bit 15:0. dummy data if output in dummy cycles.
+#define P_PSRAM_AXI_REQ_CTRL3 ((volatile uint32_t *)0xfe007620)
+//bit 31 des enable.
+//bit 26:16. DATA input clock cycles.
+//bit 10:0. DATA output clock cycles.
+#define P_PSRAM_ACTIMING0 ((volatile uint32_t *)0xfe007624)
+//bit 31:30. tSLCH
+//bit 29:28 tCLSH
+//bit 20:16 tSHWL
+//bit 15:12 tSHSL2
+//bit 11:8 tSHSL1
+//bit 7:0 tWHSL
+#define P_PSRAM_ACTIMING1 ((volatile uint32_t *)0xfe007628)
+//bit 7:0 tRWR for winbond PSRAM, = tRWR -3. Winbond PSRAM include one CS cycle and 2 command cycle.
+//for APMEMORY should be same value of tCPH
+#define P_PSRAM_ACTIMING2 ((volatile uint32_t *)0xfe00762c)
+#define P_PSRAM_WDG_CTRL ((volatile uint32_t *)0xfe007630)
+//bit [31] 1: force to reset PSRAM PCTL and PHY logic. 0: normal.
+//bit [30] 1: automatic reset PSRAM PCTL and PHY logic if watch dog triggered.
+//bit 12:0. watch dog timer. for Winbond PSRAM should be 1us for tRC. for APMEMORY should be 1us for tCEM.
+//SPI DATA BUFFER. There's a total 512KByte + 64byte(orgnized as 36x128bits) SRAM .
+// since each APB access is 32bits. So we use word address as APB read/write address.
+// But for SPI side we have to use 128bit boundary. That's the first Pragram/read SPI with data buffer must start at data buffer 128bit boundary. that means the PSRAM_USE_DBUF_ADDR last 2 bits must be 0.
+#define P_PSRAM_DBUF_0 ((volatile uint32_t *)0xfe007640)
+#define P_PSRAM_DBUF_1 ((volatile uint32_t *)0xfe007644)
+#define P_PSRAM_DBUF_2 ((volatile uint32_t *)0xfe007648)
+#define P_PSRAM_DBUF_3 ((volatile uint32_t *)0xfe00764c)
+#define P_PSRAM_DBUF_4 ((volatile uint32_t *)0xfe007650)
+#define P_PSRAM_DBUF_5 ((volatile uint32_t *)0xfe007654)
+#define P_PSRAM_DBUF_6 ((volatile uint32_t *)0xfe007658)
+#define P_PSRAM_DBUF_7 ((volatile uint32_t *)0xfe00765c)
+#define P_PSRAM_DBUF_8 ((volatile uint32_t *)0xfe007660)
+#define P_PSRAM_DBUF_9 ((volatile uint32_t *)0xfe007664)
+#define P_PSRAM_DBUF_A ((volatile uint32_t *)0xfe007668)
+#define P_PSRAM_DBUF_B ((volatile uint32_t *)0xfe00766c)
+#define P_PSRAM_DBUF_C ((volatile uint32_t *)0xfe007670)
+#define P_PSRAM_DBUF_D ((volatile uint32_t *)0xfe007674)
+#define P_PSRAM_DBUF_E ((volatile uint32_t *)0xfe007678)
+#define P_PSRAM_DBUF_F ((volatile uint32_t *)0xfe00767c)
+#define P_PSRAM_CFG_STS ((volatile uint32_t *)0xfe007680)
+//32bits register to save the USR read command read back values.
+#define P_PSRAM_STATUS ((volatile uint32_t *)0xfe007684)
+//bit 31. usr_req_done flag. 1 : user request done . write 1 to clean.
+//bit 30~11.
+//bit 10:8
+//bit 7:3.
+//bit 2. axi_data buffer idle bit. 1 : idle. 0 : working.
+//bit 1. axi interface idle bit. 1 : idle. 0 : working.
+//bit 0. psram ctrl idle bit. 1 : idle. 0 : working.
+#define P_PSRAM_CTRL ((volatile uint32_t *)0xfe007688)
+//bit 31. PSRAM in DTR mode.
+//bit 30. psram input data latch clock select. 1: from clock input pin. 0: from DQS
+//if use clock input pin as data input latch clock, bit 13:12 should select 01.
+//bit 29:27. PSRAM mode.
+//'b000 : STR SPI mode.
+//'b001 : STR QPI mode.
+//'b010 : DTR QPI mode.
+//'b011 : DTR OPI FLASH.
+//'b100 : APmemory PSRAM mode.
+//'b101 : Winbond PSRAM mode.
+//bit 26. enable to generation interruption after usr request done. 1: enable. 0: disable.
+//bit 25. to enable APMEMORY 2 command cycle mode. 1 : enable : 0: 3 command cycles.
+//bit 24. to enable the psram clock output always enable. 1 : enable. 0: disable.
+//bit 23. to enable the psram clock output extend mode to cover APMEMORY tCPI.
+//bit 22. to disable the CKN output. 1: disable PSRAM CK_N pin output. 0: CK_N working normal.
+//bit 21. PSRAM DATA IN/OUT high 8bit and low 8 bit endian. 1 : rising edge is low byte. falling edge data is high byte. 0 : rising edge is high byte. falling edge data is low byte.
+//bit 20. PSRAM ADDRESS unit. 1: Byte. 0 : word.
+// APMEMORY used byte address. Winbond use word address.
+//bit 19. DQSEN generation. if use dqs to latch input data, this bit should be set to 1 to ask DMC generate ENABLE singal in dummy stage. 0: not generate DQS_EN.
+//bit 18. PSRAM RESET I/O oe_n value. if need RESET pin.
+//bit 17. PSRAM RESET I/O output vale. if need reset pin.
+//bit 16. force CS output low. for APMEMORY exit DPPD mode. 1: to force cs output low : 0 output normal working mode.
+//bit 13:12. psram data in clock enable selection. 00: use DQSEN. 01: use clkin cnt.
+//bit 11. DM Disable. 1: disable DM output. 0: with dmoutput.
+//bit 9. psram pctl auto clock gating enable. 1: enable. 0 : disable.
+//bit 8. psram pctl clock disable. 1: disable. 0 : enable.
+//bit 2 PSRAM SPI mode, DQ2 works as WP(write protection mode).
+//bit 1. DQ2 WP mode value.
+//bit 0. PSRAM SPI mode, DQ3 works as HOLD function.
+#define P_PSRAM_PIN_CTRL ((volatile uint32_t *)0xfe00768c)
+//bit 30:28 DATA 6 DQ pin selection.
+//bit 27:24 DATA 6 DQ pin selection.
+//bit 22:20 DATA 5 DQ pin selection.
+//bit 18:16 DATA 4 DQ pin selection.
+//bit 14:12 DATA 3 DQ pin selection.
+//bit 10:8 DATA 2 DQ pin selection.
+//bit 6:4 DATA 1 DQ pin selection.
+//bit 2:0 DATA 0 DQ pin selection.
+//0 : from DQ[0]
+//1 : from DQ[1]
+//2 : from DQ[2]
+//3 : from DQ[3]
+//4 : from DQ[4]
+//5 : from DQ[5]
+//6 : from DQ[6]
+//7 : from DQ[7]
+//psram_dly_16 is used for all DQ[0~] in/out/oen delay adjustment.
+//psram_dly_16 consists of 15 delay cells, one delay cell is 50ps delay( typical corner).
+//psram_dly_16 is control by delay_sel[3:0]. 0 = no delay. 1~15 controls how many delay cells used.
+//psram_dly_16 can be controlled by each control register either with real delay mode or VT updated with 4xclock period.
+//psram_lcdl is used for DQS/DQSN input and CK/CKN output delay 90degree delay generation and/or delay fine tune.
+//psram_lcdl consits of 96 delay cells, same delay cell used in psram_dly_16.
+//psram_lcdl should be calibrated with the psram_4xclock. and tracked with psram_4xclock with VT updated.
+#define P_PSRAM_DQ0_DIN_DLY ((volatile uint32_t *)0xfe007700)
+//bit 6:0. DQ0 DIN delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ1_DIN_DLY ((volatile uint32_t *)0xfe007704)
+//bit 6:0. DQ1 input delay control. in DLY16 read mode, only [3:0] is valid.
+#define P_PSRAM_DQ2_DIN_DLY ((volatile uint32_t *)0xfe007708)
+//bit 6:0. DQ2 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ3_DIN_DLY ((volatile uint32_t *)0xfe00770c)
+//bit 6:0. DQ3 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ4_DIN_DLY ((volatile uint32_t *)0xfe007710)
+//bit 6:0. DQ4 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ5_DIN_DLY ((volatile uint32_t *)0xfe007714)
+//bit 6:0. DQ5 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ6_DIN_DLY ((volatile uint32_t *)0xfe007718)
+//bit 6:0. DQ6 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ7_DIN_DLY ((volatile uint32_t *)0xfe00771c)
+//bit 6:0. DQ7 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ0_DOUT_DLY ((volatile uint32_t *)0xfe007720)
+//bit 6:0. DQ0 DOUT delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ1_DOUT_DLY ((volatile uint32_t *)0xfe007724)
+//bit 6:0. DQ1 output delay control. in DLY16 read mode, only [3:0] is valid.
+#define P_PSRAM_DQ2_DOUT_DLY ((volatile uint32_t *)0xfe007728)
+//bit 6:0. DQ2 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ3_DOUT_DLY ((volatile uint32_t *)0xfe00772c)
+//bit 6:0. DQ3 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ4_DOUT_DLY ((volatile uint32_t *)0xfe007730)
+//bit 6:0. DQ4 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ5_DOUT_DLY ((volatile uint32_t *)0xfe007734)
+//bit 6:0. DQ5 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ6_DOUT_DLY ((volatile uint32_t *)0xfe007738)
+//bit 6:0. DQ6 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ7_DOUT_DLY ((volatile uint32_t *)0xfe00773c)
+//bit 6:0. DQ7 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ0_OEN_DLY ((volatile uint32_t *)0xfe007740)
+//bit 6:0. DQ0 OEN delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ1_OEN_DLY ((volatile uint32_t *)0xfe007744)
+//bit 6:0. DQ1 output enable delay control. in DLY16 read mode, only [3:0] is valid.
+#define P_PSRAM_DQ2_OEN_DLY ((volatile uint32_t *)0xfe007748)
+//bit 6:0. DQ2 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ3_OEN_DLY ((volatile uint32_t *)0xfe00774c)
+//bit 6:0. DQ3 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ4_OEN_DLY ((volatile uint32_t *)0xfe007750)
+//bit 6:0. DQ4 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ5_OEN_DLY ((volatile uint32_t *)0xfe007754)
+//bit 6:0. DQ5 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ6_OEN_DLY ((volatile uint32_t *)0xfe007758)
+//bit 6:0. DQ6 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ7_OEN_DLY ((volatile uint32_t *)0xfe00775c)
+//bit 6:0. DQ7 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DM_DOUT_DLY ((volatile uint32_t *)0xfe007760)
+//bit 6:0. DM output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DM_OEN_DLY ((volatile uint32_t *)0xfe007764)
+//bit 6:0. DM output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_CS_DOUT_DLY ((volatile uint32_t *)0xfe007768)
+//bit 6:0. CS output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQS_DIN_DLY ((volatile uint32_t *)0xfe00776c)
+//bit 6:0. DQS input delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define P_PSRAM_DQSN_DIN_DLY ((volatile uint32_t *)0xfe007770)
+//bit 6:0. DQSN input delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define P_PSRAM_CKN_DOUT_DLY ((volatile uint32_t *)0xfe007774)
+//bit 6:0. CKN output delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define P_PSRAM_CK_DOUT_DLY ((volatile uint32_t *)0xfe007778)
+//bit 6:0. CK output delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define P_PSRAM_RDEN_DLY ((volatile uint32_t *)0xfe00777c)
+//bit 10:7. READ enable phase delay. unit = 1UI. for AP QPI PSRAM. PSRAM only send one cycle DQS preamble.
+// We have to used this UI delay to compensate the whole clock output delay and the DQS input delay.
+// if run high frequency, this delay need to be trained. the valid value from 0 ~ 12. Since one UI is 1/4 of PSRAM clock,
+// the total delay of the clock output delay + input delay should be less than 3 PSRAM clock.
+//bit 6:0. READ enable fine tune delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define P_PSRAM_LCDL_CTRL ((volatile uint32_t *)0xfe0077c0)
+//bit 31. write 1 to update all delay cell delays control.
+//bit 30. write 1 to calibration LCDL.
+//bit 29. LCDL track enable. 1: enable LCDL auto track VT changes.
+//bit 28. LCDL delay control mode.
+//1 : real delay mode. For DQS/DQSN/CKN/CK/RDEN delay control register, one number means one delay cells.
+//0 : UI MODE. For DQS/DQSN/CKN/CK/RDEN delay control register, one number means 1/64 psram_4xclk period.
+//bit 27. DLY16 ( psram_dly_16 cell) delay control mode.
+//1 : real delay mode. For all data delay control register, one number means one delay cells.
+//0 : UI MODE. For all data delay control register, one number means 1/64 psram_4xclk period.
+//bit 27:24. not used.
+//bit 23:0. timer do trigger LCDL track the VT once. each track will compensate the UI with 1/16 delay cell delay.
+//LCDL calibration ctroller.
+#define P_PSRAM_LCDL_CAL_CTRL1 ((volatile uint32_t *)0xfe0077c4)
+//27:24. which LCDL delay line used to run calibration.
+//19:16. LCDL calibration loop end position.
+//15:12. LCDL calibration loop initial position.
+//10:0. LCDL calibration initial phase counter.
+#define P_PSRAM_LCDL_CAL_CTRL2 ((volatile uint32_t *)0xfe0077c8)
+//26:16 LCDL phase lock limit. if the lcdl phase counter difference between 2 calibration loops is less than this number, The LCDL would be locked and stop the calibration.
+//10:0. deta_init. the first loop phase changing number.
+#define P_PSRAM_LCDL_CAL_CTRL3 ((volatile uint32_t *)0xfe0077cc)
+//29:25 to configure LCDL calibration step 5 position.
+//24:20 to configure LCDL calibration step 4 position.
+//19:15 to configure LCDL calibration step 3 position.
+//14:10 to configure LCDL calibration step 2 position.
+//9:5 to configure LCDL calibration step 1 position.
+//4:0 to configure LCDL calibration step 0 position.
+#define P_PSRAM_LCDL_CAL_CTRL4 ((volatile uint32_t *)0xfe0077d0)
+//19:15 to configure LCDL calibration step 9 position.
+//14:10 to configure LCDL calibration step 8 position.
+//9:5 to configure LCDL calibration step 7 position.
+//4:0 to configure LCDL calibration step 6 position.
+#define P_PSRAM_CLK_UI ((volatile uint32_t *)0xfe0077d4)
+//bit 6:0. 4xCLOCK period delay measured from LCDL calibration.
+#define P_PSRAM_LCDL_PH ((volatile uint32_t *)0xfe0077d8)
+//10:0 LCDL phase counter after calibration.
+#define P_PSRAM_LCDL_STATUS ((volatile uint32_t *)0xfe0077dc)
+//bit 31. LCDL lock status. 1: LCDL locked to 4x clock.
+//`endif
+//
+// Closing file: ../psram/rtl/psram_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_sec.vh
+//
+//`ifdef DMC_SEC_REG_DEFINE
+//`else
+//`define DMC_SEC_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd021000
+// -----------------------------------------------
+//`define DMC_SEC_REG_BASE 32'hfd021000
+// ID assignment inside DMC..
+// id[12 :0] total 13 bit ID.
+// id[12] == 1: for DMC internal TEST module.
+// id[12] == 0: for AXI port input.
+// id[11:0] == AXI port ID.
+// id[2:0] == 0 : A55 CPU.
+// id[2:0] == 1 : DSPA
+// id[2:0] == 2 : DSPB
+// id[2:0] == 3 : Not used.
+// id[2:0] == 4 : for Device.
+//Device sublevel ID.
+//id[9:7] == 5 : for audio. id[3] == 0: audio
+//id[9:7] == 6 : for DMA. id[6:4] for DMA thread id. id[3] for DMC security level.
+//id[9:7] == others: for device other masters.
+// id[2:0] == 5 : for USB device.
+// id[2:0] == 6 : for I2C debug input.
+// id[2:0] == 7 : for USB host.
+#define P_DMC_SEC_RANGE0_STA ((volatile uint32_t *)0xfd021000)
+//bit 31:12. range0 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE0_EDA ((volatile uint32_t *)0xfd021004)
+//bit 31:12. range0 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE0_RID_CTRL ((volatile uint32_t *)0xfd021008)
+//range 0 read access enable based on DMC ID assignments.
+//bit 28. for AXI port 3. Not used in A1. should be 0.
+//bit 27. for dmc_test. 1 = enable. 0 = disable.
+//bit 26. for usbhost. 1 = enable. 0 = disable.
+//bit 25. for i2c. 1 = enable. 0 = disable.
+//bit 24. for usbdevide. 1 = enable. 0 = disable.
+//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+//bit 22:18.for AXI device sub level id 5 ~ 0.
+//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0).
+//bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0).
+//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define P_DMC_SEC_RANGE0_WID_CTRL ((volatile uint32_t *)0xfd02100c)
+//range 0 write access enable based on DMC ID assignments.
+//bit 28. for AXI port 3. Not used in A1. should be 0.
+//bit 27. for dmc_test. 1 = enable. 0 = disable.
+//bit 26. for usbhost. 1 = enable. 0 = disable.
+//bit 25. for i2c. 1 = enable. 0 = disable.
+//bit 24. for usbdevide. 1 = enable. 0 = disable.
+//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+//bit 22:18.for AXI device sub level id 5 ~ 0.
+//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0).
+//bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5).
+//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define P_DMC_SEC_RANGE1_STA ((volatile uint32_t *)0xfd021010)
+//bit 31:12. range1 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE1_EDA ((volatile uint32_t *)0xfd021014)
+//bit 31:12. range0 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE1_RID_CTRL ((volatile uint32_t *)0xfd021018)
+//range 1 read access enable based on DMC ID assignments.
+//bit 28. for AXI port 3. Not used in A1. should be 0.
+//bit 27. for dmc_test. 1 = enable. 0 = disable.
+//bit 26. for usbhost. 1 = enable. 0 = disable.
+//bit 25. for i2c. 1 = enable. 0 = disable.
+//bit 24. for usbdevide. 1 = enable. 0 = disable.
+//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+//bit 22:18.for AXI device sub level id 5 ~ 0.
+//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0).
+//bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0).
+//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define P_DMC_SEC_RANGE1_WID_CTRL ((volatile uint32_t *)0xfd02101c)
+//range 1 write access enable based on DMC ID assignments.
+//bit 28. for AXI port 3. Not used in A1. should be 0.
+//bit 27. for dmc_test. 1 = enable. 0 = disable.
+//bit 26. for usbhost. 1 = enable. 0 = disable.
+//bit 25. for i2c. 1 = enable. 0 = disable.
+//bit 24. for usbdevide. 1 = enable. 0 = disable.
+//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+//bit 22:18.for AXI device sub level id 5 ~ 0.
+//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0).
+//bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5).
+//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define P_DMC_SEC_RANGE2_STA ((volatile uint32_t *)0xfd021020)
+//bit 31:12. range2 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE2_EDA ((volatile uint32_t *)0xfd021024)
+//bit 31:12. range2 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE2_RID_CTRL ((volatile uint32_t *)0xfd021028)
+//range 2 read access enable based on DMC ID assignments.
+//bit 28. for AXI port 3. Not used in A1. should be 0.
+//bit 27. for dmc_test. 1 = enable. 0 = disable.
+//bit 26. for usbhost. 1 = enable. 0 = disable.
+//bit 25. for i2c. 1 = enable. 0 = disable.
+//bit 24. for usbdevide. 1 = enable. 0 = disable.
+//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+//bit 22:18.for AXI device sub level id 5 ~ 0.
+//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0).
+//bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0).
+//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define P_DMC_SEC_RANGE2_WID_CTRL ((volatile uint32_t *)0xfd02102c)
+//range 2 write access enable based on DMC ID assignments.
+//bit 28. for AXI port 3. Not used in A1. should be 0.
+//bit 27. for dmc_test. 1 = enable. 0 = disable.
+//bit 26. for usbhost. 1 = enable. 0 = disable.
+//bit 25. for i2c. 1 = enable. 0 = disable.
+//bit 24. for usbdevide. 1 = enable. 0 = disable.
+//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+//bit 22:18.for AXI device sub level id 5 ~ 0.
+//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0).
+//bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5).
+//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define P_DMC_SEC_RANGE3_STA ((volatile uint32_t *)0xfd021030)
+//bit 31:12. range3 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE3_EDA ((volatile uint32_t *)0xfd021034)
+//bit 31:12. range3 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE3_RID_CTRL ((volatile uint32_t *)0xfd021038)
+//range 3 read access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE3_WID_CTRL ((volatile uint32_t *)0xfd02103c)
+//range 3 write access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE4_STA ((volatile uint32_t *)0xfd021040)
+//bit 31:12. range4 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE4_EDA ((volatile uint32_t *)0xfd021044)
+//bit 31:12. range4 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE4_RID_CTRL ((volatile uint32_t *)0xfd021048)
+//range 4 read access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE4_WID_CTRL ((volatile uint32_t *)0xfd02104c)
+//range 4 write access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE5_STA ((volatile uint32_t *)0xfd021050)
+//bit 31:12. range5 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE5_EDA ((volatile uint32_t *)0xfd021054)
+//bit 31:12. range5 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE5_RID_CTRL ((volatile uint32_t *)0xfd021058)
+//range 5 read access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE5_WID_CTRL ((volatile uint32_t *)0xfd02105c)
+//range 5 write access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE6_STA ((volatile uint32_t *)0xfd021060)
+//bit 31:12. range5 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE6_EDA ((volatile uint32_t *)0xfd021064)
+//bit 31:12. range6 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE6_RID_CTRL ((volatile uint32_t *)0xfd021068)
+//range 6 read access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE6_WID_CTRL ((volatile uint32_t *)0xfd02106c)
+//range 6 write access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+//range 7 is default range if the access not hit any of the previous 7 range, if would hit range 7.
+#define P_DMC_SEC_RANGE7_RID_CTRL ((volatile uint32_t *)0xfd021070)
+//range 7 read access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE7_WID_CTRL ((volatile uint32_t *)0xfd021074)
+//range 7 write access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE_CTRL ((volatile uint32_t *)0xfd021078)
+//bit 23:16 8 range security level. to chosse with DES KEY to use data describle.
+//bit 7:0 8 range enable. each bit for one range to indentify the range is enabled or not.
+//registers to check the security protection and watch point error information.
+#define P_DMC_DES_CTRL ((volatile uint32_t *)0xfd021080)
+//bit 1 data describle enable.
+//bit 0 wirte 1 to block DES CTRL and DES PADDING read/write.
+#define P_DMC_DES_PADDING ((volatile uint32_t *)0xfd021084)
+#define P_DMC_SEC_STATUS ((volatile uint32_t *)0xfd0212e0)
+//bit 31~2. not used.
+//bit 1 write security violation.
+//bit 0. read security violation.
+#define P_DMC_VIO_ADDR0 ((volatile uint32_t *)0xfd0212e4)
+//ddr0 write secure violation address.
+#define P_DMC_VIO_ADDR1 ((volatile uint32_t *)0xfd0212e8)
+//bit 31:18 . not used. always 0.
+//17 ddr0 secure check violation.
+//16 ddr0 write address overflow. write out of DDR size.
+//15:13. ddr0 write violation AWPROT bits.
+//12:0 ddr0_write violation ID. Please check ID assignment for ID bit defines.
+#define P_DMC_VIO_ADDR2 ((volatile uint32_t *)0xfd0212ec)
+//ddr0 write secure violation address.
+#define P_DMC_VIO_ADDR3 ((volatile uint32_t *)0xfd0212f0)
+//bit 31:18 . not used. always 0.
+//17 ddr0 secure check violation.
+//16 ddr0 read address overflow. write out of DDR size.
+//15:13. ddr0 read violation AWPROT bits.
+//12:0 ddr0_read violation ID. please ID assignment for ID bit defines.
+//DDR0_ADDRMAP is used for RANK0 bank, row, col address mapping from AXI 32bits linear address.
+#define P_DDR0_ADDRMAP_0 ((volatile uint32_t *)0xfd021340)
+//29:25 ca8.
+//24:20 ca7.
+//19:15 ca6.
+//14:10 ca5.
+//9:5 ca4.
+//4:0 ca3.
+#define P_DDR0_ADDRMAP_1 ((volatile uint32_t *)0xfd021344)
+//29:25 ra2.
+//24:20 ra1.
+//19:15 ra0.
+//14:10 ca11.
+//9:5 ca10.
+//4:0 ca9.
+#define P_DDR0_ADDRMAP_2 ((volatile uint32_t *)0xfd021348)
+//29:25 ra8.
+//24:20 ra7.
+//19:15 ra6.
+//14:10 ra5.
+//9:5 ra4.
+//4:0 ra3.
+#define P_DDR0_ADDRMAP_3 ((volatile uint32_t *)0xfd02134c)
+//29:25 ra14.
+//24:20 ra13.
+//19:15 ra12.
+//14:10 ra11.
+//9:5 ra10.
+//4:0 ra9.
+#define P_DDR0_ADDRMAP_4 ((volatile uint32_t *)0xfd021350)
+//29:25 ra16 for DDR4 SDRAM
+//24:20 bg1 for DDR4 SDRAM.
+//19:15 ba2. or bg0 for DDR4.
+//14:10 ba1.
+//9:5 ba0.
+//4:0 ra15.
+#define P_DMC_DDR_CTRL ((volatile uint32_t *)0xfd021368)
+// DDR PHY and DMC only supports 16bits and rank0 only.
+//bit 24:22 3'b000 : ddr3 mode.
+//3'b001 : ddr4 mode.
+//3'b010 : lpddr3 mode.
+//3'b011 : lpddr4 mode.
+//bit 20 DDR4 BG1 enable bit.
+//bit 3:0 : DDR rank 0 size bit [2:0].
+//4'b0000 : DDR rank 0 is 128Mbyte.
+//4'b0001 : DDR rank 0 is 256Mbyte.
+//4'b0010 : DDR rank 0 is 512Mbyte.
+//4'b0011 : DDR rank 0 is 1Gbyte.
+//4'b0100 : DDR rank 0 is 2Gbyte.
+//4'b0101 : DDR rank 0 is 4Gbyte.
+//4'b1000 : DDR rank 0 is 4Gbyte.
+//4'b1001 : DDR rank 0 is 4Gbyte.
+//others : reserved.
+#define P_DMC_APB_SEC_CTRL ((volatile uint32_t *)0xfd02136c)
+//bit 19:16. DMC normal APB register secure control.
+//bit 19: 1: all can write those register. 0: the APB_PROT[0] must match the bit 16 to access those regsiter.
+//Bit15:12. DMC sticky APB regsiter secure control.
+//bit 15. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 12 to access those register.
+//bit 11:8. not used.
+//Bit 7:4. DMC DDR SDRAM protocal contorl register contorl
+//bit 11. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 4 to access those register.
+//bit 3:0. PHY APB regsiter secure control.
+//bit 3. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 0 to access those register.
+#define P_DMC_DDR_PHY_CTRL ((volatile uint32_t *)0xfd0212fc)
+//bit 4 PwrOkIn
+//bit 3. PHY APB soft reset_n
+//bit 2. PHY soft reset_n
+//bit 1. PHY DfiClk enable.
+//bit 0. PHY DfiCtlClk enable.
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd021400
+// -----------------------------------------------
+//`define DMC_TEST_REG_BASE 32'hfd021400
+#define P_DMC_TEST_WRCMD_ADDR ((volatile uint32_t *)0xfd021770)
+// the current write cmd address.
+#define P_DMC_TEST_RDRSP_ADDR ((volatile uint32_t *)0xfd021774)
+// the failed read response address(for error data )
+#define P_DMC_TEST_RDCMD_ADDR ((volatile uint32_t *)0xfd021778)
+// the current read command address.
+#define P_DMC_TEST_WDG ((volatile uint32_t *)0xfd02177c)
+//31:16. write response watch dog.
+//15:0. read response watch dog.
+#define P_DMC_TEST_STA ((volatile uint32_t *)0xfd021780)
+//test start address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary.
+// for sha mode, address must be in 64 bytes boundary. that mean the last 6 bits must be 0.
+#define P_DMC_TEST_EDA ((volatile uint32_t *)0xfd021784)
+//test end address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary.
+// for sha mode, address must be in 64 bytes boundary. that mean the last 6bits must be 1.
+#define P_DMC_TEST_CTRL ((volatile uint32_t *)0xfd021788)
+//bit 31. enable test.
+//bit 30. when enable test, enable the write to DDR function.
+//bit 29. when enable test, enable the read from DDR function.
+//bit 28. Not used.
+//bit 27. enabe to compare data. when do the read enable to enable the error comparaion. suppose the read data should be same as the data in the write buffer.
+//bit 26. Not used.
+//bit 25. address generation type. 0: continuous increase the address in the range of test start address and test end address.
+// 1: test module would pick the random address from test start address and test end address.
+//bit 24. done type. 0 : use the DMC_TEST_NUM register as the counter of test numbers.
+// for write if the write command number == the DMC_TEST_NUM, the write is done.
+// for read if the read command number == the DMC TEST_num, the read id done. for one read command can be repeated repeat number times.
+// 1 : finshed at end address.
+//bit 23. wdata type. 1 : the first write is {WD3, WD2,WD1,WD0}, then the latter is the previous data plus a pattern.( { + WD7, + WD6, + WD5, + WD4}).
+// 0 : the WDATA is the data in write register.
+//bit 23. Not used.
+//bit 22:20. read repeat times. for non-sha function, we can define multi times of the read. the test module would repeat the same adddress repeat times.
+//bit 19. limit write. 0: no outstanding write request limitation.
+// 1: limit the outstanding write commands to the number of bits [15:8]
+//bit 18. limit read. 0. no outstanding read request limitation.
+// 1. limit the read outstanding request to the number of bits[7:0].
+//bit 17:16. Not used.
+//bit 15:8. write outstanding commands limit.
+//bit 7:0. read outstanding commands limit.
+#define P_DMC_TEST_NUM ((volatile uint32_t *)0xfd02178c)
+// how many test command for the test if the DMC_TEST_CTRL bit 24 is 0.
+#define P_DMC_TEST_WD0 ((volatile uint32_t *)0xfd021790)
+// write data 0 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD1 ((volatile uint32_t *)0xfd021794)
+// write data 1 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD2 ((volatile uint32_t *)0xfd021798)
+// write data 2 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD3 ((volatile uint32_t *)0xfd02179c)
+// write data 3 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD4 ((volatile uint32_t *)0xfd0217a0)
+// write data 4 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD5 ((volatile uint32_t *)0xfd0217a4)
+// write data 5 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD6 ((volatile uint32_t *)0xfd0217a8)
+// write data 6 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD7 ((volatile uint32_t *)0xfd0217ac)
+// write data 7 for write command. also for read back data comparision.
+#define P_DMC_TEST_RD0 ((volatile uint32_t *)0xfd0217b0)
+// the read back data 0. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD1 ((volatile uint32_t *)0xfd0217b4)
+// the read back data 1. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD2 ((volatile uint32_t *)0xfd0217b8)
+// the read back data 2. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD3 ((volatile uint32_t *)0xfd0217bc)
+// the read back data 3. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD4 ((volatile uint32_t *)0xfd0217c0)
+// the read back data 4. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD5 ((volatile uint32_t *)0xfd0217c4)
+// the read back data 5. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD6 ((volatile uint32_t *)0xfd0217c8)
+// the read back data 6. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD7 ((volatile uint32_t *)0xfd0217cc)
+// the read back data 7. if error happens, it would capture the first error data.
+#define P_DMC_TEST_ERR_ADDR ((volatile uint32_t *)0xfd0217d0)
+// it capature the first error address.
+#define P_DMC_TEST_ERR_CNT ((volatile uint32_t *)0xfd0217d4)
+// how many data error happens in the whole test period.
+#define P_DMC_TEST_STS ((volatile uint32_t *)0xfd0217d8)
+//bit 31, test done bit. write 1 to clean.
+//bit 30, indicate address err
+//bit 29~7. not used.
+//bit 6. read data resp error(caused by security or rd latency).
+//bit 5. test MRR/MPR rd latency error. write 1 clear
+//bit 4, sha done. write 1 to clean.
+//bit 3, write done. write 1 to clean.
+//bit 2, read done. write 1 to clean
+//bit 1, write watchdog triggered. write 1 to clean
+//bit 0, read watchdog triggered. write 1 to clean.
+#define P_DMC_TEST_COMP_MASK ((volatile uint32_t *)0xfd0214cc)
+//32bits for DMC TEST COMPARE bit enable.
+//1 : to MASK this bit. 0: compare this bit.
+#define P_DMC_TEST_RDBI0 ((volatile uint32_t *)0xfd0214d0)
+//MPC RD FIFO command DBI read back data
+//bit 31:16 the second cycle.
+//bit 15:0 the first cycle.
+#define P_DMC_TEST_RDBI1 ((volatile uint32_t *)0xfd0214d4)
+//MPC RD FIFO command DBI read back data
+//bit 31:16. the Forth cycle.
+//bit 15:0. the third cycle.
+#define P_DMC_TEST_WSTRB0 ((volatile uint32_t *)0xfd0214d8)
+//MPC WR FIFO command DM bit write data
+//bit 31:16 the second cycle.
+//bit 15:0 the first cycle.
+#define P_DMC_TEST_DRAM_CMD ((volatile uint32_t *)0xfd0214e0)
+//bit 31. cmd done. write 0 to clean.
+//bit 30. data done. write 0 to clean.
+//bit 4:0. only one bit can be 1. read data stored in DMC_TEST_RD* write data from DMC_TEST_W
+//bit 4. LPDDR4 MPC write data command( MPC WR FIFO). Not support LPDDR4 in A1.
+//bit 3. LPDDR4 MPC read data command (MPC RD Calibration and RD FIFO).Not support LPDDR4 in A1.
+//bit 2. LPDDR4 MPC-1 command ( NOP, Start DQS interval ....)Not support LPDDR4 in A1.
+//bit 1. mrr comand.
+//bit 0. mrw command.
+#define P_DMC_TEST_DRAM_CMD_CODE ((volatile uint32_t *)0xfd0214e4)
+//bit 27:26. 128bits data cycles . 0: 1 clock cycles; 1: 2 clock cycles; 2: 3 clock cycles; 3:4 clock cycles.
+// LPDDR4 32bits: 4 clock cycles; LPDDR4 16bits: 2 clock cycles;
+// DDR3/4/LPDDR3 32 bits : 2 clock cycles. DDR3/4 16bits: 1 cycles.
+//bit 25 MRW/MRR/MPC command rank 1 select. 1: select. 0: not select. In A1, only rank0 supported.
+//bit 24. MRW/MRR/MPC command rank 0 select. 1: select. 0: not select.In A1, only rank0 supported.
+//bit 23:16 MR addr. DDR4 case : 18:16 ba[2:0]. 20:19 BG[1:0].
+//bit 15:0 opcode.
+#define P_DMC_TEST_DRAM_CMD_TIME ((volatile uint32_t *)0xfd0214e8)
+//bit 31:16 PRE CMD timer. //delay how many cycle to start the command.
+//bit 15:0 POST CMD timer //delay how many cycle after the command execute.
+//`endif
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_sec.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_reg.vh
+//
+//`ifdef DMC_REG_DEFINE
+//`else
+//`define DMC_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd020000
+// -----------------------------------------------
+//`define DMC_REG_BASE 32'hfd020000
+#define P_DMC_SOFT_RST2 ((volatile uint32_t *)0xfd02000c)
+//bit 31~11. reserved for future.
+//bit 10 DMC DFI cmd soft reset_n
+//bit 9 DMC DFI MISC soft reset_n
+//bit 8 DMC DFI data soft reset_n
+//bit 7 DMC DFI dcu soft reset_n
+//bit 6 DMC siu soft reset_n
+//bit 5. DMC test soft reset_n. 0 : reset. 1 : normal working mode.
+//bit 4. DMC low power control moudle soft reset_n. 0 : reset. 1 : normal working mode.
+//bit 3. DMC QOS monitor module soft reset_n. 0 : reset. 1 : normal working mode.
+//bit 2. DMC register modle soft reset_n. 0 : reset. 1 : normal working mode.
+//bit 1. DMC canvas transfer module soft reset_n. 0 : reset. 1 : normal working mode.
+//bit 0. DMC command buffers and command generation modules soft reset. 0 = reset. 1:
+#define P_DMC_VERSION ((volatile uint32_t *)0xfd020014)
+//read only 32'h000b0000. for A1
+#define P_DMC_MON_CTRL0 ((volatile uint32_t *)0xfd020080)
+//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
+//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
+//bit 1. qos monitor 1 enable.
+//bit 0. qos monitor 0 enable.
+#define P_DMC_MON_CTRL1 ((volatile uint32_t *)0xfd020084)
+//bit 8:0. qos monitor 0 channel select.
+//bit 8 to select DMC TEST
+//bit 7:0 each bit enable one AXI subID.
+#define P_DMC_MON_CTRL2 ((volatile uint32_t *)0xfd020088)
+//bit 8. to enabe monitor 0 second level subID selection for example device.
+//bit 7:0 each bit to enable one second level subID inside device.
+#define P_DMC_MON_CTRL3 ((volatile uint32_t *)0xfd02008c)
+//bit 8:0. qos monitor 1 channel select.
+//bit 8 to select DMC TEST
+//bit 7:0 each bit enable one AXI subID.
+#define P_DMC_MON_CTRL4 ((volatile uint32_t *)0xfd020090)
+//bit 8. to enabe monitor 1 second level subID selection for example device.
+//bit 7:0 each bit to enable one second level subID inside device.
+#define P_DMC_MON_ALL_REQ_CNT ((volatile uint32_t *)0xfd0200a4)
+// at the test period, the whole MMC request time.
+#define P_DMC_MON_ALL_GRANT_CNT ((volatile uint32_t *)0xfd0200a8)
+// at the test period, the whole MMC granted data cycles. 64bits unit.
+#define P_DMC_MON_ONE_GRANT_CNT ((volatile uint32_t *)0xfd0200ac)
+// at the test period, the granted data cycles for the selected channel and ports.
+#define P_DMC_MON_SEC_GRANT_CNT ((volatile uint32_t *)0xfd0200b0)
+// at the test period, the granted data cycles for the selected channel and ports.
+#define P_DMC_MON_TIMER ((volatile uint32_t *)0xfd0200bc)
+// timer for the monitor period.
+#define P_DMC_CLKG_CTRL2 ((volatile uint32_t *)0xfd0200c8)
+//bit 10 enable auto clock gating for dfi command generation
+//bit 9 enable auto clock gating for dram cntroller
+//bit 8 enable auto clock gating for dfi data path.
+//bit 7. enalbe auto clock gating for write rsp generation.
+//bit 6. enalbe auto clock gating for read rsp generation.
+//bit 5. enalbe auto clock gating for ddr0 command filter.
+//bit 4. enalbe auto clock gating for ddr0 write reorder buffer.
+//bit 3. enalbe auto clock gating for ddr0 write data buffer.
+//bit 2. enalbe auto clock gating for ddr0 read reorder buffer.
+//bit 1. reserved
+//bit 0. reserved
+#define P_DMC_CLKG_CTRL3 ((volatile uint32_t *)0xfd0200cc)
+//bit 10 force to disable the clock of dfi command generation
+//bit 9 force to disable the clock of dram cntroller
+//bit 8 force to disable the clock of dfi data path.
+//bit 7. force to disalbe the clock of write rsp generation.
+//bit 6. force to disalbe the clock of read rsp generation.
+//bit 5. force to disalbe the clock of command filter.
+//bit 4. force to disalbe the clock of write reorder buffer.
+//bit 3. force to disalbe the clock of write data buffer.
+//bit 2. force to disalbe the clock of read reorder buffer.
+//bit 1. reserved.
+//bit 0. reserved.
+#define P_DMC_CHAN_STS ((volatile uint32_t *)0xfd0200d8)
+//bit 4 always 1
+//bit 3 ddr0 write data buffer idle. 1 : idle 0: busy.
+//bit 2 always 1.
+//bit 1 ddr0 wbuf idle. 1 : idle 0: busy.
+//bit 0. axi0 channel idle. 1 : idle 0: busy.
+#define P_DMC_CMD_FILTER_CTRL3 ((volatile uint32_t *)0xfd020108)
+//bit 31. force wbuf empty.
+//bit 30:26 wbuf high level number
+//bit 25:21 wbuf mid level number
+//bit 20:16 wbuf low level number
+//bit 14:10 rbuf high level number
+//bit 9:5 rbuf middle level number
+//bit 4:0 rbuf low level number
+#define P_DMC_CMD_FILTER_CTRL4 ((volatile uint32_t *)0xfd02010c)
+//bit 29:25. tITW.long
+//bit 24:20. tITW. short
+//bit 19:12 tAP auto precharge the bank not used if idle that long time.
+//bit 11:6 write to read accesses if there write hit request.
+//bit 5:0 read to write accesses if there write hit request.
+#define P_DMC_CMD_FILTER_CTRL5 ((volatile uint32_t *)0xfd020110)
+//bit 31:24 Once ddr data bus switch to read, the maxmum read command number to give up the bus when there's write request pending for write buffer.
+//bit 23:16 Once ddr data bus switch to write, the maxmum write command number to give up the bus when there's read request pending too long.
+//bit 15:8. Once ddr data bus switch to read, the minimum read command number to transfer back to write stage if there's still pending read request.
+//bit 7:0. Once ddr data bus switch to write, the minimum write command number to transfer back to read stage if there's still pending write request.
+#define P_DMC_CMD_FILTER_CTRL6 ((volatile uint32_t *)0xfd020114)
+//bit 31:24 write urgent 3 request pending hold num.
+//bit 23:16 write urgent 2 request pending hold num.
+//bit 15:8. write urgent 1 request pending hold num.
+//bit 7:0. write urgent 0 request pending hold num.
+#define P_DMC_CMD_FILTER_CTRL7 ((volatile uint32_t *)0xfd020118)
+//bit 15:8 write to read waiting cycles if there write hit request.
+//bit 7:0 read to write waiting cycles if there write hit request.
+#define P_DMC_CMD_BUFFER_CTRL ((volatile uint32_t *)0xfd02011c)
+//bit 31:26 total write buffer number. default 32.
+//bit 25:20 total read buffer number. default 32.
+//bit 19:8 reserved.
+//bit 7:0 aw_pending_inc_num. incease write ugent level 1 when write command waiting to in write buffer that long.
+#define P_DMC_CMD_BUFFER_CTRL1 ((volatile uint32_t *)0xfd020120)
+//bit 29:24 read buffer number in non-urgent request.
+//bit 23:16 read buffer bank miss watch dog threshold.
+//bit 15:12 read buffer urgent level 3 counter inc weight.
+//bit 11:8 read buffer urgent level 2 counter inc weight.
+//bit 7:4 read buffer urgent level 1 counter inc weight.
+//bit 3:0 read buffer urgent level 0 counter inc weight.
+#define P_DMC_AXI0_CHAN_CTRL ((volatile uint32_t *)0xfd020200)
+//bit 31 AXI interface request enable.
+//bit 19 AXI interface auto clock gating enable. 1: enable; 0 disable.
+//bit 18 AXI interface clock disable. 1 : disable clock. 0 enable clock.
+//bit 17 AXI interface dmc clock domain soft reset. 0 : reset. 1 : normal working mode.
+//bit 16 AXI interface s0 clock domain soft reset. 0 : reset. 1 : normal working mode.
+//bit 15:12 ugt3 QOS level.
+//bit 11:8 ugt2 QOS level.
+//bit 7:4 ugt1 QOS level.
+//bit 3:0 not used.
+#define P_DMC_AXI0_HOLD_CTRL ((volatile uint32_t *)0xfd020204)
+//31:24 write hold num. max outstanding request number.
+//23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+//15:8 read hold num. max outstanding request number.
+//7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define P_DMC_AXI5_HOLD_CTRL ((volatile uint32_t *)0xfd020254)
+//31:24 write hold num. max outstanding request number.
+//23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+//15:8 read hold num. max outstanding request number.
+//7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+//`endif
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh
+//
+//`ifdef DMC_SIU_REG_DEFINE
+//`else
+//`define DMC_SIU_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd020400
+// -----------------------------------------------
+//`define DMC_DRAM_REG_BASE 32'hfd020400
+//in A1 project, don't support hardware controlled frequency change.
+#define P_DMC_DRAM_TMRD ((volatile uint32_t *)0xfd020400)
+//bit 3:0. tMRD.
+#define P_DMC_DRAM_TRFC ((volatile uint32_t *)0xfd020404)
+//bit 9:0 tRFC
+#define P_DMC_DRAM_TRP ((volatile uint32_t *)0xfd020408)
+//bit 21:16. tRP for precharge all banks.
+//bit 5:0. tRP for precharge one bank.
+#define P_DMC_DRAM_TRTW ((volatile uint32_t *)0xfd02040c)
+//bit 5:0 tRTW
+#define P_DMC_DRAM_TCL ((volatile uint32_t *)0xfd020410)
+//bit 5:0 tCL/tRL. read latency.
+#define P_DMC_DRAM_TCWL ((volatile uint32_t *)0xfd020414)
+//bit 5:0. CWL: write latency.
+#define P_DMC_DRAM_TRAS ((volatile uint32_t *)0xfd020418)
+//bit 7:0. tRAS. minimum active to precharge time for same bank.
+#define P_DMC_DRAM_TRC ((volatile uint32_t *)0xfd02041c)
+//bit 7:0. tRC. minimum active to active time for same bank.
+#define P_DMC_DRAM_TRCD ((volatile uint32_t *)0xfd020420)
+//bit 7:0 tRCD active to read/write timing for same bank.
+#define P_DMC_DRAM_TRRD ((volatile uint32_t *)0xfd020424)
+//bit 21:16. tRRD_l active bank A to active B in same band group for DDR4.
+//bit 5:0. tRRD/tRRD_s active bank A to active bank b time.
+//tRRD_s: active bank A to active bank b in different bank grousp for DDR4.
+#define P_DMC_DRAM_TFAW ((volatile uint32_t *)0xfd020428)
+//bit 8:0 tFAW. four active command windows
+#define P_DMC_DRAM_TRTP ((volatile uint32_t *)0xfd02042c)
+//bit 5:0 tRTP.
+#define P_DMC_DRAM_TWR ((volatile uint32_t *)0xfd020430)
+//bit 5:0 tWR.
+#define P_DMC_DRAM_TWTR ((volatile uint32_t *)0xfd020434)
+//bit 5:0 tWTR.
+#define P_DMC_DRAM_TCCD ((volatile uint32_t *)0xfd020438)
+//bit 19:16. tCCD/tCCD_l.
+//bit 3:0 tCCD/tCCD_s read to read command time or write to write command time.
+#define P_DMC_DRAM_TEXSR ((volatile uint32_t *)0xfd02043c)
+//bit 9:0. tEXSR. EXIT SELF-REFRESH to read/write command.
+#define P_DMC_DRAM_TXS ((volatile uint32_t *)0xfd020440)
+//bit 9:0 tXS. EXIT SELF_REFRESH to other command time
+#define P_DMC_DRAM_TXP ((volatile uint32_t *)0xfd020444)
+//bit 3:0. tXP. EXIT power down to other command time
+#define P_DMC_DRAM_TXPDLL ((volatile uint32_t *)0xfd020448)
+//bit 9:0. tXPDLL, EXIT power down to read/write command time(need to relock PLL).
+#define P_DMC_DRAM_TZQCS ((volatile uint32_t *)0xfd02044c)
+//bit 11:0. ZQCS command to other command time.
+#define P_DMC_DRAM_TCKSRE ((volatile uint32_t *)0xfd020450)
+//bit 4:0. enter self refresh to disable clock time.
+#define P_DMC_DRAM_TCKSRX ((volatile uint32_t *)0xfd020454)
+//bit 4:0. enable clock to exit self refresh time.
+#define P_DMC_DRAM_TCKE ((volatile uint32_t *)0xfd020458)
+//bit 4:0. CKE high or low minimum time.
+#define P_DMC_DRAM_TMOD ((volatile uint32_t *)0xfd02045c)
+//bit 4:0 tMOD. MRR/MRW to other command time.
+#define P_DMC_DRAM_TDQS ((volatile uint32_t *)0xfd020460)
+//bit 3:0 tDQS. the delay to access different rank.
+#define P_DMC_DRAM_TRSTL ((volatile uint32_t *)0xfd020464)
+//not used.
+#define P_DMC_DRAM_TZQLAT ((volatile uint32_t *)0xfd020468)
+//bit 5:0 ZQ LATCH command to other comand timing in LPDDR4 mode.
+#define P_DMC_DRAM_TMRR ((volatile uint32_t *)0xfd02046c)
+//bit 7:0 tMRR not used in DMC. not support MR READ.
+#define P_DMC_DRAM_TCKESR ((volatile uint32_t *)0xfd020470)
+//bit 9:0 tCKESR. CKE low minimum pulse in self refresh mode.
+#define P_DMC_DRAM_TDPD ((volatile uint32_t *)0xfd020474)
+//not support.
+#define P_DMC_DRAM_DFITCTRLDELAY ((volatile uint32_t *)0xfd020478)
+//bit 3:0. DFI_t_ctrldealy
+#define P_DMC_DRAM_DFITPHYWRDATA ((volatile uint32_t *)0xfd02047c)
+//bit 5:0. dfi_t_phy_wrdata.
+#define P_DMC_DRAM_DFITPHYWRLAT ((volatile uint32_t *)0xfd020480)
+//bit 5:0. dfi_t_phy_wrlat. in DDR3/4/LPDDR3 mode: WL -5. in LPDDR4 mode: WL -5 + 2.
+#define P_DMC_DRAM_DFITRDDATAEN ((volatile uint32_t *)0xfd020484)
+//bit 5:0. dfi_t_rddata_en. in DDR3/4/LPDDR3 mode: RL -5. in LPDDR4 mode : RL -5 + 1.
+#define P_DMC_DRAM_DFITPHYRDLAT ((volatile uint32_t *)0xfd020488)
+//bit 5:0. dfi_t_rdlat.
+#define P_DMC_DRAM_DFITCTRLUPDMIN ((volatile uint32_t *)0xfd02048c)
+//bit 7:0. CTRLUPD_MIN minimux clock cycle to maintain CTRLUPD_REQ.
+#define P_DMC_DRAM_DFITCTRLUPDMAX ((volatile uint32_t *)0xfd020490)
+//bit 7:0 CTRLUPD_MAX. maxmum clock cycle to maintain CTRLUPD_REQ if no CTRLUPD_ACK response.
+#define P_DMC_DRAM_DFITMSTRRESP ((volatile uint32_t *)0xfd020494)
+//not used.
+#define P_DMC_DRAM_DFITREFMSKI ((volatile uint32_t *)0xfd020498)
+//not used.
+#define P_DMC_DRAM_DFITCTRLUPDI ((volatile uint32_t *)0xfd02049c)
+//not used.
+#define P_DMC_DRAM_DFITDRAMCLK ((volatile uint32_t *)0xfd0204a0)
+//bit 17 dram clk1 enable.
+//bit 16 dram clk0 enable.
+//bit 15:8 DRAM CLK disable waiting time
+//bit 7:0 DRAM CLK enable enable timer
+#define P_DMC_DRAM_DFITLPRESP ((volatile uint32_t *)0xfd0204a8)
+//bit 3:0. dfi_lp_ctrl_req response time. after dfi_lp_ctrl_req asserted, and after response time if there's still no dfi_lp_ack respone, then drop the dfi_lp_ctrl_req.
+#define P_DMC_DRAM_DFITPHYMSTR ((volatile uint32_t *)0xfd0204ac)
+//bit 15 1: enable DFIPHYMASTER INTERFACE 0 disable DFIPHYMSTR en response.
+// always 0 we would use DFI_RETRAIN function for PHY retrain required from LPDDR4.
+#define P_DMC_DRAM_TCKECK ((volatile uint32_t *)0xfd0204b0)
+//bit 4:0. tCKECK from CKE low to assert dfi_dram_clk_disable time. this time + dfi_t_ctrl_delay
+#define P_DMC_DRAM_TREFI ((volatile uint32_t *)0xfd0204b4)
+//write this register will update the auto refresh related register to the auto refresh control logic.
+//bit 31:24: tZQCI dmc send zqci period. unit is how much auto refresh period.
+//bit 23:16 pvti dmc send dfi_ctrlupd_req period. unit is one auto refresh period.
+//bit 15:8. tREFI.dmc send auto refresh command period. unit is 100ns.
+//bit 7:0. t100ns period. unit is dmc clock cycles
+#define P_DMC_DRAM_TSR ((volatile uint32_t *)0xfd0204b8)
+//bit 5:0 tSR. self resfresh enter to exit time.
+#define P_DMC_DRAM_TCCDMW ((volatile uint32_t *)0xfd0204bc)
+//bit 5:0. 4*tCCD in LPDDR4 mask write.
+#define P_DMC_DRAM_TESCKE ((volatile uint32_t *)0xfd0204c0)
+//bit 5:0 tESCKE. enter self refresh to power time for LPDDR4.
+#define P_DMC_DRAM_TREFI_DDR3 ((volatile uint32_t *)0xfd0204c4)
+//7:0. 8*DDR3 SDRAM tREFI time . the unit is t100ns. use this to check in 8*tREFI time, the DMC should sent more than 16 auto REFRESH command.
+#define P_DMC_DRAM_TZQCAL ((volatile uint32_t *)0xfd0204c8)
+//7:0. ZQCAL for LPDDR4.
+#define P_DMC_DRAM_T10US ((volatile uint32_t *)0xfd0204cc)
+//10us clock cycle number used for LP2 mode.
+#define P_DMC_DRAM_TMRRI ((volatile uint32_t *)0xfd0204d0)
+//bit 7:0 tMRRI for MRR
+#define P_DMC_DRAM_DFITPHYUPDTYPE0 ((volatile uint32_t *)0xfd020600)
+//dfi_phyupd_ack hold time for dfi_phyupd_req type = 0.
+#define P_DMC_DRAM_DFITPHYUPDTYPE1 ((volatile uint32_t *)0xfd020604)
+//dfi_phyupd_ack hold time for dfi_phyupd_req type = 1.
+#define P_DMC_DRAM_DFITPHYUPDTYPE2 ((volatile uint32_t *)0xfd020608)
+//dfi_phyupd_ack hold time for dfi_phyupd_req type = 2.
+#define P_DMC_DRAM_DFITPHYUPDTYPE3 ((volatile uint32_t *)0xfd02060c)
+//dfi_phyupd_ack hold time for dfi_phyupd_req type = 3.
+#define P_DMC_DRAM_DFIODTCFG ((volatile uint32_t *)0xfd020610)
+//bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity.
+//bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1.
+//bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0.
+//bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1.
+//bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0.
+//bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity.
+//bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0.
+//bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1.
+//bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0.
+//bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1.
+#define P_DMC_DRAM_DFIODTCFG1 ((volatile uint32_t *)0xfd020614)
+//bit 27:24 ODT length for BL8 read transfer.
+//bit 19:16. ODT length for BL8 write transfer.
+//bit 12:8. ODT latency for reads. suppose to be 0.
+//bit 4:0. ODT latency for writes. suppose to be 0.
+#define P_DMC_DRAM_MCFG ((volatile uint32_t *)0xfd020618)
+//bit 14. 1: cke init low. 0 : cke init high.
+//bit 13 1: dbi write enable only for LPDDR4.
+//bit 12. 1: dbi read inversion. 0: dbi read high inversion.
+//bit 11. 1: dbi read enable. 0: dbi not enabled.
+//bit 10 1: enable staggered chip select for 2 ranks DRAM.
+//bit 9 1: enable send auto refresh command to DDR SDRAM when PCTL is in CFG/STOP state.
+//bit 8 send auto refr cmd before enter register triggered self refresh
+//bit 7 send auto refr cmd after exit regsiter triggered self refresh mode.
+//bit 6 disable dram clock after enter register triggered self refresh.
+//bit 5 send DFI_LP_REQ to PHY after enter register triggered elf refresh mode.
+//bit 4 send DRAM to power down mode after enter self refresh. ONLY for LPDDR4.
+//bit 3 send DFI_CTRLUPD_REQ after exit register triggered self refresh.
+//bit 2 send ZQCS command after exit register triggered self refresh.
+//bit 1 enable PHY triggered DFI_PHYUPD_REQ.
+//bit 0 2T mode. always 1 in DDR3/4 mode.
+#define P_DMC_DRAM_DFI_CTRL ((volatile uint32_t *)0xfd020624)
+//bit 31 siu_dfi_lat err generation enable. 1: if dfi read latency violation, generate data error. 0 : disable.
+//bit 30:0. not used.
+#define P_DMC_DRAM_DFIINITCFG ((volatile uint32_t *)0xfd020628)
+//bit 31. dfi_init_complete status. read only.
+//bit 15:14. Frequency set 1 dfi_freq_ratio value. Not used in A1
+//bit 12:8 Frequency set 1 dfi_freq value. Not used in A1
+//bit 7:6 Frequency set 0 dfi_freq_ratio value.
+//bit 5:1 Frequency set 0 dfi_freq value.
+//bit 0. dfi_init_start value can be use manually config dfi_init_start signal.
+#define P_DMC_DRAM_ZQ_CTRL ((volatile uint32_t *)0xfd02062c)
+// only bit 0 can be enable in A1.
+//bit 2 send ZQCS command to RANK0 then send comand to RANK1.
+//bit 1. send ZQCS command to both RANK0 and RANK1 together.
+//bit 0. send ZQCS command to only rank0.
+#define P_DMC_DRAM_APD_CTRL ((volatile uint32_t *)0xfd020630)
+//bit 19:16 DFI_LP_WAKEUP value in APD DFI_LP_REQ mode
+//bit 12 1: exit power down slow mode(waiting PLL LOCK). 0 : fast mode.
+//bit 11 enable DFI_LP_REQ when enter Auto power down mode.
+//bit 10 disable DFI_clk_disable when enter auto power down mode.
+//bit 9:0 0 disable auto power down mode.
+//non zero value to enable auto power down when DMC is in idle state for this number of clock cycles.
+#define P_DMC_DRAM_ASR_CTRL ((volatile uint32_t *)0xfd020634)
+//bit [25] LP2 mode PHYCLK enable. 1 : keep PHY clock enable after enter LP2 mode. 0 : shutdown PHY clock after enter LP2 mode.
+//bit [24] LP2 mode SRX waiting enable. if Self refresh too long, waiting 10us for the PHY stable before DDR SDRAM exit from self refresh state.
+//bit [23:20] DFI_LP_WAKEUP value in self refresh DFI_LP_REQ mode.
+//bit 17 : send REFRESH command after exit from auto self refersh mode(ASR).
+//bit 16 : send REFERSH command before enter to Auto self refresh mode(ASR).
+//bit 15 : send ZQCS command after exit from Auto self refresh mode(ASR).
+//bit 14 : send dfi_ctrl_upd after exit from ASR mode
+//bit 13 : send power down command when enter ASR mode. //for LPDDR4 only.
+//bit 12 : set the PHY enter LP2 mode after enter ASR mode.
+//bit 11 : send DFI_LP_REQ after enter ASR mode.
+//bit 10 : set DFI_CLK_DISABLE after enter ASR mode.
+//bit 9:0. 0 disable auto ASR mode.
+// Non-zero valule enable ASR mode. when DMC is in idle state for this number of clock cycles, the DMC will enter ASR mode.
+#define P_DMC_DRAM_PHYMSTR_CTRL ((volatile uint32_t *)0xfd020640)
+//not used in A1. should be all 0.
+#define P_DMC_DRAM_DFIODTRANKMAP ((volatile uint32_t *)0xfd020644)
+//not used in A1.
+#define P_DMC_DRAM_REFR_CTRL ((volatile uint32_t *)0xfd020648)
+//bit 17:8 auto refresh request pending cnt if there's page hit request.
+//bit 6 Disabled auto refresh command if over 16 auto refresh command sent in 2 TREFI_DDR3 period
+//bit 5 enable dmc send ZQCS command .
+//bit 4. enable dmc send DFI_CTRUPD_REQ.
+//bit 3:1. how many refresh command send for one period. = this number + 1
+//bit 0. enable dmc send auto refresh command.
+#define P_DMC_DRAM_FREQ_CTRL ((volatile uint32_t *)0xfd02064c)
+//bit 31 . wiret 1 to change freqency read 0: finished.
+//bit 30:9. not used.
+//bit 9. 1 : FREQ MRW done. let FREQ change machine continue.
+//bit 8 FREQ WAIT. 1 when freq change finishes, state machine stop at self refresh state in case there's something need to handle.
+// 0 after freq change finishes the state machine go back to access state.
+//bit 7 when change PLL setting, disable dmc clock
+//bit 6 when change PLL setting, disable PHY DfiClk and DfiCtlClk.
+//bit 5 check vpu_sleep_en ==1 when do FREQ change. if vpu_sleep_en == 0, just wait.
+//bit 4 nxt frequency selection. 1 = freq1. 0 = freq0.
+//bit 3:1. not used.
+//bit 0. current frequency selection.
+#define P_DMC_DRAM_SCFG ((volatile uint32_t *)0xfd020650)
+// bit 2:0 only one bit can be high at same time.
+// bit 2 1 : to ask PCTL enter ACCESS STATE. 0 : deassert the request.
+// bit 1 1 : to ask PCTL enter SELF REFRESH STATE. 0 : deassert the request.
+// bit 0 1 : to ask PCTL enter STOP/CONFIG STATE . 0 : deassert the request.
+#define P_DMC_DRAM_STAT ((volatile uint32_t *)0xfd020654)
+//bit 31 rd latency error. 1: means after dfiphytrdlat cycles, the read data still not back.
+//bit 28:24 dram_sr_state
+//bit 23:20 stop_st
+//bit 19:15 sleep_st
+//bit 14:12 ACCESS STATUS 0 : ACCESS is in normal working mode.
+//1 : ACCESS sending precharege command.
+//2 : ACCESS sending AUTO REFESH command.
+//3 : ACCESS sending DIF_CTRLUPD_REQ command.
+//4 : ACCESS sending ZQCS command to DDR DRAM(ZQCAL for LPDDR4).
+//5 : ACCESS sending ZQLATCH command to LPDDR4 only.
+//bit 11:8 APD STATUS: 0 : APD_IDLE
+//1 : APD sending PRECHARGE command
+//2 : APD sending CKE low command
+//3 : APD sending DISABLE DRAM CLOCK command
+//4 : APD sending DFI_LP_CTRL_REQ
+//5 : APD in Auto Power down mode.
+//6 : APD deassert DFI_LP_CTRL_REQ
+//7 : APD sending enable DRAM CLOCK command
+//8 : APD sending out CKE high command.
+//bit 7:4: DRAM_STATUS: 0 : DRAM IDLE
+//1 : DRAM_STOP/DRAM_CFG
+//2 : DRAM_ACCESS
+//3 : DRAM_SLEEP
+//4 : DRAM APD(AUTO POWER DOWN).
+//5 : IDLE -> STOP/CONFIG
+//6 : STOP -> SLEEP
+//7 : STOP -> ACCESS
+//8 : ACCESS -> SLEEP.
+//9 : ACCESS -> STOP
+//A : ACCESS -> APD
+//B : SLEEP -> STOP
+//C : SLEEP -> ACCESS
+//D : APD -> ACCESS
+//bit 3 reserved.
+//bit 2 1 : DRAM enter normal working state.
+//bit 1 1 : DRAM enter sleep state. self refresh state.
+//bit 0 1 : dram enter cfg state.
+#define P_DMC_DRAM_STAT1 ((volatile uint32_t *)0xfd020658)
+//bit 11:8 freq_st.
+//bit 7:5 train_st
+//bit 4:0 dram_phy_st
+#define P_DMC_PHY_RETRAINING_CTRL ((volatile uint32_t *)0xfd02065c)
+// A1 not support LPDDR4 so this register is not used in A1.
+//bit 31 : phy_retraining enable.
+//bit 30 : check vpu sleep_en.
+//bit 25:24 : retraining dfi_freq[4:3], the [2:0] bit still use the dfi_freq bits to keep the frequency.
+//bit 23:0: retraining period unit : 100ns.
+#define P_DMC_DFI_ERR_STAT ((volatile uint32_t *)0xfd020660)
+//LPDDR4 PHY DFI error infomation.
+//bit 31:20. not used.
+//bit 9. ddr0_dfi_error
+//bit 8:5 ddr0_dfi_error_info.
+//bit 4. ddr1_dfi_error.
+//bit 3:0. ddr1_dfi_error_info.
+#define P_DMC_LP2_TIMER ((volatile uint32_t *)0xfd020668)
+//bit 15:0. timer setting to measure how long the chip is entered LP2 mode.
+//this timer is 40bits counter with DMC PCLK.
+//we use the high 16bits to compare this register. if the counter is large than this number, that means the PHY need addition 10us after wakeup the PHY and before exit self_refresh mode.
+#define P_DMC_DRAM_DFI_SWAP_0 ((volatile uint32_t *)0xfd020680)
+//bit 5:0. dfi_act_n function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_1 ((volatile uint32_t *)0xfd020684)
+//bit 5:0. dfi_ras_n function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_2 ((volatile uint32_t *)0xfd020688)
+//bit 5:0. dfi_cas_n function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_3 ((volatile uint32_t *)0xfd02068c)
+//bit 5:0. dfi_we_n function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_4 ((volatile uint32_t *)0xfd020690)
+//bit 5:0. dfi_bg0 function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_5 ((volatile uint32_t *)0xfd020694)
+//bit 5:0. dfi_bg[1] function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_6 ((volatile uint32_t *)0xfd020698)
+//bit 5:0. dfi_ba[0] function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_7 ((volatile uint32_t *)0xfd02069c)
+//bit 5:0. dfi_ba[1] function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_8 ((volatile uint32_t *)0xfd0206a0)
+//bit 5:0. dfi_ba[2] function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_9 ((volatile uint32_t *)0xfd0206a4)
+//bit 5:0. dfi_a[0] function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_10 ((volatile uint32_t *)0xfd0206a8)
+//bit 5:0. dfi_a[1] function select
+#define P_DMC_DRAM_DFI_SWAP_11 ((volatile uint32_t *)0xfd0206ac)
+//bit 5:0. dfi_a[2] function select
+#define P_DMC_DRAM_DFI_SWAP_12 ((volatile uint32_t *)0xfd0206b0)
+//bit 5:0. dfi_a[3] function select
+#define P_DMC_DRAM_DFI_SWAP_13 ((volatile uint32_t *)0xfd0206b4)
+//bit 5:0. dfi_a[4] function select
+#define P_DMC_DRAM_DFI_SWAP_14 ((volatile uint32_t *)0xfd0206b8)
+//bit 5:0. dfi_a[5] function select
+#define P_DMC_DRAM_DFI_SWAP_15 ((volatile uint32_t *)0xfd0206bc)
+//bit 5:0. dfi_a[6] function select
+#define P_DMC_DRAM_DFI_SWAP_16 ((volatile uint32_t *)0xfd0206c0)
+//bit 5:0. dfi_a[7] function select
+#define P_DMC_DRAM_DFI_SWAP_17 ((volatile uint32_t *)0xfd0206c4)
+//bit 5:0. dfi_a[8] function select
+#define P_DMC_DRAM_DFI_SWAP_18 ((volatile uint32_t *)0xfd0206c8)
+//bit 5:0. dfi_a[9] function select
+#define P_DMC_DRAM_DFI_SWAP_19 ((volatile uint32_t *)0xfd0206cc)
+//bit 5:0. dfi_a[10] function select
+#define P_DMC_DRAM_DFI_SWAP_20 ((volatile uint32_t *)0xfd0206d0)
+//bit 5:0. dfi_a[11] function select
+#define P_DMC_DRAM_DFI_SWAP_21 ((volatile uint32_t *)0xfd0206d4)
+//bit 5:0. dfi_a[12] function select
+#define P_DMC_DRAM_DFI_SWAP_22 ((volatile uint32_t *)0xfd0206d8)
+//bit 5:0. dfi_a[13] function select
+#define P_DMC_DRAM_DFI_SWAP_23 ((volatile uint32_t *)0xfd0206dc)
+//bit 5:0. dfi_a[14] function select
+#define P_DMC_DRAM_DFI_SWAP_24 ((volatile uint32_t *)0xfd0206e0)
+//bit 5:0. dfi_a[15] function select
+#define P_DMC_DRAM_DFI_SWAP_25 ((volatile uint32_t *)0xfd0206e4)
+//bit 5:0. dfi_a[16] function select
+#define P_DMC_DRAM_DFI_SWAP_26 ((volatile uint32_t *)0xfd0206ec)
+//bit 5:0. dfi_a[17] function select
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh
+//
+//`ifdef DMC_STICKY_REG_DEFINE
+//`else
+//`define DMC_STICKY_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd020800
+// -----------------------------------------------
+//`define DMC_STICKY_REG_BASE 32'hfd020800
+//those register is for software save some tempary value. and because it's in RAM. it won't lose if DMC get reseted.
+#define P_DMC_STICKY_0 ((volatile uint32_t *)0xfd020800)
+#define P_DMC_STICKY_1 ((volatile uint32_t *)0xfd020804)
+#define P_DMC_STICKY_2 ((volatile uint32_t *)0xfd020808)
+#define P_DMC_STICKY_3 ((volatile uint32_t *)0xfd02080c)
+#define P_DMC_STICKY_4 ((volatile uint32_t *)0xfd020810)
+#define P_DMC_STICKY_5 ((volatile uint32_t *)0xfd020814)
+#define P_DMC_STICKY_6 ((volatile uint32_t *)0xfd020818)
+#define P_DMC_STICKY_7 ((volatile uint32_t *)0xfd02081c)
+#define P_DMC_STICKY_8 ((volatile uint32_t *)0xfd020820)
+#define P_DMC_STICKY_9 ((volatile uint32_t *)0xfd020824)
+#define P_DMC_STICKY_10 ((volatile uint32_t *)0xfd020828)
+#define P_DMC_STICKY_11 ((volatile uint32_t *)0xfd02082c)
+#define P_DMC_STICKY_12 ((volatile uint32_t *)0xfd020830)
+#define P_DMC_STICKY_13 ((volatile uint32_t *)0xfd020834)
+#define P_DMC_STICKY_14 ((volatile uint32_t *)0xfd020838)
+#define P_DMC_STICKY_15 ((volatile uint32_t *)0xfd02083c)
+#define P_DMC_STICKY_16 ((volatile uint32_t *)0xfd020840)
+#define P_DMC_STICKY_17 ((volatile uint32_t *)0xfd020844)
+#define P_DMC_STICKY_18 ((volatile uint32_t *)0xfd020848)
+#define P_DMC_STICKY_19 ((volatile uint32_t *)0xfd02084c)
+#define P_DMC_STICKY_20 ((volatile uint32_t *)0xfd020850)
+#define P_DMC_STICKY_21 ((volatile uint32_t *)0xfd020854)
+#define P_DMC_STICKY_22 ((volatile uint32_t *)0xfd020858)
+#define P_DMC_STICKY_23 ((volatile uint32_t *)0xfd02085c)
+#define P_DMC_STICKY_24 ((volatile uint32_t *)0xfd020860)
+#define P_DMC_STICKY_25 ((volatile uint32_t *)0xfd020864)
+#define P_DMC_STICKY_26 ((volatile uint32_t *)0xfd020868)
+#define P_DMC_STICKY_27 ((volatile uint32_t *)0xfd02086c)
+#define P_DMC_STICKY_28 ((volatile uint32_t *)0xfd020870)
+#define P_DMC_STICKY_29 ((volatile uint32_t *)0xfd020874)
+#define P_DMC_STICKY_30 ((volatile uint32_t *)0xfd020878)
+#define P_DMC_STICKY_31 ((volatile uint32_t *)0xfd02087c)
+#define P_DMC_STICKY_32 ((volatile uint32_t *)0xfd020880)
+#define P_DMC_STICKY_33 ((volatile uint32_t *)0xfd020884)
+#define P_DMC_STICKY_34 ((volatile uint32_t *)0xfd020888)
+#define P_DMC_STICKY_35 ((volatile uint32_t *)0xfd02088c)
+#define P_DMC_STICKY_36 ((volatile uint32_t *)0xfd020890)
+#define P_DMC_STICKY_37 ((volatile uint32_t *)0xfd020894)
+#define P_DMC_STICKY_38 ((volatile uint32_t *)0xfd020898)
+#define P_DMC_STICKY_39 ((volatile uint32_t *)0xfd02089c)
+#define P_DMC_STICKY_40 ((volatile uint32_t *)0xfd0208a0)
+#define P_DMC_STICKY_41 ((volatile uint32_t *)0xfd0208a4)
+#define P_DMC_STICKY_42 ((volatile uint32_t *)0xfd0208a8)
+#define P_DMC_STICKY_43 ((volatile uint32_t *)0xfd0208ac)
+#define P_DMC_STICKY_44 ((volatile uint32_t *)0xfd0208b0)
+#define P_DMC_STICKY_45 ((volatile uint32_t *)0xfd0208b4)
+#define P_DMC_STICKY_46 ((volatile uint32_t *)0xfd0208b8)
+#define P_DMC_STICKY_47 ((volatile uint32_t *)0xfd0208bc)
+#define P_DMC_STICKY_48 ((volatile uint32_t *)0xfd0208c0)
+#define P_DMC_STICKY_49 ((volatile uint32_t *)0xfd0208c4)
+#define P_DMC_STICKY_50 ((volatile uint32_t *)0xfd0208c8)
+#define P_DMC_STICKY_51 ((volatile uint32_t *)0xfd0208cc)
+#define P_DMC_STICKY_52 ((volatile uint32_t *)0xfd0208d0)
+#define P_DMC_STICKY_53 ((volatile uint32_t *)0xfd0208d4)
+#define P_DMC_STICKY_54 ((volatile uint32_t *)0xfd0208d8)
+#define P_DMC_STICKY_55 ((volatile uint32_t *)0xfd0208dc)
+#define P_DMC_STICKY_56 ((volatile uint32_t *)0xfd0208e0)
+#define P_DMC_STICKY_57 ((volatile uint32_t *)0xfd0208e4)
+#define P_DMC_STICKY_58 ((volatile uint32_t *)0xfd0208e8)
+#define P_DMC_STICKY_59 ((volatile uint32_t *)0xfd0208ec)
+#define P_DMC_STICKY_60 ((volatile uint32_t *)0xfd0208f0)
+#define P_DMC_STICKY_61 ((volatile uint32_t *)0xfd0208f4)
+#define P_DMC_STICKY_62 ((volatile uint32_t *)0xfd0208f8)
+#define P_DMC_STICKY_63 ((volatile uint32_t *)0xfd0208fc)
+//`endif
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh
+//
+//========================================================================
+// APB0_RESET_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000000
+// -----------------------------------------------
+#define P_RESETCTRL_RESET0 ((volatile uint32_t *)0xfe000000)
+#define P_RESETCTRL_RESET1 ((volatile uint32_t *)0xfe000004)
+#define P_RESETCTRL_RESET2 ((volatile uint32_t *)0xfe000008)
+#define P_RESETCTRL_RESET0_LEVEL ((volatile uint32_t *)0xfe000040)
+#define P_RESETCTRL_RESET1_LEVEL ((volatile uint32_t *)0xfe000044)
+#define P_RESETCTRL_RESET2_LEVEL ((volatile uint32_t *)0xfe000048)
+#define P_RESETCTRL_RESET0_MASK ((volatile uint32_t *)0xfe000080)
+#define P_RESETCTRL_RESET1_MASK ((volatile uint32_t *)0xfe000084)
+#define P_RESETCTRL_RESET2_MASK ((volatile uint32_t *)0xfe000088)
+#define P_RESETCTRL_RESET_HOLD_CYC ((volatile uint32_t *)0xfe0000c0)
+#define P_RESETCTRL_WATCHDOG_CTRL0 ((volatile uint32_t *)0xfe000100)
+#define P_RESETCTRL_WATCHDOG_CTRL1 ((volatile uint32_t *)0xfe000104)
+#define P_RESETCTRL_WATCHDOG_CNT ((volatile uint32_t *)0xfe000108)
+#define P_RESETCTRL_WATCHDOG_CLR ((volatile uint32_t *)0xfe00010c)
+#define P_RESETCTRL_SEC_RESET0 ((volatile uint32_t *)0xfe000140)
+#define P_RESETCTRL_SEC_RESET0_LEVEL ((volatile uint32_t *)0xfe000144)
+#define P_RESETCTRL_SEC_RESET0_MASK ((volatile uint32_t *)0xfe000148)
+//========================================================================
+// APB0_PAD_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000400
+// -----------------------------------------------
+#define P_PADCTRL_PIN_MUX_REG0 ((volatile uint32_t *)0xfe000400)
+#define P_PADCTRL_PIN_MUX_REG1 ((volatile uint32_t *)0xfe000404)
+#define P_PADCTRL_PIN_MUX_REG2 ((volatile uint32_t *)0xfe000408)
+#define P_PADCTRL_PIN_MUX_REG3 ((volatile uint32_t *)0xfe00040c)
+#define P_PADCTRL_PIN_MUX_REG4 ((volatile uint32_t *)0xfe000410)
+#define P_PADCTRL_PIN_MUX_REG5 ((volatile uint32_t *)0xfe000414)
+#define P_PADCTRL_PIN_MUX_REG6 ((volatile uint32_t *)0xfe000418)
+#define P_PADCTRL_PIN_MUX_REG7 ((volatile uint32_t *)0xfe00041c)
+#define P_PADCTRL_PIN_MUX_REG8 ((volatile uint32_t *)0xfe000420)
+#define P_PADCTRL_PIN_MUX_REG9 ((volatile uint32_t *)0xfe000424)
+#define P_PADCTRL_PIN_MUX_REGA ((volatile uint32_t *)0xfe000428)
+#define P_PADCTRL_PIN_MUX_REGB ((volatile uint32_t *)0xfe00042c)
+#define P_PADCTRL_PIN_MUX_REGC ((volatile uint32_t *)0xfe000430)
+#define P_PADCTRL_PIN_MUX_REGD ((volatile uint32_t *)0xfe000434)
+#define P_PADCTRL_PIN_MUX_REGE ((volatile uint32_t *)0xfe000438)
+#define P_PADCTRL_PIN_MUX_REGF ((volatile uint32_t *)0xfe00043c)
+#define P_PADCTRL_GPIO_IRQ_CTRL0 ((volatile uint32_t *)0xfe000440)
+#define P_PADCTRL_GPIO_IRQ_CTRL1 ((volatile uint32_t *)0xfe000444)
+#define P_PADCTRL_GPIO_IRQ_CTRL2 ((volatile uint32_t *)0xfe000448)
+#define P_PADCTRL_GPIO_IRQ_CTRL3 ((volatile uint32_t *)0xfe00044c)
+#define P_PADCTRL_GPIO_IRQ_CTRL4 ((volatile uint32_t *)0xfe000450)
+#define P_PADCTRL_WORLDSYNC_CTRL0 ((volatile uint32_t *)0xfe000460)
+#define P_PADCTRL_GPIO_MSR_CTRL0 ((volatile uint32_t *)0xfe000464)
+#define P_PADCTRL_GPIOP_I ((volatile uint32_t *)0xfe000480)
+#define P_PADCTRL_GPIOP_O ((volatile uint32_t *)0xfe000484)
+#define P_PADCTRL_GPIOP_OEN ((volatile uint32_t *)0xfe000488)
+#define P_PADCTRL_GPIOP_PULL_EN ((volatile uint32_t *)0xfe00048c)
+#define P_PADCTRL_GPIOP_PULL_UP ((volatile uint32_t *)0xfe000490)
+#define P_PADCTRL_GPIOP_DS ((volatile uint32_t *)0xfe000494)
+#define P_PADCTRL_GPIOB_I ((volatile uint32_t *)0xfe0004c0)
+#define P_PADCTRL_GPIOB_O ((volatile uint32_t *)0xfe0004c4)
+#define P_PADCTRL_GPIOB_OEN ((volatile uint32_t *)0xfe0004c8)
+#define P_PADCTRL_GPIOB_PULL_EN ((volatile uint32_t *)0xfe0004cc)
+#define P_PADCTRL_GPIOB_PULL_UP ((volatile uint32_t *)0xfe0004d0)
+#define P_PADCTRL_GPIOB_DS ((volatile uint32_t *)0xfe0004d4)
+#define P_PADCTRL_GPIOX_I ((volatile uint32_t *)0xfe000500)
+#define P_PADCTRL_GPIOX_O ((volatile uint32_t *)0xfe000504)
+#define P_PADCTRL_GPIOX_OEN ((volatile uint32_t *)0xfe000508)
+#define P_PADCTRL_GPIOX_PULL_EN ((volatile uint32_t *)0xfe00050c)
+#define P_PADCTRL_GPIOX_PULL_UP ((volatile uint32_t *)0xfe000510)
+#define P_PADCTRL_GPIOX_DS ((volatile uint32_t *)0xfe000514)
+#define P_PADCTRL_GPIOX_DS_EXT ((volatile uint32_t *)0xfe000518)
+#define P_PADCTRL_GPIOF_I ((volatile uint32_t *)0xfe000540)
+#define P_PADCTRL_GPIOF_O ((volatile uint32_t *)0xfe000544)
+#define P_PADCTRL_GPIOF_OEN ((volatile uint32_t *)0xfe000548)
+#define P_PADCTRL_GPIOF_PULL_EN ((volatile uint32_t *)0xfe00054c)
+#define P_PADCTRL_GPIOF_PULL_UP ((volatile uint32_t *)0xfe000550)
+#define P_PADCTRL_GPIOF_DS ((volatile uint32_t *)0xfe000554)
+#define P_PADCTRL_GPIOA_I ((volatile uint32_t *)0xfe000580)
+#define P_PADCTRL_GPIOA_O ((volatile uint32_t *)0xfe000584)
+#define P_PADCTRL_GPIOA_OEN ((volatile uint32_t *)0xfe000588)
+#define P_PADCTRL_GPIOA_PULL_EN ((volatile uint32_t *)0xfe00058c)
+#define P_PADCTRL_GPIOA_PULL_UP ((volatile uint32_t *)0xfe000590)
+#define P_PADCTRL_GPIOA_DS ((volatile uint32_t *)0xfe000594)
+#define P_PADCTRL_TESTN_I ((volatile uint32_t *)0xfe0005c0)
+#define P_PADCTRL_TESTN_O ((volatile uint32_t *)0xfe0005c4)
+#define P_PADCTRL_TESTN_OEN ((volatile uint32_t *)0xfe0005c8)
+#define P_PADCTRL_TESTN_PULL_EN ((volatile uint32_t *)0xfe0005cc)
+#define P_PADCTRL_TESTN_PULL_UP ((volatile uint32_t *)0xfe0005d0)
+#define P_PADCTRL_TESTN_DS ((volatile uint32_t *)0xfe0005d4)
+#define P_PADCTRL_MUTE_CTRL ((volatile uint32_t *)0xfe000600)
+//========================================================================
+// APB0_CLK_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000800
+// -----------------------------------------------
+#define P_CLKTREE_SYS_OSCIN_CTRL ((volatile uint32_t *)0xfe000800)
+#define P_CLKTREE_RTC_BY_OSCIN_CTRL0 ((volatile uint32_t *)0xfe000804)
+#define P_CLKTREE_RTC_BY_OSCIN_CTRL1 ((volatile uint32_t *)0xfe000808)
+#define P_CLKTREE_RTC_CTRL ((volatile uint32_t *)0xfe00080c)
+#define P_CLKTREE_SYS_CLK_CTRL0 ((volatile uint32_t *)0xfe000810)
+#define P_CLKTREE_AXI_CLK_CTRL0 ((volatile uint32_t *)0xfe000814)
+#define P_CLKTREE_SYS_CLK_EN0 ((volatile uint32_t *)0xfe00081c)
+#define P_CLKTREE_SYS_CLK_EN1 ((volatile uint32_t *)0xfe000820)
+#define P_CLKTREE_AXI_CLK_EN ((volatile uint32_t *)0xfe000824)
+#define P_CLKTREE_DSPA_CLK_EN ((volatile uint32_t *)0xfe000828)
+#define P_CLKTREE_DSPB_CLK_EN ((volatile uint32_t *)0xfe00082c)
+#define P_CLKTREE_DSPA_CLK_CTRL0 ((volatile uint32_t *)0xfe000830)
+#define P_CLKTREE_DSPB_CLK_CTRL0 ((volatile uint32_t *)0xfe000834)
+#define P_CLKTREE_CLK12_24_CTRL ((volatile uint32_t *)0xfe000838)
+#define P_CLKTREE_GEN_CLK_CTRL ((volatile uint32_t *)0xfe00083c)
+#define P_CLKTREE_TIMESTAMP_CTRL0 ((volatile uint32_t *)0xfe000840)
+#define P_CLKTREE_TIMESTAMP_CTRL1 ((volatile uint32_t *)0xfe000844)
+#define P_CLKTREE_TIMESTAMP_CTRL2 ((volatile uint32_t *)0xfe000848)
+#define P_CLKTREE_TIMESTAMP_VAL0 ((volatile uint32_t *)0xfe00084c)
+#define P_CLKTREE_TIMESTAMP_VAL1 ((volatile uint32_t *)0xfe000850)
+#define P_CLKTREE_TIMEBASE_CTRL0 ((volatile uint32_t *)0xfe000854)
+#define P_CLKTREE_TIMEBASE_CTRL1 ((volatile uint32_t *)0xfe000858)
+#define P_CLKTREE_SAR_ADC_CLK_CTRL ((volatile uint32_t *)0xfe0008c0)
+#define P_CLKTREE_PWM_CLK_AB_CTRL ((volatile uint32_t *)0xfe0008c4)
+#define P_CLKTREE_PWM_CLK_CD_CTRL ((volatile uint32_t *)0xfe0008c8)
+#define P_CLKTREE_PWM_CLK_EF_CTRL ((volatile uint32_t *)0xfe0008cc)
+#define P_CLKTREE_SPICC_CLK_CTRL ((volatile uint32_t *)0xfe0008d0)
+#define P_CLKTREE_TS_CLK_CTRL ((volatile uint32_t *)0xfe0008d4)
+#define P_CLKTREE_SPIFC_CLK_CTRL ((volatile uint32_t *)0xfe0008d8)
+#define P_CLKTREE_USB_BUSCLK_CTRL ((volatile uint32_t *)0xfe0008dc)
+#define P_CLKTREE_SD_EMMC_CLK_CTRL ((volatile uint32_t *)0xfe0008e0)
+#define P_CLKTREE_CECA_CLK_CTRL0 ((volatile uint32_t *)0xfe0008e4)
+#define P_CLKTREE_CECA_CLK_CTRL1 ((volatile uint32_t *)0xfe0008e8)
+#define P_CLKTREE_CECB_CLK_CTRL0 ((volatile uint32_t *)0xfe0008ec)
+#define P_CLKTREE_CECB_CLK_CTRL1 ((volatile uint32_t *)0xfe0008f0)
+#define P_CLKTREE_PSRAM_CLK_CTRL ((volatile uint32_t *)0xfe0008f4)
+#define P_CLKTREE_DMC_CLK_CTRL ((volatile uint32_t *)0xfe0008f8)
+#define P_CLKTREE_FCLK_DIV1_SEL ((volatile uint32_t *)0xfe0008fc)
+#define P_CLKTREE_TST_CTRL0 ((volatile uint32_t *)0xfe000900)
+//========================================================================
+// APB0_CEC - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000c00
+// -----------------------------------------------
+#define P_CECA_GEN_CNTL ((volatile uint32_t *)0xfe000c00)
+#define P_CECA_RW_REG ((volatile uint32_t *)0xfe000c04)
+#define P_CECA_INTR_MASKN ((volatile uint32_t *)0xfe000c08)
+#define P_CECA_INTR_CLR ((volatile uint32_t *)0xfe000c0c)
+#define P_CECA_INTR_STAT ((volatile uint32_t *)0xfe000c10)
+#define P_CECB_GEN_CNTL ((volatile uint32_t *)0xfe000c40)
+#define P_CECB_RW_REG ((volatile uint32_t *)0xfe000c44)
+#define P_CECB_INTR_MASKN ((volatile uint32_t *)0xfe000c48)
+#define P_CECB_INTR_CLR ((volatile uint32_t *)0xfe000c4c)
+#define P_CECB_INTR_STAT ((volatile uint32_t *)0xfe000c50)
+//========================================================================
+// APB0_IR_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001000
+// -----------------------------------------------
+#define P_IRCTRL_IR_DEC_LDR_ACTIVE ((volatile uint32_t *)0xfe001000)
+#define P_IRCTRL_IR_DEC_LDR_IDLE ((volatile uint32_t *)0xfe001004)
+#define P_IRCTRL_IR_DEC_LDR_REPEAT ((volatile uint32_t *)0xfe001008)
+#define P_IRCTRL_IR_DEC_BIT_0 ((volatile uint32_t *)0xfe00100c)
+#define P_IRCTRL_IR_DEC_REG0 ((volatile uint32_t *)0xfe001010)
+#define P_IRCTRL_IR_DEC_FRAME ((volatile uint32_t *)0xfe001014)
+#define P_IRCTRL_IR_DEC_STATUS ((volatile uint32_t *)0xfe001018)
+#define P_IRCTRL_IR_DEC_REG1 ((volatile uint32_t *)0xfe00101c)
+#define P_IRCTRL_MF_IR_DEC_LDR_ACTIVE ((volatile uint32_t *)0xfe001040)
+#define P_IRCTRL_MF_IR_DEC_LDR_IDLE ((volatile uint32_t *)0xfe001044)
+#define P_IRCTRL_MF_IR_DEC_LDR_REPEAT ((volatile uint32_t *)0xfe001048)
+#define P_IRCTRL_MF_IR_DEC_BIT_0 ((volatile uint32_t *)0xfe00104c)
+#define P_IRCTRL_MF_IR_DEC_REG0 ((volatile uint32_t *)0xfe001050)
+#define P_IRCTRL_MF_IR_DEC_FRAME ((volatile uint32_t *)0xfe001054)
+#define P_IRCTRL_MF_IR_DEC_STATUS ((volatile uint32_t *)0xfe001058)
+#define P_IRCTRL_MF_IR_DEC_REG1 ((volatile uint32_t *)0xfe00105c)
+#define P_IRCTRL_MF_IR_DEC_REG2 ((volatile uint32_t *)0xfe001060)
+#define P_IRCTRL_MF_IR_DEC_DURATN2 ((volatile uint32_t *)0xfe001064)
+#define P_IRCTRL_MF_IR_DEC_DURATN3 ((volatile uint32_t *)0xfe001068)
+#define P_IRCTRL_MF_IR_DEC_FRAME1 ((volatile uint32_t *)0xfe00106c)
+#define P_IRCTRL_MF_IR_DEC_STATUS1 ((volatile uint32_t *)0xfe001070)
+#define P_IRCTRL_MF_IR_DEC_STATUS2 ((volatile uint32_t *)0xfe001074)
+#define P_IRCTRL_MF_IR_DEC_REG3 ((volatile uint32_t *)0xfe001078)
+#define P_IRCTRL_MF_IR_DEC_FRAME_RSV0 ((volatile uint32_t *)0xfe00107c)
+#define P_IRCTRL_MF_IR_DEC_FRAME_RSV1 ((volatile uint32_t *)0xfe001080)
+#define P_IRCTRL_MF_IR_DEC_FILTE ((volatile uint32_t *)0xfe001084)
+#define P_IRCTRL_MF_IR_DEC_IRQ_CTL ((volatile uint32_t *)0xfe001088)
+#define P_IRCTRL_MF_IR_DEC_FIFO_CTL ((volatile uint32_t *)0xfe00108c)
+#define P_IRCTRL_MF_IR_DEC_WIDTH_NEW ((volatile uint32_t *)0xfe001090)
+#define P_IRCTRL_MF_IR_DEC_REPEAT_DET ((volatile uint32_t *)0xfe001094)
+#define P_IRCTRL_IR_DEC_DEMOD_CNTL0 ((volatile uint32_t *)0xfe0010c0)
+#define P_IRCTRL_IR_DEC_DEMOD_CNTL1 ((volatile uint32_t *)0xfe0010c4)
+#define P_IRCTRL_IR_DEC_DEMOD_IIR_THD ((volatile uint32_t *)0xfe0010c8)
+#define P_IRCTRL_IR_DEC_DEMOD_THD0 ((volatile uint32_t *)0xfe0010cc)
+#define P_IRCTRL_IR_DEC_DEMOD_THD1 ((volatile uint32_t *)0xfe0010d0)
+#define P_IRCTRL_IR_DEC_DEMOD_SUM_CNT0 ((volatile uint32_t *)0xfe0010d4)
+#define P_IRCTRL_IR_DEC_DEMOD_SUM_CNT1 ((volatile uint32_t *)0xfe0010d8)
+#define P_IRCTRL_IR_DEC_DEMOD_CNT0 ((volatile uint32_t *)0xfe0010dc)
+#define P_IRCTRL_IR_DEC_DEMOD_CNT1 ((volatile uint32_t *)0xfe0010e0)
+#define P_IRCTRL_IR_BLASTER_ADDR0 ((volatile uint32_t *)0xfe00110c)
+#define P_IRCTRL_IR_BLASTER_ADDR1 ((volatile uint32_t *)0xfe001110)
+#define P_IRCTRL_IR_BLASTER_ADDR2 ((volatile uint32_t *)0xfe001114)
+#define P_IRCTRL_IR_BLASTER_ADDR3 ((volatile uint32_t *)0xfe001118)
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001400
+// -----------------------------------------------
+#define P_I2C_M_A_CONTROL_REG ((volatile uint32_t *)0xfe001400)
+#define P_I2C_M_A_SLAVE_ADDR ((volatile uint32_t *)0xfe001404)
+#define P_I2C_M_A_TOKEN_LIST0 ((volatile uint32_t *)0xfe001408)
+#define P_I2C_M_A_TOKEN_LIST1 ((volatile uint32_t *)0xfe00140c)
+#define P_I2C_M_A_WDATA_REG0 ((volatile uint32_t *)0xfe001410)
+#define P_I2C_M_A_WDATA_REG1 ((volatile uint32_t *)0xfe001414)
+#define P_I2C_M_A_RDATA_REG0 ((volatile uint32_t *)0xfe001418)
+#define P_I2C_M_A_RDATA_REG1 ((volatile uint32_t *)0xfe00141c)
+#define P_I2C_M_A_TIMEOUT_TH ((volatile uint32_t *)0xfe001420)
+//========================================================================
+// APB0_I2C_S - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001800
+// -----------------------------------------------
+#define P_I2C_S_A_CONTROL_REG ((volatile uint32_t *)0xfe001800)
+#define P_I2C_S_A_SEND_REG ((volatile uint32_t *)0xfe001804)
+#define P_I2C_S_A_RECV_REG ((volatile uint32_t *)0xfe001808)
+#define P_I2C_S_A_CNTL1_REG ((volatile uint32_t *)0xfe00180c)
+//========================================================================
+// APB0_UART_A - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001c00
+// -----------------------------------------------
+#define P_UART_A_WFIFO ((volatile uint32_t *)0xfe001c00)
+#define P_UART_A_RFIFO ((volatile uint32_t *)0xfe001c04)
+#define P_UART_A_CONTROL ((volatile uint32_t *)0xfe001c08)
+#define P_UART_A_STATUS ((volatile uint32_t *)0xfe001c0c)
+#define P_UART_A_MISC ((volatile uint32_t *)0xfe001c10)
+#define P_UART_A_REG5 ((volatile uint32_t *)0xfe001c14)
+//========================================================================
+// APB0_UART_B - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002000
+// -----------------------------------------------
+#define P_UART_B_WFIFO ((volatile uint32_t *)0xfe002000)
+#define P_UART_B_RFIFO ((volatile uint32_t *)0xfe002004)
+#define P_UART_B_CONTROL ((volatile uint32_t *)0xfe002008)
+#define P_UART_B_STATUS ((volatile uint32_t *)0xfe00200c)
+#define P_UART_B_MISC ((volatile uint32_t *)0xfe002010)
+#define P_UART_B_REG5 ((volatile uint32_t *)0xfe002014)
+//========================================================================
+// APB0_PWM_AB - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002400
+// -----------------------------------------------
+#define P_PWMAB_PWM_A ((volatile uint32_t *)0xfe002400)
+#define P_PWMAB_PWM_B ((volatile uint32_t *)0xfe002404)
+#define P_PWMAB_MISC_REG_AB ((volatile uint32_t *)0xfe002408)
+#define P_PWMAB_DELTA_SIGMA_AB ((volatile uint32_t *)0xfe00240c)
+#define P_PWMAB_TIME_AB ((volatile uint32_t *)0xfe002410)
+#define P_PWMAB_A2 ((volatile uint32_t *)0xfe002414)
+#define P_PWMAB_B2 ((volatile uint32_t *)0xfe002418)
+#define P_PWMAB_BLINK_AB ((volatile uint32_t *)0xfe00241c)
+#define P_PWMAB_LOCK_AB ((volatile uint32_t *)0xfe002420)
+//========================================================================
+// APB0_PWM_CD - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002800
+// -----------------------------------------------
+#define P_PWMCD_PWM_C ((volatile uint32_t *)0xfe002800)
+#define P_PWMCD_PWM_D ((volatile uint32_t *)0xfe002804)
+#define P_PWMCD_MISC_REG_CD ((volatile uint32_t *)0xfe002808)
+#define P_PWMCD_DELTA_SIGMA_CD ((volatile uint32_t *)0xfe00280c)
+#define P_PWMCD_TIME_CD ((volatile uint32_t *)0xfe002810)
+#define P_PWMCD_C2 ((volatile uint32_t *)0xfe002814)
+#define P_PWMCD_D2 ((volatile uint32_t *)0xfe002818)
+#define P_PWMCD_BLINK_CD ((volatile uint32_t *)0xfe00281c)
+#define P_PWMCD_LOCK_CD ((volatile uint32_t *)0xfe002820)
+//========================================================================
+// APB0_SARADC - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002c00
+// -----------------------------------------------
+#define P_SAR_ADC_REG0 ((volatile uint32_t *)0xfe002c00)
+#define P_SAR_ADC_CHAN_LIST ((volatile uint32_t *)0xfe002c04)
+#define P_SAR_ADC_AVG_CNTL ((volatile uint32_t *)0xfe002c08)
+#define P_SAR_ADC_REG3 ((volatile uint32_t *)0xfe002c0c)
+#define P_SAR_ADC_DELAY ((volatile uint32_t *)0xfe002c10)
+#define P_SAR_ADC_LAST_RD ((volatile uint32_t *)0xfe002c14)
+#define P_SAR_ADC_FIFO_RD ((volatile uint32_t *)0xfe002c18)
+#define P_SAR_ADC_AUX_SW ((volatile uint32_t *)0xfe002c1c)
+#define P_SAR_ADC_CHAN_10_SW ((volatile uint32_t *)0xfe002c20)
+#define P_SAR_ADC_DETECT_IDLE_SW ((volatile uint32_t *)0xfe002c24)
+#define P_SAR_ADC_DELTA_10 ((volatile uint32_t *)0xfe002c28)
+#define P_SAR_ADC_REG11 ((volatile uint32_t *)0xfe002c2c)
+#define P_SAR_ADC_REG12 ((volatile uint32_t *)0xfe002c30)
+#define P_SAR_ADC_REG13 ((volatile uint32_t *)0xfe002c34)
+#define P_SAR_ADC_CHNL01 ((volatile uint32_t *)0xfe002c38)
+#define P_SAR_ADC_CHNL23 ((volatile uint32_t *)0xfe002c3c)
+#define P_SAR_ADC_CHNL45 ((volatile uint32_t *)0xfe002c40)
+#define P_SAR_ADC_CHNL67 ((volatile uint32_t *)0xfe002c44)
+//========================================================================
+// JTAGCTRL_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003000
+// -----------------------------------------------
+#define P_JTAGCTRL_CTRL0 ((volatile uint32_t *)0xfe003000)
+#define P_JTAGCTRL_PWD_CTRL0 ((volatile uint32_t *)0xfe003004)
+#define P_JTAGCTRL_PWD_ADDR0 ((volatile uint32_t *)0xfe003008)
+#define P_JTAGCTRL_PWD_ADDR1 ((volatile uint32_t *)0xfe00300c)
+#define P_JTAGCTRL_PWD_ADDR2 ((volatile uint32_t *)0xfe003010)
+#define P_JTAGCTRL_PWD_ADDR3 ((volatile uint32_t *)0xfe003014)
+#define P_JTAGCTRL_PWD_VALUE0 ((volatile uint32_t *)0xfe003018)
+#define P_JTAGCTRL_PWD_VALUE1 ((volatile uint32_t *)0xfe00301c)
+#define P_JTAGCTRL_PWD_VALUE2 ((volatile uint32_t *)0xfe003020)
+#define P_JTAGCTRL_PWD_VALUE3 ((volatile uint32_t *)0xfe003024)
+#define P_JTAGCTRL_PWD_STS ((volatile uint32_t *)0xfe003028)
+//========================================================================
+// APB0_MSR_CLK - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003400
+// -----------------------------------------------
+#define P_MSR_CLK_REG0 ((volatile uint32_t *)0xfe003400)
+#define P_MSR_CLK_REG1 ((volatile uint32_t *)0xfe003404)
+#define P_MSR_CLK_REG2 ((volatile uint32_t *)0xfe003408)
+#define P_MSR_CLK_REG3 ((volatile uint32_t *)0xfe00340c)
+#define P_MSR_CLK_REG4 ((volatile uint32_t *)0xfe003410)
+#define P_MSR_CLK_REG5 ((volatile uint32_t *)0xfe003414)
+#define P_MSR_CLK_DUTY ((volatile uint32_t *)0xfe003418)
+//========================================================================
+// APB0_SPICCA_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003800
+// -----------------------------------------------
+#define P_SPICC_A_RXDATA ((volatile uint32_t *)0xfe003800)
+#define P_SPICC_A_TXDATA ((volatile uint32_t *)0xfe003804)
+#define P_SPICC_A_CONREG ((volatile uint32_t *)0xfe003808)
+#define P_SPICC_A_INTREG ((volatile uint32_t *)0xfe00380c)
+#define P_SPICC_A_DMAREG ((volatile uint32_t *)0xfe003810)
+#define P_SPICC_A_STATREG ((volatile uint32_t *)0xfe003814)
+#define P_SPICC_A_PERIODREG ((volatile uint32_t *)0xfe003818)
+#define P_SPICC_A_TESTREG ((volatile uint32_t *)0xfe00381c)
+#define P_SPICC_A_DRADDR ((volatile uint32_t *)0xfe003820)
+#define P_SPICC_A_DWADDR ((volatile uint32_t *)0xfe003824)
+#define P_SPICC_A_LD_CNTL0 ((volatile uint32_t *)0xfe003828)
+#define P_SPICC_A_LD_CNTL1 ((volatile uint32_t *)0xfe00382c)
+#define P_SPICC_A_LD_RADDR ((volatile uint32_t *)0xfe003830)
+#define P_SPICC_A_LD_WADDR ((volatile uint32_t *)0xfe003834)
+#define P_SPICC_A_ENHANCE_CNTL ((volatile uint32_t *)0xfe003838)
+#define P_SPICC_A_ENHANCE_CNTL1 ((volatile uint32_t *)0xfe00383c)
+#define P_SPICC_A_ENHANCE_CNTL2 ((volatile uint32_t *)0xfe003840)
+//========================================================================
+// APB0_SPICCB_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003c00
+// -----------------------------------------------
+#define P_SPICC_B_RXDATA ((volatile uint32_t *)0xfe003c00)
+#define P_SPICC_B_TXDATA ((volatile uint32_t *)0xfe003c04)
+#define P_SPICC_B_CONREG ((volatile uint32_t *)0xfe003c08)
+#define P_SPICC_B_INTREG ((volatile uint32_t *)0xfe003c0c)
+#define P_SPICC_B_DMAREG ((volatile uint32_t *)0xfe003c10)
+#define P_SPICC_B_STATREG ((volatile uint32_t *)0xfe003c14)
+#define P_SPICC_B_PERIODREG ((volatile uint32_t *)0xfe003c18)
+#define P_SPICC_B_TESTREG ((volatile uint32_t *)0xfe003c1c)
+#define P_SPICC_B_DRADDR ((volatile uint32_t *)0xfe003c20)
+#define P_SPICC_B_DWADDR ((volatile uint32_t *)0xfe003c24)
+#define P_SPICC_B_LD_CNTL0 ((volatile uint32_t *)0xfe003c28)
+#define P_SPICC_B_LD_CNTL1 ((volatile uint32_t *)0xfe003c2c)
+#define P_SPICC_B_LD_RADDR ((volatile uint32_t *)0xfe003c30)
+#define P_SPICC_B_LD_WADDR ((volatile uint32_t *)0xfe003c34)
+#define P_SPICC_B_ENHANCE_CNTL ((volatile uint32_t *)0xfe003c38)
+#define P_SPICC_B_ENHANCE_CNTL1 ((volatile uint32_t *)0xfe003c3c)
+#define P_SPICC_B_ENHANCE_CNTL2 ((volatile uint32_t *)0xfe003c40)
+//========================================================================
+// USBCTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe004000
+// -----------------------------------------------
+#define P_USB_CTRL0 ((volatile uint32_t *)0xfe004000)
+#define P_USB_CTRL1 ((volatile uint32_t *)0xfe004004)
+#define P_USB_CTRL2 ((volatile uint32_t *)0xfe004008)
+#define P_USB_CTRL3 ((volatile uint32_t *)0xfe00400c)
+#define P_USB_CTRL4 ((volatile uint32_t *)0xfe004010)
+#define P_USB_CTRL5 ((volatile uint32_t *)0xfe004014)
+#define P_USB_CTRL6 ((volatile uint32_t *)0xfe004018)
+#define P_USB_CTRL7 ((volatile uint32_t *)0xfe00401c)
+#define P_USB_CTRL8 ((volatile uint32_t *)0xfe004020)
+#define P_USB_CTRL9 ((volatile uint32_t *)0xfe004024)
+#define P_USB_CTRL10 ((volatile uint32_t *)0xfe004028)
+#define P_USB_CTRL11 ((volatile uint32_t *)0xfe00402c)
+#define P_USB_CTRL12 ((volatile uint32_t *)0xfe004030)
+#define P_USB_CTRL13 ((volatile uint32_t *)0xfe004034)
+#define P_USB_CTRL14 ((volatile uint32_t *)0xfe004038)
+#define P_USB_CTRL15 ((volatile uint32_t *)0xfe00403c)
+#define P_USB_CTRL16 ((volatile uint32_t *)0xfe004040)
+#define P_USB_CTRL17 ((volatile uint32_t *)0xfe004044)
+#define P_USB_CTRL18 ((volatile uint32_t *)0xfe004048)
+#define P_USB_CTRL19 ((volatile uint32_t *)0xfe00404c)
+#define P_USB_CTRL20 ((volatile uint32_t *)0xfe004050)
+#define P_USB_CTRL21 ((volatile uint32_t *)0xfe004054)
+#define P_USB_CTRL22 ((volatile uint32_t *)0xfe004058)
+#define P_USB_CTRL23 ((volatile uint32_t *)0xfe00405c)
+#define P_USB_CTRL24 ((volatile uint32_t *)0xfe004060)
+#define P_USB_CTRL25 ((volatile uint32_t *)0xfe004064)
+#define P_USB_CTRL26 ((volatile uint32_t *)0xfe004068)
+#define P_USB_CTRL27 ((volatile uint32_t *)0xfe00406c)
+#define P_USB_CTRL28 ((volatile uint32_t *)0xfe004070)
+#define P_USB_CTRL29 ((volatile uint32_t *)0xfe004074)
+#define P_USB_CTRL30 ((volatile uint32_t *)0xfe004078)
+#define P_USB_CTRL31 ((volatile uint32_t *)0xfe00407c)
+//========================================================================
+// APB0_ACODEC_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe004800
+// -----------------------------------------------
+#define P_ACODEC_0 ((volatile uint32_t *)0xfe004800)
+#define P_ACODEC_1 ((volatile uint32_t *)0xfe004804)
+#define P_ACODEC_2 ((volatile uint32_t *)0xfe004808)
+#define P_ACODEC_3 ((volatile uint32_t *)0xfe00480c)
+#define P_ACODEC_4 ((volatile uint32_t *)0xfe004810)
+#define P_ACODEC_5 ((volatile uint32_t *)0xfe004814)
+#define P_ACODEC_6 ((volatile uint32_t *)0xfe004818)
+#define P_ACODEC_7 ((volatile uint32_t *)0xfe00481c)
+#define P_ACODEC_8 ((volatile uint32_t *)0xfe004820)
+#define P_ACODEC_9 ((volatile uint32_t *)0xfe004824)
+#define P_ACODEC_STS0 ((volatile uint32_t *)0xfe004840)
+//========================================================================
+// APB0_TEMP_SENSOR - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe004c00
+// -----------------------------------------------
+#define P_TS_CFG_REG1 ((volatile uint32_t *)0xfe004c04)
+#define P_TS_CFG_REG2 ((volatile uint32_t *)0xfe004c08)
+#define P_TS_CFG_REG3 ((volatile uint32_t *)0xfe004c0c)
+#define P_TS_CFG_REG4 ((volatile uint32_t *)0xfe004c10)
+#define P_TS_CFG_REG5 ((volatile uint32_t *)0xfe004c14)
+#define P_TS_CFG_REG6 ((volatile uint32_t *)0xfe004c18)
+#define P_TS_CFG_REG7 ((volatile uint32_t *)0xfe004c1c)
+#define P_TS_STAT0 ((volatile uint32_t *)0xfe004c40)
+#define P_TS_STAT1 ((volatile uint32_t *)0xfe004c44)
+#define P_TS_STAT2 ((volatile uint32_t *)0xfe004c48)
+#define P_TS_STAT3 ((volatile uint32_t *)0xfe004c4c)
+#define P_TS_STAT4 ((volatile uint32_t *)0xfe004c50)
+#define P_TS_STAT5 ((volatile uint32_t *)0xfe004c54)
+#define P_TS_STAT6 ((volatile uint32_t *)0xfe004c58)
+#define P_TS_STAT7 ((volatile uint32_t *)0xfe004c5c)
+#define P_TS_STAT8 ((volatile uint32_t *)0xfe004c60)
+#define P_TS_STAT9 ((volatile uint32_t *)0xfe004c64)
+//========================================================================
+// APB0_KL_EFUSE_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005000
+// -----------------------------------------------
+//
+// Reading file: ../crypto/crypto_reg.h
+//
+#define P_OTP_TEE_RDY ((volatile uint32_t *)0xfe005000)
+#define P_OTP_TEE_CHK ((volatile uint32_t *)0xfe005004)
+#define P_OTP_TEE_CFG ((volatile uint32_t *)0xfe005008)
+#define P_OTP_TEE_WR_DAT0 ((volatile uint32_t *)0xfe005010)
+#define P_OTP_TEE_WR_DAT1 ((volatile uint32_t *)0xfe005014)
+#define P_OTP_TEE_WR_DAT2 ((volatile uint32_t *)0xfe005018)
+#define P_OTP_TEE_WR_DAT3 ((volatile uint32_t *)0xfe00501c)
+#define P_OTP_TEE_RD_DAT0 ((volatile uint32_t *)0xfe005020)
+#define P_OTP_TEE_RD_DAT1 ((volatile uint32_t *)0xfe005024)
+#define P_OTP_TEE_RD_DAT2 ((volatile uint32_t *)0xfe005028)
+#define P_OTP_TEE_RD_DAT3 ((volatile uint32_t *)0xfe00502c)
+#define P_OTP_RMA_PW0 ((volatile uint32_t *)0xfe005030)
+#define P_OTP_RMA_PW1 ((volatile uint32_t *)0xfe005034)
+#define P_OTP_RMA_PW2 ((volatile uint32_t *)0xfe005038)
+#define P_OTP_RMA_PW3 ((volatile uint32_t *)0xfe00503c)
+#define P_OTP_REE_RDY ((volatile uint32_t *)0xfe005040)
+#define P_OTP_REE_CHK ((volatile uint32_t *)0xfe005044)
+#define P_OTP_REE_CFG ((volatile uint32_t *)0xfe005048)
+#define P_OTP_REE_RD_DAT0 ((volatile uint32_t *)0xfe005050)
+#define P_OTP_REE_RD_DAT1 ((volatile uint32_t *)0xfe005054)
+#define P_OTP_REE_RD_DAT2 ((volatile uint32_t *)0xfe005058)
+#define P_OTP_REE_RD_DAT3 ((volatile uint32_t *)0xfe00505c)
+#define P_OTP_LIC0 ((volatile uint32_t *)0xfe005060)
+#define P_OTP_LIC1 ((volatile uint32_t *)0xfe005064)
+#define P_OTP_LIC2 ((volatile uint32_t *)0xfe005068)
+#define P_OTP_LIC3 ((volatile uint32_t *)0xfe00506c)
+#define P_RNG_SEC_CONFIG_REG1 ((volatile uint32_t *)0xfe005104)
+#define P_RNG_SEC_CONFIG_REG2 ((volatile uint32_t *)0xfe005108)
+#define P_RNG_SEC_DATA ((volatile uint32_t *)0xfe005110)
+#define P_RNG_SEC_STS ((volatile uint32_t *)0xfe005114)
+#define P_RNG_USR_DATA ((volatile uint32_t *)0xfe005118)
+#define P_RNG_USR_STS ((volatile uint32_t *)0xfe00511c)
+#define P_KTE_SLOT0 ((volatile uint32_t *)0xfe005180)
+#define P_KTE_SLOT1 ((volatile uint32_t *)0xfe005184)
+#define P_KTE_SLOT2 ((volatile uint32_t *)0xfe005188)
+#define P_KTE_SLOT3 ((volatile uint32_t *)0xfe00518c)
+#define P_KTE_SLOT4 ((volatile uint32_t *)0xfe005190)
+#define P_KTE_SLOT5 ((volatile uint32_t *)0xfe005194)
+#define P_KTE_SLOT6 ((volatile uint32_t *)0xfe005198)
+#define P_KTE_SLOT7 ((volatile uint32_t *)0xfe00519c)
+#define P_MKL_TEE_RDY ((volatile uint32_t *)0xfe005200)
+#define P_MKL_TEE_CHK ((volatile uint32_t *)0xfe005204)
+#define P_MKL_TEE_CFG ((volatile uint32_t *)0xfe005208)
+#define P_MKL_TEE_EK ((volatile uint32_t *)0xfe005210)
+#define P_MKL_REE_RDY ((volatile uint32_t *)0xfe005280)
+#define P_MKL_REE_CHK ((volatile uint32_t *)0xfe005284)
+#define P_MKL_REE_CFG ((volatile uint32_t *)0xfe005288)
+#define P_MKL_REE_EK ((volatile uint32_t *)0xfe005290)
+//
+// Closing file: ../crypto/crypto_reg.h
+//
+//========================================================================
+// APB0_PWM_EF - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005400
+// -----------------------------------------------
+#define P_PWMEF_PWM_E ((volatile uint32_t *)0xfe005400)
+#define P_PWMEF_PWM_F ((volatile uint32_t *)0xfe005404)
+#define P_PWMEF_MISC_REG_EF ((volatile uint32_t *)0xfe005408)
+#define P_PWMEF_DELTA_SIGMA_EF ((volatile uint32_t *)0xfe00540c)
+#define P_PWMEF_TIME_EF ((volatile uint32_t *)0xfe005410)
+#define P_PWMEF_E2 ((volatile uint32_t *)0xfe005414)
+#define P_PWMEF_F2 ((volatile uint32_t *)0xfe005418)
+#define P_PWMEF_BLINK_EF ((volatile uint32_t *)0xfe00541c)
+#define P_PWMEF_LOCK_EF ((volatile uint32_t *)0xfe005420)
+//========================================================================
+// APB0_SYS_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005800
+// -----------------------------------------------
+#define P_SYSCTRL_METAL_REV0 ((volatile uint32_t *)0xfe005800)
+#define P_SYSCTRL_METAL_REV1 ((volatile uint32_t *)0xfe005804)
+//`define SYSCTRL_PROD_ENABLE 8'h0a
+#define P_SYSCTRL_CHIP_ID ((volatile uint32_t *)0xfe00582c)
+#define P_SYSCTRL_WRITEONCE1_REG0 ((volatile uint32_t *)0xfe005840)
+#define P_SYSCTRL_WRITEONCE1_STICKY_REG0 ((volatile uint32_t *)0xfe005844)
+#define P_SYSCTRL_WRITEONCE1_SEC_REG0 ((volatile uint32_t *)0xfe005848)
+#define P_SYSCTRL_WRITEONCE1_STICKY_SEC_REG0 ((volatile uint32_t *)0xfe00584c)
+#define P_SYSCTRL_WRITEONCE_REG0 ((volatile uint32_t *)0xfe005850)
+#define P_SYSCTRL_WRITEONCE_REG1 ((volatile uint32_t *)0xfe005854)
+#define P_SYSCTRL_WRITEONCE_SEC_REG0 ((volatile uint32_t *)0xfe005858)
+#define P_SYSCTRL_WRITEONCE_STICKY_REG0 ((volatile uint32_t *)0xfe00585c)
+#define P_SYSCTRL_WRITEONCE_STICKY_REG1 ((volatile uint32_t *)0xfe005860)
+#define P_SYSCTRL_WRITEONCE_STICKY_SEC_REG0 ((volatile uint32_t *)0xfe005864)
+#define P_SYSCTRL_TIMERA_CTRL ((volatile uint32_t *)0xfe0058c0)
+#define P_SYSCTRL_TIMERA ((volatile uint32_t *)0xfe0058c4)
+#define P_SYSCTRL_TIMERB_CTRL ((volatile uint32_t *)0xfe0058c8)
+#define P_SYSCTRL_TIMERB ((volatile uint32_t *)0xfe0058cc)
+#define P_SYSCTRL_TIMERC_CTRL ((volatile uint32_t *)0xfe0058d0)
+#define P_SYSCTRL_TIMERC ((volatile uint32_t *)0xfe0058d4)
+#define P_SYSCTRL_TIMERD_CTRL ((volatile uint32_t *)0xfe0058d8)
+#define P_SYSCTRL_TIMERD ((volatile uint32_t *)0xfe0058dc)
+#define P_SYSCTRL_SEC_TIMERA_CTRL ((volatile uint32_t *)0xfe0058e0)
+#define P_SYSCTRL_SEC_TIMERA ((volatile uint32_t *)0xfe0058e4)
+#define P_SYSCTRL_TIMERE_CTRL ((volatile uint32_t *)0xfe005900)
+#define P_SYSCTRL_TIMERE ((volatile uint32_t *)0xfe005904)
+#define P_SYSCTRL_TIMERE_HI ((volatile uint32_t *)0xfe005908)
+#define P_SYSCTRL_TIMERF_CTRL ((volatile uint32_t *)0xfe00590c)
+#define P_SYSCTRL_TIMERF ((volatile uint32_t *)0xfe005910)
+#define P_SYSCTRL_TIMERF_HI ((volatile uint32_t *)0xfe005914)
+#define P_SYSCTRL_SEC_TIMERE_CTRL ((volatile uint32_t *)0xfe005918)
+#define P_SYSCTRL_SEC_TIMERE ((volatile uint32_t *)0xfe00591c)
+#define P_SYSCTRL_SEC_TIMERE_HI ((volatile uint32_t *)0xfe005920)
+#define P_SYSCTRL_OSC_RING_CTRL0 ((volatile uint32_t *)0xfe005940)
+#define P_SYSCTRL_SEC_DDR_AXI_SEL ((volatile uint32_t *)0xfe005944)
+#define P_SYSCTRL_AM2AXI_CTRL0 ((volatile uint32_t *)0xfe005948)
+#define P_SYSCTRL_AM2AXI_STS ((volatile uint32_t *)0xfe00594c)
+#define P_SYSCTRL_POC ((volatile uint32_t *)0xfe005980)
+//`define SYSCTRL_PROD_PWD_VALUE0 8'h80
+//`define SYSCTRL_PROD_PWD_VALUE1 8'h81
+//`define SYSCTRL_PROD_PWD_VALUE2 8'h82
+//`define SYSCTRL_PROD_PWD_VALUE3 8'h83
+//`define SYSCTRL_PROD_STATUS 8'h84
+#define P_SYSCTRL_DEBUG_REG0 ((volatile uint32_t *)0xfe005a40)
+#define P_SYSCTRL_DEBUG_REG1 ((volatile uint32_t *)0xfe005a44)
+#define P_SYSCTRL_DEBUG_REG2 ((volatile uint32_t *)0xfe005a48)
+#define P_SYSCTRL_DEBUG_REG3 ((volatile uint32_t *)0xfe005a4c)
+#define P_SYSCTRL_DEBUG_REG4 ((volatile uint32_t *)0xfe005a50)
+#define P_SYSCTRL_DEBUG_REG5 ((volatile uint32_t *)0xfe005a54)
+#define P_SYSCTRL_DEBUG_REG6 ((volatile uint32_t *)0xfe005a58)
+#define P_SYSCTRL_DEBUG_REG7 ((volatile uint32_t *)0xfe005a5c)
+#define P_SYSCTRL_STATUS_REG0 ((volatile uint32_t *)0xfe005a80)
+#define P_SYSCTRL_STATUS_REG1 ((volatile uint32_t *)0xfe005a84)
+#define P_SYSCTRL_STATUS_REG2 ((volatile uint32_t *)0xfe005a88)
+#define P_SYSCTRL_STATUS_REG3 ((volatile uint32_t *)0xfe005a8c)
+#define P_SYSCTRL_STATUS_REG4 ((volatile uint32_t *)0xfe005a90)
+#define P_SYSCTRL_STATUS_REG5 ((volatile uint32_t *)0xfe005a94)
+#define P_SYSCTRL_STATUS_REG6 ((volatile uint32_t *)0xfe005a98)
+#define P_SYSCTRL_STATUS_REG7 ((volatile uint32_t *)0xfe005a9c)
+#define P_SYSCTRL_STICKY_REG0 ((volatile uint32_t *)0xfe005ac0)
+#define P_SYSCTRL_STICKY_REG1 ((volatile uint32_t *)0xfe005ac4)
+#define P_SYSCTRL_STICKY_REG2 ((volatile uint32_t *)0xfe005ac8)
+#define P_SYSCTRL_STICKY_REG3 ((volatile uint32_t *)0xfe005acc)
+#define P_SYSCTRL_STICKY_REG4 ((volatile uint32_t *)0xfe005ad0)
+#define P_SYSCTRL_STICKY_REG5 ((volatile uint32_t *)0xfe005ad4)
+#define P_SYSCTRL_STICKY_REG6 ((volatile uint32_t *)0xfe005ad8)
+#define P_SYSCTRL_STICKY_REG7 ((volatile uint32_t *)0xfe005adc)
+#define P_SYSCTRL_SEC_STATUS_REG0 ((volatile uint32_t *)0xfe005b00)
+#define P_SYSCTRL_SEC_STATUS_REG1 ((volatile uint32_t *)0xfe005b04)
+#define P_SYSCTRL_SEC_STATUS_REG2 ((volatile uint32_t *)0xfe005b08)
+#define P_SYSCTRL_SEC_STATUS_REG3 ((volatile uint32_t *)0xfe005b0c)
+#define P_SYSCTRL_SEC_STATUS_REG4 ((volatile uint32_t *)0xfe005b10)
+#define P_SYSCTRL_SEC_STATUS_REG5 ((volatile uint32_t *)0xfe005b14)
+#define P_SYSCTRL_SEC_STATUS_REG6 ((volatile uint32_t *)0xfe005b18)
+#define P_SYSCTRL_SEC_STATUS_REG7 ((volatile uint32_t *)0xfe005b1c)
+#define P_SYSCTRL_SEC_STATUS_REG8 ((volatile uint32_t *)0xfe005b20)
+#define P_SYSCTRL_SEC_STATUS_REG9 ((volatile uint32_t *)0xfe005b24)
+#define P_SYSCTRL_SEC_STATUS_REG10 ((volatile uint32_t *)0xfe005b28)
+#define P_SYSCTRL_SEC_STATUS_REG11 ((volatile uint32_t *)0xfe005b2c)
+#define P_SYSCTRL_SEC_STATUS_REG12 ((volatile uint32_t *)0xfe005b30)
+#define P_SYSCTRL_SEC_STATUS_REG13 ((volatile uint32_t *)0xfe005b34)
+#define P_SYSCTRL_SEC_STATUS_REG14 ((volatile uint32_t *)0xfe005b38)
+#define P_SYSCTRL_SEC_STATUS_REG15 ((volatile uint32_t *)0xfe005b3c)
+#define P_SYSCTRL_SEC_STATUS_REG16 ((volatile uint32_t *)0xfe005b40)
+#define P_SYSCTRL_SEC_STATUS_REG17 ((volatile uint32_t *)0xfe005b44)
+#define P_SYSCTRL_SEC_STATUS_REG18 ((volatile uint32_t *)0xfe005b48)
+#define P_SYSCTRL_SEC_STATUS_REG19 ((volatile uint32_t *)0xfe005b4c)
+#define P_SYSCTRL_SEC_STATUS_REG20 ((volatile uint32_t *)0xfe005b50)
+#define P_SYSCTRL_SEC_STATUS_REG21 ((volatile uint32_t *)0xfe005b54)
+#define P_SYSCTRL_SEC_STATUS_REG22 ((volatile uint32_t *)0xfe005b58)
+#define P_SYSCTRL_SEC_STATUS_REG23 ((volatile uint32_t *)0xfe005b5c)
+#define P_SYSCTRL_SEC_STICKY_REG0 ((volatile uint32_t *)0xfe005b80)
+#define P_SYSCTRL_SEC_STICKY_REG1 ((volatile uint32_t *)0xfe005b84)
+#define P_SYSCTRL_SEC_STICKY_REG2 ((volatile uint32_t *)0xfe005b88)
+#define P_SYSCTRL_SEC_STICKY_REG3 ((volatile uint32_t *)0xfe005b8c)
+#define P_SYSCTRL_SEC_STICKY_REG4 ((volatile uint32_t *)0xfe005b90)
+#define P_SYSCTRL_SEC_STICKY_REG5 ((volatile uint32_t *)0xfe005b94)
+#define P_SYSCTRL_SEC_STICKY_REG6 ((volatile uint32_t *)0xfe005b98)
+#define P_SYSCTRL_SEC_STICKY_REG7 ((volatile uint32_t *)0xfe005b9c)
+#define P_SYSCTRL_MSG_INDEX0_STICKY ((volatile uint32_t *)0xfe005bc0)
+#define P_SYSCTRL_MSG_INDEX1_STICKY ((volatile uint32_t *)0xfe005bc4)
+#define P_SYSCTRL_MSG_INDEX2_STICKY ((volatile uint32_t *)0xfe005bc8)
+#define P_SYSCTRL_MSG_INDEX3_STICKY ((volatile uint32_t *)0xfe005bcc)
+//========================================================================
+// APB0_I2C_M_B - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005c00
+// -----------------------------------------------
+#define P_I2C_M_B_CONTROL_REG ((volatile uint32_t *)0xfe005c00)
+#define P_I2C_M_B_SLAVE_ADDR ((volatile uint32_t *)0xfe005c04)
+#define P_I2C_M_B_TOKEN_LIST0 ((volatile uint32_t *)0xfe005c08)
+#define P_I2C_M_B_TOKEN_LIST1 ((volatile uint32_t *)0xfe005c0c)
+#define P_I2C_M_B_WDATA_REG0 ((volatile uint32_t *)0xfe005c10)
+#define P_I2C_M_B_WDATA_REG1 ((volatile uint32_t *)0xfe005c14)
+#define P_I2C_M_B_RDATA_REG0 ((volatile uint32_t *)0xfe005c18)
+#define P_I2C_M_B_RDATA_REG1 ((volatile uint32_t *)0xfe005c1c)
+#define P_I2C_M_B_TIMEOUT_TH ((volatile uint32_t *)0xfe005c20)
+//========================================================================
+// APB0_DMA - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006000
+// -----------------------------------------------
+//TODO
+//========================================================================
+// APB0_IRQ_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006400
+// -----------------------------------------------
+#define P_IRQCTRL_IRQOUT_MASK0 ((volatile uint32_t *)0xfe006400)
+#define P_IRQCTRL_IRQOUT_MASK1 ((volatile uint32_t *)0xfe006404)
+#define P_IRQCTRL_IRQOUT_MASK2 ((volatile uint32_t *)0xfe006408)
+#define P_IRQCTRL_IRQOUT_MASK3 ((volatile uint32_t *)0xfe00640c)
+#define P_IRQCTRL_IRQOUT_INV0 ((volatile uint32_t *)0xfe006440)
+#define P_IRQCTRL_IRQOUT_INV1 ((volatile uint32_t *)0xfe006444)
+#define P_IRQCTRL_IRQOUT_INV2 ((volatile uint32_t *)0xfe006448)
+#define P_IRQCTRL_IRQOUT_INV3 ((volatile uint32_t *)0xfe00644c)
+//`define APB0_IRQIN_MASK0_CLK_USB 8'h00
+//`define APB0_IRQIN_MASK0_CLK_CPU 8'h01
+//`define APB0_IRQIN_MASK0_CLK_SYS 8'h02
+//`define APB0_IRQIN_MASK1_CLK_SYS 8'h03
+//`define APB0_IRQIN_MASK0_CLK_DSPA 8'h04
+//`define APB0_IRQIN_MASK0_CLK_DSPB 8'h05
+//`define APB0_IRQIN_CLRLVL_CLK_USB 8'h10
+//`define APB0_IRQIN_CLRLVL_CLK_DSPA 8'h11
+//`define APB0_IRQIN_CLRLVL_CLK_DSPB 8'h12
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006800
+// -----------------------------------------------
+#define P_I2C_M_C_CONTROL_REG ((volatile uint32_t *)0xfe006800)
+#define P_I2C_M_C_SLAVE_ADDR ((volatile uint32_t *)0xfe006804)
+#define P_I2C_M_C_TOKEN_LIST0 ((volatile uint32_t *)0xfe006808)
+#define P_I2C_M_C_TOKEN_LIST1 ((volatile uint32_t *)0xfe00680c)
+#define P_I2C_M_C_WDATA_REG0 ((volatile uint32_t *)0xfe006810)
+#define P_I2C_M_C_WDATA_REG1 ((volatile uint32_t *)0xfe006814)
+#define P_I2C_M_C_RDATA_REG0 ((volatile uint32_t *)0xfe006818)
+#define P_I2C_M_C_RDATA_REG1 ((volatile uint32_t *)0xfe00681c)
+#define P_I2C_M_C_TIMEOUT_TH ((volatile uint32_t *)0xfe006820)
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006c00
+// -----------------------------------------------
+#define P_I2C_M_D_CONTROL_REG ((volatile uint32_t *)0xfe006c00)
+#define P_I2C_M_D_SLAVE_ADDR ((volatile uint32_t *)0xfe006c04)
+#define P_I2C_M_D_TOKEN_LIST0 ((volatile uint32_t *)0xfe006c08)
+#define P_I2C_M_D_TOKEN_LIST1 ((volatile uint32_t *)0xfe006c0c)
+#define P_I2C_M_D_WDATA_REG0 ((volatile uint32_t *)0xfe006c10)
+#define P_I2C_M_D_WDATA_REG1 ((volatile uint32_t *)0xfe006c14)
+#define P_I2C_M_D_RDATA_REG0 ((volatile uint32_t *)0xfe006c18)
+#define P_I2C_M_D_RDATA_REG1 ((volatile uint32_t *)0xfe006c1c)
+#define P_I2C_M_D_TIMEOUT_TH ((volatile uint32_t *)0xfe006c20)
+//========================================================================
+// APB0_UART_C - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007000
+// -----------------------------------------------
+#define P_UART_C_WFIFO ((volatile uint32_t *)0xfe007000)
+#define P_UART_C_RFIFO ((volatile uint32_t *)0xfe007004)
+#define P_UART_C_CONTROL ((volatile uint32_t *)0xfe007008)
+#define P_UART_C_STATUS ((volatile uint32_t *)0xfe00700c)
+#define P_UART_C_MISC ((volatile uint32_t *)0xfe007010)
+#define P_UART_C_REG5 ((volatile uint32_t *)0xfe007014)
+//========================================================================
+// APB0_PWR_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007800
+// -----------------------------------------------
+#define P_PWRCTRL_PWR_ACK0 ((volatile uint32_t *)0xfe007800)
+#define P_PWRCTRL_ISO_EN0 ((volatile uint32_t *)0xfe007804)
+#define P_PWRCTRL_PWR_OFF0 ((volatile uint32_t *)0xfe007808)
+#define P_PWRCTRL_SAVE_EN0 ((volatile uint32_t *)0xfe00780c)
+#define P_PWRCTRL_RESTORE_EN0 ((volatile uint32_t *)0xfe007810)
+#define P_PWRCTRL_MEM_PD0 ((volatile uint32_t *)0xfe007840)
+#define P_PWRCTRL_MEM_PD1 ((volatile uint32_t *)0xfe007844)
+#define P_PWRCTRL_MEM_PD2 ((volatile uint32_t *)0xfe007848)
+#define P_PWRCTRL_MEM_PD3 ((volatile uint32_t *)0xfe00784c)
+#define P_PWRCTRL_MEM_PD4 ((volatile uint32_t *)0xfe007850)
+#define P_PWRCTRL_R_ISO_EN0 ((volatile uint32_t *)0xfe007880)
+#define P_PWRCTRL_R_PWR_OFF0 ((volatile uint32_t *)0xfe007884)
+#define P_PWRCTRL_R_MEM_PD0 ((volatile uint32_t *)0xfe007888)
+#define P_PWRCTRL_R_MEM_PD1 ((volatile uint32_t *)0xfe00788c)
+#define P_PWRCTRL_R_MEM_PD2 ((volatile uint32_t *)0xfe007890)
+#define P_PWRCTRL_R_MEM_PD3 ((volatile uint32_t *)0xfe007894)
+#define P_PWRCTRL_R_MEM_PD4 ((volatile uint32_t *)0xfe007898)
+//`define PWRCTRL_MEM_PD_DSPA 8'h10
+//`define PWRCTRL_MEM_PD_DSPB 8'h11
+//`define PWRCTRL_MEM_PD_RAMA 8'h12
+//`define PWRCTRL_MEM_PD_RAMB 8'h13
+//`define PWRCTRL_MEM_PD_CPU 8'h14
+//`define PWRCTRL_MEM_PD_AUDIO 8'h20
+//`define PWRCTRL_MEM_PD_USBCTRL 8'h21
+//`define PWRCTRL_MEM_PD_SPICC 8'h22
+//`define PWRCTRL_MEM_PD_SPIFC 8'h23
+//`define PWRCTRL_MEM_PD_IR 8'h24
+//`define PWRCTRL_MEM_PD_SDIO 8'h25
+//`define PWRCTRL_MEM_PD_KLEFUSE 8'h26
+//`define PWRCTRL_MEM_PD_PSRAM 8'h27
+//`define PWRCTRL_MEM_PD_DDR 8'h28
+//`define PWRCTRL_MEM_PD_DMC 8'h29
+#define P_PWRCTRL_AUTO_OFF_CTRL ((volatile uint32_t *)0xfe0078c0)
+#define P_PWRCTRL_AUTO_OFF ((volatile uint32_t *)0xfe0078c4)
+#define P_PWRCTRL_AUTO_OFF_STS ((volatile uint32_t *)0xfe0078c8)
+#define P_PWRCTRL_TIMER_TH_01 ((volatile uint32_t *)0xfe0078cc)
+#define P_PWRCTRL_TIMER_TH_23 ((volatile uint32_t *)0xfe0078d0)
+#define P_PWRCTRL_TIMER_TH_45 ((volatile uint32_t *)0xfe0078d4)
+#define P_PWRCTRL_TIMER_TH_67 ((volatile uint32_t *)0xfe0078d8)
+#define P_PWRCTRL_MASK_PWR_ACK0 ((volatile uint32_t *)0xfe007900)
+#define P_PWRCTRL_MASK_RSTN_OFF0 ((volatile uint32_t *)0xfe007904)
+#define P_PWRCTRL_MASK_RSTN_ON0 ((volatile uint32_t *)0xfe007908)
+#define P_PWRCTRL_MASK_PWR_OFF0 ((volatile uint32_t *)0xfe00790c)
+#define P_PWRCTRL_MASK_PWR_ON0 ((volatile uint32_t *)0xfe007910)
+#define P_PWRCTRL_MASK_ISO_OFF0 ((volatile uint32_t *)0xfe007914)
+#define P_PWRCTRL_MASK_ISO_ON0 ((volatile uint32_t *)0xfe007918)
+#define P_PWRCTRL_MASK_MEM_OFF0 ((volatile uint32_t *)0xfe007940)
+#define P_PWRCTRL_MASK_MEM_OFF1 ((volatile uint32_t *)0xfe007944)
+#define P_PWRCTRL_MASK_MEM_OFF2 ((volatile uint32_t *)0xfe007948)
+#define P_PWRCTRL_MASK_MEM_OFF3 ((volatile uint32_t *)0xfe00794c)
+#define P_PWRCTRL_MASK_MEM_OFF4 ((volatile uint32_t *)0xfe007950)
+#define P_PWRCTRL_MASK_MEM_ON0 ((volatile uint32_t *)0xfe007960)
+#define P_PWRCTRL_MASK_MEM_ON1 ((volatile uint32_t *)0xfe007964)
+#define P_PWRCTRL_MASK_MEM_ON2 ((volatile uint32_t *)0xfe007968)
+#define P_PWRCTRL_MASK_MEM_ON3 ((volatile uint32_t *)0xfe00796c)
+#define P_PWRCTRL_MASK_MEM_ON4 ((volatile uint32_t *)0xfe007970)
+//========================================================================
+// APB0_ANA_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007c00
+// -----------------------------------------------
+#define P_ANACTRL_FIXPLL_CTRL0 ((volatile uint32_t *)0xfe007c80)
+#define P_ANACTRL_FIXPLL_CTRL1 ((volatile uint32_t *)0xfe007c84)
+#define P_ANACTRL_FIXPLL_CTRL2 ((volatile uint32_t *)0xfe007c88)
+#define P_ANACTRL_FIXPLL_CTRL3 ((volatile uint32_t *)0xfe007c8c)
+#define P_ANACTRL_FIXPLL_CTRL4 ((volatile uint32_t *)0xfe007c90)
+#define P_ANACTRL_FIXPLL_STS ((volatile uint32_t *)0xfe007c94)
+#define P_ANACTRL_SYSPLL_CTRL0 ((volatile uint32_t *)0xfe007d00)
+#define P_ANACTRL_SYSPLL_CTRL1 ((volatile uint32_t *)0xfe007d04)
+#define P_ANACTRL_SYSPLL_CTRL2 ((volatile uint32_t *)0xfe007d08)
+#define P_ANACTRL_SYSPLL_CTRL3 ((volatile uint32_t *)0xfe007d0c)
+#define P_ANACTRL_SYSPLL_CTRL4 ((volatile uint32_t *)0xfe007d10)
+#define P_ANACTRL_SYSPLL_STS ((volatile uint32_t *)0xfe007d14)
+#define P_ANACTRL_HIFIPLL_CTRL0 ((volatile uint32_t *)0xfe007d40)
+#define P_ANACTRL_HIFIPLL_CTRL1 ((volatile uint32_t *)0xfe007d44)
+#define P_ANACTRL_HIFIPLL_CTRL2 ((volatile uint32_t *)0xfe007d48)
+#define P_ANACTRL_HIFIPLL_CTRL3 ((volatile uint32_t *)0xfe007d4c)
+#define P_ANACTRL_HIFIPLL_CTRL4 ((volatile uint32_t *)0xfe007d50)
+#define P_ANACTRL_HIFIPLL_STS ((volatile uint32_t *)0xfe007d54)
+#define P_ANACTRL_AUDDDS_CTRL0 ((volatile uint32_t *)0xfe007d80)
+#define P_ANACTRL_AUDDDS_CTRL1 ((volatile uint32_t *)0xfe007d84)
+#define P_ANACTRL_AUDDDS_CTRL2 ((volatile uint32_t *)0xfe007d88)
+#define P_ANACTRL_AUDDDS_CTRL3 ((volatile uint32_t *)0xfe007d8c)
+#define P_ANACTRL_AUDDDS_CTRL4 ((volatile uint32_t *)0xfe007d90)
+#define P_ANACTRL_AUDDDS_STS ((volatile uint32_t *)0xfe007d94)
+#define P_ANACTRL_MISCTOP_CTRL0 ((volatile uint32_t *)0xfe007dc0)
+#define P_ANACTRL_POR_CNTL ((volatile uint32_t *)0xfe007e08)
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe020000
+// -----------------------------------------------
+#define P_RSA_BASE ((volatile uint32_t *)0xfe020000)
+//========================================================================
+// CPUCTRL_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd000000
+// -----------------------------------------------
+#define P_CPUCTRL_CTRL0 ((volatile uint32_t *)0xfd000000)
+#define P_CPUCTRL_CTRL1 ((volatile uint32_t *)0xfd000004)
+#define P_CPUCTRL_CTRL2 ((volatile uint32_t *)0xfd000008)
+#define P_CPUCTRL_CTRL3 ((volatile uint32_t *)0xfd00000c)
+#define P_CPUCTRL_CTRL4 ((volatile uint32_t *)0xfd000010)
+#define P_CPUCTRL_CTRL5 ((volatile uint32_t *)0xfd000014)
+#define P_CPUCTRL_CTRL6 ((volatile uint32_t *)0xfd000018)
+#define P_CPUCTRL_CTRL7 ((volatile uint32_t *)0xfd00001c)
+#define P_CPUCTRL_CTRL8 ((volatile uint32_t *)0xfd000020)
+#define P_CPUCTRL_CTRL9 ((volatile uint32_t *)0xfd000024)
+#define P_CPUCTRL_CTRL10 ((volatile uint32_t *)0xfd000028)
+#define P_CPUCTRL_CTRL11 ((volatile uint32_t *)0xfd00002c)
+#define P_CPUCTRL_CTRL12 ((volatile uint32_t *)0xfd000030)
+#define P_CPUCTRL_CTRL13 ((volatile uint32_t *)0xfd000034)
+#define P_CPUCTRL_CTRL14 ((volatile uint32_t *)0xfd000038)
+#define P_CPUCTRL_CTRL15 ((volatile uint32_t *)0xfd00003c)
+#define P_CPUCTRL_STS0 ((volatile uint32_t *)0xfd000040)
+#define P_CPUCTRL_STS1 ((volatile uint32_t *)0xfd000044)
+#define P_CPUCTRL_STS2 ((volatile uint32_t *)0xfd000048)
+#define P_CPUCTRL_STS3 ((volatile uint32_t *)0xfd00004c)
+#define P_CPUCTRL_STS4 ((volatile uint32_t *)0xfd000050)
+#define P_CPUCTRL_STS5 ((volatile uint32_t *)0xfd000054)
+#define P_CPUCTRL_STS6 ((volatile uint32_t *)0xfd000058)
+#define P_CPUCTRL_STS7 ((volatile uint32_t *)0xfd00005c)
+#define P_CPUCTRL_STS8 ((volatile uint32_t *)0xfd000060)
+#define P_CPUCTRL_STS9 ((volatile uint32_t *)0xfd000064)
+#define P_CPUCTRL_CLK_CTRL0 ((volatile uint32_t *)0xfd000080)
+#define P_CPUCTRL_CLK_CTRL1 ((volatile uint32_t *)0xfd000084)
+#define P_CPUCTRL_CLK_CTRL2 ((volatile uint32_t *)0xfd000088)
+#define P_CPUCTRL_CLK_CTRL3 ((volatile uint32_t *)0xfd00008c)
+#define P_CPUCTRL_CLK_CTRL4 ((volatile uint32_t *)0xfd000090)
+#define P_CPUCTRL_CLK_CTRL5 ((volatile uint32_t *)0xfd000094)
+#define P_CPUCTRL_CLK_CTRL6 ((volatile uint32_t *)0xfd000098)
+#define P_CPUCTRL_CLK_CTRL7 ((volatile uint32_t *)0xfd00009c)
+#define P_CPUCTRL_RESET_CTRL ((volatile uint32_t *)0xfd0000c0)
+#define P_CPUCTRL_ROM_DISABLE ((volatile uint32_t *)0xfd0000c4)
+//========================================================================
+// RAMA_SEC_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd000800
+// -----------------------------------------------
+#define P_SRAM_RANGE0_STA ((volatile uint32_t *)0xfd000800)
+#define P_SRAM_RANGE1_STA ((volatile uint32_t *)0xfd000804)
+#define P_SRAM_RANGE2_STA ((volatile uint32_t *)0xfd000808)
+#define P_SRAM_RANGE3_STA ((volatile uint32_t *)0xfd00080c)
+#define P_SRAM_RANGE4_STA ((volatile uint32_t *)0xfd000810)
+#define P_SRAM_RANGE5_STA ((volatile uint32_t *)0xfd000814)
+#define P_SRAM_RANGE6_STA ((volatile uint32_t *)0xfd000818)
+#define P_SRAM_RANGE0_EDA ((volatile uint32_t *)0xfd00081c)
+#define P_SRAM_RANGE1_EDA ((volatile uint32_t *)0xfd000820)
+#define P_SRAM_RANGE2_EDA ((volatile uint32_t *)0xfd000824)
+#define P_SRAM_RANGE3_EDA ((volatile uint32_t *)0xfd000828)
+#define P_SRAM_RANGE4_EDA ((volatile uint32_t *)0xfd00082c)
+#define P_SRAM_RANGE5_EDA ((volatile uint32_t *)0xfd000830)
+#define P_SRAM_RANGE6_EDA ((volatile uint32_t *)0xfd000834)
+#define P_SRAM_RANGE0_CTRL0 ((volatile uint32_t *)0xfd000838)
+#define P_SRAM_RANGE1_CTRL0 ((volatile uint32_t *)0xfd00083c)
+#define P_SRAM_RANGE2_CTRL0 ((volatile uint32_t *)0xfd000840)
+#define P_SRAM_RANGE3_CTRL0 ((volatile uint32_t *)0xfd000844)
+#define P_SRAM_RANGE4_CTRL0 ((volatile uint32_t *)0xfd000848)
+#define P_SRAM_RANGE5_CTRL0 ((volatile uint32_t *)0xfd00084c)
+#define P_SRAM_RANGE6_CTRL0 ((volatile uint32_t *)0xfd000850)
+#define P_SRAM_RANGE7_CTRL0 ((volatile uint32_t *)0xfd000854)
+#define P_SRAM_RANGE0_CTRL1 ((volatile uint32_t *)0xfd000858)
+#define P_SRAM_RANGE1_CTRL1 ((volatile uint32_t *)0xfd00085c)
+#define P_SRAM_RANGE2_CTRL1 ((volatile uint32_t *)0xfd000860)
+#define P_SRAM_RANGE3_CTRL1 ((volatile uint32_t *)0xfd000864)
+#define P_SRAM_RANGE4_CTRL1 ((volatile uint32_t *)0xfd000868)
+#define P_SRAM_RANGE5_CTRL1 ((volatile uint32_t *)0xfd00086c)
+#define P_SRAM_RANGE6_CTRL1 ((volatile uint32_t *)0xfd000870)
+#define P_SRAM_RANGE7_CTRL1 ((volatile uint32_t *)0xfd000874)
+#define P_SRAM_SEC_CTRL0 ((volatile uint32_t *)0xfd000878)
+#define P_SRAM_REG_LOCK ((volatile uint32_t *)0xfd00087c)
+//========================================================================
+// RAMB_SEC_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd000c00
+// -----------------------------------------------
+#define P_SRAM_RANGE0_STA_B ((volatile uint32_t *)0xfd000c00)
+#define P_SRAM_RANGE1_STA_B ((volatile uint32_t *)0xfd000c04)
+#define P_SRAM_RANGE2_STA_B ((volatile uint32_t *)0xfd000c08)
+#define P_SRAM_RANGE3_STA_B ((volatile uint32_t *)0xfd000c0c)
+#define P_SRAM_RANGE4_STA_B ((volatile uint32_t *)0xfd000c10)
+#define P_SRAM_RANGE5_STA_B ((volatile uint32_t *)0xfd000c14)
+#define P_SRAM_RANGE6_STA_B ((volatile uint32_t *)0xfd000c18)
+#define P_SRAM_RANGE0_EDA_B ((volatile uint32_t *)0xfd000c1c)
+#define P_SRAM_RANGE1_EDA_B ((volatile uint32_t *)0xfd000c20)
+#define P_SRAM_RANGE2_EDA_B ((volatile uint32_t *)0xfd000c24)
+#define P_SRAM_RANGE3_EDA_B ((volatile uint32_t *)0xfd000c28)
+#define P_SRAM_RANGE4_EDA_B ((volatile uint32_t *)0xfd000c2c)
+#define P_SRAM_RANGE5_EDA_B ((volatile uint32_t *)0xfd000c30)
+#define P_SRAM_RANGE6_EDA_B ((volatile uint32_t *)0xfd000c34)
+#define P_SRAM_RANGE0_CTRL0_B ((volatile uint32_t *)0xfd000c38)
+#define P_SRAM_RANGE1_CTRL0_B ((volatile uint32_t *)0xfd000c3c)
+#define P_SRAM_RANGE2_CTRL0_B ((volatile uint32_t *)0xfd000c40)
+#define P_SRAM_RANGE3_CTRL0_B ((volatile uint32_t *)0xfd000c44)
+#define P_SRAM_RANGE4_CTRL0_B ((volatile uint32_t *)0xfd000c48)
+#define P_SRAM_RANGE5_CTRL0_B ((volatile uint32_t *)0xfd000c4c)
+#define P_SRAM_RANGE6_CTRL0_B ((volatile uint32_t *)0xfd000c50)
+#define P_SRAM_RANGE7_CTRL0_B ((volatile uint32_t *)0xfd000c54)
+#define P_SRAM_RANGE0_CTRL1_B ((volatile uint32_t *)0xfd000c58)
+#define P_SRAM_RANGE1_CTRL1_B ((volatile uint32_t *)0xfd000c5c)
+#define P_SRAM_RANGE2_CTRL1_B ((volatile uint32_t *)0xfd000c60)
+#define P_SRAM_RANGE3_CTRL1_B ((volatile uint32_t *)0xfd000c64)
+#define P_SRAM_RANGE4_CTRL1_B ((volatile uint32_t *)0xfd000c68)
+#define P_SRAM_RANGE5_CTRL1_B ((volatile uint32_t *)0xfd000c6c)
+#define P_SRAM_RANGE6_CTRL1_B ((volatile uint32_t *)0xfd000c70)
+#define P_SRAM_RANGE7_CTRL1_B ((volatile uint32_t *)0xfd000c74)
+#define P_SRAM_SEC_CTRL0_B ((volatile uint32_t *)0xfd000c78)
+#define P_SRAM_REG_LOCK_B ((volatile uint32_t *)0xfd000c7c)
+//
+// Reading file: REG_LIST_DSP_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//========================================================================
+// DSPA - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe030000
+// -----------------------------------------------
+#define P_DSP_CFG0 ((volatile uint32_t *)0xfe030000)
+#define P_DSP_CFG1 ((volatile uint32_t *)0xfe030004)
+#define P_DSP_CFG2 ((volatile uint32_t *)0xfe030008)
+#define P_DSP_IMPWIRE ((volatile uint32_t *)0xfe03000c)
+#define P_DSP_RESET_VEC ((volatile uint32_t *)0xfe030010)
+#define P_DSP_SEC_CFG0 ((volatile uint32_t *)0xfe030018)
+#define P_DSP_SEC_CFG1 ((volatile uint32_t *)0xfe03001c)
+#define P_DSP_IRQ_CTRL0 ((volatile uint32_t *)0xfe030040)
+#define P_DSP_IRQ_CTRL1 ((volatile uint32_t *)0xfe030044)
+#define P_DSP_IRQ_CTRL2 ((volatile uint32_t *)0xfe030048)
+#define P_DSP_IRQ_CTRL3 ((volatile uint32_t *)0xfe03004c)
+#define P_DSP_IRQ_CTRL4 ((volatile uint32_t *)0xfe030050)
+#define P_DSP_IRQ_CTRL5 ((volatile uint32_t *)0xfe030054)
+#define P_DSP_IRQ_CTRL6 ((volatile uint32_t *)0xfe030058)
+#define P_DSP_IRQ_CTRL7 ((volatile uint32_t *)0xfe03005c)
+#define P_DSP_IRQ_CTRL8 ((volatile uint32_t *)0xfe030060)
+#define P_DSP_IRQ_STS ((volatile uint32_t *)0xfe03007c)
+#define P_DSP_REMAP0 ((volatile uint32_t *)0xfe030080)
+#define P_DSP_REMAP1 ((volatile uint32_t *)0xfe030084)
+#define P_DSP_REMAP2 ((volatile uint32_t *)0xfe030088)
+#define P_DSP_STS0 ((volatile uint32_t *)0xfe030100)
+#define P_DSP_STS1 ((volatile uint32_t *)0xfe030104)
+#define P_DSP_STS2 ((volatile uint32_t *)0xfe030108)
+#define P_DSP_STS3 ((volatile uint32_t *)0xfe03010c)
+#define P_DSP_STS4 ((volatile uint32_t *)0xfe030110)
+#define P_DSP_STS5 ((volatile uint32_t *)0xfe030114)
+#define P_DSP_MAILBOX_SET_0 ((volatile uint32_t *)0xfe030140)
+#define P_DSP_MAILBOX_SET_1 ((volatile uint32_t *)0xfe030144)
+#define P_DSP_MAILBOX_SET_2 ((volatile uint32_t *)0xfe030148)
+#define P_DSP_MAILBOX_SET_3 ((volatile uint32_t *)0xfe03014c)
+#define P_DSP_MAILBOX_SET_4 ((volatile uint32_t *)0xfe030150)
+#define P_DSP_MAILBOX_SET_5 ((volatile uint32_t *)0xfe030154)
+#define P_DSP_MAILBOX_SET_6 ((volatile uint32_t *)0xfe030158)
+#define P_DSP_MAILBOX_SET_7 ((volatile uint32_t *)0xfe03015c)
+#define P_DSP_MAILBOX_SET_8 ((volatile uint32_t *)0xfe030160)
+#define P_DSP_MAILBOX_SET_9 ((volatile uint32_t *)0xfe030164)
+#define P_DSP_MAILBOX_SET_10 ((volatile uint32_t *)0xfe030168)
+#define P_DSP_MAILBOX_SET_11 ((volatile uint32_t *)0xfe03016c)
+#define P_DSP_MAILBOX_CLR_0 ((volatile uint32_t *)0xfe030180)
+#define P_DSP_MAILBOX_CLR_1 ((volatile uint32_t *)0xfe030184)
+#define P_DSP_MAILBOX_CLR_2 ((volatile uint32_t *)0xfe030188)
+#define P_DSP_MAILBOX_CLR_3 ((volatile uint32_t *)0xfe03018c)
+#define P_DSP_MAILBOX_CLR_4 ((volatile uint32_t *)0xfe030190)
+#define P_DSP_MAILBOX_CLR_5 ((volatile uint32_t *)0xfe030194)
+#define P_DSP_MAILBOX_CLR_6 ((volatile uint32_t *)0xfe030198)
+#define P_DSP_MAILBOX_CLR_7 ((volatile uint32_t *)0xfe03019c)
+#define P_DSP_MAILBOX_CLR_8 ((volatile uint32_t *)0xfe0301a0)
+#define P_DSP_MAILBOX_CLR_9 ((volatile uint32_t *)0xfe0301a4)
+#define P_DSP_MAILBOX_CLR_10 ((volatile uint32_t *)0xfe0301a8)
+#define P_DSP_MAILBOX_CLR_11 ((volatile uint32_t *)0xfe0301ac)
+#define P_DSP_MAILBOX_STAT_0 ((volatile uint32_t *)0xfe0301c0)
+#define P_DSP_MAILBOX_STAT_1 ((volatile uint32_t *)0xfe0301c4)
+#define P_DSP_MAILBOX_STAT_2 ((volatile uint32_t *)0xfe0301c8)
+#define P_DSP_MAILBOX_STAT_3 ((volatile uint32_t *)0xfe0301cc)
+#define P_DSP_MAILBOX_STAT_4 ((volatile uint32_t *)0xfe0301d0)
+#define P_DSP_MAILBOX_STAT_5 ((volatile uint32_t *)0xfe0301d4)
+#define P_DSP_MAILBOX_STAT_6 ((volatile uint32_t *)0xfe0301d8)
+#define P_DSP_MAILBOX_STAT_7 ((volatile uint32_t *)0xfe0301dc)
+#define P_DSP_MAILBOX_STAT_8 ((volatile uint32_t *)0xfe0301e0)
+#define P_DSP_MAILBOX_STAT_9 ((volatile uint32_t *)0xfe0301e4)
+#define P_DSP_MAILBOX_STAT_10 ((volatile uint32_t *)0xfe0301e8)
+#define P_DSP_MAILBOX_STAT_11 ((volatile uint32_t *)0xfe0301ec)
+#define P_DSP_QIF_CTRL ((volatile uint32_t *)0xfe030200)
+#define P_DSP_QIF_STS ((volatile uint32_t *)0xfe030204)
+#define P_DSP_WRFIFO_TOCPUA ((volatile uint32_t *)0xfe030208)
+#define P_DSP_WRFIFO_TOCPUB ((volatile uint32_t *)0xfe03020c)
+#define P_DSP_WRFIFO_TODSP ((volatile uint32_t *)0xfe030210)
+#define P_DSP_RDFIFO_FRCPUA ((volatile uint32_t *)0xfe030220)
+#define P_DSP_RDFIFO_FRCPUB ((volatile uint32_t *)0xfe030224)
+#define P_DSP_RDFIFO_FRDSP ((volatile uint32_t *)0xfe030228)
+//========================================================================
+// DSPB - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe040000
+// -----------------------------------------------
+#define P_DSPB_CFG0 ((volatile uint32_t *)0xfe040000)
+#define P_DSPB_CFG1 ((volatile uint32_t *)0xfe040004)
+#define P_DSPB_CFG2 ((volatile uint32_t *)0xfe040008)
+#define P_DSPB_IMPWIRE ((volatile uint32_t *)0xfe04000c)
+#define P_DSPB_RESET_VEC ((volatile uint32_t *)0xfe040010)
+#define P_DSPB_SEC_CFG0 ((volatile uint32_t *)0xfe040018)
+#define P_DSPB_SEC_CFG1 ((volatile uint32_t *)0xfe04001c)
+#define P_DSPB_IRQ_CTRL0 ((volatile uint32_t *)0xfe040040)
+#define P_DSPB_IRQ_CTRL1 ((volatile uint32_t *)0xfe040044)
+#define P_DSPB_IRQ_CTRL2 ((volatile uint32_t *)0xfe040048)
+#define P_DSPB_IRQ_CTRL3 ((volatile uint32_t *)0xfe04004c)
+#define P_DSPB_IRQ_CTRL4 ((volatile uint32_t *)0xfe040050)
+#define P_DSPB_IRQ_CTRL5 ((volatile uint32_t *)0xfe040054)
+#define P_DSPB_IRQ_CTRL6 ((volatile uint32_t *)0xfe040058)
+#define P_DSPB_IRQ_CTRL7 ((volatile uint32_t *)0xfe04005c)
+#define P_DSPB_IRQ_CTRL8 ((volatile uint32_t *)0xfe040060)
+#define P_DSPB_IRQ_STS ((volatile uint32_t *)0xfe04007c)
+#define P_DSPB_REMAP0 ((volatile uint32_t *)0xfe040080)
+#define P_DSPB_REMAP1 ((volatile uint32_t *)0xfe040084)
+#define P_DSPB_REMAP2 ((volatile uint32_t *)0xfe040088)
+#define P_DSPB_STS0 ((volatile uint32_t *)0xfe040100)
+#define P_DSPB_STS1 ((volatile uint32_t *)0xfe040104)
+#define P_DSPB_STS2 ((volatile uint32_t *)0xfe040108)
+#define P_DSPB_STS3 ((volatile uint32_t *)0xfe04010c)
+#define P_DSPB_STS4 ((volatile uint32_t *)0xfe040110)
+#define P_DSPB_STS5 ((volatile uint32_t *)0xfe040114)
+#define P_DSPB_MAILBOX_SET_0 ((volatile uint32_t *)0xfe040140)
+#define P_DSPB_MAILBOX_SET_1 ((volatile uint32_t *)0xfe040144)
+#define P_DSPB_MAILBOX_SET_2 ((volatile uint32_t *)0xfe040148)
+#define P_DSPB_MAILBOX_SET_3 ((volatile uint32_t *)0xfe04014c)
+#define P_DSPB_MAILBOX_SET_4 ((volatile uint32_t *)0xfe040150)
+#define P_DSPB_MAILBOX_SET_5 ((volatile uint32_t *)0xfe040154)
+#define P_DSPB_MAILBOX_SET_6 ((volatile uint32_t *)0xfe040158)
+#define P_DSPB_MAILBOX_SET_7 ((volatile uint32_t *)0xfe04015c)
+#define P_DSPB_MAILBOX_SET_8 ((volatile uint32_t *)0xfe040160)
+#define P_DSPB_MAILBOX_SET_9 ((volatile uint32_t *)0xfe040164)
+#define P_DSPB_MAILBOX_SET_10 ((volatile uint32_t *)0xfe040168)
+#define P_DSPB_MAILBOX_SET_11 ((volatile uint32_t *)0xfe04016c)
+#define P_DSPB_MAILBOX_CLR_0 ((volatile uint32_t *)0xfe040180)
+#define P_DSPB_MAILBOX_CLR_1 ((volatile uint32_t *)0xfe040184)
+#define P_DSPB_MAILBOX_CLR_2 ((volatile uint32_t *)0xfe040188)
+#define P_DSPB_MAILBOX_CLR_3 ((volatile uint32_t *)0xfe04018c)
+#define P_DSPB_MAILBOX_CLR_4 ((volatile uint32_t *)0xfe040190)
+#define P_DSPB_MAILBOX_CLR_5 ((volatile uint32_t *)0xfe040194)
+#define P_DSPB_MAILBOX_CLR_6 ((volatile uint32_t *)0xfe040198)
+#define P_DSPB_MAILBOX_CLR_7 ((volatile uint32_t *)0xfe04019c)
+#define P_DSPB_MAILBOX_CLR_8 ((volatile uint32_t *)0xfe0401a0)
+#define P_DSPB_MAILBOX_CLR_9 ((volatile uint32_t *)0xfe0401a4)
+#define P_DSPB_MAILBOX_CLR_10 ((volatile uint32_t *)0xfe0401a8)
+#define P_DSPB_MAILBOX_CLR_11 ((volatile uint32_t *)0xfe0401ac)
+#define P_DSPB_MAILBOX_STAT_0 ((volatile uint32_t *)0xfe0401c0)
+#define P_DSPB_MAILBOX_STAT_1 ((volatile uint32_t *)0xfe0401c4)
+#define P_DSPB_MAILBOX_STAT_2 ((volatile uint32_t *)0xfe0401c8)
+#define P_DSPB_MAILBOX_STAT_3 ((volatile uint32_t *)0xfe0401cc)
+#define P_DSPB_MAILBOX_STAT_4 ((volatile uint32_t *)0xfe0401d0)
+#define P_DSPB_MAILBOX_STAT_5 ((volatile uint32_t *)0xfe0401d4)
+#define P_DSPB_MAILBOX_STAT_6 ((volatile uint32_t *)0xfe0401d8)
+#define P_DSPB_MAILBOX_STAT_7 ((volatile uint32_t *)0xfe0401dc)
+#define P_DSPB_MAILBOX_STAT_8 ((volatile uint32_t *)0xfe0401e0)
+#define P_DSPB_MAILBOX_STAT_9 ((volatile uint32_t *)0xfe0401e4)
+#define P_DSPB_MAILBOX_STAT_10 ((volatile uint32_t *)0xfe0401e8)
+#define P_DSPB_MAILBOX_STAT_11 ((volatile uint32_t *)0xfe0401ec)
+#define P_DSPB_QIF_CTRL ((volatile uint32_t *)0xfe040200)
+#define P_DSPB_QIF_STS ((volatile uint32_t *)0xfe040204)
+#define P_DSPB_WRFIFO_TOCPUA ((volatile uint32_t *)0xfe040208)
+#define P_DSPB_WRFIFO_TOCPUB ((volatile uint32_t *)0xfe04020c)
+#define P_DSPB_WRFIFO_TODSP ((volatile uint32_t *)0xfe040210)
+#define P_DSPB_RDFIFO_FRCPUA ((volatile uint32_t *)0xfe040220)
+#define P_DSPB_RDFIFO_FRCPUB ((volatile uint32_t *)0xfe040224)
+#define P_DSPB_RDFIFO_FRDSP ((volatile uint32_t *)0xfe040228)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: REG_LIST_DSP_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: ./REG_LIST_RTL.h
+//
+
+#endif // P_REGISTER_H
+
diff --git a/arch/arm/include/asm/arch-a1/pinctrl_init.h b/arch/arm/include/asm/arch-a1/pinctrl_init.h
new file mode 100644
index 0000000..cfbc42a
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/pinctrl_init.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _MESON_PINCTRL_INIT_H_
+#define _MESON_PINCTRL_INIT_H_
+
+#define PIN_CONTROLLER_NUM 2
+extern int pinctrl_devices_active(int pinctrl_num);
+
+#endif /* _MESON_PINCTRL_INIT_H_ */
diff --git a/arch/arm/include/asm/arch-a1/pll.h b/arch/arm/include/asm/arch-a1/pll.h
new file mode 100644
index 0000000..14c4c68
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/pll.h
@@ -0,0 +1,125 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __PLL_H
+#define __PLL_H
+
+#define PLL_TEST_SYS_TOTAL 8
+#define PLL_TEST_HDMI_TOTAL 3
+
+typedef struct sys_pll_set_s {
+ unsigned int cpu_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+}sys_pll_set_t;
+
+typedef struct hifi_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+}hifi_pll_set_t;
+
+typedef struct usbphy_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+}usbphy_pll_set_t;
+
+typedef struct sys_pll_cfg_s {
+ sys_pll_set_t sys_pll[PLL_TEST_SYS_TOTAL];
+}sys_pll_cfg_t;
+
+typedef struct hifipll_rate_table_s {
+ unsigned int rate;
+ unsigned int m;
+ unsigned int n;
+ unsigned int od;
+}hifipll_rate_table_t;
+
+#if 0
+unsigned int fix_pll_cfg[6] = {
+ /* CNTL, CNTL2, CNTL3, CNTL4, CNTL5, CNTL6*/
+ /*2G*/ 0x600006FA, 0x59C80000, 0xCA753822, 0x00010006, 0x95520E1A, 0xFC454545,
+};
+
+unsigned int ddr_pll_cfg[][6] = {
+ {0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+#endif
+
+#if 0
+typedef struct hdmi_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+}hdmi_pll_set_t;
+
+typedef struct hdmi_pll_cfg_s {
+ hdmi_pll_set_t hdmi_pll[PLL_TEST_HDMI_TOTAL];
+}hdmi_pll_cfg_t;
+
+typedef struct gpll_rate_table_s {
+ unsigned int rate;
+ unsigned int m;
+ unsigned int n;
+ unsigned int od;
+}gpll_rate_table_t;
+
+typedef struct gp0_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+}gp0_pll_set_t;
+#endif
+
+#if 0
+unsigned int hdmi_pll_cfg[][7] = {
+ /* get from enc_clk_config.c */
+ /* freq, cntl, cntl1, cntl2, cntl3, cntl4, cntl5 */
+ {5940000, 0x4000027b, 0x800cb300, 0xc60f30e0, 0x0c8e0000, 0x001fa729, 0x01a31500},
+ {5405400, 0x400002e1, 0x800cb0e6, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
+ {4455000, 0x400002b9, 0x800cb280, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
+ {4324320, 0x400002b4, 0x800cb0b8, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
+ {3712500, 0x4000029a, 0x800cb2c0, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
+ {3450000, 0x4000028f, 0x800cb300, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
+ {3243240, 0x40000287, 0x800cb08a, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
+ {2970000, 0x4000027b, 0x800cb300, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
+};
+#endif
+
+enum pll_enum {
+ PLL_SYS = 0,
+ PLL_FIX,
+ PLL_DDR,
+ PLL_HIFI,
+ PLL_USBPHY,
+ PLL_ENUM,
+};
+
+int pll_test(int argc, char * const argv[]);
+
+#endif /* __PLL_H */
diff --git a/arch/arm/include/asm/arch-a1/pwr_ctrl.h b/arch/arm/include/asm/arch-a1/pwr_ctrl.h
new file mode 100644
index 0000000..3c9b152
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/pwr_ctrl.h
@@ -0,0 +1,35 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#define PWR_ON 1
+#define PWR_OFF 0
+
+enum pm_e {
+ PM_CPU_PWR0,
+ PM_CPU_CORE0,
+ PM_CPU_CORE1,
+ PM_DSP_A = 8,
+ PM_DSP_B,
+ PM_UART,
+ PM_MMC,
+ PM_I2C,
+ PM_PSRAM,
+ PM_ACODEC,
+ PM_AUDIO,
+ PM_MKL_OTP,
+ PM_DMA,
+ PM_SDEMMC,
+ PM_SRAM_A,
+ PM_SRAM_B,
+ PM_IR,
+ PM_SPICC,
+ PM_SPIFC,
+ PM_USB,
+ PM_NIC,
+ PM_PDM,
+ PM_RSA
+};
+
+unsigned long pwr_ctrl_psci_smc(unsigned int power_domain, bool power_control);
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-a1/register.h b/arch/arm/include/asm/arch-a1/register.h
new file mode 100644
index 0000000..d800df7
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/register.h
@@ -0,0 +1,4083 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifdef REGISTER_H
+#else
+#define REGISTER_H
+
+//
+// Reading file: ./REG_LIST_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Reading file: REG_LIST_AUDIO_RTL.h
+//
+//========================================================================
+// AUDIO - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe050000
+// -----------------------------------------------
+#define EE_AUDIO_CLK_GATE_EN0 ((0x0000 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_GATE_EN1 ((0x0001 << 2) + 0xfe050000)
+#define EE_AUDIO_MCLK_A_CTRL ((0x0002 << 2) + 0xfe050000)
+#define EE_AUDIO_MCLK_B_CTRL ((0x0003 << 2) + 0xfe050000)
+#define EE_AUDIO_MCLK_C_CTRL ((0x0004 << 2) + 0xfe050000)
+#define EE_AUDIO_MCLK_D_CTRL ((0x0005 << 2) + 0xfe050000)
+#define EE_AUDIO_MCLK_E_CTRL ((0x0006 << 2) + 0xfe050000)
+#define EE_AUDIO_MCLK_F_CTRL ((0x0007 << 2) + 0xfe050000)
+#define EE_AUDIO_PAD_CTRL0 ((0x0008 << 2) + 0xfe050000)
+#define EE_AUDIO_PAD_CTRL1 ((0x0009 << 2) + 0xfe050000)
+#define EE_AUDIO_SW_RESET0 ((0x000a << 2) + 0xfe050000)
+#define EE_AUDIO_SW_RESET1 ((0x000b << 2) + 0xfe050000)
+#define EE_AUDIO_CLK81_CTRL ((0x000c << 2) + 0xfe050000)
+#define EE_AUDIO_CLK81_EN ((0x000d << 2) + 0xfe050000)
+#define EE_AUDIO_MST_A_SCLK_CTRL0 ((0x0010 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_A_SCLK_CTRL1 ((0x0011 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_B_SCLK_CTRL0 ((0x0012 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_B_SCLK_CTRL1 ((0x0013 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_C_SCLK_CTRL0 ((0x0014 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_C_SCLK_CTRL1 ((0x0015 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_D_SCLK_CTRL0 ((0x0016 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_D_SCLK_CTRL1 ((0x0017 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_E_SCLK_CTRL0 ((0x0018 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_E_SCLK_CTRL1 ((0x0019 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_F_SCLK_CTRL0 ((0x001a << 2) + 0xfe050000)
+#define EE_AUDIO_MST_F_SCLK_CTRL1 ((0x001b << 2) + 0xfe050000)
+#define EE_AUDIO_MST_DLY_CTRL0 ((0x001c << 2) + 0xfe050000)
+#define EE_AUDIO_MST_DLY_CTRL1 ((0x001d << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMIN_A_CTRL ((0x0020 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMIN_B_CTRL ((0x0021 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMIN_C_CTRL ((0x0022 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMIN_LB_CTRL ((0x0023 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMOUT_A_CTRL ((0x0024 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMOUT_B_CTRL ((0x0025 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMOUT_C_CTRL ((0x0026 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_SPDIFIN_CTRL ((0x0027 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_SPDIFOUT_CTRL ((0x0028 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_RESAMPLEA_CTRL ((0x0029 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_LOCKER_CTRL ((0x002a << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_PDMIN_CTRL0 ((0x002b << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_PDMIN_CTRL1 ((0x002c << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_SPDIFOUT_B_CTRL ((0x002d << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_RESAMPLEB_CTRL ((0x002e << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_SPDIFIN_LB_CTRL ((0x002f << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_EQDRC_CTRL0 ((0x0030 << 2) + 0xfe050000)
+#define EE_AUDIO_VAD_CLK_CTRL ((0x0031 << 2) + 0xfe050000)
+#define EE_AUDIO_EARCTX_CMDC_CLK_CTRL ((0x0032 << 2) + 0xfe050000)
+#define EE_AUDIO_EARCTX_DMAC_CLK_CTRL ((0x0033 << 2) + 0xfe050000)
+#define EE_AUDIO_EARCRX_CMDC_CLK_CTRL ((0x0034 << 2) + 0xfe050000)
+#define EE_AUDIO_EARCRX_DMAC_CLK_CTRL ((0x0035 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_LOCKERB_CTRL ((0x0036 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_CTRL0 ((0x0040 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_CTRL1 ((0x0041 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_START_ADDR ((0x0042 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_FINISH_ADDR ((0x0043 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_INT_ADDR ((0x0044 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_STATUS1 ((0x0045 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_STATUS2 ((0x0046 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_START_ADDRB ((0x0047 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_FINISH_ADDRB ((0x0048 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_INIT_ADDR ((0x0049 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_CTRL2 ((0x004a << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_CTRL0 ((0x0050 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_CTRL1 ((0x0051 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_START_ADDR ((0x0052 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_FINISH_ADDR ((0x0053 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_INT_ADDR ((0x0054 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_STATUS1 ((0x0055 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_STATUS2 ((0x0056 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_START_ADDRB ((0x0057 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_FINISH_ADDRB ((0x0058 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_INIT_ADDR ((0x0059 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_CTRL2 ((0x005a << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_CTRL0 ((0x0060 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_CTRL1 ((0x0061 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_START_ADDR ((0x0062 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_FINISH_ADDR ((0x0063 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_INT_ADDR ((0x0064 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_STATUS1 ((0x0065 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_STATUS2 ((0x0066 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_START_ADDRB ((0x0067 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_FINISH_ADDRB ((0x0068 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_INIT_ADDR ((0x0069 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_CTRL2 ((0x006a << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_CTRL0 ((0x0070 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_CTRL1 ((0x0071 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_START_ADDR ((0x0072 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_FINISH_ADDR ((0x0073 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_INT_ADDR ((0x0074 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_STATUS1 ((0x0075 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_STATUS2 ((0x0076 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_START_ADDRB ((0x0077 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_FINISH_ADDRB ((0x0078 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_INIT_ADDR ((0x0079 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_CTRL2 ((0x007a << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_CTRL0 ((0x0080 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_CTRL1 ((0x0081 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_START_ADDR ((0x0082 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_FINISH_ADDR ((0x0083 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_INT_ADDR ((0x0084 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_STATUS1 ((0x0085 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_STATUS2 ((0x0086 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_START_ADDRB ((0x0087 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_FINISH_ADDRB ((0x0088 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_INIT_ADDR ((0x0089 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_CTRL2 ((0x008a << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_CTRL0 ((0x0090 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_CTRL1 ((0x0091 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_START_ADDR ((0x0092 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_FINISH_ADDR ((0x0093 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_INT_ADDR ((0x0094 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_STATUS1 ((0x0095 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_STATUS2 ((0x0096 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_START_ADDRB ((0x0097 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_FINISH_ADDRB ((0x0098 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_INIT_ADDR ((0x0099 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_CTRL2 ((0x009a << 2) + 0xfe050000)
+#define EE_AUDIO_ARB_CTRL ((0x00a0 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_CTRL0 ((0x00b0 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_CTRL1 ((0x00b1 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_CTRL2 ((0x00b2 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_CTRL3 ((0x00b3 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_DAT_CH_ID0 ((0x00b4 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_DAT_CH_ID1 ((0x00b5 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_DAT_CH_ID2 ((0x00b6 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_DAT_CH_ID3 ((0x00b7 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_LB_CH_ID0 ((0x00b8 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_LB_CH_ID1 ((0x00b9 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_LB_CH_ID2 ((0x00ba << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_LB_CH_ID3 ((0x00bb << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_STS ((0x00bc << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_CTRL ((0x00c0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_SWAP0 ((0x00c1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK0 ((0x00c2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK1 ((0x00c3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK2 ((0x00c4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK3 ((0x00c5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_STAT ((0x00c6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE_VAL ((0x00c7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE0 ((0x00c8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE1 ((0x00c9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE2 ((0x00ca << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE3 ((0x00cb << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_CTRL ((0x00d0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_SWAP0 ((0x00d1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK0 ((0x00d2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK1 ((0x00d3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK2 ((0x00d4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK3 ((0x00d5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_STAT ((0x00d6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE_VAL ((0x00d7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE0 ((0x00d8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE1 ((0x00d9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE2 ((0x00da << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE3 ((0x00db << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_CTRL ((0x00e0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_SWAP0 ((0x00e1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK0 ((0x00e2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK1 ((0x00e3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK2 ((0x00e4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK3 ((0x00e5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_STAT ((0x00e6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE_VAL ((0x00e7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE0 ((0x00e8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE1 ((0x00e9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE2 ((0x00ea << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE3 ((0x00eb << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_CTRL ((0x00f0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_SWAP0 ((0x00f1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK0 ((0x00f2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK1 ((0x00f3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK2 ((0x00f4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK3 ((0x00f5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_STAT ((0x00f6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE_VAL ((0x00f7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE0 ((0x00f8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE1 ((0x00f9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE2 ((0x00fa << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE3 ((0x00fb << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL0 ((0x0100 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL1 ((0x0101 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL2 ((0x0102 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL3 ((0x0103 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL4 ((0x0104 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL5 ((0x0105 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL6 ((0x0106 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_STAT0 ((0x0107 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_STAT1 ((0x0108 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_STAT2 ((0x0109 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_MUTE_VAL ((0x010a << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_CTRL0 ((0x0110 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_CTRL1 ((0x0111 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_CTRL2 ((0x0112 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_CTRL3 ((0x0113 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_COEF0 ((0x0114 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_COEF1 ((0x0115 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_COEF2 ((0x0116 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_COEF3 ((0x0117 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_COEF4 ((0x0118 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_STATUS1 ((0x0119 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_STAT ((0x0120 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_GAIN0 ((0x0121 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_GAIN1 ((0x0122 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CTRL0 ((0x0123 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CTRL1 ((0x0124 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_PREAMB ((0x0125 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_SWAP ((0x0126 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS0 ((0x0127 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS1 ((0x0128 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS2 ((0x0129 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS3 ((0x012a << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS4 ((0x012b << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS5 ((0x012c << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS6 ((0x012d << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS7 ((0x012e << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS8 ((0x012f << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS9 ((0x0130 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTSA ((0x0131 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTSB ((0x0132 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_MUTE_VAL ((0x0133 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_CTRL0 ((0x0140 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_CTRL1 ((0x0141 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_SWAP0 ((0x0142 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK0 ((0x0143 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK1 ((0x0144 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK2 ((0x0145 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK3 ((0x0146 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_STAT ((0x0147 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_GAIN0 ((0x0148 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_GAIN1 ((0x0149 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE_VAL ((0x014a << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE0 ((0x014b << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE1 ((0x014c << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE2 ((0x014d << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE3 ((0x014e << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK_VAL ((0x014f << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_CTRL0 ((0x0150 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_CTRL1 ((0x0151 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_SWAP0 ((0x0152 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK0 ((0x0153 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK1 ((0x0154 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK2 ((0x0155 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK3 ((0x0156 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_STAT ((0x0157 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_GAIN0 ((0x0158 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_GAIN1 ((0x0159 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE_VAL ((0x015a << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE0 ((0x015b << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE1 ((0x015c << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE2 ((0x015d << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE3 ((0x015e << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK_VAL ((0x015f << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_CTRL0 ((0x0160 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_CTRL1 ((0x0161 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_SWAP0 ((0x0162 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK0 ((0x0163 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK1 ((0x0164 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK2 ((0x0165 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK3 ((0x0166 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_STAT ((0x0167 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_GAIN0 ((0x0168 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_GAIN1 ((0x0169 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE_VAL ((0x016a << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE0 ((0x016b << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE1 ((0x016c << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE2 ((0x016d << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE3 ((0x016e << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK_VAL ((0x016f << 2) + 0xfe050000)
+//`define EE_AUDIO_POW_DET_CTRL0 10'h180
+//`define EE_AUDIO_POW_DET_CTRL1 10'h181
+//`define EE_AUDIO_POW_DET_TH_HI 10'h182
+//`define EE_AUDIO_POW_DET_TH_LO 10'h183
+//`define EE_AUDIO_POW_DET_VALUE 10'h184
+#define EE_AUDIO_SECURITY_CTRL0 ((0x0190 << 2) + 0xfe050000)
+#define EE_AUDIO_SECURITY_CTRL1 ((0x0191 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_STAT ((0x01a0 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN0 ((0x01a1 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN1 ((0x01a2 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CTRL0 ((0x01a3 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CTRL1 ((0x01a4 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_PREAMB ((0x01a5 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_SWAP ((0x01a6 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS0 ((0x01a7 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS1 ((0x01a8 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS2 ((0x01a9 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS3 ((0x01aa << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS4 ((0x01ab << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS5 ((0x01ac << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS6 ((0x01ad << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS7 ((0x01ae << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS8 ((0x01af << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS9 ((0x01b0 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTSA ((0x01b1 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTSB ((0x01b2 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_MUTE_VAL ((0x01b3 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_CTRL0 ((0x01c0 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_CTRL1 ((0x01c1 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_START_ADDR ((0x01c2 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_FINISH_ADDR ((0x01c3 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_INT_ADDR ((0x01c4 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_STATUS1 ((0x01c5 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_STATUS2 ((0x01c6 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_INIT_ADDR ((0x01c7 << 2) + 0xfe050000)
+#define EE_AUDIO_TOACODEC_CTRL0 ((0x01d0 << 2) + 0xfe050000)
+#define EE_AUDIO_TOHDMITX_CTRL0 ((0x01d1 << 2) + 0xfe050000)
+#define EE_AUDIO_TOVAD_CTRL0 ((0x01d2 << 2) + 0xfe050000)
+#define EE_AUDIO_FRATV_CTRL0 ((0x01d3 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_CTRL0 ((0x01e0 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_CTRL1 ((0x01e1 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_CTRL2 ((0x01e2 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_CTRL3 ((0x01e3 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_COEF0 ((0x01e4 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_COEF1 ((0x01e5 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_COEF2 ((0x01e6 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_COEF3 ((0x01e7 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_COEF4 ((0x01e8 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_STATUS1 ((0x01e9 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_LB_CTRL0 ((0x01f0 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_LB_CTRL1 ((0x01f1 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_LB_CTRL6 ((0x01f6 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_LB_STAT0 ((0x01f7 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_LB_STAT1 ((0x01f8 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_LB_MUTE_VAL ((0x01fa << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_CTRL0 ((0x0200 << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_CTRL1 ((0x0201 << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_CTRL2 ((0x0202 << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_CTRL3 ((0x0203 << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_CTRL4 ((0x0204 << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_CTRL5 ((0x0205 << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_STAT0 ((0x020a << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_STAT1 ((0x020b << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_CTRL0 ((0x0210 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_CTRL1 ((0x0211 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_START_ADDR ((0x0212 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_FINISH_ADDR ((0x0213 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_INT_ADDR ((0x0214 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_STATUS1 ((0x0215 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_STATUS2 ((0x0216 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_START_ADDRB ((0x0217 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_FINISH_ADDRB ((0x0218 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_INIT_ADDR ((0x0219 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_CTRL2 ((0x021a << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_CTRL0 ((0x0220 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_CTRL1 ((0x0221 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_START_ADDR ((0x0222 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_FINISH_ADDR ((0x0223 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_INT_ADDR ((0x0224 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_STATUS1 ((0x0225 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_STATUS2 ((0x0226 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_START_ADDRB ((0x0227 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_FINISH_ADDRB ((0x0228 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_INIT_ADDR ((0x0229 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_CTRL2 ((0x022a << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_CTRL0 ((0x0230 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_CTRL1 ((0x0231 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_CTRL2 ((0x0232 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_CTRL3 ((0x0233 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_DAT_CH_ID0 ((0x0234 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_DAT_CH_ID1 ((0x0235 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_DAT_CH_ID2 ((0x0236 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_DAT_CH_ID3 ((0x0237 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_LB_CH_ID0 ((0x0238 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_LB_CH_ID1 ((0x0239 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_LB_CH_ID2 ((0x023a << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_LB_CH_ID3 ((0x023b << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_STS ((0x023c << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_CTRL0 ((0x0240 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_CTRL1 ((0x0241 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_START_ADDR ((0x0242 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_FINISH_ADDR ((0x0243 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_INT_ADDR ((0x0244 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_STATUS1 ((0x0245 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_STATUS2 ((0x0246 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_START_ADDRB ((0x0247 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_FINISH_ADDRB ((0x0248 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_INIT_ADDR ((0x0249 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_CTRL2 ((0x024a << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_CTRL0 ((0x0250 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_CTRL1 ((0x0251 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_START_ADDR ((0x0252 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_FINISH_ADDR ((0x0253 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_INT_ADDR ((0x0254 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_STATUS1 ((0x0255 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_STATUS2 ((0x0256 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_START_ADDRB ((0x0257 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_FINISH_ADDRB ((0x0258 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_INIT_ADDR ((0x0259 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_CTRL2 ((0x025a << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_SWAP1 ((0x0260 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK4 ((0x0261 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK5 ((0x0262 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK6 ((0x0263 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK7 ((0x0264 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE4 ((0x0265 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE5 ((0x0266 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE6 ((0x0267 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE7 ((0x0268 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_SWAP1 ((0x0270 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK4 ((0x0271 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK5 ((0x0272 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK6 ((0x0273 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK7 ((0x0274 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE4 ((0x0275 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE5 ((0x0276 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE6 ((0x0277 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE7 ((0x0278 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_SWAP1 ((0x0280 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK4 ((0x0281 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK5 ((0x0282 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK6 ((0x0283 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK7 ((0x0284 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE4 ((0x0285 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE5 ((0x0286 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE6 ((0x0287 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE7 ((0x0288 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_SWAP1 ((0x0290 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK4 ((0x0291 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK5 ((0x0292 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK6 ((0x0293 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK7 ((0x0294 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE4 ((0x0295 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE5 ((0x0296 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE6 ((0x0297 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE7 ((0x0298 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_CTRL2 ((0x02a0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_SWAP1 ((0x02a1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_GAIN2 ((0x02a2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_GAIN3 ((0x02a3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK4 ((0x02a4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK5 ((0x02a5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK6 ((0x02a6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK7 ((0x02a7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE4 ((0x02a8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE5 ((0x02a9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE6 ((0x02aa << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE7 ((0x02ab << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_CTRL2 ((0x02b0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_SWAP1 ((0x02b1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_GAIN2 ((0x02b2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_GAIN3 ((0x02b3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK4 ((0x02b4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK5 ((0x02b5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK6 ((0x02b6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK7 ((0x02b7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE4 ((0x02b8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE5 ((0x02b9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE6 ((0x02ba << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE7 ((0x02bb << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_CTRL2 ((0x02c0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_SWAP1 ((0x02c1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_GAIN2 ((0x02c2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_GAIN3 ((0x02c3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK4 ((0x02c4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK5 ((0x02c5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK6 ((0x02c6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK7 ((0x02c7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE4 ((0x02c8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE5 ((0x02c9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE6 ((0x02ca << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE7 ((0x02cb << 2) + 0xfe050000)
+//========================================================================
+// PDM - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051000
+// -----------------------------------------------
+#define PDM_CTRL ((0x0000 << 2) + 0xfe051000)
+ //bit 31: PDM enable.
+ //bit 30: invert the PDM_DCLK.
+ //bit 29: output mode: 1: 24bits. 0: 32 bits.
+ //bit 28: bypass mode. 1: bypass all filter. directly output the PDM input to DDR. 0: normal mode.
+ //bit 27~9: not used.
+ //bit 16:. PDM Asynchronous FIFO soft reset. write 1 to soft reset AFIFO.
+ //bit 15:8 PDM channel reset. 0: to reset each PDM channel. 1: normal mode.
+ //bit 7:0. PDM channel enable. each bit for one channel.
+#define PDM_HCIC_CTRL1 ((0x0001 << 2) + 0xfe051000)
+ //bit 31 hcic filter enable. 1 use sinc filter. 0 bypass input to output.
+ //bit 29:24. hcic final gain shift parameter.
+ //bit 23:16 hcic final gain multiplier.
+ //bit 8:4 hcic down sample rate.
+ //bit 3:0 hcic stage number. must be between 3 to 9.
+#define PDM_HCIC_CTRL2 ((0x0002 << 2) + 0xfe051000)
+ //Not used.
+#define PDM_F1_CTRL ((0x0003 << 2) + 0xfe051000)
+ //bit 31 . filter 1 enable.
+ //bit 16:15. f1 round mode. 2'b00 : sign bit at bit 49. 28bits output [49:22] round at bit 21. 32bits output [49:18]. 24bits output [49:26]
+ // 2'b01 : sign bit at bit 50. 28bits output [50:23] round at bit 22. 32bits output [49:18]. 24bits output [49:26]
+ // 2'b10 : sign bit at bit 51. 28bits output [51:24] round at bit 23 32bits output [49:18]. 24bits output [49:26].
+ //bit 15:12. filter 1 down sample rate.
+ //bit 8:0. filter 1 stage number.
+#define PDM_F2_CTRL ((0x0004 << 2) + 0xfe051000)
+ //bit 31 . filter 2 enable.
+ //bit 16:15. f2 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23.
+ //bit 15:12. filter 2 down sample rate.
+ //bit 8:0. filter 2 stage number.
+#define PDM_F3_CTRL ((0x0005 << 2) + 0xfe051000)
+ //bit 31 . filter 3 enable.
+ //bit 16:15. f3 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23.
+ //bit 15:12. filter 3 down sample rate.
+ //bit 8:0. filter 3 stage number.
+#define PDM_HPF_CTRL ((0x0006 << 2) + 0xfe051000)
+ //bit 31 High pass filter enable.
+ //bit 20:16 high pass filter shift steps. 6~19 steps.
+ //bit 15:0 high pass filter output factor.
+#define PDM_CHAN_CTRL ((0x0007 << 2) + 0xfe051000)
+ //bit 31:24. chan3 data sample pointer vs edge of the PDM_DCLK.
+ //bit 23:16 chan2 data sample pointer vs edge of the PDM_DCLK.
+ //bit 15:8. chan1 data sample pointer vs edge of the PDM_DCLK.
+ //bit 7:0 chan0 data sample pointer vs edge of the PDM_DCLK.
+#define PDM_CHAN_CTRL1 ((0x0008 << 2) + 0xfe051000)
+ //bit 31:24. chan7 data sample pointer vs edge of the PDM_DCLK.
+ //bit 23:16 chan6 data sample pointer vs edge of the PDM_DCLK.
+ //bit 15:8. chan5 data sample pointer vs edge of the PDM_DCLK.
+ //bit 7:0 chan4 data sample pointer vs edge of the PDM_DCLK.
+#define PDM_COEFF_ADDR ((0x0009 << 2) + 0xfe051000)
+ // address of the write/read of coeff data.
+#define PDM_COEFF_DATA ((0x000a << 2) + 0xfe051000)
+ //write/read data to coeff memory.
+#define PDM_CLKG_CTRL ((0x000b << 2) + 0xfe051000)
+ // auto clock gating control. 1: disable the clock gating function. the clock will awlays enabled. 0 : use RTL auto clock gating.
+ //31:7 not used.
+ //bit 6 filt_ctrl module auto clock gating control.
+ //bit 5 sinc fifo module auto clock gating control.
+ //bit 4 filter module auto clock gating control.
+ //bit 3 apb module auto clock gating control.
+ //bit 2 coeff memory module auto clock gating control.
+ //bit 1 each channel module auto clock gating control.
+ //bit 0 cts_pdm_clk auto clock gating control.
+#define PDM_STS ((0x000c << 2) + 0xfe051000)
+//bit 1 HPF filter output overflow. means the PCLK is too slow.
+//bit 0 HCIC filter output overflow. means the CTS_PDM_CLK is too slow. can't finished the filter function.
+#define PDM_MUTE_VALUE ((0x000d << 2) + 0xfe051000)
+#define PDM_MASK_NUM ((0x000e << 2) + 0xfe051000)
+//========================================================================
+// EQ DRC - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe052000
+// -----------------------------------------------
+#define AED_COEF_RAM_CNTL ((0x0000 << 2) + 0xfe052000)
+#define AED_COEF_RAM_DATA ((0x0001 << 2) + 0xfe052000)
+#define AED_EQ_EN ((0x0002 << 2) + 0xfe052000)
+#define AED_EQ_TAP_CNTL ((0x0003 << 2) + 0xfe052000)
+#define AED_EQ_VOLUME ((0x0004 << 2) + 0xfe052000)
+#define AED_EQ_VOLUME_SLEW_CNT ((0x0005 << 2) + 0xfe052000)
+#define AED_MUTE ((0x0006 << 2) + 0xfe052000)
+#define AED_DRC_CNTL ((0x0007 << 2) + 0xfe052000)
+#define AED_DRC_RMS_COEF0 ((0x0008 << 2) + 0xfe052000)
+#define AED_DRC_RMS_COEF1 ((0x0009 << 2) + 0xfe052000)
+#define AED_DRC_THD0 ((0x000a << 2) + 0xfe052000)
+#define AED_DRC_THD1 ((0x000b << 2) + 0xfe052000)
+#define AED_DRC_THD2 ((0x000c << 2) + 0xfe052000)
+#define AED_DRC_THD3 ((0x000d << 2) + 0xfe052000)
+#define AED_DRC_THD4 ((0x000e << 2) + 0xfe052000)
+#define AED_DRC_K0 ((0x000f << 2) + 0xfe052000)
+#define AED_DRC_K1 ((0x0010 << 2) + 0xfe052000)
+#define AED_DRC_K2 ((0x0011 << 2) + 0xfe052000)
+#define AED_DRC_K3 ((0x0012 << 2) + 0xfe052000)
+#define AED_DRC_K4 ((0x0013 << 2) + 0xfe052000)
+#define AED_DRC_K5 ((0x0014 << 2) + 0xfe052000)
+#define AED_DRC_THD_OUT0 ((0x0015 << 2) + 0xfe052000)
+#define AED_DRC_THD_OUT1 ((0x0016 << 2) + 0xfe052000)
+#define AED_DRC_THD_OUT2 ((0x0017 << 2) + 0xfe052000)
+#define AED_DRC_THD_OUT3 ((0x0018 << 2) + 0xfe052000)
+#define AED_DRC_OFFSET ((0x0019 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF00 ((0x001a << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF01 ((0x001b << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF10 ((0x001c << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF11 ((0x001d << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF20 ((0x001e << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF21 ((0x001f << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF30 ((0x0020 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF31 ((0x0021 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF40 ((0x0022 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF41 ((0x0023 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF50 ((0x0024 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF51 ((0x0025 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF00 ((0x0026 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF01 ((0x0027 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF10 ((0x0028 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF11 ((0x0029 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF20 ((0x002a << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF21 ((0x002b << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF30 ((0x002c << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF31 ((0x002d << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF40 ((0x002e << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF41 ((0x002f << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF50 ((0x0030 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF51 ((0x0031 << 2) + 0xfe052000)
+#define AED_DRC_LOOPBACK_CNTL ((0x0032 << 2) + 0xfe052000)
+#define AED_MDRC_CNTL ((0x0033 << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF00 ((0x0034 << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF01 ((0x0035 << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF00 ((0x0036 << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF01 ((0x0037 << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF00 ((0x0038 << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF01 ((0x0039 << 2) + 0xfe052000)
+#define AED_MDRC_THD0 ((0x003a << 2) + 0xfe052000)
+#define AED_MDRC_K0 ((0x003b << 2) + 0xfe052000)
+#define AED_MDRC_LOW_GAIN ((0x003c << 2) + 0xfe052000)
+#define AED_MDRC_OFFSET0 ((0x003d << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF10 ((0x003e << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF11 ((0x003f << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF10 ((0x0040 << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF11 ((0x0041 << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF10 ((0x0042 << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF11 ((0x0043 << 2) + 0xfe052000)
+#define AED_MDRC_THD1 ((0x0044 << 2) + 0xfe052000)
+#define AED_MDRC_K1 ((0x0045 << 2) + 0xfe052000)
+#define AED_MDRC_OFFSET1 ((0x0046 << 2) + 0xfe052000)
+#define AED_MDRC_MID_GAIN ((0x0047 << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF20 ((0x0048 << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF21 ((0x0049 << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF20 ((0x004a << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF21 ((0x004b << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF20 ((0x004c << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF21 ((0x004d << 2) + 0xfe052000)
+#define AED_MDRC_THD2 ((0x004e << 2) + 0xfe052000)
+#define AED_MDRC_K2 ((0x004f << 2) + 0xfe052000)
+#define AED_MDRC_OFFSET2 ((0x0050 << 2) + 0xfe052000)
+#define AED_MDRC_HIGH_GAIN ((0x0051 << 2) + 0xfe052000)
+#define AED_ED_CNTL ((0x0052 << 2) + 0xfe052000)
+#define AED_DC_EN ((0x0053 << 2) + 0xfe052000)
+#define AED_ND_LOW_THD ((0x0054 << 2) + 0xfe052000)
+#define AED_ND_HIGH_THD ((0x0055 << 2) + 0xfe052000)
+#define AED_ND_CNT_THD ((0x0056 << 2) + 0xfe052000)
+#define AED_ND_SUM_NUM ((0x0057 << 2) + 0xfe052000)
+#define AED_ND_CZ_NUM ((0x0058 << 2) + 0xfe052000)
+#define AED_ND_SUM_THD0 ((0x0059 << 2) + 0xfe052000)
+#define AED_ND_SUM_THD1 ((0x005a << 2) + 0xfe052000)
+#define AED_ND_CZ_THD0 ((0x005b << 2) + 0xfe052000)
+#define AED_ND_CZ_THD1 ((0x005c << 2) + 0xfe052000)
+#define AED_ND_COND_CNTL ((0x005d << 2) + 0xfe052000)
+#define AED_ND_RELEASE_COEF0 ((0x005e << 2) + 0xfe052000)
+#define AED_ND_RELEASE_COEF1 ((0x005f << 2) + 0xfe052000)
+#define AED_ND_ATTACK_COEF0 ((0x0060 << 2) + 0xfe052000)
+#define AED_ND_ATTACK_COEF1 ((0x0061 << 2) + 0xfe052000)
+#define AED_ND_CNTL ((0x0062 << 2) + 0xfe052000)
+#define AED_MIX0_LL ((0x0063 << 2) + 0xfe052000)
+#define AED_MIX0_RL ((0x0064 << 2) + 0xfe052000)
+#define AED_MIX0_LR ((0x0065 << 2) + 0xfe052000)
+#define AED_MIX0_RR ((0x0066 << 2) + 0xfe052000)
+#define AED_CLIP_THD ((0x0067 << 2) + 0xfe052000)
+#define AED_CH1_ND_SUM_OUT ((0x0068 << 2) + 0xfe052000)
+#define AED_CH2_ND_SUM_OUT ((0x0069 << 2) + 0xfe052000)
+#define AED_CH1_ND_CZ_OUT ((0x006a << 2) + 0xfe052000)
+#define AED_CH2_ND_CZ_OUT ((0x006b << 2) + 0xfe052000)
+#define AED_NOISE_STATUS ((0x006c << 2) + 0xfe052000)
+#define AED_POW_CURRENT_S0 ((0x006d << 2) + 0xfe052000)
+#define AED_POW_CURRENT_S1 ((0x006e << 2) + 0xfe052000)
+#define AED_POW_CURRENT_S2 ((0x006f << 2) + 0xfe052000)
+#define AED_POW_OUT0 ((0x0070 << 2) + 0xfe052000)
+#define AED_POW_OUT1 ((0x0071 << 2) + 0xfe052000)
+#define AED_POW_OUT2 ((0x0072 << 2) + 0xfe052000)
+#define AED_POW_ADJ_INDEX0 ((0x0073 << 2) + 0xfe052000)
+#define AED_POW_ADJ_INDEX1 ((0x0074 << 2) + 0xfe052000)
+#define AED_POW_ADJ_INDEX2 ((0x0075 << 2) + 0xfe052000)
+#define AED_DRC_GAIN_INDEX0 ((0x0076 << 2) + 0xfe052000)
+#define AED_DRC_GAIN_INDEX1 ((0x0077 << 2) + 0xfe052000)
+#define AED_DRC_GAIN_INDEX2 ((0x0078 << 2) + 0xfe052000)
+#define AED_CH1_VOLUME_STATE ((0x0079 << 2) + 0xfe052000)
+#define AED_CH2_VOLUME_STATE ((0x007a << 2) + 0xfe052000)
+#define AED_CH1_VOLUME_GAIN ((0x007b << 2) + 0xfe052000)
+#define AED_CH2_VOLUME_GAIN ((0x007c << 2) + 0xfe052000)
+#define AED_FULL_POW_CURRENT ((0x007d << 2) + 0xfe052000)
+#define AED_FULL_POW_OUT ((0x007e << 2) + 0xfe052000)
+#define AED_FULL_POW_ADJ ((0x007f << 2) + 0xfe052000)
+#define AED_FULL_DRC_GAIN ((0x0080 << 2) + 0xfe052000)
+#define AED_MASTER_VOLUME_STATE ((0x0081 << 2) + 0xfe052000)
+#define AED_MASTER_VOLUME_GAIN ((0x0082 << 2) + 0xfe052000)
+#define AED_TOP_CTL0 ((0x0083 << 2) + 0xfe052000)
+#define AED_TOP_CTL1 ((0x0084 << 2) + 0xfe052000)
+#define AED_TOP_CTL2 ((0x0085 << 2) + 0xfe052000)
+//========================================================================
+// AUDIO locker - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051400
+// -----------------------------------------------
+#define AUD_LOCK_EN ((0x0000 << 2) + 0xfe051400)
+#define AUD_LOCK_SW_RESET ((0x0001 << 2) + 0xfe051400)
+#define AUD_LOCK_SW_LATCH ((0x0002 << 2) + 0xfe051400)
+#define AUD_LOCK_HW_LATCH ((0x0003 << 2) + 0xfe051400)
+#define AUD_LOCK_REFCLK_SRC ((0x0004 << 2) + 0xfe051400)
+#define AUD_LOCK_REFCLK_LAT_INT ((0x0005 << 2) + 0xfe051400)
+#define AUD_LOCK_IMCLK_LAT_INT ((0x0006 << 2) + 0xfe051400)
+#define AUD_LOCK_OMCLK_LAT_INT ((0x0007 << 2) + 0xfe051400)
+#define AUD_LOCK_REFCLK_DS_INT ((0x0008 << 2) + 0xfe051400)
+#define AUD_LOCK_IMCLK_DS_INT ((0x0009 << 2) + 0xfe051400)
+#define AUD_LOCK_OMCLK_DS_INT ((0x000a << 2) + 0xfe051400)
+#define AUD_LOCK_INT_CLR ((0x000b << 2) + 0xfe051400)
+#define AUD_LOCK_GCLK_CTRL ((0x000c << 2) + 0xfe051400)
+#define AUD_LOCK_INT_CTRL ((0x000d << 2) + 0xfe051400)
+#define RO_REF2IMCLK_CNT_L ((0x0010 << 2) + 0xfe051400)
+#define RO_REF2IMCLK_CNT_H ((0x0011 << 2) + 0xfe051400)
+#define RO_REF2OMCLK_CNT_L ((0x0012 << 2) + 0xfe051400)
+#define RO_REF2OMCLK_CNT_H ((0x0013 << 2) + 0xfe051400)
+#define RO_IMCLK2REF_CNT_L ((0x0014 << 2) + 0xfe051400)
+#define RO_IMCLK2REF_CNT_H ((0x0015 << 2) + 0xfe051400)
+#define RO_OMCLK2REF_CNT_L ((0x0016 << 2) + 0xfe051400)
+#define RO_OMCLK2REF_CNT_H ((0x0017 << 2) + 0xfe051400)
+#define RO_REFCLK_PKG_CNT ((0x0018 << 2) + 0xfe051400)
+#define RO_IMCLK_PKG_CNT ((0x0019 << 2) + 0xfe051400)
+#define RO_OMCLK_PKG_CNT ((0x001a << 2) + 0xfe051400)
+#define RO_AUD_LOCK_INT_STATUS ((0x001b << 2) + 0xfe051400)
+//========================================================================
+// AUDIO VAD - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051800
+// -----------------------------------------------
+//
+// Reading file: VAD_REG.h
+//
+#define VAD_TOP_CTRL0 ((0x0000 << 2) + 0xfe051800)
+#define VAD_TOP_CTRL1 ((0x0001 << 2) + 0xfe051800)
+#define VAD_TOP_CTRL2 ((0x0002 << 2) + 0xfe051800)
+#define VAD_FIR_CTRL ((0x0003 << 2) + 0xfe051800)
+#define VAD_FIR_EMP ((0x0004 << 2) + 0xfe051800)
+#define VAD_FIR_COEF0 ((0x0005 << 2) + 0xfe051800)
+#define VAD_FIR_COEF1 ((0x0006 << 2) + 0xfe051800)
+#define VAD_FIR_COEF2 ((0x0007 << 2) + 0xfe051800)
+#define VAD_FIR_COEF3 ((0x0008 << 2) + 0xfe051800)
+#define VAD_FIR_COEF4 ((0x0009 << 2) + 0xfe051800)
+#define VAD_FIR_COEF5 ((0x000a << 2) + 0xfe051800)
+#define VAD_FIR_COEF6 ((0x000b << 2) + 0xfe051800)
+#define VAD_FIR_COEF7 ((0x000c << 2) + 0xfe051800)
+#define VAD_FIR_COEF8 ((0x000d << 2) + 0xfe051800)
+#define VAD_FIR_COEF9 ((0x000e << 2) + 0xfe051800)
+#define VAD_FIR_COEF10 ((0x000f << 2) + 0xfe051800)
+#define VAD_FIR_COEF11 ((0x0010 << 2) + 0xfe051800)
+#define VAD_FIR_COEF12 ((0x0011 << 2) + 0xfe051800)
+#define VAD_FRAME_CTRL0 ((0x0012 << 2) + 0xfe051800)
+#define VAD_FRAME_CTRL1 ((0x0013 << 2) + 0xfe051800)
+#define VAD_FRAME_CTRL2 ((0x0014 << 2) + 0xfe051800)
+#define VAD_CEP_CTRL0 ((0x0015 << 2) + 0xfe051800)
+#define VAD_CEP_CTRL1 ((0x0016 << 2) + 0xfe051800)
+#define VAD_CEP_CTRL2 ((0x0017 << 2) + 0xfe051800)
+#define VAD_CEP_CTRL3 ((0x0018 << 2) + 0xfe051800)
+#define VAD_CEP_CTRL4 ((0x0019 << 2) + 0xfe051800)
+#define VAD_CEP_CTRL5 ((0x001a << 2) + 0xfe051800)
+#define VAD_DEC_CTRL ((0x001b << 2) + 0xfe051800)
+#define VAD_TOP_STS0 ((0x001c << 2) + 0xfe051800)
+#define VAD_TOP_STS1 ((0x001d << 2) + 0xfe051800)
+#define VAD_TOP_STS2 ((0x001e << 2) + 0xfe051800)
+#define VAD_FIR_STS0 ((0x001f << 2) + 0xfe051800)
+#define VAD_FIR_STS1 ((0x0020 << 2) + 0xfe051800)
+#define VAD_POW_STS0 ((0x0021 << 2) + 0xfe051800)
+#define VAD_POW_STS1 ((0x0022 << 2) + 0xfe051800)
+#define VAD_POW_STS2 ((0x0023 << 2) + 0xfe051800)
+#define VAD_FFT_STS0 ((0x0024 << 2) + 0xfe051800)
+#define VAD_FFT_STS1 ((0x0025 << 2) + 0xfe051800)
+#define VAD_SPE_STS0 ((0x0026 << 2) + 0xfe051800)
+#define VAD_SPE_STS1 ((0x0027 << 2) + 0xfe051800)
+#define VAD_SPE_STS2 ((0x0028 << 2) + 0xfe051800)
+#define VAD_SPE_STS3 ((0x0029 << 2) + 0xfe051800)
+#define VAD_DEC_STS0 ((0x002a << 2) + 0xfe051800)
+#define VAD_DEC_STS1 ((0x002b << 2) + 0xfe051800)
+#define VAD_LUT_CTRL ((0x002c << 2) + 0xfe051800)
+#define VAD_LUT_WR ((0x002d << 2) + 0xfe051800)
+#define VAD_LUT_RD ((0x002e << 2) + 0xfe051800)
+#define VAD_IN_SEL0 ((0x002f << 2) + 0xfe051800)
+#define VAD_IN_SEL1 ((0x0030 << 2) + 0xfe051800)
+#define VAD_TO_DDR ((0x0031 << 2) + 0xfe051800)
+//
+// Closing file: VAD_REG.h
+//
+//========================================================================
+// AUDIO RESAMPLEA - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051c00
+// -----------------------------------------------
+//
+// Reading file: RESAMPLE.h
+//
+#define AUDIO_RSAMP_CTRL0 ((0x0000 << 2) + 0xfe051c00)
+//Bit 31:3 reserved
+//Bit 2 reg_lock_rst //unsigned , default =0;
+//Bit 1 reg_rsamp_rst //unsigned , default =0;
+//Bit 0 reg_sw_rst //unsigned , default =0;
+#define AUDIO_RSAMP_CTRL1 ((0x0001 << 2) + 0xfe051c00)
+//Bit 31:26 reserved //unsigned , default =0;
+//Bit 25 reg_rsamp_rst_sel //unsigned , default =0;
+//Bit 24 reg_module_bypas //unsigned , default =0;
+//Bit 23:18 reg_gclk_ctrl //unsigned , default =0;
+//Bit 17:13 reg_in_msb //unsigned , default =23;
+//Bit 12 reg_output_en //unsigned , default =0;
+//Bit 11 reg_rsamp_en //unsigned , default =0;
+//Bit 10 reg_filt_en //unsigned , default =0;
+//Bit 9 reg_post_en //unsigned , default =0;
+//Bit 8 reg_inp_mux_mode //unsigned , default =0;
+//Bit 7:4 reserved //unsigned , default =2;
+//Bit 3:0 reg_inp_mux //unsigned , default =0;
+#define AUDIO_RSAMP_CTRL2 ((0x0002 << 2) + 0xfe051c00)
+//Bit 31:30 reserved //unsigned , default =0;
+//Bit 29:24 reg_chx_size //unsigned , default =2;
+//Bit 23:18 reserved //unsigned , default =0;
+//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4
+//Bit 15:8 reg_filt_tap //unsigned , default =63;
+//Bit 7:0 reg_intp_tap //unsigned , default =63;
+#define AUDIO_RSAMP_PHSINIT ((0x0003 << 2) + 0xfe051c00)
+//Bit 31:28 reserved //unsigned , default = 0;
+//Bit 27:0 reg_init_phs //unsigned , default = 0;
+#define AUDIO_RSAMP_PHSSTEP ((0x0004 << 2) + 0xfe051c00)
+//Bit 31 reserved //unsigned , default = 0;
+//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000
+#define AUDIO_RSAMP_SHIFT ((0x0005 << 2) + 0xfe051c00)
+//Bit 31:24 reg_rsft_iir //unsigned , default = 23;
+//Bit 23:16 reg_rsft_blnd //unsigned , default = 21;
+//Bit 15:8 reg_rsft_sinc //unsigned , default = 31;
+//Bit 7:0 reg_rsft_aa //unsigned , default = 31;
+#define AUDIO_RSAMP_ADJ_CTRL0 ((0x0006 << 2) + 0xfe051c00)
+//Bit 31:3 reserved //unsigned
+//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0;
+//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0;
+//Bit 0 reg_rsamp_adj_en //unsigned , default = 0;
+#define AUDIO_RSAMP_ADJ_CTRL1 ((0x0007 << 2) + 0xfe051c00)
+//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8;
+//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768;
+#define AUDIO_RSAMP_ADJ_SFT ((0x0008 << 2) + 0xfe051c00)
+//Bit 31:30 reserved //unsigned , default = 0;
+//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0;
+//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9;
+//Bit 23:21 reserved //unsigned , default = 0;
+//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1;
+//Bit 15:13 reserved //unsigned , default = 0;
+//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6;
+//Bit 7:6 reserved //unsigned , default = 0;
+//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12;
+#define AUDIO_RSAMP_ADJ_IDET_LEN ((0x0009 << 2) + 0xfe051c00)
+//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000;
+#define AUDIO_RSAMP_ADJ_FORCE ((0x000a << 2) + 0xfe051c00)
+//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8;
+#define AUDIO_RSAMP_ADJ_KI_FORCE ((0x000b << 2) + 0xfe051c00)
+//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0;
+#define AUDIO_RSAMP_RO_STATUS ((0x0010 << 2) + 0xfe051c00)
+//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]}
+#define AUDIO_RSAMP_RO_ADJ_FREQ ((0x0011 << 2) + 0xfe051c00)
+//Bit 31:0 ro_rsamp_adj_freq
+#define AUDIO_RSAMP_RO_ADJ_DIFF_BAK ((0x0012 << 2) + 0xfe051c00)
+//Bit 31:0 ro_det_diff_bak
+#define AUDIO_RSAMP_RO_ADJ_DIFF_DLT ((0x0013 << 2) + 0xfe051c00)
+//Bit 31:0 ro_det_diff_dlt
+#define AUDIO_RSAMP_RO_ADJ_PHS_ERR ((0x0014 << 2) + 0xfe051c00)
+//Bit 31:0 ro_det_phase_err
+#define AUDIO_RSAMP_RO_ADJ_KI_OUT ((0x0015 << 2) + 0xfe051c00)
+//Bit 31:0 ro_rsamp_ki_out
+#define AUDIO_RSAMP_RO_IN_CNT ((0x0016 << 2) + 0xfe051c00)
+//Bit 31:0 ro_rsamp_in_cnt
+#define AUDIO_RSAMP_RO_OUT_CNT ((0x0017 << 2) + 0xfe051c00)
+//Bit 31:0 ro_rsamp_out_cnt
+#define AUDIO_RSAMP_POST_COEF0 ((0x0020 << 2) + 0xfe051c00)
+//Bit 31:0 reg_post_coef0 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF1 ((0x0021 << 2) + 0xfe051c00)
+//Bit 31:0 reg_post_coef1 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF2 ((0x0022 << 2) + 0xfe051c00)
+//Bit 31:0 reg_post_coef2 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF3 ((0x0023 << 2) + 0xfe051c00)
+//Bit 31:0 reg_post_coef3 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF4 ((0x0024 << 2) + 0xfe051c00)
+//Bit 31:0 reg_post_coef4 //signed , default = 0;
+#define AUDIO_RSAMP_AA_COEF_ADDR ((0x0030 << 2) + 0xfe051c00)
+//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0;
+#define AUDIO_RSAMP_AA_COEF_DATA ((0x0031 << 2) + 0xfe051c00)
+//Bit 31:0 reg_aa_coef_data //signed , default = 0;
+#define AUDIO_RSAMP_SINC_COEF_ADDR ((0x0040 << 2) + 0xfe051c00)
+//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0;
+#define AUDIO_RSAMP_SINC_COEF_DATA ((0x0041 << 2) + 0xfe051c00)
+//Bit 31:0 reg_sinc_coef_data //signed , default = 0;
+//
+// Closing file: RESAMPLE.h
+//
+//========================================================================
+// AUDIO TOP_VAD - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe054800
+// -----------------------------------------------
+#define EE_AUDIO2_CLK81_CTRL ((0x0000 << 2) + 0xfe054800)
+#define EE_AUDIO2_CLK81_EN ((0x0001 << 2) + 0xfe054800)
+#define EE_AUDIO2_SW_RESET0 ((0x0002 << 2) + 0xfe054800)
+#define EE_AUDIO2_CLK_GATE_EN0 ((0x0003 << 2) + 0xfe054800)
+#define EE_AUDIO2_SECURITY_CTRL0 ((0x0004 << 2) + 0xfe054800)
+#define EE_AUDIO2_MCLK_VAD_CTRL ((0x0010 << 2) + 0xfe054800)
+#define EE_AUDIO2_VAD_CLK_CTRL ((0x0011 << 2) + 0xfe054800)
+#define EE_AUDIO2_MST_DLY_CTRL0 ((0x0012 << 2) + 0xfe054800)
+#define EE_AUDIO2_MST_VAD_SCLK_CTRL0 ((0x0013 << 2) + 0xfe054800)
+#define EE_AUDIO2_MST_VAD_SCLK_CTRL1 ((0x0014 << 2) + 0xfe054800)
+#define EE_AUDIO2_CLK_TDMIN_VAD_CTRL ((0x0015 << 2) + 0xfe054800)
+#define EE_AUDIO2_CLK_PDMIN_CTRL0 ((0x0016 << 2) + 0xfe054800)
+#define EE_AUDIO2_CLK_PDMIN_CTRL1 ((0x0017 << 2) + 0xfe054800)
+#define EE_AUDIO2_TOVAD_CTRL0 ((0x0020 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_CTRL0 ((0x0030 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_CTRL1 ((0x0031 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_CTRL2 ((0x0032 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_START_ADDR ((0x0033 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_INIT_ADDR ((0x0034 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_FINISH_ADDR ((0x0035 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_START_ADDRB ((0x0036 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_FINISH_ADDRB ((0x0037 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_INT_ADDR ((0x0038 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_STATUS1 ((0x0039 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_STATUS2 ((0x003a << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_CTRL ((0x0040 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_SWAP0 ((0x0041 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_SWAP1 ((0x0042 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE_VAL ((0x0043 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_STAT ((0x0044 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE0 ((0x0050 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE1 ((0x0051 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE2 ((0x0052 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE3 ((0x0053 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE4 ((0x0054 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE5 ((0x0055 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE6 ((0x0056 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE7 ((0x0057 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK0 ((0x0058 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK1 ((0x0059 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK2 ((0x005a << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK3 ((0x005b << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK4 ((0x005c << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK5 ((0x005d << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK6 ((0x005e << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK7 ((0x005f << 2) + 0xfe054800)
+//
+// Closing file: REG_LIST_AUDIO_RTL.h
+//
+//
+// Reading file: ../spifc/rtl/spifc_reg.vh
+//
+//`ifdef SPIFC_REG_DEFINE
+//`else
+//`define SPIFC_REG_DEFINE
+//`define SPIFC BASE ADDR 32'hfd000400
+// -----------------------------------------------
+// APB_BASE: APB2_BASE_ADDR = 0xfd000400
+// -----------------------------------------------
+//AHB domain regsiter.
+#define SPIFC_AHB_CTRL ((0x0000 << 2) + 0xfd000400)
+ //bit 31 AHB BUS enable. 1 enable ahb request. 0: disable ahb request.
+ //bit 30. decerr_en for (AXI->AHB bridge).
+ //bit 29. force_incr. for ( AXI->AHB bridge).
+ //bit 19. critical word first. CWF_EN. 1: enable. 0 : disable.
+ //bit 18:17 RDBUF_SIZE . 00: 64bytes. 01: 32 bytes. 10: 16 bytes. 11: reserved.
+ //bit 16 AHB MASTER enable. if enabled, each master use one dedicated HRDATA buffer inside ahb2api model. total 3 HRDATA buffers inside ahb2spi.
+ //if disabled the 3 HRDATA buffer will random be used for all masters.
+ //bit 14 write 1 to clean the HRDATA buffer 2. read 0 finished clean operation.
+ //bit 13 write 1 to clean the HRDATA buffer 1. read 0 finished clean operation.
+ //bit 12 write 1 to clean the HRDATA buffer 0. read 0 finished clean operation.
+ //bit 11:0. not used.
+#define SPIFC_CLK_CTRL ((0x0001 << 2) + 0xfd000400)
+ //bit 14 asynchronous buffer ahb clock disable. 1 = disable. 0 = enable.
+ //bit 13 ahb2spi ahb clock disable. 1 = disable. 0 = enable.
+ //bit 12 ahb_arb ahb clock disable. 1 = disable. 0 = enable.
+ //bit 10 asynchronous buffer ahb clock auto gating enable. 1 = enable. 0 = disable.
+ //bit 9 ahb2spi ahb clock auto gating enable. 1 = enable. 0 = disable.
+ //bit 8 ahbarb ahb clock auto gating enable. 1 = enable. 0 = disable.
+ //bit 2. asynchronous AHB clock domain software reset. 1 = reset. 0 = normal working mode.
+ //bit 1. ahb2spi ahb clock domain software reset. 1 = reset. 0 = normal working mode.
+ //bit 0. not used.
+#define SPIFC_SEC_CTRL ((0x0002 << 2) + 0xfd000400)
+ //bit 31. ADDRESS security range enable. 1 = enable; 0: disable.
+ //bit 14. range6 enable: 1: enable; 0 : disable.
+ //bit 13. range5 enable: 1: enable; 0 : disable.
+ //bit 12. range4 enable: 1: enable; 0 : disable.
+ //bit 11. range3 enable: 1: enable; 0 : disable.
+ //bit 10. range2 enable: 1: enable; 0 : disable.
+ //bit 9. range1 enable: 1: enable; 0 : disable.
+ //bit 8. range0 enable: 1: enable; 0 : disable.
+ //bit 7:4 to control spi clock register security. bit 7 = 1, APB bus can access spi clock domain register. bit 7 == 0 : only PPROT[0] == bit 4, the APB can access spic clock domain register.
+ //bit 3:0 to control ahb clock domain register secruity. bit 3 = 1, APB bus can access ahb clock domain register. bit 3 ==0; only PPROT[0] == bit 0, the APB can access ahb clock domain register.
+#define SPIFC_RANGE0_STA ((0x0010 << 2) + 0xfd000400)
+ //bit 28 :6.
+ //AHB security range 0 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE0_EDA ((0x0011 << 2) + 0xfd000400)
+ //bit 28 :6.
+ //AHB security range 0 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE0_CTRL ((0x0012 << 2) + 0xfd000400)
+ // AHB secruity range 0 control.
+ //bit 15:8 range 0 access control for DMA access.
+ //bit 15 range 0 access control for DMA thread 7
+ //bit 14 range 0 access control for DMA Thread 6
+ //bit 13 range 0 access control for DMA Thread 5.
+ //bit 12 range 0 access control for DMA Thread 4.
+ // bit 11. range 0 access control for DMA thread 3
+ // bit 10. range 0 access control for DMA Thread 2
+ // bit 9. range 0 access control for DMA Thread 1.
+ // bit 8. range 0 access control for DMA Thread 0.
+ // bit 7. range 0 access control for HMASTER == 7 Not used.
+ // bit 6. range 0 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 0 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 0 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 0 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 0 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 0 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 0 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE1_STA ((0x0013 << 2) + 0xfd000400)
+ //bit 28 :6.
+ //AHB security range 1 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE1_EDA ((0x0014 << 2) + 0xfd000400)
+ //bit 28 :6.
+ //AHB security range 1 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE1_CTRL ((0x0015 << 2) + 0xfd000400)
+ // AHB secruity range 1 control.
+ //bit 15:8 range 1 access control for DMA access.
+ //bit 15 range 1 access control for DMA thread 7
+ //bit 14 range 1 access control for DMA Thread 6
+ //bit 13 range 1 access control for DMA Thread 5.
+ //bit 12 range 1 access control for DMA Thread 4.
+ // bit 11. range 1 access control for DMA thread 3
+ // bit 10. range 1 access control for DMA Thread 2
+ // bit 9. range 1 access control for DMA Thread 1.
+ // bit 8. range 1 access control for DMA Thread 0.
+ // bit 7. range 1 access control for HMASTER == 7 Not used.
+ // bit 6. range 1 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 1 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 1 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 1 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 1 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 1 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 1 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE2_STA ((0x0016 << 2) + 0xfd000400)
+ //bit 28 :6.
+ //AHB security range 2 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE2_EDA ((0x0017 << 2) + 0xfd000400)
+ //bit 28 :6.
+ //AHB security range 2 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE2_CTRL ((0x0018 << 2) + 0xfd000400)
+ // AHB secruity range 2 control.
+ //bit 15:8 range 2 access control for DMA access.
+ //bit 15 range 2 access control for DMA thread 7
+ //bit 14 range 2 access control for DMA Thread 6
+ //bit 13 range 2 access control for DMA Thread 5.
+ //bit 12 range 2 access control for DMA Thread 4.
+ // bit 11. range 2 access control for DMA thread 3
+ // bit 10. range 2 access control for DMA Thread 2
+ // bit 9. range 2 access control for DMA Thread 1.
+ // bit 8. range 2 access control for DMA Thread 0.
+ // bit 7. range 2 access control for HMASTER == 7 Not used.
+ // bit 6. range 2 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 2 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 2 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 2 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 2 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 2 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 2 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE3_STA ((0x0019 << 2) + 0xfd000400)
+ //bit 28 :6.
+ //AHB security range 3 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE3_EDA ((0x001a << 2) + 0xfd000400)
+ //bit 28 :6.
+ //AHB security range 3 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE3_CTRL ((0x001b << 2) + 0xfd000400)
+ // AHB secruity range 3 control.
+ //bit 15:8 range 3 access control for DMA access.
+ //bit 15 range 3 access control for DMA thread 7
+ //bit 14 range 3 access control for DMA Thread 6
+ //bit 13 range 3 access control for DMA Thread 5.
+ //bit 12 range 3 access control for DMA Thread 4.
+ // bit 11. range 3 access control for DMA thread 3
+ // bit 10. range 3 access control for DMA Thread 2
+ // bit 9. range 3 access control for DMA Thread 1.
+ // bit 8. range 3 access control for DMA Thread 0.
+ // bit 7. range 3 access control for HMASTER == 7 Not used.
+ // bit 6. range 3 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 3 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 3 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 3 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 3 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 3 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 3 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE4_STA ((0x001c << 2) + 0xfd000400)
+ //bit 28 :6.
+ //AHB security range 4 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE4_EDA ((0x001d << 2) + 0xfd000400)
+ //bit 28 :6.
+ //AHB security range 4 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE4_CTRL ((0x001e << 2) + 0xfd000400)
+ // AHB secruity range 4 control.
+ //bit 15:8 range 4 access control for DMA access.
+ //bit 15 range 4 access control for DMA thread 7
+ //bit 14 range 4 access control for DMA Thread 6
+ //bit 13 range 4 access control for DMA Thread 5.
+ //bit 12 range 4 access control for DMA Thread 4.
+ // bit 11. range 4 access control for DMA thread 3
+ // bit 10. range 4 access control for DMA Thread 2
+ // bit 9. range 4 access control for DMA Thread 1.
+ // bit 8. range 4 access control for DMA Thread 0.
+ // bit 7. range 4 access control for HMASTER == 7 Not used.
+ // bit 6. range 4 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 4 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 4 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 4 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 4 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 4 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 4 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE5_STA ((0x001f << 2) + 0xfd000400)
+ //bit 28 :6.
+ //AHB security range 5 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE5_EDA ((0x0021 << 2) + 0xfd000400)
+ //bit 28 :6.
+ //AHB security range 5 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE5_CTRL ((0x0020 << 2) + 0xfd000400)
+ // AHB secruity range 5 control.
+ //bit 15:8 range 5 access control for DMA access.
+ //bit 15 range 5 access control for DMA thread 7
+ //bit 14 range 5 access control for DMA Thread 6
+ //bit 13 range 5 access control for DMA Thread 5.
+ //bit 12 range 5 access control for DMA Thread 4.
+ // bit 11. range 5 access control for DMA thread 3
+ // bit 10. range 5 access control for DMA Thread 2
+ // bit 9. range 5 access control for DMA Thread 1.
+ // bit 8. range 5 access control for DMA Thread 0.
+ // bit 7. range 5 access control for HMASTER == 7 Not used.
+ // bit 6. range 5 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 5 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 5 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 5 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 5 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 5 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 5 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE6_STA ((0x0022 << 2) + 0xfd000400)
+ //bit 28 :6.
+ //AHB security range 6 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE6_EDA ((0x0023 << 2) + 0xfd000400)
+ //bit 28 :6.
+ //AHB security range 6 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE6_CTRL ((0x0024 << 2) + 0xfd000400)
+ // AHB secruity range 6 control.
+ //bit 15:8 range 6 access control for DMA access.
+ //bit 15 range 6 access control for DMA thread 7
+ //bit 14 range 6 access control for DMA Thread 6
+ //bit 13 range 6 access control for DMA Thread 5.
+ //bit 12 range 6 access control for DMA Thread 4.
+ // bit 11. range 6 access control for DMA thread 3
+ // bit 10. range 6 access control for DMA Thread 2
+ // bit 9. range 6 access control for DMA Thread 1.
+ // bit 8. range 6 access control for DMA Thread 0.
+ // bit 7. range 6 access control for HMASTER == 7 Not used.
+ // bit 6. range 6 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 6 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 6 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 6 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 6 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 6 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 6 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE7_CTRL ((0x0025 << 2) + 0xfd000400)
+ // AHB secruity range 7( default range) control.
+ //bit 15:8 range 7 access control for DMA access.
+ //bit 15 range 7 access control for DMA thread 7
+ //bit 14 range 7 access control for DMA Thread 6
+ //bit 13 range 7 access control for DMA Thread 5.
+ //bit 12 range 7 access control for DMA Thread 4.
+ // bit 11. range 7 access control for DMA thread 3
+ // bit 10. range 7 access control for DMA Thread 2
+ // bit 9. range 7 access control for DMA Thread 1.
+ // bit 8. range 7 access control for DMA Thread 0.
+ // bit 7. range 7 access control for HMASTER == 7 Not used.
+ // bit 6. range 7 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 7 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 7 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 7 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 7 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 7 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 7 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_AHB_WTCH_CTRL ((0x0026 << 2) + 0xfd000400)
+ //bit 15:0. ahb bus watch dog timer. if AHB bus not response, the timer over this number, the SPIFC will send back a error response.
+#define SPIFC_SEC_VIO0 ((0x0027 << 2) + 0xfd000400)
+ //bit 31:0 VIO ADDR
+#define SPIFC_SEC_VIO1 ((0x0028 << 2) + 0xfd000400)
+ //bit 31. AHB VIO status. write 1 to clear the error info.
+ //bit 6:5 HMASTER.
+ //bit 4:2 HPROT.
+ //bit 1 HNONSEC.
+ //bit 0 HWRITE.
+#define SPIFC_AHB_STS ((0x0029 << 2) + 0xfd000400)
+ //bit 31. AHB IDLE. when ahb disabled, to show ahb status. 1, no more ahb request or ahb requent is holded. 0, ahb is still busy.
+ //bit 30. AHB data cycle status, when ahb disabled, to show ahb data cycle status. 1, data cycle is holded, 0 : not in data cycle or data cycle is processing.
+ //bit 29. AHB bus spi requst status. 1: still waiting for spi data. 0: idle.
+ //bit 28:0. not used.
+//SPI cts_spi_clk domain regsiter.
+#define SPIFC_USER_CTRL0 ((0x0080 << 2) + 0xfd000400)
+ //bit 31. user request enable. write 1 to enable. read 0, means user command accepted by the SPI_CTRL.
+ //bit 30. user request finish bit. write 0 when enable user request. read 1 means SPI_CTRL finished this user command.
+ //bit 0. user data updated. write 0 when enable user request. 1 means there's datas/status read from SPI flash.
+#define SPIFC_USER_CTRL1 ((0x0081 << 2) + 0xfd000400)
+ //bit 31. not used.
+ //bit 30. user command cycle enable. 1) enable. 0) don't send command in usr command period.
+ //bit 29:28. user command mode. 00 = SPI extend mode. 01 : dual mode. 10: quad mode.
+ //bit 27:20. user command code. the code need to send in command period.
+ //bit 19. user address cycle enable.
+ //bit 18:17 user address mode: 00 = SPI extend mode. 01 : dual mode. 10: quad mode.
+ //bit 16:15 user address Byte length 00 = 1 byte. 01 = 2 bytes. 10 = 3 bytes. 11 = 4bytes.
+ //bit 14 user datout enable.
+ //bit 13 user dataout AES enable. 1: dataout through AES describle. 0 : original data.
+ //bit 12 user data output source. 0: from data buffer. 1: from status register.
+ //bit 11:10 user dataout mode: 00 SPI extend model. 01 : dual model. 10. quad mode.
+ //bit 9:0 User data out bytes num.
+#define SPIFC_USER_CTRL2 ((0x0082 << 2) + 0xfd000400)
+ //bit 31 usr_dummy_en 1: enable dummy cycles. 0 : no dummy cycles.
+ //bit 30: 29 usr_dummy_mode 2'b00 = SPI extend mode. 01 dual mode. 10 Quad mode.
+ //bit 28:23 user dummy clock cycle number.
+ //bit 19:16. user command input/output direction control. 000000: right after the last output.
+ // 1: after the first cycle of dummy cycle.
+ // .....
+ // 4'hf: right before the datin cycle.
+ //bit 15:8. data on the dummy cycle after the first byte.
+ //bit 7:0 The first bytes data showed on dummy cycle. some flash may need special data for enhance performance mode or XIP mode.
+#define SPIFC_USER_CTRL3 ((0x0083 << 2) + 0xfd000400)
+ //bit 31 usr_datin_en 1: datain cycle enabled. 0: no datain cycle.
+ //bit 30: datin_dest. 1: save the input data to STATUS register. 0 save the input data to data buffer.
+ //bit 29: 1: enable datain data AES describle. 0: not use AES.
+ //bit 28:27. datin mode. 2'b00 SPI extend mode. 01: dual mode. 10 Quad mode.
+ //bit 25:16. user data in data bytes. how many bytes of user datain expected.
+#define SPIFC_USER_ADDR ((0x0084 << 2) + 0xfd000400)
+ //bit 31:0. 32bits user address.
+#define SPIFC_AHB_REQ_CTRL ((0x0085 << 2) + 0xfd000400)
+ //bit 31. AHB request enable.
+ //bit 30 AHB cmd_en. command cycle enable.
+ //bit 29:28. ahb command mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode.
+ //bit 27:20:.AHB command code.
+ //bit 19. ahb request address cycle enable.
+ //bit 18:17 AHB ADDRESS mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode.
+ //bit 16:15 AHB ADDRESS data width. 2'b00: 1byte. 2'b01 : 2bytes. 2'b10: 3bytes. 2'b11 4bytes.
+ //bit 13:10 AHB request spi bus input switch time. 0 : after address cycle. 1: the frist dummy cycles. ... 0xf. after dummy cycle.
+ //bit 9:8 AHB DATAIN mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode.
+ //bit 7 DATA IN AES enable. 1: enable 0: disable.
+ //bit 1:0 AHB REQ DATA size. 2'b00: 64bytes. 2'b01: 32 bytes. 2'b10 : 16 bytes. 2'b11: reserved. this bit settign should be same as RDBUF_SIZE setting.
+#define SPIFC_AHB_REQ_CTRL1 ((0x0086 << 2) + 0xfd000400)
+ //bit 31. ahb Dummy enable.
+ //bit 30:29. ahb dummy mode.
+ //bit 28:23. ahb request dummy clock cycles.
+ //bit 15:0. ahb dummy period output data.
+#define SPIFC_AHB_REQ_CTRL2 ((0x0087 << 2) + 0xfd000400)
+ //bit 1:0 AHB address position. this settign depend on SPIFC_AHB_CTRL register CWF_EN bit and RDBUF_SIZE.
+ // if CWF_EN is enabled. these bit should be set to 2'b10 (16BYTE boundary).
+ // if CWF_EN is disabled. these bit should be set to same as the RDBUF_SIZE and AHB REQ DATA SIZE.
+ //00 : 64byte boundary.
+ //01 : 32byte boundary.
+ //10 : 16byte boundary.
+ //11 : reserved.
+#define SPIFC_ACTIMING0 ((0x0088 << 2) + 0xfd000400)
+ //bit 31:30. tSLCH
+ //bit 29:28 tCLSH
+ //bit 20:16 tSHWL
+ //bit 15:12 tSHSL2
+ //bit 11:8 tSHSL1
+ //bit 7:0 tWHSL
+#define SPIFC_ACTIMING1 ((0x0089 << 2) + 0xfd000400)
+ //bit 31. D2 pin WP_n function enable.
+ //bit 30. D2 Pin value in WP_n fucntion.
+ //bit 29. D3 Pin HOLD_n function enable.
+ //bit 8. DTR mode. not support.
+ //bit 6:4. Clock turn around delay. use it to set the system SPI clock read data delay.
+ //bit 3:0. not used.
+#define SPIFC_ACTIMING2 ((0x008a << 2) + 0xfd000400)
+ //bit 31. spi clock input pin enable. SPIFC controller used this pin as clock to latch the input data.
+ //bit [3:0] spi clock input pin delay adjustment.
+//SPI DATA BUFFER. There's a total 512Byte + 64byte(orgnized as 36x128bits) SRAM .
+// since each APB access is 32bits. So we use word address as APB read/write address.
+// But for SPI side we have to use 128bit boundary. That's the first Pragram/read SPI with data buffer must start at data buffer 128bit boundary. that means the SPIFC_USE_DBUF_ADDR last 2 bits must be 0.
+#define SPIFC_DBUF_CTRL ((0x0090 << 2) + 0xfd000400)
+ //bit 31. 1 = write DBUF. 0 : read DBUF.
+ //bit 30. 1. = auto update address. 0 don't change address.
+ //bit 7:0 DBUF address unit 32bits.
+#define SPIFC_DBUF_DATA ((0x0091 << 2) + 0xfd000400)
+ //bit 31:0. if SPIFC_DBUF_CTRL bit 31 = 1. write to this register will trigger one write to DBUF. and the data will be writen to DBUF.
+#define SPIFC_USER_DBUF_ADDR ((0x0092 << 2) + 0xfd000400)
+ //bit 7:0. the DBUF ADDRESS used to send to or receive from SPI FLASH. the last 2 bits must be 0.
+#define SPIFC_FLASH_STATUS ((0x00a0 << 2) + 0xfd000400)
+#define SPIFC_STATUS ((0x00a1 << 2) + 0xfd000400)
+ //bit 1. AES KEY valid. read only 1 : The aes key is ready to use. 0: the aes key is not ready.
+ //bit 0. SPI CTRL STATE IDLE. read only. 1 = idle; 0 = busy.
+#define SPIFC_CTRL ((0x00a2 << 2) + 0xfd000400)
+ //bit 15:14. mempd for DBUF MEMORY.
+ //bit 13 spifc asynchronous buffer clock disable. 1 = disable. 0 = enable.
+ //bit 12. spifc controller clock disable. 1 = disable. 0 = enable.
+ //bit 9. spifc asynchronous bufer clock auto gate enable. 1 = enable. 0 = disable.
+ //bit 8. spifc controller clock auto gate enable. 1 = enable. 0 = disable.
+ //bit 2. spifc interface reset. 1 = RESET. 0 = normal working mode.
+ //bit 1. spifc asynchronous buffer spi clock side reset. 1 = RESET. 0 : normal working mode.
+ //bit 0. spifc controller reset. 1 = RESET. 0 : normal working mode.
+//`endif
+//
+// Closing file: ../spifc/rtl/spifc_reg.vh
+//
+//
+// Reading file: ../psram/rtl/psram_reg.vh
+//
+//`ifdef PSRAM_REG_DEFINE
+//`else
+//`define PSRAM_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007400
+// -----------------------------------------------
+#define PSRAM_AXI_INTF_CTRL ((0x0000 << 2) + 0xfe007400)
+ //bit 3 axi interface soft reset. 1 = reset AXI interface. 0 = normal.
+ //bit 2 disable axi interface clock. 1 = disable; 0 = enable.
+ //bit 1 axi interface auto clock gating enable. 1 = enable; 0 = disable.
+ //bit 0 axi interface AXI request enable. 1 = enable. 0 = disable.
+#define PSRAM_DBUF_CTRL ((0x0001 << 2) + 0xfe007400)
+ //bit 16. MWRITE_EN. 1 : enabel mask write(with DM pin). 0 not enable.
+ //bit 15:0 DBUF AGE to write back to PSRAM if DBUF is dirty. but whole DBUF data is not READ to write.(with MWRITE enabled).
+#define PSRAM_DBUF_CTRL1 ((0x0002 << 2) + 0xfe007400)
+ //bit 15:0 DBUF AGE to write back to psram if DBUF is dirty and whole DBUF data is ready to write.
+#define PSRAM_APB_CTRL ((0x0003 << 2) + 0xfe007400)
+ //7:4 PSRAM PHY register APB secure contrl.
+ //bit 7, 1: no secure control. 0 : use bit 4 to match PPROT[0] bit.
+ //bit 4. when bit 7 == 0, bit 4 must match PPROT[0] to access.
+ //3:0 PCTL_CTRL APB bus control regsiters secure control.
+ //bit 3, 1: no secure control. 0 : use bit 0 to match PPROT[0] bit.
+ //bit 0. when bit 3 == 0, bit 0 must match PPROT[0] to access.
+#define PSRAM_SEC_CTRL ((0x0004 << 2) + 0xfe007400)
+ //bit 31. ADDRESS security range enable. 1 = enable; 0: disable.
+ //if scruity range disabled, but AXI data describle enabled key0 is selected.
+ //bit 23 range 7 des key selection 0 : key0; 1: key1;
+ //bit 22 range 6 des key selection 0 : key0; 1: key1;
+ //bit 21 range 5 des key selection 0 : key0; 1: key1;
+ //bit 20 range 4 des key selection 0 : key0; 1: key1;
+ //bit 19 range 3 des key selection 0 : key0; 1: key1;
+ //bit 18 range 2 des key selection 0 : key0; 1: key1;
+ //bit 17 range 1 des key selection 0 : key0; 1: key1;
+ //bit 16 range0 des key selection 0 : key0; 1: key1;
+ //bit 6. range6 enable: 1: enable; 0 : disable.
+ //bit 5. range5 enable: 1: enable; 0 : disable.
+ //bit 4. range4 enable: 1: enable; 0 : disable.
+ //bit 3. range3 enable: 1: enable; 0 : disable.
+ //bit 2. range2 enable: 1: enable; 0 : disable.
+ //bit 1. range1 enable: 1: enable; 0 : disable.
+ //bit 0. range0 enable: 1: enable; 0 : disable.
+#define PSRAM_DES_PADDING ((0x0005 << 2) + 0xfe007400)
+ //bit 31 :0 Padding, with address together to generate describle 64 bits input.
+#define PSRAM_RANGE0_STA ((0x0010 << 2) + 0xfe007400)
+ //bit 22 :0.
+ //AXI security range 0 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define PSRAM_RANGE0_EDA ((0x0011 << 2) + 0xfe007400)
+ //bit 22 :0.
+ //AXI security range 0 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define PSRAM_RANGE0_CTRL0 ((0x0012 << 2) + 0xfe007400)
+ // AXI secruity range 0 control.
+#define PSRAM_RANGE0_CTRL1 ((0x0013 << 2) + 0xfe007400)
+ // AXI secruity range 0 control.
+#define PSRAM_RANGE1_STA ((0x0014 << 2) + 0xfe007400)
+ //bit 22 :0.
+ //AXI security range 1 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define PSRAM_RANGE1_EDA ((0x0015 << 2) + 0xfe007400)
+ //bit 22 :0.
+ //AXI security range 1 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define PSRAM_RANGE1_CTRL0 ((0x0016 << 2) + 0xfe007400)
+ // AXI secruity range 1 control.
+#define PSRAM_RANGE1_CTRL1 ((0x0017 << 2) + 0xfe007400)
+ // AXI secruity range 1 control.
+#define PSRAM_RANGE2_STA ((0x0018 << 2) + 0xfe007400)
+ //bit 31 : 6.
+ //AXI security range 2 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define PSRAM_RANGE2_EDA ((0x0019 << 2) + 0xfe007400)
+ //bit 31 :6.
+ //AXI security range 2 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define PSRAM_RANGE2_CTRL0 ((0x001a << 2) + 0xfe007400)
+#define PSRAM_RANGE2_CTRL1 ((0x001b << 2) + 0xfe007400)
+#define PSRAM_RANGE3_STA ((0x001c << 2) + 0xfe007400)
+ //bit 31 : 6.
+ //AXI security range 3 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define PSRAM_RANGE3_EDA ((0x001d << 2) + 0xfe007400)
+ //bit 31 :6.
+ //AXI security range 3 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define PSRAM_RANGE3_CTRL0 ((0x001e << 2) + 0xfe007400)
+ // AXI secruity range 3 control.
+#define PSRAM_RANGE3_CTRL1 ((0x001f << 2) + 0xfe007400)
+ // AXI secruity range 3 control.
+#define PSRAM_RANGE4_STA ((0x0020 << 2) + 0xfe007400)
+ //bit 31 :6.
+ //AXI security range 4 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define PSRAM_RANGE4_EDA ((0x0021 << 2) + 0xfe007400)
+ //bit 31 :6.
+ //AXI security range 4 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define PSRAM_RANGE4_CTRL0 ((0x0022 << 2) + 0xfe007400)
+ // AXI secruity range 4 control.
+#define PSRAM_RANGE4_CTRL1 ((0x0023 << 2) + 0xfe007400)
+#define PSRAM_RANGE5_STA ((0x0024 << 2) + 0xfe007400)
+ //bit 22 :0.
+ //AXI security range 5 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define PSRAM_RANGE5_EDA ((0x0025 << 2) + 0xfe007400)
+ //bit 22 :0.
+ //AXI security range 5 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define PSRAM_RANGE5_CTRL0 ((0x0026 << 2) + 0xfe007400)
+ // AXI secruity range 5 control.
+#define PSRAM_RANGE5_CTRL1 ((0x0027 << 2) + 0xfe007400)
+ // AXI secruity range 5 control.
+#define PSRAM_RANGE6_STA ((0x0028 << 2) + 0xfe007400)
+ //bit 22 :0.
+ //AXI security range 6 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define PSRAM_RANGE6_EDA ((0x0029 << 2) + 0xfe007400)
+ //bit 22 :0.
+ //AXI security range 6 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define PSRAM_RANGE6_CTRL0 ((0x002a << 2) + 0xfe007400)
+ // AXI secruity range 6 control.
+#define PSRAM_RANGE6_CTRL1 ((0x002b << 2) + 0xfe007400)
+ // AXI secruity range 6 control.
+#define PSRAM_RANGE7_CTRL0 ((0x002c << 2) + 0xfe007400)
+#define PSRAM_RANGE7_CTRL1 ((0x002d << 2) + 0xfe007400)
+#define PSRAM_VIO_STATUS ((0x002e << 2) + 0xfe007400)
+ //bit 31: security violation. write 1 to clean security violation status.
+ //bit 30. 1 : AXI write violation. 0 : axi read violation.
+ //bit 18:16. AXI ARPROT/AWPROT>
+ //bit 11:0. AXI violation ID.
+#define PSRAM_VIO_ADDR ((0x002f << 2) + 0xfe007400)
+ //read only
+ //31:0 AXI violation address.
+#define PSRAM_USER_CTRL0 ((0x0080 << 2) + 0xfe007400)
+ //bit 31. user request enable. write 1 to enable. read 0, means user command accepted by the SPI_CTRL.
+ //bit 30. usr request done. after user command done. this bit set to 1.
+ //bit 29. USR COMMAND enable.
+ //bit 28. command type0. 1 READ command. 0 write command.
+ //bit 27. command type1. 1 for register. 0 : for memory.
+ //bit 21~16. USR command clock cycles
+ //bit 15~0. USR COMMAND CODE.
+#define PSRAM_USER_CTRL1 ((0x0081 << 2) + 0xfe007400)
+ //bit 31. USR_ADDR_EN
+ //bit 30:29. USR_ADDR_DW
+ //bit 28~20. USR address clock cycle number.
+ //bit 19:16 USR data output/input switch postion
+ //bit 15. USR DUMMY ENABLE
+ //bit 13~8. USR DUMMY clock cycles.
+ //bit 5:0 USR data DQS read enable postion.
+#define PSRAM_USER_CTRL2 ((0x0082 << 2) + 0xfe007400)
+ //bit 31 usr des key selection. 1 : key 1; 0 : key 0.
+ //bit 30. usr check latency. for Winbond PSRAM data read/write, DQS input indentify the latency is doubled or not.
+ //bit 29. usr data des enable.
+ //bit 28 usr datain enable.
+ //bit 27. usr datain destination. 1 : write to CFG_STS register. 0 : write to DATA REGISTERs.
+ //bit 26~16 usr data in clock cycle number.
+ //bit 15. usr datout enable.
+ //bit 14. usr data out source 1 : from CFG_STS register. 0 from DATA register.
+ //bit 13~11. not used.
+ //bit 10~0. usr dataout clock cycles.
+#define PSRAM_USER_CTRL3 ((0x0083 << 2) + 0xfe007400)
+ //bit 17:16. which cycle to ask phy to check read/write latency at PSRAM SEND COMMOND stage.
+ //since PSRAM send command stage only 3 clock cycle. So this number only can chose 0, 1, 2.
+ //bit 15:0. user dummy data when output in dummy cycle.
+#define PSRAM_USER_ADDR ((0x0084 << 2) + 0xfe007400)
+ //bit 31:0. 32bits user address.
+#define PSRAM_AXI_REQ_CTRL0 ((0x0085 << 2) + 0xfe007400)
+ //bit 31. AXI request enable.
+ //bit 30 AXI cmd_en. command cycle enable.
+ //bit 29:24. AXI request command cycle clock numbers.
+ //bit 22. AXI request address cycle enable.
+ //bit 21:16. AXI request address cycle clock number.
+ //bit 15:14. AXI address cycle data width.
+ //bit 13:12. at which clock cycle to send signal to phy to check latency flag for WINBOND PSRAM flexible latency.
+ //since PSRAM send command stage only 3 clock cycle. So this number only can chose 0, 1, 2.
+ //bit 6 // AXI Write dummy enable.
+ //bit 5:0 // axi write dummy clock cycle number.
+#define PSRAM_AXI_REQ_CTRL1 ((0x0086 << 2) + 0xfe007400)
+ //bit 31:16. AXI request psram READ command code.
+ //bit 15:0. AXI request psram write command code.
+#define PSRAM_AXI_REQ_CTRL2 ((0x0087 << 2) + 0xfe007400)
+ //bit 31. AXI read request Dummy enable.
+ //bit 30. Check latency enable for WINBOND PSRAM flexible latency.
+ //bit 27:22. clock cycles in dummy stage to eanble PSRAM PHY reading logic.
+ //bit 21:16. axi_read dummy clock cycles number.
+ //bit 15:0. dummy data if output in dummy cycles.
+#define PSRAM_AXI_REQ_CTRL3 ((0x0088 << 2) + 0xfe007400)
+ //bit 31 des enable.
+ //bit 26:16. DATA input clock cycles.
+ //bit 10:0. DATA output clock cycles.
+#define PSRAM_ACTIMING0 ((0x0089 << 2) + 0xfe007400)
+ //bit 31:30. tSLCH
+ //bit 29:28 tCLSH
+ //bit 20:16 tSHWL
+ //bit 15:12 tSHSL2
+ //bit 11:8 tSHSL1
+ //bit 7:0 tWHSL
+#define PSRAM_ACTIMING1 ((0x008a << 2) + 0xfe007400)
+ //bit 7:0 tRWR for winbond PSRAM, = tRWR -3. Winbond PSRAM include one CS cycle and 2 command cycle.
+ //for APMEMORY should be same value of tCPH
+#define PSRAM_ACTIMING2 ((0x008b << 2) + 0xfe007400)
+#define PSRAM_WDG_CTRL ((0x008c << 2) + 0xfe007400)
+ //bit [31] 1: force to reset PSRAM PCTL and PHY logic. 0: normal.
+ //bit [30] 1: automatic reset PSRAM PCTL and PHY logic if watch dog triggered.
+ //bit 12:0. watch dog timer. for Winbond PSRAM should be 1us for tRC. for APMEMORY should be 1us for tCEM.
+//SPI DATA BUFFER. There's a total 512KByte + 64byte(orgnized as 36x128bits) SRAM .
+// since each APB access is 32bits. So we use word address as APB read/write address.
+// But for SPI side we have to use 128bit boundary. That's the first Pragram/read SPI with data buffer must start at data buffer 128bit boundary. that means the PSRAM_USE_DBUF_ADDR last 2 bits must be 0.
+#define PSRAM_DBUF_0 ((0x0090 << 2) + 0xfe007400)
+#define PSRAM_DBUF_1 ((0x0091 << 2) + 0xfe007400)
+#define PSRAM_DBUF_2 ((0x0092 << 2) + 0xfe007400)
+#define PSRAM_DBUF_3 ((0x0093 << 2) + 0xfe007400)
+#define PSRAM_DBUF_4 ((0x0094 << 2) + 0xfe007400)
+#define PSRAM_DBUF_5 ((0x0095 << 2) + 0xfe007400)
+#define PSRAM_DBUF_6 ((0x0096 << 2) + 0xfe007400)
+#define PSRAM_DBUF_7 ((0x0097 << 2) + 0xfe007400)
+#define PSRAM_DBUF_8 ((0x0098 << 2) + 0xfe007400)
+#define PSRAM_DBUF_9 ((0x0099 << 2) + 0xfe007400)
+#define PSRAM_DBUF_A ((0x009a << 2) + 0xfe007400)
+#define PSRAM_DBUF_B ((0x009b << 2) + 0xfe007400)
+#define PSRAM_DBUF_C ((0x009c << 2) + 0xfe007400)
+#define PSRAM_DBUF_D ((0x009d << 2) + 0xfe007400)
+#define PSRAM_DBUF_E ((0x009e << 2) + 0xfe007400)
+#define PSRAM_DBUF_F ((0x009f << 2) + 0xfe007400)
+#define PSRAM_CFG_STS ((0x00a0 << 2) + 0xfe007400)
+ //32bits register to save the USR read command read back values.
+#define PSRAM_STATUS ((0x00a1 << 2) + 0xfe007400)
+ //bit 31. usr_req_done flag. 1 : user request done . write 1 to clean.
+ //bit 30~11.
+ //bit 10:8
+ //bit 7:3.
+ //bit 2. axi_data buffer idle bit. 1 : idle. 0 : working.
+ //bit 1. axi interface idle bit. 1 : idle. 0 : working.
+ //bit 0. psram ctrl idle bit. 1 : idle. 0 : working.
+#define PSRAM_CTRL ((0x00a2 << 2) + 0xfe007400)
+ //bit 31. PSRAM in DTR mode.
+ //bit 30. psram input data latch clock select. 1: from clock input pin. 0: from DQS
+ //if use clock input pin as data input latch clock, bit 13:12 should select 01.
+ //bit 29:27. PSRAM mode.
+ //'b000 : STR SPI mode.
+ //'b001 : STR QPI mode.
+ //'b010 : DTR QPI mode.
+ //'b011 : DTR OPI FLASH.
+ //'b100 : APmemory PSRAM mode.
+ //'b101 : Winbond PSRAM mode.
+ //bit 26. enable to generation interruption after usr request done. 1: enable. 0: disable.
+ //bit 25. to enable APMEMORY 2 command cycle mode. 1 : enable : 0: 3 command cycles.
+ //bit 24. to enable the psram clock output always enable. 1 : enable. 0: disable.
+ //bit 23. to enable the psram clock output extend mode to cover APMEMORY tCPI.
+ //bit 22. to disable the CKN output. 1: disable PSRAM CK_N pin output. 0: CK_N working normal.
+ //bit 21. PSRAM DATA IN/OUT high 8bit and low 8 bit endian. 1 : rising edge is low byte. falling edge data is high byte. 0 : rising edge is high byte. falling edge data is low byte.
+ //bit 20. PSRAM ADDRESS unit. 1: Byte. 0 : word.
+ // APMEMORY used byte address. Winbond use word address.
+ //bit 19. DQSEN generation. if use dqs to latch input data, this bit should be set to 1 to ask DMC generate ENABLE singal in dummy stage. 0: not generate DQS_EN.
+ //bit 18. PSRAM RESET I/O oe_n value. if need RESET pin.
+ //bit 17. PSRAM RESET I/O output vale. if need reset pin.
+ //bit 16. force CS output low. for APMEMORY exit DPPD mode. 1: to force cs output low : 0 output normal working mode.
+ //bit 13:12. psram data in clock enable selection. 00: use DQSEN. 01: use clkin cnt.
+ //bit 11. DM Disable. 1: disable DM output. 0: with dmoutput.
+ //bit 9. psram pctl auto clock gating enable. 1: enable. 0 : disable.
+ //bit 8. psram pctl clock disable. 1: disable. 0 : enable.
+ //bit 2 PSRAM SPI mode, DQ2 works as WP(write protection mode).
+ //bit 1. DQ2 WP mode value.
+ //bit 0. PSRAM SPI mode, DQ3 works as HOLD function.
+#define PSRAM_PIN_CTRL ((0x00a3 << 2) + 0xfe007400)
+//bit 30:28 DATA 6 DQ pin selection.
+//bit 27:24 DATA 6 DQ pin selection.
+//bit 22:20 DATA 5 DQ pin selection.
+//bit 18:16 DATA 4 DQ pin selection.
+//bit 14:12 DATA 3 DQ pin selection.
+//bit 10:8 DATA 2 DQ pin selection.
+//bit 6:4 DATA 1 DQ pin selection.
+//bit 2:0 DATA 0 DQ pin selection.
+ //0 : from DQ[0]
+ //1 : from DQ[1]
+ //2 : from DQ[2]
+ //3 : from DQ[3]
+ //4 : from DQ[4]
+ //5 : from DQ[5]
+ //6 : from DQ[6]
+ //7 : from DQ[7]
+//psram_dly_16 is used for all DQ[0~] in/out/oen delay adjustment.
+//psram_dly_16 consists of 15 delay cells, one delay cell is 50ps delay( typical corner).
+//psram_dly_16 is control by delay_sel[3:0]. 0 = no delay. 1~15 controls how many delay cells used.
+//psram_dly_16 can be controlled by each control register either with real delay mode or VT updated with 4xclock period.
+//psram_lcdl is used for DQS/DQSN input and CK/CKN output delay 90degree delay generation and/or delay fine tune.
+//psram_lcdl consits of 96 delay cells, same delay cell used in psram_dly_16.
+//psram_lcdl should be calibrated with the psram_4xclock. and tracked with psram_4xclock with VT updated.
+#define PSRAM_DQ0_DIN_DLY ((0x00c0 << 2) + 0xfe007400)
+ //bit 6:0. DQ0 DIN delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ1_DIN_DLY ((0x00c1 << 2) + 0xfe007400)
+ //bit 6:0. DQ1 input delay control. in DLY16 read mode, only [3:0] is valid.
+#define PSRAM_DQ2_DIN_DLY ((0x00c2 << 2) + 0xfe007400)
+ //bit 6:0. DQ2 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ3_DIN_DLY ((0x00c3 << 2) + 0xfe007400)
+ //bit 6:0. DQ3 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ4_DIN_DLY ((0x00c4 << 2) + 0xfe007400)
+ //bit 6:0. DQ4 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ5_DIN_DLY ((0x00c5 << 2) + 0xfe007400)
+ //bit 6:0. DQ5 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ6_DIN_DLY ((0x00c6 << 2) + 0xfe007400)
+ //bit 6:0. DQ6 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ7_DIN_DLY ((0x00c7 << 2) + 0xfe007400)
+ //bit 6:0. DQ7 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ0_DOUT_DLY ((0x00c8 << 2) + 0xfe007400)
+ //bit 6:0. DQ0 DOUT delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ1_DOUT_DLY ((0x00c9 << 2) + 0xfe007400)
+ //bit 6:0. DQ1 output delay control. in DLY16 read mode, only [3:0] is valid.
+#define PSRAM_DQ2_DOUT_DLY ((0x00ca << 2) + 0xfe007400)
+ //bit 6:0. DQ2 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ3_DOUT_DLY ((0x00cb << 2) + 0xfe007400)
+ //bit 6:0. DQ3 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ4_DOUT_DLY ((0x00cc << 2) + 0xfe007400)
+ //bit 6:0. DQ4 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ5_DOUT_DLY ((0x00cd << 2) + 0xfe007400)
+ //bit 6:0. DQ5 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ6_DOUT_DLY ((0x00ce << 2) + 0xfe007400)
+ //bit 6:0. DQ6 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ7_DOUT_DLY ((0x00cf << 2) + 0xfe007400)
+ //bit 6:0. DQ7 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ0_OEN_DLY ((0x00d0 << 2) + 0xfe007400)
+ //bit 6:0. DQ0 OEN delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ1_OEN_DLY ((0x00d1 << 2) + 0xfe007400)
+ //bit 6:0. DQ1 output enable delay control. in DLY16 read mode, only [3:0] is valid.
+#define PSRAM_DQ2_OEN_DLY ((0x00d2 << 2) + 0xfe007400)
+ //bit 6:0. DQ2 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ3_OEN_DLY ((0x00d3 << 2) + 0xfe007400)
+ //bit 6:0. DQ3 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ4_OEN_DLY ((0x00d4 << 2) + 0xfe007400)
+ //bit 6:0. DQ4 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ5_OEN_DLY ((0x00d5 << 2) + 0xfe007400)
+ //bit 6:0. DQ5 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ6_OEN_DLY ((0x00d6 << 2) + 0xfe007400)
+ //bit 6:0. DQ6 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQ7_OEN_DLY ((0x00d7 << 2) + 0xfe007400)
+ //bit 6:0. DQ7 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DM_DOUT_DLY ((0x00d8 << 2) + 0xfe007400)
+ //bit 6:0. DM output delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DM_OEN_DLY ((0x00d9 << 2) + 0xfe007400)
+ //bit 6:0. DM output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_CS_DOUT_DLY ((0x00da << 2) + 0xfe007400)
+ //bit 6:0. CS output delay control. in DLY16 real mode, only [3:0] is valid.
+#define PSRAM_DQS_DIN_DLY ((0x00db << 2) + 0xfe007400)
+ //bit 6:0. DQS input delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+ // unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define PSRAM_DQSN_DIN_DLY ((0x00dc << 2) + 0xfe007400)
+ //bit 6:0. DQSN input delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+ // unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define PSRAM_CKN_DOUT_DLY ((0x00dd << 2) + 0xfe007400)
+ //bit 6:0. CKN output delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+ // unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define PSRAM_CK_DOUT_DLY ((0x00de << 2) + 0xfe007400)
+ //bit 6:0. CK output delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+ // unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define PSRAM_RDEN_DLY ((0x00df << 2) + 0xfe007400)
+ //bit 10:7. READ enable phase delay. unit = 1UI. for AP QPI PSRAM. PSRAM only send one cycle DQS preamble.
+ // We have to used this UI delay to compensate the whole clock output delay and the DQS input delay.
+ // if run high frequency, this delay need to be trained. the valid value from 0 ~ 12. Since one UI is 1/4 of PSRAM clock,
+ // the total delay of the clock output delay + input delay should be less than 3 PSRAM clock.
+ //bit 6:0. READ enable fine tune delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+ // unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define PSRAM_LCDL_CTRL ((0x00f0 << 2) + 0xfe007400)
+ //bit 31. write 1 to update all delay cell delays control.
+ //bit 30. write 1 to calibration LCDL.
+ //bit 29. LCDL track enable. 1: enable LCDL auto track VT changes.
+ //bit 28. LCDL delay control mode.
+ //1 : real delay mode. For DQS/DQSN/CKN/CK/RDEN delay control register, one number means one delay cells.
+ //0 : UI MODE. For DQS/DQSN/CKN/CK/RDEN delay control register, one number means 1/64 psram_4xclk period.
+ //bit 27. DLY16 ( psram_dly_16 cell) delay control mode.
+ //1 : real delay mode. For all data delay control register, one number means one delay cells.
+ //0 : UI MODE. For all data delay control register, one number means 1/64 psram_4xclk period.
+ //bit 27:24. not used.
+ //bit 23:0. timer do trigger LCDL track the VT once. each track will compensate the UI with 1/16 delay cell delay.
+//LCDL calibration ctroller.
+#define PSRAM_LCDL_CAL_CTRL1 ((0x00f1 << 2) + 0xfe007400)
+ //27:24. which LCDL delay line used to run calibration.
+ //19:16. LCDL calibration loop end position.
+ //15:12. LCDL calibration loop initial position.
+ //10:0. LCDL calibration initial phase counter.
+#define PSRAM_LCDL_CAL_CTRL2 ((0x00f2 << 2) + 0xfe007400)
+ //26:16 LCDL phase lock limit. if the lcdl phase counter difference between 2 calibration loops is less than this number, The LCDL would be locked and stop the calibration.
+ //10:0. deta_init. the first loop phase changing number.
+#define PSRAM_LCDL_CAL_CTRL3 ((0x00f3 << 2) + 0xfe007400)
+ //29:25 to configure LCDL calibration step 5 position.
+ //24:20 to configure LCDL calibration step 4 position.
+ //19:15 to configure LCDL calibration step 3 position.
+ //14:10 to configure LCDL calibration step 2 position.
+ //9:5 to configure LCDL calibration step 1 position.
+ //4:0 to configure LCDL calibration step 0 position.
+#define PSRAM_LCDL_CAL_CTRL4 ((0x00f4 << 2) + 0xfe007400)
+ //19:15 to configure LCDL calibration step 9 position.
+ //14:10 to configure LCDL calibration step 8 position.
+ //9:5 to configure LCDL calibration step 7 position.
+ //4:0 to configure LCDL calibration step 6 position.
+#define PSRAM_CLK_UI ((0x00f5 << 2) + 0xfe007400)
+ //bit 6:0. 4xCLOCK period delay measured from LCDL calibration.
+#define PSRAM_LCDL_PH ((0x00f6 << 2) + 0xfe007400)
+ //10:0 LCDL phase counter after calibration.
+#define PSRAM_LCDL_STATUS ((0x00f7 << 2) + 0xfe007400)
+ //bit 31. LCDL lock status. 1: LCDL locked to 4x clock.
+//`endif
+//
+// Closing file: ../psram/rtl/psram_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_sec.vh
+//
+//`ifdef DMC_SEC_REG_DEFINE
+//`else
+//`define DMC_SEC_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd021000
+// -----------------------------------------------
+//`define DMC_SEC_REG_BASE 32'hfd021000
+// ID assignment inside DMC..
+// id[12 :0] total 13 bit ID.
+// id[12] == 1: for DMC internal TEST module.
+// id[12] == 0: for AXI port input.
+// id[11:0] == AXI port ID.
+// id[2:0] == 0 : A55 CPU.
+// id[2:0] == 1 : DSPA
+// id[2:0] == 2 : DSPB
+// id[2:0] == 3 : Not used.
+// id[2:0] == 4 : for Device.
+ //Device sublevel ID.
+ //id[9:7] == 5 : for audio. id[3] == 0: audio
+ //id[9:7] == 6 : for DMA. id[6:4] for DMA thread id. id[3] for DMC security level.
+ //id[9:7] == others: for device other masters.
+// id[2:0] == 5 : for USB device.
+// id[2:0] == 6 : for I2C debug input.
+// id[2:0] == 7 : for USB host.
+#define DMC_SEC_RANGE0_STA ((0x0000 << 2) + 0xfd021000)
+ //bit 31:12. range0 start address. in 4KB boundary.
+#define DMC_SEC_RANGE0_EDA ((0x0001 << 2) + 0xfd021000)
+ //bit 31:12. range0 end address. in 4KB boundary.
+#define DMC_SEC_RANGE0_RID_CTRL ((0x0002 << 2) + 0xfd021000)
+ //range 0 read access enable based on DMC ID assignments.
+ //bit 28. for AXI port 3. Not used in A1. should be 0.
+ //bit 27. for dmc_test. 1 = enable. 0 = disable.
+ //bit 26. for usbhost. 1 = enable. 0 = disable.
+ //bit 25. for i2c. 1 = enable. 0 = disable.
+ //bit 24. for usbdevide. 1 = enable. 0 = disable.
+ //bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+ //bit 22:18.for AXI device sub level id 5 ~ 0.
+ //bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0).
+ //bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0).
+ //bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+ //bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+ //bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define DMC_SEC_RANGE0_WID_CTRL ((0x0003 << 2) + 0xfd021000)
+ //range 0 write access enable based on DMC ID assignments.
+ //bit 28. for AXI port 3. Not used in A1. should be 0.
+ //bit 27. for dmc_test. 1 = enable. 0 = disable.
+ //bit 26. for usbhost. 1 = enable. 0 = disable.
+ //bit 25. for i2c. 1 = enable. 0 = disable.
+ //bit 24. for usbdevide. 1 = enable. 0 = disable.
+ //bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+ //bit 22:18.for AXI device sub level id 5 ~ 0.
+ //bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0).
+ //bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5).
+ //bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+ //bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+ //bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define DMC_SEC_RANGE1_STA ((0x0004 << 2) + 0xfd021000)
+ //bit 31:12. range1 start address. in 4KB boundary.
+#define DMC_SEC_RANGE1_EDA ((0x0005 << 2) + 0xfd021000)
+ //bit 31:12. range0 end address. in 4KB boundary.
+#define DMC_SEC_RANGE1_RID_CTRL ((0x0006 << 2) + 0xfd021000)
+ //range 1 read access enable based on DMC ID assignments.
+ //bit 28. for AXI port 3. Not used in A1. should be 0.
+ //bit 27. for dmc_test. 1 = enable. 0 = disable.
+ //bit 26. for usbhost. 1 = enable. 0 = disable.
+ //bit 25. for i2c. 1 = enable. 0 = disable.
+ //bit 24. for usbdevide. 1 = enable. 0 = disable.
+ //bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+ //bit 22:18.for AXI device sub level id 5 ~ 0.
+ //bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0).
+ //bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0).
+ //bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+ //bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+ //bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define DMC_SEC_RANGE1_WID_CTRL ((0x0007 << 2) + 0xfd021000)
+ //range 1 write access enable based on DMC ID assignments.
+ //bit 28. for AXI port 3. Not used in A1. should be 0.
+ //bit 27. for dmc_test. 1 = enable. 0 = disable.
+ //bit 26. for usbhost. 1 = enable. 0 = disable.
+ //bit 25. for i2c. 1 = enable. 0 = disable.
+ //bit 24. for usbdevide. 1 = enable. 0 = disable.
+ //bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+ //bit 22:18.for AXI device sub level id 5 ~ 0.
+ //bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0).
+ //bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5).
+ //bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+ //bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+ //bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define DMC_SEC_RANGE2_STA ((0x0008 << 2) + 0xfd021000)
+ //bit 31:12. range2 start address. in 4KB boundary.
+#define DMC_SEC_RANGE2_EDA ((0x0009 << 2) + 0xfd021000)
+ //bit 31:12. range2 end address. in 4KB boundary.
+#define DMC_SEC_RANGE2_RID_CTRL ((0x000a << 2) + 0xfd021000)
+ //range 2 read access enable based on DMC ID assignments.
+ //bit 28. for AXI port 3. Not used in A1. should be 0.
+ //bit 27. for dmc_test. 1 = enable. 0 = disable.
+ //bit 26. for usbhost. 1 = enable. 0 = disable.
+ //bit 25. for i2c. 1 = enable. 0 = disable.
+ //bit 24. for usbdevide. 1 = enable. 0 = disable.
+ //bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+ //bit 22:18.for AXI device sub level id 5 ~ 0.
+ //bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0).
+ //bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0).
+ //bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+ //bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+ //bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define DMC_SEC_RANGE2_WID_CTRL ((0x000b << 2) + 0xfd021000)
+ //range 2 write access enable based on DMC ID assignments.
+ //bit 28. for AXI port 3. Not used in A1. should be 0.
+ //bit 27. for dmc_test. 1 = enable. 0 = disable.
+ //bit 26. for usbhost. 1 = enable. 0 = disable.
+ //bit 25. for i2c. 1 = enable. 0 = disable.
+ //bit 24. for usbdevide. 1 = enable. 0 = disable.
+ //bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+ //bit 22:18.for AXI device sub level id 5 ~ 0.
+ //bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0).
+ //bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5).
+ //bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+ //bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+ //bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define DMC_SEC_RANGE3_STA ((0x000c << 2) + 0xfd021000)
+ //bit 31:12. range3 start address. in 4KB boundary.
+#define DMC_SEC_RANGE3_EDA ((0x000d << 2) + 0xfd021000)
+ //bit 31:12. range3 end address. in 4KB boundary.
+#define DMC_SEC_RANGE3_RID_CTRL ((0x000e << 2) + 0xfd021000)
+ //range 3 read access enable based on DMC ID assignments.
+ //check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define DMC_SEC_RANGE3_WID_CTRL ((0x000f << 2) + 0xfd021000)
+ //range 3 write access enable based on DMC ID assignments.
+ //check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+#define DMC_SEC_RANGE4_STA ((0x0010 << 2) + 0xfd021000)
+ //bit 31:12. range4 start address. in 4KB boundary.
+#define DMC_SEC_RANGE4_EDA ((0x0011 << 2) + 0xfd021000)
+ //bit 31:12. range4 end address. in 4KB boundary.
+#define DMC_SEC_RANGE4_RID_CTRL ((0x0012 << 2) + 0xfd021000)
+ //range 4 read access enable based on DMC ID assignments.
+ //check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define DMC_SEC_RANGE4_WID_CTRL ((0x0013 << 2) + 0xfd021000)
+ //range 4 write access enable based on DMC ID assignments.
+ //check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+#define DMC_SEC_RANGE5_STA ((0x0014 << 2) + 0xfd021000)
+ //bit 31:12. range5 start address. in 4KB boundary.
+#define DMC_SEC_RANGE5_EDA ((0x0015 << 2) + 0xfd021000)
+ //bit 31:12. range5 end address. in 4KB boundary.
+#define DMC_SEC_RANGE5_RID_CTRL ((0x0016 << 2) + 0xfd021000)
+ //range 5 read access enable based on DMC ID assignments.
+ //check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define DMC_SEC_RANGE5_WID_CTRL ((0x0017 << 2) + 0xfd021000)
+ //range 5 write access enable based on DMC ID assignments.
+ //check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+#define DMC_SEC_RANGE6_STA ((0x0018 << 2) + 0xfd021000)
+ //bit 31:12. range5 start address. in 4KB boundary.
+#define DMC_SEC_RANGE6_EDA ((0x0019 << 2) + 0xfd021000)
+ //bit 31:12. range6 end address. in 4KB boundary.
+#define DMC_SEC_RANGE6_RID_CTRL ((0x001a << 2) + 0xfd021000)
+ //range 6 read access enable based on DMC ID assignments.
+ //check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define DMC_SEC_RANGE6_WID_CTRL ((0x001b << 2) + 0xfd021000)
+ //range 6 write access enable based on DMC ID assignments.
+ //check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+//range 7 is default range if the access not hit any of the previous 7 range, if would hit range 7.
+#define DMC_SEC_RANGE7_RID_CTRL ((0x001c << 2) + 0xfd021000)
+ //range 7 read access enable based on DMC ID assignments.
+ //check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define DMC_SEC_RANGE7_WID_CTRL ((0x001d << 2) + 0xfd021000)
+ //range 7 write access enable based on DMC ID assignments.
+ //check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+#define DMC_SEC_RANGE_CTRL ((0x001e << 2) + 0xfd021000)
+ //bit 23:16 8 range security level. to chosse with DES KEY to use data describle.
+ //bit 7:0 8 range enable. each bit for one range to indentify the range is enabled or not.
+//registers to check the security protection and watch point error information.
+#define DMC_DES_CTRL ((0x0020 << 2) + 0xfd021000)
+ //bit 1 data describle enable.
+ //bit 0 wirte 1 to block DES CTRL and DES PADDING read/write.
+#define DMC_DES_PADDING ((0x0021 << 2) + 0xfd021000)
+#define DMC_SEC_STATUS ((0x00b8 << 2) + 0xfd021000)
+ //bit 31~2. not used.
+ //bit 1 write security violation.
+ //bit 0. read security violation.
+#define DMC_VIO_ADDR0 ((0x00b9 << 2) + 0xfd021000)
+ //ddr0 write secure violation address.
+#define DMC_VIO_ADDR1 ((0x00ba << 2) + 0xfd021000)
+ //bit 31:18 . not used. always 0.
+ //17 ddr0 secure check violation.
+ //16 ddr0 write address overflow. write out of DDR size.
+ //15:13. ddr0 write violation AWPROT bits.
+ //12:0 ddr0_write violation ID. Please check ID assignment for ID bit defines.
+#define DMC_VIO_ADDR2 ((0x00bb << 2) + 0xfd021000)
+ //ddr0 write secure violation address.
+#define DMC_VIO_ADDR3 ((0x00bc << 2) + 0xfd021000)
+ //bit 31:18 . not used. always 0.
+ //17 ddr0 secure check violation.
+ //16 ddr0 read address overflow. write out of DDR size.
+ //15:13. ddr0 read violation AWPROT bits.
+ //12:0 ddr0_read violation ID. please ID assignment for ID bit defines.
+//DDR0_ADDRMAP is used for RANK0 bank, row, col address mapping from AXI 32bits linear address.
+#define DDR0_ADDRMAP_0 ((0x00d0 << 2) + 0xfd021000)
+ //29:25 ca8.
+ //24:20 ca7.
+ //19:15 ca6.
+ //14:10 ca5.
+ //9:5 ca4.
+ //4:0 ca3.
+#define DDR0_ADDRMAP_1 ((0x00d1 << 2) + 0xfd021000)
+ //29:25 ra2.
+ //24:20 ra1.
+ //19:15 ra0.
+ //14:10 ca11.
+ //9:5 ca10.
+ //4:0 ca9.
+#define DDR0_ADDRMAP_2 ((0x00d2 << 2) + 0xfd021000)
+ //29:25 ra8.
+ //24:20 ra7.
+ //19:15 ra6.
+ //14:10 ra5.
+ //9:5 ra4.
+ //4:0 ra3.
+#define DDR0_ADDRMAP_3 ((0x00d3 << 2) + 0xfd021000)
+ //29:25 ra14.
+ //24:20 ra13.
+ //19:15 ra12.
+ //14:10 ra11.
+ //9:5 ra10.
+ //4:0 ra9.
+#define DDR0_ADDRMAP_4 ((0x00d4 << 2) + 0xfd021000)
+ //29:25 ra16 for DDR4 SDRAM
+ //24:20 bg1 for DDR4 SDRAM.
+ //19:15 ba2. or bg0 for DDR4.
+ //14:10 ba1.
+ //9:5 ba0.
+ //4:0 ra15.
+#define DMC_DDR_CTRL ((0x00da << 2) + 0xfd021000)
+ // DDR PHY and DMC only supports 16bits and rank0 only.
+ //bit 24:22 3'b000 : ddr3 mode.
+ //3'b001 : ddr4 mode.
+ //3'b010 : lpddr3 mode.
+ //3'b011 : lpddr4 mode.
+ //bit 20 DDR4 BG1 enable bit.
+ //bit 3:0 : DDR rank 0 size bit [2:0].
+ //4'b0000 : DDR rank 0 is 128Mbyte.
+ //4'b0001 : DDR rank 0 is 256Mbyte.
+ //4'b0010 : DDR rank 0 is 512Mbyte.
+ //4'b0011 : DDR rank 0 is 1Gbyte.
+ //4'b0100 : DDR rank 0 is 2Gbyte.
+ //4'b0101 : DDR rank 0 is 4Gbyte.
+ //4'b1000 : DDR rank 0 is 4Gbyte.
+ //4'b1001 : DDR rank 0 is 4Gbyte.
+ //others : reserved.
+#define DMC_APB_SEC_CTRL ((0x00db << 2) + 0xfd021000)
+ //bit 19:16. DMC normal APB register secure control.
+ //bit 19: 1: all can write those register. 0: the APB_PROT[0] must match the bit 16 to access those regsiter.
+ //Bit15:12. DMC sticky APB regsiter secure control.
+ //bit 15. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 12 to access those register.
+ //bit 11:8. not used.
+ //Bit 7:4. DMC DDR SDRAM protocal contorl register contorl
+ //bit 11. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 4 to access those register.
+ //bit 3:0. PHY APB regsiter secure control.
+ //bit 3. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 0 to access those register.
+#define DMC_DDR_PHY_CTRL ((0x00bf << 2) + 0xfd021000)
+ //bit 4 PwrOkIn
+ //bit 3. PHY APB soft reset_n
+ //bit 2. PHY soft reset_n
+ //bit 1. PHY DfiClk enable.
+ //bit 0. PHY DfiCtlClk enable.
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd021400
+// -----------------------------------------------
+//`define DMC_TEST_REG_BASE 32'hfd021400
+#define DMC_TEST_WRCMD_ADDR ((0x00dc << 2) + 0xfd021400)
+ // the current write cmd address.
+#define DMC_TEST_RDRSP_ADDR ((0x00dd << 2) + 0xfd021400)
+ // the failed read response address(for error data )
+#define DMC_TEST_RDCMD_ADDR ((0x00de << 2) + 0xfd021400)
+ // the current read command address.
+#define DMC_TEST_WDG ((0x00df << 2) + 0xfd021400)
+ //31:16. write response watch dog.
+ //15:0. read response watch dog.
+#define DMC_TEST_STA ((0x00e0 << 2) + 0xfd021400)
+ //test start address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary.
+ // for sha mode, address must be in 64 bytes boundary. that mean the last 6 bits must be 0.
+#define DMC_TEST_EDA ((0x00e1 << 2) + 0xfd021400)
+ //test end address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary.
+ // for sha mode, address must be in 64 bytes boundary. that mean the last 6bits must be 1.
+#define DMC_TEST_CTRL ((0x00e2 << 2) + 0xfd021400)
+ //bit 31. enable test.
+ //bit 30. when enable test, enable the write to DDR function.
+ //bit 29. when enable test, enable the read from DDR function.
+ //bit 28. Not used.
+ //bit 27. enabe to compare data. when do the read enable to enable the error comparaion. suppose the read data should be same as the data in the write buffer.
+ //bit 26. Not used.
+ //bit 25. address generation type. 0: continuous increase the address in the range of test start address and test end address.
+ // 1: test module would pick the random address from test start address and test end address.
+ //bit 24. done type. 0 : use the DMC_TEST_NUM register as the counter of test numbers.
+ // for write if the write command number == the DMC_TEST_NUM, the write is done.
+ // for read if the read command number == the DMC TEST_num, the read id done. for one read command can be repeated repeat number times.
+ // 1 : finshed at end address.
+ //bit 23. wdata type. 1 : the first write is {WD3, WD2,WD1,WD0}, then the latter is the previous data plus a pattern.( { + WD7, + WD6, + WD5, + WD4}).
+ // 0 : the WDATA is the data in write register.
+ //bit 23. Not used.
+ //bit 22:20. read repeat times. for non-sha function, we can define multi times of the read. the test module would repeat the same adddress repeat times.
+ //bit 19. limit write. 0: no outstanding write request limitation.
+ // 1: limit the outstanding write commands to the number of bits [15:8]
+ //bit 18. limit read. 0. no outstanding read request limitation.
+ // 1. limit the read outstanding request to the number of bits[7:0].
+ //bit 17:16. Not used.
+ //bit 15:8. write outstanding commands limit.
+ //bit 7:0. read outstanding commands limit.
+#define DMC_TEST_NUM ((0x00e3 << 2) + 0xfd021400)
+ // how many test command for the test if the DMC_TEST_CTRL bit 24 is 0.
+#define DMC_TEST_WD0 ((0x00e4 << 2) + 0xfd021400)
+ // write data 0 for write command. also for read back data comparision.
+#define DMC_TEST_WD1 ((0x00e5 << 2) + 0xfd021400)
+ // write data 1 for write command. also for read back data comparision.
+#define DMC_TEST_WD2 ((0x00e6 << 2) + 0xfd021400)
+ // write data 2 for write command. also for read back data comparision.
+#define DMC_TEST_WD3 ((0x00e7 << 2) + 0xfd021400)
+ // write data 3 for write command. also for read back data comparision.
+#define DMC_TEST_WD4 ((0x00e8 << 2) + 0xfd021400)
+ // write data 4 for write command. also for read back data comparision.
+#define DMC_TEST_WD5 ((0x00e9 << 2) + 0xfd021400)
+ // write data 5 for write command. also for read back data comparision.
+#define DMC_TEST_WD6 ((0x00ea << 2) + 0xfd021400)
+ // write data 6 for write command. also for read back data comparision.
+#define DMC_TEST_WD7 ((0x00eb << 2) + 0xfd021400)
+ // write data 7 for write command. also for read back data comparision.
+#define DMC_TEST_RD0 ((0x00ec << 2) + 0xfd021400)
+ // the read back data 0. if error happens, it would capture the first error data.
+#define DMC_TEST_RD1 ((0x00ed << 2) + 0xfd021400)
+ // the read back data 1. if error happens, it would capture the first error data.
+#define DMC_TEST_RD2 ((0x00ee << 2) + 0xfd021400)
+ // the read back data 2. if error happens, it would capture the first error data.
+#define DMC_TEST_RD3 ((0x00ef << 2) + 0xfd021400)
+ // the read back data 3. if error happens, it would capture the first error data.
+#define DMC_TEST_RD4 ((0x00f0 << 2) + 0xfd021400)
+ // the read back data 4. if error happens, it would capture the first error data.
+#define DMC_TEST_RD5 ((0x00f1 << 2) + 0xfd021400)
+ // the read back data 5. if error happens, it would capture the first error data.
+#define DMC_TEST_RD6 ((0x00f2 << 2) + 0xfd021400)
+ // the read back data 6. if error happens, it would capture the first error data.
+#define DMC_TEST_RD7 ((0x00f3 << 2) + 0xfd021400)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_ERR_ADDR ((0x00f4 << 2) + 0xfd021400)
+ // it capature the first error address.
+#define DMC_TEST_ERR_CNT ((0x00f5 << 2) + 0xfd021400)
+ // how many data error happens in the whole test period.
+#define DMC_TEST_STS ((0x00f6 << 2) + 0xfd021400)
+ //bit 31, test done bit. write 1 to clean.
+ //bit 30, indicate address err
+ //bit 29~7. not used.
+ //bit 6. read data resp error(caused by security or rd latency).
+ //bit 5. test MRR/MPR rd latency error. write 1 clear
+ //bit 4, sha done. write 1 to clean.
+ //bit 3, write done. write 1 to clean.
+ //bit 2, read done. write 1 to clean
+ //bit 1, write watchdog triggered. write 1 to clean
+ //bit 0, read watchdog triggered. write 1 to clean.
+#define DMC_TEST_COMP_MASK ((0x0033 << 2) + 0xfd021400)
+ //32bits for DMC TEST COMPARE bit enable.
+ //1 : to MASK this bit. 0: compare this bit.
+#define DMC_TEST_RDBI0 ((0x0034 << 2) + 0xfd021400)
+ //MPC RD FIFO command DBI read back data
+ //bit 31:16 the second cycle.
+ //bit 15:0 the first cycle.
+#define DMC_TEST_RDBI1 ((0x0035 << 2) + 0xfd021400)
+ //MPC RD FIFO command DBI read back data
+ //bit 31:16. the Forth cycle.
+ //bit 15:0. the third cycle.
+#define DMC_TEST_WSTRB0 ((0x0036 << 2) + 0xfd021400)
+ //MPC WR FIFO command DM bit write data
+ //bit 31:16 the second cycle.
+ //bit 15:0 the first cycle.
+#define DMC_TEST_DRAM_CMD ((0x0038 << 2) + 0xfd021400)
+ //bit 31. cmd done. write 0 to clean.
+ //bit 30. data done. write 0 to clean.
+ //bit 4:0. only one bit can be 1. read data stored in DMC_TEST_RD* write data from DMC_TEST_W
+ //bit 4. LPDDR4 MPC write data command( MPC WR FIFO). Not support LPDDR4 in A1.
+ //bit 3. LPDDR4 MPC read data command (MPC RD Calibration and RD FIFO).Not support LPDDR4 in A1.
+ //bit 2. LPDDR4 MPC-1 command ( NOP, Start DQS interval ....)Not support LPDDR4 in A1.
+ //bit 1. mrr comand.
+ //bit 0. mrw command.
+#define DMC_TEST_DRAM_CMD_CODE ((0x0039 << 2) + 0xfd021400)
+ //bit 27:26. 128bits data cycles . 0: 1 clock cycles; 1: 2 clock cycles; 2: 3 clock cycles; 3:4 clock cycles.
+ // LPDDR4 32bits: 4 clock cycles; LPDDR4 16bits: 2 clock cycles;
+ // DDR3/4/LPDDR3 32 bits : 2 clock cycles. DDR3/4 16bits: 1 cycles.
+ //bit 25 MRW/MRR/MPC command rank 1 select. 1: select. 0: not select. In A1, only rank0 supported.
+ //bit 24. MRW/MRR/MPC command rank 0 select. 1: select. 0: not select.In A1, only rank0 supported.
+ //bit 23:16 MR addr. DDR4 case : 18:16 ba[2:0]. 20:19 BG[1:0].
+ //bit 15:0 opcode.
+#define DMC_TEST_DRAM_CMD_TIME ((0x003a << 2) + 0xfd021400)
+//bit 31:16 PRE CMD timer. //delay how many cycle to start the command.
+//bit 15:0 POST CMD timer //delay how many cycle after the command execute.
+//`endif
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_sec.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_reg.vh
+//
+//`ifdef DMC_REG_DEFINE
+//`else
+//`define DMC_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd020000
+// -----------------------------------------------
+//`define DMC_REG_BASE 32'hfd020000
+#define DMC_SOFT_RST2 ((0x0003 << 2) + 0xfd020000)
+ //bit 31~11. reserved for future.
+ //bit 10 DMC DFI cmd soft reset_n
+ //bit 9 DMC DFI MISC soft reset_n
+ //bit 8 DMC DFI data soft reset_n
+ //bit 7 DMC DFI dcu soft reset_n
+ //bit 6 DMC siu soft reset_n
+ //bit 5. DMC test soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 4. DMC low power control moudle soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 3. DMC QOS monitor module soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 2. DMC register modle soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 1. DMC canvas transfer module soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 0. DMC command buffers and command generation modules soft reset. 0 = reset. 1:
+#define DMC_VERSION ((0x0005 << 2) + 0xfd020000)
+ //read only 32'h000b0000. for A1
+#define DMC_MON_CTRL0 ((0x0020 << 2) + 0xfd020000)
+ //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
+ //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
+ //bit 1. qos monitor 1 enable.
+ //bit 0. qos monitor 0 enable.
+#define DMC_MON_CTRL1 ((0x0021 << 2) + 0xfd020000)
+ //bit 8:0. qos monitor 0 channel select.
+ //bit 8 to select DMC TEST
+ //bit 7:0 each bit enable one AXI subID.
+#define DMC_MON_CTRL2 ((0x0022 << 2) + 0xfd020000)
+ //bit 8. to enabe monitor 0 second level subID selection for example device.
+ //bit 7:0 each bit to enable one second level subID inside device.
+#define DMC_MON_CTRL3 ((0x0023 << 2) + 0xfd020000)
+ //bit 8:0. qos monitor 1 channel select.
+ //bit 8 to select DMC TEST
+ //bit 7:0 each bit enable one AXI subID.
+#define DMC_MON_CTRL4 ((0x0024 << 2) + 0xfd020000)
+ //bit 8. to enabe monitor 1 second level subID selection for example device.
+ //bit 7:0 each bit to enable one second level subID inside device.
+#define DMC_MON_ALL_REQ_CNT ((0x0029 << 2) + 0xfd020000)
+ // at the test period, the whole MMC request time.
+#define DMC_MON_ALL_GRANT_CNT ((0x002a << 2) + 0xfd020000)
+ // at the test period, the whole MMC granted data cycles. 64bits unit.
+#define DMC_MON_ONE_GRANT_CNT ((0x002b << 2) + 0xfd020000)
+ // at the test period, the granted data cycles for the selected channel and ports.
+#define DMC_MON_SEC_GRANT_CNT ((0x002c << 2) + 0xfd020000)
+ // at the test period, the granted data cycles for the selected channel and ports.
+#define DMC_MON_TIMER ((0x002f << 2) + 0xfd020000)
+ // timer for the monitor period.
+#define DMC_CLKG_CTRL2 ((0x0032 << 2) + 0xfd020000)
+ //bit 10 enable auto clock gating for dfi command generation
+ //bit 9 enable auto clock gating for dram cntroller
+ //bit 8 enable auto clock gating for dfi data path.
+ //bit 7. enalbe auto clock gating for write rsp generation.
+ //bit 6. enalbe auto clock gating for read rsp generation.
+ //bit 5. enalbe auto clock gating for ddr0 command filter.
+ //bit 4. enalbe auto clock gating for ddr0 write reorder buffer.
+ //bit 3. enalbe auto clock gating for ddr0 write data buffer.
+ //bit 2. enalbe auto clock gating for ddr0 read reorder buffer.
+ //bit 1. reserved
+ //bit 0. reserved
+#define DMC_CLKG_CTRL3 ((0x0033 << 2) + 0xfd020000)
+ //bit 10 force to disable the clock of dfi command generation
+ //bit 9 force to disable the clock of dram cntroller
+ //bit 8 force to disable the clock of dfi data path.
+ //bit 7. force to disalbe the clock of write rsp generation.
+ //bit 6. force to disalbe the clock of read rsp generation.
+ //bit 5. force to disalbe the clock of command filter.
+ //bit 4. force to disalbe the clock of write reorder buffer.
+ //bit 3. force to disalbe the clock of write data buffer.
+ //bit 2. force to disalbe the clock of read reorder buffer.
+ //bit 1. reserved.
+ //bit 0. reserved.
+#define DMC_CHAN_STS ((0x0036 << 2) + 0xfd020000)
+ //bit 4 always 1
+ //bit 3 ddr0 write data buffer idle. 1 : idle 0: busy.
+ //bit 2 always 1.
+ //bit 1 ddr0 wbuf idle. 1 : idle 0: busy.
+ //bit 0. axi0 channel idle. 1 : idle 0: busy.
+#define DMC_CMD_FILTER_CTRL3 ((0x0042 << 2) + 0xfd020000)
+ //bit 31. force wbuf empty.
+ //bit 30:26 wbuf high level number
+ //bit 25:21 wbuf mid level number
+ //bit 20:16 wbuf low level number
+ //bit 14:10 rbuf high level number
+ //bit 9:5 rbuf middle level number
+ //bit 4:0 rbuf low level number
+#define DMC_CMD_FILTER_CTRL4 ((0x0043 << 2) + 0xfd020000)
+ //bit 29:25. tITW.long
+ //bit 24:20. tITW. short
+ //bit 19:12 tAP auto precharge the bank not used if idle that long time.
+ //bit 11:6 write to read accesses if there write hit request.
+ //bit 5:0 read to write accesses if there write hit request.
+#define DMC_CMD_FILTER_CTRL5 ((0x0044 << 2) + 0xfd020000)
+ //bit 31:24 Once ddr data bus switch to read, the maxmum read command number to give up the bus when there's write request pending for write buffer.
+ //bit 23:16 Once ddr data bus switch to write, the maxmum write command number to give up the bus when there's read request pending too long.
+ //bit 15:8. Once ddr data bus switch to read, the minimum read command number to transfer back to write stage if there's still pending read request.
+ //bit 7:0. Once ddr data bus switch to write, the minimum write command number to transfer back to read stage if there's still pending write request.
+#define DMC_CMD_FILTER_CTRL6 ((0x0045 << 2) + 0xfd020000)
+ //bit 31:24 write urgent 3 request pending hold num.
+ //bit 23:16 write urgent 2 request pending hold num.
+ //bit 15:8. write urgent 1 request pending hold num.
+ //bit 7:0. write urgent 0 request pending hold num.
+#define DMC_CMD_FILTER_CTRL7 ((0x0046 << 2) + 0xfd020000)
+ //bit 15:8 write to read waiting cycles if there write hit request.
+ //bit 7:0 read to write waiting cycles if there write hit request.
+#define DMC_CMD_BUFFER_CTRL ((0x0047 << 2) + 0xfd020000)
+ //bit 31:26 total write buffer number. default 32.
+ //bit 25:20 total read buffer number. default 32.
+ //bit 19:8 reserved.
+ //bit 7:0 aw_pending_inc_num. incease write ugent level 1 when write command waiting to in write buffer that long.
+#define DMC_CMD_BUFFER_CTRL1 ((0x0048 << 2) + 0xfd020000)
+ //bit 29:24 read buffer number in non-urgent request.
+ //bit 23:16 read buffer bank miss watch dog threshold.
+ //bit 15:12 read buffer urgent level 3 counter inc weight.
+ //bit 11:8 read buffer urgent level 2 counter inc weight.
+ //bit 7:4 read buffer urgent level 1 counter inc weight.
+ //bit 3:0 read buffer urgent level 0 counter inc weight.
+#define DMC_AXI0_CHAN_CTRL ((0x0080 << 2) + 0xfd020000)
+ //bit 31 AXI interface request enable.
+ //bit 19 AXI interface auto clock gating enable. 1: enable; 0 disable.
+ //bit 18 AXI interface clock disable. 1 : disable clock. 0 enable clock.
+ //bit 17 AXI interface dmc clock domain soft reset. 0 : reset. 1 : normal working mode.
+ //bit 16 AXI interface s0 clock domain soft reset. 0 : reset. 1 : normal working mode.
+ //bit 15:12 ugt3 QOS level.
+ //bit 11:8 ugt2 QOS level.
+ //bit 7:4 ugt1 QOS level.
+ //bit 3:0 not used.
+#define DMC_AXI0_HOLD_CTRL ((0x0081 << 2) + 0xfd020000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI5_HOLD_CTRL ((0x0095 << 2) + 0xfd020000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+//`endif
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh
+//
+//`ifdef DMC_SIU_REG_DEFINE
+//`else
+//`define DMC_SIU_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd020400
+// -----------------------------------------------
+//`define DMC_DRAM_REG_BASE 32'hfd020400
+//in A1 project, don't support hardware controlled frequency change.
+#define DMC_DRAM_TMRD ((0x0000 << 2) + 0xfd020400)
+ //bit 3:0. tMRD.
+#define DMC_DRAM_TRFC ((0x0001 << 2) + 0xfd020400)
+ //bit 9:0 tRFC
+#define DMC_DRAM_TRP ((0x0002 << 2) + 0xfd020400)
+ //bit 21:16. tRP for precharge all banks.
+ //bit 5:0. tRP for precharge one bank.
+#define DMC_DRAM_TRTW ((0x0003 << 2) + 0xfd020400)
+ //bit 5:0 tRTW
+#define DMC_DRAM_TCL ((0x0004 << 2) + 0xfd020400)
+ //bit 5:0 tCL/tRL. read latency.
+#define DMC_DRAM_TCWL ((0x0005 << 2) + 0xfd020400)
+ //bit 5:0. CWL: write latency.
+#define DMC_DRAM_TRAS ((0x0006 << 2) + 0xfd020400)
+ //bit 7:0. tRAS. minimum active to precharge time for same bank.
+#define DMC_DRAM_TRC ((0x0007 << 2) + 0xfd020400)
+ //bit 7:0. tRC. minimum active to active time for same bank.
+#define DMC_DRAM_TRCD ((0x0008 << 2) + 0xfd020400)
+ //bit 7:0 tRCD active to read/write timing for same bank.
+#define DMC_DRAM_TRRD ((0x0009 << 2) + 0xfd020400)
+ //bit 21:16. tRRD_l active bank A to active B in same band group for DDR4.
+ //bit 5:0. tRRD/tRRD_s active bank A to active bank b time.
+ //tRRD_s: active bank A to active bank b in different bank grousp for DDR4.
+#define DMC_DRAM_TFAW ((0x000a << 2) + 0xfd020400)
+ //bit 8:0 tFAW. four active command windows
+#define DMC_DRAM_TRTP ((0x000b << 2) + 0xfd020400)
+ //bit 5:0 tRTP.
+#define DMC_DRAM_TWR ((0x000c << 2) + 0xfd020400)
+ //bit 5:0 tWR.
+#define DMC_DRAM_TWTR ((0x000d << 2) + 0xfd020400)
+ //bit 5:0 tWTR.
+#define DMC_DRAM_TCCD ((0x000e << 2) + 0xfd020400)
+ //bit 19:16. tCCD/tCCD_l.
+ //bit 3:0 tCCD/tCCD_s read to read command time or write to write command time.
+#define DMC_DRAM_TEXSR ((0x000f << 2) + 0xfd020400)
+ //bit 9:0. tEXSR. EXIT SELF-REFRESH to read/write command.
+#define DMC_DRAM_TXS ((0x0010 << 2) + 0xfd020400)
+ //bit 9:0 tXS. EXIT SELF_REFRESH to other command time
+#define DMC_DRAM_TXP ((0x0011 << 2) + 0xfd020400)
+ //bit 3:0. tXP. EXIT power down to other command time
+#define DMC_DRAM_TXPDLL ((0x0012 << 2) + 0xfd020400)
+ //bit 9:0. tXPDLL, EXIT power down to read/write command time(need to relock PLL).
+#define DMC_DRAM_TZQCS ((0x0013 << 2) + 0xfd020400)
+ //bit 11:0. ZQCS command to other command time.
+#define DMC_DRAM_TCKSRE ((0x0014 << 2) + 0xfd020400)
+ //bit 4:0. enter self refresh to disable clock time.
+#define DMC_DRAM_TCKSRX ((0x0015 << 2) + 0xfd020400)
+ //bit 4:0. enable clock to exit self refresh time.
+#define DMC_DRAM_TCKE ((0x0016 << 2) + 0xfd020400)
+ //bit 4:0. CKE high or low minimum time.
+#define DMC_DRAM_TMOD ((0x0017 << 2) + 0xfd020400)
+ //bit 4:0 tMOD. MRR/MRW to other command time.
+#define DMC_DRAM_TDQS ((0x0018 << 2) + 0xfd020400)
+ //bit 3:0 tDQS. the delay to access different rank.
+#define DMC_DRAM_TRSTL ((0x0019 << 2) + 0xfd020400)
+ //not used.
+#define DMC_DRAM_TZQLAT ((0x001a << 2) + 0xfd020400)
+ //bit 5:0 ZQ LATCH command to other comand timing in LPDDR4 mode.
+#define DMC_DRAM_TMRR ((0x001b << 2) + 0xfd020400)
+ //bit 7:0 tMRR not used in DMC. not support MR READ.
+#define DMC_DRAM_TCKESR ((0x001c << 2) + 0xfd020400)
+ //bit 9:0 tCKESR. CKE low minimum pulse in self refresh mode.
+#define DMC_DRAM_TDPD ((0x001d << 2) + 0xfd020400)
+ //not support.
+#define DMC_DRAM_DFITCTRLDELAY ((0x001e << 2) + 0xfd020400)
+ //bit 3:0. DFI_t_ctrldealy
+#define DMC_DRAM_DFITPHYWRDATA ((0x001f << 2) + 0xfd020400)
+ //bit 5:0. dfi_t_phy_wrdata.
+#define DMC_DRAM_DFITPHYWRLAT ((0x0020 << 2) + 0xfd020400)
+ //bit 5:0. dfi_t_phy_wrlat. in DDR3/4/LPDDR3 mode: WL -5. in LPDDR4 mode: WL -5 + 2.
+#define DMC_DRAM_DFITRDDATAEN ((0x0021 << 2) + 0xfd020400)
+ //bit 5:0. dfi_t_rddata_en. in DDR3/4/LPDDR3 mode: RL -5. in LPDDR4 mode : RL -5 + 1.
+#define DMC_DRAM_DFITPHYRDLAT ((0x0022 << 2) + 0xfd020400)
+ //bit 5:0. dfi_t_rdlat.
+#define DMC_DRAM_DFITCTRLUPDMIN ((0x0023 << 2) + 0xfd020400)
+ //bit 7:0. CTRLUPD_MIN minimux clock cycle to maintain CTRLUPD_REQ.
+#define DMC_DRAM_DFITCTRLUPDMAX ((0x0024 << 2) + 0xfd020400)
+ //bit 7:0 CTRLUPD_MAX. maxmum clock cycle to maintain CTRLUPD_REQ if no CTRLUPD_ACK response.
+#define DMC_DRAM_DFITMSTRRESP ((0x0025 << 2) + 0xfd020400)
+ //not used.
+#define DMC_DRAM_DFITREFMSKI ((0x0026 << 2) + 0xfd020400)
+ //not used.
+#define DMC_DRAM_DFITCTRLUPDI ((0x0027 << 2) + 0xfd020400)
+ //not used.
+#define DMC_DRAM_DFITDRAMCLK ((0x0028 << 2) + 0xfd020400)
+//bit 17 dram clk1 enable.
+//bit 16 dram clk0 enable.
+//bit 15:8 DRAM CLK disable waiting time
+//bit 7:0 DRAM CLK enable enable timer
+#define DMC_DRAM_DFITLPRESP ((0x002a << 2) + 0xfd020400)
+ //bit 3:0. dfi_lp_ctrl_req response time. after dfi_lp_ctrl_req asserted, and after response time if there's still no dfi_lp_ack respone, then drop the dfi_lp_ctrl_req.
+#define DMC_DRAM_DFITPHYMSTR ((0x002b << 2) + 0xfd020400)
+ //bit 15 1: enable DFIPHYMASTER INTERFACE 0 disable DFIPHYMSTR en response.
+ // always 0 we would use DFI_RETRAIN function for PHY retrain required from LPDDR4.
+#define DMC_DRAM_TCKECK ((0x002c << 2) + 0xfd020400)
+ //bit 4:0. tCKECK from CKE low to assert dfi_dram_clk_disable time. this time + dfi_t_ctrl_delay
+#define DMC_DRAM_TREFI ((0x002d << 2) + 0xfd020400)
+ //write this register will update the auto refresh related register to the auto refresh control logic.
+ //bit 31:24: tZQCI dmc send zqci period. unit is how much auto refresh period.
+ //bit 23:16 pvti dmc send dfi_ctrlupd_req period. unit is one auto refresh period.
+ //bit 15:8. tREFI.dmc send auto refresh command period. unit is 100ns.
+ //bit 7:0. t100ns period. unit is dmc clock cycles
+#define DMC_DRAM_TSR ((0x002e << 2) + 0xfd020400)
+ //bit 5:0 tSR. self resfresh enter to exit time.
+#define DMC_DRAM_TCCDMW ((0x002f << 2) + 0xfd020400)
+ //bit 5:0. 4*tCCD in LPDDR4 mask write.
+#define DMC_DRAM_TESCKE ((0x0030 << 2) + 0xfd020400)
+ //bit 5:0 tESCKE. enter self refresh to power time for LPDDR4.
+#define DMC_DRAM_TREFI_DDR3 ((0x0031 << 2) + 0xfd020400)
+ //7:0. 8*DDR3 SDRAM tREFI time . the unit is t100ns. use this to check in 8*tREFI time, the DMC should sent more than 16 auto REFRESH command.
+#define DMC_DRAM_TZQCAL ((0x0032 << 2) + 0xfd020400)
+ //7:0. ZQCAL for LPDDR4.
+#define DMC_DRAM_T10US ((0x0033 << 2) + 0xfd020400)
+ //10us clock cycle number used for LP2 mode.
+#define DMC_DRAM_TMRRI ((0x0034 << 2) + 0xfd020400)
+//bit 7:0 tMRRI for MRR
+#define DMC_DRAM_DFITPHYUPDTYPE0 ((0x0080 << 2) + 0xfd020400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 0.
+#define DMC_DRAM_DFITPHYUPDTYPE1 ((0x0081 << 2) + 0xfd020400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 1.
+#define DMC_DRAM_DFITPHYUPDTYPE2 ((0x0082 << 2) + 0xfd020400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 2.
+#define DMC_DRAM_DFITPHYUPDTYPE3 ((0x0083 << 2) + 0xfd020400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 3.
+#define DMC_DRAM_DFIODTCFG ((0x0084 << 2) + 0xfd020400)
+ //bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity.
+ //bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1.
+ //bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0.
+ //bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1.
+ //bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0.
+ //bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity.
+ //bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0.
+ //bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1.
+ //bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0.
+ //bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1.
+#define DMC_DRAM_DFIODTCFG1 ((0x0085 << 2) + 0xfd020400)
+ //bit 27:24 ODT length for BL8 read transfer.
+ //bit 19:16. ODT length for BL8 write transfer.
+ //bit 12:8. ODT latency for reads. suppose to be 0.
+ //bit 4:0. ODT latency for writes. suppose to be 0.
+#define DMC_DRAM_MCFG ((0x0086 << 2) + 0xfd020400)
+ //bit 14. 1: cke init low. 0 : cke init high.
+ //bit 13 1: dbi write enable only for LPDDR4.
+ //bit 12. 1: dbi read inversion. 0: dbi read high inversion.
+ //bit 11. 1: dbi read enable. 0: dbi not enabled.
+ //bit 10 1: enable staggered chip select for 2 ranks DRAM.
+ //bit 9 1: enable send auto refresh command to DDR SDRAM when PCTL is in CFG/STOP state.
+ //bit 8 send auto refr cmd before enter register triggered self refresh
+ //bit 7 send auto refr cmd after exit regsiter triggered self refresh mode.
+ //bit 6 disable dram clock after enter register triggered self refresh.
+ //bit 5 send DFI_LP_REQ to PHY after enter register triggered elf refresh mode.
+ //bit 4 send DRAM to power down mode after enter self refresh. ONLY for LPDDR4.
+ //bit 3 send DFI_CTRLUPD_REQ after exit register triggered self refresh.
+ //bit 2 send ZQCS command after exit register triggered self refresh.
+ //bit 1 enable PHY triggered DFI_PHYUPD_REQ.
+ //bit 0 2T mode. always 1 in DDR3/4 mode.
+#define DMC_DRAM_DFI_CTRL ((0x0089 << 2) + 0xfd020400)
+ //bit 31 siu_dfi_lat err generation enable. 1: if dfi read latency violation, generate data error. 0 : disable.
+ //bit 30:0. not used.
+#define DMC_DRAM_DFIINITCFG ((0x008a << 2) + 0xfd020400)
+ //bit 31. dfi_init_complete status. read only.
+ //bit 15:14. Frequency set 1 dfi_freq_ratio value. Not used in A1
+ //bit 12:8 Frequency set 1 dfi_freq value. Not used in A1
+ //bit 7:6 Frequency set 0 dfi_freq_ratio value.
+ //bit 5:1 Frequency set 0 dfi_freq value.
+ //bit 0. dfi_init_start value can be use manually config dfi_init_start signal.
+#define DMC_DRAM_ZQ_CTRL ((0x008b << 2) + 0xfd020400)
+ // only bit 0 can be enable in A1.
+ //bit 2 send ZQCS command to RANK0 then send comand to RANK1.
+ //bit 1. send ZQCS command to both RANK0 and RANK1 together.
+ //bit 0. send ZQCS command to only rank0.
+#define DMC_DRAM_APD_CTRL ((0x008c << 2) + 0xfd020400)
+ //bit 19:16 DFI_LP_WAKEUP value in APD DFI_LP_REQ mode
+ //bit 12 1: exit power down slow mode(waiting PLL LOCK). 0 : fast mode.
+ //bit 11 enable DFI_LP_REQ when enter Auto power down mode.
+ //bit 10 disable DFI_clk_disable when enter auto power down mode.
+ //bit 9:0 0 disable auto power down mode.
+ //non zero value to enable auto power down when DMC is in idle state for this number of clock cycles.
+#define DMC_DRAM_ASR_CTRL ((0x008d << 2) + 0xfd020400)
+ //bit [25] LP2 mode PHYCLK enable. 1 : keep PHY clock enable after enter LP2 mode. 0 : shutdown PHY clock after enter LP2 mode.
+ //bit [24] LP2 mode SRX waiting enable. if Self refresh too long, waiting 10us for the PHY stable before DDR SDRAM exit from self refresh state.
+ //bit [23:20] DFI_LP_WAKEUP value in self refresh DFI_LP_REQ mode.
+ //bit 17 : send REFRESH command after exit from auto self refersh mode(ASR).
+ //bit 16 : send REFERSH command before enter to Auto self refresh mode(ASR).
+ //bit 15 : send ZQCS command after exit from Auto self refresh mode(ASR).
+ //bit 14 : send dfi_ctrl_upd after exit from ASR mode
+ //bit 13 : send power down command when enter ASR mode. //for LPDDR4 only.
+ //bit 12 : set the PHY enter LP2 mode after enter ASR mode.
+ //bit 11 : send DFI_LP_REQ after enter ASR mode.
+ //bit 10 : set DFI_CLK_DISABLE after enter ASR mode.
+ //bit 9:0. 0 disable auto ASR mode.
+ // Non-zero valule enable ASR mode. when DMC is in idle state for this number of clock cycles, the DMC will enter ASR mode.
+#define DMC_DRAM_PHYMSTR_CTRL ((0x0090 << 2) + 0xfd020400)
+ //not used in A1. should be all 0.
+#define DMC_DRAM_DFIODTRANKMAP ((0x0091 << 2) + 0xfd020400)
+ //not used in A1.
+#define DMC_DRAM_REFR_CTRL ((0x0092 << 2) + 0xfd020400)
+ //bit 17:8 auto refresh request pending cnt if there's page hit request.
+ //bit 6 Disabled auto refresh command if over 16 auto refresh command sent in 2 TREFI_DDR3 period
+ //bit 5 enable dmc send ZQCS command .
+ //bit 4. enable dmc send DFI_CTRUPD_REQ.
+ //bit 3:1. how many refresh command send for one period. = this number + 1
+ //bit 0. enable dmc send auto refresh command.
+#define DMC_DRAM_FREQ_CTRL ((0x0093 << 2) + 0xfd020400)
+//bit 31 . wiret 1 to change freqency read 0: finished.
+//bit 30:9. not used.
+//bit 9. 1 : FREQ MRW done. let FREQ change machine continue.
+//bit 8 FREQ WAIT. 1 when freq change finishes, state machine stop at self refresh state in case there's something need to handle.
+ // 0 after freq change finishes the state machine go back to access state.
+//bit 7 when change PLL setting, disable dmc clock
+//bit 6 when change PLL setting, disable PHY DfiClk and DfiCtlClk.
+//bit 5 check vpu_sleep_en ==1 when do FREQ change. if vpu_sleep_en == 0, just wait.
+//bit 4 nxt frequency selection. 1 = freq1. 0 = freq0.
+//bit 3:1. not used.
+//bit 0. current frequency selection.
+#define DMC_DRAM_SCFG ((0x0094 << 2) + 0xfd020400)
+ // bit 2:0 only one bit can be high at same time.
+ // bit 2 1 : to ask PCTL enter ACCESS STATE. 0 : deassert the request.
+ // bit 1 1 : to ask PCTL enter SELF REFRESH STATE. 0 : deassert the request.
+ // bit 0 1 : to ask PCTL enter STOP/CONFIG STATE . 0 : deassert the request.
+#define DMC_DRAM_STAT ((0x0095 << 2) + 0xfd020400)
+ //bit 31 rd latency error. 1: means after dfiphytrdlat cycles, the read data still not back.
+ //bit 28:24 dram_sr_state
+ //bit 23:20 stop_st
+ //bit 19:15 sleep_st
+ //bit 14:12 ACCESS STATUS 0 : ACCESS is in normal working mode.
+ //1 : ACCESS sending precharege command.
+ //2 : ACCESS sending AUTO REFESH command.
+ //3 : ACCESS sending DIF_CTRLUPD_REQ command.
+ //4 : ACCESS sending ZQCS command to DDR DRAM(ZQCAL for LPDDR4).
+ //5 : ACCESS sending ZQLATCH command to LPDDR4 only.
+ //bit 11:8 APD STATUS: 0 : APD_IDLE
+ //1 : APD sending PRECHARGE command
+ //2 : APD sending CKE low command
+ //3 : APD sending DISABLE DRAM CLOCK command
+ //4 : APD sending DFI_LP_CTRL_REQ
+ //5 : APD in Auto Power down mode.
+ //6 : APD deassert DFI_LP_CTRL_REQ
+ //7 : APD sending enable DRAM CLOCK command
+ //8 : APD sending out CKE high command.
+ //bit 7:4: DRAM_STATUS: 0 : DRAM IDLE
+ //1 : DRAM_STOP/DRAM_CFG
+ //2 : DRAM_ACCESS
+ //3 : DRAM_SLEEP
+ //4 : DRAM APD(AUTO POWER DOWN).
+ //5 : IDLE -> STOP/CONFIG
+ //6 : STOP -> SLEEP
+ //7 : STOP -> ACCESS
+ //8 : ACCESS -> SLEEP.
+ //9 : ACCESS -> STOP
+ //A : ACCESS -> APD
+ //B : SLEEP -> STOP
+ //C : SLEEP -> ACCESS
+ //D : APD -> ACCESS
+ //bit 3 reserved.
+ //bit 2 1 : DRAM enter normal working state.
+ //bit 1 1 : DRAM enter sleep state. self refresh state.
+ //bit 0 1 : dram enter cfg state.
+#define DMC_DRAM_STAT1 ((0x0096 << 2) + 0xfd020400)
+ //bit 11:8 freq_st.
+ //bit 7:5 train_st
+ //bit 4:0 dram_phy_st
+#define DMC_PHY_RETRAINING_CTRL ((0x0097 << 2) + 0xfd020400)
+ // A1 not support LPDDR4 so this register is not used in A1.
+ //bit 31 : phy_retraining enable.
+ //bit 30 : check vpu sleep_en.
+ //bit 25:24 : retraining dfi_freq[4:3], the [2:0] bit still use the dfi_freq bits to keep the frequency.
+ //bit 23:0: retraining period unit : 100ns.
+#define DMC_DFI_ERR_STAT ((0x0098 << 2) + 0xfd020400)
+ //LPDDR4 PHY DFI error infomation.
+ //bit 31:20. not used.
+ //bit 9. ddr0_dfi_error
+ //bit 8:5 ddr0_dfi_error_info.
+ //bit 4. ddr1_dfi_error.
+ //bit 3:0. ddr1_dfi_error_info.
+#define DMC_LP2_TIMER ((0x009a << 2) + 0xfd020400)
+//bit 15:0. timer setting to measure how long the chip is entered LP2 mode.
+//this timer is 40bits counter with DMC PCLK.
+//we use the high 16bits to compare this register. if the counter is large than this number, that means the PHY need addition 10us after wakeup the PHY and before exit self_refresh mode.
+#define DMC_DRAM_DFI_SWAP_0 ((0x00a0 << 2) + 0xfd020400)
+ //bit 5:0. dfi_act_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_1 ((0x00a1 << 2) + 0xfd020400)
+ //bit 5:0. dfi_ras_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_2 ((0x00a2 << 2) + 0xfd020400)
+ //bit 5:0. dfi_cas_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_3 ((0x00a3 << 2) + 0xfd020400)
+ //bit 5:0. dfi_we_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_4 ((0x00a4 << 2) + 0xfd020400)
+ //bit 5:0. dfi_bg0 function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_5 ((0x00a5 << 2) + 0xfd020400)
+ //bit 5:0. dfi_bg[1] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_6 ((0x00a6 << 2) + 0xfd020400)
+ //bit 5:0. dfi_ba[0] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_7 ((0x00a7 << 2) + 0xfd020400)
+ //bit 5:0. dfi_ba[1] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_8 ((0x00a8 << 2) + 0xfd020400)
+ //bit 5:0. dfi_ba[2] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_9 ((0x00a9 << 2) + 0xfd020400)
+ //bit 5:0. dfi_a[0] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_10 ((0x00aa << 2) + 0xfd020400)
+ //bit 5:0. dfi_a[1] function select
+#define DMC_DRAM_DFI_SWAP_11 ((0x00ab << 2) + 0xfd020400)
+ //bit 5:0. dfi_a[2] function select
+#define DMC_DRAM_DFI_SWAP_12 ((0x00ac << 2) + 0xfd020400)
+ //bit 5:0. dfi_a[3] function select
+#define DMC_DRAM_DFI_SWAP_13 ((0x00ad << 2) + 0xfd020400)
+ //bit 5:0. dfi_a[4] function select
+#define DMC_DRAM_DFI_SWAP_14 ((0x00ae << 2) + 0xfd020400)
+ //bit 5:0. dfi_a[5] function select
+#define DMC_DRAM_DFI_SWAP_15 ((0x00af << 2) + 0xfd020400)
+ //bit 5:0. dfi_a[6] function select
+#define DMC_DRAM_DFI_SWAP_16 ((0x00b0 << 2) + 0xfd020400)
+ //bit 5:0. dfi_a[7] function select
+#define DMC_DRAM_DFI_SWAP_17 ((0x00b1 << 2) + 0xfd020400)
+ //bit 5:0. dfi_a[8] function select
+#define DMC_DRAM_DFI_SWAP_18 ((0x00b2 << 2) + 0xfd020400)
+ //bit 5:0. dfi_a[9] function select
+#define DMC_DRAM_DFI_SWAP_19 ((0x00b3 << 2) + 0xfd020400)
+ //bit 5:0. dfi_a[10] function select
+#define DMC_DRAM_DFI_SWAP_20 ((0x00b4 << 2) + 0xfd020400)
+ //bit 5:0. dfi_a[11] function select
+#define DMC_DRAM_DFI_SWAP_21 ((0x00b5 << 2) + 0xfd020400)
+ //bit 5:0. dfi_a[12] function select
+#define DMC_DRAM_DFI_SWAP_22 ((0x00b6 << 2) + 0xfd020400)
+ //bit 5:0. dfi_a[13] function select
+#define DMC_DRAM_DFI_SWAP_23 ((0x00b7 << 2) + 0xfd020400)
+ //bit 5:0. dfi_a[14] function select
+#define DMC_DRAM_DFI_SWAP_24 ((0x00b8 << 2) + 0xfd020400)
+ //bit 5:0. dfi_a[15] function select
+#define DMC_DRAM_DFI_SWAP_25 ((0x00b9 << 2) + 0xfd020400)
+ //bit 5:0. dfi_a[16] function select
+#define DMC_DRAM_DFI_SWAP_26 ((0x00bb << 2) + 0xfd020400)
+ //bit 5:0. dfi_a[17] function select
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh
+//
+//`ifdef DMC_STICKY_REG_DEFINE
+//`else
+//`define DMC_STICKY_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd020800
+// -----------------------------------------------
+//`define DMC_STICKY_REG_BASE 32'hfd020800
+//those register is for software save some tempary value. and because it's in RAM. it won't lose if DMC get reseted.
+#define DMC_STICKY_0 ((0x0000 << 2) + 0xfd020800)
+#define DMC_STICKY_1 ((0x0001 << 2) + 0xfd020800)
+#define DMC_STICKY_2 ((0x0002 << 2) + 0xfd020800)
+#define DMC_STICKY_3 ((0x0003 << 2) + 0xfd020800)
+#define DMC_STICKY_4 ((0x0004 << 2) + 0xfd020800)
+#define DMC_STICKY_5 ((0x0005 << 2) + 0xfd020800)
+#define DMC_STICKY_6 ((0x0006 << 2) + 0xfd020800)
+#define DMC_STICKY_7 ((0x0007 << 2) + 0xfd020800)
+#define DMC_STICKY_8 ((0x0008 << 2) + 0xfd020800)
+#define DMC_STICKY_9 ((0x0009 << 2) + 0xfd020800)
+#define DMC_STICKY_10 ((0x000a << 2) + 0xfd020800)
+#define DMC_STICKY_11 ((0x000b << 2) + 0xfd020800)
+#define DMC_STICKY_12 ((0x000c << 2) + 0xfd020800)
+#define DMC_STICKY_13 ((0x000d << 2) + 0xfd020800)
+#define DMC_STICKY_14 ((0x000e << 2) + 0xfd020800)
+#define DMC_STICKY_15 ((0x000f << 2) + 0xfd020800)
+#define DMC_STICKY_16 ((0x0010 << 2) + 0xfd020800)
+#define DMC_STICKY_17 ((0x0011 << 2) + 0xfd020800)
+#define DMC_STICKY_18 ((0x0012 << 2) + 0xfd020800)
+#define DMC_STICKY_19 ((0x0013 << 2) + 0xfd020800)
+#define DMC_STICKY_20 ((0x0014 << 2) + 0xfd020800)
+#define DMC_STICKY_21 ((0x0015 << 2) + 0xfd020800)
+#define DMC_STICKY_22 ((0x0016 << 2) + 0xfd020800)
+#define DMC_STICKY_23 ((0x0017 << 2) + 0xfd020800)
+#define DMC_STICKY_24 ((0x0018 << 2) + 0xfd020800)
+#define DMC_STICKY_25 ((0x0019 << 2) + 0xfd020800)
+#define DMC_STICKY_26 ((0x001a << 2) + 0xfd020800)
+#define DMC_STICKY_27 ((0x001b << 2) + 0xfd020800)
+#define DMC_STICKY_28 ((0x001c << 2) + 0xfd020800)
+#define DMC_STICKY_29 ((0x001d << 2) + 0xfd020800)
+#define DMC_STICKY_30 ((0x001e << 2) + 0xfd020800)
+#define DMC_STICKY_31 ((0x001f << 2) + 0xfd020800)
+#define DMC_STICKY_32 ((0x0020 << 2) + 0xfd020800)
+#define DMC_STICKY_33 ((0x0021 << 2) + 0xfd020800)
+#define DMC_STICKY_34 ((0x0022 << 2) + 0xfd020800)
+#define DMC_STICKY_35 ((0x0023 << 2) + 0xfd020800)
+#define DMC_STICKY_36 ((0x0024 << 2) + 0xfd020800)
+#define DMC_STICKY_37 ((0x0025 << 2) + 0xfd020800)
+#define DMC_STICKY_38 ((0x0026 << 2) + 0xfd020800)
+#define DMC_STICKY_39 ((0x0027 << 2) + 0xfd020800)
+#define DMC_STICKY_40 ((0x0028 << 2) + 0xfd020800)
+#define DMC_STICKY_41 ((0x0029 << 2) + 0xfd020800)
+#define DMC_STICKY_42 ((0x002a << 2) + 0xfd020800)
+#define DMC_STICKY_43 ((0x002b << 2) + 0xfd020800)
+#define DMC_STICKY_44 ((0x002c << 2) + 0xfd020800)
+#define DMC_STICKY_45 ((0x002d << 2) + 0xfd020800)
+#define DMC_STICKY_46 ((0x002e << 2) + 0xfd020800)
+#define DMC_STICKY_47 ((0x002f << 2) + 0xfd020800)
+#define DMC_STICKY_48 ((0x0030 << 2) + 0xfd020800)
+#define DMC_STICKY_49 ((0x0031 << 2) + 0xfd020800)
+#define DMC_STICKY_50 ((0x0032 << 2) + 0xfd020800)
+#define DMC_STICKY_51 ((0x0033 << 2) + 0xfd020800)
+#define DMC_STICKY_52 ((0x0034 << 2) + 0xfd020800)
+#define DMC_STICKY_53 ((0x0035 << 2) + 0xfd020800)
+#define DMC_STICKY_54 ((0x0036 << 2) + 0xfd020800)
+#define DMC_STICKY_55 ((0x0037 << 2) + 0xfd020800)
+#define DMC_STICKY_56 ((0x0038 << 2) + 0xfd020800)
+#define DMC_STICKY_57 ((0x0039 << 2) + 0xfd020800)
+#define DMC_STICKY_58 ((0x003a << 2) + 0xfd020800)
+#define DMC_STICKY_59 ((0x003b << 2) + 0xfd020800)
+#define DMC_STICKY_60 ((0x003c << 2) + 0xfd020800)
+#define DMC_STICKY_61 ((0x003d << 2) + 0xfd020800)
+#define DMC_STICKY_62 ((0x003e << 2) + 0xfd020800)
+#define DMC_STICKY_63 ((0x003f << 2) + 0xfd020800)
+//`endif
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh
+//
+//========================================================================
+// APB0_RESET_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000000
+// -----------------------------------------------
+#define RESETCTRL_RESET0 ((0x0000 << 2) + 0xfe000000)
+#define RESETCTRL_RESET1 ((0x0001 << 2) + 0xfe000000)
+#define RESETCTRL_RESET2 ((0x0002 << 2) + 0xfe000000)
+#define RESETCTRL_RESET0_LEVEL ((0x0010 << 2) + 0xfe000000)
+#define RESETCTRL_RESET1_LEVEL ((0x0011 << 2) + 0xfe000000)
+#define RESETCTRL_RESET2_LEVEL ((0x0012 << 2) + 0xfe000000)
+#define RESETCTRL_RESET0_MASK ((0x0020 << 2) + 0xfe000000)
+#define RESETCTRL_RESET1_MASK ((0x0021 << 2) + 0xfe000000)
+#define RESETCTRL_RESET2_MASK ((0x0022 << 2) + 0xfe000000)
+#define RESETCTRL_RESET_HOLD_CYC ((0x0030 << 2) + 0xfe000000)
+#define RESETCTRL_WATCHDOG_CTRL0 ((0x0040 << 2) + 0xfe000000)
+#define RESETCTRL_WATCHDOG_CTRL1 ((0x0041 << 2) + 0xfe000000)
+#define RESETCTRL_WATCHDOG_CNT ((0x0042 << 2) + 0xfe000000)
+#define RESETCTRL_WATCHDOG_CLR ((0x0043 << 2) + 0xfe000000)
+#define RESETCTRL_SEC_RESET0 ((0x0050 << 2) + 0xfe000000)
+#define RESETCTRL_SEC_RESET0_LEVEL ((0x0051 << 2) + 0xfe000000)
+#define RESETCTRL_SEC_RESET0_MASK ((0x0052 << 2) + 0xfe000000)
+//========================================================================
+// APB0_PAD_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000400
+// -----------------------------------------------
+#define PADCTRL_PIN_MUX_REG0 ((0x0000 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG1 ((0x0001 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG3 ((0x0003 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG4 ((0x0004 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG5 ((0x0005 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG6 ((0x0006 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG7 ((0x0007 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG8 ((0x0008 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG9 ((0x0009 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REGA ((0x000a << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REGB ((0x000b << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REGC ((0x000c << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REGD ((0x000d << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REGE ((0x000e << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REGF ((0x000f << 2) + 0xfe000400)
+#define PADCTRL_GPIO_IRQ_CTRL0 ((0x0010 << 2) + 0xfe000400)
+#define PADCTRL_GPIO_IRQ_CTRL1 ((0x0011 << 2) + 0xfe000400)
+#define PADCTRL_GPIO_IRQ_CTRL2 ((0x0012 << 2) + 0xfe000400)
+#define PADCTRL_GPIO_IRQ_CTRL3 ((0x0013 << 2) + 0xfe000400)
+#define PADCTRL_GPIO_IRQ_CTRL4 ((0x0014 << 2) + 0xfe000400)
+#define PADCTRL_WORLDSYNC_CTRL0 ((0x0018 << 2) + 0xfe000400)
+#define PADCTRL_GPIO_MSR_CTRL0 ((0x0019 << 2) + 0xfe000400)
+#define PADCTRL_GPIOP_I ((0x0020 << 2) + 0xfe000400)
+#define PADCTRL_GPIOP_O ((0x0021 << 2) + 0xfe000400)
+#define PADCTRL_GPIOP_OEN ((0x0022 << 2) + 0xfe000400)
+#define PADCTRL_GPIOP_PULL_EN ((0x0023 << 2) + 0xfe000400)
+#define PADCTRL_GPIOP_PULL_UP ((0x0024 << 2) + 0xfe000400)
+#define PADCTRL_GPIOP_DS ((0x0025 << 2) + 0xfe000400)
+#define PADCTRL_GPIOB_I ((0x0030 << 2) + 0xfe000400)
+#define PADCTRL_GPIOB_O ((0x0031 << 2) + 0xfe000400)
+#define PADCTRL_GPIOB_OEN ((0x0032 << 2) + 0xfe000400)
+#define PADCTRL_GPIOB_PULL_EN ((0x0033 << 2) + 0xfe000400)
+#define PADCTRL_GPIOB_PULL_UP ((0x0034 << 2) + 0xfe000400)
+#define PADCTRL_GPIOB_DS ((0x0035 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_I ((0x0040 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_O ((0x0041 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_OEN ((0x0042 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_PULL_EN ((0x0043 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_PULL_UP ((0x0044 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_DS ((0x0045 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_DS_EXT ((0x0046 << 2) + 0xfe000400)
+#define PADCTRL_GPIOF_I ((0x0050 << 2) + 0xfe000400)
+#define PADCTRL_GPIOF_O ((0x0051 << 2) + 0xfe000400)
+#define PADCTRL_GPIOF_OEN ((0x0052 << 2) + 0xfe000400)
+#define PADCTRL_GPIOF_PULL_EN ((0x0053 << 2) + 0xfe000400)
+#define PADCTRL_GPIOF_PULL_UP ((0x0054 << 2) + 0xfe000400)
+#define PADCTRL_GPIOF_DS ((0x0055 << 2) + 0xfe000400)
+#define PADCTRL_GPIOA_I ((0x0060 << 2) + 0xfe000400)
+#define PADCTRL_GPIOA_O ((0x0061 << 2) + 0xfe000400)
+#define PADCTRL_GPIOA_OEN ((0x0062 << 2) + 0xfe000400)
+#define PADCTRL_GPIOA_PULL_EN ((0x0063 << 2) + 0xfe000400)
+#define PADCTRL_GPIOA_PULL_UP ((0x0064 << 2) + 0xfe000400)
+#define PADCTRL_GPIOA_DS ((0x0065 << 2) + 0xfe000400)
+#define PADCTRL_TESTN_I ((0x0070 << 2) + 0xfe000400)
+#define PADCTRL_TESTN_O ((0x0071 << 2) + 0xfe000400)
+#define PADCTRL_TESTN_OEN ((0x0072 << 2) + 0xfe000400)
+#define PADCTRL_TESTN_PULL_EN ((0x0073 << 2) + 0xfe000400)
+#define PADCTRL_TESTN_PULL_UP ((0x0074 << 2) + 0xfe000400)
+#define PADCTRL_TESTN_DS ((0x0075 << 2) + 0xfe000400)
+#define PADCTRL_MUTE_CTRL ((0x0080 << 2) + 0xfe000400)
+//========================================================================
+// APB0_CLK_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000800
+// -----------------------------------------------
+#define CLKTREE_SYS_OSCIN_CTRL ((0x0000 << 2) + 0xfe000800)
+#define CLKTREE_RTC_BY_OSCIN_CTRL0 ((0x0001 << 2) + 0xfe000800)
+#define CLKTREE_RTC_BY_OSCIN_CTRL1 ((0x0002 << 2) + 0xfe000800)
+#define CLKTREE_RTC_CTRL ((0x0003 << 2) + 0xfe000800)
+#define CLKTREE_SYS_CLK_CTRL0 ((0x0004 << 2) + 0xfe000800)
+#define CLKTREE_AXI_CLK_CTRL0 ((0x0005 << 2) + 0xfe000800)
+#define CLKTREE_SYS_CLK_EN0 ((0x0007 << 2) + 0xfe000800)
+#define CLKTREE_SYS_CLK_EN1 ((0x0008 << 2) + 0xfe000800)
+#define CLKTREE_AXI_CLK_EN ((0x0009 << 2) + 0xfe000800)
+#define CLKTREE_DSPA_CLK_EN ((0x000a << 2) + 0xfe000800)
+#define CLKTREE_DSPB_CLK_EN ((0x000b << 2) + 0xfe000800)
+#define CLKTREE_DSPA_CLK_CTRL0 ((0x000c << 2) + 0xfe000800)
+#define CLKTREE_DSPB_CLK_CTRL0 ((0x000d << 2) + 0xfe000800)
+#define CLKTREE_CLK12_24_CTRL ((0x000e << 2) + 0xfe000800)
+#define CLKTREE_GEN_CLK_CTRL ((0x000f << 2) + 0xfe000800)
+#define CLKTREE_TIMESTAMP_CTRL0 ((0x0010 << 2) + 0xfe000800)
+#define CLKTREE_TIMESTAMP_CTRL1 ((0x0011 << 2) + 0xfe000800)
+#define CLKTREE_TIMESTAMP_CTRL2 ((0x0012 << 2) + 0xfe000800)
+#define CLKTREE_TIMESTAMP_VAL0 ((0x0013 << 2) + 0xfe000800)
+#define CLKTREE_TIMESTAMP_VAL1 ((0x0014 << 2) + 0xfe000800)
+#define CLKTREE_TIMEBASE_CTRL0 ((0x0015 << 2) + 0xfe000800)
+#define CLKTREE_TIMEBASE_CTRL1 ((0x0016 << 2) + 0xfe000800)
+#define CLKTREE_SAR_ADC_CLK_CTRL ((0x0030 << 2) + 0xfe000800)
+#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800)
+#define CLKTREE_PWM_CLK_CD_CTRL ((0x0032 << 2) + 0xfe000800)
+#define CLKTREE_PWM_CLK_EF_CTRL ((0x0033 << 2) + 0xfe000800)
+#define CLKTREE_SPICC_CLK_CTRL ((0x0034 << 2) + 0xfe000800)
+#define CLKTREE_TS_CLK_CTRL ((0x0035 << 2) + 0xfe000800)
+#define CLKTREE_SPIFC_CLK_CTRL ((0x0036 << 2) + 0xfe000800)
+#define CLKTREE_USB_BUSCLK_CTRL ((0x0037 << 2) + 0xfe000800)
+#define CLKTREE_SD_EMMC_CLK_CTRL ((0x0038 << 2) + 0xfe000800)
+#define CLKTREE_CECA_CLK_CTRL0 ((0x0039 << 2) + 0xfe000800)
+#define CLKTREE_CECA_CLK_CTRL1 ((0x003a << 2) + 0xfe000800)
+#define CLKTREE_CECB_CLK_CTRL0 ((0x003b << 2) + 0xfe000800)
+#define CLKTREE_CECB_CLK_CTRL1 ((0x003c << 2) + 0xfe000800)
+#define CLKTREE_PSRAM_CLK_CTRL ((0x003d << 2) + 0xfe000800)
+#define CLKTREE_DMC_CLK_CTRL ((0x003e << 2) + 0xfe000800)
+#define CLKTREE_FCLK_DIV1_SEL ((0x003f << 2) + 0xfe000800)
+#define CLKTREE_TST_CTRL0 ((0x0040 << 2) + 0xfe000800)
+//========================================================================
+// APB0_CEC - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000c00
+// -----------------------------------------------
+#define CECA_GEN_CNTL ((0x0000 << 2) + 0xfe000c00)
+#define CECA_RW_REG ((0x0001 << 2) + 0xfe000c00)
+#define CECA_INTR_MASKN ((0x0002 << 2) + 0xfe000c00)
+#define CECA_INTR_CLR ((0x0003 << 2) + 0xfe000c00)
+#define CECA_INTR_STAT ((0x0004 << 2) + 0xfe000c00)
+#define CECB_GEN_CNTL ((0x0010 << 2) + 0xfe000c00)
+#define CECB_RW_REG ((0x0011 << 2) + 0xfe000c00)
+#define CECB_INTR_MASKN ((0x0012 << 2) + 0xfe000c00)
+#define CECB_INTR_CLR ((0x0013 << 2) + 0xfe000c00)
+#define CECB_INTR_STAT ((0x0014 << 2) + 0xfe000c00)
+//========================================================================
+// APB0_IR_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001000
+// -----------------------------------------------
+#define IRCTRL_IR_DEC_LDR_ACTIVE ((0x0000 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_LDR_IDLE ((0x0001 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_LDR_REPEAT ((0x0002 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_BIT_0 ((0x0003 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_REG0 ((0x0004 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_FRAME ((0x0005 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_STATUS ((0x0006 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_REG1 ((0x0007 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_LDR_ACTIVE ((0x0010 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_LDR_IDLE ((0x0011 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_LDR_REPEAT ((0x0012 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_BIT_0 ((0x0013 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_REG0 ((0x0014 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_FRAME ((0x0015 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_STATUS ((0x0016 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_REG1 ((0x0017 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_REG2 ((0x0018 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_DURATN2 ((0x0019 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_DURATN3 ((0x001a << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_FRAME1 ((0x001b << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_STATUS1 ((0x001c << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_STATUS2 ((0x001d << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_REG3 ((0x001e << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_FRAME_RSV0 ((0x001f << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_FRAME_RSV1 ((0x0020 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_FILTE ((0x0021 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_IRQ_CTL ((0x0022 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_FIFO_CTL ((0x0023 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_WIDTH_NEW ((0x0024 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_REPEAT_DET ((0x0025 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_CNTL0 ((0x0030 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_CNTL1 ((0x0031 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_IIR_THD ((0x0032 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_THD0 ((0x0033 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_THD1 ((0x0034 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_SUM_CNT0 ((0x0035 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_SUM_CNT1 ((0x0036 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_CNT0 ((0x0037 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_CNT1 ((0x0038 << 2) + 0xfe001000)
+#define IRCTRL_IR_BLASTER_ADDR0 ((0x0043 << 2) + 0xfe001000)
+#define IRCTRL_IR_BLASTER_ADDR1 ((0x0044 << 2) + 0xfe001000)
+#define IRCTRL_IR_BLASTER_ADDR2 ((0x0045 << 2) + 0xfe001000)
+#define IRCTRL_IR_BLASTER_ADDR3 ((0x0046 << 2) + 0xfe001000)
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001400
+// -----------------------------------------------
+#define I2C_M_A_CONTROL_REG ((0x0000 << 2) + 0xfe001400)
+#define I2C_M_A_SLAVE_ADDR ((0x0001 << 2) + 0xfe001400)
+#define I2C_M_A_TOKEN_LIST0 ((0x0002 << 2) + 0xfe001400)
+#define I2C_M_A_TOKEN_LIST1 ((0x0003 << 2) + 0xfe001400)
+#define I2C_M_A_WDATA_REG0 ((0x0004 << 2) + 0xfe001400)
+#define I2C_M_A_WDATA_REG1 ((0x0005 << 2) + 0xfe001400)
+#define I2C_M_A_RDATA_REG0 ((0x0006 << 2) + 0xfe001400)
+#define I2C_M_A_RDATA_REG1 ((0x0007 << 2) + 0xfe001400)
+#define I2C_M_A_TIMEOUT_TH ((0x0008 << 2) + 0xfe001400)
+//========================================================================
+// APB0_I2C_S - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001800
+// -----------------------------------------------
+#define I2C_S_A_CONTROL_REG ((0x0000 << 2) + 0xfe001800)
+#define I2C_S_A_SEND_REG ((0x0001 << 2) + 0xfe001800)
+#define I2C_S_A_RECV_REG ((0x0002 << 2) + 0xfe001800)
+#define I2C_S_A_CNTL1_REG ((0x0003 << 2) + 0xfe001800)
+//========================================================================
+// APB0_UART_A - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001c00
+// -----------------------------------------------
+#define UART_A_WFIFO ((0x0000 << 2) + 0xfe001c00)
+#define UART_A_RFIFO ((0x0001 << 2) + 0xfe001c00)
+#define UART_A_CONTROL ((0x0002 << 2) + 0xfe001c00)
+#define UART_A_STATUS ((0x0003 << 2) + 0xfe001c00)
+#define UART_A_MISC ((0x0004 << 2) + 0xfe001c00)
+#define UART_A_REG5 ((0x0005 << 2) + 0xfe001c00)
+//========================================================================
+// APB0_UART_B - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002000
+// -----------------------------------------------
+#define UART_B_WFIFO ((0x0000 << 2) + 0xfe002000)
+#define UART_B_RFIFO ((0x0001 << 2) + 0xfe002000)
+#define UART_B_CONTROL ((0x0002 << 2) + 0xfe002000)
+#define UART_B_STATUS ((0x0003 << 2) + 0xfe002000)
+#define UART_B_MISC ((0x0004 << 2) + 0xfe002000)
+#define UART_B_REG5 ((0x0005 << 2) + 0xfe002000)
+//========================================================================
+// APB0_PWM_AB - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002400
+// -----------------------------------------------
+#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400)
+#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400)
+#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400)
+#define PWMAB_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe002400)
+#define PWMAB_TIME_AB ((0x0004 << 2) + 0xfe002400)
+#define PWMAB_A2 ((0x0005 << 2) + 0xfe002400)
+#define PWMAB_B2 ((0x0006 << 2) + 0xfe002400)
+#define PWMAB_BLINK_AB ((0x0007 << 2) + 0xfe002400)
+#define PWMAB_LOCK_AB ((0x0008 << 2) + 0xfe002400)
+//========================================================================
+// APB0_PWM_CD - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002800
+// -----------------------------------------------
+#define PWMCD_PWM_C ((0x0000 << 2) + 0xfe002800)
+#define PWMCD_PWM_D ((0x0001 << 2) + 0xfe002800)
+#define PWMCD_MISC_REG_CD ((0x0002 << 2) + 0xfe002800)
+#define PWMCD_DELTA_SIGMA_CD ((0x0003 << 2) + 0xfe002800)
+#define PWMCD_TIME_CD ((0x0004 << 2) + 0xfe002800)
+#define PWMCD_C2 ((0x0005 << 2) + 0xfe002800)
+#define PWMCD_D2 ((0x0006 << 2) + 0xfe002800)
+#define PWMCD_BLINK_CD ((0x0007 << 2) + 0xfe002800)
+#define PWMCD_LOCK_CD ((0x0008 << 2) + 0xfe002800)
+//========================================================================
+// APB0_SARADC - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002c00
+// -----------------------------------------------
+#define SAR_ADC_REG0 ((0x0000 << 2) + 0xfe002c00)
+#define SAR_ADC_CHAN_LIST ((0x0001 << 2) + 0xfe002c00)
+#define SAR_ADC_AVG_CNTL ((0x0002 << 2) + 0xfe002c00)
+#define SAR_ADC_REG3 ((0x0003 << 2) + 0xfe002c00)
+#define SAR_ADC_DELAY ((0x0004 << 2) + 0xfe002c00)
+#define SAR_ADC_LAST_RD ((0x0005 << 2) + 0xfe002c00)
+#define SAR_ADC_FIFO_RD ((0x0006 << 2) + 0xfe002c00)
+#define SAR_ADC_AUX_SW ((0x0007 << 2) + 0xfe002c00)
+#define SAR_ADC_CHAN_10_SW ((0x0008 << 2) + 0xfe002c00)
+#define SAR_ADC_DETECT_IDLE_SW ((0x0009 << 2) + 0xfe002c00)
+#define SAR_ADC_DELTA_10 ((0x000a << 2) + 0xfe002c00)
+#define SAR_ADC_REG11 ((0x000b << 2) + 0xfe002c00)
+#define SAR_ADC_REG12 ((0x000c << 2) + 0xfe002c00)
+#define SAR_ADC_REG13 ((0x000d << 2) + 0xfe002c00)
+#define SAR_ADC_CHNL01 ((0x000e << 2) + 0xfe002c00)
+#define SAR_ADC_CHNL23 ((0x000f << 2) + 0xfe002c00)
+#define SAR_ADC_CHNL45 ((0x0010 << 2) + 0xfe002c00)
+#define SAR_ADC_CHNL67 ((0x0011 << 2) + 0xfe002c00)
+//========================================================================
+// JTAGCTRL_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003000
+// -----------------------------------------------
+#define JTAGCTRL_CTRL0 ((0x0000 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_CTRL0 ((0x0001 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_ADDR0 ((0x0002 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_ADDR1 ((0x0003 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_ADDR2 ((0x0004 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_ADDR3 ((0x0005 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_VALUE0 ((0x0006 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_VALUE1 ((0x0007 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_VALUE2 ((0x0008 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_VALUE3 ((0x0009 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_STS ((0x000a << 2) + 0xfe003000)
+//========================================================================
+// APB0_MSR_CLK - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003400
+// -----------------------------------------------
+#define MSR_CLK_REG0 ((0x0000 << 2) + 0xfe003400)
+#define MSR_CLK_REG1 ((0x0001 << 2) + 0xfe003400)
+#define MSR_CLK_REG2 ((0x0002 << 2) + 0xfe003400)
+#define MSR_CLK_REG3 ((0x0003 << 2) + 0xfe003400)
+#define MSR_CLK_REG4 ((0x0004 << 2) + 0xfe003400)
+#define MSR_CLK_REG5 ((0x0005 << 2) + 0xfe003400)
+#define MSR_CLK_DUTY ((0x0006 << 2) + 0xfe003400)
+//========================================================================
+// APB0_SPICCA_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003800
+// -----------------------------------------------
+#define SPICC_A_RXDATA ((0x0000 << 2) + 0xfe003800)
+#define SPICC_A_TXDATA ((0x0001 << 2) + 0xfe003800)
+#define SPICC_A_CONREG ((0x0002 << 2) + 0xfe003800)
+#define SPICC_A_INTREG ((0x0003 << 2) + 0xfe003800)
+#define SPICC_A_DMAREG ((0x0004 << 2) + 0xfe003800)
+#define SPICC_A_STATREG ((0x0005 << 2) + 0xfe003800)
+#define SPICC_A_PERIODREG ((0x0006 << 2) + 0xfe003800)
+#define SPICC_A_TESTREG ((0x0007 << 2) + 0xfe003800)
+#define SPICC_A_DRADDR ((0x0008 << 2) + 0xfe003800)
+#define SPICC_A_DWADDR ((0x0009 << 2) + 0xfe003800)
+#define SPICC_A_LD_CNTL0 ((0x000a << 2) + 0xfe003800)
+#define SPICC_A_LD_CNTL1 ((0x000b << 2) + 0xfe003800)
+#define SPICC_A_LD_RADDR ((0x000c << 2) + 0xfe003800)
+#define SPICC_A_LD_WADDR ((0x000d << 2) + 0xfe003800)
+#define SPICC_A_ENHANCE_CNTL ((0x000e << 2) + 0xfe003800)
+#define SPICC_A_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe003800)
+#define SPICC_A_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe003800)
+//========================================================================
+// APB0_SPICCB_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003c00
+// -----------------------------------------------
+#define SPICC_B_RXDATA ((0x0000 << 2) + 0xfe003c00)
+#define SPICC_B_TXDATA ((0x0001 << 2) + 0xfe003c00)
+#define SPICC_B_CONREG ((0x0002 << 2) + 0xfe003c00)
+#define SPICC_B_INTREG ((0x0003 << 2) + 0xfe003c00)
+#define SPICC_B_DMAREG ((0x0004 << 2) + 0xfe003c00)
+#define SPICC_B_STATREG ((0x0005 << 2) + 0xfe003c00)
+#define SPICC_B_PERIODREG ((0x0006 << 2) + 0xfe003c00)
+#define SPICC_B_TESTREG ((0x0007 << 2) + 0xfe003c00)
+#define SPICC_B_DRADDR ((0x0008 << 2) + 0xfe003c00)
+#define SPICC_B_DWADDR ((0x0009 << 2) + 0xfe003c00)
+#define SPICC_B_LD_CNTL0 ((0x000a << 2) + 0xfe003c00)
+#define SPICC_B_LD_CNTL1 ((0x000b << 2) + 0xfe003c00)
+#define SPICC_B_LD_RADDR ((0x000c << 2) + 0xfe003c00)
+#define SPICC_B_LD_WADDR ((0x000d << 2) + 0xfe003c00)
+#define SPICC_B_ENHANCE_CNTL ((0x000e << 2) + 0xfe003c00)
+#define SPICC_B_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe003c00)
+#define SPICC_B_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe003c00)
+//========================================================================
+// USBCTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe004000
+// -----------------------------------------------
+#define USB_CTRL0 ((0x0000 << 2) + 0xfe004000)
+#define USB_CTRL1 ((0x0001 << 2) + 0xfe004000)
+#define USB_CTRL2 ((0x0002 << 2) + 0xfe004000)
+#define USB_CTRL3 ((0x0003 << 2) + 0xfe004000)
+#define USB_CTRL4 ((0x0004 << 2) + 0xfe004000)
+#define USB_CTRL5 ((0x0005 << 2) + 0xfe004000)
+#define USB_CTRL6 ((0x0006 << 2) + 0xfe004000)
+#define USB_CTRL7 ((0x0007 << 2) + 0xfe004000)
+#define USB_CTRL8 ((0x0008 << 2) + 0xfe004000)
+#define USB_CTRL9 ((0x0009 << 2) + 0xfe004000)
+#define USB_CTRL10 ((0x000a << 2) + 0xfe004000)
+#define USB_CTRL11 ((0x000b << 2) + 0xfe004000)
+#define USB_CTRL12 ((0x000c << 2) + 0xfe004000)
+#define USB_CTRL13 ((0x000d << 2) + 0xfe004000)
+#define USB_CTRL14 ((0x000e << 2) + 0xfe004000)
+#define USB_CTRL15 ((0x000f << 2) + 0xfe004000)
+#define USB_CTRL16 ((0x0010 << 2) + 0xfe004000)
+#define USB_CTRL17 ((0x0011 << 2) + 0xfe004000)
+#define USB_CTRL18 ((0x0012 << 2) + 0xfe004000)
+#define USB_CTRL19 ((0x0013 << 2) + 0xfe004000)
+#define USB_CTRL20 ((0x0014 << 2) + 0xfe004000)
+#define USB_CTRL21 ((0x0015 << 2) + 0xfe004000)
+#define USB_CTRL22 ((0x0016 << 2) + 0xfe004000)
+#define USB_CTRL23 ((0x0017 << 2) + 0xfe004000)
+#define USB_CTRL24 ((0x0018 << 2) + 0xfe004000)
+#define USB_CTRL25 ((0x0019 << 2) + 0xfe004000)
+#define USB_CTRL26 ((0x001a << 2) + 0xfe004000)
+#define USB_CTRL27 ((0x001b << 2) + 0xfe004000)
+#define USB_CTRL28 ((0x001c << 2) + 0xfe004000)
+#define USB_CTRL29 ((0x001d << 2) + 0xfe004000)
+#define USB_CTRL30 ((0x001e << 2) + 0xfe004000)
+#define USB_CTRL31 ((0x001f << 2) + 0xfe004000)
+//========================================================================
+// APB0_ACODEC_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe004800
+// -----------------------------------------------
+#define ACODEC_0 ((0x0000 << 2) + 0xfe004800)
+#define ACODEC_1 ((0x0001 << 2) + 0xfe004800)
+#define ACODEC_2 ((0x0002 << 2) + 0xfe004800)
+#define ACODEC_3 ((0x0003 << 2) + 0xfe004800)
+#define ACODEC_4 ((0x0004 << 2) + 0xfe004800)
+#define ACODEC_5 ((0x0005 << 2) + 0xfe004800)
+#define ACODEC_6 ((0x0006 << 2) + 0xfe004800)
+#define ACODEC_7 ((0x0007 << 2) + 0xfe004800)
+#define ACODEC_8 ((0x0008 << 2) + 0xfe004800)
+#define ACODEC_9 ((0x0009 << 2) + 0xfe004800)
+#define ACODEC_STS0 ((0x0010 << 2) + 0xfe004800)
+//========================================================================
+// APB0_TEMP_SENSOR - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe004c00
+// -----------------------------------------------
+#define TS_CFG_REG1 ((0x0001 << 2) + 0xfe004c00)
+#define TS_CFG_REG2 ((0x0002 << 2) + 0xfe004c00)
+#define TS_CFG_REG3 ((0x0003 << 2) + 0xfe004c00)
+#define TS_CFG_REG4 ((0x0004 << 2) + 0xfe004c00)
+#define TS_CFG_REG5 ((0x0005 << 2) + 0xfe004c00)
+#define TS_CFG_REG6 ((0x0006 << 2) + 0xfe004c00)
+#define TS_CFG_REG7 ((0x0007 << 2) + 0xfe004c00)
+#define TS_STAT0 ((0x0010 << 2) + 0xfe004c00)
+#define TS_STAT1 ((0x0011 << 2) + 0xfe004c00)
+#define TS_STAT2 ((0x0012 << 2) + 0xfe004c00)
+#define TS_STAT3 ((0x0013 << 2) + 0xfe004c00)
+#define TS_STAT4 ((0x0014 << 2) + 0xfe004c00)
+#define TS_STAT5 ((0x0015 << 2) + 0xfe004c00)
+#define TS_STAT6 ((0x0016 << 2) + 0xfe004c00)
+#define TS_STAT7 ((0x0017 << 2) + 0xfe004c00)
+#define TS_STAT8 ((0x0018 << 2) + 0xfe004c00)
+#define TS_STAT9 ((0x0019 << 2) + 0xfe004c00)
+//========================================================================
+// APB0_KL_EFUSE_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005000
+// -----------------------------------------------
+//
+// Reading file: ../crypto/crypto_reg.h
+//
+#define OTP_TEE_RDY ((0x0000 << 2) + 0xfe005000)
+#define OTP_TEE_CHK ((0x0001 << 2) + 0xfe005000)
+#define OTP_TEE_CFG ((0x0002 << 2) + 0xfe005000)
+#define OTP_TEE_WR_DAT0 ((0x0004 << 2) + 0xfe005000)
+#define OTP_TEE_WR_DAT1 ((0x0005 << 2) + 0xfe005000)
+#define OTP_TEE_WR_DAT2 ((0x0006 << 2) + 0xfe005000)
+#define OTP_TEE_WR_DAT3 ((0x0007 << 2) + 0xfe005000)
+#define OTP_TEE_RD_DAT0 ((0x0008 << 2) + 0xfe005000)
+#define OTP_TEE_RD_DAT1 ((0x0009 << 2) + 0xfe005000)
+#define OTP_TEE_RD_DAT2 ((0x000a << 2) + 0xfe005000)
+#define OTP_TEE_RD_DAT3 ((0x000b << 2) + 0xfe005000)
+#define OTP_RMA_PW0 ((0x000c << 2) + 0xfe005000)
+#define OTP_RMA_PW1 ((0x000d << 2) + 0xfe005000)
+#define OTP_RMA_PW2 ((0x000e << 2) + 0xfe005000)
+#define OTP_RMA_PW3 ((0x000f << 2) + 0xfe005000)
+#define OTP_REE_RDY ((0x0010 << 2) + 0xfe005000)
+#define OTP_REE_CHK ((0x0011 << 2) + 0xfe005000)
+#define OTP_REE_CFG ((0x0012 << 2) + 0xfe005000)
+#define OTP_REE_RD_DAT0 ((0x0014 << 2) + 0xfe005000)
+#define OTP_REE_RD_DAT1 ((0x0015 << 2) + 0xfe005000)
+#define OTP_REE_RD_DAT2 ((0x0016 << 2) + 0xfe005000)
+#define OTP_REE_RD_DAT3 ((0x0017 << 2) + 0xfe005000)
+#define OTP_LIC0 ((0x0018 << 2) + 0xfe005000)
+#define OTP_LIC1 ((0x0019 << 2) + 0xfe005000)
+#define OTP_LIC2 ((0x001a << 2) + 0xfe005000)
+#define OTP_LIC3 ((0x001b << 2) + 0xfe005000)
+#define RNG_SEC_CONFIG_REG1 ((0x0041 << 2) + 0xfe005000)
+#define RNG_SEC_CONFIG_REG2 ((0x0042 << 2) + 0xfe005000)
+#define RNG_SEC_DATA ((0x0044 << 2) + 0xfe005000)
+#define RNG_SEC_STS ((0x0045 << 2) + 0xfe005000)
+#define RNG_USR_DATA ((0x0046 << 2) + 0xfe005000)
+#define RNG_USR_STS ((0x0047 << 2) + 0xfe005000)
+#define KTE_SLOT0 ((0x0060 << 2) + 0xfe005000)
+#define KTE_SLOT1 ((0x0061 << 2) + 0xfe005000)
+#define KTE_SLOT2 ((0x0062 << 2) + 0xfe005000)
+#define KTE_SLOT3 ((0x0063 << 2) + 0xfe005000)
+#define KTE_SLOT4 ((0x0064 << 2) + 0xfe005000)
+#define KTE_SLOT5 ((0x0065 << 2) + 0xfe005000)
+#define KTE_SLOT6 ((0x0066 << 2) + 0xfe005000)
+#define KTE_SLOT7 ((0x0067 << 2) + 0xfe005000)
+#define MKL_TEE_RDY ((0x0080 << 2) + 0xfe005000)
+#define MKL_TEE_CHK ((0x0081 << 2) + 0xfe005000)
+#define MKL_TEE_CFG ((0x0082 << 2) + 0xfe005000)
+#define MKL_TEE_EK ((0x0084 << 2) + 0xfe005000)
+#define MKL_REE_RDY ((0x00a0 << 2) + 0xfe005000)
+#define MKL_REE_CHK ((0x00a1 << 2) + 0xfe005000)
+#define MKL_REE_CFG ((0x00a2 << 2) + 0xfe005000)
+#define MKL_REE_EK ((0x00a4 << 2) + 0xfe005000)
+//
+// Closing file: ../crypto/crypto_reg.h
+//
+//========================================================================
+// APB0_PWM_EF - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005400
+// -----------------------------------------------
+#define PWMEF_PWM_E ((0x0000 << 2) + 0xfe005400)
+#define PWMEF_PWM_F ((0x0001 << 2) + 0xfe005400)
+#define PWMEF_MISC_REG_EF ((0x0002 << 2) + 0xfe005400)
+#define PWMEF_DELTA_SIGMA_EF ((0x0003 << 2) + 0xfe005400)
+#define PWMEF_TIME_EF ((0x0004 << 2) + 0xfe005400)
+#define PWMEF_E2 ((0x0005 << 2) + 0xfe005400)
+#define PWMEF_F2 ((0x0006 << 2) + 0xfe005400)
+#define PWMEF_BLINK_EF ((0x0007 << 2) + 0xfe005400)
+#define PWMEF_LOCK_EF ((0x0008 << 2) + 0xfe005400)
+//========================================================================
+// APB0_SYS_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005800
+// -----------------------------------------------
+#define SYSCTRL_METAL_REV0 ((0x0000 << 2) + 0xfe005800)
+#define SYSCTRL_METAL_REV1 ((0x0001 << 2) + 0xfe005800)
+//`define SYSCTRL_PROD_ENABLE 8'h0a
+#define SYSCTRL_CHIP_ID ((0x000b << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE1_REG0 ((0x0010 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE1_STICKY_REG0 ((0x0011 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE1_SEC_REG0 ((0x0012 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE1_STICKY_SEC_REG0 ((0x0013 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE_REG0 ((0x0014 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE_REG1 ((0x0015 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE_SEC_REG0 ((0x0016 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE_STICKY_REG0 ((0x0017 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE_STICKY_REG1 ((0x0018 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE_STICKY_SEC_REG0 ((0x0019 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERA_CTRL ((0x0030 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERA ((0x0031 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERB_CTRL ((0x0032 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERB ((0x0033 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERC_CTRL ((0x0034 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERC ((0x0035 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERD_CTRL ((0x0036 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERD ((0x0037 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_TIMERA_CTRL ((0x0038 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_TIMERA ((0x0039 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERE_CTRL ((0x0040 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERE ((0x0041 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERE_HI ((0x0042 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERF_CTRL ((0x0043 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERF ((0x0044 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERF_HI ((0x0045 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_TIMERE_CTRL ((0x0046 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_TIMERE ((0x0047 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_TIMERE_HI ((0x0048 << 2) + 0xfe005800)
+#define SYSCTRL_OSC_RING_CTRL0 ((0x0050 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_DDR_AXI_SEL ((0x0051 << 2) + 0xfe005800)
+#define SYSCTRL_AM2AXI_CTRL0 ((0x0052 << 2) + 0xfe005800)
+#define SYSCTRL_AM2AXI_STS ((0x0053 << 2) + 0xfe005800)
+#define SYSCTRL_POC ((0x0060 << 2) + 0xfe005800)
+//`define SYSCTRL_PROD_PWD_VALUE0 8'h80
+//`define SYSCTRL_PROD_PWD_VALUE1 8'h81
+//`define SYSCTRL_PROD_PWD_VALUE2 8'h82
+//`define SYSCTRL_PROD_PWD_VALUE3 8'h83
+//`define SYSCTRL_PROD_STATUS 8'h84
+#define SYSCTRL_DEBUG_REG0 ((0x0090 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG1 ((0x0091 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG2 ((0x0092 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG3 ((0x0093 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG4 ((0x0094 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG5 ((0x0095 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG6 ((0x0096 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG7 ((0x0097 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG0 ((0x00a0 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG1 ((0x00a1 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG2 ((0x00a2 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG3 ((0x00a3 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG4 ((0x00a4 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG5 ((0x00a5 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG6 ((0x00a6 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG7 ((0x00a7 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG0 ((0x00b0 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG1 ((0x00b1 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG2 ((0x00b2 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG3 ((0x00b3 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG4 ((0x00b4 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG5 ((0x00b5 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG6 ((0x00b6 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG7 ((0x00b7 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG0 ((0x00c0 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG1 ((0x00c1 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG2 ((0x00c2 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG3 ((0x00c3 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG4 ((0x00c4 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG5 ((0x00c5 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG6 ((0x00c6 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG7 ((0x00c7 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG8 ((0x00c8 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG9 ((0x00c9 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG10 ((0x00ca << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG11 ((0x00cb << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG12 ((0x00cc << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG13 ((0x00cd << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG14 ((0x00ce << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG15 ((0x00cf << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG16 ((0x00d0 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG17 ((0x00d1 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG18 ((0x00d2 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG19 ((0x00d3 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG20 ((0x00d4 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG21 ((0x00d5 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG22 ((0x00d6 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG23 ((0x00d7 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG0 ((0x00e0 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG1 ((0x00e1 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG2 ((0x00e2 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG3 ((0x00e3 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG4 ((0x00e4 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG5 ((0x00e5 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG6 ((0x00e6 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG7 ((0x00e7 << 2) + 0xfe005800)
+#define SYSCTRL_MSG_INDEX0_STICKY ((0x00f0 << 2) + 0xfe005800)
+#define SYSCTRL_MSG_INDEX1_STICKY ((0x00f1 << 2) + 0xfe005800)
+#define SYSCTRL_MSG_INDEX2_STICKY ((0x00f2 << 2) + 0xfe005800)
+#define SYSCTRL_MSG_INDEX3_STICKY ((0x00f3 << 2) + 0xfe005800)
+//========================================================================
+// APB0_I2C_M_B - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005c00
+// -----------------------------------------------
+#define I2C_M_B_CONTROL_REG ((0x0000 << 2) + 0xfe005c00)
+#define I2C_M_B_SLAVE_ADDR ((0x0001 << 2) + 0xfe005c00)
+#define I2C_M_B_TOKEN_LIST0 ((0x0002 << 2) + 0xfe005c00)
+#define I2C_M_B_TOKEN_LIST1 ((0x0003 << 2) + 0xfe005c00)
+#define I2C_M_B_WDATA_REG0 ((0x0004 << 2) + 0xfe005c00)
+#define I2C_M_B_WDATA_REG1 ((0x0005 << 2) + 0xfe005c00)
+#define I2C_M_B_RDATA_REG0 ((0x0006 << 2) + 0xfe005c00)
+#define I2C_M_B_RDATA_REG1 ((0x0007 << 2) + 0xfe005c00)
+#define I2C_M_B_TIMEOUT_TH ((0x0008 << 2) + 0xfe005c00)
+//========================================================================
+// APB0_DMA - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006000
+// -----------------------------------------------
+//TODO
+//========================================================================
+// APB0_IRQ_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006400
+// -----------------------------------------------
+#define IRQCTRL_IRQOUT_MASK0 ((0x0000 << 2) + 0xfe006400)
+#define IRQCTRL_IRQOUT_MASK1 ((0x0001 << 2) + 0xfe006400)
+#define IRQCTRL_IRQOUT_MASK2 ((0x0002 << 2) + 0xfe006400)
+#define IRQCTRL_IRQOUT_MASK3 ((0x0003 << 2) + 0xfe006400)
+#define IRQCTRL_IRQOUT_INV0 ((0x0010 << 2) + 0xfe006400)
+#define IRQCTRL_IRQOUT_INV1 ((0x0011 << 2) + 0xfe006400)
+#define IRQCTRL_IRQOUT_INV2 ((0x0012 << 2) + 0xfe006400)
+#define IRQCTRL_IRQOUT_INV3 ((0x0013 << 2) + 0xfe006400)
+//`define APB0_IRQIN_MASK0_CLK_USB 8'h00
+//`define APB0_IRQIN_MASK0_CLK_CPU 8'h01
+//`define APB0_IRQIN_MASK0_CLK_SYS 8'h02
+//`define APB0_IRQIN_MASK1_CLK_SYS 8'h03
+//`define APB0_IRQIN_MASK0_CLK_DSPA 8'h04
+//`define APB0_IRQIN_MASK0_CLK_DSPB 8'h05
+//`define APB0_IRQIN_CLRLVL_CLK_USB 8'h10
+//`define APB0_IRQIN_CLRLVL_CLK_DSPA 8'h11
+//`define APB0_IRQIN_CLRLVL_CLK_DSPB 8'h12
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006800
+// -----------------------------------------------
+#define I2C_M_C_CONTROL_REG ((0x0000 << 2) + 0xfe006800)
+#define I2C_M_C_SLAVE_ADDR ((0x0001 << 2) + 0xfe006800)
+#define I2C_M_C_TOKEN_LIST0 ((0x0002 << 2) + 0xfe006800)
+#define I2C_M_C_TOKEN_LIST1 ((0x0003 << 2) + 0xfe006800)
+#define I2C_M_C_WDATA_REG0 ((0x0004 << 2) + 0xfe006800)
+#define I2C_M_C_WDATA_REG1 ((0x0005 << 2) + 0xfe006800)
+#define I2C_M_C_RDATA_REG0 ((0x0006 << 2) + 0xfe006800)
+#define I2C_M_C_RDATA_REG1 ((0x0007 << 2) + 0xfe006800)
+#define I2C_M_C_TIMEOUT_TH ((0x0008 << 2) + 0xfe006800)
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006c00
+// -----------------------------------------------
+#define I2C_M_D_CONTROL_REG ((0x0000 << 2) + 0xfe006c00)
+#define I2C_M_D_SLAVE_ADDR ((0x0001 << 2) + 0xfe006c00)
+#define I2C_M_D_TOKEN_LIST0 ((0x0002 << 2) + 0xfe006c00)
+#define I2C_M_D_TOKEN_LIST1 ((0x0003 << 2) + 0xfe006c00)
+#define I2C_M_D_WDATA_REG0 ((0x0004 << 2) + 0xfe006c00)
+#define I2C_M_D_WDATA_REG1 ((0x0005 << 2) + 0xfe006c00)
+#define I2C_M_D_RDATA_REG0 ((0x0006 << 2) + 0xfe006c00)
+#define I2C_M_D_RDATA_REG1 ((0x0007 << 2) + 0xfe006c00)
+#define I2C_M_D_TIMEOUT_TH ((0x0008 << 2) + 0xfe006c00)
+//========================================================================
+// APB0_UART_C - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007000
+// -----------------------------------------------
+#define UART_C_WFIFO ((0x0000 << 2) + 0xfe007000)
+#define UART_C_RFIFO ((0x0001 << 2) + 0xfe007000)
+#define UART_C_CONTROL ((0x0002 << 2) + 0xfe007000)
+#define UART_C_STATUS ((0x0003 << 2) + 0xfe007000)
+#define UART_C_MISC ((0x0004 << 2) + 0xfe007000)
+#define UART_C_REG5 ((0x0005 << 2) + 0xfe007000)
+//========================================================================
+// APB0_PWR_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007800
+// -----------------------------------------------
+#define PWRCTRL_PWR_ACK0 ((0x0000 << 2) + 0xfe007800)
+#define PWRCTRL_ISO_EN0 ((0x0001 << 2) + 0xfe007800)
+#define PWRCTRL_PWR_OFF0 ((0x0002 << 2) + 0xfe007800)
+#define PWRCTRL_SAVE_EN0 ((0x0003 << 2) + 0xfe007800)
+#define PWRCTRL_RESTORE_EN0 ((0x0004 << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD0 ((0x0010 << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD1 ((0x0011 << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD2 ((0x0012 << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD3 ((0x0013 << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD4 ((0x0014 << 2) + 0xfe007800)
+#define PWRCTRL_R_ISO_EN0 ((0x0020 << 2) + 0xfe007800)
+#define PWRCTRL_R_PWR_OFF0 ((0x0021 << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD0 ((0x0022 << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD1 ((0x0023 << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD2 ((0x0024 << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD3 ((0x0025 << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD4 ((0x0026 << 2) + 0xfe007800)
+//`define PWRCTRL_MEM_PD_DSPA 8'h10
+//`define PWRCTRL_MEM_PD_DSPB 8'h11
+//`define PWRCTRL_MEM_PD_RAMA 8'h12
+//`define PWRCTRL_MEM_PD_RAMB 8'h13
+//`define PWRCTRL_MEM_PD_CPU 8'h14
+//`define PWRCTRL_MEM_PD_AUDIO 8'h20
+//`define PWRCTRL_MEM_PD_USBCTRL 8'h21
+//`define PWRCTRL_MEM_PD_SPICC 8'h22
+//`define PWRCTRL_MEM_PD_SPIFC 8'h23
+//`define PWRCTRL_MEM_PD_IR 8'h24
+//`define PWRCTRL_MEM_PD_SDIO 8'h25
+//`define PWRCTRL_MEM_PD_KLEFUSE 8'h26
+//`define PWRCTRL_MEM_PD_PSRAM 8'h27
+//`define PWRCTRL_MEM_PD_DDR 8'h28
+//`define PWRCTRL_MEM_PD_DMC 8'h29
+#define PWRCTRL_AUTO_OFF_CTRL ((0x0030 << 2) + 0xfe007800)
+#define PWRCTRL_AUTO_OFF ((0x0031 << 2) + 0xfe007800)
+#define PWRCTRL_AUTO_OFF_STS ((0x0032 << 2) + 0xfe007800)
+#define PWRCTRL_TIMER_TH_01 ((0x0033 << 2) + 0xfe007800)
+#define PWRCTRL_TIMER_TH_23 ((0x0034 << 2) + 0xfe007800)
+#define PWRCTRL_TIMER_TH_45 ((0x0035 << 2) + 0xfe007800)
+#define PWRCTRL_TIMER_TH_67 ((0x0036 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_PWR_ACK0 ((0x0040 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_RSTN_OFF0 ((0x0041 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_RSTN_ON0 ((0x0042 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_PWR_OFF0 ((0x0043 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_PWR_ON0 ((0x0044 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_ISO_OFF0 ((0x0045 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_ISO_ON0 ((0x0046 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF0 ((0x0050 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF1 ((0x0051 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF2 ((0x0052 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF3 ((0x0053 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF4 ((0x0054 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON0 ((0x0058 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON1 ((0x0059 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON2 ((0x005a << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON3 ((0x005b << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON4 ((0x005c << 2) + 0xfe007800)
+//========================================================================
+// APB0_ANA_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007c00
+// -----------------------------------------------
+#define ANACTRL_FIXPLL_CTRL0 ((0x0020 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_CTRL1 ((0x0021 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_CTRL2 ((0x0022 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_CTRL3 ((0x0023 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_CTRL4 ((0x0024 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_STS ((0x0025 << 2) + 0xfe007c00)
+#define ANACTRL_SYSPLL_CTRL0 ((0x0040 << 2) + 0xfe007c00)
+#define ANACTRL_SYSPLL_CTRL1 ((0x0041 << 2) + 0xfe007c00)
+#define ANACTRL_SYSPLL_CTRL2 ((0x0042 << 2) + 0xfe007c00)
+#define ANACTRL_SYSPLL_CTRL3 ((0x0043 << 2) + 0xfe007c00)
+#define ANACTRL_SYSPLL_CTRL4 ((0x0044 << 2) + 0xfe007c00)
+#define ANACTRL_SYSPLL_STS ((0x0045 << 2) + 0xfe007c00)
+#define ANACTRL_HIFIPLL_CTRL0 ((0x0050 << 2) + 0xfe007c00)
+#define ANACTRL_HIFIPLL_CTRL1 ((0x0051 << 2) + 0xfe007c00)
+#define ANACTRL_HIFIPLL_CTRL2 ((0x0052 << 2) + 0xfe007c00)
+#define ANACTRL_HIFIPLL_CTRL3 ((0x0053 << 2) + 0xfe007c00)
+#define ANACTRL_HIFIPLL_CTRL4 ((0x0054 << 2) + 0xfe007c00)
+#define ANACTRL_HIFIPLL_STS ((0x0055 << 2) + 0xfe007c00)
+#define ANACTRL_AUDDDS_CTRL0 ((0x0060 << 2) + 0xfe007c00)
+#define ANACTRL_AUDDDS_CTRL1 ((0x0061 << 2) + 0xfe007c00)
+#define ANACTRL_AUDDDS_CTRL2 ((0x0062 << 2) + 0xfe007c00)
+#define ANACTRL_AUDDDS_CTRL3 ((0x0063 << 2) + 0xfe007c00)
+#define ANACTRL_AUDDDS_CTRL4 ((0x0064 << 2) + 0xfe007c00)
+#define ANACTRL_AUDDDS_STS ((0x0065 << 2) + 0xfe007c00)
+#define ANACTRL_MISCTOP_CTRL0 ((0x0070 << 2) + 0xfe007c00)
+#define ANACTRL_POR_CNTL ((0x0082 << 2) + 0xfe007c00)
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe020000
+// -----------------------------------------------
+#define RSA_BASE ((0x0000 << 2) + 0xfe020000)
+//========================================================================
+// CPUCTRL_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd000000
+// -----------------------------------------------
+#define CPUCTRL_CTRL0 ((0x0000 << 2) + 0xfd000000)
+#define CPUCTRL_CTRL1 ((0x0001 << 2) + 0xfd000000)
+#define CPUCTRL_CTRL2 ((0x0002 << 2) + 0xfd000000)
+#define CPUCTRL_CTRL3 ((0x0003 << 2) + 0xfd000000)
+#define CPUCTRL_CTRL4 ((0x0004 << 2) + 0xfd000000)
+#define CPUCTRL_CTRL5 ((0x0005 << 2) + 0xfd000000)
+#define CPUCTRL_CTRL6 ((0x0006 << 2) + 0xfd000000)
+#define CPUCTRL_CTRL7 ((0x0007 << 2) + 0xfd000000)
+#define CPUCTRL_CTRL8 ((0x0008 << 2) + 0xfd000000)
+#define CPUCTRL_CTRL9 ((0x0009 << 2) + 0xfd000000)
+#define CPUCTRL_CTRL10 ((0x000a << 2) + 0xfd000000)
+#define CPUCTRL_CTRL11 ((0x000b << 2) + 0xfd000000)
+#define CPUCTRL_CTRL12 ((0x000c << 2) + 0xfd000000)
+#define CPUCTRL_CTRL13 ((0x000d << 2) + 0xfd000000)
+#define CPUCTRL_CTRL14 ((0x000e << 2) + 0xfd000000)
+#define CPUCTRL_CTRL15 ((0x000f << 2) + 0xfd000000)
+#define CPUCTRL_STS0 ((0x0010 << 2) + 0xfd000000)
+#define CPUCTRL_STS1 ((0x0011 << 2) + 0xfd000000)
+#define CPUCTRL_STS2 ((0x0012 << 2) + 0xfd000000)
+#define CPUCTRL_STS3 ((0x0013 << 2) + 0xfd000000)
+#define CPUCTRL_STS4 ((0x0014 << 2) + 0xfd000000)
+#define CPUCTRL_STS5 ((0x0015 << 2) + 0xfd000000)
+#define CPUCTRL_STS6 ((0x0016 << 2) + 0xfd000000)
+#define CPUCTRL_STS7 ((0x0017 << 2) + 0xfd000000)
+#define CPUCTRL_STS8 ((0x0018 << 2) + 0xfd000000)
+#define CPUCTRL_STS9 ((0x0019 << 2) + 0xfd000000)
+#define CPUCTRL_CLK_CTRL0 ((0x0020 << 2) + 0xfd000000)
+#define CPUCTRL_CLK_CTRL1 ((0x0021 << 2) + 0xfd000000)
+#define CPUCTRL_CLK_CTRL2 ((0x0022 << 2) + 0xfd000000)
+#define CPUCTRL_CLK_CTRL3 ((0x0023 << 2) + 0xfd000000)
+#define CPUCTRL_CLK_CTRL4 ((0x0024 << 2) + 0xfd000000)
+#define CPUCTRL_CLK_CTRL5 ((0x0025 << 2) + 0xfd000000)
+#define CPUCTRL_CLK_CTRL6 ((0x0026 << 2) + 0xfd000000)
+#define CPUCTRL_CLK_CTRL7 ((0x0027 << 2) + 0xfd000000)
+#define CPUCTRL_RESET_CTRL ((0x0030 << 2) + 0xfd000000)
+#define CPUCTRL_ROM_DISABLE ((0x0031 << 2) + 0xfd000000)
+//========================================================================
+// RAMA_SEC_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd000800
+// -----------------------------------------------
+#define SRAM_RANGE0_STA ((0x0000 << 2) + 0xfd000800)
+#define SRAM_RANGE1_STA ((0x0001 << 2) + 0xfd000800)
+#define SRAM_RANGE2_STA ((0x0002 << 2) + 0xfd000800)
+#define SRAM_RANGE3_STA ((0x0003 << 2) + 0xfd000800)
+#define SRAM_RANGE4_STA ((0x0004 << 2) + 0xfd000800)
+#define SRAM_RANGE5_STA ((0x0005 << 2) + 0xfd000800)
+#define SRAM_RANGE6_STA ((0x0006 << 2) + 0xfd000800)
+#define SRAM_RANGE0_EDA ((0x0007 << 2) + 0xfd000800)
+#define SRAM_RANGE1_EDA ((0x0008 << 2) + 0xfd000800)
+#define SRAM_RANGE2_EDA ((0x0009 << 2) + 0xfd000800)
+#define SRAM_RANGE3_EDA ((0x000a << 2) + 0xfd000800)
+#define SRAM_RANGE4_EDA ((0x000b << 2) + 0xfd000800)
+#define SRAM_RANGE5_EDA ((0x000c << 2) + 0xfd000800)
+#define SRAM_RANGE6_EDA ((0x000d << 2) + 0xfd000800)
+#define SRAM_RANGE0_CTRL0 ((0x000e << 2) + 0xfd000800)
+#define SRAM_RANGE1_CTRL0 ((0x000f << 2) + 0xfd000800)
+#define SRAM_RANGE2_CTRL0 ((0x0010 << 2) + 0xfd000800)
+#define SRAM_RANGE3_CTRL0 ((0x0011 << 2) + 0xfd000800)
+#define SRAM_RANGE4_CTRL0 ((0x0012 << 2) + 0xfd000800)
+#define SRAM_RANGE5_CTRL0 ((0x0013 << 2) + 0xfd000800)
+#define SRAM_RANGE6_CTRL0 ((0x0014 << 2) + 0xfd000800)
+#define SRAM_RANGE7_CTRL0 ((0x0015 << 2) + 0xfd000800)
+#define SRAM_RANGE0_CTRL1 ((0x0016 << 2) + 0xfd000800)
+#define SRAM_RANGE1_CTRL1 ((0x0017 << 2) + 0xfd000800)
+#define SRAM_RANGE2_CTRL1 ((0x0018 << 2) + 0xfd000800)
+#define SRAM_RANGE3_CTRL1 ((0x0019 << 2) + 0xfd000800)
+#define SRAM_RANGE4_CTRL1 ((0x001a << 2) + 0xfd000800)
+#define SRAM_RANGE5_CTRL1 ((0x001b << 2) + 0xfd000800)
+#define SRAM_RANGE6_CTRL1 ((0x001c << 2) + 0xfd000800)
+#define SRAM_RANGE7_CTRL1 ((0x001d << 2) + 0xfd000800)
+#define SRAM_SEC_CTRL0 ((0x001e << 2) + 0xfd000800)
+#define SRAM_REG_LOCK ((0x001f << 2) + 0xfd000800)
+//========================================================================
+// RAMB_SEC_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd000c00
+// -----------------------------------------------
+#define SRAM_RANGE0_STA_B ((0x0000 << 2) + 0xfd000c00)
+#define SRAM_RANGE1_STA_B ((0x0001 << 2) + 0xfd000c00)
+#define SRAM_RANGE2_STA_B ((0x0002 << 2) + 0xfd000c00)
+#define SRAM_RANGE3_STA_B ((0x0003 << 2) + 0xfd000c00)
+#define SRAM_RANGE4_STA_B ((0x0004 << 2) + 0xfd000c00)
+#define SRAM_RANGE5_STA_B ((0x0005 << 2) + 0xfd000c00)
+#define SRAM_RANGE6_STA_B ((0x0006 << 2) + 0xfd000c00)
+#define SRAM_RANGE0_EDA_B ((0x0007 << 2) + 0xfd000c00)
+#define SRAM_RANGE1_EDA_B ((0x0008 << 2) + 0xfd000c00)
+#define SRAM_RANGE2_EDA_B ((0x0009 << 2) + 0xfd000c00)
+#define SRAM_RANGE3_EDA_B ((0x000a << 2) + 0xfd000c00)
+#define SRAM_RANGE4_EDA_B ((0x000b << 2) + 0xfd000c00)
+#define SRAM_RANGE5_EDA_B ((0x000c << 2) + 0xfd000c00)
+#define SRAM_RANGE6_EDA_B ((0x000d << 2) + 0xfd000c00)
+#define SRAM_RANGE0_CTRL0_B ((0x000e << 2) + 0xfd000c00)
+#define SRAM_RANGE1_CTRL0_B ((0x000f << 2) + 0xfd000c00)
+#define SRAM_RANGE2_CTRL0_B ((0x0010 << 2) + 0xfd000c00)
+#define SRAM_RANGE3_CTRL0_B ((0x0011 << 2) + 0xfd000c00)
+#define SRAM_RANGE4_CTRL0_B ((0x0012 << 2) + 0xfd000c00)
+#define SRAM_RANGE5_CTRL0_B ((0x0013 << 2) + 0xfd000c00)
+#define SRAM_RANGE6_CTRL0_B ((0x0014 << 2) + 0xfd000c00)
+#define SRAM_RANGE7_CTRL0_B ((0x0015 << 2) + 0xfd000c00)
+#define SRAM_RANGE0_CTRL1_B ((0x0016 << 2) + 0xfd000c00)
+#define SRAM_RANGE1_CTRL1_B ((0x0017 << 2) + 0xfd000c00)
+#define SRAM_RANGE2_CTRL1_B ((0x0018 << 2) + 0xfd000c00)
+#define SRAM_RANGE3_CTRL1_B ((0x0019 << 2) + 0xfd000c00)
+#define SRAM_RANGE4_CTRL1_B ((0x001a << 2) + 0xfd000c00)
+#define SRAM_RANGE5_CTRL1_B ((0x001b << 2) + 0xfd000c00)
+#define SRAM_RANGE6_CTRL1_B ((0x001c << 2) + 0xfd000c00)
+#define SRAM_RANGE7_CTRL1_B ((0x001d << 2) + 0xfd000c00)
+#define SRAM_SEC_CTRL0_B ((0x001e << 2) + 0xfd000c00)
+#define SRAM_REG_LOCK_B ((0x001f << 2) + 0xfd000c00)
+//
+// Reading file: REG_LIST_DSP_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//========================================================================
+// DSPA - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe030000
+// -----------------------------------------------
+#define DSP_CFG0 ((0x0000 << 2) + 0xfe030000)
+#define DSP_CFG1 ((0x0001 << 2) + 0xfe030000)
+#define DSP_CFG2 ((0x0002 << 2) + 0xfe030000)
+#define DSP_IMPWIRE ((0x0003 << 2) + 0xfe030000)
+#define DSP_RESET_VEC ((0x0004 << 2) + 0xfe030000)
+#define DSP_SEC_CFG0 ((0x0006 << 2) + 0xfe030000)
+#define DSP_SEC_CFG1 ((0x0007 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL0 ((0x0010 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL1 ((0x0011 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL2 ((0x0012 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL3 ((0x0013 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL4 ((0x0014 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL5 ((0x0015 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL6 ((0x0016 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL7 ((0x0017 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL8 ((0x0018 << 2) + 0xfe030000)
+#define DSP_IRQ_STS ((0x001f << 2) + 0xfe030000)
+#define DSP_REMAP0 ((0x0020 << 2) + 0xfe030000)
+#define DSP_REMAP1 ((0x0021 << 2) + 0xfe030000)
+#define DSP_REMAP2 ((0x0022 << 2) + 0xfe030000)
+#define DSP_STS0 ((0x0040 << 2) + 0xfe030000)
+#define DSP_STS1 ((0x0041 << 2) + 0xfe030000)
+#define DSP_STS2 ((0x0042 << 2) + 0xfe030000)
+#define DSP_STS3 ((0x0043 << 2) + 0xfe030000)
+#define DSP_STS4 ((0x0044 << 2) + 0xfe030000)
+#define DSP_STS5 ((0x0045 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_0 ((0x0050 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_1 ((0x0051 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_2 ((0x0052 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_3 ((0x0053 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_4 ((0x0054 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_5 ((0x0055 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_6 ((0x0056 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_7 ((0x0057 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_8 ((0x0058 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_9 ((0x0059 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_10 ((0x005a << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_11 ((0x005b << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_0 ((0x0060 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_1 ((0x0061 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_2 ((0x0062 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_3 ((0x0063 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_4 ((0x0064 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_5 ((0x0065 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_6 ((0x0066 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_7 ((0x0067 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_8 ((0x0068 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_9 ((0x0069 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_10 ((0x006a << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_11 ((0x006b << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_0 ((0x0070 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_1 ((0x0071 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_2 ((0x0072 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_3 ((0x0073 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_4 ((0x0074 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_5 ((0x0075 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_6 ((0x0076 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_7 ((0x0077 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_8 ((0x0078 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_9 ((0x0079 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_10 ((0x007a << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_11 ((0x007b << 2) + 0xfe030000)
+#define DSP_QIF_CTRL ((0x0080 << 2) + 0xfe030000)
+#define DSP_QIF_STS ((0x0081 << 2) + 0xfe030000)
+#define DSP_WRFIFO_TOCPUA ((0x0082 << 2) + 0xfe030000)
+#define DSP_WRFIFO_TOCPUB ((0x0083 << 2) + 0xfe030000)
+#define DSP_WRFIFO_TODSP ((0x0084 << 2) + 0xfe030000)
+#define DSP_RDFIFO_FRCPUA ((0x0088 << 2) + 0xfe030000)
+#define DSP_RDFIFO_FRCPUB ((0x0089 << 2) + 0xfe030000)
+#define DSP_RDFIFO_FRDSP ((0x008a << 2) + 0xfe030000)
+//========================================================================
+// DSPB - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe040000
+// -----------------------------------------------
+#define DSPB_CFG0 ((0x0000 << 2) + 0xfe040000)
+#define DSPB_CFG1 ((0x0001 << 2) + 0xfe040000)
+#define DSPB_CFG2 ((0x0002 << 2) + 0xfe040000)
+#define DSPB_IMPWIRE ((0x0003 << 2) + 0xfe040000)
+#define DSPB_RESET_VEC ((0x0004 << 2) + 0xfe040000)
+#define DSPB_SEC_CFG0 ((0x0006 << 2) + 0xfe040000)
+#define DSPB_SEC_CFG1 ((0x0007 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL0 ((0x0010 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL1 ((0x0011 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL2 ((0x0012 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL3 ((0x0013 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL4 ((0x0014 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL5 ((0x0015 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL6 ((0x0016 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL7 ((0x0017 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL8 ((0x0018 << 2) + 0xfe040000)
+#define DSPB_IRQ_STS ((0x001f << 2) + 0xfe040000)
+#define DSPB_REMAP0 ((0x0020 << 2) + 0xfe040000)
+#define DSPB_REMAP1 ((0x0021 << 2) + 0xfe040000)
+#define DSPB_REMAP2 ((0x0022 << 2) + 0xfe040000)
+#define DSPB_STS0 ((0x0040 << 2) + 0xfe040000)
+#define DSPB_STS1 ((0x0041 << 2) + 0xfe040000)
+#define DSPB_STS2 ((0x0042 << 2) + 0xfe040000)
+#define DSPB_STS3 ((0x0043 << 2) + 0xfe040000)
+#define DSPB_STS4 ((0x0044 << 2) + 0xfe040000)
+#define DSPB_STS5 ((0x0045 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_0 ((0x0050 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_1 ((0x0051 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_2 ((0x0052 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_3 ((0x0053 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_4 ((0x0054 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_5 ((0x0055 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_6 ((0x0056 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_7 ((0x0057 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_8 ((0x0058 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_9 ((0x0059 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_10 ((0x005a << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_11 ((0x005b << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_0 ((0x0060 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_1 ((0x0061 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_2 ((0x0062 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_3 ((0x0063 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_4 ((0x0064 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_5 ((0x0065 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_6 ((0x0066 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_7 ((0x0067 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_8 ((0x0068 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_9 ((0x0069 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_10 ((0x006a << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_11 ((0x006b << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_0 ((0x0070 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_1 ((0x0071 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_2 ((0x0072 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_3 ((0x0073 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_4 ((0x0074 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_5 ((0x0075 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_6 ((0x0076 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_7 ((0x0077 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_8 ((0x0078 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_9 ((0x0079 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_10 ((0x007a << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_11 ((0x007b << 2) + 0xfe040000)
+#define DSPB_QIF_CTRL ((0x0080 << 2) + 0xfe040000)
+#define DSPB_QIF_STS ((0x0081 << 2) + 0xfe040000)
+#define DSPB_WRFIFO_TOCPUA ((0x0082 << 2) + 0xfe040000)
+#define DSPB_WRFIFO_TOCPUB ((0x0083 << 2) + 0xfe040000)
+#define DSPB_WRFIFO_TODSP ((0x0084 << 2) + 0xfe040000)
+#define DSPB_RDFIFO_FRCPUA ((0x0088 << 2) + 0xfe040000)
+#define DSPB_RDFIFO_FRCPUB ((0x0089 << 2) + 0xfe040000)
+#define DSPB_RDFIFO_FRDSP ((0x008a << 2) + 0xfe040000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: REG_LIST_DSP_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: ./REG_LIST_RTL.h
+//
+#include "soc_def.h"
+#endif // REGISTER_H
+
diff --git a/arch/arm/include/asm/arch-a1/regs.h b/arch/arm/include/asm/arch-a1/regs.h
new file mode 100644
index 0000000..5c23c59
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/regs.h
@@ -0,0 +1,5 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
diff --git a/arch/arm/include/asm/arch-a1/romboot.h b/arch/arm/include/asm/arch-a1/romboot.h
new file mode 100644
index 0000000..2967fbb
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/romboot.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOOT_ROM_H_
+#define __BOOT_ROM_H_
+#ifndef __ASSEMBLY__
+//#include <stdint.h>
+//uint8_t simple_i2c(uint8_t adr);
+//void spi_pin_mux(void);
+//void spi_init(void);
+//uint32_t spi_read(uint32_t src, uint32_t mem, uint32_t size);
+//void udelay(uint32_t usec);
+//void boot_des_decrypt(uint8_t *ct, uint8_t *pt, uint32_t size);
+
+#endif /* ! __ASSEMBLY__ */
+#include "config.h"
+
+/* Magic number to "boot" up A53 */
+#define AO_SEC_SD_CFG10_CB 0x80000000
+
+/*BOOT device and ddr size*/
+/*31-28: boot device id, 27-24: boot device para, 23-20: reserved*/
+/*19-8: ddr size, 7-0: board revision*/
+//#define P_AO_SEC_GP_CFG0 0xDA100240 //defined in secure_apb.h
+#define AO_SEC_GP_CFG7_W0_BIT 8
+#define AO_SEC_GP_CFG7_W0 0x100
+
+#define BOOT_ID_RESERVED 0
+#define BOOT_ID_EMMC 1
+#define BOOT_ID_NAND 2
+#define BOOT_ID_SPI 3
+#define BOOT_ID_SDCARD 4
+#define BOOT_ID_USB 5
+
+#endif /* __BOOT_ROM_H_ */
diff --git a/arch/arm/include/asm/arch-a1/sd_emmc.h b/arch/arm/include/asm/arch-a1/sd_emmc.h
new file mode 100644
index 0000000..501b590
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/sd_emmc.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __SD_EMMC_H__
+#define __SD_EMMC_H__
+
+#include <mmc.h>
+
+#define SDIO_PORT_A 0
+#define SDIO_PORT_B 1
+#define SDIO_PORT_C 2
+
+#define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */
+#define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */
+
+
+#define MESON_SD_EMMC_CLOCK 0x00
+#define CLK_MAX_DIV 63
+#define Cfg_div 0
+#define Cfg_src 6
+#define Cfg_co_phase 8
+#define Cfg_tx_phase 10
+#define Cfg_rx_phase 12
+#define Cfg_sram_pd 14
+#define Cfg_tx_delay 16
+#define Cfg_rx_delay 22
+#define Cfg_always_on 28
+#define Cfg_irq_sdio_sleep 29
+#define Cfg_irq_sdio_sleep_ds 30
+
+#define MESON_SD_EMMC_CFG 0x44
+#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
+#define CFG_BUS_WIDTH_1 0
+#define CFG_BUS_WIDTH_4 1
+#define CFG_BUS_WIDTH_8 2
+#define CFG_BL_LEN_MASK GENMASK(7, 4)
+#define CFG_BL_LEN_SHIFT 4
+#define CFG_BL_LEN_512 (9 << 4)
+#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
+#define CFG_RESP_TIMEOUT_256 (8 << 8)
+#define CFG_RC_CC_MASK GENMASK(15, 12)
+#define CFG_RC_CC_16 (4 << 12)
+#define CFG_SDCLK_ALWAYS_ON BIT(18)
+#define CFG_AUTO_CLK BIT(23)
+
+#define MESON_SD_EMMC_STATUS 0x48
+#define STATUS_MASK GENMASK(15, 0)
+#define STATUS_ERR_MASK GENMASK(12, 0)
+#define STATUS_RXD_ERR_MASK GENMASK(7, 0)
+#define STATUS_TXD_ERR BIT(8)
+#define STATUS_DESC_ERR BIT(9)
+#define STATUS_RESP_ERR BIT(10)
+#define STATUS_RESP_TIMEOUT BIT(11)
+#define STATUS_DESC_TIMEOUT BIT(12)
+#define STATUS_END_OF_CHAIN BIT(13)
+
+#define MESON_SD_EMMC_IRQ_EN 0x4c
+
+#define MESON_SD_EMMC_CMD_CFG 0x50
+#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
+#define CMD_CFG_BLOCK_MODE BIT(9)
+#define CMD_CFG_R1B BIT(10)
+#define CMD_CFG_END_OF_CHAIN BIT(11)
+#define CMD_CFG_TIMEOUT_4S (12 << 12)
+#define CMD_CFG_NO_RESP BIT(16)
+#define CMD_CFG_DATA_IO BIT(18)
+#define CMD_CFG_DATA_WR BIT(19)
+#define CMD_CFG_RESP_NOCRC BIT(20)
+#define CMD_CFG_RESP_128 BIT(21)
+#define CMD_CFG_CMD_INDEX_SHIFT 24
+#define CMD_CFG_OWNER BIT(31)
+
+#define MESON_SD_EMMC_CMD_ARG 0x54
+#define MESON_SD_EMMC_CMD_DAT 0x58
+#define MESON_SD_EMMC_CMD_RSP 0x5c
+#define MESON_SD_EMMC_CMD_RSP1 0x60
+#define MESON_SD_EMMC_CMD_RSP2 0x64
+#define MESON_SD_EMMC_CMD_RSP3 0x68
+
+struct meson_mmc_platdata {
+ struct mmc_config cfg;
+ struct mmc mmc;
+ void *regbase;
+ void *w_buf;
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-a1/secure_apb.h b/arch/arm/include/asm/arch-a1/secure_apb.h
new file mode 100644
index 0000000..428610a
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/secure_apb.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/regs.h>
+#include <asm/arch/register.h>
diff --git a/arch/arm/include/asm/arch-a1/soc_def.h b/arch/arm/include/asm/arch-a1/soc_def.h
new file mode 100644
index 0000000..f0a0b1a
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/soc_def.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __A1_DEF_H__
+#define __A1_DEF_H__
+
+#define SEC_AO_SEC_GP_CFG2 (SYSCTRL_SEC_STATUS_REG6)
+
+#endif /* __A1_DEF_H__ */
diff --git a/arch/arm/include/asm/arch-a1/timer.h b/arch/arm/include/asm/arch-a1/timer.h
new file mode 100644
index 0000000..492cc8d
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/timer.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __TIMER_H
+#define __TIMER_H
+
+#include <asm/arch/romboot.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/io.h>
+
+/**
+ * Get the current timestamp from the system timer.
+ */
+uint32_t get_time(void);
+
+/**
+ * Busy-wait.
+ *
+ * @param us Number of microseconds to delay.
+ */
+void _udelay(unsigned int us);
+
+#endif /* __TIMER_H */
diff --git a/arch/arm/include/asm/arch-a1/timing.h b/arch/arm/include/asm/arch-a1/timing.h
new file mode 100644
index 0000000..a431d1b
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/timing.h
@@ -0,0 +1,528 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AML_TIMING_H_
+#define __AML_TIMING_H_
+
+#include <asm/arch/ddr_define.h>
+#include <asm/arch/types.h>
+#include <asm/arch/mnPmuSramMsgBlock_ddr3.h>
+#include <asm/arch/mnPmuSramMsgBlock_ddr4.h>
+#include <asm/arch/mnPmuSramMsgBlock_ddr4_2d.h>
+#include <asm/arch/mnPmuSramMsgBlock_lpddr3.h>
+#include <asm/arch/mnPmuSramMsgBlock_lpddr4.h>
+#include <asm/arch/mnPmuSramMsgBlock_lpddr4_2d.h>
+
+#define BL2_INIT_STAGE_0 0
+#define BL2_INIT_STAGE_1 1
+#define BL2_INIT_STAGE_2 2
+#define BL2_INIT_STAGE_3 3
+#define BL2_INIT_STAGE_4 4
+#define BL2_INIT_STAGE_5 5
+#define BL2_INIT_STAGE_6 6
+#define BL2_INIT_STAGE_7 7
+#define BL2_INIT_STAGE_8 8
+#define BL2_INIT_STAGE_9 9
+
+#define BL2_INIT_STAGE_POWERKEY_PRE_INIT 0x81
+#define BL2_INIT_STAGE_POWERKEY_CHK_HW 0x82
+#define BL2_INIT_STAGE_POWERKEY_CFG_GROUP 0x83
+#define BL2_INIT_STAGE_POWERKEY_INIT 0xC0
+
+#define POWERKEY_CFG0 0
+#define POWERKEY_CFG1 1
+#define POWERKEY_CFG2 2
+#define POWERKEY_CFG3 3
+
+/* Share vddcore parameters with bl2 */
+#define BL2_INIT_STAGE_VDDCORE_TABLE 0x84
+#define BL2_INIT_STAGE_VDDCORE_CONFIG 0x85
+#define BL2_INIT_STAGE_VDDCORE_CONFIG_1 0x86
+
+typedef struct bl2_reg {
+ unsigned int reg;
+ unsigned int value;
+ unsigned int mask;
+ unsigned short udelay;
+ unsigned char flag;
+ unsigned char rsv_0;
+}__attribute__ ((packed)) bl2_reg_t;
+
+typedef struct ddr_reg {
+ unsigned int reg;
+ unsigned int value;
+ unsigned int mask;
+ unsigned short udelay;
+ unsigned char flag;
+ unsigned char rsv_0;
+}__attribute__ ((packed)) ddr_reg_t;
+
+typedef struct training_delay_set_ps{
+ unsigned char ac_trace_delay[10];
+ unsigned char ac_trace_delay_rev[2];
+ unsigned char read_dqs_delay[16];
+ unsigned char read_dq_bit_delay[72];
+ unsigned short write_dqs_delay[16];
+// */
+ unsigned short write_dq_bit_delay[72];
+ unsigned short read_dqs_gate_delay[16];
+ unsigned char soc_bit_vref[36];
+ unsigned char dram_bit_vref[32];
+ ///*
+ unsigned char rever1;//read_dqs read_dq,write_dqs, write_dq
+ unsigned char dfi_mrl;
+ unsigned char dfi_hwtmrl;
+ unsigned char ARdPtrInitVal;
+ unsigned short csr_vrefinglobal;
+ unsigned short csr_dqsrcvcntrl[4];
+ unsigned short csr_pptdqscntinvtrntg0[4];
+ unsigned short csr_pptdqscntinvtrntg1[4];
+ unsigned short csr_seq0bgpr[9];
+ unsigned short csr_dllgainctl;
+ unsigned short csr_dlllockpara;
+// unsigned short rever2;
+}__attribute__ ((packed)) training_delay_set_ps_t;
+
+typedef struct ddr_mrs_reg {
+ unsigned int cfg_ddr_mr[8];
+ unsigned int cfg_ddr_mr11;
+ unsigned int cfg_ddr_mr12;
+ unsigned int cfg_ddr_mr13;
+ unsigned int cfg_ddr_mr14;
+ unsigned int cfg_ddr_mr16;
+ unsigned int cfg_ddr_mr17;
+ unsigned int cfg_ddr_mr22;
+ unsigned int cfg_ddr_mr24;
+}__attribute__ ((packed)) ddr_mrs_reg_t;
+
+typedef struct ddr_timing{
+ unsigned int identifier;
+ unsigned int cfg_ddr_mrd;
+ unsigned int cfg_ddr_rfcab;
+ unsigned int cfg_ddr_rfcpb;
+ unsigned int cfg_ddr_rpab;
+ unsigned int cfg_ddr_rppb;
+ unsigned int cfg_ddr_rtw;
+ unsigned int cfg_ddr_rl;
+ unsigned int cfg_ddr_wl;
+ unsigned int cfg_ddr_ras;
+ unsigned int cfg_ddr_rc;
+ unsigned int cfg_ddr_rcd;
+ unsigned int cfg_ddr_rrds;
+ unsigned int cfg_ddr_rrdl;
+ unsigned int cfg_ddr_faw;
+ unsigned int cfg_ddr_rtp;
+ unsigned int cfg_ddr_wr;
+ unsigned int cfg_ddr_wtrs;
+ unsigned int cfg_ddr_wtrl;
+ unsigned int cfg_ddr_ccds;
+ unsigned int cfg_ddr_ccdl;
+ unsigned int cfg_ddr_exsr;
+ unsigned int cfg_ddr_xs;
+ unsigned int cfg_ddr_xp;
+ unsigned int cfg_ddr_xpdll;
+ unsigned int cfg_ddr_zqcs;
+ unsigned int cfg_ddr_cksre;
+ unsigned int cfg_ddr_cksrx;
+ unsigned int cfg_ddr_cke;
+ unsigned int cfg_ddr_mod;
+ unsigned int cfg_ddr_dqs;
+ unsigned int cfg_ddr_rstl;
+ unsigned int cfg_ddr_zqlat;
+ unsigned int cfg_ddr_mrr;
+ unsigned int cfg_ddr_ckesr;
+ unsigned int cfg_ddr_dpd;
+ unsigned int cfg_ddr_ckeck;
+ unsigned int cfg_ddr_refi;
+ unsigned int cfg_ddr_sr;
+ unsigned int cfg_ddr_ccdmw;
+ unsigned int cfg_ddr_escke;
+ unsigned int cfg_ddr_refi_ddr3;
+ unsigned int cfg_ddr_dfictrldelay;
+ unsigned int cfg_ddr_dfiphywrdata;
+ unsigned int cfg_ddr_dfiphywrlat;
+ unsigned int cfg_ddr_dfiphyrddataen;
+ unsigned int cfg_ddr_dfiphyrdlat;
+ unsigned int cfg_ddr_dfictrlupdmin;
+ unsigned int cfg_ddr_dfictrlupdmax;
+ unsigned int cfg_ddr_dfimstrresp;
+ unsigned int cfg_ddr_dfirefmski;
+ unsigned int cfg_ddr_dfictrlupdi;
+ unsigned int cfg_ddr_dfidramclk;
+ unsigned int cfg_ddr_dfilpresp;
+ unsigned int cfg_ddr_dfiphymstr;
+ unsigned int cfg_ddr_rtodt;
+ unsigned int cfg_ddr_wlmrd;
+ unsigned int cfg_ddr_wlo;
+ unsigned int cfg_ddr_al;
+ unsigned int cfg_ddr_zqcl;
+ unsigned int cfg_ddr_zqcsi;
+ unsigned int cfg_ddr_zqreset;
+ unsigned int cfg_ddr_tdqsck_min;
+ unsigned int cfg_ddr_tdqsck_max;
+ //training_delay_set_ps_t cfg_ddr_training_delay_ps;
+ ddr_mrs_reg_t cfg_ddr_mrs_reg_ps[2];
+ unsigned int dfi_odt1_config_ps[2];
+ //ddr_mrs_reg_t cfg_ddr_mrs_reg_ps1;
+ #if 0
+ unsigned int cfg_ddr_mr[8];
+ unsigned int cfg_ddr_mr11;
+ unsigned int cfg_ddr_mr12;
+ unsigned int cfg_ddr_mr13;
+ unsigned int cfg_ddr_mr14;
+ unsigned int cfg_ddr_mr16;
+ unsigned int cfg_ddr_mr17;
+ unsigned int cfg_ddr_mr22;
+ unsigned int cfg_ddr_mr24;
+ unsigned int cfg_ddr_reserve[5];
+ #endif
+}__attribute__ ((packed)) ddr_timing_t;
+
+typedef struct ddr_phy_common_extra_set{
+ unsigned short csr_pllctrl3;
+ unsigned short csr_pptctlstatic[4];
+ unsigned short csr_trainingincdecdtsmen[4];
+ unsigned short csr_tsmbyte0[4];
+ unsigned short csr_hwtcamode;
+ unsigned short csr_hwtlpcsena;
+ unsigned short csr_hwtlpcsenb;
+ unsigned short csr_acsmctrl13;
+ unsigned short csr_acsmctrl23;
+ unsigned char csr_soc_vref_dac1_dfe[36];
+}__attribute__ ((packed)) ddr_phy_common_extra_set_t;
+
+typedef struct retraining_set{
+ ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t;
+ training_delay_set_ps_t cfg_ddr_training_delay_ps;
+}__attribute__ ((packed)) retraining_set_t;
+
+typedef struct ddr_set{
+ unsigned int magic;
+ unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test
+ //unsigned int rsv_int0;
+ unsigned int ddr_func;
+ unsigned char board_id;
+ //board id reserve,,do not modify
+ unsigned char version;
+ // firmware reserve version,,do not modify
+ unsigned char DramType;
+ //support DramType should confirm with amlogic
+ //#define CONFIG_DDR_TYPE_DDR3 0
+ //#define CONFIG_DDR_TYPE_DDR4 1
+ //#define CONFIG_DDR_TYPE_LPDDR4 2
+ //#define CONFIG_DDR_TYPE_LPDDR3 3
+ //#define CONFIG_DDR_TYPE_LPDDR2 4
+ unsigned char DisabledDbyte;
+ //use for dram bus 16bit or 32bit,if use 16bit mode ,should disable bit 2,3
+ //bit 0 ---use byte 0 ,1 disable byte 0,
+ //bit 1 ---use byte 1 ,1 disable byte 1,
+ //bit 2 ---use byte 2 ,1 disable byte 2,
+ //bit 3 ---use byte 3 ,1 disable byte 3,
+ unsigned char Is2Ttiming;
+ //ddr3/ddr3 use 2t timing,now only support 2t timming
+ unsigned char HdtCtrl;
+ //training information control,do not modify
+ unsigned char dram_rank_config;
+ //support Dram connection type should confirm with amlogic
+ //#define CONFIG_DDR0_16BIT_CH0 0x1 //dram total bus width 16bit only use cs0
+ //#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 //dram total bus width 16bit use cs0 cs1
+ //#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 //dram total bus width 32bit use cs0
+ //#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 //only for lpddr4,dram total bus width 32bit use chanel a cs0 cs1 chanel b cs0 cs1
+ //#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 //dram total bus width 32bit only use cs0,but high address use 16bit mode
+ //#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 //dram total bus width 32bit use cs0 cs1,but cs1 use 16bit mode ,current phy not support reserve
+ //#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7 //dram total bus width 32bit use cs0 cs1
+ //#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8 //only for lpddr4,dram total bus width 32bit use chanel a cs0 chanel b cs0
+
+ /* rsv_char0. update for diagnose type define */
+ unsigned char diagnose;
+
+ unsigned short soc_data_drv_ohm_ps1;
+ unsigned short dram_data_drv_ohm_ps1;
+ unsigned short soc_data_odt_ohm_ps1;
+ unsigned short dram_data_odt_ohm_ps1;
+ unsigned short dram_data_wr_odt_ohm_ps1;
+ #if 0
+ /* imem/dmem define */
+ unsigned int imem_load_addr;
+ //system reserve,do not modify
+ unsigned int dmem_load_addr;
+ //system reserve,do not modify
+ unsigned short imem_load_size;
+ #endif
+ //system reserve,do not modify
+ unsigned short dmem_load_size;
+ //system reserve,do not modify
+ unsigned int ddr_base_addr;
+ //system reserve,do not modify
+ unsigned int ddr_start_offset;
+ //system reserve,do not modify
+
+ unsigned short dram_cs0_size_MB;
+ //config cs0 dram size ,like 1G DRAM ,setting 1024
+ unsigned short dram_cs1_size_MB;
+ //config cs1 dram size,like 512M DRAM ,setting 512
+ /* align8 */
+
+ unsigned short training_SequenceCtrl[2];
+ //system reserve,do not modify
+ unsigned char phy_odt_config_rank[2];
+ //unsigned char rever1;
+ //unsigned char rever2;
+ unsigned short rank1_ca_vref_permil;
+ //training odt config ,only use for training
+ // [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ // [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ unsigned int dfi_odt_config;
+ //normal go status od config,use for normal status
+ //bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity.
+ //bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1.
+ //bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0.
+ //bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1.
+ //bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0.
+ //bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity.
+ //bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0.
+ //bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1.
+ //bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0.
+ //bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1.
+ unsigned short DRAMFreq[4];
+ //config dram frequency,use DRAMFreq[0],ohter reserve
+ unsigned char PllBypassEn;
+ //system reserve,do not modify
+ unsigned char ddr_rdbi_wr_enable;
+ //system reserve,do not modify
+ unsigned char ddr_rfc_type;
+ //config dram rfc type,according dram type,also can use same dram type max config
+ //#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+ //#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+ //#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+ //#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+ //#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+ //#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+ //#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+ //#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+ //#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+ //#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+ //#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+ //#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+ unsigned char enable_lpddr4x_mode;
+ //system reserve,do not modify
+ /* align8 */
+
+ unsigned int pll_ssc_mode;
+ //
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ unsigned short clk_drv_ohm;
+ //config soc clk pin signal driver stength ,select 20,30,40,60ohm
+ unsigned short cs_drv_ohm;
+ //config soc cs0 cs1 pin signal driver stength ,select 20,30,40,60ohm
+ unsigned short ac_drv_ohm;
+ //config soc normal address command pin driver stength ,select 20,30,40,60ohm
+ unsigned short soc_data_drv_ohm_p;
+ //config soc data pin pull up driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short soc_data_drv_ohm_n;
+ //config soc data pin pull down driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short soc_data_odt_ohm_p;
+ //config soc data pin odt pull up stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short soc_data_odt_ohm_n;
+ //config soc data pin odt pull down stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short dram_data_drv_ohm;
+ //config dram data pin pull up pull down driver stength,ddr3 select 34,40ohm,ddr4 select 34,48ohm,lpddr4 select 40,48,60,80,120,240ohm
+ unsigned short dram_data_odt_ohm;
+ //config dram data pin odt pull up down stength,ddr3 select 40,60,120ohm,ddr4 select 34,40,48,60,120,240ohm,lpddr4 select 40,48,60,80,120,240ohm
+ unsigned short dram_ac_odt_ohm;
+ //config dram ac pin odt pull up down stength,use for lpddr4, select 40,48,60,80,120,240ohm
+ unsigned short soc_clk_slew_rate;
+ //system reserve,do not modify
+ unsigned short soc_cs_slew_rate;
+ //system reserve,do not modify
+ unsigned short soc_ac_slew_rate;
+ //system reserve,do not modify
+ unsigned short soc_data_slew_rate;
+ //system reserve,do not modify
+ unsigned short vref_output_permil; //phy
+ //setting same with vref_dram_permil
+ unsigned short vref_receiver_permil; //soc
+ //soc init SOC receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
+ unsigned short vref_dram_permil;
+ //soc init DRAM receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
+ unsigned short max_core_timmming_frequency;
+ //use for limited ddr speed core timmming parameter,for some old dram maybe have no over speed register
+ /* align8 */
+
+ unsigned char ac_trace_delay[10];
+ unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting;
+ //use for lpddr4 read vout voltage setting 0 --->2/5VDDQ ,1--->1/3VDDQ
+ unsigned char lpddr4_x8_mode;
+ unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function
+ //[1],slt test parameter ,use for force delay line offset
+ //system reserve,do not modify
+ unsigned short tdqs2dq;
+ unsigned char dram_data_wr_odt_ohm;
+ unsigned char bitTimeControl_2d;
+ //system reserve,do not modify
+ /* align8 */
+ unsigned char char_rev1;
+ unsigned char training_offset;//char_rev2;
+ unsigned int ddr_dmc_remap[5];
+ unsigned int dram_rtt_nom_wr_park[2];
+ //system reserve,do not modify
+ /* align8 */
+ unsigned char ddr_lpddr34_ca_remap[4];
+ ////use for lpddr3 /lpddr4 ca training data byte lane remap
+ unsigned char ddr_lpddr34_dq_remap[32];
+ ////use for lpddr3 /lpddr4 ca pinmux remap
+ unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL];
+ //use for lpddr3 /lpddr4 ca pinmux remap
+ unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL];
+ unsigned char char_rev3;
+ unsigned char char_rev4;
+ ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t;
+ training_delay_set_ps_t cfg_ddr_training_delay_ps[2];
+
+ //override read bit delay
+}__attribute__ ((packed)) ddr_set_t;
+
+typedef struct psram_set {
+ unsigned int magic;
+ unsigned int board_id;
+ /* align8 */
+ unsigned int version;
+ unsigned char psram_mr[12];
+ /* align8 */
+ unsigned char psram_board_mask;
+ unsigned char psram_amlogic_protocol_id;
+ unsigned char psram_test_function[2];
+ unsigned char psram_vendor_id;
+ unsigned char psram_device_id;
+ unsigned char psram_soc_drv;
+ unsigned char psram_dram_drv;
+ /* align8 */
+ unsigned int psram_ac_timing0;
+ unsigned int psram_ac_timing1;
+ unsigned int psram_ac_timing2;
+ unsigned int psram_mode_crtl;
+ /* align8 */
+ unsigned short psram_frequency;
+ unsigned short psram_size;
+ unsigned int psram_mode_crtl_bl33;
+ unsigned int psram_pin_crtl;
+ unsigned int psram_lcd_ctrl;
+ /* align8 */
+ unsigned char psram_pin_dq_in_delay[8];
+ unsigned char psram_pin_dq_out_delay[8];
+ unsigned char psram_pin_dq_out_oe_delay[8];
+ /* align8 */
+ unsigned char psram_pin_dm_out_delay;
+ unsigned char psram_pin_dm_out_oe_delay;
+ unsigned char psram_pin_cs_out_delay;
+ unsigned char psram_pin_dqsp_in_delay;
+ unsigned char psram_pin_dqsn_in_delay;
+ unsigned char psram_pin_ckp_out_delay;
+ unsigned char psram_pin_ckn_out_delay;
+ /* align8 */
+ unsigned char psram_pin_rden_delay;
+ unsigned char psram_bdlr_delay;
+ unsigned char psram_reserve[6];
+
+ /* pls check alignment of each variable */
+}__attribute__ ((packed)) psram_set_t;
+
+typedef struct psram_bl2_set{
+ uint16_t psram_mr[12];
+ uint32_t psram_ac_timing0;
+ uint32_t psram_ac_timing1;
+ uint32_t psram_ac_timing2;
+ uint32_t psram_mode_crtl;
+ uint32_t psram_cur_clk_frequeny;
+ char psram_cur_amlogic_protocol_id;
+ char psram_use_hifi_pll;
+ char psram_fixed_latency_enable;
+ char psram_initial_latency;
+ char psram_cmd_cycle;
+ char psram_enable_data_mask;
+ char psram_user_cmd_code_read_register;
+ char psram_user_cmd_code_write_register;
+ char psram_user_cmd_code_read_memory;
+ char psram_user_cmd_code_write_memory;
+ uint32_t axi_req_ctrl0;
+ uint32_t axi_req_ctrl1;
+ uint32_t axi_req_ctrl2;
+ uint32_t user_ctrl0;
+ uint32_t user_ctrl1;
+ uint32_t user_ctrl2;
+ uint32_t user_ctrl3;
+ uint32_t psram_ctrl;
+}psram_bl2_set_t;
+
+typedef struct psram_bl33_set{
+ char psram_board_mask;
+ char psram_amlogic_protocol_id;
+ char psram_test_function[2];
+ char psram_vendor_id;
+ char psram_device_id;
+ uint16_t psram_frequency;
+ uint16_t psram_dram_size;
+ char psram_soc_drv;
+ char psram_dram_drv;
+ uint32_t psram_mode_crtl_bl33;
+ uint32_t psram_pin_crtl;
+ uint32_t psram_lcd_ctrl;
+ char psram_pin_dq_in_delay[8];
+ char psram_pin_dq_out_delay[8];
+ char psram_pin_dq_out_oe_delay[8];
+ char psram_pin_dm_out_delay;
+ char psram_pin_dm_out_oe_delay;
+ char psram_pin_cs_out_delay;
+ char psram_pin_dqsp_in_delay;
+ char psram_pin_dqsn_in_delay;
+ char psram_pin_ckp_out_delay;
+ char psram_pin_ckn_out_delay;
+ char psram_pin_rden_delay;
+ char psram_bdlr_delay;
+ char psram_reserver[7];
+}psram_psram_dev_t;
+
+typedef struct pll_set{
+ unsigned short cpu_clk;
+ unsigned short pxp;
+ unsigned int spi_ctrl;
+ unsigned short vddee;
+ unsigned short vcck;
+ unsigned char szPad[4];
+
+ unsigned long lCustomerID;
+ unsigned char debug_mode;
+ unsigned char log_chl;
+ unsigned char log_ctrl;
+ unsigned char ddr_timming_save_mode;
+ unsigned int nCFGTAddr;
+ /* align 8Byte */
+
+ unsigned int sys_pll_cntl[8];
+ unsigned int ddr_pll_cntl[8];
+ unsigned int fix_pll_cntl[8];
+}__attribute__ ((packed)) pll_set_t;
+
+typedef struct dmem_cfg {
+ PMU_SMB_DDR3U_1D_t ddr3u;
+ PMU_SMB_DDR4U_1D_t ddr4u;
+ PMU_SMB_DDR4U_2D_t ddr4u_2d;
+ PMU_SMB_LPDDR3_1D_t lpddr3u;
+ PMU_SMB_LPDDR4_1D_t lpddr4u;
+ PMU_SMB_LPDDR4_2D_t lpddr4u_2d;
+} dmem_cfg_t;
+
+#endif //__AML_TIMING_H_
diff --git a/arch/arm/include/asm/arch-a1/tsensor.h b/arch/arm/include/asm/arch-a1/tsensor.h
new file mode 100644
index 0000000..cce98d6
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/tsensor.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __TSENSOR_H__
+#define __TSENSOR_H__
+
+
+struct tsensor_cali_data {
+ unsigned int cmd; /* R/W */
+ unsigned int offset;
+ unsigned int size;
+ unsigned long buffer_phy;
+ unsigned long retcnt_phy;
+};
+
+
+#define CONFIG_HIGH_TEMP_COOL 90
+
+#define T_AVG_NUM 16 /*trim temp cnt*/
+#define T_READ_NUM 2 /*trim temp cnt*/
+#define T_VER_MASK 0x80
+#define T_VALUE_MIN 0x1500
+#define T_VALUE_MAX 0x3500
+#define T_DLY_TIME 4500 /*update sensor register need 4.2ms*/
+
+#define T_CONTROL_DATA 0x62b
+#define T_TSCLK_DATA 0x130
+
+#define ts_b 3159
+#define ts_a 9411
+#define ts_m 424
+#define ts_n 324
+
+#ifdef CONFIG_AML_TSENSOR
+int temp_read_entry(void);
+int temp_trim_entry(int tempbase, int tempver);
+int temp_cooling_entry(void);
+#else
+int temp_read_entry(void)
+{
+ return -1;
+}
+int temp_trim_entry(int tempbase, int tempver)
+{
+ return -1;
+}
+int temp_cooling_entry(void)
+{
+ return 0;
+}
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-a1/types.h b/arch/arm/include/asm/arch-a1/types.h
new file mode 100644
index 0000000..2d362b1
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/types.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __TYPES_H
+#define __TYPES_H
+
+#ifndef _INT8_T_DECLARED
+typedef char int8_t;
+#define _INT8_T_DECLARED
+#endif
+
+#ifndef _INT16_T_DECLARED
+typedef short int16_t;
+#define _INT16_T_DECLARED
+#endif
+
+#ifndef _INT32_T_DECLARED
+typedef int int32_t;
+#define _INT32_T_DECLARED
+#endif
+
+#ifndef _INT64_T_DECLARED
+typedef long int64_t;
+#define _INT64_T_DECLARED
+#endif
+
+#ifndef _UINT8_T_DECLARED
+typedef unsigned char uint8_t;
+#define _UINT8_T_DECLARED
+#endif
+
+#ifndef _UINT16_T_DECLARED
+typedef unsigned short uint16_t;
+#define _UINT16_T_DECLARED
+#endif
+
+#ifndef _UINT32_T_DECLARED
+typedef unsigned int uint32_t;
+#define _UINT32_T_DECLARED
+#endif
+
+#ifndef _UINT64_T_DECLARED
+typedef unsigned long uint64_t;
+#define _UINT64_T_DECLARED
+#endif
+
+#ifndef _INT8PTR_T_DECLARED
+typedef char * int8ptr_t;
+#define _INT8PTR_T_DECLARED
+#endif
+
+#ifndef _INT16PTR_T_DECLARED
+typedef short * int16ptr_t;
+#define _INT16PTR_T_DECLARED
+#endif
+
+#ifndef _INT32PTR_T_DECLARED
+typedef int * int32ptr_t;
+#define _INT32PTR_T_DECLARED
+#endif
+
+#ifndef _INT64PTR_T_DECLARED
+typedef long * int64ptr_t;
+#define _INT64PTR_T_DECLARED
+#endif
+
+#ifndef _UINT8PTR_T_DECLARED
+typedef unsigned char * uint8ptr_t;
+#define _UINT8PTR_T_DECLARED
+#endif
+
+#ifndef _UINT16PTR_T_DECLARED
+typedef unsigned short * uint16ptr_t;
+#define _UINT16PTR_T_DECLARED
+#endif
+
+#ifndef _UINT32PTR_T_DECLARED
+typedef unsigned int * uint32ptr_t;
+#define _UINT32PTR_T_DECLARED
+#endif
+
+#ifndef _UINT64PTR_T_DECLARED
+typedef unsigned long * uint64ptr_t;
+#define _UINT64PTR_T_DECLARED
+#endif
+
+#endif
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-a1/uart.h b/arch/arm/include/asm/arch-a1/uart.h
new file mode 100644
index 0000000..757dc91
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/uart.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __MESON_FIRM_UART_H_
+#define __MESON_FIRM_UART_H_
+#include <config.h>
+#include <common.h>
+#include "register.h"
+//#include "io.h"
+#include <asm/arch/secure_apb.h>
+
+#ifndef CONFIG_CONS_INDEX
+#error Please define CONFIG_CONS_INDEX==[0|1]
+#endif
+
+#if CONFIG_CONS_INDEX==0
+#define UART_PORT_CONS UART_PORT_0
+#elif CONFIG_CONS_INDEX==1
+#define UART_PORT_CONS UART_PORT_1
+#elif CONFIG_CONS_INDEX==2
+#define UART_PORT_CONS UART_PORT_AO
+#define USE_AO_UART 1
+#else
+#error Please define CONFIG_CONS_INDEX==[0|1]
+#endif
+/*
+#define UART_PORT_0 CBUS_REG_ADDR(UART0_WFIFO)
+#define UART_PORT_1 CBUS_REG_ADDR(UART1_WFIFO)
+#define UART_PORT_2 CBUS_REG_ADDR(UART2_WFIFO)
+#define UART_PORT_AO P_AO_UART_WFIFO
+
+#define UART_WFIFO (0<<2)
+#define UART_RFIFO (1<<2)
+#define UART_CONTROL (2<<2)
+#define UART_STATUS (3<<2)
+#define UART_MISC (4<<2)
+*/
+
+#include "clock.h"
+
+#define UART_CLK_SRC CLK81
+#define UART_PORT_0 0xfe001c00
+#define UART_PORT_1 0xfe001c00
+#define UART_PORT_AO 0xfe001c00
+#define UART_WFIFO 0
+#define UART_RFIFO 1
+#define UART_CONTROL 2
+#define UART_STATUS 3
+#define UART_MISC 4
+
+#if USE_AO_UART == 1
+#define P_UART(uart_base,reg) (uart_base + (reg<<2))
+#else
+#define P_UART(uart_base,reg) CBUS_REG_ADDR(uart_base+reg)
+#endif
+#define P_UART_WFIFO(uart_base) P_UART(uart_base,UART_WFIFO)
+#define P_UART_RFIFO(uart_base) P_UART(uart_base,UART_RFIFO)
+
+#define P_UART_CONTROL(uart_base) P_UART(uart_base,UART_CONTROL)
+ #define UART_CNTL_MASK_BAUD_RATE (0xfff)
+ #define UART_CNTL_MASK_TX_EN (1<<12)
+ #define UART_CNTL_MASK_RX_EN (1<<13)
+ #define UART_CNTL_MASK_2WIRE (1<<15)
+ #define UART_CNTL_MASK_STP_BITS (3<<16)
+ #define UART_CNTL_MASK_STP_1BIT (0<<16)
+ #define UART_CNTL_MASK_STP_2BIT (1<<16)
+ #define UART_CNTL_MASK_PRTY_EVEN (0<<18)
+ #define UART_CNTL_MASK_PRTY_ODD (1<<18)
+ #define UART_CNTL_MASK_PRTY_TYPE (1<<18)
+ #define UART_CNTL_MASK_PRTY_EN (1<<19)
+ #define UART_CNTL_MASK_CHAR_LEN (3<<20)
+ #define UART_CNTL_MASK_CHAR_8BIT (0<<20)
+ #define UART_CNTL_MASK_CHAR_7BIT (1<<20)
+ #define UART_CNTL_MASK_CHAR_6BIT (2<<20)
+ #define UART_CNTL_MASK_CHAR_5BIT (3<<20)
+ #define UART_CNTL_MASK_RST_TX (1<<22)
+ #define UART_CNTL_MASK_RST_RX (1<<23)
+ #define UART_CNTL_MASK_CLR_ERR (1<<24)
+ #define UART_CNTL_MASK_INV_RX (1<<25)
+ #define UART_CNTL_MASK_INV_TX (1<<26)
+ #define UART_CNTL_MASK_RINT_EN (1<<27)
+ #define UART_CNTL_MASK_TINT_EN (1<<28)
+ #define UART_CNTL_MASK_INV_CTS (1<<29)
+ #define UART_CNTL_MASK_MASK_ERR (1<<30)
+ #define UART_CNTL_MASK_INV_RTS (1<<31)
+#define P_UART_STATUS(uart_base) P_UART(uart_base,UART_STATUS )
+ #define UART_STAT_MASK_RFIFO_CNT (0x7f<<0)
+ #define UART_STAT_MASK_TFIFO_CNT (0x7f<<8)
+ #define UART_STAT_MASK_PRTY_ERR (1<<16)
+ #define UART_STAT_MASK_FRAM_ERR (1<<17)
+ #define UART_STAT_MASK_WFULL_ERR (1<<18)
+ #define UART_STAT_MASK_RFIFO_FULL (1<<19)
+ #define UART_STAT_MASK_RFIFO_EMPTY (1<<20)
+ #define UART_STAT_MASK_TFIFO_FULL (1<<21)
+ #define UART_STAT_MASK_TFIFO_EMPTY (1<<22)
+ #define UART_STAT_MASK_XMIT_BUSY (1<<25)
+ #define UART_STAT_MASK_RECV_BUSY (1<<26)
+#define P_UART_MISC(uart_base) P_UART(uart_base,UART_MISC )
+
+
+#ifndef CONFIG_SERIAL_STP_BITS
+#define CONFIG_SERIAL_STP_BITS 1 // 1 , 2
+#endif
+#if CONFIG_SERIAL_STP_BITS==1
+#define UART_STP_BIT UART_CNTL_MASK_STP_1BIT
+#elif CONFIG_SERIAL_STP_BITS==2
+#define UART_STP_BIT UART_CNTL_MASK_STP_2BIT
+#else
+#error CONFIG_SERIAL_STP_BITS wrong
+#endif
+
+
+#ifndef CONFIG_SERIAL_PRTY_TYPE
+#define CONFIG_SERIAL_PRTY_TYPE 0 //0 ,2 ,3
+#endif
+#if CONFIG_SERIAL_PRTY_TYPE==0
+#define UART_PRTY_BIT 0
+#elif CONFIG_SERIAL_PRTY_TYPE==2
+#define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_EVEN)
+#elif CONFIG_SERIAL_PRTY_TYPE==3
+#define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_ODD)
+#else
+#error CONFIG_SERIAL_PRTY_TYPE wrong
+#endif
+
+#ifndef CONFIG_SERIAL_CHAR_LEN
+#define CONFIG_SERIAL_CHAR_LEN 8 //5,6,7,8
+#endif
+#if CONFIG_SERIAL_CHAR_LEN==5
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_5BIT
+#elif CONFIG_SERIAL_CHAR_LEN==6
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_6BIT
+#elif CONFIG_SERIAL_CHAR_LEN==7
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_7BIT
+#elif CONFIG_SERIAL_CHAR_LEN==8
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_8BIT
+#else
+#error CONFIG_SERIAL_CHAR_LEN wrong
+#endif
+#define UART_CONTROL_SET(baud,clk81) \
+ (((clk81)/(baud*4) -1) \
+ | UART_STP_BIT \
+ | UART_PRTY_BIT \
+ | UART_CHAR_LEN \
+ | UART_CNTL_MASK_TX_EN \
+ | UART_CNTL_MASK_RX_EN \
+ | UART_CNTL_MASK_RST_TX \
+ | UART_CNTL_MASK_RST_RX \
+ | UART_CNTL_MASK_CLR_ERR )
+#endif
diff --git a/arch/arm/include/asm/arch-a1/usb.h b/arch/arm/include/asm/arch-a1/usb.h
new file mode 100644
index 0000000..0efea92
--- /dev/null
+++ b/arch/arm/include/asm/arch-a1/usb.h
@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __ARCH_ARM_MESON_USB_H_U_BOOT__
+#define __ARCH_ARM_MESON_USB_H_U_BOOT__
+
+#include <common.h>
+#include <asm/types.h>
+#include <asm/arch/io.h>
+#include <asm/arch/secure_apb.h>
+#include <generic-phy.h>
+#include <asm-generic/gpio.h>
+
+#define USB_PHY_PORT_MAX 1
+/* Phy register MACRO definitions */
+
+#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
+#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
+#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27)
+
+#define PHYUTMI_OTGDISABLE (1 << 6)
+#define PHYUTMI_FORCESUSPEND (1 << 1)
+#define PHYUTMI_FORCESLEEP (1 << 0)
+
+#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
+#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
+
+#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
+#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
+
+#define PHYCLKRST_SSC_EN (0x1 << 20)
+#define PHYCLKRST_REF_SSP_EN (0x1 << 19)
+#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18)
+
+#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
+
+#define PHYCLKRST_FSEL_MASK (0x3f << 5)
+#define PHYCLKRST_FSEL(_x) ((_x) << 5)
+#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
+#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
+#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
+#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
+
+#define PHYCLKRST_RETENABLEN (0x1 << 4)
+
+#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
+#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
+#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
+
+#define PHYCLKRST_PORTRESET (0x1 << 1)
+#define PHYCLKRST_COMMONONN (0x1 << 0)
+
+#define PHYPARAM0_REF_USE_PAD (0x1 << 31)
+#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
+#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
+
+#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
+#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
+
+#define PHYTEST_POWERDOWN_SSP (0x1 << 3)
+#define PHYTEST_POWERDOWN_HSP (0x1 << 2)
+
+#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2)
+
+#define FSEL_CLKSEL_24M (0x5)
+
+#define USB_PHY2_ENABLE 0x10000000
+#define USB_PHY2_RESET 0x20000000
+
+/* XHCI PHY register structure */
+#define PHY_REGISTER_SIZE 0x20
+
+struct phy_aml_usb2_priv {
+ unsigned int base_addr;
+ unsigned int reset_addr;
+ unsigned int dwc2_a_addr;
+ unsigned int u2_port_num;
+ unsigned int usbphy_reset_bit[8];
+ unsigned int clktree_usb_bus_ctrl_addr;
+ unsigned int usb_phy2_pll_base_addr[4];
+};
+
+struct phy_aml_usb3_priv {
+ unsigned int base_addr;
+ unsigned int usb3_port_num;
+ struct gpio_desc desc;
+};
+
+/* Register definitions */
+typedef struct u2p_aml_regs {
+ volatile uint32_t u2p_r0;
+ volatile uint32_t u2p_r1;
+} u2p_aml_regs_t;
+
+typedef union u2p_r0 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned host_device:1;
+ unsigned power_ok:1;
+ unsigned hast_mode:1;
+ unsigned POR:1;
+ unsigned IDPULLUP0:1;
+ unsigned DRVVBUS0:1;
+ unsigned reserved:26;
+ } b;
+} u2p_r0_t;
+
+typedef union u2p_r1 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned phy_rdy:1;
+ unsigned IDDIG0:1;
+ unsigned OTGSESSVLD0:1;
+ unsigned VBUSVALID0:1;
+ unsigned reserved:28;
+ } b;
+} u2p_r1_t;
+
+
+typedef struct usb_aml_regs {
+ volatile uint32_t usb_r0;
+ volatile uint32_t usb_r1;
+ volatile uint32_t usb_r2;
+ volatile uint32_t usb_r3;
+ volatile uint32_t usb_r4;
+ volatile uint32_t usb_r5;
+} usb_aml_regs_t;
+
+typedef union usb_r0 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned reserved:17;
+ unsigned p30_lane0_tx2rx_loopback:1;
+ unsigned p30_lane0_ext_pclk_reg:1;
+ unsigned p30_pcs_rx_los_mask_val:10;
+ unsigned u2d_ss_scaledown_mode:2;
+ unsigned u2d_act:1;
+ } b;
+} usb_r0_t;
+
+typedef union usb_r1 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned u3h_bigendian_gs:1;
+ unsigned u3h_pme_en:1;
+ unsigned u3h_hub_port_overcurrent:3;
+ unsigned reserved_1:2;
+ unsigned u3h_hub_port_perm_attach:3;
+ unsigned reserved_2:2;
+ unsigned u3h_host_u2_port_disable:2;
+ unsigned reserved_3:2;
+ unsigned u3h_host_u3_port_disable:1;
+ unsigned u3h_host_port_power_control_present:1;
+ unsigned u3h_host_msi_enable:1;
+ unsigned u3h_fladj_30mhz_reg:6;
+ unsigned p30_pcs_tx_swing_full:7;
+ } b;
+} usb_r1_t;
+
+typedef union usb_r2 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned reserved:20;
+ unsigned p30_pcs_tx_deemph_3p5db:6;
+ unsigned p30_pcs_tx_deemph_6db:6;
+ } b;
+} usb_r2_t;
+
+typedef union usb_r3 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned p30_ssc_en:1;
+ unsigned p30_ssc_range:3;
+ unsigned p30_ssc_ref_clk_sel:9;
+ unsigned p30_ref_ssp_en:1;
+ unsigned reserved:18;
+ } b;
+} usb_r3_t;
+
+typedef union usb_r4 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned p21_PORTRESET0:1;
+ unsigned p21_SLEEPM0:1;
+ unsigned mem_pd:2;
+ unsigned p21_only:1;
+ unsigned reserved:27;
+ } b;
+} usb_r4_t;
+
+typedef union usb_r5 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned iddig_sync:1;
+ unsigned iddig_reg:1;
+ unsigned iddig_cfg:2;
+ unsigned iddig_en0:1;
+ unsigned iddig_en1:1;
+ unsigned iddig_curr:1;
+ unsigned usb_iddig_irq:1;
+ unsigned iddig_th:8;
+ unsigned iddig_cnt:8;
+ unsigned reserved:8;
+ } b;
+} usb_r5_t;
+
+/* usb id mode, only after M2
+ mode = 0 : HARDWARE
+ mode = 1 : SW_HOST
+ mode = 2 : SW_DEVICE
+ */
+#define USB_ID_MODE_HARDWARE (1)
+#define USB_ID_MODE_SW_HOST (2)
+#define USB_ID_MODE_SW_DEVICE (3)
+int usb2_phy_tuning(uint32_t phy2_pll_base, int port);
+void set_usb_pll(uint32_t phy2_pll_base);
+int usb_save_phy_dev (unsigned int number, struct phy *phy);
+int usb2_phy_init (struct phy *phy);
+unsigned int usb_get_dwc_a_base_addr(void);
+unsigned int usb_get_device_mode_phy_base(void);
+void usb_phy_tuning_reset(void);
+void usb_device_mode_init(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-c1/acs.h b/arch/arm/include/asm/arch-c1/acs.h
new file mode 100644
index 0000000..65de6df
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/acs.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __ACS_H
+#define __ACS_H
+
+#ifndef __ASSEMBLY__
+typedef struct acs_setting{
+ char acs_magic[5]; //acs setting magic word, make sure this piece of data was right.
+ unsigned char chip_type; //chip type
+ unsigned short version; //version of acs_setting struct, for PC tool use.
+ unsigned long acs_set_length; //length of current struct.
+
+ //ddr setting part, 16 bytes
+ char ddr_magic[5]; //magic word to indicate that following 12 bytes was ddr setting.
+ unsigned char ddr_set_version; //struct version, for PC tool use.
+ unsigned short ddr_set_length; //length of ddr struct.
+ unsigned long ddr_set_addr; //address of ddr setting.
+
+ char ddr_reg_magic[5];
+ unsigned char ddr_reg_version;
+ unsigned short ddr_reg_length;
+ unsigned long ddr_reg_addr;
+
+ char pll_magic[5];
+ unsigned char pll_set_version;
+ unsigned short pll_set_length;
+ unsigned long pll_set_addr;
+
+ char sto_magic[5];
+ unsigned char sto_set_version;
+ unsigned short sto_set_length;
+ unsigned long sto_set_addr;
+
+ char bl2_regs_magic[5];
+ unsigned char bl2_regs_version;
+ unsigned short bl2_regs_length;
+ unsigned long bl2_regs_addr;
+
+ char rsv_magic[5];
+ unsigned char rsv_set_version;
+ unsigned short rsv_set_length;
+ unsigned long rsv_set_addr;
+ char board_id[12];
+ unsigned short ddr_struct_size[12];
+ unsigned long ddr_struct_org_size;
+ char revision[40];
+}__attribute__ ((packed)) acs_set_t;
+
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-c1/bl31_apis.h b/arch/arm/include/asm/arch-c1/bl31_apis.h
new file mode 100644
index 0000000..a0c78a5
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/bl31_apis.h
@@ -0,0 +1,164 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ * Trustzone API
+ *
+ * Copyright (C) 2012 Amlogic, Inc.
+ *
+ * Author: Platform-SH@amlogic.com
+ *
+ */
+
+#ifndef __GXBB_BL31_APIS_H
+#define __GXBB_BL31_APIS_H
+
+#include <asm/arch/io.h>
+
+/*#define SRAM_READ 0x82000010
+#define CORE_RD_REV1 0x82000011
+#define SRAM_ACS_READ 0x82000012
+#define SRAM_ACS_INDIRECT_READ 0x82000013*/
+
+#define GET_SHARE_MEM_INPUT_BASE 0x82000020
+#define GET_SHARE_MEM_OUTPUT_BASE 0x82000021
+#define GET_REBOOT_REASON 0x82000022
+#define GET_SHARE_STORAGE_IN_BASE 0x82000023
+#define GET_SHARE_STORAGE_OUT_BASE 0x82000024
+#define GET_SHARE_STORAGE_BLOCK_BASE 0x82000025
+#define GET_SHARE_STORAGE_MESSAGE_BASE 0x82000026
+#define GET_SHARE_STORAGE_BLOCK_SIZE 0x82000027
+#define SET_STORAGE_INFO 0x82000028
+#define SET_REBOOT_REASON 0x82000049
+
+/* Set Reboot Reason then Reboot*/
+#define PSCI_SYS_REBOOT 0x84000009
+
+/* SECUREOS DEFINITION*/
+/* SMC Identifiers for non-secure world functions */
+#define CALL_TRUSTZONE_HAL_API 0x5
+
+/* EFUSE */
+#define EFUSE_READ 0x82000030
+#define EFUSE_WRITE 0x82000031
+#define EFUSE_WRITE_PATTERN 0x82000032
+#define EFUSE_USER_MAX 0x82000033
+
+#define DEBUG_EFUSE_WRITE_PATTERN 0x820000F0
+#define DEBUG_EFUSE_READ_PATTERN 0x820000F1
+
+/* JTAG*/
+#define JTAG_ON 0x82000040
+#define JTAG_OFF 0x82000041
+
+#define SET_USB_BOOT_FUNC 0x82000043
+ /* USB BOOT FUNC sub command list*/
+ #define CLEAR_USB_BOOT 1
+ #define FORCE_USB_BOOT 2
+ #define RUN_COMD_USB_BOOT 3
+ #define PANIC_DUMP_USB_BOOT 4
+
+#define GET_CHIP_ID 0x82000044
+
+/* tsensor calibration data */
+#define TSENSOR_CALI_SET 0x8200004C
+
+/*oscring efuse value get */
+#define OSCRING_EFUSE_GET 0x8200004D
+/* Security Key*/
+#define SECURITY_KEY_QUERY 0x82000060
+#define SECURITY_KEY_READ 0x82000061
+#define SECURITY_KEY_WRITE 0x82000062
+#define SECURITY_KEY_TELL 0x82000063
+#define SECURITY_KEY_VERIFY 0x82000064
+#define SECURITY_KEY_STATUS 0x82000065
+#define SECURITY_KEY_NOTIFY 0x82000066
+#define SECURITY_KEY_LIST 0x82000067
+#define SECURITY_KEY_REMOVE 0x82000068
+#define SECURITY_KEY_NOTIFY_EX 0x82000069
+#define SECURITY_KEY_SET_ENCTYPE 0x8200006A
+#define SECURITY_KEY_GET_ENCTYPE 0x8200006B
+#define SECURITY_KEY_VERSION 0x8200006C
+
+/*viu probe en*/
+#define VIU_PREOBE_EN 0x82000080
+/*set boot first timeout*/
+#define SET_BOOT_FIRST 0x82000087
+
+/* KEYMASTER */
+#define SET_BOOT_PARAMS 0x82000072
+#define SHA256_DIGEST_SIZE 32
+typedef struct {
+ uint32_t device_locked;
+ uint32_t verified_boot_state;
+ uint8_t verified_boot_key[SHA256_DIGEST_SIZE];
+ uint8_t verified_boot_hash[SHA256_DIGEST_SIZE];
+} keymaster_boot_params;
+
+/* Secure HAL APIs */
+#define TRUSTZONE_HAL_API_SRAM 0x400
+
+/*start hifi4 */
+#define START_HIFI4 0x82000090
+#define DSP_SEC_POWERSET 0x82000092
+
+
+#define SRAM_HAL_API_CHECK_EFUSE 0x403
+struct sram_hal_api_arg {
+ unsigned int cmd;
+ unsigned int req_len;
+ unsigned int res_len;
+ unsigned long req_phy_addr;
+ unsigned long res_phy_addr;
+ unsigned long ret_phy_addr;
+};
+
+#define JTAG_STATE_ON 0
+#define JTAG_STATE_OFF 1
+#define JTAG_M3_AO 0
+#define JTAG_M3_EE 1
+#define JTAG_A53_AO 2
+#define JTAG_A53_EE 3
+#define CLUSTER_BIT 2
+
+
+/////////////////////////////////////////////////////////////////////////////////
+#define AML_DATA_PROCESS (0x820000FF)
+ #define AML_D_P_W_EFUSE_SECURE_BOOT (0x10)
+ #define AML_D_P_W_EFUSE_PASSWORD (0x11)
+ #define AML_D_P_W_EFUSE_CUSTOMER_ID (0x12)
+ #define AML_D_P_W_EFUSE_AMLOGIC (0x20)
+ #define AML_D_P_IMG_DECRYPT (0x40)
+ #define AML_D_P_UPGRADE_CHECK (0x80)
+
+#define GXB_EFUSE_PATTERN_SIZE (0x500)
+#define GXB_IMG_SIZE (24<<20)
+#define GXB_IMG_LOAD_ADDR (0x1080000)
+ #define GXB_IMG_DEC_KNL (1<<0)
+ #define GXB_IMG_DEC_RMD (1<<1)
+ #define GXB_IMG_DEC_DTB (1<<2)
+ #define GXB_IMG_DEC_ALL (GXB_IMG_DEC_KNL|GXB_IMG_DEC_RMD|GXB_IMG_DEC_DTB)
+
+#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+void aml_set_jtag_state(unsigned state, unsigned select);
+unsigned aml_get_reboot_reason(void);
+unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2);
+void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2);
+unsigned long aml_sec_boot_check(unsigned long ,unsigned long ,unsigned long,unsigned long );
+long get_sharemem_info(unsigned long);
+void set_usb_boot_function(unsigned long command);
+void aml_system_off(void);
+
+void bl31_get_chipid(unsigned int *, unsigned int *,
+ unsigned int *, unsigned int *);
+void set_viu_probe_enable(void);
+void wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value);
+void power_set_dsp(unsigned int id, unsigned int powerflag);
+void init_dsp(unsigned int id,unsigned int addr,unsigned int cfg0);
+void set_boot_first_timeout(uint64_t arg0);
+int bl31_get_cornerinfo(uint8_t *outbuf, int size);
+int32_t set_boot_params(const keymaster_boot_params*);
+#endif
diff --git a/arch/arm/include/asm/arch-c1/board_id.h b/arch/arm/include/asm/arch-c1/board_id.h
new file mode 100644
index 0000000..6488771
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/board_id.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+unsigned int get_board_id(void);
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-c1/clk_measure_tab.h b/arch/arm/include/asm/arch-c1/clk_measure_tab.h
new file mode 100644
index 0000000..7e9162c
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/clk_measure_tab.h
@@ -0,0 +1,96 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _ARCH_MESON_A1_MEASURE_H_
+#define _ARCH_MESON_A1_MEASURE_H_
+
+static const char* clk_msr_table[] = {
+ [0] = "tdmout_b_sclk",
+ [1] = "tdmout_a_sclk",
+ [2] = "tdmin_lb_sclk",
+ [3] = "tdmin_b_sclk",
+ [4] = "tdmin_a_sclk",
+ [5] = "vad_clk",
+ [6] = "resampleA_clk",
+ [7] = "pdm_sysclk",
+ [8] = "pdm_dclk",
+ [9] = "locker_out_clk",
+ [10] = "locker_in_clk",
+ [12] = "tdmin_vad_clk",
+ [13] = "au_adc_clk",
+ [14] = "au_dac_clk",
+ [16] = "spicc_a_clk",
+ [17] = "spifc_clk",
+ [18] = "sd_emmc_a_clk",
+ [19] = "spicc_b_clk",
+ [24] = "ts_clk",
+ [25] = "pwm_f_clk",
+ [26] = "pwm_e_clk",
+ [27] = "pwm_d_clk",
+ [28] = "pwm_c_clk",
+ [29] = "pwm_b_clk",
+ [30] = "pwm_a_clk",
+ [31] = "saradc_clk",
+ [32] = "usb_bus",
+ [33] = "dsp_b_clk",
+ [34] = "dsp_a_clk",
+ [35] = "axi_clk",
+ [36] = "sys_clk",
+ [39] = "gpio_msr",
+ [40] = "rng_ring_osc0",
+ [41] = "rng_ring_osc1",
+ [42] = "rng_ring_osc2",
+ [43] = "rng_ring_osc3",
+ [44] = "dds_out",
+ [45] = "cpu_clk_div16",
+ [46] = "osc_ring_cpu0",
+ [47] = "osc_ring_cpu1",
+ [48] = "osc_ring_cpu2",
+ [49] = "osc_ring_cpu3",
+ [50] = "osc_ring_ddr",
+ [51] = "osc_ring_dmc",
+ [52] = "osc_ring_dspa",
+ [53] = "osc_ring_dspb",
+ [54] = "osc_ring_rama",
+ [55] = "osc_ring_ramb",
+ [56] = "osc_ring_ramc",
+ [57] = "osc_ring_dos0",
+ [58] = "osc_ring_dos1",
+ [59] = "osc_ring_dos2",
+ [60] = "osc_ring_dos3",
+ [62] = "eth_mppll_50m",
+ [63] = "co_clkin_to_mac",
+ [64] = "eth_phy_plltxclk",
+ [65] = "eth_phy_rxclk",
+ [66] = "co_tx_clk",
+ [67] = "co_rx_clk",
+ [68] = "cts_mipi_isp_clk",
+ [69] = "cts_mipi_csi_phy_clk",
+ [70] = "cts_nna_axi_clk",
+ [71] = "cts_nna_core_clk",
+ [72] = "cts_eth_clk_rmii",
+ [73] = "cts_eth_clk125Mhz",
+ [74] = "cts_jpeg_enc_clk ",
+ [75] = "cts_rtc_clk",
+ [76] = "cts_ge2d_clk",
+ [77] = "cts_gdc_axi_clk",
+ [78] = "cts_gdc_core_clk",
+ [79] = "cts_pwm_j_clk",
+ [80] = "cts_pwm_i_clk",
+ [81] = "cts_pwm_h_clk",
+ [82] = "cts_pwm_g_clk",
+ [83] = "cts_wave_cclk",
+ [84] = "cts_wave_bclk",
+ [85] = "cts_wave_aclk",
+ [86] = "cts_sd_emmc_C_clk",
+ [87] = "cts_sd_emmc_B_clk",
+ [88] = "ephy_test_clk",
+ [89] = "mipi_csi_phy0_clk",
+ [90] = "mipi_csi_phy1_clk",
+ [91] = "mod_eth_phy_ref_clk",
+ [92] = "ddr_dpll_pt_clk",
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-c1/clock.h b/arch/arm/include/asm/arch-c1/clock.h
new file mode 100644
index 0000000..9955501
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/clock.h
@@ -0,0 +1,121 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __C1_H
+#define __C1_H
+
+/*
+ * Clock controller register address
+ * APB_BASE: APB0_BASE_ADDR = 0xfe000800
+ */
+#define C1_SYS_OSCIN_CTRL 0x0
+#define C1_RTC_BY_OSCIN_CTRL0 0x4
+#define C1_RTC_BY_OSCIN_CTRL1 0x8
+#define C1_RTC_CTRL 0xc
+#define C1_SYS_CLK_CTRL0 0x10
+#define C1_AXI_CLK_CTRL0 0x14
+#define C1_SYS_CLK_EN0 0x18
+#define C1_SYS_CLK_EN1 0x1c
+#define C1_SYS_CLK_EN2 0x20
+#define C1_AXI_CLK_EN 0x24
+#define C1_DSPA_CLK_EN 0x28
+#define C1_DSPB_CLK_EN 0x2c
+#define C1_DSPA_CLK_CTRL0 0x30
+#define C1_DSPB_CLK_CTRL0 0x34
+#define C1_CLK12_24_CTRL 0x38
+#define C1_GEN_CLK_CTRL 0x3c
+#define C1_TIMESTAMP_CTRL0 0x40
+#define C1_TIMESTAMP_CTRL1 0x44
+#define C1_TIMESTAMP_CTRL2 0x48
+#define C1_TIMESTAMP_VAL0 0x4c
+#define C1_TIMESTAMP_VAL1 0x50
+#define C1_TIMEBASE_CTRL0 0x54
+#define C1_TIMEBASE_CTRL1 0x58
+#define C1_SAR_ADC_CLK_CTRL 0xc0
+#define C1_PWM_CLK_AB_CTRL 0xc4
+#define C1_PWM_CLK_CD_CTRL 0xc8
+#define C1_PWM_CLK_EF_CTRL 0xcc
+#define C1_SPICC_CLK_CTRL 0xd0
+#define C1_TS_CLK_CTRL 0xd4
+#define C1_SPIFC_CLK_CTRL 0xd8
+#define C1_USB_BUSCLK_CTRL 0xdc
+#define C1_SD_EMMC_CLK_CTRL 0xe0
+#define C1_CECA_CLK_CTRL0 0xe4
+#define C1_CECA_CLK_CTRL1 0xe8
+#define C1_CECB_CLK_CTRL0 0xec
+#define C1_CECB_CLK_CTRL1 0xf0
+#define C1_PSRAM_CLK_CTRL 0xf4
+#define C1_DMC_CLK_CTRL 0xf8
+#define C1_FCLK_DIV1_SEL 0xfc
+#define C1_TST_CTRL 0x100
+#define C1_WAVE_CLK_CTRL0 0x104
+#define C1_WAVE_CLK_CTRL1 0x108
+#define C1_JPEG_CLK_CTRL 0x10C
+#define C1_MIPI_ISP_CLK_CTRL 0x110
+#define C1_NNA_CLK_CTRL 0x114
+#define C1_GDC_CLK_CTRL 0x118
+#define C1_GE2D_CLK_CTRL 0x11C
+#define C1_SD_EMMC_CLK_CTRL1 0x120
+#define C1_ETH_CLK_CTRL 0x124
+#define C1_PWM_CLK_GH_CTRL 0x128
+#define C1_PWM_CLK_IJ_CTRL 0x12C
+#define C1_MBIST_ATSPEED_CTRL 0x130
+
+/*
+ * For PLl register offset
+ * APB_BASE: APB0_BASE_ADDR = 0xfe007c00
+ */
+#define C1_ANACTRL_FIXPLL_GATE_DIS 0x40 + 0x7400
+#define C1_ANACTRL_FIXPLL_CTRL0 0x80 + 0x7400
+#define C1_ANACTRL_FIXPLL_CTRL1 0x84 + 0x7400
+#define C1_ANACTRL_FIXPLL_CTRL2 0x88 + 0x7400
+#define C1_ANACTRL_FIXPLL_CTRL3 0x8c + 0x7400
+#define C1_ANACTRL_FIXPLL_CTRL4 0x90 + 0x7400
+#define C1_ANACTRL_FIXPLL_CTRL5 0x94 + 0x7400
+#define C1_ANACTRL_FIXPLL_CTRL6 0x98 + 0x7400
+#define C1_ANACTRL_FIXPLL_STS 0x9c + 0x7400
+#define C1_ANACTRL_GPPLL_CTRL0 0xc0 + 0x7400
+#define C1_ANACTRL_GPPLL_CTRL1 0xc4 + 0x7400
+#define C1_ANACTRL_GPPLL_CTRL2 0xc8 + 0x7400
+#define C1_ANACTRL_GPPLL_CTRL3 0xcc + 0x7400
+#define C1_ANACTRL_GPPLL_CTRL4 0xd0 + 0x7400
+#define C1_ANACTRL_GPPLL_CTRL5 0xd4 + 0x7400
+#define C1_ANACTRL_GPPLL_STS 0xd8 + 0x7400
+#define C1_ANACTRL_SYSPLL_CTRL0 0x100 + 0x7400
+#define C1_ANACTRL_SYSPLL_CTRL1 0x104 + 0x7400
+#define C1_ANACTRL_SYSPLL_CTRL2 0x108 + 0x7400
+#define C1_ANACTRL_SYSPLL_CTRL3 0x10c + 0x7400
+#define C1_ANACTRL_SYSPLL_CTRL4 0x110 + 0x7400
+#define C1_ANACTRL_SYSPLL_STS 0x114 + 0x7400
+#define C1_ANACTRL_HIFIPLL_CTRL0 0x140 + 0x7400
+#define C1_ANACTRL_HIFIPLL_CTRL1 0x144 + 0x7400
+#define C1_ANACTRL_HIFIPLL_CTRL2 0x148 + 0x7400
+#define C1_ANACTRL_HIFIPLL_CTRL3 0x14c + 0x7400
+#define C1_ANACTRL_HIFIPLL_CTRL4 0x150 + 0x7400
+#define C1_ANACTRL_HIFIPLL_STS 0x154 + 0x7400
+#define C1_ANACTRL_AUDDDS_CTRL0 0x180 + 0x7400
+#define C1_ANACTRL_AUDDDS_CTRL1 0x184 + 0x7400
+#define C1_ANACTRL_AUDDDS_CTRL2 0x188 + 0x7400
+#define C1_ANACTRL_AUDDDS_CTRL3 0x18c + 0x7400
+#define C1_ANACTRL_AUDDDS_CTRL4 0x190 + 0x7400
+#define C1_ANACTRL_AUDDDS_STS 0x194 + 0x7400
+#define C1_ANACTRL_MISCTOP_CTRL0 0x1c0 + 0x7400
+#define C1_ANACTRL_POR_CNTL 0x208 + 0x7400
+
+/*
+ * CPU clok register offset
+ * APB_BASE: APB1_BASE_ADDR = 0xfe007400
+ */
+/*
+ *#define C1_CPUCTRL_CLK_CTRL0 0x0 + 0x7400
+ *#define C1_CPUCTRL_CLK_CTRL1 0x4 + 0x7400
+ *#define C1_CPUCTRL_CLK_CTRL5 0x14 + 0x7400
+ *#define C1_CPUCTRL_CLK_CTRL6 0x18 + 0x7400
+ */
+
+#include <dt-bindings/clock/c1-clkc.h>
+#define NR_CLKS (CLKID_END_BASE)
+
+#endif /* __C1_H */
diff --git a/arch/arm/include/asm/arch-c1/core.h b/arch/arm/include/asm/arch-c1/core.h
new file mode 100644
index 0000000..97fd220
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/core.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __CORE_H__
+#define __CORE_H__
+
+int get_core_mpidr(unsigned int cpuid);
+int get_core_idx(unsigned int mpidr);
+int get_core_max(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-c1/cpu.h b/arch/arm/include/asm/arch-c1/cpu.h
new file mode 100644
index 0000000..478eb38
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/cpu.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+/* #include <config.h> */
+/* #include <asm/plat-cpu.h> */
+/* #include <asm/arch/ddr.h> */
+
+#if 0
+#define CONFIG_AML_MESON 1
+#define CONFIG_AML_MESON_GX 1
+#define CONFIG_AML_MESON_G12A 1
+#endif
+
+/*enable viu probe*/
+#if 0
+#define CONFIG_CMD_VIU_PROBE 1
+#endif
+
+/* for uboot envrionment use */
+#define CONFIG_DDR_SIZE 256
+
+/* dram */
+#define PHYS_SDRAM_1_BASE 0x00000000UL
+#define PHYS_SDRAM_1_SIZE 0x10000000UL
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1_BASE
+
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1_BASE + CONFIG_SYS_TEXT_BASE)
+
+/* console/print buffer */
+#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
+
+/* use "hush" command parser */
+#if 0
+#define CONFIG_SYS_HUSH_PARSER
+#endif
+
+#if 0
+#define CONFIG_DTB_MEM_ADDR 0x1000000
+#endif
+
+#if 0
+#define CONFIG_AML_CUSTOMER_ID (0)
+#endif
+
+#define AML_CUSTOMER_ID (0)
+
+//#define CONFIG_SILENT_CONSOLE
+//#define CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC
+//#define CONFIG_SILENT_U_BOOT_ONLY
+
+/* 2018.03.19 new compress solution, only support BL33 LZ4 compress */
+#define CONFIG_AML_BL33_COMPRESS_ENABLE 1
+
+/* 2018.03.19 G12A only support v3 format for normal & secure boot */
+#define CONFIG_AML_SECURE_BOOT_V3 1
+
+#define NR_CPUS 4
+
+#define CPU_ID_REG SYSCTRL_SEC_STATUS_REG0
+#define PACKAGE_ID_MASK 0xFF
+
+/*C1 SoC secure boot solution default not support AES algorithm*/
+//#define CONFIG_AML_CRYPTO_AES 1
+
+
+/*Flag for enable AES key generate to EFUSE pattern, with this flag only
+AES key will be generated to EFUSE pattern, it can be used for use case
+like the AES key not ready when secure boot enabled for the first time.
+*/
+//#define CONFIG_AML_EFUSE_GEN_AES_ONLY 1
+
+#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-c1/cpu_config.h b/arch/arm/include/asm/arch-c1/cpu_config.h
new file mode 100644
index 0000000..45e7e80
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/cpu_config.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _BOOT_ROM_CONFIG_H_
+#define _BOOT_ROM_CONFIG_H_
+
+/***********************************************************
+ * The following constants are GXBB definition
+ **********************************************************/
+#define ROMBOOT_START 0xD9040000
+#define ROM_SIZE (64*1024)
+#define ROMBOOT_END (ROMBOOT_START+ROM_SIZE)
+
+/***********************************************************
+ * AHB-SRAM Total Size 80KB, layout shown as below
+ *
+ * ROMCODE use the top 32KB
+ *
+ * [ 128] 0xD901_3F80 - 0xD901_3FFF Reserved
+ * [ 128] 0xD901_3F00 - 0xD901_3F7F CPUs Boot Entry
+ * [ 256] 0xD901_3E00 - 0xD901_3EFF Debug Info
+ * [ 512] 0xD901_3C00 - 0xD901_3DFF eFuse mirror
+ * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3)
+ * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) *
+ * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) *
+ * [ 26K] 0xD900_C800 - 0xD901_2FFF BL1 Stack, BSS
+ * [ 1K] 0xD900_C400 - 0xD900_C7FF NAND, USB Buffer
+ * [ 1K] 0xD900_C000 - 0xD900_C3FF Reserved
+ *
+ **********************************************************/
+#define RAM_START 0xD9000000
+#define RAM_SIZE (80 * 1024)
+#define BL1_RAM_START (RAM_START + 0xC000)
+#define BL1_RAM_SIZE (32 * 1024)
+#define BL1_RAM_END (BL1_RAM_START + BL1_RAM_SIZE)
+#define BSS_START (BL1_RAM_START + (2 * 1024))
+#define BSS_SIZE (18 * 1024)
+#define _STACK_END (BSS_START + BSS_SIZE + 8*1024)
+#define BL1_EFUSE_MIRROR (BL1_RAM_END - 1024)
+#define P_SHARED_EFUSE_MIRROR (volatile uint32_t *)(BL1_EFUSE_MIRROR)
+#define BL1_DEBUG_BUFFER (BL1_RAM_END - 512)
+#define CPU_BOOT_ENTRY (BL1_DEBUG_BUFFER + 256)
+#define P_SHARED_DEBUG_BUFF (volatile uint32_t *)(BL1_DEBUG_BUFFER)
+#define BL1_SEC_MBX (BL1_RAM_END - 2*1024)
+#define BL1_NAND_BUFF (BL1_RAM_START + 1024)
+#define BL1_USB_BUFF (BL1_NAND_BUFF)
+
+#define MEMORY_LOC RAM_START
+
+#define SRAM_DEBUG_BUFF_SIZE 256
+
+/* BL2 SPL size */
+#define BL2_SIZE (64 * 1024)
+
+//for signature test
+//#define CONFIG_AML_SIG_TEST_BUILD
+
+/* Software SHA2 */
+#define CONFIG_SHA2_SW
+
+/* Hardware SHA2 */
+#define CONFIG_SHA2_HW
+#define SHA2_HW_UPDATE_API
+
+/* Keep timer config in conf.h */
+#define CONFIG_TIMER
+
+/* Bootrom debug info */
+#define CONFIG_DEBUG_INFO
+
+/* Mincrypt RSA library */
+//#define CONFIG_MINCRYPT
+
+/* PolarSSL RSA library */
+#define CONFIG_POLARSSL_RSA
+
+#ifdef CONFIG_POLARSSL_RSA
+#ifndef CONFIG_MALLOC
+#define CONFIG_MALLOC
+#endif /* ! CONFIG_MALLOC */
+#endif /* CONFIG_POLARSSL_RSA */
+
+#endif /* _BOOT_ROM_CONFIG_H_ */
diff --git a/arch/arm/include/asm/arch-c1/cpu_reset.h b/arch/arm/include/asm/arch-c1/cpu_reset.h
new file mode 100644
index 0000000..46f9abf
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/cpu_reset.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _BOOT_ROM_WATCHDOG_H
+#define _BOOT_ROM_WATCHDOG_H
+#include <asm/arch/secure_apb.h>
+
+void reset_system(void);
+
+/* uboot reset interface */
+void reset_cpu(unsigned long flag);
+
+#endif /* _BOOT_ROM_WATCHDOG_H */
diff --git a/arch/arm/include/asm/arch-c1/cpu_sdio.h b/arch/arm/include/asm/arch-c1/cpu_sdio.h
new file mode 100644
index 0000000..46f366a
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/cpu_sdio.h
@@ -0,0 +1,239 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __CPU_SDIO_H__
+#define __CPU_SDIO_H__
+
+#define SD_EMMC_BASE_A 0xFFE03000
+#define SD_EMMC_BASE_B 0xFFE05000
+#define SD_EMMC_BASE_C 0xFFE07000
+
+#define SDIO_PORT_A 0
+#define SDIO_PORT_B 1
+#define SDIO_PORT_C 2
+
+struct sd_emmc_global_regs {
+ volatile uint32_t gclock; // 0x00
+ volatile uint32_t gdelay; // 0x04
+ volatile uint32_t gdelay1; //0x08
+ volatile uint32_t gadjust; // 0x0c
+ volatile uint32_t gcalout; // 0x10
+ volatile uint32_t reserved_14[11]; // 0x14~0x3c
+ volatile uint32_t gstart; // 0x40
+ volatile uint32_t gcfg; // 0x44
+ volatile uint32_t gstatus; // 0x48
+ volatile uint32_t girq_en; // 0x4c
+ volatile uint32_t gcmd_cfg; // 0x50
+ volatile uint32_t gcmd_arg; // 0x54
+ volatile uint32_t gcmd_dat; // 0x58
+ volatile uint32_t gcmd_rsp0; // 0x5c
+ volatile uint32_t gcmd_rsp1; // 0x60
+ volatile uint32_t gcmd_rsp2; // 0x64
+ volatile uint32_t gcmd_rsp3; // 0x68
+ volatile uint32_t reserved_6c; // 0x6c
+ volatile uint32_t gcurr_cfg; // 0x70
+ volatile uint32_t gcurr_arg; // 0x74
+ volatile uint32_t gcurr_dat; // 0x78
+ volatile uint32_t gcurr_rsp; // 0x7c
+ volatile uint32_t gnext_cfg; // 0x80
+ volatile uint32_t gnext_arg; // 0x84
+ volatile uint32_t gnext_dat; // 0x88
+ volatile uint32_t gnext_rsp; // 0x8c
+ volatile uint32_t grxd; // 0x90
+ volatile uint32_t gtxd; // 0x94
+ volatile uint32_t reserved_98[90]; // 0x98~0x1fc
+ volatile uint32_t gdesc[128]; // 0x200
+ volatile uint32_t gping[128]; // 0x400
+ volatile uint32_t gpong[128]; // 0x800
+};
+
+union sd_emmc_setup {
+ uint32_t d32;
+ struct {
+ unsigned bw:3;
+ unsigned fast:1;
+ unsigned par:3;
+ unsigned hcs:1;
+ unsigned sd:1;
+ unsigned sdhc:1;
+ unsigned type:6;
+ unsigned rca:16;
+ } b;
+};
+
+struct sd_emmc_desc_info{
+ uint32_t cmd_info;
+ uint32_t cmd_arg;
+ uint32_t data_addr;
+ uint32_t resp_addr;
+};
+
+struct cmd_cfg{
+ uint32_t length:9;
+ uint32_t block_mode:1;
+ uint32_t r1b:1;
+ uint32_t end_of_chain:1;
+ uint32_t timeout:4;
+ uint32_t no_resp:1;
+ uint32_t no_cmd:1;
+ uint32_t data_io:1;
+ uint32_t data_wr:1;
+ uint32_t resp_nocrc:1;
+ uint32_t resp_128:1;
+ uint32_t resp_num:1;
+ uint32_t data_num:1;
+ uint32_t cmd_index:6;
+ uint32_t error:1;
+ uint32_t owner:1;
+};
+
+struct sd_emmc_status{
+ uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire, for multiple block read, the CRC errors are ORed together.*/
+ uint32_t txd_err:1; /*[8] TX data CRC error, for multiple block write, any one of blocks CRC error. */
+ uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. The owner bit is ¡°0¡±, set cfg_ignore_owner to ignore this error.*/
+ uint32_t resp_err:1; /*[10] Response CRC error.*/
+ uint32_t resp_timeout:1; /*[11] No response received before time limit. The timeout limit is set by cfg_resp_timeout.*/
+ uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. The timeout limit is set by descriptor itself.*/
+ /* Consider the multiple block read/write, set the proper timeout limits.*/
+ uint32_t end_of_chain:1; /*[13] End of Chain IRQ, Normal IRQ. */
+ uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ, Normal IRQ, the descriptor chain execution keeps going on.*/
+ uint32_t irq_sdio:1; /*[15] SDIO device uses DAT[1] to request IRQ. */
+ uint32_t dat_i:8; /*[23:16] Input data signals. */
+ uint32_t cmd_i:1; /*[24] nput response signal. */
+ uint32_t ds:1; /*[25] Input data strobe. */
+ uint32_t bus_fsm:4; /*[29:26] BUS fsm */
+ uint32_t desc_wr_rdy:1; /*[30] Descriptor write back process is done and it is ready for CPU to read.*/
+ uint32_t core_rdy:1; /*[31] desc_busy or sd_emmc_irq or bus_fsm is not idle.*/
+};//__attribute__((__may_alias__));
+
+
+struct sd_emmc_clock{
+ uint32_t div:6; /*[5:0] Clock divider. Frequency = clock source/cfg_div, Maximum divider 63. */
+ /*Clock off: cfg_div==0, the clock is disabled */
+ /*Divider bypass: cfg_div==1, clock source is used as core clock without divider. */
+ uint32_t src:2; /*[7:6] Clock source, 0: Crystal 24MHz, 1: Fix PLL, 850MHz*/
+ /* 2: MPLL, <637MHz, used for 400MHz exactly. 3: different PLL */
+ uint32_t core_phase:2; /*[9:8] Core clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/
+ uint32_t tx_phase:2; /*[11:10] TX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/
+ uint32_t rx_phase:2; /*[13:12] RX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/
+ uint32_t reserved14:2;
+ uint32_t tx_delay:6; /*[21:16] TX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/
+ uint32_t rx_delay:6; /*[27:22] RX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/
+ uint32_t always_on:1; /*[28] 1: Keep clock always on. 0: Clock on/off controlled by activities. */
+ /*Any APB3 access or descriptor execution will keep clock on.*/
+ uint32_t irq_sdio_sleep:1; /*[29] 1: enable IRQ sdio when in sleep mode. */
+ uint32_t irq_sdio_sleep_ds:1;/*[30] 1:enable ds as irq*/
+ uint32_t reserved26:1;
+};
+
+struct sd_emmc_delay{
+ uint32_t dat0:6; /*[3:0] Data 0 delay line. */
+ uint32_t dat1:6; /*[7:4] Data 1 delay line. */
+ uint32_t dat2:6; /*[11:8] Data 2 delay line. */
+ uint32_t dat3:6; /*[15:12] Data 3 delay line. */
+ uint32_t dat4:6; /*[19:16] Data 4 delay line. */
+ uint32_t spare:2;
+};
+
+struct sd_emmc_delay1{
+ uint32_t dat5:6; /*[23:20] Data 5 delay line. */
+ uint32_t dat6:6; /*[27:24] Data 6 delay line. */
+ uint32_t dat7:6; /*[31:28] Data 7 delay line. */
+ uint32_t dat8:6; /*[31:28] Data 7 delay line. */
+ uint32_t dat9:6; /*[31:28] Data 7 delay line. */
+ uint32_t spare:2;
+};
+
+struct sd_emmc_adjust{
+ uint32_t cmd_delay:4; /*[3:0] Command delay line. */
+ uint32_t ds_delay:4; /*[7:4] DS delay line. */
+ uint32_t cali_sel:4; /*[11:8] Select one signal to be tested.*/
+ /*Signals are labeled from 0 to 9 the same as delay lines. */
+ uint32_t cali_enable:1; /*[12] Enable calibration. */
+ uint32_t adj_enable:1; /*[13] Adjust interface timing by resampling the input signals. */
+ uint32_t cali_rise:1; /*[14] 1: test the rising edge. 0: test the falling edge. */
+ uint32_t ds_enable:1; /*[15] Sampling the DAT based on DS in HS400 mode*/
+ uint32_t adj_delay:6; /*[21:16] Resample the input signals when clock index==adj_delay. */
+ uint32_t adj_auto:1; /*[22] Use cali_dut first falling edge to adjust the timing */
+ /*set cali_enable to 1 to use this function*/
+ uint32_t reserved23:9;
+};
+
+
+struct sd_emmc_calout{
+ uint32_t cali_idx:6; /*[5:0] Calibration reading. The event happens at this index. */
+ uint32_t reserved6:1;
+ uint32_t cali_vld:1; /*[7] The reading is valid. */
+ uint32_t cali_setup:8; /*[15:8] Copied from BASE+0x8 [15:8] include cali_sel, cali_enable, adj_enable, cali_rise. */
+ uint32_t reserved16:16;
+};
+
+
+struct sd_emmc_start{
+ uint32_t init:1; /*[0] 1: Read descriptor from internal SRAM, limited to 32 descriptors. */
+ /* 0: Read descriptor from external DDR */
+ uint32_t busy:1; /*[1] 1: Start command chain execution process. 0: Stop */
+ uint32_t addr:30; /*[31:2] Descriptor address, the last 2 bits are 0, 4 bytes aligned. */
+ /* When internal SRAM is used, the valid address range is from 0x200~0x3ff */
+ /* When external DDR is used, the valid address is anywhere in DDR, the length of chain is unlimited.*/
+};//__attribute__((__may_alias__));
+
+
+struct sd_emmc_config{
+ uint32_t bus_width:2; /*[1:0] 0: 1 bit, 1: 4 bits, 2: 8 bits, 3: 2 bits (not supported)*/
+ uint32_t ddr:1; /*[2] 1: DDR mode, 0: SDR mode */
+ uint32_t dc_ugt:1; /*[3] 1: DDR access urgent, 0: DDR access normal. */
+ uint32_t bl_len:4; /*[7:4] Block length 2^cfg_bl_len, because internal buffer size is limited to 512 bytes, the cfg_bl_len <=9. */
+ uint32_t resp_timeout:4; /*[11:8] Wait response till 2^cfg_resp_timeout core clock cycles. Maximum 32768 core cycles. */
+ uint32_t rc_cc:4; /*[15:12] Wait response-command, command-command gap before next command, 2^cfg_rc_cc core clock cycles. */
+ uint32_t out_fall:1; /*[16] DDR mode only. The command and TXD start from rising edge. Set 1 to start from falling edge. */
+ uint32_t blk_gap_ip:1; /*[17] 1: Enable SDIO data block gap interrupt period. 0: Disabled.*/
+ uint32_t spare:1; /*[18] Spare, ??? need check*/
+ uint32_t ignore_owner:1; /*[19] Use this descriptor even if its owner bit is ¡°0¡±.*/
+ uint32_t chk_ds:1; /*[20] Check data strobe in HS400.*/
+ uint32_t cmd_low:1; /*[21] Hold CMD as output Low, eMMC boot mode.*/
+ uint32_t stop_clk:1; /*[22] 1: stop clock. 0: normal clock.*/
+ /*In normal mode, the clock is automatically on/off during reading mode to back off reading in case of*/
+ /*DDR slow response, stop clock is used in voltage switch.*/
+ uint32_t auto_clk:1; /*[23] 1: when BUS is idle and no descriptor is available, turn off clock, to save power.*/
+ /* 0: core clock is always on.*/
+ uint32_t txd_add_err:1; /*[24] TXD add error test*/
+ /*Test feature, should not be used in normal condition.*/
+ /*It will inverted the first CRC bits of the 3rd block.*/
+ /*Block index starts from 0, 1, 2, ¡*/
+ uint32_t txd_retry:1; /*[25] When TXD CRC error, host sends the block again.*/
+ /*The total number of retries of one descriptor is limited to 15, */
+ /*after 15 retries, the TXD_err is set to high.*/
+ uint32_t revd:8; /*[31:26] reved*/
+};//__attribute__((__may_alias__));
+
+
+struct sd_emmc_irq_en{
+ uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire.*/
+ uint32_t txd_err:1; /*[8] TX data CRC error. */
+ uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. */
+ uint32_t resp_err:1; /*[10] Response CRC error.*/
+ uint32_t resp_timeout:1; /*[11] No response received before time limit. */
+ uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. */
+ uint32_t end_of_chain:1; /*[13] End of Chain IRQ. */
+ uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ. */
+ uint32_t irq_sdio:1; /*[15] Enable sdio interrupt. */
+ uint32_t revd:16; /*[31:16] reved*/
+};
+
+struct sd_emmc_data_info{
+ uint32_t cnt:10; /*[9:0] Rxd words received from BUS. Txd words received from DDR.*/
+ uint32_t blk:9; /*[24:16] Rxd Blocks received from BUS. Txd blocks received from DDR.*/
+ uint32_t revd:30; /*[31:17] Reved. */
+};
+
+
+struct sd_emmc_card_info{
+ uint32_t txd_cnt:10; /*[9:0] Txd BUS cycle counter. */
+ uint32_t txd_blk:9; /*[24:16] Txd BUS block counter.*/
+ uint32_t revd:30; /*[31:17] Reved. */
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-c1/ddr.h b/arch/arm/include/asm/arch-c1/ddr.h
new file mode 100644
index 0000000..ad27855
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/ddr.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <io.h>
+#include <stdint.h>
+#include <asm/arch/ddr_define.h>
+
+/* io defines */
+//#define wr_reg(addr, data) (*((volatile uint32_t *)addr))=(uint32_t)(uint64_t)(data)
+//#define rd_reg(addr) (*((volatile uint32_t *)(addr)))
+#define wr_reg(addr, data) writel(data, addr)
+#define rd_reg(addr) readl(addr)
+/*clear [mask] 0 bits in [addr], set these 0 bits with [value] corresponding bits*/
+#define modify_reg(addr, value, mask) wr_reg(addr, ((rd_reg(addr) & (mask)) | (value)))
+#define wait_set(addr, loc) do{}while(0 == (rd_reg(addr) & (1<<loc)));
+#define wait_clr(addr, loc) do{}while(1 == (rd_reg(addr) & (1<<loc)));
+#define wait_equal(addr, data) do{}while(data != (rd_reg(addr)));
+
+/* function defines */
+unsigned int ddr_init(void);
+unsigned int ddr_init_pll(void);
+unsigned int ddr_init_dmc(void);
+unsigned int ddr_init_pctl(void);
+unsigned int hot_boot(void);
+void ddr_print_info(void);
+void ddr_test(void);
+void ddr_pre_init(void);
+void ddr_debug(void);
+
+/* pctl status */
+#define UPCTL_STAT_MASK (7)
+#define UPCTL_STAT_INIT (0)
+#define UPCTL_STAT_CONFIG (1)
+#define UPCTL_STAT_ACCESS (3)
+#define UPCTL_STAT_LOW_POWER (5)
+
+/* pctl cmds */
+#define UPCTL_CMD_INIT (0)
+#define UPCTL_CMD_CONFIG (1)
+#define UPCTL_CMD_GO (2)
+#define UPCTL_CMD_SLEEP (3)
+#define UPCTL_CMD_WAKEUP (4)
+
+/* PUB PIR setting */
+#define PUB_PIR_INIT (1<<0)
+#define PUB_PIR_ZCAL (1<<1)
+#define PUB_PIR_CA (1<<2)
+#define PUB_PIR_PLLINIT (1<<4)
+#define PUB_PIR_DCAL (1<<5)
+#define PUB_PIR_PHYRST (1<<6)
+#define PUB_PIR_DRAMRST (1<<7)
+#define PUB_PIR_DRAMINIT (1<<8)
+#define PUB_PIR_WL (1<<9)
+#define PUB_PIR_QSGATE (1<<10)
+#define PUB_PIR_WLADJ (1<<11)
+#define PUB_PIR_RDDSKW (1<<12)
+#define PUB_PIR_WRDSKW (1<<13)
+#define PUB_PIR_RDEYE (1<<14)
+#define PUB_PIR_WREYE (1<<15)
+#define PUB_PIR_ICPC (1<<16)
+#define PUB_PIR_PLLBYP (1<<17)
+#define PUB_PIR_CTLDINIT (1<<18)
+#define PUB_PIR_RDIMMINIT (1<<19)
+#define PUB_PIR_CLRSR (1<<27)
+#define PUB_PIR_LOCKBYP (1<<28)
+#define PUB_PIR_DCALBYP (1<<29)
+#define PUB_PIR_ZCALBYP (1<<30)
+#define PUB_PIR_INITBYP (1<<31)
+
+/* PHY initialize register (PIR) */
+#define DDR_PIR ((PUB_PIR_ZCAL) |\
+ (PUB_PIR_PLLINIT) |\
+ (PUB_PIR_DCAL) |\
+ (PUB_PIR_PHYRST) |\
+ (PUB_PIR_DRAMRST) |\
+ (PUB_PIR_DRAMINIT) |\
+ (PUB_PIR_WL) |\
+ (PUB_PIR_QSGATE) |\
+ (PUB_PIR_WLADJ) |\
+ (PUB_PIR_RDDSKW) |\
+ (PUB_PIR_WRDSKW) |\
+ (PUB_PIR_RDEYE) |\
+ (PUB_PIR_WREYE) \
+ )
+
+/* PHY general status register (PGSR0) */
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+#define DDR_PGSR0_CHECK() ((rd_reg(DDR0_PUB_PGSR0) != 0xC0000fff) && \
+ (rd_reg(DDR0_PUB_PGSR0) != 0x80000fff))
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define DDR_PGSR0_CHECK()
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define DDR_PGSR0_CHECK()
+#endif
+
+/* other regs */
+#define SCRATCH0 0xC1107D3C
diff --git a/arch/arm/include/asm/arch-c1/ddr_define.h b/arch/arm/include/asm/arch-c1/ddr_define.h
new file mode 100644
index 0000000..2d2697e
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/ddr_define.h
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#define CONFIG_BOARD_ID_MASK 0xFF
+#define CONFIG_DDR_TYPE_DDR3 0
+#define CONFIG_DDR_TYPE_DDR4 1
+#define CONFIG_DDR_TYPE_LPDDR4 2
+#define CONFIG_DDR_TYPE_LPDDR3 3
+#define CONFIG_DDR_TYPE_LPDDR2 4
+#define CONFIG_DDR_TYPE_AUTO 0xf
+
+/* ddr channel defines */
+#define CONFIG_DDR0_16BIT 1
+#define CONFIG_DDR0_RANK0 2
+#define CONFIG_DDR0_RANK01 3
+#define CONFIG_DDR0_16BIT_2 4
+/* CONFIG_DDR_CHL_AUTO mode support RANK0 and RANK0+1 mode auto detect */
+#define CONFIG_DDR_CHL_AUTO 0xF
+#define CONFIG_DDR0_16BIT_CH0 0x1
+#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7
+#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8
+
+#define CFG_DDR_BASE_ADDR 0X0
+#define CFG_DDR_START_OFFSET 0X00000000 //TXLX SKIP 0MB
+
+/* ddr type identifier */
+#define CONFIG_DDR_TIMMING_LPDDR2 0x02
+#define CONFIG_DDR_TIMMING_LPDDR3 0x03
+#define CONFIG_DDR_TIMMING_DDR3_7 0x07
+#define CONFIG_DDR_TIMMING_DDR3_9 0x09
+#define CONFIG_DDR_TIMMING_DDR3_11 0x0B
+#define CONFIG_DDR_TIMMING_DDR3_12 0x0C
+#define CONFIG_DDR_TIMMING_DDR3_13 0x0D
+#define CONFIG_DDR_TIMMING_DDR3_14 0x0E
+
+#define CONFIG_DDR_TIMMING_DDR4_1600 0x0F
+#define CONFIG_DDR_TIMMING_DDR4_1866 0x10
+#define CONFIG_DDR_TIMMING_DDR4_2133 0x11
+#define CONFIG_DDR_TIMMING_DDR4_2400 0x12
+#define CONFIG_DDR_TIMMING_DDR4_2666 0x13
+#define CONFIG_DDR_TIMMING_DDR4_3200 0x14
+
+#define LPDDR_DIE_ROW_COL_R13_C9 0
+#define LPDDR_DIE_ROW_COL_R14_C9 1
+#define LPDDR_DIE_ROW_COL_R14_C10 2
+#define LPDDR_DIE_ROW_COL_R13_C10 3
+#define LPDDR_DIE_ROW_COL_R14_C11 4
+
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE0 0
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE1 1
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE2 2
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE3 3
+
+#define CONFIG_DDR_FUNC_TEST (1<<0)
+
+#define CONFIG_DDR_INIT_RETRY_TOTAL (10)
+#define CONFIG_DDR_PCTL_RETRY_TOTAL (100)
+
+#define DDR_USE_1_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK0) || \
+ (chl_set == CONFIG_DDR0_16BIT))
+#define DDR_USE_2_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK01))
+
+#define DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT 1<<5
+#define DMC_TEST_SLT_ENABLE_DDR_AUTO_WINDOW_TEST 1<<4
+/* DMC_DDR_CTRL defines */
+#define DDR_DDR4_ENABLE (1<<22)
+#define DDR_RANK1_ENABLE (1<<21)
+#define DDR_DDR4_BG_ENABLE (1<<20)
+#define DDR_16BIT_ENABLE (1<<16)
+
+#define DDR_RANK1_SIZE_CTRL (3)
+#define DDR_RANK0_SIZE_CTRL (0)
+
+/* dram cfg magic */
+#define DRAM_CFG_MAGIC 0x2e676663
+
+#define DMC_TEST_SLT_SCAN_FREQUENCY 1
+#define DMC_TEST_SLT_OFFSET_DELAY (1<<1)
+#define DMC_TEST_SLT_ENABLE_DDR_SKIP_TRAINING (1<<6)
+#define DMC_TEST_SLT_ENABLE_DDR_DVFS (1<<7)
+
+/* ddr configs */
+#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+
+#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+#define DDR_RFC_TYPE_LPDDR4_6Gbx1 12
+#define DDR_RFC_TYPE_LPDDR4_8Gbx1 13
+
+#define DDR_ENABLE_FINE_TUNE_FLAG_AC_DELAY (1<<0)
+#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQS (1<<1)
+#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS (1<<2)
+#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ (1<<3)
+#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ (1<<4)
+
+/* lpddr3 defines */
+#ifndef CONFIG_LPDDR_REMAP_SET
+#define CONFIG_LPDDR_REMAP_SET LPDDR_DIE_ROW_COL_R14_C9
+#endif
+
+/* how to add a new ddr function?
+ 1. add CONFIG_DDR_FUNC_XXX in (config).h file
+ 2. add define in this file.
+ 2.1 add
+ #ifndef CONFIG_DDR_FUNC_XXX
+ #define CONFIG_DDR_FUNC_XXX 0
+ #endif
+ 2.2 add
+ #define DDR_FUNC_XXX (CONFIG_FUNC_XXX<<X)
+ 2.3 add DDR_FUNC_XXX |\ in DDR_FUNC
+ 3. add same define and parser in bl2 code
+ */
+/* 2.1, 2,2, 2,3 example */
+/*
+#ifndef CONFIG_CMD_DDR_D2PLL
+#define CONFIG_CMD_DDR_D2PLL 0
+#endif
+#define DDR_FUNC_D2PLL (CONFIG_CMD_DDR_D2PLL<<0)
+#define DDR_FUNC (EXISTING_FUNCTIONS) |\
+ (DDR_FUNC_D2PLL)
+*/
+
+/* d2pll support */
+#ifndef CONFIG_CMD_DDR_D2PLL
+#define CONFIG_CMD_DDR_D2PLL 0
+#endif
+#define DDR_FUNC_D2PLL (CONFIG_CMD_DDR_D2PLL<<0)
+
+/* ddr low power function support */
+#ifndef CONFIG_DDR_LOW_POWER
+#define CONFIG_DDR_LOW_POWER 0
+#endif
+#define DDR_FUNC_LP (CONFIG_DDR_LOW_POWER<<1)
+
+/* ddr zq power down support */
+#ifndef CONFIG_DDR_ZQ_PD
+#define CONFIG_DDR_ZQ_PD 0
+#endif
+#define DDR_FUNC_ZQ_PD (CONFIG_DDR_ZQ_PD<<2)
+
+/* ddr vref function */
+#ifndef CONFIG_DDR_USE_EXT_VREF
+#define CONFIG_DDR_USE_EXT_VREF 0
+#endif
+#define DDR_FUNC_EXT_VREF (CONFIG_DDR_USE_EXT_VREF<<3)
+
+/* ddr4 timing test function */
+#ifndef CONFIG_DDR4_TIMING_TEST
+#define CONFIG_DDR4_TIMING_TEST 0
+#endif
+#define DDR_FUNC_DDR4_TIMING_TEST (CONFIG_DDR4_TIMING_TEST<<4)
+
+/* ddr pll bypass */
+#ifndef CONFIG_DDR_PLL_BYPASS
+#define CONFIG_DDR_PLL_BYPASS 0
+#endif
+#define DDR_FUNC_DDR_PLL_BYPASS (CONFIG_DDR_PLL_BYPASS<<5)
+
+/* ddr rdbi function */
+#ifndef CONFIG_DDR_FUNC_RDBI
+#define CONFIG_DDR_FUNC_RDBI 0
+#endif
+#define DDR_FUNC_RDBI (CONFIG_DDR_FUNC_RDBI<<6)
+
+/* lpddr3 ca trainingi function */
+#ifndef CONFIG_DDR_FUNC_LPDDR3_CA
+#define CONFIG_DDR_FUNC_LPDDR3_CA 0
+#endif
+#define DDR_FUNC_LPDDR3_CA (CONFIG_DDR_FUNC_LPDDR3_CA<<7)
+
+/* print ddr training window */
+#ifndef CONFIG_DDR_FUNC_PRINT_WINDOW
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 0
+#endif
+#define DDR_FUNC_PRINT_WINDOW (CONFIG_DDR_FUNC_PRINT_WINDOW<<8)
+
+
+/* print ddr training window */
+//#ifndef CONFIG_DDR_FULL_TEST
+//#define CONFIG_DDR_FULL_TEST 0
+//#endif
+//#define DDR_FULL_TEST (CONFIG_DDR_FULL_TEST<<10)
+
+/* non-sec region scramble function */
+#ifndef CONFIG_DDR_NONSEC_SCRAMBLE
+#define CONFIG_DDR_NONSEC_SCRAMBLE 0
+#endif
+#define DDR_NONSEC_SCRAMBLE (CONFIG_DDR_NONSEC_SCRAMBLE<<11)
+
+#if(CONFIG_DDR_FUNC_LPDDR3_CA==1)
+#if (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE0)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21)
+#elif (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE1)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (1<<20)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21)
+#elif (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE2)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (1<<21)
+#elif (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE3)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (1<<20)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (1<<21)
+#endif
+#if (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE0)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (0<<22)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (0<<23)
+#elif (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE1)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (1<<22)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (0<<23)
+#elif (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE2)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (0<<22)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (1<<23)
+#elif (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE3)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (1<<22)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (1<<23)
+#endif
+#else /* CONFIG_DDR_FUNC_LPDDR3_CA != 1 */
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (0<<22)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (0<<23)
+#endif /* CONFIG_DDR_FUNC_LPDDR3_CA */
+
+#if(CONFIG_DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP==1)
+#define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP (1<<25)
+#else
+#define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP (0<<25)
+#endif
+#define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1<<30)
+#define DDR_FUNC_CONFIG_DFE_FUNCTION (1<<29)
+#define DDR_FUNC_CONFIG_DDR_DVFS_FUNCTION (1<<28)
+#define DDR_FUNC (DDR_FUNC_D2PLL | \
+ DDR_FUNC_LP | \
+ DDR_FUNC_ZQ_PD | \
+ DDR_FUNC_EXT_VREF | \
+ DDR_FUNC_DDR4_TIMING_TEST | \
+ DDR_FUNC_DDR_PLL_BYPASS | \
+ DDR_FUNC_RDBI | \
+ DDR_FUNC_LPDDR3_CA | \
+ DDR_FUNC_PRINT_WINDOW | \
+ DDR_FULL_TEST | \
+ DDR_NONSEC_SCRAMBLE | \
+ DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0| \
+ DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1| \
+ DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0| \
+ DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1| \
+ DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP | \
+ (1 << 31) \
+ )
+
+
+
+
+/* bl2 reg override stages define */
+#define BL2_INIT_STAGE_0 0
+#define BL2_INIT_STAGE_1 1
+#define BL2_INIT_STAGE_2 2
+#define BL2_INIT_STAGE_3 3
+#define BL2_INIT_STAGE_4 4
+#define BL2_INIT_STAGE_5 5
+#define BL2_INIT_STAGE_6 6
+#define BL2_INIT_STAGE_7 7
+#define BL2_INIT_STAGE_8 8
+#define BL2_INIT_STAGE_9 9
+
+
+/* ddr reg override stages define */
+#define DDR_OVERRIDE_STAGE_DDR3_PRE_INIT 0x10
+#define DDR_OVERRIDE_STAGE_DDR3_DMC_INIT 0x11
+
+#define DDR_OVERRIDE_STAGE_DDR4_PRE_INIT 0x20
+#define DDR_OVERRIDE_STAGE_DDR4_DMC_INIT 0x21
+
+#define DDR_OVERRIDE_STAGE_LPDDR3_PRE_INIT 0x30
+#define DDR_OVERRIDE_STAGE_LPDDR3_DMC_INIT 0x31
+
+#define DDR_OVERRIDE_STAGE_LPDDR4_PRE_INIT 0x40
+#define DDR_OVERRIDE_STAGE_LPDDR4_DMC_INIT 0x41
+
+
+#define DWC_AC_PINMUX_TOTAL 28
+#define DWC_DFI_PINMUX_TOTAL 26
+#define DWC_DQ_PINMUX_TOTAL 32
+
+/* diagnose function defines */
+#define CONFIG_DIAGNOSE_DISABLE 0x0
+#define CONFIG_DIAGNOSE_1D 0x1
+#define CONFIG_DIAGNOSE_2D 0x2
+#define CONFIG_DIAGNOSE_1D_2D 0x3
diff --git a/arch/arm/include/asm/arch-c1/efuse.h b/arch/arm/include/asm/arch-c1/efuse.h
new file mode 100644
index 0000000..4a68e88
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/efuse.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __EFUSE_H
+#define __EFUSE_H
+
+#include <config.h>
+#include <common.h>
+
+/* efuse HAL_API arg */
+struct efuse_hal_api_arg {
+ unsigned int cmd; /* R/W */
+ unsigned int offset;
+ unsigned int size;
+ unsigned long buffer_phy;
+ unsigned long retcnt_phy;
+};
+
+
+#define EFUSE_BYTES 512 /* (EFUSE_BITS/8) */
+
+#define EFUSE_HAL_API_READ 0
+#define EFUSE_HAL_API_WRITE 1
+#define EFUSE_HAL_API_WRITE_PATTERN 2
+#define EFUSE_HAL_API_USER_MAX 3
+
+#define EFUSE_USER_MASK (0x1 << 16)
+#define EFUSE_THERMAL_MASK (0x1 << 17)
+#define EFUSE_THERMAL_VERFLAG_MASK (0x1 << 18)
+#define EFUSE_ENCRYPT_MASK (0x1 << 19)
+
+//#define ASSIST_HW_REV 0x1f53
+
+int efuse_read_usr(char *buf, size_t count, loff_t *ppos);
+int efuse_write_usr(char *buf, size_t count, loff_t *ppos);
+uint32_t efuse_get_max(void);
+ssize_t efuse_read(char *buf, size_t count, loff_t *ppos);
+ssize_t efuse_write(const char *buf, size_t count, loff_t *ppos);
+
+int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg);
+int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg);
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-c1/eth_setup.h b/arch/arm/include/asm/arch-c1/eth_setup.h
new file mode 100644
index 0000000..6e643f6
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/eth_setup.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/io.h>
+
+/*
+ *board configuration interface.
+ * */
+struct eth_clock_conf{
+ int enable;
+ int clock_50MHZ_phase;
+ //add ... as you need.
+};
+
+struct eth_board_socket{
+char *name ;
+int (*eth_clock_configure)(struct eth_clock_conf);
+int (*eth_pinmux_setup)(void);
+int (*eth_hw_reset)(void);
+
+};
+
+
+
+/*
+ *clock define part
+ */
+
+#define ETH_BASE (0xff3f0000)
+#define ETH_PLL_CNTL CBUS_REG_ADDR(0x2050)
+ /* Ethernet ctrl */
+#define ETH_PLL_CNTL_DIVEN (1<<0)
+#define ETH_PLL_CNTL_MACSPD (1<<1)
+#define ETH_PLL_CNTL_DATEND (1<<2)
+#define ETH_PLL_CNTL_DESEND (1<<3)
+
+
+/*
+ please refer following doc for detail
+ @AppNote-M3-ClockTrees.docx
+
+ select clk: -> CBUS_REG(0x1076)
+
+ 7-sys_pll_div2
+ 6-vid2_pll_clk
+ 5-vid_pll_clk
+ 4-aud_pll_clk
+ 3-ddr_pll_clk
+ 2-misc_pll_clk
+ 1-sys_pll_clk
+ 0-XTAL
+
+ clk_freq:800MHz
+ output_clk:50MHz
+ aways,maybe changed for others?
+*/
+
+#define ETH_CLKSRC_XTAL (0)
+#define ETH_CLKSRC_SYS_PLL_CLK (1)
+#define ETH_CLKSRC_MISC_PLL_CLK (2)
+#define ETH_CLKSRC_DDR_PLL_CLK (3)
+#define ETH_CLKSRC_AUD_PLL_CLK (
+#define ETH_CLKSRC_VID_PLL_CLK (5)
+#define ETH_CLKSRC_VID2_PLL_CLK (6)
+#define ETH_CLKSRC_SYS_PLL_DIV2_CLK (7)
+#define CLK_1M (1000000)
+
+typedef union eth_aml_reg0 {
+ /** raw register data */
+ unsigned int d32;
+ /** register bits */
+ struct {
+ unsigned phy_intf_sel:3;
+ unsigned rx_clk_rmii_invert:1;
+ unsigned rgmii_tx_clk_src:1;
+ unsigned rgmii_tx_clk_phase:2;
+ unsigned rgmii_tx_clk_ratio:3;
+ unsigned phy_ref_clk_enable:1;
+ unsigned clk_rmii_i_invert:1;
+ unsigned clk_en:1;
+ unsigned adj_enable:1;
+ unsigned adj_setup:1;
+ unsigned adj_delay:5;
+ unsigned adj_skew:5;
+ unsigned cali_start:1;
+ unsigned cali_rise:1;
+ unsigned cali_sel:3;
+ unsigned rgmii_rx_reuse:1;
+ unsigned eth_urgent:1;
+ } b;
+} eth_aml_reg0_t;
+
+#define ETH_VALIDE_CLKSRC(clk,out_clk) ((clk%out_clk)==0)
+
+int eth_clk_set(int selectclk,unsigned long clk_freq,unsigned long out_clk);
+
diff --git a/arch/arm/include/asm/arch-c1/gpio.h b/arch/arm/include/asm/arch-c1/gpio.h
new file mode 100644
index 0000000..2467368
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/gpio.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_ARCH_MESON_GPIO_H
+#define __ASM_ARCH_MESON_GPIO_H
+
+
+#endif /* __ASM_ARCH_MESON_GPIO_H */
diff --git a/arch/arm/include/asm/arch-c1/i2c.h b/arch/arm/include/asm/arch-c1/i2c.h
new file mode 100644
index 0000000..a93a09d
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/i2c.h
@@ -0,0 +1,280 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AML_MACH_I2C__
+#define __AML_MACH_I2C__
+
+#include <asm/io.h>
+#include <asm/arch/secure_apb.h>
+
+/**
+ * struct i2c_msg - an I2C transaction segment beginning with START
+ * @addr: Slave address, either seven or ten bits. When this is a ten
+ * bit address, I2C_M_TEN must be set in @flags and the adapter
+ * must support I2C_FUNC_10BIT_ADDR.
+ * @flags: I2C_M_RD is handled by all adapters. No other flags may be
+ * provided unless the adapter exported the relevant I2C_FUNC_*
+ * flags through i2c_check_functionality().
+ * @len: Number of data bytes in @buf being read from or written to the
+ * I2C slave address. For read transactions where I2C_M_RECV_LEN
+ * is set, the caller guarantees that this buffer can hold up to
+ * 32 bytes in addition to the initial length byte sent by the
+ * slave (plus, if used, the SMBus PEC); and this value will be
+ * incremented by the number of block data bytes received.
+ * @buf: The buffer into which data is read, or from which it's written.
+ *
+ * An i2c_msg is the low level representation of one segment of an I2C
+ * transaction. It is visible to drivers in the @i2c_transfer() procedure,
+ * to userspace from i2c-dev, and to I2C adapter drivers through the
+ * @i2c_adapter.@master_xfer() method.
+ *
+ * Except when I2C "protocol mangling" is used, all I2C adapters implement
+ * the standard rules for I2C transactions. Each transaction begins with a
+ * START. That is followed by the slave address, and a bit encoding read
+ * versus write. Then follow all the data bytes, possibly including a byte
+ * with SMBus PEC. The transfer terminates with a NAK, or when all those
+ * bytes have been transferred and ACKed. If this is the last message in a
+ * group, it is followed by a STOP. Otherwise it is followed by the next
+ * @i2c_msg transaction segment, beginning with a (repeated) START.
+ *
+ * Alternatively, when the adapter supports I2C_FUNC_PROTOCOL_MANGLING then
+ * passing certain @flags may have changed those standard protocol behaviors.
+ * Those flags are only for use with broken/nonconforming slaves, and with
+ * adapters which are known to support the specific mangling options they
+ * need (one or more of IGNORE_NAK, NO_RD_ACK, NOSTART, and REV_DIR_ADDR).
+ */
+struct i2c_msg {
+ __u16 addr; /* slave address */
+ __u16 flags;
+#define I2C_M_TEN 0x0010 /* this is a ten bit chip address */
+#define I2C_M_RD 0x0001 /* read data, from slave to master */
+#define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_NO_RD_ACK 0x0800 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_RECV_LEN 0x0400 /* length will be first received byte */
+ __u16 len; /* msg length */
+ __u8 *buf; /* pointer to msg data */
+};
+
+#define MESON_I2C_MASTER_AO_START (AO_I2C_M_0_CONTROL_REG)
+//#define MESON_I2C_MASTER_AO_END (0xc810051c+5)
+
+#define MESON_I2C_MASTER_A_START CBUS_REG_ADDR(I2C_M_0_CONTROL_REG)
+#define MESON_I2C_MASTER_A_END (CBUS_REG_ADDR(I2C_M_0_RDATA_REG1+1)-1)
+
+#define MESON_I2C_MASTER_B_START CBUS_REG_ADDR(I2C_M_1_CONTROL_REG)
+#define MESON_I2C_MASTER_B_END (CBUS_REG_ADDR(I2C_M_1_RDATA_REG1+1)-1)
+
+#define MESON_I2C_MASTER_C_START CBUS_REG_ADDR(I2C_M_2_CONTROL_REG)
+#define MESON_I2C_MASTER_C_END (CBUS_REG_ADDR(I2C_M_2_RDATA_REG1+1)-1)
+
+#define MESON_I2C_MASTER_D_START CBUS_REG_ADDR(I2C_M_3_CONTROL_REG)
+#define MESON_I2C_MASTER_D_END (CBUS_REG_ADDR(I2C_M_3_RDATA_REG1+1)-1)
+
+#define MESON_I2C_SLAVE_START CBUS_REG_ADDR(I2C_S_CONTROL_REG)
+#define MESON_I2C_SLAVE_END (CBUS_REG_ADDR(I2C_S_CNTL1_REG+1)-1)
+
+
+#define AML_I2C_MASTER_AO 0
+#define AML_I2C_MASTER_A 1
+#define AML_I2C_MASTER_B 2
+#define AML_I2C_MASTER_C 3
+#define AML_I2C_MASTER_D 4
+
+
+#define AML_I2C_SLAVE_ADDR 0x6c
+
+/*M1 i2c pinmux
+ * I/O I2C_MASTER_A I2C_MASTER_B I2C_SLAVE
+ * GPIO_JTAG_TMS SCK_A REG1[12] SCK_A REG1[13]
+ * GPIO_JTAG_TDI SDA_A REG1[12] SDA_A REG1[13]
+ * GPIO_JTAG_TCK SCK_B REG1[16] SCK_A REG1[17]
+ * GPIO_JTAG_TDO SDA_B REG1[20] SDA_A REG1[21]
+ * GPIOB_0 SCK_B REG2[5] SCK_A REG2[6]
+ * GPIOB_1 SDA_B REG2[2] SDA_A REG2[3]
+ * GPIOB_2 SCK_A REGS[13] SCK_A REG2[14]
+ * GPIOB_3 SDA_A REG2[9] SDA_A REG2[10]
+ * GPIOC_13 SCK_B REG3[28] SCK_A REG3[29]
+ * GPIOC_14 SDA_B REG3[25] SDA_A REG3[26]
+ * GPIOC_21 SCK_A REG7[9] SCK_A REG7[10]
+ * GPIOC_22 SDA_A REG7[6] SDA_A REG7[7]
+ * GPIOE_16 SCK_B REG5[27] SCK_A REG5[28]
+ * GPIOE_17 SDA_B REG5[25] SDA_A REG5[26]
+*/
+
+/*i2c master a*/
+
+
+#define MESON_I2C_MASTER_A_GPIOZ_17_REG (PERIPHS_PIN_MUX_9)
+#define MESON_I2C_MASTER_A_GPIOZ_17_BIT (1<<7)
+#define MESON_I2C_MASTER_A_GPIOZ_18_REG (PERIPHS_PIN_MUX_9)
+#define MESON_I2C_MASTER_A_GPIOZ_18_BIT (1<<8)
+
+#define MESON_I2C_MASTER_A_GPIOW_0_REG (PERIPHS_PIN_MUX_5)
+#define MESON_I2C_MASTER_A_GPIOW_0_BIT (1<<22)
+#define MESON_I2C_MASTER_A_GPIOW_1_REG (PERIPHS_PIN_MUX_5)
+#define MESON_I2C_MASTER_A_GPIOW_1_BIT (1<<23)
+
+/*i2c master b*/
+
+
+#define MESON_I2C_MASTER_B_GPIOH_3_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_B_GPIOH_3_BIT (1<<6)
+#define MESON_I2C_MASTER_B_GPIOH_4_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_B_GPIOH_4_BIT (1<<7)
+
+#define MESON_I2C_MASTER_B_GPIOY_12_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_B_GPIOY_12_BIT (1<<14)
+#define MESON_I2C_MASTER_B_GPIOY_13_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_B_GPIOY_13_BIT (1<<15)
+
+/*i2c master c*/
+#define MESON_I2C_MASTER_C_GPIOY_7_REG (PERIPHS_PIN_MUX_4)
+#define MESON_I2C_MASTER_C_GPIOY_7_BIT (1<<28)
+#define MESON_I2C_MASTER_C_GPIOY_8_REG (PERIPHS_PIN_MUX_4)
+#define MESON_I2C_MASTER_C_GPIOY_8_BIT (1<<29)
+
+#define MESON_I2C_MASTER_C_GPIOX_0_REG (PERIPHS_PIN_MUX_1)
+#define MESON_I2C_MASTER_C_GPIOX_0_BIT (1<<22)
+#define MESON_I2C_MASTER_C_GPIOX_1_REG (PERIPHS_PIN_MUX_1)
+#define MESON_I2C_MASTER_C_GPIOX_1_BIT (1<<23)
+
+/*i2c master d*/
+
+
+#define MESON_I2C_MASTER_D_GPIOY_10_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_D_GPIOY_10_BIT (1<<10)
+#define MESON_I2C_MASTER_D_GPIOY_11_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_D_GPIOY_11_BIT (1<<11)
+
+#define MESON_I2C_MASTER_D_GPIOH_5_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_D_GPIOH_5_BIT (1<<23)
+#define MESON_I2C_MASTER_D_GPIOH_6_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_D_GPIOH_6_BIT (1<<24)
+
+/*i2c master AO*/
+
+
+#define MESON_I2C_MASTER_AO_GPIOAO_4_REG (P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */
+#define MESON_I2C_MASTER_AO_GPIOAO_4_BIT (1<<8)
+#define MESON_I2C_MASTER_AO_GPIOAO_5_REG (P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */
+#define MESON_I2C_MASTER_AO_GPIOAO_5_BIT (1<<9)
+
+/*i2c slave*/
+#define MESON_I2C_SLAVE_JTAG_TMS_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TMS_BIT (1<<13)
+#define MESON_I2C_SLAVE_JTAG_TDI_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TDI_BIT (1<<13)
+
+#define MESON_I2C_SLAVE_GPIOB_2_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_2_BIT (1<<14)
+#define MESON_I2C_SLAVE_GPIOB_3_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_3_BIT (1<<10)
+
+#define MESON_I2C_SLAVE_GPIOC_21_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_7)
+#define MESON_I2C_SLAVE_GPIOC_21_BIT (1<<10)
+#define MESON_I2C_SLAVE_GPIOC_22_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_7)
+#define MESON_I2C_SLAVE_GPIOC_22_BIT (1<<7)
+
+#define MESON_I2C_SLAVE_JTAG_TCK_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TCK_BIT (1<<17)
+#define MESON_I2C_SLAVE_JTAG_TDO_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TDO_BIT (1<<21)
+
+#define MESON_I2C_SLAVE_GPIOB_0_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_0_BIT (1<<6)
+#define MESON_I2C_SLAVE_GPIOB_1_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_1_BIT (1<<3)
+
+#define MESON_I2C_SLAVE_GPIOC_13_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_3)
+#define MESON_I2C_SLAVE_GPIOC_13_BIT (1<<29)
+#define MESON_I2C_SLAVE_GPIOC_14_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_3)
+#define MESON_I2C_SLAVE_GPIOC_14_BIT (1<<26)
+
+#define MESON_I2C_SLAVE_GPIOC_16_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_5)
+#define MESON_I2C_SLAVE_GPIOC_16_BIT (1<<28)
+#define MESON_I2C_SLAVE_GPIOC_17_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_5)
+#define MESON_I2C_SLAVE_GPIOC_17_BIT (1<<26)
+
+
+#define AML_I2C_SPPED_50K 50000
+#define AML_I2C_SPPED_100K 100000
+#define AML_I2C_SPPED_200K 200000
+#define AML_I2C_SPPED_300K 300000
+#define AML_I2C_SPPED_400K 400000
+
+struct aml_pinmux_reg_bit {
+ unsigned long scl_reg;
+ unsigned long sda_reg;
+ unsigned int scl_bit;
+ unsigned int sda_bit;
+};
+
+struct aml_i2c_platform{
+ unsigned int slave_addr;/*7bit addr*/
+ unsigned int wait_count;/*i2c wait ack timeout =
+ wait_count * wait_ack_interval */
+ unsigned int wait_ack_interval;
+ unsigned int wait_read_interval;
+ unsigned int wait_xfer_interval;
+ unsigned int master_no;
+ unsigned int use_pio;/*0: hardware i2c, 1: manual pio i2c*/
+ unsigned int master_i2c_speed;
+
+ /* only need 1 i2c master to comunicate with several devices,
+ * should I prepare 2 master interface to use simultaneously?*/
+ struct resource * resource;
+ struct aml_pinmux_reg_bit master_ao_pinmux;
+ struct aml_pinmux_reg_bit master_a_pinmux;
+ struct aml_pinmux_reg_bit master_b_pinmux;
+ struct aml_pinmux_reg_bit master_c_pinmux;
+ struct aml_pinmux_reg_bit master_d_pinmux;
+
+ struct aml_pinmux_reg_bit slave_reg_bit;
+};
+
+/**************i2c software gpio***************/
+
+#define MESON_I2C_PREG_GPIOC_OE CBUS_REG_ADDR(PREG_FGPIO_EN_N)
+#define MESON_I2C_PREG_GPIOC_OUTLVL CBUS_REG_ADDR(PREG_FGPIO_O)
+#define MESON_I2C_PREG_GPIOC_INLVL CBUS_REG_ADDR(PREG_FGPIO_I)
+
+#define MESON_I2C_PREG_GPIOE_OE CBUS_REG_ADDR(PREG_HGPIO_EN_N)
+#define MESON_I2C_PREG_GPIOE_OUTLVL CBUS_REG_ADDR(PREG_HGPIO_O)
+#define MESON_I2C_PREG_GPIOE_INLVL CBUS_REG_ADDR(PREG_HGPIO_I)
+
+#define MESON_I2C_PREG_GPIOA_OE CBUS_REG_ADDR(PREG_EGPIO_EN_N)
+#define MESON_I2C_PREG_GPIOA_OUTLVL CBUS_REG_ADDR(PREG_EGPIO_O)
+#define MESON_I2C_PREG_GPIOA_INLVL CBUS_REG_ADDR(PREG_EGPIO_I)
+
+struct aml_sw_i2c_pins
+{
+ unsigned int scl_reg_out;
+ unsigned int scl_reg_in;
+ unsigned int scl_bit;
+ unsigned int scl_oe;
+ unsigned int sda_reg_out;
+ unsigned int sda_reg_in;
+ unsigned int sda_bit;
+ unsigned int sda_oe;
+};
+
+
+struct aml_sw_i2c_platform {
+ struct aml_sw_i2c_pins sw_pins;
+
+ /* local settings */
+ int udelay; /* half clock cycle time in us,
+ minimum 2 us for fast-mode I2C,
+ minimum 5 us for standard-mode I2C and SMBus,
+ maximum 50 us for SMBus */
+ int timeout; /* in jiffies */
+};
+
+
+#endif //__AML_MACH_I2C__
+
+
diff --git a/arch/arm/include/asm/arch-c1/io.h b/arch/arm/include/asm/arch-c1/io.h
new file mode 100644
index 0000000..fd3981a
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/io.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __MACH_MESSON_REGS_IO_H
+#define __MACH_MESSON_REGS_IO_H
+
+#ifndef __ASSEMBLY__
+
+#include <asm/io.h>
+#define IO_CBUS_BASE (0xFFD00000L)
+#define IO_AXI_BUS_BASE (0xFFB00000L) /* gpv */
+#define IO_AHB_BUS_BASE (0xFF500000L) /* usb0 */
+#define IO_APB_BUS_BASE (0xFFFC0000L) /* AHB SRAM, sec/sys ahb? txlx_mem_map.xlsx */
+#define IO_APB_HDMI_BUS_BASE (0xFFE00000L) /* */
+#define IO_VPU_BUS_BASE (0xFF900000L) /* VPU */
+
+#define CBUS_REG_OFFSET(reg) ((reg) << 2)
+#define CBUS_REG_ADDR(reg) (IO_CBUS_BASE + CBUS_REG_OFFSET(reg))
+
+#define AXI_REG_OFFSET(reg) ((reg) << 2)
+#define AXI_REG_ADDR(reg) (IO_AXI_BUS_BASE + AXI_REG_OFFSET(reg))
+
+#define AHB_REG_OFFSET(reg) ((reg) << 2)
+#define AHB_REG_ADDR(reg) (IO_AHB_BUS_BASE + AHB_REG_OFFSET(reg))
+
+#define VPU_REG_OFFSET(reg) ((reg) << 2)
+#define VPU_REG_ADDR(reg) (IO_VPU_BUS_BASE + VPU_REG_OFFSET(reg))
+
+
+#define APB_REG_OFFSET(reg) (reg)
+#define APB_REG_ADDR(reg) (IO_APB_BUS_BASE + APB_REG_OFFSET(reg))
+#define APB_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0)
+
+#define APB_HDMI_REG_OFFSET(reg) (reg)
+#define APB_HDMI_REG_ADDR(reg) (IO_APB_HDMI_BUS_BASE + APB_HDMI_REG_OFFSET(reg))
+#define APB_HDMI_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0)
+
+
+#define WRITE_CBUS_REG(reg, val) __raw_writel(val, CBUS_REG_ADDR(reg))
+#define READ_CBUS_REG(reg) (__raw_readl(CBUS_REG_ADDR(reg)))
+#define WRITE_CBUS_REG_BITS(reg, val, start, len) \
+ WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_CBUS_REG_BITS(reg, start, len) \
+ ((READ_CBUS_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)&(~(mask))))
+#define SET_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)|(mask)))
+
+#define WRITE_AXI_REG(reg, val) __raw_writel(val, AXI_REG_ADDR(reg))
+#define READ_AXI_REG(reg) (__raw_readl(AXI_REG_ADDR(reg)))
+#define WRITE_AXI_REG_BITS(reg, val, start, len) \
+ WRITE_AXI_REG(reg, (READ_AXI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_AXI_REG_BITS(reg, start, len) \
+ ((READ_AXI_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)&(~(mask))))
+#define SET_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)|(mask)))
+
+#define WRITE_AHB_REG(reg, val) __raw_writel(val, AHB_REG_ADDR(reg))
+#define READ_AHB_REG(reg) (__raw_readl(AHB_REG_ADDR(reg)))
+#define WRITE_AHB_REG_BITS(reg, val, start, len) \
+ WRITE_AHB_REG(reg, (READ_AHB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_AHB_REG_BITS(reg, start, len) \
+ ((READ_AHB_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)&(~(mask))))
+#define SET_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)|(mask)))
+
+#define WRITE_APB_REG(reg, val) __raw_writel(val, APB_REG_ADDR(reg))
+#define READ_APB_REG(reg) (__raw_readl(APB_REG_ADDR(reg)))
+#define WRITE_APB_REG_BITS(reg, val, start, len) \
+ WRITE_APB_REG(reg, (READ_APB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_APB_REG_BITS(reg, start, len) \
+ ((READ_APB_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)&(~(mask))))
+#define SET_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)|(mask)))
+
+#define WRITE_APB_HDMI_REG(reg, val) __raw_writel(val, APB_HDMI_REG_ADDR(reg))
+#define READ_APB_HDMI_REG(reg) (__raw_readl(APB_HDMI_REG_ADDR(reg)))
+#define WRITE_APB_HDMI_REG_BITS(reg, val, start, len) \
+ WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_APB_HDMI_REG_BITS(reg, start, len) \
+ ((READ_APB_HDMI_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)&(~(mask))))
+#define SET_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)|(mask)))
+
+/* for back compatible alias */
+#define WRITE_MPEG_REG(reg, val) \
+ WRITE_CBUS_REG(reg, val)
+#define READ_MPEG_REG(reg) \
+ READ_CBUS_REG(reg)
+#define WRITE_MPEG_REG_BITS(reg, val, start, len) \
+ WRITE_CBUS_REG_BITS(reg, val, start, len)
+#define READ_MPEG_REG_BITS(reg, start, len) \
+ READ_CBUS_REG_BITS(reg, start, len)
+#define CLEAR_MPEG_REG_MASK(reg, mask) \
+ CLEAR_CBUS_REG_MASK(reg, mask)
+#define SET_MPEG_REG_MASK(reg, mask) \
+ SET_CBUS_REG_MASK(reg, mask)
+#endif
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-c1/mailbox.h b/arch/arm/include/asm/arch-c1/mailbox.h
new file mode 100644
index 0000000..04ae20f
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/mailbox.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+ /*
+ *
+ * Copyright (C) 2012 Amlogic, Inc.
+ *
+ * Author: Platform-SH@amlogic.com
+ *
+ */
+
+#ifndef __GXBB_MAILBOX_H_
+#define __GXBB_MAILBOX_H_
+
+#define SCPI_CMD_SENSOR_VALUE 0x1C
+#define SCPI_CMD_SET_USR_DATA 0x20
+#define SCPI_CMD_OPEN_SCP_LOG 0xC4
+#define SCPI_CMD_THERMAL_CALIB 0xC5
+
+#define SCPI_CMD_USB_BOOT 0xB0
+#define SCPI_CMD_USB_UNBOOT 0xB1
+#define SCPI_CMD_SDCARD_BOOT 0xB2
+#define SCPI_CMD_CLEAR_BOOT 0xB3
+
+#define SCPI_CMD_REV_PWM_DELT 0x42
+
+#define LOW_PRIORITY 0
+#define HIGH_PRIORITY 1
+
+#define P_SHARE_SRAM_BASE 0xfffa0000
+#define SRAM_SIZE 0x48000
+#define MHU_HIGH_SCP_TO_AP_PAYLOAD (SRAM_SIZE - 0xc00)
+#define MHU_HIGH_AP_TO_SCP_PAYLOAD (MHU_HIGH_SCP_TO_AP_PAYLOAD + 0x200)
+#define MHU_LOW_SCP_TO_AP_PAYLOAD (SRAM_SIZE - 0x1000)
+#define MHU_LOW_AP_TO_SCP_PAYLOAD (MHU_LOW_SCP_TO_AP_PAYLOAD + 0x200)
+
+enum scpi_client_id {
+ SCPI_CL_NONE,
+ SCPI_CL_CLOCKS,
+ SCPI_CL_DVFS,
+ SCPI_CL_POWER,
+ SCPI_CL_THERMAL,
+ SCPI_CL_REMOTE,
+ SCPI_CL_LED_TIMER,
+ SCPI_MAX = 0xff,
+};
+
+enum scpi_error_codes {
+ SCPI_SUCCESS = 0, /* Success */
+ SCPI_ERR_PARAM = 1, /* Invalid parameter(s) */
+ SCPI_ERR_ALIGN = 2, /* Invalid alignment */
+ SCPI_ERR_SIZE = 3, /* Invalid size */
+ SCPI_ERR_HANDLER = 4, /* Invalid handler/callback */
+ SCPI_ERR_ACCESS = 5, /* Invalid access/permission denied */
+ SCPI_ERR_RANGE = 6, /* Value out of range */
+ SCPI_ERR_TIMEOUT = 7, /* Timeout has occurred */
+ SCPI_ERR_NOMEM = 8, /* Invalid memory area or pointer */
+ SCPI_ERR_PWRSTATE = 9, /* Invalid power state */
+ SCPI_ERR_SUPPORT = 10, /* Not supported or disabled */
+ SCPI_ERR_DEVICE = 11, /* Device error */
+ SCPI_ERR_MAX
+};
+
+void open_scp_log(unsigned int channel);
+int thermal_calibration(unsigned int type, unsigned int data);
+int thermal_get_value(unsigned int sensor_id, unsigned int *value);
+int send_usr_data(unsigned int clinet_id, unsigned int *val, unsigned int size);
+void send_pwm_delt(int32_t vcck_delt, int32_t ee_delt);
+ #endif
diff --git a/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_ddr3.h b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_ddr3.h
new file mode 100644
index 0000000..c067367
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_ddr3.h
@@ -0,0 +1,637 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief DDR3U_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_DDR3U_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Train vrefDAC0 During Read Deskew
+ // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] = MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] = SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] = SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] = RFU, must be zero (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero)
+ //
+ //
+ //
+ // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] = PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte
+ // 0x0 = All rank populated with all the byte (tyical configuration)
+ //
+ // MsgMisc[7] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware.
+ // Please reference this revision ID when filing support cases with Synopsys.
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Module Type:
+ // 0x01 = DDR3 unbuffered
+ // 0x02 = Reserved
+ // 0x03 = Reserved
+ // 0x04 = Reserved
+ // 0x05 = Reserved
+ //
+ uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7):
+ // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting)
+ uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ // Total number of DQ bits enabled in PHY
+ uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS.
+ //
+ // If the bit is set to 1, the CS is connected to DRAM.
+ // If the bit is set to 0, the CS is not connected to DRAM.
+ //
+ // CsPresent[0] = CS0 is populated with DRAM
+ // CsPresent[1] = CS1 is populated with DRAM
+ // CsPresent[2] = CS2 is populated with DRAM
+ // CsPresent[3] = CS3 is populated with DRAM
+ // CsPresent[7:4] = Reserved (must be programmed to 0)
+ //
+ //
+ uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 0
+ uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 1
+ uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ // Corresponds to CS[3:0]
+ // 1 = Address Mirror.
+ // 0 = No Address Mirror.
+ uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ // Additional mode bits.
+ //
+ // Bit fields:
+ // [0] SlowAccessMode :
+ // 1 = 2T Address Timing.
+ // 0 = 1T Address Timing.
+ // [7-1] RFU, must be zero
+ uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[10] = RFU, must be zero
+ // SequenceCtrl[11] = RFU, must be zero
+ // SequenceCtrl[12] = RFU, must be zero
+ // SequenceCtrl[13] = RFU, must be zero
+ // SequenceCtrl[15-14] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A
+
+
+
+ uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D training in: Rd2D, Wr2D
+ //
+ // Reserved1E[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1E[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR6
+ // 2 = limit to +/-4 %VDDQ from MR6
+ // …
+ // 15 = limit to +/-30% VDDQ from MR6
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A
+ // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset.
+ uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ // Value of DDR mode register MR0 for all ranks for current pstate
+ uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Value of DDR mode register MR1 for all ranks for current pstate
+ uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ // Value of DDR mode register MR2 for all ranks for current pstate
+ uint8_t Reserved64; // Byte offset 0x64, CSR Addr 0x54032, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved65; // Byte offset 0x65, CSR Addr 0x54032, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6E; // Byte offset 0x6e, CSR Addr 0x54037, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6F; // Byte offset 0x6f, CSR Addr 0x54037, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved71; // Byte offset 0x71, CSR Addr 0x54038, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved72; // Byte offset 0x72, CSR Addr 0x54039, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved73; // Byte offset 0x73, CSR Addr 0x54039, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl0; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl2; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl3; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl4; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl5; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl7; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7C; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7D; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A
+
+ uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A
+
+ uint8_t Reserved8A; // Byte offset 0x8a, CSR Addr 0x54045, Direction=N/A
+
+ uint8_t Reserved8B; // Byte offset 0x8b, CSR Addr 0x54045, Direction=N/A
+
+ uint8_t Reserved8C; // Byte offset 0x8c, CSR Addr 0x54046, Direction=N/A
+
+ uint8_t Reserved8D; // Byte offset 0x8d, CSR Addr 0x54046, Direction=N/A
+
+ uint8_t Reserved8E; // Byte offset 0x8e, CSR Addr 0x54047, Direction=N/A
+
+ uint8_t Reserved8F; // Byte offset 0x8f, CSR Addr 0x54047, Direction=N/A
+
+ uint8_t Reserved90; // Byte offset 0x90, CSR Addr 0x54048, Direction=N/A
+
+ uint8_t Reserved91; // Byte offset 0x91, CSR Addr 0x54048, Direction=N/A
+
+ uint8_t Reserved92; // Byte offset 0x92, CSR Addr 0x54049, Direction=N/A
+
+ uint8_t Reserved93; // Byte offset 0x93, CSR Addr 0x54049, Direction=N/A
+
+ uint8_t Reserved94; // Byte offset 0x94, CSR Addr 0x5404a, Direction=N/A
+
+ uint8_t Reserved95; // Byte offset 0x95, CSR Addr 0x5404a, Direction=N/A
+
+ uint8_t Reserved96; // Byte offset 0x96, CSR Addr 0x5404b, Direction=N/A
+
+ uint8_t Reserved97; // Byte offset 0x97, CSR Addr 0x5404b, Direction=N/A
+
+ uint8_t Reserved98; // Byte offset 0x98, CSR Addr 0x5404c, Direction=N/A
+
+ uint8_t Reserved99; // Byte offset 0x99, CSR Addr 0x5404c, Direction=N/A
+
+ uint8_t Reserved9A; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=N/A
+
+ uint8_t Reserved9B; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=N/A
+
+ uint8_t Reserved9C; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=N/A
+
+ uint8_t Reserved9D; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=N/A
+
+ uint8_t Reserved9E; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=N/A
+
+ uint8_t Reserved9F; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=N/A
+
+ uint8_t ReservedA0; // Byte offset 0xa0, CSR Addr 0x54050, Direction=N/A
+
+ uint8_t ReservedA1; // Byte offset 0xa1, CSR Addr 0x54050, Direction=N/A
+
+ uint8_t ReservedA2; // Byte offset 0xa2, CSR Addr 0x54051, Direction=N/A
+
+ uint8_t ReservedA3; // Byte offset 0xa3, CSR Addr 0x54051, Direction=N/A
+
+} __attribute__ ((packed)) PMU_SMB_DDR3U_1D_t;
diff --git a/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_ddr4.h b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_ddr4.h
new file mode 100644
index 0000000..6dfd4d0
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_ddr4.h
@@ -0,0 +1,2380 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief DDR4U_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_DDR4U_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Train vrefDAC0 During Read Deskew
+ // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] = MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] = SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] = SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D.
+ // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field
+ //
+ // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] = PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte
+ // 0x0 = All rank populated with all the byte (tyical configuration)
+ //
+ // MsgMisc[7] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware.
+ // Please reference this revision ID when filing support cases with Synopsys.
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Module Type:
+ // 0x01 = Reserved
+ // 0x02 = DDR4 unbuffered
+ // 0x03 = Reserved
+ // 0x04 = Reserved
+ // 0x05 = Reserved
+ //
+ uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7):
+ // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting)
+ uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ // Total number of DQ bits enabled in PHY
+ uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS.
+ //
+ // If the bit is set to 1, the CS is connected to DRAM.
+ // If the bit is set to 0, the CS is not connected to DRAM.
+ //
+ // CsPresent[0] = CS0 is populated with DRAM
+ // CsPresent[1] = CS1 is populated with DRAM
+ // CsPresent[2] = CS2 is populated with DRAM
+ // CsPresent[3] = CS3 is populated with DRAM
+ // CsPresent[7:4] = Reserved (must be programmed to 0)
+ //
+ //
+ uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 0
+ uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 1
+ uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ // Corresponds to CS[3:0]
+ // 1 = Address Mirror.
+ // 0 = No Address Mirror.
+ uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ // Additional mode bits.
+ //
+ // Bit fields:
+ // [0] SlowAccessMode :
+ // 1 = 2T Address Timing.
+ // 0 = 1T Address Timing.
+ // [7-1] RFU, must be zero
+ uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[10] = Run Reserved
+ // SequenceCtrl[11] = Run Reserved
+ // SequenceCtrl[12] = Run Reserved
+ // SequenceCtrl[13] = Run Reserved
+ // SequenceCtrl[15-14] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A
+
+
+
+ uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D training in: Rd2D, Wr2D
+ //
+ // Reserved1E[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1E[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR6
+ // 2 = limit to +/-4 %VDDQ from MR6
+ // …
+ // 15 = limit to +/-30% VDDQ from MR6
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A
+ // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset.
+ uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ // Value of DDR mode register MR0 for all ranks for current pstate
+ uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Value of DDR mode register MR1 for all ranks for current pstate
+ uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ // Value of DDR mode register MR2 for all ranks for current pstate
+ uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ // Value of DDR mode register MR3 for all ranks for current pstate
+ uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value of DDR mode register MR4 for all ranks for current pstate
+ uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value of DDR mode register MR5 for all ranks for current pstate
+ uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0.
+ uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // X16 device map. Corresponds to CS[3:0].
+ // X16Present[0] = CS0 is populated with X16 devices
+ // X16Present[1] = CS1 is populated with X16 devices
+ // X16Present[2] = CS2 is populated with X16 devices
+ // X16Present[3] = CS3 is populated with X16 devices
+ // X16Present[7:4] = Reserved (must be programmed to 0)
+ //
+ // Ranks may not contain mixed device types.
+ uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // controls timing of chip select signals when DDR4 gear-down mode is active
+ // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs
+ // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode
+ uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM:
+ // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0
+ // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0
+ // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0
+ uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM:
+ // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1
+ // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1
+ // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1
+ uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM:
+ // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2
+ // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2
+ // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2
+ uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM:
+ // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3
+ // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3
+ // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3
+ uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM:
+ // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4
+ // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4
+ // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4
+ uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM:
+ // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5
+ // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5
+ // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5
+ uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM:
+ // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6
+ // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6
+ // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6
+ uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM:
+ // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7
+ // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7
+ // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7
+ uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices.
+ uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices.
+ uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices.
+ uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices.
+ uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices.
+ uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices.
+ uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices.
+ uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices.
+ uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices.
+ uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices.
+ uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices.
+ uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices.
+ uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices.
+ uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices.
+ uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices.
+ uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices.
+ uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices.
+ uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices.
+ uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices.
+ uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices.
+ uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices.
+ uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices.
+ uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices.
+ uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices.
+ uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices.
+ uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices.
+ uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices.
+ uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices.
+ uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices.
+ uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices.
+ uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices.
+ uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices.
+ uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices.
+ uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices.
+ uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices.
+ uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices.
+ uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices.
+ uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices.
+ uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices.
+ uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices.
+ uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A
+
+ uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A
+
+ uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in
+ // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1).
+ // RdDBI is dynamically disabled in certain training steps,
+ // and so the [RdDBI disabled] CAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_CAS_L[0] == 0: use value in MR0
+ // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2]
+ // Other bits are ignored
+ uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In
+ // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1).
+ // 2tCK write prambles are dynamically disabled in certain training steps,
+ // and so the [1tCK write preamble] WCAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_WCAS_L[0] == 0: use value in MR2
+ // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3]
+ // Other bits are ignored
+ uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In
+ // Contains various options for training DDR4 Devices.
+ //
+ // Bit fields:
+ //
+ // D4Misc[7:1] RFU, must be zero
+ //
+ // D4Misc[0] = protect memory reset
+ // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training.
+ // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training
+} __attribute__ ((packed)) PMU_SMB_DDR4U_1D_t;
diff --git a/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_ddr4_2d.h b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_ddr4_2d.h
new file mode 100644
index 0000000..35b1e23
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_ddr4_2d.h
@@ -0,0 +1,2282 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief DDR4U_2D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_DDR4U_2D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Train vrefDAC0 During Read Deskew
+ // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] = MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] = SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] = SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D.
+ // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field
+ //
+ // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] = PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte
+ // 0x0 = All rank populated with all the byte (tyical configuration)
+ //
+ // MsgMisc[7] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware.
+ // Please reference this revision ID when filing support cases with Synopsys.
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Module Type:
+ // 0x01 = Reserved
+ // 0x02 = DDR4 unbuffered
+ // 0x03 = Reserved
+ // 0x04 = Reserved
+ // 0x05 = Reserved
+ //
+ uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7):
+ // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting)
+ uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ // Total number of DQ bits enabled in PHY
+ uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS.
+ //
+ // If the bit is set to 1, the CS is connected to DRAM.
+ // If the bit is set to 0, the CS is not connected to DRAM.
+ //
+ // CsPresent[0] = CS0 is populated with DRAM
+ // CsPresent[1] = CS1 is populated with DRAM
+ // CsPresent[2] = CS2 is populated with DRAM
+ // CsPresent[3] = CS3 is populated with DRAM
+ // CsPresent[7:4] = Reserved (must be programmed to 0)
+ //
+ //
+ uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 0
+ uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 1
+ uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ // Corresponds to CS[3:0]
+ // 1 = Address Mirror.
+ // 0 = No Address Mirror.
+ uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ // Additional mode bits.
+ //
+ // Bit fields:
+ // [0] SlowAccessMode :
+ // 1 = 2T Address Timing.
+ // 0 = 1T Address Timing.
+ // [7-1] RFU, must be zero
+ uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = RFU, must be zero
+ // SequenceCtrl[2] = RFU, must be zero
+ // SequenceCtrl[3] = RFU, must be zero
+ // SequenceCtrl[4] = RFU, must be zero
+ // SequenceCtrl[5] = Run rd2D - 2d read dqs training
+ // SequenceCtrl[6] = Run wr2D - 2d write dq training
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = RFU, must be zero
+ // SequenceCtrl[9] = RFU, must be zero
+ // SequenceCtrl[10] = RFU, must be zero
+ // SequenceCtrl[11] = RFU, must be zero
+ // SequenceCtrl[12] = RFU, must be zero
+ // SequenceCtrl[13] = RFU, must be zero
+ // SequenceCtrl[15-14] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t RX2D_TrainOpt; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In
+ // Bit fields, if 2D read training enabled, then use these additional options:
+ // [0] DFE
+ // 1 = Run rx2D with DFE
+ // 0 = Run rx2D with DFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5-7] RFU, must be zero
+ //
+ uint8_t TX2D_TrainOpt; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Bit fields, if 2D write training is enabled, then use these additional options:
+ // [0] FFE
+ // 1 = Train tx2D with FFE
+ // 0 = Train tx2D with FFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5] FFE Decision Algorithm Control
+ // 1 = FFE chooses the drive strength that maximizes the average eye-area across the entire phy.
+ // 0 = FFE chooses the drive strength that maximizes the smallest eye across the entire phy.
+ // [6-7] RFU, must be zero
+ //
+ uint8_t Share2DVrefResult; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // Bitmap that designates the phy's vref source for every pstate
+ // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock.
+ // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training.
+ uint8_t Delay_Weight2D; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye.
+ uint8_t Voltage_Weight2D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye.
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D training in: Rd2D, Wr2D
+ //
+ // Reserved1E[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1E[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR6
+ // 2 = limit to +/-4 %VDDQ from MR6
+ // …
+ // 15 = limit to +/-30% VDDQ from MR6
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ uint8_t R0_RxClkDly_Margin; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R0_VrefDac_Margin; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R0_TxDqDly_Margin; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R0_DeviceVref_Margin; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved29; // Byte offset 0x29, CSR Addr 0x54014, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2A; // Byte offset 0x2a, CSR Addr 0x54015, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2B; // Byte offset 0x2b, CSR Addr 0x54015, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2C; // Byte offset 0x2c, CSR Addr 0x54016, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2D; // Byte offset 0x2d, CSR Addr 0x54016, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2E; // Byte offset 0x2e, CSR Addr 0x54017, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2F; // Byte offset 0x2f, CSR Addr 0x54017, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved31; // Byte offset 0x31, CSR Addr 0x54018, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved32; // Byte offset 0x32, CSR Addr 0x54019, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t R1_RxClkDly_Margin; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R1_VrefDac_Margin; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R1_TxDqDly_Margin; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R1_DeviceVref_Margin; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved37; // Byte offset 0x37, CSR Addr 0x5401b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved39; // Byte offset 0x39, CSR Addr 0x5401c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3A; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3B; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3D; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3E; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3F; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t R2_RxClkDly_Margin; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R2_VrefDac_Margin; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R2_TxDqDly_Margin; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R2_DeviceVref_Margin; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved48; // Byte offset 0x48, CSR Addr 0x54024, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved49; // Byte offset 0x49, CSR Addr 0x54024, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4A; // Byte offset 0x4a, CSR Addr 0x54025, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t R3_RxClkDly_Margin; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R3_VrefDac_Margin; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R3_TxDqDly_Margin; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R3_DeviceVref_Margin; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved57; // Byte offset 0x57, CSR Addr 0x5402b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved58; // Byte offset 0x58, CSR Addr 0x5402c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved59; // Byte offset 0x59, CSR Addr 0x5402c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5B; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5C; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In
+ // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D.
+ //
+ // Reserved5D[0-3]: bitTimeControl
+ // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point.
+ // 0 = 1 kilobit per point (legacy behavior)
+ // 1 = 2 kilobits per point
+ // 2 = 4 kilobits per point
+ // …
+ // 15 = 32 megabits per point
+ //
+ // Reserved5D[4]: Exhaustive2D
+ // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior)
+ // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point.
+ //
+ // Reserved5D[5:7]: RFU, must be 0
+ uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ // Value of DDR mode register MR0 for all ranks for current pstate
+ uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Value of DDR mode register MR1 for all ranks for current pstate
+ uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ // Value of DDR mode register MR2 for all ranks for current pstate
+ uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ // Value of DDR mode register MR3 for all ranks for current pstate
+ uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value of DDR mode register MR4 for all ranks for current pstate
+ uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value of DDR mode register MR5 for all ranks for current pstate
+ uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0.
+ uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // X16 device map. Corresponds to CS[3:0].
+ // X16Present[0] = CS0 is populated with X16 devices
+ // X16Present[1] = CS1 is populated with X16 devices
+ // X16Present[2] = CS2 is populated with X16 devices
+ // X16Present[3] = CS3 is populated with X16 devices
+ // X16Present[7:4] = Reserved (must be programmed to 0)
+ //
+ // Ranks may not contain mixed device types.
+ uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // controls timing of chip select signals when DDR4 gear-down mode is active
+ // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs
+ // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode
+ uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM:
+ // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0
+ // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0
+ // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0
+ uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM:
+ // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1
+ // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1
+ // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1
+ uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM:
+ // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2
+ // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2
+ // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2
+ uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM:
+ // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3
+ // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3
+ // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3
+ uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM:
+ // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4
+ // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4
+ // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4
+ uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM:
+ // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5
+ // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5
+ // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5
+ uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM:
+ // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6
+ // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6
+ // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6
+ uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM:
+ // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7
+ // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7
+ // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7
+ uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices.
+ uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices.
+ uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices.
+ uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices.
+ uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices.
+ uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices.
+ uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices.
+ uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices.
+ uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices.
+ uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices.
+ uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices.
+ uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices.
+ uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices.
+ uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices.
+ uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices.
+ uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices.
+ uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices.
+ uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices.
+ uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices.
+ uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices.
+ uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices.
+ uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices.
+ uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices.
+ uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices.
+ uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices.
+ uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices.
+ uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices.
+ uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices.
+ uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices.
+ uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices.
+ uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices.
+ uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices.
+ uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices.
+ uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices.
+ uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices.
+ uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices.
+ uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices.
+ uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices.
+ uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices.
+ uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices.
+ uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A
+
+ uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A
+
+ uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in
+ // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1).
+ // RdDBI is dynamically disabled in certain training steps,
+ // and so the [RdDBI disabled] CAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_CAS_L[0] == 0: use value in MR0
+ // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2]
+ // Other bits are ignored
+ uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In
+ // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1).
+ // 2tCK write prambles are dynamically disabled in certain training steps,
+ // and so the [1tCK write preamble] WCAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_WCAS_L[0] == 0: use value in MR2
+ // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3]
+ // Other bits are ignored
+ uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In
+ // Contains various options for training DDR4 Devices.
+ //
+ // Bit fields:
+ //
+ // D4Misc[7:1] RFU, must be zero
+ //
+ // D4Misc[0] = protect memory reset
+ // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training.
+ // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training
+} __attribute__ ((packed)) PMU_SMB_DDR4U_2D_t;
diff --git a/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_lpddr3.h b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_lpddr3.h
new file mode 100644
index 0000000..6850d06
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_lpddr3.h
@@ -0,0 +1,434 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief LPDDR3_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_LPDDR3_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:5] RFU, must be zero
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] RFU, must be zero
+ //
+ // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[7-6] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t Reserved0D; // Byte offset 0x0d, CSR Addr 0x54006, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = RunWrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[10] = RFU, must be zero
+ // SequenceCtrl[11] = RFU, must be zero
+ // SequenceCtrl[12] = Run LPCA - CA Training
+ // SequenceCtrl[13] = RFU, must be zero
+ // SequenceCtrl[14] = RFU, must be zero
+ // SequenceCtrl[15] = RFU, must be zero
+ //
+ uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t DFIMRLMargin; // Byte offset 0x14, CSR Addr 0x5400a, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ //
+ // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system.
+ uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t UseBroadcastMR; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired.
+ //
+ // 0x0 = Use MR<0:17>_A0 for rank 0 channel A
+ // Use MR<0:17>_B0 for rank 0 channel B
+ // Use MR<0:17>_A1 for rank 1 channel A
+ // Use MR<0:17>_B1 for rank 1 channel B
+ //
+ // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks
+ //
+ // This should be set to 1 for all systems.
+ //
+ // Note: If setting this to 0, only mode register settings related to DRAM partial array self-refresh may be different between the ranks and channels. All other mode register settings must be the same for all ranks and channels.
+ uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t LogToPhyByteMap0; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // Physical Byte associated with Channel A logical Byte 0, depending on LogToPhyByteMap0[7] value:
+ // LogToPhyByteMap0[7]==0: Logical Byte 0 map on Physical Byte 0
+ // LogToPhyByteMap0[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap0[6:0]
+ uint8_t LogToPhyByteMap1; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In
+ // Physical Byte associated with Channel A logical Byte 1, depending on LogToPhyByteMap1[7] value:
+ // LogToPhyByteMap1[7]==0: Logical Byte 1 map on Physical Byte 1
+ // LogToPhyByteMap1[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap1[6:0]
+ uint8_t LogToPhyByteMap2; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Physical Byte associated with Channel A logical Byte 2, depending on LogToPhyByteMap2[7] value:
+ // LogToPhyByteMap2[7]==0: Logical Byte 2 map on Physical Byte 2
+ // LogToPhyByteMap2[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap2[6:0]
+ uint8_t LogToPhyByteMap3; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // Physical Byte associated with Channel A logical Byte 3, depending on LogToPhyByteMap3[7] value:
+ // LogToPhyByteMap3[7]==0: Logical Byte 3 map on Physical Byte 3
+ // LogToPhyByteMap3[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap3[6:0]
+ uint8_t LogToPhyByteMap4; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // Physical Byte associated with Channel B logical Byte 0, depending on LogToPhyByteMap4[7] value:
+ // LogToPhyByteMap4[7]==0: Logical Byte 0 map on Physical Byte 4
+ // LogToPhyByteMap4[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap4[6:0]
+ uint8_t LogToPhyByteMap5; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In
+ // Physical Byte associated with Channel B logical Byte 1, depending on LogToPhyByteMap5[7] value:
+ // LogToPhyByteMap5[7]==0: Logical Byte 1 map on Physical Byte 5
+ // LogToPhyByteMap5[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap5[6:0]
+ uint8_t LogToPhyByteMap6; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Physical Byte associated with Channel B logical Byte 2, depending on LogToPhyByteMap6[7] value:
+ // LogToPhyByteMap6[7]==0: Logical Byte 2 map on Physical Byte 6
+ // LogToPhyByteMap6[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap6[6:0]
+ uint8_t LogToPhyByteMap7; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In
+ // Physical Byte associated with Channel B logical Byte 3, depending on LogToPhyByteMap7[7] value:
+ // LogToPhyByteMap7[7]==0: Logical Byte 3 map on Physical Byte 7
+ // LogToPhyByteMap7[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap7[6:0]
+ uint8_t LogToPhyByteMap8; // Byte offset 0x20, CSR Addr 0x54010, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t LogToPhyByteMap9; // Byte offset 0x21, CSR Addr 0x54010, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t EnabledDQsChA; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Total number of DQ bits enabled in PHY Channel A
+ uint8_t CsPresentChA; // Byte offset 0x23, CSR Addr 0x54011, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel A.
+ //
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChA_RR_1_0; // Byte offset 0x24, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RR_0_1; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_1_0; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_0_1; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_A0; // Byte offset 0x31, CSR Addr 0x54018, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0}
+ uint8_t MR2_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0}
+ uint8_t MR3_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0}
+ uint8_t Reserved34; // Byte offset 0x34, CSR Addr 0x5401a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0}
+ uint8_t MR16_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0}
+ uint8_t MR17_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0}
+ uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_A1; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In
+ // Must be programmed the same as MR1_A0
+ uint8_t MR2_A1; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
+ // Must be programmed the same as MR2_A0
+ uint8_t MR3_A1; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
+ // Must be programmed the same as MR3_A0
+ uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_A1; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
+ // Must be programmed the same as MR11_A0
+ uint8_t MR16_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1}
+ uint8_t MR17_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1}
+ uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved41; // Byte offset 0x41, CSR Addr 0x54020, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved42; // Byte offset 0x42, CSR Addr 0x54021, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved43; // Byte offset 0x43, CSR Addr 0x54021, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved44; // Byte offset 0x44, CSR Addr 0x54022, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t EnabledDQsChB; // Byte offset 0x48, CSR Addr 0x54024, Direction=In
+ // Total number of DQ bits enabled in PHY Channel B
+ uint8_t CsPresentChB; // Byte offset 0x49, CSR Addr 0x54024, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel B.
+ //
+ // 0x0 = No chip selects are populated with DRAM
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChB_RR_1_0; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RR_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_1; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs01 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_1; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_1; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_0; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_1_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_0_1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_B0; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In
+ // Must be programmed the same as MR1_A0
+ uint8_t MR2_B0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In
+ // Must be programmed the same as MR2_A0
+ uint8_t MR3_B0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=In
+ // Must be programmed the same as MR3_A0
+ uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_B0; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=In
+ // Must be programmed the same as MR11_A0
+ uint8_t MR16_B0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0}
+ uint8_t MR17_B0; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0}
+ uint8_t Reserved5E; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_B1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=In
+ // Must be programmed the same as MR1_A0
+ uint8_t MR2_B1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Must be programmed the same as MR2_A0
+ uint8_t MR3_B1; // Byte offset 0x61, CSR Addr 0x54030, Direction=In
+ // Must be programmed the same as MR3_A0
+ uint8_t Reserved62; // Byte offset 0x62, CSR Addr 0x54031, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_B1; // Byte offset 0x63, CSR Addr 0x54031, Direction=In
+ // Must be programmed the same as MR11_A0
+ uint8_t MR16_B1; // Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1}
+ uint8_t MR17_B1; // Byte offset 0x65, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1}
+ uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+} __attribute__ ((packed)) PMU_SMB_LPDDR3_1D_t;
diff --git a/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_lpddr4.h b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_lpddr4.h
new file mode 100644
index 0000000..d194621
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_lpddr4.h
@@ -0,0 +1,557 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief LPDDR4_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_LPDDR4_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Quick Rd2D during 1D Training
+ // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] Disable Boot Clock
+ // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended)
+ // 0x0 = Use Boot Frequency Clock
+ //
+ // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[7-6] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.25*VDDQ, set this field to 0x20.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Lp4 specific options for training.
+ //
+ // Bit fields:
+ //
+ // Lp4Misc[0] Enable dfi_reset_n
+ //
+ // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training.
+ // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin.
+ //
+ // 0x1 = Enables dfi_reset_n to control memreset after training.
+ // PHY Internal registers control memreset during training only.
+ // To ensure that no glitches occur on BP_MEMRESET at the end of training,
+ // The MC must drive dfi_reset_n=1'b1 _prior to starting training_
+ //
+ // Lp4Misc[7-1] RFU, must be zero
+ uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D.
+ //
+ // Reserved0E[0:3]: bitTimeControl
+ // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point.
+ // 0 = 288 bits per point (legacy behavior)
+ // 1 = 576 bits per point
+ // 2 = 1.125 kilobits per point
+ // …
+ // 15 = 9 megabits per point
+ //
+ // Reserved0E[4]: Exhaustive2D
+ // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior)
+ // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point.
+ //
+ // Reserved0E[5:7]: RFU, must be 0
+ uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[11-10] = RFU, must be zero
+ // SequenceCtrl[12] = Run LPCA - CA Training
+ // SequenceCtrl[15-13] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ //
+ // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system.
+ uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired.
+ //
+ // 0x0 = Use MR<0:17>_A0 for rank 0 channel A
+ // Use MR<0:17>_B0 for rank 0 channel B
+ // Use MR<0:17>_A1 for rank 1 channel A
+ // Use MR<0:17>_B1 for rank 1 channel B
+ //
+ // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks
+ //
+ // It is recommended in most LPDDR4 system configurations to set this to 1.
+ //
+ // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels.
+ //
+ uint8_t Lp4Quickboot; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In
+ // Enable Quickboot.
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D stages: Rd2D, Wr2D
+ //
+ // Reserved1A[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1A[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR14
+ // 2 = limit to +/-4 %VDDQ from MR14
+ // …
+ // 15 = limit to +/-30% VDDQ from MR14
+ uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // CA training option bit field
+ // [0] CA VREF Training
+ // 1 = Enable CA VREF Training
+ // 0 = Disable CA VREF Training
+ // [1-7] RFU must be zero
+ uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // X8 mode configuration:
+ // 0x0 = x16 configuration for all devices
+ // 0xF = x8 configuration for all devices
+ // All other values are RFU
+ uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+
+
+
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Total number of DQ bits enabled in PHY Channel A
+ uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel A.
+ //
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0}
+ uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0}
+ uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0}
+ uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0}
+ uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0}
+ uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0}
+ uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0}
+ uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0}
+ uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0}
+ uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0}
+ uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0}
+ uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0}
+ uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1}
+ uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1}
+ uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1}
+ uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1}
+ uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1}
+ uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1}
+ uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1}
+ uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1}
+ uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1}
+ uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1}
+ uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1}
+ uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1}
+ uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In
+ // Terminating Rank for CA bus on Channel A
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A
+
+ uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A
+
+ uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A
+
+ uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A
+
+ uint8_t Reserved4F; // Byte offset 0x4f, CSR Addr 0x54027, Direction=N/A
+
+ uint8_t Reserved50; // Byte offset 0x50, CSR Addr 0x54028, Direction=N/A
+
+ uint8_t Reserved51; // Byte offset 0x51, CSR Addr 0x54028, Direction=N/A
+
+ uint8_t Reserved52; // Byte offset 0x52, CSR Addr 0x54029, Direction=N/A
+
+ uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A
+
+ uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A
+
+ uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A
+
+ uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A
+
+ uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In
+ // Total number of DQ bits enabled in PHY Channel B
+ uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel B.
+ //
+ // 0x0 = No chip selects are populated with DRAM
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs01 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0}
+ uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0}
+ uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0}
+ uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0}
+ uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0}
+ uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0}
+ uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0}
+ uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0}
+ uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0}
+ uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0}
+ uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0}
+ uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0}
+ uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1}
+ uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1}
+ uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1}
+ uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1}
+ uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1}
+ uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1}
+ uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1}
+ uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1}
+ uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1}
+ uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1}
+ uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1}
+ uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1}
+ uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In
+ // Terminating Rank for CA bus on Channel B
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A
+
+ uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A
+
+ uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A
+
+ uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A
+
+ uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A
+
+ uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A
+
+} __attribute__ ((packed)) PMU_SMB_LPDDR4_1D_t;
diff --git a/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_lpddr4_2d.h b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_lpddr4_2d.h
new file mode 100644
index 0000000..c6ab3d3
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/mnPmuSramMsgBlock_lpddr4_2d.h
@@ -0,0 +1,557 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief LPDDR4_2D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_LPDDR4_2D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Quick Rd2D during 1D Training
+ // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] Disable Boot Clock
+ // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended)
+ // 0x0 = Use Boot Frequency Clock
+ //
+ // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[7-6] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.25*VDDQ, set this field to 0x20.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Lp4 specific options for training.
+ //
+ // Bit fields:
+ //
+ // Lp4Misc[0] Enable dfi_reset_n
+ //
+ // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training.
+ // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin.
+ //
+ // 0x1 = Enables dfi_reset_n to control memreset after training.
+ // PHY Internal registers control memreset during training only.
+ // To ensure that no glitches occur on BP_MEMRESET at the end of training,
+ // The MC must drive dfi_reset_n=1'b1 _prior to starting training_
+ //
+ // Lp4Misc[7-1] RFU, must be zero
+ uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D.
+ //
+ // Reserved0E[0:3]: bitTimeControl
+ // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point.
+ // 0 = 288 bits per point (legacy behavior)
+ // 1 = 576 bits per point
+ // 2 = 1.125 kilobits per point
+ // …
+ // 15 = 9 megabits per point
+ //
+ // Reserved0E[4]: Exhaustive2D
+ // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior)
+ // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point.
+ //
+ // Reserved0E[5:7]: RFU, must be 0
+ uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = RFU, must be zero
+ // SequenceCtrl[2] = RFU, must be zero
+ // SequenceCtrl[3] = RFU, must be zero
+ // SequenceCtrl[4] = RFU, must be zero
+ // SequenceCtrl[5] = Run rd2D - 2d read dqs training
+ // SequenceCtrl[6] = Run wr2D - 2d write dq training
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = RFU, must be zero
+ // SequenceCtrl[9] = RFU, must be zero
+ // SequenceCtrl[11-10] = RFU, must be zero
+ // SequenceCtrl[12] = RFU, must be zero
+ // SequenceCtrl[15-13] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ //
+ // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system.
+ uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired.
+ //
+ // 0x0 = Use MR<0:17>_A0 for rank 0 channel A
+ // Use MR<0:17>_B0 for rank 0 channel B
+ // Use MR<0:17>_A1 for rank 1 channel A
+ // Use MR<0:17>_B1 for rank 1 channel B
+ //
+ // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks
+ //
+ // It is recommended in most LPDDR4 system configurations to set this to 1.
+ //
+ // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels.
+ //
+ uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A
+
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D stages: Rd2D, Wr2D
+ //
+ // Reserved1A[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1A[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR14
+ // 2 = limit to +/-4 %VDDQ from MR14
+ // …
+ // 15 = limit to +/-30% VDDQ from MR14
+ uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // CA training option bit field
+ // [0] CA VREF Setting
+ // 1 = Set MR12 from internal register
+ // 0 = Set MR12 from message block
+ // [1-7] RFU must be zero
+ uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // X8 mode configuration:
+ // 0x0 = x16 configuration for all devices
+ // 0xF = x8 configuration for all devices
+ // All other values are RFU
+ uint8_t RX2D_TrainOpt; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In
+ // Bit fields, if 2D read training enabled, then use these additional options:
+ // [0] DFE
+ // 1 = Run rx2D with DFE
+ // 0 = Run rx2D with DFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5-7] RFU, must be zero
+ //
+ uint8_t TX2D_TrainOpt; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Bit fields, if 2D write training is enabled, then use these additional options:
+ // [0] FFE
+ // 1 = Train tx2D with FFE
+ // 0 = Train tx2D with FFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5-7] RFU, must be zero
+ //
+ uint8_t Share2DVrefResult; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In
+ // Bitmap that designates the phy's vref source for every pstate
+ // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock.
+ // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training.
+ uint8_t Delay_Weight2D; // Byte offset 0x20, CSR Addr 0x54010, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye.
+ uint8_t Voltage_Weight2D; // Byte offset 0x21, CSR Addr 0x54010, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Total number of DQ bits enabled in PHY Channel A
+ uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel A.
+ //
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0}
+ uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0}
+ uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0}
+ uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0}
+ uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0}
+ uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0}
+ uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0}
+ uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0}
+ uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0}
+ uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0}
+ uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0}
+ uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0}
+ uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1}
+ uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1}
+ uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1}
+ uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1}
+ uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1}
+ uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1}
+ uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1}
+ uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1}
+ uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1}
+ uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1}
+ uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1}
+ uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1}
+ uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In
+ // Terminating Rank for CA bus on Channel A
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A
+
+ uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A
+
+ uint8_t TrainedVREFDQ_A0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // Trained DQ Vref setting for Ch A Rank 0
+ uint8_t TrainedVREFDQ_A1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // Trained DQ Vref setting for Ch A Rank 1
+ uint8_t RxClkDly_Margin_A0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_A0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_A0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_A0; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t RxClkDly_Margin_A1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_A1; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_A1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_A1; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In
+ // Total number of DQ bits enabled in PHY Channel B
+ uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel B.
+ //
+ // 0x0 = No chip selects are populated with DRAM
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs01 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0}
+ uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0}
+ uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0}
+ uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0}
+ uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0}
+ uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0}
+ uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0}
+ uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0}
+ uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0}
+ uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0}
+ uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0}
+ uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0}
+ uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1}
+ uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1}
+ uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1}
+ uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1}
+ uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1}
+ uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1}
+ uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1}
+ uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1}
+ uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1}
+ uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1}
+ uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1}
+ uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1}
+ uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In
+ // Terminating Rank for CA bus on Channel B
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t TrainedVREFDQ_B0; // Byte offset 0x80, CSR Addr 0x54040, Direction=Out
+ // Trained DQ Vref setting for Ch B Rank 0
+ uint8_t TrainedVREFDQ_B1; // Byte offset 0x81, CSR Addr 0x54040, Direction=Out
+ // Trained DQ Vref setting for Ch B Rank 1
+ uint8_t RxClkDly_Margin_B0; // Byte offset 0x82, CSR Addr 0x54041, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_B0; // Byte offset 0x83, CSR Addr 0x54041, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_B0; // Byte offset 0x84, CSR Addr 0x54042, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_B0; // Byte offset 0x85, CSR Addr 0x54042, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t RxClkDly_Margin_B1; // Byte offset 0x86, CSR Addr 0x54043, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_B1; // Byte offset 0x87, CSR Addr 0x54043, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_B1; // Byte offset 0x88, CSR Addr 0x54044, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_B1; // Byte offset 0x89, CSR Addr 0x54044, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+} __attribute__ ((packed)) PMU_SMB_LPDDR4_2D_t;
diff --git a/arch/arm/include/asm/arch-c1/nand.h b/arch/arm/include/asm/arch-c1/nand.h
new file mode 100644
index 0000000..91484ac
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/nand.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __NAND_H__
+#define __NAND_H__
+#include <asm/arch/cpu_config.h>
+
+#ifndef SD_EMMC_BASE_C
+#define SD_EMMC_BASE_C 0xd0074000
+#endif
+
+#define P_NAND_BASE (SD_EMMC_BASE_C | (1<<11))
+#define P_CLK_CNTL (volatile uint32_t *)(SD_EMMC_BASE_C)
+#define P_NAND_CMD (volatile uint32_t *)(P_NAND_BASE + 0x00)
+#define P_NAND_CFG (volatile uint32_t *)(P_NAND_BASE + 0x04)
+#define P_NAND_DADR (volatile uint32_t *)(P_NAND_BASE + 0x08)
+#define P_NAND_IADR (volatile uint32_t *)(P_NAND_BASE + 0x0c)
+#define P_NAND_BUF (volatile uint32_t *)(P_NAND_BASE + 0x10)
+#define P_NAND_INFO (volatile uint32_t *)(P_NAND_BASE + 0x14)
+#define P_NAND_DC (volatile uint32_t *)(P_NAND_BASE + 0x18)
+#define P_NAND_ADR (volatile uint32_t *)(P_NAND_BASE + 0x1c)
+#define P_NAND_DL (volatile uint32_t *)(P_NAND_BASE + 0x20)
+#define P_NAND_DH (volatile uint32_t *)(P_NAND_BASE + 0x24)
+#define P_NAND_CADR (volatile uint32_t *)(P_NAND_BASE + 0x28)
+#define P_NAND_SADR (volatile uint32_t *)(P_NAND_BASE + 0x2c)
+
+#define CEF (0xf<<10)
+#define CE0 (0xe<<10)
+#define CE1 (0xd<<10)
+#define CE2 (0xb<<10)
+#define CE3 (0x7<<10)
+
+#define IO4 ((0xe<<10)|(1<<18))
+#define IO5 ((0xd<<10)|(1<<18))
+#define IO6 ((0xb<<10)|(1<<18))
+
+#define CLE (0x5<<14)
+#define ALE (0x6<<14)
+#define DWR (0x4<<14)
+#define DRD (0x8<<14)
+#define IDLE (0xc<<14)
+#define RB (1<<20)
+
+#define M2N ((0<<17) | (2<<20) | (1<<19))
+#define N2M ((1<<17) | (2<<20) | (1<<19))
+#define STS ((3<<17) | (2<<20))
+#define ADL ((0<<16) | (3<<20))
+#define ADH ((1<<16) | (3<<20))
+#define AIL ((2<<16) | (3<<20))
+#define AIH ((3<<16) | (3<<20))
+#define ASL ((4<<16) | (3<<20))
+#define ASH ((5<<16) | (3<<20))
+#define SEED ((8<<16) | (3<<20))
+
+// NAND Flash Manufacturer ID Codes
+#define NAND_MFR_TOSHIBA 0x98
+#define NAND_MFR_SAMSUNG 0xec
+#define NAND_MFR_FUJITSU 0x04
+#define NAND_MFR_NATIONAL 0x8f
+#define NAND_MFR_RENESAS 0x07
+#define NAND_MFR_STMICRO 0x20
+#define NAND_MFR_HYNIX 0xad
+#define NAND_MFR_MICRON 0x2c
+#define NAND_MFR_AMD 0x01
+#define NAND_MFR_INTEL 0x89
+#define NAND_MFR_SANDISK 0x45
+#define NAND_MFR_USER 0x100
+#define NAND_MFR_EFUSE 0x101
+
+typedef struct nand_setup {
+ union {
+ uint32_t d32;
+ struct {
+ unsigned cmd:22;
+ unsigned large_page:1; // 22
+ unsigned no_rb:1; // 23 from efuse
+ unsigned a2:1; // 24
+ unsigned reserved25:1; // 25
+ unsigned page_list:1; // 26
+ unsigned sync_mode:2; // 27 from efuse
+ unsigned size:2; // 29 from efuse
+ unsigned active:1; // 31
+ } b;
+ } cfg;
+ uint16_t id;
+ uint16_t max; // id:0x100 user, max:0 disable.
+} nand_setup_t;
+
+typedef struct _nand_cmd{
+ unsigned char type;
+ unsigned char val;
+} nand_cmd_t;
+
+typedef struct _ext_info{
+ uint32_t read_info; //nand_read_info;
+ uint32_t new_type; //new_nand_type;
+ uint32_t page_per_blk; //pages_in_block;
+ uint32_t xlc; //slc=1, mlc=2, tlc=3.
+ uint32_t rsv1[5];
+} ext_info_t;
+
+typedef struct _nand_page0 {
+ nand_setup_t nand_setup; //8
+ unsigned char page_list[16]; //16
+ nand_cmd_t retry_usr[32]; //64 (32 cmd max I/F)
+ ext_info_t ext_info; //64
+} nand_page0_t; //384 bytes max.
+
+//#define NAND_PAGE0_BUF BL1_NAND_BUFF
+#define NAND_PAGE0_BUF (0x1800000)
+#define NAND_PAGE_LIST (NAND_PAGE0_BUF + sizeof(nand_setup_t))
+#define NAND_RETRY_USER (NAND_PAGE_LIST + 16)
+#define NAND_INFO_BUF (NAND_PAGE0_BUF + 512)
+#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1)
+//#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1)
+
+#define ERROR_MOD(mod,num) ((uint32_t)(((mod<<6)|num)))
+#define ERROR_NAND_TIMEOUT ERROR_MOD(2,1) //
+#define ERROR_NAND_ECC ERROR_MOD(2,2) //
+#define ERROR_NAND_MAGIC_WORD ERROR_MOD(2,3) //
+#define ERROR_NAND_INIT_READ ERROR_MOD(2,4) //
+#define ERROR_NAND_BLANK_PAGE ERROR_MOD(2,5) //
+#define ERROR_NAND_UNALIGN_SRC ERROR_MOD(2,6) //
+
+#define NAND_SECTOR_SIZE (512)
+#define NAND_MAX_PAGESIZE (0x4000) //16K
+#define SRC_ALIGN_SIZE (NAND_MAX_PAGESIZE)
+
+#define INFO_BYTE_PER_ECCPAGE (8)
+uint32_t nfio_init(void);
+uint32_t nf_read(uint32_t boot_device, uint32_t src, uint32_t des, uint32_t size);
+#endif /* __NAND_H__ */
+
diff --git a/arch/arm/include/asm/arch-c1/oscring.h b/arch/arm/include/asm/arch-c1/oscring.h
new file mode 100644
index 0000000..a1fa6fc
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/oscring.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __OSCRING_H__
+#define __OSCRING_H__
+
+#define OSCRING_CTL_REG0 SYSCTRL_OSC_RING_CTRL0
+#define OSCRING_CTL_DATA0 0x55555555 /*0:25*/
+#define OSCRING_CTL_REG1 SYSCTRL_OSC_RING_CTRL1
+#define OSCRING_CTL_DATA1 0x55555555 /*0:7*/
+
+#define RING_PWM_VCCK PWMAB_PWM_B
+#define RING_PWM_EE PWMAB_PWM_A
+
+int ring_msr(int index);
+#endif
diff --git a/arch/arm/include/asm/arch-c1/p_register.h b/arch/arm/include/asm/arch-c1/p_register.h
new file mode 100644
index 0000000..24b136d
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/p_register.h
@@ -0,0 +1,4083 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifdef P_REGISTER_H
+#else
+#define P_REGISTER_H
+
+//
+// Reading file: ./REG_LIST_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Reading file: REG_LIST_AUDIO_RTL.h
+//
+//========================================================================
+// AUDIO - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe050000
+// -----------------------------------------------
+#define P_EE_AUDIO_CLK_GATE_EN0 ((volatile uint32_t *)0xfe050000)
+#define P_EE_AUDIO_CLK_GATE_EN1 ((volatile uint32_t *)0xfe050004)
+#define P_EE_AUDIO_MCLK_A_CTRL ((volatile uint32_t *)0xfe050008)
+#define P_EE_AUDIO_MCLK_B_CTRL ((volatile uint32_t *)0xfe05000c)
+#define P_EE_AUDIO_MCLK_C_CTRL ((volatile uint32_t *)0xfe050010)
+#define P_EE_AUDIO_MCLK_D_CTRL ((volatile uint32_t *)0xfe050014)
+#define P_EE_AUDIO_MCLK_E_CTRL ((volatile uint32_t *)0xfe050018)
+#define P_EE_AUDIO_MCLK_F_CTRL ((volatile uint32_t *)0xfe05001c)
+#define P_EE_AUDIO_PAD_CTRL0 ((volatile uint32_t *)0xfe050020)
+#define P_EE_AUDIO_PAD_CTRL1 ((volatile uint32_t *)0xfe050024)
+#define P_EE_AUDIO_SW_RESET0 ((volatile uint32_t *)0xfe050028)
+#define P_EE_AUDIO_SW_RESET1 ((volatile uint32_t *)0xfe05002c)
+#define P_EE_AUDIO_CLK81_CTRL ((volatile uint32_t *)0xfe050030)
+#define P_EE_AUDIO_CLK81_EN ((volatile uint32_t *)0xfe050034)
+#define P_EE_AUDIO_MST_A_SCLK_CTRL0 ((volatile uint32_t *)0xfe050040)
+#define P_EE_AUDIO_MST_A_SCLK_CTRL1 ((volatile uint32_t *)0xfe050044)
+#define P_EE_AUDIO_MST_B_SCLK_CTRL0 ((volatile uint32_t *)0xfe050048)
+#define P_EE_AUDIO_MST_B_SCLK_CTRL1 ((volatile uint32_t *)0xfe05004c)
+#define P_EE_AUDIO_MST_C_SCLK_CTRL0 ((volatile uint32_t *)0xfe050050)
+#define P_EE_AUDIO_MST_C_SCLK_CTRL1 ((volatile uint32_t *)0xfe050054)
+#define P_EE_AUDIO_MST_D_SCLK_CTRL0 ((volatile uint32_t *)0xfe050058)
+#define P_EE_AUDIO_MST_D_SCLK_CTRL1 ((volatile uint32_t *)0xfe05005c)
+#define P_EE_AUDIO_MST_E_SCLK_CTRL0 ((volatile uint32_t *)0xfe050060)
+#define P_EE_AUDIO_MST_E_SCLK_CTRL1 ((volatile uint32_t *)0xfe050064)
+#define P_EE_AUDIO_MST_F_SCLK_CTRL0 ((volatile uint32_t *)0xfe050068)
+#define P_EE_AUDIO_MST_F_SCLK_CTRL1 ((volatile uint32_t *)0xfe05006c)
+#define P_EE_AUDIO_MST_DLY_CTRL0 ((volatile uint32_t *)0xfe050070)
+#define P_EE_AUDIO_MST_DLY_CTRL1 ((volatile uint32_t *)0xfe050074)
+#define P_EE_AUDIO_CLK_TDMIN_A_CTRL ((volatile uint32_t *)0xfe050080)
+#define P_EE_AUDIO_CLK_TDMIN_B_CTRL ((volatile uint32_t *)0xfe050084)
+#define P_EE_AUDIO_CLK_TDMIN_C_CTRL ((volatile uint32_t *)0xfe050088)
+#define P_EE_AUDIO_CLK_TDMIN_LB_CTRL ((volatile uint32_t *)0xfe05008c)
+#define P_EE_AUDIO_CLK_TDMOUT_A_CTRL ((volatile uint32_t *)0xfe050090)
+#define P_EE_AUDIO_CLK_TDMOUT_B_CTRL ((volatile uint32_t *)0xfe050094)
+#define P_EE_AUDIO_CLK_TDMOUT_C_CTRL ((volatile uint32_t *)0xfe050098)
+#define P_EE_AUDIO_CLK_SPDIFIN_CTRL ((volatile uint32_t *)0xfe05009c)
+#define P_EE_AUDIO_CLK_SPDIFOUT_CTRL ((volatile uint32_t *)0xfe0500a0)
+#define P_EE_AUDIO_CLK_RESAMPLEA_CTRL ((volatile uint32_t *)0xfe0500a4)
+#define P_EE_AUDIO_CLK_LOCKER_CTRL ((volatile uint32_t *)0xfe0500a8)
+#define P_EE_AUDIO_CLK_PDMIN_CTRL0 ((volatile uint32_t *)0xfe0500ac)
+#define P_EE_AUDIO_CLK_PDMIN_CTRL1 ((volatile uint32_t *)0xfe0500b0)
+#define P_EE_AUDIO_CLK_SPDIFOUT_B_CTRL ((volatile uint32_t *)0xfe0500b4)
+#define P_EE_AUDIO_CLK_RESAMPLEB_CTRL ((volatile uint32_t *)0xfe0500b8)
+#define P_EE_AUDIO_CLK_SPDIFIN_LB_CTRL ((volatile uint32_t *)0xfe0500bc)
+#define P_EE_AUDIO_CLK_EQDRC_CTRL0 ((volatile uint32_t *)0xfe0500c0)
+#define P_EE_AUDIO_VAD_CLK_CTRL ((volatile uint32_t *)0xfe0500c4)
+#define P_EE_AUDIO_EARCTX_CMDC_CLK_CTRL ((volatile uint32_t *)0xfe0500c8)
+#define P_EE_AUDIO_EARCTX_DMAC_CLK_CTRL ((volatile uint32_t *)0xfe0500cc)
+#define P_EE_AUDIO_EARCRX_CMDC_CLK_CTRL ((volatile uint32_t *)0xfe0500d0)
+#define P_EE_AUDIO_EARCRX_DMAC_CLK_CTRL ((volatile uint32_t *)0xfe0500d4)
+#define P_EE_AUDIO_CLK_LOCKERB_CTRL ((volatile uint32_t *)0xfe0500d8)
+#define P_EE_AUDIO_TODDR_A_CTRL0 ((volatile uint32_t *)0xfe050100)
+#define P_EE_AUDIO_TODDR_A_CTRL1 ((volatile uint32_t *)0xfe050104)
+#define P_EE_AUDIO_TODDR_A_START_ADDR ((volatile uint32_t *)0xfe050108)
+#define P_EE_AUDIO_TODDR_A_FINISH_ADDR ((volatile uint32_t *)0xfe05010c)
+#define P_EE_AUDIO_TODDR_A_INT_ADDR ((volatile uint32_t *)0xfe050110)
+#define P_EE_AUDIO_TODDR_A_STATUS1 ((volatile uint32_t *)0xfe050114)
+#define P_EE_AUDIO_TODDR_A_STATUS2 ((volatile uint32_t *)0xfe050118)
+#define P_EE_AUDIO_TODDR_A_START_ADDRB ((volatile uint32_t *)0xfe05011c)
+#define P_EE_AUDIO_TODDR_A_FINISH_ADDRB ((volatile uint32_t *)0xfe050120)
+#define P_EE_AUDIO_TODDR_A_INIT_ADDR ((volatile uint32_t *)0xfe050124)
+#define P_EE_AUDIO_TODDR_A_CTRL2 ((volatile uint32_t *)0xfe050128)
+#define P_EE_AUDIO_TODDR_B_CTRL0 ((volatile uint32_t *)0xfe050140)
+#define P_EE_AUDIO_TODDR_B_CTRL1 ((volatile uint32_t *)0xfe050144)
+#define P_EE_AUDIO_TODDR_B_START_ADDR ((volatile uint32_t *)0xfe050148)
+#define P_EE_AUDIO_TODDR_B_FINISH_ADDR ((volatile uint32_t *)0xfe05014c)
+#define P_EE_AUDIO_TODDR_B_INT_ADDR ((volatile uint32_t *)0xfe050150)
+#define P_EE_AUDIO_TODDR_B_STATUS1 ((volatile uint32_t *)0xfe050154)
+#define P_EE_AUDIO_TODDR_B_STATUS2 ((volatile uint32_t *)0xfe050158)
+#define P_EE_AUDIO_TODDR_B_START_ADDRB ((volatile uint32_t *)0xfe05015c)
+#define P_EE_AUDIO_TODDR_B_FINISH_ADDRB ((volatile uint32_t *)0xfe050160)
+#define P_EE_AUDIO_TODDR_B_INIT_ADDR ((volatile uint32_t *)0xfe050164)
+#define P_EE_AUDIO_TODDR_B_CTRL2 ((volatile uint32_t *)0xfe050168)
+#define P_EE_AUDIO_TODDR_C_CTRL0 ((volatile uint32_t *)0xfe050180)
+#define P_EE_AUDIO_TODDR_C_CTRL1 ((volatile uint32_t *)0xfe050184)
+#define P_EE_AUDIO_TODDR_C_START_ADDR ((volatile uint32_t *)0xfe050188)
+#define P_EE_AUDIO_TODDR_C_FINISH_ADDR ((volatile uint32_t *)0xfe05018c)
+#define P_EE_AUDIO_TODDR_C_INT_ADDR ((volatile uint32_t *)0xfe050190)
+#define P_EE_AUDIO_TODDR_C_STATUS1 ((volatile uint32_t *)0xfe050194)
+#define P_EE_AUDIO_TODDR_C_STATUS2 ((volatile uint32_t *)0xfe050198)
+#define P_EE_AUDIO_TODDR_C_START_ADDRB ((volatile uint32_t *)0xfe05019c)
+#define P_EE_AUDIO_TODDR_C_FINISH_ADDRB ((volatile uint32_t *)0xfe0501a0)
+#define P_EE_AUDIO_TODDR_C_INIT_ADDR ((volatile uint32_t *)0xfe0501a4)
+#define P_EE_AUDIO_TODDR_C_CTRL2 ((volatile uint32_t *)0xfe0501a8)
+#define P_EE_AUDIO_FRDDR_A_CTRL0 ((volatile uint32_t *)0xfe0501c0)
+#define P_EE_AUDIO_FRDDR_A_CTRL1 ((volatile uint32_t *)0xfe0501c4)
+#define P_EE_AUDIO_FRDDR_A_START_ADDR ((volatile uint32_t *)0xfe0501c8)
+#define P_EE_AUDIO_FRDDR_A_FINISH_ADDR ((volatile uint32_t *)0xfe0501cc)
+#define P_EE_AUDIO_FRDDR_A_INT_ADDR ((volatile uint32_t *)0xfe0501d0)
+#define P_EE_AUDIO_FRDDR_A_STATUS1 ((volatile uint32_t *)0xfe0501d4)
+#define P_EE_AUDIO_FRDDR_A_STATUS2 ((volatile uint32_t *)0xfe0501d8)
+#define P_EE_AUDIO_FRDDR_A_START_ADDRB ((volatile uint32_t *)0xfe0501dc)
+#define P_EE_AUDIO_FRDDR_A_FINISH_ADDRB ((volatile uint32_t *)0xfe0501e0)
+#define P_EE_AUDIO_FRDDR_A_INIT_ADDR ((volatile uint32_t *)0xfe0501e4)
+#define P_EE_AUDIO_FRDDR_A_CTRL2 ((volatile uint32_t *)0xfe0501e8)
+#define P_EE_AUDIO_FRDDR_B_CTRL0 ((volatile uint32_t *)0xfe050200)
+#define P_EE_AUDIO_FRDDR_B_CTRL1 ((volatile uint32_t *)0xfe050204)
+#define P_EE_AUDIO_FRDDR_B_START_ADDR ((volatile uint32_t *)0xfe050208)
+#define P_EE_AUDIO_FRDDR_B_FINISH_ADDR ((volatile uint32_t *)0xfe05020c)
+#define P_EE_AUDIO_FRDDR_B_INT_ADDR ((volatile uint32_t *)0xfe050210)
+#define P_EE_AUDIO_FRDDR_B_STATUS1 ((volatile uint32_t *)0xfe050214)
+#define P_EE_AUDIO_FRDDR_B_STATUS2 ((volatile uint32_t *)0xfe050218)
+#define P_EE_AUDIO_FRDDR_B_START_ADDRB ((volatile uint32_t *)0xfe05021c)
+#define P_EE_AUDIO_FRDDR_B_FINISH_ADDRB ((volatile uint32_t *)0xfe050220)
+#define P_EE_AUDIO_FRDDR_B_INIT_ADDR ((volatile uint32_t *)0xfe050224)
+#define P_EE_AUDIO_FRDDR_B_CTRL2 ((volatile uint32_t *)0xfe050228)
+#define P_EE_AUDIO_FRDDR_C_CTRL0 ((volatile uint32_t *)0xfe050240)
+#define P_EE_AUDIO_FRDDR_C_CTRL1 ((volatile uint32_t *)0xfe050244)
+#define P_EE_AUDIO_FRDDR_C_START_ADDR ((volatile uint32_t *)0xfe050248)
+#define P_EE_AUDIO_FRDDR_C_FINISH_ADDR ((volatile uint32_t *)0xfe05024c)
+#define P_EE_AUDIO_FRDDR_C_INT_ADDR ((volatile uint32_t *)0xfe050250)
+#define P_EE_AUDIO_FRDDR_C_STATUS1 ((volatile uint32_t *)0xfe050254)
+#define P_EE_AUDIO_FRDDR_C_STATUS2 ((volatile uint32_t *)0xfe050258)
+#define P_EE_AUDIO_FRDDR_C_START_ADDRB ((volatile uint32_t *)0xfe05025c)
+#define P_EE_AUDIO_FRDDR_C_FINISH_ADDRB ((volatile uint32_t *)0xfe050260)
+#define P_EE_AUDIO_FRDDR_C_INIT_ADDR ((volatile uint32_t *)0xfe050264)
+#define P_EE_AUDIO_FRDDR_C_CTRL2 ((volatile uint32_t *)0xfe050268)
+#define P_EE_AUDIO_ARB_CTRL ((volatile uint32_t *)0xfe050280)
+#define P_EE_AUDIO_LB_A_CTRL0 ((volatile uint32_t *)0xfe0502c0)
+#define P_EE_AUDIO_LB_A_CTRL1 ((volatile uint32_t *)0xfe0502c4)
+#define P_EE_AUDIO_LB_A_CTRL2 ((volatile uint32_t *)0xfe0502c8)
+#define P_EE_AUDIO_LB_A_CTRL3 ((volatile uint32_t *)0xfe0502cc)
+#define P_EE_AUDIO_LB_A_DAT_CH_ID0 ((volatile uint32_t *)0xfe0502d0)
+#define P_EE_AUDIO_LB_A_DAT_CH_ID1 ((volatile uint32_t *)0xfe0502d4)
+#define P_EE_AUDIO_LB_A_DAT_CH_ID2 ((volatile uint32_t *)0xfe0502d8)
+#define P_EE_AUDIO_LB_A_DAT_CH_ID3 ((volatile uint32_t *)0xfe0502dc)
+#define P_EE_AUDIO_LB_A_LB_CH_ID0 ((volatile uint32_t *)0xfe0502e0)
+#define P_EE_AUDIO_LB_A_LB_CH_ID1 ((volatile uint32_t *)0xfe0502e4)
+#define P_EE_AUDIO_LB_A_LB_CH_ID2 ((volatile uint32_t *)0xfe0502e8)
+#define P_EE_AUDIO_LB_A_LB_CH_ID3 ((volatile uint32_t *)0xfe0502ec)
+#define P_EE_AUDIO_LB_A_STS ((volatile uint32_t *)0xfe0502f0)
+#define P_EE_AUDIO_TDMIN_A_CTRL ((volatile uint32_t *)0xfe050300)
+#define P_EE_AUDIO_TDMIN_A_SWAP0 ((volatile uint32_t *)0xfe050304)
+#define P_EE_AUDIO_TDMIN_A_MASK0 ((volatile uint32_t *)0xfe050308)
+#define P_EE_AUDIO_TDMIN_A_MASK1 ((volatile uint32_t *)0xfe05030c)
+#define P_EE_AUDIO_TDMIN_A_MASK2 ((volatile uint32_t *)0xfe050310)
+#define P_EE_AUDIO_TDMIN_A_MASK3 ((volatile uint32_t *)0xfe050314)
+#define P_EE_AUDIO_TDMIN_A_STAT ((volatile uint32_t *)0xfe050318)
+#define P_EE_AUDIO_TDMIN_A_MUTE_VAL ((volatile uint32_t *)0xfe05031c)
+#define P_EE_AUDIO_TDMIN_A_MUTE0 ((volatile uint32_t *)0xfe050320)
+#define P_EE_AUDIO_TDMIN_A_MUTE1 ((volatile uint32_t *)0xfe050324)
+#define P_EE_AUDIO_TDMIN_A_MUTE2 ((volatile uint32_t *)0xfe050328)
+#define P_EE_AUDIO_TDMIN_A_MUTE3 ((volatile uint32_t *)0xfe05032c)
+#define P_EE_AUDIO_TDMIN_B_CTRL ((volatile uint32_t *)0xfe050340)
+#define P_EE_AUDIO_TDMIN_B_SWAP0 ((volatile uint32_t *)0xfe050344)
+#define P_EE_AUDIO_TDMIN_B_MASK0 ((volatile uint32_t *)0xfe050348)
+#define P_EE_AUDIO_TDMIN_B_MASK1 ((volatile uint32_t *)0xfe05034c)
+#define P_EE_AUDIO_TDMIN_B_MASK2 ((volatile uint32_t *)0xfe050350)
+#define P_EE_AUDIO_TDMIN_B_MASK3 ((volatile uint32_t *)0xfe050354)
+#define P_EE_AUDIO_TDMIN_B_STAT ((volatile uint32_t *)0xfe050358)
+#define P_EE_AUDIO_TDMIN_B_MUTE_VAL ((volatile uint32_t *)0xfe05035c)
+#define P_EE_AUDIO_TDMIN_B_MUTE0 ((volatile uint32_t *)0xfe050360)
+#define P_EE_AUDIO_TDMIN_B_MUTE1 ((volatile uint32_t *)0xfe050364)
+#define P_EE_AUDIO_TDMIN_B_MUTE2 ((volatile uint32_t *)0xfe050368)
+#define P_EE_AUDIO_TDMIN_B_MUTE3 ((volatile uint32_t *)0xfe05036c)
+#define P_EE_AUDIO_TDMIN_C_CTRL ((volatile uint32_t *)0xfe050380)
+#define P_EE_AUDIO_TDMIN_C_SWAP0 ((volatile uint32_t *)0xfe050384)
+#define P_EE_AUDIO_TDMIN_C_MASK0 ((volatile uint32_t *)0xfe050388)
+#define P_EE_AUDIO_TDMIN_C_MASK1 ((volatile uint32_t *)0xfe05038c)
+#define P_EE_AUDIO_TDMIN_C_MASK2 ((volatile uint32_t *)0xfe050390)
+#define P_EE_AUDIO_TDMIN_C_MASK3 ((volatile uint32_t *)0xfe050394)
+#define P_EE_AUDIO_TDMIN_C_STAT ((volatile uint32_t *)0xfe050398)
+#define P_EE_AUDIO_TDMIN_C_MUTE_VAL ((volatile uint32_t *)0xfe05039c)
+#define P_EE_AUDIO_TDMIN_C_MUTE0 ((volatile uint32_t *)0xfe0503a0)
+#define P_EE_AUDIO_TDMIN_C_MUTE1 ((volatile uint32_t *)0xfe0503a4)
+#define P_EE_AUDIO_TDMIN_C_MUTE2 ((volatile uint32_t *)0xfe0503a8)
+#define P_EE_AUDIO_TDMIN_C_MUTE3 ((volatile uint32_t *)0xfe0503ac)
+#define P_EE_AUDIO_TDMIN_LB_CTRL ((volatile uint32_t *)0xfe0503c0)
+#define P_EE_AUDIO_TDMIN_LB_SWAP0 ((volatile uint32_t *)0xfe0503c4)
+#define P_EE_AUDIO_TDMIN_LB_MASK0 ((volatile uint32_t *)0xfe0503c8)
+#define P_EE_AUDIO_TDMIN_LB_MASK1 ((volatile uint32_t *)0xfe0503cc)
+#define P_EE_AUDIO_TDMIN_LB_MASK2 ((volatile uint32_t *)0xfe0503d0)
+#define P_EE_AUDIO_TDMIN_LB_MASK3 ((volatile uint32_t *)0xfe0503d4)
+#define P_EE_AUDIO_TDMIN_LB_STAT ((volatile uint32_t *)0xfe0503d8)
+#define P_EE_AUDIO_TDMIN_LB_MUTE_VAL ((volatile uint32_t *)0xfe0503dc)
+#define P_EE_AUDIO_TDMIN_LB_MUTE0 ((volatile uint32_t *)0xfe0503e0)
+#define P_EE_AUDIO_TDMIN_LB_MUTE1 ((volatile uint32_t *)0xfe0503e4)
+#define P_EE_AUDIO_TDMIN_LB_MUTE2 ((volatile uint32_t *)0xfe0503e8)
+#define P_EE_AUDIO_TDMIN_LB_MUTE3 ((volatile uint32_t *)0xfe0503ec)
+#define P_EE_AUDIO_SPDIFIN_CTRL0 ((volatile uint32_t *)0xfe050400)
+#define P_EE_AUDIO_SPDIFIN_CTRL1 ((volatile uint32_t *)0xfe050404)
+#define P_EE_AUDIO_SPDIFIN_CTRL2 ((volatile uint32_t *)0xfe050408)
+#define P_EE_AUDIO_SPDIFIN_CTRL3 ((volatile uint32_t *)0xfe05040c)
+#define P_EE_AUDIO_SPDIFIN_CTRL4 ((volatile uint32_t *)0xfe050410)
+#define P_EE_AUDIO_SPDIFIN_CTRL5 ((volatile uint32_t *)0xfe050414)
+#define P_EE_AUDIO_SPDIFIN_CTRL6 ((volatile uint32_t *)0xfe050418)
+#define P_EE_AUDIO_SPDIFIN_STAT0 ((volatile uint32_t *)0xfe05041c)
+#define P_EE_AUDIO_SPDIFIN_STAT1 ((volatile uint32_t *)0xfe050420)
+#define P_EE_AUDIO_SPDIFIN_STAT2 ((volatile uint32_t *)0xfe050424)
+#define P_EE_AUDIO_SPDIFIN_MUTE_VAL ((volatile uint32_t *)0xfe050428)
+#define P_EE_AUDIO_RESAMPLEA_CTRL0 ((volatile uint32_t *)0xfe050440)
+#define P_EE_AUDIO_RESAMPLEA_CTRL1 ((volatile uint32_t *)0xfe050444)
+#define P_EE_AUDIO_RESAMPLEA_CTRL2 ((volatile uint32_t *)0xfe050448)
+#define P_EE_AUDIO_RESAMPLEA_CTRL3 ((volatile uint32_t *)0xfe05044c)
+#define P_EE_AUDIO_RESAMPLEA_COEF0 ((volatile uint32_t *)0xfe050450)
+#define P_EE_AUDIO_RESAMPLEA_COEF1 ((volatile uint32_t *)0xfe050454)
+#define P_EE_AUDIO_RESAMPLEA_COEF2 ((volatile uint32_t *)0xfe050458)
+#define P_EE_AUDIO_RESAMPLEA_COEF3 ((volatile uint32_t *)0xfe05045c)
+#define P_EE_AUDIO_RESAMPLEA_COEF4 ((volatile uint32_t *)0xfe050460)
+#define P_EE_AUDIO_RESAMPLEA_STATUS1 ((volatile uint32_t *)0xfe050464)
+#define P_EE_AUDIO_SPDIFOUT_STAT ((volatile uint32_t *)0xfe050480)
+#define P_EE_AUDIO_SPDIFOUT_GAIN0 ((volatile uint32_t *)0xfe050484)
+#define P_EE_AUDIO_SPDIFOUT_GAIN1 ((volatile uint32_t *)0xfe050488)
+#define P_EE_AUDIO_SPDIFOUT_CTRL0 ((volatile uint32_t *)0xfe05048c)
+#define P_EE_AUDIO_SPDIFOUT_CTRL1 ((volatile uint32_t *)0xfe050490)
+#define P_EE_AUDIO_SPDIFOUT_PREAMB ((volatile uint32_t *)0xfe050494)
+#define P_EE_AUDIO_SPDIFOUT_SWAP ((volatile uint32_t *)0xfe050498)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS0 ((volatile uint32_t *)0xfe05049c)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS1 ((volatile uint32_t *)0xfe0504a0)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS2 ((volatile uint32_t *)0xfe0504a4)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS3 ((volatile uint32_t *)0xfe0504a8)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS4 ((volatile uint32_t *)0xfe0504ac)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS5 ((volatile uint32_t *)0xfe0504b0)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS6 ((volatile uint32_t *)0xfe0504b4)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS7 ((volatile uint32_t *)0xfe0504b8)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS8 ((volatile uint32_t *)0xfe0504bc)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS9 ((volatile uint32_t *)0xfe0504c0)
+#define P_EE_AUDIO_SPDIFOUT_CHSTSA ((volatile uint32_t *)0xfe0504c4)
+#define P_EE_AUDIO_SPDIFOUT_CHSTSB ((volatile uint32_t *)0xfe0504c8)
+#define P_EE_AUDIO_SPDIFOUT_MUTE_VAL ((volatile uint32_t *)0xfe0504cc)
+#define P_EE_AUDIO_TDMOUT_A_CTRL0 ((volatile uint32_t *)0xfe050500)
+#define P_EE_AUDIO_TDMOUT_A_CTRL1 ((volatile uint32_t *)0xfe050504)
+#define P_EE_AUDIO_TDMOUT_A_SWAP0 ((volatile uint32_t *)0xfe050508)
+#define P_EE_AUDIO_TDMOUT_A_MASK0 ((volatile uint32_t *)0xfe05050c)
+#define P_EE_AUDIO_TDMOUT_A_MASK1 ((volatile uint32_t *)0xfe050510)
+#define P_EE_AUDIO_TDMOUT_A_MASK2 ((volatile uint32_t *)0xfe050514)
+#define P_EE_AUDIO_TDMOUT_A_MASK3 ((volatile uint32_t *)0xfe050518)
+#define P_EE_AUDIO_TDMOUT_A_STAT ((volatile uint32_t *)0xfe05051c)
+#define P_EE_AUDIO_TDMOUT_A_GAIN0 ((volatile uint32_t *)0xfe050520)
+#define P_EE_AUDIO_TDMOUT_A_GAIN1 ((volatile uint32_t *)0xfe050524)
+#define P_EE_AUDIO_TDMOUT_A_MUTE_VAL ((volatile uint32_t *)0xfe050528)
+#define P_EE_AUDIO_TDMOUT_A_MUTE0 ((volatile uint32_t *)0xfe05052c)
+#define P_EE_AUDIO_TDMOUT_A_MUTE1 ((volatile uint32_t *)0xfe050530)
+#define P_EE_AUDIO_TDMOUT_A_MUTE2 ((volatile uint32_t *)0xfe050534)
+#define P_EE_AUDIO_TDMOUT_A_MUTE3 ((volatile uint32_t *)0xfe050538)
+#define P_EE_AUDIO_TDMOUT_A_MASK_VAL ((volatile uint32_t *)0xfe05053c)
+#define P_EE_AUDIO_TDMOUT_B_CTRL0 ((volatile uint32_t *)0xfe050540)
+#define P_EE_AUDIO_TDMOUT_B_CTRL1 ((volatile uint32_t *)0xfe050544)
+#define P_EE_AUDIO_TDMOUT_B_SWAP0 ((volatile uint32_t *)0xfe050548)
+#define P_EE_AUDIO_TDMOUT_B_MASK0 ((volatile uint32_t *)0xfe05054c)
+#define P_EE_AUDIO_TDMOUT_B_MASK1 ((volatile uint32_t *)0xfe050550)
+#define P_EE_AUDIO_TDMOUT_B_MASK2 ((volatile uint32_t *)0xfe050554)
+#define P_EE_AUDIO_TDMOUT_B_MASK3 ((volatile uint32_t *)0xfe050558)
+#define P_EE_AUDIO_TDMOUT_B_STAT ((volatile uint32_t *)0xfe05055c)
+#define P_EE_AUDIO_TDMOUT_B_GAIN0 ((volatile uint32_t *)0xfe050560)
+#define P_EE_AUDIO_TDMOUT_B_GAIN1 ((volatile uint32_t *)0xfe050564)
+#define P_EE_AUDIO_TDMOUT_B_MUTE_VAL ((volatile uint32_t *)0xfe050568)
+#define P_EE_AUDIO_TDMOUT_B_MUTE0 ((volatile uint32_t *)0xfe05056c)
+#define P_EE_AUDIO_TDMOUT_B_MUTE1 ((volatile uint32_t *)0xfe050570)
+#define P_EE_AUDIO_TDMOUT_B_MUTE2 ((volatile uint32_t *)0xfe050574)
+#define P_EE_AUDIO_TDMOUT_B_MUTE3 ((volatile uint32_t *)0xfe050578)
+#define P_EE_AUDIO_TDMOUT_B_MASK_VAL ((volatile uint32_t *)0xfe05057c)
+#define P_EE_AUDIO_TDMOUT_C_CTRL0 ((volatile uint32_t *)0xfe050580)
+#define P_EE_AUDIO_TDMOUT_C_CTRL1 ((volatile uint32_t *)0xfe050584)
+#define P_EE_AUDIO_TDMOUT_C_SWAP0 ((volatile uint32_t *)0xfe050588)
+#define P_EE_AUDIO_TDMOUT_C_MASK0 ((volatile uint32_t *)0xfe05058c)
+#define P_EE_AUDIO_TDMOUT_C_MASK1 ((volatile uint32_t *)0xfe050590)
+#define P_EE_AUDIO_TDMOUT_C_MASK2 ((volatile uint32_t *)0xfe050594)
+#define P_EE_AUDIO_TDMOUT_C_MASK3 ((volatile uint32_t *)0xfe050598)
+#define P_EE_AUDIO_TDMOUT_C_STAT ((volatile uint32_t *)0xfe05059c)
+#define P_EE_AUDIO_TDMOUT_C_GAIN0 ((volatile uint32_t *)0xfe0505a0)
+#define P_EE_AUDIO_TDMOUT_C_GAIN1 ((volatile uint32_t *)0xfe0505a4)
+#define P_EE_AUDIO_TDMOUT_C_MUTE_VAL ((volatile uint32_t *)0xfe0505a8)
+#define P_EE_AUDIO_TDMOUT_C_MUTE0 ((volatile uint32_t *)0xfe0505ac)
+#define P_EE_AUDIO_TDMOUT_C_MUTE1 ((volatile uint32_t *)0xfe0505b0)
+#define P_EE_AUDIO_TDMOUT_C_MUTE2 ((volatile uint32_t *)0xfe0505b4)
+#define P_EE_AUDIO_TDMOUT_C_MUTE3 ((volatile uint32_t *)0xfe0505b8)
+#define P_EE_AUDIO_TDMOUT_C_MASK_VAL ((volatile uint32_t *)0xfe0505bc)
+//`define EE_AUDIO_POW_DET_CTRL0 10'h180
+//`define EE_AUDIO_POW_DET_CTRL1 10'h181
+//`define EE_AUDIO_POW_DET_TH_HI 10'h182
+//`define EE_AUDIO_POW_DET_TH_LO 10'h183
+//`define EE_AUDIO_POW_DET_VALUE 10'h184
+#define P_EE_AUDIO_SECURITY_CTRL0 ((volatile uint32_t *)0xfe050640)
+#define P_EE_AUDIO_SECURITY_CTRL1 ((volatile uint32_t *)0xfe050644)
+#define P_EE_AUDIO_SPDIFOUT_B_STAT ((volatile uint32_t *)0xfe050680)
+#define P_EE_AUDIO_SPDIFOUT_B_GAIN0 ((volatile uint32_t *)0xfe050684)
+#define P_EE_AUDIO_SPDIFOUT_B_GAIN1 ((volatile uint32_t *)0xfe050688)
+#define P_EE_AUDIO_SPDIFOUT_B_CTRL0 ((volatile uint32_t *)0xfe05068c)
+#define P_EE_AUDIO_SPDIFOUT_B_CTRL1 ((volatile uint32_t *)0xfe050690)
+#define P_EE_AUDIO_SPDIFOUT_B_PREAMB ((volatile uint32_t *)0xfe050694)
+#define P_EE_AUDIO_SPDIFOUT_B_SWAP ((volatile uint32_t *)0xfe050698)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS0 ((volatile uint32_t *)0xfe05069c)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS1 ((volatile uint32_t *)0xfe0506a0)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS2 ((volatile uint32_t *)0xfe0506a4)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS3 ((volatile uint32_t *)0xfe0506a8)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS4 ((volatile uint32_t *)0xfe0506ac)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS5 ((volatile uint32_t *)0xfe0506b0)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS6 ((volatile uint32_t *)0xfe0506b4)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS7 ((volatile uint32_t *)0xfe0506b8)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS8 ((volatile uint32_t *)0xfe0506bc)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS9 ((volatile uint32_t *)0xfe0506c0)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTSA ((volatile uint32_t *)0xfe0506c4)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTSB ((volatile uint32_t *)0xfe0506c8)
+#define P_EE_AUDIO_SPDIFOUT_B_MUTE_VAL ((volatile uint32_t *)0xfe0506cc)
+#define P_EE_AUDIO_TORAM_CTRL0 ((volatile uint32_t *)0xfe050700)
+#define P_EE_AUDIO_TORAM_CTRL1 ((volatile uint32_t *)0xfe050704)
+#define P_EE_AUDIO_TORAM_START_ADDR ((volatile uint32_t *)0xfe050708)
+#define P_EE_AUDIO_TORAM_FINISH_ADDR ((volatile uint32_t *)0xfe05070c)
+#define P_EE_AUDIO_TORAM_INT_ADDR ((volatile uint32_t *)0xfe050710)
+#define P_EE_AUDIO_TORAM_STATUS1 ((volatile uint32_t *)0xfe050714)
+#define P_EE_AUDIO_TORAM_STATUS2 ((volatile uint32_t *)0xfe050718)
+#define P_EE_AUDIO_TORAM_INIT_ADDR ((volatile uint32_t *)0xfe05071c)
+#define P_EE_AUDIO_TOACODEC_CTRL0 ((volatile uint32_t *)0xfe050740)
+#define P_EE_AUDIO_TOHDMITX_CTRL0 ((volatile uint32_t *)0xfe050744)
+#define P_EE_AUDIO_TOVAD_CTRL0 ((volatile uint32_t *)0xfe050748)
+#define P_EE_AUDIO_FRATV_CTRL0 ((volatile uint32_t *)0xfe05074c)
+#define P_EE_AUDIO_RESAMPLEB_CTRL0 ((volatile uint32_t *)0xfe050780)
+#define P_EE_AUDIO_RESAMPLEB_CTRL1 ((volatile uint32_t *)0xfe050784)
+#define P_EE_AUDIO_RESAMPLEB_CTRL2 ((volatile uint32_t *)0xfe050788)
+#define P_EE_AUDIO_RESAMPLEB_CTRL3 ((volatile uint32_t *)0xfe05078c)
+#define P_EE_AUDIO_RESAMPLEB_COEF0 ((volatile uint32_t *)0xfe050790)
+#define P_EE_AUDIO_RESAMPLEB_COEF1 ((volatile uint32_t *)0xfe050794)
+#define P_EE_AUDIO_RESAMPLEB_COEF2 ((volatile uint32_t *)0xfe050798)
+#define P_EE_AUDIO_RESAMPLEB_COEF3 ((volatile uint32_t *)0xfe05079c)
+#define P_EE_AUDIO_RESAMPLEB_COEF4 ((volatile uint32_t *)0xfe0507a0)
+#define P_EE_AUDIO_RESAMPLEB_STATUS1 ((volatile uint32_t *)0xfe0507a4)
+#define P_EE_AUDIO_SPDIFIN_LB_CTRL0 ((volatile uint32_t *)0xfe0507c0)
+#define P_EE_AUDIO_SPDIFIN_LB_CTRL1 ((volatile uint32_t *)0xfe0507c4)
+#define P_EE_AUDIO_SPDIFIN_LB_CTRL6 ((volatile uint32_t *)0xfe0507d8)
+#define P_EE_AUDIO_SPDIFIN_LB_STAT0 ((volatile uint32_t *)0xfe0507dc)
+#define P_EE_AUDIO_SPDIFIN_LB_STAT1 ((volatile uint32_t *)0xfe0507e0)
+#define P_EE_AUDIO_SPDIFIN_LB_MUTE_VAL ((volatile uint32_t *)0xfe0507e8)
+#define P_EE_AUDIO_FRHDMIRX_CTRL0 ((volatile uint32_t *)0xfe050800)
+#define P_EE_AUDIO_FRHDMIRX_CTRL1 ((volatile uint32_t *)0xfe050804)
+#define P_EE_AUDIO_FRHDMIRX_CTRL2 ((volatile uint32_t *)0xfe050808)
+#define P_EE_AUDIO_FRHDMIRX_CTRL3 ((volatile uint32_t *)0xfe05080c)
+#define P_EE_AUDIO_FRHDMIRX_CTRL4 ((volatile uint32_t *)0xfe050810)
+#define P_EE_AUDIO_FRHDMIRX_CTRL5 ((volatile uint32_t *)0xfe050814)
+#define P_EE_AUDIO_FRHDMIRX_STAT0 ((volatile uint32_t *)0xfe050828)
+#define P_EE_AUDIO_FRHDMIRX_STAT1 ((volatile uint32_t *)0xfe05082c)
+#define P_EE_AUDIO_TODDR_D_CTRL0 ((volatile uint32_t *)0xfe050840)
+#define P_EE_AUDIO_TODDR_D_CTRL1 ((volatile uint32_t *)0xfe050844)
+#define P_EE_AUDIO_TODDR_D_START_ADDR ((volatile uint32_t *)0xfe050848)
+#define P_EE_AUDIO_TODDR_D_FINISH_ADDR ((volatile uint32_t *)0xfe05084c)
+#define P_EE_AUDIO_TODDR_D_INT_ADDR ((volatile uint32_t *)0xfe050850)
+#define P_EE_AUDIO_TODDR_D_STATUS1 ((volatile uint32_t *)0xfe050854)
+#define P_EE_AUDIO_TODDR_D_STATUS2 ((volatile uint32_t *)0xfe050858)
+#define P_EE_AUDIO_TODDR_D_START_ADDRB ((volatile uint32_t *)0xfe05085c)
+#define P_EE_AUDIO_TODDR_D_FINISH_ADDRB ((volatile uint32_t *)0xfe050860)
+#define P_EE_AUDIO_TODDR_D_INIT_ADDR ((volatile uint32_t *)0xfe050864)
+#define P_EE_AUDIO_TODDR_D_CTRL2 ((volatile uint32_t *)0xfe050868)
+#define P_EE_AUDIO_FRDDR_D_CTRL0 ((volatile uint32_t *)0xfe050880)
+#define P_EE_AUDIO_FRDDR_D_CTRL1 ((volatile uint32_t *)0xfe050884)
+#define P_EE_AUDIO_FRDDR_D_START_ADDR ((volatile uint32_t *)0xfe050888)
+#define P_EE_AUDIO_FRDDR_D_FINISH_ADDR ((volatile uint32_t *)0xfe05088c)
+#define P_EE_AUDIO_FRDDR_D_INT_ADDR ((volatile uint32_t *)0xfe050890)
+#define P_EE_AUDIO_FRDDR_D_STATUS1 ((volatile uint32_t *)0xfe050894)
+#define P_EE_AUDIO_FRDDR_D_STATUS2 ((volatile uint32_t *)0xfe050898)
+#define P_EE_AUDIO_FRDDR_D_START_ADDRB ((volatile uint32_t *)0xfe05089c)
+#define P_EE_AUDIO_FRDDR_D_FINISH_ADDRB ((volatile uint32_t *)0xfe0508a0)
+#define P_EE_AUDIO_FRDDR_D_INIT_ADDR ((volatile uint32_t *)0xfe0508a4)
+#define P_EE_AUDIO_FRDDR_D_CTRL2 ((volatile uint32_t *)0xfe0508a8)
+#define P_EE_AUDIO_LB_B_CTRL0 ((volatile uint32_t *)0xfe0508c0)
+#define P_EE_AUDIO_LB_B_CTRL1 ((volatile uint32_t *)0xfe0508c4)
+#define P_EE_AUDIO_LB_B_CTRL2 ((volatile uint32_t *)0xfe0508c8)
+#define P_EE_AUDIO_LB_B_CTRL3 ((volatile uint32_t *)0xfe0508cc)
+#define P_EE_AUDIO_LB_B_DAT_CH_ID0 ((volatile uint32_t *)0xfe0508d0)
+#define P_EE_AUDIO_LB_B_DAT_CH_ID1 ((volatile uint32_t *)0xfe0508d4)
+#define P_EE_AUDIO_LB_B_DAT_CH_ID2 ((volatile uint32_t *)0xfe0508d8)
+#define P_EE_AUDIO_LB_B_DAT_CH_ID3 ((volatile uint32_t *)0xfe0508dc)
+#define P_EE_AUDIO_LB_B_LB_CH_ID0 ((volatile uint32_t *)0xfe0508e0)
+#define P_EE_AUDIO_LB_B_LB_CH_ID1 ((volatile uint32_t *)0xfe0508e4)
+#define P_EE_AUDIO_LB_B_LB_CH_ID2 ((volatile uint32_t *)0xfe0508e8)
+#define P_EE_AUDIO_LB_B_LB_CH_ID3 ((volatile uint32_t *)0xfe0508ec)
+#define P_EE_AUDIO_LB_B_STS ((volatile uint32_t *)0xfe0508f0)
+#define P_EE_AUDIO_TODDR_E_CTRL0 ((volatile uint32_t *)0xfe050900)
+#define P_EE_AUDIO_TODDR_E_CTRL1 ((volatile uint32_t *)0xfe050904)
+#define P_EE_AUDIO_TODDR_E_START_ADDR ((volatile uint32_t *)0xfe050908)
+#define P_EE_AUDIO_TODDR_E_FINISH_ADDR ((volatile uint32_t *)0xfe05090c)
+#define P_EE_AUDIO_TODDR_E_INT_ADDR ((volatile uint32_t *)0xfe050910)
+#define P_EE_AUDIO_TODDR_E_STATUS1 ((volatile uint32_t *)0xfe050914)
+#define P_EE_AUDIO_TODDR_E_STATUS2 ((volatile uint32_t *)0xfe050918)
+#define P_EE_AUDIO_TODDR_E_START_ADDRB ((volatile uint32_t *)0xfe05091c)
+#define P_EE_AUDIO_TODDR_E_FINISH_ADDRB ((volatile uint32_t *)0xfe050920)
+#define P_EE_AUDIO_TODDR_E_INIT_ADDR ((volatile uint32_t *)0xfe050924)
+#define P_EE_AUDIO_TODDR_E_CTRL2 ((volatile uint32_t *)0xfe050928)
+#define P_EE_AUDIO_FRDDR_E_CTRL0 ((volatile uint32_t *)0xfe050940)
+#define P_EE_AUDIO_FRDDR_E_CTRL1 ((volatile uint32_t *)0xfe050944)
+#define P_EE_AUDIO_FRDDR_E_START_ADDR ((volatile uint32_t *)0xfe050948)
+#define P_EE_AUDIO_FRDDR_E_FINISH_ADDR ((volatile uint32_t *)0xfe05094c)
+#define P_EE_AUDIO_FRDDR_E_INT_ADDR ((volatile uint32_t *)0xfe050950)
+#define P_EE_AUDIO_FRDDR_E_STATUS1 ((volatile uint32_t *)0xfe050954)
+#define P_EE_AUDIO_FRDDR_E_STATUS2 ((volatile uint32_t *)0xfe050958)
+#define P_EE_AUDIO_FRDDR_E_START_ADDRB ((volatile uint32_t *)0xfe05095c)
+#define P_EE_AUDIO_FRDDR_E_FINISH_ADDRB ((volatile uint32_t *)0xfe050960)
+#define P_EE_AUDIO_FRDDR_E_INIT_ADDR ((volatile uint32_t *)0xfe050964)
+#define P_EE_AUDIO_FRDDR_E_CTRL2 ((volatile uint32_t *)0xfe050968)
+#define P_EE_AUDIO_TDMIN_A_SWAP1 ((volatile uint32_t *)0xfe050980)
+#define P_EE_AUDIO_TDMIN_A_MASK4 ((volatile uint32_t *)0xfe050984)
+#define P_EE_AUDIO_TDMIN_A_MASK5 ((volatile uint32_t *)0xfe050988)
+#define P_EE_AUDIO_TDMIN_A_MASK6 ((volatile uint32_t *)0xfe05098c)
+#define P_EE_AUDIO_TDMIN_A_MASK7 ((volatile uint32_t *)0xfe050990)
+#define P_EE_AUDIO_TDMIN_A_MUTE4 ((volatile uint32_t *)0xfe050994)
+#define P_EE_AUDIO_TDMIN_A_MUTE5 ((volatile uint32_t *)0xfe050998)
+#define P_EE_AUDIO_TDMIN_A_MUTE6 ((volatile uint32_t *)0xfe05099c)
+#define P_EE_AUDIO_TDMIN_A_MUTE7 ((volatile uint32_t *)0xfe0509a0)
+#define P_EE_AUDIO_TDMIN_B_SWAP1 ((volatile uint32_t *)0xfe0509c0)
+#define P_EE_AUDIO_TDMIN_B_MASK4 ((volatile uint32_t *)0xfe0509c4)
+#define P_EE_AUDIO_TDMIN_B_MASK5 ((volatile uint32_t *)0xfe0509c8)
+#define P_EE_AUDIO_TDMIN_B_MASK6 ((volatile uint32_t *)0xfe0509cc)
+#define P_EE_AUDIO_TDMIN_B_MASK7 ((volatile uint32_t *)0xfe0509d0)
+#define P_EE_AUDIO_TDMIN_B_MUTE4 ((volatile uint32_t *)0xfe0509d4)
+#define P_EE_AUDIO_TDMIN_B_MUTE5 ((volatile uint32_t *)0xfe0509d8)
+#define P_EE_AUDIO_TDMIN_B_MUTE6 ((volatile uint32_t *)0xfe0509dc)
+#define P_EE_AUDIO_TDMIN_B_MUTE7 ((volatile uint32_t *)0xfe0509e0)
+#define P_EE_AUDIO_TDMIN_C_SWAP1 ((volatile uint32_t *)0xfe050a00)
+#define P_EE_AUDIO_TDMIN_C_MASK4 ((volatile uint32_t *)0xfe050a04)
+#define P_EE_AUDIO_TDMIN_C_MASK5 ((volatile uint32_t *)0xfe050a08)
+#define P_EE_AUDIO_TDMIN_C_MASK6 ((volatile uint32_t *)0xfe050a0c)
+#define P_EE_AUDIO_TDMIN_C_MASK7 ((volatile uint32_t *)0xfe050a10)
+#define P_EE_AUDIO_TDMIN_C_MUTE4 ((volatile uint32_t *)0xfe050a14)
+#define P_EE_AUDIO_TDMIN_C_MUTE5 ((volatile uint32_t *)0xfe050a18)
+#define P_EE_AUDIO_TDMIN_C_MUTE6 ((volatile uint32_t *)0xfe050a1c)
+#define P_EE_AUDIO_TDMIN_C_MUTE7 ((volatile uint32_t *)0xfe050a20)
+#define P_EE_AUDIO_TDMIN_LB_SWAP1 ((volatile uint32_t *)0xfe050a40)
+#define P_EE_AUDIO_TDMIN_LB_MASK4 ((volatile uint32_t *)0xfe050a44)
+#define P_EE_AUDIO_TDMIN_LB_MASK5 ((volatile uint32_t *)0xfe050a48)
+#define P_EE_AUDIO_TDMIN_LB_MASK6 ((volatile uint32_t *)0xfe050a4c)
+#define P_EE_AUDIO_TDMIN_LB_MASK7 ((volatile uint32_t *)0xfe050a50)
+#define P_EE_AUDIO_TDMIN_LB_MUTE4 ((volatile uint32_t *)0xfe050a54)
+#define P_EE_AUDIO_TDMIN_LB_MUTE5 ((volatile uint32_t *)0xfe050a58)
+#define P_EE_AUDIO_TDMIN_LB_MUTE6 ((volatile uint32_t *)0xfe050a5c)
+#define P_EE_AUDIO_TDMIN_LB_MUTE7 ((volatile uint32_t *)0xfe050a60)
+#define P_EE_AUDIO_TDMOUT_A_CTRL2 ((volatile uint32_t *)0xfe050a80)
+#define P_EE_AUDIO_TDMOUT_A_SWAP1 ((volatile uint32_t *)0xfe050a84)
+#define P_EE_AUDIO_TDMOUT_A_GAIN2 ((volatile uint32_t *)0xfe050a88)
+#define P_EE_AUDIO_TDMOUT_A_GAIN3 ((volatile uint32_t *)0xfe050a8c)
+#define P_EE_AUDIO_TDMOUT_A_MASK4 ((volatile uint32_t *)0xfe050a90)
+#define P_EE_AUDIO_TDMOUT_A_MASK5 ((volatile uint32_t *)0xfe050a94)
+#define P_EE_AUDIO_TDMOUT_A_MASK6 ((volatile uint32_t *)0xfe050a98)
+#define P_EE_AUDIO_TDMOUT_A_MASK7 ((volatile uint32_t *)0xfe050a9c)
+#define P_EE_AUDIO_TDMOUT_A_MUTE4 ((volatile uint32_t *)0xfe050aa0)
+#define P_EE_AUDIO_TDMOUT_A_MUTE5 ((volatile uint32_t *)0xfe050aa4)
+#define P_EE_AUDIO_TDMOUT_A_MUTE6 ((volatile uint32_t *)0xfe050aa8)
+#define P_EE_AUDIO_TDMOUT_A_MUTE7 ((volatile uint32_t *)0xfe050aac)
+#define P_EE_AUDIO_TDMOUT_B_CTRL2 ((volatile uint32_t *)0xfe050ac0)
+#define P_EE_AUDIO_TDMOUT_B_SWAP1 ((volatile uint32_t *)0xfe050ac4)
+#define P_EE_AUDIO_TDMOUT_B_GAIN2 ((volatile uint32_t *)0xfe050ac8)
+#define P_EE_AUDIO_TDMOUT_B_GAIN3 ((volatile uint32_t *)0xfe050acc)
+#define P_EE_AUDIO_TDMOUT_B_MASK4 ((volatile uint32_t *)0xfe050ad0)
+#define P_EE_AUDIO_TDMOUT_B_MASK5 ((volatile uint32_t *)0xfe050ad4)
+#define P_EE_AUDIO_TDMOUT_B_MASK6 ((volatile uint32_t *)0xfe050ad8)
+#define P_EE_AUDIO_TDMOUT_B_MASK7 ((volatile uint32_t *)0xfe050adc)
+#define P_EE_AUDIO_TDMOUT_B_MUTE4 ((volatile uint32_t *)0xfe050ae0)
+#define P_EE_AUDIO_TDMOUT_B_MUTE5 ((volatile uint32_t *)0xfe050ae4)
+#define P_EE_AUDIO_TDMOUT_B_MUTE6 ((volatile uint32_t *)0xfe050ae8)
+#define P_EE_AUDIO_TDMOUT_B_MUTE7 ((volatile uint32_t *)0xfe050aec)
+#define P_EE_AUDIO_TDMOUT_C_CTRL2 ((volatile uint32_t *)0xfe050b00)
+#define P_EE_AUDIO_TDMOUT_C_SWAP1 ((volatile uint32_t *)0xfe050b04)
+#define P_EE_AUDIO_TDMOUT_C_GAIN2 ((volatile uint32_t *)0xfe050b08)
+#define P_EE_AUDIO_TDMOUT_C_GAIN3 ((volatile uint32_t *)0xfe050b0c)
+#define P_EE_AUDIO_TDMOUT_C_MASK4 ((volatile uint32_t *)0xfe050b10)
+#define P_EE_AUDIO_TDMOUT_C_MASK5 ((volatile uint32_t *)0xfe050b14)
+#define P_EE_AUDIO_TDMOUT_C_MASK6 ((volatile uint32_t *)0xfe050b18)
+#define P_EE_AUDIO_TDMOUT_C_MASK7 ((volatile uint32_t *)0xfe050b1c)
+#define P_EE_AUDIO_TDMOUT_C_MUTE4 ((volatile uint32_t *)0xfe050b20)
+#define P_EE_AUDIO_TDMOUT_C_MUTE5 ((volatile uint32_t *)0xfe050b24)
+#define P_EE_AUDIO_TDMOUT_C_MUTE6 ((volatile uint32_t *)0xfe050b28)
+#define P_EE_AUDIO_TDMOUT_C_MUTE7 ((volatile uint32_t *)0xfe050b2c)
+//========================================================================
+// PDM - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051000
+// -----------------------------------------------
+#define P_PDM_CTRL ((volatile uint32_t *)0xfe051000)
+//bit 31: PDM enable.
+//bit 30: invert the PDM_DCLK.
+//bit 29: output mode: 1: 24bits. 0: 32 bits.
+//bit 28: bypass mode. 1: bypass all filter. directly output the PDM input to DDR. 0: normal mode.
+//bit 27~9: not used.
+//bit 16:. PDM Asynchronous FIFO soft reset. write 1 to soft reset AFIFO.
+//bit 15:8 PDM channel reset. 0: to reset each PDM channel. 1: normal mode.
+//bit 7:0. PDM channel enable. each bit for one channel.
+#define P_PDM_HCIC_CTRL1 ((volatile uint32_t *)0xfe051004)
+//bit 31 hcic filter enable. 1 use sinc filter. 0 bypass input to output.
+//bit 29:24. hcic final gain shift parameter.
+//bit 23:16 hcic final gain multiplier.
+//bit 8:4 hcic down sample rate.
+//bit 3:0 hcic stage number. must be between 3 to 9.
+#define P_PDM_HCIC_CTRL2 ((volatile uint32_t *)0xfe051008)
+//Not used.
+#define P_PDM_F1_CTRL ((volatile uint32_t *)0xfe05100c)
+//bit 31 . filter 1 enable.
+//bit 16:15. f1 round mode. 2'b00 : sign bit at bit 49. 28bits output [49:22] round at bit 21. 32bits output [49:18]. 24bits output [49:26]
+// 2'b01 : sign bit at bit 50. 28bits output [50:23] round at bit 22. 32bits output [49:18]. 24bits output [49:26]
+// 2'b10 : sign bit at bit 51. 28bits output [51:24] round at bit 23 32bits output [49:18]. 24bits output [49:26].
+//bit 15:12. filter 1 down sample rate.
+//bit 8:0. filter 1 stage number.
+#define P_PDM_F2_CTRL ((volatile uint32_t *)0xfe051010)
+//bit 31 . filter 2 enable.
+//bit 16:15. f2 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23.
+//bit 15:12. filter 2 down sample rate.
+//bit 8:0. filter 2 stage number.
+#define P_PDM_F3_CTRL ((volatile uint32_t *)0xfe051014)
+//bit 31 . filter 3 enable.
+//bit 16:15. f3 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23.
+//bit 15:12. filter 3 down sample rate.
+//bit 8:0. filter 3 stage number.
+#define P_PDM_HPF_CTRL ((volatile uint32_t *)0xfe051018)
+//bit 31 High pass filter enable.
+//bit 20:16 high pass filter shift steps. 6~19 steps.
+//bit 15:0 high pass filter output factor.
+#define P_PDM_CHAN_CTRL ((volatile uint32_t *)0xfe05101c)
+//bit 31:24. chan3 data sample pointer vs edge of the PDM_DCLK.
+//bit 23:16 chan2 data sample pointer vs edge of the PDM_DCLK.
+//bit 15:8. chan1 data sample pointer vs edge of the PDM_DCLK.
+//bit 7:0 chan0 data sample pointer vs edge of the PDM_DCLK.
+#define P_PDM_CHAN_CTRL1 ((volatile uint32_t *)0xfe051020)
+//bit 31:24. chan7 data sample pointer vs edge of the PDM_DCLK.
+//bit 23:16 chan6 data sample pointer vs edge of the PDM_DCLK.
+//bit 15:8. chan5 data sample pointer vs edge of the PDM_DCLK.
+//bit 7:0 chan4 data sample pointer vs edge of the PDM_DCLK.
+#define P_PDM_COEFF_ADDR ((volatile uint32_t *)0xfe051024)
+// address of the write/read of coeff data.
+#define P_PDM_COEFF_DATA ((volatile uint32_t *)0xfe051028)
+//write/read data to coeff memory.
+#define P_PDM_CLKG_CTRL ((volatile uint32_t *)0xfe05102c)
+// auto clock gating control. 1: disable the clock gating function. the clock will awlays enabled. 0 : use RTL auto clock gating.
+//31:7 not used.
+//bit 6 filt_ctrl module auto clock gating control.
+//bit 5 sinc fifo module auto clock gating control.
+//bit 4 filter module auto clock gating control.
+//bit 3 apb module auto clock gating control.
+//bit 2 coeff memory module auto clock gating control.
+//bit 1 each channel module auto clock gating control.
+//bit 0 cts_pdm_clk auto clock gating control.
+#define P_PDM_STS ((volatile uint32_t *)0xfe051030)
+//bit 1 HPF filter output overflow. means the PCLK is too slow.
+//bit 0 HCIC filter output overflow. means the CTS_PDM_CLK is too slow. can't finished the filter function.
+#define P_PDM_MUTE_VALUE ((volatile uint32_t *)0xfe051034)
+#define P_PDM_MASK_NUM ((volatile uint32_t *)0xfe051038)
+//========================================================================
+// EQ DRC - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe052000
+// -----------------------------------------------
+#define P_AED_COEF_RAM_CNTL ((volatile uint32_t *)0xfe052000)
+#define P_AED_COEF_RAM_DATA ((volatile uint32_t *)0xfe052004)
+#define P_AED_EQ_EN ((volatile uint32_t *)0xfe052008)
+#define P_AED_EQ_TAP_CNTL ((volatile uint32_t *)0xfe05200c)
+#define P_AED_EQ_VOLUME ((volatile uint32_t *)0xfe052010)
+#define P_AED_EQ_VOLUME_SLEW_CNT ((volatile uint32_t *)0xfe052014)
+#define P_AED_MUTE ((volatile uint32_t *)0xfe052018)
+#define P_AED_DRC_CNTL ((volatile uint32_t *)0xfe05201c)
+#define P_AED_DRC_RMS_COEF0 ((volatile uint32_t *)0xfe052020)
+#define P_AED_DRC_RMS_COEF1 ((volatile uint32_t *)0xfe052024)
+#define P_AED_DRC_THD0 ((volatile uint32_t *)0xfe052028)
+#define P_AED_DRC_THD1 ((volatile uint32_t *)0xfe05202c)
+#define P_AED_DRC_THD2 ((volatile uint32_t *)0xfe052030)
+#define P_AED_DRC_THD3 ((volatile uint32_t *)0xfe052034)
+#define P_AED_DRC_THD4 ((volatile uint32_t *)0xfe052038)
+#define P_AED_DRC_K0 ((volatile uint32_t *)0xfe05203c)
+#define P_AED_DRC_K1 ((volatile uint32_t *)0xfe052040)
+#define P_AED_DRC_K2 ((volatile uint32_t *)0xfe052044)
+#define P_AED_DRC_K3 ((volatile uint32_t *)0xfe052048)
+#define P_AED_DRC_K4 ((volatile uint32_t *)0xfe05204c)
+#define P_AED_DRC_K5 ((volatile uint32_t *)0xfe052050)
+#define P_AED_DRC_THD_OUT0 ((volatile uint32_t *)0xfe052054)
+#define P_AED_DRC_THD_OUT1 ((volatile uint32_t *)0xfe052058)
+#define P_AED_DRC_THD_OUT2 ((volatile uint32_t *)0xfe05205c)
+#define P_AED_DRC_THD_OUT3 ((volatile uint32_t *)0xfe052060)
+#define P_AED_DRC_OFFSET ((volatile uint32_t *)0xfe052064)
+#define P_AED_DRC_RELEASE_COEF00 ((volatile uint32_t *)0xfe052068)
+#define P_AED_DRC_RELEASE_COEF01 ((volatile uint32_t *)0xfe05206c)
+#define P_AED_DRC_RELEASE_COEF10 ((volatile uint32_t *)0xfe052070)
+#define P_AED_DRC_RELEASE_COEF11 ((volatile uint32_t *)0xfe052074)
+#define P_AED_DRC_RELEASE_COEF20 ((volatile uint32_t *)0xfe052078)
+#define P_AED_DRC_RELEASE_COEF21 ((volatile uint32_t *)0xfe05207c)
+#define P_AED_DRC_RELEASE_COEF30 ((volatile uint32_t *)0xfe052080)
+#define P_AED_DRC_RELEASE_COEF31 ((volatile uint32_t *)0xfe052084)
+#define P_AED_DRC_RELEASE_COEF40 ((volatile uint32_t *)0xfe052088)
+#define P_AED_DRC_RELEASE_COEF41 ((volatile uint32_t *)0xfe05208c)
+#define P_AED_DRC_RELEASE_COEF50 ((volatile uint32_t *)0xfe052090)
+#define P_AED_DRC_RELEASE_COEF51 ((volatile uint32_t *)0xfe052094)
+#define P_AED_DRC_ATTACK_COEF00 ((volatile uint32_t *)0xfe052098)
+#define P_AED_DRC_ATTACK_COEF01 ((volatile uint32_t *)0xfe05209c)
+#define P_AED_DRC_ATTACK_COEF10 ((volatile uint32_t *)0xfe0520a0)
+#define P_AED_DRC_ATTACK_COEF11 ((volatile uint32_t *)0xfe0520a4)
+#define P_AED_DRC_ATTACK_COEF20 ((volatile uint32_t *)0xfe0520a8)
+#define P_AED_DRC_ATTACK_COEF21 ((volatile uint32_t *)0xfe0520ac)
+#define P_AED_DRC_ATTACK_COEF30 ((volatile uint32_t *)0xfe0520b0)
+#define P_AED_DRC_ATTACK_COEF31 ((volatile uint32_t *)0xfe0520b4)
+#define P_AED_DRC_ATTACK_COEF40 ((volatile uint32_t *)0xfe0520b8)
+#define P_AED_DRC_ATTACK_COEF41 ((volatile uint32_t *)0xfe0520bc)
+#define P_AED_DRC_ATTACK_COEF50 ((volatile uint32_t *)0xfe0520c0)
+#define P_AED_DRC_ATTACK_COEF51 ((volatile uint32_t *)0xfe0520c4)
+#define P_AED_DRC_LOOPBACK_CNTL ((volatile uint32_t *)0xfe0520c8)
+#define P_AED_MDRC_CNTL ((volatile uint32_t *)0xfe0520cc)
+#define P_AED_MDRC_RMS_COEF00 ((volatile uint32_t *)0xfe0520d0)
+#define P_AED_MDRC_RMS_COEF01 ((volatile uint32_t *)0xfe0520d4)
+#define P_AED_MDRC_RELEASE_COEF00 ((volatile uint32_t *)0xfe0520d8)
+#define P_AED_MDRC_RELEASE_COEF01 ((volatile uint32_t *)0xfe0520dc)
+#define P_AED_MDRC_ATTACK_COEF00 ((volatile uint32_t *)0xfe0520e0)
+#define P_AED_MDRC_ATTACK_COEF01 ((volatile uint32_t *)0xfe0520e4)
+#define P_AED_MDRC_THD0 ((volatile uint32_t *)0xfe0520e8)
+#define P_AED_MDRC_K0 ((volatile uint32_t *)0xfe0520ec)
+#define P_AED_MDRC_LOW_GAIN ((volatile uint32_t *)0xfe0520f0)
+#define P_AED_MDRC_OFFSET0 ((volatile uint32_t *)0xfe0520f4)
+#define P_AED_MDRC_RMS_COEF10 ((volatile uint32_t *)0xfe0520f8)
+#define P_AED_MDRC_RMS_COEF11 ((volatile uint32_t *)0xfe0520fc)
+#define P_AED_MDRC_RELEASE_COEF10 ((volatile uint32_t *)0xfe052100)
+#define P_AED_MDRC_RELEASE_COEF11 ((volatile uint32_t *)0xfe052104)
+#define P_AED_MDRC_ATTACK_COEF10 ((volatile uint32_t *)0xfe052108)
+#define P_AED_MDRC_ATTACK_COEF11 ((volatile uint32_t *)0xfe05210c)
+#define P_AED_MDRC_THD1 ((volatile uint32_t *)0xfe052110)
+#define P_AED_MDRC_K1 ((volatile uint32_t *)0xfe052114)
+#define P_AED_MDRC_OFFSET1 ((volatile uint32_t *)0xfe052118)
+#define P_AED_MDRC_MID_GAIN ((volatile uint32_t *)0xfe05211c)
+#define P_AED_MDRC_RMS_COEF20 ((volatile uint32_t *)0xfe052120)
+#define P_AED_MDRC_RMS_COEF21 ((volatile uint32_t *)0xfe052124)
+#define P_AED_MDRC_RELEASE_COEF20 ((volatile uint32_t *)0xfe052128)
+#define P_AED_MDRC_RELEASE_COEF21 ((volatile uint32_t *)0xfe05212c)
+#define P_AED_MDRC_ATTACK_COEF20 ((volatile uint32_t *)0xfe052130)
+#define P_AED_MDRC_ATTACK_COEF21 ((volatile uint32_t *)0xfe052134)
+#define P_AED_MDRC_THD2 ((volatile uint32_t *)0xfe052138)
+#define P_AED_MDRC_K2 ((volatile uint32_t *)0xfe05213c)
+#define P_AED_MDRC_OFFSET2 ((volatile uint32_t *)0xfe052140)
+#define P_AED_MDRC_HIGH_GAIN ((volatile uint32_t *)0xfe052144)
+#define P_AED_ED_CNTL ((volatile uint32_t *)0xfe052148)
+#define P_AED_DC_EN ((volatile uint32_t *)0xfe05214c)
+#define P_AED_ND_LOW_THD ((volatile uint32_t *)0xfe052150)
+#define P_AED_ND_HIGH_THD ((volatile uint32_t *)0xfe052154)
+#define P_AED_ND_CNT_THD ((volatile uint32_t *)0xfe052158)
+#define P_AED_ND_SUM_NUM ((volatile uint32_t *)0xfe05215c)
+#define P_AED_ND_CZ_NUM ((volatile uint32_t *)0xfe052160)
+#define P_AED_ND_SUM_THD0 ((volatile uint32_t *)0xfe052164)
+#define P_AED_ND_SUM_THD1 ((volatile uint32_t *)0xfe052168)
+#define P_AED_ND_CZ_THD0 ((volatile uint32_t *)0xfe05216c)
+#define P_AED_ND_CZ_THD1 ((volatile uint32_t *)0xfe052170)
+#define P_AED_ND_COND_CNTL ((volatile uint32_t *)0xfe052174)
+#define P_AED_ND_RELEASE_COEF0 ((volatile uint32_t *)0xfe052178)
+#define P_AED_ND_RELEASE_COEF1 ((volatile uint32_t *)0xfe05217c)
+#define P_AED_ND_ATTACK_COEF0 ((volatile uint32_t *)0xfe052180)
+#define P_AED_ND_ATTACK_COEF1 ((volatile uint32_t *)0xfe052184)
+#define P_AED_ND_CNTL ((volatile uint32_t *)0xfe052188)
+#define P_AED_MIX0_LL ((volatile uint32_t *)0xfe05218c)
+#define P_AED_MIX0_RL ((volatile uint32_t *)0xfe052190)
+#define P_AED_MIX0_LR ((volatile uint32_t *)0xfe052194)
+#define P_AED_MIX0_RR ((volatile uint32_t *)0xfe052198)
+#define P_AED_CLIP_THD ((volatile uint32_t *)0xfe05219c)
+#define P_AED_CH1_ND_SUM_OUT ((volatile uint32_t *)0xfe0521a0)
+#define P_AED_CH2_ND_SUM_OUT ((volatile uint32_t *)0xfe0521a4)
+#define P_AED_CH1_ND_CZ_OUT ((volatile uint32_t *)0xfe0521a8)
+#define P_AED_CH2_ND_CZ_OUT ((volatile uint32_t *)0xfe0521ac)
+#define P_AED_NOISE_STATUS ((volatile uint32_t *)0xfe0521b0)
+#define P_AED_POW_CURRENT_S0 ((volatile uint32_t *)0xfe0521b4)
+#define P_AED_POW_CURRENT_S1 ((volatile uint32_t *)0xfe0521b8)
+#define P_AED_POW_CURRENT_S2 ((volatile uint32_t *)0xfe0521bc)
+#define P_AED_POW_OUT0 ((volatile uint32_t *)0xfe0521c0)
+#define P_AED_POW_OUT1 ((volatile uint32_t *)0xfe0521c4)
+#define P_AED_POW_OUT2 ((volatile uint32_t *)0xfe0521c8)
+#define P_AED_POW_ADJ_INDEX0 ((volatile uint32_t *)0xfe0521cc)
+#define P_AED_POW_ADJ_INDEX1 ((volatile uint32_t *)0xfe0521d0)
+#define P_AED_POW_ADJ_INDEX2 ((volatile uint32_t *)0xfe0521d4)
+#define P_AED_DRC_GAIN_INDEX0 ((volatile uint32_t *)0xfe0521d8)
+#define P_AED_DRC_GAIN_INDEX1 ((volatile uint32_t *)0xfe0521dc)
+#define P_AED_DRC_GAIN_INDEX2 ((volatile uint32_t *)0xfe0521e0)
+#define P_AED_CH1_VOLUME_STATE ((volatile uint32_t *)0xfe0521e4)
+#define P_AED_CH2_VOLUME_STATE ((volatile uint32_t *)0xfe0521e8)
+#define P_AED_CH1_VOLUME_GAIN ((volatile uint32_t *)0xfe0521ec)
+#define P_AED_CH2_VOLUME_GAIN ((volatile uint32_t *)0xfe0521f0)
+#define P_AED_FULL_POW_CURRENT ((volatile uint32_t *)0xfe0521f4)
+#define P_AED_FULL_POW_OUT ((volatile uint32_t *)0xfe0521f8)
+#define P_AED_FULL_POW_ADJ ((volatile uint32_t *)0xfe0521fc)
+#define P_AED_FULL_DRC_GAIN ((volatile uint32_t *)0xfe052200)
+#define P_AED_MASTER_VOLUME_STATE ((volatile uint32_t *)0xfe052204)
+#define P_AED_MASTER_VOLUME_GAIN ((volatile uint32_t *)0xfe052208)
+#define P_AED_TOP_CTL0 ((volatile uint32_t *)0xfe05220c)
+#define P_AED_TOP_CTL1 ((volatile uint32_t *)0xfe052210)
+#define P_AED_TOP_CTL2 ((volatile uint32_t *)0xfe052214)
+//========================================================================
+// AUDIO locker - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051400
+// -----------------------------------------------
+#define P_AUD_LOCK_EN ((volatile uint32_t *)0xfe051400)
+#define P_AUD_LOCK_SW_RESET ((volatile uint32_t *)0xfe051404)
+#define P_AUD_LOCK_SW_LATCH ((volatile uint32_t *)0xfe051408)
+#define P_AUD_LOCK_HW_LATCH ((volatile uint32_t *)0xfe05140c)
+#define P_AUD_LOCK_REFCLK_SRC ((volatile uint32_t *)0xfe051410)
+#define P_AUD_LOCK_REFCLK_LAT_INT ((volatile uint32_t *)0xfe051414)
+#define P_AUD_LOCK_IMCLK_LAT_INT ((volatile uint32_t *)0xfe051418)
+#define P_AUD_LOCK_OMCLK_LAT_INT ((volatile uint32_t *)0xfe05141c)
+#define P_AUD_LOCK_REFCLK_DS_INT ((volatile uint32_t *)0xfe051420)
+#define P_AUD_LOCK_IMCLK_DS_INT ((volatile uint32_t *)0xfe051424)
+#define P_AUD_LOCK_OMCLK_DS_INT ((volatile uint32_t *)0xfe051428)
+#define P_AUD_LOCK_INT_CLR ((volatile uint32_t *)0xfe05142c)
+#define P_AUD_LOCK_GCLK_CTRL ((volatile uint32_t *)0xfe051430)
+#define P_AUD_LOCK_INT_CTRL ((volatile uint32_t *)0xfe051434)
+#define P_RO_REF2IMCLK_CNT_L ((volatile uint32_t *)0xfe051440)
+#define P_RO_REF2IMCLK_CNT_H ((volatile uint32_t *)0xfe051444)
+#define P_RO_REF2OMCLK_CNT_L ((volatile uint32_t *)0xfe051448)
+#define P_RO_REF2OMCLK_CNT_H ((volatile uint32_t *)0xfe05144c)
+#define P_RO_IMCLK2REF_CNT_L ((volatile uint32_t *)0xfe051450)
+#define P_RO_IMCLK2REF_CNT_H ((volatile uint32_t *)0xfe051454)
+#define P_RO_OMCLK2REF_CNT_L ((volatile uint32_t *)0xfe051458)
+#define P_RO_OMCLK2REF_CNT_H ((volatile uint32_t *)0xfe05145c)
+#define P_RO_REFCLK_PKG_CNT ((volatile uint32_t *)0xfe051460)
+#define P_RO_IMCLK_PKG_CNT ((volatile uint32_t *)0xfe051464)
+#define P_RO_OMCLK_PKG_CNT ((volatile uint32_t *)0xfe051468)
+#define P_RO_AUD_LOCK_INT_STATUS ((volatile uint32_t *)0xfe05146c)
+//========================================================================
+// AUDIO VAD - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051800
+// -----------------------------------------------
+//
+// Reading file: VAD_REG.h
+//
+#define P_VAD_TOP_CTRL0 ((volatile uint32_t *)0xfe051800)
+#define P_VAD_TOP_CTRL1 ((volatile uint32_t *)0xfe051804)
+#define P_VAD_TOP_CTRL2 ((volatile uint32_t *)0xfe051808)
+#define P_VAD_FIR_CTRL ((volatile uint32_t *)0xfe05180c)
+#define P_VAD_FIR_EMP ((volatile uint32_t *)0xfe051810)
+#define P_VAD_FIR_COEF0 ((volatile uint32_t *)0xfe051814)
+#define P_VAD_FIR_COEF1 ((volatile uint32_t *)0xfe051818)
+#define P_VAD_FIR_COEF2 ((volatile uint32_t *)0xfe05181c)
+#define P_VAD_FIR_COEF3 ((volatile uint32_t *)0xfe051820)
+#define P_VAD_FIR_COEF4 ((volatile uint32_t *)0xfe051824)
+#define P_VAD_FIR_COEF5 ((volatile uint32_t *)0xfe051828)
+#define P_VAD_FIR_COEF6 ((volatile uint32_t *)0xfe05182c)
+#define P_VAD_FIR_COEF7 ((volatile uint32_t *)0xfe051830)
+#define P_VAD_FIR_COEF8 ((volatile uint32_t *)0xfe051834)
+#define P_VAD_FIR_COEF9 ((volatile uint32_t *)0xfe051838)
+#define P_VAD_FIR_COEF10 ((volatile uint32_t *)0xfe05183c)
+#define P_VAD_FIR_COEF11 ((volatile uint32_t *)0xfe051840)
+#define P_VAD_FIR_COEF12 ((volatile uint32_t *)0xfe051844)
+#define P_VAD_FRAME_CTRL0 ((volatile uint32_t *)0xfe051848)
+#define P_VAD_FRAME_CTRL1 ((volatile uint32_t *)0xfe05184c)
+#define P_VAD_FRAME_CTRL2 ((volatile uint32_t *)0xfe051850)
+#define P_VAD_CEP_CTRL0 ((volatile uint32_t *)0xfe051854)
+#define P_VAD_CEP_CTRL1 ((volatile uint32_t *)0xfe051858)
+#define P_VAD_CEP_CTRL2 ((volatile uint32_t *)0xfe05185c)
+#define P_VAD_CEP_CTRL3 ((volatile uint32_t *)0xfe051860)
+#define P_VAD_CEP_CTRL4 ((volatile uint32_t *)0xfe051864)
+#define P_VAD_CEP_CTRL5 ((volatile uint32_t *)0xfe051868)
+#define P_VAD_DEC_CTRL ((volatile uint32_t *)0xfe05186c)
+#define P_VAD_TOP_STS0 ((volatile uint32_t *)0xfe051870)
+#define P_VAD_TOP_STS1 ((volatile uint32_t *)0xfe051874)
+#define P_VAD_TOP_STS2 ((volatile uint32_t *)0xfe051878)
+#define P_VAD_FIR_STS0 ((volatile uint32_t *)0xfe05187c)
+#define P_VAD_FIR_STS1 ((volatile uint32_t *)0xfe051880)
+#define P_VAD_POW_STS0 ((volatile uint32_t *)0xfe051884)
+#define P_VAD_POW_STS1 ((volatile uint32_t *)0xfe051888)
+#define P_VAD_POW_STS2 ((volatile uint32_t *)0xfe05188c)
+#define P_VAD_FFT_STS0 ((volatile uint32_t *)0xfe051890)
+#define P_VAD_FFT_STS1 ((volatile uint32_t *)0xfe051894)
+#define P_VAD_SPE_STS0 ((volatile uint32_t *)0xfe051898)
+#define P_VAD_SPE_STS1 ((volatile uint32_t *)0xfe05189c)
+#define P_VAD_SPE_STS2 ((volatile uint32_t *)0xfe0518a0)
+#define P_VAD_SPE_STS3 ((volatile uint32_t *)0xfe0518a4)
+#define P_VAD_DEC_STS0 ((volatile uint32_t *)0xfe0518a8)
+#define P_VAD_DEC_STS1 ((volatile uint32_t *)0xfe0518ac)
+#define P_VAD_LUT_CTRL ((volatile uint32_t *)0xfe0518b0)
+#define P_VAD_LUT_WR ((volatile uint32_t *)0xfe0518b4)
+#define P_VAD_LUT_RD ((volatile uint32_t *)0xfe0518b8)
+#define P_VAD_IN_SEL0 ((volatile uint32_t *)0xfe0518bc)
+#define P_VAD_IN_SEL1 ((volatile uint32_t *)0xfe0518c0)
+#define P_VAD_TO_DDR ((volatile uint32_t *)0xfe0518c4)
+//
+// Closing file: VAD_REG.h
+//
+//========================================================================
+// AUDIO RESAMPLEA - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051c00
+// -----------------------------------------------
+//
+// Reading file: RESAMPLE.h
+//
+#define P_AUDIO_RSAMP_CTRL0 ((volatile uint32_t *)0xfe051c00)
+//Bit 31:3 reserved
+//Bit 2 reg_lock_rst //unsigned , default =0;
+//Bit 1 reg_rsamp_rst //unsigned , default =0;
+//Bit 0 reg_sw_rst //unsigned , default =0;
+#define P_AUDIO_RSAMP_CTRL1 ((volatile uint32_t *)0xfe051c04)
+//Bit 31:26 reserved //unsigned , default =0;
+//Bit 25 reg_rsamp_rst_sel //unsigned , default =0;
+//Bit 24 reg_module_bypas //unsigned , default =0;
+//Bit 23:18 reg_gclk_ctrl //unsigned , default =0;
+//Bit 17:13 reg_in_msb //unsigned , default =23;
+//Bit 12 reg_output_en //unsigned , default =0;
+//Bit 11 reg_rsamp_en //unsigned , default =0;
+//Bit 10 reg_filt_en //unsigned , default =0;
+//Bit 9 reg_post_en //unsigned , default =0;
+//Bit 8 reg_inp_mux_mode //unsigned , default =0;
+//Bit 7:4 reserved //unsigned , default =2;
+//Bit 3:0 reg_inp_mux //unsigned , default =0;
+#define P_AUDIO_RSAMP_CTRL2 ((volatile uint32_t *)0xfe051c08)
+//Bit 31:30 reserved //unsigned , default =0;
+//Bit 29:24 reg_chx_size //unsigned , default =2;
+//Bit 23:18 reserved //unsigned , default =0;
+//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4
+//Bit 15:8 reg_filt_tap //unsigned , default =63;
+//Bit 7:0 reg_intp_tap //unsigned , default =63;
+#define P_AUDIO_RSAMP_PHSINIT ((volatile uint32_t *)0xfe051c0c)
+//Bit 31:28 reserved //unsigned , default = 0;
+//Bit 27:0 reg_init_phs //unsigned , default = 0;
+#define P_AUDIO_RSAMP_PHSSTEP ((volatile uint32_t *)0xfe051c10)
+//Bit 31 reserved //unsigned , default = 0;
+//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000
+#define P_AUDIO_RSAMP_SHIFT ((volatile uint32_t *)0xfe051c14)
+//Bit 31:24 reg_rsft_iir //unsigned , default = 23;
+//Bit 23:16 reg_rsft_blnd //unsigned , default = 21;
+//Bit 15:8 reg_rsft_sinc //unsigned , default = 31;
+//Bit 7:0 reg_rsft_aa //unsigned , default = 31;
+#define P_AUDIO_RSAMP_ADJ_CTRL0 ((volatile uint32_t *)0xfe051c18)
+//Bit 31:3 reserved //unsigned
+//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0;
+//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0;
+//Bit 0 reg_rsamp_adj_en //unsigned , default = 0;
+#define P_AUDIO_RSAMP_ADJ_CTRL1 ((volatile uint32_t *)0xfe051c1c)
+//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8;
+//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768;
+#define P_AUDIO_RSAMP_ADJ_SFT ((volatile uint32_t *)0xfe051c20)
+//Bit 31:30 reserved //unsigned , default = 0;
+//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0;
+//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9;
+//Bit 23:21 reserved //unsigned , default = 0;
+//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1;
+//Bit 15:13 reserved //unsigned , default = 0;
+//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6;
+//Bit 7:6 reserved //unsigned , default = 0;
+//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12;
+#define P_AUDIO_RSAMP_ADJ_IDET_LEN ((volatile uint32_t *)0xfe051c24)
+//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000;
+#define P_AUDIO_RSAMP_ADJ_FORCE ((volatile uint32_t *)0xfe051c28)
+//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8;
+#define P_AUDIO_RSAMP_ADJ_KI_FORCE ((volatile uint32_t *)0xfe051c2c)
+//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0;
+#define P_AUDIO_RSAMP_RO_STATUS ((volatile uint32_t *)0xfe051c40)
+//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]}
+#define P_AUDIO_RSAMP_RO_ADJ_FREQ ((volatile uint32_t *)0xfe051c44)
+//Bit 31:0 ro_rsamp_adj_freq
+#define P_AUDIO_RSAMP_RO_ADJ_DIFF_BAK ((volatile uint32_t *)0xfe051c48)
+//Bit 31:0 ro_det_diff_bak
+#define P_AUDIO_RSAMP_RO_ADJ_DIFF_DLT ((volatile uint32_t *)0xfe051c4c)
+//Bit 31:0 ro_det_diff_dlt
+#define P_AUDIO_RSAMP_RO_ADJ_PHS_ERR ((volatile uint32_t *)0xfe051c50)
+//Bit 31:0 ro_det_phase_err
+#define P_AUDIO_RSAMP_RO_ADJ_KI_OUT ((volatile uint32_t *)0xfe051c54)
+//Bit 31:0 ro_rsamp_ki_out
+#define P_AUDIO_RSAMP_RO_IN_CNT ((volatile uint32_t *)0xfe051c58)
+//Bit 31:0 ro_rsamp_in_cnt
+#define P_AUDIO_RSAMP_RO_OUT_CNT ((volatile uint32_t *)0xfe051c5c)
+//Bit 31:0 ro_rsamp_out_cnt
+#define P_AUDIO_RSAMP_POST_COEF0 ((volatile uint32_t *)0xfe051c80)
+//Bit 31:0 reg_post_coef0 //signed , default = 0;
+#define P_AUDIO_RSAMP_POST_COEF1 ((volatile uint32_t *)0xfe051c84)
+//Bit 31:0 reg_post_coef1 //signed , default = 0;
+#define P_AUDIO_RSAMP_POST_COEF2 ((volatile uint32_t *)0xfe051c88)
+//Bit 31:0 reg_post_coef2 //signed , default = 0;
+#define P_AUDIO_RSAMP_POST_COEF3 ((volatile uint32_t *)0xfe051c8c)
+//Bit 31:0 reg_post_coef3 //signed , default = 0;
+#define P_AUDIO_RSAMP_POST_COEF4 ((volatile uint32_t *)0xfe051c90)
+//Bit 31:0 reg_post_coef4 //signed , default = 0;
+#define P_AUDIO_RSAMP_AA_COEF_ADDR ((volatile uint32_t *)0xfe051cc0)
+//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0;
+#define P_AUDIO_RSAMP_AA_COEF_DATA ((volatile uint32_t *)0xfe051cc4)
+//Bit 31:0 reg_aa_coef_data //signed , default = 0;
+#define P_AUDIO_RSAMP_SINC_COEF_ADDR ((volatile uint32_t *)0xfe051d00)
+//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0;
+#define P_AUDIO_RSAMP_SINC_COEF_DATA ((volatile uint32_t *)0xfe051d04)
+//Bit 31:0 reg_sinc_coef_data //signed , default = 0;
+//
+// Closing file: RESAMPLE.h
+//
+//========================================================================
+// AUDIO TOP_VAD - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe054800
+// -----------------------------------------------
+#define P_EE_AUDIO2_CLK81_CTRL ((volatile uint32_t *)0xfe054800)
+#define P_EE_AUDIO2_CLK81_EN ((volatile uint32_t *)0xfe054804)
+#define P_EE_AUDIO2_SW_RESET0 ((volatile uint32_t *)0xfe054808)
+#define P_EE_AUDIO2_CLK_GATE_EN0 ((volatile uint32_t *)0xfe05480c)
+#define P_EE_AUDIO2_SECURITY_CTRL0 ((volatile uint32_t *)0xfe054810)
+#define P_EE_AUDIO2_MCLK_VAD_CTRL ((volatile uint32_t *)0xfe054840)
+#define P_EE_AUDIO2_VAD_CLK_CTRL ((volatile uint32_t *)0xfe054844)
+#define P_EE_AUDIO2_MST_DLY_CTRL0 ((volatile uint32_t *)0xfe054848)
+#define P_EE_AUDIO2_MST_VAD_SCLK_CTRL0 ((volatile uint32_t *)0xfe05484c)
+#define P_EE_AUDIO2_MST_VAD_SCLK_CTRL1 ((volatile uint32_t *)0xfe054850)
+#define P_EE_AUDIO2_CLK_TDMIN_VAD_CTRL ((volatile uint32_t *)0xfe054854)
+#define P_EE_AUDIO2_CLK_PDMIN_CTRL0 ((volatile uint32_t *)0xfe054858)
+#define P_EE_AUDIO2_CLK_PDMIN_CTRL1 ((volatile uint32_t *)0xfe05485c)
+#define P_EE_AUDIO2_TOVAD_CTRL0 ((volatile uint32_t *)0xfe054880)
+#define P_EE_AUDIO2_TODDR_VAD_CTRL0 ((volatile uint32_t *)0xfe0548c0)
+#define P_EE_AUDIO2_TODDR_VAD_CTRL1 ((volatile uint32_t *)0xfe0548c4)
+#define P_EE_AUDIO2_TODDR_VAD_CTRL2 ((volatile uint32_t *)0xfe0548c8)
+#define P_EE_AUDIO2_TODDR_VAD_START_ADDR ((volatile uint32_t *)0xfe0548cc)
+#define P_EE_AUDIO2_TODDR_VAD_INIT_ADDR ((volatile uint32_t *)0xfe0548d0)
+#define P_EE_AUDIO2_TODDR_VAD_FINISH_ADDR ((volatile uint32_t *)0xfe0548d4)
+#define P_EE_AUDIO2_TODDR_VAD_START_ADDRB ((volatile uint32_t *)0xfe0548d8)
+#define P_EE_AUDIO2_TODDR_VAD_FINISH_ADDRB ((volatile uint32_t *)0xfe0548dc)
+#define P_EE_AUDIO2_TODDR_VAD_INT_ADDR ((volatile uint32_t *)0xfe0548e0)
+#define P_EE_AUDIO2_TODDR_VAD_STATUS1 ((volatile uint32_t *)0xfe0548e4)
+#define P_EE_AUDIO2_TODDR_VAD_STATUS2 ((volatile uint32_t *)0xfe0548e8)
+#define P_EE_AUDIO2_TDMIN_VAD_CTRL ((volatile uint32_t *)0xfe054900)
+#define P_EE_AUDIO2_TDMIN_VAD_SWAP0 ((volatile uint32_t *)0xfe054904)
+#define P_EE_AUDIO2_TDMIN_VAD_SWAP1 ((volatile uint32_t *)0xfe054908)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE_VAL ((volatile uint32_t *)0xfe05490c)
+#define P_EE_AUDIO2_TDMIN_VAD_STAT ((volatile uint32_t *)0xfe054910)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE0 ((volatile uint32_t *)0xfe054940)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE1 ((volatile uint32_t *)0xfe054944)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE2 ((volatile uint32_t *)0xfe054948)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE3 ((volatile uint32_t *)0xfe05494c)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE4 ((volatile uint32_t *)0xfe054950)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE5 ((volatile uint32_t *)0xfe054954)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE6 ((volatile uint32_t *)0xfe054958)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE7 ((volatile uint32_t *)0xfe05495c)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK0 ((volatile uint32_t *)0xfe054960)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK1 ((volatile uint32_t *)0xfe054964)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK2 ((volatile uint32_t *)0xfe054968)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK3 ((volatile uint32_t *)0xfe05496c)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK4 ((volatile uint32_t *)0xfe054970)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK5 ((volatile uint32_t *)0xfe054974)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK6 ((volatile uint32_t *)0xfe054978)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK7 ((volatile uint32_t *)0xfe05497c)
+//
+// Closing file: REG_LIST_AUDIO_RTL.h
+//
+//
+// Reading file: ../spifc/rtl/spifc_reg.vh
+//
+//`ifdef SPIFC_REG_DEFINE
+//`else
+//`define SPIFC_REG_DEFINE
+//`define SPIFC BASE ADDR 32'hfd000400
+// -----------------------------------------------
+// APB_BASE: APB2_BASE_ADDR = 0xfd000400
+// -----------------------------------------------
+//AHB domain regsiter.
+#define P_SPIFC_AHB_CTRL ((volatile uint32_t *)0xfd000400)
+//bit 31 AHB BUS enable. 1 enable ahb request. 0: disable ahb request.
+//bit 30. decerr_en for (AXI->AHB bridge).
+//bit 29. force_incr. for ( AXI->AHB bridge).
+//bit 19. critical word first. CWF_EN. 1: enable. 0 : disable.
+//bit 18:17 RDBUF_SIZE . 00: 64bytes. 01: 32 bytes. 10: 16 bytes. 11: reserved.
+//bit 16 AHB MASTER enable. if enabled, each master use one dedicated HRDATA buffer inside ahb2api model. total 3 HRDATA buffers inside ahb2spi.
+//if disabled the 3 HRDATA buffer will random be used for all masters.
+//bit 14 write 1 to clean the HRDATA buffer 2. read 0 finished clean operation.
+//bit 13 write 1 to clean the HRDATA buffer 1. read 0 finished clean operation.
+//bit 12 write 1 to clean the HRDATA buffer 0. read 0 finished clean operation.
+//bit 11:0. not used.
+#define P_SPIFC_CLK_CTRL ((volatile uint32_t *)0xfd000404)
+//bit 14 asynchronous buffer ahb clock disable. 1 = disable. 0 = enable.
+//bit 13 ahb2spi ahb clock disable. 1 = disable. 0 = enable.
+//bit 12 ahb_arb ahb clock disable. 1 = disable. 0 = enable.
+//bit 10 asynchronous buffer ahb clock auto gating enable. 1 = enable. 0 = disable.
+//bit 9 ahb2spi ahb clock auto gating enable. 1 = enable. 0 = disable.
+//bit 8 ahbarb ahb clock auto gating enable. 1 = enable. 0 = disable.
+//bit 2. asynchronous AHB clock domain software reset. 1 = reset. 0 = normal working mode.
+//bit 1. ahb2spi ahb clock domain software reset. 1 = reset. 0 = normal working mode.
+//bit 0. not used.
+#define P_SPIFC_SEC_CTRL ((volatile uint32_t *)0xfd000408)
+//bit 31. ADDRESS security range enable. 1 = enable; 0: disable.
+//bit 14. range6 enable: 1: enable; 0 : disable.
+//bit 13. range5 enable: 1: enable; 0 : disable.
+//bit 12. range4 enable: 1: enable; 0 : disable.
+//bit 11. range3 enable: 1: enable; 0 : disable.
+//bit 10. range2 enable: 1: enable; 0 : disable.
+//bit 9. range1 enable: 1: enable; 0 : disable.
+//bit 8. range0 enable: 1: enable; 0 : disable.
+//bit 7:4 to control spi clock register security. bit 7 = 1, APB bus can access spi clock domain register. bit 7 == 0 : only PPROT[0] == bit 4, the APB can access spic clock domain register.
+//bit 3:0 to control ahb clock domain register secruity. bit 3 = 1, APB bus can access ahb clock domain register. bit 3 ==0; only PPROT[0] == bit 0, the APB can access ahb clock domain register.
+#define P_SPIFC_RANGE0_STA ((volatile uint32_t *)0xfd000440)
+//bit 28 :6.
+//AHB security range 0 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE0_EDA ((volatile uint32_t *)0xfd000444)
+//bit 28 :6.
+//AHB security range 0 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE0_CTRL ((volatile uint32_t *)0xfd000448)
+// AHB secruity range 0 control.
+//bit 15:8 range 0 access control for DMA access.
+//bit 15 range 0 access control for DMA thread 7
+//bit 14 range 0 access control for DMA Thread 6
+//bit 13 range 0 access control for DMA Thread 5.
+//bit 12 range 0 access control for DMA Thread 4.
+// bit 11. range 0 access control for DMA thread 3
+// bit 10. range 0 access control for DMA Thread 2
+// bit 9. range 0 access control for DMA Thread 1.
+// bit 8. range 0 access control for DMA Thread 0.
+// bit 7. range 0 access control for HMASTER == 7 Not used.
+// bit 6. range 0 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 0 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 0 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 0 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 0 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 0 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 0 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE1_STA ((volatile uint32_t *)0xfd00044c)
+//bit 28 :6.
+//AHB security range 1 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE1_EDA ((volatile uint32_t *)0xfd000450)
+//bit 28 :6.
+//AHB security range 1 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE1_CTRL ((volatile uint32_t *)0xfd000454)
+// AHB secruity range 1 control.
+//bit 15:8 range 1 access control for DMA access.
+//bit 15 range 1 access control for DMA thread 7
+//bit 14 range 1 access control for DMA Thread 6
+//bit 13 range 1 access control for DMA Thread 5.
+//bit 12 range 1 access control for DMA Thread 4.
+// bit 11. range 1 access control for DMA thread 3
+// bit 10. range 1 access control for DMA Thread 2
+// bit 9. range 1 access control for DMA Thread 1.
+// bit 8. range 1 access control for DMA Thread 0.
+// bit 7. range 1 access control for HMASTER == 7 Not used.
+// bit 6. range 1 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 1 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 1 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 1 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 1 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 1 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 1 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE2_STA ((volatile uint32_t *)0xfd000458)
+//bit 28 :6.
+//AHB security range 2 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE2_EDA ((volatile uint32_t *)0xfd00045c)
+//bit 28 :6.
+//AHB security range 2 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE2_CTRL ((volatile uint32_t *)0xfd000460)
+// AHB secruity range 2 control.
+//bit 15:8 range 2 access control for DMA access.
+//bit 15 range 2 access control for DMA thread 7
+//bit 14 range 2 access control for DMA Thread 6
+//bit 13 range 2 access control for DMA Thread 5.
+//bit 12 range 2 access control for DMA Thread 4.
+// bit 11. range 2 access control for DMA thread 3
+// bit 10. range 2 access control for DMA Thread 2
+// bit 9. range 2 access control for DMA Thread 1.
+// bit 8. range 2 access control for DMA Thread 0.
+// bit 7. range 2 access control for HMASTER == 7 Not used.
+// bit 6. range 2 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 2 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 2 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 2 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 2 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 2 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 2 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE3_STA ((volatile uint32_t *)0xfd000464)
+//bit 28 :6.
+//AHB security range 3 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE3_EDA ((volatile uint32_t *)0xfd000468)
+//bit 28 :6.
+//AHB security range 3 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE3_CTRL ((volatile uint32_t *)0xfd00046c)
+// AHB secruity range 3 control.
+//bit 15:8 range 3 access control for DMA access.
+//bit 15 range 3 access control for DMA thread 7
+//bit 14 range 3 access control for DMA Thread 6
+//bit 13 range 3 access control for DMA Thread 5.
+//bit 12 range 3 access control for DMA Thread 4.
+// bit 11. range 3 access control for DMA thread 3
+// bit 10. range 3 access control for DMA Thread 2
+// bit 9. range 3 access control for DMA Thread 1.
+// bit 8. range 3 access control for DMA Thread 0.
+// bit 7. range 3 access control for HMASTER == 7 Not used.
+// bit 6. range 3 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 3 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 3 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 3 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 3 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 3 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 3 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE4_STA ((volatile uint32_t *)0xfd000470)
+//bit 28 :6.
+//AHB security range 4 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE4_EDA ((volatile uint32_t *)0xfd000474)
+//bit 28 :6.
+//AHB security range 4 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE4_CTRL ((volatile uint32_t *)0xfd000478)
+// AHB secruity range 4 control.
+//bit 15:8 range 4 access control for DMA access.
+//bit 15 range 4 access control for DMA thread 7
+//bit 14 range 4 access control for DMA Thread 6
+//bit 13 range 4 access control for DMA Thread 5.
+//bit 12 range 4 access control for DMA Thread 4.
+// bit 11. range 4 access control for DMA thread 3
+// bit 10. range 4 access control for DMA Thread 2
+// bit 9. range 4 access control for DMA Thread 1.
+// bit 8. range 4 access control for DMA Thread 0.
+// bit 7. range 4 access control for HMASTER == 7 Not used.
+// bit 6. range 4 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 4 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 4 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 4 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 4 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 4 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 4 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE5_STA ((volatile uint32_t *)0xfd00047c)
+//bit 28 :6.
+//AHB security range 5 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE5_EDA ((volatile uint32_t *)0xfd000484)
+//bit 28 :6.
+//AHB security range 5 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE5_CTRL ((volatile uint32_t *)0xfd000480)
+// AHB secruity range 5 control.
+//bit 15:8 range 5 access control for DMA access.
+//bit 15 range 5 access control for DMA thread 7
+//bit 14 range 5 access control for DMA Thread 6
+//bit 13 range 5 access control for DMA Thread 5.
+//bit 12 range 5 access control for DMA Thread 4.
+// bit 11. range 5 access control for DMA thread 3
+// bit 10. range 5 access control for DMA Thread 2
+// bit 9. range 5 access control for DMA Thread 1.
+// bit 8. range 5 access control for DMA Thread 0.
+// bit 7. range 5 access control for HMASTER == 7 Not used.
+// bit 6. range 5 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 5 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 5 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 5 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 5 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 5 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 5 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE6_STA ((volatile uint32_t *)0xfd000488)
+//bit 28 :6.
+//AHB security range 6 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE6_EDA ((volatile uint32_t *)0xfd00048c)
+//bit 28 :6.
+//AHB security range 6 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE6_CTRL ((volatile uint32_t *)0xfd000490)
+// AHB secruity range 6 control.
+//bit 15:8 range 6 access control for DMA access.
+//bit 15 range 6 access control for DMA thread 7
+//bit 14 range 6 access control for DMA Thread 6
+//bit 13 range 6 access control for DMA Thread 5.
+//bit 12 range 6 access control for DMA Thread 4.
+// bit 11. range 6 access control for DMA thread 3
+// bit 10. range 6 access control for DMA Thread 2
+// bit 9. range 6 access control for DMA Thread 1.
+// bit 8. range 6 access control for DMA Thread 0.
+// bit 7. range 6 access control for HMASTER == 7 Not used.
+// bit 6. range 6 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 6 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 6 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 6 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 6 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 6 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 6 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE7_CTRL ((volatile uint32_t *)0xfd000494)
+// AHB secruity range 7( default range) control.
+//bit 15:8 range 7 access control for DMA access.
+//bit 15 range 7 access control for DMA thread 7
+//bit 14 range 7 access control for DMA Thread 6
+//bit 13 range 7 access control for DMA Thread 5.
+//bit 12 range 7 access control for DMA Thread 4.
+// bit 11. range 7 access control for DMA thread 3
+// bit 10. range 7 access control for DMA Thread 2
+// bit 9. range 7 access control for DMA Thread 1.
+// bit 8. range 7 access control for DMA Thread 0.
+// bit 7. range 7 access control for HMASTER == 7 Not used.
+// bit 6. range 7 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 7 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 7 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 7 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 7 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 7 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 7 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_AHB_WTCH_CTRL ((volatile uint32_t *)0xfd000498)
+//bit 15:0. ahb bus watch dog timer. if AHB bus not response, the timer over this number, the SPIFC will send back a error response.
+#define P_SPIFC_SEC_VIO0 ((volatile uint32_t *)0xfd00049c)
+//bit 31:0 VIO ADDR
+#define P_SPIFC_SEC_VIO1 ((volatile uint32_t *)0xfd0004a0)
+//bit 31. AHB VIO status. write 1 to clear the error info.
+//bit 6:5 HMASTER.
+//bit 4:2 HPROT.
+//bit 1 HNONSEC.
+//bit 0 HWRITE.
+#define P_SPIFC_AHB_STS ((volatile uint32_t *)0xfd0004a4)
+//bit 31. AHB IDLE. when ahb disabled, to show ahb status. 1, no more ahb request or ahb requent is holded. 0, ahb is still busy.
+//bit 30. AHB data cycle status, when ahb disabled, to show ahb data cycle status. 1, data cycle is holded, 0 : not in data cycle or data cycle is processing.
+//bit 29. AHB bus spi requst status. 1: still waiting for spi data. 0: idle.
+//bit 28:0. not used.
+//SPI cts_spi_clk domain regsiter.
+#define P_SPIFC_USER_CTRL0 ((volatile uint32_t *)0xfd000600)
+//bit 31. user request enable. write 1 to enable. read 0, means user command accepted by the SPI_CTRL.
+//bit 30. user request finish bit. write 0 when enable user request. read 1 means SPI_CTRL finished this user command.
+//bit 0. user data updated. write 0 when enable user request. 1 means there's datas/status read from SPI flash.
+#define P_SPIFC_USER_CTRL1 ((volatile uint32_t *)0xfd000604)
+//bit 31. not used.
+//bit 30. user command cycle enable. 1) enable. 0) don't send command in usr command period.
+//bit 29:28. user command mode. 00 = SPI extend mode. 01 : dual mode. 10: quad mode.
+//bit 27:20. user command code. the code need to send in command period.
+//bit 19. user address cycle enable.
+//bit 18:17 user address mode: 00 = SPI extend mode. 01 : dual mode. 10: quad mode.
+//bit 16:15 user address Byte length 00 = 1 byte. 01 = 2 bytes. 10 = 3 bytes. 11 = 4bytes.
+//bit 14 user datout enable.
+//bit 13 user dataout AES enable. 1: dataout through AES describle. 0 : original data.
+//bit 12 user data output source. 0: from data buffer. 1: from status register.
+//bit 11:10 user dataout mode: 00 SPI extend model. 01 : dual model. 10. quad mode.
+//bit 9:0 User data out bytes num.
+#define P_SPIFC_USER_CTRL2 ((volatile uint32_t *)0xfd000608)
+//bit 31 usr_dummy_en 1: enable dummy cycles. 0 : no dummy cycles.
+//bit 30: 29 usr_dummy_mode 2'b00 = SPI extend mode. 01 dual mode. 10 Quad mode.
+//bit 28:23 user dummy clock cycle number.
+//bit 19:16. user command input/output direction control. 000000: right after the last output.
+// 1: after the first cycle of dummy cycle.
+// .....
+// 4'hf: right before the datin cycle.
+//bit 15:8. data on the dummy cycle after the first byte.
+//bit 7:0 The first bytes data showed on dummy cycle. some flash may need special data for enhance performance mode or XIP mode.
+#define P_SPIFC_USER_CTRL3 ((volatile uint32_t *)0xfd00060c)
+//bit 31 usr_datin_en 1: datain cycle enabled. 0: no datain cycle.
+//bit 30: datin_dest. 1: save the input data to STATUS register. 0 save the input data to data buffer.
+//bit 29: 1: enable datain data AES describle. 0: not use AES.
+//bit 28:27. datin mode. 2'b00 SPI extend mode. 01: dual mode. 10 Quad mode.
+//bit 25:16. user data in data bytes. how many bytes of user datain expected.
+#define P_SPIFC_USER_ADDR ((volatile uint32_t *)0xfd000610)
+//bit 31:0. 32bits user address.
+#define P_SPIFC_AHB_REQ_CTRL ((volatile uint32_t *)0xfd000614)
+//bit 31. AHB request enable.
+//bit 30 AHB cmd_en. command cycle enable.
+//bit 29:28. ahb command mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode.
+//bit 27:20:.AHB command code.
+//bit 19. ahb request address cycle enable.
+//bit 18:17 AHB ADDRESS mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode.
+//bit 16:15 AHB ADDRESS data width. 2'b00: 1byte. 2'b01 : 2bytes. 2'b10: 3bytes. 2'b11 4bytes.
+//bit 13:10 AHB request spi bus input switch time. 0 : after address cycle. 1: the frist dummy cycles. ... 0xf. after dummy cycle.
+//bit 9:8 AHB DATAIN mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode.
+//bit 7 DATA IN AES enable. 1: enable 0: disable.
+//bit 1:0 AHB REQ DATA size. 2'b00: 64bytes. 2'b01: 32 bytes. 2'b10 : 16 bytes. 2'b11: reserved. this bit settign should be same as RDBUF_SIZE setting.
+#define P_SPIFC_AHB_REQ_CTRL1 ((volatile uint32_t *)0xfd000618)
+//bit 31. ahb Dummy enable.
+//bit 30:29. ahb dummy mode.
+//bit 28:23. ahb request dummy clock cycles.
+//bit 15:0. ahb dummy period output data.
+#define P_SPIFC_AHB_REQ_CTRL2 ((volatile uint32_t *)0xfd00061c)
+//bit 1:0 AHB address position. this settign depend on SPIFC_AHB_CTRL register CWF_EN bit and RDBUF_SIZE.
+// if CWF_EN is enabled. these bit should be set to 2'b10 (16BYTE boundary).
+// if CWF_EN is disabled. these bit should be set to same as the RDBUF_SIZE and AHB REQ DATA SIZE.
+//00 : 64byte boundary.
+//01 : 32byte boundary.
+//10 : 16byte boundary.
+//11 : reserved.
+#define P_SPIFC_ACTIMING0 ((volatile uint32_t *)0xfd000620)
+//bit 31:30. tSLCH
+//bit 29:28 tCLSH
+//bit 20:16 tSHWL
+//bit 15:12 tSHSL2
+//bit 11:8 tSHSL1
+//bit 7:0 tWHSL
+#define P_SPIFC_ACTIMING1 ((volatile uint32_t *)0xfd000624)
+//bit 31. D2 pin WP_n function enable.
+//bit 30. D2 Pin value in WP_n fucntion.
+//bit 29. D3 Pin HOLD_n function enable.
+//bit 8. DTR mode. not support.
+//bit 6:4. Clock turn around delay. use it to set the system SPI clock read data delay.
+//bit 3:0. not used.
+#define P_SPIFC_ACTIMING2 ((volatile uint32_t *)0xfd000628)
+//bit 31. spi clock input pin enable. SPIFC controller used this pin as clock to latch the input data.
+//bit [3:0] spi clock input pin delay adjustment.
+//SPI DATA BUFFER. There's a total 512Byte + 64byte(orgnized as 36x128bits) SRAM .
+// since each APB access is 32bits. So we use word address as APB read/write address.
+// But for SPI side we have to use 128bit boundary. That's the first Pragram/read SPI with data buffer must start at data buffer 128bit boundary. that means the SPIFC_USE_DBUF_ADDR last 2 bits must be 0.
+#define P_SPIFC_DBUF_CTRL ((volatile uint32_t *)0xfd000640)
+//bit 31. 1 = write DBUF. 0 : read DBUF.
+//bit 30. 1. = auto update address. 0 don't change address.
+//bit 7:0 DBUF address unit 32bits.
+#define P_SPIFC_DBUF_DATA ((volatile uint32_t *)0xfd000644)
+//bit 31:0. if SPIFC_DBUF_CTRL bit 31 = 1. write to this register will trigger one write to DBUF. and the data will be writen to DBUF.
+#define P_SPIFC_USER_DBUF_ADDR ((volatile uint32_t *)0xfd000648)
+//bit 7:0. the DBUF ADDRESS used to send to or receive from SPI FLASH. the last 2 bits must be 0.
+#define P_SPIFC_FLASH_STATUS ((volatile uint32_t *)0xfd000680)
+#define P_SPIFC_STATUS ((volatile uint32_t *)0xfd000684)
+//bit 1. AES KEY valid. read only 1 : The aes key is ready to use. 0: the aes key is not ready.
+//bit 0. SPI CTRL STATE IDLE. read only. 1 = idle; 0 = busy.
+#define P_SPIFC_CTRL ((volatile uint32_t *)0xfd000688)
+//bit 15:14. mempd for DBUF MEMORY.
+//bit 13 spifc asynchronous buffer clock disable. 1 = disable. 0 = enable.
+//bit 12. spifc controller clock disable. 1 = disable. 0 = enable.
+//bit 9. spifc asynchronous bufer clock auto gate enable. 1 = enable. 0 = disable.
+//bit 8. spifc controller clock auto gate enable. 1 = enable. 0 = disable.
+//bit 2. spifc interface reset. 1 = RESET. 0 = normal working mode.
+//bit 1. spifc asynchronous buffer spi clock side reset. 1 = RESET. 0 : normal working mode.
+//bit 0. spifc controller reset. 1 = RESET. 0 : normal working mode.
+//`endif
+//
+// Closing file: ../spifc/rtl/spifc_reg.vh
+//
+//
+// Reading file: ../psram/rtl/psram_reg.vh
+//
+//`ifdef PSRAM_REG_DEFINE
+//`else
+//`define PSRAM_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007400
+// -----------------------------------------------
+#define P_PSRAM_AXI_INTF_CTRL ((volatile uint32_t *)0xfe007400)
+//bit 3 axi interface soft reset. 1 = reset AXI interface. 0 = normal.
+//bit 2 disable axi interface clock. 1 = disable; 0 = enable.
+//bit 1 axi interface auto clock gating enable. 1 = enable; 0 = disable.
+//bit 0 axi interface AXI request enable. 1 = enable. 0 = disable.
+#define P_PSRAM_DBUF_CTRL ((volatile uint32_t *)0xfe007404)
+//bit 16. MWRITE_EN. 1 : enabel mask write(with DM pin). 0 not enable.
+//bit 15:0 DBUF AGE to write back to PSRAM if DBUF is dirty. but whole DBUF data is not READ to write.(with MWRITE enabled).
+#define P_PSRAM_DBUF_CTRL1 ((volatile uint32_t *)0xfe007408)
+//bit 15:0 DBUF AGE to write back to psram if DBUF is dirty and whole DBUF data is ready to write.
+#define P_PSRAM_APB_CTRL ((volatile uint32_t *)0xfe00740c)
+//7:4 PSRAM PHY register APB secure contrl.
+//bit 7, 1: no secure control. 0 : use bit 4 to match PPROT[0] bit.
+//bit 4. when bit 7 == 0, bit 4 must match PPROT[0] to access.
+//3:0 PCTL_CTRL APB bus control regsiters secure control.
+//bit 3, 1: no secure control. 0 : use bit 0 to match PPROT[0] bit.
+//bit 0. when bit 3 == 0, bit 0 must match PPROT[0] to access.
+#define P_PSRAM_SEC_CTRL ((volatile uint32_t *)0xfe007410)
+//bit 31. ADDRESS security range enable. 1 = enable; 0: disable.
+//if scruity range disabled, but AXI data describle enabled key0 is selected.
+//bit 23 range 7 des key selection 0 : key0; 1: key1;
+//bit 22 range 6 des key selection 0 : key0; 1: key1;
+//bit 21 range 5 des key selection 0 : key0; 1: key1;
+//bit 20 range 4 des key selection 0 : key0; 1: key1;
+//bit 19 range 3 des key selection 0 : key0; 1: key1;
+//bit 18 range 2 des key selection 0 : key0; 1: key1;
+//bit 17 range 1 des key selection 0 : key0; 1: key1;
+//bit 16 range0 des key selection 0 : key0; 1: key1;
+//bit 6. range6 enable: 1: enable; 0 : disable.
+//bit 5. range5 enable: 1: enable; 0 : disable.
+//bit 4. range4 enable: 1: enable; 0 : disable.
+//bit 3. range3 enable: 1: enable; 0 : disable.
+//bit 2. range2 enable: 1: enable; 0 : disable.
+//bit 1. range1 enable: 1: enable; 0 : disable.
+//bit 0. range0 enable: 1: enable; 0 : disable.
+#define P_PSRAM_DES_PADDING ((volatile uint32_t *)0xfe007414)
+//bit 31 :0 Padding, with address together to generate describle 64 bits input.
+#define P_PSRAM_RANGE0_STA ((volatile uint32_t *)0xfe007440)
+//bit 22 :0.
+//AXI security range 0 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE0_EDA ((volatile uint32_t *)0xfe007444)
+//bit 22 :0.
+//AXI security range 0 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE0_CTRL0 ((volatile uint32_t *)0xfe007448)
+// AXI secruity range 0 control.
+#define P_PSRAM_RANGE0_CTRL1 ((volatile uint32_t *)0xfe00744c)
+// AXI secruity range 0 control.
+#define P_PSRAM_RANGE1_STA ((volatile uint32_t *)0xfe007450)
+//bit 22 :0.
+//AXI security range 1 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE1_EDA ((volatile uint32_t *)0xfe007454)
+//bit 22 :0.
+//AXI security range 1 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE1_CTRL0 ((volatile uint32_t *)0xfe007458)
+// AXI secruity range 1 control.
+#define P_PSRAM_RANGE1_CTRL1 ((volatile uint32_t *)0xfe00745c)
+// AXI secruity range 1 control.
+#define P_PSRAM_RANGE2_STA ((volatile uint32_t *)0xfe007460)
+//bit 31 : 6.
+//AXI security range 2 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE2_EDA ((volatile uint32_t *)0xfe007464)
+//bit 31 :6.
+//AXI security range 2 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE2_CTRL0 ((volatile uint32_t *)0xfe007468)
+#define P_PSRAM_RANGE2_CTRL1 ((volatile uint32_t *)0xfe00746c)
+#define P_PSRAM_RANGE3_STA ((volatile uint32_t *)0xfe007470)
+//bit 31 : 6.
+//AXI security range 3 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE3_EDA ((volatile uint32_t *)0xfe007474)
+//bit 31 :6.
+//AXI security range 3 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE3_CTRL0 ((volatile uint32_t *)0xfe007478)
+// AXI secruity range 3 control.
+#define P_PSRAM_RANGE3_CTRL1 ((volatile uint32_t *)0xfe00747c)
+// AXI secruity range 3 control.
+#define P_PSRAM_RANGE4_STA ((volatile uint32_t *)0xfe007480)
+//bit 31 :6.
+//AXI security range 4 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE4_EDA ((volatile uint32_t *)0xfe007484)
+//bit 31 :6.
+//AXI security range 4 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE4_CTRL0 ((volatile uint32_t *)0xfe007488)
+// AXI secruity range 4 control.
+#define P_PSRAM_RANGE4_CTRL1 ((volatile uint32_t *)0xfe00748c)
+#define P_PSRAM_RANGE5_STA ((volatile uint32_t *)0xfe007490)
+//bit 22 :0.
+//AXI security range 5 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE5_EDA ((volatile uint32_t *)0xfe007494)
+//bit 22 :0.
+//AXI security range 5 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE5_CTRL0 ((volatile uint32_t *)0xfe007498)
+// AXI secruity range 5 control.
+#define P_PSRAM_RANGE5_CTRL1 ((volatile uint32_t *)0xfe00749c)
+// AXI secruity range 5 control.
+#define P_PSRAM_RANGE6_STA ((volatile uint32_t *)0xfe0074a0)
+//bit 22 :0.
+//AXI security range 6 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE6_EDA ((volatile uint32_t *)0xfe0074a4)
+//bit 22 :0.
+//AXI security range 6 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE6_CTRL0 ((volatile uint32_t *)0xfe0074a8)
+// AXI secruity range 6 control.
+#define P_PSRAM_RANGE6_CTRL1 ((volatile uint32_t *)0xfe0074ac)
+// AXI secruity range 6 control.
+#define P_PSRAM_RANGE7_CTRL0 ((volatile uint32_t *)0xfe0074b0)
+#define P_PSRAM_RANGE7_CTRL1 ((volatile uint32_t *)0xfe0074b4)
+#define P_PSRAM_VIO_STATUS ((volatile uint32_t *)0xfe0074b8)
+//bit 31: security violation. write 1 to clean security violation status.
+//bit 30. 1 : AXI write violation. 0 : axi read violation.
+//bit 18:16. AXI ARPROT/AWPROT>
+//bit 11:0. AXI violation ID.
+#define P_PSRAM_VIO_ADDR ((volatile uint32_t *)0xfe0074bc)
+//read only
+//31:0 AXI violation address.
+#define P_PSRAM_USER_CTRL0 ((volatile uint32_t *)0xfe007600)
+//bit 31. user request enable. write 1 to enable. read 0, means user command accepted by the SPI_CTRL.
+//bit 30. usr request done. after user command done. this bit set to 1.
+//bit 29. USR COMMAND enable.
+//bit 28. command type0. 1 READ command. 0 write command.
+//bit 27. command type1. 1 for register. 0 : for memory.
+//bit 21~16. USR command clock cycles
+//bit 15~0. USR COMMAND CODE.
+#define P_PSRAM_USER_CTRL1 ((volatile uint32_t *)0xfe007604)
+//bit 31. USR_ADDR_EN
+//bit 30:29. USR_ADDR_DW
+//bit 28~20. USR address clock cycle number.
+//bit 19:16 USR data output/input switch postion
+//bit 15. USR DUMMY ENABLE
+//bit 13~8. USR DUMMY clock cycles.
+//bit 5:0 USR data DQS read enable postion.
+#define P_PSRAM_USER_CTRL2 ((volatile uint32_t *)0xfe007608)
+//bit 31 usr des key selection. 1 : key 1; 0 : key 0.
+//bit 30. usr check latency. for Winbond PSRAM data read/write, DQS input indentify the latency is doubled or not.
+//bit 29. usr data des enable.
+//bit 28 usr datain enable.
+//bit 27. usr datain destination. 1 : write to CFG_STS register. 0 : write to DATA REGISTERs.
+//bit 26~16 usr data in clock cycle number.
+//bit 15. usr datout enable.
+//bit 14. usr data out source 1 : from CFG_STS register. 0 from DATA register.
+//bit 13~11. not used.
+//bit 10~0. usr dataout clock cycles.
+#define P_PSRAM_USER_CTRL3 ((volatile uint32_t *)0xfe00760c)
+//bit 17:16. which cycle to ask phy to check read/write latency at PSRAM SEND COMMOND stage.
+//since PSRAM send command stage only 3 clock cycle. So this number only can chose 0, 1, 2.
+//bit 15:0. user dummy data when output in dummy cycle.
+#define P_PSRAM_USER_ADDR ((volatile uint32_t *)0xfe007610)
+//bit 31:0. 32bits user address.
+#define P_PSRAM_AXI_REQ_CTRL0 ((volatile uint32_t *)0xfe007614)
+//bit 31. AXI request enable.
+//bit 30 AXI cmd_en. command cycle enable.
+//bit 29:24. AXI request command cycle clock numbers.
+//bit 22. AXI request address cycle enable.
+//bit 21:16. AXI request address cycle clock number.
+//bit 15:14. AXI address cycle data width.
+//bit 13:12. at which clock cycle to send signal to phy to check latency flag for WINBOND PSRAM flexible latency.
+//since PSRAM send command stage only 3 clock cycle. So this number only can chose 0, 1, 2.
+//bit 6 // AXI Write dummy enable.
+//bit 5:0 // axi write dummy clock cycle number.
+#define P_PSRAM_AXI_REQ_CTRL1 ((volatile uint32_t *)0xfe007618)
+//bit 31:16. AXI request psram READ command code.
+//bit 15:0. AXI request psram write command code.
+#define P_PSRAM_AXI_REQ_CTRL2 ((volatile uint32_t *)0xfe00761c)
+//bit 31. AXI read request Dummy enable.
+//bit 30. Check latency enable for WINBOND PSRAM flexible latency.
+//bit 27:22. clock cycles in dummy stage to eanble PSRAM PHY reading logic.
+//bit 21:16. axi_read dummy clock cycles number.
+//bit 15:0. dummy data if output in dummy cycles.
+#define P_PSRAM_AXI_REQ_CTRL3 ((volatile uint32_t *)0xfe007620)
+//bit 31 des enable.
+//bit 26:16. DATA input clock cycles.
+//bit 10:0. DATA output clock cycles.
+#define P_PSRAM_ACTIMING0 ((volatile uint32_t *)0xfe007624)
+//bit 31:30. tSLCH
+//bit 29:28 tCLSH
+//bit 20:16 tSHWL
+//bit 15:12 tSHSL2
+//bit 11:8 tSHSL1
+//bit 7:0 tWHSL
+#define P_PSRAM_ACTIMING1 ((volatile uint32_t *)0xfe007628)
+//bit 7:0 tRWR for winbond PSRAM, = tRWR -3. Winbond PSRAM include one CS cycle and 2 command cycle.
+//for APMEMORY should be same value of tCPH
+#define P_PSRAM_ACTIMING2 ((volatile uint32_t *)0xfe00762c)
+#define P_PSRAM_WDG_CTRL ((volatile uint32_t *)0xfe007630)
+//bit [31] 1: force to reset PSRAM PCTL and PHY logic. 0: normal.
+//bit [30] 1: automatic reset PSRAM PCTL and PHY logic if watch dog triggered.
+//bit 12:0. watch dog timer. for Winbond PSRAM should be 1us for tRC. for APMEMORY should be 1us for tCEM.
+//SPI DATA BUFFER. There's a total 512KByte + 64byte(orgnized as 36x128bits) SRAM .
+// since each APB access is 32bits. So we use word address as APB read/write address.
+// But for SPI side we have to use 128bit boundary. That's the first Pragram/read SPI with data buffer must start at data buffer 128bit boundary. that means the PSRAM_USE_DBUF_ADDR last 2 bits must be 0.
+#define P_PSRAM_DBUF_0 ((volatile uint32_t *)0xfe007640)
+#define P_PSRAM_DBUF_1 ((volatile uint32_t *)0xfe007644)
+#define P_PSRAM_DBUF_2 ((volatile uint32_t *)0xfe007648)
+#define P_PSRAM_DBUF_3 ((volatile uint32_t *)0xfe00764c)
+#define P_PSRAM_DBUF_4 ((volatile uint32_t *)0xfe007650)
+#define P_PSRAM_DBUF_5 ((volatile uint32_t *)0xfe007654)
+#define P_PSRAM_DBUF_6 ((volatile uint32_t *)0xfe007658)
+#define P_PSRAM_DBUF_7 ((volatile uint32_t *)0xfe00765c)
+#define P_PSRAM_DBUF_8 ((volatile uint32_t *)0xfe007660)
+#define P_PSRAM_DBUF_9 ((volatile uint32_t *)0xfe007664)
+#define P_PSRAM_DBUF_A ((volatile uint32_t *)0xfe007668)
+#define P_PSRAM_DBUF_B ((volatile uint32_t *)0xfe00766c)
+#define P_PSRAM_DBUF_C ((volatile uint32_t *)0xfe007670)
+#define P_PSRAM_DBUF_D ((volatile uint32_t *)0xfe007674)
+#define P_PSRAM_DBUF_E ((volatile uint32_t *)0xfe007678)
+#define P_PSRAM_DBUF_F ((volatile uint32_t *)0xfe00767c)
+#define P_PSRAM_CFG_STS ((volatile uint32_t *)0xfe007680)
+//32bits register to save the USR read command read back values.
+#define P_PSRAM_STATUS ((volatile uint32_t *)0xfe007684)
+//bit 31. usr_req_done flag. 1 : user request done . write 1 to clean.
+//bit 30~11.
+//bit 10:8
+//bit 7:3.
+//bit 2. axi_data buffer idle bit. 1 : idle. 0 : working.
+//bit 1. axi interface idle bit. 1 : idle. 0 : working.
+//bit 0. psram ctrl idle bit. 1 : idle. 0 : working.
+#define P_PSRAM_CTRL ((volatile uint32_t *)0xfe007688)
+//bit 31. PSRAM in DTR mode.
+//bit 30. psram input data latch clock select. 1: from clock input pin. 0: from DQS
+//if use clock input pin as data input latch clock, bit 13:12 should select 01.
+//bit 29:27. PSRAM mode.
+//'b000 : STR SPI mode.
+//'b001 : STR QPI mode.
+//'b010 : DTR QPI mode.
+//'b011 : DTR OPI FLASH.
+//'b100 : APmemory PSRAM mode.
+//'b101 : Winbond PSRAM mode.
+//bit 26. enable to generation interruption after usr request done. 1: enable. 0: disable.
+//bit 25. to enable APMEMORY 2 command cycle mode. 1 : enable : 0: 3 command cycles.
+//bit 24. to enable the psram clock output always enable. 1 : enable. 0: disable.
+//bit 23. to enable the psram clock output extend mode to cover APMEMORY tCPI.
+//bit 22. to disable the CKN output. 1: disable PSRAM CK_N pin output. 0: CK_N working normal.
+//bit 21. PSRAM DATA IN/OUT high 8bit and low 8 bit endian. 1 : rising edge is low byte. falling edge data is high byte. 0 : rising edge is high byte. falling edge data is low byte.
+//bit 20. PSRAM ADDRESS unit. 1: Byte. 0 : word.
+// APMEMORY used byte address. Winbond use word address.
+//bit 19. DQSEN generation. if use dqs to latch input data, this bit should be set to 1 to ask DMC generate ENABLE singal in dummy stage. 0: not generate DQS_EN.
+//bit 18. PSRAM RESET I/O oe_n value. if need RESET pin.
+//bit 17. PSRAM RESET I/O output vale. if need reset pin.
+//bit 16. force CS output low. for APMEMORY exit DPPD mode. 1: to force cs output low : 0 output normal working mode.
+//bit 13:12. psram data in clock enable selection. 00: use DQSEN. 01: use clkin cnt.
+//bit 11. DM Disable. 1: disable DM output. 0: with dmoutput.
+//bit 9. psram pctl auto clock gating enable. 1: enable. 0 : disable.
+//bit 8. psram pctl clock disable. 1: disable. 0 : enable.
+//bit 2 PSRAM SPI mode, DQ2 works as WP(write protection mode).
+//bit 1. DQ2 WP mode value.
+//bit 0. PSRAM SPI mode, DQ3 works as HOLD function.
+#define P_PSRAM_PIN_CTRL ((volatile uint32_t *)0xfe00768c)
+//bit 30:28 DATA 6 DQ pin selection.
+//bit 27:24 DATA 6 DQ pin selection.
+//bit 22:20 DATA 5 DQ pin selection.
+//bit 18:16 DATA 4 DQ pin selection.
+//bit 14:12 DATA 3 DQ pin selection.
+//bit 10:8 DATA 2 DQ pin selection.
+//bit 6:4 DATA 1 DQ pin selection.
+//bit 2:0 DATA 0 DQ pin selection.
+//0 : from DQ[0]
+//1 : from DQ[1]
+//2 : from DQ[2]
+//3 : from DQ[3]
+//4 : from DQ[4]
+//5 : from DQ[5]
+//6 : from DQ[6]
+//7 : from DQ[7]
+//psram_dly_16 is used for all DQ[0~] in/out/oen delay adjustment.
+//psram_dly_16 consists of 15 delay cells, one delay cell is 50ps delay( typical corner).
+//psram_dly_16 is control by delay_sel[3:0]. 0 = no delay. 1~15 controls how many delay cells used.
+//psram_dly_16 can be controlled by each control register either with real delay mode or VT updated with 4xclock period.
+//psram_lcdl is used for DQS/DQSN input and CK/CKN output delay 90degree delay generation and/or delay fine tune.
+//psram_lcdl consits of 96 delay cells, same delay cell used in psram_dly_16.
+//psram_lcdl should be calibrated with the psram_4xclock. and tracked with psram_4xclock with VT updated.
+#define P_PSRAM_DQ0_DIN_DLY ((volatile uint32_t *)0xfe007700)
+//bit 6:0. DQ0 DIN delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ1_DIN_DLY ((volatile uint32_t *)0xfe007704)
+//bit 6:0. DQ1 input delay control. in DLY16 read mode, only [3:0] is valid.
+#define P_PSRAM_DQ2_DIN_DLY ((volatile uint32_t *)0xfe007708)
+//bit 6:0. DQ2 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ3_DIN_DLY ((volatile uint32_t *)0xfe00770c)
+//bit 6:0. DQ3 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ4_DIN_DLY ((volatile uint32_t *)0xfe007710)
+//bit 6:0. DQ4 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ5_DIN_DLY ((volatile uint32_t *)0xfe007714)
+//bit 6:0. DQ5 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ6_DIN_DLY ((volatile uint32_t *)0xfe007718)
+//bit 6:0. DQ6 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ7_DIN_DLY ((volatile uint32_t *)0xfe00771c)
+//bit 6:0. DQ7 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ0_DOUT_DLY ((volatile uint32_t *)0xfe007720)
+//bit 6:0. DQ0 DOUT delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ1_DOUT_DLY ((volatile uint32_t *)0xfe007724)
+//bit 6:0. DQ1 output delay control. in DLY16 read mode, only [3:0] is valid.
+#define P_PSRAM_DQ2_DOUT_DLY ((volatile uint32_t *)0xfe007728)
+//bit 6:0. DQ2 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ3_DOUT_DLY ((volatile uint32_t *)0xfe00772c)
+//bit 6:0. DQ3 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ4_DOUT_DLY ((volatile uint32_t *)0xfe007730)
+//bit 6:0. DQ4 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ5_DOUT_DLY ((volatile uint32_t *)0xfe007734)
+//bit 6:0. DQ5 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ6_DOUT_DLY ((volatile uint32_t *)0xfe007738)
+//bit 6:0. DQ6 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ7_DOUT_DLY ((volatile uint32_t *)0xfe00773c)
+//bit 6:0. DQ7 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ0_OEN_DLY ((volatile uint32_t *)0xfe007740)
+//bit 6:0. DQ0 OEN delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ1_OEN_DLY ((volatile uint32_t *)0xfe007744)
+//bit 6:0. DQ1 output enable delay control. in DLY16 read mode, only [3:0] is valid.
+#define P_PSRAM_DQ2_OEN_DLY ((volatile uint32_t *)0xfe007748)
+//bit 6:0. DQ2 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ3_OEN_DLY ((volatile uint32_t *)0xfe00774c)
+//bit 6:0. DQ3 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ4_OEN_DLY ((volatile uint32_t *)0xfe007750)
+//bit 6:0. DQ4 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ5_OEN_DLY ((volatile uint32_t *)0xfe007754)
+//bit 6:0. DQ5 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ6_OEN_DLY ((volatile uint32_t *)0xfe007758)
+//bit 6:0. DQ6 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ7_OEN_DLY ((volatile uint32_t *)0xfe00775c)
+//bit 6:0. DQ7 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DM_DOUT_DLY ((volatile uint32_t *)0xfe007760)
+//bit 6:0. DM output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DM_OEN_DLY ((volatile uint32_t *)0xfe007764)
+//bit 6:0. DM output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_CS_DOUT_DLY ((volatile uint32_t *)0xfe007768)
+//bit 6:0. CS output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQS_DIN_DLY ((volatile uint32_t *)0xfe00776c)
+//bit 6:0. DQS input delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define P_PSRAM_DQSN_DIN_DLY ((volatile uint32_t *)0xfe007770)
+//bit 6:0. DQSN input delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define P_PSRAM_CKN_DOUT_DLY ((volatile uint32_t *)0xfe007774)
+//bit 6:0. CKN output delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define P_PSRAM_CK_DOUT_DLY ((volatile uint32_t *)0xfe007778)
+//bit 6:0. CK output delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define P_PSRAM_RDEN_DLY ((volatile uint32_t *)0xfe00777c)
+//bit 10:7. READ enable phase delay. unit = 1UI. for AP QPI PSRAM. PSRAM only send one cycle DQS preamble.
+// We have to used this UI delay to compensate the whole clock output delay and the DQS input delay.
+// if run high frequency, this delay need to be trained. the valid value from 0 ~ 12. Since one UI is 1/4 of PSRAM clock,
+// the total delay of the clock output delay + input delay should be less than 3 PSRAM clock.
+//bit 6:0. READ enable fine tune delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define P_PSRAM_LCDL_CTRL ((volatile uint32_t *)0xfe0077c0)
+//bit 31. write 1 to update all delay cell delays control.
+//bit 30. write 1 to calibration LCDL.
+//bit 29. LCDL track enable. 1: enable LCDL auto track VT changes.
+//bit 28. LCDL delay control mode.
+//1 : real delay mode. For DQS/DQSN/CKN/CK/RDEN delay control register, one number means one delay cells.
+//0 : UI MODE. For DQS/DQSN/CKN/CK/RDEN delay control register, one number means 1/64 psram_4xclk period.
+//bit 27. DLY16 ( psram_dly_16 cell) delay control mode.
+//1 : real delay mode. For all data delay control register, one number means one delay cells.
+//0 : UI MODE. For all data delay control register, one number means 1/64 psram_4xclk period.
+//bit 27:24. not used.
+//bit 23:0. timer do trigger LCDL track the VT once. each track will compensate the UI with 1/16 delay cell delay.
+//LCDL calibration ctroller.
+#define P_PSRAM_LCDL_CAL_CTRL1 ((volatile uint32_t *)0xfe0077c4)
+//27:24. which LCDL delay line used to run calibration.
+//19:16. LCDL calibration loop end position.
+//15:12. LCDL calibration loop initial position.
+//10:0. LCDL calibration initial phase counter.
+#define P_PSRAM_LCDL_CAL_CTRL2 ((volatile uint32_t *)0xfe0077c8)
+//26:16 LCDL phase lock limit. if the lcdl phase counter difference between 2 calibration loops is less than this number, The LCDL would be locked and stop the calibration.
+//10:0. deta_init. the first loop phase changing number.
+#define P_PSRAM_LCDL_CAL_CTRL3 ((volatile uint32_t *)0xfe0077cc)
+//29:25 to configure LCDL calibration step 5 position.
+//24:20 to configure LCDL calibration step 4 position.
+//19:15 to configure LCDL calibration step 3 position.
+//14:10 to configure LCDL calibration step 2 position.
+//9:5 to configure LCDL calibration step 1 position.
+//4:0 to configure LCDL calibration step 0 position.
+#define P_PSRAM_LCDL_CAL_CTRL4 ((volatile uint32_t *)0xfe0077d0)
+//19:15 to configure LCDL calibration step 9 position.
+//14:10 to configure LCDL calibration step 8 position.
+//9:5 to configure LCDL calibration step 7 position.
+//4:0 to configure LCDL calibration step 6 position.
+#define P_PSRAM_CLK_UI ((volatile uint32_t *)0xfe0077d4)
+//bit 6:0. 4xCLOCK period delay measured from LCDL calibration.
+#define P_PSRAM_LCDL_PH ((volatile uint32_t *)0xfe0077d8)
+//10:0 LCDL phase counter after calibration.
+#define P_PSRAM_LCDL_STATUS ((volatile uint32_t *)0xfe0077dc)
+//bit 31. LCDL lock status. 1: LCDL locked to 4x clock.
+//`endif
+//
+// Closing file: ../psram/rtl/psram_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_sec.vh
+//
+//`ifdef DMC_SEC_REG_DEFINE
+//`else
+//`define DMC_SEC_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd021000
+// -----------------------------------------------
+//`define DMC_SEC_REG_BASE 32'hfd021000
+// ID assignment inside DMC..
+// id[12 :0] total 13 bit ID.
+// id[12] == 1: for DMC internal TEST module.
+// id[12] == 0: for AXI port input.
+// id[11:0] == AXI port ID.
+// id[2:0] == 0 : A55 CPU.
+// id[2:0] == 1 : DSPA
+// id[2:0] == 2 : DSPB
+// id[2:0] == 3 : Not used.
+// id[2:0] == 4 : for Device.
+//Device sublevel ID.
+//id[9:7] == 5 : for audio. id[3] == 0: audio
+//id[9:7] == 6 : for DMA. id[6:4] for DMA thread id. id[3] for DMC security level.
+//id[9:7] == others: for device other masters.
+// id[2:0] == 5 : for USB device.
+// id[2:0] == 6 : for I2C debug input.
+// id[2:0] == 7 : for USB host.
+#define P_DMC_SEC_RANGE0_STA ((volatile uint32_t *)0xfd021000)
+//bit 31:12. range0 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE0_EDA ((volatile uint32_t *)0xfd021004)
+//bit 31:12. range0 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE0_RID_CTRL ((volatile uint32_t *)0xfd021008)
+//range 0 read access enable based on DMC ID assignments.
+//bit 28. for AXI port 3. Not used in A1. should be 0.
+//bit 27. for dmc_test. 1 = enable. 0 = disable.
+//bit 26. for usbhost. 1 = enable. 0 = disable.
+//bit 25. for i2c. 1 = enable. 0 = disable.
+//bit 24. for usbdevide. 1 = enable. 0 = disable.
+//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+//bit 22:18.for AXI device sub level id 5 ~ 0.
+//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0).
+//bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0).
+//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define P_DMC_SEC_RANGE0_WID_CTRL ((volatile uint32_t *)0xfd02100c)
+//range 0 write access enable based on DMC ID assignments.
+//bit 28. for AXI port 3. Not used in A1. should be 0.
+//bit 27. for dmc_test. 1 = enable. 0 = disable.
+//bit 26. for usbhost. 1 = enable. 0 = disable.
+//bit 25. for i2c. 1 = enable. 0 = disable.
+//bit 24. for usbdevide. 1 = enable. 0 = disable.
+//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+//bit 22:18.for AXI device sub level id 5 ~ 0.
+//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0).
+//bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5).
+//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define P_DMC_SEC_RANGE1_STA ((volatile uint32_t *)0xfd021010)
+//bit 31:12. range1 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE1_EDA ((volatile uint32_t *)0xfd021014)
+//bit 31:12. range0 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE1_RID_CTRL ((volatile uint32_t *)0xfd021018)
+//range 1 read access enable based on DMC ID assignments.
+//bit 28. for AXI port 3. Not used in A1. should be 0.
+//bit 27. for dmc_test. 1 = enable. 0 = disable.
+//bit 26. for usbhost. 1 = enable. 0 = disable.
+//bit 25. for i2c. 1 = enable. 0 = disable.
+//bit 24. for usbdevide. 1 = enable. 0 = disable.
+//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+//bit 22:18.for AXI device sub level id 5 ~ 0.
+//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0).
+//bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0).
+//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define P_DMC_SEC_RANGE1_WID_CTRL ((volatile uint32_t *)0xfd02101c)
+//range 1 write access enable based on DMC ID assignments.
+//bit 28. for AXI port 3. Not used in A1. should be 0.
+//bit 27. for dmc_test. 1 = enable. 0 = disable.
+//bit 26. for usbhost. 1 = enable. 0 = disable.
+//bit 25. for i2c. 1 = enable. 0 = disable.
+//bit 24. for usbdevide. 1 = enable. 0 = disable.
+//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+//bit 22:18.for AXI device sub level id 5 ~ 0.
+//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0).
+//bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5).
+//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define P_DMC_SEC_RANGE2_STA ((volatile uint32_t *)0xfd021020)
+//bit 31:12. range2 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE2_EDA ((volatile uint32_t *)0xfd021024)
+//bit 31:12. range2 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE2_RID_CTRL ((volatile uint32_t *)0xfd021028)
+//range 2 read access enable based on DMC ID assignments.
+//bit 28. for AXI port 3. Not used in A1. should be 0.
+//bit 27. for dmc_test. 1 = enable. 0 = disable.
+//bit 26. for usbhost. 1 = enable. 0 = disable.
+//bit 25. for i2c. 1 = enable. 0 = disable.
+//bit 24. for usbdevide. 1 = enable. 0 = disable.
+//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+//bit 22:18.for AXI device sub level id 5 ~ 0.
+//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0).
+//bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0).
+//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define P_DMC_SEC_RANGE2_WID_CTRL ((volatile uint32_t *)0xfd02102c)
+//range 2 write access enable based on DMC ID assignments.
+//bit 28. for AXI port 3. Not used in A1. should be 0.
+//bit 27. for dmc_test. 1 = enable. 0 = disable.
+//bit 26. for usbhost. 1 = enable. 0 = disable.
+//bit 25. for i2c. 1 = enable. 0 = disable.
+//bit 24. for usbdevide. 1 = enable. 0 = disable.
+//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+//bit 22:18.for AXI device sub level id 5 ~ 0.
+//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0).
+//bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5).
+//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define P_DMC_SEC_RANGE3_STA ((volatile uint32_t *)0xfd021030)
+//bit 31:12. range3 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE3_EDA ((volatile uint32_t *)0xfd021034)
+//bit 31:12. range3 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE3_RID_CTRL ((volatile uint32_t *)0xfd021038)
+//range 3 read access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE3_WID_CTRL ((volatile uint32_t *)0xfd02103c)
+//range 3 write access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE4_STA ((volatile uint32_t *)0xfd021040)
+//bit 31:12. range4 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE4_EDA ((volatile uint32_t *)0xfd021044)
+//bit 31:12. range4 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE4_RID_CTRL ((volatile uint32_t *)0xfd021048)
+//range 4 read access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE4_WID_CTRL ((volatile uint32_t *)0xfd02104c)
+//range 4 write access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE5_STA ((volatile uint32_t *)0xfd021050)
+//bit 31:12. range5 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE5_EDA ((volatile uint32_t *)0xfd021054)
+//bit 31:12. range5 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE5_RID_CTRL ((volatile uint32_t *)0xfd021058)
+//range 5 read access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE5_WID_CTRL ((volatile uint32_t *)0xfd02105c)
+//range 5 write access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE6_STA ((volatile uint32_t *)0xfd021060)
+//bit 31:12. range5 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE6_EDA ((volatile uint32_t *)0xfd021064)
+//bit 31:12. range6 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE6_RID_CTRL ((volatile uint32_t *)0xfd021068)
+//range 6 read access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE6_WID_CTRL ((volatile uint32_t *)0xfd02106c)
+//range 6 write access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+//range 7 is default range if the access not hit any of the previous 7 range, if would hit range 7.
+#define P_DMC_SEC_RANGE7_RID_CTRL ((volatile uint32_t *)0xfd021070)
+//range 7 read access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE7_WID_CTRL ((volatile uint32_t *)0xfd021074)
+//range 7 write access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE_CTRL ((volatile uint32_t *)0xfd021078)
+//bit 23:16 8 range security level. to chosse with DES KEY to use data describle.
+//bit 7:0 8 range enable. each bit for one range to indentify the range is enabled or not.
+//registers to check the security protection and watch point error information.
+#define P_DMC_DES_CTRL ((volatile uint32_t *)0xfd021080)
+//bit 1 data describle enable.
+//bit 0 wirte 1 to block DES CTRL and DES PADDING read/write.
+#define P_DMC_DES_PADDING ((volatile uint32_t *)0xfd021084)
+#define P_DMC_SEC_STATUS ((volatile uint32_t *)0xfd0212e0)
+//bit 31~2. not used.
+//bit 1 write security violation.
+//bit 0. read security violation.
+#define P_DMC_VIO_ADDR0 ((volatile uint32_t *)0xfd0212e4)
+//ddr0 write secure violation address.
+#define P_DMC_VIO_ADDR1 ((volatile uint32_t *)0xfd0212e8)
+//bit 31:18 . not used. always 0.
+//17 ddr0 secure check violation.
+//16 ddr0 write address overflow. write out of DDR size.
+//15:13. ddr0 write violation AWPROT bits.
+//12:0 ddr0_write violation ID. Please check ID assignment for ID bit defines.
+#define P_DMC_VIO_ADDR2 ((volatile uint32_t *)0xfd0212ec)
+//ddr0 write secure violation address.
+#define P_DMC_VIO_ADDR3 ((volatile uint32_t *)0xfd0212f0)
+//bit 31:18 . not used. always 0.
+//17 ddr0 secure check violation.
+//16 ddr0 read address overflow. write out of DDR size.
+//15:13. ddr0 read violation AWPROT bits.
+//12:0 ddr0_read violation ID. please ID assignment for ID bit defines.
+//DDR0_ADDRMAP is used for RANK0 bank, row, col address mapping from AXI 32bits linear address.
+#define P_DDR0_ADDRMAP_0 ((volatile uint32_t *)0xfd021340)
+//29:25 ca8.
+//24:20 ca7.
+//19:15 ca6.
+//14:10 ca5.
+//9:5 ca4.
+//4:0 ca3.
+#define P_DDR0_ADDRMAP_1 ((volatile uint32_t *)0xfd021344)
+//29:25 ra2.
+//24:20 ra1.
+//19:15 ra0.
+//14:10 ca11.
+//9:5 ca10.
+//4:0 ca9.
+#define P_DDR0_ADDRMAP_2 ((volatile uint32_t *)0xfd021348)
+//29:25 ra8.
+//24:20 ra7.
+//19:15 ra6.
+//14:10 ra5.
+//9:5 ra4.
+//4:0 ra3.
+#define P_DDR0_ADDRMAP_3 ((volatile uint32_t *)0xfd02134c)
+//29:25 ra14.
+//24:20 ra13.
+//19:15 ra12.
+//14:10 ra11.
+//9:5 ra10.
+//4:0 ra9.
+#define P_DDR0_ADDRMAP_4 ((volatile uint32_t *)0xfd021350)
+//29:25 ra16 for DDR4 SDRAM
+//24:20 bg1 for DDR4 SDRAM.
+//19:15 ba2. or bg0 for DDR4.
+//14:10 ba1.
+//9:5 ba0.
+//4:0 ra15.
+#define P_DMC_DDR_CTRL ((volatile uint32_t *)0xfd021368)
+// DDR PHY and DMC only supports 16bits and rank0 only.
+//bit 24:22 3'b000 : ddr3 mode.
+//3'b001 : ddr4 mode.
+//3'b010 : lpddr3 mode.
+//3'b011 : lpddr4 mode.
+//bit 20 DDR4 BG1 enable bit.
+//bit 3:0 : DDR rank 0 size bit [2:0].
+//4'b0000 : DDR rank 0 is 128Mbyte.
+//4'b0001 : DDR rank 0 is 256Mbyte.
+//4'b0010 : DDR rank 0 is 512Mbyte.
+//4'b0011 : DDR rank 0 is 1Gbyte.
+//4'b0100 : DDR rank 0 is 2Gbyte.
+//4'b0101 : DDR rank 0 is 4Gbyte.
+//4'b1000 : DDR rank 0 is 4Gbyte.
+//4'b1001 : DDR rank 0 is 4Gbyte.
+//others : reserved.
+#define P_DMC_APB_SEC_CTRL ((volatile uint32_t *)0xfd02136c)
+//bit 19:16. DMC normal APB register secure control.
+//bit 19: 1: all can write those register. 0: the APB_PROT[0] must match the bit 16 to access those regsiter.
+//Bit15:12. DMC sticky APB regsiter secure control.
+//bit 15. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 12 to access those register.
+//bit 11:8. not used.
+//Bit 7:4. DMC DDR SDRAM protocal contorl register contorl
+//bit 11. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 4 to access those register.
+//bit 3:0. PHY APB regsiter secure control.
+//bit 3. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 0 to access those register.
+#define P_DMC_DDR_PHY_CTRL ((volatile uint32_t *)0xfd0212fc)
+//bit 4 PwrOkIn
+//bit 3. PHY APB soft reset_n
+//bit 2. PHY soft reset_n
+//bit 1. PHY DfiClk enable.
+//bit 0. PHY DfiCtlClk enable.
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd021400
+// -----------------------------------------------
+//`define DMC_TEST_REG_BASE 32'hfd021400
+#define P_DMC_TEST_WRCMD_ADDR ((volatile uint32_t *)0xfd021770)
+// the current write cmd address.
+#define P_DMC_TEST_RDRSP_ADDR ((volatile uint32_t *)0xfd021774)
+// the failed read response address(for error data )
+#define P_DMC_TEST_RDCMD_ADDR ((volatile uint32_t *)0xfd021778)
+// the current read command address.
+#define P_DMC_TEST_WDG ((volatile uint32_t *)0xfd02177c)
+//31:16. write response watch dog.
+//15:0. read response watch dog.
+#define P_DMC_TEST_STA ((volatile uint32_t *)0xfd021780)
+//test start address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary.
+// for sha mode, address must be in 64 bytes boundary. that mean the last 6 bits must be 0.
+#define P_DMC_TEST_EDA ((volatile uint32_t *)0xfd021784)
+//test end address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary.
+// for sha mode, address must be in 64 bytes boundary. that mean the last 6bits must be 1.
+#define P_DMC_TEST_CTRL ((volatile uint32_t *)0xfd021788)
+//bit 31. enable test.
+//bit 30. when enable test, enable the write to DDR function.
+//bit 29. when enable test, enable the read from DDR function.
+//bit 28. Not used.
+//bit 27. enabe to compare data. when do the read enable to enable the error comparaion. suppose the read data should be same as the data in the write buffer.
+//bit 26. Not used.
+//bit 25. address generation type. 0: continuous increase the address in the range of test start address and test end address.
+// 1: test module would pick the random address from test start address and test end address.
+//bit 24. done type. 0 : use the DMC_TEST_NUM register as the counter of test numbers.
+// for write if the write command number == the DMC_TEST_NUM, the write is done.
+// for read if the read command number == the DMC TEST_num, the read id done. for one read command can be repeated repeat number times.
+// 1 : finshed at end address.
+//bit 23. wdata type. 1 : the first write is {WD3, WD2,WD1,WD0}, then the latter is the previous data plus a pattern.( { + WD7, + WD6, + WD5, + WD4}).
+// 0 : the WDATA is the data in write register.
+//bit 23. Not used.
+//bit 22:20. read repeat times. for non-sha function, we can define multi times of the read. the test module would repeat the same adddress repeat times.
+//bit 19. limit write. 0: no outstanding write request limitation.
+// 1: limit the outstanding write commands to the number of bits [15:8]
+//bit 18. limit read. 0. no outstanding read request limitation.
+// 1. limit the read outstanding request to the number of bits[7:0].
+//bit 17:16. Not used.
+//bit 15:8. write outstanding commands limit.
+//bit 7:0. read outstanding commands limit.
+#define P_DMC_TEST_NUM ((volatile uint32_t *)0xfd02178c)
+// how many test command for the test if the DMC_TEST_CTRL bit 24 is 0.
+#define P_DMC_TEST_WD0 ((volatile uint32_t *)0xfd021790)
+// write data 0 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD1 ((volatile uint32_t *)0xfd021794)
+// write data 1 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD2 ((volatile uint32_t *)0xfd021798)
+// write data 2 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD3 ((volatile uint32_t *)0xfd02179c)
+// write data 3 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD4 ((volatile uint32_t *)0xfd0217a0)
+// write data 4 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD5 ((volatile uint32_t *)0xfd0217a4)
+// write data 5 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD6 ((volatile uint32_t *)0xfd0217a8)
+// write data 6 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD7 ((volatile uint32_t *)0xfd0217ac)
+// write data 7 for write command. also for read back data comparision.
+#define P_DMC_TEST_RD0 ((volatile uint32_t *)0xfd0217b0)
+// the read back data 0. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD1 ((volatile uint32_t *)0xfd0217b4)
+// the read back data 1. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD2 ((volatile uint32_t *)0xfd0217b8)
+// the read back data 2. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD3 ((volatile uint32_t *)0xfd0217bc)
+// the read back data 3. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD4 ((volatile uint32_t *)0xfd0217c0)
+// the read back data 4. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD5 ((volatile uint32_t *)0xfd0217c4)
+// the read back data 5. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD6 ((volatile uint32_t *)0xfd0217c8)
+// the read back data 6. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD7 ((volatile uint32_t *)0xfd0217cc)
+// the read back data 7. if error happens, it would capture the first error data.
+#define P_DMC_TEST_ERR_ADDR ((volatile uint32_t *)0xfd0217d0)
+// it capature the first error address.
+#define P_DMC_TEST_ERR_CNT ((volatile uint32_t *)0xfd0217d4)
+// how many data error happens in the whole test period.
+#define P_DMC_TEST_STS ((volatile uint32_t *)0xfd0217d8)
+//bit 31, test done bit. write 1 to clean.
+//bit 30, indicate address err
+//bit 29~7. not used.
+//bit 6. read data resp error(caused by security or rd latency).
+//bit 5. test MRR/MPR rd latency error. write 1 clear
+//bit 4, sha done. write 1 to clean.
+//bit 3, write done. write 1 to clean.
+//bit 2, read done. write 1 to clean
+//bit 1, write watchdog triggered. write 1 to clean
+//bit 0, read watchdog triggered. write 1 to clean.
+#define P_DMC_TEST_COMP_MASK ((volatile uint32_t *)0xfd0214cc)
+//32bits for DMC TEST COMPARE bit enable.
+//1 : to MASK this bit. 0: compare this bit.
+#define P_DMC_TEST_RDBI0 ((volatile uint32_t *)0xfd0214d0)
+//MPC RD FIFO command DBI read back data
+//bit 31:16 the second cycle.
+//bit 15:0 the first cycle.
+#define P_DMC_TEST_RDBI1 ((volatile uint32_t *)0xfd0214d4)
+//MPC RD FIFO command DBI read back data
+//bit 31:16. the Forth cycle.
+//bit 15:0. the third cycle.
+#define P_DMC_TEST_WSTRB0 ((volatile uint32_t *)0xfd0214d8)
+//MPC WR FIFO command DM bit write data
+//bit 31:16 the second cycle.
+//bit 15:0 the first cycle.
+#define P_DMC_TEST_DRAM_CMD ((volatile uint32_t *)0xfd0214e0)
+//bit 31. cmd done. write 0 to clean.
+//bit 30. data done. write 0 to clean.
+//bit 4:0. only one bit can be 1. read data stored in DMC_TEST_RD* write data from DMC_TEST_W
+//bit 4. LPDDR4 MPC write data command( MPC WR FIFO). Not support LPDDR4 in A1.
+//bit 3. LPDDR4 MPC read data command (MPC RD Calibration and RD FIFO).Not support LPDDR4 in A1.
+//bit 2. LPDDR4 MPC-1 command ( NOP, Start DQS interval ....)Not support LPDDR4 in A1.
+//bit 1. mrr comand.
+//bit 0. mrw command.
+#define P_DMC_TEST_DRAM_CMD_CODE ((volatile uint32_t *)0xfd0214e4)
+//bit 27:26. 128bits data cycles . 0: 1 clock cycles; 1: 2 clock cycles; 2: 3 clock cycles; 3:4 clock cycles.
+// LPDDR4 32bits: 4 clock cycles; LPDDR4 16bits: 2 clock cycles;
+// DDR3/4/LPDDR3 32 bits : 2 clock cycles. DDR3/4 16bits: 1 cycles.
+//bit 25 MRW/MRR/MPC command rank 1 select. 1: select. 0: not select. In A1, only rank0 supported.
+//bit 24. MRW/MRR/MPC command rank 0 select. 1: select. 0: not select.In A1, only rank0 supported.
+//bit 23:16 MR addr. DDR4 case : 18:16 ba[2:0]. 20:19 BG[1:0].
+//bit 15:0 opcode.
+#define P_DMC_TEST_DRAM_CMD_TIME ((volatile uint32_t *)0xfd0214e8)
+//bit 31:16 PRE CMD timer. //delay how many cycle to start the command.
+//bit 15:0 POST CMD timer //delay how many cycle after the command execute.
+//`endif
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_sec.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_reg.vh
+//
+//`ifdef DMC_REG_DEFINE
+//`else
+//`define DMC_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd020000
+// -----------------------------------------------
+//`define DMC_REG_BASE 32'hfd020000
+#define P_DMC_SOFT_RST2 ((volatile uint32_t *)0xfd02000c)
+//bit 31~11. reserved for future.
+//bit 10 DMC DFI cmd soft reset_n
+//bit 9 DMC DFI MISC soft reset_n
+//bit 8 DMC DFI data soft reset_n
+//bit 7 DMC DFI dcu soft reset_n
+//bit 6 DMC siu soft reset_n
+//bit 5. DMC test soft reset_n. 0 : reset. 1 : normal working mode.
+//bit 4. DMC low power control moudle soft reset_n. 0 : reset. 1 : normal working mode.
+//bit 3. DMC QOS monitor module soft reset_n. 0 : reset. 1 : normal working mode.
+//bit 2. DMC register modle soft reset_n. 0 : reset. 1 : normal working mode.
+//bit 1. DMC canvas transfer module soft reset_n. 0 : reset. 1 : normal working mode.
+//bit 0. DMC command buffers and command generation modules soft reset. 0 = reset. 1:
+#define P_DMC_VERSION ((volatile uint32_t *)0xfd020014)
+//read only 32'h000b0000. for A1
+#define P_DMC_MON_CTRL0 ((volatile uint32_t *)0xfd020080)
+//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
+//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
+//bit 1. qos monitor 1 enable.
+//bit 0. qos monitor 0 enable.
+#define P_DMC_MON_CTRL1 ((volatile uint32_t *)0xfd020084)
+//bit 8:0. qos monitor 0 channel select.
+//bit 8 to select DMC TEST
+//bit 7:0 each bit enable one AXI subID.
+#define P_DMC_MON_CTRL2 ((volatile uint32_t *)0xfd020088)
+//bit 8. to enabe monitor 0 second level subID selection for example device.
+//bit 7:0 each bit to enable one second level subID inside device.
+#define P_DMC_MON_CTRL3 ((volatile uint32_t *)0xfd02008c)
+//bit 8:0. qos monitor 1 channel select.
+//bit 8 to select DMC TEST
+//bit 7:0 each bit enable one AXI subID.
+#define P_DMC_MON_CTRL4 ((volatile uint32_t *)0xfd020090)
+//bit 8. to enabe monitor 1 second level subID selection for example device.
+//bit 7:0 each bit to enable one second level subID inside device.
+#define P_DMC_MON_ALL_REQ_CNT ((volatile uint32_t *)0xfd0200a4)
+// at the test period, the whole MMC request time.
+#define P_DMC_MON_ALL_GRANT_CNT ((volatile uint32_t *)0xfd0200a8)
+// at the test period, the whole MMC granted data cycles. 64bits unit.
+#define P_DMC_MON_ONE_GRANT_CNT ((volatile uint32_t *)0xfd0200ac)
+// at the test period, the granted data cycles for the selected channel and ports.
+#define P_DMC_MON_SEC_GRANT_CNT ((volatile uint32_t *)0xfd0200b0)
+// at the test period, the granted data cycles for the selected channel and ports.
+#define P_DMC_MON_TIMER ((volatile uint32_t *)0xfd0200bc)
+// timer for the monitor period.
+#define P_DMC_CLKG_CTRL2 ((volatile uint32_t *)0xfd0200c8)
+//bit 10 enable auto clock gating for dfi command generation
+//bit 9 enable auto clock gating for dram cntroller
+//bit 8 enable auto clock gating for dfi data path.
+//bit 7. enalbe auto clock gating for write rsp generation.
+//bit 6. enalbe auto clock gating for read rsp generation.
+//bit 5. enalbe auto clock gating for ddr0 command filter.
+//bit 4. enalbe auto clock gating for ddr0 write reorder buffer.
+//bit 3. enalbe auto clock gating for ddr0 write data buffer.
+//bit 2. enalbe auto clock gating for ddr0 read reorder buffer.
+//bit 1. reserved
+//bit 0. reserved
+#define P_DMC_CLKG_CTRL3 ((volatile uint32_t *)0xfd0200cc)
+//bit 10 force to disable the clock of dfi command generation
+//bit 9 force to disable the clock of dram cntroller
+//bit 8 force to disable the clock of dfi data path.
+//bit 7. force to disalbe the clock of write rsp generation.
+//bit 6. force to disalbe the clock of read rsp generation.
+//bit 5. force to disalbe the clock of command filter.
+//bit 4. force to disalbe the clock of write reorder buffer.
+//bit 3. force to disalbe the clock of write data buffer.
+//bit 2. force to disalbe the clock of read reorder buffer.
+//bit 1. reserved.
+//bit 0. reserved.
+#define P_DMC_CHAN_STS ((volatile uint32_t *)0xfd0200d8)
+//bit 4 always 1
+//bit 3 ddr0 write data buffer idle. 1 : idle 0: busy.
+//bit 2 always 1.
+//bit 1 ddr0 wbuf idle. 1 : idle 0: busy.
+//bit 0. axi0 channel idle. 1 : idle 0: busy.
+#define P_DMC_CMD_FILTER_CTRL3 ((volatile uint32_t *)0xfd020108)
+//bit 31. force wbuf empty.
+//bit 30:26 wbuf high level number
+//bit 25:21 wbuf mid level number
+//bit 20:16 wbuf low level number
+//bit 14:10 rbuf high level number
+//bit 9:5 rbuf middle level number
+//bit 4:0 rbuf low level number
+#define P_DMC_CMD_FILTER_CTRL4 ((volatile uint32_t *)0xfd02010c)
+//bit 29:25. tITW.long
+//bit 24:20. tITW. short
+//bit 19:12 tAP auto precharge the bank not used if idle that long time.
+//bit 11:6 write to read accesses if there write hit request.
+//bit 5:0 read to write accesses if there write hit request.
+#define P_DMC_CMD_FILTER_CTRL5 ((volatile uint32_t *)0xfd020110)
+//bit 31:24 Once ddr data bus switch to read, the maxmum read command number to give up the bus when there's write request pending for write buffer.
+//bit 23:16 Once ddr data bus switch to write, the maxmum write command number to give up the bus when there's read request pending too long.
+//bit 15:8. Once ddr data bus switch to read, the minimum read command number to transfer back to write stage if there's still pending read request.
+//bit 7:0. Once ddr data bus switch to write, the minimum write command number to transfer back to read stage if there's still pending write request.
+#define P_DMC_CMD_FILTER_CTRL6 ((volatile uint32_t *)0xfd020114)
+//bit 31:24 write urgent 3 request pending hold num.
+//bit 23:16 write urgent 2 request pending hold num.
+//bit 15:8. write urgent 1 request pending hold num.
+//bit 7:0. write urgent 0 request pending hold num.
+#define P_DMC_CMD_FILTER_CTRL7 ((volatile uint32_t *)0xfd020118)
+//bit 15:8 write to read waiting cycles if there write hit request.
+//bit 7:0 read to write waiting cycles if there write hit request.
+#define P_DMC_CMD_BUFFER_CTRL ((volatile uint32_t *)0xfd02011c)
+//bit 31:26 total write buffer number. default 32.
+//bit 25:20 total read buffer number. default 32.
+//bit 19:8 reserved.
+//bit 7:0 aw_pending_inc_num. incease write ugent level 1 when write command waiting to in write buffer that long.
+#define P_DMC_CMD_BUFFER_CTRL1 ((volatile uint32_t *)0xfd020120)
+//bit 29:24 read buffer number in non-urgent request.
+//bit 23:16 read buffer bank miss watch dog threshold.
+//bit 15:12 read buffer urgent level 3 counter inc weight.
+//bit 11:8 read buffer urgent level 2 counter inc weight.
+//bit 7:4 read buffer urgent level 1 counter inc weight.
+//bit 3:0 read buffer urgent level 0 counter inc weight.
+#define P_DMC_AXI0_CHAN_CTRL ((volatile uint32_t *)0xfd020200)
+//bit 31 AXI interface request enable.
+//bit 19 AXI interface auto clock gating enable. 1: enable; 0 disable.
+//bit 18 AXI interface clock disable. 1 : disable clock. 0 enable clock.
+//bit 17 AXI interface dmc clock domain soft reset. 0 : reset. 1 : normal working mode.
+//bit 16 AXI interface s0 clock domain soft reset. 0 : reset. 1 : normal working mode.
+//bit 15:12 ugt3 QOS level.
+//bit 11:8 ugt2 QOS level.
+//bit 7:4 ugt1 QOS level.
+//bit 3:0 not used.
+#define P_DMC_AXI0_HOLD_CTRL ((volatile uint32_t *)0xfd020204)
+//31:24 write hold num. max outstanding request number.
+//23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+//15:8 read hold num. max outstanding request number.
+//7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define P_DMC_AXI5_HOLD_CTRL ((volatile uint32_t *)0xfd020254)
+//31:24 write hold num. max outstanding request number.
+//23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+//15:8 read hold num. max outstanding request number.
+//7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+//`endif
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh
+//
+//`ifdef DMC_SIU_REG_DEFINE
+//`else
+//`define DMC_SIU_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd020400
+// -----------------------------------------------
+//`define DMC_DRAM_REG_BASE 32'hfd020400
+//in A1 project, don't support hardware controlled frequency change.
+#define P_DMC_DRAM_TMRD ((volatile uint32_t *)0xfd020400)
+//bit 3:0. tMRD.
+#define P_DMC_DRAM_TRFC ((volatile uint32_t *)0xfd020404)
+//bit 9:0 tRFC
+#define P_DMC_DRAM_TRP ((volatile uint32_t *)0xfd020408)
+//bit 21:16. tRP for precharge all banks.
+//bit 5:0. tRP for precharge one bank.
+#define P_DMC_DRAM_TRTW ((volatile uint32_t *)0xfd02040c)
+//bit 5:0 tRTW
+#define P_DMC_DRAM_TCL ((volatile uint32_t *)0xfd020410)
+//bit 5:0 tCL/tRL. read latency.
+#define P_DMC_DRAM_TCWL ((volatile uint32_t *)0xfd020414)
+//bit 5:0. CWL: write latency.
+#define P_DMC_DRAM_TRAS ((volatile uint32_t *)0xfd020418)
+//bit 7:0. tRAS. minimum active to precharge time for same bank.
+#define P_DMC_DRAM_TRC ((volatile uint32_t *)0xfd02041c)
+//bit 7:0. tRC. minimum active to active time for same bank.
+#define P_DMC_DRAM_TRCD ((volatile uint32_t *)0xfd020420)
+//bit 7:0 tRCD active to read/write timing for same bank.
+#define P_DMC_DRAM_TRRD ((volatile uint32_t *)0xfd020424)
+//bit 21:16. tRRD_l active bank A to active B in same band group for DDR4.
+//bit 5:0. tRRD/tRRD_s active bank A to active bank b time.
+//tRRD_s: active bank A to active bank b in different bank grousp for DDR4.
+#define P_DMC_DRAM_TFAW ((volatile uint32_t *)0xfd020428)
+//bit 8:0 tFAW. four active command windows
+#define P_DMC_DRAM_TRTP ((volatile uint32_t *)0xfd02042c)
+//bit 5:0 tRTP.
+#define P_DMC_DRAM_TWR ((volatile uint32_t *)0xfd020430)
+//bit 5:0 tWR.
+#define P_DMC_DRAM_TWTR ((volatile uint32_t *)0xfd020434)
+//bit 5:0 tWTR.
+#define P_DMC_DRAM_TCCD ((volatile uint32_t *)0xfd020438)
+//bit 19:16. tCCD/tCCD_l.
+//bit 3:0 tCCD/tCCD_s read to read command time or write to write command time.
+#define P_DMC_DRAM_TEXSR ((volatile uint32_t *)0xfd02043c)
+//bit 9:0. tEXSR. EXIT SELF-REFRESH to read/write command.
+#define P_DMC_DRAM_TXS ((volatile uint32_t *)0xfd020440)
+//bit 9:0 tXS. EXIT SELF_REFRESH to other command time
+#define P_DMC_DRAM_TXP ((volatile uint32_t *)0xfd020444)
+//bit 3:0. tXP. EXIT power down to other command time
+#define P_DMC_DRAM_TXPDLL ((volatile uint32_t *)0xfd020448)
+//bit 9:0. tXPDLL, EXIT power down to read/write command time(need to relock PLL).
+#define P_DMC_DRAM_TZQCS ((volatile uint32_t *)0xfd02044c)
+//bit 11:0. ZQCS command to other command time.
+#define P_DMC_DRAM_TCKSRE ((volatile uint32_t *)0xfd020450)
+//bit 4:0. enter self refresh to disable clock time.
+#define P_DMC_DRAM_TCKSRX ((volatile uint32_t *)0xfd020454)
+//bit 4:0. enable clock to exit self refresh time.
+#define P_DMC_DRAM_TCKE ((volatile uint32_t *)0xfd020458)
+//bit 4:0. CKE high or low minimum time.
+#define P_DMC_DRAM_TMOD ((volatile uint32_t *)0xfd02045c)
+//bit 4:0 tMOD. MRR/MRW to other command time.
+#define P_DMC_DRAM_TDQS ((volatile uint32_t *)0xfd020460)
+//bit 3:0 tDQS. the delay to access different rank.
+#define P_DMC_DRAM_TRSTL ((volatile uint32_t *)0xfd020464)
+//not used.
+#define P_DMC_DRAM_TZQLAT ((volatile uint32_t *)0xfd020468)
+//bit 5:0 ZQ LATCH command to other comand timing in LPDDR4 mode.
+#define P_DMC_DRAM_TMRR ((volatile uint32_t *)0xfd02046c)
+//bit 7:0 tMRR not used in DMC. not support MR READ.
+#define P_DMC_DRAM_TCKESR ((volatile uint32_t *)0xfd020470)
+//bit 9:0 tCKESR. CKE low minimum pulse in self refresh mode.
+#define P_DMC_DRAM_TDPD ((volatile uint32_t *)0xfd020474)
+//not support.
+#define P_DMC_DRAM_DFITCTRLDELAY ((volatile uint32_t *)0xfd020478)
+//bit 3:0. DFI_t_ctrldealy
+#define P_DMC_DRAM_DFITPHYWRDATA ((volatile uint32_t *)0xfd02047c)
+//bit 5:0. dfi_t_phy_wrdata.
+#define P_DMC_DRAM_DFITPHYWRLAT ((volatile uint32_t *)0xfd020480)
+//bit 5:0. dfi_t_phy_wrlat. in DDR3/4/LPDDR3 mode: WL -5. in LPDDR4 mode: WL -5 + 2.
+#define P_DMC_DRAM_DFITRDDATAEN ((volatile uint32_t *)0xfd020484)
+//bit 5:0. dfi_t_rddata_en. in DDR3/4/LPDDR3 mode: RL -5. in LPDDR4 mode : RL -5 + 1.
+#define P_DMC_DRAM_DFITPHYRDLAT ((volatile uint32_t *)0xfd020488)
+//bit 5:0. dfi_t_rdlat.
+#define P_DMC_DRAM_DFITCTRLUPDMIN ((volatile uint32_t *)0xfd02048c)
+//bit 7:0. CTRLUPD_MIN minimux clock cycle to maintain CTRLUPD_REQ.
+#define P_DMC_DRAM_DFITCTRLUPDMAX ((volatile uint32_t *)0xfd020490)
+//bit 7:0 CTRLUPD_MAX. maxmum clock cycle to maintain CTRLUPD_REQ if no CTRLUPD_ACK response.
+#define P_DMC_DRAM_DFITMSTRRESP ((volatile uint32_t *)0xfd020494)
+//not used.
+#define P_DMC_DRAM_DFITREFMSKI ((volatile uint32_t *)0xfd020498)
+//not used.
+#define P_DMC_DRAM_DFITCTRLUPDI ((volatile uint32_t *)0xfd02049c)
+//not used.
+#define P_DMC_DRAM_DFITDRAMCLK ((volatile uint32_t *)0xfd0204a0)
+//bit 17 dram clk1 enable.
+//bit 16 dram clk0 enable.
+//bit 15:8 DRAM CLK disable waiting time
+//bit 7:0 DRAM CLK enable enable timer
+#define P_DMC_DRAM_DFITLPRESP ((volatile uint32_t *)0xfd0204a8)
+//bit 3:0. dfi_lp_ctrl_req response time. after dfi_lp_ctrl_req asserted, and after response time if there's still no dfi_lp_ack respone, then drop the dfi_lp_ctrl_req.
+#define P_DMC_DRAM_DFITPHYMSTR ((volatile uint32_t *)0xfd0204ac)
+//bit 15 1: enable DFIPHYMASTER INTERFACE 0 disable DFIPHYMSTR en response.
+// always 0 we would use DFI_RETRAIN function for PHY retrain required from LPDDR4.
+#define P_DMC_DRAM_TCKECK ((volatile uint32_t *)0xfd0204b0)
+//bit 4:0. tCKECK from CKE low to assert dfi_dram_clk_disable time. this time + dfi_t_ctrl_delay
+#define P_DMC_DRAM_TREFI ((volatile uint32_t *)0xfd0204b4)
+//write this register will update the auto refresh related register to the auto refresh control logic.
+//bit 31:24: tZQCI dmc send zqci period. unit is how much auto refresh period.
+//bit 23:16 pvti dmc send dfi_ctrlupd_req period. unit is one auto refresh period.
+//bit 15:8. tREFI.dmc send auto refresh command period. unit is 100ns.
+//bit 7:0. t100ns period. unit is dmc clock cycles
+#define P_DMC_DRAM_TSR ((volatile uint32_t *)0xfd0204b8)
+//bit 5:0 tSR. self resfresh enter to exit time.
+#define P_DMC_DRAM_TCCDMW ((volatile uint32_t *)0xfd0204bc)
+//bit 5:0. 4*tCCD in LPDDR4 mask write.
+#define P_DMC_DRAM_TESCKE ((volatile uint32_t *)0xfd0204c0)
+//bit 5:0 tESCKE. enter self refresh to power time for LPDDR4.
+#define P_DMC_DRAM_TREFI_DDR3 ((volatile uint32_t *)0xfd0204c4)
+//7:0. 8*DDR3 SDRAM tREFI time . the unit is t100ns. use this to check in 8*tREFI time, the DMC should sent more than 16 auto REFRESH command.
+#define P_DMC_DRAM_TZQCAL ((volatile uint32_t *)0xfd0204c8)
+//7:0. ZQCAL for LPDDR4.
+#define P_DMC_DRAM_T10US ((volatile uint32_t *)0xfd0204cc)
+//10us clock cycle number used for LP2 mode.
+#define P_DMC_DRAM_TMRRI ((volatile uint32_t *)0xfd0204d0)
+//bit 7:0 tMRRI for MRR
+#define P_DMC_DRAM_DFITPHYUPDTYPE0 ((volatile uint32_t *)0xfd020600)
+//dfi_phyupd_ack hold time for dfi_phyupd_req type = 0.
+#define P_DMC_DRAM_DFITPHYUPDTYPE1 ((volatile uint32_t *)0xfd020604)
+//dfi_phyupd_ack hold time for dfi_phyupd_req type = 1.
+#define P_DMC_DRAM_DFITPHYUPDTYPE2 ((volatile uint32_t *)0xfd020608)
+//dfi_phyupd_ack hold time for dfi_phyupd_req type = 2.
+#define P_DMC_DRAM_DFITPHYUPDTYPE3 ((volatile uint32_t *)0xfd02060c)
+//dfi_phyupd_ack hold time for dfi_phyupd_req type = 3.
+#define P_DMC_DRAM_DFIODTCFG ((volatile uint32_t *)0xfd020610)
+//bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity.
+//bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1.
+//bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0.
+//bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1.
+//bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0.
+//bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity.
+//bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0.
+//bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1.
+//bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0.
+//bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1.
+#define P_DMC_DRAM_DFIODTCFG1 ((volatile uint32_t *)0xfd020614)
+//bit 27:24 ODT length for BL8 read transfer.
+//bit 19:16. ODT length for BL8 write transfer.
+//bit 12:8. ODT latency for reads. suppose to be 0.
+//bit 4:0. ODT latency for writes. suppose to be 0.
+#define P_DMC_DRAM_MCFG ((volatile uint32_t *)0xfd020618)
+//bit 14. 1: cke init low. 0 : cke init high.
+//bit 13 1: dbi write enable only for LPDDR4.
+//bit 12. 1: dbi read inversion. 0: dbi read high inversion.
+//bit 11. 1: dbi read enable. 0: dbi not enabled.
+//bit 10 1: enable staggered chip select for 2 ranks DRAM.
+//bit 9 1: enable send auto refresh command to DDR SDRAM when PCTL is in CFG/STOP state.
+//bit 8 send auto refr cmd before enter register triggered self refresh
+//bit 7 send auto refr cmd after exit regsiter triggered self refresh mode.
+//bit 6 disable dram clock after enter register triggered self refresh.
+//bit 5 send DFI_LP_REQ to PHY after enter register triggered elf refresh mode.
+//bit 4 send DRAM to power down mode after enter self refresh. ONLY for LPDDR4.
+//bit 3 send DFI_CTRLUPD_REQ after exit register triggered self refresh.
+//bit 2 send ZQCS command after exit register triggered self refresh.
+//bit 1 enable PHY triggered DFI_PHYUPD_REQ.
+//bit 0 2T mode. always 1 in DDR3/4 mode.
+#define P_DMC_DRAM_DFI_CTRL ((volatile uint32_t *)0xfd020624)
+//bit 31 siu_dfi_lat err generation enable. 1: if dfi read latency violation, generate data error. 0 : disable.
+//bit 30:0. not used.
+#define P_DMC_DRAM_DFIINITCFG ((volatile uint32_t *)0xfd020628)
+//bit 31. dfi_init_complete status. read only.
+//bit 15:14. Frequency set 1 dfi_freq_ratio value. Not used in A1
+//bit 12:8 Frequency set 1 dfi_freq value. Not used in A1
+//bit 7:6 Frequency set 0 dfi_freq_ratio value.
+//bit 5:1 Frequency set 0 dfi_freq value.
+//bit 0. dfi_init_start value can be use manually config dfi_init_start signal.
+#define P_DMC_DRAM_ZQ_CTRL ((volatile uint32_t *)0xfd02062c)
+// only bit 0 can be enable in A1.
+//bit 2 send ZQCS command to RANK0 then send comand to RANK1.
+//bit 1. send ZQCS command to both RANK0 and RANK1 together.
+//bit 0. send ZQCS command to only rank0.
+#define P_DMC_DRAM_APD_CTRL ((volatile uint32_t *)0xfd020630)
+//bit 19:16 DFI_LP_WAKEUP value in APD DFI_LP_REQ mode
+//bit 12 1: exit power down slow mode(waiting PLL LOCK). 0 : fast mode.
+//bit 11 enable DFI_LP_REQ when enter Auto power down mode.
+//bit 10 disable DFI_clk_disable when enter auto power down mode.
+//bit 9:0 0 disable auto power down mode.
+//non zero value to enable auto power down when DMC is in idle state for this number of clock cycles.
+#define P_DMC_DRAM_ASR_CTRL ((volatile uint32_t *)0xfd020634)
+//bit [25] LP2 mode PHYCLK enable. 1 : keep PHY clock enable after enter LP2 mode. 0 : shutdown PHY clock after enter LP2 mode.
+//bit [24] LP2 mode SRX waiting enable. if Self refresh too long, waiting 10us for the PHY stable before DDR SDRAM exit from self refresh state.
+//bit [23:20] DFI_LP_WAKEUP value in self refresh DFI_LP_REQ mode.
+//bit 17 : send REFRESH command after exit from auto self refersh mode(ASR).
+//bit 16 : send REFERSH command before enter to Auto self refresh mode(ASR).
+//bit 15 : send ZQCS command after exit from Auto self refresh mode(ASR).
+//bit 14 : send dfi_ctrl_upd after exit from ASR mode
+//bit 13 : send power down command when enter ASR mode. //for LPDDR4 only.
+//bit 12 : set the PHY enter LP2 mode after enter ASR mode.
+//bit 11 : send DFI_LP_REQ after enter ASR mode.
+//bit 10 : set DFI_CLK_DISABLE after enter ASR mode.
+//bit 9:0. 0 disable auto ASR mode.
+// Non-zero valule enable ASR mode. when DMC is in idle state for this number of clock cycles, the DMC will enter ASR mode.
+#define P_DMC_DRAM_PHYMSTR_CTRL ((volatile uint32_t *)0xfd020640)
+//not used in A1. should be all 0.
+#define P_DMC_DRAM_DFIODTRANKMAP ((volatile uint32_t *)0xfd020644)
+//not used in A1.
+#define P_DMC_DRAM_REFR_CTRL ((volatile uint32_t *)0xfd020648)
+//bit 17:8 auto refresh request pending cnt if there's page hit request.
+//bit 6 Disabled auto refresh command if over 16 auto refresh command sent in 2 TREFI_DDR3 period
+//bit 5 enable dmc send ZQCS command .
+//bit 4. enable dmc send DFI_CTRUPD_REQ.
+//bit 3:1. how many refresh command send for one period. = this number + 1
+//bit 0. enable dmc send auto refresh command.
+#define P_DMC_DRAM_FREQ_CTRL ((volatile uint32_t *)0xfd02064c)
+//bit 31 . wiret 1 to change freqency read 0: finished.
+//bit 30:9. not used.
+//bit 9. 1 : FREQ MRW done. let FREQ change machine continue.
+//bit 8 FREQ WAIT. 1 when freq change finishes, state machine stop at self refresh state in case there's something need to handle.
+// 0 after freq change finishes the state machine go back to access state.
+//bit 7 when change PLL setting, disable dmc clock
+//bit 6 when change PLL setting, disable PHY DfiClk and DfiCtlClk.
+//bit 5 check vpu_sleep_en ==1 when do FREQ change. if vpu_sleep_en == 0, just wait.
+//bit 4 nxt frequency selection. 1 = freq1. 0 = freq0.
+//bit 3:1. not used.
+//bit 0. current frequency selection.
+#define P_DMC_DRAM_SCFG ((volatile uint32_t *)0xfd020650)
+// bit 2:0 only one bit can be high at same time.
+// bit 2 1 : to ask PCTL enter ACCESS STATE. 0 : deassert the request.
+// bit 1 1 : to ask PCTL enter SELF REFRESH STATE. 0 : deassert the request.
+// bit 0 1 : to ask PCTL enter STOP/CONFIG STATE . 0 : deassert the request.
+#define P_DMC_DRAM_STAT ((volatile uint32_t *)0xfd020654)
+//bit 31 rd latency error. 1: means after dfiphytrdlat cycles, the read data still not back.
+//bit 28:24 dram_sr_state
+//bit 23:20 stop_st
+//bit 19:15 sleep_st
+//bit 14:12 ACCESS STATUS 0 : ACCESS is in normal working mode.
+//1 : ACCESS sending precharege command.
+//2 : ACCESS sending AUTO REFESH command.
+//3 : ACCESS sending DIF_CTRLUPD_REQ command.
+//4 : ACCESS sending ZQCS command to DDR DRAM(ZQCAL for LPDDR4).
+//5 : ACCESS sending ZQLATCH command to LPDDR4 only.
+//bit 11:8 APD STATUS: 0 : APD_IDLE
+//1 : APD sending PRECHARGE command
+//2 : APD sending CKE low command
+//3 : APD sending DISABLE DRAM CLOCK command
+//4 : APD sending DFI_LP_CTRL_REQ
+//5 : APD in Auto Power down mode.
+//6 : APD deassert DFI_LP_CTRL_REQ
+//7 : APD sending enable DRAM CLOCK command
+//8 : APD sending out CKE high command.
+//bit 7:4: DRAM_STATUS: 0 : DRAM IDLE
+//1 : DRAM_STOP/DRAM_CFG
+//2 : DRAM_ACCESS
+//3 : DRAM_SLEEP
+//4 : DRAM APD(AUTO POWER DOWN).
+//5 : IDLE -> STOP/CONFIG
+//6 : STOP -> SLEEP
+//7 : STOP -> ACCESS
+//8 : ACCESS -> SLEEP.
+//9 : ACCESS -> STOP
+//A : ACCESS -> APD
+//B : SLEEP -> STOP
+//C : SLEEP -> ACCESS
+//D : APD -> ACCESS
+//bit 3 reserved.
+//bit 2 1 : DRAM enter normal working state.
+//bit 1 1 : DRAM enter sleep state. self refresh state.
+//bit 0 1 : dram enter cfg state.
+#define P_DMC_DRAM_STAT1 ((volatile uint32_t *)0xfd020658)
+//bit 11:8 freq_st.
+//bit 7:5 train_st
+//bit 4:0 dram_phy_st
+#define P_DMC_PHY_RETRAINING_CTRL ((volatile uint32_t *)0xfd02065c)
+// A1 not support LPDDR4 so this register is not used in A1.
+//bit 31 : phy_retraining enable.
+//bit 30 : check vpu sleep_en.
+//bit 25:24 : retraining dfi_freq[4:3], the [2:0] bit still use the dfi_freq bits to keep the frequency.
+//bit 23:0: retraining period unit : 100ns.
+#define P_DMC_DFI_ERR_STAT ((volatile uint32_t *)0xfd020660)
+//LPDDR4 PHY DFI error infomation.
+//bit 31:20. not used.
+//bit 9. ddr0_dfi_error
+//bit 8:5 ddr0_dfi_error_info.
+//bit 4. ddr1_dfi_error.
+//bit 3:0. ddr1_dfi_error_info.
+#define P_DMC_LP2_TIMER ((volatile uint32_t *)0xfd020668)
+//bit 15:0. timer setting to measure how long the chip is entered LP2 mode.
+//this timer is 40bits counter with DMC PCLK.
+//we use the high 16bits to compare this register. if the counter is large than this number, that means the PHY need addition 10us after wakeup the PHY and before exit self_refresh mode.
+#define P_DMC_DRAM_DFI_SWAP_0 ((volatile uint32_t *)0xfd020680)
+//bit 5:0. dfi_act_n function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_1 ((volatile uint32_t *)0xfd020684)
+//bit 5:0. dfi_ras_n function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_2 ((volatile uint32_t *)0xfd020688)
+//bit 5:0. dfi_cas_n function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_3 ((volatile uint32_t *)0xfd02068c)
+//bit 5:0. dfi_we_n function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_4 ((volatile uint32_t *)0xfd020690)
+//bit 5:0. dfi_bg0 function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_5 ((volatile uint32_t *)0xfd020694)
+//bit 5:0. dfi_bg[1] function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_6 ((volatile uint32_t *)0xfd020698)
+//bit 5:0. dfi_ba[0] function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_7 ((volatile uint32_t *)0xfd02069c)
+//bit 5:0. dfi_ba[1] function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_8 ((volatile uint32_t *)0xfd0206a0)
+//bit 5:0. dfi_ba[2] function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_9 ((volatile uint32_t *)0xfd0206a4)
+//bit 5:0. dfi_a[0] function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_10 ((volatile uint32_t *)0xfd0206a8)
+//bit 5:0. dfi_a[1] function select
+#define P_DMC_DRAM_DFI_SWAP_11 ((volatile uint32_t *)0xfd0206ac)
+//bit 5:0. dfi_a[2] function select
+#define P_DMC_DRAM_DFI_SWAP_12 ((volatile uint32_t *)0xfd0206b0)
+//bit 5:0. dfi_a[3] function select
+#define P_DMC_DRAM_DFI_SWAP_13 ((volatile uint32_t *)0xfd0206b4)
+//bit 5:0. dfi_a[4] function select
+#define P_DMC_DRAM_DFI_SWAP_14 ((volatile uint32_t *)0xfd0206b8)
+//bit 5:0. dfi_a[5] function select
+#define P_DMC_DRAM_DFI_SWAP_15 ((volatile uint32_t *)0xfd0206bc)
+//bit 5:0. dfi_a[6] function select
+#define P_DMC_DRAM_DFI_SWAP_16 ((volatile uint32_t *)0xfd0206c0)
+//bit 5:0. dfi_a[7] function select
+#define P_DMC_DRAM_DFI_SWAP_17 ((volatile uint32_t *)0xfd0206c4)
+//bit 5:0. dfi_a[8] function select
+#define P_DMC_DRAM_DFI_SWAP_18 ((volatile uint32_t *)0xfd0206c8)
+//bit 5:0. dfi_a[9] function select
+#define P_DMC_DRAM_DFI_SWAP_19 ((volatile uint32_t *)0xfd0206cc)
+//bit 5:0. dfi_a[10] function select
+#define P_DMC_DRAM_DFI_SWAP_20 ((volatile uint32_t *)0xfd0206d0)
+//bit 5:0. dfi_a[11] function select
+#define P_DMC_DRAM_DFI_SWAP_21 ((volatile uint32_t *)0xfd0206d4)
+//bit 5:0. dfi_a[12] function select
+#define P_DMC_DRAM_DFI_SWAP_22 ((volatile uint32_t *)0xfd0206d8)
+//bit 5:0. dfi_a[13] function select
+#define P_DMC_DRAM_DFI_SWAP_23 ((volatile uint32_t *)0xfd0206dc)
+//bit 5:0. dfi_a[14] function select
+#define P_DMC_DRAM_DFI_SWAP_24 ((volatile uint32_t *)0xfd0206e0)
+//bit 5:0. dfi_a[15] function select
+#define P_DMC_DRAM_DFI_SWAP_25 ((volatile uint32_t *)0xfd0206e4)
+//bit 5:0. dfi_a[16] function select
+#define P_DMC_DRAM_DFI_SWAP_26 ((volatile uint32_t *)0xfd0206ec)
+//bit 5:0. dfi_a[17] function select
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh
+//
+//`ifdef DMC_STICKY_REG_DEFINE
+//`else
+//`define DMC_STICKY_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd020800
+// -----------------------------------------------
+//`define DMC_STICKY_REG_BASE 32'hfd020800
+//those register is for software save some tempary value. and because it's in RAM. it won't lose if DMC get reseted.
+#define P_DMC_STICKY_0 ((volatile uint32_t *)0xfd020800)
+#define P_DMC_STICKY_1 ((volatile uint32_t *)0xfd020804)
+#define P_DMC_STICKY_2 ((volatile uint32_t *)0xfd020808)
+#define P_DMC_STICKY_3 ((volatile uint32_t *)0xfd02080c)
+#define P_DMC_STICKY_4 ((volatile uint32_t *)0xfd020810)
+#define P_DMC_STICKY_5 ((volatile uint32_t *)0xfd020814)
+#define P_DMC_STICKY_6 ((volatile uint32_t *)0xfd020818)
+#define P_DMC_STICKY_7 ((volatile uint32_t *)0xfd02081c)
+#define P_DMC_STICKY_8 ((volatile uint32_t *)0xfd020820)
+#define P_DMC_STICKY_9 ((volatile uint32_t *)0xfd020824)
+#define P_DMC_STICKY_10 ((volatile uint32_t *)0xfd020828)
+#define P_DMC_STICKY_11 ((volatile uint32_t *)0xfd02082c)
+#define P_DMC_STICKY_12 ((volatile uint32_t *)0xfd020830)
+#define P_DMC_STICKY_13 ((volatile uint32_t *)0xfd020834)
+#define P_DMC_STICKY_14 ((volatile uint32_t *)0xfd020838)
+#define P_DMC_STICKY_15 ((volatile uint32_t *)0xfd02083c)
+#define P_DMC_STICKY_16 ((volatile uint32_t *)0xfd020840)
+#define P_DMC_STICKY_17 ((volatile uint32_t *)0xfd020844)
+#define P_DMC_STICKY_18 ((volatile uint32_t *)0xfd020848)
+#define P_DMC_STICKY_19 ((volatile uint32_t *)0xfd02084c)
+#define P_DMC_STICKY_20 ((volatile uint32_t *)0xfd020850)
+#define P_DMC_STICKY_21 ((volatile uint32_t *)0xfd020854)
+#define P_DMC_STICKY_22 ((volatile uint32_t *)0xfd020858)
+#define P_DMC_STICKY_23 ((volatile uint32_t *)0xfd02085c)
+#define P_DMC_STICKY_24 ((volatile uint32_t *)0xfd020860)
+#define P_DMC_STICKY_25 ((volatile uint32_t *)0xfd020864)
+#define P_DMC_STICKY_26 ((volatile uint32_t *)0xfd020868)
+#define P_DMC_STICKY_27 ((volatile uint32_t *)0xfd02086c)
+#define P_DMC_STICKY_28 ((volatile uint32_t *)0xfd020870)
+#define P_DMC_STICKY_29 ((volatile uint32_t *)0xfd020874)
+#define P_DMC_STICKY_30 ((volatile uint32_t *)0xfd020878)
+#define P_DMC_STICKY_31 ((volatile uint32_t *)0xfd02087c)
+#define P_DMC_STICKY_32 ((volatile uint32_t *)0xfd020880)
+#define P_DMC_STICKY_33 ((volatile uint32_t *)0xfd020884)
+#define P_DMC_STICKY_34 ((volatile uint32_t *)0xfd020888)
+#define P_DMC_STICKY_35 ((volatile uint32_t *)0xfd02088c)
+#define P_DMC_STICKY_36 ((volatile uint32_t *)0xfd020890)
+#define P_DMC_STICKY_37 ((volatile uint32_t *)0xfd020894)
+#define P_DMC_STICKY_38 ((volatile uint32_t *)0xfd020898)
+#define P_DMC_STICKY_39 ((volatile uint32_t *)0xfd02089c)
+#define P_DMC_STICKY_40 ((volatile uint32_t *)0xfd0208a0)
+#define P_DMC_STICKY_41 ((volatile uint32_t *)0xfd0208a4)
+#define P_DMC_STICKY_42 ((volatile uint32_t *)0xfd0208a8)
+#define P_DMC_STICKY_43 ((volatile uint32_t *)0xfd0208ac)
+#define P_DMC_STICKY_44 ((volatile uint32_t *)0xfd0208b0)
+#define P_DMC_STICKY_45 ((volatile uint32_t *)0xfd0208b4)
+#define P_DMC_STICKY_46 ((volatile uint32_t *)0xfd0208b8)
+#define P_DMC_STICKY_47 ((volatile uint32_t *)0xfd0208bc)
+#define P_DMC_STICKY_48 ((volatile uint32_t *)0xfd0208c0)
+#define P_DMC_STICKY_49 ((volatile uint32_t *)0xfd0208c4)
+#define P_DMC_STICKY_50 ((volatile uint32_t *)0xfd0208c8)
+#define P_DMC_STICKY_51 ((volatile uint32_t *)0xfd0208cc)
+#define P_DMC_STICKY_52 ((volatile uint32_t *)0xfd0208d0)
+#define P_DMC_STICKY_53 ((volatile uint32_t *)0xfd0208d4)
+#define P_DMC_STICKY_54 ((volatile uint32_t *)0xfd0208d8)
+#define P_DMC_STICKY_55 ((volatile uint32_t *)0xfd0208dc)
+#define P_DMC_STICKY_56 ((volatile uint32_t *)0xfd0208e0)
+#define P_DMC_STICKY_57 ((volatile uint32_t *)0xfd0208e4)
+#define P_DMC_STICKY_58 ((volatile uint32_t *)0xfd0208e8)
+#define P_DMC_STICKY_59 ((volatile uint32_t *)0xfd0208ec)
+#define P_DMC_STICKY_60 ((volatile uint32_t *)0xfd0208f0)
+#define P_DMC_STICKY_61 ((volatile uint32_t *)0xfd0208f4)
+#define P_DMC_STICKY_62 ((volatile uint32_t *)0xfd0208f8)
+#define P_DMC_STICKY_63 ((volatile uint32_t *)0xfd0208fc)
+//`endif
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh
+//
+//========================================================================
+// APB0_RESET_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000000
+// -----------------------------------------------
+#define P_RESETCTRL_RESET0 ((volatile uint32_t *)0xfe000000)
+#define P_RESETCTRL_RESET1 ((volatile uint32_t *)0xfe000004)
+#define P_RESETCTRL_RESET2 ((volatile uint32_t *)0xfe000008)
+#define P_RESETCTRL_RESET0_LEVEL ((volatile uint32_t *)0xfe000040)
+#define P_RESETCTRL_RESET1_LEVEL ((volatile uint32_t *)0xfe000044)
+#define P_RESETCTRL_RESET2_LEVEL ((volatile uint32_t *)0xfe000048)
+#define P_RESETCTRL_RESET0_MASK ((volatile uint32_t *)0xfe000080)
+#define P_RESETCTRL_RESET1_MASK ((volatile uint32_t *)0xfe000084)
+#define P_RESETCTRL_RESET2_MASK ((volatile uint32_t *)0xfe000088)
+#define P_RESETCTRL_RESET_HOLD_CYC ((volatile uint32_t *)0xfe0000c0)
+#define P_RESETCTRL_WATCHDOG_CTRL0 ((volatile uint32_t *)0xfe000100)
+#define P_RESETCTRL_WATCHDOG_CTRL1 ((volatile uint32_t *)0xfe000104)
+#define P_RESETCTRL_WATCHDOG_CNT ((volatile uint32_t *)0xfe000108)
+#define P_RESETCTRL_WATCHDOG_CLR ((volatile uint32_t *)0xfe00010c)
+#define P_RESETCTRL_SEC_RESET0 ((volatile uint32_t *)0xfe000140)
+#define P_RESETCTRL_SEC_RESET0_LEVEL ((volatile uint32_t *)0xfe000144)
+#define P_RESETCTRL_SEC_RESET0_MASK ((volatile uint32_t *)0xfe000148)
+//========================================================================
+// APB0_PAD_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000400
+// -----------------------------------------------
+#define P_PADCTRL_PIN_MUX_REG0 ((volatile uint32_t *)0xfe000400)
+#define P_PADCTRL_PIN_MUX_REG1 ((volatile uint32_t *)0xfe000404)
+#define P_PADCTRL_PIN_MUX_REG2 ((volatile uint32_t *)0xfe000408)
+#define P_PADCTRL_PIN_MUX_REG3 ((volatile uint32_t *)0xfe00040c)
+#define P_PADCTRL_PIN_MUX_REG4 ((volatile uint32_t *)0xfe000410)
+#define P_PADCTRL_PIN_MUX_REG5 ((volatile uint32_t *)0xfe000414)
+#define P_PADCTRL_PIN_MUX_REG6 ((volatile uint32_t *)0xfe000418)
+#define P_PADCTRL_PIN_MUX_REG7 ((volatile uint32_t *)0xfe00041c)
+#define P_PADCTRL_PIN_MUX_REG8 ((volatile uint32_t *)0xfe000420)
+#define P_PADCTRL_PIN_MUX_REG9 ((volatile uint32_t *)0xfe000424)
+#define P_PADCTRL_PIN_MUX_REGA ((volatile uint32_t *)0xfe000428)
+#define P_PADCTRL_PIN_MUX_REGB ((volatile uint32_t *)0xfe00042c)
+#define P_PADCTRL_PIN_MUX_REGC ((volatile uint32_t *)0xfe000430)
+#define P_PADCTRL_PIN_MUX_REGD ((volatile uint32_t *)0xfe000434)
+#define P_PADCTRL_PIN_MUX_REGE ((volatile uint32_t *)0xfe000438)
+#define P_PADCTRL_PIN_MUX_REGF ((volatile uint32_t *)0xfe00043c)
+#define P_PADCTRL_GPIO_IRQ_CTRL0 ((volatile uint32_t *)0xfe000440)
+#define P_PADCTRL_GPIO_IRQ_CTRL1 ((volatile uint32_t *)0xfe000444)
+#define P_PADCTRL_GPIO_IRQ_CTRL2 ((volatile uint32_t *)0xfe000448)
+#define P_PADCTRL_GPIO_IRQ_CTRL3 ((volatile uint32_t *)0xfe00044c)
+#define P_PADCTRL_GPIO_IRQ_CTRL4 ((volatile uint32_t *)0xfe000450)
+#define P_PADCTRL_WORLDSYNC_CTRL0 ((volatile uint32_t *)0xfe000460)
+#define P_PADCTRL_GPIO_MSR_CTRL0 ((volatile uint32_t *)0xfe000464)
+#define P_PADCTRL_GPIOP_I ((volatile uint32_t *)0xfe000480)
+#define P_PADCTRL_GPIOP_O ((volatile uint32_t *)0xfe000484)
+#define P_PADCTRL_GPIOP_OEN ((volatile uint32_t *)0xfe000488)
+#define P_PADCTRL_GPIOP_PULL_EN ((volatile uint32_t *)0xfe00048c)
+#define P_PADCTRL_GPIOP_PULL_UP ((volatile uint32_t *)0xfe000490)
+#define P_PADCTRL_GPIOP_DS ((volatile uint32_t *)0xfe000494)
+#define P_PADCTRL_GPIOB_I ((volatile uint32_t *)0xfe0004c0)
+#define P_PADCTRL_GPIOB_O ((volatile uint32_t *)0xfe0004c4)
+#define P_PADCTRL_GPIOB_OEN ((volatile uint32_t *)0xfe0004c8)
+#define P_PADCTRL_GPIOB_PULL_EN ((volatile uint32_t *)0xfe0004cc)
+#define P_PADCTRL_GPIOB_PULL_UP ((volatile uint32_t *)0xfe0004d0)
+#define P_PADCTRL_GPIOB_DS ((volatile uint32_t *)0xfe0004d4)
+#define P_PADCTRL_GPIOX_I ((volatile uint32_t *)0xfe000500)
+#define P_PADCTRL_GPIOX_O ((volatile uint32_t *)0xfe000504)
+#define P_PADCTRL_GPIOX_OEN ((volatile uint32_t *)0xfe000508)
+#define P_PADCTRL_GPIOX_PULL_EN ((volatile uint32_t *)0xfe00050c)
+#define P_PADCTRL_GPIOX_PULL_UP ((volatile uint32_t *)0xfe000510)
+#define P_PADCTRL_GPIOX_DS ((volatile uint32_t *)0xfe000514)
+#define P_PADCTRL_GPIOX_DS_EXT ((volatile uint32_t *)0xfe000518)
+#define P_PADCTRL_GPIOF_I ((volatile uint32_t *)0xfe000540)
+#define P_PADCTRL_GPIOF_O ((volatile uint32_t *)0xfe000544)
+#define P_PADCTRL_GPIOF_OEN ((volatile uint32_t *)0xfe000548)
+#define P_PADCTRL_GPIOF_PULL_EN ((volatile uint32_t *)0xfe00054c)
+#define P_PADCTRL_GPIOF_PULL_UP ((volatile uint32_t *)0xfe000550)
+#define P_PADCTRL_GPIOF_DS ((volatile uint32_t *)0xfe000554)
+#define P_PADCTRL_GPIOA_I ((volatile uint32_t *)0xfe000580)
+#define P_PADCTRL_GPIOA_O ((volatile uint32_t *)0xfe000584)
+#define P_PADCTRL_GPIOA_OEN ((volatile uint32_t *)0xfe000588)
+#define P_PADCTRL_GPIOA_PULL_EN ((volatile uint32_t *)0xfe00058c)
+#define P_PADCTRL_GPIOA_PULL_UP ((volatile uint32_t *)0xfe000590)
+#define P_PADCTRL_GPIOA_DS ((volatile uint32_t *)0xfe000594)
+#define P_PADCTRL_TESTN_I ((volatile uint32_t *)0xfe0005c0)
+#define P_PADCTRL_TESTN_O ((volatile uint32_t *)0xfe0005c4)
+#define P_PADCTRL_TESTN_OEN ((volatile uint32_t *)0xfe0005c8)
+#define P_PADCTRL_TESTN_PULL_EN ((volatile uint32_t *)0xfe0005cc)
+#define P_PADCTRL_TESTN_PULL_UP ((volatile uint32_t *)0xfe0005d0)
+#define P_PADCTRL_TESTN_DS ((volatile uint32_t *)0xfe0005d4)
+#define P_PADCTRL_MUTE_CTRL ((volatile uint32_t *)0xfe000600)
+//========================================================================
+// APB0_CLK_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000800
+// -----------------------------------------------
+#define P_CLKTREE_SYS_OSCIN_CTRL ((volatile uint32_t *)0xfe000800)
+#define P_CLKTREE_RTC_BY_OSCIN_CTRL0 ((volatile uint32_t *)0xfe000804)
+#define P_CLKTREE_RTC_BY_OSCIN_CTRL1 ((volatile uint32_t *)0xfe000808)
+#define P_CLKTREE_RTC_CTRL ((volatile uint32_t *)0xfe00080c)
+#define P_CLKTREE_SYS_CLK_CTRL0 ((volatile uint32_t *)0xfe000810)
+#define P_CLKTREE_AXI_CLK_CTRL0 ((volatile uint32_t *)0xfe000814)
+#define P_CLKTREE_SYS_CLK_EN0 ((volatile uint32_t *)0xfe00081c)
+#define P_CLKTREE_SYS_CLK_EN1 ((volatile uint32_t *)0xfe000820)
+#define P_CLKTREE_AXI_CLK_EN ((volatile uint32_t *)0xfe000824)
+#define P_CLKTREE_DSPA_CLK_EN ((volatile uint32_t *)0xfe000828)
+#define P_CLKTREE_DSPB_CLK_EN ((volatile uint32_t *)0xfe00082c)
+#define P_CLKTREE_DSPA_CLK_CTRL0 ((volatile uint32_t *)0xfe000830)
+#define P_CLKTREE_DSPB_CLK_CTRL0 ((volatile uint32_t *)0xfe000834)
+#define P_CLKTREE_CLK12_24_CTRL ((volatile uint32_t *)0xfe000838)
+#define P_CLKTREE_GEN_CLK_CTRL ((volatile uint32_t *)0xfe00083c)
+#define P_CLKTREE_TIMESTAMP_CTRL0 ((volatile uint32_t *)0xfe000840)
+#define P_CLKTREE_TIMESTAMP_CTRL1 ((volatile uint32_t *)0xfe000844)
+#define P_CLKTREE_TIMESTAMP_CTRL2 ((volatile uint32_t *)0xfe000848)
+#define P_CLKTREE_TIMESTAMP_VAL0 ((volatile uint32_t *)0xfe00084c)
+#define P_CLKTREE_TIMESTAMP_VAL1 ((volatile uint32_t *)0xfe000850)
+#define P_CLKTREE_TIMEBASE_CTRL0 ((volatile uint32_t *)0xfe000854)
+#define P_CLKTREE_TIMEBASE_CTRL1 ((volatile uint32_t *)0xfe000858)
+#define P_CLKTREE_SAR_ADC_CLK_CTRL ((volatile uint32_t *)0xfe0008c0)
+#define P_CLKTREE_PWM_CLK_AB_CTRL ((volatile uint32_t *)0xfe0008c4)
+#define P_CLKTREE_PWM_CLK_CD_CTRL ((volatile uint32_t *)0xfe0008c8)
+#define P_CLKTREE_PWM_CLK_EF_CTRL ((volatile uint32_t *)0xfe0008cc)
+#define P_CLKTREE_SPICC_CLK_CTRL ((volatile uint32_t *)0xfe0008d0)
+#define P_CLKTREE_TS_CLK_CTRL ((volatile uint32_t *)0xfe0008d4)
+#define P_CLKTREE_SPIFC_CLK_CTRL ((volatile uint32_t *)0xfe0008d8)
+#define P_CLKTREE_USB_BUSCLK_CTRL ((volatile uint32_t *)0xfe0008dc)
+#define P_CLKTREE_SD_EMMC_CLK_CTRL ((volatile uint32_t *)0xfe0008e0)
+#define P_CLKTREE_CECA_CLK_CTRL0 ((volatile uint32_t *)0xfe0008e4)
+#define P_CLKTREE_CECA_CLK_CTRL1 ((volatile uint32_t *)0xfe0008e8)
+#define P_CLKTREE_CECB_CLK_CTRL0 ((volatile uint32_t *)0xfe0008ec)
+#define P_CLKTREE_CECB_CLK_CTRL1 ((volatile uint32_t *)0xfe0008f0)
+#define P_CLKTREE_PSRAM_CLK_CTRL ((volatile uint32_t *)0xfe0008f4)
+#define P_CLKTREE_DMC_CLK_CTRL ((volatile uint32_t *)0xfe0008f8)
+#define P_CLKTREE_FCLK_DIV1_SEL ((volatile uint32_t *)0xfe0008fc)
+#define P_CLKTREE_TST_CTRL0 ((volatile uint32_t *)0xfe000900)
+//========================================================================
+// APB0_CEC - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000c00
+// -----------------------------------------------
+#define P_CECA_GEN_CNTL ((volatile uint32_t *)0xfe000c00)
+#define P_CECA_RW_REG ((volatile uint32_t *)0xfe000c04)
+#define P_CECA_INTR_MASKN ((volatile uint32_t *)0xfe000c08)
+#define P_CECA_INTR_CLR ((volatile uint32_t *)0xfe000c0c)
+#define P_CECA_INTR_STAT ((volatile uint32_t *)0xfe000c10)
+#define P_CECB_GEN_CNTL ((volatile uint32_t *)0xfe000c40)
+#define P_CECB_RW_REG ((volatile uint32_t *)0xfe000c44)
+#define P_CECB_INTR_MASKN ((volatile uint32_t *)0xfe000c48)
+#define P_CECB_INTR_CLR ((volatile uint32_t *)0xfe000c4c)
+#define P_CECB_INTR_STAT ((volatile uint32_t *)0xfe000c50)
+//========================================================================
+// APB0_IR_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001000
+// -----------------------------------------------
+#define P_IRCTRL_IR_DEC_LDR_ACTIVE ((volatile uint32_t *)0xfe001000)
+#define P_IRCTRL_IR_DEC_LDR_IDLE ((volatile uint32_t *)0xfe001004)
+#define P_IRCTRL_IR_DEC_LDR_REPEAT ((volatile uint32_t *)0xfe001008)
+#define P_IRCTRL_IR_DEC_BIT_0 ((volatile uint32_t *)0xfe00100c)
+#define P_IRCTRL_IR_DEC_REG0 ((volatile uint32_t *)0xfe001010)
+#define P_IRCTRL_IR_DEC_FRAME ((volatile uint32_t *)0xfe001014)
+#define P_IRCTRL_IR_DEC_STATUS ((volatile uint32_t *)0xfe001018)
+#define P_IRCTRL_IR_DEC_REG1 ((volatile uint32_t *)0xfe00101c)
+#define P_IRCTRL_MF_IR_DEC_LDR_ACTIVE ((volatile uint32_t *)0xfe001040)
+#define P_IRCTRL_MF_IR_DEC_LDR_IDLE ((volatile uint32_t *)0xfe001044)
+#define P_IRCTRL_MF_IR_DEC_LDR_REPEAT ((volatile uint32_t *)0xfe001048)
+#define P_IRCTRL_MF_IR_DEC_BIT_0 ((volatile uint32_t *)0xfe00104c)
+#define P_IRCTRL_MF_IR_DEC_REG0 ((volatile uint32_t *)0xfe001050)
+#define P_IRCTRL_MF_IR_DEC_FRAME ((volatile uint32_t *)0xfe001054)
+#define P_IRCTRL_MF_IR_DEC_STATUS ((volatile uint32_t *)0xfe001058)
+#define P_IRCTRL_MF_IR_DEC_REG1 ((volatile uint32_t *)0xfe00105c)
+#define P_IRCTRL_MF_IR_DEC_REG2 ((volatile uint32_t *)0xfe001060)
+#define P_IRCTRL_MF_IR_DEC_DURATN2 ((volatile uint32_t *)0xfe001064)
+#define P_IRCTRL_MF_IR_DEC_DURATN3 ((volatile uint32_t *)0xfe001068)
+#define P_IRCTRL_MF_IR_DEC_FRAME1 ((volatile uint32_t *)0xfe00106c)
+#define P_IRCTRL_MF_IR_DEC_STATUS1 ((volatile uint32_t *)0xfe001070)
+#define P_IRCTRL_MF_IR_DEC_STATUS2 ((volatile uint32_t *)0xfe001074)
+#define P_IRCTRL_MF_IR_DEC_REG3 ((volatile uint32_t *)0xfe001078)
+#define P_IRCTRL_MF_IR_DEC_FRAME_RSV0 ((volatile uint32_t *)0xfe00107c)
+#define P_IRCTRL_MF_IR_DEC_FRAME_RSV1 ((volatile uint32_t *)0xfe001080)
+#define P_IRCTRL_MF_IR_DEC_FILTE ((volatile uint32_t *)0xfe001084)
+#define P_IRCTRL_MF_IR_DEC_IRQ_CTL ((volatile uint32_t *)0xfe001088)
+#define P_IRCTRL_MF_IR_DEC_FIFO_CTL ((volatile uint32_t *)0xfe00108c)
+#define P_IRCTRL_MF_IR_DEC_WIDTH_NEW ((volatile uint32_t *)0xfe001090)
+#define P_IRCTRL_MF_IR_DEC_REPEAT_DET ((volatile uint32_t *)0xfe001094)
+#define P_IRCTRL_IR_DEC_DEMOD_CNTL0 ((volatile uint32_t *)0xfe0010c0)
+#define P_IRCTRL_IR_DEC_DEMOD_CNTL1 ((volatile uint32_t *)0xfe0010c4)
+#define P_IRCTRL_IR_DEC_DEMOD_IIR_THD ((volatile uint32_t *)0xfe0010c8)
+#define P_IRCTRL_IR_DEC_DEMOD_THD0 ((volatile uint32_t *)0xfe0010cc)
+#define P_IRCTRL_IR_DEC_DEMOD_THD1 ((volatile uint32_t *)0xfe0010d0)
+#define P_IRCTRL_IR_DEC_DEMOD_SUM_CNT0 ((volatile uint32_t *)0xfe0010d4)
+#define P_IRCTRL_IR_DEC_DEMOD_SUM_CNT1 ((volatile uint32_t *)0xfe0010d8)
+#define P_IRCTRL_IR_DEC_DEMOD_CNT0 ((volatile uint32_t *)0xfe0010dc)
+#define P_IRCTRL_IR_DEC_DEMOD_CNT1 ((volatile uint32_t *)0xfe0010e0)
+#define P_IRCTRL_IR_BLASTER_ADDR0 ((volatile uint32_t *)0xfe00110c)
+#define P_IRCTRL_IR_BLASTER_ADDR1 ((volatile uint32_t *)0xfe001110)
+#define P_IRCTRL_IR_BLASTER_ADDR2 ((volatile uint32_t *)0xfe001114)
+#define P_IRCTRL_IR_BLASTER_ADDR3 ((volatile uint32_t *)0xfe001118)
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001400
+// -----------------------------------------------
+#define P_I2C_M_A_CONTROL_REG ((volatile uint32_t *)0xfe001400)
+#define P_I2C_M_A_SLAVE_ADDR ((volatile uint32_t *)0xfe001404)
+#define P_I2C_M_A_TOKEN_LIST0 ((volatile uint32_t *)0xfe001408)
+#define P_I2C_M_A_TOKEN_LIST1 ((volatile uint32_t *)0xfe00140c)
+#define P_I2C_M_A_WDATA_REG0 ((volatile uint32_t *)0xfe001410)
+#define P_I2C_M_A_WDATA_REG1 ((volatile uint32_t *)0xfe001414)
+#define P_I2C_M_A_RDATA_REG0 ((volatile uint32_t *)0xfe001418)
+#define P_I2C_M_A_RDATA_REG1 ((volatile uint32_t *)0xfe00141c)
+#define P_I2C_M_A_TIMEOUT_TH ((volatile uint32_t *)0xfe001420)
+//========================================================================
+// APB0_I2C_S - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001800
+// -----------------------------------------------
+#define P_I2C_S_A_CONTROL_REG ((volatile uint32_t *)0xfe001800)
+#define P_I2C_S_A_SEND_REG ((volatile uint32_t *)0xfe001804)
+#define P_I2C_S_A_RECV_REG ((volatile uint32_t *)0xfe001808)
+#define P_I2C_S_A_CNTL1_REG ((volatile uint32_t *)0xfe00180c)
+//========================================================================
+// APB0_UART_A - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001c00
+// -----------------------------------------------
+#define P_UART_A_WFIFO ((volatile uint32_t *)0xfe001c00)
+#define P_UART_A_RFIFO ((volatile uint32_t *)0xfe001c04)
+#define P_UART_A_CONTROL ((volatile uint32_t *)0xfe001c08)
+#define P_UART_A_STATUS ((volatile uint32_t *)0xfe001c0c)
+#define P_UART_A_MISC ((volatile uint32_t *)0xfe001c10)
+#define P_UART_A_REG5 ((volatile uint32_t *)0xfe001c14)
+//========================================================================
+// APB0_UART_B - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002000
+// -----------------------------------------------
+#define P_UART_B_WFIFO ((volatile uint32_t *)0xfe002000)
+#define P_UART_B_RFIFO ((volatile uint32_t *)0xfe002004)
+#define P_UART_B_CONTROL ((volatile uint32_t *)0xfe002008)
+#define P_UART_B_STATUS ((volatile uint32_t *)0xfe00200c)
+#define P_UART_B_MISC ((volatile uint32_t *)0xfe002010)
+#define P_UART_B_REG5 ((volatile uint32_t *)0xfe002014)
+//========================================================================
+// APB0_PWM_AB - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002400
+// -----------------------------------------------
+#define P_PWMAB_PWM_A ((volatile uint32_t *)0xfe002400)
+#define P_PWMAB_PWM_B ((volatile uint32_t *)0xfe002404)
+#define P_PWMAB_MISC_REG_AB ((volatile uint32_t *)0xfe002408)
+#define P_PWMAB_DELTA_SIGMA_AB ((volatile uint32_t *)0xfe00240c)
+#define P_PWMAB_TIME_AB ((volatile uint32_t *)0xfe002410)
+#define P_PWMAB_A2 ((volatile uint32_t *)0xfe002414)
+#define P_PWMAB_B2 ((volatile uint32_t *)0xfe002418)
+#define P_PWMAB_BLINK_AB ((volatile uint32_t *)0xfe00241c)
+#define P_PWMAB_LOCK_AB ((volatile uint32_t *)0xfe002420)
+//========================================================================
+// APB0_PWM_CD - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002800
+// -----------------------------------------------
+#define P_PWMCD_PWM_C ((volatile uint32_t *)0xfe002800)
+#define P_PWMCD_PWM_D ((volatile uint32_t *)0xfe002804)
+#define P_PWMCD_MISC_REG_CD ((volatile uint32_t *)0xfe002808)
+#define P_PWMCD_DELTA_SIGMA_CD ((volatile uint32_t *)0xfe00280c)
+#define P_PWMCD_TIME_CD ((volatile uint32_t *)0xfe002810)
+#define P_PWMCD_C2 ((volatile uint32_t *)0xfe002814)
+#define P_PWMCD_D2 ((volatile uint32_t *)0xfe002818)
+#define P_PWMCD_BLINK_CD ((volatile uint32_t *)0xfe00281c)
+#define P_PWMCD_LOCK_CD ((volatile uint32_t *)0xfe002820)
+//========================================================================
+// APB0_SARADC - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002c00
+// -----------------------------------------------
+#define P_SAR_ADC_REG0 ((volatile uint32_t *)0xfe002c00)
+#define P_SAR_ADC_CHAN_LIST ((volatile uint32_t *)0xfe002c04)
+#define P_SAR_ADC_AVG_CNTL ((volatile uint32_t *)0xfe002c08)
+#define P_SAR_ADC_REG3 ((volatile uint32_t *)0xfe002c0c)
+#define P_SAR_ADC_DELAY ((volatile uint32_t *)0xfe002c10)
+#define P_SAR_ADC_LAST_RD ((volatile uint32_t *)0xfe002c14)
+#define P_SAR_ADC_FIFO_RD ((volatile uint32_t *)0xfe002c18)
+#define P_SAR_ADC_AUX_SW ((volatile uint32_t *)0xfe002c1c)
+#define P_SAR_ADC_CHAN_10_SW ((volatile uint32_t *)0xfe002c20)
+#define P_SAR_ADC_DETECT_IDLE_SW ((volatile uint32_t *)0xfe002c24)
+#define P_SAR_ADC_DELTA_10 ((volatile uint32_t *)0xfe002c28)
+#define P_SAR_ADC_REG11 ((volatile uint32_t *)0xfe002c2c)
+#define P_SAR_ADC_REG12 ((volatile uint32_t *)0xfe002c30)
+#define P_SAR_ADC_REG13 ((volatile uint32_t *)0xfe002c34)
+#define P_SAR_ADC_CHNL01 ((volatile uint32_t *)0xfe002c38)
+#define P_SAR_ADC_CHNL23 ((volatile uint32_t *)0xfe002c3c)
+#define P_SAR_ADC_CHNL45 ((volatile uint32_t *)0xfe002c40)
+#define P_SAR_ADC_CHNL67 ((volatile uint32_t *)0xfe002c44)
+//========================================================================
+// JTAGCTRL_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003000
+// -----------------------------------------------
+#define P_JTAGCTRL_CTRL0 ((volatile uint32_t *)0xfe003000)
+#define P_JTAGCTRL_PWD_CTRL0 ((volatile uint32_t *)0xfe003004)
+#define P_JTAGCTRL_PWD_ADDR0 ((volatile uint32_t *)0xfe003008)
+#define P_JTAGCTRL_PWD_ADDR1 ((volatile uint32_t *)0xfe00300c)
+#define P_JTAGCTRL_PWD_ADDR2 ((volatile uint32_t *)0xfe003010)
+#define P_JTAGCTRL_PWD_ADDR3 ((volatile uint32_t *)0xfe003014)
+#define P_JTAGCTRL_PWD_VALUE0 ((volatile uint32_t *)0xfe003018)
+#define P_JTAGCTRL_PWD_VALUE1 ((volatile uint32_t *)0xfe00301c)
+#define P_JTAGCTRL_PWD_VALUE2 ((volatile uint32_t *)0xfe003020)
+#define P_JTAGCTRL_PWD_VALUE3 ((volatile uint32_t *)0xfe003024)
+#define P_JTAGCTRL_PWD_STS ((volatile uint32_t *)0xfe003028)
+//========================================================================
+// APB0_MSR_CLK - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003400
+// -----------------------------------------------
+#define P_MSR_CLK_REG0 ((volatile uint32_t *)0xfe003400)
+#define P_MSR_CLK_REG1 ((volatile uint32_t *)0xfe003404)
+#define P_MSR_CLK_REG2 ((volatile uint32_t *)0xfe003408)
+#define P_MSR_CLK_REG3 ((volatile uint32_t *)0xfe00340c)
+#define P_MSR_CLK_REG4 ((volatile uint32_t *)0xfe003410)
+#define P_MSR_CLK_REG5 ((volatile uint32_t *)0xfe003414)
+#define P_MSR_CLK_DUTY ((volatile uint32_t *)0xfe003418)
+//========================================================================
+// APB0_SPICCA_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003800
+// -----------------------------------------------
+#define P_SPICC_A_RXDATA ((volatile uint32_t *)0xfe003800)
+#define P_SPICC_A_TXDATA ((volatile uint32_t *)0xfe003804)
+#define P_SPICC_A_CONREG ((volatile uint32_t *)0xfe003808)
+#define P_SPICC_A_INTREG ((volatile uint32_t *)0xfe00380c)
+#define P_SPICC_A_DMAREG ((volatile uint32_t *)0xfe003810)
+#define P_SPICC_A_STATREG ((volatile uint32_t *)0xfe003814)
+#define P_SPICC_A_PERIODREG ((volatile uint32_t *)0xfe003818)
+#define P_SPICC_A_TESTREG ((volatile uint32_t *)0xfe00381c)
+#define P_SPICC_A_DRADDR ((volatile uint32_t *)0xfe003820)
+#define P_SPICC_A_DWADDR ((volatile uint32_t *)0xfe003824)
+#define P_SPICC_A_LD_CNTL0 ((volatile uint32_t *)0xfe003828)
+#define P_SPICC_A_LD_CNTL1 ((volatile uint32_t *)0xfe00382c)
+#define P_SPICC_A_LD_RADDR ((volatile uint32_t *)0xfe003830)
+#define P_SPICC_A_LD_WADDR ((volatile uint32_t *)0xfe003834)
+#define P_SPICC_A_ENHANCE_CNTL ((volatile uint32_t *)0xfe003838)
+#define P_SPICC_A_ENHANCE_CNTL1 ((volatile uint32_t *)0xfe00383c)
+#define P_SPICC_A_ENHANCE_CNTL2 ((volatile uint32_t *)0xfe003840)
+//========================================================================
+// APB0_SPICCB_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003c00
+// -----------------------------------------------
+#define P_SPICC_B_RXDATA ((volatile uint32_t *)0xfe003c00)
+#define P_SPICC_B_TXDATA ((volatile uint32_t *)0xfe003c04)
+#define P_SPICC_B_CONREG ((volatile uint32_t *)0xfe003c08)
+#define P_SPICC_B_INTREG ((volatile uint32_t *)0xfe003c0c)
+#define P_SPICC_B_DMAREG ((volatile uint32_t *)0xfe003c10)
+#define P_SPICC_B_STATREG ((volatile uint32_t *)0xfe003c14)
+#define P_SPICC_B_PERIODREG ((volatile uint32_t *)0xfe003c18)
+#define P_SPICC_B_TESTREG ((volatile uint32_t *)0xfe003c1c)
+#define P_SPICC_B_DRADDR ((volatile uint32_t *)0xfe003c20)
+#define P_SPICC_B_DWADDR ((volatile uint32_t *)0xfe003c24)
+#define P_SPICC_B_LD_CNTL0 ((volatile uint32_t *)0xfe003c28)
+#define P_SPICC_B_LD_CNTL1 ((volatile uint32_t *)0xfe003c2c)
+#define P_SPICC_B_LD_RADDR ((volatile uint32_t *)0xfe003c30)
+#define P_SPICC_B_LD_WADDR ((volatile uint32_t *)0xfe003c34)
+#define P_SPICC_B_ENHANCE_CNTL ((volatile uint32_t *)0xfe003c38)
+#define P_SPICC_B_ENHANCE_CNTL1 ((volatile uint32_t *)0xfe003c3c)
+#define P_SPICC_B_ENHANCE_CNTL2 ((volatile uint32_t *)0xfe003c40)
+//========================================================================
+// USBCTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe004000
+// -----------------------------------------------
+#define P_USB_CTRL0 ((volatile uint32_t *)0xfe004000)
+#define P_USB_CTRL1 ((volatile uint32_t *)0xfe004004)
+#define P_USB_CTRL2 ((volatile uint32_t *)0xfe004008)
+#define P_USB_CTRL3 ((volatile uint32_t *)0xfe00400c)
+#define P_USB_CTRL4 ((volatile uint32_t *)0xfe004010)
+#define P_USB_CTRL5 ((volatile uint32_t *)0xfe004014)
+#define P_USB_CTRL6 ((volatile uint32_t *)0xfe004018)
+#define P_USB_CTRL7 ((volatile uint32_t *)0xfe00401c)
+#define P_USB_CTRL8 ((volatile uint32_t *)0xfe004020)
+#define P_USB_CTRL9 ((volatile uint32_t *)0xfe004024)
+#define P_USB_CTRL10 ((volatile uint32_t *)0xfe004028)
+#define P_USB_CTRL11 ((volatile uint32_t *)0xfe00402c)
+#define P_USB_CTRL12 ((volatile uint32_t *)0xfe004030)
+#define P_USB_CTRL13 ((volatile uint32_t *)0xfe004034)
+#define P_USB_CTRL14 ((volatile uint32_t *)0xfe004038)
+#define P_USB_CTRL15 ((volatile uint32_t *)0xfe00403c)
+#define P_USB_CTRL16 ((volatile uint32_t *)0xfe004040)
+#define P_USB_CTRL17 ((volatile uint32_t *)0xfe004044)
+#define P_USB_CTRL18 ((volatile uint32_t *)0xfe004048)
+#define P_USB_CTRL19 ((volatile uint32_t *)0xfe00404c)
+#define P_USB_CTRL20 ((volatile uint32_t *)0xfe004050)
+#define P_USB_CTRL21 ((volatile uint32_t *)0xfe004054)
+#define P_USB_CTRL22 ((volatile uint32_t *)0xfe004058)
+#define P_USB_CTRL23 ((volatile uint32_t *)0xfe00405c)
+#define P_USB_CTRL24 ((volatile uint32_t *)0xfe004060)
+#define P_USB_CTRL25 ((volatile uint32_t *)0xfe004064)
+#define P_USB_CTRL26 ((volatile uint32_t *)0xfe004068)
+#define P_USB_CTRL27 ((volatile uint32_t *)0xfe00406c)
+#define P_USB_CTRL28 ((volatile uint32_t *)0xfe004070)
+#define P_USB_CTRL29 ((volatile uint32_t *)0xfe004074)
+#define P_USB_CTRL30 ((volatile uint32_t *)0xfe004078)
+#define P_USB_CTRL31 ((volatile uint32_t *)0xfe00407c)
+//========================================================================
+// APB0_ACODEC_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe004800
+// -----------------------------------------------
+#define P_ACODEC_0 ((volatile uint32_t *)0xfe004800)
+#define P_ACODEC_1 ((volatile uint32_t *)0xfe004804)
+#define P_ACODEC_2 ((volatile uint32_t *)0xfe004808)
+#define P_ACODEC_3 ((volatile uint32_t *)0xfe00480c)
+#define P_ACODEC_4 ((volatile uint32_t *)0xfe004810)
+#define P_ACODEC_5 ((volatile uint32_t *)0xfe004814)
+#define P_ACODEC_6 ((volatile uint32_t *)0xfe004818)
+#define P_ACODEC_7 ((volatile uint32_t *)0xfe00481c)
+#define P_ACODEC_8 ((volatile uint32_t *)0xfe004820)
+#define P_ACODEC_9 ((volatile uint32_t *)0xfe004824)
+#define P_ACODEC_STS0 ((volatile uint32_t *)0xfe004840)
+//========================================================================
+// APB0_TEMP_SENSOR - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe004c00
+// -----------------------------------------------
+#define P_TS_CFG_REG1 ((volatile uint32_t *)0xfe004c04)
+#define P_TS_CFG_REG2 ((volatile uint32_t *)0xfe004c08)
+#define P_TS_CFG_REG3 ((volatile uint32_t *)0xfe004c0c)
+#define P_TS_CFG_REG4 ((volatile uint32_t *)0xfe004c10)
+#define P_TS_CFG_REG5 ((volatile uint32_t *)0xfe004c14)
+#define P_TS_CFG_REG6 ((volatile uint32_t *)0xfe004c18)
+#define P_TS_CFG_REG7 ((volatile uint32_t *)0xfe004c1c)
+#define P_TS_STAT0 ((volatile uint32_t *)0xfe004c40)
+#define P_TS_STAT1 ((volatile uint32_t *)0xfe004c44)
+#define P_TS_STAT2 ((volatile uint32_t *)0xfe004c48)
+#define P_TS_STAT3 ((volatile uint32_t *)0xfe004c4c)
+#define P_TS_STAT4 ((volatile uint32_t *)0xfe004c50)
+#define P_TS_STAT5 ((volatile uint32_t *)0xfe004c54)
+#define P_TS_STAT6 ((volatile uint32_t *)0xfe004c58)
+#define P_TS_STAT7 ((volatile uint32_t *)0xfe004c5c)
+#define P_TS_STAT8 ((volatile uint32_t *)0xfe004c60)
+#define P_TS_STAT9 ((volatile uint32_t *)0xfe004c64)
+//========================================================================
+// APB0_KL_EFUSE_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005000
+// -----------------------------------------------
+//
+// Reading file: ../crypto/crypto_reg.h
+//
+#define P_OTP_TEE_RDY ((volatile uint32_t *)0xfe005000)
+#define P_OTP_TEE_CHK ((volatile uint32_t *)0xfe005004)
+#define P_OTP_TEE_CFG ((volatile uint32_t *)0xfe005008)
+#define P_OTP_TEE_WR_DAT0 ((volatile uint32_t *)0xfe005010)
+#define P_OTP_TEE_WR_DAT1 ((volatile uint32_t *)0xfe005014)
+#define P_OTP_TEE_WR_DAT2 ((volatile uint32_t *)0xfe005018)
+#define P_OTP_TEE_WR_DAT3 ((volatile uint32_t *)0xfe00501c)
+#define P_OTP_TEE_RD_DAT0 ((volatile uint32_t *)0xfe005020)
+#define P_OTP_TEE_RD_DAT1 ((volatile uint32_t *)0xfe005024)
+#define P_OTP_TEE_RD_DAT2 ((volatile uint32_t *)0xfe005028)
+#define P_OTP_TEE_RD_DAT3 ((volatile uint32_t *)0xfe00502c)
+#define P_OTP_RMA_PW0 ((volatile uint32_t *)0xfe005030)
+#define P_OTP_RMA_PW1 ((volatile uint32_t *)0xfe005034)
+#define P_OTP_RMA_PW2 ((volatile uint32_t *)0xfe005038)
+#define P_OTP_RMA_PW3 ((volatile uint32_t *)0xfe00503c)
+#define P_OTP_REE_RDY ((volatile uint32_t *)0xfe005040)
+#define P_OTP_REE_CHK ((volatile uint32_t *)0xfe005044)
+#define P_OTP_REE_CFG ((volatile uint32_t *)0xfe005048)
+#define P_OTP_REE_RD_DAT0 ((volatile uint32_t *)0xfe005050)
+#define P_OTP_REE_RD_DAT1 ((volatile uint32_t *)0xfe005054)
+#define P_OTP_REE_RD_DAT2 ((volatile uint32_t *)0xfe005058)
+#define P_OTP_REE_RD_DAT3 ((volatile uint32_t *)0xfe00505c)
+#define P_OTP_LIC0 ((volatile uint32_t *)0xfe005060)
+#define P_OTP_LIC1 ((volatile uint32_t *)0xfe005064)
+#define P_OTP_LIC2 ((volatile uint32_t *)0xfe005068)
+#define P_OTP_LIC3 ((volatile uint32_t *)0xfe00506c)
+#define P_RNG_SEC_CONFIG_REG1 ((volatile uint32_t *)0xfe005104)
+#define P_RNG_SEC_CONFIG_REG2 ((volatile uint32_t *)0xfe005108)
+#define P_RNG_SEC_DATA ((volatile uint32_t *)0xfe005110)
+#define P_RNG_SEC_STS ((volatile uint32_t *)0xfe005114)
+#define P_RNG_USR_DATA ((volatile uint32_t *)0xfe005118)
+#define P_RNG_USR_STS ((volatile uint32_t *)0xfe00511c)
+#define P_KTE_SLOT0 ((volatile uint32_t *)0xfe005180)
+#define P_KTE_SLOT1 ((volatile uint32_t *)0xfe005184)
+#define P_KTE_SLOT2 ((volatile uint32_t *)0xfe005188)
+#define P_KTE_SLOT3 ((volatile uint32_t *)0xfe00518c)
+#define P_KTE_SLOT4 ((volatile uint32_t *)0xfe005190)
+#define P_KTE_SLOT5 ((volatile uint32_t *)0xfe005194)
+#define P_KTE_SLOT6 ((volatile uint32_t *)0xfe005198)
+#define P_KTE_SLOT7 ((volatile uint32_t *)0xfe00519c)
+#define P_MKL_TEE_RDY ((volatile uint32_t *)0xfe005200)
+#define P_MKL_TEE_CHK ((volatile uint32_t *)0xfe005204)
+#define P_MKL_TEE_CFG ((volatile uint32_t *)0xfe005208)
+#define P_MKL_TEE_EK ((volatile uint32_t *)0xfe005210)
+#define P_MKL_REE_RDY ((volatile uint32_t *)0xfe005280)
+#define P_MKL_REE_CHK ((volatile uint32_t *)0xfe005284)
+#define P_MKL_REE_CFG ((volatile uint32_t *)0xfe005288)
+#define P_MKL_REE_EK ((volatile uint32_t *)0xfe005290)
+//
+// Closing file: ../crypto/crypto_reg.h
+//
+//========================================================================
+// APB0_PWM_EF - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005400
+// -----------------------------------------------
+#define P_PWMEF_PWM_E ((volatile uint32_t *)0xfe005400)
+#define P_PWMEF_PWM_F ((volatile uint32_t *)0xfe005404)
+#define P_PWMEF_MISC_REG_EF ((volatile uint32_t *)0xfe005408)
+#define P_PWMEF_DELTA_SIGMA_EF ((volatile uint32_t *)0xfe00540c)
+#define P_PWMEF_TIME_EF ((volatile uint32_t *)0xfe005410)
+#define P_PWMEF_E2 ((volatile uint32_t *)0xfe005414)
+#define P_PWMEF_F2 ((volatile uint32_t *)0xfe005418)
+#define P_PWMEF_BLINK_EF ((volatile uint32_t *)0xfe00541c)
+#define P_PWMEF_LOCK_EF ((volatile uint32_t *)0xfe005420)
+//========================================================================
+// APB0_SYS_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005800
+// -----------------------------------------------
+#define P_SYSCTRL_METAL_REV0 ((volatile uint32_t *)0xfe005800)
+#define P_SYSCTRL_METAL_REV1 ((volatile uint32_t *)0xfe005804)
+//`define SYSCTRL_PROD_ENABLE 8'h0a
+#define P_SYSCTRL_CHIP_ID ((volatile uint32_t *)0xfe00582c)
+#define P_SYSCTRL_WRITEONCE1_REG0 ((volatile uint32_t *)0xfe005840)
+#define P_SYSCTRL_WRITEONCE1_STICKY_REG0 ((volatile uint32_t *)0xfe005844)
+#define P_SYSCTRL_WRITEONCE1_SEC_REG0 ((volatile uint32_t *)0xfe005848)
+#define P_SYSCTRL_WRITEONCE1_STICKY_SEC_REG0 ((volatile uint32_t *)0xfe00584c)
+#define P_SYSCTRL_WRITEONCE_REG0 ((volatile uint32_t *)0xfe005850)
+#define P_SYSCTRL_WRITEONCE_REG1 ((volatile uint32_t *)0xfe005854)
+#define P_SYSCTRL_WRITEONCE_SEC_REG0 ((volatile uint32_t *)0xfe005858)
+#define P_SYSCTRL_WRITEONCE_STICKY_REG0 ((volatile uint32_t *)0xfe00585c)
+#define P_SYSCTRL_WRITEONCE_STICKY_REG1 ((volatile uint32_t *)0xfe005860)
+#define P_SYSCTRL_WRITEONCE_STICKY_SEC_REG0 ((volatile uint32_t *)0xfe005864)
+#define P_SYSCTRL_TIMERA_CTRL ((volatile uint32_t *)0xfe0058c0)
+#define P_SYSCTRL_TIMERA ((volatile uint32_t *)0xfe0058c4)
+#define P_SYSCTRL_TIMERB_CTRL ((volatile uint32_t *)0xfe0058c8)
+#define P_SYSCTRL_TIMERB ((volatile uint32_t *)0xfe0058cc)
+#define P_SYSCTRL_TIMERC_CTRL ((volatile uint32_t *)0xfe0058d0)
+#define P_SYSCTRL_TIMERC ((volatile uint32_t *)0xfe0058d4)
+#define P_SYSCTRL_TIMERD_CTRL ((volatile uint32_t *)0xfe0058d8)
+#define P_SYSCTRL_TIMERD ((volatile uint32_t *)0xfe0058dc)
+#define P_SYSCTRL_SEC_TIMERA_CTRL ((volatile uint32_t *)0xfe0058e0)
+#define P_SYSCTRL_SEC_TIMERA ((volatile uint32_t *)0xfe0058e4)
+#define P_SYSCTRL_TIMERE_CTRL ((volatile uint32_t *)0xfe005900)
+#define P_SYSCTRL_TIMERE ((volatile uint32_t *)0xfe005904)
+#define P_SYSCTRL_TIMERE_HI ((volatile uint32_t *)0xfe005908)
+#define P_SYSCTRL_TIMERF_CTRL ((volatile uint32_t *)0xfe00590c)
+#define P_SYSCTRL_TIMERF ((volatile uint32_t *)0xfe005910)
+#define P_SYSCTRL_TIMERF_HI ((volatile uint32_t *)0xfe005914)
+#define P_SYSCTRL_SEC_TIMERE_CTRL ((volatile uint32_t *)0xfe005918)
+#define P_SYSCTRL_SEC_TIMERE ((volatile uint32_t *)0xfe00591c)
+#define P_SYSCTRL_SEC_TIMERE_HI ((volatile uint32_t *)0xfe005920)
+#define P_SYSCTRL_OSC_RING_CTRL0 ((volatile uint32_t *)0xfe005940)
+#define P_SYSCTRL_SEC_DDR_AXI_SEL ((volatile uint32_t *)0xfe005944)
+#define P_SYSCTRL_AM2AXI_CTRL0 ((volatile uint32_t *)0xfe005948)
+#define P_SYSCTRL_AM2AXI_STS ((volatile uint32_t *)0xfe00594c)
+#define P_SYSCTRL_POC ((volatile uint32_t *)0xfe005980)
+//`define SYSCTRL_PROD_PWD_VALUE0 8'h80
+//`define SYSCTRL_PROD_PWD_VALUE1 8'h81
+//`define SYSCTRL_PROD_PWD_VALUE2 8'h82
+//`define SYSCTRL_PROD_PWD_VALUE3 8'h83
+//`define SYSCTRL_PROD_STATUS 8'h84
+#define P_SYSCTRL_DEBUG_REG0 ((volatile uint32_t *)0xfe005a40)
+#define P_SYSCTRL_DEBUG_REG1 ((volatile uint32_t *)0xfe005a44)
+#define P_SYSCTRL_DEBUG_REG2 ((volatile uint32_t *)0xfe005a48)
+#define P_SYSCTRL_DEBUG_REG3 ((volatile uint32_t *)0xfe005a4c)
+#define P_SYSCTRL_DEBUG_REG4 ((volatile uint32_t *)0xfe005a50)
+#define P_SYSCTRL_DEBUG_REG5 ((volatile uint32_t *)0xfe005a54)
+#define P_SYSCTRL_DEBUG_REG6 ((volatile uint32_t *)0xfe005a58)
+#define P_SYSCTRL_DEBUG_REG7 ((volatile uint32_t *)0xfe005a5c)
+#define P_SYSCTRL_STATUS_REG0 ((volatile uint32_t *)0xfe005a80)
+#define P_SYSCTRL_STATUS_REG1 ((volatile uint32_t *)0xfe005a84)
+#define P_SYSCTRL_STATUS_REG2 ((volatile uint32_t *)0xfe005a88)
+#define P_SYSCTRL_STATUS_REG3 ((volatile uint32_t *)0xfe005a8c)
+#define P_SYSCTRL_STATUS_REG4 ((volatile uint32_t *)0xfe005a90)
+#define P_SYSCTRL_STATUS_REG5 ((volatile uint32_t *)0xfe005a94)
+#define P_SYSCTRL_STATUS_REG6 ((volatile uint32_t *)0xfe005a98)
+#define P_SYSCTRL_STATUS_REG7 ((volatile uint32_t *)0xfe005a9c)
+#define P_SYSCTRL_STICKY_REG0 ((volatile uint32_t *)0xfe005ac0)
+#define P_SYSCTRL_STICKY_REG1 ((volatile uint32_t *)0xfe005ac4)
+#define P_SYSCTRL_STICKY_REG2 ((volatile uint32_t *)0xfe005ac8)
+#define P_SYSCTRL_STICKY_REG3 ((volatile uint32_t *)0xfe005acc)
+#define P_SYSCTRL_STICKY_REG4 ((volatile uint32_t *)0xfe005ad0)
+#define P_SYSCTRL_STICKY_REG5 ((volatile uint32_t *)0xfe005ad4)
+#define P_SYSCTRL_STICKY_REG6 ((volatile uint32_t *)0xfe005ad8)
+#define P_SYSCTRL_STICKY_REG7 ((volatile uint32_t *)0xfe005adc)
+#define P_SYSCTRL_SEC_STATUS_REG0 ((volatile uint32_t *)0xfe005b00)
+#define P_SYSCTRL_SEC_STATUS_REG1 ((volatile uint32_t *)0xfe005b04)
+#define P_SYSCTRL_SEC_STATUS_REG2 ((volatile uint32_t *)0xfe005b08)
+#define P_SYSCTRL_SEC_STATUS_REG3 ((volatile uint32_t *)0xfe005b0c)
+#define P_SYSCTRL_SEC_STATUS_REG4 ((volatile uint32_t *)0xfe005b10)
+#define P_SYSCTRL_SEC_STATUS_REG5 ((volatile uint32_t *)0xfe005b14)
+#define P_SYSCTRL_SEC_STATUS_REG6 ((volatile uint32_t *)0xfe005b18)
+#define P_SYSCTRL_SEC_STATUS_REG7 ((volatile uint32_t *)0xfe005b1c)
+#define P_SYSCTRL_SEC_STATUS_REG8 ((volatile uint32_t *)0xfe005b20)
+#define P_SYSCTRL_SEC_STATUS_REG9 ((volatile uint32_t *)0xfe005b24)
+#define P_SYSCTRL_SEC_STATUS_REG10 ((volatile uint32_t *)0xfe005b28)
+#define P_SYSCTRL_SEC_STATUS_REG11 ((volatile uint32_t *)0xfe005b2c)
+#define P_SYSCTRL_SEC_STATUS_REG12 ((volatile uint32_t *)0xfe005b30)
+#define P_SYSCTRL_SEC_STATUS_REG13 ((volatile uint32_t *)0xfe005b34)
+#define P_SYSCTRL_SEC_STATUS_REG14 ((volatile uint32_t *)0xfe005b38)
+#define P_SYSCTRL_SEC_STATUS_REG15 ((volatile uint32_t *)0xfe005b3c)
+#define P_SYSCTRL_SEC_STATUS_REG16 ((volatile uint32_t *)0xfe005b40)
+#define P_SYSCTRL_SEC_STATUS_REG17 ((volatile uint32_t *)0xfe005b44)
+#define P_SYSCTRL_SEC_STATUS_REG18 ((volatile uint32_t *)0xfe005b48)
+#define P_SYSCTRL_SEC_STATUS_REG19 ((volatile uint32_t *)0xfe005b4c)
+#define P_SYSCTRL_SEC_STATUS_REG20 ((volatile uint32_t *)0xfe005b50)
+#define P_SYSCTRL_SEC_STATUS_REG21 ((volatile uint32_t *)0xfe005b54)
+#define P_SYSCTRL_SEC_STATUS_REG22 ((volatile uint32_t *)0xfe005b58)
+#define P_SYSCTRL_SEC_STATUS_REG23 ((volatile uint32_t *)0xfe005b5c)
+#define P_SYSCTRL_SEC_STICKY_REG0 ((volatile uint32_t *)0xfe005b80)
+#define P_SYSCTRL_SEC_STICKY_REG1 ((volatile uint32_t *)0xfe005b84)
+#define P_SYSCTRL_SEC_STICKY_REG2 ((volatile uint32_t *)0xfe005b88)
+#define P_SYSCTRL_SEC_STICKY_REG3 ((volatile uint32_t *)0xfe005b8c)
+#define P_SYSCTRL_SEC_STICKY_REG4 ((volatile uint32_t *)0xfe005b90)
+#define P_SYSCTRL_SEC_STICKY_REG5 ((volatile uint32_t *)0xfe005b94)
+#define P_SYSCTRL_SEC_STICKY_REG6 ((volatile uint32_t *)0xfe005b98)
+#define P_SYSCTRL_SEC_STICKY_REG7 ((volatile uint32_t *)0xfe005b9c)
+#define P_SYSCTRL_MSG_INDEX0_STICKY ((volatile uint32_t *)0xfe005bc0)
+#define P_SYSCTRL_MSG_INDEX1_STICKY ((volatile uint32_t *)0xfe005bc4)
+#define P_SYSCTRL_MSG_INDEX2_STICKY ((volatile uint32_t *)0xfe005bc8)
+#define P_SYSCTRL_MSG_INDEX3_STICKY ((volatile uint32_t *)0xfe005bcc)
+//========================================================================
+// APB0_I2C_M_B - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005c00
+// -----------------------------------------------
+#define P_I2C_M_B_CONTROL_REG ((volatile uint32_t *)0xfe005c00)
+#define P_I2C_M_B_SLAVE_ADDR ((volatile uint32_t *)0xfe005c04)
+#define P_I2C_M_B_TOKEN_LIST0 ((volatile uint32_t *)0xfe005c08)
+#define P_I2C_M_B_TOKEN_LIST1 ((volatile uint32_t *)0xfe005c0c)
+#define P_I2C_M_B_WDATA_REG0 ((volatile uint32_t *)0xfe005c10)
+#define P_I2C_M_B_WDATA_REG1 ((volatile uint32_t *)0xfe005c14)
+#define P_I2C_M_B_RDATA_REG0 ((volatile uint32_t *)0xfe005c18)
+#define P_I2C_M_B_RDATA_REG1 ((volatile uint32_t *)0xfe005c1c)
+#define P_I2C_M_B_TIMEOUT_TH ((volatile uint32_t *)0xfe005c20)
+//========================================================================
+// APB0_DMA - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006000
+// -----------------------------------------------
+//TODO
+//========================================================================
+// APB0_IRQ_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006400
+// -----------------------------------------------
+#define P_IRQCTRL_IRQOUT_MASK0 ((volatile uint32_t *)0xfe006400)
+#define P_IRQCTRL_IRQOUT_MASK1 ((volatile uint32_t *)0xfe006404)
+#define P_IRQCTRL_IRQOUT_MASK2 ((volatile uint32_t *)0xfe006408)
+#define P_IRQCTRL_IRQOUT_MASK3 ((volatile uint32_t *)0xfe00640c)
+#define P_IRQCTRL_IRQOUT_INV0 ((volatile uint32_t *)0xfe006440)
+#define P_IRQCTRL_IRQOUT_INV1 ((volatile uint32_t *)0xfe006444)
+#define P_IRQCTRL_IRQOUT_INV2 ((volatile uint32_t *)0xfe006448)
+#define P_IRQCTRL_IRQOUT_INV3 ((volatile uint32_t *)0xfe00644c)
+//`define APB0_IRQIN_MASK0_CLK_USB 8'h00
+//`define APB0_IRQIN_MASK0_CLK_CPU 8'h01
+//`define APB0_IRQIN_MASK0_CLK_SYS 8'h02
+//`define APB0_IRQIN_MASK1_CLK_SYS 8'h03
+//`define APB0_IRQIN_MASK0_CLK_DSPA 8'h04
+//`define APB0_IRQIN_MASK0_CLK_DSPB 8'h05
+//`define APB0_IRQIN_CLRLVL_CLK_USB 8'h10
+//`define APB0_IRQIN_CLRLVL_CLK_DSPA 8'h11
+//`define APB0_IRQIN_CLRLVL_CLK_DSPB 8'h12
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006800
+// -----------------------------------------------
+#define P_I2C_M_C_CONTROL_REG ((volatile uint32_t *)0xfe006800)
+#define P_I2C_M_C_SLAVE_ADDR ((volatile uint32_t *)0xfe006804)
+#define P_I2C_M_C_TOKEN_LIST0 ((volatile uint32_t *)0xfe006808)
+#define P_I2C_M_C_TOKEN_LIST1 ((volatile uint32_t *)0xfe00680c)
+#define P_I2C_M_C_WDATA_REG0 ((volatile uint32_t *)0xfe006810)
+#define P_I2C_M_C_WDATA_REG1 ((volatile uint32_t *)0xfe006814)
+#define P_I2C_M_C_RDATA_REG0 ((volatile uint32_t *)0xfe006818)
+#define P_I2C_M_C_RDATA_REG1 ((volatile uint32_t *)0xfe00681c)
+#define P_I2C_M_C_TIMEOUT_TH ((volatile uint32_t *)0xfe006820)
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006c00
+// -----------------------------------------------
+#define P_I2C_M_D_CONTROL_REG ((volatile uint32_t *)0xfe006c00)
+#define P_I2C_M_D_SLAVE_ADDR ((volatile uint32_t *)0xfe006c04)
+#define P_I2C_M_D_TOKEN_LIST0 ((volatile uint32_t *)0xfe006c08)
+#define P_I2C_M_D_TOKEN_LIST1 ((volatile uint32_t *)0xfe006c0c)
+#define P_I2C_M_D_WDATA_REG0 ((volatile uint32_t *)0xfe006c10)
+#define P_I2C_M_D_WDATA_REG1 ((volatile uint32_t *)0xfe006c14)
+#define P_I2C_M_D_RDATA_REG0 ((volatile uint32_t *)0xfe006c18)
+#define P_I2C_M_D_RDATA_REG1 ((volatile uint32_t *)0xfe006c1c)
+#define P_I2C_M_D_TIMEOUT_TH ((volatile uint32_t *)0xfe006c20)
+//========================================================================
+// APB0_UART_C - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007000
+// -----------------------------------------------
+#define P_UART_C_WFIFO ((volatile uint32_t *)0xfe007000)
+#define P_UART_C_RFIFO ((volatile uint32_t *)0xfe007004)
+#define P_UART_C_CONTROL ((volatile uint32_t *)0xfe007008)
+#define P_UART_C_STATUS ((volatile uint32_t *)0xfe00700c)
+#define P_UART_C_MISC ((volatile uint32_t *)0xfe007010)
+#define P_UART_C_REG5 ((volatile uint32_t *)0xfe007014)
+//========================================================================
+// APB0_PWR_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007800
+// -----------------------------------------------
+#define P_PWRCTRL_PWR_ACK0 ((volatile uint32_t *)0xfe007800)
+#define P_PWRCTRL_ISO_EN0 ((volatile uint32_t *)0xfe007804)
+#define P_PWRCTRL_PWR_OFF0 ((volatile uint32_t *)0xfe007808)
+#define P_PWRCTRL_SAVE_EN0 ((volatile uint32_t *)0xfe00780c)
+#define P_PWRCTRL_RESTORE_EN0 ((volatile uint32_t *)0xfe007810)
+#define P_PWRCTRL_MEM_PD0 ((volatile uint32_t *)0xfe007840)
+#define P_PWRCTRL_MEM_PD1 ((volatile uint32_t *)0xfe007844)
+#define P_PWRCTRL_MEM_PD2 ((volatile uint32_t *)0xfe007848)
+#define P_PWRCTRL_MEM_PD3 ((volatile uint32_t *)0xfe00784c)
+#define P_PWRCTRL_MEM_PD4 ((volatile uint32_t *)0xfe007850)
+#define P_PWRCTRL_R_ISO_EN0 ((volatile uint32_t *)0xfe007880)
+#define P_PWRCTRL_R_PWR_OFF0 ((volatile uint32_t *)0xfe007884)
+#define P_PWRCTRL_R_MEM_PD0 ((volatile uint32_t *)0xfe007888)
+#define P_PWRCTRL_R_MEM_PD1 ((volatile uint32_t *)0xfe00788c)
+#define P_PWRCTRL_R_MEM_PD2 ((volatile uint32_t *)0xfe007890)
+#define P_PWRCTRL_R_MEM_PD3 ((volatile uint32_t *)0xfe007894)
+#define P_PWRCTRL_R_MEM_PD4 ((volatile uint32_t *)0xfe007898)
+//`define PWRCTRL_MEM_PD_DSPA 8'h10
+//`define PWRCTRL_MEM_PD_DSPB 8'h11
+//`define PWRCTRL_MEM_PD_RAMA 8'h12
+//`define PWRCTRL_MEM_PD_RAMB 8'h13
+//`define PWRCTRL_MEM_PD_CPU 8'h14
+//`define PWRCTRL_MEM_PD_AUDIO 8'h20
+//`define PWRCTRL_MEM_PD_USBCTRL 8'h21
+//`define PWRCTRL_MEM_PD_SPICC 8'h22
+//`define PWRCTRL_MEM_PD_SPIFC 8'h23
+//`define PWRCTRL_MEM_PD_IR 8'h24
+//`define PWRCTRL_MEM_PD_SDIO 8'h25
+//`define PWRCTRL_MEM_PD_KLEFUSE 8'h26
+//`define PWRCTRL_MEM_PD_PSRAM 8'h27
+//`define PWRCTRL_MEM_PD_DDR 8'h28
+//`define PWRCTRL_MEM_PD_DMC 8'h29
+#define P_PWRCTRL_AUTO_OFF_CTRL ((volatile uint32_t *)0xfe0078c0)
+#define P_PWRCTRL_AUTO_OFF ((volatile uint32_t *)0xfe0078c4)
+#define P_PWRCTRL_AUTO_OFF_STS ((volatile uint32_t *)0xfe0078c8)
+#define P_PWRCTRL_TIMER_TH_01 ((volatile uint32_t *)0xfe0078cc)
+#define P_PWRCTRL_TIMER_TH_23 ((volatile uint32_t *)0xfe0078d0)
+#define P_PWRCTRL_TIMER_TH_45 ((volatile uint32_t *)0xfe0078d4)
+#define P_PWRCTRL_TIMER_TH_67 ((volatile uint32_t *)0xfe0078d8)
+#define P_PWRCTRL_MASK_PWR_ACK0 ((volatile uint32_t *)0xfe007900)
+#define P_PWRCTRL_MASK_RSTN_OFF0 ((volatile uint32_t *)0xfe007904)
+#define P_PWRCTRL_MASK_RSTN_ON0 ((volatile uint32_t *)0xfe007908)
+#define P_PWRCTRL_MASK_PWR_OFF0 ((volatile uint32_t *)0xfe00790c)
+#define P_PWRCTRL_MASK_PWR_ON0 ((volatile uint32_t *)0xfe007910)
+#define P_PWRCTRL_MASK_ISO_OFF0 ((volatile uint32_t *)0xfe007914)
+#define P_PWRCTRL_MASK_ISO_ON0 ((volatile uint32_t *)0xfe007918)
+#define P_PWRCTRL_MASK_MEM_OFF0 ((volatile uint32_t *)0xfe007940)
+#define P_PWRCTRL_MASK_MEM_OFF1 ((volatile uint32_t *)0xfe007944)
+#define P_PWRCTRL_MASK_MEM_OFF2 ((volatile uint32_t *)0xfe007948)
+#define P_PWRCTRL_MASK_MEM_OFF3 ((volatile uint32_t *)0xfe00794c)
+#define P_PWRCTRL_MASK_MEM_OFF4 ((volatile uint32_t *)0xfe007950)
+#define P_PWRCTRL_MASK_MEM_ON0 ((volatile uint32_t *)0xfe007960)
+#define P_PWRCTRL_MASK_MEM_ON1 ((volatile uint32_t *)0xfe007964)
+#define P_PWRCTRL_MASK_MEM_ON2 ((volatile uint32_t *)0xfe007968)
+#define P_PWRCTRL_MASK_MEM_ON3 ((volatile uint32_t *)0xfe00796c)
+#define P_PWRCTRL_MASK_MEM_ON4 ((volatile uint32_t *)0xfe007970)
+//========================================================================
+// APB0_ANA_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007c00
+// -----------------------------------------------
+#define P_ANACTRL_FIXPLL_CTRL0 ((volatile uint32_t *)0xfe007c80)
+#define P_ANACTRL_FIXPLL_CTRL1 ((volatile uint32_t *)0xfe007c84)
+#define P_ANACTRL_FIXPLL_CTRL2 ((volatile uint32_t *)0xfe007c88)
+#define P_ANACTRL_FIXPLL_CTRL3 ((volatile uint32_t *)0xfe007c8c)
+#define P_ANACTRL_FIXPLL_CTRL4 ((volatile uint32_t *)0xfe007c90)
+#define P_ANACTRL_FIXPLL_STS ((volatile uint32_t *)0xfe007c94)
+#define P_ANACTRL_SYSPLL_CTRL0 ((volatile uint32_t *)0xfe007d00)
+#define P_ANACTRL_SYSPLL_CTRL1 ((volatile uint32_t *)0xfe007d04)
+#define P_ANACTRL_SYSPLL_CTRL2 ((volatile uint32_t *)0xfe007d08)
+#define P_ANACTRL_SYSPLL_CTRL3 ((volatile uint32_t *)0xfe007d0c)
+#define P_ANACTRL_SYSPLL_CTRL4 ((volatile uint32_t *)0xfe007d10)
+#define P_ANACTRL_SYSPLL_STS ((volatile uint32_t *)0xfe007d14)
+#define P_ANACTRL_HIFIPLL_CTRL0 ((volatile uint32_t *)0xfe007d40)
+#define P_ANACTRL_HIFIPLL_CTRL1 ((volatile uint32_t *)0xfe007d44)
+#define P_ANACTRL_HIFIPLL_CTRL2 ((volatile uint32_t *)0xfe007d48)
+#define P_ANACTRL_HIFIPLL_CTRL3 ((volatile uint32_t *)0xfe007d4c)
+#define P_ANACTRL_HIFIPLL_CTRL4 ((volatile uint32_t *)0xfe007d50)
+#define P_ANACTRL_HIFIPLL_STS ((volatile uint32_t *)0xfe007d54)
+#define P_ANACTRL_AUDDDS_CTRL0 ((volatile uint32_t *)0xfe007d80)
+#define P_ANACTRL_AUDDDS_CTRL1 ((volatile uint32_t *)0xfe007d84)
+#define P_ANACTRL_AUDDDS_CTRL2 ((volatile uint32_t *)0xfe007d88)
+#define P_ANACTRL_AUDDDS_CTRL3 ((volatile uint32_t *)0xfe007d8c)
+#define P_ANACTRL_AUDDDS_CTRL4 ((volatile uint32_t *)0xfe007d90)
+#define P_ANACTRL_AUDDDS_STS ((volatile uint32_t *)0xfe007d94)
+#define P_ANACTRL_MISCTOP_CTRL0 ((volatile uint32_t *)0xfe007dc0)
+#define P_ANACTRL_POR_CNTL ((volatile uint32_t *)0xfe007e08)
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe020000
+// -----------------------------------------------
+#define P_RSA_BASE ((volatile uint32_t *)0xfe020000)
+//========================================================================
+// CPUCTRL_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd000000
+// -----------------------------------------------
+#define P_CPUCTRL_CTRL0 ((volatile uint32_t *)0xfd000000)
+#define P_CPUCTRL_CTRL1 ((volatile uint32_t *)0xfd000004)
+#define P_CPUCTRL_CTRL2 ((volatile uint32_t *)0xfd000008)
+#define P_CPUCTRL_CTRL3 ((volatile uint32_t *)0xfd00000c)
+#define P_CPUCTRL_CTRL4 ((volatile uint32_t *)0xfd000010)
+#define P_CPUCTRL_CTRL5 ((volatile uint32_t *)0xfd000014)
+#define P_CPUCTRL_CTRL6 ((volatile uint32_t *)0xfd000018)
+#define P_CPUCTRL_CTRL7 ((volatile uint32_t *)0xfd00001c)
+#define P_CPUCTRL_CTRL8 ((volatile uint32_t *)0xfd000020)
+#define P_CPUCTRL_CTRL9 ((volatile uint32_t *)0xfd000024)
+#define P_CPUCTRL_CTRL10 ((volatile uint32_t *)0xfd000028)
+#define P_CPUCTRL_CTRL11 ((volatile uint32_t *)0xfd00002c)
+#define P_CPUCTRL_CTRL12 ((volatile uint32_t *)0xfd000030)
+#define P_CPUCTRL_CTRL13 ((volatile uint32_t *)0xfd000034)
+#define P_CPUCTRL_CTRL14 ((volatile uint32_t *)0xfd000038)
+#define P_CPUCTRL_CTRL15 ((volatile uint32_t *)0xfd00003c)
+#define P_CPUCTRL_STS0 ((volatile uint32_t *)0xfd000040)
+#define P_CPUCTRL_STS1 ((volatile uint32_t *)0xfd000044)
+#define P_CPUCTRL_STS2 ((volatile uint32_t *)0xfd000048)
+#define P_CPUCTRL_STS3 ((volatile uint32_t *)0xfd00004c)
+#define P_CPUCTRL_STS4 ((volatile uint32_t *)0xfd000050)
+#define P_CPUCTRL_STS5 ((volatile uint32_t *)0xfd000054)
+#define P_CPUCTRL_STS6 ((volatile uint32_t *)0xfd000058)
+#define P_CPUCTRL_STS7 ((volatile uint32_t *)0xfd00005c)
+#define P_CPUCTRL_STS8 ((volatile uint32_t *)0xfd000060)
+#define P_CPUCTRL_STS9 ((volatile uint32_t *)0xfd000064)
+#define P_CPUCTRL_CLK_CTRL0 ((volatile uint32_t *)0xfd000080)
+#define P_CPUCTRL_CLK_CTRL1 ((volatile uint32_t *)0xfd000084)
+#define P_CPUCTRL_CLK_CTRL2 ((volatile uint32_t *)0xfd000088)
+#define P_CPUCTRL_CLK_CTRL3 ((volatile uint32_t *)0xfd00008c)
+#define P_CPUCTRL_CLK_CTRL4 ((volatile uint32_t *)0xfd000090)
+#define P_CPUCTRL_CLK_CTRL5 ((volatile uint32_t *)0xfd000094)
+#define P_CPUCTRL_CLK_CTRL6 ((volatile uint32_t *)0xfd000098)
+#define P_CPUCTRL_CLK_CTRL7 ((volatile uint32_t *)0xfd00009c)
+#define P_CPUCTRL_RESET_CTRL ((volatile uint32_t *)0xfd0000c0)
+#define P_CPUCTRL_ROM_DISABLE ((volatile uint32_t *)0xfd0000c4)
+//========================================================================
+// RAMA_SEC_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd000800
+// -----------------------------------------------
+#define P_SRAM_RANGE0_STA ((volatile uint32_t *)0xfd000800)
+#define P_SRAM_RANGE1_STA ((volatile uint32_t *)0xfd000804)
+#define P_SRAM_RANGE2_STA ((volatile uint32_t *)0xfd000808)
+#define P_SRAM_RANGE3_STA ((volatile uint32_t *)0xfd00080c)
+#define P_SRAM_RANGE4_STA ((volatile uint32_t *)0xfd000810)
+#define P_SRAM_RANGE5_STA ((volatile uint32_t *)0xfd000814)
+#define P_SRAM_RANGE6_STA ((volatile uint32_t *)0xfd000818)
+#define P_SRAM_RANGE0_EDA ((volatile uint32_t *)0xfd00081c)
+#define P_SRAM_RANGE1_EDA ((volatile uint32_t *)0xfd000820)
+#define P_SRAM_RANGE2_EDA ((volatile uint32_t *)0xfd000824)
+#define P_SRAM_RANGE3_EDA ((volatile uint32_t *)0xfd000828)
+#define P_SRAM_RANGE4_EDA ((volatile uint32_t *)0xfd00082c)
+#define P_SRAM_RANGE5_EDA ((volatile uint32_t *)0xfd000830)
+#define P_SRAM_RANGE6_EDA ((volatile uint32_t *)0xfd000834)
+#define P_SRAM_RANGE0_CTRL0 ((volatile uint32_t *)0xfd000838)
+#define P_SRAM_RANGE1_CTRL0 ((volatile uint32_t *)0xfd00083c)
+#define P_SRAM_RANGE2_CTRL0 ((volatile uint32_t *)0xfd000840)
+#define P_SRAM_RANGE3_CTRL0 ((volatile uint32_t *)0xfd000844)
+#define P_SRAM_RANGE4_CTRL0 ((volatile uint32_t *)0xfd000848)
+#define P_SRAM_RANGE5_CTRL0 ((volatile uint32_t *)0xfd00084c)
+#define P_SRAM_RANGE6_CTRL0 ((volatile uint32_t *)0xfd000850)
+#define P_SRAM_RANGE7_CTRL0 ((volatile uint32_t *)0xfd000854)
+#define P_SRAM_RANGE0_CTRL1 ((volatile uint32_t *)0xfd000858)
+#define P_SRAM_RANGE1_CTRL1 ((volatile uint32_t *)0xfd00085c)
+#define P_SRAM_RANGE2_CTRL1 ((volatile uint32_t *)0xfd000860)
+#define P_SRAM_RANGE3_CTRL1 ((volatile uint32_t *)0xfd000864)
+#define P_SRAM_RANGE4_CTRL1 ((volatile uint32_t *)0xfd000868)
+#define P_SRAM_RANGE5_CTRL1 ((volatile uint32_t *)0xfd00086c)
+#define P_SRAM_RANGE6_CTRL1 ((volatile uint32_t *)0xfd000870)
+#define P_SRAM_RANGE7_CTRL1 ((volatile uint32_t *)0xfd000874)
+#define P_SRAM_SEC_CTRL0 ((volatile uint32_t *)0xfd000878)
+#define P_SRAM_REG_LOCK ((volatile uint32_t *)0xfd00087c)
+//========================================================================
+// RAMB_SEC_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd000c00
+// -----------------------------------------------
+#define P_SRAM_RANGE0_STA_B ((volatile uint32_t *)0xfd000c00)
+#define P_SRAM_RANGE1_STA_B ((volatile uint32_t *)0xfd000c04)
+#define P_SRAM_RANGE2_STA_B ((volatile uint32_t *)0xfd000c08)
+#define P_SRAM_RANGE3_STA_B ((volatile uint32_t *)0xfd000c0c)
+#define P_SRAM_RANGE4_STA_B ((volatile uint32_t *)0xfd000c10)
+#define P_SRAM_RANGE5_STA_B ((volatile uint32_t *)0xfd000c14)
+#define P_SRAM_RANGE6_STA_B ((volatile uint32_t *)0xfd000c18)
+#define P_SRAM_RANGE0_EDA_B ((volatile uint32_t *)0xfd000c1c)
+#define P_SRAM_RANGE1_EDA_B ((volatile uint32_t *)0xfd000c20)
+#define P_SRAM_RANGE2_EDA_B ((volatile uint32_t *)0xfd000c24)
+#define P_SRAM_RANGE3_EDA_B ((volatile uint32_t *)0xfd000c28)
+#define P_SRAM_RANGE4_EDA_B ((volatile uint32_t *)0xfd000c2c)
+#define P_SRAM_RANGE5_EDA_B ((volatile uint32_t *)0xfd000c30)
+#define P_SRAM_RANGE6_EDA_B ((volatile uint32_t *)0xfd000c34)
+#define P_SRAM_RANGE0_CTRL0_B ((volatile uint32_t *)0xfd000c38)
+#define P_SRAM_RANGE1_CTRL0_B ((volatile uint32_t *)0xfd000c3c)
+#define P_SRAM_RANGE2_CTRL0_B ((volatile uint32_t *)0xfd000c40)
+#define P_SRAM_RANGE3_CTRL0_B ((volatile uint32_t *)0xfd000c44)
+#define P_SRAM_RANGE4_CTRL0_B ((volatile uint32_t *)0xfd000c48)
+#define P_SRAM_RANGE5_CTRL0_B ((volatile uint32_t *)0xfd000c4c)
+#define P_SRAM_RANGE6_CTRL0_B ((volatile uint32_t *)0xfd000c50)
+#define P_SRAM_RANGE7_CTRL0_B ((volatile uint32_t *)0xfd000c54)
+#define P_SRAM_RANGE0_CTRL1_B ((volatile uint32_t *)0xfd000c58)
+#define P_SRAM_RANGE1_CTRL1_B ((volatile uint32_t *)0xfd000c5c)
+#define P_SRAM_RANGE2_CTRL1_B ((volatile uint32_t *)0xfd000c60)
+#define P_SRAM_RANGE3_CTRL1_B ((volatile uint32_t *)0xfd000c64)
+#define P_SRAM_RANGE4_CTRL1_B ((volatile uint32_t *)0xfd000c68)
+#define P_SRAM_RANGE5_CTRL1_B ((volatile uint32_t *)0xfd000c6c)
+#define P_SRAM_RANGE6_CTRL1_B ((volatile uint32_t *)0xfd000c70)
+#define P_SRAM_RANGE7_CTRL1_B ((volatile uint32_t *)0xfd000c74)
+#define P_SRAM_SEC_CTRL0_B ((volatile uint32_t *)0xfd000c78)
+#define P_SRAM_REG_LOCK_B ((volatile uint32_t *)0xfd000c7c)
+//
+// Reading file: REG_LIST_DSP_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//========================================================================
+// DSPA - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe030000
+// -----------------------------------------------
+#define P_DSP_CFG0 ((volatile uint32_t *)0xfe030000)
+#define P_DSP_CFG1 ((volatile uint32_t *)0xfe030004)
+#define P_DSP_CFG2 ((volatile uint32_t *)0xfe030008)
+#define P_DSP_IMPWIRE ((volatile uint32_t *)0xfe03000c)
+#define P_DSP_RESET_VEC ((volatile uint32_t *)0xfe030010)
+#define P_DSP_SEC_CFG0 ((volatile uint32_t *)0xfe030018)
+#define P_DSP_SEC_CFG1 ((volatile uint32_t *)0xfe03001c)
+#define P_DSP_IRQ_CTRL0 ((volatile uint32_t *)0xfe030040)
+#define P_DSP_IRQ_CTRL1 ((volatile uint32_t *)0xfe030044)
+#define P_DSP_IRQ_CTRL2 ((volatile uint32_t *)0xfe030048)
+#define P_DSP_IRQ_CTRL3 ((volatile uint32_t *)0xfe03004c)
+#define P_DSP_IRQ_CTRL4 ((volatile uint32_t *)0xfe030050)
+#define P_DSP_IRQ_CTRL5 ((volatile uint32_t *)0xfe030054)
+#define P_DSP_IRQ_CTRL6 ((volatile uint32_t *)0xfe030058)
+#define P_DSP_IRQ_CTRL7 ((volatile uint32_t *)0xfe03005c)
+#define P_DSP_IRQ_CTRL8 ((volatile uint32_t *)0xfe030060)
+#define P_DSP_IRQ_STS ((volatile uint32_t *)0xfe03007c)
+#define P_DSP_REMAP0 ((volatile uint32_t *)0xfe030080)
+#define P_DSP_REMAP1 ((volatile uint32_t *)0xfe030084)
+#define P_DSP_REMAP2 ((volatile uint32_t *)0xfe030088)
+#define P_DSP_STS0 ((volatile uint32_t *)0xfe030100)
+#define P_DSP_STS1 ((volatile uint32_t *)0xfe030104)
+#define P_DSP_STS2 ((volatile uint32_t *)0xfe030108)
+#define P_DSP_STS3 ((volatile uint32_t *)0xfe03010c)
+#define P_DSP_STS4 ((volatile uint32_t *)0xfe030110)
+#define P_DSP_STS5 ((volatile uint32_t *)0xfe030114)
+#define P_DSP_MAILBOX_SET_0 ((volatile uint32_t *)0xfe030140)
+#define P_DSP_MAILBOX_SET_1 ((volatile uint32_t *)0xfe030144)
+#define P_DSP_MAILBOX_SET_2 ((volatile uint32_t *)0xfe030148)
+#define P_DSP_MAILBOX_SET_3 ((volatile uint32_t *)0xfe03014c)
+#define P_DSP_MAILBOX_SET_4 ((volatile uint32_t *)0xfe030150)
+#define P_DSP_MAILBOX_SET_5 ((volatile uint32_t *)0xfe030154)
+#define P_DSP_MAILBOX_SET_6 ((volatile uint32_t *)0xfe030158)
+#define P_DSP_MAILBOX_SET_7 ((volatile uint32_t *)0xfe03015c)
+#define P_DSP_MAILBOX_SET_8 ((volatile uint32_t *)0xfe030160)
+#define P_DSP_MAILBOX_SET_9 ((volatile uint32_t *)0xfe030164)
+#define P_DSP_MAILBOX_SET_10 ((volatile uint32_t *)0xfe030168)
+#define P_DSP_MAILBOX_SET_11 ((volatile uint32_t *)0xfe03016c)
+#define P_DSP_MAILBOX_CLR_0 ((volatile uint32_t *)0xfe030180)
+#define P_DSP_MAILBOX_CLR_1 ((volatile uint32_t *)0xfe030184)
+#define P_DSP_MAILBOX_CLR_2 ((volatile uint32_t *)0xfe030188)
+#define P_DSP_MAILBOX_CLR_3 ((volatile uint32_t *)0xfe03018c)
+#define P_DSP_MAILBOX_CLR_4 ((volatile uint32_t *)0xfe030190)
+#define P_DSP_MAILBOX_CLR_5 ((volatile uint32_t *)0xfe030194)
+#define P_DSP_MAILBOX_CLR_6 ((volatile uint32_t *)0xfe030198)
+#define P_DSP_MAILBOX_CLR_7 ((volatile uint32_t *)0xfe03019c)
+#define P_DSP_MAILBOX_CLR_8 ((volatile uint32_t *)0xfe0301a0)
+#define P_DSP_MAILBOX_CLR_9 ((volatile uint32_t *)0xfe0301a4)
+#define P_DSP_MAILBOX_CLR_10 ((volatile uint32_t *)0xfe0301a8)
+#define P_DSP_MAILBOX_CLR_11 ((volatile uint32_t *)0xfe0301ac)
+#define P_DSP_MAILBOX_STAT_0 ((volatile uint32_t *)0xfe0301c0)
+#define P_DSP_MAILBOX_STAT_1 ((volatile uint32_t *)0xfe0301c4)
+#define P_DSP_MAILBOX_STAT_2 ((volatile uint32_t *)0xfe0301c8)
+#define P_DSP_MAILBOX_STAT_3 ((volatile uint32_t *)0xfe0301cc)
+#define P_DSP_MAILBOX_STAT_4 ((volatile uint32_t *)0xfe0301d0)
+#define P_DSP_MAILBOX_STAT_5 ((volatile uint32_t *)0xfe0301d4)
+#define P_DSP_MAILBOX_STAT_6 ((volatile uint32_t *)0xfe0301d8)
+#define P_DSP_MAILBOX_STAT_7 ((volatile uint32_t *)0xfe0301dc)
+#define P_DSP_MAILBOX_STAT_8 ((volatile uint32_t *)0xfe0301e0)
+#define P_DSP_MAILBOX_STAT_9 ((volatile uint32_t *)0xfe0301e4)
+#define P_DSP_MAILBOX_STAT_10 ((volatile uint32_t *)0xfe0301e8)
+#define P_DSP_MAILBOX_STAT_11 ((volatile uint32_t *)0xfe0301ec)
+#define P_DSP_QIF_CTRL ((volatile uint32_t *)0xfe030200)
+#define P_DSP_QIF_STS ((volatile uint32_t *)0xfe030204)
+#define P_DSP_WRFIFO_TOCPUA ((volatile uint32_t *)0xfe030208)
+#define P_DSP_WRFIFO_TOCPUB ((volatile uint32_t *)0xfe03020c)
+#define P_DSP_WRFIFO_TODSP ((volatile uint32_t *)0xfe030210)
+#define P_DSP_RDFIFO_FRCPUA ((volatile uint32_t *)0xfe030220)
+#define P_DSP_RDFIFO_FRCPUB ((volatile uint32_t *)0xfe030224)
+#define P_DSP_RDFIFO_FRDSP ((volatile uint32_t *)0xfe030228)
+//========================================================================
+// DSPB - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe040000
+// -----------------------------------------------
+#define P_DSPB_CFG0 ((volatile uint32_t *)0xfe040000)
+#define P_DSPB_CFG1 ((volatile uint32_t *)0xfe040004)
+#define P_DSPB_CFG2 ((volatile uint32_t *)0xfe040008)
+#define P_DSPB_IMPWIRE ((volatile uint32_t *)0xfe04000c)
+#define P_DSPB_RESET_VEC ((volatile uint32_t *)0xfe040010)
+#define P_DSPB_SEC_CFG0 ((volatile uint32_t *)0xfe040018)
+#define P_DSPB_SEC_CFG1 ((volatile uint32_t *)0xfe04001c)
+#define P_DSPB_IRQ_CTRL0 ((volatile uint32_t *)0xfe040040)
+#define P_DSPB_IRQ_CTRL1 ((volatile uint32_t *)0xfe040044)
+#define P_DSPB_IRQ_CTRL2 ((volatile uint32_t *)0xfe040048)
+#define P_DSPB_IRQ_CTRL3 ((volatile uint32_t *)0xfe04004c)
+#define P_DSPB_IRQ_CTRL4 ((volatile uint32_t *)0xfe040050)
+#define P_DSPB_IRQ_CTRL5 ((volatile uint32_t *)0xfe040054)
+#define P_DSPB_IRQ_CTRL6 ((volatile uint32_t *)0xfe040058)
+#define P_DSPB_IRQ_CTRL7 ((volatile uint32_t *)0xfe04005c)
+#define P_DSPB_IRQ_CTRL8 ((volatile uint32_t *)0xfe040060)
+#define P_DSPB_IRQ_STS ((volatile uint32_t *)0xfe04007c)
+#define P_DSPB_REMAP0 ((volatile uint32_t *)0xfe040080)
+#define P_DSPB_REMAP1 ((volatile uint32_t *)0xfe040084)
+#define P_DSPB_REMAP2 ((volatile uint32_t *)0xfe040088)
+#define P_DSPB_STS0 ((volatile uint32_t *)0xfe040100)
+#define P_DSPB_STS1 ((volatile uint32_t *)0xfe040104)
+#define P_DSPB_STS2 ((volatile uint32_t *)0xfe040108)
+#define P_DSPB_STS3 ((volatile uint32_t *)0xfe04010c)
+#define P_DSPB_STS4 ((volatile uint32_t *)0xfe040110)
+#define P_DSPB_STS5 ((volatile uint32_t *)0xfe040114)
+#define P_DSPB_MAILBOX_SET_0 ((volatile uint32_t *)0xfe040140)
+#define P_DSPB_MAILBOX_SET_1 ((volatile uint32_t *)0xfe040144)
+#define P_DSPB_MAILBOX_SET_2 ((volatile uint32_t *)0xfe040148)
+#define P_DSPB_MAILBOX_SET_3 ((volatile uint32_t *)0xfe04014c)
+#define P_DSPB_MAILBOX_SET_4 ((volatile uint32_t *)0xfe040150)
+#define P_DSPB_MAILBOX_SET_5 ((volatile uint32_t *)0xfe040154)
+#define P_DSPB_MAILBOX_SET_6 ((volatile uint32_t *)0xfe040158)
+#define P_DSPB_MAILBOX_SET_7 ((volatile uint32_t *)0xfe04015c)
+#define P_DSPB_MAILBOX_SET_8 ((volatile uint32_t *)0xfe040160)
+#define P_DSPB_MAILBOX_SET_9 ((volatile uint32_t *)0xfe040164)
+#define P_DSPB_MAILBOX_SET_10 ((volatile uint32_t *)0xfe040168)
+#define P_DSPB_MAILBOX_SET_11 ((volatile uint32_t *)0xfe04016c)
+#define P_DSPB_MAILBOX_CLR_0 ((volatile uint32_t *)0xfe040180)
+#define P_DSPB_MAILBOX_CLR_1 ((volatile uint32_t *)0xfe040184)
+#define P_DSPB_MAILBOX_CLR_2 ((volatile uint32_t *)0xfe040188)
+#define P_DSPB_MAILBOX_CLR_3 ((volatile uint32_t *)0xfe04018c)
+#define P_DSPB_MAILBOX_CLR_4 ((volatile uint32_t *)0xfe040190)
+#define P_DSPB_MAILBOX_CLR_5 ((volatile uint32_t *)0xfe040194)
+#define P_DSPB_MAILBOX_CLR_6 ((volatile uint32_t *)0xfe040198)
+#define P_DSPB_MAILBOX_CLR_7 ((volatile uint32_t *)0xfe04019c)
+#define P_DSPB_MAILBOX_CLR_8 ((volatile uint32_t *)0xfe0401a0)
+#define P_DSPB_MAILBOX_CLR_9 ((volatile uint32_t *)0xfe0401a4)
+#define P_DSPB_MAILBOX_CLR_10 ((volatile uint32_t *)0xfe0401a8)
+#define P_DSPB_MAILBOX_CLR_11 ((volatile uint32_t *)0xfe0401ac)
+#define P_DSPB_MAILBOX_STAT_0 ((volatile uint32_t *)0xfe0401c0)
+#define P_DSPB_MAILBOX_STAT_1 ((volatile uint32_t *)0xfe0401c4)
+#define P_DSPB_MAILBOX_STAT_2 ((volatile uint32_t *)0xfe0401c8)
+#define P_DSPB_MAILBOX_STAT_3 ((volatile uint32_t *)0xfe0401cc)
+#define P_DSPB_MAILBOX_STAT_4 ((volatile uint32_t *)0xfe0401d0)
+#define P_DSPB_MAILBOX_STAT_5 ((volatile uint32_t *)0xfe0401d4)
+#define P_DSPB_MAILBOX_STAT_6 ((volatile uint32_t *)0xfe0401d8)
+#define P_DSPB_MAILBOX_STAT_7 ((volatile uint32_t *)0xfe0401dc)
+#define P_DSPB_MAILBOX_STAT_8 ((volatile uint32_t *)0xfe0401e0)
+#define P_DSPB_MAILBOX_STAT_9 ((volatile uint32_t *)0xfe0401e4)
+#define P_DSPB_MAILBOX_STAT_10 ((volatile uint32_t *)0xfe0401e8)
+#define P_DSPB_MAILBOX_STAT_11 ((volatile uint32_t *)0xfe0401ec)
+#define P_DSPB_QIF_CTRL ((volatile uint32_t *)0xfe040200)
+#define P_DSPB_QIF_STS ((volatile uint32_t *)0xfe040204)
+#define P_DSPB_WRFIFO_TOCPUA ((volatile uint32_t *)0xfe040208)
+#define P_DSPB_WRFIFO_TOCPUB ((volatile uint32_t *)0xfe04020c)
+#define P_DSPB_WRFIFO_TODSP ((volatile uint32_t *)0xfe040210)
+#define P_DSPB_RDFIFO_FRCPUA ((volatile uint32_t *)0xfe040220)
+#define P_DSPB_RDFIFO_FRCPUB ((volatile uint32_t *)0xfe040224)
+#define P_DSPB_RDFIFO_FRDSP ((volatile uint32_t *)0xfe040228)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: REG_LIST_DSP_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: ./REG_LIST_RTL.h
+//
+
+#endif // P_REGISTER_H
+
diff --git a/arch/arm/include/asm/arch-c1/pinctrl_init.h b/arch/arm/include/asm/arch-c1/pinctrl_init.h
new file mode 100644
index 0000000..cfbc42a
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/pinctrl_init.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _MESON_PINCTRL_INIT_H_
+#define _MESON_PINCTRL_INIT_H_
+
+#define PIN_CONTROLLER_NUM 2
+extern int pinctrl_devices_active(int pinctrl_num);
+
+#endif /* _MESON_PINCTRL_INIT_H_ */
diff --git a/arch/arm/include/asm/arch-c1/pll.h b/arch/arm/include/asm/arch-c1/pll.h
new file mode 100644
index 0000000..5821c3c
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/pll.h
@@ -0,0 +1,133 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __PLL_H
+#define __PLL_H
+
+#define PLL_TEST_SYS_TOTAL 8
+#define PLL_TEST_HDMI_TOTAL 3
+
+typedef struct sys_pll_set_s {
+ unsigned int cpu_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+}sys_pll_set_t;
+
+typedef struct sys_pll_cfg_s {
+ sys_pll_set_t sys_pll[PLL_TEST_SYS_TOTAL];
+}sys_pll_cfg_t;
+
+typedef struct hifi_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+}hifi_pll_set_t;
+
+
+#if 0
+unsigned int fix_pll_cfg[6] = {
+ /* CNTL, CNTL2, CNTL3, CNTL4, CNTL5, CNTL6*/
+ /*2G*/ 0x600006FA, 0x59C80000, 0xCA753822, 0x00010006, 0x95520E1A, 0xFC454545,
+};
+
+unsigned int ddr_pll_cfg[][6] = {
+ {0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+#endif
+
+typedef struct hifipll_rate_table_s {
+ unsigned int rate;
+ unsigned int m;
+ unsigned int n;
+ unsigned int od;
+}hifipll_rate_table_t;
+
+typedef struct gpll_rate_table_s {
+ unsigned int rate;
+ unsigned int m;
+ unsigned int n;
+ unsigned int od;
+}gpll_rate_table_t;
+
+typedef struct ddspll_rate_table_t {
+ unsigned int RATE;
+ unsigned int CTS;
+ unsigned int N;
+}ddspll_rate_table_t;
+
+typedef struct gp_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+}gp_pll_set_t;
+
+typedef struct dds_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int misctop_cntl0;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+}dds_pll_set_t;
+
+typedef struct usbphy_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+}usbphy_pll_set_t;
+
+typedef struct ethphy_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+}ethphy_pll_set_t;
+
+#if 0
+unsigned int hdmi_pll_cfg[][7] = {
+ /* get from enc_clk_config.c */
+ /* freq, cntl, cntl1, cntl2, cntl3, cntl4, cntl5 */
+ {5940000, 0x4000027b, 0x800cb300, 0xc60f30e0, 0x0c8e0000, 0x001fa729, 0x01a31500},
+ {5405400, 0x400002e1, 0x800cb0e6, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
+ {4455000, 0x400002b9, 0x800cb280, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
+ {4324320, 0x400002b4, 0x800cb0b8, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
+ {3712500, 0x4000029a, 0x800cb2c0, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
+ {3450000, 0x4000028f, 0x800cb300, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
+ {3243240, 0x40000287, 0x800cb08a, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
+ {2970000, 0x4000027b, 0x800cb300, 0x860f30c4, 0x0c8e0000, 0x001fa729, 0x01a31500},
+};
+#endif
+
+enum pll_enum {
+ PLL_SYS = 0,
+ PLL_FIX,
+ PLL_DDR,
+ PLL_HIFI,
+ PLL_GP,
+ PLL_DDS,
+ PLL_USBPHY,
+ PLL_ETHPHY,
+ PLL_ENUM,
+};
+int pll_test(int argc, char * const argv[]);
+
+#endif /* __PLL_H */
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-c1/pwr_ctrl.h b/arch/arm/include/asm/arch-c1/pwr_ctrl.h
new file mode 100644
index 0000000..15d4baa
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/pwr_ctrl.h
@@ -0,0 +1,47 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#define PWR_ON 1
+#define PWR_OFF 0
+
+enum pm_e {
+ PM_CPU_PWR0,
+ PM_CPU_CORE0,
+ PM_CPU_CORE1,
+ PM_DSP_A = 8,
+ PM_DSP_B,
+ PM_UART,
+ PM_DMC,
+ PM_I2C,
+ PM_SDEMMC_B,
+ PM_ACODEC,
+ PM_AUDIO,
+ PM_MKL_OTP,
+ PM_DMA,
+ PM_SDEMMC_A,
+ PM_SRAM_A,
+ PM_SRAM_B,
+ PM_IR,
+ PM_SPICC,
+ PM_SPIFC,
+ PM_USB,
+ PM_NIC,
+ PM_PDM,
+ PM_RSA,
+ PM_MIPI_ISP,
+ PM_HCODEC,
+ PM_WAVE,
+ PM_SDEMMC_C,
+ PM_SRAM_C,
+ PM_GDC,
+ PM_GE2D,
+ PM_NNA,
+ PM_ETH,
+ PM_GIC,
+ PM_DDR,
+ PM_SPICC_B
+};
+
+unsigned long pwr_ctrl_psci_smc(unsigned int power_domain, bool power_control);
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-c1/register.h b/arch/arm/include/asm/arch-c1/register.h
new file mode 100644
index 0000000..34a8114
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/register.h
@@ -0,0 +1,7225 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifdef REGISTER_H
+#else
+#define REGISTER_H
+
+//
+// Reading file: ./REG_LIST_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Reading file: REG_LIST_AUDIO_RTL.h
+//
+//========================================================================
+// AUDIO - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe050000
+// -----------------------------------------------
+#define EE_AUDIO_CLK_GATE_EN0 ((0x0000 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_GATE_EN1 ((0x0001 << 2) + 0xfe050000)
+#define EE_AUDIO_MCLK_A_CTRL ((0x0002 << 2) + 0xfe050000)
+#define EE_AUDIO_MCLK_B_CTRL ((0x0003 << 2) + 0xfe050000)
+#define EE_AUDIO_MCLK_C_CTRL ((0x0004 << 2) + 0xfe050000)
+#define EE_AUDIO_MCLK_D_CTRL ((0x0005 << 2) + 0xfe050000)
+#define EE_AUDIO_MCLK_E_CTRL ((0x0006 << 2) + 0xfe050000)
+#define EE_AUDIO_MCLK_F_CTRL ((0x0007 << 2) + 0xfe050000)
+#define EE_AUDIO_PAD_CTRL0 ((0x0008 << 2) + 0xfe050000)
+#define EE_AUDIO_PAD_CTRL1 ((0x0009 << 2) + 0xfe050000)
+#define EE_AUDIO_SW_RESET0 ((0x000a << 2) + 0xfe050000)
+#define EE_AUDIO_SW_RESET1 ((0x000b << 2) + 0xfe050000)
+#define EE_AUDIO_CLK81_CTRL ((0x000c << 2) + 0xfe050000)
+#define EE_AUDIO_CLK81_EN ((0x000d << 2) + 0xfe050000)
+#define EE_AUDIO_MST_A_SCLK_CTRL0 ((0x0010 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_A_SCLK_CTRL1 ((0x0011 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_B_SCLK_CTRL0 ((0x0012 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_B_SCLK_CTRL1 ((0x0013 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_C_SCLK_CTRL0 ((0x0014 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_C_SCLK_CTRL1 ((0x0015 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_D_SCLK_CTRL0 ((0x0016 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_D_SCLK_CTRL1 ((0x0017 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_E_SCLK_CTRL0 ((0x0018 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_E_SCLK_CTRL1 ((0x0019 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_F_SCLK_CTRL0 ((0x001a << 2) + 0xfe050000)
+#define EE_AUDIO_MST_F_SCLK_CTRL1 ((0x001b << 2) + 0xfe050000)
+#define EE_AUDIO_MST_DLY_CTRL0 ((0x001c << 2) + 0xfe050000)
+#define EE_AUDIO_MST_DLY_CTRL1 ((0x001d << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMIN_A_CTRL ((0x0020 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMIN_B_CTRL ((0x0021 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMIN_C_CTRL ((0x0022 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMIN_LB_CTRL ((0x0023 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMOUT_A_CTRL ((0x0024 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMOUT_B_CTRL ((0x0025 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMOUT_C_CTRL ((0x0026 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_SPDIFIN_CTRL ((0x0027 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_SPDIFOUT_CTRL ((0x0028 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_RESAMPLEA_CTRL ((0x0029 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_LOCKER_CTRL ((0x002a << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_PDMIN_CTRL0 ((0x002b << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_PDMIN_CTRL1 ((0x002c << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_SPDIFOUT_B_CTRL ((0x002d << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_RESAMPLEB_CTRL ((0x002e << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_SPDIFIN_LB_CTRL ((0x002f << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_EQDRC_CTRL0 ((0x0030 << 2) + 0xfe050000)
+#define EE_AUDIO_VAD_CLK_CTRL ((0x0031 << 2) + 0xfe050000)
+#define EE_AUDIO_EARCTX_CMDC_CLK_CTRL ((0x0032 << 2) + 0xfe050000)
+#define EE_AUDIO_EARCTX_DMAC_CLK_CTRL ((0x0033 << 2) + 0xfe050000)
+#define EE_AUDIO_EARCRX_CMDC_CLK_CTRL ((0x0034 << 2) + 0xfe050000)
+#define EE_AUDIO_EARCRX_DMAC_CLK_CTRL ((0x0035 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_LOCKERB_CTRL ((0x0036 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_CTRL0 ((0x0040 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_CTRL1 ((0x0041 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_START_ADDR ((0x0042 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_FINISH_ADDR ((0x0043 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_INT_ADDR ((0x0044 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_STATUS1 ((0x0045 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_STATUS2 ((0x0046 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_START_ADDRB ((0x0047 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_FINISH_ADDRB ((0x0048 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_INIT_ADDR ((0x0049 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_CTRL2 ((0x004a << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_CTRL0 ((0x0050 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_CTRL1 ((0x0051 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_START_ADDR ((0x0052 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_FINISH_ADDR ((0x0053 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_INT_ADDR ((0x0054 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_STATUS1 ((0x0055 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_STATUS2 ((0x0056 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_START_ADDRB ((0x0057 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_FINISH_ADDRB ((0x0058 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_INIT_ADDR ((0x0059 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_CTRL2 ((0x005a << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_CTRL0 ((0x0060 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_CTRL1 ((0x0061 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_START_ADDR ((0x0062 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_FINISH_ADDR ((0x0063 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_INT_ADDR ((0x0064 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_STATUS1 ((0x0065 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_STATUS2 ((0x0066 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_START_ADDRB ((0x0067 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_FINISH_ADDRB ((0x0068 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_INIT_ADDR ((0x0069 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_CTRL2 ((0x006a << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_CTRL0 ((0x0070 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_CTRL1 ((0x0071 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_START_ADDR ((0x0072 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_FINISH_ADDR ((0x0073 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_INT_ADDR ((0x0074 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_STATUS1 ((0x0075 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_STATUS2 ((0x0076 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_START_ADDRB ((0x0077 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_FINISH_ADDRB ((0x0078 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_INIT_ADDR ((0x0079 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_CTRL2 ((0x007a << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_CTRL0 ((0x0080 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_CTRL1 ((0x0081 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_START_ADDR ((0x0082 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_FINISH_ADDR ((0x0083 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_INT_ADDR ((0x0084 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_STATUS1 ((0x0085 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_STATUS2 ((0x0086 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_START_ADDRB ((0x0087 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_FINISH_ADDRB ((0x0088 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_INIT_ADDR ((0x0089 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_CTRL2 ((0x008a << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_CTRL0 ((0x0090 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_CTRL1 ((0x0091 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_START_ADDR ((0x0092 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_FINISH_ADDR ((0x0093 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_INT_ADDR ((0x0094 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_STATUS1 ((0x0095 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_STATUS2 ((0x0096 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_START_ADDRB ((0x0097 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_FINISH_ADDRB ((0x0098 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_INIT_ADDR ((0x0099 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_CTRL2 ((0x009a << 2) + 0xfe050000)
+#define EE_AUDIO_ARB_CTRL ((0x00a0 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_CTRL0 ((0x00b0 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_CTRL1 ((0x00b1 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_CTRL2 ((0x00b2 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_CTRL3 ((0x00b3 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_DAT_CH_ID0 ((0x00b4 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_DAT_CH_ID1 ((0x00b5 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_DAT_CH_ID2 ((0x00b6 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_DAT_CH_ID3 ((0x00b7 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_LB_CH_ID0 ((0x00b8 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_LB_CH_ID1 ((0x00b9 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_LB_CH_ID2 ((0x00ba << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_LB_CH_ID3 ((0x00bb << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_STS ((0x00bc << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_CTRL ((0x00c0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_SWAP0 ((0x00c1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK0 ((0x00c2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK1 ((0x00c3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK2 ((0x00c4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK3 ((0x00c5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_STAT ((0x00c6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE_VAL ((0x00c7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE0 ((0x00c8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE1 ((0x00c9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE2 ((0x00ca << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE3 ((0x00cb << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_CTRL ((0x00d0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_SWAP0 ((0x00d1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK0 ((0x00d2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK1 ((0x00d3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK2 ((0x00d4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK3 ((0x00d5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_STAT ((0x00d6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE_VAL ((0x00d7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE0 ((0x00d8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE1 ((0x00d9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE2 ((0x00da << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE3 ((0x00db << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_CTRL ((0x00e0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_SWAP0 ((0x00e1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK0 ((0x00e2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK1 ((0x00e3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK2 ((0x00e4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK3 ((0x00e5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_STAT ((0x00e6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE_VAL ((0x00e7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE0 ((0x00e8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE1 ((0x00e9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE2 ((0x00ea << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE3 ((0x00eb << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_CTRL ((0x00f0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_SWAP0 ((0x00f1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK0 ((0x00f2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK1 ((0x00f3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK2 ((0x00f4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK3 ((0x00f5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_STAT ((0x00f6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE_VAL ((0x00f7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE0 ((0x00f8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE1 ((0x00f9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE2 ((0x00fa << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE3 ((0x00fb << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL0 ((0x0100 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL1 ((0x0101 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL2 ((0x0102 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL3 ((0x0103 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL4 ((0x0104 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL5 ((0x0105 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL6 ((0x0106 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_STAT0 ((0x0107 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_STAT1 ((0x0108 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_STAT2 ((0x0109 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_MUTE_VAL ((0x010a << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_CTRL0 ((0x0110 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_CTRL1 ((0x0111 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_CTRL2 ((0x0112 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_CTRL3 ((0x0113 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_COEF0 ((0x0114 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_COEF1 ((0x0115 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_COEF2 ((0x0116 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_COEF3 ((0x0117 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_COEF4 ((0x0118 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_STATUS1 ((0x0119 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_STAT ((0x0120 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_GAIN0 ((0x0121 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_GAIN1 ((0x0122 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CTRL0 ((0x0123 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CTRL1 ((0x0124 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_PREAMB ((0x0125 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_SWAP ((0x0126 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS0 ((0x0127 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS1 ((0x0128 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS2 ((0x0129 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS3 ((0x012a << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS4 ((0x012b << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS5 ((0x012c << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS6 ((0x012d << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS7 ((0x012e << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS8 ((0x012f << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS9 ((0x0130 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTSA ((0x0131 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTSB ((0x0132 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_MUTE_VAL ((0x0133 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_CTRL0 ((0x0140 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_CTRL1 ((0x0141 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_SWAP0 ((0x0142 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK0 ((0x0143 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK1 ((0x0144 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK2 ((0x0145 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK3 ((0x0146 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_STAT ((0x0147 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_GAIN0 ((0x0148 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_GAIN1 ((0x0149 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE_VAL ((0x014a << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE0 ((0x014b << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE1 ((0x014c << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE2 ((0x014d << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE3 ((0x014e << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK_VAL ((0x014f << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_CTRL0 ((0x0150 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_CTRL1 ((0x0151 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_SWAP0 ((0x0152 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK0 ((0x0153 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK1 ((0x0154 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK2 ((0x0155 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK3 ((0x0156 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_STAT ((0x0157 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_GAIN0 ((0x0158 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_GAIN1 ((0x0159 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE_VAL ((0x015a << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE0 ((0x015b << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE1 ((0x015c << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE2 ((0x015d << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE3 ((0x015e << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK_VAL ((0x015f << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_CTRL0 ((0x0160 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_CTRL1 ((0x0161 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_SWAP0 ((0x0162 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK0 ((0x0163 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK1 ((0x0164 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK2 ((0x0165 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK3 ((0x0166 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_STAT ((0x0167 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_GAIN0 ((0x0168 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_GAIN1 ((0x0169 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE_VAL ((0x016a << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE0 ((0x016b << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE1 ((0x016c << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE2 ((0x016d << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE3 ((0x016e << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK_VAL ((0x016f << 2) + 0xfe050000)
+//`define EE_AUDIO_POW_DET_CTRL0 10'h180
+//`define EE_AUDIO_POW_DET_CTRL1 10'h181
+//`define EE_AUDIO_POW_DET_TH_HI 10'h182
+//`define EE_AUDIO_POW_DET_TH_LO 10'h183
+//`define EE_AUDIO_POW_DET_VALUE 10'h184
+#define EE_AUDIO_SECURITY_CTRL0 ((0x0190 << 2) + 0xfe050000)
+#define EE_AUDIO_SECURITY_CTRL1 ((0x0191 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_STAT ((0x01a0 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN0 ((0x01a1 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN1 ((0x01a2 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CTRL0 ((0x01a3 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CTRL1 ((0x01a4 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_PREAMB ((0x01a5 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_SWAP ((0x01a6 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS0 ((0x01a7 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS1 ((0x01a8 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS2 ((0x01a9 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS3 ((0x01aa << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS4 ((0x01ab << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS5 ((0x01ac << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS6 ((0x01ad << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS7 ((0x01ae << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS8 ((0x01af << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS9 ((0x01b0 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTSA ((0x01b1 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTSB ((0x01b2 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_MUTE_VAL ((0x01b3 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_CTRL0 ((0x01c0 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_CTRL1 ((0x01c1 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_START_ADDR ((0x01c2 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_FINISH_ADDR ((0x01c3 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_INT_ADDR ((0x01c4 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_STATUS1 ((0x01c5 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_STATUS2 ((0x01c6 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_INIT_ADDR ((0x01c7 << 2) + 0xfe050000)
+#define EE_AUDIO_TOACODEC_CTRL0 ((0x01d0 << 2) + 0xfe050000)
+#define EE_AUDIO_TOHDMITX_CTRL0 ((0x01d1 << 2) + 0xfe050000)
+#define EE_AUDIO_TOVAD_CTRL0 ((0x01d2 << 2) + 0xfe050000)
+#define EE_AUDIO_FRATV_CTRL0 ((0x01d3 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_CTRL0 ((0x01e0 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_CTRL1 ((0x01e1 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_CTRL2 ((0x01e2 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_CTRL3 ((0x01e3 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_COEF0 ((0x01e4 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_COEF1 ((0x01e5 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_COEF2 ((0x01e6 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_COEF3 ((0x01e7 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_COEF4 ((0x01e8 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_STATUS1 ((0x01e9 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_LB_CTRL0 ((0x01f0 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_LB_CTRL1 ((0x01f1 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_LB_CTRL6 ((0x01f6 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_LB_STAT0 ((0x01f7 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_LB_STAT1 ((0x01f8 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_LB_MUTE_VAL ((0x01fa << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_CTRL0 ((0x0200 << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_CTRL1 ((0x0201 << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_CTRL2 ((0x0202 << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_CTRL3 ((0x0203 << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_CTRL4 ((0x0204 << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_CTRL5 ((0x0205 << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_STAT0 ((0x020a << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_STAT1 ((0x020b << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_CTRL0 ((0x0210 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_CTRL1 ((0x0211 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_START_ADDR ((0x0212 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_FINISH_ADDR ((0x0213 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_INT_ADDR ((0x0214 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_STATUS1 ((0x0215 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_STATUS2 ((0x0216 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_START_ADDRB ((0x0217 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_FINISH_ADDRB ((0x0218 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_INIT_ADDR ((0x0219 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_CTRL2 ((0x021a << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_CTRL0 ((0x0220 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_CTRL1 ((0x0221 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_START_ADDR ((0x0222 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_FINISH_ADDR ((0x0223 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_INT_ADDR ((0x0224 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_STATUS1 ((0x0225 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_STATUS2 ((0x0226 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_START_ADDRB ((0x0227 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_FINISH_ADDRB ((0x0228 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_INIT_ADDR ((0x0229 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_CTRL2 ((0x022a << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_CTRL0 ((0x0230 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_CTRL1 ((0x0231 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_CTRL2 ((0x0232 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_CTRL3 ((0x0233 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_DAT_CH_ID0 ((0x0234 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_DAT_CH_ID1 ((0x0235 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_DAT_CH_ID2 ((0x0236 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_DAT_CH_ID3 ((0x0237 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_LB_CH_ID0 ((0x0238 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_LB_CH_ID1 ((0x0239 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_LB_CH_ID2 ((0x023a << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_LB_CH_ID3 ((0x023b << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_STS ((0x023c << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_CTRL0 ((0x0240 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_CTRL1 ((0x0241 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_START_ADDR ((0x0242 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_FINISH_ADDR ((0x0243 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_INT_ADDR ((0x0244 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_STATUS1 ((0x0245 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_STATUS2 ((0x0246 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_START_ADDRB ((0x0247 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_FINISH_ADDRB ((0x0248 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_INIT_ADDR ((0x0249 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_CTRL2 ((0x024a << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_CTRL0 ((0x0250 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_CTRL1 ((0x0251 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_START_ADDR ((0x0252 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_FINISH_ADDR ((0x0253 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_INT_ADDR ((0x0254 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_STATUS1 ((0x0255 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_STATUS2 ((0x0256 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_START_ADDRB ((0x0257 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_FINISH_ADDRB ((0x0258 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_INIT_ADDR ((0x0259 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_CTRL2 ((0x025a << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_SWAP1 ((0x0260 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK4 ((0x0261 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK5 ((0x0262 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK6 ((0x0263 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK7 ((0x0264 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE4 ((0x0265 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE5 ((0x0266 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE6 ((0x0267 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE7 ((0x0268 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_SWAP1 ((0x0270 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK4 ((0x0271 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK5 ((0x0272 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK6 ((0x0273 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK7 ((0x0274 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE4 ((0x0275 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE5 ((0x0276 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE6 ((0x0277 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE7 ((0x0278 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_SWAP1 ((0x0280 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK4 ((0x0281 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK5 ((0x0282 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK6 ((0x0283 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK7 ((0x0284 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE4 ((0x0285 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE5 ((0x0286 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE6 ((0x0287 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE7 ((0x0288 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_SWAP1 ((0x0290 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK4 ((0x0291 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK5 ((0x0292 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK6 ((0x0293 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK7 ((0x0294 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE4 ((0x0295 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE5 ((0x0296 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE6 ((0x0297 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE7 ((0x0298 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_CTRL2 ((0x02a0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_SWAP1 ((0x02a1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_GAIN2 ((0x02a2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_GAIN3 ((0x02a3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK4 ((0x02a4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK5 ((0x02a5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK6 ((0x02a6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK7 ((0x02a7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE4 ((0x02a8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE5 ((0x02a9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE6 ((0x02aa << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE7 ((0x02ab << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_CTRL2 ((0x02b0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_SWAP1 ((0x02b1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_GAIN2 ((0x02b2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_GAIN3 ((0x02b3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK4 ((0x02b4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK5 ((0x02b5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK6 ((0x02b6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK7 ((0x02b7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE4 ((0x02b8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE5 ((0x02b9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE6 ((0x02ba << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE7 ((0x02bb << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_CTRL2 ((0x02c0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_SWAP1 ((0x02c1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_GAIN2 ((0x02c2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_GAIN3 ((0x02c3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK4 ((0x02c4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK5 ((0x02c5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK6 ((0x02c6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK7 ((0x02c7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE4 ((0x02c8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE5 ((0x02c9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE6 ((0x02ca << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE7 ((0x02cb << 2) + 0xfe050000)
+//========================================================================
+// PDM - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051000
+// -----------------------------------------------
+#define PDM_CTRL ((0x0000 << 2) + 0xfe051000)
+ //bit 31: PDM enable.
+ //bit 30: invert the PDM_DCLK.
+ //bit 29: output mode: 1: 24bits. 0: 32 bits.
+ //bit 28: bypass mode. 1: bypass all filter. directly output the PDM input to DDR. 0: normal mode.
+ //bit 27~9: not used.
+ //bit 16:. PDM Asynchronous FIFO soft reset. write 1 to soft reset AFIFO.
+ //bit 15:8 PDM channel reset. 0: to reset each PDM channel. 1: normal mode.
+ //bit 7:0. PDM channel enable. each bit for one channel.
+#define PDM_HCIC_CTRL1 ((0x0001 << 2) + 0xfe051000)
+ //bit 31 hcic filter enable. 1 use sinc filter. 0 bypass input to output.
+ //bit 29:24. hcic final gain shift parameter.
+ //bit 23:16 hcic final gain multiplier.
+ //bit 8:4 hcic down sample rate.
+ //bit 3:0 hcic stage number. must be between 3 to 9.
+#define PDM_HCIC_CTRL2 ((0x0002 << 2) + 0xfe051000)
+ //Not used.
+#define PDM_F1_CTRL ((0x0003 << 2) + 0xfe051000)
+ //bit 31 . filter 1 enable.
+ //bit 16:15. f1 round mode. 2'b00 : sign bit at bit 49. 28bits output [49:22] round at bit 21. 32bits output [49:18]. 24bits output [49:26]
+ // 2'b01 : sign bit at bit 50. 28bits output [50:23] round at bit 22. 32bits output [49:18]. 24bits output [49:26]
+ // 2'b10 : sign bit at bit 51. 28bits output [51:24] round at bit 23 32bits output [49:18]. 24bits output [49:26].
+ //bit 15:12. filter 1 down sample rate.
+ //bit 8:0. filter 1 stage number.
+#define PDM_F2_CTRL ((0x0004 << 2) + 0xfe051000)
+ //bit 31 . filter 2 enable.
+ //bit 16:15. f2 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23.
+ //bit 15:12. filter 2 down sample rate.
+ //bit 8:0. filter 2 stage number.
+#define PDM_F3_CTRL ((0x0005 << 2) + 0xfe051000)
+ //bit 31 . filter 3 enable.
+ //bit 16:15. f3 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23.
+ //bit 15:12. filter 3 down sample rate.
+ //bit 8:0. filter 3 stage number.
+#define PDM_HPF_CTRL ((0x0006 << 2) + 0xfe051000)
+ //bit 31 High pass filter enable.
+ //bit 20:16 high pass filter shift steps. 6~19 steps.
+ //bit 15:0 high pass filter output factor.
+#define PDM_CHAN_CTRL ((0x0007 << 2) + 0xfe051000)
+ //bit 31:24. chan3 data sample pointer vs edge of the PDM_DCLK.
+ //bit 23:16 chan2 data sample pointer vs edge of the PDM_DCLK.
+ //bit 15:8. chan1 data sample pointer vs edge of the PDM_DCLK.
+ //bit 7:0 chan0 data sample pointer vs edge of the PDM_DCLK.
+#define PDM_CHAN_CTRL1 ((0x0008 << 2) + 0xfe051000)
+ //bit 31:24. chan7 data sample pointer vs edge of the PDM_DCLK.
+ //bit 23:16 chan6 data sample pointer vs edge of the PDM_DCLK.
+ //bit 15:8. chan5 data sample pointer vs edge of the PDM_DCLK.
+ //bit 7:0 chan4 data sample pointer vs edge of the PDM_DCLK.
+#define PDM_COEFF_ADDR ((0x0009 << 2) + 0xfe051000)
+ // address of the write/read of coeff data.
+#define PDM_COEFF_DATA ((0x000a << 2) + 0xfe051000)
+ //write/read data to coeff memory.
+#define PDM_CLKG_CTRL ((0x000b << 2) + 0xfe051000)
+ // auto clock gating control. 1: disable the clock gating function. the clock will awlays enabled. 0 : use RTL auto clock gating.
+ //31:7 not used.
+ //bit 6 filt_ctrl module auto clock gating control.
+ //bit 5 sinc fifo module auto clock gating control.
+ //bit 4 filter module auto clock gating control.
+ //bit 3 apb module auto clock gating control.
+ //bit 2 coeff memory module auto clock gating control.
+ //bit 1 each channel module auto clock gating control.
+ //bit 0 cts_pdm_clk auto clock gating control.
+#define PDM_STS ((0x000c << 2) + 0xfe051000)
+//bit 1 HPF filter output overflow. means the PCLK is too slow.
+//bit 0 HCIC filter output overflow. means the CTS_PDM_CLK is too slow. can't finished the filter function.
+#define PDM_MUTE_VALUE ((0x000d << 2) + 0xfe051000)
+#define PDM_MASK_NUM ((0x000e << 2) + 0xfe051000)
+//========================================================================
+// EQ DRC - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe052000
+// -----------------------------------------------
+#define AED_COEF_RAM_CNTL ((0x0000 << 2) + 0xfe052000)
+#define AED_COEF_RAM_DATA ((0x0001 << 2) + 0xfe052000)
+#define AED_EQ_EN ((0x0002 << 2) + 0xfe052000)
+#define AED_EQ_TAP_CNTL ((0x0003 << 2) + 0xfe052000)
+#define AED_EQ_VOLUME ((0x0004 << 2) + 0xfe052000)
+#define AED_EQ_VOLUME_SLEW_CNT ((0x0005 << 2) + 0xfe052000)
+#define AED_MUTE ((0x0006 << 2) + 0xfe052000)
+#define AED_DRC_CNTL ((0x0007 << 2) + 0xfe052000)
+#define AED_DRC_RMS_COEF0 ((0x0008 << 2) + 0xfe052000)
+#define AED_DRC_RMS_COEF1 ((0x0009 << 2) + 0xfe052000)
+#define AED_DRC_THD0 ((0x000a << 2) + 0xfe052000)
+#define AED_DRC_THD1 ((0x000b << 2) + 0xfe052000)
+#define AED_DRC_THD2 ((0x000c << 2) + 0xfe052000)
+#define AED_DRC_THD3 ((0x000d << 2) + 0xfe052000)
+#define AED_DRC_THD4 ((0x000e << 2) + 0xfe052000)
+#define AED_DRC_K0 ((0x000f << 2) + 0xfe052000)
+#define AED_DRC_K1 ((0x0010 << 2) + 0xfe052000)
+#define AED_DRC_K2 ((0x0011 << 2) + 0xfe052000)
+#define AED_DRC_K3 ((0x0012 << 2) + 0xfe052000)
+#define AED_DRC_K4 ((0x0013 << 2) + 0xfe052000)
+#define AED_DRC_K5 ((0x0014 << 2) + 0xfe052000)
+#define AED_DRC_THD_OUT0 ((0x0015 << 2) + 0xfe052000)
+#define AED_DRC_THD_OUT1 ((0x0016 << 2) + 0xfe052000)
+#define AED_DRC_THD_OUT2 ((0x0017 << 2) + 0xfe052000)
+#define AED_DRC_THD_OUT3 ((0x0018 << 2) + 0xfe052000)
+#define AED_DRC_OFFSET ((0x0019 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF00 ((0x001a << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF01 ((0x001b << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF10 ((0x001c << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF11 ((0x001d << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF20 ((0x001e << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF21 ((0x001f << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF30 ((0x0020 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF31 ((0x0021 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF40 ((0x0022 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF41 ((0x0023 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF50 ((0x0024 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF51 ((0x0025 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF00 ((0x0026 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF01 ((0x0027 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF10 ((0x0028 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF11 ((0x0029 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF20 ((0x002a << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF21 ((0x002b << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF30 ((0x002c << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF31 ((0x002d << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF40 ((0x002e << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF41 ((0x002f << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF50 ((0x0030 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF51 ((0x0031 << 2) + 0xfe052000)
+#define AED_DRC_LOOPBACK_CNTL ((0x0032 << 2) + 0xfe052000)
+#define AED_MDRC_CNTL ((0x0033 << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF00 ((0x0034 << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF01 ((0x0035 << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF00 ((0x0036 << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF01 ((0x0037 << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF00 ((0x0038 << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF01 ((0x0039 << 2) + 0xfe052000)
+#define AED_MDRC_THD0 ((0x003a << 2) + 0xfe052000)
+#define AED_MDRC_K0 ((0x003b << 2) + 0xfe052000)
+#define AED_MDRC_LOW_GAIN ((0x003c << 2) + 0xfe052000)
+#define AED_MDRC_OFFSET0 ((0x003d << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF10 ((0x003e << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF11 ((0x003f << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF10 ((0x0040 << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF11 ((0x0041 << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF10 ((0x0042 << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF11 ((0x0043 << 2) + 0xfe052000)
+#define AED_MDRC_THD1 ((0x0044 << 2) + 0xfe052000)
+#define AED_MDRC_K1 ((0x0045 << 2) + 0xfe052000)
+#define AED_MDRC_OFFSET1 ((0x0046 << 2) + 0xfe052000)
+#define AED_MDRC_MID_GAIN ((0x0047 << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF20 ((0x0048 << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF21 ((0x0049 << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF20 ((0x004a << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF21 ((0x004b << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF20 ((0x004c << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF21 ((0x004d << 2) + 0xfe052000)
+#define AED_MDRC_THD2 ((0x004e << 2) + 0xfe052000)
+#define AED_MDRC_K2 ((0x004f << 2) + 0xfe052000)
+#define AED_MDRC_OFFSET2 ((0x0050 << 2) + 0xfe052000)
+#define AED_MDRC_HIGH_GAIN ((0x0051 << 2) + 0xfe052000)
+#define AED_ED_CNTL ((0x0052 << 2) + 0xfe052000)
+#define AED_DC_EN ((0x0053 << 2) + 0xfe052000)
+#define AED_ND_LOW_THD ((0x0054 << 2) + 0xfe052000)
+#define AED_ND_HIGH_THD ((0x0055 << 2) + 0xfe052000)
+#define AED_ND_CNT_THD ((0x0056 << 2) + 0xfe052000)
+#define AED_ND_SUM_NUM ((0x0057 << 2) + 0xfe052000)
+#define AED_ND_CZ_NUM ((0x0058 << 2) + 0xfe052000)
+#define AED_ND_SUM_THD0 ((0x0059 << 2) + 0xfe052000)
+#define AED_ND_SUM_THD1 ((0x005a << 2) + 0xfe052000)
+#define AED_ND_CZ_THD0 ((0x005b << 2) + 0xfe052000)
+#define AED_ND_CZ_THD1 ((0x005c << 2) + 0xfe052000)
+#define AED_ND_COND_CNTL ((0x005d << 2) + 0xfe052000)
+#define AED_ND_RELEASE_COEF0 ((0x005e << 2) + 0xfe052000)
+#define AED_ND_RELEASE_COEF1 ((0x005f << 2) + 0xfe052000)
+#define AED_ND_ATTACK_COEF0 ((0x0060 << 2) + 0xfe052000)
+#define AED_ND_ATTACK_COEF1 ((0x0061 << 2) + 0xfe052000)
+#define AED_ND_CNTL ((0x0062 << 2) + 0xfe052000)
+#define AED_MIX0_LL ((0x0063 << 2) + 0xfe052000)
+#define AED_MIX0_RL ((0x0064 << 2) + 0xfe052000)
+#define AED_MIX0_LR ((0x0065 << 2) + 0xfe052000)
+#define AED_MIX0_RR ((0x0066 << 2) + 0xfe052000)
+#define AED_CLIP_THD ((0x0067 << 2) + 0xfe052000)
+#define AED_CH1_ND_SUM_OUT ((0x0068 << 2) + 0xfe052000)
+#define AED_CH2_ND_SUM_OUT ((0x0069 << 2) + 0xfe052000)
+#define AED_CH1_ND_CZ_OUT ((0x006a << 2) + 0xfe052000)
+#define AED_CH2_ND_CZ_OUT ((0x006b << 2) + 0xfe052000)
+#define AED_NOISE_STATUS ((0x006c << 2) + 0xfe052000)
+#define AED_POW_CURRENT_S0 ((0x006d << 2) + 0xfe052000)
+#define AED_POW_CURRENT_S1 ((0x006e << 2) + 0xfe052000)
+#define AED_POW_CURRENT_S2 ((0x006f << 2) + 0xfe052000)
+#define AED_POW_OUT0 ((0x0070 << 2) + 0xfe052000)
+#define AED_POW_OUT1 ((0x0071 << 2) + 0xfe052000)
+#define AED_POW_OUT2 ((0x0072 << 2) + 0xfe052000)
+#define AED_POW_ADJ_INDEX0 ((0x0073 << 2) + 0xfe052000)
+#define AED_POW_ADJ_INDEX1 ((0x0074 << 2) + 0xfe052000)
+#define AED_POW_ADJ_INDEX2 ((0x0075 << 2) + 0xfe052000)
+#define AED_DRC_GAIN_INDEX0 ((0x0076 << 2) + 0xfe052000)
+#define AED_DRC_GAIN_INDEX1 ((0x0077 << 2) + 0xfe052000)
+#define AED_DRC_GAIN_INDEX2 ((0x0078 << 2) + 0xfe052000)
+#define AED_CH1_VOLUME_STATE ((0x0079 << 2) + 0xfe052000)
+#define AED_CH2_VOLUME_STATE ((0x007a << 2) + 0xfe052000)
+#define AED_CH1_VOLUME_GAIN ((0x007b << 2) + 0xfe052000)
+#define AED_CH2_VOLUME_GAIN ((0x007c << 2) + 0xfe052000)
+#define AED_FULL_POW_CURRENT ((0x007d << 2) + 0xfe052000)
+#define AED_FULL_POW_OUT ((0x007e << 2) + 0xfe052000)
+#define AED_FULL_POW_ADJ ((0x007f << 2) + 0xfe052000)
+#define AED_FULL_DRC_GAIN ((0x0080 << 2) + 0xfe052000)
+#define AED_MASTER_VOLUME_STATE ((0x0081 << 2) + 0xfe052000)
+#define AED_MASTER_VOLUME_GAIN ((0x0082 << 2) + 0xfe052000)
+#define AED_TOP_CTL0 ((0x0083 << 2) + 0xfe052000)
+#define AED_TOP_CTL1 ((0x0084 << 2) + 0xfe052000)
+#define AED_TOP_CTL2 ((0x0085 << 2) + 0xfe052000)
+//========================================================================
+// AUDIO locker - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051400
+// -----------------------------------------------
+#define AUD_LOCK_EN ((0x0000 << 2) + 0xfe051400)
+#define AUD_LOCK_SW_RESET ((0x0001 << 2) + 0xfe051400)
+#define AUD_LOCK_SW_LATCH ((0x0002 << 2) + 0xfe051400)
+#define AUD_LOCK_HW_LATCH ((0x0003 << 2) + 0xfe051400)
+#define AUD_LOCK_REFCLK_SRC ((0x0004 << 2) + 0xfe051400)
+#define AUD_LOCK_REFCLK_LAT_INT ((0x0005 << 2) + 0xfe051400)
+#define AUD_LOCK_IMCLK_LAT_INT ((0x0006 << 2) + 0xfe051400)
+#define AUD_LOCK_OMCLK_LAT_INT ((0x0007 << 2) + 0xfe051400)
+#define AUD_LOCK_REFCLK_DS_INT ((0x0008 << 2) + 0xfe051400)
+#define AUD_LOCK_IMCLK_DS_INT ((0x0009 << 2) + 0xfe051400)
+#define AUD_LOCK_OMCLK_DS_INT ((0x000a << 2) + 0xfe051400)
+#define AUD_LOCK_INT_CLR ((0x000b << 2) + 0xfe051400)
+#define AUD_LOCK_GCLK_CTRL ((0x000c << 2) + 0xfe051400)
+#define AUD_LOCK_INT_CTRL ((0x000d << 2) + 0xfe051400)
+#define RO_REF2IMCLK_CNT_L ((0x0010 << 2) + 0xfe051400)
+#define RO_REF2IMCLK_CNT_H ((0x0011 << 2) + 0xfe051400)
+#define RO_REF2OMCLK_CNT_L ((0x0012 << 2) + 0xfe051400)
+#define RO_REF2OMCLK_CNT_H ((0x0013 << 2) + 0xfe051400)
+#define RO_IMCLK2REF_CNT_L ((0x0014 << 2) + 0xfe051400)
+#define RO_IMCLK2REF_CNT_H ((0x0015 << 2) + 0xfe051400)
+#define RO_OMCLK2REF_CNT_L ((0x0016 << 2) + 0xfe051400)
+#define RO_OMCLK2REF_CNT_H ((0x0017 << 2) + 0xfe051400)
+#define RO_REFCLK_PKG_CNT ((0x0018 << 2) + 0xfe051400)
+#define RO_IMCLK_PKG_CNT ((0x0019 << 2) + 0xfe051400)
+#define RO_OMCLK_PKG_CNT ((0x001a << 2) + 0xfe051400)
+#define RO_AUD_LOCK_INT_STATUS ((0x001b << 2) + 0xfe051400)
+//========================================================================
+// AUDIO VAD - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051800
+// -----------------------------------------------
+//
+// Reading file: VAD_REG.h
+//
+#define VAD_TOP_CTRL0 ((0x0000 << 2) + 0xfe051800)
+#define VAD_TOP_CTRL1 ((0x0001 << 2) + 0xfe051800)
+#define VAD_TOP_CTRL2 ((0x0002 << 2) + 0xfe051800)
+#define VAD_FIR_CTRL ((0x0003 << 2) + 0xfe051800)
+#define VAD_FIR_EMP ((0x0004 << 2) + 0xfe051800)
+#define VAD_FIR_COEF0 ((0x0005 << 2) + 0xfe051800)
+#define VAD_FIR_COEF1 ((0x0006 << 2) + 0xfe051800)
+#define VAD_FIR_COEF2 ((0x0007 << 2) + 0xfe051800)
+#define VAD_FIR_COEF3 ((0x0008 << 2) + 0xfe051800)
+#define VAD_FIR_COEF4 ((0x0009 << 2) + 0xfe051800)
+#define VAD_FIR_COEF5 ((0x000a << 2) + 0xfe051800)
+#define VAD_FIR_COEF6 ((0x000b << 2) + 0xfe051800)
+#define VAD_FIR_COEF7 ((0x000c << 2) + 0xfe051800)
+#define VAD_FIR_COEF8 ((0x000d << 2) + 0xfe051800)
+#define VAD_FIR_COEF9 ((0x000e << 2) + 0xfe051800)
+#define VAD_FIR_COEF10 ((0x000f << 2) + 0xfe051800)
+#define VAD_FIR_COEF11 ((0x0010 << 2) + 0xfe051800)
+#define VAD_FIR_COEF12 ((0x0011 << 2) + 0xfe051800)
+#define VAD_FRAME_CTRL0 ((0x0012 << 2) + 0xfe051800)
+#define VAD_FRAME_CTRL1 ((0x0013 << 2) + 0xfe051800)
+#define VAD_FRAME_CTRL2 ((0x0014 << 2) + 0xfe051800)
+#define VAD_CEP_CTRL0 ((0x0015 << 2) + 0xfe051800)
+#define VAD_CEP_CTRL1 ((0x0016 << 2) + 0xfe051800)
+#define VAD_CEP_CTRL2 ((0x0017 << 2) + 0xfe051800)
+#define VAD_CEP_CTRL3 ((0x0018 << 2) + 0xfe051800)
+#define VAD_CEP_CTRL4 ((0x0019 << 2) + 0xfe051800)
+#define VAD_CEP_CTRL5 ((0x001a << 2) + 0xfe051800)
+#define VAD_DEC_CTRL ((0x001b << 2) + 0xfe051800)
+#define VAD_TOP_STS0 ((0x001c << 2) + 0xfe051800)
+#define VAD_TOP_STS1 ((0x001d << 2) + 0xfe051800)
+#define VAD_TOP_STS2 ((0x001e << 2) + 0xfe051800)
+#define VAD_FIR_STS0 ((0x001f << 2) + 0xfe051800)
+#define VAD_FIR_STS1 ((0x0020 << 2) + 0xfe051800)
+#define VAD_POW_STS0 ((0x0021 << 2) + 0xfe051800)
+#define VAD_POW_STS1 ((0x0022 << 2) + 0xfe051800)
+#define VAD_POW_STS2 ((0x0023 << 2) + 0xfe051800)
+#define VAD_FFT_STS0 ((0x0024 << 2) + 0xfe051800)
+#define VAD_FFT_STS1 ((0x0025 << 2) + 0xfe051800)
+#define VAD_SPE_STS0 ((0x0026 << 2) + 0xfe051800)
+#define VAD_SPE_STS1 ((0x0027 << 2) + 0xfe051800)
+#define VAD_SPE_STS2 ((0x0028 << 2) + 0xfe051800)
+#define VAD_SPE_STS3 ((0x0029 << 2) + 0xfe051800)
+#define VAD_DEC_STS0 ((0x002a << 2) + 0xfe051800)
+#define VAD_DEC_STS1 ((0x002b << 2) + 0xfe051800)
+#define VAD_LUT_CTRL ((0x002c << 2) + 0xfe051800)
+#define VAD_LUT_WR ((0x002d << 2) + 0xfe051800)
+#define VAD_LUT_RD ((0x002e << 2) + 0xfe051800)
+#define VAD_IN_SEL0 ((0x002f << 2) + 0xfe051800)
+#define VAD_IN_SEL1 ((0x0030 << 2) + 0xfe051800)
+#define VAD_TO_DDR ((0x0031 << 2) + 0xfe051800)
+//
+// Closing file: VAD_REG.h
+//
+//========================================================================
+// AUDIO RESAMPLEA - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051c00
+// -----------------------------------------------
+//
+// Reading file: RESAMPLE.h
+//
+#define AUDIO_RSAMP_CTRL0 ((0x0000 << 2) + 0xfe051c00)
+//Bit 31:3 reserved
+//Bit 2 reg_lock_rst //unsigned , default =0;
+//Bit 1 reg_rsamp_rst //unsigned , default =0;
+//Bit 0 reg_sw_rst //unsigned , default =0;
+#define AUDIO_RSAMP_CTRL1 ((0x0001 << 2) + 0xfe051c00)
+//Bit 31:26 reserved //unsigned , default =0;
+//Bit 25 reg_rsamp_rst_sel //unsigned , default =0;
+//Bit 24 reg_module_bypas //unsigned , default =0;
+//Bit 23:18 reg_gclk_ctrl //unsigned , default =0;
+//Bit 17:13 reg_in_msb //unsigned , default =23;
+//Bit 12 reg_output_en //unsigned , default =0;
+//Bit 11 reg_rsamp_en //unsigned , default =0;
+//Bit 10 reg_filt_en //unsigned , default =0;
+//Bit 9 reg_post_en //unsigned , default =0;
+//Bit 8 reg_inp_mux_mode //unsigned , default =0;
+//Bit 7:4 reserved //unsigned , default =2;
+//Bit 3:0 reg_inp_mux //unsigned , default =0;
+#define AUDIO_RSAMP_CTRL2 ((0x0002 << 2) + 0xfe051c00)
+//Bit 31:30 reserved //unsigned , default =0;
+//Bit 29:24 reg_chx_size //unsigned , default =2;
+//Bit 23:18 reserved //unsigned , default =0;
+//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4
+//Bit 15:8 reg_filt_tap //unsigned , default =63;
+//Bit 7:0 reg_intp_tap //unsigned , default =63;
+#define AUDIO_RSAMP_PHSINIT ((0x0003 << 2) + 0xfe051c00)
+//Bit 31:28 reserved //unsigned , default = 0;
+//Bit 27:0 reg_init_phs //unsigned , default = 0;
+#define AUDIO_RSAMP_PHSSTEP ((0x0004 << 2) + 0xfe051c00)
+//Bit 31 reserved //unsigned , default = 0;
+//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000
+#define AUDIO_RSAMP_SHIFT ((0x0005 << 2) + 0xfe051c00)
+//Bit 31:24 reg_rsft_iir //unsigned , default = 23;
+//Bit 23:16 reg_rsft_blnd //unsigned , default = 21;
+//Bit 15:8 reg_rsft_sinc //unsigned , default = 31;
+//Bit 7:0 reg_rsft_aa //unsigned , default = 31;
+#define AUDIO_RSAMP_ADJ_CTRL0 ((0x0006 << 2) + 0xfe051c00)
+//Bit 31:3 reserved //unsigned
+//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0;
+//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0;
+//Bit 0 reg_rsamp_adj_en //unsigned , default = 0;
+#define AUDIO_RSAMP_ADJ_CTRL1 ((0x0007 << 2) + 0xfe051c00)
+//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8;
+//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768;
+#define AUDIO_RSAMP_ADJ_SFT ((0x0008 << 2) + 0xfe051c00)
+//Bit 31:30 reserved //unsigned , default = 0;
+//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0;
+//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9;
+//Bit 23:21 reserved //unsigned , default = 0;
+//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1;
+//Bit 15:13 reserved //unsigned , default = 0;
+//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6;
+//Bit 7:6 reserved //unsigned , default = 0;
+//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12;
+#define AUDIO_RSAMP_ADJ_IDET_LEN ((0x0009 << 2) + 0xfe051c00)
+//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000;
+#define AUDIO_RSAMP_ADJ_FORCE ((0x000a << 2) + 0xfe051c00)
+//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8;
+#define AUDIO_RSAMP_ADJ_KI_FORCE ((0x000b << 2) + 0xfe051c00)
+//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0;
+#define AUDIO_RSAMP_RO_STATUS ((0x0010 << 2) + 0xfe051c00)
+//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]}
+#define AUDIO_RSAMP_RO_ADJ_FREQ ((0x0011 << 2) + 0xfe051c00)
+//Bit 31:0 ro_rsamp_adj_freq
+#define AUDIO_RSAMP_RO_ADJ_DIFF_BAK ((0x0012 << 2) + 0xfe051c00)
+//Bit 31:0 ro_det_diff_bak
+#define AUDIO_RSAMP_RO_ADJ_DIFF_DLT ((0x0013 << 2) + 0xfe051c00)
+//Bit 31:0 ro_det_diff_dlt
+#define AUDIO_RSAMP_RO_ADJ_PHS_ERR ((0x0014 << 2) + 0xfe051c00)
+//Bit 31:0 ro_det_phase_err
+#define AUDIO_RSAMP_RO_ADJ_KI_OUT ((0x0015 << 2) + 0xfe051c00)
+//Bit 31:0 ro_rsamp_ki_out
+#define AUDIO_RSAMP_RO_IN_CNT ((0x0016 << 2) + 0xfe051c00)
+//Bit 31:0 ro_rsamp_in_cnt
+#define AUDIO_RSAMP_RO_OUT_CNT ((0x0017 << 2) + 0xfe051c00)
+//Bit 31:0 ro_rsamp_out_cnt
+#define AUDIO_RSAMP_RO_ADJ_PHS_ERR_VAR ((0x0018 << 2) + 0xfe051c00)
+//Bit 31:0 ro_det_phase_err_var
+#define AUDIO_RSAMP_POST_COEF0 ((0x0020 << 2) + 0xfe051c00)
+//Bit 31:0 reg_post_coef0 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF1 ((0x0021 << 2) + 0xfe051c00)
+//Bit 31:0 reg_post_coef1 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF2 ((0x0022 << 2) + 0xfe051c00)
+//Bit 31:0 reg_post_coef2 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF3 ((0x0023 << 2) + 0xfe051c00)
+//Bit 31:0 reg_post_coef3 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF4 ((0x0024 << 2) + 0xfe051c00)
+//Bit 31:0 reg_post_coef4 //signed , default = 0;
+#define AUDIO_RSAMP_AA_COEF_ADDR ((0x0030 << 2) + 0xfe051c00)
+//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0;
+#define AUDIO_RSAMP_AA_COEF_DATA ((0x0031 << 2) + 0xfe051c00)
+//Bit 31:0 reg_aa_coef_data //signed , default = 0;
+#define AUDIO_RSAMP_SINC_COEF_ADDR ((0x0040 << 2) + 0xfe051c00)
+//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0;
+#define AUDIO_RSAMP_SINC_COEF_DATA ((0x0041 << 2) + 0xfe051c00)
+//Bit 31:0 reg_sinc_coef_data //signed , default = 0;
+//
+// Closing file: RESAMPLE.h
+//
+//========================================================================
+// AUDIO TOP_VAD - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe054800
+// -----------------------------------------------
+#define EE_AUDIO2_CLK81_CTRL ((0x0000 << 2) + 0xfe054800)
+#define EE_AUDIO2_CLK81_EN ((0x0001 << 2) + 0xfe054800)
+#define EE_AUDIO2_SW_RESET0 ((0x0002 << 2) + 0xfe054800)
+#define EE_AUDIO2_CLK_GATE_EN0 ((0x0003 << 2) + 0xfe054800)
+#define EE_AUDIO2_SECURITY_CTRL0 ((0x0004 << 2) + 0xfe054800)
+#define EE_AUDIO2_MCLK_VAD_CTRL ((0x0010 << 2) + 0xfe054800)
+#define EE_AUDIO2_VAD_CLK_CTRL ((0x0011 << 2) + 0xfe054800)
+#define EE_AUDIO2_MST_DLY_CTRL0 ((0x0012 << 2) + 0xfe054800)
+#define EE_AUDIO2_MST_VAD_SCLK_CTRL0 ((0x0013 << 2) + 0xfe054800)
+#define EE_AUDIO2_MST_VAD_SCLK_CTRL1 ((0x0014 << 2) + 0xfe054800)
+#define EE_AUDIO2_CLK_TDMIN_VAD_CTRL ((0x0015 << 2) + 0xfe054800)
+#define EE_AUDIO2_CLK_PDMIN_CTRL0 ((0x0016 << 2) + 0xfe054800)
+#define EE_AUDIO2_CLK_PDMIN_CTRL1 ((0x0017 << 2) + 0xfe054800)
+#define EE_AUDIO2_TOVAD_CTRL0 ((0x0020 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_CTRL0 ((0x0030 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_CTRL1 ((0x0031 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_CTRL2 ((0x0032 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_START_ADDR ((0x0033 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_INIT_ADDR ((0x0034 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_FINISH_ADDR ((0x0035 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_START_ADDRB ((0x0036 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_FINISH_ADDRB ((0x0037 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_INT_ADDR ((0x0038 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_STATUS1 ((0x0039 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_STATUS2 ((0x003a << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_CTRL ((0x0040 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_SWAP0 ((0x0041 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_SWAP1 ((0x0042 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE_VAL ((0x0043 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_STAT ((0x0044 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE0 ((0x0050 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE1 ((0x0051 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE2 ((0x0052 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE3 ((0x0053 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE4 ((0x0054 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE5 ((0x0055 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE6 ((0x0056 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE7 ((0x0057 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK0 ((0x0058 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK1 ((0x0059 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK2 ((0x005a << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK3 ((0x005b << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK4 ((0x005c << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK5 ((0x005d << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK6 ((0x005e << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK7 ((0x005f << 2) + 0xfe054800)
+//
+// Closing file: REG_LIST_AUDIO_RTL.h
+//
+//
+// Reading file: ../spifc/rtl/spifc_reg.vh
+//
+//`ifdef SPIFC_REG_DEFINE
+//`else
+//`define SPIFC_REG_DEFINE
+//`define SPIFC BASE ADDR 32'hfe00ac00
+// -----------------------------------------------
+// APB_BASE: APB2_BASE_ADDR = 0xfe00ac00
+// -----------------------------------------------
+//AHB domain regsiter.
+#define SPIFC_AHB_CTRL ((0x0000 << 2) + 0xfe00ac00)
+ //bit 31 AHB BUS enable. 1 enable ahb request. 0: disable ahb request.
+ //bit 30. decerr_en for (AXI->AHB bridge).
+ //bit 29. force_incr. for ( AXI->AHB bridge).
+ //bit 19. critical word first. CWF_EN. 1: enable. 0 : disable.
+ //bit 18:17 RDBUF_SIZE . 00: 64bytes. 01: 32 bytes. 10: 16 bytes. 11: reserved.
+ //bit 16 AHB MASTER enable. if enabled, each master use one dedicated HRDATA buffer inside ahb2api model. total 3 HRDATA buffers inside ahb2spi.
+ //if disabled the 3 HRDATA buffer will random be used for all masters.
+ //bit 14 write 1 to clean the HRDATA buffer 2. read 0 finished clean operation.
+ //bit 13 write 1 to clean the HRDATA buffer 1. read 0 finished clean operation.
+ //bit 12 write 1 to clean the HRDATA buffer 0. read 0 finished clean operation.
+ //bit 11:0. not used.
+#define SPIFC_CLK_CTRL ((0x0001 << 2) + 0xfe00ac00)
+ //bit 14 asynchronous buffer ahb clock disable. 1 = disable. 0 = enable.
+ //bit 13 ahb2spi ahb clock disable. 1 = disable. 0 = enable.
+ //bit 12 ahb_arb ahb clock disable. 1 = disable. 0 = enable.
+ //bit 10 asynchronous buffer ahb clock auto gating enable. 1 = enable. 0 = disable.
+ //bit 9 ahb2spi ahb clock auto gating enable. 1 = enable. 0 = disable.
+ //bit 8 ahbarb ahb clock auto gating enable. 1 = enable. 0 = disable.
+ //bit 2. asynchronous AHB clock domain software reset. 1 = reset. 0 = normal working mode.
+ //bit 1. ahb2spi ahb clock domain software reset. 1 = reset. 0 = normal working mode.
+ //bit 0. not used.
+#define SPIFC_SEC_CTRL ((0x0002 << 2) + 0xfe00ac00)
+ //bit 31. ADDRESS security range enable. 1 = enable; 0: disable.
+ //bit 14. range6 enable: 1: enable; 0 : disable.
+ //bit 13. range5 enable: 1: enable; 0 : disable.
+ //bit 12. range4 enable: 1: enable; 0 : disable.
+ //bit 11. range3 enable: 1: enable; 0 : disable.
+ //bit 10. range2 enable: 1: enable; 0 : disable.
+ //bit 9. range1 enable: 1: enable; 0 : disable.
+ //bit 8. range0 enable: 1: enable; 0 : disable.
+ //bit 7:4 to control spi clock register security. bit 7 = 1, APB bus can access spi clock domain register. bit 7 == 0 : only PPROT[0] == bit 4, the APB can access spic clock domain register.
+ //bit 3:0 to control ahb clock domain register secruity. bit 3 = 1, APB bus can access ahb clock domain register. bit 3 ==0; only PPROT[0] == bit 0, the APB can access ahb clock domain register.
+#define SPIFC_RANGE0_STA ((0x0010 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 0 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE0_EDA ((0x0011 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 0 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE0_CTRL ((0x0012 << 2) + 0xfe00ac00)
+ // AHB secruity range 0 control.
+ //bit 15:8 range 0 access control for DMA access.
+ //bit 15 range 0 access control for DMA thread 7
+ //bit 14 range 0 access control for DMA Thread 6
+ //bit 13 range 0 access control for DMA Thread 5.
+ //bit 12 range 0 access control for DMA Thread 4.
+ // bit 11. range 0 access control for DMA thread 3
+ // bit 10. range 0 access control for DMA Thread 2
+ // bit 9. range 0 access control for DMA Thread 1.
+ // bit 8. range 0 access control for DMA Thread 0.
+ // bit 7. range 0 access control for HMASTER == 7 Not used.
+ // bit 6. range 0 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 0 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 0 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 0 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 0 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 0 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 0 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE1_STA ((0x0013 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 1 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE1_EDA ((0x0014 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 1 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE1_CTRL ((0x0015 << 2) + 0xfe00ac00)
+ // AHB secruity range 1 control.
+ //bit 15:8 range 1 access control for DMA access.
+ //bit 15 range 1 access control for DMA thread 7
+ //bit 14 range 1 access control for DMA Thread 6
+ //bit 13 range 1 access control for DMA Thread 5.
+ //bit 12 range 1 access control for DMA Thread 4.
+ // bit 11. range 1 access control for DMA thread 3
+ // bit 10. range 1 access control for DMA Thread 2
+ // bit 9. range 1 access control for DMA Thread 1.
+ // bit 8. range 1 access control for DMA Thread 0.
+ // bit 7. range 1 access control for HMASTER == 7 Not used.
+ // bit 6. range 1 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 1 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 1 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 1 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 1 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 1 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 1 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE2_STA ((0x0016 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 2 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE2_EDA ((0x0017 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 2 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE2_CTRL ((0x0018 << 2) + 0xfe00ac00)
+ // AHB secruity range 2 control.
+ //bit 15:8 range 2 access control for DMA access.
+ //bit 15 range 2 access control for DMA thread 7
+ //bit 14 range 2 access control for DMA Thread 6
+ //bit 13 range 2 access control for DMA Thread 5.
+ //bit 12 range 2 access control for DMA Thread 4.
+ // bit 11. range 2 access control for DMA thread 3
+ // bit 10. range 2 access control for DMA Thread 2
+ // bit 9. range 2 access control for DMA Thread 1.
+ // bit 8. range 2 access control for DMA Thread 0.
+ // bit 7. range 2 access control for HMASTER == 7 Not used.
+ // bit 6. range 2 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 2 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 2 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 2 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 2 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 2 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 2 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE3_STA ((0x0019 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 3 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE3_EDA ((0x001a << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 3 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE3_CTRL ((0x001b << 2) + 0xfe00ac00)
+ // AHB secruity range 3 control.
+ //bit 15:8 range 3 access control for DMA access.
+ //bit 15 range 3 access control for DMA thread 7
+ //bit 14 range 3 access control for DMA Thread 6
+ //bit 13 range 3 access control for DMA Thread 5.
+ //bit 12 range 3 access control for DMA Thread 4.
+ // bit 11. range 3 access control for DMA thread 3
+ // bit 10. range 3 access control for DMA Thread 2
+ // bit 9. range 3 access control for DMA Thread 1.
+ // bit 8. range 3 access control for DMA Thread 0.
+ // bit 7. range 3 access control for HMASTER == 7 Not used.
+ // bit 6. range 3 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 3 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 3 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 3 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 3 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 3 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 3 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE4_STA ((0x001c << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 4 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE4_EDA ((0x001d << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 4 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE4_CTRL ((0x001e << 2) + 0xfe00ac00)
+ // AHB secruity range 4 control.
+ //bit 15:8 range 4 access control for DMA access.
+ //bit 15 range 4 access control for DMA thread 7
+ //bit 14 range 4 access control for DMA Thread 6
+ //bit 13 range 4 access control for DMA Thread 5.
+ //bit 12 range 4 access control for DMA Thread 4.
+ // bit 11. range 4 access control for DMA thread 3
+ // bit 10. range 4 access control for DMA Thread 2
+ // bit 9. range 4 access control for DMA Thread 1.
+ // bit 8. range 4 access control for DMA Thread 0.
+ // bit 7. range 4 access control for HMASTER == 7 Not used.
+ // bit 6. range 4 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 4 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 4 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 4 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 4 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 4 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 4 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE5_STA ((0x001f << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 5 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE5_EDA ((0x0021 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 5 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE5_CTRL ((0x0020 << 2) + 0xfe00ac00)
+ // AHB secruity range 5 control.
+ //bit 15:8 range 5 access control for DMA access.
+ //bit 15 range 5 access control for DMA thread 7
+ //bit 14 range 5 access control for DMA Thread 6
+ //bit 13 range 5 access control for DMA Thread 5.
+ //bit 12 range 5 access control for DMA Thread 4.
+ // bit 11. range 5 access control for DMA thread 3
+ // bit 10. range 5 access control for DMA Thread 2
+ // bit 9. range 5 access control for DMA Thread 1.
+ // bit 8. range 5 access control for DMA Thread 0.
+ // bit 7. range 5 access control for HMASTER == 7 Not used.
+ // bit 6. range 5 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 5 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 5 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 5 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 5 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 5 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 5 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE6_STA ((0x0022 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 6 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE6_EDA ((0x0023 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 6 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE6_CTRL ((0x0024 << 2) + 0xfe00ac00)
+ // AHB secruity range 6 control.
+ //bit 15:8 range 6 access control for DMA access.
+ //bit 15 range 6 access control for DMA thread 7
+ //bit 14 range 6 access control for DMA Thread 6
+ //bit 13 range 6 access control for DMA Thread 5.
+ //bit 12 range 6 access control for DMA Thread 4.
+ // bit 11. range 6 access control for DMA thread 3
+ // bit 10. range 6 access control for DMA Thread 2
+ // bit 9. range 6 access control for DMA Thread 1.
+ // bit 8. range 6 access control for DMA Thread 0.
+ // bit 7. range 6 access control for HMASTER == 7 Not used.
+ // bit 6. range 6 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 6 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 6 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 6 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 6 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 6 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 6 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE7_CTRL ((0x0025 << 2) + 0xfe00ac00)
+ // AHB secruity range 7( default range) control.
+ //bit 15:8 range 7 access control for DMA access.
+ //bit 15 range 7 access control for DMA thread 7
+ //bit 14 range 7 access control for DMA Thread 6
+ //bit 13 range 7 access control for DMA Thread 5.
+ //bit 12 range 7 access control for DMA Thread 4.
+ // bit 11. range 7 access control for DMA thread 3
+ // bit 10. range 7 access control for DMA Thread 2
+ // bit 9. range 7 access control for DMA Thread 1.
+ // bit 8. range 7 access control for DMA Thread 0.
+ // bit 7. range 7 access control for HMASTER == 7 Not used.
+ // bit 6. range 7 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 7 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 7 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 7 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 7 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 7 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 7 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_AHB_WTCH_CTRL ((0x0026 << 2) + 0xfe00ac00)
+ //bit 15:0. ahb bus watch dog timer. if AHB bus not response, the timer over this number, the SPIFC will send back a error response.
+#define SPIFC_SEC_VIO0 ((0x0027 << 2) + 0xfe00ac00)
+ //bit 31:0 VIO ADDR
+#define SPIFC_SEC_VIO1 ((0x0028 << 2) + 0xfe00ac00)
+ //bit 31. AHB VIO status. write 1 to clear the error info.
+ //bit 6:5 HMASTER.
+ //bit 4:2 HPROT.
+ //bit 1 HNONSEC.
+ //bit 0 HWRITE.
+#define SPIFC_AHB_STS ((0x0029 << 2) + 0xfe00ac00)
+ //bit 31. AHB IDLE. when ahb disabled, to show ahb status. 1, no more ahb request or ahb requent is holded. 0, ahb is still busy.
+ //bit 30. AHB data cycle status, when ahb disabled, to show ahb data cycle status. 1, data cycle is holded, 0 : not in data cycle or data cycle is processing.
+ //bit 29. AHB bus spi requst status. 1: still waiting for spi data. 0: idle.
+ //bit 28:0. not used.
+//SPI cts_spi_clk domain regsiter.
+#define SPIFC_USER_CTRL0 ((0x0080 << 2) + 0xfe00ac00)
+ //bit 31. user request enable. write 1 to enable. read 0, means user command accepted by the SPI_CTRL.
+ //bit 30. user request finish bit. write 0 when enable user request. read 1 means SPI_CTRL finished this user command.
+ //bit 0. user data updated. write 0 when enable user request. 1 means there's datas/status read from SPI flash.
+#define SPIFC_USER_CTRL1 ((0x0081 << 2) + 0xfe00ac00)
+ //bit 31. not used.
+ //bit 30. user command cycle enable. 1) enable. 0) don't send command in usr command period.
+ //bit 29:28. user command mode. 00 = SPI extend mode. 01 : dual mode. 10: quad mode.
+ //bit 27:20. user command code. the code need to send in command period.
+ //bit 19. user address cycle enable.
+ //bit 18:17 user address mode: 00 = SPI extend mode. 01 : dual mode. 10: quad mode.
+ //bit 16:15 user address Byte length 00 = 1 byte. 01 = 2 bytes. 10 = 3 bytes. 11 = 4bytes.
+ //bit 14 user datout enable.
+ //bit 13 user dataout AES enable. 1: dataout through AES describle. 0 : original data.
+ //bit 12 user data output source. 0: from data buffer. 1: from status register.
+ //bit 11:10 user dataout mode: 00 SPI extend model. 01 : dual model. 10. quad mode.
+ //bit 9:0 User data out bytes num.
+#define SPIFC_USER_CTRL2 ((0x0082 << 2) + 0xfe00ac00)
+ //bit 31 usr_dummy_en 1: enable dummy cycles. 0 : no dummy cycles.
+ //bit 30: 29 usr_dummy_mode 2'b00 = SPI extend mode. 01 dual mode. 10 Quad mode.
+ //bit 28:23 user dummy clock cycle number.
+ //bit 19:16. user command input/output direction control. 000000: right after the last output.
+ // 1: after the first cycle of dummy cycle.
+ // .....
+ // 4'hf: right before the datin cycle.
+ //bit 15:8. data on the dummy cycle after the first byte.
+ //bit 7:0 The first bytes data showed on dummy cycle. some flash may need special data for enhance performance mode or XIP mode.
+#define SPIFC_USER_CTRL3 ((0x0083 << 2) + 0xfe00ac00)
+ //bit 31 usr_datin_en 1: datain cycle enabled. 0: no datain cycle.
+ //bit 30: datin_dest. 1: save the input data to STATUS register. 0 save the input data to data buffer.
+ //bit 29: 1: enable datain data AES describle. 0: not use AES.
+ //bit 28:27. datin mode. 2'b00 SPI extend mode. 01: dual mode. 10 Quad mode.
+ //bit 25:16. user data in data bytes. how many bytes of user datain expected.
+#define SPIFC_USER_ADDR ((0x0084 << 2) + 0xfe00ac00)
+ //bit 31:0. 32bits user address.
+#define SPIFC_AHB_REQ_CTRL ((0x0085 << 2) + 0xfe00ac00)
+ //bit 31. AHB request enable.
+ //bit 30 AHB cmd_en. command cycle enable.
+ //bit 29:28. ahb command mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode.
+ //bit 27:20:.AHB command code.
+ //bit 19. ahb request address cycle enable.
+ //bit 18:17 AHB ADDRESS mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode.
+ //bit 16:15 AHB ADDRESS data width. 2'b00: 1byte. 2'b01 : 2bytes. 2'b10: 3bytes. 2'b11 4bytes.
+ //bit 13:10 AHB request spi bus input switch time. 0 : after address cycle. 1: the frist dummy cycles. ... 0xf. after dummy cycle.
+ //bit 9:8 AHB DATAIN mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode.
+ //bit 7 DATA IN AES enable. 1: enable 0: disable.
+ //bit 1:0 AHB REQ DATA size. 2'b00: 64bytes. 2'b01: 32 bytes. 2'b10 : 16 bytes. 2'b11: reserved. this bit settign should be same as RDBUF_SIZE setting.
+#define SPIFC_AHB_REQ_CTRL1 ((0x0086 << 2) + 0xfe00ac00)
+ //bit 31. ahb Dummy enable.
+ //bit 30:29. ahb dummy mode.
+ //bit 28:23. ahb request dummy clock cycles.
+ //bit 15:0. ahb dummy period output data.
+#define SPIFC_AHB_REQ_CTRL2 ((0x0087 << 2) + 0xfe00ac00)
+ //bit 1:0 AHB address position. this settign depend on SPIFC_AHB_CTRL register CWF_EN bit and RDBUF_SIZE.
+ // if CWF_EN is enabled. these bit should be set to 2'b10 (16BYTE boundary).
+ // if CWF_EN is disabled. these bit should be set to same as the RDBUF_SIZE and AHB REQ DATA SIZE.
+ //00 : 64byte boundary.
+ //01 : 32byte boundary.
+ //10 : 16byte boundary.
+ //11 : reserved.
+#define SPIFC_ACTIMING0 ((0x0088 << 2) + 0xfe00ac00)
+ //bit 31:30. tSLCH
+ //bit 29:28 tCLSH
+ //bit 20:16 tSHWL
+ //bit 15:12 tSHSL2
+ //bit 11:8 tSHSL1
+ //bit 7:0 tWHSL
+#define SPIFC_ACTIMING1 ((0x0089 << 2) + 0xfe00ac00)
+ //bit 31. D2 pin WP_n function enable.
+ //bit 30. D2 Pin value in WP_n fucntion.
+ //bit 29. D3 Pin HOLD_n function enable.
+ //bit 8. DTR mode. not support.
+ //bit 6:4. Clock turn around delay. use it to set the system SPI clock read data delay.
+ //bit 3:0. not used.
+#define SPIFC_ACTIMING2 ((0x008a << 2) + 0xfe00ac00)
+ //bit 31. spi clock input pin enable. SPIFC controller used this pin as clock to latch the input data.
+ //bit [3:0] spi clock input pin delay adjustment.
+//SPI DATA BUFFER. There's a total 512Byte + 64byte(orgnized as 36x128bits) SRAM .
+// since each APB access is 32bits. So we use word address as APB read/write address.
+// But for SPI side we have to use 128bit boundary. That's the first Pragram/read SPI with data buffer must start at data buffer 128bit boundary. that means the SPIFC_USE_DBUF_ADDR last 2 bits must be 0.
+#define SPIFC_DBUF_CTRL ((0x0090 << 2) + 0xfe00ac00)
+ //bit 31. 1 = write DBUF. 0 : read DBUF.
+ //bit 30. 1. = auto update address. 0 don't change address.
+ //bit 7:0 DBUF address unit 32bits.
+#define SPIFC_DBUF_DATA ((0x0091 << 2) + 0xfe00ac00)
+ //bit 31:0. if SPIFC_DBUF_CTRL bit 31 = 1. write to this register will trigger one write to DBUF. and the data will be writen to DBUF.
+#define SPIFC_USER_DBUF_ADDR ((0x0092 << 2) + 0xfe00ac00)
+ //bit 7:0. the DBUF ADDRESS used to send to or receive from SPI FLASH. the last 2 bits must be 0.
+#define SPIFC_FLASH_STATUS ((0x00a0 << 2) + 0xfe00ac00)
+#define SPIFC_STATUS ((0x00a1 << 2) + 0xfe00ac00)
+ //bit 1. AES KEY valid. read only 1 : The aes key is ready to use. 0: the aes key is not ready.
+ //bit 0. SPI CTRL STATE IDLE. read only. 1 = idle; 0 = busy.
+#define SPIFC_CTRL ((0x00a2 << 2) + 0xfe00ac00)
+ //bit 15:14. mempd for DBUF MEMORY.
+ //bit 13 spifc asynchronous buffer clock disable. 1 = disable. 0 = enable.
+ //bit 12. spifc controller clock disable. 1 = disable. 0 = enable.
+ //bit 9. spifc asynchronous bufer clock auto gate enable. 1 = enable. 0 = disable.
+ //bit 8. spifc controller clock auto gate enable. 1 = enable. 0 = disable.
+ //bit 2. spifc interface reset. 1 = RESET. 0 = normal working mode.
+ //bit 1. spifc asynchronous buffer spi clock side reset. 1 = RESET. 0 : normal working mode.
+ //bit 0. spifc controller reset. 1 = RESET. 0 : normal working mode.
+//`endif
+//
+// Closing file: ../spifc/rtl/spifc_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_sec.vh
+//
+//`ifdef DMC_SEC_REG_DEFINE
+//`else
+//`define DMC_SEC_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfe025000
+// -----------------------------------------------
+//`define DMC_SEC_REG_BASE 32'hfe025000
+// DMC ID assignment.
+// ID[13 :0] total 14 bit ID.
+// ID[4:0]: for MASTER IDs.
+// 0: A55 CPU.
+// 1: DSPA
+// 2: DSPB
+// 3: WAVE
+// 4: GDC
+// 5: GE2D
+// 6: ISP
+// 7: NNA
+// 8: JPEG
+// 9~15: not used in C1.
+// 16 : Device. need to look at ID bit [11:9] to see the sub module master.
+// 16 : for Device. need to look at ID bit [11:9] to see the sub module master.
+// 17 : for USB AHB device.
+// 18 : for USB AXI host.
+// 19 : for I2C debug input.
+// 20~30: Not used in C1
+// 31: DMC internal test channel.
+// Device master is for small periphs. it is consists of 8 sub modules and identified with ID bits [11:9]
+// bit[11:9] == 0 : ETH
+// bit[11:9] == 1 : SPICC_A
+// bit[11:9] == 2 : SPICC_B
+// bit[11:9] == 3 : SD_EMMCA
+// bit[11:9] == 4 : SD_EMMCB
+// bit[11:9] == 5 : AUDIO. For AUDIO need to check ID[8:5] for detail.
+// ID[8:5] == 0: TO_DDR A
+// ID[8:5] == 1: TO_DDR B
+// ID[8:5] == 4: FROM_DDR A
+// ID[8:5] == 5: FROM_DDR B
+// bit[11:9] == 6 : DMA. For DMC need to check ID [8:6] for totoal 8 threads IDs.
+// bit[11:9] == 7 : NAND_EMMCC
+// Total 16 address regions can be defined in All DDR address space.
+// The first 15 region can be defined by start address and end address in 4Kbyte boundary. The 16th range is all other space not defined by the first 15 regions.
+// all the 15 regions can be enabled or disabled seperately. Each range use security level bit to select one of the two des key to do data scramble.
+// The region can be overlapped or crossover. For one transaction, DMC would check the address from region 0 to 15.
+// DMC would use the policy defined in the region that this transaction address hit first.
+// the region is define by >= STA && <= EDA.
+#define DMC_SEC_RANGE0_STA ((0x0000 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 start address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE0_EDA ((0x0001 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 end address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE1_STA ((0x0002 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 start address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE1_EDA ((0x0003 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 end address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE2_STA ((0x0004 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 start address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE2_EDA ((0x0005 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 end address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE3_STA ((0x0006 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 start address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE3_EDA ((0x0007 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 end address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE4_STA ((0x0008 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 start address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE4_EDA ((0x0009 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 end address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE5_STA ((0x000a << 2) + 0xfe025000)
+ //bit 31:12 : range 0 start address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE5_EDA ((0x000b << 2) + 0xfe025000)
+ //bit 31:12 : range 0 end address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE6_STA ((0x000c << 2) + 0xfe025000)
+ //bit 31:12 : range 0 start address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE6_EDA ((0x000d << 2) + 0xfe025000)
+ //bit 31:12 : range 0 end address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE7_STA ((0x000e << 2) + 0xfe025000)
+ //bit 31:12 : range 0 start address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE7_EDA ((0x000f << 2) + 0xfe025000)
+ //bit 31:12 : range 0 end address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE8_STA ((0x0010 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 start address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE8_EDA ((0x0011 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 end address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE9_STA ((0x0012 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 start address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE9_EDA ((0x0013 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 end address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE10_STA ((0x0014 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 start address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE10_EDA ((0x0015 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 end address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE11_STA ((0x0016 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 start address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE11_EDA ((0x0017 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 end address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE12_STA ((0x0018 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 start address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE12_EDA ((0x0019 << 2) + 0xfe025000)
+ //bit 31:12 : range 0 end address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE13_STA ((0x001a << 2) + 0xfe025000)
+ //bit 31:12 : range 0 start address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE13_EDA ((0x001b << 2) + 0xfe025000)
+ //bit 31:12 : range 0 end address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE14_STA ((0x001c << 2) + 0xfe025000)
+ //bit 31:12 : range 0 start address.
+ //bit 11:0 : reserved to be 0.
+#define DMC_SEC_RANGE14_EDA ((0x001d << 2) + 0xfe025000)
+ //bit 31:12 : range 0 end address.
+ //bit 11:0 : reserved to be 0.
+//there's total 36 bit sid_en polocis for each region read/write seperately.
+//*_sid_en[35:0]
+//bit 35: dmc_test access enable bit. 1: enable : 0 disable.
+//bit 34: i2c access enable bit. 1: enable : 0 disable.
+//bit 33: jpeg access enable bit. 1: enable : 0 disable.
+//bit 32: USB host access enable bit. 1: enable : 0 disable.
+//bit 31: USB device access enable bit. 1: enable : 0 disable.
+//bit 30: NNA non-secure access enable bit. 1: enable : 0 disable.
+//bit 29: NNA secure access enable bit. 1: enable : 0 disable.
+//bit 28: ISP access enable bit. 1: enable : 0 disable.
+//bit 27: GE2D read source 1 enable bit. not used for write. 1: enable : 0 disable.
+//bit 26: GE2D read source 0 enable bit. GE2D write access enable bit for write. 1: enable : 0 disable.
+//bit 25: GDC access enable bit. 1: enable. 0: disable.
+//bit 24: WAVE access enable bit. 1: enable. 0: disable.
+//bit 23: NAND_EMMCC access enable bit. 1: enable. 0: disable.
+//bit 22: SD_EMMCB access enable bit. 1: enable. 0: disable.
+//bit 21: SD_EMMCA access enable bit. 1: enable. 0: disable.
+//bit 20: SPICC_B access enable bit. 1: enable. 0: disable.
+//bit 19: SPICC_A access enable bit. 1: enable. 0: disable.
+//bit 18: ETH access enable bit. 1: enable. 0: disable.
+//bit 17:10: DMA thread ID access enable bit. each thread for one bit. (only 4/6 threads supports in C1). 1: enable. 0: disable.
+//bit 9:6: AUDIO channel sub ID access enable bit. each ID for one bit. (2 read IDs and 2 write IDs supports in C1). 1: enable. 0: disable.
+//bit 5: DSP_B non-secure access enable bit. 1: enable. 0: disable.
+//bit 4: DSP_B secure access enable bit. 1: enable. 0: disable.
+//bit 3: DSP_A non-secure access enable bit. 1: enable. 0: disable.
+//bit 2: DSP_A secure access enable bit. 1: enable. 0: disable.
+//bit 1: A55 non-secure access enable bit. 1: enable. 0: disable.
+//bit 0: A55 secure access enable bit. 1: enable. 0: disable.
+//wire [1:0] cpu_sid_en = range_sid_en[1:0];
+//wire [1:0] dspa_sid_en = range_sid_en[3:2];
+//wire [1:0] dspb_sid_en = range_sid_en[5:4];
+//wire [3:0] audio_sid_en = range_sid_en[9:6];
+//wire [7:0] dma_sid_en = range_sid_en[17:10];
+//wire [7:0] dev_sid_en = {range_sid_en[23], 2'b0, range_sid_en[22:18]};
+//wire wave_sid_en = range_sid_en[24];
+//wire gdc_sid_en = range_sid_en[25];
+//wire [1:0] ge2d_sid_en = range_sid_en[27:26];
+//wire isp_sid_en = range_sid_en[28];
+//wire [1:0] nna_sid_en = range_sid_en[30:29];
+//wire usb_sid_en = range_sid_en[31];
+//wire usb2_sid_en = range_sid_en[32];
+//wire jpeg_sid_en = range_sid_en[33];
+//wire i2c_sid_en = range_sid_en[34];
+//wire test_sid_en = range_sid_en[35];
+#define DMC_SEC_RANGE0_RID_CTRL0 ((0x0020 << 2) + 0xfe025000)
+ //range0_rd_sid_en[31:0];
+#define DMC_SEC_RANGE0_RID_CTRL1 ((0x0021 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range0_rd_sid_en[35:32];
+#define DMC_SEC_RANGE1_RID_CTRL0 ((0x0022 << 2) + 0xfe025000)
+ //range1_rd_sid_en[31:0];
+#define DMC_SEC_RANGE1_RID_CTRL1 ((0x0023 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range1_rd_sid_en[35:32];
+#define DMC_SEC_RANGE2_RID_CTRL0 ((0x0024 << 2) + 0xfe025000)
+ //range2_rd_sid_en[31:0];
+#define DMC_SEC_RANGE2_RID_CTRL1 ((0x0025 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range2_rd_sid_en[35:32];
+#define DMC_SEC_RANGE3_RID_CTRL0 ((0x0026 << 2) + 0xfe025000)
+ //range3_rd_sid_en[31:0];
+#define DMC_SEC_RANGE3_RID_CTRL1 ((0x0027 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range3_rd_sid_en[35:32];
+#define DMC_SEC_RANGE4_RID_CTRL0 ((0x0028 << 2) + 0xfe025000)
+ //range4_rd_sid_en[31:0];
+#define DMC_SEC_RANGE4_RID_CTRL1 ((0x0029 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range4_rd_sid_en[35:32];
+#define DMC_SEC_RANGE5_RID_CTRL0 ((0x002a << 2) + 0xfe025000)
+ //range5_rd_sid_en[31:0];
+#define DMC_SEC_RANGE5_RID_CTRL1 ((0x002b << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range5_rd_sid_en[35:32];
+#define DMC_SEC_RANGE6_RID_CTRL0 ((0x002c << 2) + 0xfe025000)
+ //range6_rd_sid_en[31:0];
+#define DMC_SEC_RANGE6_RID_CTRL1 ((0x002d << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range6_rd_sid_en[35:32];
+#define DMC_SEC_RANGE7_RID_CTRL0 ((0x002e << 2) + 0xfe025000)
+ //range7_rd_sid_en[31:0];
+#define DMC_SEC_RANGE7_RID_CTRL1 ((0x002f << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range7_rd_sid_en[35:32];
+#define DMC_SEC_RANGE8_RID_CTRL0 ((0x0030 << 2) + 0xfe025000)
+ //range8_rd_sid_en[31:0];
+#define DMC_SEC_RANGE8_RID_CTRL1 ((0x0031 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range8_rd_sid_en[35:32];
+#define DMC_SEC_RANGE9_RID_CTRL0 ((0x0032 << 2) + 0xfe025000)
+ //range9_rd_sid_en[31:0];
+#define DMC_SEC_RANGE9_RID_CTRL1 ((0x0033 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range9_rd_sid_en[35:32];
+#define DMC_SEC_RANGE10_RID_CTRL0 ((0x0034 << 2) + 0xfe025000)
+ //range10_rd_sid_en[31:0];
+#define DMC_SEC_RANGE10_RID_CTRL1 ((0x0035 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range10_rd_sid_en[35:32];
+#define DMC_SEC_RANGE11_RID_CTRL0 ((0x0036 << 2) + 0xfe025000)
+ //range11_rd_sid_en[31:0];
+#define DMC_SEC_RANGE11_RID_CTRL1 ((0x0037 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range11_rd_sid_en[35:32];
+#define DMC_SEC_RANGE12_RID_CTRL0 ((0x0038 << 2) + 0xfe025000)
+ //range12_rd_sid_en[31:0];
+#define DMC_SEC_RANGE12_RID_CTRL1 ((0x0039 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range12_rd_sid_en[35:32];
+#define DMC_SEC_RANGE13_RID_CTRL0 ((0x003a << 2) + 0xfe025000)
+ //range13_rd_sid_en[31:0];
+#define DMC_SEC_RANGE13_RID_CTRL1 ((0x003b << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range13_rd_sid_en[35:32];
+#define DMC_SEC_RANGE14_RID_CTRL0 ((0x003c << 2) + 0xfe025000)
+ //range14_rd_sid_en[31:0];
+#define DMC_SEC_RANGE14_RID_CTRL1 ((0x003d << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range14_rd_sid_en[35:32];
+#define DMC_SEC_RANGE15_RID_CTRL0 ((0x003e << 2) + 0xfe025000)
+ //range15_rd_sid_en[31:0];
+#define DMC_SEC_RANGE15_RID_CTRL1 ((0x003f << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range15_rd_sid_en[35:32];
+#define DMC_SEC_RANGE0_WID_CTRL0 ((0x0060 << 2) + 0xfe025000)
+ //range0_wr_sid_en[31:0];
+#define DMC_SEC_RANGE0_WID_CTRL1 ((0x0061 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range0_wr_sid_en[35:32];
+#define DMC_SEC_RANGE1_WID_CTRL0 ((0x0062 << 2) + 0xfe025000)
+ //range1_wr_sid_en[31:0];
+#define DMC_SEC_RANGE1_WID_CTRL1 ((0x0063 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range0_wr_sid_en[35:32];
+#define DMC_SEC_RANGE2_WID_CTRL0 ((0x0064 << 2) + 0xfe025000)
+ //range2_wr_sid_en[31:0];
+#define DMC_SEC_RANGE2_WID_CTRL1 ((0x0065 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range0_wr_sid_en[35:32];
+#define DMC_SEC_RANGE3_WID_CTRL0 ((0x0066 << 2) + 0xfe025000)
+ //range3_wr_sid_en[31:0];
+#define DMC_SEC_RANGE3_WID_CTRL1 ((0x0067 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range0_wr_sid_en[35:32];
+#define DMC_SEC_RANGE4_WID_CTRL0 ((0x0068 << 2) + 0xfe025000)
+ //range4_wr_sid_en[31:0];
+#define DMC_SEC_RANGE4_WID_CTRL1 ((0x0069 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range0_wr_sid_en[35:32];
+#define DMC_SEC_RANGE5_WID_CTRL0 ((0x006a << 2) + 0xfe025000)
+ //range5_wr_sid_en[31:0];
+#define DMC_SEC_RANGE5_WID_CTRL1 ((0x006b << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range0_wr_sid_en[35:32];
+#define DMC_SEC_RANGE6_WID_CTRL0 ((0x006c << 2) + 0xfe025000)
+ //range6_wr_sid_en[31:0];
+#define DMC_SEC_RANGE6_WID_CTRL1 ((0x006d << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range0_wr_sid_en[35:32];
+#define DMC_SEC_RANGE7_WID_CTRL0 ((0x006e << 2) + 0xfe025000)
+ //range7_wr_sid_en[31:0];
+#define DMC_SEC_RANGE7_WID_CTRL1 ((0x006f << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range0_wr_sid_en[35:32];
+#define DMC_SEC_RANGE8_WID_CTRL0 ((0x0070 << 2) + 0xfe025000)
+ //range8_wr_sid_en[31:0];
+#define DMC_SEC_RANGE8_WID_CTRL1 ((0x0071 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range0_wr_sid_en[35:32];
+#define DMC_SEC_RANGE9_WID_CTRL0 ((0x0072 << 2) + 0xfe025000)
+ //range9_wr_sid_en[31:0];
+#define DMC_SEC_RANGE9_WID_CTRL1 ((0x0073 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range0_wr_sid_en[35:32];
+#define DMC_SEC_RANGE10_WID_CTRL0 ((0x0074 << 2) + 0xfe025000)
+ //range10_wr_sid_en[31:0];
+#define DMC_SEC_RANGE10_WID_CTRL1 ((0x0075 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range0_wr_sid_en[35:32];
+#define DMC_SEC_RANGE11_WID_CTRL0 ((0x0076 << 2) + 0xfe025000)
+ //range11_wr_sid_en[31:0];
+#define DMC_SEC_RANGE11_WID_CTRL1 ((0x0077 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range0_wr_sid_en[35:32];
+#define DMC_SEC_RANGE12_WID_CTRL0 ((0x0078 << 2) + 0xfe025000)
+ //range12_wr_sid_en[31:0];
+#define DMC_SEC_RANGE12_WID_CTRL1 ((0x0079 << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range0_wr_sid_en[35:32];
+#define DMC_SEC_RANGE13_WID_CTRL0 ((0x007a << 2) + 0xfe025000)
+ //range13_wr_sid_en[31:0];
+#define DMC_SEC_RANGE13_WID_CTRL1 ((0x007b << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range0_wr_sid_en[35:32];
+#define DMC_SEC_RANGE14_WID_CTRL0 ((0x007c << 2) + 0xfe025000)
+ //range14_wr_sid_en[31:0];
+#define DMC_SEC_RANGE14_WID_CTRL1 ((0x007d << 2) + 0xfe025000)
+ //bit 31:4. Not used.
+ //bit 3:0 range0_wr_sid_en[35:32];
+#define DMC_SEC_RANGE15_WID_CTRL0 ((0x007e << 2) + 0xfe025000)
+ //range15_wr_sid_en[31:0];
+#define DMC_SEC_RANGE15_WID_CTRL1 ((0x007f << 2) + 0xfe025000)
+#define DMC_SEC_RANGE_CTRL ((0x00a0 << 2) + 0xfe025000)
+ //bit 31:16 16 range security level. each
+ //bit 15:0 16 range enable. each bit for one range to indentify the range is enabled or not.
+#define DMC_DES_PADDING ((0x00a1 << 2) + 0xfe025000)
+ //32bits address padding used for DES data generation.
+#define DMC_DES_CTRL ((0x00a2 << 2) + 0xfe025000)
+ //bit 1 DES enable. 1: DES enable. 0 : DES disable. default is 1.
+ //bit 0. DES register mask. if write 1 only. after write 1, DES_CTRL and DES_padding regsiter can't be write and read.
+// two address protection function for debug purpose.
+// protected address[31:12] >= STA && <= EDA,
+#define DMC_PROT0_STA ((0x00a3 << 2) + 0xfe025000)
+ //bit 31:12. PROT0 start addresss
+#define DMC_PROT0_EDA ((0x00a4 << 2) + 0xfe025000)
+ //bit 31:12. PROT0 end addresss
+#define DMC_PROT0_CTRL ((0x00a5 << 2) + 0xfe025000)
+ //31:0 PROT0 IDs enable bit for ID[4:0]. 1: under protection control. 0 normal access.
+#define DMC_PROT0_CTRL1 ((0x00a6 << 2) + 0xfe025000)
+ //bit 26. protection 0 read access protection enable.
+ //bit 25. protection 0 write access block function. if enabled, the hit access wouldn't write to the DDR SDRAM. if not enabled only generate a interrupt, but the access still wrote to DDR.
+ //bit 24. protection 0 write access protection enable.
+ //other bits not used.
+#define DMC_PROT1_STA ((0x00a7 << 2) + 0xfe025000)
+ //bit 31:12. PROT1 start addresss
+#define DMC_PROT1_EDA ((0x00a8 << 2) + 0xfe025000)
+ //bit 31:12. PROT1 end addresss
+#define DMC_PROT1_CTRL ((0x00a9 << 2) + 0xfe025000)
+ //31:0 PROT1 IDs enable bit for ID[4:0]. 1: under protection control. 0 normal access.
+#define DMC_PROT1_CTRL1 ((0x00aa << 2) + 0xfe025000)
+ //bit 26. PROT1 read access protection enable.
+ //bit 25. PROT1 write access block function. if enabled, the hit access wouldn't write to the DDR SDRAM. if not enabled only generate a interrupt, but the access still wrote to DDR.
+ //bit 24. PROT1 write access protection enable.
+ //other bits not used.
+//registers to check the security protection and watch point error information.
+#define DMC_SEC_STATUS ((0x00b8 << 2) + 0xfe025000)
+ //bit 31. sec key valid. des key is from outside, when is valid, DMC will catch the Key and save in local when the key valid signal change to 1 from 0.
+ //bit 30~2. not used.
+ //bit 1 write security violation.
+ //bit 0. read security violation.
+#define DMC_VIO_ADDR0 ((0x00b9 << 2) + 0xfe025000)
+ //ddr0 write secure violation address.
+#define DMC_VIO_ADDR1 ((0x00ba << 2) + 0xfe025000)
+ //bit 31:25 . not used. always 0.
+ //24 ddr0 secure check violation.
+ //23 ddr0 protection 1 vilation.
+ //22 ddr0 protection 0 vilation.
+ //21:20 not used. always 0.
+ //19 ddr0 write address overflow. write out of DDR size.
+ //18:16. ddr0 write violation AWPROT bits.
+ //15:14. reserved for future ID bits.
+ //13:0 ddr0_write violation ID.
+#define DMC_VIO_ADDR2 ((0x00bb << 2) + 0xfe025000)
+ //ddr0 read seure violation address
+#define DMC_VIO_ADDR3 ((0x00bc << 2) + 0xfe025000)
+ //24 ddr0 read secure check violation.
+ //23 ddr0 read protection 1 violation.
+ //22 ddr0 read protection 0 violation.
+ //21:20 Not used. read to be 0.
+ //19 ddr 0 read address overflow. write out of DDR size.
+ //18:16. ddr 0 read violation ARPROT bits.
+ //15:14 reserved for future ID bits.
+ //13:0 ddr 0 read violation ID.
+//DDR3/4 LPDDR3/4 SDRAM address to 32bits linear address address map:
+//DDR0_ADDRMAP is used to select RANK0 bank, row, col address selection.
+//DDR1_ADDRMAP is used to select RANK1 bank, row, col address selection.
+#define DDR0_ADDRMAP_0 ((0x00d0 << 2) + 0xfe025000)
+ //29:25 ca8.
+ //24:20 ca7.
+ //19:15 ca6.
+ //14:10 ca5.
+ //9:5 ca4.
+ //4:0 ca3.
+#define DDR0_ADDRMAP_1 ((0x00d1 << 2) + 0xfe025000)
+ //29:25 ra2.
+ //24:20 ra1.
+ //19:15 ra0.
+ //14:10 ca11.
+ //9:5 ca10.
+ //4:0 ca9.
+#define DDR0_ADDRMAP_2 ((0x00d2 << 2) + 0xfe025000)
+ //29:25 ra8.
+ //24:20 ra7.
+ //19:15 ra6.
+ //14:10 ra5.
+ //9:5 ra4.
+ //4:0 ra3.
+#define DDR0_ADDRMAP_3 ((0x00d3 << 2) + 0xfe025000)
+ //29:25 ra14.
+ //24:20 ra13.
+ //19:15 ra12.
+ //14:10 ra11.
+ //9:5 ra10.
+ //4:0 ra9.
+#define DDR0_ADDRMAP_4 ((0x00d4 << 2) + 0xfe025000)
+ //29:25 ra16 for DDR4 SDRAM
+ //24:20 bg1 for DDR4 SDRAM.
+ //19:15 ba2. or bg0 for DDR4.
+ //14:10 ba1.
+ //9:5 ba0.
+ //4:0 ra15.
+#define DDR1_ADDRMAP_0 ((0x00d5 << 2) + 0xfe025000)
+ //29:25 ca8.
+ //24:20 ca7.
+ //19:15 ca6.
+ //14:10 ca5.
+ //9:5 ca4.
+ //4:0 ca3.
+#define DDR1_ADDRMAP_1 ((0x00d6 << 2) + 0xfe025000)
+ //29:25 ra2.
+ //24:20 ra1.
+ //19:15 ra0.
+ //14:10 ca11.
+ //9:5 ca10.
+ //4:0 ca9.
+#define DDR1_ADDRMAP_2 ((0x00d7 << 2) + 0xfe025000)
+ //29:25 ra8.
+ //24:20 ra7.
+ //19:15 ra6.
+ //14:10 ra5.
+ //9:5 ra4.
+ //4:0 ra3.
+#define DDR1_ADDRMAP_3 ((0x00d8 << 2) + 0xfe025000)
+ //29:25 ra14.
+ //24:20 ra13.
+ //19:15 ra12.
+ //14:10 ra11.
+ //9:5 ra10.
+ //4:0 ra9.
+#define DDR1_ADDRMAP_4 ((0x00d9 << 2) + 0xfe025000)
+ //29:25 ra16 for DDR4 SDRAM
+ //24:20 bg1 for DDR4 SDRAM.
+ //19:15 ba2 or bg0 for DDR4 SDRAM..
+ //14:10 ba1.
+ //9:5 ba0.
+ //4:0 ra15.
+#define DMC_DDR_CTRL ((0x00da << 2) + 0xfe025000)
+ //bit 31:28. 16bit selection for DDR3/4 not balanced mode.
+ //4'b1000: 3Gbyte mode. low 2Gbyte is in 32bits mode. 2G~3G is 16bits mode.
+ //4'b0100: 1.5Gbyte mode. low 1Gbyte is in 32bits mode. 1G~1.5G is in 16bits mode.
+ //4'b0010: 768Mbyte mode. low 512Mbyte is in 32bits mode. 512M~768M is in 16bits mode.
+ //4'b0001: 384Mbyte mode. low 25Mbyte is in 32bits mode. 256M~384M is in 16bits m0doe.
+ // 4'b000 or others balance mode. ether 32bits mode or 16bits mode depends on bit
+ //bit 27. 0 : in 16bits mode. 16bit address postion at the top.
+ // 1 : in 16bits mode. 16bits address postion start at address 0.
+ //bit 24:22 3'b000 : ddr3 mode.
+ //3'b001 : ddr4 mode.
+ //3'b010 : lpddr3 mode.
+ //3'b011 : lpddr4 mode.
+ //bit 21. rank1 enable bit. if 1, rank1 used the address map is as bit 5:3 defined.
+ //bit 20 DDR4 BG1 enable bit.
+ //bit 18: always 0.
+ //bit 16. 1 only use 16bits data in a 32bits phy data interface. 0 : normal data interface.
+ //bit 7:4 : DDR rank 1 size.
+ //4'b0000 : DDR rank 1 is 128Mbyte.
+ //4'b0001 : DDR rank 1 is 256Mbyte.
+ //4'b0010 : DDR rank 1 is 512Mbyte.
+ //4'b0011 : DDR rank 1 is 1Gbyte.
+ //4'b0100 : DDR rank 1 is 2Gbyte.
+ //4'b1000 : DDR rank 1 is 192Mbyte.
+ //4'b1001 : DDR rank 1 is 374Mbyte.
+ //4'b1010 : DDR rank 1 is 768Mbyte.
+ //4'b1011 : DDR rank 1 is 1.5Gbyte.
+ //4'b1100 : DDR rank 1 is 3Gbyte.
+ //others : reserved.
+ //bit 3:0 : DDR rank 0 size.
+ //4'b0000 : DDR rank 0 is 128Mbyte.
+ //4'b0001 : DDR rank 0 is 256Mbyte.
+ //4'b0010 : DDR rank 0 is 512Mbyte.
+ //4'b0011 : DDR rank 0 is 1Gbyte.
+ //4'b0100 : DDR rank 0 is 2Gbyte.
+ //4'b1000 : DDR rank 0 is 192Mbyte.
+ //4'b1001 : DDR rank 0 is 374Mbyte.
+ //4'b1010 : DDR rank 0 is 768Mbyte.
+ //4'b1011 : DDR rank 0 is 1.5Gbyte.
+ //4'b1100 : DDR rank 0 is 3Gbyte.
+ //others : reserved.
+#define DDR_APB_SEC_CTRL ((0x00db << 2) + 0xfe025000)
+ //bit 19:16. DMC normal APB register secure control.
+ //bit 19: 1: all can write those register. 0: the APB_PROT[0] must match the bit 0 to write those regsiter.
+ //Bit15:12. DMC sticky APB regsiter secure control.
+ //bit 15. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 12 to write those register.
+ //bit 11:8. DMC DDR PLL clock related APB regsiter secure control.
+ //bit 11. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 8 to write those register.
+ //Bit 7:4. DMC DDR SDRAM protocal contorl register contorl
+ //bit 11. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 4 to write those register.
+ //bit 3:0. LPDDR4 PHY APB regsiter secure control.
+ //bit 3. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 0 to write those register.
+//`endif
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_sec.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_test.vh
+//
+// -----------------------------------------------
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfe025400
+// -----------------------------------------------
+// -----------------------------------------------
+//`define DMC_TEST_REG_BASE 32'hfe025400
+#define DMC_TEST_WRCMD_ADDR ((0x0000 << 2) + 0xfe025400)
+ // the current write cmd address.
+#define DMC_TEST_RDRSP_ADDR ((0x0001 << 2) + 0xfe025400)
+ // the failed read response address(for error data )
+#define DMC_TEST_RDCMD_ADDR ((0x0002 << 2) + 0xfe025400)
+ // the current read command address.
+#define DMC_TEST_WDG ((0x0003 << 2) + 0xfe025400)
+ //31:16. write response watch dog.
+ //15:0. read response watch dog.
+#define DMC_TEST_STA ((0x0004 << 2) + 0xfe025400)
+ //test start address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary.
+ // for sha mode, address must be in 64 bytes boundary. that mean the last 6 bits must be 0.
+#define DMC_TEST_EDA ((0x0005 << 2) + 0xfe025400)
+ //test end address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary.
+ // for sha mode, address must be in 64 bytes boundary. that mean the last 6bits must be 1.
+#define DMC_TEST_CTRL ((0x0006 << 2) + 0xfe025400)
+ //bit 31. enable test.
+ //bit 30. when enable test, enable the write to DDR function.
+ //bit 29. when enable test, enable the read from DDR function.
+ //bit 28. when enable test, enable the sha calculation function must be same as read enable but without write function.
+ //bit 27. enabe to compare data. when do the read enable to enable the error comparaion. suppose the read data should be same as the data in the write buffer.
+ //bit 26. reserved.
+ //bit 25. address generation type. 0: continuous increase the address in the range of test start address and test end address.
+ // 1: test module would pick the random address from test start address and test end address.
+ //bit 24. done type. 0 : use the DMC_TEST_NUM register as the counter of test numbers.
+ // for write if the write command number == the DMC_TEST_NUM, the write is done.
+ // for read if the read command number == the DMC TEST_num, the read id done. for one read command can be repeated repeat number times.
+ // 1 : finshed at end address.
+ //bit 23. wdata type. 1 : the first write is {WD3, WD2,WD1,WD0}, then the latter is the previous data plus a pattern.( { + WD7, + WD6, + WD5, + WD4}).
+ // 0 : the WDATA is the data in write register.
+ //bit 23. reserved.
+ //bit 22:20. read repeat times. for non-sha function, we can define multi times of the read. the test module would repeat the same adddress repeat times.
+ //bit 19. limit write. 0: no outstanding write request limitation.
+ // 1: limit the outstanding write commands to the number of bits [15:8]
+ //bit 18. limit read. 0. no outstanding read request limitation.
+ // 1. limit the read outstanding request to the number of bits[7:0].
+ //bit 17:16. sha mode for sha function enabled. 00 : not used. 01 : sha1. 2: sha2-256. 3: sha2_224. not used in GXL fixed to be Sha 2.
+ //bit 15:8. write outstanding commands limit.
+ //bit 7:0. read outstanding commands limit.
+#define DMC_TEST_NUM ((0x0007 << 2) + 0xfe025400)
+ // how many test command for the test if the DMC_TEST_CTRL bit 24 is 0.
+#define DMC_TEST_WD0 ((0x0010 << 2) + 0xfe025400)
+ // write data 0 for write command. also for read back data comparision.
+#define DMC_TEST_WD1 ((0x0011 << 2) + 0xfe025400)
+ // write data 1 for write command. also for read back data comparision.
+#define DMC_TEST_WD2 ((0x0012 << 2) + 0xfe025400)
+ // write data 2 for write command. also for read back data comparision.
+#define DMC_TEST_WD3 ((0x0013 << 2) + 0xfe025400)
+ // write data 3 for write command. also for read back data comparision.
+#define DMC_TEST_WD4 ((0x0014 << 2) + 0xfe025400)
+ // write data 4 for write command. also for read back data comparision.
+#define DMC_TEST_WD5 ((0x0015 << 2) + 0xfe025400)
+ // write data 5 for write command. also for read back data comparision.
+#define DMC_TEST_WD6 ((0x0016 << 2) + 0xfe025400)
+ // write data 6 for write command. also for read back data comparision.
+#define DMC_TEST_WD7 ((0x0017 << 2) + 0xfe025400)
+ // write data 7 for write command. also for read back data comparision.
+#define DMC_TEST_WD8 ((0x0018 << 2) + 0xfe025400)
+ // write data 8 for write command. also for read back data comparision.
+#define DMC_TEST_WD9 ((0x0019 << 2) + 0xfe025400)
+ // write data 9 for write command. also for read back data comparision.
+#define DMC_TEST_WD10 ((0x001a << 2) + 0xfe025400)
+ // write data 10 for write command. also for read back data comparision.
+#define DMC_TEST_WD11 ((0x001b << 2) + 0xfe025400)
+ // write data 11 for write command. also for read back data comparision.
+#define DMC_TEST_WD12 ((0x001c << 2) + 0xfe025400)
+ // write data 12 for write command. also for read back data comparision.
+#define DMC_TEST_WD13 ((0x001d << 2) + 0xfe025400)
+ // write data 13 for write command. also for read back data comparision.
+#define DMC_TEST_WD14 ((0x001e << 2) + 0xfe025400)
+ // write data 14 for write command. also for read back data comparision.
+#define DMC_TEST_WD15 ((0x001f << 2) + 0xfe025400)
+ // write data 15 for write command. also for read back data comparision.
+#define DMC_TEST_RD0 ((0x0020 << 2) + 0xfe025400)
+ // the read back data 0. if error happens, it would capture the first error data.
+#define DMC_TEST_RD1 ((0x0021 << 2) + 0xfe025400)
+ // the read back data 1. if error happens, it would capture the first error data.
+#define DMC_TEST_RD2 ((0x0022 << 2) + 0xfe025400)
+ // the read back data 2. if error happens, it would capture the first error data.
+#define DMC_TEST_RD3 ((0x0023 << 2) + 0xfe025400)
+ // the read back data 3. if error happens, it would capture the first error data.
+#define DMC_TEST_RD4 ((0x0024 << 2) + 0xfe025400)
+ // the read back data 4. if error happens, it would capture the first error data.
+#define DMC_TEST_RD5 ((0x0025 << 2) + 0xfe025400)
+ // the read back data 5. if error happens, it would capture the first error data.
+#define DMC_TEST_RD6 ((0x0026 << 2) + 0xfe025400)
+ // the read back data 6. if error happens, it would capture the first error data.
+#define DMC_TEST_RD7 ((0x0027 << 2) + 0xfe025400)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD8 ((0x0028 << 2) + 0xfe025400)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD9 ((0x0029 << 2) + 0xfe025400)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD10 ((0x002a << 2) + 0xfe025400)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD11 ((0x002b << 2) + 0xfe025400)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD12 ((0x002c << 2) + 0xfe025400)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD13 ((0x002d << 2) + 0xfe025400)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD14 ((0x002e << 2) + 0xfe025400)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD15 ((0x002f << 2) + 0xfe025400)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_ERR_ADDR ((0x0030 << 2) + 0xfe025400)
+ // it capature the first error address.
+#define DMC_TEST_ERR_CNT ((0x0031 << 2) + 0xfe025400)
+ // how many data error happens in the whole test period.
+#define DMC_TEST_STS ((0x0032 << 2) + 0xfe025400)
+ //bit 31, test done bit. write 1 to clean.
+ //bit 30, indicate address err
+ //bit 29~7. not used.
+ //bit 6. read data resp error(caused by security or rd latency).
+ //bit 5. test MRR/MPR rd latency error. write 1 clear
+ //bit 4, sha done. write 1 to clean.
+ //bit 3, write done. write 1 to clean.
+ //bit 2, read done. write 1 to clean
+ //bit 1, write watchdog triggered. write 1 to clean
+ //bit 0, read watchdog triggered. write 1 to clean.
+#define DMC_TEST_COMP_MASK ((0x0033 << 2) + 0xfe025400)
+ //32bits for DMC TEST COMPARE bit enable.
+ //1 : to MASK this bit. 0: compare this bit.
+#define DMC_TEST_RDBI0 ((0x0034 << 2) + 0xfe025400)
+ //MPC RD FIFO command DBI read back data
+ //bit 31:16 the second cycle.
+ //bit 15:0 the first cycle.
+#define DMC_TEST_RDBI1 ((0x0035 << 2) + 0xfe025400)
+ //MPC RD FIFO command DBI read back data
+ //bit 31:16. the Forth cycle.
+ //bit 15:0. the third cycle.
+#define DMC_TEST_WSTRB0 ((0x0036 << 2) + 0xfe025400)
+ //MPC WR FIFO command DM bit write data
+ //bit 31:16 the second cycle.
+ //bit 15:0 the first cycle.
+#define DMC_TEST_WSTRB1 ((0x0037 << 2) + 0xfe025400)
+ //MPC WR FIFO command DM bit write data
+ //bit 31:16. the Forth cycle.
+ //bit 15:0. the third cycle.
+#define DMC_TEST_DRAM_CMD ((0x0038 << 2) + 0xfe025400)
+ //bit 31. cmd done. write 0 to clean.
+ //bit 30. data done. write 0 to clean.
+ //bit 4:0. only one bit can be 1. read data stored in DMC_TEST_RD* write data from DMC_TEST_W
+ //bit 4. LPDDR4 MPC write data command( MPC WR FIFO).
+ //bit 3. LPDDR4 MPC read data command (MPC RD Calibration and RD FIFO).
+ //bit 2. LPDDR4 MPC-1 command ( NOP, Start DQS interval ....)
+ //bit 1. mrr comand.
+ //bit 0. mrw command.
+#define DMC_TEST_DRAM_CMD_CODE ((0x0039 << 2) + 0xfe025400)
+ //bit 27:26. 128bits data cycles . 0: 1 clock cycles; 1: 2 clock cycles; 2: 3 clock cycles; 3:4 clock cycles.
+ // LPDDR4 32bits: 4 clock cycles; LPDDR4 16bits: 2 clock cycles;
+ // DDR3/4/LPDDR3 32 bits : 2 clock cycles. DDR3/4 16bits: 1 cycles.
+ //bit 25 MRW/MRR/MPC command rank 1 select. 1: select. 0: not select.
+ //bit 24. MRW/MRR/MPC command rank 0 select. 1: select. 0: not select.
+ //bit 23:16 MR addr. DDR4 case : 18:16 ba[2:0]. 20:19 BG[1:0].
+ //bit 15:0 opcode.
+#define DMC_TEST_DRAM_CMD_TIME ((0x003a << 2) + 0xfe025400)
+//bit 31:16 PRE CMD timer. //delay how many cycle to start the command.
+//bit 15:0 POST CMD timer //delay how many cycle after the command execute.
+//`endif
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_test.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_reg.vh
+//
+//`ifdef DMC_REG_DEFINE
+//`else
+//`define DMC_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfe024000
+// -----------------------------------------------
+//`define DMC_REG_BASE 32'hfe024000
+#define DMC_SOFT_RST ((0x0000 << 2) + 0xfe024000)
+#define DMC_SOFT_RST1 ((0x0002 << 2) + 0xfe024000)
+#define DMC_SOFT_RST2 ((0x0003 << 2) + 0xfe024000)
+ //bit 31~11. reserved for future.
+ //bit 10 DMC DFI cmd soft reset_n
+ //bit 9 DMC DFI MISC soft reset_n
+ //bit 8 DMC DFI data soft reset_n
+ //bit 7 DMC DFI dcu soft reset_n
+ //bit 6 DMC siu soft reset_n
+ //bit 5. DMC test soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 4. DMC low power control moudle soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 3. DMC QOS monitor module soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 2. DMC register modle soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 1. DMC canvas transfer module soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 0. DMC command buffers and command generation modules soft reset. 0 = reset. 1:
+#define DMC_VERSION ((0x0005 << 2) + 0xfe024000)
+ //read only 32'h000b0001. for A1
+#define DMC_MON_CTRL0 ((0x0020 << 2) + 0xfe024000)
+ //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
+ //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
+ //bit 3. qos monitor 3 enable.
+ //bit 2. qos monitor 2 enable.
+ //bit 1. qos monitor 1 enable.
+ //bit 0. qos monitor 0 enable.
+#define DMC_MON_CTRL1 ((0x0021 << 2) + 0xfe024000)
+ //enable to check which modules bandwidth in QOS monitor 0
+ //bit 31:21: not used.
+ //bit 20: enable DMC_TEST bandwidth check. 1 : enable. 0 : disable.
+ //bit 19: enable I2C bandwidth check. 1 : enable. 0 : disable.
+ //bit 18: enable USB host bandwidth check. 1 : enable. 0 : disable.
+ //bit 17: enable USB device bandwidth check. 1 : enable. 0 : disable.
+ //bit 16: enable NAND_EMMCC bandwidth check. 1 : enable. 0 : disable.
+ //bit 15: enable DMA bandwidth check. 1 : enable. 0 : disable.
+ //bit 14: enable AUDIO bandwidth check. 1 : enable. 0 : disable.
+ //bit 13: enable SD_EMMCB bandwidth check. 1 : enable. 0 : disable.
+ //bit 12: enable SD_EMMCA bandwidth check. 1 : enable. 0 : disable.
+ //bit 11: enable SPICC_B bandwidth check. 1 : enable. 0 : disable.
+ //bit 10: enable SPICC_A bandwidth check. 1 : enable. 0 : disable.
+ //bit 9: enable ETH bandwidth check. 1 : enable. 0 : disable.
+ //bit 8: enable JPEG bandwidth check. 1 : enable. 0 : disable.
+ //bit 7: enable NNA bandwidth check. 1 : enable. 0 : disable.
+ //bit 6: enable ISP bandwidth check. 1 : enable. 0 : disable.
+ //bit 5: enable GE2D bandwidth check. 1 : enable. 0 : disable.
+ //bit 4: enable GDC bandwidth check. 1 : enable. 0 : disable.
+ //bit 3: enable WAVE bandwidth check. 1 : enable. 0 : disable.
+ //bit 2: enable DSPB bandwidth check. 1 : enable. 0 : disable.
+ //bit 1: enable DSPA bandwidth check. 1 : enable. 0 : disable.
+ //bit 0: enable CPU bandwidth check. 1 : enable. 0 : disable.
+#define DMC_MON_CTRL2 ((0x0022 << 2) + 0xfe024000)
+ //not used in C1
+#define DMC_MON_CTRL3 ((0x0023 << 2) + 0xfe024000)
+ //enable to check which modules bandwidth in QOS monitor 1
+ //bit 31:21: not used.
+ //bit 20: enable DMC_TEST bandwidth check. 1 : enable. 0 : disable.
+ //bit 19: enable I2C bandwidth check. 1 : enable. 0 : disable.
+ //bit 18: enable USB host bandwidth check. 1 : enable. 0 : disable.
+ //bit 17: enable USB device bandwidth check. 1 : enable. 0 : disable.
+ //bit 16: enable NAND_EMMCC bandwidth check. 1 : enable. 0 : disable.
+ //bit 15: enable DMA bandwidth check. 1 : enable. 0 : disable.
+ //bit 14: enable AUDIO bandwidth check. 1 : enable. 0 : disable.
+ //bit 13: enable SD_EMMCB bandwidth check. 1 : enable. 0 : disable.
+ //bit 12: enable SD_EMMCA bandwidth check. 1 : enable. 0 : disable.
+ //bit 11: enable SPICC_B bandwidth check. 1 : enable. 0 : disable.
+ //bit 10: enable SPICC_A bandwidth check. 1 : enable. 0 : disable.
+ //bit 9: enable ETH bandwidth check. 1 : enable. 0 : disable.
+ //bit 8: enable JPEG bandwidth check. 1 : enable. 0 : disable.
+ //bit 7: enable NNA bandwidth check. 1 : enable. 0 : disable.
+ //bit 6: enable ISP bandwidth check. 1 : enable. 0 : disable.
+ //bit 5: enable GE2D bandwidth check. 1 : enable. 0 : disable.
+ //bit 4: enable GDC bandwidth check. 1 : enable. 0 : disable.
+ //bit 3: enable WAVE bandwidth check. 1 : enable. 0 : disable.
+ //bit 2: enable DSPB bandwidth check. 1 : enable. 0 : disable.
+ //bit 1: enable DSPA bandwidth check. 1 : enable. 0 : disable.
+ //bit 0: enable CPU bandwidth check. 1 : enable. 0 : disable.
+#define DMC_MON_CTRL4 ((0x0024 << 2) + 0xfe024000)
+ //not used in C1
+#define DMC_MON_CTRL5 ((0x0025 << 2) + 0xfe024000)
+ //enable to check which modules bandwidth in QOS monitor 2
+ //bit 31:21: not used.
+ //bit 20: enable DMC_TEST bandwidth check. 1 : enable. 0 : disable.
+ //bit 19: enable I2C bandwidth check. 1 : enable. 0 : disable.
+ //bit 18: enable USB host bandwidth check. 1 : enable. 0 : disable.
+ //bit 17: enable USB device bandwidth check. 1 : enable. 0 : disable.
+ //bit 16: enable NAND_EMMCC bandwidth check. 1 : enable. 0 : disable.
+ //bit 15: enable DMA bandwidth check. 1 : enable. 0 : disable.
+ //bit 14: enable AUDIO bandwidth check. 1 : enable. 0 : disable.
+ //bit 13: enable SD_EMMCB bandwidth check. 1 : enable. 0 : disable.
+ //bit 12: enable SD_EMMCA bandwidth check. 1 : enable. 0 : disable.
+ //bit 11: enable SPICC_B bandwidth check. 1 : enable. 0 : disable.
+ //bit 10: enable SPICC_A bandwidth check. 1 : enable. 0 : disable.
+ //bit 9: enable ETH bandwidth check. 1 : enable. 0 : disable.
+ //bit 8: enable JPEG bandwidth check. 1 : enable. 0 : disable.
+ //bit 7: enable NNA bandwidth check. 1 : enable. 0 : disable.
+ //bit 6: enable ISP bandwidth check. 1 : enable. 0 : disable.
+ //bit 5: enable GE2D bandwidth check. 1 : enable. 0 : disable.
+ //bit 4: enable GDC bandwidth check. 1 : enable. 0 : disable.
+ //bit 3: enable WAVE bandwidth check. 1 : enable. 0 : disable.
+ //bit 2: enable DSPB bandwidth check. 1 : enable. 0 : disable.
+ //bit 1: enable DSPA bandwidth check. 1 : enable. 0 : disable.
+ //bit 0: enable CPU bandwidth check. 1 : enable. 0 : disable.
+#define DMC_MON_CTRL6 ((0x0026 << 2) + 0xfe024000)
+ //not USED in C1
+#define DMC_MON_CTRL7 ((0x0027 << 2) + 0xfe024000)
+ //enable to check which modules bandwidth in QOS monitor 3
+ //bit 31:21: not used.
+ //bit 20: enable DMC_TEST bandwidth check. 1 : enable. 0 : disable.
+ //bit 19: enable I2C bandwidth check. 1 : enable. 0 : disable.
+ //bit 18: enable USB host bandwidth check. 1 : enable. 0 : disable.
+ //bit 17: enable USB device bandwidth check. 1 : enable. 0 : disable.
+ //bit 16: enable NAND_EMMCC bandwidth check. 1 : enable. 0 : disable.
+ //bit 15: enable DMA bandwidth check. 1 : enable. 0 : disable.
+ //bit 14: enable AUDIO bandwidth check. 1 : enable. 0 : disable.
+ //bit 13: enable SD_EMMCB bandwidth check. 1 : enable. 0 : disable.
+ //bit 12: enable SD_EMMCA bandwidth check. 1 : enable. 0 : disable.
+ //bit 11: enable SPICC_B bandwidth check. 1 : enable. 0 : disable.
+ //bit 10: enable SPICC_A bandwidth check. 1 : enable. 0 : disable.
+ //bit 9: enable ETH bandwidth check. 1 : enable. 0 : disable.
+ //bit 8: enable JPEG bandwidth check. 1 : enable. 0 : disable.
+ //bit 7: enable NNA bandwidth check. 1 : enable. 0 : disable.
+ //bit 6: enable ISP bandwidth check. 1 : enable. 0 : disable.
+ //bit 5: enable GE2D bandwidth check. 1 : enable. 0 : disable.
+ //bit 4: enable GDC bandwidth check. 1 : enable. 0 : disable.
+ //bit 3: enable WAVE bandwidth check. 1 : enable. 0 : disable.
+ //bit 2: enable DSPB bandwidth check. 1 : enable. 0 : disable.
+ //bit 1: enable DSPA bandwidth check. 1 : enable. 0 : disable.
+ //bit 0: enable CPU bandwidth check. 1 : enable. 0 : disable.
+#define DMC_MON_CTRL8 ((0x0028 << 2) + 0xfe024000)
+ //not used.
+#define DMC_MON_ALL_REQ_CNT ((0x0029 << 2) + 0xfe024000)
+ // at the test period, the whole MMC request time.
+#define DMC_MON_ALL_GRANT_CNT ((0x002a << 2) + 0xfe024000)
+ // at the test period, the whole MMC granted data cycles. 64bits unit.
+#define DMC_MON_ONE_GRANT_CNT ((0x002b << 2) + 0xfe024000)
+ // at the test period, the granted data cycles for the selected channel and ports.
+#define DMC_MON_SEC_GRANT_CNT ((0x002c << 2) + 0xfe024000)
+ // at the test period, the granted data cycles for the selected channel and ports.
+#define DMC_MON_THD_GRANT_CNT ((0x002d << 2) + 0xfe024000)
+ // at the test period, the granted data cycles for the selected channel and ports.
+#define DMC_MON_FOR_GRANT_CNT ((0x002e << 2) + 0xfe024000)
+ // at the test period, the granted data cycles for the selected channel and ports.
+#define DMC_MON_TIMER ((0x002f << 2) + 0xfe024000)
+ // timer for the monitor period.
+#define DMC_CLKG_CTRL2 ((0x0032 << 2) + 0xfe024000)
+ //bit 10 enable auto clock gating for dfi command generation
+ //bit 9 enable auto clock gating for dram cntroller
+ //bit 8 enable auto clock gating for dfi data path.
+ //bit 7. enalbe auto clock gating for write rsp generation.
+ //bit 6. enalbe auto clock gating for read rsp generation.
+ //bit 5. enalbe auto clock gating for ddr0 command filter.
+ //bit 4. enalbe auto clock gating for ddr0 write reorder buffer.
+ //bit 3. enalbe auto clock gating for ddr0 write data buffer.
+ //bit 2. enalbe auto clock gating for ddr0 read reorder buffer.
+ //bit 1. reserved
+ //bit 0. reserved
+#define DMC_CLKG_CTRL3 ((0x0033 << 2) + 0xfe024000)
+ //bit 10 force to disable the clock of dfi command generation
+ //bit 9 force to disable the clock of dram cntroller
+ //bit 8 force to disable the clock of dfi data path.
+ //bit 7. force to disalbe the clock of write rsp generation.
+ //bit 6. force to disalbe the clock of read rsp generation.
+ //bit 5. force to disalbe the clock of command filter.
+ //bit 4. force to disalbe the clock of write reorder buffer.
+ //bit 3. force to disalbe the clock of write data buffer.
+ //bit 2. force to disalbe the clock of read reorder buffer.
+ //bit 1. reserved.
+ //bit 0. reserved.
+#define DMC_CHAN_STS ((0x0036 << 2) + 0xfe024000)
+ //bit 4 always 1
+ //bit 3 ddr0 write data buffer idle. 1 : idle 0: busy.
+ //bit 2 always 1.
+ //bit 1 ddr0 wbuf idle. 1 : idle 0: busy.
+ //bit 0. axi0 channel idle. 1 : idle 0: busy.
+#define DMC_CMD_FILTER_CTRL3 ((0x0042 << 2) + 0xfe024000)
+ //bit 31. force wbuf empty.
+ //bit 30:26 wbuf high level number
+ //bit 25:21 wbuf mid level number
+ //bit 20:16 wbuf low level number
+ //bit 14:10 rbuf high level number
+ //bit 9:5 rbuf middle level number
+ //bit 4:0 rbuf low level number
+#define DMC_CMD_FILTER_CTRL4 ((0x0043 << 2) + 0xfe024000)
+ //bit 29:25. tITW.long
+ //bit 24:20. tITW. short
+ //bit 19:12 tAP auto precharge the bank not used if idle that long time.
+ //bit 11:6 write to read accesses if there write hit request.
+ //bit 5:0 read to write accesses if there write hit request.
+#define DMC_CMD_FILTER_CTRL5 ((0x0044 << 2) + 0xfe024000)
+ //bit 31:24 Once ddr data bus switch to read, the maxmum read command number to give up the bus when there's write request pending for write buffer.
+ //bit 23:16 Once ddr data bus switch to write, the maxmum write command number to give up the bus when there's read request pending too long.
+ //bit 15:8. Once ddr data bus switch to read, the minimum read command number to transfer back to write stage if there's still pending read request.
+ //bit 7:0. Once ddr data bus switch to write, the minimum write command number to transfer back to read stage if there's still pending write request.
+#define DMC_CMD_FILTER_CTRL6 ((0x0045 << 2) + 0xfe024000)
+ //bit 31:24 write urgent 3 request pending hold num.
+ //bit 23:16 write urgent 2 request pending hold num.
+ //bit 15:8. write urgent 1 request pending hold num.
+ //bit 7:0. write urgent 0 request pending hold num.
+#define DMC_CMD_FILTER_CTRL7 ((0x0046 << 2) + 0xfe024000)
+ //bit 15:8 write to read waiting cycles if there write hit request.
+ //bit 7:0 read to write waiting cycles if there write hit request.
+#define DMC_CMD_BUFFER_CTRL ((0x0047 << 2) + 0xfe024000)
+ //bit 31:26 total write buffer number. default 32.
+ //bit 25:20 total read buffer number. default 32.
+ //bit 19:14. Not used.
+ //bit 13:8 write command fifo depth. default 32.
+ //bit 7:0 aw_pending_inc_num. incease write ugent level 1 when write command waiting to in write buffer that long.
+#define DMC_CMD_BUFFER_CTRL1 ((0x0048 << 2) + 0xfe024000)
+ //bit 29:24 read buffer number in non-urgent request.
+ //bit 23:16 read buffer bank miss watch dog threshold.
+ //bit 15:12 read buffer urgent level 3 counter inc weight.
+ //bit 11:8 read buffer urgent level 2 counter inc weight.
+ //bit 7:4 read buffer urgent level 1 counter inc weight.
+ //bit 3:0 read buffer urgent level 0 counter inc weight.
+#define DMC_AXI0_CHAN_CTRL ((0x0080 << 2) + 0xfe024000)
+ //bit 31 AXI interface request enable.
+ //bit 19 AXI interface auto clock gating enable. 1: enable; 0 disable.
+ //bit 18 AXI interface clock disable. 1 : disable clock. 0 enable clock.
+ //bit 17 AXI interface dmc clock domain soft reset. 0 : reset. 1 : normal working mode.
+ //bit 16 AXI interface s0 clock domain soft reset. 0 : reset. 1 : normal working mode.
+ //bit 15:12 ugt3 QOS level.
+ //bit 11:8 ugt2 QOS level.
+ //bit 7:4 ugt1 QOS level.
+ //bit 3:0 not used.
+#define DMC_AXI0_HOLD_CTRL ((0x0081 << 2) + 0xfe024000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI5_HOLD_CTRL ((0x0095 << 2) + 0xfe024000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+//`endif
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh
+//
+//`ifdef DMC_SIU_REG_DEFINE
+//`else
+//`define DMC_SIU_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfe024400
+// -----------------------------------------------
+//`define DMC_DRAM_REG_BASE 32'hfe024400
+//there's 2 set of timing DDR timing parameter for 2 set of DDR freqency parameter.
+//when change frequency, the hardware would automatically select one of these two set of timing parameter
+//DMC_DRAM_* is for Frequency set 0.
+//DMC_NFQ_* is for Freqency set 1.
+#define DMC_DRAM_TMRD ((0x0000 << 2) + 0xfe024400)
+ //bit 3:0. tMRD.
+#define DMC_DRAM_TRFC ((0x0001 << 2) + 0xfe024400)
+ //bit 9:0 tRFC
+#define DMC_DRAM_TRP ((0x0002 << 2) + 0xfe024400)
+ //bit 21:16. tRP for precharge all banks.
+ //bit 5:0. tRP for precharge one bank.
+#define DMC_DRAM_TRTW ((0x0003 << 2) + 0xfe024400)
+ //bit 5:0 tRTW
+#define DMC_DRAM_TCL ((0x0004 << 2) + 0xfe024400)
+ //bit 5:0 tCL/tRL. read latency.
+#define DMC_DRAM_TCWL ((0x0005 << 2) + 0xfe024400)
+ //bit 5:0. CWL: write latency.
+#define DMC_DRAM_TRAS ((0x0006 << 2) + 0xfe024400)
+ //bit 7:0. tRAS. minimum active to precharge time for same bank.
+#define DMC_DRAM_TRC ((0x0007 << 2) + 0xfe024400)
+ //bit 7:0. tRC. minimum active to active time for same bank.
+#define DMC_DRAM_TRCD ((0x0008 << 2) + 0xfe024400)
+ //bit 7:0 tRCD active to read/write timing for same bank.
+#define DMC_DRAM_TRRD ((0x0009 << 2) + 0xfe024400)
+ //bit 21:16. tRRD_l active bank A to active B in same band group for DDR4.
+ //bit 5:0. tRRD/tRRD_s active bank A to active bank b time.
+ //tRRD_s: active bank A to active bank b in different bank grousp for DDR4.
+#define DMC_DRAM_TFAW ((0x000a << 2) + 0xfe024400)
+ //bit 8:0 tFAW. four active command windows
+#define DMC_DRAM_TRTP ((0x000b << 2) + 0xfe024400)
+ //bit 5:0 tRTP.
+#define DMC_DRAM_TWR ((0x000c << 2) + 0xfe024400)
+ //bit 5:0 tWR.
+#define DMC_DRAM_TWTR ((0x000d << 2) + 0xfe024400)
+ //bit 5:0 tWTR.
+#define DMC_DRAM_TCCD ((0x000e << 2) + 0xfe024400)
+ //bit 19:16. tCCD/tCCD_l.
+ //bit 3:0 tCCD/tCCD_s read to read command time or write to write command time.
+#define DMC_DRAM_TEXSR ((0x000f << 2) + 0xfe024400)
+ //bit 9:0. tEXSR. EXIT SELF-REFRESH to read/write command.
+#define DMC_DRAM_TXS ((0x0010 << 2) + 0xfe024400)
+ //bit 9:0 tXS. EXIT SELF_REFRESH to other command time
+#define DMC_DRAM_TXP ((0x0011 << 2) + 0xfe024400)
+ //bit 3:0. tXP. EXIT power down to other command time
+#define DMC_DRAM_TXPDLL ((0x0012 << 2) + 0xfe024400)
+ //bit 9:0. tXPDLL, EXIT power down to read/write command time(need to relock PLL).
+#define DMC_DRAM_TZQCS ((0x0013 << 2) + 0xfe024400)
+ //bit 11:0. ZQCS command to other command time.
+#define DMC_DRAM_TCKSRE ((0x0014 << 2) + 0xfe024400)
+ //bit 4:0. enter self refresh to disable clock time.
+#define DMC_DRAM_TCKSRX ((0x0015 << 2) + 0xfe024400)
+ //bit 4:0. enable clock to exit self refresh time.
+#define DMC_DRAM_TCKE ((0x0016 << 2) + 0xfe024400)
+ //bit 4:0. CKE high or low minimum time.
+#define DMC_DRAM_TMOD ((0x0017 << 2) + 0xfe024400)
+ //bit 4:0 tMOD. MRR/MRW to other command time.
+#define DMC_DRAM_TDQS ((0x0018 << 2) + 0xfe024400)
+ //bit 3:0 tDQS. the delay to access different rank.
+#define DMC_DRAM_TRSTL ((0x0019 << 2) + 0xfe024400)
+ //not used.
+#define DMC_DRAM_TZQLAT ((0x001a << 2) + 0xfe024400)
+ //bit 5:0 ZQ LATCH command to other comand timing in LPDDR4 mode.
+#define DMC_DRAM_TMRR ((0x001b << 2) + 0xfe024400)
+ //bit 7:0 tMRR not used in DMC. not support MR READ.
+#define DMC_DRAM_TCKESR ((0x001c << 2) + 0xfe024400)
+ //bit 9:0 tCKESR. CKE low minimum pulse in self refresh mode.
+#define DMC_DRAM_TDPD ((0x001d << 2) + 0xfe024400)
+ //not support.
+#define DMC_DRAM_DFITCTRLDELAY ((0x001e << 2) + 0xfe024400)
+ //bit 3:0. DFI_t_ctrldealy
+#define DMC_DRAM_DFITPHYWRDATA ((0x001f << 2) + 0xfe024400)
+ //bit 5:0. dfi_t_phy_wrdata.
+#define DMC_DRAM_DFITPHYWRLAT ((0x0020 << 2) + 0xfe024400)
+ //bit 5:0. dfi_t_phy_wrlat. in DDR3/4/LPDDR3 mode: WL -5. in LPDDR4 mode: WL -5 + 2.
+#define DMC_DRAM_DFITRDDATAEN ((0x0021 << 2) + 0xfe024400)
+ //bit 5:0. dfi_t_rddata_en. in DDR3/4/LPDDR3 mode: RL -5. in LPDDR4 mode : RL -5 + 1.
+#define DMC_DRAM_DFITPHYRDLAT ((0x0022 << 2) + 0xfe024400)
+ //bit 5:0. dfi_t_rdlat.
+#define DMC_DRAM_DFITCTRLUPDMIN ((0x0023 << 2) + 0xfe024400)
+ //bit 7:0. CTRLUPD_MIN minimux clock cycle to maintain CTRLUPD_REQ.
+#define DMC_DRAM_DFITCTRLUPDMAX ((0x0024 << 2) + 0xfe024400)
+ //bit 7:0 CTRLUPD_MAX. maxmum clock cycle to maintain CTRLUPD_REQ if no CTRLUPD_ACK response.
+#define DMC_DRAM_DFITMSTRRESP ((0x0025 << 2) + 0xfe024400)
+ //not used.
+#define DMC_DRAM_DFITREFMSKI ((0x0026 << 2) + 0xfe024400)
+ //not used.
+#define DMC_DRAM_DFITCTRLUPDI ((0x0027 << 2) + 0xfe024400)
+ //not used.
+#define DMC_DRAM_DFITDRAMCLK ((0x0028 << 2) + 0xfe024400)
+//bit 17 dram clk1 enable.
+//bit 16 dram clk0 enable.
+//bit 15:8 DRAM CLK disable waiting time
+//bit 7:0 DRAM CLK enable enable timer
+#define DMC_DRAM_DFITLPRESP ((0x002a << 2) + 0xfe024400)
+ //bit 3:0. dfi_lp_ctrl_req response time. after dfi_lp_ctrl_req asserted, and after response time if there's still no dfi_lp_ack respone, then drop the dfi_lp_ctrl_req.
+#define DMC_DRAM_DFITPHYMSTR ((0x002b << 2) + 0xfe024400)
+ //bit 15 1: enable DFIPHYMASTER INTERFACE 0 disable DFIPHYMSTR en response.
+ // always 0 we would use DFI_RETRAIN function for PHY retrain required from LPDDR4.
+#define DMC_DRAM_TCKECK ((0x002c << 2) + 0xfe024400)
+ //bit 4:0. tCKECK from CKE low to assert dfi_dram_clk_disable time. this time + dfi_t_ctrl_delay
+#define DMC_DRAM_TREFI ((0x002d << 2) + 0xfe024400)
+ //write this register will update the auto refresh related register to the auto refresh control logic.
+ //bit 31:24: tZQCI dmc send zqci period. unit is how much auto refresh period.
+ //bit 23:16 pvti dmc send dfi_ctrlupd_req period. unit is one auto refresh period.
+ //bit 15:8. tREFI.dmc send auto refresh command period. unit is 100ns.
+ //bit 7:0. t100ns period. unit is dmc clock cycles
+#define DMC_DRAM_TSR ((0x002e << 2) + 0xfe024400)
+ //bit 5:0 tSR. self resfresh enter to exit time.
+#define DMC_DRAM_TCCDMW ((0x002f << 2) + 0xfe024400)
+ //bit 5:0. 4*tCCD in LPDDR4 mask write.
+#define DMC_DRAM_TESCKE ((0x0030 << 2) + 0xfe024400)
+ //bit 5:0 tESCKE. enter self refresh to power time for LPDDR4.
+#define DMC_DRAM_TREFI_DDR3 ((0x0031 << 2) + 0xfe024400)
+ //7:0. 8*DDR3 SDRAM tREFI time . the unit is t100ns. use this to check in 8*tREFI time, the DMC should sent more than 16 auto REFRESH command.
+#define DMC_DRAM_TZQCAL ((0x0032 << 2) + 0xfe024400)
+ //7:0. ZQCAL for LPDDR4.
+#define DMC_DRAM_T10US ((0x0033 << 2) + 0xfe024400)
+ //10us clock cycle number used for LP2 mode.
+#define DMC_DRAM_TMRRI ((0x0034 << 2) + 0xfe024400)
+//bit 7:0 tMRRI for MRR
+//timing paramter for frequency set 1.
+#define DMC_NFQ_TMRD ((0x0040 << 2) + 0xfe024400)
+#define DMC_NFQ_TRFC ((0x0041 << 2) + 0xfe024400)
+#define DMC_NFQ_TRP ((0x0042 << 2) + 0xfe024400)
+#define DMC_NFQ_TRTW ((0x0043 << 2) + 0xfe024400)
+#define DMC_NFQ_TCL ((0x0044 << 2) + 0xfe024400)
+#define DMC_NFQ_TCWL ((0x0045 << 2) + 0xfe024400)
+#define DMC_NFQ_TRAS ((0x0046 << 2) + 0xfe024400)
+#define DMC_NFQ_TRC ((0x0047 << 2) + 0xfe024400)
+#define DMC_NFQ_TRCD ((0x0048 << 2) + 0xfe024400)
+#define DMC_NFQ_TRRD ((0x0049 << 2) + 0xfe024400)
+#define DMC_NFQ_TFAW ((0x004a << 2) + 0xfe024400)
+#define DMC_NFQ_TRTP ((0x004b << 2) + 0xfe024400)
+#define DMC_NFQ_TWR ((0x004c << 2) + 0xfe024400)
+#define DMC_NFQ_TWTR ((0x004d << 2) + 0xfe024400)
+#define DMC_NFQ_TCCD ((0x004e << 2) + 0xfe024400)
+#define DMC_NFQ_TEXSR ((0x004f << 2) + 0xfe024400)
+#define DMC_NFQ_TXS ((0x0050 << 2) + 0xfe024400)
+#define DMC_NFQ_TXP ((0x0051 << 2) + 0xfe024400)
+#define DMC_NFQ_TXPDLL ((0x0052 << 2) + 0xfe024400)
+#define DMC_NFQ_TZQCS ((0x0053 << 2) + 0xfe024400)
+#define DMC_NFQ_TCKSRE ((0x0054 << 2) + 0xfe024400)
+#define DMC_NFQ_TCKSRX ((0x0055 << 2) + 0xfe024400)
+#define DMC_NFQ_TCKE ((0x0056 << 2) + 0xfe024400)
+#define DMC_NFQ_TMOD ((0x0057 << 2) + 0xfe024400)
+#define DMC_NFQ_TDQS ((0x0058 << 2) + 0xfe024400)
+#define DMC_NFQ_TRSTL ((0x0059 << 2) + 0xfe024400)
+#define DMC_NFQ_TZQLAT ((0x005a << 2) + 0xfe024400)
+#define DMC_NFQ_TMRR ((0x005b << 2) + 0xfe024400)
+#define DMC_NFQ_TCKESR ((0x005c << 2) + 0xfe024400)
+#define DMC_NFQ_TDPD ((0x005d << 2) + 0xfe024400)
+#define DMC_NFQ_DFITCTRLDELAY ((0x005e << 2) + 0xfe024400)
+#define DMC_NFQ_DFITPHYWRDATA ((0x005f << 2) + 0xfe024400)
+#define DMC_NFQ_DFITPHYWRLAT ((0x0060 << 2) + 0xfe024400)
+#define DMC_NFQ_DFITRDDATAEN ((0x0061 << 2) + 0xfe024400)
+#define DMC_NFQ_DFITPHYRDLAT ((0x0062 << 2) + 0xfe024400)
+#define DMC_NFQ_DFITCTRLUPDMIN ((0x0063 << 2) + 0xfe024400)
+#define DMC_NFQ_DFITCTRLUPDMAX ((0x0064 << 2) + 0xfe024400)
+#define DMC_NFQ_DFITMSTRRESP ((0x0065 << 2) + 0xfe024400)
+#define DMC_NFQ_DFITREFMSKI ((0x0066 << 2) + 0xfe024400)
+#define DMC_NFQ_DFITCTRLUPDI ((0x0067 << 2) + 0xfe024400)
+#define DMC_NFQ_DFITDRAMCLK ((0x0068 << 2) + 0xfe024400)
+#define DMC_NFQ_DFITLPRESP ((0x006a << 2) + 0xfe024400)
+#define DMC_NFQ_DFITPHYMSTR ((0x006b << 2) + 0xfe024400)
+#define DMC_NFQ_TCKECK ((0x006c << 2) + 0xfe024400)
+#define DMC_NFQ_TREFI ((0x006d << 2) + 0xfe024400)
+#define DMC_NFQ_TSR ((0x006e << 2) + 0xfe024400)
+#define DMC_NFQ_TCCDMW ((0x006f << 2) + 0xfe024400)
+#define DMC_NFQ_TESCKE ((0x0070 << 2) + 0xfe024400)
+#define DMC_NFQ_TREFI_DDR3 ((0x0071 << 2) + 0xfe024400)
+#define DMC_NFQ_TZQCAL ((0x0072 << 2) + 0xfe024400)
+#define DMC_NFQ_T10US ((0x0073 << 2) + 0xfe024400)
+#define DMC_NFQ_TMRRI ((0x0074 << 2) + 0xfe024400)
+#define DMC_DRAM_DFITPHYUPDTYPE0 ((0x0080 << 2) + 0xfe024400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 0.
+#define DMC_DRAM_DFITPHYUPDTYPE1 ((0x0081 << 2) + 0xfe024400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 1.
+#define DMC_DRAM_DFITPHYUPDTYPE2 ((0x0082 << 2) + 0xfe024400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 2.
+#define DMC_DRAM_DFITPHYUPDTYPE3 ((0x0083 << 2) + 0xfe024400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 3.
+#define DMC_DRAM_DFIODTCFG ((0x0084 << 2) + 0xfe024400)
+ //bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity.
+ //bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1.
+ //bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0.
+ //bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1.
+ //bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0.
+ //bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity.
+ //bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0.
+ //bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1.
+ //bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0.
+ //bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1.
+#define DMC_DRAM_DFIODTCFG1 ((0x0085 << 2) + 0xfe024400)
+ //bit 27:24 ODT length for BL8 read transfer.
+ //bit 19:16. ODT length for BL8 write transfer.
+ //bit 12:8. ODT latency for reads. suppose to be 0.
+ //bit 4:0. ODT latency for writes. suppose to be 0.
+#define DMC_DRAM_MCFG ((0x0086 << 2) + 0xfe024400)
+ //bit 16. send refresh command after finish frequency change. 1 : enable. 0 : disable.
+ //bit 15. send refresh command after finish LPDDR4 retraining. 1 : enable. 0 : disable.
+ //bit 14. 1: cke init low. 0 : cke init high.
+ //bit 13 1: dbi write enable only for LPDDR4.
+ //bit 12. 1: dbi read inversion. 0: dbi read high inversion.
+ //bit 11. 1: dbi read enable. 0: dbi not enabled.
+ //bit 10 1: enable staggered chip select for 2 ranks DRAM.
+ //bit 9 1: enable send auto refresh command to DDR SDRAM when PCTL is in CFG/STOP state.
+ //bit 8 send auto refr cmd before enter register triggered self refresh
+ //bit 7 send auto refr cmd after exit regsiter triggered self refresh mode.
+ //bit 6 disable dram clock after enter register triggered self refresh.
+ //bit 5 send DFI_LP_REQ to PHY after enter register triggered elf refresh mode.
+ //bit 4 send DRAM to power down mode after enter self refresh. ONLY for LPDDR4.
+ //bit 3 send DFI_CTRLUPD_REQ after exit register triggered self refresh.
+ //bit 2 send ZQCS command after exit register triggered self refresh.
+ //bit 1 enable PHY triggered DFI_PHYUPD_REQ.
+ //bit 0 2T mode. always 1 in DDR3/4 mode.
+#define DMC_DRAM_DFI_CTRL ((0x0089 << 2) + 0xfe024400)
+ //bit 20 siu_dfi1_phymstr_ack_en
+ //bit 19 siu_dfi_phymstr_req_and
+ //bit 18 siu_dfi_phymstr_req_or
+ //bit 17 siu_dfi_phymstr_type_sel
+ //bit 16 siu_dfi_phymstr_cs_sel
+ //bit 15 siu_dfi1_lp_en
+ //bit 14 siu_dfi_lp_ack_and
+ //bit 13 siu_dfi_lp_ack_or
+ //bit 12 siu_dfi1_init_start_en
+ //bit 11 siu_dfi_init_com_and
+ //bit 10 siu_dfi_init_com_or
+ //bit 9 siu_dfi1_freq_en
+ //bit 8 siu_dfi1_dram_clk_dis_en
+ //bit 7 siu_dfi_phyupd_type_sel
+ //bit 6 siu_dfi1_phyupd_ack_en
+ //bit 5 siu_dfi_phyupd_req_and
+ //bit 4 siu_dfi_phyupd_req_or
+ //bit 3 siu_dfi_ctrlupd_ack_and
+ //bit 2 siu_dfi_ctrlupd_ack_or
+ //bit 1 siu_dfi1_ctrlupd_req_en
+ //bit 0 siu_dfi1_cmd_en
+#define DMC_DRAM_DFIINITCFG ((0x008a << 2) + 0xfe024400)
+ //bit 31. dfi_init_complete status. read only.
+ //bit 15:14. Frequency set 1 dfi_freq_ratio value.
+ //bit 12:8 Frequency set 1 dfi_freq value.
+ //bit 7:6 Frequency set 0 dfi_freq_ratio value.
+ //bit 5:1 Frequency set 0 dfi_freq value.
+ //bit 0. dfi_init_start value can be use manually config dfi_init_start signal.
+#define DMC_DRAM_ZQ_CTRL ((0x008b << 2) + 0xfe024400)
+ // only 1 bit can be enabled at same time.
+ //bit 2 send ZQCS command to RANK0 then send comand to RANK1.
+ //bit 1. send ZQCS command to both RANK0 and RANK1 together.
+ //bit 0. send ZQCS command to only rank0.
+#define DMC_DRAM_APD_CTRL ((0x008c << 2) + 0xfe024400)
+ //bit 19:16 DFI_LP_WAKEUP value in APD DFI_LP_REQ mode
+ //bit 12 1: exit power down slow mode(waiting PLL LOCK). 0 : fast mode.
+ //bit 11 enable DFI_LP_REQ when enter Auto power down mode.
+ //bit 10 disable DFI_clk_disable when enter auto power down mode.
+ //bit 9:0 0 disable auto power down mode.
+ //non zero value to enable auto power down when DMC is in idle state for this number of clock cycles.
+#define DMC_DRAM_ASR_CTRL ((0x008d << 2) + 0xfe024400)
+ //bit [23:20] DFI_LP_WAKEUP value in self refresh DFI_LP_REQ mode.
+ //bit 17 : send REFRESH command after exit from auto self refersh mode(ASR).
+ //bit 16 : send REFERSH command before enter to Auto self refresh mode(ASR).
+ //bit 15 : send ZQCS command after exit from Auto self refresh mode(ASR).
+ //bit 14 : send dfi_ctrl_upd after exit from ASR mode
+ //bit 13 : send power down command when enter ASR mode. //for LPDDR4 only.
+ //bit 12 : set the PHY enter LP2 mode after enter ASR mode.
+ //bit 11 : send DFI_LP_REQ after enter ASR mode.
+ //bit 10 : set DFI_CLK_DISABLE after enter ASR mode.
+ //bit 9:0. 0 disable auto ASR mode.
+ // Non-zero valule enable ASR mode. when DMC is in idle state for this number of clock cycles, the DMC will enter ASR mode.
+#define DMC_DRAM_PHYMSTR_CTRL ((0x0090 << 2) + 0xfe024400)
+ //not used in G12A. should be all 0.
+#define DMC_DRAM_DFIODTRANKMAP ((0x0091 << 2) + 0xfe024400)
+ //not used in G12A.
+#define DMC_DRAM_REFR_CTRL ((0x0092 << 2) + 0xfe024400)
+ //bit 17:8 auto refresh request pending cnt if there's page hit request.
+ //bit 6 Disabled auto refresh command if over 16 auto refresh command sent in 2 TREFI_DDR3 period
+ //bit 5 enable dmc send ZQCS command .
+ //bit 4. enable dmc send DFI_CTRUPD_REQ.
+ //bit 3:1. how many refresh command send for one period. = this number + 1
+ //bit 0. enable dmc send auto refresh command.
+#define DMC_DRAM_FREQ_CTRL ((0x0093 << 2) + 0xfe024400)
+//bit 31 . wiret 1 to change freqency read 0: finished.
+//bit 30:9. not used.
+//bit 9. 1 : FREQ MRW done. let FREQ change machine continue.
+//bit 8 FREQ WAIT. 1 when freq change finishes, state machine stop at self refresh state in case there's something need to handle.
+ // 0 after freq change finishes the state machine go back to access state.
+//bit 7 when change PLL setting, disable dmc clock
+//bit 6 when change PLL setting, disable PHY DfiClk and DfiCtlClk.
+//bit 5 check vpu_sleep_en ==1 when do FREQ change. if vpu_sleep_en == 0, just wait.
+//bit 4 nxt frequency selection. 1 = freq1. 0 = freq0.
+//bit 3:1. not used.
+//bit 0. current frequency selection.
+#define DMC_DRAM_SCFG ((0x0094 << 2) + 0xfe024400)
+ // bit 2:0 only one bit can be high at same time.
+ // bit 2 1 : to ask PCTL enter ACCESS STATE. 0 : deassert the request.
+ // bit 1 1 : to ask PCTL enter SELF REFRESH STATE. 0 : deassert the request.
+ // bit 0 1 : to ask PCTL enter STOP/CONFIG STATE . 0 : deassert the request.
+#define DMC_DRAM_STAT ((0x0095 << 2) + 0xfe024400)
+ //bit 31 rd latency error. 1: means after dfiphytrdlat cycles, the read data still not back.
+ //bit 28:24 dram_sr_state
+ //bit 23:20 stop_st
+ //bit 19:15 sleep_st
+ //bit 14:12 ACCESS STATUS 0 : ACCESS is in normal working mode.
+ //1 : ACCESS sending precharege command.
+ //2 : ACCESS sending AUTO REFESH command.
+ //3 : ACCESS sending DIF_CTRLUPD_REQ command.
+ //4 : ACCESS sending ZQCS command to DDR DRAM(ZQCAL for LPDDR4).
+ //5 : ACCESS sending ZQLATCH command to LPDDR4 only.
+ //bit 11:8 APD STATUS: 0 : APD_IDLE
+ //1 : APD sending PRECHARGE command
+ //2 : APD sending CKE low command
+ //3 : APD sending DISABLE DRAM CLOCK command
+ //4 : APD sending DFI_LP_CTRL_REQ
+ //5 : APD in Auto Power down mode.
+ //6 : APD deassert DFI_LP_CTRL_REQ
+ //7 : APD sending enable DRAM CLOCK command
+ //8 : APD sending out CKE high command.
+ //bit 7:4: DRAM_STATUS: 0 : DRAM IDLE
+ //1 : DRAM_STOP/DRAM_CFG
+ //2 : DRAM_ACCESS
+ //3 : DRAM_SLEEP
+ //4 : DRAM APD(AUTO POWER DOWN).
+ //5 : IDLE -> STOP/CONFIG
+ //6 : STOP -> SLEEP
+ //7 : STOP -> ACCESS
+ //8 : ACCESS -> SLEEP.
+ //9 : ACCESS -> STOP
+ //A : ACCESS -> APD
+ //B : SLEEP -> STOP
+ //C : SLEEP -> ACCESS
+ //D : APD -> ACCESS
+ //bit 3 reserved.
+ //bit 2 1 : DRAM enter normal working state.
+ //bit 1 1 : DRAM enter sleep state. self refresh state.
+ //bit 0 1 : dram enter cfg state.
+#define DMC_DRAM_STAT1 ((0x0096 << 2) + 0xfe024400)
+ //bit 11:8 freq_st.
+ //bit 7:5 train_st
+ //bit 4:0 dram_phy_st
+#define DMC_PHY_RETRAINING_CTRL ((0x0097 << 2) + 0xfe024400)
+ //bit 31 : phy_retraining enable.
+ //bit 30 : check vpu sleep_en.
+ //bit 25:24 : retraining dfi_freq[4:3], the [2:0] bit still use the dfi_freq bits to keep the frequency.
+ //bit 23:0: retraining period unit : 100ns.
+#define DMC_DFI_ERR_STAT ((0x0098 << 2) + 0xfe024400)
+ //LPDDR4 PHY DFI error infomation.
+ //bit 31:20. not used.
+ //bit 9. ddr0_dfi_error
+ //bit 8:5 ddr0_dfi_error_info.
+ //bit 4. ddr1_dfi_error.
+ //bit 3:0. ddr1_dfi_error_info.
+#define DMC_LP2_TIMER ((0x009a << 2) + 0xfe024400)
+//bit 15:0. timer setting to measure how long the chip is entered LP2 mode.
+//this timer is 40bits counter with DMC PCLK.
+//we use the high 16bits to compare this register. if the counter is large than this number, that means the PHY need addition 10us after wakeup the PHY and before exit self_refresh mode.
+#define DMC_DRAM_DFI_SWAP_0 ((0x00a0 << 2) + 0xfe024400)
+ //bit 5:0. dfi_act_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_1 ((0x00a1 << 2) + 0xfe024400)
+ //bit 5:0. dfi_ras_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_2 ((0x00a2 << 2) + 0xfe024400)
+ //bit 5:0. dfi_cas_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_3 ((0x00a3 << 2) + 0xfe024400)
+ //bit 5:0. dfi_we_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_4 ((0x00a4 << 2) + 0xfe024400)
+ //bit 5:0. dfi_bg0 function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_5 ((0x00a5 << 2) + 0xfe024400)
+ //bit 5:0. dfi_bg[1] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_6 ((0x00a6 << 2) + 0xfe024400)
+ //bit 5:0. dfi_ba[0] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_7 ((0x00a7 << 2) + 0xfe024400)
+ //bit 5:0. dfi_ba[1] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_8 ((0x00a8 << 2) + 0xfe024400)
+ //bit 5:0. dfi_ba[2] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_9 ((0x00a9 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[0] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_10 ((0x00aa << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[1] function select
+#define DMC_DRAM_DFI_SWAP_11 ((0x00ab << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[2] function select
+#define DMC_DRAM_DFI_SWAP_12 ((0x00ac << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[3] function select
+#define DMC_DRAM_DFI_SWAP_13 ((0x00ad << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[4] function select
+#define DMC_DRAM_DFI_SWAP_14 ((0x00ae << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[5] function select
+#define DMC_DRAM_DFI_SWAP_15 ((0x00af << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[6] function select
+#define DMC_DRAM_DFI_SWAP_16 ((0x00b0 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[7] function select
+#define DMC_DRAM_DFI_SWAP_17 ((0x00b1 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[8] function select
+#define DMC_DRAM_DFI_SWAP_18 ((0x00b2 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[9] function select
+#define DMC_DRAM_DFI_SWAP_19 ((0x00b3 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[10] function select
+#define DMC_DRAM_DFI_SWAP_20 ((0x00b4 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[11] function select
+#define DMC_DRAM_DFI_SWAP_21 ((0x00b5 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[12] function select
+#define DMC_DRAM_DFI_SWAP_22 ((0x00b6 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[13] function select
+#define DMC_DRAM_DFI_SWAP_23 ((0x00b7 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[14] function select
+#define DMC_DRAM_DFI_SWAP_24 ((0x00b8 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[15] function select
+#define DMC_DRAM_DFI_SWAP_25 ((0x00b9 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[16] function select
+#define DMC_DRAM_DFI_SWAP_26 ((0x00bb << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[17] function select
+//`endif
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh
+//
+//`ifdef DMC_STICKY_REG_DEFINE
+//`else
+//`define DMC_STICKY_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfe024800
+// -----------------------------------------------
+//`define DMC_STICKY_REG_BASE 32'hfe024800
+//those register is for software save some tempary value. and because it's in RAM. it won't lose if DMC get reseted.
+#define DMC_STICKY_0 ((0x0000 << 2) + 0xfe024800)
+#define DMC_STICKY_1 ((0x0001 << 2) + 0xfe024800)
+#define DMC_STICKY_2 ((0x0002 << 2) + 0xfe024800)
+#define DMC_STICKY_3 ((0x0003 << 2) + 0xfe024800)
+#define DMC_STICKY_4 ((0x0004 << 2) + 0xfe024800)
+#define DMC_STICKY_5 ((0x0005 << 2) + 0xfe024800)
+#define DMC_STICKY_6 ((0x0006 << 2) + 0xfe024800)
+#define DMC_STICKY_7 ((0x0007 << 2) + 0xfe024800)
+#define DMC_STICKY_8 ((0x0008 << 2) + 0xfe024800)
+#define DMC_STICKY_9 ((0x0009 << 2) + 0xfe024800)
+#define DMC_STICKY_10 ((0x000a << 2) + 0xfe024800)
+#define DMC_STICKY_11 ((0x000b << 2) + 0xfe024800)
+#define DMC_STICKY_12 ((0x000c << 2) + 0xfe024800)
+#define DMC_STICKY_13 ((0x000d << 2) + 0xfe024800)
+#define DMC_STICKY_14 ((0x000e << 2) + 0xfe024800)
+#define DMC_STICKY_15 ((0x000f << 2) + 0xfe024800)
+#define DMC_STICKY_16 ((0x0010 << 2) + 0xfe024800)
+#define DMC_STICKY_17 ((0x0011 << 2) + 0xfe024800)
+#define DMC_STICKY_18 ((0x0012 << 2) + 0xfe024800)
+#define DMC_STICKY_19 ((0x0013 << 2) + 0xfe024800)
+#define DMC_STICKY_20 ((0x0014 << 2) + 0xfe024800)
+#define DMC_STICKY_21 ((0x0015 << 2) + 0xfe024800)
+#define DMC_STICKY_22 ((0x0016 << 2) + 0xfe024800)
+#define DMC_STICKY_23 ((0x0017 << 2) + 0xfe024800)
+#define DMC_STICKY_24 ((0x0018 << 2) + 0xfe024800)
+#define DMC_STICKY_25 ((0x0019 << 2) + 0xfe024800)
+#define DMC_STICKY_26 ((0x001a << 2) + 0xfe024800)
+#define DMC_STICKY_27 ((0x001b << 2) + 0xfe024800)
+#define DMC_STICKY_28 ((0x001c << 2) + 0xfe024800)
+#define DMC_STICKY_29 ((0x001d << 2) + 0xfe024800)
+#define DMC_STICKY_30 ((0x001e << 2) + 0xfe024800)
+#define DMC_STICKY_31 ((0x001f << 2) + 0xfe024800)
+#define DMC_STICKY_32 ((0x0020 << 2) + 0xfe024800)
+#define DMC_STICKY_33 ((0x0021 << 2) + 0xfe024800)
+#define DMC_STICKY_34 ((0x0022 << 2) + 0xfe024800)
+#define DMC_STICKY_35 ((0x0023 << 2) + 0xfe024800)
+#define DMC_STICKY_36 ((0x0024 << 2) + 0xfe024800)
+#define DMC_STICKY_37 ((0x0025 << 2) + 0xfe024800)
+#define DMC_STICKY_38 ((0x0026 << 2) + 0xfe024800)
+#define DMC_STICKY_39 ((0x0027 << 2) + 0xfe024800)
+#define DMC_STICKY_40 ((0x0028 << 2) + 0xfe024800)
+#define DMC_STICKY_41 ((0x0029 << 2) + 0xfe024800)
+#define DMC_STICKY_42 ((0x002a << 2) + 0xfe024800)
+#define DMC_STICKY_43 ((0x002b << 2) + 0xfe024800)
+#define DMC_STICKY_44 ((0x002c << 2) + 0xfe024800)
+#define DMC_STICKY_45 ((0x002d << 2) + 0xfe024800)
+#define DMC_STICKY_46 ((0x002e << 2) + 0xfe024800)
+#define DMC_STICKY_47 ((0x002f << 2) + 0xfe024800)
+#define DMC_STICKY_48 ((0x0030 << 2) + 0xfe024800)
+#define DMC_STICKY_49 ((0x0031 << 2) + 0xfe024800)
+#define DMC_STICKY_50 ((0x0032 << 2) + 0xfe024800)
+#define DMC_STICKY_51 ((0x0033 << 2) + 0xfe024800)
+#define DMC_STICKY_52 ((0x0034 << 2) + 0xfe024800)
+#define DMC_STICKY_53 ((0x0035 << 2) + 0xfe024800)
+#define DMC_STICKY_54 ((0x0036 << 2) + 0xfe024800)
+#define DMC_STICKY_55 ((0x0037 << 2) + 0xfe024800)
+#define DMC_STICKY_56 ((0x0038 << 2) + 0xfe024800)
+#define DMC_STICKY_57 ((0x0039 << 2) + 0xfe024800)
+#define DMC_STICKY_58 ((0x003a << 2) + 0xfe024800)
+#define DMC_STICKY_59 ((0x003b << 2) + 0xfe024800)
+#define DMC_STICKY_60 ((0x003c << 2) + 0xfe024800)
+#define DMC_STICKY_61 ((0x003d << 2) + 0xfe024800)
+#define DMC_STICKY_62 ((0x003e << 2) + 0xfe024800)
+#define DMC_STICKY_63 ((0x003f << 2) + 0xfe024800)
+//`endif
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc_clk_freq/rtl/dmc_clk_freq.vh
+//
+//`ifdef DMC_FREQ_REG_DEFINE
+//`else
+//`define DMC_FREQ_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfe024c00
+// -----------------------------------------------
+//`define DMC_FREQ_REG_BASE 32'hfe024c00
+#define AM_DDR_PLL_CNTL0 ((0x0000 << 2) + 0xfe024c00)
+ //bit 29 : dpll_reset.
+ //bit 28 : dpll_en.
+ //bit 27:26 : dpll_clk_en
+ //bit
+ //bit 20:19 : od1
+ //bit 18:16 : od
+ //bit 14:10 : dpll_ref_div_n
+ //bit 8:0 : dpll_int_num
+#define AM_DDR_PLL_CNTL1 ((0x0001 << 2) + 0xfe024c00)
+ //bit 18:0 : ddr_dpll_frac
+#define AM_DDR_PLL_CNTL2 ((0x0002 << 2) + 0xfe024c00)
+ //bit 22:20 : fref_sel
+ //bit 17:16 : os_ssc
+ //bit 15:12 : ssc_str_m
+ //bit 8 : ssc_en
+ //bit 7:4 : ssc_dep_sel
+ //bit 1:0 : dpll ss_mode.
+#define AM_DDR_PLL_CNTL3 ((0x0003 << 2) + 0xfe024c00)
+ //bit 31 : afc bypass
+ //bit 30 : afc clk sel
+ //bit 29 : code new
+ //bit 28 : dco_m_en
+ //bit 27 : dco_sdm_en
+ //bit 26 : div2
+ //bit 25 : div mode
+ //bit 24 : fast_lock mode
+ //bit 23 : fb_pre_div
+ //bit 22 : filter_mode
+ //bit 21 : fix_en
+ //bit 20 : freq_shift_en
+ //bit 19 : load
+ //bit 18 : load_en
+ //bit 17 : lock_f
+ //bit 16 : pulse_width_en
+ //bit 15 : sdmnc_en
+ //bit 14 : sdmnc_mode
+ //bit 13 : sdmnc_range
+ //bit 12 : tdc_en
+ //bit 11 : tdc_mode_sel
+ //bit 10 : wait_en
+#define AM_DDR_PLL_CNTL4 ((0x0004 << 2) + 0xfe024c00)
+ //bit 1:0 : pfd_gain
+ //bit 7:4 : filter_pvt1
+ //bit 11:8 : filter pvt2
+ //bit 13:12 : acq_gain
+ //bit 18:16 : lambda0
+ //bit 22:20 : lambda1
+ //bit 26:24 : rou
+ //bit 30:28 : alpha
+#define AM_DDR_PLL_CNTL5 ((0x0005 << 2) + 0xfe024c00)
+ //bit 15:0 : reve
+ //bit 21:16 : lm_s
+ //bit 27:24 : lm_w
+ //bit 30:28 : adj_vco_ldo
+#define AM_DDR_PLL_CNTL6 ((0x0006 << 2) + 0xfe024c00)
+ //bit 15:0 : reve
+ //bit 21:16 : lm_s
+ //bit 27:24 : lm_w
+ //bit 30:28 : adj_vco_ldo
+#define AM_DDR_PLL_STS ((0x0007 << 2) + 0xfe024c00)
+ //bit 31 : DDR_PLL_LOCK
+ //bit 30:19 : not used.
+ //bit 18 : DDR_AFC_DONE
+ //bit 17 : DDR_PLL_LOCK
+ //bit 16:7 : DDR_DPLL_OUT_RSV
+ //bit 6:0 : DDR_SDMNC_MONITOR
+#define DDR_CLK_CNTL ((0x0008 << 2) + 0xfe024c00)
+ //bit 31 ddr_pll_clk enable. enable the clock from DDR_PLL to clock generateion.
+ // whenever change the DDR_PLL frequency, disable the clock, after the DDR_PLL locked, then enable it again.
+ //bit 30. ddr_pll_prod_test_en. enable the clock to clock/32 which to clock frequency measurement and production test pin.
+ //bit 29. not used.
+ //bit 28. clock generation logic soft reset. 0 = reset.
+ //bit 27. phy_4xclk phase inverter..
+ //bit 25. DDRPHY DfiClk/DfiCtlClk/DMC clock selection. 1: AM_PLL clk output /2. 0: directly output from AM_PLL .
+ //bit 24. enable AM_PLL CLK output /2 function. 1: enable. 0: disable. if try to use this clkoutput/2 function.
+ //bit 26. pll_freq divide/2. 1: use pll div/2 clock as the n_clk. 0: use pll clock as n_clk. this setting is used for the synopsys DDR PHY PLL fast lock mode.
+ //bit 2. enable dmc_clk.
+ //bit 1. enable LPDDR4-PHY DfiClk.
+ //bit 0. enable LPDDR4-PHY DfiCtlClk.
+#define DDR_PHY_CTRL ((0x0009 << 2) + 0xfe024c00)
+ // LPDDR4 power on reset need to special combination of PwrOkIn and phy_reset_n.
+ // please check the PHY PUB data book for detail.
+ //bit 4. DDR PHY PwrOkIn pin.
+ //bit 1. DDR PHY APB soft reset_n.
+ //bit 0. phy_reset_n.
+#define AM_DDR_PLL_FREQ1_OD ((0x000c << 2) + 0xfe024c00)
+ //freqency set 1 PLL OD and OD1 setting. when change to freqency 1 will use this setting.
+//frequency set 0 use original DDR_PLL_CNTL0 setting.
+ //bit 8 currunt FREQ selection. it can forced to change to select which freqency to select, or it can auto changed by FREQ change hardware.
+ //bit 5:4 OD1.
+ //bit 2:0. OD.
+//`endif
+//
+// Closing file: ../mmc_lp4/dmc_clk_freq/rtl/dmc_clk_freq.vh
+//
+//========================================================================
+// APB0_RESET_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000000
+// -----------------------------------------------
+#define RESETCTRL_RESET0 ((0x0000 << 2) + 0xfe000000)
+#define RESETCTRL_RESET1 ((0x0001 << 2) + 0xfe000000)
+#define RESETCTRL_RESET2 ((0x0002 << 2) + 0xfe000000)
+#define RESETCTRL_RESET0_LEVEL ((0x0010 << 2) + 0xfe000000)
+#define RESETCTRL_RESET1_LEVEL ((0x0011 << 2) + 0xfe000000)
+#define RESETCTRL_RESET2_LEVEL ((0x0012 << 2) + 0xfe000000)
+#define RESETCTRL_RESET0_MASK ((0x0020 << 2) + 0xfe000000)
+#define RESETCTRL_RESET1_MASK ((0x0021 << 2) + 0xfe000000)
+#define RESETCTRL_RESET2_MASK ((0x0022 << 2) + 0xfe000000)
+#define RESETCTRL_RESET_HOLD_CYC ((0x0030 << 2) + 0xfe000000)
+#define RESETCTRL_WATCHDOG_CTRL0 ((0x0040 << 2) + 0xfe000000)
+#define RESETCTRL_WATCHDOG_CTRL1 ((0x0041 << 2) + 0xfe000000)
+#define RESETCTRL_WATCHDOG_CNT ((0x0042 << 2) + 0xfe000000)
+#define RESETCTRL_WATCHDOG_CLR ((0x0043 << 2) + 0xfe000000)
+#define RESETCTRL_SEC_RESET0 ((0x0050 << 2) + 0xfe000000)
+#define RESETCTRL_SEC_RESET0_LEVEL ((0x0051 << 2) + 0xfe000000)
+#define RESETCTRL_SEC_RESET0_MASK ((0x0052 << 2) + 0xfe000000)
+//========================================================================
+// APB0_PAD_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000400
+// -----------------------------------------------
+#define PADCTRL_PIN_MUX_REG0 ((0x0000 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG1 ((0x0001 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG3 ((0x0003 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG4 ((0x0004 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG5 ((0x0005 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG6 ((0x0006 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG7 ((0x0007 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG8 ((0x0008 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG9 ((0x0009 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REGA ((0x000a << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REGB ((0x000b << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REGC ((0x000c << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REGD ((0x000d << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REGE ((0x000e << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REGF ((0x000f << 2) + 0xfe000400)
+#define PADCTRL_GPIO_IRQ_CTRL0 ((0x0010 << 2) + 0xfe000400)
+#define PADCTRL_GPIO_IRQ_CTRL1 ((0x0011 << 2) + 0xfe000400)
+#define PADCTRL_GPIO_IRQ_CTRL2 ((0x0012 << 2) + 0xfe000400)
+#define PADCTRL_GPIO_IRQ_CTRL3 ((0x0013 << 2) + 0xfe000400)
+#define PADCTRL_GPIO_IRQ_CTRL4 ((0x0014 << 2) + 0xfe000400)
+#define PADCTRL_WORLDSYNC_CTRL0 ((0x0018 << 2) + 0xfe000400)
+#define PADCTRL_GPIO_MSR_CTRL0 ((0x0019 << 2) + 0xfe000400)
+#define PADCTRL_MISC_CTRL0 ((0x001a << 2) + 0xfe000400)
+#define PADCTRL_GPIOD_I ((0x0020 << 2) + 0xfe000400)
+#define PADCTRL_GPIOD_O ((0x0021 << 2) + 0xfe000400)
+#define PADCTRL_GPIOD_OEN ((0x0022 << 2) + 0xfe000400)
+#define PADCTRL_GPIOD_PULL_EN ((0x0023 << 2) + 0xfe000400)
+#define PADCTRL_GPIOD_PULL_UP ((0x0024 << 2) + 0xfe000400)
+#define PADCTRL_GPIOD_DS ((0x0025 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_I ((0x0030 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_O ((0x0031 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_OEN ((0x0032 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_PULL_EN ((0x0033 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_PULL_UP ((0x0034 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400)
+#define PADCTRL_GPIOB_I ((0x0040 << 2) + 0xfe000400)
+#define PADCTRL_GPIOB_O ((0x0041 << 2) + 0xfe000400)
+#define PADCTRL_GPIOB_OEN ((0x0042 << 2) + 0xfe000400)
+#define PADCTRL_GPIOB_PULL_EN ((0x0043 << 2) + 0xfe000400)
+#define PADCTRL_GPIOB_PULL_UP ((0x0044 << 2) + 0xfe000400)
+#define PADCTRL_GPIOB_DS ((0x0045 << 2) + 0xfe000400)
+#define PADCTRL_GPIOC_I ((0x0050 << 2) + 0xfe000400)
+#define PADCTRL_GPIOC_O ((0x0051 << 2) + 0xfe000400)
+#define PADCTRL_GPIOC_OEN ((0x0052 << 2) + 0xfe000400)
+#define PADCTRL_GPIOC_PULL_EN ((0x0053 << 2) + 0xfe000400)
+#define PADCTRL_GPIOC_PULL_UP ((0x0054 << 2) + 0xfe000400)
+#define PADCTRL_GPIOC_DS ((0x0055 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_I ((0x0060 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_O ((0x0061 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_OEN ((0x0062 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_PULL_EN ((0x0063 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_PULL_UP ((0x0064 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_DS ((0x0065 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_DS_EXT ((0x0066 << 2) + 0xfe000400)
+#define PADCTRL_GPIOM_I ((0x0070 << 2) + 0xfe000400)
+#define PADCTRL_GPIOM_O ((0x0071 << 2) + 0xfe000400)
+#define PADCTRL_GPIOM_OEN ((0x0072 << 2) + 0xfe000400)
+#define PADCTRL_GPIOM_PULL_EN ((0x0073 << 2) + 0xfe000400)
+#define PADCTRL_GPIOM_PULL_UP ((0x0074 << 2) + 0xfe000400)
+#define PADCTRL_GPIOM_DS ((0x0075 << 2) + 0xfe000400)
+#define PADCTRL_GPIOA_I ((0x0080 << 2) + 0xfe000400)
+#define PADCTRL_GPIOA_O ((0x0081 << 2) + 0xfe000400)
+#define PADCTRL_GPIOA_OEN ((0x0082 << 2) + 0xfe000400)
+#define PADCTRL_GPIOA_PULL_EN ((0x0083 << 2) + 0xfe000400)
+#define PADCTRL_GPIOA_PULL_UP ((0x0084 << 2) + 0xfe000400)
+#define PADCTRL_GPIOA_DS ((0x0085 << 2) + 0xfe000400)
+#define PADCTRL_TESTN_I ((0x0090 << 2) + 0xfe000400)
+#define PADCTRL_TESTN_O ((0x0091 << 2) + 0xfe000400)
+#define PADCTRL_TESTN_OEN ((0x0092 << 2) + 0xfe000400)
+#define PADCTRL_TESTN_PULL_EN ((0x0093 << 2) + 0xfe000400)
+#define PADCTRL_TESTN_PULL_UP ((0x0094 << 2) + 0xfe000400)
+#define PADCTRL_TESTN_DS ((0x0095 << 2) + 0xfe000400)
+#define PADCTRL_MUTE_CTRL ((0x00a0 << 2) + 0xfe000400)
+//========================================================================
+// APB0_CLK_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000800
+// -----------------------------------------------
+#define CLKTREE_SYS_OSCIN_CTRL ((0x0000 << 2) + 0xfe000800)
+#define CLKTREE_RTC_BY_OSCIN_CTRL0 ((0x0001 << 2) + 0xfe000800)
+#define CLKTREE_RTC_BY_OSCIN_CTRL1 ((0x0002 << 2) + 0xfe000800)
+#define CLKTREE_RTC_CTRL ((0x0003 << 2) + 0xfe000800)
+#define CLKTREE_SYS_CLK_CTRL0 ((0x0004 << 2) + 0xfe000800)
+#define CLKTREE_AXI_CLK_CTRL0 ((0x0005 << 2) + 0xfe000800)
+#define CLKTREE_SYS_CLK_EN0 ((0x0006 << 2) + 0xfe000800)
+#define CLKTREE_SYS_CLK_EN1 ((0x0007 << 2) + 0xfe000800)
+#define CLKTREE_SYS_CLK_EN2 ((0x0008 << 2) + 0xfe000800)
+#define CLKTREE_AXI_CLK_EN ((0x0009 << 2) + 0xfe000800)
+#define CLKTREE_DSPA_CLK_EN ((0x000a << 2) + 0xfe000800)
+#define CLKTREE_DSPB_CLK_EN ((0x000b << 2) + 0xfe000800)
+#define CLKTREE_DSPA_CLK_CTRL0 ((0x000c << 2) + 0xfe000800)
+#define CLKTREE_DSPB_CLK_CTRL0 ((0x000d << 2) + 0xfe000800)
+#define CLKTREE_CLK12_24_CTRL ((0x000e << 2) + 0xfe000800)
+#define CLKTREE_GEN_CLK_CTRL ((0x000f << 2) + 0xfe000800)
+#define CLKTREE_TIMESTAMP_CTRL0 ((0x0010 << 2) + 0xfe000800)
+#define CLKTREE_TIMESTAMP_CTRL1 ((0x0011 << 2) + 0xfe000800)
+#define CLKTREE_TIMESTAMP_CTRL2 ((0x0012 << 2) + 0xfe000800)
+#define CLKTREE_TIMESTAMP_VAL0 ((0x0013 << 2) + 0xfe000800)
+#define CLKTREE_TIMESTAMP_VAL1 ((0x0014 << 2) + 0xfe000800)
+#define CLKTREE_TIMEBASE_CTRL0 ((0x0015 << 2) + 0xfe000800)
+#define CLKTREE_TIMEBASE_CTRL1 ((0x0016 << 2) + 0xfe000800)
+#define CLKTREE_SAR_ADC_CLK_CTRL ((0x0030 << 2) + 0xfe000800)
+#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800)
+#define CLKTREE_PWM_CLK_CD_CTRL ((0x0032 << 2) + 0xfe000800)
+#define CLKTREE_PWM_CLK_EF_CTRL ((0x0033 << 2) + 0xfe000800)
+#define CLKTREE_SPICC_CLK_CTRL ((0x0034 << 2) + 0xfe000800)
+#define CLKTREE_TS_CLK_CTRL ((0x0035 << 2) + 0xfe000800)
+#define CLKTREE_SPIFC_CLK_CTRL ((0x0036 << 2) + 0xfe000800)
+#define CLKTREE_USB_BUSCLK_CTRL ((0x0037 << 2) + 0xfe000800)
+#define CLKTREE_SD_EMMC_CLK_CTRL ((0x0038 << 2) + 0xfe000800)
+#define CLKTREE_CECA_CLK_CTRL0 ((0x0039 << 2) + 0xfe000800)
+#define CLKTREE_CECA_CLK_CTRL1 ((0x003a << 2) + 0xfe000800)
+#define CLKTREE_CECB_CLK_CTRL0 ((0x003b << 2) + 0xfe000800)
+#define CLKTREE_CECB_CLK_CTRL1 ((0x003c << 2) + 0xfe000800)
+#define CLKTREE_PSRAM_CLK_CTRL ((0x003d << 2) + 0xfe000800)
+#define CLKTREE_DMC_CLK_CTRL ((0x003e << 2) + 0xfe000800)
+#define CLKTREE_FCLK_DIV1_SEL ((0x003f << 2) + 0xfe000800)
+#define CLKTREE_TST_CTRL0 ((0x0040 << 2) + 0xfe000800)
+#define CLKTREE_WAVE_CLK_CTRL0 ((0x0041 << 2) + 0xfe000800)
+#define CLKTREE_WAVE_CLK_CTRL1 ((0x0042 << 2) + 0xfe000800)
+#define CLKTREE_JPEG_CLK_CTRL ((0x0043 << 2) + 0xfe000800)
+#define CLKTREE_MIPI_ISP_CLK_CTRL ((0x0044 << 2) + 0xfe000800)
+#define CLKTREE_NNA_CLK_CTRL ((0x0045 << 2) + 0xfe000800)
+#define CLKTREE_GDC_CLK_CTRL ((0x0046 << 2) + 0xfe000800)
+#define CLKTREE_GE2D_CLK_CTRL ((0x0047 << 2) + 0xfe000800)
+#define CLKTREE_SD_EMMC_CLK_CTRL1 ((0x0048 << 2) + 0xfe000800)
+#define CLKTREE_ETH_CLK_CTRL ((0x0049 << 2) + 0xfe000800)
+#define CLKTREE_PWM_CLK_GH_CTRL ((0x004a << 2) + 0xfe000800)
+#define CLKTREE_PWM_CLK_IJ_CTRL ((0x004b << 2) + 0xfe000800)
+#define CLKTREE_MBIST_ATSPEED_CTRL ((0x004c << 2) + 0xfe000800)
+//========================================================================
+// APB0_CEC - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000c00
+// -----------------------------------------------
+#define CECA_GEN_CNTL ((0x0000 << 2) + 0xfe000c00)
+#define CECA_RW_REG ((0x0001 << 2) + 0xfe000c00)
+#define CECA_INTR_MASKN ((0x0002 << 2) + 0xfe000c00)
+#define CECA_INTR_CLR ((0x0003 << 2) + 0xfe000c00)
+#define CECA_INTR_STAT ((0x0004 << 2) + 0xfe000c00)
+#define CECB_GEN_CNTL ((0x0010 << 2) + 0xfe000c00)
+#define CECB_RW_REG ((0x0011 << 2) + 0xfe000c00)
+#define CECB_INTR_MASKN ((0x0012 << 2) + 0xfe000c00)
+#define CECB_INTR_CLR ((0x0013 << 2) + 0xfe000c00)
+#define CECB_INTR_STAT ((0x0014 << 2) + 0xfe000c00)
+//========================================================================
+// APB0_IR_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001000
+// -----------------------------------------------
+#define IRCTRL_IR_DEC_LDR_ACTIVE ((0x0000 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_LDR_IDLE ((0x0001 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_LDR_REPEAT ((0x0002 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_BIT_0 ((0x0003 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_REG0 ((0x0004 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_FRAME ((0x0005 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_STATUS ((0x0006 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_REG1 ((0x0007 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_LDR_ACTIVE ((0x0010 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_LDR_IDLE ((0x0011 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_LDR_REPEAT ((0x0012 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_BIT_0 ((0x0013 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_REG0 ((0x0014 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_FRAME ((0x0015 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_STATUS ((0x0016 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_REG1 ((0x0017 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_REG2 ((0x0018 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_DURATN2 ((0x0019 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_DURATN3 ((0x001a << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_FRAME1 ((0x001b << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_STATUS1 ((0x001c << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_STATUS2 ((0x001d << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_REG3 ((0x001e << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_FRAME_RSV0 ((0x001f << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_FRAME_RSV1 ((0x0020 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_FILTE ((0x0021 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_IRQ_CTL ((0x0022 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_FIFO_CTL ((0x0023 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_WIDTH_NEW ((0x0024 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_REPEAT_DET ((0x0025 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_CNTL0 ((0x0030 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_CNTL1 ((0x0031 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_IIR_THD ((0x0032 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_THD0 ((0x0033 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_THD1 ((0x0034 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_SUM_CNT0 ((0x0035 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_SUM_CNT1 ((0x0036 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_CNT0 ((0x0037 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_CNT1 ((0x0038 << 2) + 0xfe001000)
+#define IRCTRL_IR_BLASTER_ADDR0 ((0x0043 << 2) + 0xfe001000)
+#define IRCTRL_IR_BLASTER_ADDR1 ((0x0044 << 2) + 0xfe001000)
+#define IRCTRL_IR_BLASTER_ADDR2 ((0x0045 << 2) + 0xfe001000)
+#define IRCTRL_IR_BLASTER_ADDR3 ((0x0046 << 2) + 0xfe001000)
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001400
+// -----------------------------------------------
+#define I2C_M_A_CONTROL_REG ((0x0000 << 2) + 0xfe001400)
+#define I2C_M_A_SLAVE_ADDR ((0x0001 << 2) + 0xfe001400)
+#define I2C_M_A_TOKEN_LIST0 ((0x0002 << 2) + 0xfe001400)
+#define I2C_M_A_TOKEN_LIST1 ((0x0003 << 2) + 0xfe001400)
+#define I2C_M_A_WDATA_REG0 ((0x0004 << 2) + 0xfe001400)
+#define I2C_M_A_WDATA_REG1 ((0x0005 << 2) + 0xfe001400)
+#define I2C_M_A_RDATA_REG0 ((0x0006 << 2) + 0xfe001400)
+#define I2C_M_A_RDATA_REG1 ((0x0007 << 2) + 0xfe001400)
+#define I2C_M_A_TIMEOUT_TH ((0x0008 << 2) + 0xfe001400)
+#define I2C_M_A_CNTL_DELY1 ((0x0009 << 2) + 0xfe001400)
+#define I2C_M_A_CNTL_DELY2 ((0x000a << 2) + 0xfe001400)
+#define I2C_M_A_LOW_DELY ((0x000b << 2) + 0xfe001400)
+#define I2C_M_A_HIGH_DELY ((0x000c << 2) + 0xfe001400)
+#define I2C_M_A_FIFO_CTRL_REG ((0x000d << 2) + 0xfe001400)
+#define I2C_M_A_STATE_REG ((0x000e << 2) + 0xfe001400)
+//========================================================================
+// APB0_I2C_S - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001800
+// -----------------------------------------------
+#define I2C_S_A_CONTROL_REG ((0x0000 << 2) + 0xfe001800)
+#define I2C_S_A_SEND_REG ((0x0001 << 2) + 0xfe001800)
+#define I2C_S_A_RECV_REG ((0x0002 << 2) + 0xfe001800)
+#define I2C_S_A_CNTL1_REG ((0x0003 << 2) + 0xfe001800)
+//========================================================================
+// APB0_UART_A - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001c00
+// -----------------------------------------------
+#define UART_A_WFIFO ((0x0000 << 2) + 0xfe001c00)
+#define UART_A_RFIFO ((0x0001 << 2) + 0xfe001c00)
+#define UART_A_CONTROL ((0x0002 << 2) + 0xfe001c00)
+#define UART_A_STATUS ((0x0003 << 2) + 0xfe001c00)
+#define UART_A_MISC ((0x0004 << 2) + 0xfe001c00)
+#define UART_A_REG5 ((0x0005 << 2) + 0xfe001c00)
+//========================================================================
+// APB0_UART_B - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002000
+// -----------------------------------------------
+#define UART_B_WFIFO ((0x0000 << 2) + 0xfe002000)
+#define UART_B_RFIFO ((0x0001 << 2) + 0xfe002000)
+#define UART_B_CONTROL ((0x0002 << 2) + 0xfe002000)
+#define UART_B_STATUS ((0x0003 << 2) + 0xfe002000)
+#define UART_B_MISC ((0x0004 << 2) + 0xfe002000)
+#define UART_B_REG5 ((0x0005 << 2) + 0xfe002000)
+//========================================================================
+// APB0_PWM_AB - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002400
+// -----------------------------------------------
+#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400)
+#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400)
+#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400)
+#define PWMAB_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe002400)
+#define PWMAB_TIME_AB ((0x0004 << 2) + 0xfe002400)
+#define PWMAB_A2 ((0x0005 << 2) + 0xfe002400)
+#define PWMAB_B2 ((0x0006 << 2) + 0xfe002400)
+#define PWMAB_BLINK_AB ((0x0007 << 2) + 0xfe002400)
+#define PWMAB_LOCK_AB ((0x0008 << 2) + 0xfe002400)
+//========================================================================
+// APB0_PWM_CD - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002800
+// -----------------------------------------------
+#define PWMCD_PWM_C ((0x0000 << 2) + 0xfe002800)
+#define PWMCD_PWM_D ((0x0001 << 2) + 0xfe002800)
+#define PWMCD_MISC_REG_CD ((0x0002 << 2) + 0xfe002800)
+#define PWMCD_DELTA_SIGMA_CD ((0x0003 << 2) + 0xfe002800)
+#define PWMCD_TIME_CD ((0x0004 << 2) + 0xfe002800)
+#define PWMCD_C2 ((0x0005 << 2) + 0xfe002800)
+#define PWMCD_D2 ((0x0006 << 2) + 0xfe002800)
+#define PWMCD_BLINK_CD ((0x0007 << 2) + 0xfe002800)
+#define PWMCD_LOCK_CD ((0x0008 << 2) + 0xfe002800)
+//========================================================================
+// APB0_SARADC - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002c00
+// -----------------------------------------------
+#define SAR_ADC_REG0 ((0x0000 << 2) + 0xfe002c00)
+#define SAR_ADC_CHAN_LIST ((0x0001 << 2) + 0xfe002c00)
+#define SAR_ADC_AVG_CNTL ((0x0002 << 2) + 0xfe002c00)
+#define SAR_ADC_REG3 ((0x0003 << 2) + 0xfe002c00)
+#define SAR_ADC_DELAY ((0x0004 << 2) + 0xfe002c00)
+#define SAR_ADC_LAST_RD ((0x0005 << 2) + 0xfe002c00)
+#define SAR_ADC_FIFO_RD ((0x0006 << 2) + 0xfe002c00)
+#define SAR_ADC_AUX_SW ((0x0007 << 2) + 0xfe002c00)
+#define SAR_ADC_CHAN_10_SW ((0x0008 << 2) + 0xfe002c00)
+#define SAR_ADC_DETECT_IDLE_SW ((0x0009 << 2) + 0xfe002c00)
+#define SAR_ADC_DELTA_10 ((0x000a << 2) + 0xfe002c00)
+#define SAR_ADC_REG11 ((0x000b << 2) + 0xfe002c00)
+#define SAR_ADC_REG12 ((0x000c << 2) + 0xfe002c00)
+#define SAR_ADC_REG13 ((0x000d << 2) + 0xfe002c00)
+#define SAR_ADC_CHNL01 ((0x000e << 2) + 0xfe002c00)
+#define SAR_ADC_CHNL23 ((0x000f << 2) + 0xfe002c00)
+#define SAR_ADC_CHNL45 ((0x0010 << 2) + 0xfe002c00)
+#define SAR_ADC_CHNL67 ((0x0011 << 2) + 0xfe002c00)
+//========================================================================
+// JTAGCTRL_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003000
+// -----------------------------------------------
+#define JTAGCTRL_CTRL0 ((0x0000 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_CTRL0 ((0x0001 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_ADDR0 ((0x0002 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_ADDR1 ((0x0003 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_ADDR2 ((0x0004 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_ADDR3 ((0x0005 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_VALUE0 ((0x0006 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_VALUE1 ((0x0007 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_VALUE2 ((0x0008 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_VALUE3 ((0x0009 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_STS ((0x000a << 2) + 0xfe003000)
+//========================================================================
+// APB0_MSR_CLK - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003400
+// -----------------------------------------------
+#define MSR_CLK_REG0 ((0x0000 << 2) + 0xfe003400)
+#define MSR_CLK_REG1 ((0x0001 << 2) + 0xfe003400)
+#define MSR_CLK_REG2 ((0x0002 << 2) + 0xfe003400)
+#define MSR_CLK_REG3 ((0x0003 << 2) + 0xfe003400)
+#define MSR_CLK_REG4 ((0x0004 << 2) + 0xfe003400)
+#define MSR_CLK_REG5 ((0x0005 << 2) + 0xfe003400)
+#define MSR_CLK_DUTY ((0x0006 << 2) + 0xfe003400)
+//========================================================================
+// APB0_SPICCA_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003800
+// -----------------------------------------------
+#define SPICC_A_RXDATA ((0x0000 << 2) + 0xfe003800)
+#define SPICC_A_TXDATA ((0x0001 << 2) + 0xfe003800)
+#define SPICC_A_CONREG ((0x0002 << 2) + 0xfe003800)
+#define SPICC_A_INTREG ((0x0003 << 2) + 0xfe003800)
+#define SPICC_A_DMAREG ((0x0004 << 2) + 0xfe003800)
+#define SPICC_A_STATREG ((0x0005 << 2) + 0xfe003800)
+#define SPICC_A_PERIODREG ((0x0006 << 2) + 0xfe003800)
+#define SPICC_A_TESTREG ((0x0007 << 2) + 0xfe003800)
+#define SPICC_A_DRADDR ((0x0008 << 2) + 0xfe003800)
+#define SPICC_A_DWADDR ((0x0009 << 2) + 0xfe003800)
+#define SPICC_A_LD_CNTL0 ((0x000a << 2) + 0xfe003800)
+#define SPICC_A_LD_CNTL1 ((0x000b << 2) + 0xfe003800)
+#define SPICC_A_LD_RADDR ((0x000c << 2) + 0xfe003800)
+#define SPICC_A_LD_WADDR ((0x000d << 2) + 0xfe003800)
+#define SPICC_A_ENHANCE_CNTL ((0x000e << 2) + 0xfe003800)
+#define SPICC_A_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe003800)
+#define SPICC_A_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe003800)
+//========================================================================
+// APB0_SPICCB_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003c00
+// -----------------------------------------------
+#define SPICC_B_RXDATA ((0x0000 << 2) + 0xfe003c00)
+#define SPICC_B_TXDATA ((0x0001 << 2) + 0xfe003c00)
+#define SPICC_B_CONREG ((0x0002 << 2) + 0xfe003c00)
+#define SPICC_B_INTREG ((0x0003 << 2) + 0xfe003c00)
+#define SPICC_B_DMAREG ((0x0004 << 2) + 0xfe003c00)
+#define SPICC_B_STATREG ((0x0005 << 2) + 0xfe003c00)
+#define SPICC_B_PERIODREG ((0x0006 << 2) + 0xfe003c00)
+#define SPICC_B_TESTREG ((0x0007 << 2) + 0xfe003c00)
+#define SPICC_B_DRADDR ((0x0008 << 2) + 0xfe003c00)
+#define SPICC_B_DWADDR ((0x0009 << 2) + 0xfe003c00)
+#define SPICC_B_LD_CNTL0 ((0x000a << 2) + 0xfe003c00)
+#define SPICC_B_LD_CNTL1 ((0x000b << 2) + 0xfe003c00)
+#define SPICC_B_LD_RADDR ((0x000c << 2) + 0xfe003c00)
+#define SPICC_B_LD_WADDR ((0x000d << 2) + 0xfe003c00)
+#define SPICC_B_ENHANCE_CNTL ((0x000e << 2) + 0xfe003c00)
+#define SPICC_B_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe003c00)
+#define SPICC_B_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe003c00)
+//========================================================================
+// USBCTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe004000
+// -----------------------------------------------
+#define USB_CTRL0 ((0x0000 << 2) + 0xfe004000)
+#define USB_CTRL1 ((0x0001 << 2) + 0xfe004000)
+#define USB_CTRL2 ((0x0002 << 2) + 0xfe004000)
+#define USB_CTRL3 ((0x0003 << 2) + 0xfe004000)
+#define USB_CTRL4 ((0x0004 << 2) + 0xfe004000)
+#define USB_CTRL5 ((0x0005 << 2) + 0xfe004000)
+#define USB_CTRL6 ((0x0006 << 2) + 0xfe004000)
+#define USB_CTRL7 ((0x0007 << 2) + 0xfe004000)
+#define USB_CTRL8 ((0x0008 << 2) + 0xfe004000)
+#define USB_CTRL9 ((0x0009 << 2) + 0xfe004000)
+#define USB_CTRL10 ((0x000a << 2) + 0xfe004000)
+#define USB_CTRL11 ((0x000b << 2) + 0xfe004000)
+#define USB_CTRL12 ((0x000c << 2) + 0xfe004000)
+#define USB_CTRL13 ((0x000d << 2) + 0xfe004000)
+#define USB_CTRL14 ((0x000e << 2) + 0xfe004000)
+#define USB_CTRL15 ((0x000f << 2) + 0xfe004000)
+#define USB_CTRL16 ((0x0010 << 2) + 0xfe004000)
+#define USB_CTRL17 ((0x0011 << 2) + 0xfe004000)
+#define USB_CTRL18 ((0x0012 << 2) + 0xfe004000)
+#define USB_CTRL19 ((0x0013 << 2) + 0xfe004000)
+#define USB_CTRL20 ((0x0014 << 2) + 0xfe004000)
+#define USB_CTRL21 ((0x0015 << 2) + 0xfe004000)
+#define USB_CTRL22 ((0x0016 << 2) + 0xfe004000)
+#define USB_CTRL23 ((0x0017 << 2) + 0xfe004000)
+#define USB_CTRL24 ((0x0018 << 2) + 0xfe004000)
+#define USB_CTRL25 ((0x0019 << 2) + 0xfe004000)
+#define USB_CTRL26 ((0x001a << 2) + 0xfe004000)
+#define USB_CTRL27 ((0x001b << 2) + 0xfe004000)
+#define USB_CTRL28 ((0x001c << 2) + 0xfe004000)
+#define USB_CTRL29 ((0x001d << 2) + 0xfe004000)
+#define USB_CTRL30 ((0x001e << 2) + 0xfe004000)
+#define USB_CTRL31 ((0x001f << 2) + 0xfe004000)
+//========================================================================
+// APB0_ACODEC_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe004800
+// -----------------------------------------------
+#define ACODEC_0 ((0x0000 << 2) + 0xfe004800)
+#define ACODEC_1 ((0x0001 << 2) + 0xfe004800)
+#define ACODEC_2 ((0x0002 << 2) + 0xfe004800)
+#define ACODEC_3 ((0x0003 << 2) + 0xfe004800)
+#define ACODEC_4 ((0x0004 << 2) + 0xfe004800)
+#define ACODEC_5 ((0x0005 << 2) + 0xfe004800)
+#define ACODEC_6 ((0x0006 << 2) + 0xfe004800)
+#define ACODEC_7 ((0x0007 << 2) + 0xfe004800)
+#define ACODEC_8 ((0x0008 << 2) + 0xfe004800)
+#define ACODEC_9 ((0x0009 << 2) + 0xfe004800)
+#define ACODEC_STS0 ((0x0010 << 2) + 0xfe004800)
+//========================================================================
+// APB0_TEMP_SENSOR - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe004c00
+// -----------------------------------------------
+#define TS_CFG_REG1 ((0x0001 << 2) + 0xfe004c00)
+#define TS_CFG_REG2 ((0x0002 << 2) + 0xfe004c00)
+#define TS_CFG_REG3 ((0x0003 << 2) + 0xfe004c00)
+#define TS_CFG_REG4 ((0x0004 << 2) + 0xfe004c00)
+#define TS_CFG_REG5 ((0x0005 << 2) + 0xfe004c00)
+#define TS_CFG_REG6 ((0x0006 << 2) + 0xfe004c00)
+#define TS_CFG_REG7 ((0x0007 << 2) + 0xfe004c00)
+#define TS_STAT0 ((0x0010 << 2) + 0xfe004c00)
+#define TS_STAT1 ((0x0011 << 2) + 0xfe004c00)
+#define TS_STAT2 ((0x0012 << 2) + 0xfe004c00)
+#define TS_STAT3 ((0x0013 << 2) + 0xfe004c00)
+#define TS_STAT4 ((0x0014 << 2) + 0xfe004c00)
+#define TS_STAT5 ((0x0015 << 2) + 0xfe004c00)
+#define TS_STAT6 ((0x0016 << 2) + 0xfe004c00)
+#define TS_STAT7 ((0x0017 << 2) + 0xfe004c00)
+#define TS_STAT8 ((0x0018 << 2) + 0xfe004c00)
+#define TS_STAT9 ((0x0019 << 2) + 0xfe004c00)
+//========================================================================
+// APB0_KL_EFUSE_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005000
+// -----------------------------------------------
+//
+// Reading file: ../crypto/crypto_reg.h
+//
+#define OTP_TEE_RDY ((0x0000 << 2) + 0xfe005000)
+#define OTP_TEE_CHK ((0x0001 << 2) + 0xfe005000)
+#define OTP_TEE_CFG ((0x0002 << 2) + 0xfe005000)
+#define OTP_TEE_WR_DAT0 ((0x0004 << 2) + 0xfe005000)
+#define OTP_TEE_WR_DAT1 ((0x0005 << 2) + 0xfe005000)
+#define OTP_TEE_WR_DAT2 ((0x0006 << 2) + 0xfe005000)
+#define OTP_TEE_WR_DAT3 ((0x0007 << 2) + 0xfe005000)
+#define OTP_TEE_RD_DAT0 ((0x0008 << 2) + 0xfe005000)
+#define OTP_TEE_RD_DAT1 ((0x0009 << 2) + 0xfe005000)
+#define OTP_TEE_RD_DAT2 ((0x000a << 2) + 0xfe005000)
+#define OTP_TEE_RD_DAT3 ((0x000b << 2) + 0xfe005000)
+#define OTP_RMA_PW0 ((0x000c << 2) + 0xfe005000)
+#define OTP_RMA_PW1 ((0x000d << 2) + 0xfe005000)
+#define OTP_RMA_PW2 ((0x000e << 2) + 0xfe005000)
+#define OTP_RMA_PW3 ((0x000f << 2) + 0xfe005000)
+#define OTP_REE_RDY ((0x0010 << 2) + 0xfe005000)
+#define OTP_REE_CHK ((0x0011 << 2) + 0xfe005000)
+#define OTP_REE_CFG ((0x0012 << 2) + 0xfe005000)
+#define OTP_REE_RD_DAT0 ((0x0014 << 2) + 0xfe005000)
+#define OTP_REE_RD_DAT1 ((0x0015 << 2) + 0xfe005000)
+#define OTP_REE_RD_DAT2 ((0x0016 << 2) + 0xfe005000)
+#define OTP_REE_RD_DAT3 ((0x0017 << 2) + 0xfe005000)
+#define OTP_LIC0 ((0x0018 << 2) + 0xfe005000)
+#define OTP_LIC1 ((0x0019 << 2) + 0xfe005000)
+#define OTP_LIC2 ((0x001a << 2) + 0xfe005000)
+#define OTP_LIC3 ((0x001b << 2) + 0xfe005000)
+#define RNG_SEC_CONFIG_REG1 ((0x0041 << 2) + 0xfe005000)
+#define RNG_SEC_CONFIG_REG2 ((0x0042 << 2) + 0xfe005000)
+#define RNG_SEC_DATA ((0x0044 << 2) + 0xfe005000)
+#define RNG_SEC_STS ((0x0045 << 2) + 0xfe005000)
+#define RNG_USR_DATA ((0x0046 << 2) + 0xfe005000)
+#define RNG_USR_STS ((0x0047 << 2) + 0xfe005000)
+#define KTE_SLOT0 ((0x0060 << 2) + 0xfe005000)
+#define KTE_SLOT1 ((0x0061 << 2) + 0xfe005000)
+#define KTE_SLOT2 ((0x0062 << 2) + 0xfe005000)
+#define KTE_SLOT3 ((0x0063 << 2) + 0xfe005000)
+#define KTE_SLOT4 ((0x0064 << 2) + 0xfe005000)
+#define KTE_SLOT5 ((0x0065 << 2) + 0xfe005000)
+#define KTE_SLOT6 ((0x0066 << 2) + 0xfe005000)
+#define KTE_SLOT7 ((0x0067 << 2) + 0xfe005000)
+#define MKL_TEE_RDY ((0x0080 << 2) + 0xfe005000)
+#define MKL_TEE_CHK ((0x0081 << 2) + 0xfe005000)
+#define MKL_TEE_CFG ((0x0082 << 2) + 0xfe005000)
+#define MKL_TEE_EK ((0x0084 << 2) + 0xfe005000)
+#define MKL_REE_RDY ((0x00a0 << 2) + 0xfe005000)
+#define MKL_REE_CHK ((0x00a1 << 2) + 0xfe005000)
+#define MKL_REE_CFG ((0x00a2 << 2) + 0xfe005000)
+#define MKL_REE_EK ((0x00a4 << 2) + 0xfe005000)
+//
+// Closing file: ../crypto/crypto_reg.h
+//
+//========================================================================
+// APB0_PWM_EF - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005400
+// -----------------------------------------------
+#define PWMEF_PWM_E ((0x0000 << 2) + 0xfe005400)
+#define PWMEF_PWM_F ((0x0001 << 2) + 0xfe005400)
+#define PWMEF_MISC_REG_EF ((0x0002 << 2) + 0xfe005400)
+#define PWMEF_DELTA_SIGMA_EF ((0x0003 << 2) + 0xfe005400)
+#define PWMEF_TIME_EF ((0x0004 << 2) + 0xfe005400)
+#define PWMEF_E2 ((0x0005 << 2) + 0xfe005400)
+#define PWMEF_F2 ((0x0006 << 2) + 0xfe005400)
+#define PWMEF_BLINK_EF ((0x0007 << 2) + 0xfe005400)
+#define PWMEF_LOCK_EF ((0x0008 << 2) + 0xfe005400)
+//========================================================================
+// APB0_SYS_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005800
+// -----------------------------------------------
+#define SYSCTRL_METAL_REV0 ((0x0000 << 2) + 0xfe005800)
+#define SYSCTRL_METAL_REV1 ((0x0001 << 2) + 0xfe005800)
+//`define SYSCTRL_PROD_ENABLE 8'h0a
+#define SYSCTRL_CHIP_ID ((0x000b << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE1_REG0 ((0x0010 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE1_STICKY_REG0 ((0x0011 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE1_SEC_REG0 ((0x0012 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE1_STICKY_SEC_REG0 ((0x0013 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE_REG0 ((0x0014 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE_REG1 ((0x0015 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE_SEC_REG0 ((0x0016 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE_STICKY_REG0 ((0x0017 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE_STICKY_REG1 ((0x0018 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE_STICKY_SEC_REG0 ((0x0019 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERA_CTRL ((0x0030 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERA ((0x0031 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERB_CTRL ((0x0032 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERB ((0x0033 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERC_CTRL ((0x0034 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERC ((0x0035 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERD_CTRL ((0x0036 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERD ((0x0037 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_TIMERA_CTRL ((0x0038 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_TIMERA ((0x0039 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERE_CTRL ((0x0040 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERE ((0x0041 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERE_HI ((0x0042 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERF_CTRL ((0x0043 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERF ((0x0044 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERF_HI ((0x0045 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_TIMERE_CTRL ((0x0046 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_TIMERE ((0x0047 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_TIMERE_HI ((0x0048 << 2) + 0xfe005800)
+#define SYSCTRL_OSC_RING_CTRL0 ((0x0050 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_DDR_AXI_SEL ((0x0051 << 2) + 0xfe005800)
+#define SYSCTRL_AM2AXI_CTRL0 ((0x0052 << 2) + 0xfe005800)
+#define SYSCTRL_AM2AXI_STS ((0x0053 << 2) + 0xfe005800)
+#define SYSCTRL_OSC_RING_CTRL1 ((0x0054 << 2) + 0xfe005800)
+#define SYSCTRL_POC ((0x0060 << 2) + 0xfe005800)
+//`define SYSCTRL_PROD_PWD_VALUE0 8'h80
+//`define SYSCTRL_PROD_PWD_VALUE1 8'h81
+//`define SYSCTRL_PROD_PWD_VALUE2 8'h82
+//`define SYSCTRL_PROD_PWD_VALUE3 8'h83
+//`define SYSCTRL_PROD_STATUS 8'h84
+#define SYSCTRL_DEBUG_REG0 ((0x0090 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG1 ((0x0091 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG2 ((0x0092 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG3 ((0x0093 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG4 ((0x0094 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG5 ((0x0095 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG6 ((0x0096 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG7 ((0x0097 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG0 ((0x00a0 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG1 ((0x00a1 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG2 ((0x00a2 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG3 ((0x00a3 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG4 ((0x00a4 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG5 ((0x00a5 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG6 ((0x00a6 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG7 ((0x00a7 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG0 ((0x00b0 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG1 ((0x00b1 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG2 ((0x00b2 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG3 ((0x00b3 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG4 ((0x00b4 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG5 ((0x00b5 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG6 ((0x00b6 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG7 ((0x00b7 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG0 ((0x00c0 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG1 ((0x00c1 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG2 ((0x00c2 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG3 ((0x00c3 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG4 ((0x00c4 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG5 ((0x00c5 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG6 ((0x00c6 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG7 ((0x00c7 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG8 ((0x00c8 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG9 ((0x00c9 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG10 ((0x00ca << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG11 ((0x00cb << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG12 ((0x00cc << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG13 ((0x00cd << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG14 ((0x00ce << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG15 ((0x00cf << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG16 ((0x00d0 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG17 ((0x00d1 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG18 ((0x00d2 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG19 ((0x00d3 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG20 ((0x00d4 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG21 ((0x00d5 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG22 ((0x00d6 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG23 ((0x00d7 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG0 ((0x00e0 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG1 ((0x00e1 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG2 ((0x00e2 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG3 ((0x00e3 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG4 ((0x00e4 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG5 ((0x00e5 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG6 ((0x00e6 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG7 ((0x00e7 << 2) + 0xfe005800)
+#define SYSCTRL_MSG_INDEX0_STICKY ((0x00f0 << 2) + 0xfe005800)
+#define SYSCTRL_MSG_INDEX1_STICKY ((0x00f1 << 2) + 0xfe005800)
+#define SYSCTRL_MSG_INDEX2_STICKY ((0x00f2 << 2) + 0xfe005800)
+#define SYSCTRL_MSG_INDEX3_STICKY ((0x00f3 << 2) + 0xfe005800)
+//========================================================================
+// APB0_I2C_M_B - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005c00
+// -----------------------------------------------
+#define I2C_M_B_CONTROL_REG ((0x0000 << 2) + 0xfe005c00)
+#define I2C_M_B_SLAVE_ADDR ((0x0001 << 2) + 0xfe005c00)
+#define I2C_M_B_TOKEN_LIST0 ((0x0002 << 2) + 0xfe005c00)
+#define I2C_M_B_TOKEN_LIST1 ((0x0003 << 2) + 0xfe005c00)
+#define I2C_M_B_WDATA_REG0 ((0x0004 << 2) + 0xfe005c00)
+#define I2C_M_B_WDATA_REG1 ((0x0005 << 2) + 0xfe005c00)
+#define I2C_M_B_RDATA_REG0 ((0x0006 << 2) + 0xfe005c00)
+#define I2C_M_B_RDATA_REG1 ((0x0007 << 2) + 0xfe005c00)
+#define I2C_M_B_TIMEOUT_TH ((0x0008 << 2) + 0xfe005c00)
+#define I2C_M_B_CNTL_DELY1 ((0x0009 << 2) + 0xfe005c00)
+#define I2C_M_B_CNTL_DELY2 ((0x000a << 2) + 0xfe005c00)
+#define I2C_M_B_LOW_DELY ((0x000b << 2) + 0xfe005c00)
+#define I2C_M_B_HIGH_DELY ((0x000c << 2) + 0xfe005c00)
+#define I2C_M_B_FIFO_CTRL_REG ((0x000d << 2) + 0xfe005c00)
+#define I2C_M_B_STATE_REG ((0x000e << 2) + 0xfe005c00)
+//========================================================================
+// APB0_DMA - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006000
+// -----------------------------------------------
+//TODO
+//========================================================================
+// APB0_IRQ_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006400
+// -----------------------------------------------
+#define IRQCTRL_IRQOUT_MASK0 ((0x0000 << 2) + 0xfe006400)
+#define IRQCTRL_IRQOUT_MASK1 ((0x0001 << 2) + 0xfe006400)
+#define IRQCTRL_IRQOUT_MASK2 ((0x0002 << 2) + 0xfe006400)
+#define IRQCTRL_IRQOUT_MASK3 ((0x0003 << 2) + 0xfe006400)
+#define IRQCTRL_IRQOUT_MASK4 ((0x0004 << 2) + 0xfe006400)
+#define IRQCTRL_IRQOUT_MASK5 ((0x0005 << 2) + 0xfe006400)
+#define IRQCTRL_IRQOUT_INV0 ((0x0010 << 2) + 0xfe006400)
+#define IRQCTRL_IRQOUT_INV1 ((0x0011 << 2) + 0xfe006400)
+#define IRQCTRL_IRQOUT_INV2 ((0x0012 << 2) + 0xfe006400)
+#define IRQCTRL_IRQOUT_INV3 ((0x0013 << 2) + 0xfe006400)
+#define IRQCTRL_IRQOUT_INV4 ((0x0014 << 2) + 0xfe006400)
+#define IRQCTRL_IRQOUT_INV5 ((0x0015 << 2) + 0xfe006400)
+//`define APB0_IRQIN_MASK0_CLK_USB 8'h00
+//`define APB0_IRQIN_MASK0_CLK_CPU 8'h01
+//`define APB0_IRQIN_MASK0_CLK_SYS 8'h02
+//`define APB0_IRQIN_MASK1_CLK_SYS 8'h03
+//`define APB0_IRQIN_MASK0_CLK_DSPA 8'h04
+//`define APB0_IRQIN_MASK0_CLK_DSPB 8'h05
+//`define APB0_IRQIN_CLRLVL_CLK_USB 8'h10
+//`define APB0_IRQIN_CLRLVL_CLK_DSPA 8'h11
+//`define APB0_IRQIN_CLRLVL_CLK_DSPB 8'h12
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006800
+// -----------------------------------------------
+#define I2C_M_C_CONTROL_REG ((0x0000 << 2) + 0xfe006800)
+#define I2C_M_C_SLAVE_ADDR ((0x0001 << 2) + 0xfe006800)
+#define I2C_M_C_TOKEN_LIST0 ((0x0002 << 2) + 0xfe006800)
+#define I2C_M_C_TOKEN_LIST1 ((0x0003 << 2) + 0xfe006800)
+#define I2C_M_C_WDATA_REG0 ((0x0004 << 2) + 0xfe006800)
+#define I2C_M_C_WDATA_REG1 ((0x0005 << 2) + 0xfe006800)
+#define I2C_M_C_RDATA_REG0 ((0x0006 << 2) + 0xfe006800)
+#define I2C_M_C_RDATA_REG1 ((0x0007 << 2) + 0xfe006800)
+#define I2C_M_C_TIMEOUT_TH ((0x0008 << 2) + 0xfe006800)
+#define I2C_M_C_CNTL_DELY1 ((0x0009 << 2) + 0xfe006800)
+#define I2C_M_C_CNTL_DELY2 ((0x000a << 2) + 0xfe006800)
+#define I2C_M_C_LOW_DELY ((0x000b << 2) + 0xfe006800)
+#define I2C_M_C_HIGH_DELY ((0x000c << 2) + 0xfe006800)
+#define I2C_M_C_FIFO_CTRL_REG ((0x000d << 2) + 0xfe006800)
+#define I2C_M_C_STATE_REG ((0x000e << 2) + 0xfe006800)
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006c00
+// -----------------------------------------------
+#define I2C_M_D_CONTROL_REG ((0x0000 << 2) + 0xfe006c00)
+#define I2C_M_D_SLAVE_ADDR ((0x0001 << 2) + 0xfe006c00)
+#define I2C_M_D_TOKEN_LIST0 ((0x0002 << 2) + 0xfe006c00)
+#define I2C_M_D_TOKEN_LIST1 ((0x0003 << 2) + 0xfe006c00)
+#define I2C_M_D_WDATA_REG0 ((0x0004 << 2) + 0xfe006c00)
+#define I2C_M_D_WDATA_REG1 ((0x0005 << 2) + 0xfe006c00)
+#define I2C_M_D_RDATA_REG0 ((0x0006 << 2) + 0xfe006c00)
+#define I2C_M_D_RDATA_REG1 ((0x0007 << 2) + 0xfe006c00)
+#define I2C_M_D_TIMEOUT_TH ((0x0008 << 2) + 0xfe006c00)
+#define I2C_M_D_CNTL_DELY1 ((0x0009 << 2) + 0xfe006c00)
+#define I2C_M_D_CNTL_DELY2 ((0x000a << 2) + 0xfe006c00)
+#define I2C_M_D_LOW_DELY ((0x000b << 2) + 0xfe006c00)
+#define I2C_M_D_HIGH_DELY ((0x000c << 2) + 0xfe006c00)
+#define I2C_M_D_FIFO_CTRL_REG ((0x000d << 2) + 0xfe006c00)
+#define I2C_M_D_STATE_REG ((0x000e << 2) + 0xfe006c00)
+//========================================================================
+// APB0_UART_C - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007000
+// -----------------------------------------------
+#define UART_C_WFIFO ((0x0000 << 2) + 0xfe007000)
+#define UART_C_RFIFO ((0x0001 << 2) + 0xfe007000)
+#define UART_C_CONTROL ((0x0002 << 2) + 0xfe007000)
+#define UART_C_STATUS ((0x0003 << 2) + 0xfe007000)
+#define UART_C_MISC ((0x0004 << 2) + 0xfe007000)
+#define UART_C_REG5 ((0x0005 << 2) + 0xfe007000)
+//========================================================================
+// CPUCTRL_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007400
+// -----------------------------------------------
+#define CPUCTRL_CTRL0 ((0x0000 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL1 ((0x0001 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL2 ((0x0002 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL3 ((0x0003 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL4 ((0x0004 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL5 ((0x0005 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL6 ((0x0006 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL7 ((0x0007 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL8 ((0x0008 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL9 ((0x0009 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL10 ((0x000a << 2) + 0xfe007400)
+#define CPUCTRL_CTRL11 ((0x000b << 2) + 0xfe007400)
+#define CPUCTRL_CTRL12 ((0x000c << 2) + 0xfe007400)
+#define CPUCTRL_CTRL13 ((0x000d << 2) + 0xfe007400)
+#define CPUCTRL_CTRL14 ((0x000e << 2) + 0xfe007400)
+#define CPUCTRL_CTRL15 ((0x000f << 2) + 0xfe007400)
+#define CPUCTRL_STS0 ((0x0010 << 2) + 0xfe007400)
+#define CPUCTRL_STS1 ((0x0011 << 2) + 0xfe007400)
+#define CPUCTRL_STS2 ((0x0012 << 2) + 0xfe007400)
+#define CPUCTRL_STS3 ((0x0013 << 2) + 0xfe007400)
+#define CPUCTRL_STS4 ((0x0014 << 2) + 0xfe007400)
+#define CPUCTRL_STS5 ((0x0015 << 2) + 0xfe007400)
+#define CPUCTRL_STS6 ((0x0016 << 2) + 0xfe007400)
+#define CPUCTRL_STS7 ((0x0017 << 2) + 0xfe007400)
+#define CPUCTRL_STS8 ((0x0018 << 2) + 0xfe007400)
+#define CPUCTRL_STS9 ((0x0019 << 2) + 0xfe007400)
+#define CPUCTRL_CLK_CTRL0 ((0x0020 << 2) + 0xfe007400)
+#define CPUCTRL_CLK_CTRL1 ((0x0021 << 2) + 0xfe007400)
+#define CPUCTRL_CLK_CTRL2 ((0x0022 << 2) + 0xfe007400)
+#define CPUCTRL_CLK_CTRL3 ((0x0023 << 2) + 0xfe007400)
+#define CPUCTRL_CLK_CTRL4 ((0x0024 << 2) + 0xfe007400)
+#define CPUCTRL_CLK_CTRL5 ((0x0025 << 2) + 0xfe007400)
+#define CPUCTRL_CLK_CTRL6 ((0x0026 << 2) + 0xfe007400)
+#define CPUCTRL_CLK_CTRL7 ((0x0027 << 2) + 0xfe007400)
+#define CPUCTRL_RESET_CTRL ((0x0030 << 2) + 0xfe007400)
+#define CPUCTRL_ROM_DISABLE ((0x0031 << 2) + 0xfe007400)
+//========================================================================
+// APB0_PWR_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007800
+// -----------------------------------------------
+#define PWRCTRL_PWR_ACK0 ((0x0000 << 2) + 0xfe007800)
+#define PWRCTRL_ISO_EN0 ((0x0001 << 2) + 0xfe007800)
+#define PWRCTRL_PWR_OFF0 ((0x0002 << 2) + 0xfe007800)
+#define PWRCTRL_SAVE_EN0 ((0x0003 << 2) + 0xfe007800)
+#define PWRCTRL_RESTORE_EN0 ((0x0004 << 2) + 0xfe007800)
+#define PWRCTRL_PWR_ACK1 ((0x0005 << 2) + 0xfe007800)
+#define PWRCTRL_ISO_EN1 ((0x0006 << 2) + 0xfe007800)
+#define PWRCTRL_PWR_OFF1 ((0x0007 << 2) + 0xfe007800)
+#define PWRCTRL_FOCRSTN0 ((0x0008 << 2) + 0xfe007800)
+#define PWRCTRL_FOCRSTN1 ((0x0009 << 2) + 0xfe007800)
+#define PWRCTRL_R_ISO_EN0 ((0x0010 << 2) + 0xfe007800)
+#define PWRCTRL_R_PWR_OFF0 ((0x0011 << 2) + 0xfe007800)
+#define PWRCTRL_R_ISO_EN1 ((0x0012 << 2) + 0xfe007800)
+#define PWRCTRL_R_PWR_OFF1 ((0x0013 << 2) + 0xfe007800)
+#define PWRCTRL_R_FOCRSTN0 ((0x0014 << 2) + 0xfe007800)
+#define PWRCTRL_R_FOCRSTN1 ((0x0015 << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD0 ((0x0020 << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD1 ((0x0021 << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD2 ((0x0022 << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD3 ((0x0023 << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD4 ((0x0024 << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD5 ((0x0025 << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD6 ((0x0026 << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD7 ((0x0027 << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD8 ((0x0028 << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD9 ((0x0029 << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD10 ((0x002a << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD11 ((0x002b << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD12 ((0x002c << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD13 ((0x002d << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD14 ((0x002e << 2) + 0xfe007800)
+#define PWRCTRL_MEM_PD15 ((0x002f << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD0 ((0x0030 << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD1 ((0x0031 << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD2 ((0x0032 << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD3 ((0x0033 << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD4 ((0x0034 << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD5 ((0x0035 << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD6 ((0x0036 << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD7 ((0x0037 << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD8 ((0x0038 << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD9 ((0x0039 << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD10 ((0x003a << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD11 ((0x003b << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD12 ((0x003c << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD13 ((0x003d << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD14 ((0x003e << 2) + 0xfe007800)
+#define PWRCTRL_R_MEM_PD15 ((0x003f << 2) + 0xfe007800)
+#define PWRCTRL_AUTO_OFF_CTRL ((0x0040 << 2) + 0xfe007800)
+#define PWRCTRL_AUTO_OFF ((0x0041 << 2) + 0xfe007800)
+#define PWRCTRL_AUTO_OFF_STS ((0x0042 << 2) + 0xfe007800)
+#define PWRCTRL_TIMER_TH_01 ((0x0043 << 2) + 0xfe007800)
+#define PWRCTRL_TIMER_TH_23 ((0x0044 << 2) + 0xfe007800)
+#define PWRCTRL_TIMER_TH_45 ((0x0045 << 2) + 0xfe007800)
+#define PWRCTRL_TIMER_TH_67 ((0x0046 << 2) + 0xfe007800)
+#define PWRCTRL_AUTO_OFF_CTRL1 ((0x0048 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_PWR_ACK0 ((0x0050 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_RSTN_OFF0 ((0x0051 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_RSTN_ON0 ((0x0052 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_PWR_OFF0 ((0x0053 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_PWR_ON0 ((0x0054 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_ISO_OFF0 ((0x0055 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_ISO_ON0 ((0x0056 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_PWR_ACK1 ((0x0058 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_RSTN_OFF1 ((0x0059 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_RSTN_ON1 ((0x005a << 2) + 0xfe007800)
+#define PWRCTRL_MASK_PWR_OFF1 ((0x005b << 2) + 0xfe007800)
+#define PWRCTRL_MASK_PWR_ON1 ((0x005c << 2) + 0xfe007800)
+#define PWRCTRL_MASK_ISO_OFF1 ((0x005d << 2) + 0xfe007800)
+#define PWRCTRL_MASK_ISO_ON1 ((0x005e << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF0 ((0x0060 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF1 ((0x0061 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF2 ((0x0062 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF3 ((0x0063 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF4 ((0x0064 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF5 ((0x0065 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF6 ((0x0066 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF7 ((0x0067 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF8 ((0x0068 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF9 ((0x0069 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF10 ((0x006a << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF11 ((0x006b << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF12 ((0x006c << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF13 ((0x006d << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF14 ((0x006e << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_OFF15 ((0x006f << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON0 ((0x0070 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON1 ((0x0071 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON2 ((0x0072 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON3 ((0x0073 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON4 ((0x0074 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON5 ((0x0075 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON6 ((0x0076 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON7 ((0x0077 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON8 ((0x0078 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON9 ((0x0079 << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON10 ((0x007a << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON11 ((0x007b << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON12 ((0x007c << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON13 ((0x007d << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON14 ((0x007e << 2) + 0xfe007800)
+#define PWRCTRL_MASK_MEM_ON15 ((0x007f << 2) + 0xfe007800)
+#define PWRCTRL_NNA_AXI_PWR_CNTL ((0x0080 << 2) + 0xfe007800)
+//========================================================================
+// APB0_ANA_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007c00
+// -----------------------------------------------
+#define ANACTRL_PLL_GATE_DIS ((0x0010 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_CTRL0 ((0x0020 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_CTRL1 ((0x0021 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_CTRL2 ((0x0022 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_CTRL3 ((0x0023 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_CTRL4 ((0x0024 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_CTRL5 ((0x0025 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_CTRL6 ((0x0026 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_STS ((0x0027 << 2) + 0xfe007c00)
+#define ANACTRL_GPPLL_CTRL0 ((0x0030 << 2) + 0xfe007c00)
+#define ANACTRL_GPPLL_CTRL1 ((0x0031 << 2) + 0xfe007c00)
+#define ANACTRL_GPPLL_CTRL2 ((0x0032 << 2) + 0xfe007c00)
+#define ANACTRL_GPPLL_CTRL3 ((0x0033 << 2) + 0xfe007c00)
+#define ANACTRL_GPPLL_CTRL4 ((0x0034 << 2) + 0xfe007c00)
+#define ANACTRL_GPPLL_CTRL5 ((0x0035 << 2) + 0xfe007c00)
+#define ANACTRL_GPPLL_STS ((0x0036 << 2) + 0xfe007c00)
+#define ANACTRL_SYSPLL_CTRL0 ((0x0040 << 2) + 0xfe007c00)
+#define ANACTRL_SYSPLL_CTRL1 ((0x0041 << 2) + 0xfe007c00)
+#define ANACTRL_SYSPLL_CTRL2 ((0x0042 << 2) + 0xfe007c00)
+#define ANACTRL_SYSPLL_CTRL3 ((0x0043 << 2) + 0xfe007c00)
+#define ANACTRL_SYSPLL_CTRL4 ((0x0044 << 2) + 0xfe007c00)
+#define ANACTRL_SYSPLL_STS ((0x0045 << 2) + 0xfe007c00)
+#define ANACTRL_HIFIPLL_CTRL0 ((0x0050 << 2) + 0xfe007c00)
+#define ANACTRL_HIFIPLL_CTRL1 ((0x0051 << 2) + 0xfe007c00)
+#define ANACTRL_HIFIPLL_CTRL2 ((0x0052 << 2) + 0xfe007c00)
+#define ANACTRL_HIFIPLL_CTRL3 ((0x0053 << 2) + 0xfe007c00)
+#define ANACTRL_HIFIPLL_CTRL4 ((0x0054 << 2) + 0xfe007c00)
+#define ANACTRL_HIFIPLL_STS ((0x0055 << 2) + 0xfe007c00)
+#define ANACTRL_AUDDDS_CTRL0 ((0x0060 << 2) + 0xfe007c00)
+#define ANACTRL_AUDDDS_CTRL1 ((0x0061 << 2) + 0xfe007c00)
+#define ANACTRL_AUDDDS_CTRL2 ((0x0062 << 2) + 0xfe007c00)
+#define ANACTRL_AUDDDS_CTRL3 ((0x0063 << 2) + 0xfe007c00)
+#define ANACTRL_AUDDDS_CTRL4 ((0x0064 << 2) + 0xfe007c00)
+#define ANACTRL_AUDDDS_STS ((0x0065 << 2) + 0xfe007c00)
+#define ANACTRL_MISCTOP_CTRL0 ((0x0070 << 2) + 0xfe007c00)
+#define ANACTRL_POR_CNTL ((0x0082 << 2) + 0xfe007c00)
+#define ANACTRL_CSI_PHY_CNTL0 ((0x0090 << 2) + 0xfe007c00)
+#define ANACTRL_CSI_PHY_CNTL1 ((0x0091 << 2) + 0xfe007c00)
+#define ANACTRL_CSI_PHY_CNTL2 ((0x0092 << 2) + 0xfe007c00)
+#define ANACTRL_CSI_PHY_CNTL3 ((0x0093 << 2) + 0xfe007c00)
+#define ANACTRL_CSI_PHY_STS ((0x0094 << 2) + 0xfe007c00)
+#define ANACTRL_ISP_MAX_ADDR_CNTL ((0x0095 << 2) + 0xfe007c00)
+//========================================================================
+// APB0_ETHTOP - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe009000
+// -----------------------------------------------
+#define ETHTOP_CNTL0 ((0x0000 << 2) + 0xfe009000)
+#define ETHTOP_CNTL1 ((0x0001 << 2) + 0xfe009000)
+//========================================================================
+// APB0_ETHPHY - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe009400
+// -----------------------------------------------
+#define ETH_PHY_DBG_CTL0 ((0x0000 << 2) + 0xfe009400)
+#define ETH_PHY_DBG_CTL1 ((0x0001 << 2) + 0xfe009400)
+#define ETH_PHY_DBG_CFG0 ((0x0002 << 2) + 0xfe009400)
+#define ETH_PHY_DBG_CFG1 ((0x0003 << 2) + 0xfe009400)
+#define ETH_PHY_DBG_CFG2 ((0x0004 << 2) + 0xfe009400)
+#define ETH_PHY_DBG_CFG3 ((0x0005 << 2) + 0xfe009400)
+#define ETH_PHY_DBG_CFG4 ((0x0006 << 2) + 0xfe009400)
+#define ETH_PLL_STS ((0x0010 << 2) + 0xfe009400)
+#define ETH_PLL_CTL0 ((0x0011 << 2) + 0xfe009400)
+#define ETH_PLL_CTL1 ((0x0012 << 2) + 0xfe009400)
+#define ETH_PLL_CTL2 ((0x0013 << 2) + 0xfe009400)
+#define ETH_PLL_CTL3 ((0x0014 << 2) + 0xfe009400)
+#define ETH_PLL_CTL4 ((0x0015 << 2) + 0xfe009400)
+#define ETH_PLL_CTL5 ((0x0016 << 2) + 0xfe009400)
+#define ETH_PLL_CTL6 ((0x0017 << 2) + 0xfe009400)
+#define ETH_PLL_CTL7 ((0x0018 << 2) + 0xfe009400)
+#define ETH_PHY_CNTL0 ((0x0020 << 2) + 0xfe009400)
+#define ETH_PHY_CNTL1 ((0x0021 << 2) + 0xfe009400)
+#define ETH_PHY_CNTL2 ((0x0022 << 2) + 0xfe009400)
+#define ETH_PHY_CNTL3 ((0x0023 << 2) + 0xfe009400)
+#define ETH_PHY_STS0 ((0x0025 << 2) + 0xfe009400)
+#define ETH_PHY_STS1 ((0x0026 << 2) + 0xfe009400)
+#define ETH_PHY_STS2 ((0x0027 << 2) + 0xfe009400)
+#define ETH_PHY_DBG_REG ((0x0028 << 2) + 0xfe009400)
+//========================================================================
+// APB0_UART_D - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe009c00
+// -----------------------------------------------
+#define UART_D_WFIFO ((0x0000 << 2) + 0xfe009c00)
+#define UART_D_RFIFO ((0x0001 << 2) + 0xfe009c00)
+#define UART_D_CONTROL ((0x0002 << 2) + 0xfe009c00)
+#define UART_D_STATUS ((0x0003 << 2) + 0xfe009c00)
+#define UART_D_MISC ((0x0004 << 2) + 0xfe009c00)
+#define UART_D_REG5 ((0x0005 << 2) + 0xfe009c00)
+//========================================================================
+// APB0_UART_E - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe00a000
+// -----------------------------------------------
+#define UART_E_WFIFO ((0x0000 << 2) + 0xfe00a000)
+#define UART_E_RFIFO ((0x0001 << 2) + 0xfe00a000)
+#define UART_E_CONTROL ((0x0002 << 2) + 0xfe00a000)
+#define UART_E_STATUS ((0x0003 << 2) + 0xfe00a000)
+#define UART_E_MISC ((0x0004 << 2) + 0xfe00a000)
+#define UART_E_REG5 ((0x0005 << 2) + 0xfe00a000)
+//========================================================================
+// APB0_PWM_GH - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe00a400
+// -----------------------------------------------
+#define PWMGH_PWM_G ((0x0000 << 2) + 0xfe00a400)
+#define PWMGH_PWM_H ((0x0001 << 2) + 0xfe00a400)
+#define PWMGH_MISC_REG_GH ((0x0002 << 2) + 0xfe00a400)
+#define PWMGH_DELTA_SIGMA_GH ((0x0003 << 2) + 0xfe00a400)
+#define PWMGH_TIME_GH ((0x0004 << 2) + 0xfe00a400)
+#define PWMGH_G2 ((0x0005 << 2) + 0xfe00a400)
+#define PWMGH_H2 ((0x0006 << 2) + 0xfe00a400)
+#define PWMGH_BLINK_GH ((0x0007 << 2) + 0xfe00a400)
+#define PWMGH_LOCK_GH ((0x0008 << 2) + 0xfe00a400)
+//========================================================================
+// APB0_PWM_IJ - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe00a800
+// -----------------------------------------------
+#define PWMIJ_PWM_I ((0x0000 << 2) + 0xfe00a800)
+#define PWMIJ_PWM_J ((0x0001 << 2) + 0xfe00a800)
+#define PWMIJ_MISC_REG_IJ ((0x0002 << 2) + 0xfe00a800)
+#define PWMIJ_DELTA_SIGMA_IJ ((0x0003 << 2) + 0xfe00a800)
+#define PWMIJ_TIME_IJ ((0x0004 << 2) + 0xfe00a800)
+#define PWMIJ_I2 ((0x0005 << 2) + 0xfe00a800)
+#define PWMIJ_J2 ((0x0006 << 2) + 0xfe00a800)
+#define PWMIJ_BLINK_IJ ((0x0007 << 2) + 0xfe00a800)
+#define PWMIJ_LOCK_IJ ((0x0008 << 2) + 0xfe00a800)
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe00b000
+// -----------------------------------------------
+#define I2C_M_E_CONTROL_REG ((0x0000 << 2) + 0xfe00b000)
+#define I2C_M_E_SLAVE_ADDR ((0x0001 << 2) + 0xfe00b000)
+#define I2C_M_E_TOKEN_LIST0 ((0x0002 << 2) + 0xfe00b000)
+#define I2C_M_E_TOKEN_LIST1 ((0x0003 << 2) + 0xfe00b000)
+#define I2C_M_E_WDATA_REG0 ((0x0004 << 2) + 0xfe00b000)
+#define I2C_M_E_WDATA_REG1 ((0x0005 << 2) + 0xfe00b000)
+#define I2C_M_E_RDATA_REG0 ((0x0006 << 2) + 0xfe00b000)
+#define I2C_M_E_RDATA_REG1 ((0x0007 << 2) + 0xfe00b000)
+#define I2C_M_E_TIMEOUT_TH ((0x0008 << 2) + 0xfe00b000)
+#define I2C_M_E_CNTL_DELY1 ((0x0009 << 2) + 0xfe00b000)
+#define I2C_M_E_CNTL_DELY2 ((0x000a << 2) + 0xfe00b000)
+#define I2C_M_E_LOW_DELY ((0x000b << 2) + 0xfe00b000)
+#define I2C_M_E_HIGH_DELY ((0x000c << 2) + 0xfe00b000)
+#define I2C_M_E_FIFO_CTRL_REG ((0x000d << 2) + 0xfe00b000)
+#define I2C_M_E_STATE_REG ((0x000e << 2) + 0xfe00b000)
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe020000
+// -----------------------------------------------
+#define RSA_BASE ((0x0000 << 2) + 0xfe020000)
+//========================================================================
+// RAMA_SEC_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe00b400
+// -----------------------------------------------
+#define SRAM_RANGE0_STA ((0x0000 << 2) + 0xfe00b400)
+#define SRAM_RANGE1_STA ((0x0001 << 2) + 0xfe00b400)
+#define SRAM_RANGE2_STA ((0x0002 << 2) + 0xfe00b400)
+#define SRAM_RANGE3_STA ((0x0003 << 2) + 0xfe00b400)
+#define SRAM_RANGE4_STA ((0x0004 << 2) + 0xfe00b400)
+#define SRAM_RANGE5_STA ((0x0005 << 2) + 0xfe00b400)
+#define SRAM_RANGE6_STA ((0x0006 << 2) + 0xfe00b400)
+#define SRAM_RANGE0_EDA ((0x0007 << 2) + 0xfe00b400)
+#define SRAM_RANGE1_EDA ((0x0008 << 2) + 0xfe00b400)
+#define SRAM_RANGE2_EDA ((0x0009 << 2) + 0xfe00b400)
+#define SRAM_RANGE3_EDA ((0x000a << 2) + 0xfe00b400)
+#define SRAM_RANGE4_EDA ((0x000b << 2) + 0xfe00b400)
+#define SRAM_RANGE5_EDA ((0x000c << 2) + 0xfe00b400)
+#define SRAM_RANGE6_EDA ((0x000d << 2) + 0xfe00b400)
+#define SRAM_RANGE0_CTRL0 ((0x000e << 2) + 0xfe00b400)
+#define SRAM_RANGE0_CTRL01 ((0x000f << 2) + 0xfe00b400)
+#define SRAM_RANGE1_CTRL0 ((0x0010 << 2) + 0xfe00b400)
+#define SRAM_RANGE1_CTRL01 ((0x0011 << 2) + 0xfe00b400)
+#define SRAM_RANGE2_CTRL0 ((0x0012 << 2) + 0xfe00b400)
+#define SRAM_RANGE2_CTRL01 ((0x0013 << 2) + 0xfe00b400)
+#define SRAM_RANGE3_CTRL0 ((0x0014 << 2) + 0xfe00b400)
+#define SRAM_RANGE3_CTRL01 ((0x0015 << 2) + 0xfe00b400)
+#define SRAM_RANGE4_CTRL0 ((0x0016 << 2) + 0xfe00b400)
+#define SRAM_RANGE4_CTRL01 ((0x0017 << 2) + 0xfe00b400)
+#define SRAM_RANGE5_CTRL0 ((0x0018 << 2) + 0xfe00b400)
+#define SRAM_RANGE5_CTRL01 ((0x0019 << 2) + 0xfe00b400)
+#define SRAM_RANGE6_CTRL0 ((0x001a << 2) + 0xfe00b400)
+#define SRAM_RANGE6_CTRL01 ((0x001b << 2) + 0xfe00b400)
+#define SRAM_RANGE7_CTRL0 ((0x001c << 2) + 0xfe00b400)
+#define SRAM_RANGE7_CTRL01 ((0x001d << 2) + 0xfe00b400)
+#define SRAM_RANGE0_CTRL1 ((0x001e << 2) + 0xfe00b400)
+#define SRAM_RANGE0_CTRL11 ((0x001f << 2) + 0xfe00b400)
+#define SRAM_RANGE1_CTRL1 ((0x0020 << 2) + 0xfe00b400)
+#define SRAM_RANGE1_CTRL11 ((0x0021 << 2) + 0xfe00b400)
+#define SRAM_RANGE2_CTRL1 ((0x0022 << 2) + 0xfe00b400)
+#define SRAM_RANGE2_CTRL11 ((0x0023 << 2) + 0xfe00b400)
+#define SRAM_RANGE3_CTRL1 ((0x0024 << 2) + 0xfe00b400)
+#define SRAM_RANGE3_CTRL11 ((0x0025 << 2) + 0xfe00b400)
+#define SRAM_RANGE4_CTRL1 ((0x0026 << 2) + 0xfe00b400)
+#define SRAM_RANGE4_CTRL11 ((0x0027 << 2) + 0xfe00b400)
+#define SRAM_RANGE5_CTRL1 ((0x0028 << 2) + 0xfe00b400)
+#define SRAM_RANGE5_CTRL11 ((0x0029 << 2) + 0xfe00b400)
+#define SRAM_RANGE6_CTRL1 ((0x002a << 2) + 0xfe00b400)
+#define SRAM_RANGE6_CTRL11 ((0x002b << 2) + 0xfe00b400)
+#define SRAM_RANGE7_CTRL1 ((0x002c << 2) + 0xfe00b400)
+#define SRAM_RANGE7_CTRL11 ((0x002d << 2) + 0xfe00b400)
+#define SRAM_SEC_CTRL0 ((0x002e << 2) + 0xfe00b400)
+#define SRAM_REG_LOCK0 ((0x002f << 2) + 0xfe00b400)
+#define SRAM_REG_LOCK1 ((0x0030 << 2) + 0xfe00b400)
+//========================================================================
+// RAMB_SEC_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe00b800
+// -----------------------------------------------
+#define SRAM_RANGE0_STA_B ((0x0000 << 2) + 0xfe00b800)
+#define SRAM_RANGE1_STA_B ((0x0001 << 2) + 0xfe00b800)
+#define SRAM_RANGE2_STA_B ((0x0002 << 2) + 0xfe00b800)
+#define SRAM_RANGE3_STA_B ((0x0003 << 2) + 0xfe00b800)
+#define SRAM_RANGE4_STA_B ((0x0004 << 2) + 0xfe00b800)
+#define SRAM_RANGE5_STA_B ((0x0005 << 2) + 0xfe00b800)
+#define SRAM_RANGE6_STA_B ((0x0006 << 2) + 0xfe00b800)
+#define SRAM_RANGE0_EDA_B ((0x0007 << 2) + 0xfe00b800)
+#define SRAM_RANGE1_EDA_B ((0x0008 << 2) + 0xfe00b800)
+#define SRAM_RANGE2_EDA_B ((0x0009 << 2) + 0xfe00b800)
+#define SRAM_RANGE3_EDA_B ((0x000a << 2) + 0xfe00b800)
+#define SRAM_RANGE4_EDA_B ((0x000b << 2) + 0xfe00b800)
+#define SRAM_RANGE5_EDA_B ((0x000c << 2) + 0xfe00b800)
+#define SRAM_RANGE6_EDA_B ((0x000d << 2) + 0xfe00b800)
+#define SRAM_RANGE0_CTRL0_B ((0x000e << 2) + 0xfe00b800)
+#define SRAM_RANGE0_CTRL01_B ((0x000f << 2) + 0xfe00b800)
+#define SRAM_RANGE1_CTRL0_B ((0x0010 << 2) + 0xfe00b800)
+#define SRAM_RANGE1_CTRL01_B ((0x0011 << 2) + 0xfe00b800)
+#define SRAM_RANGE2_CTRL0_B ((0x0012 << 2) + 0xfe00b800)
+#define SRAM_RANGE2_CTRL01_B ((0x0013 << 2) + 0xfe00b800)
+#define SRAM_RANGE3_CTRL0_B ((0x0014 << 2) + 0xfe00b800)
+#define SRAM_RANGE3_CTRL01_B ((0x0015 << 2) + 0xfe00b800)
+#define SRAM_RANGE4_CTRL0_B ((0x0016 << 2) + 0xfe00b800)
+#define SRAM_RANGE4_CTRL01_B ((0x0017 << 2) + 0xfe00b800)
+#define SRAM_RANGE5_CTRL0_B ((0x0018 << 2) + 0xfe00b800)
+#define SRAM_RANGE5_CTRL01_B ((0x0019 << 2) + 0xfe00b800)
+#define SRAM_RANGE6_CTRL0_B ((0x001a << 2) + 0xfe00b800)
+#define SRAM_RANGE6_CTRL01_B ((0x001b << 2) + 0xfe00b800)
+#define SRAM_RANGE7_CTRL0_B ((0x001c << 2) + 0xfe00b800)
+#define SRAM_RANGE7_CTRL01_B ((0x001d << 2) + 0xfe00b800)
+#define SRAM_RANGE0_CTRL1_B ((0x001e << 2) + 0xfe00b800)
+#define SRAM_RANGE0_CTRL11_B ((0x001f << 2) + 0xfe00b800)
+#define SRAM_RANGE1_CTRL1_B ((0x0020 << 2) + 0xfe00b800)
+#define SRAM_RANGE1_CTRL11_B ((0x0021 << 2) + 0xfe00b800)
+#define SRAM_RANGE2_CTRL1_B ((0x0022 << 2) + 0xfe00b800)
+#define SRAM_RANGE2_CTRL11_B ((0x0023 << 2) + 0xfe00b800)
+#define SRAM_RANGE3_CTRL1_B ((0x0024 << 2) + 0xfe00b800)
+#define SRAM_RANGE3_CTRL11_B ((0x0025 << 2) + 0xfe00b800)
+#define SRAM_RANGE4_CTRL1_B ((0x0026 << 2) + 0xfe00b800)
+#define SRAM_RANGE4_CTRL11_B ((0x0027 << 2) + 0xfe00b800)
+#define SRAM_RANGE5_CTRL1_B ((0x0028 << 2) + 0xfe00b800)
+#define SRAM_RANGE5_CTRL11_B ((0x0029 << 2) + 0xfe00b800)
+#define SRAM_RANGE6_CTRL1_B ((0x002a << 2) + 0xfe00b800)
+#define SRAM_RANGE6_CTRL11_B ((0x002b << 2) + 0xfe00b800)
+#define SRAM_RANGE7_CTRL1_B ((0x002c << 2) + 0xfe00b800)
+#define SRAM_RANGE7_CTRL11_B ((0x002d << 2) + 0xfe00b800)
+#define SRAM_SEC_CTRL0_B ((0x002e << 2) + 0xfe00b800)
+#define SRAM_REG_LOCK0_B ((0x002f << 2) + 0xfe00b800)
+#define SRAM_REG_LOCK1_B ((0x0030 << 2) + 0xfe00b800)
+//========================================================================
+// RAMC_SEC_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe00bc00
+// -----------------------------------------------
+#define SRAM_RANGE0_STA_C ((0x0000 << 2) + 0xfe00bc00)
+#define SRAM_RANGE1_STA_C ((0x0001 << 2) + 0xfe00bc00)
+#define SRAM_RANGE2_STA_C ((0x0002 << 2) + 0xfe00bc00)
+#define SRAM_RANGE3_STA_C ((0x0003 << 2) + 0xfe00bc00)
+#define SRAM_RANGE4_STA_C ((0x0004 << 2) + 0xfe00bc00)
+#define SRAM_RANGE5_STA_C ((0x0005 << 2) + 0xfe00bc00)
+#define SRAM_RANGE6_STA_C ((0x0006 << 2) + 0xfe00bc00)
+#define SRAM_RANGE0_EDA_C ((0x0007 << 2) + 0xfe00bc00)
+#define SRAM_RANGE1_EDA_C ((0x0008 << 2) + 0xfe00bc00)
+#define SRAM_RANGE2_EDA_C ((0x0009 << 2) + 0xfe00bc00)
+#define SRAM_RANGE3_EDA_C ((0x000a << 2) + 0xfe00bc00)
+#define SRAM_RANGE4_EDA_C ((0x000b << 2) + 0xfe00bc00)
+#define SRAM_RANGE5_EDA_C ((0x000c << 2) + 0xfe00bc00)
+#define SRAM_RANGE6_EDA_C ((0x000d << 2) + 0xfe00bc00)
+#define SRAM_RANGE0_CTRL0_C ((0x000e << 2) + 0xfe00bc00)
+#define SRAM_RANGE0_CTRL01_C ((0x000f << 2) + 0xfe00bc00)
+#define SRAM_RANGE1_CTRL0_C ((0x0010 << 2) + 0xfe00bc00)
+#define SRAM_RANGE1_CTRL01_C ((0x0011 << 2) + 0xfe00bc00)
+#define SRAM_RANGE2_CTRL0_C ((0x0012 << 2) + 0xfe00bc00)
+#define SRAM_RANGE2_CTRL01_C ((0x0013 << 2) + 0xfe00bc00)
+#define SRAM_RANGE3_CTRL0_C ((0x0014 << 2) + 0xfe00bc00)
+#define SRAM_RANGE3_CTRL01_C ((0x0015 << 2) + 0xfe00bc00)
+#define SRAM_RANGE4_CTRL0_C ((0x0016 << 2) + 0xfe00bc00)
+#define SRAM_RANGE4_CTRL01_C ((0x0017 << 2) + 0xfe00bc00)
+#define SRAM_RANGE5_CTRL0_C ((0x0018 << 2) + 0xfe00bc00)
+#define SRAM_RANGE5_CTRL01_C ((0x0019 << 2) + 0xfe00bc00)
+#define SRAM_RANGE6_CTRL0_C ((0x001a << 2) + 0xfe00bc00)
+#define SRAM_RANGE6_CTRL01_C ((0x001b << 2) + 0xfe00bc00)
+#define SRAM_RANGE7_CTRL0_C ((0x001c << 2) + 0xfe00bc00)
+#define SRAM_RANGE7_CTRL01_C ((0x001d << 2) + 0xfe00bc00)
+#define SRAM_RANGE0_CTRL1_C ((0x001e << 2) + 0xfe00bc00)
+#define SRAM_RANGE0_CTRL11_C ((0x001f << 2) + 0xfe00bc00)
+#define SRAM_RANGE1_CTRL1_C ((0x0020 << 2) + 0xfe00bc00)
+#define SRAM_RANGE1_CTRL11_C ((0x0021 << 2) + 0xfe00bc00)
+#define SRAM_RANGE2_CTRL1_C ((0x0022 << 2) + 0xfe00bc00)
+#define SRAM_RANGE2_CTRL11_C ((0x0023 << 2) + 0xfe00bc00)
+#define SRAM_RANGE3_CTRL1_C ((0x0024 << 2) + 0xfe00bc00)
+#define SRAM_RANGE3_CTRL11_C ((0x0025 << 2) + 0xfe00bc00)
+#define SRAM_RANGE4_CTRL1_C ((0x0026 << 2) + 0xfe00bc00)
+#define SRAM_RANGE4_CTRL11_C ((0x0027 << 2) + 0xfe00bc00)
+#define SRAM_RANGE5_CTRL1_C ((0x0028 << 2) + 0xfe00bc00)
+#define SRAM_RANGE5_CTRL11_C ((0x0029 << 2) + 0xfe00bc00)
+#define SRAM_RANGE6_CTRL1_C ((0x002a << 2) + 0xfe00bc00)
+#define SRAM_RANGE6_CTRL11_C ((0x002b << 2) + 0xfe00bc00)
+#define SRAM_RANGE7_CTRL1_C ((0x002c << 2) + 0xfe00bc00)
+#define SRAM_RANGE7_CTRL11_C ((0x002d << 2) + 0xfe00bc00)
+#define SRAM_SEC_CTRL0_C ((0x002e << 2) + 0xfe00bc00)
+#define SRAM_REG_LOCK0_C ((0x002f << 2) + 0xfe00bc00)
+#define SRAM_REG_LOCK1_C ((0x0030 << 2) + 0xfe00bc00)
+//
+// Reading file: REG_LIST_DSP_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//========================================================================
+// DSPA - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe030000
+// -----------------------------------------------
+#define DSP_CFG0 ((0x0000 << 2) + 0xfe030000)
+#define DSP_CFG1 ((0x0001 << 2) + 0xfe030000)
+#define DSP_CFG2 ((0x0002 << 2) + 0xfe030000)
+#define DSP_IMPWIRE ((0x0003 << 2) + 0xfe030000)
+#define DSP_RESET_VEC ((0x0004 << 2) + 0xfe030000)
+#define DSP_SEC_CFG0 ((0x0006 << 2) + 0xfe030000)
+#define DSP_SEC_CFG1 ((0x0007 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL0 ((0x0010 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL1 ((0x0011 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL2 ((0x0012 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL3 ((0x0013 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL4 ((0x0014 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL5 ((0x0015 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL6 ((0x0016 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL7 ((0x0017 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL8 ((0x0018 << 2) + 0xfe030000)
+#define DSP_IRQ_STS ((0x001f << 2) + 0xfe030000)
+#define DSP_REMAP0 ((0x0020 << 2) + 0xfe030000)
+#define DSP_REMAP1 ((0x0021 << 2) + 0xfe030000)
+#define DSP_REMAP2 ((0x0022 << 2) + 0xfe030000)
+#define DSP_STS0 ((0x0040 << 2) + 0xfe030000)
+#define DSP_STS1 ((0x0041 << 2) + 0xfe030000)
+#define DSP_STS2 ((0x0042 << 2) + 0xfe030000)
+#define DSP_STS3 ((0x0043 << 2) + 0xfe030000)
+#define DSP_STS4 ((0x0044 << 2) + 0xfe030000)
+#define DSP_STS5 ((0x0045 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_0 ((0x0050 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_1 ((0x0051 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_2 ((0x0052 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_3 ((0x0053 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_4 ((0x0054 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_5 ((0x0055 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_6 ((0x0056 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_7 ((0x0057 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_8 ((0x0058 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_9 ((0x0059 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_10 ((0x005a << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_11 ((0x005b << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_0 ((0x0060 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_1 ((0x0061 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_2 ((0x0062 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_3 ((0x0063 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_4 ((0x0064 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_5 ((0x0065 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_6 ((0x0066 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_7 ((0x0067 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_8 ((0x0068 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_9 ((0x0069 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_10 ((0x006a << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_11 ((0x006b << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_0 ((0x0070 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_1 ((0x0071 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_2 ((0x0072 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_3 ((0x0073 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_4 ((0x0074 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_5 ((0x0075 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_6 ((0x0076 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_7 ((0x0077 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_8 ((0x0078 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_9 ((0x0079 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_10 ((0x007a << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_11 ((0x007b << 2) + 0xfe030000)
+#define DSP_QIF_CTRL ((0x0080 << 2) + 0xfe030000)
+#define DSP_QIF_STS ((0x0081 << 2) + 0xfe030000)
+#define DSP_WRFIFO_TOCPUA ((0x0082 << 2) + 0xfe030000)
+#define DSP_WRFIFO_TOCPUB ((0x0083 << 2) + 0xfe030000)
+#define DSP_WRFIFO_TODSP ((0x0084 << 2) + 0xfe030000)
+#define DSP_RDFIFO_FRCPUA ((0x0088 << 2) + 0xfe030000)
+#define DSP_RDFIFO_FRCPUB ((0x0089 << 2) + 0xfe030000)
+#define DSP_RDFIFO_FRDSP ((0x008a << 2) + 0xfe030000)
+//========================================================================
+// DSPB - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe040000
+// -----------------------------------------------
+#define DSPB_CFG0 ((0x0000 << 2) + 0xfe040000)
+#define DSPB_CFG1 ((0x0001 << 2) + 0xfe040000)
+#define DSPB_CFG2 ((0x0002 << 2) + 0xfe040000)
+#define DSPB_IMPWIRE ((0x0003 << 2) + 0xfe040000)
+#define DSPB_RESET_VEC ((0x0004 << 2) + 0xfe040000)
+#define DSPB_SEC_CFG0 ((0x0006 << 2) + 0xfe040000)
+#define DSPB_SEC_CFG1 ((0x0007 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL0 ((0x0010 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL1 ((0x0011 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL2 ((0x0012 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL3 ((0x0013 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL4 ((0x0014 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL5 ((0x0015 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL6 ((0x0016 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL7 ((0x0017 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL8 ((0x0018 << 2) + 0xfe040000)
+#define DSPB_IRQ_STS ((0x001f << 2) + 0xfe040000)
+#define DSPB_REMAP0 ((0x0020 << 2) + 0xfe040000)
+#define DSPB_REMAP1 ((0x0021 << 2) + 0xfe040000)
+#define DSPB_REMAP2 ((0x0022 << 2) + 0xfe040000)
+#define DSPB_STS0 ((0x0040 << 2) + 0xfe040000)
+#define DSPB_STS1 ((0x0041 << 2) + 0xfe040000)
+#define DSPB_STS2 ((0x0042 << 2) + 0xfe040000)
+#define DSPB_STS3 ((0x0043 << 2) + 0xfe040000)
+#define DSPB_STS4 ((0x0044 << 2) + 0xfe040000)
+#define DSPB_STS5 ((0x0045 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_0 ((0x0050 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_1 ((0x0051 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_2 ((0x0052 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_3 ((0x0053 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_4 ((0x0054 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_5 ((0x0055 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_6 ((0x0056 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_7 ((0x0057 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_8 ((0x0058 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_9 ((0x0059 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_10 ((0x005a << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_11 ((0x005b << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_0 ((0x0060 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_1 ((0x0061 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_2 ((0x0062 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_3 ((0x0063 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_4 ((0x0064 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_5 ((0x0065 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_6 ((0x0066 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_7 ((0x0067 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_8 ((0x0068 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_9 ((0x0069 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_10 ((0x006a << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_11 ((0x006b << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_0 ((0x0070 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_1 ((0x0071 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_2 ((0x0072 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_3 ((0x0073 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_4 ((0x0074 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_5 ((0x0075 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_6 ((0x0076 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_7 ((0x0077 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_8 ((0x0078 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_9 ((0x0079 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_10 ((0x007a << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_11 ((0x007b << 2) + 0xfe040000)
+#define DSPB_QIF_CTRL ((0x0080 << 2) + 0xfe040000)
+#define DSPB_QIF_STS ((0x0081 << 2) + 0xfe040000)
+#define DSPB_WRFIFO_TOCPUA ((0x0082 << 2) + 0xfe040000)
+#define DSPB_WRFIFO_TOCPUB ((0x0083 << 2) + 0xfe040000)
+#define DSPB_WRFIFO_TODSP ((0x0084 << 2) + 0xfe040000)
+#define DSPB_RDFIFO_FRCPUA ((0x0088 << 2) + 0xfe040000)
+#define DSPB_RDFIFO_FRCPUB ((0x0089 << 2) + 0xfe040000)
+#define DSPB_RDFIFO_FRDSP ((0x008a << 2) + 0xfe040000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: REG_LIST_DSP_RTL.h
+//
+//
+// Reading file: REG_LIST_DOS_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// `define APB_DOS_VDEC_ADDR_OFFSET 6'h00 // VDEC 1
+// -----------------------------------------------
+// -----------------------------------------------
+// `define APB_DOS_HCODEC_ADDR_OFFSET 6'h10 // HCODEC 1
+// -----------------------------------------------
+// -----------------------------------------------
+// `define APB_DOS_VDEC2_ADDR_OFFSET 6'h20 // VDEC 2 // Share with HEVC2
+// -----------------------------------------------
+// -----------------------------------------------
+// `define APB_DOS_HEVC2_ADDR_OFFSET 6'h20 // HEVC 2 // Share with VDEC2
+// -----------------------------------------------
+// -----------------------------------------------
+// `define APB_DOS_HEVC_ADDR_OFFSET 6'h30 // HEVC
+// -----------------------------------------------
+//========================================================================
+// DOS - Registers
+//========================================================================
+// VDEC
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe060000
+// -----------------------------------------------
+// HCODEC
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe064000
+// -----------------------------------------------
+// -----------------------------------------------
+// `define DOS_HCODEC_ASSIST_CBUS_BASE 8'h00
+// -----------------------------------------------
+#define HCODEC_ASSIST_MMC_CTRL0 ((0x0001 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MMC_CTRL1 ((0x0002 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MMC_CTRL2 ((0x0003 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MMC_CTRL3 ((0x0004 << 2) + 0xfe064000)
+// bit[11] canvas_blk32_wr
+// bit[10] canvas_blk32
+// bit[9] Reserved
+// bit[8] canvas_index_wr
+// bit[7:0] canvas_index
+#define HCODEC_ASSIST_CANVAS_BLK32 ((0x0005 << 2) + 0xfe064000)
+//cfg_soft_rst = mfdin_reg0_crst[0]; // Soft Reset
+//cfg_cg_cfe = mfdin_reg0_crst[1]; // Clock Gating Forcing Enable
+//cfg_dbuf_rst = mfdin_reg0_crst[2]; // Reset DBUF information
+#define HCODEC_MFDIN_REG0_CRST ((0x0008 << 2) + 0xfe064000)
+//cfg_iformat = mfdin_reg1_ctrl[3:0]; // Data In Format: 0 :CANVAS 422 YCbCr<-one canvas,
+ // 1 :CANVAS 444 YCbCr(or RGB)<-one canvas,
+ // 2 :CANVAS 420 Y<-one CrCb<-one (NV21)
+ // 3 :CANVAS 420 Y<-one CbCr<-one (NV12)
+ // 4 :CANVAS 420 Y<-one Cb<-one Cr<-one
+ // 5 :CANVAS 444 Y<-one Cb<-one Cr<-one
+ // 6 : Reserved for other canvas mode
+ // 7 : should combine with cfg_ifmt_extra, for 10-12bits
+ // 8 :LINEAR RGB888 (24bit)
+ // 9 :LINEAR RGB565 (16bit)
+ // 10:LINEAR YUV422
+ // 11:LINEAR YUV420 (Note:Legacy mode not supported)
+ // 12~15: Reserved for other linear mode
+//cfg_oformat = mfdin_reg1_ctrl[5:4]; // Data Out Format: 0:420 1:422 2:444 3:reserved
+//cfg_dsample_enable= mfdin_reg1_ctrl[6]; // Downsample Enable
+//cfg_dsample_trunc = mfdin_reg1_ctrl[7]; // Downsample Addition Option: 0:Round 1:Truncated
+//cfg_block_ysize = mfdin_reg1_ctrl[8]; // 0:block-y-size=16, 1:block-y-size=8(for JPEG's efficiency)
+//cfg_interp_enable = mfdin_reg1_ctrl[9]; // Chroma Interpolation Enable
+//cfg_interp_mode = mfdin_reg1_ctrl[11:10];// 0:average round 1:average truncated 2:repeat left 3:repeat right
+//cfg_r2y_enable = mfdin_reg1_ctrl[12]; // RGb->YUV Enable
+//cfg_r2y_mode = mfdin_reg1_ctrl[14:13];// RGb->YUV Mode
+//cfg_rgb565_mode = mfdin_reg1_ctrl[15]; // RGB565 mode: 0:fill zero in tail 1:fill zero in head
+//cfg_ifmt_extra = mfdin_reg1_ctrl[17:16];// when cfg_iformat==7,
+ // 0: CANVAS 12bit 422, YCbCr<-one canvas{...Y1[11:0],C1[11:0],Y0[11:0],C0[11:0]}
+ // 1: CANVAS 10bit 444, YCbCr<-one canvas{...2'b0,Y0[9:0],U0[9:0],V0[9:0]}
+ // 2: CANVAS 10bit 422, YCbCr<-one canvas{...Y1[9:0],C1[9:0],Y0[9:0],C0[9:0]}
+//cfg_reserved1 = mfdin_reg1_ctrl[18]; // Reserved
+//cfg_nr_enable = mfdin_reg1_ctrl[19]; // Noise Reduction Enable
+//cfg_outofpic = mfdin_reg1_ctrl[28:20];// Out Of Picture Control: [8]mode:0:extend 1:fixed, [7:0]fixed value
+//cfg_rd_blktype = mfdin_reg1_ctrl[30:29];// Block Type: 0:H264_I_PIC_ALL_4x4, 1:H264_P_PIC_Y_16x16_C_8x8, 2:JPEG_ALL_8x8, 3:Reserved
+//cfg_rd_nonycintl = mfdin_reg1_ctrl[31]; // 0:YC interleaved 1:YC non-interleaved(for JPEG)
+#define HCODEC_MFDIN_REG1_CTRL ((0x0009 << 2) + 0xfe064000)
+//mfdin_reg2: DEBUG Only Status
+#define HCODEC_MFDIN_REG2_STAT ((0x000a << 2) + 0xfe064000)
+//cfg_canvas_index0 = mfdin_reg3_canv[7:0]; //canvas index 0
+//cfg_canvas_index1 = mfdin_reg3_canv[15:8]; //canvas index 1
+//cfg_canvas_index2 = mfdin_reg3_canv[23:16];//canvas index 2
+//cfg_canv_idx0_bppx = mfdin_reg3_canv[25:24];//canvas bytes per pixel in x direction for index0, 0:half 1:1 2:2 3:3
+//cfg_canv_idx1_bppx = mfdin_reg3_canv[27:26];//canvas bytes per pixel in x direction for index1, 0:half 1:1 2:2 3:3
+//cfg_canv_idx0_bppy = mfdin_reg3_canv[29:28];//canvas bytes per pixel in y direction for index0, 0:half 1:1 2:2 3:3
+//cfg_canv_idx1_bppy = mfdin_reg3_canv[31:30];//canvas bytes per pixel in y direction for index1, 0:half 1:1 2:2 3:3
+#define HCODEC_MFDIN_REG3_CANV ((0x000b << 2) + 0xfe064000)
+//cfg_bytes_per_line = mfdin_reg4_lnr0[15:0]; //linear Bytes per line
+//cfg_linear_bytes4p = mfdin_reg4_lnr0[17:16]; //linear (Bytes per pixel) - 1
+//cfg_linear_dbl2line = mfdin_reg4_lnr0[18]; //linear double size for odd line
+#define HCODEC_MFDIN_REG4_LNR0 ((0x000c << 2) + 0xfe064000)
+//cfg_base_address = mfdin_reg5_lnr1[31:0]; //linear base address
+#define HCODEC_MFDIN_REG5_LNR1 ((0x000d << 2) + 0xfe064000)
+//assign cfg_r2y_trunc = mfdin_reg6_dcfg[9]; //RGb->YUV Addition Option: 0:Round 1:Truncated
+//assign cfg_dma_ugt = mfdin_reg6_dcfg[8]; //DMA Urgent
+//assign cfg_dma_thread_id = mfdin_reg6_dcfg[7:6]; //DMA Thread ID
+//assign cfg_dma_burst_num = mfdin_reg6_dcfg[5:0]; //DMA Burst Number
+#define HCODEC_MFDIN_REG6_DCFG ((0x000e << 2) + 0xfe064000)
+//cfg_soft_cmd = mfdin_reg7_scmd; // Soft Command [28]selfcleared start,[27:14]dmb_x,[13:0]dmb_y
+#define HCODEC_MFDIN_REG7_SCMD ((0x000f << 2) + 0xfe064000)
+//cfg_pic_xsize = mfdin_reg8_dmbl[23:12]; //pixel (x,y) at the begining of last dmb in the picturem, picture x size
+//cfg_pic_ysize = mfdin_reg8_dmbl[11:0]; //picture y size
+#define HCODEC_MFDIN_REG8_DMBL ((0x0010 << 2) + 0xfe064000)
+//cfg_endian = mfdin_reg9_endn; //Endian Control
+#define HCODEC_MFDIN_REG9_ENDN ((0x0011 << 2) + 0xfe064000)
+//cfg_canv_biasx = mfdin_rega_cav1[23:12]; //canvas bias address x
+//cfg_canv_biasy = mfdin_rega_cav1[11:0]; //canvas bias address y
+#define HCODEC_MFDIN_REGA_CAV1 ((0x0012 << 2) + 0xfe064000)
+//cfg_amp_en = mfdin_regb_ampc[24]; //Amplitude Enable
+//cfg_amp_cy = mfdin_regb_ampc[23:16]; //Amplitude Coeff Y
+//cfg_amp_cu = mfdin_regb_ampc[15:8]; //Amplitude Coeff U
+//cfg_amp_cv = mfdin_regb_ampc[7:0]; //Amplitude Coeff V
+#define HCODEC_MFDIN_REGB_AMPC ((0x0013 << 2) + 0xfe064000)
+//cfg_mb_end = mfdin_regc_mblp; // Soft Command [28]mb end enable,[27:14]dmb_x,[13:0]dmb_y
+#define HCODEC_MFDIN_REGC_MBLP ((0x0014 << 2) + 0xfe064000)
+// cfg_y_snr_en = mfdin_reg0d[0];
+// cfg_y_snr_err_norm = mfdin_reg0d[1];
+// [3:0] cfg_y_snr_gau_bld_core = mfdin_reg0d[5:2];
+// [7:0] cfg_y_snr_gau_bld_ofst = mfdin_reg0d[13:6];
+// [5:0] cfg_y_snr_gau_bld_rate = mfdin_reg0d[19:14];
+// [5:0] cfg_y_snr_gau_alp0_min = mfdin_reg0d[25:20];
+// [5:0] cfg_y_snr_gau_alp0_max = mfdin_reg0d[31:26];
+#define HCODEC_MFDIN_REG0D ((0x0015 << 2) + 0xfe064000)
+// cfg_y_tnr_en = mfdin_reg0e[0];
+// cfg_y_tnr_mc_en = mfdin_reg0e[1];
+// cfg_y_tnr_txt_mode = mfdin_reg0e[2];
+// [3:0] cfg_y_tnr_mot_sad_margin = mfdin_reg0e[6:3];
+// [5:0] cfg_y_tnr_alpha_min = mfdin_reg0e[12:7];
+// [5:0] cfg_y_tnr_alpha_max = mfdin_reg0e[18:13];
+// [5:0] cfg_y_tnr_deghost_os = mfdin_reg0e[24:19];
+#define HCODEC_MFDIN_REG0E ((0x0016 << 2) + 0xfe064000)
+// [3:0] cfg_y_tnr_mot_cortxt_rate = mfdin_reg0f[3:0];
+// [7:0] cfg_y_tnr_mot_distxt_ofst = mfdin_reg0f[15:8];
+// [3:0] cfg_y_tnr_mot_distxt_rate = mfdin_reg0f[7:4];
+// [7:0] cfg_y_tnr_mot_dismot_ofst = mfdin_reg0f[23:16];
+// [7:0] cfg_y_tnr_mot_frcsad_lock = mfdin_reg0f[31:24];
+#define HCODEC_MFDIN_REG0F ((0x0017 << 2) + 0xfe064000)
+// [7:0] cfg_y_tnr_mot2alp_frc_gain = mfdin_reg10[7:0];
+// [7:0] cfg_y_tnr_mot2alp_nrm_gain = mfdin_reg10[15:8];
+// [7:0] cfg_y_tnr_mot2alp_dis_gain = mfdin_reg10[23:16];
+// [5:0] cfg_y_tnr_mot2alp_dis_ofst = mfdin_reg10[29:24];
+#define HCODEC_MFDIN_REG10 ((0x0018 << 2) + 0xfe064000)
+// [7:0] cfg_y_bld_beta2alp_rate = mfdin_reg11[7:0];
+// [5:0] cfg_y_bld_beta_min = mfdin_reg11[13:8];
+// [5:0] cfg_y_bld_beta_max = mfdin_reg11[19:14];
+#define HCODEC_MFDIN_REG11 ((0x0019 << 2) + 0xfe064000)
+// REG12~16 for Chroma, same as Luma
+#define HCODEC_MFDIN_REG12 ((0x001a << 2) + 0xfe064000)
+#define HCODEC_MFDIN_REG13 ((0x001b << 2) + 0xfe064000)
+#define HCODEC_MFDIN_REG14 ((0x001c << 2) + 0xfe064000)
+#define HCODEC_MFDIN_REG15 ((0x001d << 2) + 0xfe064000)
+#define HCODEC_MFDIN_REG16 ((0x001e << 2) + 0xfe064000)
+#define HCODEC_MFDIN_REG17 ((0x001f << 2) + 0xfe064000)
+#define HCODEC_MFDIN_REG18 ((0x0020 << 2) + 0xfe064000)
+#define HCODEC_MFDIN_REG19 ((0x0021 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT0 ((0x0025 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT1 ((0x0026 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT2 ((0x0027 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT3 ((0x0028 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT4 ((0x0029 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT5 ((0x002a << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT6 ((0x002b << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT7 ((0x002c << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT8 ((0x002d << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT9 ((0x002e << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INTA ((0x002f << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INTB ((0x0030 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INTC ((0x0031 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INTD ((0x0032 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INTE ((0x0033 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INTF ((0x0034 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT0 ((0x0035 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT1 ((0x0036 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT2 ((0x0037 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT3 ((0x0038 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT4 ((0x0039 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT5 ((0x003a << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT6 ((0x003b << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT7 ((0x003c << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT8 ((0x003d << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT9 ((0x003e << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INTA ((0x003f << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INTB ((0x0040 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INTC ((0x0041 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INTD ((0x0042 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INTE ((0x0043 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INTF ((0x0044 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBX_SSEL ((0x0045 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_TIMER0_LO ((0x0060 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_TIMER0_HI ((0x0061 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_TIMER1_LO ((0x0062 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_TIMER1_HI ((0x0063 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_DMA_INT ((0x0064 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_DMA_INT_MSK ((0x0065 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_DMA_INT2 ((0x0066 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_DMA_INT_MSK2 ((0x0067 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX0_IRQ_REG ((0x0070 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX0_CLR_REG ((0x0071 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX0_MASK ((0x0072 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX0_FIQ_SEL ((0x0073 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX1_IRQ_REG ((0x0074 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX1_CLR_REG ((0x0075 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX1_MASK ((0x0076 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX1_FIQ_SEL ((0x0077 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX2_IRQ_REG ((0x0078 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX2_CLR_REG ((0x0079 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX2_MASK ((0x007a << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX2_FIQ_SEL ((0x007b << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AXI_CTRL ((0x007c << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AXI_STATUS ((0x007d << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AXI_SETTING_VLC ((0x007e << 2) + 0xfe064000)
+//------------------------------------------------------------------------------
+// HCODEC IQIDCT module level register offset
+//------------------------------------------------------------------------------
+// `define DOS_HCODEC_VCPU_CBUS_BASE 8'h03
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe064c00
+// -----------------------------------------------
+//
+// Reading file: hcodec_vcpu_regs.h
+//
+//========================================================================
+// VCPU module level register offset
+//========================================================================
+// -----------------------------------------------
+// `define DOS_HCODEC_VCPU_CBUS_BASE 8'h03
+// -----------------------------------------------
+#define HCODEC_MSP ((0x0000 << 2) + 0xfe064c00)
+#define HCODEC_MPSR ((0x0001 << 2) + 0xfe064c00)
+#define HCODEC_MINT_VEC_BASE ((0x0002 << 2) + 0xfe064c00)
+#define HCODEC_MCPU_INTR_GRP ((0x0003 << 2) + 0xfe064c00)
+#define HCODEC_MCPU_INTR_MSK ((0x0004 << 2) + 0xfe064c00)
+#define HCODEC_MCPU_INTR_REQ ((0x0005 << 2) + 0xfe064c00)
+//`define HCODEC_MPC_P 8'h06
+//`define HCODEC_MPC_D 8'h07
+//`define HCODEC_MPC_E 8'h08
+//`define HCODEC_MPC_W 8'h09
+//`define HCODEC_MINDEX0_REG 8'h0a
+//`define HCODEC_MINDEX1_REG 8'h0b
+//`define HCODEC_MINDEX2_REG 8'h0c
+//`define HCODEC_MINDEX3_REG 8'h0d
+//`define HCODEC_MINDEX4_REG 8'h0e
+//`define HCODEC_MINDEX5_REG 8'h0f
+//`define HCODEC_MINDEX6_REG 8'h10
+//`define HCODEC_MINDEX7_REG 8'h11
+//`define HCODEC_MMIN_REG 8'h12
+//`define HCODEC_MMAX_REG 8'h13
+//`define HCODEC_MBREAK0_REG 8'h14
+//`define HCODEC_MBREAK1_REG 8'h15
+//`define HCODEC_MBREAK2_REG 8'h16
+//`define HCODEC_MBREAK3_REG 8'h17
+//`define HCODEC_MBREAK_TYPE 8'h18
+//`define HCODEC_MBREAK_CTRL 8'h19
+//`define HCODEC_MBREAK_STAUTS 8'h1a
+//`define HCODEC_MDB_ADDR_REG 8'h1b
+//`define HCODEC_MDB_DATA_REG 8'h1c
+//`define HCODEC_MDB_CTRL 8'h1d
+//`define HCODEC_MSFTINT0 8'h1e
+//`define HCODEC_MSFTINT1 8'h1f
+//
+#define HCODEC_CSP ((0x0020 << 2) + 0xfe064c00)
+#define HCODEC_CPSR ((0x0021 << 2) + 0xfe064c00)
+//`define HCODEC_CINT_VEC_BASE 8'h22
+//`define HCODEC_CCPU_INTR_GRP 8'h23
+//`define HCODEC_CCPU_INTR_MSK 8'h24
+//`define HCODEC_CCPU_INTR_REQ 8'h25
+//`define HCODEC_CPC_P 8'h26
+//`define HCODEC_CPC_D 8'h27
+//`define HCODEC_CPC_E 8'h28
+//`define HCODEC_CPC_W 8'h29
+//`define HCODEC_CINDEX0_REG 8'h2a
+//`define HCODEC_CINDEX1_REG 8'h2b
+//`define HCODEC_CINDEX2_REG 8'h2c
+//`define HCODEC_CINDEX3_REG 8'h2d
+//`define HCODEC_CINDEX4_REG 8'h2e
+//`define HCODEC_CINDEX5_REG 8'h2f
+//`define HCODEC_CINDEX6_REG 8'h30
+//`define HCODEC_CINDEX7_REG 8'h31
+//`define HCODEC_CMIN_REG 8'h32
+//`define HCODEC_CMAX_REG 8'h33
+//`define HCODEC_CBREAK0_REG 8'h34
+//`define HCODEC_CBREAK1_REG 8'h35
+//`define HCODEC_CBREAK2_REG 8'h36
+//`define HCODEC_CBREAK3_REG 8'h37
+//`define HCODEC_CBREAK_TYPE 8'h38
+//`define HCODEC_CBREAK_CTRL 8'h39
+//`define HCODEC_CBREAK_STAUTS 8'h3a
+//`define HCODEC_CDB_ADDR_REG 8'h3b
+//`define HCODEC_CDB_DATA_REG 8'h3c
+//`define HCODEC_CDB_CTRL 8'h3d
+//`define HCODEC_CSFTINT0 8'h3e
+//`define HCODEC_CSFTINT1 8'h3f
+//
+#define HCODEC_IMEM_DMA_CTRL ((0x0040 << 2) + 0xfe064c00)
+#define HCODEC_IMEM_DMA_ADR ((0x0041 << 2) + 0xfe064c00)
+#define HCODEC_IMEM_DMA_COUNT ((0x0042 << 2) + 0xfe064c00)
+//// bit[29:24] A_brst_num_imem
+//// bit[21:16] A_id_imem
+//// bit[11:0] wrrsp_count_imem (reserved)
+#define HCODEC_WRRSP_IMEM ((0x0043 << 2) + 0xfe064c00)
+//
+//`define HCODEC_LMEM_DMA_CTRL 8'h50
+//`define HCODEC_LMEM_DMA_ADR 8'h51
+//`define HCODEC_LMEM_DMA_COUNT 8'h52
+//// bit[29:24] A_brst_num_lmem
+//// bit[21:16] A_id_lmem
+//// bit[11:0] wrrsp_count_lmem
+//`define HCODEC_WRRSP_LMEM 8'h53
+//
+//`define HCODEC_MAC_CTRL1 8'h60
+//`define HCODEC_ACC0REG1 8'h61
+//`define HCODEC_ACC1REG1 8'h62
+//
+//`define HCODEC_MAC_CTRL2 8'h70
+//`define HCODEC_ACC0REG2 8'h71
+//`define HCODEC_ACC1REG2 8'h72
+//`define HCODEC_CPU_TRACE 8'h80
+//
+//
+// Closing file: hcodec_vcpu_regs.h
+//
+//------------------------------------------------------------------------------
+// -----------------------------------------------
+// `define DOS_HCODEC_HDEC_CBUS_BASE 8'h09
+// -----------------------------------------------
+//------------------------------------------------------------------------------
+// HENC module level register offset
+//------------------------------------------------------------------------------
+// `define DOS_HCODEC_HENC_CBUS_BASE 8'h0a
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe066800
+// -----------------------------------------------
+//
+// Reading file: henc_regs.h
+//
+//========================================================================
+// MDEC module level register offset
+//========================================================================
+// -----------------------------------------------
+// `define DOS_HCODEC_HENC_CBUS_BASE 8'h0a
+// -----------------------------------------------
+#define HENC_SCRATCH_0 ((0x00c0 << 2) + 0xfe066800)
+#define HENC_SCRATCH_1 ((0x00c1 << 2) + 0xfe066800)
+#define HENC_SCRATCH_2 ((0x00c2 << 2) + 0xfe066800)
+#define HENC_SCRATCH_3 ((0x00c3 << 2) + 0xfe066800)
+#define HENC_SCRATCH_4 ((0x00c4 << 2) + 0xfe066800)
+#define HENC_SCRATCH_5 ((0x00c5 << 2) + 0xfe066800)
+#define HENC_SCRATCH_6 ((0x00c6 << 2) + 0xfe066800)
+#define HENC_SCRATCH_7 ((0x00c7 << 2) + 0xfe066800)
+#define HENC_SCRATCH_8 ((0x00c8 << 2) + 0xfe066800)
+#define HENC_SCRATCH_9 ((0x00c9 << 2) + 0xfe066800)
+#define HENC_SCRATCH_A ((0x00ca << 2) + 0xfe066800)
+#define HENC_SCRATCH_B ((0x00cb << 2) + 0xfe066800)
+#define HENC_SCRATCH_C ((0x00cc << 2) + 0xfe066800)
+#define HENC_SCRATCH_D ((0x00cd << 2) + 0xfe066800)
+#define HENC_SCRATCH_E ((0x00ce << 2) + 0xfe066800)
+#define HENC_SCRATCH_F ((0x00cf << 2) + 0xfe066800)
+#define HENC_SCRATCH_G ((0x00d0 << 2) + 0xfe066800)
+#define HENC_SCRATCH_H ((0x00d1 << 2) + 0xfe066800)
+#define HENC_SCRATCH_I ((0x00d2 << 2) + 0xfe066800)
+#define HENC_SCRATCH_J ((0x00d3 << 2) + 0xfe066800)
+#define HENC_SCRATCH_K ((0x00d4 << 2) + 0xfe066800)
+#define HENC_SCRATCH_L ((0x00d5 << 2) + 0xfe066800)
+#define HENC_SCRATCH_M ((0x00d6 << 2) + 0xfe066800)
+#define HENC_SCRATCH_N ((0x00d7 << 2) + 0xfe066800)
+// bit [7:0] data_feed_buff_id
+#define IE_DATA_FEED_BUFF_INFO ((0x00d8 << 2) + 0xfe066800)
+//
+// Closing file: henc_regs.h
+//
+//------------------------------------------------------------------------------
+// -----------------------------------------------
+// `define DOS_HCODEC_VLD_CBUS_BASE 8'h0c
+// -----------------------------------------------
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+// VLC module level register offset
+//------------------------------------------------------------------------------
+// `define DOS_HCODEC_VLC_CBUS_BASE 8'h0d
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe067400
+// -----------------------------------------------
+//
+// Reading file: vlc_regs.h
+//
+//========================================================================
+// VLC module level register offset
+//========================================================================
+// -----------------------------------------------
+// `define DOS_HCODEC_VLC_CBUS_BASE 8'h0d
+// -----------------------------------------------
+// Bit[31:28] - henc_status
+// Bit[27:9] - reserved
+// Bit[8] disable_UVLC_SKIP_fix
+// Bit[7] mc_hcmd_buff_enable
+// Bit[6] mc_hcmd_use_mc_hcmd_buff
+// Bit[5] mc_hcmd_use_mc_hcmd_hw_start
+// Bit[4] no_mc_out_null_non_skipped_mb
+// Bit[3] mc_out_even_skipped_mb
+// Bit[2] - hcmd_enable
+// Bit[1] - vlc_control_enable (0 will treat as soft_reset)
+// Bit[0] - vlc_input_enable (enable input interface)
+#define VLC_STATUS_CTRL ((0x0000 << 2) + 0xfe067400)
+// Bit [31] - small_luma_ignore_chroma
+// Bit[30:16] - Reserved
+// Bit [15] - enable_free_clk_mc_hcmd_buff
+// Bit [14] - enable_free_clk_reg
+// Bit [13] - enable_free_clk_stream
+// Bit [12] - enable_free_clk_pre_buff
+// Bit [11] - enable_free_clk_vb_buff
+// Bit [10] - enable_free_clk_dc_input
+// Bit [9] - enable_free_clk_input
+// Bit [8] - enable_free_clk_mv_cal
+// Bit [7] - enable_free_clk_status
+// Bit [6] - enable_free_clk_mc_dblk_cmd_if
+// Bit [5] - disable_mvd_enc_finished
+// Bit [4] - I16MB_share_ipred_mode_with_I4MB
+// Bit [3] - fixed_picture_qp
+// Bit [2] - use_set_b8_mode ( not used now)
+// Bit [1] - use_set_mb_skip_run
+// Bit [0] - pop_coeff_even_all_zero
+#define VLC_CONFIG ((0x0001 << 2) + 0xfe067400)
+// --------------------------------------------
+// Bitstream DDR Interface
+// --------------------------------------------
+#define VLC_VB_START_PTR ((0x0010 << 2) + 0xfe067400)
+#define VLC_VB_END_PTR ((0x0011 << 2) + 0xfe067400)
+#define VLC_VB_WR_PTR ((0x0012 << 2) + 0xfe067400)
+// Read Only, VLC_VB_SW_RD_PTR or VLC_VB_HW_RD_PTR
+#define VLC_VB_RD_PTR ((0x0013 << 2) + 0xfe067400)
+#define VLC_VB_SW_RD_PTR ((0x0014 << 2) + 0xfe067400)
+// Read Only
+#define VLC_VB_LEFT ((0x0015 << 2) + 0xfe067400)
+// VB FIFO Control
+// bit [31:24] vb_full_int_enable_cpu[7:0]
+// bit [23:16] vb_full_int_enable_amrisc[7:0]
+// -bit 23 Video BUFFER LEFT < 0x400 Bytes
+// -bit 22 Video BUFFER LEFT < 0x200 Bytes
+// -bit 21 Video BUFFER LEFT < 0x100 Bytes
+// -bit 20 Video BUFFER LEFT < 0x80 Bytes
+// -bit 19 Video BUFFER LEFT < 0x40 Bytes
+// -bit 18 Video BUFFER LEFT < 0x20 Bytes
+// -bit 17 vbfifo left < 16 double words (8x64bits)
+// -bit 16 vbfifo left < 8 double words (4x64bits)
+// bit [15] wr_ptr_int_enable_cpu
+// bit [14] wr_ptr_int_enable_amrisc
+// bit [13] wr_ptr_int (Read Only, write 1 will clear)
+// bit [12] vb_full_int_enable_cpu(Read Only)
+// bit [11] vb_full_int_enable_amrisc(Read Only)
+// bit [10] reserved
+// bit [9] use_vb_hw_rd_ptr
+// bit [8] vb_always_ready Set to 1 to ignore vb_level blocking DDR write
+// bit [7] vb_ready_for_transfer (Read Only)
+// bit [6] data_ready_for_transfer (Read Only)
+// bits [5:3] vb_endian Set VB Endian inside DDR memory
+// bit [2] vb_write_busy Read Only - indicate DDR write busy
+// bit [1] vb_write_en Set to 1 to enable writing data to DDR memory
+// bit [0] vb_soft_reset Soft reset
+#define VLC_VB_CONTROL ((0x0016 << 2) + 0xfe067400)
+// bit 31 transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request // default : 0
+// bit 30 A_urgent // default : 0
+// bit 29:24 A_brst_num // default : 0x3f
+// bit 23:22 reserved
+// bit 21:16 A_id // default : 0x20
+// bit 15:0 vb_left_hold // default : 0
+#define VLC_VB_MEM_CTL ((0x0017 << 2) + 0xfe067400)
+// vb_wr_ptr address to generate interrupt
+#define VLC_VB_INT_PTR ((0x0018 << 2) + 0xfe067400)
+// bit[31:12] reserved
+// bit[11:0] vlc_wrrsp_count
+#define VLC_WRRSP ((0x0019 << 2) + 0xfe067400)
+#define VLC_TOTAL_BYTES ((0x001a << 2) + 0xfe067400)
+// bit [31:26] reserved
+// bit [25] vb_flush
+// bit [24] vb_reg_ready
+// bit [23:16] vb_buff_left -- Read only
+// bit [15:8] vb_buff_wr_point -- RW
+// bit [7:0] vb_buff_rd_point -- RW
+#define VLC_VB_BUFF ((0x001b << 2) + 0xfe067400)
+// bit[31] flush_vlc_pre_buff
+// bit[30:27] reserved
+// bit[26:24] vb_pre_buff_level
+// bit[23:0] vb_pre_buff_data[55:32]
+#define VLC_VB_PRE_BUFF_HI ((0x001c << 2) + 0xfe067400)
+// bit[31:0] vb_pre_buff_data[31:0]
+#define VLC_VB_PRE_BUFF_LOW ((0x001d << 2) + 0xfe067400)
+// bit[31] stream_encap_enable // 0x0000(00-03) will be changed to 0x000003(00-03) if enabled
+// bit[30:29] stream_encap_delay // delay bytes for encap used
+// bit[28:24] stream_buff_point
+// bit[23:0] stream_buff_data
+#define VLC_STREAM_BUFF ((0x001e << 2) + 0xfe067400)
+// bit[31] push_stream_block - Read Only (Will set if vb_buff full)
+// bit[30] push_stream_busy - Read Only (busy when output one byte from stream_buf (max 2 clocks for 8 bits push)
+// bit[29:28] stream_encap_status - Read Only
+// bit[27:21] reserved
+// Long Mode : (Amrisc need movilo and mvihi high to set stream_info)
+// bit[20:16] push_stream_long_length (0 or 31 : Mid or Short mode)
+// bit[15:0] push_stream_data
+// Mid Mode : (Amrisc need movi to set stream_info)
+// bit[15:12]] push_stream_mid_length (1-12 : mid mode active, 0-short mode, 15 - byte align)
+// bit[11:0] push_stream_data
+// Short Mode : (Amrisc can use mtspi to push stream directely)
+// bit[7:5] push_stream_short_length (0-5 : short length, else - invalid)
+// bit[4:0] push_stream_data
+#define VLC_PUSH_STREAM ((0x001f << 2) + 0xfe067400)
+// bit[15:8] ELEMENT_LENGTH
+// bit[7:1] reserved
+// bit[0] Write - push start, Read - Push Busy
+#define VLC_PUSH_ELEMENT ((0x0020 << 2) + 0xfe067400)
+#define VLC_ELEMENT_DATA ((0x0021 << 2) + 0xfe067400)
+// bit[9] reset_last_dquant_ne_zero
+// bit[8] set_last_dquant_ne_zero
+// bit[7] hcmd_intra_use_sw_info
+// bit[6] hcmd_use_sw_info
+// bit[5] always_use_info_0_cbp_blk
+// bit[4] always_update_info_0_cbp_blk
+// bit[3] reset_left_mb_wr
+// bit[2] reset_top_mb_wr
+// bit[1] set_left_mb_wr
+// bit[0] set_top_mb_wr
+#define VLC_SPECIAL_CTL ((0x0022 << 2) + 0xfe067400)
+// bit[28] left_intra
+// bit[27:22] left_quant
+// bit[21:16] left_quant_c
+// bit[12] top_intra
+// bit[11:6] top_quant
+// bit[5:0] top_quant_c
+#define VLC_HCMD_T_L_INFO ((0x0023 << 2) + 0xfe067400)
+// bit[12] cur_intra
+// bit[11:6] cur_quant
+// bit[5:0] cur_quant_c
+#define VLC_HCMD_CUR_INFO ((0x0024 << 2) + 0xfe067400)
+// bit[13] top_left_info_in_data_mv_cal
+// bit[12] only_use_info_0_top_left_in_I
+// bit[11] top_left_info_in_data
+// bit[10] early_mix_mc_hcmd
+// bit[9] update_top_left_mix
+// bit[8] p_top_left_mix
+// bit[7] mv_cal_mixed_type
+// bit[6] mc_hcmd_mixed_type
+// bit[5] use_seperate_int_control
+// bit[4] hcmd_intra_use_q_info
+// bit[3] hcmd_left_use_prev_info
+// bit[2] hcmd_use_q_info
+// bit[1] use_q_delta_quant
+// bit[0] detect_I16_from_I4
+#define VLC_ADV_CONFIG ((0x0025 << 2) + 0xfe067400)
+// 31 - use_hcmd_mb_xy_auto
+//23:16 - hcmd_max_mb_x
+//15:8 - hcmd_mb_y_auto
+// 7:0 - hcmd_mb_x_auto
+#define VLC_HCMD_MBXY_AUTO ((0x0026 << 2) + 0xfe067400)
+// bit[31:0] vlc_int_control_inter -- will be used when use_seperate_int_control is set
+#define VLC_INT_CONTROL_INTER ((0x002f << 2) + 0xfe067400)
+// --------------------------------------------
+// Picture VLC
+// --------------------------------------------
+// (&(int|(~AND_enable))|(|(int&OR_enable)))
+// bit[31] OR interrupt Enable Reserved
+// bit[30] OR interrupt Enable for mv_busy
+// bit[29] OR interrupt Enable for b8_mode_busy
+// bit[28] OR interrupt Enable for mb_skip_run_busy
+// bit[27] OR interrupt Enable for cbp_busy
+// bit[26] OR interrupt Enable for Reserved
+// bit[25] OR interrupt Enable for Reserved
+// bit[24] OR interrupt Enable for mb_info_busy
+// bit[23] AND interrupt Enable Reserved
+// bit[22] AND interrupt Enable for mv_busy
+// bit[21] AND interrupt Enable for b8_mode_busy
+// bit[20] AND interrupt Enable for mb_skip_run_busy
+// bit[19] AND interrupt Enable for cbp_busy
+// bit[18] AND interrupt Enable for Reserved
+// bit[17] AND interrupt Enable for Reserved
+// bit[16] AND interrupt Enable for mb_info_busy
+// bit[15] OR interrupt Enable Reserved
+// bit[14] OR interrupt Enable for mvd
+// bit[13] OR interrupt Enable for b8_mode
+// bit[12] OR interrupt Enable for mb_skip_run
+// bit[11] OR interrupt Enable for cbp_ready
+// bit[10] OR interrupt Enable for c_ipred_mode_ready
+// bit[9] OR interrupt Enable for ipred_mode_ready
+// bit[8] OR interrupt Enable for mb_info_ready
+// bit[7] AND interrupt Enable Reserved
+// bit[6] AND interrupt Enable for mvd
+// bit[5] AND interrupt Enable for b8_mode
+// bit[4] AND interrupt Enable for mb_skip_run
+// bit[3] AND interrupt Enable for cbp_ready
+// bit[2] AND interrupt Enable for c_ipred_mode_ready
+// bit[1] AND interrupt Enable for ipred_mode_ready
+// bit[0] AND interrupt Enable for mb_info_ready
+#define VLC_INT_CONTROL ((0x0030 << 2) + 0xfe067400)
+// Bit[31:16] picture_height
+// Bit[15:0] picture_width
+#define VLC_PIC_SIZE ((0x0031 << 2) + 0xfe067400)
+// [31:16] Reserved
+// [15:3] pic_width_in_mbs_minus1
+// [2:0] picture_type
+#define VLC_PIC_INFO ((0x0032 << 2) + 0xfe067400)
+// Bit[31:16] MB_NR
+// Bit[15:8] MBY
+// Bit[7:0] MBX
+#define VLC_PIC_POSITION ((0x0033 << 2) + 0xfe067400)
+// Bit[31] MV_busy
+// Bit[30:6] Reserved
+// Bit[15] Reserved
+// Bit[14] vlc_input_MV_busy
+// Bit[13] vlc_input_b8_mode_busy
+// Bit[12] vlc_input_mb_skip_run_busy
+// Bit[11] vlc_input_cbp_busy
+// Bit[10] Reserved
+// Bit[9] Reserved
+// Bit[8] vlc_input_mb_info_busy
+// Bit[7] Reserved
+// Bit[6] mvd
+// Bit[5] b8_mode
+// Bit[4] mb_skip_run
+// Bit[3] cbp
+// Bit[2] c_ipred_mode
+// Bit[1] ipred_mode
+// Bit[0] mb_info ( mb_type, mb_x, mb_y)
+#define VLC_INPUT_STATUS ((0x0034 << 2) + 0xfe067400)
+// Bit[31:28] detected_mb_type
+// Bit[27:16] mb_y
+// Bit[15:4] mb_x
+// Bit[3:0] mb_type
+#define VLC_MB_INFO ((0x0035 << 2) + 0xfe067400)
+// commnad 0 -- no pending
+// normal command + 1 is pending command
+//
+// bit 31:28 -- pending command 7
+// bit 27:24 -- pending command 6
+// bit 23:20 -- pending command 5
+// bit 19:16 -- pending command 4
+// bit 15:12 -- pending command 3
+// bit 11:8 -- pending command 2
+// bit 7:4 -- pending command 1
+// bit 3:0 -- pending command 0
+#define VLC_ENC_PEND_CMD ((0x0036 << 2) + 0xfe067400)
+// For I Slice
+// Bit[31:16] Reserved
+// Bit[15:0] IntraType
+#define HENC_TOP_INFO_0 ((0x0037 << 2) + 0xfe067400)
+#define HENC_LEFT_INFO_0 ((0x0038 << 2) + 0xfe067400)
+// For I Slice
+// Bit[31:24] V_nnz
+// Bit[23:16] U_nnz
+// Bit[15:0] Y_nnz
+#define HENC_TOP_INFO_1 ((0x0039 << 2) + 0xfe067400)
+#define HENC_LEFT_INFO_1 ((0x003a << 2) + 0xfe067400)
+// bit[63:0] ipred_mode
+#define VLC_IPRED_MODE_HI ((0x003b << 2) + 0xfe067400)
+#define VLC_IPRED_MODE_LO ((0x003c << 2) + 0xfe067400)
+// bit[15:8] SE delta quant
+// bit[7:0] UE delta quant
+#define VLC_DELTA_QP ((0x003d << 2) + 0xfe067400)
+// bit[31:16] Reserved
+// bit[15:12] Reserved
+// bit[11:8] c_ipred_mode
+// bit[7:0] cbp
+#define VLC_MB_HEADER_INFO ((0x003e << 2) + 0xfe067400)
+// bit[31:16] mb_skip_run
+// bit[15:0] b8_mode
+#define VLC_P_MB_HEADER_INFO ((0x003f << 2) + 0xfe067400)
+// bit[31] write_ptr_update
+// bit[30] read_ptr_update
+// bit[29:20] coeff_buf_level
+// bit[19:10] coeff_buf_write_ptr
+// bit[9:0] coeff_buf_read_ptr
+#define VLC_COEFF_BUF_STATUS ((0x0040 << 2) + 0xfe067400)
+// bit[31:10] Reserved
+// bit[9:0] read_req_addr
+#define VLC_COEFF_RD_REQ ((0x0041 << 2) + 0xfe067400)
+// bit[20] - coeff_buf_read_finished
+// bit[19] - coeff_first
+// bit[18:4] - coeff_level
+// bit[3:0] - coeff_run
+#define VLC_COEFF ((0x0042 << 2) + 0xfe067400)
+// bit[31] - coeff_info_ready
+// bit[30:25] - Reserved
+// bit[24:15] - block_begin_addr
+// bit[14:11] - trailing_one_sign
+// bit[10:6] - total_coeff
+// bit[5:4] - trailing_ones
+// bit[3:0] - total_zeros
+#define VLC_COEFF_INFO ((0x0043 << 2) + 0xfe067400)
+// bit[31] write_ptr_update
+// bit[30] read_ptr_update
+// bit[29:25] Reserved
+// bit[24:20] dc_buf_level -- 0-16
+// bit[19:15] Reserved
+// bit[14:10] dc_buf_write_ptr
+// bit[9:5] Reserved
+// bit[4:0] dc_buf_read_ptr
+#define VLC_DC_BUF_STATUS ((0x0044 << 2) + 0xfe067400)
+// bit[31:10] Reserved
+// bit[9:4] Reserved
+// bit[3:0] read_req_addr
+#define VLC_DC_RD_REQ ((0x0045 << 2) + 0xfe067400)
+// bit[31:17] - Reserved
+// bit[16] - dc_first
+// bit[15:1] - dc_level
+// bit[0] - dc_type 0 - CDC, 1 - LDC
+#define VLC_DC ((0x0046 << 2) + 0xfe067400)
+// bit[31] - dc_info_ready
+// bit[30:25] - Reserved
+// bit[24:20] - Reserved
+// bit[19:15] - dc_idx_begin_addr
+// bit[14:11] - dc_trailing_one_sign
+// bit[10:6] - dc_total_coeff
+// bit[5:4] - dc_trailing_ones
+// bit[3:0] - dc_total_zeros
+#define VLC_DC_INFO ((0x0047 << 2) + 0xfe067400)
+// bit[31:4] - Reserved
+// bit[3:0] - mv_rw_idx (auto increment when read/write VLC_MV)
+#define VLC_MV_INDEX ((0x0048 << 2) + 0xfe067400)
+// bit[31:16] - MVY
+// bit[15:0] - MVX
+#define VLC_MV ((0x0049 << 2) + 0xfe067400)
+// bit[31:16] - MVY
+// bitp15:0] - MVX
+// Write to HENC_TOP_MV_0 will cause previous U->UL, UR->U, and UR write
+// Read will read U MV only
+#define HENC_TOP_MV_0 ((0x004a << 2) + 0xfe067400)
+#define HENC_TOP_MV_1 ((0x004b << 2) + 0xfe067400)
+#define HENC_TOP_MV_2 ((0x004c << 2) + 0xfe067400)
+#define HENC_TOP_MV_3 ((0x004d << 2) + 0xfe067400)
+#define HENC_LEFT_MV_0 ((0x004e << 2) + 0xfe067400)
+#define HENC_LEFT_MV_1 ((0x004f << 2) + 0xfe067400)
+#define HENC_LEFT_MV_2 ((0x0050 << 2) + 0xfe067400)
+#define HENC_LEFT_MV_3 ((0x0051 << 2) + 0xfe067400)
+// Bit[31:1] Reserved
+// Bit[0] top_left_mv_ready
+#define TOP_LEFT_READY ((0x0052 << 2) + 0xfe067400)
+// Bit[31:16] Reserved
+// Bit[15:0] mb_skip_run
+#define MB_SKIP_RUN ((0x0053 << 2) + 0xfe067400)
+// Bit[31:16] Reserved
+// Bit[15] Reserved
+// Bit[14:13] rd_struct // 00 - frame, 10 - top field, 11 - bottom field
+// Bit[12:11] wr_struct // 00 - frame, 10 - top field, 11 - bottom field
+// Bit[10:5] mv_buff_id
+// Bit[4:0] mv_ref
+#define VLC_HCMD_CONFIG ((0x0054 << 2) + 0xfe067400)
+// Bit[9:0] h264_dblk_info
+#define VLC_HCMD_DBLK_INFO ((0x0055 << 2) + 0xfe067400)
+// Bit[3:0] vlc_dbg_idx
+#define VLC_DBG_IDX ((0x0056 << 2) + 0xfe067400)
+// Read Only
+#define VLC_DBG_READ ((0x0057 << 2) + 0xfe067400)
+// [ 29] RW jpeg_comp2_ac_table_sel. Default 0.
+// [ 28] RW jpeg_comp2_dc_table_sel. Default 0.
+// [26:25] RW jpeg_comp2_cnt_max. Default 0.
+// [ 24] RW jpeg_comp2_en. Set 1 if the scan will include component 2 (Cr). Default 0.
+// [ 21] RW jpeg_comp1_ac_table_sel. Default 0.
+// [ 20] RW jpeg_comp1_dc_table_sel. Default 0.
+// [18:17] RW jpeg_comp1_cnt_max. Default 0.
+// [ 16] RW jpeg_comp1_en. Set 1 if the scan will include component 1 (Cb). Default 0.
+// [ 13] RW jpeg_comp0_ac_table_sel. Default 0.
+// [ 12] RW jpeg_comp0_dc_table_sel. Default 0.
+// [10: 9] RW jpeg_comp0_cnt_max. Default 0.
+// [ 8] RW jpeg_comp0_en. Set 1 if the scan will include component 0 (Y). Default 0.
+// [ 1] W jpeg_coeff_init. Write 1 to this bit to initialize JPEG run length encoder.
+// [ 0] RW jpeg_en. 0=Disable JPEG encoder; 1=Enable JPEG encoder. Default 0.
+#define VLC_JPEG_CTRL ((0x0058 << 2) + 0xfe067400)
+// [ 13] RW jpeg_coeff_buf_overfl. Write this bit to 1 to clear overfl.
+// [ 12] RW jpeg_coeff_buf_undrfl. Write this bit to 1 to clear undrfl.
+// [ 11] R jpeg_coeff_buf_full.
+// [ 10] R jpeg_coeff_buf_empty.
+// [ 8: 0] R jpeg_coeff_buf_level.
+#define VLC_JPEG_COEFF_BUF_STAT ((0x0059 << 2) + 0xfe067400)
+// [ 16] RW JPEG HUFFMAN table access mode. 0=Write; 1=Read. Default 1.
+// [ 8: 0] RW JPEG HUFFMAN table addr. Default 0.
+#define VLC_HUFFMAN_ADDR ((0x005a << 2) + 0xfe067400)
+// [19: 0] RW JPEG HUFFMAN table data.
+#define VLC_HUFFMAN_DATA ((0x005b << 2) + 0xfe067400)
+// bit[31:0] enc_mv_bits - including b8_mode and mvd
+#define VLC_ENC_MV_BITS ((0x005c << 2) + 0xfe067400)
+// bit[31:0] enc_coeff_bits - including cbp, token, trailing_sign, coeff_enc, h264_totzeros, h264_run
+#define VLC_ENC_COEFF_BITS ((0x005d << 2) + 0xfe067400)
+#define VLC_RESERVED_5E ((0x005e << 2) + 0xfe067400)
+#define VLC_RESERVED_5F ((0x005f << 2) + 0xfe067400)
+// ----------------------------------------------------------
+// CABAC
+// ----------------------------------------------------------
+// [15] h264_biari_init
+// [14] h264_cabac_init
+// [13:12] reserved
+// [11:10] picture_ty
+// [9:8] cabac_init_idc // should be 0 for I_SLICE
+// [7] reserved
+// [6] cabac_en
+// [5:0] slice_quant
+#define VLC_SLICE_QP ((0x0060 << 2) + 0xfe067400)
+// For save mvd[12:0] {mvd_y[6:0], mvd_x[5:0]}
+#define HENC_TOP_INFO_2 ((0x0061 << 2) + 0xfe067400)
+#define HENC_LEFT_INFO_2 ((0x0062 << 2) + 0xfe067400)
+#define HENC_TOP_INFO_3 ((0x0063 << 2) + 0xfe067400)
+#define HENC_LEFT_INFO_3 ((0x0064 << 2) + 0xfe067400)
+//
+// Closing file: vlc_regs.h
+//
+//------------------------------------------------------------------------------
+// -----------------------------------------------
+// `define DOS_HCODEC_IQIDCT_CBUS_BASE 8'h0e
+// -----------------------------------------------
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+// QDCT module level register offset
+//------------------------------------------------------------------------------
+// `define DOS_HCODEC_QDCT_CBUS_BASE 8'h0f
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe067c00
+// -----------------------------------------------
+//
+// Reading file: qdct_regs.h
+//
+//========================================================================
+// QDCT module level register offset
+//========================================================================
+// -----------------------------------------------
+// `define DOS_HCODEC_QDCT_CBUS_BASE 8'h0f
+// -----------------------------------------------
+// bit[31:28] - mb_info_state
+#define QDCT_STATUS_CTRL ((0x0000 << 2) + 0xfe067c00)
+// bit[18] - enable_free_clk_sad_top
+// bit[17] - enable_free_clk_ie_top
+// bit[16] - enable_free_clk_ie_sub
+// bit[15] - enable_free_clk_mc_out
+// bit[14] - enable_free_clk_i_pred_top
+// bit[13] - enable_free_clk_idct_top
+// bit[12] - enable_free_clk_iq_top
+// bit[11] - enable_free_clk_q_top
+// bit[10] - enable_free_clk_dc_buff_8
+// bit[9] - enable_free_clk_dct_top
+// bit[8] - enable_free_clk_mb_info
+// bit[7] - enable_free_clk_mb_buff
+// bit[6] - enable_free_clk_reg
+// bit[5] - ignore_1_include_2nd_half_c
+// bit[4] - ignore_1_include_2nd_half
+// bit[3] - ignore_t_p8x8
+// bit[2] - not_ignore_dc
+// bit[1] - ignore_small_lac_intra
+// bit[0] - disable_fast_zero_block
+#define QDCT_CONFIG ((0x0001 << 2) + 0xfe067c00)
+// bit[31] - ignore_lac_coeff_en
+// bit[30:26] - ignore_lac_coeff_else
+// bit[25:21] - ignore_lac_coeff_2
+// bit[20:16] - ignore_lac_coeff_1
+// bit[15] - ignore_cac_coeff_en
+// bit[14:10] - ignore_cac_coeff_else
+// bit[9:5] - ignore_cac_coeff_2
+// bit[4:0] - ignore_cac_coeff_1
+#define IGNORE_CONFIG ((0x0002 << 2) + 0xfe067c00)
+// bit[31] - ignore_t_lac_coeff_en
+// bit[30:26] - ignore_t_lac_coeff_else
+// bit[25:21] - ignore_t_lac_coeff_2
+// bit[20:16] - ignore_t_lac_coeff_1
+// bit[15] - ignore_cdc_coeff_en
+// bit[14] - ignore_t_lac_coeff_else_le_3
+// bit[13] - ignore_t_lac_coeff_else_le_4
+// bit[12] - ignore_cdc_only_when_empty_cac_inter
+// bit[11] - ignore_cdc_only_when_one_empty_inter
+// bit[10:9] - ignore_cdc_range_max_inter // 0-0, 1-1, 2,-2, 3-3
+// bit[8:7] - ignore_cdc_abs_max_inter // 0-1, 1-2, 2,-3, 3-4
+// bit[6] - reserved
+// bit[5] - ignore_cdc_only_when_empty_cac_intra
+// bit[4] - ignore_cdc_only_when_one_empty_intra
+// bit[3:2] - ignore_cdc_range_max_intra // 0-0, 1-1, 2,-2, 3-3
+// bit[1:0] - ignore_cdc_abs_max_intra // 0-1, 1-2, 2,-3, 3-4
+#define IGNORE_CONFIG_2 ((0x0003 << 2) + 0xfe067c00)
+// --------------------------------------------
+// MB DATA DDR Interface
+// --------------------------------------------
+#define QDCT_MB_START_PTR ((0x0010 << 2) + 0xfe067c00)
+#define QDCT_MB_END_PTR ((0x0011 << 2) + 0xfe067c00)
+#define QDCT_MB_WR_PTR ((0x0012 << 2) + 0xfe067c00)
+#define QDCT_MB_RD_PTR ((0x0013 << 2) + 0xfe067c00)
+#define QDCT_MB_LEVEL ((0x0014 << 2) + 0xfe067c00)
+// bit [31] disable_mbxy_ie_save
+// bit [30] no_wait_after_q_cdc
+// bit [29] ie_start_int_enable
+// bit [28] ignore_t_p8x8
+// bit [27] zero_mc_out_null_non_skipped_mb
+// bit [26] no_mc_out_null_non_skipped_mb
+// bit [25] mc_out_even_skipped_mb
+// bit [24] mc_out_wait_cbp_ready
+// bit [23] mc_out_wait_mb_type_ready
+// bit [22] i_pred_int_enable
+// bit [21] intra_sat8_enable
+// bit [20] ie_sub_enable
+// bit [19] i_pred_enable
+// bit [18] iq_enable
+// bit [17] idct_enable
+// bit [16] no_zero_coeff_mb
+// bit [15] add_zero_coeff_block
+// bit [14] mb_pause_enable
+// bit [13] q_enable
+// bit [12] dct_enable
+// bit [11] ignore_magic_word
+// bit [10] mb_info_en
+// bit [9] mb_info_soft_reset
+// bit [8] mb_always_ready Set to 1 to ignore mb_level blocking DDR read
+// bit [7] mb_ready_for_transfer (Read Only)
+// bit [6] data_ready_for_transfer (Read Only)
+// bits [5:3] mb_endian Set MB Endian inside DDR memory
+// bit [2] mb_read_busy Read Only - indicate DDR read busy
+// bit [1] mb_read_en Set to 1 to enable reading data from DDR memory
+// bit [0] mb_soft_reset Soft reset
+#define QDCT_MB_CONTROL ((0x0015 << 2) + 0xfe067c00)
+// bit 31 transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request // default : 0
+// bit 30 A_urgent // default : 0
+// bit 29:24 A_brst_num // default : 0x3f
+// bit 23 reserved
+// bit 22 read_till_zero
+// bit 21:16 A_id // default : 0x21
+// bit 15:0 mb_level_hold // default : 0
+#define QDCT_MB_MEM_CTL ((0x0016 << 2) + 0xfe067c00)
+// bit [31:24] reserved
+// bit [23:16] vb_buff_level -- Read only
+// bit [15:8] vb_buff_wr_point -- RW
+// bit [7:0] vb_buff_rd_point -- RW
+#define QDCT_MB_BUFF ((0x0017 << 2) + 0xfe067c00)
+// bit [31:0] mb infor data begin magic word - default : 0xa55aaa55
+#define QDCT_MB_MAGIC_WORD ((0x0018 << 2) + 0xfe067c00)
+// Read Only Register
+// bit[19] dct_ready_1
+// bit[18] dct_ready_0
+// bit[17] dct_rd_idx
+// bit[16] dct_wr_idx
+// bit[15] dct_srdy
+// bit[14] dct_rrdy
+// bit[13] Reserved
+// bit[12:8] dct_block_number
+// bit[7:4] dct_rw_addr
+// bit[3:0] dct_status
+#define QDCT_DCT_STATUS ((0x0019 << 2) + 0xfe067c00)
+// bit[24:23] vlc_quant_count
+// bit[22:16] vlc_delta_quant_data
+// bit[15:10] vlc_quant_data
+// bit[9:4] vlc_prev_quant_data
+// bit[3:0] q_status
+#define QDCT_Q_STATUS ((0x001a << 2) + 0xfe067c00)
+// bit[31:3] Reserved
+// bit[2:0] picture_type
+#define QDCT_PIC_INFO ((0x001b << 2) + 0xfe067c00)
+// bit[31:28] Reserved
+// bit[27:22] I_pic_quant_c
+// bit[21:16] I_pic_quant
+// bit[15] reserved
+// bit[14:12] quant_rem_c
+// bit[11:8] quant_per_c
+// bit[7] reserved
+// bit[6:4] quant_rem
+// bit[3:0] quant_per
+#define QDCT_Q_QUANT_I ((0x001c << 2) + 0xfe067c00)
+// bit[31:28] Reserved
+// bit[27:22] P_pic_quant_c
+// bit[21:16] P_pic_quant
+// bit[15] reserved
+// bit[14:12] quant_rem_c
+// bit[11:8] quant_per_c
+// bit[7] reserved
+// bit[6:4] quant_rem
+// bit[3:0] quant_per
+#define QDCT_Q_QUANT_P ((0x001d << 2) + 0xfe067c00)
+// bit[31] mb_info_pause
+// bit[30:16] pause_mby
+// bit[15:0] pause_mbx
+#define QDCT_MB_PAUSE_CTL ((0x001e << 2) + 0xfe067c00)
+// bit[31] top_control_ready_i_pred
+// bit[30:28]top_dma_status
+// bit[27] top_control_ready_ie
+// bit[26:24]Reserved
+// bit[23] ul_mb
+// bit[22] right_mb
+// bit[21] top_mb
+// bit[20] left_mb
+// bit[19:8] mb_x
+// bit[7:6] i_pred_ref_idx_L
+// bit[5:4] i_pred_ref_idx_UL
+// bit[3:2] i_pred_ref_idx_U
+// bit[1:0] i_pred_ref_idx_UR
+#define QDCT_TOP_CONTROL ((0x001f << 2) + 0xfe067c00)
+// bit[31:0] top_base_addr - DDR Memory start address for save top Pixel
+#define QDCT_TOP_BASE_MEM ((0x0020 << 2) + 0xfe067c00)
+// bit 15:13 Reserved
+// bit 12 A_urgent // default : 0
+// bit 11:6 A_brst_num // default : 0x3f
+// bit 5:0 A_id // default : 0x22
+#define QDCT_TOP_MEM_CTL ((0x0021 << 2) + 0xfe067c00)
+// bit [11:0] top_wrrsp_count
+#define QDCT_TOP_WRRSP ((0x0022 << 2) + 0xfe067c00)
+// Bit[3:0] qdct_dbg_idx
+#define QDCT_DBG_IDX ((0x0023 << 2) + 0xfe067c00)
+// Read Only
+#define QDCT_DBG_READ ((0x0024 << 2) + 0xfe067c00)
+// [19:18] RW jdct_inflow_ctrl. JPEG DCT input flow control. Default 0.
+// 0=No halt;
+// 1=DCT halts request at end of each 8x8 block;
+// 2=DCT halts request at end of each MCU.
+// [17:16] RW jpeg_coeff_last_sel. Default 0.
+// Select at which point to finish processing, give update to AmRISC so it can control the next step.
+// 0=Mark last coeff at the end of an 8x8 block;
+// 1=Mark at the end of an MCU;
+// 2=Mark at the end of a scan.
+// [ 15] RW jpeg_quant_sel_comp2. 0=Comp2 select Quantization table 0; 1=Select table 1. Default 0.
+// [ 14] RW jpeg_v_factor_comp2. Component 2's vertical sampling factor. Default 0.
+// [ 13] RW jpeg_h_factor_comp2. Component 2's horizontal sampling factor. Default 0.
+// [ 12] RW jpeg_comp2_en. Set 1 if the scan will include component 2 (Cr). Default 0.
+// [ 11] RW jpeg_quant_sel_comp1. 0=Comp1 select Quantization table 0; 1=Select table 1. Default 0.
+// [ 10] RW jpeg_v_factor_comp1. Component 1's vertical sampling factor. Default 0.
+// [ 9] RW jpeg_h_factor_comp1. Component 1's horizontal sampling factor. Default 0.
+// [ 8] RW jpeg_comp1_en. Set 1 if the scan will include component 1 (Cb). Default 0.
+// [ 7] RW jpeg_quant_sel_comp0. 0=Comp0 select Quantization table 0; 1=Select table 1. Default 0.
+// [ 6] RW jpeg_v_factor_comp0. Component 0's vertical sampling factor. Default 0.
+// [ 5] RW jpeg_h_factor_comp0. Component 0's horizontal sampling factor. Default 0.
+// [ 4] RW jpeg_comp0_en. Set 1 if the scan will include component 0 (Y). Default 0.
+// [ 3: 1] RW jdct_intr_sel. JPEG DCT interrupt select. Default 0.
+// 0=Disable intr;
+// 1=Intr at end of each 8x8 block of DCT input;
+// 2=Intr at end of each MCU of DCT input;
+// 3=Intr at end of a scan of DCT input;
+// 4=Intr at end of each 8x8 block of DCT output;
+// 5=Intr at end of each MCU of DCT output;
+// 6=Intr at end of a scan of DCT output.
+// [ 0] RW jpeg_en. 0=Disable JPEG QDCT; 1=Enable JPEG QDCT. Default 0.
+#define QDCT_JPEG_CTRL ((0x0025 << 2) + 0xfe067c00)
+// [29:16] RW jpeg_x_end. Picture X end. Default 0.
+// [13: 0] RW jpeg_x_start. Picture X start. Default 0.
+#define QDCT_JPEG_X_START_END ((0x0026 << 2) + 0xfe067c00)
+// [29:16] RW jpeg_y_end. Picture Y end. Default 0.
+// [13: 0] RW jpeg_y_start. Picture Y start. Default 0.
+#define QDCT_JPEG_Y_START_END ((0x0027 << 2) + 0xfe067c00)
+// [ 8] RW JPEG QUANT table access mode. 0=Write; 1=Read. Default 1.
+// [ 5: 0] RW JPEG QUANT table addr. Default 0.
+#define QDCT_JPEG_QUANT_ADDR ((0x0028 << 2) + 0xfe067c00)
+// [31: 0] RW JPEG QUANT table data.
+#define QDCT_JPEG_QUANT_DATA ((0x0029 << 2) + 0xfe067c00)
+// [ 1] W resume_jdct.
+// Write 1 to this bit will resume JPEG input engine when previously
+// it is halted by QDCT_JPEG_CTRL.jdct_inflow_ctrl.
+// [ 0] W jpeg_sof.
+// Write 1 to this bit will start JPEG input engine.
+#define QDCT_JPEG_SOF_RESUME ((0x002a << 2) + 0xfe067c00)
+// [31:30] R dct_st. jdct_ctrl state. 0=IDLE; 1=WAIT; 2=DCT_REQ.
+// [29:28] R mfdin_comp. Current component at pixel request to MFDIN.
+// [27:14] R mfdin_y. Current Y at pixel request to MFDIN.
+// [13: 0] R mfdin_x. Current X at pixel request to MFDIN.
+#define QDCT_JPEG_DCT_STATUS0 ((0x002b << 2) + 0xfe067c00)
+// [15:12] R JPEG Quant read MEM select.
+// [11: 8] R JPEG DCT2 write MEM select.
+// [ 7: 4] R JPEG DCT2 read MEM select.
+// [ 3: 0] R JPEG DCT1 write MEM select.
+#define QDCT_JPEG_DCT_STATUS1 ((0x002c << 2) + 0xfe067c00)
+// [28:16] RW jdct_coeff1. Default 13'h1D90; // 7568 = 4096 * sqrt(2) * (cos(Pi/8) + sin(Pi/8)) // 7569
+// [12: 0] RW jdct_coeff0. Default 13'h16A1; // 5793 = 4096 * sqrt(2)
+#define QDCT_JPEG_DCT_COEFF01 ((0x002d << 2) + 0xfe067c00)
+// [28:16] RW jdct_coeff3. Default 13'h0C3F; // 3135 = 4096 * sqrt(2) * (cos(Pi/8) - sin(Pi/8))
+// [12: 0] RW jdct_coeff2. Default 13'h08A9; // 2217 = 4096 * sqrt(2) * sin(Pi/8) // 2215
+#define QDCT_JPEG_DCT_COEFF23 ((0x002e << 2) + 0xfe067c00)
+// [28:16] RW jdct_coeff5. Default 13'h046A; // 1130 = 4096 * (cos(3Pi/16) - sin(3Pi/16))
+// [12: 0] RW jdct_coeff4. Default 13'h1631; // 5681 = 4096 * (cos(3Pi/16) + sin(3Pi/16)) // 5682
+#define QDCT_JPEG_DCT_COEFF45 ((0x002f << 2) + 0xfe067c00)
+// [28:16] RW jdct_coeff7. Default 13'h0C92; // 3218 = 4096 * (cos(Pi/16) - sin(Pi/16))
+// [12: 0] RW jdct_coeff6. Default 13'h12D0; // 4816 = 4096 * (cos(Pi/16) + sin(Pi/16))
+#define QDCT_JPEG_DCT_COEFF67 ((0x0030 << 2) + 0xfe067c00)
+// [28:16] RW jdct_coeff9. Default 13'h0FB1; // 4017 = 4096 * cos(Pi/16)
+// [12: 0] RW jdct_coeff8. Default 13'h0D4E; // 3406 = 4096 * cos(3Pi/16)
+#define QDCT_JPEG_DCT_COEFF89 ((0x0031 << 2) + 0xfe067c00)
+#define QDCT_I_PRED_REF_WR_IDX ((0x0032 << 2) + 0xfe067c00)
+#define QDCT_I_PRED_REF_WR_DATA ((0x0033 << 2) + 0xfe067c00)
+// bit[29] mb_info_latch_no_I16_pred_mode
+// bit[28] ie_dma_mbxy_use_i_pred
+// bit[27] ie_dma_read_write_use_ip_idx
+// bit[26] ie_start_use_top_dma_count
+// bit[25] i_pred_top_dma_rd_mbbot
+// bit[24] i_pred_top_dma_wr_disable
+// bit[23] i_pred_mix
+// bit[22] me_ab_rd_when_intra_in_p
+// bit[21] force_mb_skip_run_when_intra
+// bit[20] mc_out_mixed_type
+// bit[19] ie_start_when_quant_not_full
+// bit[18] mb_info_state_mix
+// bit[17] mb_type_use_mix_result
+// bit[16] me_cb_ie_read_enable
+// bit[15] ie_cur_data_from_me
+// bit[14] rem_per_use_table
+// bit[13] q_latch_int_enable
+// bit[12] q_use_table
+// bit[11] q_start_wait
+// bit[10] LUMA_16_LEFT_use_cur
+// bit[9] DC_16_LEFT_SUM_use_cur
+// bit[8] c_ref_ie_sel_cur
+// bit[7] c_ipred_perfect_mode
+// bit[6] ref_ie_ul_sel 0-old, 1-use next_set
+// bit[5] mb_type_use_ie_result
+// bit[4] detect_I16_from_I4
+// bit[3] ie_not_wait_ref_busy
+// bit[2] ie_I16_enable
+// bit[1:0] ie_done_sel (0, 1, 2, -1)
+#define QDCT_ADV_CONFIG ((0x0034 << 2) + 0xfe067c00)
+// bit [31:16] I16x16_weight
+// bit [15:0] I4x4_weight
+#define IE_WEIGHT ((0x0035 << 2) + 0xfe067c00)
+// bit [31] reserved
+// bit [30] q_I16MB
+// bit [29] reserved
+// bit [28] reserved
+// bit [27:23] quant_table_addr I4MB:[0,7], I16MB:[8:15], INTER:[16:23], Reserved:[24:31]
+// bit [22] quant_table_addr_update(when notupdate_rem_per) (read is arb_result : q_intra)
+// bit [21:19] quant_rem_c
+// bit [18:16] quant_rem_y
+// bit [15:12] quant_per_c
+// bit [11:8] quant_per_y
+// bit [7:2] quant
+// bit [1] update_rem_per
+// bit [0] clear_wait_status
+#define Q_QUANT_CONTROL ((0x0036 << 2) + 0xfe067c00)
+#define MBBOT_EVEN_ADDR ((0x0037 << 2) + 0xfe067c00)
+#define MBBOT_ODD_ADDR ((0x0038 << 2) + 0xfe067c00)
+// bit [29:24] quant_table_data_3
+// bit [21:16] quant_table_data_2
+// bit [13:8] quant_table_data_1
+// bit [5:0] quant_table_data_0
+#define QUANT_TABLE_DATA ((0x0039 << 2) + 0xfe067c00)
+// bit [31:16] ie_sad_offset_I16
+// bit [15:0] ie_sad_offset_I4
+#define SAD_CONTROL_0 ((0x003a << 2) + 0xfe067c00)
+// bit [31] sad_soft_reset
+// bit [30:27] reserved
+// bit [26:24] ie_sad_shift_I16
+// bit [22:20] ie_sad_shift_I4
+// bit [18:16] me_sad_shift_INTER
+// bit [15:0] me_sad_offset_INTER
+#define SAD_CONTROL_1 ((0x003b << 2) + 0xfe067c00)
+// bit [31] vlc_quant_rd_ptr
+// bit [30] vlc_quant_rd_ptr_update
+// bit [29] vlc_quant_wr_ptr
+// bit [28] vlc_quant_wr_ptr_update
+// bit [27:26] reserved
+// bit [25:19] vlc_delta_quant_1
+// bit [18:13] vlc_quant_1
+// bit [12:6] vlc_delta_quant_0
+// bit [5:0] vlc_quant_0
+#define QDCT_VLC_QUANT_CTL_0 ((0x003c << 2) + 0xfe067c00)
+// bit [31:30] me_sad_rd_idx
+// bit [29] me_sad_rd_idx_update
+// bit [28:27] me_sad_wr_idx
+// bit [26] me_sad_wr_idx_update
+// bit [25:24] ie_sad_rd_idx
+// bit [23] ie_sad_rd_idx_update
+// bit [22:21] ie_sad_wr_idx
+// bit [20] ie_sad_wr_idx_update
+// bit [19:12] Reserved
+// bit [11:6] vlc_max_delta_q_neg
+// bit [5:0] vlc_max_delta_q_pos
+#define QDCT_VLC_QUANT_CTL_1 ((0x003d << 2) + 0xfe067c00)
+// bit[4] jdct_int
+// bit[3] quant_latch
+// bit[2] me_done
+// bit[1] ie_start
+// bit[0] i_pred_start
+#define QDCT_INT_STATUS ((0x003e << 2) + 0xfe067c00)
+// bit[3] mix_i_pred_wait_left_en
+// bit[2:0] mc_pending_mb_count
+#define QDCT_MIX_I_PRED_STATUS ((0x003f << 2) + 0xfe067c00)
+// IE/ME share same cbus_base as QDCT
+//
+// bit[31] active_ur_block
+// bit[30] active_ul_block
+// bit[21] disable_HENC_V_PRED_16
+// bit[20] disable_HENC_H_PRED_16
+// bit[19] disable_HENC_DC_PRED_16
+// bit[18] disable_HENC_HENC_HOR_UP_PRED
+// bit[17] disable_HENC_VERT_LEFT_PRED
+// bit[16] disable_HENC_HENC_HOR_DOWN_PRED
+// bit[15] disable_HENC_VERT_RIGHT_PRED
+// bit[14] disable_HENC_DIAG_DOWN_RIGHT_PRED
+// bit[13] disable_HENC_DIAG_DOWN_LEFT_PRED
+// bit[12] disable_HENC_DC_PRED
+// bit[11] disable_HENC_HOR_PRED
+// bit[10] disable_HENC_VERT_PRED
+// bit[9] ie_c_wait_ie_pause
+// bit[8:4] max_ie_result_buff_count
+// bit[3] ie_wait_for_ie_result // use for (max_ie_result_buff_count == 0) to wait every block
+// bit[2] reserved
+// bit[1] ie_enable
+// bit[0] ie_soft_reset
+#define IE_CONTROL ((0x0040 << 2) + 0xfe067c00)
+// bit[31:12] Reserved
+// bit[11:0] mb_y
+#define IE_MB_POSITION ((0x0041 << 2) + 0xfe067c00)
+// bit[31:16] me_skip_run
+// bit[15:8] reserved
+// bit [7:4] me_b8_mode
+// bit [3:0] ie_me_mb_type
+#define IE_ME_MB_INFO ((0x0042 << 2) + 0xfe067c00)
+// bit[3] ie_result_buff_enable
+// bit[2] ie_result_buff_soft_reset
+// bit[1] sad_enable
+// bit[0] ie_sad_soft_reset
+#define SAD_CONTROL ((0x0043 << 2) + 0xfe067c00)
+// bit[31:16] - ie_result_buff_count - read only
+// bit[14:12] -current_ie_result (pred_mode) - read only
+// bit[11] top_control_data_buff_wr_ptr - rd/wr
+// bit[10] top_control_data_buff_rd_ptr - rd/wr
+// bit[9:5] ie_result_buff_wr_ptr - rd/wr
+// bit[4:0] ie_result_buff_rd_ptr - rd/wr
+#define IE_RESULT_BUFFER ((0x0044 << 2) + 0xfe067c00)
+// bit[63:0] ie_i4_pred_mode
+#define IE_I4_PRED_MODE_HI ((0x0045 << 2) + 0xfe067c00)
+#define IE_I4_PRED_MODE_LO ((0x0046 << 2) + 0xfe067c00)
+// bit [31:9] reserved
+// bit [8:4] i_pred_block_number
+// bit [3:0] ie_c_pred_mode
+#define IE_C_PRED_MODE ((0x0047 << 2) + 0xfe067c00)
+// 31:16 - Left, 0-select ie_pixel, 1-select mc_data_out
+// 15:0 - Top, 0-select ie_pixel, 1-select mc_data_out
+#define IE_CUR_REF_SEL ((0x0048 << 2) + 0xfe067c00)
+// bit[31] enable_f_skip_1_step_3
+// bit[30] enable_f_skip_1_step_2
+// bit[29] enable_f_skip_1_step_1
+// bit[28] step_3_enable
+// bit[27] step_2_sub_pixel
+// bit[26] always_f_skip_step_3
+// bit[25] always_f_skip_step_2
+// bit[24] always_f_skip_step_1
+// bit[23] half_pixel_only
+// bit[22:13] reserved
+// bit[12] adv_mv_enable
+// bit[11] sad_short_valid
+// bit[10:9] mv_flexable_ctl 00:0x40, 01:0x80, 10:0xc0, 11 : 0x100
+// bit[8] no_md_ab_rd
+// bit[7] use_dct_state
+// bit[6] enable_free_clk_me_ctl
+// bit[5] enable_free_clk_me_ab
+// bit[4] enable_free_clk_me_cb
+// bit[3] reserved
+// bit[2] me_done_int_enable
+// bit[1] me_enable
+// bit[0] me_soft_reset
+#define ME_CONTROL ((0x0049 << 2) + 0xfe067c00)
+// bit[31:28] Reserved
+// bit[27:16] me_start_mby
+// bit[15:12] Reserved
+// bit[11:0] me_start_mbx
+#define ME_START_POSITION ((0x004a << 2) + 0xfe067c00)
+// bit [31:28] me_status - Read only
+// bit [27:24] me_cb_status // current buffer
+// bit [23:20] me_ab_status // anc buffer
+// bit [19] Reserved
+// bit [18:16] me_ab_wr_ptr // read only
+// bit [15:4] me_last_mbx
+// bit [3:1] me_ab_rd_ptr // read only
+// bit [0] me_action
+#define ME_STATUS ((0x004b << 2) + 0xfe067c00)
+// all Read-only
+// bit [31:28] Reserved
+// bit [27:16] me_ab_mbx
+// bit [15:14] me_cb_wr_ptr
+// bit [13:12] me_cb_rd_ptr
+// bit [11:0] me_cb_mbx
+#define ME_DEBUG ((0x004c << 2) + 0xfe067c00)
+// bit[29:24] step_3_skip_line
+// bit[23:18] step_2_skip_line
+// bit[17:12] step_1_skip_line
+// bit[11:6] step_0_skip_line
+// bit[5:0] read_skip_line
+#define ME_SKIP_LINE ((0x004d << 2) + 0xfe067c00)
+// bit 15:13 Reserved
+// bit 12 A_urgent // default : 0
+// bit 11:6 A_brst_num // default : 0x3f
+// bit 5:0 A_id // default : 0x23
+#define ME_AB_MEM_CTL ((0x004e << 2) + 0xfe067c00)
+// bit[31:24] anc_pic_canvas
+// bit[23:12] max_me_mby_num
+// bit[11:0] max_me_mbx_num
+#define ME_PIC_INFO ((0x004f << 2) + 0xfe067c00)
+// bit [23:12] me_sad_enough_1
+// bit [11:0] me_sad_enough_0
+#define ME_SAD_ENOUGH_01 ((0x0050 << 2) + 0xfe067c00)
+// bit [25:12] adv_mv_8x8_enough
+// bit [11:0] me_sad_enough_2
+#define ME_SAD_ENOUGH_23 ((0x0051 << 2) + 0xfe067c00)
+// bit [21:10] me_step0_big_sad
+// bit [9:5] me_step0_close_mv_y
+// bit [4:0] me_step0_close_mv_x
+#define ME_STEP0_CLOSE_MV ((0x0052 << 2) + 0xfe067c00)
+// bit[31:24] force_skip_sad_3
+// bit[23:16] force_skip_sad_2
+// bit[15:08] force_skip_sad_1
+// bit[07:00] force_skip_sad_0
+#define ME_F_SKIP_SAD ((0x0053 << 2) + 0xfe067c00)
+// bit[31:24] force_skip_weight_3
+// bit[23:16] force_skip_weight_2
+// bit[15:08] force_skip_weight_1
+// bit[07:00] force_skip_weight_0
+#define ME_F_SKIP_WEIGHT ((0x0054 << 2) + 0xfe067c00)
+// Merge when (
+// (flex & me_merge_flex_en) |
+// (big_sad & me_merge_sad_en)|
+// ((~me_merge_flex_en)&(~me_merge_sad_en))
+// ) &
+// ( small_mv_diff |(~me_merge_small_mv_en))
+// & (me_merge_flex_en | me_merge_sad_en | me_merge_small_mv_en)
+// bit[31] me_merge_mv_en_16
+// bit[30] me_merge_small_mv_en_16
+// bit[29] me_merge_flex_en_16
+// bit[28] me_merge_sad_en_16
+// bit[27] me_merge_mv_en_8
+// bit[26] me_merge_small_mv_en_8
+// bit[25] me_merge_flex_en_8
+// bit[24] me_merge_sad_en_8
+// bit[23:18] me_merge_mv_diff_16
+// bit[17:12] me_merge_mv_diff_8
+// bit[11:0] me_merge_min_sad
+#define ME_MV_MERGE_CTL ((0x0055 << 2) + 0xfe067c00)
+// bit[31:24] mv_step_weight_1
+// bit[23:16] mv_pre_weight_1
+// bit [15:0] mv_step_weight_0
+// bit[7:0] mv_pre_weight_0
+#define ME_MV_WEIGHT_01 ((0x0056 << 2) + 0xfe067c00)
+// bit[31:24] mv_step_weight_3 (mv_step_weight_1_2nd)
+// bit[23:16] mv_pre_weight_3 (mv_pre_weight_1_2nd)
+// bit[15:8] mv_step_weight_2
+// bit[7:0] mv_pre_weight_2
+#define ME_MV_WEIGHT_23 ((0x0057 << 2) + 0xfe067c00)
+// bit[31:24] me_sad_range_inc_3
+// bit[23:16] me_sad_range_inc_2
+// bit[15:8] me_sad_range_inc_1
+// bit[7:0] me_sad_range_inc_0
+#define ME_SAD_RANGE_INC ((0x0058 << 2) + 0xfe067c00)
+// bit[31:19] reserved
+// bit[18] sub_relative_any_1_en
+// bit[17] sub_relative_any_2_en
+// bit[16] sub_relative_any_3_en
+// bit[15] sub_relative_any_4_en
+// bit[14] sub_relative_any_h_en
+// bit[13] sub_make_non_flex_fix
+// bit[12] sub_make_big_non_flex_fix
+// bit[11:8] sub_normal_mv_diff_16
+// bit[7:4] sub_normal_mv_diff_8
+// bit[3:2] Reserved
+// bit[1] sub_merge_enable_16
+// bit[0] sub_merge_enable_8
+#define ME_SUB_MERGE_CTL ((0x0059 << 2) + 0xfe067c00)
+// bit[31:28] sub_ref_mv_diff_near
+// bit[27:24] sub_ref_mv_diff_near_flex
+// bit[23:20] sub_ref_mv_diff
+// bit[19:16] sub_ref_mv_diff_flex
+// bit[15:8] sub_ref_mv_near_weight
+// bit[7:0] sub_ref_mv_weight
+#define ME_SUB_REF_MV_CTL ((0x005a << 2) + 0xfe067c00)
+// bit[31:24] sub_weight_max_sad
+// bit[23:16] sub_any_range_sad
+// bit[15:8] sub_any_min_sad
+// bit[7:0] sub_any_max_sad
+#define ME_SUB_ANY_WEIGHT_SAD ((0x005b << 2) + 0xfe067c00)
+// bit[31:24] sub_fix_sad
+// bit[23:16] sub_fix_diff_sad
+// bit[15:8] sub_sad_flex_adj
+// bit[7:0] sub_big_non_flex_fix_sad
+#define ME_SUB_FIX_SAD ((0x005c << 2) + 0xfe067c00)
+// bit[31:24] sub_fix_min_sad
+// bit[23:16] sub_fix_min_diff_sad
+// bit[15:8] sub_fix_min_sad_2
+// bit[7:0] sub_fix_min_diff_sad_2
+#define ME_SUB_FIX_MIN_SAD ((0x005d << 2) + 0xfe067c00)
+// bit[31:24] sub_snap_to_ref_max_sad
+// bit[23] sub_snap_to_ref_non_flex
+// bit[22:16] sub_snap_to_ref_mv_diff
+// bit[15:4] sub_glitch_mv_sad
+// bit[3:0] sub_glitch_mv_diff
+#define ME_SUB_SNAP_GLITCH ((0x005e << 2) + 0xfe067c00)
+// bit[31:20] sad_act_limit
+// bit[19:8] s_a_any_sad
+// bit[7] Reserved
+// bit[6:5] sub_merge_method
+// bit[4] use_sub_act_result
+// bit[3] s_a_rnd
+// bit[2] Reserved
+// bit[1] sub_act_en_16
+// bit[0] sub_act_en
+#define ME_SUB_ACT_CTL ((0x005f << 2) + 0xfe067c00)
+// bit[31:16] reserved
+// bit[15:0] me_weight
+#define ME_WEIGHT ((0x0060 << 2) + 0xfe067c00)
+// bit[31] ready_update
+// bit[30] data_update
+// bit[29:28] reserved
+// bit[27:22] me_quant_0
+// bit[21] ie_sad_ready_0
+// bit[20:18] Reserved
+// bit[17:16] me_sad_mv_type_0
+// bit[15:0] me_sad_0
+#define ME_SAD_0 ((0x0061 << 2) + 0xfe067c00)
+// bit[31] ready_update
+// bit[30] data_update
+// bit[29:28] reserved
+// bit[27:22] me_quant_1
+// bit[21] me_sad_ready_1
+// bit[20:18] Reserved
+// bit[17:16] me_sad_mv_type_1
+// bit[15:0] me_sad_1
+#define ME_SAD_1 ((0x0062 << 2) + 0xfe067c00)
+// bit[31] ready_update
+// bit[30] data_update
+// bit[29:28] reserved
+// bit[27:22] me_quant_2
+// bit[21] me_sad_ready_2
+// bit[20:18] Reserved
+// bit[17:16] me_sad_mv_type_2
+// bit[15:0] me_sad_2
+#define ME_SAD_2 ((0x0063 << 2) + 0xfe067c00)
+// bit[31] ready_update
+// bit[30] data_update
+// bit[29:28] reserved
+// bit[27:22] me_quant_3
+// bit[21] me_sad_ready_3
+// bit[20:18] Reserved
+// bit[17:16] me_sad_mv_type_3
+// bit[15:0] me_sad_3
+#define ME_SAD_3 ((0x0064 << 2) + 0xfe067c00)
+// bit[31] ready_update
+// bit[30] data_update
+// bit[29:28] reserved
+// bit[27:22] ie_quant_0
+// bit[21] ie_sad_ready_0
+// bit[20] I4/I16 (0-I4MB, 1-I16MB)
+// bit[19:0] ie_sad_0
+#define IE_SAD_0 ((0x0065 << 2) + 0xfe067c00)
+// bit[31] ready_update
+// bit[30] data_update
+// bit[29:28] reserved
+// bit[27:22] ie_quant_1
+// bit[21] ie_sad_ready_1
+// bit[20] I4/I16 (0-I4MB, 1-I16MB)
+// bit[19:0] ie_sad_1
+#define IE_SAD_1 ((0x0066 << 2) + 0xfe067c00)
+// bit[31] ready_update
+// bit[30] data_update
+// bit[29:28] reserved
+// bit[27:22] ie_quant_2
+// bit[21] ie_sad_ready_2
+// bit[20] I4/I16 (0-I4MB, 1-I16MB)
+// bit[19:0] ie_sad_2
+#define IE_SAD_2 ((0x0067 << 2) + 0xfe067c00)
+// bit[31] ready_update
+// bit[30] data_update
+// bit[29:28] reserved
+// bit[27:22] ie_quant_3
+// bit[21] ie_sad_ready_3
+// bit[20] I4/I16 (0-I4MB, 1-I16MB)
+// bit[19:0] ie_sad_3
+#define IE_SAD_3 ((0x0068 << 2) + 0xfe067c00)
+// bit[31] enable_large_diff_16x8
+// bit[30] enable_large_diff_8x16
+// bit[29:16] adv_mv_8x8_weight
+// bit[15:14] reserved
+// bit[13:0] adv_mv_4x4x4_weight
+#define ADV_MV_CTL0 ((0x0069 << 2) + 0xfe067c00)
+// bit[31:16] adv_mv_16x16_weight
+// bit[15] enable_large_diff_16x16
+// bit[14:0] adv_mv_16_8_weight
+#define ADV_MV_CTL1 ((0x006a << 2) + 0xfe067c00)
+#define ADV_MV_CTL2 ((0x006b << 2) + 0xfe067c00)
+// bit[31] v3_skip_enable
+// bit[30] v3_step_1_weight_enable // for step1, will only use pre_weight for block0, only step_weight for block 1,2,3
+// bit[29] v3_l2_skip_only_use_l2_sad // set to 1 may allow l1 maybe not skip
+// bit[28] v3_mv_sad_weight_enable
+// bit[27] v3_ipred_type_enable
+// bit[25:12] force_skip_sad_1
+// bit[11:0] force_skip_sad_0
+#define V3_SKIP_CONTROL ((0x006c << 2) + 0xfe067c00)
+// bit[18:16] top_ipred_type_count
+// bit[15:14] Reserved
+// bit[13:12] top_ipred_type_rd_idx
+// bit[11:10] top_ipred_type_wr_idx
+// bit[9] left_ipred_type_ready
+// bit[8] top_ipred_type_ready
+// bit[7:6] left_mv_idx
+// bit[5:4] top_mv_idx
+// bit[3] - left_mv_ready
+// bit[2:0] top_mv_ready
+#define V3_TOP_LEFT_CTL ((0x006d << 2) + 0xfe067c00)
+#define V3_TOP_MV ((0x006e << 2) + 0xfe067c00)
+#define V3_LEFT_MV ((0x006f << 2) + 0xfe067c00)
+// bit[31:30] reserved
+// bit[29:16] v3_skip_weight_1
+// bit[15:12] reserved
+// bit[11:0] v3_skip_weight_0
+#define V3_SKIP_WEIGHT ((0x0070 << 2) + 0xfe067c00)
+// bit[31:28] reserved
+// bit[27:16] v3_l1_f_skip_max_sad
+// bit[15:12] reserved
+// bit[11:0] v3_l1_skip_max_sad
+#define V3_L1_SKIP_MAX_SAD ((0x0071 << 2) + 0xfe067c00)
+// bit[31:16] force_skip_sad_2
+// bit[15:0] v3_skip_weight_2
+#define V3_L2_SKIP_WEIGHT ((0x0072 << 2) + 0xfe067c00)
+// bit[21:16] v3_mv_sad_table_addr 0-15 table_step_0
+// bit[11:0] v3_mv_sad
+#define V3_MV_SAD_TABLE ((0x0073 << 2) + 0xfe067c00)
+// [31:16] v3_ie_f_zero_sad_i16
+// [15:0] v3_ie_f_zero_sad_i4
+#define V3_F_ZERO_CTL_0 ((0x0074 << 2) + 0xfe067c00)
+// [25] v3_no_ver_when_top_zero_en
+// [24] v3_no_hor_when_left_zero_en
+// [23:16] v3_max_I16_H_num // 0 means no break
+// [15:0] v3_me_f_zero_sad
+#define V3_F_ZERO_CTL_1 ((0x0075 << 2) + 0xfe067c00)
+#define V3_TOP_INTRA_INFO ((0x0076 << 2) + 0xfe067c00)
+#define V3_LEFT_INTRA_INFO ((0x0077 << 2) + 0xfe067c00)
+// [31:24] C_ipred_weight_H
+// [23:16] C_ipred_weight_V
+// [15:8] I4_ipred_weight_else
+// [7:0] I4_ipred_weight_most
+#define V3_IPRED_TYPE_WEIGHT_0 ((0x0078 << 2) + 0xfe067c00)
+// [31:24] I16_ipred_weight_DC
+// [23:16] I16_ipred_weight_H
+// [15:8] I16_ipred_weight_V
+// [7:0] C_ipred_weight_DC
+#define V3_IPRED_TYPE_WEIGHT_1 ((0x0079 << 2) + 0xfe067c00)
+// [31:16] v3_left_small_max_me_sad
+// [15:0] v3_left_small_max_ie_sad
+#define V3_LEFT_SMALL_MAX_SAD ((0x007a << 2) + 0xfe067c00)
+// (qr==7) & (qp==15) means force zero block
+// [31:26] v4_force_q_r_intra
+// [25:20] v4_force_q_r_inter
+// [19] v4_force_q_y_enable
+// [18:16] v4_force_qr_y
+// [15:12] v4_force_qp_y
+// [11:0] v4_force_skip_sad
+#define V4_FORCE_SKIP_CFG ((0x007b << 2) + 0xfe067c00)
+// v5 Complexity // Y(256 pixel per MB) and C(128 pixel per MB)
+// For every 4x4 block, calculate average and Add abs(pixel-average) together
+// bit[31:16] v5_diff_sum_C
+// bit[15:0] v5_diff_sum_Y
+#define V5_MB_DIFF_SUM ((0x007c << 2) + 0xfe067c00)
+// bit[31:24] v5_small_diff_cnt_C
+// bit[23:16] v5_small_diff_C
+// bit[15:8] v5_small_diff_cnt_Y
+// bit[7:0] v5_small_diff_Y
+#define V5_SMALL_DIFF_CNT ((0x007d << 2) + 0xfe067c00)
+// bit[31:29] Reserved
+// bit[28:24] v5_simple_block_cnt // 0 -15 Y 16-23 C
+// bit[23:20] v5_simple_pixel_cnt
+// bit[19:18] v5_simple_dq_wr_ptr
+// bit[17:16] v5_simple_dq_rd_ptr
+// bit[15:12] v5_simple_dq (Read Only)
+// bit[11:8] v5_simple_me_weight(Read Only)
+// bit[7] v5_use_small_diff_cnt
+// bit[6] v5_simple_mb_inter_all_en
+// bit[5] v5_simple_mb_inter_8x8_en
+// bit[4] v5_simple_mb_inter_16_8_en
+// bit[3] v5_simple_mb_inter_16x16_en
+// bit[2] v5_simple_mb_intra_en
+// bit[1] v5_simple_mb_C_en
+// bit[0] v5_simple_mb_Y_en
+#define V5_SIMPLE_MB_CTL ((0x007e << 2) + 0xfe067c00)
+// bit[31:28] v5_simple_dq_shift
+// bit[27:24] v5_simple_dq_6(-7 to +7)
+// bit[23:20] v5_simple_dq_5(-7 to +7)
+// bit[19:16] v5_simple_dq_4(-7 to +7)
+// bit[15:12] v5_simple_dq_3(-7 to +7)
+// bit[11:08] v5_simple_dq_2(-7 to +7)
+// bit[07:04] v5_simple_dq_1(-7 to +7)
+// bit[03:00] v5_simple_dq_0(-7 to +7)
+#define V5_SIMPLE_MB_DQUANT ((0x007f << 2) + 0xfe067c00)
+// bit[31:28] v5_simple_me_weight_shift
+// bit[27:24] v5_simple_me_weight_6(-7 to +7)
+// bit[23:20] v5_simple_me_weight_5(-7 to +7)
+// bit[19:16] v5_simple_me_weight_4(-7 to +7)
+// bit[15:12] v5_simple_me_weight_3(-7 to +7)
+// bit[11:08] v5_simple_me_weight_2(-7 to +7)
+// bit[07:04] v5_simple_me_weight_1(-7 to +7)
+// bit[03:00] v5_simple_me_weight_0(-7 to +7)
+#define V5_SIMPLE_MB_ME_WEIGHT ((0x0080 << 2) + 0xfe067c00)
+//
+// Closing file: qdct_regs.h
+//
+// HEVC
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe068000
+// -----------------------------------------------
+// HEVC2
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe06c000
+// -----------------------------------------------
+// DOC_TOP
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe06fc00
+// -----------------------------------------------
+//------------------------------------------------------------------------------
+// DOS top-level register offset
+//------------------------------------------------------------------------------
+// -----------------------------------------------
+// `define DOS_TOP_CBUS_BASE 8'h3f
+// -----------------------------------------------
+// [0] reserved
+// [1] Reset Dos top level registers, except sw_reset0/1/2 which is only reset by external reset_n.
+// [2] VDEC1 Reset assist, mdec's CBUS
+// [3] VDEC1 Reset mdec's VLD
+// [4] VDEC1 Reset mdec's VLD
+// [5] VDEC1 Reset mdec's VLD
+// [6] VDEC1 Reset mdec's IQIDCT
+// [7] VDEC1 Reset mdec's MC
+// [8] VDEC1 Reset mdec's DBLK
+// [9] VDEC1 Reset mdec's PIC_DC
+// [10] VDEC1 Reset mdec's Pscale
+// [11] VDEC1 Reset vcpu's MCPU
+// [12] VDEC1 Reset vcpu's CCPU
+// [13] VDEC1 Reset mmc_pre_arb
+#define DOS_SW_RESET0 ((0x0000 << 2) + 0xfe06fc00)
+// [31:27] reserved
+// [26] hcodec clk_en for henc assist
+// [25:22] reserved
+// [21] hcodec clk_en for henc qdct
+// [20] hcodec clk_en for henc vlc
+// [19] hcodec clk_en for assist and cbus
+// [18] hcodec clk_en for ddr
+// [17] hcodec clk_en for vcpu
+// [16] hcodec clk_en for hdec assist
+// [15] hcodec clk_en for hdec dblk
+// [14] reserved
+// [13] hcodec clk_en for hdec mc
+// [12] hcodec clk_en for hdec pic_dc
+// [11:10] reserved
+// [9] vdec clk_en for vdec assist and cbus
+// [8] vdec clk_en for ddr
+// [7] vdec clk_en for vcpu
+// [6] vdec clk_en for mdec vld
+// [5] vdec clk_en for mdec psc
+// [4] vdec clk_en for mdec pic_dc
+// [3] vdec clk_en for mdec mc
+// [2] vdec clk_en for mdec iqidct
+// [1] vdec clk_en for mdec dblk
+// [0] vdec clk_en for mdec assist
+#define DOS_GCLK_EN0 ((0x0001 << 2) + 0xfe06fc00)
+#define DOS_GEN_CTRL0 ((0x0002 << 2) + 0xfe06fc00)
+#define DOS_APB_ERR_CTRL ((0x0003 << 2) + 0xfe06fc00)
+#define DOS_APB_ERR_STAT ((0x0004 << 2) + 0xfe06fc00)
+#define DOS_VDEC_INT_EN ((0x0005 << 2) + 0xfe06fc00)
+#define DOS_HCODEC_INT_EN ((0x0006 << 2) + 0xfe06fc00)
+// [0] Reserved
+// [1] Reserved
+// [2] HCODEC Reset assist, hdec's CBUS
+// [3] HCODEC Reset hdec's VLD
+// [4] HCODEC Reset hdec's VLD
+// [5] HCODEC Reset hdec's VLD
+// [6] HCODEC Reset hdec's IQIDCT
+// [7] HCODEC Reset hdec's MC
+// [8] HCODEC Reset hdec's DBLK
+// [9] HCODEC Reset hdec's PIC_DC
+// [10] HCODEC Reset hdec's Pscale
+// [11] HCODEC Reset vcpu's MCPU
+// [12] HCODEC Reset vcpu's CCPU
+// [13] HCODEC Reset mmc_pre_arb
+// [14] HCODEC Reserved
+// [15] HCODEC Reserved
+// [16] HCODEC Reset henc's VLC
+#define DOS_SW_RESET1 ((0x0007 << 2) + 0xfe06fc00)
+// [0] Reserved
+// [1] Reserved
+// [2] VDEC2 Reset assist, mdec's CBUS
+// [3] VDEC2 Reset mdec's VLD
+// [4] VDEC2 Reset mdec's VLD
+// [5] VDEC2 Reset mdec's VLD
+// [6] VDEC2 Reset mdec's IQIDCT
+// [7] VDEC2 Reset mdec's MC
+// [8] VDEC2 Reset mdec's DBLK
+// [9] VDEC2 Reset mdec's PIC_DC
+// [10] VDEC2 Reset mdec's Pscale
+// [11] VDEC2 Reset vcpu's MCPU
+// [12] VDEC2 Reset vcpu's CCPU
+// [13] VDEC2 Reset mmc_pre_arb
+#define DOS_SW_RESET2 ((0x0008 << 2) + 0xfe06fc00)
+// [31:10] Reserved
+// [9] vdec2 clk_en for assist and cbus.
+// [8] vdec2 clk_en for ddr;
+// [7] vdec2 clk_en for vcpu;
+// [6] vdec2 clk_en for mdec vld
+// [5] vdec2 clk_en for mdec psc
+// [4] vdec2 clk_en for mdec pic_dc
+// [3] vdec2 clk_en for mdec mc
+// [2] vdec2 clk_en for mdec iqidct
+// [1] vdec2 clk_en for mdec dblk
+// [0] vdec2 clk_en for mdec assist
+#define DOS_GCLK_EN1 ((0x0009 << 2) + 0xfe06fc00)
+#define DOS_VDEC2_INT_EN ((0x000a << 2) + 0xfe06fc00)
+#define DOS_VDIN_LCNT ((0x000b << 2) + 0xfe06fc00)
+#define DOS_VDIN_FCNT ((0x000c << 2) + 0xfe06fc00)
+#define DOS_VDIN_CCTL ((0x000d << 2) + 0xfe06fc00)
+#define DOS_SCRATCH0 ((0x0010 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH1 ((0x0011 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH2 ((0x0012 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH3 ((0x0013 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH4 ((0x0014 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH5 ((0x0015 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH6 ((0x0016 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH7 ((0x0017 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH8 ((0x0018 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH9 ((0x0019 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH10 ((0x001a << 2) + 0xfe06fc00)
+#define DOS_SCRATCH11 ((0x001b << 2) + 0xfe06fc00)
+#define DOS_SCRATCH12 ((0x001c << 2) + 0xfe06fc00)
+#define DOS_SCRATCH13 ((0x001d << 2) + 0xfe06fc00)
+#define DOS_SCRATCH14 ((0x001e << 2) + 0xfe06fc00)
+#define DOS_SCRATCH15 ((0x001f << 2) + 0xfe06fc00)
+#define DOS_SCRATCH16 ((0x0020 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH17 ((0x0021 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH18 ((0x0022 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH19 ((0x0023 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH20 ((0x0024 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH21 ((0x0025 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH22 ((0x0026 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH23 ((0x0027 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH24 ((0x0028 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH25 ((0x0029 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH26 ((0x002a << 2) + 0xfe06fc00)
+#define DOS_SCRATCH27 ((0x002b << 2) + 0xfe06fc00)
+#define DOS_SCRATCH28 ((0x002c << 2) + 0xfe06fc00)
+#define DOS_SCRATCH29 ((0x002d << 2) + 0xfe06fc00)
+#define DOS_SCRATCH30 ((0x002e << 2) + 0xfe06fc00)
+#define DOS_SCRATCH31 ((0x002f << 2) + 0xfe06fc00)
+#define DOS_MEM_PD_VDEC ((0x0030 << 2) + 0xfe06fc00)
+#define DOS_MEM_PD_VDEC2 ((0x0031 << 2) + 0xfe06fc00)
+#define DOS_MEM_PD_HCODEC ((0x0032 << 2) + 0xfe06fc00)
+#define DOS_MEM_PD_HEVC ((0x0033 << 2) + 0xfe06fc00)
+#define DOS_SW_RESET3 ((0x0034 << 2) + 0xfe06fc00)
+#define DOS_GCLK_EN3 ((0x0035 << 2) + 0xfe06fc00)
+#define DOS_HEVC_INT_EN ((0x0036 << 2) + 0xfe06fc00)
+#define DOS_SW_RESET4 ((0x0037 << 2) + 0xfe06fc00)
+#define DOS_GCLK_EN4 ((0x0038 << 2) + 0xfe06fc00)
+#define DOS_MEM_PD_WAVE_0 ((0x0039 << 2) + 0xfe06fc00)
+#define DOS_WAVE_CNTL_STAT ((0x003a << 2) + 0xfe06fc00)
+#define DOS_MEM_PD_WAVE_1 ((0x003b << 2) + 0xfe06fc00)
+#define DOS_MEM_PD_WAVE_2 ((0x003c << 2) + 0xfe06fc00)
+// bit[31] mcrcc_stall_en
+// bit[30:28] Reserved
+// bit[27:20] target_canvas
+// bit[19:10] target_mby
+// bit[ 9: 0] target_mbx
+#define DOS_VDEC_MCRCC_STALL_CTRL ((0x0040 << 2) + 0xfe06fc00)
+#define DOS_VDEC_MCRCC_STALL2_CTRL ((0x0042 << 2) + 0xfe06fc00)
+#define DOS_VDEC2_MCRCC_STALL_CTRL ((0x0041 << 2) + 0xfe06fc00)
+#define DOS_VDEC2_MCRCC_STALL2_CTRL ((0x0043 << 2) + 0xfe06fc00)
+#define DOS_MEM_PD_HEVC2 ((0x0044 << 2) + 0xfe06fc00)
+#define DOS_HEVC2_INT_EN ((0x0045 << 2) + 0xfe06fc00)
+// bit[1] s_clk off
+// bit[0] m_clk off
+#define DOS_CFG_CMPIF_BRIDGE ((0x0048 << 2) + 0xfe06fc00)
+// bit[31] cfg_stall_en
+// bit[30] co_mv_stall_en
+// bit[29] cfg_stall_force
+// bit[28:24] reserved
+// bit[23:12] cfg_stall_tilestrt_ctb_y
+// bit[11: 0] cfg_stall_tilestrt_ctb_x
+#define DOS_HEVC_STALL_START ((0x0050 << 2) + 0xfe06fc00)
+// bit[31:24] cfg_stall_canvas
+// bit[23:12] cfg_stall_tileend_ctb_y
+// bit[11: 0] cfg_stall_tileend_ctb_x
+#define DOS_HEVC_STALL_END ((0x0051 << 2) + 0xfe06fc00)
+// bit[31:24] reserved
+// bit[23:12] cfg_stall_ctb_y
+// bit[11: 0] cfg_stall_ctb_x
+#define DOS_HEVC_STALL_POSITION ((0x0052 << 2) + 0xfe06fc00)
+// bit[31] cfg_stall_en
+// bit[30] co_mv_stall_en
+// bit[29] cfg_stall_force
+// bit[28:24] reserved
+// bit[23:12] cfg_stall_tilestrt_ctb_y
+// bit[11: 0] cfg_stall_tilestrt_ctb_x
+#define DOS_HEVC2_STALL_START ((0x0053 << 2) + 0xfe06fc00)
+// bit[31:24] cfg_stall_canvas
+// bit[23:12] cfg_stall_tileend_ctb_y
+// bit[11: 0] cfg_stall_tileend_ctb_x
+#define DOS_HEVC2_STALL_END ((0x0054 << 2) + 0xfe06fc00)
+// bit[31:24] reserved
+// bit[23:12] cfg_stall_ctb_y
+// bit[11: 0] cfg_stall_ctb_x
+#define DOS_HEVC2_STALL_POSITION ((0x0055 << 2) + 0xfe06fc00)
+#define DOS_SECURE_CTL_INDEX ((0x0080 << 2) + 0xfe06fc00)
+#define DOS_SECURE_CTL_DATA ((0x0081 << 2) + 0xfe06fc00)
+#define DOS_SECURE_REG_NULL ((0x0082 << 2) + 0xfe06fc00)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: REG_LIST_DOS_RTL.h
+//
+//
+// Reading file: gdc_regs.h
+//
+//===========================================================================
+////// GDC Registers
+//===========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe008800
+// -----------------------------------------------
+#define GDC_REG_START ((0x0000 << 2) + 0xfe008800)
+//
+// Closing file: gdc_regs.h
+//
+//
+// Reading file: ge2d_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+//GE2D Registers
+//===========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe008c00
+// -----------------------------------------------
+//Bit 31, destination bytemask only if destination bitmask is enable
+//Bit 30, destination bitmask enable
+//Bit 29, source2 key enable
+//Bit 28, source2 key mode, 0: mask data when match, 1: mask data when unmatch
+//Bit 27, source1 key enable
+//Bit 26, source1 key mode, 0: mask data when match, 1: mask data when unmatch
+//Bit 25:24, dst1 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 23 dst clip mode, 0: write inside clip window, 1: write outside clip window
+//Bit 22:17, reserved
+//Bit 16:15, src2 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 14 src2 fill mode, 0: repeat data, 1: fill default color
+//Bit 13:12 src2 picture struct, 00: frame, 10: even, 11: odd
+//Bit 11 src1 x direction yc ration, 0: 1:1, 1: 2:1
+//Bit 10 src1 y direction yc ration, 0: 1:1, 1: 2:1
+//Bit 9:7 reserved
+//Bit 6:5, src1 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 4 src1 fill mode, 0: repeat data, 1: fill default color
+//Bit 3 src1 lookup table enable
+//Bit 2:1 src1 picture struct, 00: frame, 10: even, 11: odd
+//Bit 0 src1 separate buffer enable
+#define GE2D_GEN_CTRL0 ((0x00a0 << 2) + 0xfe008c00)
+//Bit 31, soft rst
+//Bit 30, dst write response counter reset
+//Bit 29, disable adding dst write response count to busy bit
+//Bit 28:26, reserved
+//bit 25:24, interrupt control, if bit[0] true, generate interrupt when one command done,
+// if bit[1] true, generate interrupt when ge2d change from busy to not busy
+//Bit 23:22 src2 burst size control
+//Bit 21:16 src1 burst size control, 5:4, yfifo, 3:2, cbfifo, 1:0, crfifo
+// each 2bit, 00: 24 64bitword, 01: 32 64bitword, 10: 48 64bitwords, 11: 64 64bitwords
+//Bit 15:14, dst1 picture struct, 00: frame, 10:top, 11: bottom
+//Bit 13:12, bit 13 if true, force read src1, bit 12 if true, force read src2
+//Bit 11, dst2 request urgent enable
+//Bit 10, src1 request urgent enable
+//Bit 9, src2 request urgent enable
+//Bit 8, dst1 request urgent enable
+//Bit 7:0 src1 global alpha
+#define GE2D_GEN_CTRL1 ((0x00a1 << 2) + 0xfe008c00)
+//Bit31 alpha conversion mode in alu, 0: alpha_out = (alpha !=0) ? alpha +1 : 0;
+// otherwise, alpha_out = (alpha < 128) ? alpha: alpha + 1;
+//Bit30 color conversion mode in alu, 0: color_out = (color != 0) ? color +1: 0;
+// otherwise, color_out = (color < 128) ? color: color + 1;
+//Bit29 src1_gb_alpha_en, As = src1_gb_alpha_en ? Asr * Ag: Asr
+//Bit28 dst1_color_round_mode, 0: truncate, 1: + 0.5 rounding
+//Bit27 src2_color_expand_mode, 0: add 0, 1: add MSBs
+//Bit26 src2_alpha_expand_mode, 0: add 0, 1: add MSBs
+//Bit25 src1_color_expand_mode, 0: add 0, 1: add MSBs
+//Bit24 src1_alpha_expand_mode, 0: add 0, 1: add MSBs
+//Bit 23 if true, dst little endian, otherwise big endian
+//Bit 22:19 dst1 color_map
+// dst1_format=0 : output 8-bit;
+// dst1_format=1, dst1_color_map=1: output 16-bit YCbCr 655;
+// dst1_format=1, dst1_color_map=2: output 16-bit YCbCr 844;
+// dst1_format=1, dst1_color_map=3: output 16-bit YCbCrA 6442;
+// dst1_format=1, dst1_color_map=4: output 16-bit YCbCrA 4444;
+// dst1_format=1, dst1_color_map=5: output 16-bit YCbCr 565;
+// dst1_format=1, dst1_color_map=6: output 16-bit AYCbCr 4444;
+// dst1_format=1, dst1_color_map=7: output 16-bit AYCbCr 1555;
+// dst1_format=1, dst1_color_map=8: output 16-bit YCbCrA 4642;
+// dst1_format=1, dst1_color_map=9: output 16-bit CbCr 88;
+// dst1_format=1, dst1_color_map=10:output 16-bit CrCb 88;
+// dst1_format=2, dst1_color_map=0: output 24-bit YCbCr 888;
+// dst1_format=2, dst1_color_map=1: output 24-bit YCbCrA 5658;
+// dst1_format=2, dst1_color_map=2: output 24-bit AYCbCr 8565;
+// dst1_format=2, dst1_color_map=3: output 24-bit YCbCrA 6666;
+// dst1_format=2, dst1_color_map=4: output 24-bit AYCbCr 6666;
+// dst1_format=2, dst1_color_map=5: output 24-bit CrCbY 888;
+// dst1_format=3, dst1_color_map=0: output 32-bit YCbCrA 8888;
+// dst1_format=3, dst1_color_map=1: output 32-bit AYCbCr 8888;
+// dst1_format=3, dst1_color_map=2: output 32-bit ACrCbY 8888;
+// dst1_format=3, dst1_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 17:16 dst1_format, 00: 8bit, 01:16bit, 10:24bit, 11: 32bit
+//Bit 15 if true, src2 little endian, otherwise big endian
+//Bit 14:11 src2 color_map
+// src2_format=0 : output 8-bit;
+// src2_format=1, src2_color_map=1: output 16-bit YCbCr 655;
+// src2_format=1, src2_color_map=2: output 16-bit YCbCr 844;
+// src2_format=1, src2_color_map=3: output 16-bit YCbCrA 6442;
+// src2_format=1, src2_color_map=4: output 16-bit YCbCrA 4444;
+// src2_format=1, src2_color_map=5: output 16-bit YCbCr 565;
+// src2_format=1, src2_color_map=6: output 16-bit AYCbCr 4444;
+// src2_format=1, src2_color_map=7: output 16-bit AYCbCr 1555;
+// src2_format=1, src2_color_map=8: output 16-bit YCbCrA 4642;
+// src2_format=2, src2_color_map=0: output 24-bit YCbCr 888;
+// src2_format=2, src2_color_map=1: output 24-bit YCbCrA 5658;
+// src2_format=2, src2_color_map=2: output 24-bit AYCbCr 8565;
+// src2_format=2, src2_color_map=3: output 24-bit YCbCrA 6666;
+// src2_format=2, src2_color_map=4: output 24-bit AYCbCr 6666;
+// src2_format=2, src2_color_map=5: output 24-bit CrCbY 888;
+// src2_format=3, src2_color_map=0: output 32-bit YCbCrA 8888;
+// src2_format=3, src2_color_map=1: output 32-bit AYCbCr 8888;
+// src2_format=3, src2_color_map=2: output 32-bit ACrCbY 8888;
+// src2_format=3, src2_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 9:8 src2 format, 00: 8bit, 01:16bit, 10:24bit 11: 32bit
+//Bit 7 if true, src1 little endian, otherwise big endian
+//Bit 6:3 src1 color_map
+// src1_format=0 : output 8-bit;
+// src1_format=1, src1_color_map=0: output 4:2:2 (Y0Cb0Y1Cr0);
+// src1_format=1, src1_color_map=1: output 16-bit YCbCr 655;
+// src1_format=1, src1_color_map=2: output 16-bit YCbCr 844;
+// src1_format=1, src1_color_map=3: output 16-bit YCbCrA 6442;
+// src1_format=1, src1_color_map=4: output 16-bit YCbCrA 4444;
+// src1_format=1, src1_color_map=5: output 16-bit YCbCr 565;
+// src1_format=1, src1_color_map=6: output 16-bit AYCbCr 4444;
+// src1_format=1, src1_color_map=7: output 16-bit AYCbCr 1555;
+// src1_format=1, src2_color_map=8: output 16-bit YCbCrA 4642;
+// src1_format=2, src1_color_map=0: output 24-bit YCbCr 888;
+// src1_format=2, src1_color_map=1: output 24-bit YCbCrA 5658;
+// src1_format=2, src1_color_map=2: output 24-bit AYCbCr 8565;
+// src1_format=2, src1_color_map=3: output 24-bit YCbCrA 6666;
+// src1_format=2, src1_color_map=4: output 24-bit AYCbCr 6666;
+// src1_format=2, src1_color_map=5: output 24-bit CrCbY 888;
+// src1_format=2, src1_color_map=14:output 8-bit Y and 16-bit CbCr;
+// src1_format=2, src1_color_map=15:output 8-bit Y and 16-bit CrCb;
+// src1_format=3, src1_color_map=0: output 32-bit YCbCrA 8888;
+// src1_format=3, src1_color_map=1: output 32-bit AYCbCr 8888;
+// src1_format=3, src1_color_map=2: output 32-bit ACrCbY 8888;
+// src1_format=3, src1_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 1:0 src1 format, 00: 8bit, 01:16bit/4:2:2, 10:24bit 11: 32bit
+#define GE2D_GEN_CTRL2 ((0x00a2 << 2) + 0xfe008c00)
+//Bit 9 if true, all src2 data use default color
+//Bit 8 if true, all src1 data use default color
+//Bit 7 if true, dst x/y swap
+//Bit 6 if true, dst x direction reversely read
+//Bit 5 if true, dst y direction reversely read
+//Bit 4 if true, src2 x direction reversely read
+//Bit 3 if true, src2 y direction reversely read
+//Bit 2 if true, src1 x direction reversely read
+//Bit 1 if true, src1 y direction reversely read
+//Bit 0 cmd write
+#define GE2D_CMD_CTRL ((0x00a3 << 2) + 0xfe008c00)
+//Read only
+//Bit 28:17 dst write response counter, for debug only
+//Bit 16:7 ge2d_dp status, for debug only
+//Bit 6 read src1 cmd ready
+//Bit 5 read src2 cmd ready
+//Bit 4 pre dpcmd ready
+//Bit 3 ge2d dpcmd ready
+//Bit 2 ge2d buffer command valid
+//Bit 1 ge2d current command valid
+//Bit 0 ge2d busy
+#define GE2D_STATUS0 ((0x00a4 << 2) + 0xfe008c00)
+//
+//Read only
+// Bit 29:16 ge2d_dst1_status, for debug only
+// Bit 15 ge2d_rd_src2 core.fifo_empty
+// Bit 14 ge2d_rd_src2 core.fifo_overflow
+// Bit 13:12 ge2d_rd_src2 core.req_st
+// Bit 11 ge2d_rd_src2 cmd_if.cmd_err, true if cmd_format=1
+// Bit 10 ge2d_rd_src2 cmd_if.cmd_st, 0=IDLE state, 1=BUSY state
+// Bit 9 ge2d_rd_src1 luma_core(chroma_core).fifo_empty
+// Bit 8 ge2d_rd_src1 luma_core(chroma_core).fifo_overflow
+// Bit 7: 6 ge2d_rd_src1 chroma_core.req_st_cr
+// Bit 5: 4 ge2d_rd_src1 chroma_core.req_st_cb
+// Bit 3: 2 ge2d_rd_src1 luma_core.req_st_y
+// Bit 1 ge2d_rd_src1 cmd_if.stat_read_window_err, 1=reading/clipping window setting exceed limit
+// Bit 0 ge2d_rd_src1 cmd_if.cmd_st, 0=IDLE state, 1=BUSY state
+#define GE2D_STATUS1 ((0x00a5 << 2) + 0xfe008c00)
+//SRC1 default clolor
+//{Y,Cb,Cr,A}/{R,G,B,A}
+#define GE2D_SRC1_DEF_COLOR ((0x00a6 << 2) + 0xfe008c00)
+//Bit 31, SRC1 clip x start extra, if true, one more data is read for chroma
+//Bit 28:16, SRC1 clip x start
+//Bit 15, SRC1 clip x end extra, if true, one more data is read for chroma
+//Bit 12:0, SRC1 clip x end
+#define GE2D_SRC1_CLIPX_START_END ((0x00a7 << 2) + 0xfe008c00)
+//Bit 31, SRC1 clip y start extra, if true, one more data is read for chroma
+//Bit 28:16, SRC1 clip y start
+//Bit 15, SRC1 clip y end extra, if true, one more data is read for chroma
+//Bit 12:0, SRC1 clip y end
+#define GE2D_SRC1_CLIPY_START_END ((0x00a8 << 2) + 0xfe008c00)
+//Bit 31:24, SRC1 canvas address0
+//Bit 23:16, SRC1 canvas address1
+//Bit 15:8, SRC1 canvas address2
+#define GE2D_SRC1_CANVAS ((0x00a9 << 2) + 0xfe008c00)
+//Bit 31, SRC1 x start extra bit1, if true, one more chroma data is read for x even start chroma data when y/c ratio = 2
+// or x even/odd start chroma extra data when y/c ratio = 1
+//Bit 30, SRC1 x start extra bit0, if true, one more chroma data is read for x odd start chroma data when y/c ratio = 2
+//Bit 29:16, SRC1 x start, signed data
+//Bit 15, SRC1 x end extra bit1, if true, one more chroma data is read for x odd end chroma data when y/c ratio = 2
+// or x even/odd end chroma extra data when y/c ratio = 1
+//Bit 14, SRC1 x end extra bit0, if true, one more chroma data is read for x even end chroma data when y/c ratio = 2
+//Bit 13:0, SRC1 x end, signed data
+#define GE2D_SRC1_X_START_END ((0x00aa << 2) + 0xfe008c00)
+//Bit 31, SRC1 y start extra, if true, one more chroma data is read for y even start chroma data when y/c ratio = 2
+// or y even/odd start chroma extra data when y/c ratio = 1
+//Bit 30, SRC1 y start extra, if true, one more chroma data is read for x odd start chroma data when y/c ratio = 2
+//Bit 28:16, SRC1 y start
+//Bit 15, SRC1 y end extra bit1, if true, one more chroma data is read for y odd end chroma data when y/c ratio = 2
+// or y even/odd end chroma extra data when y/c ratio = 1
+//Bit 14, SRC1 y end extra bit0, if true, one more chroma data is read for y even end chroma data when y/c ratio = 2
+//Bit 12:0, SRC1 y end
+#define GE2D_SRC1_Y_START_END ((0x00ab << 2) + 0xfe008c00)
+// Bit 31: 9 Reserved
+// Bit 8 RW, 0 = Write LUT, 1 = Read LUT
+// Bit 7: 0 RW, lut_addr
+#define GE2D_SRC1_LUT_ADDR ((0x00ac << 2) + 0xfe008c00)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define GE2D_SRC1_LUT_DAT ((0x00ad << 2) + 0xfe008c00)
+//Bit 19, if true, horizontal formatter using repeat to get the pixel, otherwise using interpolation
+//Bit 18, horizontal formatter en
+//Bit 17, if true, vertical formatter using repeat to get the pixel, otherwise using interpolation
+//Bit 16, vertical formatter en
+//Bit 15:8 X direction chroma phase,
+// [7:4] for x direction even start/end chroma phase when y/c ratio = 2
+// or start/end even/odd chroma phase when y/c ratio = 1
+// [3:0] for x direction odd start/end chroma phase only when y/c ration = 2
+//Bit 7:0 Y direction chroma phase,
+// [7:4] for y direction even start/end chroma phase when y/c ratio = 2
+// or start/end even/odd chroma phase when y/c ratio = 1
+// [3:0] for y direction odd start/end chroma phase only when y/c ration = 2
+#define GE2D_SRC1_FMT_CTRL ((0x00ae << 2) + 0xfe008c00)
+//SRC2 default clolor
+//{Y,Cb,Cr,A}/{R,G,B,A}
+#define GE2D_SRC2_DEF_COLOR ((0x00af << 2) + 0xfe008c00)
+//Bit 28:16, SRC2 clip x start
+//Bit 12:0, SRC2 clip x end
+#define GE2D_SRC2_CLIPX_START_END ((0x00b0 << 2) + 0xfe008c00)
+//Bit 28:16, SRC2 clip y start
+//Bit 12:0, SRC2 clip y end
+#define GE2D_SRC2_CLIPY_START_END ((0x00b1 << 2) + 0xfe008c00)
+//Bit 28:16, SRC2 x start
+//Bit 12:0, SRC2 x end
+#define GE2D_SRC2_X_START_END ((0x00b2 << 2) + 0xfe008c00)
+//Bit 28:16, SRC2 y start
+//Bit 12:0, SRC2 y end
+#define GE2D_SRC2_Y_START_END ((0x00b3 << 2) + 0xfe008c00)
+//Bit 28:16, DST clip x start
+//Bit 12:0, DST clip x end
+#define GE2D_DST_CLIPX_START_END ((0x00b4 << 2) + 0xfe008c00)
+//
+//Bit 28:16, DST clip y start
+//Bit 12:0, DST clip y end
+#define GE2D_DST_CLIPY_START_END ((0x00b5 << 2) + 0xfe008c00)
+//Bit 28:16, DST x start
+//Bit 12:0, DST x end
+#define GE2D_DST_X_START_END ((0x00b6 << 2) + 0xfe008c00)
+//
+//Bit 28:16, DST x start
+//Bit 12:0, DST x end
+#define GE2D_DST_Y_START_END ((0x00b7 << 2) + 0xfe008c00)
+//Bit 23:16 DST2 canvas address
+//Bit 15:8 SRC2 canvas address
+//Bit 7:0 DST1 canvas address
+#define GE2D_SRC2_DST_CANVAS ((0x00b8 << 2) + 0xfe008c00)
+//vertical scaler phase step
+//Bit 28:0, 5.24 format
+#define GE2D_VSC_START_PHASE_STEP ((0x00b9 << 2) + 0xfe008c00)
+//phase slope
+//Bit 24:0, bit 24 signed bit
+#define GE2D_VSC_PHASE_SLOPE ((0x00ba << 2) + 0xfe008c00)
+//Bit 30:29, vertical repeat line0 number
+//Bit 23:0, vertical scaler initial phase
+#define GE2D_VSC_INI_CTRL ((0x00bb << 2) + 0xfe008c00)
+//horizontal scaler phase step
+//Bit 28:0, 5.24 format
+#define GE2D_HSC_START_PHASE_STEP ((0x00bc << 2) + 0xfe008c00)
+//phase slope
+//Bit 24:0, bit 24 signed bit
+#define GE2D_HSC_PHASE_SLOPE ((0x00bd << 2) + 0xfe008c00)
+//Bit 30:29, horizontal repeat line0 number
+//Bit 23:0, horizontal scaler initial phase
+#define GE2D_HSC_INI_CTRL ((0x00be << 2) + 0xfe008c00)
+//Bit 31:24, advance number in this round, if horizontal scaler is working on dividing mode
+//Bit 23:0, horizontal scaler advance phase in this round, if horizontal scaler is working on dividing mode
+#define GE2D_HSC_ADV_CTRL ((0x00bf << 2) + 0xfe008c00)
+//Bit 30, vertical nearest mode enable, must set vt_bank_length = 4
+//Bit 29, horizontal nearest mode enable, must set hz_bank_length = 4
+//Bit 28, horizontal scaler dividing mode enable
+//Bit 27:15, horizontal dividing length, if bit 28 is enable
+//Bit 14, pre horizontal scaler enable
+//Bit 13, pre vertical scale enable
+//Bit 12, vertical scale enable
+//Bit 11, horizontal scaler enable
+//Bit 9, if true, treat horizontal repeat line number(GE2D_HSC_INI_CTRL bit 30:29) as repeating line,
+// otherwise using treat horizontal repeat line number as minus line number.
+//Bit 8, if true, treat vertical repeat line number(GE2D_VSC_INI_CTRL bit 30:29) as repeating line,
+// otherwise using treat vertical repeat line number as minus line number.
+//Bit 7, if true, always use phase0 in vertical scaler
+//Bit 6:4, vertical scaler bank length
+//Bit 3, if true, always use phase0 in horizontal scaler
+//Bit 2:0, horizontal scaler bank length
+#define GE2D_SC_MISC_CTRL ((0x00c0 << 2) + 0xfe008c00)
+//Read only
+//vertical scaler next round integer pixel pointer, signed data
+//Bit 13:0
+#define GE2D_VSC_NRND_POINT ((0x00c1 << 2) + 0xfe008c00)
+//Read only
+//vertical scaler next round phase
+//bit 23:0
+#define GE2D_VSC_NRND_PHASE ((0x00c2 << 2) + 0xfe008c00)
+//Read only
+//horizontal scaler next round integer pixel pointer, signed data
+//Bit 13:0
+#define GE2D_HSC_NRND_POINT ((0x00c3 << 2) + 0xfe008c00)
+//Read only
+//horizontal scaler next round phase
+//bit 23:0
+#define GE2D_HSC_NRND_PHASE ((0x00c4 << 2) + 0xfe008c00)
+//
+//Bit 28:20, pre_offset0
+//Bit 18:10, pre_offset1
+//Bit 8:0, pre_offset2
+#define GE2D_MATRIX_PRE_OFFSET ((0x00c5 << 2) + 0xfe008c00)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define GE2D_MATRIX_COEF00_01 ((0x00c6 << 2) + 0xfe008c00)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define GE2D_MATRIX_COEF02_10 ((0x00c7 << 2) + 0xfe008c00)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define GE2D_MATRIX_COEF11_12 ((0x00c8 << 2) + 0xfe008c00)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define GE2D_MATRIX_COEF20_21 ((0x00c9 << 2) + 0xfe008c00)
+//Bit 28:16 coef22
+//Bit 7 input y/cb/cr saturation enable
+//Bit 0 conversion matrix enable
+#define GE2D_MATRIX_COEF22_CTRL ((0x00ca << 2) + 0xfe008c00)
+//Bit 28:20, offset0
+//Bit 18:10, offset1
+//Bit 8:0, offset2
+#define GE2D_MATRIX_OFFSET ((0x00cb << 2) + 0xfe008c00)
+//Bit 26:25, SRC1 color multiplier alpha selection
+// if 00, Cs = Csr
+// if 01, Cs = Csr * Asr * Ag (if source is not premultiplied)
+// if 10, Cs = Csr * Ag (if source is premultipied)
+//Bit 24 SRC2 color multiplier alpha selection
+// if 0, no multiplier, Cd = Cdr, otherwise, Cd = Cdr * Ad.
+//Bit 22:12 ALU color operation
+// bit10:8 Blending Mode Parameter
+// 3'b000: ADD Cs*Fs + Cd*Fd
+// 3'b001: SUBTRACT Cs*Fs - Cd*Fd
+// 3'b010: REVERSE SUBTRACT Cd*Fd - Cs*Fs
+// 3'b011: MIN min(Cs*Fs, Cd*Fd)
+// 3'b100: MAX max(Cs*Fs, Cd*Fd)
+// 3'b101: LOGIC OP Cs op Cd
+// bit7:4 Source Color Blending Factor CFs
+// 4'b0000: ZERO 0
+// 4'b0001: ONE 1
+// 4'b0010: SRC_COLOR Cs(RGBs)
+// 4'b0011: ONE_MINUS_SRC_COLOR 1 - Cs(RGBs)
+// 4'b0100: DST_COLOR Cd(RGBd)
+// 4'b0101: ONE_MINUS_DST_COLOR 1 - Cd(RGBd)
+// 4'b0110: SRC_ALPHA As
+// 4'b0111: ONE_MINUS_SRC_ALPHA 1 - As
+// 4'b1000: DST_ALPHA Ad
+// 4'b1001: ONE_MINUS_DST_ALPHA 1 - Ad
+// 4'b1010: CONST_COLOR Cc(RGBc)
+// 4'b1011: ONE_MINUS_CONST_COLOR 1 - Cc(RGBc)
+// 4'b1100: CONST_ALPHA Ac
+// 4'b1101: ONE_MINUS_CONST_ALPHA 1 - Ac
+// 4'b1110: SRC_ALPHA_SATURATE min(As,1-Ad)
+// bit3:0 dest Color Blending Factor CFd, when bit10:8 != LOGIC OP
+// 4'b0000: ZERO 0
+// 4'b0001: ONE 1
+// 4'b0010: SRC_COLOR Cs(RGBs)
+// 4'b0011: ONE_MINUS_SRC_COLOR 1 - Cs(RGBs)
+// 4'b0100: DST_COLOR Cd(RGBd)
+// 4'b0101: ONE_MINUS_DST_COLOR 1 - Cd(RGBd)
+// 4'b0110: SRC_ALPHA As
+// 4'b0111: ONE_MINUS_SRC_ALPHA 1 - As
+// 4'b1000: DST_ALPHA Ad
+// 4'b1001: ONE_MINUS_DST_ALPHA 1 - Ad
+// 4'b1010: CONST_COLOR Cc(RGBc)
+// 4'b1011: ONE_MINUS_CONST_COLOR 1 - Cc(RGBc)
+// 4'b1100: CONST_ALPHA Ac
+// 4'b1101: ONE_MINUS_CONST_ALPHA 1 - Ac
+// 4'b1110: SRC_ALPHA_SATURATE min(As,1-Ad)
+// bit3:0 logic operations, when bit10:8 == LOGIC OP
+// 4'b0000: CLEAR 0
+// 4'b0001: COPY s
+// 4'b0010: NOOP d
+// 4'b0011: SET 1
+// 4'b0100: COPY_INVERT ~s
+// 4'b0101: INVERT ~d
+// 4'b0110: AND_REVERSE s & ~d
+// 4'b0111: OR_REVERSE s | ~d
+// 4'b1000: AND s & d
+// 4'b1001: OR s | d
+// 4'b1010: NAND ~(s & d)
+// 4'b1011: NOR ~(s | d)
+// 4'b1100: XOR s ^ d
+// 4'b1101: EQUIV ~(s ^ d)
+// 4'b1110: AND_INVERTED ~s & d
+// 4'b1111: OR_INVERTED ~s | d
+//Bit 10:0 ALU alpha operation
+// bit10:8 Blending Equation Math Operation
+// 3'b000: ADD As*Fs + Ad*Fd
+// 3'b001: SUBTRACT As*Fs - Ad*Fd
+// 3'b010: REVERSE SUBTRACT Ad*Fd - As*Fs
+// 3'b011: MIN min(As*Fs, Ad*Fd)
+// 3'b100: MAX max(As*Fs, Ad*Fd)
+// 3'b101: LOGIC OP As op Ad
+// bit7:4 Source alpha Blending Factor AFs
+// 4'b0000 0
+// 4'b0001 1
+// 4'b0010 As
+// 4'b0011 1 - As
+// 4'b0100 Ad
+// 4'b0101 1 - Ad
+// 4'b0110 Ac
+// 4'b0111 1 - Ac
+// .... reserved
+// bit3:0 Destination alpha Blending Factor AFd, when bit10:8 != LOGIC OP
+// 4'b0000 0
+// 4'b0001 1
+// 4'b0010 As
+// 4'b0011 1 - As
+// 4'b0100 Ad
+// 4'b0101 1 - Ad
+// 4'b0110 Ac
+// 4'b0111 1 - Ac
+// .... reserved
+// bit3:0 logic operations, when bit10:8 == LOGIC OP
+// 4'b0000: CLEAR 0
+// 4'b0001: COPY s
+// 4'b0010: NOOP d
+// 4'b0011: SET 1
+// 4'b0100: COPY_INVERT ~s
+// 4'b0101: INVERT ~d
+// 4'b0110: AND_REVERSE s & ~d
+// 4'b0111: OR_REVERSE s | ~d
+// 4'b1000: AND s & d
+// 4'b1001: OR s | d
+// 4'b1010: NAND ~(s & d)
+// 4'b1011: NOR ~(s | d)
+// 4'b1100: XOR s ^ d
+// 4'b1101: EQUIV ~(s ^ d)
+// 4'b1110: AND_INVERTED ~s & d
+// 4'b1111: OR_INVERTED ~s | d
+#define GE2D_ALU_OP_CTRL ((0x00cc << 2) + 0xfe008c00)
+//bit 31:0 (RGBA,YCBCRA)
+#define GE2D_ALU_CONST_COLOR ((0x00cd << 2) + 0xfe008c00)
+//SRC1 Key
+//31:0
+#define GE2D_SRC1_KEY ((0x00ce << 2) + 0xfe008c00)
+//SRC1 Key Mask
+//31:0
+#define GE2D_SRC1_KEY_MASK ((0x00cf << 2) + 0xfe008c00)
+//SRC2 Key
+//31:0
+#define GE2D_SRC2_KEY ((0x00d0 << 2) + 0xfe008c00)
+//SRC2 Key Mask
+//31:0
+#define GE2D_SRC2_KEY_MASK ((0x00d1 << 2) + 0xfe008c00)
+//Destination Bit Mask
+//31:0
+#define GE2D_DST_BITMASK ((0x00d2 << 2) + 0xfe008c00)
+//Bit 31 DP onoff mode, 0: on_counter means how many pixels will output before ge2d turns off
+// 1: on_counter means how many clocks will ge2d turn on before ge2d turns off
+//Bit 30:16 DP on counter
+//Bit 15 0: vd_format doesnt have onoff mode, 1: vd format has onoff mode
+//Bit 14:0 DP off counter
+#define GE2D_DP_ONOFF_CTRL ((0x00d3 << 2) + 0xfe008c00)
+//Because there are many coefficients used in the vertical filter and horizontal filters,
+//indirect access the coefficients of vertical filter and horizontal filter is used.
+//For vertical filter, there are 33x4 coefficients
+//For horizontal filter, there are 33x4 coefficients
+//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
+//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
+//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
+//Bit 8 type of index, 0: vertical coef
+// 1: horizontal coef
+//Bit 6:0 coef index
+#define GE2D_SCALE_COEF_IDX ((0x00d4 << 2) + 0xfe008c00)
+//coefficients for vertical filter and horizontal filter
+#define GE2D_SCALE_COEF ((0x00d5 << 2) + 0xfe008c00)
+//Bit 24 src2 alpha fill mode: together with GE2D_GEN_CTRL0[4](fill_mode), define what alpha values are used
+// for the area outside the clipping window. As below:
+// fill_mode=0, alpha_fill_mode=0 : use inner alpha, (or default_alpha if src data have no alpha values);
+// fill_mode=0, alpha_fill_mode=1 : use outside_alpha;
+// fill_mode=1, alpha_fill_mode=0 : use default_alpha;
+// fill_mode=1, alpha_fill_mode=1 : use outside_alpha.
+//Bit 23:16 src2 outside alpha
+//Bit 8 src1 alpha fill mode, refer to src2 alpha fill mode above.
+//Bit 7:0 src1 outside alpha
+#define GE2D_SRC_OUTSIDE_ALPHA ((0x00d6 << 2) + 0xfe008c00)
+//Bit 31 antiflick enable
+//Bit 24 1: alpha value for the first line use repeated alpha, 0: use bit 23:16 as the first line alpha
+//Bit 23:16 register value for the first line alpha when bit 24 is 1
+//Bit 8 1: alpha value for the last line use repeated alpha, 0: use bit 7:0 as the last line alpha
+//Bit 7:0 register value for the last line alpha when bit 8 is 1
+#define GE2D_ANTIFLICK_CTRL0 ((0x00d8 << 2) + 0xfe008c00)
+//Bit 25, rgb_sel, 1: antiflick RGBA, 0: antiflick YCbCrA
+//Bit 24, cbcr_en, 1: also filter cbcr in case of antiflicking YCbCrA, 0: no filter on cbcr in case of antiflicking YCbCrA
+//Bit 23:16, R mult coef for converting RGB to Y
+//Bit 15:8, G mult coef for converting RGB to Y
+//Bit 7:0, B mult coef for converting RGB to Y
+//Y = (R * y_r + G * y_g + B * y_b) / 256
+#define GE2D_ANTIFLICK_CTRL1 ((0x00d9 << 2) + 0xfe008c00)
+//Bit 31:24, Y threhold1, when 0<Y<=th1, use filter0;
+//Bit 23:16, color antiflick filter0 n3
+//Bit 15:8, color antiflick filter0 n2
+//Bit 7:0, color antiflick filter0 n1
+//Y = (line_up * n1 + line_center * n2 + line_dn * n3) / 128
+#define GE2D_ANTIFLICK_COLOR_FILT0 ((0x00da << 2) + 0xfe008c00)
+//Bit 31:24, Y threhold2, when th1<Y<=th2, use filter1;
+//Bit 23:16, color antiflick filter1 n3
+//Bit 15:8, color antiflick filter1 n2
+//Bit 7:0, color antiflick filter1 n1
+#define GE2D_ANTIFLICK_COLOR_FILT1 ((0x00db << 2) + 0xfe008c00)
+//Bit 31:24, Y threhold3, when th2<Y<=th3, use filter2; Y>th3, use filter3
+//Bit 23:16, color antiflick filter2 n3
+//Bit 15:8, color antiflick filter2 n2
+//Bit 7:0, color antiflick filter2 n1
+#define GE2D_ANTIFLICK_COLOR_FILT2 ((0x00dc << 2) + 0xfe008c00)
+//Bit 23:16, color antiflick filter3 n3
+//Bit 15:8, color antiflick filter3 n2
+//Bit 7:0, color antiflick filter3 n1
+#define GE2D_ANTIFLICK_COLOR_FILT3 ((0x00dd << 2) + 0xfe008c00)
+//Bit 31:24, Alpha threhold1, when 0<Alpha<=th1, use filter0;
+//Bit 23:16, Alpha antiflick filter0 n3
+//Bit 15:8, Alpha antiflick filter0 n2
+//Bit 7:0, Alpha antiflick filter0 n1
+//Alpha = (line_up * n1 + line_center * n2 + line_dn * n3) / 128
+#define GE2D_ANTIFLICK_ALPHA_FILT0 ((0x00de << 2) + 0xfe008c00)
+//Bit 31:24, Alpha threhold2, when th1<Alpha<=th2, use filter1;
+//Bit 23:16, Alpha antiflick filter1 n3
+//Bit 15:8, Alpha antiflick filter1 n2
+//Bit 7:0, Alpha antiflick filter1 n1
+#define GE2D_ANTIFLICK_ALPHA_FILT1 ((0x00df << 2) + 0xfe008c00)
+//Bit 31:24, Alpha threhold3, when th2<Alpha<=th3, use filter2; Alpha>th3, use filter3
+//Bit 23:16, Alpha antiflick filter2 n3
+//Bit 15:8, Alpha antiflick filter2 n2
+//Bit 7:0, Alpha antiflick filter2 n1
+#define GE2D_ANTIFLICK_ALPHA_FILT2 ((0x00e0 << 2) + 0xfe008c00)
+//Bit 23:16, Alpha antiflick filter3 n3
+//Bit 15:8, Alpha antiflick filter3 n2
+//Bit 7:0, Alpha antiflick filter3 n1
+#define GE2D_ANTIFLICK_ALPHA_FILT3 ((0x00e1 << 2) + 0xfe008c00)
+//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset)
+//Bit 30:22 din_offset (signed data)
+//Bit 21:14 map_coef (unsigned data)
+//Bit 13:10 map_sr (unsigned data)
+//Bit 9:1 dout_offset (signed data)
+//Bit 0 enable
+#define GE2D_SRC1_RANGE_MAP_Y_CTRL ((0x00e3 << 2) + 0xfe008c00)
+//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset)
+//Bit 30:22 din_offset (signed data)
+//Bit 21:14 map_coef (unsigned data)
+//Bit 13:10 map_sr (unsigned data)
+//Bit 9:1 dout_offset (signed data)
+//Bit 0 enable
+#define GE2D_SRC1_RANGE_MAP_CB_CTRL ((0x00e4 << 2) + 0xfe008c00)
+//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset)
+//Bit 30:22 din_offset (signed data)
+//Bit 21:14 map_coef (unsigned data)
+//Bit 13:10 map_sr (unsigned data)
+//Bit 9:1 dout_offset (signed data)
+//Bit 0 enable
+#define GE2D_SRC1_RANGE_MAP_CR_CTRL ((0x00e5 << 2) + 0xfe008c00)
+//Bit 21:16 src1 prearbitor burst number
+//Bit 13:8 src2 prearbitor burst number
+//Bit 5:0 dst prearbitor burst number
+#define GE2D_ARB_BURST_NUM ((0x00e6 << 2) + 0xfe008c00)
+//each 6bit ID, high 4bit are thread ID, low 2bits are the token
+//Bit 21:16 src1 ID
+//Bit 13:8 src2 ID
+//Bit 5:0 dst ID
+#define GE2D_TID_TOKEN ((0x00e7 << 2) + 0xfe008c00)
+//Bit 31:28 dst2_bytemask_val. 1-bit mask for each byte (8-bit). Applicable only if both dst_bitmask_en=1 and dst_bytemask_only=1.
+//Bit 27:26, dst2 picture struct, 00: frame, 10:top, 11: bottom
+//Bit 25:24, dst2 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 22:19 dst2 color_map
+// dst2_format=0 : output 8-bit;
+// dst2_format=1, dst2_color_map=1: output 16-bit YCbCr 655;
+// dst2_format=1, dst2_color_map=2: output 16-bit YCbCr 844;
+// dst2_format=1, dst2_color_map=3: output 16-bit YCbCrA 6442;
+// dst2_format=1, dst2_color_map=4: output 16-bit YCbCrA 4444;
+// dst2_format=1, dst2_color_map=5: output 16-bit YCbCr 565;
+// dst2_format=1, dst2_color_map=6: output 16-bit AYCbCr 4444;
+// dst2_format=1, dst2_color_map=7: output 16-bit AYCbCr 1555;
+// dst2_format=1, dst2_color_map=8: output 16-bit YCbCrA 4642;
+// dst2_format=1, dst2_color_map=9: output 16-bit CbCr 88;
+// dst2_format=1, dst2_color_map=10:output 16-bit CrCb 88;
+// dst2_format=2, dst2_color_map=0: output 24-bit YCbCr 888;
+// dst2_format=2, dst2_color_map=1: output 24-bit YCbCrA 5658;
+// dst2_format=2, dst2_color_map=2: output 24-bit AYCbCr 8565;
+// dst2_format=2, dst2_color_map=3: output 24-bit YCbCrA 6666;
+// dst2_format=2, dst2_color_map=4: output 24-bit AYCbCr 6666;
+// dst2_format=2, dst2_color_map=5: output 24-bit CrCbY 888;
+// dst2_format=3, dst2_color_map=0: output 32-bit YCbCrA 8888;
+// dst2_format=3, dst2_color_map=1: output 32-bit AYCbCr 8888;
+// dst2_format=3, dst2_color_map=2: output 32-bit ACrCbY 8888;
+// dst2_format=3, dst2_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 17:16 dst2_format, 00: 8bit, 01:16bit, 10:24bit, 11: 32bit
+//Bit 15 reserved
+//Bit 14 dst2_color_round_mode, 0: truncate, 1: + 0.5 rounding
+//Bit 13:12, dst2_x_discard_mode. 00: no discard; 10=discard even x; 11=discard odd x. Note: x is post reverse/rotation.
+//Bit 11:10, dst2_y_discard_mode. 00: no discard; 10=discard even y; 11=discard odd y. Note: y is post reverse/rotation.
+//Bit 9 reserved
+//Bit 8, dst2_enable. 0: disable dst2 (default); 1=enable dst2.
+//Bit 7: 6 reserved
+//Bit 5: 4, dst1_x_discard_mode. 00: no discard; 10=discard even x; 11=discard odd x. Note: x is post reverse/rotation.
+//Bit 3: 2, dst1_y_discard_mode. 00: no discard; 10=discard even y; 11=discard odd y. Note: y is post reverse/rotation.
+//Bit 1 reserved
+//Bit 0, dst1_enable. 0: disable dst1; 1=enable dst1 (default).
+#define GE2D_GEN_CTRL3 ((0x00e8 << 2) + 0xfe008c00)
+//Read only
+// Bit 13:0 ge2d_dst2_status, for debug only
+#define GE2D_STATUS2 ((0x00e9 << 2) + 0xfe008c00)
+//Bit 27:26 src1 Y fifo size control, 00: 512, 01: 256, 10: 128 11: 96
+//Bit 25:24 src2 fifo size control, 00: 512, 01: 256, 10: 128 11: 96
+//Bit 23:22 dst1 fifo size control, 00: 512, 01: 256, 10: 128 11: 64
+//Bit 21:20 dst2 fifo size control, 00: 512, 01: 256, 10: 128 11: 64
+//Bit 19:18, dst1 fifo burst control, 00: 24x64, 01: 32x64, 10: 48x64, 11:64x64
+//Bit 17:16, dst2 fifo burst control, 00: 24x64, 01: 32x64, 10: 48x64, 11:64x64
+//Bit 15:1, top_wrap_ctrl
+//bit 0, if true, disable bug fix about the dp_out_done/scale_out_done(test1823) hang issue when scaling down ratio is high.
+#define GE2D_GEN_CTRL4 ((0x00ea << 2) + 0xfe008c00)
+#define GE2D_GCLK_CTRL0 ((0x00ef << 2) + 0xfe008c00)
+#define GE2D_GCLK_CTRL1 ((0x00f0 << 2) + 0xfe008c00)
+#define GE2D_GEN_CTRL5 ((0x00f1 << 2) + 0xfe008c00)
+#define GE2D_DST1_BADDR_CTRL ((0x00f2 << 2) + 0xfe008c00)
+//Bit 31:0, dst1 base address in 64bits
+#define GE2D_DST1_STRIDE_CTRL ((0x00f3 << 2) + 0xfe008c00)
+//Bit 19:0, dst1 stride size in 64bits
+#define GE2D_DST2_BADDR_CTRL ((0x00f4 << 2) + 0xfe008c00)
+//Bit 31:0, dst1 base address in 64bits
+#define GE2D_DST2_STRIDE_CTRL ((0x00f5 << 2) + 0xfe008c00)
+//Bit 19:0, dst1 stride size in 64bits
+#define GE2D_SRC1_BADDR_CTRL_Y ((0x00f6 << 2) + 0xfe008c00)
+//Bit 31:0, src1 base address in 64bits
+#define GE2D_SRC1_STRIDE_CTRL_Y ((0x00f7 << 2) + 0xfe008c00)
+//Bit 19:0, src1 stride size in 64bits
+#define GE2D_SRC1_BADDR_CTRL_CB ((0x00f8 << 2) + 0xfe008c00)
+//Bit 31:0, src1 base address in 64bits
+#define GE2D_SRC1_STRIDE_CTRL_CB ((0x00f9 << 2) + 0xfe008c00)
+//Bit 19:0, src1 stride size in 64bits
+#define GE2D_SRC1_BADDR_CTRL_CR ((0x00fa << 2) + 0xfe008c00)
+//Bit 31:0, src1 base address in 64bits
+#define GE2D_SRC1_STRIDE_CTRL_CR ((0x00fb << 2) + 0xfe008c00)
+//Bit 19:0, src1 stride size in 64bits
+#define GE2D_SRC2_BADDR_CTRL ((0x00fc << 2) + 0xfe008c00)
+//Bit 31:0, src2 base address in 64bits
+#define GE2D_SRC2_STRIDE_CTRL ((0x00fd << 2) + 0xfe008c00)
+//Bit 19:0, src2 stride size in 64bits
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: ge2d_regs.h
+//
+//
+// Reading file: mipi_isp.h
+//
+//========================================================================
+// MIPI_ISP
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe023000
+// -----------------------------------------------
+#define MIPI_ADAPT_DDR_RD0_CNTL0 ((0x0000 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD0_CNTL1 ((0x0001 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD0_CNTL2 ((0x0002 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD0_CNTL3 ((0x0003 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD0_CNTL4 ((0x0004 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD0_ST0 ((0x0005 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD0_ST1 ((0x0006 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD0_ST2 ((0x0007 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD0_CNTL5 ((0x0008 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD0_CNTL6 ((0x0009 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_CNTL0 ((0x0010 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_CNTL1 ((0x0011 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_CNTL2 ((0x0012 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_CNTL3 ((0x0013 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_CNTL4 ((0x0014 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_ST0 ((0x0015 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_ST1 ((0x0016 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_ST2 ((0x0017 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_CNTL5 ((0x0018 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_CNTL6 ((0x0019 << 2) + 0xfe023000)
+#define MIPI_ADAPT_PIXEL0_CNTL0 ((0x0020 << 2) + 0xfe023000)
+#define MIPI_ADAPT_PIXEL0_CNTL1 ((0x0021 << 2) + 0xfe023000)
+#define MIPI_ADAPT_PIXEL1_CNTL0 ((0x0022 << 2) + 0xfe023000)
+#define MIPI_ADAPT_PIXEL1_CNTL1 ((0x0023 << 2) + 0xfe023000)
+#define MIPI_ADAPT_PIXEL0_ST0 ((0x002a << 2) + 0xfe023000)
+#define MIPI_ADAPT_PIXEL0_ST1 ((0x002b << 2) + 0xfe023000)
+#define MIPI_ADAPT_PIXEL1_ST0 ((0x002c << 2) + 0xfe023000)
+#define MIPI_ADAPT_PIXEL1_ST1 ((0x002d << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL0 ((0x0030 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL1 ((0x0031 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL2 ((0x0032 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL3 ((0x0033 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL4 ((0x0034 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL5 ((0x0035 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL6 ((0x0036 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL7 ((0x0037 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL8 ((0x0038 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL9 ((0x0039 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_ST0 ((0x003a << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_ST1 ((0x003b << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL10 ((0x003c << 2) + 0xfe023000)
+#define MIPI_OTHER_CNTL0 ((0x0040 << 2) + 0xfe023000)
+#define MIPI_OTHER_CNTL1 ((0x0041 << 2) + 0xfe023000)
+#define MIPI_OTHER_CNTL2 ((0x0042 << 2) + 0xfe023000)
+#define MIPI_OTHER_CNTL3 ((0x0043 << 2) + 0xfe023000)
+#define MIPI_OTHER_CNTL4 ((0x0044 << 2) + 0xfe023000)
+#define MIPI_OTHER_ST0 ((0x004a << 2) + 0xfe023000)
+#define MIPI_OTHER_ST1 ((0x004b << 2) + 0xfe023000)
+#define DDR_RD0_LBUF_STATUS ((0x0050 << 2) + 0xfe023000)
+#define DDR_RD1_LBUF_STATUS ((0x0051 << 2) + 0xfe023000)
+#define MIPI_ADAPT_IRQ_MASK0 ((0x0060 << 2) + 0xfe023000)
+#define MIPI_ADAPT_IRQ_PENDING0 ((0x0061 << 2) + 0xfe023000)
+#define MIPI_ADAPT_IRQ_MASK1 ((0x0062 << 2) + 0xfe023000)
+#define MIPI_ADAPT_IRQ_PENDING1 ((0x0063 << 2) + 0xfe023000)
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe023800
+// -----------------------------------------------
+#define MIPI_ISP_RDARB_MODE ((0x0000 << 2) + 0xfe023800)
+#define MIPI_ISP_RDARB_REQEN_SLV ((0x0001 << 2) + 0xfe023800)
+#define MIPI_ISP_RDARB_WEIGH0_SLV ((0x0002 << 2) + 0xfe023800)
+#define MIPI_ISP_RDARB_WEIGH1_SLV ((0x0003 << 2) + 0xfe023800)
+#define MIPI_ISP_RDARB_UGT ((0x0004 << 2) + 0xfe023800)
+#define MIPI_ISP_RDARB_LIMT0 ((0x0005 << 2) + 0xfe023800)
+#define MIPI_ISP_WRARB_MODE ((0x0006 << 2) + 0xfe023800)
+#define MIPI_ISP_WRARB_REQEN_SLV ((0x0007 << 2) + 0xfe023800)
+#define MIPI_ISP_WRARB_WEIGH0_SLV ((0x0008 << 2) + 0xfe023800)
+#define MIPI_ISP_WRARB_WEIGH1_SLV ((0x0009 << 2) + 0xfe023800)
+#define MIPI_ISP_WRARB_UGT ((0x000a << 2) + 0xfe023800)
+#define MIPI_ISP_RDWR_ARB_STATUS ((0x000b << 2) + 0xfe023800)
+#define MIPI_ISP_ARB_DBG_CTRL ((0x000c << 2) + 0xfe023800)
+#define MIPI_ISP_ARB_DBG_STAT ((0x000d << 2) + 0xfe023800)
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe023c00
+// -----------------------------------------------
+#define MIPI_BL_FR_PING_ADDR0_ST ((0x0000 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_PING_ADDR0_ED ((0x0001 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_PING_ADDR1_ST ((0x0002 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_PING_ADDR1_ED ((0x0003 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_PONG_ADDR0_ST ((0x0004 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_PONG_ADDR0_ED ((0x0005 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_PONG_ADDR1_ST ((0x0006 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_PONG_ADDR1_ED ((0x0007 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_FRAME_TH ((0x0008 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_FRAME_BUFFER_START_ADDR0 ((0x0009 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_FRAME_SIZE0 ((0x000a << 2) + 0xfe023c00)
+#define MIPI_BL_FR_FRAME_BUF_SIZE0 ((0x000b << 2) + 0xfe023c00)
+#define MIPI_BL_FR_FRAME_BUFFER_START_ADDR1 ((0x000c << 2) + 0xfe023c00)
+#define MIPI_BL_FR_FRAME_SIZE1 ((0x000d << 2) + 0xfe023c00)
+#define MIPI_BL_FR_FRAME_BUF_SIZE1 ((0x000e << 2) + 0xfe023c00)
+#define MIPI_BL_FR_CTRL0 ((0x000f << 2) + 0xfe023c00)
+#define MIPI_BL_FR_CTRL1 ((0x0010 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_FRAME_COUNT ((0x0011 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_AWADDR_O ((0x0012 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_AWADDR_I ((0x0013 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_STAT0 ((0x0014 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_STAT1 ((0x0015 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_STAT2 ((0x0016 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_STAT3 ((0x0017 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_FRAME_BUFFER_START_ADDR0P ((0x0018 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_PING_ADDR0_ST ((0x0020 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_PING_ADDR0_ED ((0x0021 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_PING_ADDR1_ST ((0x0022 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_PING_ADDR1_ED ((0x0023 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_PONG_ADDR0_ST ((0x0024 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_PONG_ADDR0_ED ((0x0025 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_PONG_ADDR1_ST ((0x0026 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_PONG_ADDR1_ED ((0x0027 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_FRAME_TH ((0x0028 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_FRAME_BUFFER_START_ADDR0 ((0x0029 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_FRAME_SIZE0 ((0x002a << 2) + 0xfe023c00)
+#define MIPI_BL_DS_FRAME_BUF_SIZE0 ((0x002b << 2) + 0xfe023c00)
+#define MIPI_BL_DS_FRAME_BUFFER_START_ADDR1 ((0x002c << 2) + 0xfe023c00)
+#define MIPI_BL_DS_FRAME_SIZE1 ((0x002d << 2) + 0xfe023c00)
+#define MIPI_BL_DS_FRAME_BUF_SIZE1 ((0x002e << 2) + 0xfe023c00)
+#define MIPI_BL_DS_CTRL0 ((0x002f << 2) + 0xfe023c00)
+#define MIPI_BL_DS_CTRL1 ((0x0030 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_FRAME_COUNT ((0x0031 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_AWADDR_O ((0x0032 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_AWADDR_I ((0x0033 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_STAT0 ((0x0034 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_STAT1 ((0x0035 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_STAT2 ((0x0036 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_STAT3 ((0x0037 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_FRAME_BUFFER_START_ADDR0P ((0x0038 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_PING_ADDR0_ST ((0x0040 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_PING_ADDR0_ED ((0x0041 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_PING_ADDR1_ST ((0x0042 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_PING_ADDR1_ED ((0x0043 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_PONG_ADDR0_ST ((0x0044 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_PONG_ADDR0_ED ((0x0045 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_PONG_ADDR1_ST ((0x0046 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_PONG_ADDR1_ED ((0x0047 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_FRAME_TH ((0x0048 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_FRAME_BUFFER_START_ADDR0 ((0x0049 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_FRAME_SIZE0 ((0x004a << 2) + 0xfe023c00)
+#define MIPI_BL_WF_FRAME_BUF_SIZE0 ((0x004b << 2) + 0xfe023c00)
+#define MIPI_BL_WF_FRAME_BUFFER_START_ADDR1 ((0x004c << 2) + 0xfe023c00)
+#define MIPI_BL_WF_FRAME_SIZE1 ((0x004d << 2) + 0xfe023c00)
+#define MIPI_BL_WF_FRAME_BUF_SIZE1 ((0x004e << 2) + 0xfe023c00)
+#define MIPI_BL_WF_CTRL0 ((0x004f << 2) + 0xfe023c00)
+#define MIPI_BL_WF_CTRL1 ((0x0050 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_FRAME_COUNT ((0x0051 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_AWADDR_O ((0x0052 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_AWADDR_I ((0x0053 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_STAT0 ((0x0054 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_STAT1 ((0x0055 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_STAT2 ((0x0056 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_STAT3 ((0x0057 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_FRAME_BUFFER_START_ADDR0P ((0x0058 << 2) + 0xfe023c00)
+//
+// Closing file: mipi_isp.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: ./REG_LIST_RTL.h
+//
+#include "soc_def.h"
+#endif // REGISTER_H
+
diff --git a/arch/arm/include/asm/arch-c1/regs.h b/arch/arm/include/asm/arch-c1/regs.h
new file mode 100644
index 0000000..b1aa2a0
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/regs.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AML_REG_H__
+#define __AML_REG_H__
+/*
+ * all used regs
+ */
+/*
+ * ISA_TIMERE use SYSCTRL_TIMERE
+ * WATCHDOG_CNTL use RESETCTRL_WATCHDOG_CTRL0
+ * WATCHDOG_TCNT use RESETCTRL_WATCHDOG_CNT
+ * WATCHDOG_RST use RESETCTRL_WATCHDOG_CLR
+ */
+#define ISA_TIMERE ((0x0041 << 2) + 0xfe005800)
+#define WATCHDOG_CNTL ((0x0040 << 2) + 0xfe000000)
+#define WATCHDOG_TCNT ((0x0042 << 2) + 0xfe000000)
+#define WATCHDOG_RST ((0x0043 << 2) + 0xfe000000)
+
+/*
+ * SEC_AO_SEC_GP_CFG0 use SYSCTRL_SEC_STATUS_REG4
+ * AO_SEC_GP_CFG0 use SYSCTRL_SEC_STATUS_REG4
+ * AO_RTI_STATUS_REG3 use SYSCTRL_SEC_STICKY_REG1
+ * AO_SEC_SD_CFG15 use SYSCTRL_SEC_STATUS_REG2
+ */
+#define AO_SEC_GP_CFG0 ((0x00c4 << 2) + 0xfe005800)
+#define AO_RTI_STATUS_REG3 ((0x00e1 << 2) + 0xfe005800)
+#define AO_SEC_SD_CFG15 ((0x00c2 << 2) + 0xfe005800)
+
+/* PREG_STICKY_REG8 use SYSCTRL_STICKY_REG7
+ * P_AO_SEC_GP_CFG12 use SYSCTRL_DEBUG_REG6
+ * P_AO_SEC_GP_CFG13 use SYSCTRL_DEBUG_REG7
+ */
+#define PREG_STICKY_REG8 ((0x00b7 << 2) + 0xfe005800)
+#define P_AO_SEC_GP_CFG12 (volatile uint32_t *)((0x0096 << 2) + 0xfe005800)
+#define P_AO_SEC_GP_CFG13 (volatile uint32_t *)((0x0097 << 2) + 0xfe005800)
+
+/*
+ * P_AO_RTI_PINMUX_REG0 use PADCTRL_PIN_MUX_REG0
+ * P_AO_TIMEBASE_CNTL1 use CLKTREE_TIMEBASE_CTRL1
+ * AO_UART_WFIFO use UART_B_WFIFO
+ */
+#define P_AO_RTI_PINMUX_REG0 ((0x0000 << 2) + 0xfe000400)
+#define P_AO_TIMEBASE_CNTL1 ((0x0016 << 2) + 0xfe000800)
+#define AO_UART_WFIFO ((0x0000 << 2) + 0xfe002000)
+
+/*
+ * Not AO watch dog
+ */
+#define P_WATCHDOG_CNTL (volatile uint32_t *)(WATCHDOG_CNTL)
+#define P_WATCHDOG_TCNT (volatile uint32_t *)(WATCHDOG_TCNT)
+#define P_WATCHDOG_RST (volatile uint32_t *)(WATCHDOG_RST)
+#define P_ISA_TIMERE (volatile uint32_t *)(ISA_TIMERE)
+
+#endif /* __AML_REG_H__ */
diff --git a/arch/arm/include/asm/arch-c1/romboot.h b/arch/arm/include/asm/arch-c1/romboot.h
new file mode 100644
index 0000000..2967fbb
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/romboot.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOOT_ROM_H_
+#define __BOOT_ROM_H_
+#ifndef __ASSEMBLY__
+//#include <stdint.h>
+//uint8_t simple_i2c(uint8_t adr);
+//void spi_pin_mux(void);
+//void spi_init(void);
+//uint32_t spi_read(uint32_t src, uint32_t mem, uint32_t size);
+//void udelay(uint32_t usec);
+//void boot_des_decrypt(uint8_t *ct, uint8_t *pt, uint32_t size);
+
+#endif /* ! __ASSEMBLY__ */
+#include "config.h"
+
+/* Magic number to "boot" up A53 */
+#define AO_SEC_SD_CFG10_CB 0x80000000
+
+/*BOOT device and ddr size*/
+/*31-28: boot device id, 27-24: boot device para, 23-20: reserved*/
+/*19-8: ddr size, 7-0: board revision*/
+//#define P_AO_SEC_GP_CFG0 0xDA100240 //defined in secure_apb.h
+#define AO_SEC_GP_CFG7_W0_BIT 8
+#define AO_SEC_GP_CFG7_W0 0x100
+
+#define BOOT_ID_RESERVED 0
+#define BOOT_ID_EMMC 1
+#define BOOT_ID_NAND 2
+#define BOOT_ID_SPI 3
+#define BOOT_ID_SDCARD 4
+#define BOOT_ID_USB 5
+
+#endif /* __BOOT_ROM_H_ */
diff --git a/arch/arm/include/asm/arch-c1/sd_emmc.h b/arch/arm/include/asm/arch-c1/sd_emmc.h
new file mode 100644
index 0000000..82d4fb2
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/sd_emmc.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __SD_EMMC_H__
+#define __SD_EMMC_H__
+
+#include <mmc.h>
+
+#define SDIO_PORT_A 0
+#define SDIO_PORT_B 1
+#define SDIO_PORT_C 2
+
+#define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */
+#define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */
+
+#define MESON_SD_EMMC_CLOCK 0x00
+#define CLK_MAX_DIV GENMASK(5, 0)
+#define CLK_MAX_SRC GENMASK(7, 6)
+#define Cfg_div 0
+#define Cfg_src 6
+#define Cfg_co_phase 8
+#define Cfg_tx_phase 10
+#define Cfg_rx_phase 12
+#define Cfg_sram_pd 14
+#define Cfg_tx_delay 16
+#define Cfg_rx_delay 22
+#define Cfg_always_on 28
+#define Cfg_irq_sdio_sleep 29
+#define Cfg_irq_sdio_sleep_ds 30
+
+#define MESON_SD_EMMC_DELAY1 0x4
+#define DLY_D0_MASK GENMASK(5, 0)
+#define DLY_D1_MASK GENMASK(11, 6)
+#define DLY_D2_MASK GENMASK(17, 12)
+#define DLY_D3_MASK GENMASK(23, 18)
+#define DLY_D4_MASK GENMASK(31, 24)
+#define Dly_d0 0
+#define Dly_d1 6
+#define Dly_d2 12
+#define Dly_d3 18
+#define Dly_d4 24
+
+#define MESON_SD_EMMC_DELAY2 0x8
+#define DLY_D5_MASK GENMASK(5, 0)
+#define DLY_D6_MASK GENMASK(11, 6)
+#define DLY_D7_MASK GENMASK(17, 12)
+#define DLY_D8_MASK GENMASK(23, 18)
+#define DLY_D9_MASK GENMASK(31, 24)
+#define Dly_d5 0
+#define Dly_d6 6
+#define Dly_d7 12
+#define Dly_d8 18
+#define Dly_d9 24
+
+#define MESON_SD_EMMC_ADJUST 0xC
+#define CALI_SEL_MASK GENMASK(11, 8)
+#define ADJ_DLY_MASK GENMASK(21, 16)
+#define Cfg_cali_sel 8
+#define Cfg_cali_en 12
+#define Cfg_adj_en 13
+#define Cfg_cali_rise 14
+#define Cfg_ds_en 15
+#define Cfg_adj_dly 16
+#define Cfg_adj_auto 22
+#define Cfg_adj_init 23
+
+#define MESON_SD_EMMC_START 0x40
+#define CFG_DESC_INIT BIT(0)
+#define CFG_DESC_BUSY BIT(1)
+#define CFG_DESC_ADDR 2
+
+#define MESON_SD_EMMC_CFG 0x44
+#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
+#define CFG_BUS_WIDTH_1 0
+#define CFG_BUS_WIDTH_4 1
+#define CFG_BUS_WIDTH_8 2
+#define CFG_DDR BIT(2)
+#define CFG_BL_LEN_MASK GENMASK(7, 4)
+#define CFG_BL_LEN_SHIFT 4
+#define CFG_BL_LEN_512 (9 << 4)
+#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
+#define CFG_RESP_TIMEOUT_256 (8 << 8)
+#define CFG_RC_CC_MASK GENMASK(15, 12)
+#define CFG_RC_CC_16 (4 << 12)
+#define CFG_SDCLK_ALWAYS_ON BIT(18)
+#define CFG_AUTO_CLK BIT(23)
+
+#define MESON_SD_EMMC_STATUS 0x48
+#define STATUS_MASK GENMASK(15, 0)
+#define STATUS_ERR_MASK GENMASK(12, 0)
+#define STATUS_RXD_ERR_MASK GENMASK(7, 0)
+#define STATUS_TXD_ERR BIT(8)
+#define STATUS_DESC_ERR BIT(9)
+#define STATUS_RESP_ERR BIT(10)
+#define STATUS_RESP_TIMEOUT BIT(11)
+#define STATUS_DESC_TIMEOUT BIT(12)
+#define STATUS_END_OF_CHAIN BIT(13)
+
+#define MESON_SD_EMMC_IRQ_EN 0x4c
+
+#define MESON_SD_EMMC_CMD_CFG 0x50
+#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
+#define CMD_CFG_BLOCK_MODE BIT(9)
+#define CMD_CFG_R1B BIT(10)
+#define CMD_CFG_END_OF_CHAIN BIT(11)
+#define CMD_CFG_TIMEOUT_4S (12 << 12)
+#define CMD_CFG_NO_RESP BIT(16)
+#define CMD_CFG_NO_CMD BIT(17)
+#define CMD_CFG_DATA_IO BIT(18)
+#define CMD_CFG_DATA_WR BIT(19)
+#define CMD_CFG_RESP_NOCRC BIT(20)
+#define CMD_CFG_RESP_128 BIT(21)
+#define CMD_CFG_RESP_NUM BIT(22)
+#define CMD_CFG_DATA_NUM BIT(23)
+#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
+#define CMD_CFG_CMD_INDEX_SHIFT 24
+#define CMD_CFG_ERR BIT(30)
+#define CMD_CFG_OWNER BIT(31)
+
+#define MESON_SD_EMMC_CMD_ARG 0x54
+#define MESON_SD_EMMC_CMD_DAT 0x58
+#define MESON_SD_EMMC_CMD_RSP 0x5c
+#define MESON_SD_EMMC_CMD_RSP1 0x60
+#define MESON_SD_EMMC_CMD_RSP2 0x64
+#define MESON_SD_EMMC_CMD_RSP3 0x68
+
+#define SD_EMMC_RXD_ERROR (1 << 0)
+#define SD_EMMC_TXD_ERROR (1 << 1)
+#define SD_EMMC_DESC_ERROR (1 << 2)
+#define SD_EMMC_RESP_CRC_ERROR (1 << 3)
+#define SD_EMMC_RESP_TIMEOUT_ERROR (1 << 4)
+#define SD_EMMC_DESC_TIMEOUT_ERROR (1 << 5)
+
+//boot from sd or emmc
+#define SEC_AO_SEC_GP_CFG0 (SYSCTRL_SEC_STATUS_REG4)
+#endif
diff --git a/arch/arm/include/asm/arch-c1/secure_apb.h b/arch/arm/include/asm/arch-c1/secure_apb.h
new file mode 100644
index 0000000..b3c0b34
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/secure_apb.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/regs.h>
+#include <asm/arch/register.h>
+
+#define DMA_BASE (uint32_t)(0xfe006000)
+
+#define DMA_T0 (uint32_t)(DMA_BASE + 0x00)
+#define DMA_T1 (uint32_t)(DMA_BASE + 0x04)
+#define DMA_T2 (uint32_t)(DMA_BASE + 0x08)
+#define DMA_T3 (uint32_t)(DMA_BASE + 0x0c)
+#define DMA_T4 (uint32_t)(DMA_BASE + 0x10)
+#define DMA_T5 (uint32_t)(DMA_BASE + 0x14)
+#define DMA_STS0 (uint32_t)(DMA_BASE + 0x20)
+#define DMA_STS1 (uint32_t)(DMA_BASE + 0x24)
+#define DMA_STS2 (uint32_t)(DMA_BASE + 0x28)
+#define DMA_STS3 (uint32_t)(DMA_BASE + 0x2c)
+#define DMA_STS4 (uint32_t)(DMA_BASE + 0x30)
+#define DMA_STS5 (uint32_t)(DMA_BASE + 0x34)
+#define DMA_CFG (uint32_t)(DMA_BASE + 0x40)
+#define DMA_SEC (uint32_t)(DMA_BASE + 0x44)
+#define DMA_END (uint32_t)(DMA_BASE + 0x3ff)
+
+#define P_DMA_T0 (volatile uint32_t *)(DMA_BASE + 0x00)
+#define P_DMA_T1 (volatile uint32_t *)(DMA_BASE + 0x04)
+#define P_DMA_T2 (volatile uint32_t *)(DMA_BASE + 0x08)
+#define P_DMA_T3 (volatile uint32_t *)(DMA_BASE + 0x0c)
+#define P_DMA_T4 (volatile uint32_t *)(DMA_BASE + 0x10)
+#define P_DMA_T5 (volatile uint32_t *)(DMA_BASE + 0x14)
+#define P_DMA_STS0 (volatile uint32_t *)(DMA_BASE + 0x20)
+#define P_DMA_STS1 (volatile uint32_t *)(DMA_BASE + 0x24)
+#define P_DMA_STS2 (volatile uint32_t *)(DMA_BASE + 0x28)
+#define P_DMA_STS3 (volatile uint32_t *)(DMA_BASE + 0x2c)
+#define P_DMA_STS4 (volatile uint32_t *)(DMA_BASE + 0x30)
+#define P_DMA_STS5 (volatile uint32_t *)(DMA_BASE + 0x34)
+#define P_DMA_CFG (volatile uint32_t *)(DMA_BASE + 0x40)
+#define P_DMA_SEC (volatile uint32_t *)(DMA_BASE + 0x44)
diff --git a/arch/arm/include/asm/arch-c1/soc_def.h b/arch/arm/include/asm/arch-c1/soc_def.h
new file mode 100644
index 0000000..e927661
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/soc_def.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __C1_DEF_H__
+#define __C1_DEF_H__
+
+#define SEC_AO_SEC_GP_CFG2 (SYSCTRL_SEC_STATUS_REG6)
+
+#endif /* __C1_DEF_H__ */
diff --git a/arch/arm/include/asm/arch-c1/timer.h b/arch/arm/include/asm/arch-c1/timer.h
new file mode 100644
index 0000000..492cc8d
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/timer.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __TIMER_H
+#define __TIMER_H
+
+#include <asm/arch/romboot.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/io.h>
+
+/**
+ * Get the current timestamp from the system timer.
+ */
+uint32_t get_time(void);
+
+/**
+ * Busy-wait.
+ *
+ * @param us Number of microseconds to delay.
+ */
+void _udelay(unsigned int us);
+
+#endif /* __TIMER_H */
diff --git a/arch/arm/include/asm/arch-c1/timing.h b/arch/arm/include/asm/arch-c1/timing.h
new file mode 100644
index 0000000..1c06587
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/timing.h
@@ -0,0 +1,413 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AML_TIMING_H_
+#define __AML_TIMING_H_
+
+#include <asm/arch/ddr_define.h>
+#include <asm/arch/types.h>
+#include <asm/arch/mnPmuSramMsgBlock_ddr3.h>
+#include <asm/arch/mnPmuSramMsgBlock_ddr4.h>
+#include <asm/arch/mnPmuSramMsgBlock_ddr4_2d.h>
+#include <asm/arch/mnPmuSramMsgBlock_lpddr3.h>
+#include <asm/arch/mnPmuSramMsgBlock_lpddr4.h>
+#include <asm/arch/mnPmuSramMsgBlock_lpddr4_2d.h>
+
+#define BL2_INIT_STAGE_0 0
+#define BL2_INIT_STAGE_1 1
+#define BL2_INIT_STAGE_2 2
+#define BL2_INIT_STAGE_3 3
+#define BL2_INIT_STAGE_4 4
+#define BL2_INIT_STAGE_5 5
+#define BL2_INIT_STAGE_6 6
+#define BL2_INIT_STAGE_7 7
+#define BL2_INIT_STAGE_8 8
+#define BL2_INIT_STAGE_9 9
+
+typedef struct bl2_reg {
+ unsigned int reg;
+ unsigned int value;
+ unsigned int mask;
+ unsigned short udelay;
+ unsigned char flag;
+ unsigned char rsv_0;
+}__attribute__ ((packed)) bl2_reg_t;
+
+typedef struct ddr_reg {
+ unsigned int reg;
+ unsigned int value;
+ unsigned int mask;
+ unsigned short udelay;
+ unsigned char flag;
+ unsigned char rsv_0;
+}__attribute__ ((packed)) ddr_reg_t;
+
+typedef struct training_delay_set_ps{
+ unsigned char ac_trace_delay[10];
+ unsigned char ac_trace_delay_rev[2];
+ unsigned char read_dqs_delay[16];
+ unsigned char read_dq_bit_delay[72];
+ unsigned short write_dqs_delay[16];
+// */
+ unsigned short write_dq_bit_delay[72];
+ unsigned short read_dqs_gate_delay[16];
+ unsigned char soc_bit_vref[36];
+ unsigned char dram_bit_vref[32];
+ ///*
+ unsigned char rever1;//read_dqs read_dq,write_dqs, write_dq
+ unsigned char dfi_mrl;
+ unsigned char dfi_hwtmrl;
+ unsigned char ARdPtrInitVal;
+ unsigned short csr_vrefinglobal;
+ unsigned short csr_dqsrcvcntrl[4];
+ unsigned short csr_pptdqscntinvtrntg0[4];
+ unsigned short csr_pptdqscntinvtrntg1[4];
+ unsigned short csr_seq0bgpr[9];
+ unsigned short csr_dllgainctl;
+ unsigned short csr_dlllockpara;
+// unsigned short rever2;
+}__attribute__ ((packed)) training_delay_set_ps_t;
+
+typedef struct ddr_mrs_reg {
+ unsigned int cfg_ddr_mr[8];
+ unsigned int cfg_ddr_mr11;
+ unsigned int cfg_ddr_mr12;
+ unsigned int cfg_ddr_mr13;
+ unsigned int cfg_ddr_mr14;
+ unsigned int cfg_ddr_mr16;
+ unsigned int cfg_ddr_mr17;
+ unsigned int cfg_ddr_mr22;
+ unsigned int cfg_ddr_mr24;
+}__attribute__ ((packed)) ddr_mrs_reg_t;
+
+typedef struct ddr_timing{
+ unsigned int identifier;
+ unsigned int cfg_ddr_mrd;
+ unsigned int cfg_ddr_rfcab;
+ unsigned int cfg_ddr_rfcpb;
+ unsigned int cfg_ddr_rpab;
+ unsigned int cfg_ddr_rppb;
+ unsigned int cfg_ddr_rtw;
+ unsigned int cfg_ddr_rl;
+ unsigned int cfg_ddr_wl;
+ unsigned int cfg_ddr_ras;
+ unsigned int cfg_ddr_rc;
+ unsigned int cfg_ddr_rcd;
+ unsigned int cfg_ddr_rrds;
+ unsigned int cfg_ddr_rrdl;
+ unsigned int cfg_ddr_faw;
+ unsigned int cfg_ddr_rtp;
+ unsigned int cfg_ddr_wr;
+ unsigned int cfg_ddr_wtrs;
+ unsigned int cfg_ddr_wtrl;
+ unsigned int cfg_ddr_ccds;
+ unsigned int cfg_ddr_ccdl;
+ unsigned int cfg_ddr_exsr;
+ unsigned int cfg_ddr_xs;
+ unsigned int cfg_ddr_xp;
+ unsigned int cfg_ddr_xpdll;
+ unsigned int cfg_ddr_zqcs;
+ unsigned int cfg_ddr_cksre;
+ unsigned int cfg_ddr_cksrx;
+ unsigned int cfg_ddr_cke;
+ unsigned int cfg_ddr_mod;
+ unsigned int cfg_ddr_dqs;
+ unsigned int cfg_ddr_rstl;
+ unsigned int cfg_ddr_zqlat;
+ unsigned int cfg_ddr_mrr;
+ unsigned int cfg_ddr_ckesr;
+ unsigned int cfg_ddr_dpd;
+ unsigned int cfg_ddr_ckeck;
+ unsigned int cfg_ddr_refi;
+ unsigned int cfg_ddr_sr;
+ unsigned int cfg_ddr_ccdmw;
+ unsigned int cfg_ddr_escke;
+ unsigned int cfg_ddr_refi_ddr3;
+ unsigned int cfg_ddr_dfictrldelay;
+ unsigned int cfg_ddr_dfiphywrdata;
+ unsigned int cfg_ddr_dfiphywrlat;
+ unsigned int cfg_ddr_dfiphyrddataen;
+ unsigned int cfg_ddr_dfiphyrdlat;
+ unsigned int cfg_ddr_dfictrlupdmin;
+ unsigned int cfg_ddr_dfictrlupdmax;
+ unsigned int cfg_ddr_dfimstrresp;
+ unsigned int cfg_ddr_dfirefmski;
+ unsigned int cfg_ddr_dfictrlupdi;
+ unsigned int cfg_ddr_dfidramclk;
+ unsigned int cfg_ddr_dfilpresp;
+ unsigned int cfg_ddr_dfiphymstr;
+ unsigned int cfg_ddr_rtodt;
+ unsigned int cfg_ddr_wlmrd;
+ unsigned int cfg_ddr_wlo;
+ unsigned int cfg_ddr_al;
+ unsigned int cfg_ddr_zqcl;
+ unsigned int cfg_ddr_zqcsi;
+ unsigned int cfg_ddr_zqreset;
+ unsigned int cfg_ddr_tdqsck_min;
+ unsigned int cfg_ddr_tdqsck_max;
+ //training_delay_set_ps_t cfg_ddr_training_delay_ps;
+ ddr_mrs_reg_t cfg_ddr_mrs_reg_ps[2];
+ unsigned int dfi_odt1_config_ps[2];
+ //ddr_mrs_reg_t cfg_ddr_mrs_reg_ps1;
+ #if 0
+ unsigned int cfg_ddr_mr[8];
+ unsigned int cfg_ddr_mr11;
+ unsigned int cfg_ddr_mr12;
+ unsigned int cfg_ddr_mr13;
+ unsigned int cfg_ddr_mr14;
+ unsigned int cfg_ddr_mr16;
+ unsigned int cfg_ddr_mr17;
+ unsigned int cfg_ddr_mr22;
+ unsigned int cfg_ddr_mr24;
+ unsigned int cfg_ddr_reserve[5];
+ #endif
+}__attribute__ ((packed)) ddr_timing_t;
+
+typedef struct ddr_phy_common_extra_set{
+ unsigned short csr_pllctrl3;
+ unsigned short csr_pptctlstatic[4];
+ unsigned short csr_trainingincdecdtsmen[4];
+ unsigned short csr_tsmbyte0[4];
+ unsigned short csr_hwtcamode;
+ unsigned short csr_hwtlpcsena;
+ unsigned short csr_hwtlpcsenb;
+ unsigned short csr_acsmctrl13;
+ unsigned short csr_acsmctrl23;
+ unsigned char csr_soc_vref_dac1_dfe[36];
+}__attribute__ ((packed)) ddr_phy_common_extra_set_t;
+
+typedef struct retraining_set{
+ ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t;
+ training_delay_set_ps_t cfg_ddr_training_delay_ps;
+}__attribute__ ((packed)) retraining_set_t;
+
+typedef struct ddr_set{
+ unsigned int magic;
+ unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test
+ //unsigned int rsv_int0;
+ unsigned int ddr_func;
+ unsigned char board_id;
+ //board id reserve,,do not modify
+ unsigned char version;
+ // firmware reserve version,,do not modify
+ unsigned char DramType;
+ //support DramType should confirm with amlogic
+ //#define CONFIG_DDR_TYPE_DDR3 0
+ //#define CONFIG_DDR_TYPE_DDR4 1
+ //#define CONFIG_DDR_TYPE_LPDDR4 2
+ //#define CONFIG_DDR_TYPE_LPDDR3 3
+ //#define CONFIG_DDR_TYPE_LPDDR2 4
+ unsigned char DisabledDbyte;
+ //use for dram bus 16bit or 32bit,if use 16bit mode ,should disable bit 2,3
+ //bit 0 ---use byte 0 ,1 disable byte 0,
+ //bit 1 ---use byte 1 ,1 disable byte 1,
+ //bit 2 ---use byte 2 ,1 disable byte 2,
+ //bit 3 ---use byte 3 ,1 disable byte 3,
+ unsigned char Is2Ttiming;
+ //ddr3/ddr3 use 2t timing,now only support 2t timming
+ unsigned char HdtCtrl;
+ //training information control,do not modify
+ unsigned char dram_rank_config;
+ //support Dram connection type should confirm with amlogic
+ //#define CONFIG_DDR0_16BIT_CH0 0x1 //dram total bus width 16bit only use cs0
+ //#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 //dram total bus width 16bit use cs0 cs1
+ //#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 //dram total bus width 32bit use cs0
+ //#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 //only for lpddr4,dram total bus width 32bit use chanel a cs0 cs1 chanel b cs0 cs1
+ //#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 //dram total bus width 32bit only use cs0,but high address use 16bit mode
+ //#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 //dram total bus width 32bit use cs0 cs1,but cs1 use 16bit mode ,current phy not support reserve
+ //#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7 //dram total bus width 32bit use cs0 cs1
+ //#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8 //only for lpddr4,dram total bus width 32bit use chanel a cs0 chanel b cs0
+
+ /* rsv_char0. update for diagnose type define */
+ unsigned char diagnose;
+
+ unsigned short soc_data_drv_ohm_ps1;
+ unsigned short dram_data_drv_ohm_ps1;
+ unsigned short soc_data_odt_ohm_ps1;
+ unsigned short dram_data_odt_ohm_ps1;
+ unsigned short dram_data_wr_odt_ohm_ps1;
+ #if 0
+ /* imem/dmem define */
+ unsigned int imem_load_addr;
+ //system reserve,do not modify
+ unsigned int dmem_load_addr;
+ //system reserve,do not modify
+ unsigned short imem_load_size;
+ #endif
+ //system reserve,do not modify
+ unsigned short dmem_load_size;
+ //system reserve,do not modify
+ unsigned int ddr_base_addr;
+ //system reserve,do not modify
+ unsigned int ddr_start_offset;
+ //system reserve,do not modify
+
+ unsigned short dram_cs0_size_MB;
+ //config cs0 dram size ,like 1G DRAM ,setting 1024
+ unsigned short dram_cs1_size_MB;
+ //config cs1 dram size,like 512M DRAM ,setting 512
+ /* align8 */
+
+ unsigned short training_SequenceCtrl[2];
+ //system reserve,do not modify
+ unsigned char phy_odt_config_rank[2];
+ //unsigned char rever1;
+ //unsigned char rever2;
+ unsigned short rank1_ca_vref_permil;
+ //training odt config ,only use for training
+ // [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ // [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ unsigned int dfi_odt_config;
+ //normal go status od config,use for normal status
+ //bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity.
+ //bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1.
+ //bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0.
+ //bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1.
+ //bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0.
+ //bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity.
+ //bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0.
+ //bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1.
+ //bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0.
+ //bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1.
+ unsigned short DRAMFreq[4];
+ //config dram frequency,use DRAMFreq[0],ohter reserve
+ unsigned char PllBypassEn;
+ //system reserve,do not modify
+ unsigned char ddr_rdbi_wr_enable;
+ //system reserve,do not modify
+ unsigned char ddr_rfc_type;
+ //config dram rfc type,according dram type,also can use same dram type max config
+ //#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+ //#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+ //#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+ //#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+ //#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+ //#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+ //#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+ //#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+ //#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+ //#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+ //#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+ //#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+ unsigned char enable_lpddr4x_mode;
+ //system reserve,do not modify
+ /* align8 */
+
+ unsigned int pll_ssc_mode;
+ //
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ unsigned short clk_drv_ohm;
+ //config soc clk pin signal driver stength ,select 20,30,40,60ohm
+ unsigned short cs_drv_ohm;
+ //config soc cs0 cs1 pin signal driver stength ,select 20,30,40,60ohm
+ unsigned short ac_drv_ohm;
+ //config soc normal address command pin driver stength ,select 20,30,40,60ohm
+ unsigned short soc_data_drv_ohm_p;
+ //config soc data pin pull up driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short soc_data_drv_ohm_n;
+ //config soc data pin pull down driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short soc_data_odt_ohm_p;
+ //config soc data pin odt pull up stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short soc_data_odt_ohm_n;
+ //config soc data pin odt pull down stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short dram_data_drv_ohm;
+ //config dram data pin pull up pull down driver stength,ddr3 select 34,40ohm,ddr4 select 34,48ohm,lpddr4 select 40,48,60,80,120,240ohm
+ unsigned short dram_data_odt_ohm;
+ //config dram data pin odt pull up down stength,ddr3 select 40,60,120ohm,ddr4 select 34,40,48,60,120,240ohm,lpddr4 select 40,48,60,80,120,240ohm
+ unsigned short dram_ac_odt_ohm;
+ //config dram ac pin odt pull up down stength,use for lpddr4, select 40,48,60,80,120,240ohm
+ unsigned short soc_clk_slew_rate;
+ //system reserve,do not modify
+ unsigned short soc_cs_slew_rate;
+ //system reserve,do not modify
+ unsigned short soc_ac_slew_rate;
+ //system reserve,do not modify
+ unsigned short soc_data_slew_rate;
+ //system reserve,do not modify
+ unsigned short vref_output_permil; //phy
+ //setting same with vref_dram_permil
+ unsigned short vref_receiver_permil; //soc
+ //soc init SOC receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
+ unsigned short vref_dram_permil;
+ //soc init DRAM receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
+ unsigned short max_core_timmming_frequency;
+ //use for limited ddr speed core timmming parameter,for some old dram maybe have no over speed register
+ /* align8 */
+
+ unsigned char ac_trace_delay[10];
+ unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting;
+ //use for lpddr4 read vout voltage setting 0 --->2/5VDDQ ,1--->1/3VDDQ
+ unsigned char lpddr4_x8_mode;
+ unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function
+ //[1],slt test parameter ,use for force delay line offset
+ //system reserve,do not modify
+ unsigned short tdqs2dq;
+ unsigned char dram_data_wr_odt_ohm;
+ unsigned char bitTimeControl_2d;
+ //system reserve,do not modify
+ /* align8 */
+ unsigned char char_rev1;
+ unsigned char training_offset;//char_rev2;
+ unsigned int ddr_dmc_remap[5];
+ unsigned int dram_rtt_nom_wr_park[2];
+ //system reserve,do not modify
+ /* align8 */
+ unsigned char ddr_lpddr34_ca_remap[4];
+ ////use for lpddr3 /lpddr4 ca training data byte lane remap
+ unsigned char ddr_lpddr34_dq_remap[32];
+ ////use for lpddr3 /lpddr4 ca pinmux remap
+ unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL];
+ //use for lpddr3 /lpddr4 ca pinmux remap
+ unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL];
+ unsigned char char_rev3;
+ unsigned char char_rev4;
+ ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t;
+ training_delay_set_ps_t cfg_ddr_training_delay_ps[2];
+
+ //override read bit delay
+}__attribute__ ((packed)) ddr_set_t;
+
+typedef struct pll_set{
+ unsigned short cpu_clk;
+ unsigned short pxp;
+ unsigned int spi_ctrl;
+ unsigned short vddee;
+ unsigned short vcck;
+ unsigned char szPad[4];
+
+ unsigned long lCustomerID;
+ unsigned char debug_mode;
+ unsigned char log_chl;
+ unsigned char log_ctrl;
+ unsigned char ddr_timming_save_mode;
+ unsigned int nCFGTAddr;
+ /* align 8Byte */
+
+ unsigned int sys_pll_cntl[8];
+ unsigned int ddr_pll_cntl[8];
+ unsigned int fix_pll_cntl[8];
+}__attribute__ ((packed)) pll_set_t;
+
+typedef struct dmem_cfg {
+ PMU_SMB_DDR3U_1D_t ddr3u;
+ PMU_SMB_DDR4U_1D_t ddr4u;
+ PMU_SMB_DDR4U_2D_t ddr4u_2d;
+ PMU_SMB_LPDDR3_1D_t lpddr3u;
+ PMU_SMB_LPDDR4_1D_t lpddr4u;
+ PMU_SMB_LPDDR4_2D_t lpddr4u_2d;
+} dmem_cfg_t;
+
+#endif //__AML_TIMING_H_
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-c1/tsensor.h b/arch/arm/include/asm/arch-c1/tsensor.h
new file mode 100644
index 0000000..8b365a4
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/tsensor.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __TSENSOR_H__
+#define __TSENSOR_H__
+
+
+struct tsensor_cali_data {
+ unsigned int cmd; /* R/W */
+ unsigned int offset;
+ unsigned int size;
+ unsigned long buffer_phy;
+ unsigned long retcnt_phy;
+};
+
+
+#define CONFIG_HIGH_TEMP_COOL 90
+
+#define T_AVG_NUM 16 /*read temp cnt*/
+#define T_VER_MASK 0x80
+#define T_VALUE_MIN 0x1500
+#define T_VALUE_MAX 0x3500
+#define T_DLY_TIME 4500 /*update sensor register need 4.2ms*/
+
+#define T_CONTROL_DATA 0x62b
+#define T_TSCLK_DATA 0x130
+
+#define ts_b 3159
+#define ts_a 9411
+#define ts_m 424
+#define ts_n 324
+
+#ifdef CONFIG_AML_TSENSOR
+int temp_read_entry(void);
+int temp_trim_entry(int tempbase, int tempver);
+int temp_cooling_entry(void);
+#else
+int temp_read_entry(void)
+{
+ return -1;
+}
+int temp_trim_entry(int tempbase, int tempver)
+{
+ return -1;
+}
+int temp_cooling_entry(void)
+{
+ return 0;
+}
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-c1/types.h b/arch/arm/include/asm/arch-c1/types.h
new file mode 100644
index 0000000..2d362b1
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/types.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __TYPES_H
+#define __TYPES_H
+
+#ifndef _INT8_T_DECLARED
+typedef char int8_t;
+#define _INT8_T_DECLARED
+#endif
+
+#ifndef _INT16_T_DECLARED
+typedef short int16_t;
+#define _INT16_T_DECLARED
+#endif
+
+#ifndef _INT32_T_DECLARED
+typedef int int32_t;
+#define _INT32_T_DECLARED
+#endif
+
+#ifndef _INT64_T_DECLARED
+typedef long int64_t;
+#define _INT64_T_DECLARED
+#endif
+
+#ifndef _UINT8_T_DECLARED
+typedef unsigned char uint8_t;
+#define _UINT8_T_DECLARED
+#endif
+
+#ifndef _UINT16_T_DECLARED
+typedef unsigned short uint16_t;
+#define _UINT16_T_DECLARED
+#endif
+
+#ifndef _UINT32_T_DECLARED
+typedef unsigned int uint32_t;
+#define _UINT32_T_DECLARED
+#endif
+
+#ifndef _UINT64_T_DECLARED
+typedef unsigned long uint64_t;
+#define _UINT64_T_DECLARED
+#endif
+
+#ifndef _INT8PTR_T_DECLARED
+typedef char * int8ptr_t;
+#define _INT8PTR_T_DECLARED
+#endif
+
+#ifndef _INT16PTR_T_DECLARED
+typedef short * int16ptr_t;
+#define _INT16PTR_T_DECLARED
+#endif
+
+#ifndef _INT32PTR_T_DECLARED
+typedef int * int32ptr_t;
+#define _INT32PTR_T_DECLARED
+#endif
+
+#ifndef _INT64PTR_T_DECLARED
+typedef long * int64ptr_t;
+#define _INT64PTR_T_DECLARED
+#endif
+
+#ifndef _UINT8PTR_T_DECLARED
+typedef unsigned char * uint8ptr_t;
+#define _UINT8PTR_T_DECLARED
+#endif
+
+#ifndef _UINT16PTR_T_DECLARED
+typedef unsigned short * uint16ptr_t;
+#define _UINT16PTR_T_DECLARED
+#endif
+
+#ifndef _UINT32PTR_T_DECLARED
+typedef unsigned int * uint32ptr_t;
+#define _UINT32PTR_T_DECLARED
+#endif
+
+#ifndef _UINT64PTR_T_DECLARED
+typedef unsigned long * uint64ptr_t;
+#define _UINT64PTR_T_DECLARED
+#endif
+
+#endif
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-c1/uart.h b/arch/arm/include/asm/arch-c1/uart.h
new file mode 100644
index 0000000..757dc91
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/uart.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __MESON_FIRM_UART_H_
+#define __MESON_FIRM_UART_H_
+#include <config.h>
+#include <common.h>
+#include "register.h"
+//#include "io.h"
+#include <asm/arch/secure_apb.h>
+
+#ifndef CONFIG_CONS_INDEX
+#error Please define CONFIG_CONS_INDEX==[0|1]
+#endif
+
+#if CONFIG_CONS_INDEX==0
+#define UART_PORT_CONS UART_PORT_0
+#elif CONFIG_CONS_INDEX==1
+#define UART_PORT_CONS UART_PORT_1
+#elif CONFIG_CONS_INDEX==2
+#define UART_PORT_CONS UART_PORT_AO
+#define USE_AO_UART 1
+#else
+#error Please define CONFIG_CONS_INDEX==[0|1]
+#endif
+/*
+#define UART_PORT_0 CBUS_REG_ADDR(UART0_WFIFO)
+#define UART_PORT_1 CBUS_REG_ADDR(UART1_WFIFO)
+#define UART_PORT_2 CBUS_REG_ADDR(UART2_WFIFO)
+#define UART_PORT_AO P_AO_UART_WFIFO
+
+#define UART_WFIFO (0<<2)
+#define UART_RFIFO (1<<2)
+#define UART_CONTROL (2<<2)
+#define UART_STATUS (3<<2)
+#define UART_MISC (4<<2)
+*/
+
+#include "clock.h"
+
+#define UART_CLK_SRC CLK81
+#define UART_PORT_0 0xfe001c00
+#define UART_PORT_1 0xfe001c00
+#define UART_PORT_AO 0xfe001c00
+#define UART_WFIFO 0
+#define UART_RFIFO 1
+#define UART_CONTROL 2
+#define UART_STATUS 3
+#define UART_MISC 4
+
+#if USE_AO_UART == 1
+#define P_UART(uart_base,reg) (uart_base + (reg<<2))
+#else
+#define P_UART(uart_base,reg) CBUS_REG_ADDR(uart_base+reg)
+#endif
+#define P_UART_WFIFO(uart_base) P_UART(uart_base,UART_WFIFO)
+#define P_UART_RFIFO(uart_base) P_UART(uart_base,UART_RFIFO)
+
+#define P_UART_CONTROL(uart_base) P_UART(uart_base,UART_CONTROL)
+ #define UART_CNTL_MASK_BAUD_RATE (0xfff)
+ #define UART_CNTL_MASK_TX_EN (1<<12)
+ #define UART_CNTL_MASK_RX_EN (1<<13)
+ #define UART_CNTL_MASK_2WIRE (1<<15)
+ #define UART_CNTL_MASK_STP_BITS (3<<16)
+ #define UART_CNTL_MASK_STP_1BIT (0<<16)
+ #define UART_CNTL_MASK_STP_2BIT (1<<16)
+ #define UART_CNTL_MASK_PRTY_EVEN (0<<18)
+ #define UART_CNTL_MASK_PRTY_ODD (1<<18)
+ #define UART_CNTL_MASK_PRTY_TYPE (1<<18)
+ #define UART_CNTL_MASK_PRTY_EN (1<<19)
+ #define UART_CNTL_MASK_CHAR_LEN (3<<20)
+ #define UART_CNTL_MASK_CHAR_8BIT (0<<20)
+ #define UART_CNTL_MASK_CHAR_7BIT (1<<20)
+ #define UART_CNTL_MASK_CHAR_6BIT (2<<20)
+ #define UART_CNTL_MASK_CHAR_5BIT (3<<20)
+ #define UART_CNTL_MASK_RST_TX (1<<22)
+ #define UART_CNTL_MASK_RST_RX (1<<23)
+ #define UART_CNTL_MASK_CLR_ERR (1<<24)
+ #define UART_CNTL_MASK_INV_RX (1<<25)
+ #define UART_CNTL_MASK_INV_TX (1<<26)
+ #define UART_CNTL_MASK_RINT_EN (1<<27)
+ #define UART_CNTL_MASK_TINT_EN (1<<28)
+ #define UART_CNTL_MASK_INV_CTS (1<<29)
+ #define UART_CNTL_MASK_MASK_ERR (1<<30)
+ #define UART_CNTL_MASK_INV_RTS (1<<31)
+#define P_UART_STATUS(uart_base) P_UART(uart_base,UART_STATUS )
+ #define UART_STAT_MASK_RFIFO_CNT (0x7f<<0)
+ #define UART_STAT_MASK_TFIFO_CNT (0x7f<<8)
+ #define UART_STAT_MASK_PRTY_ERR (1<<16)
+ #define UART_STAT_MASK_FRAM_ERR (1<<17)
+ #define UART_STAT_MASK_WFULL_ERR (1<<18)
+ #define UART_STAT_MASK_RFIFO_FULL (1<<19)
+ #define UART_STAT_MASK_RFIFO_EMPTY (1<<20)
+ #define UART_STAT_MASK_TFIFO_FULL (1<<21)
+ #define UART_STAT_MASK_TFIFO_EMPTY (1<<22)
+ #define UART_STAT_MASK_XMIT_BUSY (1<<25)
+ #define UART_STAT_MASK_RECV_BUSY (1<<26)
+#define P_UART_MISC(uart_base) P_UART(uart_base,UART_MISC )
+
+
+#ifndef CONFIG_SERIAL_STP_BITS
+#define CONFIG_SERIAL_STP_BITS 1 // 1 , 2
+#endif
+#if CONFIG_SERIAL_STP_BITS==1
+#define UART_STP_BIT UART_CNTL_MASK_STP_1BIT
+#elif CONFIG_SERIAL_STP_BITS==2
+#define UART_STP_BIT UART_CNTL_MASK_STP_2BIT
+#else
+#error CONFIG_SERIAL_STP_BITS wrong
+#endif
+
+
+#ifndef CONFIG_SERIAL_PRTY_TYPE
+#define CONFIG_SERIAL_PRTY_TYPE 0 //0 ,2 ,3
+#endif
+#if CONFIG_SERIAL_PRTY_TYPE==0
+#define UART_PRTY_BIT 0
+#elif CONFIG_SERIAL_PRTY_TYPE==2
+#define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_EVEN)
+#elif CONFIG_SERIAL_PRTY_TYPE==3
+#define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_ODD)
+#else
+#error CONFIG_SERIAL_PRTY_TYPE wrong
+#endif
+
+#ifndef CONFIG_SERIAL_CHAR_LEN
+#define CONFIG_SERIAL_CHAR_LEN 8 //5,6,7,8
+#endif
+#if CONFIG_SERIAL_CHAR_LEN==5
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_5BIT
+#elif CONFIG_SERIAL_CHAR_LEN==6
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_6BIT
+#elif CONFIG_SERIAL_CHAR_LEN==7
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_7BIT
+#elif CONFIG_SERIAL_CHAR_LEN==8
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_8BIT
+#else
+#error CONFIG_SERIAL_CHAR_LEN wrong
+#endif
+#define UART_CONTROL_SET(baud,clk81) \
+ (((clk81)/(baud*4) -1) \
+ | UART_STP_BIT \
+ | UART_PRTY_BIT \
+ | UART_CHAR_LEN \
+ | UART_CNTL_MASK_TX_EN \
+ | UART_CNTL_MASK_RX_EN \
+ | UART_CNTL_MASK_RST_TX \
+ | UART_CNTL_MASK_RST_RX \
+ | UART_CNTL_MASK_CLR_ERR )
+#endif
diff --git a/arch/arm/include/asm/arch-c1/usb.h b/arch/arm/include/asm/arch-c1/usb.h
new file mode 100644
index 0000000..0efea92
--- /dev/null
+++ b/arch/arm/include/asm/arch-c1/usb.h
@@ -0,0 +1,247 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __ARCH_ARM_MESON_USB_H_U_BOOT__
+#define __ARCH_ARM_MESON_USB_H_U_BOOT__
+
+#include <common.h>
+#include <asm/types.h>
+#include <asm/arch/io.h>
+#include <asm/arch/secure_apb.h>
+#include <generic-phy.h>
+#include <asm-generic/gpio.h>
+
+#define USB_PHY_PORT_MAX 1
+/* Phy register MACRO definitions */
+
+#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
+#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
+#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27)
+
+#define PHYUTMI_OTGDISABLE (1 << 6)
+#define PHYUTMI_FORCESUSPEND (1 << 1)
+#define PHYUTMI_FORCESLEEP (1 << 0)
+
+#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
+#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
+
+#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
+#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
+
+#define PHYCLKRST_SSC_EN (0x1 << 20)
+#define PHYCLKRST_REF_SSP_EN (0x1 << 19)
+#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18)
+
+#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
+
+#define PHYCLKRST_FSEL_MASK (0x3f << 5)
+#define PHYCLKRST_FSEL(_x) ((_x) << 5)
+#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
+#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
+#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
+#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
+
+#define PHYCLKRST_RETENABLEN (0x1 << 4)
+
+#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
+#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
+#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
+
+#define PHYCLKRST_PORTRESET (0x1 << 1)
+#define PHYCLKRST_COMMONONN (0x1 << 0)
+
+#define PHYPARAM0_REF_USE_PAD (0x1 << 31)
+#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
+#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
+
+#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
+#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
+
+#define PHYTEST_POWERDOWN_SSP (0x1 << 3)
+#define PHYTEST_POWERDOWN_HSP (0x1 << 2)
+
+#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2)
+
+#define FSEL_CLKSEL_24M (0x5)
+
+#define USB_PHY2_ENABLE 0x10000000
+#define USB_PHY2_RESET 0x20000000
+
+/* XHCI PHY register structure */
+#define PHY_REGISTER_SIZE 0x20
+
+struct phy_aml_usb2_priv {
+ unsigned int base_addr;
+ unsigned int reset_addr;
+ unsigned int dwc2_a_addr;
+ unsigned int u2_port_num;
+ unsigned int usbphy_reset_bit[8];
+ unsigned int clktree_usb_bus_ctrl_addr;
+ unsigned int usb_phy2_pll_base_addr[4];
+};
+
+struct phy_aml_usb3_priv {
+ unsigned int base_addr;
+ unsigned int usb3_port_num;
+ struct gpio_desc desc;
+};
+
+/* Register definitions */
+typedef struct u2p_aml_regs {
+ volatile uint32_t u2p_r0;
+ volatile uint32_t u2p_r1;
+} u2p_aml_regs_t;
+
+typedef union u2p_r0 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned host_device:1;
+ unsigned power_ok:1;
+ unsigned hast_mode:1;
+ unsigned POR:1;
+ unsigned IDPULLUP0:1;
+ unsigned DRVVBUS0:1;
+ unsigned reserved:26;
+ } b;
+} u2p_r0_t;
+
+typedef union u2p_r1 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned phy_rdy:1;
+ unsigned IDDIG0:1;
+ unsigned OTGSESSVLD0:1;
+ unsigned VBUSVALID0:1;
+ unsigned reserved:28;
+ } b;
+} u2p_r1_t;
+
+
+typedef struct usb_aml_regs {
+ volatile uint32_t usb_r0;
+ volatile uint32_t usb_r1;
+ volatile uint32_t usb_r2;
+ volatile uint32_t usb_r3;
+ volatile uint32_t usb_r4;
+ volatile uint32_t usb_r5;
+} usb_aml_regs_t;
+
+typedef union usb_r0 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned reserved:17;
+ unsigned p30_lane0_tx2rx_loopback:1;
+ unsigned p30_lane0_ext_pclk_reg:1;
+ unsigned p30_pcs_rx_los_mask_val:10;
+ unsigned u2d_ss_scaledown_mode:2;
+ unsigned u2d_act:1;
+ } b;
+} usb_r0_t;
+
+typedef union usb_r1 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned u3h_bigendian_gs:1;
+ unsigned u3h_pme_en:1;
+ unsigned u3h_hub_port_overcurrent:3;
+ unsigned reserved_1:2;
+ unsigned u3h_hub_port_perm_attach:3;
+ unsigned reserved_2:2;
+ unsigned u3h_host_u2_port_disable:2;
+ unsigned reserved_3:2;
+ unsigned u3h_host_u3_port_disable:1;
+ unsigned u3h_host_port_power_control_present:1;
+ unsigned u3h_host_msi_enable:1;
+ unsigned u3h_fladj_30mhz_reg:6;
+ unsigned p30_pcs_tx_swing_full:7;
+ } b;
+} usb_r1_t;
+
+typedef union usb_r2 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned reserved:20;
+ unsigned p30_pcs_tx_deemph_3p5db:6;
+ unsigned p30_pcs_tx_deemph_6db:6;
+ } b;
+} usb_r2_t;
+
+typedef union usb_r3 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned p30_ssc_en:1;
+ unsigned p30_ssc_range:3;
+ unsigned p30_ssc_ref_clk_sel:9;
+ unsigned p30_ref_ssp_en:1;
+ unsigned reserved:18;
+ } b;
+} usb_r3_t;
+
+typedef union usb_r4 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned p21_PORTRESET0:1;
+ unsigned p21_SLEEPM0:1;
+ unsigned mem_pd:2;
+ unsigned p21_only:1;
+ unsigned reserved:27;
+ } b;
+} usb_r4_t;
+
+typedef union usb_r5 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned iddig_sync:1;
+ unsigned iddig_reg:1;
+ unsigned iddig_cfg:2;
+ unsigned iddig_en0:1;
+ unsigned iddig_en1:1;
+ unsigned iddig_curr:1;
+ unsigned usb_iddig_irq:1;
+ unsigned iddig_th:8;
+ unsigned iddig_cnt:8;
+ unsigned reserved:8;
+ } b;
+} usb_r5_t;
+
+/* usb id mode, only after M2
+ mode = 0 : HARDWARE
+ mode = 1 : SW_HOST
+ mode = 2 : SW_DEVICE
+ */
+#define USB_ID_MODE_HARDWARE (1)
+#define USB_ID_MODE_SW_HOST (2)
+#define USB_ID_MODE_SW_DEVICE (3)
+int usb2_phy_tuning(uint32_t phy2_pll_base, int port);
+void set_usb_pll(uint32_t phy2_pll_base);
+int usb_save_phy_dev (unsigned int number, struct phy *phy);
+int usb2_phy_init (struct phy *phy);
+unsigned int usb_get_dwc_a_base_addr(void);
+unsigned int usb_get_device_mode_phy_base(void);
+void usb_phy_tuning_reset(void);
+void usb_device_mode_init(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-c2/acs.h b/arch/arm/include/asm/arch-c2/acs.h
new file mode 100644
index 0000000..65de6df
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/acs.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __ACS_H
+#define __ACS_H
+
+#ifndef __ASSEMBLY__
+typedef struct acs_setting{
+ char acs_magic[5]; //acs setting magic word, make sure this piece of data was right.
+ unsigned char chip_type; //chip type
+ unsigned short version; //version of acs_setting struct, for PC tool use.
+ unsigned long acs_set_length; //length of current struct.
+
+ //ddr setting part, 16 bytes
+ char ddr_magic[5]; //magic word to indicate that following 12 bytes was ddr setting.
+ unsigned char ddr_set_version; //struct version, for PC tool use.
+ unsigned short ddr_set_length; //length of ddr struct.
+ unsigned long ddr_set_addr; //address of ddr setting.
+
+ char ddr_reg_magic[5];
+ unsigned char ddr_reg_version;
+ unsigned short ddr_reg_length;
+ unsigned long ddr_reg_addr;
+
+ char pll_magic[5];
+ unsigned char pll_set_version;
+ unsigned short pll_set_length;
+ unsigned long pll_set_addr;
+
+ char sto_magic[5];
+ unsigned char sto_set_version;
+ unsigned short sto_set_length;
+ unsigned long sto_set_addr;
+
+ char bl2_regs_magic[5];
+ unsigned char bl2_regs_version;
+ unsigned short bl2_regs_length;
+ unsigned long bl2_regs_addr;
+
+ char rsv_magic[5];
+ unsigned char rsv_set_version;
+ unsigned short rsv_set_length;
+ unsigned long rsv_set_addr;
+ char board_id[12];
+ unsigned short ddr_struct_size[12];
+ unsigned long ddr_struct_org_size;
+ char revision[40];
+}__attribute__ ((packed)) acs_set_t;
+
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-c2/bl31_apis.h b/arch/arm/include/asm/arch-c2/bl31_apis.h
new file mode 100644
index 0000000..115b260
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/bl31_apis.h
@@ -0,0 +1,153 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ * Trustzone API
+ *
+ * Copyright (C) 2012 Amlogic, Inc.
+ *
+ * Author: Platform-SH@amlogic.com
+ *
+ */
+
+#ifndef __GXBB_BL31_APIS_H
+#define __GXBB_BL31_APIS_H
+
+#include <asm/arch/io.h>
+
+/*#define SRAM_READ 0x82000010
+#define CORE_RD_REV1 0x82000011
+#define SRAM_ACS_READ 0x82000012
+#define SRAM_ACS_INDIRECT_READ 0x82000013*/
+
+#define GET_SHARE_MEM_INPUT_BASE 0x82000020
+#define GET_SHARE_MEM_OUTPUT_BASE 0x82000021
+#define GET_REBOOT_REASON 0x82000022
+#define GET_SHARE_STORAGE_IN_BASE 0x82000023
+#define GET_SHARE_STORAGE_OUT_BASE 0x82000024
+#define GET_SHARE_STORAGE_BLOCK_BASE 0x82000025
+#define GET_SHARE_STORAGE_MESSAGE_BASE 0x82000026
+#define GET_SHARE_STORAGE_BLOCK_SIZE 0x82000027
+#define SET_STORAGE_INFO 0x82000028
+#define SET_REBOOT_REASON 0x82000049
+
+/* Set Reboot Reason then Reboot*/
+#define PSCI_SYS_REBOOT 0x84000009
+
+/* SECUREOS DEFINITION*/
+/* SMC Identifiers for non-secure world functions */
+#define CALL_TRUSTZONE_HAL_API 0x5
+
+/* EFUSE */
+#define EFUSE_READ 0x82000030
+#define EFUSE_WRITE 0x82000031
+#define EFUSE_WRITE_PATTERN 0x82000032
+#define EFUSE_USER_MAX 0x82000033
+
+#define DEBUG_EFUSE_WRITE_PATTERN 0x820000F0
+#define DEBUG_EFUSE_READ_PATTERN 0x820000F1
+
+/* JTAG*/
+#define JTAG_ON 0x82000040
+#define JTAG_OFF 0x82000041
+
+#define SET_USB_BOOT_FUNC 0x82000043
+ /* USB BOOT FUNC sub command list*/
+ #define CLEAR_USB_BOOT 1
+ #define FORCE_USB_BOOT 2
+ #define RUN_COMD_USB_BOOT 3
+ #define PANIC_DUMP_USB_BOOT 4
+
+#define GET_CHIP_ID 0x82000044
+
+/* tsensor calibration data */
+#define TSENSOR_CALI_SET 0x8200004C
+
+/*oscring efuse value get */
+#define OSCRING_EFUSE_GET 0x8200004D
+/* Security Key*/
+#define SECURITY_KEY_QUERY 0x82000060
+#define SECURITY_KEY_READ 0x82000061
+#define SECURITY_KEY_WRITE 0x82000062
+#define SECURITY_KEY_TELL 0x82000063
+#define SECURITY_KEY_VERIFY 0x82000064
+#define SECURITY_KEY_STATUS 0x82000065
+#define SECURITY_KEY_NOTIFY 0x82000066
+#define SECURITY_KEY_LIST 0x82000067
+#define SECURITY_KEY_REMOVE 0x82000068
+#define SECURITY_KEY_NOTIFY_EX 0x82000069
+#define SECURITY_KEY_SET_ENCTYPE 0x8200006A
+#define SECURITY_KEY_GET_ENCTYPE 0x8200006B
+#define SECURITY_KEY_VERSION 0x8200006C
+
+/*viu probe en*/
+#define VIU_PREOBE_EN 0x82000080
+/*set boot first timeout*/
+#define SET_BOOT_FIRST 0x82000087
+
+/* Secure HAL APIs */
+#define TRUSTZONE_HAL_API_SRAM 0x400
+
+/*start hifi4 */
+#define START_HIFI4 0x82000090
+#define DSP_SEC_POWERSET 0x82000092
+
+
+#define SRAM_HAL_API_CHECK_EFUSE 0x403
+struct sram_hal_api_arg {
+ unsigned int cmd;
+ unsigned int req_len;
+ unsigned int res_len;
+ unsigned long req_phy_addr;
+ unsigned long res_phy_addr;
+ unsigned long ret_phy_addr;
+};
+
+#define JTAG_STATE_ON 0
+#define JTAG_STATE_OFF 1
+#define JTAG_M3_AO 0
+#define JTAG_M3_EE 1
+#define JTAG_A53_AO 2
+#define JTAG_A53_EE 3
+#define CLUSTER_BIT 2
+
+
+/////////////////////////////////////////////////////////////////////////////////
+#define AML_DATA_PROCESS (0x820000FF)
+ #define AML_D_P_W_EFUSE_SECURE_BOOT (0x10)
+ #define AML_D_P_W_EFUSE_PASSWORD (0x11)
+ #define AML_D_P_W_EFUSE_CUSTOMER_ID (0x12)
+ #define AML_D_P_W_EFUSE_AMLOGIC (0x20)
+ #define AML_D_P_IMG_DECRYPT (0x40)
+ #define AML_D_P_UPGRADE_CHECK (0x80)
+
+#define GXB_EFUSE_PATTERN_SIZE (0x500)
+#define GXB_IMG_SIZE (24<<20)
+#define GXB_IMG_LOAD_ADDR (0x1080000)
+ #define GXB_IMG_DEC_KNL (1<<0)
+ #define GXB_IMG_DEC_RMD (1<<1)
+ #define GXB_IMG_DEC_DTB (1<<2)
+ #define GXB_IMG_DEC_ALL (GXB_IMG_DEC_KNL|GXB_IMG_DEC_RMD|GXB_IMG_DEC_DTB)
+
+#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+void aml_set_jtag_state(unsigned state, unsigned select);
+unsigned aml_get_reboot_reason(void);
+unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2);
+void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2);
+unsigned long aml_sec_boot_check(unsigned long ,unsigned long ,unsigned long,unsigned long );
+long get_sharemem_info(unsigned long);
+void set_usb_boot_function(unsigned long command);
+void aml_system_off(void);
+
+void bl31_get_chipid(unsigned int *, unsigned int *,
+ unsigned int *, unsigned int *);
+void set_viu_probe_enable(void);
+void wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value);
+void power_set_dsp(unsigned int id, unsigned int powerflag);
+void init_dsp(unsigned int id,unsigned int addr,unsigned int cfg0);
+void set_boot_first_timeout(uint64_t arg0);
+int bl31_get_cornerinfo(uint8_t *outbuf, int size);
+#endif
diff --git a/arch/arm/include/asm/arch-c2/board_id.h b/arch/arm/include/asm/arch-c2/board_id.h
new file mode 100644
index 0000000..6488771
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/board_id.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+unsigned int get_board_id(void);
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-c2/clk_measure_tab.h b/arch/arm/include/asm/arch-c2/clk_measure_tab.h
new file mode 100644
index 0000000..ceeb14f
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/clk_measure_tab.h
@@ -0,0 +1,84 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _ARCH_MESON_C2_MEASURE_H_
+#define _ARCH_MESON_A1_MEASURE_H_
+
+static const char* clk_msr_table[] = {
+ [0] = "tdmout_b_sclk",
+ [1] = "tdmout_a_sclk",
+ [2] = "tdmin_lb_sclk",
+ [3] = "tdmin_b_sclk",
+ [4] = "tdmin_a_sclk",
+ [5] = "vad_clk",
+ [6] = "resampleA_clk",
+ [7] = "pdm_sysclk",
+ [8] = "pdm_dclk",
+ [9] = "locker_out_clk",
+ [10] = "locker_in_clk",
+ [12] = "tdmin_vad_clk",
+ [13] = "au_adc_clk",
+ [14] = "au_dac_clk",
+ [15] = "resampleb_clk",
+ [16] = "spicc_a_clk",
+ [17] = "spifc_clk",
+ [18] = "sd_emmc_a_clk",
+ [19] = "spicc_b_clk",
+ [20] = "axi_clk_frcpu",
+ [21] = "deskew_pll_clk",
+ [24] = "ts_clk",
+ [25] = "pwm_f_clk",
+ [26] = "pwm_e_clk",
+ [27] = "pwm_d_clk",
+ [28] = "pwm_c_clk",
+ [29] = "pwm_b_clk",
+ [30] = "pwm_a_clk",
+ [31] = "saradc_clk",
+ [32] = "usb_bus",
+ [34] = "dsp_a_clk",
+ [35] = "axi_clk_nic",
+ [36] = "sys_clk_nic",
+ [37] = "gp_pll_ckout2",
+ [38] = "gp_pll_ckout1",
+ [39] = "gpio_msr",
+ [40] = "rng_ring_osc0",
+ [41] = "rng_ring_osc1",
+ [42] = "rng_ring_osc2",
+ [43] = "rng_ring_osc3",
+ [45] = "sys_cpu_clk_div16",
+
+ [64] = "usb_pll_out",
+ [65] = "sar_adc_clk",
+ [66] = "mod_crt_clk25",
+ [67] = "mod_crt_clk12_24",
+ [68] = "cts_mipi_isp_clk",
+ [69] = "cts_mipi_csi_phy_clk",
+ [70] = "cts_nna_axi_clk",
+ [71] = "cts_nna_core_clk",
+ [73] = "cts_secpu_clk",
+ [74] = "cts_jpeg_enc_clk ",
+ [75] = "cts_rtc_clk",
+ [76] = "cts_ge2d_clk",
+ [77] = "cts_gdc_axi_clk",
+ [78] = "cts_gdc_core_clk",
+ [79] = "cts_pwm_j_clk",
+ [80] = "cts_pwm_i_clk",
+ [81] = "cts_pwm_h_clk",
+ [82] = "cts_pwm_g_clk",
+ [83] = "cts_wave_cclk",
+ [84] = "cts_wave_bclk",
+ [85] = "cts_wave_aclk",
+ [86] = "cts_sd_emmc_C_clk",
+ [87] = "cts_sd_emmc_B_clk",
+ [89] = "mipi_csi_phy0_clk",
+ [90] = "mipi_csi_phy1_clk",
+ [91] = "mod_eth_phy_ref_clk",
+ [92] = "ddr_dpll_pt_clk",
+ [93] = "osc_ring_cpu0",
+ [94] = "osc_ring_cpu0",
+ [95] = "osc_ring_cpu0",
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-c2/clock.h b/arch/arm/include/asm/arch-c2/clock.h
new file mode 100644
index 0000000..e361e1f
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/clock.h
@@ -0,0 +1,122 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __C2_H
+#define __C2_H
+
+/*
+ * Clock controller register address
+ * APB_BASE: APB0_BASE_ADDR = 0xfe000800
+ */
+#define C2_SYS_OSCIN_CTRL 0x0
+#define C2_RTC_BY_OSCIN_CTRL0 0x4
+#define C2_RTC_BY_OSCIN_CTRL1 0x8
+#define C2_RTC_CTRL 0xc
+#define C2_SYS_CLK_CTRL0 0x10
+#define C2_AXI_CLK_CTRL0 0x14
+#define C2_SYS_CLK_EN0 0x18
+#define C2_SYS_CLK_EN1 0x1c
+#define C2_SYS_CLK_EN2 0x20
+#define C2_AXI_CLK_EN 0x24
+#define C2_DSPA_CLK_EN 0x28
+#define C2_DSPB_CLK_EN 0x2c
+#define C2_DSPA_CLK_CTRL0 0x30
+#define C2_DSPB_CLK_CTRL0 0x34
+#define C2_CLK12_24_CTRL 0x38
+#define C2_GEN_CLK_CTRL 0x3c
+#define C2_TIMESTAMP_CTRL0 0x40
+#define C2_TIMESTAMP_CTRL1 0x44
+#define C2_TIMESTAMP_CTRL2 0x48
+#define C2_TIMESTAMP_VAL0 0x4c
+#define C2_TIMESTAMP_VAL1 0x50
+#define C2_TIMEBASE_CTRL0 0x54
+#define C2_TIMEBASE_CTRL1 0x58
+#define C2_SAR_ADC_CLK_CTRL 0xc0
+#define C2_PWM_CLK_AB_CTRL 0xc4
+#define C2_PWM_CLK_CD_CTRL 0xc8
+#define C2_PWM_CLK_EF_CTRL 0xcc
+#define C2_SPICC_CLK_CTRL 0xd0
+#define C2_TS_CLK_CTRL 0xd4
+#define C2_SPIFC_CLK_CTRL 0xd8
+#define C2_USB_BUSCLK_CTRL 0xdc
+#define C2_SD_EMMC_CLK_CTRL 0xe0
+#define C2_CECA_CLK_CTRL0 0xe4
+#define C2_CECA_CLK_CTRL1 0xe8
+#define C2_CECB_CLK_CTRL0 0xec
+#define C2_CECB_CLK_CTRL1 0xf0
+#define C2_PSRAM_CLK_CTRL 0xf4
+#define C2_DMC_CLK_CTRL 0xf8
+#define C2_FCLK_DIV1_SEL 0xfc
+#define C2_TST_CTRL 0x100
+#define C2_WAVE_CLK_CTRL0 0x104
+#define C2_WAVE_CLK_CTRL1 0x108
+#define C2_JPEG_CLK_CTRL 0x10C
+#define C2_MIPI_ISP_CLK_CTRL 0x110
+#define C2_NNA_CLK_CTRL 0x114
+#define C2_GDC_CLK_CTRL 0x118
+#define C2_GE2D_CLK_CTRL 0x11C
+#define C2_SD_EMMC_CLK_CTRL1 0x120
+#define C2_ETH_CLK_CTRL 0x124
+#define C2_PWM_CLK_GH_CTRL 0x128
+#define C2_PWM_CLK_IJ_CTRL 0x12C
+#define C2_MBIST_ATSPEED_CTRL 0x130
+
+/*
+ * For PLl register offset
+ * APB_BASE: APB0_BASE_ADDR = 0xfe007c00
+ */
+#define C2_ANACTRL_FIXPLL_GATE_DIS 0x40 + 0x7400
+#define C2_ANACTRL_FIXPLL_CTRL0 0x80 + 0x7400
+#define C2_ANACTRL_FIXPLL_CTRL1 0x84 + 0x7400
+#define C2_ANACTRL_FIXPLL_CTRL2 0x88 + 0x7400
+#define C2_ANACTRL_FIXPLL_CTRL3 0x8c + 0x7400
+#define C2_ANACTRL_FIXPLL_CTRL4 0x90 + 0x7400
+#define C2_ANACTRL_FIXPLL_CTRL5 0x94 + 0x7400
+#define C2_ANACTRL_FIXPLL_CTRL6 0x98 + 0x7400
+#define C2_ANACTRL_FIXPLL_STS 0x9c + 0x7400
+#define C2_ANACTRL_GPPLL_CTRL0 0xc0 + 0x7400
+#define C2_ANACTRL_GPPLL_CTRL1 0xc4 + 0x7400
+#define C2_ANACTRL_GPPLL_CTRL2 0xc8 + 0x7400
+#define C2_ANACTRL_GPPLL_CTRL3 0xcc + 0x7400
+#define C2_ANACTRL_GPPLL_CTRL4 0xd0 + 0x7400
+#define C2_ANACTRL_GPPLL_CTRL5 0xd4 + 0x7400
+#define C2_ANACTRL_GPPLL_STS 0xd8 + 0x7400
+#define C2_ANACTRL_GPPLL_CTRL6 0xdc + 0x7400
+#define C2_ANACTRL_SYSPLL_CTRL0 0x100 + 0x7400
+#define C2_ANACTRL_SYSPLL_CTRL1 0x104 + 0x7400
+#define C2_ANACTRL_SYSPLL_CTRL2 0x108 + 0x7400
+#define C2_ANACTRL_SYSPLL_CTRL3 0x10c + 0x7400
+#define C2_ANACTRL_SYSPLL_CTRL4 0x110 + 0x7400
+#define C2_ANACTRL_SYSPLL_STS 0x114 + 0x7400
+#define C2_ANACTRL_HIFIPLL_CTRL0 0x140 + 0x7400
+#define C2_ANACTRL_HIFIPLL_CTRL1 0x144 + 0x7400
+#define C2_ANACTRL_HIFIPLL_CTRL2 0x148 + 0x7400
+#define C2_ANACTRL_HIFIPLL_CTRL3 0x14c + 0x7400
+#define C2_ANACTRL_HIFIPLL_CTRL4 0x150 + 0x7400
+#define C2_ANACTRL_HIFIPLL_STS 0x154 + 0x7400
+//#define C1_ANACTRL_AUDDDS_CTRL0 0x180 + 0x7400
+//#define C1_ANACTRL_AUDDDS_CTRL1 0x184 + 0x7400
+//#define C1_ANACTRL_AUDDDS_CTRL2 0x188 + 0x7400
+//#define C1_ANACTRL_AUDDDS_CTRL3 0x18c + 0x7400
+//#define C1_ANACTRL_AUDDDS_CTRL4 0x190 + 0x7400
+//#define C1_ANACTRL_AUDDDS_STS 0x194 + 0x7400
+#define C2_ANACTRL_MISCTOP_CTRL0 0x1c0 + 0x7400
+#define C2_ANACTRL_POR_CNTL 0x208 + 0x7400
+
+/*
+ * CPU clok register offset
+ * APB_BASE: APB1_BASE_ADDR = 0xfe007400
+ */
+/*
+ *#define C1_CPUCTRL_CLK_CTRL0 0x0 + 0x7400
+ *#define C1_CPUCTRL_CLK_CTRL1 0x4 + 0x7400
+ *#define C1_CPUCTRL_CLK_CTRL5 0x14 + 0x7400
+ *#define C1_CPUCTRL_CLK_CTRL6 0x18 + 0x7400
+ */
+
+#include <dt-bindings/clock/c2-clkc.h>
+#define NR_CLKS (CLKID_END_BASE)
+
+#endif /* __C1_H */
diff --git a/arch/arm/include/asm/arch-c2/core.h b/arch/arm/include/asm/arch-c2/core.h
new file mode 100644
index 0000000..97fd220
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/core.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __CORE_H__
+#define __CORE_H__
+
+int get_core_mpidr(unsigned int cpuid);
+int get_core_idx(unsigned int mpidr);
+int get_core_max(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-c2/cpu.h b/arch/arm/include/asm/arch-c2/cpu.h
new file mode 100644
index 0000000..478eb38
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/cpu.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+/* #include <config.h> */
+/* #include <asm/plat-cpu.h> */
+/* #include <asm/arch/ddr.h> */
+
+#if 0
+#define CONFIG_AML_MESON 1
+#define CONFIG_AML_MESON_GX 1
+#define CONFIG_AML_MESON_G12A 1
+#endif
+
+/*enable viu probe*/
+#if 0
+#define CONFIG_CMD_VIU_PROBE 1
+#endif
+
+/* for uboot envrionment use */
+#define CONFIG_DDR_SIZE 256
+
+/* dram */
+#define PHYS_SDRAM_1_BASE 0x00000000UL
+#define PHYS_SDRAM_1_SIZE 0x10000000UL
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1_BASE
+
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1_BASE + CONFIG_SYS_TEXT_BASE)
+
+/* console/print buffer */
+#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
+
+/* use "hush" command parser */
+#if 0
+#define CONFIG_SYS_HUSH_PARSER
+#endif
+
+#if 0
+#define CONFIG_DTB_MEM_ADDR 0x1000000
+#endif
+
+#if 0
+#define CONFIG_AML_CUSTOMER_ID (0)
+#endif
+
+#define AML_CUSTOMER_ID (0)
+
+//#define CONFIG_SILENT_CONSOLE
+//#define CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC
+//#define CONFIG_SILENT_U_BOOT_ONLY
+
+/* 2018.03.19 new compress solution, only support BL33 LZ4 compress */
+#define CONFIG_AML_BL33_COMPRESS_ENABLE 1
+
+/* 2018.03.19 G12A only support v3 format for normal & secure boot */
+#define CONFIG_AML_SECURE_BOOT_V3 1
+
+#define NR_CPUS 4
+
+#define CPU_ID_REG SYSCTRL_SEC_STATUS_REG0
+#define PACKAGE_ID_MASK 0xFF
+
+/*C1 SoC secure boot solution default not support AES algorithm*/
+//#define CONFIG_AML_CRYPTO_AES 1
+
+
+/*Flag for enable AES key generate to EFUSE pattern, with this flag only
+AES key will be generated to EFUSE pattern, it can be used for use case
+like the AES key not ready when secure boot enabled for the first time.
+*/
+//#define CONFIG_AML_EFUSE_GEN_AES_ONLY 1
+
+#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-c2/cpu_config.h b/arch/arm/include/asm/arch-c2/cpu_config.h
new file mode 100644
index 0000000..45e7e80
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/cpu_config.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _BOOT_ROM_CONFIG_H_
+#define _BOOT_ROM_CONFIG_H_
+
+/***********************************************************
+ * The following constants are GXBB definition
+ **********************************************************/
+#define ROMBOOT_START 0xD9040000
+#define ROM_SIZE (64*1024)
+#define ROMBOOT_END (ROMBOOT_START+ROM_SIZE)
+
+/***********************************************************
+ * AHB-SRAM Total Size 80KB, layout shown as below
+ *
+ * ROMCODE use the top 32KB
+ *
+ * [ 128] 0xD901_3F80 - 0xD901_3FFF Reserved
+ * [ 128] 0xD901_3F00 - 0xD901_3F7F CPUs Boot Entry
+ * [ 256] 0xD901_3E00 - 0xD901_3EFF Debug Info
+ * [ 512] 0xD901_3C00 - 0xD901_3DFF eFuse mirror
+ * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3)
+ * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) *
+ * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) *
+ * [ 26K] 0xD900_C800 - 0xD901_2FFF BL1 Stack, BSS
+ * [ 1K] 0xD900_C400 - 0xD900_C7FF NAND, USB Buffer
+ * [ 1K] 0xD900_C000 - 0xD900_C3FF Reserved
+ *
+ **********************************************************/
+#define RAM_START 0xD9000000
+#define RAM_SIZE (80 * 1024)
+#define BL1_RAM_START (RAM_START + 0xC000)
+#define BL1_RAM_SIZE (32 * 1024)
+#define BL1_RAM_END (BL1_RAM_START + BL1_RAM_SIZE)
+#define BSS_START (BL1_RAM_START + (2 * 1024))
+#define BSS_SIZE (18 * 1024)
+#define _STACK_END (BSS_START + BSS_SIZE + 8*1024)
+#define BL1_EFUSE_MIRROR (BL1_RAM_END - 1024)
+#define P_SHARED_EFUSE_MIRROR (volatile uint32_t *)(BL1_EFUSE_MIRROR)
+#define BL1_DEBUG_BUFFER (BL1_RAM_END - 512)
+#define CPU_BOOT_ENTRY (BL1_DEBUG_BUFFER + 256)
+#define P_SHARED_DEBUG_BUFF (volatile uint32_t *)(BL1_DEBUG_BUFFER)
+#define BL1_SEC_MBX (BL1_RAM_END - 2*1024)
+#define BL1_NAND_BUFF (BL1_RAM_START + 1024)
+#define BL1_USB_BUFF (BL1_NAND_BUFF)
+
+#define MEMORY_LOC RAM_START
+
+#define SRAM_DEBUG_BUFF_SIZE 256
+
+/* BL2 SPL size */
+#define BL2_SIZE (64 * 1024)
+
+//for signature test
+//#define CONFIG_AML_SIG_TEST_BUILD
+
+/* Software SHA2 */
+#define CONFIG_SHA2_SW
+
+/* Hardware SHA2 */
+#define CONFIG_SHA2_HW
+#define SHA2_HW_UPDATE_API
+
+/* Keep timer config in conf.h */
+#define CONFIG_TIMER
+
+/* Bootrom debug info */
+#define CONFIG_DEBUG_INFO
+
+/* Mincrypt RSA library */
+//#define CONFIG_MINCRYPT
+
+/* PolarSSL RSA library */
+#define CONFIG_POLARSSL_RSA
+
+#ifdef CONFIG_POLARSSL_RSA
+#ifndef CONFIG_MALLOC
+#define CONFIG_MALLOC
+#endif /* ! CONFIG_MALLOC */
+#endif /* CONFIG_POLARSSL_RSA */
+
+#endif /* _BOOT_ROM_CONFIG_H_ */
diff --git a/arch/arm/include/asm/arch-c2/cpu_reset.h b/arch/arm/include/asm/arch-c2/cpu_reset.h
new file mode 100644
index 0000000..46f9abf
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/cpu_reset.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _BOOT_ROM_WATCHDOG_H
+#define _BOOT_ROM_WATCHDOG_H
+#include <asm/arch/secure_apb.h>
+
+void reset_system(void);
+
+/* uboot reset interface */
+void reset_cpu(unsigned long flag);
+
+#endif /* _BOOT_ROM_WATCHDOG_H */
diff --git a/arch/arm/include/asm/arch-c2/cpu_sdio.h b/arch/arm/include/asm/arch-c2/cpu_sdio.h
new file mode 100644
index 0000000..46f366a
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/cpu_sdio.h
@@ -0,0 +1,239 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __CPU_SDIO_H__
+#define __CPU_SDIO_H__
+
+#define SD_EMMC_BASE_A 0xFFE03000
+#define SD_EMMC_BASE_B 0xFFE05000
+#define SD_EMMC_BASE_C 0xFFE07000
+
+#define SDIO_PORT_A 0
+#define SDIO_PORT_B 1
+#define SDIO_PORT_C 2
+
+struct sd_emmc_global_regs {
+ volatile uint32_t gclock; // 0x00
+ volatile uint32_t gdelay; // 0x04
+ volatile uint32_t gdelay1; //0x08
+ volatile uint32_t gadjust; // 0x0c
+ volatile uint32_t gcalout; // 0x10
+ volatile uint32_t reserved_14[11]; // 0x14~0x3c
+ volatile uint32_t gstart; // 0x40
+ volatile uint32_t gcfg; // 0x44
+ volatile uint32_t gstatus; // 0x48
+ volatile uint32_t girq_en; // 0x4c
+ volatile uint32_t gcmd_cfg; // 0x50
+ volatile uint32_t gcmd_arg; // 0x54
+ volatile uint32_t gcmd_dat; // 0x58
+ volatile uint32_t gcmd_rsp0; // 0x5c
+ volatile uint32_t gcmd_rsp1; // 0x60
+ volatile uint32_t gcmd_rsp2; // 0x64
+ volatile uint32_t gcmd_rsp3; // 0x68
+ volatile uint32_t reserved_6c; // 0x6c
+ volatile uint32_t gcurr_cfg; // 0x70
+ volatile uint32_t gcurr_arg; // 0x74
+ volatile uint32_t gcurr_dat; // 0x78
+ volatile uint32_t gcurr_rsp; // 0x7c
+ volatile uint32_t gnext_cfg; // 0x80
+ volatile uint32_t gnext_arg; // 0x84
+ volatile uint32_t gnext_dat; // 0x88
+ volatile uint32_t gnext_rsp; // 0x8c
+ volatile uint32_t grxd; // 0x90
+ volatile uint32_t gtxd; // 0x94
+ volatile uint32_t reserved_98[90]; // 0x98~0x1fc
+ volatile uint32_t gdesc[128]; // 0x200
+ volatile uint32_t gping[128]; // 0x400
+ volatile uint32_t gpong[128]; // 0x800
+};
+
+union sd_emmc_setup {
+ uint32_t d32;
+ struct {
+ unsigned bw:3;
+ unsigned fast:1;
+ unsigned par:3;
+ unsigned hcs:1;
+ unsigned sd:1;
+ unsigned sdhc:1;
+ unsigned type:6;
+ unsigned rca:16;
+ } b;
+};
+
+struct sd_emmc_desc_info{
+ uint32_t cmd_info;
+ uint32_t cmd_arg;
+ uint32_t data_addr;
+ uint32_t resp_addr;
+};
+
+struct cmd_cfg{
+ uint32_t length:9;
+ uint32_t block_mode:1;
+ uint32_t r1b:1;
+ uint32_t end_of_chain:1;
+ uint32_t timeout:4;
+ uint32_t no_resp:1;
+ uint32_t no_cmd:1;
+ uint32_t data_io:1;
+ uint32_t data_wr:1;
+ uint32_t resp_nocrc:1;
+ uint32_t resp_128:1;
+ uint32_t resp_num:1;
+ uint32_t data_num:1;
+ uint32_t cmd_index:6;
+ uint32_t error:1;
+ uint32_t owner:1;
+};
+
+struct sd_emmc_status{
+ uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire, for multiple block read, the CRC errors are ORed together.*/
+ uint32_t txd_err:1; /*[8] TX data CRC error, for multiple block write, any one of blocks CRC error. */
+ uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. The owner bit is ¡°0¡±, set cfg_ignore_owner to ignore this error.*/
+ uint32_t resp_err:1; /*[10] Response CRC error.*/
+ uint32_t resp_timeout:1; /*[11] No response received before time limit. The timeout limit is set by cfg_resp_timeout.*/
+ uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. The timeout limit is set by descriptor itself.*/
+ /* Consider the multiple block read/write, set the proper timeout limits.*/
+ uint32_t end_of_chain:1; /*[13] End of Chain IRQ, Normal IRQ. */
+ uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ, Normal IRQ, the descriptor chain execution keeps going on.*/
+ uint32_t irq_sdio:1; /*[15] SDIO device uses DAT[1] to request IRQ. */
+ uint32_t dat_i:8; /*[23:16] Input data signals. */
+ uint32_t cmd_i:1; /*[24] nput response signal. */
+ uint32_t ds:1; /*[25] Input data strobe. */
+ uint32_t bus_fsm:4; /*[29:26] BUS fsm */
+ uint32_t desc_wr_rdy:1; /*[30] Descriptor write back process is done and it is ready for CPU to read.*/
+ uint32_t core_rdy:1; /*[31] desc_busy or sd_emmc_irq or bus_fsm is not idle.*/
+};//__attribute__((__may_alias__));
+
+
+struct sd_emmc_clock{
+ uint32_t div:6; /*[5:0] Clock divider. Frequency = clock source/cfg_div, Maximum divider 63. */
+ /*Clock off: cfg_div==0, the clock is disabled */
+ /*Divider bypass: cfg_div==1, clock source is used as core clock without divider. */
+ uint32_t src:2; /*[7:6] Clock source, 0: Crystal 24MHz, 1: Fix PLL, 850MHz*/
+ /* 2: MPLL, <637MHz, used for 400MHz exactly. 3: different PLL */
+ uint32_t core_phase:2; /*[9:8] Core clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/
+ uint32_t tx_phase:2; /*[11:10] TX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/
+ uint32_t rx_phase:2; /*[13:12] RX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/
+ uint32_t reserved14:2;
+ uint32_t tx_delay:6; /*[21:16] TX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/
+ uint32_t rx_delay:6; /*[27:22] RX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/
+ uint32_t always_on:1; /*[28] 1: Keep clock always on. 0: Clock on/off controlled by activities. */
+ /*Any APB3 access or descriptor execution will keep clock on.*/
+ uint32_t irq_sdio_sleep:1; /*[29] 1: enable IRQ sdio when in sleep mode. */
+ uint32_t irq_sdio_sleep_ds:1;/*[30] 1:enable ds as irq*/
+ uint32_t reserved26:1;
+};
+
+struct sd_emmc_delay{
+ uint32_t dat0:6; /*[3:0] Data 0 delay line. */
+ uint32_t dat1:6; /*[7:4] Data 1 delay line. */
+ uint32_t dat2:6; /*[11:8] Data 2 delay line. */
+ uint32_t dat3:6; /*[15:12] Data 3 delay line. */
+ uint32_t dat4:6; /*[19:16] Data 4 delay line. */
+ uint32_t spare:2;
+};
+
+struct sd_emmc_delay1{
+ uint32_t dat5:6; /*[23:20] Data 5 delay line. */
+ uint32_t dat6:6; /*[27:24] Data 6 delay line. */
+ uint32_t dat7:6; /*[31:28] Data 7 delay line. */
+ uint32_t dat8:6; /*[31:28] Data 7 delay line. */
+ uint32_t dat9:6; /*[31:28] Data 7 delay line. */
+ uint32_t spare:2;
+};
+
+struct sd_emmc_adjust{
+ uint32_t cmd_delay:4; /*[3:0] Command delay line. */
+ uint32_t ds_delay:4; /*[7:4] DS delay line. */
+ uint32_t cali_sel:4; /*[11:8] Select one signal to be tested.*/
+ /*Signals are labeled from 0 to 9 the same as delay lines. */
+ uint32_t cali_enable:1; /*[12] Enable calibration. */
+ uint32_t adj_enable:1; /*[13] Adjust interface timing by resampling the input signals. */
+ uint32_t cali_rise:1; /*[14] 1: test the rising edge. 0: test the falling edge. */
+ uint32_t ds_enable:1; /*[15] Sampling the DAT based on DS in HS400 mode*/
+ uint32_t adj_delay:6; /*[21:16] Resample the input signals when clock index==adj_delay. */
+ uint32_t adj_auto:1; /*[22] Use cali_dut first falling edge to adjust the timing */
+ /*set cali_enable to 1 to use this function*/
+ uint32_t reserved23:9;
+};
+
+
+struct sd_emmc_calout{
+ uint32_t cali_idx:6; /*[5:0] Calibration reading. The event happens at this index. */
+ uint32_t reserved6:1;
+ uint32_t cali_vld:1; /*[7] The reading is valid. */
+ uint32_t cali_setup:8; /*[15:8] Copied from BASE+0x8 [15:8] include cali_sel, cali_enable, adj_enable, cali_rise. */
+ uint32_t reserved16:16;
+};
+
+
+struct sd_emmc_start{
+ uint32_t init:1; /*[0] 1: Read descriptor from internal SRAM, limited to 32 descriptors. */
+ /* 0: Read descriptor from external DDR */
+ uint32_t busy:1; /*[1] 1: Start command chain execution process. 0: Stop */
+ uint32_t addr:30; /*[31:2] Descriptor address, the last 2 bits are 0, 4 bytes aligned. */
+ /* When internal SRAM is used, the valid address range is from 0x200~0x3ff */
+ /* When external DDR is used, the valid address is anywhere in DDR, the length of chain is unlimited.*/
+};//__attribute__((__may_alias__));
+
+
+struct sd_emmc_config{
+ uint32_t bus_width:2; /*[1:0] 0: 1 bit, 1: 4 bits, 2: 8 bits, 3: 2 bits (not supported)*/
+ uint32_t ddr:1; /*[2] 1: DDR mode, 0: SDR mode */
+ uint32_t dc_ugt:1; /*[3] 1: DDR access urgent, 0: DDR access normal. */
+ uint32_t bl_len:4; /*[7:4] Block length 2^cfg_bl_len, because internal buffer size is limited to 512 bytes, the cfg_bl_len <=9. */
+ uint32_t resp_timeout:4; /*[11:8] Wait response till 2^cfg_resp_timeout core clock cycles. Maximum 32768 core cycles. */
+ uint32_t rc_cc:4; /*[15:12] Wait response-command, command-command gap before next command, 2^cfg_rc_cc core clock cycles. */
+ uint32_t out_fall:1; /*[16] DDR mode only. The command and TXD start from rising edge. Set 1 to start from falling edge. */
+ uint32_t blk_gap_ip:1; /*[17] 1: Enable SDIO data block gap interrupt period. 0: Disabled.*/
+ uint32_t spare:1; /*[18] Spare, ??? need check*/
+ uint32_t ignore_owner:1; /*[19] Use this descriptor even if its owner bit is ¡°0¡±.*/
+ uint32_t chk_ds:1; /*[20] Check data strobe in HS400.*/
+ uint32_t cmd_low:1; /*[21] Hold CMD as output Low, eMMC boot mode.*/
+ uint32_t stop_clk:1; /*[22] 1: stop clock. 0: normal clock.*/
+ /*In normal mode, the clock is automatically on/off during reading mode to back off reading in case of*/
+ /*DDR slow response, stop clock is used in voltage switch.*/
+ uint32_t auto_clk:1; /*[23] 1: when BUS is idle and no descriptor is available, turn off clock, to save power.*/
+ /* 0: core clock is always on.*/
+ uint32_t txd_add_err:1; /*[24] TXD add error test*/
+ /*Test feature, should not be used in normal condition.*/
+ /*It will inverted the first CRC bits of the 3rd block.*/
+ /*Block index starts from 0, 1, 2, ¡*/
+ uint32_t txd_retry:1; /*[25] When TXD CRC error, host sends the block again.*/
+ /*The total number of retries of one descriptor is limited to 15, */
+ /*after 15 retries, the TXD_err is set to high.*/
+ uint32_t revd:8; /*[31:26] reved*/
+};//__attribute__((__may_alias__));
+
+
+struct sd_emmc_irq_en{
+ uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire.*/
+ uint32_t txd_err:1; /*[8] TX data CRC error. */
+ uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. */
+ uint32_t resp_err:1; /*[10] Response CRC error.*/
+ uint32_t resp_timeout:1; /*[11] No response received before time limit. */
+ uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. */
+ uint32_t end_of_chain:1; /*[13] End of Chain IRQ. */
+ uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ. */
+ uint32_t irq_sdio:1; /*[15] Enable sdio interrupt. */
+ uint32_t revd:16; /*[31:16] reved*/
+};
+
+struct sd_emmc_data_info{
+ uint32_t cnt:10; /*[9:0] Rxd words received from BUS. Txd words received from DDR.*/
+ uint32_t blk:9; /*[24:16] Rxd Blocks received from BUS. Txd blocks received from DDR.*/
+ uint32_t revd:30; /*[31:17] Reved. */
+};
+
+
+struct sd_emmc_card_info{
+ uint32_t txd_cnt:10; /*[9:0] Txd BUS cycle counter. */
+ uint32_t txd_blk:9; /*[24:16] Txd BUS block counter.*/
+ uint32_t revd:30; /*[31:17] Reved. */
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-c2/ddr.h b/arch/arm/include/asm/arch-c2/ddr.h
new file mode 100644
index 0000000..ad27855
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/ddr.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <io.h>
+#include <stdint.h>
+#include <asm/arch/ddr_define.h>
+
+/* io defines */
+//#define wr_reg(addr, data) (*((volatile uint32_t *)addr))=(uint32_t)(uint64_t)(data)
+//#define rd_reg(addr) (*((volatile uint32_t *)(addr)))
+#define wr_reg(addr, data) writel(data, addr)
+#define rd_reg(addr) readl(addr)
+/*clear [mask] 0 bits in [addr], set these 0 bits with [value] corresponding bits*/
+#define modify_reg(addr, value, mask) wr_reg(addr, ((rd_reg(addr) & (mask)) | (value)))
+#define wait_set(addr, loc) do{}while(0 == (rd_reg(addr) & (1<<loc)));
+#define wait_clr(addr, loc) do{}while(1 == (rd_reg(addr) & (1<<loc)));
+#define wait_equal(addr, data) do{}while(data != (rd_reg(addr)));
+
+/* function defines */
+unsigned int ddr_init(void);
+unsigned int ddr_init_pll(void);
+unsigned int ddr_init_dmc(void);
+unsigned int ddr_init_pctl(void);
+unsigned int hot_boot(void);
+void ddr_print_info(void);
+void ddr_test(void);
+void ddr_pre_init(void);
+void ddr_debug(void);
+
+/* pctl status */
+#define UPCTL_STAT_MASK (7)
+#define UPCTL_STAT_INIT (0)
+#define UPCTL_STAT_CONFIG (1)
+#define UPCTL_STAT_ACCESS (3)
+#define UPCTL_STAT_LOW_POWER (5)
+
+/* pctl cmds */
+#define UPCTL_CMD_INIT (0)
+#define UPCTL_CMD_CONFIG (1)
+#define UPCTL_CMD_GO (2)
+#define UPCTL_CMD_SLEEP (3)
+#define UPCTL_CMD_WAKEUP (4)
+
+/* PUB PIR setting */
+#define PUB_PIR_INIT (1<<0)
+#define PUB_PIR_ZCAL (1<<1)
+#define PUB_PIR_CA (1<<2)
+#define PUB_PIR_PLLINIT (1<<4)
+#define PUB_PIR_DCAL (1<<5)
+#define PUB_PIR_PHYRST (1<<6)
+#define PUB_PIR_DRAMRST (1<<7)
+#define PUB_PIR_DRAMINIT (1<<8)
+#define PUB_PIR_WL (1<<9)
+#define PUB_PIR_QSGATE (1<<10)
+#define PUB_PIR_WLADJ (1<<11)
+#define PUB_PIR_RDDSKW (1<<12)
+#define PUB_PIR_WRDSKW (1<<13)
+#define PUB_PIR_RDEYE (1<<14)
+#define PUB_PIR_WREYE (1<<15)
+#define PUB_PIR_ICPC (1<<16)
+#define PUB_PIR_PLLBYP (1<<17)
+#define PUB_PIR_CTLDINIT (1<<18)
+#define PUB_PIR_RDIMMINIT (1<<19)
+#define PUB_PIR_CLRSR (1<<27)
+#define PUB_PIR_LOCKBYP (1<<28)
+#define PUB_PIR_DCALBYP (1<<29)
+#define PUB_PIR_ZCALBYP (1<<30)
+#define PUB_PIR_INITBYP (1<<31)
+
+/* PHY initialize register (PIR) */
+#define DDR_PIR ((PUB_PIR_ZCAL) |\
+ (PUB_PIR_PLLINIT) |\
+ (PUB_PIR_DCAL) |\
+ (PUB_PIR_PHYRST) |\
+ (PUB_PIR_DRAMRST) |\
+ (PUB_PIR_DRAMINIT) |\
+ (PUB_PIR_WL) |\
+ (PUB_PIR_QSGATE) |\
+ (PUB_PIR_WLADJ) |\
+ (PUB_PIR_RDDSKW) |\
+ (PUB_PIR_WRDSKW) |\
+ (PUB_PIR_RDEYE) |\
+ (PUB_PIR_WREYE) \
+ )
+
+/* PHY general status register (PGSR0) */
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+#define DDR_PGSR0_CHECK() ((rd_reg(DDR0_PUB_PGSR0) != 0xC0000fff) && \
+ (rd_reg(DDR0_PUB_PGSR0) != 0x80000fff))
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define DDR_PGSR0_CHECK()
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define DDR_PGSR0_CHECK()
+#endif
+
+/* other regs */
+#define SCRATCH0 0xC1107D3C
diff --git a/arch/arm/include/asm/arch-c2/ddr_define.h b/arch/arm/include/asm/arch-c2/ddr_define.h
new file mode 100644
index 0000000..28e6173
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/ddr_define.h
@@ -0,0 +1,577 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/* board id */
+#define CONFIG_BOARD_ID_MASK 0xFF
+#define CONFIG_FW_INFO_MASK 0xFFFFFFFF
+
+#define RESULT_OK 0x0
+#define RESULT_FAIL 0xFF
+#define RESULT_PLL_LOCK_FAIL 0x0F
+#define RESULT_USB_BOOT_NEVER 0xF0
+
+#define DDR_HDTCTRL_ENABLE_AMLOGIC_DDR4_PHY_VREF_CORRECTION 0x7
+#define DDR_HDTCTRL_SHOW_DDR3_LPDDR3_TRAINING_MARGIN 0x9
+#define DDR_HDTCTRL_SHOW_DDR3_LPDDR3_TRAINING_MARGIN_WRITE_DQ 0x00210005
+#define DDR_HDTCTRL_SHOW_DDR3_LPDDR3_TRAINING_MARGIN_WRITE_DQM 0x00290005
+#define DDR_HDTCTRL_SHOW_DDR3_LPDDR3_TRAINING_MARGIN_READ_DQ 0x003a0005
+
+#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_READ_START_1 0x00200004
+#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_READ_START_2 0x001e0004
+#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_READ_VREF 0x0014001f
+#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_READ_VREF_END 0x00610000
+
+#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_WRITE_START_1 0x001c0004
+#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_WRITE_START_2 0x00230004
+#define DDR_HDTCTRL_SHOW_LPDDR4_TRAINING_TDQS2DQ 0x00dd0002
+//#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_WRITE_VREF 0x0014001f
+//#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_WRITE_VREF_END 0x00610000
+#define DMC_PSTATE_MAX 4
+
+#define CONFIG_CHIP_TYPE_DRAM 0x1F
+#define CONFIG_CHIP_TYPE_PSRAM 0x2F
+#define CONFIG_DDR_TYPE_DDR3 0
+#define CONFIG_DDR_TYPE_DDR4 1
+#define CONFIG_DDR_TYPE_LPDDR4 2
+#define CONFIG_DDR_TYPE_LPDDR3 3
+#define CONFIG_DDR_TYPE_LPDDR2 4
+//#define CONFIG_DDR_TYPE_LPDDR4X 5
+#define CONFIG_DDR_TYPE_AUTO 0xf
+#define CONFIG_DDR_TYPE_AUTO_LIMIT CONFIG_DDR_TYPE_DDR4
+
+/* lpddr3 related define */
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE0 0
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE1 1
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE2 2
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE3 3
+
+#define LPDDR_DIE_ROW_COL_R13_C9 0
+#define LPDDR_DIE_ROW_COL_R14_C9 1
+#define LPDDR_DIE_ROW_COL_R14_C10 2
+#define LPDDR_DIE_ROW_COL_R13_C10 3
+#define LPDDR_DIE_ROW_COL_R14_C11 4
+
+#if 0
+/* ddr channel defines */
+#define CONFIG_DDR0_16BIT 1
+#define CONFIG_DDR0_RANK0 2
+#define CONFIG_DDR0_RANK01 3
+#define CONFIG_DDR0_16BIT_2 4
+#define CONFIG_DDR_CHL_AUTO 0xF
+#define CONFIG_DDR0_16BIT_CH0 0x1
+#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7
+#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8
+#define ENABLE_SKIP_1D_MEM_LOAD 0x0
+#define ENABLE_SKIP_1D_MEM_TRAINING 0x1
+#define ENABLE_SKIP_2D_MEM_LOAD 0x2
+#define ENABLE_SKIP_2D_MEM_TRAINING 0x3
+
+#define PHY_IMEM_STEP_1D 0x1
+#define PHY_IMEM_STEP_2D 0x2
+
+#endif
+#define VREF_SOC 0x1
+#define VREF_DRAM 0x2
+
+
+#define CFG_DDR_BASE_ADDR 0X0
+#define CFG_DDR_START_OFFSET 0X01000000 //SKIP 16MB
+
+/* ddr type identifier */
+#define CONFIG_DDR_TIMMING_LPDDR2 0x02
+#define CONFIG_DDR_TIMMING_LPDDR3 0x03
+#define CONFIG_DDR_TIMMING_DDR3_7 0x07
+#define CONFIG_DDR_TIMMING_DDR3_9 0x09
+#define CONFIG_DDR_TIMMING_DDR3_11 0x0B
+#define CONFIG_DDR_TIMMING_DDR3_12 0x0C
+#define CONFIG_DDR_TIMMING_DDR3_13 0x0D
+#define CONFIG_DDR_TIMMING_DDR3_14 0x0E
+
+#define CONFIG_DDR_TIMMING_DDR4_1600 0x0F
+#define CONFIG_DDR_TIMMING_DDR4_1866 0x10
+#define CONFIG_DDR_TIMMING_DDR4_2133 0x11
+#define CONFIG_DDR_TIMMING_DDR4_2400 0x12
+#define CONFIG_DDR_TIMMING_DDR4_2666 0x13
+#define CONFIG_DDR_TIMMING_DDR4_3200 0x14
+
+#define CONFIG_DDR_FUNC_TEST (1<<0)
+
+#define CONFIG_DDR_INIT_RETRY_TOTAL (10)
+#define CONFIG_DDR_PCTL_RETRY_TOTAL (100)
+
+#define DDR_USE_1_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK0) || \
+ (chl_set == CONFIG_DDR0_16BIT))
+#define DDR_USE_2_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK01) || \
+ (chl_set == CONFIG_DDR0_16BIT_2))
+
+#ifndef CONFIG_LPDDR3_CA_TRAINING_CA0
+#define CONFIG_LPDDR3_CA_TRAINING_CA0 CONFIG_LPDDR3_CA_TRAINING_USE_LANE0
+#endif
+#ifndef CONFIG_LPDDR3_CA_TRAINING_CA1
+#define CONFIG_LPDDR3_CA_TRAINING_CA1 CONFIG_LPDDR3_CA_TRAINING_USE_LANE1
+#endif
+
+/* DMC_DDR_CTRL defines */
+#define DDR_DDR4_ENABLE (1<<22)
+#define DDR_RANK1_ENABLE (1<<21)
+#define DDR_DDR4_BG_ENABLE (1<<20)
+#define DDR_16BIT_ENABLE (1<<16)
+
+#define DDR_RANK1_SIZE_CTRL (3)
+#define DDR_RANK0_SIZE_CTRL (0)
+
+/* ddr functions */
+#define DDR_FUNC_D2PLL (1<<0)
+#define DDR_FUNC_LP (1<<1)
+#define DDR_FUNC_ZQ_PD (1<<2)
+#define DDR_FUNC_EXT_VREF (1<<3)
+#define DDR_FUNC_DDR4_TIMING_TEST (1<<4)
+#define DDR_FUNC_DDR_PLL_BYPASS (1<<5)
+#define DDR_FUNC_RDBI (1<<6)
+#define DDR_FUNC_LPDDR3_CA (1<<7)
+#define DDR_FUNC_PRINT_WINDOW (1<<8)
+#define DDR_FUNC_FULL_TEST (1<<10)
+#define DDR_FUNC_NONSEC_SCRAMBLE (1<<11)
+#define DDR_FUNC_LPDDR3_CA_CA0_BIT0 (1<<20)
+#define DDR_FUNC_LPDDR3_CA_CA0_BIT1 (1<<21)
+#define DDR_FUNC_LPDDR3_CA_CA1_BIT0 (1<<22)
+#define DDR_FUNC_LPDDR3_CA_CA1_BIT1 (1<<23)
+#define DDR_FUNC_LPDDR3_CA_CA0_OFFSET (20)
+#define DDR_FUNC_LPDDR3_CA_CA1_OFFSET (22)
+#define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP (1<<25)
+#define DDR_FUNC_CONFIG_DDR_DVFS_FUNCTION (1<<28)
+#define DDR_FUNC_CONFIG_DFE_FUNCTION (1<<29)
+#define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1<<30)
+#define DDR_FUNC_SCRAMBLE (1<<31)
+
+
+/* dwc imem/dmem */
+#define DWC_MEM_LOAD_ADDR 0xFFFE0000
+#define DWC_IRAM_ADDR (0x50000)
+#define DWC_IRAM_SIZE (0x8000) /* 32K */
+#define DWC_DRAM_ADDR (0x54000)
+#define DWC_DRAM_SIZE (0x4000) /* 16K */
+
+/* dwc apb regs */
+#define UctWriteProtShadow 0xd0004
+#define UctWriteOnlyShadow 0xd0032
+#define UctWriteProt 0xd0031
+#define UctDatWriteOnlyShadow 0xd0034
+
+/* pctl status */
+#define UPCTL_STAT_MASK (7)
+#define UPCTL_STAT_INIT (0)
+#define UPCTL_STAT_CONFIG (1)
+#define UPCTL_STAT_ACCESS (3)
+#define UPCTL_STAT_LOW_POWER (5)
+
+/* pctl cmds */
+#define UPCTL_CMD_INIT (0)
+#define UPCTL_CMD_CONFIG (1)
+#define UPCTL_CMD_GO (2)
+#define UPCTL_CMD_SLEEP (3)
+#define UPCTL_CMD_WAKEUP (4)
+
+
+/* name id defined in firmware header */
+#define DDR_NAME_ID_AML_FW 0x304c4d41 //AML0
+#define DDR_NAME_ID_PIEI 0x61656165 //eaea
+#define DDR_NAME_ID_DDR3 0x33333364 //d333
+#define DDR_NAME_ID_DDR4 0x34343464 //d444
+#define DDR_NAME_ID_DDR4_2D 0x32323464 //d422
+#define DDR_NAME_ID_LPDDR3 0x33336C64 //dl33
+#define DDR_NAME_ID_LPDDR4 0x34346C64 //dl44
+#define DDR_NAME_ID_LPDDR4_2D 0x30346C64 //dl42
+#define DDR_NAME_ID_DIAGNOSE1 0x31676464 //ddg1
+#define DDR_NAME_ID_DIAGNOSE2 0x32676464 //ddg2
+/* PIEI */
+#define DDR_PIEI_START_FLAG 0xfeed //eaea
+
+/* dram cfg magic */
+#define DRAM_CFG_MAGIC 0x2e676663
+
+/* flow control */
+#define DDR_FIRMWARE_VERSION_1 0x00201709
+#define FW_LOAD_STEP_AML_FW 0xF
+#define FW_LOAD_STEP_PIEI 0
+#define FW_LOAD_STEP_1D 1
+#define FW_LOAD_STEP_2D 2
+#define FW_LOAD_STEP_DIAG1 3
+#define FW_LOAD_STEP_DIAG2 4
+
+/* basic defines */
+#define AML_AC_PINMUX_G0_TOTAL 6
+#define AML_AC_PINMUX_G1_TOTAL 29
+#define AML_DFI_PINMUX_TOTAL 26
+#define AML_DQ_PINMUX_TOTAL 36
+#define AML_DQ_BYTES_TOTAL 4
+
+
+/* d2pll defines */
+#define D2PLL_ENABLE 1
+#define DDR_STICKY_MAGIC_NUMBER 0x20180000
+#define DDR_CHIP_ID 0x30
+#define DDR_STICKY_OVERRIDE_CONFIG_MESSAGE_CMD 0x1 //override config
+#define DDR_STICKY_SPECIAL_FUNCTION_CMD 0x2 //special test such as shift some bdlr or parameter or interleave test
+#define DDR_INIT_CONFIG_STICKY_MESSAGE_SRAM_ADDRESS 0x00040000
+#define DDR_INIT_CONFIG_GLOBAL_MESSAGE_SRAM_ADDRESS 0x00050000
+
+
+/* debug function*/
+
+/* ddr configs */
+#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+
+#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+#define DDR_RFC_TYPE_LPDDR4_6Gbx1 12
+#define DDR_RFC_TYPE_LPDDR4_8Gbx1 13
+
+#define DDR_ENABLE_FINE_TUNE_FLAG_AC_DELAY (1<<0)
+#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQS (1<<1)
+#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS (1<<2)
+#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ (1<<3)
+#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ (1<<4)
+
+#define IMPEDENCE_120P3_240P2_480P1 1
+#define IMPEDENCE_120P6_1 2
+#define IMPEDENCE_120P3_240P2_480P1_ODT 3
+
+#define IMPEDENCE_AML_SOC_DATA 1
+#define IMPEDENCE_AML_SOC_AC 2
+
+
+#define VREF_DDR4_SDRAM_DAC 1
+#define VREF_LPDDR4_SDRAM_DAC 2
+#define VREF_LPDDR4X_SDRAM_DAC 3
+#define VREF_SOC_AML_DAC_LPDDR4 4
+#define VREF_SOC_AML_DAC_LPDDR4X 5
+#define VREF_SOC_AML_DAC_DDR3 6
+#define VREF_SOC_AML_DAC_DDR4 7
+
+#define DDR_PHY_BLOCK_ANIB 0x0
+#define DDR_PHY_BLOCK_DBYTE 0x1
+#define DDR_PHY_BLOCK_MASTER 0x2
+#define DDR_PHY_BLOCK_ACSM 0x4
+#define DDR_PHY_BLOCK_UPTCL_MEMORY 0x5
+#define DDR_PHY_BLOCK_PPGC 0x7
+#define DDR_PHY_BLOCK_INITENG 0x9
+#define DDR_PHY_BLOCK_PUB 0xC
+#define DDR_PHY_BLOCK_APBONLY 0xD
+
+/* others */ /* useless? */
+
+/* bist */
+#define CONFIG_DDR_CODE_INCLUDE_LPDDR3 0
+#define CONFIG_DDR_CODE_INCLUDE_DDR4 1
+#define CONFIG_DEBUG_INCLUDE_D2PLL 1
+#define CONFIG_DEBUG_DDR_BIST_TEST_WINDOWS 1
+#define CONFIG_DEBUG_DDR_BIST_ONLY_COMPARE_ONE_LANE 1
+#define CONFIG_DEBUG_DDR_BIST_BYTE_EXTRA_PATTERN 1
+#define CONFIG_DEBUG_DDR_BIST_NO_USE_FSM_INIT_VALUE 1
+#define CONFIG_DEBUG_DDR_BIST_NO_USE_FSM_INIT_VALUE_USE_LINEAR 0
+#define CONFIG_DEBUG_DDR_BIST_NO_USE_FSM_INIT_VALUE_USE_FAST_LINEAR 1
+#define CONFIG_DEBUG_DDR_BIST_USE_OLD_METHOD_AGAIN 0
+#define CONFIG_DDR_DMC_DDR_TEST 0
+#define CONFIG_DDR_CPU_DDR_TEST 0
+#define CONFIG_BIST_USE_THRESHOLD 0
+#define CONFIG_DEBUG_DDR_BIST_TEST_2D_EYE 0
+
+#define CONFIG_DEBUG_DDR_BIST_TEST_DATA
+//#define CONFIG_DEBUG_DDR_BIST_TEST_ADD
+
+#define DDR_BIST_LANE_DATA0 0
+#define DDR_BIST_LANE_DATA1 1
+#define DDR_BIST_LANE_DATA2 2
+#define DDR_BIST_LANE_DATA3 3
+#define DDR_BIST_LANE_AC 4
+
+#define DDR_BIST_PATTERN_WALK_0 0
+#define DDR_BIST_PATTERN_WALK_1 1
+#define DDR_BIST_PATTERN_WALK_RANDOM 2
+#define DDR_BIST_PATTERN_WALK_PRE 3
+
+/* diagnose function defines */
+#define CONFIG_DIAGNOSE_DISABLE 0x0
+#define CONFIG_DIAGNOSE_1D 0x1
+#define CONFIG_DIAGNOSE_2D 0x2
+#define CONFIG_DIAGNOSE_1D_2D 0x3
+
+#define DDR_RFC_TYPE_LPDDR4_6Gbx1 12
+#define DDR_RFC_TYPE_LPDDR4_8Gbx1 13
+
+
+#define CONFIG_BOARD_ID_DISABLE 0
+#define CONFIG_BOARD_ID_MASK 0xFF
+
+#define CONFIG_DDR_TYPE_DDR3 0
+#define CONFIG_DDR_TYPE_DDR4 1
+#define CONFIG_DDR_TYPE_LPDDR4 2
+#define CONFIG_DDR_TYPE_LPDDR3 3
+#define CONFIG_DDR_TYPE_LPDDR2 4
+#define CONFIG_DDR_TYPE_LPDDR4X 5
+
+#define CONFIG_DDR0_16BIT_CH0 1
+#define CONFIG_DDR0_16BIT_RANK01_CH0 4
+#define CONFIG_DDR0_32BIT_RANK0_CH0 2
+#define CONFIG_DDR0_32BIT_RANK01_CH01 3
+#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 5
+#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 6
+#define CONFIG_DDR0_32BIT_RANK01_CH0 7
+#define CONFIG_DDR0_32BIT_RANK0_CH01 8
+#define CONFIG_DDR0_32BIT_RANK0_16BIT_RANK1_LOW_CH0 0x9
+#define CONFIG_DDR0_32BIT_RANK0_16BIT_RANK1_HIGH_CH0 0xa
+#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0_MODE2 0xB
+#define CONFIG_DDR0_32BIT_RANK0_16BIT_RANK1_LOW_CH0_MODE2 0xC
+
+#define CONFIG_DISABLE_D32_D63 0xf0
+#define CONFIG_DISABLE_D16_D31 0xfc
+
+#define CONFIG_DDR0_SIZE_0MB 0
+#define CONFIG_DDR0_SIZE_128MB 128
+#define CONFIG_DDR0_SIZE_256MB 256
+#define CONFIG_DDR0_SIZE_512MB 512
+#define CONFIG_DDR0_SIZE_768MB 768
+#define CONFIG_DDR0_SIZE_1024MB 1024
+#define CONFIG_DDR0_SIZE_1536MB 1536
+#define CONFIG_DDR0_SIZE_2048MB 2048
+#define CONFIG_DDR0_SIZE_3072MB 3072
+#define CONFIG_DDR0_SIZE_4096MB 4096
+#define CONFIG_DDR0_SIZE_AUTO_SIZE 0xffff
+#define CONFIG_DDR1_SIZE_0MB 0
+#define CONFIG_DDR1_SIZE_128MB 128
+#define CONFIG_DDR1_SIZE_256MB 256
+#define CONFIG_DDR1_SIZE_512MB 512
+#define CONFIG_DDR1_SIZE_768MB 768
+#define CONFIG_DDR1_SIZE_1024MB 1024
+#define CONFIG_DDR1_SIZE_1536MB 1536
+#define CONFIG_DDR1_SIZE_2048MB 2048
+#define CONFIG_DDR1_SIZE_3072MB 3072
+#define CONFIG_DDR1_SIZE_4096MB 4096
+#define CONFIG_DDR1_SIZE_AUTO_SIZE 0xffff
+
+#define CONFIG_DRAM_MODE_X4 1
+#define CONFIG_DRAM_MODE_X8 1
+#define CONFIG_DRAM_MODE_X16 0
+
+#define CONFIG_USE_DDR_1T_MODE 0
+#define CONFIG_USE_DDR_2T_MODE 1
+
+#define eLOG_CHL_0 0
+#define eLOG_CHL_1 1
+#define eLOG_CHL_2 2
+#define eLOG_CHL_3 3
+#define eLOG_CHL_4 4
+#define eLOG_CHL_5 5
+#define eLOG_CHL_6 6
+#define eLOG_CHL_7 7
+
+#define LOG_LEVEL_BASIC (1<<eLOG_CHL_0)
+#define LOG_LEVEL_FULL (1<<eLOG_CHL_0)|(1<<eLOG_CHL_1)|(1<<eLOG_CHL_2)|(1<<eLOG_CHL_3)|(1<<eLOG_CHL_4)|(1<<eLOG_CHL_5)|(1<<eLOG_CHL_6)
+#define LOG_LEVEL_DEBUG (1<<eLOG_CHL_0)|(1<<eLOG_CHL_1)|(1<<eLOG_CHL_2)|(1<<eLOG_CHL_3)|(1<<eLOG_CHL_4)|(1<<eLOG_CHL_5)|(1<<eLOG_CHL_6)|(1<<eLOG_CHL_7)
+
+#define DDR_WRITE_READ_DBI_DISABLE 0
+#define DDR_READ_DBI_ENABLE 1
+#define DDR_WRITE_DBI_ENABLE 2
+#define DDR_WRITE_READ_DBI_ENABLE 3
+
+#define DDR_PLL_SSC_DISABLE 0
+#define DDR_PLL_SSC_3000PPM 0x3000
+#define DDR_PLL_SSC_5000PPM 0x3001
+#define DDR_PLL_SSC_6000PPM 0x3002
+#define DDR_PLL_SSC_8000PPM 0x3003
+#define DDR_PLL_SSC_9000PPM 0x3004
+
+#define DDR_DMC_REMAP_DDR3_32BIT {\
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25 ),\
+ [1] = ( 11| 0 << 5 | 0 << 10 | 12 << 15 | 16 << 20 | 17 << 25 ),\
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),\
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),\
+ [4] = ( 30| 13 << 5 | 14 << 10 | 15 << 15 | 0 << 20 | 0 << 25 ),\
+ }
+
+#define DDR_DMC_REMAP_DDR4_32BIT {\
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),\
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),\
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),\
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),\
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 31 << 25 ),\
+ }
+
+
+#define DDR_DMC_REMAP_DDR3_16BIT {\
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),\
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),\
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),\
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),\
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),\
+ }
+
+#define DDR_DMC_REMAP_DDR4_16BIT {\
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),\
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),\
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),\
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),\
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 30 << 25 ),\
+ }
+#define DDR_DMC_REMAP_LPDDR4_16BIT {\
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),\
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),\
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),\
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),\
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),\
+ }
+
+#define DDR_DMC_REMAP_LPDDR4_32BIT {\
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25 ),\
+ [1] = ( 11| 0 << 5 | 0 << 10 | 12 << 15 | 14 << 20 | 15 << 25 ),\
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),\
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),\
+ [4] = ( 0 | 13 << 5 | 16 << 10 | 20 << 15 | 0 << 20 | 0 << 25 ),\
+ }
+ //cs0 write bit0-1,cs0 read bit4-5,cs1 write bit 8-9,cs1 read bit 12-13
+#define DDR_DRAM_ODT_DISABLE 0
+#define DDR_DRAM_ODT_W_CS0_ODT0 0x1
+#define DDR_DRAM_ODT_W_CS0_ODT0_CS1_ODT1 0x201
+#define DDR_DRAM_ODT_W_CS0_ODT1_CS1_ODT0 0x102
+#define DDR_DRAM_ODT_W_CS0_ODT01_CS1_ODT01 0x303
+#define DDR_DRAM_ODT_W_CS0_ODT0_CS1_ODT1__R_CS0_ODT1_CS1_ODT0 0x1221
+#define DDR_DRAM_ODT_W_CS0_ODT1_CS1_ODT0__R_CS0_ODT1_CS1_ODT0 0x1122
+#define DDR_DRAM_ODT_W_CS0_ODT01_CS1_ODT01__R_CS0_ODT1_CS1_ODT0 0x1323
+#define DDR_DRAM_ODT_R_CS0_ODT1_CS1_ODT0 0x1020
+
+#define DDR_SOC_AC_DRV_0_OHM 0
+#define DDR_SOC_AC_DRV_120_OHM 120
+#define DDR_SOC_AC_DRV_60_OHM 60
+#define DDR_SOC_AC_DRV_40_OHM 40
+#define DDR_SOC_AC_DRV_30_OHM 30
+#define DDR_SOC_AC_DRV_24_OHM 24
+#define DDR_SOC_AC_DRV_20_OHM 20
+
+#define DDR_SOC_DATA_DRV_ODT_0_OHM 0
+#define DDR_SOC_DATA_DRV_ODT_240_OHM 240
+#define DDR_SOC_DATA_DRV_ODT_120_OHM 120
+#define DDR_SOC_DATA_DRV_ODT_80_OHM 80
+#define DDR_SOC_DATA_DRV_ODT_60_OHM 60
+#define DDR_SOC_DATA_DRV_ODT_48_OHM 48
+#define DDR_SOC_DATA_DRV_ODT_40_OHM 40
+#define DDR_SOC_DATA_DRV_ODT_34_OHM 34
+
+#define DDR_DRAM_DDR3_DRV_34_OHM 34
+#define DDR_DRAM_DDR3_DRV_40_OHM 40
+#define DDR_DRAM_DDR4_DRV_34_OHM 34
+#define DDR_DRAM_DDR4_DRV_48_OHM 48
+#define DDR_DRAM_LPDDR3_DRV_34_OHM 34
+#define DDR_DRAM_LPDDR3_DRV_40_OHM 40
+#define DDR_DRAM_LPDDR3_DRV_48_OHM 48
+#define DDR_DRAM_LPDDR4_DRV_40_OHM 40
+#define DDR_DRAM_LPDDR4_DRV_48_OHM 48
+#define DDR_DRAM_LPDDR4_DRV_60_OHM 60
+#define DDR_DRAM_LPDDR4_DRV_80_OHM 80
+#define DDR_DRAM_LPDDR4_DRV_120_OHM 120
+#define DDR_DRAM_LPDDR4_DRV_240_OHM 240
+
+#define DDR_DRAM_DDR3_ODT_0_OHM 0
+#define DDR_DRAM_DDR3_ODT_120_OHM 120
+#define DDR_DRAM_DDR3_ODT_60_OHM 60
+#define DDR_DRAM_DDR3_ODT_40_OHM 40
+#define DDR_DRAM_LPDDR3_ODT_0_OHM 0
+#define DDR_DRAM_LPDDR3_ODT_240_OHM 240
+#define DDR_DRAM_LPDDR3_ODT_120_OHM 120
+#define DDR_DRAM_LPDDR3_ODT_60_OHM 60
+#define DDR_DRAM_LPDDR4_ODT_0_OHM 0
+#define DDR_DRAM_LPDDR4_ODT_240_OHM 240
+#define DDR_DRAM_LPDDR4_ODT_120_OHM 120
+#define DDR_DRAM_LPDDR4_ODT_80_OHM 80
+#define DDR_DRAM_LPDDR4_ODT_60_OHM 60
+#define DDR_DRAM_LPDDR4_ODT_48_OHM 48
+#define DDR_DRAM_LPDDR4_ODT_40_OHM 40
+#define DDR_DRAM_DDR4_ODT_0_OHM 0
+#define DDR_DRAM_DDR4_ODT_34_OHM 34
+#define DDR_DRAM_DDR4_ODT_40_OHM 40
+#define DDR_DRAM_DDR4_ODT_48_OHM 48
+#define DDR_DRAM_DDR4_ODT_60_OHM 60
+#define DDR_DRAM_DDR4_ODT_80_OHM 80
+#define DDR_DRAM_DDR4_ODT_120_OHM 120
+#define DDR_DRAM_DDR4_ODT_240_OHM 240
+
+#define DDR_DRAM_DDR_WR_ODT_0_OHM 0
+#define DDR_DRAM_DDR3_WR_ODT_0_OHM 0
+#define DDR_DRAM_DDR3_WR_ODT_120_OHM 120
+#define DDR_DRAM_DDR3_WR_ODT_60_OHM 60
+#define DDR_DRAM_DDR4_WR_ODT_0_OHM 0
+#define DDR_DRAM_DDR4_WR_ODT_240_OHM 240
+#define DDR_DRAM_DDR4_WR_ODT_120_OHM 120
+#define DDR_DRAM_DDR4_WR_ODT_80_OHM 80
+
+#define DDR_DRAM_DDR_AC_ODT_0_OHM 0
+#define DDR_DRAM_LPDDR4_AC_ODT_0_OHM 0
+#define DDR_DRAM_LPDDR4_AC_ODT_240_OHM 240
+#define DDR_DRAM_LPDDR4_AC_ODT_120_OHM 120
+#define DDR_DRAM_LPDDR4_AC_ODT_80_OHM 80
+#define DDR_DRAM_LPDDR4_AC_ODT_60_OHM 60
+#define DDR_DRAM_LPDDR4_AC_ODT_48_OHM 48
+#define DDR_DRAM_LPDDR4_AC_ODT_40_OHM 40
+
+#define DDR_DRAM_LPDDR4_OUTPUT_2_5_VDDQ 0
+#define DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ 1
+
+#define DDR_SOC_READ_DQS_GATE_MODE_WINDOW_MODE_0_DDR3 1
+#define DDR_SOC_READ_DQS_GATE_MODE_WINDOW_MODE_1_DDR4 2
+#define DDR_SOC_READ_DQS_GATE_MODE_WINDOW_MODE_2_DDR4 3
+#define DDR_SOC_READ_DQS_GATE_MODE_WINDOW_MODE_3_LPDDR4 4
+
+#define DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR3 5
+#define DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR4 6
+#define DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_LPDDR4 7
+#define DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_3_LPDDR4 8
+
+#define DDR_SOC_READ_DQS_GATE_MODE_WIDE_MODE_RPULL_0_DDR3 9
+#define DDR_SOC_READ_DQS_GATE_MODE_WIDE_MODE_RPULL_1_LPDDR4 10
+
+#if 0
+#define DDR_SOC_READ_DQS_GATE_MODE_RPULL_WIDE_WINDOW 1
+
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_WINDOW_MODE_0 2
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_WINDOW_MODE_1 3
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_WINDOW_MODE_2 4
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_WINDOW_MODE_3 5
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_EDGE_MODE_0 6
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_EDGE_MODE_1 7
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_EDGE_MODE_2 8
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_EDGE_MODE_3 9
+
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_WINDOW_MODE_0 10
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_WINDOW_MODE_1 11
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_WINDOW_MODE_2 12
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_WINDOW_MODE_3 13
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_EDGE_MODE_0 14
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_EDGE_MODE_1 15
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_EDGE_MODE_2 16
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_EDGE_MODE_3 17
+
+#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_WINDOW_MODE_0 18
+#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_WINDOW_MODE_1 19
+#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_WINDOW_MODE_2 20
+#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_WINDOW_MODE_3 21
+#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_EDGE_MODE_0 22
+#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_EDGE_MODE_1 23
+#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_EDGE_MODE_2 24
+#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_EDGE_MODE_3 25
+#endif
diff --git a/arch/arm/include/asm/arch-c2/efuse.h b/arch/arm/include/asm/arch-c2/efuse.h
new file mode 100644
index 0000000..4a68e88
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/efuse.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __EFUSE_H
+#define __EFUSE_H
+
+#include <config.h>
+#include <common.h>
+
+/* efuse HAL_API arg */
+struct efuse_hal_api_arg {
+ unsigned int cmd; /* R/W */
+ unsigned int offset;
+ unsigned int size;
+ unsigned long buffer_phy;
+ unsigned long retcnt_phy;
+};
+
+
+#define EFUSE_BYTES 512 /* (EFUSE_BITS/8) */
+
+#define EFUSE_HAL_API_READ 0
+#define EFUSE_HAL_API_WRITE 1
+#define EFUSE_HAL_API_WRITE_PATTERN 2
+#define EFUSE_HAL_API_USER_MAX 3
+
+#define EFUSE_USER_MASK (0x1 << 16)
+#define EFUSE_THERMAL_MASK (0x1 << 17)
+#define EFUSE_THERMAL_VERFLAG_MASK (0x1 << 18)
+#define EFUSE_ENCRYPT_MASK (0x1 << 19)
+
+//#define ASSIST_HW_REV 0x1f53
+
+int efuse_read_usr(char *buf, size_t count, loff_t *ppos);
+int efuse_write_usr(char *buf, size_t count, loff_t *ppos);
+uint32_t efuse_get_max(void);
+ssize_t efuse_read(char *buf, size_t count, loff_t *ppos);
+ssize_t efuse_write(const char *buf, size_t count, loff_t *ppos);
+
+int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg);
+int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg);
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-c2/eth_setup.h b/arch/arm/include/asm/arch-c2/eth_setup.h
new file mode 100644
index 0000000..6e643f6
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/eth_setup.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/io.h>
+
+/*
+ *board configuration interface.
+ * */
+struct eth_clock_conf{
+ int enable;
+ int clock_50MHZ_phase;
+ //add ... as you need.
+};
+
+struct eth_board_socket{
+char *name ;
+int (*eth_clock_configure)(struct eth_clock_conf);
+int (*eth_pinmux_setup)(void);
+int (*eth_hw_reset)(void);
+
+};
+
+
+
+/*
+ *clock define part
+ */
+
+#define ETH_BASE (0xff3f0000)
+#define ETH_PLL_CNTL CBUS_REG_ADDR(0x2050)
+ /* Ethernet ctrl */
+#define ETH_PLL_CNTL_DIVEN (1<<0)
+#define ETH_PLL_CNTL_MACSPD (1<<1)
+#define ETH_PLL_CNTL_DATEND (1<<2)
+#define ETH_PLL_CNTL_DESEND (1<<3)
+
+
+/*
+ please refer following doc for detail
+ @AppNote-M3-ClockTrees.docx
+
+ select clk: -> CBUS_REG(0x1076)
+
+ 7-sys_pll_div2
+ 6-vid2_pll_clk
+ 5-vid_pll_clk
+ 4-aud_pll_clk
+ 3-ddr_pll_clk
+ 2-misc_pll_clk
+ 1-sys_pll_clk
+ 0-XTAL
+
+ clk_freq:800MHz
+ output_clk:50MHz
+ aways,maybe changed for others?
+*/
+
+#define ETH_CLKSRC_XTAL (0)
+#define ETH_CLKSRC_SYS_PLL_CLK (1)
+#define ETH_CLKSRC_MISC_PLL_CLK (2)
+#define ETH_CLKSRC_DDR_PLL_CLK (3)
+#define ETH_CLKSRC_AUD_PLL_CLK (
+#define ETH_CLKSRC_VID_PLL_CLK (5)
+#define ETH_CLKSRC_VID2_PLL_CLK (6)
+#define ETH_CLKSRC_SYS_PLL_DIV2_CLK (7)
+#define CLK_1M (1000000)
+
+typedef union eth_aml_reg0 {
+ /** raw register data */
+ unsigned int d32;
+ /** register bits */
+ struct {
+ unsigned phy_intf_sel:3;
+ unsigned rx_clk_rmii_invert:1;
+ unsigned rgmii_tx_clk_src:1;
+ unsigned rgmii_tx_clk_phase:2;
+ unsigned rgmii_tx_clk_ratio:3;
+ unsigned phy_ref_clk_enable:1;
+ unsigned clk_rmii_i_invert:1;
+ unsigned clk_en:1;
+ unsigned adj_enable:1;
+ unsigned adj_setup:1;
+ unsigned adj_delay:5;
+ unsigned adj_skew:5;
+ unsigned cali_start:1;
+ unsigned cali_rise:1;
+ unsigned cali_sel:3;
+ unsigned rgmii_rx_reuse:1;
+ unsigned eth_urgent:1;
+ } b;
+} eth_aml_reg0_t;
+
+#define ETH_VALIDE_CLKSRC(clk,out_clk) ((clk%out_clk)==0)
+
+int eth_clk_set(int selectclk,unsigned long clk_freq,unsigned long out_clk);
+
diff --git a/arch/arm/include/asm/arch-c2/gpio.h b/arch/arm/include/asm/arch-c2/gpio.h
new file mode 100644
index 0000000..2467368
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/gpio.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_ARCH_MESON_GPIO_H
+#define __ASM_ARCH_MESON_GPIO_H
+
+
+#endif /* __ASM_ARCH_MESON_GPIO_H */
diff --git a/arch/arm/include/asm/arch-c2/i2c.h b/arch/arm/include/asm/arch-c2/i2c.h
new file mode 100644
index 0000000..a93a09d
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/i2c.h
@@ -0,0 +1,280 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AML_MACH_I2C__
+#define __AML_MACH_I2C__
+
+#include <asm/io.h>
+#include <asm/arch/secure_apb.h>
+
+/**
+ * struct i2c_msg - an I2C transaction segment beginning with START
+ * @addr: Slave address, either seven or ten bits. When this is a ten
+ * bit address, I2C_M_TEN must be set in @flags and the adapter
+ * must support I2C_FUNC_10BIT_ADDR.
+ * @flags: I2C_M_RD is handled by all adapters. No other flags may be
+ * provided unless the adapter exported the relevant I2C_FUNC_*
+ * flags through i2c_check_functionality().
+ * @len: Number of data bytes in @buf being read from or written to the
+ * I2C slave address. For read transactions where I2C_M_RECV_LEN
+ * is set, the caller guarantees that this buffer can hold up to
+ * 32 bytes in addition to the initial length byte sent by the
+ * slave (plus, if used, the SMBus PEC); and this value will be
+ * incremented by the number of block data bytes received.
+ * @buf: The buffer into which data is read, or from which it's written.
+ *
+ * An i2c_msg is the low level representation of one segment of an I2C
+ * transaction. It is visible to drivers in the @i2c_transfer() procedure,
+ * to userspace from i2c-dev, and to I2C adapter drivers through the
+ * @i2c_adapter.@master_xfer() method.
+ *
+ * Except when I2C "protocol mangling" is used, all I2C adapters implement
+ * the standard rules for I2C transactions. Each transaction begins with a
+ * START. That is followed by the slave address, and a bit encoding read
+ * versus write. Then follow all the data bytes, possibly including a byte
+ * with SMBus PEC. The transfer terminates with a NAK, or when all those
+ * bytes have been transferred and ACKed. If this is the last message in a
+ * group, it is followed by a STOP. Otherwise it is followed by the next
+ * @i2c_msg transaction segment, beginning with a (repeated) START.
+ *
+ * Alternatively, when the adapter supports I2C_FUNC_PROTOCOL_MANGLING then
+ * passing certain @flags may have changed those standard protocol behaviors.
+ * Those flags are only for use with broken/nonconforming slaves, and with
+ * adapters which are known to support the specific mangling options they
+ * need (one or more of IGNORE_NAK, NO_RD_ACK, NOSTART, and REV_DIR_ADDR).
+ */
+struct i2c_msg {
+ __u16 addr; /* slave address */
+ __u16 flags;
+#define I2C_M_TEN 0x0010 /* this is a ten bit chip address */
+#define I2C_M_RD 0x0001 /* read data, from slave to master */
+#define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_NO_RD_ACK 0x0800 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_RECV_LEN 0x0400 /* length will be first received byte */
+ __u16 len; /* msg length */
+ __u8 *buf; /* pointer to msg data */
+};
+
+#define MESON_I2C_MASTER_AO_START (AO_I2C_M_0_CONTROL_REG)
+//#define MESON_I2C_MASTER_AO_END (0xc810051c+5)
+
+#define MESON_I2C_MASTER_A_START CBUS_REG_ADDR(I2C_M_0_CONTROL_REG)
+#define MESON_I2C_MASTER_A_END (CBUS_REG_ADDR(I2C_M_0_RDATA_REG1+1)-1)
+
+#define MESON_I2C_MASTER_B_START CBUS_REG_ADDR(I2C_M_1_CONTROL_REG)
+#define MESON_I2C_MASTER_B_END (CBUS_REG_ADDR(I2C_M_1_RDATA_REG1+1)-1)
+
+#define MESON_I2C_MASTER_C_START CBUS_REG_ADDR(I2C_M_2_CONTROL_REG)
+#define MESON_I2C_MASTER_C_END (CBUS_REG_ADDR(I2C_M_2_RDATA_REG1+1)-1)
+
+#define MESON_I2C_MASTER_D_START CBUS_REG_ADDR(I2C_M_3_CONTROL_REG)
+#define MESON_I2C_MASTER_D_END (CBUS_REG_ADDR(I2C_M_3_RDATA_REG1+1)-1)
+
+#define MESON_I2C_SLAVE_START CBUS_REG_ADDR(I2C_S_CONTROL_REG)
+#define MESON_I2C_SLAVE_END (CBUS_REG_ADDR(I2C_S_CNTL1_REG+1)-1)
+
+
+#define AML_I2C_MASTER_AO 0
+#define AML_I2C_MASTER_A 1
+#define AML_I2C_MASTER_B 2
+#define AML_I2C_MASTER_C 3
+#define AML_I2C_MASTER_D 4
+
+
+#define AML_I2C_SLAVE_ADDR 0x6c
+
+/*M1 i2c pinmux
+ * I/O I2C_MASTER_A I2C_MASTER_B I2C_SLAVE
+ * GPIO_JTAG_TMS SCK_A REG1[12] SCK_A REG1[13]
+ * GPIO_JTAG_TDI SDA_A REG1[12] SDA_A REG1[13]
+ * GPIO_JTAG_TCK SCK_B REG1[16] SCK_A REG1[17]
+ * GPIO_JTAG_TDO SDA_B REG1[20] SDA_A REG1[21]
+ * GPIOB_0 SCK_B REG2[5] SCK_A REG2[6]
+ * GPIOB_1 SDA_B REG2[2] SDA_A REG2[3]
+ * GPIOB_2 SCK_A REGS[13] SCK_A REG2[14]
+ * GPIOB_3 SDA_A REG2[9] SDA_A REG2[10]
+ * GPIOC_13 SCK_B REG3[28] SCK_A REG3[29]
+ * GPIOC_14 SDA_B REG3[25] SDA_A REG3[26]
+ * GPIOC_21 SCK_A REG7[9] SCK_A REG7[10]
+ * GPIOC_22 SDA_A REG7[6] SDA_A REG7[7]
+ * GPIOE_16 SCK_B REG5[27] SCK_A REG5[28]
+ * GPIOE_17 SDA_B REG5[25] SDA_A REG5[26]
+*/
+
+/*i2c master a*/
+
+
+#define MESON_I2C_MASTER_A_GPIOZ_17_REG (PERIPHS_PIN_MUX_9)
+#define MESON_I2C_MASTER_A_GPIOZ_17_BIT (1<<7)
+#define MESON_I2C_MASTER_A_GPIOZ_18_REG (PERIPHS_PIN_MUX_9)
+#define MESON_I2C_MASTER_A_GPIOZ_18_BIT (1<<8)
+
+#define MESON_I2C_MASTER_A_GPIOW_0_REG (PERIPHS_PIN_MUX_5)
+#define MESON_I2C_MASTER_A_GPIOW_0_BIT (1<<22)
+#define MESON_I2C_MASTER_A_GPIOW_1_REG (PERIPHS_PIN_MUX_5)
+#define MESON_I2C_MASTER_A_GPIOW_1_BIT (1<<23)
+
+/*i2c master b*/
+
+
+#define MESON_I2C_MASTER_B_GPIOH_3_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_B_GPIOH_3_BIT (1<<6)
+#define MESON_I2C_MASTER_B_GPIOH_4_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_B_GPIOH_4_BIT (1<<7)
+
+#define MESON_I2C_MASTER_B_GPIOY_12_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_B_GPIOY_12_BIT (1<<14)
+#define MESON_I2C_MASTER_B_GPIOY_13_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_B_GPIOY_13_BIT (1<<15)
+
+/*i2c master c*/
+#define MESON_I2C_MASTER_C_GPIOY_7_REG (PERIPHS_PIN_MUX_4)
+#define MESON_I2C_MASTER_C_GPIOY_7_BIT (1<<28)
+#define MESON_I2C_MASTER_C_GPIOY_8_REG (PERIPHS_PIN_MUX_4)
+#define MESON_I2C_MASTER_C_GPIOY_8_BIT (1<<29)
+
+#define MESON_I2C_MASTER_C_GPIOX_0_REG (PERIPHS_PIN_MUX_1)
+#define MESON_I2C_MASTER_C_GPIOX_0_BIT (1<<22)
+#define MESON_I2C_MASTER_C_GPIOX_1_REG (PERIPHS_PIN_MUX_1)
+#define MESON_I2C_MASTER_C_GPIOX_1_BIT (1<<23)
+
+/*i2c master d*/
+
+
+#define MESON_I2C_MASTER_D_GPIOY_10_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_D_GPIOY_10_BIT (1<<10)
+#define MESON_I2C_MASTER_D_GPIOY_11_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_D_GPIOY_11_BIT (1<<11)
+
+#define MESON_I2C_MASTER_D_GPIOH_5_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_D_GPIOH_5_BIT (1<<23)
+#define MESON_I2C_MASTER_D_GPIOH_6_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_D_GPIOH_6_BIT (1<<24)
+
+/*i2c master AO*/
+
+
+#define MESON_I2C_MASTER_AO_GPIOAO_4_REG (P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */
+#define MESON_I2C_MASTER_AO_GPIOAO_4_BIT (1<<8)
+#define MESON_I2C_MASTER_AO_GPIOAO_5_REG (P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */
+#define MESON_I2C_MASTER_AO_GPIOAO_5_BIT (1<<9)
+
+/*i2c slave*/
+#define MESON_I2C_SLAVE_JTAG_TMS_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TMS_BIT (1<<13)
+#define MESON_I2C_SLAVE_JTAG_TDI_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TDI_BIT (1<<13)
+
+#define MESON_I2C_SLAVE_GPIOB_2_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_2_BIT (1<<14)
+#define MESON_I2C_SLAVE_GPIOB_3_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_3_BIT (1<<10)
+
+#define MESON_I2C_SLAVE_GPIOC_21_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_7)
+#define MESON_I2C_SLAVE_GPIOC_21_BIT (1<<10)
+#define MESON_I2C_SLAVE_GPIOC_22_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_7)
+#define MESON_I2C_SLAVE_GPIOC_22_BIT (1<<7)
+
+#define MESON_I2C_SLAVE_JTAG_TCK_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TCK_BIT (1<<17)
+#define MESON_I2C_SLAVE_JTAG_TDO_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TDO_BIT (1<<21)
+
+#define MESON_I2C_SLAVE_GPIOB_0_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_0_BIT (1<<6)
+#define MESON_I2C_SLAVE_GPIOB_1_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_1_BIT (1<<3)
+
+#define MESON_I2C_SLAVE_GPIOC_13_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_3)
+#define MESON_I2C_SLAVE_GPIOC_13_BIT (1<<29)
+#define MESON_I2C_SLAVE_GPIOC_14_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_3)
+#define MESON_I2C_SLAVE_GPIOC_14_BIT (1<<26)
+
+#define MESON_I2C_SLAVE_GPIOC_16_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_5)
+#define MESON_I2C_SLAVE_GPIOC_16_BIT (1<<28)
+#define MESON_I2C_SLAVE_GPIOC_17_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_5)
+#define MESON_I2C_SLAVE_GPIOC_17_BIT (1<<26)
+
+
+#define AML_I2C_SPPED_50K 50000
+#define AML_I2C_SPPED_100K 100000
+#define AML_I2C_SPPED_200K 200000
+#define AML_I2C_SPPED_300K 300000
+#define AML_I2C_SPPED_400K 400000
+
+struct aml_pinmux_reg_bit {
+ unsigned long scl_reg;
+ unsigned long sda_reg;
+ unsigned int scl_bit;
+ unsigned int sda_bit;
+};
+
+struct aml_i2c_platform{
+ unsigned int slave_addr;/*7bit addr*/
+ unsigned int wait_count;/*i2c wait ack timeout =
+ wait_count * wait_ack_interval */
+ unsigned int wait_ack_interval;
+ unsigned int wait_read_interval;
+ unsigned int wait_xfer_interval;
+ unsigned int master_no;
+ unsigned int use_pio;/*0: hardware i2c, 1: manual pio i2c*/
+ unsigned int master_i2c_speed;
+
+ /* only need 1 i2c master to comunicate with several devices,
+ * should I prepare 2 master interface to use simultaneously?*/
+ struct resource * resource;
+ struct aml_pinmux_reg_bit master_ao_pinmux;
+ struct aml_pinmux_reg_bit master_a_pinmux;
+ struct aml_pinmux_reg_bit master_b_pinmux;
+ struct aml_pinmux_reg_bit master_c_pinmux;
+ struct aml_pinmux_reg_bit master_d_pinmux;
+
+ struct aml_pinmux_reg_bit slave_reg_bit;
+};
+
+/**************i2c software gpio***************/
+
+#define MESON_I2C_PREG_GPIOC_OE CBUS_REG_ADDR(PREG_FGPIO_EN_N)
+#define MESON_I2C_PREG_GPIOC_OUTLVL CBUS_REG_ADDR(PREG_FGPIO_O)
+#define MESON_I2C_PREG_GPIOC_INLVL CBUS_REG_ADDR(PREG_FGPIO_I)
+
+#define MESON_I2C_PREG_GPIOE_OE CBUS_REG_ADDR(PREG_HGPIO_EN_N)
+#define MESON_I2C_PREG_GPIOE_OUTLVL CBUS_REG_ADDR(PREG_HGPIO_O)
+#define MESON_I2C_PREG_GPIOE_INLVL CBUS_REG_ADDR(PREG_HGPIO_I)
+
+#define MESON_I2C_PREG_GPIOA_OE CBUS_REG_ADDR(PREG_EGPIO_EN_N)
+#define MESON_I2C_PREG_GPIOA_OUTLVL CBUS_REG_ADDR(PREG_EGPIO_O)
+#define MESON_I2C_PREG_GPIOA_INLVL CBUS_REG_ADDR(PREG_EGPIO_I)
+
+struct aml_sw_i2c_pins
+{
+ unsigned int scl_reg_out;
+ unsigned int scl_reg_in;
+ unsigned int scl_bit;
+ unsigned int scl_oe;
+ unsigned int sda_reg_out;
+ unsigned int sda_reg_in;
+ unsigned int sda_bit;
+ unsigned int sda_oe;
+};
+
+
+struct aml_sw_i2c_platform {
+ struct aml_sw_i2c_pins sw_pins;
+
+ /* local settings */
+ int udelay; /* half clock cycle time in us,
+ minimum 2 us for fast-mode I2C,
+ minimum 5 us for standard-mode I2C and SMBus,
+ maximum 50 us for SMBus */
+ int timeout; /* in jiffies */
+};
+
+
+#endif //__AML_MACH_I2C__
+
+
diff --git a/arch/arm/include/asm/arch-c2/io.h b/arch/arm/include/asm/arch-c2/io.h
new file mode 100644
index 0000000..fd3981a
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/io.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __MACH_MESSON_REGS_IO_H
+#define __MACH_MESSON_REGS_IO_H
+
+#ifndef __ASSEMBLY__
+
+#include <asm/io.h>
+#define IO_CBUS_BASE (0xFFD00000L)
+#define IO_AXI_BUS_BASE (0xFFB00000L) /* gpv */
+#define IO_AHB_BUS_BASE (0xFF500000L) /* usb0 */
+#define IO_APB_BUS_BASE (0xFFFC0000L) /* AHB SRAM, sec/sys ahb? txlx_mem_map.xlsx */
+#define IO_APB_HDMI_BUS_BASE (0xFFE00000L) /* */
+#define IO_VPU_BUS_BASE (0xFF900000L) /* VPU */
+
+#define CBUS_REG_OFFSET(reg) ((reg) << 2)
+#define CBUS_REG_ADDR(reg) (IO_CBUS_BASE + CBUS_REG_OFFSET(reg))
+
+#define AXI_REG_OFFSET(reg) ((reg) << 2)
+#define AXI_REG_ADDR(reg) (IO_AXI_BUS_BASE + AXI_REG_OFFSET(reg))
+
+#define AHB_REG_OFFSET(reg) ((reg) << 2)
+#define AHB_REG_ADDR(reg) (IO_AHB_BUS_BASE + AHB_REG_OFFSET(reg))
+
+#define VPU_REG_OFFSET(reg) ((reg) << 2)
+#define VPU_REG_ADDR(reg) (IO_VPU_BUS_BASE + VPU_REG_OFFSET(reg))
+
+
+#define APB_REG_OFFSET(reg) (reg)
+#define APB_REG_ADDR(reg) (IO_APB_BUS_BASE + APB_REG_OFFSET(reg))
+#define APB_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0)
+
+#define APB_HDMI_REG_OFFSET(reg) (reg)
+#define APB_HDMI_REG_ADDR(reg) (IO_APB_HDMI_BUS_BASE + APB_HDMI_REG_OFFSET(reg))
+#define APB_HDMI_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0)
+
+
+#define WRITE_CBUS_REG(reg, val) __raw_writel(val, CBUS_REG_ADDR(reg))
+#define READ_CBUS_REG(reg) (__raw_readl(CBUS_REG_ADDR(reg)))
+#define WRITE_CBUS_REG_BITS(reg, val, start, len) \
+ WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_CBUS_REG_BITS(reg, start, len) \
+ ((READ_CBUS_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)&(~(mask))))
+#define SET_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)|(mask)))
+
+#define WRITE_AXI_REG(reg, val) __raw_writel(val, AXI_REG_ADDR(reg))
+#define READ_AXI_REG(reg) (__raw_readl(AXI_REG_ADDR(reg)))
+#define WRITE_AXI_REG_BITS(reg, val, start, len) \
+ WRITE_AXI_REG(reg, (READ_AXI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_AXI_REG_BITS(reg, start, len) \
+ ((READ_AXI_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)&(~(mask))))
+#define SET_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)|(mask)))
+
+#define WRITE_AHB_REG(reg, val) __raw_writel(val, AHB_REG_ADDR(reg))
+#define READ_AHB_REG(reg) (__raw_readl(AHB_REG_ADDR(reg)))
+#define WRITE_AHB_REG_BITS(reg, val, start, len) \
+ WRITE_AHB_REG(reg, (READ_AHB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_AHB_REG_BITS(reg, start, len) \
+ ((READ_AHB_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)&(~(mask))))
+#define SET_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)|(mask)))
+
+#define WRITE_APB_REG(reg, val) __raw_writel(val, APB_REG_ADDR(reg))
+#define READ_APB_REG(reg) (__raw_readl(APB_REG_ADDR(reg)))
+#define WRITE_APB_REG_BITS(reg, val, start, len) \
+ WRITE_APB_REG(reg, (READ_APB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_APB_REG_BITS(reg, start, len) \
+ ((READ_APB_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)&(~(mask))))
+#define SET_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)|(mask)))
+
+#define WRITE_APB_HDMI_REG(reg, val) __raw_writel(val, APB_HDMI_REG_ADDR(reg))
+#define READ_APB_HDMI_REG(reg) (__raw_readl(APB_HDMI_REG_ADDR(reg)))
+#define WRITE_APB_HDMI_REG_BITS(reg, val, start, len) \
+ WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_APB_HDMI_REG_BITS(reg, start, len) \
+ ((READ_APB_HDMI_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)&(~(mask))))
+#define SET_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)|(mask)))
+
+/* for back compatible alias */
+#define WRITE_MPEG_REG(reg, val) \
+ WRITE_CBUS_REG(reg, val)
+#define READ_MPEG_REG(reg) \
+ READ_CBUS_REG(reg)
+#define WRITE_MPEG_REG_BITS(reg, val, start, len) \
+ WRITE_CBUS_REG_BITS(reg, val, start, len)
+#define READ_MPEG_REG_BITS(reg, start, len) \
+ READ_CBUS_REG_BITS(reg, start, len)
+#define CLEAR_MPEG_REG_MASK(reg, mask) \
+ CLEAR_CBUS_REG_MASK(reg, mask)
+#define SET_MPEG_REG_MASK(reg, mask) \
+ SET_CBUS_REG_MASK(reg, mask)
+#endif
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-c2/mailbox.h b/arch/arm/include/asm/arch-c2/mailbox.h
new file mode 100644
index 0000000..04ae20f
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/mailbox.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+ /*
+ *
+ * Copyright (C) 2012 Amlogic, Inc.
+ *
+ * Author: Platform-SH@amlogic.com
+ *
+ */
+
+#ifndef __GXBB_MAILBOX_H_
+#define __GXBB_MAILBOX_H_
+
+#define SCPI_CMD_SENSOR_VALUE 0x1C
+#define SCPI_CMD_SET_USR_DATA 0x20
+#define SCPI_CMD_OPEN_SCP_LOG 0xC4
+#define SCPI_CMD_THERMAL_CALIB 0xC5
+
+#define SCPI_CMD_USB_BOOT 0xB0
+#define SCPI_CMD_USB_UNBOOT 0xB1
+#define SCPI_CMD_SDCARD_BOOT 0xB2
+#define SCPI_CMD_CLEAR_BOOT 0xB3
+
+#define SCPI_CMD_REV_PWM_DELT 0x42
+
+#define LOW_PRIORITY 0
+#define HIGH_PRIORITY 1
+
+#define P_SHARE_SRAM_BASE 0xfffa0000
+#define SRAM_SIZE 0x48000
+#define MHU_HIGH_SCP_TO_AP_PAYLOAD (SRAM_SIZE - 0xc00)
+#define MHU_HIGH_AP_TO_SCP_PAYLOAD (MHU_HIGH_SCP_TO_AP_PAYLOAD + 0x200)
+#define MHU_LOW_SCP_TO_AP_PAYLOAD (SRAM_SIZE - 0x1000)
+#define MHU_LOW_AP_TO_SCP_PAYLOAD (MHU_LOW_SCP_TO_AP_PAYLOAD + 0x200)
+
+enum scpi_client_id {
+ SCPI_CL_NONE,
+ SCPI_CL_CLOCKS,
+ SCPI_CL_DVFS,
+ SCPI_CL_POWER,
+ SCPI_CL_THERMAL,
+ SCPI_CL_REMOTE,
+ SCPI_CL_LED_TIMER,
+ SCPI_MAX = 0xff,
+};
+
+enum scpi_error_codes {
+ SCPI_SUCCESS = 0, /* Success */
+ SCPI_ERR_PARAM = 1, /* Invalid parameter(s) */
+ SCPI_ERR_ALIGN = 2, /* Invalid alignment */
+ SCPI_ERR_SIZE = 3, /* Invalid size */
+ SCPI_ERR_HANDLER = 4, /* Invalid handler/callback */
+ SCPI_ERR_ACCESS = 5, /* Invalid access/permission denied */
+ SCPI_ERR_RANGE = 6, /* Value out of range */
+ SCPI_ERR_TIMEOUT = 7, /* Timeout has occurred */
+ SCPI_ERR_NOMEM = 8, /* Invalid memory area or pointer */
+ SCPI_ERR_PWRSTATE = 9, /* Invalid power state */
+ SCPI_ERR_SUPPORT = 10, /* Not supported or disabled */
+ SCPI_ERR_DEVICE = 11, /* Device error */
+ SCPI_ERR_MAX
+};
+
+void open_scp_log(unsigned int channel);
+int thermal_calibration(unsigned int type, unsigned int data);
+int thermal_get_value(unsigned int sensor_id, unsigned int *value);
+int send_usr_data(unsigned int clinet_id, unsigned int *val, unsigned int size);
+void send_pwm_delt(int32_t vcck_delt, int32_t ee_delt);
+ #endif
diff --git a/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_ddr3.h b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_ddr3.h
new file mode 100644
index 0000000..c067367
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_ddr3.h
@@ -0,0 +1,637 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief DDR3U_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_DDR3U_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Train vrefDAC0 During Read Deskew
+ // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] = MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] = SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] = SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] = RFU, must be zero (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero)
+ //
+ //
+ //
+ // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] = PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte
+ // 0x0 = All rank populated with all the byte (tyical configuration)
+ //
+ // MsgMisc[7] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware.
+ // Please reference this revision ID when filing support cases with Synopsys.
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Module Type:
+ // 0x01 = DDR3 unbuffered
+ // 0x02 = Reserved
+ // 0x03 = Reserved
+ // 0x04 = Reserved
+ // 0x05 = Reserved
+ //
+ uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7):
+ // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting)
+ uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ // Total number of DQ bits enabled in PHY
+ uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS.
+ //
+ // If the bit is set to 1, the CS is connected to DRAM.
+ // If the bit is set to 0, the CS is not connected to DRAM.
+ //
+ // CsPresent[0] = CS0 is populated with DRAM
+ // CsPresent[1] = CS1 is populated with DRAM
+ // CsPresent[2] = CS2 is populated with DRAM
+ // CsPresent[3] = CS3 is populated with DRAM
+ // CsPresent[7:4] = Reserved (must be programmed to 0)
+ //
+ //
+ uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 0
+ uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 1
+ uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ // Corresponds to CS[3:0]
+ // 1 = Address Mirror.
+ // 0 = No Address Mirror.
+ uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ // Additional mode bits.
+ //
+ // Bit fields:
+ // [0] SlowAccessMode :
+ // 1 = 2T Address Timing.
+ // 0 = 1T Address Timing.
+ // [7-1] RFU, must be zero
+ uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[10] = RFU, must be zero
+ // SequenceCtrl[11] = RFU, must be zero
+ // SequenceCtrl[12] = RFU, must be zero
+ // SequenceCtrl[13] = RFU, must be zero
+ // SequenceCtrl[15-14] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A
+
+
+
+ uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D training in: Rd2D, Wr2D
+ //
+ // Reserved1E[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1E[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR6
+ // 2 = limit to +/-4 %VDDQ from MR6
+ // …
+ // 15 = limit to +/-30% VDDQ from MR6
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A
+ // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset.
+ uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ // Value of DDR mode register MR0 for all ranks for current pstate
+ uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Value of DDR mode register MR1 for all ranks for current pstate
+ uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ // Value of DDR mode register MR2 for all ranks for current pstate
+ uint8_t Reserved64; // Byte offset 0x64, CSR Addr 0x54032, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved65; // Byte offset 0x65, CSR Addr 0x54032, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6E; // Byte offset 0x6e, CSR Addr 0x54037, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6F; // Byte offset 0x6f, CSR Addr 0x54037, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved71; // Byte offset 0x71, CSR Addr 0x54038, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved72; // Byte offset 0x72, CSR Addr 0x54039, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved73; // Byte offset 0x73, CSR Addr 0x54039, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl0; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl2; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl3; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl4; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl5; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl7; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7C; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7D; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A
+
+ uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A
+
+ uint8_t Reserved8A; // Byte offset 0x8a, CSR Addr 0x54045, Direction=N/A
+
+ uint8_t Reserved8B; // Byte offset 0x8b, CSR Addr 0x54045, Direction=N/A
+
+ uint8_t Reserved8C; // Byte offset 0x8c, CSR Addr 0x54046, Direction=N/A
+
+ uint8_t Reserved8D; // Byte offset 0x8d, CSR Addr 0x54046, Direction=N/A
+
+ uint8_t Reserved8E; // Byte offset 0x8e, CSR Addr 0x54047, Direction=N/A
+
+ uint8_t Reserved8F; // Byte offset 0x8f, CSR Addr 0x54047, Direction=N/A
+
+ uint8_t Reserved90; // Byte offset 0x90, CSR Addr 0x54048, Direction=N/A
+
+ uint8_t Reserved91; // Byte offset 0x91, CSR Addr 0x54048, Direction=N/A
+
+ uint8_t Reserved92; // Byte offset 0x92, CSR Addr 0x54049, Direction=N/A
+
+ uint8_t Reserved93; // Byte offset 0x93, CSR Addr 0x54049, Direction=N/A
+
+ uint8_t Reserved94; // Byte offset 0x94, CSR Addr 0x5404a, Direction=N/A
+
+ uint8_t Reserved95; // Byte offset 0x95, CSR Addr 0x5404a, Direction=N/A
+
+ uint8_t Reserved96; // Byte offset 0x96, CSR Addr 0x5404b, Direction=N/A
+
+ uint8_t Reserved97; // Byte offset 0x97, CSR Addr 0x5404b, Direction=N/A
+
+ uint8_t Reserved98; // Byte offset 0x98, CSR Addr 0x5404c, Direction=N/A
+
+ uint8_t Reserved99; // Byte offset 0x99, CSR Addr 0x5404c, Direction=N/A
+
+ uint8_t Reserved9A; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=N/A
+
+ uint8_t Reserved9B; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=N/A
+
+ uint8_t Reserved9C; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=N/A
+
+ uint8_t Reserved9D; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=N/A
+
+ uint8_t Reserved9E; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=N/A
+
+ uint8_t Reserved9F; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=N/A
+
+ uint8_t ReservedA0; // Byte offset 0xa0, CSR Addr 0x54050, Direction=N/A
+
+ uint8_t ReservedA1; // Byte offset 0xa1, CSR Addr 0x54050, Direction=N/A
+
+ uint8_t ReservedA2; // Byte offset 0xa2, CSR Addr 0x54051, Direction=N/A
+
+ uint8_t ReservedA3; // Byte offset 0xa3, CSR Addr 0x54051, Direction=N/A
+
+} __attribute__ ((packed)) PMU_SMB_DDR3U_1D_t;
diff --git a/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_ddr4.h b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_ddr4.h
new file mode 100644
index 0000000..6dfd4d0
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_ddr4.h
@@ -0,0 +1,2380 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief DDR4U_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_DDR4U_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Train vrefDAC0 During Read Deskew
+ // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] = MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] = SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] = SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D.
+ // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field
+ //
+ // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] = PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte
+ // 0x0 = All rank populated with all the byte (tyical configuration)
+ //
+ // MsgMisc[7] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware.
+ // Please reference this revision ID when filing support cases with Synopsys.
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Module Type:
+ // 0x01 = Reserved
+ // 0x02 = DDR4 unbuffered
+ // 0x03 = Reserved
+ // 0x04 = Reserved
+ // 0x05 = Reserved
+ //
+ uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7):
+ // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting)
+ uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ // Total number of DQ bits enabled in PHY
+ uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS.
+ //
+ // If the bit is set to 1, the CS is connected to DRAM.
+ // If the bit is set to 0, the CS is not connected to DRAM.
+ //
+ // CsPresent[0] = CS0 is populated with DRAM
+ // CsPresent[1] = CS1 is populated with DRAM
+ // CsPresent[2] = CS2 is populated with DRAM
+ // CsPresent[3] = CS3 is populated with DRAM
+ // CsPresent[7:4] = Reserved (must be programmed to 0)
+ //
+ //
+ uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 0
+ uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 1
+ uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ // Corresponds to CS[3:0]
+ // 1 = Address Mirror.
+ // 0 = No Address Mirror.
+ uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ // Additional mode bits.
+ //
+ // Bit fields:
+ // [0] SlowAccessMode :
+ // 1 = 2T Address Timing.
+ // 0 = 1T Address Timing.
+ // [7-1] RFU, must be zero
+ uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[10] = Run Reserved
+ // SequenceCtrl[11] = Run Reserved
+ // SequenceCtrl[12] = Run Reserved
+ // SequenceCtrl[13] = Run Reserved
+ // SequenceCtrl[15-14] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A
+
+
+
+ uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D training in: Rd2D, Wr2D
+ //
+ // Reserved1E[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1E[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR6
+ // 2 = limit to +/-4 %VDDQ from MR6
+ // …
+ // 15 = limit to +/-30% VDDQ from MR6
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A
+ // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset.
+ uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ // Value of DDR mode register MR0 for all ranks for current pstate
+ uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Value of DDR mode register MR1 for all ranks for current pstate
+ uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ // Value of DDR mode register MR2 for all ranks for current pstate
+ uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ // Value of DDR mode register MR3 for all ranks for current pstate
+ uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value of DDR mode register MR4 for all ranks for current pstate
+ uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value of DDR mode register MR5 for all ranks for current pstate
+ uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0.
+ uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // X16 device map. Corresponds to CS[3:0].
+ // X16Present[0] = CS0 is populated with X16 devices
+ // X16Present[1] = CS1 is populated with X16 devices
+ // X16Present[2] = CS2 is populated with X16 devices
+ // X16Present[3] = CS3 is populated with X16 devices
+ // X16Present[7:4] = Reserved (must be programmed to 0)
+ //
+ // Ranks may not contain mixed device types.
+ uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // controls timing of chip select signals when DDR4 gear-down mode is active
+ // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs
+ // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode
+ uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM:
+ // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0
+ // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0
+ // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0
+ uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM:
+ // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1
+ // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1
+ // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1
+ uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM:
+ // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2
+ // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2
+ // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2
+ uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM:
+ // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3
+ // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3
+ // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3
+ uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM:
+ // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4
+ // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4
+ // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4
+ uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM:
+ // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5
+ // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5
+ // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5
+ uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM:
+ // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6
+ // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6
+ // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6
+ uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM:
+ // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7
+ // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7
+ // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7
+ uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices.
+ uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices.
+ uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices.
+ uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices.
+ uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices.
+ uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices.
+ uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices.
+ uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices.
+ uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices.
+ uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices.
+ uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices.
+ uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices.
+ uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices.
+ uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices.
+ uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices.
+ uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices.
+ uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices.
+ uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices.
+ uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices.
+ uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices.
+ uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices.
+ uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices.
+ uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices.
+ uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices.
+ uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices.
+ uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices.
+ uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices.
+ uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices.
+ uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices.
+ uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices.
+ uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices.
+ uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices.
+ uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices.
+ uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices.
+ uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices.
+ uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices.
+ uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices.
+ uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices.
+ uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices.
+ uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices.
+ uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A
+
+ uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A
+
+ uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in
+ // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1).
+ // RdDBI is dynamically disabled in certain training steps,
+ // and so the [RdDBI disabled] CAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_CAS_L[0] == 0: use value in MR0
+ // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2]
+ // Other bits are ignored
+ uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In
+ // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1).
+ // 2tCK write prambles are dynamically disabled in certain training steps,
+ // and so the [1tCK write preamble] WCAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_WCAS_L[0] == 0: use value in MR2
+ // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3]
+ // Other bits are ignored
+ uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In
+ // Contains various options for training DDR4 Devices.
+ //
+ // Bit fields:
+ //
+ // D4Misc[7:1] RFU, must be zero
+ //
+ // D4Misc[0] = protect memory reset
+ // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training.
+ // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training
+} __attribute__ ((packed)) PMU_SMB_DDR4U_1D_t;
diff --git a/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_ddr4_2d.h b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_ddr4_2d.h
new file mode 100644
index 0000000..35b1e23
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_ddr4_2d.h
@@ -0,0 +1,2282 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief DDR4U_2D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_DDR4U_2D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Train vrefDAC0 During Read Deskew
+ // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] = MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] = SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] = SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D.
+ // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field
+ //
+ // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] = PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte
+ // 0x0 = All rank populated with all the byte (tyical configuration)
+ //
+ // MsgMisc[7] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware.
+ // Please reference this revision ID when filing support cases with Synopsys.
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Module Type:
+ // 0x01 = Reserved
+ // 0x02 = DDR4 unbuffered
+ // 0x03 = Reserved
+ // 0x04 = Reserved
+ // 0x05 = Reserved
+ //
+ uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7):
+ // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting)
+ uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ // Total number of DQ bits enabled in PHY
+ uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS.
+ //
+ // If the bit is set to 1, the CS is connected to DRAM.
+ // If the bit is set to 0, the CS is not connected to DRAM.
+ //
+ // CsPresent[0] = CS0 is populated with DRAM
+ // CsPresent[1] = CS1 is populated with DRAM
+ // CsPresent[2] = CS2 is populated with DRAM
+ // CsPresent[3] = CS3 is populated with DRAM
+ // CsPresent[7:4] = Reserved (must be programmed to 0)
+ //
+ //
+ uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 0
+ uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 1
+ uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ // Corresponds to CS[3:0]
+ // 1 = Address Mirror.
+ // 0 = No Address Mirror.
+ uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ // Additional mode bits.
+ //
+ // Bit fields:
+ // [0] SlowAccessMode :
+ // 1 = 2T Address Timing.
+ // 0 = 1T Address Timing.
+ // [7-1] RFU, must be zero
+ uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = RFU, must be zero
+ // SequenceCtrl[2] = RFU, must be zero
+ // SequenceCtrl[3] = RFU, must be zero
+ // SequenceCtrl[4] = RFU, must be zero
+ // SequenceCtrl[5] = Run rd2D - 2d read dqs training
+ // SequenceCtrl[6] = Run wr2D - 2d write dq training
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = RFU, must be zero
+ // SequenceCtrl[9] = RFU, must be zero
+ // SequenceCtrl[10] = RFU, must be zero
+ // SequenceCtrl[11] = RFU, must be zero
+ // SequenceCtrl[12] = RFU, must be zero
+ // SequenceCtrl[13] = RFU, must be zero
+ // SequenceCtrl[15-14] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t RX2D_TrainOpt; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In
+ // Bit fields, if 2D read training enabled, then use these additional options:
+ // [0] DFE
+ // 1 = Run rx2D with DFE
+ // 0 = Run rx2D with DFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5-7] RFU, must be zero
+ //
+ uint8_t TX2D_TrainOpt; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Bit fields, if 2D write training is enabled, then use these additional options:
+ // [0] FFE
+ // 1 = Train tx2D with FFE
+ // 0 = Train tx2D with FFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5] FFE Decision Algorithm Control
+ // 1 = FFE chooses the drive strength that maximizes the average eye-area across the entire phy.
+ // 0 = FFE chooses the drive strength that maximizes the smallest eye across the entire phy.
+ // [6-7] RFU, must be zero
+ //
+ uint8_t Share2DVrefResult; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // Bitmap that designates the phy's vref source for every pstate
+ // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock.
+ // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training.
+ uint8_t Delay_Weight2D; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye.
+ uint8_t Voltage_Weight2D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye.
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D training in: Rd2D, Wr2D
+ //
+ // Reserved1E[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1E[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR6
+ // 2 = limit to +/-4 %VDDQ from MR6
+ // …
+ // 15 = limit to +/-30% VDDQ from MR6
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ uint8_t R0_RxClkDly_Margin; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R0_VrefDac_Margin; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R0_TxDqDly_Margin; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R0_DeviceVref_Margin; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved29; // Byte offset 0x29, CSR Addr 0x54014, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2A; // Byte offset 0x2a, CSR Addr 0x54015, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2B; // Byte offset 0x2b, CSR Addr 0x54015, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2C; // Byte offset 0x2c, CSR Addr 0x54016, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2D; // Byte offset 0x2d, CSR Addr 0x54016, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2E; // Byte offset 0x2e, CSR Addr 0x54017, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2F; // Byte offset 0x2f, CSR Addr 0x54017, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved31; // Byte offset 0x31, CSR Addr 0x54018, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved32; // Byte offset 0x32, CSR Addr 0x54019, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t R1_RxClkDly_Margin; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R1_VrefDac_Margin; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R1_TxDqDly_Margin; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R1_DeviceVref_Margin; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved37; // Byte offset 0x37, CSR Addr 0x5401b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved39; // Byte offset 0x39, CSR Addr 0x5401c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3A; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3B; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3D; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3E; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3F; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t R2_RxClkDly_Margin; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R2_VrefDac_Margin; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R2_TxDqDly_Margin; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R2_DeviceVref_Margin; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved48; // Byte offset 0x48, CSR Addr 0x54024, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved49; // Byte offset 0x49, CSR Addr 0x54024, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4A; // Byte offset 0x4a, CSR Addr 0x54025, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t R3_RxClkDly_Margin; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R3_VrefDac_Margin; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R3_TxDqDly_Margin; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R3_DeviceVref_Margin; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved57; // Byte offset 0x57, CSR Addr 0x5402b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved58; // Byte offset 0x58, CSR Addr 0x5402c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved59; // Byte offset 0x59, CSR Addr 0x5402c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5B; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5C; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In
+ // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D.
+ //
+ // Reserved5D[0-3]: bitTimeControl
+ // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point.
+ // 0 = 1 kilobit per point (legacy behavior)
+ // 1 = 2 kilobits per point
+ // 2 = 4 kilobits per point
+ // …
+ // 15 = 32 megabits per point
+ //
+ // Reserved5D[4]: Exhaustive2D
+ // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior)
+ // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point.
+ //
+ // Reserved5D[5:7]: RFU, must be 0
+ uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ // Value of DDR mode register MR0 for all ranks for current pstate
+ uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Value of DDR mode register MR1 for all ranks for current pstate
+ uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ // Value of DDR mode register MR2 for all ranks for current pstate
+ uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ // Value of DDR mode register MR3 for all ranks for current pstate
+ uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value of DDR mode register MR4 for all ranks for current pstate
+ uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value of DDR mode register MR5 for all ranks for current pstate
+ uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0.
+ uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // X16 device map. Corresponds to CS[3:0].
+ // X16Present[0] = CS0 is populated with X16 devices
+ // X16Present[1] = CS1 is populated with X16 devices
+ // X16Present[2] = CS2 is populated with X16 devices
+ // X16Present[3] = CS3 is populated with X16 devices
+ // X16Present[7:4] = Reserved (must be programmed to 0)
+ //
+ // Ranks may not contain mixed device types.
+ uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // controls timing of chip select signals when DDR4 gear-down mode is active
+ // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs
+ // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode
+ uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM:
+ // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0
+ // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0
+ // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0
+ uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM:
+ // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1
+ // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1
+ // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1
+ uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM:
+ // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2
+ // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2
+ // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2
+ uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM:
+ // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3
+ // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3
+ // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3
+ uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM:
+ // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4
+ // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4
+ // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4
+ uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM:
+ // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5
+ // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5
+ // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5
+ uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM:
+ // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6
+ // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6
+ // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6
+ uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM:
+ // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7
+ // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7
+ // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7
+ uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices.
+ uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices.
+ uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices.
+ uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices.
+ uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices.
+ uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices.
+ uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices.
+ uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices.
+ uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices.
+ uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices.
+ uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices.
+ uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices.
+ uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices.
+ uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices.
+ uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices.
+ uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices.
+ uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices.
+ uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices.
+ uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices.
+ uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices.
+ uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices.
+ uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices.
+ uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices.
+ uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices.
+ uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices.
+ uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices.
+ uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices.
+ uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices.
+ uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices.
+ uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices.
+ uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices.
+ uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices.
+ uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices.
+ uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices.
+ uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices.
+ uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices.
+ uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices.
+ uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices.
+ uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices.
+ uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices.
+ uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A
+
+ uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A
+
+ uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in
+ // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1).
+ // RdDBI is dynamically disabled in certain training steps,
+ // and so the [RdDBI disabled] CAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_CAS_L[0] == 0: use value in MR0
+ // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2]
+ // Other bits are ignored
+ uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In
+ // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1).
+ // 2tCK write prambles are dynamically disabled in certain training steps,
+ // and so the [1tCK write preamble] WCAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_WCAS_L[0] == 0: use value in MR2
+ // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3]
+ // Other bits are ignored
+ uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In
+ // Contains various options for training DDR4 Devices.
+ //
+ // Bit fields:
+ //
+ // D4Misc[7:1] RFU, must be zero
+ //
+ // D4Misc[0] = protect memory reset
+ // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training.
+ // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training
+} __attribute__ ((packed)) PMU_SMB_DDR4U_2D_t;
diff --git a/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_lpddr3.h b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_lpddr3.h
new file mode 100644
index 0000000..6850d06
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_lpddr3.h
@@ -0,0 +1,434 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief LPDDR3_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_LPDDR3_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:5] RFU, must be zero
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] RFU, must be zero
+ //
+ // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[7-6] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t Reserved0D; // Byte offset 0x0d, CSR Addr 0x54006, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = RunWrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[10] = RFU, must be zero
+ // SequenceCtrl[11] = RFU, must be zero
+ // SequenceCtrl[12] = Run LPCA - CA Training
+ // SequenceCtrl[13] = RFU, must be zero
+ // SequenceCtrl[14] = RFU, must be zero
+ // SequenceCtrl[15] = RFU, must be zero
+ //
+ uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t DFIMRLMargin; // Byte offset 0x14, CSR Addr 0x5400a, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ //
+ // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system.
+ uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t UseBroadcastMR; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired.
+ //
+ // 0x0 = Use MR<0:17>_A0 for rank 0 channel A
+ // Use MR<0:17>_B0 for rank 0 channel B
+ // Use MR<0:17>_A1 for rank 1 channel A
+ // Use MR<0:17>_B1 for rank 1 channel B
+ //
+ // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks
+ //
+ // This should be set to 1 for all systems.
+ //
+ // Note: If setting this to 0, only mode register settings related to DRAM partial array self-refresh may be different between the ranks and channels. All other mode register settings must be the same for all ranks and channels.
+ uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t LogToPhyByteMap0; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // Physical Byte associated with Channel A logical Byte 0, depending on LogToPhyByteMap0[7] value:
+ // LogToPhyByteMap0[7]==0: Logical Byte 0 map on Physical Byte 0
+ // LogToPhyByteMap0[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap0[6:0]
+ uint8_t LogToPhyByteMap1; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In
+ // Physical Byte associated with Channel A logical Byte 1, depending on LogToPhyByteMap1[7] value:
+ // LogToPhyByteMap1[7]==0: Logical Byte 1 map on Physical Byte 1
+ // LogToPhyByteMap1[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap1[6:0]
+ uint8_t LogToPhyByteMap2; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Physical Byte associated with Channel A logical Byte 2, depending on LogToPhyByteMap2[7] value:
+ // LogToPhyByteMap2[7]==0: Logical Byte 2 map on Physical Byte 2
+ // LogToPhyByteMap2[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap2[6:0]
+ uint8_t LogToPhyByteMap3; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // Physical Byte associated with Channel A logical Byte 3, depending on LogToPhyByteMap3[7] value:
+ // LogToPhyByteMap3[7]==0: Logical Byte 3 map on Physical Byte 3
+ // LogToPhyByteMap3[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap3[6:0]
+ uint8_t LogToPhyByteMap4; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // Physical Byte associated with Channel B logical Byte 0, depending on LogToPhyByteMap4[7] value:
+ // LogToPhyByteMap4[7]==0: Logical Byte 0 map on Physical Byte 4
+ // LogToPhyByteMap4[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap4[6:0]
+ uint8_t LogToPhyByteMap5; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In
+ // Physical Byte associated with Channel B logical Byte 1, depending on LogToPhyByteMap5[7] value:
+ // LogToPhyByteMap5[7]==0: Logical Byte 1 map on Physical Byte 5
+ // LogToPhyByteMap5[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap5[6:0]
+ uint8_t LogToPhyByteMap6; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Physical Byte associated with Channel B logical Byte 2, depending on LogToPhyByteMap6[7] value:
+ // LogToPhyByteMap6[7]==0: Logical Byte 2 map on Physical Byte 6
+ // LogToPhyByteMap6[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap6[6:0]
+ uint8_t LogToPhyByteMap7; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In
+ // Physical Byte associated with Channel B logical Byte 3, depending on LogToPhyByteMap7[7] value:
+ // LogToPhyByteMap7[7]==0: Logical Byte 3 map on Physical Byte 7
+ // LogToPhyByteMap7[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap7[6:0]
+ uint8_t LogToPhyByteMap8; // Byte offset 0x20, CSR Addr 0x54010, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t LogToPhyByteMap9; // Byte offset 0x21, CSR Addr 0x54010, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t EnabledDQsChA; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Total number of DQ bits enabled in PHY Channel A
+ uint8_t CsPresentChA; // Byte offset 0x23, CSR Addr 0x54011, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel A.
+ //
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChA_RR_1_0; // Byte offset 0x24, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RR_0_1; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_1_0; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_0_1; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_A0; // Byte offset 0x31, CSR Addr 0x54018, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0}
+ uint8_t MR2_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0}
+ uint8_t MR3_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0}
+ uint8_t Reserved34; // Byte offset 0x34, CSR Addr 0x5401a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0}
+ uint8_t MR16_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0}
+ uint8_t MR17_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0}
+ uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_A1; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In
+ // Must be programmed the same as MR1_A0
+ uint8_t MR2_A1; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
+ // Must be programmed the same as MR2_A0
+ uint8_t MR3_A1; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
+ // Must be programmed the same as MR3_A0
+ uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_A1; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
+ // Must be programmed the same as MR11_A0
+ uint8_t MR16_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1}
+ uint8_t MR17_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1}
+ uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved41; // Byte offset 0x41, CSR Addr 0x54020, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved42; // Byte offset 0x42, CSR Addr 0x54021, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved43; // Byte offset 0x43, CSR Addr 0x54021, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved44; // Byte offset 0x44, CSR Addr 0x54022, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t EnabledDQsChB; // Byte offset 0x48, CSR Addr 0x54024, Direction=In
+ // Total number of DQ bits enabled in PHY Channel B
+ uint8_t CsPresentChB; // Byte offset 0x49, CSR Addr 0x54024, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel B.
+ //
+ // 0x0 = No chip selects are populated with DRAM
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChB_RR_1_0; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RR_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_1; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs01 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_1; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_1; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_0; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_1_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_0_1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_B0; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In
+ // Must be programmed the same as MR1_A0
+ uint8_t MR2_B0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In
+ // Must be programmed the same as MR2_A0
+ uint8_t MR3_B0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=In
+ // Must be programmed the same as MR3_A0
+ uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_B0; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=In
+ // Must be programmed the same as MR11_A0
+ uint8_t MR16_B0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0}
+ uint8_t MR17_B0; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0}
+ uint8_t Reserved5E; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_B1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=In
+ // Must be programmed the same as MR1_A0
+ uint8_t MR2_B1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Must be programmed the same as MR2_A0
+ uint8_t MR3_B1; // Byte offset 0x61, CSR Addr 0x54030, Direction=In
+ // Must be programmed the same as MR3_A0
+ uint8_t Reserved62; // Byte offset 0x62, CSR Addr 0x54031, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_B1; // Byte offset 0x63, CSR Addr 0x54031, Direction=In
+ // Must be programmed the same as MR11_A0
+ uint8_t MR16_B1; // Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1}
+ uint8_t MR17_B1; // Byte offset 0x65, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1}
+ uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+} __attribute__ ((packed)) PMU_SMB_LPDDR3_1D_t;
diff --git a/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_lpddr4.h b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_lpddr4.h
new file mode 100644
index 0000000..d194621
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_lpddr4.h
@@ -0,0 +1,557 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief LPDDR4_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_LPDDR4_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Quick Rd2D during 1D Training
+ // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] Disable Boot Clock
+ // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended)
+ // 0x0 = Use Boot Frequency Clock
+ //
+ // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[7-6] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.25*VDDQ, set this field to 0x20.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Lp4 specific options for training.
+ //
+ // Bit fields:
+ //
+ // Lp4Misc[0] Enable dfi_reset_n
+ //
+ // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training.
+ // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin.
+ //
+ // 0x1 = Enables dfi_reset_n to control memreset after training.
+ // PHY Internal registers control memreset during training only.
+ // To ensure that no glitches occur on BP_MEMRESET at the end of training,
+ // The MC must drive dfi_reset_n=1'b1 _prior to starting training_
+ //
+ // Lp4Misc[7-1] RFU, must be zero
+ uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D.
+ //
+ // Reserved0E[0:3]: bitTimeControl
+ // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point.
+ // 0 = 288 bits per point (legacy behavior)
+ // 1 = 576 bits per point
+ // 2 = 1.125 kilobits per point
+ // …
+ // 15 = 9 megabits per point
+ //
+ // Reserved0E[4]: Exhaustive2D
+ // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior)
+ // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point.
+ //
+ // Reserved0E[5:7]: RFU, must be 0
+ uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[11-10] = RFU, must be zero
+ // SequenceCtrl[12] = Run LPCA - CA Training
+ // SequenceCtrl[15-13] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ //
+ // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system.
+ uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired.
+ //
+ // 0x0 = Use MR<0:17>_A0 for rank 0 channel A
+ // Use MR<0:17>_B0 for rank 0 channel B
+ // Use MR<0:17>_A1 for rank 1 channel A
+ // Use MR<0:17>_B1 for rank 1 channel B
+ //
+ // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks
+ //
+ // It is recommended in most LPDDR4 system configurations to set this to 1.
+ //
+ // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels.
+ //
+ uint8_t Lp4Quickboot; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In
+ // Enable Quickboot.
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D stages: Rd2D, Wr2D
+ //
+ // Reserved1A[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1A[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR14
+ // 2 = limit to +/-4 %VDDQ from MR14
+ // …
+ // 15 = limit to +/-30% VDDQ from MR14
+ uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // CA training option bit field
+ // [0] CA VREF Training
+ // 1 = Enable CA VREF Training
+ // 0 = Disable CA VREF Training
+ // [1-7] RFU must be zero
+ uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // X8 mode configuration:
+ // 0x0 = x16 configuration for all devices
+ // 0xF = x8 configuration for all devices
+ // All other values are RFU
+ uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+
+
+
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Total number of DQ bits enabled in PHY Channel A
+ uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel A.
+ //
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0}
+ uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0}
+ uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0}
+ uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0}
+ uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0}
+ uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0}
+ uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0}
+ uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0}
+ uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0}
+ uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0}
+ uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0}
+ uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0}
+ uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1}
+ uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1}
+ uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1}
+ uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1}
+ uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1}
+ uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1}
+ uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1}
+ uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1}
+ uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1}
+ uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1}
+ uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1}
+ uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1}
+ uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In
+ // Terminating Rank for CA bus on Channel A
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A
+
+ uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A
+
+ uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A
+
+ uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A
+
+ uint8_t Reserved4F; // Byte offset 0x4f, CSR Addr 0x54027, Direction=N/A
+
+ uint8_t Reserved50; // Byte offset 0x50, CSR Addr 0x54028, Direction=N/A
+
+ uint8_t Reserved51; // Byte offset 0x51, CSR Addr 0x54028, Direction=N/A
+
+ uint8_t Reserved52; // Byte offset 0x52, CSR Addr 0x54029, Direction=N/A
+
+ uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A
+
+ uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A
+
+ uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A
+
+ uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A
+
+ uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In
+ // Total number of DQ bits enabled in PHY Channel B
+ uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel B.
+ //
+ // 0x0 = No chip selects are populated with DRAM
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs01 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0}
+ uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0}
+ uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0}
+ uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0}
+ uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0}
+ uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0}
+ uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0}
+ uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0}
+ uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0}
+ uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0}
+ uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0}
+ uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0}
+ uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1}
+ uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1}
+ uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1}
+ uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1}
+ uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1}
+ uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1}
+ uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1}
+ uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1}
+ uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1}
+ uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1}
+ uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1}
+ uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1}
+ uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In
+ // Terminating Rank for CA bus on Channel B
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A
+
+ uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A
+
+ uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A
+
+ uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A
+
+ uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A
+
+ uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A
+
+} __attribute__ ((packed)) PMU_SMB_LPDDR4_1D_t;
diff --git a/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_lpddr4_2d.h b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_lpddr4_2d.h
new file mode 100644
index 0000000..c6ab3d3
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/mnPmuSramMsgBlock_lpddr4_2d.h
@@ -0,0 +1,557 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief LPDDR4_2D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_LPDDR4_2D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Quick Rd2D during 1D Training
+ // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] Disable Boot Clock
+ // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended)
+ // 0x0 = Use Boot Frequency Clock
+ //
+ // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[7-6] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.25*VDDQ, set this field to 0x20.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Lp4 specific options for training.
+ //
+ // Bit fields:
+ //
+ // Lp4Misc[0] Enable dfi_reset_n
+ //
+ // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training.
+ // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin.
+ //
+ // 0x1 = Enables dfi_reset_n to control memreset after training.
+ // PHY Internal registers control memreset during training only.
+ // To ensure that no glitches occur on BP_MEMRESET at the end of training,
+ // The MC must drive dfi_reset_n=1'b1 _prior to starting training_
+ //
+ // Lp4Misc[7-1] RFU, must be zero
+ uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D.
+ //
+ // Reserved0E[0:3]: bitTimeControl
+ // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point.
+ // 0 = 288 bits per point (legacy behavior)
+ // 1 = 576 bits per point
+ // 2 = 1.125 kilobits per point
+ // …
+ // 15 = 9 megabits per point
+ //
+ // Reserved0E[4]: Exhaustive2D
+ // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior)
+ // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point.
+ //
+ // Reserved0E[5:7]: RFU, must be 0
+ uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = RFU, must be zero
+ // SequenceCtrl[2] = RFU, must be zero
+ // SequenceCtrl[3] = RFU, must be zero
+ // SequenceCtrl[4] = RFU, must be zero
+ // SequenceCtrl[5] = Run rd2D - 2d read dqs training
+ // SequenceCtrl[6] = Run wr2D - 2d write dq training
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = RFU, must be zero
+ // SequenceCtrl[9] = RFU, must be zero
+ // SequenceCtrl[11-10] = RFU, must be zero
+ // SequenceCtrl[12] = RFU, must be zero
+ // SequenceCtrl[15-13] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ //
+ // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system.
+ uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired.
+ //
+ // 0x0 = Use MR<0:17>_A0 for rank 0 channel A
+ // Use MR<0:17>_B0 for rank 0 channel B
+ // Use MR<0:17>_A1 for rank 1 channel A
+ // Use MR<0:17>_B1 for rank 1 channel B
+ //
+ // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks
+ //
+ // It is recommended in most LPDDR4 system configurations to set this to 1.
+ //
+ // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels.
+ //
+ uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A
+
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D stages: Rd2D, Wr2D
+ //
+ // Reserved1A[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1A[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR14
+ // 2 = limit to +/-4 %VDDQ from MR14
+ // …
+ // 15 = limit to +/-30% VDDQ from MR14
+ uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // CA training option bit field
+ // [0] CA VREF Setting
+ // 1 = Set MR12 from internal register
+ // 0 = Set MR12 from message block
+ // [1-7] RFU must be zero
+ uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // X8 mode configuration:
+ // 0x0 = x16 configuration for all devices
+ // 0xF = x8 configuration for all devices
+ // All other values are RFU
+ uint8_t RX2D_TrainOpt; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In
+ // Bit fields, if 2D read training enabled, then use these additional options:
+ // [0] DFE
+ // 1 = Run rx2D with DFE
+ // 0 = Run rx2D with DFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5-7] RFU, must be zero
+ //
+ uint8_t TX2D_TrainOpt; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Bit fields, if 2D write training is enabled, then use these additional options:
+ // [0] FFE
+ // 1 = Train tx2D with FFE
+ // 0 = Train tx2D with FFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5-7] RFU, must be zero
+ //
+ uint8_t Share2DVrefResult; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In
+ // Bitmap that designates the phy's vref source for every pstate
+ // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock.
+ // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training.
+ uint8_t Delay_Weight2D; // Byte offset 0x20, CSR Addr 0x54010, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye.
+ uint8_t Voltage_Weight2D; // Byte offset 0x21, CSR Addr 0x54010, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Total number of DQ bits enabled in PHY Channel A
+ uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel A.
+ //
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0}
+ uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0}
+ uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0}
+ uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0}
+ uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0}
+ uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0}
+ uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0}
+ uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0}
+ uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0}
+ uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0}
+ uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0}
+ uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0}
+ uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1}
+ uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1}
+ uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1}
+ uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1}
+ uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1}
+ uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1}
+ uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1}
+ uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1}
+ uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1}
+ uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1}
+ uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1}
+ uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1}
+ uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In
+ // Terminating Rank for CA bus on Channel A
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A
+
+ uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A
+
+ uint8_t TrainedVREFDQ_A0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // Trained DQ Vref setting for Ch A Rank 0
+ uint8_t TrainedVREFDQ_A1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // Trained DQ Vref setting for Ch A Rank 1
+ uint8_t RxClkDly_Margin_A0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_A0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_A0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_A0; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t RxClkDly_Margin_A1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_A1; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_A1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_A1; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In
+ // Total number of DQ bits enabled in PHY Channel B
+ uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel B.
+ //
+ // 0x0 = No chip selects are populated with DRAM
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs01 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0}
+ uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0}
+ uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0}
+ uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0}
+ uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0}
+ uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0}
+ uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0}
+ uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0}
+ uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0}
+ uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0}
+ uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0}
+ uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0}
+ uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1}
+ uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1}
+ uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1}
+ uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1}
+ uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1}
+ uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1}
+ uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1}
+ uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1}
+ uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1}
+ uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1}
+ uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1}
+ uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1}
+ uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In
+ // Terminating Rank for CA bus on Channel B
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t TrainedVREFDQ_B0; // Byte offset 0x80, CSR Addr 0x54040, Direction=Out
+ // Trained DQ Vref setting for Ch B Rank 0
+ uint8_t TrainedVREFDQ_B1; // Byte offset 0x81, CSR Addr 0x54040, Direction=Out
+ // Trained DQ Vref setting for Ch B Rank 1
+ uint8_t RxClkDly_Margin_B0; // Byte offset 0x82, CSR Addr 0x54041, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_B0; // Byte offset 0x83, CSR Addr 0x54041, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_B0; // Byte offset 0x84, CSR Addr 0x54042, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_B0; // Byte offset 0x85, CSR Addr 0x54042, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t RxClkDly_Margin_B1; // Byte offset 0x86, CSR Addr 0x54043, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_B1; // Byte offset 0x87, CSR Addr 0x54043, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_B1; // Byte offset 0x88, CSR Addr 0x54044, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_B1; // Byte offset 0x89, CSR Addr 0x54044, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+} __attribute__ ((packed)) PMU_SMB_LPDDR4_2D_t;
diff --git a/arch/arm/include/asm/arch-c2/nand.h b/arch/arm/include/asm/arch-c2/nand.h
new file mode 100644
index 0000000..91484ac
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/nand.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __NAND_H__
+#define __NAND_H__
+#include <asm/arch/cpu_config.h>
+
+#ifndef SD_EMMC_BASE_C
+#define SD_EMMC_BASE_C 0xd0074000
+#endif
+
+#define P_NAND_BASE (SD_EMMC_BASE_C | (1<<11))
+#define P_CLK_CNTL (volatile uint32_t *)(SD_EMMC_BASE_C)
+#define P_NAND_CMD (volatile uint32_t *)(P_NAND_BASE + 0x00)
+#define P_NAND_CFG (volatile uint32_t *)(P_NAND_BASE + 0x04)
+#define P_NAND_DADR (volatile uint32_t *)(P_NAND_BASE + 0x08)
+#define P_NAND_IADR (volatile uint32_t *)(P_NAND_BASE + 0x0c)
+#define P_NAND_BUF (volatile uint32_t *)(P_NAND_BASE + 0x10)
+#define P_NAND_INFO (volatile uint32_t *)(P_NAND_BASE + 0x14)
+#define P_NAND_DC (volatile uint32_t *)(P_NAND_BASE + 0x18)
+#define P_NAND_ADR (volatile uint32_t *)(P_NAND_BASE + 0x1c)
+#define P_NAND_DL (volatile uint32_t *)(P_NAND_BASE + 0x20)
+#define P_NAND_DH (volatile uint32_t *)(P_NAND_BASE + 0x24)
+#define P_NAND_CADR (volatile uint32_t *)(P_NAND_BASE + 0x28)
+#define P_NAND_SADR (volatile uint32_t *)(P_NAND_BASE + 0x2c)
+
+#define CEF (0xf<<10)
+#define CE0 (0xe<<10)
+#define CE1 (0xd<<10)
+#define CE2 (0xb<<10)
+#define CE3 (0x7<<10)
+
+#define IO4 ((0xe<<10)|(1<<18))
+#define IO5 ((0xd<<10)|(1<<18))
+#define IO6 ((0xb<<10)|(1<<18))
+
+#define CLE (0x5<<14)
+#define ALE (0x6<<14)
+#define DWR (0x4<<14)
+#define DRD (0x8<<14)
+#define IDLE (0xc<<14)
+#define RB (1<<20)
+
+#define M2N ((0<<17) | (2<<20) | (1<<19))
+#define N2M ((1<<17) | (2<<20) | (1<<19))
+#define STS ((3<<17) | (2<<20))
+#define ADL ((0<<16) | (3<<20))
+#define ADH ((1<<16) | (3<<20))
+#define AIL ((2<<16) | (3<<20))
+#define AIH ((3<<16) | (3<<20))
+#define ASL ((4<<16) | (3<<20))
+#define ASH ((5<<16) | (3<<20))
+#define SEED ((8<<16) | (3<<20))
+
+// NAND Flash Manufacturer ID Codes
+#define NAND_MFR_TOSHIBA 0x98
+#define NAND_MFR_SAMSUNG 0xec
+#define NAND_MFR_FUJITSU 0x04
+#define NAND_MFR_NATIONAL 0x8f
+#define NAND_MFR_RENESAS 0x07
+#define NAND_MFR_STMICRO 0x20
+#define NAND_MFR_HYNIX 0xad
+#define NAND_MFR_MICRON 0x2c
+#define NAND_MFR_AMD 0x01
+#define NAND_MFR_INTEL 0x89
+#define NAND_MFR_SANDISK 0x45
+#define NAND_MFR_USER 0x100
+#define NAND_MFR_EFUSE 0x101
+
+typedef struct nand_setup {
+ union {
+ uint32_t d32;
+ struct {
+ unsigned cmd:22;
+ unsigned large_page:1; // 22
+ unsigned no_rb:1; // 23 from efuse
+ unsigned a2:1; // 24
+ unsigned reserved25:1; // 25
+ unsigned page_list:1; // 26
+ unsigned sync_mode:2; // 27 from efuse
+ unsigned size:2; // 29 from efuse
+ unsigned active:1; // 31
+ } b;
+ } cfg;
+ uint16_t id;
+ uint16_t max; // id:0x100 user, max:0 disable.
+} nand_setup_t;
+
+typedef struct _nand_cmd{
+ unsigned char type;
+ unsigned char val;
+} nand_cmd_t;
+
+typedef struct _ext_info{
+ uint32_t read_info; //nand_read_info;
+ uint32_t new_type; //new_nand_type;
+ uint32_t page_per_blk; //pages_in_block;
+ uint32_t xlc; //slc=1, mlc=2, tlc=3.
+ uint32_t rsv1[5];
+} ext_info_t;
+
+typedef struct _nand_page0 {
+ nand_setup_t nand_setup; //8
+ unsigned char page_list[16]; //16
+ nand_cmd_t retry_usr[32]; //64 (32 cmd max I/F)
+ ext_info_t ext_info; //64
+} nand_page0_t; //384 bytes max.
+
+//#define NAND_PAGE0_BUF BL1_NAND_BUFF
+#define NAND_PAGE0_BUF (0x1800000)
+#define NAND_PAGE_LIST (NAND_PAGE0_BUF + sizeof(nand_setup_t))
+#define NAND_RETRY_USER (NAND_PAGE_LIST + 16)
+#define NAND_INFO_BUF (NAND_PAGE0_BUF + 512)
+#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1)
+//#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1)
+
+#define ERROR_MOD(mod,num) ((uint32_t)(((mod<<6)|num)))
+#define ERROR_NAND_TIMEOUT ERROR_MOD(2,1) //
+#define ERROR_NAND_ECC ERROR_MOD(2,2) //
+#define ERROR_NAND_MAGIC_WORD ERROR_MOD(2,3) //
+#define ERROR_NAND_INIT_READ ERROR_MOD(2,4) //
+#define ERROR_NAND_BLANK_PAGE ERROR_MOD(2,5) //
+#define ERROR_NAND_UNALIGN_SRC ERROR_MOD(2,6) //
+
+#define NAND_SECTOR_SIZE (512)
+#define NAND_MAX_PAGESIZE (0x4000) //16K
+#define SRC_ALIGN_SIZE (NAND_MAX_PAGESIZE)
+
+#define INFO_BYTE_PER_ECCPAGE (8)
+uint32_t nfio_init(void);
+uint32_t nf_read(uint32_t boot_device, uint32_t src, uint32_t des, uint32_t size);
+#endif /* __NAND_H__ */
+
diff --git a/arch/arm/include/asm/arch-c2/oscring.h b/arch/arm/include/asm/arch-c2/oscring.h
new file mode 100644
index 0000000..ce7d7eb
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/oscring.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __OSCRING_H__
+#define __OSCRING_H__
+
+#define OSCRING_CTL_REG0 SYSCTRL_OSC_RING_CTRL0
+#define OSCRING_CTL_DATA0 0x00000555 /*0:25*/
+#define OSCRING_CTL_REG1 SYSCTRL_OSC_RING_CTRL1
+#define OSCRING_CTL_DATA1 0x15555555 /*0:7*/
+#define OSCRING_CTL_REG2 SYSCTRL_OSC_RING_CTRL2
+#define OSCRING_CTL_DATA2 0x00000555
+
+#define RING_PWM_VCCK PWMAB_PWM_B
+#define RING_PWM_EE PWMAB_PWM_A
+
+int ring_msr(int index);
+#endif
diff --git a/arch/arm/include/asm/arch-c2/p_register.h b/arch/arm/include/asm/arch-c2/p_register.h
new file mode 100644
index 0000000..24b136d
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/p_register.h
@@ -0,0 +1,4083 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifdef P_REGISTER_H
+#else
+#define P_REGISTER_H
+
+//
+// Reading file: ./REG_LIST_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Reading file: REG_LIST_AUDIO_RTL.h
+//
+//========================================================================
+// AUDIO - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe050000
+// -----------------------------------------------
+#define P_EE_AUDIO_CLK_GATE_EN0 ((volatile uint32_t *)0xfe050000)
+#define P_EE_AUDIO_CLK_GATE_EN1 ((volatile uint32_t *)0xfe050004)
+#define P_EE_AUDIO_MCLK_A_CTRL ((volatile uint32_t *)0xfe050008)
+#define P_EE_AUDIO_MCLK_B_CTRL ((volatile uint32_t *)0xfe05000c)
+#define P_EE_AUDIO_MCLK_C_CTRL ((volatile uint32_t *)0xfe050010)
+#define P_EE_AUDIO_MCLK_D_CTRL ((volatile uint32_t *)0xfe050014)
+#define P_EE_AUDIO_MCLK_E_CTRL ((volatile uint32_t *)0xfe050018)
+#define P_EE_AUDIO_MCLK_F_CTRL ((volatile uint32_t *)0xfe05001c)
+#define P_EE_AUDIO_PAD_CTRL0 ((volatile uint32_t *)0xfe050020)
+#define P_EE_AUDIO_PAD_CTRL1 ((volatile uint32_t *)0xfe050024)
+#define P_EE_AUDIO_SW_RESET0 ((volatile uint32_t *)0xfe050028)
+#define P_EE_AUDIO_SW_RESET1 ((volatile uint32_t *)0xfe05002c)
+#define P_EE_AUDIO_CLK81_CTRL ((volatile uint32_t *)0xfe050030)
+#define P_EE_AUDIO_CLK81_EN ((volatile uint32_t *)0xfe050034)
+#define P_EE_AUDIO_MST_A_SCLK_CTRL0 ((volatile uint32_t *)0xfe050040)
+#define P_EE_AUDIO_MST_A_SCLK_CTRL1 ((volatile uint32_t *)0xfe050044)
+#define P_EE_AUDIO_MST_B_SCLK_CTRL0 ((volatile uint32_t *)0xfe050048)
+#define P_EE_AUDIO_MST_B_SCLK_CTRL1 ((volatile uint32_t *)0xfe05004c)
+#define P_EE_AUDIO_MST_C_SCLK_CTRL0 ((volatile uint32_t *)0xfe050050)
+#define P_EE_AUDIO_MST_C_SCLK_CTRL1 ((volatile uint32_t *)0xfe050054)
+#define P_EE_AUDIO_MST_D_SCLK_CTRL0 ((volatile uint32_t *)0xfe050058)
+#define P_EE_AUDIO_MST_D_SCLK_CTRL1 ((volatile uint32_t *)0xfe05005c)
+#define P_EE_AUDIO_MST_E_SCLK_CTRL0 ((volatile uint32_t *)0xfe050060)
+#define P_EE_AUDIO_MST_E_SCLK_CTRL1 ((volatile uint32_t *)0xfe050064)
+#define P_EE_AUDIO_MST_F_SCLK_CTRL0 ((volatile uint32_t *)0xfe050068)
+#define P_EE_AUDIO_MST_F_SCLK_CTRL1 ((volatile uint32_t *)0xfe05006c)
+#define P_EE_AUDIO_MST_DLY_CTRL0 ((volatile uint32_t *)0xfe050070)
+#define P_EE_AUDIO_MST_DLY_CTRL1 ((volatile uint32_t *)0xfe050074)
+#define P_EE_AUDIO_CLK_TDMIN_A_CTRL ((volatile uint32_t *)0xfe050080)
+#define P_EE_AUDIO_CLK_TDMIN_B_CTRL ((volatile uint32_t *)0xfe050084)
+#define P_EE_AUDIO_CLK_TDMIN_C_CTRL ((volatile uint32_t *)0xfe050088)
+#define P_EE_AUDIO_CLK_TDMIN_LB_CTRL ((volatile uint32_t *)0xfe05008c)
+#define P_EE_AUDIO_CLK_TDMOUT_A_CTRL ((volatile uint32_t *)0xfe050090)
+#define P_EE_AUDIO_CLK_TDMOUT_B_CTRL ((volatile uint32_t *)0xfe050094)
+#define P_EE_AUDIO_CLK_TDMOUT_C_CTRL ((volatile uint32_t *)0xfe050098)
+#define P_EE_AUDIO_CLK_SPDIFIN_CTRL ((volatile uint32_t *)0xfe05009c)
+#define P_EE_AUDIO_CLK_SPDIFOUT_CTRL ((volatile uint32_t *)0xfe0500a0)
+#define P_EE_AUDIO_CLK_RESAMPLEA_CTRL ((volatile uint32_t *)0xfe0500a4)
+#define P_EE_AUDIO_CLK_LOCKER_CTRL ((volatile uint32_t *)0xfe0500a8)
+#define P_EE_AUDIO_CLK_PDMIN_CTRL0 ((volatile uint32_t *)0xfe0500ac)
+#define P_EE_AUDIO_CLK_PDMIN_CTRL1 ((volatile uint32_t *)0xfe0500b0)
+#define P_EE_AUDIO_CLK_SPDIFOUT_B_CTRL ((volatile uint32_t *)0xfe0500b4)
+#define P_EE_AUDIO_CLK_RESAMPLEB_CTRL ((volatile uint32_t *)0xfe0500b8)
+#define P_EE_AUDIO_CLK_SPDIFIN_LB_CTRL ((volatile uint32_t *)0xfe0500bc)
+#define P_EE_AUDIO_CLK_EQDRC_CTRL0 ((volatile uint32_t *)0xfe0500c0)
+#define P_EE_AUDIO_VAD_CLK_CTRL ((volatile uint32_t *)0xfe0500c4)
+#define P_EE_AUDIO_EARCTX_CMDC_CLK_CTRL ((volatile uint32_t *)0xfe0500c8)
+#define P_EE_AUDIO_EARCTX_DMAC_CLK_CTRL ((volatile uint32_t *)0xfe0500cc)
+#define P_EE_AUDIO_EARCRX_CMDC_CLK_CTRL ((volatile uint32_t *)0xfe0500d0)
+#define P_EE_AUDIO_EARCRX_DMAC_CLK_CTRL ((volatile uint32_t *)0xfe0500d4)
+#define P_EE_AUDIO_CLK_LOCKERB_CTRL ((volatile uint32_t *)0xfe0500d8)
+#define P_EE_AUDIO_TODDR_A_CTRL0 ((volatile uint32_t *)0xfe050100)
+#define P_EE_AUDIO_TODDR_A_CTRL1 ((volatile uint32_t *)0xfe050104)
+#define P_EE_AUDIO_TODDR_A_START_ADDR ((volatile uint32_t *)0xfe050108)
+#define P_EE_AUDIO_TODDR_A_FINISH_ADDR ((volatile uint32_t *)0xfe05010c)
+#define P_EE_AUDIO_TODDR_A_INT_ADDR ((volatile uint32_t *)0xfe050110)
+#define P_EE_AUDIO_TODDR_A_STATUS1 ((volatile uint32_t *)0xfe050114)
+#define P_EE_AUDIO_TODDR_A_STATUS2 ((volatile uint32_t *)0xfe050118)
+#define P_EE_AUDIO_TODDR_A_START_ADDRB ((volatile uint32_t *)0xfe05011c)
+#define P_EE_AUDIO_TODDR_A_FINISH_ADDRB ((volatile uint32_t *)0xfe050120)
+#define P_EE_AUDIO_TODDR_A_INIT_ADDR ((volatile uint32_t *)0xfe050124)
+#define P_EE_AUDIO_TODDR_A_CTRL2 ((volatile uint32_t *)0xfe050128)
+#define P_EE_AUDIO_TODDR_B_CTRL0 ((volatile uint32_t *)0xfe050140)
+#define P_EE_AUDIO_TODDR_B_CTRL1 ((volatile uint32_t *)0xfe050144)
+#define P_EE_AUDIO_TODDR_B_START_ADDR ((volatile uint32_t *)0xfe050148)
+#define P_EE_AUDIO_TODDR_B_FINISH_ADDR ((volatile uint32_t *)0xfe05014c)
+#define P_EE_AUDIO_TODDR_B_INT_ADDR ((volatile uint32_t *)0xfe050150)
+#define P_EE_AUDIO_TODDR_B_STATUS1 ((volatile uint32_t *)0xfe050154)
+#define P_EE_AUDIO_TODDR_B_STATUS2 ((volatile uint32_t *)0xfe050158)
+#define P_EE_AUDIO_TODDR_B_START_ADDRB ((volatile uint32_t *)0xfe05015c)
+#define P_EE_AUDIO_TODDR_B_FINISH_ADDRB ((volatile uint32_t *)0xfe050160)
+#define P_EE_AUDIO_TODDR_B_INIT_ADDR ((volatile uint32_t *)0xfe050164)
+#define P_EE_AUDIO_TODDR_B_CTRL2 ((volatile uint32_t *)0xfe050168)
+#define P_EE_AUDIO_TODDR_C_CTRL0 ((volatile uint32_t *)0xfe050180)
+#define P_EE_AUDIO_TODDR_C_CTRL1 ((volatile uint32_t *)0xfe050184)
+#define P_EE_AUDIO_TODDR_C_START_ADDR ((volatile uint32_t *)0xfe050188)
+#define P_EE_AUDIO_TODDR_C_FINISH_ADDR ((volatile uint32_t *)0xfe05018c)
+#define P_EE_AUDIO_TODDR_C_INT_ADDR ((volatile uint32_t *)0xfe050190)
+#define P_EE_AUDIO_TODDR_C_STATUS1 ((volatile uint32_t *)0xfe050194)
+#define P_EE_AUDIO_TODDR_C_STATUS2 ((volatile uint32_t *)0xfe050198)
+#define P_EE_AUDIO_TODDR_C_START_ADDRB ((volatile uint32_t *)0xfe05019c)
+#define P_EE_AUDIO_TODDR_C_FINISH_ADDRB ((volatile uint32_t *)0xfe0501a0)
+#define P_EE_AUDIO_TODDR_C_INIT_ADDR ((volatile uint32_t *)0xfe0501a4)
+#define P_EE_AUDIO_TODDR_C_CTRL2 ((volatile uint32_t *)0xfe0501a8)
+#define P_EE_AUDIO_FRDDR_A_CTRL0 ((volatile uint32_t *)0xfe0501c0)
+#define P_EE_AUDIO_FRDDR_A_CTRL1 ((volatile uint32_t *)0xfe0501c4)
+#define P_EE_AUDIO_FRDDR_A_START_ADDR ((volatile uint32_t *)0xfe0501c8)
+#define P_EE_AUDIO_FRDDR_A_FINISH_ADDR ((volatile uint32_t *)0xfe0501cc)
+#define P_EE_AUDIO_FRDDR_A_INT_ADDR ((volatile uint32_t *)0xfe0501d0)
+#define P_EE_AUDIO_FRDDR_A_STATUS1 ((volatile uint32_t *)0xfe0501d4)
+#define P_EE_AUDIO_FRDDR_A_STATUS2 ((volatile uint32_t *)0xfe0501d8)
+#define P_EE_AUDIO_FRDDR_A_START_ADDRB ((volatile uint32_t *)0xfe0501dc)
+#define P_EE_AUDIO_FRDDR_A_FINISH_ADDRB ((volatile uint32_t *)0xfe0501e0)
+#define P_EE_AUDIO_FRDDR_A_INIT_ADDR ((volatile uint32_t *)0xfe0501e4)
+#define P_EE_AUDIO_FRDDR_A_CTRL2 ((volatile uint32_t *)0xfe0501e8)
+#define P_EE_AUDIO_FRDDR_B_CTRL0 ((volatile uint32_t *)0xfe050200)
+#define P_EE_AUDIO_FRDDR_B_CTRL1 ((volatile uint32_t *)0xfe050204)
+#define P_EE_AUDIO_FRDDR_B_START_ADDR ((volatile uint32_t *)0xfe050208)
+#define P_EE_AUDIO_FRDDR_B_FINISH_ADDR ((volatile uint32_t *)0xfe05020c)
+#define P_EE_AUDIO_FRDDR_B_INT_ADDR ((volatile uint32_t *)0xfe050210)
+#define P_EE_AUDIO_FRDDR_B_STATUS1 ((volatile uint32_t *)0xfe050214)
+#define P_EE_AUDIO_FRDDR_B_STATUS2 ((volatile uint32_t *)0xfe050218)
+#define P_EE_AUDIO_FRDDR_B_START_ADDRB ((volatile uint32_t *)0xfe05021c)
+#define P_EE_AUDIO_FRDDR_B_FINISH_ADDRB ((volatile uint32_t *)0xfe050220)
+#define P_EE_AUDIO_FRDDR_B_INIT_ADDR ((volatile uint32_t *)0xfe050224)
+#define P_EE_AUDIO_FRDDR_B_CTRL2 ((volatile uint32_t *)0xfe050228)
+#define P_EE_AUDIO_FRDDR_C_CTRL0 ((volatile uint32_t *)0xfe050240)
+#define P_EE_AUDIO_FRDDR_C_CTRL1 ((volatile uint32_t *)0xfe050244)
+#define P_EE_AUDIO_FRDDR_C_START_ADDR ((volatile uint32_t *)0xfe050248)
+#define P_EE_AUDIO_FRDDR_C_FINISH_ADDR ((volatile uint32_t *)0xfe05024c)
+#define P_EE_AUDIO_FRDDR_C_INT_ADDR ((volatile uint32_t *)0xfe050250)
+#define P_EE_AUDIO_FRDDR_C_STATUS1 ((volatile uint32_t *)0xfe050254)
+#define P_EE_AUDIO_FRDDR_C_STATUS2 ((volatile uint32_t *)0xfe050258)
+#define P_EE_AUDIO_FRDDR_C_START_ADDRB ((volatile uint32_t *)0xfe05025c)
+#define P_EE_AUDIO_FRDDR_C_FINISH_ADDRB ((volatile uint32_t *)0xfe050260)
+#define P_EE_AUDIO_FRDDR_C_INIT_ADDR ((volatile uint32_t *)0xfe050264)
+#define P_EE_AUDIO_FRDDR_C_CTRL2 ((volatile uint32_t *)0xfe050268)
+#define P_EE_AUDIO_ARB_CTRL ((volatile uint32_t *)0xfe050280)
+#define P_EE_AUDIO_LB_A_CTRL0 ((volatile uint32_t *)0xfe0502c0)
+#define P_EE_AUDIO_LB_A_CTRL1 ((volatile uint32_t *)0xfe0502c4)
+#define P_EE_AUDIO_LB_A_CTRL2 ((volatile uint32_t *)0xfe0502c8)
+#define P_EE_AUDIO_LB_A_CTRL3 ((volatile uint32_t *)0xfe0502cc)
+#define P_EE_AUDIO_LB_A_DAT_CH_ID0 ((volatile uint32_t *)0xfe0502d0)
+#define P_EE_AUDIO_LB_A_DAT_CH_ID1 ((volatile uint32_t *)0xfe0502d4)
+#define P_EE_AUDIO_LB_A_DAT_CH_ID2 ((volatile uint32_t *)0xfe0502d8)
+#define P_EE_AUDIO_LB_A_DAT_CH_ID3 ((volatile uint32_t *)0xfe0502dc)
+#define P_EE_AUDIO_LB_A_LB_CH_ID0 ((volatile uint32_t *)0xfe0502e0)
+#define P_EE_AUDIO_LB_A_LB_CH_ID1 ((volatile uint32_t *)0xfe0502e4)
+#define P_EE_AUDIO_LB_A_LB_CH_ID2 ((volatile uint32_t *)0xfe0502e8)
+#define P_EE_AUDIO_LB_A_LB_CH_ID3 ((volatile uint32_t *)0xfe0502ec)
+#define P_EE_AUDIO_LB_A_STS ((volatile uint32_t *)0xfe0502f0)
+#define P_EE_AUDIO_TDMIN_A_CTRL ((volatile uint32_t *)0xfe050300)
+#define P_EE_AUDIO_TDMIN_A_SWAP0 ((volatile uint32_t *)0xfe050304)
+#define P_EE_AUDIO_TDMIN_A_MASK0 ((volatile uint32_t *)0xfe050308)
+#define P_EE_AUDIO_TDMIN_A_MASK1 ((volatile uint32_t *)0xfe05030c)
+#define P_EE_AUDIO_TDMIN_A_MASK2 ((volatile uint32_t *)0xfe050310)
+#define P_EE_AUDIO_TDMIN_A_MASK3 ((volatile uint32_t *)0xfe050314)
+#define P_EE_AUDIO_TDMIN_A_STAT ((volatile uint32_t *)0xfe050318)
+#define P_EE_AUDIO_TDMIN_A_MUTE_VAL ((volatile uint32_t *)0xfe05031c)
+#define P_EE_AUDIO_TDMIN_A_MUTE0 ((volatile uint32_t *)0xfe050320)
+#define P_EE_AUDIO_TDMIN_A_MUTE1 ((volatile uint32_t *)0xfe050324)
+#define P_EE_AUDIO_TDMIN_A_MUTE2 ((volatile uint32_t *)0xfe050328)
+#define P_EE_AUDIO_TDMIN_A_MUTE3 ((volatile uint32_t *)0xfe05032c)
+#define P_EE_AUDIO_TDMIN_B_CTRL ((volatile uint32_t *)0xfe050340)
+#define P_EE_AUDIO_TDMIN_B_SWAP0 ((volatile uint32_t *)0xfe050344)
+#define P_EE_AUDIO_TDMIN_B_MASK0 ((volatile uint32_t *)0xfe050348)
+#define P_EE_AUDIO_TDMIN_B_MASK1 ((volatile uint32_t *)0xfe05034c)
+#define P_EE_AUDIO_TDMIN_B_MASK2 ((volatile uint32_t *)0xfe050350)
+#define P_EE_AUDIO_TDMIN_B_MASK3 ((volatile uint32_t *)0xfe050354)
+#define P_EE_AUDIO_TDMIN_B_STAT ((volatile uint32_t *)0xfe050358)
+#define P_EE_AUDIO_TDMIN_B_MUTE_VAL ((volatile uint32_t *)0xfe05035c)
+#define P_EE_AUDIO_TDMIN_B_MUTE0 ((volatile uint32_t *)0xfe050360)
+#define P_EE_AUDIO_TDMIN_B_MUTE1 ((volatile uint32_t *)0xfe050364)
+#define P_EE_AUDIO_TDMIN_B_MUTE2 ((volatile uint32_t *)0xfe050368)
+#define P_EE_AUDIO_TDMIN_B_MUTE3 ((volatile uint32_t *)0xfe05036c)
+#define P_EE_AUDIO_TDMIN_C_CTRL ((volatile uint32_t *)0xfe050380)
+#define P_EE_AUDIO_TDMIN_C_SWAP0 ((volatile uint32_t *)0xfe050384)
+#define P_EE_AUDIO_TDMIN_C_MASK0 ((volatile uint32_t *)0xfe050388)
+#define P_EE_AUDIO_TDMIN_C_MASK1 ((volatile uint32_t *)0xfe05038c)
+#define P_EE_AUDIO_TDMIN_C_MASK2 ((volatile uint32_t *)0xfe050390)
+#define P_EE_AUDIO_TDMIN_C_MASK3 ((volatile uint32_t *)0xfe050394)
+#define P_EE_AUDIO_TDMIN_C_STAT ((volatile uint32_t *)0xfe050398)
+#define P_EE_AUDIO_TDMIN_C_MUTE_VAL ((volatile uint32_t *)0xfe05039c)
+#define P_EE_AUDIO_TDMIN_C_MUTE0 ((volatile uint32_t *)0xfe0503a0)
+#define P_EE_AUDIO_TDMIN_C_MUTE1 ((volatile uint32_t *)0xfe0503a4)
+#define P_EE_AUDIO_TDMIN_C_MUTE2 ((volatile uint32_t *)0xfe0503a8)
+#define P_EE_AUDIO_TDMIN_C_MUTE3 ((volatile uint32_t *)0xfe0503ac)
+#define P_EE_AUDIO_TDMIN_LB_CTRL ((volatile uint32_t *)0xfe0503c0)
+#define P_EE_AUDIO_TDMIN_LB_SWAP0 ((volatile uint32_t *)0xfe0503c4)
+#define P_EE_AUDIO_TDMIN_LB_MASK0 ((volatile uint32_t *)0xfe0503c8)
+#define P_EE_AUDIO_TDMIN_LB_MASK1 ((volatile uint32_t *)0xfe0503cc)
+#define P_EE_AUDIO_TDMIN_LB_MASK2 ((volatile uint32_t *)0xfe0503d0)
+#define P_EE_AUDIO_TDMIN_LB_MASK3 ((volatile uint32_t *)0xfe0503d4)
+#define P_EE_AUDIO_TDMIN_LB_STAT ((volatile uint32_t *)0xfe0503d8)
+#define P_EE_AUDIO_TDMIN_LB_MUTE_VAL ((volatile uint32_t *)0xfe0503dc)
+#define P_EE_AUDIO_TDMIN_LB_MUTE0 ((volatile uint32_t *)0xfe0503e0)
+#define P_EE_AUDIO_TDMIN_LB_MUTE1 ((volatile uint32_t *)0xfe0503e4)
+#define P_EE_AUDIO_TDMIN_LB_MUTE2 ((volatile uint32_t *)0xfe0503e8)
+#define P_EE_AUDIO_TDMIN_LB_MUTE3 ((volatile uint32_t *)0xfe0503ec)
+#define P_EE_AUDIO_SPDIFIN_CTRL0 ((volatile uint32_t *)0xfe050400)
+#define P_EE_AUDIO_SPDIFIN_CTRL1 ((volatile uint32_t *)0xfe050404)
+#define P_EE_AUDIO_SPDIFIN_CTRL2 ((volatile uint32_t *)0xfe050408)
+#define P_EE_AUDIO_SPDIFIN_CTRL3 ((volatile uint32_t *)0xfe05040c)
+#define P_EE_AUDIO_SPDIFIN_CTRL4 ((volatile uint32_t *)0xfe050410)
+#define P_EE_AUDIO_SPDIFIN_CTRL5 ((volatile uint32_t *)0xfe050414)
+#define P_EE_AUDIO_SPDIFIN_CTRL6 ((volatile uint32_t *)0xfe050418)
+#define P_EE_AUDIO_SPDIFIN_STAT0 ((volatile uint32_t *)0xfe05041c)
+#define P_EE_AUDIO_SPDIFIN_STAT1 ((volatile uint32_t *)0xfe050420)
+#define P_EE_AUDIO_SPDIFIN_STAT2 ((volatile uint32_t *)0xfe050424)
+#define P_EE_AUDIO_SPDIFIN_MUTE_VAL ((volatile uint32_t *)0xfe050428)
+#define P_EE_AUDIO_RESAMPLEA_CTRL0 ((volatile uint32_t *)0xfe050440)
+#define P_EE_AUDIO_RESAMPLEA_CTRL1 ((volatile uint32_t *)0xfe050444)
+#define P_EE_AUDIO_RESAMPLEA_CTRL2 ((volatile uint32_t *)0xfe050448)
+#define P_EE_AUDIO_RESAMPLEA_CTRL3 ((volatile uint32_t *)0xfe05044c)
+#define P_EE_AUDIO_RESAMPLEA_COEF0 ((volatile uint32_t *)0xfe050450)
+#define P_EE_AUDIO_RESAMPLEA_COEF1 ((volatile uint32_t *)0xfe050454)
+#define P_EE_AUDIO_RESAMPLEA_COEF2 ((volatile uint32_t *)0xfe050458)
+#define P_EE_AUDIO_RESAMPLEA_COEF3 ((volatile uint32_t *)0xfe05045c)
+#define P_EE_AUDIO_RESAMPLEA_COEF4 ((volatile uint32_t *)0xfe050460)
+#define P_EE_AUDIO_RESAMPLEA_STATUS1 ((volatile uint32_t *)0xfe050464)
+#define P_EE_AUDIO_SPDIFOUT_STAT ((volatile uint32_t *)0xfe050480)
+#define P_EE_AUDIO_SPDIFOUT_GAIN0 ((volatile uint32_t *)0xfe050484)
+#define P_EE_AUDIO_SPDIFOUT_GAIN1 ((volatile uint32_t *)0xfe050488)
+#define P_EE_AUDIO_SPDIFOUT_CTRL0 ((volatile uint32_t *)0xfe05048c)
+#define P_EE_AUDIO_SPDIFOUT_CTRL1 ((volatile uint32_t *)0xfe050490)
+#define P_EE_AUDIO_SPDIFOUT_PREAMB ((volatile uint32_t *)0xfe050494)
+#define P_EE_AUDIO_SPDIFOUT_SWAP ((volatile uint32_t *)0xfe050498)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS0 ((volatile uint32_t *)0xfe05049c)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS1 ((volatile uint32_t *)0xfe0504a0)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS2 ((volatile uint32_t *)0xfe0504a4)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS3 ((volatile uint32_t *)0xfe0504a8)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS4 ((volatile uint32_t *)0xfe0504ac)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS5 ((volatile uint32_t *)0xfe0504b0)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS6 ((volatile uint32_t *)0xfe0504b4)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS7 ((volatile uint32_t *)0xfe0504b8)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS8 ((volatile uint32_t *)0xfe0504bc)
+#define P_EE_AUDIO_SPDIFOUT_CHSTS9 ((volatile uint32_t *)0xfe0504c0)
+#define P_EE_AUDIO_SPDIFOUT_CHSTSA ((volatile uint32_t *)0xfe0504c4)
+#define P_EE_AUDIO_SPDIFOUT_CHSTSB ((volatile uint32_t *)0xfe0504c8)
+#define P_EE_AUDIO_SPDIFOUT_MUTE_VAL ((volatile uint32_t *)0xfe0504cc)
+#define P_EE_AUDIO_TDMOUT_A_CTRL0 ((volatile uint32_t *)0xfe050500)
+#define P_EE_AUDIO_TDMOUT_A_CTRL1 ((volatile uint32_t *)0xfe050504)
+#define P_EE_AUDIO_TDMOUT_A_SWAP0 ((volatile uint32_t *)0xfe050508)
+#define P_EE_AUDIO_TDMOUT_A_MASK0 ((volatile uint32_t *)0xfe05050c)
+#define P_EE_AUDIO_TDMOUT_A_MASK1 ((volatile uint32_t *)0xfe050510)
+#define P_EE_AUDIO_TDMOUT_A_MASK2 ((volatile uint32_t *)0xfe050514)
+#define P_EE_AUDIO_TDMOUT_A_MASK3 ((volatile uint32_t *)0xfe050518)
+#define P_EE_AUDIO_TDMOUT_A_STAT ((volatile uint32_t *)0xfe05051c)
+#define P_EE_AUDIO_TDMOUT_A_GAIN0 ((volatile uint32_t *)0xfe050520)
+#define P_EE_AUDIO_TDMOUT_A_GAIN1 ((volatile uint32_t *)0xfe050524)
+#define P_EE_AUDIO_TDMOUT_A_MUTE_VAL ((volatile uint32_t *)0xfe050528)
+#define P_EE_AUDIO_TDMOUT_A_MUTE0 ((volatile uint32_t *)0xfe05052c)
+#define P_EE_AUDIO_TDMOUT_A_MUTE1 ((volatile uint32_t *)0xfe050530)
+#define P_EE_AUDIO_TDMOUT_A_MUTE2 ((volatile uint32_t *)0xfe050534)
+#define P_EE_AUDIO_TDMOUT_A_MUTE3 ((volatile uint32_t *)0xfe050538)
+#define P_EE_AUDIO_TDMOUT_A_MASK_VAL ((volatile uint32_t *)0xfe05053c)
+#define P_EE_AUDIO_TDMOUT_B_CTRL0 ((volatile uint32_t *)0xfe050540)
+#define P_EE_AUDIO_TDMOUT_B_CTRL1 ((volatile uint32_t *)0xfe050544)
+#define P_EE_AUDIO_TDMOUT_B_SWAP0 ((volatile uint32_t *)0xfe050548)
+#define P_EE_AUDIO_TDMOUT_B_MASK0 ((volatile uint32_t *)0xfe05054c)
+#define P_EE_AUDIO_TDMOUT_B_MASK1 ((volatile uint32_t *)0xfe050550)
+#define P_EE_AUDIO_TDMOUT_B_MASK2 ((volatile uint32_t *)0xfe050554)
+#define P_EE_AUDIO_TDMOUT_B_MASK3 ((volatile uint32_t *)0xfe050558)
+#define P_EE_AUDIO_TDMOUT_B_STAT ((volatile uint32_t *)0xfe05055c)
+#define P_EE_AUDIO_TDMOUT_B_GAIN0 ((volatile uint32_t *)0xfe050560)
+#define P_EE_AUDIO_TDMOUT_B_GAIN1 ((volatile uint32_t *)0xfe050564)
+#define P_EE_AUDIO_TDMOUT_B_MUTE_VAL ((volatile uint32_t *)0xfe050568)
+#define P_EE_AUDIO_TDMOUT_B_MUTE0 ((volatile uint32_t *)0xfe05056c)
+#define P_EE_AUDIO_TDMOUT_B_MUTE1 ((volatile uint32_t *)0xfe050570)
+#define P_EE_AUDIO_TDMOUT_B_MUTE2 ((volatile uint32_t *)0xfe050574)
+#define P_EE_AUDIO_TDMOUT_B_MUTE3 ((volatile uint32_t *)0xfe050578)
+#define P_EE_AUDIO_TDMOUT_B_MASK_VAL ((volatile uint32_t *)0xfe05057c)
+#define P_EE_AUDIO_TDMOUT_C_CTRL0 ((volatile uint32_t *)0xfe050580)
+#define P_EE_AUDIO_TDMOUT_C_CTRL1 ((volatile uint32_t *)0xfe050584)
+#define P_EE_AUDIO_TDMOUT_C_SWAP0 ((volatile uint32_t *)0xfe050588)
+#define P_EE_AUDIO_TDMOUT_C_MASK0 ((volatile uint32_t *)0xfe05058c)
+#define P_EE_AUDIO_TDMOUT_C_MASK1 ((volatile uint32_t *)0xfe050590)
+#define P_EE_AUDIO_TDMOUT_C_MASK2 ((volatile uint32_t *)0xfe050594)
+#define P_EE_AUDIO_TDMOUT_C_MASK3 ((volatile uint32_t *)0xfe050598)
+#define P_EE_AUDIO_TDMOUT_C_STAT ((volatile uint32_t *)0xfe05059c)
+#define P_EE_AUDIO_TDMOUT_C_GAIN0 ((volatile uint32_t *)0xfe0505a0)
+#define P_EE_AUDIO_TDMOUT_C_GAIN1 ((volatile uint32_t *)0xfe0505a4)
+#define P_EE_AUDIO_TDMOUT_C_MUTE_VAL ((volatile uint32_t *)0xfe0505a8)
+#define P_EE_AUDIO_TDMOUT_C_MUTE0 ((volatile uint32_t *)0xfe0505ac)
+#define P_EE_AUDIO_TDMOUT_C_MUTE1 ((volatile uint32_t *)0xfe0505b0)
+#define P_EE_AUDIO_TDMOUT_C_MUTE2 ((volatile uint32_t *)0xfe0505b4)
+#define P_EE_AUDIO_TDMOUT_C_MUTE3 ((volatile uint32_t *)0xfe0505b8)
+#define P_EE_AUDIO_TDMOUT_C_MASK_VAL ((volatile uint32_t *)0xfe0505bc)
+//`define EE_AUDIO_POW_DET_CTRL0 10'h180
+//`define EE_AUDIO_POW_DET_CTRL1 10'h181
+//`define EE_AUDIO_POW_DET_TH_HI 10'h182
+//`define EE_AUDIO_POW_DET_TH_LO 10'h183
+//`define EE_AUDIO_POW_DET_VALUE 10'h184
+#define P_EE_AUDIO_SECURITY_CTRL0 ((volatile uint32_t *)0xfe050640)
+#define P_EE_AUDIO_SECURITY_CTRL1 ((volatile uint32_t *)0xfe050644)
+#define P_EE_AUDIO_SPDIFOUT_B_STAT ((volatile uint32_t *)0xfe050680)
+#define P_EE_AUDIO_SPDIFOUT_B_GAIN0 ((volatile uint32_t *)0xfe050684)
+#define P_EE_AUDIO_SPDIFOUT_B_GAIN1 ((volatile uint32_t *)0xfe050688)
+#define P_EE_AUDIO_SPDIFOUT_B_CTRL0 ((volatile uint32_t *)0xfe05068c)
+#define P_EE_AUDIO_SPDIFOUT_B_CTRL1 ((volatile uint32_t *)0xfe050690)
+#define P_EE_AUDIO_SPDIFOUT_B_PREAMB ((volatile uint32_t *)0xfe050694)
+#define P_EE_AUDIO_SPDIFOUT_B_SWAP ((volatile uint32_t *)0xfe050698)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS0 ((volatile uint32_t *)0xfe05069c)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS1 ((volatile uint32_t *)0xfe0506a0)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS2 ((volatile uint32_t *)0xfe0506a4)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS3 ((volatile uint32_t *)0xfe0506a8)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS4 ((volatile uint32_t *)0xfe0506ac)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS5 ((volatile uint32_t *)0xfe0506b0)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS6 ((volatile uint32_t *)0xfe0506b4)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS7 ((volatile uint32_t *)0xfe0506b8)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS8 ((volatile uint32_t *)0xfe0506bc)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTS9 ((volatile uint32_t *)0xfe0506c0)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTSA ((volatile uint32_t *)0xfe0506c4)
+#define P_EE_AUDIO_SPDIFOUT_B_CHSTSB ((volatile uint32_t *)0xfe0506c8)
+#define P_EE_AUDIO_SPDIFOUT_B_MUTE_VAL ((volatile uint32_t *)0xfe0506cc)
+#define P_EE_AUDIO_TORAM_CTRL0 ((volatile uint32_t *)0xfe050700)
+#define P_EE_AUDIO_TORAM_CTRL1 ((volatile uint32_t *)0xfe050704)
+#define P_EE_AUDIO_TORAM_START_ADDR ((volatile uint32_t *)0xfe050708)
+#define P_EE_AUDIO_TORAM_FINISH_ADDR ((volatile uint32_t *)0xfe05070c)
+#define P_EE_AUDIO_TORAM_INT_ADDR ((volatile uint32_t *)0xfe050710)
+#define P_EE_AUDIO_TORAM_STATUS1 ((volatile uint32_t *)0xfe050714)
+#define P_EE_AUDIO_TORAM_STATUS2 ((volatile uint32_t *)0xfe050718)
+#define P_EE_AUDIO_TORAM_INIT_ADDR ((volatile uint32_t *)0xfe05071c)
+#define P_EE_AUDIO_TOACODEC_CTRL0 ((volatile uint32_t *)0xfe050740)
+#define P_EE_AUDIO_TOHDMITX_CTRL0 ((volatile uint32_t *)0xfe050744)
+#define P_EE_AUDIO_TOVAD_CTRL0 ((volatile uint32_t *)0xfe050748)
+#define P_EE_AUDIO_FRATV_CTRL0 ((volatile uint32_t *)0xfe05074c)
+#define P_EE_AUDIO_RESAMPLEB_CTRL0 ((volatile uint32_t *)0xfe050780)
+#define P_EE_AUDIO_RESAMPLEB_CTRL1 ((volatile uint32_t *)0xfe050784)
+#define P_EE_AUDIO_RESAMPLEB_CTRL2 ((volatile uint32_t *)0xfe050788)
+#define P_EE_AUDIO_RESAMPLEB_CTRL3 ((volatile uint32_t *)0xfe05078c)
+#define P_EE_AUDIO_RESAMPLEB_COEF0 ((volatile uint32_t *)0xfe050790)
+#define P_EE_AUDIO_RESAMPLEB_COEF1 ((volatile uint32_t *)0xfe050794)
+#define P_EE_AUDIO_RESAMPLEB_COEF2 ((volatile uint32_t *)0xfe050798)
+#define P_EE_AUDIO_RESAMPLEB_COEF3 ((volatile uint32_t *)0xfe05079c)
+#define P_EE_AUDIO_RESAMPLEB_COEF4 ((volatile uint32_t *)0xfe0507a0)
+#define P_EE_AUDIO_RESAMPLEB_STATUS1 ((volatile uint32_t *)0xfe0507a4)
+#define P_EE_AUDIO_SPDIFIN_LB_CTRL0 ((volatile uint32_t *)0xfe0507c0)
+#define P_EE_AUDIO_SPDIFIN_LB_CTRL1 ((volatile uint32_t *)0xfe0507c4)
+#define P_EE_AUDIO_SPDIFIN_LB_CTRL6 ((volatile uint32_t *)0xfe0507d8)
+#define P_EE_AUDIO_SPDIFIN_LB_STAT0 ((volatile uint32_t *)0xfe0507dc)
+#define P_EE_AUDIO_SPDIFIN_LB_STAT1 ((volatile uint32_t *)0xfe0507e0)
+#define P_EE_AUDIO_SPDIFIN_LB_MUTE_VAL ((volatile uint32_t *)0xfe0507e8)
+#define P_EE_AUDIO_FRHDMIRX_CTRL0 ((volatile uint32_t *)0xfe050800)
+#define P_EE_AUDIO_FRHDMIRX_CTRL1 ((volatile uint32_t *)0xfe050804)
+#define P_EE_AUDIO_FRHDMIRX_CTRL2 ((volatile uint32_t *)0xfe050808)
+#define P_EE_AUDIO_FRHDMIRX_CTRL3 ((volatile uint32_t *)0xfe05080c)
+#define P_EE_AUDIO_FRHDMIRX_CTRL4 ((volatile uint32_t *)0xfe050810)
+#define P_EE_AUDIO_FRHDMIRX_CTRL5 ((volatile uint32_t *)0xfe050814)
+#define P_EE_AUDIO_FRHDMIRX_STAT0 ((volatile uint32_t *)0xfe050828)
+#define P_EE_AUDIO_FRHDMIRX_STAT1 ((volatile uint32_t *)0xfe05082c)
+#define P_EE_AUDIO_TODDR_D_CTRL0 ((volatile uint32_t *)0xfe050840)
+#define P_EE_AUDIO_TODDR_D_CTRL1 ((volatile uint32_t *)0xfe050844)
+#define P_EE_AUDIO_TODDR_D_START_ADDR ((volatile uint32_t *)0xfe050848)
+#define P_EE_AUDIO_TODDR_D_FINISH_ADDR ((volatile uint32_t *)0xfe05084c)
+#define P_EE_AUDIO_TODDR_D_INT_ADDR ((volatile uint32_t *)0xfe050850)
+#define P_EE_AUDIO_TODDR_D_STATUS1 ((volatile uint32_t *)0xfe050854)
+#define P_EE_AUDIO_TODDR_D_STATUS2 ((volatile uint32_t *)0xfe050858)
+#define P_EE_AUDIO_TODDR_D_START_ADDRB ((volatile uint32_t *)0xfe05085c)
+#define P_EE_AUDIO_TODDR_D_FINISH_ADDRB ((volatile uint32_t *)0xfe050860)
+#define P_EE_AUDIO_TODDR_D_INIT_ADDR ((volatile uint32_t *)0xfe050864)
+#define P_EE_AUDIO_TODDR_D_CTRL2 ((volatile uint32_t *)0xfe050868)
+#define P_EE_AUDIO_FRDDR_D_CTRL0 ((volatile uint32_t *)0xfe050880)
+#define P_EE_AUDIO_FRDDR_D_CTRL1 ((volatile uint32_t *)0xfe050884)
+#define P_EE_AUDIO_FRDDR_D_START_ADDR ((volatile uint32_t *)0xfe050888)
+#define P_EE_AUDIO_FRDDR_D_FINISH_ADDR ((volatile uint32_t *)0xfe05088c)
+#define P_EE_AUDIO_FRDDR_D_INT_ADDR ((volatile uint32_t *)0xfe050890)
+#define P_EE_AUDIO_FRDDR_D_STATUS1 ((volatile uint32_t *)0xfe050894)
+#define P_EE_AUDIO_FRDDR_D_STATUS2 ((volatile uint32_t *)0xfe050898)
+#define P_EE_AUDIO_FRDDR_D_START_ADDRB ((volatile uint32_t *)0xfe05089c)
+#define P_EE_AUDIO_FRDDR_D_FINISH_ADDRB ((volatile uint32_t *)0xfe0508a0)
+#define P_EE_AUDIO_FRDDR_D_INIT_ADDR ((volatile uint32_t *)0xfe0508a4)
+#define P_EE_AUDIO_FRDDR_D_CTRL2 ((volatile uint32_t *)0xfe0508a8)
+#define P_EE_AUDIO_LB_B_CTRL0 ((volatile uint32_t *)0xfe0508c0)
+#define P_EE_AUDIO_LB_B_CTRL1 ((volatile uint32_t *)0xfe0508c4)
+#define P_EE_AUDIO_LB_B_CTRL2 ((volatile uint32_t *)0xfe0508c8)
+#define P_EE_AUDIO_LB_B_CTRL3 ((volatile uint32_t *)0xfe0508cc)
+#define P_EE_AUDIO_LB_B_DAT_CH_ID0 ((volatile uint32_t *)0xfe0508d0)
+#define P_EE_AUDIO_LB_B_DAT_CH_ID1 ((volatile uint32_t *)0xfe0508d4)
+#define P_EE_AUDIO_LB_B_DAT_CH_ID2 ((volatile uint32_t *)0xfe0508d8)
+#define P_EE_AUDIO_LB_B_DAT_CH_ID3 ((volatile uint32_t *)0xfe0508dc)
+#define P_EE_AUDIO_LB_B_LB_CH_ID0 ((volatile uint32_t *)0xfe0508e0)
+#define P_EE_AUDIO_LB_B_LB_CH_ID1 ((volatile uint32_t *)0xfe0508e4)
+#define P_EE_AUDIO_LB_B_LB_CH_ID2 ((volatile uint32_t *)0xfe0508e8)
+#define P_EE_AUDIO_LB_B_LB_CH_ID3 ((volatile uint32_t *)0xfe0508ec)
+#define P_EE_AUDIO_LB_B_STS ((volatile uint32_t *)0xfe0508f0)
+#define P_EE_AUDIO_TODDR_E_CTRL0 ((volatile uint32_t *)0xfe050900)
+#define P_EE_AUDIO_TODDR_E_CTRL1 ((volatile uint32_t *)0xfe050904)
+#define P_EE_AUDIO_TODDR_E_START_ADDR ((volatile uint32_t *)0xfe050908)
+#define P_EE_AUDIO_TODDR_E_FINISH_ADDR ((volatile uint32_t *)0xfe05090c)
+#define P_EE_AUDIO_TODDR_E_INT_ADDR ((volatile uint32_t *)0xfe050910)
+#define P_EE_AUDIO_TODDR_E_STATUS1 ((volatile uint32_t *)0xfe050914)
+#define P_EE_AUDIO_TODDR_E_STATUS2 ((volatile uint32_t *)0xfe050918)
+#define P_EE_AUDIO_TODDR_E_START_ADDRB ((volatile uint32_t *)0xfe05091c)
+#define P_EE_AUDIO_TODDR_E_FINISH_ADDRB ((volatile uint32_t *)0xfe050920)
+#define P_EE_AUDIO_TODDR_E_INIT_ADDR ((volatile uint32_t *)0xfe050924)
+#define P_EE_AUDIO_TODDR_E_CTRL2 ((volatile uint32_t *)0xfe050928)
+#define P_EE_AUDIO_FRDDR_E_CTRL0 ((volatile uint32_t *)0xfe050940)
+#define P_EE_AUDIO_FRDDR_E_CTRL1 ((volatile uint32_t *)0xfe050944)
+#define P_EE_AUDIO_FRDDR_E_START_ADDR ((volatile uint32_t *)0xfe050948)
+#define P_EE_AUDIO_FRDDR_E_FINISH_ADDR ((volatile uint32_t *)0xfe05094c)
+#define P_EE_AUDIO_FRDDR_E_INT_ADDR ((volatile uint32_t *)0xfe050950)
+#define P_EE_AUDIO_FRDDR_E_STATUS1 ((volatile uint32_t *)0xfe050954)
+#define P_EE_AUDIO_FRDDR_E_STATUS2 ((volatile uint32_t *)0xfe050958)
+#define P_EE_AUDIO_FRDDR_E_START_ADDRB ((volatile uint32_t *)0xfe05095c)
+#define P_EE_AUDIO_FRDDR_E_FINISH_ADDRB ((volatile uint32_t *)0xfe050960)
+#define P_EE_AUDIO_FRDDR_E_INIT_ADDR ((volatile uint32_t *)0xfe050964)
+#define P_EE_AUDIO_FRDDR_E_CTRL2 ((volatile uint32_t *)0xfe050968)
+#define P_EE_AUDIO_TDMIN_A_SWAP1 ((volatile uint32_t *)0xfe050980)
+#define P_EE_AUDIO_TDMIN_A_MASK4 ((volatile uint32_t *)0xfe050984)
+#define P_EE_AUDIO_TDMIN_A_MASK5 ((volatile uint32_t *)0xfe050988)
+#define P_EE_AUDIO_TDMIN_A_MASK6 ((volatile uint32_t *)0xfe05098c)
+#define P_EE_AUDIO_TDMIN_A_MASK7 ((volatile uint32_t *)0xfe050990)
+#define P_EE_AUDIO_TDMIN_A_MUTE4 ((volatile uint32_t *)0xfe050994)
+#define P_EE_AUDIO_TDMIN_A_MUTE5 ((volatile uint32_t *)0xfe050998)
+#define P_EE_AUDIO_TDMIN_A_MUTE6 ((volatile uint32_t *)0xfe05099c)
+#define P_EE_AUDIO_TDMIN_A_MUTE7 ((volatile uint32_t *)0xfe0509a0)
+#define P_EE_AUDIO_TDMIN_B_SWAP1 ((volatile uint32_t *)0xfe0509c0)
+#define P_EE_AUDIO_TDMIN_B_MASK4 ((volatile uint32_t *)0xfe0509c4)
+#define P_EE_AUDIO_TDMIN_B_MASK5 ((volatile uint32_t *)0xfe0509c8)
+#define P_EE_AUDIO_TDMIN_B_MASK6 ((volatile uint32_t *)0xfe0509cc)
+#define P_EE_AUDIO_TDMIN_B_MASK7 ((volatile uint32_t *)0xfe0509d0)
+#define P_EE_AUDIO_TDMIN_B_MUTE4 ((volatile uint32_t *)0xfe0509d4)
+#define P_EE_AUDIO_TDMIN_B_MUTE5 ((volatile uint32_t *)0xfe0509d8)
+#define P_EE_AUDIO_TDMIN_B_MUTE6 ((volatile uint32_t *)0xfe0509dc)
+#define P_EE_AUDIO_TDMIN_B_MUTE7 ((volatile uint32_t *)0xfe0509e0)
+#define P_EE_AUDIO_TDMIN_C_SWAP1 ((volatile uint32_t *)0xfe050a00)
+#define P_EE_AUDIO_TDMIN_C_MASK4 ((volatile uint32_t *)0xfe050a04)
+#define P_EE_AUDIO_TDMIN_C_MASK5 ((volatile uint32_t *)0xfe050a08)
+#define P_EE_AUDIO_TDMIN_C_MASK6 ((volatile uint32_t *)0xfe050a0c)
+#define P_EE_AUDIO_TDMIN_C_MASK7 ((volatile uint32_t *)0xfe050a10)
+#define P_EE_AUDIO_TDMIN_C_MUTE4 ((volatile uint32_t *)0xfe050a14)
+#define P_EE_AUDIO_TDMIN_C_MUTE5 ((volatile uint32_t *)0xfe050a18)
+#define P_EE_AUDIO_TDMIN_C_MUTE6 ((volatile uint32_t *)0xfe050a1c)
+#define P_EE_AUDIO_TDMIN_C_MUTE7 ((volatile uint32_t *)0xfe050a20)
+#define P_EE_AUDIO_TDMIN_LB_SWAP1 ((volatile uint32_t *)0xfe050a40)
+#define P_EE_AUDIO_TDMIN_LB_MASK4 ((volatile uint32_t *)0xfe050a44)
+#define P_EE_AUDIO_TDMIN_LB_MASK5 ((volatile uint32_t *)0xfe050a48)
+#define P_EE_AUDIO_TDMIN_LB_MASK6 ((volatile uint32_t *)0xfe050a4c)
+#define P_EE_AUDIO_TDMIN_LB_MASK7 ((volatile uint32_t *)0xfe050a50)
+#define P_EE_AUDIO_TDMIN_LB_MUTE4 ((volatile uint32_t *)0xfe050a54)
+#define P_EE_AUDIO_TDMIN_LB_MUTE5 ((volatile uint32_t *)0xfe050a58)
+#define P_EE_AUDIO_TDMIN_LB_MUTE6 ((volatile uint32_t *)0xfe050a5c)
+#define P_EE_AUDIO_TDMIN_LB_MUTE7 ((volatile uint32_t *)0xfe050a60)
+#define P_EE_AUDIO_TDMOUT_A_CTRL2 ((volatile uint32_t *)0xfe050a80)
+#define P_EE_AUDIO_TDMOUT_A_SWAP1 ((volatile uint32_t *)0xfe050a84)
+#define P_EE_AUDIO_TDMOUT_A_GAIN2 ((volatile uint32_t *)0xfe050a88)
+#define P_EE_AUDIO_TDMOUT_A_GAIN3 ((volatile uint32_t *)0xfe050a8c)
+#define P_EE_AUDIO_TDMOUT_A_MASK4 ((volatile uint32_t *)0xfe050a90)
+#define P_EE_AUDIO_TDMOUT_A_MASK5 ((volatile uint32_t *)0xfe050a94)
+#define P_EE_AUDIO_TDMOUT_A_MASK6 ((volatile uint32_t *)0xfe050a98)
+#define P_EE_AUDIO_TDMOUT_A_MASK7 ((volatile uint32_t *)0xfe050a9c)
+#define P_EE_AUDIO_TDMOUT_A_MUTE4 ((volatile uint32_t *)0xfe050aa0)
+#define P_EE_AUDIO_TDMOUT_A_MUTE5 ((volatile uint32_t *)0xfe050aa4)
+#define P_EE_AUDIO_TDMOUT_A_MUTE6 ((volatile uint32_t *)0xfe050aa8)
+#define P_EE_AUDIO_TDMOUT_A_MUTE7 ((volatile uint32_t *)0xfe050aac)
+#define P_EE_AUDIO_TDMOUT_B_CTRL2 ((volatile uint32_t *)0xfe050ac0)
+#define P_EE_AUDIO_TDMOUT_B_SWAP1 ((volatile uint32_t *)0xfe050ac4)
+#define P_EE_AUDIO_TDMOUT_B_GAIN2 ((volatile uint32_t *)0xfe050ac8)
+#define P_EE_AUDIO_TDMOUT_B_GAIN3 ((volatile uint32_t *)0xfe050acc)
+#define P_EE_AUDIO_TDMOUT_B_MASK4 ((volatile uint32_t *)0xfe050ad0)
+#define P_EE_AUDIO_TDMOUT_B_MASK5 ((volatile uint32_t *)0xfe050ad4)
+#define P_EE_AUDIO_TDMOUT_B_MASK6 ((volatile uint32_t *)0xfe050ad8)
+#define P_EE_AUDIO_TDMOUT_B_MASK7 ((volatile uint32_t *)0xfe050adc)
+#define P_EE_AUDIO_TDMOUT_B_MUTE4 ((volatile uint32_t *)0xfe050ae0)
+#define P_EE_AUDIO_TDMOUT_B_MUTE5 ((volatile uint32_t *)0xfe050ae4)
+#define P_EE_AUDIO_TDMOUT_B_MUTE6 ((volatile uint32_t *)0xfe050ae8)
+#define P_EE_AUDIO_TDMOUT_B_MUTE7 ((volatile uint32_t *)0xfe050aec)
+#define P_EE_AUDIO_TDMOUT_C_CTRL2 ((volatile uint32_t *)0xfe050b00)
+#define P_EE_AUDIO_TDMOUT_C_SWAP1 ((volatile uint32_t *)0xfe050b04)
+#define P_EE_AUDIO_TDMOUT_C_GAIN2 ((volatile uint32_t *)0xfe050b08)
+#define P_EE_AUDIO_TDMOUT_C_GAIN3 ((volatile uint32_t *)0xfe050b0c)
+#define P_EE_AUDIO_TDMOUT_C_MASK4 ((volatile uint32_t *)0xfe050b10)
+#define P_EE_AUDIO_TDMOUT_C_MASK5 ((volatile uint32_t *)0xfe050b14)
+#define P_EE_AUDIO_TDMOUT_C_MASK6 ((volatile uint32_t *)0xfe050b18)
+#define P_EE_AUDIO_TDMOUT_C_MASK7 ((volatile uint32_t *)0xfe050b1c)
+#define P_EE_AUDIO_TDMOUT_C_MUTE4 ((volatile uint32_t *)0xfe050b20)
+#define P_EE_AUDIO_TDMOUT_C_MUTE5 ((volatile uint32_t *)0xfe050b24)
+#define P_EE_AUDIO_TDMOUT_C_MUTE6 ((volatile uint32_t *)0xfe050b28)
+#define P_EE_AUDIO_TDMOUT_C_MUTE7 ((volatile uint32_t *)0xfe050b2c)
+//========================================================================
+// PDM - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051000
+// -----------------------------------------------
+#define P_PDM_CTRL ((volatile uint32_t *)0xfe051000)
+//bit 31: PDM enable.
+//bit 30: invert the PDM_DCLK.
+//bit 29: output mode: 1: 24bits. 0: 32 bits.
+//bit 28: bypass mode. 1: bypass all filter. directly output the PDM input to DDR. 0: normal mode.
+//bit 27~9: not used.
+//bit 16:. PDM Asynchronous FIFO soft reset. write 1 to soft reset AFIFO.
+//bit 15:8 PDM channel reset. 0: to reset each PDM channel. 1: normal mode.
+//bit 7:0. PDM channel enable. each bit for one channel.
+#define P_PDM_HCIC_CTRL1 ((volatile uint32_t *)0xfe051004)
+//bit 31 hcic filter enable. 1 use sinc filter. 0 bypass input to output.
+//bit 29:24. hcic final gain shift parameter.
+//bit 23:16 hcic final gain multiplier.
+//bit 8:4 hcic down sample rate.
+//bit 3:0 hcic stage number. must be between 3 to 9.
+#define P_PDM_HCIC_CTRL2 ((volatile uint32_t *)0xfe051008)
+//Not used.
+#define P_PDM_F1_CTRL ((volatile uint32_t *)0xfe05100c)
+//bit 31 . filter 1 enable.
+//bit 16:15. f1 round mode. 2'b00 : sign bit at bit 49. 28bits output [49:22] round at bit 21. 32bits output [49:18]. 24bits output [49:26]
+// 2'b01 : sign bit at bit 50. 28bits output [50:23] round at bit 22. 32bits output [49:18]. 24bits output [49:26]
+// 2'b10 : sign bit at bit 51. 28bits output [51:24] round at bit 23 32bits output [49:18]. 24bits output [49:26].
+//bit 15:12. filter 1 down sample rate.
+//bit 8:0. filter 1 stage number.
+#define P_PDM_F2_CTRL ((volatile uint32_t *)0xfe051010)
+//bit 31 . filter 2 enable.
+//bit 16:15. f2 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23.
+//bit 15:12. filter 2 down sample rate.
+//bit 8:0. filter 2 stage number.
+#define P_PDM_F3_CTRL ((volatile uint32_t *)0xfe051014)
+//bit 31 . filter 3 enable.
+//bit 16:15. f3 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23.
+//bit 15:12. filter 3 down sample rate.
+//bit 8:0. filter 3 stage number.
+#define P_PDM_HPF_CTRL ((volatile uint32_t *)0xfe051018)
+//bit 31 High pass filter enable.
+//bit 20:16 high pass filter shift steps. 6~19 steps.
+//bit 15:0 high pass filter output factor.
+#define P_PDM_CHAN_CTRL ((volatile uint32_t *)0xfe05101c)
+//bit 31:24. chan3 data sample pointer vs edge of the PDM_DCLK.
+//bit 23:16 chan2 data sample pointer vs edge of the PDM_DCLK.
+//bit 15:8. chan1 data sample pointer vs edge of the PDM_DCLK.
+//bit 7:0 chan0 data sample pointer vs edge of the PDM_DCLK.
+#define P_PDM_CHAN_CTRL1 ((volatile uint32_t *)0xfe051020)
+//bit 31:24. chan7 data sample pointer vs edge of the PDM_DCLK.
+//bit 23:16 chan6 data sample pointer vs edge of the PDM_DCLK.
+//bit 15:8. chan5 data sample pointer vs edge of the PDM_DCLK.
+//bit 7:0 chan4 data sample pointer vs edge of the PDM_DCLK.
+#define P_PDM_COEFF_ADDR ((volatile uint32_t *)0xfe051024)
+// address of the write/read of coeff data.
+#define P_PDM_COEFF_DATA ((volatile uint32_t *)0xfe051028)
+//write/read data to coeff memory.
+#define P_PDM_CLKG_CTRL ((volatile uint32_t *)0xfe05102c)
+// auto clock gating control. 1: disable the clock gating function. the clock will awlays enabled. 0 : use RTL auto clock gating.
+//31:7 not used.
+//bit 6 filt_ctrl module auto clock gating control.
+//bit 5 sinc fifo module auto clock gating control.
+//bit 4 filter module auto clock gating control.
+//bit 3 apb module auto clock gating control.
+//bit 2 coeff memory module auto clock gating control.
+//bit 1 each channel module auto clock gating control.
+//bit 0 cts_pdm_clk auto clock gating control.
+#define P_PDM_STS ((volatile uint32_t *)0xfe051030)
+//bit 1 HPF filter output overflow. means the PCLK is too slow.
+//bit 0 HCIC filter output overflow. means the CTS_PDM_CLK is too slow. can't finished the filter function.
+#define P_PDM_MUTE_VALUE ((volatile uint32_t *)0xfe051034)
+#define P_PDM_MASK_NUM ((volatile uint32_t *)0xfe051038)
+//========================================================================
+// EQ DRC - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe052000
+// -----------------------------------------------
+#define P_AED_COEF_RAM_CNTL ((volatile uint32_t *)0xfe052000)
+#define P_AED_COEF_RAM_DATA ((volatile uint32_t *)0xfe052004)
+#define P_AED_EQ_EN ((volatile uint32_t *)0xfe052008)
+#define P_AED_EQ_TAP_CNTL ((volatile uint32_t *)0xfe05200c)
+#define P_AED_EQ_VOLUME ((volatile uint32_t *)0xfe052010)
+#define P_AED_EQ_VOLUME_SLEW_CNT ((volatile uint32_t *)0xfe052014)
+#define P_AED_MUTE ((volatile uint32_t *)0xfe052018)
+#define P_AED_DRC_CNTL ((volatile uint32_t *)0xfe05201c)
+#define P_AED_DRC_RMS_COEF0 ((volatile uint32_t *)0xfe052020)
+#define P_AED_DRC_RMS_COEF1 ((volatile uint32_t *)0xfe052024)
+#define P_AED_DRC_THD0 ((volatile uint32_t *)0xfe052028)
+#define P_AED_DRC_THD1 ((volatile uint32_t *)0xfe05202c)
+#define P_AED_DRC_THD2 ((volatile uint32_t *)0xfe052030)
+#define P_AED_DRC_THD3 ((volatile uint32_t *)0xfe052034)
+#define P_AED_DRC_THD4 ((volatile uint32_t *)0xfe052038)
+#define P_AED_DRC_K0 ((volatile uint32_t *)0xfe05203c)
+#define P_AED_DRC_K1 ((volatile uint32_t *)0xfe052040)
+#define P_AED_DRC_K2 ((volatile uint32_t *)0xfe052044)
+#define P_AED_DRC_K3 ((volatile uint32_t *)0xfe052048)
+#define P_AED_DRC_K4 ((volatile uint32_t *)0xfe05204c)
+#define P_AED_DRC_K5 ((volatile uint32_t *)0xfe052050)
+#define P_AED_DRC_THD_OUT0 ((volatile uint32_t *)0xfe052054)
+#define P_AED_DRC_THD_OUT1 ((volatile uint32_t *)0xfe052058)
+#define P_AED_DRC_THD_OUT2 ((volatile uint32_t *)0xfe05205c)
+#define P_AED_DRC_THD_OUT3 ((volatile uint32_t *)0xfe052060)
+#define P_AED_DRC_OFFSET ((volatile uint32_t *)0xfe052064)
+#define P_AED_DRC_RELEASE_COEF00 ((volatile uint32_t *)0xfe052068)
+#define P_AED_DRC_RELEASE_COEF01 ((volatile uint32_t *)0xfe05206c)
+#define P_AED_DRC_RELEASE_COEF10 ((volatile uint32_t *)0xfe052070)
+#define P_AED_DRC_RELEASE_COEF11 ((volatile uint32_t *)0xfe052074)
+#define P_AED_DRC_RELEASE_COEF20 ((volatile uint32_t *)0xfe052078)
+#define P_AED_DRC_RELEASE_COEF21 ((volatile uint32_t *)0xfe05207c)
+#define P_AED_DRC_RELEASE_COEF30 ((volatile uint32_t *)0xfe052080)
+#define P_AED_DRC_RELEASE_COEF31 ((volatile uint32_t *)0xfe052084)
+#define P_AED_DRC_RELEASE_COEF40 ((volatile uint32_t *)0xfe052088)
+#define P_AED_DRC_RELEASE_COEF41 ((volatile uint32_t *)0xfe05208c)
+#define P_AED_DRC_RELEASE_COEF50 ((volatile uint32_t *)0xfe052090)
+#define P_AED_DRC_RELEASE_COEF51 ((volatile uint32_t *)0xfe052094)
+#define P_AED_DRC_ATTACK_COEF00 ((volatile uint32_t *)0xfe052098)
+#define P_AED_DRC_ATTACK_COEF01 ((volatile uint32_t *)0xfe05209c)
+#define P_AED_DRC_ATTACK_COEF10 ((volatile uint32_t *)0xfe0520a0)
+#define P_AED_DRC_ATTACK_COEF11 ((volatile uint32_t *)0xfe0520a4)
+#define P_AED_DRC_ATTACK_COEF20 ((volatile uint32_t *)0xfe0520a8)
+#define P_AED_DRC_ATTACK_COEF21 ((volatile uint32_t *)0xfe0520ac)
+#define P_AED_DRC_ATTACK_COEF30 ((volatile uint32_t *)0xfe0520b0)
+#define P_AED_DRC_ATTACK_COEF31 ((volatile uint32_t *)0xfe0520b4)
+#define P_AED_DRC_ATTACK_COEF40 ((volatile uint32_t *)0xfe0520b8)
+#define P_AED_DRC_ATTACK_COEF41 ((volatile uint32_t *)0xfe0520bc)
+#define P_AED_DRC_ATTACK_COEF50 ((volatile uint32_t *)0xfe0520c0)
+#define P_AED_DRC_ATTACK_COEF51 ((volatile uint32_t *)0xfe0520c4)
+#define P_AED_DRC_LOOPBACK_CNTL ((volatile uint32_t *)0xfe0520c8)
+#define P_AED_MDRC_CNTL ((volatile uint32_t *)0xfe0520cc)
+#define P_AED_MDRC_RMS_COEF00 ((volatile uint32_t *)0xfe0520d0)
+#define P_AED_MDRC_RMS_COEF01 ((volatile uint32_t *)0xfe0520d4)
+#define P_AED_MDRC_RELEASE_COEF00 ((volatile uint32_t *)0xfe0520d8)
+#define P_AED_MDRC_RELEASE_COEF01 ((volatile uint32_t *)0xfe0520dc)
+#define P_AED_MDRC_ATTACK_COEF00 ((volatile uint32_t *)0xfe0520e0)
+#define P_AED_MDRC_ATTACK_COEF01 ((volatile uint32_t *)0xfe0520e4)
+#define P_AED_MDRC_THD0 ((volatile uint32_t *)0xfe0520e8)
+#define P_AED_MDRC_K0 ((volatile uint32_t *)0xfe0520ec)
+#define P_AED_MDRC_LOW_GAIN ((volatile uint32_t *)0xfe0520f0)
+#define P_AED_MDRC_OFFSET0 ((volatile uint32_t *)0xfe0520f4)
+#define P_AED_MDRC_RMS_COEF10 ((volatile uint32_t *)0xfe0520f8)
+#define P_AED_MDRC_RMS_COEF11 ((volatile uint32_t *)0xfe0520fc)
+#define P_AED_MDRC_RELEASE_COEF10 ((volatile uint32_t *)0xfe052100)
+#define P_AED_MDRC_RELEASE_COEF11 ((volatile uint32_t *)0xfe052104)
+#define P_AED_MDRC_ATTACK_COEF10 ((volatile uint32_t *)0xfe052108)
+#define P_AED_MDRC_ATTACK_COEF11 ((volatile uint32_t *)0xfe05210c)
+#define P_AED_MDRC_THD1 ((volatile uint32_t *)0xfe052110)
+#define P_AED_MDRC_K1 ((volatile uint32_t *)0xfe052114)
+#define P_AED_MDRC_OFFSET1 ((volatile uint32_t *)0xfe052118)
+#define P_AED_MDRC_MID_GAIN ((volatile uint32_t *)0xfe05211c)
+#define P_AED_MDRC_RMS_COEF20 ((volatile uint32_t *)0xfe052120)
+#define P_AED_MDRC_RMS_COEF21 ((volatile uint32_t *)0xfe052124)
+#define P_AED_MDRC_RELEASE_COEF20 ((volatile uint32_t *)0xfe052128)
+#define P_AED_MDRC_RELEASE_COEF21 ((volatile uint32_t *)0xfe05212c)
+#define P_AED_MDRC_ATTACK_COEF20 ((volatile uint32_t *)0xfe052130)
+#define P_AED_MDRC_ATTACK_COEF21 ((volatile uint32_t *)0xfe052134)
+#define P_AED_MDRC_THD2 ((volatile uint32_t *)0xfe052138)
+#define P_AED_MDRC_K2 ((volatile uint32_t *)0xfe05213c)
+#define P_AED_MDRC_OFFSET2 ((volatile uint32_t *)0xfe052140)
+#define P_AED_MDRC_HIGH_GAIN ((volatile uint32_t *)0xfe052144)
+#define P_AED_ED_CNTL ((volatile uint32_t *)0xfe052148)
+#define P_AED_DC_EN ((volatile uint32_t *)0xfe05214c)
+#define P_AED_ND_LOW_THD ((volatile uint32_t *)0xfe052150)
+#define P_AED_ND_HIGH_THD ((volatile uint32_t *)0xfe052154)
+#define P_AED_ND_CNT_THD ((volatile uint32_t *)0xfe052158)
+#define P_AED_ND_SUM_NUM ((volatile uint32_t *)0xfe05215c)
+#define P_AED_ND_CZ_NUM ((volatile uint32_t *)0xfe052160)
+#define P_AED_ND_SUM_THD0 ((volatile uint32_t *)0xfe052164)
+#define P_AED_ND_SUM_THD1 ((volatile uint32_t *)0xfe052168)
+#define P_AED_ND_CZ_THD0 ((volatile uint32_t *)0xfe05216c)
+#define P_AED_ND_CZ_THD1 ((volatile uint32_t *)0xfe052170)
+#define P_AED_ND_COND_CNTL ((volatile uint32_t *)0xfe052174)
+#define P_AED_ND_RELEASE_COEF0 ((volatile uint32_t *)0xfe052178)
+#define P_AED_ND_RELEASE_COEF1 ((volatile uint32_t *)0xfe05217c)
+#define P_AED_ND_ATTACK_COEF0 ((volatile uint32_t *)0xfe052180)
+#define P_AED_ND_ATTACK_COEF1 ((volatile uint32_t *)0xfe052184)
+#define P_AED_ND_CNTL ((volatile uint32_t *)0xfe052188)
+#define P_AED_MIX0_LL ((volatile uint32_t *)0xfe05218c)
+#define P_AED_MIX0_RL ((volatile uint32_t *)0xfe052190)
+#define P_AED_MIX0_LR ((volatile uint32_t *)0xfe052194)
+#define P_AED_MIX0_RR ((volatile uint32_t *)0xfe052198)
+#define P_AED_CLIP_THD ((volatile uint32_t *)0xfe05219c)
+#define P_AED_CH1_ND_SUM_OUT ((volatile uint32_t *)0xfe0521a0)
+#define P_AED_CH2_ND_SUM_OUT ((volatile uint32_t *)0xfe0521a4)
+#define P_AED_CH1_ND_CZ_OUT ((volatile uint32_t *)0xfe0521a8)
+#define P_AED_CH2_ND_CZ_OUT ((volatile uint32_t *)0xfe0521ac)
+#define P_AED_NOISE_STATUS ((volatile uint32_t *)0xfe0521b0)
+#define P_AED_POW_CURRENT_S0 ((volatile uint32_t *)0xfe0521b4)
+#define P_AED_POW_CURRENT_S1 ((volatile uint32_t *)0xfe0521b8)
+#define P_AED_POW_CURRENT_S2 ((volatile uint32_t *)0xfe0521bc)
+#define P_AED_POW_OUT0 ((volatile uint32_t *)0xfe0521c0)
+#define P_AED_POW_OUT1 ((volatile uint32_t *)0xfe0521c4)
+#define P_AED_POW_OUT2 ((volatile uint32_t *)0xfe0521c8)
+#define P_AED_POW_ADJ_INDEX0 ((volatile uint32_t *)0xfe0521cc)
+#define P_AED_POW_ADJ_INDEX1 ((volatile uint32_t *)0xfe0521d0)
+#define P_AED_POW_ADJ_INDEX2 ((volatile uint32_t *)0xfe0521d4)
+#define P_AED_DRC_GAIN_INDEX0 ((volatile uint32_t *)0xfe0521d8)
+#define P_AED_DRC_GAIN_INDEX1 ((volatile uint32_t *)0xfe0521dc)
+#define P_AED_DRC_GAIN_INDEX2 ((volatile uint32_t *)0xfe0521e0)
+#define P_AED_CH1_VOLUME_STATE ((volatile uint32_t *)0xfe0521e4)
+#define P_AED_CH2_VOLUME_STATE ((volatile uint32_t *)0xfe0521e8)
+#define P_AED_CH1_VOLUME_GAIN ((volatile uint32_t *)0xfe0521ec)
+#define P_AED_CH2_VOLUME_GAIN ((volatile uint32_t *)0xfe0521f0)
+#define P_AED_FULL_POW_CURRENT ((volatile uint32_t *)0xfe0521f4)
+#define P_AED_FULL_POW_OUT ((volatile uint32_t *)0xfe0521f8)
+#define P_AED_FULL_POW_ADJ ((volatile uint32_t *)0xfe0521fc)
+#define P_AED_FULL_DRC_GAIN ((volatile uint32_t *)0xfe052200)
+#define P_AED_MASTER_VOLUME_STATE ((volatile uint32_t *)0xfe052204)
+#define P_AED_MASTER_VOLUME_GAIN ((volatile uint32_t *)0xfe052208)
+#define P_AED_TOP_CTL0 ((volatile uint32_t *)0xfe05220c)
+#define P_AED_TOP_CTL1 ((volatile uint32_t *)0xfe052210)
+#define P_AED_TOP_CTL2 ((volatile uint32_t *)0xfe052214)
+//========================================================================
+// AUDIO locker - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051400
+// -----------------------------------------------
+#define P_AUD_LOCK_EN ((volatile uint32_t *)0xfe051400)
+#define P_AUD_LOCK_SW_RESET ((volatile uint32_t *)0xfe051404)
+#define P_AUD_LOCK_SW_LATCH ((volatile uint32_t *)0xfe051408)
+#define P_AUD_LOCK_HW_LATCH ((volatile uint32_t *)0xfe05140c)
+#define P_AUD_LOCK_REFCLK_SRC ((volatile uint32_t *)0xfe051410)
+#define P_AUD_LOCK_REFCLK_LAT_INT ((volatile uint32_t *)0xfe051414)
+#define P_AUD_LOCK_IMCLK_LAT_INT ((volatile uint32_t *)0xfe051418)
+#define P_AUD_LOCK_OMCLK_LAT_INT ((volatile uint32_t *)0xfe05141c)
+#define P_AUD_LOCK_REFCLK_DS_INT ((volatile uint32_t *)0xfe051420)
+#define P_AUD_LOCK_IMCLK_DS_INT ((volatile uint32_t *)0xfe051424)
+#define P_AUD_LOCK_OMCLK_DS_INT ((volatile uint32_t *)0xfe051428)
+#define P_AUD_LOCK_INT_CLR ((volatile uint32_t *)0xfe05142c)
+#define P_AUD_LOCK_GCLK_CTRL ((volatile uint32_t *)0xfe051430)
+#define P_AUD_LOCK_INT_CTRL ((volatile uint32_t *)0xfe051434)
+#define P_RO_REF2IMCLK_CNT_L ((volatile uint32_t *)0xfe051440)
+#define P_RO_REF2IMCLK_CNT_H ((volatile uint32_t *)0xfe051444)
+#define P_RO_REF2OMCLK_CNT_L ((volatile uint32_t *)0xfe051448)
+#define P_RO_REF2OMCLK_CNT_H ((volatile uint32_t *)0xfe05144c)
+#define P_RO_IMCLK2REF_CNT_L ((volatile uint32_t *)0xfe051450)
+#define P_RO_IMCLK2REF_CNT_H ((volatile uint32_t *)0xfe051454)
+#define P_RO_OMCLK2REF_CNT_L ((volatile uint32_t *)0xfe051458)
+#define P_RO_OMCLK2REF_CNT_H ((volatile uint32_t *)0xfe05145c)
+#define P_RO_REFCLK_PKG_CNT ((volatile uint32_t *)0xfe051460)
+#define P_RO_IMCLK_PKG_CNT ((volatile uint32_t *)0xfe051464)
+#define P_RO_OMCLK_PKG_CNT ((volatile uint32_t *)0xfe051468)
+#define P_RO_AUD_LOCK_INT_STATUS ((volatile uint32_t *)0xfe05146c)
+//========================================================================
+// AUDIO VAD - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051800
+// -----------------------------------------------
+//
+// Reading file: VAD_REG.h
+//
+#define P_VAD_TOP_CTRL0 ((volatile uint32_t *)0xfe051800)
+#define P_VAD_TOP_CTRL1 ((volatile uint32_t *)0xfe051804)
+#define P_VAD_TOP_CTRL2 ((volatile uint32_t *)0xfe051808)
+#define P_VAD_FIR_CTRL ((volatile uint32_t *)0xfe05180c)
+#define P_VAD_FIR_EMP ((volatile uint32_t *)0xfe051810)
+#define P_VAD_FIR_COEF0 ((volatile uint32_t *)0xfe051814)
+#define P_VAD_FIR_COEF1 ((volatile uint32_t *)0xfe051818)
+#define P_VAD_FIR_COEF2 ((volatile uint32_t *)0xfe05181c)
+#define P_VAD_FIR_COEF3 ((volatile uint32_t *)0xfe051820)
+#define P_VAD_FIR_COEF4 ((volatile uint32_t *)0xfe051824)
+#define P_VAD_FIR_COEF5 ((volatile uint32_t *)0xfe051828)
+#define P_VAD_FIR_COEF6 ((volatile uint32_t *)0xfe05182c)
+#define P_VAD_FIR_COEF7 ((volatile uint32_t *)0xfe051830)
+#define P_VAD_FIR_COEF8 ((volatile uint32_t *)0xfe051834)
+#define P_VAD_FIR_COEF9 ((volatile uint32_t *)0xfe051838)
+#define P_VAD_FIR_COEF10 ((volatile uint32_t *)0xfe05183c)
+#define P_VAD_FIR_COEF11 ((volatile uint32_t *)0xfe051840)
+#define P_VAD_FIR_COEF12 ((volatile uint32_t *)0xfe051844)
+#define P_VAD_FRAME_CTRL0 ((volatile uint32_t *)0xfe051848)
+#define P_VAD_FRAME_CTRL1 ((volatile uint32_t *)0xfe05184c)
+#define P_VAD_FRAME_CTRL2 ((volatile uint32_t *)0xfe051850)
+#define P_VAD_CEP_CTRL0 ((volatile uint32_t *)0xfe051854)
+#define P_VAD_CEP_CTRL1 ((volatile uint32_t *)0xfe051858)
+#define P_VAD_CEP_CTRL2 ((volatile uint32_t *)0xfe05185c)
+#define P_VAD_CEP_CTRL3 ((volatile uint32_t *)0xfe051860)
+#define P_VAD_CEP_CTRL4 ((volatile uint32_t *)0xfe051864)
+#define P_VAD_CEP_CTRL5 ((volatile uint32_t *)0xfe051868)
+#define P_VAD_DEC_CTRL ((volatile uint32_t *)0xfe05186c)
+#define P_VAD_TOP_STS0 ((volatile uint32_t *)0xfe051870)
+#define P_VAD_TOP_STS1 ((volatile uint32_t *)0xfe051874)
+#define P_VAD_TOP_STS2 ((volatile uint32_t *)0xfe051878)
+#define P_VAD_FIR_STS0 ((volatile uint32_t *)0xfe05187c)
+#define P_VAD_FIR_STS1 ((volatile uint32_t *)0xfe051880)
+#define P_VAD_POW_STS0 ((volatile uint32_t *)0xfe051884)
+#define P_VAD_POW_STS1 ((volatile uint32_t *)0xfe051888)
+#define P_VAD_POW_STS2 ((volatile uint32_t *)0xfe05188c)
+#define P_VAD_FFT_STS0 ((volatile uint32_t *)0xfe051890)
+#define P_VAD_FFT_STS1 ((volatile uint32_t *)0xfe051894)
+#define P_VAD_SPE_STS0 ((volatile uint32_t *)0xfe051898)
+#define P_VAD_SPE_STS1 ((volatile uint32_t *)0xfe05189c)
+#define P_VAD_SPE_STS2 ((volatile uint32_t *)0xfe0518a0)
+#define P_VAD_SPE_STS3 ((volatile uint32_t *)0xfe0518a4)
+#define P_VAD_DEC_STS0 ((volatile uint32_t *)0xfe0518a8)
+#define P_VAD_DEC_STS1 ((volatile uint32_t *)0xfe0518ac)
+#define P_VAD_LUT_CTRL ((volatile uint32_t *)0xfe0518b0)
+#define P_VAD_LUT_WR ((volatile uint32_t *)0xfe0518b4)
+#define P_VAD_LUT_RD ((volatile uint32_t *)0xfe0518b8)
+#define P_VAD_IN_SEL0 ((volatile uint32_t *)0xfe0518bc)
+#define P_VAD_IN_SEL1 ((volatile uint32_t *)0xfe0518c0)
+#define P_VAD_TO_DDR ((volatile uint32_t *)0xfe0518c4)
+//
+// Closing file: VAD_REG.h
+//
+//========================================================================
+// AUDIO RESAMPLEA - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051c00
+// -----------------------------------------------
+//
+// Reading file: RESAMPLE.h
+//
+#define P_AUDIO_RSAMP_CTRL0 ((volatile uint32_t *)0xfe051c00)
+//Bit 31:3 reserved
+//Bit 2 reg_lock_rst //unsigned , default =0;
+//Bit 1 reg_rsamp_rst //unsigned , default =0;
+//Bit 0 reg_sw_rst //unsigned , default =0;
+#define P_AUDIO_RSAMP_CTRL1 ((volatile uint32_t *)0xfe051c04)
+//Bit 31:26 reserved //unsigned , default =0;
+//Bit 25 reg_rsamp_rst_sel //unsigned , default =0;
+//Bit 24 reg_module_bypas //unsigned , default =0;
+//Bit 23:18 reg_gclk_ctrl //unsigned , default =0;
+//Bit 17:13 reg_in_msb //unsigned , default =23;
+//Bit 12 reg_output_en //unsigned , default =0;
+//Bit 11 reg_rsamp_en //unsigned , default =0;
+//Bit 10 reg_filt_en //unsigned , default =0;
+//Bit 9 reg_post_en //unsigned , default =0;
+//Bit 8 reg_inp_mux_mode //unsigned , default =0;
+//Bit 7:4 reserved //unsigned , default =2;
+//Bit 3:0 reg_inp_mux //unsigned , default =0;
+#define P_AUDIO_RSAMP_CTRL2 ((volatile uint32_t *)0xfe051c08)
+//Bit 31:30 reserved //unsigned , default =0;
+//Bit 29:24 reg_chx_size //unsigned , default =2;
+//Bit 23:18 reserved //unsigned , default =0;
+//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4
+//Bit 15:8 reg_filt_tap //unsigned , default =63;
+//Bit 7:0 reg_intp_tap //unsigned , default =63;
+#define P_AUDIO_RSAMP_PHSINIT ((volatile uint32_t *)0xfe051c0c)
+//Bit 31:28 reserved //unsigned , default = 0;
+//Bit 27:0 reg_init_phs //unsigned , default = 0;
+#define P_AUDIO_RSAMP_PHSSTEP ((volatile uint32_t *)0xfe051c10)
+//Bit 31 reserved //unsigned , default = 0;
+//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000
+#define P_AUDIO_RSAMP_SHIFT ((volatile uint32_t *)0xfe051c14)
+//Bit 31:24 reg_rsft_iir //unsigned , default = 23;
+//Bit 23:16 reg_rsft_blnd //unsigned , default = 21;
+//Bit 15:8 reg_rsft_sinc //unsigned , default = 31;
+//Bit 7:0 reg_rsft_aa //unsigned , default = 31;
+#define P_AUDIO_RSAMP_ADJ_CTRL0 ((volatile uint32_t *)0xfe051c18)
+//Bit 31:3 reserved //unsigned
+//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0;
+//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0;
+//Bit 0 reg_rsamp_adj_en //unsigned , default = 0;
+#define P_AUDIO_RSAMP_ADJ_CTRL1 ((volatile uint32_t *)0xfe051c1c)
+//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8;
+//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768;
+#define P_AUDIO_RSAMP_ADJ_SFT ((volatile uint32_t *)0xfe051c20)
+//Bit 31:30 reserved //unsigned , default = 0;
+//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0;
+//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9;
+//Bit 23:21 reserved //unsigned , default = 0;
+//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1;
+//Bit 15:13 reserved //unsigned , default = 0;
+//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6;
+//Bit 7:6 reserved //unsigned , default = 0;
+//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12;
+#define P_AUDIO_RSAMP_ADJ_IDET_LEN ((volatile uint32_t *)0xfe051c24)
+//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000;
+#define P_AUDIO_RSAMP_ADJ_FORCE ((volatile uint32_t *)0xfe051c28)
+//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8;
+#define P_AUDIO_RSAMP_ADJ_KI_FORCE ((volatile uint32_t *)0xfe051c2c)
+//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0;
+#define P_AUDIO_RSAMP_RO_STATUS ((volatile uint32_t *)0xfe051c40)
+//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]}
+#define P_AUDIO_RSAMP_RO_ADJ_FREQ ((volatile uint32_t *)0xfe051c44)
+//Bit 31:0 ro_rsamp_adj_freq
+#define P_AUDIO_RSAMP_RO_ADJ_DIFF_BAK ((volatile uint32_t *)0xfe051c48)
+//Bit 31:0 ro_det_diff_bak
+#define P_AUDIO_RSAMP_RO_ADJ_DIFF_DLT ((volatile uint32_t *)0xfe051c4c)
+//Bit 31:0 ro_det_diff_dlt
+#define P_AUDIO_RSAMP_RO_ADJ_PHS_ERR ((volatile uint32_t *)0xfe051c50)
+//Bit 31:0 ro_det_phase_err
+#define P_AUDIO_RSAMP_RO_ADJ_KI_OUT ((volatile uint32_t *)0xfe051c54)
+//Bit 31:0 ro_rsamp_ki_out
+#define P_AUDIO_RSAMP_RO_IN_CNT ((volatile uint32_t *)0xfe051c58)
+//Bit 31:0 ro_rsamp_in_cnt
+#define P_AUDIO_RSAMP_RO_OUT_CNT ((volatile uint32_t *)0xfe051c5c)
+//Bit 31:0 ro_rsamp_out_cnt
+#define P_AUDIO_RSAMP_POST_COEF0 ((volatile uint32_t *)0xfe051c80)
+//Bit 31:0 reg_post_coef0 //signed , default = 0;
+#define P_AUDIO_RSAMP_POST_COEF1 ((volatile uint32_t *)0xfe051c84)
+//Bit 31:0 reg_post_coef1 //signed , default = 0;
+#define P_AUDIO_RSAMP_POST_COEF2 ((volatile uint32_t *)0xfe051c88)
+//Bit 31:0 reg_post_coef2 //signed , default = 0;
+#define P_AUDIO_RSAMP_POST_COEF3 ((volatile uint32_t *)0xfe051c8c)
+//Bit 31:0 reg_post_coef3 //signed , default = 0;
+#define P_AUDIO_RSAMP_POST_COEF4 ((volatile uint32_t *)0xfe051c90)
+//Bit 31:0 reg_post_coef4 //signed , default = 0;
+#define P_AUDIO_RSAMP_AA_COEF_ADDR ((volatile uint32_t *)0xfe051cc0)
+//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0;
+#define P_AUDIO_RSAMP_AA_COEF_DATA ((volatile uint32_t *)0xfe051cc4)
+//Bit 31:0 reg_aa_coef_data //signed , default = 0;
+#define P_AUDIO_RSAMP_SINC_COEF_ADDR ((volatile uint32_t *)0xfe051d00)
+//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0;
+#define P_AUDIO_RSAMP_SINC_COEF_DATA ((volatile uint32_t *)0xfe051d04)
+//Bit 31:0 reg_sinc_coef_data //signed , default = 0;
+//
+// Closing file: RESAMPLE.h
+//
+//========================================================================
+// AUDIO TOP_VAD - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe054800
+// -----------------------------------------------
+#define P_EE_AUDIO2_CLK81_CTRL ((volatile uint32_t *)0xfe054800)
+#define P_EE_AUDIO2_CLK81_EN ((volatile uint32_t *)0xfe054804)
+#define P_EE_AUDIO2_SW_RESET0 ((volatile uint32_t *)0xfe054808)
+#define P_EE_AUDIO2_CLK_GATE_EN0 ((volatile uint32_t *)0xfe05480c)
+#define P_EE_AUDIO2_SECURITY_CTRL0 ((volatile uint32_t *)0xfe054810)
+#define P_EE_AUDIO2_MCLK_VAD_CTRL ((volatile uint32_t *)0xfe054840)
+#define P_EE_AUDIO2_VAD_CLK_CTRL ((volatile uint32_t *)0xfe054844)
+#define P_EE_AUDIO2_MST_DLY_CTRL0 ((volatile uint32_t *)0xfe054848)
+#define P_EE_AUDIO2_MST_VAD_SCLK_CTRL0 ((volatile uint32_t *)0xfe05484c)
+#define P_EE_AUDIO2_MST_VAD_SCLK_CTRL1 ((volatile uint32_t *)0xfe054850)
+#define P_EE_AUDIO2_CLK_TDMIN_VAD_CTRL ((volatile uint32_t *)0xfe054854)
+#define P_EE_AUDIO2_CLK_PDMIN_CTRL0 ((volatile uint32_t *)0xfe054858)
+#define P_EE_AUDIO2_CLK_PDMIN_CTRL1 ((volatile uint32_t *)0xfe05485c)
+#define P_EE_AUDIO2_TOVAD_CTRL0 ((volatile uint32_t *)0xfe054880)
+#define P_EE_AUDIO2_TODDR_VAD_CTRL0 ((volatile uint32_t *)0xfe0548c0)
+#define P_EE_AUDIO2_TODDR_VAD_CTRL1 ((volatile uint32_t *)0xfe0548c4)
+#define P_EE_AUDIO2_TODDR_VAD_CTRL2 ((volatile uint32_t *)0xfe0548c8)
+#define P_EE_AUDIO2_TODDR_VAD_START_ADDR ((volatile uint32_t *)0xfe0548cc)
+#define P_EE_AUDIO2_TODDR_VAD_INIT_ADDR ((volatile uint32_t *)0xfe0548d0)
+#define P_EE_AUDIO2_TODDR_VAD_FINISH_ADDR ((volatile uint32_t *)0xfe0548d4)
+#define P_EE_AUDIO2_TODDR_VAD_START_ADDRB ((volatile uint32_t *)0xfe0548d8)
+#define P_EE_AUDIO2_TODDR_VAD_FINISH_ADDRB ((volatile uint32_t *)0xfe0548dc)
+#define P_EE_AUDIO2_TODDR_VAD_INT_ADDR ((volatile uint32_t *)0xfe0548e0)
+#define P_EE_AUDIO2_TODDR_VAD_STATUS1 ((volatile uint32_t *)0xfe0548e4)
+#define P_EE_AUDIO2_TODDR_VAD_STATUS2 ((volatile uint32_t *)0xfe0548e8)
+#define P_EE_AUDIO2_TDMIN_VAD_CTRL ((volatile uint32_t *)0xfe054900)
+#define P_EE_AUDIO2_TDMIN_VAD_SWAP0 ((volatile uint32_t *)0xfe054904)
+#define P_EE_AUDIO2_TDMIN_VAD_SWAP1 ((volatile uint32_t *)0xfe054908)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE_VAL ((volatile uint32_t *)0xfe05490c)
+#define P_EE_AUDIO2_TDMIN_VAD_STAT ((volatile uint32_t *)0xfe054910)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE0 ((volatile uint32_t *)0xfe054940)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE1 ((volatile uint32_t *)0xfe054944)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE2 ((volatile uint32_t *)0xfe054948)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE3 ((volatile uint32_t *)0xfe05494c)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE4 ((volatile uint32_t *)0xfe054950)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE5 ((volatile uint32_t *)0xfe054954)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE6 ((volatile uint32_t *)0xfe054958)
+#define P_EE_AUDIO2_TDMIN_VAD_MUTE7 ((volatile uint32_t *)0xfe05495c)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK0 ((volatile uint32_t *)0xfe054960)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK1 ((volatile uint32_t *)0xfe054964)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK2 ((volatile uint32_t *)0xfe054968)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK3 ((volatile uint32_t *)0xfe05496c)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK4 ((volatile uint32_t *)0xfe054970)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK5 ((volatile uint32_t *)0xfe054974)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK6 ((volatile uint32_t *)0xfe054978)
+#define P_EE_AUDIO2_TDMIN_VAD_MASK7 ((volatile uint32_t *)0xfe05497c)
+//
+// Closing file: REG_LIST_AUDIO_RTL.h
+//
+//
+// Reading file: ../spifc/rtl/spifc_reg.vh
+//
+//`ifdef SPIFC_REG_DEFINE
+//`else
+//`define SPIFC_REG_DEFINE
+//`define SPIFC BASE ADDR 32'hfd000400
+// -----------------------------------------------
+// APB_BASE: APB2_BASE_ADDR = 0xfd000400
+// -----------------------------------------------
+//AHB domain regsiter.
+#define P_SPIFC_AHB_CTRL ((volatile uint32_t *)0xfd000400)
+//bit 31 AHB BUS enable. 1 enable ahb request. 0: disable ahb request.
+//bit 30. decerr_en for (AXI->AHB bridge).
+//bit 29. force_incr. for ( AXI->AHB bridge).
+//bit 19. critical word first. CWF_EN. 1: enable. 0 : disable.
+//bit 18:17 RDBUF_SIZE . 00: 64bytes. 01: 32 bytes. 10: 16 bytes. 11: reserved.
+//bit 16 AHB MASTER enable. if enabled, each master use one dedicated HRDATA buffer inside ahb2api model. total 3 HRDATA buffers inside ahb2spi.
+//if disabled the 3 HRDATA buffer will random be used for all masters.
+//bit 14 write 1 to clean the HRDATA buffer 2. read 0 finished clean operation.
+//bit 13 write 1 to clean the HRDATA buffer 1. read 0 finished clean operation.
+//bit 12 write 1 to clean the HRDATA buffer 0. read 0 finished clean operation.
+//bit 11:0. not used.
+#define P_SPIFC_CLK_CTRL ((volatile uint32_t *)0xfd000404)
+//bit 14 asynchronous buffer ahb clock disable. 1 = disable. 0 = enable.
+//bit 13 ahb2spi ahb clock disable. 1 = disable. 0 = enable.
+//bit 12 ahb_arb ahb clock disable. 1 = disable. 0 = enable.
+//bit 10 asynchronous buffer ahb clock auto gating enable. 1 = enable. 0 = disable.
+//bit 9 ahb2spi ahb clock auto gating enable. 1 = enable. 0 = disable.
+//bit 8 ahbarb ahb clock auto gating enable. 1 = enable. 0 = disable.
+//bit 2. asynchronous AHB clock domain software reset. 1 = reset. 0 = normal working mode.
+//bit 1. ahb2spi ahb clock domain software reset. 1 = reset. 0 = normal working mode.
+//bit 0. not used.
+#define P_SPIFC_SEC_CTRL ((volatile uint32_t *)0xfd000408)
+//bit 31. ADDRESS security range enable. 1 = enable; 0: disable.
+//bit 14. range6 enable: 1: enable; 0 : disable.
+//bit 13. range5 enable: 1: enable; 0 : disable.
+//bit 12. range4 enable: 1: enable; 0 : disable.
+//bit 11. range3 enable: 1: enable; 0 : disable.
+//bit 10. range2 enable: 1: enable; 0 : disable.
+//bit 9. range1 enable: 1: enable; 0 : disable.
+//bit 8. range0 enable: 1: enable; 0 : disable.
+//bit 7:4 to control spi clock register security. bit 7 = 1, APB bus can access spi clock domain register. bit 7 == 0 : only PPROT[0] == bit 4, the APB can access spic clock domain register.
+//bit 3:0 to control ahb clock domain register secruity. bit 3 = 1, APB bus can access ahb clock domain register. bit 3 ==0; only PPROT[0] == bit 0, the APB can access ahb clock domain register.
+#define P_SPIFC_RANGE0_STA ((volatile uint32_t *)0xfd000440)
+//bit 28 :6.
+//AHB security range 0 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE0_EDA ((volatile uint32_t *)0xfd000444)
+//bit 28 :6.
+//AHB security range 0 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE0_CTRL ((volatile uint32_t *)0xfd000448)
+// AHB secruity range 0 control.
+//bit 15:8 range 0 access control for DMA access.
+//bit 15 range 0 access control for DMA thread 7
+//bit 14 range 0 access control for DMA Thread 6
+//bit 13 range 0 access control for DMA Thread 5.
+//bit 12 range 0 access control for DMA Thread 4.
+// bit 11. range 0 access control for DMA thread 3
+// bit 10. range 0 access control for DMA Thread 2
+// bit 9. range 0 access control for DMA Thread 1.
+// bit 8. range 0 access control for DMA Thread 0.
+// bit 7. range 0 access control for HMASTER == 7 Not used.
+// bit 6. range 0 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 0 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 0 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 0 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 0 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 0 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 0 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE1_STA ((volatile uint32_t *)0xfd00044c)
+//bit 28 :6.
+//AHB security range 1 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE1_EDA ((volatile uint32_t *)0xfd000450)
+//bit 28 :6.
+//AHB security range 1 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE1_CTRL ((volatile uint32_t *)0xfd000454)
+// AHB secruity range 1 control.
+//bit 15:8 range 1 access control for DMA access.
+//bit 15 range 1 access control for DMA thread 7
+//bit 14 range 1 access control for DMA Thread 6
+//bit 13 range 1 access control for DMA Thread 5.
+//bit 12 range 1 access control for DMA Thread 4.
+// bit 11. range 1 access control for DMA thread 3
+// bit 10. range 1 access control for DMA Thread 2
+// bit 9. range 1 access control for DMA Thread 1.
+// bit 8. range 1 access control for DMA Thread 0.
+// bit 7. range 1 access control for HMASTER == 7 Not used.
+// bit 6. range 1 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 1 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 1 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 1 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 1 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 1 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 1 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE2_STA ((volatile uint32_t *)0xfd000458)
+//bit 28 :6.
+//AHB security range 2 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE2_EDA ((volatile uint32_t *)0xfd00045c)
+//bit 28 :6.
+//AHB security range 2 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE2_CTRL ((volatile uint32_t *)0xfd000460)
+// AHB secruity range 2 control.
+//bit 15:8 range 2 access control for DMA access.
+//bit 15 range 2 access control for DMA thread 7
+//bit 14 range 2 access control for DMA Thread 6
+//bit 13 range 2 access control for DMA Thread 5.
+//bit 12 range 2 access control for DMA Thread 4.
+// bit 11. range 2 access control for DMA thread 3
+// bit 10. range 2 access control for DMA Thread 2
+// bit 9. range 2 access control for DMA Thread 1.
+// bit 8. range 2 access control for DMA Thread 0.
+// bit 7. range 2 access control for HMASTER == 7 Not used.
+// bit 6. range 2 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 2 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 2 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 2 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 2 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 2 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 2 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE3_STA ((volatile uint32_t *)0xfd000464)
+//bit 28 :6.
+//AHB security range 3 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE3_EDA ((volatile uint32_t *)0xfd000468)
+//bit 28 :6.
+//AHB security range 3 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE3_CTRL ((volatile uint32_t *)0xfd00046c)
+// AHB secruity range 3 control.
+//bit 15:8 range 3 access control for DMA access.
+//bit 15 range 3 access control for DMA thread 7
+//bit 14 range 3 access control for DMA Thread 6
+//bit 13 range 3 access control for DMA Thread 5.
+//bit 12 range 3 access control for DMA Thread 4.
+// bit 11. range 3 access control for DMA thread 3
+// bit 10. range 3 access control for DMA Thread 2
+// bit 9. range 3 access control for DMA Thread 1.
+// bit 8. range 3 access control for DMA Thread 0.
+// bit 7. range 3 access control for HMASTER == 7 Not used.
+// bit 6. range 3 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 3 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 3 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 3 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 3 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 3 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 3 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE4_STA ((volatile uint32_t *)0xfd000470)
+//bit 28 :6.
+//AHB security range 4 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE4_EDA ((volatile uint32_t *)0xfd000474)
+//bit 28 :6.
+//AHB security range 4 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE4_CTRL ((volatile uint32_t *)0xfd000478)
+// AHB secruity range 4 control.
+//bit 15:8 range 4 access control for DMA access.
+//bit 15 range 4 access control for DMA thread 7
+//bit 14 range 4 access control for DMA Thread 6
+//bit 13 range 4 access control for DMA Thread 5.
+//bit 12 range 4 access control for DMA Thread 4.
+// bit 11. range 4 access control for DMA thread 3
+// bit 10. range 4 access control for DMA Thread 2
+// bit 9. range 4 access control for DMA Thread 1.
+// bit 8. range 4 access control for DMA Thread 0.
+// bit 7. range 4 access control for HMASTER == 7 Not used.
+// bit 6. range 4 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 4 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 4 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 4 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 4 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 4 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 4 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE5_STA ((volatile uint32_t *)0xfd00047c)
+//bit 28 :6.
+//AHB security range 5 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE5_EDA ((volatile uint32_t *)0xfd000484)
+//bit 28 :6.
+//AHB security range 5 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE5_CTRL ((volatile uint32_t *)0xfd000480)
+// AHB secruity range 5 control.
+//bit 15:8 range 5 access control for DMA access.
+//bit 15 range 5 access control for DMA thread 7
+//bit 14 range 5 access control for DMA Thread 6
+//bit 13 range 5 access control for DMA Thread 5.
+//bit 12 range 5 access control for DMA Thread 4.
+// bit 11. range 5 access control for DMA thread 3
+// bit 10. range 5 access control for DMA Thread 2
+// bit 9. range 5 access control for DMA Thread 1.
+// bit 8. range 5 access control for DMA Thread 0.
+// bit 7. range 5 access control for HMASTER == 7 Not used.
+// bit 6. range 5 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 5 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 5 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 5 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 5 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 5 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 5 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE6_STA ((volatile uint32_t *)0xfd000488)
+//bit 28 :6.
+//AHB security range 6 start address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE6_EDA ((volatile uint32_t *)0xfd00048c)
+//bit 28 :6.
+//AHB security range 6 end address in unit of 64Byte. related to HADDR bit 28:6.
+//bit 5:0. always 0.
+#define P_SPIFC_RANGE6_CTRL ((volatile uint32_t *)0xfd000490)
+// AHB secruity range 6 control.
+//bit 15:8 range 6 access control for DMA access.
+//bit 15 range 6 access control for DMA thread 7
+//bit 14 range 6 access control for DMA Thread 6
+//bit 13 range 6 access control for DMA Thread 5.
+//bit 12 range 6 access control for DMA Thread 4.
+// bit 11. range 6 access control for DMA thread 3
+// bit 10. range 6 access control for DMA Thread 2
+// bit 9. range 6 access control for DMA Thread 1.
+// bit 8. range 6 access control for DMA Thread 0.
+// bit 7. range 6 access control for HMASTER == 7 Not used.
+// bit 6. range 6 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 6 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 6 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 6 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 6 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 6 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 6 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_RANGE7_CTRL ((volatile uint32_t *)0xfd000494)
+// AHB secruity range 7( default range) control.
+//bit 15:8 range 7 access control for DMA access.
+//bit 15 range 7 access control for DMA thread 7
+//bit 14 range 7 access control for DMA Thread 6
+//bit 13 range 7 access control for DMA Thread 5.
+//bit 12 range 7 access control for DMA Thread 4.
+// bit 11. range 7 access control for DMA thread 3
+// bit 10. range 7 access control for DMA Thread 2
+// bit 9. range 7 access control for DMA Thread 1.
+// bit 8. range 7 access control for DMA Thread 0.
+// bit 7. range 7 access control for HMASTER == 7 Not used.
+// bit 6. range 7 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+// bit 5. range 7 access control for HMASTER == 5 //DSPB non secure
+// bit 4. range 7 access control for HMASTER == 4 //DSPB non secure
+// bit 3. range 7 access control for HMASTER == 3 //DSPA secure
+// bit 2. range 7 access control for HMASTER == 2 //DSPA non secure
+// bit 1. range 7 access control for HMASTER == 1 //CPU secure access
+// bit 0. range 7 access control for HMASTER == 0 //CPU non secure.
+#define P_SPIFC_AHB_WTCH_CTRL ((volatile uint32_t *)0xfd000498)
+//bit 15:0. ahb bus watch dog timer. if AHB bus not response, the timer over this number, the SPIFC will send back a error response.
+#define P_SPIFC_SEC_VIO0 ((volatile uint32_t *)0xfd00049c)
+//bit 31:0 VIO ADDR
+#define P_SPIFC_SEC_VIO1 ((volatile uint32_t *)0xfd0004a0)
+//bit 31. AHB VIO status. write 1 to clear the error info.
+//bit 6:5 HMASTER.
+//bit 4:2 HPROT.
+//bit 1 HNONSEC.
+//bit 0 HWRITE.
+#define P_SPIFC_AHB_STS ((volatile uint32_t *)0xfd0004a4)
+//bit 31. AHB IDLE. when ahb disabled, to show ahb status. 1, no more ahb request or ahb requent is holded. 0, ahb is still busy.
+//bit 30. AHB data cycle status, when ahb disabled, to show ahb data cycle status. 1, data cycle is holded, 0 : not in data cycle or data cycle is processing.
+//bit 29. AHB bus spi requst status. 1: still waiting for spi data. 0: idle.
+//bit 28:0. not used.
+//SPI cts_spi_clk domain regsiter.
+#define P_SPIFC_USER_CTRL0 ((volatile uint32_t *)0xfd000600)
+//bit 31. user request enable. write 1 to enable. read 0, means user command accepted by the SPI_CTRL.
+//bit 30. user request finish bit. write 0 when enable user request. read 1 means SPI_CTRL finished this user command.
+//bit 0. user data updated. write 0 when enable user request. 1 means there's datas/status read from SPI flash.
+#define P_SPIFC_USER_CTRL1 ((volatile uint32_t *)0xfd000604)
+//bit 31. not used.
+//bit 30. user command cycle enable. 1) enable. 0) don't send command in usr command period.
+//bit 29:28. user command mode. 00 = SPI extend mode. 01 : dual mode. 10: quad mode.
+//bit 27:20. user command code. the code need to send in command period.
+//bit 19. user address cycle enable.
+//bit 18:17 user address mode: 00 = SPI extend mode. 01 : dual mode. 10: quad mode.
+//bit 16:15 user address Byte length 00 = 1 byte. 01 = 2 bytes. 10 = 3 bytes. 11 = 4bytes.
+//bit 14 user datout enable.
+//bit 13 user dataout AES enable. 1: dataout through AES describle. 0 : original data.
+//bit 12 user data output source. 0: from data buffer. 1: from status register.
+//bit 11:10 user dataout mode: 00 SPI extend model. 01 : dual model. 10. quad mode.
+//bit 9:0 User data out bytes num.
+#define P_SPIFC_USER_CTRL2 ((volatile uint32_t *)0xfd000608)
+//bit 31 usr_dummy_en 1: enable dummy cycles. 0 : no dummy cycles.
+//bit 30: 29 usr_dummy_mode 2'b00 = SPI extend mode. 01 dual mode. 10 Quad mode.
+//bit 28:23 user dummy clock cycle number.
+//bit 19:16. user command input/output direction control. 000000: right after the last output.
+// 1: after the first cycle of dummy cycle.
+// .....
+// 4'hf: right before the datin cycle.
+//bit 15:8. data on the dummy cycle after the first byte.
+//bit 7:0 The first bytes data showed on dummy cycle. some flash may need special data for enhance performance mode or XIP mode.
+#define P_SPIFC_USER_CTRL3 ((volatile uint32_t *)0xfd00060c)
+//bit 31 usr_datin_en 1: datain cycle enabled. 0: no datain cycle.
+//bit 30: datin_dest. 1: save the input data to STATUS register. 0 save the input data to data buffer.
+//bit 29: 1: enable datain data AES describle. 0: not use AES.
+//bit 28:27. datin mode. 2'b00 SPI extend mode. 01: dual mode. 10 Quad mode.
+//bit 25:16. user data in data bytes. how many bytes of user datain expected.
+#define P_SPIFC_USER_ADDR ((volatile uint32_t *)0xfd000610)
+//bit 31:0. 32bits user address.
+#define P_SPIFC_AHB_REQ_CTRL ((volatile uint32_t *)0xfd000614)
+//bit 31. AHB request enable.
+//bit 30 AHB cmd_en. command cycle enable.
+//bit 29:28. ahb command mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode.
+//bit 27:20:.AHB command code.
+//bit 19. ahb request address cycle enable.
+//bit 18:17 AHB ADDRESS mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode.
+//bit 16:15 AHB ADDRESS data width. 2'b00: 1byte. 2'b01 : 2bytes. 2'b10: 3bytes. 2'b11 4bytes.
+//bit 13:10 AHB request spi bus input switch time. 0 : after address cycle. 1: the frist dummy cycles. ... 0xf. after dummy cycle.
+//bit 9:8 AHB DATAIN mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode.
+//bit 7 DATA IN AES enable. 1: enable 0: disable.
+//bit 1:0 AHB REQ DATA size. 2'b00: 64bytes. 2'b01: 32 bytes. 2'b10 : 16 bytes. 2'b11: reserved. this bit settign should be same as RDBUF_SIZE setting.
+#define P_SPIFC_AHB_REQ_CTRL1 ((volatile uint32_t *)0xfd000618)
+//bit 31. ahb Dummy enable.
+//bit 30:29. ahb dummy mode.
+//bit 28:23. ahb request dummy clock cycles.
+//bit 15:0. ahb dummy period output data.
+#define P_SPIFC_AHB_REQ_CTRL2 ((volatile uint32_t *)0xfd00061c)
+//bit 1:0 AHB address position. this settign depend on SPIFC_AHB_CTRL register CWF_EN bit and RDBUF_SIZE.
+// if CWF_EN is enabled. these bit should be set to 2'b10 (16BYTE boundary).
+// if CWF_EN is disabled. these bit should be set to same as the RDBUF_SIZE and AHB REQ DATA SIZE.
+//00 : 64byte boundary.
+//01 : 32byte boundary.
+//10 : 16byte boundary.
+//11 : reserved.
+#define P_SPIFC_ACTIMING0 ((volatile uint32_t *)0xfd000620)
+//bit 31:30. tSLCH
+//bit 29:28 tCLSH
+//bit 20:16 tSHWL
+//bit 15:12 tSHSL2
+//bit 11:8 tSHSL1
+//bit 7:0 tWHSL
+#define P_SPIFC_ACTIMING1 ((volatile uint32_t *)0xfd000624)
+//bit 31. D2 pin WP_n function enable.
+//bit 30. D2 Pin value in WP_n fucntion.
+//bit 29. D3 Pin HOLD_n function enable.
+//bit 8. DTR mode. not support.
+//bit 6:4. Clock turn around delay. use it to set the system SPI clock read data delay.
+//bit 3:0. not used.
+#define P_SPIFC_ACTIMING2 ((volatile uint32_t *)0xfd000628)
+//bit 31. spi clock input pin enable. SPIFC controller used this pin as clock to latch the input data.
+//bit [3:0] spi clock input pin delay adjustment.
+//SPI DATA BUFFER. There's a total 512Byte + 64byte(orgnized as 36x128bits) SRAM .
+// since each APB access is 32bits. So we use word address as APB read/write address.
+// But for SPI side we have to use 128bit boundary. That's the first Pragram/read SPI with data buffer must start at data buffer 128bit boundary. that means the SPIFC_USE_DBUF_ADDR last 2 bits must be 0.
+#define P_SPIFC_DBUF_CTRL ((volatile uint32_t *)0xfd000640)
+//bit 31. 1 = write DBUF. 0 : read DBUF.
+//bit 30. 1. = auto update address. 0 don't change address.
+//bit 7:0 DBUF address unit 32bits.
+#define P_SPIFC_DBUF_DATA ((volatile uint32_t *)0xfd000644)
+//bit 31:0. if SPIFC_DBUF_CTRL bit 31 = 1. write to this register will trigger one write to DBUF. and the data will be writen to DBUF.
+#define P_SPIFC_USER_DBUF_ADDR ((volatile uint32_t *)0xfd000648)
+//bit 7:0. the DBUF ADDRESS used to send to or receive from SPI FLASH. the last 2 bits must be 0.
+#define P_SPIFC_FLASH_STATUS ((volatile uint32_t *)0xfd000680)
+#define P_SPIFC_STATUS ((volatile uint32_t *)0xfd000684)
+//bit 1. AES KEY valid. read only 1 : The aes key is ready to use. 0: the aes key is not ready.
+//bit 0. SPI CTRL STATE IDLE. read only. 1 = idle; 0 = busy.
+#define P_SPIFC_CTRL ((volatile uint32_t *)0xfd000688)
+//bit 15:14. mempd for DBUF MEMORY.
+//bit 13 spifc asynchronous buffer clock disable. 1 = disable. 0 = enable.
+//bit 12. spifc controller clock disable. 1 = disable. 0 = enable.
+//bit 9. spifc asynchronous bufer clock auto gate enable. 1 = enable. 0 = disable.
+//bit 8. spifc controller clock auto gate enable. 1 = enable. 0 = disable.
+//bit 2. spifc interface reset. 1 = RESET. 0 = normal working mode.
+//bit 1. spifc asynchronous buffer spi clock side reset. 1 = RESET. 0 : normal working mode.
+//bit 0. spifc controller reset. 1 = RESET. 0 : normal working mode.
+//`endif
+//
+// Closing file: ../spifc/rtl/spifc_reg.vh
+//
+//
+// Reading file: ../psram/rtl/psram_reg.vh
+//
+//`ifdef PSRAM_REG_DEFINE
+//`else
+//`define PSRAM_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007400
+// -----------------------------------------------
+#define P_PSRAM_AXI_INTF_CTRL ((volatile uint32_t *)0xfe007400)
+//bit 3 axi interface soft reset. 1 = reset AXI interface. 0 = normal.
+//bit 2 disable axi interface clock. 1 = disable; 0 = enable.
+//bit 1 axi interface auto clock gating enable. 1 = enable; 0 = disable.
+//bit 0 axi interface AXI request enable. 1 = enable. 0 = disable.
+#define P_PSRAM_DBUF_CTRL ((volatile uint32_t *)0xfe007404)
+//bit 16. MWRITE_EN. 1 : enabel mask write(with DM pin). 0 not enable.
+//bit 15:0 DBUF AGE to write back to PSRAM if DBUF is dirty. but whole DBUF data is not READ to write.(with MWRITE enabled).
+#define P_PSRAM_DBUF_CTRL1 ((volatile uint32_t *)0xfe007408)
+//bit 15:0 DBUF AGE to write back to psram if DBUF is dirty and whole DBUF data is ready to write.
+#define P_PSRAM_APB_CTRL ((volatile uint32_t *)0xfe00740c)
+//7:4 PSRAM PHY register APB secure contrl.
+//bit 7, 1: no secure control. 0 : use bit 4 to match PPROT[0] bit.
+//bit 4. when bit 7 == 0, bit 4 must match PPROT[0] to access.
+//3:0 PCTL_CTRL APB bus control regsiters secure control.
+//bit 3, 1: no secure control. 0 : use bit 0 to match PPROT[0] bit.
+//bit 0. when bit 3 == 0, bit 0 must match PPROT[0] to access.
+#define P_PSRAM_SEC_CTRL ((volatile uint32_t *)0xfe007410)
+//bit 31. ADDRESS security range enable. 1 = enable; 0: disable.
+//if scruity range disabled, but AXI data describle enabled key0 is selected.
+//bit 23 range 7 des key selection 0 : key0; 1: key1;
+//bit 22 range 6 des key selection 0 : key0; 1: key1;
+//bit 21 range 5 des key selection 0 : key0; 1: key1;
+//bit 20 range 4 des key selection 0 : key0; 1: key1;
+//bit 19 range 3 des key selection 0 : key0; 1: key1;
+//bit 18 range 2 des key selection 0 : key0; 1: key1;
+//bit 17 range 1 des key selection 0 : key0; 1: key1;
+//bit 16 range0 des key selection 0 : key0; 1: key1;
+//bit 6. range6 enable: 1: enable; 0 : disable.
+//bit 5. range5 enable: 1: enable; 0 : disable.
+//bit 4. range4 enable: 1: enable; 0 : disable.
+//bit 3. range3 enable: 1: enable; 0 : disable.
+//bit 2. range2 enable: 1: enable; 0 : disable.
+//bit 1. range1 enable: 1: enable; 0 : disable.
+//bit 0. range0 enable: 1: enable; 0 : disable.
+#define P_PSRAM_DES_PADDING ((volatile uint32_t *)0xfe007414)
+//bit 31 :0 Padding, with address together to generate describle 64 bits input.
+#define P_PSRAM_RANGE0_STA ((volatile uint32_t *)0xfe007440)
+//bit 22 :0.
+//AXI security range 0 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE0_EDA ((volatile uint32_t *)0xfe007444)
+//bit 22 :0.
+//AXI security range 0 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE0_CTRL0 ((volatile uint32_t *)0xfe007448)
+// AXI secruity range 0 control.
+#define P_PSRAM_RANGE0_CTRL1 ((volatile uint32_t *)0xfe00744c)
+// AXI secruity range 0 control.
+#define P_PSRAM_RANGE1_STA ((volatile uint32_t *)0xfe007450)
+//bit 22 :0.
+//AXI security range 1 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE1_EDA ((volatile uint32_t *)0xfe007454)
+//bit 22 :0.
+//AXI security range 1 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE1_CTRL0 ((volatile uint32_t *)0xfe007458)
+// AXI secruity range 1 control.
+#define P_PSRAM_RANGE1_CTRL1 ((volatile uint32_t *)0xfe00745c)
+// AXI secruity range 1 control.
+#define P_PSRAM_RANGE2_STA ((volatile uint32_t *)0xfe007460)
+//bit 31 : 6.
+//AXI security range 2 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE2_EDA ((volatile uint32_t *)0xfe007464)
+//bit 31 :6.
+//AXI security range 2 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE2_CTRL0 ((volatile uint32_t *)0xfe007468)
+#define P_PSRAM_RANGE2_CTRL1 ((volatile uint32_t *)0xfe00746c)
+#define P_PSRAM_RANGE3_STA ((volatile uint32_t *)0xfe007470)
+//bit 31 : 6.
+//AXI security range 3 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE3_EDA ((volatile uint32_t *)0xfe007474)
+//bit 31 :6.
+//AXI security range 3 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE3_CTRL0 ((volatile uint32_t *)0xfe007478)
+// AXI secruity range 3 control.
+#define P_PSRAM_RANGE3_CTRL1 ((volatile uint32_t *)0xfe00747c)
+// AXI secruity range 3 control.
+#define P_PSRAM_RANGE4_STA ((volatile uint32_t *)0xfe007480)
+//bit 31 :6.
+//AXI security range 4 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE4_EDA ((volatile uint32_t *)0xfe007484)
+//bit 31 :6.
+//AXI security range 4 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE4_CTRL0 ((volatile uint32_t *)0xfe007488)
+// AXI secruity range 4 control.
+#define P_PSRAM_RANGE4_CTRL1 ((volatile uint32_t *)0xfe00748c)
+#define P_PSRAM_RANGE5_STA ((volatile uint32_t *)0xfe007490)
+//bit 22 :0.
+//AXI security range 5 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE5_EDA ((volatile uint32_t *)0xfe007494)
+//bit 22 :0.
+//AXI security range 5 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE5_CTRL0 ((volatile uint32_t *)0xfe007498)
+// AXI secruity range 5 control.
+#define P_PSRAM_RANGE5_CTRL1 ((volatile uint32_t *)0xfe00749c)
+// AXI secruity range 5 control.
+#define P_PSRAM_RANGE6_STA ((volatile uint32_t *)0xfe0074a0)
+//bit 22 :0.
+//AXI security range 6 start address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE6_EDA ((volatile uint32_t *)0xfe0074a4)
+//bit 22 :0.
+//AXI security range 6 end address in unit of 64Byte. related to HADDR bit 28:6.
+#define P_PSRAM_RANGE6_CTRL0 ((volatile uint32_t *)0xfe0074a8)
+// AXI secruity range 6 control.
+#define P_PSRAM_RANGE6_CTRL1 ((volatile uint32_t *)0xfe0074ac)
+// AXI secruity range 6 control.
+#define P_PSRAM_RANGE7_CTRL0 ((volatile uint32_t *)0xfe0074b0)
+#define P_PSRAM_RANGE7_CTRL1 ((volatile uint32_t *)0xfe0074b4)
+#define P_PSRAM_VIO_STATUS ((volatile uint32_t *)0xfe0074b8)
+//bit 31: security violation. write 1 to clean security violation status.
+//bit 30. 1 : AXI write violation. 0 : axi read violation.
+//bit 18:16. AXI ARPROT/AWPROT>
+//bit 11:0. AXI violation ID.
+#define P_PSRAM_VIO_ADDR ((volatile uint32_t *)0xfe0074bc)
+//read only
+//31:0 AXI violation address.
+#define P_PSRAM_USER_CTRL0 ((volatile uint32_t *)0xfe007600)
+//bit 31. user request enable. write 1 to enable. read 0, means user command accepted by the SPI_CTRL.
+//bit 30. usr request done. after user command done. this bit set to 1.
+//bit 29. USR COMMAND enable.
+//bit 28. command type0. 1 READ command. 0 write command.
+//bit 27. command type1. 1 for register. 0 : for memory.
+//bit 21~16. USR command clock cycles
+//bit 15~0. USR COMMAND CODE.
+#define P_PSRAM_USER_CTRL1 ((volatile uint32_t *)0xfe007604)
+//bit 31. USR_ADDR_EN
+//bit 30:29. USR_ADDR_DW
+//bit 28~20. USR address clock cycle number.
+//bit 19:16 USR data output/input switch postion
+//bit 15. USR DUMMY ENABLE
+//bit 13~8. USR DUMMY clock cycles.
+//bit 5:0 USR data DQS read enable postion.
+#define P_PSRAM_USER_CTRL2 ((volatile uint32_t *)0xfe007608)
+//bit 31 usr des key selection. 1 : key 1; 0 : key 0.
+//bit 30. usr check latency. for Winbond PSRAM data read/write, DQS input indentify the latency is doubled or not.
+//bit 29. usr data des enable.
+//bit 28 usr datain enable.
+//bit 27. usr datain destination. 1 : write to CFG_STS register. 0 : write to DATA REGISTERs.
+//bit 26~16 usr data in clock cycle number.
+//bit 15. usr datout enable.
+//bit 14. usr data out source 1 : from CFG_STS register. 0 from DATA register.
+//bit 13~11. not used.
+//bit 10~0. usr dataout clock cycles.
+#define P_PSRAM_USER_CTRL3 ((volatile uint32_t *)0xfe00760c)
+//bit 17:16. which cycle to ask phy to check read/write latency at PSRAM SEND COMMOND stage.
+//since PSRAM send command stage only 3 clock cycle. So this number only can chose 0, 1, 2.
+//bit 15:0. user dummy data when output in dummy cycle.
+#define P_PSRAM_USER_ADDR ((volatile uint32_t *)0xfe007610)
+//bit 31:0. 32bits user address.
+#define P_PSRAM_AXI_REQ_CTRL0 ((volatile uint32_t *)0xfe007614)
+//bit 31. AXI request enable.
+//bit 30 AXI cmd_en. command cycle enable.
+//bit 29:24. AXI request command cycle clock numbers.
+//bit 22. AXI request address cycle enable.
+//bit 21:16. AXI request address cycle clock number.
+//bit 15:14. AXI address cycle data width.
+//bit 13:12. at which clock cycle to send signal to phy to check latency flag for WINBOND PSRAM flexible latency.
+//since PSRAM send command stage only 3 clock cycle. So this number only can chose 0, 1, 2.
+//bit 6 // AXI Write dummy enable.
+//bit 5:0 // axi write dummy clock cycle number.
+#define P_PSRAM_AXI_REQ_CTRL1 ((volatile uint32_t *)0xfe007618)
+//bit 31:16. AXI request psram READ command code.
+//bit 15:0. AXI request psram write command code.
+#define P_PSRAM_AXI_REQ_CTRL2 ((volatile uint32_t *)0xfe00761c)
+//bit 31. AXI read request Dummy enable.
+//bit 30. Check latency enable for WINBOND PSRAM flexible latency.
+//bit 27:22. clock cycles in dummy stage to eanble PSRAM PHY reading logic.
+//bit 21:16. axi_read dummy clock cycles number.
+//bit 15:0. dummy data if output in dummy cycles.
+#define P_PSRAM_AXI_REQ_CTRL3 ((volatile uint32_t *)0xfe007620)
+//bit 31 des enable.
+//bit 26:16. DATA input clock cycles.
+//bit 10:0. DATA output clock cycles.
+#define P_PSRAM_ACTIMING0 ((volatile uint32_t *)0xfe007624)
+//bit 31:30. tSLCH
+//bit 29:28 tCLSH
+//bit 20:16 tSHWL
+//bit 15:12 tSHSL2
+//bit 11:8 tSHSL1
+//bit 7:0 tWHSL
+#define P_PSRAM_ACTIMING1 ((volatile uint32_t *)0xfe007628)
+//bit 7:0 tRWR for winbond PSRAM, = tRWR -3. Winbond PSRAM include one CS cycle and 2 command cycle.
+//for APMEMORY should be same value of tCPH
+#define P_PSRAM_ACTIMING2 ((volatile uint32_t *)0xfe00762c)
+#define P_PSRAM_WDG_CTRL ((volatile uint32_t *)0xfe007630)
+//bit [31] 1: force to reset PSRAM PCTL and PHY logic. 0: normal.
+//bit [30] 1: automatic reset PSRAM PCTL and PHY logic if watch dog triggered.
+//bit 12:0. watch dog timer. for Winbond PSRAM should be 1us for tRC. for APMEMORY should be 1us for tCEM.
+//SPI DATA BUFFER. There's a total 512KByte + 64byte(orgnized as 36x128bits) SRAM .
+// since each APB access is 32bits. So we use word address as APB read/write address.
+// But for SPI side we have to use 128bit boundary. That's the first Pragram/read SPI with data buffer must start at data buffer 128bit boundary. that means the PSRAM_USE_DBUF_ADDR last 2 bits must be 0.
+#define P_PSRAM_DBUF_0 ((volatile uint32_t *)0xfe007640)
+#define P_PSRAM_DBUF_1 ((volatile uint32_t *)0xfe007644)
+#define P_PSRAM_DBUF_2 ((volatile uint32_t *)0xfe007648)
+#define P_PSRAM_DBUF_3 ((volatile uint32_t *)0xfe00764c)
+#define P_PSRAM_DBUF_4 ((volatile uint32_t *)0xfe007650)
+#define P_PSRAM_DBUF_5 ((volatile uint32_t *)0xfe007654)
+#define P_PSRAM_DBUF_6 ((volatile uint32_t *)0xfe007658)
+#define P_PSRAM_DBUF_7 ((volatile uint32_t *)0xfe00765c)
+#define P_PSRAM_DBUF_8 ((volatile uint32_t *)0xfe007660)
+#define P_PSRAM_DBUF_9 ((volatile uint32_t *)0xfe007664)
+#define P_PSRAM_DBUF_A ((volatile uint32_t *)0xfe007668)
+#define P_PSRAM_DBUF_B ((volatile uint32_t *)0xfe00766c)
+#define P_PSRAM_DBUF_C ((volatile uint32_t *)0xfe007670)
+#define P_PSRAM_DBUF_D ((volatile uint32_t *)0xfe007674)
+#define P_PSRAM_DBUF_E ((volatile uint32_t *)0xfe007678)
+#define P_PSRAM_DBUF_F ((volatile uint32_t *)0xfe00767c)
+#define P_PSRAM_CFG_STS ((volatile uint32_t *)0xfe007680)
+//32bits register to save the USR read command read back values.
+#define P_PSRAM_STATUS ((volatile uint32_t *)0xfe007684)
+//bit 31. usr_req_done flag. 1 : user request done . write 1 to clean.
+//bit 30~11.
+//bit 10:8
+//bit 7:3.
+//bit 2. axi_data buffer idle bit. 1 : idle. 0 : working.
+//bit 1. axi interface idle bit. 1 : idle. 0 : working.
+//bit 0. psram ctrl idle bit. 1 : idle. 0 : working.
+#define P_PSRAM_CTRL ((volatile uint32_t *)0xfe007688)
+//bit 31. PSRAM in DTR mode.
+//bit 30. psram input data latch clock select. 1: from clock input pin. 0: from DQS
+//if use clock input pin as data input latch clock, bit 13:12 should select 01.
+//bit 29:27. PSRAM mode.
+//'b000 : STR SPI mode.
+//'b001 : STR QPI mode.
+//'b010 : DTR QPI mode.
+//'b011 : DTR OPI FLASH.
+//'b100 : APmemory PSRAM mode.
+//'b101 : Winbond PSRAM mode.
+//bit 26. enable to generation interruption after usr request done. 1: enable. 0: disable.
+//bit 25. to enable APMEMORY 2 command cycle mode. 1 : enable : 0: 3 command cycles.
+//bit 24. to enable the psram clock output always enable. 1 : enable. 0: disable.
+//bit 23. to enable the psram clock output extend mode to cover APMEMORY tCPI.
+//bit 22. to disable the CKN output. 1: disable PSRAM CK_N pin output. 0: CK_N working normal.
+//bit 21. PSRAM DATA IN/OUT high 8bit and low 8 bit endian. 1 : rising edge is low byte. falling edge data is high byte. 0 : rising edge is high byte. falling edge data is low byte.
+//bit 20. PSRAM ADDRESS unit. 1: Byte. 0 : word.
+// APMEMORY used byte address. Winbond use word address.
+//bit 19. DQSEN generation. if use dqs to latch input data, this bit should be set to 1 to ask DMC generate ENABLE singal in dummy stage. 0: not generate DQS_EN.
+//bit 18. PSRAM RESET I/O oe_n value. if need RESET pin.
+//bit 17. PSRAM RESET I/O output vale. if need reset pin.
+//bit 16. force CS output low. for APMEMORY exit DPPD mode. 1: to force cs output low : 0 output normal working mode.
+//bit 13:12. psram data in clock enable selection. 00: use DQSEN. 01: use clkin cnt.
+//bit 11. DM Disable. 1: disable DM output. 0: with dmoutput.
+//bit 9. psram pctl auto clock gating enable. 1: enable. 0 : disable.
+//bit 8. psram pctl clock disable. 1: disable. 0 : enable.
+//bit 2 PSRAM SPI mode, DQ2 works as WP(write protection mode).
+//bit 1. DQ2 WP mode value.
+//bit 0. PSRAM SPI mode, DQ3 works as HOLD function.
+#define P_PSRAM_PIN_CTRL ((volatile uint32_t *)0xfe00768c)
+//bit 30:28 DATA 6 DQ pin selection.
+//bit 27:24 DATA 6 DQ pin selection.
+//bit 22:20 DATA 5 DQ pin selection.
+//bit 18:16 DATA 4 DQ pin selection.
+//bit 14:12 DATA 3 DQ pin selection.
+//bit 10:8 DATA 2 DQ pin selection.
+//bit 6:4 DATA 1 DQ pin selection.
+//bit 2:0 DATA 0 DQ pin selection.
+//0 : from DQ[0]
+//1 : from DQ[1]
+//2 : from DQ[2]
+//3 : from DQ[3]
+//4 : from DQ[4]
+//5 : from DQ[5]
+//6 : from DQ[6]
+//7 : from DQ[7]
+//psram_dly_16 is used for all DQ[0~] in/out/oen delay adjustment.
+//psram_dly_16 consists of 15 delay cells, one delay cell is 50ps delay( typical corner).
+//psram_dly_16 is control by delay_sel[3:0]. 0 = no delay. 1~15 controls how many delay cells used.
+//psram_dly_16 can be controlled by each control register either with real delay mode or VT updated with 4xclock period.
+//psram_lcdl is used for DQS/DQSN input and CK/CKN output delay 90degree delay generation and/or delay fine tune.
+//psram_lcdl consits of 96 delay cells, same delay cell used in psram_dly_16.
+//psram_lcdl should be calibrated with the psram_4xclock. and tracked with psram_4xclock with VT updated.
+#define P_PSRAM_DQ0_DIN_DLY ((volatile uint32_t *)0xfe007700)
+//bit 6:0. DQ0 DIN delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ1_DIN_DLY ((volatile uint32_t *)0xfe007704)
+//bit 6:0. DQ1 input delay control. in DLY16 read mode, only [3:0] is valid.
+#define P_PSRAM_DQ2_DIN_DLY ((volatile uint32_t *)0xfe007708)
+//bit 6:0. DQ2 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ3_DIN_DLY ((volatile uint32_t *)0xfe00770c)
+//bit 6:0. DQ3 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ4_DIN_DLY ((volatile uint32_t *)0xfe007710)
+//bit 6:0. DQ4 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ5_DIN_DLY ((volatile uint32_t *)0xfe007714)
+//bit 6:0. DQ5 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ6_DIN_DLY ((volatile uint32_t *)0xfe007718)
+//bit 6:0. DQ6 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ7_DIN_DLY ((volatile uint32_t *)0xfe00771c)
+//bit 6:0. DQ7 input delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ0_DOUT_DLY ((volatile uint32_t *)0xfe007720)
+//bit 6:0. DQ0 DOUT delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ1_DOUT_DLY ((volatile uint32_t *)0xfe007724)
+//bit 6:0. DQ1 output delay control. in DLY16 read mode, only [3:0] is valid.
+#define P_PSRAM_DQ2_DOUT_DLY ((volatile uint32_t *)0xfe007728)
+//bit 6:0. DQ2 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ3_DOUT_DLY ((volatile uint32_t *)0xfe00772c)
+//bit 6:0. DQ3 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ4_DOUT_DLY ((volatile uint32_t *)0xfe007730)
+//bit 6:0. DQ4 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ5_DOUT_DLY ((volatile uint32_t *)0xfe007734)
+//bit 6:0. DQ5 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ6_DOUT_DLY ((volatile uint32_t *)0xfe007738)
+//bit 6:0. DQ6 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ7_DOUT_DLY ((volatile uint32_t *)0xfe00773c)
+//bit 6:0. DQ7 output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ0_OEN_DLY ((volatile uint32_t *)0xfe007740)
+//bit 6:0. DQ0 OEN delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ1_OEN_DLY ((volatile uint32_t *)0xfe007744)
+//bit 6:0. DQ1 output enable delay control. in DLY16 read mode, only [3:0] is valid.
+#define P_PSRAM_DQ2_OEN_DLY ((volatile uint32_t *)0xfe007748)
+//bit 6:0. DQ2 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ3_OEN_DLY ((volatile uint32_t *)0xfe00774c)
+//bit 6:0. DQ3 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ4_OEN_DLY ((volatile uint32_t *)0xfe007750)
+//bit 6:0. DQ4 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ5_OEN_DLY ((volatile uint32_t *)0xfe007754)
+//bit 6:0. DQ5 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ6_OEN_DLY ((volatile uint32_t *)0xfe007758)
+//bit 6:0. DQ6 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQ7_OEN_DLY ((volatile uint32_t *)0xfe00775c)
+//bit 6:0. DQ7 output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DM_DOUT_DLY ((volatile uint32_t *)0xfe007760)
+//bit 6:0. DM output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DM_OEN_DLY ((volatile uint32_t *)0xfe007764)
+//bit 6:0. DM output enable delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_CS_DOUT_DLY ((volatile uint32_t *)0xfe007768)
+//bit 6:0. CS output delay control. in DLY16 real mode, only [3:0] is valid.
+#define P_PSRAM_DQS_DIN_DLY ((volatile uint32_t *)0xfe00776c)
+//bit 6:0. DQS input delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define P_PSRAM_DQSN_DIN_DLY ((volatile uint32_t *)0xfe007770)
+//bit 6:0. DQSN input delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define P_PSRAM_CKN_DOUT_DLY ((volatile uint32_t *)0xfe007774)
+//bit 6:0. CKN output delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define P_PSRAM_CK_DOUT_DLY ((volatile uint32_t *)0xfe007778)
+//bit 6:0. CK output delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define P_PSRAM_RDEN_DLY ((volatile uint32_t *)0xfe00777c)
+//bit 10:7. READ enable phase delay. unit = 1UI. for AP QPI PSRAM. PSRAM only send one cycle DQS preamble.
+// We have to used this UI delay to compensate the whole clock output delay and the DQS input delay.
+// if run high frequency, this delay need to be trained. the valid value from 0 ~ 12. Since one UI is 1/4 of PSRAM clock,
+// the total delay of the clock output delay + input delay should be less than 3 PSRAM clock.
+//bit 6:0. READ enable fine tune delay control. unit = 1/64 UI with PSRAM_LCDL_CTRL bit 28 = 0;
+// unit = 1 delay cell, with PSRAM_LCDL_CTRL bit 28 = 1;
+#define P_PSRAM_LCDL_CTRL ((volatile uint32_t *)0xfe0077c0)
+//bit 31. write 1 to update all delay cell delays control.
+//bit 30. write 1 to calibration LCDL.
+//bit 29. LCDL track enable. 1: enable LCDL auto track VT changes.
+//bit 28. LCDL delay control mode.
+//1 : real delay mode. For DQS/DQSN/CKN/CK/RDEN delay control register, one number means one delay cells.
+//0 : UI MODE. For DQS/DQSN/CKN/CK/RDEN delay control register, one number means 1/64 psram_4xclk period.
+//bit 27. DLY16 ( psram_dly_16 cell) delay control mode.
+//1 : real delay mode. For all data delay control register, one number means one delay cells.
+//0 : UI MODE. For all data delay control register, one number means 1/64 psram_4xclk period.
+//bit 27:24. not used.
+//bit 23:0. timer do trigger LCDL track the VT once. each track will compensate the UI with 1/16 delay cell delay.
+//LCDL calibration ctroller.
+#define P_PSRAM_LCDL_CAL_CTRL1 ((volatile uint32_t *)0xfe0077c4)
+//27:24. which LCDL delay line used to run calibration.
+//19:16. LCDL calibration loop end position.
+//15:12. LCDL calibration loop initial position.
+//10:0. LCDL calibration initial phase counter.
+#define P_PSRAM_LCDL_CAL_CTRL2 ((volatile uint32_t *)0xfe0077c8)
+//26:16 LCDL phase lock limit. if the lcdl phase counter difference between 2 calibration loops is less than this number, The LCDL would be locked and stop the calibration.
+//10:0. deta_init. the first loop phase changing number.
+#define P_PSRAM_LCDL_CAL_CTRL3 ((volatile uint32_t *)0xfe0077cc)
+//29:25 to configure LCDL calibration step 5 position.
+//24:20 to configure LCDL calibration step 4 position.
+//19:15 to configure LCDL calibration step 3 position.
+//14:10 to configure LCDL calibration step 2 position.
+//9:5 to configure LCDL calibration step 1 position.
+//4:0 to configure LCDL calibration step 0 position.
+#define P_PSRAM_LCDL_CAL_CTRL4 ((volatile uint32_t *)0xfe0077d0)
+//19:15 to configure LCDL calibration step 9 position.
+//14:10 to configure LCDL calibration step 8 position.
+//9:5 to configure LCDL calibration step 7 position.
+//4:0 to configure LCDL calibration step 6 position.
+#define P_PSRAM_CLK_UI ((volatile uint32_t *)0xfe0077d4)
+//bit 6:0. 4xCLOCK period delay measured from LCDL calibration.
+#define P_PSRAM_LCDL_PH ((volatile uint32_t *)0xfe0077d8)
+//10:0 LCDL phase counter after calibration.
+#define P_PSRAM_LCDL_STATUS ((volatile uint32_t *)0xfe0077dc)
+//bit 31. LCDL lock status. 1: LCDL locked to 4x clock.
+//`endif
+//
+// Closing file: ../psram/rtl/psram_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_sec.vh
+//
+//`ifdef DMC_SEC_REG_DEFINE
+//`else
+//`define DMC_SEC_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd021000
+// -----------------------------------------------
+//`define DMC_SEC_REG_BASE 32'hfd021000
+// ID assignment inside DMC..
+// id[12 :0] total 13 bit ID.
+// id[12] == 1: for DMC internal TEST module.
+// id[12] == 0: for AXI port input.
+// id[11:0] == AXI port ID.
+// id[2:0] == 0 : A55 CPU.
+// id[2:0] == 1 : DSPA
+// id[2:0] == 2 : DSPB
+// id[2:0] == 3 : Not used.
+// id[2:0] == 4 : for Device.
+//Device sublevel ID.
+//id[9:7] == 5 : for audio. id[3] == 0: audio
+//id[9:7] == 6 : for DMA. id[6:4] for DMA thread id. id[3] for DMC security level.
+//id[9:7] == others: for device other masters.
+// id[2:0] == 5 : for USB device.
+// id[2:0] == 6 : for I2C debug input.
+// id[2:0] == 7 : for USB host.
+#define P_DMC_SEC_RANGE0_STA ((volatile uint32_t *)0xfd021000)
+//bit 31:12. range0 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE0_EDA ((volatile uint32_t *)0xfd021004)
+//bit 31:12. range0 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE0_RID_CTRL ((volatile uint32_t *)0xfd021008)
+//range 0 read access enable based on DMC ID assignments.
+//bit 28. for AXI port 3. Not used in A1. should be 0.
+//bit 27. for dmc_test. 1 = enable. 0 = disable.
+//bit 26. for usbhost. 1 = enable. 0 = disable.
+//bit 25. for i2c. 1 = enable. 0 = disable.
+//bit 24. for usbdevide. 1 = enable. 0 = disable.
+//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+//bit 22:18.for AXI device sub level id 5 ~ 0.
+//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0).
+//bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0).
+//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define P_DMC_SEC_RANGE0_WID_CTRL ((volatile uint32_t *)0xfd02100c)
+//range 0 write access enable based on DMC ID assignments.
+//bit 28. for AXI port 3. Not used in A1. should be 0.
+//bit 27. for dmc_test. 1 = enable. 0 = disable.
+//bit 26. for usbhost. 1 = enable. 0 = disable.
+//bit 25. for i2c. 1 = enable. 0 = disable.
+//bit 24. for usbdevide. 1 = enable. 0 = disable.
+//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+//bit 22:18.for AXI device sub level id 5 ~ 0.
+//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0).
+//bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5).
+//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define P_DMC_SEC_RANGE1_STA ((volatile uint32_t *)0xfd021010)
+//bit 31:12. range1 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE1_EDA ((volatile uint32_t *)0xfd021014)
+//bit 31:12. range0 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE1_RID_CTRL ((volatile uint32_t *)0xfd021018)
+//range 1 read access enable based on DMC ID assignments.
+//bit 28. for AXI port 3. Not used in A1. should be 0.
+//bit 27. for dmc_test. 1 = enable. 0 = disable.
+//bit 26. for usbhost. 1 = enable. 0 = disable.
+//bit 25. for i2c. 1 = enable. 0 = disable.
+//bit 24. for usbdevide. 1 = enable. 0 = disable.
+//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+//bit 22:18.for AXI device sub level id 5 ~ 0.
+//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0).
+//bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0).
+//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define P_DMC_SEC_RANGE1_WID_CTRL ((volatile uint32_t *)0xfd02101c)
+//range 1 write access enable based on DMC ID assignments.
+//bit 28. for AXI port 3. Not used in A1. should be 0.
+//bit 27. for dmc_test. 1 = enable. 0 = disable.
+//bit 26. for usbhost. 1 = enable. 0 = disable.
+//bit 25. for i2c. 1 = enable. 0 = disable.
+//bit 24. for usbdevide. 1 = enable. 0 = disable.
+//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+//bit 22:18.for AXI device sub level id 5 ~ 0.
+//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0).
+//bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5).
+//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define P_DMC_SEC_RANGE2_STA ((volatile uint32_t *)0xfd021020)
+//bit 31:12. range2 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE2_EDA ((volatile uint32_t *)0xfd021024)
+//bit 31:12. range2 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE2_RID_CTRL ((volatile uint32_t *)0xfd021028)
+//range 2 read access enable based on DMC ID assignments.
+//bit 28. for AXI port 3. Not used in A1. should be 0.
+//bit 27. for dmc_test. 1 = enable. 0 = disable.
+//bit 26. for usbhost. 1 = enable. 0 = disable.
+//bit 25. for i2c. 1 = enable. 0 = disable.
+//bit 24. for usbdevide. 1 = enable. 0 = disable.
+//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+//bit 22:18.for AXI device sub level id 5 ~ 0.
+//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only has thread 3 to thread 0).
+//bit 9:6. for AXI device audio read subid 3~0. (in A1, audio read only has subid 1 and subid 0).
+//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define P_DMC_SEC_RANGE2_WID_CTRL ((volatile uint32_t *)0xfd02102c)
+//range 2 write access enable based on DMC ID assignments.
+//bit 28. for AXI port 3. Not used in A1. should be 0.
+//bit 27. for dmc_test. 1 = enable. 0 = disable.
+//bit 26. for usbhost. 1 = enable. 0 = disable.
+//bit 25. for i2c. 1 = enable. 0 = disable.
+//bit 24. for usbdevide. 1 = enable. 0 = disable.
+//bit 23. for AXI device sublevel id 7. 1 = enable. 0 = disable.
+//bit 22:18.for AXI device sub level id 5 ~ 0.
+//bit 17:10.for AXI device DMA thread 7 ~ thread 0.( in A1, DMA only 4 threads from thread 3 to thread 0).
+//bit 9:6. for AXI device audio write subid 7~4. (in A1, audio write only 2 masters usey subid 4 and subid 5).
+//bit 5:4. for AXI DSPB. bit 5 for security access. bit 4 for non secure access.
+//bit 3:2. for AXI DSPA. bit 3 for security access. bit 2 for non secure access.
+//bit 1:0. for AXI A55 CPU. bit 1 for security access. bit 0 for non secure access.
+#define P_DMC_SEC_RANGE3_STA ((volatile uint32_t *)0xfd021030)
+//bit 31:12. range3 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE3_EDA ((volatile uint32_t *)0xfd021034)
+//bit 31:12. range3 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE3_RID_CTRL ((volatile uint32_t *)0xfd021038)
+//range 3 read access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE3_WID_CTRL ((volatile uint32_t *)0xfd02103c)
+//range 3 write access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE4_STA ((volatile uint32_t *)0xfd021040)
+//bit 31:12. range4 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE4_EDA ((volatile uint32_t *)0xfd021044)
+//bit 31:12. range4 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE4_RID_CTRL ((volatile uint32_t *)0xfd021048)
+//range 4 read access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE4_WID_CTRL ((volatile uint32_t *)0xfd02104c)
+//range 4 write access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE5_STA ((volatile uint32_t *)0xfd021050)
+//bit 31:12. range5 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE5_EDA ((volatile uint32_t *)0xfd021054)
+//bit 31:12. range5 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE5_RID_CTRL ((volatile uint32_t *)0xfd021058)
+//range 5 read access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE5_WID_CTRL ((volatile uint32_t *)0xfd02105c)
+//range 5 write access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE6_STA ((volatile uint32_t *)0xfd021060)
+//bit 31:12. range5 start address. in 4KB boundary.
+#define P_DMC_SEC_RANGE6_EDA ((volatile uint32_t *)0xfd021064)
+//bit 31:12. range6 end address. in 4KB boundary.
+#define P_DMC_SEC_RANGE6_RID_CTRL ((volatile uint32_t *)0xfd021068)
+//range 6 read access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE6_WID_CTRL ((volatile uint32_t *)0xfd02106c)
+//range 6 write access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+//range 7 is default range if the access not hit any of the previous 7 range, if would hit range 7.
+#define P_DMC_SEC_RANGE7_RID_CTRL ((volatile uint32_t *)0xfd021070)
+//range 7 read access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_RID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE7_WID_CTRL ((volatile uint32_t *)0xfd021074)
+//range 7 write access enable based on DMC ID assignments.
+//check DMC_SEC_RANGE0_WID_CTRL for each bit define.
+#define P_DMC_SEC_RANGE_CTRL ((volatile uint32_t *)0xfd021078)
+//bit 23:16 8 range security level. to chosse with DES KEY to use data describle.
+//bit 7:0 8 range enable. each bit for one range to indentify the range is enabled or not.
+//registers to check the security protection and watch point error information.
+#define P_DMC_DES_CTRL ((volatile uint32_t *)0xfd021080)
+//bit 1 data describle enable.
+//bit 0 wirte 1 to block DES CTRL and DES PADDING read/write.
+#define P_DMC_DES_PADDING ((volatile uint32_t *)0xfd021084)
+#define P_DMC_SEC_STATUS ((volatile uint32_t *)0xfd0212e0)
+//bit 31~2. not used.
+//bit 1 write security violation.
+//bit 0. read security violation.
+#define P_DMC_VIO_ADDR0 ((volatile uint32_t *)0xfd0212e4)
+//ddr0 write secure violation address.
+#define P_DMC_VIO_ADDR1 ((volatile uint32_t *)0xfd0212e8)
+//bit 31:18 . not used. always 0.
+//17 ddr0 secure check violation.
+//16 ddr0 write address overflow. write out of DDR size.
+//15:13. ddr0 write violation AWPROT bits.
+//12:0 ddr0_write violation ID. Please check ID assignment for ID bit defines.
+#define P_DMC_VIO_ADDR2 ((volatile uint32_t *)0xfd0212ec)
+//ddr0 write secure violation address.
+#define P_DMC_VIO_ADDR3 ((volatile uint32_t *)0xfd0212f0)
+//bit 31:18 . not used. always 0.
+//17 ddr0 secure check violation.
+//16 ddr0 read address overflow. write out of DDR size.
+//15:13. ddr0 read violation AWPROT bits.
+//12:0 ddr0_read violation ID. please ID assignment for ID bit defines.
+//DDR0_ADDRMAP is used for RANK0 bank, row, col address mapping from AXI 32bits linear address.
+#define P_DDR0_ADDRMAP_0 ((volatile uint32_t *)0xfd021340)
+//29:25 ca8.
+//24:20 ca7.
+//19:15 ca6.
+//14:10 ca5.
+//9:5 ca4.
+//4:0 ca3.
+#define P_DDR0_ADDRMAP_1 ((volatile uint32_t *)0xfd021344)
+//29:25 ra2.
+//24:20 ra1.
+//19:15 ra0.
+//14:10 ca11.
+//9:5 ca10.
+//4:0 ca9.
+#define P_DDR0_ADDRMAP_2 ((volatile uint32_t *)0xfd021348)
+//29:25 ra8.
+//24:20 ra7.
+//19:15 ra6.
+//14:10 ra5.
+//9:5 ra4.
+//4:0 ra3.
+#define P_DDR0_ADDRMAP_3 ((volatile uint32_t *)0xfd02134c)
+//29:25 ra14.
+//24:20 ra13.
+//19:15 ra12.
+//14:10 ra11.
+//9:5 ra10.
+//4:0 ra9.
+#define P_DDR0_ADDRMAP_4 ((volatile uint32_t *)0xfd021350)
+//29:25 ra16 for DDR4 SDRAM
+//24:20 bg1 for DDR4 SDRAM.
+//19:15 ba2. or bg0 for DDR4.
+//14:10 ba1.
+//9:5 ba0.
+//4:0 ra15.
+#define P_DMC_DDR_CTRL ((volatile uint32_t *)0xfd021368)
+// DDR PHY and DMC only supports 16bits and rank0 only.
+//bit 24:22 3'b000 : ddr3 mode.
+//3'b001 : ddr4 mode.
+//3'b010 : lpddr3 mode.
+//3'b011 : lpddr4 mode.
+//bit 20 DDR4 BG1 enable bit.
+//bit 3:0 : DDR rank 0 size bit [2:0].
+//4'b0000 : DDR rank 0 is 128Mbyte.
+//4'b0001 : DDR rank 0 is 256Mbyte.
+//4'b0010 : DDR rank 0 is 512Mbyte.
+//4'b0011 : DDR rank 0 is 1Gbyte.
+//4'b0100 : DDR rank 0 is 2Gbyte.
+//4'b0101 : DDR rank 0 is 4Gbyte.
+//4'b1000 : DDR rank 0 is 4Gbyte.
+//4'b1001 : DDR rank 0 is 4Gbyte.
+//others : reserved.
+#define P_DMC_APB_SEC_CTRL ((volatile uint32_t *)0xfd02136c)
+//bit 19:16. DMC normal APB register secure control.
+//bit 19: 1: all can write those register. 0: the APB_PROT[0] must match the bit 16 to access those regsiter.
+//Bit15:12. DMC sticky APB regsiter secure control.
+//bit 15. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 12 to access those register.
+//bit 11:8. not used.
+//Bit 7:4. DMC DDR SDRAM protocal contorl register contorl
+//bit 11. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 4 to access those register.
+//bit 3:0. PHY APB regsiter secure control.
+//bit 3. 1: All APB bus can write those registers. 0: The APB_PROT[0] must match the bit 0 to access those register.
+#define P_DMC_DDR_PHY_CTRL ((volatile uint32_t *)0xfd0212fc)
+//bit 4 PwrOkIn
+//bit 3. PHY APB soft reset_n
+//bit 2. PHY soft reset_n
+//bit 1. PHY DfiClk enable.
+//bit 0. PHY DfiCtlClk enable.
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd021400
+// -----------------------------------------------
+//`define DMC_TEST_REG_BASE 32'hfd021400
+#define P_DMC_TEST_WRCMD_ADDR ((volatile uint32_t *)0xfd021770)
+// the current write cmd address.
+#define P_DMC_TEST_RDRSP_ADDR ((volatile uint32_t *)0xfd021774)
+// the failed read response address(for error data )
+#define P_DMC_TEST_RDCMD_ADDR ((volatile uint32_t *)0xfd021778)
+// the current read command address.
+#define P_DMC_TEST_WDG ((volatile uint32_t *)0xfd02177c)
+//31:16. write response watch dog.
+//15:0. read response watch dog.
+#define P_DMC_TEST_STA ((volatile uint32_t *)0xfd021780)
+//test start address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary.
+// for sha mode, address must be in 64 bytes boundary. that mean the last 6 bits must be 0.
+#define P_DMC_TEST_EDA ((volatile uint32_t *)0xfd021784)
+//test end address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary.
+// for sha mode, address must be in 64 bytes boundary. that mean the last 6bits must be 1.
+#define P_DMC_TEST_CTRL ((volatile uint32_t *)0xfd021788)
+//bit 31. enable test.
+//bit 30. when enable test, enable the write to DDR function.
+//bit 29. when enable test, enable the read from DDR function.
+//bit 28. Not used.
+//bit 27. enabe to compare data. when do the read enable to enable the error comparaion. suppose the read data should be same as the data in the write buffer.
+//bit 26. Not used.
+//bit 25. address generation type. 0: continuous increase the address in the range of test start address and test end address.
+// 1: test module would pick the random address from test start address and test end address.
+//bit 24. done type. 0 : use the DMC_TEST_NUM register as the counter of test numbers.
+// for write if the write command number == the DMC_TEST_NUM, the write is done.
+// for read if the read command number == the DMC TEST_num, the read id done. for one read command can be repeated repeat number times.
+// 1 : finshed at end address.
+//bit 23. wdata type. 1 : the first write is {WD3, WD2,WD1,WD0}, then the latter is the previous data plus a pattern.( { + WD7, + WD6, + WD5, + WD4}).
+// 0 : the WDATA is the data in write register.
+//bit 23. Not used.
+//bit 22:20. read repeat times. for non-sha function, we can define multi times of the read. the test module would repeat the same adddress repeat times.
+//bit 19. limit write. 0: no outstanding write request limitation.
+// 1: limit the outstanding write commands to the number of bits [15:8]
+//bit 18. limit read. 0. no outstanding read request limitation.
+// 1. limit the read outstanding request to the number of bits[7:0].
+//bit 17:16. Not used.
+//bit 15:8. write outstanding commands limit.
+//bit 7:0. read outstanding commands limit.
+#define P_DMC_TEST_NUM ((volatile uint32_t *)0xfd02178c)
+// how many test command for the test if the DMC_TEST_CTRL bit 24 is 0.
+#define P_DMC_TEST_WD0 ((volatile uint32_t *)0xfd021790)
+// write data 0 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD1 ((volatile uint32_t *)0xfd021794)
+// write data 1 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD2 ((volatile uint32_t *)0xfd021798)
+// write data 2 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD3 ((volatile uint32_t *)0xfd02179c)
+// write data 3 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD4 ((volatile uint32_t *)0xfd0217a0)
+// write data 4 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD5 ((volatile uint32_t *)0xfd0217a4)
+// write data 5 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD6 ((volatile uint32_t *)0xfd0217a8)
+// write data 6 for write command. also for read back data comparision.
+#define P_DMC_TEST_WD7 ((volatile uint32_t *)0xfd0217ac)
+// write data 7 for write command. also for read back data comparision.
+#define P_DMC_TEST_RD0 ((volatile uint32_t *)0xfd0217b0)
+// the read back data 0. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD1 ((volatile uint32_t *)0xfd0217b4)
+// the read back data 1. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD2 ((volatile uint32_t *)0xfd0217b8)
+// the read back data 2. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD3 ((volatile uint32_t *)0xfd0217bc)
+// the read back data 3. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD4 ((volatile uint32_t *)0xfd0217c0)
+// the read back data 4. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD5 ((volatile uint32_t *)0xfd0217c4)
+// the read back data 5. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD6 ((volatile uint32_t *)0xfd0217c8)
+// the read back data 6. if error happens, it would capture the first error data.
+#define P_DMC_TEST_RD7 ((volatile uint32_t *)0xfd0217cc)
+// the read back data 7. if error happens, it would capture the first error data.
+#define P_DMC_TEST_ERR_ADDR ((volatile uint32_t *)0xfd0217d0)
+// it capature the first error address.
+#define P_DMC_TEST_ERR_CNT ((volatile uint32_t *)0xfd0217d4)
+// how many data error happens in the whole test period.
+#define P_DMC_TEST_STS ((volatile uint32_t *)0xfd0217d8)
+//bit 31, test done bit. write 1 to clean.
+//bit 30, indicate address err
+//bit 29~7. not used.
+//bit 6. read data resp error(caused by security or rd latency).
+//bit 5. test MRR/MPR rd latency error. write 1 clear
+//bit 4, sha done. write 1 to clean.
+//bit 3, write done. write 1 to clean.
+//bit 2, read done. write 1 to clean
+//bit 1, write watchdog triggered. write 1 to clean
+//bit 0, read watchdog triggered. write 1 to clean.
+#define P_DMC_TEST_COMP_MASK ((volatile uint32_t *)0xfd0214cc)
+//32bits for DMC TEST COMPARE bit enable.
+//1 : to MASK this bit. 0: compare this bit.
+#define P_DMC_TEST_RDBI0 ((volatile uint32_t *)0xfd0214d0)
+//MPC RD FIFO command DBI read back data
+//bit 31:16 the second cycle.
+//bit 15:0 the first cycle.
+#define P_DMC_TEST_RDBI1 ((volatile uint32_t *)0xfd0214d4)
+//MPC RD FIFO command DBI read back data
+//bit 31:16. the Forth cycle.
+//bit 15:0. the third cycle.
+#define P_DMC_TEST_WSTRB0 ((volatile uint32_t *)0xfd0214d8)
+//MPC WR FIFO command DM bit write data
+//bit 31:16 the second cycle.
+//bit 15:0 the first cycle.
+#define P_DMC_TEST_DRAM_CMD ((volatile uint32_t *)0xfd0214e0)
+//bit 31. cmd done. write 0 to clean.
+//bit 30. data done. write 0 to clean.
+//bit 4:0. only one bit can be 1. read data stored in DMC_TEST_RD* write data from DMC_TEST_W
+//bit 4. LPDDR4 MPC write data command( MPC WR FIFO). Not support LPDDR4 in A1.
+//bit 3. LPDDR4 MPC read data command (MPC RD Calibration and RD FIFO).Not support LPDDR4 in A1.
+//bit 2. LPDDR4 MPC-1 command ( NOP, Start DQS interval ....)Not support LPDDR4 in A1.
+//bit 1. mrr comand.
+//bit 0. mrw command.
+#define P_DMC_TEST_DRAM_CMD_CODE ((volatile uint32_t *)0xfd0214e4)
+//bit 27:26. 128bits data cycles . 0: 1 clock cycles; 1: 2 clock cycles; 2: 3 clock cycles; 3:4 clock cycles.
+// LPDDR4 32bits: 4 clock cycles; LPDDR4 16bits: 2 clock cycles;
+// DDR3/4/LPDDR3 32 bits : 2 clock cycles. DDR3/4 16bits: 1 cycles.
+//bit 25 MRW/MRR/MPC command rank 1 select. 1: select. 0: not select. In A1, only rank0 supported.
+//bit 24. MRW/MRR/MPC command rank 0 select. 1: select. 0: not select.In A1, only rank0 supported.
+//bit 23:16 MR addr. DDR4 case : 18:16 ba[2:0]. 20:19 BG[1:0].
+//bit 15:0 opcode.
+#define P_DMC_TEST_DRAM_CMD_TIME ((volatile uint32_t *)0xfd0214e8)
+//bit 31:16 PRE CMD timer. //delay how many cycle to start the command.
+//bit 15:0 POST CMD timer //delay how many cycle after the command execute.
+//`endif
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_sec.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_reg.vh
+//
+//`ifdef DMC_REG_DEFINE
+//`else
+//`define DMC_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd020000
+// -----------------------------------------------
+//`define DMC_REG_BASE 32'hfd020000
+#define P_DMC_SOFT_RST2 ((volatile uint32_t *)0xfd02000c)
+//bit 31~11. reserved for future.
+//bit 10 DMC DFI cmd soft reset_n
+//bit 9 DMC DFI MISC soft reset_n
+//bit 8 DMC DFI data soft reset_n
+//bit 7 DMC DFI dcu soft reset_n
+//bit 6 DMC siu soft reset_n
+//bit 5. DMC test soft reset_n. 0 : reset. 1 : normal working mode.
+//bit 4. DMC low power control moudle soft reset_n. 0 : reset. 1 : normal working mode.
+//bit 3. DMC QOS monitor module soft reset_n. 0 : reset. 1 : normal working mode.
+//bit 2. DMC register modle soft reset_n. 0 : reset. 1 : normal working mode.
+//bit 1. DMC canvas transfer module soft reset_n. 0 : reset. 1 : normal working mode.
+//bit 0. DMC command buffers and command generation modules soft reset. 0 = reset. 1:
+#define P_DMC_VERSION ((volatile uint32_t *)0xfd020014)
+//read only 32'h000b0000. for A1
+#define P_DMC_MON_CTRL0 ((volatile uint32_t *)0xfd020080)
+//bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
+//bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
+//bit 1. qos monitor 1 enable.
+//bit 0. qos monitor 0 enable.
+#define P_DMC_MON_CTRL1 ((volatile uint32_t *)0xfd020084)
+//bit 8:0. qos monitor 0 channel select.
+//bit 8 to select DMC TEST
+//bit 7:0 each bit enable one AXI subID.
+#define P_DMC_MON_CTRL2 ((volatile uint32_t *)0xfd020088)
+//bit 8. to enabe monitor 0 second level subID selection for example device.
+//bit 7:0 each bit to enable one second level subID inside device.
+#define P_DMC_MON_CTRL3 ((volatile uint32_t *)0xfd02008c)
+//bit 8:0. qos monitor 1 channel select.
+//bit 8 to select DMC TEST
+//bit 7:0 each bit enable one AXI subID.
+#define P_DMC_MON_CTRL4 ((volatile uint32_t *)0xfd020090)
+//bit 8. to enabe monitor 1 second level subID selection for example device.
+//bit 7:0 each bit to enable one second level subID inside device.
+#define P_DMC_MON_ALL_REQ_CNT ((volatile uint32_t *)0xfd0200a4)
+// at the test period, the whole MMC request time.
+#define P_DMC_MON_ALL_GRANT_CNT ((volatile uint32_t *)0xfd0200a8)
+// at the test period, the whole MMC granted data cycles. 64bits unit.
+#define P_DMC_MON_ONE_GRANT_CNT ((volatile uint32_t *)0xfd0200ac)
+// at the test period, the granted data cycles for the selected channel and ports.
+#define P_DMC_MON_SEC_GRANT_CNT ((volatile uint32_t *)0xfd0200b0)
+// at the test period, the granted data cycles for the selected channel and ports.
+#define P_DMC_MON_TIMER ((volatile uint32_t *)0xfd0200bc)
+// timer for the monitor period.
+#define P_DMC_CLKG_CTRL2 ((volatile uint32_t *)0xfd0200c8)
+//bit 10 enable auto clock gating for dfi command generation
+//bit 9 enable auto clock gating for dram cntroller
+//bit 8 enable auto clock gating for dfi data path.
+//bit 7. enalbe auto clock gating for write rsp generation.
+//bit 6. enalbe auto clock gating for read rsp generation.
+//bit 5. enalbe auto clock gating for ddr0 command filter.
+//bit 4. enalbe auto clock gating for ddr0 write reorder buffer.
+//bit 3. enalbe auto clock gating for ddr0 write data buffer.
+//bit 2. enalbe auto clock gating for ddr0 read reorder buffer.
+//bit 1. reserved
+//bit 0. reserved
+#define P_DMC_CLKG_CTRL3 ((volatile uint32_t *)0xfd0200cc)
+//bit 10 force to disable the clock of dfi command generation
+//bit 9 force to disable the clock of dram cntroller
+//bit 8 force to disable the clock of dfi data path.
+//bit 7. force to disalbe the clock of write rsp generation.
+//bit 6. force to disalbe the clock of read rsp generation.
+//bit 5. force to disalbe the clock of command filter.
+//bit 4. force to disalbe the clock of write reorder buffer.
+//bit 3. force to disalbe the clock of write data buffer.
+//bit 2. force to disalbe the clock of read reorder buffer.
+//bit 1. reserved.
+//bit 0. reserved.
+#define P_DMC_CHAN_STS ((volatile uint32_t *)0xfd0200d8)
+//bit 4 always 1
+//bit 3 ddr0 write data buffer idle. 1 : idle 0: busy.
+//bit 2 always 1.
+//bit 1 ddr0 wbuf idle. 1 : idle 0: busy.
+//bit 0. axi0 channel idle. 1 : idle 0: busy.
+#define P_DMC_CMD_FILTER_CTRL3 ((volatile uint32_t *)0xfd020108)
+//bit 31. force wbuf empty.
+//bit 30:26 wbuf high level number
+//bit 25:21 wbuf mid level number
+//bit 20:16 wbuf low level number
+//bit 14:10 rbuf high level number
+//bit 9:5 rbuf middle level number
+//bit 4:0 rbuf low level number
+#define P_DMC_CMD_FILTER_CTRL4 ((volatile uint32_t *)0xfd02010c)
+//bit 29:25. tITW.long
+//bit 24:20. tITW. short
+//bit 19:12 tAP auto precharge the bank not used if idle that long time.
+//bit 11:6 write to read accesses if there write hit request.
+//bit 5:0 read to write accesses if there write hit request.
+#define P_DMC_CMD_FILTER_CTRL5 ((volatile uint32_t *)0xfd020110)
+//bit 31:24 Once ddr data bus switch to read, the maxmum read command number to give up the bus when there's write request pending for write buffer.
+//bit 23:16 Once ddr data bus switch to write, the maxmum write command number to give up the bus when there's read request pending too long.
+//bit 15:8. Once ddr data bus switch to read, the minimum read command number to transfer back to write stage if there's still pending read request.
+//bit 7:0. Once ddr data bus switch to write, the minimum write command number to transfer back to read stage if there's still pending write request.
+#define P_DMC_CMD_FILTER_CTRL6 ((volatile uint32_t *)0xfd020114)
+//bit 31:24 write urgent 3 request pending hold num.
+//bit 23:16 write urgent 2 request pending hold num.
+//bit 15:8. write urgent 1 request pending hold num.
+//bit 7:0. write urgent 0 request pending hold num.
+#define P_DMC_CMD_FILTER_CTRL7 ((volatile uint32_t *)0xfd020118)
+//bit 15:8 write to read waiting cycles if there write hit request.
+//bit 7:0 read to write waiting cycles if there write hit request.
+#define P_DMC_CMD_BUFFER_CTRL ((volatile uint32_t *)0xfd02011c)
+//bit 31:26 total write buffer number. default 32.
+//bit 25:20 total read buffer number. default 32.
+//bit 19:8 reserved.
+//bit 7:0 aw_pending_inc_num. incease write ugent level 1 when write command waiting to in write buffer that long.
+#define P_DMC_CMD_BUFFER_CTRL1 ((volatile uint32_t *)0xfd020120)
+//bit 29:24 read buffer number in non-urgent request.
+//bit 23:16 read buffer bank miss watch dog threshold.
+//bit 15:12 read buffer urgent level 3 counter inc weight.
+//bit 11:8 read buffer urgent level 2 counter inc weight.
+//bit 7:4 read buffer urgent level 1 counter inc weight.
+//bit 3:0 read buffer urgent level 0 counter inc weight.
+#define P_DMC_AXI0_CHAN_CTRL ((volatile uint32_t *)0xfd020200)
+//bit 31 AXI interface request enable.
+//bit 19 AXI interface auto clock gating enable. 1: enable; 0 disable.
+//bit 18 AXI interface clock disable. 1 : disable clock. 0 enable clock.
+//bit 17 AXI interface dmc clock domain soft reset. 0 : reset. 1 : normal working mode.
+//bit 16 AXI interface s0 clock domain soft reset. 0 : reset. 1 : normal working mode.
+//bit 15:12 ugt3 QOS level.
+//bit 11:8 ugt2 QOS level.
+//bit 7:4 ugt1 QOS level.
+//bit 3:0 not used.
+#define P_DMC_AXI0_HOLD_CTRL ((volatile uint32_t *)0xfd020204)
+//31:24 write hold num. max outstanding request number.
+//23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+//15:8 read hold num. max outstanding request number.
+//7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define P_DMC_AXI5_HOLD_CTRL ((volatile uint32_t *)0xfd020254)
+//31:24 write hold num. max outstanding request number.
+//23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+//15:8 read hold num. max outstanding request number.
+//7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+//`endif
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh
+//
+//`ifdef DMC_SIU_REG_DEFINE
+//`else
+//`define DMC_SIU_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd020400
+// -----------------------------------------------
+//`define DMC_DRAM_REG_BASE 32'hfd020400
+//in A1 project, don't support hardware controlled frequency change.
+#define P_DMC_DRAM_TMRD ((volatile uint32_t *)0xfd020400)
+//bit 3:0. tMRD.
+#define P_DMC_DRAM_TRFC ((volatile uint32_t *)0xfd020404)
+//bit 9:0 tRFC
+#define P_DMC_DRAM_TRP ((volatile uint32_t *)0xfd020408)
+//bit 21:16. tRP for precharge all banks.
+//bit 5:0. tRP for precharge one bank.
+#define P_DMC_DRAM_TRTW ((volatile uint32_t *)0xfd02040c)
+//bit 5:0 tRTW
+#define P_DMC_DRAM_TCL ((volatile uint32_t *)0xfd020410)
+//bit 5:0 tCL/tRL. read latency.
+#define P_DMC_DRAM_TCWL ((volatile uint32_t *)0xfd020414)
+//bit 5:0. CWL: write latency.
+#define P_DMC_DRAM_TRAS ((volatile uint32_t *)0xfd020418)
+//bit 7:0. tRAS. minimum active to precharge time for same bank.
+#define P_DMC_DRAM_TRC ((volatile uint32_t *)0xfd02041c)
+//bit 7:0. tRC. minimum active to active time for same bank.
+#define P_DMC_DRAM_TRCD ((volatile uint32_t *)0xfd020420)
+//bit 7:0 tRCD active to read/write timing for same bank.
+#define P_DMC_DRAM_TRRD ((volatile uint32_t *)0xfd020424)
+//bit 21:16. tRRD_l active bank A to active B in same band group for DDR4.
+//bit 5:0. tRRD/tRRD_s active bank A to active bank b time.
+//tRRD_s: active bank A to active bank b in different bank grousp for DDR4.
+#define P_DMC_DRAM_TFAW ((volatile uint32_t *)0xfd020428)
+//bit 8:0 tFAW. four active command windows
+#define P_DMC_DRAM_TRTP ((volatile uint32_t *)0xfd02042c)
+//bit 5:0 tRTP.
+#define P_DMC_DRAM_TWR ((volatile uint32_t *)0xfd020430)
+//bit 5:0 tWR.
+#define P_DMC_DRAM_TWTR ((volatile uint32_t *)0xfd020434)
+//bit 5:0 tWTR.
+#define P_DMC_DRAM_TCCD ((volatile uint32_t *)0xfd020438)
+//bit 19:16. tCCD/tCCD_l.
+//bit 3:0 tCCD/tCCD_s read to read command time or write to write command time.
+#define P_DMC_DRAM_TEXSR ((volatile uint32_t *)0xfd02043c)
+//bit 9:0. tEXSR. EXIT SELF-REFRESH to read/write command.
+#define P_DMC_DRAM_TXS ((volatile uint32_t *)0xfd020440)
+//bit 9:0 tXS. EXIT SELF_REFRESH to other command time
+#define P_DMC_DRAM_TXP ((volatile uint32_t *)0xfd020444)
+//bit 3:0. tXP. EXIT power down to other command time
+#define P_DMC_DRAM_TXPDLL ((volatile uint32_t *)0xfd020448)
+//bit 9:0. tXPDLL, EXIT power down to read/write command time(need to relock PLL).
+#define P_DMC_DRAM_TZQCS ((volatile uint32_t *)0xfd02044c)
+//bit 11:0. ZQCS command to other command time.
+#define P_DMC_DRAM_TCKSRE ((volatile uint32_t *)0xfd020450)
+//bit 4:0. enter self refresh to disable clock time.
+#define P_DMC_DRAM_TCKSRX ((volatile uint32_t *)0xfd020454)
+//bit 4:0. enable clock to exit self refresh time.
+#define P_DMC_DRAM_TCKE ((volatile uint32_t *)0xfd020458)
+//bit 4:0. CKE high or low minimum time.
+#define P_DMC_DRAM_TMOD ((volatile uint32_t *)0xfd02045c)
+//bit 4:0 tMOD. MRR/MRW to other command time.
+#define P_DMC_DRAM_TDQS ((volatile uint32_t *)0xfd020460)
+//bit 3:0 tDQS. the delay to access different rank.
+#define P_DMC_DRAM_TRSTL ((volatile uint32_t *)0xfd020464)
+//not used.
+#define P_DMC_DRAM_TZQLAT ((volatile uint32_t *)0xfd020468)
+//bit 5:0 ZQ LATCH command to other comand timing in LPDDR4 mode.
+#define P_DMC_DRAM_TMRR ((volatile uint32_t *)0xfd02046c)
+//bit 7:0 tMRR not used in DMC. not support MR READ.
+#define P_DMC_DRAM_TCKESR ((volatile uint32_t *)0xfd020470)
+//bit 9:0 tCKESR. CKE low minimum pulse in self refresh mode.
+#define P_DMC_DRAM_TDPD ((volatile uint32_t *)0xfd020474)
+//not support.
+#define P_DMC_DRAM_DFITCTRLDELAY ((volatile uint32_t *)0xfd020478)
+//bit 3:0. DFI_t_ctrldealy
+#define P_DMC_DRAM_DFITPHYWRDATA ((volatile uint32_t *)0xfd02047c)
+//bit 5:0. dfi_t_phy_wrdata.
+#define P_DMC_DRAM_DFITPHYWRLAT ((volatile uint32_t *)0xfd020480)
+//bit 5:0. dfi_t_phy_wrlat. in DDR3/4/LPDDR3 mode: WL -5. in LPDDR4 mode: WL -5 + 2.
+#define P_DMC_DRAM_DFITRDDATAEN ((volatile uint32_t *)0xfd020484)
+//bit 5:0. dfi_t_rddata_en. in DDR3/4/LPDDR3 mode: RL -5. in LPDDR4 mode : RL -5 + 1.
+#define P_DMC_DRAM_DFITPHYRDLAT ((volatile uint32_t *)0xfd020488)
+//bit 5:0. dfi_t_rdlat.
+#define P_DMC_DRAM_DFITCTRLUPDMIN ((volatile uint32_t *)0xfd02048c)
+//bit 7:0. CTRLUPD_MIN minimux clock cycle to maintain CTRLUPD_REQ.
+#define P_DMC_DRAM_DFITCTRLUPDMAX ((volatile uint32_t *)0xfd020490)
+//bit 7:0 CTRLUPD_MAX. maxmum clock cycle to maintain CTRLUPD_REQ if no CTRLUPD_ACK response.
+#define P_DMC_DRAM_DFITMSTRRESP ((volatile uint32_t *)0xfd020494)
+//not used.
+#define P_DMC_DRAM_DFITREFMSKI ((volatile uint32_t *)0xfd020498)
+//not used.
+#define P_DMC_DRAM_DFITCTRLUPDI ((volatile uint32_t *)0xfd02049c)
+//not used.
+#define P_DMC_DRAM_DFITDRAMCLK ((volatile uint32_t *)0xfd0204a0)
+//bit 17 dram clk1 enable.
+//bit 16 dram clk0 enable.
+//bit 15:8 DRAM CLK disable waiting time
+//bit 7:0 DRAM CLK enable enable timer
+#define P_DMC_DRAM_DFITLPRESP ((volatile uint32_t *)0xfd0204a8)
+//bit 3:0. dfi_lp_ctrl_req response time. after dfi_lp_ctrl_req asserted, and after response time if there's still no dfi_lp_ack respone, then drop the dfi_lp_ctrl_req.
+#define P_DMC_DRAM_DFITPHYMSTR ((volatile uint32_t *)0xfd0204ac)
+//bit 15 1: enable DFIPHYMASTER INTERFACE 0 disable DFIPHYMSTR en response.
+// always 0 we would use DFI_RETRAIN function for PHY retrain required from LPDDR4.
+#define P_DMC_DRAM_TCKECK ((volatile uint32_t *)0xfd0204b0)
+//bit 4:0. tCKECK from CKE low to assert dfi_dram_clk_disable time. this time + dfi_t_ctrl_delay
+#define P_DMC_DRAM_TREFI ((volatile uint32_t *)0xfd0204b4)
+//write this register will update the auto refresh related register to the auto refresh control logic.
+//bit 31:24: tZQCI dmc send zqci period. unit is how much auto refresh period.
+//bit 23:16 pvti dmc send dfi_ctrlupd_req period. unit is one auto refresh period.
+//bit 15:8. tREFI.dmc send auto refresh command period. unit is 100ns.
+//bit 7:0. t100ns period. unit is dmc clock cycles
+#define P_DMC_DRAM_TSR ((volatile uint32_t *)0xfd0204b8)
+//bit 5:0 tSR. self resfresh enter to exit time.
+#define P_DMC_DRAM_TCCDMW ((volatile uint32_t *)0xfd0204bc)
+//bit 5:0. 4*tCCD in LPDDR4 mask write.
+#define P_DMC_DRAM_TESCKE ((volatile uint32_t *)0xfd0204c0)
+//bit 5:0 tESCKE. enter self refresh to power time for LPDDR4.
+#define P_DMC_DRAM_TREFI_DDR3 ((volatile uint32_t *)0xfd0204c4)
+//7:0. 8*DDR3 SDRAM tREFI time . the unit is t100ns. use this to check in 8*tREFI time, the DMC should sent more than 16 auto REFRESH command.
+#define P_DMC_DRAM_TZQCAL ((volatile uint32_t *)0xfd0204c8)
+//7:0. ZQCAL for LPDDR4.
+#define P_DMC_DRAM_T10US ((volatile uint32_t *)0xfd0204cc)
+//10us clock cycle number used for LP2 mode.
+#define P_DMC_DRAM_TMRRI ((volatile uint32_t *)0xfd0204d0)
+//bit 7:0 tMRRI for MRR
+#define P_DMC_DRAM_DFITPHYUPDTYPE0 ((volatile uint32_t *)0xfd020600)
+//dfi_phyupd_ack hold time for dfi_phyupd_req type = 0.
+#define P_DMC_DRAM_DFITPHYUPDTYPE1 ((volatile uint32_t *)0xfd020604)
+//dfi_phyupd_ack hold time for dfi_phyupd_req type = 1.
+#define P_DMC_DRAM_DFITPHYUPDTYPE2 ((volatile uint32_t *)0xfd020608)
+//dfi_phyupd_ack hold time for dfi_phyupd_req type = 2.
+#define P_DMC_DRAM_DFITPHYUPDTYPE3 ((volatile uint32_t *)0xfd02060c)
+//dfi_phyupd_ack hold time for dfi_phyupd_req type = 3.
+#define P_DMC_DRAM_DFIODTCFG ((volatile uint32_t *)0xfd020610)
+//bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity.
+//bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1.
+//bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0.
+//bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1.
+//bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0.
+//bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity.
+//bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0.
+//bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1.
+//bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0.
+//bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1.
+#define P_DMC_DRAM_DFIODTCFG1 ((volatile uint32_t *)0xfd020614)
+//bit 27:24 ODT length for BL8 read transfer.
+//bit 19:16. ODT length for BL8 write transfer.
+//bit 12:8. ODT latency for reads. suppose to be 0.
+//bit 4:0. ODT latency for writes. suppose to be 0.
+#define P_DMC_DRAM_MCFG ((volatile uint32_t *)0xfd020618)
+//bit 14. 1: cke init low. 0 : cke init high.
+//bit 13 1: dbi write enable only for LPDDR4.
+//bit 12. 1: dbi read inversion. 0: dbi read high inversion.
+//bit 11. 1: dbi read enable. 0: dbi not enabled.
+//bit 10 1: enable staggered chip select for 2 ranks DRAM.
+//bit 9 1: enable send auto refresh command to DDR SDRAM when PCTL is in CFG/STOP state.
+//bit 8 send auto refr cmd before enter register triggered self refresh
+//bit 7 send auto refr cmd after exit regsiter triggered self refresh mode.
+//bit 6 disable dram clock after enter register triggered self refresh.
+//bit 5 send DFI_LP_REQ to PHY after enter register triggered elf refresh mode.
+//bit 4 send DRAM to power down mode after enter self refresh. ONLY for LPDDR4.
+//bit 3 send DFI_CTRLUPD_REQ after exit register triggered self refresh.
+//bit 2 send ZQCS command after exit register triggered self refresh.
+//bit 1 enable PHY triggered DFI_PHYUPD_REQ.
+//bit 0 2T mode. always 1 in DDR3/4 mode.
+#define P_DMC_DRAM_DFI_CTRL ((volatile uint32_t *)0xfd020624)
+//bit 31 siu_dfi_lat err generation enable. 1: if dfi read latency violation, generate data error. 0 : disable.
+//bit 30:0. not used.
+#define P_DMC_DRAM_DFIINITCFG ((volatile uint32_t *)0xfd020628)
+//bit 31. dfi_init_complete status. read only.
+//bit 15:14. Frequency set 1 dfi_freq_ratio value. Not used in A1
+//bit 12:8 Frequency set 1 dfi_freq value. Not used in A1
+//bit 7:6 Frequency set 0 dfi_freq_ratio value.
+//bit 5:1 Frequency set 0 dfi_freq value.
+//bit 0. dfi_init_start value can be use manually config dfi_init_start signal.
+#define P_DMC_DRAM_ZQ_CTRL ((volatile uint32_t *)0xfd02062c)
+// only bit 0 can be enable in A1.
+//bit 2 send ZQCS command to RANK0 then send comand to RANK1.
+//bit 1. send ZQCS command to both RANK0 and RANK1 together.
+//bit 0. send ZQCS command to only rank0.
+#define P_DMC_DRAM_APD_CTRL ((volatile uint32_t *)0xfd020630)
+//bit 19:16 DFI_LP_WAKEUP value in APD DFI_LP_REQ mode
+//bit 12 1: exit power down slow mode(waiting PLL LOCK). 0 : fast mode.
+//bit 11 enable DFI_LP_REQ when enter Auto power down mode.
+//bit 10 disable DFI_clk_disable when enter auto power down mode.
+//bit 9:0 0 disable auto power down mode.
+//non zero value to enable auto power down when DMC is in idle state for this number of clock cycles.
+#define P_DMC_DRAM_ASR_CTRL ((volatile uint32_t *)0xfd020634)
+//bit [25] LP2 mode PHYCLK enable. 1 : keep PHY clock enable after enter LP2 mode. 0 : shutdown PHY clock after enter LP2 mode.
+//bit [24] LP2 mode SRX waiting enable. if Self refresh too long, waiting 10us for the PHY stable before DDR SDRAM exit from self refresh state.
+//bit [23:20] DFI_LP_WAKEUP value in self refresh DFI_LP_REQ mode.
+//bit 17 : send REFRESH command after exit from auto self refersh mode(ASR).
+//bit 16 : send REFERSH command before enter to Auto self refresh mode(ASR).
+//bit 15 : send ZQCS command after exit from Auto self refresh mode(ASR).
+//bit 14 : send dfi_ctrl_upd after exit from ASR mode
+//bit 13 : send power down command when enter ASR mode. //for LPDDR4 only.
+//bit 12 : set the PHY enter LP2 mode after enter ASR mode.
+//bit 11 : send DFI_LP_REQ after enter ASR mode.
+//bit 10 : set DFI_CLK_DISABLE after enter ASR mode.
+//bit 9:0. 0 disable auto ASR mode.
+// Non-zero valule enable ASR mode. when DMC is in idle state for this number of clock cycles, the DMC will enter ASR mode.
+#define P_DMC_DRAM_PHYMSTR_CTRL ((volatile uint32_t *)0xfd020640)
+//not used in A1. should be all 0.
+#define P_DMC_DRAM_DFIODTRANKMAP ((volatile uint32_t *)0xfd020644)
+//not used in A1.
+#define P_DMC_DRAM_REFR_CTRL ((volatile uint32_t *)0xfd020648)
+//bit 17:8 auto refresh request pending cnt if there's page hit request.
+//bit 6 Disabled auto refresh command if over 16 auto refresh command sent in 2 TREFI_DDR3 period
+//bit 5 enable dmc send ZQCS command .
+//bit 4. enable dmc send DFI_CTRUPD_REQ.
+//bit 3:1. how many refresh command send for one period. = this number + 1
+//bit 0. enable dmc send auto refresh command.
+#define P_DMC_DRAM_FREQ_CTRL ((volatile uint32_t *)0xfd02064c)
+//bit 31 . wiret 1 to change freqency read 0: finished.
+//bit 30:9. not used.
+//bit 9. 1 : FREQ MRW done. let FREQ change machine continue.
+//bit 8 FREQ WAIT. 1 when freq change finishes, state machine stop at self refresh state in case there's something need to handle.
+// 0 after freq change finishes the state machine go back to access state.
+//bit 7 when change PLL setting, disable dmc clock
+//bit 6 when change PLL setting, disable PHY DfiClk and DfiCtlClk.
+//bit 5 check vpu_sleep_en ==1 when do FREQ change. if vpu_sleep_en == 0, just wait.
+//bit 4 nxt frequency selection. 1 = freq1. 0 = freq0.
+//bit 3:1. not used.
+//bit 0. current frequency selection.
+#define P_DMC_DRAM_SCFG ((volatile uint32_t *)0xfd020650)
+// bit 2:0 only one bit can be high at same time.
+// bit 2 1 : to ask PCTL enter ACCESS STATE. 0 : deassert the request.
+// bit 1 1 : to ask PCTL enter SELF REFRESH STATE. 0 : deassert the request.
+// bit 0 1 : to ask PCTL enter STOP/CONFIG STATE . 0 : deassert the request.
+#define P_DMC_DRAM_STAT ((volatile uint32_t *)0xfd020654)
+//bit 31 rd latency error. 1: means after dfiphytrdlat cycles, the read data still not back.
+//bit 28:24 dram_sr_state
+//bit 23:20 stop_st
+//bit 19:15 sleep_st
+//bit 14:12 ACCESS STATUS 0 : ACCESS is in normal working mode.
+//1 : ACCESS sending precharege command.
+//2 : ACCESS sending AUTO REFESH command.
+//3 : ACCESS sending DIF_CTRLUPD_REQ command.
+//4 : ACCESS sending ZQCS command to DDR DRAM(ZQCAL for LPDDR4).
+//5 : ACCESS sending ZQLATCH command to LPDDR4 only.
+//bit 11:8 APD STATUS: 0 : APD_IDLE
+//1 : APD sending PRECHARGE command
+//2 : APD sending CKE low command
+//3 : APD sending DISABLE DRAM CLOCK command
+//4 : APD sending DFI_LP_CTRL_REQ
+//5 : APD in Auto Power down mode.
+//6 : APD deassert DFI_LP_CTRL_REQ
+//7 : APD sending enable DRAM CLOCK command
+//8 : APD sending out CKE high command.
+//bit 7:4: DRAM_STATUS: 0 : DRAM IDLE
+//1 : DRAM_STOP/DRAM_CFG
+//2 : DRAM_ACCESS
+//3 : DRAM_SLEEP
+//4 : DRAM APD(AUTO POWER DOWN).
+//5 : IDLE -> STOP/CONFIG
+//6 : STOP -> SLEEP
+//7 : STOP -> ACCESS
+//8 : ACCESS -> SLEEP.
+//9 : ACCESS -> STOP
+//A : ACCESS -> APD
+//B : SLEEP -> STOP
+//C : SLEEP -> ACCESS
+//D : APD -> ACCESS
+//bit 3 reserved.
+//bit 2 1 : DRAM enter normal working state.
+//bit 1 1 : DRAM enter sleep state. self refresh state.
+//bit 0 1 : dram enter cfg state.
+#define P_DMC_DRAM_STAT1 ((volatile uint32_t *)0xfd020658)
+//bit 11:8 freq_st.
+//bit 7:5 train_st
+//bit 4:0 dram_phy_st
+#define P_DMC_PHY_RETRAINING_CTRL ((volatile uint32_t *)0xfd02065c)
+// A1 not support LPDDR4 so this register is not used in A1.
+//bit 31 : phy_retraining enable.
+//bit 30 : check vpu sleep_en.
+//bit 25:24 : retraining dfi_freq[4:3], the [2:0] bit still use the dfi_freq bits to keep the frequency.
+//bit 23:0: retraining period unit : 100ns.
+#define P_DMC_DFI_ERR_STAT ((volatile uint32_t *)0xfd020660)
+//LPDDR4 PHY DFI error infomation.
+//bit 31:20. not used.
+//bit 9. ddr0_dfi_error
+//bit 8:5 ddr0_dfi_error_info.
+//bit 4. ddr1_dfi_error.
+//bit 3:0. ddr1_dfi_error_info.
+#define P_DMC_LP2_TIMER ((volatile uint32_t *)0xfd020668)
+//bit 15:0. timer setting to measure how long the chip is entered LP2 mode.
+//this timer is 40bits counter with DMC PCLK.
+//we use the high 16bits to compare this register. if the counter is large than this number, that means the PHY need addition 10us after wakeup the PHY and before exit self_refresh mode.
+#define P_DMC_DRAM_DFI_SWAP_0 ((volatile uint32_t *)0xfd020680)
+//bit 5:0. dfi_act_n function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_1 ((volatile uint32_t *)0xfd020684)
+//bit 5:0. dfi_ras_n function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_2 ((volatile uint32_t *)0xfd020688)
+//bit 5:0. dfi_cas_n function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_3 ((volatile uint32_t *)0xfd02068c)
+//bit 5:0. dfi_we_n function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_4 ((volatile uint32_t *)0xfd020690)
+//bit 5:0. dfi_bg0 function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_5 ((volatile uint32_t *)0xfd020694)
+//bit 5:0. dfi_bg[1] function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_6 ((volatile uint32_t *)0xfd020698)
+//bit 5:0. dfi_ba[0] function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_7 ((volatile uint32_t *)0xfd02069c)
+//bit 5:0. dfi_ba[1] function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_8 ((volatile uint32_t *)0xfd0206a0)
+//bit 5:0. dfi_ba[2] function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_9 ((volatile uint32_t *)0xfd0206a4)
+//bit 5:0. dfi_a[0] function select
+// 6'h00 : the function itself.
+// 6'h01 : act_n.
+// 6'h02 : ras_n.
+// 6'h03 : cas_n.
+// 6'h04 : we_n.
+// 6'h05 : bg[0].
+// 6'h06 : bg[1].
+// 6'h07 : ba[0].
+// 6'h08 : ba[1].
+// 6'h09 : ba[2].
+// 6'h0a : a[0].
+// 6'h0b : a[1].
+// 6'h0c : a[2].
+// 6'h0d : a[3].
+// 6'h0e : a[4].
+// 6'h0f : a[5].
+// 6'h10 : a[6].
+// 6'h11 : a[7].
+// 6'h12 : a[8].
+// 6'h13 : a[9].
+// 6'h14 : a[10].
+// 6'h15 : a[11].
+// 6'h16 : a[12].
+// 6'h17 : a[13].
+// 6'h18 : a[14].
+// 6'h19 : a[15].
+// 6'h1a : a[16].
+// 6'h1b : a[17].
+#define P_DMC_DRAM_DFI_SWAP_10 ((volatile uint32_t *)0xfd0206a8)
+//bit 5:0. dfi_a[1] function select
+#define P_DMC_DRAM_DFI_SWAP_11 ((volatile uint32_t *)0xfd0206ac)
+//bit 5:0. dfi_a[2] function select
+#define P_DMC_DRAM_DFI_SWAP_12 ((volatile uint32_t *)0xfd0206b0)
+//bit 5:0. dfi_a[3] function select
+#define P_DMC_DRAM_DFI_SWAP_13 ((volatile uint32_t *)0xfd0206b4)
+//bit 5:0. dfi_a[4] function select
+#define P_DMC_DRAM_DFI_SWAP_14 ((volatile uint32_t *)0xfd0206b8)
+//bit 5:0. dfi_a[5] function select
+#define P_DMC_DRAM_DFI_SWAP_15 ((volatile uint32_t *)0xfd0206bc)
+//bit 5:0. dfi_a[6] function select
+#define P_DMC_DRAM_DFI_SWAP_16 ((volatile uint32_t *)0xfd0206c0)
+//bit 5:0. dfi_a[7] function select
+#define P_DMC_DRAM_DFI_SWAP_17 ((volatile uint32_t *)0xfd0206c4)
+//bit 5:0. dfi_a[8] function select
+#define P_DMC_DRAM_DFI_SWAP_18 ((volatile uint32_t *)0xfd0206c8)
+//bit 5:0. dfi_a[9] function select
+#define P_DMC_DRAM_DFI_SWAP_19 ((volatile uint32_t *)0xfd0206cc)
+//bit 5:0. dfi_a[10] function select
+#define P_DMC_DRAM_DFI_SWAP_20 ((volatile uint32_t *)0xfd0206d0)
+//bit 5:0. dfi_a[11] function select
+#define P_DMC_DRAM_DFI_SWAP_21 ((volatile uint32_t *)0xfd0206d4)
+//bit 5:0. dfi_a[12] function select
+#define P_DMC_DRAM_DFI_SWAP_22 ((volatile uint32_t *)0xfd0206d8)
+//bit 5:0. dfi_a[13] function select
+#define P_DMC_DRAM_DFI_SWAP_23 ((volatile uint32_t *)0xfd0206dc)
+//bit 5:0. dfi_a[14] function select
+#define P_DMC_DRAM_DFI_SWAP_24 ((volatile uint32_t *)0xfd0206e0)
+//bit 5:0. dfi_a[15] function select
+#define P_DMC_DRAM_DFI_SWAP_25 ((volatile uint32_t *)0xfd0206e4)
+//bit 5:0. dfi_a[16] function select
+#define P_DMC_DRAM_DFI_SWAP_26 ((volatile uint32_t *)0xfd0206ec)
+//bit 5:0. dfi_a[17] function select
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh
+//
+//`ifdef DMC_STICKY_REG_DEFINE
+//`else
+//`define DMC_STICKY_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd020800
+// -----------------------------------------------
+//`define DMC_STICKY_REG_BASE 32'hfd020800
+//those register is for software save some tempary value. and because it's in RAM. it won't lose if DMC get reseted.
+#define P_DMC_STICKY_0 ((volatile uint32_t *)0xfd020800)
+#define P_DMC_STICKY_1 ((volatile uint32_t *)0xfd020804)
+#define P_DMC_STICKY_2 ((volatile uint32_t *)0xfd020808)
+#define P_DMC_STICKY_3 ((volatile uint32_t *)0xfd02080c)
+#define P_DMC_STICKY_4 ((volatile uint32_t *)0xfd020810)
+#define P_DMC_STICKY_5 ((volatile uint32_t *)0xfd020814)
+#define P_DMC_STICKY_6 ((volatile uint32_t *)0xfd020818)
+#define P_DMC_STICKY_7 ((volatile uint32_t *)0xfd02081c)
+#define P_DMC_STICKY_8 ((volatile uint32_t *)0xfd020820)
+#define P_DMC_STICKY_9 ((volatile uint32_t *)0xfd020824)
+#define P_DMC_STICKY_10 ((volatile uint32_t *)0xfd020828)
+#define P_DMC_STICKY_11 ((volatile uint32_t *)0xfd02082c)
+#define P_DMC_STICKY_12 ((volatile uint32_t *)0xfd020830)
+#define P_DMC_STICKY_13 ((volatile uint32_t *)0xfd020834)
+#define P_DMC_STICKY_14 ((volatile uint32_t *)0xfd020838)
+#define P_DMC_STICKY_15 ((volatile uint32_t *)0xfd02083c)
+#define P_DMC_STICKY_16 ((volatile uint32_t *)0xfd020840)
+#define P_DMC_STICKY_17 ((volatile uint32_t *)0xfd020844)
+#define P_DMC_STICKY_18 ((volatile uint32_t *)0xfd020848)
+#define P_DMC_STICKY_19 ((volatile uint32_t *)0xfd02084c)
+#define P_DMC_STICKY_20 ((volatile uint32_t *)0xfd020850)
+#define P_DMC_STICKY_21 ((volatile uint32_t *)0xfd020854)
+#define P_DMC_STICKY_22 ((volatile uint32_t *)0xfd020858)
+#define P_DMC_STICKY_23 ((volatile uint32_t *)0xfd02085c)
+#define P_DMC_STICKY_24 ((volatile uint32_t *)0xfd020860)
+#define P_DMC_STICKY_25 ((volatile uint32_t *)0xfd020864)
+#define P_DMC_STICKY_26 ((volatile uint32_t *)0xfd020868)
+#define P_DMC_STICKY_27 ((volatile uint32_t *)0xfd02086c)
+#define P_DMC_STICKY_28 ((volatile uint32_t *)0xfd020870)
+#define P_DMC_STICKY_29 ((volatile uint32_t *)0xfd020874)
+#define P_DMC_STICKY_30 ((volatile uint32_t *)0xfd020878)
+#define P_DMC_STICKY_31 ((volatile uint32_t *)0xfd02087c)
+#define P_DMC_STICKY_32 ((volatile uint32_t *)0xfd020880)
+#define P_DMC_STICKY_33 ((volatile uint32_t *)0xfd020884)
+#define P_DMC_STICKY_34 ((volatile uint32_t *)0xfd020888)
+#define P_DMC_STICKY_35 ((volatile uint32_t *)0xfd02088c)
+#define P_DMC_STICKY_36 ((volatile uint32_t *)0xfd020890)
+#define P_DMC_STICKY_37 ((volatile uint32_t *)0xfd020894)
+#define P_DMC_STICKY_38 ((volatile uint32_t *)0xfd020898)
+#define P_DMC_STICKY_39 ((volatile uint32_t *)0xfd02089c)
+#define P_DMC_STICKY_40 ((volatile uint32_t *)0xfd0208a0)
+#define P_DMC_STICKY_41 ((volatile uint32_t *)0xfd0208a4)
+#define P_DMC_STICKY_42 ((volatile uint32_t *)0xfd0208a8)
+#define P_DMC_STICKY_43 ((volatile uint32_t *)0xfd0208ac)
+#define P_DMC_STICKY_44 ((volatile uint32_t *)0xfd0208b0)
+#define P_DMC_STICKY_45 ((volatile uint32_t *)0xfd0208b4)
+#define P_DMC_STICKY_46 ((volatile uint32_t *)0xfd0208b8)
+#define P_DMC_STICKY_47 ((volatile uint32_t *)0xfd0208bc)
+#define P_DMC_STICKY_48 ((volatile uint32_t *)0xfd0208c0)
+#define P_DMC_STICKY_49 ((volatile uint32_t *)0xfd0208c4)
+#define P_DMC_STICKY_50 ((volatile uint32_t *)0xfd0208c8)
+#define P_DMC_STICKY_51 ((volatile uint32_t *)0xfd0208cc)
+#define P_DMC_STICKY_52 ((volatile uint32_t *)0xfd0208d0)
+#define P_DMC_STICKY_53 ((volatile uint32_t *)0xfd0208d4)
+#define P_DMC_STICKY_54 ((volatile uint32_t *)0xfd0208d8)
+#define P_DMC_STICKY_55 ((volatile uint32_t *)0xfd0208dc)
+#define P_DMC_STICKY_56 ((volatile uint32_t *)0xfd0208e0)
+#define P_DMC_STICKY_57 ((volatile uint32_t *)0xfd0208e4)
+#define P_DMC_STICKY_58 ((volatile uint32_t *)0xfd0208e8)
+#define P_DMC_STICKY_59 ((volatile uint32_t *)0xfd0208ec)
+#define P_DMC_STICKY_60 ((volatile uint32_t *)0xfd0208f0)
+#define P_DMC_STICKY_61 ((volatile uint32_t *)0xfd0208f4)
+#define P_DMC_STICKY_62 ((volatile uint32_t *)0xfd0208f8)
+#define P_DMC_STICKY_63 ((volatile uint32_t *)0xfd0208fc)
+//`endif
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh
+//
+//========================================================================
+// APB0_RESET_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000000
+// -----------------------------------------------
+#define P_RESETCTRL_RESET0 ((volatile uint32_t *)0xfe000000)
+#define P_RESETCTRL_RESET1 ((volatile uint32_t *)0xfe000004)
+#define P_RESETCTRL_RESET2 ((volatile uint32_t *)0xfe000008)
+#define P_RESETCTRL_RESET0_LEVEL ((volatile uint32_t *)0xfe000040)
+#define P_RESETCTRL_RESET1_LEVEL ((volatile uint32_t *)0xfe000044)
+#define P_RESETCTRL_RESET2_LEVEL ((volatile uint32_t *)0xfe000048)
+#define P_RESETCTRL_RESET0_MASK ((volatile uint32_t *)0xfe000080)
+#define P_RESETCTRL_RESET1_MASK ((volatile uint32_t *)0xfe000084)
+#define P_RESETCTRL_RESET2_MASK ((volatile uint32_t *)0xfe000088)
+#define P_RESETCTRL_RESET_HOLD_CYC ((volatile uint32_t *)0xfe0000c0)
+#define P_RESETCTRL_WATCHDOG_CTRL0 ((volatile uint32_t *)0xfe000100)
+#define P_RESETCTRL_WATCHDOG_CTRL1 ((volatile uint32_t *)0xfe000104)
+#define P_RESETCTRL_WATCHDOG_CNT ((volatile uint32_t *)0xfe000108)
+#define P_RESETCTRL_WATCHDOG_CLR ((volatile uint32_t *)0xfe00010c)
+#define P_RESETCTRL_SEC_RESET0 ((volatile uint32_t *)0xfe000140)
+#define P_RESETCTRL_SEC_RESET0_LEVEL ((volatile uint32_t *)0xfe000144)
+#define P_RESETCTRL_SEC_RESET0_MASK ((volatile uint32_t *)0xfe000148)
+//========================================================================
+// APB0_PAD_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000400
+// -----------------------------------------------
+#define P_PADCTRL_PIN_MUX_REG0 ((volatile uint32_t *)0xfe000400)
+#define P_PADCTRL_PIN_MUX_REG1 ((volatile uint32_t *)0xfe000404)
+#define P_PADCTRL_PIN_MUX_REG2 ((volatile uint32_t *)0xfe000408)
+#define P_PADCTRL_PIN_MUX_REG3 ((volatile uint32_t *)0xfe00040c)
+#define P_PADCTRL_PIN_MUX_REG4 ((volatile uint32_t *)0xfe000410)
+#define P_PADCTRL_PIN_MUX_REG5 ((volatile uint32_t *)0xfe000414)
+#define P_PADCTRL_PIN_MUX_REG6 ((volatile uint32_t *)0xfe000418)
+#define P_PADCTRL_PIN_MUX_REG7 ((volatile uint32_t *)0xfe00041c)
+#define P_PADCTRL_PIN_MUX_REG8 ((volatile uint32_t *)0xfe000420)
+#define P_PADCTRL_PIN_MUX_REG9 ((volatile uint32_t *)0xfe000424)
+#define P_PADCTRL_PIN_MUX_REGA ((volatile uint32_t *)0xfe000428)
+#define P_PADCTRL_PIN_MUX_REGB ((volatile uint32_t *)0xfe00042c)
+#define P_PADCTRL_PIN_MUX_REGC ((volatile uint32_t *)0xfe000430)
+#define P_PADCTRL_PIN_MUX_REGD ((volatile uint32_t *)0xfe000434)
+#define P_PADCTRL_PIN_MUX_REGE ((volatile uint32_t *)0xfe000438)
+#define P_PADCTRL_PIN_MUX_REGF ((volatile uint32_t *)0xfe00043c)
+#define P_PADCTRL_GPIO_IRQ_CTRL0 ((volatile uint32_t *)0xfe000440)
+#define P_PADCTRL_GPIO_IRQ_CTRL1 ((volatile uint32_t *)0xfe000444)
+#define P_PADCTRL_GPIO_IRQ_CTRL2 ((volatile uint32_t *)0xfe000448)
+#define P_PADCTRL_GPIO_IRQ_CTRL3 ((volatile uint32_t *)0xfe00044c)
+#define P_PADCTRL_GPIO_IRQ_CTRL4 ((volatile uint32_t *)0xfe000450)
+#define P_PADCTRL_WORLDSYNC_CTRL0 ((volatile uint32_t *)0xfe000460)
+#define P_PADCTRL_GPIO_MSR_CTRL0 ((volatile uint32_t *)0xfe000464)
+#define P_PADCTRL_GPIOP_I ((volatile uint32_t *)0xfe000480)
+#define P_PADCTRL_GPIOP_O ((volatile uint32_t *)0xfe000484)
+#define P_PADCTRL_GPIOP_OEN ((volatile uint32_t *)0xfe000488)
+#define P_PADCTRL_GPIOP_PULL_EN ((volatile uint32_t *)0xfe00048c)
+#define P_PADCTRL_GPIOP_PULL_UP ((volatile uint32_t *)0xfe000490)
+#define P_PADCTRL_GPIOP_DS ((volatile uint32_t *)0xfe000494)
+#define P_PADCTRL_GPIOB_I ((volatile uint32_t *)0xfe0004c0)
+#define P_PADCTRL_GPIOB_O ((volatile uint32_t *)0xfe0004c4)
+#define P_PADCTRL_GPIOB_OEN ((volatile uint32_t *)0xfe0004c8)
+#define P_PADCTRL_GPIOB_PULL_EN ((volatile uint32_t *)0xfe0004cc)
+#define P_PADCTRL_GPIOB_PULL_UP ((volatile uint32_t *)0xfe0004d0)
+#define P_PADCTRL_GPIOB_DS ((volatile uint32_t *)0xfe0004d4)
+#define P_PADCTRL_GPIOX_I ((volatile uint32_t *)0xfe000500)
+#define P_PADCTRL_GPIOX_O ((volatile uint32_t *)0xfe000504)
+#define P_PADCTRL_GPIOX_OEN ((volatile uint32_t *)0xfe000508)
+#define P_PADCTRL_GPIOX_PULL_EN ((volatile uint32_t *)0xfe00050c)
+#define P_PADCTRL_GPIOX_PULL_UP ((volatile uint32_t *)0xfe000510)
+#define P_PADCTRL_GPIOX_DS ((volatile uint32_t *)0xfe000514)
+#define P_PADCTRL_GPIOX_DS_EXT ((volatile uint32_t *)0xfe000518)
+#define P_PADCTRL_GPIOF_I ((volatile uint32_t *)0xfe000540)
+#define P_PADCTRL_GPIOF_O ((volatile uint32_t *)0xfe000544)
+#define P_PADCTRL_GPIOF_OEN ((volatile uint32_t *)0xfe000548)
+#define P_PADCTRL_GPIOF_PULL_EN ((volatile uint32_t *)0xfe00054c)
+#define P_PADCTRL_GPIOF_PULL_UP ((volatile uint32_t *)0xfe000550)
+#define P_PADCTRL_GPIOF_DS ((volatile uint32_t *)0xfe000554)
+#define P_PADCTRL_GPIOA_I ((volatile uint32_t *)0xfe000580)
+#define P_PADCTRL_GPIOA_O ((volatile uint32_t *)0xfe000584)
+#define P_PADCTRL_GPIOA_OEN ((volatile uint32_t *)0xfe000588)
+#define P_PADCTRL_GPIOA_PULL_EN ((volatile uint32_t *)0xfe00058c)
+#define P_PADCTRL_GPIOA_PULL_UP ((volatile uint32_t *)0xfe000590)
+#define P_PADCTRL_GPIOA_DS ((volatile uint32_t *)0xfe000594)
+#define P_PADCTRL_TESTN_I ((volatile uint32_t *)0xfe0005c0)
+#define P_PADCTRL_TESTN_O ((volatile uint32_t *)0xfe0005c4)
+#define P_PADCTRL_TESTN_OEN ((volatile uint32_t *)0xfe0005c8)
+#define P_PADCTRL_TESTN_PULL_EN ((volatile uint32_t *)0xfe0005cc)
+#define P_PADCTRL_TESTN_PULL_UP ((volatile uint32_t *)0xfe0005d0)
+#define P_PADCTRL_TESTN_DS ((volatile uint32_t *)0xfe0005d4)
+#define P_PADCTRL_MUTE_CTRL ((volatile uint32_t *)0xfe000600)
+//========================================================================
+// APB0_CLK_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000800
+// -----------------------------------------------
+#define P_CLKTREE_SYS_OSCIN_CTRL ((volatile uint32_t *)0xfe000800)
+#define P_CLKTREE_RTC_BY_OSCIN_CTRL0 ((volatile uint32_t *)0xfe000804)
+#define P_CLKTREE_RTC_BY_OSCIN_CTRL1 ((volatile uint32_t *)0xfe000808)
+#define P_CLKTREE_RTC_CTRL ((volatile uint32_t *)0xfe00080c)
+#define P_CLKTREE_SYS_CLK_CTRL0 ((volatile uint32_t *)0xfe000810)
+#define P_CLKTREE_AXI_CLK_CTRL0 ((volatile uint32_t *)0xfe000814)
+#define P_CLKTREE_SYS_CLK_EN0 ((volatile uint32_t *)0xfe00081c)
+#define P_CLKTREE_SYS_CLK_EN1 ((volatile uint32_t *)0xfe000820)
+#define P_CLKTREE_AXI_CLK_EN ((volatile uint32_t *)0xfe000824)
+#define P_CLKTREE_DSPA_CLK_EN ((volatile uint32_t *)0xfe000828)
+#define P_CLKTREE_DSPB_CLK_EN ((volatile uint32_t *)0xfe00082c)
+#define P_CLKTREE_DSPA_CLK_CTRL0 ((volatile uint32_t *)0xfe000830)
+#define P_CLKTREE_DSPB_CLK_CTRL0 ((volatile uint32_t *)0xfe000834)
+#define P_CLKTREE_CLK12_24_CTRL ((volatile uint32_t *)0xfe000838)
+#define P_CLKTREE_GEN_CLK_CTRL ((volatile uint32_t *)0xfe00083c)
+#define P_CLKTREE_TIMESTAMP_CTRL0 ((volatile uint32_t *)0xfe000840)
+#define P_CLKTREE_TIMESTAMP_CTRL1 ((volatile uint32_t *)0xfe000844)
+#define P_CLKTREE_TIMESTAMP_CTRL2 ((volatile uint32_t *)0xfe000848)
+#define P_CLKTREE_TIMESTAMP_VAL0 ((volatile uint32_t *)0xfe00084c)
+#define P_CLKTREE_TIMESTAMP_VAL1 ((volatile uint32_t *)0xfe000850)
+#define P_CLKTREE_TIMEBASE_CTRL0 ((volatile uint32_t *)0xfe000854)
+#define P_CLKTREE_TIMEBASE_CTRL1 ((volatile uint32_t *)0xfe000858)
+#define P_CLKTREE_SAR_ADC_CLK_CTRL ((volatile uint32_t *)0xfe0008c0)
+#define P_CLKTREE_PWM_CLK_AB_CTRL ((volatile uint32_t *)0xfe0008c4)
+#define P_CLKTREE_PWM_CLK_CD_CTRL ((volatile uint32_t *)0xfe0008c8)
+#define P_CLKTREE_PWM_CLK_EF_CTRL ((volatile uint32_t *)0xfe0008cc)
+#define P_CLKTREE_SPICC_CLK_CTRL ((volatile uint32_t *)0xfe0008d0)
+#define P_CLKTREE_TS_CLK_CTRL ((volatile uint32_t *)0xfe0008d4)
+#define P_CLKTREE_SPIFC_CLK_CTRL ((volatile uint32_t *)0xfe0008d8)
+#define P_CLKTREE_USB_BUSCLK_CTRL ((volatile uint32_t *)0xfe0008dc)
+#define P_CLKTREE_SD_EMMC_CLK_CTRL ((volatile uint32_t *)0xfe0008e0)
+#define P_CLKTREE_CECA_CLK_CTRL0 ((volatile uint32_t *)0xfe0008e4)
+#define P_CLKTREE_CECA_CLK_CTRL1 ((volatile uint32_t *)0xfe0008e8)
+#define P_CLKTREE_CECB_CLK_CTRL0 ((volatile uint32_t *)0xfe0008ec)
+#define P_CLKTREE_CECB_CLK_CTRL1 ((volatile uint32_t *)0xfe0008f0)
+#define P_CLKTREE_PSRAM_CLK_CTRL ((volatile uint32_t *)0xfe0008f4)
+#define P_CLKTREE_DMC_CLK_CTRL ((volatile uint32_t *)0xfe0008f8)
+#define P_CLKTREE_FCLK_DIV1_SEL ((volatile uint32_t *)0xfe0008fc)
+#define P_CLKTREE_TST_CTRL0 ((volatile uint32_t *)0xfe000900)
+//========================================================================
+// APB0_CEC - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000c00
+// -----------------------------------------------
+#define P_CECA_GEN_CNTL ((volatile uint32_t *)0xfe000c00)
+#define P_CECA_RW_REG ((volatile uint32_t *)0xfe000c04)
+#define P_CECA_INTR_MASKN ((volatile uint32_t *)0xfe000c08)
+#define P_CECA_INTR_CLR ((volatile uint32_t *)0xfe000c0c)
+#define P_CECA_INTR_STAT ((volatile uint32_t *)0xfe000c10)
+#define P_CECB_GEN_CNTL ((volatile uint32_t *)0xfe000c40)
+#define P_CECB_RW_REG ((volatile uint32_t *)0xfe000c44)
+#define P_CECB_INTR_MASKN ((volatile uint32_t *)0xfe000c48)
+#define P_CECB_INTR_CLR ((volatile uint32_t *)0xfe000c4c)
+#define P_CECB_INTR_STAT ((volatile uint32_t *)0xfe000c50)
+//========================================================================
+// APB0_IR_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001000
+// -----------------------------------------------
+#define P_IRCTRL_IR_DEC_LDR_ACTIVE ((volatile uint32_t *)0xfe001000)
+#define P_IRCTRL_IR_DEC_LDR_IDLE ((volatile uint32_t *)0xfe001004)
+#define P_IRCTRL_IR_DEC_LDR_REPEAT ((volatile uint32_t *)0xfe001008)
+#define P_IRCTRL_IR_DEC_BIT_0 ((volatile uint32_t *)0xfe00100c)
+#define P_IRCTRL_IR_DEC_REG0 ((volatile uint32_t *)0xfe001010)
+#define P_IRCTRL_IR_DEC_FRAME ((volatile uint32_t *)0xfe001014)
+#define P_IRCTRL_IR_DEC_STATUS ((volatile uint32_t *)0xfe001018)
+#define P_IRCTRL_IR_DEC_REG1 ((volatile uint32_t *)0xfe00101c)
+#define P_IRCTRL_MF_IR_DEC_LDR_ACTIVE ((volatile uint32_t *)0xfe001040)
+#define P_IRCTRL_MF_IR_DEC_LDR_IDLE ((volatile uint32_t *)0xfe001044)
+#define P_IRCTRL_MF_IR_DEC_LDR_REPEAT ((volatile uint32_t *)0xfe001048)
+#define P_IRCTRL_MF_IR_DEC_BIT_0 ((volatile uint32_t *)0xfe00104c)
+#define P_IRCTRL_MF_IR_DEC_REG0 ((volatile uint32_t *)0xfe001050)
+#define P_IRCTRL_MF_IR_DEC_FRAME ((volatile uint32_t *)0xfe001054)
+#define P_IRCTRL_MF_IR_DEC_STATUS ((volatile uint32_t *)0xfe001058)
+#define P_IRCTRL_MF_IR_DEC_REG1 ((volatile uint32_t *)0xfe00105c)
+#define P_IRCTRL_MF_IR_DEC_REG2 ((volatile uint32_t *)0xfe001060)
+#define P_IRCTRL_MF_IR_DEC_DURATN2 ((volatile uint32_t *)0xfe001064)
+#define P_IRCTRL_MF_IR_DEC_DURATN3 ((volatile uint32_t *)0xfe001068)
+#define P_IRCTRL_MF_IR_DEC_FRAME1 ((volatile uint32_t *)0xfe00106c)
+#define P_IRCTRL_MF_IR_DEC_STATUS1 ((volatile uint32_t *)0xfe001070)
+#define P_IRCTRL_MF_IR_DEC_STATUS2 ((volatile uint32_t *)0xfe001074)
+#define P_IRCTRL_MF_IR_DEC_REG3 ((volatile uint32_t *)0xfe001078)
+#define P_IRCTRL_MF_IR_DEC_FRAME_RSV0 ((volatile uint32_t *)0xfe00107c)
+#define P_IRCTRL_MF_IR_DEC_FRAME_RSV1 ((volatile uint32_t *)0xfe001080)
+#define P_IRCTRL_MF_IR_DEC_FILTE ((volatile uint32_t *)0xfe001084)
+#define P_IRCTRL_MF_IR_DEC_IRQ_CTL ((volatile uint32_t *)0xfe001088)
+#define P_IRCTRL_MF_IR_DEC_FIFO_CTL ((volatile uint32_t *)0xfe00108c)
+#define P_IRCTRL_MF_IR_DEC_WIDTH_NEW ((volatile uint32_t *)0xfe001090)
+#define P_IRCTRL_MF_IR_DEC_REPEAT_DET ((volatile uint32_t *)0xfe001094)
+#define P_IRCTRL_IR_DEC_DEMOD_CNTL0 ((volatile uint32_t *)0xfe0010c0)
+#define P_IRCTRL_IR_DEC_DEMOD_CNTL1 ((volatile uint32_t *)0xfe0010c4)
+#define P_IRCTRL_IR_DEC_DEMOD_IIR_THD ((volatile uint32_t *)0xfe0010c8)
+#define P_IRCTRL_IR_DEC_DEMOD_THD0 ((volatile uint32_t *)0xfe0010cc)
+#define P_IRCTRL_IR_DEC_DEMOD_THD1 ((volatile uint32_t *)0xfe0010d0)
+#define P_IRCTRL_IR_DEC_DEMOD_SUM_CNT0 ((volatile uint32_t *)0xfe0010d4)
+#define P_IRCTRL_IR_DEC_DEMOD_SUM_CNT1 ((volatile uint32_t *)0xfe0010d8)
+#define P_IRCTRL_IR_DEC_DEMOD_CNT0 ((volatile uint32_t *)0xfe0010dc)
+#define P_IRCTRL_IR_DEC_DEMOD_CNT1 ((volatile uint32_t *)0xfe0010e0)
+#define P_IRCTRL_IR_BLASTER_ADDR0 ((volatile uint32_t *)0xfe00110c)
+#define P_IRCTRL_IR_BLASTER_ADDR1 ((volatile uint32_t *)0xfe001110)
+#define P_IRCTRL_IR_BLASTER_ADDR2 ((volatile uint32_t *)0xfe001114)
+#define P_IRCTRL_IR_BLASTER_ADDR3 ((volatile uint32_t *)0xfe001118)
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001400
+// -----------------------------------------------
+#define P_I2C_M_A_CONTROL_REG ((volatile uint32_t *)0xfe001400)
+#define P_I2C_M_A_SLAVE_ADDR ((volatile uint32_t *)0xfe001404)
+#define P_I2C_M_A_TOKEN_LIST0 ((volatile uint32_t *)0xfe001408)
+#define P_I2C_M_A_TOKEN_LIST1 ((volatile uint32_t *)0xfe00140c)
+#define P_I2C_M_A_WDATA_REG0 ((volatile uint32_t *)0xfe001410)
+#define P_I2C_M_A_WDATA_REG1 ((volatile uint32_t *)0xfe001414)
+#define P_I2C_M_A_RDATA_REG0 ((volatile uint32_t *)0xfe001418)
+#define P_I2C_M_A_RDATA_REG1 ((volatile uint32_t *)0xfe00141c)
+#define P_I2C_M_A_TIMEOUT_TH ((volatile uint32_t *)0xfe001420)
+//========================================================================
+// APB0_I2C_S - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001800
+// -----------------------------------------------
+#define P_I2C_S_A_CONTROL_REG ((volatile uint32_t *)0xfe001800)
+#define P_I2C_S_A_SEND_REG ((volatile uint32_t *)0xfe001804)
+#define P_I2C_S_A_RECV_REG ((volatile uint32_t *)0xfe001808)
+#define P_I2C_S_A_CNTL1_REG ((volatile uint32_t *)0xfe00180c)
+//========================================================================
+// APB0_UART_A - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001c00
+// -----------------------------------------------
+#define P_UART_A_WFIFO ((volatile uint32_t *)0xfe001c00)
+#define P_UART_A_RFIFO ((volatile uint32_t *)0xfe001c04)
+#define P_UART_A_CONTROL ((volatile uint32_t *)0xfe001c08)
+#define P_UART_A_STATUS ((volatile uint32_t *)0xfe001c0c)
+#define P_UART_A_MISC ((volatile uint32_t *)0xfe001c10)
+#define P_UART_A_REG5 ((volatile uint32_t *)0xfe001c14)
+//========================================================================
+// APB0_UART_B - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002000
+// -----------------------------------------------
+#define P_UART_B_WFIFO ((volatile uint32_t *)0xfe002000)
+#define P_UART_B_RFIFO ((volatile uint32_t *)0xfe002004)
+#define P_UART_B_CONTROL ((volatile uint32_t *)0xfe002008)
+#define P_UART_B_STATUS ((volatile uint32_t *)0xfe00200c)
+#define P_UART_B_MISC ((volatile uint32_t *)0xfe002010)
+#define P_UART_B_REG5 ((volatile uint32_t *)0xfe002014)
+//========================================================================
+// APB0_PWM_AB - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002400
+// -----------------------------------------------
+#define P_PWMAB_PWM_A ((volatile uint32_t *)0xfe002400)
+#define P_PWMAB_PWM_B ((volatile uint32_t *)0xfe002404)
+#define P_PWMAB_MISC_REG_AB ((volatile uint32_t *)0xfe002408)
+#define P_PWMAB_DELTA_SIGMA_AB ((volatile uint32_t *)0xfe00240c)
+#define P_PWMAB_TIME_AB ((volatile uint32_t *)0xfe002410)
+#define P_PWMAB_A2 ((volatile uint32_t *)0xfe002414)
+#define P_PWMAB_B2 ((volatile uint32_t *)0xfe002418)
+#define P_PWMAB_BLINK_AB ((volatile uint32_t *)0xfe00241c)
+#define P_PWMAB_LOCK_AB ((volatile uint32_t *)0xfe002420)
+//========================================================================
+// APB0_PWM_CD - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002800
+// -----------------------------------------------
+#define P_PWMCD_PWM_C ((volatile uint32_t *)0xfe002800)
+#define P_PWMCD_PWM_D ((volatile uint32_t *)0xfe002804)
+#define P_PWMCD_MISC_REG_CD ((volatile uint32_t *)0xfe002808)
+#define P_PWMCD_DELTA_SIGMA_CD ((volatile uint32_t *)0xfe00280c)
+#define P_PWMCD_TIME_CD ((volatile uint32_t *)0xfe002810)
+#define P_PWMCD_C2 ((volatile uint32_t *)0xfe002814)
+#define P_PWMCD_D2 ((volatile uint32_t *)0xfe002818)
+#define P_PWMCD_BLINK_CD ((volatile uint32_t *)0xfe00281c)
+#define P_PWMCD_LOCK_CD ((volatile uint32_t *)0xfe002820)
+//========================================================================
+// APB0_SARADC - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002c00
+// -----------------------------------------------
+#define P_SAR_ADC_REG0 ((volatile uint32_t *)0xfe002c00)
+#define P_SAR_ADC_CHAN_LIST ((volatile uint32_t *)0xfe002c04)
+#define P_SAR_ADC_AVG_CNTL ((volatile uint32_t *)0xfe002c08)
+#define P_SAR_ADC_REG3 ((volatile uint32_t *)0xfe002c0c)
+#define P_SAR_ADC_DELAY ((volatile uint32_t *)0xfe002c10)
+#define P_SAR_ADC_LAST_RD ((volatile uint32_t *)0xfe002c14)
+#define P_SAR_ADC_FIFO_RD ((volatile uint32_t *)0xfe002c18)
+#define P_SAR_ADC_AUX_SW ((volatile uint32_t *)0xfe002c1c)
+#define P_SAR_ADC_CHAN_10_SW ((volatile uint32_t *)0xfe002c20)
+#define P_SAR_ADC_DETECT_IDLE_SW ((volatile uint32_t *)0xfe002c24)
+#define P_SAR_ADC_DELTA_10 ((volatile uint32_t *)0xfe002c28)
+#define P_SAR_ADC_REG11 ((volatile uint32_t *)0xfe002c2c)
+#define P_SAR_ADC_REG12 ((volatile uint32_t *)0xfe002c30)
+#define P_SAR_ADC_REG13 ((volatile uint32_t *)0xfe002c34)
+#define P_SAR_ADC_CHNL01 ((volatile uint32_t *)0xfe002c38)
+#define P_SAR_ADC_CHNL23 ((volatile uint32_t *)0xfe002c3c)
+#define P_SAR_ADC_CHNL45 ((volatile uint32_t *)0xfe002c40)
+#define P_SAR_ADC_CHNL67 ((volatile uint32_t *)0xfe002c44)
+//========================================================================
+// JTAGCTRL_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003000
+// -----------------------------------------------
+#define P_JTAGCTRL_CTRL0 ((volatile uint32_t *)0xfe003000)
+#define P_JTAGCTRL_PWD_CTRL0 ((volatile uint32_t *)0xfe003004)
+#define P_JTAGCTRL_PWD_ADDR0 ((volatile uint32_t *)0xfe003008)
+#define P_JTAGCTRL_PWD_ADDR1 ((volatile uint32_t *)0xfe00300c)
+#define P_JTAGCTRL_PWD_ADDR2 ((volatile uint32_t *)0xfe003010)
+#define P_JTAGCTRL_PWD_ADDR3 ((volatile uint32_t *)0xfe003014)
+#define P_JTAGCTRL_PWD_VALUE0 ((volatile uint32_t *)0xfe003018)
+#define P_JTAGCTRL_PWD_VALUE1 ((volatile uint32_t *)0xfe00301c)
+#define P_JTAGCTRL_PWD_VALUE2 ((volatile uint32_t *)0xfe003020)
+#define P_JTAGCTRL_PWD_VALUE3 ((volatile uint32_t *)0xfe003024)
+#define P_JTAGCTRL_PWD_STS ((volatile uint32_t *)0xfe003028)
+//========================================================================
+// APB0_MSR_CLK - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003400
+// -----------------------------------------------
+#define P_MSR_CLK_REG0 ((volatile uint32_t *)0xfe003400)
+#define P_MSR_CLK_REG1 ((volatile uint32_t *)0xfe003404)
+#define P_MSR_CLK_REG2 ((volatile uint32_t *)0xfe003408)
+#define P_MSR_CLK_REG3 ((volatile uint32_t *)0xfe00340c)
+#define P_MSR_CLK_REG4 ((volatile uint32_t *)0xfe003410)
+#define P_MSR_CLK_REG5 ((volatile uint32_t *)0xfe003414)
+#define P_MSR_CLK_DUTY ((volatile uint32_t *)0xfe003418)
+//========================================================================
+// APB0_SPICCA_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003800
+// -----------------------------------------------
+#define P_SPICC_A_RXDATA ((volatile uint32_t *)0xfe003800)
+#define P_SPICC_A_TXDATA ((volatile uint32_t *)0xfe003804)
+#define P_SPICC_A_CONREG ((volatile uint32_t *)0xfe003808)
+#define P_SPICC_A_INTREG ((volatile uint32_t *)0xfe00380c)
+#define P_SPICC_A_DMAREG ((volatile uint32_t *)0xfe003810)
+#define P_SPICC_A_STATREG ((volatile uint32_t *)0xfe003814)
+#define P_SPICC_A_PERIODREG ((volatile uint32_t *)0xfe003818)
+#define P_SPICC_A_TESTREG ((volatile uint32_t *)0xfe00381c)
+#define P_SPICC_A_DRADDR ((volatile uint32_t *)0xfe003820)
+#define P_SPICC_A_DWADDR ((volatile uint32_t *)0xfe003824)
+#define P_SPICC_A_LD_CNTL0 ((volatile uint32_t *)0xfe003828)
+#define P_SPICC_A_LD_CNTL1 ((volatile uint32_t *)0xfe00382c)
+#define P_SPICC_A_LD_RADDR ((volatile uint32_t *)0xfe003830)
+#define P_SPICC_A_LD_WADDR ((volatile uint32_t *)0xfe003834)
+#define P_SPICC_A_ENHANCE_CNTL ((volatile uint32_t *)0xfe003838)
+#define P_SPICC_A_ENHANCE_CNTL1 ((volatile uint32_t *)0xfe00383c)
+#define P_SPICC_A_ENHANCE_CNTL2 ((volatile uint32_t *)0xfe003840)
+//========================================================================
+// APB0_SPICCB_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003c00
+// -----------------------------------------------
+#define P_SPICC_B_RXDATA ((volatile uint32_t *)0xfe003c00)
+#define P_SPICC_B_TXDATA ((volatile uint32_t *)0xfe003c04)
+#define P_SPICC_B_CONREG ((volatile uint32_t *)0xfe003c08)
+#define P_SPICC_B_INTREG ((volatile uint32_t *)0xfe003c0c)
+#define P_SPICC_B_DMAREG ((volatile uint32_t *)0xfe003c10)
+#define P_SPICC_B_STATREG ((volatile uint32_t *)0xfe003c14)
+#define P_SPICC_B_PERIODREG ((volatile uint32_t *)0xfe003c18)
+#define P_SPICC_B_TESTREG ((volatile uint32_t *)0xfe003c1c)
+#define P_SPICC_B_DRADDR ((volatile uint32_t *)0xfe003c20)
+#define P_SPICC_B_DWADDR ((volatile uint32_t *)0xfe003c24)
+#define P_SPICC_B_LD_CNTL0 ((volatile uint32_t *)0xfe003c28)
+#define P_SPICC_B_LD_CNTL1 ((volatile uint32_t *)0xfe003c2c)
+#define P_SPICC_B_LD_RADDR ((volatile uint32_t *)0xfe003c30)
+#define P_SPICC_B_LD_WADDR ((volatile uint32_t *)0xfe003c34)
+#define P_SPICC_B_ENHANCE_CNTL ((volatile uint32_t *)0xfe003c38)
+#define P_SPICC_B_ENHANCE_CNTL1 ((volatile uint32_t *)0xfe003c3c)
+#define P_SPICC_B_ENHANCE_CNTL2 ((volatile uint32_t *)0xfe003c40)
+//========================================================================
+// USBCTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe004000
+// -----------------------------------------------
+#define P_USB_CTRL0 ((volatile uint32_t *)0xfe004000)
+#define P_USB_CTRL1 ((volatile uint32_t *)0xfe004004)
+#define P_USB_CTRL2 ((volatile uint32_t *)0xfe004008)
+#define P_USB_CTRL3 ((volatile uint32_t *)0xfe00400c)
+#define P_USB_CTRL4 ((volatile uint32_t *)0xfe004010)
+#define P_USB_CTRL5 ((volatile uint32_t *)0xfe004014)
+#define P_USB_CTRL6 ((volatile uint32_t *)0xfe004018)
+#define P_USB_CTRL7 ((volatile uint32_t *)0xfe00401c)
+#define P_USB_CTRL8 ((volatile uint32_t *)0xfe004020)
+#define P_USB_CTRL9 ((volatile uint32_t *)0xfe004024)
+#define P_USB_CTRL10 ((volatile uint32_t *)0xfe004028)
+#define P_USB_CTRL11 ((volatile uint32_t *)0xfe00402c)
+#define P_USB_CTRL12 ((volatile uint32_t *)0xfe004030)
+#define P_USB_CTRL13 ((volatile uint32_t *)0xfe004034)
+#define P_USB_CTRL14 ((volatile uint32_t *)0xfe004038)
+#define P_USB_CTRL15 ((volatile uint32_t *)0xfe00403c)
+#define P_USB_CTRL16 ((volatile uint32_t *)0xfe004040)
+#define P_USB_CTRL17 ((volatile uint32_t *)0xfe004044)
+#define P_USB_CTRL18 ((volatile uint32_t *)0xfe004048)
+#define P_USB_CTRL19 ((volatile uint32_t *)0xfe00404c)
+#define P_USB_CTRL20 ((volatile uint32_t *)0xfe004050)
+#define P_USB_CTRL21 ((volatile uint32_t *)0xfe004054)
+#define P_USB_CTRL22 ((volatile uint32_t *)0xfe004058)
+#define P_USB_CTRL23 ((volatile uint32_t *)0xfe00405c)
+#define P_USB_CTRL24 ((volatile uint32_t *)0xfe004060)
+#define P_USB_CTRL25 ((volatile uint32_t *)0xfe004064)
+#define P_USB_CTRL26 ((volatile uint32_t *)0xfe004068)
+#define P_USB_CTRL27 ((volatile uint32_t *)0xfe00406c)
+#define P_USB_CTRL28 ((volatile uint32_t *)0xfe004070)
+#define P_USB_CTRL29 ((volatile uint32_t *)0xfe004074)
+#define P_USB_CTRL30 ((volatile uint32_t *)0xfe004078)
+#define P_USB_CTRL31 ((volatile uint32_t *)0xfe00407c)
+//========================================================================
+// APB0_ACODEC_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe004800
+// -----------------------------------------------
+#define P_ACODEC_0 ((volatile uint32_t *)0xfe004800)
+#define P_ACODEC_1 ((volatile uint32_t *)0xfe004804)
+#define P_ACODEC_2 ((volatile uint32_t *)0xfe004808)
+#define P_ACODEC_3 ((volatile uint32_t *)0xfe00480c)
+#define P_ACODEC_4 ((volatile uint32_t *)0xfe004810)
+#define P_ACODEC_5 ((volatile uint32_t *)0xfe004814)
+#define P_ACODEC_6 ((volatile uint32_t *)0xfe004818)
+#define P_ACODEC_7 ((volatile uint32_t *)0xfe00481c)
+#define P_ACODEC_8 ((volatile uint32_t *)0xfe004820)
+#define P_ACODEC_9 ((volatile uint32_t *)0xfe004824)
+#define P_ACODEC_STS0 ((volatile uint32_t *)0xfe004840)
+//========================================================================
+// APB0_TEMP_SENSOR - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe004c00
+// -----------------------------------------------
+#define P_TS_CFG_REG1 ((volatile uint32_t *)0xfe004c04)
+#define P_TS_CFG_REG2 ((volatile uint32_t *)0xfe004c08)
+#define P_TS_CFG_REG3 ((volatile uint32_t *)0xfe004c0c)
+#define P_TS_CFG_REG4 ((volatile uint32_t *)0xfe004c10)
+#define P_TS_CFG_REG5 ((volatile uint32_t *)0xfe004c14)
+#define P_TS_CFG_REG6 ((volatile uint32_t *)0xfe004c18)
+#define P_TS_CFG_REG7 ((volatile uint32_t *)0xfe004c1c)
+#define P_TS_STAT0 ((volatile uint32_t *)0xfe004c40)
+#define P_TS_STAT1 ((volatile uint32_t *)0xfe004c44)
+#define P_TS_STAT2 ((volatile uint32_t *)0xfe004c48)
+#define P_TS_STAT3 ((volatile uint32_t *)0xfe004c4c)
+#define P_TS_STAT4 ((volatile uint32_t *)0xfe004c50)
+#define P_TS_STAT5 ((volatile uint32_t *)0xfe004c54)
+#define P_TS_STAT6 ((volatile uint32_t *)0xfe004c58)
+#define P_TS_STAT7 ((volatile uint32_t *)0xfe004c5c)
+#define P_TS_STAT8 ((volatile uint32_t *)0xfe004c60)
+#define P_TS_STAT9 ((volatile uint32_t *)0xfe004c64)
+//========================================================================
+// APB0_KL_EFUSE_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005000
+// -----------------------------------------------
+//
+// Reading file: ../crypto/crypto_reg.h
+//
+#define P_OTP_TEE_RDY ((volatile uint32_t *)0xfe005000)
+#define P_OTP_TEE_CHK ((volatile uint32_t *)0xfe005004)
+#define P_OTP_TEE_CFG ((volatile uint32_t *)0xfe005008)
+#define P_OTP_TEE_WR_DAT0 ((volatile uint32_t *)0xfe005010)
+#define P_OTP_TEE_WR_DAT1 ((volatile uint32_t *)0xfe005014)
+#define P_OTP_TEE_WR_DAT2 ((volatile uint32_t *)0xfe005018)
+#define P_OTP_TEE_WR_DAT3 ((volatile uint32_t *)0xfe00501c)
+#define P_OTP_TEE_RD_DAT0 ((volatile uint32_t *)0xfe005020)
+#define P_OTP_TEE_RD_DAT1 ((volatile uint32_t *)0xfe005024)
+#define P_OTP_TEE_RD_DAT2 ((volatile uint32_t *)0xfe005028)
+#define P_OTP_TEE_RD_DAT3 ((volatile uint32_t *)0xfe00502c)
+#define P_OTP_RMA_PW0 ((volatile uint32_t *)0xfe005030)
+#define P_OTP_RMA_PW1 ((volatile uint32_t *)0xfe005034)
+#define P_OTP_RMA_PW2 ((volatile uint32_t *)0xfe005038)
+#define P_OTP_RMA_PW3 ((volatile uint32_t *)0xfe00503c)
+#define P_OTP_REE_RDY ((volatile uint32_t *)0xfe005040)
+#define P_OTP_REE_CHK ((volatile uint32_t *)0xfe005044)
+#define P_OTP_REE_CFG ((volatile uint32_t *)0xfe005048)
+#define P_OTP_REE_RD_DAT0 ((volatile uint32_t *)0xfe005050)
+#define P_OTP_REE_RD_DAT1 ((volatile uint32_t *)0xfe005054)
+#define P_OTP_REE_RD_DAT2 ((volatile uint32_t *)0xfe005058)
+#define P_OTP_REE_RD_DAT3 ((volatile uint32_t *)0xfe00505c)
+#define P_OTP_LIC0 ((volatile uint32_t *)0xfe005060)
+#define P_OTP_LIC1 ((volatile uint32_t *)0xfe005064)
+#define P_OTP_LIC2 ((volatile uint32_t *)0xfe005068)
+#define P_OTP_LIC3 ((volatile uint32_t *)0xfe00506c)
+#define P_RNG_SEC_CONFIG_REG1 ((volatile uint32_t *)0xfe005104)
+#define P_RNG_SEC_CONFIG_REG2 ((volatile uint32_t *)0xfe005108)
+#define P_RNG_SEC_DATA ((volatile uint32_t *)0xfe005110)
+#define P_RNG_SEC_STS ((volatile uint32_t *)0xfe005114)
+#define P_RNG_USR_DATA ((volatile uint32_t *)0xfe005118)
+#define P_RNG_USR_STS ((volatile uint32_t *)0xfe00511c)
+#define P_KTE_SLOT0 ((volatile uint32_t *)0xfe005180)
+#define P_KTE_SLOT1 ((volatile uint32_t *)0xfe005184)
+#define P_KTE_SLOT2 ((volatile uint32_t *)0xfe005188)
+#define P_KTE_SLOT3 ((volatile uint32_t *)0xfe00518c)
+#define P_KTE_SLOT4 ((volatile uint32_t *)0xfe005190)
+#define P_KTE_SLOT5 ((volatile uint32_t *)0xfe005194)
+#define P_KTE_SLOT6 ((volatile uint32_t *)0xfe005198)
+#define P_KTE_SLOT7 ((volatile uint32_t *)0xfe00519c)
+#define P_MKL_TEE_RDY ((volatile uint32_t *)0xfe005200)
+#define P_MKL_TEE_CHK ((volatile uint32_t *)0xfe005204)
+#define P_MKL_TEE_CFG ((volatile uint32_t *)0xfe005208)
+#define P_MKL_TEE_EK ((volatile uint32_t *)0xfe005210)
+#define P_MKL_REE_RDY ((volatile uint32_t *)0xfe005280)
+#define P_MKL_REE_CHK ((volatile uint32_t *)0xfe005284)
+#define P_MKL_REE_CFG ((volatile uint32_t *)0xfe005288)
+#define P_MKL_REE_EK ((volatile uint32_t *)0xfe005290)
+//
+// Closing file: ../crypto/crypto_reg.h
+//
+//========================================================================
+// APB0_PWM_EF - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005400
+// -----------------------------------------------
+#define P_PWMEF_PWM_E ((volatile uint32_t *)0xfe005400)
+#define P_PWMEF_PWM_F ((volatile uint32_t *)0xfe005404)
+#define P_PWMEF_MISC_REG_EF ((volatile uint32_t *)0xfe005408)
+#define P_PWMEF_DELTA_SIGMA_EF ((volatile uint32_t *)0xfe00540c)
+#define P_PWMEF_TIME_EF ((volatile uint32_t *)0xfe005410)
+#define P_PWMEF_E2 ((volatile uint32_t *)0xfe005414)
+#define P_PWMEF_F2 ((volatile uint32_t *)0xfe005418)
+#define P_PWMEF_BLINK_EF ((volatile uint32_t *)0xfe00541c)
+#define P_PWMEF_LOCK_EF ((volatile uint32_t *)0xfe005420)
+//========================================================================
+// APB0_SYS_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005800
+// -----------------------------------------------
+#define P_SYSCTRL_METAL_REV0 ((volatile uint32_t *)0xfe005800)
+#define P_SYSCTRL_METAL_REV1 ((volatile uint32_t *)0xfe005804)
+//`define SYSCTRL_PROD_ENABLE 8'h0a
+#define P_SYSCTRL_CHIP_ID ((volatile uint32_t *)0xfe00582c)
+#define P_SYSCTRL_WRITEONCE1_REG0 ((volatile uint32_t *)0xfe005840)
+#define P_SYSCTRL_WRITEONCE1_STICKY_REG0 ((volatile uint32_t *)0xfe005844)
+#define P_SYSCTRL_WRITEONCE1_SEC_REG0 ((volatile uint32_t *)0xfe005848)
+#define P_SYSCTRL_WRITEONCE1_STICKY_SEC_REG0 ((volatile uint32_t *)0xfe00584c)
+#define P_SYSCTRL_WRITEONCE_REG0 ((volatile uint32_t *)0xfe005850)
+#define P_SYSCTRL_WRITEONCE_REG1 ((volatile uint32_t *)0xfe005854)
+#define P_SYSCTRL_WRITEONCE_SEC_REG0 ((volatile uint32_t *)0xfe005858)
+#define P_SYSCTRL_WRITEONCE_STICKY_REG0 ((volatile uint32_t *)0xfe00585c)
+#define P_SYSCTRL_WRITEONCE_STICKY_REG1 ((volatile uint32_t *)0xfe005860)
+#define P_SYSCTRL_WRITEONCE_STICKY_SEC_REG0 ((volatile uint32_t *)0xfe005864)
+#define P_SYSCTRL_TIMERA_CTRL ((volatile uint32_t *)0xfe0058c0)
+#define P_SYSCTRL_TIMERA ((volatile uint32_t *)0xfe0058c4)
+#define P_SYSCTRL_TIMERB_CTRL ((volatile uint32_t *)0xfe0058c8)
+#define P_SYSCTRL_TIMERB ((volatile uint32_t *)0xfe0058cc)
+#define P_SYSCTRL_TIMERC_CTRL ((volatile uint32_t *)0xfe0058d0)
+#define P_SYSCTRL_TIMERC ((volatile uint32_t *)0xfe0058d4)
+#define P_SYSCTRL_TIMERD_CTRL ((volatile uint32_t *)0xfe0058d8)
+#define P_SYSCTRL_TIMERD ((volatile uint32_t *)0xfe0058dc)
+#define P_SYSCTRL_SEC_TIMERA_CTRL ((volatile uint32_t *)0xfe0058e0)
+#define P_SYSCTRL_SEC_TIMERA ((volatile uint32_t *)0xfe0058e4)
+#define P_SYSCTRL_TIMERE_CTRL ((volatile uint32_t *)0xfe005900)
+#define P_SYSCTRL_TIMERE ((volatile uint32_t *)0xfe005904)
+#define P_SYSCTRL_TIMERE_HI ((volatile uint32_t *)0xfe005908)
+#define P_SYSCTRL_TIMERF_CTRL ((volatile uint32_t *)0xfe00590c)
+#define P_SYSCTRL_TIMERF ((volatile uint32_t *)0xfe005910)
+#define P_SYSCTRL_TIMERF_HI ((volatile uint32_t *)0xfe005914)
+#define P_SYSCTRL_SEC_TIMERE_CTRL ((volatile uint32_t *)0xfe005918)
+#define P_SYSCTRL_SEC_TIMERE ((volatile uint32_t *)0xfe00591c)
+#define P_SYSCTRL_SEC_TIMERE_HI ((volatile uint32_t *)0xfe005920)
+#define P_SYSCTRL_OSC_RING_CTRL0 ((volatile uint32_t *)0xfe005940)
+#define P_SYSCTRL_SEC_DDR_AXI_SEL ((volatile uint32_t *)0xfe005944)
+#define P_SYSCTRL_AM2AXI_CTRL0 ((volatile uint32_t *)0xfe005948)
+#define P_SYSCTRL_AM2AXI_STS ((volatile uint32_t *)0xfe00594c)
+#define P_SYSCTRL_POC ((volatile uint32_t *)0xfe005980)
+//`define SYSCTRL_PROD_PWD_VALUE0 8'h80
+//`define SYSCTRL_PROD_PWD_VALUE1 8'h81
+//`define SYSCTRL_PROD_PWD_VALUE2 8'h82
+//`define SYSCTRL_PROD_PWD_VALUE3 8'h83
+//`define SYSCTRL_PROD_STATUS 8'h84
+#define P_SYSCTRL_DEBUG_REG0 ((volatile uint32_t *)0xfe005a40)
+#define P_SYSCTRL_DEBUG_REG1 ((volatile uint32_t *)0xfe005a44)
+#define P_SYSCTRL_DEBUG_REG2 ((volatile uint32_t *)0xfe005a48)
+#define P_SYSCTRL_DEBUG_REG3 ((volatile uint32_t *)0xfe005a4c)
+#define P_SYSCTRL_DEBUG_REG4 ((volatile uint32_t *)0xfe005a50)
+#define P_SYSCTRL_DEBUG_REG5 ((volatile uint32_t *)0xfe005a54)
+#define P_SYSCTRL_DEBUG_REG6 ((volatile uint32_t *)0xfe005a58)
+#define P_SYSCTRL_DEBUG_REG7 ((volatile uint32_t *)0xfe005a5c)
+#define P_SYSCTRL_STATUS_REG0 ((volatile uint32_t *)0xfe005a80)
+#define P_SYSCTRL_STATUS_REG1 ((volatile uint32_t *)0xfe005a84)
+#define P_SYSCTRL_STATUS_REG2 ((volatile uint32_t *)0xfe005a88)
+#define P_SYSCTRL_STATUS_REG3 ((volatile uint32_t *)0xfe005a8c)
+#define P_SYSCTRL_STATUS_REG4 ((volatile uint32_t *)0xfe005a90)
+#define P_SYSCTRL_STATUS_REG5 ((volatile uint32_t *)0xfe005a94)
+#define P_SYSCTRL_STATUS_REG6 ((volatile uint32_t *)0xfe005a98)
+#define P_SYSCTRL_STATUS_REG7 ((volatile uint32_t *)0xfe005a9c)
+#define P_SYSCTRL_STICKY_REG0 ((volatile uint32_t *)0xfe005ac0)
+#define P_SYSCTRL_STICKY_REG1 ((volatile uint32_t *)0xfe005ac4)
+#define P_SYSCTRL_STICKY_REG2 ((volatile uint32_t *)0xfe005ac8)
+#define P_SYSCTRL_STICKY_REG3 ((volatile uint32_t *)0xfe005acc)
+#define P_SYSCTRL_STICKY_REG4 ((volatile uint32_t *)0xfe005ad0)
+#define P_SYSCTRL_STICKY_REG5 ((volatile uint32_t *)0xfe005ad4)
+#define P_SYSCTRL_STICKY_REG6 ((volatile uint32_t *)0xfe005ad8)
+#define P_SYSCTRL_STICKY_REG7 ((volatile uint32_t *)0xfe005adc)
+#define P_SYSCTRL_SEC_STATUS_REG0 ((volatile uint32_t *)0xfe005b00)
+#define P_SYSCTRL_SEC_STATUS_REG1 ((volatile uint32_t *)0xfe005b04)
+#define P_SYSCTRL_SEC_STATUS_REG2 ((volatile uint32_t *)0xfe005b08)
+#define P_SYSCTRL_SEC_STATUS_REG3 ((volatile uint32_t *)0xfe005b0c)
+#define P_SYSCTRL_SEC_STATUS_REG4 ((volatile uint32_t *)0xfe005b10)
+#define P_SYSCTRL_SEC_STATUS_REG5 ((volatile uint32_t *)0xfe005b14)
+#define P_SYSCTRL_SEC_STATUS_REG6 ((volatile uint32_t *)0xfe005b18)
+#define P_SYSCTRL_SEC_STATUS_REG7 ((volatile uint32_t *)0xfe005b1c)
+#define P_SYSCTRL_SEC_STATUS_REG8 ((volatile uint32_t *)0xfe005b20)
+#define P_SYSCTRL_SEC_STATUS_REG9 ((volatile uint32_t *)0xfe005b24)
+#define P_SYSCTRL_SEC_STATUS_REG10 ((volatile uint32_t *)0xfe005b28)
+#define P_SYSCTRL_SEC_STATUS_REG11 ((volatile uint32_t *)0xfe005b2c)
+#define P_SYSCTRL_SEC_STATUS_REG12 ((volatile uint32_t *)0xfe005b30)
+#define P_SYSCTRL_SEC_STATUS_REG13 ((volatile uint32_t *)0xfe005b34)
+#define P_SYSCTRL_SEC_STATUS_REG14 ((volatile uint32_t *)0xfe005b38)
+#define P_SYSCTRL_SEC_STATUS_REG15 ((volatile uint32_t *)0xfe005b3c)
+#define P_SYSCTRL_SEC_STATUS_REG16 ((volatile uint32_t *)0xfe005b40)
+#define P_SYSCTRL_SEC_STATUS_REG17 ((volatile uint32_t *)0xfe005b44)
+#define P_SYSCTRL_SEC_STATUS_REG18 ((volatile uint32_t *)0xfe005b48)
+#define P_SYSCTRL_SEC_STATUS_REG19 ((volatile uint32_t *)0xfe005b4c)
+#define P_SYSCTRL_SEC_STATUS_REG20 ((volatile uint32_t *)0xfe005b50)
+#define P_SYSCTRL_SEC_STATUS_REG21 ((volatile uint32_t *)0xfe005b54)
+#define P_SYSCTRL_SEC_STATUS_REG22 ((volatile uint32_t *)0xfe005b58)
+#define P_SYSCTRL_SEC_STATUS_REG23 ((volatile uint32_t *)0xfe005b5c)
+#define P_SYSCTRL_SEC_STICKY_REG0 ((volatile uint32_t *)0xfe005b80)
+#define P_SYSCTRL_SEC_STICKY_REG1 ((volatile uint32_t *)0xfe005b84)
+#define P_SYSCTRL_SEC_STICKY_REG2 ((volatile uint32_t *)0xfe005b88)
+#define P_SYSCTRL_SEC_STICKY_REG3 ((volatile uint32_t *)0xfe005b8c)
+#define P_SYSCTRL_SEC_STICKY_REG4 ((volatile uint32_t *)0xfe005b90)
+#define P_SYSCTRL_SEC_STICKY_REG5 ((volatile uint32_t *)0xfe005b94)
+#define P_SYSCTRL_SEC_STICKY_REG6 ((volatile uint32_t *)0xfe005b98)
+#define P_SYSCTRL_SEC_STICKY_REG7 ((volatile uint32_t *)0xfe005b9c)
+#define P_SYSCTRL_MSG_INDEX0_STICKY ((volatile uint32_t *)0xfe005bc0)
+#define P_SYSCTRL_MSG_INDEX1_STICKY ((volatile uint32_t *)0xfe005bc4)
+#define P_SYSCTRL_MSG_INDEX2_STICKY ((volatile uint32_t *)0xfe005bc8)
+#define P_SYSCTRL_MSG_INDEX3_STICKY ((volatile uint32_t *)0xfe005bcc)
+//========================================================================
+// APB0_I2C_M_B - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005c00
+// -----------------------------------------------
+#define P_I2C_M_B_CONTROL_REG ((volatile uint32_t *)0xfe005c00)
+#define P_I2C_M_B_SLAVE_ADDR ((volatile uint32_t *)0xfe005c04)
+#define P_I2C_M_B_TOKEN_LIST0 ((volatile uint32_t *)0xfe005c08)
+#define P_I2C_M_B_TOKEN_LIST1 ((volatile uint32_t *)0xfe005c0c)
+#define P_I2C_M_B_WDATA_REG0 ((volatile uint32_t *)0xfe005c10)
+#define P_I2C_M_B_WDATA_REG1 ((volatile uint32_t *)0xfe005c14)
+#define P_I2C_M_B_RDATA_REG0 ((volatile uint32_t *)0xfe005c18)
+#define P_I2C_M_B_RDATA_REG1 ((volatile uint32_t *)0xfe005c1c)
+#define P_I2C_M_B_TIMEOUT_TH ((volatile uint32_t *)0xfe005c20)
+//========================================================================
+// APB0_DMA - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006000
+// -----------------------------------------------
+//TODO
+//========================================================================
+// APB0_IRQ_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006400
+// -----------------------------------------------
+#define P_IRQCTRL_IRQOUT_MASK0 ((volatile uint32_t *)0xfe006400)
+#define P_IRQCTRL_IRQOUT_MASK1 ((volatile uint32_t *)0xfe006404)
+#define P_IRQCTRL_IRQOUT_MASK2 ((volatile uint32_t *)0xfe006408)
+#define P_IRQCTRL_IRQOUT_MASK3 ((volatile uint32_t *)0xfe00640c)
+#define P_IRQCTRL_IRQOUT_INV0 ((volatile uint32_t *)0xfe006440)
+#define P_IRQCTRL_IRQOUT_INV1 ((volatile uint32_t *)0xfe006444)
+#define P_IRQCTRL_IRQOUT_INV2 ((volatile uint32_t *)0xfe006448)
+#define P_IRQCTRL_IRQOUT_INV3 ((volatile uint32_t *)0xfe00644c)
+//`define APB0_IRQIN_MASK0_CLK_USB 8'h00
+//`define APB0_IRQIN_MASK0_CLK_CPU 8'h01
+//`define APB0_IRQIN_MASK0_CLK_SYS 8'h02
+//`define APB0_IRQIN_MASK1_CLK_SYS 8'h03
+//`define APB0_IRQIN_MASK0_CLK_DSPA 8'h04
+//`define APB0_IRQIN_MASK0_CLK_DSPB 8'h05
+//`define APB0_IRQIN_CLRLVL_CLK_USB 8'h10
+//`define APB0_IRQIN_CLRLVL_CLK_DSPA 8'h11
+//`define APB0_IRQIN_CLRLVL_CLK_DSPB 8'h12
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006800
+// -----------------------------------------------
+#define P_I2C_M_C_CONTROL_REG ((volatile uint32_t *)0xfe006800)
+#define P_I2C_M_C_SLAVE_ADDR ((volatile uint32_t *)0xfe006804)
+#define P_I2C_M_C_TOKEN_LIST0 ((volatile uint32_t *)0xfe006808)
+#define P_I2C_M_C_TOKEN_LIST1 ((volatile uint32_t *)0xfe00680c)
+#define P_I2C_M_C_WDATA_REG0 ((volatile uint32_t *)0xfe006810)
+#define P_I2C_M_C_WDATA_REG1 ((volatile uint32_t *)0xfe006814)
+#define P_I2C_M_C_RDATA_REG0 ((volatile uint32_t *)0xfe006818)
+#define P_I2C_M_C_RDATA_REG1 ((volatile uint32_t *)0xfe00681c)
+#define P_I2C_M_C_TIMEOUT_TH ((volatile uint32_t *)0xfe006820)
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006c00
+// -----------------------------------------------
+#define P_I2C_M_D_CONTROL_REG ((volatile uint32_t *)0xfe006c00)
+#define P_I2C_M_D_SLAVE_ADDR ((volatile uint32_t *)0xfe006c04)
+#define P_I2C_M_D_TOKEN_LIST0 ((volatile uint32_t *)0xfe006c08)
+#define P_I2C_M_D_TOKEN_LIST1 ((volatile uint32_t *)0xfe006c0c)
+#define P_I2C_M_D_WDATA_REG0 ((volatile uint32_t *)0xfe006c10)
+#define P_I2C_M_D_WDATA_REG1 ((volatile uint32_t *)0xfe006c14)
+#define P_I2C_M_D_RDATA_REG0 ((volatile uint32_t *)0xfe006c18)
+#define P_I2C_M_D_RDATA_REG1 ((volatile uint32_t *)0xfe006c1c)
+#define P_I2C_M_D_TIMEOUT_TH ((volatile uint32_t *)0xfe006c20)
+//========================================================================
+// APB0_UART_C - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007000
+// -----------------------------------------------
+#define P_UART_C_WFIFO ((volatile uint32_t *)0xfe007000)
+#define P_UART_C_RFIFO ((volatile uint32_t *)0xfe007004)
+#define P_UART_C_CONTROL ((volatile uint32_t *)0xfe007008)
+#define P_UART_C_STATUS ((volatile uint32_t *)0xfe00700c)
+#define P_UART_C_MISC ((volatile uint32_t *)0xfe007010)
+#define P_UART_C_REG5 ((volatile uint32_t *)0xfe007014)
+//========================================================================
+// APB0_PWR_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007800
+// -----------------------------------------------
+#define P_PWRCTRL_PWR_ACK0 ((volatile uint32_t *)0xfe007800)
+#define P_PWRCTRL_ISO_EN0 ((volatile uint32_t *)0xfe007804)
+#define P_PWRCTRL_PWR_OFF0 ((volatile uint32_t *)0xfe007808)
+#define P_PWRCTRL_SAVE_EN0 ((volatile uint32_t *)0xfe00780c)
+#define P_PWRCTRL_RESTORE_EN0 ((volatile uint32_t *)0xfe007810)
+#define P_PWRCTRL_MEM_PD0 ((volatile uint32_t *)0xfe007840)
+#define P_PWRCTRL_MEM_PD1 ((volatile uint32_t *)0xfe007844)
+#define P_PWRCTRL_MEM_PD2 ((volatile uint32_t *)0xfe007848)
+#define P_PWRCTRL_MEM_PD3 ((volatile uint32_t *)0xfe00784c)
+#define P_PWRCTRL_MEM_PD4 ((volatile uint32_t *)0xfe007850)
+#define P_PWRCTRL_R_ISO_EN0 ((volatile uint32_t *)0xfe007880)
+#define P_PWRCTRL_R_PWR_OFF0 ((volatile uint32_t *)0xfe007884)
+#define P_PWRCTRL_R_MEM_PD0 ((volatile uint32_t *)0xfe007888)
+#define P_PWRCTRL_R_MEM_PD1 ((volatile uint32_t *)0xfe00788c)
+#define P_PWRCTRL_R_MEM_PD2 ((volatile uint32_t *)0xfe007890)
+#define P_PWRCTRL_R_MEM_PD3 ((volatile uint32_t *)0xfe007894)
+#define P_PWRCTRL_R_MEM_PD4 ((volatile uint32_t *)0xfe007898)
+//`define PWRCTRL_MEM_PD_DSPA 8'h10
+//`define PWRCTRL_MEM_PD_DSPB 8'h11
+//`define PWRCTRL_MEM_PD_RAMA 8'h12
+//`define PWRCTRL_MEM_PD_RAMB 8'h13
+//`define PWRCTRL_MEM_PD_CPU 8'h14
+//`define PWRCTRL_MEM_PD_AUDIO 8'h20
+//`define PWRCTRL_MEM_PD_USBCTRL 8'h21
+//`define PWRCTRL_MEM_PD_SPICC 8'h22
+//`define PWRCTRL_MEM_PD_SPIFC 8'h23
+//`define PWRCTRL_MEM_PD_IR 8'h24
+//`define PWRCTRL_MEM_PD_SDIO 8'h25
+//`define PWRCTRL_MEM_PD_KLEFUSE 8'h26
+//`define PWRCTRL_MEM_PD_PSRAM 8'h27
+//`define PWRCTRL_MEM_PD_DDR 8'h28
+//`define PWRCTRL_MEM_PD_DMC 8'h29
+#define P_PWRCTRL_AUTO_OFF_CTRL ((volatile uint32_t *)0xfe0078c0)
+#define P_PWRCTRL_AUTO_OFF ((volatile uint32_t *)0xfe0078c4)
+#define P_PWRCTRL_AUTO_OFF_STS ((volatile uint32_t *)0xfe0078c8)
+#define P_PWRCTRL_TIMER_TH_01 ((volatile uint32_t *)0xfe0078cc)
+#define P_PWRCTRL_TIMER_TH_23 ((volatile uint32_t *)0xfe0078d0)
+#define P_PWRCTRL_TIMER_TH_45 ((volatile uint32_t *)0xfe0078d4)
+#define P_PWRCTRL_TIMER_TH_67 ((volatile uint32_t *)0xfe0078d8)
+#define P_PWRCTRL_MASK_PWR_ACK0 ((volatile uint32_t *)0xfe007900)
+#define P_PWRCTRL_MASK_RSTN_OFF0 ((volatile uint32_t *)0xfe007904)
+#define P_PWRCTRL_MASK_RSTN_ON0 ((volatile uint32_t *)0xfe007908)
+#define P_PWRCTRL_MASK_PWR_OFF0 ((volatile uint32_t *)0xfe00790c)
+#define P_PWRCTRL_MASK_PWR_ON0 ((volatile uint32_t *)0xfe007910)
+#define P_PWRCTRL_MASK_ISO_OFF0 ((volatile uint32_t *)0xfe007914)
+#define P_PWRCTRL_MASK_ISO_ON0 ((volatile uint32_t *)0xfe007918)
+#define P_PWRCTRL_MASK_MEM_OFF0 ((volatile uint32_t *)0xfe007940)
+#define P_PWRCTRL_MASK_MEM_OFF1 ((volatile uint32_t *)0xfe007944)
+#define P_PWRCTRL_MASK_MEM_OFF2 ((volatile uint32_t *)0xfe007948)
+#define P_PWRCTRL_MASK_MEM_OFF3 ((volatile uint32_t *)0xfe00794c)
+#define P_PWRCTRL_MASK_MEM_OFF4 ((volatile uint32_t *)0xfe007950)
+#define P_PWRCTRL_MASK_MEM_ON0 ((volatile uint32_t *)0xfe007960)
+#define P_PWRCTRL_MASK_MEM_ON1 ((volatile uint32_t *)0xfe007964)
+#define P_PWRCTRL_MASK_MEM_ON2 ((volatile uint32_t *)0xfe007968)
+#define P_PWRCTRL_MASK_MEM_ON3 ((volatile uint32_t *)0xfe00796c)
+#define P_PWRCTRL_MASK_MEM_ON4 ((volatile uint32_t *)0xfe007970)
+//========================================================================
+// APB0_ANA_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007c00
+// -----------------------------------------------
+#define P_ANACTRL_FIXPLL_CTRL0 ((volatile uint32_t *)0xfe007c80)
+#define P_ANACTRL_FIXPLL_CTRL1 ((volatile uint32_t *)0xfe007c84)
+#define P_ANACTRL_FIXPLL_CTRL2 ((volatile uint32_t *)0xfe007c88)
+#define P_ANACTRL_FIXPLL_CTRL3 ((volatile uint32_t *)0xfe007c8c)
+#define P_ANACTRL_FIXPLL_CTRL4 ((volatile uint32_t *)0xfe007c90)
+#define P_ANACTRL_FIXPLL_STS ((volatile uint32_t *)0xfe007c94)
+#define P_ANACTRL_SYSPLL_CTRL0 ((volatile uint32_t *)0xfe007d00)
+#define P_ANACTRL_SYSPLL_CTRL1 ((volatile uint32_t *)0xfe007d04)
+#define P_ANACTRL_SYSPLL_CTRL2 ((volatile uint32_t *)0xfe007d08)
+#define P_ANACTRL_SYSPLL_CTRL3 ((volatile uint32_t *)0xfe007d0c)
+#define P_ANACTRL_SYSPLL_CTRL4 ((volatile uint32_t *)0xfe007d10)
+#define P_ANACTRL_SYSPLL_STS ((volatile uint32_t *)0xfe007d14)
+#define P_ANACTRL_HIFIPLL_CTRL0 ((volatile uint32_t *)0xfe007d40)
+#define P_ANACTRL_HIFIPLL_CTRL1 ((volatile uint32_t *)0xfe007d44)
+#define P_ANACTRL_HIFIPLL_CTRL2 ((volatile uint32_t *)0xfe007d48)
+#define P_ANACTRL_HIFIPLL_CTRL3 ((volatile uint32_t *)0xfe007d4c)
+#define P_ANACTRL_HIFIPLL_CTRL4 ((volatile uint32_t *)0xfe007d50)
+#define P_ANACTRL_HIFIPLL_STS ((volatile uint32_t *)0xfe007d54)
+#define P_ANACTRL_AUDDDS_CTRL0 ((volatile uint32_t *)0xfe007d80)
+#define P_ANACTRL_AUDDDS_CTRL1 ((volatile uint32_t *)0xfe007d84)
+#define P_ANACTRL_AUDDDS_CTRL2 ((volatile uint32_t *)0xfe007d88)
+#define P_ANACTRL_AUDDDS_CTRL3 ((volatile uint32_t *)0xfe007d8c)
+#define P_ANACTRL_AUDDDS_CTRL4 ((volatile uint32_t *)0xfe007d90)
+#define P_ANACTRL_AUDDDS_STS ((volatile uint32_t *)0xfe007d94)
+#define P_ANACTRL_MISCTOP_CTRL0 ((volatile uint32_t *)0xfe007dc0)
+#define P_ANACTRL_POR_CNTL ((volatile uint32_t *)0xfe007e08)
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe020000
+// -----------------------------------------------
+#define P_RSA_BASE ((volatile uint32_t *)0xfe020000)
+//========================================================================
+// CPUCTRL_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd000000
+// -----------------------------------------------
+#define P_CPUCTRL_CTRL0 ((volatile uint32_t *)0xfd000000)
+#define P_CPUCTRL_CTRL1 ((volatile uint32_t *)0xfd000004)
+#define P_CPUCTRL_CTRL2 ((volatile uint32_t *)0xfd000008)
+#define P_CPUCTRL_CTRL3 ((volatile uint32_t *)0xfd00000c)
+#define P_CPUCTRL_CTRL4 ((volatile uint32_t *)0xfd000010)
+#define P_CPUCTRL_CTRL5 ((volatile uint32_t *)0xfd000014)
+#define P_CPUCTRL_CTRL6 ((volatile uint32_t *)0xfd000018)
+#define P_CPUCTRL_CTRL7 ((volatile uint32_t *)0xfd00001c)
+#define P_CPUCTRL_CTRL8 ((volatile uint32_t *)0xfd000020)
+#define P_CPUCTRL_CTRL9 ((volatile uint32_t *)0xfd000024)
+#define P_CPUCTRL_CTRL10 ((volatile uint32_t *)0xfd000028)
+#define P_CPUCTRL_CTRL11 ((volatile uint32_t *)0xfd00002c)
+#define P_CPUCTRL_CTRL12 ((volatile uint32_t *)0xfd000030)
+#define P_CPUCTRL_CTRL13 ((volatile uint32_t *)0xfd000034)
+#define P_CPUCTRL_CTRL14 ((volatile uint32_t *)0xfd000038)
+#define P_CPUCTRL_CTRL15 ((volatile uint32_t *)0xfd00003c)
+#define P_CPUCTRL_STS0 ((volatile uint32_t *)0xfd000040)
+#define P_CPUCTRL_STS1 ((volatile uint32_t *)0xfd000044)
+#define P_CPUCTRL_STS2 ((volatile uint32_t *)0xfd000048)
+#define P_CPUCTRL_STS3 ((volatile uint32_t *)0xfd00004c)
+#define P_CPUCTRL_STS4 ((volatile uint32_t *)0xfd000050)
+#define P_CPUCTRL_STS5 ((volatile uint32_t *)0xfd000054)
+#define P_CPUCTRL_STS6 ((volatile uint32_t *)0xfd000058)
+#define P_CPUCTRL_STS7 ((volatile uint32_t *)0xfd00005c)
+#define P_CPUCTRL_STS8 ((volatile uint32_t *)0xfd000060)
+#define P_CPUCTRL_STS9 ((volatile uint32_t *)0xfd000064)
+#define P_CPUCTRL_CLK_CTRL0 ((volatile uint32_t *)0xfd000080)
+#define P_CPUCTRL_CLK_CTRL1 ((volatile uint32_t *)0xfd000084)
+#define P_CPUCTRL_CLK_CTRL2 ((volatile uint32_t *)0xfd000088)
+#define P_CPUCTRL_CLK_CTRL3 ((volatile uint32_t *)0xfd00008c)
+#define P_CPUCTRL_CLK_CTRL4 ((volatile uint32_t *)0xfd000090)
+#define P_CPUCTRL_CLK_CTRL5 ((volatile uint32_t *)0xfd000094)
+#define P_CPUCTRL_CLK_CTRL6 ((volatile uint32_t *)0xfd000098)
+#define P_CPUCTRL_CLK_CTRL7 ((volatile uint32_t *)0xfd00009c)
+#define P_CPUCTRL_RESET_CTRL ((volatile uint32_t *)0xfd0000c0)
+#define P_CPUCTRL_ROM_DISABLE ((volatile uint32_t *)0xfd0000c4)
+//========================================================================
+// RAMA_SEC_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd000800
+// -----------------------------------------------
+#define P_SRAM_RANGE0_STA ((volatile uint32_t *)0xfd000800)
+#define P_SRAM_RANGE1_STA ((volatile uint32_t *)0xfd000804)
+#define P_SRAM_RANGE2_STA ((volatile uint32_t *)0xfd000808)
+#define P_SRAM_RANGE3_STA ((volatile uint32_t *)0xfd00080c)
+#define P_SRAM_RANGE4_STA ((volatile uint32_t *)0xfd000810)
+#define P_SRAM_RANGE5_STA ((volatile uint32_t *)0xfd000814)
+#define P_SRAM_RANGE6_STA ((volatile uint32_t *)0xfd000818)
+#define P_SRAM_RANGE0_EDA ((volatile uint32_t *)0xfd00081c)
+#define P_SRAM_RANGE1_EDA ((volatile uint32_t *)0xfd000820)
+#define P_SRAM_RANGE2_EDA ((volatile uint32_t *)0xfd000824)
+#define P_SRAM_RANGE3_EDA ((volatile uint32_t *)0xfd000828)
+#define P_SRAM_RANGE4_EDA ((volatile uint32_t *)0xfd00082c)
+#define P_SRAM_RANGE5_EDA ((volatile uint32_t *)0xfd000830)
+#define P_SRAM_RANGE6_EDA ((volatile uint32_t *)0xfd000834)
+#define P_SRAM_RANGE0_CTRL0 ((volatile uint32_t *)0xfd000838)
+#define P_SRAM_RANGE1_CTRL0 ((volatile uint32_t *)0xfd00083c)
+#define P_SRAM_RANGE2_CTRL0 ((volatile uint32_t *)0xfd000840)
+#define P_SRAM_RANGE3_CTRL0 ((volatile uint32_t *)0xfd000844)
+#define P_SRAM_RANGE4_CTRL0 ((volatile uint32_t *)0xfd000848)
+#define P_SRAM_RANGE5_CTRL0 ((volatile uint32_t *)0xfd00084c)
+#define P_SRAM_RANGE6_CTRL0 ((volatile uint32_t *)0xfd000850)
+#define P_SRAM_RANGE7_CTRL0 ((volatile uint32_t *)0xfd000854)
+#define P_SRAM_RANGE0_CTRL1 ((volatile uint32_t *)0xfd000858)
+#define P_SRAM_RANGE1_CTRL1 ((volatile uint32_t *)0xfd00085c)
+#define P_SRAM_RANGE2_CTRL1 ((volatile uint32_t *)0xfd000860)
+#define P_SRAM_RANGE3_CTRL1 ((volatile uint32_t *)0xfd000864)
+#define P_SRAM_RANGE4_CTRL1 ((volatile uint32_t *)0xfd000868)
+#define P_SRAM_RANGE5_CTRL1 ((volatile uint32_t *)0xfd00086c)
+#define P_SRAM_RANGE6_CTRL1 ((volatile uint32_t *)0xfd000870)
+#define P_SRAM_RANGE7_CTRL1 ((volatile uint32_t *)0xfd000874)
+#define P_SRAM_SEC_CTRL0 ((volatile uint32_t *)0xfd000878)
+#define P_SRAM_REG_LOCK ((volatile uint32_t *)0xfd00087c)
+//========================================================================
+// RAMB_SEC_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfd000c00
+// -----------------------------------------------
+#define P_SRAM_RANGE0_STA_B ((volatile uint32_t *)0xfd000c00)
+#define P_SRAM_RANGE1_STA_B ((volatile uint32_t *)0xfd000c04)
+#define P_SRAM_RANGE2_STA_B ((volatile uint32_t *)0xfd000c08)
+#define P_SRAM_RANGE3_STA_B ((volatile uint32_t *)0xfd000c0c)
+#define P_SRAM_RANGE4_STA_B ((volatile uint32_t *)0xfd000c10)
+#define P_SRAM_RANGE5_STA_B ((volatile uint32_t *)0xfd000c14)
+#define P_SRAM_RANGE6_STA_B ((volatile uint32_t *)0xfd000c18)
+#define P_SRAM_RANGE0_EDA_B ((volatile uint32_t *)0xfd000c1c)
+#define P_SRAM_RANGE1_EDA_B ((volatile uint32_t *)0xfd000c20)
+#define P_SRAM_RANGE2_EDA_B ((volatile uint32_t *)0xfd000c24)
+#define P_SRAM_RANGE3_EDA_B ((volatile uint32_t *)0xfd000c28)
+#define P_SRAM_RANGE4_EDA_B ((volatile uint32_t *)0xfd000c2c)
+#define P_SRAM_RANGE5_EDA_B ((volatile uint32_t *)0xfd000c30)
+#define P_SRAM_RANGE6_EDA_B ((volatile uint32_t *)0xfd000c34)
+#define P_SRAM_RANGE0_CTRL0_B ((volatile uint32_t *)0xfd000c38)
+#define P_SRAM_RANGE1_CTRL0_B ((volatile uint32_t *)0xfd000c3c)
+#define P_SRAM_RANGE2_CTRL0_B ((volatile uint32_t *)0xfd000c40)
+#define P_SRAM_RANGE3_CTRL0_B ((volatile uint32_t *)0xfd000c44)
+#define P_SRAM_RANGE4_CTRL0_B ((volatile uint32_t *)0xfd000c48)
+#define P_SRAM_RANGE5_CTRL0_B ((volatile uint32_t *)0xfd000c4c)
+#define P_SRAM_RANGE6_CTRL0_B ((volatile uint32_t *)0xfd000c50)
+#define P_SRAM_RANGE7_CTRL0_B ((volatile uint32_t *)0xfd000c54)
+#define P_SRAM_RANGE0_CTRL1_B ((volatile uint32_t *)0xfd000c58)
+#define P_SRAM_RANGE1_CTRL1_B ((volatile uint32_t *)0xfd000c5c)
+#define P_SRAM_RANGE2_CTRL1_B ((volatile uint32_t *)0xfd000c60)
+#define P_SRAM_RANGE3_CTRL1_B ((volatile uint32_t *)0xfd000c64)
+#define P_SRAM_RANGE4_CTRL1_B ((volatile uint32_t *)0xfd000c68)
+#define P_SRAM_RANGE5_CTRL1_B ((volatile uint32_t *)0xfd000c6c)
+#define P_SRAM_RANGE6_CTRL1_B ((volatile uint32_t *)0xfd000c70)
+#define P_SRAM_RANGE7_CTRL1_B ((volatile uint32_t *)0xfd000c74)
+#define P_SRAM_SEC_CTRL0_B ((volatile uint32_t *)0xfd000c78)
+#define P_SRAM_REG_LOCK_B ((volatile uint32_t *)0xfd000c7c)
+//
+// Reading file: REG_LIST_DSP_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//========================================================================
+// DSPA - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe030000
+// -----------------------------------------------
+#define P_DSP_CFG0 ((volatile uint32_t *)0xfe030000)
+#define P_DSP_CFG1 ((volatile uint32_t *)0xfe030004)
+#define P_DSP_CFG2 ((volatile uint32_t *)0xfe030008)
+#define P_DSP_IMPWIRE ((volatile uint32_t *)0xfe03000c)
+#define P_DSP_RESET_VEC ((volatile uint32_t *)0xfe030010)
+#define P_DSP_SEC_CFG0 ((volatile uint32_t *)0xfe030018)
+#define P_DSP_SEC_CFG1 ((volatile uint32_t *)0xfe03001c)
+#define P_DSP_IRQ_CTRL0 ((volatile uint32_t *)0xfe030040)
+#define P_DSP_IRQ_CTRL1 ((volatile uint32_t *)0xfe030044)
+#define P_DSP_IRQ_CTRL2 ((volatile uint32_t *)0xfe030048)
+#define P_DSP_IRQ_CTRL3 ((volatile uint32_t *)0xfe03004c)
+#define P_DSP_IRQ_CTRL4 ((volatile uint32_t *)0xfe030050)
+#define P_DSP_IRQ_CTRL5 ((volatile uint32_t *)0xfe030054)
+#define P_DSP_IRQ_CTRL6 ((volatile uint32_t *)0xfe030058)
+#define P_DSP_IRQ_CTRL7 ((volatile uint32_t *)0xfe03005c)
+#define P_DSP_IRQ_CTRL8 ((volatile uint32_t *)0xfe030060)
+#define P_DSP_IRQ_STS ((volatile uint32_t *)0xfe03007c)
+#define P_DSP_REMAP0 ((volatile uint32_t *)0xfe030080)
+#define P_DSP_REMAP1 ((volatile uint32_t *)0xfe030084)
+#define P_DSP_REMAP2 ((volatile uint32_t *)0xfe030088)
+#define P_DSP_STS0 ((volatile uint32_t *)0xfe030100)
+#define P_DSP_STS1 ((volatile uint32_t *)0xfe030104)
+#define P_DSP_STS2 ((volatile uint32_t *)0xfe030108)
+#define P_DSP_STS3 ((volatile uint32_t *)0xfe03010c)
+#define P_DSP_STS4 ((volatile uint32_t *)0xfe030110)
+#define P_DSP_STS5 ((volatile uint32_t *)0xfe030114)
+#define P_DSP_MAILBOX_SET_0 ((volatile uint32_t *)0xfe030140)
+#define P_DSP_MAILBOX_SET_1 ((volatile uint32_t *)0xfe030144)
+#define P_DSP_MAILBOX_SET_2 ((volatile uint32_t *)0xfe030148)
+#define P_DSP_MAILBOX_SET_3 ((volatile uint32_t *)0xfe03014c)
+#define P_DSP_MAILBOX_SET_4 ((volatile uint32_t *)0xfe030150)
+#define P_DSP_MAILBOX_SET_5 ((volatile uint32_t *)0xfe030154)
+#define P_DSP_MAILBOX_SET_6 ((volatile uint32_t *)0xfe030158)
+#define P_DSP_MAILBOX_SET_7 ((volatile uint32_t *)0xfe03015c)
+#define P_DSP_MAILBOX_SET_8 ((volatile uint32_t *)0xfe030160)
+#define P_DSP_MAILBOX_SET_9 ((volatile uint32_t *)0xfe030164)
+#define P_DSP_MAILBOX_SET_10 ((volatile uint32_t *)0xfe030168)
+#define P_DSP_MAILBOX_SET_11 ((volatile uint32_t *)0xfe03016c)
+#define P_DSP_MAILBOX_CLR_0 ((volatile uint32_t *)0xfe030180)
+#define P_DSP_MAILBOX_CLR_1 ((volatile uint32_t *)0xfe030184)
+#define P_DSP_MAILBOX_CLR_2 ((volatile uint32_t *)0xfe030188)
+#define P_DSP_MAILBOX_CLR_3 ((volatile uint32_t *)0xfe03018c)
+#define P_DSP_MAILBOX_CLR_4 ((volatile uint32_t *)0xfe030190)
+#define P_DSP_MAILBOX_CLR_5 ((volatile uint32_t *)0xfe030194)
+#define P_DSP_MAILBOX_CLR_6 ((volatile uint32_t *)0xfe030198)
+#define P_DSP_MAILBOX_CLR_7 ((volatile uint32_t *)0xfe03019c)
+#define P_DSP_MAILBOX_CLR_8 ((volatile uint32_t *)0xfe0301a0)
+#define P_DSP_MAILBOX_CLR_9 ((volatile uint32_t *)0xfe0301a4)
+#define P_DSP_MAILBOX_CLR_10 ((volatile uint32_t *)0xfe0301a8)
+#define P_DSP_MAILBOX_CLR_11 ((volatile uint32_t *)0xfe0301ac)
+#define P_DSP_MAILBOX_STAT_0 ((volatile uint32_t *)0xfe0301c0)
+#define P_DSP_MAILBOX_STAT_1 ((volatile uint32_t *)0xfe0301c4)
+#define P_DSP_MAILBOX_STAT_2 ((volatile uint32_t *)0xfe0301c8)
+#define P_DSP_MAILBOX_STAT_3 ((volatile uint32_t *)0xfe0301cc)
+#define P_DSP_MAILBOX_STAT_4 ((volatile uint32_t *)0xfe0301d0)
+#define P_DSP_MAILBOX_STAT_5 ((volatile uint32_t *)0xfe0301d4)
+#define P_DSP_MAILBOX_STAT_6 ((volatile uint32_t *)0xfe0301d8)
+#define P_DSP_MAILBOX_STAT_7 ((volatile uint32_t *)0xfe0301dc)
+#define P_DSP_MAILBOX_STAT_8 ((volatile uint32_t *)0xfe0301e0)
+#define P_DSP_MAILBOX_STAT_9 ((volatile uint32_t *)0xfe0301e4)
+#define P_DSP_MAILBOX_STAT_10 ((volatile uint32_t *)0xfe0301e8)
+#define P_DSP_MAILBOX_STAT_11 ((volatile uint32_t *)0xfe0301ec)
+#define P_DSP_QIF_CTRL ((volatile uint32_t *)0xfe030200)
+#define P_DSP_QIF_STS ((volatile uint32_t *)0xfe030204)
+#define P_DSP_WRFIFO_TOCPUA ((volatile uint32_t *)0xfe030208)
+#define P_DSP_WRFIFO_TOCPUB ((volatile uint32_t *)0xfe03020c)
+#define P_DSP_WRFIFO_TODSP ((volatile uint32_t *)0xfe030210)
+#define P_DSP_RDFIFO_FRCPUA ((volatile uint32_t *)0xfe030220)
+#define P_DSP_RDFIFO_FRCPUB ((volatile uint32_t *)0xfe030224)
+#define P_DSP_RDFIFO_FRDSP ((volatile uint32_t *)0xfe030228)
+//========================================================================
+// DSPB - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe040000
+// -----------------------------------------------
+#define P_DSPB_CFG0 ((volatile uint32_t *)0xfe040000)
+#define P_DSPB_CFG1 ((volatile uint32_t *)0xfe040004)
+#define P_DSPB_CFG2 ((volatile uint32_t *)0xfe040008)
+#define P_DSPB_IMPWIRE ((volatile uint32_t *)0xfe04000c)
+#define P_DSPB_RESET_VEC ((volatile uint32_t *)0xfe040010)
+#define P_DSPB_SEC_CFG0 ((volatile uint32_t *)0xfe040018)
+#define P_DSPB_SEC_CFG1 ((volatile uint32_t *)0xfe04001c)
+#define P_DSPB_IRQ_CTRL0 ((volatile uint32_t *)0xfe040040)
+#define P_DSPB_IRQ_CTRL1 ((volatile uint32_t *)0xfe040044)
+#define P_DSPB_IRQ_CTRL2 ((volatile uint32_t *)0xfe040048)
+#define P_DSPB_IRQ_CTRL3 ((volatile uint32_t *)0xfe04004c)
+#define P_DSPB_IRQ_CTRL4 ((volatile uint32_t *)0xfe040050)
+#define P_DSPB_IRQ_CTRL5 ((volatile uint32_t *)0xfe040054)
+#define P_DSPB_IRQ_CTRL6 ((volatile uint32_t *)0xfe040058)
+#define P_DSPB_IRQ_CTRL7 ((volatile uint32_t *)0xfe04005c)
+#define P_DSPB_IRQ_CTRL8 ((volatile uint32_t *)0xfe040060)
+#define P_DSPB_IRQ_STS ((volatile uint32_t *)0xfe04007c)
+#define P_DSPB_REMAP0 ((volatile uint32_t *)0xfe040080)
+#define P_DSPB_REMAP1 ((volatile uint32_t *)0xfe040084)
+#define P_DSPB_REMAP2 ((volatile uint32_t *)0xfe040088)
+#define P_DSPB_STS0 ((volatile uint32_t *)0xfe040100)
+#define P_DSPB_STS1 ((volatile uint32_t *)0xfe040104)
+#define P_DSPB_STS2 ((volatile uint32_t *)0xfe040108)
+#define P_DSPB_STS3 ((volatile uint32_t *)0xfe04010c)
+#define P_DSPB_STS4 ((volatile uint32_t *)0xfe040110)
+#define P_DSPB_STS5 ((volatile uint32_t *)0xfe040114)
+#define P_DSPB_MAILBOX_SET_0 ((volatile uint32_t *)0xfe040140)
+#define P_DSPB_MAILBOX_SET_1 ((volatile uint32_t *)0xfe040144)
+#define P_DSPB_MAILBOX_SET_2 ((volatile uint32_t *)0xfe040148)
+#define P_DSPB_MAILBOX_SET_3 ((volatile uint32_t *)0xfe04014c)
+#define P_DSPB_MAILBOX_SET_4 ((volatile uint32_t *)0xfe040150)
+#define P_DSPB_MAILBOX_SET_5 ((volatile uint32_t *)0xfe040154)
+#define P_DSPB_MAILBOX_SET_6 ((volatile uint32_t *)0xfe040158)
+#define P_DSPB_MAILBOX_SET_7 ((volatile uint32_t *)0xfe04015c)
+#define P_DSPB_MAILBOX_SET_8 ((volatile uint32_t *)0xfe040160)
+#define P_DSPB_MAILBOX_SET_9 ((volatile uint32_t *)0xfe040164)
+#define P_DSPB_MAILBOX_SET_10 ((volatile uint32_t *)0xfe040168)
+#define P_DSPB_MAILBOX_SET_11 ((volatile uint32_t *)0xfe04016c)
+#define P_DSPB_MAILBOX_CLR_0 ((volatile uint32_t *)0xfe040180)
+#define P_DSPB_MAILBOX_CLR_1 ((volatile uint32_t *)0xfe040184)
+#define P_DSPB_MAILBOX_CLR_2 ((volatile uint32_t *)0xfe040188)
+#define P_DSPB_MAILBOX_CLR_3 ((volatile uint32_t *)0xfe04018c)
+#define P_DSPB_MAILBOX_CLR_4 ((volatile uint32_t *)0xfe040190)
+#define P_DSPB_MAILBOX_CLR_5 ((volatile uint32_t *)0xfe040194)
+#define P_DSPB_MAILBOX_CLR_6 ((volatile uint32_t *)0xfe040198)
+#define P_DSPB_MAILBOX_CLR_7 ((volatile uint32_t *)0xfe04019c)
+#define P_DSPB_MAILBOX_CLR_8 ((volatile uint32_t *)0xfe0401a0)
+#define P_DSPB_MAILBOX_CLR_9 ((volatile uint32_t *)0xfe0401a4)
+#define P_DSPB_MAILBOX_CLR_10 ((volatile uint32_t *)0xfe0401a8)
+#define P_DSPB_MAILBOX_CLR_11 ((volatile uint32_t *)0xfe0401ac)
+#define P_DSPB_MAILBOX_STAT_0 ((volatile uint32_t *)0xfe0401c0)
+#define P_DSPB_MAILBOX_STAT_1 ((volatile uint32_t *)0xfe0401c4)
+#define P_DSPB_MAILBOX_STAT_2 ((volatile uint32_t *)0xfe0401c8)
+#define P_DSPB_MAILBOX_STAT_3 ((volatile uint32_t *)0xfe0401cc)
+#define P_DSPB_MAILBOX_STAT_4 ((volatile uint32_t *)0xfe0401d0)
+#define P_DSPB_MAILBOX_STAT_5 ((volatile uint32_t *)0xfe0401d4)
+#define P_DSPB_MAILBOX_STAT_6 ((volatile uint32_t *)0xfe0401d8)
+#define P_DSPB_MAILBOX_STAT_7 ((volatile uint32_t *)0xfe0401dc)
+#define P_DSPB_MAILBOX_STAT_8 ((volatile uint32_t *)0xfe0401e0)
+#define P_DSPB_MAILBOX_STAT_9 ((volatile uint32_t *)0xfe0401e4)
+#define P_DSPB_MAILBOX_STAT_10 ((volatile uint32_t *)0xfe0401e8)
+#define P_DSPB_MAILBOX_STAT_11 ((volatile uint32_t *)0xfe0401ec)
+#define P_DSPB_QIF_CTRL ((volatile uint32_t *)0xfe040200)
+#define P_DSPB_QIF_STS ((volatile uint32_t *)0xfe040204)
+#define P_DSPB_WRFIFO_TOCPUA ((volatile uint32_t *)0xfe040208)
+#define P_DSPB_WRFIFO_TOCPUB ((volatile uint32_t *)0xfe04020c)
+#define P_DSPB_WRFIFO_TODSP ((volatile uint32_t *)0xfe040210)
+#define P_DSPB_RDFIFO_FRCPUA ((volatile uint32_t *)0xfe040220)
+#define P_DSPB_RDFIFO_FRCPUB ((volatile uint32_t *)0xfe040224)
+#define P_DSPB_RDFIFO_FRDSP ((volatile uint32_t *)0xfe040228)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: REG_LIST_DSP_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: ./REG_LIST_RTL.h
+//
+
+#endif // P_REGISTER_H
+
diff --git a/arch/arm/include/asm/arch-c2/pinctrl_init.h b/arch/arm/include/asm/arch-c2/pinctrl_init.h
new file mode 100644
index 0000000..cfbc42a
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/pinctrl_init.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _MESON_PINCTRL_INIT_H_
+#define _MESON_PINCTRL_INIT_H_
+
+#define PIN_CONTROLLER_NUM 2
+extern int pinctrl_devices_active(int pinctrl_num);
+
+#endif /* _MESON_PINCTRL_INIT_H_ */
diff --git a/arch/arm/include/asm/arch-c2/pll.h b/arch/arm/include/asm/arch-c2/pll.h
new file mode 100644
index 0000000..f43c364
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/pll.h
@@ -0,0 +1,111 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __PLL_H
+#define __PLL_H
+
+#define PLL_TEST_SYS_TOTAL 2
+#define PLL_TEST_HDMI_TOTAL 3
+#define PLL_TEST_HIFI_TOTAL 2
+#define PLL_TEST_GP0_TOTAL 2
+
+typedef struct sys_pll_set_s {
+ unsigned int cpu_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+}sys_pll_set_t;
+
+typedef struct sys_pll_cfg_s {
+ sys_pll_set_t sys_pll[PLL_TEST_SYS_TOTAL];
+}sys_pll_cfg_t;
+
+typedef struct hifi_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+}hifi_pll_set_t;
+
+typedef struct hifi_pll_cfg_s {
+ hifi_pll_set_t hifi_pll[PLL_TEST_HIFI_TOTAL];
+}hifi_pll_cfg_t;
+
+typedef struct hifipll_rate_table_s {
+ unsigned int rate;
+ unsigned int m;
+ unsigned int n;
+ unsigned int od;
+}hifipll_rate_table_t;
+
+typedef struct gpll_rate_table_s {
+ unsigned int rate;
+ unsigned int m;
+ unsigned int n;
+ unsigned int od;
+}gpll_rate_table_t;
+
+typedef struct ddspll_rate_table_t {
+ unsigned int RATE;
+ unsigned int CTS;
+ unsigned int N;
+}ddspll_rate_table_t;
+
+typedef struct gp_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+}gp_pll_set_t;
+
+typedef struct gp0_pll_cfg_s {
+ gp_pll_set_t gp0_pll[PLL_TEST_GP0_TOTAL];
+}gp0_pll_cfg_t;
+
+typedef struct dds_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int misctop_cntl0;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+}dds_pll_set_t;
+
+typedef struct usbphy_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+}usbphy_pll_set_t;
+
+typedef struct ethphy_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+}ethphy_pll_set_t;
+
+enum pll_enum {
+ PLL_SYS = 0,
+ PLL_FIX,
+ PLL_DDR,
+ PLL_HIFI,
+ PLL_GP,
+ PLL_DDS,
+ PLL_USBPHY,
+ PLL_ETHPHY,
+ PLL_ENUM,
+};
+int pll_test(int argc, char * const argv[]);
+
+#endif /* __PLL_H */
diff --git a/arch/arm/include/asm/arch-c2/pwr_ctrl.h b/arch/arm/include/asm/arch-c2/pwr_ctrl.h
new file mode 100644
index 0000000..2a21dd7
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/pwr_ctrl.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#define PWR_ON 1
+#define PWR_OFF 0
+
+enum pm_e {
+ PM_CPU_PWR0,
+ PM_CPU_CORE0,
+ PM_CPU_CORE1,
+ PM_SPTOP = 5,
+ PM_DSP_A = 8,
+ PM_DSP_B,
+ PM_UART,
+ PM_DMC,
+ PM_I2C,
+ PM_SDEMMC_B,
+ PM_ACODEC,
+ PM_AUDIO,
+ PM_MKL_OTP,
+ PM_DMA,
+ PM_SDEMMC_A,
+ PM_SRAM_A,
+ PM_SRAM_B,
+ PM_IR,
+ PM_SPICC,
+ PM_SPIFC,
+ PM_USB,
+ PM_NIC,
+ PM_PDM,
+ PM_RSA,
+ PM_MIPI_ISP,
+ PM_HCODEC,
+ PM_WAVE,
+ PM_SDEMMC_C,
+ PM_SRAM_C,
+ PM_GDC,
+ PM_GE2D,
+ PM_NNA,
+ PM_ETH,
+ PM_GIC,
+ PM_DDR,
+ PM_SPICC_B
+};
+
+unsigned long pwr_ctrl_psci_smc(unsigned int power_domain, bool power_control);
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-c2/register.h b/arch/arm/include/asm/arch-c2/register.h
new file mode 100644
index 0000000..ec64c8f
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/register.h
@@ -0,0 +1,8310 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifdef REGISTER_H
+#else
+#define REGISTER_H
+
+
+#if 0
+#ifndef VERIFICATION
+ #define Wr64(addr, data) *(volatile uint64_t *)(addr)=(data)
+ #define Rd64(addr) *(volatile uint64_t *)(addr)
+ #define Wr(addr, data) *(volatile uint32_t *)(addr)=(data)
+ #define Rd(addr) *(volatile uint32_t *)(addr)
+ #define Wr_reg_bits(reg, val, start, len) \
+ Wr(reg, ((Rd(reg) & ~(((1L<<(len))-1)<<(start))) | ((uint32_t)(val) << (start))))
+#else
+ #include "dpi.h"
+#endif
+#endif
+
+//
+// Reading file: ./REG_LIST_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Reading file: REG_LIST_AUDIO_RTL.h
+//
+//========================================================================
+// AUDIO - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe050000
+// -----------------------------------------------
+#define EE_AUDIO_CLK_GATE_EN0 ((0x0000 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_GATE_EN1 ((0x0001 << 2) + 0xfe050000)
+#define EE_AUDIO_MCLK_A_CTRL ((0x0002 << 2) + 0xfe050000)
+#define EE_AUDIO_MCLK_B_CTRL ((0x0003 << 2) + 0xfe050000)
+#define EE_AUDIO_MCLK_C_CTRL ((0x0004 << 2) + 0xfe050000)
+#define EE_AUDIO_MCLK_D_CTRL ((0x0005 << 2) + 0xfe050000)
+#define EE_AUDIO_MCLK_E_CTRL ((0x0006 << 2) + 0xfe050000)
+#define EE_AUDIO_MCLK_F_CTRL ((0x0007 << 2) + 0xfe050000)
+#define EE_AUDIO_PAD_CTRL0 ((0x0008 << 2) + 0xfe050000)
+#define EE_AUDIO_PAD_CTRL1 ((0x0009 << 2) + 0xfe050000)
+#define EE_AUDIO_SW_RESET0 ((0x000a << 2) + 0xfe050000)
+#define EE_AUDIO_SW_RESET1 ((0x000b << 2) + 0xfe050000)
+#define EE_AUDIO_CLK81_CTRL ((0x000c << 2) + 0xfe050000)
+#define EE_AUDIO_CLK81_EN ((0x000d << 2) + 0xfe050000)
+#define EE_AUDIO_MST_A_SCLK_CTRL0 ((0x0010 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_A_SCLK_CTRL1 ((0x0011 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_B_SCLK_CTRL0 ((0x0012 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_B_SCLK_CTRL1 ((0x0013 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_C_SCLK_CTRL0 ((0x0014 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_C_SCLK_CTRL1 ((0x0015 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_D_SCLK_CTRL0 ((0x0016 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_D_SCLK_CTRL1 ((0x0017 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_E_SCLK_CTRL0 ((0x0018 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_E_SCLK_CTRL1 ((0x0019 << 2) + 0xfe050000)
+#define EE_AUDIO_MST_F_SCLK_CTRL0 ((0x001a << 2) + 0xfe050000)
+#define EE_AUDIO_MST_F_SCLK_CTRL1 ((0x001b << 2) + 0xfe050000)
+#define EE_AUDIO_MST_DLY_CTRL0 ((0x001c << 2) + 0xfe050000)
+#define EE_AUDIO_MST_DLY_CTRL1 ((0x001d << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMIN_A_CTRL ((0x0020 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMIN_B_CTRL ((0x0021 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMIN_C_CTRL ((0x0022 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMIN_LB_CTRL ((0x0023 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMOUT_A_CTRL ((0x0024 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMOUT_B_CTRL ((0x0025 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_TDMOUT_C_CTRL ((0x0026 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_SPDIFIN_CTRL ((0x0027 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_SPDIFOUT_CTRL ((0x0028 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_RESAMPLEA_CTRL ((0x0029 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_LOCKER_CTRL ((0x002a << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_PDMIN_CTRL0 ((0x002b << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_PDMIN_CTRL1 ((0x002c << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_SPDIFOUT_B_CTRL ((0x002d << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_RESAMPLEB_CTRL ((0x002e << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_SPDIFIN_LB_CTRL ((0x002f << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_EQDRC_CTRL0 ((0x0030 << 2) + 0xfe050000)
+#define EE_AUDIO_VAD_CLK_CTRL ((0x0031 << 2) + 0xfe050000)
+#define EE_AUDIO_EARCTX_CMDC_CLK_CTRL ((0x0032 << 2) + 0xfe050000)
+#define EE_AUDIO_EARCTX_DMAC_CLK_CTRL ((0x0033 << 2) + 0xfe050000)
+#define EE_AUDIO_EARCRX_CMDC_CLK_CTRL ((0x0034 << 2) + 0xfe050000)
+#define EE_AUDIO_EARCRX_DMAC_CLK_CTRL ((0x0035 << 2) + 0xfe050000)
+#define EE_AUDIO_CLK_LOCKERB_CTRL ((0x0036 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_CTRL0 ((0x0040 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_CTRL1 ((0x0041 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_START_ADDR ((0x0042 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_FINISH_ADDR ((0x0043 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_INT_ADDR ((0x0044 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_STATUS1 ((0x0045 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_STATUS2 ((0x0046 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_START_ADDRB ((0x0047 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_FINISH_ADDRB ((0x0048 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_INIT_ADDR ((0x0049 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_CTRL2 ((0x004a << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_CTRL0 ((0x0050 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_CTRL1 ((0x0051 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_START_ADDR ((0x0052 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_FINISH_ADDR ((0x0053 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_INT_ADDR ((0x0054 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_STATUS1 ((0x0055 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_STATUS2 ((0x0056 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_START_ADDRB ((0x0057 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_FINISH_ADDRB ((0x0058 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_INIT_ADDR ((0x0059 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_CTRL2 ((0x005a << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_CTRL0 ((0x0060 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_CTRL1 ((0x0061 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_START_ADDR ((0x0062 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_FINISH_ADDR ((0x0063 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_INT_ADDR ((0x0064 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_STATUS1 ((0x0065 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_STATUS2 ((0x0066 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_START_ADDRB ((0x0067 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_FINISH_ADDRB ((0x0068 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_INIT_ADDR ((0x0069 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_C_CTRL2 ((0x006a << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_CTRL0 ((0x0070 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_CTRL1 ((0x0071 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_START_ADDR ((0x0072 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_FINISH_ADDR ((0x0073 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_INT_ADDR ((0x0074 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_STATUS1 ((0x0075 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_STATUS2 ((0x0076 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_START_ADDRB ((0x0077 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_FINISH_ADDRB ((0x0078 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_INIT_ADDR ((0x0079 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_A_CTRL2 ((0x007a << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_CTRL0 ((0x0080 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_CTRL1 ((0x0081 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_START_ADDR ((0x0082 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_FINISH_ADDR ((0x0083 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_INT_ADDR ((0x0084 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_STATUS1 ((0x0085 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_STATUS2 ((0x0086 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_START_ADDRB ((0x0087 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_FINISH_ADDRB ((0x0088 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_INIT_ADDR ((0x0089 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_B_CTRL2 ((0x008a << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_CTRL0 ((0x0090 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_CTRL1 ((0x0091 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_START_ADDR ((0x0092 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_FINISH_ADDR ((0x0093 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_INT_ADDR ((0x0094 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_STATUS1 ((0x0095 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_STATUS2 ((0x0096 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_START_ADDRB ((0x0097 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_FINISH_ADDRB ((0x0098 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_INIT_ADDR ((0x0099 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_C_CTRL2 ((0x009a << 2) + 0xfe050000)
+#define EE_AUDIO_ARB_CTRL0 ((0x00a0 << 2) + 0xfe050000)
+#define EE_AUDIO_ARB_CTRL1 ((0x00a1 << 2) + 0xfe050000)
+#define EE_AUDIO_ARB_STS ((0x00a8 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_CTRL0 ((0x00b0 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_CTRL1 ((0x00b1 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_CTRL2 ((0x00b2 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_CTRL3 ((0x00b3 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_DAT_CH_ID0 ((0x00b4 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_DAT_CH_ID1 ((0x00b5 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_DAT_CH_ID2 ((0x00b6 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_DAT_CH_ID3 ((0x00b7 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_LB_CH_ID0 ((0x00b8 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_LB_CH_ID1 ((0x00b9 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_LB_CH_ID2 ((0x00ba << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_LB_CH_ID3 ((0x00bb << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_STS ((0x00bc << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_CHSYNC_CTRL_INSERT ((0x00bd << 2) + 0xfe050000)
+#define EE_AUDIO_LB_A_CHSYNC_CTRL_ORIG ((0x00be << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_CTRL ((0x00c0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_SWAP0 ((0x00c1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK0 ((0x00c2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK1 ((0x00c3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK2 ((0x00c4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK3 ((0x00c5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_STAT ((0x00c6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE_VAL ((0x00c7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE0 ((0x00c8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE1 ((0x00c9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE2 ((0x00ca << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE3 ((0x00cb << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_CTRL ((0x00d0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_SWAP0 ((0x00d1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK0 ((0x00d2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK1 ((0x00d3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK2 ((0x00d4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK3 ((0x00d5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_STAT ((0x00d6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE_VAL ((0x00d7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE0 ((0x00d8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE1 ((0x00d9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE2 ((0x00da << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE3 ((0x00db << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_CTRL ((0x00e0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_SWAP0 ((0x00e1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK0 ((0x00e2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK1 ((0x00e3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK2 ((0x00e4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK3 ((0x00e5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_STAT ((0x00e6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE_VAL ((0x00e7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE0 ((0x00e8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE1 ((0x00e9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE2 ((0x00ea << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE3 ((0x00eb << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_CTRL ((0x00f0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_SWAP0 ((0x00f1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK0 ((0x00f2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK1 ((0x00f3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK2 ((0x00f4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK3 ((0x00f5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_STAT ((0x00f6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE_VAL ((0x00f7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE0 ((0x00f8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE1 ((0x00f9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE2 ((0x00fa << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE3 ((0x00fb << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL0 ((0x0100 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL1 ((0x0101 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL2 ((0x0102 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL3 ((0x0103 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL4 ((0x0104 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL5 ((0x0105 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_CTRL6 ((0x0106 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_STAT0 ((0x0107 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_STAT1 ((0x0108 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_STAT2 ((0x0109 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_MUTE_VAL ((0x010a << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_CTRL0 ((0x0110 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_CTRL1 ((0x0111 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_CTRL2 ((0x0112 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_CTRL3 ((0x0113 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_COEF0 ((0x0114 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_COEF1 ((0x0115 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_COEF2 ((0x0116 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_COEF3 ((0x0117 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_COEF4 ((0x0118 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEA_STATUS1 ((0x0119 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_STAT ((0x0120 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_GAIN0 ((0x0121 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_GAIN1 ((0x0122 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CTRL0 ((0x0123 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CTRL1 ((0x0124 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_PREAMB ((0x0125 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_SWAP ((0x0126 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS0 ((0x0127 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS1 ((0x0128 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS2 ((0x0129 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS3 ((0x012a << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS4 ((0x012b << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS5 ((0x012c << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS6 ((0x012d << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS7 ((0x012e << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS8 ((0x012f << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTS9 ((0x0130 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTSA ((0x0131 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_CHSTSB ((0x0132 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_MUTE_VAL ((0x0133 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_CTRL0 ((0x0140 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_CTRL1 ((0x0141 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_SWAP0 ((0x0142 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK0 ((0x0143 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK1 ((0x0144 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK2 ((0x0145 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK3 ((0x0146 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_STAT ((0x0147 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_GAIN0 ((0x0148 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_GAIN1 ((0x0149 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE_VAL ((0x014a << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE0 ((0x014b << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE1 ((0x014c << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE2 ((0x014d << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE3 ((0x014e << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK_VAL ((0x014f << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_CTRL0 ((0x0150 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_CTRL1 ((0x0151 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_SWAP0 ((0x0152 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK0 ((0x0153 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK1 ((0x0154 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK2 ((0x0155 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK3 ((0x0156 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_STAT ((0x0157 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_GAIN0 ((0x0158 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_GAIN1 ((0x0159 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE_VAL ((0x015a << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE0 ((0x015b << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE1 ((0x015c << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE2 ((0x015d << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE3 ((0x015e << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK_VAL ((0x015f << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_CTRL0 ((0x0160 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_CTRL1 ((0x0161 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_SWAP0 ((0x0162 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK0 ((0x0163 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK1 ((0x0164 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK2 ((0x0165 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK3 ((0x0166 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_STAT ((0x0167 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_GAIN0 ((0x0168 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_GAIN1 ((0x0169 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE_VAL ((0x016a << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE0 ((0x016b << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE1 ((0x016c << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE2 ((0x016d << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE3 ((0x016e << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK_VAL ((0x016f << 2) + 0xfe050000)
+//`define EE_AUDIO_POW_DET_CTRL0 10'h180
+//`define EE_AUDIO_POW_DET_CTRL1 10'h181
+//`define EE_AUDIO_POW_DET_TH_HI 10'h182
+//`define EE_AUDIO_POW_DET_TH_LO 10'h183
+//`define EE_AUDIO_POW_DET_VALUE 10'h184
+#define EE_AUDIO_SECURITY_CTRL0 ((0x0190 << 2) + 0xfe050000)
+#define EE_AUDIO_SECURITY_CTRL1 ((0x0191 << 2) + 0xfe050000)
+#define EE_AUDIO_IRQ_FIFO_CNT ((0x0192 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_STAT ((0x01a0 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN0 ((0x01a1 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN1 ((0x01a2 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CTRL0 ((0x01a3 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CTRL1 ((0x01a4 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_PREAMB ((0x01a5 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_SWAP ((0x01a6 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS0 ((0x01a7 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS1 ((0x01a8 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS2 ((0x01a9 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS3 ((0x01aa << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS4 ((0x01ab << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS5 ((0x01ac << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS6 ((0x01ad << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS7 ((0x01ae << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS8 ((0x01af << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS9 ((0x01b0 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTSA ((0x01b1 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTSB ((0x01b2 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_MUTE_VAL ((0x01b3 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN2 ((0x01b4 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN3 ((0x01b5 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN_EN ((0x01b6 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN_CTRL ((0x01b7 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_CTRL0 ((0x01c0 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_CTRL1 ((0x01c1 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_START_ADDR ((0x01c2 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_FINISH_ADDR ((0x01c3 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_INT_ADDR ((0x01c4 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_STATUS1 ((0x01c5 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_STATUS2 ((0x01c6 << 2) + 0xfe050000)
+#define EE_AUDIO_TORAM_INIT_ADDR ((0x01c7 << 2) + 0xfe050000)
+#define EE_AUDIO_TOACODEC_CTRL0 ((0x01d0 << 2) + 0xfe050000)
+#define EE_AUDIO_TOHDMITX_CTRL0 ((0x01d1 << 2) + 0xfe050000)
+#define EE_AUDIO_TOVAD_CTRL0 ((0x01d2 << 2) + 0xfe050000)
+#define EE_AUDIO_FRATV_CTRL0 ((0x01d3 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_CTRL0 ((0x01e0 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_CTRL1 ((0x01e1 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_CTRL2 ((0x01e2 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_CTRL3 ((0x01e3 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_COEF0 ((0x01e4 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_COEF1 ((0x01e5 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_COEF2 ((0x01e6 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_COEF3 ((0x01e7 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_COEF4 ((0x01e8 << 2) + 0xfe050000)
+#define EE_AUDIO_RESAMPLEB_STATUS1 ((0x01e9 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_LB_CTRL0 ((0x01f0 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_LB_CTRL1 ((0x01f1 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_LB_CTRL6 ((0x01f6 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_LB_STAT0 ((0x01f7 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_LB_STAT1 ((0x01f8 << 2) + 0xfe050000)
+#define EE_AUDIO_SPDIFIN_LB_MUTE_VAL ((0x01fa << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_CTRL0 ((0x0200 << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_CTRL1 ((0x0201 << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_CTRL2 ((0x0202 << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_CTRL3 ((0x0203 << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_CTRL4 ((0x0204 << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_CTRL5 ((0x0205 << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_STAT0 ((0x020a << 2) + 0xfe050000)
+#define EE_AUDIO_FRHDMIRX_STAT1 ((0x020b << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_CTRL0 ((0x0210 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_CTRL1 ((0x0211 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_START_ADDR ((0x0212 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_FINISH_ADDR ((0x0213 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_INT_ADDR ((0x0214 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_STATUS1 ((0x0215 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_STATUS2 ((0x0216 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_START_ADDRB ((0x0217 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_FINISH_ADDRB ((0x0218 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_INIT_ADDR ((0x0219 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_D_CTRL2 ((0x021a << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_CTRL0 ((0x0220 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_CTRL1 ((0x0221 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_START_ADDR ((0x0222 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_FINISH_ADDR ((0x0223 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_INT_ADDR ((0x0224 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_STATUS1 ((0x0225 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_STATUS2 ((0x0226 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_START_ADDRB ((0x0227 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_FINISH_ADDRB ((0x0228 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_INIT_ADDR ((0x0229 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_D_CTRL2 ((0x022a << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_CTRL0 ((0x0230 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_CTRL1 ((0x0231 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_CTRL2 ((0x0232 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_CTRL3 ((0x0233 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_DAT_CH_ID0 ((0x0234 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_DAT_CH_ID1 ((0x0235 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_DAT_CH_ID2 ((0x0236 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_DAT_CH_ID3 ((0x0237 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_LB_CH_ID0 ((0x0238 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_LB_CH_ID1 ((0x0239 << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_LB_CH_ID2 ((0x023a << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_LB_CH_ID3 ((0x023b << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_STS ((0x023c << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_CHSYNC_CTRL_INSERT ((0x023d << 2) + 0xfe050000)
+#define EE_AUDIO_LB_B_CHSYNC_CTRL_ORIG ((0x023e << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_CTRL0 ((0x0240 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_CTRL1 ((0x0241 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_START_ADDR ((0x0242 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_FINISH_ADDR ((0x0243 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_INT_ADDR ((0x0244 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_STATUS1 ((0x0245 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_STATUS2 ((0x0246 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_START_ADDRB ((0x0247 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_FINISH_ADDRB ((0x0248 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_INIT_ADDR ((0x0249 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_E_CTRL2 ((0x024a << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_CTRL0 ((0x0250 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_CTRL1 ((0x0251 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_START_ADDR ((0x0252 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_FINISH_ADDR ((0x0253 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_INT_ADDR ((0x0254 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_STATUS1 ((0x0255 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_STATUS2 ((0x0256 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_START_ADDRB ((0x0257 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_FINISH_ADDRB ((0x0258 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_INIT_ADDR ((0x0259 << 2) + 0xfe050000)
+#define EE_AUDIO_FRDDR_E_CTRL2 ((0x025a << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_SWAP1 ((0x0260 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK4 ((0x0261 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK5 ((0x0262 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK6 ((0x0263 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MASK7 ((0x0264 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE4 ((0x0265 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE5 ((0x0266 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE6 ((0x0267 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_A_MUTE7 ((0x0268 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_SWAP1 ((0x0270 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK4 ((0x0271 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK5 ((0x0272 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK6 ((0x0273 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MASK7 ((0x0274 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE4 ((0x0275 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE5 ((0x0276 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE6 ((0x0277 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_B_MUTE7 ((0x0278 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_SWAP1 ((0x0280 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK4 ((0x0281 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK5 ((0x0282 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK6 ((0x0283 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MASK7 ((0x0284 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE4 ((0x0285 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE5 ((0x0286 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE6 ((0x0287 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_C_MUTE7 ((0x0288 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_SWAP1 ((0x0290 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK4 ((0x0291 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK5 ((0x0292 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK6 ((0x0293 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MASK7 ((0x0294 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE4 ((0x0295 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE5 ((0x0296 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE6 ((0x0297 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMIN_LB_MUTE7 ((0x0298 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_CTRL2 ((0x02a0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_SWAP1 ((0x02a1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_GAIN2 ((0x02a2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_GAIN3 ((0x02a3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK4 ((0x02a4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK5 ((0x02a5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK6 ((0x02a6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MASK7 ((0x02a7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE4 ((0x02a8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE5 ((0x02a9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE6 ((0x02aa << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_MUTE7 ((0x02ab << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_GAIN_EN ((0x02ac << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_A_GAIN_CTRL ((0x02ad << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_CTRL2 ((0x02b0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_SWAP1 ((0x02b1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_GAIN2 ((0x02b2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_GAIN3 ((0x02b3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK4 ((0x02b4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK5 ((0x02b5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK6 ((0x02b6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MASK7 ((0x02b7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE4 ((0x02b8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE5 ((0x02b9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE6 ((0x02ba << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_MUTE7 ((0x02bb << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_GAIN_EN ((0x02bc << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_B_GAIN_CTRL ((0x02bd << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_CTRL2 ((0x02c0 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_SWAP1 ((0x02c1 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_GAIN2 ((0x02c2 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_GAIN3 ((0x02c3 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK4 ((0x02c4 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK5 ((0x02c5 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK6 ((0x02c6 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MASK7 ((0x02c7 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE4 ((0x02c8 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE5 ((0x02c9 << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE6 ((0x02ca << 2) + 0xfe050000)
+#define EE_AUDIO_TDMOUT_C_MUTE7 ((0x02cb << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID0 ((0x0300 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID1 ((0x0301 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID2 ((0x0302 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID3 ((0x0303 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID4 ((0x0304 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID5 ((0x0305 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID6 ((0x0306 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID7 ((0x0307 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_A_CHSYNC_CTRL ((0x030f << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID0 ((0x0310 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID1 ((0x0311 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID2 ((0x0312 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID3 ((0x0313 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID4 ((0x0314 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID5 ((0x0315 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID6 ((0x0316 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID7 ((0x0317 << 2) + 0xfe050000)
+#define EE_AUDIO_TODDR_B_CHSYNC_CTRL ((0x031f << 2) + 0xfe050000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID0 ((0x0350 << 2) + 0xfe050000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID1 ((0x0351 << 2) + 0xfe050000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID2 ((0x0352 << 2) + 0xfe050000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID3 ((0x0353 << 2) + 0xfe050000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID4 ((0x0354 << 2) + 0xfe050000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID5 ((0x0355 << 2) + 0xfe050000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID6 ((0x0356 << 2) + 0xfe050000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID7 ((0x0357 << 2) + 0xfe050000)
+#define EE_AUDIO_RSAMP_CHSYNC_MASK ((0x035e << 2) + 0xfe050000)
+#define EE_AUDIO_RSAMP_A_CHSYNC_CTRL ((0x035f << 2) + 0xfe050000)
+#define EE_AUDIO_EXCEPTION_IRQ_STS0 ((0x0380 << 2) + 0xfe050000)
+#define EE_AUDIO_EXCEPTION_IRQ_STS1 ((0x0381 << 2) + 0xfe050000)
+#define EE_AUDIO_EXCEPTION_IRQ_MASK0 ((0x0382 << 2) + 0xfe050000)
+#define EE_AUDIO_EXCEPTION_IRQ_MASK1 ((0x0383 << 2) + 0xfe050000)
+#define EE_AUDIO_EXCEPTION_IRQ_MODE0 ((0x0384 << 2) + 0xfe050000)
+#define EE_AUDIO_EXCEPTION_IRQ_MODE1 ((0x0385 << 2) + 0xfe050000)
+#define EE_AUDIO_EXCEPTION_IRQ_CLR0 ((0x0386 << 2) + 0xfe050000)
+#define EE_AUDIO_EXCEPTION_IRQ_CLR1 ((0x0387 << 2) + 0xfe050000)
+#define EE_AUDIO_EXCEPTION_IRQ_INV0 ((0x0388 << 2) + 0xfe050000)
+#define EE_AUDIO_EXCEPTION_IRQ_INV1 ((0x0389 << 2) + 0xfe050000)
+//========================================================================
+// PDM - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051000
+// -----------------------------------------------
+#define PDM_CTRL ((0x0000 << 2) + 0xfe051000)
+ //bit 31: PDM enable.
+ //bit 30: invert the PDM_DCLK.
+ //bit 29: output mode: 1: 24bits. 0: 32 bits.
+ //bit 28: bypass mode. 1: bypass all filter. directly output the PDM input to DDR. 0: normal mode.
+ //bit 27~9: not used.
+ //bit 16:. PDM Asynchronous FIFO soft reset. write 1 to soft reset AFIFO.
+ //bit 15:8 PDM channel reset. 0: to reset each PDM channel. 1: normal mode.
+ //bit 7:0. PDM channel enable. each bit for one channel.
+#define PDM_HCIC_CTRL1 ((0x0001 << 2) + 0xfe051000)
+ //bit 31 hcic filter enable. 1 use sinc filter. 0 bypass input to output.
+ //bit 29:24. hcic final gain shift parameter.
+ //bit 23:16 hcic final gain multiplier.
+ //bit 8:4 hcic down sample rate.
+ //bit 3:0 hcic stage number. must be between 3 to 9.
+#define PDM_HCIC_CTRL2 ((0x0002 << 2) + 0xfe051000)
+ //Not used.
+#define PDM_F1_CTRL ((0x0003 << 2) + 0xfe051000)
+ //bit 31 . filter 1 enable.
+ //bit 16:15. f1 round mode. 2'b00 : sign bit at bit 49. 28bits output [49:22] round at bit 21. 32bits output [49:18]. 24bits output [49:26]
+ // 2'b01 : sign bit at bit 50. 28bits output [50:23] round at bit 22. 32bits output [49:18]. 24bits output [49:26]
+ // 2'b10 : sign bit at bit 51. 28bits output [51:24] round at bit 23 32bits output [49:18]. 24bits output [49:26].
+ //bit 15:12. filter 1 down sample rate.
+ //bit 8:0. filter 1 stage number.
+#define PDM_F2_CTRL ((0x0004 << 2) + 0xfe051000)
+ //bit 31 . filter 2 enable.
+ //bit 16:15. f2 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23.
+ //bit 15:12. filter 2 down sample rate.
+ //bit 8:0. filter 2 stage number.
+#define PDM_F3_CTRL ((0x0005 << 2) + 0xfe051000)
+ //bit 31 . filter 3 enable.
+ //bit 16:15. f3 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23.
+ //bit 15:12. filter 3 down sample rate.
+ //bit 8:0. filter 3 stage number.
+#define PDM_HPF_CTRL ((0x0006 << 2) + 0xfe051000)
+ //bit 31 High pass filter enable.
+ //bit 20:16 high pass filter shift steps. 6~19 steps.
+ //bit 15:0 high pass filter output factor.
+#define PDM_CHAN_CTRL ((0x0007 << 2) + 0xfe051000)
+ //bit 31:24. chan3 data sample pointer vs edge of the PDM_DCLK.
+ //bit 23:16 chan2 data sample pointer vs edge of the PDM_DCLK.
+ //bit 15:8. chan1 data sample pointer vs edge of the PDM_DCLK.
+ //bit 7:0 chan0 data sample pointer vs edge of the PDM_DCLK.
+#define PDM_CHAN_CTRL1 ((0x0008 << 2) + 0xfe051000)
+ //bit 31:24. chan7 data sample pointer vs edge of the PDM_DCLK.
+ //bit 23:16 chan6 data sample pointer vs edge of the PDM_DCLK.
+ //bit 15:8. chan5 data sample pointer vs edge of the PDM_DCLK.
+ //bit 7:0 chan4 data sample pointer vs edge of the PDM_DCLK.
+#define PDM_COEFF_ADDR ((0x0009 << 2) + 0xfe051000)
+ // address of the write/read of coeff data.
+#define PDM_COEFF_DATA ((0x000a << 2) + 0xfe051000)
+ //write/read data to coeff memory.
+#define PDM_CLKG_CTRL ((0x000b << 2) + 0xfe051000)
+ // auto clock gating control. 1: disable the clock gating function. the clock will awlays enabled. 0 : use RTL auto clock gating.
+ //31:7 not used.
+ //bit 6 filt_ctrl module auto clock gating control.
+ //bit 5 sinc fifo module auto clock gating control.
+ //bit 4 filter module auto clock gating control.
+ //bit 3 apb module auto clock gating control.
+ //bit 2 coeff memory module auto clock gating control.
+ //bit 1 each channel module auto clock gating control.
+ //bit 0 cts_pdm_clk auto clock gating control.
+#define PDM_STS ((0x000c << 2) + 0xfe051000)
+//bit 1 HPF filter output overflow. means the PCLK is too slow.
+//bit 0 HCIC filter output overflow. means the CTS_PDM_CLK is too slow. can't finished the filter function.
+#define PDM_MUTE_VALUE ((0x000d << 2) + 0xfe051000)
+#define PDM_MASK_NUM ((0x000e << 2) + 0xfe051000)
+//========================================================================
+// EQ DRC - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe052000
+// -----------------------------------------------
+#define AED_COEF_RAM_CNTL ((0x0000 << 2) + 0xfe052000)
+#define AED_COEF_RAM_DATA ((0x0001 << 2) + 0xfe052000)
+#define AED_EQ_EN ((0x0002 << 2) + 0xfe052000)
+#define AED_EQ_TAP_CNTL ((0x0003 << 2) + 0xfe052000)
+#define AED_EQ_VOLUME ((0x0004 << 2) + 0xfe052000)
+#define AED_EQ_VOLUME_SLEW_CNT ((0x0005 << 2) + 0xfe052000)
+#define AED_MUTE ((0x0006 << 2) + 0xfe052000)
+#define AED_DRC_CNTL ((0x0007 << 2) + 0xfe052000)
+#define AED_DRC_RMS_COEF0 ((0x0008 << 2) + 0xfe052000)
+#define AED_DRC_RMS_COEF1 ((0x0009 << 2) + 0xfe052000)
+#define AED_DRC_THD0 ((0x000a << 2) + 0xfe052000)
+#define AED_DRC_THD1 ((0x000b << 2) + 0xfe052000)
+#define AED_DRC_THD2 ((0x000c << 2) + 0xfe052000)
+#define AED_DRC_THD3 ((0x000d << 2) + 0xfe052000)
+#define AED_DRC_THD4 ((0x000e << 2) + 0xfe052000)
+#define AED_DRC_K0 ((0x000f << 2) + 0xfe052000)
+#define AED_DRC_K1 ((0x0010 << 2) + 0xfe052000)
+#define AED_DRC_K2 ((0x0011 << 2) + 0xfe052000)
+#define AED_DRC_K3 ((0x0012 << 2) + 0xfe052000)
+#define AED_DRC_K4 ((0x0013 << 2) + 0xfe052000)
+#define AED_DRC_K5 ((0x0014 << 2) + 0xfe052000)
+#define AED_DRC_THD_OUT0 ((0x0015 << 2) + 0xfe052000)
+#define AED_DRC_THD_OUT1 ((0x0016 << 2) + 0xfe052000)
+#define AED_DRC_THD_OUT2 ((0x0017 << 2) + 0xfe052000)
+#define AED_DRC_THD_OUT3 ((0x0018 << 2) + 0xfe052000)
+#define AED_DRC_OFFSET ((0x0019 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF00 ((0x001a << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF01 ((0x001b << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF10 ((0x001c << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF11 ((0x001d << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF20 ((0x001e << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF21 ((0x001f << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF30 ((0x0020 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF31 ((0x0021 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF40 ((0x0022 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF41 ((0x0023 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF50 ((0x0024 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF51 ((0x0025 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF00 ((0x0026 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF01 ((0x0027 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF10 ((0x0028 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF11 ((0x0029 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF20 ((0x002a << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF21 ((0x002b << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF30 ((0x002c << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF31 ((0x002d << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF40 ((0x002e << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF41 ((0x002f << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF50 ((0x0030 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF51 ((0x0031 << 2) + 0xfe052000)
+#define AED_DRC_LOOPBACK_CNTL ((0x0032 << 2) + 0xfe052000)
+#define AED_MDRC_CNTL ((0x0033 << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF00 ((0x0034 << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF01 ((0x0035 << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF00 ((0x0036 << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF01 ((0x0037 << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF00 ((0x0038 << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF01 ((0x0039 << 2) + 0xfe052000)
+#define AED_MDRC_THD0 ((0x003a << 2) + 0xfe052000)
+#define AED_MDRC_K0 ((0x003b << 2) + 0xfe052000)
+#define AED_MDRC_LOW_GAIN ((0x003c << 2) + 0xfe052000)
+#define AED_MDRC_OFFSET0 ((0x003d << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF10 ((0x003e << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF11 ((0x003f << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF10 ((0x0040 << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF11 ((0x0041 << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF10 ((0x0042 << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF11 ((0x0043 << 2) + 0xfe052000)
+#define AED_MDRC_THD1 ((0x0044 << 2) + 0xfe052000)
+#define AED_MDRC_K1 ((0x0045 << 2) + 0xfe052000)
+#define AED_MDRC_OFFSET1 ((0x0046 << 2) + 0xfe052000)
+#define AED_MDRC_MID_GAIN ((0x0047 << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF20 ((0x0048 << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF21 ((0x0049 << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF20 ((0x004a << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF21 ((0x004b << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF20 ((0x004c << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF21 ((0x004d << 2) + 0xfe052000)
+#define AED_MDRC_THD2 ((0x004e << 2) + 0xfe052000)
+#define AED_MDRC_K2 ((0x004f << 2) + 0xfe052000)
+#define AED_MDRC_OFFSET2 ((0x0050 << 2) + 0xfe052000)
+#define AED_MDRC_HIGH_GAIN ((0x0051 << 2) + 0xfe052000)
+#define AED_ED_CNTL ((0x0052 << 2) + 0xfe052000)
+#define AED_DC_EN ((0x0053 << 2) + 0xfe052000)
+#define AED_ND_LOW_THD ((0x0054 << 2) + 0xfe052000)
+#define AED_ND_HIGH_THD ((0x0055 << 2) + 0xfe052000)
+#define AED_ND_CNT_THD ((0x0056 << 2) + 0xfe052000)
+#define AED_ND_SUM_NUM ((0x0057 << 2) + 0xfe052000)
+#define AED_ND_CZ_NUM ((0x0058 << 2) + 0xfe052000)
+#define AED_ND_SUM_THD0 ((0x0059 << 2) + 0xfe052000)
+#define AED_ND_SUM_THD1 ((0x005a << 2) + 0xfe052000)
+#define AED_ND_CZ_THD0 ((0x005b << 2) + 0xfe052000)
+#define AED_ND_CZ_THD1 ((0x005c << 2) + 0xfe052000)
+#define AED_ND_COND_CNTL ((0x005d << 2) + 0xfe052000)
+#define AED_ND_RELEASE_COEF0 ((0x005e << 2) + 0xfe052000)
+#define AED_ND_RELEASE_COEF1 ((0x005f << 2) + 0xfe052000)
+#define AED_ND_ATTACK_COEF0 ((0x0060 << 2) + 0xfe052000)
+#define AED_ND_ATTACK_COEF1 ((0x0061 << 2) + 0xfe052000)
+#define AED_ND_CNTL ((0x0062 << 2) + 0xfe052000)
+#define AED_MIX0_LL ((0x0063 << 2) + 0xfe052000)
+#define AED_MIX0_RL ((0x0064 << 2) + 0xfe052000)
+#define AED_MIX0_LR ((0x0065 << 2) + 0xfe052000)
+#define AED_MIX0_RR ((0x0066 << 2) + 0xfe052000)
+#define AED_CLIP_THD ((0x0067 << 2) + 0xfe052000)
+#define AED_CH1_ND_SUM_OUT ((0x0068 << 2) + 0xfe052000)
+#define AED_CH2_ND_SUM_OUT ((0x0069 << 2) + 0xfe052000)
+#define AED_CH1_ND_CZ_OUT ((0x006a << 2) + 0xfe052000)
+#define AED_CH2_ND_CZ_OUT ((0x006b << 2) + 0xfe052000)
+#define AED_NOISE_STATUS ((0x006c << 2) + 0xfe052000)
+#define AED_POW_CURRENT_S0 ((0x006d << 2) + 0xfe052000)
+#define AED_POW_CURRENT_S1 ((0x006e << 2) + 0xfe052000)
+#define AED_POW_CURRENT_S2 ((0x006f << 2) + 0xfe052000)
+#define AED_POW_OUT0 ((0x0070 << 2) + 0xfe052000)
+#define AED_POW_OUT1 ((0x0071 << 2) + 0xfe052000)
+#define AED_POW_OUT2 ((0x0072 << 2) + 0xfe052000)
+#define AED_POW_ADJ_INDEX0 ((0x0073 << 2) + 0xfe052000)
+#define AED_POW_ADJ_INDEX1 ((0x0074 << 2) + 0xfe052000)
+#define AED_POW_ADJ_INDEX2 ((0x0075 << 2) + 0xfe052000)
+#define AED_DRC_GAIN_INDEX0 ((0x0076 << 2) + 0xfe052000)
+#define AED_DRC_GAIN_INDEX1 ((0x0077 << 2) + 0xfe052000)
+#define AED_DRC_GAIN_INDEX2 ((0x0078 << 2) + 0xfe052000)
+#define AED_CH1_VOLUME_STATE ((0x0079 << 2) + 0xfe052000)
+#define AED_CH2_VOLUME_STATE ((0x007a << 2) + 0xfe052000)
+#define AED_CH1_VOLUME_GAIN ((0x007b << 2) + 0xfe052000)
+#define AED_CH2_VOLUME_GAIN ((0x007c << 2) + 0xfe052000)
+#define AED_FULL_POW_CURRENT ((0x007d << 2) + 0xfe052000)
+#define AED_FULL_POW_OUT ((0x007e << 2) + 0xfe052000)
+#define AED_FULL_POW_ADJ ((0x007f << 2) + 0xfe052000)
+#define AED_FULL_DRC_GAIN ((0x0080 << 2) + 0xfe052000)
+#define AED_MASTER_VOLUME_STATE ((0x0081 << 2) + 0xfe052000)
+#define AED_MASTER_VOLUME_GAIN ((0x0082 << 2) + 0xfe052000)
+#define AED_TOP_CTL0 ((0x0083 << 2) + 0xfe052000)
+#define AED_TOP_CTL1 ((0x0084 << 2) + 0xfe052000)
+#define AED_TOP_CTL2 ((0x0085 << 2) + 0xfe052000)
+#define AED_TOP_ST ((0x0086 << 2) + 0xfe052000)
+#define AED_EQDRC_DYNAMIC_CNTL ((0x0090 << 2) + 0xfe052000)
+#define AED_COEF_RAM_CNTL_B ((0x0091 << 2) + 0xfe052000)
+#define AED_COEF_RAM_DATA_B ((0x0092 << 2) + 0xfe052000)
+#define AED_DRC_RMS_COEF0_B ((0x0093 << 2) + 0xfe052000)
+#define AED_DRC_RMS_COEF1_B ((0x0094 << 2) + 0xfe052000)
+#define AED_DRC_THD0_B ((0x0095 << 2) + 0xfe052000)
+#define AED_DRC_THD1_B ((0x0096 << 2) + 0xfe052000)
+#define AED_DRC_THD2_B ((0x0097 << 2) + 0xfe052000)
+#define AED_DRC_THD3_B ((0x0098 << 2) + 0xfe052000)
+#define AED_DRC_THD4_B ((0x0099 << 2) + 0xfe052000)
+#define AED_DRC_K0_B ((0x009a << 2) + 0xfe052000)
+#define AED_DRC_K1_B ((0x009b << 2) + 0xfe052000)
+#define AED_DRC_K2_B ((0x009c << 2) + 0xfe052000)
+#define AED_DRC_K3_B ((0x009d << 2) + 0xfe052000)
+#define AED_DRC_K4_B ((0x009e << 2) + 0xfe052000)
+#define AED_DRC_K5_B ((0x009f << 2) + 0xfe052000)
+#define AED_DRC_THD_OUT0_B ((0x00a0 << 2) + 0xfe052000)
+#define AED_DRC_THD_OUT1_B ((0x00a1 << 2) + 0xfe052000)
+#define AED_DRC_THD_OUT2_B ((0x00a2 << 2) + 0xfe052000)
+#define AED_DRC_THD_OUT3_B ((0x00a3 << 2) + 0xfe052000)
+#define AED_DRC_OFFSET_B ((0x00a4 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF00_B ((0x00a5 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF01_B ((0x00a6 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF10_B ((0x00a7 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF11_B ((0x00a8 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF20_B ((0x00a9 << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF21_B ((0x00aa << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF30_B ((0x00ab << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF31_B ((0x00ac << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF40_B ((0x00ad << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF41_B ((0x00ae << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF50_B ((0x00af << 2) + 0xfe052000)
+#define AED_DRC_RELEASE_COEF51_B ((0x00b0 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF00_B ((0x00b1 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF01_B ((0x00b2 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF10_B ((0x00b3 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF11_B ((0x00b4 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF20_B ((0x00b5 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF21_B ((0x00b6 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF30_B ((0x00b7 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF31_B ((0x00b8 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF40_B ((0x00b9 << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF41_B ((0x00ba << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF50_B ((0x00bb << 2) + 0xfe052000)
+#define AED_DRC_ATTACK_COEF51_B ((0x00bc << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF00_B ((0x00bd << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF01_B ((0x00be << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF10_B ((0x00bf << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF11_B ((0x00c0 << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF20_B ((0x00c1 << 2) + 0xfe052000)
+#define AED_MDRC_RMS_COEF21_B ((0x00c2 << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF00_B ((0x00c3 << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF01_B ((0x00c4 << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF10_B ((0x00c5 << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF11_B ((0x00c6 << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF20_B ((0x00c7 << 2) + 0xfe052000)
+#define AED_MDRC_RELEASE_COEF21_B ((0x00c8 << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF00_B ((0x00c9 << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF01_B ((0x00ca << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF10_B ((0x00cb << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF11_B ((0x00cc << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF20_B ((0x00cd << 2) + 0xfe052000)
+#define AED_MDRC_ATTACK_COEF21_B ((0x00ce << 2) + 0xfe052000)
+#define AED_MDRC_THD0_B ((0x00cf << 2) + 0xfe052000)
+#define AED_MDRC_THD1_B ((0x00d0 << 2) + 0xfe052000)
+#define AED_MDRC_THD2_B ((0x00d1 << 2) + 0xfe052000)
+#define AED_MDRC_K0_B ((0x00d2 << 2) + 0xfe052000)
+#define AED_MDRC_K1_B ((0x00d3 << 2) + 0xfe052000)
+#define AED_MDRC_K2_B ((0x00d4 << 2) + 0xfe052000)
+#define AED_MDRC_OFFSET0_B ((0x00d5 << 2) + 0xfe052000)
+#define AED_MDRC_OFFSET1_B ((0x00d6 << 2) + 0xfe052000)
+#define AED_MDRC_OFFSET2_B ((0x00d7 << 2) + 0xfe052000)
+#define AED_MDRC_LOW_GAIN_B ((0x00d8 << 2) + 0xfe052000)
+#define AED_MDRC_MID_GAIN_B ((0x00d9 << 2) + 0xfe052000)
+#define AED_MDRC_HIGH_GAIN_B ((0x00da << 2) + 0xfe052000)
+#define AED_DRC_CNTL_B ((0x00db << 2) + 0xfe052000)
+#define AED_DRC_LOOPBACK_CNTL_B ((0x00dc << 2) + 0xfe052000)
+#define AED_MDRC_CNTL_B ((0x00dd << 2) + 0xfe052000)
+#define AED_STATUS_REG ((0x00de << 2) + 0xfe052000)
+//========================================================================
+// AUDIO locker - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051400
+// -----------------------------------------------
+#define AUD_LOCK_EN ((0x0000 << 2) + 0xfe051400)
+#define AUD_LOCK_SW_RESET ((0x0001 << 2) + 0xfe051400)
+#define AUD_LOCK_SW_LATCH ((0x0002 << 2) + 0xfe051400)
+#define AUD_LOCK_HW_LATCH ((0x0003 << 2) + 0xfe051400)
+#define AUD_LOCK_REFCLK_SRC ((0x0004 << 2) + 0xfe051400)
+#define AUD_LOCK_REFCLK_LAT_INT ((0x0005 << 2) + 0xfe051400)
+#define AUD_LOCK_IMCLK_LAT_INT ((0x0006 << 2) + 0xfe051400)
+#define AUD_LOCK_OMCLK_LAT_INT ((0x0007 << 2) + 0xfe051400)
+#define AUD_LOCK_REFCLK_DS_INT ((0x0008 << 2) + 0xfe051400)
+#define AUD_LOCK_IMCLK_DS_INT ((0x0009 << 2) + 0xfe051400)
+#define AUD_LOCK_OMCLK_DS_INT ((0x000a << 2) + 0xfe051400)
+#define AUD_LOCK_INT_CLR ((0x000b << 2) + 0xfe051400)
+#define AUD_LOCK_GCLK_CTRL ((0x000c << 2) + 0xfe051400)
+#define AUD_LOCK_INT_CTRL ((0x000d << 2) + 0xfe051400)
+#define RO_REF2IMCLK_CNT_L ((0x0010 << 2) + 0xfe051400)
+#define RO_REF2IMCLK_CNT_H ((0x0011 << 2) + 0xfe051400)
+#define RO_REF2OMCLK_CNT_L ((0x0012 << 2) + 0xfe051400)
+#define RO_REF2OMCLK_CNT_H ((0x0013 << 2) + 0xfe051400)
+#define RO_IMCLK2REF_CNT_L ((0x0014 << 2) + 0xfe051400)
+#define RO_IMCLK2REF_CNT_H ((0x0015 << 2) + 0xfe051400)
+#define RO_OMCLK2REF_CNT_L ((0x0016 << 2) + 0xfe051400)
+#define RO_OMCLK2REF_CNT_H ((0x0017 << 2) + 0xfe051400)
+#define RO_REFCLK_PKG_CNT ((0x0018 << 2) + 0xfe051400)
+#define RO_IMCLK_PKG_CNT ((0x0019 << 2) + 0xfe051400)
+#define RO_OMCLK_PKG_CNT ((0x001a << 2) + 0xfe051400)
+#define RO_AUD_LOCK_INT_STATUS ((0x001b << 2) + 0xfe051400)
+//========================================================================
+// AUDIO VAD - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051800
+// -----------------------------------------------
+//
+// Reading file: VAD_REG.h
+//
+#define VAD_TOP_CTRL0 ((0x0000 << 2) + 0xfe051800)
+#define VAD_TOP_CTRL1 ((0x0001 << 2) + 0xfe051800)
+#define VAD_TOP_CTRL2 ((0x0002 << 2) + 0xfe051800)
+#define VAD_FIR_CTRL ((0x0003 << 2) + 0xfe051800)
+#define VAD_FIR_EMP ((0x0004 << 2) + 0xfe051800)
+#define VAD_FIR_COEF0 ((0x0005 << 2) + 0xfe051800)
+#define VAD_FIR_COEF1 ((0x0006 << 2) + 0xfe051800)
+#define VAD_FIR_COEF2 ((0x0007 << 2) + 0xfe051800)
+#define VAD_FIR_COEF3 ((0x0008 << 2) + 0xfe051800)
+#define VAD_FIR_COEF4 ((0x0009 << 2) + 0xfe051800)
+#define VAD_FIR_COEF5 ((0x000a << 2) + 0xfe051800)
+#define VAD_FIR_COEF6 ((0x000b << 2) + 0xfe051800)
+#define VAD_FIR_COEF7 ((0x000c << 2) + 0xfe051800)
+#define VAD_FIR_COEF8 ((0x000d << 2) + 0xfe051800)
+#define VAD_FIR_COEF9 ((0x000e << 2) + 0xfe051800)
+#define VAD_FIR_COEF10 ((0x000f << 2) + 0xfe051800)
+#define VAD_FIR_COEF11 ((0x0010 << 2) + 0xfe051800)
+#define VAD_FIR_COEF12 ((0x0011 << 2) + 0xfe051800)
+#define VAD_FRAME_CTRL0 ((0x0012 << 2) + 0xfe051800)
+#define VAD_FRAME_CTRL1 ((0x0013 << 2) + 0xfe051800)
+#define VAD_FRAME_CTRL2 ((0x0014 << 2) + 0xfe051800)
+#define VAD_CEP_CTRL0 ((0x0015 << 2) + 0xfe051800)
+#define VAD_CEP_CTRL1 ((0x0016 << 2) + 0xfe051800)
+#define VAD_CEP_CTRL2 ((0x0017 << 2) + 0xfe051800)
+#define VAD_CEP_CTRL3 ((0x0018 << 2) + 0xfe051800)
+#define VAD_CEP_CTRL4 ((0x0019 << 2) + 0xfe051800)
+#define VAD_CEP_CTRL5 ((0x001a << 2) + 0xfe051800)
+#define VAD_DEC_CTRL ((0x001b << 2) + 0xfe051800)
+#define VAD_TOP_STS0 ((0x001c << 2) + 0xfe051800)
+#define VAD_TOP_STS1 ((0x001d << 2) + 0xfe051800)
+#define VAD_TOP_STS2 ((0x001e << 2) + 0xfe051800)
+#define VAD_FIR_STS0 ((0x001f << 2) + 0xfe051800)
+#define VAD_FIR_STS1 ((0x0020 << 2) + 0xfe051800)
+#define VAD_POW_STS0 ((0x0021 << 2) + 0xfe051800)
+#define VAD_POW_STS1 ((0x0022 << 2) + 0xfe051800)
+#define VAD_POW_STS2 ((0x0023 << 2) + 0xfe051800)
+#define VAD_FFT_STS0 ((0x0024 << 2) + 0xfe051800)
+#define VAD_FFT_STS1 ((0x0025 << 2) + 0xfe051800)
+#define VAD_SPE_STS0 ((0x0026 << 2) + 0xfe051800)
+#define VAD_SPE_STS1 ((0x0027 << 2) + 0xfe051800)
+#define VAD_SPE_STS2 ((0x0028 << 2) + 0xfe051800)
+#define VAD_SPE_STS3 ((0x0029 << 2) + 0xfe051800)
+#define VAD_DEC_STS0 ((0x002a << 2) + 0xfe051800)
+#define VAD_DEC_STS1 ((0x002b << 2) + 0xfe051800)
+#define VAD_LUT_CTRL ((0x002c << 2) + 0xfe051800)
+#define VAD_LUT_WR ((0x002d << 2) + 0xfe051800)
+#define VAD_LUT_RD ((0x002e << 2) + 0xfe051800)
+#define VAD_IN_SEL0 ((0x002f << 2) + 0xfe051800)
+#define VAD_IN_SEL1 ((0x0030 << 2) + 0xfe051800)
+#define VAD_TO_DDR ((0x0031 << 2) + 0xfe051800)
+#define VAD_SYNC_CTRL0 ((0x0032 << 2) + 0xfe051800)
+#define VAD_SYNC_CHNUM_ID0 ((0x0033 << 2) + 0xfe051800)
+#define VAD_SYNC_CHNUM_ID1 ((0x0034 << 2) + 0xfe051800)
+#define VAD_SYNC_CHNUM_ID2 ((0x0035 << 2) + 0xfe051800)
+#define VAD_SYNC_CHNUM_ID3 ((0x0036 << 2) + 0xfe051800)
+#define VAD_SYNC_CHNUM_ID4 ((0x0037 << 2) + 0xfe051800)
+#define VAD_SYNC_CHNUM_ID5 ((0x0038 << 2) + 0xfe051800)
+#define VAD_SYNC_CHNUM_ID6 ((0x0039 << 2) + 0xfe051800)
+#define VAD_SYNC_CHNUM_ID7 ((0x003a << 2) + 0xfe051800)
+//
+// Closing file: VAD_REG.h
+//
+//========================================================================
+// AUDIO RESAMPLEA - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe051c00
+// -----------------------------------------------
+//
+// Reading file: RESAMPLE.h
+//
+#define AUDIO_RSAMP_CTRL0 ((0x0000 << 2) + 0xfe051c00)
+//Bit 31:3 reserved
+//Bit 2 reg_lock_rst //unsigned , default =0;
+//Bit 1 reg_rsamp_rst //unsigned , default =0;
+//Bit 0 reg_sw_rst //unsigned , default =0;
+#define AUDIO_RSAMP_CTRL1 ((0x0001 << 2) + 0xfe051c00)
+//Bit 31:27 reserved //unsigned , default =0;
+//Bit 26 reg_watchdog_en //unsigned , default =0;
+//Bit 25 reg_rsamp_rst_sel //unsigned , default =0;
+//Bit 24 reg_module_bypas //unsigned , default =0;
+//Bit 23:18 reg_gclk_ctrl //unsigned , default =0;
+//Bit 17:13 reg_in_msb //unsigned , default =23;
+//Bit 12 reg_output_en //unsigned , default =0;
+//Bit 11 reg_rsamp_en //unsigned , default =0;
+//Bit 10 reg_filt_en //unsigned , default =0;
+//Bit 9 reg_post_en //unsigned , default =0;
+//Bit 8 reg_inp_mux_mode //unsigned , default =0;
+//Bit 7:4 reserved //unsigned , default =2;
+//Bit 3:0 reg_inp_mux //unsigned , default =0;
+#define AUDIO_RSAMP_CTRL2 ((0x0002 << 2) + 0xfe051c00)
+//Bit 31:30 reserved //unsigned , default =0;
+//Bit 29:24 reg_chx_size //unsigned , default =2;
+//Bit 23:18 reserved //unsigned , default =0;
+//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4
+//Bit 15:8 reg_filt_tap //unsigned , default =63;
+//Bit 7:0 reg_intp_tap //unsigned , default =63;
+#define AUDIO_RSAMP_PHSINIT ((0x0003 << 2) + 0xfe051c00)
+//Bit 31:28 reserved //unsigned , default = 0;
+//Bit 27:0 reg_init_phs //unsigned , default = 0;
+#define AUDIO_RSAMP_PHSSTEP ((0x0004 << 2) + 0xfe051c00)
+//Bit 31 reserved //unsigned , default = 0;
+//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000
+#define AUDIO_RSAMP_SHIFT ((0x0005 << 2) + 0xfe051c00)
+//Bit 31:24 reg_rsft_iir //unsigned , default = 23;
+//Bit 23:16 reg_rsft_blnd //unsigned , default = 21;
+//Bit 15:8 reg_rsft_sinc //unsigned , default = 31;
+//Bit 7:0 reg_rsft_aa //unsigned , default = 31;
+#define AUDIO_RSAMP_ADJ_CTRL0 ((0x0006 << 2) + 0xfe051c00)
+//Bit 31:3 reserved //unsigned
+//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0;
+//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0;
+//Bit 0 reg_rsamp_adj_en //unsigned , default = 0;
+#define AUDIO_RSAMP_ADJ_CTRL1 ((0x0007 << 2) + 0xfe051c00)
+//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8;
+//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768;
+#define AUDIO_RSAMP_ADJ_SFT ((0x0008 << 2) + 0xfe051c00)
+//Bit 31:30 reserved //unsigned , default = 0;
+//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0;
+//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9;
+//Bit 23:21 reserved //unsigned , default = 0;
+//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1;
+//Bit 15:13 reserved //unsigned , default = 0;
+//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6;
+//Bit 7:6 reserved //unsigned , default = 0;
+//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12;
+#define AUDIO_RSAMP_ADJ_IDET_LEN ((0x0009 << 2) + 0xfe051c00)
+//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000;
+#define AUDIO_RSAMP_ADJ_FORCE ((0x000a << 2) + 0xfe051c00)
+//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8;
+#define AUDIO_RSAMP_ADJ_KI_FORCE ((0x000b << 2) + 0xfe051c00)
+//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0;
+#define AUDIO_RSAMP_WATCHDOG_THRD ((0x000c << 2) + 0xfe051c00)
+//Bit 31:0 reg_watchdog_thrd //signed , default = 32'h1000;
+#define AUDIO_RSAMP_RO_STATUS ((0x0010 << 2) + 0xfe051c00)
+//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]}
+#define AUDIO_RSAMP_RO_ADJ_FREQ ((0x0011 << 2) + 0xfe051c00)
+//Bit 31:0 ro_rsamp_adj_freq
+#define AUDIO_RSAMP_RO_ADJ_DIFF_BAK ((0x0012 << 2) + 0xfe051c00)
+//Bit 31:0 ro_det_diff_bak
+#define AUDIO_RSAMP_RO_ADJ_DIFF_DLT ((0x0013 << 2) + 0xfe051c00)
+//Bit 31:0 ro_det_diff_dlt
+#define AUDIO_RSAMP_RO_ADJ_PHS_ERR ((0x0014 << 2) + 0xfe051c00)
+//Bit 31:0 ro_det_phase_err
+#define AUDIO_RSAMP_RO_ADJ_KI_OUT ((0x0015 << 2) + 0xfe051c00)
+//Bit 31:0 ro_rsamp_ki_out
+#define AUDIO_RSAMP_RO_IN_CNT ((0x0016 << 2) + 0xfe051c00)
+//Bit 31:0 ro_rsamp_in_cnt
+#define AUDIO_RSAMP_RO_OUT_CNT ((0x0017 << 2) + 0xfe051c00)
+//Bit 31:0 ro_rsamp_out_cnt
+#define AUDIO_RSAMP_RO_ADJ_PHS_ERR_VAR ((0x0018 << 2) + 0xfe051c00)
+//Bit 31:0 ro_det_phase_err_var
+#define AUDIO_RSAMP_POST_COEF0 ((0x0020 << 2) + 0xfe051c00)
+//Bit 31:0 reg_post_coef0 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF1 ((0x0021 << 2) + 0xfe051c00)
+//Bit 31:0 reg_post_coef1 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF2 ((0x0022 << 2) + 0xfe051c00)
+//Bit 31:0 reg_post_coef2 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF3 ((0x0023 << 2) + 0xfe051c00)
+//Bit 31:0 reg_post_coef3 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF4 ((0x0024 << 2) + 0xfe051c00)
+//Bit 31:0 reg_post_coef4 //signed , default = 0;
+#define AUDIO_RSAMP_AA_COEF_ADDR ((0x0030 << 2) + 0xfe051c00)
+//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0;
+#define AUDIO_RSAMP_AA_COEF_DATA ((0x0031 << 2) + 0xfe051c00)
+//Bit 31:0 reg_aa_coef_data //signed , default = 0;
+#define AUDIO_RSAMP_SINC_COEF_ADDR ((0x0040 << 2) + 0xfe051c00)
+//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0;
+#define AUDIO_RSAMP_SINC_COEF_DATA ((0x0041 << 2) + 0xfe051c00)
+//Bit 31:0 reg_sinc_coef_data //signed , default = 0;
+//
+// Closing file: RESAMPLE.h
+//
+//========================================================================
+// AUDIO TOP_VAD - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe054800
+// -----------------------------------------------
+#define EE_AUDIO2_CLK81_CTRL ((0x0000 << 2) + 0xfe054800)
+#define EE_AUDIO2_CLK81_EN ((0x0001 << 2) + 0xfe054800)
+#define EE_AUDIO2_SW_RESET0 ((0x0002 << 2) + 0xfe054800)
+#define EE_AUDIO2_CLK_GATE_EN0 ((0x0003 << 2) + 0xfe054800)
+#define EE_AUDIO2_SECURITY_CTRL0 ((0x0004 << 2) + 0xfe054800)
+#define EE_AUDIO2_IRQ_FIFO_CNT ((0x0007 << 2) + 0xfe054800)
+#define EE_AUDIO2_DDRASYNC_STAT ((0x0008 << 2) + 0xfe054800)
+#define EE_AUDIO2_MCLK_VAD_CTRL ((0x0010 << 2) + 0xfe054800)
+#define EE_AUDIO2_VAD_CLK_CTRL ((0x0011 << 2) + 0xfe054800)
+#define EE_AUDIO2_MST_DLY_CTRL0 ((0x0012 << 2) + 0xfe054800)
+#define EE_AUDIO2_MST_VAD_SCLK_CTRL0 ((0x0013 << 2) + 0xfe054800)
+#define EE_AUDIO2_MST_VAD_SCLK_CTRL1 ((0x0014 << 2) + 0xfe054800)
+#define EE_AUDIO2_CLK_TDMIN_VAD_CTRL ((0x0015 << 2) + 0xfe054800)
+#define EE_AUDIO2_CLK_PDMIN_CTRL0 ((0x0016 << 2) + 0xfe054800)
+#define EE_AUDIO2_CLK_PDMIN_CTRL1 ((0x0017 << 2) + 0xfe054800)
+#define EE_AUDIO2_TOVAD_CTRL0 ((0x0020 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_CTRL0 ((0x0030 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_CTRL1 ((0x0031 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_CTRL2 ((0x0032 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_START_ADDR ((0x0033 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_INIT_ADDR ((0x0034 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_FINISH_ADDR ((0x0035 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_START_ADDRB ((0x0036 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_FINISH_ADDRB ((0x0037 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_INT_ADDR ((0x0038 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_STATUS1 ((0x0039 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_STATUS2 ((0x003a << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_CTRL ((0x0040 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_SWAP0 ((0x0041 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_SWAP1 ((0x0042 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE_VAL ((0x0043 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_STAT ((0x0044 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE0 ((0x0050 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE1 ((0x0051 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE2 ((0x0052 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE3 ((0x0053 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE4 ((0x0054 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE5 ((0x0055 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE6 ((0x0056 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MUTE7 ((0x0057 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK0 ((0x0058 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK1 ((0x0059 << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK2 ((0x005a << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK3 ((0x005b << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK4 ((0x005c << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK5 ((0x005d << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK6 ((0x005e << 2) + 0xfe054800)
+#define EE_AUDIO2_TDMIN_VAD_MASK7 ((0x005f << 2) + 0xfe054800)
+#define EE_AUDIO2_EXCEPTION_IRQ_STS0 ((0x0060 << 2) + 0xfe054800)
+#define EE_AUDIO2_EXCEPTION_IRQ_MASK0 ((0x0062 << 2) + 0xfe054800)
+#define EE_AUDIO2_EXCEPTION_IRQ_MODE0 ((0x0064 << 2) + 0xfe054800)
+#define EE_AUDIO2_EXCEPTION_IRQ_CLR0 ((0x0066 << 2) + 0xfe054800)
+#define EE_AUDIO2_EXCEPTION_IRQ_INV0 ((0x0068 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_CHNUM_ID0 ((0x0070 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_CHNUM_ID1 ((0x0071 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_CHNUM_ID2 ((0x0072 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_CHNUM_ID3 ((0x0073 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_CHNUM_ID4 ((0x0074 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_CHNUM_ID5 ((0x0075 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_CHNUM_ID6 ((0x0076 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_CHNUM_ID7 ((0x0077 << 2) + 0xfe054800)
+#define EE_AUDIO2_TODDR_VAD_CHSYNC_CTRL ((0x007f << 2) + 0xfe054800)
+//
+// Closing file: REG_LIST_AUDIO_RTL.h
+//
+//
+// Reading file: ../spifc/rtl/spifc_reg.vh
+//
+//`ifdef SPIFC_REG_DEFINE
+//`else
+//`define SPIFC_REG_DEFINE
+//`define SPIFC BASE ADDR 32'hfe00ac00
+// -----------------------------------------------
+// APB_BASE: APB2_BASE_ADDR = 0xfe00ac00
+// -----------------------------------------------
+//AHB domain regsiter.
+#define SPIFC_AHB_CTRL ((0x0000 << 2) + 0xfe00ac00)
+ //bit 31 AHB BUS enable. 1 enable ahb request. 0: disable ahb request.
+ //bit 30. decerr_en for (AXI->AHB bridge).
+ //bit 29. force_incr. for ( AXI->AHB bridge).
+ //bit 20. ahb_idle_ctrl. 1: show idle status in C1 mode. 0: show Idle always.
+ //bit 19. critical word first. CWF_EN. 1: enable. 0 : disable.
+ //bit 18:17 RDBUF_SIZE . 00: 64bytes. 01: 32 bytes. 10: 16 bytes. 11: reserved.
+ //bit 16 AHB MASTER enable. if enabled, each master use one dedicated HRDATA buffer inside ahb2api model. total 3 HRDATA buffers inside ahb2spi.
+ //if disabled the 3 HRDATA buffer will random be used for all masters.
+ //bit 14 write 1 to clean the HRDATA buffer 2. read 0 finished clean operation.
+ //bit 13 write 1 to clean the HRDATA buffer 1. read 0 finished clean operation.
+ //bit 12 write 1 to clean the HRDATA buffer 0. read 0 finished clean operation.
+ //bit 11. clr_wtchdg: 1: clear WTCHDG_STS bits in STS registers. 0 : normal.
+ //bit 10:0. not used.
+#define SPIFC_CLK_CTRL ((0x0001 << 2) + 0xfe00ac00)
+ //bit 14 asynchronous buffer ahb clock disable. 1 = disable. 0 = enable.
+ //bit 13 ahb2spi ahb clock disable. 1 = disable. 0 = enable.
+ //bit 12 ahb_arb ahb clock disable. 1 = disable. 0 = enable.
+ //bit 10 asynchronous buffer ahb clock auto gating enable. 1 = enable. 0 = disable.
+ //bit 9 ahb2spi ahb clock auto gating enable. 1 = enable. 0 = disable.
+ //bit 8 ahbarb ahb clock auto gating enable. 1 = enable. 0 = disable.
+ //bit 2. asynchronous AHB clock domain software reset. 1 = reset. 0 = normal working mode.
+ //bit 1. ahb2spi ahb clock domain software reset. 1 = reset. 0 = normal working mode.
+ //bit 0. not used.
+#define SPIFC_SEC_CTRL ((0x0002 << 2) + 0xfe00ac00)
+ //bit 31. ADDRESS security range enable. 1 = enable; 0: disable.
+ //bit 14. range6 enable: 1: enable; 0 : disable.
+ //bit 13. range5 enable: 1: enable; 0 : disable.
+ //bit 12. range4 enable: 1: enable; 0 : disable.
+ //bit 11. range3 enable: 1: enable; 0 : disable.
+ //bit 10. range2 enable: 1: enable; 0 : disable.
+ //bit 9. range1 enable: 1: enable; 0 : disable.
+ //bit 8. range0 enable: 1: enable; 0 : disable.
+#define SPIFC_APB_CTRL ((0x0003 << 2) + 0xfe00ac00)
+ //bit 31 APB control lock bit. if this bit = 1, this register can't access any more.
+ //bit 30~16. Not used.
+ //bit 15:8. SPI clock domain regsiter APB access control. each bit for one APB user ID.
+ //bit 7:0 AHB clock domain register APB access control. each bit for one APB user ID.
+#define SPIFC_RANGE0_STA ((0x0010 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 0 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE0_EDA ((0x0011 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 0 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+//HMASTER[4:0] defines:
+//5'h0: CPU secure data access.
+//5'h1: CPU secure instruction access.
+//5'h2: CPU non-secure data access.
+//5'h3: CPU non-secure instruction access.
+//5'h4: DSPA secure data access.
+//5'h5: DSPA secure instruction access.
+//5'h6: DSPA non-secure data access.
+//5'h7: DSPA non-secure instruction access.
+//5'h08~5'h0f. for DMA access with HMASTER[2:0] as DMA thread ID.
+//5'h10 all other REQUEST not CPU DSP and DMA.
+//5'h1x. Not used.
+#define SPIFC_RANGE0_CTRL ((0x0012 << 2) + 0xfe00ac00)
+ // AHB secruity range 0 control.
+ // bit 16. range 0 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ //bit 15:8 range 0 access control for DMA access.
+ //bit 15 range 0 access control for DMA thread 7
+ //bit 14 range 0 access control for DMA Thread 6
+ //bit 13 range 0 access control for DMA Thread 5.
+ //bit 12 range 0 access control for DMA Thread 4.
+ // bit 11. range 0 access control for DMA thread 3
+ // bit 10. range 0 access control for DMA Thread 2
+ // bit 9. range 0 access control for DMA Thread 1.
+ // bit 8. range 0 access control for DMA Thread 0.
+ // bit 7. range 0 access control for HMASTER == 7 //DSPA secure instruction access.
+ // bit 6. range 0 access control for HMASTER == 6 //DSPA secure data access.
+ // bit 5. range 0 access control for HMASTER == 5 //DSPA non secure instruction access
+ // bit 4. range 0 access control for HMASTER == 4 //DSPA non secure data access.
+ // bit 3. range 0 access control for HMASTER == 3 //CPU secure instruction access.
+ // bit 2. range 0 access control for HMASTER == 2 //CPU secure data access.
+ // bit 1. range 0 access control for HMASTER == 1 //CPU non secure instruction access
+ // bit 0. range 0 access control for HMASTER == 0 //CPU non secure data access.
+#define SPIFC_RANGE1_STA ((0x0013 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 1 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE1_EDA ((0x0014 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 1 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE1_CTRL ((0x0015 << 2) + 0xfe00ac00)
+ // AHB secruity range 1 control.
+ //bit 15:8 range 1 access control for DMA access.
+ //bit 15 range 1 access control for DMA thread 7
+ //bit 14 range 1 access control for DMA Thread 6
+ //bit 13 range 1 access control for DMA Thread 5.
+ //bit 12 range 1 access control for DMA Thread 4.
+ // bit 11. range 1 access control for DMA thread 3
+ // bit 10. range 1 access control for DMA Thread 2
+ // bit 9. range 1 access control for DMA Thread 1.
+ // bit 8. range 1 access control for DMA Thread 0.
+ // bit 7. range 1 access control for HMASTER == 7 Not used.
+ // bit 6. range 1 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 1 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 1 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 1 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 1 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 1 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 1 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE2_STA ((0x0016 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 2 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE2_EDA ((0x0017 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 2 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE2_CTRL ((0x0018 << 2) + 0xfe00ac00)
+ // AHB secruity range 2 control.
+ //bit 15:8 range 2 access control for DMA access.
+ //bit 15 range 2 access control for DMA thread 7
+ //bit 14 range 2 access control for DMA Thread 6
+ //bit 13 range 2 access control for DMA Thread 5.
+ //bit 12 range 2 access control for DMA Thread 4.
+ // bit 11. range 2 access control for DMA thread 3
+ // bit 10. range 2 access control for DMA Thread 2
+ // bit 9. range 2 access control for DMA Thread 1.
+ // bit 8. range 2 access control for DMA Thread 0.
+ // bit 7. range 2 access control for HMASTER == 7 Not used.
+ // bit 6. range 2 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 2 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 2 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 2 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 2 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 2 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 2 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE3_STA ((0x0019 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 3 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE3_EDA ((0x001a << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 3 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE3_CTRL ((0x001b << 2) + 0xfe00ac00)
+ // AHB secruity range 3 control.
+ //bit 15:8 range 3 access control for DMA access.
+ //bit 15 range 3 access control for DMA thread 7
+ //bit 14 range 3 access control for DMA Thread 6
+ //bit 13 range 3 access control for DMA Thread 5.
+ //bit 12 range 3 access control for DMA Thread 4.
+ // bit 11. range 3 access control for DMA thread 3
+ // bit 10. range 3 access control for DMA Thread 2
+ // bit 9. range 3 access control for DMA Thread 1.
+ // bit 8. range 3 access control for DMA Thread 0.
+ // bit 7. range 3 access control for HMASTER == 7 Not used.
+ // bit 6. range 3 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 3 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 3 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 3 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 3 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 3 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 3 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE4_STA ((0x001c << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 4 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE4_EDA ((0x001d << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 4 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE4_CTRL ((0x001e << 2) + 0xfe00ac00)
+ // AHB secruity range 4 control.
+ //bit 15:8 range 4 access control for DMA access.
+ //bit 15 range 4 access control for DMA thread 7
+ //bit 14 range 4 access control for DMA Thread 6
+ //bit 13 range 4 access control for DMA Thread 5.
+ //bit 12 range 4 access control for DMA Thread 4.
+ // bit 11. range 4 access control for DMA thread 3
+ // bit 10. range 4 access control for DMA Thread 2
+ // bit 9. range 4 access control for DMA Thread 1.
+ // bit 8. range 4 access control for DMA Thread 0.
+ // bit 7. range 4 access control for HMASTER == 7 Not used.
+ // bit 6. range 4 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 4 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 4 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 4 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 4 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 4 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 4 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE5_STA ((0x001f << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 5 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE5_EDA ((0x0021 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 5 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE5_CTRL ((0x0020 << 2) + 0xfe00ac00)
+ // AHB secruity range 5 control.
+ //bit 15:8 range 5 access control for DMA access.
+ //bit 15 range 5 access control for DMA thread 7
+ //bit 14 range 5 access control for DMA Thread 6
+ //bit 13 range 5 access control for DMA Thread 5.
+ //bit 12 range 5 access control for DMA Thread 4.
+ // bit 11. range 5 access control for DMA thread 3
+ // bit 10. range 5 access control for DMA Thread 2
+ // bit 9. range 5 access control for DMA Thread 1.
+ // bit 8. range 5 access control for DMA Thread 0.
+ // bit 7. range 5 access control for HMASTER == 7 Not used.
+ // bit 6. range 5 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 5 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 5 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 5 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 5 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 5 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 5 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE6_STA ((0x0022 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 6 start address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE6_EDA ((0x0023 << 2) + 0xfe00ac00)
+ //bit 28 :6.
+ //AHB security range 6 end address in unit of 64Byte. related to HADDR bit 28:6.
+ //bit 5:0. always 0.
+#define SPIFC_RANGE6_CTRL ((0x0024 << 2) + 0xfe00ac00)
+ // AHB secruity range 6 control.
+ //bit 15:8 range 6 access control for DMA access.
+ //bit 15 range 6 access control for DMA thread 7
+ //bit 14 range 6 access control for DMA Thread 6
+ //bit 13 range 6 access control for DMA Thread 5.
+ //bit 12 range 6 access control for DMA Thread 4.
+ // bit 11. range 6 access control for DMA thread 3
+ // bit 10. range 6 access control for DMA Thread 2
+ // bit 9. range 6 access control for DMA Thread 1.
+ // bit 8. range 6 access control for DMA Thread 0.
+ // bit 7. range 6 access control for HMASTER == 7 Not used.
+ // bit 6. range 6 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 6 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 6 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 6 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 6 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 6 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 6 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_RANGE7_CTRL ((0x0025 << 2) + 0xfe00ac00)
+ // AHB secruity range 7( default range) control.
+ //bit 15:8 range 7 access control for DMA access.
+ //bit 15 range 7 access control for DMA thread 7
+ //bit 14 range 7 access control for DMA Thread 6
+ //bit 13 range 7 access control for DMA Thread 5.
+ //bit 12 range 7 access control for DMA Thread 4.
+ // bit 11. range 7 access control for DMA thread 3
+ // bit 10. range 7 access control for DMA Thread 2
+ // bit 9. range 7 access control for DMA Thread 1.
+ // bit 8. range 7 access control for DMA Thread 0.
+ // bit 7. range 7 access control for HMASTER == 7 Not used.
+ // bit 6. range 7 access control for HMASTEr == 6 //all other access that is not CPU DSP and DMA.
+ // bit 5. range 7 access control for HMASTER == 5 //DSPB non secure
+ // bit 4. range 7 access control for HMASTER == 4 //DSPB non secure
+ // bit 3. range 7 access control for HMASTER == 3 //DSPA secure
+ // bit 2. range 7 access control for HMASTER == 2 //DSPA non secure
+ // bit 1. range 7 access control for HMASTER == 1 //CPU secure access
+ // bit 0. range 7 access control for HMASTER == 0 //CPU non secure.
+#define SPIFC_AHB_WTCH_CTRL ((0x0026 << 2) + 0xfe00ac00)
+ //bit 16. Wtch dog enable.
+ //bit 15:0. ahb bus watch dog timer. if AHB bus not response, the timer over this number, the SPIFC will send back a error response.
+#define SPIFC_SEC_VIO0 ((0x0027 << 2) + 0xfe00ac00)
+ //bit 31:0 VIO ADDR
+#define SPIFC_SEC_VIO1 ((0x0028 << 2) + 0xfe00ac00)
+ //bit 31. AHB VIO status. write 1 to clear the error info.
+ //bit 30:6 Not used.
+ //bit 5:1 HMASTER.
+ //bit 0 HWRITE.
+#define SPIFC_AHB_STS ((0x0029 << 2) + 0xfe00ac00)
+ //bit 31. AHB IDLE. when ahb disabled, to show ahb status. 1, no more ahb request or ahb requent is holded. 0, ahb is still busy.
+ //bit 30. AHB data cycle status, when ahb disabled, to show ahb data cycle status. 1, data cycle is holded, 0 : not in data cycle or data cycle is processing.
+ //bit 29. AHB bus spi requst status. 1: still waiting for spi data. 0: idle.
+ //bit 28. WTCHDG_STS. 1: AHB BUS access watchdog triggered. 0: no watchdo triggered.
+ //bit 27:21. not used.
+ //bit 20:16. WTCHDOG triggered AHB Master.
+ //bit 15:0. not used.
+#define SPIFC_AHB_WTCH_ADDR ((0x0030 << 2) + 0xfe00ac00)
+ //bit 27:0 WTCHDG triggered AHB ADDRESS
+//SPI cts_spi_clk domain regsiter.
+#define SPIFC_USER_CTRL0 ((0x0080 << 2) + 0xfe00ac00)
+ //bit 31. user request enable. write 1 to enable. read 0, means user command accepted by the SPI_CTRL.
+ //bit 30. user request finish bit. write 0 when enable user request. read 1 means SPI_CTRL finished this user command.
+ //bit 0. user data updated. write 0 when enable user request. 1 means there's datas/status read from SPI flash.
+#define SPIFC_USER_CTRL1 ((0x0081 << 2) + 0xfe00ac00)
+ //bit 31. not used.
+ //bit 30. user command cycle enable. 1) enable. 0) don't send command in usr command period.
+ //bit 29:28. user command mode. 00 = SPI extend mode. 01 : dual mode. 10: quad mode.
+ //bit 27:20. user command code. the code need to send in command period.
+ //bit 19. user address cycle enable.
+ //bit 18:17 user address mode: 00 = SPI extend mode. 01 : dual mode. 10: quad mode.
+ //bit 16:15 user address Byte length 00 = 1 byte. 01 = 2 bytes. 10 = 3 bytes. 11 = 4bytes.
+ //bit 14 user datout enable.
+ //bit 13 user dataout AES enable. 1: dataout through AES describle. 0 : original data.
+ //bit 12 user data output source. 0: from data buffer. 1: from status register.
+ //bit 11:10 user dataout mode: 00 SPI extend model. 01 : dual model. 10. quad mode.
+ //bit 9:0 User data out bytes num.
+#define SPIFC_USER_CTRL2 ((0x0082 << 2) + 0xfe00ac00)
+ //bit 31 usr_dummy_en 1: enable dummy cycles. 0 : no dummy cycles.
+ //bit 30: 29 usr_dummy_mode 2'b00 = SPI extend mode. 01 dual mode. 10 Quad mode.
+ //bit 28:23 user dummy clock cycle number.
+ //bit 19:16. user command input/output direction control. 000000: right after the last output.
+ // 1: after the first cycle of dummy cycle.
+ // .....
+ // 4'hf: right before the datin cycle.
+ //bit 15:8. data on the dummy cycle after the first byte.
+ //bit 7:0 The first bytes data showed on dummy cycle. some flash may need special data for enhance performance mode or XIP mode.
+#define SPIFC_USER_CTRL3 ((0x0083 << 2) + 0xfe00ac00)
+ //bit 31 usr_datin_en 1: datain cycle enabled. 0: no datain cycle.
+ //bit 30: datin_dest. 1: save the input data to STATUS register. 0 save the input data to data buffer.
+ //bit 29: 1: enable datain data AES describle. 0: not use AES.
+ //bit 28:27. datin mode. 2'b00 SPI extend mode. 01: dual mode. 10 Quad mode.
+ //bit 25:16. user data in data bytes. how many bytes of user datain expected.
+#define SPIFC_USER_ADDR ((0x0084 << 2) + 0xfe00ac00)
+ //bit 31:0. 32bits user address.
+#define SPIFC_AHB_REQ_CTRL ((0x0085 << 2) + 0xfe00ac00)
+ //bit 31. AHB request enable.
+ //bit 30 AHB cmd_en. command cycle enable.
+ //bit 29:28. ahb command mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode.
+ //bit 27:20:.AHB command code.
+ //bit 19. ahb request address cycle enable.
+ //bit 18:17 AHB ADDRESS mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode.
+ //bit 16:15 AHB ADDRESS data width. 2'b00: 1byte. 2'b01 : 2bytes. 2'b10: 3bytes. 2'b11 4bytes.
+ //bit 13:10 AHB request spi bus input switch time. 0 : after address cycle. 1: the frist dummy cycles. ... 0xf. after dummy cycle.
+ //bit 9:8 AHB DATAIN mode. 2'b00: spi mode. 01: dual mode. 10 Quad mode.
+ //bit 7 DATA IN AES enable. 1: enable 0: disable.
+ //bit 1:0 AHB REQ DATA size. 2'b00: 64bytes. 2'b01: 32 bytes. 2'b10 : 16 bytes. 2'b11: reserved. this bit settign should be same as RDBUF_SIZE setting.
+#define SPIFC_AHB_REQ_CTRL1 ((0x0086 << 2) + 0xfe00ac00)
+ //bit 31. ahb Dummy enable.
+ //bit 30:29. ahb dummy mode.
+ //bit 28:23. ahb request dummy clock cycles.
+ //bit 15:0. ahb dummy period output data.
+#define SPIFC_AHB_REQ_CTRL2 ((0x0087 << 2) + 0xfe00ac00)
+ //bit 1:0 AHB address position. this settign depend on SPIFC_AHB_CTRL register CWF_EN bit and RDBUF_SIZE.
+ // if CWF_EN is enabled. these bit should be set to 2'b10 (16BYTE boundary).
+ // if CWF_EN is disabled. these bit should be set to same as the RDBUF_SIZE and AHB REQ DATA SIZE.
+ //00 : 64byte boundary.
+ //01 : 32byte boundary.
+ //10 : 16byte boundary.
+ //11 : reserved.
+#define SPIFC_ACTIMING0 ((0x0088 << 2) + 0xfe00ac00)
+ //bit 31:30. tSLCH
+ //bit 29:28 tCLSH
+ //bit 20:16 tSHWL
+ //bit 15:12 tSHSL2
+ //bit 11:8 tSHSL1
+ //bit 7:0 tWHSL
+#define SPIFC_ACTIMING1 ((0x0089 << 2) + 0xfe00ac00)
+ //bit 31. D2 pin WP_n function enable.
+ //bit 30. D2 Pin value in WP_n fucntion.
+ //bit 29. D3 Pin HOLD_n function enable.
+ //bit 8. DTR mode. not support.
+ //bit 6:4. Clock turn around delay. use it to set the system SPI clock read data delay.
+ //bit 3:0. not used.
+#define SPIFC_ACTIMING2 ((0x008a << 2) + 0xfe00ac00)
+ //bit 31. spi clock input pin enable. SPIFC controller used this pin as clock to latch the input data.
+ //bit [3:0] spi clock input pin delay adjustment.
+//SPI DATA BUFFER. There's a total 512Byte + 64byte(orgnized as 36x128bits) SRAM .
+// since each APB access is 32bits. So we use word address as APB read/write address.
+// But for SPI side we have to use 128bit boundary. That's the first Pragram/read SPI with data buffer must start at data buffer 128bit boundary. that means the SPIFC_USE_DBUF_ADDR last 2 bits must be 0.
+#define SPIFC_DBUF_CTRL ((0x0090 << 2) + 0xfe00ac00)
+ //bit 31. 1 = write DBUF. 0 : read DBUF.
+ //bit 30. 1. = auto update address. 0 don't change address.
+ //bit 7:0 DBUF address unit 32bits.
+#define SPIFC_DBUF_DATA ((0x0091 << 2) + 0xfe00ac00)
+ //bit 31:0. if SPIFC_DBUF_CTRL bit 31 = 1. write to this register will trigger one write to DBUF. and the data will be writen to DBUF.
+#define SPIFC_USER_DBUF_ADDR ((0x0092 << 2) + 0xfe00ac00)
+ //bit 7:0. the DBUF ADDRESS used to send to or receive from SPI FLASH. the last 2 bits must be 0.
+#define SPIFC_FLASH_STATUS ((0x00a0 << 2) + 0xfe00ac00)
+#define SPIFC_STATUS ((0x00a1 << 2) + 0xfe00ac00)
+ //bit 1. AES KEY valid. read only 1 : The aes key is ready to use. 0: the aes key is not ready.
+ //bit 0. SPI CTRL STATE IDLE. read only. 1 = idle; 0 = busy.
+#define SPIFC_CTRL ((0x00a2 << 2) + 0xfe00ac00)
+ //bit 15:14. mempd for DBUF MEMORY.
+ //bit 13 spifc asynchronous buffer clock disable. 1 = disable. 0 = enable.
+ //bit 12. spifc controller clock disable. 1 = disable. 0 = enable.
+ //bit 9. spifc asynchronous bufer clock auto gate enable. 1 = enable. 0 = disable.
+ //bit 8. spifc controller clock auto gate enable. 1 = enable. 0 = disable.
+ //bit 2. spifc interface reset. 1 = RESET. 0 = normal working mode.
+ //bit 1. spifc asynchronous buffer spi clock side reset. 1 = RESET. 0 : normal working mode.
+ //bit 0. spifc controller reset. 1 = RESET. 0 : normal working mode.
+//`endif
+//
+// Closing file: ../spifc/rtl/spifc_reg.vh
+//
+//
+// Reading file: ../mmc_new/dmc_clk_freq/rtl/dmc_clk_freq.vh
+//
+//`ifdef DMC_FREQ_REG_DEFINE
+//`else
+//`define DMC_FREQ_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfe024c00
+// -----------------------------------------------
+//`define DMC_FREQ_REG_BASE 32'hfe024c00
+#define AM_DDR_PLL_CNTL0 ((0x0000 << 2) + 0xfe024c00)
+ //bit 31 : ddr_gp_pll_rst. default 1
+ //bit 30 : ddr_gp_pll_rstn. default 0.
+ //bit 29 : ddr_gp_pll_lk_rstn default 0
+ //bit 28 : ddr_gp_pll_en. default 0
+ //bit 25:24 : ddr_gp_pll_output_od2 default 0
+ //bit 23:20 : ddr_gp_pll_od1 default 0
+ //bit 17:16 : ddr_gp_pll_od_s1 default 0
+ //bit 15 : ddr_gp_pll_clk1x_inv_sel default 0
+ //bit 14 : ddr_gp_pll_clk4x_by_en default 0
+ //bit 12:8 : ddr_gp_pll_n default 0
+ //bit 7:0 : ddr_gp_pll_pll_div_m default 0
+#define AM_DDR_PLL_CNTL1 ((0x0001 << 2) + 0xfe024c00)
+ //bit 31 : ddr_sdm_pll_rst default 1
+ //bit 30 : ddr_sdm_pll_e default 0.
+ //bit 29 : ddr_sdm_pll_dvdd_pd default 0
+ //bit 28 : ddr_sdm_pll_free_run default 0
+ //bit 17:16 : ddr_sdm_pll_output_od default 1
+ //bit 12:8 : ddr_sdm_pll_n default 1
+ //bit 7:0 : ddr_sdm_pll_div_m
+#define AM_DDR_PLL_CNTL2 ((0x0002 << 2) + 0xfe024c00)
+ //default 0x0
+ //bit 31:24 : ddr_sdm_pll_reve
+ //bit 23:20 : ddr_sdm_pll_cp_adj
+ //bit 19:16 : ddr_sdm_pll_bias_icp_adj
+ //bit 15:14 : ddr_sdm_pll_lock_long
+ //bit 12 : ddr_sdm_pll_dead_time_select
+ //bit 11 : ddr_sdm_pll_cp_offset_en
+ //bit 10 : ddr_sdm_pll_ldo0p8_adj
+ //bit 9 : ddr_sdm_pll_ldo1p5_adj
+ //bit 8 : ddr_sdm_pll_lock_f
+ //bit 7:6 : ddr_sdm_pll_r3_cnt
+ //bit 5:4 : ddr_sdm_pll_r2_cnt
+ //bit 3:2 : ddr_sdm_pll_c3_cnt
+ //bit 1:0 : ddr_sdm_pll_c2_cnt.
+#define AM_DDR_PLL_CNTL3 ((0x0003 << 2) + 0xfe024c00)
+ //default 0x0
+ //bit 31:4 : not used.
+ //bit 3:2 : ddr_sdm_pll_ini_vco_adj
+ //bit 1:0 : ddr_sdm_pll_lkdet_sel
+#define AM_DDR_PLL_CNTL4 ((0x0004 << 2) + 0xfe024c00)
+ //default 0x0
+ //bit 31 : ddr_gp_pll_dpll_load
+ //bit 30 : ddr_gp_pll_free_run
+ //bit 29:28 : ddr_gp_pll_judge_win
+ //bit 27 : ddr_gp_pll_ldo0p8_ref_mux
+ //bit 26 : ddr_gp_pll_ldo1p5_adj
+ //bit 25 : ddr_gp_pll_ldo0p8_daj
+ //bit 24:21 : ddr_gp_pll_ssc_str_m
+ //bit 20:18 : ddr_gp_pll_fref_sel
+ //bit 17:16 : ddr_gp_pll_lk_vco_div_od
+ //bit 15:12 : ddr_gp_pll_cp_icp_ctrl
+ //bit 11:8 : ddr_gp_pll_ssc_dep_sel
+ //bit 7 : ddr_gp_pll_dead_time_select
+ //bit 6:0 : ddr_gp_pll_m_s1
+#define AM_DDR_PLL_CNTL5 ((0x0005 << 2) + 0xfe024c00)
+ //default 0x0
+ //bit 31:24 : ddr_gp_pll_reve
+ //bit 23:22 : ddr_gp_pll_ss_mode
+ //bit 21:20 : ddr_gp_pll_ini_vco_adj
+ //bit 19:16 : ddr_gp_pll_bias_icp_ctrl
+ //bit 15 : ddr_gp_pll_clk_by_sel
+ //bit 14 : ddr_gp_pll_cp_offset_en
+ //bit 13 : ddr_gp_pll_lk_width
+ //bit 12 : ddr_gp_pll_lk_bypass
+ //bit 11 : ddr_gp_pll_sdm_en
+ //bit 10 : ddr_gp_pll_shift_en
+ //bit 9 : ddr_gp_pll_load_en
+ //bit 8:4 : ddr_gp_pll_vco_limit
+ //bit 3:2 : ddr_gp_pll_shift_v
+ //bit 1:0 : ddr_gp_pll_os_ssc
+#define AM_DDR_PLL_CNTL6 ((0x0006 << 2) + 0xfe024c00)
+ //default 0x0
+ //bit 31:30 : ddr_gp_pll_c3_cnt
+ //bit 29:28 : ddr_gp_pll_c2_cnt
+ //bit 27:26 : ddr_gp_pll_r3_cnt
+ //bit 25:24 : ddr_gp_pll_r2_cnt
+ //bit 23:19 : ddr_gp_pll_inte_num
+ //bit 18:0 : ddr_gp_pll_fracin
+#define AM_DDR_PLL_STS ((0x0007 << 2) + 0xfe024c00)
+ //bit 31 : DDR PLL lock bit. 1 = locked. 0 = not locked.
+ //bit 30:0 : not used.
+#define DDR_CLK_CNTL ((0x0008 << 2) + 0xfe024c00)
+ //bit 31 ddr_pll_clk enable. enable the clock from DDR_PLL to clock generateion.
+ // whenever change the DDR_PLL frequency, disable the clock, after the DDR_PLL locked, then enable it again.
+ //bit 30. ddr_pll_prod_test_en. enable the clock to clock/32 which to clock frequency measurement and production test pin.
+ //bit 29. not used.
+ //bit 28. clock generation logic soft reset. 0 = reset.
+ //bit 27. phy_4xclk phase inverter..
+ //bit 25. DDRPHY DfiClk/DMC clock selection. 1: AM_PLL clk output /2. 0: directly output from AM_PLL .
+ //bit 24. enable AM_PLL CLK output /2 function. 1: enable. 0: disable. if try to use this clkoutput/2 function.
+ //bit 26. pll_freq divide/2. 1: use pll div/2 clock as the n_clk. 0: use pll clock as n_clk. this setting is used for the synopsys DDR PHY PLL fast lock mode.
+ //bit 2. enable dmc_clk.
+ //bit 1. not used.
+ //bit 0. enable LPDDR4-PHY clock
+#define DDR_PHY_CTRL ((0x0009 << 2) + 0xfe024c00)
+ // LPDDR4 power on reset need to special combination of PwrOkIn and phy_reset_n.
+ //bit 31: DDr PHY power on status. read only.
+ //bit 4. DDR PHY PwrOkIn pin.
+ //bit 1. DDR PHY APB soft reset_n.
+ //bit 0. phy_reset_n.
+#define AM_DDR_PLL_FREQ1_OD ((0x000c << 2) + 0xfe024c00)
+ //freqency set 1 PLL OD and OD1 setting. when change to freqency 1 will use this setting.
+//frequency set 0 use original DDR_PLL_CNTL0 setting.
+ //bit 8 currunt FREQ selection. it can forced to change to select which freqency to select, or it can auto changed by FREQ change hardware.
+ //bit 7:0 is the FREQ1 GP_PLL output clock setting.
+ //bit 7 gp_pll_clk1x_inv_sel
+ //bit 6 gp_pll_clk4x_by_en
+ //bit 5:4 gp_pll_output_od2.
+ //bit 3:0. gp_pll_od1.
+//`endif
+//
+// Closing file: ../mmc_new/dmc_clk_freq/rtl/dmc_clk_freq.vh
+//
+//
+// Reading file: ../mmc_new/dmc/rtl/dmc_sec.vh
+//
+//`ifdef DMC_SEC_REG_DEFINE
+//`else
+//`define DMC_SEC_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfe025000
+// -----------------------------------------------
+//`define DMC_SEC_REG_BASE 32'hfe025000
+// DMC ID assignment.
+// ID[13 :0] total 14 bit ID.
+// ID[4:0]: for MASTER IDs.
+// 0: A55 CPU.
+// 1: DSPA
+// 2: DSPB
+// 3: WAVE
+// 4: GDC
+// 5: GE2D
+// 6: ISP
+// 7: NNA
+// 8: JPEG
+// 9~15: not used in C1.
+// 16 : Device. need to look at ID bit [11:9] to see the sub module master.
+// 16 : for Device. need to look at ID bit [11:9] to see the sub module master.
+// 17 : for USB AHB device.
+// 18 : for USB AXI host.
+// 19 : for I2C debug input.
+// 20~30: Not used in C1
+// 31: DMC internal test channel.
+// Device master is for small periphs. it is consists of 8 sub modules and identified with ID bits [11:9]
+// bit[11:9] == 0 : ETH
+// bit[11:9] == 1 : SPICC_A
+// bit[11:9] == 2 : SPICC_B
+// bit[11:9] == 3 : SD_EMMCA
+// bit[11:9] == 4 : SD_EMMCB
+// bit[11:9] == 5 : AUDIO. For AUDIO need to check ID[8:5] for detail.
+// ID[8:5] == 0: TO_DDR A
+// ID[8:5] == 1: TO_DDR B
+// ID[8:5] == 4: FROM_DDR A
+// ID[8:5] == 5: FROM_DDR B
+// bit[11:9] == 6 : DMA. For DMC need to check ID [8:6] for totoal 8 threads IDs.
+// bit[11:9] == 7 : NAND_EMMCC
+// Total 16 address regions can be defined in All DDR address space.
+// The first 15 region can be defined by start address and end address in 4Kbyte boundary. The 16th range is all other space not defined by the first 15 regions.
+// all the 15 regions can be enabled or disabled seperately. Each range use security level bit to select one of the two des key to do data scramble.
+// The region can be overlapped or crossover. For one transaction, DMC would check the address from region 0 to 15.
+// DMC would use the policy defined in the region that this transaction address hit first.
+#define DMC_SEC_RANGE0_CTRL ((0x0000 << 2) + 0xfe025000)
+ //bit 31:16 | 0 | range0_eda | range 0 end address higher 16bits.
+ //bit 15:0 | 0 | range0_sta | range 0 start address higher 16bits.
+#define DMC_SEC_RANGE0_CTRL1 ((0x0001 << 2) + 0xfe025000)
+ //bit 7:5 | 0 | range0_secrity_level | range0 secruity level for DMC and DEMUX only.
+ //bit 4 | 0 | range0_prot_en | range0 allow protect monitor function. 1: allowed. 0: not allowed.
+ //bit 3 | 0 | range0_local_des_en | range0 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES_EN to decide this region data describle enable or not.
+ //bit 2 | 0 | range0_lock | lock range 0 registers. write 1 to lock range 0 register. can't change anymore.
+ //bit 1 | 0 | range0_key_sel | range 0 data describle key selection. 1 : key1. 0 : key0.
+ //bit 0 | 0 | range0_en | range 0 enable bit. 1 : enable, 0 : disable.
+#define DMC_SEC_RANGE1_CTRL ((0x0002 << 2) + 0xfe025000)
+ //bit 31:16 | 0 | range1_eda | range 1 end address higher 16bits.
+ //bit 15:0 | 0 | range1_sta | range 1 start address higher 16bits.
+#define DMC_SEC_RANGE1_CTRL1 ((0x0003 << 2) + 0xfe025000)
+ //bit 7:5 | 0 | range1_secrity_level | range1 secruity level for DMC and DEMUX only.
+ //bit 4 | 0 | range1_prot_en | range1 allow protect monitor function. 1: allowed. 0: not allowed.
+ //bit 3 | 0 | range1_local_des_en | range1 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES_EN to decide this region data describle enable or not.
+ //bit 2 | 0 | range1_lock | lock range 1 registers. write 1 to lock range 1 register. can't change anymore.
+ //bit 1 | 0 | range1_key_sel | range 1 data describle key selection. 1 : key1. 1 : key0.
+ //bit 0 | 0 | range1_en | range 0 enable bit. 1 : enable, 0 : disable.
+#define DMC_SEC_RANGE2_CTRL ((0x0004 << 2) + 0xfe025000)
+ //bit 31:16 | 0 | range2_eda | range 2 end address higher 16bits.
+ //bit 15:0 | 0 | range2_sta | range 2 start address higher 16bits.
+#define DMC_SEC_RANGE2_CTRL1 ((0x0005 << 2) + 0xfe025000)
+ //bit 7:5 | 0 | range2_secrity_level | range2 secruity level for DMC and DEMUX only.
+ //bit 4 | 0 | range2_prot_en | range2 allow protect monitor function. 1: allowed. 0: not allowed.
+ //bit 3 | 0 | range2_local_des_en | range2 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES to decide this region data describle enable or not.
+ //bit 2 | 0 | range2_lock | lock range 2 registers. write 1 to lock range 2 register. can't change anymore.
+ //bit 1 | 0 | range2_key_sel | range 2 data describle key selection. 1 : key1. 1 : key0.
+ //bit 0 | 0 | range2_en | range 2 enable bit. 1 : enable, 0 : disable.
+#define DMC_SEC_RANGE3_CTRL ((0x0006 << 2) + 0xfe025000)
+ //bit 31:16 | 0 | range3_eda | range 3 end address higher 16bits.
+ //bit 15:0 | 0 | range3_sta | range 3 start address higher 16bits.
+#define DMC_SEC_RANGE3_CTRL1 ((0x0007 << 2) + 0xfe025000)
+ //bit 7:5 | 0 | range3_secrity_level | range3 secruity level for DMC and DEMUX only.
+ //bit 4 | 0 | range3_prot_en | range3 allow protect monitor function. 1: allowed. 0: not allowed.
+ //bit 3 | 0 | range3_local_des_en | range3 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES to decide this region data describle enable or not.
+ //bit 2 | 0 | range3_lock | lock range 3 registers. write 1 to lock range 3 related registers. can't change anymore.
+ //bit 1 | 0 | range3_key_sel | range 3 data describle key selection. 1 : key1. 1 : key0.
+ //bit 0 | 0 | range3_en | range 3 enable bit. 1 : enable, 0 : disable.
+#define DMC_SEC_RANGE4_CTRL ((0x0008 << 2) + 0xfe025000)
+ //bit 31:16 | 0 | range4_eda | range 4 end address higher 16bits.
+ //bit 15:0 | 0 | range4_sta | range 4 start address higher 16bits.
+#define DMC_SEC_RANGE4_CTRL1 ((0x0009 << 2) + 0xfe025000)
+ //bit 7:5 | 0 | range4_secrity_level | range4 secruity level for DMC and DEMUX only.
+ //bit 4 | 0 | range4_prot_en | range4 allow protect monitor function. 1: allowed. 0: not allowed.
+ //bit 3 | 0 | range4_local_des_en | range4 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES to decide this region data describle enable or not.
+ //bit 2 | 0 | range4_lock | lock range 4 registers. write 1 to lock range 4 related registers. can't change anymore.
+ //bit 1 | 0 | range4_key_sel | range 4 data describle key selection. 1 : key1. 1 : key0.
+ //bit 0 | 0 | range4_en | range 4 enable bit. 1 : enable, 0 : disable.
+#define DMC_SEC_RANGE5_CTRL ((0x000a << 2) + 0xfe025000)
+#define DMC_SEC_RANGE5_CTRL1 ((0x000b << 2) + 0xfe025000)
+#define DMC_SEC_RANGE6_CTRL ((0x000c << 2) + 0xfe025000)
+#define DMC_SEC_RANGE6_CTRL1 ((0x000d << 2) + 0xfe025000)
+#define DMC_SEC_RANGE7_CTRL ((0x000e << 2) + 0xfe025000)
+#define DMC_SEC_RANGE7_CTRL1 ((0x000f << 2) + 0xfe025000)
+#define DMC_SEC_RANGE8_CTRL ((0x0010 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE8_CTRL1 ((0x0011 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE9_CTRL ((0x0012 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE9_CTRL1 ((0x0013 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE10_CTRL ((0x0014 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE10_CTRL1 ((0x0015 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE11_CTRL ((0x0016 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE11_CTRL1 ((0x0017 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE12_CTRL ((0x0018 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE12_CTRL1 ((0x0019 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE13_CTRL ((0x001a << 2) + 0xfe025000)
+#define DMC_SEC_RANGE13_CTRL1 ((0x001b << 2) + 0xfe025000)
+#define DMC_SEC_RANGE14_CTRL ((0x001c << 2) + 0xfe025000)
+#define DMC_SEC_RANGE14_CTRL1 ((0x001d << 2) + 0xfe025000)
+#define DMC_SEC_RANGE15_CTRL1 ((0x001f << 2) + 0xfe025000)
+//per range per sub ID access enable.
+#define DMC_SEC_RANGE0_RID_CTRL0 ((0x0020 << 2) + 0xfe025000)
+ //range_rd_sid_en[31:0];
+#define DMC_SEC_RANGE0_RID_CTRL1 ((0x0021 << 2) + 0xfe025000)
+ //range_rd_sid_en[63:32];
+#define DMC_SEC_RANGE0_RID_CTRL2 ((0x0022 << 2) + 0xfe025000)
+ //range_rd_sid_en[95:64];
+#define DMC_SEC_RANGE0_RID_CTRL3 ((0x0023 << 2) + 0xfe025000)
+ //range_rd_sid_en[127:96];
+#define DMC_SEC_RANGE0_RID_CTRL4 ((0x0024 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE1_RID_CTRL0 ((0x0026 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE1_RID_CTRL1 ((0x0027 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE1_RID_CTRL2 ((0x0028 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE1_RID_CTRL3 ((0x0029 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE1_RID_CTRL4 ((0x002a << 2) + 0xfe025000)
+#define DMC_SEC_RANGE2_RID_CTRL0 ((0x002c << 2) + 0xfe025000)
+#define DMC_SEC_RANGE2_RID_CTRL1 ((0x002d << 2) + 0xfe025000)
+#define DMC_SEC_RANGE2_RID_CTRL2 ((0x002e << 2) + 0xfe025000)
+#define DMC_SEC_RANGE2_RID_CTRL3 ((0x002f << 2) + 0xfe025000)
+#define DMC_SEC_RANGE2_RID_CTRL4 ((0x0030 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE3_RID_CTRL0 ((0x0032 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE3_RID_CTRL1 ((0x0033 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE3_RID_CTRL2 ((0x0034 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE3_RID_CTRL3 ((0x0035 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE3_RID_CTRL4 ((0x0036 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE4_RID_CTRL0 ((0x0038 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE4_RID_CTRL1 ((0x0039 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE4_RID_CTRL2 ((0x003a << 2) + 0xfe025000)
+#define DMC_SEC_RANGE4_RID_CTRL3 ((0x003b << 2) + 0xfe025000)
+#define DMC_SEC_RANGE4_RID_CTRL4 ((0x003c << 2) + 0xfe025000)
+#define DMC_SEC_RANGE5_RID_CTRL0 ((0x003e << 2) + 0xfe025000)
+#define DMC_SEC_RANGE5_RID_CTRL1 ((0x003f << 2) + 0xfe025000)
+#define DMC_SEC_RANGE5_RID_CTRL2 ((0x0040 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE5_RID_CTRL3 ((0x0041 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE5_RID_CTRL4 ((0x0042 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE6_RID_CTRL0 ((0x0044 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE6_RID_CTRL1 ((0x0045 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE6_RID_CTRL2 ((0x0046 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE6_RID_CTRL3 ((0x0047 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE6_RID_CTRL4 ((0x0048 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE7_RID_CTRL0 ((0x004a << 2) + 0xfe025000)
+#define DMC_SEC_RANGE7_RID_CTRL1 ((0x004b << 2) + 0xfe025000)
+#define DMC_SEC_RANGE7_RID_CTRL2 ((0x004c << 2) + 0xfe025000)
+#define DMC_SEC_RANGE7_RID_CTRL3 ((0x004d << 2) + 0xfe025000)
+#define DMC_SEC_RANGE7_RID_CTRL4 ((0x004e << 2) + 0xfe025000)
+#define DMC_SEC_RANGE8_RID_CTRL0 ((0x0050 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE8_RID_CTRL1 ((0x0051 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE8_RID_CTRL2 ((0x0052 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE8_RID_CTRL3 ((0x0053 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE8_RID_CTRL4 ((0x0054 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE9_RID_CTRL0 ((0x0056 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE9_RID_CTRL1 ((0x0057 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE9_RID_CTRL2 ((0x0058 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE9_RID_CTRL3 ((0x0059 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE9_RID_CTRL4 ((0x005a << 2) + 0xfe025000)
+#define DMC_SEC_RANGE10_RID_CTRL0 ((0x005c << 2) + 0xfe025000)
+#define DMC_SEC_RANGE10_RID_CTRL1 ((0x005d << 2) + 0xfe025000)
+#define DMC_SEC_RANGE10_RID_CTRL2 ((0x005e << 2) + 0xfe025000)
+#define DMC_SEC_RANGE10_RID_CTRL3 ((0x005f << 2) + 0xfe025000)
+#define DMC_SEC_RANGE10_RID_CTRL4 ((0x0060 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE11_RID_CTRL0 ((0x0062 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE11_RID_CTRL1 ((0x0063 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE11_RID_CTRL2 ((0x0064 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE11_RID_CTRL3 ((0x0065 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE11_RID_CTRL4 ((0x0066 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE12_RID_CTRL0 ((0x0068 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE12_RID_CTRL1 ((0x0069 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE12_RID_CTRL2 ((0x006a << 2) + 0xfe025000)
+#define DMC_SEC_RANGE12_RID_CTRL3 ((0x006b << 2) + 0xfe025000)
+#define DMC_SEC_RANGE12_RID_CTRL4 ((0x006c << 2) + 0xfe025000)
+#define DMC_SEC_RANGE13_RID_CTRL0 ((0x006e << 2) + 0xfe025000)
+#define DMC_SEC_RANGE13_RID_CTRL1 ((0x006f << 2) + 0xfe025000)
+#define DMC_SEC_RANGE13_RID_CTRL2 ((0x0070 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE13_RID_CTRL3 ((0x0071 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE13_RID_CTRL4 ((0x0072 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE14_RID_CTRL0 ((0x0074 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE14_RID_CTRL1 ((0x0075 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE14_RID_CTRL2 ((0x0076 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE14_RID_CTRL3 ((0x0077 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE14_RID_CTRL4 ((0x0078 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE15_RID_CTRL0 ((0x007a << 2) + 0xfe025000)
+#define DMC_SEC_RANGE15_RID_CTRL1 ((0x007b << 2) + 0xfe025000)
+#define DMC_SEC_RANGE15_RID_CTRL2 ((0x007c << 2) + 0xfe025000)
+#define DMC_SEC_RANGE15_RID_CTRL3 ((0x007d << 2) + 0xfe025000)
+#define DMC_SEC_RANGE15_RID_CTRL4 ((0x007e << 2) + 0xfe025000)
+//per range per sub ID access enable.
+#define DMC_SEC_RANGE0_WID_CTRL0 ((0x0080 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE0_WID_CTRL1 ((0x0081 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE0_WID_CTRL2 ((0x0082 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE0_WID_CTRL3 ((0x0083 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE0_WID_CTRL4 ((0x0084 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE1_WID_CTRL0 ((0x0086 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE1_WID_CTRL1 ((0x0087 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE1_WID_CTRL2 ((0x0088 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE1_WID_CTRL3 ((0x0089 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE1_WID_CTRL4 ((0x008a << 2) + 0xfe025000)
+#define DMC_SEC_RANGE2_WID_CTRL0 ((0x008c << 2) + 0xfe025000)
+#define DMC_SEC_RANGE2_WID_CTRL1 ((0x008d << 2) + 0xfe025000)
+#define DMC_SEC_RANGE2_WID_CTRL2 ((0x008e << 2) + 0xfe025000)
+#define DMC_SEC_RANGE2_WID_CTRL3 ((0x008f << 2) + 0xfe025000)
+#define DMC_SEC_RANGE2_WID_CTRL4 ((0x0090 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE3_WID_CTRL0 ((0x0092 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE3_WID_CTRL1 ((0x0093 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE3_WID_CTRL2 ((0x0094 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE3_WID_CTRL3 ((0x0095 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE3_WID_CTRL4 ((0x0096 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE4_WID_CTRL0 ((0x0098 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE4_WID_CTRL1 ((0x0099 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE4_WID_CTRL2 ((0x009a << 2) + 0xfe025000)
+#define DMC_SEC_RANGE4_WID_CTRL3 ((0x009b << 2) + 0xfe025000)
+#define DMC_SEC_RANGE4_WID_CTRL4 ((0x009c << 2) + 0xfe025000)
+#define DMC_SEC_RANGE5_WID_CTRL0 ((0x009e << 2) + 0xfe025000)
+#define DMC_SEC_RANGE5_WID_CTRL1 ((0x009f << 2) + 0xfe025000)
+#define DMC_SEC_RANGE5_WID_CTRL2 ((0x00a0 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE5_WID_CTRL3 ((0x00a1 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE5_WID_CTRL4 ((0x00a2 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE6_WID_CTRL0 ((0x00a4 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE6_WID_CTRL1 ((0x00a5 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE6_WID_CTRL2 ((0x00a6 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE6_WID_CTRL3 ((0x00a7 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE6_WID_CTRL4 ((0x00a8 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE7_WID_CTRL0 ((0x00aa << 2) + 0xfe025000)
+#define DMC_SEC_RANGE7_WID_CTRL1 ((0x00ab << 2) + 0xfe025000)
+#define DMC_SEC_RANGE7_WID_CTRL2 ((0x00ac << 2) + 0xfe025000)
+#define DMC_SEC_RANGE7_WID_CTRL3 ((0x00ad << 2) + 0xfe025000)
+#define DMC_SEC_RANGE7_WID_CTRL4 ((0x00ae << 2) + 0xfe025000)
+#define DMC_SEC_RANGE8_WID_CTRL0 ((0x00b0 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE8_WID_CTRL1 ((0x00b1 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE8_WID_CTRL2 ((0x00b2 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE8_WID_CTRL3 ((0x00b3 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE8_WID_CTRL4 ((0x00b4 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE9_WID_CTRL0 ((0x00b6 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE9_WID_CTRL1 ((0x00b7 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE9_WID_CTRL2 ((0x00b8 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE9_WID_CTRL3 ((0x00b9 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE9_WID_CTRL4 ((0x00ba << 2) + 0xfe025000)
+#define DMC_SEC_RANGE10_WID_CTRL0 ((0x00bc << 2) + 0xfe025000)
+#define DMC_SEC_RANGE10_WID_CTRL1 ((0x00bd << 2) + 0xfe025000)
+#define DMC_SEC_RANGE10_WID_CTRL2 ((0x00be << 2) + 0xfe025000)
+#define DMC_SEC_RANGE10_WID_CTRL3 ((0x00bf << 2) + 0xfe025000)
+#define DMC_SEC_RANGE10_WID_CTRL4 ((0x00c0 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE11_WID_CTRL0 ((0x00c2 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE11_WID_CTRL1 ((0x00c3 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE11_WID_CTRL2 ((0x00c4 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE11_WID_CTRL3 ((0x00c5 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE11_WID_CTRL4 ((0x00c6 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE12_WID_CTRL0 ((0x00c8 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE12_WID_CTRL1 ((0x00c9 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE12_WID_CTRL2 ((0x00ca << 2) + 0xfe025000)
+#define DMC_SEC_RANGE12_WID_CTRL3 ((0x00cb << 2) + 0xfe025000)
+#define DMC_SEC_RANGE12_WID_CTRL4 ((0x00cc << 2) + 0xfe025000)
+#define DMC_SEC_RANGE13_WID_CTRL0 ((0x00ce << 2) + 0xfe025000)
+#define DMC_SEC_RANGE13_WID_CTRL1 ((0x00cf << 2) + 0xfe025000)
+#define DMC_SEC_RANGE13_WID_CTRL2 ((0x00d0 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE13_WID_CTRL3 ((0x00d1 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE13_WID_CTRL4 ((0x00d2 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE14_WID_CTRL0 ((0x00d4 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE14_WID_CTRL1 ((0x00d5 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE14_WID_CTRL2 ((0x00d6 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE14_WID_CTRL3 ((0x00d7 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE14_WID_CTRL4 ((0x00d8 << 2) + 0xfe025000)
+#define DMC_SEC_RANGE15_WID_CTRL0 ((0x00da << 2) + 0xfe025000)
+#define DMC_SEC_RANGE15_WID_CTRL1 ((0x00db << 2) + 0xfe025000)
+#define DMC_SEC_RANGE15_WID_CTRL2 ((0x00dc << 2) + 0xfe025000)
+#define DMC_SEC_RANGE15_WID_CTRL3 ((0x00dd << 2) + 0xfe025000)
+#define DMC_SEC_RANGE15_WID_CTRL4 ((0x00de << 2) + 0xfe025000)
+#define DMC_DES_PADDING ((0x00e0 << 2) + 0xfe025000)
+ //bit 31:0 | 0 | des_pading | 32bits address padding used for DES dkey generation.
+#define DMC_DES_CTRL ((0x00e1 << 2) + 0xfe025000)
+ //bit 31 : range15_des_en policy : 1 range15_des_en = range15_local_des_en && GLOBAL_DES_EN. 0 : range15_des_en = range15_local_des_en || GLOBAL_DES_EN.
+ //bit 30 : range14_des_en policy : 1 range14_des_en = range14_local_des_en && GLOBAL_DES_EN. 0 : range14_des_en = range14_local_des_en || GLOBAL_DES_EN.
+ //bit 29 : range13_des_en policy : 1 range13_des_en = range13_local_des_en && GLOBAL_DES_EN. 0 : range13_des_en = range13_local_des_en || GLOBAL_DES_EN.
+ //bit 28 : range12_des_en policy : 1 range12_des_en = range12_local_des_en && GLOBAL_DES_EN. 0 : range12_des_en = range12_local_des_en || GLOBAL_DES_EN.
+ //bit 27 : range11_des_en policy : 1 range11_des_en = range11_local_des_en && GLOBAL_DES_EN. 0 : range11_des_en = range11_local_des_en || GLOBAL_DES_EN.
+ //bit 26 : range10_des_en policy : 1 range11_des_en = range10_local_des_en && GLOBAL_DES_EN. 0 : range10_des_en = range10_local_des_en || GLOBAL_DES_EN.
+ //bit 25 : range9_des_en policy : 1 range9_des_en = range9_local_des_en && GLOBAL_DES_EN. 0 : range9_des_en = range9_local_des_en || GLOBAL_DES_EN.
+ //bit 24 : range8_des_en policy : 1 range8_des_en = range8_local_des_en && GLOBAL_DES_EN. 0 : range8_des_en = range8_local_des_en || GLOBAL_DES_EN.
+ //bit 23 : range7_des_en policy : 1 range7_des_en = range7_local_des_en && GLOBAL_DES_EN. 0 : range7_des_en = range7_local_des_en || GLOBAL_DES_EN.
+ //bit 22 : range6_des_en policy : 1 range6_des_en = range6_local_des_en && GLOBAL_DES_EN. 0 : range6_des_en = range6_local_des_en || GLOBAL_DES_EN.
+ //bit 21 : range5_des_en policy : 1 range5_des_en = range5_local_des_en && GLOBAL_DES_EN. 0 : range5_des_en = range5_local_des_en || GLOBAL_DES_EN.
+ //bit 20 : range4_des_en policy : 1 range4_des_en = range4_local_des_en && GLOBAL_DES_EN. 0 : range4_des_en = range4_local_des_en || GLOBAL_DES_EN.
+ //bit 19 : range3_des_en policy : 1 range3_des_en = range3_local_des_en && GLOBAL_DES_EN. 0 : range3_des_en = range3_local_des_en || GLOBAL_DES_EN.
+ //bit 18 : range2_des_en policy : 1 range2_des_en = range2_local_des_en && GLOBAL_DES_EN. 0 : range2_des_en = range2_local_des_en || GLOBAL_DES_EN.
+ //bit 17 : range1_des_en policy : 1 range1_des_en = range1_local_des_en && GLOBAL_DES_EN. 0 : range1_des_en = range1_local_des_en || GLOBAL_DES_EN.
+ //bit 16 : range0_des_en policy : 1 range0_des_en = range0_local_des_en && GLOBAL_DES_EN. 0 : range0_des_en = range0_local_des_en || GLOBAL_DES_EN.
+ //bit 1 | 0 | GLOBAL_DES_EN | 1: Global DES enable. 0 : global DES disable. default is 0.
+ //bit 0 | 0 | DES_lock | one time lock bit. after write 1 to this bit, DMC_DES_CTRL,DMC_DES_PADDING can't be write and read.
+//DES KEY register can only be reset by pad reset. But it can be changed by software after watch dog reset.
+#define DMC_DES_KEY0_REG0 ((0x00e2 << 2) + 0xfe025000)
+#define DMC_DES_KEY0_REG1 ((0x00e3 << 2) + 0xfe025000)
+#define DMC_DES_KEY0_REG2 ((0x00e4 << 2) + 0xfe025000)
+#define DMC_DES_KEY0_REG3 ((0x00e5 << 2) + 0xfe025000)
+#define DMC_DES_KEY1_REG0 ((0x00e6 << 2) + 0xfe025000)
+#define DMC_DES_KEY1_REG1 ((0x00e7 << 2) + 0xfe025000)
+#define DMC_DES_KEY1_REG2 ((0x00e8 << 2) + 0xfe025000)
+#define DMC_DES_KEY1_REG3 ((0x00e9 << 2) + 0xfe025000)
+//FROM SC2, the APB bus provided Master ID through PUSER signals.
+//there's total 8 master IDs could access DMC non-secure registers.
+//we assign 1 control bit for each APB Master and each DMC non-secure register domains
+#define DDR_APB_SEC_CTRL0 ((0x00f0 << 2) + 0xfe025000)
+ // APB access control for dmc REQUEST control register access control register.
+ // default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL1 ((0x00f1 << 2) + 0xfe025000)
+ // APB access control for DMC DRAM timing parameter and DFI inteface registers.
+ //default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL2 ((0x00f2 << 2) + 0xfe025000)
+ // APB access control for DMC PLL clock frequency control regsiter.
+ //default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL3 ((0x00f3 << 2) + 0xfe025000)
+ // APB access control for DMC sticky control regsiter.
+ //default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL4 ((0x00f4 << 2) + 0xfe025000)
+ // APB access control for DMC test control regsiter.
+ //default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL5 ((0x00f5 << 2) + 0xfe025000)
+ // APB access control for DMC clk reset control regsiter.
+ //default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL6 ((0x00f6 << 2) + 0xfe025000)
+ // APB access control for DMC protection regsiter.
+ //default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL7 ((0x00f7 << 2) + 0xfe025000)
+ // APB access control for DMC normal regsiter.
+ //default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL8 ((0x00f8 << 2) + 0xfe025000)
+ // APB access control for DDR PHY group 0 regsiters.
+ //default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL9 ((0x00f9 << 2) + 0xfe025000)
+ // APB access control for DDR PHY group 1 regsiters.
+ //default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+//registers to check the security protection and watch point error information.
+#define DMC_SEC_STATUS ((0x00fa << 2) + 0xfe025000)
+ //bit 31~2. not used.
+ //bit 6
+ //bit 5
+ //bit 4
+ //bit 3 1 : normal security register write violation.( APB bus WDATA not equre the register value when APB write). write 1 to clean this bit to 0.
+ //bit 2 sec_alert. 1 DMC secruity register alert function triggered. can't clean. only reset DMC can clear this bit.
+ //bit 1 write security violation.
+ //bit 0. read security violation.
+#define DMC_VIO_ADDR0 ((0x00fb << 2) + 0xfe025000)
+ //ddr0 write secure violation address.
+#define DMC_VIO_ADDR1 ((0x00fc << 2) + 0xfe025000)
+ //bit 31:24 . not used. always 0.
+ //24 ddr0 secure check violation.
+ //23 not used.
+ //22 not used.
+ //21 not used.
+ //20. not used.
+ //19 ddr0 write address overflow. write out of DDR size.
+ //18:16. ddr0 write violation AWPROT bits.
+ //15:0 ddr0_write violation ID.
+#define DMC_VIO_ADDR2 ((0x00fd << 2) + 0xfe025000)
+ //ddr0 read seure violation address
+#define DMC_VIO_ADDR3 ((0x00fe << 2) + 0xfe025000)
+ //24 ddr0 read secure check violation.
+ //23 not used.
+ //22 not used.
+ //21 ddr0 read trap1 violation
+ //20 ddr0 read trap0 violation
+ //19 ddr 0 read address overflow. write out of DDR size.
+ //18:16. ddr 0 read violation ARPROT bits.
+ //15:0 ddr 0 read violation ID.
+#define DMC_DDR_CTRL ((0x0100 << 2) + 0xfe025000)
+ //bit 24:22 3'b000 : ddr3 mode.
+ //3'b001 : ddr4 mode.
+ //3'b010 : lpddr3 mode.
+ //3'b011 : lpddr4 mode.
+ //bit 21. rank1 enable bit. if 1, rank1 used the address map is as bit 5:3 defined.
+ //bit 20 DDR4 BG1 enable bit.
+ //bit 18: ddrphy_16b, DDR PHY DDR SDRAM data bits width. 1: 16bits. 0 : 32 bits.
+ //bit 16. ddr_16b, 1: only use 16bits data in a 32bits DDR PHY data interface. 0 : normal data interface.
+ //bit 7:4 : ddr1_size. DDR rank1 size control.
+ //4'b0000 : DDR rank 1 is 128Mbyte.
+ //4'b0001 : DDR rank 1 is 256Mbyte.
+ //4'b0010 : DDR rank 1 is 512Mbyte.
+ //4'b0011 : DDR rank 1 is 1Gbyte.
+ //4'b0100 : DDR rank 1 is 2Gbyte.
+ //4'b0101 : DDR rank 1 is 4Gbyte.
+ //4'b1000 : DDR rank 1 is 192Mbyte.
+ //4'b1001 : DDR rank 1 is 374Mbyte.
+ //4'b1010 : DDR rank 1 is 768Mbyte.
+ //4'b1011 : DDR rank 1 is 1.5Gbyte.
+ //4'b1100 : DDR rank 1 is 3Gbyte.
+ //others : reserved.
+ //bit 3:0 : ddr0_size. DDR rank0 size control.
+ //4'b0000 : DDR rank 0 is 128Mbyte.
+ //4'b0001 : DDR rank 0 is 256Mbyte.
+ //4'b0010 : DDR rank 0 is 512Mbyte.
+ //4'b0011 : DDR rank 0 is 1Gbyte.
+ //4'b0100 : DDR rank 0 is 2Gbyte.
+ //4'b0101 : DDR rank 0 is 4Gbyte.
+ //4'b1000 : DDR rank 1 is 192Mbyte.
+ //4'b1001 : DDR rank 1 is 374Mbyte.
+ //4'b1010 : DDR rank 1 is 768Mbyte.
+ //4'b1011 : DDR rank 1 is 1.5Gbyte.
+ //4'b1100 : DDR rank 1 is 3Gbyte.
+ //others : reserved.
+//DDR3/4 LPDDR3/4 SDRAM address to 32bits linear address address map:
+//DDR0_ADDRMAP is used to select RANK0 bank, row, col address selection.
+//DDR1_ADDRMAP is used to select RANK1 bank, row, col address selection.
+#define DDR0_ADDRMAP_0 ((0x0101 << 2) + 0xfe025000)
+ //29:25 ca8.
+ //24:20 ca7.
+ //19:15 ca6.
+ //14:10 ca5.
+ //9:5 ca4.
+ //4:0 ca3.
+#define DDR0_ADDRMAP_1 ((0x0102 << 2) + 0xfe025000)
+ //29:25 ra2.
+ //24:20 ra1.
+ //19:15 ra0.
+ //14:10 ca11.
+ //9:5 ca10.
+ //4:0 ca9.
+#define DDR0_ADDRMAP_2 ((0x0103 << 2) + 0xfe025000)
+ //29:25 ra8.
+ //24:20 ra7.
+ //19:15 ra6.
+ //14:10 ra5.
+ //9:5 ra4.
+ //4:0 ra3.
+#define DDR0_ADDRMAP_3 ((0x0104 << 2) + 0xfe025000)
+ //29:25 ra14.
+ //24:20 ra13.
+ //19:15 ra12.
+ //14:10 ra11.
+ //9:5 ra10.
+ //4:0 ra9.
+#define DDR0_ADDRMAP_4 ((0x0105 << 2) + 0xfe025000)
+ //29:25 ra16 for DDR4 SDRAM
+ //24:20 bg1 for DDR4 SDRAM.
+ //19:15 ba2. or bg0 for DDR4.
+ //14:10 ba1.
+ //9:5 ba0.
+ //4:0 ra15.
+#define DDR1_ADDRMAP_0 ((0x0106 << 2) + 0xfe025000)
+ //29:25 ca8.
+ //24:20 ca7.
+ //19:15 ca6.
+ //14:10 ca5.
+ //9:5 ca4.
+ //4:0 ca3.
+#define DDR1_ADDRMAP_1 ((0x0107 << 2) + 0xfe025000)
+ //29:25 ra2.
+ //24:20 ra1.
+ //19:15 ra0.
+ //14:10 ca11.
+ //9:5 ca10.
+ //4:0 ca9.
+#define DDR1_ADDRMAP_2 ((0x0108 << 2) + 0xfe025000)
+ //29:25 ra8.
+ //24:20 ra7.
+ //19:15 ra6.
+ //14:10 ra5.
+ //9:5 ra4.
+ //4:0 ra3.
+#define DDR1_ADDRMAP_3 ((0x0109 << 2) + 0xfe025000)
+ //29:25 ra14.
+ //24:20 ra13.
+ //19:15 ra12.
+ //14:10 ra11.
+ //9:5 ra10.
+ //4:0 ra9.
+#define DDR1_ADDRMAP_4 ((0x010a << 2) + 0xfe025000)
+ //29:25 ra16 for DDR4 SDRAM
+ //24:20 bg1 for DDR4 SDRAM.
+ //19:15 ba2 or bg0 for DDR4 SDRAM..
+ //14:10 ba1.
+ //9:5 ba0.
+ //4:0 ra15.
+#define DDR_MEM_PD_CTRL ((0x010b << 2) + 0xfe025000)
+ //bit 31:14 not used.
+ //2 bit control for each mem. 00 normal working. 11 power down.
+ //bit 13:12 wc_fifo
+ //bit 11:10 wd_mem
+ //bit 9:8 rd_mem
+ //bit 7:6 dfifo
+ //bit 5:4 cfifo
+ //bit 3:2 cav_ram
+ //bit 1:0 sticky ram
+#define DMC_AXI2DDR0 ((0x0120 << 2) + 0xfe025000)
+ //for AXI address first 256MB AXI ADDRESS[31:28] == 4'b0000.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR1 ((0x0121 << 2) + 0xfe025000)
+ //for AXI_ADDRESS[31:28] == 4'b0001.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR2 ((0x0122 << 2) + 0xfe025000)
+ //for AXI_ADDRESS[31:28] == 4'b0010.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR3 ((0x0123 << 2) + 0xfe025000)
+ //for AXI_ADDRESS[31:28] == 4'b0011.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR4 ((0x0124 << 2) + 0xfe025000)
+ //for AXI_ADDRESS[31:28] == 4'b0100.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR5 ((0x0125 << 2) + 0xfe025000)
+ //for AXI_ADDRESS[31:28] == 4'b0101.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR6 ((0x0126 << 2) + 0xfe025000)
+ //for AXI_ADDRESS[31:28] == 4'b0110.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR7 ((0x0127 << 2) + 0xfe025000)
+ //for AXI_ADDRESS[31:28] == 4'b0111.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR8 ((0x0128 << 2) + 0xfe025000)
+ //for AXI_ADDRESS[31:28] == 4'b1000.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR9 ((0x0129 << 2) + 0xfe025000)
+ //for AXI_ADDRESS[31:28] == 4'b1001.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDRA ((0x012a << 2) + 0xfe025000)
+ //for AXI_ADDRESS[31:28] == 4'b1010.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDRB ((0x012b << 2) + 0xfe025000)
+ //for AXI_ADDRESS[31:28] == 4'b1011.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDRC ((0x012c << 2) + 0xfe025000)
+ //for AXI_ADDRESS[31:28] == 4'b1100.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDRD ((0x012d << 2) + 0xfe025000)
+ //for AXI_ADDRESS[31:28] == 4'b1101.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDRE ((0x012e << 2) + 0xfe025000)
+ //for AXI_ADDRESS[31:28] == 4'b1110.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDRF ((0x012f << 2) + 0xfe025000)
+ //for AXI_ADDRESS[31:28] == 4'b1111.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_DDR_CTRL1 ((0x0130 << 2) + 0xfe025000)
+ //bit 0. DMC_DDR_LOCK. 1: LOCK DMC_DDR_CTRL, DMC_DDR_CTRL1, DMC_AXI2DDRx, DDR0/1_ADDRMAP_x registers. those register can't modified any more.
+ // 0: all these regsiters can be read/write by secure APB access.
+//
+// Closing file: ../mmc_new/dmc/rtl/dmc_sec.vh
+//
+//
+// Reading file: ../mmc_new/dmc/rtl/dmc_test.vh
+//
+// -----------------------------------------------
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfe037800
+// -----------------------------------------------
+// -----------------------------------------------
+//`define DMC_TEST_REG_BASE 32'hfe025800
+#define DMC_TEST_STA ((0x0000 << 2) + 0xfe037800)
+ //test start address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary.
+ // for sha mode, address must be in 64 bytes boundary. that mean the last 6 bits must be 0.
+#define DMC_TEST_EDA ((0x0001 << 2) + 0xfe037800)
+ //test end address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary.
+ // for sha mode, address must be in 64 bytes boundary. that mean the last 6bits must be 1.
+#define DMC_TEST_CTRL ((0x0002 << 2) + 0xfe037800)
+ //bit 31. enable test.
+ //bit 30. when enable test, enable the write to DDR function.
+ //bit 29. when enable test, enable the read from DDR function.
+ //bit 28. when enable test, enable the sha calculation function must be same as read enable but without write function.
+ //bit 27. enabe to compare data. when do the read enable to enable the error comparaion. suppose the read data should be same as the data in the write buffer.
+ //bit 26. 0: save sha result to test_sha_message registers. 1 : don't save.
+ //bit 25. address generation type. 0: continuous increase the address in the range of test start address and test end address.
+ // 1: test module would pick the random address from test start address and test end address.
+ //bit 24. done type. 0 : use the DMC_TEST_NUM register as the counter of test numbers.
+ // for write if the write command number == the DMC_TEST_NUM, the write is done.
+ // for read if the read command number == the DMC TEST_num, the read id done. for one read command can be repeated repeat number times.
+ // 1 : finshed at end address.
+ //bit 23. wdata type. 1 : the first write is {WD3, WD2,WD1,WD0}, then the latter is the previous data plus a pattern.( { + WD7, + WD6, + WD5, + WD4}).
+ // 0 : the WDATA is the data in write register.
+ //bit 23. 1 compare the sha result with the test sha message registers. 0 : dont compare the result.
+ //bit 22:20. read repeat times. for non-sha function, we can define multi times of the read. the test module would repeat the same adddress repeat times.
+ //bit 19. limit write. 0: no outstanding write request limitation.
+ // 1: limit the outstanding write commands to the number of bits [15:8]
+ //bit 18. limit read. 0. no outstanding read request limitation.
+ // 1. limit the read outstanding request to the number of bits[7:0].
+ //bit 17:16. sha mode for sha function enabled. 00 : not used. 01 : sha1. 2: sha2-256. 3: sha2_224. not used in GXL fixed to be Sha 2.
+ //bit 15:8. write outstanding commands limit.
+ //bit 7:0. read outstanding commands limit.
+#define DMC_TEST_NUM ((0x0003 << 2) + 0xfe037800)
+ // how many test command for the test if the DMC_TEST_CTRL bit 24 is 0.
+#define DMC_TEST_WDG ((0x0004 << 2) + 0xfe037800)
+ //31:16. write response watch dog.
+ //15:0. read response watch dog.
+#define DMC_TEST_COMP_MASK ((0x0005 << 2) + 0xfe037800)
+ //32bits for DMC TEST COMPARE bit enable.
+ //1 : to MASK this bit. 0: compare this bit.
+#define DMC_TEST_WSTRB0 ((0x0006 << 2) + 0xfe037800)
+ //MPC WR FIFO command DM bit write data
+ //bit 31:16 the second cycle.
+ //bit 15:0 the first cycle.
+#define DMC_TEST_WSTRB1 ((0x0007 << 2) + 0xfe037800)
+ //MPC WR FIFO command DM bit write data
+ //bit 31:16. the Forth cycle.
+ //bit 15:0. the third cycle.
+#define DMC_TEST_WD0 ((0x0010 << 2) + 0xfe037800)
+ // write data 0 for write command. also for read back data comparision.
+#define DMC_TEST_WD1 ((0x0011 << 2) + 0xfe037800)
+ // write data 1 for write command. also for read back data comparision.
+#define DMC_TEST_WD2 ((0x0012 << 2) + 0xfe037800)
+ // write data 2 for write command. also for read back data comparision.
+#define DMC_TEST_WD3 ((0x0013 << 2) + 0xfe037800)
+ // write data 3 for write command. also for read back data comparision.
+#define DMC_TEST_WD4 ((0x0014 << 2) + 0xfe037800)
+ // write data 4 for write command. also for read back data comparision.
+#define DMC_TEST_WD5 ((0x0015 << 2) + 0xfe037800)
+ // write data 5 for write command. also for read back data comparision.
+#define DMC_TEST_WD6 ((0x0016 << 2) + 0xfe037800)
+ // write data 6 for write command. also for read back data comparision.
+#define DMC_TEST_WD7 ((0x0017 << 2) + 0xfe037800)
+ // write data 7 for write command. also for read back data comparision.
+#define DMC_TEST_WD8 ((0x0018 << 2) + 0xfe037800)
+ // write data 8 for write command. also for read back data comparision.
+#define DMC_TEST_WD9 ((0x0019 << 2) + 0xfe037800)
+ // write data 9 for write command. also for read back data comparision.
+#define DMC_TEST_WD10 ((0x001a << 2) + 0xfe037800)
+ // write data 10 for write command. also for read back data comparision.
+#define DMC_TEST_WD11 ((0x001b << 2) + 0xfe037800)
+ // write data 11 for write command. also for read back data comparision.
+#define DMC_TEST_WD12 ((0x001c << 2) + 0xfe037800)
+ // write data 12 for write command. also for read back data comparision.
+#define DMC_TEST_WD13 ((0x001d << 2) + 0xfe037800)
+ // write data 13 for write command. also for read back data comparision.
+#define DMC_TEST_WD14 ((0x001e << 2) + 0xfe037800)
+ // write data 14 for write command. also for read back data comparision.
+#define DMC_TEST_WD15 ((0x001f << 2) + 0xfe037800)
+ // write data 15 for write command. also for read back data comparision.
+#define DMC_TEST_RD0 ((0x0020 << 2) + 0xfe037800)
+ // the read back data 0. if error happens, it would capture the first error data.
+#define DMC_TEST_RD1 ((0x0021 << 2) + 0xfe037800)
+ // the read back data 1. if error happens, it would capture the first error data.
+#define DMC_TEST_RD2 ((0x0022 << 2) + 0xfe037800)
+ // the read back data 2. if error happens, it would capture the first error data.
+#define DMC_TEST_RD3 ((0x0023 << 2) + 0xfe037800)
+ // the read back data 3. if error happens, it would capture the first error data.
+#define DMC_TEST_RD4 ((0x0024 << 2) + 0xfe037800)
+ // the read back data 4. if error happens, it would capture the first error data.
+#define DMC_TEST_RD5 ((0x0025 << 2) + 0xfe037800)
+ // the read back data 5. if error happens, it would capture the first error data.
+#define DMC_TEST_RD6 ((0x0026 << 2) + 0xfe037800)
+ // the read back data 6. if error happens, it would capture the first error data.
+#define DMC_TEST_RD7 ((0x0027 << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD8 ((0x0028 << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD9 ((0x0029 << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD10 ((0x002a << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD11 ((0x002b << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD12 ((0x002c << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD13 ((0x002d << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD14 ((0x002e << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD15 ((0x002f << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_ERR_ADDR ((0x0040 << 2) + 0xfe037800)
+ //read only. it capature the first error address.
+#define DMC_TEST_ERR_CNT ((0x0041 << 2) + 0xfe037800)
+ //read only. how many data error happens in the whole test period.
+#define DMC_TEST_STS ((0x0042 << 2) + 0xfe037800)
+ //read only.
+ //bit 31, test done bit. write 1 to clean.
+ //bit 30, indicate address err
+ //bit 29~7. not used.
+ //bit 6. read data resp error(caused by security or rd latency).
+ //bit 5. test MRR/MPR rd latency error. write 1 clear
+ //bit 4, sha done. write 1 to clean.
+ //bit 3, write done. write 1 to clean.
+ //bit 2, read done. write 1 to clean
+ //bit 1, write watchdog triggered. write 1 to clean
+ //bit 0, read watchdog triggered. write 1 to clean.
+#define DMC_TEST_WRCMD_ADDR ((0x0043 << 2) + 0xfe037800)
+ //read only. the current write cmd address.
+#define DMC_TEST_RDCMD_ADDR ((0x0044 << 2) + 0xfe037800)
+ //read only. the current read command address.
+#define DMC_TEST_RDRSP_ADDR ((0x0045 << 2) + 0xfe037800)
+ //read only. the failed read response address(for error data )
+//`endif
+//
+// Closing file: ../mmc_new/dmc/rtl/dmc_test.vh
+//
+//
+// Reading file: ../mmc_new/dmc/rtl/dmc_reg.vh
+//
+//`ifdef DMC_REG_DEFINE
+//`else
+//`define DMC_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfe024000
+// -----------------------------------------------
+//`define DMC_REG_BASE 32'hfe024000
+#define DMC_SOFT_RST ((0x0001 << 2) + 0xfe024000)
+ //bit 31~24. reserved for future.
+ //bit 23:16 8 AMBUS input interface n_clk domain reset_n signal. 0 : reset. 1: normal working mode.
+ //bit 15:0. 16 AXI BUS input intefaces n_clk domain reset_n signal. 0: reset. 1: normal working mode. each bit for one interface.
+#define DMC_SOFT_RST1 ((0x0002 << 2) + 0xfe024000)
+ //To reset the Async interface, you need to disable the interface both clock domain, then reset both n_clk and m_clk domain
+ //bit 31~24 not used.
+ //bit 23.16 8 am bus interfaces master clock domain reset_n signal. 0 : reset : 1 normal working mode.
+ //bit 15:0. 16 AXI bus interfaces master clock domain reset_n signal. 0 : reset : 1 normal working mode.
+#define DMC_SOFT_RST2 ((0x0003 << 2) + 0xfe024000)
+ //bit 31~11. reserved for future.
+ //bit 10 DMC DFI cmd soft reset_n
+ //bit 9 DMC DFI MISC soft reset_n
+ //bit 8 DMC DFI data soft reset_n
+ //bit 7 DMC DFI dcu soft reset_n
+ //bit 6 DMC siu soft reset_n
+ //bit 5. DMC test soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 4. DMC low power control moudle soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 3. DMC QOS monitor module soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 2. DMC register modle soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 1. DMC canvas transfer module soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 0. DMC command buffers and command generation modules soft reset. 0 = reset. 1:
+#define DMC_RST_STS1 ((0x0004 << 2) + 0xfe024000)
+ //31~24. not used.
+ //23~0. Read only. the DMC_SOFT_RST1 signal in n_clk domain. the purpose of this register is when one of the 2 clocks is too slow or too fast, we can read this register to make sure another clock domain reset is done.
+#define DMC_CLKG_CTRL0 ((0x0006 << 2) + 0xfe024000)
+ //bit 23:16. enable the 8 ambus interfaces both main and n_clk auto clock gating function. each 1 bit for one interface.
+ //bit 15:0. enable the 16 axi interfaces both main and n_clk auto clock gating function. each 1 bit for one interface.
+#define DMC_CLKG_CTRL1 ((0x0007 << 2) + 0xfe024000)
+ //bit 23:16. force to disable the 8 ambus interfaces both main and n_clk. each 1 bit for one interface.
+ //bit 15:0. force to disable the 16 axi interfaces both main and n_clk. each 1 bit for one interface.
+#define DMC_CLKG_CTRL2 ((0x0008 << 2) + 0xfe024000)
+ //bit 12 enalbe auto clock gating for awcmdfifo.
+ //bit 11 enalbe auto clock gating for arcmdfifo.
+ //bit 10 enable auto clock gating for dfi command generation
+ //bit 9 enable auto clock gating for dram cntroller
+ //bit 8 enable auto clock gating for dfi data path.
+ //bit 7. enalbe auto clock gating for write rsp generation.
+ //bit 6. enalbe auto clock gating for read rsp generation.
+ //bit 5. enalbe auto clock gating for ddr0 command filter.
+ //bit 4. enalbe auto clock gating for ddr0 write reorder buffer.
+ //bit 3. enalbe auto clock gating for ddr0 write data buffer.
+ //bit 2. enalbe auto clock gating for ddr0 read reorder buffer.
+ //bit 1. enalbe auto clock gating for read canvas.
+ //bit 0. enalbe auto clock gating for write canvas.
+#define DMC_CLKG_CTRL3 ((0x0009 << 2) + 0xfe024000)
+ //bit 12 force to disable the clock of awcmdfifo.
+ //bit 11 force to disable the clock of arcmdfifo.
+ //bit 10 force to disable the clock of dfi command generation
+ //bit 9 force to disable the clock of dram cntroller
+ //bit 8 force to disable the clock of dfi data path.
+ //bit 7. force to disalbe the clock of write rsp generation.
+ //bit 6. force to disalbe the clock of read rsp generation.
+ //bit 5. force to disalbe the clock of command filter.
+ //bit 4. force to disalbe the clock of write reorder buffer.
+ //bit 3. force to disalbe the clock of write data buffer.
+ //bit 2. force to disalbe the clock of read reorder buffer.
+ //bit 1. force to disalbe the clock of read canvas.
+ //bit 0. force to disalbe the clock of write canvas.
+#define DMC_VERSION ((0x0010 << 2) + 0xfe024000)
+ //read only 32'h000a0006. for TM2_REVB
+#define DMC_MON_CTRL0 ((0x0020 << 2) + 0xfe024000)
+ //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
+ //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
+ //bit 3. qos monitor 3 enable.
+ //bit 2. qos monitor 2 enable.
+ //bit 1. qos monitor 1 enable.
+ //bit 0. qos monitor 0 enable.
+#define DMC_MON_CTRL1 ((0x0021 << 2) + 0xfe024000)
+ //enable to check which modules bandwidth in QOS monitor 0
+ //32bits for 32 different ID protection.
+ //bit 24. prot_en for all undefined IDs.
+ //bit 23. prot_en for SDEMMC_C
+ //bit 22. prot_en for DMA
+ //bit 21. prot_en for AUDIO
+ //bit 20. prot_en for SDEMMC_B
+ //bit 19. prot_en for SDEMMC_A
+ //bit 18. prot_en for SPICC_B
+ //bit 17. prot_en for SPICC_A
+ //bit 16. prot_en for ETH
+ //bit 15. prot_en for DMC TEST
+ //bit 14. prot_en for VAD
+ //bit 13. prot_en for NNA
+ //bit 12. prot_en for ISP
+ //bit 11. prot_en for USB Host
+ //bit 10. prot_en for USB Devi
+ //bit 9. prot_en for GE2D SRC1
+ //bit 8. prot_en for GE2D SRC0/DEST
+ //bit 7. prot_en for GDC
+ //bit 6. prot_en for WAVE
+ //bit 5. prot_en for JPEG
+ //bit 4. prot_en for DSPA
+ //bit 3. prot_en for RICV
+ //bit 2. prot_en for JTAG/PROD
+ //bit 1. prot_en for REE
+ //bit 0. prot_en for TEE
+#define DMC_MON_CTRL2 ((0x0022 << 2) + 0xfe024000)
+ //not used in C2
+#define DMC_MON_CTRL3 ((0x0023 << 2) + 0xfe024000)
+ //enable to check which modules bandwidth in QOS monitor 1
+ //32bits for 32 different ID protection.
+ //bit 24. prot_en for all undefined IDs.
+ //bit 23. prot_en for SDEMMC_C
+ //bit 22. prot_en for DMA
+ //bit 21. prot_en for AUDIO
+ //bit 20. prot_en for SDEMMC_B
+ //bit 19. prot_en for SDEMMC_A
+ //bit 18. prot_en for SPICC_B
+ //bit 17. prot_en for SPICC_A
+ //bit 16. prot_en for ETH
+ //bit 15. prot_en for DMC TEST
+ //bit 14. prot_en for VAD
+ //bit 13. prot_en for NNA
+ //bit 12. prot_en for ISP
+ //bit 11. prot_en for USB Host
+ //bit 10. prot_en for USB Devi
+ //bit 9. prot_en for GE2D SRC1
+ //bit 8. prot_en for GE2D SRC0/DEST
+ //bit 7. prot_en for GDC
+ //bit 6. prot_en for WAVE
+ //bit 5. prot_en for JPEG
+ //bit 4. prot_en for DSPA
+ //bit 3. prot_en for RICV
+ //bit 2. prot_en for JTAG/PROD
+ //bit 1. prot_en for REE
+ //bit 0. prot_en for TEE
+#define DMC_MON_CTRL4 ((0x0024 << 2) + 0xfe024000)
+ //not used in C2
+#define DMC_MON_CTRL5 ((0x0025 << 2) + 0xfe024000)
+ //enable to check which modules bandwidth in QOS monitor 2
+ //32bits for 32 different ID protection.
+ //bit 24. prot_en for all undefined IDs.
+ //bit 23. prot_en for SDEMMC_C
+ //bit 22. prot_en for DMA
+ //bit 21. prot_en for AUDIO
+ //bit 20. prot_en for SDEMMC_B
+ //bit 19. prot_en for SDEMMC_A
+ //bit 18. prot_en for SPICC_B
+ //bit 17. prot_en for SPICC_A
+ //bit 16. prot_en for ETH
+ //bit 15. prot_en for DMC TEST
+ //bit 14. prot_en for VAD
+ //bit 13. prot_en for NNA
+ //bit 12. prot_en for ISP
+ //bit 11. prot_en for USB Host
+ //bit 10. prot_en for USB Devi
+ //bit 9. prot_en for GE2D SRC1
+ //bit 8. prot_en for GE2D SRC0/DEST
+ //bit 7. prot_en for GDC
+ //bit 6. prot_en for WAVE
+ //bit 5. prot_en for JPEG
+ //bit 4. prot_en for DSPA
+ //bit 3. prot_en for RICV
+ //bit 2. prot_en for JTAG/PROD
+ //bit 1. prot_en for REE
+ //bit 0. prot_en for TEE
+#define DMC_MON_CTRL6 ((0x0026 << 2) + 0xfe024000)
+ //not USED in C2
+#define DMC_MON_CTRL7 ((0x0027 << 2) + 0xfe024000)
+ //enable to check which modules bandwidth in QOS monitor 3
+ //32bits for 32 different ID protection.
+ //bit 24. prot_en for all undefined IDs.
+ //bit 23. prot_en for SDEMMC_C
+ //bit 22. prot_en for DMA
+ //bit 21. prot_en for AUDIO
+ //bit 20. prot_en for SDEMMC_B
+ //bit 19. prot_en for SDEMMC_A
+ //bit 18. prot_en for SPICC_B
+ //bit 17. prot_en for SPICC_A
+ //bit 16. prot_en for ETH
+ //bit 15. prot_en for DMC TEST
+ //bit 14. prot_en for VAD
+ //bit 13. prot_en for NNA
+ //bit 12. prot_en for ISP
+ //bit 11. prot_en for USB Host
+ //bit 10. prot_en for USB Devi
+ //bit 9. prot_en for GE2D SRC1
+ //bit 8. prot_en for GE2D SRC0/DEST
+ //bit 7. prot_en for GDC
+ //bit 6. prot_en for WAVE
+ //bit 5. prot_en for JPEG
+ //bit 4. prot_en for DSPA
+ //bit 3. prot_en for RICV
+ //bit 2. prot_en for JTAG/PROD
+ //bit 1. prot_en for REE
+ //bit 0. prot_en for TEE
+#define DMC_MON_CTRL8 ((0x0028 << 2) + 0xfe024000)
+ //not used.
+#define DMC_MON_ALL_REQ_CNT ((0x0029 << 2) + 0xfe024000)
+ // at the test period, the whole MMC request time.
+#define DMC_MON_ALL_GRANT_CNT ((0x002a << 2) + 0xfe024000)
+ // at the test period, the whole MMC granted data cycles. 64bits unit.
+#define DMC_MON_ONE_GRANT_CNT ((0x002b << 2) + 0xfe024000)
+ // at the test period, the granted data cycles for the selected channel and ports.
+#define DMC_MON_SEC_GRANT_CNT ((0x002c << 2) + 0xfe024000)
+ // at the test period, the granted data cycles for the selected channel and ports.
+#define DMC_MON_THD_GRANT_CNT ((0x002d << 2) + 0xfe024000)
+ // at the test period, the granted data cycles for the selected channel and ports.
+#define DMC_MON_FOR_GRANT_CNT ((0x002e << 2) + 0xfe024000)
+ // at the test period, the granted data cycles for the selected channel and ports.
+#define DMC_MON_TIMER ((0x002f << 2) + 0xfe024000)
+ // timer for the monitor period.
+#define DMC_IRQ_STS ((0x0030 << 2) + 0xfe024000)
+ //bit 31:3 Not used.
+ //bit 2 : QOS Monitor interrupt flag. 1: means there's QOS monitor interrup. write 1 to clean this interrupt.
+ //bit 1 : WRITE protection interrupt. 1: means there's write protection violation. need to write DMC_PROT_IRQ_CTRL bit 1to clean this bit.
+ //bit 0 : read protection interrupt. 1: means there's read protection violation. need to write DMC_PROT_IRQ_CTRL bit 0 to clean this bit.
+#define DMC_AXI0_HOLD_CTRL ((0x0031 << 2) + 0xfe024000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI5_HOLD_CTRL ((0x0035 << 2) + 0xfe024000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_CHAN_STS ((0x003c << 2) + 0xfe024000)
+ //bit 4 always 1
+ //bit 3 ddr0 write data buffer idle. 1 : idle 0: busy.
+ //bit 2 always 1.
+ //bit 1 ddr0 wbuf idle. 1 : idle 0: busy.
+ //bit 0. axi0 channel idle. 1 : idle 0: busy.
+#define DMC_CMD_FILTER_CTRL1 ((0x0040 << 2) + 0xfe024000)
+ //not used.
+#define DMC_CMD_FILTER_CTRL2 ((0x0041 << 2) + 0xfe024000)
+ //31:24. keep the bank active if there's urgent level 3 read bank hit request.
+ //23:16. keep the bank active if there's urgent level 2 read bank hit request.
+ //15:8. keep the bank active if there's urgent level 1 read bank hit request.
+ //7:0. keep the bank active if there's urgent level 0 read bank hit request.
+#define DMC_CMD_FILTER_CTRL3 ((0x0042 << 2) + 0xfe024000)
+ //bit 31. force wbuf empty.
+ //bit 30:26 wbuf high level number
+ //bit 25:21 wbuf mid level number
+ //bit 20:16 wbuf low level number
+ //bit 14:10 rbuf high level number
+ //bit 9:5 rbuf middle level number
+ //bit 4:0 rbuf low level number
+#define DMC_CMD_FILTER_CTRL4 ((0x0043 << 2) + 0xfe024000)
+ //bit 29:25. tITW.long
+ //bit 24:20. tITW. short
+ //bit 19:12 tAP auto precharge the bank not used if idle that long time.
+ //bit 11:6 write to read accesses if there write hit request.
+ //bit 5:0 read to write accesses if there write hit request.
+#define DMC_CMD_FILTER_CTRL5 ((0x0044 << 2) + 0xfe024000)
+ //bit 31:24 Once ddr data bus switch to read, the maxmum read command number to give up the bus when there's write request pending for write buffer.
+ //bit 23:16 Once ddr data bus switch to write, the maxmum write command number to give up the bus when there's read request pending too long.
+ //bit 15:8. Once ddr data bus switch to read, the minimum read command number to transfer back to write stage if there's still pending read request.
+ //bit 7:0. Once ddr data bus switch to write, the minimum write command number to transfer back to read stage if there's still pending write request.
+#define DMC_CMD_FILTER_CTRL6 ((0x0045 << 2) + 0xfe024000)
+ //bit 31:24 write urgent 3 request pending hold num.
+ //bit 23:16 write urgent 2 request pending hold num.
+ //bit 15:8. write urgent 1 request pending hold num.
+ //bit 7:0. write urgent 0 request pending hold num.
+#define DMC_CMD_FILTER_CTRL7 ((0x0046 << 2) + 0xfe024000)
+ //bit 31:24. aw_req_pedning singal assertion after wbuf full.
+ //bit 23:16 aw_req_pending singal hold how long if wbuf not full.
+ //bit 15:8 write to read waiting cycles if there write hit request.
+ //bit 7:0 read to write waiting cycles if there write hit request.
+#define DMC_CMD_FILTER_CTRL8 ((0x0047 << 2) + 0xfe024000)
+ //bit 31:8 reserved.
+ //bit 7:0 rank limit to change to another rank.
+#define DMC_CMD_BUFFER_CTRL ((0x0048 << 2) + 0xfe024000)
+ //bit 31:26 total write buffer number. default 32.
+ //bit 25:20 total read buffer number. default 32.
+ //bit 19:14 reserved.
+ //bit 13:8 wr cmd fifo depth
+ //bit 7:0 aw_pending_inc_num. incease write ugent level 1 when write command waiting to in write buffer that long.
+#define DMC_CMD_BUFFER_CTRL1 ((0x0049 << 2) + 0xfe024000)
+ //bit 29:24 read buffer number in non-urgent request.
+ //bit 23:16 read buffer bank miss watch dog threshold.
+ //bit 15:12 read buffer urgent level 3 counter inc weight.
+ //bit 11:8 read buffer urgent level 2 counter inc weight.
+ //bit 7:4 read buffer urgent level 1 counter inc weight.
+ //bit 3:0 read buffer urgent level 0 counter inc weight.
+#define DMC_AXI0_CHAN_CTRL ((0x0080 << 2) + 0xfe024000)
+ //bit 31 AXI interface request enable.
+ //bit 19 AXI interface auto clock gating enable. 1: enable; 0 disable.
+ //bit 18 AXI interface clock disable. 1 : disable clock. 0 enable clock.
+ //bit 17 AXI interface dmc clock domain soft reset. 0 : reset. 1 : normal working mode.
+ //bit 16 AXI interface s0 clock domain soft reset. 0 : reset. 1 : normal working mode.
+ //bit 15:12 ugt3 QOS level.
+ //bit 11:8 ugt2 QOS level.
+ //bit 7:4 ugt1 QOS level.
+ //bit 3:0 not used.
+#define DMC_PROT0_RANGE ((0x0090 << 2) + 0xfe024000)
+ //protection 0 address range. the range define is 64Kbyte boundary. current address [31:16] >= start address && current address [31:16] <= end address.
+ //bit 31:16 : range end address.
+ //bit 15:0 : range start address
+#define DMC_PROT0_CTRL ((0x0091 << 2) + 0xfe024000)
+ //32bits for 32 different ID protection.
+ //bit 24. prot_en for all undefined IDs.
+ //bit 23. prot_en for SDEMMC_C
+ //bit 22. prot_en for DMA
+ //bit 21. prot_en for AUDIO
+ //bit 20. prot_en for SDEMMC_B
+ //bit 19. prot_en for SDEMMC_A
+ //bit 18. prot_en for SPICC_B
+ //bit 17. prot_en for SPICC_A
+ //bit 16. prot_en for ETH
+ //bit 15. prot_en for DMC TEST
+ //bit 14. prot_en for VAD
+ //bit 13. prot_en for NNA
+ //bit 12. prot_en for ISP
+ //bit 11. prot_en for USB Host
+ //bit 10. prot_en for USB Devi
+ //bit 9. prot_en for GE2D SRC1
+ //bit 8. prot_en for GE2D SRC0/DEST
+ //bit 7. prot_en for GDC
+ //bit 6. prot_en for WAVE
+ //bit 5. prot_en for JPEG
+ //bit 4. prot_en for DSPA
+ //bit 3. prot_en for RICV
+ //bit 2. prot_en for JTAG/PROD
+ //bit 1. prot_en for REE
+ //bit 0. prot_en for TEE
+#define DMC_PROT0_CTRL1 ((0x0092 << 2) + 0xfe024000)
+ //bit 26. protection 0 read access protection enable.
+ //bit 25. protection 0 write access block function. if enabled, the access wouldn't write to the DDR SDRAM. if not enabled only generate a interrupt, but the access still wrote to DDR.
+ //bit 24. protection range 0 write access protection enable.
+#define DMC_PROT1_RANGE ((0x0093 << 2) + 0xfe024000)
+ //protection 1 address range. the range define is 64Kbyte boundary. current address [31:16] >= start address && current address [31:16] <= end address.
+ //bit 31:16 : range end address.
+ //bit 15:0 : range start address
+#define DMC_PROT1_CTRL ((0x0094 << 2) + 0xfe024000)
+ //32bits for 32 different ID protection.
+ //bit 24. prot_en for all undefined IDs.
+ //bit 23. prot_en for SDEMMC_C
+ //bit 22. prot_en for DMA
+ //bit 21. prot_en for AUDIO
+ //bit 20. prot_en for SDEMMC_B
+ //bit 19. prot_en for SDEMMC_A
+ //bit 18. prot_en for SPICC_B
+ //bit 17. prot_en for SPICC_A
+ //bit 16. prot_en for ETH
+ //bit 15. prot_en for DMC TEST
+ //bit 14. prot_en for VAD
+ //bit 13. prot_en for NNA
+ //bit 12. prot_en for ISP
+ //bit 11. prot_en for USB Host
+ //bit 10. prot_en for USB Devi
+ //bit 9. prot_en for GE2D SRC1
+ //bit 8. prot_en for GE2D SRC0/DEST
+ //bit 7. prot_en for GDC
+ //bit 6. prot_en for WAVE
+ //bit 5. prot_en for JPEG
+ //bit 4. prot_en for DSPA
+ //bit 3. prot_en for RICV
+ //bit 2. prot_en for JTAG/PROD
+ //bit 1. prot_en for REE
+ //bit 0. prot_en for TEE
+#define DMC_PROT1_CTRL1 ((0x0095 << 2) + 0xfe024000)
+ //bit 26. protection range 1 read access protection enable bit.
+ //bit 25. protection 1 write access block function. if enabled, the access wouldn't write to the DDR SDRAM. if not enabled only generate a interrupt, but the access still wrote to DDR.
+ //bit 24. protection range 1 write access protection enable bit.
+#define DMC_PROT_VIO_0 ((0x0096 << 2) + 0xfe024000)
+ //ddr0 write proection violation address.
+#define DMC_PROT_VIO_1 ((0x0097 << 2) + 0xfe024000)
+ //31 ddr0 protection 1 vilation.
+ //30 ddr0 protection 0 vilation.
+ //29 not used.
+ //28:26. ddr0 write violation AWPROT bits.
+ //25:16. ddr0_write AWUSER[9:0];
+ //15:0 ddr0_write violation ID.
+#define DMC_PROT_VIO_2 ((0x0098 << 2) + 0xfe024000)
+ //ddr0 read prot violation address
+#define DMC_PROT_VIO_3 ((0x0099 << 2) + 0xfe024000)
+ //bit 31:21 . not used. always 0.
+ //20 ddr0 read protection 1 violation.
+ //19 ddr0 read protection 0 violation.
+ //18:16. ddr0 read violation ARPROT bits.
+ //15:0 ddr0 read violation ID.
+#define DMC_PROT_IRQ_CTRL ((0x009a << 2) + 0xfe024000)
+ //bit 2 : protect function IRQ enable.
+ //bit 1 : write protection violation. write 1 to clean write protection vio registers.
+ //bit 0 : read protection violation. write 1 to clean read protection vio registers.
+//`endif
+//
+// Closing file: ../mmc_new/dmc/rtl/dmc_reg.vh
+//
+//
+// Reading file: ../mmc_new/dmc/rtl/dmc_siu_reg.vh
+//
+//`ifdef DMC_SIU_REG_DEFINE
+//`else
+//`define DMC_SIU_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfe024400
+// -----------------------------------------------
+//`define DMC_DRAM_REG_BASE 32'hfe024400
+//there's 2 set of timing DDR timing parameter for 2 set of DDR freqency parameter.
+//when change frequency, the hardware would automatically select one of these two set of timing parameter
+//DMC_DRAM_* is for Frequency set 0.
+//DMC_NFQ_* is for Freqency set 1.
+#define DMC_DRAM_TMRD ((0x0000 << 2) + 0xfe024400)
+ //bit 4:0. tMRD. //MR command cycles, in DDR3/4. in LPDDR4, it should be value of tMRW
+#define DMC_DRAM_TRFC ((0x0001 << 2) + 0xfe024400)
+ //bit 9:0 tRFC
+#define DMC_DRAM_TRP ((0x0002 << 2) + 0xfe024400)
+ //bit 21:16. tRP for precharge all banks.
+ //bit 5:0. tRP for precharge one bank.
+#define DMC_DRAM_TRTW ((0x0003 << 2) + 0xfe024400)
+ //bit 5:0 tRTW
+ //In LPDDR4 . the total read command -> write command = RL +DQSCK_MAX + BL/2 - tODT_on + tWPRE +RD(tRPST) + tODT_on.
+ // tRTW = TDQSCK_MAX + tWPRE + tRD(tRPST) tODT_on + (delay margin)
+ //In DDR4 mode.
+#define DMC_DRAM_TCL ((0x0004 << 2) + 0xfe024400)
+ //bit 5:0 tCL/tRL. read latency.
+#define DMC_DRAM_TCWL ((0x0005 << 2) + 0xfe024400)
+ //bit 5:0. CWL: write latency.
+#define DMC_DRAM_TRAS ((0x0006 << 2) + 0xfe024400)
+ //bit 7:0. tRAS. minimum active to precharge time for same bank.
+#define DMC_DRAM_TRC ((0x0007 << 2) + 0xfe024400)
+ //bit 7:0. tRC. minimum active to active time for same bank.
+#define DMC_DRAM_TRCD ((0x0008 << 2) + 0xfe024400)
+ //bit 7:0 tRCD active to read/write timing for same bank.
+#define DMC_DRAM_TRRD ((0x0009 << 2) + 0xfe024400)
+ //bit 21:16. tRRD_l active bank A to active B in same band group for DDR4.
+ //bit 5:0. tRRD/tRRD_s active bank A to active bank b time.
+ //tRRD_s: active bank A to active bank b in different bank grousp for DDR4.
+#define DMC_DRAM_TFAW ((0x000a << 2) + 0xfe024400)
+ //bit 8:0 tFAW. four active command windows
+#define DMC_DRAM_TRTP ((0x000b << 2) + 0xfe024400)
+ //bit 5:0 tRTP.
+#define DMC_DRAM_TWR ((0x000c << 2) + 0xfe024400)
+ //bit 5:0 tWR.
+#define DMC_DRAM_TWTR ((0x000d << 2) + 0xfe024400)
+ //bit 5:0 tWTR.
+#define DMC_DRAM_TCCD ((0x000e << 2) + 0xfe024400)
+ //bit 19:16. tCCD/tCCD_l.
+ //bit 3:0 tCCD/tCCD_s read to read command time or write to write command time.
+#define DMC_DRAM_TEXSR ((0x000f << 2) + 0xfe024400)
+ //bit 12:0. tEXSR. EXIT SELF-REFRESH to read/write command.
+#define DMC_DRAM_TXS ((0x0010 << 2) + 0xfe024400)
+ //bit 9:0 tXS. EXIT SELF_REFRESH to other command time
+#define DMC_DRAM_TXP ((0x0011 << 2) + 0xfe024400)
+ //bit 3:0. tXP. EXIT power down to other command time
+#define DMC_DRAM_TXPDLL ((0x0012 << 2) + 0xfe024400)
+ //bit 12:0. tXPDLL, EXIT power down to read/write command time(need to relock PLL).
+#define DMC_DRAM_TZQCS ((0x0013 << 2) + 0xfe024400)
+ //bit 11:0. ZQCS command to other command time.
+#define DMC_DRAM_TCKSRE ((0x0014 << 2) + 0xfe024400)
+ //bit 4:0. enter self refresh to disable clock time.
+#define DMC_DRAM_TCKSRX ((0x0015 << 2) + 0xfe024400)
+ //bit 4:0. enable clock to exit self refresh time.
+#define DMC_DRAM_TCKE ((0x0016 << 2) + 0xfe024400)
+ //bit 4:0. CKE high or low minimum time.
+#define DMC_DRAM_TMOD ((0x0017 << 2) + 0xfe024400)
+ //bit 4:0 tMOD. MRR/MRW to other command time. in LPDDR4, still use this register but it called tMRD.
+#define DMC_DRAM_TDQS ((0x0018 << 2) + 0xfe024400)
+ //bit 31:28 reserved
+ //bit 27:24 tDQS. the delay for write after read in different rank.
+ //bit 23:20 reserved
+ //bit 19:16 tDQS. the delay for read after write in different rank.
+ //bit 15:12 reserved
+ //bit 11:8 tDQS. the delay for write after write in different rank.
+ //bit 7:4 reserved
+ //bit 3:0 tDQS. the delay for read after read in different rank.
+#define DMC_DRAM_TRSTL ((0x0019 << 2) + 0xfe024400)
+ //not used.
+#define DMC_DRAM_TZQLAT ((0x001a << 2) + 0xfe024400)
+ //bit 5:0 ZQ LATCH command to other comand timing in LPDDR4 mode.
+#define DMC_DRAM_TMRR ((0x001b << 2) + 0xfe024400)
+ //bit 7:0 tMRR not used in DMC.
+#define DMC_DRAM_TCKESR ((0x001c << 2) + 0xfe024400)
+ //bit 9:0 tCKESR. CKE low minimum pulse in self refresh mode.
+#define DMC_DRAM_TDPD ((0x001d << 2) + 0xfe024400)
+ //not support.
+#define DMC_DRAM_DFITCTRLDELAY ((0x001e << 2) + 0xfe024400)
+ //bit 3:0. DFI_t_ctrldealy
+#define DMC_DRAM_DFITPHYWRDATA ((0x001f << 2) + 0xfe024400)
+ //bit 5:0. dfi_t_phy_wrdata.
+#define DMC_DRAM_DFITPHYWRLAT ((0x0020 << 2) + 0xfe024400)
+ //bit 5:0. dfi_t_phy_wrlat. in DDR3/4/LPDDR3 mode: WL -5. in LPDDR4 mode: WL -5 + 2.
+#define DMC_DRAM_DFITRDDATAEN ((0x0021 << 2) + 0xfe024400)
+ //bit 5:0. dfi_t_rddata_en. in DDR3/4/LPDDR3 mode: RL -5. in LPDDR4 mode : RL -5 + 1.
+#define DMC_DRAM_DFITPHYRDLAT ((0x0022 << 2) + 0xfe024400)
+ //bit 5:0. dfi_t_rdlat.
+#define DMC_DRAM_DFITCTRLUPDMIN ((0x0023 << 2) + 0xfe024400)
+ //bit 7:0. CTRLUPD_MIN minimux clock cycle to maintain CTRLUPD_REQ.
+#define DMC_DRAM_DFITCTRLUPDMAX ((0x0024 << 2) + 0xfe024400)
+ //bit 7:0 CTRLUPD_MAX. maxmum clock cycle to maintain CTRLUPD_REQ if no CTRLUPD_ACK response.
+#define DMC_DRAM_DFITREFMSKI ((0x0026 << 2) + 0xfe024400)
+ //not used.
+#define DMC_DRAM_DFITCTRLUPDI ((0x0027 << 2) + 0xfe024400)
+ //not used.
+#define DMC_DRAM_DFITDRAMCLK ((0x0028 << 2) + 0xfe024400)
+//bit 17 dram clk1 enable.
+//bit 16 dram clk0 enable.
+//bit 15:8 DRAM CLK disable waiting time
+//bit 7:0 DRAM CLK enable enable timer
+#define DMC_DRAM_DFITLPRESP ((0x002a << 2) + 0xfe024400)
+ //bit 3:0. dfi_lp_ctrl_req response time. after dfi_lp_ctrl_req asserted, and after response time if there's still no dfi_lp_ack respone, then drop the dfi_lp_ctrl_req.
+#define DMC_DRAM_TCKECK ((0x002c << 2) + 0xfe024400)
+ //bit 4:0. tCKECK from CKE low to assert dfi_dram_clk_disable time. this time + dfi_t_ctrl_delay
+#define DMC_DRAM_TREFI ((0x002d << 2) + 0xfe024400)
+ //write this register will update the auto refresh related register to the auto refresh control logic.
+ //bit 31:24: tZQCI dmc send zqci period. unit is how much auto refresh period.
+ //bit 23:16 pvti dmc send dfi_ctrlupd_req period. unit is one auto refresh period.
+ //bit 15:8. tREFI.dmc send auto refresh command period. unit is 100ns.
+ //bit 7:0. t100ns period. unit is dmc clock cycles
+#define DMC_DRAM_TSR ((0x002e << 2) + 0xfe024400)
+ //bit 5:0 tSR. self resfresh enter to exit time.
+#define DMC_DRAM_TCCDMW ((0x002f << 2) + 0xfe024400)
+ //bit 5:0. 4*tCCD in LPDDR4 mask write.
+#define DMC_DRAM_TESCKE ((0x0030 << 2) + 0xfe024400)
+ //bit 5:0 tESCKE. enter self refresh to power time for LPDDR4.
+#define DMC_DRAM_TREFI_DDR3 ((0x0031 << 2) + 0xfe024400)
+ //7:0. DDR3 SDRAM tREFI single auto refresh time . the unit is t100ns.
+ //use this to check in 8*tREFI time, the DMC should not sent more than 16 auto REFRESH command.
+#define DMC_DRAM_TZQCAL ((0x0032 << 2) + 0xfe024400)
+ //11:0. ZQCAL for LPDDR4. ZQINIT/ZQoper for DDR3/4 ZQCL command.
+#define DMC_DRAM_T10US ((0x0033 << 2) + 0xfe024400)
+ //10us clock cycle number used for LP2 mode.
+#define DMC_DRAM_TMRRI ((0x0034 << 2) + 0xfe024400)
+//bit 7:0 tMRRI for MRR
+#define DMC_DRAM_TXS_FAST ((0x0035 << 2) + 0xfe024400)
+ //bit 9:0 DDR4 mode XS_FAST exit self_refrest to zqcl/zqcs/mrs command.
+#define DMC_DRAM_DFIODTCFG ((0x0036 << 2) + 0xfe024400)
+ //bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity.
+ //bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1.
+ //bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0.
+ //bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1.
+ //bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0.
+ //bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity.
+ //bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0.
+ //bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1.
+ //bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0.
+ //bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1.
+#define DMC_DRAM_DFIODTCFG1 ((0x0037 << 2) + 0xfe024400)
+ //bit 27:24 ODT length for BL8 read transfer.
+ //bit 19:16. ODT length for BL8 write transfer.
+ //bit 12:8. ODT latency for reads. suppose to be 0.
+ //bit 4:0. ODT latency for writes. suppose to be 0.
+#define DMC_DRAM_TWODTON ((0x0038 << 2) + 0xfe024400)
+ //bit 5:0 DRAM write access ODT on time.
+ // in DDR3/4 should be same as WL.
+ // in LPDDR4 = tODTLon + tODTon.min
+#define DMC_DRAM_TRETRAIN ((0x0039 << 2) + 0xfe024400)
+ //bit 15:0 LPDDR4 OSCRING retraining timer(units = auto_refresh timer). sync with autorefresh
+#define DMC_DRAM_PHYADDRON ((0x003a << 2) + 0xfe024400)
+ //PHY_CTRL_ADDR_ON for new PHY. default : 12
+#define DMC_DRAM_PHYWRON ((0x003b << 2) + 0xfe024400)
+ // PHY_CTRL_WR_ON. = 10 + WL/2 + (tDQSS+ tDQS2DQ + tWPST)/dfi_clk + BL/4
+#define DMC_DRAM_PHYRDON ((0x003c << 2) + 0xfe024400)
+ // PHY_CTRL_RD_ON. = 10 + RL/2 + (tDQSCK+ tRPST + tDQSQ)/dfi_clk + BL/4
+#define DMC_DRAM_DFITRDDATACSEN ((0x003d << 2) + 0xfe024400)
+#define DMC_DRAM_DFITPHYWRCSLAT ((0x003e << 2) + 0xfe024400)
+//timing paramter for frequency set 1.
+#define DMC_NFQ_TMRD ((0x0040 << 2) + 0xfe024400)
+#define DMC_NFQ_TRFC ((0x0041 << 2) + 0xfe024400)
+#define DMC_NFQ_TRP ((0x0042 << 2) + 0xfe024400)
+#define DMC_NFQ_TRTW ((0x0043 << 2) + 0xfe024400)
+#define DMC_NFQ_TCL ((0x0044 << 2) + 0xfe024400)
+#define DMC_NFQ_TCWL ((0x0045 << 2) + 0xfe024400)
+#define DMC_NFQ_TRAS ((0x0046 << 2) + 0xfe024400)
+#define DMC_NFQ_TRC ((0x0047 << 2) + 0xfe024400)
+#define DMC_NFQ_TRCD ((0x0048 << 2) + 0xfe024400)
+#define DMC_NFQ_TRRD ((0x0049 << 2) + 0xfe024400)
+#define DMC_NFQ_TFAW ((0x004a << 2) + 0xfe024400)
+#define DMC_NFQ_TRTP ((0x004b << 2) + 0xfe024400)
+#define DMC_NFQ_TWR ((0x004c << 2) + 0xfe024400)
+#define DMC_NFQ_TWTR ((0x004d << 2) + 0xfe024400)
+#define DMC_NFQ_TCCD ((0x004e << 2) + 0xfe024400)
+#define DMC_NFQ_TEXSR ((0x004f << 2) + 0xfe024400)
+#define DMC_NFQ_TXS ((0x0050 << 2) + 0xfe024400)
+#define DMC_NFQ_TXP ((0x0051 << 2) + 0xfe024400)
+#define DMC_NFQ_TXPDLL ((0x0052 << 2) + 0xfe024400)
+#define DMC_NFQ_TZQCS ((0x0053 << 2) + 0xfe024400)
+#define DMC_NFQ_TCKSRE ((0x0054 << 2) + 0xfe024400)
+#define DMC_NFQ_TCKSRX ((0x0055 << 2) + 0xfe024400)
+#define DMC_NFQ_TCKE ((0x0056 << 2) + 0xfe024400)
+#define DMC_NFQ_TMOD ((0x0057 << 2) + 0xfe024400)
+#define DMC_NFQ_TDQS ((0x0058 << 2) + 0xfe024400)
+#define DMC_NFQ_TRSTL ((0x0059 << 2) + 0xfe024400)
+#define DMC_NFQ_TZQLAT ((0x005a << 2) + 0xfe024400)
+#define DMC_NFQ_TMRR ((0x005b << 2) + 0xfe024400)
+#define DMC_NFQ_TCKESR ((0x005c << 2) + 0xfe024400)
+#define DMC_NFQ_TDPD ((0x005d << 2) + 0xfe024400)
+#define DMC_NFQ_DFITCTRLDELAY ((0x005e << 2) + 0xfe024400)
+#define DMC_NFQ_DFITPHYWRDATA ((0x005f << 2) + 0xfe024400)
+#define DMC_NFQ_DFITPHYWRLAT ((0x0060 << 2) + 0xfe024400)
+#define DMC_NFQ_DFITRDDATAEN ((0x0061 << 2) + 0xfe024400)
+#define DMC_NFQ_DFITPHYRDLAT ((0x0062 << 2) + 0xfe024400)
+#define DMC_NFQ_DFITCTRLUPDMIN ((0x0063 << 2) + 0xfe024400)
+#define DMC_NFQ_DFITCTRLUPDMAX ((0x0064 << 2) + 0xfe024400)
+#define DMC_NFQ_DFITREFMSKI ((0x0066 << 2) + 0xfe024400)
+#define DMC_NFQ_DFITCTRLUPDI ((0x0067 << 2) + 0xfe024400)
+#define DMC_NFQ_DFITDRAMCLK ((0x0068 << 2) + 0xfe024400)
+#define DMC_NFQ_DFITLPRESP ((0x006a << 2) + 0xfe024400)
+#define DMC_NFQ_TCKECK ((0x006c << 2) + 0xfe024400)
+#define DMC_NFQ_TREFI ((0x006d << 2) + 0xfe024400)
+#define DMC_NFQ_TSR ((0x006e << 2) + 0xfe024400)
+#define DMC_NFQ_TCCDMW ((0x006f << 2) + 0xfe024400)
+#define DMC_NFQ_TESCKE ((0x0070 << 2) + 0xfe024400)
+#define DMC_NFQ_TREFI_DDR3 ((0x0071 << 2) + 0xfe024400)
+#define DMC_NFQ_TZQCAL ((0x0072 << 2) + 0xfe024400)
+#define DMC_NFQ_T10US ((0x0073 << 2) + 0xfe024400)
+#define DMC_NFQ_TMRRI ((0x0074 << 2) + 0xfe024400)
+#define DMC_NFQ_TXS_FAST ((0x0075 << 2) + 0xfe024400)
+#define DMC_NFQ_DFIODTCFG ((0x0076 << 2) + 0xfe024400)
+#define DMC_NFQ_DFIODTCFG1 ((0x0077 << 2) + 0xfe024400)
+#define DMC_NFQ_TWODTON ((0x0078 << 2) + 0xfe024400)
+#define DMC_NFQ_TRETRAIN ((0x0079 << 2) + 0xfe024400)
+#define DMC_NFQ_PHYADDRON ((0x007a << 2) + 0xfe024400)
+#define DMC_NFQ_PHYWRON ((0x007b << 2) + 0xfe024400)
+#define DMC_NFQ_PHYRDON ((0x007c << 2) + 0xfe024400)
+#define DMC_NFQ_DFITRDDATACSEN ((0x007d << 2) + 0xfe024400)
+#define DMC_NFQ_DFITPHYWRCSLAT ((0x007e << 2) + 0xfe024400)
+//end of second frequency timing parameter
+#define DMC_DRAM_DFITPHYUPDTYPE0 ((0x0080 << 2) + 0xfe024400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 0.
+#define DMC_DRAM_DFITPHYUPDTYPE1 ((0x0081 << 2) + 0xfe024400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 1.
+#define DMC_DRAM_DFITPHYUPDTYPE2 ((0x0082 << 2) + 0xfe024400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 2.
+#define DMC_DRAM_DFITPHYUPDTYPE3 ((0x0083 << 2) + 0xfe024400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 3.
+#define DMC_DRAM_MCFG ((0x0086 << 2) + 0xfe024400)
+ //bit 18. send retrain command after siu self refresh exit. 1 : enable. 0 : disable.
+ //bit 17. in DDR3/4 mode, send ZQCL command after exit register triggered self refresh.
+ //bit 16. send refresh command after finish frequency change. 1 : enable. 0 : disable.
+ //bit 15. send refresh command after finish LPDDR4 retraining. 1 : enable. 0 : disable.
+ //bit 14. 1: cke init low. 0 : cke init high.
+ //bit 13 1: dbi write enable only for LPDDR4.
+ //bit 12. 1: dbi read inversion. 0: dbi read high inversion.
+ //bit 11. 1: dbi read enable. 0: dbi not enabled.
+ //bit 10 1: enable staggered chip select for 2 ranks DRAM.
+ //bit 9 1: enable send auto refresh command to DDR SDRAM when PCTL is in CFG/STOP state.
+ //bit 8 send auto refr cmd before enter register triggered self refresh
+ //bit 7 send auto refr cmd after exit regsiter triggered self refresh mode.
+ //bit 6 disable dram clock after enter register triggered self refresh.
+ //bit 5 send DFI_LP_REQ to PHY after enter register triggered elf refresh mode.
+ //bit 4 send DRAM to power down mode after enter self refresh. ONLY for LPDDR4.
+ //bit 3 send DFI_CTRLUPD_REQ after exit register triggered self refresh.
+ //bit 2 send ZQCS command after exit register triggered self refresh.
+ //bit 1 enable PHY triggered DFI_PHYUPD_REQ.
+ //bit 0 2T mode. always 1 in DDR3/4 mode.
+#define DMC_DRAM_DFI_CTRL ((0x0089 << 2) + 0xfe024400)
+ //bit 31 siu_dfi_lat err generation enable. 1: if dfi read latency violation, generate data error. 0 : disable.
+ //bit 18: dfi_rddata_cs_n polariy. 0: rank0 select = 2'b10. rank1 select = 2'b10. 1: rank0 select = 2'b01, rank1_select = 2'b10.
+ //bit 17: dfi_wrdata_cs_n polariy. 0: rank0 select = 2'b10. rank1 select = 2'b10. 1: rank0 select = 2'b01, rank1_select = 2'b10.
+ //bit 16: force PHY ctrl_on if = 1, phy_ctrl_on singal will keep on.
+ //bit 15 siu_dfi1_lp_en
+ //bit 14 siu_dfi_lp_ack_and
+ //bit 13 siu_dfi_lp_ack_or
+ //bit 12 siu_dfi1_init_start_en
+ //bit 11 siu_dfi_init_com_and
+ //bit 10 siu_dfi_init_com_or
+ //bit 9 siu_dfi1_freq_en
+ //bit 8 siu_dfi1_dram_clk_dis_en
+ //bit 7 siu_dfi_phyupd_type_sel
+ //bit 6 siu_dfi1_phyupd_ack_en
+ //bit 5 siu_dfi_phyupd_req_and
+ //bit 4 siu_dfi_phyupd_req_or
+ //bit 3 siu_dfi_ctrlupd_ack_and
+ //bit 2 siu_dfi_ctrlupd_ack_or
+ //bit 1 siu_dfi1_ctrlupd_req_en
+ //bit 0 siu_dfi1_cmd_en
+#define DMC_DRAM_DFIINITCFG ((0x008a << 2) + 0xfe024400)
+ //bit 31. dfi_init_complete status. read only.
+ //bit 15:14. Frequency set 1 dfi_freq_ratio value.
+ //bit 12:8 Frequency set 1 dfi_freq value.
+ //bit 7:6 Frequency set 0 dfi_freq_ratio value.
+ //bit 5:1 Frequency set 0 dfi_freq value.
+ //bit 0. dfi_init_start value can be use manually config dfi_init_start signal.
+#define DMC_DRAM_ZQ_CTRL ((0x008b << 2) + 0xfe024400)
+ // only 1 bit can be enabled at same time.
+ //bit 2 send ZQCS command to RANK0 then send comand to RANK1.
+ //bit 1. send ZQCS command to both RANK0 and RANK1 together.
+ //bit 0. send ZQCS command to only rank0.
+#define DMC_DRAM_APD_CTRL ((0x008c << 2) + 0xfe024400)
+ //bit 19:16 DFI_LP_WAKEUP value in APD DFI_LP_REQ mode
+ //bit 12 1: exit power down slow mode(waiting PLL LOCK). 0 : fast mode.
+ //bit 11 enable DFI_LP_REQ when enter Auto power down mode.
+ //bit 10 disable DFI_clk_disable when enter auto power down mode.
+ //bit 9:0 0 disable auto power down mode.
+ //non zero value to enable auto power down when DMC is in idle state for this number of clock cycles.
+#define DMC_DRAM_ASR_CTRL ((0x008d << 2) + 0xfe024400)
+ //bit 31. enable RETRAIN PHY after auto selfrefresh exit. for AM_PHY only.
+ //bit 30. in DDR3/4 mode, send ZQCL command after exit from auto self refresh mode.
+ //bit 29. enable PHY clock in LP2 mode. 1: enable. 0 : disable.
+ //bit 28. enable dmc wait 10us after LP2 mode exit if it's long time the PHY in LP2 mode..
+ //bit [27:24] DFI_LP_WAKEUP value in self refresh DFI_LP_REQ mode.
+ //bit 23 : send REFRESH command after exit from auto self refersh mode(ASR).
+ //bit 22 : send REFERSH command before enter to Auto self refresh mode(ASR).
+ //bit 21 : send ZQCS command after exit from Auto self refresh mode(ASR).
+ //bit 20 : send dfi_ctrl_upd after exit from ASR mode
+ //bit 19 : send power down command when enter ASR mode. //for LPDDR4 only.
+ //bit 18 : set the PHY enter LP2 mode after enter ASR mode.
+ //bit 17 : send DFI_LP_REQ after enter ASR mode.
+ //bit 16 : set DFI_CLK_DISABLE after enter ASR mode.
+ //bit 15:0. 0 disable auto ASR mode.
+ // Non-zero valule enable ASR mode. when DMC is in idle state for this number of clock cycles, the DMC will enter ASR mode.
+#define DMC_DRAM_REFR_CTRL ((0x0092 << 2) + 0xfe024400)
+ //bit 17:8 auto refresh request pending cnt if there's page hit request.
+ //bit 7 retrain enable for auto refresh requent. 1: enable. 0: disable.
+ //bit 6 Disabled auto refresh command if over 16 auto refresh command sent in 2 TREFI_DDR3 period
+ //bit 5 enable dmc send ZQCS command .
+ //bit 4. enable dmc send DFI_CTRUPD_REQ.
+ //bit 3:1. how many refresh command send for one period. = this number + 1
+ //bit 0. enable dmc send auto refresh command.
+#define DMC_DRAM_FREQ_CTRL ((0x0093 << 2) + 0xfe024400)
+//bit 31 . write 1 to change freqency read 0: finished.
+//bit 30. waiting for software to send some manual command. 1 : waiting. 0 : not ready yet.
+//bit 29:9. not used.
+//bit 19:16. how many cycles to send PLL change req after init_complete signal to low.
+//bit 15. freq pre config_en. Before freq enter stop state let DMC configure DDR SDRAM.
+//bit 13. freq post config_en. After freq enter stop state let DMC configure DDR SDRAM.
+//bit 13. send zqcl after freq change in DDR3/4 mode.
+//bit 13. send zqcl after freq change in DDR3/4 mode.
+//bit 12. send zqcs after freq change. 1: enable. 0 not send.
+//bit 11. in AUTO MRW fucntion: the data format. 1: use USR_CMD format. 0: MRW format.
+//bit 10. AUTO MRW function: 1 use hardware auto MRW function. 0: don't do auto MRW.
+//bit 9. 1 : FREQ MRW done. let FREQ change machine continue.
+//bit 8 FREQ WAIT. 1 when freq change finishes, state machine stop at self refresh state in case there's something need to handle.
+ // 0 after freq change finishes the state machine go back to access state.
+//bit 7 when change PLL setting, disable dmc clock
+//bit 6 when change PLL setting, disable PHY DfiClk and DfiCtlClk.
+//bit 5 check vpu_sleep_en ==1 when do FREQ change. if vpu_sleep_en == 0, just wait.
+//bit 4 nxt frequency selection. 1 = freq1. 0 = freq0.
+//bit 3:1. not used.
+//bit 0. current frequency selection.
+#define DMC_DRAM_SCFG ((0x0094 << 2) + 0xfe024400)
+ // bit 2:0 only one bit can be high at same time.
+ // bit 2 1 : to ask PCTL enter ACCESS STATE. 0 : deassert the request.
+ // bit 1 1 : to ask PCTL enter SELF REFRESH STATE. 0 : deassert the request.
+ // bit 0 1 : to ask PCTL enter STOP/CONFIG STATE . 0 : deassert the request.
+#define DMC_DRAM_STAT ((0x0095 << 2) + 0xfe024400)
+ //bit 31 rd latency error. 1: means after dfiphytrdlat cycles, the read data still not back.
+ //bit 28:24 dram_sr_state
+ //bit 23:20 stop_st
+ //bit 19:15 sleep_st
+ //bit 14:12 ACCESS STATUS 0 : ACCESS is in normal working mode.
+ //1 : ACCESS sending precharege command.
+ //2 : ACCESS sending AUTO REFESH command.
+ //3 : ACCESS sending DIF_CTRLUPD_REQ command.
+ //4 : ACCESS sending ZQCS command to DDR DRAM(ZQCAL for LPDDR4).
+ //5 : ACCESS sending ZQLATCH command to LPDDR4 only.
+ //bit 11:8 APD STATUS: 0 : APD_IDLE
+ //1 : APD sending PRECHARGE command
+ //2 : APD sending CKE low command
+ //3 : APD sending DISABLE DRAM CLOCK command
+ //4 : APD sending DFI_LP_CTRL_REQ
+ //5 : APD in Auto Power down mode.
+ //6 : APD deassert DFI_LP_CTRL_REQ
+ //7 : APD sending enable DRAM CLOCK command
+ //8 : APD sending out CKE high command.
+ //bit 7:4: DRAM_STATUS: 0 : DRAM IDLE
+ //1 : DRAM_STOP/DRAM_CFG
+ //2 : DRAM_ACCESS
+ //3 : DRAM_SLEEP
+ //4 : DRAM APD(AUTO POWER DOWN).
+ //5 : IDLE -> STOP/CONFIG
+ //6 : STOP -> SLEEP
+ //7 : STOP -> ACCESS
+ //8 : ACCESS -> SLEEP.
+ //9 : ACCESS -> STOP
+ //A : ACCESS -> APD
+ //B : SLEEP -> STOP
+ //C : SLEEP -> ACCESS
+ //D : APD -> ACCESS
+ //bit 3 reserved.
+ //bit 2 1 : DRAM enter normal working state.
+ //bit 1 1 : DRAM enter sleep state. self refresh state.
+ //bit 0 1 : dram enter cfg state.
+#define DMC_DRAM_STAT1 ((0x0096 << 2) + 0xfe024400)
+ //bit 11:8 freq_st.
+ //bit 7:5 train_st
+ //bit 4:0 dram_phy_st
+#define DMC_PHY_RETRAINING_CTRL ((0x0097 << 2) + 0xfe024400)
+ //bit 31 : phy_retraining enable.
+ //bit 30 : check vpu sleep_en.
+ //bit 25:24 : retraining dfi_freq[4:3], the [2:0] bit still use the dfi_freq bits to keep the frequency.
+ //bit 23:0: retraining period unit : 100ns.
+#define DMC_DFI_ERR_STAT ((0x0098 << 2) + 0xfe024400)
+ //LPDDR4 PHY DFI error infomation.
+ //bit 31:20. not used.
+ //bit 9. ddr0_dfi_error
+ //bit 8:5 ddr0_dfi_error_info.
+ //bit 4. ddr1_dfi_error.
+ //bit 3:0. ddr1_dfi_error_info.
+#define DMC_LP2_TIMER ((0x009a << 2) + 0xfe024400)
+//bit 15:0. timer setting to measure how long the chip is entered LP2 mode.
+//this timer is 40bits counter with DMC PCLK.
+//we use the high 16bits to compare this register. if the counter is large than this number, that means the PHY need addition 10us after wakeup the PHY and before exit self_refresh mode.
+#define DMC_DRAM_COMPLETE_WAIT ((0x009b << 2) + 0xfe024400)
+ //read only how long to waiting for DFI_INIT_COMPLETE become high after DFI_INIT_START triggered.
+#define DMC_DRAM_DFI_SWAP_0 ((0x00a0 << 2) + 0xfe024400)
+ //bit 5:0. dfi_act_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_1 ((0x00a1 << 2) + 0xfe024400)
+ //bit 5:0. dfi_ras_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_2 ((0x00a2 << 2) + 0xfe024400)
+ //bit 5:0. dfi_cas_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_3 ((0x00a3 << 2) + 0xfe024400)
+ //bit 5:0. dfi_we_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_4 ((0x00a4 << 2) + 0xfe024400)
+ //bit 5:0. dfi_bg0 function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_5 ((0x00a5 << 2) + 0xfe024400)
+ //bit 5:0. dfi_bg[1] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_6 ((0x00a6 << 2) + 0xfe024400)
+ //bit 5:0. dfi_ba[0] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_7 ((0x00a7 << 2) + 0xfe024400)
+ //bit 5:0. dfi_ba[1] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_8 ((0x00a8 << 2) + 0xfe024400)
+ //bit 5:0. dfi_ba[2] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_9 ((0x00a9 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[0] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_10 ((0x00aa << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[1] function select
+#define DMC_DRAM_DFI_SWAP_11 ((0x00ab << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[2] function select
+#define DMC_DRAM_DFI_SWAP_12 ((0x00ac << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[3] function select
+#define DMC_DRAM_DFI_SWAP_13 ((0x00ad << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[4] function select
+#define DMC_DRAM_DFI_SWAP_14 ((0x00ae << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[5] function select
+#define DMC_DRAM_DFI_SWAP_15 ((0x00af << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[6] function select
+#define DMC_DRAM_DFI_SWAP_16 ((0x00b0 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[7] function select
+#define DMC_DRAM_DFI_SWAP_17 ((0x00b1 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[8] function select
+#define DMC_DRAM_DFI_SWAP_18 ((0x00b2 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[9] function select
+#define DMC_DRAM_DFI_SWAP_19 ((0x00b3 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[10] function select
+#define DMC_DRAM_DFI_SWAP_20 ((0x00b4 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[11] function select
+#define DMC_DRAM_DFI_SWAP_21 ((0x00b5 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[12] function select
+#define DMC_DRAM_DFI_SWAP_22 ((0x00b6 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[13] function select
+#define DMC_DRAM_DFI_SWAP_23 ((0x00b7 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[14] function select
+#define DMC_DRAM_DFI_SWAP_24 ((0x00b8 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[15] function select
+#define DMC_DRAM_DFI_SWAP_25 ((0x00b9 << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[16] function select
+#define DMC_DRAM_DFI_SWAP_26 ((0x00ba << 2) + 0xfe024400)
+ //bit 5:0. dfi_a[17] function select
+#define DMC_DRAM_CMD ((0x00d0 << 2) + 0xfe024400)
+ //bit 31. cmd done. write 0 to clean.
+ //bit 30. data done. write 0 to clean.
+ //bit 5. user defined command.
+ //bit 4. LPDDR4 MPC write data command( MPC WR FIFO).
+ //bit 3. LPDDR4 MPC read data command (MPC RD Calibration and RD FIFO).
+ //bit 2. LPDDR4 MPC-1 command ( NOP, Start DQS interval ....)
+ //bit 1. mrr comand.
+ //bit 0. mrw command.
+#define DMC_DRAM_CMD_CODE ((0x00d1 << 2) + 0xfe024400)
+ //bit 31:28 user command case: = {act_n, ras_n, cas_n, we_n}
+ //bit 27:26. 128bits data cycles . 0: 1 clock cycles; 1: 2 clock cycles; 2: 3 clock cycles; 3:4 clock cycles.
+ // LPDDR4 32bits: 4 clock cycles; LPDDR4 16bits: 2 clock cycles;
+ // DDR3/4/LPDDR3 32 bits : 2 clock cycles. DDR3/4 16bits: 1 cycles.
+ //bit 25 MRW/MRR/MPC command rank 1 select. 1: select. 0: not select.
+ //bit 24. MRW/MRR/MPC command rank 0 select. 1: select. 0: not select.
+ //bit 23:16 MR addr. DDR4 case : 18:16 ba[2:0]. 20:19 BG[1:0].
+ //bit 15:0 opcode.
+#define DMC_DRAM_CMD_TIME ((0x00d2 << 2) + 0xfe024400)
+//bit 31:16 PRE CMD timer. //delay how many cycle to start the command.
+//bit 15:0 POST CMD timer //delay how many cycle after the command execute.
+#define DMC_DRAM_WSTRB0 ((0x00d3 << 2) + 0xfe024400)
+#define DMC_DRAM_WSTRB1 ((0x00d4 << 2) + 0xfe024400)
+#define DMC_DRAM_RDBI0 ((0x00d5 << 2) + 0xfe024400)
+ //MPC RD FIFO command DBI read back data
+ //bit 31:16 the second cycle.
+ //bit 15:0 the first cycle.
+#define DMC_DRAM_RDBI1 ((0x00d6 << 2) + 0xfe024400)
+ //MPC RD FIFO command DBI read back data
+ //bit 31:16. the Forth cycle.
+ //bit 15:0. the third cycle.
+//WD0~16 and RD0~16 can be used as MRW command as Frequency change .
+//WD0~16 is for Freq1 DRAM MR setting, it would send to DRAM right before FREQ0-> FREQ1
+//RD0_16 is for Freq0 DRAM MR setting. it would send to DRAM right before FREQ1-> FREQ0.
+//each register can be one MRW command. So total 16 MRW command can be sent to DRAM.
+//The register formats:
+//bit 31. MRW/USER comand enable. 1: enabled command. 0 not enabled.
+//bit 30. last MRW/USER command. if this bit =1, After send this command, the DRAM controller will contine frequency next stage.
+//bit 29:26. USER COMMAND parameter: in DDR3/DDR4. {act_n, ras_n, cas_n, we_n} value for user command
+ //in LPDDR4. bit 16: 1 4 cycles command. 0 2 cycles command.
+//bit 25 MRW/USER command rank 1 select. 1: select. 0: not select.
+//bit 24. MRW/USER command rank 0 select. 1: select. 0: not select.
+//bit 23:0. USER command.
+ //DDR3: 18:16 bank address. 15:0: address.
+ //DDR4: 20:19 bank group address. 18:16: bank address. 15:0 address.
+ //LPDDR3: 9:0. rising edge address. 19:10. falling edge address.
+ //LPDDR4. 5:0, first edge address, 11:6 second edge address, 17:12: third edge address. 23:18, forth edge address.
+ //MRW command format:
+ //bit 23:16 MR addr. DDR4 case : 18:16 ba[2:0]. 20:19 BG[1:0].
+ //bit 15:0 opcode.
+#define DMC_DRAM_WD0 ((0x00e0 << 2) + 0xfe024400)
+#define DMC_DRAM_WD1 ((0x00e1 << 2) + 0xfe024400)
+#define DMC_DRAM_WD2 ((0x00e2 << 2) + 0xfe024400)
+#define DMC_DRAM_WD3 ((0x00e3 << 2) + 0xfe024400)
+#define DMC_DRAM_WD4 ((0x00e4 << 2) + 0xfe024400)
+#define DMC_DRAM_WD5 ((0x00e5 << 2) + 0xfe024400)
+#define DMC_DRAM_WD6 ((0x00e6 << 2) + 0xfe024400)
+#define DMC_DRAM_WD7 ((0x00e7 << 2) + 0xfe024400)
+#define DMC_DRAM_WD8 ((0x00e8 << 2) + 0xfe024400)
+#define DMC_DRAM_WD9 ((0x00e9 << 2) + 0xfe024400)
+#define DMC_DRAM_WD10 ((0x00ea << 2) + 0xfe024400)
+#define DMC_DRAM_WD11 ((0x00eb << 2) + 0xfe024400)
+#define DMC_DRAM_WD12 ((0x00ec << 2) + 0xfe024400)
+#define DMC_DRAM_WD13 ((0x00ed << 2) + 0xfe024400)
+#define DMC_DRAM_WD14 ((0x00ee << 2) + 0xfe024400)
+#define DMC_DRAM_WD15 ((0x00ef << 2) + 0xfe024400)
+#define DMC_DRAM_RD0 ((0x00f0 << 2) + 0xfe024400)
+#define DMC_DRAM_RD1 ((0x00f1 << 2) + 0xfe024400)
+#define DMC_DRAM_RD2 ((0x00f2 << 2) + 0xfe024400)
+#define DMC_DRAM_RD3 ((0x00f3 << 2) + 0xfe024400)
+#define DMC_DRAM_RD4 ((0x00f4 << 2) + 0xfe024400)
+#define DMC_DRAM_RD5 ((0x00f5 << 2) + 0xfe024400)
+#define DMC_DRAM_RD6 ((0x00f6 << 2) + 0xfe024400)
+#define DMC_DRAM_RD7 ((0x00f7 << 2) + 0xfe024400)
+#define DMC_DRAM_RD8 ((0x00f8 << 2) + 0xfe024400)
+#define DMC_DRAM_RD9 ((0x00f9 << 2) + 0xfe024400)
+#define DMC_DRAM_RD10 ((0x00fa << 2) + 0xfe024400)
+#define DMC_DRAM_RD11 ((0x00fb << 2) + 0xfe024400)
+#define DMC_DRAM_RD12 ((0x00fc << 2) + 0xfe024400)
+#define DMC_DRAM_RD13 ((0x00fd << 2) + 0xfe024400)
+#define DMC_DRAM_RD14 ((0x00fe << 2) + 0xfe024400)
+#define DMC_DRAM_RD15 ((0x00ff << 2) + 0xfe024400)
+//
+// Closing file: ../mmc_new/dmc/rtl/dmc_siu_reg.vh
+//
+//
+// Reading file: ../mmc_new/dmc/rtl/dmc_sticky_reg.vh
+//
+//`ifdef DMC_STICKY_REG_DEFINE
+//`else
+//`define DMC_STICKY_REG_DEFINE
+// -----------------------------------------------
+// APB_BASE: APB1_BASE_ADDR = 0xfe024800
+// -----------------------------------------------
+//`define DMC_STICKY_REG_BASE 32'hfe024800
+//those register is for software save some tempary value. and because it's in RAM. it won't lose if DMC get reseted.
+#define DMC_STICKY_0 ((0x0000 << 2) + 0xfe024800)
+#define DMC_STICKY_1 ((0x0001 << 2) + 0xfe024800)
+#define DMC_STICKY_2 ((0x0002 << 2) + 0xfe024800)
+#define DMC_STICKY_3 ((0x0003 << 2) + 0xfe024800)
+#define DMC_STICKY_4 ((0x0004 << 2) + 0xfe024800)
+#define DMC_STICKY_5 ((0x0005 << 2) + 0xfe024800)
+#define DMC_STICKY_6 ((0x0006 << 2) + 0xfe024800)
+#define DMC_STICKY_7 ((0x0007 << 2) + 0xfe024800)
+#define DMC_STICKY_8 ((0x0008 << 2) + 0xfe024800)
+#define DMC_STICKY_9 ((0x0009 << 2) + 0xfe024800)
+#define DMC_STICKY_10 ((0x000a << 2) + 0xfe024800)
+#define DMC_STICKY_11 ((0x000b << 2) + 0xfe024800)
+#define DMC_STICKY_12 ((0x000c << 2) + 0xfe024800)
+#define DMC_STICKY_13 ((0x000d << 2) + 0xfe024800)
+#define DMC_STICKY_14 ((0x000e << 2) + 0xfe024800)
+#define DMC_STICKY_15 ((0x000f << 2) + 0xfe024800)
+#define DMC_STICKY_16 ((0x0010 << 2) + 0xfe024800)
+#define DMC_STICKY_17 ((0x0011 << 2) + 0xfe024800)
+#define DMC_STICKY_18 ((0x0012 << 2) + 0xfe024800)
+#define DMC_STICKY_19 ((0x0013 << 2) + 0xfe024800)
+#define DMC_STICKY_20 ((0x0014 << 2) + 0xfe024800)
+#define DMC_STICKY_21 ((0x0015 << 2) + 0xfe024800)
+#define DMC_STICKY_22 ((0x0016 << 2) + 0xfe024800)
+#define DMC_STICKY_23 ((0x0017 << 2) + 0xfe024800)
+#define DMC_STICKY_24 ((0x0018 << 2) + 0xfe024800)
+#define DMC_STICKY_25 ((0x0019 << 2) + 0xfe024800)
+#define DMC_STICKY_26 ((0x001a << 2) + 0xfe024800)
+#define DMC_STICKY_27 ((0x001b << 2) + 0xfe024800)
+#define DMC_STICKY_28 ((0x001c << 2) + 0xfe024800)
+#define DMC_STICKY_29 ((0x001d << 2) + 0xfe024800)
+#define DMC_STICKY_30 ((0x001e << 2) + 0xfe024800)
+#define DMC_STICKY_31 ((0x001f << 2) + 0xfe024800)
+#define DMC_STICKY_32 ((0x0020 << 2) + 0xfe024800)
+#define DMC_STICKY_33 ((0x0021 << 2) + 0xfe024800)
+#define DMC_STICKY_34 ((0x0022 << 2) + 0xfe024800)
+#define DMC_STICKY_35 ((0x0023 << 2) + 0xfe024800)
+#define DMC_STICKY_36 ((0x0024 << 2) + 0xfe024800)
+#define DMC_STICKY_37 ((0x0025 << 2) + 0xfe024800)
+#define DMC_STICKY_38 ((0x0026 << 2) + 0xfe024800)
+#define DMC_STICKY_39 ((0x0027 << 2) + 0xfe024800)
+#define DMC_STICKY_40 ((0x0028 << 2) + 0xfe024800)
+#define DMC_STICKY_41 ((0x0029 << 2) + 0xfe024800)
+#define DMC_STICKY_42 ((0x002a << 2) + 0xfe024800)
+#define DMC_STICKY_43 ((0x002b << 2) + 0xfe024800)
+#define DMC_STICKY_44 ((0x002c << 2) + 0xfe024800)
+#define DMC_STICKY_45 ((0x002d << 2) + 0xfe024800)
+#define DMC_STICKY_46 ((0x002e << 2) + 0xfe024800)
+#define DMC_STICKY_47 ((0x002f << 2) + 0xfe024800)
+#define DMC_STICKY_48 ((0x0030 << 2) + 0xfe024800)
+#define DMC_STICKY_49 ((0x0031 << 2) + 0xfe024800)
+#define DMC_STICKY_50 ((0x0032 << 2) + 0xfe024800)
+#define DMC_STICKY_51 ((0x0033 << 2) + 0xfe024800)
+#define DMC_STICKY_52 ((0x0034 << 2) + 0xfe024800)
+#define DMC_STICKY_53 ((0x0035 << 2) + 0xfe024800)
+#define DMC_STICKY_54 ((0x0036 << 2) + 0xfe024800)
+#define DMC_STICKY_55 ((0x0037 << 2) + 0xfe024800)
+#define DMC_STICKY_56 ((0x0038 << 2) + 0xfe024800)
+#define DMC_STICKY_57 ((0x0039 << 2) + 0xfe024800)
+#define DMC_STICKY_58 ((0x003a << 2) + 0xfe024800)
+#define DMC_STICKY_59 ((0x003b << 2) + 0xfe024800)
+#define DMC_STICKY_60 ((0x003c << 2) + 0xfe024800)
+#define DMC_STICKY_61 ((0x003d << 2) + 0xfe024800)
+#define DMC_STICKY_62 ((0x003e << 2) + 0xfe024800)
+#define DMC_STICKY_63 ((0x003f << 2) + 0xfe024800)
+//`endif
+//
+// Closing file: ../mmc_new/dmc/rtl/dmc_sticky_reg.vh
+//
+//
+// Reading file: ../sp/rtl/SP_REG_LIST.h
+//
+//========================================================================
+// APB_MPU_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB_BASE_ADDR = 0xfe00c000
+// -----------------------------------------------
+#define MPU_REGION0_ST ((0x0000 << 2) + 0xfe00c000)
+#define MPU_REGION0_ED ((0x0001 << 2) + 0xfe00c000)
+#define MPU_REGION1_ST ((0x0002 << 2) + 0xfe00c000)
+#define MPU_REGION1_ED ((0x0003 << 2) + 0xfe00c000)
+#define MPU_REGION2_ST ((0x0004 << 2) + 0xfe00c000)
+#define MPU_REGION2_ED ((0x0005 << 2) + 0xfe00c000)
+#define MPU_REGION3_ST ((0x0006 << 2) + 0xfe00c000)
+#define MPU_REGION3_ED ((0x0007 << 2) + 0xfe00c000)
+#define MPU_REGION4_ST ((0x0008 << 2) + 0xfe00c000)
+#define MPU_REGION4_ED ((0x0009 << 2) + 0xfe00c000)
+#define MPU_REGION5_ST ((0x000a << 2) + 0xfe00c000)
+#define MPU_REGION5_ED ((0x000b << 2) + 0xfe00c000)
+#define MPU_REGION6_ST ((0x000c << 2) + 0xfe00c000)
+#define MPU_REGION6_ED ((0x000d << 2) + 0xfe00c000)
+#define MPU_REGION7_ST ((0x000e << 2) + 0xfe00c000)
+#define MPU_REGION7_ED ((0x000f << 2) + 0xfe00c000)
+#define MPU_REGION8_ST ((0x0010 << 2) + 0xfe00c000)
+#define MPU_REGION8_ED ((0x0011 << 2) + 0xfe00c000)
+#define MPU_REGION9_ST ((0x0012 << 2) + 0xfe00c000)
+#define MPU_REGION9_ED ((0x0013 << 2) + 0xfe00c000)
+#define MPU_REGION10_ST ((0x0014 << 2) + 0xfe00c000)
+#define MPU_REGION10_ED ((0x0015 << 2) + 0xfe00c000)
+#define MPU_REGION11_ST ((0x0016 << 2) + 0xfe00c000)
+#define MPU_REGION11_ED ((0x0017 << 2) + 0xfe00c000)
+#define MPU_REGION12_ST ((0x0018 << 2) + 0xfe00c000)
+#define MPU_REGION12_ED ((0x0019 << 2) + 0xfe00c000)
+#define MPU_REGION13_ST ((0x001a << 2) + 0xfe00c000)
+#define MPU_REGION13_ED ((0x001b << 2) + 0xfe00c000)
+#define MPU_REGION14_ST ((0x001c << 2) + 0xfe00c000)
+#define MPU_REGION14_ED ((0x001d << 2) + 0xfe00c000)
+#define MPU_REGION15_ST ((0x001e << 2) + 0xfe00c000)
+#define MPU_REGION15_ED ((0x001f << 2) + 0xfe00c000)
+#define MPU_SEC_CTRL0 ((0x0020 << 2) + 0xfe00c000)
+#define MPU_ILLEGAL0_INFO0 ((0x0021 << 2) + 0xfe00c000)
+#define MPU_ILLEGAL0_INFO1 ((0x0022 << 2) + 0xfe00c000)
+#define MPU_ILLEGAL0_COUNT ((0x0023 << 2) + 0xfe00c000)
+#define MPU_ILLEGAL1_INFO0 ((0x0024 << 2) + 0xfe00c000)
+#define MPU_ILLEGAL1_INFO1 ((0x0025 << 2) + 0xfe00c000)
+#define MPU_ILLEGAL1_COUNT ((0x0026 << 2) + 0xfe00c000)
+#define MPU_CONFIG_VIO ((0x0027 << 2) + 0xfe00c000)
+//========================================================================
+// APB_MAILBOX_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB_BASE_ADDR = 0xff010000
+// -----------------------------------------------
+// `define MB_SCPU2REE_CSR_ADDR 12'h300
+// `define MB_SCPU2REE_DATA_ST_ADDR 12'h380
+// `define MB_SCPU2REE_DATA_ED_ADDR 12'h39f
+// `define MB_SCPU2TEE_CSR_ADDR 12'h100
+// `define MB_SCPU2TEE_DATA_ST_ADDR 12'h180
+// `define MB_SCPU2TEE_DATA_ED_ADDR 12'h19f
+// `define MB_REE2SCPU_CSR_ADDR 12'h200
+// `define MB_REE2SCPU_DATA_ST_ADDR 12'h280
+// `define MB_REE2SCPU_DATA_ED_ADDR 12'h29f
+// `define MB_TEE2SCPU_CSR_ADDR 12'h0
+// `define MB_TEE2SCPU_DATA_ST_ADDR 12'h80
+// `define MB_TEE2SCPU_DATA_ED_ADDR 12'h9f
+//========================================================================
+// APB_EDP_KL_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB_BASE_ADDR = 0xff020000
+// -----------------------------------------------
+//========================================================================
+// APB_RSA_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB_BASE_ADDR = 0xff030000
+// -----------------------------------------------
+//========================================================================
+// APB_DMA_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB_BASE_ADDR = 0xff060000
+// -----------------------------------------------
+//========================================================================
+// APB_REG_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB_BASE_ADDR = 0xfe00c200
+// -----------------------------------------------
+#define SP_TOP_CTRL0 ((0x0000 << 2) + 0xfe00c200)
+#define SP_TOP_CTRL1 ((0x0001 << 2) + 0xfe00c200)
+#define SP_TOP_CTRL2 ((0x0002 << 2) + 0xfe00c200)
+#define SP_TOP_CTRL3 ((0x0003 << 2) + 0xfe00c200)
+#define SP_TOP_CTRL4 ((0x0004 << 2) + 0xfe00c200)
+#define SP_TOP_CTRL5 ((0x0005 << 2) + 0xfe00c200)
+#define SP_TOP_CTRL6 ((0x0006 << 2) + 0xfe00c200)
+#define SP_TOP_CTRL7 ((0x0007 << 2) + 0xfe00c200)
+#define SP_TOP_CTRL8 ((0x0008 << 2) + 0xfe00c200)
+#define SP_TOP_CTRL9 ((0x0009 << 2) + 0xfe00c200)
+#define SP_TOP_CTRL10_LOCK ((0x000a << 2) + 0xfe00c200)
+#define SP_TOP_CTRL11_LOCK ((0x000b << 2) + 0xfe00c200)
+#define SP_TOP_CTRL12_LOCK ((0x000c << 2) + 0xfe00c200)
+#define SP_TOP_CTRL13_LOCK ((0x000d << 2) + 0xfe00c200)
+#define SP_TOP_CTRL14_LOCK ((0x000e << 2) + 0xfe00c200)
+#define SP_TOP_LOCK_CTRL ((0x000f << 2) + 0xfe00c200)
+#define SP_TOP_STATUS0 ((0x0020 << 2) + 0xfe00c200)
+#define SP_TOP_STATUS1 ((0x0021 << 2) + 0xfe00c200)
+#define SP_TOP_STATUS2 ((0x0022 << 2) + 0xfe00c200)
+#define SP_TOP_STATUS3 ((0x0023 << 2) + 0xfe00c200)
+#define SP_TOP_ACPU_CTRL0 ((0x0010 << 2) + 0xfe00c200)
+#define SP_TOP_ACPU_CTRL1 ((0x0011 << 2) + 0xfe00c200)
+#define SP_TOP_ACPU_CTRL2 ((0x0012 << 2) + 0xfe00c200)
+#define SP_TOP_ACPU_CTRL3 ((0x0013 << 2) + 0xfe00c200)
+#define SP_TOP_ACPU_LOCK_CTRL ((0x0014 << 2) + 0xfe00c200)
+#define SP_TOP_ACPU_STATUS0 ((0x0018 << 2) + 0xfe00c200)
+#define SP_TOP_ACPU_STATUS1 ((0x0019 << 2) + 0xfe00c200)
+#define SP_TOP_ACPU_STATUS2 ((0x001a << 2) + 0xfe00c200)
+#define SP_TOP_ACPU_STATUS3 ((0x001b << 2) + 0xfe00c200)
+#define SP_TOP_INFO0 ((0x0030 << 2) + 0xfe00c200)
+#define SP_TOP_INFO1 ((0x0031 << 2) + 0xfe00c200)
+#define SP_TOP_INFO2 ((0x0032 << 2) + 0xfe00c200)
+#define SP_TOP_INFO3 ((0x0033 << 2) + 0xfe00c200)
+#define SP_TOP_INFO4 ((0x0034 << 2) + 0xfe00c200)
+#define SP_TOP_INFO5 ((0x0035 << 2) + 0xfe00c200)
+#define SP_TOP_INFO6 ((0x0036 << 2) + 0xfe00c200)
+#define SP_TOP_INFO7 ((0x0037 << 2) + 0xfe00c200)
+#define SP_TOP_INFO8 ((0x0038 << 2) + 0xfe00c200)
+#define SP_TOP_INFO9 ((0x0039 << 2) + 0xfe00c200)
+#define SP_TOP_INFO10 ((0x003a << 2) + 0xfe00c200)
+#define SP_TOP_INFO11 ((0x003b << 2) + 0xfe00c200)
+#define SP_TOP_INFO12 ((0x003c << 2) + 0xfe00c200)
+#define SP_TOP_INFO13 ((0x003d << 2) + 0xfe00c200)
+#define SP_TOP_INFO14 ((0x003e << 2) + 0xfe00c200)
+#define SP_TOP_INFO15 ((0x003f << 2) + 0xfe00c200)
+#define SP_EXCEPTION_HANDLER ((0x0040 << 2) + 0xfe00c200)
+#define SP_AOCPU_IRQ_SEL0 ((0x0060 << 2) + 0xfe00c200)
+#define SP_AOCPU_IRQ_SEL1 ((0x0061 << 2) + 0xfe00c200)
+#define SP_AOCPU_IRQ_SEL2 ((0x0062 << 2) + 0xfe00c200)
+#define SP_AOCPU_IRQ_SEL3 ((0x0063 << 2) + 0xfe00c200)
+#define SP_AOCPU_IRQ_SEL4 ((0x0064 << 2) + 0xfe00c200)
+#define SP_AOCPU_IRQ_SEL5 ((0x0065 << 2) + 0xfe00c200)
+#define SP_AOCPU_IRQ_SEL6 ((0x0066 << 2) + 0xfe00c200)
+#define SP_AOCPU_IRQ_SEL7 ((0x0067 << 2) + 0xfe00c200)
+//========================================================================
+// APB_RNG_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB_BASE_ADDR = 0xff0e0000
+// -----------------------------------------------
+//========================================================================
+// APB_OTP_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB_BASE_ADDR = 0xff0f0000
+// -----------------------------------------------
+//
+// Closing file: ../sp/rtl/SP_REG_LIST.h
+//
+//========================================================================
+// APB0_RESET_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000000
+// -----------------------------------------------
+#define RESETCTRL_RESET0 ((0x0000 << 2) + 0xfe000000)
+#define RESETCTRL_RESET1 ((0x0001 << 2) + 0xfe000000)
+#define RESETCTRL_RESET2 ((0x0002 << 2) + 0xfe000000)
+#define RESETCTRL_RESET0_LEVEL ((0x0010 << 2) + 0xfe000000)
+#define RESETCTRL_RESET1_LEVEL ((0x0011 << 2) + 0xfe000000)
+#define RESETCTRL_RESET2_LEVEL ((0x0012 << 2) + 0xfe000000)
+#define RESETCTRL_RESET0_MASK ((0x0020 << 2) + 0xfe000000)
+#define RESETCTRL_RESET1_MASK ((0x0021 << 2) + 0xfe000000)
+#define RESETCTRL_RESET2_MASK ((0x0022 << 2) + 0xfe000000)
+#define RESETCTRL_RESET_HOLD_CYC ((0x0030 << 2) + 0xfe000000)
+#define RESETCTRL_WATCHDOG_CTRL0 ((0x0040 << 2) + 0xfe000000)
+#define RESETCTRL_WATCHDOG_CTRL1 ((0x0041 << 2) + 0xfe000000)
+#define RESETCTRL_WATCHDOG_CNT ((0x0042 << 2) + 0xfe000000)
+#define RESETCTRL_WATCHDOG_CLR ((0x0043 << 2) + 0xfe000000)
+#define RESETCTRL_SEC_RESET0 ((0x0050 << 2) + 0xfe000000)
+#define RESETCTRL_SEC_RESET0_LEVEL ((0x0051 << 2) + 0xfe000000)
+#define RESETCTRL_SEC_RESET0_MASK ((0x0052 << 2) + 0xfe000000)
+//========================================================================
+// APB0_PAD_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000400
+// -----------------------------------------------
+#define PADCTRL_PIN_MUX_REG0 ((0x0000 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG1 ((0x0001 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG3 ((0x0003 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG4 ((0x0004 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG5 ((0x0005 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG6 ((0x0006 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG7 ((0x0007 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG8 ((0x0008 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REG9 ((0x0009 << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REGA ((0x000a << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REGB ((0x000b << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REGC ((0x000c << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REGD ((0x000d << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REGE ((0x000e << 2) + 0xfe000400)
+#define PADCTRL_PIN_MUX_REGF ((0x000f << 2) + 0xfe000400)
+#define PADCTRL_GPIO_IRQ_CTRL0 ((0x0010 << 2) + 0xfe000400)
+#define PADCTRL_GPIO_IRQ_CTRL1 ((0x0011 << 2) + 0xfe000400)
+#define PADCTRL_GPIO_IRQ_CTRL2 ((0x0012 << 2) + 0xfe000400)
+#define PADCTRL_GPIO_IRQ_CTRL3 ((0x0013 << 2) + 0xfe000400)
+#define PADCTRL_GPIO_IRQ_CTRL4 ((0x0014 << 2) + 0xfe000400)
+#define PADCTRL_WORLDSYNC_CTRL0 ((0x0018 << 2) + 0xfe000400)
+#define PADCTRL_GPIO_MSR_CTRL0 ((0x0019 << 2) + 0xfe000400)
+#define PADCTRL_MISC_CTRL0 ((0x001a << 2) + 0xfe000400)
+#define PADCTRL_GPIOD_I ((0x0020 << 2) + 0xfe000400)
+#define PADCTRL_GPIOD_O ((0x0021 << 2) + 0xfe000400)
+#define PADCTRL_GPIOD_OEN ((0x0022 << 2) + 0xfe000400)
+#define PADCTRL_GPIOD_PULL_EN ((0x0023 << 2) + 0xfe000400)
+#define PADCTRL_GPIOD_PULL_UP ((0x0024 << 2) + 0xfe000400)
+#define PADCTRL_GPIOD_DS ((0x0025 << 2) + 0xfe000400)
+#define PADCTRL_GPIOD_VTHX ((0x0026 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_I ((0x0030 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_O ((0x0031 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_OEN ((0x0032 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_PULL_EN ((0x0033 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_PULL_UP ((0x0034 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_VTHX ((0x0036 << 2) + 0xfe000400)
+#define PADCTRL_GPIOB_I ((0x0040 << 2) + 0xfe000400)
+#define PADCTRL_GPIOB_O ((0x0041 << 2) + 0xfe000400)
+#define PADCTRL_GPIOB_OEN ((0x0042 << 2) + 0xfe000400)
+#define PADCTRL_GPIOB_PULL_EN ((0x0043 << 2) + 0xfe000400)
+#define PADCTRL_GPIOB_PULL_UP ((0x0044 << 2) + 0xfe000400)
+#define PADCTRL_GPIOB_DS ((0x0045 << 2) + 0xfe000400)
+#define PADCTRL_GPIOB_VTHX ((0x0046 << 2) + 0xfe000400)
+#define PADCTRL_GPIOC_I ((0x0050 << 2) + 0xfe000400)
+#define PADCTRL_GPIOC_O ((0x0051 << 2) + 0xfe000400)
+#define PADCTRL_GPIOC_OEN ((0x0052 << 2) + 0xfe000400)
+#define PADCTRL_GPIOC_PULL_EN ((0x0053 << 2) + 0xfe000400)
+#define PADCTRL_GPIOC_PULL_UP ((0x0054 << 2) + 0xfe000400)
+#define PADCTRL_GPIOC_DS ((0x0055 << 2) + 0xfe000400)
+#define PADCTRL_GPIOC_VTHX ((0x0056 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_I ((0x0060 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_O ((0x0061 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_OEN ((0x0062 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_PULL_EN ((0x0063 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_PULL_UP ((0x0064 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_DS ((0x0065 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_DS_EXT ((0x0066 << 2) + 0xfe000400)
+#define PADCTRL_GPIOX_VTHX ((0x0067 << 2) + 0xfe000400)
+#define PADCTRL_GPIOM_I ((0x0070 << 2) + 0xfe000400)
+#define PADCTRL_GPIOM_O ((0x0071 << 2) + 0xfe000400)
+#define PADCTRL_GPIOM_OEN ((0x0072 << 2) + 0xfe000400)
+#define PADCTRL_GPIOM_PULL_EN ((0x0073 << 2) + 0xfe000400)
+#define PADCTRL_GPIOM_PULL_UP ((0x0074 << 2) + 0xfe000400)
+#define PADCTRL_GPIOM_DS ((0x0075 << 2) + 0xfe000400)
+#define PADCTRL_GPIOM_VTHX ((0x0076 << 2) + 0xfe000400)
+#define PADCTRL_GPIOA_I ((0x0080 << 2) + 0xfe000400)
+#define PADCTRL_GPIOA_O ((0x0081 << 2) + 0xfe000400)
+#define PADCTRL_GPIOA_OEN ((0x0082 << 2) + 0xfe000400)
+#define PADCTRL_GPIOA_PULL_EN ((0x0083 << 2) + 0xfe000400)
+#define PADCTRL_GPIOA_PULL_UP ((0x0084 << 2) + 0xfe000400)
+#define PADCTRL_GPIOA_DS ((0x0085 << 2) + 0xfe000400)
+#define PADCTRL_GPIOA_VTHX ((0x0086 << 2) + 0xfe000400)
+#define PADCTRL_TESTN_I ((0x0090 << 2) + 0xfe000400)
+#define PADCTRL_TESTN_O ((0x0091 << 2) + 0xfe000400)
+#define PADCTRL_TESTN_OEN ((0x0092 << 2) + 0xfe000400)
+#define PADCTRL_TESTN_PULL_EN ((0x0093 << 2) + 0xfe000400)
+#define PADCTRL_TESTN_PULL_UP ((0x0094 << 2) + 0xfe000400)
+#define PADCTRL_TESTN_DS ((0x0095 << 2) + 0xfe000400)
+#define PADCTRL_MUTE_CTRL ((0x00a0 << 2) + 0xfe000400)
+//========================================================================
+// APB0_CLK_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000800
+// -----------------------------------------------
+#define CLKTREE_SYS_OSCIN_CTRL ((0x0000 << 2) + 0xfe000800)
+#define CLKTREE_RTC_BY_OSCIN_CTRL0 ((0x0001 << 2) + 0xfe000800)
+#define CLKTREE_RTC_BY_OSCIN_CTRL1 ((0x0002 << 2) + 0xfe000800)
+#define CLKTREE_RTC_CTRL ((0x0003 << 2) + 0xfe000800)
+#define CLKTREE_SYS_CLK_CTRL0 ((0x0004 << 2) + 0xfe000800)
+#define CLKTREE_AXI_CLK_CTRL0 ((0x0005 << 2) + 0xfe000800)
+#define CLKTREE_SYS_CLK_EN0 ((0x0006 << 2) + 0xfe000800)
+#define CLKTREE_SYS_CLK_EN1 ((0x0007 << 2) + 0xfe000800)
+#define CLKTREE_SYS_CLK_EN2 ((0x0008 << 2) + 0xfe000800)
+#define CLKTREE_AXI_CLK_EN ((0x0009 << 2) + 0xfe000800)
+#define CLKTREE_DSPA_CLK_EN ((0x000a << 2) + 0xfe000800)
+#define CLKTREE_DSPB_CLK_EN ((0x000b << 2) + 0xfe000800)
+#define CLKTREE_DSPA_CLK_CTRL0 ((0x000c << 2) + 0xfe000800)
+#define CLKTREE_DSPB_CLK_CTRL0 ((0x000d << 2) + 0xfe000800)
+#define CLKTREE_CLK12_24_CTRL ((0x000e << 2) + 0xfe000800)
+#define CLKTREE_GEN_CLK_CTRL ((0x000f << 2) + 0xfe000800)
+#define CLKTREE_TIMESTAMP_CTRL0 ((0x0010 << 2) + 0xfe000800)
+#define CLKTREE_TIMESTAMP_CTRL1 ((0x0011 << 2) + 0xfe000800)
+#define CLKTREE_TIMESTAMP_CTRL2 ((0x0012 << 2) + 0xfe000800)
+#define CLKTREE_TIMESTAMP_VAL0 ((0x0013 << 2) + 0xfe000800)
+#define CLKTREE_TIMESTAMP_VAL1 ((0x0014 << 2) + 0xfe000800)
+#define CLKTREE_TIMEBASE_CTRL0 ((0x0015 << 2) + 0xfe000800)
+#define CLKTREE_TIMEBASE_CTRL1 ((0x0016 << 2) + 0xfe000800)
+#define CLKTREE_SAR_ADC_CLK_CTRL ((0x0030 << 2) + 0xfe000800)
+#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800)
+#define CLKTREE_PWM_CLK_CD_CTRL ((0x0032 << 2) + 0xfe000800)
+#define CLKTREE_PWM_CLK_EF_CTRL ((0x0033 << 2) + 0xfe000800)
+#define CLKTREE_SPICC_CLK_CTRL ((0x0034 << 2) + 0xfe000800)
+#define CLKTREE_TS_CLK_CTRL ((0x0035 << 2) + 0xfe000800)
+#define CLKTREE_SPIFC_CLK_CTRL ((0x0036 << 2) + 0xfe000800)
+#define CLKTREE_USB_BUSCLK_CTRL ((0x0037 << 2) + 0xfe000800)
+#define CLKTREE_SD_EMMC_CLK_CTRL ((0x0038 << 2) + 0xfe000800)
+#define CLKTREE_CECA_CLK_CTRL0 ((0x0039 << 2) + 0xfe000800)
+#define CLKTREE_CECA_CLK_CTRL1 ((0x003a << 2) + 0xfe000800)
+#define CLKTREE_CECB_CLK_CTRL0 ((0x003b << 2) + 0xfe000800)
+#define CLKTREE_CECB_CLK_CTRL1 ((0x003c << 2) + 0xfe000800)
+#define CLKTREE_PSRAM_CLK_CTRL ((0x003d << 2) + 0xfe000800)
+#define CLKTREE_DMC_CLK_CTRL ((0x003e << 2) + 0xfe000800)
+#define CLKTREE_FCLK_DIV1_SEL ((0x003f << 2) + 0xfe000800)
+#define CLKTREE_TST_CTRL0 ((0x0040 << 2) + 0xfe000800)
+#define CLKTREE_WAVE_CLK_CTRL0 ((0x0041 << 2) + 0xfe000800)
+#define CLKTREE_WAVE_CLK_CTRL1 ((0x0042 << 2) + 0xfe000800)
+#define CLKTREE_JPEG_CLK_CTRL ((0x0043 << 2) + 0xfe000800)
+#define CLKTREE_MIPI_ISP_CLK_CTRL ((0x0044 << 2) + 0xfe000800)
+#define CLKTREE_NNA_CLK_CTRL ((0x0045 << 2) + 0xfe000800)
+#define CLKTREE_GDC_CLK_CTRL ((0x0046 << 2) + 0xfe000800)
+#define CLKTREE_GE2D_CLK_CTRL ((0x0047 << 2) + 0xfe000800)
+#define CLKTREE_SD_EMMC_CLK_CTRL1 ((0x0048 << 2) + 0xfe000800)
+#define CLKTREE_ETH_CLK_CTRL ((0x0049 << 2) + 0xfe000800)
+#define CLKTREE_PWM_CLK_GH_CTRL ((0x004a << 2) + 0xfe000800)
+#define CLKTREE_PWM_CLK_IJ_CTRL ((0x004b << 2) + 0xfe000800)
+#define CLKTREE_MBIST_ATSPEED_CTRL ((0x004c << 2) + 0xfe000800)
+#define CLKTREE_SECPU_CLK_CTRL ((0x004d << 2) + 0xfe000800)
+//========================================================================
+// APB0_CEC - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe000c00
+// -----------------------------------------------
+#define CECA_GEN_CNTL ((0x0000 << 2) + 0xfe000c00)
+#define CECA_RW_REG ((0x0001 << 2) + 0xfe000c00)
+#define CECA_INTR_MASKN ((0x0002 << 2) + 0xfe000c00)
+#define CECA_INTR_CLR ((0x0003 << 2) + 0xfe000c00)
+#define CECA_INTR_STAT ((0x0004 << 2) + 0xfe000c00)
+#define CECB_GEN_CNTL ((0x0010 << 2) + 0xfe000c00)
+#define CECB_RW_REG ((0x0011 << 2) + 0xfe000c00)
+#define CECB_INTR_MASKN ((0x0012 << 2) + 0xfe000c00)
+#define CECB_INTR_CLR ((0x0013 << 2) + 0xfe000c00)
+#define CECB_INTR_STAT ((0x0014 << 2) + 0xfe000c00)
+//========================================================================
+// APB0_IR_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001000
+// -----------------------------------------------
+#define IRCTRL_IR_DEC_LDR_ACTIVE ((0x0000 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_LDR_IDLE ((0x0001 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_LDR_REPEAT ((0x0002 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_BIT_0 ((0x0003 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_REG0 ((0x0004 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_FRAME ((0x0005 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_STATUS ((0x0006 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_REG1 ((0x0007 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_LDR_ACTIVE ((0x0010 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_LDR_IDLE ((0x0011 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_LDR_REPEAT ((0x0012 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_BIT_0 ((0x0013 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_REG0 ((0x0014 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_FRAME ((0x0015 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_STATUS ((0x0016 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_REG1 ((0x0017 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_REG2 ((0x0018 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_DURATN2 ((0x0019 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_DURATN3 ((0x001a << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_FRAME1 ((0x001b << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_STATUS1 ((0x001c << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_STATUS2 ((0x001d << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_REG3 ((0x001e << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_FRAME_RSV0 ((0x001f << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_FRAME_RSV1 ((0x0020 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_FILTE ((0x0021 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_IRQ_CTL ((0x0022 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_FIFO_CTL ((0x0023 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_WIDTH_NEW ((0x0024 << 2) + 0xfe001000)
+#define IRCTRL_MF_IR_DEC_REPEAT_DET ((0x0025 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_CNTL0 ((0x0030 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_CNTL1 ((0x0031 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_IIR_THD ((0x0032 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_THD0 ((0x0033 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_THD1 ((0x0034 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_SUM_CNT0 ((0x0035 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_SUM_CNT1 ((0x0036 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_CNT0 ((0x0037 << 2) + 0xfe001000)
+#define IRCTRL_IR_DEC_DEMOD_CNT1 ((0x0038 << 2) + 0xfe001000)
+#define IRCTRL_IR_BLASTER_ADDR0 ((0x0043 << 2) + 0xfe001000)
+#define IRCTRL_IR_BLASTER_ADDR1 ((0x0044 << 2) + 0xfe001000)
+#define IRCTRL_IR_BLASTER_ADDR2 ((0x0045 << 2) + 0xfe001000)
+#define IRCTRL_IR_BLASTER_ADDR3 ((0x0046 << 2) + 0xfe001000)
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001400
+// -----------------------------------------------
+#define I2C_M_A_CONTROL_REG ((0x0000 << 2) + 0xfe001400)
+#define I2C_M_A_SLAVE_ADDR ((0x0001 << 2) + 0xfe001400)
+#define I2C_M_A_TOKEN_LIST0 ((0x0002 << 2) + 0xfe001400)
+#define I2C_M_A_TOKEN_LIST1 ((0x0003 << 2) + 0xfe001400)
+#define I2C_M_A_WDATA_REG0 ((0x0004 << 2) + 0xfe001400)
+#define I2C_M_A_WDATA_REG1 ((0x0005 << 2) + 0xfe001400)
+#define I2C_M_A_RDATA_REG0 ((0x0006 << 2) + 0xfe001400)
+#define I2C_M_A_RDATA_REG1 ((0x0007 << 2) + 0xfe001400)
+#define I2C_M_A_TIMEOUT_TH ((0x0008 << 2) + 0xfe001400)
+#define I2C_M_A_CNTL_DELY1 ((0x0009 << 2) + 0xfe001400)
+#define I2C_M_A_CNTL_DELY2 ((0x000a << 2) + 0xfe001400)
+#define I2C_M_A_LOW_DELY ((0x000b << 2) + 0xfe001400)
+#define I2C_M_A_HIGH_DELY ((0x000c << 2) + 0xfe001400)
+#define I2C_M_A_FIFO_CTRL0 ((0x000d << 2) + 0xfe001400)
+#define I2C_M_A_FIFO_CTRL1 ((0x000e << 2) + 0xfe001400)
+#define I2C_M_A_FIFO_PENDING ((0x000f << 2) + 0xfe001400)
+#define I2C_M_A_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe001400)
+#define I2C_M_A_FIFO_ST0 ((0x0011 << 2) + 0xfe001400)
+//========================================================================
+// APB0_I2C_S - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001800
+// -----------------------------------------------
+#define I2C_S_A_CONTROL_REG ((0x0000 << 2) + 0xfe001800)
+#define I2C_S_A_SEND_REG ((0x0001 << 2) + 0xfe001800)
+#define I2C_S_A_RECV_REG ((0x0002 << 2) + 0xfe001800)
+#define I2C_S_A_CNTL1_REG ((0x0003 << 2) + 0xfe001800)
+//========================================================================
+// APB0_UART_A - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe001c00
+// -----------------------------------------------
+#define UART_A_WFIFO ((0x0000 << 2) + 0xfe001c00)
+#define UART_A_RFIFO ((0x0001 << 2) + 0xfe001c00)
+#define UART_A_CONTROL ((0x0002 << 2) + 0xfe001c00)
+#define UART_A_STATUS ((0x0003 << 2) + 0xfe001c00)
+#define UART_A_MISC ((0x0004 << 2) + 0xfe001c00)
+#define UART_A_REG5 ((0x0005 << 2) + 0xfe001c00)
+//========================================================================
+// APB0_UART_B - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002000
+// -----------------------------------------------
+#define UART_B_WFIFO ((0x0000 << 2) + 0xfe002000)
+#define UART_B_RFIFO ((0x0001 << 2) + 0xfe002000)
+#define UART_B_CONTROL ((0x0002 << 2) + 0xfe002000)
+#define UART_B_STATUS ((0x0003 << 2) + 0xfe002000)
+#define UART_B_MISC ((0x0004 << 2) + 0xfe002000)
+#define UART_B_REG5 ((0x0005 << 2) + 0xfe002000)
+//========================================================================
+// APB0_PWM_AB - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002400
+// -----------------------------------------------
+#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400)
+#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400)
+#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400)
+#define PWMAB_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe002400)
+#define PWMAB_TIME_AB ((0x0004 << 2) + 0xfe002400)
+#define PWMAB_A2 ((0x0005 << 2) + 0xfe002400)
+#define PWMAB_B2 ((0x0006 << 2) + 0xfe002400)
+#define PWMAB_BLINK_AB ((0x0007 << 2) + 0xfe002400)
+#define PWMAB_LOCK_AB ((0x0008 << 2) + 0xfe002400)
+//========================================================================
+// APB0_PWM_CD - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002800
+// -----------------------------------------------
+#define PWMCD_PWM_C ((0x0000 << 2) + 0xfe002800)
+#define PWMCD_PWM_D ((0x0001 << 2) + 0xfe002800)
+#define PWMCD_MISC_REG_CD ((0x0002 << 2) + 0xfe002800)
+#define PWMCD_DELTA_SIGMA_CD ((0x0003 << 2) + 0xfe002800)
+#define PWMCD_TIME_CD ((0x0004 << 2) + 0xfe002800)
+#define PWMCD_C2 ((0x0005 << 2) + 0xfe002800)
+#define PWMCD_D2 ((0x0006 << 2) + 0xfe002800)
+#define PWMCD_BLINK_CD ((0x0007 << 2) + 0xfe002800)
+#define PWMCD_LOCK_CD ((0x0008 << 2) + 0xfe002800)
+//========================================================================
+// APB0_SARADC - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe002c00
+// -----------------------------------------------
+#define SAR_ADC_REG0 ((0x0000 << 2) + 0xfe002c00)
+#define SAR_ADC_CHAN_LIST ((0x0001 << 2) + 0xfe002c00)
+#define SAR_ADC_AVG_CNTL ((0x0002 << 2) + 0xfe002c00)
+#define SAR_ADC_REG3 ((0x0003 << 2) + 0xfe002c00)
+#define SAR_ADC_DELAY ((0x0004 << 2) + 0xfe002c00)
+#define SAR_ADC_LAST_RD ((0x0005 << 2) + 0xfe002c00)
+#define SAR_ADC_FIFO_RD ((0x0006 << 2) + 0xfe002c00)
+#define SAR_ADC_AUX_SW ((0x0007 << 2) + 0xfe002c00)
+#define SAR_ADC_CHAN_10_SW ((0x0008 << 2) + 0xfe002c00)
+#define SAR_ADC_DETECT_IDLE_SW ((0x0009 << 2) + 0xfe002c00)
+#define SAR_ADC_DELTA_10 ((0x000a << 2) + 0xfe002c00)
+#define SAR_ADC_REG11 ((0x000b << 2) + 0xfe002c00)
+#define SAR_ADC_REG12 ((0x000c << 2) + 0xfe002c00)
+#define SAR_ADC_REG13 ((0x000d << 2) + 0xfe002c00)
+#define SAR_ADC_REG14 ((0x000e << 2) + 0xfe002c00)
+#define SAR_ADC_CH0_CTRL1 ((0x0013 << 2) + 0xfe002c00)
+#define SAR_ADC_CH0_CTRL2 ((0x0014 << 2) + 0xfe002c00)
+#define SAR_ADC_CH0_CTRL3 ((0x0015 << 2) + 0xfe002c00)
+#define SAR_ADC_CH1_CTRL1 ((0x0016 << 2) + 0xfe002c00)
+#define SAR_ADC_CH1_CTRL2 ((0x0017 << 2) + 0xfe002c00)
+#define SAR_ADC_CH1_CTRL3 ((0x0018 << 2) + 0xfe002c00)
+#define SAR_ADC_CH2_CTRL1 ((0x0019 << 2) + 0xfe002c00)
+#define SAR_ADC_CH2_CTRL2 ((0x001a << 2) + 0xfe002c00)
+#define SAR_ADC_CH2_CTRL3 ((0x001b << 2) + 0xfe002c00)
+#define SAR_ADC_CH3_CTRL1 ((0x001c << 2) + 0xfe002c00)
+#define SAR_ADC_CH3_CTRL2 ((0x001d << 2) + 0xfe002c00)
+#define SAR_ADC_CH3_CTRL3 ((0x001e << 2) + 0xfe002c00)
+#define SAR_ADC_CH4_CTRL1 ((0x001f << 2) + 0xfe002c00)
+#define SAR_ADC_CH4_CTRL2 ((0x0020 << 2) + 0xfe002c00)
+#define SAR_ADC_CH4_CTRL3 ((0x0021 << 2) + 0xfe002c00)
+#define SAR_ADC_CH5_CTRL1 ((0x0022 << 2) + 0xfe002c00)
+#define SAR_ADC_CH5_CTRL2 ((0x0023 << 2) + 0xfe002c00)
+#define SAR_ADC_CH5_CTRL3 ((0x0024 << 2) + 0xfe002c00)
+#define SAR_ADC_CH6_CTRL1 ((0x0025 << 2) + 0xfe002c00)
+#define SAR_ADC_CH6_CTRL2 ((0x0026 << 2) + 0xfe002c00)
+#define SAR_ADC_CH6_CTRL3 ((0x0027 << 2) + 0xfe002c00)
+#define SAR_ADC_CH7_CTRL1 ((0x0028 << 2) + 0xfe002c00)
+#define SAR_ADC_CH7_CTRL2 ((0x0029 << 2) + 0xfe002c00)
+#define SAR_ADC_CH7_CTRL3 ((0x002a << 2) + 0xfe002c00)
+#define SAR_ADC_HCIC_CTRL1 ((0x002b << 2) + 0xfe002c00)
+#define SAR_ADC_F1_CTRL ((0x002c << 2) + 0xfe002c00)
+#define SAR_ADC_F2_CTRL ((0x002d << 2) + 0xfe002c00)
+#define SAR_ADC_F3_CTRL ((0x002e << 2) + 0xfe002c00)
+#define SAR_ADC_DECI_FILTER_CTRL ((0x002f << 2) + 0xfe002c00)
+#define SAR_ADC_COEF_RAM_CNTL ((0x0030 << 2) + 0xfe002c00)
+#define SAR_ADC_COEF_RAM_DATA ((0x0031 << 2) + 0xfe002c00)
+#define SAR_ADC_FIFO_RD_NEW ((0x0032 << 2) + 0xfe002c00)
+#define SAR_ADC_RAW ((0x0033 << 2) + 0xfe002c00)
+#define SAR_ADC_CHNL0 ((0x0034 << 2) + 0xfe002c00)
+#define SAR_ADC_CHNL1 ((0x0035 << 2) + 0xfe002c00)
+#define SAR_ADC_CHNL2 ((0x0036 << 2) + 0xfe002c00)
+#define SAR_ADC_CHNL3 ((0x0037 << 2) + 0xfe002c00)
+#define SAR_ADC_CHNL4 ((0x0038 << 2) + 0xfe002c00)
+#define SAR_ADC_CHNL5 ((0x0039 << 2) + 0xfe002c00)
+#define SAR_ADC_CHNL6 ((0x003a << 2) + 0xfe002c00)
+#define SAR_ADC_CHNL7 ((0x003b << 2) + 0xfe002c00)
+//========================================================================
+// JTAGCTRL_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003000
+// -----------------------------------------------
+#define JTAGCTRL_CTRL0 ((0x0000 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_CTRL0 ((0x0001 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_ADDR0 ((0x0002 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_ADDR1 ((0x0003 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_ADDR2 ((0x0004 << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_ADDR3 ((0x0005 << 2) + 0xfe003000)
+#define JTEECTRL_PWD_ADDR0 ((0x0006 << 2) + 0xfe003000)
+#define JTEECTRL_PWD_ADDR1 ((0x0007 << 2) + 0xfe003000)
+#define JTEECTRL_PWD_ADDR2 ((0x0008 << 2) + 0xfe003000)
+#define JTEECTRL_PWD_ADDR3 ((0x0009 << 2) + 0xfe003000)
+#define JSECCTRL_PWD_ADDR0 ((0x000a << 2) + 0xfe003000)
+#define JSECCTRL_PWD_ADDR1 ((0x000b << 2) + 0xfe003000)
+#define JSECCTRL_PWD_ADDR2 ((0x000c << 2) + 0xfe003000)
+#define JSECCTRL_PWD_ADDR3 ((0x000d << 2) + 0xfe003000)
+#define JTAGCTRL_PWD_STS ((0x000e << 2) + 0xfe003000)
+//========================================================================
+// APB0_MSR_CLK - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003400
+// -----------------------------------------------
+#define MSR_CLK_REG0 ((0x0000 << 2) + 0xfe003400)
+#define MSR_CLK_REG1 ((0x0001 << 2) + 0xfe003400)
+#define MSR_CLK_REG2 ((0x0002 << 2) + 0xfe003400)
+#define MSR_CLK_REG3 ((0x0003 << 2) + 0xfe003400)
+#define MSR_CLK_REG4 ((0x0004 << 2) + 0xfe003400)
+#define MSR_CLK_REG5 ((0x0005 << 2) + 0xfe003400)
+#define MSR_CLK_DUTY ((0x0006 << 2) + 0xfe003400)
+//========================================================================
+// APB0_SPICCA_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003800
+// -----------------------------------------------
+#define SPICC_A_RXDATA ((0x0000 << 2) + 0xfe003800)
+#define SPICC_A_TXDATA ((0x0001 << 2) + 0xfe003800)
+#define SPICC_A_CONREG ((0x0002 << 2) + 0xfe003800)
+#define SPICC_A_INTREG ((0x0003 << 2) + 0xfe003800)
+#define SPICC_A_DMAREG ((0x0004 << 2) + 0xfe003800)
+#define SPICC_A_STATREG ((0x0005 << 2) + 0xfe003800)
+#define SPICC_A_PERIODREG ((0x0006 << 2) + 0xfe003800)
+#define SPICC_A_TESTREG ((0x0007 << 2) + 0xfe003800)
+#define SPICC_A_DRADDR ((0x0008 << 2) + 0xfe003800)
+#define SPICC_A_DWADDR ((0x0009 << 2) + 0xfe003800)
+#define SPICC_A_LD_CNTL0 ((0x000a << 2) + 0xfe003800)
+#define SPICC_A_LD_CNTL1 ((0x000b << 2) + 0xfe003800)
+#define SPICC_A_LD_RADDR ((0x000c << 2) + 0xfe003800)
+#define SPICC_A_LD_WADDR ((0x000d << 2) + 0xfe003800)
+#define SPICC_A_ENHANCE_CNTL ((0x000e << 2) + 0xfe003800)
+#define SPICC_A_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe003800)
+#define SPICC_A_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe003800)
+//========================================================================
+// APB0_SPICCB_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe003c00
+// -----------------------------------------------
+#define SPICC_B_RXDATA ((0x0000 << 2) + 0xfe003c00)
+#define SPICC_B_TXDATA ((0x0001 << 2) + 0xfe003c00)
+#define SPICC_B_CONREG ((0x0002 << 2) + 0xfe003c00)
+#define SPICC_B_INTREG ((0x0003 << 2) + 0xfe003c00)
+#define SPICC_B_DMAREG ((0x0004 << 2) + 0xfe003c00)
+#define SPICC_B_STATREG ((0x0005 << 2) + 0xfe003c00)
+#define SPICC_B_PERIODREG ((0x0006 << 2) + 0xfe003c00)
+#define SPICC_B_TESTREG ((0x0007 << 2) + 0xfe003c00)
+#define SPICC_B_DRADDR ((0x0008 << 2) + 0xfe003c00)
+#define SPICC_B_DWADDR ((0x0009 << 2) + 0xfe003c00)
+#define SPICC_B_LD_CNTL0 ((0x000a << 2) + 0xfe003c00)
+#define SPICC_B_LD_CNTL1 ((0x000b << 2) + 0xfe003c00)
+#define SPICC_B_LD_RADDR ((0x000c << 2) + 0xfe003c00)
+#define SPICC_B_LD_WADDR ((0x000d << 2) + 0xfe003c00)
+#define SPICC_B_ENHANCE_CNTL ((0x000e << 2) + 0xfe003c00)
+#define SPICC_B_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe003c00)
+#define SPICC_B_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe003c00)
+//========================================================================
+// USBCTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe004000
+// -----------------------------------------------
+#define USB_CTRL0 ((0x0000 << 2) + 0xfe004000)
+#define USB_CTRL1 ((0x0001 << 2) + 0xfe004000)
+#define USB_CTRL2 ((0x0002 << 2) + 0xfe004000)
+#define USB_CTRL3 ((0x0003 << 2) + 0xfe004000)
+#define USB_CTRL4 ((0x0004 << 2) + 0xfe004000)
+#define USB_CTRL5 ((0x0005 << 2) + 0xfe004000)
+#define USB_CTRL6 ((0x0006 << 2) + 0xfe004000)
+#define USB_CTRL7 ((0x0007 << 2) + 0xfe004000)
+#define USB_CTRL8 ((0x0008 << 2) + 0xfe004000)
+#define USB_CTRL9 ((0x0009 << 2) + 0xfe004000)
+#define USB_CTRL10 ((0x000a << 2) + 0xfe004000)
+#define USB_CTRL11 ((0x000b << 2) + 0xfe004000)
+#define USB_CTRL12 ((0x000c << 2) + 0xfe004000)
+#define USB_CTRL13 ((0x000d << 2) + 0xfe004000)
+#define USB_CTRL14 ((0x000e << 2) + 0xfe004000)
+#define USB_CTRL15 ((0x000f << 2) + 0xfe004000)
+#define USB_CTRL16 ((0x0010 << 2) + 0xfe004000)
+#define USB_CTRL17 ((0x0011 << 2) + 0xfe004000)
+#define USB_CTRL18 ((0x0012 << 2) + 0xfe004000)
+#define USB_CTRL19 ((0x0013 << 2) + 0xfe004000)
+#define USB_CTRL20 ((0x0014 << 2) + 0xfe004000)
+#define USB_CTRL21 ((0x0015 << 2) + 0xfe004000)
+#define USB_CTRL22 ((0x0016 << 2) + 0xfe004000)
+#define USB_CTRL23 ((0x0017 << 2) + 0xfe004000)
+#define USB_CTRL24 ((0x0018 << 2) + 0xfe004000)
+#define USB_CTRL25 ((0x0019 << 2) + 0xfe004000)
+#define USB_CTRL26 ((0x001a << 2) + 0xfe004000)
+#define USB_CTRL27 ((0x001b << 2) + 0xfe004000)
+#define USB_CTRL28 ((0x001c << 2) + 0xfe004000)
+#define USB_CTRL29 ((0x001d << 2) + 0xfe004000)
+#define USB_CTRL30 ((0x001e << 2) + 0xfe004000)
+#define USB_CTRL31 ((0x001f << 2) + 0xfe004000)
+//========================================================================
+// APB0_ACODEC_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe004800
+// -----------------------------------------------
+#define ACODEC_0 ((0x0000 << 2) + 0xfe004800)
+#define ACODEC_1 ((0x0001 << 2) + 0xfe004800)
+#define ACODEC_2 ((0x0002 << 2) + 0xfe004800)
+#define ACODEC_3 ((0x0003 << 2) + 0xfe004800)
+#define ACODEC_4 ((0x0004 << 2) + 0xfe004800)
+#define ACODEC_5 ((0x0005 << 2) + 0xfe004800)
+#define ACODEC_6 ((0x0006 << 2) + 0xfe004800)
+#define ACODEC_7 ((0x0007 << 2) + 0xfe004800)
+#define ACODEC_8 ((0x0008 << 2) + 0xfe004800)
+#define ACODEC_9 ((0x0009 << 2) + 0xfe004800)
+#define ACODEC_STS0 ((0x0010 << 2) + 0xfe004800)
+//========================================================================
+// APB0_TEMP_SENSOR - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe004c00
+// -----------------------------------------------
+#define TS_CFG_REG1 ((0x0001 << 2) + 0xfe004c00)
+#define TS_CFG_REG2 ((0x0002 << 2) + 0xfe004c00)
+#define TS_CFG_REG3 ((0x0003 << 2) + 0xfe004c00)
+#define TS_CFG_REG4 ((0x0004 << 2) + 0xfe004c00)
+#define TS_CFG_REG5 ((0x0005 << 2) + 0xfe004c00)
+#define TS_CFG_REG6 ((0x0006 << 2) + 0xfe004c00)
+#define TS_CFG_REG7 ((0x0007 << 2) + 0xfe004c00)
+#define TS_STAT0 ((0x0010 << 2) + 0xfe004c00)
+#define TS_STAT1 ((0x0011 << 2) + 0xfe004c00)
+#define TS_STAT2 ((0x0012 << 2) + 0xfe004c00)
+#define TS_STAT3 ((0x0013 << 2) + 0xfe004c00)
+#define TS_STAT4 ((0x0014 << 2) + 0xfe004c00)
+#define TS_STAT5 ((0x0015 << 2) + 0xfe004c00)
+#define TS_STAT6 ((0x0016 << 2) + 0xfe004c00)
+#define TS_STAT7 ((0x0017 << 2) + 0xfe004c00)
+#define TS_STAT8 ((0x0018 << 2) + 0xfe004c00)
+#define TS_STAT9 ((0x0019 << 2) + 0xfe004c00)
+//========================================================================
+// APB0_KL_EFUSE_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005000
+// -----------------------------------------------
+//
+// Reading file: ../crypto/crypto_reg.h
+//
+#define OTP_TEE_RDY ((0x0000 << 2) + 0xfe005000)
+#define OTP_TEE_CHK ((0x0001 << 2) + 0xfe005000)
+#define OTP_TEE_CFG ((0x0002 << 2) + 0xfe005000)
+#define OTP_TEE_WR_DAT0 ((0x0004 << 2) + 0xfe005000)
+#define OTP_TEE_WR_DAT1 ((0x0005 << 2) + 0xfe005000)
+#define OTP_TEE_WR_DAT2 ((0x0006 << 2) + 0xfe005000)
+#define OTP_TEE_WR_DAT3 ((0x0007 << 2) + 0xfe005000)
+#define OTP_TEE_RD_DAT0 ((0x0008 << 2) + 0xfe005000)
+#define OTP_TEE_RD_DAT1 ((0x0009 << 2) + 0xfe005000)
+#define OTP_TEE_RD_DAT2 ((0x000a << 2) + 0xfe005000)
+#define OTP_TEE_RD_DAT3 ((0x000b << 2) + 0xfe005000)
+#define OTP_RMA_PW0 ((0x000c << 2) + 0xfe005000)
+#define OTP_RMA_PW1 ((0x000d << 2) + 0xfe005000)
+#define OTP_RMA_PW2 ((0x000e << 2) + 0xfe005000)
+#define OTP_RMA_PW3 ((0x000f << 2) + 0xfe005000)
+#define OTP_REE_RDY ((0x0010 << 2) + 0xfe005000)
+#define OTP_REE_CHK ((0x0011 << 2) + 0xfe005000)
+#define OTP_REE_CFG ((0x0012 << 2) + 0xfe005000)
+#define OTP_REE_RD_DAT0 ((0x0014 << 2) + 0xfe005000)
+#define OTP_REE_RD_DAT1 ((0x0015 << 2) + 0xfe005000)
+#define OTP_REE_RD_DAT2 ((0x0016 << 2) + 0xfe005000)
+#define OTP_REE_RD_DAT3 ((0x0017 << 2) + 0xfe005000)
+#define OTP_SEC_RDY ((0x0020 << 2) + 0xfe005000)
+#define OTP_SEC_CHK ((0x0021 << 2) + 0xfe005000)
+#define OTP_SEC_CFG ((0x0022 << 2) + 0xfe005000)
+#define OTP_SEC_WR_DAT0 ((0x0024 << 2) + 0xfe005000)
+#define OTP_SEC_WR_DAT1 ((0x0025 << 2) + 0xfe005000)
+#define OTP_SEC_WR_DAT2 ((0x0026 << 2) + 0xfe005000)
+#define OTP_SEC_WR_DAT3 ((0x0027 << 2) + 0xfe005000)
+#define OTP_SEC_RD_DAT0 ((0x0028 << 2) + 0xfe005000)
+#define OTP_SEC_RD_DAT1 ((0x0029 << 2) + 0xfe005000)
+#define OTP_SEC_RD_DAT2 ((0x002a << 2) + 0xfe005000)
+#define OTP_SEC_RD_DAT3 ((0x002b << 2) + 0xfe005000)
+#define OTP_LIC0 ((0x0018 << 2) + 0xfe005000)
+#define OTP_LIC1 ((0x0019 << 2) + 0xfe005000)
+#define OTP_LIC2 ((0x001a << 2) + 0xfe005000)
+#define OTP_LIC3 ((0x001b << 2) + 0xfe005000)
+#define RNG_SEC_CONFIG_REG1 ((0x0041 << 2) + 0xfe005000)
+#define RNG_SEC_CONFIG_REG2 ((0x0042 << 2) + 0xfe005000)
+#define RNG_SEC_DATA ((0x0044 << 2) + 0xfe005000)
+#define RNG_SEC_STS ((0x0045 << 2) + 0xfe005000)
+#define RNG_USR_DATA ((0x0046 << 2) + 0xfe005000)
+#define RNG_USR_STS ((0x0047 << 2) + 0xfe005000)
+#define RNG_ENCLAVE_CONFIG_REG1 ((0x0048 << 2) + 0xfe005000)
+#define RNG_ENCLAVE_CONFIG_REG2 ((0x0049 << 2) + 0xfe005000)
+#define RNG_ENCLAVE_DATA ((0x004a << 2) + 0xfe005000)
+#define RNG_ENCLAVE_STS ((0x004b << 2) + 0xfe005000)
+#define KTE_SLOT0 ((0x0060 << 2) + 0xfe005000)
+#define KTE_SLOT1 ((0x0061 << 2) + 0xfe005000)
+#define KTE_SLOT2 ((0x0062 << 2) + 0xfe005000)
+#define KTE_SLOT3 ((0x0063 << 2) + 0xfe005000)
+#define KTE_SLOT4 ((0x0064 << 2) + 0xfe005000)
+#define KTE_SLOT5 ((0x0065 << 2) + 0xfe005000)
+#define KTE_SLOT6 ((0x0066 << 2) + 0xfe005000)
+#define KTE_SLOT7 ((0x0067 << 2) + 0xfe005000)
+#define KTE_SLOT8 ((0x0068 << 2) + 0xfe005000)
+#define KTE_SLOT9 ((0x0069 << 2) + 0xfe005000)
+#define KTE_SLOT10 ((0x006a << 2) + 0xfe005000)
+#define KTE_SLOT11 ((0x006b << 2) + 0xfe005000)
+#define MKL_TEE_RDY ((0x0080 << 2) + 0xfe005000)
+#define MKL_TEE_CHK ((0x0081 << 2) + 0xfe005000)
+#define MKL_TEE_CFG ((0x0082 << 2) + 0xfe005000)
+#define MKL_TEE_EK ((0x0084 << 2) + 0xfe005000)
+#define MKL_REE_RDY ((0x00a0 << 2) + 0xfe005000)
+#define MKL_REE_CHK ((0x00a1 << 2) + 0xfe005000)
+#define MKL_REE_CFG ((0x00a2 << 2) + 0xfe005000)
+#define MKL_REE_EK ((0x00a4 << 2) + 0xfe005000)
+#define MKL_SEC_RDY ((0x00c0 << 2) + 0xfe005000)
+#define MKL_SEC_CHK ((0x00c1 << 2) + 0xfe005000)
+#define MKL_SEC_CFG ((0x00c2 << 2) + 0xfe005000)
+#define MKL_SEC_EK ((0x00c4 << 2) + 0xfe005000)
+//
+// Closing file: ../crypto/crypto_reg.h
+//
+//========================================================================
+// APB0_PWM_EF - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005400
+// -----------------------------------------------
+#define PWMEF_PWM_E ((0x0000 << 2) + 0xfe005400)
+#define PWMEF_PWM_F ((0x0001 << 2) + 0xfe005400)
+#define PWMEF_MISC_REG_EF ((0x0002 << 2) + 0xfe005400)
+#define PWMEF_DELTA_SIGMA_EF ((0x0003 << 2) + 0xfe005400)
+#define PWMEF_TIME_EF ((0x0004 << 2) + 0xfe005400)
+#define PWMEF_E2 ((0x0005 << 2) + 0xfe005400)
+#define PWMEF_F2 ((0x0006 << 2) + 0xfe005400)
+#define PWMEF_BLINK_EF ((0x0007 << 2) + 0xfe005400)
+#define PWMEF_LOCK_EF ((0x0008 << 2) + 0xfe005400)
+//========================================================================
+// APB0_SYS_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005800
+// -----------------------------------------------
+#define SYSCTRL_METAL_REV0 ((0x0000 << 2) + 0xfe005800)
+#define SYSCTRL_METAL_REV1 ((0x0001 << 2) + 0xfe005800)
+#define SYSCTRL_METAL_REV2 ((0x0002 << 2) + 0xfe005800)
+//`define SYSCTRL_PROD_ENABLE 8'h0a
+#define SYSCTRL_CHIP_ID ((0x000b << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE1_REG0 ((0x0010 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE1_STICKY_REG0 ((0x0011 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE1_SEC_REG0 ((0x0012 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE1_STICKY_SEC_REG0 ((0x0013 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE_REG0 ((0x0014 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE_REG1 ((0x0015 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE_SEC_REG0 ((0x0016 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE_STICKY_REG0 ((0x0017 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE_STICKY_REG1 ((0x0018 << 2) + 0xfe005800)
+#define SYSCTRL_WRITEONCE_STICKY_SEC_REG0 ((0x0019 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERA_CTRL ((0x0030 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERA ((0x0031 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERB_CTRL ((0x0032 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERB ((0x0033 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERC_CTRL ((0x0034 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERC ((0x0035 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERD_CTRL ((0x0036 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERD ((0x0037 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_TIMERA_CTRL ((0x0038 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_TIMERA ((0x0039 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERE_CTRL ((0x0040 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERE ((0x0041 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERE_HI ((0x0042 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERF_CTRL ((0x0043 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERF ((0x0044 << 2) + 0xfe005800)
+#define SYSCTRL_TIMERF_HI ((0x0045 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_TIMERE_CTRL ((0x0046 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_TIMERE ((0x0047 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_TIMERE_HI ((0x0048 << 2) + 0xfe005800)
+#define SYSCTRL_OSC_RING_CTRL0 ((0x0050 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_DDR_AXI_SEL ((0x0051 << 2) + 0xfe005800)
+#define SYSCTRL_AM2AXI_CTRL0 ((0x0052 << 2) + 0xfe005800)
+#define SYSCTRL_AM2AXI_STS ((0x0053 << 2) + 0xfe005800)
+#define SYSCTRL_OSC_RING_CTRL1 ((0x0054 << 2) + 0xfe005800)
+#define SYSCTRL_OSC_RING_CTRL2 ((0x0055 << 2) + 0xfe005800)
+#define SYSCTRL_POC ((0x0060 << 2) + 0xfe005800)
+#define SYSCTRL_TOP_SPSRAM_EMA_CTL ((0x0070 << 2) + 0xfe005800)
+#define SYSCTRL_TOP_DP1CLK_EMA_CTL ((0x0071 << 2) + 0xfe005800)
+#define SYSCTRL_TOP_DP2CLK_EMA_CTL ((0x0072 << 2) + 0xfe005800)
+#define SYSCTRL_TOP_ROM_EMA_CTL ((0x0073 << 2) + 0xfe005800)
+#define SYSCTRL_CPU_SPSRAM_EMA_CTL ((0x0074 << 2) + 0xfe005800)
+#define SYSCTRL_CPU_DP1CLK_EMA_CTL ((0x0075 << 2) + 0xfe005800)
+#define SYSCTRL_CPU_DP2CLK_EMA_CTL ((0x0076 << 2) + 0xfe005800)
+#define SYSCTRL_NNA_SPSRAM_EMA_CTL ((0x0078 << 2) + 0xfe005800)
+#define SYSCTRL_NNA_DP1CLK_EMA_CTL ((0x0079 << 2) + 0xfe005800)
+#define SYSCTRL_NNA_DP2CLK_EMA_CTL ((0x007a << 2) + 0xfe005800)
+#define SYSCTRL_DDR_TEST_CTL ((0x007c << 2) + 0xfe005800)
+//`define SYSCTRL_PROD_PWD_VALUE0 8'h80
+//`define SYSCTRL_PROD_PWD_VALUE1 8'h81
+//`define SYSCTRL_PROD_PWD_VALUE2 8'h82
+//`define SYSCTRL_PROD_PWD_VALUE3 8'h83
+//`define SYSCTRL_PROD_STATUS 8'h84
+#define SYSCTRL_DEBUG_REG0 ((0x0090 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG1 ((0x0091 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG2 ((0x0092 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG3 ((0x0093 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG4 ((0x0094 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG5 ((0x0095 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG6 ((0x0096 << 2) + 0xfe005800)
+#define SYSCTRL_DEBUG_REG7 ((0x0097 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG0 ((0x00a0 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG1 ((0x00a1 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG2 ((0x00a2 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG3 ((0x00a3 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG4 ((0x00a4 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG5 ((0x00a5 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG6 ((0x00a6 << 2) + 0xfe005800)
+#define SYSCTRL_STATUS_REG7 ((0x00a7 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG0 ((0x00b0 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG1 ((0x00b1 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG2 ((0x00b2 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG3 ((0x00b3 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG4 ((0x00b4 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG5 ((0x00b5 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG6 ((0x00b6 << 2) + 0xfe005800)
+#define SYSCTRL_STICKY_REG7 ((0x00b7 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG0 ((0x00c0 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG1 ((0x00c1 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG2 ((0x00c2 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG3 ((0x00c3 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG4 ((0x00c4 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG5 ((0x00c5 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG6 ((0x00c6 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG7 ((0x00c7 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG8 ((0x00c8 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG9 ((0x00c9 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG10 ((0x00ca << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG11 ((0x00cb << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG12 ((0x00cc << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG13 ((0x00cd << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG14 ((0x00ce << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG15 ((0x00cf << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG16 ((0x00d0 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG17 ((0x00d1 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG18 ((0x00d2 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG19 ((0x00d3 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG20 ((0x00d4 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG21 ((0x00d5 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG22 ((0x00d6 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STATUS_REG23 ((0x00d7 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG0 ((0x00e0 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG1 ((0x00e1 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG2 ((0x00e2 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG3 ((0x00e3 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG4 ((0x00e4 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG5 ((0x00e5 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG6 ((0x00e6 << 2) + 0xfe005800)
+#define SYSCTRL_SEC_STICKY_REG7 ((0x00e7 << 2) + 0xfe005800)
+#define SYSCTRL_MSG_INDEX0_STICKY ((0x00f0 << 2) + 0xfe005800)
+#define SYSCTRL_MSG_INDEX1_STICKY ((0x00f1 << 2) + 0xfe005800)
+#define SYSCTRL_MSG_INDEX2_STICKY ((0x00f2 << 2) + 0xfe005800)
+#define SYSCTRL_MSG_INDEX3_STICKY ((0x00f3 << 2) + 0xfe005800)
+//========================================================================
+// APB0_I2C_M_B - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe005c00
+// -----------------------------------------------
+#define I2C_M_B_CONTROL_REG ((0x0000 << 2) + 0xfe005c00)
+#define I2C_M_B_SLAVE_ADDR ((0x0001 << 2) + 0xfe005c00)
+#define I2C_M_B_TOKEN_LIST0 ((0x0002 << 2) + 0xfe005c00)
+#define I2C_M_B_TOKEN_LIST1 ((0x0003 << 2) + 0xfe005c00)
+#define I2C_M_B_WDATA_REG0 ((0x0004 << 2) + 0xfe005c00)
+#define I2C_M_B_WDATA_REG1 ((0x0005 << 2) + 0xfe005c00)
+#define I2C_M_B_RDATA_REG0 ((0x0006 << 2) + 0xfe005c00)
+#define I2C_M_B_RDATA_REG1 ((0x0007 << 2) + 0xfe005c00)
+#define I2C_M_B_TIMEOUT_TH ((0x0008 << 2) + 0xfe005c00)
+#define I2C_M_B_CNTL_DELY1 ((0x0009 << 2) + 0xfe005c00)
+#define I2C_M_B_CNTL_DELY2 ((0x000a << 2) + 0xfe005c00)
+#define I2C_M_B_LOW_DELY ((0x000b << 2) + 0xfe005c00)
+#define I2C_M_B_HIGH_DELY ((0x000c << 2) + 0xfe005c00)
+#define I2C_M_B_FIFO_CTRL0 ((0x000d << 2) + 0xfe005c00)
+#define I2C_M_B_FIFO_CTRL1 ((0x000e << 2) + 0xfe005c00)
+#define I2C_M_B_FIFO_PENDING ((0x000f << 2) + 0xfe005c00)
+#define I2C_M_B_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe005c00)
+#define I2C_M_B_FIFO_ST0 ((0x0011 << 2) + 0xfe005c00)
+//========================================================================
+// APB0_DMA - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006000
+// -----------------------------------------------
+//TODO
+//========================================================================
+// APB0_IRQ_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006400
+// -----------------------------------------------
+#define IRQCTRL_IRQ_INV0 ((0x0000 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_INV1 ((0x0001 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_INV2 ((0x0002 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_INV3 ((0x0003 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_INV4 ((0x0004 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_INV5 ((0x0005 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_INV6 ((0x0006 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_INV7 ((0x0007 << 2) + 0xfe006400)
+#define IRQCTRL_MASK0_GIC ((0x0010 << 2) + 0xfe006400)
+#define IRQCTRL_MASK1_GIC ((0x0011 << 2) + 0xfe006400)
+#define IRQCTRL_MASK2_GIC ((0x0012 << 2) + 0xfe006400)
+#define IRQCTRL_MASK3_GIC ((0x0013 << 2) + 0xfe006400)
+#define IRQCTRL_MASK4_GIC ((0x0014 << 2) + 0xfe006400)
+#define IRQCTRL_MASK5_GIC ((0x0015 << 2) + 0xfe006400)
+#define IRQCTRL_MASK6_GIC ((0x0016 << 2) + 0xfe006400)
+#define IRQCTRL_MASK7_GIC ((0x0017 << 2) + 0xfe006400)
+#define IRQCTRL_MASK0_DSP ((0x0020 << 2) + 0xfe006400)
+#define IRQCTRL_MASK1_DSP ((0x0021 << 2) + 0xfe006400)
+#define IRQCTRL_MASK2_DSP ((0x0022 << 2) + 0xfe006400)
+#define IRQCTRL_MASK3_DSP ((0x0023 << 2) + 0xfe006400)
+#define IRQCTRL_MASK4_DSP ((0x0024 << 2) + 0xfe006400)
+#define IRQCTRL_MASK5_DSP ((0x0025 << 2) + 0xfe006400)
+#define IRQCTRL_MASK6_DSP ((0x0026 << 2) + 0xfe006400)
+#define IRQCTRL_MASK7_DSP ((0x0027 << 2) + 0xfe006400)
+#define IRQCTRL_MASK0_PWRCTRL ((0x0030 << 2) + 0xfe006400)
+#define IRQCTRL_MASK1_PWRCTRL ((0x0031 << 2) + 0xfe006400)
+#define IRQCTRL_MASK2_PWRCTRL ((0x0032 << 2) + 0xfe006400)
+#define IRQCTRL_MASK3_PWRCTRL ((0x0033 << 2) + 0xfe006400)
+#define IRQCTRL_MASK4_PWRCTRL ((0x0034 << 2) + 0xfe006400)
+#define IRQCTRL_MASK5_PWRCTRL ((0x0035 << 2) + 0xfe006400)
+#define IRQCTRL_MASK6_PWRCTRL ((0x0036 << 2) + 0xfe006400)
+#define IRQCTRL_MASK7_PWRCTRL ((0x0037 << 2) + 0xfe006400)
+#define IRQCTRL_MASK0_AOCPU ((0x0040 << 2) + 0xfe006400)
+#define IRQCTRL_MASK1_AOCPU ((0x0041 << 2) + 0xfe006400)
+#define IRQCTRL_MASK2_AOCPU ((0x0042 << 2) + 0xfe006400)
+#define IRQCTRL_MASK3_AOCPU ((0x0043 << 2) + 0xfe006400)
+#define IRQCTRL_MASK4_AOCPU ((0x0044 << 2) + 0xfe006400)
+#define IRQCTRL_MASK5_AOCPU ((0x0045 << 2) + 0xfe006400)
+#define IRQCTRL_MASK6_AOCPU ((0x0046 << 2) + 0xfe006400)
+#define IRQCTRL_MASK7_AOCPU ((0x0047 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_MODE0 ((0x0050 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_MODE1 ((0x0051 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_MODE2 ((0x0052 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_MODE3 ((0x0053 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_MODE4 ((0x0054 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_MODE5 ((0x0055 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_MODE6 ((0x0056 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_MODE7 ((0x0057 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_LATCH0 ((0x0060 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_LATCH1 ((0x0061 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_LATCH2 ((0x0062 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_LATCH3 ((0x0063 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_LATCH4 ((0x0064 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_LATCH5 ((0x0065 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_LATCH6 ((0x0066 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_LATCH7 ((0x0067 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_LATCH_CLR0 ((0x0070 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_LATCH_CLR1 ((0x0071 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_LATCH_CLR2 ((0x0072 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_LATCH_CLR3 ((0x0073 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_LATCH_CLR4 ((0x0074 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_LATCH_CLR5 ((0x0075 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_LATCH_CLR6 ((0x0076 << 2) + 0xfe006400)
+#define IRQCTRL_IRQ_LATCH_CLR7 ((0x0077 << 2) + 0xfe006400)
+#define IRQCTRL_LOCK_BIT ((0x0080 << 2) + 0xfe006400)
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006800
+// -----------------------------------------------
+#define I2C_M_C_CONTROL_REG ((0x0000 << 2) + 0xfe006800)
+#define I2C_M_C_SLAVE_ADDR ((0x0001 << 2) + 0xfe006800)
+#define I2C_M_C_TOKEN_LIST0 ((0x0002 << 2) + 0xfe006800)
+#define I2C_M_C_TOKEN_LIST1 ((0x0003 << 2) + 0xfe006800)
+#define I2C_M_C_WDATA_REG0 ((0x0004 << 2) + 0xfe006800)
+#define I2C_M_C_WDATA_REG1 ((0x0005 << 2) + 0xfe006800)
+#define I2C_M_C_RDATA_REG0 ((0x0006 << 2) + 0xfe006800)
+#define I2C_M_C_RDATA_REG1 ((0x0007 << 2) + 0xfe006800)
+#define I2C_M_C_TIMEOUT_TH ((0x0008 << 2) + 0xfe006800)
+#define I2C_M_C_CNTL_DELY1 ((0x0009 << 2) + 0xfe006800)
+#define I2C_M_C_CNTL_DELY2 ((0x000a << 2) + 0xfe006800)
+#define I2C_M_C_LOW_DELY ((0x000b << 2) + 0xfe006800)
+#define I2C_M_C_HIGH_DELY ((0x000c << 2) + 0xfe006800)
+#define I2C_M_C_FIFO_CTRL0 ((0x000d << 2) + 0xfe006800)
+#define I2C_M_C_FIFO_CTRL1 ((0x000e << 2) + 0xfe006800)
+#define I2C_M_C_FIFO_PENDING ((0x000f << 2) + 0xfe006800)
+#define I2C_M_C_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe006800)
+#define I2C_M_C_FIFO_ST0 ((0x0011 << 2) + 0xfe006800)
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe006c00
+// -----------------------------------------------
+#define I2C_M_D_CONTROL_REG ((0x0000 << 2) + 0xfe006c00)
+#define I2C_M_D_SLAVE_ADDR ((0x0001 << 2) + 0xfe006c00)
+#define I2C_M_D_TOKEN_LIST0 ((0x0002 << 2) + 0xfe006c00)
+#define I2C_M_D_TOKEN_LIST1 ((0x0003 << 2) + 0xfe006c00)
+#define I2C_M_D_WDATA_REG0 ((0x0004 << 2) + 0xfe006c00)
+#define I2C_M_D_WDATA_REG1 ((0x0005 << 2) + 0xfe006c00)
+#define I2C_M_D_RDATA_REG0 ((0x0006 << 2) + 0xfe006c00)
+#define I2C_M_D_RDATA_REG1 ((0x0007 << 2) + 0xfe006c00)
+#define I2C_M_D_TIMEOUT_TH ((0x0008 << 2) + 0xfe006c00)
+#define I2C_M_D_CNTL_DELY1 ((0x0009 << 2) + 0xfe006c00)
+#define I2C_M_D_CNTL_DELY2 ((0x000a << 2) + 0xfe006c00)
+#define I2C_M_D_LOW_DELY ((0x000b << 2) + 0xfe006c00)
+#define I2C_M_D_HIGH_DELY ((0x000c << 2) + 0xfe006c00)
+#define I2C_M_D_FIFO_CTRL0 ((0x000d << 2) + 0xfe006c00)
+#define I2C_M_D_FIFO_CTRL1 ((0x000e << 2) + 0xfe006c00)
+#define I2C_M_D_FIFO_PENDING ((0x000f << 2) + 0xfe006c00)
+#define I2C_M_D_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe006c00)
+#define I2C_M_D_FIFO_ST0 ((0x0011 << 2) + 0xfe006c00)
+//========================================================================
+// APB0_UART_C - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007000
+// -----------------------------------------------
+#define UART_C_WFIFO ((0x0000 << 2) + 0xfe007000)
+#define UART_C_RFIFO ((0x0001 << 2) + 0xfe007000)
+#define UART_C_CONTROL ((0x0002 << 2) + 0xfe007000)
+#define UART_C_STATUS ((0x0003 << 2) + 0xfe007000)
+#define UART_C_MISC ((0x0004 << 2) + 0xfe007000)
+#define UART_C_REG5 ((0x0005 << 2) + 0xfe007000)
+//========================================================================
+// CPUCTRL_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007400
+// -----------------------------------------------
+#define CPUCTRL_CTRL0 ((0x0000 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL1 ((0x0001 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL2 ((0x0002 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL3 ((0x0003 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL4 ((0x0004 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL5 ((0x0005 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL6 ((0x0006 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL7 ((0x0007 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL8 ((0x0008 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL9 ((0x0009 << 2) + 0xfe007400)
+#define CPUCTRL_CTRL10 ((0x000a << 2) + 0xfe007400)
+#define CPUCTRL_CTRL11 ((0x000b << 2) + 0xfe007400)
+#define CPUCTRL_CTRL12 ((0x000c << 2) + 0xfe007400)
+#define CPUCTRL_CTRL13 ((0x000d << 2) + 0xfe007400)
+#define CPUCTRL_CTRL14 ((0x000e << 2) + 0xfe007400)
+#define CPUCTRL_CTRL15 ((0x000f << 2) + 0xfe007400)
+#define CPUCTRL_STS0 ((0x0010 << 2) + 0xfe007400)
+#define CPUCTRL_STS1 ((0x0011 << 2) + 0xfe007400)
+#define CPUCTRL_STS2 ((0x0012 << 2) + 0xfe007400)
+#define CPUCTRL_STS3 ((0x0013 << 2) + 0xfe007400)
+#define CPUCTRL_STS4 ((0x0014 << 2) + 0xfe007400)
+#define CPUCTRL_STS5 ((0x0015 << 2) + 0xfe007400)
+#define CPUCTRL_STS6 ((0x0016 << 2) + 0xfe007400)
+#define CPUCTRL_STS7 ((0x0017 << 2) + 0xfe007400)
+#define CPUCTRL_STS8 ((0x0018 << 2) + 0xfe007400)
+#define CPUCTRL_STS9 ((0x0019 << 2) + 0xfe007400)
+#define CPUCTRL_CLK_CTRL0 ((0x0020 << 2) + 0xfe007400)
+#define CPUCTRL_CLK_CTRL1 ((0x0021 << 2) + 0xfe007400)
+#define CPUCTRL_CLK_CTRL2 ((0x0022 << 2) + 0xfe007400)
+#define CPUCTRL_CLK_CTRL3 ((0x0023 << 2) + 0xfe007400)
+#define CPUCTRL_CLK_CTRL4 ((0x0024 << 2) + 0xfe007400)
+#define CPUCTRL_CLK_CTRL5 ((0x0025 << 2) + 0xfe007400)
+#define CPUCTRL_CLK_CTRL6 ((0x0026 << 2) + 0xfe007400)
+#define CPUCTRL_CLK_CTRL7 ((0x0027 << 2) + 0xfe007400)
+#define CPUCTRL_RESET_CTRL ((0x0030 << 2) + 0xfe007400)
+#define CPUCTRL_ROM_DISABLE ((0x0031 << 2) + 0xfe007400)
+//========================================================================
+// APB0_CAPU - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007800
+// -----------------------------------------------
+#define CAPU_ACCESS_EN_SLOT00_16M ((0x0000 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT00_1K ((0x0010 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT01_1K ((0x0011 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT02_1K ((0x0012 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT03_1K ((0x0013 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT04_1K ((0x0014 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT05_1K ((0x0015 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT06_1K ((0x0016 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT07_1K ((0x0017 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT08_1K ((0x0018 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT09_1K ((0x0019 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT10_1K ((0x001a << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT11_1K ((0x001b << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT12_1K ((0x001c << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT13_1K ((0x001d << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT14_1K ((0x001e << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT15_1K ((0x001f << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT16_1K ((0x0020 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT17_1K ((0x0021 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT18_1K ((0x0022 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT19_1K ((0x0023 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT20_1K ((0x0024 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT21_1K ((0x0025 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT22_1K ((0x0026 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT23_1K ((0x0027 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT24_1K ((0x0028 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT25_1K ((0x0029 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT26_1K ((0x002a << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT27_1K ((0x002b << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT28_1K ((0x002c << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT29_1K ((0x002d << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT30_1K ((0x002e << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT31_1K ((0x002f << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT32_1K ((0x0030 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT33_1K ((0x0031 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT34_1K ((0x0032 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT35_1K ((0x0033 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT36_1K ((0x0034 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT37_1K ((0x0035 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT38_1K ((0x0036 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT39_1K ((0x0037 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT40_1K ((0x0038 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT41_1K ((0x0039 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT42_1K ((0x003a << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT43_1K ((0x003b << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT44_1K ((0x003c << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT45_1K ((0x003d << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT46_1K ((0x003e << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT47_1K ((0x003f << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT48_1K ((0x0040 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT49_1K ((0x0041 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT00_4K ((0x0050 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT01_4K ((0x0051 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT02_4K ((0x0052 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT03_4K ((0x0053 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT00_8K ((0x0054 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT01_8K ((0x0055 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT02_8K ((0x0056 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT00_64K ((0x0060 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT01_64K ((0x0061 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT02_64K ((0x0062 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT03_64K ((0x0063 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT04_64K ((0x0064 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_SLOT00_8M ((0x0070 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_AHB_ISP ((0x00a0 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_AHB_ETH ((0x00a1 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_AHB_NNA ((0x00a2 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_AHB_USBDEV ((0x00a3 << 2) + 0xfe007800)
+#define CAPU_ACCESS_EN_AHB_USBHOST ((0x00a4 << 2) + 0xfe007800)
+//========================================================================
+// APB0_PWR_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe013000
+// -----------------------------------------------
+#define PWRCTRL_PWR_ACK0 ((0x0001 << 2) + 0xfe013000)
+#define PWRCTRL_PWR_ACK1 ((0x0002 << 2) + 0xfe013000)
+#define PWRCTRL_PWR_OFF0 ((0x0003 << 2) + 0xfe013000)
+#define PWRCTRL_PWR_OFF1 ((0x0004 << 2) + 0xfe013000)
+#define PWRCTRL_ISO_EN0 ((0x0005 << 2) + 0xfe013000)
+#define PWRCTRL_ISO_EN1 ((0x0006 << 2) + 0xfe013000)
+#define PWRCTRL_MEM_PD0 ((0x0007 << 2) + 0xfe013000)
+#define PWRCTRL_MEM_PD1 ((0x0008 << 2) + 0xfe013000)
+#define PWRCTRL_MEM_PD2 ((0x0009 << 2) + 0xfe013000)
+#define PWRCTRL_MEM_PD3 ((0x000a << 2) + 0xfe013000)
+#define PWRCTRL_MEM_PD4 ((0x000b << 2) + 0xfe013000)
+#define PWRCTRL_MEM_PD5 ((0x000c << 2) + 0xfe013000)
+#define PWRCTRL_MEM_PD6 ((0x000d << 2) + 0xfe013000)
+#define PWRCTRL_MEM_PD7 ((0x000e << 2) + 0xfe013000)
+#define PWRCTRL_MEM_PD8 ((0x000f << 2) + 0xfe013000)
+#define PWRCTRL_MEM_PD9 ((0x0010 << 2) + 0xfe013000)
+#define PWRCTRL_MEM_PD10 ((0x0011 << 2) + 0xfe013000)
+#define PWRCTRL_MEM_PD11 ((0x0012 << 2) + 0xfe013000)
+#define PWRCTRL_MEM_PD12 ((0x0013 << 2) + 0xfe013000)
+#define PWRCTRL_MEM_PD13 ((0x0014 << 2) + 0xfe013000)
+#define PWRCTRL_MEM_PD14 ((0x0015 << 2) + 0xfe013000)
+#define PWRCTRL_MEM_PD15 ((0x0016 << 2) + 0xfe013000)
+#define PWRCTRL_FOCRST0 ((0x0020 << 2) + 0xfe013000)
+#define PWRCTRL_FOCRST1 ((0x0021 << 2) + 0xfe013000)
+#define PWRCTRL_DDRPHY_PWROFF_CTRL ((0x0030 << 2) + 0xfe013000)
+#define PWRCTRL_NNA_AXI_PWR_CNTL ((0x0031 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL0 ((0x0040 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL1 ((0x0041 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL2 ((0x0042 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL3 ((0x0043 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL4 ((0x0044 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_TIMER_TH_01 ((0x0048 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_TIMER_TH_23 ((0x0049 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_TIMER_TH_45 ((0x004a << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_TIMER_TH_67 ((0x004b << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_TIMER_TH_89 ((0x004c << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_IRQ_MASK0 ((0x0050 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_IRQ_MASK1 ((0x0051 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_IRQ_MASK2 ((0x0052 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_IRQ_MASK3 ((0x0053 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_IRQ_MASK4 ((0x0054 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_IRQ_MASK5 ((0x0055 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_IRQ_MASK6 ((0x0056 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_IRQ_MASK7 ((0x0057 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_MEMPD_INIT_SET ((0x0060 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_MEMPD_OFF_SET ((0x0061 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_MEMPD_ON_A_SET ((0x0062 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_MEMPD_ON_B_SET ((0x0063 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_MEMPD_ON_C_SET ((0x0064 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_MEMPD_ON_D_SET ((0x0065 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_MEMPD_STS ((0x0066 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_FSM_STS0 ((0x0067 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_FSM_STS1 ((0x0068 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_FSM_STS2 ((0x0069 << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_FSM_START ((0x006e << 2) + 0xfe013000)
+#define PWRCTRL_CPU0_FSM_JUMP ((0x006f << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL0 ((0x0070 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL1 ((0x0071 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL2 ((0x0072 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL3 ((0x0073 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL4 ((0x0074 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_TIMER_TH_01 ((0x0078 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_TIMER_TH_23 ((0x0079 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_TIMER_TH_45 ((0x007a << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_TIMER_TH_67 ((0x007b << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_TIMER_TH_89 ((0x007c << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_IRQ_MASK0 ((0x0080 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_IRQ_MASK1 ((0x0081 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_IRQ_MASK2 ((0x0082 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_IRQ_MASK3 ((0x0083 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_IRQ_MASK4 ((0x0084 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_IRQ_MASK5 ((0x0085 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_IRQ_MASK6 ((0x0086 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_IRQ_MASK7 ((0x0087 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_MEMPD_INIT_SET ((0x0090 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_MEMPD_OFF_SET ((0x0091 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_MEMPD_ON_A_SET ((0x0092 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_MEMPD_ON_B_SET ((0x0093 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_MEMPD_ON_C_SET ((0x0094 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_MEMPD_ON_D_SET ((0x0095 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_MEMPD_STS ((0x0096 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_FSM_STS0 ((0x0097 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_FSM_STS1 ((0x0098 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_FSM_STS2 ((0x0099 << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_FSM_START ((0x009e << 2) + 0xfe013000)
+#define PWRCTRL_CPU1_FSM_JUMP ((0x009f << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL0 ((0x00a0 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL1 ((0x00a1 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL2 ((0x00a2 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL3 ((0x00a3 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL4 ((0x00a4 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_TIMER_TH_01 ((0x00a8 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_TIMER_TH_23 ((0x00a9 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_TIMER_TH_45 ((0x00aa << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_TIMER_TH_67 ((0x00ab << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_TIMER_TH_89 ((0x00ac << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_IRQ_MASK0 ((0x00b0 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_IRQ_MASK1 ((0x00b1 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_IRQ_MASK2 ((0x00b2 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_IRQ_MASK3 ((0x00b3 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_IRQ_MASK4 ((0x00b4 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_IRQ_MASK5 ((0x00b5 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_IRQ_MASK6 ((0x00b6 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_IRQ_MASK7 ((0x00b7 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_MEMPD_INIT_SET ((0x00c0 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_MEMPD_OFF_SET ((0x00c1 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_MEMPD_ON_A_SET ((0x00c2 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_MEMPD_ON_B_SET ((0x00c3 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_MEMPD_ON_C_SET ((0x00c4 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_MEMPD_ON_D_SET ((0x00c5 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_MEMPD_STS ((0x00c6 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_FSM_STS0 ((0x00c7 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_FSM_STS1 ((0x00c8 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_FSM_STS2 ((0x00c9 << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_FSM_START ((0x00ce << 2) + 0xfe013000)
+#define PWRCTRL_CPU2_FSM_JUMP ((0x00cf << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL0 ((0x00d0 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL1 ((0x00d1 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL2 ((0x00d2 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL3 ((0x00d3 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL4 ((0x00d4 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_TIMER_TH_01 ((0x00d8 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_TIMER_TH_23 ((0x00d9 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_TIMER_TH_45 ((0x00da << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_TIMER_TH_67 ((0x00db << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_TIMER_TH_89 ((0x00dc << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_IRQ_MASK0 ((0x00e0 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_IRQ_MASK1 ((0x00e1 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_IRQ_MASK2 ((0x00e2 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_IRQ_MASK3 ((0x00e3 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_IRQ_MASK4 ((0x00e4 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_IRQ_MASK5 ((0x00e5 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_IRQ_MASK6 ((0x00e6 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_IRQ_MASK7 ((0x00e7 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_MEMPD_INIT_SET ((0x00f0 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_MEMPD_OFF_SET ((0x00f1 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_MEMPD_ON_A_SET ((0x00f2 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_MEMPD_ON_B_SET ((0x00f3 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_MEMPD_ON_C_SET ((0x00f4 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_MEMPD_ON_D_SET ((0x00f5 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_MEMPD_STS ((0x00f6 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_FSM_STS0 ((0x00f7 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_FSM_STS1 ((0x00f8 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_FSM_STS2 ((0x00f9 << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_FSM_START ((0x00fe << 2) + 0xfe013000)
+#define PWRCTRL_CPU3_FSM_JUMP ((0x00ff << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL0 ((0x0100 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL1 ((0x0101 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL2 ((0x0102 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL3 ((0x0103 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL4 ((0x0104 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_TIMER_TH_01 ((0x0108 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_TIMER_TH_23 ((0x0109 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_TIMER_TH_45 ((0x010a << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_TIMER_TH_67 ((0x010b << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_TIMER_TH_89 ((0x010c << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_IRQ_MASK0 ((0x0110 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_IRQ_MASK1 ((0x0111 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_IRQ_MASK2 ((0x0112 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_IRQ_MASK3 ((0x0113 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_IRQ_MASK4 ((0x0114 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_IRQ_MASK5 ((0x0115 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_IRQ_MASK6 ((0x0116 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_IRQ_MASK7 ((0x0117 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_MEMPD_INIT_SET ((0x0120 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_MEMPD_OFF_SET ((0x0121 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_MEMPD_ON_A_SET ((0x0122 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_MEMPD_ON_B_SET ((0x0123 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_MEMPD_ON_C_SET ((0x0124 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_MEMPD_ON_D_SET ((0x0125 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_MEMPD_STS ((0x0126 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_FSM_STS0 ((0x0127 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_FSM_STS1 ((0x0128 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_FSM_STS2 ((0x0129 << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_FSM_START ((0x012e << 2) + 0xfe013000)
+#define PWRCTRL_CPUTOP_FSM_JUMP ((0x012f << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL0 ((0x0130 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL1 ((0x0131 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL2 ((0x0132 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL3 ((0x0133 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL4 ((0x0134 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_TIMER_TH_01 ((0x0138 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_TIMER_TH_23 ((0x0139 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_TIMER_TH_45 ((0x013a << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_TIMER_TH_67 ((0x013b << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_TIMER_TH_89 ((0x013c << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_IRQ_MASK0 ((0x0140 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_IRQ_MASK1 ((0x0141 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_IRQ_MASK2 ((0x0142 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_IRQ_MASK3 ((0x0143 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_IRQ_MASK4 ((0x0144 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_IRQ_MASK5 ((0x0145 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_IRQ_MASK6 ((0x0146 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_IRQ_MASK7 ((0x0147 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_MEMPD_INIT_SET ((0x0150 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_MEMPD_OFF_SET ((0x0151 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_MEMPD_ON_A_SET ((0x0152 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_MEMPD_ON_B_SET ((0x0153 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_MEMPD_ON_C_SET ((0x0154 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_MEMPD_ON_D_SET ((0x0155 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_MEMPD_STS ((0x0156 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_FSM_STS0 ((0x0157 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_FSM_STS1 ((0x0158 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_FSM_STS2 ((0x0159 << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_FSM_START ((0x015e << 2) + 0xfe013000)
+#define PWRCTRL_DSPA_FSM_JUMP ((0x015f << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL0 ((0x0160 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL1 ((0x0161 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL2 ((0x0162 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL3 ((0x0163 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL4 ((0x0164 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_TIMER_TH_01 ((0x0168 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_TIMER_TH_23 ((0x0169 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_TIMER_TH_45 ((0x016a << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_TIMER_TH_67 ((0x016b << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_TIMER_TH_89 ((0x016c << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_IRQ_MASK0 ((0x0170 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_IRQ_MASK1 ((0x0171 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_IRQ_MASK2 ((0x0172 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_IRQ_MASK3 ((0x0173 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_IRQ_MASK4 ((0x0174 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_IRQ_MASK5 ((0x0175 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_IRQ_MASK6 ((0x0176 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_IRQ_MASK7 ((0x0177 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_MEMPD_INIT_SET ((0x0180 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_MEMPD_OFF_SET ((0x0181 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_MEMPD_ON_A_SET ((0x0182 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_MEMPD_ON_B_SET ((0x0183 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_MEMPD_ON_C_SET ((0x0184 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_MEMPD_ON_D_SET ((0x0185 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_MEMPD_STS ((0x0186 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_FSM_STS0 ((0x0187 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_FSM_STS1 ((0x0188 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_FSM_STS2 ((0x0189 << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_FSM_START ((0x018e << 2) + 0xfe013000)
+#define PWRCTRL_DSPB_FSM_JUMP ((0x018f << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_AUTO_OFF_CTRL0 ((0x0190 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_AUTO_OFF_CTRL1 ((0x0191 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_AUTO_OFF_CTRL2 ((0x0192 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_AUTO_OFF_CTRL3 ((0x0193 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_AUTO_OFF_CTRL4 ((0x0194 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_TIMER_TH_01 ((0x0198 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_TIMER_TH_23 ((0x0199 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_TIMER_TH_45 ((0x019a << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_TIMER_TH_67 ((0x019b << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_TIMER_TH_89 ((0x019c << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_IRQ_MASK0 ((0x01a0 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_IRQ_MASK1 ((0x01a1 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_IRQ_MASK2 ((0x01a2 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_IRQ_MASK3 ((0x01a3 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_IRQ_MASK4 ((0x01a4 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_IRQ_MASK5 ((0x01a5 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_IRQ_MASK6 ((0x01a6 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_IRQ_MASK7 ((0x01a7 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_MEMPD_INIT_SET ((0x01b0 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_MEMPD_OFF_SET ((0x01b1 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_MEMPD_ON_A_SET ((0x01b2 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_MEMPD_ON_B_SET ((0x01b3 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_MEMPD_ON_C_SET ((0x01b4 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_MEMPD_ON_D_SET ((0x01b5 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_MEMPD_STS ((0x01b6 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_FSM_STS0 ((0x01b7 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_FSM_STS1 ((0x01b8 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_FSM_STS2 ((0x01b9 << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_FSM_START ((0x01be << 2) + 0xfe013000)
+#define PWRCTRL_SPTOP_FSM_JUMP ((0x01bf << 2) + 0xfe013000)
+//========================================================================
+// APB0_ANA_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe007c00
+// -----------------------------------------------
+#define ANACTRL_PLL_GATE_DIS ((0x0010 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_CTRL0 ((0x0020 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_CTRL1 ((0x0021 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_CTRL2 ((0x0022 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_CTRL3 ((0x0023 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_CTRL4 ((0x0024 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_CTRL5 ((0x0025 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_CTRL6 ((0x0026 << 2) + 0xfe007c00)
+#define ANACTRL_FIXPLL_STS ((0x0027 << 2) + 0xfe007c00)
+#define ANACTRL_GPPLL_CTRL0 ((0x0030 << 2) + 0xfe007c00)
+#define ANACTRL_GPPLL_CTRL1 ((0x0031 << 2) + 0xfe007c00)
+#define ANACTRL_GPPLL_CTRL2 ((0x0032 << 2) + 0xfe007c00)
+#define ANACTRL_GPPLL_CTRL3 ((0x0033 << 2) + 0xfe007c00)
+#define ANACTRL_GPPLL_CTRL4 ((0x0034 << 2) + 0xfe007c00)
+#define ANACTRL_GPPLL_CTRL5 ((0x0035 << 2) + 0xfe007c00)
+#define ANACTRL_GPPLL_STS ((0x0036 << 2) + 0xfe007c00)
+#define ANACTRL_GPPLL_CTRL6 ((0x0037 << 2) + 0xfe007c00)
+#define ANACTRL_SYSPLL_CTRL0 ((0x0040 << 2) + 0xfe007c00)
+#define ANACTRL_SYSPLL_CTRL1 ((0x0041 << 2) + 0xfe007c00)
+#define ANACTRL_SYSPLL_CTRL2 ((0x0042 << 2) + 0xfe007c00)
+#define ANACTRL_SYSPLL_CTRL3 ((0x0043 << 2) + 0xfe007c00)
+#define ANACTRL_SYSPLL_CTRL4 ((0x0044 << 2) + 0xfe007c00)
+#define ANACTRL_SYSPLL_STS ((0x0045 << 2) + 0xfe007c00)
+#define ANACTRL_HIFIPLL_CTRL0 ((0x0050 << 2) + 0xfe007c00)
+#define ANACTRL_HIFIPLL_CTRL1 ((0x0051 << 2) + 0xfe007c00)
+#define ANACTRL_HIFIPLL_CTRL2 ((0x0052 << 2) + 0xfe007c00)
+#define ANACTRL_HIFIPLL_CTRL3 ((0x0053 << 2) + 0xfe007c00)
+#define ANACTRL_HIFIPLL_CTRL4 ((0x0054 << 2) + 0xfe007c00)
+#define ANACTRL_HIFIPLL_STS ((0x0055 << 2) + 0xfe007c00)
+//`define ANACTRL_AUDDDS_CTRL0 8'h60
+//`define ANACTRL_AUDDDS_CTRL1 8'h61
+//`define ANACTRL_AUDDDS_CTRL2 8'h62
+//`define ANACTRL_AUDDDS_CTRL3 8'h63
+//`define ANACTRL_AUDDDS_CTRL4 8'h64
+//`define ANACTRL_AUDDDS_STS 8'h65
+#define ANACTRL_MISCTOP_CTRL0 ((0x0070 << 2) + 0xfe007c00)
+#define ANACTRL_POR_CNTL ((0x0082 << 2) + 0xfe007c00)
+#define ANACTRL_CSI_PHY_CNTL0 ((0x0090 << 2) + 0xfe007c00)
+#define ANACTRL_CSI_PHY_CNTL1 ((0x0091 << 2) + 0xfe007c00)
+#define ANACTRL_CSI_PHY_CNTL2 ((0x0092 << 2) + 0xfe007c00)
+#define ANACTRL_CSI_PHY_CNTL3 ((0x0093 << 2) + 0xfe007c00)
+#define ANACTRL_CSI_PHY_STS ((0x0094 << 2) + 0xfe007c00)
+#define ANACTRL_ISP_MAX_ADDR_CNTL ((0x0095 << 2) + 0xfe007c00)
+//========================================================================
+// APB0_ETHTOP - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe009000
+// -----------------------------------------------
+#define ETHTOP_CNTL0 ((0x0000 << 2) + 0xfe009000)
+#define ETHTOP_CNTL1 ((0x0001 << 2) + 0xfe009000)
+//========================================================================
+// APB0_ETHPHY - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe009400
+// -----------------------------------------------
+#define ETH_PHY_DBG_CTL0 ((0x0000 << 2) + 0xfe009400)
+#define ETH_PHY_DBG_CTL1 ((0x0001 << 2) + 0xfe009400)
+#define ETH_PHY_DBG_CFG0 ((0x0002 << 2) + 0xfe009400)
+#define ETH_PHY_DBG_CFG1 ((0x0003 << 2) + 0xfe009400)
+#define ETH_PHY_DBG_CFG2 ((0x0004 << 2) + 0xfe009400)
+#define ETH_PHY_DBG_CFG3 ((0x0005 << 2) + 0xfe009400)
+#define ETH_PHY_DBG_CFG4 ((0x0006 << 2) + 0xfe009400)
+#define ETH_PLL_STS ((0x0010 << 2) + 0xfe009400)
+#define ETH_PLL_CTL0 ((0x0011 << 2) + 0xfe009400)
+#define ETH_PLL_CTL1 ((0x0012 << 2) + 0xfe009400)
+#define ETH_PLL_CTL2 ((0x0013 << 2) + 0xfe009400)
+#define ETH_PLL_CTL3 ((0x0014 << 2) + 0xfe009400)
+#define ETH_PLL_CTL4 ((0x0015 << 2) + 0xfe009400)
+#define ETH_PLL_CTL5 ((0x0016 << 2) + 0xfe009400)
+#define ETH_PLL_CTL6 ((0x0017 << 2) + 0xfe009400)
+#define ETH_PLL_CTL7 ((0x0018 << 2) + 0xfe009400)
+#define ETH_PHY_CNTL0 ((0x0020 << 2) + 0xfe009400)
+#define ETH_PHY_CNTL1 ((0x0021 << 2) + 0xfe009400)
+#define ETH_PHY_CNTL2 ((0x0022 << 2) + 0xfe009400)
+#define ETH_PHY_CNTL3 ((0x0023 << 2) + 0xfe009400)
+#define ETH_PHY_STS0 ((0x0025 << 2) + 0xfe009400)
+#define ETH_PHY_STS1 ((0x0026 << 2) + 0xfe009400)
+#define ETH_PHY_STS2 ((0x0027 << 2) + 0xfe009400)
+#define ETH_PHY_DBG_REG ((0x0028 << 2) + 0xfe009400)
+//========================================================================
+// APB0_UART_D - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe009c00
+// -----------------------------------------------
+#define UART_D_WFIFO ((0x0000 << 2) + 0xfe009c00)
+#define UART_D_RFIFO ((0x0001 << 2) + 0xfe009c00)
+#define UART_D_CONTROL ((0x0002 << 2) + 0xfe009c00)
+#define UART_D_STATUS ((0x0003 << 2) + 0xfe009c00)
+#define UART_D_MISC ((0x0004 << 2) + 0xfe009c00)
+#define UART_D_REG5 ((0x0005 << 2) + 0xfe009c00)
+//========================================================================
+// APB0_UART_E - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe00a000
+// -----------------------------------------------
+#define UART_E_WFIFO ((0x0000 << 2) + 0xfe00a000)
+#define UART_E_RFIFO ((0x0001 << 2) + 0xfe00a000)
+#define UART_E_CONTROL ((0x0002 << 2) + 0xfe00a000)
+#define UART_E_STATUS ((0x0003 << 2) + 0xfe00a000)
+#define UART_E_MISC ((0x0004 << 2) + 0xfe00a000)
+#define UART_E_REG5 ((0x0005 << 2) + 0xfe00a000)
+//========================================================================
+// APB0_PWM_GH - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe00a400
+// -----------------------------------------------
+#define PWMGH_PWM_G ((0x0000 << 2) + 0xfe00a400)
+#define PWMGH_PWM_H ((0x0001 << 2) + 0xfe00a400)
+#define PWMGH_MISC_REG_GH ((0x0002 << 2) + 0xfe00a400)
+#define PWMGH_DELTA_SIGMA_GH ((0x0003 << 2) + 0xfe00a400)
+#define PWMGH_TIME_GH ((0x0004 << 2) + 0xfe00a400)
+#define PWMGH_G2 ((0x0005 << 2) + 0xfe00a400)
+#define PWMGH_H2 ((0x0006 << 2) + 0xfe00a400)
+#define PWMGH_BLINK_GH ((0x0007 << 2) + 0xfe00a400)
+#define PWMGH_LOCK_GH ((0x0008 << 2) + 0xfe00a400)
+//========================================================================
+// APB0_PWM_IJ - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe00a800
+// -----------------------------------------------
+#define PWMIJ_PWM_I ((0x0000 << 2) + 0xfe00a800)
+#define PWMIJ_PWM_J ((0x0001 << 2) + 0xfe00a800)
+#define PWMIJ_MISC_REG_IJ ((0x0002 << 2) + 0xfe00a800)
+#define PWMIJ_DELTA_SIGMA_IJ ((0x0003 << 2) + 0xfe00a800)
+#define PWMIJ_TIME_IJ ((0x0004 << 2) + 0xfe00a800)
+#define PWMIJ_I2 ((0x0005 << 2) + 0xfe00a800)
+#define PWMIJ_J2 ((0x0006 << 2) + 0xfe00a800)
+#define PWMIJ_BLINK_IJ ((0x0007 << 2) + 0xfe00a800)
+#define PWMIJ_LOCK_IJ ((0x0008 << 2) + 0xfe00a800)
+//========================================================================
+// APB0_I2C_M - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe00b000
+// -----------------------------------------------
+#define I2C_M_E_CONTROL_REG ((0x0000 << 2) + 0xfe00b000)
+#define I2C_M_E_SLAVE_ADDR ((0x0001 << 2) + 0xfe00b000)
+#define I2C_M_E_TOKEN_LIST0 ((0x0002 << 2) + 0xfe00b000)
+#define I2C_M_E_TOKEN_LIST1 ((0x0003 << 2) + 0xfe00b000)
+#define I2C_M_E_WDATA_REG0 ((0x0004 << 2) + 0xfe00b000)
+#define I2C_M_E_WDATA_REG1 ((0x0005 << 2) + 0xfe00b000)
+#define I2C_M_E_RDATA_REG0 ((0x0006 << 2) + 0xfe00b000)
+#define I2C_M_E_RDATA_REG1 ((0x0007 << 2) + 0xfe00b000)
+#define I2C_M_E_TIMEOUT_TH ((0x0008 << 2) + 0xfe00b000)
+#define I2C_M_E_CNTL_DELY1 ((0x0009 << 2) + 0xfe00b000)
+#define I2C_M_E_CNTL_DELY2 ((0x000a << 2) + 0xfe00b000)
+#define I2C_M_E_LOW_DELY ((0x000b << 2) + 0xfe00b000)
+#define I2C_M_E_HIGH_DELY ((0x000c << 2) + 0xfe00b000)
+#define I2C_M_E_FIFO_CTRL0 ((0x000d << 2) + 0xfe00b000)
+#define I2C_M_E_FIFO_CTRL1 ((0x000e << 2) + 0xfe00b000)
+#define I2C_M_E_FIFO_PENDING ((0x000f << 2) + 0xfe00b000)
+#define I2C_M_E_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe00b000)
+#define I2C_M_E_FIFO_ST0 ((0x0011 << 2) + 0xfe00b000)
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe020000
+// -----------------------------------------------
+#define RSA_BASE ((0x0000 << 2) + 0xfe020000)
+//========================================================================
+// MAILBOX_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe00c400
+// -----------------------------------------------
+#define MAILBOX_SET_0 ((0x0000 << 2) + 0xfe00c400)
+#define MAILBOX_CLR_0 ((0x0001 << 2) + 0xfe00c400)
+#define MAILBOX_STAT_0 ((0x0002 << 2) + 0xfe00c400)
+#define MAILBOX_SET_1 ((0x0004 << 2) + 0xfe00c400)
+#define MAILBOX_CLR_1 ((0x0005 << 2) + 0xfe00c400)
+#define MAILBOX_STAT_1 ((0x0006 << 2) + 0xfe00c400)
+#define MAILBOX_SET_2 ((0x0008 << 2) + 0xfe00c400)
+#define MAILBOX_CLR_2 ((0x0009 << 2) + 0xfe00c400)
+#define MAILBOX_STAT_2 ((0x000a << 2) + 0xfe00c400)
+#define MAILBOX_SET_3 ((0x000c << 2) + 0xfe00c400)
+#define MAILBOX_CLR_3 ((0x000d << 2) + 0xfe00c400)
+#define MAILBOX_STAT_3 ((0x000e << 2) + 0xfe00c400)
+//========================================================================
+// RAMA_SEC_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe00b400
+// -----------------------------------------------
+#define SRAM_RANGE0_STA ((0x0000 << 2) + 0xfe00b400)
+#define SRAM_RANGE1_STA ((0x0001 << 2) + 0xfe00b400)
+#define SRAM_RANGE2_STA ((0x0002 << 2) + 0xfe00b400)
+#define SRAM_RANGE3_STA ((0x0003 << 2) + 0xfe00b400)
+#define SRAM_RANGE4_STA ((0x0004 << 2) + 0xfe00b400)
+#define SRAM_RANGE5_STA ((0x0005 << 2) + 0xfe00b400)
+#define SRAM_RANGE6_STA ((0x0006 << 2) + 0xfe00b400)
+#define SRAM_RANGE7_STA ((0x0007 << 2) + 0xfe00b400)
+#define SRAM_RANGE8_STA ((0x0008 << 2) + 0xfe00b400)
+#define SRAM_RANGE9_STA ((0x0009 << 2) + 0xfe00b400)
+#define SRAM_RANGE10_STA ((0x000a << 2) + 0xfe00b400)
+#define SRAM_RANGE11_STA ((0x000b << 2) + 0xfe00b400)
+#define SRAM_RANGE12_STA ((0x000c << 2) + 0xfe00b400)
+#define SRAM_RANGE13_STA ((0x000d << 2) + 0xfe00b400)
+#define SRAM_RANGE14_STA ((0x000e << 2) + 0xfe00b400)
+#define SRAM_RANGE0_EDA ((0x000f << 2) + 0xfe00b400)
+#define SRAM_RANGE1_EDA ((0x0010 << 2) + 0xfe00b400)
+#define SRAM_RANGE2_EDA ((0x0011 << 2) + 0xfe00b400)
+#define SRAM_RANGE3_EDA ((0x0012 << 2) + 0xfe00b400)
+#define SRAM_RANGE4_EDA ((0x0013 << 2) + 0xfe00b400)
+#define SRAM_RANGE5_EDA ((0x0014 << 2) + 0xfe00b400)
+#define SRAM_RANGE6_EDA ((0x0015 << 2) + 0xfe00b400)
+#define SRAM_RANGE7_EDA ((0x0016 << 2) + 0xfe00b400)
+#define SRAM_RANGE8_EDA ((0x0017 << 2) + 0xfe00b400)
+#define SRAM_RANGE9_EDA ((0x0018 << 2) + 0xfe00b400)
+#define SRAM_RANGE10_EDA ((0x0019 << 2) + 0xfe00b400)
+#define SRAM_RANGE11_EDA ((0x001a << 2) + 0xfe00b400)
+#define SRAM_RANGE12_EDA ((0x001b << 2) + 0xfe00b400)
+#define SRAM_RANGE13_EDA ((0x001c << 2) + 0xfe00b400)
+#define SRAM_RANGE14_EDA ((0x001d << 2) + 0xfe00b400)
+#define SRAM_RANGE0_READ_CTRL0 ((0x001e << 2) + 0xfe00b400)
+#define SRAM_RANGE1_READ_CTRL0 ((0x001f << 2) + 0xfe00b400)
+#define SRAM_RANGE2_READ_CTRL0 ((0x0020 << 2) + 0xfe00b400)
+#define SRAM_RANGE3_READ_CTRL0 ((0x0021 << 2) + 0xfe00b400)
+#define SRAM_RANGE4_READ_CTRL0 ((0x0022 << 2) + 0xfe00b400)
+#define SRAM_RANGE5_READ_CTRL0 ((0x0023 << 2) + 0xfe00b400)
+#define SRAM_RANGE6_READ_CTRL0 ((0x0024 << 2) + 0xfe00b400)
+#define SRAM_RANGE7_READ_CTRL0 ((0x0025 << 2) + 0xfe00b400)
+#define SRAM_RANGE8_READ_CTRL0 ((0x0026 << 2) + 0xfe00b400)
+#define SRAM_RANGE9_READ_CTRL0 ((0x0027 << 2) + 0xfe00b400)
+#define SRAM_RANGE10_READ_CTRL0 ((0x0028 << 2) + 0xfe00b400)
+#define SRAM_RANGE11_READ_CTRL0 ((0x0029 << 2) + 0xfe00b400)
+#define SRAM_RANGE12_READ_CTRL0 ((0x002a << 2) + 0xfe00b400)
+#define SRAM_RANGE13_READ_CTRL0 ((0x002b << 2) + 0xfe00b400)
+#define SRAM_RANGE14_READ_CTRL0 ((0x002c << 2) + 0xfe00b400)
+#define SRAM_RANGE15_READ_CTRL0 ((0x002d << 2) + 0xfe00b400)
+#define SRAM_RANGE0_WRITE_CTRL0 ((0x002e << 2) + 0xfe00b400)
+#define SRAM_RANGE1_WRITE_CTRL0 ((0x002f << 2) + 0xfe00b400)
+#define SRAM_RANGE2_WRITE_CTRL0 ((0x0030 << 2) + 0xfe00b400)
+#define SRAM_RANGE3_WRITE_CTRL0 ((0x0031 << 2) + 0xfe00b400)
+#define SRAM_RANGE4_WRITE_CTRL0 ((0x0032 << 2) + 0xfe00b400)
+#define SRAM_RANGE5_WRITE_CTRL0 ((0x0033 << 2) + 0xfe00b400)
+#define SRAM_RANGE6_WRITE_CTRL0 ((0x0034 << 2) + 0xfe00b400)
+#define SRAM_RANGE7_WRITE_CTRL0 ((0x0035 << 2) + 0xfe00b400)
+#define SRAM_RANGE8_WRITE_CTRL0 ((0x0036 << 2) + 0xfe00b400)
+#define SRAM_RANGE9_WRITE_CTRL0 ((0x0037 << 2) + 0xfe00b400)
+#define SRAM_RANGE10_WRITE_CTRL0 ((0x0038 << 2) + 0xfe00b400)
+#define SRAM_RANGE11_WRITE_CTRL0 ((0x0039 << 2) + 0xfe00b400)
+#define SRAM_RANGE12_WRITE_CTRL0 ((0x003a << 2) + 0xfe00b400)
+#define SRAM_RANGE13_WRITE_CTRL0 ((0x003b << 2) + 0xfe00b400)
+#define SRAM_RANGE14_WRITE_CTRL0 ((0x003c << 2) + 0xfe00b400)
+#define SRAM_RANGE15_WRITE_CTRL0 ((0x003d << 2) + 0xfe00b400)
+#define SRAM_RANGE0_READ_CTRL1 ((0x003e << 2) + 0xfe00b400)
+#define SRAM_RANGE1_READ_CTRL1 ((0x003f << 2) + 0xfe00b400)
+#define SRAM_RANGE2_READ_CTRL1 ((0x0040 << 2) + 0xfe00b400)
+#define SRAM_RANGE3_READ_CTRL1 ((0x0041 << 2) + 0xfe00b400)
+#define SRAM_RANGE4_READ_CTRL1 ((0x0042 << 2) + 0xfe00b400)
+#define SRAM_RANGE5_READ_CTRL1 ((0x0043 << 2) + 0xfe00b400)
+#define SRAM_RANGE6_READ_CTRL1 ((0x0044 << 2) + 0xfe00b400)
+#define SRAM_RANGE7_READ_CTRL1 ((0x0045 << 2) + 0xfe00b400)
+#define SRAM_RANGE8_READ_CTRL1 ((0x0046 << 2) + 0xfe00b400)
+#define SRAM_RANGE9_READ_CTRL1 ((0x0047 << 2) + 0xfe00b400)
+#define SRAM_RANGE10_READ_CTRL1 ((0x0048 << 2) + 0xfe00b400)
+#define SRAM_RANGE11_READ_CTRL1 ((0x0049 << 2) + 0xfe00b400)
+#define SRAM_RANGE12_READ_CTRL1 ((0x004a << 2) + 0xfe00b400)
+#define SRAM_RANGE13_READ_CTRL1 ((0x004b << 2) + 0xfe00b400)
+#define SRAM_RANGE14_READ_CTRL1 ((0x004c << 2) + 0xfe00b400)
+#define SRAM_RANGE15_READ_CTRL1 ((0x004d << 2) + 0xfe00b400)
+#define SRAM_RANGE0_WRITE_CTRL1 ((0x004e << 2) + 0xfe00b400)
+#define SRAM_RANGE1_WRITE_CTRL1 ((0x004f << 2) + 0xfe00b400)
+#define SRAM_RANGE2_WRITE_CTRL1 ((0x0050 << 2) + 0xfe00b400)
+#define SRAM_RANGE3_WRITE_CTRL1 ((0x0051 << 2) + 0xfe00b400)
+#define SRAM_RANGE4_WRITE_CTRL1 ((0x0052 << 2) + 0xfe00b400)
+#define SRAM_RANGE5_WRITE_CTRL1 ((0x0053 << 2) + 0xfe00b400)
+#define SRAM_RANGE6_WRITE_CTRL1 ((0x0054 << 2) + 0xfe00b400)
+#define SRAM_RANGE7_WRITE_CTRL1 ((0x0055 << 2) + 0xfe00b400)
+#define SRAM_RANGE8_WRITE_CTRL1 ((0x0056 << 2) + 0xfe00b400)
+#define SRAM_RANGE9_WRITE_CTRL1 ((0x0057 << 2) + 0xfe00b400)
+#define SRAM_RANGE10_WRITE_CTRL1 ((0x0058 << 2) + 0xfe00b400)
+#define SRAM_RANGE11_WRITE_CTRL1 ((0x0059 << 2) + 0xfe00b400)
+#define SRAM_RANGE12_WRITE_CTRL1 ((0x005a << 2) + 0xfe00b400)
+#define SRAM_RANGE13_WRITE_CTRL1 ((0x005b << 2) + 0xfe00b400)
+#define SRAM_RANGE14_WRITE_CTRL1 ((0x005c << 2) + 0xfe00b400)
+#define SRAM_RANGE15_WRITE_CTRL1 ((0x005d << 2) + 0xfe00b400)
+#define SRAM_SEC_CTRL0 ((0x005e << 2) + 0xfe00b400)
+#define SRAM_REG_LOCK0 ((0x005f << 2) + 0xfe00b400)
+#define SRAM_REG_LOCK1 ((0x0060 << 2) + 0xfe00b400)
+#define SRAM_REG_LOCK2 ((0x0061 << 2) + 0xfe00b400)
+//
+// Reading file: REG_LIST_DSP_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//========================================================================
+// DSPA - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe030000
+// -----------------------------------------------
+#define DSP_CFG0 ((0x0000 << 2) + 0xfe030000)
+#define DSP_CFG1 ((0x0001 << 2) + 0xfe030000)
+#define DSP_CFG2 ((0x0002 << 2) + 0xfe030000)
+#define DSP_IMPWIRE ((0x0003 << 2) + 0xfe030000)
+#define DSP_RESET_VEC ((0x0004 << 2) + 0xfe030000)
+#define DSP_SEC_CFG0 ((0x0006 << 2) + 0xfe030000)
+#define DSP_SEC_CFG1 ((0x0007 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL0 ((0x0010 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL1 ((0x0011 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL2 ((0x0012 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL3 ((0x0013 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL4 ((0x0014 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL5 ((0x0015 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL6 ((0x0016 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL7 ((0x0017 << 2) + 0xfe030000)
+#define DSP_IRQ_CTRL8 ((0x0018 << 2) + 0xfe030000)
+#define DSP_IRQ_STS ((0x001f << 2) + 0xfe030000)
+#define DSP_REMAP0 ((0x0020 << 2) + 0xfe030000)
+#define DSP_REMAP1 ((0x0021 << 2) + 0xfe030000)
+#define DSP_REMAP2 ((0x0022 << 2) + 0xfe030000)
+#define DSP_STS0 ((0x0040 << 2) + 0xfe030000)
+#define DSP_STS1 ((0x0041 << 2) + 0xfe030000)
+#define DSP_STS2 ((0x0042 << 2) + 0xfe030000)
+#define DSP_STS3 ((0x0043 << 2) + 0xfe030000)
+#define DSP_STS4 ((0x0044 << 2) + 0xfe030000)
+#define DSP_STS5 ((0x0045 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_0 ((0x0050 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_1 ((0x0051 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_2 ((0x0052 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_3 ((0x0053 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_4 ((0x0054 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_5 ((0x0055 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_6 ((0x0056 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_7 ((0x0057 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_8 ((0x0058 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_9 ((0x0059 << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_10 ((0x005a << 2) + 0xfe030000)
+#define DSP_MAILBOX_SET_11 ((0x005b << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_0 ((0x0060 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_1 ((0x0061 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_2 ((0x0062 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_3 ((0x0063 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_4 ((0x0064 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_5 ((0x0065 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_6 ((0x0066 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_7 ((0x0067 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_8 ((0x0068 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_9 ((0x0069 << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_10 ((0x006a << 2) + 0xfe030000)
+#define DSP_MAILBOX_CLR_11 ((0x006b << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_0 ((0x0070 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_1 ((0x0071 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_2 ((0x0072 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_3 ((0x0073 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_4 ((0x0074 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_5 ((0x0075 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_6 ((0x0076 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_7 ((0x0077 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_8 ((0x0078 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_9 ((0x0079 << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_10 ((0x007a << 2) + 0xfe030000)
+#define DSP_MAILBOX_STAT_11 ((0x007b << 2) + 0xfe030000)
+#define DSP_QIF_CTRL ((0x0080 << 2) + 0xfe030000)
+#define DSP_QIF_STS ((0x0081 << 2) + 0xfe030000)
+#define DSP_WRFIFO_TOCPUA ((0x0082 << 2) + 0xfe030000)
+#define DSP_WRFIFO_TOCPUB ((0x0083 << 2) + 0xfe030000)
+#define DSP_WRFIFO_TODSP ((0x0084 << 2) + 0xfe030000)
+#define DSP_RDFIFO_FRCPUA ((0x0088 << 2) + 0xfe030000)
+#define DSP_RDFIFO_FRCPUB ((0x0089 << 2) + 0xfe030000)
+#define DSP_RDFIFO_FRDSP ((0x008a << 2) + 0xfe030000)
+//========================================================================
+// DSPB - Registers
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe040000
+// -----------------------------------------------
+#define DSPB_CFG0 ((0x0000 << 2) + 0xfe040000)
+#define DSPB_CFG1 ((0x0001 << 2) + 0xfe040000)
+#define DSPB_CFG2 ((0x0002 << 2) + 0xfe040000)
+#define DSPB_IMPWIRE ((0x0003 << 2) + 0xfe040000)
+#define DSPB_RESET_VEC ((0x0004 << 2) + 0xfe040000)
+#define DSPB_SEC_CFG0 ((0x0006 << 2) + 0xfe040000)
+#define DSPB_SEC_CFG1 ((0x0007 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL0 ((0x0010 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL1 ((0x0011 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL2 ((0x0012 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL3 ((0x0013 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL4 ((0x0014 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL5 ((0x0015 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL6 ((0x0016 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL7 ((0x0017 << 2) + 0xfe040000)
+#define DSPB_IRQ_CTRL8 ((0x0018 << 2) + 0xfe040000)
+#define DSPB_IRQ_STS ((0x001f << 2) + 0xfe040000)
+#define DSPB_REMAP0 ((0x0020 << 2) + 0xfe040000)
+#define DSPB_REMAP1 ((0x0021 << 2) + 0xfe040000)
+#define DSPB_REMAP2 ((0x0022 << 2) + 0xfe040000)
+#define DSPB_STS0 ((0x0040 << 2) + 0xfe040000)
+#define DSPB_STS1 ((0x0041 << 2) + 0xfe040000)
+#define DSPB_STS2 ((0x0042 << 2) + 0xfe040000)
+#define DSPB_STS3 ((0x0043 << 2) + 0xfe040000)
+#define DSPB_STS4 ((0x0044 << 2) + 0xfe040000)
+#define DSPB_STS5 ((0x0045 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_0 ((0x0050 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_1 ((0x0051 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_2 ((0x0052 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_3 ((0x0053 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_4 ((0x0054 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_5 ((0x0055 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_6 ((0x0056 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_7 ((0x0057 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_8 ((0x0058 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_9 ((0x0059 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_10 ((0x005a << 2) + 0xfe040000)
+#define DSPB_MAILBOX_SET_11 ((0x005b << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_0 ((0x0060 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_1 ((0x0061 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_2 ((0x0062 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_3 ((0x0063 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_4 ((0x0064 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_5 ((0x0065 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_6 ((0x0066 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_7 ((0x0067 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_8 ((0x0068 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_9 ((0x0069 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_10 ((0x006a << 2) + 0xfe040000)
+#define DSPB_MAILBOX_CLR_11 ((0x006b << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_0 ((0x0070 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_1 ((0x0071 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_2 ((0x0072 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_3 ((0x0073 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_4 ((0x0074 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_5 ((0x0075 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_6 ((0x0076 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_7 ((0x0077 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_8 ((0x0078 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_9 ((0x0079 << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_10 ((0x007a << 2) + 0xfe040000)
+#define DSPB_MAILBOX_STAT_11 ((0x007b << 2) + 0xfe040000)
+#define DSPB_QIF_CTRL ((0x0080 << 2) + 0xfe040000)
+#define DSPB_QIF_STS ((0x0081 << 2) + 0xfe040000)
+#define DSPB_WRFIFO_TOCPUA ((0x0082 << 2) + 0xfe040000)
+#define DSPB_WRFIFO_TOCPUB ((0x0083 << 2) + 0xfe040000)
+#define DSPB_WRFIFO_TODSP ((0x0084 << 2) + 0xfe040000)
+#define DSPB_RDFIFO_FRCPUA ((0x0088 << 2) + 0xfe040000)
+#define DSPB_RDFIFO_FRCPUB ((0x0089 << 2) + 0xfe040000)
+#define DSPB_RDFIFO_FRDSP ((0x008a << 2) + 0xfe040000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: REG_LIST_DSP_RTL.h
+//
+//
+// Reading file: REG_LIST_DOS_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// `define APB_DOS_VDEC_ADDR_OFFSET 6'h00 // VDEC 1
+// -----------------------------------------------
+// -----------------------------------------------
+// `define APB_DOS_HCODEC_ADDR_OFFSET 6'h10 // HCODEC 1
+// -----------------------------------------------
+// -----------------------------------------------
+// `define APB_DOS_VDEC2_ADDR_OFFSET 6'h20 // VDEC 2 // Share with HEVC2
+// -----------------------------------------------
+// -----------------------------------------------
+// `define APB_DOS_HEVC2_ADDR_OFFSET 6'h20 // HEVC 2 // Share with VDEC2
+// -----------------------------------------------
+// -----------------------------------------------
+// `define APB_DOS_HEVC_ADDR_OFFSET 6'h30 // HEVC
+// -----------------------------------------------
+//========================================================================
+// DOS - Registers
+//========================================================================
+// VDEC
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe060000
+// -----------------------------------------------
+// HCODEC
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe064000
+// -----------------------------------------------
+// -----------------------------------------------
+// `define DOS_HCODEC_ASSIST_CBUS_BASE 8'h00
+// -----------------------------------------------
+#define HCODEC_ASSIST_MMC_CTRL0 ((0x0001 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MMC_CTRL1 ((0x0002 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MMC_CTRL2 ((0x0003 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MMC_CTRL3 ((0x0004 << 2) + 0xfe064000)
+// bit[11] canvas_blk32_wr
+// bit[10] canvas_blk32
+// bit[9] Reserved
+// bit[8] canvas_index_wr
+// bit[7:0] canvas_index
+#define HCODEC_ASSIST_CANVAS_BLK32 ((0x0005 << 2) + 0xfe064000)
+//cfg_soft_rst = mfdin_reg0_crst[0]; // Soft Reset
+//cfg_cg_cfe = mfdin_reg0_crst[1]; // Clock Gating Forcing Enable
+//cfg_dbuf_rst = mfdin_reg0_crst[2]; // Reset DBUF information
+#define HCODEC_MFDIN_REG0_CRST ((0x0008 << 2) + 0xfe064000)
+//cfg_iformat = mfdin_reg1_ctrl[3:0]; // Data In Format: 0 :CANVAS 422 YCbCr<-one canvas,
+ // 1 :CANVAS 444 YCbCr(or RGB)<-one canvas,
+ // 2 :CANVAS 420 Y<-one CrCb<-one (NV21)
+ // 3 :CANVAS 420 Y<-one CbCr<-one (NV12)
+ // 4 :CANVAS 420 Y<-one Cb<-one Cr<-one
+ // 5 :CANVAS 444 Y<-one Cb<-one Cr<-one
+ // 6 : Reserved for other canvas mode
+ // 7 : should combine with cfg_ifmt_extra, for 10-12bits
+ // 8 :LINEAR RGB888 (24bit)
+ // 9 :LINEAR RGB565 (16bit)
+ // 10:LINEAR YUV422
+ // 11:LINEAR YUV420 (Note:Legacy mode not supported)
+ // 12~15: Reserved for other linear mode
+//cfg_oformat = mfdin_reg1_ctrl[5:4]; // Data Out Format: 0:420 1:422 2:444 3:reserved
+//cfg_dsample_enable= mfdin_reg1_ctrl[6]; // Downsample Enable
+//cfg_dsample_trunc = mfdin_reg1_ctrl[7]; // Downsample Addition Option: 0:Round 1:Truncated
+//cfg_block_ysize = mfdin_reg1_ctrl[8]; // 0:block-y-size=16, 1:block-y-size=8(for JPEG's efficiency)
+//cfg_interp_enable = mfdin_reg1_ctrl[9]; // Chroma Interpolation Enable
+//cfg_interp_mode = mfdin_reg1_ctrl[11:10];// 0:average round 1:average truncated 2:repeat left 3:repeat right
+//cfg_r2y_enable = mfdin_reg1_ctrl[12]; // RGb->YUV Enable
+//cfg_r2y_mode = mfdin_reg1_ctrl[14:13];// RGb->YUV Mode
+//cfg_rgb565_mode = mfdin_reg1_ctrl[15]; // RGB565 mode: 0:fill zero in tail 1:fill zero in head
+//cfg_ifmt_extra = mfdin_reg1_ctrl[17:16];// when cfg_iformat==7,
+ // 0: CANVAS 12bit 422, YCbCr<-one canvas{...Y1[11:0],C1[11:0],Y0[11:0],C0[11:0]}
+ // 1: CANVAS 10bit 444, YCbCr<-one canvas{...2'b0,Y0[9:0],U0[9:0],V0[9:0]}
+ // 2: CANVAS 10bit 422, YCbCr<-one canvas{...Y1[9:0],C1[9:0],Y0[9:0],C0[9:0]}
+//cfg_reserved1 = mfdin_reg1_ctrl[18]; // Reserved
+//cfg_nr_enable = mfdin_reg1_ctrl[19]; // Noise Reduction Enable
+//cfg_outofpic = mfdin_reg1_ctrl[28:20];// Out Of Picture Control: [8]mode:0:extend 1:fixed, [7:0]fixed value
+//cfg_rd_blktype = mfdin_reg1_ctrl[30:29];// Block Type: 0:H264_I_PIC_ALL_4x4, 1:H264_P_PIC_Y_16x16_C_8x8, 2:JPEG_ALL_8x8, 3:Reserved
+//cfg_rd_nonycintl = mfdin_reg1_ctrl[31]; // 0:YC interleaved 1:YC non-interleaved(for JPEG)
+#define HCODEC_MFDIN_REG1_CTRL ((0x0009 << 2) + 0xfe064000)
+//mfdin_reg2: DEBUG Only Status
+#define HCODEC_MFDIN_REG2_STAT ((0x000a << 2) + 0xfe064000)
+//cfg_canvas_index0 = mfdin_reg3_canv[7:0]; //canvas index 0
+//cfg_canvas_index1 = mfdin_reg3_canv[15:8]; //canvas index 1
+//cfg_canvas_index2 = mfdin_reg3_canv[23:16];//canvas index 2
+//cfg_canv_idx0_bppx = mfdin_reg3_canv[25:24];//canvas bytes per pixel in x direction for index0, 0:half 1:1 2:2 3:3
+//cfg_canv_idx1_bppx = mfdin_reg3_canv[27:26];//canvas bytes per pixel in x direction for index1, 0:half 1:1 2:2 3:3
+//cfg_canv_idx0_bppy = mfdin_reg3_canv[29:28];//canvas bytes per pixel in y direction for index0, 0:half 1:1 2:2 3:3
+//cfg_canv_idx1_bppy = mfdin_reg3_canv[31:30];//canvas bytes per pixel in y direction for index1, 0:half 1:1 2:2 3:3
+#define HCODEC_MFDIN_REG3_CANV ((0x000b << 2) + 0xfe064000)
+//cfg_bytes_per_line = mfdin_reg4_lnr0[15:0]; //linear Bytes per line
+//cfg_linear_bytes4p = mfdin_reg4_lnr0[17:16]; //linear (Bytes per pixel) - 1
+//cfg_linear_dbl2line = mfdin_reg4_lnr0[18]; //linear double size for odd line
+#define HCODEC_MFDIN_REG4_LNR0 ((0x000c << 2) + 0xfe064000)
+//cfg_base_address = mfdin_reg5_lnr1[31:0]; //linear base address
+#define HCODEC_MFDIN_REG5_LNR1 ((0x000d << 2) + 0xfe064000)
+//assign cfg_r2y_trunc = mfdin_reg6_dcfg[9]; //RGb->YUV Addition Option: 0:Round 1:Truncated
+//assign cfg_dma_ugt = mfdin_reg6_dcfg[8]; //DMA Urgent
+//assign cfg_dma_thread_id = mfdin_reg6_dcfg[7:6]; //DMA Thread ID
+//assign cfg_dma_burst_num = mfdin_reg6_dcfg[5:0]; //DMA Burst Number
+#define HCODEC_MFDIN_REG6_DCFG ((0x000e << 2) + 0xfe064000)
+//cfg_soft_cmd = mfdin_reg7_scmd; // Soft Command [28]selfcleared start,[27:14]dmb_x,[13:0]dmb_y
+#define HCODEC_MFDIN_REG7_SCMD ((0x000f << 2) + 0xfe064000)
+//cfg_pic_xsize = mfdin_reg8_dmbl[23:12]; //pixel (x,y) at the begining of last dmb in the picturem, picture x size
+//cfg_pic_ysize = mfdin_reg8_dmbl[11:0]; //picture y size
+#define HCODEC_MFDIN_REG8_DMBL ((0x0010 << 2) + 0xfe064000)
+//cfg_endian = mfdin_reg9_endn; //Endian Control
+#define HCODEC_MFDIN_REG9_ENDN ((0x0011 << 2) + 0xfe064000)
+//cfg_canv_biasx = mfdin_rega_cav1[23:12]; //canvas bias address x
+//cfg_canv_biasy = mfdin_rega_cav1[11:0]; //canvas bias address y
+#define HCODEC_MFDIN_REGA_CAV1 ((0x0012 << 2) + 0xfe064000)
+//cfg_amp_en = mfdin_regb_ampc[24]; //Amplitude Enable
+//cfg_amp_cy = mfdin_regb_ampc[23:16]; //Amplitude Coeff Y
+//cfg_amp_cu = mfdin_regb_ampc[15:8]; //Amplitude Coeff U
+//cfg_amp_cv = mfdin_regb_ampc[7:0]; //Amplitude Coeff V
+#define HCODEC_MFDIN_REGB_AMPC ((0x0013 << 2) + 0xfe064000)
+//cfg_mb_end = mfdin_regc_mblp; // Soft Command [28]mb end enable,[27:14]dmb_x,[13:0]dmb_y
+#define HCODEC_MFDIN_REGC_MBLP ((0x0014 << 2) + 0xfe064000)
+// cfg_y_snr_en = mfdin_reg0d[0];
+// cfg_y_snr_err_norm = mfdin_reg0d[1];
+// [3:0] cfg_y_snr_gau_bld_core = mfdin_reg0d[5:2];
+// [7:0] cfg_y_snr_gau_bld_ofst = mfdin_reg0d[13:6];
+// [5:0] cfg_y_snr_gau_bld_rate = mfdin_reg0d[19:14];
+// [5:0] cfg_y_snr_gau_alp0_min = mfdin_reg0d[25:20];
+// [5:0] cfg_y_snr_gau_alp0_max = mfdin_reg0d[31:26];
+#define HCODEC_MFDIN_REG0D ((0x0015 << 2) + 0xfe064000)
+// cfg_y_tnr_en = mfdin_reg0e[0];
+// cfg_y_tnr_mc_en = mfdin_reg0e[1];
+// cfg_y_tnr_txt_mode = mfdin_reg0e[2];
+// [3:0] cfg_y_tnr_mot_sad_margin = mfdin_reg0e[6:3];
+// [5:0] cfg_y_tnr_alpha_min = mfdin_reg0e[12:7];
+// [5:0] cfg_y_tnr_alpha_max = mfdin_reg0e[18:13];
+// [5:0] cfg_y_tnr_deghost_os = mfdin_reg0e[24:19];
+#define HCODEC_MFDIN_REG0E ((0x0016 << 2) + 0xfe064000)
+// [3:0] cfg_y_tnr_mot_cortxt_rate = mfdin_reg0f[3:0];
+// [7:0] cfg_y_tnr_mot_distxt_ofst = mfdin_reg0f[15:8];
+// [3:0] cfg_y_tnr_mot_distxt_rate = mfdin_reg0f[7:4];
+// [7:0] cfg_y_tnr_mot_dismot_ofst = mfdin_reg0f[23:16];
+// [7:0] cfg_y_tnr_mot_frcsad_lock = mfdin_reg0f[31:24];
+#define HCODEC_MFDIN_REG0F ((0x0017 << 2) + 0xfe064000)
+// [7:0] cfg_y_tnr_mot2alp_frc_gain = mfdin_reg10[7:0];
+// [7:0] cfg_y_tnr_mot2alp_nrm_gain = mfdin_reg10[15:8];
+// [7:0] cfg_y_tnr_mot2alp_dis_gain = mfdin_reg10[23:16];
+// [5:0] cfg_y_tnr_mot2alp_dis_ofst = mfdin_reg10[29:24];
+#define HCODEC_MFDIN_REG10 ((0x0018 << 2) + 0xfe064000)
+// [7:0] cfg_y_bld_beta2alp_rate = mfdin_reg11[7:0];
+// [5:0] cfg_y_bld_beta_min = mfdin_reg11[13:8];
+// [5:0] cfg_y_bld_beta_max = mfdin_reg11[19:14];
+#define HCODEC_MFDIN_REG11 ((0x0019 << 2) + 0xfe064000)
+// REG12~16 for Chroma, same as Luma
+#define HCODEC_MFDIN_REG12 ((0x001a << 2) + 0xfe064000)
+#define HCODEC_MFDIN_REG13 ((0x001b << 2) + 0xfe064000)
+#define HCODEC_MFDIN_REG14 ((0x001c << 2) + 0xfe064000)
+#define HCODEC_MFDIN_REG15 ((0x001d << 2) + 0xfe064000)
+#define HCODEC_MFDIN_REG16 ((0x001e << 2) + 0xfe064000)
+#define HCODEC_MFDIN_REG17 ((0x001f << 2) + 0xfe064000)
+#define HCODEC_MFDIN_REG18 ((0x0020 << 2) + 0xfe064000)
+#define HCODEC_MFDIN_REG19 ((0x0021 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT0 ((0x0025 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT1 ((0x0026 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT2 ((0x0027 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT3 ((0x0028 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT4 ((0x0029 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT5 ((0x002a << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT6 ((0x002b << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT7 ((0x002c << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT8 ((0x002d << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INT9 ((0x002e << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INTA ((0x002f << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INTB ((0x0030 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INTC ((0x0031 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INTD ((0x0032 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INTE ((0x0033 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR1_INTF ((0x0034 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT0 ((0x0035 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT1 ((0x0036 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT2 ((0x0037 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT3 ((0x0038 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT4 ((0x0039 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT5 ((0x003a << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT6 ((0x003b << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT7 ((0x003c << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT8 ((0x003d << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INT9 ((0x003e << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INTA ((0x003f << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INTB ((0x0040 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INTC ((0x0041 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INTD ((0x0042 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INTE ((0x0043 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AMR2_INTF ((0x0044 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBX_SSEL ((0x0045 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_TIMER0_LO ((0x0060 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_TIMER0_HI ((0x0061 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_TIMER1_LO ((0x0062 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_TIMER1_HI ((0x0063 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_DMA_INT ((0x0064 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_DMA_INT_MSK ((0x0065 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_DMA_INT2 ((0x0066 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_DMA_INT_MSK2 ((0x0067 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX0_IRQ_REG ((0x0070 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX0_CLR_REG ((0x0071 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX0_MASK ((0x0072 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX0_FIQ_SEL ((0x0073 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX1_IRQ_REG ((0x0074 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX1_CLR_REG ((0x0075 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX1_MASK ((0x0076 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX1_FIQ_SEL ((0x0077 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX2_IRQ_REG ((0x0078 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX2_CLR_REG ((0x0079 << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX2_MASK ((0x007a << 2) + 0xfe064000)
+#define HCODEC_ASSIST_MBOX2_FIQ_SEL ((0x007b << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AXI_CTRL ((0x007c << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AXI_STATUS ((0x007d << 2) + 0xfe064000)
+#define HCODEC_ASSIST_AXI_SETTING_VLC ((0x007e << 2) + 0xfe064000)
+//------------------------------------------------------------------------------
+// HCODEC IQIDCT module level register offset
+//------------------------------------------------------------------------------
+// `define DOS_HCODEC_VCPU_CBUS_BASE 8'h03
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe064c00
+// -----------------------------------------------
+//
+// Reading file: hcodec_vcpu_regs.h
+//
+//========================================================================
+// VCPU module level register offset
+//========================================================================
+// -----------------------------------------------
+// `define DOS_HCODEC_VCPU_CBUS_BASE 8'h03
+// -----------------------------------------------
+#define HCODEC_MSP ((0x0000 << 2) + 0xfe064c00)
+#define HCODEC_MPSR ((0x0001 << 2) + 0xfe064c00)
+#define HCODEC_MINT_VEC_BASE ((0x0002 << 2) + 0xfe064c00)
+#define HCODEC_MCPU_INTR_GRP ((0x0003 << 2) + 0xfe064c00)
+#define HCODEC_MCPU_INTR_MSK ((0x0004 << 2) + 0xfe064c00)
+#define HCODEC_MCPU_INTR_REQ ((0x0005 << 2) + 0xfe064c00)
+//`define HCODEC_MPC_P 8'h06
+//`define HCODEC_MPC_D 8'h07
+//`define HCODEC_MPC_E 8'h08
+//`define HCODEC_MPC_W 8'h09
+//`define HCODEC_MINDEX0_REG 8'h0a
+//`define HCODEC_MINDEX1_REG 8'h0b
+//`define HCODEC_MINDEX2_REG 8'h0c
+//`define HCODEC_MINDEX3_REG 8'h0d
+//`define HCODEC_MINDEX4_REG 8'h0e
+//`define HCODEC_MINDEX5_REG 8'h0f
+//`define HCODEC_MINDEX6_REG 8'h10
+//`define HCODEC_MINDEX7_REG 8'h11
+//`define HCODEC_MMIN_REG 8'h12
+//`define HCODEC_MMAX_REG 8'h13
+//`define HCODEC_MBREAK0_REG 8'h14
+//`define HCODEC_MBREAK1_REG 8'h15
+//`define HCODEC_MBREAK2_REG 8'h16
+//`define HCODEC_MBREAK3_REG 8'h17
+//`define HCODEC_MBREAK_TYPE 8'h18
+//`define HCODEC_MBREAK_CTRL 8'h19
+//`define HCODEC_MBREAK_STAUTS 8'h1a
+//`define HCODEC_MDB_ADDR_REG 8'h1b
+//`define HCODEC_MDB_DATA_REG 8'h1c
+//`define HCODEC_MDB_CTRL 8'h1d
+//`define HCODEC_MSFTINT0 8'h1e
+//`define HCODEC_MSFTINT1 8'h1f
+//
+#define HCODEC_CSP ((0x0020 << 2) + 0xfe064c00)
+#define HCODEC_CPSR ((0x0021 << 2) + 0xfe064c00)
+//`define HCODEC_CINT_VEC_BASE 8'h22
+//`define HCODEC_CCPU_INTR_GRP 8'h23
+//`define HCODEC_CCPU_INTR_MSK 8'h24
+//`define HCODEC_CCPU_INTR_REQ 8'h25
+//`define HCODEC_CPC_P 8'h26
+//`define HCODEC_CPC_D 8'h27
+//`define HCODEC_CPC_E 8'h28
+//`define HCODEC_CPC_W 8'h29
+//`define HCODEC_CINDEX0_REG 8'h2a
+//`define HCODEC_CINDEX1_REG 8'h2b
+//`define HCODEC_CINDEX2_REG 8'h2c
+//`define HCODEC_CINDEX3_REG 8'h2d
+//`define HCODEC_CINDEX4_REG 8'h2e
+//`define HCODEC_CINDEX5_REG 8'h2f
+//`define HCODEC_CINDEX6_REG 8'h30
+//`define HCODEC_CINDEX7_REG 8'h31
+//`define HCODEC_CMIN_REG 8'h32
+//`define HCODEC_CMAX_REG 8'h33
+//`define HCODEC_CBREAK0_REG 8'h34
+//`define HCODEC_CBREAK1_REG 8'h35
+//`define HCODEC_CBREAK2_REG 8'h36
+//`define HCODEC_CBREAK3_REG 8'h37
+//`define HCODEC_CBREAK_TYPE 8'h38
+//`define HCODEC_CBREAK_CTRL 8'h39
+//`define HCODEC_CBREAK_STAUTS 8'h3a
+//`define HCODEC_CDB_ADDR_REG 8'h3b
+//`define HCODEC_CDB_DATA_REG 8'h3c
+//`define HCODEC_CDB_CTRL 8'h3d
+//`define HCODEC_CSFTINT0 8'h3e
+//`define HCODEC_CSFTINT1 8'h3f
+//
+#define HCODEC_IMEM_DMA_CTRL ((0x0040 << 2) + 0xfe064c00)
+#define HCODEC_IMEM_DMA_ADR ((0x0041 << 2) + 0xfe064c00)
+#define HCODEC_IMEM_DMA_COUNT ((0x0042 << 2) + 0xfe064c00)
+//// bit[29:24] A_brst_num_imem
+//// bit[21:16] A_id_imem
+//// bit[11:0] wrrsp_count_imem (reserved)
+#define HCODEC_WRRSP_IMEM ((0x0043 << 2) + 0xfe064c00)
+//
+//`define HCODEC_LMEM_DMA_CTRL 8'h50
+//`define HCODEC_LMEM_DMA_ADR 8'h51
+//`define HCODEC_LMEM_DMA_COUNT 8'h52
+//// bit[29:24] A_brst_num_lmem
+//// bit[21:16] A_id_lmem
+//// bit[11:0] wrrsp_count_lmem
+//`define HCODEC_WRRSP_LMEM 8'h53
+//
+//`define HCODEC_MAC_CTRL1 8'h60
+//`define HCODEC_ACC0REG1 8'h61
+//`define HCODEC_ACC1REG1 8'h62
+//
+//`define HCODEC_MAC_CTRL2 8'h70
+//`define HCODEC_ACC0REG2 8'h71
+//`define HCODEC_ACC1REG2 8'h72
+//`define HCODEC_CPU_TRACE 8'h80
+//
+//
+// Closing file: hcodec_vcpu_regs.h
+//
+//------------------------------------------------------------------------------
+// -----------------------------------------------
+// `define DOS_HCODEC_HDEC_CBUS_BASE 8'h09
+// -----------------------------------------------
+//------------------------------------------------------------------------------
+// HENC module level register offset
+//------------------------------------------------------------------------------
+// `define DOS_HCODEC_HENC_CBUS_BASE 8'h0a
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe066800
+// -----------------------------------------------
+//
+// Reading file: henc_regs.h
+//
+//========================================================================
+// MDEC module level register offset
+//========================================================================
+// -----------------------------------------------
+// `define DOS_HCODEC_HENC_CBUS_BASE 8'h0a
+// -----------------------------------------------
+#define HENC_SCRATCH_0 ((0x00c0 << 2) + 0xfe066800)
+#define HENC_SCRATCH_1 ((0x00c1 << 2) + 0xfe066800)
+#define HENC_SCRATCH_2 ((0x00c2 << 2) + 0xfe066800)
+#define HENC_SCRATCH_3 ((0x00c3 << 2) + 0xfe066800)
+#define HENC_SCRATCH_4 ((0x00c4 << 2) + 0xfe066800)
+#define HENC_SCRATCH_5 ((0x00c5 << 2) + 0xfe066800)
+#define HENC_SCRATCH_6 ((0x00c6 << 2) + 0xfe066800)
+#define HENC_SCRATCH_7 ((0x00c7 << 2) + 0xfe066800)
+#define HENC_SCRATCH_8 ((0x00c8 << 2) + 0xfe066800)
+#define HENC_SCRATCH_9 ((0x00c9 << 2) + 0xfe066800)
+#define HENC_SCRATCH_A ((0x00ca << 2) + 0xfe066800)
+#define HENC_SCRATCH_B ((0x00cb << 2) + 0xfe066800)
+#define HENC_SCRATCH_C ((0x00cc << 2) + 0xfe066800)
+#define HENC_SCRATCH_D ((0x00cd << 2) + 0xfe066800)
+#define HENC_SCRATCH_E ((0x00ce << 2) + 0xfe066800)
+#define HENC_SCRATCH_F ((0x00cf << 2) + 0xfe066800)
+#define HENC_SCRATCH_G ((0x00d0 << 2) + 0xfe066800)
+#define HENC_SCRATCH_H ((0x00d1 << 2) + 0xfe066800)
+#define HENC_SCRATCH_I ((0x00d2 << 2) + 0xfe066800)
+#define HENC_SCRATCH_J ((0x00d3 << 2) + 0xfe066800)
+#define HENC_SCRATCH_K ((0x00d4 << 2) + 0xfe066800)
+#define HENC_SCRATCH_L ((0x00d5 << 2) + 0xfe066800)
+#define HENC_SCRATCH_M ((0x00d6 << 2) + 0xfe066800)
+#define HENC_SCRATCH_N ((0x00d7 << 2) + 0xfe066800)
+// bit [7:0] data_feed_buff_id
+#define IE_DATA_FEED_BUFF_INFO ((0x00d8 << 2) + 0xfe066800)
+//
+// Closing file: henc_regs.h
+//
+//------------------------------------------------------------------------------
+// -----------------------------------------------
+// `define DOS_HCODEC_VLD_CBUS_BASE 8'h0c
+// -----------------------------------------------
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+// VLC module level register offset
+//------------------------------------------------------------------------------
+// `define DOS_HCODEC_VLC_CBUS_BASE 8'h0d
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe067400
+// -----------------------------------------------
+//
+// Reading file: vlc_regs.h
+//
+//========================================================================
+// VLC module level register offset
+//========================================================================
+// -----------------------------------------------
+// `define DOS_HCODEC_VLC_CBUS_BASE 8'h0d
+// -----------------------------------------------
+// Bit[31:28] - henc_status
+// Bit[27:9] - reserved
+// Bit[8] disable_UVLC_SKIP_fix
+// Bit[7] mc_hcmd_buff_enable
+// Bit[6] mc_hcmd_use_mc_hcmd_buff
+// Bit[5] mc_hcmd_use_mc_hcmd_hw_start
+// Bit[4] no_mc_out_null_non_skipped_mb
+// Bit[3] mc_out_even_skipped_mb
+// Bit[2] - hcmd_enable
+// Bit[1] - vlc_control_enable (0 will treat as soft_reset)
+// Bit[0] - vlc_input_enable (enable input interface)
+#define VLC_STATUS_CTRL ((0x0000 << 2) + 0xfe067400)
+// Bit [31] - small_luma_ignore_chroma
+// Bit[30:16] - Reserved
+// Bit [15] - enable_free_clk_mc_hcmd_buff
+// Bit [14] - enable_free_clk_reg
+// Bit [13] - enable_free_clk_stream
+// Bit [12] - enable_free_clk_pre_buff
+// Bit [11] - enable_free_clk_vb_buff
+// Bit [10] - enable_free_clk_dc_input
+// Bit [9] - enable_free_clk_input
+// Bit [8] - enable_free_clk_mv_cal
+// Bit [7] - enable_free_clk_status
+// Bit [6] - enable_free_clk_mc_dblk_cmd_if
+// Bit [5] - disable_mvd_enc_finished
+// Bit [4] - I16MB_share_ipred_mode_with_I4MB
+// Bit [3] - fixed_picture_qp
+// Bit [2] - use_set_b8_mode ( not used now)
+// Bit [1] - use_set_mb_skip_run
+// Bit [0] - pop_coeff_even_all_zero
+#define VLC_CONFIG ((0x0001 << 2) + 0xfe067400)
+// --------------------------------------------
+// Bitstream DDR Interface
+// --------------------------------------------
+#define VLC_VB_START_PTR ((0x0010 << 2) + 0xfe067400)
+#define VLC_VB_END_PTR ((0x0011 << 2) + 0xfe067400)
+#define VLC_VB_WR_PTR ((0x0012 << 2) + 0xfe067400)
+// Read Only, VLC_VB_SW_RD_PTR or VLC_VB_HW_RD_PTR
+#define VLC_VB_RD_PTR ((0x0013 << 2) + 0xfe067400)
+#define VLC_VB_SW_RD_PTR ((0x0014 << 2) + 0xfe067400)
+// Read Only
+#define VLC_VB_LEFT ((0x0015 << 2) + 0xfe067400)
+// VB FIFO Control
+// bit [31:24] vb_full_int_enable_cpu[7:0]
+// bit [23:16] vb_full_int_enable_amrisc[7:0]
+// -bit 23 Video BUFFER LEFT < 0x400 Bytes
+// -bit 22 Video BUFFER LEFT < 0x200 Bytes
+// -bit 21 Video BUFFER LEFT < 0x100 Bytes
+// -bit 20 Video BUFFER LEFT < 0x80 Bytes
+// -bit 19 Video BUFFER LEFT < 0x40 Bytes
+// -bit 18 Video BUFFER LEFT < 0x20 Bytes
+// -bit 17 vbfifo left < 16 double words (8x64bits)
+// -bit 16 vbfifo left < 8 double words (4x64bits)
+// bit [15] wr_ptr_int_enable_cpu
+// bit [14] wr_ptr_int_enable_amrisc
+// bit [13] wr_ptr_int (Read Only, write 1 will clear)
+// bit [12] vb_full_int_enable_cpu(Read Only)
+// bit [11] vb_full_int_enable_amrisc(Read Only)
+// bit [10] reserved
+// bit [9] use_vb_hw_rd_ptr
+// bit [8] vb_always_ready Set to 1 to ignore vb_level blocking DDR write
+// bit [7] vb_ready_for_transfer (Read Only)
+// bit [6] data_ready_for_transfer (Read Only)
+// bits [5:3] vb_endian Set VB Endian inside DDR memory
+// bit [2] vb_write_busy Read Only - indicate DDR write busy
+// bit [1] vb_write_en Set to 1 to enable writing data to DDR memory
+// bit [0] vb_soft_reset Soft reset
+#define VLC_VB_CONTROL ((0x0016 << 2) + 0xfe067400)
+// bit 31 transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request // default : 0
+// bit 30 A_urgent // default : 0
+// bit 29:24 A_brst_num // default : 0x3f
+// bit 23:22 reserved
+// bit 21:16 A_id // default : 0x20
+// bit 15:0 vb_left_hold // default : 0
+#define VLC_VB_MEM_CTL ((0x0017 << 2) + 0xfe067400)
+// vb_wr_ptr address to generate interrupt
+#define VLC_VB_INT_PTR ((0x0018 << 2) + 0xfe067400)
+// bit[31:12] reserved
+// bit[11:0] vlc_wrrsp_count
+#define VLC_WRRSP ((0x0019 << 2) + 0xfe067400)
+#define VLC_TOTAL_BYTES ((0x001a << 2) + 0xfe067400)
+// bit [31:26] reserved
+// bit [25] vb_flush
+// bit [24] vb_reg_ready
+// bit [23:16] vb_buff_left -- Read only
+// bit [15:8] vb_buff_wr_point -- RW
+// bit [7:0] vb_buff_rd_point -- RW
+#define VLC_VB_BUFF ((0x001b << 2) + 0xfe067400)
+// bit[31] flush_vlc_pre_buff
+// bit[30:27] reserved
+// bit[26:24] vb_pre_buff_level
+// bit[23:0] vb_pre_buff_data[55:32]
+#define VLC_VB_PRE_BUFF_HI ((0x001c << 2) + 0xfe067400)
+// bit[31:0] vb_pre_buff_data[31:0]
+#define VLC_VB_PRE_BUFF_LOW ((0x001d << 2) + 0xfe067400)
+// bit[31] stream_encap_enable // 0x0000(00-03) will be changed to 0x000003(00-03) if enabled
+// bit[30:29] stream_encap_delay // delay bytes for encap used
+// bit[28:24] stream_buff_point
+// bit[23:0] stream_buff_data
+#define VLC_STREAM_BUFF ((0x001e << 2) + 0xfe067400)
+// bit[31] push_stream_block - Read Only (Will set if vb_buff full)
+// bit[30] push_stream_busy - Read Only (busy when output one byte from stream_buf (max 2 clocks for 8 bits push)
+// bit[29:28] stream_encap_status - Read Only
+// bit[27:21] reserved
+// Long Mode : (Amrisc need movilo and mvihi high to set stream_info)
+// bit[20:16] push_stream_long_length (0 or 31 : Mid or Short mode)
+// bit[15:0] push_stream_data
+// Mid Mode : (Amrisc need movi to set stream_info)
+// bit[15:12]] push_stream_mid_length (1-12 : mid mode active, 0-short mode, 15 - byte align)
+// bit[11:0] push_stream_data
+// Short Mode : (Amrisc can use mtspi to push stream directely)
+// bit[7:5] push_stream_short_length (0-5 : short length, else - invalid)
+// bit[4:0] push_stream_data
+#define VLC_PUSH_STREAM ((0x001f << 2) + 0xfe067400)
+// bit[15:8] ELEMENT_LENGTH
+// bit[7:1] reserved
+// bit[0] Write - push start, Read - Push Busy
+#define VLC_PUSH_ELEMENT ((0x0020 << 2) + 0xfe067400)
+#define VLC_ELEMENT_DATA ((0x0021 << 2) + 0xfe067400)
+// bit[9] reset_last_dquant_ne_zero
+// bit[8] set_last_dquant_ne_zero
+// bit[7] hcmd_intra_use_sw_info
+// bit[6] hcmd_use_sw_info
+// bit[5] always_use_info_0_cbp_blk
+// bit[4] always_update_info_0_cbp_blk
+// bit[3] reset_left_mb_wr
+// bit[2] reset_top_mb_wr
+// bit[1] set_left_mb_wr
+// bit[0] set_top_mb_wr
+#define VLC_SPECIAL_CTL ((0x0022 << 2) + 0xfe067400)
+// bit[28] left_intra
+// bit[27:22] left_quant
+// bit[21:16] left_quant_c
+// bit[12] top_intra
+// bit[11:6] top_quant
+// bit[5:0] top_quant_c
+#define VLC_HCMD_T_L_INFO ((0x0023 << 2) + 0xfe067400)
+// bit[12] cur_intra
+// bit[11:6] cur_quant
+// bit[5:0] cur_quant_c
+#define VLC_HCMD_CUR_INFO ((0x0024 << 2) + 0xfe067400)
+// bit[13] top_left_info_in_data_mv_cal
+// bit[12] only_use_info_0_top_left_in_I
+// bit[11] top_left_info_in_data
+// bit[10] early_mix_mc_hcmd
+// bit[9] update_top_left_mix
+// bit[8] p_top_left_mix
+// bit[7] mv_cal_mixed_type
+// bit[6] mc_hcmd_mixed_type
+// bit[5] use_seperate_int_control
+// bit[4] hcmd_intra_use_q_info
+// bit[3] hcmd_left_use_prev_info
+// bit[2] hcmd_use_q_info
+// bit[1] use_q_delta_quant
+// bit[0] detect_I16_from_I4
+#define VLC_ADV_CONFIG ((0x0025 << 2) + 0xfe067400)
+// 31 - use_hcmd_mb_xy_auto
+//23:16 - hcmd_max_mb_x
+//15:8 - hcmd_mb_y_auto
+// 7:0 - hcmd_mb_x_auto
+#define VLC_HCMD_MBXY_AUTO ((0x0026 << 2) + 0xfe067400)
+// bit[31:0] vlc_int_control_inter -- will be used when use_seperate_int_control is set
+#define VLC_INT_CONTROL_INTER ((0x002f << 2) + 0xfe067400)
+// --------------------------------------------
+// Picture VLC
+// --------------------------------------------
+// (&(int|(~AND_enable))|(|(int&OR_enable)))
+// bit[31] OR interrupt Enable Reserved
+// bit[30] OR interrupt Enable for mv_busy
+// bit[29] OR interrupt Enable for b8_mode_busy
+// bit[28] OR interrupt Enable for mb_skip_run_busy
+// bit[27] OR interrupt Enable for cbp_busy
+// bit[26] OR interrupt Enable for Reserved
+// bit[25] OR interrupt Enable for Reserved
+// bit[24] OR interrupt Enable for mb_info_busy
+// bit[23] AND interrupt Enable Reserved
+// bit[22] AND interrupt Enable for mv_busy
+// bit[21] AND interrupt Enable for b8_mode_busy
+// bit[20] AND interrupt Enable for mb_skip_run_busy
+// bit[19] AND interrupt Enable for cbp_busy
+// bit[18] AND interrupt Enable for Reserved
+// bit[17] AND interrupt Enable for Reserved
+// bit[16] AND interrupt Enable for mb_info_busy
+// bit[15] OR interrupt Enable Reserved
+// bit[14] OR interrupt Enable for mvd
+// bit[13] OR interrupt Enable for b8_mode
+// bit[12] OR interrupt Enable for mb_skip_run
+// bit[11] OR interrupt Enable for cbp_ready
+// bit[10] OR interrupt Enable for c_ipred_mode_ready
+// bit[9] OR interrupt Enable for ipred_mode_ready
+// bit[8] OR interrupt Enable for mb_info_ready
+// bit[7] AND interrupt Enable Reserved
+// bit[6] AND interrupt Enable for mvd
+// bit[5] AND interrupt Enable for b8_mode
+// bit[4] AND interrupt Enable for mb_skip_run
+// bit[3] AND interrupt Enable for cbp_ready
+// bit[2] AND interrupt Enable for c_ipred_mode_ready
+// bit[1] AND interrupt Enable for ipred_mode_ready
+// bit[0] AND interrupt Enable for mb_info_ready
+#define VLC_INT_CONTROL ((0x0030 << 2) + 0xfe067400)
+// Bit[31:16] picture_height
+// Bit[15:0] picture_width
+#define VLC_PIC_SIZE ((0x0031 << 2) + 0xfe067400)
+// [31:16] Reserved
+// [15:3] pic_width_in_mbs_minus1
+// [2:0] picture_type
+#define VLC_PIC_INFO ((0x0032 << 2) + 0xfe067400)
+// Bit[31:16] MB_NR
+// Bit[15:8] MBY
+// Bit[7:0] MBX
+#define VLC_PIC_POSITION ((0x0033 << 2) + 0xfe067400)
+// Bit[31] MV_busy
+// Bit[30:6] Reserved
+// Bit[15] Reserved
+// Bit[14] vlc_input_MV_busy
+// Bit[13] vlc_input_b8_mode_busy
+// Bit[12] vlc_input_mb_skip_run_busy
+// Bit[11] vlc_input_cbp_busy
+// Bit[10] Reserved
+// Bit[9] Reserved
+// Bit[8] vlc_input_mb_info_busy
+// Bit[7] Reserved
+// Bit[6] mvd
+// Bit[5] b8_mode
+// Bit[4] mb_skip_run
+// Bit[3] cbp
+// Bit[2] c_ipred_mode
+// Bit[1] ipred_mode
+// Bit[0] mb_info ( mb_type, mb_x, mb_y)
+#define VLC_INPUT_STATUS ((0x0034 << 2) + 0xfe067400)
+// Bit[31:28] detected_mb_type
+// Bit[27:16] mb_y
+// Bit[15:4] mb_x
+// Bit[3:0] mb_type
+#define VLC_MB_INFO ((0x0035 << 2) + 0xfe067400)
+// commnad 0 -- no pending
+// normal command + 1 is pending command
+//
+// bit 31:28 -- pending command 7
+// bit 27:24 -- pending command 6
+// bit 23:20 -- pending command 5
+// bit 19:16 -- pending command 4
+// bit 15:12 -- pending command 3
+// bit 11:8 -- pending command 2
+// bit 7:4 -- pending command 1
+// bit 3:0 -- pending command 0
+#define VLC_ENC_PEND_CMD ((0x0036 << 2) + 0xfe067400)
+// For I Slice
+// Bit[31:16] Reserved
+// Bit[15:0] IntraType
+#define HENC_TOP_INFO_0 ((0x0037 << 2) + 0xfe067400)
+#define HENC_LEFT_INFO_0 ((0x0038 << 2) + 0xfe067400)
+// For I Slice
+// Bit[31:24] V_nnz
+// Bit[23:16] U_nnz
+// Bit[15:0] Y_nnz
+#define HENC_TOP_INFO_1 ((0x0039 << 2) + 0xfe067400)
+#define HENC_LEFT_INFO_1 ((0x003a << 2) + 0xfe067400)
+// bit[63:0] ipred_mode
+#define VLC_IPRED_MODE_HI ((0x003b << 2) + 0xfe067400)
+#define VLC_IPRED_MODE_LO ((0x003c << 2) + 0xfe067400)
+// bit[15:8] SE delta quant
+// bit[7:0] UE delta quant
+#define VLC_DELTA_QP ((0x003d << 2) + 0xfe067400)
+// bit[31:16] Reserved
+// bit[15:12] Reserved
+// bit[11:8] c_ipred_mode
+// bit[7:0] cbp
+#define VLC_MB_HEADER_INFO ((0x003e << 2) + 0xfe067400)
+// bit[31:16] mb_skip_run
+// bit[15:0] b8_mode
+#define VLC_P_MB_HEADER_INFO ((0x003f << 2) + 0xfe067400)
+// bit[31] write_ptr_update
+// bit[30] read_ptr_update
+// bit[29:20] coeff_buf_level
+// bit[19:10] coeff_buf_write_ptr
+// bit[9:0] coeff_buf_read_ptr
+#define VLC_COEFF_BUF_STATUS ((0x0040 << 2) + 0xfe067400)
+// bit[31:10] Reserved
+// bit[9:0] read_req_addr
+#define VLC_COEFF_RD_REQ ((0x0041 << 2) + 0xfe067400)
+// bit[20] - coeff_buf_read_finished
+// bit[19] - coeff_first
+// bit[18:4] - coeff_level
+// bit[3:0] - coeff_run
+#define VLC_COEFF ((0x0042 << 2) + 0xfe067400)
+// bit[31] - coeff_info_ready
+// bit[30:25] - Reserved
+// bit[24:15] - block_begin_addr
+// bit[14:11] - trailing_one_sign
+// bit[10:6] - total_coeff
+// bit[5:4] - trailing_ones
+// bit[3:0] - total_zeros
+#define VLC_COEFF_INFO ((0x0043 << 2) + 0xfe067400)
+// bit[31] write_ptr_update
+// bit[30] read_ptr_update
+// bit[29:25] Reserved
+// bit[24:20] dc_buf_level -- 0-16
+// bit[19:15] Reserved
+// bit[14:10] dc_buf_write_ptr
+// bit[9:5] Reserved
+// bit[4:0] dc_buf_read_ptr
+#define VLC_DC_BUF_STATUS ((0x0044 << 2) + 0xfe067400)
+// bit[31:10] Reserved
+// bit[9:4] Reserved
+// bit[3:0] read_req_addr
+#define VLC_DC_RD_REQ ((0x0045 << 2) + 0xfe067400)
+// bit[31:17] - Reserved
+// bit[16] - dc_first
+// bit[15:1] - dc_level
+// bit[0] - dc_type 0 - CDC, 1 - LDC
+#define VLC_DC ((0x0046 << 2) + 0xfe067400)
+// bit[31] - dc_info_ready
+// bit[30:25] - Reserved
+// bit[24:20] - Reserved
+// bit[19:15] - dc_idx_begin_addr
+// bit[14:11] - dc_trailing_one_sign
+// bit[10:6] - dc_total_coeff
+// bit[5:4] - dc_trailing_ones
+// bit[3:0] - dc_total_zeros
+#define VLC_DC_INFO ((0x0047 << 2) + 0xfe067400)
+// bit[31:4] - Reserved
+// bit[3:0] - mv_rw_idx (auto increment when read/write VLC_MV)
+#define VLC_MV_INDEX ((0x0048 << 2) + 0xfe067400)
+// bit[31:16] - MVY
+// bit[15:0] - MVX
+#define VLC_MV ((0x0049 << 2) + 0xfe067400)
+// bit[31:16] - MVY
+// bitp15:0] - MVX
+// Write to HENC_TOP_MV_0 will cause previous U->UL, UR->U, and UR write
+// Read will read U MV only
+#define HENC_TOP_MV_0 ((0x004a << 2) + 0xfe067400)
+#define HENC_TOP_MV_1 ((0x004b << 2) + 0xfe067400)
+#define HENC_TOP_MV_2 ((0x004c << 2) + 0xfe067400)
+#define HENC_TOP_MV_3 ((0x004d << 2) + 0xfe067400)
+#define HENC_LEFT_MV_0 ((0x004e << 2) + 0xfe067400)
+#define HENC_LEFT_MV_1 ((0x004f << 2) + 0xfe067400)
+#define HENC_LEFT_MV_2 ((0x0050 << 2) + 0xfe067400)
+#define HENC_LEFT_MV_3 ((0x0051 << 2) + 0xfe067400)
+// Bit[31:1] Reserved
+// Bit[0] top_left_mv_ready
+#define TOP_LEFT_READY ((0x0052 << 2) + 0xfe067400)
+// Bit[31:16] Reserved
+// Bit[15:0] mb_skip_run
+#define MB_SKIP_RUN ((0x0053 << 2) + 0xfe067400)
+// Bit[31:16] Reserved
+// Bit[15] Reserved
+// Bit[14:13] rd_struct // 00 - frame, 10 - top field, 11 - bottom field
+// Bit[12:11] wr_struct // 00 - frame, 10 - top field, 11 - bottom field
+// Bit[10:5] mv_buff_id
+// Bit[4:0] mv_ref
+#define VLC_HCMD_CONFIG ((0x0054 << 2) + 0xfe067400)
+// Bit[9:0] h264_dblk_info
+#define VLC_HCMD_DBLK_INFO ((0x0055 << 2) + 0xfe067400)
+// Bit[3:0] vlc_dbg_idx
+#define VLC_DBG_IDX ((0x0056 << 2) + 0xfe067400)
+// Read Only
+#define VLC_DBG_READ ((0x0057 << 2) + 0xfe067400)
+// [ 29] RW jpeg_comp2_ac_table_sel. Default 0.
+// [ 28] RW jpeg_comp2_dc_table_sel. Default 0.
+// [26:25] RW jpeg_comp2_cnt_max. Default 0.
+// [ 24] RW jpeg_comp2_en. Set 1 if the scan will include component 2 (Cr). Default 0.
+// [ 21] RW jpeg_comp1_ac_table_sel. Default 0.
+// [ 20] RW jpeg_comp1_dc_table_sel. Default 0.
+// [18:17] RW jpeg_comp1_cnt_max. Default 0.
+// [ 16] RW jpeg_comp1_en. Set 1 if the scan will include component 1 (Cb). Default 0.
+// [ 13] RW jpeg_comp0_ac_table_sel. Default 0.
+// [ 12] RW jpeg_comp0_dc_table_sel. Default 0.
+// [10: 9] RW jpeg_comp0_cnt_max. Default 0.
+// [ 8] RW jpeg_comp0_en. Set 1 if the scan will include component 0 (Y). Default 0.
+// [ 1] W jpeg_coeff_init. Write 1 to this bit to initialize JPEG run length encoder.
+// [ 0] RW jpeg_en. 0=Disable JPEG encoder; 1=Enable JPEG encoder. Default 0.
+#define VLC_JPEG_CTRL ((0x0058 << 2) + 0xfe067400)
+// [ 13] RW jpeg_coeff_buf_overfl. Write this bit to 1 to clear overfl.
+// [ 12] RW jpeg_coeff_buf_undrfl. Write this bit to 1 to clear undrfl.
+// [ 11] R jpeg_coeff_buf_full.
+// [ 10] R jpeg_coeff_buf_empty.
+// [ 8: 0] R jpeg_coeff_buf_level.
+#define VLC_JPEG_COEFF_BUF_STAT ((0x0059 << 2) + 0xfe067400)
+// [ 16] RW JPEG HUFFMAN table access mode. 0=Write; 1=Read. Default 1.
+// [ 8: 0] RW JPEG HUFFMAN table addr. Default 0.
+#define VLC_HUFFMAN_ADDR ((0x005a << 2) + 0xfe067400)
+// [19: 0] RW JPEG HUFFMAN table data.
+#define VLC_HUFFMAN_DATA ((0x005b << 2) + 0xfe067400)
+// bit[31:0] enc_mv_bits - including b8_mode and mvd
+#define VLC_ENC_MV_BITS ((0x005c << 2) + 0xfe067400)
+// bit[31:0] enc_coeff_bits - including cbp, token, trailing_sign, coeff_enc, h264_totzeros, h264_run
+#define VLC_ENC_COEFF_BITS ((0x005d << 2) + 0xfe067400)
+#define VLC_RESERVED_5E ((0x005e << 2) + 0xfe067400)
+#define VLC_RESERVED_5F ((0x005f << 2) + 0xfe067400)
+// ----------------------------------------------------------
+// CABAC
+// ----------------------------------------------------------
+// [15] h264_biari_init
+// [14] h264_cabac_init
+// [13:12] reserved
+// [11:10] picture_ty
+// [9:8] cabac_init_idc // should be 0 for I_SLICE
+// [7] reserved
+// [6] cabac_en
+// [5:0] slice_quant
+#define VLC_SLICE_QP ((0x0060 << 2) + 0xfe067400)
+// For save mvd[12:0] {mvd_y[6:0], mvd_x[5:0]}
+#define HENC_TOP_INFO_2 ((0x0061 << 2) + 0xfe067400)
+#define HENC_LEFT_INFO_2 ((0x0062 << 2) + 0xfe067400)
+#define HENC_TOP_INFO_3 ((0x0063 << 2) + 0xfe067400)
+#define HENC_LEFT_INFO_3 ((0x0064 << 2) + 0xfe067400)
+//
+// Closing file: vlc_regs.h
+//
+//------------------------------------------------------------------------------
+// -----------------------------------------------
+// `define DOS_HCODEC_IQIDCT_CBUS_BASE 8'h0e
+// -----------------------------------------------
+//------------------------------------------------------------------------------
+//------------------------------------------------------------------------------
+// QDCT module level register offset
+//------------------------------------------------------------------------------
+// `define DOS_HCODEC_QDCT_CBUS_BASE 8'h0f
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe067c00
+// -----------------------------------------------
+//
+// Reading file: qdct_regs.h
+//
+//========================================================================
+// QDCT module level register offset
+//========================================================================
+// -----------------------------------------------
+// `define DOS_HCODEC_QDCT_CBUS_BASE 8'h0f
+// -----------------------------------------------
+// bit[31:28] - mb_info_state
+#define QDCT_STATUS_CTRL ((0x0000 << 2) + 0xfe067c00)
+// bit[18] - enable_free_clk_sad_top
+// bit[17] - enable_free_clk_ie_top
+// bit[16] - enable_free_clk_ie_sub
+// bit[15] - enable_free_clk_mc_out
+// bit[14] - enable_free_clk_i_pred_top
+// bit[13] - enable_free_clk_idct_top
+// bit[12] - enable_free_clk_iq_top
+// bit[11] - enable_free_clk_q_top
+// bit[10] - enable_free_clk_dc_buff_8
+// bit[9] - enable_free_clk_dct_top
+// bit[8] - enable_free_clk_mb_info
+// bit[7] - enable_free_clk_mb_buff
+// bit[6] - enable_free_clk_reg
+// bit[5] - ignore_1_include_2nd_half_c
+// bit[4] - ignore_1_include_2nd_half
+// bit[3] - ignore_t_p8x8
+// bit[2] - not_ignore_dc
+// bit[1] - ignore_small_lac_intra
+// bit[0] - disable_fast_zero_block
+#define QDCT_CONFIG ((0x0001 << 2) + 0xfe067c00)
+// bit[31] - ignore_lac_coeff_en
+// bit[30:26] - ignore_lac_coeff_else
+// bit[25:21] - ignore_lac_coeff_2
+// bit[20:16] - ignore_lac_coeff_1
+// bit[15] - ignore_cac_coeff_en
+// bit[14:10] - ignore_cac_coeff_else
+// bit[9:5] - ignore_cac_coeff_2
+// bit[4:0] - ignore_cac_coeff_1
+#define IGNORE_CONFIG ((0x0002 << 2) + 0xfe067c00)
+// bit[31] - ignore_t_lac_coeff_en
+// bit[30:26] - ignore_t_lac_coeff_else
+// bit[25:21] - ignore_t_lac_coeff_2
+// bit[20:16] - ignore_t_lac_coeff_1
+// bit[15] - ignore_cdc_coeff_en
+// bit[14] - ignore_t_lac_coeff_else_le_3
+// bit[13] - ignore_t_lac_coeff_else_le_4
+// bit[12] - ignore_cdc_only_when_empty_cac_inter
+// bit[11] - ignore_cdc_only_when_one_empty_inter
+// bit[10:9] - ignore_cdc_range_max_inter // 0-0, 1-1, 2,-2, 3-3
+// bit[8:7] - ignore_cdc_abs_max_inter // 0-1, 1-2, 2,-3, 3-4
+// bit[6] - reserved
+// bit[5] - ignore_cdc_only_when_empty_cac_intra
+// bit[4] - ignore_cdc_only_when_one_empty_intra
+// bit[3:2] - ignore_cdc_range_max_intra // 0-0, 1-1, 2,-2, 3-3
+// bit[1:0] - ignore_cdc_abs_max_intra // 0-1, 1-2, 2,-3, 3-4
+#define IGNORE_CONFIG_2 ((0x0003 << 2) + 0xfe067c00)
+// --------------------------------------------
+// MB DATA DDR Interface
+// --------------------------------------------
+#define QDCT_MB_START_PTR ((0x0010 << 2) + 0xfe067c00)
+#define QDCT_MB_END_PTR ((0x0011 << 2) + 0xfe067c00)
+#define QDCT_MB_WR_PTR ((0x0012 << 2) + 0xfe067c00)
+#define QDCT_MB_RD_PTR ((0x0013 << 2) + 0xfe067c00)
+#define QDCT_MB_LEVEL ((0x0014 << 2) + 0xfe067c00)
+// bit [31] disable_mbxy_ie_save
+// bit [30] no_wait_after_q_cdc
+// bit [29] ie_start_int_enable
+// bit [28] ignore_t_p8x8
+// bit [27] zero_mc_out_null_non_skipped_mb
+// bit [26] no_mc_out_null_non_skipped_mb
+// bit [25] mc_out_even_skipped_mb
+// bit [24] mc_out_wait_cbp_ready
+// bit [23] mc_out_wait_mb_type_ready
+// bit [22] i_pred_int_enable
+// bit [21] intra_sat8_enable
+// bit [20] ie_sub_enable
+// bit [19] i_pred_enable
+// bit [18] iq_enable
+// bit [17] idct_enable
+// bit [16] no_zero_coeff_mb
+// bit [15] add_zero_coeff_block
+// bit [14] mb_pause_enable
+// bit [13] q_enable
+// bit [12] dct_enable
+// bit [11] ignore_magic_word
+// bit [10] mb_info_en
+// bit [9] mb_info_soft_reset
+// bit [8] mb_always_ready Set to 1 to ignore mb_level blocking DDR read
+// bit [7] mb_ready_for_transfer (Read Only)
+// bit [6] data_ready_for_transfer (Read Only)
+// bits [5:3] mb_endian Set MB Endian inside DDR memory
+// bit [2] mb_read_busy Read Only - indicate DDR read busy
+// bit [1] mb_read_en Set to 1 to enable reading data from DDR memory
+// bit [0] mb_soft_reset Soft reset
+#define QDCT_MB_CONTROL ((0x0015 << 2) + 0xfe067c00)
+// bit 31 transfer_length 0 - 32x64 Bits per request, 1 - 16x64 Bits per request // default : 0
+// bit 30 A_urgent // default : 0
+// bit 29:24 A_brst_num // default : 0x3f
+// bit 23 reserved
+// bit 22 read_till_zero
+// bit 21:16 A_id // default : 0x21
+// bit 15:0 mb_level_hold // default : 0
+#define QDCT_MB_MEM_CTL ((0x0016 << 2) + 0xfe067c00)
+// bit [31:24] reserved
+// bit [23:16] vb_buff_level -- Read only
+// bit [15:8] vb_buff_wr_point -- RW
+// bit [7:0] vb_buff_rd_point -- RW
+#define QDCT_MB_BUFF ((0x0017 << 2) + 0xfe067c00)
+// bit [31:0] mb infor data begin magic word - default : 0xa55aaa55
+#define QDCT_MB_MAGIC_WORD ((0x0018 << 2) + 0xfe067c00)
+// Read Only Register
+// bit[19] dct_ready_1
+// bit[18] dct_ready_0
+// bit[17] dct_rd_idx
+// bit[16] dct_wr_idx
+// bit[15] dct_srdy
+// bit[14] dct_rrdy
+// bit[13] Reserved
+// bit[12:8] dct_block_number
+// bit[7:4] dct_rw_addr
+// bit[3:0] dct_status
+#define QDCT_DCT_STATUS ((0x0019 << 2) + 0xfe067c00)
+// bit[24:23] vlc_quant_count
+// bit[22:16] vlc_delta_quant_data
+// bit[15:10] vlc_quant_data
+// bit[9:4] vlc_prev_quant_data
+// bit[3:0] q_status
+#define QDCT_Q_STATUS ((0x001a << 2) + 0xfe067c00)
+// bit[31:3] Reserved
+// bit[2:0] picture_type
+#define QDCT_PIC_INFO ((0x001b << 2) + 0xfe067c00)
+// bit[31:28] Reserved
+// bit[27:22] I_pic_quant_c
+// bit[21:16] I_pic_quant
+// bit[15] reserved
+// bit[14:12] quant_rem_c
+// bit[11:8] quant_per_c
+// bit[7] reserved
+// bit[6:4] quant_rem
+// bit[3:0] quant_per
+#define QDCT_Q_QUANT_I ((0x001c << 2) + 0xfe067c00)
+// bit[31:28] Reserved
+// bit[27:22] P_pic_quant_c
+// bit[21:16] P_pic_quant
+// bit[15] reserved
+// bit[14:12] quant_rem_c
+// bit[11:8] quant_per_c
+// bit[7] reserved
+// bit[6:4] quant_rem
+// bit[3:0] quant_per
+#define QDCT_Q_QUANT_P ((0x001d << 2) + 0xfe067c00)
+// bit[31] mb_info_pause
+// bit[30:16] pause_mby
+// bit[15:0] pause_mbx
+#define QDCT_MB_PAUSE_CTL ((0x001e << 2) + 0xfe067c00)
+// bit[31] top_control_ready_i_pred
+// bit[30:28]top_dma_status
+// bit[27] top_control_ready_ie
+// bit[26:24]Reserved
+// bit[23] ul_mb
+// bit[22] right_mb
+// bit[21] top_mb
+// bit[20] left_mb
+// bit[19:8] mb_x
+// bit[7:6] i_pred_ref_idx_L
+// bit[5:4] i_pred_ref_idx_UL
+// bit[3:2] i_pred_ref_idx_U
+// bit[1:0] i_pred_ref_idx_UR
+#define QDCT_TOP_CONTROL ((0x001f << 2) + 0xfe067c00)
+// bit[31:0] top_base_addr - DDR Memory start address for save top Pixel
+#define QDCT_TOP_BASE_MEM ((0x0020 << 2) + 0xfe067c00)
+// bit 15:13 Reserved
+// bit 12 A_urgent // default : 0
+// bit 11:6 A_brst_num // default : 0x3f
+// bit 5:0 A_id // default : 0x22
+#define QDCT_TOP_MEM_CTL ((0x0021 << 2) + 0xfe067c00)
+// bit [11:0] top_wrrsp_count
+#define QDCT_TOP_WRRSP ((0x0022 << 2) + 0xfe067c00)
+// Bit[3:0] qdct_dbg_idx
+#define QDCT_DBG_IDX ((0x0023 << 2) + 0xfe067c00)
+// Read Only
+#define QDCT_DBG_READ ((0x0024 << 2) + 0xfe067c00)
+// [19:18] RW jdct_inflow_ctrl. JPEG DCT input flow control. Default 0.
+// 0=No halt;
+// 1=DCT halts request at end of each 8x8 block;
+// 2=DCT halts request at end of each MCU.
+// [17:16] RW jpeg_coeff_last_sel. Default 0.
+// Select at which point to finish processing, give update to AmRISC so it can control the next step.
+// 0=Mark last coeff at the end of an 8x8 block;
+// 1=Mark at the end of an MCU;
+// 2=Mark at the end of a scan.
+// [ 15] RW jpeg_quant_sel_comp2. 0=Comp2 select Quantization table 0; 1=Select table 1. Default 0.
+// [ 14] RW jpeg_v_factor_comp2. Component 2's vertical sampling factor. Default 0.
+// [ 13] RW jpeg_h_factor_comp2. Component 2's horizontal sampling factor. Default 0.
+// [ 12] RW jpeg_comp2_en. Set 1 if the scan will include component 2 (Cr). Default 0.
+// [ 11] RW jpeg_quant_sel_comp1. 0=Comp1 select Quantization table 0; 1=Select table 1. Default 0.
+// [ 10] RW jpeg_v_factor_comp1. Component 1's vertical sampling factor. Default 0.
+// [ 9] RW jpeg_h_factor_comp1. Component 1's horizontal sampling factor. Default 0.
+// [ 8] RW jpeg_comp1_en. Set 1 if the scan will include component 1 (Cb). Default 0.
+// [ 7] RW jpeg_quant_sel_comp0. 0=Comp0 select Quantization table 0; 1=Select table 1. Default 0.
+// [ 6] RW jpeg_v_factor_comp0. Component 0's vertical sampling factor. Default 0.
+// [ 5] RW jpeg_h_factor_comp0. Component 0's horizontal sampling factor. Default 0.
+// [ 4] RW jpeg_comp0_en. Set 1 if the scan will include component 0 (Y). Default 0.
+// [ 3: 1] RW jdct_intr_sel. JPEG DCT interrupt select. Default 0.
+// 0=Disable intr;
+// 1=Intr at end of each 8x8 block of DCT input;
+// 2=Intr at end of each MCU of DCT input;
+// 3=Intr at end of a scan of DCT input;
+// 4=Intr at end of each 8x8 block of DCT output;
+// 5=Intr at end of each MCU of DCT output;
+// 6=Intr at end of a scan of DCT output.
+// [ 0] RW jpeg_en. 0=Disable JPEG QDCT; 1=Enable JPEG QDCT. Default 0.
+#define QDCT_JPEG_CTRL ((0x0025 << 2) + 0xfe067c00)
+// [29:16] RW jpeg_x_end. Picture X end. Default 0.
+// [13: 0] RW jpeg_x_start. Picture X start. Default 0.
+#define QDCT_JPEG_X_START_END ((0x0026 << 2) + 0xfe067c00)
+// [29:16] RW jpeg_y_end. Picture Y end. Default 0.
+// [13: 0] RW jpeg_y_start. Picture Y start. Default 0.
+#define QDCT_JPEG_Y_START_END ((0x0027 << 2) + 0xfe067c00)
+// [ 8] RW JPEG QUANT table access mode. 0=Write; 1=Read. Default 1.
+// [ 5: 0] RW JPEG QUANT table addr. Default 0.
+#define QDCT_JPEG_QUANT_ADDR ((0x0028 << 2) + 0xfe067c00)
+// [31: 0] RW JPEG QUANT table data.
+#define QDCT_JPEG_QUANT_DATA ((0x0029 << 2) + 0xfe067c00)
+// [ 1] W resume_jdct.
+// Write 1 to this bit will resume JPEG input engine when previously
+// it is halted by QDCT_JPEG_CTRL.jdct_inflow_ctrl.
+// [ 0] W jpeg_sof.
+// Write 1 to this bit will start JPEG input engine.
+#define QDCT_JPEG_SOF_RESUME ((0x002a << 2) + 0xfe067c00)
+// [31:30] R dct_st. jdct_ctrl state. 0=IDLE; 1=WAIT; 2=DCT_REQ.
+// [29:28] R mfdin_comp. Current component at pixel request to MFDIN.
+// [27:14] R mfdin_y. Current Y at pixel request to MFDIN.
+// [13: 0] R mfdin_x. Current X at pixel request to MFDIN.
+#define QDCT_JPEG_DCT_STATUS0 ((0x002b << 2) + 0xfe067c00)
+// [15:12] R JPEG Quant read MEM select.
+// [11: 8] R JPEG DCT2 write MEM select.
+// [ 7: 4] R JPEG DCT2 read MEM select.
+// [ 3: 0] R JPEG DCT1 write MEM select.
+#define QDCT_JPEG_DCT_STATUS1 ((0x002c << 2) + 0xfe067c00)
+// [28:16] RW jdct_coeff1. Default 13'h1D90; // 7568 = 4096 * sqrt(2) * (cos(Pi/8) + sin(Pi/8)) // 7569
+// [12: 0] RW jdct_coeff0. Default 13'h16A1; // 5793 = 4096 * sqrt(2)
+#define QDCT_JPEG_DCT_COEFF01 ((0x002d << 2) + 0xfe067c00)
+// [28:16] RW jdct_coeff3. Default 13'h0C3F; // 3135 = 4096 * sqrt(2) * (cos(Pi/8) - sin(Pi/8))
+// [12: 0] RW jdct_coeff2. Default 13'h08A9; // 2217 = 4096 * sqrt(2) * sin(Pi/8) // 2215
+#define QDCT_JPEG_DCT_COEFF23 ((0x002e << 2) + 0xfe067c00)
+// [28:16] RW jdct_coeff5. Default 13'h046A; // 1130 = 4096 * (cos(3Pi/16) - sin(3Pi/16))
+// [12: 0] RW jdct_coeff4. Default 13'h1631; // 5681 = 4096 * (cos(3Pi/16) + sin(3Pi/16)) // 5682
+#define QDCT_JPEG_DCT_COEFF45 ((0x002f << 2) + 0xfe067c00)
+// [28:16] RW jdct_coeff7. Default 13'h0C92; // 3218 = 4096 * (cos(Pi/16) - sin(Pi/16))
+// [12: 0] RW jdct_coeff6. Default 13'h12D0; // 4816 = 4096 * (cos(Pi/16) + sin(Pi/16))
+#define QDCT_JPEG_DCT_COEFF67 ((0x0030 << 2) + 0xfe067c00)
+// [28:16] RW jdct_coeff9. Default 13'h0FB1; // 4017 = 4096 * cos(Pi/16)
+// [12: 0] RW jdct_coeff8. Default 13'h0D4E; // 3406 = 4096 * cos(3Pi/16)
+#define QDCT_JPEG_DCT_COEFF89 ((0x0031 << 2) + 0xfe067c00)
+#define QDCT_I_PRED_REF_WR_IDX ((0x0032 << 2) + 0xfe067c00)
+#define QDCT_I_PRED_REF_WR_DATA ((0x0033 << 2) + 0xfe067c00)
+// bit[29] mb_info_latch_no_I16_pred_mode
+// bit[28] ie_dma_mbxy_use_i_pred
+// bit[27] ie_dma_read_write_use_ip_idx
+// bit[26] ie_start_use_top_dma_count
+// bit[25] i_pred_top_dma_rd_mbbot
+// bit[24] i_pred_top_dma_wr_disable
+// bit[23] i_pred_mix
+// bit[22] me_ab_rd_when_intra_in_p
+// bit[21] force_mb_skip_run_when_intra
+// bit[20] mc_out_mixed_type
+// bit[19] ie_start_when_quant_not_full
+// bit[18] mb_info_state_mix
+// bit[17] mb_type_use_mix_result
+// bit[16] me_cb_ie_read_enable
+// bit[15] ie_cur_data_from_me
+// bit[14] rem_per_use_table
+// bit[13] q_latch_int_enable
+// bit[12] q_use_table
+// bit[11] q_start_wait
+// bit[10] LUMA_16_LEFT_use_cur
+// bit[9] DC_16_LEFT_SUM_use_cur
+// bit[8] c_ref_ie_sel_cur
+// bit[7] c_ipred_perfect_mode
+// bit[6] ref_ie_ul_sel 0-old, 1-use next_set
+// bit[5] mb_type_use_ie_result
+// bit[4] detect_I16_from_I4
+// bit[3] ie_not_wait_ref_busy
+// bit[2] ie_I16_enable
+// bit[1:0] ie_done_sel (0, 1, 2, -1)
+#define QDCT_ADV_CONFIG ((0x0034 << 2) + 0xfe067c00)
+// bit [31:16] I16x16_weight
+// bit [15:0] I4x4_weight
+#define IE_WEIGHT ((0x0035 << 2) + 0xfe067c00)
+// bit [31] reserved
+// bit [30] q_I16MB
+// bit [29] reserved
+// bit [28] reserved
+// bit [27:23] quant_table_addr I4MB:[0,7], I16MB:[8:15], INTER:[16:23], Reserved:[24:31]
+// bit [22] quant_table_addr_update(when notupdate_rem_per) (read is arb_result : q_intra)
+// bit [21:19] quant_rem_c
+// bit [18:16] quant_rem_y
+// bit [15:12] quant_per_c
+// bit [11:8] quant_per_y
+// bit [7:2] quant
+// bit [1] update_rem_per
+// bit [0] clear_wait_status
+#define Q_QUANT_CONTROL ((0x0036 << 2) + 0xfe067c00)
+#define MBBOT_EVEN_ADDR ((0x0037 << 2) + 0xfe067c00)
+#define MBBOT_ODD_ADDR ((0x0038 << 2) + 0xfe067c00)
+// bit [29:24] quant_table_data_3
+// bit [21:16] quant_table_data_2
+// bit [13:8] quant_table_data_1
+// bit [5:0] quant_table_data_0
+#define QUANT_TABLE_DATA ((0x0039 << 2) + 0xfe067c00)
+// bit [31:16] ie_sad_offset_I16
+// bit [15:0] ie_sad_offset_I4
+#define SAD_CONTROL_0 ((0x003a << 2) + 0xfe067c00)
+// bit [31] sad_soft_reset
+// bit [30:27] reserved
+// bit [26:24] ie_sad_shift_I16
+// bit [22:20] ie_sad_shift_I4
+// bit [18:16] me_sad_shift_INTER
+// bit [15:0] me_sad_offset_INTER
+#define SAD_CONTROL_1 ((0x003b << 2) + 0xfe067c00)
+// bit [31] vlc_quant_rd_ptr
+// bit [30] vlc_quant_rd_ptr_update
+// bit [29] vlc_quant_wr_ptr
+// bit [28] vlc_quant_wr_ptr_update
+// bit [27:26] reserved
+// bit [25:19] vlc_delta_quant_1
+// bit [18:13] vlc_quant_1
+// bit [12:6] vlc_delta_quant_0
+// bit [5:0] vlc_quant_0
+#define QDCT_VLC_QUANT_CTL_0 ((0x003c << 2) + 0xfe067c00)
+// bit [31:30] me_sad_rd_idx
+// bit [29] me_sad_rd_idx_update
+// bit [28:27] me_sad_wr_idx
+// bit [26] me_sad_wr_idx_update
+// bit [25:24] ie_sad_rd_idx
+// bit [23] ie_sad_rd_idx_update
+// bit [22:21] ie_sad_wr_idx
+// bit [20] ie_sad_wr_idx_update
+// bit [19:12] Reserved
+// bit [11:6] vlc_max_delta_q_neg
+// bit [5:0] vlc_max_delta_q_pos
+#define QDCT_VLC_QUANT_CTL_1 ((0x003d << 2) + 0xfe067c00)
+// bit[4] jdct_int
+// bit[3] quant_latch
+// bit[2] me_done
+// bit[1] ie_start
+// bit[0] i_pred_start
+#define QDCT_INT_STATUS ((0x003e << 2) + 0xfe067c00)
+// bit[3] mix_i_pred_wait_left_en
+// bit[2:0] mc_pending_mb_count
+#define QDCT_MIX_I_PRED_STATUS ((0x003f << 2) + 0xfe067c00)
+// IE/ME share same cbus_base as QDCT
+//
+// bit[31] active_ur_block
+// bit[30] active_ul_block
+// bit[21] disable_HENC_V_PRED_16
+// bit[20] disable_HENC_H_PRED_16
+// bit[19] disable_HENC_DC_PRED_16
+// bit[18] disable_HENC_HENC_HOR_UP_PRED
+// bit[17] disable_HENC_VERT_LEFT_PRED
+// bit[16] disable_HENC_HENC_HOR_DOWN_PRED
+// bit[15] disable_HENC_VERT_RIGHT_PRED
+// bit[14] disable_HENC_DIAG_DOWN_RIGHT_PRED
+// bit[13] disable_HENC_DIAG_DOWN_LEFT_PRED
+// bit[12] disable_HENC_DC_PRED
+// bit[11] disable_HENC_HOR_PRED
+// bit[10] disable_HENC_VERT_PRED
+// bit[9] ie_c_wait_ie_pause
+// bit[8:4] max_ie_result_buff_count
+// bit[3] ie_wait_for_ie_result // use for (max_ie_result_buff_count == 0) to wait every block
+// bit[2] reserved
+// bit[1] ie_enable
+// bit[0] ie_soft_reset
+#define IE_CONTROL ((0x0040 << 2) + 0xfe067c00)
+// bit[31:12] Reserved
+// bit[11:0] mb_y
+#define IE_MB_POSITION ((0x0041 << 2) + 0xfe067c00)
+// bit[31:16] me_skip_run
+// bit[15:8] reserved
+// bit [7:4] me_b8_mode
+// bit [3:0] ie_me_mb_type
+#define IE_ME_MB_INFO ((0x0042 << 2) + 0xfe067c00)
+// bit[3] ie_result_buff_enable
+// bit[2] ie_result_buff_soft_reset
+// bit[1] sad_enable
+// bit[0] ie_sad_soft_reset
+#define SAD_CONTROL ((0x0043 << 2) + 0xfe067c00)
+// bit[31:16] - ie_result_buff_count - read only
+// bit[14:12] -current_ie_result (pred_mode) - read only
+// bit[11] top_control_data_buff_wr_ptr - rd/wr
+// bit[10] top_control_data_buff_rd_ptr - rd/wr
+// bit[9:5] ie_result_buff_wr_ptr - rd/wr
+// bit[4:0] ie_result_buff_rd_ptr - rd/wr
+#define IE_RESULT_BUFFER ((0x0044 << 2) + 0xfe067c00)
+// bit[63:0] ie_i4_pred_mode
+#define IE_I4_PRED_MODE_HI ((0x0045 << 2) + 0xfe067c00)
+#define IE_I4_PRED_MODE_LO ((0x0046 << 2) + 0xfe067c00)
+// bit [31:9] reserved
+// bit [8:4] i_pred_block_number
+// bit [3:0] ie_c_pred_mode
+#define IE_C_PRED_MODE ((0x0047 << 2) + 0xfe067c00)
+// 31:16 - Left, 0-select ie_pixel, 1-select mc_data_out
+// 15:0 - Top, 0-select ie_pixel, 1-select mc_data_out
+#define IE_CUR_REF_SEL ((0x0048 << 2) + 0xfe067c00)
+// bit[31] enable_f_skip_1_step_3
+// bit[30] enable_f_skip_1_step_2
+// bit[29] enable_f_skip_1_step_1
+// bit[28] step_3_enable
+// bit[27] step_2_sub_pixel
+// bit[26] always_f_skip_step_3
+// bit[25] always_f_skip_step_2
+// bit[24] always_f_skip_step_1
+// bit[23] half_pixel_only
+// bit[22:13] reserved
+// bit[12] adv_mv_enable
+// bit[11] sad_short_valid
+// bit[10:9] mv_flexable_ctl 00:0x40, 01:0x80, 10:0xc0, 11 : 0x100
+// bit[8] no_md_ab_rd
+// bit[7] use_dct_state
+// bit[6] enable_free_clk_me_ctl
+// bit[5] enable_free_clk_me_ab
+// bit[4] enable_free_clk_me_cb
+// bit[3] reserved
+// bit[2] me_done_int_enable
+// bit[1] me_enable
+// bit[0] me_soft_reset
+#define ME_CONTROL ((0x0049 << 2) + 0xfe067c00)
+// bit[31:28] Reserved
+// bit[27:16] me_start_mby
+// bit[15:12] Reserved
+// bit[11:0] me_start_mbx
+#define ME_START_POSITION ((0x004a << 2) + 0xfe067c00)
+// bit [31:28] me_status - Read only
+// bit [27:24] me_cb_status // current buffer
+// bit [23:20] me_ab_status // anc buffer
+// bit [19] Reserved
+// bit [18:16] me_ab_wr_ptr // read only
+// bit [15:4] me_last_mbx
+// bit [3:1] me_ab_rd_ptr // read only
+// bit [0] me_action
+#define ME_STATUS ((0x004b << 2) + 0xfe067c00)
+// all Read-only
+// bit [31:28] Reserved
+// bit [27:16] me_ab_mbx
+// bit [15:14] me_cb_wr_ptr
+// bit [13:12] me_cb_rd_ptr
+// bit [11:0] me_cb_mbx
+#define ME_DEBUG ((0x004c << 2) + 0xfe067c00)
+// bit[29:24] step_3_skip_line
+// bit[23:18] step_2_skip_line
+// bit[17:12] step_1_skip_line
+// bit[11:6] step_0_skip_line
+// bit[5:0] read_skip_line
+#define ME_SKIP_LINE ((0x004d << 2) + 0xfe067c00)
+// bit 15:13 Reserved
+// bit 12 A_urgent // default : 0
+// bit 11:6 A_brst_num // default : 0x3f
+// bit 5:0 A_id // default : 0x23
+#define ME_AB_MEM_CTL ((0x004e << 2) + 0xfe067c00)
+// bit[31:24] anc_pic_canvas
+// bit[23:12] max_me_mby_num
+// bit[11:0] max_me_mbx_num
+#define ME_PIC_INFO ((0x004f << 2) + 0xfe067c00)
+// bit [23:12] me_sad_enough_1
+// bit [11:0] me_sad_enough_0
+#define ME_SAD_ENOUGH_01 ((0x0050 << 2) + 0xfe067c00)
+// bit [25:12] adv_mv_8x8_enough
+// bit [11:0] me_sad_enough_2
+#define ME_SAD_ENOUGH_23 ((0x0051 << 2) + 0xfe067c00)
+// bit [21:10] me_step0_big_sad
+// bit [9:5] me_step0_close_mv_y
+// bit [4:0] me_step0_close_mv_x
+#define ME_STEP0_CLOSE_MV ((0x0052 << 2) + 0xfe067c00)
+// bit[31:24] force_skip_sad_3
+// bit[23:16] force_skip_sad_2
+// bit[15:08] force_skip_sad_1
+// bit[07:00] force_skip_sad_0
+#define ME_F_SKIP_SAD ((0x0053 << 2) + 0xfe067c00)
+// bit[31:24] force_skip_weight_3
+// bit[23:16] force_skip_weight_2
+// bit[15:08] force_skip_weight_1
+// bit[07:00] force_skip_weight_0
+#define ME_F_SKIP_WEIGHT ((0x0054 << 2) + 0xfe067c00)
+// Merge when (
+// (flex & me_merge_flex_en) |
+// (big_sad & me_merge_sad_en)|
+// ((~me_merge_flex_en)&(~me_merge_sad_en))
+// ) &
+// ( small_mv_diff |(~me_merge_small_mv_en))
+// & (me_merge_flex_en | me_merge_sad_en | me_merge_small_mv_en)
+// bit[31] me_merge_mv_en_16
+// bit[30] me_merge_small_mv_en_16
+// bit[29] me_merge_flex_en_16
+// bit[28] me_merge_sad_en_16
+// bit[27] me_merge_mv_en_8
+// bit[26] me_merge_small_mv_en_8
+// bit[25] me_merge_flex_en_8
+// bit[24] me_merge_sad_en_8
+// bit[23:18] me_merge_mv_diff_16
+// bit[17:12] me_merge_mv_diff_8
+// bit[11:0] me_merge_min_sad
+#define ME_MV_MERGE_CTL ((0x0055 << 2) + 0xfe067c00)
+// bit[31:24] mv_step_weight_1
+// bit[23:16] mv_pre_weight_1
+// bit [15:0] mv_step_weight_0
+// bit[7:0] mv_pre_weight_0
+#define ME_MV_WEIGHT_01 ((0x0056 << 2) + 0xfe067c00)
+// bit[31:24] mv_step_weight_3 (mv_step_weight_1_2nd)
+// bit[23:16] mv_pre_weight_3 (mv_pre_weight_1_2nd)
+// bit[15:8] mv_step_weight_2
+// bit[7:0] mv_pre_weight_2
+#define ME_MV_WEIGHT_23 ((0x0057 << 2) + 0xfe067c00)
+// bit[31:24] me_sad_range_inc_3
+// bit[23:16] me_sad_range_inc_2
+// bit[15:8] me_sad_range_inc_1
+// bit[7:0] me_sad_range_inc_0
+#define ME_SAD_RANGE_INC ((0x0058 << 2) + 0xfe067c00)
+// bit[31:19] reserved
+// bit[18] sub_relative_any_1_en
+// bit[17] sub_relative_any_2_en
+// bit[16] sub_relative_any_3_en
+// bit[15] sub_relative_any_4_en
+// bit[14] sub_relative_any_h_en
+// bit[13] sub_make_non_flex_fix
+// bit[12] sub_make_big_non_flex_fix
+// bit[11:8] sub_normal_mv_diff_16
+// bit[7:4] sub_normal_mv_diff_8
+// bit[3:2] Reserved
+// bit[1] sub_merge_enable_16
+// bit[0] sub_merge_enable_8
+#define ME_SUB_MERGE_CTL ((0x0059 << 2) + 0xfe067c00)
+// bit[31:28] sub_ref_mv_diff_near
+// bit[27:24] sub_ref_mv_diff_near_flex
+// bit[23:20] sub_ref_mv_diff
+// bit[19:16] sub_ref_mv_diff_flex
+// bit[15:8] sub_ref_mv_near_weight
+// bit[7:0] sub_ref_mv_weight
+#define ME_SUB_REF_MV_CTL ((0x005a << 2) + 0xfe067c00)
+// bit[31:24] sub_weight_max_sad
+// bit[23:16] sub_any_range_sad
+// bit[15:8] sub_any_min_sad
+// bit[7:0] sub_any_max_sad
+#define ME_SUB_ANY_WEIGHT_SAD ((0x005b << 2) + 0xfe067c00)
+// bit[31:24] sub_fix_sad
+// bit[23:16] sub_fix_diff_sad
+// bit[15:8] sub_sad_flex_adj
+// bit[7:0] sub_big_non_flex_fix_sad
+#define ME_SUB_FIX_SAD ((0x005c << 2) + 0xfe067c00)
+// bit[31:24] sub_fix_min_sad
+// bit[23:16] sub_fix_min_diff_sad
+// bit[15:8] sub_fix_min_sad_2
+// bit[7:0] sub_fix_min_diff_sad_2
+#define ME_SUB_FIX_MIN_SAD ((0x005d << 2) + 0xfe067c00)
+// bit[31:24] sub_snap_to_ref_max_sad
+// bit[23] sub_snap_to_ref_non_flex
+// bit[22:16] sub_snap_to_ref_mv_diff
+// bit[15:4] sub_glitch_mv_sad
+// bit[3:0] sub_glitch_mv_diff
+#define ME_SUB_SNAP_GLITCH ((0x005e << 2) + 0xfe067c00)
+// bit[31:20] sad_act_limit
+// bit[19:8] s_a_any_sad
+// bit[7] Reserved
+// bit[6:5] sub_merge_method
+// bit[4] use_sub_act_result
+// bit[3] s_a_rnd
+// bit[2] Reserved
+// bit[1] sub_act_en_16
+// bit[0] sub_act_en
+#define ME_SUB_ACT_CTL ((0x005f << 2) + 0xfe067c00)
+// bit[31:16] reserved
+// bit[15:0] me_weight
+#define ME_WEIGHT ((0x0060 << 2) + 0xfe067c00)
+// bit[31] ready_update
+// bit[30] data_update
+// bit[29:28] reserved
+// bit[27:22] me_quant_0
+// bit[21] ie_sad_ready_0
+// bit[20:18] Reserved
+// bit[17:16] me_sad_mv_type_0
+// bit[15:0] me_sad_0
+#define ME_SAD_0 ((0x0061 << 2) + 0xfe067c00)
+// bit[31] ready_update
+// bit[30] data_update
+// bit[29:28] reserved
+// bit[27:22] me_quant_1
+// bit[21] me_sad_ready_1
+// bit[20:18] Reserved
+// bit[17:16] me_sad_mv_type_1
+// bit[15:0] me_sad_1
+#define ME_SAD_1 ((0x0062 << 2) + 0xfe067c00)
+// bit[31] ready_update
+// bit[30] data_update
+// bit[29:28] reserved
+// bit[27:22] me_quant_2
+// bit[21] me_sad_ready_2
+// bit[20:18] Reserved
+// bit[17:16] me_sad_mv_type_2
+// bit[15:0] me_sad_2
+#define ME_SAD_2 ((0x0063 << 2) + 0xfe067c00)
+// bit[31] ready_update
+// bit[30] data_update
+// bit[29:28] reserved
+// bit[27:22] me_quant_3
+// bit[21] me_sad_ready_3
+// bit[20:18] Reserved
+// bit[17:16] me_sad_mv_type_3
+// bit[15:0] me_sad_3
+#define ME_SAD_3 ((0x0064 << 2) + 0xfe067c00)
+// bit[31] ready_update
+// bit[30] data_update
+// bit[29:28] reserved
+// bit[27:22] ie_quant_0
+// bit[21] ie_sad_ready_0
+// bit[20] I4/I16 (0-I4MB, 1-I16MB)
+// bit[19:0] ie_sad_0
+#define IE_SAD_0 ((0x0065 << 2) + 0xfe067c00)
+// bit[31] ready_update
+// bit[30] data_update
+// bit[29:28] reserved
+// bit[27:22] ie_quant_1
+// bit[21] ie_sad_ready_1
+// bit[20] I4/I16 (0-I4MB, 1-I16MB)
+// bit[19:0] ie_sad_1
+#define IE_SAD_1 ((0x0066 << 2) + 0xfe067c00)
+// bit[31] ready_update
+// bit[30] data_update
+// bit[29:28] reserved
+// bit[27:22] ie_quant_2
+// bit[21] ie_sad_ready_2
+// bit[20] I4/I16 (0-I4MB, 1-I16MB)
+// bit[19:0] ie_sad_2
+#define IE_SAD_2 ((0x0067 << 2) + 0xfe067c00)
+// bit[31] ready_update
+// bit[30] data_update
+// bit[29:28] reserved
+// bit[27:22] ie_quant_3
+// bit[21] ie_sad_ready_3
+// bit[20] I4/I16 (0-I4MB, 1-I16MB)
+// bit[19:0] ie_sad_3
+#define IE_SAD_3 ((0x0068 << 2) + 0xfe067c00)
+// bit[31] enable_large_diff_16x8
+// bit[30] enable_large_diff_8x16
+// bit[29:16] adv_mv_8x8_weight
+// bit[15:14] reserved
+// bit[13:0] adv_mv_4x4x4_weight
+#define ADV_MV_CTL0 ((0x0069 << 2) + 0xfe067c00)
+// bit[31:16] adv_mv_16x16_weight
+// bit[15] enable_large_diff_16x16
+// bit[14:0] adv_mv_16_8_weight
+#define ADV_MV_CTL1 ((0x006a << 2) + 0xfe067c00)
+#define ADV_MV_CTL2 ((0x006b << 2) + 0xfe067c00)
+// bit[31] v3_skip_enable
+// bit[30] v3_step_1_weight_enable // for step1, will only use pre_weight for block0, only step_weight for block 1,2,3
+// bit[29] v3_l2_skip_only_use_l2_sad // set to 1 may allow l1 maybe not skip
+// bit[28] v3_mv_sad_weight_enable
+// bit[27] v3_ipred_type_enable
+// bit[25:12] force_skip_sad_1
+// bit[11:0] force_skip_sad_0
+#define V3_SKIP_CONTROL ((0x006c << 2) + 0xfe067c00)
+// bit[18:16] top_ipred_type_count
+// bit[15:14] Reserved
+// bit[13:12] top_ipred_type_rd_idx
+// bit[11:10] top_ipred_type_wr_idx
+// bit[9] left_ipred_type_ready
+// bit[8] top_ipred_type_ready
+// bit[7:6] left_mv_idx
+// bit[5:4] top_mv_idx
+// bit[3] - left_mv_ready
+// bit[2:0] top_mv_ready
+#define V3_TOP_LEFT_CTL ((0x006d << 2) + 0xfe067c00)
+#define V3_TOP_MV ((0x006e << 2) + 0xfe067c00)
+#define V3_LEFT_MV ((0x006f << 2) + 0xfe067c00)
+// bit[31:30] reserved
+// bit[29:16] v3_skip_weight_1
+// bit[15:12] reserved
+// bit[11:0] v3_skip_weight_0
+#define V3_SKIP_WEIGHT ((0x0070 << 2) + 0xfe067c00)
+// bit[31:28] reserved
+// bit[27:16] v3_l1_f_skip_max_sad
+// bit[15:12] reserved
+// bit[11:0] v3_l1_skip_max_sad
+#define V3_L1_SKIP_MAX_SAD ((0x0071 << 2) + 0xfe067c00)
+// bit[31:16] force_skip_sad_2
+// bit[15:0] v3_skip_weight_2
+#define V3_L2_SKIP_WEIGHT ((0x0072 << 2) + 0xfe067c00)
+// bit[21:16] v3_mv_sad_table_addr 0-15 table_step_0
+// bit[11:0] v3_mv_sad
+#define V3_MV_SAD_TABLE ((0x0073 << 2) + 0xfe067c00)
+// [31:16] v3_ie_f_zero_sad_i16
+// [15:0] v3_ie_f_zero_sad_i4
+#define V3_F_ZERO_CTL_0 ((0x0074 << 2) + 0xfe067c00)
+// [25] v3_no_ver_when_top_zero_en
+// [24] v3_no_hor_when_left_zero_en
+// [23:16] v3_max_I16_H_num // 0 means no break
+// [15:0] v3_me_f_zero_sad
+#define V3_F_ZERO_CTL_1 ((0x0075 << 2) + 0xfe067c00)
+#define V3_TOP_INTRA_INFO ((0x0076 << 2) + 0xfe067c00)
+#define V3_LEFT_INTRA_INFO ((0x0077 << 2) + 0xfe067c00)
+// [31:24] C_ipred_weight_H
+// [23:16] C_ipred_weight_V
+// [15:8] I4_ipred_weight_else
+// [7:0] I4_ipred_weight_most
+#define V3_IPRED_TYPE_WEIGHT_0 ((0x0078 << 2) + 0xfe067c00)
+// [31:24] I16_ipred_weight_DC
+// [23:16] I16_ipred_weight_H
+// [15:8] I16_ipred_weight_V
+// [7:0] C_ipred_weight_DC
+#define V3_IPRED_TYPE_WEIGHT_1 ((0x0079 << 2) + 0xfe067c00)
+// [31:16] v3_left_small_max_me_sad
+// [15:0] v3_left_small_max_ie_sad
+#define V3_LEFT_SMALL_MAX_SAD ((0x007a << 2) + 0xfe067c00)
+// (qr==7) & (qp==15) means force zero block
+// [31:26] v4_force_q_r_intra
+// [25:20] v4_force_q_r_inter
+// [19] v4_force_q_y_enable
+// [18:16] v4_force_qr_y
+// [15:12] v4_force_qp_y
+// [11:0] v4_force_skip_sad
+#define V4_FORCE_SKIP_CFG ((0x007b << 2) + 0xfe067c00)
+// v5 Complexity // Y(256 pixel per MB) and C(128 pixel per MB)
+// For every 4x4 block, calculate average and Add abs(pixel-average) together
+// bit[31:16] v5_diff_sum_C
+// bit[15:0] v5_diff_sum_Y
+#define V5_MB_DIFF_SUM ((0x007c << 2) + 0xfe067c00)
+// bit[31:24] v5_small_diff_cnt_C
+// bit[23:16] v5_small_diff_C
+// bit[15:8] v5_small_diff_cnt_Y
+// bit[7:0] v5_small_diff_Y
+#define V5_SMALL_DIFF_CNT ((0x007d << 2) + 0xfe067c00)
+// bit[31:29] Reserved
+// bit[28:24] v5_simple_block_cnt // 0 -15 Y 16-23 C
+// bit[23:20] v5_simple_pixel_cnt
+// bit[19:18] v5_simple_dq_wr_ptr
+// bit[17:16] v5_simple_dq_rd_ptr
+// bit[15:12] v5_simple_dq (Read Only)
+// bit[11:8] v5_simple_me_weight(Read Only)
+// bit[7] v5_use_small_diff_cnt
+// bit[6] v5_simple_mb_inter_all_en
+// bit[5] v5_simple_mb_inter_8x8_en
+// bit[4] v5_simple_mb_inter_16_8_en
+// bit[3] v5_simple_mb_inter_16x16_en
+// bit[2] v5_simple_mb_intra_en
+// bit[1] v5_simple_mb_C_en
+// bit[0] v5_simple_mb_Y_en
+#define V5_SIMPLE_MB_CTL ((0x007e << 2) + 0xfe067c00)
+// bit[31:28] v5_simple_dq_shift
+// bit[27:24] v5_simple_dq_6(-7 to +7)
+// bit[23:20] v5_simple_dq_5(-7 to +7)
+// bit[19:16] v5_simple_dq_4(-7 to +7)
+// bit[15:12] v5_simple_dq_3(-7 to +7)
+// bit[11:08] v5_simple_dq_2(-7 to +7)
+// bit[07:04] v5_simple_dq_1(-7 to +7)
+// bit[03:00] v5_simple_dq_0(-7 to +7)
+#define V5_SIMPLE_MB_DQUANT ((0x007f << 2) + 0xfe067c00)
+// bit[31:28] v5_simple_me_weight_shift
+// bit[27:24] v5_simple_me_weight_6(-7 to +7)
+// bit[23:20] v5_simple_me_weight_5(-7 to +7)
+// bit[19:16] v5_simple_me_weight_4(-7 to +7)
+// bit[15:12] v5_simple_me_weight_3(-7 to +7)
+// bit[11:08] v5_simple_me_weight_2(-7 to +7)
+// bit[07:04] v5_simple_me_weight_1(-7 to +7)
+// bit[03:00] v5_simple_me_weight_0(-7 to +7)
+#define V5_SIMPLE_MB_ME_WEIGHT ((0x0080 << 2) + 0xfe067c00)
+//
+// Closing file: qdct_regs.h
+//
+// HEVC
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe068000
+// -----------------------------------------------
+// HEVC2
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe06c000
+// -----------------------------------------------
+// DOC_TOP
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe06fc00
+// -----------------------------------------------
+//------------------------------------------------------------------------------
+// DOS top-level register offset
+//------------------------------------------------------------------------------
+// -----------------------------------------------
+// `define DOS_TOP_CBUS_BASE 8'h3f
+// -----------------------------------------------
+// [0] reserved
+// [1] Reset Dos top level registers, except sw_reset0/1/2 which is only reset by external reset_n.
+// [2] VDEC1 Reset assist, mdec's CBUS
+// [3] VDEC1 Reset mdec's VLD
+// [4] VDEC1 Reset mdec's VLD
+// [5] VDEC1 Reset mdec's VLD
+// [6] VDEC1 Reset mdec's IQIDCT
+// [7] VDEC1 Reset mdec's MC
+// [8] VDEC1 Reset mdec's DBLK
+// [9] VDEC1 Reset mdec's PIC_DC
+// [10] VDEC1 Reset mdec's Pscale
+// [11] VDEC1 Reset vcpu's MCPU
+// [12] VDEC1 Reset vcpu's CCPU
+// [13] VDEC1 Reset mmc_pre_arb
+#define DOS_SW_RESET0 ((0x0000 << 2) + 0xfe06fc00)
+// [31:27] reserved
+// [26] hcodec clk_en for henc assist
+// [25:22] reserved
+// [21] hcodec clk_en for henc qdct
+// [20] hcodec clk_en for henc vlc
+// [19] hcodec clk_en for assist and cbus
+// [18] hcodec clk_en for ddr
+// [17] hcodec clk_en for vcpu
+// [16] hcodec clk_en for hdec assist
+// [15] hcodec clk_en for hdec dblk
+// [14] reserved
+// [13] hcodec clk_en for hdec mc
+// [12] hcodec clk_en for hdec pic_dc
+// [11:10] reserved
+// [9] vdec clk_en for vdec assist and cbus
+// [8] vdec clk_en for ddr
+// [7] vdec clk_en for vcpu
+// [6] vdec clk_en for mdec vld
+// [5] vdec clk_en for mdec psc
+// [4] vdec clk_en for mdec pic_dc
+// [3] vdec clk_en for mdec mc
+// [2] vdec clk_en for mdec iqidct
+// [1] vdec clk_en for mdec dblk
+// [0] vdec clk_en for mdec assist
+#define DOS_GCLK_EN0 ((0x0001 << 2) + 0xfe06fc00)
+#define DOS_GEN_CTRL0 ((0x0002 << 2) + 0xfe06fc00)
+#define DOS_APB_ERR_CTRL ((0x0003 << 2) + 0xfe06fc00)
+#define DOS_APB_ERR_STAT ((0x0004 << 2) + 0xfe06fc00)
+#define DOS_VDEC_INT_EN ((0x0005 << 2) + 0xfe06fc00)
+#define DOS_HCODEC_INT_EN ((0x0006 << 2) + 0xfe06fc00)
+// [0] Reserved
+// [1] Reserved
+// [2] HCODEC Reset assist, hdec's CBUS
+// [3] HCODEC Reset hdec's VLD
+// [4] HCODEC Reset hdec's VLD
+// [5] HCODEC Reset hdec's VLD
+// [6] HCODEC Reset hdec's IQIDCT
+// [7] HCODEC Reset hdec's MC
+// [8] HCODEC Reset hdec's DBLK
+// [9] HCODEC Reset hdec's PIC_DC
+// [10] HCODEC Reset hdec's Pscale
+// [11] HCODEC Reset vcpu's MCPU
+// [12] HCODEC Reset vcpu's CCPU
+// [13] HCODEC Reset mmc_pre_arb
+// [14] HCODEC Reserved
+// [15] HCODEC Reserved
+// [16] HCODEC Reset henc's VLC
+#define DOS_SW_RESET1 ((0x0007 << 2) + 0xfe06fc00)
+// [0] Reserved
+// [1] Reserved
+// [2] VDEC2 Reset assist, mdec's CBUS
+// [3] VDEC2 Reset mdec's VLD
+// [4] VDEC2 Reset mdec's VLD
+// [5] VDEC2 Reset mdec's VLD
+// [6] VDEC2 Reset mdec's IQIDCT
+// [7] VDEC2 Reset mdec's MC
+// [8] VDEC2 Reset mdec's DBLK
+// [9] VDEC2 Reset mdec's PIC_DC
+// [10] VDEC2 Reset mdec's Pscale
+// [11] VDEC2 Reset vcpu's MCPU
+// [12] VDEC2 Reset vcpu's CCPU
+// [13] VDEC2 Reset mmc_pre_arb
+#define DOS_SW_RESET2 ((0x0008 << 2) + 0xfe06fc00)
+// [31:10] Reserved
+// [9] vdec2 clk_en for assist and cbus.
+// [8] vdec2 clk_en for ddr;
+// [7] vdec2 clk_en for vcpu;
+// [6] vdec2 clk_en for mdec vld
+// [5] vdec2 clk_en for mdec psc
+// [4] vdec2 clk_en for mdec pic_dc
+// [3] vdec2 clk_en for mdec mc
+// [2] vdec2 clk_en for mdec iqidct
+// [1] vdec2 clk_en for mdec dblk
+// [0] vdec2 clk_en for mdec assist
+#define DOS_GCLK_EN1 ((0x0009 << 2) + 0xfe06fc00)
+#define DOS_VDEC2_INT_EN ((0x000a << 2) + 0xfe06fc00)
+#define DOS_VDIN_LCNT ((0x000b << 2) + 0xfe06fc00)
+#define DOS_VDIN_FCNT ((0x000c << 2) + 0xfe06fc00)
+#define DOS_VDIN_CCTL ((0x000d << 2) + 0xfe06fc00)
+#define DOS_SCRATCH0 ((0x0010 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH1 ((0x0011 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH2 ((0x0012 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH3 ((0x0013 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH4 ((0x0014 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH5 ((0x0015 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH6 ((0x0016 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH7 ((0x0017 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH8 ((0x0018 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH9 ((0x0019 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH10 ((0x001a << 2) + 0xfe06fc00)
+#define DOS_SCRATCH11 ((0x001b << 2) + 0xfe06fc00)
+#define DOS_SCRATCH12 ((0x001c << 2) + 0xfe06fc00)
+#define DOS_SCRATCH13 ((0x001d << 2) + 0xfe06fc00)
+#define DOS_SCRATCH14 ((0x001e << 2) + 0xfe06fc00)
+#define DOS_SCRATCH15 ((0x001f << 2) + 0xfe06fc00)
+#define DOS_SCRATCH16 ((0x0020 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH17 ((0x0021 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH18 ((0x0022 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH19 ((0x0023 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH20 ((0x0024 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH21 ((0x0025 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH22 ((0x0026 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH23 ((0x0027 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH24 ((0x0028 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH25 ((0x0029 << 2) + 0xfe06fc00)
+#define DOS_SCRATCH26 ((0x002a << 2) + 0xfe06fc00)
+#define DOS_SCRATCH27 ((0x002b << 2) + 0xfe06fc00)
+#define DOS_SCRATCH28 ((0x002c << 2) + 0xfe06fc00)
+#define DOS_SCRATCH29 ((0x002d << 2) + 0xfe06fc00)
+#define DOS_SCRATCH30 ((0x002e << 2) + 0xfe06fc00)
+#define DOS_SCRATCH31 ((0x002f << 2) + 0xfe06fc00)
+#define DOS_MEM_PD_VDEC ((0x0030 << 2) + 0xfe06fc00)
+#define DOS_MEM_PD_VDEC2 ((0x0031 << 2) + 0xfe06fc00)
+#define DOS_MEM_PD_HCODEC ((0x0032 << 2) + 0xfe06fc00)
+#define DOS_MEM_PD_HEVC ((0x0033 << 2) + 0xfe06fc00)
+#define DOS_SW_RESET3 ((0x0034 << 2) + 0xfe06fc00)
+#define DOS_GCLK_EN3 ((0x0035 << 2) + 0xfe06fc00)
+#define DOS_HEVC_INT_EN ((0x0036 << 2) + 0xfe06fc00)
+#define DOS_SW_RESET4 ((0x0037 << 2) + 0xfe06fc00)
+#define DOS_GCLK_EN4 ((0x0038 << 2) + 0xfe06fc00)
+#define DOS_MEM_PD_WAVE_0 ((0x0039 << 2) + 0xfe06fc00)
+#define DOS_WAVE_CNTL_STAT ((0x003a << 2) + 0xfe06fc00)
+#define DOS_MEM_PD_WAVE_1 ((0x003b << 2) + 0xfe06fc00)
+#define DOS_MEM_PD_WAVE_2 ((0x003c << 2) + 0xfe06fc00)
+// bit[31] mcrcc_stall_en
+// bit[30:28] Reserved
+// bit[27:20] target_canvas
+// bit[19:10] target_mby
+// bit[ 9: 0] target_mbx
+#define DOS_VDEC_MCRCC_STALL_CTRL ((0x0040 << 2) + 0xfe06fc00)
+#define DOS_VDEC_MCRCC_STALL2_CTRL ((0x0042 << 2) + 0xfe06fc00)
+#define DOS_VDEC2_MCRCC_STALL_CTRL ((0x0041 << 2) + 0xfe06fc00)
+#define DOS_VDEC2_MCRCC_STALL2_CTRL ((0x0043 << 2) + 0xfe06fc00)
+#define DOS_MEM_PD_HEVC2 ((0x0044 << 2) + 0xfe06fc00)
+#define DOS_HEVC2_INT_EN ((0x0045 << 2) + 0xfe06fc00)
+// bit[1] s_clk off
+// bit[0] m_clk off
+#define DOS_CFG_CMPIF_BRIDGE ((0x0048 << 2) + 0xfe06fc00)
+// bit[31] cfg_stall_en
+// bit[30] co_mv_stall_en
+// bit[29] cfg_stall_force
+// bit[28:24] reserved
+// bit[23:12] cfg_stall_tilestrt_ctb_y
+// bit[11: 0] cfg_stall_tilestrt_ctb_x
+#define DOS_HEVC_STALL_START ((0x0050 << 2) + 0xfe06fc00)
+// bit[31:24] cfg_stall_canvas
+// bit[23:12] cfg_stall_tileend_ctb_y
+// bit[11: 0] cfg_stall_tileend_ctb_x
+#define DOS_HEVC_STALL_END ((0x0051 << 2) + 0xfe06fc00)
+// bit[31:24] reserved
+// bit[23:12] cfg_stall_ctb_y
+// bit[11: 0] cfg_stall_ctb_x
+#define DOS_HEVC_STALL_POSITION ((0x0052 << 2) + 0xfe06fc00)
+// bit[31] cfg_stall_en
+// bit[30] co_mv_stall_en
+// bit[29] cfg_stall_force
+// bit[28:24] reserved
+// bit[23:12] cfg_stall_tilestrt_ctb_y
+// bit[11: 0] cfg_stall_tilestrt_ctb_x
+#define DOS_HEVC2_STALL_START ((0x0053 << 2) + 0xfe06fc00)
+// bit[31:24] cfg_stall_canvas
+// bit[23:12] cfg_stall_tileend_ctb_y
+// bit[11: 0] cfg_stall_tileend_ctb_x
+#define DOS_HEVC2_STALL_END ((0x0054 << 2) + 0xfe06fc00)
+// bit[31:24] reserved
+// bit[23:12] cfg_stall_ctb_y
+// bit[11: 0] cfg_stall_ctb_x
+#define DOS_HEVC2_STALL_POSITION ((0x0055 << 2) + 0xfe06fc00)
+#define DOS_SECURE_CTL_INDEX ((0x0080 << 2) + 0xfe06fc00)
+#define DOS_SECURE_CTL_DATA ((0x0081 << 2) + 0xfe06fc00)
+#define DOS_SECURE_REG_NULL ((0x0082 << 2) + 0xfe06fc00)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: REG_LIST_DOS_RTL.h
+//
+//
+// Reading file: gdc_regs.h
+//
+//===========================================================================
+////// GDC Registers
+//===========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe008800
+// -----------------------------------------------
+#define GDC_REG_START ((0x0000 << 2) + 0xfe008800)
+//
+// Closing file: gdc_regs.h
+//
+//
+// Reading file: ge2d_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+//GE2D Registers
+//===========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe008c00
+// -----------------------------------------------
+//Bit 31, destination bytemask only if destination bitmask is enable
+//Bit 30, destination bitmask enable
+//Bit 29, source2 key enable
+//Bit 28, source2 key mode, 0: mask data when match, 1: mask data when unmatch
+//Bit 27, source1 key enable
+//Bit 26, source1 key mode, 0: mask data when match, 1: mask data when unmatch
+//Bit 25:24, dst1 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 23 dst clip mode, 0: write inside clip window, 1: write outside clip window
+//Bit 22:17, reserved
+//Bit 16:15, src2 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 14 src2 fill mode, 0: repeat data, 1: fill default color
+//Bit 13:12 src2 picture struct, 00: frame, 10: even, 11: odd
+//Bit 11 src1 x direction yc ration, 0: 1:1, 1: 2:1
+//Bit 10 src1 y direction yc ration, 0: 1:1, 1: 2:1
+//Bit 9:7 reserved
+//Bit 6:5, src1 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 4 src1 fill mode, 0: repeat data, 1: fill default color
+//Bit 3 src1 lookup table enable
+//Bit 2:1 src1 picture struct, 00: frame, 10: even, 11: odd
+//Bit 0 src1 separate buffer enable
+#define GE2D_GEN_CTRL0 ((0x00a0 << 2) + 0xfe008c00)
+//Bit 31, soft rst
+//Bit 30, dst write response counter reset
+//Bit 29, disable adding dst write response count to busy bit
+//Bit 28:26, reserved
+//bit 25:24, interrupt control, if bit[0] true, generate interrupt when one command done,
+// if bit[1] true, generate interrupt when ge2d change from busy to not busy
+//Bit 23:22 src2 burst size control
+//Bit 21:16 src1 burst size control, 5:4, yfifo, 3:2, cbfifo, 1:0, crfifo
+// each 2bit, 00: 24 64bitword, 01: 32 64bitword, 10: 48 64bitwords, 11: 64 64bitwords
+//Bit 15:14, dst1 picture struct, 00: frame, 10:top, 11: bottom
+//Bit 13:12, bit 13 if true, force read src1, bit 12 if true, force read src2
+//Bit 11, dst2 request urgent enable
+//Bit 10, src1 request urgent enable
+//Bit 9, src2 request urgent enable
+//Bit 8, dst1 request urgent enable
+//Bit 7:0 src1 global alpha
+#define GE2D_GEN_CTRL1 ((0x00a1 << 2) + 0xfe008c00)
+//Bit31 alpha conversion mode in alu, 0: alpha_out = (alpha !=0) ? alpha +1 : 0;
+// otherwise, alpha_out = (alpha < 128) ? alpha: alpha + 1;
+//Bit30 color conversion mode in alu, 0: color_out = (color != 0) ? color +1: 0;
+// otherwise, color_out = (color < 128) ? color: color + 1;
+//Bit29 src1_gb_alpha_en, As = src1_gb_alpha_en ? Asr * Ag: Asr
+//Bit28 dst1_color_round_mode, 0: truncate, 1: + 0.5 rounding
+//Bit27 src2_color_expand_mode, 0: add 0, 1: add MSBs
+//Bit26 src2_alpha_expand_mode, 0: add 0, 1: add MSBs
+//Bit25 src1_color_expand_mode, 0: add 0, 1: add MSBs
+//Bit24 src1_alpha_expand_mode, 0: add 0, 1: add MSBs
+//Bit 23 if true, dst little endian, otherwise big endian
+//Bit 22:19 dst1 color_map
+// dst1_format=0 : output 8-bit;
+// dst1_format=1, dst1_color_map=1: output 16-bit YCbCr 655;
+// dst1_format=1, dst1_color_map=2: output 16-bit YCbCr 844;
+// dst1_format=1, dst1_color_map=3: output 16-bit YCbCrA 6442;
+// dst1_format=1, dst1_color_map=4: output 16-bit YCbCrA 4444;
+// dst1_format=1, dst1_color_map=5: output 16-bit YCbCr 565;
+// dst1_format=1, dst1_color_map=6: output 16-bit AYCbCr 4444;
+// dst1_format=1, dst1_color_map=7: output 16-bit AYCbCr 1555;
+// dst1_format=1, dst1_color_map=8: output 16-bit YCbCrA 4642;
+// dst1_format=1, dst1_color_map=9: output 16-bit CbCr 88;
+// dst1_format=1, dst1_color_map=10:output 16-bit CrCb 88;
+// dst1_format=2, dst1_color_map=0: output 24-bit YCbCr 888;
+// dst1_format=2, dst1_color_map=1: output 24-bit YCbCrA 5658;
+// dst1_format=2, dst1_color_map=2: output 24-bit AYCbCr 8565;
+// dst1_format=2, dst1_color_map=3: output 24-bit YCbCrA 6666;
+// dst1_format=2, dst1_color_map=4: output 24-bit AYCbCr 6666;
+// dst1_format=2, dst1_color_map=5: output 24-bit CrCbY 888;
+// dst1_format=3, dst1_color_map=0: output 32-bit YCbCrA 8888;
+// dst1_format=3, dst1_color_map=1: output 32-bit AYCbCr 8888;
+// dst1_format=3, dst1_color_map=2: output 32-bit ACrCbY 8888;
+// dst1_format=3, dst1_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 17:16 dst1_format, 00: 8bit, 01:16bit, 10:24bit, 11: 32bit
+//Bit 15 if true, src2 little endian, otherwise big endian
+//Bit 14:11 src2 color_map
+// src2_format=0 : output 8-bit;
+// src2_format=1, src2_color_map=1: output 16-bit YCbCr 655;
+// src2_format=1, src2_color_map=2: output 16-bit YCbCr 844;
+// src2_format=1, src2_color_map=3: output 16-bit YCbCrA 6442;
+// src2_format=1, src2_color_map=4: output 16-bit YCbCrA 4444;
+// src2_format=1, src2_color_map=5: output 16-bit YCbCr 565;
+// src2_format=1, src2_color_map=6: output 16-bit AYCbCr 4444;
+// src2_format=1, src2_color_map=7: output 16-bit AYCbCr 1555;
+// src2_format=1, src2_color_map=8: output 16-bit YCbCrA 4642;
+// src2_format=2, src2_color_map=0: output 24-bit YCbCr 888;
+// src2_format=2, src2_color_map=1: output 24-bit YCbCrA 5658;
+// src2_format=2, src2_color_map=2: output 24-bit AYCbCr 8565;
+// src2_format=2, src2_color_map=3: output 24-bit YCbCrA 6666;
+// src2_format=2, src2_color_map=4: output 24-bit AYCbCr 6666;
+// src2_format=2, src2_color_map=5: output 24-bit CrCbY 888;
+// src2_format=3, src2_color_map=0: output 32-bit YCbCrA 8888;
+// src2_format=3, src2_color_map=1: output 32-bit AYCbCr 8888;
+// src2_format=3, src2_color_map=2: output 32-bit ACrCbY 8888;
+// src2_format=3, src2_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 9:8 src2 format, 00: 8bit, 01:16bit, 10:24bit 11: 32bit
+//Bit 7 if true, src1 little endian, otherwise big endian
+//Bit 6:3 src1 color_map
+// src1_format=0 : output 8-bit;
+// src1_format=1, src1_color_map=0: output 4:2:2 (Y0Cb0Y1Cr0);
+// src1_format=1, src1_color_map=1: output 16-bit YCbCr 655;
+// src1_format=1, src1_color_map=2: output 16-bit YCbCr 844;
+// src1_format=1, src1_color_map=3: output 16-bit YCbCrA 6442;
+// src1_format=1, src1_color_map=4: output 16-bit YCbCrA 4444;
+// src1_format=1, src1_color_map=5: output 16-bit YCbCr 565;
+// src1_format=1, src1_color_map=6: output 16-bit AYCbCr 4444;
+// src1_format=1, src1_color_map=7: output 16-bit AYCbCr 1555;
+// src1_format=1, src2_color_map=8: output 16-bit YCbCrA 4642;
+// src1_format=2, src1_color_map=0: output 24-bit YCbCr 888;
+// src1_format=2, src1_color_map=1: output 24-bit YCbCrA 5658;
+// src1_format=2, src1_color_map=2: output 24-bit AYCbCr 8565;
+// src1_format=2, src1_color_map=3: output 24-bit YCbCrA 6666;
+// src1_format=2, src1_color_map=4: output 24-bit AYCbCr 6666;
+// src1_format=2, src1_color_map=5: output 24-bit CrCbY 888;
+// src1_format=2, src1_color_map=14:output 8-bit Y and 16-bit CbCr;
+// src1_format=2, src1_color_map=15:output 8-bit Y and 16-bit CrCb;
+// src1_format=3, src1_color_map=0: output 32-bit YCbCrA 8888;
+// src1_format=3, src1_color_map=1: output 32-bit AYCbCr 8888;
+// src1_format=3, src1_color_map=2: output 32-bit ACrCbY 8888;
+// src1_format=3, src1_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 1:0 src1 format, 00: 8bit, 01:16bit/4:2:2, 10:24bit 11: 32bit
+#define GE2D_GEN_CTRL2 ((0x00a2 << 2) + 0xfe008c00)
+//Bit 9 if true, all src2 data use default color
+//Bit 8 if true, all src1 data use default color
+//Bit 7 if true, dst x/y swap
+//Bit 6 if true, dst x direction reversely read
+//Bit 5 if true, dst y direction reversely read
+//Bit 4 if true, src2 x direction reversely read
+//Bit 3 if true, src2 y direction reversely read
+//Bit 2 if true, src1 x direction reversely read
+//Bit 1 if true, src1 y direction reversely read
+//Bit 0 cmd write
+#define GE2D_CMD_CTRL ((0x00a3 << 2) + 0xfe008c00)
+//Read only
+//Bit 28:17 dst write response counter, for debug only
+//Bit 16:7 ge2d_dp status, for debug only
+//Bit 6 read src1 cmd ready
+//Bit 5 read src2 cmd ready
+//Bit 4 pre dpcmd ready
+//Bit 3 ge2d dpcmd ready
+//Bit 2 ge2d buffer command valid
+//Bit 1 ge2d current command valid
+//Bit 0 ge2d busy
+#define GE2D_STATUS0 ((0x00a4 << 2) + 0xfe008c00)
+//
+//Read only
+// Bit 29:16 ge2d_dst1_status, for debug only
+// Bit 15 ge2d_rd_src2 core.fifo_empty
+// Bit 14 ge2d_rd_src2 core.fifo_overflow
+// Bit 13:12 ge2d_rd_src2 core.req_st
+// Bit 11 ge2d_rd_src2 cmd_if.cmd_err, true if cmd_format=1
+// Bit 10 ge2d_rd_src2 cmd_if.cmd_st, 0=IDLE state, 1=BUSY state
+// Bit 9 ge2d_rd_src1 luma_core(chroma_core).fifo_empty
+// Bit 8 ge2d_rd_src1 luma_core(chroma_core).fifo_overflow
+// Bit 7: 6 ge2d_rd_src1 chroma_core.req_st_cr
+// Bit 5: 4 ge2d_rd_src1 chroma_core.req_st_cb
+// Bit 3: 2 ge2d_rd_src1 luma_core.req_st_y
+// Bit 1 ge2d_rd_src1 cmd_if.stat_read_window_err, 1=reading/clipping window setting exceed limit
+// Bit 0 ge2d_rd_src1 cmd_if.cmd_st, 0=IDLE state, 1=BUSY state
+#define GE2D_STATUS1 ((0x00a5 << 2) + 0xfe008c00)
+//SRC1 default clolor
+//{Y,Cb,Cr,A}/{R,G,B,A}
+#define GE2D_SRC1_DEF_COLOR ((0x00a6 << 2) + 0xfe008c00)
+//Bit 31, SRC1 clip x start extra, if true, one more data is read for chroma
+//Bit 28:16, SRC1 clip x start
+//Bit 15, SRC1 clip x end extra, if true, one more data is read for chroma
+//Bit 12:0, SRC1 clip x end
+#define GE2D_SRC1_CLIPX_START_END ((0x00a7 << 2) + 0xfe008c00)
+//Bit 31, SRC1 clip y start extra, if true, one more data is read for chroma
+//Bit 28:16, SRC1 clip y start
+//Bit 15, SRC1 clip y end extra, if true, one more data is read for chroma
+//Bit 12:0, SRC1 clip y end
+#define GE2D_SRC1_CLIPY_START_END ((0x00a8 << 2) + 0xfe008c00)
+//Bit 31:24, SRC1 canvas address0
+//Bit 23:16, SRC1 canvas address1
+//Bit 15:8, SRC1 canvas address2
+#define GE2D_SRC1_CANVAS ((0x00a9 << 2) + 0xfe008c00)
+//Bit 31, SRC1 x start extra bit1, if true, one more chroma data is read for x even start chroma data when y/c ratio = 2
+// or x even/odd start chroma extra data when y/c ratio = 1
+//Bit 30, SRC1 x start extra bit0, if true, one more chroma data is read for x odd start chroma data when y/c ratio = 2
+//Bit 29:16, SRC1 x start, signed data
+//Bit 15, SRC1 x end extra bit1, if true, one more chroma data is read for x odd end chroma data when y/c ratio = 2
+// or x even/odd end chroma extra data when y/c ratio = 1
+//Bit 14, SRC1 x end extra bit0, if true, one more chroma data is read for x even end chroma data when y/c ratio = 2
+//Bit 13:0, SRC1 x end, signed data
+#define GE2D_SRC1_X_START_END ((0x00aa << 2) + 0xfe008c00)
+//Bit 31, SRC1 y start extra, if true, one more chroma data is read for y even start chroma data when y/c ratio = 2
+// or y even/odd start chroma extra data when y/c ratio = 1
+//Bit 30, SRC1 y start extra, if true, one more chroma data is read for x odd start chroma data when y/c ratio = 2
+//Bit 28:16, SRC1 y start
+//Bit 15, SRC1 y end extra bit1, if true, one more chroma data is read for y odd end chroma data when y/c ratio = 2
+// or y even/odd end chroma extra data when y/c ratio = 1
+//Bit 14, SRC1 y end extra bit0, if true, one more chroma data is read for y even end chroma data when y/c ratio = 2
+//Bit 12:0, SRC1 y end
+#define GE2D_SRC1_Y_START_END ((0x00ab << 2) + 0xfe008c00)
+// Bit 31: 9 Reserved
+// Bit 8 RW, 0 = Write LUT, 1 = Read LUT
+// Bit 7: 0 RW, lut_addr
+#define GE2D_SRC1_LUT_ADDR ((0x00ac << 2) + 0xfe008c00)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define GE2D_SRC1_LUT_DAT ((0x00ad << 2) + 0xfe008c00)
+//Bit 19, if true, horizontal formatter using repeat to get the pixel, otherwise using interpolation
+//Bit 18, horizontal formatter en
+//Bit 17, if true, vertical formatter using repeat to get the pixel, otherwise using interpolation
+//Bit 16, vertical formatter en
+//Bit 15:8 X direction chroma phase,
+// [7:4] for x direction even start/end chroma phase when y/c ratio = 2
+// or start/end even/odd chroma phase when y/c ratio = 1
+// [3:0] for x direction odd start/end chroma phase only when y/c ration = 2
+//Bit 7:0 Y direction chroma phase,
+// [7:4] for y direction even start/end chroma phase when y/c ratio = 2
+// or start/end even/odd chroma phase when y/c ratio = 1
+// [3:0] for y direction odd start/end chroma phase only when y/c ration = 2
+#define GE2D_SRC1_FMT_CTRL ((0x00ae << 2) + 0xfe008c00)
+//SRC2 default clolor
+//{Y,Cb,Cr,A}/{R,G,B,A}
+#define GE2D_SRC2_DEF_COLOR ((0x00af << 2) + 0xfe008c00)
+//Bit 28:16, SRC2 clip x start
+//Bit 12:0, SRC2 clip x end
+#define GE2D_SRC2_CLIPX_START_END ((0x00b0 << 2) + 0xfe008c00)
+//Bit 28:16, SRC2 clip y start
+//Bit 12:0, SRC2 clip y end
+#define GE2D_SRC2_CLIPY_START_END ((0x00b1 << 2) + 0xfe008c00)
+//Bit 28:16, SRC2 x start
+//Bit 12:0, SRC2 x end
+#define GE2D_SRC2_X_START_END ((0x00b2 << 2) + 0xfe008c00)
+//Bit 28:16, SRC2 y start
+//Bit 12:0, SRC2 y end
+#define GE2D_SRC2_Y_START_END ((0x00b3 << 2) + 0xfe008c00)
+//Bit 28:16, DST clip x start
+//Bit 12:0, DST clip x end
+#define GE2D_DST_CLIPX_START_END ((0x00b4 << 2) + 0xfe008c00)
+//
+//Bit 28:16, DST clip y start
+//Bit 12:0, DST clip y end
+#define GE2D_DST_CLIPY_START_END ((0x00b5 << 2) + 0xfe008c00)
+//Bit 28:16, DST x start
+//Bit 12:0, DST x end
+#define GE2D_DST_X_START_END ((0x00b6 << 2) + 0xfe008c00)
+//
+//Bit 28:16, DST x start
+//Bit 12:0, DST x end
+#define GE2D_DST_Y_START_END ((0x00b7 << 2) + 0xfe008c00)
+//Bit 23:16 DST2 canvas address
+//Bit 15:8 SRC2 canvas address
+//Bit 7:0 DST1 canvas address
+#define GE2D_SRC2_DST_CANVAS ((0x00b8 << 2) + 0xfe008c00)
+//vertical scaler phase step
+//Bit 28:0, 5.24 format
+#define GE2D_VSC_START_PHASE_STEP ((0x00b9 << 2) + 0xfe008c00)
+//phase slope
+//Bit 24:0, bit 24 signed bit
+#define GE2D_VSC_PHASE_SLOPE ((0x00ba << 2) + 0xfe008c00)
+//Bit 30:29, vertical repeat line0 number
+//Bit 23:0, vertical scaler initial phase
+#define GE2D_VSC_INI_CTRL ((0x00bb << 2) + 0xfe008c00)
+//horizontal scaler phase step
+//Bit 28:0, 5.24 format
+#define GE2D_HSC_START_PHASE_STEP ((0x00bc << 2) + 0xfe008c00)
+//phase slope
+//Bit 24:0, bit 24 signed bit
+#define GE2D_HSC_PHASE_SLOPE ((0x00bd << 2) + 0xfe008c00)
+//Bit 30:29, horizontal repeat line0 number
+//Bit 23:0, horizontal scaler initial phase
+#define GE2D_HSC_INI_CTRL ((0x00be << 2) + 0xfe008c00)
+//Bit 31:24, advance number in this round, if horizontal scaler is working on dividing mode
+//Bit 23:0, horizontal scaler advance phase in this round, if horizontal scaler is working on dividing mode
+#define GE2D_HSC_ADV_CTRL ((0x00bf << 2) + 0xfe008c00)
+//Bit 30, vertical nearest mode enable, must set vt_bank_length = 4
+//Bit 29, horizontal nearest mode enable, must set hz_bank_length = 4
+//Bit 28, horizontal scaler dividing mode enable
+//Bit 27:15, horizontal dividing length, if bit 28 is enable
+//Bit 14, pre horizontal scaler enable
+//Bit 13, pre vertical scale enable
+//Bit 12, vertical scale enable
+//Bit 11, horizontal scaler enable
+//Bit 9, if true, treat horizontal repeat line number(GE2D_HSC_INI_CTRL bit 30:29) as repeating line,
+// otherwise using treat horizontal repeat line number as minus line number.
+//Bit 8, if true, treat vertical repeat line number(GE2D_VSC_INI_CTRL bit 30:29) as repeating line,
+// otherwise using treat vertical repeat line number as minus line number.
+//Bit 7, if true, always use phase0 in vertical scaler
+//Bit 6:4, vertical scaler bank length
+//Bit 3, if true, always use phase0 in horizontal scaler
+//Bit 2:0, horizontal scaler bank length
+#define GE2D_SC_MISC_CTRL ((0x00c0 << 2) + 0xfe008c00)
+//Read only
+//vertical scaler next round integer pixel pointer, signed data
+//Bit 13:0
+#define GE2D_VSC_NRND_POINT ((0x00c1 << 2) + 0xfe008c00)
+//Read only
+//vertical scaler next round phase
+//bit 23:0
+#define GE2D_VSC_NRND_PHASE ((0x00c2 << 2) + 0xfe008c00)
+//Read only
+//horizontal scaler next round integer pixel pointer, signed data
+//Bit 13:0
+#define GE2D_HSC_NRND_POINT ((0x00c3 << 2) + 0xfe008c00)
+//Read only
+//horizontal scaler next round phase
+//bit 23:0
+#define GE2D_HSC_NRND_PHASE ((0x00c4 << 2) + 0xfe008c00)
+//
+//Bit 28:20, pre_offset0
+//Bit 18:10, pre_offset1
+//Bit 8:0, pre_offset2
+#define GE2D_MATRIX_PRE_OFFSET ((0x00c5 << 2) + 0xfe008c00)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define GE2D_MATRIX_COEF00_01 ((0x00c6 << 2) + 0xfe008c00)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define GE2D_MATRIX_COEF02_10 ((0x00c7 << 2) + 0xfe008c00)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define GE2D_MATRIX_COEF11_12 ((0x00c8 << 2) + 0xfe008c00)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define GE2D_MATRIX_COEF20_21 ((0x00c9 << 2) + 0xfe008c00)
+//Bit 28:16 coef22
+//Bit 7 input y/cb/cr saturation enable
+//Bit 0 conversion matrix enable
+#define GE2D_MATRIX_COEF22_CTRL ((0x00ca << 2) + 0xfe008c00)
+//Bit 28:20, offset0
+//Bit 18:10, offset1
+//Bit 8:0, offset2
+#define GE2D_MATRIX_OFFSET ((0x00cb << 2) + 0xfe008c00)
+//Bit 26:25, SRC1 color multiplier alpha selection
+// if 00, Cs = Csr
+// if 01, Cs = Csr * Asr * Ag (if source is not premultiplied)
+// if 10, Cs = Csr * Ag (if source is premultipied)
+//Bit 24 SRC2 color multiplier alpha selection
+// if 0, no multiplier, Cd = Cdr, otherwise, Cd = Cdr * Ad.
+//Bit 22:12 ALU color operation
+// bit10:8 Blending Mode Parameter
+// 3'b000: ADD Cs*Fs + Cd*Fd
+// 3'b001: SUBTRACT Cs*Fs - Cd*Fd
+// 3'b010: REVERSE SUBTRACT Cd*Fd - Cs*Fs
+// 3'b011: MIN min(Cs*Fs, Cd*Fd)
+// 3'b100: MAX max(Cs*Fs, Cd*Fd)
+// 3'b101: LOGIC OP Cs op Cd
+// bit7:4 Source Color Blending Factor CFs
+// 4'b0000: ZERO 0
+// 4'b0001: ONE 1
+// 4'b0010: SRC_COLOR Cs(RGBs)
+// 4'b0011: ONE_MINUS_SRC_COLOR 1 - Cs(RGBs)
+// 4'b0100: DST_COLOR Cd(RGBd)
+// 4'b0101: ONE_MINUS_DST_COLOR 1 - Cd(RGBd)
+// 4'b0110: SRC_ALPHA As
+// 4'b0111: ONE_MINUS_SRC_ALPHA 1 - As
+// 4'b1000: DST_ALPHA Ad
+// 4'b1001: ONE_MINUS_DST_ALPHA 1 - Ad
+// 4'b1010: CONST_COLOR Cc(RGBc)
+// 4'b1011: ONE_MINUS_CONST_COLOR 1 - Cc(RGBc)
+// 4'b1100: CONST_ALPHA Ac
+// 4'b1101: ONE_MINUS_CONST_ALPHA 1 - Ac
+// 4'b1110: SRC_ALPHA_SATURATE min(As,1-Ad)
+// bit3:0 dest Color Blending Factor CFd, when bit10:8 != LOGIC OP
+// 4'b0000: ZERO 0
+// 4'b0001: ONE 1
+// 4'b0010: SRC_COLOR Cs(RGBs)
+// 4'b0011: ONE_MINUS_SRC_COLOR 1 - Cs(RGBs)
+// 4'b0100: DST_COLOR Cd(RGBd)
+// 4'b0101: ONE_MINUS_DST_COLOR 1 - Cd(RGBd)
+// 4'b0110: SRC_ALPHA As
+// 4'b0111: ONE_MINUS_SRC_ALPHA 1 - As
+// 4'b1000: DST_ALPHA Ad
+// 4'b1001: ONE_MINUS_DST_ALPHA 1 - Ad
+// 4'b1010: CONST_COLOR Cc(RGBc)
+// 4'b1011: ONE_MINUS_CONST_COLOR 1 - Cc(RGBc)
+// 4'b1100: CONST_ALPHA Ac
+// 4'b1101: ONE_MINUS_CONST_ALPHA 1 - Ac
+// 4'b1110: SRC_ALPHA_SATURATE min(As,1-Ad)
+// bit3:0 logic operations, when bit10:8 == LOGIC OP
+// 4'b0000: CLEAR 0
+// 4'b0001: COPY s
+// 4'b0010: NOOP d
+// 4'b0011: SET 1
+// 4'b0100: COPY_INVERT ~s
+// 4'b0101: INVERT ~d
+// 4'b0110: AND_REVERSE s & ~d
+// 4'b0111: OR_REVERSE s | ~d
+// 4'b1000: AND s & d
+// 4'b1001: OR s | d
+// 4'b1010: NAND ~(s & d)
+// 4'b1011: NOR ~(s | d)
+// 4'b1100: XOR s ^ d
+// 4'b1101: EQUIV ~(s ^ d)
+// 4'b1110: AND_INVERTED ~s & d
+// 4'b1111: OR_INVERTED ~s | d
+//Bit 10:0 ALU alpha operation
+// bit10:8 Blending Equation Math Operation
+// 3'b000: ADD As*Fs + Ad*Fd
+// 3'b001: SUBTRACT As*Fs - Ad*Fd
+// 3'b010: REVERSE SUBTRACT Ad*Fd - As*Fs
+// 3'b011: MIN min(As*Fs, Ad*Fd)
+// 3'b100: MAX max(As*Fs, Ad*Fd)
+// 3'b101: LOGIC OP As op Ad
+// bit7:4 Source alpha Blending Factor AFs
+// 4'b0000 0
+// 4'b0001 1
+// 4'b0010 As
+// 4'b0011 1 - As
+// 4'b0100 Ad
+// 4'b0101 1 - Ad
+// 4'b0110 Ac
+// 4'b0111 1 - Ac
+// .... reserved
+// bit3:0 Destination alpha Blending Factor AFd, when bit10:8 != LOGIC OP
+// 4'b0000 0
+// 4'b0001 1
+// 4'b0010 As
+// 4'b0011 1 - As
+// 4'b0100 Ad
+// 4'b0101 1 - Ad
+// 4'b0110 Ac
+// 4'b0111 1 - Ac
+// .... reserved
+// bit3:0 logic operations, when bit10:8 == LOGIC OP
+// 4'b0000: CLEAR 0
+// 4'b0001: COPY s
+// 4'b0010: NOOP d
+// 4'b0011: SET 1
+// 4'b0100: COPY_INVERT ~s
+// 4'b0101: INVERT ~d
+// 4'b0110: AND_REVERSE s & ~d
+// 4'b0111: OR_REVERSE s | ~d
+// 4'b1000: AND s & d
+// 4'b1001: OR s | d
+// 4'b1010: NAND ~(s & d)
+// 4'b1011: NOR ~(s | d)
+// 4'b1100: XOR s ^ d
+// 4'b1101: EQUIV ~(s ^ d)
+// 4'b1110: AND_INVERTED ~s & d
+// 4'b1111: OR_INVERTED ~s | d
+#define GE2D_ALU_OP_CTRL ((0x00cc << 2) + 0xfe008c00)
+//bit 31:0 (RGBA,YCBCRA)
+#define GE2D_ALU_CONST_COLOR ((0x00cd << 2) + 0xfe008c00)
+//SRC1 Key
+//31:0
+#define GE2D_SRC1_KEY ((0x00ce << 2) + 0xfe008c00)
+//SRC1 Key Mask
+//31:0
+#define GE2D_SRC1_KEY_MASK ((0x00cf << 2) + 0xfe008c00)
+//SRC2 Key
+//31:0
+#define GE2D_SRC2_KEY ((0x00d0 << 2) + 0xfe008c00)
+//SRC2 Key Mask
+//31:0
+#define GE2D_SRC2_KEY_MASK ((0x00d1 << 2) + 0xfe008c00)
+//Destination Bit Mask
+//31:0
+#define GE2D_DST_BITMASK ((0x00d2 << 2) + 0xfe008c00)
+//Bit 31 DP onoff mode, 0: on_counter means how many pixels will output before ge2d turns off
+// 1: on_counter means how many clocks will ge2d turn on before ge2d turns off
+//Bit 30:16 DP on counter
+//Bit 15 0: vd_format doesnt have onoff mode, 1: vd format has onoff mode
+//Bit 14:0 DP off counter
+#define GE2D_DP_ONOFF_CTRL ((0x00d3 << 2) + 0xfe008c00)
+//Because there are many coefficients used in the vertical filter and horizontal filters,
+//indirect access the coefficients of vertical filter and horizontal filter is used.
+//For vertical filter, there are 33x4 coefficients
+//For horizontal filter, there are 33x4 coefficients
+//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
+//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
+//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
+//Bit 8 type of index, 0: vertical coef
+// 1: horizontal coef
+//Bit 6:0 coef index
+#define GE2D_SCALE_COEF_IDX ((0x00d4 << 2) + 0xfe008c00)
+//coefficients for vertical filter and horizontal filter
+#define GE2D_SCALE_COEF ((0x00d5 << 2) + 0xfe008c00)
+//Bit 24 src2 alpha fill mode: together with GE2D_GEN_CTRL0[4](fill_mode), define what alpha values are used
+// for the area outside the clipping window. As below:
+// fill_mode=0, alpha_fill_mode=0 : use inner alpha, (or default_alpha if src data have no alpha values);
+// fill_mode=0, alpha_fill_mode=1 : use outside_alpha;
+// fill_mode=1, alpha_fill_mode=0 : use default_alpha;
+// fill_mode=1, alpha_fill_mode=1 : use outside_alpha.
+//Bit 23:16 src2 outside alpha
+//Bit 8 src1 alpha fill mode, refer to src2 alpha fill mode above.
+//Bit 7:0 src1 outside alpha
+#define GE2D_SRC_OUTSIDE_ALPHA ((0x00d6 << 2) + 0xfe008c00)
+//Bit 31 antiflick enable
+//Bit 24 1: alpha value for the first line use repeated alpha, 0: use bit 23:16 as the first line alpha
+//Bit 23:16 register value for the first line alpha when bit 24 is 1
+//Bit 8 1: alpha value for the last line use repeated alpha, 0: use bit 7:0 as the last line alpha
+//Bit 7:0 register value for the last line alpha when bit 8 is 1
+#define GE2D_ANTIFLICK_CTRL0 ((0x00d8 << 2) + 0xfe008c00)
+//Bit 25, rgb_sel, 1: antiflick RGBA, 0: antiflick YCbCrA
+//Bit 24, cbcr_en, 1: also filter cbcr in case of antiflicking YCbCrA, 0: no filter on cbcr in case of antiflicking YCbCrA
+//Bit 23:16, R mult coef for converting RGB to Y
+//Bit 15:8, G mult coef for converting RGB to Y
+//Bit 7:0, B mult coef for converting RGB to Y
+//Y = (R * y_r + G * y_g + B * y_b) / 256
+#define GE2D_ANTIFLICK_CTRL1 ((0x00d9 << 2) + 0xfe008c00)
+//Bit 31:24, Y threhold1, when 0<Y<=th1, use filter0;
+//Bit 23:16, color antiflick filter0 n3
+//Bit 15:8, color antiflick filter0 n2
+//Bit 7:0, color antiflick filter0 n1
+//Y = (line_up * n1 + line_center * n2 + line_dn * n3) / 128
+#define GE2D_ANTIFLICK_COLOR_FILT0 ((0x00da << 2) + 0xfe008c00)
+//Bit 31:24, Y threhold2, when th1<Y<=th2, use filter1;
+//Bit 23:16, color antiflick filter1 n3
+//Bit 15:8, color antiflick filter1 n2
+//Bit 7:0, color antiflick filter1 n1
+#define GE2D_ANTIFLICK_COLOR_FILT1 ((0x00db << 2) + 0xfe008c00)
+//Bit 31:24, Y threhold3, when th2<Y<=th3, use filter2; Y>th3, use filter3
+//Bit 23:16, color antiflick filter2 n3
+//Bit 15:8, color antiflick filter2 n2
+//Bit 7:0, color antiflick filter2 n1
+#define GE2D_ANTIFLICK_COLOR_FILT2 ((0x00dc << 2) + 0xfe008c00)
+//Bit 23:16, color antiflick filter3 n3
+//Bit 15:8, color antiflick filter3 n2
+//Bit 7:0, color antiflick filter3 n1
+#define GE2D_ANTIFLICK_COLOR_FILT3 ((0x00dd << 2) + 0xfe008c00)
+//Bit 31:24, Alpha threhold1, when 0<Alpha<=th1, use filter0;
+//Bit 23:16, Alpha antiflick filter0 n3
+//Bit 15:8, Alpha antiflick filter0 n2
+//Bit 7:0, Alpha antiflick filter0 n1
+//Alpha = (line_up * n1 + line_center * n2 + line_dn * n3) / 128
+#define GE2D_ANTIFLICK_ALPHA_FILT0 ((0x00de << 2) + 0xfe008c00)
+//Bit 31:24, Alpha threhold2, when th1<Alpha<=th2, use filter1;
+//Bit 23:16, Alpha antiflick filter1 n3
+//Bit 15:8, Alpha antiflick filter1 n2
+//Bit 7:0, Alpha antiflick filter1 n1
+#define GE2D_ANTIFLICK_ALPHA_FILT1 ((0x00df << 2) + 0xfe008c00)
+//Bit 31:24, Alpha threhold3, when th2<Alpha<=th3, use filter2; Alpha>th3, use filter3
+//Bit 23:16, Alpha antiflick filter2 n3
+//Bit 15:8, Alpha antiflick filter2 n2
+//Bit 7:0, Alpha antiflick filter2 n1
+#define GE2D_ANTIFLICK_ALPHA_FILT2 ((0x00e0 << 2) + 0xfe008c00)
+//Bit 23:16, Alpha antiflick filter3 n3
+//Bit 15:8, Alpha antiflick filter3 n2
+//Bit 7:0, Alpha antiflick filter3 n1
+#define GE2D_ANTIFLICK_ALPHA_FILT3 ((0x00e1 << 2) + 0xfe008c00)
+//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset)
+//Bit 30:22 din_offset (signed data)
+//Bit 21:14 map_coef (unsigned data)
+//Bit 13:10 map_sr (unsigned data)
+//Bit 9:1 dout_offset (signed data)
+//Bit 0 enable
+#define GE2D_SRC1_RANGE_MAP_Y_CTRL ((0x00e3 << 2) + 0xfe008c00)
+//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset)
+//Bit 30:22 din_offset (signed data)
+//Bit 21:14 map_coef (unsigned data)
+//Bit 13:10 map_sr (unsigned data)
+//Bit 9:1 dout_offset (signed data)
+//Bit 0 enable
+#define GE2D_SRC1_RANGE_MAP_CB_CTRL ((0x00e4 << 2) + 0xfe008c00)
+//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset)
+//Bit 30:22 din_offset (signed data)
+//Bit 21:14 map_coef (unsigned data)
+//Bit 13:10 map_sr (unsigned data)
+//Bit 9:1 dout_offset (signed data)
+//Bit 0 enable
+#define GE2D_SRC1_RANGE_MAP_CR_CTRL ((0x00e5 << 2) + 0xfe008c00)
+//Bit 21:16 src1 prearbitor burst number
+//Bit 13:8 src2 prearbitor burst number
+//Bit 5:0 dst prearbitor burst number
+#define GE2D_ARB_BURST_NUM ((0x00e6 << 2) + 0xfe008c00)
+//each 6bit ID, high 4bit are thread ID, low 2bits are the token
+//Bit 21:16 src1 ID
+//Bit 13:8 src2 ID
+//Bit 5:0 dst ID
+#define GE2D_TID_TOKEN ((0x00e7 << 2) + 0xfe008c00)
+//Bit 31:28 dst2_bytemask_val. 1-bit mask for each byte (8-bit). Applicable only if both dst_bitmask_en=1 and dst_bytemask_only=1.
+//Bit 27:26, dst2 picture struct, 00: frame, 10:top, 11: bottom
+//Bit 25:24, dst2 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 22:19 dst2 color_map
+// dst2_format=0 : output 8-bit;
+// dst2_format=1, dst2_color_map=1: output 16-bit YCbCr 655;
+// dst2_format=1, dst2_color_map=2: output 16-bit YCbCr 844;
+// dst2_format=1, dst2_color_map=3: output 16-bit YCbCrA 6442;
+// dst2_format=1, dst2_color_map=4: output 16-bit YCbCrA 4444;
+// dst2_format=1, dst2_color_map=5: output 16-bit YCbCr 565;
+// dst2_format=1, dst2_color_map=6: output 16-bit AYCbCr 4444;
+// dst2_format=1, dst2_color_map=7: output 16-bit AYCbCr 1555;
+// dst2_format=1, dst2_color_map=8: output 16-bit YCbCrA 4642;
+// dst2_format=1, dst2_color_map=9: output 16-bit CbCr 88;
+// dst2_format=1, dst2_color_map=10:output 16-bit CrCb 88;
+// dst2_format=2, dst2_color_map=0: output 24-bit YCbCr 888;
+// dst2_format=2, dst2_color_map=1: output 24-bit YCbCrA 5658;
+// dst2_format=2, dst2_color_map=2: output 24-bit AYCbCr 8565;
+// dst2_format=2, dst2_color_map=3: output 24-bit YCbCrA 6666;
+// dst2_format=2, dst2_color_map=4: output 24-bit AYCbCr 6666;
+// dst2_format=2, dst2_color_map=5: output 24-bit CrCbY 888;
+// dst2_format=3, dst2_color_map=0: output 32-bit YCbCrA 8888;
+// dst2_format=3, dst2_color_map=1: output 32-bit AYCbCr 8888;
+// dst2_format=3, dst2_color_map=2: output 32-bit ACrCbY 8888;
+// dst2_format=3, dst2_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 17:16 dst2_format, 00: 8bit, 01:16bit, 10:24bit, 11: 32bit
+//Bit 15 reserved
+//Bit 14 dst2_color_round_mode, 0: truncate, 1: + 0.5 rounding
+//Bit 13:12, dst2_x_discard_mode. 00: no discard; 10=discard even x; 11=discard odd x. Note: x is post reverse/rotation.
+//Bit 11:10, dst2_y_discard_mode. 00: no discard; 10=discard even y; 11=discard odd y. Note: y is post reverse/rotation.
+//Bit 9 reserved
+//Bit 8, dst2_enable. 0: disable dst2 (default); 1=enable dst2.
+//Bit 7: 6 reserved
+//Bit 5: 4, dst1_x_discard_mode. 00: no discard; 10=discard even x; 11=discard odd x. Note: x is post reverse/rotation.
+//Bit 3: 2, dst1_y_discard_mode. 00: no discard; 10=discard even y; 11=discard odd y. Note: y is post reverse/rotation.
+//Bit 1 reserved
+//Bit 0, dst1_enable. 0: disable dst1; 1=enable dst1 (default).
+#define GE2D_GEN_CTRL3 ((0x00e8 << 2) + 0xfe008c00)
+//Read only
+// Bit 13:0 ge2d_dst2_status, for debug only
+#define GE2D_STATUS2 ((0x00e9 << 2) + 0xfe008c00)
+//Bit 27:26 src1 Y fifo size control, 00: 512, 01: 256, 10: 128 11: 96
+//Bit 25:24 src2 fifo size control, 00: 512, 01: 256, 10: 128 11: 96
+//Bit 23:22 dst1 fifo size control, 00: 512, 01: 256, 10: 128 11: 64
+//Bit 21:20 dst2 fifo size control, 00: 512, 01: 256, 10: 128 11: 64
+//Bit 19:18, dst1 fifo burst control, 00: 24x64, 01: 32x64, 10: 48x64, 11:64x64
+//Bit 17:16, dst2 fifo burst control, 00: 24x64, 01: 32x64, 10: 48x64, 11:64x64
+//Bit 15:1, top_wrap_ctrl
+//bit 0, if true, disable bug fix about the dp_out_done/scale_out_done(test1823) hang issue when scaling down ratio is high.
+#define GE2D_GEN_CTRL4 ((0x00ea << 2) + 0xfe008c00)
+#define GE2D_GCLK_CTRL0 ((0x00ef << 2) + 0xfe008c00)
+#define GE2D_GCLK_CTRL1 ((0x00f0 << 2) + 0xfe008c00)
+#define GE2D_GEN_CTRL5 ((0x00f1 << 2) + 0xfe008c00)
+#define GE2D_DST1_BADDR_CTRL ((0x00f2 << 2) + 0xfe008c00)
+//Bit 31:0, dst1 base address in 64bits
+#define GE2D_DST1_STRIDE_CTRL ((0x00f3 << 2) + 0xfe008c00)
+//Bit 19:0, dst1 stride size in 64bits
+#define GE2D_DST2_BADDR_CTRL ((0x00f4 << 2) + 0xfe008c00)
+//Bit 31:0, dst1 base address in 64bits
+#define GE2D_DST2_STRIDE_CTRL ((0x00f5 << 2) + 0xfe008c00)
+//Bit 19:0, dst1 stride size in 64bits
+#define GE2D_SRC1_BADDR_CTRL_Y ((0x00f6 << 2) + 0xfe008c00)
+//Bit 31:0, src1 base address in 64bits
+#define GE2D_SRC1_STRIDE_CTRL_Y ((0x00f7 << 2) + 0xfe008c00)
+//Bit 19:0, src1 stride size in 64bits
+#define GE2D_SRC1_BADDR_CTRL_CB ((0x00f8 << 2) + 0xfe008c00)
+//Bit 31:0, src1 base address in 64bits
+#define GE2D_SRC1_STRIDE_CTRL_CB ((0x00f9 << 2) + 0xfe008c00)
+//Bit 19:0, src1 stride size in 64bits
+#define GE2D_SRC1_BADDR_CTRL_CR ((0x00fa << 2) + 0xfe008c00)
+//Bit 31:0, src1 base address in 64bits
+#define GE2D_SRC1_STRIDE_CTRL_CR ((0x00fb << 2) + 0xfe008c00)
+//Bit 19:0, src1 stride size in 64bits
+#define GE2D_SRC2_BADDR_CTRL ((0x00fc << 2) + 0xfe008c00)
+//Bit 31:0, src2 base address in 64bits
+#define GE2D_SRC2_STRIDE_CTRL ((0x00fd << 2) + 0xfe008c00)
+//Bit 19:0, src2 stride size in 64bits
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: ge2d_regs.h
+//
+//
+// Reading file: mipi_isp.h
+//
+//========================================================================
+// MIPI_ISP
+//========================================================================
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe023000
+// -----------------------------------------------
+#define MIPI_ADAPT_DDR_RD0_CNTL0 ((0x0000 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD0_CNTL1 ((0x0001 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD0_CNTL2 ((0x0002 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD0_CNTL3 ((0x0003 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD0_CNTL4 ((0x0004 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD0_ST0 ((0x0005 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD0_ST1 ((0x0006 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD0_ST2 ((0x0007 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD0_CNTL5 ((0x0008 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD0_CNTL6 ((0x0009 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_CNTL0 ((0x0010 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_CNTL1 ((0x0011 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_CNTL2 ((0x0012 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_CNTL3 ((0x0013 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_CNTL4 ((0x0014 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_ST0 ((0x0015 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_ST1 ((0x0016 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_ST2 ((0x0017 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_CNTL5 ((0x0018 << 2) + 0xfe023000)
+#define MIPI_ADAPT_DDR_RD1_CNTL6 ((0x0019 << 2) + 0xfe023000)
+#define MIPI_ADAPT_PIXEL0_CNTL0 ((0x0020 << 2) + 0xfe023000)
+#define MIPI_ADAPT_PIXEL0_CNTL1 ((0x0021 << 2) + 0xfe023000)
+#define MIPI_ADAPT_PIXEL1_CNTL0 ((0x0022 << 2) + 0xfe023000)
+#define MIPI_ADAPT_PIXEL1_CNTL1 ((0x0023 << 2) + 0xfe023000)
+#define MIPI_ADAPT_PIXEL0_ST0 ((0x002a << 2) + 0xfe023000)
+#define MIPI_ADAPT_PIXEL0_ST1 ((0x002b << 2) + 0xfe023000)
+#define MIPI_ADAPT_PIXEL1_ST0 ((0x002c << 2) + 0xfe023000)
+#define MIPI_ADAPT_PIXEL1_ST1 ((0x002d << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL0 ((0x0030 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL1 ((0x0031 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL2 ((0x0032 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL3 ((0x0033 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL4 ((0x0034 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL5 ((0x0035 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL6 ((0x0036 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL7 ((0x0037 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL8 ((0x0038 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL9 ((0x0039 << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_ST0 ((0x003a << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_ST1 ((0x003b << 2) + 0xfe023000)
+#define MIPI_ADAPT_ALIG_CNTL10 ((0x003c << 2) + 0xfe023000)
+#define MIPI_OTHER_CNTL0 ((0x0040 << 2) + 0xfe023000)
+#define MIPI_OTHER_CNTL1 ((0x0041 << 2) + 0xfe023000)
+#define MIPI_OTHER_CNTL2 ((0x0042 << 2) + 0xfe023000)
+#define MIPI_OTHER_CNTL3 ((0x0043 << 2) + 0xfe023000)
+#define MIPI_OTHER_CNTL4 ((0x0044 << 2) + 0xfe023000)
+#define MIPI_OTHER_ST0 ((0x004a << 2) + 0xfe023000)
+#define MIPI_OTHER_ST1 ((0x004b << 2) + 0xfe023000)
+#define DDR_RD0_LBUF_STATUS ((0x0050 << 2) + 0xfe023000)
+#define DDR_RD1_LBUF_STATUS ((0x0051 << 2) + 0xfe023000)
+#define MIPI_ADAPT_IRQ_MASK0 ((0x0060 << 2) + 0xfe023000)
+#define MIPI_ADAPT_IRQ_PENDING0 ((0x0061 << 2) + 0xfe023000)
+#define MIPI_ADAPT_IRQ_MASK1 ((0x0062 << 2) + 0xfe023000)
+#define MIPI_ADAPT_IRQ_PENDING1 ((0x0063 << 2) + 0xfe023000)
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe023800
+// -----------------------------------------------
+#define MIPI_ISP_RDARB_MODE ((0x0000 << 2) + 0xfe023800)
+#define MIPI_ISP_RDARB_REQEN_SLV ((0x0001 << 2) + 0xfe023800)
+#define MIPI_ISP_RDARB_WEIGH0_SLV ((0x0002 << 2) + 0xfe023800)
+#define MIPI_ISP_RDARB_WEIGH1_SLV ((0x0003 << 2) + 0xfe023800)
+#define MIPI_ISP_RDARB_UGT ((0x0004 << 2) + 0xfe023800)
+#define MIPI_ISP_RDARB_LIMT0 ((0x0005 << 2) + 0xfe023800)
+#define MIPI_ISP_WRARB_MODE ((0x0006 << 2) + 0xfe023800)
+#define MIPI_ISP_WRARB_REQEN_SLV ((0x0007 << 2) + 0xfe023800)
+#define MIPI_ISP_WRARB_WEIGH0_SLV ((0x0008 << 2) + 0xfe023800)
+#define MIPI_ISP_WRARB_WEIGH1_SLV ((0x0009 << 2) + 0xfe023800)
+#define MIPI_ISP_WRARB_UGT ((0x000a << 2) + 0xfe023800)
+#define MIPI_ISP_RDWR_ARB_STATUS ((0x000b << 2) + 0xfe023800)
+#define MIPI_ISP_ARB_DBG_CTRL ((0x000c << 2) + 0xfe023800)
+#define MIPI_ISP_ARB_DBG_STAT ((0x000d << 2) + 0xfe023800)
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe023a00
+// -----------------------------------------------
+#define ISP_DMA_BUS_CNTL ((0x0000 << 2) + 0xfe023a00)
+#define ISP_DMA_CTL0 ((0x0001 << 2) + 0xfe023a00)
+#define ISP_DMA_SRC_ADDR0 ((0x0002 << 2) + 0xfe023a00)
+#define ISP_DMA_DST_ADDR0 ((0x0003 << 2) + 0xfe023a00)
+#define ISP_DMA_CTL_TASK0 ((0x0004 << 2) + 0xfe023a00)
+#define ISP_DMA_SRC_ADDR1 ((0x0005 << 2) + 0xfe023a00)
+#define ISP_DMA_DST_ADDR1 ((0x0006 << 2) + 0xfe023a00)
+#define ISP_DMA_CTL_TASK1 ((0x0007 << 2) + 0xfe023a00)
+#define ISP_DMA_SRC_ADDR2 ((0x0008 << 2) + 0xfe023a00)
+#define ISP_DMA_DST_ADDR2 ((0x0009 << 2) + 0xfe023a00)
+#define ISP_DMA_CTL_TASK2 ((0x000a << 2) + 0xfe023a00)
+#define ISP_DMA_SRC_ADDR3 ((0x000b << 2) + 0xfe023a00)
+#define ISP_DMA_DST_ADDR3 ((0x000c << 2) + 0xfe023a00)
+#define ISP_DMA_CTL_TASK3 ((0x000d << 2) + 0xfe023a00)
+#define ISP_DMA_SRC_ADDR4 ((0x000e << 2) + 0xfe023a00)
+#define ISP_DMA_DST_ADDR4 ((0x000f << 2) + 0xfe023a00)
+#define ISP_DMA_CTL_TASK4 ((0x0010 << 2) + 0xfe023a00)
+#define ISP_DMA_SRC_ADDR5 ((0x0011 << 2) + 0xfe023a00)
+#define ISP_DMA_DST_ADDR5 ((0x0012 << 2) + 0xfe023a00)
+#define ISP_DMA_CTL_TASK5 ((0x0013 << 2) + 0xfe023a00)
+#define ISP_DMA_SRC_ADDR6 ((0x0014 << 2) + 0xfe023a00)
+#define ISP_DMA_DST_ADDR6 ((0x0015 << 2) + 0xfe023a00)
+#define ISP_DMA_CTL_TASK6 ((0x0016 << 2) + 0xfe023a00)
+#define ISP_DMA_SRC_ADDR7 ((0x0017 << 2) + 0xfe023a00)
+#define ISP_DMA_DST_ADDR7 ((0x0018 << 2) + 0xfe023a00)
+#define ISP_DMA_CTL_TASK7 ((0x0019 << 2) + 0xfe023a00)
+#define ISP_DMA_ST0 ((0x001a << 2) + 0xfe023a00)
+#define ISP_DMA_ST1 ((0x001b << 2) + 0xfe023a00)
+#define ISP_DMA_ST2 ((0x001c << 2) + 0xfe023a00)
+#define ISP_DMA_ST3 ((0x001d << 2) + 0xfe023a00)
+#define ISP_DMA_ST4 ((0x001e << 2) + 0xfe023a00)
+#define ISP_DMA_ST5 ((0x001f << 2) + 0xfe023a00)
+#define ISP_DMA_ST6 ((0x0020 << 2) + 0xfe023a00)
+// -----------------------------------------------
+// APB_BASE: APB0_BASE_ADDR = 0xfe023c00
+// -----------------------------------------------
+#define MIPI_BL_FR_PING_ADDR0_ST ((0x0000 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_PING_ADDR0_ED ((0x0001 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_PING_ADDR1_ST ((0x0002 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_PING_ADDR1_ED ((0x0003 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_PONG_ADDR0_ST ((0x0004 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_PONG_ADDR0_ED ((0x0005 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_PONG_ADDR1_ST ((0x0006 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_PONG_ADDR1_ED ((0x0007 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_FRAME_TH ((0x0008 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_FRAME_BUFFER_START_ADDR0 ((0x0009 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_FRAME_SIZE0 ((0x000a << 2) + 0xfe023c00)
+#define MIPI_BL_FR_FRAME_BUF_SIZE0 ((0x000b << 2) + 0xfe023c00)
+#define MIPI_BL_FR_FRAME_BUFFER_START_ADDR1 ((0x000c << 2) + 0xfe023c00)
+#define MIPI_BL_FR_FRAME_SIZE1 ((0x000d << 2) + 0xfe023c00)
+#define MIPI_BL_FR_FRAME_BUF_SIZE1 ((0x000e << 2) + 0xfe023c00)
+#define MIPI_BL_FR_CTRL0 ((0x000f << 2) + 0xfe023c00)
+#define MIPI_BL_FR_CTRL1 ((0x0010 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_FRAME_COUNT ((0x0011 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_AWADDR_O ((0x0012 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_AWADDR_I ((0x0013 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_STAT0 ((0x0014 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_STAT1 ((0x0015 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_STAT2 ((0x0016 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_STAT3 ((0x0017 << 2) + 0xfe023c00)
+#define MIPI_BL_FR_FRAME_BUFFER_START_ADDR0P ((0x0018 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_PING_ADDR0_ST ((0x0020 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_PING_ADDR0_ED ((0x0021 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_PING_ADDR1_ST ((0x0022 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_PING_ADDR1_ED ((0x0023 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_PONG_ADDR0_ST ((0x0024 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_PONG_ADDR0_ED ((0x0025 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_PONG_ADDR1_ST ((0x0026 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_PONG_ADDR1_ED ((0x0027 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_FRAME_TH ((0x0028 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_FRAME_BUFFER_START_ADDR0 ((0x0029 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_FRAME_SIZE0 ((0x002a << 2) + 0xfe023c00)
+#define MIPI_BL_DS_FRAME_BUF_SIZE0 ((0x002b << 2) + 0xfe023c00)
+#define MIPI_BL_DS_FRAME_BUFFER_START_ADDR1 ((0x002c << 2) + 0xfe023c00)
+#define MIPI_BL_DS_FRAME_SIZE1 ((0x002d << 2) + 0xfe023c00)
+#define MIPI_BL_DS_FRAME_BUF_SIZE1 ((0x002e << 2) + 0xfe023c00)
+#define MIPI_BL_DS_CTRL0 ((0x002f << 2) + 0xfe023c00)
+#define MIPI_BL_DS_CTRL1 ((0x0030 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_FRAME_COUNT ((0x0031 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_AWADDR_O ((0x0032 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_AWADDR_I ((0x0033 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_STAT0 ((0x0034 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_STAT1 ((0x0035 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_STAT2 ((0x0036 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_STAT3 ((0x0037 << 2) + 0xfe023c00)
+#define MIPI_BL_DS_FRAME_BUFFER_START_ADDR0P ((0x0038 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_PING_ADDR0_ST ((0x0040 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_PING_ADDR0_ED ((0x0041 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_PING_ADDR1_ST ((0x0042 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_PING_ADDR1_ED ((0x0043 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_PONG_ADDR0_ST ((0x0044 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_PONG_ADDR0_ED ((0x0045 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_PONG_ADDR1_ST ((0x0046 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_PONG_ADDR1_ED ((0x0047 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_FRAME_TH ((0x0048 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_FRAME_BUFFER_START_ADDR0 ((0x0049 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_FRAME_SIZE0 ((0x004a << 2) + 0xfe023c00)
+#define MIPI_BL_WF_FRAME_BUF_SIZE0 ((0x004b << 2) + 0xfe023c00)
+#define MIPI_BL_WF_FRAME_BUFFER_START_ADDR1 ((0x004c << 2) + 0xfe023c00)
+#define MIPI_BL_WF_FRAME_SIZE1 ((0x004d << 2) + 0xfe023c00)
+#define MIPI_BL_WF_FRAME_BUF_SIZE1 ((0x004e << 2) + 0xfe023c00)
+#define MIPI_BL_WF_CTRL0 ((0x004f << 2) + 0xfe023c00)
+#define MIPI_BL_WF_CTRL1 ((0x0050 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_FRAME_COUNT ((0x0051 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_AWADDR_O ((0x0052 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_AWADDR_I ((0x0053 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_STAT0 ((0x0054 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_STAT1 ((0x0055 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_STAT2 ((0x0056 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_STAT3 ((0x0057 << 2) + 0xfe023c00)
+#define MIPI_BL_WF_FRAME_BUFFER_START_ADDR0P ((0x0058 << 2) + 0xfe023c00)
+//
+// Closing file: mipi_isp.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: ./REG_LIST_RTL.h
+//
+#include "soc_def.h"
+#endif // REGISTER_H
+
diff --git a/arch/arm/include/asm/arch-c2/regs.h b/arch/arm/include/asm/arch-c2/regs.h
new file mode 100644
index 0000000..d8e58b4
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/regs.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AML_REG_H__
+#define __AML_REG_H__
+/*
+ * all used regs
+ */
+/*
+#define SYSCTRL_TIMERE_CTRL ((0x0040 << 2) + 0xfe005800)
+#define RESETCTRL_WATCHDOG_CTRL0 ((0x0040 << 2) + 0xfe000000)
+#define RESETCTRL_WATCHDOG_CTRL1 ((0x0041 << 2) + 0xfe000000)
+#define RESETCTRL_WATCHDOG_CNT ((0x0042 << 2) + 0xfe000000)
+#define RESETCTRL_WATCHDOG_CLR ((0x0043 << 2) + 0xfe000000)
+ */
+#define ISA_TIMERE ((0x0041 << 2) + 0xfe005800)
+#define WATCHDOG_CNTL ((0x0040 << 2) + 0xfe000000)
+#define WATCHDOG_TCNT ((0x0042 << 2) + 0xfe000000)
+#define WATCHDOG_RST ((0x0043 << 2) + 0xfe000000)
+
+/*
+ * SEC_AO_SEC_GP_CFG0 use SYSCTRL_SEC_STATUS_REG4
+ * AO_SEC_GP_CFG0 use SYSCTRL_SEC_STATUS_REG4
+ * AO_RTI_STATUS_REG3 use SYSCTRL_SEC_STICKY_REG1
+ * AO_SEC_SD_CFG15 use SYSCTRL_SEC_STATUS_REG2
+ */
+#define AO_SEC_GP_CFG0 ((0x00c4 << 2) + 0xfe005800)
+#define AO_RTI_STATUS_REG3 ((0x00e1 << 2) + 0xfe005800)
+#define AO_SEC_SD_CFG15 ((0x00c2 << 2) + 0xfe005800)
+
+/* PREG_STICKY_REG8 use SYSCTRL_STICKY_REG7
+ * P_AO_SEC_GP_CFG12 use SYSCTRL_DEBUG_REG6
+ * P_AO_SEC_GP_CFG13 use SYSCTRL_DEBUG_REG7
+ */
+#define PREG_STICKY_REG8 ((0x00b7 << 2) + 0xfe005800)
+#define P_AO_SEC_GP_CFG12 (volatile uint32_t *)((0x0096 << 2) + 0xfe005800)
+#define P_AO_SEC_GP_CFG13 (volatile uint32_t *)((0x0097 << 2) + 0xfe005800)
+
+/*
+ * P_AO_RTI_PINMUX_REG0 use PADCTRL_PIN_MUX_REG0
+ * P_AO_TIMEBASE_CNTL1 use CLKTREE_TIMEBASE_CTRL1
+ * AO_UART_WFIFO use UART_B_WFIFO
+ */
+#define P_AO_RTI_PINMUX_REG0 ((0x0000 << 2) + 0xfe000400)
+#define P_AO_TIMEBASE_CNTL1 ((0x0016 << 2) + 0xfe000800)
+#define AO_UART_WFIFO ((0x0000 << 2) + 0xfe002000)
+
+/*
+ * Not AO watch dog
+ */
+#define P_WATCHDOG_CNTL (volatile uint32_t *)(WATCHDOG_CNTL)
+#define P_WATCHDOG_TCNT (volatile uint32_t *)(WATCHDOG_TCNT)
+#define P_WATCHDOG_RST (volatile uint32_t *)(WATCHDOG_RST)
+#define P_ISA_TIMERE (volatile uint32_t *)(ISA_TIMERE)
+
+#endif /* __AML_REG_H__ */
diff --git a/arch/arm/include/asm/arch-c2/romboot.h b/arch/arm/include/asm/arch-c2/romboot.h
new file mode 100644
index 0000000..2967fbb
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/romboot.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOOT_ROM_H_
+#define __BOOT_ROM_H_
+#ifndef __ASSEMBLY__
+//#include <stdint.h>
+//uint8_t simple_i2c(uint8_t adr);
+//void spi_pin_mux(void);
+//void spi_init(void);
+//uint32_t spi_read(uint32_t src, uint32_t mem, uint32_t size);
+//void udelay(uint32_t usec);
+//void boot_des_decrypt(uint8_t *ct, uint8_t *pt, uint32_t size);
+
+#endif /* ! __ASSEMBLY__ */
+#include "config.h"
+
+/* Magic number to "boot" up A53 */
+#define AO_SEC_SD_CFG10_CB 0x80000000
+
+/*BOOT device and ddr size*/
+/*31-28: boot device id, 27-24: boot device para, 23-20: reserved*/
+/*19-8: ddr size, 7-0: board revision*/
+//#define P_AO_SEC_GP_CFG0 0xDA100240 //defined in secure_apb.h
+#define AO_SEC_GP_CFG7_W0_BIT 8
+#define AO_SEC_GP_CFG7_W0 0x100
+
+#define BOOT_ID_RESERVED 0
+#define BOOT_ID_EMMC 1
+#define BOOT_ID_NAND 2
+#define BOOT_ID_SPI 3
+#define BOOT_ID_SDCARD 4
+#define BOOT_ID_USB 5
+
+#endif /* __BOOT_ROM_H_ */
diff --git a/arch/arm/include/asm/arch-c2/sd_emmc.h b/arch/arm/include/asm/arch-c2/sd_emmc.h
new file mode 100644
index 0000000..82d4fb2
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/sd_emmc.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __SD_EMMC_H__
+#define __SD_EMMC_H__
+
+#include <mmc.h>
+
+#define SDIO_PORT_A 0
+#define SDIO_PORT_B 1
+#define SDIO_PORT_C 2
+
+#define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */
+#define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */
+
+#define MESON_SD_EMMC_CLOCK 0x00
+#define CLK_MAX_DIV GENMASK(5, 0)
+#define CLK_MAX_SRC GENMASK(7, 6)
+#define Cfg_div 0
+#define Cfg_src 6
+#define Cfg_co_phase 8
+#define Cfg_tx_phase 10
+#define Cfg_rx_phase 12
+#define Cfg_sram_pd 14
+#define Cfg_tx_delay 16
+#define Cfg_rx_delay 22
+#define Cfg_always_on 28
+#define Cfg_irq_sdio_sleep 29
+#define Cfg_irq_sdio_sleep_ds 30
+
+#define MESON_SD_EMMC_DELAY1 0x4
+#define DLY_D0_MASK GENMASK(5, 0)
+#define DLY_D1_MASK GENMASK(11, 6)
+#define DLY_D2_MASK GENMASK(17, 12)
+#define DLY_D3_MASK GENMASK(23, 18)
+#define DLY_D4_MASK GENMASK(31, 24)
+#define Dly_d0 0
+#define Dly_d1 6
+#define Dly_d2 12
+#define Dly_d3 18
+#define Dly_d4 24
+
+#define MESON_SD_EMMC_DELAY2 0x8
+#define DLY_D5_MASK GENMASK(5, 0)
+#define DLY_D6_MASK GENMASK(11, 6)
+#define DLY_D7_MASK GENMASK(17, 12)
+#define DLY_D8_MASK GENMASK(23, 18)
+#define DLY_D9_MASK GENMASK(31, 24)
+#define Dly_d5 0
+#define Dly_d6 6
+#define Dly_d7 12
+#define Dly_d8 18
+#define Dly_d9 24
+
+#define MESON_SD_EMMC_ADJUST 0xC
+#define CALI_SEL_MASK GENMASK(11, 8)
+#define ADJ_DLY_MASK GENMASK(21, 16)
+#define Cfg_cali_sel 8
+#define Cfg_cali_en 12
+#define Cfg_adj_en 13
+#define Cfg_cali_rise 14
+#define Cfg_ds_en 15
+#define Cfg_adj_dly 16
+#define Cfg_adj_auto 22
+#define Cfg_adj_init 23
+
+#define MESON_SD_EMMC_START 0x40
+#define CFG_DESC_INIT BIT(0)
+#define CFG_DESC_BUSY BIT(1)
+#define CFG_DESC_ADDR 2
+
+#define MESON_SD_EMMC_CFG 0x44
+#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
+#define CFG_BUS_WIDTH_1 0
+#define CFG_BUS_WIDTH_4 1
+#define CFG_BUS_WIDTH_8 2
+#define CFG_DDR BIT(2)
+#define CFG_BL_LEN_MASK GENMASK(7, 4)
+#define CFG_BL_LEN_SHIFT 4
+#define CFG_BL_LEN_512 (9 << 4)
+#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
+#define CFG_RESP_TIMEOUT_256 (8 << 8)
+#define CFG_RC_CC_MASK GENMASK(15, 12)
+#define CFG_RC_CC_16 (4 << 12)
+#define CFG_SDCLK_ALWAYS_ON BIT(18)
+#define CFG_AUTO_CLK BIT(23)
+
+#define MESON_SD_EMMC_STATUS 0x48
+#define STATUS_MASK GENMASK(15, 0)
+#define STATUS_ERR_MASK GENMASK(12, 0)
+#define STATUS_RXD_ERR_MASK GENMASK(7, 0)
+#define STATUS_TXD_ERR BIT(8)
+#define STATUS_DESC_ERR BIT(9)
+#define STATUS_RESP_ERR BIT(10)
+#define STATUS_RESP_TIMEOUT BIT(11)
+#define STATUS_DESC_TIMEOUT BIT(12)
+#define STATUS_END_OF_CHAIN BIT(13)
+
+#define MESON_SD_EMMC_IRQ_EN 0x4c
+
+#define MESON_SD_EMMC_CMD_CFG 0x50
+#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
+#define CMD_CFG_BLOCK_MODE BIT(9)
+#define CMD_CFG_R1B BIT(10)
+#define CMD_CFG_END_OF_CHAIN BIT(11)
+#define CMD_CFG_TIMEOUT_4S (12 << 12)
+#define CMD_CFG_NO_RESP BIT(16)
+#define CMD_CFG_NO_CMD BIT(17)
+#define CMD_CFG_DATA_IO BIT(18)
+#define CMD_CFG_DATA_WR BIT(19)
+#define CMD_CFG_RESP_NOCRC BIT(20)
+#define CMD_CFG_RESP_128 BIT(21)
+#define CMD_CFG_RESP_NUM BIT(22)
+#define CMD_CFG_DATA_NUM BIT(23)
+#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
+#define CMD_CFG_CMD_INDEX_SHIFT 24
+#define CMD_CFG_ERR BIT(30)
+#define CMD_CFG_OWNER BIT(31)
+
+#define MESON_SD_EMMC_CMD_ARG 0x54
+#define MESON_SD_EMMC_CMD_DAT 0x58
+#define MESON_SD_EMMC_CMD_RSP 0x5c
+#define MESON_SD_EMMC_CMD_RSP1 0x60
+#define MESON_SD_EMMC_CMD_RSP2 0x64
+#define MESON_SD_EMMC_CMD_RSP3 0x68
+
+#define SD_EMMC_RXD_ERROR (1 << 0)
+#define SD_EMMC_TXD_ERROR (1 << 1)
+#define SD_EMMC_DESC_ERROR (1 << 2)
+#define SD_EMMC_RESP_CRC_ERROR (1 << 3)
+#define SD_EMMC_RESP_TIMEOUT_ERROR (1 << 4)
+#define SD_EMMC_DESC_TIMEOUT_ERROR (1 << 5)
+
+//boot from sd or emmc
+#define SEC_AO_SEC_GP_CFG0 (SYSCTRL_SEC_STATUS_REG4)
+#endif
diff --git a/arch/arm/include/asm/arch-c2/secure_apb.h b/arch/arm/include/asm/arch-c2/secure_apb.h
new file mode 100644
index 0000000..48bbb47
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/secure_apb.h
@@ -0,0 +1,38 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/regs.h>
+#include <asm/arch/register.h>
+
+#define DMA_T0 (uint32_t)(0xfe006000 + 0x00)
+#define DMA_T1 (uint32_t)(0xfe006000 + 0x04)
+#define DMA_T2 (uint32_t)(0xfe006000 + 0x08)
+#define DMA_T3 (uint32_t)(0xfe006000 + 0x0c)
+#define DMA_T4 (uint32_t)(0xfe006000 + 0x10)
+#define DMA_T5 (uint32_t)(0xfe006000 + 0x14)
+#define DMA_STS0 (uint32_t)(0xfe006000 + 0x20)
+#define DMA_STS1 (uint32_t)(0xfe006000 + 0x24)
+#define DMA_STS2 (uint32_t)(0xfe006000 + 0x28)
+#define DMA_STS3 (uint32_t)(0xfe006000 + 0x2c)
+#define DMA_STS4 (uint32_t)(0xfe006000 + 0x30)
+#define DMA_STS5 (uint32_t)(0xfe006000 + 0x34)
+#define DMA_CFG (uint32_t)(0xfe006000 + 0x40)
+#define DMA_SEC (uint32_t)(0xfe006000 + 0x44)
+#define DMA_END (uint32_t)(0xfe006000 + 0x3ff)
+
+#define P_DMA_T0 (volatile uint32_t *)(0xfe006000 + 0x00)
+#define P_DMA_T1 (volatile uint32_t *)(0xfe006000 + 0x04)
+#define P_DMA_T2 (volatile uint32_t *)(0xfe006000 + 0x08)
+#define P_DMA_T3 (volatile uint32_t *)(0xfe006000 + 0x0c)
+#define P_DMA_T4 (volatile uint32_t *)(0xfe006000 + 0x10)
+#define P_DMA_T5 (volatile uint32_t *)(0xfe006000 + 0x14)
+#define P_DMA_STS0 (volatile uint32_t *)(0xfe006000 + 0x20)
+#define P_DMA_STS1 (volatile uint32_t *)(0xfe006000 + 0x24)
+#define P_DMA_STS2 (volatile uint32_t *)(0xfe006000 + 0x28)
+#define P_DMA_STS3 (volatile uint32_t *)(0xfe006000 + 0x2c)
+#define P_DMA_STS4 (volatile uint32_t *)(0xfe006000 + 0x30)
+#define P_DMA_STS5 (volatile uint32_t *)(0xfe006000 + 0x34)
+#define P_DMA_CFG (volatile uint32_t *)(0xfe006000 + 0x40)
+#define P_DMA_SEC (volatile uint32_t *)(0xfe006000 + 0x44)
diff --git a/arch/arm/include/asm/arch-c2/soc_def.h b/arch/arm/include/asm/arch-c2/soc_def.h
new file mode 100644
index 0000000..3a1af9a
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/soc_def.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __C2_DEF_H__
+#define __C2_DEF_H__
+
+#define SEC_AO_SEC_GP_CFG2 (SYSCTRL_SEC_STATUS_REG6)
+
+#endif /* __C2_DEF_H__ */
diff --git a/arch/arm/include/asm/arch-c2/timer.h b/arch/arm/include/asm/arch-c2/timer.h
new file mode 100644
index 0000000..492cc8d
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/timer.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __TIMER_H
+#define __TIMER_H
+
+#include <asm/arch/romboot.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/io.h>
+
+/**
+ * Get the current timestamp from the system timer.
+ */
+uint32_t get_time(void);
+
+/**
+ * Busy-wait.
+ *
+ * @param us Number of microseconds to delay.
+ */
+void _udelay(unsigned int us);
+
+#endif /* __TIMER_H */
diff --git a/arch/arm/include/asm/arch-c2/timing.h b/arch/arm/include/asm/arch-c2/timing.h
new file mode 100644
index 0000000..9934337
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/timing.h
@@ -0,0 +1,336 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AML_TIMING_H_
+#define __AML_TIMING_H_
+
+#include <asm/arch/ddr_define.h>
+//#include <asm/arch/types.h>
+
+#define BL2_INIT_STAGE_0 0
+#define BL2_INIT_STAGE_1 1
+#define BL2_INIT_STAGE_2 2
+#define BL2_INIT_STAGE_3 3
+#define BL2_INIT_STAGE_4 4
+#define BL2_INIT_STAGE_5 5
+#define BL2_INIT_STAGE_6 6
+#define BL2_INIT_STAGE_7 7
+#define BL2_INIT_STAGE_8 8
+#define BL2_INIT_STAGE_9 9
+
+#define BL2_INIT_STAGE_PWM_PRE_INIT 0x81
+#define BL2_INIT_STAGE_PWM_CHK_HW 0x82
+#define BL2_INIT_STAGE_PWM_CFG_GROUP 0x83
+#define BL2_INIT_STAGE_PWM_INIT 0xC0
+
+typedef struct bl2_reg {
+ unsigned int reg;
+ unsigned int value;
+ unsigned int mask;
+ unsigned short udelay;
+ unsigned char flag;
+ unsigned char rsv_0;
+}__attribute__ ((packed)) bl2_reg_t;
+
+typedef struct ddr_reg {
+ unsigned int reg;
+ unsigned int value;
+ unsigned int mask;
+ unsigned short udelay;
+ unsigned char flag;
+ unsigned char rsv_0;
+}__attribute__ ((packed)) ddr_reg_t;
+
+typedef struct training_delay_set_ps{
+ unsigned char ac_trace_delay[10];
+ unsigned char ac_trace_delay_rev[2];
+ unsigned char read_dqs_delay[16];
+ unsigned char read_dq_bit_delay[72];
+ unsigned short write_dqs_delay[16];
+// */
+ unsigned short write_dq_bit_delay[72];
+ unsigned short read_dqs_gate_delay[16];
+ unsigned char soc_bit_vref[36];
+ unsigned char dram_bit_vref[32];
+ ///*
+ unsigned char rever1;//read_dqs read_dq,write_dqs, write_dq
+ unsigned char dfi_mrl;
+ unsigned char dfi_hwtmrl;
+ unsigned char ARdPtrInitVal;
+ unsigned short csr_vrefinglobal;
+ unsigned short csr_dqsrcvcntrl[4];
+ unsigned short csr_pptdqscntinvtrntg0[4];
+ unsigned short csr_pptdqscntinvtrntg1[4];
+ unsigned short csr_seq0bgpr[9];
+ unsigned short csr_dllgainctl;
+ unsigned short csr_dlllockpara;
+// unsigned short rever2;
+}__attribute__ ((packed)) training_delay_set_ps_t;
+
+typedef struct ddr_mrs_reg {
+ unsigned int cfg_ddr_mr[8];
+ unsigned int cfg_ddr_mr11;
+ unsigned int cfg_ddr_mr12;
+ unsigned int cfg_ddr_mr13;
+ unsigned int cfg_ddr_mr14;
+ unsigned int cfg_ddr_mr16;
+ unsigned int cfg_ddr_mr17;
+ unsigned int cfg_ddr_mr22;
+ unsigned int cfg_ddr_mr24;
+}__attribute__ ((packed)) ddr_mrs_reg_t;
+
+typedef struct ddr_timing{
+ unsigned int identifier;
+ unsigned int cfg_ddr_mrd;
+ unsigned int cfg_ddr_rfcab;
+ unsigned int cfg_ddr_rfcpb;
+ unsigned int cfg_ddr_rpab;
+ unsigned int cfg_ddr_rppb;
+ unsigned int cfg_ddr_rtw;
+ unsigned int cfg_ddr_rl;
+ unsigned int cfg_ddr_wl;
+ unsigned int cfg_ddr_ras;
+ unsigned int cfg_ddr_rc;
+ unsigned int cfg_ddr_rcd;
+ unsigned int cfg_ddr_rrds;
+ unsigned int cfg_ddr_rrdl;
+ unsigned int cfg_ddr_faw;
+ unsigned int cfg_ddr_rtp;
+ unsigned int cfg_ddr_wr;
+ unsigned int cfg_ddr_wtrs;
+ unsigned int cfg_ddr_wtrl;
+ unsigned int cfg_ddr_ccds;
+ unsigned int cfg_ddr_ccdl;
+ unsigned int cfg_ddr_exsr;
+ unsigned int cfg_ddr_xs;
+ unsigned int cfg_ddr_xp;
+ unsigned int cfg_ddr_xpdll;
+ unsigned int cfg_ddr_zqcs;
+ unsigned int cfg_ddr_cksre;
+ unsigned int cfg_ddr_cksrx;
+ unsigned int cfg_ddr_cke;
+ unsigned int cfg_ddr_mod;
+ unsigned int cfg_ddr_dqs;
+ unsigned int cfg_ddr_rstl;
+ unsigned int cfg_ddr_zqlat;
+ unsigned int cfg_ddr_mrr;
+ unsigned int cfg_ddr_ckesr;
+ unsigned int cfg_ddr_dpd;
+ unsigned int cfg_ddr_ckeck;
+ unsigned int cfg_ddr_refi;
+ unsigned int cfg_ddr_sr;
+ unsigned int cfg_ddr_ccdmw;
+ unsigned int cfg_ddr_escke;
+ unsigned int cfg_ddr_refi_ddr3;
+ unsigned int cfg_ddr_dfictrldelay;
+ unsigned int cfg_ddr_dfiphywrdata;
+ unsigned int cfg_ddr_dfiphywrlat;
+ unsigned int cfg_ddr_dfiphyrddataen;
+ unsigned int cfg_ddr_dfiphyrdlat;
+ unsigned int cfg_ddr_dfictrlupdmin;
+ unsigned int cfg_ddr_dfictrlupdmax;
+ unsigned int cfg_ddr_dfimstrresp;
+ unsigned int cfg_ddr_dfirefmski;
+ unsigned int cfg_ddr_dfictrlupdi;
+ unsigned int cfg_ddr_dfidramclk;
+ unsigned int cfg_ddr_dfilpresp;
+ unsigned int cfg_ddr_dfiphymstr;
+ unsigned int cfg_ddr_rtodt;
+ unsigned int cfg_ddr_wlmrd;
+ unsigned int cfg_ddr_wlo;
+ unsigned int cfg_ddr_al;
+ unsigned int cfg_ddr_zqcl;
+ unsigned int cfg_ddr_zqcsi;
+ unsigned int cfg_ddr_zqreset;
+ unsigned int cfg_ddr_tdqsck_min;
+ unsigned int cfg_ddr_tdqsck_max;
+ //training_delay_set_ps_t cfg_ddr_training_delay_ps;
+ ddr_mrs_reg_t cfg_ddr_mrs_reg_ps[2];
+ unsigned int dfi_odt1_config_ps[2];
+ //ddr_mrs_reg_t cfg_ddr_mrs_reg_ps1;
+ #if 0
+ unsigned int cfg_ddr_mr[8];
+ unsigned int cfg_ddr_mr11;
+ unsigned int cfg_ddr_mr12;
+ unsigned int cfg_ddr_mr13;
+ unsigned int cfg_ddr_mr14;
+ unsigned int cfg_ddr_mr16;
+ unsigned int cfg_ddr_mr17;
+ unsigned int cfg_ddr_mr22;
+ unsigned int cfg_ddr_mr24;
+ unsigned int cfg_ddr_reserve[5];
+ #endif
+}__attribute__ ((packed)) ddr_timing_t;
+
+typedef struct board_common_setting
+{
+unsigned int timming_magic;
+unsigned short timming_max_valid_configs;
+unsigned short timming_struct_version;
+unsigned short timming_struct_org_size;
+unsigned short timming_struct_real_size;
+unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test enable
+unsigned int ddr_func;
+unsigned char board_id;
+unsigned char DramType;
+unsigned char dram_rank_config;
+unsigned char DisabledDbyte;
+unsigned int dram_cs0_base_add;
+unsigned int dram_cs1_base_add;
+unsigned short dram_cs0_size_MB;
+unsigned short dram_cs1_size_MB;
+unsigned char dram_x4x8x16_mode;
+unsigned char Is2Ttiming;
+unsigned char log_level;
+unsigned char ddr_rdbi_wr_enable;
+unsigned int pll_ssc_mode;
+unsigned short org_tdqs2dq;
+unsigned char reserve1_test_function[2];
+unsigned int ddr_dmc_remap[5];
+unsigned char ac_pinmux[35];
+unsigned char ddr_dqs_swap;
+unsigned char ddr_dq_remap[36];
+unsigned int ddr_vddee_setting[4];//add,default-value,default-voltage,step
+}__attribute__ ((packed)) board_common_setting_t;
+typedef struct board_SI_setting_ps
+{
+unsigned short DRAMFreq;
+unsigned char PllBypassEn;
+unsigned char training_SequenceCtrl;
+unsigned short ddr_odt_config;
+unsigned char clk_drv_ohm;
+unsigned char cs_drv_ohm;
+unsigned char ac_drv_ohm;
+unsigned char soc_data_drv_ohm_p;
+unsigned char soc_data_drv_ohm_n;
+unsigned char soc_data_odt_ohm_p;
+unsigned char soc_data_odt_ohm_n;
+unsigned char dram_data_drv_ohm;
+unsigned char dram_data_odt_ohm;
+unsigned char dram_data_wr_odt_ohm;
+unsigned char dram_ac_odt_ohm;
+unsigned char dram_data_drv_pull_up_calibration_ohm;
+unsigned char lpddr4_dram_vout_voltage_range_setting;
+unsigned char reserve2;
+unsigned short vref_ac_permil; //phy
+unsigned short vref_soc_data_permil; //soc
+unsigned short vref_dram_data_permil;
+unsigned short max_core_timmming_frequency;
+unsigned short training_phase_parameter[2];
+unsigned short ac_trace_delay_org[36];
+}__attribute__ ((packed)) board_SI_setting_ps_t;
+typedef struct board_phase_setting_ps
+{
+unsigned short ac_trace_delay[36];
+unsigned short write_dqs_delay[8];
+unsigned short write_dq_bit_delay[72];
+unsigned short read_dqs_gate_delay[8];
+unsigned char read_dqs_delay[8];
+unsigned char read_dq_bit_delay[72];
+unsigned char soc_bit_vref[44];
+unsigned char dram_bit_vref[36];
+unsigned char reserve_training_parameter[16];//0-7 read dqs offset,8-15 write dqs offset,MSB bit 7 use 0 mean right offset
+}__attribute__ ((packed)) board_phase_setting_ps_t;
+typedef struct ddr_set
+{
+board_common_setting_t cfg_board_common_setting;
+board_SI_setting_ps_t cfg_board_SI_setting_ps[2];
+board_phase_setting_ps_t cfg_ddr_training_delay_ps[2];
+}__attribute__ ((packed)) ddr_set_t;
+
+
+#if 0
+ #define DDR_FW_TOTAL_OFFSET 0
+ #define DDR_FW_TOTAL_SIZE 2
+ #define DDR_FW_TOTAL_VERSION 3
+ #define DDR_FW_BIN_OFFSET 4
+ #define DDR_FW_BIN_SIZE 6
+ #define DDR_FW_VERSION 7
+ #define DDR_ACS_BIN_OFFSET 8
+ #define DDR_ACS_BIN_SIZE 10
+ #define DDR_ACS_VERSION 11
+ #define DDR_FAST_BOOT_DATA_OFFSET 12
+ #define DDR_FAST_BOOT_DATA_SIZE 14
+ #define DDR_FAST_BOOT_DATA_VERSION 15
+ #define DDR_STICKY_REG_ADD_OFFSET 16
+ #define DDR_STICKY_REG_SIZE_OFFSET 18
+ #define DDR_STICKY_REG_VERSION_OFFSET 19
+
+ //#define DDR_FW_HEAD_SIZE (32<<2)//>96
+ //#define DDR_BL2_DDR_FW_HEAD_SIZE 256
+ typedef struct ddr_fw_head_struct{
+
+ uint32_t ddr_all_fw_add;
+ uint32_t ddr_all_fw_size;
+ uint32_t ddr_all_fw_version;
+
+ uint32_t ddr_fw_add;
+ uint32_t ddr_fw_size;
+ uint32_t ddr_fw_version;
+
+ uint32_t ddr_acs_bin_add;
+ uint32_t ddr_acs_bin_size;
+ uint32_t ddr_acs_bin_version;
+
+ uint32_t ddr_fast_boot_data_add;
+ uint32_t ddr_fast_boot_data_size;
+ uint32_t ddr_fast_boot_data_version;
+
+ uint32_t ddr_sticky_add;
+ uint32_t ddr_sticky_size;
+ uint32_t ddr_sticky_version;
+
+ //void (*log_info)(log_chl chl,const char *fmt, ...);
+ int (*serial_puts)(const char *s);
+ void (*serial_put_hex)(unsigned long data, int bitlen);
+ void (*ddr_init_return)(void);
+
+ uint32_t ddr_bl2_ddr_fw_mail_message[12];
+
+ } ddr_fw_head_struct_t;
+#endif
+typedef struct pll_ctrl {
+ unsigned short delay_u;
+ unsigned short flag;
+ unsigned int clkset;
+ unsigned int pll_para[10];
+ unsigned int reserve;
+
+}__attribute__ ((packed)) pll_ctrl_t;
+
+typedef struct pll_set_new {
+ pll_ctrl_t sys_pll_ctrl;
+ pll_ctrl_t fix_pll_cntl;
+ pll_ctrl_t gp0_pll_cntl;
+ pll_ctrl_t gp1_pll_cntl;
+ pll_ctrl_t hifi_pll_cntl;
+
+}__attribute__ ((packed)) pll_set_t_new;
+
+typedef struct pll_set{
+ unsigned short cpu_clk;
+ unsigned short pxp;
+ unsigned int spi_ctrl;
+ unsigned short vddee;
+ unsigned short vcck;
+ unsigned char szPad[4];
+
+ unsigned long long lCustomerID;
+ unsigned char debug_mode;
+ unsigned char log_chl;
+ unsigned char log_ctrl;
+ unsigned char ddr_timming_save_mode;
+ unsigned int nCFGTAddr;
+ /* align 8Byte */
+
+ pll_set_t_new pll_struct;
+}__attribute__ ((packed)) pll_set_t;
+
+typedef struct dwc_apb {
+ unsigned int addr;
+ unsigned short val;
+} dwc_apb_t;
+
+#endif //__AML_TIMING_H_
diff --git a/arch/arm/include/asm/arch-c2/tsensor.h b/arch/arm/include/asm/arch-c2/tsensor.h
new file mode 100644
index 0000000..c209b0c
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/tsensor.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __TSENSOR_H__
+#define __TSENSOR_H__
+
+
+struct tsensor_cali_data {
+ unsigned int cmd; /* R/W */
+ unsigned int offset;
+ unsigned int size;
+ unsigned long buffer_phy;
+ unsigned long retcnt_phy;
+};
+
+
+#define CONFIG_HIGH_TEMP_COOL 90
+
+#define T_AVG_NUM 16 /*read temp cnt*/
+#define T_VER_MASK 0x80
+#define T_VALUE_MIN 0x1500
+#define T_VALUE_MAX 0x3500
+#define T_DLY_TIME 4500 /*update sensor register need 4.2ms*/
+
+#define T_CONTROL_DATA 0x62b
+#define T_TSCLK_DATA 0x130
+
+#define ts_b 3094
+#define ts_a 9700
+#define ts_m 360
+#define ts_n 260
+
+#ifdef CONFIG_AML_TSENSOR
+int temp_read_entry(void);
+int temp_trim_entry(int tempbase, int tempver);
+int temp_cooling_entry(void);
+#else
+int temp_read_entry(void)
+{
+ return -1;
+}
+int temp_trim_entry(int tempbase, int tempver)
+{
+ return -1;
+}
+int temp_cooling_entry(void)
+{
+ return 0;
+}
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-c2/types.h b/arch/arm/include/asm/arch-c2/types.h
new file mode 100644
index 0000000..2d362b1
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/types.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __TYPES_H
+#define __TYPES_H
+
+#ifndef _INT8_T_DECLARED
+typedef char int8_t;
+#define _INT8_T_DECLARED
+#endif
+
+#ifndef _INT16_T_DECLARED
+typedef short int16_t;
+#define _INT16_T_DECLARED
+#endif
+
+#ifndef _INT32_T_DECLARED
+typedef int int32_t;
+#define _INT32_T_DECLARED
+#endif
+
+#ifndef _INT64_T_DECLARED
+typedef long int64_t;
+#define _INT64_T_DECLARED
+#endif
+
+#ifndef _UINT8_T_DECLARED
+typedef unsigned char uint8_t;
+#define _UINT8_T_DECLARED
+#endif
+
+#ifndef _UINT16_T_DECLARED
+typedef unsigned short uint16_t;
+#define _UINT16_T_DECLARED
+#endif
+
+#ifndef _UINT32_T_DECLARED
+typedef unsigned int uint32_t;
+#define _UINT32_T_DECLARED
+#endif
+
+#ifndef _UINT64_T_DECLARED
+typedef unsigned long uint64_t;
+#define _UINT64_T_DECLARED
+#endif
+
+#ifndef _INT8PTR_T_DECLARED
+typedef char * int8ptr_t;
+#define _INT8PTR_T_DECLARED
+#endif
+
+#ifndef _INT16PTR_T_DECLARED
+typedef short * int16ptr_t;
+#define _INT16PTR_T_DECLARED
+#endif
+
+#ifndef _INT32PTR_T_DECLARED
+typedef int * int32ptr_t;
+#define _INT32PTR_T_DECLARED
+#endif
+
+#ifndef _INT64PTR_T_DECLARED
+typedef long * int64ptr_t;
+#define _INT64PTR_T_DECLARED
+#endif
+
+#ifndef _UINT8PTR_T_DECLARED
+typedef unsigned char * uint8ptr_t;
+#define _UINT8PTR_T_DECLARED
+#endif
+
+#ifndef _UINT16PTR_T_DECLARED
+typedef unsigned short * uint16ptr_t;
+#define _UINT16PTR_T_DECLARED
+#endif
+
+#ifndef _UINT32PTR_T_DECLARED
+typedef unsigned int * uint32ptr_t;
+#define _UINT32PTR_T_DECLARED
+#endif
+
+#ifndef _UINT64PTR_T_DECLARED
+typedef unsigned long * uint64ptr_t;
+#define _UINT64PTR_T_DECLARED
+#endif
+
+#endif
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-c2/uart.h b/arch/arm/include/asm/arch-c2/uart.h
new file mode 100644
index 0000000..757dc91
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/uart.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __MESON_FIRM_UART_H_
+#define __MESON_FIRM_UART_H_
+#include <config.h>
+#include <common.h>
+#include "register.h"
+//#include "io.h"
+#include <asm/arch/secure_apb.h>
+
+#ifndef CONFIG_CONS_INDEX
+#error Please define CONFIG_CONS_INDEX==[0|1]
+#endif
+
+#if CONFIG_CONS_INDEX==0
+#define UART_PORT_CONS UART_PORT_0
+#elif CONFIG_CONS_INDEX==1
+#define UART_PORT_CONS UART_PORT_1
+#elif CONFIG_CONS_INDEX==2
+#define UART_PORT_CONS UART_PORT_AO
+#define USE_AO_UART 1
+#else
+#error Please define CONFIG_CONS_INDEX==[0|1]
+#endif
+/*
+#define UART_PORT_0 CBUS_REG_ADDR(UART0_WFIFO)
+#define UART_PORT_1 CBUS_REG_ADDR(UART1_WFIFO)
+#define UART_PORT_2 CBUS_REG_ADDR(UART2_WFIFO)
+#define UART_PORT_AO P_AO_UART_WFIFO
+
+#define UART_WFIFO (0<<2)
+#define UART_RFIFO (1<<2)
+#define UART_CONTROL (2<<2)
+#define UART_STATUS (3<<2)
+#define UART_MISC (4<<2)
+*/
+
+#include "clock.h"
+
+#define UART_CLK_SRC CLK81
+#define UART_PORT_0 0xfe001c00
+#define UART_PORT_1 0xfe001c00
+#define UART_PORT_AO 0xfe001c00
+#define UART_WFIFO 0
+#define UART_RFIFO 1
+#define UART_CONTROL 2
+#define UART_STATUS 3
+#define UART_MISC 4
+
+#if USE_AO_UART == 1
+#define P_UART(uart_base,reg) (uart_base + (reg<<2))
+#else
+#define P_UART(uart_base,reg) CBUS_REG_ADDR(uart_base+reg)
+#endif
+#define P_UART_WFIFO(uart_base) P_UART(uart_base,UART_WFIFO)
+#define P_UART_RFIFO(uart_base) P_UART(uart_base,UART_RFIFO)
+
+#define P_UART_CONTROL(uart_base) P_UART(uart_base,UART_CONTROL)
+ #define UART_CNTL_MASK_BAUD_RATE (0xfff)
+ #define UART_CNTL_MASK_TX_EN (1<<12)
+ #define UART_CNTL_MASK_RX_EN (1<<13)
+ #define UART_CNTL_MASK_2WIRE (1<<15)
+ #define UART_CNTL_MASK_STP_BITS (3<<16)
+ #define UART_CNTL_MASK_STP_1BIT (0<<16)
+ #define UART_CNTL_MASK_STP_2BIT (1<<16)
+ #define UART_CNTL_MASK_PRTY_EVEN (0<<18)
+ #define UART_CNTL_MASK_PRTY_ODD (1<<18)
+ #define UART_CNTL_MASK_PRTY_TYPE (1<<18)
+ #define UART_CNTL_MASK_PRTY_EN (1<<19)
+ #define UART_CNTL_MASK_CHAR_LEN (3<<20)
+ #define UART_CNTL_MASK_CHAR_8BIT (0<<20)
+ #define UART_CNTL_MASK_CHAR_7BIT (1<<20)
+ #define UART_CNTL_MASK_CHAR_6BIT (2<<20)
+ #define UART_CNTL_MASK_CHAR_5BIT (3<<20)
+ #define UART_CNTL_MASK_RST_TX (1<<22)
+ #define UART_CNTL_MASK_RST_RX (1<<23)
+ #define UART_CNTL_MASK_CLR_ERR (1<<24)
+ #define UART_CNTL_MASK_INV_RX (1<<25)
+ #define UART_CNTL_MASK_INV_TX (1<<26)
+ #define UART_CNTL_MASK_RINT_EN (1<<27)
+ #define UART_CNTL_MASK_TINT_EN (1<<28)
+ #define UART_CNTL_MASK_INV_CTS (1<<29)
+ #define UART_CNTL_MASK_MASK_ERR (1<<30)
+ #define UART_CNTL_MASK_INV_RTS (1<<31)
+#define P_UART_STATUS(uart_base) P_UART(uart_base,UART_STATUS )
+ #define UART_STAT_MASK_RFIFO_CNT (0x7f<<0)
+ #define UART_STAT_MASK_TFIFO_CNT (0x7f<<8)
+ #define UART_STAT_MASK_PRTY_ERR (1<<16)
+ #define UART_STAT_MASK_FRAM_ERR (1<<17)
+ #define UART_STAT_MASK_WFULL_ERR (1<<18)
+ #define UART_STAT_MASK_RFIFO_FULL (1<<19)
+ #define UART_STAT_MASK_RFIFO_EMPTY (1<<20)
+ #define UART_STAT_MASK_TFIFO_FULL (1<<21)
+ #define UART_STAT_MASK_TFIFO_EMPTY (1<<22)
+ #define UART_STAT_MASK_XMIT_BUSY (1<<25)
+ #define UART_STAT_MASK_RECV_BUSY (1<<26)
+#define P_UART_MISC(uart_base) P_UART(uart_base,UART_MISC )
+
+
+#ifndef CONFIG_SERIAL_STP_BITS
+#define CONFIG_SERIAL_STP_BITS 1 // 1 , 2
+#endif
+#if CONFIG_SERIAL_STP_BITS==1
+#define UART_STP_BIT UART_CNTL_MASK_STP_1BIT
+#elif CONFIG_SERIAL_STP_BITS==2
+#define UART_STP_BIT UART_CNTL_MASK_STP_2BIT
+#else
+#error CONFIG_SERIAL_STP_BITS wrong
+#endif
+
+
+#ifndef CONFIG_SERIAL_PRTY_TYPE
+#define CONFIG_SERIAL_PRTY_TYPE 0 //0 ,2 ,3
+#endif
+#if CONFIG_SERIAL_PRTY_TYPE==0
+#define UART_PRTY_BIT 0
+#elif CONFIG_SERIAL_PRTY_TYPE==2
+#define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_EVEN)
+#elif CONFIG_SERIAL_PRTY_TYPE==3
+#define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_ODD)
+#else
+#error CONFIG_SERIAL_PRTY_TYPE wrong
+#endif
+
+#ifndef CONFIG_SERIAL_CHAR_LEN
+#define CONFIG_SERIAL_CHAR_LEN 8 //5,6,7,8
+#endif
+#if CONFIG_SERIAL_CHAR_LEN==5
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_5BIT
+#elif CONFIG_SERIAL_CHAR_LEN==6
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_6BIT
+#elif CONFIG_SERIAL_CHAR_LEN==7
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_7BIT
+#elif CONFIG_SERIAL_CHAR_LEN==8
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_8BIT
+#else
+#error CONFIG_SERIAL_CHAR_LEN wrong
+#endif
+#define UART_CONTROL_SET(baud,clk81) \
+ (((clk81)/(baud*4) -1) \
+ | UART_STP_BIT \
+ | UART_PRTY_BIT \
+ | UART_CHAR_LEN \
+ | UART_CNTL_MASK_TX_EN \
+ | UART_CNTL_MASK_RX_EN \
+ | UART_CNTL_MASK_RST_TX \
+ | UART_CNTL_MASK_RST_RX \
+ | UART_CNTL_MASK_CLR_ERR )
+#endif
diff --git a/arch/arm/include/asm/arch-c2/usb.h b/arch/arm/include/asm/arch-c2/usb.h
new file mode 100644
index 0000000..7b49ac2
--- /dev/null
+++ b/arch/arm/include/asm/arch-c2/usb.h
@@ -0,0 +1,253 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __ARCH_ARM_MESON_USB_H_U_BOOT__
+#define __ARCH_ARM_MESON_USB_H_U_BOOT__
+
+#include <common.h>
+#include <asm/types.h>
+#include <asm/arch/io.h>
+#include <asm/arch/secure_apb.h>
+#include <generic-phy.h>
+#include <asm-generic/gpio.h>
+
+#define HOST_MODE 0
+#define DEVICE_MODE 1
+
+#define USB_PHY_PORT_MAX 1
+/* Phy register MACRO definitions */
+
+#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
+#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
+#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27)
+
+#define PHYUTMI_OTGDISABLE (1 << 6)
+#define PHYUTMI_FORCESUSPEND (1 << 1)
+#define PHYUTMI_FORCESLEEP (1 << 0)
+
+#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
+#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
+
+#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
+#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
+
+#define PHYCLKRST_SSC_EN (0x1 << 20)
+#define PHYCLKRST_REF_SSP_EN (0x1 << 19)
+#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18)
+
+#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
+
+#define PHYCLKRST_FSEL_MASK (0x3f << 5)
+#define PHYCLKRST_FSEL(_x) ((_x) << 5)
+#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
+#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
+#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
+#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
+
+#define PHYCLKRST_RETENABLEN (0x1 << 4)
+
+#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
+#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
+#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
+
+#define PHYCLKRST_PORTRESET (0x1 << 1)
+#define PHYCLKRST_COMMONONN (0x1 << 0)
+
+#define PHYPARAM0_REF_USE_PAD (0x1 << 31)
+#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
+#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
+
+#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
+#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
+
+#define PHYTEST_POWERDOWN_SSP (0x1 << 3)
+#define PHYTEST_POWERDOWN_HSP (0x1 << 2)
+
+#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2)
+
+#define FSEL_CLKSEL_24M (0x5)
+
+#define USB_PHY2_ENABLE (0x1 << 1)
+#define USB_PHY2_RESET (0x1 << 0)
+#define USBPLL_LK_OD_EN (0x1 << 16)
+#define USBPLL_LOCKFLAG_BIT (31)
+
+
+/* XHCI PHY register structure */
+#define PHY_REGISTER_SIZE 0x20
+
+struct phy_aml_usb2_priv {
+ unsigned int base_addr;
+ unsigned int reset_addr;
+ unsigned int dwc2_a_addr;
+ unsigned int u2_port_num;
+ unsigned int usbphy_reset_bit[8];
+ unsigned int clktree_usb_bus_ctrl_addr;
+ unsigned int usb_phy2_pll_base_addr[4];
+};
+
+struct phy_aml_usb3_priv {
+ unsigned int base_addr;
+ unsigned int usb3_port_num;
+ struct gpio_desc desc;
+};
+
+/* Register definitions */
+typedef struct u2p_aml_regs {
+ volatile uint32_t u2p_r0;
+ volatile uint32_t u2p_r1;
+} u2p_aml_regs_t;
+
+typedef union u2p_r0 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned host_device:1;
+ unsigned power_ok:1;
+ unsigned hast_mode:1;
+ unsigned POR:1;
+ unsigned IDPULLUP0:1;
+ unsigned DRVVBUS0:1;
+ unsigned reserved:26;
+ } b;
+} u2p_r0_t;
+
+typedef union u2p_r1 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned phy_rdy:1;
+ unsigned IDDIG0:1;
+ unsigned OTGSESSVLD0:1;
+ unsigned VBUSVALID0:1;
+ unsigned reserved:28;
+ } b;
+} u2p_r1_t;
+
+
+typedef struct usb_aml_regs {
+ volatile uint32_t usb_r0;
+ volatile uint32_t usb_r1;
+ volatile uint32_t usb_r2;
+ volatile uint32_t usb_r3;
+ volatile uint32_t usb_r4;
+ volatile uint32_t usb_r5;
+} usb_aml_regs_t;
+
+typedef union usb_r0 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned reserved:17;
+ unsigned p30_lane0_tx2rx_loopback:1;
+ unsigned p30_lane0_ext_pclk_reg:1;
+ unsigned p30_pcs_rx_los_mask_val:10;
+ unsigned u2d_ss_scaledown_mode:2;
+ unsigned u2d_act:1;
+ } b;
+} usb_r0_t;
+
+typedef union usb_r1 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned u3h_bigendian_gs:1;
+ unsigned u3h_pme_en:1;
+ unsigned u3h_hub_port_overcurrent:3;
+ unsigned reserved_1:2;
+ unsigned u3h_hub_port_perm_attach:3;
+ unsigned reserved_2:2;
+ unsigned u3h_host_u2_port_disable:2;
+ unsigned reserved_3:2;
+ unsigned u3h_host_u3_port_disable:1;
+ unsigned u3h_host_port_power_control_present:1;
+ unsigned u3h_host_msi_enable:1;
+ unsigned u3h_fladj_30mhz_reg:6;
+ unsigned p30_pcs_tx_swing_full:7;
+ } b;
+} usb_r1_t;
+
+typedef union usb_r2 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned reserved:20;
+ unsigned p30_pcs_tx_deemph_3p5db:6;
+ unsigned p30_pcs_tx_deemph_6db:6;
+ } b;
+} usb_r2_t;
+
+typedef union usb_r3 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned p30_ssc_en:1;
+ unsigned p30_ssc_range:3;
+ unsigned p30_ssc_ref_clk_sel:9;
+ unsigned p30_ref_ssp_en:1;
+ unsigned reserved:18;
+ } b;
+} usb_r3_t;
+
+typedef union usb_r4 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned p21_PORTRESET0:1;
+ unsigned p21_SLEEPM0:1;
+ unsigned mem_pd:2;
+ unsigned p21_only:1;
+ unsigned reserved:27;
+ } b;
+} usb_r4_t;
+
+typedef union usb_r5 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned iddig_sync:1;
+ unsigned iddig_reg:1;
+ unsigned iddig_cfg:2;
+ unsigned iddig_en0:1;
+ unsigned iddig_en1:1;
+ unsigned iddig_curr:1;
+ unsigned usb_iddig_irq:1;
+ unsigned iddig_th:8;
+ unsigned iddig_cnt:8;
+ unsigned reserved:8;
+ } b;
+} usb_r5_t;
+
+/* usb id mode, only after M2
+ mode = 0 : HARDWARE
+ mode = 1 : SW_HOST
+ mode = 2 : SW_DEVICE
+ */
+#define USB_ID_MODE_HARDWARE (1)
+#define USB_ID_MODE_SW_HOST (2)
+#define USB_ID_MODE_SW_DEVICE (3)
+int usb2_phy_tuning(uint32_t phy2_pll_base, int port);
+void set_usb_pll(uint32_t phy2_pll_base);
+int usb_save_phy_dev (unsigned int number, struct phy *phy);
+int usb2_phy_init (struct phy *phy);
+unsigned int usb_get_dwc_a_base_addr(void);
+unsigned int usb_get_device_mode_phy_base(void);
+void usb_phy_tuning_reset(void);
+void usb_device_mode_init(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-g12a/acs.h b/arch/arm/include/asm/arch-g12a/acs.h
index c65c647..c98cbee 100644
--- a/arch/arm/include/asm/arch-g12a/acs.h
+++ b/arch/arm/include/asm/arch-g12a/acs.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/acs.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __ACS_H
#define __ACS_H
@@ -59,6 +43,9 @@
unsigned char rsv_set_version;
unsigned short rsv_set_length;
unsigned long rsv_set_addr;
+ char board_id[12];
+ unsigned short ddr_struct_size[12];
+ unsigned long ddr_struct_org_size;
}__attribute__ ((packed)) acs_set_t;
#endif
diff --git a/arch/arm/include/asm/arch-g12a/bl31_apis.h b/arch/arm/include/asm/arch-g12a/bl31_apis.h
index ec0840b..abe6c8d 100644
--- a/arch/arm/include/asm/arch-g12a/bl31_apis.h
+++ b/arch/arm/include/asm/arch-g12a/bl31_apis.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/bl31_apis.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
/*
* Trustzone API
@@ -48,7 +32,6 @@
#define GET_SHARE_STORAGE_BLOCK_SIZE 0x82000027
#define SET_STORAGE_INFO 0x82000028
#define SET_REBOOT_REASON 0x82000049
-#define GET_DVFS_TABLE_INDEX 0x82000088
/* Set Reboot Reason then Reboot*/
#define PSCI_SYS_REBOOT 0x84000009
@@ -95,6 +78,17 @@
/*viu probe en*/
#define VIU_PREOBE_EN 0x82000080
+
+/* KEYMASTER */
+#define SET_BOOT_PARAMS 0x82000072
+#define SHA256_DIGEST_SIZE 32
+typedef struct {
+ uint32_t device_locked;
+ uint32_t verified_boot_state;
+ uint8_t verified_boot_key[SHA256_DIGEST_SIZE];
+ uint8_t verified_boot_hash[SHA256_DIGEST_SIZE];
+} keymaster_boot_params;
+
/* Secure HAL APIs */
#define TRUSTZONE_HAL_API_SRAM 0x400
@@ -117,6 +111,7 @@
#define JTAG_A53_EE 3
#define CLUSTER_BIT 2
+#define GET_AVBKEY_FROM_FIP 0x820000b0
/////////////////////////////////////////////////////////////////////////////////
#define AML_DATA_PROCESS (0x820000FF)
@@ -125,8 +120,6 @@
#define AML_D_P_W_EFUSE_CUSTOMER_ID (0x12)
#define AML_D_P_W_EFUSE_AMLOGIC (0x20)
#define AML_D_P_IMG_DECRYPT (0x40)
- #define AML_D_P_IMG_DECRYPT_V3 (0x41)
- #define AML_D_P_EXT_IMG_DECRYPT_V3 (0x51)
#define AML_D_P_UPGRADE_CHECK (0x80)
#define AML_D_Q_IMG_SIG_HDR_SIZE (0x100)
@@ -142,7 +135,6 @@
void aml_set_jtag_state(unsigned state, unsigned select);
unsigned aml_get_reboot_reason(void);
-unsigned aml_get_dvfs_id(void);
unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2);
void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2);
unsigned long aml_sec_boot_check(unsigned long ,unsigned long ,unsigned long,unsigned long );
@@ -153,4 +145,6 @@
void bl31_get_chipid(unsigned int *, unsigned int *,
unsigned int *, unsigned int *);
void set_viu_probe_enable(void);
+int32_t set_boot_params(const keymaster_boot_params*);
+int32_t get_avbkey_from_fip(uint8_t *buf, uint32_t buflen);
#endif
diff --git a/arch/arm/include/asm/arch-g12a/board_id.h b/arch/arm/include/asm/arch-g12a/board_id.h
index 6137e12..6488771 100644
--- a/arch/arm/include/asm/arch-g12a/board_id.h
+++ b/arch/arm/include/asm/arch-g12a/board_id.h
@@ -1,19 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
unsigned int get_board_id(void);
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-g12a/clk_measure_tab.h b/arch/arm/include/asm/arch-g12a/clk_measure_tab.h
new file mode 100644
index 0000000..fd23263
--- /dev/null
+++ b/arch/arm/include/asm/arch-g12a/clk_measure_tab.h
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _ARCH_MESON_G12A_MEASURE_H_
+#define _ARCH_MESON_G12A_MEASURE_H_
+
+const char* clk_msr_table[] = {
+ [127] = "1'b0 ",
+ [126] = "1'b0 ",
+ [125] = "1'b0 ",
+ [124] = "1'b0 ",
+ [123] = "1'b0 ",
+ [122] = "mod_audio_pdm_dclk_o ",
+ [121] = "audio_spdifin_mst_clk ",
+ [120] = "audio_spdifout_mst_clk ",
+ [119] = "audio_spdifout_b_mst_clk ",
+ [118] = "audio_pdm_sysclk ",
+ [117] = "audio_resample_sclk ",
+ [116] = "audio_tdmin_a_sclk ",
+ [115] = "audio_tdmin_b_sclk ",
+ [114] = "audio_tdmin_c_sclk ",
+ [113] = "audio_tdmin_lb_sclk ",
+ [112] = "audio_tdmout_a_sclk ",
+ [111] = "audio_tdmout_b_sclk ",
+ [110] = "audio_tdmout_c_sclk ",
+ [109] = "c_alocker_out_clk ",
+ [108] = "c_alocker_in_clk ",
+ [107] = "au_dac_clk_g128x ",
+ [106] = "ephy_test_clk ",
+ [105] = "am_ring_osc_clk_out_ee[9] ",
+ [104] = "am_ring_osc_clk_out_ee[8] ",
+ [103] = "am_ring_osc_clk_out_ee[7] ",
+ [102] = "am_ring_osc_clk_out_ee[6] ",
+ [101] = "am_ring_osc_clk_out_ee[5] ",
+ [100] = "am_ring_osc_clk_out_ee[4] ",
+ [99] = "am_ring_osc_clk_out_ee[3] ",
+ [98] = "cts_ts_clk ",
+ [97] = "cts_vpu_clkb_tmp ",
+ [96] = "cts_vpu_clkb ",
+ [95] = "eth_phy_plltxclk ",
+ [94] = "eth_phy_rxclk ",
+ [93] = "1'b0 ",
+ [92] = "1'b0 ",
+ [91] = "1'b0 ",
+ [90] = "cts_hdmitx_sys_clk ",
+ [89] = "HDMI_CLK_TODIG ",
+ [88] = "1'b0 ",
+ [87] = "1'b0 ",
+ [86] = "1'b0 ",
+ [85] = "1'b0 ",
+ [84] = "co_tx_clk ",
+ [83] = "co_rx_clk ",
+ [82] = "Cts_ge2d_clk ",
+ [81] = "Cts_vapbclk ",
+ [80] = "Rng_ring_osc_clk[3] ",
+ [79] = "Rng_ring_osc_clk[2] ",
+ [78] = "Rng_ring_osc_clk[1] ",
+ [77] = "Rng_ring_osc_clk[0] ",
+ [76] = "1'b0 ",
+ [75] = "cts_hevcf_clk ",
+ [74] = "1'b0 ",
+ [73] = "cts_pwm_C_clk ",
+ [72] = "cts_pwm_D_clk ",
+ [71] = "cts_pwm_E_clk ",
+ [70] = "cts_pwm_F_clk ",
+ [69] = "Cts_hdcp22_skpclk ",
+ [68] = "Cts_hdcp22_esmclk ",
+ [67] = "cts_dsi_phy_clk ",
+ [66] = "cts_vid_lock_clk ",
+ [65] = "cts_spicc_0_clk ",
+ [64] = "Cts_spicc_1_clk ",
+ [63] = "cts_dsi_meas_clk ",
+ [62] = "cts_hevcb_clk ",
+ [61] = "gpio_clk_msr ",
+ [60] = "1'b0 ",
+ [59] = "cts_hcodec_clk ",
+ [58] = "cts_wave4201_bclk ",
+ [57] = "cts_wave4201_cclk ",
+ [56] = "cts_wave4201_aclk ",
+ [55] = "vid_pll_div_clk_out ",
+ [54] = "cts_vpu_clkc ",
+ [53] = "sd_emmc_clk_A ",
+ [52] = "sd_emmc_clk_B ",
+ [51] = "sd_emmc_clk_C ",
+ [50] = "mp3_clk_out ",
+ [49] = "mp2_clk_out ",
+ [48] = "mp1_clk_out ",
+ [47] = "ddr_dpll_pt_clk ",
+ [46] = "cts_vpu_clk ",
+ [45] = "cts_pwm_A_clk ",
+ [44] = "cts_pwm_B_clk ",
+ [43] = "fclk_div5 ",
+ [42] = "mp0_clk_out ",
+ [41] = "mac_eth_rx_clk_rmii ",
+ [40] = "1'b0 ",
+ [39] = "cts_bt656_clk0 ",
+ [38] = "Cts_vdin_meas_clk ",
+ [37] = "cts_cdac_clk_c ",
+ [36] = "cts_hdmi_tx_pixel_clk ",
+ [35] = "cts_mali_clk ",
+ [34] = "eth_mppll_50m_ckout ",
+ [33] = "sys_cpu_ring_osc_clk[1] ",
+ [32] = "cts_vdec_clk ",
+ [31] = "MPLL_CLK_TEST_OUT ",
+ [30] = "pcie_clk_inn ",
+ [29] = "pcie_clk_inp ",
+ [28] = "Cts_sar_adc_clk ",
+ [27] = "co_clkin_to_mac ",
+ [26] = "sc_clk_int ",
+ [25] = "cts_eth_clk_rmii ",
+ [24] = "cts_eth_clk125Mhz ",
+ [23] = "mpll_clk_50m ",
+ [22] = "mac_eth_phy_ref_clk ",
+ [21] = "lcd_an_clk_ph3 ",
+ [20] = "rtc_osc_clk_out ",
+ [19] = "lcd_an_clk_ph2 ",
+ [18] = "sys_cpu_clk_div16 ",
+ [17] = "sys_pll_div16 ",
+ [16] = "cts_FEC_CLK_2 ",
+ [15] = "cts_FEC_CLK_1 ",
+ [14] = "cts_FEC_CLK_0 ",
+ [13] = "mod_tcon_clko ",
+ [12] = "hifi_pll_clk ",
+ [11] = "mac_eth_tx_clk ",
+ [10] = "cts_vdac_clk ",
+ [9] = "cts_encl_clk ",
+ [8] = "cts_encp_clk ",
+ [7] = "clk81 ",
+ [6] = "cts_enci_clk ",
+ [5] = "1'b0 ",
+ [4] = "gp0_pll_clk ",
+ [3] = "A53_ring_osc_clk ",
+ [2] = "am_ring_osc_clk_out_ee[2] ",
+ [1] = "am_ring_osc_clk_out_ee[1] ",
+ [0] = "am_ring_osc_clk_out_ee[0] ",
+
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-g12a/clock.h b/arch/arm/include/asm/arch-g12a/clock.h
index 3a24778..59f2131 100644
--- a/arch/arm/include/asm/arch-g12a/clock.h
+++ b/arch/arm/include/asm/arch-g12a/clock.h
@@ -1,7 +1,8 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Copyright 2018 - AmLogic, Inc.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#ifndef _ARCH_MESON_G12A_CLOCK_H_
#define _ARCH_MESON_G12A_CLOCK_H_
@@ -13,28 +14,28 @@
* to get the right value
*/
-#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet1 */
-#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet1 */
-#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet1 */
-#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet1 */
-#define HHI_FIX_PLL_CNTL0 0x2A0 /* 0xa8 offset in data sheet1 */
-#define HHI_FIX_PLL_CNTL1 0x2A4 /* 0xa9 offset in data sheet1 */
-#define HHI_SYS_PLL_CNTL0 0x2f4 /* 0xbd offset in data sheet1 */
-#define HHI_SYS_PLL_CNTL1 0x2f8 /* 0xbe offset in data sheet1 */
-#define HHI_SYS_PLL_CNTL2 0x2fc /* 0xbf offset in data sheet1 */
-#define HHI_SYS_PLL_CNTL3 0x300 /* 0xc0 offset in data sheet1 */
-#define HHI_SYS_PLL_CNTL4 0x304 /* 0xc1 offset in data sheet1 */
-#define HHI_SYS_PLL_CNTL5 0x308 /* 0xc2 offset in data sheet1 */
-#define HHI_SYS_PLL_CNTL6 0x30c /* 0xc3 offset in data sheet1 */
-#define HHI_SPICC_CLK_CNTL 0x3dc /* 0xf7 offset in data sheet1 */
-#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet1 */
-#define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet1 */
+#define G12_HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet1 */
+#define G12_HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet1 */
+#define G12_HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet1 */
+#define G12_HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet1 */
+#define G12_HHI_FIX_PLL_CNTL0 0x2A0 /* 0xa8 offset in data sheet1 */
+#define G12_HHI_FIX_PLL_CNTL1 0x2A4 /* 0xa9 offset in data sheet1 */
+#define G12_HHI_SYS_PLL_CNTL0 0x2f4 /* 0xbd offset in data sheet1 */
+#define G12_HHI_SYS_PLL_CNTL1 0x2f8 /* 0xbe offset in data sheet1 */
+#define G12_HHI_SYS_PLL_CNTL2 0x2fc /* 0xbf offset in data sheet1 */
+#define G12_HHI_SYS_PLL_CNTL3 0x300 /* 0xc0 offset in data sheet1 */
+#define G12_HHI_SYS_PLL_CNTL4 0x304 /* 0xc1 offset in data sheet1 */
+#define G12_HHI_SYS_PLL_CNTL5 0x308 /* 0xc2 offset in data sheet1 */
+#define G12_HHI_SYS_PLL_CNTL6 0x30c /* 0xc3 offset in data sheet1 */
+#define G12_HHI_SPICC_CLK_CNTL 0x3dc /* 0xf7 offset in data sheet1 */
+#define G12_HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet1 */
+#define G12_HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet1 */
#define CLKID_UNREALIZED 0xfff
/* AO registers */
-#define AO_SAR_CLK 0x90
-#define AO_CLK_GATE0 0x4c
+#define G12_AO_SAR_CLK 0x90
+#define G12_AO_CLK_GATE0 0x4c
ulong meson_measure_clk_rate(unsigned int clk);
diff --git a/arch/arm/include/asm/arch-g12a/core.h b/arch/arm/include/asm/arch-g12a/core.h
index f336935..97fd220 100644
--- a/arch/arm/include/asm/arch-g12a/core.h
+++ b/arch/arm/include/asm/arch-g12a/core.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-g12a/core.h
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __CORE_H__
#define __CORE_H__
diff --git a/arch/arm/include/asm/arch-g12a/cpu.h b/arch/arm/include/asm/arch-g12a/cpu.h
index a5f181e..ba73ba3 100644
--- a/arch/arm/include/asm/arch-g12a/cpu.h
+++ b/arch/arm/include/asm/arch-g12a/cpu.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-g12a/cpu.h
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _CPU_H
#define _CPU_H
@@ -37,7 +21,7 @@
#endif
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (64*1024*1024)
+#define CONFIG_SYS_MALLOC_LEN (96*1024*1024)
/* for uboot envrionment use */
/* #define CONFIG_DDR_SIZE 1024 */
@@ -87,4 +71,11 @@
#define NR_CPUS 4
+#define CPU_ID_REG P_AO_SEC_SD_CFG8
+#define PACKAGE_ID_MASK 0xFF
+
+#define MIPI_DSI_REGISTER 1
+#define MIPI_DSI_BASE 0xffd07000L
+#define MIPI_DSI_PHY_BASE 0xff644000L
+
#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-g12a/cpu_config.h b/arch/arm/include/asm/arch-g12a/cpu_config.h
index 7e7c758..45e7e80 100644
--- a/arch/arm/include/asm/arch-g12a/cpu_config.h
+++ b/arch/arm/include/asm/arch-g12a/cpu_config.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/cpu_config.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _BOOT_ROM_CONFIG_H_
#define _BOOT_ROM_CONFIG_H_
diff --git a/arch/arm/include/asm/arch-g12a/cpu_id.h b/arch/arm/include/asm/arch-g12a/cpu_id.h
deleted file mode 100644
index 6645edd..0000000
--- a/arch/arm/include/asm/arch-g12a/cpu_id.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * arch/arm/include/asm/cpu_id.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#define MESON_CPU_MAJOR_ID_M6 0x16
-#define MESON_CPU_MAJOR_ID_M6TV 0x17
-#define MESON_CPU_MAJOR_ID_M6TVL 0x18
-#define MESON_CPU_MAJOR_ID_M8 0x19
-#define MESON_CPU_MAJOR_ID_MTVD 0x1A
-#define MESON_CPU_MAJOR_ID_M8B 0x1B
-#define MESON_CPU_MAJOR_ID_MG9TV 0x1C
-#define MESON_CPU_MAJOR_ID_M8M2 0x1D
-#define MESON_CPU_MAJOR_ID_GXBB 0x1F
-#define MESON_CPU_MAJOR_ID_GXTVBB 0x20
-#define MESON_CPU_MAJOR_ID_GXL 0x21
-#define MESON_CPU_MAJOR_ID_GXM 0x22
-#define MESON_CPU_MAJOR_ID_TXL 0x23
-#define MESON_CPU_MAJOR_ID_TXLX 0x24
-#define MESON_CPU_MAJOR_ID_AXG 0x25
-#define MESON_CPU_MAJOR_ID_GXLX 0x26
-#define MESON_CPU_MAJOR_ID_TXHD 0x27
-#define MESON_CPU_MAJOR_ID_G12A 0x28
-#define MESON_CPU_MAJOR_ID_G12B 0x29
-#define MESON_CPU_MAJOR_ID_SM1 0x2B
-#define MESON_CPU_MAJOR_ID_TL1 0x2E
-#define MESON_CPU_MAJOR_ID_TM2 0x2F
-
-#define MESON_CPU_PACKAGE_ID_905D 0X00
-#define MESON_CPU_PACKAGE_ID_905M 0x20
-#define MESON_CPU_PACKAGE_ID_905X 0X80
-#define MESON_CPU_PACKAGE_ID_905L 0XC0
-#define MESON_CPU_PACKAGE_ID_905M2 0XE0
-
-#define MESON_CPU_PACKAGE_ID_T962X 0x10
-#define MESON_CPU_PACKAGE_ID_T962E 0x20
-
-#define MESON_CPU_PACKAGE_ID_A113X 0x37
-#define MESON_CPU_PACKAGE_ID_A113D 0xD0
-
-#define MESON_CPU_CHIP_REVISION_A 0xA
-#define MESON_CPU_CHIP_REVISION_B 0xB
-#define MESON_CPU_CHIP_REVISION_C 0xC
-#define MESON_CPU_CHIP_REVISION_D 0xD
-
-typedef struct cpu_id {
- unsigned int family_id:8; //S905/T968 etc.
- unsigned int package_id:8; //T968/T966 etc.
- unsigned int chip_rev:8; //RevA/RevB etc.
- unsigned int reserve:4;
- unsigned int layout_ver:4;
-} cpu_id_t;
-
-typedef struct chip_id {
- unsigned int version;
- unsigned char chipid[16];
-} chip_id_t;
-
-cpu_id_t get_cpu_id(void);
-
-extern chip_id_t aml_chip_id;
-int get_chip_id(unsigned char *buff, unsigned int size);
-
-/**
- * TODO: Remove this API after move static system information to RO
- * register or SRAM
- *
- * Should *NOT* call this API directly, always use get_chip_id()
- */
-int __get_chip_id(unsigned char *buff, unsigned int size);
diff --git a/arch/arm/include/asm/arch-g12a/cpu_reset.h b/arch/arm/include/asm/arch-g12a/cpu_reset.h
new file mode 100644
index 0000000..46f9abf
--- /dev/null
+++ b/arch/arm/include/asm/arch-g12a/cpu_reset.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _BOOT_ROM_WATCHDOG_H
+#define _BOOT_ROM_WATCHDOG_H
+#include <asm/arch/secure_apb.h>
+
+void reset_system(void);
+
+/* uboot reset interface */
+void reset_cpu(unsigned long flag);
+
+#endif /* _BOOT_ROM_WATCHDOG_H */
diff --git a/arch/arm/include/asm/arch-g12a/cpu_sdio.h b/arch/arm/include/asm/arch-g12a/cpu_sdio.h
index 552b315..418f08e 100644
--- a/arch/arm/include/asm/arch-g12a/cpu_sdio.h
+++ b/arch/arm/include/asm/arch-g12a/cpu_sdio.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/cpu_sdio.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __CPU_SDIO_H__
#define __CPU_SDIO_H__
@@ -30,6 +14,15 @@
#define SDIO_PORT_B 1
#define SDIO_PORT_C 2
+#if 0
+#define SD_EMMC_RXD_ERROR 1
+#define SD_EMMC_TXD_ERROR 1<<1
+#define SD_EMMC_DESC_ERROR 1<<2
+#define SD_EMMC_RESP_CRC_ERROR 1<<3
+#define SD_EMMC_RESP_TIMEOUT_ERROR 1<<4
+#define SD_EMMC_DESC_TIMEOUT_ERROR 1<<5
+#endif
+
struct sd_emmc_global_regs {
volatile uint32_t gclock; // 0x00
volatile uint32_t gdelay; // 0x04
diff --git a/arch/arm/include/asm/arch-g12a/ddr.h b/arch/arm/include/asm/arch-g12a/ddr.h
index f5ea6c7..ad27855 100644
--- a/arch/arm/include/asm/arch-g12a/ddr.h
+++ b/arch/arm/include/asm/arch-g12a/ddr.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/ddr.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <config.h>
#include <io.h>
diff --git a/arch/arm/include/asm/arch-g12a/ddr_define.h b/arch/arm/include/asm/arch-g12a/ddr_define.h
index d745000..09d626e 100644
--- a/arch/arm/include/asm/arch-g12a/ddr_define.h
+++ b/arch/arm/include/asm/arch-g12a/ddr_define.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/ddr_define.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#define CONFIG_BOARD_ID_MASK 0xFF
#define CONFIG_DDR_TYPE_DDR3 0
@@ -83,6 +67,8 @@
(chl_set == CONFIG_DDR0_16BIT))
#define DDR_USE_2_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK01))
+#define DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT 1<<5
+#define DMC_TEST_SLT_ENABLE_DDR_AUTO_WINDOW_TEST 1<<4
/* DMC_DDR_CTRL defines */
#define DDR_DDR4_ENABLE (1<<22)
#define DDR_RANK1_ENABLE (1<<21)
@@ -97,6 +83,8 @@
#define DMC_TEST_SLT_SCAN_FREQUENCY 1
#define DMC_TEST_SLT_OFFSET_DELAY (1<<1)
+
+//#define DMC_TEST_SLT_ENABLE_DDR_MAX_CORE_TIMMING_LIMIT 1<<6
#define DMC_TEST_SLT_ENABLE_DDR_SKIP_TRAINING (1<<6)
#define DMC_TEST_SLT_ENABLE_DDR_DVFS (1<<7)
@@ -151,68 +139,73 @@
*/
/* d2pll support */
-#ifndef CONFIG_CMD_D2PLL
-#define CONFIG_CMD_D2PLL 0
+#ifndef CONFIG_CMD_DDR_D2PLL
+#define CONFIG_CMD_DDR_D2PLL 0
#endif
-#define DDR_FUNC_D2PLL (CONFIG_CMD_D2PLL<<0)
+#define DDR_FUNC_D2PLL (CONFIG_CMD_DDR_D2PLL<<0)
/* ddr low power function support */
-#ifndef DDR_LOW_POWER
-#define DDR_LOW_POWER 0
+#ifndef CONFIG_DDR_LOW_POWER
+#define CONFIG_DDR_LOW_POWER 0
#endif
-#define DDR_FUNC_LP (DDR_LOW_POWER<<1)
+#define DDR_FUNC_LP (CONFIG_DDR_LOW_POWER<<1)
/* ddr zq power down support */
-#ifndef DDR_ZQ_PD
-#define DDR_ZQ_PD 0
+#ifndef CONFIG_DDR_ZQ_PD
+#define CONFIG_DDR_ZQ_PD 0
#endif
-#define DDR_FUNC_ZQ_PD (DDR_ZQ_PD<<2)
+#define DDR_FUNC_ZQ_PD (CONFIG_DDR_ZQ_PD<<2)
/* ddr vref function */
-#ifndef DDR_USE_EXT_VREF
-#define DDR_USE_EXT_VREF 0
+#ifndef CONFIG_DDR_USE_EXT_VREF
+#define CONFIG_DDR_USE_EXT_VREF 0
#endif
-#define DDR_FUNC_EXT_VREF (DDR_USE_EXT_VREF<<3)
+#define DDR_FUNC_EXT_VREF (CONFIG_DDR_USE_EXT_VREF<<3)
/* ddr4 timing test function */
-#ifndef DDR4_TIMING_TEST
-#define DDR4_TIMING_TEST 0
+#ifndef CONFIG_DDR4_TIMING_TEST
+#define CONFIG_DDR4_TIMING_TEST 0
#endif
-#define DDR_FUNC_DDR4_TIMING_TEST (DDR4_TIMING_TEST<<4)
+#define DDR_FUNC_DDR4_TIMING_TEST (CONFIG_DDR4_TIMING_TEST<<4)
/* ddr pll bypass */
-#ifndef DDR_PLL_BYPASS
-#define DDR_PLL_BYPASS 0
+#ifndef CONFIG_DDR_PLL_BYPASS
+#define CONFIG_DDR_PLL_BYPASS 0
#endif
-#define DDR_FUNC_DDR_PLL_BYPASS (DDR_PLL_BYPASS<<5)
+#define DDR_FUNC_DDR_PLL_BYPASS (CONFIG_DDR_PLL_BYPASS<<5)
/* ddr rdbi function */
-#ifndef DDR_FUNC_RDBI
-#define DDR_FUNC_RDBI 0
+#ifndef CONFIG_DDR_FUNC_RDBI
+#define CONFIG_DDR_FUNC_RDBI 0
#endif
-#define DDR_FUNC_DDR_RDBI (DDR_FUNC_RDBI<<6)
+#define DDR_FUNC_RDBI (CONFIG_DDR_FUNC_RDBI<<6)
/* lpddr3 ca trainingi function */
-#ifndef DDR_FUNC_LPDDR3_CA
-#define DDR_FUNC_LPDDR3_CA 0
+#ifndef CONFIG_DDR_FUNC_LPDDR3_CA
+#define CONFIG_DDR_FUNC_LPDDR3_CA 0
#endif
-#define DDR_FUNC_LPDDR3_CA_TRAIN (DDR_FUNC_LPDDR3_CA<<7)
+#define DDR_FUNC_LPDDR3_CA (CONFIG_DDR_FUNC_LPDDR3_CA<<7)
/* print ddr training window */
-#ifndef DDR_FUNC_PRINT_WINDOW
-#define DDR_FUNC_PRINT_WINDOW 0
+#ifndef CONFIG_DDR_FUNC_PRINT_WINDOW
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 0
#endif
-#define DDR_FUNC_PRINT_WINDOW_EN (DDR_FUNC_PRINT_WINDOW<<8)
+#define DDR_FUNC_PRINT_WINDOW (CONFIG_DDR_FUNC_PRINT_WINDOW<<8)
/* print ddr training window */
-#ifndef DDR_FULL_TEST
-#define DDR_FULL_TEST 0
+//#ifndef CONFIG_DDR_FULL_TEST
+//#define CONFIG_DDR_FULL_TEST 0
+//#endif
+//#define DDR_FULL_TEST (CONFIG_DDR_FULL_TEST<<10)
+
+/* non-sec region scramble function */
+#ifndef CONFIG_DDR_NONSEC_SCRAMBLE
+#define CONFIG_DDR_NONSEC_SCRAMBLE 0
#endif
-#define DDR_FULL_TEST_EN (DDR_FULL_TEST<<10)
+#define DDR_NONSEC_SCRAMBLE (CONFIG_DDR_NONSEC_SCRAMBLE<<11)
-
-#if(DDR_FUNC_LPDDR3_CA==1)
+#if(CONFIG_DDR_FUNC_LPDDR3_CA==1)
#if (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE0)
#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20)
#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21)
@@ -251,17 +244,20 @@
#else
#define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP (0<<25)
#endif
-
+#define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1<<30)
+#define DDR_FUNC_CONFIG_DFE_FUNCTION (1<<29)
+#define DDR_FUNC_CONFIG_DDR_DVFS_FUNCTION (1<<28)
#define DDR_FUNC (DDR_FUNC_D2PLL | \
DDR_FUNC_LP | \
DDR_FUNC_ZQ_PD | \
DDR_FUNC_EXT_VREF | \
DDR_FUNC_DDR4_TIMING_TEST | \
DDR_FUNC_DDR_PLL_BYPASS | \
- DDR_FUNC_DDR_RDBI | \
- DDR_FUNC_LPDDR3_CA_TRAIN | \
- DDR_FUNC_PRINT_WINDOW_EN | \
- DDR_FULL_TEST_EN | \
+ DDR_FUNC_RDBI | \
+ DDR_FUNC_LPDDR3_CA | \
+ DDR_FUNC_PRINT_WINDOW | \
+ DDR_FULL_TEST | \
+ DDR_NONSEC_SCRAMBLE | \
DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0| \
DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1| \
DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0| \
diff --git a/arch/arm/include/asm/arch-g12a/efuse.h b/arch/arm/include/asm/arch-g12a/efuse.h
index b5ea027..4a68e88 100644
--- a/arch/arm/include/asm/arch-g12a/efuse.h
+++ b/arch/arm/include/asm/arch-g12a/efuse.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/efuse.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __EFUSE_H
#define __EFUSE_H
diff --git a/arch/arm/include/asm/arch-g12a/eth_setup.h b/arch/arm/include/asm/arch-g12a/eth_setup.h
index 2b0d877..6e643f6 100644
--- a/arch/arm/include/asm/arch-g12a/eth_setup.h
+++ b/arch/arm/include/asm/arch-g12a/eth_setup.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/eth_setup.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <asm/arch/io.h>
diff --git a/arch/arm/include/asm/arch-g12a/gpio.h b/arch/arm/include/asm/arch-g12a/gpio.h
index d0142f1..2467368 100644
--- a/arch/arm/include/asm/arch-g12a/gpio.h
+++ b/arch/arm/include/asm/arch-g12a/gpio.h
@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * (C) Copyright 2017 - Beniamino Galvani <b.galvani@gmail.com>
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __ASM_ARCH_MESON_GPIO_H
diff --git a/arch/arm/include/asm/arch-g12a/io.h b/arch/arm/include/asm/arch-g12a/io.h
index 8640303..4035ee8 100644
--- a/arch/arm/include/asm/arch-g12a/io.h
+++ b/arch/arm/include/asm/arch-g12a/io.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/io.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __MACH_MESSON_REGS_IO_H
#define __MACH_MESSON_REGS_IO_H
@@ -25,12 +9,14 @@
#ifndef __ASSEMBLY__
#include <asm/io.h>
-#define IO_CBUS_BASE (0xFFD00000L)
-#define IO_AXI_BUS_BASE (0xFFB00000L) /* gpv */
-#define IO_AHB_BUS_BASE (0xFF500000L) /* usb0 */
-#define IO_APB_BUS_BASE (0xFFFC0000L) /* AHB SRAM, sec/sys ahb? txlx_mem_map.xlsx */
-#define IO_APB_HDMI_BUS_BASE (0xFFE00000L) /* */
-#define IO_VPU_BUS_BASE (0xFF900000L) /* VPU */
+#include <asm/arch/register.h>
+
+//#define IO_CBUS_BASE (0xFFD00000L)
+//#define IO_AXI_BUS_BASE (0xFFB00000L) /* gpv */
+//#define IO_AHB_BUS_BASE (0xFF500000L) /* usb0 */
+//#define IO_APB_BUS_BASE (0xFFFC0000L) /* AHB SRAM, sec/sys ahb? txlx_mem_map.xlsx */
+//#define IO_APB_HDMI_BUS_BASE (0xFFE00000L) /* */
+//#define IO_VPU_BUS_BASE (0xFF900000L) /* VPU */
#define CBUS_REG_OFFSET(reg) ((reg) << 2)
#define CBUS_REG_ADDR(reg) (IO_CBUS_BASE + CBUS_REG_OFFSET(reg))
diff --git a/arch/arm/include/asm/arch-g12a/mailbox.h b/arch/arm/include/asm/arch-g12a/mailbox.h
index a5fd4bf..63bffec 100644
--- a/arch/arm/include/asm/arch-g12a/mailbox.h
+++ b/arch/arm/include/asm/arch-g12a/mailbox.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/mailbox.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
/*
*
diff --git a/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_ddr3.h b/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_ddr3.h
index 496f3b7..c067367 100644
--- a/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_ddr3.h
+++ b/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_ddr3.h
@@ -1,6 +1,6 @@
-
-/** \file
- * \brief defines _PMU_SMB_DDR3U_1D data structure
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
/** \brief DDR3U_1D training firmware message block structure
diff --git a/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_ddr4.h b/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_ddr4.h
index fa3e4a6..6dfd4d0 100644
--- a/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_ddr4.h
+++ b/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_ddr4.h
@@ -1,6 +1,6 @@
-
-/** \file
- * \brief defines _PMU_SMB_DDR4U_1D data structure
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
/** \brief DDR4U_1D training firmware message block structure
diff --git a/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_ddr4_2d.h b/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_ddr4_2d.h
index 5131262..35b1e23 100644
--- a/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_ddr4_2d.h
+++ b/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_ddr4_2d.h
@@ -1,6 +1,6 @@
-
-/** \file
- * \brief defines _PMU_SMB_DDR4U_2D data structure
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
/** \brief DDR4U_2D training firmware message block structure
diff --git a/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_lpddr3.h b/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_lpddr3.h
index c30b3c4..6850d06 100644
--- a/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_lpddr3.h
+++ b/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_lpddr3.h
@@ -1,6 +1,6 @@
-
-/** \file
- * \brief defines _PMU_SMB_LPDDR3_1D data structure
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
/** \brief LPDDR3_1D training firmware message block structure
diff --git a/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_lpddr4.h b/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_lpddr4.h
index c574c3c..d194621 100644
--- a/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_lpddr4.h
+++ b/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_lpddr4.h
@@ -1,6 +1,6 @@
-
-/** \file
- * \brief defines _PMU_SMB_LPDDR4_1D data structure
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
/** \brief LPDDR4_1D training firmware message block structure
diff --git a/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_lpddr4_2d.h b/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_lpddr4_2d.h
index 5a4d62a..c6ab3d3 100644
--- a/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_lpddr4_2d.h
+++ b/arch/arm/include/asm/arch-g12a/mnPmuSramMsgBlock_lpddr4_2d.h
@@ -1,6 +1,6 @@
-
-/** \file
- * \brief defines _PMU_SMB_LPDDR4_2D data structure
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
/** \brief LPDDR4_2D training firmware message block structure
diff --git a/arch/arm/include/asm/arch-g12a/nand.h b/arch/arm/include/asm/arch-g12a/nand.h
index 8ab9f42..91484ac 100644
--- a/arch/arm/include/asm/arch-g12a/nand.h
+++ b/arch/arm/include/asm/arch-g12a/nand.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/nand.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __NAND_H__
#define __NAND_H__
diff --git a/arch/arm/include/asm/arch-g12a/oscring.h b/arch/arm/include/asm/arch-g12a/oscring.h
index 7140d7f..321bead 100644
--- a/arch/arm/include/asm/arch-g12a/oscring.h
+++ b/arch/arm/include/asm/arch-g12a/oscring.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __OSCRING_H__
#define __OSCRING_H__
diff --git a/arch/arm/include/asm/arch-g12a/pinctrl_init.h b/arch/arm/include/asm/arch-g12a/pinctrl_init.h
index 31d20b2..cfbc42a 100644
--- a/arch/arm/include/asm/arch-g12a/pinctrl_init.h
+++ b/arch/arm/include/asm/arch-g12a/pinctrl_init.h
@@ -1,8 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
- * Author: Xingyu Chen <xingyu.chen@amlogic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef _MESON_PINCTRL_INIT_H_
diff --git a/arch/arm/include/asm/arch-g12a/pll.h b/arch/arm/include/asm/arch-g12a/pll.h
index d1a4929..3fcb514 100644
--- a/arch/arm/include/asm/arch-g12a/pll.h
+++ b/arch/arm/include/asm/arch-g12a/pll.h
@@ -1,3 +1,7 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __PLL_H
#define __PLL_H
diff --git a/arch/arm/include/asm/arch-g12a/reboot.h b/arch/arm/include/asm/arch-g12a/reboot.h
index 0cdc3cd..50ca64a 100644
--- a/arch/arm/include/asm/arch-g12a/reboot.h
+++ b/arch/arm/include/asm/arch-g12a/reboot.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/reboot.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __REBOOT_H
#define __REBOOT_H
@@ -35,7 +19,7 @@
8: Shutdown reboot shutdown_reboot
9: RPMBP reboot rpmbp
10: quiescent reboot quiescent reboot
-11: Crash dump crash_dump
+11 : rescueparty rollback in AB mode
12: Kernel panic kernel_panic
13: Watchdog reboot watchdog_reboot
14: quiescent recovery reboot quiescent recovery
@@ -52,7 +36,7 @@
#define AMLOGIC_SHUTDOWN_REBOOT 8
#define AMLOGIC_RPMBP_REBOOT 9
#define AMLOGIC_QUIESCENT_REBOOT 10
-#define AMLOGIC_CRASH_REBOOT 11
+#define AMLOGIC_RESCUEPARTY_REBOOT 11
#define AMLOGIC_KERNEL_PANIC 12
#define AMLOGIC_WATCHDOG_REBOOT 13
#define AMLOGIC_RECOVERY_QUIESCENT_REBOOT 14
diff --git a/arch/arm/include/asm/arch-g12a/register.h b/arch/arm/include/asm/arch-g12a/register.h
index aa342a5..8720271 100644
--- a/arch/arm/include/asm/arch-g12a/register.h
+++ b/arch/arm/include/asm/arch-g12a/register.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/register.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __REGISTER_H__
#define __REGISTER_H__
diff --git a/arch/arm/include/asm/arch-g12a/regs.h b/arch/arm/include/asm/arch-g12a/regs.h
index af9fa9b..634ef31 100644
--- a/arch/arm/include/asm/arch-g12a/regs.h
+++ b/arch/arm/include/asm/arch-g12a/regs.h
@@ -1,10 +1,8 @@
-// ----------------------------------------------------------------------
-// regs.h header
-//
-// bus base define, update manually
-//
-// ----------------------------------------------------------------------
-//
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef _BASE_REGISTER
#define _BASE_REGISTER
#define REG_BASE_AOBUS (0xFF800000L)
@@ -13318,8 +13316,8 @@
#define P_WATCHDOG_CNTL1 (volatile unsigned int *)((0x3c35 << 2) + 0xffd00000)
#define WATCHDOG_TCNT (0x3c36)
#define P_WATCHDOG_TCNT (volatile unsigned int *)((0x3c36 << 2) + 0xffd00000)
-#define WATCHDOG_RESET (0x3c37)
-#define P_WATCHDOG_RESET (volatile unsigned int *)((0x3c37 << 2) + 0xffd00000)
+#define WATCHDOG_RST (0x3c37)
+#define P_WATCHDOG_RST (volatile unsigned int *)((0x3c37 << 2) + 0xffd00000)
// -----------------------------------------------------------
#define AHB_ARBITER_REG (0x3c42)
#define P_AHB_ARBITER_REG (volatile unsigned int *)((0x3c42 << 2) + 0xffd00000)
@@ -32583,7 +32581,6 @@
//===========================================================================
// -----------------------------------------------
// CBUS_BASE: DSI_CBUS_BASE = 0x1c
-#define MIPI_DSI_REGISTER
// -----------------------------------------------
//------------------------------------------------------------------------------
// DWC IP registers: Synopsys IP, please refer to MIPI DSI HOST Databook
@@ -32780,3 +32777,185 @@
// synopsys translate_on
//
// Closing file: dsi_regs.h
+#define VD1_HDR2_CTRL 0x3800
+#define VD1_HDR2_CLK_GATE 0x3801
+#define VD1_HDR2_MATRIXI_COEF00_01 0x3802
+#define VD1_HDR2_MATRIXI_COEF02_10 0x3803
+#define VD1_HDR2_MATRIXI_COEF11_12 0x3804
+#define VD1_HDR2_MATRIXI_COEF20_21 0x3805
+#define VD1_HDR2_MATRIXI_COEF22 0x3806
+#define VD1_HDR2_MATRIXI_COEF30_31 0x3807
+#define VD1_HDR2_MATRIXI_COEF32_40 0x3808
+#define VD1_HDR2_MATRIXI_COEF41_42 0x3809
+#define VD1_HDR2_MATRIXI_OFFSET0_1 0x380a
+#define VD1_HDR2_MATRIXI_OFFSET2 0x380b
+#define VD1_HDR2_MATRIXI_PRE_OFFSET0_1 0x380c
+#define VD1_HDR2_MATRIXI_PRE_OFFSET2 0x380d
+#define VD1_HDR2_MATRIXO_COEF00_01 0x380e
+#define VD1_HDR2_MATRIXO_COEF02_10 0x380f
+#define VD1_HDR2_MATRIXO_COEF11_12 0x3810
+#define VD1_HDR2_MATRIXO_COEF20_21 0x3811
+#define VD1_HDR2_MATRIXO_COEF22 0x3812
+#define VD1_HDR2_MATRIXO_COEF30_31 0x3813
+#define VD1_HDR2_MATRIXO_COEF32_40 0x3814
+#define VD1_HDR2_MATRIXO_COEF41_42 0x3815
+#define VD1_HDR2_MATRIXO_OFFSET0_1 0x3816
+#define VD1_HDR2_MATRIXO_OFFSET2 0x3817
+#define VD1_HDR2_MATRIXO_PRE_OFFSET0_1 0x3818
+#define VD1_HDR2_MATRIXO_PRE_OFFSET2 0x3819
+#define VD1_HDR2_MATRIXI_CLIP 0x381a
+#define VD1_HDR2_MATRIXO_CLIP 0x381b
+#define VD1_HDR2_CGAIN_OFFT 0x381c
+#define VD1_EOTF_LUT_ADDR_PORT 0x381e
+#define VD1_EOTF_LUT_DATA_PORT 0x381f
+#define VD1_OETF_LUT_ADDR_PORT 0x3820
+#define VD1_OETF_LUT_DATA_PORT 0x3821
+#define VD1_CGAIN_LUT_ADDR_PORT 0x3822
+#define VD1_CGAIN_LUT_DATA_PORT 0x3823
+#define VD1_HDR2_CGAIN_COEF0 0x3824
+#define VD1_HDR2_CGAIN_COEF1 0x3825
+#define VD1_OGAIN_LUT_ADDR_PORT 0x3826
+#define VD1_OGAIN_LUT_DATA_PORT 0x3827
+#define VD1_HDR2_ADPS_CTRL 0x3828
+#define VD1_HDR2_ADPS_ALPHA0 0x3829
+#define VD1_HDR2_ADPS_ALPHA1 0x382a
+#define VD1_HDR2_ADPS_BETA0 0x382b
+#define VD1_HDR2_ADPS_BETA1 0x382c
+#define VD1_HDR2_ADPS_BETA2 0x382d
+#define VD1_HDR2_ADPS_COEF0 0x382e
+#define VD1_HDR2_ADPS_COEF1 0x382f
+#define VD1_HDR2_GMUT_CTRL 0x3830
+#define VD1_HDR2_GMUT_COEF0 0x3831
+#define VD1_HDR2_GMUT_COEF1 0x3832
+#define VD1_HDR2_GMUT_COEF2 0x3833
+#define VD1_HDR2_GMUT_COEF3 0x3834
+#define VD1_HDR2_GMUT_COEF4 0x3835
+#define VD1_HDR2_PIPE_CTRL1 0x3836
+#define VD1_HDR2_PIPE_CTRL2 0x3837
+#define VD1_HDR2_PIPE_CTRL3 0x3838
+#define VD1_HDR2_PROC_WIN1 0x3839
+#define VD1_HDR2_PROC_WIN2 0x383a
+#define VD1_HDR2_MATRIXI_EN_CTRL 0x383b
+#define VD1_HDR2_MATRIXO_EN_CTRL 0x383c
+
+#define VD2_HDR2_CTRL 0x3850
+#define VD2_HDR2_CLK_GATE 0x3851
+#define VD2_HDR2_MATRIXI_COEF00_01 0x3852
+#define VD2_HDR2_MATRIXI_COEF02_10 0x3853
+#define VD2_HDR2_MATRIXI_COEF11_12 0x3854
+#define VD2_HDR2_MATRIXI_COEF20_21 0x3855
+#define VD2_HDR2_MATRIXI_COEF22 0x3856
+#define VD2_HDR2_MATRIXI_COEF30_31 0x3857
+#define VD2_HDR2_MATRIXI_COEF32_40 0x3858
+#define VD2_HDR2_MATRIXI_COEF41_42 0x3859
+#define VD2_HDR2_MATRIXI_OFFSET0_1 0x385a
+#define VD2_HDR2_MATRIXI_OFFSET2 0x385b
+#define VD2_HDR2_MATRIXI_PRE_OFFSET0_1 0x385c
+#define VD2_HDR2_MATRIXI_PRE_OFFSET2 0x385d
+#define VD2_HDR2_MATRIXO_COEF00_01 0x385e
+#define VD2_HDR2_MATRIXO_COEF02_10 0x385f
+#define VD2_HDR2_MATRIXO_COEF11_12 0x3860
+#define VD2_HDR2_MATRIXO_COEF20_21 0x3861
+#define VD2_HDR2_MATRIXO_COEF22 0x3862
+#define VD2_HDR2_MATRIXO_COEF30_31 0x3863
+#define VD2_HDR2_MATRIXO_COEF32_40 0x3864
+#define VD2_HDR2_MATRIXO_COEF41_42 0x3865
+#define VD2_HDR2_MATRIXO_OFFSET0_1 0x3866
+#define VD2_HDR2_MATRIXO_OFFSET2 0x3867
+#define VD2_HDR2_MATRIXO_PRE_OFFSET0_1 0x3868
+#define VD2_HDR2_MATRIXO_PRE_OFFSET2 0x3869
+#define VD2_HDR2_MATRIXI_CLIP 0x386a
+#define VD2_HDR2_MATRIXO_CLIP 0x386b
+#define VD2_HDR2_CGAIN_OFFT 0x386c
+#define VD2_EOTF_LUT_ADDR_PORT 0x386e
+#define VD2_EOTF_LUT_DATA_PORT 0x386f
+#define VD2_OETF_LUT_ADDR_PORT 0x3870
+#define VD2_OETF_LUT_DATA_PORT 0x3871
+#define VD2_CGAIN_LUT_ADDR_PORT 0x3872
+#define VD2_CGAIN_LUT_DATA_PORT 0x3873
+#define VD2_HDR2_CGAIN_COEF0 0x3874
+#define VD2_HDR2_CGAIN_COEF1 0x3875
+#define VD2_OGAIN_LUT_ADDR_PORT 0x3876
+#define VD2_OGAIN_LUT_DATA_PORT 0x3877
+#define VD2_HDR2_ADPS_CTRL 0x3878
+#define VD2_HDR2_ADPS_ALPHA0 0x3879
+#define VD2_HDR2_ADPS_ALPHA1 0x387a
+#define VD2_HDR2_ADPS_BETA0 0x387b
+#define VD2_HDR2_ADPS_BETA1 0x387c
+#define VD2_HDR2_ADPS_BETA2 0x387d
+#define VD2_HDR2_ADPS_COEF0 0x387e
+#define VD2_HDR2_ADPS_COEF1 0x387f
+#define VD2_HDR2_GMUT_CTRL 0x3880
+#define VD2_HDR2_GMUT_COEF0 0x3881
+#define VD2_HDR2_GMUT_COEF1 0x3882
+#define VD2_HDR2_GMUT_COEF2 0x3883
+#define VD2_HDR2_GMUT_COEF3 0x3884
+#define VD2_HDR2_GMUT_COEF4 0x3885
+#define VD2_HDR2_PIPE_CTRL1 0x3886
+#define VD2_HDR2_PIPE_CTRL2 0x3887
+#define VD2_HDR2_PIPE_CTRL3 0x3888
+#define VD2_HDR2_PROC_WIN1 0x3889
+#define VD2_HDR2_PROC_WIN2 0x388a
+#define VD2_HDR2_MATRIXI_EN_CTRL 0x388b
+#define VD2_HDR2_MATRIXO_EN_CTRL 0x388c
+
+#define OSD1_HDR2_CTRL 0x38a0
+#define OSD1_HDR2_CLK_GATE 0x38a1
+#define OSD1_HDR2_MATRIXI_COEF00_01 0x38a2
+#define OSD1_HDR2_MATRIXI_COEF02_10 0x38a3
+#define OSD1_HDR2_MATRIXI_COEF11_12 0x38a4
+#define OSD1_HDR2_MATRIXI_COEF20_21 0x38a5
+#define OSD1_HDR2_MATRIXI_COEF22 0x38a6
+#define OSD1_HDR2_MATRIXI_COEF30_31 0x38a7
+#define OSD1_HDR2_MATRIXI_COEF32_40 0x38a8
+#define OSD1_HDR2_MATRIXI_COEF41_42 0x38a9
+#define OSD1_HDR2_MATRIXI_OFFSET0_1 0x38aa
+#define OSD1_HDR2_MATRIXI_OFFSET2 0x38ab
+#define OSD1_HDR2_MATRIXI_PRE_OFFSET0_1 0x38ac
+#define OSD1_HDR2_MATRIXI_PRE_OFFSET2 0x38ad
+#define OSD1_HDR2_MATRIXO_COEF00_01 0x38ae
+#define OSD1_HDR2_MATRIXO_COEF02_10 0x38af
+#define OSD1_HDR2_MATRIXO_COEF11_12 0x38b0
+#define OSD1_HDR2_MATRIXO_COEF20_21 0x38b1
+#define OSD1_HDR2_MATRIXO_COEF22 0x38b2
+#define OSD1_HDR2_MATRIXO_COEF30_31 0x38b3
+#define OSD1_HDR2_MATRIXO_COEF32_40 0x38b4
+#define OSD1_HDR2_MATRIXO_COEF41_42 0x38b5
+#define OSD1_HDR2_MATRIXO_OFFSET0_1 0x38b6
+#define OSD1_HDR2_MATRIXO_OFFSET2 0x38b7
+#define OSD1_HDR2_MATRIXO_PRE_OFFSET0_1 0x38b8
+#define OSD1_HDR2_MATRIXO_PRE_OFFSET2 0x38b9
+#define OSD1_HDR2_MATRIXI_CLIP 0x38ba
+#define OSD1_HDR2_MATRIXO_CLIP 0x38bb
+#define OSD1_HDR2_CGAIN_OFFT 0x38bc
+#define OSD1_EOTF_LUT_ADDR_PORT 0x38be
+#define OSD1_EOTF_LUT_DATA_PORT 0x38bf
+#define OSD1_OETF_LUT_ADDR_PORT 0x38c0
+#define OSD1_OETF_LUT_DATA_PORT 0x38c1
+#define OSD1_CGAIN_LUT_ADDR_PORT 0x38c2
+#define OSD1_CGAIN_LUT_DATA_PORT 0x38c3
+#define OSD1_HDR2_CGAIN_COEF0 0x38c4
+#define OSD1_HDR2_CGAIN_COEF1 0x38c5
+#define OSD1_OGAIN_LUT_ADDR_PORT 0x38c6
+#define OSD1_OGAIN_LUT_DATA_PORT 0x38c7
+#define OSD1_HDR2_ADPS_CTRL 0x38c8
+#define OSD1_HDR2_ADPS_ALPHA0 0x38c9
+#define OSD1_HDR2_ADPS_ALPHA1 0x38ca
+#define OSD1_HDR2_ADPS_BETA0 0x38cb
+#define OSD1_HDR2_ADPS_BETA1 0x38cc
+#define OSD1_HDR2_ADPS_BETA2 0x38cd
+#define OSD1_HDR2_ADPS_COEF0 0x38ce
+#define OSD1_HDR2_ADPS_COEF1 0x38cf
+#define OSD1_HDR2_GMUT_CTRL 0x38d0
+#define OSD1_HDR2_GMUT_COEF0 0x38d1
+#define OSD1_HDR2_GMUT_COEF1 0x38d2
+#define OSD1_HDR2_GMUT_COEF2 0x38d3
+#define OSD1_HDR2_GMUT_COEF3 0x38d4
+#define OSD1_HDR2_GMUT_COEF4 0x38d5
+#define OSD1_HDR2_PIPE_CTRL1 0x38d6
+#define OSD1_HDR2_PIPE_CTRL2 0x38d7
+#define OSD1_HDR2_PIPE_CTRL3 0x38d8
+#define OSD1_HDR2_PROC_WIN1 0x38d9
+#define OSD1_HDR2_PROC_WIN2 0x38da
+#define OSD1_HDR2_MATRIXI_EN_CTRL 0x38db
+#define OSD1_HDR2_MATRIXO_EN_CTRL 0x38dc
diff --git a/arch/arm/include/asm/arch-g12a/romboot.h b/arch/arm/include/asm/arch-g12a/romboot.h
index 338365e..2967fbb 100644
--- a/arch/arm/include/asm/arch-g12a/romboot.h
+++ b/arch/arm/include/asm/arch-g12a/romboot.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/romboot.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __BOOT_ROM_H_
#define __BOOT_ROM_H_
diff --git a/arch/arm/include/asm/arch-g12a/saradc.h b/arch/arm/include/asm/arch-g12a/saradc.h
deleted file mode 100644
index 13d2d73..0000000
--- a/arch/arm/include/asm/arch-g12a/saradc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __MESON_SARADC_H__
-#define __MESON_SARADC_H__
-
-#include <adc.h>
-
-enum ADC_CHANNEL_TYPE {
- MESON_SARADC_CH0 = 0,
- MESON_SARADC_CH1,
- MESON_SARADC_CH2,
- MESON_SARADC_CH3,
- MESON_SARADC_CH4,
- MESON_SARADC_CH5,
- MESON_SARADC_CH6,
- MESON_SARADC_CH7,
- MESON_SARADC_CH_MAX,
-};
-
-#define SARADC_CH_SELF_TEST MESON_SARADC_CH7
-
-#endif /*_MESON_SARADC_H_*/
diff --git a/arch/arm/include/asm/arch-g12a/sd_emmc.h b/arch/arm/include/asm/arch-g12a/sd_emmc.h
index 44011cc..e8239b4 100644
--- a/arch/arm/include/asm/arch-g12a/sd_emmc.h
+++ b/arch/arm/include/asm/arch-g12a/sd_emmc.h
@@ -1,12 +1,11 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * (C) Copyright 2016 Carlo Caione <carlo@caione.org>
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __SD_EMMC_H__
#define __SD_EMMC_H__
-#include <clk.h>
#include <mmc.h>
#define SDIO_PORT_A 0
@@ -68,57 +67,57 @@
#define Cfg_adj_init 23
#define MESON_SD_EMMC_START 0x40
-#define CFG_DESC_INIT BIT(0)
-#define CFG_DESC_BUSY BIT(1)
-#define CFG_DESC_ADDR 2
+#define CFG_DESC_INIT BIT(0)
+#define CFG_DESC_BUSY BIT(1)
+#define CFG_DESC_ADDR 2
#define MESON_SD_EMMC_CFG 0x44
-#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
-#define CFG_BUS_WIDTH_1 0
-#define CFG_BUS_WIDTH_4 1
-#define CFG_BUS_WIDTH_8 2
-#define CFG_DDR BIT(2)
-#define CFG_BL_LEN_MASK GENMASK(7, 4)
-#define CFG_BL_LEN_SHIFT 4
-#define CFG_BL_LEN_512 (9 << 4)
-#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
-#define CFG_RESP_TIMEOUT_256 (8 << 8)
-#define CFG_RC_CC_MASK GENMASK(15, 12)
-#define CFG_RC_CC_16 (4 << 12)
-#define CFG_SDCLK_ALWAYS_ON BIT(18)
-#define CFG_AUTO_CLK BIT(23)
+#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
+#define CFG_BUS_WIDTH_1 0
+#define CFG_BUS_WIDTH_4 1
+#define CFG_BUS_WIDTH_8 2
+#define CFG_DDR BIT(2)
+#define CFG_BL_LEN_MASK GENMASK(7, 4)
+#define CFG_BL_LEN_SHIFT 4
+#define CFG_BL_LEN_512 (9 << 4)
+#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
+#define CFG_RESP_TIMEOUT_256 (8 << 8)
+#define CFG_RC_CC_MASK GENMASK(15, 12)
+#define CFG_RC_CC_16 (4 << 12)
+#define CFG_SDCLK_ALWAYS_ON BIT(18)
+#define CFG_AUTO_CLK BIT(23)
#define MESON_SD_EMMC_STATUS 0x48
-#define STATUS_MASK GENMASK(15, 0)
-#define STATUS_ERR_MASK GENMASK(12, 0)
-#define STATUS_RXD_ERR_MASK GENMASK(7, 0)
-#define STATUS_TXD_ERR BIT(8)
-#define STATUS_DESC_ERR BIT(9)
-#define STATUS_RESP_ERR BIT(10)
-#define STATUS_RESP_TIMEOUT BIT(11)
-#define STATUS_DESC_TIMEOUT BIT(12)
-#define STATUS_END_OF_CHAIN BIT(13)
+#define STATUS_MASK GENMASK(15, 0)
+#define STATUS_ERR_MASK GENMASK(12, 0)
+#define STATUS_RXD_ERR_MASK GENMASK(7, 0)
+#define STATUS_TXD_ERR BIT(8)
+#define STATUS_DESC_ERR BIT(9)
+#define STATUS_RESP_ERR BIT(10)
+#define STATUS_RESP_TIMEOUT BIT(11)
+#define STATUS_DESC_TIMEOUT BIT(12)
+#define STATUS_END_OF_CHAIN BIT(13)
#define MESON_SD_EMMC_IRQ_EN 0x4c
#define MESON_SD_EMMC_CMD_CFG 0x50
-#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
-#define CMD_CFG_BLOCK_MODE BIT(9)
-#define CMD_CFG_R1B BIT(10)
-#define CMD_CFG_END_OF_CHAIN BIT(11)
-#define CMD_CFG_TIMEOUT_4S (12 << 12)
-#define CMD_CFG_NO_RESP BIT(16)
-#define CMD_CFG_NO_CMD BIT(17)
-#define CMD_CFG_DATA_IO BIT(18)
-#define CMD_CFG_DATA_WR BIT(19)
-#define CMD_CFG_RESP_NOCRC BIT(20)
-#define CMD_CFG_RESP_128 BIT(21)
-#define CMD_CFG_RESP_NUM BIT(22)
-#define CMD_CFG_DATA_NUM BIT(23)
-#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
-#define CMD_CFG_CMD_INDEX_SHIFT 24
-#define CMD_CFG_ERR BIT(30)
-#define CMD_CFG_OWNER BIT(31)
+#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
+#define CMD_CFG_BLOCK_MODE BIT(9)
+#define CMD_CFG_R1B BIT(10)
+#define CMD_CFG_END_OF_CHAIN BIT(11)
+#define CMD_CFG_TIMEOUT_4S (12 << 12)
+#define CMD_CFG_NO_RESP BIT(16)
+#define CMD_CFG_NO_CMD BIT(17)
+#define CMD_CFG_DATA_IO BIT(18)
+#define CMD_CFG_DATA_WR BIT(19)
+#define CMD_CFG_RESP_NOCRC BIT(20)
+#define CMD_CFG_RESP_128 BIT(21)
+#define CMD_CFG_RESP_NUM BIT(22)
+#define CMD_CFG_DATA_NUM BIT(23)
+#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
+#define CMD_CFG_CMD_INDEX_SHIFT 24
+#define CMD_CFG_ERR BIT(30)
+#define CMD_CFG_OWNER BIT(31)
#define MESON_SD_EMMC_CMD_ARG 0x54
#define MESON_SD_EMMC_CMD_DAT 0x58
@@ -134,27 +133,4 @@
#define SD_EMMC_RESP_TIMEOUT_ERROR (1 << 4)
#define SD_EMMC_DESC_TIMEOUT_ERROR (1 << 5)
-struct meson_host {
- struct mmc *mmc;
- uint is_in;
- uint is_tuning;
- struct clk core;
- struct clk xtal;
- struct clk div2;
- struct clk mux;
- struct clk div;
- struct clk gate;
- struct gpio_desc gpio_cd;
- struct gpio_desc gpio_reset;
- char *blk_test;
- char* desc_buf;
-};
-
-struct meson_mmc_platdata {
- struct mmc_config cfg;
- struct mmc mmc;
- void *regbase;
- void *w_buf;
-};
-
#endif
diff --git a/arch/arm/include/asm/arch-g12a/secure_apb.h b/arch/arm/include/asm/arch-g12a/secure_apb.h
index 3b3a984..30652a7 100644
--- a/arch/arm/include/asm/arch-g12a/secure_apb.h
+++ b/arch/arm/include/asm/arch-g12a/secure_apb.h
@@ -1,15 +1,8 @@
-// ----------------------------------------------------------------------
-// This file is automatically generated from the script:
-//
-// ./create_headers_from_register_map_h.pl
-//
-// and was applied to the file
-//
-// ./register_map.h
-//
-// DO NOT EDIT!!!!!
-// ----------------------------------------------------------------------
-//
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include <asm/arch/regs.h>
#ifdef REGISTER_H
diff --git a/arch/arm/include/asm/arch-g12a/timer.h b/arch/arm/include/asm/arch-g12a/timer.h
index 6710403..492cc8d 100644
--- a/arch/arm/include/asm/arch-g12a/timer.h
+++ b/arch/arm/include/asm/arch-g12a/timer.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/timer.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __TIMER_H
#define __TIMER_H
diff --git a/arch/arm/include/asm/arch-g12a/timing.h b/arch/arm/include/asm/arch-g12a/timing.h
old mode 100755
new mode 100644
index 3529dce..10152a3
--- a/arch/arm/include/asm/arch-g12a/timing.h
+++ b/arch/arm/include/asm/arch-g12a/timing.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/timing.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __AML_TIMING_H_
#define __AML_TIMING_H_
@@ -54,104 +38,167 @@
/* etc... */
typedef struct bl2_reg {
- unsigned int reg;
- unsigned int value;
- unsigned int mask;
- unsigned short udelay;
- unsigned char flag;
- unsigned char rsv_0;
+ unsigned int reg;
+ unsigned int value;
+ unsigned int mask;
+ unsigned short udelay;
+ unsigned char flag;
+ unsigned char rsv_0;
}__attribute__ ((packed)) bl2_reg_t;
typedef struct ddr_reg {
- unsigned int reg;
- unsigned int value;
- unsigned int mask;
- unsigned short udelay;
- unsigned char flag;
- unsigned char rsv_0;
+ unsigned int reg;
+ unsigned int value;
+ unsigned int mask;
+ unsigned short udelay;
+ unsigned char flag;
+ unsigned char rsv_0;
}__attribute__ ((packed)) ddr_reg_t;
+typedef struct training_delay_set_ps{
+ unsigned char ac_trace_delay[10];
+ unsigned char ac_trace_delay_rev[2];
+ unsigned char read_dqs_delay[16];
+ unsigned char read_dq_bit_delay[72];
+ unsigned short write_dqs_delay[16];
+// */
+ unsigned short write_dq_bit_delay[72];
+ unsigned short read_dqs_gate_delay[16];
+ unsigned char soc_bit_vref[36];
+ unsigned char dram_bit_vref[32];
+ ///*
+ unsigned char rever1;//read_dqs read_dq,write_dqs, write_dq
+ unsigned char dfi_mrl;
+ unsigned char dfi_hwtmrl;
+ unsigned char ARdPtrInitVal;
+ unsigned short csr_vrefinglobal;
+ unsigned short csr_dqsrcvcntrl[4];
+ unsigned short csr_pptdqscntinvtrntg0[4];
+ unsigned short csr_pptdqscntinvtrntg1[4];
+ unsigned short csr_seq0bgpr[9];
+ unsigned short csr_dllgainctl;
+ unsigned short csr_dlllockpara;
+// unsigned short rever2;
+}__attribute__ ((packed)) training_delay_set_ps_t;
+
+typedef struct ddr_mrs_reg {
+ unsigned int cfg_ddr_mr[8];
+ unsigned int cfg_ddr_mr11;
+ unsigned int cfg_ddr_mr12;
+ unsigned int cfg_ddr_mr13;
+ unsigned int cfg_ddr_mr14;
+ unsigned int cfg_ddr_mr16;
+ unsigned int cfg_ddr_mr17;
+ unsigned int cfg_ddr_mr22;
+ unsigned int cfg_ddr_mr24;
+}__attribute__ ((packed)) ddr_mrs_reg_t;
+
typedef struct ddr_timing{
- unsigned int identifier;
- unsigned int cfg_ddr_mrd;
- unsigned int cfg_ddr_rfcab;
- unsigned int cfg_ddr_rfcpb;
- unsigned int cfg_ddr_rpab;
- unsigned int cfg_ddr_rppb;
- unsigned int cfg_ddr_rtw;
- unsigned int cfg_ddr_rl;
- unsigned int cfg_ddr_wl;
- unsigned int cfg_ddr_ras;
- unsigned int cfg_ddr_rc;
- unsigned int cfg_ddr_rcd;
- unsigned int cfg_ddr_rrds;
- unsigned int cfg_ddr_rrdl;
- unsigned int cfg_ddr_faw;
- unsigned int cfg_ddr_rtp;
- unsigned int cfg_ddr_wr;
- unsigned int cfg_ddr_wtrs;
- unsigned int cfg_ddr_wtrl;
- unsigned int cfg_ddr_ccds;
- unsigned int cfg_ddr_ccdl;
- unsigned int cfg_ddr_exsr;
- unsigned int cfg_ddr_xs;
- unsigned int cfg_ddr_xp;
- unsigned int cfg_ddr_xpdll;
- unsigned int cfg_ddr_zqcs;
- unsigned int cfg_ddr_cksre;
- unsigned int cfg_ddr_cksrx;
- unsigned int cfg_ddr_cke;
- unsigned int cfg_ddr_mod;
- unsigned int cfg_ddr_dqs;
- unsigned int cfg_ddr_rstl;
- unsigned int cfg_ddr_zqlat;
- unsigned int cfg_ddr_mrr;
- unsigned int cfg_ddr_ckesr;
- unsigned int cfg_ddr_dpd;
- unsigned int cfg_ddr_ckeck;
- unsigned int cfg_ddr_refi;
- unsigned int cfg_ddr_sr;
- unsigned int cfg_ddr_ccdmw;
- unsigned int cfg_ddr_escke;
- unsigned int cfg_ddr_refi_ddr3;
- unsigned int cfg_ddr_dfictrldelay;
- unsigned int cfg_ddr_dfiphywrdata;
- unsigned int cfg_ddr_dfiphywrlat;
- unsigned int cfg_ddr_dfiphyrddataen;
- unsigned int cfg_ddr_dfiphyrdlat;
- unsigned int cfg_ddr_dfictrlupdmin;
- unsigned int cfg_ddr_dfictrlupdmax;
- unsigned int cfg_ddr_dfimstrresp;
- unsigned int cfg_ddr_dfirefmski;
- unsigned int cfg_ddr_dfictrlupdi;
- unsigned int cfg_ddr_dfidramclk;
- unsigned int cfg_ddr_dfilpresp;
- unsigned int cfg_ddr_dfiphymstr;
- unsigned int cfg_ddr_rtodt;
- unsigned int cfg_ddr_wlmrd;
- unsigned int cfg_ddr_wlo;
- unsigned int cfg_ddr_al;
- unsigned int cfg_ddr_zqcl;
- unsigned int cfg_ddr_zqcsi;
- unsigned int cfg_ddr_zqreset;
- unsigned int cfg_ddr_tdqsck_min;
- unsigned int cfg_ddr_tdqsck_max;
- unsigned int cfg_ddr_mr[8];
- unsigned int cfg_ddr_mr11;
- unsigned int cfg_ddr_mr12;
- unsigned int cfg_ddr_mr13;
- unsigned int cfg_ddr_mr14;
- unsigned int cfg_ddr_mr16;
- unsigned int cfg_ddr_mr17;
- unsigned int cfg_ddr_mr22;
- unsigned int cfg_ddr_mr24;
- unsigned int cfg_ddr_reserve[5];
+ unsigned int identifier;
+ unsigned int cfg_ddr_mrd;
+ unsigned int cfg_ddr_rfcab;
+ unsigned int cfg_ddr_rfcpb;
+ unsigned int cfg_ddr_rpab;
+ unsigned int cfg_ddr_rppb;
+ unsigned int cfg_ddr_rtw;
+ unsigned int cfg_ddr_rl;
+ unsigned int cfg_ddr_wl;
+ unsigned int cfg_ddr_ras;
+ unsigned int cfg_ddr_rc;
+ unsigned int cfg_ddr_rcd;
+ unsigned int cfg_ddr_rrds;
+ unsigned int cfg_ddr_rrdl;
+ unsigned int cfg_ddr_faw;
+ unsigned int cfg_ddr_rtp;
+ unsigned int cfg_ddr_wr;
+ unsigned int cfg_ddr_wtrs;
+ unsigned int cfg_ddr_wtrl;
+ unsigned int cfg_ddr_ccds;
+ unsigned int cfg_ddr_ccdl;
+ unsigned int cfg_ddr_exsr;
+ unsigned int cfg_ddr_xs;
+ unsigned int cfg_ddr_xp;
+ unsigned int cfg_ddr_xpdll;
+ unsigned int cfg_ddr_zqcs;
+ unsigned int cfg_ddr_cksre;
+ unsigned int cfg_ddr_cksrx;
+ unsigned int cfg_ddr_cke;
+ unsigned int cfg_ddr_mod;
+ unsigned int cfg_ddr_dqs;
+ unsigned int cfg_ddr_rstl;
+ unsigned int cfg_ddr_zqlat;
+ unsigned int cfg_ddr_mrr;
+ unsigned int cfg_ddr_ckesr;
+ unsigned int cfg_ddr_dpd;
+ unsigned int cfg_ddr_ckeck;
+ unsigned int cfg_ddr_refi;
+ unsigned int cfg_ddr_sr;
+ unsigned int cfg_ddr_ccdmw;
+ unsigned int cfg_ddr_escke;
+ unsigned int cfg_ddr_refi_ddr3;
+ unsigned int cfg_ddr_dfictrldelay;
+ unsigned int cfg_ddr_dfiphywrdata;
+ unsigned int cfg_ddr_dfiphywrlat;
+ unsigned int cfg_ddr_dfiphyrddataen;
+ unsigned int cfg_ddr_dfiphyrdlat;
+ unsigned int cfg_ddr_dfictrlupdmin;
+ unsigned int cfg_ddr_dfictrlupdmax;
+ unsigned int cfg_ddr_dfimstrresp;
+ unsigned int cfg_ddr_dfirefmski;
+ unsigned int cfg_ddr_dfictrlupdi;
+ unsigned int cfg_ddr_dfidramclk;
+ unsigned int cfg_ddr_dfilpresp;
+ unsigned int cfg_ddr_dfiphymstr;
+ unsigned int cfg_ddr_rtodt;
+ unsigned int cfg_ddr_wlmrd;
+ unsigned int cfg_ddr_wlo;
+ unsigned int cfg_ddr_al;
+ unsigned int cfg_ddr_zqcl;
+ unsigned int cfg_ddr_zqcsi;
+ unsigned int cfg_ddr_zqreset;
+ unsigned int cfg_ddr_tdqsck_min;
+ unsigned int cfg_ddr_tdqsck_max;
+ //training_delay_set_ps_t cfg_ddr_training_delay_ps;
+ ddr_mrs_reg_t cfg_ddr_mrs_reg_ps[2];
+ unsigned int dfi_odt1_config_ps[2];
+ //ddr_mrs_reg_t cfg_ddr_mrs_reg_ps1;
+ #if 0
+ unsigned int cfg_ddr_mr[8];
+ unsigned int cfg_ddr_mr11;
+ unsigned int cfg_ddr_mr12;
+ unsigned int cfg_ddr_mr13;
+ unsigned int cfg_ddr_mr14;
+ unsigned int cfg_ddr_mr16;
+ unsigned int cfg_ddr_mr17;
+ unsigned int cfg_ddr_mr22;
+ unsigned int cfg_ddr_mr24;
+ unsigned int cfg_ddr_reserve[5];
+ #endif
}__attribute__ ((packed)) ddr_timing_t;
+typedef struct ddr_phy_common_extra_set{
+ unsigned short csr_pllctrl3;
+ unsigned short csr_pptctlstatic[4];
+ unsigned short csr_trainingincdecdtsmen[4];
+ unsigned short csr_tsmbyte0[4];
+ unsigned short csr_hwtcamode;
+ unsigned short csr_hwtlpcsena;
+ unsigned short csr_hwtlpcsenb;
+ unsigned short csr_acsmctrl13;
+ unsigned short csr_acsmctrl23;
+ unsigned char csr_soc_vref_dac1_dfe[36];
+}__attribute__ ((packed)) ddr_phy_common_extra_set_t;
+
+typedef struct retraining_set{
+ ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t;
+ training_delay_set_ps_t cfg_ddr_training_delay_ps;
+}__attribute__ ((packed)) retraining_set_t;
+
typedef struct ddr_set{
unsigned int magic;
unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test
//unsigned int rsv_int0;
+ unsigned int ddr_func;
unsigned char board_id;
//board id reserve,,do not modify
unsigned char version;
@@ -187,12 +234,19 @@
/* rsv_char0. update for diagnose type define */
unsigned char diagnose;
+ unsigned short soc_data_drv_ohm_ps1;
+ unsigned short dram_data_drv_ohm_ps1;
+ unsigned short soc_data_odt_ohm_ps1;
+ unsigned short dram_data_odt_ohm_ps1;
+ unsigned short dram_data_wr_odt_ohm_ps1;
+ #if 0
/* imem/dmem define */
unsigned int imem_load_addr;
//system reserve,do not modify
unsigned int dmem_load_addr;
//system reserve,do not modify
unsigned short imem_load_size;
+ #endif
//system reserve,do not modify
unsigned short dmem_load_size;
//system reserve,do not modify
@@ -210,8 +264,9 @@
unsigned short training_SequenceCtrl[2];
//system reserve,do not modify
unsigned char phy_odt_config_rank[2];
- unsigned char rever1;
- unsigned char rever2;
+ //unsigned char rever1;
+ //unsigned char rever2;
+ unsigned short rank1_ca_vref_permil;
//training odt config ,only use for training
// [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
// [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
@@ -301,15 +356,12 @@
//soc init DRAM receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
unsigned short max_core_timmming_frequency;
//use for limited ddr speed core timmming parameter,for some old dram maybe have no over speed register
+ /* align8 */
unsigned char ac_trace_delay[10];
unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting;
//use for lpddr4 read vout voltage setting 0 --->2/5VDDQ ,1--->1/3VDDQ
unsigned char lpddr4_x8_mode;
- //system reserve,do not modify ,take care ,please follow SI
- unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL];
- //use for lpddr3 /lpddr4 ca pinmux remap
- unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL];
unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function
//[1],slt test parameter ,use for force delay line offset
//system reserve,do not modify
@@ -318,63 +370,55 @@
unsigned char bitTimeControl_2d;
//system reserve,do not modify
/* align8 */
-
+ unsigned char char_rev1;
+ unsigned char training_offset;//char_rev2;
unsigned int ddr_dmc_remap[5];
+ unsigned int dram_rtt_nom_wr_park[2];
//system reserve,do not modify
/* align8 */
- unsigned char ddr_lpddr34_ca_remap[4];
+ unsigned char ddr_lpddr34_ca_remap[4];
////use for lpddr3 /lpddr4 ca training data byte lane remap
unsigned char ddr_lpddr34_dq_remap[32];
////use for lpddr3 /lpddr4 ca pinmux remap
- unsigned int dram_rtt_nom_wr_park[2];
- //system reserve,do not modify
- unsigned int ddr_func;
- //system reserve,do not modify
- /* align8 */
+ unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL];
+ //use for lpddr3 /lpddr4 ca pinmux remap
+ unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL];
+ unsigned char char_rev3;
+ unsigned char char_rev4;
+ ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t;
+ training_delay_set_ps_t cfg_ddr_training_delay_ps[2];
- //unsigned long rsv_long0[2];
- /* v1 end */
-// /*
- unsigned char read_dqs_delay[16];
- unsigned char read_dq_bit_delay[72];
- unsigned short write_dqs_delay[16];
-// */
- unsigned short write_dq_bit_delay[72];
- unsigned short read_dqs_gate_delay[16];
- unsigned char soc_bit_vref[32];
- unsigned char dram_bit_vref[32];
- ///*
- unsigned char rever3;//read_dqs read_dq,write_dqs, write_dq
- unsigned char dfi_mrl;
- unsigned char dfi_hwtmrl;
- unsigned char ARdPtrInitVal;
- unsigned char retraining[16];
//override read bit delay
-} __attribute__ ((packed)) ddr_set_t;
+}__attribute__ ((packed)) ddr_set_t;
typedef struct pll_set{
- unsigned short cpu_clk;
- unsigned short pxp;
- unsigned int spi_ctrl;
- unsigned short vddee;
- unsigned short vcck;
- unsigned char szPad[4];
+ unsigned short cpu_clk;
+ unsigned short pxp;
+ unsigned int spi_ctrl;
+ unsigned short vddee;
+ unsigned short vcck;
+ unsigned char szPad[4];
- unsigned long lCustomerID;
- unsigned short debug_mode;
- unsigned short rsv1;
- unsigned short rsv2;
- unsigned short rsv3;
+ unsigned long lCustomerID;
+ unsigned char debug_mode;
+ unsigned char log_chl;
+ unsigned char log_ctrl;
+ unsigned char ddr_timming_save_mode;
+ unsigned int nCFGTAddr;
/* align 8Byte */
- unsigned int sys_pll_cntl[8];
- unsigned int ddr_pll_cntl[8];
- unsigned int fix_pll_cntl[8];
+ unsigned int sys_pll_cntl[8];
+ unsigned int ddr_pll_cntl[8];
+ unsigned int fix_pll_cntl[8];
}__attribute__ ((packed)) pll_set_t;
-typedef struct dwc_apb {
- unsigned int addr;
- unsigned short val;
-} dwc_apb_t;
+typedef struct dmem_cfg {
+ PMU_SMB_DDR3U_1D_t ddr3u;
+ PMU_SMB_DDR4U_1D_t ddr4u;
+ PMU_SMB_DDR4U_2D_t ddr4u_2d;
+ PMU_SMB_LPDDR3_1D_t lpddr3u;
+ PMU_SMB_LPDDR4_1D_t lpddr4u;
+ PMU_SMB_LPDDR4_2D_t lpddr4u_2d;
+} dmem_cfg_t;
#endif //__AML_TIMING_H_
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-g12a/tsensor.h b/arch/arm/include/asm/arch-g12a/tsensor.h
index 54dbb7f..f35f559 100644
--- a/arch/arm/include/asm/arch-g12a/tsensor.h
+++ b/arch/arm/include/asm/arch-g12a/tsensor.h
@@ -1,29 +1,15 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-g12a/tsensor.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __TSENSOR_H__
#define __TSENSOR_H__
#define CONFIG_HIGH_TEMP_COOL 90
-#define T_AVG_NUM 16 /*read temp cnt*/
+#define T_AVG_NUM 16 /*trim temp cnt*/
+#define T_READ_NUM 2 /*read temp cnt*/
#define T_VER_MASK 0x80
#define T_VALUE_MIN 0x1500
#define T_VALUE_MAX 0x3500
diff --git a/arch/arm/include/asm/arch-g12a/types.h b/arch/arm/include/asm/arch-g12a/types.h
index cab85ed..2d362b1 100644
--- a/arch/arm/include/asm/arch-g12a/types.h
+++ b/arch/arm/include/asm/arch-g12a/types.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __TYPES_H
#define __TYPES_H
diff --git a/arch/arm/include/asm/arch-g12a/uart.h b/arch/arm/include/asm/arch-g12a/uart.h
index 8f71c5a..22edaa7 100644
--- a/arch/arm/include/asm/arch-g12a/uart.h
+++ b/arch/arm/include/asm/arch-g12a/uart.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/uart.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __MESON_FIRM_UART_H_
#define __MESON_FIRM_UART_H_
diff --git a/arch/arm/include/asm/arch-g12a/usb.h b/arch/arm/include/asm/arch-g12a/usb.h
index 445f15a..f2669d5 100644
--- a/arch/arm/include/asm/arch-g12a/usb.h
+++ b/arch/arm/include/asm/arch-g12a/usb.h
@@ -1,22 +1,7 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/usb-new.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __ARCH_ARM_MESON_USB_H_U_BOOT__
#define __ARCH_ARM_MESON_USB_H_U_BOOT__
@@ -25,6 +10,8 @@
#include <asm/types.h>
#include <asm/arch/io.h>
#include <asm/arch/secure_apb.h>
+#include <generic-phy.h>
+#include <asm-generic/gpio.h>
#define USB_PHY_PORT_MAX 1
/* Phy register MACRO definitions */
@@ -89,6 +76,22 @@
/* XHCI PHY register structure */
#define PHY_REGISTER_SIZE 0x20
+
+struct phy_aml_usb2_priv {
+ unsigned int base_addr;
+ unsigned int reset_addr;
+ unsigned int dwc2_a_addr;
+ unsigned int u2_port_num;
+ unsigned int usbphy_reset_bit[8];
+ unsigned int usb_phy2_pll_base_addr[4];
+};
+
+struct phy_aml_usb3_priv {
+ unsigned int base_addr;
+ unsigned int usb3_port_num;
+ struct gpio_desc desc;
+};
+
/* Register definitions */
typedef struct u2p_aml_regs {
volatile uint32_t u2p_r0;
@@ -231,5 +234,13 @@
#define USB_ID_MODE_HARDWARE (1)
#define USB_ID_MODE_SW_HOST (2)
#define USB_ID_MODE_SW_DEVICE (3)
+int usb2_phy_tuning(uint32_t phy2_pll_base, int port);
+void set_usb_pll(uint32_t phy2_pll_base);
+int usb_save_phy_dev (unsigned int number, struct phy *phy);
+int usb2_phy_init (struct phy *phy);
+unsigned int usb_get_dwc_a_base_addr(void);
+unsigned int usb_get_device_mode_phy_base(void);
+void usb_phy_tuning_reset(void);
+void usb_device_mode_init(void);
#endif
diff --git a/arch/arm/include/asm/arch-g12a/watchdog.h b/arch/arm/include/asm/arch-g12a/watchdog.h
deleted file mode 100644
index bf61981..0000000
--- a/arch/arm/include/asm/arch-g12a/watchdog.h
+++ /dev/null
@@ -1,37 +0,0 @@
-
-/*
- * arch/arm/include/asm/arch-txl/watchdog.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#ifndef _BOOT_ROM_WATCHDOG_H
-#define _BOOT_ROM_WATCHDOG_H
-
-#include <asm/arch/secure_apb.h>
-
-//#include "common.h"
-
-void watchdog_init(uint32_t msec);
-void watchdog_reset(void);
-void reset_system(void);
-void watchdog_disable(void);
-
-/* uboot reset interface */
-void reset_cpu(unsigned long flag);
-
-#endif /* _BOOT_ROM_WATCHDOG_H */
diff --git a/arch/arm/include/asm/arch-g12b/acs.h b/arch/arm/include/asm/arch-g12b/acs.h
index c65c647..c98cbee 100644
--- a/arch/arm/include/asm/arch-g12b/acs.h
+++ b/arch/arm/include/asm/arch-g12b/acs.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/acs.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __ACS_H
#define __ACS_H
@@ -59,6 +43,9 @@
unsigned char rsv_set_version;
unsigned short rsv_set_length;
unsigned long rsv_set_addr;
+ char board_id[12];
+ unsigned short ddr_struct_size[12];
+ unsigned long ddr_struct_org_size;
}__attribute__ ((packed)) acs_set_t;
#endif
diff --git a/arch/arm/include/asm/arch-g12b/bl31_apis.h b/arch/arm/include/asm/arch-g12b/bl31_apis.h
index 0577964..b23d4c1 100644
--- a/arch/arm/include/asm/arch-g12b/bl31_apis.h
+++ b/arch/arm/include/asm/arch-g12b/bl31_apis.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/bl31_apis.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
/*
* Trustzone API
@@ -93,6 +77,17 @@
/*viu probe en*/
#define VIU_PREOBE_EN 0x82000080
+
+/* KEYMASTER */
+#define SET_BOOT_PARAMS 0x82000072
+#define SHA256_DIGEST_SIZE 32
+typedef struct {
+ uint32_t device_locked;
+ uint32_t verified_boot_state;
+ uint8_t verified_boot_key[SHA256_DIGEST_SIZE];
+ uint8_t verified_boot_hash[SHA256_DIGEST_SIZE];
+} keymaster_boot_params;
+
/* Secure HAL APIs */
#define TRUSTZONE_HAL_API_SRAM 0x400
@@ -115,6 +110,8 @@
#define JTAG_A53_EE 3
#define CLUSTER_BIT 2
+/* AVB2 */
+#define GET_AVBKEY_FROM_FIP 0x820000b0
/////////////////////////////////////////////////////////////////////////////////
#define AML_DATA_PROCESS (0x820000FF)
@@ -123,8 +120,6 @@
#define AML_D_P_W_EFUSE_CUSTOMER_ID (0x12)
#define AML_D_P_W_EFUSE_AMLOGIC (0x20)
#define AML_D_P_IMG_DECRYPT (0x40)
- #define AML_D_P_IMG_DECRYPT_V3 (0x41)
- #define AML_D_P_EXT_IMG_DECRYPT_V3 (0x51)
#define AML_D_P_UPGRADE_CHECK (0x80)
#define AML_D_Q_IMG_SIG_HDR_SIZE (0x100)
@@ -149,4 +144,6 @@
void bl31_get_chipid(unsigned int *, unsigned int *,
unsigned int *, unsigned int *);
void set_viu_probe_enable(void);
+int32_t set_boot_params(const keymaster_boot_params*);
+int32_t get_avbkey_from_fip(uint8_t *buf, uint32_t buflen);
#endif
diff --git a/arch/arm/include/asm/arch-g12b/board_id.h b/arch/arm/include/asm/arch-g12b/board_id.h
index 6137e12..6488771 100644
--- a/arch/arm/include/asm/arch-g12b/board_id.h
+++ b/arch/arm/include/asm/arch-g12b/board_id.h
@@ -1,19 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
unsigned int get_board_id(void);
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-g12b/clk_measure_tab.h b/arch/arm/include/asm/arch-g12b/clk_measure_tab.h
new file mode 100644
index 0000000..ee4d197
--- /dev/null
+++ b/arch/arm/include/asm/arch-g12b/clk_measure_tab.h
@@ -0,0 +1,140 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _ARCH_MESON_G12B_MEASURE_H_
+#define _ARCH_MESON_G12B_MEASURE_H_
+
+const char* clk_msr_table[] = {
+ [127] = "1'b0 ",
+ [126] = "1'b0 ",
+ [125] = "1'b0 ",
+ [124] = "1'b0 ",
+ [123] = "1'b0 ",
+ [122] = "mod_audio_pdm_dclk_o ",
+ [121] = "audio_spdifin_mst_clk ",
+ [120] = "audio_spdifout_mst_clk ",
+ [119] = "audio_spdifout_b_mst_clk ",
+ [118] = "audio_pdm_sysclk ",
+ [117] = "audio_resample_sclk ",
+ [116] = "audio_tdmin_a_sclk ",
+ [115] = "audio_tdmin_b_sclk ",
+ [114] = "audio_tdmin_c_sclk ",
+ [113] = "audio_tdmin_lb_sclk ",
+ [112] = "audio_tdmout_a_sclk ",
+ [111] = "audio_tdmout_b_sclk ",
+ [110] = "audio_tdmout_c_sclk ",
+ [109] = "c_alocker_out_clk ",
+ [108] = "c_alocker_in_clk ",
+ [107] = "au_dac_clk_g128x ",
+ [106] = "ephy_test_clk ",
+ [105] = "am_ring_osc_clk_out_ee[9] ",
+ [104] = "am_ring_osc_clk_out_ee[8] ",
+ [103] = "am_ring_osc_clk_out_ee[7] ",
+ [102] = "am_ring_osc_clk_out_ee[6] ",
+ [101] = "am_ring_osc_clk_out_ee[5] ",
+ [100] = "am_ring_osc_clk_out_ee[4] ",
+ [99] = "am_ring_osc_clk_out_ee[3] ",
+ [98] = "cts_ts_clk ",
+ [97] = "cts_vpu_clkb_tmp ",
+ [96] = "cts_vpu_clkb ",
+ [95] = "eth_phy_plltxclk ",
+ [94] = "eth_phy_rxclk ",
+ [93] = "1'b0 ",
+ [92] = "1'b0 ",
+ [91] = "1'b0 ",
+ [90] = "cts_hdmitx_sys_clk ",
+ [89] = "HDMI_CLK_TODIG ",
+ [88] = "1'b0 ",
+ [87] = "1'b0 ",
+ [86] = "1'b0 ",
+ [85] = "1'b0 ",
+ [84] = "co_tx_clk ",
+ [83] = "co_rx_clk ",
+ [82] = "Cts_ge2d_clk ",
+ [81] = "Cts_vapbclk ",
+ [80] = "Rng_ring_osc_clk[3] ",
+ [79] = "Rng_ring_osc_clk[2] ",
+ [78] = "Rng_ring_osc_clk[1] ",
+ [77] = "Rng_ring_osc_clk[0] ",
+ [76] = "1'b0 ",
+ [75] = "cts_hevcf_clk ",
+ [74] = "1'b0 ",
+ [73] = "cts_pwm_C_clk ",
+ [72] = "cts_pwm_D_clk ",
+ [71] = "cts_pwm_E_clk ",
+ [70] = "cts_pwm_F_clk ",
+ [69] = "Cts_hdcp22_skpclk ",
+ [68] = "Cts_hdcp22_esmclk ",
+ [67] = "cts_dsi_phy_clk ",
+ [66] = "cts_vid_lock_clk ",
+ [65] = "cts_spicc_0_clk ",
+ [64] = "Cts_spicc_1_clk ",
+ [63] = "cts_dsi_meas_clk ",
+ [62] = "cts_hevcb_clk ",
+ [61] = "gpio_clk_msr ",
+ [60] = "1'b0 ",
+ [59] = "cts_hcodec_clk ",
+ [58] = "cts_wave4201_bclk ",
+ [57] = "cts_wave4201_cclk ",
+ [56] = "cts_wave4201_aclk ",
+ [55] = "vid_pll_div_clk_out ",
+ [54] = "cts_vpu_clkc ",
+ [53] = "sd_emmc_clk_A ",
+ [52] = "sd_emmc_clk_B ",
+ [51] = "sd_emmc_clk_C ",
+ [50] = "mp3_clk_out ",
+ [49] = "mp2_clk_out ",
+ [48] = "mp1_clk_out ",
+ [47] = "ddr_dpll_pt_clk ",
+ [46] = "cts_vpu_clk ",
+ [45] = "cts_pwm_A_clk ",
+ [44] = "cts_pwm_B_clk ",
+ [43] = "fclk_div5 ",
+ [42] = "mp0_clk_out ",
+ [41] = "mac_eth_rx_clk_rmii ",
+ [40] = "1'b0 ",
+ [39] = "cts_bt656_clk0 ",
+ [38] = "Cts_vdin_meas_clk ",
+ [37] = "cts_cdac_clk_c ",
+ [36] = "cts_hdmi_tx_pixel_clk ",
+ [35] = "cts_mali_clk ",
+ [34] = "eth_mppll_50m_ckout ",
+ [33] = "sys_cpu_ring_osc_clk[1] ",
+ [32] = "cts_vdec_clk ",
+ [31] = "MPLL_CLK_TEST_OUT ",
+ [30] = "pcie_clk_inn ",
+ [29] = "pcie_clk_inp ",
+ [28] = "Cts_sar_adc_clk ",
+ [27] = "co_clkin_to_mac ",
+ [26] = "sc_clk_int ",
+ [25] = "cts_eth_clk_rmii ",
+ [24] = "cts_eth_clk125Mhz ",
+ [23] = "mpll_clk_50m ",
+ [22] = "mac_eth_phy_ref_clk ",
+ [21] = "lcd_an_clk_ph3 ",
+ [20] = "rtc_osc_clk_out ",
+ [19] = "lcd_an_clk_ph2 ",
+ [18] = "sys_cpu_clk_div16 ",
+ [17] = "sys_pll_div16 ",
+ [16] = "cts_FEC_CLK_2 ",
+ [15] = "cts_FEC_CLK_1 ",
+ [14] = "cts_FEC_CLK_0 ",
+ [13] = "mod_tcon_clko ",
+ [12] = "hifi_pll_clk ",
+ [11] = "mac_eth_tx_clk ",
+ [10] = "cts_vdac_clk ",
+ [9] = "cts_encl_clk ",
+ [8] = "cts_encp_clk ",
+ [7] = "clk81 ",
+ [6] = "cts_enci_clk ",
+ [5] = "1'b0 ",
+ [4] = "gp0_pll_clk ",
+ [3] = "A53_ring_osc_clk ",
+ [2] = "am_ring_osc_clk_out_ee[2] ",
+ [1] = "am_ring_osc_clk_out_ee[1] ",
+ [0] = "am_ring_osc_clk_out_ee[0] ",
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-g12b/clock.h b/arch/arm/include/asm/arch-g12b/clock.h
index 90e7403..081cc1e 100644
--- a/arch/arm/include/asm/arch-g12b/clock.h
+++ b/arch/arm/include/asm/arch-g12b/clock.h
@@ -1,7 +1,8 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Copyright 2018 - AmLogic, Inc.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#ifndef _ARCH_MESON_G12A_CLOCK_H_
#define _ARCH_MESON_G12A_CLOCK_H_
@@ -13,31 +14,31 @@
* to get the right value
*/
-#define HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet1 */
-#define HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet1 */
-#define HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet1 */
-#define HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet1 */
+#define G12_HHI_GCLK_MPEG0 0x140 /* 0x50 offset in data sheet1 */
+#define G12_HHI_GCLK_MPEG1 0x144 /* 0x51 offset in data sheet1 */
+#define G12_HHI_GCLK_MPEG2 0x148 /* 0x52 offset in data sheet1 */
+#define G12_HHI_GCLK_OTHER 0x150 /* 0x54 offset in data sheet1 */
-#define HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet1 */
-#define HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet1 */
+#define G12_HHI_NAND_CLK_CNTL 0x25c /* 0x97 offset in data sheet1 */
+#define G12_HHI_SD_EMMC_CLK_CNTL 0x264 /* 0x99 offset in data sheet1 */
-#define HHI_FIX_PLL_CNTL0 0x2A0 /* 0xa8 offset in data sheet1 */
-#define HHI_FIX_PLL_CNTL1 0x2A4 /* 0xa9 offset in data sheet1 */
+#define G12_HHI_FIX_PLL_CNTL0 0x2A0 /* 0xa8 offset in data sheet1 */
+#define G12_HHI_FIX_PLL_CNTL1 0x2A4 /* 0xa9 offset in data sheet1 */
-#define HHI_SYS_PLL_CNTL0 0x2f4 /* 0xbd offset in data sheet1 */
-#define HHI_SYS_PLL_CNTL1 0x2f8 /* 0xbe offset in data sheet1 */
-#define HHI_SYS_PLL_CNTL2 0x2fc /* 0xbf offset in data sheet1 */
-#define HHI_SYS_PLL_CNTL3 0x300 /* 0xc0 offset in data sheet1 */
-#define HHI_SYS_PLL_CNTL4 0x304 /* 0xc1 offset in data sheet1 */
-#define HHI_SYS_PLL_CNTL5 0x308 /* 0xc2 offset in data sheet1 */
-#define HHI_SYS_PLL_CNTL6 0x30c /* 0xc3 offset in data sheet1 */
-#define HHI_SPICC_CLK_CNTL 0x3dc /* 0xf7 offset in data sheet1 */
+#define G12_HHI_SYS_PLL_CNTL0 0x2f4 /* 0xbd offset in data sheet1 */
+#define G12_HHI_SYS_PLL_CNTL1 0x2f8 /* 0xbe offset in data sheet1 */
+#define G12_HHI_SYS_PLL_CNTL2 0x2fc /* 0xbf offset in data sheet1 */
+#define G12_HHI_SYS_PLL_CNTL3 0x300 /* 0xc0 offset in data sheet1 */
+#define G12_HHI_SYS_PLL_CNTL4 0x304 /* 0xc1 offset in data sheet1 */
+#define G12_HHI_SYS_PLL_CNTL5 0x308 /* 0xc2 offset in data sheet1 */
+#define G12_HHI_SYS_PLL_CNTL6 0x30c /* 0xc3 offset in data sheet1 */
+#define G12_HHI_SPICC_CLK_CNTL 0x3dc /* 0xf7 offset in data sheet1 */
#define CLKID_UNREALIZED 0xfff
/* AO registers */
-#define AO_SAR_CLK 0x90
-#define AO_CLK_GATE0 0x4c
+#define G12_AO_SAR_CLK 0x90
+#define G12_AO_CLK_GATE0 0x4c
ulong meson_measure_clk_rate(unsigned int clk);
diff --git a/arch/arm/include/asm/arch-g12b/cpu.h b/arch/arm/include/asm/arch-g12b/cpu.h
index a5f181e..ba73ba3 100644
--- a/arch/arm/include/asm/arch-g12b/cpu.h
+++ b/arch/arm/include/asm/arch-g12b/cpu.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-g12a/cpu.h
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _CPU_H
#define _CPU_H
@@ -37,7 +21,7 @@
#endif
/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN (64*1024*1024)
+#define CONFIG_SYS_MALLOC_LEN (96*1024*1024)
/* for uboot envrionment use */
/* #define CONFIG_DDR_SIZE 1024 */
@@ -87,4 +71,11 @@
#define NR_CPUS 4
+#define CPU_ID_REG P_AO_SEC_SD_CFG8
+#define PACKAGE_ID_MASK 0xFF
+
+#define MIPI_DSI_REGISTER 1
+#define MIPI_DSI_BASE 0xffd07000L
+#define MIPI_DSI_PHY_BASE 0xff644000L
+
#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-g12b/cpu_config.h b/arch/arm/include/asm/arch-g12b/cpu_config.h
index 7e7c758..45e7e80 100644
--- a/arch/arm/include/asm/arch-g12b/cpu_config.h
+++ b/arch/arm/include/asm/arch-g12b/cpu_config.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/cpu_config.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _BOOT_ROM_CONFIG_H_
#define _BOOT_ROM_CONFIG_H_
diff --git a/arch/arm/include/asm/arch-g12b/cpu_id.h b/arch/arm/include/asm/arch-g12b/cpu_id.h
deleted file mode 100644
index 6645edd..0000000
--- a/arch/arm/include/asm/arch-g12b/cpu_id.h
+++ /dev/null
@@ -1,85 +0,0 @@
-/*
- * arch/arm/include/asm/cpu_id.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#define MESON_CPU_MAJOR_ID_M6 0x16
-#define MESON_CPU_MAJOR_ID_M6TV 0x17
-#define MESON_CPU_MAJOR_ID_M6TVL 0x18
-#define MESON_CPU_MAJOR_ID_M8 0x19
-#define MESON_CPU_MAJOR_ID_MTVD 0x1A
-#define MESON_CPU_MAJOR_ID_M8B 0x1B
-#define MESON_CPU_MAJOR_ID_MG9TV 0x1C
-#define MESON_CPU_MAJOR_ID_M8M2 0x1D
-#define MESON_CPU_MAJOR_ID_GXBB 0x1F
-#define MESON_CPU_MAJOR_ID_GXTVBB 0x20
-#define MESON_CPU_MAJOR_ID_GXL 0x21
-#define MESON_CPU_MAJOR_ID_GXM 0x22
-#define MESON_CPU_MAJOR_ID_TXL 0x23
-#define MESON_CPU_MAJOR_ID_TXLX 0x24
-#define MESON_CPU_MAJOR_ID_AXG 0x25
-#define MESON_CPU_MAJOR_ID_GXLX 0x26
-#define MESON_CPU_MAJOR_ID_TXHD 0x27
-#define MESON_CPU_MAJOR_ID_G12A 0x28
-#define MESON_CPU_MAJOR_ID_G12B 0x29
-#define MESON_CPU_MAJOR_ID_SM1 0x2B
-#define MESON_CPU_MAJOR_ID_TL1 0x2E
-#define MESON_CPU_MAJOR_ID_TM2 0x2F
-
-#define MESON_CPU_PACKAGE_ID_905D 0X00
-#define MESON_CPU_PACKAGE_ID_905M 0x20
-#define MESON_CPU_PACKAGE_ID_905X 0X80
-#define MESON_CPU_PACKAGE_ID_905L 0XC0
-#define MESON_CPU_PACKAGE_ID_905M2 0XE0
-
-#define MESON_CPU_PACKAGE_ID_T962X 0x10
-#define MESON_CPU_PACKAGE_ID_T962E 0x20
-
-#define MESON_CPU_PACKAGE_ID_A113X 0x37
-#define MESON_CPU_PACKAGE_ID_A113D 0xD0
-
-#define MESON_CPU_CHIP_REVISION_A 0xA
-#define MESON_CPU_CHIP_REVISION_B 0xB
-#define MESON_CPU_CHIP_REVISION_C 0xC
-#define MESON_CPU_CHIP_REVISION_D 0xD
-
-typedef struct cpu_id {
- unsigned int family_id:8; //S905/T968 etc.
- unsigned int package_id:8; //T968/T966 etc.
- unsigned int chip_rev:8; //RevA/RevB etc.
- unsigned int reserve:4;
- unsigned int layout_ver:4;
-} cpu_id_t;
-
-typedef struct chip_id {
- unsigned int version;
- unsigned char chipid[16];
-} chip_id_t;
-
-cpu_id_t get_cpu_id(void);
-
-extern chip_id_t aml_chip_id;
-int get_chip_id(unsigned char *buff, unsigned int size);
-
-/**
- * TODO: Remove this API after move static system information to RO
- * register or SRAM
- *
- * Should *NOT* call this API directly, always use get_chip_id()
- */
-int __get_chip_id(unsigned char *buff, unsigned int size);
diff --git a/arch/arm/include/asm/arch-g12b/cpu_reset.h b/arch/arm/include/asm/arch-g12b/cpu_reset.h
new file mode 100644
index 0000000..46f9abf
--- /dev/null
+++ b/arch/arm/include/asm/arch-g12b/cpu_reset.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _BOOT_ROM_WATCHDOG_H
+#define _BOOT_ROM_WATCHDOG_H
+#include <asm/arch/secure_apb.h>
+
+void reset_system(void);
+
+/* uboot reset interface */
+void reset_cpu(unsigned long flag);
+
+#endif /* _BOOT_ROM_WATCHDOG_H */
diff --git a/arch/arm/include/asm/arch-g12b/cpu_sdio.h b/arch/arm/include/asm/arch-g12b/cpu_sdio.h
index 552b315..ba35ed6 100644
--- a/arch/arm/include/asm/arch-g12b/cpu_sdio.h
+++ b/arch/arm/include/asm/arch-g12b/cpu_sdio.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/cpu_sdio.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __CPU_SDIO_H__
#define __CPU_SDIO_H__
@@ -30,6 +14,16 @@
#define SDIO_PORT_B 1
#define SDIO_PORT_C 2
+
+#if 0
+#define SD_EMMC_RXD_ERROR 1
+#define SD_EMMC_TXD_ERROR 1<<1
+#define SD_EMMC_DESC_ERROR 1<<2
+#define SD_EMMC_RESP_CRC_ERROR 1<<3
+#define SD_EMMC_RESP_TIMEOUT_ERROR 1<<4
+#define SD_EMMC_DESC_TIMEOUT_ERROR 1<<5
+#endif
+
struct sd_emmc_global_regs {
volatile uint32_t gclock; // 0x00
volatile uint32_t gdelay; // 0x04
diff --git a/arch/arm/include/asm/arch-g12b/ddr.h b/arch/arm/include/asm/arch-g12b/ddr.h
index f5ea6c7..ad27855 100644
--- a/arch/arm/include/asm/arch-g12b/ddr.h
+++ b/arch/arm/include/asm/arch-g12b/ddr.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/ddr.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <config.h>
#include <io.h>
diff --git a/arch/arm/include/asm/arch-g12b/ddr_define.h b/arch/arm/include/asm/arch-g12b/ddr_define.h
old mode 100755
new mode 100644
index ba472b3..b44cf14
--- a/arch/arm/include/asm/arch-g12b/ddr_define.h
+++ b/arch/arm/include/asm/arch-g12b/ddr_define.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/ddr_define.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#define CONFIG_BOARD_ID_MASK 0xFF
#define CONFIG_DDR_TYPE_DDR3 0
@@ -83,7 +67,6 @@
(chl_set == CONFIG_DDR0_16BIT))
#define DDR_USE_2_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK01))
-
#define DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT 1<<5
#define DMC_TEST_SLT_ENABLE_DDR_AUTO_WINDOW_TEST 1<<4
/* DMC_DDR_CTRL defines */
@@ -154,68 +137,73 @@
*/
/* d2pll support */
-#ifndef CONFIG_CMD_D2PLL
-#define CONFIG_CMD_D2PLL 0
+#ifndef CONFIG_CMD_DDR_D2PLL
+#define CONFIG_CMD_DDR_D2PLL 0
#endif
-#define DDR_FUNC_D2PLL (CONFIG_CMD_D2PLL<<0)
+#define DDR_FUNC_D2PLL (CONFIG_CMD_DDR_D2PLL<<0)
/* ddr low power function support */
-#ifndef DDR_LOW_POWER
-#define DDR_LOW_POWER 0
+#ifndef CONFIG_DDR_LOW_POWER
+#define CONFIG_DDR_LOW_POWER 0
#endif
-#define DDR_FUNC_LP (DDR_LOW_POWER<<1)
+#define DDR_FUNC_LP (CONFIG_DDR_LOW_POWER<<1)
/* ddr zq power down support */
-#ifndef DDR_ZQ_PD
-#define DDR_ZQ_PD 0
+#ifndef CONFIG_DDR_ZQ_PD
+#define CONFIG_DDR_ZQ_PD 0
#endif
-#define DDR_FUNC_ZQ_PD (DDR_ZQ_PD<<2)
+#define DDR_FUNC_ZQ_PD (CONFIG_DDR_ZQ_PD<<2)
/* ddr vref function */
-#ifndef DDR_USE_EXT_VREF
-#define DDR_USE_EXT_VREF 0
+#ifndef CONFIG_DDR_USE_EXT_VREF
+#define CONFIG_DDR_USE_EXT_VREF 0
#endif
-#define DDR_FUNC_EXT_VREF (DDR_USE_EXT_VREF<<3)
+#define DDR_FUNC_EXT_VREF (CONFIG_DDR_USE_EXT_VREF<<3)
/* ddr4 timing test function */
-#ifndef DDR4_TIMING_TEST
-#define DDR4_TIMING_TEST 0
+#ifndef CONFIG_DDR4_TIMING_TEST
+#define CONFIG_DDR4_TIMING_TEST 0
#endif
-#define DDR_FUNC_DDR4_TIMING_TEST (DDR4_TIMING_TEST<<4)
+#define DDR_FUNC_DDR4_TIMING_TEST (CONFIG_DDR4_TIMING_TEST<<4)
/* ddr pll bypass */
-#ifndef DDR_PLL_BYPASS
-#define DDR_PLL_BYPASS 0
+#ifndef CONFIG_DDR_PLL_BYPASS
+#define CONFIG_DDR_PLL_BYPASS 0
#endif
-#define DDR_FUNC_DDR_PLL_BYPASS (DDR_PLL_BYPASS<<5)
+#define DDR_FUNC_DDR_PLL_BYPASS (CONFIG_DDR_PLL_BYPASS<<5)
/* ddr rdbi function */
-#ifndef DDR_FUNC_RDBI
-#define DDR_FUNC_RDBI 0
+#ifndef CONFIG_DDR_FUNC_RDBI
+#define CONFIG_DDR_FUNC_RDBI 0
#endif
-#define DDR_FUNC_DDR_RDBI (DDR_FUNC_RDBI<<6)
+#define DDR_FUNC_RDBI (CONFIG_DDR_FUNC_RDBI<<6)
/* lpddr3 ca trainingi function */
-#ifndef DDR_FUNC_LPDDR3_CA
-#define DDR_FUNC_LPDDR3_CA 0
+#ifndef CONFIG_DDR_FUNC_LPDDR3_CA
+#define CONFIG_DDR_FUNC_LPDDR3_CA 0
#endif
-#define DDR_FUNC_LPDDR3_CA_TRAIN (DDR_FUNC_LPDDR3_CA<<7)
+#define DDR_FUNC_LPDDR3_CA (CONFIG_DDR_FUNC_LPDDR3_CA<<7)
/* print ddr training window */
-#ifndef DDR_FUNC_PRINT_WINDOW
-#define DDR_FUNC_PRINT_WINDOW 0
+#ifndef CONFIG_DDR_FUNC_PRINT_WINDOW
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 0
#endif
-#define DDR_FUNC_PRINT_WINDOW_EN (DDR_FUNC_PRINT_WINDOW<<8)
+#define DDR_FUNC_PRINT_WINDOW (CONFIG_DDR_FUNC_PRINT_WINDOW<<8)
/* print ddr training window */
-#ifndef DDR_FULL_TEST
-#define DDR_FULL_TEST 0
+//#ifndef CONFIG_DDR_FULL_TEST
+//#define CONFIG_DDR_FULL_TEST 0
+//#endif
+//#define DDR_FULL_TEST (CONFIG_DDR_FULL_TEST<<10)
+
+/* non-sec region scramble function */
+#ifndef CONFIG_DDR_NONSEC_SCRAMBLE
+#define CONFIG_DDR_NONSEC_SCRAMBLE 0
#endif
-#define DDR_FULL_TEST_EN (DDR_FULL_TEST<<10)
+#define DDR_NONSEC_SCRAMBLE (CONFIG_DDR_NONSEC_SCRAMBLE<<11)
-
-#if(DDR_FUNC_LPDDR3_CA==1)
+#if(CONFIG_DDR_FUNC_LPDDR3_CA==1)
#if (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE0)
#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20)
#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21)
@@ -254,17 +242,20 @@
#else
#define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP (0<<25)
#endif
-
+#define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1<<30)
+#define DDR_FUNC_CONFIG_DFE_FUNCTION (1<<29)
+#define DDR_FUNC_CONFIG_DDR_DVFS_FUNCTION (1<<28)
#define DDR_FUNC (DDR_FUNC_D2PLL | \
DDR_FUNC_LP | \
DDR_FUNC_ZQ_PD | \
DDR_FUNC_EXT_VREF | \
DDR_FUNC_DDR4_TIMING_TEST | \
DDR_FUNC_DDR_PLL_BYPASS | \
- DDR_FUNC_DDR_RDBI | \
- DDR_FUNC_LPDDR3_CA_TRAIN | \
- DDR_FUNC_PRINT_WINDOW_EN | \
- DDR_FULL_TEST_EN | \
+ DDR_FUNC_RDBI | \
+ DDR_FUNC_LPDDR3_CA | \
+ DDR_FUNC_PRINT_WINDOW | \
+ DDR_FULL_TEST | \
+ DDR_NONSEC_SCRAMBLE | \
DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0| \
DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1| \
DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0| \
diff --git a/arch/arm/include/asm/arch-g12b/efuse.h b/arch/arm/include/asm/arch-g12b/efuse.h
index b5ea027..4a68e88 100644
--- a/arch/arm/include/asm/arch-g12b/efuse.h
+++ b/arch/arm/include/asm/arch-g12b/efuse.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/efuse.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __EFUSE_H
#define __EFUSE_H
diff --git a/arch/arm/include/asm/arch-g12b/eth_setup.h b/arch/arm/include/asm/arch-g12b/eth_setup.h
index 2b0d877..6e643f6 100644
--- a/arch/arm/include/asm/arch-g12b/eth_setup.h
+++ b/arch/arm/include/asm/arch-g12b/eth_setup.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/eth_setup.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <asm/arch/io.h>
diff --git a/arch/arm/include/asm/arch-g12b/gpio.h b/arch/arm/include/asm/arch-g12b/gpio.h
index d0142f1..2467368 100644
--- a/arch/arm/include/asm/arch-g12b/gpio.h
+++ b/arch/arm/include/asm/arch-g12b/gpio.h
@@ -1,6 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * (C) Copyright 2017 - Beniamino Galvani <b.galvani@gmail.com>
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __ASM_ARCH_MESON_GPIO_H
diff --git a/arch/arm/include/asm/arch-g12b/io.h b/arch/arm/include/asm/arch-g12b/io.h
index 8640303..4035ee8 100644
--- a/arch/arm/include/asm/arch-g12b/io.h
+++ b/arch/arm/include/asm/arch-g12b/io.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/io.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __MACH_MESSON_REGS_IO_H
#define __MACH_MESSON_REGS_IO_H
@@ -25,12 +9,14 @@
#ifndef __ASSEMBLY__
#include <asm/io.h>
-#define IO_CBUS_BASE (0xFFD00000L)
-#define IO_AXI_BUS_BASE (0xFFB00000L) /* gpv */
-#define IO_AHB_BUS_BASE (0xFF500000L) /* usb0 */
-#define IO_APB_BUS_BASE (0xFFFC0000L) /* AHB SRAM, sec/sys ahb? txlx_mem_map.xlsx */
-#define IO_APB_HDMI_BUS_BASE (0xFFE00000L) /* */
-#define IO_VPU_BUS_BASE (0xFF900000L) /* VPU */
+#include <asm/arch/register.h>
+
+//#define IO_CBUS_BASE (0xFFD00000L)
+//#define IO_AXI_BUS_BASE (0xFFB00000L) /* gpv */
+//#define IO_AHB_BUS_BASE (0xFF500000L) /* usb0 */
+//#define IO_APB_BUS_BASE (0xFFFC0000L) /* AHB SRAM, sec/sys ahb? txlx_mem_map.xlsx */
+//#define IO_APB_HDMI_BUS_BASE (0xFFE00000L) /* */
+//#define IO_VPU_BUS_BASE (0xFF900000L) /* VPU */
#define CBUS_REG_OFFSET(reg) ((reg) << 2)
#define CBUS_REG_ADDR(reg) (IO_CBUS_BASE + CBUS_REG_OFFSET(reg))
diff --git a/arch/arm/include/asm/arch-g12b/mailbox.h b/arch/arm/include/asm/arch-g12b/mailbox.h
index 5f06480..75b65b7 100644
--- a/arch/arm/include/asm/arch-g12b/mailbox.h
+++ b/arch/arm/include/asm/arch-g12b/mailbox.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/mailbox.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
/*
*
diff --git a/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_ddr3.h b/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_ddr3.h
index 496f3b7..c067367 100644
--- a/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_ddr3.h
+++ b/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_ddr3.h
@@ -1,6 +1,6 @@
-
-/** \file
- * \brief defines _PMU_SMB_DDR3U_1D data structure
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
/** \brief DDR3U_1D training firmware message block structure
diff --git a/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_ddr4.h b/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_ddr4.h
index fa3e4a6..6dfd4d0 100644
--- a/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_ddr4.h
+++ b/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_ddr4.h
@@ -1,6 +1,6 @@
-
-/** \file
- * \brief defines _PMU_SMB_DDR4U_1D data structure
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
/** \brief DDR4U_1D training firmware message block structure
diff --git a/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_ddr4_2d.h b/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_ddr4_2d.h
index 5131262..35b1e23 100644
--- a/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_ddr4_2d.h
+++ b/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_ddr4_2d.h
@@ -1,6 +1,6 @@
-
-/** \file
- * \brief defines _PMU_SMB_DDR4U_2D data structure
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
/** \brief DDR4U_2D training firmware message block structure
diff --git a/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_lpddr3.h b/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_lpddr3.h
index c30b3c4..6850d06 100644
--- a/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_lpddr3.h
+++ b/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_lpddr3.h
@@ -1,6 +1,6 @@
-
-/** \file
- * \brief defines _PMU_SMB_LPDDR3_1D data structure
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
/** \brief LPDDR3_1D training firmware message block structure
diff --git a/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_lpddr4.h b/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_lpddr4.h
index c574c3c..d194621 100644
--- a/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_lpddr4.h
+++ b/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_lpddr4.h
@@ -1,6 +1,6 @@
-
-/** \file
- * \brief defines _PMU_SMB_LPDDR4_1D data structure
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
/** \brief LPDDR4_1D training firmware message block structure
diff --git a/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_lpddr4_2d.h b/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_lpddr4_2d.h
index 5a4d62a..c6ab3d3 100644
--- a/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_lpddr4_2d.h
+++ b/arch/arm/include/asm/arch-g12b/mnPmuSramMsgBlock_lpddr4_2d.h
@@ -1,6 +1,6 @@
-
-/** \file
- * \brief defines _PMU_SMB_LPDDR4_2D data structure
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
/** \brief LPDDR4_2D training firmware message block structure
diff --git a/arch/arm/include/asm/arch-g12b/nand.h b/arch/arm/include/asm/arch-g12b/nand.h
index 8ab9f42..91484ac 100644
--- a/arch/arm/include/asm/arch-g12b/nand.h
+++ b/arch/arm/include/asm/arch-g12b/nand.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/nand.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __NAND_H__
#define __NAND_H__
diff --git a/arch/arm/include/asm/arch-g12b/oscring.h b/arch/arm/include/asm/arch-g12b/oscring.h
index af14619..cd29ef1 100644
--- a/arch/arm/include/asm/arch-g12b/oscring.h
+++ b/arch/arm/include/asm/arch-g12b/oscring.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __OSCRING_H__
#define __OSCRING_H__
diff --git a/arch/arm/include/asm/arch-g12b/pinctrl_init.h b/arch/arm/include/asm/arch-g12b/pinctrl_init.h
index 31d20b2..cfbc42a 100644
--- a/arch/arm/include/asm/arch-g12b/pinctrl_init.h
+++ b/arch/arm/include/asm/arch-g12b/pinctrl_init.h
@@ -1,8 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
- * Author: Xingyu Chen <xingyu.chen@amlogic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef _MESON_PINCTRL_INIT_H_
diff --git a/arch/arm/include/asm/arch-g12b/pll.h b/arch/arm/include/asm/arch-g12b/pll.h
index 1de82ed..1b2069e 100644
--- a/arch/arm/include/asm/arch-g12b/pll.h
+++ b/arch/arm/include/asm/arch-g12b/pll.h
@@ -1,3 +1,7 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __PLL_H
#define __PLL_H
diff --git a/arch/arm/include/asm/arch-g12b/reboot.h b/arch/arm/include/asm/arch-g12b/reboot.h
index 0cdc3cd..50ca64a 100644
--- a/arch/arm/include/asm/arch-g12b/reboot.h
+++ b/arch/arm/include/asm/arch-g12b/reboot.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/reboot.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __REBOOT_H
#define __REBOOT_H
@@ -35,7 +19,7 @@
8: Shutdown reboot shutdown_reboot
9: RPMBP reboot rpmbp
10: quiescent reboot quiescent reboot
-11: Crash dump crash_dump
+11 : rescueparty rollback in AB mode
12: Kernel panic kernel_panic
13: Watchdog reboot watchdog_reboot
14: quiescent recovery reboot quiescent recovery
@@ -52,7 +36,7 @@
#define AMLOGIC_SHUTDOWN_REBOOT 8
#define AMLOGIC_RPMBP_REBOOT 9
#define AMLOGIC_QUIESCENT_REBOOT 10
-#define AMLOGIC_CRASH_REBOOT 11
+#define AMLOGIC_RESCUEPARTY_REBOOT 11
#define AMLOGIC_KERNEL_PANIC 12
#define AMLOGIC_WATCHDOG_REBOOT 13
#define AMLOGIC_RECOVERY_QUIESCENT_REBOOT 14
diff --git a/arch/arm/include/asm/arch-g12b/register.h b/arch/arm/include/asm/arch-g12b/register.h
index aa342a5..8720271 100644
--- a/arch/arm/include/asm/arch-g12b/register.h
+++ b/arch/arm/include/asm/arch-g12b/register.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/register.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __REGISTER_H__
#define __REGISTER_H__
diff --git a/arch/arm/include/asm/arch-g12b/regs.h b/arch/arm/include/asm/arch-g12b/regs.h
index af9fa9b..634ef31 100644
--- a/arch/arm/include/asm/arch-g12b/regs.h
+++ b/arch/arm/include/asm/arch-g12b/regs.h
@@ -1,10 +1,8 @@
-// ----------------------------------------------------------------------
-// regs.h header
-//
-// bus base define, update manually
-//
-// ----------------------------------------------------------------------
-//
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef _BASE_REGISTER
#define _BASE_REGISTER
#define REG_BASE_AOBUS (0xFF800000L)
@@ -13318,8 +13316,8 @@
#define P_WATCHDOG_CNTL1 (volatile unsigned int *)((0x3c35 << 2) + 0xffd00000)
#define WATCHDOG_TCNT (0x3c36)
#define P_WATCHDOG_TCNT (volatile unsigned int *)((0x3c36 << 2) + 0xffd00000)
-#define WATCHDOG_RESET (0x3c37)
-#define P_WATCHDOG_RESET (volatile unsigned int *)((0x3c37 << 2) + 0xffd00000)
+#define WATCHDOG_RST (0x3c37)
+#define P_WATCHDOG_RST (volatile unsigned int *)((0x3c37 << 2) + 0xffd00000)
// -----------------------------------------------------------
#define AHB_ARBITER_REG (0x3c42)
#define P_AHB_ARBITER_REG (volatile unsigned int *)((0x3c42 << 2) + 0xffd00000)
@@ -32583,7 +32581,6 @@
//===========================================================================
// -----------------------------------------------
// CBUS_BASE: DSI_CBUS_BASE = 0x1c
-#define MIPI_DSI_REGISTER
// -----------------------------------------------
//------------------------------------------------------------------------------
// DWC IP registers: Synopsys IP, please refer to MIPI DSI HOST Databook
@@ -32780,3 +32777,185 @@
// synopsys translate_on
//
// Closing file: dsi_regs.h
+#define VD1_HDR2_CTRL 0x3800
+#define VD1_HDR2_CLK_GATE 0x3801
+#define VD1_HDR2_MATRIXI_COEF00_01 0x3802
+#define VD1_HDR2_MATRIXI_COEF02_10 0x3803
+#define VD1_HDR2_MATRIXI_COEF11_12 0x3804
+#define VD1_HDR2_MATRIXI_COEF20_21 0x3805
+#define VD1_HDR2_MATRIXI_COEF22 0x3806
+#define VD1_HDR2_MATRIXI_COEF30_31 0x3807
+#define VD1_HDR2_MATRIXI_COEF32_40 0x3808
+#define VD1_HDR2_MATRIXI_COEF41_42 0x3809
+#define VD1_HDR2_MATRIXI_OFFSET0_1 0x380a
+#define VD1_HDR2_MATRIXI_OFFSET2 0x380b
+#define VD1_HDR2_MATRIXI_PRE_OFFSET0_1 0x380c
+#define VD1_HDR2_MATRIXI_PRE_OFFSET2 0x380d
+#define VD1_HDR2_MATRIXO_COEF00_01 0x380e
+#define VD1_HDR2_MATRIXO_COEF02_10 0x380f
+#define VD1_HDR2_MATRIXO_COEF11_12 0x3810
+#define VD1_HDR2_MATRIXO_COEF20_21 0x3811
+#define VD1_HDR2_MATRIXO_COEF22 0x3812
+#define VD1_HDR2_MATRIXO_COEF30_31 0x3813
+#define VD1_HDR2_MATRIXO_COEF32_40 0x3814
+#define VD1_HDR2_MATRIXO_COEF41_42 0x3815
+#define VD1_HDR2_MATRIXO_OFFSET0_1 0x3816
+#define VD1_HDR2_MATRIXO_OFFSET2 0x3817
+#define VD1_HDR2_MATRIXO_PRE_OFFSET0_1 0x3818
+#define VD1_HDR2_MATRIXO_PRE_OFFSET2 0x3819
+#define VD1_HDR2_MATRIXI_CLIP 0x381a
+#define VD1_HDR2_MATRIXO_CLIP 0x381b
+#define VD1_HDR2_CGAIN_OFFT 0x381c
+#define VD1_EOTF_LUT_ADDR_PORT 0x381e
+#define VD1_EOTF_LUT_DATA_PORT 0x381f
+#define VD1_OETF_LUT_ADDR_PORT 0x3820
+#define VD1_OETF_LUT_DATA_PORT 0x3821
+#define VD1_CGAIN_LUT_ADDR_PORT 0x3822
+#define VD1_CGAIN_LUT_DATA_PORT 0x3823
+#define VD1_HDR2_CGAIN_COEF0 0x3824
+#define VD1_HDR2_CGAIN_COEF1 0x3825
+#define VD1_OGAIN_LUT_ADDR_PORT 0x3826
+#define VD1_OGAIN_LUT_DATA_PORT 0x3827
+#define VD1_HDR2_ADPS_CTRL 0x3828
+#define VD1_HDR2_ADPS_ALPHA0 0x3829
+#define VD1_HDR2_ADPS_ALPHA1 0x382a
+#define VD1_HDR2_ADPS_BETA0 0x382b
+#define VD1_HDR2_ADPS_BETA1 0x382c
+#define VD1_HDR2_ADPS_BETA2 0x382d
+#define VD1_HDR2_ADPS_COEF0 0x382e
+#define VD1_HDR2_ADPS_COEF1 0x382f
+#define VD1_HDR2_GMUT_CTRL 0x3830
+#define VD1_HDR2_GMUT_COEF0 0x3831
+#define VD1_HDR2_GMUT_COEF1 0x3832
+#define VD1_HDR2_GMUT_COEF2 0x3833
+#define VD1_HDR2_GMUT_COEF3 0x3834
+#define VD1_HDR2_GMUT_COEF4 0x3835
+#define VD1_HDR2_PIPE_CTRL1 0x3836
+#define VD1_HDR2_PIPE_CTRL2 0x3837
+#define VD1_HDR2_PIPE_CTRL3 0x3838
+#define VD1_HDR2_PROC_WIN1 0x3839
+#define VD1_HDR2_PROC_WIN2 0x383a
+#define VD1_HDR2_MATRIXI_EN_CTRL 0x383b
+#define VD1_HDR2_MATRIXO_EN_CTRL 0x383c
+
+#define VD2_HDR2_CTRL 0x3850
+#define VD2_HDR2_CLK_GATE 0x3851
+#define VD2_HDR2_MATRIXI_COEF00_01 0x3852
+#define VD2_HDR2_MATRIXI_COEF02_10 0x3853
+#define VD2_HDR2_MATRIXI_COEF11_12 0x3854
+#define VD2_HDR2_MATRIXI_COEF20_21 0x3855
+#define VD2_HDR2_MATRIXI_COEF22 0x3856
+#define VD2_HDR2_MATRIXI_COEF30_31 0x3857
+#define VD2_HDR2_MATRIXI_COEF32_40 0x3858
+#define VD2_HDR2_MATRIXI_COEF41_42 0x3859
+#define VD2_HDR2_MATRIXI_OFFSET0_1 0x385a
+#define VD2_HDR2_MATRIXI_OFFSET2 0x385b
+#define VD2_HDR2_MATRIXI_PRE_OFFSET0_1 0x385c
+#define VD2_HDR2_MATRIXI_PRE_OFFSET2 0x385d
+#define VD2_HDR2_MATRIXO_COEF00_01 0x385e
+#define VD2_HDR2_MATRIXO_COEF02_10 0x385f
+#define VD2_HDR2_MATRIXO_COEF11_12 0x3860
+#define VD2_HDR2_MATRIXO_COEF20_21 0x3861
+#define VD2_HDR2_MATRIXO_COEF22 0x3862
+#define VD2_HDR2_MATRIXO_COEF30_31 0x3863
+#define VD2_HDR2_MATRIXO_COEF32_40 0x3864
+#define VD2_HDR2_MATRIXO_COEF41_42 0x3865
+#define VD2_HDR2_MATRIXO_OFFSET0_1 0x3866
+#define VD2_HDR2_MATRIXO_OFFSET2 0x3867
+#define VD2_HDR2_MATRIXO_PRE_OFFSET0_1 0x3868
+#define VD2_HDR2_MATRIXO_PRE_OFFSET2 0x3869
+#define VD2_HDR2_MATRIXI_CLIP 0x386a
+#define VD2_HDR2_MATRIXO_CLIP 0x386b
+#define VD2_HDR2_CGAIN_OFFT 0x386c
+#define VD2_EOTF_LUT_ADDR_PORT 0x386e
+#define VD2_EOTF_LUT_DATA_PORT 0x386f
+#define VD2_OETF_LUT_ADDR_PORT 0x3870
+#define VD2_OETF_LUT_DATA_PORT 0x3871
+#define VD2_CGAIN_LUT_ADDR_PORT 0x3872
+#define VD2_CGAIN_LUT_DATA_PORT 0x3873
+#define VD2_HDR2_CGAIN_COEF0 0x3874
+#define VD2_HDR2_CGAIN_COEF1 0x3875
+#define VD2_OGAIN_LUT_ADDR_PORT 0x3876
+#define VD2_OGAIN_LUT_DATA_PORT 0x3877
+#define VD2_HDR2_ADPS_CTRL 0x3878
+#define VD2_HDR2_ADPS_ALPHA0 0x3879
+#define VD2_HDR2_ADPS_ALPHA1 0x387a
+#define VD2_HDR2_ADPS_BETA0 0x387b
+#define VD2_HDR2_ADPS_BETA1 0x387c
+#define VD2_HDR2_ADPS_BETA2 0x387d
+#define VD2_HDR2_ADPS_COEF0 0x387e
+#define VD2_HDR2_ADPS_COEF1 0x387f
+#define VD2_HDR2_GMUT_CTRL 0x3880
+#define VD2_HDR2_GMUT_COEF0 0x3881
+#define VD2_HDR2_GMUT_COEF1 0x3882
+#define VD2_HDR2_GMUT_COEF2 0x3883
+#define VD2_HDR2_GMUT_COEF3 0x3884
+#define VD2_HDR2_GMUT_COEF4 0x3885
+#define VD2_HDR2_PIPE_CTRL1 0x3886
+#define VD2_HDR2_PIPE_CTRL2 0x3887
+#define VD2_HDR2_PIPE_CTRL3 0x3888
+#define VD2_HDR2_PROC_WIN1 0x3889
+#define VD2_HDR2_PROC_WIN2 0x388a
+#define VD2_HDR2_MATRIXI_EN_CTRL 0x388b
+#define VD2_HDR2_MATRIXO_EN_CTRL 0x388c
+
+#define OSD1_HDR2_CTRL 0x38a0
+#define OSD1_HDR2_CLK_GATE 0x38a1
+#define OSD1_HDR2_MATRIXI_COEF00_01 0x38a2
+#define OSD1_HDR2_MATRIXI_COEF02_10 0x38a3
+#define OSD1_HDR2_MATRIXI_COEF11_12 0x38a4
+#define OSD1_HDR2_MATRIXI_COEF20_21 0x38a5
+#define OSD1_HDR2_MATRIXI_COEF22 0x38a6
+#define OSD1_HDR2_MATRIXI_COEF30_31 0x38a7
+#define OSD1_HDR2_MATRIXI_COEF32_40 0x38a8
+#define OSD1_HDR2_MATRIXI_COEF41_42 0x38a9
+#define OSD1_HDR2_MATRIXI_OFFSET0_1 0x38aa
+#define OSD1_HDR2_MATRIXI_OFFSET2 0x38ab
+#define OSD1_HDR2_MATRIXI_PRE_OFFSET0_1 0x38ac
+#define OSD1_HDR2_MATRIXI_PRE_OFFSET2 0x38ad
+#define OSD1_HDR2_MATRIXO_COEF00_01 0x38ae
+#define OSD1_HDR2_MATRIXO_COEF02_10 0x38af
+#define OSD1_HDR2_MATRIXO_COEF11_12 0x38b0
+#define OSD1_HDR2_MATRIXO_COEF20_21 0x38b1
+#define OSD1_HDR2_MATRIXO_COEF22 0x38b2
+#define OSD1_HDR2_MATRIXO_COEF30_31 0x38b3
+#define OSD1_HDR2_MATRIXO_COEF32_40 0x38b4
+#define OSD1_HDR2_MATRIXO_COEF41_42 0x38b5
+#define OSD1_HDR2_MATRIXO_OFFSET0_1 0x38b6
+#define OSD1_HDR2_MATRIXO_OFFSET2 0x38b7
+#define OSD1_HDR2_MATRIXO_PRE_OFFSET0_1 0x38b8
+#define OSD1_HDR2_MATRIXO_PRE_OFFSET2 0x38b9
+#define OSD1_HDR2_MATRIXI_CLIP 0x38ba
+#define OSD1_HDR2_MATRIXO_CLIP 0x38bb
+#define OSD1_HDR2_CGAIN_OFFT 0x38bc
+#define OSD1_EOTF_LUT_ADDR_PORT 0x38be
+#define OSD1_EOTF_LUT_DATA_PORT 0x38bf
+#define OSD1_OETF_LUT_ADDR_PORT 0x38c0
+#define OSD1_OETF_LUT_DATA_PORT 0x38c1
+#define OSD1_CGAIN_LUT_ADDR_PORT 0x38c2
+#define OSD1_CGAIN_LUT_DATA_PORT 0x38c3
+#define OSD1_HDR2_CGAIN_COEF0 0x38c4
+#define OSD1_HDR2_CGAIN_COEF1 0x38c5
+#define OSD1_OGAIN_LUT_ADDR_PORT 0x38c6
+#define OSD1_OGAIN_LUT_DATA_PORT 0x38c7
+#define OSD1_HDR2_ADPS_CTRL 0x38c8
+#define OSD1_HDR2_ADPS_ALPHA0 0x38c9
+#define OSD1_HDR2_ADPS_ALPHA1 0x38ca
+#define OSD1_HDR2_ADPS_BETA0 0x38cb
+#define OSD1_HDR2_ADPS_BETA1 0x38cc
+#define OSD1_HDR2_ADPS_BETA2 0x38cd
+#define OSD1_HDR2_ADPS_COEF0 0x38ce
+#define OSD1_HDR2_ADPS_COEF1 0x38cf
+#define OSD1_HDR2_GMUT_CTRL 0x38d0
+#define OSD1_HDR2_GMUT_COEF0 0x38d1
+#define OSD1_HDR2_GMUT_COEF1 0x38d2
+#define OSD1_HDR2_GMUT_COEF2 0x38d3
+#define OSD1_HDR2_GMUT_COEF3 0x38d4
+#define OSD1_HDR2_GMUT_COEF4 0x38d5
+#define OSD1_HDR2_PIPE_CTRL1 0x38d6
+#define OSD1_HDR2_PIPE_CTRL2 0x38d7
+#define OSD1_HDR2_PIPE_CTRL3 0x38d8
+#define OSD1_HDR2_PROC_WIN1 0x38d9
+#define OSD1_HDR2_PROC_WIN2 0x38da
+#define OSD1_HDR2_MATRIXI_EN_CTRL 0x38db
+#define OSD1_HDR2_MATRIXO_EN_CTRL 0x38dc
diff --git a/arch/arm/include/asm/arch-g12b/romboot.h b/arch/arm/include/asm/arch-g12b/romboot.h
index 338365e..2967fbb 100644
--- a/arch/arm/include/asm/arch-g12b/romboot.h
+++ b/arch/arm/include/asm/arch-g12b/romboot.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/romboot.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __BOOT_ROM_H_
#define __BOOT_ROM_H_
diff --git a/arch/arm/include/asm/arch-g12b/saradc.h b/arch/arm/include/asm/arch-g12b/saradc.h
deleted file mode 100644
index 13d2d73..0000000
--- a/arch/arm/include/asm/arch-g12b/saradc.h
+++ /dev/null
@@ -1,20 +0,0 @@
-#ifndef __MESON_SARADC_H__
-#define __MESON_SARADC_H__
-
-#include <adc.h>
-
-enum ADC_CHANNEL_TYPE {
- MESON_SARADC_CH0 = 0,
- MESON_SARADC_CH1,
- MESON_SARADC_CH2,
- MESON_SARADC_CH3,
- MESON_SARADC_CH4,
- MESON_SARADC_CH5,
- MESON_SARADC_CH6,
- MESON_SARADC_CH7,
- MESON_SARADC_CH_MAX,
-};
-
-#define SARADC_CH_SELF_TEST MESON_SARADC_CH7
-
-#endif /*_MESON_SARADC_H_*/
diff --git a/arch/arm/include/asm/arch-g12b/sd_emmc.h b/arch/arm/include/asm/arch-g12b/sd_emmc.h
index 385a398..e8239b4 100644
--- a/arch/arm/include/asm/arch-g12b/sd_emmc.h
+++ b/arch/arm/include/asm/arch-g12b/sd_emmc.h
@@ -1,12 +1,11 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * (C) Copyright 2016 Carlo Caione <carlo@caione.org>
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __SD_EMMC_H__
#define __SD_EMMC_H__
-#include <clk.h>
#include <mmc.h>
#define SDIO_PORT_A 0
@@ -68,57 +67,57 @@
#define Cfg_adj_init 23
#define MESON_SD_EMMC_START 0x40
-#define CFG_DESC_INIT BIT(0)
-#define CFG_DESC_BUSY BIT(1)
-#define CFG_DESC_ADDR 2
+#define CFG_DESC_INIT BIT(0)
+#define CFG_DESC_BUSY BIT(1)
+#define CFG_DESC_ADDR 2
#define MESON_SD_EMMC_CFG 0x44
-#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
-#define CFG_BUS_WIDTH_1 0
-#define CFG_BUS_WIDTH_4 1
-#define CFG_BUS_WIDTH_8 2
-#define CFG_DDR BIT(2)
-#define CFG_BL_LEN_MASK GENMASK(7, 4)
-#define CFG_BL_LEN_SHIFT 4
-#define CFG_BL_LEN_512 (9 << 4)
-#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
-#define CFG_RESP_TIMEOUT_256 (8 << 8)
-#define CFG_RC_CC_MASK GENMASK(15, 12)
-#define CFG_RC_CC_16 (4 << 12)
-#define CFG_SDCLK_ALWAYS_ON BIT(18)
-#define CFG_AUTO_CLK BIT(23)
+#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
+#define CFG_BUS_WIDTH_1 0
+#define CFG_BUS_WIDTH_4 1
+#define CFG_BUS_WIDTH_8 2
+#define CFG_DDR BIT(2)
+#define CFG_BL_LEN_MASK GENMASK(7, 4)
+#define CFG_BL_LEN_SHIFT 4
+#define CFG_BL_LEN_512 (9 << 4)
+#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
+#define CFG_RESP_TIMEOUT_256 (8 << 8)
+#define CFG_RC_CC_MASK GENMASK(15, 12)
+#define CFG_RC_CC_16 (4 << 12)
+#define CFG_SDCLK_ALWAYS_ON BIT(18)
+#define CFG_AUTO_CLK BIT(23)
#define MESON_SD_EMMC_STATUS 0x48
-#define STATUS_MASK GENMASK(15, 0)
-#define STATUS_ERR_MASK GENMASK(12, 0)
-#define STATUS_RXD_ERR_MASK GENMASK(7, 0)
-#define STATUS_TXD_ERR BIT(8)
-#define STATUS_DESC_ERR BIT(9)
-#define STATUS_RESP_ERR BIT(10)
-#define STATUS_RESP_TIMEOUT BIT(11)
-#define STATUS_DESC_TIMEOUT BIT(12)
-#define STATUS_END_OF_CHAIN BIT(13)
+#define STATUS_MASK GENMASK(15, 0)
+#define STATUS_ERR_MASK GENMASK(12, 0)
+#define STATUS_RXD_ERR_MASK GENMASK(7, 0)
+#define STATUS_TXD_ERR BIT(8)
+#define STATUS_DESC_ERR BIT(9)
+#define STATUS_RESP_ERR BIT(10)
+#define STATUS_RESP_TIMEOUT BIT(11)
+#define STATUS_DESC_TIMEOUT BIT(12)
+#define STATUS_END_OF_CHAIN BIT(13)
#define MESON_SD_EMMC_IRQ_EN 0x4c
#define MESON_SD_EMMC_CMD_CFG 0x50
-#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
-#define CMD_CFG_BLOCK_MODE BIT(9)
-#define CMD_CFG_R1B BIT(10)
-#define CMD_CFG_END_OF_CHAIN BIT(11)
-#define CMD_CFG_TIMEOUT_4S (12 << 12)
-#define CMD_CFG_NO_RESP BIT(16)
-#define CMD_CFG_NO_CMD BIT(17)
-#define CMD_CFG_DATA_IO BIT(18)
-#define CMD_CFG_DATA_WR BIT(19)
-#define CMD_CFG_RESP_NOCRC BIT(20)
-#define CMD_CFG_RESP_128 BIT(21)
-#define CMD_CFG_RESP_NUM BIT(22)
-#define CMD_CFG_DATA_NUM BIT(23)
-#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
-#define CMD_CFG_CMD_INDEX_SHIFT 24
-#define CMD_CFG_ERR BIT(30)
-#define CMD_CFG_OWNER BIT(31)
+#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
+#define CMD_CFG_BLOCK_MODE BIT(9)
+#define CMD_CFG_R1B BIT(10)
+#define CMD_CFG_END_OF_CHAIN BIT(11)
+#define CMD_CFG_TIMEOUT_4S (12 << 12)
+#define CMD_CFG_NO_RESP BIT(16)
+#define CMD_CFG_NO_CMD BIT(17)
+#define CMD_CFG_DATA_IO BIT(18)
+#define CMD_CFG_DATA_WR BIT(19)
+#define CMD_CFG_RESP_NOCRC BIT(20)
+#define CMD_CFG_RESP_128 BIT(21)
+#define CMD_CFG_RESP_NUM BIT(22)
+#define CMD_CFG_DATA_NUM BIT(23)
+#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
+#define CMD_CFG_CMD_INDEX_SHIFT 24
+#define CMD_CFG_ERR BIT(30)
+#define CMD_CFG_OWNER BIT(31)
#define MESON_SD_EMMC_CMD_ARG 0x54
#define MESON_SD_EMMC_CMD_DAT 0x58
@@ -134,27 +133,4 @@
#define SD_EMMC_RESP_TIMEOUT_ERROR (1 << 4)
#define SD_EMMC_DESC_TIMEOUT_ERROR (1 << 5)
-struct meson_host {
- struct mmc *mmc;
- uint is_in;
- uint is_tuning;
- struct clk core;
- struct clk xtal;
- struct clk div2;
- struct clk mux;
- struct clk div;
- struct clk gate;
- struct gpio_desc gpio_cd;
- struct gpio_desc gpio_reset;
- char *blk_test;
- char* desc_buf;
-};
-
-struct meson_mmc_platdata {
- struct mmc_config cfg;
- struct mmc mmc;
- void *regbase;
- void *w_buf;
-};
-
#endif
diff --git a/arch/arm/include/asm/arch-g12b/secure_apb.h b/arch/arm/include/asm/arch-g12b/secure_apb.h
index 3278770..e3b74f2 100644
--- a/arch/arm/include/asm/arch-g12b/secure_apb.h
+++ b/arch/arm/include/asm/arch-g12b/secure_apb.h
@@ -1,15 +1,7 @@
-// ----------------------------------------------------------------------
-// This file is automatically generated from the script:
-//
-// ./create_headers_from_secure_apb4_h.pl
-//
-// and was applied to the file
-//
-// ./secure_apb4_ee.h ./ao_rti_reg.h
-//
-// DO NOT EDIT!!!!!
-// ----------------------------------------------------------------------
-//
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <asm/arch/regs.h>
diff --git a/arch/arm/include/asm/arch-g12b/timer.h b/arch/arm/include/asm/arch-g12b/timer.h
index 6710403..492cc8d 100644
--- a/arch/arm/include/asm/arch-g12b/timer.h
+++ b/arch/arm/include/asm/arch-g12b/timer.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/timer.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __TIMER_H
#define __TIMER_H
diff --git a/arch/arm/include/asm/arch-g12b/timing.h b/arch/arm/include/asm/arch-g12b/timing.h
old mode 100755
new mode 100644
index fc66ffd..10152a3
--- a/arch/arm/include/asm/arch-g12b/timing.h
+++ b/arch/arm/include/asm/arch-g12b/timing.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/timing.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __AML_TIMING_H_
#define __AML_TIMING_H_
@@ -54,27 +38,167 @@
/* etc... */
typedef struct bl2_reg {
- unsigned int reg;
- unsigned int value;
- unsigned int mask;
- unsigned short udelay;
- unsigned char flag;
- unsigned char rsv_0;
+ unsigned int reg;
+ unsigned int value;
+ unsigned int mask;
+ unsigned short udelay;
+ unsigned char flag;
+ unsigned char rsv_0;
}__attribute__ ((packed)) bl2_reg_t;
typedef struct ddr_reg {
- unsigned int reg;
- unsigned int value;
- unsigned int mask;
- unsigned short udelay;
- unsigned char flag;
- unsigned char rsv_0;
+ unsigned int reg;
+ unsigned int value;
+ unsigned int mask;
+ unsigned short udelay;
+ unsigned char flag;
+ unsigned char rsv_0;
}__attribute__ ((packed)) ddr_reg_t;
+typedef struct training_delay_set_ps{
+ unsigned char ac_trace_delay[10];
+ unsigned char ac_trace_delay_rev[2];
+ unsigned char read_dqs_delay[16];
+ unsigned char read_dq_bit_delay[72];
+ unsigned short write_dqs_delay[16];
+// */
+ unsigned short write_dq_bit_delay[72];
+ unsigned short read_dqs_gate_delay[16];
+ unsigned char soc_bit_vref[36];
+ unsigned char dram_bit_vref[32];
+ ///*
+ unsigned char rever1;//read_dqs read_dq,write_dqs, write_dq
+ unsigned char dfi_mrl;
+ unsigned char dfi_hwtmrl;
+ unsigned char ARdPtrInitVal;
+ unsigned short csr_vrefinglobal;
+ unsigned short csr_dqsrcvcntrl[4];
+ unsigned short csr_pptdqscntinvtrntg0[4];
+ unsigned short csr_pptdqscntinvtrntg1[4];
+ unsigned short csr_seq0bgpr[9];
+ unsigned short csr_dllgainctl;
+ unsigned short csr_dlllockpara;
+// unsigned short rever2;
+}__attribute__ ((packed)) training_delay_set_ps_t;
+
+typedef struct ddr_mrs_reg {
+ unsigned int cfg_ddr_mr[8];
+ unsigned int cfg_ddr_mr11;
+ unsigned int cfg_ddr_mr12;
+ unsigned int cfg_ddr_mr13;
+ unsigned int cfg_ddr_mr14;
+ unsigned int cfg_ddr_mr16;
+ unsigned int cfg_ddr_mr17;
+ unsigned int cfg_ddr_mr22;
+ unsigned int cfg_ddr_mr24;
+}__attribute__ ((packed)) ddr_mrs_reg_t;
+
+typedef struct ddr_timing{
+ unsigned int identifier;
+ unsigned int cfg_ddr_mrd;
+ unsigned int cfg_ddr_rfcab;
+ unsigned int cfg_ddr_rfcpb;
+ unsigned int cfg_ddr_rpab;
+ unsigned int cfg_ddr_rppb;
+ unsigned int cfg_ddr_rtw;
+ unsigned int cfg_ddr_rl;
+ unsigned int cfg_ddr_wl;
+ unsigned int cfg_ddr_ras;
+ unsigned int cfg_ddr_rc;
+ unsigned int cfg_ddr_rcd;
+ unsigned int cfg_ddr_rrds;
+ unsigned int cfg_ddr_rrdl;
+ unsigned int cfg_ddr_faw;
+ unsigned int cfg_ddr_rtp;
+ unsigned int cfg_ddr_wr;
+ unsigned int cfg_ddr_wtrs;
+ unsigned int cfg_ddr_wtrl;
+ unsigned int cfg_ddr_ccds;
+ unsigned int cfg_ddr_ccdl;
+ unsigned int cfg_ddr_exsr;
+ unsigned int cfg_ddr_xs;
+ unsigned int cfg_ddr_xp;
+ unsigned int cfg_ddr_xpdll;
+ unsigned int cfg_ddr_zqcs;
+ unsigned int cfg_ddr_cksre;
+ unsigned int cfg_ddr_cksrx;
+ unsigned int cfg_ddr_cke;
+ unsigned int cfg_ddr_mod;
+ unsigned int cfg_ddr_dqs;
+ unsigned int cfg_ddr_rstl;
+ unsigned int cfg_ddr_zqlat;
+ unsigned int cfg_ddr_mrr;
+ unsigned int cfg_ddr_ckesr;
+ unsigned int cfg_ddr_dpd;
+ unsigned int cfg_ddr_ckeck;
+ unsigned int cfg_ddr_refi;
+ unsigned int cfg_ddr_sr;
+ unsigned int cfg_ddr_ccdmw;
+ unsigned int cfg_ddr_escke;
+ unsigned int cfg_ddr_refi_ddr3;
+ unsigned int cfg_ddr_dfictrldelay;
+ unsigned int cfg_ddr_dfiphywrdata;
+ unsigned int cfg_ddr_dfiphywrlat;
+ unsigned int cfg_ddr_dfiphyrddataen;
+ unsigned int cfg_ddr_dfiphyrdlat;
+ unsigned int cfg_ddr_dfictrlupdmin;
+ unsigned int cfg_ddr_dfictrlupdmax;
+ unsigned int cfg_ddr_dfimstrresp;
+ unsigned int cfg_ddr_dfirefmski;
+ unsigned int cfg_ddr_dfictrlupdi;
+ unsigned int cfg_ddr_dfidramclk;
+ unsigned int cfg_ddr_dfilpresp;
+ unsigned int cfg_ddr_dfiphymstr;
+ unsigned int cfg_ddr_rtodt;
+ unsigned int cfg_ddr_wlmrd;
+ unsigned int cfg_ddr_wlo;
+ unsigned int cfg_ddr_al;
+ unsigned int cfg_ddr_zqcl;
+ unsigned int cfg_ddr_zqcsi;
+ unsigned int cfg_ddr_zqreset;
+ unsigned int cfg_ddr_tdqsck_min;
+ unsigned int cfg_ddr_tdqsck_max;
+ //training_delay_set_ps_t cfg_ddr_training_delay_ps;
+ ddr_mrs_reg_t cfg_ddr_mrs_reg_ps[2];
+ unsigned int dfi_odt1_config_ps[2];
+ //ddr_mrs_reg_t cfg_ddr_mrs_reg_ps1;
+ #if 0
+ unsigned int cfg_ddr_mr[8];
+ unsigned int cfg_ddr_mr11;
+ unsigned int cfg_ddr_mr12;
+ unsigned int cfg_ddr_mr13;
+ unsigned int cfg_ddr_mr14;
+ unsigned int cfg_ddr_mr16;
+ unsigned int cfg_ddr_mr17;
+ unsigned int cfg_ddr_mr22;
+ unsigned int cfg_ddr_mr24;
+ unsigned int cfg_ddr_reserve[5];
+ #endif
+}__attribute__ ((packed)) ddr_timing_t;
+
+typedef struct ddr_phy_common_extra_set{
+ unsigned short csr_pllctrl3;
+ unsigned short csr_pptctlstatic[4];
+ unsigned short csr_trainingincdecdtsmen[4];
+ unsigned short csr_tsmbyte0[4];
+ unsigned short csr_hwtcamode;
+ unsigned short csr_hwtlpcsena;
+ unsigned short csr_hwtlpcsenb;
+ unsigned short csr_acsmctrl13;
+ unsigned short csr_acsmctrl23;
+ unsigned char csr_soc_vref_dac1_dfe[36];
+}__attribute__ ((packed)) ddr_phy_common_extra_set_t;
+
+typedef struct retraining_set{
+ ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t;
+ training_delay_set_ps_t cfg_ddr_training_delay_ps;
+}__attribute__ ((packed)) retraining_set_t;
+
typedef struct ddr_set{
unsigned int magic;
unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test
//unsigned int rsv_int0;
+ unsigned int ddr_func;
unsigned char board_id;
//board id reserve,,do not modify
unsigned char version;
@@ -110,12 +234,19 @@
/* rsv_char0. update for diagnose type define */
unsigned char diagnose;
+ unsigned short soc_data_drv_ohm_ps1;
+ unsigned short dram_data_drv_ohm_ps1;
+ unsigned short soc_data_odt_ohm_ps1;
+ unsigned short dram_data_odt_ohm_ps1;
+ unsigned short dram_data_wr_odt_ohm_ps1;
+ #if 0
/* imem/dmem define */
unsigned int imem_load_addr;
//system reserve,do not modify
unsigned int dmem_load_addr;
//system reserve,do not modify
unsigned short imem_load_size;
+ #endif
//system reserve,do not modify
unsigned short dmem_load_size;
//system reserve,do not modify
@@ -133,8 +264,9 @@
unsigned short training_SequenceCtrl[2];
//system reserve,do not modify
unsigned char phy_odt_config_rank[2];
- unsigned char rever1;
- unsigned char rever2;
+ //unsigned char rever1;
+ //unsigned char rever2;
+ unsigned short rank1_ca_vref_permil;
//training odt config ,only use for training
// [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
// [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
@@ -224,78 +356,60 @@
//soc init DRAM receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
unsigned short max_core_timmming_frequency;
//use for limited ddr speed core timmming parameter,for some old dram maybe have no over speed register
+ /* align8 */
unsigned char ac_trace_delay[10];
unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting;
//use for lpddr4 read vout voltage setting 0 --->2/5VDDQ ,1--->1/3VDDQ
unsigned char lpddr4_x8_mode;
- //system reserve,do not modify ,take care ,please follow SI
- unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL];
- //use for lpddr3 /lpddr4 ca pinmux remap
- unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL];
- unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,[1],slt test parameter ,use for force delay line offset
- //system reserve,do not modify
+ unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function
+ //[1],slt test parameter ,use for force delay line offset
+ //system reserve,do not modify
unsigned short tdqs2dq;
- unsigned char dram_data_wr_odt_ohm;
+ unsigned char dram_data_wr_odt_ohm;
unsigned char bitTimeControl_2d;
//system reserve,do not modify
/* align8 */
-
+ unsigned char char_rev1;
+ unsigned char training_offset;//char_rev2;
unsigned int ddr_dmc_remap[5];
+ unsigned int dram_rtt_nom_wr_park[2];
//system reserve,do not modify
/* align8 */
- unsigned char ddr_lpddr34_ca_remap[4];
+ unsigned char ddr_lpddr34_ca_remap[4];
////use for lpddr3 /lpddr4 ca training data byte lane remap
unsigned char ddr_lpddr34_dq_remap[32];
////use for lpddr3 /lpddr4 ca pinmux remap
- unsigned int dram_rtt_nom_wr_park[2];
- //system reserve,do not modify
- unsigned int ddr_func;
- //system reserve,do not modify
- /* align8 */
+ unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL];
+ //use for lpddr3 /lpddr4 ca pinmux remap
+ unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL];
+ unsigned char char_rev3;
+ unsigned char char_rev4;
+ ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t;
+ training_delay_set_ps_t cfg_ddr_training_delay_ps[2];
- //unsigned long rsv_long0[2];
- /* v1 end */
- //unsigned char read_dqs_adjust[16]; //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read
- //unsigned char read_dq_bit_delay[72];
- //unsigned char write_dq_bit_delay[72];
-
-///*
- unsigned char read_dqs_delay[16];
- unsigned char read_dq_bit_delay[72];
- unsigned short write_dqs_delay[16];
-//*/
- unsigned short write_dq_bit_delay[72];
- unsigned short read_dqs_gate_delay[16];
- unsigned char soc_bit_vref[32];
- unsigned char dram_bit_vref[32];
-// /*
- unsigned char rever3;//read_dqs read_dq,write_dqs, write_dq
- unsigned char dfi_mrl;
- unsigned char dfi_hwtmrl;
- unsigned char ARdPtrInitVal;
- unsigned char retraining[16];
//override read bit delay
}__attribute__ ((packed)) ddr_set_t;
typedef struct pll_set{
- unsigned short cpu_clk;
- unsigned short pxp;
- unsigned int spi_ctrl;
- unsigned short vddee;
- unsigned short vcck;
- unsigned char szPad[4];
+ unsigned short cpu_clk;
+ unsigned short pxp;
+ unsigned int spi_ctrl;
+ unsigned short vddee;
+ unsigned short vcck;
+ unsigned char szPad[4];
- unsigned long lCustomerID;
- unsigned short debug_mode;
- unsigned short rsv1;
- unsigned short rsv2;
- unsigned short rsv3;
+ unsigned long lCustomerID;
+ unsigned char debug_mode;
+ unsigned char log_chl;
+ unsigned char log_ctrl;
+ unsigned char ddr_timming_save_mode;
+ unsigned int nCFGTAddr;
/* align 8Byte */
- unsigned int sys_pll_cntl[8];
- unsigned int ddr_pll_cntl[8];
- unsigned int fix_pll_cntl[8];
+ unsigned int sys_pll_cntl[8];
+ unsigned int ddr_pll_cntl[8];
+ unsigned int fix_pll_cntl[8];
}__attribute__ ((packed)) pll_set_t;
typedef struct dmem_cfg {
@@ -307,4 +421,4 @@
PMU_SMB_LPDDR4_2D_t lpddr4u_2d;
} dmem_cfg_t;
-#endif //__AML_TIMING_H_
+#endif //__AML_TIMING_H_
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-g12b/tsensor.h b/arch/arm/include/asm/arch-g12b/tsensor.h
index 54dbb7f..f35f559 100644
--- a/arch/arm/include/asm/arch-g12b/tsensor.h
+++ b/arch/arm/include/asm/arch-g12b/tsensor.h
@@ -1,29 +1,15 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-g12a/tsensor.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __TSENSOR_H__
#define __TSENSOR_H__
#define CONFIG_HIGH_TEMP_COOL 90
-#define T_AVG_NUM 16 /*read temp cnt*/
+#define T_AVG_NUM 16 /*trim temp cnt*/
+#define T_READ_NUM 2 /*read temp cnt*/
#define T_VER_MASK 0x80
#define T_VALUE_MIN 0x1500
#define T_VALUE_MAX 0x3500
diff --git a/arch/arm/include/asm/arch-g12b/types.h b/arch/arm/include/asm/arch-g12b/types.h
index cab85ed..2d362b1 100644
--- a/arch/arm/include/asm/arch-g12b/types.h
+++ b/arch/arm/include/asm/arch-g12b/types.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __TYPES_H
#define __TYPES_H
diff --git a/arch/arm/include/asm/arch-g12b/uart.h b/arch/arm/include/asm/arch-g12b/uart.h
index 8f71c5a..22edaa7 100644
--- a/arch/arm/include/asm/arch-g12b/uart.h
+++ b/arch/arm/include/asm/arch-g12b/uart.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/uart.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __MESON_FIRM_UART_H_
#define __MESON_FIRM_UART_H_
diff --git a/arch/arm/include/asm/arch-g12b/usb.h b/arch/arm/include/asm/arch-g12b/usb.h
index 445f15a..f2669d5 100644
--- a/arch/arm/include/asm/arch-g12b/usb.h
+++ b/arch/arm/include/asm/arch-g12b/usb.h
@@ -1,22 +1,7 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/include/asm/arch-txl/usb-new.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __ARCH_ARM_MESON_USB_H_U_BOOT__
#define __ARCH_ARM_MESON_USB_H_U_BOOT__
@@ -25,6 +10,8 @@
#include <asm/types.h>
#include <asm/arch/io.h>
#include <asm/arch/secure_apb.h>
+#include <generic-phy.h>
+#include <asm-generic/gpio.h>
#define USB_PHY_PORT_MAX 1
/* Phy register MACRO definitions */
@@ -89,6 +76,22 @@
/* XHCI PHY register structure */
#define PHY_REGISTER_SIZE 0x20
+
+struct phy_aml_usb2_priv {
+ unsigned int base_addr;
+ unsigned int reset_addr;
+ unsigned int dwc2_a_addr;
+ unsigned int u2_port_num;
+ unsigned int usbphy_reset_bit[8];
+ unsigned int usb_phy2_pll_base_addr[4];
+};
+
+struct phy_aml_usb3_priv {
+ unsigned int base_addr;
+ unsigned int usb3_port_num;
+ struct gpio_desc desc;
+};
+
/* Register definitions */
typedef struct u2p_aml_regs {
volatile uint32_t u2p_r0;
@@ -231,5 +234,13 @@
#define USB_ID_MODE_HARDWARE (1)
#define USB_ID_MODE_SW_HOST (2)
#define USB_ID_MODE_SW_DEVICE (3)
+int usb2_phy_tuning(uint32_t phy2_pll_base, int port);
+void set_usb_pll(uint32_t phy2_pll_base);
+int usb_save_phy_dev (unsigned int number, struct phy *phy);
+int usb2_phy_init (struct phy *phy);
+unsigned int usb_get_dwc_a_base_addr(void);
+unsigned int usb_get_device_mode_phy_base(void);
+void usb_phy_tuning_reset(void);
+void usb_device_mode_init(void);
#endif
diff --git a/arch/arm/include/asm/arch-g12b/watchdog.h b/arch/arm/include/asm/arch-g12b/watchdog.h
deleted file mode 100644
index bf61981..0000000
--- a/arch/arm/include/asm/arch-g12b/watchdog.h
+++ /dev/null
@@ -1,37 +0,0 @@
-
-/*
- * arch/arm/include/asm/arch-txl/watchdog.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#ifndef _BOOT_ROM_WATCHDOG_H
-#define _BOOT_ROM_WATCHDOG_H
-
-#include <asm/arch/secure_apb.h>
-
-//#include "common.h"
-
-void watchdog_init(uint32_t msec);
-void watchdog_reset(void);
-void reset_system(void);
-void watchdog_disable(void);
-
-/* uboot reset interface */
-void reset_cpu(unsigned long flag);
-
-#endif /* _BOOT_ROM_WATCHDOG_H */
diff --git a/arch/arm/include/asm/arch-s4/acs.h b/arch/arm/include/asm/arch-s4/acs.h
new file mode 100644
index 0000000..7727f14
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/acs.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __ACS_H
+#define __ACS_H
+
+#define CHIP_PARAM_MAGIC 0x50696863 //"chiP"
+#define DEV_PARAM_MAGIC 0x50766564 //"devP"
+
+#define CHIP_PARAM_VERSION 0x1
+#define DEV_PARAM_VERSION 0x1
+
+#ifndef __ASSEMBLY__
+
+typedef struct dev_param_hdr {
+ unsigned int magic;
+ unsigned int version;
+
+ char bl2_regs_magic[6];
+ unsigned short bl2_regs_length;
+
+ char board_clk_magic[6];
+ unsigned short board_clk_length;
+
+ char opt_reg_magic[6];
+ unsigned short opt_reg_length;
+
+ char sto_set_magic[6];
+ unsigned short sto_set_length;
+
+ char ddr_set_magic[6];
+ unsigned short ddr_set_length;
+
+ unsigned int RFU[4];
+} __attribute__ ((packed)) dev_param_hdr_t;
+
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-s4/bl31_apis.h b/arch/arm/include/asm/arch-s4/bl31_apis.h
new file mode 100644
index 0000000..9e99395
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/bl31_apis.h
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ * Trustzone API
+ *
+ * Copyright (C) 2012 Amlogic, Inc.
+ *
+ * Author: Platform-SH@amlogic.com
+ *
+ */
+
+#ifndef __GXBB_BL31_APIS_H
+#define __GXBB_BL31_APIS_H
+
+#include <asm/arch/io.h>
+
+/*#define SRAM_READ 0x82000010
+#define CORE_RD_REV1 0x82000011
+#define SRAM_ACS_READ 0x82000012
+#define SRAM_ACS_INDIRECT_READ 0x82000013*/
+
+#define GET_SHARE_MEM_INPUT_BASE 0x82000020
+#define GET_SHARE_MEM_OUTPUT_BASE 0x82000021
+#define GET_REBOOT_REASON 0x82000022
+#define GET_SHARE_STORAGE_IN_BASE 0x82000023
+#define GET_SHARE_STORAGE_OUT_BASE 0x82000024
+#define GET_SHARE_STORAGE_BLOCK_BASE 0x82000025
+#define GET_SHARE_STORAGE_MESSAGE_BASE 0x82000026
+#define GET_SHARE_STORAGE_BLOCK_SIZE 0x82000027
+#define SET_STORAGE_INFO 0x82000028
+#define SET_STORAGE_BOOTSEQUENCE 0x82000029
+#define SET_REBOOT_REASON 0x82000049
+
+/* Set Reboot Reason then Reboot*/
+#define PSCI_SYS_REBOOT 0x84000009
+
+/* SECUREOS DEFINITION*/
+/* SMC Identifiers for non-secure world functions */
+#define CALL_TRUSTZONE_HAL_API 0x5
+
+/* EFUSE */
+#define EFUSE_READ 0x82000030
+#define EFUSE_WRITE 0x82000031
+#define EFUSE_WRITE_PATTERN 0x82000032
+#define EFUSE_USER_MAX 0x82000033
+
+#define DEBUG_EFUSE_WRITE_PATTERN 0x820000F0
+#define DEBUG_EFUSE_READ_PATTERN 0x820000F1
+
+/* JTAG*/
+#define JTAG_ON 0x82000040
+#define JTAG_OFF 0x82000041
+
+#define SET_USB_BOOT_FUNC 0x82000043
+ /* USB BOOT FUNC sub command list*/
+ #define CLEAR_USB_BOOT 1
+ #define FORCE_USB_BOOT 2
+ #define RUN_COMD_USB_BOOT 3
+ #define PANIC_DUMP_USB_BOOT 4
+
+#define GET_CHIP_ID 0x82000044
+
+/* tsensor calibration data */
+#define TSENSOR_CALI_SET 0x8200004C
+#define TSENSOR_CALI_READ 0x82000047
+
+/*oscring efuse value get */
+#define OSCRING_EFUSE_GET 0x8200004D
+/* Security Key*/
+#define SECURITY_KEY_QUERY 0x82000060
+#define SECURITY_KEY_READ 0x82000061
+#define SECURITY_KEY_WRITE 0x82000062
+#define SECURITY_KEY_TELL 0x82000063
+#define SECURITY_KEY_VERIFY 0x82000064
+#define SECURITY_KEY_STATUS 0x82000065
+#define SECURITY_KEY_NOTIFY 0x82000066
+#define SECURITY_KEY_LIST 0x82000067
+#define SECURITY_KEY_REMOVE 0x82000068
+#define SECURITY_KEY_NOTIFY_EX 0x82000069
+#define SECURITY_KEY_SET_ENCTYPE 0x8200006A
+#define SECURITY_KEY_GET_ENCTYPE 0x8200006B
+#define SECURITY_KEY_VERSION 0x8200006C
+
+/*viu probe en*/
+#define VIU_PREOBE_EN 0x82000080
+/*set boot first timeout*/
+#define SET_BOOT_FIRST 0x82000087
+
+/* KEYMASTER */
+#define SET_BOOT_PARAMS 0x82000072
+#define SHA256_DIGEST_SIZE 32
+typedef struct {
+ uint32_t device_locked;
+ uint32_t verified_boot_state;
+ uint8_t verified_boot_key[SHA256_DIGEST_SIZE];
+ uint8_t verified_boot_hash[SHA256_DIGEST_SIZE];
+} keymaster_boot_params;
+
+/* Secure HAL APIs */
+#define TRUSTZONE_HAL_API_SRAM 0x400
+
+/*start hifi4 */
+#define START_HIFI4 0x82000090
+#define DSP_SEC_POWERSET 0x82000092
+
+
+#define SRAM_HAL_API_CHECK_EFUSE 0x403
+struct sram_hal_api_arg {
+ unsigned int cmd;
+ unsigned int req_len;
+ unsigned int res_len;
+ unsigned long req_phy_addr;
+ unsigned long res_phy_addr;
+ unsigned long ret_phy_addr;
+};
+
+#define JTAG_STATE_ON 0
+#define JTAG_STATE_OFF 1
+#define JTAG_M3_AO 0
+#define JTAG_M3_EE 1
+#define JTAG_A53_AO 2
+#define JTAG_A53_EE 3
+#define CLUSTER_BIT 2
+
+
+/* AVB2 */
+#define GET_AVBKEY_FROM_FIP 0x820000b0
+
+/////////////////////////////////////////////////////////////////////////////////
+#define AML_DATA_PROCESS (0x820000FF)
+ #define AML_D_P_W_EFUSE_SECURE_BOOT (0x10)
+ #define AML_D_P_W_EFUSE_PASSWORD (0x11)
+ #define AML_D_P_W_EFUSE_CUSTOMER_ID (0x12)
+ #define AML_D_P_W_EFUSE_AMLOGIC (0x20)
+ #define AML_D_P_IMG_DECRYPT (0x40)
+ #define AML_D_P_UPGRADE_CHECK (0x80)
+
+#define GXB_EFUSE_PATTERN_SIZE (0x2 << 9)
+#define GXB_IMG_SIZE (24<<20)
+#define GXB_IMG_LOAD_ADDR (0x1080000)
+ #define GXB_IMG_DEC_KNL (1<<0)
+ #define GXB_IMG_DEC_RMD (1<<1)
+ #define GXB_IMG_DEC_DTB (1<<2)
+ #define GXB_IMG_DEC_ALL (GXB_IMG_DEC_KNL|GXB_IMG_DEC_RMD|GXB_IMG_DEC_DTB)
+
+#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+void aml_set_jtag_state(unsigned state, unsigned select);
+unsigned aml_get_reboot_reason(void);
+unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2);
+void aml_set_bootsequence(uint32_t val);
+void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2);
+unsigned long aml_sec_boot_check(unsigned long ,unsigned long ,unsigned long,unsigned long );
+long get_sharemem_info(unsigned long);
+void set_usb_boot_function(unsigned long command);
+void aml_system_off(void);
+
+void bl31_get_chipid(unsigned int *, unsigned int *,
+ unsigned int *, unsigned int *);
+void set_viu_probe_enable(void);
+void wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value);
+void power_set_dsp(unsigned int id, unsigned int powerflag);
+void init_dsp(unsigned int id,unsigned int addr,unsigned int cfg0);
+void set_boot_first_timeout(uint64_t arg0);
+int bl31_get_cornerinfo(uint8_t *outbuf, int size);
+int32_t set_boot_params(const keymaster_boot_params*);
+int32_t get_avbkey_from_fip(uint8_t *buf, uint32_t buflen);
+#endif
diff --git a/arch/arm/include/asm/arch-s4/board_id.h b/arch/arm/include/asm/arch-s4/board_id.h
new file mode 100644
index 0000000..6488771
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/board_id.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+unsigned int get_board_id(void);
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-s4/clk_measure_tab.h b/arch/arm/include/asm/arch-s4/clk_measure_tab.h
new file mode 100644
index 0000000..8f18c37
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/clk_measure_tab.h
@@ -0,0 +1,157 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _ARCH_MESON_S4_MEASURE_H_
+#define _ARCH_MESON_S4_MEASURE_H_
+
+static const char* clk_msr_table[] = {
+ [0] = "cts_sys_clk",
+ [1] = "cts_axi_clk",
+ [2] = "cts_rtc_clk",
+ [5] = "cts_mali_clk",
+ [6] = "sys_cpu_clk_div16",
+ [7] = "cts_ceca_clk",
+ [8] = "cts_cecb_clk",
+ [10] = "fclk_div5",
+ [11] = "mp0_clk_out",
+ [12] = "mp1_clk_out",
+ [13] = "mp2_clk_out",
+ [14] = "mp3_clk_out",
+ [15] = "mpll_clk_50m",
+ [18] = "mpll_clk_test_out",
+ [19] = "hifi_pll_clk",
+ [20] = "gp0_pll_clk",
+ [22] = "eth_mppll_50m_ckout",
+ [23] = "sys_pll_div16",
+ [24] = "ddr_dpll_pt_clk",
+ [30] = "mod_eth_phy_ref_clk",
+ [31] = "mod_eth_tx_clk",
+ [32] = "cts_eth_clk125Mhz",
+ [33] = "cts_eth_clk_rmii",
+ [34] = "co_clkin_to_mac",
+ [35] = "mod_eth_rx_clk_rmii",
+ [36] = "co_rx_clk",
+ [37] = "co_tx_clk",
+ [38] = "eth_phy_rxclk",
+ [39] = "eth_phy_plltxclk",
+ [40] = "ephy_test_clk",
+ [50] = "vid_pll_div_clk_out",
+ [51] = "cts_enci_clk",
+ [52] = "cts_encp_clk",
+ [53] = "cts_encl_clk",
+ [54] = "cts_vdac_clk",
+ [55] = "cts_cdac_clk_c",
+ [56] = "mod_tcon_clko",
+ [57] = "lcd_an_clk_ph2",
+ [58] = "lcd_an_clk_ph3",
+ [59] = "cts_hdmi_tx_pixel_clk",
+ [60] = "cts_vdin_meas_clk",
+ [61] = "cts_vpu_clk",
+ [62] = "cts_vpu_clkb",
+ [63] = "cts_vpu_clkb_tmp",
+ [64] = "cts_vpu_clkc",
+ [65] = "cts_vid_lock_clk",
+ [66] = "cts_vapbclk",
+ [67] = "cts_ge2d_clk",
+ [68] = "cts_hdcp22_esmclk",
+ [69] = "cts_hdcp22_skpclk",
+ [76] = "hdmitx_tmds_clk",
+ [77] = "cts_hdmitx_sys_clk",
+ [78] = "cts_hdmitx_fe_clk",
+ [79] = "cts_rama_clk",
+ [93] = "cts_vdec_clk",
+ [99] = "cts_hevcf_clk",
+ [100] = "cts_demod_core_clk",
+ [101] = "adc_extclk_in",
+ [103] = "adc_dpll_intclk",
+ [104] = "adc_dpll_clk_b3",
+ [105] = "s2_adc_clk",
+ [106] = "deskew_pll_clk_div32_out",
+ [110] = "cts_sc_clk(smartcard)",
+ [111] = "cts_sar_adc_clk",
+ [113] = "cts_sd_emmc_C_clk(nand)",
+ [114] = "cts_sd_emmc_B_clk",
+ [115] = "cts_sd_emmc_A_clk",
+ [116] = "gpio_msr_clk",
+ [118] = "cts_spicc_0_clk",
+ [121] = "cts_ts_clk(temp sensor)",
+ [130] = "audio_vad_clk",
+ [131] = "acodec_dac_clk_x128",
+ [132] = "audio_locker_in_clk",
+ [133] = "audio_locker_out_clk",
+ [134] = "audio_tdmout_c_sclk",
+ [135] = "audio_tdmout_b_sclk",
+ [136] = "audio_tdmout_a_sclk",
+ [137] = "audio_tdmin_lb_sclk",
+ [138] = "audio_tdmin_c_sclk",
+ [139] = "audio_tdmin_b_sclk",
+ [140] = "audio_tdmin_a_sclk",
+ [141] = "audio_resamplea_clk",
+ [142] = "audio_pdm_sysclk",
+ [143] = "audio_spdifout_b_mst_clk",
+ [144] = "audio_spdifout_mst_clk",
+ [145] = "audio_spdifin_mst_clk",
+ [146] = "audio_pdm_dclk",
+ [147] = "audio_resampleb_clk",
+ [160] = "pwm_j_clk",
+ [161] = "pwm_i_clk",
+ [162] = "pwm_h_clk",
+ [163] = "pwm_g_clk",
+ [164] = "pwm_f_clk",
+ [165] = "pwm_e_clk",
+ [166] = "pwm_d_clk",
+ [167] = "pwm_c_clk",
+ [168] = "pwm_b_clk",
+ [169] = "pwm_a_clk",
+ [176] = "rng_ring_0",
+ [177] = "rng_ring_1",
+ [178] = "rng_ring_2",
+ [179] = "rng_ring_3",
+ [180] = "dmc_osc_ring(LVT16)",
+ [181] = "gpu_osc_ring0(LVT16)",
+ [182] = "gpu_osc_ring1(ULVT16)",
+ [183] = "gpu_osc_ring2(SVT16)",
+ [184] = "vpu_osc_ring0(SVT24)",
+ [185] = "vpu_osc_ring1(LVT20)",
+ [186] = "vpu_osc_ring2(LVT16)",
+ [187] = "dos_osc_ring0(SVT24)",
+ [188] = "dos_osc_ring1(SVT16)",
+ [189] = "dos_osc_ring2(LVT16)",
+ [190] = "dos_osc_ring3(ULVT20)",
+ [192] = "axi_sram_osc_ring(SVT16)",
+ [193] = "demod_osc_ring0",
+ [194] = "demod_osc_ring1",
+ [195] = "sar_osc_ring",
+ [196] = "sys_cpu_osc_ring0",
+ [197] = "sys_cpu_osc_ring1",
+ [198] = "sys_cpu_osc_ring2",
+ [199] = "sys_cpu_osc_ring3",
+ [200] = "sys_cpu_osc_ring4",
+ [201] = "sys_cpu_osc_ring5",
+ [202] = "sys_cpu_osc_ring6",
+ [203] = "sys_cpu_osc_ring7",
+ [204] = "sys_cpu_osc_ring8",
+ [205] = "sys_cpu_osc_ring9",
+ [206] = "sys_cpu_osc_ring10",
+ [207] = "sys_cpu_osc_ring11",
+ [208] = "sys_cpu_osc_ring12",
+ [209] = "sys_cpu_osc_ring13",
+ [210] = "sys_cpu_osc_ring14",
+ [211] = "sys_cpu_osc_ring15",
+ [212] = "sys_cpu_osc_ring16",
+ [213] = "sys_cpu_osc_ring17",
+ [214] = "sys_cpu_osc_ring18",
+ [215] = "sys_cpu_osc_ring19",
+ [216] = "sys_cpu_osc_ring20",
+ [217] = "sys_cpu_osc_ring21",
+ [218] = "sys_cpu_osc_ring22",
+ [219] = "sys_cpu_osc_ring23",
+ [220] = "sys_cpu_osc_ring24",
+ [221] = "sys_cpu_osc_ring25",
+ [222] = "sys_cpu_osc_ring26",
+ [223] = "sys_cpu_osc_ring27",
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-s4/clock.h b/arch/arm/include/asm/arch-s4/clock.h
new file mode 100644
index 0000000..07170ff
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/clock.h
@@ -0,0 +1,207 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __S4_H
+#define __S4_H
+
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe000000
+// -----------------------------------------------
+#define S4_CLKCTRL_OSCIN_CTRL (0x0001 << 2)
+#define S4_CLKCTRL_RTC_BY_OSCIN_CTRL0 (0x0002 << 2)
+#define S4_CLKCTRL_RTC_BY_OSCIN_CTRL1 (0x0003 << 2)
+#define S4_CLKCTRL_RTC_CTRL (0x0004 << 2)
+#define S4_CLKCTRL_CHECK_CLK_RESULT (0x0005 << 2)
+#define S4_CLKCTRL_MBIST_ATSPEED_CTRL (0x0006 << 2)
+#define S4_CLKCTRL_LOCK_BIT_REG0 (0x0008 << 2)
+#define S4_CLKCTRL_LOCK_BIT_REG1 (0x0009 << 2)
+#define S4_CLKCTRL_LOCK_BIT_REG2 (0x000a << 2)
+#define S4_CLKCTRL_LOCK_BIT_REG3 (0x000b << 2)
+#define S4_CLKCTRL_PROT_BIT_REG0 (0x000c << 2)
+#define S4_CLKCTRL_PROT_BIT_REG1 (0x000d << 2)
+#define S4_CLKCTRL_PROT_BIT_REG2 (0x000e << 2)
+#define S4_CLKCTRL_PROT_BIT_REG3 (0x000f << 2)
+#define S4_CLKCTRL_SYS_CLK_CTRL0 (0x0010 << 2)
+#define S4_CLKCTRL_SYS_CLK_EN0_REG0 (0x0011 << 2)
+#define S4_CLKCTRL_SYS_CLK_EN0_REG1 (0x0012 << 2)
+#define S4_CLKCTRL_SYS_CLK_EN0_REG2 (0x0013 << 2)
+#define S4_CLKCTRL_SYS_CLK_EN0_REG3 (0x0014 << 2)
+#define S4_CLKCTRL_SYS_CLK_EN1_REG0 (0x0015 << 2)
+#define S4_CLKCTRL_SYS_CLK_EN1_REG1 (0x0016 << 2)
+#define S4_CLKCTRL_SYS_CLK_EN1_REG2 (0x0017 << 2)
+#define S4_CLKCTRL_SYS_CLK_EN1_REG3 (0x0018 << 2)
+#define S4_CLKCTRL_SYS_CLK_VPU_EN0 (0x0019 << 2)
+#define S4_CLKCTRL_SYS_CLK_VPU_EN1 (0x001a << 2)
+#define S4_CLKCTRL_AXI_CLK_CTRL0 (0x001b << 2)
+#define S4_CLKCTRL_TST_CTRL0 (0x0020 << 2)
+#define S4_CLKCTRL_TST_CTRL1 (0x0021 << 2)
+#define S4_CLKCTRL_CECA_CTRL0 (0x0022 << 2)
+#define S4_CLKCTRL_CECA_CTRL1 (0x0023 << 2)
+#define S4_CLKCTRL_CECB_CTRL0 (0x0024 << 2)
+#define S4_CLKCTRL_CECB_CTRL1 (0x0025 << 2)
+#define S4_CLKCTRL_SC_CLK_CTRL (0x0026 << 2)
+#define S4_CLKCTRL_DSPA_CLK_CTRL0 (0x0027 << 2)
+#define S4_CLKCTRL_DSPB_CLK_CTRL0 (0x0028 << 2)
+#define S4_CLKCTRL_RAMA_CLK_CTRL0 (0x0029 << 2)
+#define S4_CLKCTRL_CLK12_24_CTRL (0x002a << 2)
+#define S4_CLKCTRL_VID_CLK_CTRL (0x0030 << 2)
+#define S4_CLKCTRL_VID_CLK_CTRL2 (0x0031 << 2)
+#define S4_CLKCTRL_VID_CLK_DIV (0x0032 << 2)
+#define S4_CLKCTRL_VIID_CLK_DIV (0x0033 << 2)
+#define S4_CLKCTRL_VIID_CLK_CTRL (0x0034 << 2)
+#define S4_CLKCTRL_HDMI_CLK_CTRL (0x0038 << 2)
+#define S4_CLKCTRL_VID_PLL_CLK_DIV (0x0039 << 2)
+#define S4_CLKCTRL_VPU_CLK_CTRL (0x003a << 2)
+#define S4_CLKCTRL_VPU_CLKB_CTRL (0x003b << 2)
+#define S4_CLKCTRL_VPU_CLKC_CTRL (0x003c << 2)
+#define S4_CLKCTRL_VID_LOCK_CLK_CTRL (0x003d << 2)
+#define S4_CLKCTRL_VDIN_MEAS_CLK_CTRL (0x003e << 2)
+#define S4_CLKCTRL_VAPBCLK_CTRL (0x003f << 2)
+#define S4_CLKCTRL_HDCP22_CLK_CTRL (0x0040 << 2)
+#define S4_CLKCTRL_MIPIDSI_PHY_CLK_CTRL (0x0041 << 2)
+#define S4_CLKCTRL_CDAC_CLK_CTRL (0x0042 << 2)
+#define S4_CLKCTRL_MIPI_CSI_PHY_CLK_CTRL (0x0043 << 2)
+#define S4_CLKCTRL_CSI2_ADAPT_CLK_CTRL (0x0044 << 2)
+#define S4_CLKCTRL_VDEC_CLK_CTRL (0x0050 << 2)
+#define S4_CLKCTRL_VDEC2_CLK_CTRL (0x0051 << 2)
+#define S4_CLKCTRL_VDEC3_CLK_CTRL (0x0052 << 2)
+#define S4_CLKCTRL_VDEC4_CLK_CTRL (0x0053 << 2)
+#define S4_CLKCTRL_WAVE420L_CLK_CTRL (0x0054 << 2)
+#define S4_CLKCTRL_WAVE420L_CLK_CTRL2 (0x0055 << 2)
+#define S4_CLKCTRL_TS_CLK_CTRL (0x0056 << 2)
+#define S4_CLKCTRL_MALI_CLK_CTRL (0x0057 << 2)
+#define S4_CLKCTRL_VIPNANOQ_CLK_CTRL (0x0058 << 2)
+#define S4_CLKCTRL_ETH_CLK_CTRL (0x0059 << 2)
+#define S4_CLKCTRL_NAND_CLK_CTRL (0x005a << 2)
+#define S4_CLKCTRL_SD_EMMC_CLK_CTRL (0x005b << 2)
+#define S4_CLKCTRL_BT656_CLK_CTRL (0x005c << 2)
+#define S4_CLKCTRL_SPICC_CLK_CTRL (0x005d << 2)
+#define S4_CLKCTRL_GEN_CLK_CTRL (0x005e << 2)
+#define S4_CLKCTRL_SAR_CLK_CTRL (0x005f << 2)
+#define S4_CLKCTRL_PWM_CLK_AB_CTRL (0x0060 << 2)
+#define S4_CLKCTRL_PWM_CLK_CD_CTRL (0x0061 << 2)
+#define S4_CLKCTRL_PWM_CLK_EF_CTRL (0x0062 << 2)
+#define S4_CLKCTRL_PWM_CLK_GH_CTRL (0x0063 << 2)
+#define S4_CLKCTRL_PWM_CLK_IJ_CTRL (0x0064 << 2)
+#define S4_CLKCTRL_TIMESTAMP_CTRL (0x0100 << 2)
+#define S4_CLKCTRL_TIMESTAMP_CTRL1 (0x0101 << 2)
+#define S4_CLKCTRL_TIMESTAMP_CTRL2 (0x0103 << 2)
+#define S4_CLKCTRL_TIMESTAMP_RD0 (0x0104 << 2)
+#define S4_CLKCTRL_TIMESTAMP_RD1 (0x0105 << 2)
+#define S4_CLKCTRL_TIMEBASE_CTRL0 (0x0106 << 2)
+#define S4_CLKCTRL_TIMEBASE_CTRL1 (0x0107 << 2)
+#define S4_CLKCTRL_EFUSE_CPU_CFG01 (0x0120 << 2)
+#define S4_CLKCTRL_EFUSE_CPU_CFG2 (0x0121 << 2)
+#define S4_CLKCTRL_EFUSE_ENCP_CFG0 (0x0122 << 2)
+#define S4_CLKCTRL_EFUSE_MALI_CFG01 (0x0123 << 2)
+#define S4_CLKCTRL_EFUSE_HEVCB_CFG01 (0x0124 << 2)
+#define S4_CLKCTRL_EFUSE_HEVCB_CFG2 (0x0125 << 2)
+#define S4_CLKCTRL_EFUSE_LOCK (0x0126 << 2)
+//========================================================================
+
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe008000
+// -----------------------------------------------
+#define S4_ANACTRL_SYSPLL_CTRL0 ((0x00 << 2) + 0x8000)
+#define S4_ANACTRL_SYSPLL_CTRL1 ((0x01 << 2) + 0x8000)
+#define S4_ANACTRL_SYSPLL_CTRL2 ((0x02 << 2) + 0x8000)
+#define S4_ANACTRL_SYSPLL_CTRL3 ((0x03 << 2) + 0x8000)
+#define S4_ANACTRL_SYSPLL_CTRL4 ((0x04 << 2) + 0x8000)
+#define S4_ANACTRL_SYSPLL_CTRL5 ((0x05 << 2) + 0x8000)
+#define S4_ANACTRL_SYSPLL_CTRL6 ((0x06 << 2) + 0x8000)
+#define S4_ANACTRL_SYSPLL_STS ((0x07 << 2) + 0x8000)
+#define S4_ANACTRL_FIXPLL_CTRL0 ((0x10 << 2) + 0x8000)
+#define S4_ANACTRL_FIXPLL_CTRL1 ((0x11 << 2) + 0x8000)
+#define S4_ANACTRL_FIXPLL_CTRL2 ((0x12 << 2) + 0x8000)
+#define S4_ANACTRL_FIXPLL_CTRL3 ((0x13 << 2) + 0x8000)
+#define S4_ANACTRL_FIXPLL_CTRL4 ((0x14 << 2) + 0x8000)
+#define S4_ANACTRL_FIXPLL_CTRL5 ((0x15 << 2) + 0x8000)
+#define S4_ANACTRL_FIXPLL_CTRL6 ((0x16 << 2) + 0x8000)
+#define S4_ANACTRL_FIXPLL_STS ((0x17 << 2) + 0x8000)
+#define S4_ANACTRL_GP0PLL_CTRL0 ((0x20 << 2) + 0x8000)
+#define S4_ANACTRL_GP0PLL_CTRL1 ((0x21 << 2) + 0x8000)
+#define S4_ANACTRL_GP0PLL_CTRL2 ((0x22 << 2) + 0x8000)
+#define S4_ANACTRL_GP0PLL_CTRL3 ((0x23 << 2) + 0x8000)
+#define S4_ANACTRL_GP0PLL_CTRL4 ((0x24 << 2) + 0x8000)
+#define S4_ANACTRL_GP0PLL_CTRL5 ((0x25 << 2) + 0x8000)
+#define S4_ANACTRL_GP0PLL_CTRL6 ((0x26 << 2) + 0x8000)
+#define S4_ANACTRL_GP0PLL_STS ((0x27 << 2) + 0x8000)
+#define S4_ANACTRL_GP1PLL_CTRL0 ((0x30 << 2) + 0x8000)
+#define S4_ANACTRL_GP1PLL_CTRL1 ((0x31 << 2) + 0x8000)
+#define S4_ANACTRL_GP1PLL_CTRL2 ((0x32 << 2) + 0x8000)
+#define S4_ANACTRL_GP1PLL_CTRL3 ((0x33 << 2) + 0x8000)
+#define S4_ANACTRL_GP1PLL_CTRL4 ((0x34 << 2) + 0x8000)
+#define S4_ANACTRL_GP1PLL_CTRL5 ((0x35 << 2) + 0x8000)
+#define S4_ANACTRL_GP1PLL_CTRL6 ((0x36 << 2) + 0x8000)
+#define S4_ANACTRL_GP1PLL_STS ((0x37 << 2) + 0x8000)
+#define S4_ANACTRL_HIFIPLL_CTRL0 ((0x40 << 2) + 0x8000)
+#define S4_ANACTRL_HIFIPLL_CTRL1 ((0x41 << 2) + 0x8000)
+#define S4_ANACTRL_HIFIPLL_CTRL2 ((0x42 << 2) + 0x8000)
+#define S4_ANACTRL_HIFIPLL_CTRL3 ((0x43 << 2) + 0x8000)
+#define S4_ANACTRL_HIFIPLL_CTRL4 ((0x44 << 2) + 0x8000)
+#define S4_ANACTRL_HIFIPLL_CTRL5 ((0x45 << 2) + 0x8000)
+#define S4_ANACTRL_HIFIPLL_CTRL6 ((0x46 << 2) + 0x8000)
+#define S4_ANACTRL_HIFIPLL_STS ((0x47 << 2) + 0x8000)
+#define S4_ANACTRL_PCIEPLL_CTRL0 ((0x50 << 2) + 0x8000)
+#define S4_ANACTRL_PCIEPLL_CTRL1 ((0x51 << 2) + 0x8000)
+#define S4_ANACTRL_PCIEPLL_CTRL2 ((0x52 << 2) + 0x8000)
+#define S4_ANACTRL_PCIEPLL_CTRL3 ((0x53 << 2) + 0x8000)
+#define S4_ANACTRL_PCIEPLL_CTRL4 ((0x54 << 2) + 0x8000)
+#define S4_ANACTRL_PCIEPLL_CTRL5 ((0x55 << 2) + 0x8000)
+#define S4_ANACTRL_PCIEPLL_STS ((0x56 << 2) + 0x8000)
+#define S4_ANACTRL_MPLL_CTRL0 ((0x60 << 2) + 0x8000)
+#define S4_ANACTRL_MPLL_CTRL1 ((0x61 << 2) + 0x8000)
+#define S4_ANACTRL_MPLL_CTRL2 ((0x62 << 2) + 0x8000)
+#define S4_ANACTRL_MPLL_CTRL3 ((0x63 << 2) + 0x8000)
+#define S4_ANACTRL_MPLL_CTRL4 ((0x64 << 2) + 0x8000)
+#define S4_ANACTRL_MPLL_CTRL5 ((0x65 << 2) + 0x8000)
+#define S4_ANACTRL_MPLL_CTRL6 ((0x66 << 2) + 0x8000)
+#define S4_ANACTRL_MPLL_CTRL7 ((0x67 << 2) + 0x8000)
+#define S4_ANACTRL_MPLL_CTRL8 ((0x68 << 2) + 0x8000)
+#define S4_ANACTRL_MPLL_STS ((0x69 << 2) + 0x8000)
+#define S4_ANACTRL_HDMIPLL_CTRL0 ((0x70 << 2) + 0x8000)
+#define S4_ANACTRL_HDMIPLL_CTRL1 ((0x71 << 2) + 0x8000)
+#define S4_ANACTRL_HDMIPLL_CTRL2 ((0x72 << 2) + 0x8000)
+#define S4_ANACTRL_HDMIPLL_CTRL3 ((0x73 << 2) + 0x8000)
+#define S4_ANACTRL_HDMIPLL_CTRL4 ((0x74 << 2) + 0x8000)
+#define S4_ANACTRL_HDMIPLL_CTRL5 ((0x75 << 2) + 0x8000)
+#define S4_ANACTRL_HDMIPLL_CTRL6 ((0x76 << 2) + 0x8000)
+#define S4_ANACTRL_HDMIPLL_STS ((0x77 << 2) + 0x8000)
+#define S4_ANACTRL_HDMIPLL_VLOCK ((0x79 << 2) + 0x8000)
+#define S4_ANACTRL_HDMIPHY_CTRL0 ((0x80 << 2) + 0x8000)
+#define S4_ANACTRL_HDMIPHY_CTRL1 ((0x81 << 2) + 0x8000)
+#define S4_ANACTRL_HDMIPHY_CTRL2 ((0x82 << 2) + 0x8000)
+#define S4_ANACTRL_HDMIPHY_CTRL3 ((0x83 << 2) + 0x8000)
+#define S4_ANACTRL_HDMIPHY_CTRL4 ((0x84 << 2) + 0x8000)
+#define S4_ANACTRL_HDMIPHY_CTRL5 ((0x85 << 2) + 0x8000)
+#define S4_ANACTRL_HDMIPHY_STS ((0x86 << 2) + 0x8000)
+#define S4_ANACTRL_MIPICSI_CTRL0 ((0x90 << 2) + 0x8000)
+#define S4_ANACTRL_MIPICSI_CTRL1 ((0x91 << 2) + 0x8000)
+#define S4_ANACTRL_MIPICSI_CTRL2 ((0x92 << 2) + 0x8000)
+#define S4_ANACTRL_MIPICSI_CTRL3 ((0x93 << 2) + 0x8000)
+#define S4_ANACTRL_MIPICSI_CTRL4 ((0x94 << 2) + 0x8000)
+#define S4_ANACTRL_MIPICSI_CTRL5 ((0x95 << 2) + 0x8000)
+#define S4_ANACTRL_MIPIDSI_CTRL0 ((0xa0 << 2) + 0x8000)
+#define S4_ANACTRL_MIPIDSI_CTRL1 ((0xa1 << 2) + 0x8000)
+#define S4_ANACTRL_MIPIDSI_CTRL2 ((0xa2 << 2) + 0x8000)
+#define S4_ANACTRL_MIPIDSI_STS ((0xa3 << 2) + 0x8000)
+#define S4_ANACTRL_VDAC_CTRL0 ((0xb0 << 2) + 0x8000)
+#define S4_ANACTRL_VDAC_CTRL1 ((0xb1 << 2) + 0x8000)
+#define S4_ANACTRL_POR_CTRL ((0xb6 << 2) + 0x8000)
+#define S4_ANACTRL_LOCK_BIT ((0xb8 << 2) + 0x8000)
+#define S4_ANACTRL_PROT_BIT ((0xb9 << 2) + 0x8000)
+//========================================================================
+
+/*
+ * CPU clok register offset
+ * APB_BASE: APB1_BASE_ADDR = 0xfe007400
+ */
+
+#include <dt-bindings/clock/s4-clkc.h>
+#define NR_CLKS (CLKID_END_BASE)
+
+#endif /* __S4_H */
diff --git a/arch/arm/include/asm/arch-s4/core.h b/arch/arm/include/asm/arch-s4/core.h
new file mode 100644
index 0000000..97fd220
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/core.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __CORE_H__
+#define __CORE_H__
+
+int get_core_mpidr(unsigned int cpuid);
+int get_core_idx(unsigned int mpidr);
+int get_core_max(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-s4/cpu.h b/arch/arm/include/asm/arch-s4/cpu.h
new file mode 100644
index 0000000..2acbd3f
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/cpu.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+/* #include <config.h> */
+/* #include <asm/plat-cpu.h> */
+/* #include <asm/arch/ddr.h> */
+
+#if 0
+#define CONFIG_AML_MESON 1
+#define CONFIG_AML_MESON_GX 1
+#define CONFIG_AML_MESON_G12A 1
+#endif
+
+/*enable viu probe*/
+#if 0
+#define CONFIG_CMD_VIU_PROBE 1
+#endif
+
+/* for uboot envrionment use */
+#define CONFIG_DDR_SIZE 2048
+
+/* dram */
+#define PHYS_SDRAM_1_BASE 0x00000000UL
+#define PHYS_SDRAM_1_SIZE 0x80000000UL
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1_BASE
+
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1_BASE + CONFIG_SYS_TEXT_BASE)
+
+/* console/print buffer */
+#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
+
+/* use "hush" command parser */
+#if 0
+#define CONFIG_SYS_HUSH_PARSER
+#endif
+
+#if 0
+#define CONFIG_DTB_MEM_ADDR 0x1000000
+#endif
+
+#if 0
+#define CONFIG_AML_CUSTOMER_ID (0)
+#endif
+
+#define AML_CUSTOMER_ID (0)
+
+#define CONFIG_SILENT_CONSOLE
+//#define CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC
+#define CONFIG_SILENT_U_BOOT_ONLY
+
+/* 2018.03.19 new compress solution, only support BL33 LZ4 compress */
+#define CONFIG_AML_BL33_COMPRESS_ENABLE 1
+
+/* 2018.03.19 G12A only support v3 format for normal & secure boot */
+#define CONFIG_AML_SECURE_BOOT_V3 1
+
+#define NR_CPUS 4
+
+#define CPU_ID_REG SYSCTRL_SEC_STATUS_REG0
+#define PACKAGE_ID_MASK 0xFF
+
+/*C1 SoC secure boot solution default not support AES algorithm*/
+//#define CONFIG_AML_CRYPTO_AES 1
+
+
+/*Flag for enable AES key generate to EFUSE pattern, with this flag only
+AES key will be generated to EFUSE pattern, it can be used for use case
+like the AES key not ready when secure boot enabled for the first time.
+*/
+//#define CONFIG_AML_EFUSE_GEN_AES_ONLY 1
+
+#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-s4/cpu_config.h b/arch/arm/include/asm/arch-s4/cpu_config.h
new file mode 100644
index 0000000..72453c5
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/cpu_config.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _BOOT_ROM_CONFIG_H_
+#define _BOOT_ROM_CONFIG_H_
+
+/***********************************************************
+ * The following constants are GXBB definition
+ **********************************************************/
+#define ROMBOOT_START 0xD9040000
+#define ROM_SIZE (64*1024)
+#define ROMBOOT_END (ROMBOOT_START+ROM_SIZE)
+
+/***********************************************************
+ * AHB-SRAM Total Size 80KB, layout shown as below
+ *
+ * ROMCODE use the top 32KB
+ *
+ * [ 128] 0xD901_3F80 - 0xD901_3FFF Reserved
+ * [ 128] 0xD901_3F00 - 0xD901_3F7F CPUs Boot Entry
+ * [ 256] 0xD901_3E00 - 0xD901_3EFF Debug Info
+ * [ 512] 0xD901_3C00 - 0xD901_3DFF eFuse mirror
+ * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3)
+ * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) *
+ * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) *
+ * [ 26K] 0xD900_C800 - 0xD901_2FFF BL1 Stack, BSS
+ * [ 1K] 0xD900_C400 - 0xD900_C7FF NAND, USB Buffer
+ * [ 1K] 0xD900_C000 - 0xD900_C3FF Reserved
+ *
+ **********************************************************/
+#define RAM_START 0xD9000000
+#define RAM_SIZE (80 * 1024)
+#define BL1_RAM_START (RAM_START + 0xC000)
+#define BL1_RAM_SIZE (32 * 1024)
+#define BL1_RAM_END (BL1_RAM_START + BL1_RAM_SIZE)
+#define BSS_START (BL1_RAM_START + (2 * 1024))
+#define BSS_SIZE (18 * 1024)
+#define _STACK_END (BSS_START + BSS_SIZE + 8*1024)
+#define BL1_EFUSE_MIRROR (BL1_RAM_END - 1024)
+#define P_SHARED_EFUSE_MIRROR (volatile uint32_t *)(BL1_EFUSE_MIRROR)
+#define BL1_DEBUG_BUFFER (BL1_RAM_END - 512)
+#define CPU_BOOT_ENTRY (BL1_DEBUG_BUFFER + 256)
+#define P_SHARED_DEBUG_BUFF (volatile uint32_t *)(BL1_DEBUG_BUFFER)
+#define BL1_SEC_MBX (BL1_RAM_END - 2*1024)
+#define BL1_NAND_BUFF (BL1_RAM_START + 1024)
+#define BL1_USB_BUFF (BL1_NAND_BUFF)
+
+#define MEMORY_LOC RAM_START
+
+#define SRAM_DEBUG_BUFF_SIZE 256
+
+/* BL2 SPL size */
+#define BL2_SIZE (166 * 1024)
+
+//for signature test
+//#define CONFIG_AML_SIG_TEST_BUILD
+
+/* Software SHA2 */
+#define CONFIG_SHA2_SW
+
+/* Hardware SHA2 */
+#define CONFIG_SHA2_HW
+#define SHA2_HW_UPDATE_API
+
+/* Keep timer config in conf.h */
+#define CONFIG_TIMER
+
+/* Bootrom debug info */
+#define CONFIG_DEBUG_INFO
+
+/* Mincrypt RSA library */
+//#define CONFIG_MINCRYPT
+
+/* PolarSSL RSA library */
+#define CONFIG_POLARSSL_RSA
+
+#ifdef CONFIG_POLARSSL_RSA
+#ifndef CONFIG_MALLOC
+#define CONFIG_MALLOC
+#endif /* ! CONFIG_MALLOC */
+#endif /* CONFIG_POLARSSL_RSA */
+
+#endif /* _BOOT_ROM_CONFIG_H_ */
diff --git a/arch/arm/include/asm/arch-s4/cpu_reset.h b/arch/arm/include/asm/arch-s4/cpu_reset.h
new file mode 100644
index 0000000..46f9abf
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/cpu_reset.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _BOOT_ROM_WATCHDOG_H
+#define _BOOT_ROM_WATCHDOG_H
+#include <asm/arch/secure_apb.h>
+
+void reset_system(void);
+
+/* uboot reset interface */
+void reset_cpu(unsigned long flag);
+
+#endif /* _BOOT_ROM_WATCHDOG_H */
diff --git a/arch/arm/include/asm/arch-s4/cpu_sdio.h b/arch/arm/include/asm/arch-s4/cpu_sdio.h
new file mode 100644
index 0000000..46f366a
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/cpu_sdio.h
@@ -0,0 +1,239 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __CPU_SDIO_H__
+#define __CPU_SDIO_H__
+
+#define SD_EMMC_BASE_A 0xFFE03000
+#define SD_EMMC_BASE_B 0xFFE05000
+#define SD_EMMC_BASE_C 0xFFE07000
+
+#define SDIO_PORT_A 0
+#define SDIO_PORT_B 1
+#define SDIO_PORT_C 2
+
+struct sd_emmc_global_regs {
+ volatile uint32_t gclock; // 0x00
+ volatile uint32_t gdelay; // 0x04
+ volatile uint32_t gdelay1; //0x08
+ volatile uint32_t gadjust; // 0x0c
+ volatile uint32_t gcalout; // 0x10
+ volatile uint32_t reserved_14[11]; // 0x14~0x3c
+ volatile uint32_t gstart; // 0x40
+ volatile uint32_t gcfg; // 0x44
+ volatile uint32_t gstatus; // 0x48
+ volatile uint32_t girq_en; // 0x4c
+ volatile uint32_t gcmd_cfg; // 0x50
+ volatile uint32_t gcmd_arg; // 0x54
+ volatile uint32_t gcmd_dat; // 0x58
+ volatile uint32_t gcmd_rsp0; // 0x5c
+ volatile uint32_t gcmd_rsp1; // 0x60
+ volatile uint32_t gcmd_rsp2; // 0x64
+ volatile uint32_t gcmd_rsp3; // 0x68
+ volatile uint32_t reserved_6c; // 0x6c
+ volatile uint32_t gcurr_cfg; // 0x70
+ volatile uint32_t gcurr_arg; // 0x74
+ volatile uint32_t gcurr_dat; // 0x78
+ volatile uint32_t gcurr_rsp; // 0x7c
+ volatile uint32_t gnext_cfg; // 0x80
+ volatile uint32_t gnext_arg; // 0x84
+ volatile uint32_t gnext_dat; // 0x88
+ volatile uint32_t gnext_rsp; // 0x8c
+ volatile uint32_t grxd; // 0x90
+ volatile uint32_t gtxd; // 0x94
+ volatile uint32_t reserved_98[90]; // 0x98~0x1fc
+ volatile uint32_t gdesc[128]; // 0x200
+ volatile uint32_t gping[128]; // 0x400
+ volatile uint32_t gpong[128]; // 0x800
+};
+
+union sd_emmc_setup {
+ uint32_t d32;
+ struct {
+ unsigned bw:3;
+ unsigned fast:1;
+ unsigned par:3;
+ unsigned hcs:1;
+ unsigned sd:1;
+ unsigned sdhc:1;
+ unsigned type:6;
+ unsigned rca:16;
+ } b;
+};
+
+struct sd_emmc_desc_info{
+ uint32_t cmd_info;
+ uint32_t cmd_arg;
+ uint32_t data_addr;
+ uint32_t resp_addr;
+};
+
+struct cmd_cfg{
+ uint32_t length:9;
+ uint32_t block_mode:1;
+ uint32_t r1b:1;
+ uint32_t end_of_chain:1;
+ uint32_t timeout:4;
+ uint32_t no_resp:1;
+ uint32_t no_cmd:1;
+ uint32_t data_io:1;
+ uint32_t data_wr:1;
+ uint32_t resp_nocrc:1;
+ uint32_t resp_128:1;
+ uint32_t resp_num:1;
+ uint32_t data_num:1;
+ uint32_t cmd_index:6;
+ uint32_t error:1;
+ uint32_t owner:1;
+};
+
+struct sd_emmc_status{
+ uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire, for multiple block read, the CRC errors are ORed together.*/
+ uint32_t txd_err:1; /*[8] TX data CRC error, for multiple block write, any one of blocks CRC error. */
+ uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. The owner bit is ¡°0¡±, set cfg_ignore_owner to ignore this error.*/
+ uint32_t resp_err:1; /*[10] Response CRC error.*/
+ uint32_t resp_timeout:1; /*[11] No response received before time limit. The timeout limit is set by cfg_resp_timeout.*/
+ uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. The timeout limit is set by descriptor itself.*/
+ /* Consider the multiple block read/write, set the proper timeout limits.*/
+ uint32_t end_of_chain:1; /*[13] End of Chain IRQ, Normal IRQ. */
+ uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ, Normal IRQ, the descriptor chain execution keeps going on.*/
+ uint32_t irq_sdio:1; /*[15] SDIO device uses DAT[1] to request IRQ. */
+ uint32_t dat_i:8; /*[23:16] Input data signals. */
+ uint32_t cmd_i:1; /*[24] nput response signal. */
+ uint32_t ds:1; /*[25] Input data strobe. */
+ uint32_t bus_fsm:4; /*[29:26] BUS fsm */
+ uint32_t desc_wr_rdy:1; /*[30] Descriptor write back process is done and it is ready for CPU to read.*/
+ uint32_t core_rdy:1; /*[31] desc_busy or sd_emmc_irq or bus_fsm is not idle.*/
+};//__attribute__((__may_alias__));
+
+
+struct sd_emmc_clock{
+ uint32_t div:6; /*[5:0] Clock divider. Frequency = clock source/cfg_div, Maximum divider 63. */
+ /*Clock off: cfg_div==0, the clock is disabled */
+ /*Divider bypass: cfg_div==1, clock source is used as core clock without divider. */
+ uint32_t src:2; /*[7:6] Clock source, 0: Crystal 24MHz, 1: Fix PLL, 850MHz*/
+ /* 2: MPLL, <637MHz, used for 400MHz exactly. 3: different PLL */
+ uint32_t core_phase:2; /*[9:8] Core clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/
+ uint32_t tx_phase:2; /*[11:10] TX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/
+ uint32_t rx_phase:2; /*[13:12] RX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/
+ uint32_t reserved14:2;
+ uint32_t tx_delay:6; /*[21:16] TX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/
+ uint32_t rx_delay:6; /*[27:22] RX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/
+ uint32_t always_on:1; /*[28] 1: Keep clock always on. 0: Clock on/off controlled by activities. */
+ /*Any APB3 access or descriptor execution will keep clock on.*/
+ uint32_t irq_sdio_sleep:1; /*[29] 1: enable IRQ sdio when in sleep mode. */
+ uint32_t irq_sdio_sleep_ds:1;/*[30] 1:enable ds as irq*/
+ uint32_t reserved26:1;
+};
+
+struct sd_emmc_delay{
+ uint32_t dat0:6; /*[3:0] Data 0 delay line. */
+ uint32_t dat1:6; /*[7:4] Data 1 delay line. */
+ uint32_t dat2:6; /*[11:8] Data 2 delay line. */
+ uint32_t dat3:6; /*[15:12] Data 3 delay line. */
+ uint32_t dat4:6; /*[19:16] Data 4 delay line. */
+ uint32_t spare:2;
+};
+
+struct sd_emmc_delay1{
+ uint32_t dat5:6; /*[23:20] Data 5 delay line. */
+ uint32_t dat6:6; /*[27:24] Data 6 delay line. */
+ uint32_t dat7:6; /*[31:28] Data 7 delay line. */
+ uint32_t dat8:6; /*[31:28] Data 7 delay line. */
+ uint32_t dat9:6; /*[31:28] Data 7 delay line. */
+ uint32_t spare:2;
+};
+
+struct sd_emmc_adjust{
+ uint32_t cmd_delay:4; /*[3:0] Command delay line. */
+ uint32_t ds_delay:4; /*[7:4] DS delay line. */
+ uint32_t cali_sel:4; /*[11:8] Select one signal to be tested.*/
+ /*Signals are labeled from 0 to 9 the same as delay lines. */
+ uint32_t cali_enable:1; /*[12] Enable calibration. */
+ uint32_t adj_enable:1; /*[13] Adjust interface timing by resampling the input signals. */
+ uint32_t cali_rise:1; /*[14] 1: test the rising edge. 0: test the falling edge. */
+ uint32_t ds_enable:1; /*[15] Sampling the DAT based on DS in HS400 mode*/
+ uint32_t adj_delay:6; /*[21:16] Resample the input signals when clock index==adj_delay. */
+ uint32_t adj_auto:1; /*[22] Use cali_dut first falling edge to adjust the timing */
+ /*set cali_enable to 1 to use this function*/
+ uint32_t reserved23:9;
+};
+
+
+struct sd_emmc_calout{
+ uint32_t cali_idx:6; /*[5:0] Calibration reading. The event happens at this index. */
+ uint32_t reserved6:1;
+ uint32_t cali_vld:1; /*[7] The reading is valid. */
+ uint32_t cali_setup:8; /*[15:8] Copied from BASE+0x8 [15:8] include cali_sel, cali_enable, adj_enable, cali_rise. */
+ uint32_t reserved16:16;
+};
+
+
+struct sd_emmc_start{
+ uint32_t init:1; /*[0] 1: Read descriptor from internal SRAM, limited to 32 descriptors. */
+ /* 0: Read descriptor from external DDR */
+ uint32_t busy:1; /*[1] 1: Start command chain execution process. 0: Stop */
+ uint32_t addr:30; /*[31:2] Descriptor address, the last 2 bits are 0, 4 bytes aligned. */
+ /* When internal SRAM is used, the valid address range is from 0x200~0x3ff */
+ /* When external DDR is used, the valid address is anywhere in DDR, the length of chain is unlimited.*/
+};//__attribute__((__may_alias__));
+
+
+struct sd_emmc_config{
+ uint32_t bus_width:2; /*[1:0] 0: 1 bit, 1: 4 bits, 2: 8 bits, 3: 2 bits (not supported)*/
+ uint32_t ddr:1; /*[2] 1: DDR mode, 0: SDR mode */
+ uint32_t dc_ugt:1; /*[3] 1: DDR access urgent, 0: DDR access normal. */
+ uint32_t bl_len:4; /*[7:4] Block length 2^cfg_bl_len, because internal buffer size is limited to 512 bytes, the cfg_bl_len <=9. */
+ uint32_t resp_timeout:4; /*[11:8] Wait response till 2^cfg_resp_timeout core clock cycles. Maximum 32768 core cycles. */
+ uint32_t rc_cc:4; /*[15:12] Wait response-command, command-command gap before next command, 2^cfg_rc_cc core clock cycles. */
+ uint32_t out_fall:1; /*[16] DDR mode only. The command and TXD start from rising edge. Set 1 to start from falling edge. */
+ uint32_t blk_gap_ip:1; /*[17] 1: Enable SDIO data block gap interrupt period. 0: Disabled.*/
+ uint32_t spare:1; /*[18] Spare, ??? need check*/
+ uint32_t ignore_owner:1; /*[19] Use this descriptor even if its owner bit is ¡°0¡±.*/
+ uint32_t chk_ds:1; /*[20] Check data strobe in HS400.*/
+ uint32_t cmd_low:1; /*[21] Hold CMD as output Low, eMMC boot mode.*/
+ uint32_t stop_clk:1; /*[22] 1: stop clock. 0: normal clock.*/
+ /*In normal mode, the clock is automatically on/off during reading mode to back off reading in case of*/
+ /*DDR slow response, stop clock is used in voltage switch.*/
+ uint32_t auto_clk:1; /*[23] 1: when BUS is idle and no descriptor is available, turn off clock, to save power.*/
+ /* 0: core clock is always on.*/
+ uint32_t txd_add_err:1; /*[24] TXD add error test*/
+ /*Test feature, should not be used in normal condition.*/
+ /*It will inverted the first CRC bits of the 3rd block.*/
+ /*Block index starts from 0, 1, 2, ¡*/
+ uint32_t txd_retry:1; /*[25] When TXD CRC error, host sends the block again.*/
+ /*The total number of retries of one descriptor is limited to 15, */
+ /*after 15 retries, the TXD_err is set to high.*/
+ uint32_t revd:8; /*[31:26] reved*/
+};//__attribute__((__may_alias__));
+
+
+struct sd_emmc_irq_en{
+ uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire.*/
+ uint32_t txd_err:1; /*[8] TX data CRC error. */
+ uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. */
+ uint32_t resp_err:1; /*[10] Response CRC error.*/
+ uint32_t resp_timeout:1; /*[11] No response received before time limit. */
+ uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. */
+ uint32_t end_of_chain:1; /*[13] End of Chain IRQ. */
+ uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ. */
+ uint32_t irq_sdio:1; /*[15] Enable sdio interrupt. */
+ uint32_t revd:16; /*[31:16] reved*/
+};
+
+struct sd_emmc_data_info{
+ uint32_t cnt:10; /*[9:0] Rxd words received from BUS. Txd words received from DDR.*/
+ uint32_t blk:9; /*[24:16] Rxd Blocks received from BUS. Txd blocks received from DDR.*/
+ uint32_t revd:30; /*[31:17] Reved. */
+};
+
+
+struct sd_emmc_card_info{
+ uint32_t txd_cnt:10; /*[9:0] Txd BUS cycle counter. */
+ uint32_t txd_blk:9; /*[24:16] Txd BUS block counter.*/
+ uint32_t revd:30; /*[31:17] Reved. */
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-s4/ddr.h b/arch/arm/include/asm/arch-s4/ddr.h
new file mode 100644
index 0000000..ad27855
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/ddr.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <io.h>
+#include <stdint.h>
+#include <asm/arch/ddr_define.h>
+
+/* io defines */
+//#define wr_reg(addr, data) (*((volatile uint32_t *)addr))=(uint32_t)(uint64_t)(data)
+//#define rd_reg(addr) (*((volatile uint32_t *)(addr)))
+#define wr_reg(addr, data) writel(data, addr)
+#define rd_reg(addr) readl(addr)
+/*clear [mask] 0 bits in [addr], set these 0 bits with [value] corresponding bits*/
+#define modify_reg(addr, value, mask) wr_reg(addr, ((rd_reg(addr) & (mask)) | (value)))
+#define wait_set(addr, loc) do{}while(0 == (rd_reg(addr) & (1<<loc)));
+#define wait_clr(addr, loc) do{}while(1 == (rd_reg(addr) & (1<<loc)));
+#define wait_equal(addr, data) do{}while(data != (rd_reg(addr)));
+
+/* function defines */
+unsigned int ddr_init(void);
+unsigned int ddr_init_pll(void);
+unsigned int ddr_init_dmc(void);
+unsigned int ddr_init_pctl(void);
+unsigned int hot_boot(void);
+void ddr_print_info(void);
+void ddr_test(void);
+void ddr_pre_init(void);
+void ddr_debug(void);
+
+/* pctl status */
+#define UPCTL_STAT_MASK (7)
+#define UPCTL_STAT_INIT (0)
+#define UPCTL_STAT_CONFIG (1)
+#define UPCTL_STAT_ACCESS (3)
+#define UPCTL_STAT_LOW_POWER (5)
+
+/* pctl cmds */
+#define UPCTL_CMD_INIT (0)
+#define UPCTL_CMD_CONFIG (1)
+#define UPCTL_CMD_GO (2)
+#define UPCTL_CMD_SLEEP (3)
+#define UPCTL_CMD_WAKEUP (4)
+
+/* PUB PIR setting */
+#define PUB_PIR_INIT (1<<0)
+#define PUB_PIR_ZCAL (1<<1)
+#define PUB_PIR_CA (1<<2)
+#define PUB_PIR_PLLINIT (1<<4)
+#define PUB_PIR_DCAL (1<<5)
+#define PUB_PIR_PHYRST (1<<6)
+#define PUB_PIR_DRAMRST (1<<7)
+#define PUB_PIR_DRAMINIT (1<<8)
+#define PUB_PIR_WL (1<<9)
+#define PUB_PIR_QSGATE (1<<10)
+#define PUB_PIR_WLADJ (1<<11)
+#define PUB_PIR_RDDSKW (1<<12)
+#define PUB_PIR_WRDSKW (1<<13)
+#define PUB_PIR_RDEYE (1<<14)
+#define PUB_PIR_WREYE (1<<15)
+#define PUB_PIR_ICPC (1<<16)
+#define PUB_PIR_PLLBYP (1<<17)
+#define PUB_PIR_CTLDINIT (1<<18)
+#define PUB_PIR_RDIMMINIT (1<<19)
+#define PUB_PIR_CLRSR (1<<27)
+#define PUB_PIR_LOCKBYP (1<<28)
+#define PUB_PIR_DCALBYP (1<<29)
+#define PUB_PIR_ZCALBYP (1<<30)
+#define PUB_PIR_INITBYP (1<<31)
+
+/* PHY initialize register (PIR) */
+#define DDR_PIR ((PUB_PIR_ZCAL) |\
+ (PUB_PIR_PLLINIT) |\
+ (PUB_PIR_DCAL) |\
+ (PUB_PIR_PHYRST) |\
+ (PUB_PIR_DRAMRST) |\
+ (PUB_PIR_DRAMINIT) |\
+ (PUB_PIR_WL) |\
+ (PUB_PIR_QSGATE) |\
+ (PUB_PIR_WLADJ) |\
+ (PUB_PIR_RDDSKW) |\
+ (PUB_PIR_WRDSKW) |\
+ (PUB_PIR_RDEYE) |\
+ (PUB_PIR_WREYE) \
+ )
+
+/* PHY general status register (PGSR0) */
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+#define DDR_PGSR0_CHECK() ((rd_reg(DDR0_PUB_PGSR0) != 0xC0000fff) && \
+ (rd_reg(DDR0_PUB_PGSR0) != 0x80000fff))
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define DDR_PGSR0_CHECK()
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define DDR_PGSR0_CHECK()
+#endif
+
+/* other regs */
+#define SCRATCH0 0xC1107D3C
diff --git a/arch/arm/include/asm/arch-s4/ddr_define.h b/arch/arm/include/asm/arch-s4/ddr_define.h
new file mode 100644
index 0000000..28e6173
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/ddr_define.h
@@ -0,0 +1,577 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/* board id */
+#define CONFIG_BOARD_ID_MASK 0xFF
+#define CONFIG_FW_INFO_MASK 0xFFFFFFFF
+
+#define RESULT_OK 0x0
+#define RESULT_FAIL 0xFF
+#define RESULT_PLL_LOCK_FAIL 0x0F
+#define RESULT_USB_BOOT_NEVER 0xF0
+
+#define DDR_HDTCTRL_ENABLE_AMLOGIC_DDR4_PHY_VREF_CORRECTION 0x7
+#define DDR_HDTCTRL_SHOW_DDR3_LPDDR3_TRAINING_MARGIN 0x9
+#define DDR_HDTCTRL_SHOW_DDR3_LPDDR3_TRAINING_MARGIN_WRITE_DQ 0x00210005
+#define DDR_HDTCTRL_SHOW_DDR3_LPDDR3_TRAINING_MARGIN_WRITE_DQM 0x00290005
+#define DDR_HDTCTRL_SHOW_DDR3_LPDDR3_TRAINING_MARGIN_READ_DQ 0x003a0005
+
+#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_READ_START_1 0x00200004
+#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_READ_START_2 0x001e0004
+#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_READ_VREF 0x0014001f
+#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_READ_VREF_END 0x00610000
+
+#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_WRITE_START_1 0x001c0004
+#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_WRITE_START_2 0x00230004
+#define DDR_HDTCTRL_SHOW_LPDDR4_TRAINING_TDQS2DQ 0x00dd0002
+//#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_WRITE_VREF 0x0014001f
+//#define DDR_HDTCTRL_SHOW_DDR4_TRAINING_EYE_DATA_WRITE_VREF_END 0x00610000
+#define DMC_PSTATE_MAX 4
+
+#define CONFIG_CHIP_TYPE_DRAM 0x1F
+#define CONFIG_CHIP_TYPE_PSRAM 0x2F
+#define CONFIG_DDR_TYPE_DDR3 0
+#define CONFIG_DDR_TYPE_DDR4 1
+#define CONFIG_DDR_TYPE_LPDDR4 2
+#define CONFIG_DDR_TYPE_LPDDR3 3
+#define CONFIG_DDR_TYPE_LPDDR2 4
+//#define CONFIG_DDR_TYPE_LPDDR4X 5
+#define CONFIG_DDR_TYPE_AUTO 0xf
+#define CONFIG_DDR_TYPE_AUTO_LIMIT CONFIG_DDR_TYPE_DDR4
+
+/* lpddr3 related define */
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE0 0
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE1 1
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE2 2
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE3 3
+
+#define LPDDR_DIE_ROW_COL_R13_C9 0
+#define LPDDR_DIE_ROW_COL_R14_C9 1
+#define LPDDR_DIE_ROW_COL_R14_C10 2
+#define LPDDR_DIE_ROW_COL_R13_C10 3
+#define LPDDR_DIE_ROW_COL_R14_C11 4
+
+#if 0
+/* ddr channel defines */
+#define CONFIG_DDR0_16BIT 1
+#define CONFIG_DDR0_RANK0 2
+#define CONFIG_DDR0_RANK01 3
+#define CONFIG_DDR0_16BIT_2 4
+#define CONFIG_DDR_CHL_AUTO 0xF
+#define CONFIG_DDR0_16BIT_CH0 0x1
+#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7
+#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8
+#define ENABLE_SKIP_1D_MEM_LOAD 0x0
+#define ENABLE_SKIP_1D_MEM_TRAINING 0x1
+#define ENABLE_SKIP_2D_MEM_LOAD 0x2
+#define ENABLE_SKIP_2D_MEM_TRAINING 0x3
+
+#define PHY_IMEM_STEP_1D 0x1
+#define PHY_IMEM_STEP_2D 0x2
+
+#endif
+#define VREF_SOC 0x1
+#define VREF_DRAM 0x2
+
+
+#define CFG_DDR_BASE_ADDR 0X0
+#define CFG_DDR_START_OFFSET 0X01000000 //SKIP 16MB
+
+/* ddr type identifier */
+#define CONFIG_DDR_TIMMING_LPDDR2 0x02
+#define CONFIG_DDR_TIMMING_LPDDR3 0x03
+#define CONFIG_DDR_TIMMING_DDR3_7 0x07
+#define CONFIG_DDR_TIMMING_DDR3_9 0x09
+#define CONFIG_DDR_TIMMING_DDR3_11 0x0B
+#define CONFIG_DDR_TIMMING_DDR3_12 0x0C
+#define CONFIG_DDR_TIMMING_DDR3_13 0x0D
+#define CONFIG_DDR_TIMMING_DDR3_14 0x0E
+
+#define CONFIG_DDR_TIMMING_DDR4_1600 0x0F
+#define CONFIG_DDR_TIMMING_DDR4_1866 0x10
+#define CONFIG_DDR_TIMMING_DDR4_2133 0x11
+#define CONFIG_DDR_TIMMING_DDR4_2400 0x12
+#define CONFIG_DDR_TIMMING_DDR4_2666 0x13
+#define CONFIG_DDR_TIMMING_DDR4_3200 0x14
+
+#define CONFIG_DDR_FUNC_TEST (1<<0)
+
+#define CONFIG_DDR_INIT_RETRY_TOTAL (10)
+#define CONFIG_DDR_PCTL_RETRY_TOTAL (100)
+
+#define DDR_USE_1_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK0) || \
+ (chl_set == CONFIG_DDR0_16BIT))
+#define DDR_USE_2_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK01) || \
+ (chl_set == CONFIG_DDR0_16BIT_2))
+
+#ifndef CONFIG_LPDDR3_CA_TRAINING_CA0
+#define CONFIG_LPDDR3_CA_TRAINING_CA0 CONFIG_LPDDR3_CA_TRAINING_USE_LANE0
+#endif
+#ifndef CONFIG_LPDDR3_CA_TRAINING_CA1
+#define CONFIG_LPDDR3_CA_TRAINING_CA1 CONFIG_LPDDR3_CA_TRAINING_USE_LANE1
+#endif
+
+/* DMC_DDR_CTRL defines */
+#define DDR_DDR4_ENABLE (1<<22)
+#define DDR_RANK1_ENABLE (1<<21)
+#define DDR_DDR4_BG_ENABLE (1<<20)
+#define DDR_16BIT_ENABLE (1<<16)
+
+#define DDR_RANK1_SIZE_CTRL (3)
+#define DDR_RANK0_SIZE_CTRL (0)
+
+/* ddr functions */
+#define DDR_FUNC_D2PLL (1<<0)
+#define DDR_FUNC_LP (1<<1)
+#define DDR_FUNC_ZQ_PD (1<<2)
+#define DDR_FUNC_EXT_VREF (1<<3)
+#define DDR_FUNC_DDR4_TIMING_TEST (1<<4)
+#define DDR_FUNC_DDR_PLL_BYPASS (1<<5)
+#define DDR_FUNC_RDBI (1<<6)
+#define DDR_FUNC_LPDDR3_CA (1<<7)
+#define DDR_FUNC_PRINT_WINDOW (1<<8)
+#define DDR_FUNC_FULL_TEST (1<<10)
+#define DDR_FUNC_NONSEC_SCRAMBLE (1<<11)
+#define DDR_FUNC_LPDDR3_CA_CA0_BIT0 (1<<20)
+#define DDR_FUNC_LPDDR3_CA_CA0_BIT1 (1<<21)
+#define DDR_FUNC_LPDDR3_CA_CA1_BIT0 (1<<22)
+#define DDR_FUNC_LPDDR3_CA_CA1_BIT1 (1<<23)
+#define DDR_FUNC_LPDDR3_CA_CA0_OFFSET (20)
+#define DDR_FUNC_LPDDR3_CA_CA1_OFFSET (22)
+#define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP (1<<25)
+#define DDR_FUNC_CONFIG_DDR_DVFS_FUNCTION (1<<28)
+#define DDR_FUNC_CONFIG_DFE_FUNCTION (1<<29)
+#define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1<<30)
+#define DDR_FUNC_SCRAMBLE (1<<31)
+
+
+/* dwc imem/dmem */
+#define DWC_MEM_LOAD_ADDR 0xFFFE0000
+#define DWC_IRAM_ADDR (0x50000)
+#define DWC_IRAM_SIZE (0x8000) /* 32K */
+#define DWC_DRAM_ADDR (0x54000)
+#define DWC_DRAM_SIZE (0x4000) /* 16K */
+
+/* dwc apb regs */
+#define UctWriteProtShadow 0xd0004
+#define UctWriteOnlyShadow 0xd0032
+#define UctWriteProt 0xd0031
+#define UctDatWriteOnlyShadow 0xd0034
+
+/* pctl status */
+#define UPCTL_STAT_MASK (7)
+#define UPCTL_STAT_INIT (0)
+#define UPCTL_STAT_CONFIG (1)
+#define UPCTL_STAT_ACCESS (3)
+#define UPCTL_STAT_LOW_POWER (5)
+
+/* pctl cmds */
+#define UPCTL_CMD_INIT (0)
+#define UPCTL_CMD_CONFIG (1)
+#define UPCTL_CMD_GO (2)
+#define UPCTL_CMD_SLEEP (3)
+#define UPCTL_CMD_WAKEUP (4)
+
+
+/* name id defined in firmware header */
+#define DDR_NAME_ID_AML_FW 0x304c4d41 //AML0
+#define DDR_NAME_ID_PIEI 0x61656165 //eaea
+#define DDR_NAME_ID_DDR3 0x33333364 //d333
+#define DDR_NAME_ID_DDR4 0x34343464 //d444
+#define DDR_NAME_ID_DDR4_2D 0x32323464 //d422
+#define DDR_NAME_ID_LPDDR3 0x33336C64 //dl33
+#define DDR_NAME_ID_LPDDR4 0x34346C64 //dl44
+#define DDR_NAME_ID_LPDDR4_2D 0x30346C64 //dl42
+#define DDR_NAME_ID_DIAGNOSE1 0x31676464 //ddg1
+#define DDR_NAME_ID_DIAGNOSE2 0x32676464 //ddg2
+/* PIEI */
+#define DDR_PIEI_START_FLAG 0xfeed //eaea
+
+/* dram cfg magic */
+#define DRAM_CFG_MAGIC 0x2e676663
+
+/* flow control */
+#define DDR_FIRMWARE_VERSION_1 0x00201709
+#define FW_LOAD_STEP_AML_FW 0xF
+#define FW_LOAD_STEP_PIEI 0
+#define FW_LOAD_STEP_1D 1
+#define FW_LOAD_STEP_2D 2
+#define FW_LOAD_STEP_DIAG1 3
+#define FW_LOAD_STEP_DIAG2 4
+
+/* basic defines */
+#define AML_AC_PINMUX_G0_TOTAL 6
+#define AML_AC_PINMUX_G1_TOTAL 29
+#define AML_DFI_PINMUX_TOTAL 26
+#define AML_DQ_PINMUX_TOTAL 36
+#define AML_DQ_BYTES_TOTAL 4
+
+
+/* d2pll defines */
+#define D2PLL_ENABLE 1
+#define DDR_STICKY_MAGIC_NUMBER 0x20180000
+#define DDR_CHIP_ID 0x30
+#define DDR_STICKY_OVERRIDE_CONFIG_MESSAGE_CMD 0x1 //override config
+#define DDR_STICKY_SPECIAL_FUNCTION_CMD 0x2 //special test such as shift some bdlr or parameter or interleave test
+#define DDR_INIT_CONFIG_STICKY_MESSAGE_SRAM_ADDRESS 0x00040000
+#define DDR_INIT_CONFIG_GLOBAL_MESSAGE_SRAM_ADDRESS 0x00050000
+
+
+/* debug function*/
+
+/* ddr configs */
+#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+
+#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+#define DDR_RFC_TYPE_LPDDR4_6Gbx1 12
+#define DDR_RFC_TYPE_LPDDR4_8Gbx1 13
+
+#define DDR_ENABLE_FINE_TUNE_FLAG_AC_DELAY (1<<0)
+#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQS (1<<1)
+#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS (1<<2)
+#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ (1<<3)
+#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ (1<<4)
+
+#define IMPEDENCE_120P3_240P2_480P1 1
+#define IMPEDENCE_120P6_1 2
+#define IMPEDENCE_120P3_240P2_480P1_ODT 3
+
+#define IMPEDENCE_AML_SOC_DATA 1
+#define IMPEDENCE_AML_SOC_AC 2
+
+
+#define VREF_DDR4_SDRAM_DAC 1
+#define VREF_LPDDR4_SDRAM_DAC 2
+#define VREF_LPDDR4X_SDRAM_DAC 3
+#define VREF_SOC_AML_DAC_LPDDR4 4
+#define VREF_SOC_AML_DAC_LPDDR4X 5
+#define VREF_SOC_AML_DAC_DDR3 6
+#define VREF_SOC_AML_DAC_DDR4 7
+
+#define DDR_PHY_BLOCK_ANIB 0x0
+#define DDR_PHY_BLOCK_DBYTE 0x1
+#define DDR_PHY_BLOCK_MASTER 0x2
+#define DDR_PHY_BLOCK_ACSM 0x4
+#define DDR_PHY_BLOCK_UPTCL_MEMORY 0x5
+#define DDR_PHY_BLOCK_PPGC 0x7
+#define DDR_PHY_BLOCK_INITENG 0x9
+#define DDR_PHY_BLOCK_PUB 0xC
+#define DDR_PHY_BLOCK_APBONLY 0xD
+
+/* others */ /* useless? */
+
+/* bist */
+#define CONFIG_DDR_CODE_INCLUDE_LPDDR3 0
+#define CONFIG_DDR_CODE_INCLUDE_DDR4 1
+#define CONFIG_DEBUG_INCLUDE_D2PLL 1
+#define CONFIG_DEBUG_DDR_BIST_TEST_WINDOWS 1
+#define CONFIG_DEBUG_DDR_BIST_ONLY_COMPARE_ONE_LANE 1
+#define CONFIG_DEBUG_DDR_BIST_BYTE_EXTRA_PATTERN 1
+#define CONFIG_DEBUG_DDR_BIST_NO_USE_FSM_INIT_VALUE 1
+#define CONFIG_DEBUG_DDR_BIST_NO_USE_FSM_INIT_VALUE_USE_LINEAR 0
+#define CONFIG_DEBUG_DDR_BIST_NO_USE_FSM_INIT_VALUE_USE_FAST_LINEAR 1
+#define CONFIG_DEBUG_DDR_BIST_USE_OLD_METHOD_AGAIN 0
+#define CONFIG_DDR_DMC_DDR_TEST 0
+#define CONFIG_DDR_CPU_DDR_TEST 0
+#define CONFIG_BIST_USE_THRESHOLD 0
+#define CONFIG_DEBUG_DDR_BIST_TEST_2D_EYE 0
+
+#define CONFIG_DEBUG_DDR_BIST_TEST_DATA
+//#define CONFIG_DEBUG_DDR_BIST_TEST_ADD
+
+#define DDR_BIST_LANE_DATA0 0
+#define DDR_BIST_LANE_DATA1 1
+#define DDR_BIST_LANE_DATA2 2
+#define DDR_BIST_LANE_DATA3 3
+#define DDR_BIST_LANE_AC 4
+
+#define DDR_BIST_PATTERN_WALK_0 0
+#define DDR_BIST_PATTERN_WALK_1 1
+#define DDR_BIST_PATTERN_WALK_RANDOM 2
+#define DDR_BIST_PATTERN_WALK_PRE 3
+
+/* diagnose function defines */
+#define CONFIG_DIAGNOSE_DISABLE 0x0
+#define CONFIG_DIAGNOSE_1D 0x1
+#define CONFIG_DIAGNOSE_2D 0x2
+#define CONFIG_DIAGNOSE_1D_2D 0x3
+
+#define DDR_RFC_TYPE_LPDDR4_6Gbx1 12
+#define DDR_RFC_TYPE_LPDDR4_8Gbx1 13
+
+
+#define CONFIG_BOARD_ID_DISABLE 0
+#define CONFIG_BOARD_ID_MASK 0xFF
+
+#define CONFIG_DDR_TYPE_DDR3 0
+#define CONFIG_DDR_TYPE_DDR4 1
+#define CONFIG_DDR_TYPE_LPDDR4 2
+#define CONFIG_DDR_TYPE_LPDDR3 3
+#define CONFIG_DDR_TYPE_LPDDR2 4
+#define CONFIG_DDR_TYPE_LPDDR4X 5
+
+#define CONFIG_DDR0_16BIT_CH0 1
+#define CONFIG_DDR0_16BIT_RANK01_CH0 4
+#define CONFIG_DDR0_32BIT_RANK0_CH0 2
+#define CONFIG_DDR0_32BIT_RANK01_CH01 3
+#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 5
+#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 6
+#define CONFIG_DDR0_32BIT_RANK01_CH0 7
+#define CONFIG_DDR0_32BIT_RANK0_CH01 8
+#define CONFIG_DDR0_32BIT_RANK0_16BIT_RANK1_LOW_CH0 0x9
+#define CONFIG_DDR0_32BIT_RANK0_16BIT_RANK1_HIGH_CH0 0xa
+#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0_MODE2 0xB
+#define CONFIG_DDR0_32BIT_RANK0_16BIT_RANK1_LOW_CH0_MODE2 0xC
+
+#define CONFIG_DISABLE_D32_D63 0xf0
+#define CONFIG_DISABLE_D16_D31 0xfc
+
+#define CONFIG_DDR0_SIZE_0MB 0
+#define CONFIG_DDR0_SIZE_128MB 128
+#define CONFIG_DDR0_SIZE_256MB 256
+#define CONFIG_DDR0_SIZE_512MB 512
+#define CONFIG_DDR0_SIZE_768MB 768
+#define CONFIG_DDR0_SIZE_1024MB 1024
+#define CONFIG_DDR0_SIZE_1536MB 1536
+#define CONFIG_DDR0_SIZE_2048MB 2048
+#define CONFIG_DDR0_SIZE_3072MB 3072
+#define CONFIG_DDR0_SIZE_4096MB 4096
+#define CONFIG_DDR0_SIZE_AUTO_SIZE 0xffff
+#define CONFIG_DDR1_SIZE_0MB 0
+#define CONFIG_DDR1_SIZE_128MB 128
+#define CONFIG_DDR1_SIZE_256MB 256
+#define CONFIG_DDR1_SIZE_512MB 512
+#define CONFIG_DDR1_SIZE_768MB 768
+#define CONFIG_DDR1_SIZE_1024MB 1024
+#define CONFIG_DDR1_SIZE_1536MB 1536
+#define CONFIG_DDR1_SIZE_2048MB 2048
+#define CONFIG_DDR1_SIZE_3072MB 3072
+#define CONFIG_DDR1_SIZE_4096MB 4096
+#define CONFIG_DDR1_SIZE_AUTO_SIZE 0xffff
+
+#define CONFIG_DRAM_MODE_X4 1
+#define CONFIG_DRAM_MODE_X8 1
+#define CONFIG_DRAM_MODE_X16 0
+
+#define CONFIG_USE_DDR_1T_MODE 0
+#define CONFIG_USE_DDR_2T_MODE 1
+
+#define eLOG_CHL_0 0
+#define eLOG_CHL_1 1
+#define eLOG_CHL_2 2
+#define eLOG_CHL_3 3
+#define eLOG_CHL_4 4
+#define eLOG_CHL_5 5
+#define eLOG_CHL_6 6
+#define eLOG_CHL_7 7
+
+#define LOG_LEVEL_BASIC (1<<eLOG_CHL_0)
+#define LOG_LEVEL_FULL (1<<eLOG_CHL_0)|(1<<eLOG_CHL_1)|(1<<eLOG_CHL_2)|(1<<eLOG_CHL_3)|(1<<eLOG_CHL_4)|(1<<eLOG_CHL_5)|(1<<eLOG_CHL_6)
+#define LOG_LEVEL_DEBUG (1<<eLOG_CHL_0)|(1<<eLOG_CHL_1)|(1<<eLOG_CHL_2)|(1<<eLOG_CHL_3)|(1<<eLOG_CHL_4)|(1<<eLOG_CHL_5)|(1<<eLOG_CHL_6)|(1<<eLOG_CHL_7)
+
+#define DDR_WRITE_READ_DBI_DISABLE 0
+#define DDR_READ_DBI_ENABLE 1
+#define DDR_WRITE_DBI_ENABLE 2
+#define DDR_WRITE_READ_DBI_ENABLE 3
+
+#define DDR_PLL_SSC_DISABLE 0
+#define DDR_PLL_SSC_3000PPM 0x3000
+#define DDR_PLL_SSC_5000PPM 0x3001
+#define DDR_PLL_SSC_6000PPM 0x3002
+#define DDR_PLL_SSC_8000PPM 0x3003
+#define DDR_PLL_SSC_9000PPM 0x3004
+
+#define DDR_DMC_REMAP_DDR3_32BIT {\
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25 ),\
+ [1] = ( 11| 0 << 5 | 0 << 10 | 12 << 15 | 16 << 20 | 17 << 25 ),\
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),\
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),\
+ [4] = ( 30| 13 << 5 | 14 << 10 | 15 << 15 | 0 << 20 | 0 << 25 ),\
+ }
+
+#define DDR_DMC_REMAP_DDR4_32BIT {\
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),\
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),\
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),\
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),\
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 31 << 25 ),\
+ }
+
+
+#define DDR_DMC_REMAP_DDR3_16BIT {\
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),\
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),\
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),\
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),\
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),\
+ }
+
+#define DDR_DMC_REMAP_DDR4_16BIT {\
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),\
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),\
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),\
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),\
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 30 << 25 ),\
+ }
+#define DDR_DMC_REMAP_LPDDR4_16BIT {\
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),\
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),\
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),\
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),\
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),\
+ }
+
+#define DDR_DMC_REMAP_LPDDR4_32BIT {\
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25 ),\
+ [1] = ( 11| 0 << 5 | 0 << 10 | 12 << 15 | 14 << 20 | 15 << 25 ),\
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),\
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),\
+ [4] = ( 0 | 13 << 5 | 16 << 10 | 20 << 15 | 0 << 20 | 0 << 25 ),\
+ }
+ //cs0 write bit0-1,cs0 read bit4-5,cs1 write bit 8-9,cs1 read bit 12-13
+#define DDR_DRAM_ODT_DISABLE 0
+#define DDR_DRAM_ODT_W_CS0_ODT0 0x1
+#define DDR_DRAM_ODT_W_CS0_ODT0_CS1_ODT1 0x201
+#define DDR_DRAM_ODT_W_CS0_ODT1_CS1_ODT0 0x102
+#define DDR_DRAM_ODT_W_CS0_ODT01_CS1_ODT01 0x303
+#define DDR_DRAM_ODT_W_CS0_ODT0_CS1_ODT1__R_CS0_ODT1_CS1_ODT0 0x1221
+#define DDR_DRAM_ODT_W_CS0_ODT1_CS1_ODT0__R_CS0_ODT1_CS1_ODT0 0x1122
+#define DDR_DRAM_ODT_W_CS0_ODT01_CS1_ODT01__R_CS0_ODT1_CS1_ODT0 0x1323
+#define DDR_DRAM_ODT_R_CS0_ODT1_CS1_ODT0 0x1020
+
+#define DDR_SOC_AC_DRV_0_OHM 0
+#define DDR_SOC_AC_DRV_120_OHM 120
+#define DDR_SOC_AC_DRV_60_OHM 60
+#define DDR_SOC_AC_DRV_40_OHM 40
+#define DDR_SOC_AC_DRV_30_OHM 30
+#define DDR_SOC_AC_DRV_24_OHM 24
+#define DDR_SOC_AC_DRV_20_OHM 20
+
+#define DDR_SOC_DATA_DRV_ODT_0_OHM 0
+#define DDR_SOC_DATA_DRV_ODT_240_OHM 240
+#define DDR_SOC_DATA_DRV_ODT_120_OHM 120
+#define DDR_SOC_DATA_DRV_ODT_80_OHM 80
+#define DDR_SOC_DATA_DRV_ODT_60_OHM 60
+#define DDR_SOC_DATA_DRV_ODT_48_OHM 48
+#define DDR_SOC_DATA_DRV_ODT_40_OHM 40
+#define DDR_SOC_DATA_DRV_ODT_34_OHM 34
+
+#define DDR_DRAM_DDR3_DRV_34_OHM 34
+#define DDR_DRAM_DDR3_DRV_40_OHM 40
+#define DDR_DRAM_DDR4_DRV_34_OHM 34
+#define DDR_DRAM_DDR4_DRV_48_OHM 48
+#define DDR_DRAM_LPDDR3_DRV_34_OHM 34
+#define DDR_DRAM_LPDDR3_DRV_40_OHM 40
+#define DDR_DRAM_LPDDR3_DRV_48_OHM 48
+#define DDR_DRAM_LPDDR4_DRV_40_OHM 40
+#define DDR_DRAM_LPDDR4_DRV_48_OHM 48
+#define DDR_DRAM_LPDDR4_DRV_60_OHM 60
+#define DDR_DRAM_LPDDR4_DRV_80_OHM 80
+#define DDR_DRAM_LPDDR4_DRV_120_OHM 120
+#define DDR_DRAM_LPDDR4_DRV_240_OHM 240
+
+#define DDR_DRAM_DDR3_ODT_0_OHM 0
+#define DDR_DRAM_DDR3_ODT_120_OHM 120
+#define DDR_DRAM_DDR3_ODT_60_OHM 60
+#define DDR_DRAM_DDR3_ODT_40_OHM 40
+#define DDR_DRAM_LPDDR3_ODT_0_OHM 0
+#define DDR_DRAM_LPDDR3_ODT_240_OHM 240
+#define DDR_DRAM_LPDDR3_ODT_120_OHM 120
+#define DDR_DRAM_LPDDR3_ODT_60_OHM 60
+#define DDR_DRAM_LPDDR4_ODT_0_OHM 0
+#define DDR_DRAM_LPDDR4_ODT_240_OHM 240
+#define DDR_DRAM_LPDDR4_ODT_120_OHM 120
+#define DDR_DRAM_LPDDR4_ODT_80_OHM 80
+#define DDR_DRAM_LPDDR4_ODT_60_OHM 60
+#define DDR_DRAM_LPDDR4_ODT_48_OHM 48
+#define DDR_DRAM_LPDDR4_ODT_40_OHM 40
+#define DDR_DRAM_DDR4_ODT_0_OHM 0
+#define DDR_DRAM_DDR4_ODT_34_OHM 34
+#define DDR_DRAM_DDR4_ODT_40_OHM 40
+#define DDR_DRAM_DDR4_ODT_48_OHM 48
+#define DDR_DRAM_DDR4_ODT_60_OHM 60
+#define DDR_DRAM_DDR4_ODT_80_OHM 80
+#define DDR_DRAM_DDR4_ODT_120_OHM 120
+#define DDR_DRAM_DDR4_ODT_240_OHM 240
+
+#define DDR_DRAM_DDR_WR_ODT_0_OHM 0
+#define DDR_DRAM_DDR3_WR_ODT_0_OHM 0
+#define DDR_DRAM_DDR3_WR_ODT_120_OHM 120
+#define DDR_DRAM_DDR3_WR_ODT_60_OHM 60
+#define DDR_DRAM_DDR4_WR_ODT_0_OHM 0
+#define DDR_DRAM_DDR4_WR_ODT_240_OHM 240
+#define DDR_DRAM_DDR4_WR_ODT_120_OHM 120
+#define DDR_DRAM_DDR4_WR_ODT_80_OHM 80
+
+#define DDR_DRAM_DDR_AC_ODT_0_OHM 0
+#define DDR_DRAM_LPDDR4_AC_ODT_0_OHM 0
+#define DDR_DRAM_LPDDR4_AC_ODT_240_OHM 240
+#define DDR_DRAM_LPDDR4_AC_ODT_120_OHM 120
+#define DDR_DRAM_LPDDR4_AC_ODT_80_OHM 80
+#define DDR_DRAM_LPDDR4_AC_ODT_60_OHM 60
+#define DDR_DRAM_LPDDR4_AC_ODT_48_OHM 48
+#define DDR_DRAM_LPDDR4_AC_ODT_40_OHM 40
+
+#define DDR_DRAM_LPDDR4_OUTPUT_2_5_VDDQ 0
+#define DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ 1
+
+#define DDR_SOC_READ_DQS_GATE_MODE_WINDOW_MODE_0_DDR3 1
+#define DDR_SOC_READ_DQS_GATE_MODE_WINDOW_MODE_1_DDR4 2
+#define DDR_SOC_READ_DQS_GATE_MODE_WINDOW_MODE_2_DDR4 3
+#define DDR_SOC_READ_DQS_GATE_MODE_WINDOW_MODE_3_LPDDR4 4
+
+#define DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR3 5
+#define DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR4 6
+#define DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_LPDDR4 7
+#define DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_3_LPDDR4 8
+
+#define DDR_SOC_READ_DQS_GATE_MODE_WIDE_MODE_RPULL_0_DDR3 9
+#define DDR_SOC_READ_DQS_GATE_MODE_WIDE_MODE_RPULL_1_LPDDR4 10
+
+#if 0
+#define DDR_SOC_READ_DQS_GATE_MODE_RPULL_WIDE_WINDOW 1
+
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_WINDOW_MODE_0 2
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_WINDOW_MODE_1 3
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_WINDOW_MODE_2 4
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_WINDOW_MODE_3 5
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_EDGE_MODE_0 6
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_EDGE_MODE_1 7
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_EDGE_MODE_2 8
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR3_EDGE_MODE_3 9
+
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_WINDOW_MODE_0 10
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_WINDOW_MODE_1 11
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_WINDOW_MODE_2 12
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_WINDOW_MODE_3 13
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_EDGE_MODE_0 14
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_EDGE_MODE_1 15
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_EDGE_MODE_2 16
+#define DDR_SOC_READ_DQS_GATE_MODE_DDR4_EDGE_MODE_3 17
+
+#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_WINDOW_MODE_0 18
+#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_WINDOW_MODE_1 19
+#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_WINDOW_MODE_2 20
+#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_WINDOW_MODE_3 21
+#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_EDGE_MODE_0 22
+#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_EDGE_MODE_1 23
+#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_EDGE_MODE_2 24
+#define DDR_SOC_READ_DQS_GATE_MODE_LPDDR4_EDGE_MODE_3 25
+#endif
diff --git a/arch/arm/include/asm/arch-s4/dev_parameter.h b/arch/arm/include/asm/arch-s4/dev_parameter.h
new file mode 100644
index 0000000..f7590e3
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/dev_parameter.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __DEV_PARAMETER_H__
+#define __DEV_PARAMETER_H__
+
+/* gpio/pinmux/pwm */
+typedef struct _register_ops {
+ /* register address*/
+ uint32_t reg;
+ /* value to set*/
+ uint32_t value;
+ /* bitmask of the value setting */
+ uint32_t mask;
+ /* for HW stable consideration */
+ uint16_t udelay;
+ /* setting stage and etc. */
+ uint8_t flag;
+ /* reserved. */
+ uint8_t rsv_0;
+}__attribute__ ((packed)) register_ops_t;
+
+#define MAX_REG_OPS_ENTRIES (32)
+typedef struct pin_pwm_parameter {
+ register_ops_t pin_pwm[MAX_REG_OPS_ENTRIES];
+}__attribute__ ((packed)) pin_pwm_parameter_t;
+
+typedef struct common_storage_parameter {
+ /* version info of the common storage parameter */
+ uint32_t version;
+ /* fip sector counts */
+ uint32_t device_fip_container_size;
+ /* fip copies */
+ uint32_t device_fip_container_copies;
+ /*ddrfip size*/
+ uint32_t ddr_fip_container_size;
+
+ uint8_t reserved[16];
+}__attribute__ ((packed)) common_storage_parameter_t;
+
+
+typedef struct nand_parameter {
+ /* version info of the common storage parameter */
+ uint32_t version;
+ /* the same as bbt_start_block, tell the bbt size for scanning mechanism */
+ uint32_t bbt_pages;
+ /* for bl2 stage, it can quickly generate the small part of the fromt bbt table. 20 for start block of bbt scanning */
+ uint32_t bbt_start_block;
+ /* 1: bl2 and fip is stored separately in different area 0: bl2 and fip is stored in first 1024 pages. 1 for slc nand flash. */
+ uint32_t discrete_mode;
+ /* set the setup_data the same as rom code reading from page0. see union cmdinfo in nand.h. */
+ union {
+ uint32_t nand_setup_data;
+ uint32_t spi_nand_page_size;
+ } setup_data;
+ union {
+ uint32_t nand_reserved;
+ uint32_t spi_nand_planes_per_lun;
+ } reserved;
+ /* Block counts of the reserved area */
+ uint32_t reserved_area_blk_cnt;
+ /* Page number of each block */
+ uint32_t page_per_block;
+ /* Page list source of the bl2 NAND driver. 0: calculated in source code; 1: get from byte32~63 */
+ uint8_t use_param_page_list;
+ /* List of page addresses, 8-bit per entry */
+ uint8_t page_list[32];
+ uint8_t reserved1[63];
+}__attribute__ ((packed)) nand_parameter_t;
+
+
+typedef struct storage_parameter {
+ /* for all the storage media */
+ common_storage_parameter_t common;
+ /* for NAND and SPINAND */
+ nand_parameter_t nand;
+}__attribute__ ((packed)) storage_parameter_t;
+
+#endif //__AML_TIMING_H_
diff --git a/arch/arm/include/asm/arch-s4/efuse.h b/arch/arm/include/asm/arch-s4/efuse.h
new file mode 100644
index 0000000..4a68e88
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/efuse.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __EFUSE_H
+#define __EFUSE_H
+
+#include <config.h>
+#include <common.h>
+
+/* efuse HAL_API arg */
+struct efuse_hal_api_arg {
+ unsigned int cmd; /* R/W */
+ unsigned int offset;
+ unsigned int size;
+ unsigned long buffer_phy;
+ unsigned long retcnt_phy;
+};
+
+
+#define EFUSE_BYTES 512 /* (EFUSE_BITS/8) */
+
+#define EFUSE_HAL_API_READ 0
+#define EFUSE_HAL_API_WRITE 1
+#define EFUSE_HAL_API_WRITE_PATTERN 2
+#define EFUSE_HAL_API_USER_MAX 3
+
+#define EFUSE_USER_MASK (0x1 << 16)
+#define EFUSE_THERMAL_MASK (0x1 << 17)
+#define EFUSE_THERMAL_VERFLAG_MASK (0x1 << 18)
+#define EFUSE_ENCRYPT_MASK (0x1 << 19)
+
+//#define ASSIST_HW_REV 0x1f53
+
+int efuse_read_usr(char *buf, size_t count, loff_t *ppos);
+int efuse_write_usr(char *buf, size_t count, loff_t *ppos);
+uint32_t efuse_get_max(void);
+ssize_t efuse_read(char *buf, size_t count, loff_t *ppos);
+ssize_t efuse_write(const char *buf, size_t count, loff_t *ppos);
+
+int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg);
+int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg);
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-s4/eth_setup.h b/arch/arm/include/asm/arch-s4/eth_setup.h
new file mode 100644
index 0000000..6e643f6
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/eth_setup.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/io.h>
+
+/*
+ *board configuration interface.
+ * */
+struct eth_clock_conf{
+ int enable;
+ int clock_50MHZ_phase;
+ //add ... as you need.
+};
+
+struct eth_board_socket{
+char *name ;
+int (*eth_clock_configure)(struct eth_clock_conf);
+int (*eth_pinmux_setup)(void);
+int (*eth_hw_reset)(void);
+
+};
+
+
+
+/*
+ *clock define part
+ */
+
+#define ETH_BASE (0xff3f0000)
+#define ETH_PLL_CNTL CBUS_REG_ADDR(0x2050)
+ /* Ethernet ctrl */
+#define ETH_PLL_CNTL_DIVEN (1<<0)
+#define ETH_PLL_CNTL_MACSPD (1<<1)
+#define ETH_PLL_CNTL_DATEND (1<<2)
+#define ETH_PLL_CNTL_DESEND (1<<3)
+
+
+/*
+ please refer following doc for detail
+ @AppNote-M3-ClockTrees.docx
+
+ select clk: -> CBUS_REG(0x1076)
+
+ 7-sys_pll_div2
+ 6-vid2_pll_clk
+ 5-vid_pll_clk
+ 4-aud_pll_clk
+ 3-ddr_pll_clk
+ 2-misc_pll_clk
+ 1-sys_pll_clk
+ 0-XTAL
+
+ clk_freq:800MHz
+ output_clk:50MHz
+ aways,maybe changed for others?
+*/
+
+#define ETH_CLKSRC_XTAL (0)
+#define ETH_CLKSRC_SYS_PLL_CLK (1)
+#define ETH_CLKSRC_MISC_PLL_CLK (2)
+#define ETH_CLKSRC_DDR_PLL_CLK (3)
+#define ETH_CLKSRC_AUD_PLL_CLK (
+#define ETH_CLKSRC_VID_PLL_CLK (5)
+#define ETH_CLKSRC_VID2_PLL_CLK (6)
+#define ETH_CLKSRC_SYS_PLL_DIV2_CLK (7)
+#define CLK_1M (1000000)
+
+typedef union eth_aml_reg0 {
+ /** raw register data */
+ unsigned int d32;
+ /** register bits */
+ struct {
+ unsigned phy_intf_sel:3;
+ unsigned rx_clk_rmii_invert:1;
+ unsigned rgmii_tx_clk_src:1;
+ unsigned rgmii_tx_clk_phase:2;
+ unsigned rgmii_tx_clk_ratio:3;
+ unsigned phy_ref_clk_enable:1;
+ unsigned clk_rmii_i_invert:1;
+ unsigned clk_en:1;
+ unsigned adj_enable:1;
+ unsigned adj_setup:1;
+ unsigned adj_delay:5;
+ unsigned adj_skew:5;
+ unsigned cali_start:1;
+ unsigned cali_rise:1;
+ unsigned cali_sel:3;
+ unsigned rgmii_rx_reuse:1;
+ unsigned eth_urgent:1;
+ } b;
+} eth_aml_reg0_t;
+
+#define ETH_VALIDE_CLKSRC(clk,out_clk) ((clk%out_clk)==0)
+
+int eth_clk_set(int selectclk,unsigned long clk_freq,unsigned long out_clk);
+
diff --git a/arch/arm/include/asm/arch-s4/gpio.h b/arch/arm/include/asm/arch-s4/gpio.h
new file mode 100644
index 0000000..2467368
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/gpio.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_ARCH_MESON_GPIO_H
+#define __ASM_ARCH_MESON_GPIO_H
+
+
+#endif /* __ASM_ARCH_MESON_GPIO_H */
diff --git a/arch/arm/include/asm/arch-s4/i2c.h b/arch/arm/include/asm/arch-s4/i2c.h
new file mode 100644
index 0000000..a93a09d
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/i2c.h
@@ -0,0 +1,280 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AML_MACH_I2C__
+#define __AML_MACH_I2C__
+
+#include <asm/io.h>
+#include <asm/arch/secure_apb.h>
+
+/**
+ * struct i2c_msg - an I2C transaction segment beginning with START
+ * @addr: Slave address, either seven or ten bits. When this is a ten
+ * bit address, I2C_M_TEN must be set in @flags and the adapter
+ * must support I2C_FUNC_10BIT_ADDR.
+ * @flags: I2C_M_RD is handled by all adapters. No other flags may be
+ * provided unless the adapter exported the relevant I2C_FUNC_*
+ * flags through i2c_check_functionality().
+ * @len: Number of data bytes in @buf being read from or written to the
+ * I2C slave address. For read transactions where I2C_M_RECV_LEN
+ * is set, the caller guarantees that this buffer can hold up to
+ * 32 bytes in addition to the initial length byte sent by the
+ * slave (plus, if used, the SMBus PEC); and this value will be
+ * incremented by the number of block data bytes received.
+ * @buf: The buffer into which data is read, or from which it's written.
+ *
+ * An i2c_msg is the low level representation of one segment of an I2C
+ * transaction. It is visible to drivers in the @i2c_transfer() procedure,
+ * to userspace from i2c-dev, and to I2C adapter drivers through the
+ * @i2c_adapter.@master_xfer() method.
+ *
+ * Except when I2C "protocol mangling" is used, all I2C adapters implement
+ * the standard rules for I2C transactions. Each transaction begins with a
+ * START. That is followed by the slave address, and a bit encoding read
+ * versus write. Then follow all the data bytes, possibly including a byte
+ * with SMBus PEC. The transfer terminates with a NAK, or when all those
+ * bytes have been transferred and ACKed. If this is the last message in a
+ * group, it is followed by a STOP. Otherwise it is followed by the next
+ * @i2c_msg transaction segment, beginning with a (repeated) START.
+ *
+ * Alternatively, when the adapter supports I2C_FUNC_PROTOCOL_MANGLING then
+ * passing certain @flags may have changed those standard protocol behaviors.
+ * Those flags are only for use with broken/nonconforming slaves, and with
+ * adapters which are known to support the specific mangling options they
+ * need (one or more of IGNORE_NAK, NO_RD_ACK, NOSTART, and REV_DIR_ADDR).
+ */
+struct i2c_msg {
+ __u16 addr; /* slave address */
+ __u16 flags;
+#define I2C_M_TEN 0x0010 /* this is a ten bit chip address */
+#define I2C_M_RD 0x0001 /* read data, from slave to master */
+#define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_NO_RD_ACK 0x0800 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_RECV_LEN 0x0400 /* length will be first received byte */
+ __u16 len; /* msg length */
+ __u8 *buf; /* pointer to msg data */
+};
+
+#define MESON_I2C_MASTER_AO_START (AO_I2C_M_0_CONTROL_REG)
+//#define MESON_I2C_MASTER_AO_END (0xc810051c+5)
+
+#define MESON_I2C_MASTER_A_START CBUS_REG_ADDR(I2C_M_0_CONTROL_REG)
+#define MESON_I2C_MASTER_A_END (CBUS_REG_ADDR(I2C_M_0_RDATA_REG1+1)-1)
+
+#define MESON_I2C_MASTER_B_START CBUS_REG_ADDR(I2C_M_1_CONTROL_REG)
+#define MESON_I2C_MASTER_B_END (CBUS_REG_ADDR(I2C_M_1_RDATA_REG1+1)-1)
+
+#define MESON_I2C_MASTER_C_START CBUS_REG_ADDR(I2C_M_2_CONTROL_REG)
+#define MESON_I2C_MASTER_C_END (CBUS_REG_ADDR(I2C_M_2_RDATA_REG1+1)-1)
+
+#define MESON_I2C_MASTER_D_START CBUS_REG_ADDR(I2C_M_3_CONTROL_REG)
+#define MESON_I2C_MASTER_D_END (CBUS_REG_ADDR(I2C_M_3_RDATA_REG1+1)-1)
+
+#define MESON_I2C_SLAVE_START CBUS_REG_ADDR(I2C_S_CONTROL_REG)
+#define MESON_I2C_SLAVE_END (CBUS_REG_ADDR(I2C_S_CNTL1_REG+1)-1)
+
+
+#define AML_I2C_MASTER_AO 0
+#define AML_I2C_MASTER_A 1
+#define AML_I2C_MASTER_B 2
+#define AML_I2C_MASTER_C 3
+#define AML_I2C_MASTER_D 4
+
+
+#define AML_I2C_SLAVE_ADDR 0x6c
+
+/*M1 i2c pinmux
+ * I/O I2C_MASTER_A I2C_MASTER_B I2C_SLAVE
+ * GPIO_JTAG_TMS SCK_A REG1[12] SCK_A REG1[13]
+ * GPIO_JTAG_TDI SDA_A REG1[12] SDA_A REG1[13]
+ * GPIO_JTAG_TCK SCK_B REG1[16] SCK_A REG1[17]
+ * GPIO_JTAG_TDO SDA_B REG1[20] SDA_A REG1[21]
+ * GPIOB_0 SCK_B REG2[5] SCK_A REG2[6]
+ * GPIOB_1 SDA_B REG2[2] SDA_A REG2[3]
+ * GPIOB_2 SCK_A REGS[13] SCK_A REG2[14]
+ * GPIOB_3 SDA_A REG2[9] SDA_A REG2[10]
+ * GPIOC_13 SCK_B REG3[28] SCK_A REG3[29]
+ * GPIOC_14 SDA_B REG3[25] SDA_A REG3[26]
+ * GPIOC_21 SCK_A REG7[9] SCK_A REG7[10]
+ * GPIOC_22 SDA_A REG7[6] SDA_A REG7[7]
+ * GPIOE_16 SCK_B REG5[27] SCK_A REG5[28]
+ * GPIOE_17 SDA_B REG5[25] SDA_A REG5[26]
+*/
+
+/*i2c master a*/
+
+
+#define MESON_I2C_MASTER_A_GPIOZ_17_REG (PERIPHS_PIN_MUX_9)
+#define MESON_I2C_MASTER_A_GPIOZ_17_BIT (1<<7)
+#define MESON_I2C_MASTER_A_GPIOZ_18_REG (PERIPHS_PIN_MUX_9)
+#define MESON_I2C_MASTER_A_GPIOZ_18_BIT (1<<8)
+
+#define MESON_I2C_MASTER_A_GPIOW_0_REG (PERIPHS_PIN_MUX_5)
+#define MESON_I2C_MASTER_A_GPIOW_0_BIT (1<<22)
+#define MESON_I2C_MASTER_A_GPIOW_1_REG (PERIPHS_PIN_MUX_5)
+#define MESON_I2C_MASTER_A_GPIOW_1_BIT (1<<23)
+
+/*i2c master b*/
+
+
+#define MESON_I2C_MASTER_B_GPIOH_3_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_B_GPIOH_3_BIT (1<<6)
+#define MESON_I2C_MASTER_B_GPIOH_4_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_B_GPIOH_4_BIT (1<<7)
+
+#define MESON_I2C_MASTER_B_GPIOY_12_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_B_GPIOY_12_BIT (1<<14)
+#define MESON_I2C_MASTER_B_GPIOY_13_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_B_GPIOY_13_BIT (1<<15)
+
+/*i2c master c*/
+#define MESON_I2C_MASTER_C_GPIOY_7_REG (PERIPHS_PIN_MUX_4)
+#define MESON_I2C_MASTER_C_GPIOY_7_BIT (1<<28)
+#define MESON_I2C_MASTER_C_GPIOY_8_REG (PERIPHS_PIN_MUX_4)
+#define MESON_I2C_MASTER_C_GPIOY_8_BIT (1<<29)
+
+#define MESON_I2C_MASTER_C_GPIOX_0_REG (PERIPHS_PIN_MUX_1)
+#define MESON_I2C_MASTER_C_GPIOX_0_BIT (1<<22)
+#define MESON_I2C_MASTER_C_GPIOX_1_REG (PERIPHS_PIN_MUX_1)
+#define MESON_I2C_MASTER_C_GPIOX_1_BIT (1<<23)
+
+/*i2c master d*/
+
+
+#define MESON_I2C_MASTER_D_GPIOY_10_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_D_GPIOY_10_BIT (1<<10)
+#define MESON_I2C_MASTER_D_GPIOY_11_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_D_GPIOY_11_BIT (1<<11)
+
+#define MESON_I2C_MASTER_D_GPIOH_5_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_D_GPIOH_5_BIT (1<<23)
+#define MESON_I2C_MASTER_D_GPIOH_6_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_D_GPIOH_6_BIT (1<<24)
+
+/*i2c master AO*/
+
+
+#define MESON_I2C_MASTER_AO_GPIOAO_4_REG (P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */
+#define MESON_I2C_MASTER_AO_GPIOAO_4_BIT (1<<8)
+#define MESON_I2C_MASTER_AO_GPIOAO_5_REG (P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */
+#define MESON_I2C_MASTER_AO_GPIOAO_5_BIT (1<<9)
+
+/*i2c slave*/
+#define MESON_I2C_SLAVE_JTAG_TMS_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TMS_BIT (1<<13)
+#define MESON_I2C_SLAVE_JTAG_TDI_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TDI_BIT (1<<13)
+
+#define MESON_I2C_SLAVE_GPIOB_2_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_2_BIT (1<<14)
+#define MESON_I2C_SLAVE_GPIOB_3_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_3_BIT (1<<10)
+
+#define MESON_I2C_SLAVE_GPIOC_21_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_7)
+#define MESON_I2C_SLAVE_GPIOC_21_BIT (1<<10)
+#define MESON_I2C_SLAVE_GPIOC_22_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_7)
+#define MESON_I2C_SLAVE_GPIOC_22_BIT (1<<7)
+
+#define MESON_I2C_SLAVE_JTAG_TCK_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TCK_BIT (1<<17)
+#define MESON_I2C_SLAVE_JTAG_TDO_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TDO_BIT (1<<21)
+
+#define MESON_I2C_SLAVE_GPIOB_0_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_0_BIT (1<<6)
+#define MESON_I2C_SLAVE_GPIOB_1_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_1_BIT (1<<3)
+
+#define MESON_I2C_SLAVE_GPIOC_13_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_3)
+#define MESON_I2C_SLAVE_GPIOC_13_BIT (1<<29)
+#define MESON_I2C_SLAVE_GPIOC_14_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_3)
+#define MESON_I2C_SLAVE_GPIOC_14_BIT (1<<26)
+
+#define MESON_I2C_SLAVE_GPIOC_16_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_5)
+#define MESON_I2C_SLAVE_GPIOC_16_BIT (1<<28)
+#define MESON_I2C_SLAVE_GPIOC_17_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_5)
+#define MESON_I2C_SLAVE_GPIOC_17_BIT (1<<26)
+
+
+#define AML_I2C_SPPED_50K 50000
+#define AML_I2C_SPPED_100K 100000
+#define AML_I2C_SPPED_200K 200000
+#define AML_I2C_SPPED_300K 300000
+#define AML_I2C_SPPED_400K 400000
+
+struct aml_pinmux_reg_bit {
+ unsigned long scl_reg;
+ unsigned long sda_reg;
+ unsigned int scl_bit;
+ unsigned int sda_bit;
+};
+
+struct aml_i2c_platform{
+ unsigned int slave_addr;/*7bit addr*/
+ unsigned int wait_count;/*i2c wait ack timeout =
+ wait_count * wait_ack_interval */
+ unsigned int wait_ack_interval;
+ unsigned int wait_read_interval;
+ unsigned int wait_xfer_interval;
+ unsigned int master_no;
+ unsigned int use_pio;/*0: hardware i2c, 1: manual pio i2c*/
+ unsigned int master_i2c_speed;
+
+ /* only need 1 i2c master to comunicate with several devices,
+ * should I prepare 2 master interface to use simultaneously?*/
+ struct resource * resource;
+ struct aml_pinmux_reg_bit master_ao_pinmux;
+ struct aml_pinmux_reg_bit master_a_pinmux;
+ struct aml_pinmux_reg_bit master_b_pinmux;
+ struct aml_pinmux_reg_bit master_c_pinmux;
+ struct aml_pinmux_reg_bit master_d_pinmux;
+
+ struct aml_pinmux_reg_bit slave_reg_bit;
+};
+
+/**************i2c software gpio***************/
+
+#define MESON_I2C_PREG_GPIOC_OE CBUS_REG_ADDR(PREG_FGPIO_EN_N)
+#define MESON_I2C_PREG_GPIOC_OUTLVL CBUS_REG_ADDR(PREG_FGPIO_O)
+#define MESON_I2C_PREG_GPIOC_INLVL CBUS_REG_ADDR(PREG_FGPIO_I)
+
+#define MESON_I2C_PREG_GPIOE_OE CBUS_REG_ADDR(PREG_HGPIO_EN_N)
+#define MESON_I2C_PREG_GPIOE_OUTLVL CBUS_REG_ADDR(PREG_HGPIO_O)
+#define MESON_I2C_PREG_GPIOE_INLVL CBUS_REG_ADDR(PREG_HGPIO_I)
+
+#define MESON_I2C_PREG_GPIOA_OE CBUS_REG_ADDR(PREG_EGPIO_EN_N)
+#define MESON_I2C_PREG_GPIOA_OUTLVL CBUS_REG_ADDR(PREG_EGPIO_O)
+#define MESON_I2C_PREG_GPIOA_INLVL CBUS_REG_ADDR(PREG_EGPIO_I)
+
+struct aml_sw_i2c_pins
+{
+ unsigned int scl_reg_out;
+ unsigned int scl_reg_in;
+ unsigned int scl_bit;
+ unsigned int scl_oe;
+ unsigned int sda_reg_out;
+ unsigned int sda_reg_in;
+ unsigned int sda_bit;
+ unsigned int sda_oe;
+};
+
+
+struct aml_sw_i2c_platform {
+ struct aml_sw_i2c_pins sw_pins;
+
+ /* local settings */
+ int udelay; /* half clock cycle time in us,
+ minimum 2 us for fast-mode I2C,
+ minimum 5 us for standard-mode I2C and SMBus,
+ maximum 50 us for SMBus */
+ int timeout; /* in jiffies */
+};
+
+
+#endif //__AML_MACH_I2C__
+
+
diff --git a/arch/arm/include/asm/arch-s4/io.h b/arch/arm/include/asm/arch-s4/io.h
new file mode 100644
index 0000000..fd3981a
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/io.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __MACH_MESSON_REGS_IO_H
+#define __MACH_MESSON_REGS_IO_H
+
+#ifndef __ASSEMBLY__
+
+#include <asm/io.h>
+#define IO_CBUS_BASE (0xFFD00000L)
+#define IO_AXI_BUS_BASE (0xFFB00000L) /* gpv */
+#define IO_AHB_BUS_BASE (0xFF500000L) /* usb0 */
+#define IO_APB_BUS_BASE (0xFFFC0000L) /* AHB SRAM, sec/sys ahb? txlx_mem_map.xlsx */
+#define IO_APB_HDMI_BUS_BASE (0xFFE00000L) /* */
+#define IO_VPU_BUS_BASE (0xFF900000L) /* VPU */
+
+#define CBUS_REG_OFFSET(reg) ((reg) << 2)
+#define CBUS_REG_ADDR(reg) (IO_CBUS_BASE + CBUS_REG_OFFSET(reg))
+
+#define AXI_REG_OFFSET(reg) ((reg) << 2)
+#define AXI_REG_ADDR(reg) (IO_AXI_BUS_BASE + AXI_REG_OFFSET(reg))
+
+#define AHB_REG_OFFSET(reg) ((reg) << 2)
+#define AHB_REG_ADDR(reg) (IO_AHB_BUS_BASE + AHB_REG_OFFSET(reg))
+
+#define VPU_REG_OFFSET(reg) ((reg) << 2)
+#define VPU_REG_ADDR(reg) (IO_VPU_BUS_BASE + VPU_REG_OFFSET(reg))
+
+
+#define APB_REG_OFFSET(reg) (reg)
+#define APB_REG_ADDR(reg) (IO_APB_BUS_BASE + APB_REG_OFFSET(reg))
+#define APB_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0)
+
+#define APB_HDMI_REG_OFFSET(reg) (reg)
+#define APB_HDMI_REG_ADDR(reg) (IO_APB_HDMI_BUS_BASE + APB_HDMI_REG_OFFSET(reg))
+#define APB_HDMI_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0)
+
+
+#define WRITE_CBUS_REG(reg, val) __raw_writel(val, CBUS_REG_ADDR(reg))
+#define READ_CBUS_REG(reg) (__raw_readl(CBUS_REG_ADDR(reg)))
+#define WRITE_CBUS_REG_BITS(reg, val, start, len) \
+ WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_CBUS_REG_BITS(reg, start, len) \
+ ((READ_CBUS_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)&(~(mask))))
+#define SET_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)|(mask)))
+
+#define WRITE_AXI_REG(reg, val) __raw_writel(val, AXI_REG_ADDR(reg))
+#define READ_AXI_REG(reg) (__raw_readl(AXI_REG_ADDR(reg)))
+#define WRITE_AXI_REG_BITS(reg, val, start, len) \
+ WRITE_AXI_REG(reg, (READ_AXI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_AXI_REG_BITS(reg, start, len) \
+ ((READ_AXI_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)&(~(mask))))
+#define SET_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)|(mask)))
+
+#define WRITE_AHB_REG(reg, val) __raw_writel(val, AHB_REG_ADDR(reg))
+#define READ_AHB_REG(reg) (__raw_readl(AHB_REG_ADDR(reg)))
+#define WRITE_AHB_REG_BITS(reg, val, start, len) \
+ WRITE_AHB_REG(reg, (READ_AHB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_AHB_REG_BITS(reg, start, len) \
+ ((READ_AHB_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)&(~(mask))))
+#define SET_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)|(mask)))
+
+#define WRITE_APB_REG(reg, val) __raw_writel(val, APB_REG_ADDR(reg))
+#define READ_APB_REG(reg) (__raw_readl(APB_REG_ADDR(reg)))
+#define WRITE_APB_REG_BITS(reg, val, start, len) \
+ WRITE_APB_REG(reg, (READ_APB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_APB_REG_BITS(reg, start, len) \
+ ((READ_APB_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)&(~(mask))))
+#define SET_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)|(mask)))
+
+#define WRITE_APB_HDMI_REG(reg, val) __raw_writel(val, APB_HDMI_REG_ADDR(reg))
+#define READ_APB_HDMI_REG(reg) (__raw_readl(APB_HDMI_REG_ADDR(reg)))
+#define WRITE_APB_HDMI_REG_BITS(reg, val, start, len) \
+ WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_APB_HDMI_REG_BITS(reg, start, len) \
+ ((READ_APB_HDMI_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)&(~(mask))))
+#define SET_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)|(mask)))
+
+/* for back compatible alias */
+#define WRITE_MPEG_REG(reg, val) \
+ WRITE_CBUS_REG(reg, val)
+#define READ_MPEG_REG(reg) \
+ READ_CBUS_REG(reg)
+#define WRITE_MPEG_REG_BITS(reg, val, start, len) \
+ WRITE_CBUS_REG_BITS(reg, val, start, len)
+#define READ_MPEG_REG_BITS(reg, start, len) \
+ READ_CBUS_REG_BITS(reg, start, len)
+#define CLEAR_MPEG_REG_MASK(reg, mask) \
+ CLEAR_CBUS_REG_MASK(reg, mask)
+#define SET_MPEG_REG_MASK(reg, mask) \
+ SET_CBUS_REG_MASK(reg, mask)
+#endif
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-s4/mailbox.h b/arch/arm/include/asm/arch-s4/mailbox.h
new file mode 100644
index 0000000..259ae8f
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/mailbox.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+ /*
+ *
+ * Copyright (C) 2012 Amlogic, Inc.
+ *
+ * Author: Platform-SH@amlogic.com
+ *
+ */
+
+#ifndef __MAILBOX_H__
+#define __MAILBOX_H__
+#include <asm/arch/secure_apb.h>
+#include <common.h>
+
+#define REE2AO_SET_ADDR MAILBOX_SET_MBOX03
+#define REE2AO_STS_ADDR MAILBOX_STS_MBOX03
+#define REE2AO_CLR_ADDR MAILBOX_CLR_MBOX03
+#define REE2AO_WR_ADDR MAILBOX_WR_MBOX03
+#define REE2AO_RD_ADDR MAILBOX_RD_MBOX03
+#define REE2AO_IRQCLR_ADDR MAILBOX_IRQA_CLR
+
+#define MAILBOX_USER_DATA_SIZE 96
+
+#define MHU_SYNC (1 << 26)
+#define MHU_CMD_BUILD(command, size) \
+ (((command) & 0xffff) | (((size) & 0x1ff) << 16) | MHU_SYNC)
+#define MHU_ACK_MASK(mbox) (1 << ((mbox)*2 + 1))
+
+#define MHU_PAYLOAD_SIZE 0x80
+#define MHU_DATA_OFFSET 0x1c
+#define REE2AO_MBOX_ID 0x3
+/* ...Message composition with module(6bits), function(10bits) */
+#define __MBX_COMPOSE_MSG(mod, func) (((mod) << 10) | ((func) & 0x3FF))
+
+/*******************************************************************************
+ * Define moudle type here, 6bits valid
+ ******************************************************************************/
+#define MBX_SYSTEM 0x0
+
+/*******************************************************************************
+ * Define function here, 10bits valid
+ ******************************************************************************/
+ /*SYSTEM*/
+#define CMD_UNDEFINE 0x0
+#define CMD_TEST 0x6
+#define CMD_LED_INFO 0xF7
+
+/*******************************************************************************
+ * Mssage Comopsition
+ ******************************************************************************/
+#define MBX_CMD_TEST __MBX_COMPOSE_MSG(MBX_SYSTEM, CMD_TEST)
+enum {
+ HIFIA_REE_CHANNEL = 0,
+ HIFIB_REE_CHANNEL = 1,
+ SECPU_REE_CHANNEL = 2,
+ AOCPU_REE_CHANNEL = 3,
+};
+
+void mhu_init(void);
+/*message max size MAILBOX_USER_DATA_SIZE 96 byte*/
+int scpi_send_data(uint32_t chan, uint32_t command,
+ void *sendmessage, uint32_t sendsize,
+ void *revmessage, uint32_t revsize);
+#endif /* __SCPI_FIFO_H__ */
diff --git a/arch/arm/include/asm/arch-s4/mnPmuSramMsgBlock_ddr3.h b/arch/arm/include/asm/arch-s4/mnPmuSramMsgBlock_ddr3.h
new file mode 100644
index 0000000..c067367
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/mnPmuSramMsgBlock_ddr3.h
@@ -0,0 +1,637 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief DDR3U_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_DDR3U_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Train vrefDAC0 During Read Deskew
+ // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] = MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] = SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] = SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] = RFU, must be zero (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero)
+ //
+ //
+ //
+ // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] = PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte
+ // 0x0 = All rank populated with all the byte (tyical configuration)
+ //
+ // MsgMisc[7] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware.
+ // Please reference this revision ID when filing support cases with Synopsys.
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Module Type:
+ // 0x01 = DDR3 unbuffered
+ // 0x02 = Reserved
+ // 0x03 = Reserved
+ // 0x04 = Reserved
+ // 0x05 = Reserved
+ //
+ uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7):
+ // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting)
+ uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ // Total number of DQ bits enabled in PHY
+ uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS.
+ //
+ // If the bit is set to 1, the CS is connected to DRAM.
+ // If the bit is set to 0, the CS is not connected to DRAM.
+ //
+ // CsPresent[0] = CS0 is populated with DRAM
+ // CsPresent[1] = CS1 is populated with DRAM
+ // CsPresent[2] = CS2 is populated with DRAM
+ // CsPresent[3] = CS3 is populated with DRAM
+ // CsPresent[7:4] = Reserved (must be programmed to 0)
+ //
+ //
+ uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 0
+ uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 1
+ uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ // Corresponds to CS[3:0]
+ // 1 = Address Mirror.
+ // 0 = No Address Mirror.
+ uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ // Additional mode bits.
+ //
+ // Bit fields:
+ // [0] SlowAccessMode :
+ // 1 = 2T Address Timing.
+ // 0 = 1T Address Timing.
+ // [7-1] RFU, must be zero
+ uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[10] = RFU, must be zero
+ // SequenceCtrl[11] = RFU, must be zero
+ // SequenceCtrl[12] = RFU, must be zero
+ // SequenceCtrl[13] = RFU, must be zero
+ // SequenceCtrl[15-14] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A
+
+
+
+ uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D training in: Rd2D, Wr2D
+ //
+ // Reserved1E[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1E[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR6
+ // 2 = limit to +/-4 %VDDQ from MR6
+ // …
+ // 15 = limit to +/-30% VDDQ from MR6
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A
+ // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset.
+ uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ // Value of DDR mode register MR0 for all ranks for current pstate
+ uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Value of DDR mode register MR1 for all ranks for current pstate
+ uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ // Value of DDR mode register MR2 for all ranks for current pstate
+ uint8_t Reserved64; // Byte offset 0x64, CSR Addr 0x54032, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved65; // Byte offset 0x65, CSR Addr 0x54032, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6E; // Byte offset 0x6e, CSR Addr 0x54037, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6F; // Byte offset 0x6f, CSR Addr 0x54037, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved71; // Byte offset 0x71, CSR Addr 0x54038, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved72; // Byte offset 0x72, CSR Addr 0x54039, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved73; // Byte offset 0x73, CSR Addr 0x54039, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl0; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl2; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl3; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl4; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl5; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl7; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7C; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7D; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A
+
+ uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A
+
+ uint8_t Reserved8A; // Byte offset 0x8a, CSR Addr 0x54045, Direction=N/A
+
+ uint8_t Reserved8B; // Byte offset 0x8b, CSR Addr 0x54045, Direction=N/A
+
+ uint8_t Reserved8C; // Byte offset 0x8c, CSR Addr 0x54046, Direction=N/A
+
+ uint8_t Reserved8D; // Byte offset 0x8d, CSR Addr 0x54046, Direction=N/A
+
+ uint8_t Reserved8E; // Byte offset 0x8e, CSR Addr 0x54047, Direction=N/A
+
+ uint8_t Reserved8F; // Byte offset 0x8f, CSR Addr 0x54047, Direction=N/A
+
+ uint8_t Reserved90; // Byte offset 0x90, CSR Addr 0x54048, Direction=N/A
+
+ uint8_t Reserved91; // Byte offset 0x91, CSR Addr 0x54048, Direction=N/A
+
+ uint8_t Reserved92; // Byte offset 0x92, CSR Addr 0x54049, Direction=N/A
+
+ uint8_t Reserved93; // Byte offset 0x93, CSR Addr 0x54049, Direction=N/A
+
+ uint8_t Reserved94; // Byte offset 0x94, CSR Addr 0x5404a, Direction=N/A
+
+ uint8_t Reserved95; // Byte offset 0x95, CSR Addr 0x5404a, Direction=N/A
+
+ uint8_t Reserved96; // Byte offset 0x96, CSR Addr 0x5404b, Direction=N/A
+
+ uint8_t Reserved97; // Byte offset 0x97, CSR Addr 0x5404b, Direction=N/A
+
+ uint8_t Reserved98; // Byte offset 0x98, CSR Addr 0x5404c, Direction=N/A
+
+ uint8_t Reserved99; // Byte offset 0x99, CSR Addr 0x5404c, Direction=N/A
+
+ uint8_t Reserved9A; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=N/A
+
+ uint8_t Reserved9B; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=N/A
+
+ uint8_t Reserved9C; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=N/A
+
+ uint8_t Reserved9D; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=N/A
+
+ uint8_t Reserved9E; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=N/A
+
+ uint8_t Reserved9F; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=N/A
+
+ uint8_t ReservedA0; // Byte offset 0xa0, CSR Addr 0x54050, Direction=N/A
+
+ uint8_t ReservedA1; // Byte offset 0xa1, CSR Addr 0x54050, Direction=N/A
+
+ uint8_t ReservedA2; // Byte offset 0xa2, CSR Addr 0x54051, Direction=N/A
+
+ uint8_t ReservedA3; // Byte offset 0xa3, CSR Addr 0x54051, Direction=N/A
+
+} __attribute__ ((packed)) PMU_SMB_DDR3U_1D_t;
diff --git a/arch/arm/include/asm/arch-s4/mnPmuSramMsgBlock_ddr4.h b/arch/arm/include/asm/arch-s4/mnPmuSramMsgBlock_ddr4.h
new file mode 100644
index 0000000..6dfd4d0
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/mnPmuSramMsgBlock_ddr4.h
@@ -0,0 +1,2380 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief DDR4U_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_DDR4U_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Train vrefDAC0 During Read Deskew
+ // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] = MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] = SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] = SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D.
+ // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field
+ //
+ // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] = PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte
+ // 0x0 = All rank populated with all the byte (tyical configuration)
+ //
+ // MsgMisc[7] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware.
+ // Please reference this revision ID when filing support cases with Synopsys.
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Module Type:
+ // 0x01 = Reserved
+ // 0x02 = DDR4 unbuffered
+ // 0x03 = Reserved
+ // 0x04 = Reserved
+ // 0x05 = Reserved
+ //
+ uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7):
+ // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting)
+ uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ // Total number of DQ bits enabled in PHY
+ uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS.
+ //
+ // If the bit is set to 1, the CS is connected to DRAM.
+ // If the bit is set to 0, the CS is not connected to DRAM.
+ //
+ // CsPresent[0] = CS0 is populated with DRAM
+ // CsPresent[1] = CS1 is populated with DRAM
+ // CsPresent[2] = CS2 is populated with DRAM
+ // CsPresent[3] = CS3 is populated with DRAM
+ // CsPresent[7:4] = Reserved (must be programmed to 0)
+ //
+ //
+ uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 0
+ uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 1
+ uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ // Corresponds to CS[3:0]
+ // 1 = Address Mirror.
+ // 0 = No Address Mirror.
+ uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ // Additional mode bits.
+ //
+ // Bit fields:
+ // [0] SlowAccessMode :
+ // 1 = 2T Address Timing.
+ // 0 = 1T Address Timing.
+ // [7-1] RFU, must be zero
+ uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[10] = Run Reserved
+ // SequenceCtrl[11] = Run Reserved
+ // SequenceCtrl[12] = Run Reserved
+ // SequenceCtrl[13] = Run Reserved
+ // SequenceCtrl[15-14] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A
+
+
+
+ uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D training in: Rd2D, Wr2D
+ //
+ // Reserved1E[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1E[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR6
+ // 2 = limit to +/-4 %VDDQ from MR6
+ // …
+ // 15 = limit to +/-30% VDDQ from MR6
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A
+ // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset.
+ uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ // Value of DDR mode register MR0 for all ranks for current pstate
+ uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Value of DDR mode register MR1 for all ranks for current pstate
+ uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ // Value of DDR mode register MR2 for all ranks for current pstate
+ uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ // Value of DDR mode register MR3 for all ranks for current pstate
+ uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value of DDR mode register MR4 for all ranks for current pstate
+ uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value of DDR mode register MR5 for all ranks for current pstate
+ uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0.
+ uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // X16 device map. Corresponds to CS[3:0].
+ // X16Present[0] = CS0 is populated with X16 devices
+ // X16Present[1] = CS1 is populated with X16 devices
+ // X16Present[2] = CS2 is populated with X16 devices
+ // X16Present[3] = CS3 is populated with X16 devices
+ // X16Present[7:4] = Reserved (must be programmed to 0)
+ //
+ // Ranks may not contain mixed device types.
+ uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // controls timing of chip select signals when DDR4 gear-down mode is active
+ // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs
+ // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode
+ uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM:
+ // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0
+ // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0
+ // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0
+ uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM:
+ // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1
+ // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1
+ // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1
+ uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM:
+ // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2
+ // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2
+ // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2
+ uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM:
+ // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3
+ // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3
+ // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3
+ uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM:
+ // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4
+ // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4
+ // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4
+ uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM:
+ // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5
+ // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5
+ // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5
+ uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM:
+ // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6
+ // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6
+ // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6
+ uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM:
+ // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7
+ // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7
+ // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7
+ uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices.
+ uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices.
+ uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices.
+ uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices.
+ uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices.
+ uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices.
+ uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices.
+ uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices.
+ uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices.
+ uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices.
+ uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices.
+ uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices.
+ uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices.
+ uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices.
+ uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices.
+ uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices.
+ uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices.
+ uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices.
+ uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices.
+ uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices.
+ uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices.
+ uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices.
+ uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices.
+ uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices.
+ uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices.
+ uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices.
+ uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices.
+ uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices.
+ uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices.
+ uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices.
+ uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices.
+ uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices.
+ uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices.
+ uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices.
+ uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices.
+ uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices.
+ uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices.
+ uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices.
+ uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices.
+ uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices.
+ uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A
+
+ uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A
+
+ uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in
+ // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1).
+ // RdDBI is dynamically disabled in certain training steps,
+ // and so the [RdDBI disabled] CAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_CAS_L[0] == 0: use value in MR0
+ // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2]
+ // Other bits are ignored
+ uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In
+ // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1).
+ // 2tCK write prambles are dynamically disabled in certain training steps,
+ // and so the [1tCK write preamble] WCAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_WCAS_L[0] == 0: use value in MR2
+ // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3]
+ // Other bits are ignored
+ uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In
+ // Contains various options for training DDR4 Devices.
+ //
+ // Bit fields:
+ //
+ // D4Misc[7:1] RFU, must be zero
+ //
+ // D4Misc[0] = protect memory reset
+ // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training.
+ // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training
+} __attribute__ ((packed)) PMU_SMB_DDR4U_1D_t;
diff --git a/arch/arm/include/asm/arch-s4/mnPmuSramMsgBlock_ddr4_2d.h b/arch/arm/include/asm/arch-s4/mnPmuSramMsgBlock_ddr4_2d.h
new file mode 100644
index 0000000..35b1e23
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/mnPmuSramMsgBlock_ddr4_2d.h
@@ -0,0 +1,2282 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief DDR4U_2D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_DDR4U_2D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Train vrefDAC0 During Read Deskew
+ // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] = MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] = SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] = SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D.
+ // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field
+ //
+ // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] = PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte
+ // 0x0 = All rank populated with all the byte (tyical configuration)
+ //
+ // MsgMisc[7] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware.
+ // Please reference this revision ID when filing support cases with Synopsys.
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Module Type:
+ // 0x01 = Reserved
+ // 0x02 = DDR4 unbuffered
+ // 0x03 = Reserved
+ // 0x04 = Reserved
+ // 0x05 = Reserved
+ //
+ uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7):
+ // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting)
+ uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ // Total number of DQ bits enabled in PHY
+ uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS.
+ //
+ // If the bit is set to 1, the CS is connected to DRAM.
+ // If the bit is set to 0, the CS is not connected to DRAM.
+ //
+ // CsPresent[0] = CS0 is populated with DRAM
+ // CsPresent[1] = CS1 is populated with DRAM
+ // CsPresent[2] = CS2 is populated with DRAM
+ // CsPresent[3] = CS3 is populated with DRAM
+ // CsPresent[7:4] = Reserved (must be programmed to 0)
+ //
+ //
+ uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 0
+ uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 1
+ uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ // Corresponds to CS[3:0]
+ // 1 = Address Mirror.
+ // 0 = No Address Mirror.
+ uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ // Additional mode bits.
+ //
+ // Bit fields:
+ // [0] SlowAccessMode :
+ // 1 = 2T Address Timing.
+ // 0 = 1T Address Timing.
+ // [7-1] RFU, must be zero
+ uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = RFU, must be zero
+ // SequenceCtrl[2] = RFU, must be zero
+ // SequenceCtrl[3] = RFU, must be zero
+ // SequenceCtrl[4] = RFU, must be zero
+ // SequenceCtrl[5] = Run rd2D - 2d read dqs training
+ // SequenceCtrl[6] = Run wr2D - 2d write dq training
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = RFU, must be zero
+ // SequenceCtrl[9] = RFU, must be zero
+ // SequenceCtrl[10] = RFU, must be zero
+ // SequenceCtrl[11] = RFU, must be zero
+ // SequenceCtrl[12] = RFU, must be zero
+ // SequenceCtrl[13] = RFU, must be zero
+ // SequenceCtrl[15-14] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t RX2D_TrainOpt; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In
+ // Bit fields, if 2D read training enabled, then use these additional options:
+ // [0] DFE
+ // 1 = Run rx2D with DFE
+ // 0 = Run rx2D with DFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5-7] RFU, must be zero
+ //
+ uint8_t TX2D_TrainOpt; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Bit fields, if 2D write training is enabled, then use these additional options:
+ // [0] FFE
+ // 1 = Train tx2D with FFE
+ // 0 = Train tx2D with FFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5] FFE Decision Algorithm Control
+ // 1 = FFE chooses the drive strength that maximizes the average eye-area across the entire phy.
+ // 0 = FFE chooses the drive strength that maximizes the smallest eye across the entire phy.
+ // [6-7] RFU, must be zero
+ //
+ uint8_t Share2DVrefResult; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // Bitmap that designates the phy's vref source for every pstate
+ // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock.
+ // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training.
+ uint8_t Delay_Weight2D; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye.
+ uint8_t Voltage_Weight2D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye.
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D training in: Rd2D, Wr2D
+ //
+ // Reserved1E[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1E[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR6
+ // 2 = limit to +/-4 %VDDQ from MR6
+ // …
+ // 15 = limit to +/-30% VDDQ from MR6
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ uint8_t R0_RxClkDly_Margin; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R0_VrefDac_Margin; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R0_TxDqDly_Margin; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R0_DeviceVref_Margin; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved29; // Byte offset 0x29, CSR Addr 0x54014, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2A; // Byte offset 0x2a, CSR Addr 0x54015, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2B; // Byte offset 0x2b, CSR Addr 0x54015, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2C; // Byte offset 0x2c, CSR Addr 0x54016, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2D; // Byte offset 0x2d, CSR Addr 0x54016, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2E; // Byte offset 0x2e, CSR Addr 0x54017, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2F; // Byte offset 0x2f, CSR Addr 0x54017, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved31; // Byte offset 0x31, CSR Addr 0x54018, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved32; // Byte offset 0x32, CSR Addr 0x54019, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t R1_RxClkDly_Margin; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R1_VrefDac_Margin; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R1_TxDqDly_Margin; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R1_DeviceVref_Margin; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved37; // Byte offset 0x37, CSR Addr 0x5401b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved39; // Byte offset 0x39, CSR Addr 0x5401c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3A; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3B; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3D; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3E; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3F; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t R2_RxClkDly_Margin; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R2_VrefDac_Margin; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R2_TxDqDly_Margin; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R2_DeviceVref_Margin; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved48; // Byte offset 0x48, CSR Addr 0x54024, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved49; // Byte offset 0x49, CSR Addr 0x54024, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4A; // Byte offset 0x4a, CSR Addr 0x54025, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t R3_RxClkDly_Margin; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R3_VrefDac_Margin; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R3_TxDqDly_Margin; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R3_DeviceVref_Margin; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved57; // Byte offset 0x57, CSR Addr 0x5402b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved58; // Byte offset 0x58, CSR Addr 0x5402c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved59; // Byte offset 0x59, CSR Addr 0x5402c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5B; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5C; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In
+ // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D.
+ //
+ // Reserved5D[0-3]: bitTimeControl
+ // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point.
+ // 0 = 1 kilobit per point (legacy behavior)
+ // 1 = 2 kilobits per point
+ // 2 = 4 kilobits per point
+ // …
+ // 15 = 32 megabits per point
+ //
+ // Reserved5D[4]: Exhaustive2D
+ // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior)
+ // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point.
+ //
+ // Reserved5D[5:7]: RFU, must be 0
+ uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ // Value of DDR mode register MR0 for all ranks for current pstate
+ uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Value of DDR mode register MR1 for all ranks for current pstate
+ uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ // Value of DDR mode register MR2 for all ranks for current pstate
+ uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ // Value of DDR mode register MR3 for all ranks for current pstate
+ uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value of DDR mode register MR4 for all ranks for current pstate
+ uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value of DDR mode register MR5 for all ranks for current pstate
+ uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0.
+ uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // X16 device map. Corresponds to CS[3:0].
+ // X16Present[0] = CS0 is populated with X16 devices
+ // X16Present[1] = CS1 is populated with X16 devices
+ // X16Present[2] = CS2 is populated with X16 devices
+ // X16Present[3] = CS3 is populated with X16 devices
+ // X16Present[7:4] = Reserved (must be programmed to 0)
+ //
+ // Ranks may not contain mixed device types.
+ uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // controls timing of chip select signals when DDR4 gear-down mode is active
+ // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs
+ // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode
+ uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM:
+ // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0
+ // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0
+ // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0
+ uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM:
+ // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1
+ // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1
+ // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1
+ uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM:
+ // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2
+ // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2
+ // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2
+ uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM:
+ // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3
+ // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3
+ // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3
+ uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM:
+ // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4
+ // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4
+ // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4
+ uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM:
+ // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5
+ // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5
+ // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5
+ uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM:
+ // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6
+ // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6
+ // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6
+ uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM:
+ // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7
+ // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7
+ // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7
+ uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices.
+ uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices.
+ uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices.
+ uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices.
+ uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices.
+ uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices.
+ uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices.
+ uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices.
+ uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices.
+ uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices.
+ uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices.
+ uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices.
+ uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices.
+ uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices.
+ uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices.
+ uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices.
+ uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices.
+ uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices.
+ uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices.
+ uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices.
+ uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices.
+ uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices.
+ uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices.
+ uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices.
+ uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices.
+ uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices.
+ uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices.
+ uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices.
+ uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices.
+ uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices.
+ uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices.
+ uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices.
+ uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices.
+ uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices.
+ uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices.
+ uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices.
+ uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices.
+ uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices.
+ uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices.
+ uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices.
+ uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A
+
+ uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A
+
+ uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in
+ // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1).
+ // RdDBI is dynamically disabled in certain training steps,
+ // and so the [RdDBI disabled] CAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_CAS_L[0] == 0: use value in MR0
+ // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2]
+ // Other bits are ignored
+ uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In
+ // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1).
+ // 2tCK write prambles are dynamically disabled in certain training steps,
+ // and so the [1tCK write preamble] WCAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_WCAS_L[0] == 0: use value in MR2
+ // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3]
+ // Other bits are ignored
+ uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In
+ // Contains various options for training DDR4 Devices.
+ //
+ // Bit fields:
+ //
+ // D4Misc[7:1] RFU, must be zero
+ //
+ // D4Misc[0] = protect memory reset
+ // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training.
+ // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training
+} __attribute__ ((packed)) PMU_SMB_DDR4U_2D_t;
diff --git a/arch/arm/include/asm/arch-s4/mnPmuSramMsgBlock_lpddr3.h b/arch/arm/include/asm/arch-s4/mnPmuSramMsgBlock_lpddr3.h
new file mode 100644
index 0000000..6850d06
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/mnPmuSramMsgBlock_lpddr3.h
@@ -0,0 +1,434 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief LPDDR3_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_LPDDR3_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:5] RFU, must be zero
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] RFU, must be zero
+ //
+ // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[7-6] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t Reserved0D; // Byte offset 0x0d, CSR Addr 0x54006, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = RunWrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[10] = RFU, must be zero
+ // SequenceCtrl[11] = RFU, must be zero
+ // SequenceCtrl[12] = Run LPCA - CA Training
+ // SequenceCtrl[13] = RFU, must be zero
+ // SequenceCtrl[14] = RFU, must be zero
+ // SequenceCtrl[15] = RFU, must be zero
+ //
+ uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t DFIMRLMargin; // Byte offset 0x14, CSR Addr 0x5400a, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ //
+ // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system.
+ uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t UseBroadcastMR; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired.
+ //
+ // 0x0 = Use MR<0:17>_A0 for rank 0 channel A
+ // Use MR<0:17>_B0 for rank 0 channel B
+ // Use MR<0:17>_A1 for rank 1 channel A
+ // Use MR<0:17>_B1 for rank 1 channel B
+ //
+ // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks
+ //
+ // This should be set to 1 for all systems.
+ //
+ // Note: If setting this to 0, only mode register settings related to DRAM partial array self-refresh may be different between the ranks and channels. All other mode register settings must be the same for all ranks and channels.
+ uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t LogToPhyByteMap0; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // Physical Byte associated with Channel A logical Byte 0, depending on LogToPhyByteMap0[7] value:
+ // LogToPhyByteMap0[7]==0: Logical Byte 0 map on Physical Byte 0
+ // LogToPhyByteMap0[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap0[6:0]
+ uint8_t LogToPhyByteMap1; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In
+ // Physical Byte associated with Channel A logical Byte 1, depending on LogToPhyByteMap1[7] value:
+ // LogToPhyByteMap1[7]==0: Logical Byte 1 map on Physical Byte 1
+ // LogToPhyByteMap1[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap1[6:0]
+ uint8_t LogToPhyByteMap2; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Physical Byte associated with Channel A logical Byte 2, depending on LogToPhyByteMap2[7] value:
+ // LogToPhyByteMap2[7]==0: Logical Byte 2 map on Physical Byte 2
+ // LogToPhyByteMap2[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap2[6:0]
+ uint8_t LogToPhyByteMap3; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // Physical Byte associated with Channel A logical Byte 3, depending on LogToPhyByteMap3[7] value:
+ // LogToPhyByteMap3[7]==0: Logical Byte 3 map on Physical Byte 3
+ // LogToPhyByteMap3[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap3[6:0]
+ uint8_t LogToPhyByteMap4; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // Physical Byte associated with Channel B logical Byte 0, depending on LogToPhyByteMap4[7] value:
+ // LogToPhyByteMap4[7]==0: Logical Byte 0 map on Physical Byte 4
+ // LogToPhyByteMap4[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap4[6:0]
+ uint8_t LogToPhyByteMap5; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In
+ // Physical Byte associated with Channel B logical Byte 1, depending on LogToPhyByteMap5[7] value:
+ // LogToPhyByteMap5[7]==0: Logical Byte 1 map on Physical Byte 5
+ // LogToPhyByteMap5[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap5[6:0]
+ uint8_t LogToPhyByteMap6; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Physical Byte associated with Channel B logical Byte 2, depending on LogToPhyByteMap6[7] value:
+ // LogToPhyByteMap6[7]==0: Logical Byte 2 map on Physical Byte 6
+ // LogToPhyByteMap6[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap6[6:0]
+ uint8_t LogToPhyByteMap7; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In
+ // Physical Byte associated with Channel B logical Byte 3, depending on LogToPhyByteMap7[7] value:
+ // LogToPhyByteMap7[7]==0: Logical Byte 3 map on Physical Byte 7
+ // LogToPhyByteMap7[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap7[6:0]
+ uint8_t LogToPhyByteMap8; // Byte offset 0x20, CSR Addr 0x54010, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t LogToPhyByteMap9; // Byte offset 0x21, CSR Addr 0x54010, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t EnabledDQsChA; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Total number of DQ bits enabled in PHY Channel A
+ uint8_t CsPresentChA; // Byte offset 0x23, CSR Addr 0x54011, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel A.
+ //
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChA_RR_1_0; // Byte offset 0x24, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RR_0_1; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_1_0; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_0_1; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_A0; // Byte offset 0x31, CSR Addr 0x54018, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0}
+ uint8_t MR2_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0}
+ uint8_t MR3_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0}
+ uint8_t Reserved34; // Byte offset 0x34, CSR Addr 0x5401a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0}
+ uint8_t MR16_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0}
+ uint8_t MR17_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0}
+ uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_A1; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In
+ // Must be programmed the same as MR1_A0
+ uint8_t MR2_A1; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
+ // Must be programmed the same as MR2_A0
+ uint8_t MR3_A1; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
+ // Must be programmed the same as MR3_A0
+ uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_A1; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
+ // Must be programmed the same as MR11_A0
+ uint8_t MR16_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1}
+ uint8_t MR17_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1}
+ uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved41; // Byte offset 0x41, CSR Addr 0x54020, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved42; // Byte offset 0x42, CSR Addr 0x54021, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved43; // Byte offset 0x43, CSR Addr 0x54021, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved44; // Byte offset 0x44, CSR Addr 0x54022, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t EnabledDQsChB; // Byte offset 0x48, CSR Addr 0x54024, Direction=In
+ // Total number of DQ bits enabled in PHY Channel B
+ uint8_t CsPresentChB; // Byte offset 0x49, CSR Addr 0x54024, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel B.
+ //
+ // 0x0 = No chip selects are populated with DRAM
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChB_RR_1_0; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RR_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_1; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs01 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_1; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_1; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_0; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_1_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_0_1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_B0; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In
+ // Must be programmed the same as MR1_A0
+ uint8_t MR2_B0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In
+ // Must be programmed the same as MR2_A0
+ uint8_t MR3_B0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=In
+ // Must be programmed the same as MR3_A0
+ uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_B0; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=In
+ // Must be programmed the same as MR11_A0
+ uint8_t MR16_B0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0}
+ uint8_t MR17_B0; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0}
+ uint8_t Reserved5E; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_B1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=In
+ // Must be programmed the same as MR1_A0
+ uint8_t MR2_B1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Must be programmed the same as MR2_A0
+ uint8_t MR3_B1; // Byte offset 0x61, CSR Addr 0x54030, Direction=In
+ // Must be programmed the same as MR3_A0
+ uint8_t Reserved62; // Byte offset 0x62, CSR Addr 0x54031, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_B1; // Byte offset 0x63, CSR Addr 0x54031, Direction=In
+ // Must be programmed the same as MR11_A0
+ uint8_t MR16_B1; // Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1}
+ uint8_t MR17_B1; // Byte offset 0x65, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1}
+ uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+} __attribute__ ((packed)) PMU_SMB_LPDDR3_1D_t;
diff --git a/arch/arm/include/asm/arch-s4/mnPmuSramMsgBlock_lpddr4.h b/arch/arm/include/asm/arch-s4/mnPmuSramMsgBlock_lpddr4.h
new file mode 100644
index 0000000..d194621
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/mnPmuSramMsgBlock_lpddr4.h
@@ -0,0 +1,557 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief LPDDR4_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_LPDDR4_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Quick Rd2D during 1D Training
+ // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] Disable Boot Clock
+ // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended)
+ // 0x0 = Use Boot Frequency Clock
+ //
+ // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[7-6] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.25*VDDQ, set this field to 0x20.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Lp4 specific options for training.
+ //
+ // Bit fields:
+ //
+ // Lp4Misc[0] Enable dfi_reset_n
+ //
+ // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training.
+ // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin.
+ //
+ // 0x1 = Enables dfi_reset_n to control memreset after training.
+ // PHY Internal registers control memreset during training only.
+ // To ensure that no glitches occur on BP_MEMRESET at the end of training,
+ // The MC must drive dfi_reset_n=1'b1 _prior to starting training_
+ //
+ // Lp4Misc[7-1] RFU, must be zero
+ uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D.
+ //
+ // Reserved0E[0:3]: bitTimeControl
+ // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point.
+ // 0 = 288 bits per point (legacy behavior)
+ // 1 = 576 bits per point
+ // 2 = 1.125 kilobits per point
+ // …
+ // 15 = 9 megabits per point
+ //
+ // Reserved0E[4]: Exhaustive2D
+ // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior)
+ // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point.
+ //
+ // Reserved0E[5:7]: RFU, must be 0
+ uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[11-10] = RFU, must be zero
+ // SequenceCtrl[12] = Run LPCA - CA Training
+ // SequenceCtrl[15-13] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ //
+ // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system.
+ uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired.
+ //
+ // 0x0 = Use MR<0:17>_A0 for rank 0 channel A
+ // Use MR<0:17>_B0 for rank 0 channel B
+ // Use MR<0:17>_A1 for rank 1 channel A
+ // Use MR<0:17>_B1 for rank 1 channel B
+ //
+ // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks
+ //
+ // It is recommended in most LPDDR4 system configurations to set this to 1.
+ //
+ // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels.
+ //
+ uint8_t Lp4Quickboot; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In
+ // Enable Quickboot.
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D stages: Rd2D, Wr2D
+ //
+ // Reserved1A[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1A[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR14
+ // 2 = limit to +/-4 %VDDQ from MR14
+ // …
+ // 15 = limit to +/-30% VDDQ from MR14
+ uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // CA training option bit field
+ // [0] CA VREF Training
+ // 1 = Enable CA VREF Training
+ // 0 = Disable CA VREF Training
+ // [1-7] RFU must be zero
+ uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // X8 mode configuration:
+ // 0x0 = x16 configuration for all devices
+ // 0xF = x8 configuration for all devices
+ // All other values are RFU
+ uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+
+
+
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Total number of DQ bits enabled in PHY Channel A
+ uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel A.
+ //
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0}
+ uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0}
+ uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0}
+ uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0}
+ uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0}
+ uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0}
+ uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0}
+ uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0}
+ uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0}
+ uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0}
+ uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0}
+ uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0}
+ uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1}
+ uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1}
+ uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1}
+ uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1}
+ uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1}
+ uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1}
+ uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1}
+ uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1}
+ uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1}
+ uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1}
+ uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1}
+ uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1}
+ uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In
+ // Terminating Rank for CA bus on Channel A
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A
+
+ uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A
+
+ uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A
+
+ uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A
+
+ uint8_t Reserved4F; // Byte offset 0x4f, CSR Addr 0x54027, Direction=N/A
+
+ uint8_t Reserved50; // Byte offset 0x50, CSR Addr 0x54028, Direction=N/A
+
+ uint8_t Reserved51; // Byte offset 0x51, CSR Addr 0x54028, Direction=N/A
+
+ uint8_t Reserved52; // Byte offset 0x52, CSR Addr 0x54029, Direction=N/A
+
+ uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A
+
+ uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A
+
+ uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A
+
+ uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A
+
+ uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In
+ // Total number of DQ bits enabled in PHY Channel B
+ uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel B.
+ //
+ // 0x0 = No chip selects are populated with DRAM
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs01 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0}
+ uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0}
+ uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0}
+ uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0}
+ uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0}
+ uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0}
+ uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0}
+ uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0}
+ uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0}
+ uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0}
+ uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0}
+ uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0}
+ uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1}
+ uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1}
+ uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1}
+ uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1}
+ uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1}
+ uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1}
+ uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1}
+ uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1}
+ uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1}
+ uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1}
+ uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1}
+ uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1}
+ uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In
+ // Terminating Rank for CA bus on Channel B
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A
+
+ uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A
+
+ uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A
+
+ uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A
+
+ uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A
+
+ uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A
+
+} __attribute__ ((packed)) PMU_SMB_LPDDR4_1D_t;
diff --git a/arch/arm/include/asm/arch-s4/mnPmuSramMsgBlock_lpddr4_2d.h b/arch/arm/include/asm/arch-s4/mnPmuSramMsgBlock_lpddr4_2d.h
new file mode 100644
index 0000000..c6ab3d3
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/mnPmuSramMsgBlock_lpddr4_2d.h
@@ -0,0 +1,557 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief LPDDR4_2D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_LPDDR4_2D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Quick Rd2D during 1D Training
+ // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] Disable Boot Clock
+ // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended)
+ // 0x0 = Use Boot Frequency Clock
+ //
+ // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[7-6] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.25*VDDQ, set this field to 0x20.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Lp4 specific options for training.
+ //
+ // Bit fields:
+ //
+ // Lp4Misc[0] Enable dfi_reset_n
+ //
+ // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training.
+ // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin.
+ //
+ // 0x1 = Enables dfi_reset_n to control memreset after training.
+ // PHY Internal registers control memreset during training only.
+ // To ensure that no glitches occur on BP_MEMRESET at the end of training,
+ // The MC must drive dfi_reset_n=1'b1 _prior to starting training_
+ //
+ // Lp4Misc[7-1] RFU, must be zero
+ uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D.
+ //
+ // Reserved0E[0:3]: bitTimeControl
+ // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point.
+ // 0 = 288 bits per point (legacy behavior)
+ // 1 = 576 bits per point
+ // 2 = 1.125 kilobits per point
+ // …
+ // 15 = 9 megabits per point
+ //
+ // Reserved0E[4]: Exhaustive2D
+ // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior)
+ // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point.
+ //
+ // Reserved0E[5:7]: RFU, must be 0
+ uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = RFU, must be zero
+ // SequenceCtrl[2] = RFU, must be zero
+ // SequenceCtrl[3] = RFU, must be zero
+ // SequenceCtrl[4] = RFU, must be zero
+ // SequenceCtrl[5] = Run rd2D - 2d read dqs training
+ // SequenceCtrl[6] = Run wr2D - 2d write dq training
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = RFU, must be zero
+ // SequenceCtrl[9] = RFU, must be zero
+ // SequenceCtrl[11-10] = RFU, must be zero
+ // SequenceCtrl[12] = RFU, must be zero
+ // SequenceCtrl[15-13] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ //
+ // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system.
+ uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired.
+ //
+ // 0x0 = Use MR<0:17>_A0 for rank 0 channel A
+ // Use MR<0:17>_B0 for rank 0 channel B
+ // Use MR<0:17>_A1 for rank 1 channel A
+ // Use MR<0:17>_B1 for rank 1 channel B
+ //
+ // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks
+ //
+ // It is recommended in most LPDDR4 system configurations to set this to 1.
+ //
+ // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels.
+ //
+ uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A
+
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D stages: Rd2D, Wr2D
+ //
+ // Reserved1A[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1A[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR14
+ // 2 = limit to +/-4 %VDDQ from MR14
+ // …
+ // 15 = limit to +/-30% VDDQ from MR14
+ uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // CA training option bit field
+ // [0] CA VREF Setting
+ // 1 = Set MR12 from internal register
+ // 0 = Set MR12 from message block
+ // [1-7] RFU must be zero
+ uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // X8 mode configuration:
+ // 0x0 = x16 configuration for all devices
+ // 0xF = x8 configuration for all devices
+ // All other values are RFU
+ uint8_t RX2D_TrainOpt; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In
+ // Bit fields, if 2D read training enabled, then use these additional options:
+ // [0] DFE
+ // 1 = Run rx2D with DFE
+ // 0 = Run rx2D with DFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5-7] RFU, must be zero
+ //
+ uint8_t TX2D_TrainOpt; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Bit fields, if 2D write training is enabled, then use these additional options:
+ // [0] FFE
+ // 1 = Train tx2D with FFE
+ // 0 = Train tx2D with FFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5-7] RFU, must be zero
+ //
+ uint8_t Share2DVrefResult; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In
+ // Bitmap that designates the phy's vref source for every pstate
+ // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock.
+ // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training.
+ uint8_t Delay_Weight2D; // Byte offset 0x20, CSR Addr 0x54010, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye.
+ uint8_t Voltage_Weight2D; // Byte offset 0x21, CSR Addr 0x54010, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Total number of DQ bits enabled in PHY Channel A
+ uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel A.
+ //
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0}
+ uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0}
+ uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0}
+ uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0}
+ uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0}
+ uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0}
+ uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0}
+ uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0}
+ uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0}
+ uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0}
+ uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0}
+ uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0}
+ uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1}
+ uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1}
+ uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1}
+ uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1}
+ uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1}
+ uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1}
+ uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1}
+ uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1}
+ uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1}
+ uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1}
+ uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1}
+ uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1}
+ uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In
+ // Terminating Rank for CA bus on Channel A
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A
+
+ uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A
+
+ uint8_t TrainedVREFDQ_A0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // Trained DQ Vref setting for Ch A Rank 0
+ uint8_t TrainedVREFDQ_A1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // Trained DQ Vref setting for Ch A Rank 1
+ uint8_t RxClkDly_Margin_A0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_A0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_A0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_A0; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t RxClkDly_Margin_A1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_A1; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_A1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_A1; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In
+ // Total number of DQ bits enabled in PHY Channel B
+ uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel B.
+ //
+ // 0x0 = No chip selects are populated with DRAM
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs01 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0}
+ uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0}
+ uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0}
+ uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0}
+ uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0}
+ uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0}
+ uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0}
+ uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0}
+ uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0}
+ uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0}
+ uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0}
+ uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0}
+ uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1}
+ uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1}
+ uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1}
+ uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1}
+ uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1}
+ uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1}
+ uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1}
+ uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1}
+ uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1}
+ uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1}
+ uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1}
+ uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1}
+ uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In
+ // Terminating Rank for CA bus on Channel B
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t TrainedVREFDQ_B0; // Byte offset 0x80, CSR Addr 0x54040, Direction=Out
+ // Trained DQ Vref setting for Ch B Rank 0
+ uint8_t TrainedVREFDQ_B1; // Byte offset 0x81, CSR Addr 0x54040, Direction=Out
+ // Trained DQ Vref setting for Ch B Rank 1
+ uint8_t RxClkDly_Margin_B0; // Byte offset 0x82, CSR Addr 0x54041, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_B0; // Byte offset 0x83, CSR Addr 0x54041, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_B0; // Byte offset 0x84, CSR Addr 0x54042, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_B0; // Byte offset 0x85, CSR Addr 0x54042, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t RxClkDly_Margin_B1; // Byte offset 0x86, CSR Addr 0x54043, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_B1; // Byte offset 0x87, CSR Addr 0x54043, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_B1; // Byte offset 0x88, CSR Addr 0x54044, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_B1; // Byte offset 0x89, CSR Addr 0x54044, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+} __attribute__ ((packed)) PMU_SMB_LPDDR4_2D_t;
diff --git a/arch/arm/include/asm/arch-s4/nand.h b/arch/arm/include/asm/arch-s4/nand.h
new file mode 100644
index 0000000..91484ac
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/nand.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __NAND_H__
+#define __NAND_H__
+#include <asm/arch/cpu_config.h>
+
+#ifndef SD_EMMC_BASE_C
+#define SD_EMMC_BASE_C 0xd0074000
+#endif
+
+#define P_NAND_BASE (SD_EMMC_BASE_C | (1<<11))
+#define P_CLK_CNTL (volatile uint32_t *)(SD_EMMC_BASE_C)
+#define P_NAND_CMD (volatile uint32_t *)(P_NAND_BASE + 0x00)
+#define P_NAND_CFG (volatile uint32_t *)(P_NAND_BASE + 0x04)
+#define P_NAND_DADR (volatile uint32_t *)(P_NAND_BASE + 0x08)
+#define P_NAND_IADR (volatile uint32_t *)(P_NAND_BASE + 0x0c)
+#define P_NAND_BUF (volatile uint32_t *)(P_NAND_BASE + 0x10)
+#define P_NAND_INFO (volatile uint32_t *)(P_NAND_BASE + 0x14)
+#define P_NAND_DC (volatile uint32_t *)(P_NAND_BASE + 0x18)
+#define P_NAND_ADR (volatile uint32_t *)(P_NAND_BASE + 0x1c)
+#define P_NAND_DL (volatile uint32_t *)(P_NAND_BASE + 0x20)
+#define P_NAND_DH (volatile uint32_t *)(P_NAND_BASE + 0x24)
+#define P_NAND_CADR (volatile uint32_t *)(P_NAND_BASE + 0x28)
+#define P_NAND_SADR (volatile uint32_t *)(P_NAND_BASE + 0x2c)
+
+#define CEF (0xf<<10)
+#define CE0 (0xe<<10)
+#define CE1 (0xd<<10)
+#define CE2 (0xb<<10)
+#define CE3 (0x7<<10)
+
+#define IO4 ((0xe<<10)|(1<<18))
+#define IO5 ((0xd<<10)|(1<<18))
+#define IO6 ((0xb<<10)|(1<<18))
+
+#define CLE (0x5<<14)
+#define ALE (0x6<<14)
+#define DWR (0x4<<14)
+#define DRD (0x8<<14)
+#define IDLE (0xc<<14)
+#define RB (1<<20)
+
+#define M2N ((0<<17) | (2<<20) | (1<<19))
+#define N2M ((1<<17) | (2<<20) | (1<<19))
+#define STS ((3<<17) | (2<<20))
+#define ADL ((0<<16) | (3<<20))
+#define ADH ((1<<16) | (3<<20))
+#define AIL ((2<<16) | (3<<20))
+#define AIH ((3<<16) | (3<<20))
+#define ASL ((4<<16) | (3<<20))
+#define ASH ((5<<16) | (3<<20))
+#define SEED ((8<<16) | (3<<20))
+
+// NAND Flash Manufacturer ID Codes
+#define NAND_MFR_TOSHIBA 0x98
+#define NAND_MFR_SAMSUNG 0xec
+#define NAND_MFR_FUJITSU 0x04
+#define NAND_MFR_NATIONAL 0x8f
+#define NAND_MFR_RENESAS 0x07
+#define NAND_MFR_STMICRO 0x20
+#define NAND_MFR_HYNIX 0xad
+#define NAND_MFR_MICRON 0x2c
+#define NAND_MFR_AMD 0x01
+#define NAND_MFR_INTEL 0x89
+#define NAND_MFR_SANDISK 0x45
+#define NAND_MFR_USER 0x100
+#define NAND_MFR_EFUSE 0x101
+
+typedef struct nand_setup {
+ union {
+ uint32_t d32;
+ struct {
+ unsigned cmd:22;
+ unsigned large_page:1; // 22
+ unsigned no_rb:1; // 23 from efuse
+ unsigned a2:1; // 24
+ unsigned reserved25:1; // 25
+ unsigned page_list:1; // 26
+ unsigned sync_mode:2; // 27 from efuse
+ unsigned size:2; // 29 from efuse
+ unsigned active:1; // 31
+ } b;
+ } cfg;
+ uint16_t id;
+ uint16_t max; // id:0x100 user, max:0 disable.
+} nand_setup_t;
+
+typedef struct _nand_cmd{
+ unsigned char type;
+ unsigned char val;
+} nand_cmd_t;
+
+typedef struct _ext_info{
+ uint32_t read_info; //nand_read_info;
+ uint32_t new_type; //new_nand_type;
+ uint32_t page_per_blk; //pages_in_block;
+ uint32_t xlc; //slc=1, mlc=2, tlc=3.
+ uint32_t rsv1[5];
+} ext_info_t;
+
+typedef struct _nand_page0 {
+ nand_setup_t nand_setup; //8
+ unsigned char page_list[16]; //16
+ nand_cmd_t retry_usr[32]; //64 (32 cmd max I/F)
+ ext_info_t ext_info; //64
+} nand_page0_t; //384 bytes max.
+
+//#define NAND_PAGE0_BUF BL1_NAND_BUFF
+#define NAND_PAGE0_BUF (0x1800000)
+#define NAND_PAGE_LIST (NAND_PAGE0_BUF + sizeof(nand_setup_t))
+#define NAND_RETRY_USER (NAND_PAGE_LIST + 16)
+#define NAND_INFO_BUF (NAND_PAGE0_BUF + 512)
+#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1)
+//#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1)
+
+#define ERROR_MOD(mod,num) ((uint32_t)(((mod<<6)|num)))
+#define ERROR_NAND_TIMEOUT ERROR_MOD(2,1) //
+#define ERROR_NAND_ECC ERROR_MOD(2,2) //
+#define ERROR_NAND_MAGIC_WORD ERROR_MOD(2,3) //
+#define ERROR_NAND_INIT_READ ERROR_MOD(2,4) //
+#define ERROR_NAND_BLANK_PAGE ERROR_MOD(2,5) //
+#define ERROR_NAND_UNALIGN_SRC ERROR_MOD(2,6) //
+
+#define NAND_SECTOR_SIZE (512)
+#define NAND_MAX_PAGESIZE (0x4000) //16K
+#define SRC_ALIGN_SIZE (NAND_MAX_PAGESIZE)
+
+#define INFO_BYTE_PER_ECCPAGE (8)
+uint32_t nfio_init(void);
+uint32_t nf_read(uint32_t boot_device, uint32_t src, uint32_t des, uint32_t size);
+#endif /* __NAND_H__ */
+
diff --git a/arch/arm/include/asm/arch-s4/oscring.h b/arch/arm/include/asm/arch-s4/oscring.h
new file mode 100644
index 0000000..0f5cba1
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/oscring.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __OSCRING_H__
+#define __OSCRING_H__
+
+#define OSCRING_CTL_REG0 SYSCTRL_OSC_RING_CTRL0
+#define OSCRING_CTL_DATA0 0x55555555 /*0:25*/
+#define OSCRING_CTL_REG1 SYSCTRL_OSC_RING_CTRL1
+#define OSCRING_CTL_DATA1 0x85555555 /*0:7*/
+
+#define RING_PWM_VCCK PWMIJ_PWM_B
+#define RING_PWM_EE PWMGH_PWM_B
+
+int ring_msr(int index);
+#endif
diff --git a/arch/arm/include/asm/arch-s4/pinctrl_init.h b/arch/arm/include/asm/arch-s4/pinctrl_init.h
new file mode 100644
index 0000000..cfbc42a
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/pinctrl_init.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _MESON_PINCTRL_INIT_H_
+#define _MESON_PINCTRL_INIT_H_
+
+#define PIN_CONTROLLER_NUM 2
+extern int pinctrl_devices_active(int pinctrl_num);
+
+#endif /* _MESON_PINCTRL_INIT_H_ */
diff --git a/arch/arm/include/asm/arch-s4/pll.h b/arch/arm/include/asm/arch-s4/pll.h
new file mode 100644
index 0000000..da9549b
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/pll.h
@@ -0,0 +1,181 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __PLL_H
+#define __PLL_H
+
+#define PLL_TEST_SYS_TOTAL 2
+#define PLL_TEST_HIFI_TOTAL 2
+#define PLL_TEST_GP0_TOTAL 2
+#define PLL_TEST_GP1_TOTAL 2
+#define PLL_TEST_HDMI_TOTAL 2
+
+typedef struct sys_pll_set_s {
+ unsigned int cpu_clk;
+ unsigned int pll_cntl;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+}sys_pll_set_t;
+
+typedef struct sys_pll_cfg_s {
+ sys_pll_set_t sys_pll[PLL_TEST_SYS_TOTAL];
+}sys_pll_cfg_t;
+
+typedef struct hdmi_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+}hdmi_pll_set_t;
+
+typedef struct hdmi_pll_cfg_s {
+ hdmi_pll_set_t hdmi_pll[PLL_TEST_HDMI_TOTAL];
+}hdmi_pll_cfg_t;
+
+typedef struct gpll_rate_table_s {
+ unsigned int rate;
+ unsigned int m;
+ unsigned int n;
+ unsigned int od;
+}gpll_rate_table_t;
+
+typedef struct hifipll_rate_table_s {
+ unsigned int rate;
+ unsigned int m;
+ unsigned int n;
+ unsigned int od;
+}hifipll_rate_table_t;
+
+typedef struct gp0_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+}gp0_pll_set_t;
+
+typedef struct gp0_pll_cfg_s {
+ gp0_pll_set_t gp0_pll[PLL_TEST_GP0_TOTAL];
+}gp0_pll_cfg_t;
+
+typedef struct gp1_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+}gp1_pll_set_t;
+
+typedef struct gp1_pll_cfg_s {
+ gp1_pll_set_t gp1_pll[PLL_TEST_GP1_TOTAL];
+}gp1_pll_cfg_t;
+
+typedef struct hifi_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+}hifi_pll_set_t;
+
+typedef struct hifi_pll_cfg_s {
+ hifi_pll_set_t hifi_pll[PLL_TEST_HIFI_TOTAL];
+}hifi_pll_cfg_t;
+
+typedef struct pcie_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+}pcie_pll_set_t;
+
+typedef struct mpll_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+ unsigned int pll_cntl7;
+ unsigned int pll_cntl8;
+}mpll_pll_set_t;
+
+typedef struct ethphy_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+}ethphy_pll_set_t;
+
+typedef struct usbphy_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+ unsigned int pll_cntl7;
+}usbphy_pll_set_t;
+
+struct pciepll_rate_table {
+ u16 rate;
+ u16 m;
+ u16 n;
+ u16 od;
+ u16 od2;
+ u16 frac;
+};
+
+#define PLL_RATE(_r, _m, _n, _od) \
+ { \
+ .rate = (_r), \
+ .m = (_m), \
+ .n = (_n), \
+ .od = (_od), \
+ } \
+
+enum pll_enum {
+ PLL_SYS = 0,
+ PLL_FIX,
+ PLL_DDR,
+ PLL_HDMI,
+ PLL_GP0,
+ PLL_HIFI,
+ PLL_PCIE,
+ PLL_GP1,
+ PLL_USBPHY,
+ PLL_MPLL,
+ PLL_ENUM,
+
+};
+
+int pll_test(int argc, char * const argv[]);
+
+#endif /* __PLL_H */
diff --git a/arch/arm/include/asm/arch-s4/pwr_ctrl.h b/arch/arm/include/asm/arch-s4/pwr_ctrl.h
new file mode 100644
index 0000000..96339b1
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/pwr_ctrl.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _PWRC_H_
+#define _PWRC_H_
+
+#define PWR_ON 1
+#define PWR_OFF 0
+
+#define PM_DOS_HEVC 0
+#define PM_DOS_VDEC 1
+#define PM_VPU_HDMI 2
+#define PM_USB_COMB 3
+#define PM_GE2D 4
+#define PM_ETH 5
+#define PM_DEMOD 6
+#define PM_AUDIO 7
+
+#define PM_MAX 8
+//static int pm_max = 8;
+/*
+char* domain_name[] =
+{
+ "PM_DOS_HEVC",
+ "PM_DOS_VDEC",
+ "PM_VPU_HDMI",
+ "PM_USB_COMB",
+ "PM_GE2D",
+ "PM_ETH",
+ "PM_DEMOD",
+ "PM_AUDIO",
+};
+*/
+unsigned long pwr_ctrl_psci_smc(unsigned int power_domain, bool power_control);
+#endif
diff --git a/arch/arm/include/asm/arch-s4/reboot.h b/arch/arm/include/asm/arch-s4/reboot.h
new file mode 100644
index 0000000..e7fb8bd
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/reboot.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __REBOOT_H
+#define __REBOOT_H
+
+#include "soc_def.h"
+
+/*
+Reboot reason AND corresponding env setting:
+0: Cold boot cold_boot
+1: Normal boot normal
+2: Factory reset factory_reset
+3: Upgrade system update
+4: Fastboot fastboot
+5: Suspend suspend_off
+6: Hibernate hibernate
+7: Fastboot Bootloader bootloader
+8: Shutdown reboot shutdown_reboot
+9: RPMBP reboot rpmbp
+10: quiescent reboot quiescent reboot
+11 : rescueparty rollback in AB mode
+12: Kernel panic kernel_panic
+13: Watchdog reboot watchdog_reboot
+14: quiescent recovery reboot quiescent recovery
+15: reserved
+*/
+#define AMLOGIC_COLD_BOOT 0
+#define AMLOGIC_NORMAL_BOOT 1
+#define AMLOGIC_FACTORY_RESET_REBOOT 2
+#define AMLOGIC_UPDATE_REBOOT 3
+#define AMLOGIC_FASTBOOT_REBOOT 4
+#define AMLOGIC_SUSPEND_REBOOT 5
+#define AMLOGIC_HIBERNATE_REBOOT 6
+#define AMLOGIC_BOOTLOADER_REBOOT 7 /* fastboot bootloader */
+#define AMLOGIC_SHUTDOWN_REBOOT 8
+#define AMLOGIC_RPMBP_REBOOT 9
+#define AMLOGIC_QUIESCENT_REBOOT 10
+#define AMLOGIC_RESCUEPARTY_REBOOT 11
+#define AMLOGIC_KERNEL_PANIC 12
+#define AMLOGIC_WATCHDOG_REBOOT 13
+#define AMLOGIC_RECOVERY_QUIESCENT_REBOOT 14
+
+/*
+old version env
+0x01010101, normal
+0x02020202, factory_reset
+0x03030303, update
+0x09090909, usb_burning
+0x0b0b0b0b, suspend_off
+*/
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-s4/register.h b/arch/arm/include/asm/arch-s4/register.h
new file mode 100644
index 0000000..7d69743
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/register.h
@@ -0,0 +1,30944 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifdef REGISTER_H
+#else
+#define REGISTER_H
+
+
+#if 0
+#ifndef VERIFICATION
+ #define Wr64(addr, data) *(volatile uint64_t *)(addr)=(data)
+ #define Rd64(addr) *(volatile uint64_t *)(addr)
+ #define Wr(addr, data) *(volatile uint32_t *)(addr)=(data)
+ #define Rd(addr) *(volatile uint32_t *)(addr)
+ #define Wr_reg_bits(reg, val, start, len) \
+ Wr(reg, ((Rd(reg) & ~(((1L<<(len))-1)<<(start))) | ((uint32_t)(val) << (start))))
+#else
+ #include "dpi.h"
+#endif
+#endif
+
+//
+// Reading file: ./REG_LIST_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_sec.vh
+//
+//`define DMC_SEC_REG_BASE 32'hfe037000
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe037000
+// -----------------------------------------------
+//DMC use 15bits ID to identify the input ports and ID.
+// bit 14:10.
+// 0 : CPU and MALI. Mali and cpu will be seperated to 2 channel. CPU traffic will be assigned to ID = 0. Mali traffic will assigned to ID =1.
+// 1 : Mali
+// 2 : PCIE
+// 3 : HDMI.
+// 4 : HEVC_F.
+// 5 : TEST.
+// 6 : USB
+// 7 : Device.
+// 8 : HEVC_B
+// 9 : WAVE.
+//10 : CPU, GPU and NNA. CPU will assign to ID = 13. GPU and NNA still in ID = 10. we use the GPU/NNA ID to cotrol the secure control.
+//11 : GDC.
+//12 : ISP.
+// 15:13 Not used.
+// 16: VPU read 0.
+// 17: VPU read 1.
+// 18: VPU read 2.
+// 19: VPU write 0.
+// 20: VPU write 1.
+// 21: VDEC.
+// 22: HCODEC.
+// 23: ge2d.
+//control bit for SubID functions for all the input.
+// ARM 2 bit. HPROT[1] == 0 : SECURE CPU; HPROT[1] == 1 : NONSEC CPU.
+// GPU 2 bit. HPROT[2] == 1 : SECURE GPU; HPROT[2] == 0 : NONSEC GPU access;
+// PCIE 1 bit.
+// HDCP 2 bits. ID AR/AWID[0].
+// HEVC_F 9 bits. dc_id_in[7:4] == 0 : for IMEM. dc_id_in[7:4] == 1 : for PMEM. dc_id_in[7:5] != 0 for other 7 types.
+// TEST 1 type.
+// USB 1 type.
+// DEVICE AO_CPU : AR/AWID[7:3] == 4'ha. 4bits control. use AR/WID[1:0].
+// DMA : AR/AWID[7:3] == 4'h2. 8bits control use AR/WID[3:1].
+// AUDIO : AR/AWID[7:3] == 4'h6. 16bits control. use AR/AWID[3:0].
+// the others total 13 bits use AR/AWID[7:3] - (4'ha, 4'h2 and 4'h6).
+//VPU read port 0 and read port 2. total 16bits. use ARID[3:0] (number 0~15).
+//VPU read port 1. total 8bits. use ARID[3:0] (number 0~7).
+//VPU write port 0 total 16bits. use AWID[3:0] (number 0~16).
+//VPU write port 1 total 8bits. use AWID[3:0] (number 0~7).
+//VDEC total 16bits. use AR/WID[5:2]
+//HCODEC total 16bits. use AR/WID[5:2].
+//GE2D. total 3bits. 2 read bits, check ARID[0]. 1 write bit. AWID dont care.
+//HEVC_B. 8 bits. use AR/WID[7:5].
+//NNA. AR/WPROT[1] == 0: secure access. AR/WPROT[1] == 1: None secure access.
+//GDC. 4bits for AR/AWID[5:4]. actuall for write there's only 1 ID. AWID[5:4] always 0.
+//ISP. one channel.
+//there's total 16 ranges in the whole memory range.
+// 15 ranges can be defined in 64kbyte boundary start address and end address.
+// the 16th range is all other space not defined by 15 ranges.
+// Each range can be enabled or disabled and each range use security level bit to select key to do data scramble.
+// The ranges can be overlapped or crossover. But from 0 to 15 ranges, the earlier has higher priority.
+#define DMC_SEC_RANGE0_CTRL ((0x0000 << 2) + 0xfe037000)
+ //default : 32'hffff0000
+ //bit 31:16 | 0 | range0_eda | range 0 end address higher 16bits.
+ //bit 15:0 | 0 | range0_sta | range 0 start address higher 16bits.
+#define DMC_SEC_RANGE0_CTRL1 ((0x0001 << 2) + 0xfe037000)
+ //default : 32'h00000003
+ //bit 7:5 | 0 | range0_secrity_level | range0 secruity level for DMA and DEMUX only.
+ //bit 4 | 0 | range0_prot_en | range0 allow protect monitor function. 1: allowed. 0: not allowed.
+ //bit 3 | 0 | range0_local_des_en | range0 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES_EN to decide this region data describle enable or not.
+ //bit 2 | 0 | range0_lock | lock range 0 registers. write 1 to lock range 0 register. can't change anymore.
+ //bit 1 | 0 | range0_key_sel | range 0 data describle key selection. 1 : key1. 0 : key0.
+ //bit 0 | 0 | range0_en | range 0 enable bit. 1 : enable, 0 : disable.
+#define DMC_SEC_RANGE1_CTRL ((0x0002 << 2) + 0xfe037000)
+ //default : 32'hffffffff
+ //bit 31:16 | 0 | range1_eda | range 1 end address higher 16bits.
+ //bit 15:0 | 0 | range1_sta | range 1 start address higher 16bits.
+#define DMC_SEC_RANGE1_CTRL1 ((0x0003 << 2) + 0xfe037000)
+ //default : 0
+ //bit 7:5 | 0 | range1_secrity_level | range1 secruity level for DMA and DEMUX only.
+ //bit 4 | 0 | range1_prot_en | range1 allow protect monitor function. 1: allowed. 0: not allowed.
+ //bit 3 | 0 | range1_local_des_en | range1 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES_EN to decide this region data describle enable or not.
+ //bit 2 | 0 | range1_lock | lock range 1 registers. write 1 to lock range 1 register. can't change anymore.
+ //bit 1 | 0 | range1_key_sel | range 1 data describle key selection. 1 : key1. 1 : key0.
+ //bit 0 | 0 | range1_en | range 0 enable bit. 1 : enable, 0 : disable.
+#define DMC_SEC_RANGE2_CTRL ((0x0004 << 2) + 0xfe037000)
+ //default : 32'hffffffff
+ //bit 31:16 | 0 | range2_eda | range 2 end address higher 16bits.
+ //bit 15:0 | 0 | range2_sta | range 2 start address higher 16bits.
+#define DMC_SEC_RANGE2_CTRL1 ((0x0005 << 2) + 0xfe037000)
+ //default : 0
+ //bit 7:5 | 0 | range2_secrity_level | range2 secruity level for DMA and DEMUX only.
+ //bit 4 | 0 | range2_prot_en | range2 allow protect monitor function. 1: allowed. 0: not allowed.
+ //bit 3 | 0 | range2_local_des_en | range2 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES to decide this region data describle enable or not.
+ //bit 2 | 0 | range2_lock | lock range 2 registers. write 1 to lock range 2 register. can't change anymore.
+ //bit 1 | 0 | range2_key_sel | range 2 data describle key selection. 1 : key1. 1 : key0.
+ //bit 0 | 0 | range2_en | range 2 enable bit. 1 : enable, 0 : disable.
+#define DMC_SEC_RANGE3_CTRL ((0x0006 << 2) + 0xfe037000)
+ //default : 32'hffffffff
+ //bit 31:16 | 0 | range3_eda | range 3 end address higher 16bits.
+ //bit 15:0 | 0 | range3_sta | range 3 start address higher 16bits.
+#define DMC_SEC_RANGE3_CTRL1 ((0x0007 << 2) + 0xfe037000)
+ //default : 0
+ //bit 7:5 | 0 | range3_secrity_level | range3 secruity level for DMA and DEMUX only.
+ //bit 4 | 0 | range3_prot_en | range3 allow protect monitor function. 1: allowed. 0: not allowed.
+ //bit 3 | 0 | range3_local_des_en | range3 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES to decide this region data describle enable or not.
+ //bit 2 | 0 | range3_lock | lock range 3 registers. write 1 to lock range 3 related registers. can't change anymore.
+ //bit 1 | 0 | range3_key_sel | range 3 data describle key selection. 1 : key1. 1 : key0.
+ //bit 0 | 0 | range3_en | range 3 enable bit. 1 : enable, 0 : disable.
+#define DMC_SEC_RANGE4_CTRL ((0x0008 << 2) + 0xfe037000)
+ //default : 32'hffffffff
+ //bit 31:16 | 0 | range4_eda | range 4 end address higher 16bits.
+ //bit 15:0 | 0 | range4_sta | range 4 start address higher 16bits.
+#define DMC_SEC_RANGE4_CTRL1 ((0x0009 << 2) + 0xfe037000)
+ //default : 0
+ //bit 7:5 | 0 | range4_secrity_level | range4 secruity level for DMA and DEMUX only.
+ //bit 4 | 0 | range4_prot_en | range4 allow protect monitor function. 1: allowed. 0: not allowed.
+ //bit 3 | 0 | range4_local_des_en | range4 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES to decide this region data describle enable or not.
+ //bit 2 | 0 | range4_lock | lock range 4 registers. write 1 to lock range 4 related registers. can't change anymore.
+ //bit 1 | 0 | range4_key_sel | range 4 data describle key selection. 1 : key1. 1 : key0.
+ //bit 0 | 0 | range4_en | range 4 enable bit. 1 : enable, 0 : disable.
+#define DMC_SEC_RANGE5_CTRL ((0x000a << 2) + 0xfe037000)
+#define DMC_SEC_RANGE5_CTRL1 ((0x000b << 2) + 0xfe037000)
+#define DMC_SEC_RANGE6_CTRL ((0x000c << 2) + 0xfe037000)
+#define DMC_SEC_RANGE6_CTRL1 ((0x000d << 2) + 0xfe037000)
+#define DMC_SEC_RANGE7_CTRL ((0x000e << 2) + 0xfe037000)
+#define DMC_SEC_RANGE7_CTRL1 ((0x000f << 2) + 0xfe037000)
+#define DMC_SEC_RANGE8_CTRL ((0x0010 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE8_CTRL1 ((0x0011 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE9_CTRL ((0x0012 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE9_CTRL1 ((0x0013 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE10_CTRL ((0x0014 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE10_CTRL1 ((0x0015 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE11_CTRL ((0x0016 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE11_CTRL1 ((0x0017 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE12_CTRL ((0x0018 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE12_CTRL1 ((0x0019 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE13_CTRL ((0x001a << 2) + 0xfe037000)
+#define DMC_SEC_RANGE13_CTRL1 ((0x001b << 2) + 0xfe037000)
+#define DMC_SEC_RANGE14_CTRL ((0x001c << 2) + 0xfe037000)
+#define DMC_SEC_RANGE14_CTRL1 ((0x001d << 2) + 0xfe037000)
+#define DMC_SEC_RANGE15_CTRL1 ((0x001f << 2) + 0xfe037000)
+ //default : 0
+ //bit 7:5 | 0 | range1_secrity_level | range1 secruity level for DMC and DEMUX only.
+ //bit 4 | 0 | range1_prot_en | range1 allow protect monitor function. 1: allowed. 0: not allowed.
+ //bit 3 | 0 | range1_local_des_en | range1 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES_EN to decide this region data describle enable or not.
+ //bit 2 | 0 | range1_lock | lock range 1 registers. write 1 to lock range 1 register. can't change anymore.
+ //bit 1 | 0 | range1_key_sel | range 1 data describle key selection. 1 : key1. 1 : key0.
+ //bit 0 | 0 | not used. range 15 is always enabled.
+//per range per sub ID access enable.
+#define DMC_SEC_RANGE0_RID_CTRL0 ((0x0020 << 2) + 0xfe037000)
+ //default : 0
+ //range_rd_sid_en[31:0];
+#define DMC_SEC_RANGE0_RID_CTRL1 ((0x0021 << 2) + 0xfe037000)
+ //default : 0
+ //range_rd_sid_en[63:32];
+#define DMC_SEC_RANGE0_RID_CTRL2 ((0x0022 << 2) + 0xfe037000)
+ //default : 0
+ //range_rd_sid_en[95:64];
+#define DMC_SEC_RANGE0_RID_CTRL3 ((0x0023 << 2) + 0xfe037000)
+ //default : 0
+ //range_rd_sid_en[127:96];
+#define DMC_SEC_RANGE0_RID_CTRL4 ((0x0024 << 2) + 0xfe037000)
+ //default : 0 not used in
+#define DMC_SEC_RANGE1_RID_CTRL0 ((0x0026 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE1_RID_CTRL1 ((0x0027 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE1_RID_CTRL2 ((0x0028 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE1_RID_CTRL3 ((0x0029 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE1_RID_CTRL4 ((0x002a << 2) + 0xfe037000)
+#define DMC_SEC_RANGE2_RID_CTRL0 ((0x002c << 2) + 0xfe037000)
+#define DMC_SEC_RANGE2_RID_CTRL1 ((0x002d << 2) + 0xfe037000)
+#define DMC_SEC_RANGE2_RID_CTRL2 ((0x002e << 2) + 0xfe037000)
+#define DMC_SEC_RANGE2_RID_CTRL3 ((0x002f << 2) + 0xfe037000)
+#define DMC_SEC_RANGE2_RID_CTRL4 ((0x0030 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE3_RID_CTRL0 ((0x0032 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE3_RID_CTRL1 ((0x0033 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE3_RID_CTRL2 ((0x0034 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE3_RID_CTRL3 ((0x0035 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE3_RID_CTRL4 ((0x0036 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE4_RID_CTRL0 ((0x0038 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE4_RID_CTRL1 ((0x0039 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE4_RID_CTRL2 ((0x003a << 2) + 0xfe037000)
+#define DMC_SEC_RANGE4_RID_CTRL3 ((0x003b << 2) + 0xfe037000)
+#define DMC_SEC_RANGE4_RID_CTRL4 ((0x003c << 2) + 0xfe037000)
+#define DMC_SEC_RANGE5_RID_CTRL0 ((0x003e << 2) + 0xfe037000)
+#define DMC_SEC_RANGE5_RID_CTRL1 ((0x003f << 2) + 0xfe037000)
+#define DMC_SEC_RANGE5_RID_CTRL2 ((0x0040 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE5_RID_CTRL3 ((0x0041 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE5_RID_CTRL4 ((0x0042 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE6_RID_CTRL0 ((0x0044 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE6_RID_CTRL1 ((0x0045 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE6_RID_CTRL2 ((0x0046 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE6_RID_CTRL3 ((0x0047 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE6_RID_CTRL4 ((0x0048 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE7_RID_CTRL0 ((0x004a << 2) + 0xfe037000)
+#define DMC_SEC_RANGE7_RID_CTRL1 ((0x004b << 2) + 0xfe037000)
+#define DMC_SEC_RANGE7_RID_CTRL2 ((0x004c << 2) + 0xfe037000)
+#define DMC_SEC_RANGE7_RID_CTRL3 ((0x004d << 2) + 0xfe037000)
+#define DMC_SEC_RANGE7_RID_CTRL4 ((0x004e << 2) + 0xfe037000)
+#define DMC_SEC_RANGE8_RID_CTRL0 ((0x0050 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE8_RID_CTRL1 ((0x0051 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE8_RID_CTRL2 ((0x0052 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE8_RID_CTRL3 ((0x0053 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE8_RID_CTRL4 ((0x0054 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE9_RID_CTRL0 ((0x0056 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE9_RID_CTRL1 ((0x0057 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE9_RID_CTRL2 ((0x0058 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE9_RID_CTRL3 ((0x0059 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE9_RID_CTRL4 ((0x005a << 2) + 0xfe037000)
+#define DMC_SEC_RANGE10_RID_CTRL0 ((0x005c << 2) + 0xfe037000)
+#define DMC_SEC_RANGE10_RID_CTRL1 ((0x005d << 2) + 0xfe037000)
+#define DMC_SEC_RANGE10_RID_CTRL2 ((0x005e << 2) + 0xfe037000)
+#define DMC_SEC_RANGE10_RID_CTRL3 ((0x005f << 2) + 0xfe037000)
+#define DMC_SEC_RANGE10_RID_CTRL4 ((0x0060 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE11_RID_CTRL0 ((0x0062 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE11_RID_CTRL1 ((0x0063 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE11_RID_CTRL2 ((0x0064 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE11_RID_CTRL3 ((0x0065 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE11_RID_CTRL4 ((0x0066 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE12_RID_CTRL0 ((0x0068 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE12_RID_CTRL1 ((0x0069 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE12_RID_CTRL2 ((0x006a << 2) + 0xfe037000)
+#define DMC_SEC_RANGE12_RID_CTRL3 ((0x006b << 2) + 0xfe037000)
+#define DMC_SEC_RANGE12_RID_CTRL4 ((0x006c << 2) + 0xfe037000)
+#define DMC_SEC_RANGE13_RID_CTRL0 ((0x006e << 2) + 0xfe037000)
+#define DMC_SEC_RANGE13_RID_CTRL1 ((0x006f << 2) + 0xfe037000)
+#define DMC_SEC_RANGE13_RID_CTRL2 ((0x0070 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE13_RID_CTRL3 ((0x0071 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE13_RID_CTRL4 ((0x0072 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE14_RID_CTRL0 ((0x0074 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE14_RID_CTRL1 ((0x0075 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE14_RID_CTRL2 ((0x0076 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE14_RID_CTRL3 ((0x0077 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE14_RID_CTRL4 ((0x0078 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE15_RID_CTRL0 ((0x007a << 2) + 0xfe037000)
+#define DMC_SEC_RANGE15_RID_CTRL1 ((0x007b << 2) + 0xfe037000)
+#define DMC_SEC_RANGE15_RID_CTRL2 ((0x007c << 2) + 0xfe037000)
+#define DMC_SEC_RANGE15_RID_CTRL3 ((0x007d << 2) + 0xfe037000)
+#define DMC_SEC_RANGE15_RID_CTRL4 ((0x007e << 2) + 0xfe037000)
+//per range per sub ID access enable.
+#define DMC_SEC_RANGE0_WID_CTRL0 ((0x0080 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE0_WID_CTRL1 ((0x0081 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE0_WID_CTRL2 ((0x0082 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE0_WID_CTRL3 ((0x0083 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE0_WID_CTRL4 ((0x0084 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE1_WID_CTRL0 ((0x0086 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE1_WID_CTRL1 ((0x0087 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE1_WID_CTRL2 ((0x0088 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE1_WID_CTRL3 ((0x0089 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE1_WID_CTRL4 ((0x008a << 2) + 0xfe037000)
+#define DMC_SEC_RANGE2_WID_CTRL0 ((0x008c << 2) + 0xfe037000)
+#define DMC_SEC_RANGE2_WID_CTRL1 ((0x008d << 2) + 0xfe037000)
+#define DMC_SEC_RANGE2_WID_CTRL2 ((0x008e << 2) + 0xfe037000)
+#define DMC_SEC_RANGE2_WID_CTRL3 ((0x008f << 2) + 0xfe037000)
+#define DMC_SEC_RANGE2_WID_CTRL4 ((0x0090 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE3_WID_CTRL0 ((0x0092 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE3_WID_CTRL1 ((0x0093 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE3_WID_CTRL2 ((0x0094 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE3_WID_CTRL3 ((0x0095 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE3_WID_CTRL4 ((0x0096 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE4_WID_CTRL0 ((0x0098 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE4_WID_CTRL1 ((0x0099 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE4_WID_CTRL2 ((0x009a << 2) + 0xfe037000)
+#define DMC_SEC_RANGE4_WID_CTRL3 ((0x009b << 2) + 0xfe037000)
+#define DMC_SEC_RANGE4_WID_CTRL4 ((0x009c << 2) + 0xfe037000)
+#define DMC_SEC_RANGE5_WID_CTRL0 ((0x009e << 2) + 0xfe037000)
+#define DMC_SEC_RANGE5_WID_CTRL1 ((0x009f << 2) + 0xfe037000)
+#define DMC_SEC_RANGE5_WID_CTRL2 ((0x00a0 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE5_WID_CTRL3 ((0x00a1 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE5_WID_CTRL4 ((0x00a2 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE6_WID_CTRL0 ((0x00a4 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE6_WID_CTRL1 ((0x00a5 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE6_WID_CTRL2 ((0x00a6 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE6_WID_CTRL3 ((0x00a7 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE6_WID_CTRL4 ((0x00a8 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE7_WID_CTRL0 ((0x00aa << 2) + 0xfe037000)
+#define DMC_SEC_RANGE7_WID_CTRL1 ((0x00ab << 2) + 0xfe037000)
+#define DMC_SEC_RANGE7_WID_CTRL2 ((0x00ac << 2) + 0xfe037000)
+#define DMC_SEC_RANGE7_WID_CTRL3 ((0x00ad << 2) + 0xfe037000)
+#define DMC_SEC_RANGE7_WID_CTRL4 ((0x00ae << 2) + 0xfe037000)
+#define DMC_SEC_RANGE8_WID_CTRL0 ((0x00b0 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE8_WID_CTRL1 ((0x00b1 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE8_WID_CTRL2 ((0x00b2 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE8_WID_CTRL3 ((0x00b3 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE8_WID_CTRL4 ((0x00b4 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE9_WID_CTRL0 ((0x00b6 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE9_WID_CTRL1 ((0x00b7 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE9_WID_CTRL2 ((0x00b8 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE9_WID_CTRL3 ((0x00b9 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE9_WID_CTRL4 ((0x00ba << 2) + 0xfe037000)
+#define DMC_SEC_RANGE10_WID_CTRL0 ((0x00bc << 2) + 0xfe037000)
+#define DMC_SEC_RANGE10_WID_CTRL1 ((0x00bd << 2) + 0xfe037000)
+#define DMC_SEC_RANGE10_WID_CTRL2 ((0x00be << 2) + 0xfe037000)
+#define DMC_SEC_RANGE10_WID_CTRL3 ((0x00bf << 2) + 0xfe037000)
+#define DMC_SEC_RANGE10_WID_CTRL4 ((0x00c0 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE11_WID_CTRL0 ((0x00c2 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE11_WID_CTRL1 ((0x00c3 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE11_WID_CTRL2 ((0x00c4 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE11_WID_CTRL3 ((0x00c5 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE11_WID_CTRL4 ((0x00c6 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE12_WID_CTRL0 ((0x00c8 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE12_WID_CTRL1 ((0x00c9 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE12_WID_CTRL2 ((0x00ca << 2) + 0xfe037000)
+#define DMC_SEC_RANGE12_WID_CTRL3 ((0x00cb << 2) + 0xfe037000)
+#define DMC_SEC_RANGE12_WID_CTRL4 ((0x00cc << 2) + 0xfe037000)
+#define DMC_SEC_RANGE13_WID_CTRL0 ((0x00ce << 2) + 0xfe037000)
+#define DMC_SEC_RANGE13_WID_CTRL1 ((0x00cf << 2) + 0xfe037000)
+#define DMC_SEC_RANGE13_WID_CTRL2 ((0x00d0 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE13_WID_CTRL3 ((0x00d1 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE13_WID_CTRL4 ((0x00d2 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE14_WID_CTRL0 ((0x00d4 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE14_WID_CTRL1 ((0x00d5 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE14_WID_CTRL2 ((0x00d6 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE14_WID_CTRL3 ((0x00d7 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE14_WID_CTRL4 ((0x00d8 << 2) + 0xfe037000)
+#define DMC_SEC_RANGE15_WID_CTRL0 ((0x00da << 2) + 0xfe037000)
+#define DMC_SEC_RANGE15_WID_CTRL1 ((0x00db << 2) + 0xfe037000)
+#define DMC_SEC_RANGE15_WID_CTRL2 ((0x00dc << 2) + 0xfe037000)
+#define DMC_SEC_RANGE15_WID_CTRL3 ((0x00dd << 2) + 0xfe037000)
+#define DMC_SEC_RANGE15_WID_CTRL4 ((0x00de << 2) + 0xfe037000)
+#define DMC_DES_CTRL ((0x00e1 << 2) + 0xfe037000)
+ //bit 31 : range15_des_en policy : 1 range15_des_en = range15_local_des_en && GLOBAL_DES_EN. 0 : range15_des_en = range15_local_des_en || GLOBAL_DES_EN.
+ //bit 30 : range14_des_en policy : 1 range14_des_en = range14_local_des_en && GLOBAL_DES_EN. 0 : range14_des_en = range14_local_des_en || GLOBAL_DES_EN.
+ //bit 29 : range13_des_en policy : 1 range13_des_en = range13_local_des_en && GLOBAL_DES_EN. 0 : range13_des_en = range13_local_des_en || GLOBAL_DES_EN.
+ //bit 28 : range12_des_en policy : 1 range12_des_en = range12_local_des_en && GLOBAL_DES_EN. 0 : range12_des_en = range12_local_des_en || GLOBAL_DES_EN.
+ //bit 27 : range11_des_en policy : 1 range11_des_en = range11_local_des_en && GLOBAL_DES_EN. 0 : range11_des_en = range11_local_des_en || GLOBAL_DES_EN.
+ //bit 26 : range10_des_en policy : 1 range11_des_en = range10_local_des_en && GLOBAL_DES_EN. 0 : range10_des_en = range10_local_des_en || GLOBAL_DES_EN.
+ //bit 25 : range9_des_en policy : 1 range9_des_en = range9_local_des_en && GLOBAL_DES_EN. 0 : range9_des_en = range9_local_des_en || GLOBAL_DES_EN.
+ //bit 24 : range8_des_en policy : 1 range8_des_en = range8_local_des_en && GLOBAL_DES_EN. 0 : range8_des_en = range8_local_des_en || GLOBAL_DES_EN.
+ //bit 23 : range7_des_en policy : 1 range7_des_en = range7_local_des_en && GLOBAL_DES_EN. 0 : range7_des_en = range7_local_des_en || GLOBAL_DES_EN.
+ //bit 22 : range6_des_en policy : 1 range6_des_en = range6_local_des_en && GLOBAL_DES_EN. 0 : range6_des_en = range6_local_des_en || GLOBAL_DES_EN.
+ //bit 21 : range5_des_en policy : 1 range5_des_en = range5_local_des_en && GLOBAL_DES_EN. 0 : range5_des_en = range5_local_des_en || GLOBAL_DES_EN.
+ //bit 20 : range4_des_en policy : 1 range4_des_en = range4_local_des_en && GLOBAL_DES_EN. 0 : range4_des_en = range4_local_des_en || GLOBAL_DES_EN.
+ //bit 19 : range3_des_en policy : 1 range3_des_en = range3_local_des_en && GLOBAL_DES_EN. 0 : range3_des_en = range3_local_des_en || GLOBAL_DES_EN.
+ //bit 18 : range2_des_en policy : 1 range2_des_en = range2_local_des_en && GLOBAL_DES_EN. 0 : range2_des_en = range2_local_des_en || GLOBAL_DES_EN.
+ //bit 17 : range1_des_en policy : 1 range1_des_en = range1_local_des_en && GLOBAL_DES_EN. 0 : range1_des_en = range1_local_des_en || GLOBAL_DES_EN.
+ //bit 16 : range0_des_en policy : 1 range0_des_en = range0_local_des_en && GLOBAL_DES_EN. 0 : range0_des_en = range0_local_des_en || GLOBAL_DES_EN.
+ //bit 1 | 0 | GLOBAL_DES_EN | 1: Global DES enable. 0 : global DES disable. default is 0.
+ //bit 0 | 0 | DES_lock | one time lock bit. after write 1 to this bit, DMC_DES_CTRL,DMC_DES_PADDING can't be write and read.
+//DES KEY registers and DES_PADDING can only be reset by pad reset. But it can be changed by software after watch dog reset.
+#define DMC_DES_KEY0_REG0 ((0x00e2 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_DES_KEY0_REG1 ((0x00e3 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_DES_KEY0_REG2 ((0x00e4 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_DES_KEY0_REG3 ((0x00e5 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_DES_KEY1_REG0 ((0x00e6 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_DES_KEY1_REG1 ((0x00e7 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_DES_KEY1_REG2 ((0x00e8 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_DES_KEY1_REG3 ((0x00e9 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_DES_PADDING ((0x00e0 << 2) + 0xfe037000)
+ //default : 0
+ //bit 31:0 | 0 | des_pading | 32bits address padding used for DES dkey generation.
+//FROM SC2, the APB bus provided Master ID through PUSER signals.
+//there's total 8 master IDs could access DMC non-secure registers.
+//we assign 1 control bit for each APB Master and each DMC non-secure register domains
+//and we added one lock bits to lock this setting can't be modified any more.
+#define DDR_APB_SEC_CTRL0 ((0x00f0 << 2) + 0xfe037000)
+ // APB access control for dmc REQUEST control register access control register.
+ // default : 0x005
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL1 ((0x00f1 << 2) + 0xfe037000)
+ // APB access control for DMC DRAM timing parameter and DFI inteface registers.
+ //default : 0x005
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL2 ((0x00f2 << 2) + 0xfe037000)
+ // APB access control for DMC PLL clock frequency control regsiter.
+ //default : 0x005
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL3 ((0x00f3 << 2) + 0xfe037000)
+ // APB access control for DMC sticky control regsiter.
+ //default : 0x005
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL4 ((0x00f4 << 2) + 0xfe037000)
+ // APB access control for DMC test control regsiter.
+ //default : 0x005
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL5 ((0x00f5 << 2) + 0xfe037000)
+ // APB access control for DMC clk reset control regsiter.
+ //default : 0x005
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL6 ((0x00f6 << 2) + 0xfe037000)
+ // APB access control for DMC protection regsiter.
+ //default : 0x005
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL7 ((0x00f7 << 2) + 0xfe037000)
+ // APB access control for DMC normal regsiter.
+ //default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL8 ((0x00f8 << 2) + 0xfe037000)
+ // APB access control for DDR PHY group regsiters.
+ //default : 0x50005
+ //bit 23:16. APB access enable for DDR PHY group 1 register.
+ //bit 10 PHY IMEM control 1: force PHY IMEM output 0. 0: normal working mode.
+ //bit 9 PHY DMEM control 1: force PHY DMEM output 0. 0: normal working mode.
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL9 ((0x00f9 << 2) + 0xfe037000)
+ // APB access control for DMC canvas regsiter.
+ //default : 0x005
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+//registers to check the security protection and watch point error information.
+#define DMC_SEC_STATUS ((0x00fa << 2) + 0xfe037000)
+ //bit 31~2. not used.
+ //bit 6
+ //bit 5
+ //bit 4
+ //bit 3 1 : normal security register write violation.( APB bus WDATA not equre the register value when APB write). write 1 to clean this bit to 0.
+ //bit 2 sec_alert. 1 DMC secruity register alert function triggered. can't clean. only reset DMC can clear this bit.
+ //bit 1 write security violation.
+ //bit 0. read security violation.
+#define DMC_VIO_ADDR0 ((0x00fb << 2) + 0xfe037000)
+ //ddr0 write secure violation address.
+#define DMC_VIO_ADDR1 ((0x00fc << 2) + 0xfe037000)
+ //bit 31:24 . not used. always 0.
+ //24 ddr0 secure check violation.
+ //23 not used.
+ //22 not used.
+ //21 not used.
+ //20. not used.
+ //19 ddr0 write address overflow. write out of DDR size.
+ //18:16. ddr0 write violation AWPROT bits.
+ //15:0 ddr0_write violation ID.
+#define DMC_VIO_ADDR2 ((0x00fd << 2) + 0xfe037000)
+ //ddr0 read seure violation address
+#define DMC_VIO_ADDR3 ((0x00fe << 2) + 0xfe037000)
+ //24 ddr0 read secure check violation.
+ //23 not used.
+ //22 not used.
+ //21 ddr0 read trap1 violation
+ //20 ddr0 read trap0 violation
+ //19 ddr 0 read address overflow. write out of DDR size.
+ //18:16. ddr 0 read violation ARPROT bits.
+ //15:0 ddr 0 read violation ID.
+#define DMC_DDR_CTRL ((0x0100 << 2) + 0xfe037000)
+ //bit 27. 0 : cavnas use 64bytes boundary
+ // 1 : canvas use 32bytes boundary.
+ //bit 24:22 3'b000 : ddr3 mode.
+ //3'b001 : ddr4 mode.
+ //3'b010 : lpddr3 mode.
+ //3'b011 : lpddr4 mode.
+ //bit 21. rank1 enable bit. if 1, rank1 used the address map is as bit 5:3 defined.
+ //bit 20 DDR4 BG1 enable bit.
+ //bit 18: ddrphy_16b, DDR PHY DDR SDRAM data bits width. 1: 16bits. 0 : 32 bits.
+ //bit 16. ddr_16b, 1: only use 16bits data in a 32bits DDR PHY data interface. 0 : normal data interface.
+ //bit 7:4 : ddr1_size. DDR rank1 size control.
+ //4'b0000 : DDR rank 1 is 128Mbyte.
+ //4'b0001 : DDR rank 1 is 256Mbyte.
+ //4'b0010 : DDR rank 1 is 512Mbyte.
+ //4'b0011 : DDR rank 1 is 1Gbyte.
+ //4'b0100 : DDR rank 1 is 2Gbyte.
+ //4'b0101 : DDR rank 1 is 4Gbyte.
+ //4'b1000 : DDR rank 1 is 192Mbyte.
+ //4'b1001 : DDR rank 1 is 374Mbyte.
+ //4'b1010 : DDR rank 1 is 768Mbyte.
+ //4'b1011 : DDR rank 1 is 1.5Gbyte.
+ //4'b1100 : DDR rank 1 is 3Gbyte.
+ //others : reserved.
+ //bit 3:0 : ddr0_size. DDR rank0 size control.
+ //4'b0000 : DDR rank 0 is 128Mbyte.
+ //4'b0001 : DDR rank 0 is 256Mbyte.
+ //4'b0010 : DDR rank 0 is 512Mbyte.
+ //4'b0011 : DDR rank 0 is 1Gbyte.
+ //4'b0100 : DDR rank 0 is 2Gbyte.
+ //4'b0101 : DDR rank 0 is 4Gbyte.
+ //4'b1000 : DDR rank 1 is 192Mbyte.
+ //4'b1001 : DDR rank 1 is 374Mbyte.
+ //4'b1010 : DDR rank 1 is 768Mbyte.
+ //4'b1011 : DDR rank 1 is 1.5Gbyte.
+ //4'b1100 : DDR rank 1 is 3Gbyte.
+ //others : reserved.
+//DDR3/4 LPDDR3/4 SDRAM address to 32bits linear address address map:
+//DDR0_ADDRMAP is used to select RANK0 bank, row, col address selection.
+//DDR1_ADDRMAP is used to select RANK1 bank, row, col address selection.
+#define DDR0_ADDRMAP_0 ((0x0101 << 2) + 0xfe037000)
+ //29:25 ca8.
+ //24:20 ca7.
+ //19:15 ca6.
+ //14:10 ca5.
+ //9:5 ca4.
+ //4:0 ca3.
+#define DDR0_ADDRMAP_1 ((0x0102 << 2) + 0xfe037000)
+ //29:25 ra2.
+ //24:20 ra1.
+ //19:15 ra0.
+ //14:10 ca11.
+ //9:5 ca10.
+ //4:0 ca9.
+#define DDR0_ADDRMAP_2 ((0x0103 << 2) + 0xfe037000)
+ //29:25 ra8.
+ //24:20 ra7.
+ //19:15 ra6.
+ //14:10 ra5.
+ //9:5 ra4.
+ //4:0 ra3.
+#define DDR0_ADDRMAP_3 ((0x0104 << 2) + 0xfe037000)
+ //29:25 ra14.
+ //24:20 ra13.
+ //19:15 ra12.
+ //14:10 ra11.
+ //9:5 ra10.
+ //4:0 ra9.
+#define DDR0_ADDRMAP_4 ((0x0105 << 2) + 0xfe037000)
+ //29:25 ra16 for DDR4 SDRAM
+ //24:20 bg1 for DDR4 SDRAM.
+ //19:15 ba2. or bg0 for DDR4.
+ //14:10 ba1.
+ //9:5 ba0.
+ //4:0 ra15.
+#define DDR1_ADDRMAP_0 ((0x0106 << 2) + 0xfe037000)
+ //29:25 ca8.
+ //24:20 ca7.
+ //19:15 ca6.
+ //14:10 ca5.
+ //9:5 ca4.
+ //4:0 ca3.
+#define DDR1_ADDRMAP_1 ((0x0107 << 2) + 0xfe037000)
+ //29:25 ra2.
+ //24:20 ra1.
+ //19:15 ra0.
+ //14:10 ca11.
+ //9:5 ca10.
+ //4:0 ca9.
+#define DDR1_ADDRMAP_2 ((0x0108 << 2) + 0xfe037000)
+ //29:25 ra8.
+ //24:20 ra7.
+ //19:15 ra6.
+ //14:10 ra5.
+ //9:5 ra4.
+ //4:0 ra3.
+#define DDR1_ADDRMAP_3 ((0x0109 << 2) + 0xfe037000)
+ //29:25 ra14.
+ //24:20 ra13.
+ //19:15 ra12.
+ //14:10 ra11.
+ //9:5 ra10.
+ //4:0 ra9.
+#define DDR1_ADDRMAP_4 ((0x010a << 2) + 0xfe037000)
+ //29:25 ra16 for DDR4 SDRAM
+ //24:20 bg1 for DDR4 SDRAM.
+ //19:15 ba2 or bg0 for DDR4 SDRAM..
+ //14:10 ba1.
+ //9:5 ba0.
+ //4:0 ra15.
+#define DMC_AXI2DDR0 ((0x0120 << 2) + 0xfe037000)
+ //for AXI address first 256MB AXI ADDRESS[31:28] == 4'b0000.
+ //bit 7 ddr_data_with 0 : 32bits. 1: 16bits data in a 16bits data bus.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr data 16bits mode 0 : 32bits. 1: 16 bits valid data in a 32bits data bus.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR1 ((0x0121 << 2) + 0xfe037000)
+ //for AXI_ADDRESS[31:28] == 4'b0001.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR2 ((0x0122 << 2) + 0xfe037000)
+ //for AXI_ADDRESS[31:28] == 4'b0010.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR3 ((0x0123 << 2) + 0xfe037000)
+ //for AXI_ADDRESS[31:28] == 4'b0011.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR4 ((0x0124 << 2) + 0xfe037000)
+ //for AXI_ADDRESS[31:28] == 4'b0100.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR5 ((0x0125 << 2) + 0xfe037000)
+ //for AXI_ADDRESS[31:28] == 4'b0101.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR6 ((0x0126 << 2) + 0xfe037000)
+ //for AXI_ADDRESS[31:28] == 4'b0110.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR7 ((0x0127 << 2) + 0xfe037000)
+ //for AXI_ADDRESS[31:28] == 4'b0111.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR8 ((0x0128 << 2) + 0xfe037000)
+ //for AXI_ADDRESS[31:28] == 4'b1000.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR9 ((0x0129 << 2) + 0xfe037000)
+ //for AXI_ADDRESS[31:28] == 4'b1001.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDRA ((0x012a << 2) + 0xfe037000)
+ //for AXI_ADDRESS[31:28] == 4'b1010.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDRB ((0x012b << 2) + 0xfe037000)
+ //for AXI_ADDRESS[31:28] == 4'b1011.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDRC ((0x012c << 2) + 0xfe037000)
+ //for AXI_ADDRESS[31:28] == 4'b1100.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDRD ((0x012d << 2) + 0xfe037000)
+ //for AXI_ADDRESS[31:28] == 4'b1101.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDRE ((0x012e << 2) + 0xfe037000)
+ //for AXI_ADDRESS[31:28] == 4'b1110.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDRF ((0x012f << 2) + 0xfe037000)
+ //for AXI_ADDRESS[31:28] == 4'b1111.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_DDR_CTRL1 ((0x0130 << 2) + 0xfe037000)
+ //bit 0. DMC_DDR_LOCK. 1: LOCK DMC_DDR_CTRL, DMC_DDR_CTRL1, DMC_AXI2DDRx, DDR0/1_ADDRMAP_x registers. those register can't modified any more.
+ // 0: all these regsiters can be read/write by secure APB access.
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_sec.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc_clk_freq/rtl/dmc_clk_freq.vh
+//
+//`ifdef DMC_FREQ_REG_DEFINE
+//`else
+//`define DMC_FREQ_REG_DEFINE
+// -----------------------------------------------
+// REG_BASE: APB1_BASE_ADDR = 0xfe036c00
+// -----------------------------------------------
+//`define DMC_FREQ_REG_BASE 32'hfe036c00
+#define AM_DDR_PLL_CNTL0 ((0x0000 << 2) + 0xfe036c00)
+ //bit 29 : dpll_reset.
+ //bit 28 : dpll_en.
+ //bit 27:26 : dpll_clk_en
+ //bit 25 : dpll_inv_sel
+ //bit 21:19 : od1 OD1[0] : 0 /2, 1: /4. OD1[2:1]. 2'b00: /1, 2'b01: /2. 2'b10 /4. 2'b11: /8.
+ //bit 18:16 : od
+ //bit 14:10 : dpll_ref_div_n
+ //bit 8:0 : dpll_int_num
+#define AM_DDR_PLL_CNTL1 ((0x0001 << 2) + 0xfe036c00)
+ //bit 18:0 : ddr_dpll_frac
+#define AM_DDR_PLL_CNTL2 ((0x0002 << 2) + 0xfe036c00)
+ //bit 22:20 : fref_sel
+ //bit 17:16 : os_ssc
+ //bit 15:12 : ssc_str_m
+ //bit 8 : ssc_en
+ //bit 7:4 : ssc_dep_sel
+ //bit 1:0 : dpll ss_mode.
+#define AM_DDR_PLL_CNTL3 ((0x0003 << 2) + 0xfe036c00)
+ //bit 31 : afc bypass
+ //bit 30 : afc clk sel
+ //bit 29 : code new
+ //bit 28 : dco_m_en
+ //bit 27 : dco_sdm_en
+ //bit 26 : div2
+ //bit 25 : div mode
+ //bit 24 : fast_lock mode
+ //bit 23 : fb_pre_div
+ //bit 22 : filter_mode
+ //bit 21 : fix_en
+ //bit 20 : freq_shift_en
+ //bit 19 : load
+ //bit 18 : load_en
+ //bit 17 : lock_f
+ //bit 16 : pulse_width_en
+ //bit 15 : sdmnc_en
+ //bit 14 : sdmnc_mode
+ //bit 13 : sdmnc_range
+ //bit 12 : tdc_en
+ //bit 11 : tdc_mode_sel
+ //bit 10 : wait_en
+#define AM_DDR_PLL_CNTL4 ((0x0004 << 2) + 0xfe036c00)
+ //bit 1:0 : pfd_gain
+ //bit 7:4 : filter_pvt1
+ //bit 11:8 : filter pvt2
+ //bit 13:12 : acq_gain
+ //bit 18:16 : lambda0
+ //bit 22:20 : lambda1
+ //bit 26:24 : rou
+ //bit 30:28 : alpha
+#define AM_DDR_PLL_CNTL5 ((0x0005 << 2) + 0xfe036c00)
+ //bit 15:0 : reve
+ //bit 21:16 : lm_s
+ //bit 27:24 : lm_w
+ //bit 30:28 : adj_vco_ldo
+#define AM_DDR_PLL_CNTL6 ((0x0006 << 2) + 0xfe036c00)
+ //bit 15:0 : reve
+ //bit 21:16 : lm_s
+ //bit 27:24 : lm_w
+ //bit 30:28 : adj_vco_ldo
+#define AM_DDR_PLL_STS ((0x0007 << 2) + 0xfe036c00)
+ //bit 31 : DDR_PLL_LOCK
+ //bit 30:19 : not used.
+ //bit 18 : DDR_AFC_DONE
+ //bit 17 : DDR_PLL_LOCK
+ //bit 16:7 : DDR_DPLL_OUT_RSV
+ //bit 6:0 : DDR_SDMNC_MONITOR
+#define DDR_CLK_CNTL ((0x0008 << 2) + 0xfe036c00)
+ //bit 31 ddr_pll_clk enable. enable the clock from DDR_PLL to clock generateion.
+ // whenever change the DDR_PLL frequency, disable the clock, after the DDR_PLL locked, then enable it again.
+ //bit 30. ddr_pll_prod_test_en. enable the clock to clock/32 which to clock frequency measurement and production test pin.
+ //bit 29. not used.
+ //bit 28. clock generation logic soft reset. 0 = reset.
+ //bit 27. phy_4xclk phase inverter..
+ //bit 25. DDRPHY DfiClk/DMC clock selection. 1: AM_PLL clk output /2. 0: directly output from AM_PLL .
+ //bit 24. enable AM_PLL CLK output /2 function. 1: enable. 0: disable. if try to use this clkoutput/2 function.
+ //bit 26. pll_freq divide/2. 1: use pll div/2 clock as the n_clk. 0: use pll clock as n_clk. this setting is used for the synopsys DDR PHY PLL fast lock mode.
+ //bit 2. enable dmc_clk.
+ //bit 1. not used.
+ //bit 0. enable LPDDR4-PHY clock
+#define DDR_PHY_CTRL ((0x0009 << 2) + 0xfe036c00)
+ // LPDDR4 power on reset need to special combination of PwrOkIn and phy_reset_n.
+ //bit 31: DDr PHY power on status. read only.
+ //bit 4. DDR PHY PwrOkIn pin.
+ //bit 1. DDR PHY APB soft reset_n.
+ //bit 0. phy_reset_n.
+#define AM_DDR_PLL_FREQ1_OD ((0x000c << 2) + 0xfe036c00)
+ //freqency set 1 PLL OD and OD1 setting. when change to freqency 1 will use this setting.
+//frequency set 0 use original DDR_PLL_CNTL0 setting.
+ //bit 8 currunt FREQ selection. it can forced to change to select which freqency to select, or it can auto changed by FREQ change hardware.
+ //bit 5:3 OD1.
+ //bit 2:0. OD.
+//`endif
+//
+// Closing file: ../mmc_lp4/dmc_clk_freq/rtl/dmc_clk_freq.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_reg.vh
+//
+//`define DMC_REG_BASE 32'hfe036000
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe036000
+// -----------------------------------------------
+#define DMC_REQ_CTRL ((0x0000 << 2) + 0xfe036000)
+ //bit 23. enable dmc request of ambus chan 7. Reserved for GE2D interface. Async interface.
+ //bit 22. enable dmc request of ambus chan 6. DOS HCODEC interface Sync interface.
+ //bit 21. enable dmc request of ambus chan 5. DOS VDEC interface Sync interface.
+ //bit 20. enable dmc request of ambus chan 4. VPU write interface 1 Sync interface.
+ //bit 19. enable dmc request of ambus chan 3. VPU write interface 0 Sync interface.
+ //bit 18. enable dmc request of ambus chan 2. VPU read interface 2. Sync interface.
+ //bit 17. enable dmc request of ambus chan 1. VPU read interface 1. Sync interface.
+ //bit 16. enable dmc request of ambus chan 0. VPU read interface 0. Sync interface.
+ //bit 9 enable dmc request of axibus chan 9. wave async interface.
+ //bit 8. enable dmc request of axibus chan 8 hevc_b async interface.
+ //bit 7. enable dmc request of axibus chan 7. DEVICE. Async interface.
+ //bit 6. enable dmc request of axibus chan 6. USB Async interface.
+ //bit 5. enable dmc request of axibus chan 5. reserved for dmc_test.
+ //bit 4. enable dmc request of axibus chan 4. hevc front Async interface.
+ //bit 3. enable dmc request of axibus chan 3. HDCP/HDMI Async interface.
+ //bit 2. enable dmc request of axibus chan 2. pcie async
+ //bit 1. enable dmc request of axibus chan 1. Mali . async interface.
+ //bit 0. enable dmc request of axibus chan 0. CPU/A53 async interface.
+//DMC CLK and RESET domain register. please check DMC_SEC_APB_CTRLx register for access details.
+#define DMC_SOFT_RST ((0x0001 << 2) + 0xfe036000)
+ //bit 31~24. reserved for future.
+ //bit 23:16 8 AMBUS input interface n_clk domain reset_n signal. 0 : reset. 1: normal working mode.
+ //bit 15:0. 16 AXI BUS input intefaces n_clk domain reset_n signal. 0: reset. 1: normal working mode. each bit for one interface.
+#define DMC_SOFT_RST1 ((0x0002 << 2) + 0xfe036000)
+ //To reset the Async interface, you need to disable the interface both clock domain, then reset both n_clk and m_clk domain
+ //bit 31~24 not used.
+ //bit 23.16 8 am bus interfaces master clock domain reset_n signal. 0 : reset : 1 normal working mode.
+ //bit 15:0. 16 AXI bus interfaces master clock domain reset_n signal. 0 : reset : 1 normal working mode.
+#define DMC_SOFT_RST2 ((0x0003 << 2) + 0xfe036000)
+ //bit 31~11. reserved for future.
+ //bit 10 DMC DFI cmd soft reset_n
+ //bit 9 DMC DFI MISC soft reset_n
+ //bit 8 DMC DFI data soft reset_n
+ //bit 7 DMC DFI dcu soft reset_n
+ //bit 6 DMC siu soft reset_n
+ //bit 5. DMC test soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 4. DMC low power control moudle soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 3. DMC QOS monitor module soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 2. DMC register modle soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 1. DMC canvas transfer module soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 0. DMC command buffers and command generation modules soft reset. 0 = reset. 1:
+#define DMC_RST_STS1 ((0x0004 << 2) + 0xfe036000)
+ //31~24. not used.
+ //23~0. Read only. the DMC_SOFT_RST1 signal in n_clk domain. the purpose of this register is when one of the 2 clocks is too slow or too fast, we can read this register to make sure another clock domain reset is done.
+#define DMC_CLKG_CTRL0 ((0x0006 << 2) + 0xfe036000)
+ //bit 23:16. enable the 8 ambus interfaces both main and n_clk auto clock gating function. each 1 bit for one interface.
+ //bit 15:0. enable the 16 axi interfaces both main and n_clk auto clock gating function. each 1 bit for one interface.
+#define DMC_CLKG_CTRL1 ((0x0007 << 2) + 0xfe036000)
+ //bit 23:16. force to disable the 8 ambus interfaces both main and n_clk. each 1 bit for one interface.
+ //bit 15:0. force to disable the 16 axi interfaces both main and n_clk. each 1 bit for one interface.
+#define DMC_CLKG_CTRL2 ((0x0008 << 2) + 0xfe036000)
+ //bit 12 enalbe auto clock gating for awcmdfifo.
+ //bit 11 enalbe auto clock gating for arcmdfifo.
+ //bit 10 enable auto clock gating for dfi command generation
+ //bit 9 enable auto clock gating for dram cntroller
+ //bit 8 enable auto clock gating for dfi data path.
+ //bit 7. enalbe auto clock gating for write rsp generation.
+ //bit 6. enalbe auto clock gating for read rsp generation.
+ //bit 5. enalbe auto clock gating for ddr0 command filter.
+ //bit 4. enalbe auto clock gating for ddr0 write reorder buffer.
+ //bit 3. enalbe auto clock gating for ddr0 write data buffer.
+ //bit 2. enalbe auto clock gating for ddr0 read reorder buffer.
+ //bit 1. enalbe auto clock gating for read canvas.
+ //bit 0. enalbe auto clock gating for write canvas.
+#define DMC_CLKG_CTRL3 ((0x0009 << 2) + 0xfe036000)
+ //bit 12 force to disable the clock of awcmdfifo.
+ //bit 11 force to disable the clock of arcmdfifo.
+ //bit 10 force to disable the clock of dfi command generation
+ //bit 9 force to disable the clock of dram cntroller
+ //bit 8 force to disable the clock of dfi data path.
+ //bit 7. force to disalbe the clock of write rsp generation.
+ //bit 6. force to disalbe the clock of read rsp generation.
+ //bit 5. force to disalbe the clock of command filter.
+ //bit 4. force to disalbe the clock of write reorder buffer.
+ //bit 3. force to disalbe the clock of write data buffer.
+ //bit 2. force to disalbe the clock of read reorder buffer.
+ //bit 1. force to disalbe the clock of read canvas.
+ //bit 0. force to disalbe the clock of write canvas.
+// DMC CANVAS setting domain control regsiters.
+#define DC_CAV_LUT_DATAL ((0x0012 << 2) + 0xfe036000)
+ //low 32 bits of canvas data which need to be configured to canvas memory.
+#define DC_CAV_LUT_DATAH ((0x0013 << 2) + 0xfe036000)
+ //high 32bits of cavnas data which need to be configured to canvas memory.
+ //64bits CANVAS look up table
+ //bit 60:58 Endian control.
+ //3'b000: no endian change.
+ //3'b001:
+ //bit 57:56. Canvas block mode. 2 : 64x32, 1: 32x32; 0 : linear mode.
+ //bit 55: canvas Y direction wrap control. 1: wrap back in y. 0: not wrap back.
+ //bit 54: canvas X direction wrap control. 1: wrap back in X. 0: not wrap back.
+ //bit 53:41. canvas Hight.
+ //bit 40:29. canvas Width, unit: 8bytes. must in 32bytes boundary. that means last 2 bits must be 0.
+ //bit 28:0. cavnas start address. unit. 8 bytes. must be in 32bytes boundary. that means last 2bits must be 0.
+#define DC_CAV_LUT_ADDR ((0x0014 << 2) + 0xfe036000)
+ //bit 9:8. write 9:8 2'b10. the canvas data will saved in canvas memory with addres 7:0.
+ //bit 7:0. 256 canvas Look up table address.
+#define DC_CAV_LUT_RDATAL ((0x0015 << 2) + 0xfe036000)
+ // CBUS low 32bytes canvas read back data from LUT.
+#define DC_CAV_LUT_RDATAH ((0x0016 << 2) + 0xfe036000)
+ // Cbus high 32bytes canvas read back data from LUT.
+// there are total 256 canvas table, So we added a 256bits register to record the those canvas mode.
+// when we configure the canvas table and if the canvas mode is 32x32 blkmode, we'll mark this related bit.
+// we will use this bit to check the VPU canvas access. if it's in 32x32 blkmode, we need break the input in 32bytes boundary.
+// You can also use below register to read/write those bit.
+#define DC_CAV_BLK_CTRL0 ((0x0018 << 2) + 0xfe036000)
+ //canvas index 31:0 blkmode. 1 : 32x32. 0 : others.
+#define DC_CAV_BLK_CTRL1 ((0x0019 << 2) + 0xfe036000)
+ //canvas index 63:32 blkmode. 1 : 32x32. 0 : others.
+#define DC_CAV_BLK_CTRL2 ((0x001a << 2) + 0xfe036000)
+ //canvas index 95:64 blkmode. 1 : 32x32. 0 : others.
+#define DC_CAV_BLK_CTRL3 ((0x001b << 2) + 0xfe036000)
+ //canvas index 127:96 blkmode. 1 : 32x32. 0 : others.
+#define DC_CAV_BLK_CTRL4 ((0x001c << 2) + 0xfe036000)
+ //canvas index 159:128 blkmode. 1 : 32x32. 0 : others.
+#define DC_CAV_BLK_CTRL5 ((0x001d << 2) + 0xfe036000)
+ //canvas index 191:160 blkmode. 1 : 32x32. 0 : others.
+#define DC_CAV_BLK_CTRL6 ((0x001e << 2) + 0xfe036000)
+ //canvas index 223:192 blkmode. 1 : 32x32. 0 : others.
+#define DC_CAV_BLK_CTRL7 ((0x001f << 2) + 0xfe036000)
+ //canvas index 255:224 blkmode. 1 : 32x32. 0 : others.
+#define DMC_MON_CTRL0 ((0x0020 << 2) + 0xfe036000)
+ //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
+ //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
+ //bit 7. BW monitor 3 enable.
+ //bit 6. BW monitor 3 enable.
+ //bit 5. BW monitor 3 enable.
+ //bit 4. BW monitor 3 enable.
+ //bit 3. BW monitor 3 enable.
+ //bit 2. BW monitor 2 enable.
+ //bit 1. BW monitor 1 enable.
+ //bit 0. BW monitor 0 enable.
+#define DMC_MON_TIMER ((0x0021 << 2) + 0xfe036000)
+ // timer for the monitor period.
+#define DMC_MON_ALL_IDLE_CNT ((0x0022 << 2) + 0xfe036000)
+ // at the test period, the whole MMC all channel IDLE time. unit, dmc clock.
+#define DMC_MON_ALL_BW ((0x0023 << 2) + 0xfe036000)
+ // at the test period, the whole MMC granted data cycles. 64bits unit.
+#define DMC_MON_ALL16_BW ((0x0024 << 2) + 0xfe036000)
+ // at the test period, the whole MMC granted data cycles which goes to 16bits ddr. unit:64bits
+#define DMC_MON0_CTRL ((0x0025 << 2) + 0xfe036000)
+ //BW MONTIOR 0 address range ctrol. start addrss <= AXI address[31:16] <= end address
+ //bit 31:16 End address[31:16]
+ //bit 15:0. start address[31:16]
+#define DMC_MON0_CTRL1 ((0x0026 << 2) + 0xfe036000)
+ //bit 23:0. BW monitor 0 channel select. 8 ambus port and 16 AXI port selection. 1 bit for one port.
+ // if only 1 channel selected, you can use DMC_MONx_CTRL2 to chose any subid of this selected channel. otherwise DMC_MONx_CTRL2 should be set 0xffff
+#define DMC_MON0_CTRL2 ((0x0027 << 2) + 0xfe036000)
+ //bit 15:0. BW monitor 0 port select for the selected channel.
+#define DMC_MON0_BW ((0x0028 << 2) + 0xfe036000)
+ // at the test period, this range granted data cycles for the seletec channel and ports.
+#define DMC_MON1_CTRL ((0x0029 << 2) + 0xfe036000)
+ //BW monitor 1 address range ctrol. start addrss <= AXI address[31:16] <= end address
+ //bit 31:16 End address[31:16]
+ //bit 15:0. start address[31:16]
+#define DMC_MON1_CTRL1 ((0x002a << 2) + 0xfe036000)
+ //bit 23:0. BW monitor 1 channel select. 8 ambus port and 16 AXI port selection. 1 bit for one port.
+ // if only 1 channel selected, you can use DMC_MONx_CTRL2 to chose any subid of this selected channel. otherwise DMC_MONx_CTRL2 should be set 0xffff
+#define DMC_MON1_CTRL2 ((0x002b << 2) + 0xfe036000)
+ //bit 15:0. BW monitor 1 port select for the selected channel.
+#define DMC_MON1_BW ((0x002c << 2) + 0xfe036000)
+ // at the test period, this range granted data cycles for the seletec channel and ports.
+#define DMC_MON2_CTRL ((0x002d << 2) + 0xfe036000)
+ //BW monitor 2 address range ctrol. start addrss <= AXI address[31:16] <= end address
+ //bit 31:16 End address[31:16]
+ //bit 15:0. start address[31:16]
+#define DMC_MON2_CTRL1 ((0x002e << 2) + 0xfe036000)
+ //bit 23:0. BW monitor 2 channel select. 8 ambus port and 16 AXI port selection. 1 bit for one port.
+ // if only 1 channel selected, you can use DMC_MONx_CTRL2 to chose any subid of this selected channel. otherwise DMC_MONx_CTRL2 should be set 0xffff
+#define DMC_MON2_CTRL2 ((0x002f << 2) + 0xfe036000)
+ //bit 15:0. BW monitor 2 port select for the selected channel.
+#define DMC_MON2_BW ((0x0030 << 2) + 0xfe036000)
+ // at the test period, this range granted data cycles for the seletec channel and ports.
+#define DMC_MON3_CTRL ((0x0031 << 2) + 0xfe036000)
+ //BW monitor 3 address range ctrol. start addrss <= AXI address[31:16] <= end address
+ //bit 31:16 End address[31:16]
+ //bit 15:0. start address[31:16]
+#define DMC_MON3_CTRL1 ((0x0032 << 2) + 0xfe036000)
+ //bit 23:0. BW monitor 3 channel select. 8 ambus port and 16 AXI port selection. 1 bit for one port.
+ // if only 1 channel selected, you can use DMC_MONx_CTRL2 to chose any subid of this selected channel. otherwise DMC_MONx_CTRL2 should be set 0xffff
+#define DMC_MON3_CTRL2 ((0x0033 << 2) + 0xfe036000)
+ //bit 15:0. BW monitor 3 port select for the selected channel.
+#define DMC_MON3_BW ((0x0034 << 2) + 0xfe036000)
+ // at the test period, this range granted data cycles for the seletec channel and ports.
+#define DMC_MON4_CTRL ((0x0035 << 2) + 0xfe036000)
+ //BW monitor 4 address range ctrol. start addrss <= AXI address[31:16] <= end address
+ //bit 31:16 End address[31:16]
+ //bit 15:0. start address[31:16]
+#define DMC_MON4_CTRL1 ((0x0036 << 2) + 0xfe036000)
+ //bit 23:0. BW monitor 4 channel select. 8 ambus port and 16 AXI port selection. 1 bit for one port.
+ // if only 1 channel selected, you can use DMC_MONx_CTRL2 to chose any subid of this selected channel. otherwise DMC_MONx_CTRL2 should be set 0xffff
+#define DMC_MON4_CTRL2 ((0x0037 << 2) + 0xfe036000)
+ //bit 15:0. BW monitor 4 port select for the selected channel.
+#define DMC_MON4_BW ((0x0038 << 2) + 0xfe036000)
+ // at the test period, this range granted data cycles for the seletec channel and ports.
+#define DMC_MON5_CTRL ((0x0039 << 2) + 0xfe036000)
+ //BW monitor 5 address range ctrol. start addrss <= AXI address[31:16] <= end address
+ //bit 31:16 End address[31:16]
+ //bit 15:0. start address[31:16]
+#define DMC_MON5_CTRL1 ((0x003a << 2) + 0xfe036000)
+ //bit 23:0. BW monitor 5 channel select. 8 ambus port and 16 AXI port selection. 1 bit for one port.
+ // if only 1 channel selected, you can use DMC_MONx_CTRL2 to chose any subid of this selected channel. otherwise DMC_MONx_CTRL2 should be set 0xffff
+#define DMC_MON5_CTRL2 ((0x003b << 2) + 0xfe036000)
+ //bit 15:0. BW monitor 5 port select for the selected channel.
+#define DMC_MON5_BW ((0x003c << 2) + 0xfe036000)
+ // at the test period, this range granted data cycles for the seletec channel and ports.
+#define DMC_MON6_CTRL ((0x003d << 2) + 0xfe036000)
+ //BW monitor 6 address range ctrol. start addrss <= AXI address[31:16] <= end address
+ //bit 31:16 End address[31:16]
+ //bit 15:0. start address[31:16]
+#define DMC_MON6_CTRL1 ((0x003e << 2) + 0xfe036000)
+ //bit 23:0. BW monitor 6 channel select. 8 ambus port and 16 AXI port selection. 1 bit for one port.
+ // if only 1 channel selected, you can use DMC_MONx_CTRL2 to chose any subid of this selected channel. otherwise DMC_MONx_CTRL2 should be set 0xffff
+#define DMC_MON6_CTRL2 ((0x003f << 2) + 0xfe036000)
+ //bit 15:0. BW monitor 6 port select for the selected channel.
+#define DMC_MON6_BW ((0x0040 << 2) + 0xfe036000)
+ // at the test period, this range granted data cycles for the seletec channel and ports.
+#define DMC_MON7_CTRL ((0x0041 << 2) + 0xfe036000)
+ //BW monitor 7 address range ctrol. start addrss <= AXI address[31:16] <= end address
+ //bit 31:16 End address[31:16]
+ //bit 15:0. start address[31:16]
+#define DMC_MON7_CTRL1 ((0x0042 << 2) + 0xfe036000)
+ //bit 23:0. BW monitor 7 channel select. 8 ambus port and 16 AXI port selection. 1 bit for one port.
+ // if only 1 channel selected, you can use DMC_MONx_CTRL2 to chose any subid of this selected channel. otherwise DMC_MONx_CTRL2 should be set 0xffff
+#define DMC_MON7_CTRL2 ((0x0043 << 2) + 0xfe036000)
+ //bit 15:0. BW monitor 7 port select for the selected channel.
+#define DMC_MON7_BW ((0x0044 << 2) + 0xfe036000)
+ // at the test period, this range granted data cycles for the seletec channel and ports.
+#define DMC_CMD_FILTER_CTRL1 ((0x0050 << 2) + 0xfe036000)
+ //not used.
+#define DMC_CMD_FILTER_CTRL2 ((0x0051 << 2) + 0xfe036000)
+ //31:24. keep the bank active if there's urgent level 3 read bank hit request.
+ //23:16. keep the bank active if there's urgent level 2 read bank hit request.
+ //15:8. keep the bank active if there's urgent level 1 read bank hit request.
+ //7:0. keep the bank active if there's urgent level 0 read bank hit request.
+#define DMC_CMD_FILTER_CTRL3 ((0x0052 << 2) + 0xfe036000)
+ //bit 31. force wbuf empty.
+ //bit 30:26 wbuf high level number
+ //bit 25:21 wbuf mid level number
+ //bit 20:16 wbuf low level number
+ //bit 14:10 rbuf high level number
+ //bit 9:5 rbuf middle level number
+ //bit 4:0 rbuf low level number
+#define DMC_CMD_FILTER_CTRL4 ((0x0053 << 2) + 0xfe036000)
+ //bit 29:25. tITW.long
+ //bit 24:20. tITW. short
+ //bit 19:12 tAP auto precharge the bank not used if idle that long time.
+ //bit 11:6 write to read accesses if there write hit request.
+ //bit 5:0 read to write accesses if there write hit request.
+#define DMC_CMD_FILTER_CTRL5 ((0x0054 << 2) + 0xfe036000)
+ //bit 31:24 Once ddr data bus switch to read, the maxmum read command number to give up the bus when there's write request pending for write buffer.
+ //bit 23:16 Once ddr data bus switch to write, the maxmum write command number to give up the bus when there's read request pending too long.
+ //bit 15:8. Once ddr data bus switch to read, the minimum read command number to transfer back to write stage if there's still pending read request.
+ //bit 7:0. Once ddr data bus switch to write, the minimum write command number to transfer back to read stage if there's still pending write request.
+#define DMC_CMD_FILTER_CTRL6 ((0x0055 << 2) + 0xfe036000)
+ //bit 31:24 write urgent 3 request pending hold num.
+ //bit 23:16 write urgent 2 request pending hold num.
+ //bit 15:8. write urgent 1 request pending hold num.
+ //bit 7:0. write urgent 0 request pending hold num.
+#define DMC_CMD_FILTER_CTRL7 ((0x0056 << 2) + 0xfe036000)
+ //bit 31:24. aw_req_pedning singal assertion after wbuf full.
+ //bit 23:16 aw_req_pending singal hold how long if wbuf not full.
+ //bit 15:8 write to read waiting cycles if there write hit request.
+ //bit 7:0 read to write waiting cycles if there write hit request.
+#define DMC_CMD_FILTER_CTRL8 ((0x0057 << 2) + 0xfe036000)
+ //bit 31:8 reserved.
+ //bit 7:0 rank limit to change to another rank.
+#define DMC_CMD_BUFFER_CTRL ((0x0058 << 2) + 0xfe036000)
+ //bit 31:26 total write buffer number. default 32.
+ //bit 25:20 total read buffer number. default 32.
+ //bit 19:8 reserved.
+ //bit 7:0 aw_pending_inc_num. incease write ugent level 1 when write command waiting to in write buffer that long.
+#define DMC_CMD_BUFFER_CTRL1 ((0x0059 << 2) + 0xfe036000)
+ //bit 29:24 read buffer number in non-urgent request.
+ //bit 23:16 read buffer bank miss watch dog threshold.
+ //bit 15:12 read buffer urgent level 3 counter inc weight.
+ //bit 11:8 read buffer urgent level 2 counter inc weight.
+ //bit 7:4 read buffer urgent level 1 counter inc weight.
+ //bit 3:0 read buffer urgent level 0 counter inc weight.
+#define DMC_2ARB_CTRL ((0x005c << 2) + 0xfe036000)
+ //32:24. Waiting limit to use the highest urgent level in the pipelines.
+ //22. 1: allow to increase 2 urgent levels if waiting time is doubled than inc_ugt_limit.
+ //21:12 inc_ugt_limit. if waiting time > inc_ugt_limit, increase the urgent level by one
+ //11:6. the final arbitration control from AXI bus(port channel 0~7).
+ //5:0. the final arbitration weight control for Ambus ( port channel 8~15).
+#define DMC_VERSION ((0x005f << 2) + 0xfe036000)
+ //read only 32'h000a0008 for sc2
+#define DMC_AM0_CHAN_CTRL ((0x0060 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AM0_HOLD_CTRL ((0x0061 << 2) + 0xfe036000)
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AM0_CHAN_CTRL1 ((0x0062 << 2) + 0xfe036000)
+ //bit 31: side band signal used as block other request.
+ //bit 30 : side band urgent increase enable.
+ //bit 29 : side band urgent decrease urgent enable.
+ //bit 23:16 : when bit 31 enabled, block the ambus related bits read request.
+ //bit 15:0 : when bit 31 enabled, block the axi bus related bits read request.
+#define DMC_AM0_CHAN_CTRL2 ((0x0063 << 2) + 0xfe036000)
+ //bit 31:24 not used.
+ //bit 23:16 : when side band signal used as block other request, and side bank signal is high, block the ambus related bits write request.
+ //bit 15:0 : when side band signal used as block other request, and side bank signal is high, block the axi bus related bits write request.
+#define DMC_AM1_CHAN_CTRL ((0x0064 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AM1_HOLD_CTRL ((0x0065 << 2) + 0xfe036000)
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AM1_CHAN_CTRL1 ((0x0066 << 2) + 0xfe036000)
+ //bit 31: side band signal used as block other request.
+ //bit 30 : side band urgent increase enable.
+ //bit 29 : side band urgent decrease urgent enable.
+ //bit 23:16 : when bit 31 enabled, block the ambus related bits read request.
+ //bit 15:0 : when bit 31 enabled, block the axi bus related bits read request.
+#define DMC_AM1_CHAN_CTRL2 ((0x0067 << 2) + 0xfe036000)
+ //bit 31:24 not used.
+ //bit 23:16 : when side band signal used as block other request, and side bank signal is high, block the ambus related bits write request.
+ //bit 15:0 : when side band signal used as block other request, and side bank signal is high, block the axi bus related bits write request.
+#define DMC_AM2_CHAN_CTRL ((0x0068 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AM2_HOLD_CTRL ((0x0069 << 2) + 0xfe036000)
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AM2_CHAN_CTRL1 ((0x006a << 2) + 0xfe036000)
+ //bit 31: side band signal used as block other request.
+ //bit 30 : side band urgent increase enable.
+ //bit 29 : side band urgent decrease urgent enable.
+ //bit 23:16 : when bit 31 enabled, block the ambus related bits read request.
+ //bit 15:0 : when bit 31 enabled, block the axi bus related bits read request.
+#define DMC_AM2_CHAN_CTRL2 ((0x006b << 2) + 0xfe036000)
+ //bit 31:24 not used.
+ //bit 23:16 : when side band signal used as block other request, and side bank signal is high, block the ambus related bits write request.
+ //bit 15:0 : when side band signal used as block other request, and side bank signal is high, block the axi bus related bits write request.
+#define DMC_AM3_CHAN_CTRL ((0x006c << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AM3_HOLD_CTRL ((0x006d << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AM3_CHAN_CTRL1 ((0x006e << 2) + 0xfe036000)
+ //bit 31: side band signal used as block other request.
+ //bit 30 : side band urgent increase enable.
+ //bit 29 : side band urgent decrease urgent enable.
+ //bit 23:16 : when bit 31 enabled, block the ambus related bits read request.
+ //bit 15:0 : when bit 31 enabled, block the axi bus related bits read request.
+#define DMC_AM3_CHAN_CTRL2 ((0x006f << 2) + 0xfe036000)
+ //bit 31:24 not used.
+ //bit 23:16 : when side band signal used as block other request, and side bank signal is high, block the ambus related bits write request.
+ //bit 15:0 : when side band signal used as block other request, and side bank signal is high, block the axi bus related bits write request.
+#define DMC_AM4_CHAN_CTRL ((0x0070 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AM4_HOLD_CTRL ((0x0071 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AM4_CHAN_CTRL1 ((0x0072 << 2) + 0xfe036000)
+ //bit 31: side band signal used as block other request.
+ //bit 30 : side band urgent increase enable.
+ //bit 29 : side band urgent decrease urgent enable.
+ //bit 23:16 : when bit 31 enabled, block the ambus related bits read request.
+ //bit 15:0 : when bit 31 enabled, block the axi bus related bits read request.
+#define DMC_AM4_CHAN_CTRL2 ((0x0073 << 2) + 0xfe036000)
+ //bit 31:24 not used.
+ //bit 23:16 : when bit 31 enabled, block the ambus related bits write request.
+ //bit 15:0 : when bit 31 enabled, block the axi bus related bits write request.
+#define DMC_AM5_CHAN_CTRL ((0x0074 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AM5_HOLD_CTRL ((0x0075 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AM6_CHAN_CTRL ((0x0078 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AM6_HOLD_CTRL ((0x0079 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AM7_CHAN_CTRL ((0x007c << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AM7_HOLD_CTRL ((0x007d << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI0_CHAN_CTRL ((0x0080 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi0 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 arbiter weight
+#define DMC_AXI0_HOLD_CTRL ((0x0081 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI0_CHAN_CTRL1 ((0x0082 << 2) + 0xfe036000)
+ //bit 31:28. FIQ status
+ //bit 27:24. IRQ status.
+ //bit 22 use ACTIVE input as clock gating control.
+ //bit 21:20. chan0 QOS mode.
+ //bit 19:16. AXI0 QOS high limit.
+ //bit 15:12 AXI0 QOS mit limit.
+ //bit 11 ARM FIQ controlled super urgent enable.
+ //bit 10 ARM FIQ controlled urgent enable.
+ //bit 9. ARM IRQ controlled super urgent enable.
+ //bit 8. ARM IRQ controlled urgent enable.
+ //bit 7. IRQ/FIQ controll enable.
+ //bit 6:5. not used.
+ //bit 4. enable AXI0 auto urgent enable. When there's no other request, treat the AXI0 as super urgent request. other wise, use the bit3:0 to set the urgent.
+ //bit 3:2 A9 urgent if there's VIU request.
+ //bit 1:0 A9 urgent if there's request other than VIU
+#define DMC_AXI1_CHAN_CTRL ((0x0084 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI1_HOLD_CTRL ((0x0085 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI1_CHAN_CTRL1 ((0x0086 << 2) + 0xfe036000)
+ //bit 31:28. FIQ status
+ //bit 27:24. IRQ status.
+ //bit 21:20. Mali QOS mode.
+ //bit 19:16. mail QOS high limit.
+ //bit 15:12 mail QOS mit limit.
+ //bit 11 ARM FIQ controlled super urgent enable.
+ //bit 10 ARM FIQ controlled urgent enable.
+ //bit 9. ARM IRQ controlled super urgent enable.
+ //bit 8. ARM IRQ controlled urgent enable.
+ //bit 7. IRQ/FIQ controll enable.
+ //bit 6:0. not used.
+#define DMC_AXI2_CHAN_CTRL ((0x0088 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI2_HOLD_CTRL ((0x0089 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI3_CHAN_CTRL ((0x008c << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI3_HOLD_CTRL ((0x008d << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI4_CHAN_CTRL ((0x0090 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI4_HOLD_CTRL ((0x0091 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI5_CHAN_CTRL ((0x0094 << 2) + 0xfe036000)
+ //not used.
+#define DMC_AXI5_HOLD_CTRL ((0x0095 << 2) + 0xfe036000)
+ //not used.
+#define DMC_AXI6_CHAN_CTRL ((0x0098 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI6_HOLD_CTRL ((0x0099 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI7_CHAN_CTRL ((0x009c << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI7_HOLD_CTRL ((0x009d << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI8_CHAN_CTRL ((0x00a0 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI8_HOLD_CTRL ((0x00a1 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI9_CHAN_CTRL ((0x00a4 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI9_HOLD_CTRL ((0x00a5 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI10_CHAN_CTRL ((0x00a8 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI10_HOLD_CTRL ((0x00a9 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI10_CHAN_CTRL1 ((0x00aa << 2) + 0xfe036000)
+ //bit 11 Mali/NNA channel FIQ controlled super urgent enable.
+ //bit 10 Mali/NNA channel FIQ controlled urgent enable.
+ //bit 9. Mali/NNA channel IRQ controlled super urgent enable.
+ //bit 8. Mali/NNA channel IRQ controlled urgent enable.
+ //bit 7. IRQ/FIQ controll enable.
+ //bit 6:0. not used.
+#define DMC_AXI11_CHAN_CTRL ((0x00ac << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI11_HOLD_CTRL ((0x00ad << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI12_CHAN_CTRL ((0x00b0 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI12_HOLD_CTRL ((0x00b1 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI13_CHAN_CTRL ((0x00b4 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI13_HOLD_CTRL ((0x00b5 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AM0_CHAN_STS ((0x00b8 << 2) + 0xfe036000)
+#define DMC_AM1_CHAN_STS ((0x00b9 << 2) + 0xfe036000)
+#define DMC_AM2_CHAN_STS ((0x00ba << 2) + 0xfe036000)
+#define DMC_AM3_CHAN_STS ((0x00bb << 2) + 0xfe036000)
+#define DMC_AM4_CHAN_STS ((0x00bc << 2) + 0xfe036000)
+#define DMC_AM5_CHAN_STS ((0x00bd << 2) + 0xfe036000)
+#define DMC_AM6_CHAN_STS ((0x00be << 2) + 0xfe036000)
+#define DMC_AM7_CHAN_STS ((0x00bf << 2) + 0xfe036000)
+#define DMC_AXI0_CHAN_STS ((0x00c0 << 2) + 0xfe036000)
+#define DMC_AXI1_CHAN_STS ((0x00c1 << 2) + 0xfe036000)
+#define DMC_AXI2_CHAN_STS ((0x00c2 << 2) + 0xfe036000)
+#define DMC_AXI3_CHAN_STS ((0x00c3 << 2) + 0xfe036000)
+#define DMC_AXI4_CHAN_STS ((0x00c4 << 2) + 0xfe036000)
+#define DMC_AXI5_CHAN_STS ((0x00c5 << 2) + 0xfe036000)
+#define DMC_AXI6_CHAN_STS ((0x00c6 << 2) + 0xfe036000)
+#define DMC_AXI7_CHAN_STS ((0x00c7 << 2) + 0xfe036000)
+#define DMC_AXI8_CHAN_STS ((0x00c8 << 2) + 0xfe036000)
+#define DMC_AXI9_CHAN_STS ((0x00c9 << 2) + 0xfe036000)
+#define DMC_AXI10_CHAN_STS ((0x00ca << 2) + 0xfe036000)
+#define DMC_AXI11_CHAN_STS ((0x00cb << 2) + 0xfe036000)
+#define DMC_AXI12_CHAN_STS ((0x00cc << 2) + 0xfe036000)
+#define DMC_AXI13_CHAN_STS ((0x00cd << 2) + 0xfe036000)
+#define DMC_CHAN_STS ((0x00ce << 2) + 0xfe036000)
+ //AXI0 is first CPU and Mali conbined channel from CCI-400 directly. The first 2Gbyte address will go through this channel.
+ //AXI10 is the second CPU, Mali channel combined with NNA from NIC-400. The upper 2Gbyte address will go through this channel.
+ // read only regsiter.
+ // the second mali and NNA channel IDLE.
+ // the second CPU channel IDLE.
+ // the first mali channel IDLE.
+ // the first CPU channel IDLE.
+ //bit 27 always 1
+ //bit 26 ddr0 write data buffer idle. 1 : idle 0: busy.
+ //bit 25 always 1.
+ //bit 24 ddr0 wbuf idle. 1 : idle 0: busy.
+ //bit 23:16 ambus channel idle. 1 : idle 0: busy.
+ //bit 15:0. axibus channel idle. 1 : idle 0: busy.
+#define DMC_IRQ_STS ((0x00cf << 2) + 0xfe036000)
+ //bit 31:3 Not used.
+ //bit 2 : QOS Monitor interrupt flag. 1: means there's QOS monitor interrup. write 1 to clean this interrupt.
+ //bit 1 : WRITE protection interrupt. 1: means there's write protection violation. need to write DMC_PROT_IRQ_CTRL bit 1to clean this bit.
+ //bit 0 : read protection interrupt. 1: means there's read protection violation. need to write DMC_PROT_IRQ_CTRL bit 0 to clean this bit.
+#define DMC_PROT0_RANGE ((0x00d0 << 2) + 0xfe036000)
+ //protection 0 address range. the range define is 64Kbyte boundary. current address [31:16] >= start address && current address [31:16] <= end address.
+ //bit 31:16 : range end address.
+ //bit 15:0 : range start address
+#define DMC_PROT0_CTRL ((0x00d1 << 2) + 0xfe036000)
+ //bit 23:16. each bit to eanble one of the 8 ambus channal for the protection function.
+ //bit 15:0 each bit to enable one of the 15 channel input for the protection function.
+#define DMC_PROT0_CTRL1 ((0x00d2 << 2) + 0xfe036000)
+ //bit 26. protection 0 read access protection enable.
+ //bit 25. protection 0 write access block function. if enabled, the access wouldn't write to the DDR SDRAM. if not enabled only generate a interrupt, but the access still wrote to DDR.
+ //bit 24. protection range 0 write access protection enable.
+#define DMC_PROT1_RANGE ((0x00d3 << 2) + 0xfe036000)
+ //protection 1 address range. the range define is 64Kbyte boundary. current address [31:16] >= start address && current address [31:16] <= end address.
+ //bit 31:16 : range end address.
+ //bit 15:0 : range start address
+#define DMC_PROT1_CTRL ((0x00d4 << 2) + 0xfe036000)
+ //bit 23:16. each bit to eanble one of the 8 ambus channal for the protection function.
+ //bit 15:0 each bit to enable one of the 15 channel input for the protection function.
+#define DMC_PROT1_CTRL1 ((0x00d5 << 2) + 0xfe036000)
+ //bit 26. protection range 1 read access protection enable bit.
+ //bit 25. protection 1 write access block function. if enabled, the access wouldn't write to the DDR SDRAM. if not enabled only generate a interrupt, but the access still wrote to DDR.
+ //bit 24. protection range 1 write access protection enable bit.
+#define DMC_PROT_VIO_0 ((0x00d6 << 2) + 0xfe036000)
+ //ddr0 write proection violation address.
+#define DMC_PROT_VIO_1 ((0x00d7 << 2) + 0xfe036000)
+ //bit 31:21 . not used. always 0.
+ //20 ddr0 protection 1 vilation.
+ //19 ddr0 protection 0 vilation.
+ //18:16. ddr0 write violation AWPROT bits.
+ //15:0 ddr0_write violation ID.
+#define DMC_PROT_VIO_2 ((0x00d8 << 2) + 0xfe036000)
+ //ddr0 read prot violation address
+#define DMC_PROT_VIO_3 ((0x00d9 << 2) + 0xfe036000)
+ //bit 31:21 . not used. always 0.
+ //20 ddr0 read protection 1 violation.
+ //19 ddr0 read protection 0 violation.
+ //18:16. ddr0 read violation ARPROT bits.
+ //15:0 ddr0 read violation ID.
+#define DMC_PROT_IRQ_CTRL ((0x00da << 2) + 0xfe036000)
+ //bit 2 : protect function IRQ enable.
+ //bit 1 : write protection violation. write 1 to clean write protection vio registers.
+ //bit 0 : read protection violation. write 1 to clean read protection vio registers.
+//`define DMC_TEST_REG_BASE 32'hfe037800
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe037800
+// -----------------------------------------------
+#define DMC_TEST_STA ((0x0000 << 2) + 0xfe037800)
+ //test start address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary.
+ // for sha mode, address must be in 64 bytes boundary. that mean the last 6 bits must be 0.
+#define DMC_TEST_EDA ((0x0001 << 2) + 0xfe037800)
+ //test end address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary.
+ // for sha mode, address must be in 64 bytes boundary. that mean the last 6bits must be 1.
+#define DMC_TEST_CTRL ((0x0002 << 2) + 0xfe037800)
+ //bit 31. enable test.
+ //bit 30. when enable test, enable the write to DDR function.
+ //bit 29. when enable test, enable the read from DDR function.
+ //bit 28. when enable test, enable the sha calculation function must be same as read enable but without write function.
+ //bit 27. enabe to compare data. when do the read enable to enable the error comparaion. suppose the read data should be same as the data in the write buffer.
+ //bit 26. 0: save sha result to test_sha_message registers. 1 : don't save.
+ //bit 25. address generation type. 0: continuous increase the address in the range of test start address and test end address.
+ // 1: test module would pick the random address from test start address and test end address.
+ //bit 24. done type. 0 : use the DMC_TEST_NUM register as the counter of test numbers.
+ // for write if the write command number == the DMC_TEST_NUM, the write is done.
+ // for read if the read command number == the DMC TEST_num, the read id done. for one read command can be repeated repeat number times.
+ // 1 : finshed at end address.
+ //bit 23. wdata type. 1 : the first write is {WD3, WD2,WD1,WD0}, then the latter is the previous data plus a pattern.( { + WD7, + WD6, + WD5, + WD4}).
+ // 0 : the WDATA is the data in write register.
+ //bit 23. 1 compare the sha result with the test sha message registers. 0 : dont compare the result.
+ //bit 22:20. read repeat times. for non-sha function, we can define multi times of the read. the test module would repeat the same adddress repeat times.
+ //bit 19. limit write. 0: no outstanding write request limitation.
+ // 1: limit the outstanding write commands to the number of bits [15:8]
+ //bit 18. limit read. 0. no outstanding read request limitation.
+ // 1. limit the read outstanding request to the number of bits[7:0].
+ //bit 17:16. sha mode for sha function enabled. 00 : not used. 01 : sha1. 2: sha2-256. 3: sha2_224. not used in GXL fixed to be Sha 2.
+ //bit 15:8. write outstanding commands limit.
+ //bit 7:0. read outstanding commands limit.
+#define DMC_TEST_NUM ((0x0003 << 2) + 0xfe037800)
+ // how many test command for the test if the DMC_TEST_CTRL bit 24 is 0.
+#define DMC_TEST_WDG ((0x0004 << 2) + 0xfe037800)
+ //31:16. write response watch dog.
+ //15:0. read response watch dog.
+#define DMC_TEST_COMP_MASK ((0x0005 << 2) + 0xfe037800)
+ //32bits for DMC TEST COMPARE bit enable.
+ //1 : to MASK this bit. 0: compare this bit.
+#define DMC_TEST_WSTRB0 ((0x0006 << 2) + 0xfe037800)
+ //MPC WR FIFO command DM bit write data
+ //bit 31:16 the second cycle.
+ //bit 15:0 the first cycle.
+#define DMC_TEST_WSTRB1 ((0x0007 << 2) + 0xfe037800)
+ //MPC WR FIFO command DM bit write data
+ //bit 31:16. the Forth cycle.
+ //bit 15:0. the third cycle.
+#define DMC_TEST_WD0 ((0x0010 << 2) + 0xfe037800)
+ // write data 0 for write command. also for read back data comparision.
+#define DMC_TEST_WD1 ((0x0011 << 2) + 0xfe037800)
+ // write data 1 for write command. also for read back data comparision.
+#define DMC_TEST_WD2 ((0x0012 << 2) + 0xfe037800)
+ // write data 2 for write command. also for read back data comparision.
+#define DMC_TEST_WD3 ((0x0013 << 2) + 0xfe037800)
+ // write data 3 for write command. also for read back data comparision.
+#define DMC_TEST_WD4 ((0x0014 << 2) + 0xfe037800)
+ // write data 4 for write command. also for read back data comparision.
+#define DMC_TEST_WD5 ((0x0015 << 2) + 0xfe037800)
+ // write data 5 for write command. also for read back data comparision.
+#define DMC_TEST_WD6 ((0x0016 << 2) + 0xfe037800)
+ // write data 6 for write command. also for read back data comparision.
+#define DMC_TEST_WD7 ((0x0017 << 2) + 0xfe037800)
+ // write data 7 for write command. also for read back data comparision.
+#define DMC_TEST_WD8 ((0x0018 << 2) + 0xfe037800)
+ // write data 8 for write command. also for read back data comparision.
+#define DMC_TEST_WD9 ((0x0019 << 2) + 0xfe037800)
+ // write data 9 for write command. also for read back data comparision.
+#define DMC_TEST_WD10 ((0x001a << 2) + 0xfe037800)
+ // write data 10 for write command. also for read back data comparision.
+#define DMC_TEST_WD11 ((0x001b << 2) + 0xfe037800)
+ // write data 11 for write command. also for read back data comparision.
+#define DMC_TEST_WD12 ((0x001c << 2) + 0xfe037800)
+ // write data 12 for write command. also for read back data comparision.
+#define DMC_TEST_WD13 ((0x001d << 2) + 0xfe037800)
+ // write data 13 for write command. also for read back data comparision.
+#define DMC_TEST_WD14 ((0x001e << 2) + 0xfe037800)
+ // write data 14 for write command. also for read back data comparision.
+#define DMC_TEST_WD15 ((0x001f << 2) + 0xfe037800)
+ // write data 15 for write command. also for read back data comparision.
+#define DMC_TEST_RD0 ((0x0020 << 2) + 0xfe037800)
+ // the read back data 0. if error happens, it would capture the first error data.
+#define DMC_TEST_RD1 ((0x0021 << 2) + 0xfe037800)
+ // the read back data 1. if error happens, it would capture the first error data.
+#define DMC_TEST_RD2 ((0x0022 << 2) + 0xfe037800)
+ // the read back data 2. if error happens, it would capture the first error data.
+#define DMC_TEST_RD3 ((0x0023 << 2) + 0xfe037800)
+ // the read back data 3. if error happens, it would capture the first error data.
+#define DMC_TEST_RD4 ((0x0024 << 2) + 0xfe037800)
+ // the read back data 4. if error happens, it would capture the first error data.
+#define DMC_TEST_RD5 ((0x0025 << 2) + 0xfe037800)
+ // the read back data 5. if error happens, it would capture the first error data.
+#define DMC_TEST_RD6 ((0x0026 << 2) + 0xfe037800)
+ // the read back data 6. if error happens, it would capture the first error data.
+#define DMC_TEST_RD7 ((0x0027 << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD8 ((0x0028 << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD9 ((0x0029 << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD10 ((0x002a << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD11 ((0x002b << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD12 ((0x002c << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD13 ((0x002d << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD14 ((0x002e << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD15 ((0x002f << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_ERR_ADDR ((0x0040 << 2) + 0xfe037800)
+ //read only. it capature the first error address.
+#define DMC_TEST_ERR_CNT ((0x0041 << 2) + 0xfe037800)
+ //read only. how many data error happens in the whole test period.
+#define DMC_TEST_STS ((0x0042 << 2) + 0xfe037800)
+ //read only.
+ //bit 31, test done bit. write 1 to clean.
+ //bit 30, indicate address err
+ //bit 29~7. not used.
+ //bit 6. read data resp error(caused by security or rd latency).
+ //bit 5. test MRR/MPR rd latency error. write 1 clear
+ //bit 4, sha done. write 1 to clean.
+ //bit 3, write done. write 1 to clean.
+ //bit 2, read done. write 1 to clean
+ //bit 1, write watchdog triggered. write 1 to clean
+ //bit 0, read watchdog triggered. write 1 to clean.
+#define DMC_TEST_WRCMD_ADDR ((0x0043 << 2) + 0xfe037800)
+ //read only. the current write cmd address.
+#define DMC_TEST_RDCMD_ADDR ((0x0044 << 2) + 0xfe037800)
+ //read only. the current read command address.
+#define DMC_TEST_RDRSP_ADDR ((0x0045 << 2) + 0xfe037800)
+ //read only. the failed read response address(for error data )
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh
+//
+//`define DMC_DRAM_REG_BASE 32'hfe036400
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe036400
+// -----------------------------------------------
+//there's 2 set of timing DDR timing parameter for 2 set of DDR freqency parameter.
+//when change frequency, the hardware would automatically select one of these two set of timing parameter
+//DMC_DRAM_* is for Frequency set 0.
+//DMC_NFQ_* is for Freqency set 1.
+#define DMC_DRAM_TMRD ((0x0000 << 2) + 0xfe036400)
+ //bit 4:0. tMRD. //MR command cycles, in DDR3/4. in LPDDR4, it should be value of tMRW
+#define DMC_DRAM_TRFC ((0x0001 << 2) + 0xfe036400)
+ //bit 9:0 tRFC
+#define DMC_DRAM_TRP ((0x0002 << 2) + 0xfe036400)
+ //bit 21:16. tRP for precharge all banks.
+ //bit 5:0. tRP for precharge one bank.
+#define DMC_DRAM_TRTW ((0x0003 << 2) + 0xfe036400)
+ //bit 31:6: Not used.
+ //bit 5:0 DDR3/4 mode : tRTW.
+ // For LPDDR4 . The total read command -> write command = (RL + BL/2 - tWODTON) + TDQSCK_MAX + tWPRE +RD(tRPST).
+ // tRTW = TDQSCK_max + tWPRE + tRD(tRPST) + (delay margin)
+#define DMC_DRAM_TCL ((0x0004 << 2) + 0xfe036400)
+ //bit 5:0 tCL/tRL. read latency.
+#define DMC_DRAM_TCWL ((0x0005 << 2) + 0xfe036400)
+ //bit 5:0. CWL: write latency.
+#define DMC_DRAM_TRAS ((0x0006 << 2) + 0xfe036400)
+ //bit 7:0. tRAS. minimum active to precharge time for same bank.
+#define DMC_DRAM_TRC ((0x0007 << 2) + 0xfe036400)
+ //bit 7:0. tRC. minimum active to active time for same bank.
+#define DMC_DRAM_TRCD ((0x0008 << 2) + 0xfe036400)
+ //bit 7:0 tRCD active to read/write timing for same bank.
+#define DMC_DRAM_TRRD ((0x0009 << 2) + 0xfe036400)
+ //bit 21:16. tRRD_l active bank A to active B in same band group for DDR4.
+ //bit 5:0. tRRD/tRRD_s active bank A to active bank b time.
+ //tRRD_s: active bank A to active bank b in different bank grousp for DDR4.
+#define DMC_DRAM_TFAW ((0x000a << 2) + 0xfe036400)
+ //bit 8:0 tFAW. four active command windows
+#define DMC_DRAM_TRTP ((0x000b << 2) + 0xfe036400)
+ //bit 5:0 tRTP.
+#define DMC_DRAM_TWR ((0x000c << 2) + 0xfe036400)
+ //bit 5:0 tWR.
+#define DMC_DRAM_TWTR ((0x000d << 2) + 0xfe036400)
+ //bit 21:16 tWTR_l For DDR4 WTR_l. FOR DDR3/LPDDR4 same as tWTR_s.
+ //bit 5:0 tWTR_s.
+#define DMC_DRAM_TCCD ((0x000e << 2) + 0xfe036400)
+ //bit 19:16. tCCD/tCCD_l.
+ //bit 3:0 tCCD/tCCD_s read to read command time or write to write command time.
+#define DMC_DRAM_TEXSR ((0x000f << 2) + 0xfe036400)
+ //bit 12:0. tEXSR. EXIT SELF-REFRESH to read/write command.
+#define DMC_DRAM_TXS ((0x0010 << 2) + 0xfe036400)
+ //bit 9:0 tXS. EXIT SELF_REFRESH to other command time
+#define DMC_DRAM_TXP ((0x0011 << 2) + 0xfe036400)
+ //bit 3:0. tXP. EXIT power down to other command time
+#define DMC_DRAM_TXPDLL ((0x0012 << 2) + 0xfe036400)
+ //bit 12:0. tXPDLL, EXIT power down to read/write command time(need to relock PLL).
+#define DMC_DRAM_TZQCS ((0x0013 << 2) + 0xfe036400)
+ //bit 11:0. ZQCS command to other command time.
+#define DMC_DRAM_TCKSRE ((0x0014 << 2) + 0xfe036400)
+ //bit 4:0. enter self refresh to disable clock time.
+#define DMC_DRAM_TCKSRX ((0x0015 << 2) + 0xfe036400)
+ //bit 4:0. enable clock to exit self refresh time.
+#define DMC_DRAM_TCKE ((0x0016 << 2) + 0xfe036400)
+ //bit 4:0. CKE high or low minimum time.
+#define DMC_DRAM_TMOD ((0x0017 << 2) + 0xfe036400)
+ //bit 4:0 tMOD. MRR/MRW to other command time. in LPDDR4, still use this register but it called tMRD.
+#define DMC_DRAM_TDQS ((0x0018 << 2) + 0xfe036400)
+ //bit 31:28 reserved
+ //bit 27:24 tDQS. the delay for write after read in different rank.
+ //bit 23:20 reserved
+ //bit 19:16 tDQS. the delay for read after write in different rank.
+ //bit 15:12 reserved
+ //bit 11:8 tDQS. the delay for write after write in different rank.
+ //bit 7:4 reserved
+ //bit 3:0 tDQS. the delay for read after read in different rank.
+#define DMC_DRAM_TRSTL ((0x0019 << 2) + 0xfe036400)
+ //not used.
+#define DMC_DRAM_TZQLAT ((0x001a << 2) + 0xfe036400)
+ //bit 5:0 ZQ LATCH command to other comand timing in LPDDR4 mode.
+#define DMC_DRAM_TMRR ((0x001b << 2) + 0xfe036400)
+ //bit 7:0 tMRR not used in DMC.
+#define DMC_DRAM_TCKESR ((0x001c << 2) + 0xfe036400)
+ //bit 9:0 tCKESR. CKE low minimum pulse in self refresh mode.
+#define DMC_DRAM_TDPD ((0x001d << 2) + 0xfe036400)
+ //not support.
+#define DMC_DRAM_DFITCTRLDELAY ((0x001e << 2) + 0xfe036400)
+ //bit 3:0. DFI_t_ctrldealy
+#define DMC_DRAM_DFITPHYWRDATA ((0x001f << 2) + 0xfe036400)
+ //bit 5:0. dfi_t_phy_wrdata.
+#define DMC_DRAM_DFITPHYWRLAT ((0x0020 << 2) + 0xfe036400)
+ //bit 5:0. dfi_t_phy_wrlat. in DDR3/4/LPDDR3 mode: WL -5. in LPDDR4 mode: WL -5 + 2.
+#define DMC_DRAM_DFITRDDATAEN ((0x0021 << 2) + 0xfe036400)
+ //bit 5:0. dfi_t_rddata_en. in DDR3/4/LPDDR3 mode: RL -5. in LPDDR4 mode : RL -5 + 1.
+#define DMC_DRAM_DFITPHYRDLAT ((0x0022 << 2) + 0xfe036400)
+ //bit 5:0. dfi_t_rdlat.
+#define DMC_DRAM_DFITCTRLUPDMIN ((0x0023 << 2) + 0xfe036400)
+ //bit 7:0. CTRLUPD_MIN minimux clock cycle to maintain CTRLUPD_REQ.
+#define DMC_DRAM_DFITCTRLUPDMAX ((0x0024 << 2) + 0xfe036400)
+ //bit 7:0 CTRLUPD_MAX. maxmum clock cycle to maintain CTRLUPD_REQ if no CTRLUPD_ACK response.
+#define DMC_DRAM_DFITREFMSKI ((0x0026 << 2) + 0xfe036400)
+ //not used.
+#define DMC_DRAM_DFITCTRLUPDI ((0x0027 << 2) + 0xfe036400)
+ //not used.
+#define DMC_DRAM_DFITDRAMCLK ((0x0028 << 2) + 0xfe036400)
+//bit 17 dram clk1 enable.
+//bit 16 dram clk0 enable.
+//bit 15:8 DRAM CLK disable waiting time
+//bit 7:0 DRAM CLK enable enable timer
+#define DMC_DRAM_DFITLPRESP ((0x002a << 2) + 0xfe036400)
+ //bit 3:0. dfi_lp_ctrl_req response time. after dfi_lp_ctrl_req asserted, and after response time if there's still no dfi_lp_ack respone, then drop the dfi_lp_ctrl_req.
+#define DMC_DRAM_TCKECK ((0x002c << 2) + 0xfe036400)
+ //bit 4:0. tCKECK from CKE low to assert dfi_dram_clk_disable time. this time + dfi_t_ctrl_delay
+#define DMC_DRAM_TREFI ((0x002d << 2) + 0xfe036400)
+ //write this register will update the auto refresh related register to the auto refresh control logic.
+ //bit 31:24: tZQCI dmc send zqci period. unit is how much auto refresh period.
+ //bit 23:16 pvti dmc send dfi_ctrlupd_req period. unit is one auto refresh period.
+ //bit 15:8. tREFI.dmc send auto refresh command period. unit is 100ns.
+ //bit 7:0. t100ns period. unit is dmc clock cycles
+#define DMC_DRAM_TSR ((0x002e << 2) + 0xfe036400)
+ //bit 5:0 tSR. self resfresh enter to exit time.
+#define DMC_DRAM_TCCDMW ((0x002f << 2) + 0xfe036400)
+ //bit 5:0. 4*tCCD in LPDDR4 mask write.
+#define DMC_DRAM_TESCKE ((0x0030 << 2) + 0xfe036400)
+ //bit 5:0 tESCKE. enter self refresh to power time for LPDDR4.
+#define DMC_DRAM_TREFI_DDR3 ((0x0031 << 2) + 0xfe036400)
+ //7:0. DDR3 SDRAM tREFI single auto refresh time . the unit is t100ns.
+ //use this to check in 8*tREFI time, the DMC should not sent more than 16 auto REFRESH command.
+#define DMC_DRAM_TZQCAL ((0x0032 << 2) + 0xfe036400)
+ //11:0. ZQCAL for LPDDR4. ZQINIT/ZQoper for DDR3/4 ZQCL command.
+#define DMC_DRAM_T10US ((0x0033 << 2) + 0xfe036400)
+ //10us clock cycle number used for LP2 mode.
+#define DMC_DRAM_TMRRI ((0x0034 << 2) + 0xfe036400)
+//bit 7:0 tMRRI for MRR
+#define DMC_DRAM_TXS_FAST ((0x0035 << 2) + 0xfe036400)
+ //bit 9:0 DDR4 mode XS_FAST exit self_refrest to zqcl/zqcs/mrs command.
+#define DMC_DRAM_DFIODTCFG ((0x0036 << 2) + 0xfe036400)
+ //bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity.
+ //bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1.
+ //bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0.
+ //bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1.
+ //bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0.
+ //bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity.
+ //bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0.
+ //bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1.
+ //bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0.
+ //bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1.
+#define DMC_DRAM_DFIODTCFG1 ((0x0037 << 2) + 0xfe036400)
+ //bit 27:24 ODT length for BL8 read transfer.
+ //bit 19:16. ODT length for BL8 write transfer.
+ //bit 12:8. ODT latency for reads. suppose to be 0.
+ //bit 4:0. ODT latency for writes. suppose to be 0.
+#define DMC_DRAM_TWODTON ((0x0038 << 2) + 0xfe036400)
+ //bit 5:0 DRAM write access ODT on time.
+ // in DDR3/4 should be same as WL.
+ // in LPDDR4 ODT enable mode: tODTLon + tODTon.min
+ // In LPDDR4 ODT disable mode: tWL.
+#define DMC_DRAM_TRETRAIN ((0x0039 << 2) + 0xfe036400)
+ //bit 15:0 LPDDR4 OSCRING retraining timer(units = auto_refresh timer). sync with autorefresh
+#define DMC_DRAM_PHYADDRON ((0x003a << 2) + 0xfe036400)
+ //bit 5:0 PHY_CTRL_ADDR_ON for new PHY. default : 12 unit: DfiClk
+#define DMC_DRAM_PHYWRON ((0x003b << 2) + 0xfe036400)
+ //bit 6:0 PHY_CTRL_ADDR_ON for new PHY. unit: ddr clk
+ // PHY_CTRL_WR_ON. = 20 + WL + (tDQSS+ tDQS2DQ + tWPST)/ddr_clk + BL/2
+#define DMC_DRAM_PHYRDON ((0x003c << 2) + 0xfe036400)
+ // PHY_CTRL_RD_ON. = 20 + RL + (tDQSCK+ tRPST + tDQSQ)/ddr_clk + BL/2
+#define DMC_DRAM_ZQCTRL ((0x003d << 2) + 0xfe036400)
+ //tZQCI bits in DMC_DRAM_TREFI defined how many refresh period send ZQCS/ZQUPD/command.
+ //this register defines in 0~tZQCI period, which refresh period count to send partical ZQCS/ZACAL/ZQUPD command
+ //31:24. in LPDDR4 case when to send ZQLAT comman to both RANKs of LPDDR4 SDRAM
+ //23:16. when to send PHY ZQ UPDATE command.
+ //15:8. when to send ZQCS/ZQCAL to rank1 DDR SDRAM.
+ //7:0. when to senc ZQCS/ZQCAL to rank0 DDR SDRAM.
+//timing paramter for frequency set 1.
+#define DMC_NFQ_TMRD ((0x0040 << 2) + 0xfe036400)
+#define DMC_NFQ_TRFC ((0x0041 << 2) + 0xfe036400)
+#define DMC_NFQ_TRP ((0x0042 << 2) + 0xfe036400)
+#define DMC_NFQ_TRTW ((0x0043 << 2) + 0xfe036400)
+#define DMC_NFQ_TCL ((0x0044 << 2) + 0xfe036400)
+#define DMC_NFQ_TCWL ((0x0045 << 2) + 0xfe036400)
+#define DMC_NFQ_TRAS ((0x0046 << 2) + 0xfe036400)
+#define DMC_NFQ_TRC ((0x0047 << 2) + 0xfe036400)
+#define DMC_NFQ_TRCD ((0x0048 << 2) + 0xfe036400)
+#define DMC_NFQ_TRRD ((0x0049 << 2) + 0xfe036400)
+#define DMC_NFQ_TFAW ((0x004a << 2) + 0xfe036400)
+#define DMC_NFQ_TRTP ((0x004b << 2) + 0xfe036400)
+#define DMC_NFQ_TWR ((0x004c << 2) + 0xfe036400)
+#define DMC_NFQ_TWTR ((0x004d << 2) + 0xfe036400)
+#define DMC_NFQ_TCCD ((0x004e << 2) + 0xfe036400)
+#define DMC_NFQ_TEXSR ((0x004f << 2) + 0xfe036400)
+#define DMC_NFQ_TXS ((0x0050 << 2) + 0xfe036400)
+#define DMC_NFQ_TXP ((0x0051 << 2) + 0xfe036400)
+#define DMC_NFQ_TXPDLL ((0x0052 << 2) + 0xfe036400)
+#define DMC_NFQ_TZQCS ((0x0053 << 2) + 0xfe036400)
+#define DMC_NFQ_TCKSRE ((0x0054 << 2) + 0xfe036400)
+#define DMC_NFQ_TCKSRX ((0x0055 << 2) + 0xfe036400)
+#define DMC_NFQ_TCKE ((0x0056 << 2) + 0xfe036400)
+#define DMC_NFQ_TMOD ((0x0057 << 2) + 0xfe036400)
+#define DMC_NFQ_TDQS ((0x0058 << 2) + 0xfe036400)
+#define DMC_NFQ_TRSTL ((0x0059 << 2) + 0xfe036400)
+#define DMC_NFQ_TZQLAT ((0x005a << 2) + 0xfe036400)
+#define DMC_NFQ_TMRR ((0x005b << 2) + 0xfe036400)
+#define DMC_NFQ_TCKESR ((0x005c << 2) + 0xfe036400)
+#define DMC_NFQ_TDPD ((0x005d << 2) + 0xfe036400)
+#define DMC_NFQ_DFITCTRLDELAY ((0x005e << 2) + 0xfe036400)
+#define DMC_NFQ_DFITPHYWRDATA ((0x005f << 2) + 0xfe036400)
+#define DMC_NFQ_DFITPHYWRLAT ((0x0060 << 2) + 0xfe036400)
+#define DMC_NFQ_DFITRDDATAEN ((0x0061 << 2) + 0xfe036400)
+#define DMC_NFQ_DFITPHYRDLAT ((0x0062 << 2) + 0xfe036400)
+#define DMC_NFQ_DFITCTRLUPDMIN ((0x0063 << 2) + 0xfe036400)
+#define DMC_NFQ_DFITCTRLUPDMAX ((0x0064 << 2) + 0xfe036400)
+#define DMC_NFQ_DFITREFMSKI ((0x0066 << 2) + 0xfe036400)
+#define DMC_NFQ_DFITCTRLUPDI ((0x0067 << 2) + 0xfe036400)
+#define DMC_NFQ_DFITDRAMCLK ((0x0068 << 2) + 0xfe036400)
+#define DMC_NFQ_DFITLPRESP ((0x006a << 2) + 0xfe036400)
+#define DMC_NFQ_TCKECK ((0x006c << 2) + 0xfe036400)
+#define DMC_NFQ_TREFI ((0x006d << 2) + 0xfe036400)
+#define DMC_NFQ_TSR ((0x006e << 2) + 0xfe036400)
+#define DMC_NFQ_TCCDMW ((0x006f << 2) + 0xfe036400)
+#define DMC_NFQ_TESCKE ((0x0070 << 2) + 0xfe036400)
+#define DMC_NFQ_TREFI_DDR3 ((0x0071 << 2) + 0xfe036400)
+#define DMC_NFQ_TZQCAL ((0x0072 << 2) + 0xfe036400)
+#define DMC_NFQ_T10US ((0x0073 << 2) + 0xfe036400)
+#define DMC_NFQ_TMRRI ((0x0074 << 2) + 0xfe036400)
+#define DMC_NFQ_TXS_FAST ((0x0075 << 2) + 0xfe036400)
+#define DMC_NFQ_DFIODTCFG ((0x0076 << 2) + 0xfe036400)
+#define DMC_NFQ_DFIODTCFG1 ((0x0077 << 2) + 0xfe036400)
+#define DMC_NFQ_TWODTON ((0x0078 << 2) + 0xfe036400)
+#define DMC_NFQ_TRETRAIN ((0x0079 << 2) + 0xfe036400)
+#define DMC_NFQ_PHYADDRON ((0x007a << 2) + 0xfe036400)
+#define DMC_NFQ_PHYWRON ((0x007b << 2) + 0xfe036400)
+#define DMC_NFQ_PHYRDON ((0x007c << 2) + 0xfe036400)
+#define DMC_NFQ_ZQCTRL ((0x007d << 2) + 0xfe036400)
+//end of second frequency timing parameter
+#define DMC_DRAM_DFITPHYUPDTYPE0 ((0x0080 << 2) + 0xfe036400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 0.
+#define DMC_DRAM_DFITPHYUPDTYPE1 ((0x0081 << 2) + 0xfe036400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 1.
+#define DMC_DRAM_DFITPHYUPDTYPE2 ((0x0082 << 2) + 0xfe036400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 2.
+#define DMC_DRAM_DFITPHYUPDTYPE3 ((0x0083 << 2) + 0xfe036400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 3.
+#define DMC_DRAM_MCFG ((0x0086 << 2) + 0xfe036400)
+ //bit 31:27 not used.
+ //bit 26:24 rank1_d16_sel. 16bit mode, rank 1 byte selection.
+ //bit 23 not used.
+ //bit 22:20. rank0_d16_sel. 16bit mode, rank 0 byte selection.
+ //bit 19. send PHY ZQ command after siu self refresh exit. 1 : enable. 0 : disable.
+ //bit 18. send retrain command after siu self refresh exit. 1 : enable. 0 : disable.
+ //bit 17. in DDR3/4 mode, send ZQCL command after exit register triggered self refresh.
+ //bit 16. send refresh command after finish frequency change. 1 : enable. 0 : disable.
+ //bit 15. send refresh command after finish LPDDR4 retraining. 1 : enable. 0 : disable.
+ //bit 14. 1: cke init low. 0 : cke init high.
+ //bit 13 1: dbi write enable only for LPDDR4.
+ //bit 12. 1: dbi read inversion. 0: dbi read high inversion.
+ //bit 11. 1: dbi read enable. 0: dbi not enabled.
+ //bit 10 1: enable staggered chip select for 2 ranks DRAM.
+ //bit 9 1: enable send auto refresh command to DDR SDRAM when PCTL is in CFG/STOP state.
+ //bit 8 send auto refr cmd before enter register triggered self refresh
+ //bit 7 send auto refr cmd after exit regsiter triggered self refresh mode.
+ //bit 6 disable dram clock after enter register triggered self refresh.
+ //bit 5 send DFI_LP_REQ to PHY after enter register triggered elf refresh mode.
+ //bit 4 send DRAM to power down mode after enter self refresh. ONLY for LPDDR4.
+ //bit 3 send DFI_CTRLUPD_REQ after exit register triggered self refresh.
+ //bit 2 send ZQCS command after exit register triggered self refresh.
+ //bit 1 enable PHY triggered DFI_PHYUPD_REQ.
+ //bit 0 2T mode. always 1 in DDR3/4 mode.
+#define DMC_DRAM_ZQ_CTRL ((0x0087 << 2) + 0xfe036400)
+ //bit 2 ZQ command must be send in different time.
+ //bit 1 ZQ command can be send at same time.
+ //bit 0 rank0 ZQ only
+#define DMC_DRAM_MCFG1 ((0x0088 << 2) + 0xfe036400)
+ //bit7:0 LPDDR4 WDBI mode maskwrite dbi pattern
+#define DMC_DRAM_DFI_CTRL ((0x0089 << 2) + 0xfe036400)
+ //bit 31 siu_dfi_lat err generation enable. 1: if dfi read latency violation, generate data error. 0 : disable.
+ //bit 20 phy_ctrl_rd_on phy_ctrl_wr_on ignore 16bit mode. 1: sending 0xf in 16bit mode. 0: sending valid byte enable in 16bit mode
+ //bit 19: dfi_init_complete wait enable. 1: after dfi_init_complete, wait additional EXSR time for new command. 0: phy will handle all the timing after dfi_init_complete DMC can do everything they want.
+ //bit 18: dfi_rddata_cs_n polariy. 0: rank0 select = 2'b10. rank1 select = 2'b10. 1: rank0 select = 2'b01, rank1_select = 2'b10.
+ //bit 17: dfi_wrdata_cs_n polariy. 0: rank0 select = 2'b10. rank1 select = 2'b10. 1: rank0 select = 2'b01, rank1_select = 2'b10.
+ //bit 16: force PHY ctrl_on if = 1, phy_ctrl_on singal will keep on.
+ //bit 15 siu_dfi1_lp_en
+ //bit 14 siu_dfi_lp_ack_and
+ //bit 13 siu_dfi_lp_ack_or
+ //bit 12 siu_dfi1_init_start_en
+ //bit 11 siu_dfi_init_com_and
+ //bit 10 siu_dfi_init_com_or
+ //bit 9 siu_dfi1_freq_en
+ //bit 8 siu_dfi1_dram_clk_dis_en
+ //bit 7 siu_dfi_phyupd_type_sel
+ //bit 6 siu_dfi1_phyupd_ack_en
+ //bit 5 siu_dfi_phyupd_req_and
+ //bit 4 siu_dfi_phyupd_req_or
+ //bit 3 siu_dfi_ctrlupd_ack_and
+ //bit 2 siu_dfi_ctrlupd_ack_or
+ //bit 1 siu_dfi1_ctrlupd_req_en
+ //bit 0 siu_dfi1_cmd_en
+#define DMC_DRAM_DFIINITCFG ((0x008a << 2) + 0xfe036400)
+ //bit 31. dfi_init_complete status. read only.
+ //bit 15:14. Frequency set 1 dfi_freq_ratio value.
+ //bit 12:8 Frequency set 1 dfi_freq value.
+ //bit 7:6 Frequency set 0 dfi_freq_ratio value.
+ //bit 5:1 Frequency set 0 dfi_freq value.
+ //bit 0. dfi_init_start value can be use manually config dfi_init_start signal.
+#define DMC_DRAM_APD_CTRL ((0x008c << 2) + 0xfe036400)
+ //bit 19:16 DFI_LP_WAKEUP value in APD DFI_LP_REQ mode
+ //bit 12 1: exit power down slow mode(waiting PLL LOCK). 0 : fast mode.
+ //bit 11 enable DFI_LP_REQ when enter Auto power down mode.
+ //bit 10 disable DFI_clk_disable when enter auto power down mode.
+ //bit 9:0 0 disable auto power down mode.
+ //non zero value to enable auto power down when DMC is in idle state for this number of clock cycles.
+#define DMC_DRAM_ASR_CTRL ((0x008d << 2) + 0xfe036400)
+ //bit 31. enable RETRAIN PHY after auto selfrefresh exit. for AM_PHY only.
+ //bit 30. in DDR3/4 mode, send ZQCL command after exit from auto self refresh mode.
+ //bit 29. enable PHY clock in LP2 mode. 1: enable. 0 : disable.
+ //bit 28. enable dmc wait 10us after LP2 mode exit if it's long time the PHY in LP2 mode..
+ //bit [27:24] DFI_LP_WAKEUP value in self refresh DFI_LP_REQ mode.
+ //bit 23 : send REFRESH command after exit from auto self refersh mode(ASR).
+ //bit 22 : send REFERSH command before enter to Auto self refresh mode(ASR).
+ //bit 21 : send ZQCS command after exit from Auto self refresh mode(ASR).
+ //bit 20 : send dfi_ctrl_upd after exit from ASR mode
+ //bit 19 : send power down command when enter ASR mode. //for LPDDR4 only.
+ //bit 18 : set the PHY enter LP2 mode after enter ASR mode.
+ //bit 17 : send DFI_LP_REQ after enter ASR mode.
+ //bit 16 : set DFI_CLK_DISABLE after enter ASR mode.
+ //bit 15:0. 0 disable auto ASR mode.
+ // Non-zero valule enable ASR mode. when DMC is in idle state for this number of clock cycles, the DMC will enter ASR mode.
+#define DMC_DRAM_REFR_CTRL ((0x0092 << 2) + 0xfe036400)
+ //bit 22 dmc to control DFI_CTRLUPD_REQ with zq generation together.
+ //bit 21 dmc to control PHY ZQ generation enable.
+ //bit 20 dmc to control zqlat(in LPDDR4 mode) generation enable.
+ //bit 19 dmc to control zqcs1 generation enable.
+ //bit 18 dmc to control zqcs0 generation enable.
+ //bit 17:8 auto refresh request pending cnt if there's page hit request.
+ //bit 7 retrain enable for auto refresh requent. 1: enable. 0: disable.
+ //bit 6 Disabled auto refresh command if over 16 auto refresh command sent in 2 TREFI_DDR3 period
+ //bit 5 enable dmc send ZQCS command .
+ //bit 4. enable dmc send DFI_CTRUPD_REQ.
+ //bit 3:1. how many refresh command send for one period. = this number + 1
+ //bit 0. enable dmc send auto refresh command.
+#define DMC_DRAM_FREQ_CTRL ((0x0093 << 2) + 0xfe036400)
+//bit 31 . write 1 to change freqency read 0: finished.
+//bit 30. waiting for software to send some manual command. 1 : waiting. 0 : not ready yet.
+//bit 29:22. not used.
+//bit 21 after Freqchange send PHY ZQ update.
+//bit 20 send CTRLUPD_REQ to PHY after freq_change finished.
+//bit 19:16. how many cycles to send PLL change req after init_complete signal to low.
+//bit 15. freq pre config_en. Before freq enter stop state let DMC configure DDR SDRAM.
+//bit 14. freq post config_en. After freq enter stop state let DMC configure DDR SDRAM.
+//bit 13. send zqcl after freq change in DDR3/4 mode.
+//bit 12. send zqcs after freq change. 1: enable. 0 not send.
+//bit 11. in AUTO MRW fucntion: the data format. 1: use USR_CMD format. 0: MRW format.
+//bit 10. AUTO MRW function: 1 use hardware auto MRW function. 0: don't do auto MRW.
+//bit 9. 1 : FREQ MRW done. let FREQ change machine continue.
+//bit 8 FREQ WAIT. 1 when freq change finishes, state machine stop at self refresh state in case there's something need to handle.
+ // 0 after freq change finishes the state machine go back to access state.
+//bit 7 when change PLL setting, disable dmc clock
+//bit 6 when change PLL setting, disable PHY DfiClk and DfiCtlClk.
+//bit 5 check vpu_sleep_en ==1 when do FREQ change. if vpu_sleep_en == 0, just wait.
+//bit 4 nxt frequency selection. 1 = freq1. 0 = freq0.
+//bit 3:1. not used.
+//bit 0. current frequency selection.
+#define DMC_DRAM_SCFG ((0x0094 << 2) + 0xfe036400)
+ // bit 2:0 only one bit can be high at same time.
+ // bit 2 1 : to ask PCTL enter ACCESS STATE. 0 : deassert the request.
+ // bit 1 1 : to ask PCTL enter SELF REFRESH STATE. 0 : deassert the request.
+ // bit 0 1 : to ask PCTL enter STOP/CONFIG STATE . 0 : deassert the request.
+#define DMC_DRAM_STAT ((0x0095 << 2) + 0xfe036400)
+ //bit 31 rd latency error. 1: means after dfiphytrdlat cycles, the read data still not back.
+ //bit 28:24 dram_sr_state
+ //bit 23:20 stop_st
+ //bit 19:15 sleep_st
+ //bit 14:12 ACCESS STATUS 0 : ACCESS is in normal working mode.
+ //1 : ACCESS sending precharege command.
+ //2 : ACCESS sending AUTO REFESH command.
+ //3 : ACCESS sending DIF_CTRLUPD_REQ command.
+ //4 : ACCESS sending ZQCS command to DDR DRAM(ZQCAL for LPDDR4).
+ //5 : ACCESS sending ZQLATCH command to LPDDR4 only.
+ //bit 11:8 APD STATUS: 0 : APD_IDLE
+ //1 : APD sending PRECHARGE command
+ //2 : APD sending CKE low command
+ //3 : APD sending DISABLE DRAM CLOCK command
+ //4 : APD sending DFI_LP_CTRL_REQ
+ //5 : APD in Auto Power down mode.
+ //6 : APD deassert DFI_LP_CTRL_REQ
+ //7 : APD sending enable DRAM CLOCK command
+ //8 : APD sending out CKE high command.
+ //bit 7:4: DRAM_STATUS: 0 : DRAM IDLE
+ //1 : DRAM_STOP/DRAM_CFG
+ //2 : DRAM_ACCESS
+ //3 : DRAM_SLEEP
+ //4 : DRAM APD(AUTO POWER DOWN).
+ //5 : IDLE -> STOP/CONFIG
+ //6 : STOP -> SLEEP
+ //7 : STOP -> ACCESS
+ //8 : ACCESS -> SLEEP.
+ //9 : ACCESS -> STOP
+ //A : ACCESS -> APD
+ //B : SLEEP -> STOP
+ //C : SLEEP -> ACCESS
+ //D : APD -> ACCESS
+ //bit 3 reserved.
+ //bit 2 1 : DRAM enter normal working state.
+ //bit 1 1 : DRAM enter sleep state. self refresh state.
+ //bit 0 1 : dram enter cfg state.
+#define DMC_DRAM_STAT1 ((0x0096 << 2) + 0xfe036400)
+ //bit 11:8 freq_st.
+ //4'h0 : IDLE
+ //4'h1 : FREQ_CHECK_VPU
+ //4'h2 : FREQ_WAITING_STOP
+ //4'h3 : FREQ_DRAM_CFG. waiting DMC/software to send special MRW/MPC command to configure DDR SDRAM either before Freq change or after freq change.
+ //4'h4 : FREQ_SELF_REFR_ST.
+ //4'h5 : FREQ_SET_DFI_FREQ.
+ //4'h6 : FREQ_DFI_INIT_START_HIGH.
+ //4'h7 : FREQ_CHANGE PLL_ST.
+ //4'h8 : FREQ_UPDATA REG.
+ //4'h9 : FREQ_DFI_INIT_START_LOW.
+ //4'ha : FREQ_WAITING_FINISH
+ //4'hb : FREQ_ZQCS
+ //4'hc : FREQ_ZQ_LATCH
+ //4'hd : FREQ_PVT
+ //bit 7:5 train_st
+ //bit 4:0 dram_phy_st
+#define DMC_PHY_RETRAINING_CTRL ((0x0097 << 2) + 0xfe036400)
+ //bit 31 : phy_retraining enable.
+ //bit 30 : check vpu sleep_en.
+ //bit 25:24 : retraining dfi_freq[4:3], the [2:0] bit still use the dfi_freq bits to keep the frequency.
+ //bit 23:0: retraining period unit : 100ns.
+#define DMC_DFI_ERR_STAT ((0x0098 << 2) + 0xfe036400)
+ //LPDDR4 PHY DFI error infomation.
+ //bit 31:20. not used.
+ //bit 9. ddr0_dfi_error
+ //bit 8:5 ddr0_dfi_error_info.
+ //bit 4. ddr1_dfi_error.
+ //bit 3:0. ddr1_dfi_error_info.
+#define DMC_LP2_TIMER ((0x009a << 2) + 0xfe036400)
+//bit 15:0. timer setting to measure how long the chip is entered LP2 mode.
+//this timer is 40bits counter with DMC PCLK.
+//we use the high 16bits to compare this register. if the counter is large than this number, that means the PHY need addition 10us after wakeup the PHY and before exit self_refresh mode.
+#define DMC_DRAM_COMPLETE_WAIT ((0x009b << 2) + 0xfe036400)
+ //read only how long to waiting for DFI_INIT_COMPLETE become high after DFI_INIT_START triggered.
+#define DMC_DRAM_DFI_SWAP_0 ((0x00a0 << 2) + 0xfe036400)
+ //bit 5:0. dfi_act_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_1 ((0x00a1 << 2) + 0xfe036400)
+ //bit 5:0. dfi_ras_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_2 ((0x00a2 << 2) + 0xfe036400)
+ //bit 5:0. dfi_cas_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_3 ((0x00a3 << 2) + 0xfe036400)
+ //bit 5:0. dfi_we_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_4 ((0x00a4 << 2) + 0xfe036400)
+ //bit 5:0. dfi_bg0 function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_5 ((0x00a5 << 2) + 0xfe036400)
+ //bit 5:0. dfi_bg[1] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_6 ((0x00a6 << 2) + 0xfe036400)
+ //bit 5:0. dfi_ba[0] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_7 ((0x00a7 << 2) + 0xfe036400)
+ //bit 5:0. dfi_ba[1] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_8 ((0x00a8 << 2) + 0xfe036400)
+ //bit 5:0. dfi_ba[2] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_9 ((0x00a9 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[0] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_10 ((0x00aa << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[1] function select
+#define DMC_DRAM_DFI_SWAP_11 ((0x00ab << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[2] function select
+#define DMC_DRAM_DFI_SWAP_12 ((0x00ac << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[3] function select
+#define DMC_DRAM_DFI_SWAP_13 ((0x00ad << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[4] function select
+#define DMC_DRAM_DFI_SWAP_14 ((0x00ae << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[5] function select
+#define DMC_DRAM_DFI_SWAP_15 ((0x00af << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[6] function select
+#define DMC_DRAM_DFI_SWAP_16 ((0x00b0 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[7] function select
+#define DMC_DRAM_DFI_SWAP_17 ((0x00b1 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[8] function select
+#define DMC_DRAM_DFI_SWAP_18 ((0x00b2 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[9] function select
+#define DMC_DRAM_DFI_SWAP_19 ((0x00b3 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[10] function select
+#define DMC_DRAM_DFI_SWAP_20 ((0x00b4 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[11] function select
+#define DMC_DRAM_DFI_SWAP_21 ((0x00b5 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[12] function select
+#define DMC_DRAM_DFI_SWAP_22 ((0x00b6 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[13] function select
+#define DMC_DRAM_DFI_SWAP_23 ((0x00b7 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[14] function select
+#define DMC_DRAM_DFI_SWAP_24 ((0x00b8 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[15] function select
+#define DMC_DRAM_DFI_SWAP_25 ((0x00b9 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[16] function select
+#define DMC_DRAM_DFI_SWAP_26 ((0x00ba << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[17] function select
+#define DMC_DRAM_CMD ((0x00d0 << 2) + 0xfe036400)
+ //bit 31. cmd done. write 0 to clean.
+ //bit 30. data done. write 0 to clean.
+ //bit 5. user defined command.
+ //bit 4. LPDDR4 MPC write data command( MPC WR FIFO).
+ //bit 3. LPDDR4 MPC read data command (MPC RD Calibration and RD FIFO).
+ //bit 2. LPDDR4 MPC-1 command ( NOP, Start DQS interval ....)
+ //bit 1. mrr comand.
+ //bit 0. mrw command.
+#define DMC_DRAM_CMD_CODE ((0x00d1 << 2) + 0xfe036400)
+ //bit 31:28 user command case: = {act_n, ras_n, cas_n, we_n}
+ //bit 27:26. 128bits data cycles . 0: 1 clock cycles; 1: 2 clock cycles; 2: 3 clock cycles; 3:4 clock cycles.
+ // LPDDR4 : 4 clock cycles;
+ // DDR3/4/LPDDR3 : 2 clock cycles.
+ //bit 25 MRW/MRR/MPC command rank 1 select. 1: select. 0: not select.
+ //bit 24. MRW/MRR/MPC command rank 0 select. 1: select. 0: not select.
+ //bit 23:16 MR addr. DDR4 case : 18:16 ba[2:0]. 20:19 BG[1:0].
+ //bit 15:0 opcode.
+#define DMC_DRAM_CMD_TIME ((0x00d2 << 2) + 0xfe036400)
+//bit 31:16 PRE CMD timer. //delay how many cycle to start the command.
+//bit 15:0 POST CMD timer //delay how many cycle after the command execute.
+#define DMC_DRAM_WSTRB0 ((0x00d3 << 2) + 0xfe036400)
+#define DMC_DRAM_WSTRB1 ((0x00d4 << 2) + 0xfe036400)
+#define DMC_DRAM_RDBI0 ((0x00d5 << 2) + 0xfe036400)
+ //MPC RD FIFO command DBI read back data
+ //bit 31:16 the second cycle.
+ //bit 15:0 the first cycle.
+#define DMC_DRAM_RDBI1 ((0x00d6 << 2) + 0xfe036400)
+ //MPC RD FIFO command DBI read back data
+ //bit 31:16. the Forth cycle.
+ //bit 15:0. the third cycle.
+//WD0~16 and RD0~16 can be used as MRW command as Frequency change .
+//WD0~16 is for Freq1 DRAM MR setting, it would send to DRAM right before FREQ0-> FREQ1
+//RD0_16 is for Freq0 DRAM MR setting. it would send to DRAM right before FREQ1-> FREQ0.
+//each register can be one MRW command. So total 16 MRW command can be sent to DRAM.
+//The register formats:
+//bit 31. MRW/USER comand enable. 1: enabled command. 0 not enabled.
+//bit 30. last MRW/USER command. if this bit =1, After send this command, the DRAM controller will contine frequency next stage.
+//bit 29:26. USER COMMAND parameter: in DDR3/DDR4. {act_n, ras_n, cas_n, we_n} value for user command
+ //in LPDDR4. bit 16: 1 4 cycles command. 0 2 cycles command.
+//bit 25 MRW/USER command rank 1 select. 1: select. 0: not select.
+//bit 24. MRW/USER command rank 0 select. 1: select. 0: not select.
+//bit 23:0. USER command.
+ //DDR3: 18:16 bank address. 15:0: address.
+ //DDR4: 20:19 bank group address. 18:16: bank address. 15:0 address.
+ //LPDDR3: 9:0. rising edge address. 19:10. falling edge address.
+ //LPDDR4. 5:0, first edge address, 11:6 second edge address, 17:12: third edge address. 23:18, forth edge address.
+ //MRW command format:
+ //bit 23:16 MR addr. DDR4 case : 18:16 ba[2:0]. 20:19 BG[1:0].
+ //bit 15:0 opcode.
+#define DMC_DRAM_WD0 ((0x00e0 << 2) + 0xfe036400)
+#define DMC_DRAM_WD1 ((0x00e1 << 2) + 0xfe036400)
+#define DMC_DRAM_WD2 ((0x00e2 << 2) + 0xfe036400)
+#define DMC_DRAM_WD3 ((0x00e3 << 2) + 0xfe036400)
+#define DMC_DRAM_WD4 ((0x00e4 << 2) + 0xfe036400)
+#define DMC_DRAM_WD5 ((0x00e5 << 2) + 0xfe036400)
+#define DMC_DRAM_WD6 ((0x00e6 << 2) + 0xfe036400)
+#define DMC_DRAM_WD7 ((0x00e7 << 2) + 0xfe036400)
+#define DMC_DRAM_WD8 ((0x00e8 << 2) + 0xfe036400)
+#define DMC_DRAM_WD9 ((0x00e9 << 2) + 0xfe036400)
+#define DMC_DRAM_WD10 ((0x00ea << 2) + 0xfe036400)
+#define DMC_DRAM_WD11 ((0x00eb << 2) + 0xfe036400)
+#define DMC_DRAM_WD12 ((0x00ec << 2) + 0xfe036400)
+#define DMC_DRAM_WD13 ((0x00ed << 2) + 0xfe036400)
+#define DMC_DRAM_WD14 ((0x00ee << 2) + 0xfe036400)
+#define DMC_DRAM_WD15 ((0x00ef << 2) + 0xfe036400)
+#define DMC_DRAM_RD0 ((0x00f0 << 2) + 0xfe036400)
+#define DMC_DRAM_RD1 ((0x00f1 << 2) + 0xfe036400)
+#define DMC_DRAM_RD2 ((0x00f2 << 2) + 0xfe036400)
+#define DMC_DRAM_RD3 ((0x00f3 << 2) + 0xfe036400)
+#define DMC_DRAM_RD4 ((0x00f4 << 2) + 0xfe036400)
+#define DMC_DRAM_RD5 ((0x00f5 << 2) + 0xfe036400)
+#define DMC_DRAM_RD6 ((0x00f6 << 2) + 0xfe036400)
+#define DMC_DRAM_RD7 ((0x00f7 << 2) + 0xfe036400)
+#define DMC_DRAM_RD8 ((0x00f8 << 2) + 0xfe036400)
+#define DMC_DRAM_RD9 ((0x00f9 << 2) + 0xfe036400)
+#define DMC_DRAM_RD10 ((0x00fa << 2) + 0xfe036400)
+#define DMC_DRAM_RD11 ((0x00fb << 2) + 0xfe036400)
+#define DMC_DRAM_RD12 ((0x00fc << 2) + 0xfe036400)
+#define DMC_DRAM_RD13 ((0x00fd << 2) + 0xfe036400)
+#define DMC_DRAM_RD14 ((0x00fe << 2) + 0xfe036400)
+#define DMC_DRAM_RD15 ((0x00ff << 2) + 0xfe036400)
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh
+//
+//`define DMC_STICKY_REG_BASE 32'hfe036800
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe036800
+// -----------------------------------------------
+//those register is for software save some tempary value. and because it's in RAM. it won't lose if DMC get reseted.
+#define DMC_STICKY_0 ((0x0000 << 2) + 0xfe036800)
+#define DMC_STICKY_1 ((0x0001 << 2) + 0xfe036800)
+#define DMC_STICKY_2 ((0x0002 << 2) + 0xfe036800)
+#define DMC_STICKY_3 ((0x0003 << 2) + 0xfe036800)
+#define DMC_STICKY_4 ((0x0004 << 2) + 0xfe036800)
+#define DMC_STICKY_5 ((0x0005 << 2) + 0xfe036800)
+#define DMC_STICKY_6 ((0x0006 << 2) + 0xfe036800)
+#define DMC_STICKY_7 ((0x0007 << 2) + 0xfe036800)
+#define DMC_STICKY_8 ((0x0008 << 2) + 0xfe036800)
+#define DMC_STICKY_9 ((0x0009 << 2) + 0xfe036800)
+#define DMC_STICKY_10 ((0x000a << 2) + 0xfe036800)
+#define DMC_STICKY_11 ((0x000b << 2) + 0xfe036800)
+#define DMC_STICKY_12 ((0x000c << 2) + 0xfe036800)
+#define DMC_STICKY_13 ((0x000d << 2) + 0xfe036800)
+#define DMC_STICKY_14 ((0x000e << 2) + 0xfe036800)
+#define DMC_STICKY_15 ((0x000f << 2) + 0xfe036800)
+#define DMC_STICKY_16 ((0x0010 << 2) + 0xfe036800)
+#define DMC_STICKY_17 ((0x0011 << 2) + 0xfe036800)
+#define DMC_STICKY_18 ((0x0012 << 2) + 0xfe036800)
+#define DMC_STICKY_19 ((0x0013 << 2) + 0xfe036800)
+#define DMC_STICKY_20 ((0x0014 << 2) + 0xfe036800)
+#define DMC_STICKY_21 ((0x0015 << 2) + 0xfe036800)
+#define DMC_STICKY_22 ((0x0016 << 2) + 0xfe036800)
+#define DMC_STICKY_23 ((0x0017 << 2) + 0xfe036800)
+#define DMC_STICKY_24 ((0x0018 << 2) + 0xfe036800)
+#define DMC_STICKY_25 ((0x0019 << 2) + 0xfe036800)
+#define DMC_STICKY_26 ((0x001a << 2) + 0xfe036800)
+#define DMC_STICKY_27 ((0x001b << 2) + 0xfe036800)
+#define DMC_STICKY_28 ((0x001c << 2) + 0xfe036800)
+#define DMC_STICKY_29 ((0x001d << 2) + 0xfe036800)
+#define DMC_STICKY_30 ((0x001e << 2) + 0xfe036800)
+#define DMC_STICKY_31 ((0x001f << 2) + 0xfe036800)
+#define DMC_STICKY_32 ((0x0020 << 2) + 0xfe036800)
+#define DMC_STICKY_33 ((0x0021 << 2) + 0xfe036800)
+#define DMC_STICKY_34 ((0x0022 << 2) + 0xfe036800)
+#define DMC_STICKY_35 ((0x0023 << 2) + 0xfe036800)
+#define DMC_STICKY_36 ((0x0024 << 2) + 0xfe036800)
+#define DMC_STICKY_37 ((0x0025 << 2) + 0xfe036800)
+#define DMC_STICKY_38 ((0x0026 << 2) + 0xfe036800)
+#define DMC_STICKY_39 ((0x0027 << 2) + 0xfe036800)
+#define DMC_STICKY_40 ((0x0028 << 2) + 0xfe036800)
+#define DMC_STICKY_41 ((0x0029 << 2) + 0xfe036800)
+#define DMC_STICKY_42 ((0x002a << 2) + 0xfe036800)
+#define DMC_STICKY_43 ((0x002b << 2) + 0xfe036800)
+#define DMC_STICKY_44 ((0x002c << 2) + 0xfe036800)
+#define DMC_STICKY_45 ((0x002d << 2) + 0xfe036800)
+#define DMC_STICKY_46 ((0x002e << 2) + 0xfe036800)
+#define DMC_STICKY_47 ((0x002f << 2) + 0xfe036800)
+#define DMC_STICKY_48 ((0x0030 << 2) + 0xfe036800)
+#define DMC_STICKY_49 ((0x0031 << 2) + 0xfe036800)
+#define DMC_STICKY_50 ((0x0032 << 2) + 0xfe036800)
+#define DMC_STICKY_51 ((0x0033 << 2) + 0xfe036800)
+#define DMC_STICKY_52 ((0x0034 << 2) + 0xfe036800)
+#define DMC_STICKY_53 ((0x0035 << 2) + 0xfe036800)
+#define DMC_STICKY_54 ((0x0036 << 2) + 0xfe036800)
+#define DMC_STICKY_55 ((0x0037 << 2) + 0xfe036800)
+#define DMC_STICKY_56 ((0x0038 << 2) + 0xfe036800)
+#define DMC_STICKY_57 ((0x0039 << 2) + 0xfe036800)
+#define DMC_STICKY_58 ((0x003a << 2) + 0xfe036800)
+#define DMC_STICKY_59 ((0x003b << 2) + 0xfe036800)
+#define DMC_STICKY_60 ((0x003c << 2) + 0xfe036800)
+#define DMC_STICKY_61 ((0x003d << 2) + 0xfe036800)
+#define DMC_STICKY_62 ((0x003e << 2) + 0xfe036800)
+#define DMC_STICKY_63 ((0x003f << 2) + 0xfe036800)
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh
+//
+//========================================================================
+// STARTUP
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe02e000
+// -----------------------------------------------
+#define STARTUP_LOCK ((0x0000 << 2) + 0xfe02e000)
+#define STARTUP_DFU_STS ((0x0004 << 2) + 0xfe02e000)
+#define STARTUP_BOOT_SRC ((0x0008 << 2) + 0xfe02e000)
+#define STARTUP_TEE_REQ_DFU ((0x0009 << 2) + 0xfe02e000)
+#define STARTUP_BOOT_OVERRIDE ((0x000a << 2) + 0xfe02e000)
+#define STARTUP_COLD_BOOT_CNT ((0x000b << 2) + 0xfe02e000)
+#define STARTUP_KEY_PRESERVE ((0x000c << 2) + 0xfe02e000)
+//========================================================================
+// MIPI_DSI_PHY
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe01c000
+// -----------------------------------------------
+//`define MIPI_DSI_PHY_START 8'h00
+//`define MIPI_DSI_PHY_END 16'hffff
+#define MIPI_DSI_PHY_CTRL ((0x0000 << 2) + 0xfe01c000)
+ //bit 31. soft reset for the phy. 1 = reset. 0 = dessert the reset.
+ //bit 30. clock lane soft reset.
+ //bit 29. data byte lane 3 soft reset.
+ //bit 28. data byte lane 2 soft reset.
+ //bit 27. data byte lane 1 soft reset.
+ //bit 26. data byte lane 0 soft reset.
+ //bit 5. LPDT data endian. 1 = transfer the high bit first. 0 : transfer the low bit first.
+ //bit 4. HS data endian.
+ //bit 3. force data byte lane in stop mode.
+ //bit 2. force data byte lane 0 in reciever mode.
+ //bit 1. write 1 to sync the txclkesc input. the internal logic have to use txclkesc to decide Txvalid and Txready.
+ //bit 0. enalbe the MIPI DSI PHY TxDDRClk.
+#define MIPI_DSI_CHAN_CTRL ((0x0001 << 2) + 0xfe01c000)
+ //bit 31. clk lane tx_hs_en control selection. 1 = from register. 0 use clk lane state machine.
+ //bit 30. register bit for clock lane tx_hs_en.
+ //bit 29. clk lane tx_lp_en contrl selection. 1 = from register. 0 from clk lane state machine.
+ //bit 28. register bit for clock lane tx_lp_en.
+ //bit 27. chan0 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 26. register bit for chan0 tx_hs_en.
+ //bit 25. chan0 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 24. register bit from chan0 tx_lp_en.
+ //bit 23. chan0 rx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 22. register bit from chan0 rx_lp_en.
+ //bit 21. chan0 contention detection enable control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 20. register bit from chan0 contention dectection enable.
+ //bit 19. chan1 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 18. register bit for chan1 tx_hs_en.
+ //bit 17. chan1 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 16. register bit from chan1 tx_lp_en.
+ //bit 15. chan2 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 14. register bit for chan2 tx_hs_en.
+ //bit 13. chan2 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 12. register bit from chan2 tx_lp_en.
+ //bit 11. chan3 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 10. register bit for chan3 tx_hs_en.
+ //bit 9. chan3 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 8. register bit from chan3 tx_lp_en.
+ //bit 4. clk chan power down. this bit is also used as the power down of the whole MIPI_DSI_PHY.
+ //bit 3. chan3 power down.
+ //bit 2. chan2 power down.
+ //bit 1. chan1 power down.
+ //bit 0. chan0 power down.
+#define MIPI_DSI_CHAN_STS ((0x0002 << 2) + 0xfe01c000)
+ //bit 24. chan0 TX->RX turn can't accept the ACK command from slave watch dog triggered. write 1 to clear the status bit.
+ //bit 23. chan0 RX ESC command watch dog triggered. write 1 to clean this bit.
+ //bit
+#define MIPI_DSI_CLK_TIM ((0x0003 << 2) + 0xfe01c000)
+ //bit 31:24. TCLK_PREPARE.
+ //bit 23:16. TCLK_ZERO.
+ //bit 15:8. TCLK_POST.
+ //bit 7:0. TCLK_TRAIL.
+#define MIPI_DSI_HS_TIM ((0x0004 << 2) + 0xfe01c000)
+ //bit 31:24. THS_PREPARE.
+ //bit 23:16. THS_ZERO.
+ //bit 15:8. THS_TRAIL.
+ //bit 7:0. THS_EXIT.
+#define MIPI_DSI_LP_TIM ((0x0005 << 2) + 0xfe01c000)
+ //bit 31:24. tTA_GET.
+ //bit 23:16. tTA_GO.
+ //bit 15:8. tTA_SURE.
+ //bit 7:0. tLPX.
+#define MIPI_DSI_ANA_UP_TIM ((0x0006 << 2) + 0xfe01c000)
+ //wait time to MIPI DIS analog ready.
+#define MIPI_DSI_INIT_TIM ((0x0007 << 2) + 0xfe01c000)
+ // TINIT.
+#define MIPI_DSI_WAKEUP_TIM ((0x0008 << 2) + 0xfe01c000)
+ //TWAKEUP.
+#define MIPI_DSI_LPOK_TIM ((0x0009 << 2) + 0xfe01c000)
+ //bit 31:0 when in RxULPS state, RX reciever is in sleep mode.
+ //every MIPI_DSI_ULPS_CHECK period, the reciever would be enabled once, and waiting this timer period to get the stable input.
+#define MIPI_DSI_LP_WCHDOG ((0x000a << 2) + 0xfe01c000)
+ //bit 31:0 watch dog timer for MIPI DSI LP receive state.
+#define MIPI_DSI_ANA_CTRL ((0x000b << 2) + 0xfe01c000)
+ //bit 31:0 tMBIAS. timer to wait for analog mBIAS voltage stable.
+#define MIPI_DSI_CLK_TIM1 ((0x000c << 2) + 0xfe01c000)
+ //bit 31:8 not used.
+ //bit 7:0 tCLK_PRE
+#define MIPI_DSI_TURN_WCHDOG ((0x000d << 2) + 0xfe01c000)
+ //bit 31:0 watch dog timer for lane 0 LP turn around waiting time.
+#define MIPI_DSI_ULPS_CHECK ((0x000e << 2) + 0xfe01c000)
+ //bit 31:0 when Lane0 in LP recieve state, if the another side sent Low power command, using this timer to enable Tcheck the another size wakeup nor not.
+#define MIPI_DSI_TEST_CTRL0 ((0x000f << 2) + 0xfe01c000)
+#define MIPI_DSI_TEST_CTRL1 ((0x0010 << 2) + 0xfe01c000)
+//========================================================================
+// Temp sensor PLL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe020000
+// -----------------------------------------------
+#define TS_PLL_CFG_REG1 ((0x0001 << 2) + 0xfe020000)
+#define TS_PLL_CFG_REG2 ((0x0002 << 2) + 0xfe020000)
+#define TS_PLL_CFG_REG3 ((0x0003 << 2) + 0xfe020000)
+#define TS_PLL_CFG_REG4 ((0x0004 << 2) + 0xfe020000)
+#define TS_PLL_CFG_REG5 ((0x0005 << 2) + 0xfe020000)
+#define TS_PLL_CFG_REG6 ((0x0006 << 2) + 0xfe020000)
+#define TS_PLL_CFG_REG7 ((0x0007 << 2) + 0xfe020000)
+#define TS_PLL_STAT0 ((0x0010 << 2) + 0xfe020000)
+#define TS_PLL_STAT1 ((0x0011 << 2) + 0xfe020000)
+#define TS_PLL_STAT2 ((0x0012 << 2) + 0xfe020000)
+#define TS_PLL_STAT3 ((0x0013 << 2) + 0xfe020000)
+#define TS_PLL_STAT4 ((0x0014 << 2) + 0xfe020000)
+#define TS_PLL_STAT5 ((0x0015 << 2) + 0xfe020000)
+#define TS_PLL_STAT6 ((0x0016 << 2) + 0xfe020000)
+#define TS_PLL_STAT7 ((0x0017 << 2) + 0xfe020000)
+#define TS_PLL_STAT8 ((0x0018 << 2) + 0xfe020000)
+#define TS_PLL_STAT9 ((0x0019 << 2) + 0xfe020000)
+//========================================================================
+// Temp sensor DDR
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe022000
+// -----------------------------------------------
+#define TS_DDR_CFG_REG1 ((0x0001 << 2) + 0xfe022000)
+#define TS_DDR_CFG_REG2 ((0x0002 << 2) + 0xfe022000)
+#define TS_DDR_CFG_REG3 ((0x0003 << 2) + 0xfe022000)
+#define TS_DDR_CFG_REG4 ((0x0004 << 2) + 0xfe022000)
+#define TS_DDR_CFG_REG5 ((0x0005 << 2) + 0xfe022000)
+#define TS_DDR_CFG_REG6 ((0x0006 << 2) + 0xfe022000)
+#define TS_DDR_CFG_REG7 ((0x0007 << 2) + 0xfe022000)
+#define TS_DDR_STAT0 ((0x0010 << 2) + 0xfe022000)
+#define TS_DDR_STAT1 ((0x0011 << 2) + 0xfe022000)
+#define TS_DDR_STAT2 ((0x0012 << 2) + 0xfe022000)
+#define TS_DDR_STAT3 ((0x0013 << 2) + 0xfe022000)
+#define TS_DDR_STAT4 ((0x0014 << 2) + 0xfe022000)
+#define TS_DDR_STAT5 ((0x0015 << 2) + 0xfe022000)
+#define TS_DDR_STAT6 ((0x0016 << 2) + 0xfe022000)
+#define TS_DDR_STAT7 ((0x0017 << 2) + 0xfe022000)
+#define TS_DDR_STAT8 ((0x0018 << 2) + 0xfe022000)
+#define TS_DDR_STAT9 ((0x0019 << 2) + 0xfe022000)
+//========================================================================
+// Temp sensor GPU
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe035000
+// -----------------------------------------------
+//`define TS_GPU_CFG_REG1 8'h01
+//`define TS_GPU_CFG_REG2 8'h02
+//`define TS_GPU_CFG_REG3 8'h03
+//`define TS_GPU_CFG_REG4 8'h04
+//`define TS_GPU_CFG_REG5 8'h05
+//`define TS_GPU_CFG_REG6 8'h06
+//`define TS_GPU_CFG_REG7 8'h07
+//`define TS_GPU_STAT0 8'h10
+//`define TS_GPU_STAT1 8'h11
+//`define TS_GPU_STAT2 8'h12
+//`define TS_GPU_STAT3 8'h13
+//`define TS_GPU_STAT4 8'h14
+//`define TS_GPU_STAT5 8'h15
+//`define TS_GPU_STAT6 8'h16
+//`define TS_GPU_STAT7 8'h17
+//`define TS_GPU_STAT8 8'h18
+//`define TS_GPU_STAT9 8'h19
+//========================================================================
+// RNG
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe034000
+// -----------------------------------------------
+//========================================================================
+// ACODEC
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe01a000
+// -----------------------------------------------
+#define ACODEC_0 ((0x0000 << 2) + 0xfe01a000)
+#define ACODEC_1 ((0x0001 << 2) + 0xfe01a000)
+#define ACODEC_2 ((0x0002 << 2) + 0xfe01a000)
+#define ACODEC_3 ((0x0003 << 2) + 0xfe01a000)
+#define ACODEC_4 ((0x0004 << 2) + 0xfe01a000)
+#define ACODEC_5 ((0x0005 << 2) + 0xfe01a000)
+#define ACODEC_6 ((0x0006 << 2) + 0xfe01a000)
+#define ACODEC_7 ((0x0007 << 2) + 0xfe01a000)
+//========================================================================
+// AML USB PHY A
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe03c000
+// -----------------------------------------------
+#define AMLUSB_A0 ((0x0000 << 2) + 0xfe03c000)
+#define AMLUSB_A1 ((0x0001 << 2) + 0xfe03c000)
+#define AMLUSB_A2 ((0x0002 << 2) + 0xfe03c000)
+#define AMLUSB_A3 ((0x0003 << 2) + 0xfe03c000)
+#define AMLUSB_A4 ((0x0004 << 2) + 0xfe03c000)
+#define AMLUSB_A5 ((0x0005 << 2) + 0xfe03c000)
+#define AMLUSB_A6 ((0x0006 << 2) + 0xfe03c000)
+#define AMLUSB_A7 ((0x0007 << 2) + 0xfe03c000)
+#define AMLUSB_A8 ((0x0008 << 2) + 0xfe03c000)
+#define AMLUSB_A9 ((0x0009 << 2) + 0xfe03c000)
+#define AMLUSB_A10 ((0x000a << 2) + 0xfe03c000)
+#define AMLUSB_A11 ((0x000b << 2) + 0xfe03c000)
+#define AMLUSB_A12 ((0x000c << 2) + 0xfe03c000)
+#define AMLUSB_A13 ((0x000d << 2) + 0xfe03c000)
+#define AMLUSB_A14 ((0x000e << 2) + 0xfe03c000)
+#define AMLUSB_A15 ((0x000f << 2) + 0xfe03c000)
+#define AMLUSB_A16 ((0x0010 << 2) + 0xfe03c000)
+#define AMLUSB_A17 ((0x0011 << 2) + 0xfe03c000)
+#define AMLUSB_A18 ((0x0012 << 2) + 0xfe03c000)
+#define AMLUSB_A19 ((0x0013 << 2) + 0xfe03c000)
+#define AMLUSB_A20 ((0x0014 << 2) + 0xfe03c000)
+#define AMLUSB_A21 ((0x0015 << 2) + 0xfe03c000)
+#define AMLUSB_A22 ((0x0016 << 2) + 0xfe03c000)
+#define AMLUSB_A23 ((0x0017 << 2) + 0xfe03c000)
+#define AMLUSB_A24 ((0x0018 << 2) + 0xfe03c000)
+#define AMLUSB_A25 ((0x0019 << 2) + 0xfe03c000)
+#define AMLUSB_A26 ((0x001a << 2) + 0xfe03c000)
+#define AMLUSB_A27 ((0x001b << 2) + 0xfe03c000)
+#define AMLUSB_A28 ((0x001c << 2) + 0xfe03c000)
+#define AMLUSB_A29 ((0x001d << 2) + 0xfe03c000)
+#define AMLUSB_A30 ((0x001e << 2) + 0xfe03c000)
+#define AMLUSB_A31 ((0x001f << 2) + 0xfe03c000)
+//========================================================================
+// AML USB PHY B
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe03e000
+// -----------------------------------------------
+#define AMLUSB_B0 ((0x0000 << 2) + 0xfe03e000)
+#define AMLUSB_B1 ((0x0001 << 2) + 0xfe03e000)
+#define AMLUSB_B2 ((0x0002 << 2) + 0xfe03e000)
+#define AMLUSB_B3 ((0x0003 << 2) + 0xfe03e000)
+#define AMLUSB_B4 ((0x0004 << 2) + 0xfe03e000)
+#define AMLUSB_B5 ((0x0005 << 2) + 0xfe03e000)
+#define AMLUSB_B6 ((0x0006 << 2) + 0xfe03e000)
+#define AMLUSB_B7 ((0x0007 << 2) + 0xfe03e000)
+#define AMLUSB_B8 ((0x0008 << 2) + 0xfe03e000)
+#define AMLUSB_B9 ((0x0009 << 2) + 0xfe03e000)
+#define AMLUSB_B10 ((0x000a << 2) + 0xfe03e000)
+#define AMLUSB_B11 ((0x000b << 2) + 0xfe03e000)
+#define AMLUSB_B12 ((0x000c << 2) + 0xfe03e000)
+#define AMLUSB_B13 ((0x000d << 2) + 0xfe03e000)
+#define AMLUSB_B14 ((0x000e << 2) + 0xfe03e000)
+#define AMLUSB_B15 ((0x000f << 2) + 0xfe03e000)
+#define AMLUSB_B16 ((0x0010 << 2) + 0xfe03e000)
+#define AMLUSB_B17 ((0x0011 << 2) + 0xfe03e000)
+#define AMLUSB_B18 ((0x0012 << 2) + 0xfe03e000)
+#define AMLUSB_B19 ((0x0013 << 2) + 0xfe03e000)
+#define AMLUSB_B20 ((0x0014 << 2) + 0xfe03e000)
+#define AMLUSB_B21 ((0x0015 << 2) + 0xfe03e000)
+#define AMLUSB_B22 ((0x0016 << 2) + 0xfe03e000)
+#define AMLUSB_B23 ((0x0017 << 2) + 0xfe03e000)
+#define AMLUSB_B24 ((0x0018 << 2) + 0xfe03e000)
+#define AMLUSB_B25 ((0x0019 << 2) + 0xfe03e000)
+#define AMLUSB_B26 ((0x001a << 2) + 0xfe03e000)
+#define AMLUSB_B27 ((0x001b << 2) + 0xfe03e000)
+#define AMLUSB_B28 ((0x001c << 2) + 0xfe03e000)
+#define AMLUSB_B29 ((0x001d << 2) + 0xfe03e000)
+#define AMLUSB_B30 ((0x001e << 2) + 0xfe03e000)
+#define AMLUSB_B31 ((0x001f << 2) + 0xfe03e000)
+//========================================================================
+// PAD_CTRL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe004000
+// -----------------------------------------------
+#define PADCTRL_PIN_MUX_REG0 ((0x0000 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG1 ((0x0001 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG3 ((0x0003 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG4 ((0x0004 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG5 ((0x0005 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG6 ((0x0006 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG7 ((0x0007 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG8 ((0x0008 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG9 ((0x0009 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGA ((0x000a << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGB ((0x000b << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGC ((0x000c << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGD ((0x000d << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGE ((0x000e << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGF ((0x000f << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGG ((0x0010 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGH ((0x0011 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGI ((0x0012 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGJ ((0x0013 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL0 ((0x0020 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL1 ((0x0021 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL2 ((0x0022 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL3 ((0x0023 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL4 ((0x0024 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL5 ((0x0025 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL6 ((0x0026 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL7 ((0x0027 << 2) + 0xfe004000)
+#define PADCTRL_WORLD_SYNC_CTRL0 ((0x0028 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_MSR_CTRL0 ((0x0029 << 2) + 0xfe004000)
+#define PADCTRL_MISC_CTRL0 ((0x002a << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_I ((0x0030 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_O ((0x0031 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_OEN ((0x0032 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_PULL_EN ((0x0033 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_PULL_UP ((0x0034 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_LOCK ((0x0035 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_PROT ((0x0036 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_DS ((0x0037 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_I ((0x0040 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_O ((0x0041 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_OEN ((0x0042 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_PULL_EN ((0x0043 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_PULL_UP ((0x0044 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_LOCK ((0x0045 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_PROT ((0x0046 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_DS ((0x0047 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_DS_EXT ((0x0048 << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_I ((0x0050 << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_O ((0x0051 << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_OEN ((0x0052 << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_PULL_EN ((0x0053 << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_PULL_UP ((0x0054 << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_LOCK ((0x0055 << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_PROT ((0x0056 << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_DS ((0x0057 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_I ((0x0060 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_O ((0x0061 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_OEN ((0x0062 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_PULL_EN ((0x0063 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_PULL_UP ((0x0064 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_LOCK ((0x0065 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_PROT ((0x0066 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_DS ((0x0067 << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_I ((0x0070 << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_O ((0x0071 << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_OEN ((0x0072 << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_PULL_EN ((0x0073 << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_PULL_UP ((0x0074 << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_LOCK ((0x0075 << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_PROT ((0x0076 << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_DS ((0x0077 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_I ((0x0080 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_O ((0x0081 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_OEN ((0x0082 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_PULL_EN ((0x0083 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_PULL_UP ((0x0084 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_LOCK ((0x0085 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_PROT ((0x0086 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_DS ((0x0087 << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_I ((0x0090 << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_O ((0x0091 << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_OEN ((0x0092 << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_PULL_EN ((0x0093 << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_PULL_UP ((0x0094 << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_LOCK ((0x0095 << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_PROT ((0x0096 << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_DS ((0x0097 << 2) + 0xfe004000)
+#define PADCTRL_GPIOA_I ((0x00a0 << 2) + 0xfe004000)
+#define PADCTRL_GPIOA_O ((0x00a1 << 2) + 0xfe004000)
+#define PADCTRL_GPIOA_OEN ((0x00a2 << 2) + 0xfe004000)
+#define PADCTRL_GPIOA_PULL_EN ((0x00a3 << 2) + 0xfe004000)
+#define PADCTRL_GPIOA_PULL_UP ((0x00a4 << 2) + 0xfe004000)
+#define PADCTRL_GPIOA_LOCK ((0x00a5 << 2) + 0xfe004000)
+#define PADCTRL_GPIOA_PROT ((0x00a6 << 2) + 0xfe004000)
+#define PADCTRL_GPIOA_DS ((0x00a7 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_I ((0x00b0 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_O ((0x00b1 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_OEN ((0x00b2 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_PULL_EN ((0x00b3 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_PULL_UP ((0x00b4 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_LOCK ((0x00b5 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_PROT ((0x00b6 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_DS ((0x00b7 << 2) + 0xfe004000)
+#define PADCTRL_ANALOG_I ((0x00c0 << 2) + 0xfe004000)
+#define PADCTRL_ANALOG_EN ((0x00c1 << 2) + 0xfe004000)
+#define PADCTRL_LOCK_PIN_MUX0 ((0x00d0 << 2) + 0xfe004000)
+#define PADCTRL_LOCK_PIN_MUX1 ((0x00d1 << 2) + 0xfe004000)
+#define PADCTRL_LOCK_PIN_MUX2 ((0x00d2 << 2) + 0xfe004000)
+#define PADCTRL_LOCK_PIN_MUX3 ((0x00d3 << 2) + 0xfe004000)
+#define PADCTRL_LOCK_PIN_MUX4 ((0x00d4 << 2) + 0xfe004000)
+#define PADCTRL_PROT_PIN_MUX0 ((0x00d8 << 2) + 0xfe004000)
+#define PADCTRL_PROT_PIN_MUX1 ((0x00d9 << 2) + 0xfe004000)
+#define PADCTRL_PROT_PIN_MUX2 ((0x00da << 2) + 0xfe004000)
+#define PADCTRL_PROT_PIN_MUX3 ((0x00db << 2) + 0xfe004000)
+#define PADCTRL_PROT_PIN_MUX4 ((0x00dc << 2) + 0xfe004000)
+#define PADCTRL_MUTE_CTRL ((0x00e0 << 2) + 0xfe004000)
+#define PADCTRL_MUTE_TDM_DISA ((0x00e1 << 2) + 0xfe004000)
+#define PADCTRL_DEBUG_SEL ((0x00e2 << 2) + 0xfe004000)
+//========================================================================
+// SYS_CTRL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe010000
+// -----------------------------------------------
+#define SYSCTRL_METAL_REV0 ((0x0000 << 2) + 0xfe010000)
+#define SYSCTRL_METAL_REV1 ((0x0001 << 2) + 0xfe010000)
+#define SYSCTRL_METAL_REV2 ((0x0002 << 2) + 0xfe010000)
+#define SYSCTRL_CHIP_ID ((0x000b << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE1_REG0 ((0x0010 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE1_STICKY_REG0 ((0x0011 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE1_SEC_REG0 ((0x0012 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE1_STICKY_SEC_REG0 ((0x0013 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE_REG0 ((0x0014 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE_REG1 ((0x0015 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE_SEC_REG0 ((0x0016 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE_STICKY_REG0 ((0x0017 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE_STICKY_REG1 ((0x0018 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE_STICKY_SEC_REG0 ((0x0019 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERA_CTRL ((0x0030 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERA ((0x0031 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERB_CTRL ((0x0032 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERB ((0x0033 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERC_CTRL ((0x0034 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERC ((0x0035 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERD_CTRL ((0x0036 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERD ((0x0037 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_TIMERA_CTRL ((0x0038 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_TIMERA ((0x0039 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERE_CTRL ((0x003a << 2) + 0xfe010000)
+#define SYSCTRL_TIMERE ((0x003b << 2) + 0xfe010000)
+#define SYSCTRL_TIMERE_HI ((0x003c << 2) + 0xfe010000)
+#define SYSCTRL_TIMERF_CTRL ((0x003d << 2) + 0xfe010000)
+#define SYSCTRL_TIMERF ((0x003e << 2) + 0xfe010000)
+#define SYSCTRL_TIMERF_HI ((0x003f << 2) + 0xfe010000)
+#define SYSCTRL_TIMERG_CTRL ((0x0040 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERG ((0x0041 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERH_CTRL ((0x0042 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERH ((0x0043 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERI_CTRL ((0x0044 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERI ((0x0045 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERJ_CTRL ((0x0046 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERJ ((0x0047 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_TIMERE_CTRL ((0x0048 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_TIMERE ((0x0049 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_TIMERE_HI ((0x004a << 2) + 0xfe010000)
+#define SYSCTRL_OSC_RING_CTRL0 ((0x0050 << 2) + 0xfe010000)
+#define SYSCTRL_OSC_RING_CTRL1 ((0x0051 << 2) + 0xfe010000)
+#define SYSCTRL_AM2AXI_CTRL0 ((0x0052 << 2) + 0xfe010000)
+#define SYSCTRL_AM2AXI_STS ((0x0053 << 2) + 0xfe010000)
+#define SYSCTRL_AXI_PIPE_CTRL0 ((0x0055 << 2) + 0xfe010000)
+#define SYSCTRL_AXI_PIPE_CTRL1 ((0x0056 << 2) + 0xfe010000)
+#define SYSCTRL_TIMER90K ((0x0057 << 2) + 0xfe010000)
+#define SYSCTRL_SCR ((0x0058 << 2) + 0xfe010000)
+#define SYSCTRL_HPG_TIMER ((0x0059 << 2) + 0xfe010000)
+//`define SYSCTRL_VIPNANOQ_CTRL0 10'h5A
+#define SYSCTRL_AHB2DDR_CTRL0 ((0x005b << 2) + 0xfe010000)
+#define SYSCTRL_AHB2DDR_CTRL1 ((0x005c << 2) + 0xfe010000)
+#define SYSCTRL_POC ((0x0060 << 2) + 0xfe010000)
+#define SYSCTRL_VPU_SECURE_REG0 ((0x0061 << 2) + 0xfe010000)
+#define SYSCTRL_VPU_SECURE_REG1 ((0x0062 << 2) + 0xfe010000)
+//`define SYSCTRL_NIC_CFG0 10'h63
+#define SYSCTRL_ALERT_STS_STICKY ((0x0064 << 2) + 0xfe010000)
+#define SYSCTRL_ALERT_ENABLE ((0x0066 << 2) + 0xfe010000)
+#define SYSCTRL_ENABLE_SPIFC ((0x0068 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG0 ((0x0090 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG1 ((0x0091 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG2 ((0x0092 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG3 ((0x0093 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG4 ((0x0094 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG5 ((0x0095 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG6 ((0x0096 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG7 ((0x0097 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG0 ((0x00a0 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG1 ((0x00a1 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG2 ((0x00a2 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG3 ((0x00a3 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG4 ((0x00a4 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG5 ((0x00a5 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG6 ((0x00a6 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG7 ((0x00a7 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG0 ((0x00b0 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG1 ((0x00b1 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG2 ((0x00b2 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG3 ((0x00b3 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG4 ((0x00b4 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG5 ((0x00b5 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG6 ((0x00b6 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG7 ((0x00b7 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG0 ((0x00c0 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG1 ((0x00c1 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG2 ((0x00c2 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG3 ((0x00c3 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG4 ((0x00c4 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG5 ((0x00c5 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG6 ((0x00c6 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG7 ((0x00c7 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG8 ((0x00c8 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG9 ((0x00c9 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG10 ((0x00ca << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG11 ((0x00cb << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG12 ((0x00cc << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG13 ((0x00cd << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG14 ((0x00ce << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG15 ((0x00cf << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG16 ((0x00d0 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG17 ((0x00d1 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG18 ((0x00d2 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG19 ((0x00d3 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG20 ((0x00d4 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG21 ((0x00d5 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG22 ((0x00d6 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG23 ((0x00d7 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG24 ((0x00d8 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG25 ((0x00d9 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG26 ((0x00da << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG27 ((0x00db << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG28 ((0x00dc << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG29 ((0x00dd << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG30 ((0x00de << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG31 ((0x00df << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG0 ((0x00e0 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG1 ((0x00e1 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG2 ((0x00e2 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG3 ((0x00e3 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG4 ((0x00e4 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG5 ((0x00e5 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG6 ((0x00e6 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG7 ((0x00e7 << 2) + 0xfe010000)
+#define SYSCTRL_MSG_INDEX0_STICKY ((0x00f0 << 2) + 0xfe010000)
+#define SYSCTRL_MSG_INDEX1_STICKY ((0x00f1 << 2) + 0xfe010000)
+#define SYSCTRL_MSG_INDEX2_STICKY ((0x00f2 << 2) + 0xfe010000)
+#define SYSCTRL_MSG_INDEX3_STICKY ((0x00f3 << 2) + 0xfe010000)
+//========================================================================
+// CLK_CTRL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe000000
+// -----------------------------------------------
+#define CLKCTRL_OSCIN_CTRL ((0x0001 << 2) + 0xfe000000)
+#define CLKCTRL_RTC_BY_OSCIN_CTRL0 ((0x0002 << 2) + 0xfe000000)
+#define CLKCTRL_RTC_BY_OSCIN_CTRL1 ((0x0003 << 2) + 0xfe000000)
+#define CLKCTRL_RTC_CTRL ((0x0004 << 2) + 0xfe000000)
+#define CLKCTRL_CHECK_CLK_RESULT ((0x0005 << 2) + 0xfe000000)
+#define CLKCTRL_MBIST_ATSPEED_CTRL ((0x0006 << 2) + 0xfe000000)
+#define CLKCTRL_LOCK_BIT_REG0 ((0x0008 << 2) + 0xfe000000)
+#define CLKCTRL_LOCK_BIT_REG1 ((0x0009 << 2) + 0xfe000000)
+#define CLKCTRL_LOCK_BIT_REG2 ((0x000a << 2) + 0xfe000000)
+#define CLKCTRL_LOCK_BIT_REG3 ((0x000b << 2) + 0xfe000000)
+#define CLKCTRL_PROT_BIT_REG0 ((0x000c << 2) + 0xfe000000)
+#define CLKCTRL_PROT_BIT_REG1 ((0x000d << 2) + 0xfe000000)
+#define CLKCTRL_PROT_BIT_REG2 ((0x000e << 2) + 0xfe000000)
+#define CLKCTRL_PROT_BIT_REG3 ((0x000f << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_CTRL0 ((0x0010 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN0_REG0 ((0x0011 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN0_REG1 ((0x0012 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN0_REG2 ((0x0013 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN0_REG3 ((0x0014 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN1_REG0 ((0x0015 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN1_REG1 ((0x0016 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN1_REG2 ((0x0017 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN1_REG3 ((0x0018 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_VPU_EN0 ((0x0019 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_VPU_EN1 ((0x001a << 2) + 0xfe000000)
+#define CLKCTRL_AXI_CLK_CTRL0 ((0x001b << 2) + 0xfe000000)
+#define CLKCTRL_TST_CTRL0 ((0x0020 << 2) + 0xfe000000)
+#define CLKCTRL_TST_CTRL1 ((0x0021 << 2) + 0xfe000000)
+#define CLKCTRL_CECA_CTRL0 ((0x0022 << 2) + 0xfe000000)
+#define CLKCTRL_CECA_CTRL1 ((0x0023 << 2) + 0xfe000000)
+#define CLKCTRL_CECB_CTRL0 ((0x0024 << 2) + 0xfe000000)
+#define CLKCTRL_CECB_CTRL1 ((0x0025 << 2) + 0xfe000000)
+#define CLKCTRL_SC_CLK_CTRL ((0x0026 << 2) + 0xfe000000)
+#define CLKCTRL_DSPA_CLK_CTRL0 ((0x0027 << 2) + 0xfe000000)
+#define CLKCTRL_DSPB_CLK_CTRL0 ((0x0028 << 2) + 0xfe000000)
+#define CLKCTRL_RAMA_CLK_CTRL0 ((0x0029 << 2) + 0xfe000000)
+#define CLKCTRL_CLK12_24_CTRL ((0x002a << 2) + 0xfe000000)
+#define CLKCTRL_VID_CLK_CTRL ((0x0030 << 2) + 0xfe000000)
+#define CLKCTRL_VID_CLK_CTRL2 ((0x0031 << 2) + 0xfe000000)
+#define CLKCTRL_VID_CLK_DIV ((0x0032 << 2) + 0xfe000000)
+#define CLKCTRL_VIID_CLK_DIV ((0x0033 << 2) + 0xfe000000)
+#define CLKCTRL_VIID_CLK_CTRL ((0x0034 << 2) + 0xfe000000)
+#define CLKCTRL_HDMI_CLK_CTRL ((0x0038 << 2) + 0xfe000000)
+#define CLKCTRL_VID_PLL_CLK_DIV ((0x0039 << 2) + 0xfe000000)
+#define CLKCTRL_VPU_CLK_CTRL ((0x003a << 2) + 0xfe000000)
+#define CLKCTRL_VPU_CLKB_CTRL ((0x003b << 2) + 0xfe000000)
+#define CLKCTRL_VPU_CLKC_CTRL ((0x003c << 2) + 0xfe000000)
+#define CLKCTRL_VID_LOCK_CLK_CTRL ((0x003d << 2) + 0xfe000000)
+#define CLKCTRL_VDIN_MEAS_CLK_CTRL ((0x003e << 2) + 0xfe000000)
+#define CLKCTRL_VAPBCLK_CTRL ((0x003f << 2) + 0xfe000000)
+#define CLKCTRL_HDCP22_CLK_CTRL ((0x0040 << 2) + 0xfe000000)
+#define CLKCTRL_MIPIDSI_PHY_CLK_CTRL ((0x0041 << 2) + 0xfe000000)
+#define CLKCTRL_CDAC_CLK_CTRL ((0x0042 << 2) + 0xfe000000)
+#define CLKCTRL_MIPI_CSI_PHY_CLK_CTRL ((0x0043 << 2) + 0xfe000000)
+#define CLKCTRL_CSI2_ADAPT_CLK_CTRL ((0x0044 << 2) + 0xfe000000)
+#define CLKCTRL_VDEC_CLK_CTRL ((0x0050 << 2) + 0xfe000000)
+#define CLKCTRL_VDEC2_CLK_CTRL ((0x0051 << 2) + 0xfe000000)
+#define CLKCTRL_VDEC3_CLK_CTRL ((0x0052 << 2) + 0xfe000000)
+#define CLKCTRL_VDEC4_CLK_CTRL ((0x0053 << 2) + 0xfe000000)
+#define CLKCTRL_WAVE420L_CLK_CTRL ((0x0054 << 2) + 0xfe000000)
+#define CLKCTRL_WAVE420L_CLK_CTRL2 ((0x0055 << 2) + 0xfe000000)
+#define CLKCTRL_TS_CLK_CTRL ((0x0056 << 2) + 0xfe000000)
+#define CLKCTRL_MALI_CLK_CTRL ((0x0057 << 2) + 0xfe000000)
+#define CLKCTRL_VIPNANOQ_CLK_CTRL ((0x0058 << 2) + 0xfe000000)
+#define CLKCTRL_ETH_CLK_CTRL ((0x0059 << 2) + 0xfe000000)
+#define CLKCTRL_NAND_CLK_CTRL ((0x005a << 2) + 0xfe000000)
+#define CLKCTRL_SD_EMMC_CLK_CTRL ((0x005b << 2) + 0xfe000000)
+#define CLKCTRL_BT656_CLK_CTRL ((0x005c << 2) + 0xfe000000)
+#define CLKCTRL_SPICC_CLK_CTRL ((0x005d << 2) + 0xfe000000)
+#define CLKCTRL_GEN_CLK_CTRL ((0x005e << 2) + 0xfe000000)
+#define CLKCTRL_SAR_CLK_CTRL0 ((0x005f << 2) + 0xfe000000)
+#define CLKCTRL_PWM_CLK_AB_CTRL ((0x0060 << 2) + 0xfe000000)
+#define CLKCTRL_PWM_CLK_CD_CTRL ((0x0061 << 2) + 0xfe000000)
+#define CLKCTRL_PWM_CLK_EF_CTRL ((0x0062 << 2) + 0xfe000000)
+#define CLKCTRL_PWM_CLK_GH_CTRL ((0x0063 << 2) + 0xfe000000)
+#define CLKCTRL_PWM_CLK_IJ_CTRL ((0x0064 << 2) + 0xfe000000)
+#define CLKCTRL_DEMOD_CLK_CTRL ((0x0080 << 2) + 0xfe000000)
+#define CLKCTRL_TIMESTAMP_CTRL ((0x0100 << 2) + 0xfe000000)
+#define CLKCTRL_TIMESTAMP_CTRL1 ((0x0101 << 2) + 0xfe000000)
+#define CLKCTRL_TIMESTAMP_CTRL2 ((0x0103 << 2) + 0xfe000000)
+#define CLKCTRL_TIMESTAMP_RD0 ((0x0104 << 2) + 0xfe000000)
+#define CLKCTRL_TIMESTAMP_RD1 ((0x0105 << 2) + 0xfe000000)
+#define CLKCTRL_TIMEBASE_CTRL0 ((0x0106 << 2) + 0xfe000000)
+#define CLKCTRL_TIMEBASE_CTRL1 ((0x0107 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_CPU_CFG01 ((0x0120 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_CPU_CFG2 ((0x0121 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_ENCP_CFG0 ((0x0122 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_MALI_CFG01 ((0x0123 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_HEVCB_CFG01 ((0x0124 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_HEVCB_CFG2 ((0x0125 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_LOCK ((0x0126 << 2) + 0xfe000000)
+//========================================================================
+// PWR_CTRL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe00c000
+// -----------------------------------------------
+#define PWRCTRL_PWR_ACK0 ((0x0000 << 2) + 0xfe00c000)
+#define PWRCTRL_PWR_ACK1 ((0x0001 << 2) + 0xfe00c000)
+#define PWRCTRL_PWR_OFF0 ((0x0004 << 2) + 0xfe00c000)
+#define PWRCTRL_PWR_OFF1 ((0x0005 << 2) + 0xfe00c000)
+#define PWRCTRL_ISO_EN0 ((0x0008 << 2) + 0xfe00c000)
+#define PWRCTRL_ISO_EN1 ((0x0009 << 2) + 0xfe00c000)
+#define PWRCTRL_FOCRST0 ((0x000c << 2) + 0xfe00c000)
+#define PWRCTRL_FOCRST1 ((0x000d << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD0 ((0x0010 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD1 ((0x0011 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD2 ((0x0012 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD3 ((0x0013 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD4 ((0x0014 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD5 ((0x0015 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD6 ((0x0016 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD7 ((0x0017 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD8 ((0x0018 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD9 ((0x0019 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD10 ((0x001a << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD11 ((0x001b << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD12 ((0x001c << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD13 ((0x001d << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD14 ((0x001e << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD15 ((0x001f << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL0 ((0x0040 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL1 ((0x0041 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL2 ((0x0042 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL3 ((0x0043 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL4 ((0x0044 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_TIMER_TH_01 ((0x0048 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_TIMER_TH_23 ((0x0049 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_TIMER_TH_45 ((0x004a << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_TIMER_TH_67 ((0x004b << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_TIMER_TH_89 ((0x004c << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK0 ((0x0050 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK1 ((0x0051 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK2 ((0x0052 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK3 ((0x0053 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK4 ((0x0054 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK5 ((0x0055 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK6 ((0x0056 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK7 ((0x0057 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_INIT_SET ((0x0060 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_OFF_SET ((0x0061 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_ON_A_SET ((0x0062 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_ON_B_SET ((0x0063 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_ON_C_SET ((0x0064 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_ON_D_SET ((0x0065 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_STS ((0x0066 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_FSM_STS0 ((0x0067 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_FSM_STS1 ((0x0068 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_FSM_STS2 ((0x0069 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_FSM_START_OFF ((0x006d << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_FSM_START_ON ((0x006e << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_FSM_JUMP ((0x006f << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL0 ((0x0070 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL1 ((0x0071 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL2 ((0x0072 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL3 ((0x0073 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL4 ((0x0074 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_TIMER_TH_01 ((0x0078 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_TIMER_TH_23 ((0x0079 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_TIMER_TH_45 ((0x007a << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_TIMER_TH_67 ((0x007b << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_TIMER_TH_89 ((0x007c << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK0 ((0x0080 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK1 ((0x0081 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK2 ((0x0082 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK3 ((0x0083 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK4 ((0x0084 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK5 ((0x0085 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK6 ((0x0086 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK7 ((0x0087 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_INIT_SET ((0x0090 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_OFF_SET ((0x0091 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_ON_A_SET ((0x0092 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_ON_B_SET ((0x0093 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_ON_C_SET ((0x0094 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_ON_D_SET ((0x0095 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_STS ((0x0096 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_FSM_STS0 ((0x0097 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_FSM_STS1 ((0x0098 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_FSM_STS2 ((0x0099 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_FSM_START_OFF ((0x009d << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_FSM_START_ON ((0x009e << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_FSM_JUMP ((0x009f << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL0 ((0x00a0 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL1 ((0x00a1 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL2 ((0x00a2 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL3 ((0x00a3 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL4 ((0x00a4 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_TIMER_TH_01 ((0x00a8 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_TIMER_TH_23 ((0x00a9 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_TIMER_TH_45 ((0x00aa << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_TIMER_TH_67 ((0x00ab << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_TIMER_TH_89 ((0x00ac << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK0 ((0x00b0 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK1 ((0x00b1 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK2 ((0x00b2 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK3 ((0x00b3 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK4 ((0x00b4 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK5 ((0x00b5 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK6 ((0x00b6 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK7 ((0x00b7 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_INIT_SET ((0x00c0 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_OFF_SET ((0x00c1 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_ON_A_SET ((0x00c2 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_ON_B_SET ((0x00c3 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_ON_C_SET ((0x00c4 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_ON_D_SET ((0x00c5 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_STS ((0x00c6 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_FSM_STS0 ((0x00c7 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_FSM_STS1 ((0x00c8 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_FSM_STS2 ((0x00c9 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_FSM_START_OFF ((0x00cd << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_FSM_START_ON ((0x00ce << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_FSM_JUMP ((0x00cf << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL0 ((0x00d0 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL1 ((0x00d1 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL2 ((0x00d2 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL3 ((0x00d3 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL4 ((0x00d4 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_TIMER_TH_01 ((0x00d8 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_TIMER_TH_23 ((0x00d9 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_TIMER_TH_45 ((0x00da << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_TIMER_TH_67 ((0x00db << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_TIMER_TH_89 ((0x00dc << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK0 ((0x00e0 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK1 ((0x00e1 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK2 ((0x00e2 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK3 ((0x00e3 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK4 ((0x00e4 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK5 ((0x00e5 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK6 ((0x00e6 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK7 ((0x00e7 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_INIT_SET ((0x00f0 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_OFF_SET ((0x00f1 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_ON_A_SET ((0x00f2 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_ON_B_SET ((0x00f3 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_ON_C_SET ((0x00f4 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_ON_D_SET ((0x00f5 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_STS ((0x00f6 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_FSM_STS0 ((0x00f7 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_FSM_STS1 ((0x00f8 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_FSM_STS2 ((0x00f9 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_FSM_START_OFF ((0x00fd << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_FSM_START_ON ((0x00fe << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_FSM_JUMP ((0x00ff << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL0 ((0x0100 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL1 ((0x0101 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL2 ((0x0102 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL3 ((0x0103 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL4 ((0x0104 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_TIMER_TH_01 ((0x0108 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_TIMER_TH_23 ((0x0109 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_TIMER_TH_45 ((0x010a << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_TIMER_TH_67 ((0x010b << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_TIMER_TH_89 ((0x010c << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK0 ((0x0110 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK1 ((0x0111 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK2 ((0x0112 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK3 ((0x0113 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK4 ((0x0114 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK5 ((0x0115 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK6 ((0x0116 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK7 ((0x0117 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_INIT_SET ((0x0120 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_OFF_SET ((0x0121 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_ON_A_SET ((0x0122 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_ON_B_SET ((0x0123 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_ON_C_SET ((0x0124 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_ON_D_SET ((0x0125 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_STS ((0x0126 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_FSM_STS0 ((0x0127 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_FSM_STS1 ((0x0128 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_FSM_STS2 ((0x0129 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_FSM_START_OFF ((0x012d << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_FSM_START_ON ((0x012e << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_FSM_JUMP ((0x012f << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL0 ((0x0130 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL1 ((0x0131 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL2 ((0x0132 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL3 ((0x0133 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL4 ((0x0134 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_TIMER_TH_01 ((0x0138 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_TIMER_TH_23 ((0x0139 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_TIMER_TH_45 ((0x013a << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_TIMER_TH_67 ((0x013b << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_TIMER_TH_89 ((0x013c << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK0 ((0x0140 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK1 ((0x0141 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK2 ((0x0142 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK3 ((0x0143 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK4 ((0x0144 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK5 ((0x0145 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK6 ((0x0146 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK7 ((0x0147 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_INIT_SET ((0x0150 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_OFF_SET ((0x0151 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_ON_A_SET ((0x0152 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_ON_B_SET ((0x0153 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_ON_C_SET ((0x0154 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_ON_D_SET ((0x0155 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_STS ((0x0156 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_FSM_STS0 ((0x0157 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_FSM_STS1 ((0x0158 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_FSM_STS2 ((0x0159 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_FSM_START_OFF ((0x015d << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_FSM_START_ON ((0x015e << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_FSM_JUMP ((0x015f << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL0 ((0x0160 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL1 ((0x0161 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL2 ((0x0162 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL3 ((0x0163 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL4 ((0x0164 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_TIMER_TH_01 ((0x0168 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_TIMER_TH_23 ((0x0169 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_TIMER_TH_45 ((0x016a << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_TIMER_TH_67 ((0x016b << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_TIMER_TH_89 ((0x016c << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK0 ((0x0170 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK1 ((0x0171 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK2 ((0x0172 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK3 ((0x0173 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK4 ((0x0174 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK5 ((0x0175 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK6 ((0x0176 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK7 ((0x0177 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_INIT_SET ((0x0180 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_OFF_SET ((0x0181 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_ON_A_SET ((0x0182 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_ON_B_SET ((0x0183 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_ON_C_SET ((0x0184 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_ON_D_SET ((0x0185 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_STS ((0x0186 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_FSM_STS0 ((0x0187 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_FSM_STS1 ((0x0188 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_FSM_STS2 ((0x0189 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_FSM_START_OFF ((0x018d << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_FSM_START_ON ((0x018e << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_FSM_JUMP ((0x018f << 2) + 0xfe00c000)
+//========================================================================
+// RSA
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe042000
+// -----------------------------------------------
+#define RSA_BASE ((0x0000 << 2) + 0xfe042000)
+//========================================================================
+// AOCPU
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe09c000
+// -----------------------------------------------
+#define AOCPU_CPU_CTRL0 ((0x0000 << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_CPU_CTRL1 ((0x0001 << 2) + 0xfe09c000)
+//Bit 31:11- 0 - n205 address shift, 1: 0x8000_0000~0x4000_0000
+//Bit 30:11- 0 - reserved
+//Bit 10 - 0 - gate by sleep, 1: gate, 0: free run
+//Bit 9 - 0 - RXEV for riscv input refer riscv doc
+//Bit 8 - 0 - reserved
+//Bit 7:6- 0 - n205_debug_sel,aocpu_core_status0 info select
+//Bit 5:2- 0 - reserved
+//Bit 1 - 0 - n205_i_dbg_stop
+//Bit 0 - 0 - n205_pc_enable
+#define AOCPU_CPU_CTRL2 ((0x0002 << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_CPU_CTRL3 ((0x0003 << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_CPU_CTRL4 ((0x0004 << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_CPU_CTRL5 ((0x0005 << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_CPU_STS0 ((0x000a << 2) + 0xfe09c000)
+//Bit 31:0 - 0 - n205_debug_sel==0 : n205_trace_casuse, 1:n205_trace_tval, 2:n205_trace_iaddr, 3:n205_trace_instr
+#define AOCPU_CPU_STS1 ((0x000b << 2) + 0xfe09c000)
+//Bit 31 - 0 - n205_core_sleep_value
+//Bit 30:29- 0 - n205_trace_priv
+//Bit 28:20- 0 - reserved
+//Bit 19 - 0 - n205_core_wfi_mode
+//Bit 18 - 0 - n205_trace_ivalid
+//Bit 17 - 0 - n205_trace_iexception
+//Bit 16 - 0 - n205_trace_interrupt
+//Bit 15:0 - 0 - reserved
+#define AOCPU_CPU_STS2 ((0x000c << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_CPU_STS3 ((0x000d << 2) + 0xfe09c000)
+//Bit 31 - 0 - n205_hart_halted
+//Bit 30 - 0 - n205_ndmreset
+//Bit 29 - 0 - n205_dmactive
+//Bit 28:0 - 0 - reserved
+#define AOCPU_CPU_VECTOR ((0x000f << 2) + 0xfe09c000)
+//Bit 31:0- 0x1000_0000 - reserved
+#define AOCPU_IRQ_SEL0 ((0x0010 << 2) + 0xfe09c000)
+//Bit 31:24- 0 - INTISR03 interrupt source select in int_map
+//Bit 23:16- 0 - INTISR02 interrupt source select in int_map
+//Bit 15:8 - 0 - INTISR01 interrupt source select in int_map
+//Bit 7:0 - 0 - INTISR00 interrupt source select in int_map
+#define AOCPU_IRQ_SEL1 ((0x0011 << 2) + 0xfe09c000)
+//Bit 31:24- 0 - INTISR07 interrupt source select in int_map
+//Bit 23:16- 0 - INTISR06 interrupt source select in int_map
+//Bit 15:8 - 0 - INTISR05 interrupt source select in int_map
+//Bit 7:0 - 0 - INTISR04 interrupt source select in int_map
+#define AOCPU_IRQ_SEL2 ((0x0012 << 2) + 0xfe09c000)
+//Bit 31:24- 0 - INTISR11 interrupt source select in int_map
+//Bit 23:16- 0 - INTISR10 interrupt source select in int_map
+//Bit 15:8 - 0 - INTISR09 interrupt source select in int_map
+//Bit 7:0 - 0 - INTISR08 interrupt source select in int_map
+#define AOCPU_IRQ_SEL3 ((0x0013 << 2) + 0xfe09c000)
+//Bit 31:24- 0 - INTISR15 interrupt source select in int_map
+//Bit 23:16- 0 - INTISR14 interrupt source select in int_map
+//Bit 15:8 - 0 - INTISR13 interrupt source select in int_map
+//Bit 7:0 - 0 - INTISR12 interrupt source select in int_map
+#define AOCPU_IRQ_SEL4 ((0x0014 << 2) + 0xfe09c000)
+//Bit 31:24- 0 - INTISR19 interrupt source select in int_map
+//Bit 23:16- 0 - INTISR18 interrupt source select in int_map
+//Bit 15:8 - 0 - INTISR17 interrupt source select in int_map
+//Bit 7:0 - 0 - INTISR16 interrupt source select in int_map
+#define AOCPU_IRQ_SEL5 ((0x0015 << 2) + 0xfe09c000)
+//Bit 31:24- 0 - INTISR23 interrupt source select in int_map
+//Bit 23:16- 0 - INTISR22 interrupt source select in int_map
+//Bit 15:8 - 0 - INTISR21 interrupt source select in int_map
+//Bit 7:0 - 0 - INTISR20 interrupt source select in int_map
+#define AOCPU_IRQ_SEL6 ((0x0016 << 2) + 0xfe09c000)
+//Bit 31:24- 0 - INTISR27 interrupt source select in int_map
+//Bit 23:16- 0 - INTISR26 interrupt source select in int_map
+//Bit 15:8 - 0 - INTISR25 interrupt source select in int_map
+//Bit 7:0 - 0 - INTISR24 interrupt source select in int_map
+#define AOCPU_IRQ_SEL7 ((0x0017 << 2) + 0xfe09c000)
+//Bit 31:24- 0 - INTISR31 interrupt source select in int_map
+//Bit 23:16- 0 - INTISR30 interrupt source select in int_map
+//Bit 15:8 - 0 - INTISR29 interrupt source select in int_map
+//Bit 7:0 - 0 - INTISR28 interrupt source select in int_map
+#define AOCPU_STS00_BYCPU ((0x0018 << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_STS01_BYCPU ((0x0019 << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_STS02_BYCPU ((0x001a << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_STS03_BYCPU ((0x001b << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_STS04_BYCPU ((0x001c << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_STS05_BYCPU ((0x001d << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_STS06_BYCPU ((0x001e << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_STS07_BYCPU ((0x001f << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+//========================================================================
+// AUCPU
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe09e000
+// -----------------------------------------------
+#define AUCPU_CPU_CTRL0 ((0x0000 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_CPU_CTRL1 ((0x0001 << 2) + 0xfe09e000)
+//Bit 31:11- 0 - reserved
+//Bit 10 - 0 - gate by sleep
+//Bit 9 - 0 - RXEV
+//Bit 8 - 0 - reserved
+//Bit 7:6 - 0 - n205_debug_sel,aucpu_core_status0 info select
+//Bit 5:2 - 0 - reserved
+//Bit 1 - 0 - n205_i_dbg_stop
+//Bit 0 - 0 - n205_pc_enable
+#define AUCPU_CPU_CTRL2 ((0x0002 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_CPU_CTRL3 ((0x0003 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_CPU_CTRL4 ((0x0004 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_CPU_CTRL5 ((0x0005 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_CPU_STS0 ((0x000a << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - n205_debug_sel==0 : n205_trace_casuse, 1:n205_trace_tval, 2:n205_trace_iaddr, 3:n205_trace_instr
+#define AUCPU_CPU_STS1 ((0x000b << 2) + 0xfe09e000)
+//Bit 31 - 0 - n205_core_sleep_value
+//Bit 30:29- 0 - n205_trace_priv
+//Bit 28:20- 0 - reserved
+//Bit 19 - 0 - n205_core_wfi_mode
+//Bit 18 - 0 - n205_trace_ivalid
+//Bit 17 - 0 - n205_trace_iexception
+//Bit 16 - 0 - n205_trace_interrupt
+//Bit 15:0 - 0 - reserved
+#define AUCPU_CPU_STS2 ((0x000c << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_CPU_STS3 ((0x000d << 2) + 0xfe09e000)
+//Bit 31 - 0 - n205_hart_halted
+//Bit 30 - 0 - n205_ndmreset
+//Bit 29 - 0 - n205_dmactive
+//Bit 28:0 - 0 - reserved
+#define AUCPU_DMA_APB_SEL ((0x0010 << 2) + 0xfe09e000)
+//Bit 31:30- 0 - reserved
+//Bit 0 - 0 - 1: riscv control dma, 0: ap control dma
+#define AUCPU_IRQ_AP2RISCV ((0x0011 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - AP cpu send irq to riscv
+#define AUCPU_IRQ_RISCV2AP ((0x0012 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - riscv send irq to AP
+#define AUCPU_STS00_BY_AP ((0x0020 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS01_BY_AP ((0x0021 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS02_BY_AP ((0x0022 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS03_BY_AP ((0x0023 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS04_BY_AP ((0x0024 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS05_BY_AP ((0x0025 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS06_BY_AP ((0x0026 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS07_BY_AP ((0x0027 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS08_BY_AP ((0x0028 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS09_BY_AP ((0x0029 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS10_BY_AP ((0x002a << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS11_BY_AP ((0x002b << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS12_BY_AP ((0x002c << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS13_BY_AP ((0x002d << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS14_BY_AP ((0x002e << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS15_BY_AP ((0x002f << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS16_BY_AP ((0x0030 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS17_BY_AP ((0x0031 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS18_BY_AP ((0x0032 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS19_BY_AP ((0x0033 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS20_BY_AP ((0x0034 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS21_BY_AP ((0x0035 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS22_BY_AP ((0x0036 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS23_BY_AP ((0x0037 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS24_BY_AP ((0x0038 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS25_BY_AP ((0x0039 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS26_BY_AP ((0x003a << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS27_BY_AP ((0x003b << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS28_BY_AP ((0x003c << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS29_BY_AP ((0x003d << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS30_BY_AP ((0x003e << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS31_BY_AP ((0x003f << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS00_BY_RISCV ((0x0040 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS01_BY_RISCV ((0x0041 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS02_BY_RISCV ((0x0042 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS03_BY_RISCV ((0x0043 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS04_BY_RISCV ((0x0044 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS05_BY_RISCV ((0x0045 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS06_BY_RISCV ((0x0046 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS07_BY_RISCV ((0x0047 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS08_BY_RISCV ((0x0048 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS09_BY_RISCV ((0x0049 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS10_BY_RISCV ((0x004a << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS11_BY_RISCV ((0x004b << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS12_BY_RISCV ((0x004c << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS13_BY_RISCV ((0x004d << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS14_BY_RISCV ((0x004e << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS15_BY_RISCV ((0x004f << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS16_BY_RISCV ((0x0050 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS17_BY_RISCV ((0x0051 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS18_BY_RISCV ((0x0052 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS19_BY_RISCV ((0x0053 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS20_BY_RISCV ((0x0054 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS21_BY_RISCV ((0x0055 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS22_BY_RISCV ((0x0056 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS23_BY_RISCV ((0x0057 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS24_BY_RISCV ((0x0058 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS25_BY_RISCV ((0x0059 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS26_BY_RISCV ((0x005a << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS27_BY_RISCV ((0x005b << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS28_BY_RISCV ((0x005c << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS29_BY_RISCV ((0x005d << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS30_BY_RISCV ((0x005e << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS31_BY_RISCV ((0x005f << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_DEMUX_STS_BY_RISCV ((0x0060 << 2) + 0xfe09e000)
+//Bit 31 - 0 - read only, demux status updated
+//Bit 31:8 - 0 - reserved
+//Bit 7:0 - 0 - read demux chn select
+#define AUCPU_DEMUX_STS0 ((0x0061 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - demux status 0
+#define AUCPU_DEMUX_STS1 ((0x0062 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - demux status 1
+//========================================================================
+// AXI_SRAM
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe090000
+// -----------------------------------------------
+#define SRAM_RANGE0_STA ((0x0000 << 2) + 0xfe090000)
+#define SRAM_RANGE1_STA ((0x0001 << 2) + 0xfe090000)
+#define SRAM_RANGE2_STA ((0x0002 << 2) + 0xfe090000)
+#define SRAM_RANGE3_STA ((0x0003 << 2) + 0xfe090000)
+#define SRAM_RANGE4_STA ((0x0004 << 2) + 0xfe090000)
+#define SRAM_RANGE5_STA ((0x0005 << 2) + 0xfe090000)
+#define SRAM_RANGE6_STA ((0x0006 << 2) + 0xfe090000)
+#define SRAM_RANGE7_STA ((0x0007 << 2) + 0xfe090000)
+#define SRAM_RANGE8_STA ((0x0008 << 2) + 0xfe090000)
+#define SRAM_RANGE9_STA ((0x0009 << 2) + 0xfe090000)
+#define SRAM_RANGE10_STA ((0x000a << 2) + 0xfe090000)
+#define SRAM_RANGE11_STA ((0x000b << 2) + 0xfe090000)
+#define SRAM_RANGE12_STA ((0x000c << 2) + 0xfe090000)
+#define SRAM_RANGE13_STA ((0x000d << 2) + 0xfe090000)
+#define SRAM_RANGE14_STA ((0x000e << 2) + 0xfe090000)
+#define SRAM_RANGE0_EDA ((0x000f << 2) + 0xfe090000)
+#define SRAM_RANGE1_EDA ((0x0010 << 2) + 0xfe090000)
+#define SRAM_RANGE2_EDA ((0x0011 << 2) + 0xfe090000)
+#define SRAM_RANGE3_EDA ((0x0012 << 2) + 0xfe090000)
+#define SRAM_RANGE4_EDA ((0x0013 << 2) + 0xfe090000)
+#define SRAM_RANGE5_EDA ((0x0014 << 2) + 0xfe090000)
+#define SRAM_RANGE6_EDA ((0x0015 << 2) + 0xfe090000)
+#define SRAM_RANGE7_EDA ((0x0016 << 2) + 0xfe090000)
+#define SRAM_RANGE8_EDA ((0x0017 << 2) + 0xfe090000)
+#define SRAM_RANGE9_EDA ((0x0018 << 2) + 0xfe090000)
+#define SRAM_RANGE10_EDA ((0x0019 << 2) + 0xfe090000)
+#define SRAM_RANGE11_EDA ((0x001a << 2) + 0xfe090000)
+#define SRAM_RANGE12_EDA ((0x001b << 2) + 0xfe090000)
+#define SRAM_RANGE13_EDA ((0x001c << 2) + 0xfe090000)
+#define SRAM_RANGE14_EDA ((0x001d << 2) + 0xfe090000)
+#define SRAM_RANGE0_READ_CTRL0 ((0x001e << 2) + 0xfe090000)
+#define SRAM_RANGE1_READ_CTRL0 ((0x001f << 2) + 0xfe090000)
+#define SRAM_RANGE2_READ_CTRL0 ((0x0020 << 2) + 0xfe090000)
+#define SRAM_RANGE3_READ_CTRL0 ((0x0021 << 2) + 0xfe090000)
+#define SRAM_RANGE4_READ_CTRL0 ((0x0022 << 2) + 0xfe090000)
+#define SRAM_RANGE5_READ_CTRL0 ((0x0023 << 2) + 0xfe090000)
+#define SRAM_RANGE6_READ_CTRL0 ((0x0024 << 2) + 0xfe090000)
+#define SRAM_RANGE7_READ_CTRL0 ((0x0025 << 2) + 0xfe090000)
+#define SRAM_RANGE8_READ_CTRL0 ((0x0026 << 2) + 0xfe090000)
+#define SRAM_RANGE9_READ_CTRL0 ((0x0027 << 2) + 0xfe090000)
+#define SRAM_RANGE10_READ_CTRL0 ((0x0028 << 2) + 0xfe090000)
+#define SRAM_RANGE11_READ_CTRL0 ((0x0029 << 2) + 0xfe090000)
+#define SRAM_RANGE12_READ_CTRL0 ((0x002a << 2) + 0xfe090000)
+#define SRAM_RANGE13_READ_CTRL0 ((0x002b << 2) + 0xfe090000)
+#define SRAM_RANGE14_READ_CTRL0 ((0x002c << 2) + 0xfe090000)
+#define SRAM_RANGE15_READ_CTRL0 ((0x002d << 2) + 0xfe090000)
+#define SRAM_RANGE0_WRITE_CTRL0 ((0x002e << 2) + 0xfe090000)
+#define SRAM_RANGE1_WRITE_CTRL0 ((0x002f << 2) + 0xfe090000)
+#define SRAM_RANGE2_WRITE_CTRL0 ((0x0030 << 2) + 0xfe090000)
+#define SRAM_RANGE3_WRITE_CTRL0 ((0x0031 << 2) + 0xfe090000)
+#define SRAM_RANGE4_WRITE_CTRL0 ((0x0032 << 2) + 0xfe090000)
+#define SRAM_RANGE5_WRITE_CTRL0 ((0x0033 << 2) + 0xfe090000)
+#define SRAM_RANGE6_WRITE_CTRL0 ((0x0034 << 2) + 0xfe090000)
+#define SRAM_RANGE7_WRITE_CTRL0 ((0x0035 << 2) + 0xfe090000)
+#define SRAM_RANGE8_WRITE_CTRL0 ((0x0036 << 2) + 0xfe090000)
+#define SRAM_RANGE9_WRITE_CTRL0 ((0x0037 << 2) + 0xfe090000)
+#define SRAM_RANGE10_WRITE_CTRL0 ((0x0038 << 2) + 0xfe090000)
+#define SRAM_RANGE11_WRITE_CTRL0 ((0x0039 << 2) + 0xfe090000)
+#define SRAM_RANGE12_WRITE_CTRL0 ((0x003a << 2) + 0xfe090000)
+#define SRAM_RANGE13_WRITE_CTRL0 ((0x003b << 2) + 0xfe090000)
+#define SRAM_RANGE14_WRITE_CTRL0 ((0x003c << 2) + 0xfe090000)
+#define SRAM_RANGE15_WRITE_CTRL0 ((0x003d << 2) + 0xfe090000)
+#define SRAM_RANGE0_READ_CTRL1 ((0x003e << 2) + 0xfe090000)
+#define SRAM_RANGE1_READ_CTRL1 ((0x003f << 2) + 0xfe090000)
+#define SRAM_RANGE2_READ_CTRL1 ((0x0040 << 2) + 0xfe090000)
+#define SRAM_RANGE3_READ_CTRL1 ((0x0041 << 2) + 0xfe090000)
+#define SRAM_RANGE4_READ_CTRL1 ((0x0042 << 2) + 0xfe090000)
+#define SRAM_RANGE5_READ_CTRL1 ((0x0043 << 2) + 0xfe090000)
+#define SRAM_RANGE6_READ_CTRL1 ((0x0044 << 2) + 0xfe090000)
+#define SRAM_RANGE7_READ_CTRL1 ((0x0045 << 2) + 0xfe090000)
+#define SRAM_RANGE8_READ_CTRL1 ((0x0046 << 2) + 0xfe090000)
+#define SRAM_RANGE9_READ_CTRL1 ((0x0047 << 2) + 0xfe090000)
+#define SRAM_RANGE10_READ_CTRL1 ((0x0048 << 2) + 0xfe090000)
+#define SRAM_RANGE11_READ_CTRL1 ((0x0049 << 2) + 0xfe090000)
+#define SRAM_RANGE12_READ_CTRL1 ((0x004a << 2) + 0xfe090000)
+#define SRAM_RANGE13_READ_CTRL1 ((0x004b << 2) + 0xfe090000)
+#define SRAM_RANGE14_READ_CTRL1 ((0x004c << 2) + 0xfe090000)
+#define SRAM_RANGE15_READ_CTRL1 ((0x004d << 2) + 0xfe090000)
+#define SRAM_RANGE0_WRITE_CTRL1 ((0x004e << 2) + 0xfe090000)
+#define SRAM_RANGE1_WRITE_CTRL1 ((0x004f << 2) + 0xfe090000)
+#define SRAM_RANGE2_WRITE_CTRL1 ((0x0050 << 2) + 0xfe090000)
+#define SRAM_RANGE3_WRITE_CTRL1 ((0x0051 << 2) + 0xfe090000)
+#define SRAM_RANGE4_WRITE_CTRL1 ((0x0052 << 2) + 0xfe090000)
+#define SRAM_RANGE5_WRITE_CTRL1 ((0x0053 << 2) + 0xfe090000)
+#define SRAM_RANGE6_WRITE_CTRL1 ((0x0054 << 2) + 0xfe090000)
+#define SRAM_RANGE7_WRITE_CTRL1 ((0x0055 << 2) + 0xfe090000)
+#define SRAM_RANGE8_WRITE_CTRL1 ((0x0056 << 2) + 0xfe090000)
+#define SRAM_RANGE9_WRITE_CTRL1 ((0x0057 << 2) + 0xfe090000)
+#define SRAM_RANGE10_WRITE_CTRL1 ((0x0058 << 2) + 0xfe090000)
+#define SRAM_RANGE11_WRITE_CTRL1 ((0x0059 << 2) + 0xfe090000)
+#define SRAM_RANGE12_WRITE_CTRL1 ((0x005a << 2) + 0xfe090000)
+#define SRAM_RANGE13_WRITE_CTRL1 ((0x005b << 2) + 0xfe090000)
+#define SRAM_RANGE14_WRITE_CTRL1 ((0x005c << 2) + 0xfe090000)
+#define SRAM_RANGE15_WRITE_CTRL1 ((0x005d << 2) + 0xfe090000)
+#define SRAM_GLOBAL_READ_CTRL0 ((0x005e << 2) + 0xfe090000)
+#define SRAM_GLOBAL_READ_CTRL1 ((0x005f << 2) + 0xfe090000)
+#define SRAM_GLOBAL_WRITE_CTRL0 ((0x0060 << 2) + 0xfe090000)
+#define SRAM_GLOBAL_WRITE_CTRL1 ((0x0061 << 2) + 0xfe090000)
+#define SRAM_SEC_CTRL0 ((0x0062 << 2) + 0xfe090000)
+#define SRAM_REG_LOCK0 ((0x0063 << 2) + 0xfe090000)
+#define SRAM_REG_LOCK1 ((0x0064 << 2) + 0xfe090000)
+#define SRAM_REG_LOCK2 ((0x0065 << 2) + 0xfe090000)
+#define SRAM_GLOBAL_READ_CTRL0_LOCK ((0x0066 << 2) + 0xfe090000)
+#define SRAM_GLOBAL_READ_CTRL1_LOCK ((0x0067 << 2) + 0xfe090000)
+#define SRAM_GLOBAL_WRITE_CTRL0_LOCK ((0x0068 << 2) + 0xfe090000)
+#define SRAM_GLOBAL_WRITE_CTRL1_LOCK ((0x0069 << 2) + 0xfe090000)
+#define SRAM_SEC_CTRL0_LOCK ((0x006a << 2) + 0xfe090000)
+#define SRAM_STATUS_REG ((0x006b << 2) + 0xfe090000)
+//========================================================================
+// MAILBOX
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe006000
+// -----------------------------------------------
+#define MAILBOX_WR_MBOX00 ((0x0000 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX01 ((0x0020 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX02 ((0x0040 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX03 ((0x0060 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX04 ((0x0080 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX05 ((0x00a0 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX06 ((0x00c0 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX07 ((0x00e0 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX08 ((0x0100 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX09 ((0x0120 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX10 ((0x0140 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX11 ((0x0160 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX12 ((0x0180 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX13 ((0x01a0 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX14 ((0x01c0 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX15 ((0x01e0 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX00 ((0x0200 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX01 ((0x0220 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX02 ((0x0240 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX03 ((0x0260 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX04 ((0x0280 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX05 ((0x02a0 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX06 ((0x02c0 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX07 ((0x02e0 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX08 ((0x0300 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX09 ((0x0320 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX10 ((0x0340 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX11 ((0x0360 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX12 ((0x0380 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX13 ((0x03a0 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX14 ((0x03c0 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX15 ((0x03e0 << 2) + 0xfe006000)
+#define MAILBOX_LOCK_BIT0 ((0x0400 << 2) + 0xfe006000)
+#define MAILBOX_LOCK_BIT1 ((0x0401 << 2) + 0xfe006000)
+#define MAILBOX_PROT_BIT0 ((0x0402 << 2) + 0xfe006000)
+#define MAILBOX_PROT_BIT1 ((0x0403 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_IRQA_CLR ((0x0404 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_IRQB_CLR ((0x0405 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_IRQC_CLR ((0x0406 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_IRQD_CLR ((0x0407 << 2) + 0xfe006000)
+#define MAILBOX_IRQA_MASK ((0x0408 << 2) + 0xfe006000)
+#define MAILBOX_IRQB_MASK ((0x0409 << 2) + 0xfe006000)
+#define MAILBOX_IRQC_MASK ((0x040a << 2) + 0xfe006000)
+#define MAILBOX_IRQD_MASK ((0x040b << 2) + 0xfe006000)
+#define MAILBOX_IRQ_TYPE ((0x040c << 2) + 0xfe006000)
+#define MAILBOX_IRQA_CLR ((0x0410 << 2) + 0xfe006000)
+#define MAILBOX_IRQB_CLR ((0x0411 << 2) + 0xfe006000)
+#define MAILBOX_IRQC_CLR ((0x0412 << 2) + 0xfe006000)
+#define MAILBOX_IRQD_CLR ((0x0413 << 2) + 0xfe006000)
+#define MAILBOX_IRQA_STS ((0x0414 << 2) + 0xfe006000)
+#define MAILBOX_IRQB_STS ((0x0415 << 2) + 0xfe006000)
+#define MAILBOX_IRQC_STS ((0x0416 << 2) + 0xfe006000)
+#define MAILBOX_IRQD_STS ((0x0417 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX00 ((0x0420 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX01 ((0x0421 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX02 ((0x0422 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX03 ((0x0423 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX04 ((0x0424 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX05 ((0x0425 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX06 ((0x0426 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX07 ((0x0427 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX08 ((0x0428 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX09 ((0x0429 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX10 ((0x042a << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX11 ((0x042b << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX12 ((0x042c << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX13 ((0x042d << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX14 ((0x042e << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX15 ((0x042f << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX00 ((0x0430 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX01 ((0x0431 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX02 ((0x0432 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX03 ((0x0433 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX04 ((0x0434 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX05 ((0x0435 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX06 ((0x0436 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX07 ((0x0437 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX08 ((0x0438 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX09 ((0x0439 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX10 ((0x043a << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX11 ((0x043b << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX12 ((0x043c << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX13 ((0x043d << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX14 ((0x043e << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX15 ((0x043f << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX00 ((0x0440 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX01 ((0x0441 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX02 ((0x0442 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX03 ((0x0443 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX04 ((0x0444 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX05 ((0x0445 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX06 ((0x0446 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX07 ((0x0447 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX08 ((0x0448 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX09 ((0x0449 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX10 ((0x044a << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX11 ((0x044b << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX12 ((0x044c << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX13 ((0x044d << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX14 ((0x044e << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX15 ((0x044f << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX00 ((0x0450 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX01 ((0x0451 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX02 ((0x0452 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX03 ((0x0453 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX04 ((0x0454 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX05 ((0x0455 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX06 ((0x0456 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX07 ((0x0457 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX08 ((0x0458 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX09 ((0x0459 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX10 ((0x045a << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX11 ((0x045b << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX12 ((0x045c << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX13 ((0x045d << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX14 ((0x045e << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX15 ((0x045f << 2) + 0xfe006000)
+//========================================================================
+// IRQ_CTRL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe00a000
+// -----------------------------------------------
+#define IRQCTRL_IRQ_INV0 ((0x0000 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV1 ((0x0001 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV2 ((0x0002 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV3 ((0x0003 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV4 ((0x0004 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV5 ((0x0005 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV6 ((0x0006 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV7 ((0x0007 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK0_GIC ((0x0010 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK1_GIC ((0x0011 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK2_GIC ((0x0012 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK3_GIC ((0x0013 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK4_GIC ((0x0014 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK5_GIC ((0x0015 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK6_GIC ((0x0016 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK7_GIC ((0x0017 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK0_DSP ((0x0020 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK1_DSP ((0x0021 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK2_DSP ((0x0022 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK3_DSP ((0x0023 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK4_DSP ((0x0024 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK5_DSP ((0x0025 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK6_DSP ((0x0026 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK7_DSP ((0x0027 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK0_PWRCTRL ((0x0030 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK1_PWRCTRL ((0x0031 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK2_PWRCTRL ((0x0032 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK3_PWRCTRL ((0x0033 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK4_PWRCTRL ((0x0034 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK5_PWRCTRL ((0x0035 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK6_PWRCTRL ((0x0036 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK7_PWRCTRL ((0x0037 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK0_AOCPU ((0x0040 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK1_AOCPU ((0x0041 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK2_AOCPU ((0x0042 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK3_AOCPU ((0x0043 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK4_AOCPU ((0x0044 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK5_AOCPU ((0x0045 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK6_AOCPU ((0x0046 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK7_AOCPU ((0x0047 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE0 ((0x0050 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE1 ((0x0051 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE2 ((0x0052 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE3 ((0x0053 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE4 ((0x0054 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE5 ((0x0055 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE6 ((0x0056 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE7 ((0x0057 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH0 ((0x0060 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH1 ((0x0061 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH2 ((0x0062 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH3 ((0x0063 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH4 ((0x0064 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH5 ((0x0065 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH6 ((0x0066 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH7 ((0x0067 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR0 ((0x0070 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR1 ((0x0071 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR2 ((0x0072 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR3 ((0x0073 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR4 ((0x0074 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR5 ((0x0075 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR6 ((0x0076 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR7 ((0x0077 << 2) + 0xfe00a000)
+#define IRQCTRL_LOCK_BIT ((0x0080 << 2) + 0xfe00a000)
+#define IRQCTRL_PROT_BIT ((0x0081 << 2) + 0xfe00a000)
+//========================================================================
+// RESET_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe002000
+// -----------------------------------------------
+#define RESETCTRL_RESET0 ((0x0000 << 2) + 0xfe002000)
+#define RESETCTRL_RESET1 ((0x0001 << 2) + 0xfe002000)
+#define RESETCTRL_RESET2 ((0x0002 << 2) + 0xfe002000)
+#define RESETCTRL_RESET3 ((0x0003 << 2) + 0xfe002000)
+#define RESETCTRL_RESET4 ((0x0004 << 2) + 0xfe002000)
+#define RESETCTRL_RESET5 ((0x0005 << 2) + 0xfe002000)
+#define RESETCTRL_RESET0_LEVEL ((0x0010 << 2) + 0xfe002000)
+#define RESETCTRL_RESET1_LEVEL ((0x0011 << 2) + 0xfe002000)
+#define RESETCTRL_RESET2_LEVEL ((0x0012 << 2) + 0xfe002000)
+#define RESETCTRL_RESET3_LEVEL ((0x0013 << 2) + 0xfe002000)
+#define RESETCTRL_RESET4_LEVEL ((0x0014 << 2) + 0xfe002000)
+#define RESETCTRL_RESET5_LEVEL ((0x0015 << 2) + 0xfe002000)
+#define RESETCTRL_RESET0_MASK ((0x0020 << 2) + 0xfe002000)
+#define RESETCTRL_RESET1_MASK ((0x0021 << 2) + 0xfe002000)
+#define RESETCTRL_RESET2_MASK ((0x0022 << 2) + 0xfe002000)
+#define RESETCTRL_RESET3_MASK ((0x0023 << 2) + 0xfe002000)
+#define RESETCTRL_RESET4_MASK ((0x0024 << 2) + 0xfe002000)
+#define RESETCTRL_RESET5_MASK ((0x0025 << 2) + 0xfe002000)
+#define RESETCTRL_RESET_HOLD_CYC ((0x0030 << 2) + 0xfe002000)
+#define RESETCTRL_WATCHDOG_CTRL0 ((0x0040 << 2) + 0xfe002000)
+#define RESETCTRL_WATCHDOG_CTRL1 ((0x0041 << 2) + 0xfe002000)
+#define RESETCTRL_WATCHDOG_CNT ((0x0042 << 2) + 0xfe002000)
+#define RESETCTRL_WATCHDOG_CLR ((0x0043 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_WATCHDOG_CTRL0 ((0x0044 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_WATCHDOG_CTRL1 ((0x0045 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_WATCHDOG_CNT ((0x0046 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_WATCHDOG_CLR ((0x0047 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET0 ((0x0050 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET1 ((0x0051 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET0_LEVEL ((0x0060 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET1_LEVEL ((0x0061 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET0_MASK ((0x0070 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET1_MASK ((0x0071 << 2) + 0xfe002000)
+#define RESETCTRL_RESET0_LOCK ((0x0080 << 2) + 0xfe002000)
+#define RESETCTRL_RESET1_LOCK ((0x0081 << 2) + 0xfe002000)
+#define RESETCTRL_RESET2_LOCK ((0x0082 << 2) + 0xfe002000)
+#define RESETCTRL_RESET3_LOCK ((0x0083 << 2) + 0xfe002000)
+#define RESETCTRL_RESET4_LOCK ((0x0084 << 2) + 0xfe002000)
+#define RESETCTRL_RESET5_LOCK ((0x0085 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET0_LOCK ((0x0088 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET1_LOCK ((0x0089 << 2) + 0xfe002000)
+#define RESETCTRL_RESET0_PROT ((0x0090 << 2) + 0xfe002000)
+#define RESETCTRL_RESET1_PROT ((0x0091 << 2) + 0xfe002000)
+#define RESETCTRL_RESET2_PROT ((0x0092 << 2) + 0xfe002000)
+#define RESETCTRL_RESET3_PROT ((0x0093 << 2) + 0xfe002000)
+#define RESETCTRL_RESET4_PROT ((0x0094 << 2) + 0xfe002000)
+#define RESETCTRL_RESET5_PROT ((0x0095 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET0_PROT ((0x0098 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET1_PROT ((0x0099 << 2) + 0xfe002000)
+//========================================================================
+// CPU_CTRL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe00e000
+// -----------------------------------------------
+#define CPUCTRL_SYS_CPU_RESET_CNTL ((0x0050 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CLK_CTRL ((0x0051 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CLK_CTRL1 ((0x0052 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CLK_CTRL2 ((0x0053 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CLK_CTRL3 ((0x0054 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CLK_CTRL4 ((0x0055 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CLK_CTRL5 ((0x0056 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CLK_CTRL6 ((0x0057 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CLK_RESULT ((0x0058 << 2) + 0xfe00e000)
+#define CPUCTRL_ROM_DISABLE ((0x0060 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_POR_CFG0 ((0x0090 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_POR_CFG1 ((0x0091 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG0 ((0x0092 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG1 ((0x0093 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG2 ((0x0094 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG3 ((0x0095 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG4 ((0x0096 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG5 ((0x0097 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG6 ((0x0098 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG7 ((0x0099 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG8 ((0x009a << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG9 ((0x009b << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG10 ((0x009c << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG11 ((0x009d << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG12 ((0x009e << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG13 ((0x009f << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS0 ((0x00a0 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS1 ((0x00a1 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS2 ((0x00a2 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS3 ((0x00a3 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS4 ((0x00a4 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS5 ((0x00a5 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS6 ((0x00a6 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS7 ((0x00a7 << 2) + 0xfe00e000)
+#define SYS_CPU_MISC ((0x00a8 << 2) + 0xfe00e000)
+//========================================================================
+// SAR_ADC
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe026000
+// -----------------------------------------------
+#define SAR_ADC_REG0 ((0x0000 << 2) + 0xfe026000)
+#define SAR_ADC_CHAN_LIST ((0x0001 << 2) + 0xfe026000)
+#define SAR_ADC_AVG_CNTL ((0x0002 << 2) + 0xfe026000)
+#define SAR_ADC_REG3 ((0x0003 << 2) + 0xfe026000)
+#define SAR_ADC_DELAY ((0x0004 << 2) + 0xfe026000)
+#define SAR_ADC_LAST_RD ((0x0005 << 2) + 0xfe026000)
+#define SAR_ADC_FIFO_RD ((0x0006 << 2) + 0xfe026000)
+#define SAR_ADC_AUX_SW ((0x0007 << 2) + 0xfe026000)
+#define SAR_ADC_CHAN_10_SW ((0x0008 << 2) + 0xfe026000)
+#define SAR_ADC_DETECT_IDLE_SW ((0x0009 << 2) + 0xfe026000)
+#define SAR_ADC_DELTA_10 ((0x000a << 2) + 0xfe026000)
+#define SAR_ADC_REG11 ((0x000b << 2) + 0xfe026000)
+#define SAR_ADC_REG12 ((0x000c << 2) + 0xfe026000)
+#define SAR_ADC_REG13 ((0x000d << 2) + 0xfe026000)
+#define SAR_ADC_CHNL01 ((0x000e << 2) + 0xfe026000)
+#define SAR_ADC_CHNL23 ((0x000f << 2) + 0xfe026000)
+#define SAR_ADC_CHNL45 ((0x0010 << 2) + 0xfe026000)
+#define SAR_ADC_CHNL67 ((0x0011 << 2) + 0xfe026000)
+//========================================================================
+// ANA_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe008000
+// -----------------------------------------------
+#define ANACTRL_SYSPLL_CTRL0 ((0x0000 << 2) + 0xfe008000)
+#define ANACTRL_SYSPLL_CTRL1 ((0x0001 << 2) + 0xfe008000)
+#define ANACTRL_SYSPLL_CTRL2 ((0x0002 << 2) + 0xfe008000)
+#define ANACTRL_SYSPLL_CTRL3 ((0x0003 << 2) + 0xfe008000)
+#define ANACTRL_SYSPLL_CTRL4 ((0x0004 << 2) + 0xfe008000)
+#define ANACTRL_SYSPLL_CTRL5 ((0x0005 << 2) + 0xfe008000)
+#define ANACTRL_SYSPLL_CTRL6 ((0x0006 << 2) + 0xfe008000)
+#define ANACTRL_SYSPLL_STS ((0x0007 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL0 ((0x0010 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL1 ((0x0011 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL2 ((0x0012 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL3 ((0x0013 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL4 ((0x0014 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL5 ((0x0015 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL6 ((0x0016 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_STS ((0x0017 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL0 ((0x0020 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL1 ((0x0021 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL2 ((0x0022 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL3 ((0x0023 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL4 ((0x0024 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL5 ((0x0025 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL6 ((0x0026 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_STS ((0x0027 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_CTRL0 ((0x0030 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_CTRL1 ((0x0031 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_CTRL2 ((0x0032 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_CTRL3 ((0x0033 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_CTRL4 ((0x0034 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_CTRL5 ((0x0035 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_CTRL6 ((0x0036 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_STS ((0x0037 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL0 ((0x0040 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL1 ((0x0041 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL2 ((0x0042 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL3 ((0x0043 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL4 ((0x0044 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL5 ((0x0045 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL6 ((0x0046 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_STS ((0x0047 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_CTRL0 ((0x0050 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_CTRL1 ((0x0051 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_CTRL2 ((0x0052 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_CTRL3 ((0x0053 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_CTRL4 ((0x0054 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_CTRL5 ((0x0055 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_STS ((0x0056 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL0 ((0x0060 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL1 ((0x0061 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL2 ((0x0062 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL3 ((0x0063 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL4 ((0x0064 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL5 ((0x0065 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL6 ((0x0066 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL7 ((0x0067 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL8 ((0x0068 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_STS ((0x0069 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL0 ((0x0070 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL1 ((0x0071 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL2 ((0x0072 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL3 ((0x0073 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL4 ((0x0074 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL5 ((0x0075 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL6 ((0x0076 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_STS ((0x0077 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_VLOCK ((0x0079 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_CTRL0 ((0x0080 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_CTRL1 ((0x0081 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_CTRL2 ((0x0082 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_CTRL3 ((0x0083 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_CTRL4 ((0x0084 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_CTRL5 ((0x0085 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_STS ((0x0086 << 2) + 0xfe008000)
+#define ANACTRL_MIPICSI_CTRL0 ((0x0090 << 2) + 0xfe008000)
+#define ANACTRL_MIPICSI_CTRL1 ((0x0091 << 2) + 0xfe008000)
+#define ANACTRL_MIPICSI_CTRL2 ((0x0092 << 2) + 0xfe008000)
+#define ANACTRL_MIPICSI_CTRL3 ((0x0093 << 2) + 0xfe008000)
+#define ANACTRL_MIPICSI_CTRL4 ((0x0094 << 2) + 0xfe008000)
+#define ANACTRL_MIPICSI_CTRL5 ((0x0095 << 2) + 0xfe008000)
+#define ANACTRL_MIPIDSI_CTRL0 ((0x00a0 << 2) + 0xfe008000)
+#define ANACTRL_MIPIDSI_CTRL1 ((0x00a1 << 2) + 0xfe008000)
+#define ANACTRL_MIPIDSI_CTRL2 ((0x00a2 << 2) + 0xfe008000)
+#define ANACTRL_MIPIDSI_STS ((0x00a3 << 2) + 0xfe008000)
+#define ANACTRL_VDAC_CTRL0 ((0x00b0 << 2) + 0xfe008000)
+#define ANACTRL_VDAC_CTRL1 ((0x00b1 << 2) + 0xfe008000)
+#define ANACTRL_POR_CTRL ((0x00b6 << 2) + 0xfe008000)
+#define ANACTRL_LOCK_BIT ((0x00b8 << 2) + 0xfe008000)
+#define ANACTRL_PROT_BIT ((0x00b9 << 2) + 0xfe008000)
+#define ANACTRL_ADC_PLL_CTRL ((0x00c0 << 2) + 0xfe008000)
+#define ANACTRL_ADC_PLL_CTRL1 ((0x00c1 << 2) + 0xfe008000)
+#define ANACTRL_ADC_PLL_CTRL2 ((0x00c2 << 2) + 0xfe008000)
+#define ANACTRL_ADC_PLL_CTRL3 ((0x00c3 << 2) + 0xfe008000)
+#define ANACTRL_ADC_PLL_CTRL4 ((0x00c4 << 2) + 0xfe008000)
+#define ANACTRL_ADC_PLL_CTRL5 ((0x00c5 << 2) + 0xfe008000)
+#define ANACTRL_ADC_PLL_CTRL6 ((0x00c6 << 2) + 0xfe008000)
+#define ANACTRL_ADC_PLL_STS ((0x00c7 << 2) + 0xfe008000)
+#define ANACTRL_S2_DADC_CTRL ((0x00d0 << 2) + 0xfe008000)
+#define ANACTRL_S2_DADC_CTRL2 ((0x00d1 << 2) + 0xfe008000)
+//========================================================================
+// Ethernet Phy
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe028000
+// -----------------------------------------------
+#define ETH_PHY_DBG_CTL0 ((0x0000 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_CTL1 ((0x0001 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_CFG0 ((0x0002 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_CFG1 ((0x0003 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_CFG2 ((0x0004 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_CFG3 ((0x0005 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_CFG4 ((0x0006 << 2) + 0xfe028000)
+#define ETH_PLL_STS ((0x0010 << 2) + 0xfe028000)
+#define ETH_PLL_CTL0 ((0x0011 << 2) + 0xfe028000)
+#define ETH_PLL_CTL1 ((0x0012 << 2) + 0xfe028000)
+#define ETH_PLL_CTL2 ((0x0013 << 2) + 0xfe028000)
+#define ETH_PLL_CTL3 ((0x0014 << 2) + 0xfe028000)
+#define ETH_PLL_CTL4 ((0x0015 << 2) + 0xfe028000)
+#define ETH_PLL_CTL5 ((0x0016 << 2) + 0xfe028000)
+#define ETH_PLL_CTL6 ((0x0017 << 2) + 0xfe028000)
+#define ETH_PLL_CTL7 ((0x0018 << 2) + 0xfe028000)
+#define ETH_PHY_CNTL0 ((0x0020 << 2) + 0xfe028000)
+#define ETH_PHY_CNTL1 ((0x0021 << 2) + 0xfe028000)
+#define ETH_PHY_CNTL2 ((0x0022 << 2) + 0xfe028000)
+#define ETH_PHY_CNTL3 ((0x0023 << 2) + 0xfe028000)
+#define ETH_PHY_STS0 ((0x0025 << 2) + 0xfe028000)
+#define ETH_PHY_STS1 ((0x0026 << 2) + 0xfe028000)
+#define ETH_PHY_STS2 ((0x0027 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_REG ((0x0028 << 2) + 0xfe028000)
+//========================================================================
+// Ethernet TOP
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe024000
+// -----------------------------------------------
+#define ETHTOP_CNTL0 ((0x0000 << 2) + 0xfe024000)
+#define ETHTOP_CNTL1 ((0x0001 << 2) + 0xfe024000)
+//========================================================================
+// I2C Slave A
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe064000
+// -----------------------------------------------
+#define I2C_S_A_CONTROL_REG ((0x0000 << 2) + 0xfe064000)
+#define I2C_S_A_SEND_REG ((0x0001 << 2) + 0xfe064000)
+#define I2C_S_A_RECV_REG ((0x0002 << 2) + 0xfe064000)
+#define I2C_S_A_CNTL1_REG ((0x0003 << 2) + 0xfe064000)
+//========================================================================
+// IR RX/TX
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe084000
+// -----------------------------------------------
+#define IRCTRL_IR_DEC_LDR_ACTIVE ((0x0000 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_LDR_IDLE ((0x0001 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_LDR_REPEAT ((0x0002 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_BIT_0 ((0x0003 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_REG0 ((0x0004 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_FRAME ((0x0005 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_STATUS ((0x0006 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_REG1 ((0x0007 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_LDR_ACTIVE ((0x0010 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_LDR_IDLE ((0x0011 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_LDR_REPEAT ((0x0012 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_BIT_0 ((0x0013 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_REG0 ((0x0014 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_FRAME ((0x0015 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_STATUS ((0x0016 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_REG1 ((0x0017 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_REG2 ((0x0018 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_DURATN2 ((0x0019 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_DURATN3 ((0x001a << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_FRAME1 ((0x001b << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_STATUS1 ((0x001c << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_STATUS2 ((0x001d << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_REG3 ((0x001e << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_FRAME_RSV0 ((0x001f << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_FRAME_RSV1 ((0x0020 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_FILTE ((0x0021 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_IRQ_CTL ((0x0022 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_FIFO_CTL ((0x0023 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_WIDTH_NEW ((0x0024 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_REPEAT_DET ((0x0025 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_CNTL0 ((0x0030 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_CNTL1 ((0x0031 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_IIR_THD ((0x0032 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_THD0 ((0x0033 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_THD1 ((0x0034 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_SUM_CNT0 ((0x0035 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_SUM_CNT1 ((0x0036 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_CNT0 ((0x0037 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_CNT1 ((0x0038 << 2) + 0xfe084000)
+#define IRCTRL_IR_BLASTER_ADDR0 ((0x0043 << 2) + 0xfe084000)
+#define IRCTRL_IR_BLASTER_ADDR1 ((0x0044 << 2) + 0xfe084000)
+#define IRCTRL_IR_BLASTER_ADDR2 ((0x0045 << 2) + 0xfe084000)
+#define IRCTRL_IR_BLASTER_ADDR3 ((0x0046 << 2) + 0xfe084000)
+//========================================================================
+// I2C Master A
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe066000
+// -----------------------------------------------
+#define I2C_M_A_CONTROL_REG ((0x0000 << 2) + 0xfe066000)
+#define I2C_M_A_SLAVE_ADDR ((0x0001 << 2) + 0xfe066000)
+#define I2C_M_A_TOKEN_LIST0 ((0x0002 << 2) + 0xfe066000)
+#define I2C_M_A_TOKEN_LIST1 ((0x0003 << 2) + 0xfe066000)
+#define I2C_M_A_WDATA_REG0 ((0x0004 << 2) + 0xfe066000)
+#define I2C_M_A_WDATA_REG1 ((0x0005 << 2) + 0xfe066000)
+#define I2C_M_A_RDATA_REG0 ((0x0006 << 2) + 0xfe066000)
+#define I2C_M_A_RDATA_REG1 ((0x0007 << 2) + 0xfe066000)
+#define I2C_M_A_TIMEOUT_TH ((0x0008 << 2) + 0xfe066000)
+#define I2C_M_A_CNTL_DELY1 ((0x0009 << 2) + 0xfe066000)
+#define I2C_M_A_CNTL_DELY2 ((0x000a << 2) + 0xfe066000)
+#define I2C_M_A_LOW_DELY ((0x000b << 2) + 0xfe066000)
+#define I2C_M_A_HIGH_DELY ((0x000c << 2) + 0xfe066000)
+#define I2C_M_A_FIFO_CTRL0 ((0x000d << 2) + 0xfe066000)
+#define I2C_M_A_FIFO_CTRL1 ((0x000e << 2) + 0xfe066000)
+#define I2C_M_A_FIFO_PENDING ((0x000f << 2) + 0xfe066000)
+#define I2C_M_A_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe066000)
+#define I2C_M_A_FIFO_ST0 ((0x0011 << 2) + 0xfe066000)
+//========================================================================
+// I2C Master B
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe068000
+// -----------------------------------------------
+#define I2C_M_B_CONTROL_REG ((0x0000 << 2) + 0xfe068000)
+#define I2C_M_B_SLAVE_ADDR ((0x0001 << 2) + 0xfe068000)
+#define I2C_M_B_TOKEN_LIST0 ((0x0002 << 2) + 0xfe068000)
+#define I2C_M_B_TOKEN_LIST1 ((0x0003 << 2) + 0xfe068000)
+#define I2C_M_B_WDATA_REG0 ((0x0004 << 2) + 0xfe068000)
+#define I2C_M_B_WDATA_REG1 ((0x0005 << 2) + 0xfe068000)
+#define I2C_M_B_RDATA_REG0 ((0x0006 << 2) + 0xfe068000)
+#define I2C_M_B_RDATA_REG1 ((0x0007 << 2) + 0xfe068000)
+#define I2C_M_B_TIMEOUT_TH ((0x0008 << 2) + 0xfe068000)
+#define I2C_M_B_CNTL_DELY1 ((0x0009 << 2) + 0xfe068000)
+#define I2C_M_B_CNTL_DELY2 ((0x000a << 2) + 0xfe068000)
+#define I2C_M_B_LOW_DELY ((0x000b << 2) + 0xfe068000)
+#define I2C_M_B_HIGH_DELY ((0x000c << 2) + 0xfe068000)
+#define I2C_M_B_FIFO_CTRL0 ((0x000d << 2) + 0xfe068000)
+#define I2C_M_B_FIFO_CTRL1 ((0x000e << 2) + 0xfe068000)
+#define I2C_M_B_FIFO_PENDING ((0x000f << 2) + 0xfe068000)
+#define I2C_M_B_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe068000)
+#define I2C_M_B_FIFO_ST0 ((0x0011 << 2) + 0xfe068000)
+//========================================================================
+// I2C Master C
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe06a000
+// -----------------------------------------------
+#define I2C_M_C_CONTROL_REG ((0x0000 << 2) + 0xfe06a000)
+#define I2C_M_C_SLAVE_ADDR ((0x0001 << 2) + 0xfe06a000)
+#define I2C_M_C_TOKEN_LIST0 ((0x0002 << 2) + 0xfe06a000)
+#define I2C_M_C_TOKEN_LIST1 ((0x0003 << 2) + 0xfe06a000)
+#define I2C_M_C_WDATA_REG0 ((0x0004 << 2) + 0xfe06a000)
+#define I2C_M_C_WDATA_REG1 ((0x0005 << 2) + 0xfe06a000)
+#define I2C_M_C_RDATA_REG0 ((0x0006 << 2) + 0xfe06a000)
+#define I2C_M_C_RDATA_REG1 ((0x0007 << 2) + 0xfe06a000)
+#define I2C_M_C_TIMEOUT_TH ((0x0008 << 2) + 0xfe06a000)
+#define I2C_M_C_CNTL_DELY1 ((0x0009 << 2) + 0xfe06a000)
+#define I2C_M_C_CNTL_DELY2 ((0x000a << 2) + 0xfe06a000)
+#define I2C_M_C_LOW_DELY ((0x000b << 2) + 0xfe06a000)
+#define I2C_M_C_HIGH_DELY ((0x000c << 2) + 0xfe06a000)
+#define I2C_M_C_FIFO_CTRL0 ((0x000d << 2) + 0xfe06a000)
+#define I2C_M_C_FIFO_CTRL1 ((0x000e << 2) + 0xfe06a000)
+#define I2C_M_C_FIFO_PENDING ((0x000f << 2) + 0xfe06a000)
+#define I2C_M_C_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe06a000)
+#define I2C_M_C_FIFO_ST0 ((0x0011 << 2) + 0xfe06a000)
+//========================================================================
+// I2C Master D
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe06c000
+// -----------------------------------------------
+#define I2C_M_D_CONTROL_REG ((0x0000 << 2) + 0xfe06c000)
+#define I2C_M_D_SLAVE_ADDR ((0x0001 << 2) + 0xfe06c000)
+#define I2C_M_D_TOKEN_LIST0 ((0x0002 << 2) + 0xfe06c000)
+#define I2C_M_D_TOKEN_LIST1 ((0x0003 << 2) + 0xfe06c000)
+#define I2C_M_D_WDATA_REG0 ((0x0004 << 2) + 0xfe06c000)
+#define I2C_M_D_WDATA_REG1 ((0x0005 << 2) + 0xfe06c000)
+#define I2C_M_D_RDATA_REG0 ((0x0006 << 2) + 0xfe06c000)
+#define I2C_M_D_RDATA_REG1 ((0x0007 << 2) + 0xfe06c000)
+#define I2C_M_D_TIMEOUT_TH ((0x0008 << 2) + 0xfe06c000)
+#define I2C_M_D_CNTL_DELY1 ((0x0009 << 2) + 0xfe06c000)
+#define I2C_M_D_CNTL_DELY2 ((0x000a << 2) + 0xfe06c000)
+#define I2C_M_D_LOW_DELY ((0x000b << 2) + 0xfe06c000)
+#define I2C_M_D_HIGH_DELY ((0x000c << 2) + 0xfe06c000)
+#define I2C_M_D_FIFO_CTRL0 ((0x000d << 2) + 0xfe06c000)
+#define I2C_M_D_FIFO_CTRL1 ((0x000e << 2) + 0xfe06c000)
+#define I2C_M_D_FIFO_PENDING ((0x000f << 2) + 0xfe06c000)
+#define I2C_M_D_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe06c000)
+#define I2C_M_D_FIFO_ST0 ((0x0011 << 2) + 0xfe06c000)
+//========================================================================
+// I2C Master E
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe06e000
+// -----------------------------------------------
+#define I2C_M_E_CONTROL_REG ((0x0000 << 2) + 0xfe06e000)
+#define I2C_M_E_SLAVE_ADDR ((0x0001 << 2) + 0xfe06e000)
+#define I2C_M_E_TOKEN_LIST0 ((0x0002 << 2) + 0xfe06e000)
+#define I2C_M_E_TOKEN_LIST1 ((0x0003 << 2) + 0xfe06e000)
+#define I2C_M_E_WDATA_REG0 ((0x0004 << 2) + 0xfe06e000)
+#define I2C_M_E_WDATA_REG1 ((0x0005 << 2) + 0xfe06e000)
+#define I2C_M_E_RDATA_REG0 ((0x0006 << 2) + 0xfe06e000)
+#define I2C_M_E_RDATA_REG1 ((0x0007 << 2) + 0xfe06e000)
+#define I2C_M_E_TIMEOUT_TH ((0x0008 << 2) + 0xfe06e000)
+#define I2C_M_E_CNTL_DELY1 ((0x0009 << 2) + 0xfe06e000)
+#define I2C_M_E_CNTL_DELY2 ((0x000a << 2) + 0xfe06e000)
+#define I2C_M_E_LOW_DELY ((0x000b << 2) + 0xfe06e000)
+#define I2C_M_E_HIGH_DELY ((0x000c << 2) + 0xfe06e000)
+#define I2C_M_E_FIFO_CTRL0 ((0x000d << 2) + 0xfe06e000)
+#define I2C_M_E_FIFO_CTRL1 ((0x000e << 2) + 0xfe06e000)
+#define I2C_M_E_FIFO_PENDING ((0x000f << 2) + 0xfe06e000)
+#define I2C_M_E_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe06e000)
+#define I2C_M_E_FIFO_ST0 ((0x0011 << 2) + 0xfe06e000)
+//========================================================================
+// I2C Master F
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe070000
+// -----------------------------------------------
+#define I2C_M_F_CONTROL_REG ((0x0000 << 2) + 0xfe070000)
+#define I2C_M_F_SLAVE_ADDR ((0x0001 << 2) + 0xfe070000)
+#define I2C_M_F_TOKEN_LIST0 ((0x0002 << 2) + 0xfe070000)
+#define I2C_M_F_TOKEN_LIST1 ((0x0003 << 2) + 0xfe070000)
+#define I2C_M_F_WDATA_REG0 ((0x0004 << 2) + 0xfe070000)
+#define I2C_M_F_WDATA_REG1 ((0x0005 << 2) + 0xfe070000)
+#define I2C_M_F_RDATA_REG0 ((0x0006 << 2) + 0xfe070000)
+#define I2C_M_F_RDATA_REG1 ((0x0007 << 2) + 0xfe070000)
+#define I2C_M_F_TIMEOUT_TH ((0x0008 << 2) + 0xfe070000)
+#define I2C_M_F_CNTL_DELY1 ((0x0009 << 2) + 0xfe070000)
+#define I2C_M_F_CNTL_DELY2 ((0x000a << 2) + 0xfe070000)
+#define I2C_M_F_LOW_DELY ((0x000b << 2) + 0xfe070000)
+#define I2C_M_F_HIGH_DELY ((0x000c << 2) + 0xfe070000)
+#define I2C_M_F_FIFO_CTRL_REG ((0x000d << 2) + 0xfe070000)
+#define I2C_M_F_STATE_REG ((0x000e << 2) + 0xfe070000)
+//========================================================================
+// APB0_UART_A - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe078000
+// -----------------------------------------------
+#define UART_A_WFIFO ((0x0000 << 2) + 0xfe078000)
+#define UART_A_RFIFO ((0x0001 << 2) + 0xfe078000)
+#define UART_A_CONTROL ((0x0002 << 2) + 0xfe078000)
+#define UART_A_STATUS ((0x0003 << 2) + 0xfe078000)
+#define UART_A_MISC ((0x0004 << 2) + 0xfe078000)
+#define UART_A_REG5 ((0x0005 << 2) + 0xfe078000)
+//========================================================================
+// APB0_UART_B - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe07a000
+// -----------------------------------------------
+#define UART_B_WFIFO ((0x0000 << 2) + 0xfe07a000)
+#define UART_B_RFIFO ((0x0001 << 2) + 0xfe07a000)
+#define UART_B_CONTROL ((0x0002 << 2) + 0xfe07a000)
+#define UART_B_STATUS ((0x0003 << 2) + 0xfe07a000)
+#define UART_B_MISC ((0x0004 << 2) + 0xfe07a000)
+#define UART_B_REG5 ((0x0005 << 2) + 0xfe07a000)
+//========================================================================
+// APB0_UART_C - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe07c000
+// -----------------------------------------------
+#define UART_C_WFIFO ((0x0000 << 2) + 0xfe07c000)
+#define UART_C_RFIFO ((0x0001 << 2) + 0xfe07c000)
+#define UART_C_CONTROL ((0x0002 << 2) + 0xfe07c000)
+#define UART_C_STATUS ((0x0003 << 2) + 0xfe07c000)
+#define UART_C_MISC ((0x0004 << 2) + 0xfe07c000)
+#define UART_C_REG5 ((0x0005 << 2) + 0xfe07c000)
+//========================================================================
+// APB0_UART_D - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe07e000
+// -----------------------------------------------
+#define UART_D_WFIFO ((0x0000 << 2) + 0xfe07e000)
+#define UART_D_RFIFO ((0x0001 << 2) + 0xfe07e000)
+#define UART_D_CONTROL ((0x0002 << 2) + 0xfe07e000)
+#define UART_D_STATUS ((0x0003 << 2) + 0xfe07e000)
+#define UART_D_MISC ((0x0004 << 2) + 0xfe07e000)
+#define UART_D_REG5 ((0x0005 << 2) + 0xfe07e000)
+//========================================================================
+// APB0_UART_E - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe080000
+// -----------------------------------------------
+#define UART_E_WFIFO ((0x0000 << 2) + 0xfe080000)
+#define UART_E_RFIFO ((0x0001 << 2) + 0xfe080000)
+#define UART_E_CONTROL ((0x0002 << 2) + 0xfe080000)
+#define UART_E_STATUS ((0x0003 << 2) + 0xfe080000)
+#define UART_E_MISC ((0x0004 << 2) + 0xfe080000)
+#define UART_E_REG5 ((0x0005 << 2) + 0xfe080000)
+//========================================================================
+// PWM_AB - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe058000
+// -----------------------------------------------
+#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe058000)
+#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe058000)
+#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe058000)
+#define PWMAB_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe058000)
+#define PWMAB_TIME_AB ((0x0004 << 2) + 0xfe058000)
+#define PWMAB_A2 ((0x0005 << 2) + 0xfe058000)
+#define PWMAB_B2 ((0x0006 << 2) + 0xfe058000)
+#define PWMAB_BLINK_AB ((0x0007 << 2) + 0xfe058000)
+#define PWMAB_LOCK_AB ((0x0008 << 2) + 0xfe058000)
+//========================================================================
+// PWM_CD - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe05a000
+// -----------------------------------------------
+#define PWMCD_PWM_A ((0x0000 << 2) + 0xfe05a000)
+#define PWMCD_PWM_B ((0x0001 << 2) + 0xfe05a000)
+#define PWMCD_MISC_REG_AB ((0x0002 << 2) + 0xfe05a000)
+#define PWMCD_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe05a000)
+#define PWMCD_TIME_AB ((0x0004 << 2) + 0xfe05a000)
+#define PWMCD_A2 ((0x0005 << 2) + 0xfe05a000)
+#define PWMCD_B2 ((0x0006 << 2) + 0xfe05a000)
+#define PWMCD_BLINK_AB ((0x0007 << 2) + 0xfe05a000)
+#define PWMCD_LOCK_AB ((0x0008 << 2) + 0xfe05a000)
+//========================================================================
+// PWM_EF - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe05c000
+// -----------------------------------------------
+#define PWMEF_PWM_A ((0x0000 << 2) + 0xfe05c000)
+#define PWMEF_PWM_B ((0x0001 << 2) + 0xfe05c000)
+#define PWMEF_MISC_REG_AB ((0x0002 << 2) + 0xfe05c000)
+#define PWMEF_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe05c000)
+#define PWMEF_TIME_AB ((0x0004 << 2) + 0xfe05c000)
+#define PWMEF_A2 ((0x0005 << 2) + 0xfe05c000)
+#define PWMEF_B2 ((0x0006 << 2) + 0xfe05c000)
+#define PWMEF_BLINK_AB ((0x0007 << 2) + 0xfe05c000)
+#define PWMEF_LOCK_AB ((0x0008 << 2) + 0xfe05c000)
+//========================================================================
+// PWM_GH - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe05e000
+// -----------------------------------------------
+#define PWMGH_PWM_A ((0x0000 << 2) + 0xfe05e000)
+#define PWMGH_PWM_B ((0x0001 << 2) + 0xfe05e000)
+#define PWMGH_MISC_REG_AB ((0x0002 << 2) + 0xfe05e000)
+#define PWMGH_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe05e000)
+#define PWMGH_TIME_AB ((0x0004 << 2) + 0xfe05e000)
+#define PWMGH_A2 ((0x0005 << 2) + 0xfe05e000)
+#define PWMGH_B2 ((0x0006 << 2) + 0xfe05e000)
+#define PWMGH_BLINK_AB ((0x0007 << 2) + 0xfe05e000)
+#define PWMGH_LOCK_AB ((0x0008 << 2) + 0xfe05e000)
+//========================================================================
+// PWM_IJ - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe060000
+// -----------------------------------------------
+#define PWMIJ_PWM_A ((0x0000 << 2) + 0xfe060000)
+#define PWMIJ_PWM_B ((0x0001 << 2) + 0xfe060000)
+#define PWMIJ_MISC_REG_AB ((0x0002 << 2) + 0xfe060000)
+#define PWMIJ_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe060000)
+#define PWMIJ_TIME_AB ((0x0004 << 2) + 0xfe060000)
+#define PWMIJ_A2 ((0x0005 << 2) + 0xfe060000)
+#define PWMIJ_B2 ((0x0006 << 2) + 0xfe060000)
+#define PWMIJ_BLINK_AB ((0x0007 << 2) + 0xfe060000)
+#define PWMIJ_LOCK_AB ((0x0008 << 2) + 0xfe060000)
+//========================================================================
+// SPICC_0
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe050000
+// -----------------------------------------------
+#define SPICC0_RXDATA ((0x0000 << 2) + 0xfe050000)
+#define SPICC0_TXDATA ((0x0001 << 2) + 0xfe050000)
+#define SPICC0_CONREG ((0x0002 << 2) + 0xfe050000)
+#define SPICC0_INTREG ((0x0003 << 2) + 0xfe050000)
+#define SPICC0_DMAREG ((0x0004 << 2) + 0xfe050000)
+#define SPICC0_STATREG ((0x0005 << 2) + 0xfe050000)
+#define SPICC0_PERIODREG ((0x0006 << 2) + 0xfe050000)
+#define SPICC0_TESTREG ((0x0007 << 2) + 0xfe050000)
+#define SPICC0_DRADDR ((0x0008 << 2) + 0xfe050000)
+#define SPICC0_DWADDR ((0x0009 << 2) + 0xfe050000)
+#define SPICC0_LD_CNTL0 ((0x000a << 2) + 0xfe050000)
+#define SPICC0_LD_CNTL1 ((0x000b << 2) + 0xfe050000)
+#define SPICC0_LD_RADDR ((0x000c << 2) + 0xfe050000)
+#define SPICC0_LD_WADDR ((0x000d << 2) + 0xfe050000)
+#define SPICC0_ENHANCE_CNTL ((0x000e << 2) + 0xfe050000)
+#define SPICC0_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe050000)
+#define SPICC0_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe050000)
+//========================================================================
+// SPICC_1
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe052000
+// -----------------------------------------------
+#define SPICC1_RXDATA ((0x0000 << 2) + 0xfe052000)
+#define SPICC1_TXDATA ((0x0001 << 2) + 0xfe052000)
+#define SPICC1_CONREG ((0x0002 << 2) + 0xfe052000)
+#define SPICC1_INTREG ((0x0003 << 2) + 0xfe052000)
+#define SPICC1_DMAREG ((0x0004 << 2) + 0xfe052000)
+#define SPICC1_STATREG ((0x0005 << 2) + 0xfe052000)
+#define SPICC1_PERIODREG ((0x0006 << 2) + 0xfe052000)
+#define SPICC1_TESTREG ((0x0007 << 2) + 0xfe052000)
+#define SPICC1_DRADDR ((0x0008 << 2) + 0xfe052000)
+#define SPICC1_DWADDR ((0x0009 << 2) + 0xfe052000)
+#define SPICC1_LD_CNTL0 ((0x000a << 2) + 0xfe052000)
+#define SPICC1_LD_CNTL1 ((0x000b << 2) + 0xfe052000)
+#define SPICC1_LD_RADDR ((0x000c << 2) + 0xfe052000)
+#define SPICC1_LD_WADDR ((0x000d << 2) + 0xfe052000)
+#define SPICC1_ENHANCE_CNTL ((0x000e << 2) + 0xfe052000)
+#define SPICC1_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe052000)
+#define SPICC1_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe052000)
+//========================================================================
+// AIFIFO - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe046000
+// -----------------------------------------------
+#define AIU_AIFIFO_CTRL ((0x0000 << 2) + 0xfe046000)
+#define AIU_AIFIFO_STATUS ((0x0001 << 2) + 0xfe046000)
+#define AIU_AIFIFO_GBIT ((0x0002 << 2) + 0xfe046000)
+#define AIU_AIFIFO_CLB ((0x0003 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_START_PTR ((0x0004 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_CURR_PTR ((0x0005 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_END_PTR ((0x0006 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_BYTES_AVAIL ((0x0007 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_CONTROL ((0x0008 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_MAN_WP ((0x0009 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_MAN_RP ((0x000a << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_LEVEL ((0x000b << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_BUF_CNTL ((0x000c << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_BUF_WRAP_COUNT ((0x000d << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_MEM_CTL ((0x000f << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_CNTL ((0x0010 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_SYNC_0 ((0x0011 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_SYNC_1 ((0x0012 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_0 ((0x0013 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_1 ((0x0014 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_2 ((0x0015 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_3 ((0x0016 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_LENGTH ((0x0017 << 2) + 0xfe046000)
+//========================================================================
+// MSR_CLK - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe048000
+// -----------------------------------------------
+#define MSR_CLK_REG0 ((0x0000 << 2) + 0xfe048000)
+#define MSR_CLK_REG1 ((0x0001 << 2) + 0xfe048000)
+#define MSR_CLK_REG2 ((0x0002 << 2) + 0xfe048000)
+#define MSR_CLK_REG3 ((0x0003 << 2) + 0xfe048000)
+#define MSR_CLK_REG4 ((0x0004 << 2) + 0xfe048000)
+#define MSR_CLK_REG5 ((0x0005 << 2) + 0xfe048000)
+#define MSR_CLK_DUTY ((0x0006 << 2) + 0xfe048000)
+//========================================================================
+// SPIFC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe056000
+// -----------------------------------------------
+#define SPI_FLASH_CMD ((0x0000 << 2) + 0xfe056000)
+ // SPI_FLASH_READ 31
+ // SPI_FLASH_WREN 30
+ // SPI_FLASH_WRDI 29
+ // SPI_FLASH_RDID 28
+ // SPI_FLASH_RDSR 27
+ // SPI_FLASH_WRSR 26
+ // SPI_FLASH_PP 25
+ // SPI_FLASH_SE 24
+ // SPI_FLASH_BE 23
+ // SPI_FLASH_CE 22
+ // SPI_FLASH_DP 21
+ // SPI_FLASH_RES 20
+ // SPI_HPM 19
+ // SPI_FLASH_USR 18
+ // SPI_FLASH_USR_ADDR 15
+ // SPI_FLASH_USR_DUMMY 14
+ // SPI_FLASH_USR_DIN 13
+ // SPI_FLASH_USR_DOUT 12
+ // SPI_FLASH_USR_DUMMY_BLEN 10
+ // SPI_FLASH_USR_CMD 0
+#define SPI_FLASH_ADDR ((0x0001 << 2) + 0xfe056000)
+ // SPI_FLASH_BYTES_LEN 24
+ // SPI_FLASH_ADDR_START 0
+#define SPI_FLASH_CTRL ((0x0002 << 2) + 0xfe056000)
+ // SPI_ENABLE_AHB 17
+ // SPI_SST_AAI 16
+ // SPI_RES_RID 15
+ // SPI_FREAD_DUAL 14
+ // SPI_READ_READ_EN 13
+ // SPI_CLK_DIV0 12
+ // SPI_CLKCNT_N 8
+ // SPI_CLKCNT_H 4
+ // SPI_CLKCNT_L 0
+#define SPI_FLASH_CTRL1 ((0x0003 << 2) + 0xfe056000)
+#define SPI_FLASH_STATUS ((0x0004 << 2) + 0xfe056000)
+#define SPI_FLASH_CTRL2 ((0x0005 << 2) + 0xfe056000)
+#define SPI_FLASH_CLOCK ((0x0006 << 2) + 0xfe056000)
+#define SPI_FLASH_USER ((0x0007 << 2) + 0xfe056000)
+#define SPI_FLASH_USER1 ((0x0008 << 2) + 0xfe056000)
+#define SPI_FLASH_USER2 ((0x0009 << 2) + 0xfe056000)
+#define SPI_FLASH_USER3 ((0x000a << 2) + 0xfe056000)
+#define SPI_FLASH_USER4 ((0x000b << 2) + 0xfe056000)
+#define SPI_FLASH_SLAVE ((0x000c << 2) + 0xfe056000)
+#define SPI_FLASH_SLAVE1 ((0x000d << 2) + 0xfe056000)
+#define SPI_FLASH_SLAVE2 ((0x000e << 2) + 0xfe056000)
+#define SPI_FLASH_SLAVE3 ((0x000f << 2) + 0xfe056000)
+#define SPI_FLASH_C0 ((0x0010 << 2) + 0xfe056000)
+#define SPI_FLASH_C1 ((0x0011 << 2) + 0xfe056000)
+#define SPI_FLASH_C2 ((0x0012 << 2) + 0xfe056000)
+#define SPI_FLASH_C3 ((0x0013 << 2) + 0xfe056000)
+#define SPI_FLASH_C4 ((0x0014 << 2) + 0xfe056000)
+#define SPI_FLASH_C5 ((0x0015 << 2) + 0xfe056000)
+#define SPI_FLASH_C6 ((0x0016 << 2) + 0xfe056000)
+#define SPI_FLASH_C7 ((0x0017 << 2) + 0xfe056000)
+#define SPI_FLASH_B8 ((0x0018 << 2) + 0xfe056000)
+#define SPI_FLASH_B9 ((0x0019 << 2) + 0xfe056000)
+#define SPI_FLASH_B10 ((0x001a << 2) + 0xfe056000)
+#define SPI_FLASH_B11 ((0x001b << 2) + 0xfe056000)
+#define SPI_FLASH_B12 ((0x001c << 2) + 0xfe056000)
+#define SPI_FLASH_B13 ((0x001d << 2) + 0xfe056000)
+#define SPI_FLASH_B14 ((0x001e << 2) + 0xfe056000)
+#define SPI_FLASH_B15 ((0x001f << 2) + 0xfe056000)
+//========================================================================
+// CEC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe044000
+// -----------------------------------------------
+#define CECA_GEN_CNTL ((0x0000 << 2) + 0xfe044000)
+#define CECA_RW_REG ((0x0001 << 2) + 0xfe044000)
+#define CECA_INTR_MASKN ((0x0002 << 2) + 0xfe044000)
+#define CECA_INTR_CLR ((0x0003 << 2) + 0xfe044000)
+#define CECA_INTR_STAT ((0x0004 << 2) + 0xfe044000)
+#define CECB_GEN_CNTL ((0x0010 << 2) + 0xfe044000)
+#define CECB_RW_REG ((0x0011 << 2) + 0xfe044000)
+#define CECB_INTR_MASKN ((0x0012 << 2) + 0xfe044000)
+#define CECB_INTR_CLR ((0x0013 << 2) + 0xfe044000)
+#define CECB_INTR_STAT ((0x0014 << 2) + 0xfe044000)
+//========================================================================
+// SMART CARD - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe038000
+// -----------------------------------------------
+#define SMARTCARD_REG0 ((0x0000 << 2) + 0xfe038000)
+#define SMARTCARD_REG1 ((0x0001 << 2) + 0xfe038000)
+#define SMARTCARD_REG2 ((0x0002 << 2) + 0xfe038000)
+#define SMARTCARD_STATUS ((0x0003 << 2) + 0xfe038000)
+#define SMARTCARD_INTR ((0x0004 << 2) + 0xfe038000)
+#define SMARTCARD_REG5 ((0x0005 << 2) + 0xfe038000)
+#define SMARTCARD_REG6 ((0x0006 << 2) + 0xfe038000)
+#define SMARTCARD_FIFO ((0x0007 << 2) + 0xfe038000)
+#define SMARTCARD_REG8 ((0x0008 << 2) + 0xfe038000)
+//========================================================================
+// CAPU
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe012000
+// -----------------------------------------------
+#define CAPU_ACCESS_EN_AHB_ETH ((0x00c2 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_AHB_USB0 ((0x00c1 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_AHB_USB1 ((0x00c0 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_16M_SLOT0 ((0x00b0 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_256K_SLOT1 ((0x00a1 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_256K_SLOT0 ((0x00a0 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT5 ((0x0085 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT4 ((0x0084 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT3 ((0x0083 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT2 ((0x0082 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT1 ((0x0081 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT0 ((0x0080 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT4F ((0x004f << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT4E ((0x004e << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT4D ((0x004d << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT4C ((0x004c << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT4B ((0x004b << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT4A ((0x004a << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT49 ((0x0049 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT48 ((0x0048 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT47 ((0x0047 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT46 ((0x0046 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT45 ((0x0045 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT44 ((0x0044 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT43 ((0x0043 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT42 ((0x0042 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT41 ((0x0041 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT40 ((0x0040 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT3F ((0x003f << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT3E ((0x003e << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT3D ((0x003d << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT3C ((0x003c << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT3B ((0x003b << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT3A ((0x003a << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT39 ((0x0039 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT38 ((0x0038 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT37 ((0x0037 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT36 ((0x0036 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT35 ((0x0035 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT34 ((0x0034 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT33 ((0x0033 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT32 ((0x0032 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT31 ((0x0031 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT30 ((0x0030 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT2F ((0x002f << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT2E ((0x002e << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT2D ((0x002d << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT2C ((0x002c << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT2B ((0x002b << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT2A ((0x002a << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT29 ((0x0029 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT28 ((0x0028 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT27 ((0x0027 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT26 ((0x0026 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT25 ((0x0025 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT24 ((0x0024 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT23 ((0x0023 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT22 ((0x0022 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT21 ((0x0021 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT20 ((0x0020 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT1F ((0x001f << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT1E ((0x001e << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT1D ((0x001d << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT1C ((0x001c << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT1B ((0x001b << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT1A ((0x001a << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT19 ((0x0019 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT18 ((0x0018 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT17 ((0x0017 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT16 ((0x0016 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT15 ((0x0015 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT14 ((0x0014 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT13 ((0x0013 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT12 ((0x0012 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT11 ((0x0011 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT10 ((0x0010 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT0F ((0x000f << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT0E ((0x000e << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT0D ((0x000d << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT0C ((0x000c << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT0B ((0x000b << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT0A ((0x000a << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT09 ((0x0009 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT08 ((0x0008 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT07 ((0x0007 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT06 ((0x0006 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT05 ((0x0005 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT04 ((0x0004 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT03 ((0x0003 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT02 ((0x0002 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT01 ((0x0001 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT00 ((0x0000 << 2) + 0xfe012000)
+//========================================================================
+// BT656
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe030000
+// -----------------------------------------------
+#define BT_CTRL ((0x0000 << 2) + 0xfe030000)
+ #define BT_SOFT_RESET 31 // Soft reset
+ #define BT_JPEG_START 30
+ #define BT_JPEG_IGNORE_BYTES 18 //20:18
+ #define BT_JPEG_IGNORE_LAST 17
+ #define BT_UPDATE_ST_SEL 16
+ #define BT_COLOR_REPEAT 15
+ #define BT_VIDEO_MODE 13 // 14:13
+ #define BT_AUTO_FMT 12
+ #define BT_PROG_MODE 11
+ #define BT_JPEG_MODE 10
+ #define BT_XCLK27_EN_BIT 9 // 1 : xclk27 is input. 0 : xclk27 is output.
+ #define BT_FID_EN_BIT 8 // 1 : enable use FID port.
+ #define BT_CLK27_SEL_BIT 7 // 1 : external xclk27 0 : internal clk27.
+ #define BT_CLK27_PHASE_BIT 6 // 1 : no inverted 0 : inverted.
+ #define BT_ACE_MODE_BIT 5 // 1 : auto cover error by hardware.
+ #define BT_SLICE_MODE_BIT 4 // 1 : no ancillay flag 0 : with ancillay flag.
+ #define BT_FMT_MODE_BIT 3 // 1 : ntsc 0 : pal.
+ #define BT_REF_MODE_BIT 2 // 1 : from bit stream. 0 : from ports.
+ #define BT_MODE_BIT 1 // 1 : BT656 model 0 : SAA7118 mode.
+ #define BT_EN_BIT 0 // 1 : enable.
+#define BT_VBISTART ((0x0001 << 2) + 0xfe030000)
+#define BT_VBIEND ((0x0002 << 2) + 0xfe030000)
+#define BT_FIELDSADR ((0x0003 << 2) + 0xfe030000)
+#define BT_LINECTRL ((0x0004 << 2) + 0xfe030000)
+#define BT_VIDEOSTART ((0x0005 << 2) + 0xfe030000)
+#define BT_VIDEOEND ((0x0006 << 2) + 0xfe030000)
+#define BT_SLICELINE0 ((0x0007 << 2) + 0xfe030000)
+#define BT_SLICELINE1 ((0x0008 << 2) + 0xfe030000)
+#define BT_PORT_CTRL ((0x0009 << 2) + 0xfe030000)
+ #define BT_HSYNC_PHASE 0
+ #define BT_VSYNC_PHASE 1
+ #define BT_HSYNC_PULSE 2
+ #define BT_VSYNC_PULSE 3
+ #define BT_FID_PHASE 4
+ #define BT_FID_HSVS 5
+ #define BT_IDQ_EN 6
+ #define BT_IDQ_PHASE 7
+ #define BT_D8B 8
+ #define BT_10BTO8B 9
+ #define BT_FID_DELAY 10 //12:10
+ #define BT_VSYNC_DELAY 13 //
+ #define BT_HSYNC_DELAY 16
+ #define BT_FID_HSVS_PCNT 19
+ #define BT_FID_HSVS_VS_RISING 20
+ #define BT_FID_HSVS_VS_FALLING 21
+ #define BT_VREF_FROM_VS_ONLY 22
+ #define BT_PORT_ACTIVE_HMODE 23
+ #define BT_DUAL_EDGE_CLK_EN 24
+ #define BT_CLK_INV_SEL 25
+ #define BT_DATA_ENDIAN 26
+#define BT_SWAP_CTRL ((0x000a << 2) + 0xfe030000)
+#define BT_601_CTRL0 ((0x000e << 2) + 0xfe030000)
+#define BT_601_CTRL1 ((0x000f << 2) + 0xfe030000)
+#define BT_601_CTRL2 ((0x0010 << 2) + 0xfe030000)
+#define BT_601_CTRL3 ((0x0011 << 2) + 0xfe030000)
+#define BT_FIELD_LUMA ((0x0012 << 2) + 0xfe030000)
+#define BT_RAW_CTRL ((0x0013 << 2) + 0xfe030000)
+#define BT_STATUS ((0x0014 << 2) + 0xfe030000)
+#define BT_INT_CTRL ((0x0015 << 2) + 0xfe030000)
+#define BT_VLINE_STATUS ((0x0017 << 2) + 0xfe030000)
+#define BT_ERR_CNT ((0x0019 << 2) + 0xfe030000)
+#define BT_LCNT_STATUS ((0x001a << 2) + 0xfe030000)
+#define BT_PCNT_STATUS ((0x001c << 2) + 0xfe030000)
+#define BT_DELAY_CTRL ((0x001d << 2) + 0xfe030000)
+#define BT_REF_000 ((0x0020 << 2) + 0xfe030000)
+#define BT_REF_001 ((0x0021 << 2) + 0xfe030000)
+#define BT_REF_010 ((0x0022 << 2) + 0xfe030000)
+#define BT_REF_011 ((0x0023 << 2) + 0xfe030000)
+#define BT_REF_100 ((0x0024 << 2) + 0xfe030000)
+#define BT_REF_101 ((0x0025 << 2) + 0xfe030000)
+#define BT_REF_110 ((0x0026 << 2) + 0xfe030000)
+#define BT_REF_111 ((0x0027 << 2) + 0xfe030000)
+//========================================================================
+// PDM
+//========================================================================
+//`include "../audio/rtl/pdm_reg.vh"
+//
+// Reading file: REG_LIST_AUDIO_RTL.h
+//
+//========================================================================
+// AUDIO - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe330000
+// -----------------------------------------------
+#define EE_AUDIO_CLK_GATE_EN0 ((0x0000 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_GATE_EN1 ((0x0001 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_A_CTRL ((0x0002 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_B_CTRL ((0x0003 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_C_CTRL ((0x0004 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_D_CTRL ((0x0005 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_E_CTRL ((0x0006 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_F_CTRL ((0x0007 << 2) + 0xfe330000)
+#define EE_AUDIO_SW_RESET0 ((0x000a << 2) + 0xfe330000)
+#define EE_AUDIO_SW_RESET1 ((0x000b << 2) + 0xfe330000)
+#define EE_AUDIO_CLK81_CTRL ((0x000c << 2) + 0xfe330000)
+#define EE_AUDIO_CLK81_EN ((0x000d << 2) + 0xfe330000)
+#define EE_AUDIO_MST_A_SCLK_CTRL0 ((0x0010 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_A_SCLK_CTRL1 ((0x0011 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_B_SCLK_CTRL0 ((0x0012 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_B_SCLK_CTRL1 ((0x0013 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_C_SCLK_CTRL0 ((0x0014 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_C_SCLK_CTRL1 ((0x0015 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_D_SCLK_CTRL0 ((0x0016 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_D_SCLK_CTRL1 ((0x0017 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_E_SCLK_CTRL0 ((0x0018 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_E_SCLK_CTRL1 ((0x0019 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_F_SCLK_CTRL0 ((0x001a << 2) + 0xfe330000)
+#define EE_AUDIO_MST_F_SCLK_CTRL1 ((0x001b << 2) + 0xfe330000)
+#define EE_AUDIO_MST_DLY_CTRL0 ((0x001c << 2) + 0xfe330000)
+#define EE_AUDIO_MST_DLY_CTRL1 ((0x001d << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMIN_A_CTRL ((0x0020 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMIN_B_CTRL ((0x0021 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMIN_C_CTRL ((0x0022 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMIN_LB_CTRL ((0x0023 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMOUT_A_CTRL ((0x0024 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMOUT_B_CTRL ((0x0025 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMOUT_C_CTRL ((0x0026 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_SPDIFIN_CTRL ((0x0027 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_SPDIFOUT_CTRL ((0x0028 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_RESAMPLEA_CTRL ((0x0029 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_LOCKER_CTRL ((0x002a << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_PDMIN_CTRL0 ((0x002b << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_PDMIN_CTRL1 ((0x002c << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_SPDIFOUT_B_CTRL ((0x002d << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_RESAMPLEB_CTRL ((0x002e << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_SPDIFIN_LB_CTRL ((0x002f << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_EQDRC_CTRL0 ((0x0030 << 2) + 0xfe330000)
+#define EE_AUDIO_VAD_CLK_CTRL ((0x0031 << 2) + 0xfe330000)
+#define EE_AUDIO_EARCTX_CMDC_CLK_CTRL ((0x0032 << 2) + 0xfe330000)
+#define EE_AUDIO_EARCTX_DMAC_CLK_CTRL ((0x0033 << 2) + 0xfe330000)
+#define EE_AUDIO_EARCRX_CMDC_CLK_CTRL ((0x0034 << 2) + 0xfe330000)
+#define EE_AUDIO_EARCRX_DMAC_CLK_CTRL ((0x0035 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_LOCKERB_CTRL ((0x0036 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CTRL0 ((0x0040 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CTRL1 ((0x0041 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_START_ADDR ((0x0042 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_FINISH_ADDR ((0x0043 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_INT_ADDR ((0x0044 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_STATUS1 ((0x0045 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_STATUS2 ((0x0046 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_START_ADDRB ((0x0047 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_FINISH_ADDRB ((0x0048 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_INIT_ADDR ((0x0049 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CTRL2 ((0x004a << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CTRL0 ((0x0050 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CTRL1 ((0x0051 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_START_ADDR ((0x0052 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_FINISH_ADDR ((0x0053 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_INT_ADDR ((0x0054 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_STATUS1 ((0x0055 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_STATUS2 ((0x0056 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_START_ADDRB ((0x0057 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_FINISH_ADDRB ((0x0058 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_INIT_ADDR ((0x0059 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CTRL2 ((0x005a << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CTRL0 ((0x0060 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CTRL1 ((0x0061 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_START_ADDR ((0x0062 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_FINISH_ADDR ((0x0063 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_INT_ADDR ((0x0064 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_STATUS1 ((0x0065 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_STATUS2 ((0x0066 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_START_ADDRB ((0x0067 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_FINISH_ADDRB ((0x0068 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_INIT_ADDR ((0x0069 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CTRL2 ((0x006a << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_CTRL0 ((0x0070 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_CTRL1 ((0x0071 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_START_ADDR ((0x0072 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_FINISH_ADDR ((0x0073 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_INT_ADDR ((0x0074 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_STATUS1 ((0x0075 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_STATUS2 ((0x0076 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_START_ADDRB ((0x0077 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_FINISH_ADDRB ((0x0078 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_INIT_ADDR ((0x0079 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_CTRL2 ((0x007a << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_CTRL0 ((0x0080 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_CTRL1 ((0x0081 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_START_ADDR ((0x0082 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_FINISH_ADDR ((0x0083 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_INT_ADDR ((0x0084 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_STATUS1 ((0x0085 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_STATUS2 ((0x0086 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_START_ADDRB ((0x0087 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_FINISH_ADDRB ((0x0088 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_INIT_ADDR ((0x0089 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_CTRL2 ((0x008a << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_CTRL0 ((0x0090 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_CTRL1 ((0x0091 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_START_ADDR ((0x0092 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_FINISH_ADDR ((0x0093 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_INT_ADDR ((0x0094 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_STATUS1 ((0x0095 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_STATUS2 ((0x0096 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_START_ADDRB ((0x0097 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_FINISH_ADDRB ((0x0098 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_INIT_ADDR ((0x0099 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_CTRL2 ((0x009a << 2) + 0xfe330000)
+#define EE_AUDIO_ARB_CTRL0 ((0x00a0 << 2) + 0xfe330000)
+#define EE_AUDIO_ARB_CTRL1 ((0x00a1 << 2) + 0xfe330000)
+#define EE_AUDIO_ARB_STS ((0x00a8 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CTRL0 ((0x00b0 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CTRL1 ((0x00b1 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CTRL2 ((0x00b2 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CTRL3 ((0x00b3 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_DAT_CH_ID0 ((0x00b4 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_DAT_CH_ID1 ((0x00b5 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_DAT_CH_ID2 ((0x00b6 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_DAT_CH_ID3 ((0x00b7 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_LB_CH_ID0 ((0x00b8 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_LB_CH_ID1 ((0x00b9 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_LB_CH_ID2 ((0x00ba << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_LB_CH_ID3 ((0x00bb << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_STS ((0x00bc << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CHSYNC_CTRL_INSERT ((0x00bd << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CHSYNC_CTRL_ORIG ((0x00be << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CTRL4 ((0x00bf << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_CTRL ((0x00c0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_SWAP0 ((0x00c1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK0 ((0x00c2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK1 ((0x00c3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK2 ((0x00c4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK3 ((0x00c5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_STAT ((0x00c6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE_VAL ((0x00c7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE0 ((0x00c8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE1 ((0x00c9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE2 ((0x00ca << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE3 ((0x00cb << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_CTRL ((0x00d0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_SWAP0 ((0x00d1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK0 ((0x00d2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK1 ((0x00d3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK2 ((0x00d4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK3 ((0x00d5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_STAT ((0x00d6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE_VAL ((0x00d7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE0 ((0x00d8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE1 ((0x00d9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE2 ((0x00da << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE3 ((0x00db << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_CTRL ((0x00e0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_SWAP0 ((0x00e1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK0 ((0x00e2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK1 ((0x00e3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK2 ((0x00e4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK3 ((0x00e5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_STAT ((0x00e6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE_VAL ((0x00e7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE0 ((0x00e8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE1 ((0x00e9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE2 ((0x00ea << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE3 ((0x00eb << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_CTRL ((0x00f0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_SWAP0 ((0x00f1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK0 ((0x00f2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK1 ((0x00f3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK2 ((0x00f4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK3 ((0x00f5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_STAT ((0x00f6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE_VAL ((0x00f7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE0 ((0x00f8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE1 ((0x00f9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE2 ((0x00fa << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE3 ((0x00fb << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL0 ((0x0100 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL1 ((0x0101 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL2 ((0x0102 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL3 ((0x0103 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL4 ((0x0104 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL5 ((0x0105 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL6 ((0x0106 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_STAT0 ((0x0107 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_STAT1 ((0x0108 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_STAT2 ((0x0109 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_MUTE_VAL ((0x010a << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL7 ((0x010b << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_CTRL0 ((0x0110 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_CTRL1 ((0x0111 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_CTRL2 ((0x0112 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_CTRL3 ((0x0113 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_COEF0 ((0x0114 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_COEF1 ((0x0115 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_COEF2 ((0x0116 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_COEF3 ((0x0117 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_COEF4 ((0x0118 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_STATUS1 ((0x0119 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_STAT ((0x0120 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_GAIN0 ((0x0121 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_GAIN1 ((0x0122 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CTRL0 ((0x0123 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CTRL1 ((0x0124 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_PREAMB ((0x0125 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_SWAP ((0x0126 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS0 ((0x0127 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS1 ((0x0128 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS2 ((0x0129 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS3 ((0x012a << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS4 ((0x012b << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS5 ((0x012c << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS6 ((0x012d << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS7 ((0x012e << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS8 ((0x012f << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS9 ((0x0130 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTSA ((0x0131 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTSB ((0x0132 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_MUTE_VAL ((0x0133 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_GAIN2 ((0x0134 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_GAIN3 ((0x0135 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_GAIN_EN ((0x0136 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_GAIN_CTRL ((0x0137 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_CTRL0 ((0x0140 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_CTRL1 ((0x0141 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_SWAP0 ((0x0142 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK0 ((0x0143 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK1 ((0x0144 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK2 ((0x0145 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK3 ((0x0146 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_STAT ((0x0147 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_GAIN0 ((0x0148 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_GAIN1 ((0x0149 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE_VAL ((0x014a << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE0 ((0x014b << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE1 ((0x014c << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE2 ((0x014d << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE3 ((0x014e << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK_VAL ((0x014f << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_CTRL0 ((0x0150 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_CTRL1 ((0x0151 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_SWAP0 ((0x0152 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK0 ((0x0153 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK1 ((0x0154 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK2 ((0x0155 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK3 ((0x0156 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_STAT ((0x0157 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_GAIN0 ((0x0158 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_GAIN1 ((0x0159 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE_VAL ((0x015a << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE0 ((0x015b << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE1 ((0x015c << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE2 ((0x015d << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE3 ((0x015e << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK_VAL ((0x015f << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_CTRL0 ((0x0160 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_CTRL1 ((0x0161 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_SWAP0 ((0x0162 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK0 ((0x0163 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK1 ((0x0164 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK2 ((0x0165 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK3 ((0x0166 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_STAT ((0x0167 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_GAIN0 ((0x0168 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_GAIN1 ((0x0169 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE_VAL ((0x016a << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE0 ((0x016b << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE1 ((0x016c << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE2 ((0x016d << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE3 ((0x016e << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK_VAL ((0x016f << 2) + 0xfe330000)
+//`define EE_AUDIO_POW_DET_CTRL0 10'h180
+//`define EE_AUDIO_POW_DET_CTRL1 10'h181
+//`define EE_AUDIO_POW_DET_TH_HI 10'h182
+//`define EE_AUDIO_POW_DET_TH_LO 10'h183
+//`define EE_AUDIO_POW_DET_VALUE 10'h184
+#define EE_AUDIO_SECURITY_CTRL0 ((0x0190 << 2) + 0xfe330000)
+#define EE_AUDIO_SECURITY_CTRL1 ((0x0191 << 2) + 0xfe330000)
+#define EE_AUDIO_SECURITY_CTRL2 ((0x0192 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_STAT ((0x01a0 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN0 ((0x01a1 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN1 ((0x01a2 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CTRL0 ((0x01a3 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CTRL1 ((0x01a4 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_PREAMB ((0x01a5 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_SWAP ((0x01a6 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS0 ((0x01a7 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS1 ((0x01a8 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS2 ((0x01a9 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS3 ((0x01aa << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS4 ((0x01ab << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS5 ((0x01ac << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS6 ((0x01ad << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS7 ((0x01ae << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS8 ((0x01af << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS9 ((0x01b0 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTSA ((0x01b1 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTSB ((0x01b2 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_MUTE_VAL ((0x01b3 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN2 ((0x01b4 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN3 ((0x01b5 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN_EN ((0x01b6 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN_CTRL ((0x01b7 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_CTRL0 ((0x01c0 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_CTRL1 ((0x01c1 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_START_ADDR ((0x01c2 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_FINISH_ADDR ((0x01c3 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_INT_ADDR ((0x01c4 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_STATUS1 ((0x01c5 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_STATUS2 ((0x01c6 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_INIT_ADDR ((0x01c7 << 2) + 0xfe330000)
+#define EE_AUDIO_TOACODEC_CTRL0 ((0x01d0 << 2) + 0xfe330000)
+#define EE_AUDIO_TOHDMITX_CTRL0 ((0x01d1 << 2) + 0xfe330000)
+#define EE_AUDIO_TOVAD_CTRL0 ((0x01d2 << 2) + 0xfe330000)
+#define EE_AUDIO_FRATV_CTRL0 ((0x01d3 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_CTRL0 ((0x01e0 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_CTRL1 ((0x01e1 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_CTRL2 ((0x01e2 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_CTRL3 ((0x01e3 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_COEF0 ((0x01e4 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_COEF1 ((0x01e5 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_COEF2 ((0x01e6 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_COEF3 ((0x01e7 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_COEF4 ((0x01e8 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_STATUS1 ((0x01e9 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_LB_CTRL0 ((0x01f0 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_LB_CTRL1 ((0x01f1 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_LB_CTRL6 ((0x01f6 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_LB_STAT0 ((0x01f7 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_LB_STAT1 ((0x01f8 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_LB_MUTE_VAL ((0x01fa << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL0 ((0x0200 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL1 ((0x0201 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL2 ((0x0202 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL3 ((0x0203 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL4 ((0x0204 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL5 ((0x0205 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL6 ((0x0206 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL7 ((0x0207 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_STAT0 ((0x020a << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_STAT1 ((0x020b << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CTRL0 ((0x0210 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CTRL1 ((0x0211 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_START_ADDR ((0x0212 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_FINISH_ADDR ((0x0213 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_INT_ADDR ((0x0214 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_STATUS1 ((0x0215 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_STATUS2 ((0x0216 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_START_ADDRB ((0x0217 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_FINISH_ADDRB ((0x0218 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_INIT_ADDR ((0x0219 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CTRL2 ((0x021a << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_CTRL0 ((0x0220 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_CTRL1 ((0x0221 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_START_ADDR ((0x0222 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_FINISH_ADDR ((0x0223 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_INT_ADDR ((0x0224 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_STATUS1 ((0x0225 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_STATUS2 ((0x0226 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_START_ADDRB ((0x0227 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_FINISH_ADDRB ((0x0228 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_INIT_ADDR ((0x0229 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_CTRL2 ((0x022a << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CTRL0 ((0x0230 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CTRL1 ((0x0231 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CTRL2 ((0x0232 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CTRL3 ((0x0233 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_DAT_CH_ID0 ((0x0234 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_DAT_CH_ID1 ((0x0235 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_DAT_CH_ID2 ((0x0236 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_DAT_CH_ID3 ((0x0237 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_LB_CH_ID0 ((0x0238 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_LB_CH_ID1 ((0x0239 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_LB_CH_ID2 ((0x023a << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_LB_CH_ID3 ((0x023b << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_STS ((0x023c << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CHSYNC_CTRL_INSERT ((0x023d << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CHSYNC_CTRL_ORIG ((0x023e << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CTRL4 ((0x023f << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CTRL0 ((0x0240 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CTRL1 ((0x0241 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_START_ADDR ((0x0242 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_FINISH_ADDR ((0x0243 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_INT_ADDR ((0x0244 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_STATUS1 ((0x0245 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_STATUS2 ((0x0246 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_START_ADDRB ((0x0247 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_FINISH_ADDRB ((0x0248 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_INIT_ADDR ((0x0249 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CTRL2 ((0x024a << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_CTRL0 ((0x0250 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_CTRL1 ((0x0251 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_START_ADDR ((0x0252 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_FINISH_ADDR ((0x0253 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_INT_ADDR ((0x0254 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_STATUS1 ((0x0255 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_STATUS2 ((0x0256 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_START_ADDRB ((0x0257 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_FINISH_ADDRB ((0x0258 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_INIT_ADDR ((0x0259 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_CTRL2 ((0x025a << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_SWAP1 ((0x0260 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK4 ((0x0261 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK5 ((0x0262 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK6 ((0x0263 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK7 ((0x0264 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE4 ((0x0265 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE5 ((0x0266 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE6 ((0x0267 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE7 ((0x0268 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_SWAP1 ((0x0270 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK4 ((0x0271 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK5 ((0x0272 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK6 ((0x0273 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK7 ((0x0274 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE4 ((0x0275 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE5 ((0x0276 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE6 ((0x0277 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE7 ((0x0278 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_SWAP1 ((0x0280 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK4 ((0x0281 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK5 ((0x0282 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK6 ((0x0283 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK7 ((0x0284 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE4 ((0x0285 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE5 ((0x0286 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE6 ((0x0287 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE7 ((0x0288 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_SWAP1 ((0x0290 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK4 ((0x0291 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK5 ((0x0292 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK6 ((0x0293 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK7 ((0x0294 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE4 ((0x0295 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE5 ((0x0296 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE6 ((0x0297 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE7 ((0x0298 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_CTRL2 ((0x02a0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_SWAP1 ((0x02a1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_GAIN2 ((0x02a2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_GAIN3 ((0x02a3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK4 ((0x02a4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK5 ((0x02a5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK6 ((0x02a6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK7 ((0x02a7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE4 ((0x02a8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE5 ((0x02a9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE6 ((0x02aa << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE7 ((0x02ab << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_GAIN_EN ((0x02ac << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_GAIN_CTRL ((0x02ad << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_CTRL2 ((0x02b0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_SWAP1 ((0x02b1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_GAIN2 ((0x02b2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_GAIN3 ((0x02b3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK4 ((0x02b4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK5 ((0x02b5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK6 ((0x02b6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK7 ((0x02b7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE4 ((0x02b8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE5 ((0x02b9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE6 ((0x02ba << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE7 ((0x02bb << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_GAIN_EN ((0x02bc << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_GAIN_CTRL ((0x02bd << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_CTRL2 ((0x02c0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_SWAP1 ((0x02c1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_GAIN2 ((0x02c2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_GAIN3 ((0x02c3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK4 ((0x02c4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK5 ((0x02c5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK6 ((0x02c6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK7 ((0x02c7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE4 ((0x02c8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE5 ((0x02c9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE6 ((0x02ca << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE7 ((0x02cb << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_GAIN_EN ((0x02cc << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_GAIN_CTRL ((0x02cd << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID0 ((0x0300 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID1 ((0x0301 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID2 ((0x0302 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID3 ((0x0303 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID4 ((0x0304 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID5 ((0x0305 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID6 ((0x0306 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID7 ((0x0307 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHSYNC_CTRL ((0x030f << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID0 ((0x0310 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID1 ((0x0311 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID2 ((0x0312 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID3 ((0x0313 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID4 ((0x0314 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID5 ((0x0315 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID6 ((0x0316 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID7 ((0x0317 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHSYNC_CTRL ((0x031f << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID0 ((0x0320 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID1 ((0x0321 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID2 ((0x0322 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID3 ((0x0323 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID4 ((0x0324 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID5 ((0x0325 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID6 ((0x0326 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID7 ((0x0327 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHSYNC_CTRL ((0x032f << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID0 ((0x0330 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID1 ((0x0331 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID2 ((0x0332 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID3 ((0x0333 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID4 ((0x0334 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID5 ((0x0335 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID6 ((0x0336 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID7 ((0x0337 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHSYNC_CTRL ((0x033f << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID0 ((0x0340 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID1 ((0x0341 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID2 ((0x0342 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID3 ((0x0343 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID4 ((0x0344 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID5 ((0x0345 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID6 ((0x0346 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID7 ((0x0347 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHSYNC_CTRL ((0x034f << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID0 ((0x0350 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID1 ((0x0351 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID2 ((0x0352 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID3 ((0x0353 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID4 ((0x0354 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID5 ((0x0355 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID6 ((0x0356 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID7 ((0x0357 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_CHSYNC_MASK ((0x035e << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHSYNC_CTRL ((0x035f << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID0 ((0x0360 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID1 ((0x0361 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID2 ((0x0362 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID3 ((0x0363 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID4 ((0x0364 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID5 ((0x0365 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID6 ((0x0366 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID7 ((0x0367 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHSYNC_CTRL ((0x036f << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID0 ((0x0370 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID1 ((0x0371 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID2 ((0x0372 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID3 ((0x0373 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID4 ((0x0374 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID5 ((0x0375 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID6 ((0x0376 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID7 ((0x0377 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHSYNC_CTRL ((0x037f << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_STS0 ((0x0380 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_STS1 ((0x0381 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_MASK0 ((0x0382 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_MASK1 ((0x0383 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_MODE0 ((0x0384 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_MODE1 ((0x0385 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_CLR0 ((0x0386 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_CLR1 ((0x0387 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_INV0 ((0x0388 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_INV1 ((0x0389 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL0 ((0x0390 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL1 ((0x0391 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL2 ((0x0392 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL3 ((0x0393 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL4 ((0x0394 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL5 ((0x0395 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL6 ((0x0396 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL7 ((0x0397 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL8 ((0x0398 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL9 ((0x0399 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRLA ((0x039a << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRLB ((0x039b << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRLC ((0x039c << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRLD ((0x039d << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRLE ((0x039e << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRLF ((0x039f << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_PAD_CTRL0 ((0x03a0 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_PAD_CTRL1 ((0x03a1 << 2) + 0xfe330000)
+#define EE_AUDIO_SCLK_PAD_CTRL0 ((0x03a2 << 2) + 0xfe330000)
+#define EE_AUDIO_LRCLK_PAD_CTRL0 ((0x03a3 << 2) + 0xfe330000)
+//========================================================================
+// PDM - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe331000
+// -----------------------------------------------
+#define PDM_CTRL ((0x0000 << 2) + 0xfe331000)
+ //bit 31: PDM enable.
+ //bit 30: invert the PDM_DCLK.
+ //bit 29: output mode: 1: 24bits. 0: 32 bits.
+ //bit 28: bypass mode. 1: bypass all filter. directly output the PDM input to DDR. 0: normal mode.
+ //bit 27~9: not used.
+ //bit 16:. PDM Asynchronous FIFO soft reset. write 1 to soft reset AFIFO.
+ //bit 15:8 PDM channel reset. 0: to reset each PDM channel. 1: normal mode.
+ //bit 7:0. PDM channel enable. each bit for one channel.
+#define PDM_HCIC_CTRL1 ((0x0001 << 2) + 0xfe331000)
+ //bit 31 hcic filter enable. 1 use sinc filter. 0 bypass input to output.
+ //bit 29:24. hcic final gain shift parameter.
+ //bit 23:16 hcic final gain multiplier.
+ //bit 8:4 hcic down sample rate.
+ //bit 3:0 hcic stage number. must be between 3 to 9.
+#define PDM_HCIC_CTRL2 ((0x0002 << 2) + 0xfe331000)
+ //Not used.
+#define PDM_F1_CTRL ((0x0003 << 2) + 0xfe331000)
+ //bit 31 . filter 1 enable.
+ //bit 16:15. f1 round mode. 2'b00 : sign bit at bit 49. 28bits output [49:22] round at bit 21. 32bits output [49:18]. 24bits output [49:26]
+ // 2'b01 : sign bit at bit 50. 28bits output [50:23] round at bit 22. 32bits output [49:18]. 24bits output [49:26]
+ // 2'b10 : sign bit at bit 51. 28bits output [51:24] round at bit 23 32bits output [49:18]. 24bits output [49:26].
+ //bit 15:12. filter 1 down sample rate.
+ //bit 8:0. filter 1 stage number.
+#define PDM_F2_CTRL ((0x0004 << 2) + 0xfe331000)
+ //bit 31 . filter 2 enable.
+ //bit 16:15. f2 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23.
+ //bit 15:12. filter 2 down sample rate.
+ //bit 8:0. filter 2 stage number.
+#define PDM_F3_CTRL ((0x0005 << 2) + 0xfe331000)
+ //bit 31 . filter 3 enable.
+ //bit 16:15. f3 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23.
+ //bit 15:12. filter 3 down sample rate.
+ //bit 8:0. filter 3 stage number.
+#define PDM_HPF_CTRL ((0x0006 << 2) + 0xfe331000)
+ //bit 31 High pass filter enable.
+ //bit 20:16 high pass filter shift steps. 6~19 steps.
+ //bit 15:0 high pass filter output factor.
+#define PDM_CHAN_CTRL ((0x0007 << 2) + 0xfe331000)
+ //bit 31:24. chan3 data sample pointer vs edge of the PDM_DCLK.
+ //bit 23:16 chan2 data sample pointer vs edge of the PDM_DCLK.
+ //bit 15:8. chan1 data sample pointer vs edge of the PDM_DCLK.
+ //bit 7:0 chan0 data sample pointer vs edge of the PDM_DCLK.
+#define PDM_CHAN_CTRL1 ((0x0008 << 2) + 0xfe331000)
+ //bit 31:24. chan7 data sample pointer vs edge of the PDM_DCLK.
+ //bit 23:16 chan6 data sample pointer vs edge of the PDM_DCLK.
+ //bit 15:8. chan5 data sample pointer vs edge of the PDM_DCLK.
+ //bit 7:0 chan4 data sample pointer vs edge of the PDM_DCLK.
+#define PDM_COEFF_ADDR ((0x0009 << 2) + 0xfe331000)
+ // address of the write/read of coeff data.
+#define PDM_COEFF_DATA ((0x000a << 2) + 0xfe331000)
+ //write/read data to coeff memory.
+#define PDM_CLKG_CTRL ((0x000b << 2) + 0xfe331000)
+ // auto clock gating control. 1: disable the clock gating function. the clock will awlays enabled. 0 : use RTL auto clock gating.
+ //31:7 not used.
+ //bit 6 filt_ctrl module auto clock gating control.
+ //bit 5 sinc fifo module auto clock gating control.
+ //bit 4 filter module auto clock gating control.
+ //bit 3 apb module auto clock gating control.
+ //bit 2 coeff memory module auto clock gating control.
+ //bit 1 each channel module auto clock gating control.
+ //bit 0 cts_pdm_clk auto clock gating control.
+#define PDM_STS ((0x000c << 2) + 0xfe331000)
+//bit 1 HPF filter output overflow. means the PCLK is too slow.
+//bit 0 HCIC filter output overflow. means the CTS_PDM_CLK is too slow. can't finished the filter function.
+#define PDM_MUTE_VALUE ((0x000d << 2) + 0xfe331000)
+#define PDM_MASK_NUM ((0x000e << 2) + 0xfe331000)
+#define PDM_CHAN_CTRL2 ((0x000f << 2) + 0xfe331000)
+ //bit 7:0 second sample and start FSM point vs rise edge of PDM_DCLK
+//========================================================================
+// EQ DRC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe332000
+// -----------------------------------------------
+#define AED_COEF_RAM_CNTL ((0x0000 << 2) + 0xfe332000)
+#define AED_COEF_RAM_DATA ((0x0001 << 2) + 0xfe332000)
+#define AED_EQ_EN ((0x0002 << 2) + 0xfe332000)
+#define AED_EQ_TAP_CNTL ((0x0003 << 2) + 0xfe332000)
+#define AED_EQ_VOLUME ((0x0004 << 2) + 0xfe332000)
+#define AED_EQ_VOLUME_SLEW_CNT ((0x0005 << 2) + 0xfe332000)
+#define AED_MUTE ((0x0006 << 2) + 0xfe332000)
+#define AED_DRC_CNTL ((0x0007 << 2) + 0xfe332000)
+#define AED_DRC_RMS_COEF0 ((0x0008 << 2) + 0xfe332000)
+#define AED_DRC_RMS_COEF1 ((0x0009 << 2) + 0xfe332000)
+#define AED_DRC_THD0 ((0x000a << 2) + 0xfe332000)
+#define AED_DRC_THD1 ((0x000b << 2) + 0xfe332000)
+#define AED_DRC_THD2 ((0x000c << 2) + 0xfe332000)
+#define AED_DRC_THD3 ((0x000d << 2) + 0xfe332000)
+#define AED_DRC_THD4 ((0x000e << 2) + 0xfe332000)
+#define AED_DRC_K0 ((0x000f << 2) + 0xfe332000)
+#define AED_DRC_K1 ((0x0010 << 2) + 0xfe332000)
+#define AED_DRC_K2 ((0x0011 << 2) + 0xfe332000)
+#define AED_DRC_K3 ((0x0012 << 2) + 0xfe332000)
+#define AED_DRC_K4 ((0x0013 << 2) + 0xfe332000)
+#define AED_DRC_K5 ((0x0014 << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT0 ((0x0015 << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT1 ((0x0016 << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT2 ((0x0017 << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT3 ((0x0018 << 2) + 0xfe332000)
+#define AED_DRC_OFFSET ((0x0019 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF00 ((0x001a << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF01 ((0x001b << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF10 ((0x001c << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF11 ((0x001d << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF20 ((0x001e << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF21 ((0x001f << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF30 ((0x0020 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF31 ((0x0021 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF40 ((0x0022 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF41 ((0x0023 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF50 ((0x0024 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF51 ((0x0025 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF00 ((0x0026 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF01 ((0x0027 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF10 ((0x0028 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF11 ((0x0029 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF20 ((0x002a << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF21 ((0x002b << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF30 ((0x002c << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF31 ((0x002d << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF40 ((0x002e << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF41 ((0x002f << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF50 ((0x0030 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF51 ((0x0031 << 2) + 0xfe332000)
+#define AED_DRC_LOOPBACK_CNTL ((0x0032 << 2) + 0xfe332000)
+#define AED_MDRC_CNTL ((0x0033 << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF00 ((0x0034 << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF01 ((0x0035 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF00 ((0x0036 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF01 ((0x0037 << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF00 ((0x0038 << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF01 ((0x0039 << 2) + 0xfe332000)
+#define AED_MDRC_THD0 ((0x003a << 2) + 0xfe332000)
+#define AED_MDRC_K0 ((0x003b << 2) + 0xfe332000)
+#define AED_MDRC_LOW_GAIN ((0x003c << 2) + 0xfe332000)
+#define AED_MDRC_OFFSET0 ((0x003d << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF10 ((0x003e << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF11 ((0x003f << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF10 ((0x0040 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF11 ((0x0041 << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF10 ((0x0042 << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF11 ((0x0043 << 2) + 0xfe332000)
+#define AED_MDRC_THD1 ((0x0044 << 2) + 0xfe332000)
+#define AED_MDRC_K1 ((0x0045 << 2) + 0xfe332000)
+#define AED_MDRC_OFFSET1 ((0x0046 << 2) + 0xfe332000)
+#define AED_MDRC_MID_GAIN ((0x0047 << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF20 ((0x0048 << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF21 ((0x0049 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF20 ((0x004a << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF21 ((0x004b << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF20 ((0x004c << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF21 ((0x004d << 2) + 0xfe332000)
+#define AED_MDRC_THD2 ((0x004e << 2) + 0xfe332000)
+#define AED_MDRC_K2 ((0x004f << 2) + 0xfe332000)
+#define AED_MDRC_OFFSET2 ((0x0050 << 2) + 0xfe332000)
+#define AED_MDRC_HIGH_GAIN ((0x0051 << 2) + 0xfe332000)
+#define AED_ED_CNTL ((0x0052 << 2) + 0xfe332000)
+#define AED_DC_EN ((0x0053 << 2) + 0xfe332000)
+#define AED_ND_LOW_THD ((0x0054 << 2) + 0xfe332000)
+#define AED_ND_HIGH_THD ((0x0055 << 2) + 0xfe332000)
+#define AED_ND_CNT_THD ((0x0056 << 2) + 0xfe332000)
+#define AED_ND_SUM_NUM ((0x0057 << 2) + 0xfe332000)
+#define AED_ND_CZ_NUM ((0x0058 << 2) + 0xfe332000)
+#define AED_ND_SUM_THD0 ((0x0059 << 2) + 0xfe332000)
+#define AED_ND_SUM_THD1 ((0x005a << 2) + 0xfe332000)
+#define AED_ND_CZ_THD0 ((0x005b << 2) + 0xfe332000)
+#define AED_ND_CZ_THD1 ((0x005c << 2) + 0xfe332000)
+#define AED_ND_COND_CNTL ((0x005d << 2) + 0xfe332000)
+#define AED_ND_RELEASE_COEF0 ((0x005e << 2) + 0xfe332000)
+#define AED_ND_RELEASE_COEF1 ((0x005f << 2) + 0xfe332000)
+#define AED_ND_ATTACK_COEF0 ((0x0060 << 2) + 0xfe332000)
+#define AED_ND_ATTACK_COEF1 ((0x0061 << 2) + 0xfe332000)
+#define AED_ND_CNTL ((0x0062 << 2) + 0xfe332000)
+#define AED_MIX0_LL ((0x0063 << 2) + 0xfe332000)
+#define AED_MIX0_RL ((0x0064 << 2) + 0xfe332000)
+#define AED_MIX0_LR ((0x0065 << 2) + 0xfe332000)
+#define AED_MIX0_RR ((0x0066 << 2) + 0xfe332000)
+#define AED_CLIP_THD ((0x0067 << 2) + 0xfe332000)
+#define AED_CH1_ND_SUM_OUT ((0x0068 << 2) + 0xfe332000)
+#define AED_CH2_ND_SUM_OUT ((0x0069 << 2) + 0xfe332000)
+#define AED_CH1_ND_CZ_OUT ((0x006a << 2) + 0xfe332000)
+#define AED_CH2_ND_CZ_OUT ((0x006b << 2) + 0xfe332000)
+#define AED_NOISE_STATUS ((0x006c << 2) + 0xfe332000)
+#define AED_POW_CURRENT_S0 ((0x006d << 2) + 0xfe332000)
+#define AED_POW_CURRENT_S1 ((0x006e << 2) + 0xfe332000)
+#define AED_POW_CURRENT_S2 ((0x006f << 2) + 0xfe332000)
+#define AED_POW_OUT0 ((0x0070 << 2) + 0xfe332000)
+#define AED_POW_OUT1 ((0x0071 << 2) + 0xfe332000)
+#define AED_POW_OUT2 ((0x0072 << 2) + 0xfe332000)
+#define AED_POW_ADJ_INDEX0 ((0x0073 << 2) + 0xfe332000)
+#define AED_POW_ADJ_INDEX1 ((0x0074 << 2) + 0xfe332000)
+#define AED_POW_ADJ_INDEX2 ((0x0075 << 2) + 0xfe332000)
+#define AED_DRC_GAIN_INDEX0 ((0x0076 << 2) + 0xfe332000)
+#define AED_DRC_GAIN_INDEX1 ((0x0077 << 2) + 0xfe332000)
+#define AED_DRC_GAIN_INDEX2 ((0x0078 << 2) + 0xfe332000)
+#define AED_CH1_VOLUME_STATE ((0x0079 << 2) + 0xfe332000)
+#define AED_CH2_VOLUME_STATE ((0x007a << 2) + 0xfe332000)
+#define AED_CH1_VOLUME_GAIN ((0x007b << 2) + 0xfe332000)
+#define AED_CH2_VOLUME_GAIN ((0x007c << 2) + 0xfe332000)
+#define AED_FULL_POW_CURRENT ((0x007d << 2) + 0xfe332000)
+#define AED_FULL_POW_OUT ((0x007e << 2) + 0xfe332000)
+#define AED_FULL_POW_ADJ ((0x007f << 2) + 0xfe332000)
+#define AED_FULL_DRC_GAIN ((0x0080 << 2) + 0xfe332000)
+#define AED_MASTER_VOLUME_STATE ((0x0081 << 2) + 0xfe332000)
+#define AED_MASTER_VOLUME_GAIN ((0x0082 << 2) + 0xfe332000)
+#define AED_TOP_CTL0 ((0x0083 << 2) + 0xfe332000)
+#define AED_TOP_CTL1 ((0x0084 << 2) + 0xfe332000)
+#define AED_TOP_CTL2 ((0x0085 << 2) + 0xfe332000)
+#define AED_TOP_ST0 ((0x0086 << 2) + 0xfe332000)
+#define AED_TOP_ST1 ((0x0087 << 2) + 0xfe332000)
+//`define AED_EQDRC_DYNAMIC_CNTL 10'h90
+//`define AED_COEF_RAM_CNTL_B 10'h91
+//`define AED_COEF_RAM_DATA_B 10'h92
+//`define AED_DRC_RMS_COEF0_B 10'h93
+//`define AED_DRC_RMS_COEF1_B 10'h94
+//`define AED_DRC_THD0_B 10'h95
+//`define AED_DRC_THD1_B 10'h96
+//`define AED_DRC_THD2_B 10'h97
+//`define AED_DRC_THD3_B 10'h98
+//`define AED_DRC_THD4_B 10'h99
+//`define AED_DRC_K0_B 10'h9a
+//`define AED_DRC_K1_B 10'h9b
+//`define AED_DRC_K2_B 10'h9c
+//`define AED_DRC_K3_B 10'h9d
+//`define AED_DRC_K4_B 10'h9e
+//`define AED_DRC_K5_B 10'h9f
+//`define AED_DRC_THD_OUT0_B 10'ha0
+//`define AED_DRC_THD_OUT1_B 10'ha1
+//`define AED_DRC_THD_OUT2_B 10'ha2
+//`define AED_DRC_THD_OUT3_B 10'ha3
+//`define AED_DRC_OFFSET_B 10'ha4
+//`define AED_DRC_RELEASE_COEF00_B 10'ha5
+//`define AED_DRC_RELEASE_COEF01_B 10'ha6
+//`define AED_DRC_RELEASE_COEF10_B 10'ha7
+//`define AED_DRC_RELEASE_COEF11_B 10'ha8
+//`define AED_DRC_RELEASE_COEF20_B 10'ha9
+//`define AED_DRC_RELEASE_COEF21_B 10'haa
+//`define AED_DRC_RELEASE_COEF30_B 10'hab
+//`define AED_DRC_RELEASE_COEF31_B 10'hac
+//`define AED_DRC_RELEASE_COEF40_B 10'had
+//`define AED_DRC_RELEASE_COEF41_B 10'hae
+//`define AED_DRC_RELEASE_COEF50_B 10'haf
+//`define AED_DRC_RELEASE_COEF51_B 10'hb0
+//`define AED_DRC_ATTACK_COEF00_B 10'hb1
+//`define AED_DRC_ATTACK_COEF01_B 10'hb2
+//`define AED_DRC_ATTACK_COEF10_B 10'hb3
+//`define AED_DRC_ATTACK_COEF11_B 10'hb4
+//`define AED_DRC_ATTACK_COEF20_B 10'hb5
+//`define AED_DRC_ATTACK_COEF21_B 10'hb6
+//`define AED_DRC_ATTACK_COEF30_B 10'hb7
+//`define AED_DRC_ATTACK_COEF31_B 10'hb8
+//`define AED_DRC_ATTACK_COEF40_B 10'hb9
+//`define AED_DRC_ATTACK_COEF41_B 10'hba
+//`define AED_DRC_ATTACK_COEF50_B 10'hbb
+//`define AED_DRC_ATTACK_COEF51_B 10'hbc
+//`define AED_MDRC_RMS_COEF00_B 10'hbd
+//`define AED_MDRC_RMS_COEF01_B 10'hbe
+//`define AED_MDRC_RMS_COEF10_B 10'hbf
+//`define AED_MDRC_RMS_COEF11_B 10'hc0
+//`define AED_MDRC_RMS_COEF20_B 10'hc1
+//`define AED_MDRC_RMS_COEF21_B 10'hc2
+//`define AED_MDRC_RELEASE_COEF00_B 10'hc3
+//`define AED_MDRC_RELEASE_COEF01_B 10'hc4
+//`define AED_MDRC_RELEASE_COEF10_B 10'hc5
+//`define AED_MDRC_RELEASE_COEF11_B 10'hc6
+//`define AED_MDRC_RELEASE_COEF20_B 10'hc7
+//`define AED_MDRC_RELEASE_COEF21_B 10'hc8
+//`define AED_MDRC_ATTACK_COEF00_B 10'hc9
+//`define AED_MDRC_ATTACK_COEF01_B 10'hca
+//`define AED_MDRC_ATTACK_COEF10_B 10'hcb
+//`define AED_MDRC_ATTACK_COEF11_B 10'hcc
+//`define AED_MDRC_ATTACK_COEF20_B 10'hcd
+//`define AED_MDRC_ATTACK_COEF21_B 10'hce
+//`define AED_MDRC_THD0_B 10'hcf
+//`define AED_MDRC_THD1_B 10'hd0
+//`define AED_MDRC_THD2_B 10'hd1
+//`define AED_MDRC_K0_B 10'hd2
+//`define AED_MDRC_K1_B 10'hd3
+//`define AED_MDRC_K2_B 10'hd4
+//`define AED_MDRC_OFFSET0_B 10'hd5
+//`define AED_MDRC_OFFSET1_B 10'hd6
+//`define AED_MDRC_OFFSET2_B 10'hd7
+//`define AED_MDRC_LOW_GAIN_B 10'hd8
+//`define AED_MDRC_MID_GAIN_B 10'hd9
+//`define AED_MDRC_HIGH_GAIN_B 10'hda
+//`define AED_DRC_CNTL_B 10'hdb
+//`define AED_DRC_LOOPBACK_CNTL_B 10'hdc
+//`define AED_MDRC_CNTL_B 10'hdd
+//`define AED_STATUS_REG 10'hde
+//========================================================================
+// AUDIO locker - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe331400
+// -----------------------------------------------
+#define AUD_LOCK_EN ((0x0000 << 2) + 0xfe331400)
+#define AUD_LOCK_SW_RESET ((0x0001 << 2) + 0xfe331400)
+#define AUD_LOCK_SW_LATCH ((0x0002 << 2) + 0xfe331400)
+#define AUD_LOCK_HW_LATCH ((0x0003 << 2) + 0xfe331400)
+#define AUD_LOCK_REFCLK_SRC ((0x0004 << 2) + 0xfe331400)
+#define AUD_LOCK_REFCLK_LAT_INT ((0x0005 << 2) + 0xfe331400)
+#define AUD_LOCK_IMCLK_LAT_INT ((0x0006 << 2) + 0xfe331400)
+#define AUD_LOCK_OMCLK_LAT_INT ((0x0007 << 2) + 0xfe331400)
+#define AUD_LOCK_REFCLK_DS_INT ((0x0008 << 2) + 0xfe331400)
+#define AUD_LOCK_IMCLK_DS_INT ((0x0009 << 2) + 0xfe331400)
+#define AUD_LOCK_OMCLK_DS_INT ((0x000a << 2) + 0xfe331400)
+#define AUD_LOCK_INT_CLR ((0x000b << 2) + 0xfe331400)
+#define AUD_LOCK_GCLK_CTRL ((0x000c << 2) + 0xfe331400)
+#define AUD_LOCK_INT_CTRL ((0x000d << 2) + 0xfe331400)
+#define RO_REF2IMCLK_CNT_L ((0x0010 << 2) + 0xfe331400)
+#define RO_REF2IMCLK_CNT_H ((0x0011 << 2) + 0xfe331400)
+#define RO_REF2OMCLK_CNT_L ((0x0012 << 2) + 0xfe331400)
+#define RO_REF2OMCLK_CNT_H ((0x0013 << 2) + 0xfe331400)
+#define RO_IMCLK2REF_CNT_L ((0x0014 << 2) + 0xfe331400)
+#define RO_IMCLK2REF_CNT_H ((0x0015 << 2) + 0xfe331400)
+#define RO_OMCLK2REF_CNT_L ((0x0016 << 2) + 0xfe331400)
+#define RO_OMCLK2REF_CNT_H ((0x0017 << 2) + 0xfe331400)
+#define RO_REFCLK_PKG_CNT ((0x0018 << 2) + 0xfe331400)
+#define RO_IMCLK_PKG_CNT ((0x0019 << 2) + 0xfe331400)
+#define RO_OMCLK_PKG_CNT ((0x001a << 2) + 0xfe331400)
+#define RO_AUD_LOCK_INT_STATUS ((0x001b << 2) + 0xfe331400)
+//========================================================================
+// AUDIO lockerB - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe334400
+// -----------------------------------------------
+#define AUD_LOCKB_EN ((0x0000 << 2) + 0xfe334400)
+#define AUD_LOCKB_SW_RESET ((0x0001 << 2) + 0xfe334400)
+#define AUD_LOCKB_SW_LATCH ((0x0002 << 2) + 0xfe334400)
+#define AUD_LOCKB_HW_LATCH ((0x0003 << 2) + 0xfe334400)
+#define AUD_LOCKB_REFCLK_SRC ((0x0004 << 2) + 0xfe334400)
+#define AUD_LOCKB_REFCLK_LAT_INT ((0x0005 << 2) + 0xfe334400)
+#define AUD_LOCKB_IMCLK_LAT_INT ((0x0006 << 2) + 0xfe334400)
+#define AUD_LOCKB_OMCLK_LAT_INT ((0x0007 << 2) + 0xfe334400)
+#define AUD_LOCKB_REFCLK_DS_INT ((0x0008 << 2) + 0xfe334400)
+#define AUD_LOCKB_IMCLK_DS_INT ((0x0009 << 2) + 0xfe334400)
+#define AUD_LOCKB_OMCLK_DS_INT ((0x000a << 2) + 0xfe334400)
+#define AUD_LOCKB_INT_CLR ((0x000b << 2) + 0xfe334400)
+#define AUD_LOCKB_GCLK_CTRL ((0x000c << 2) + 0xfe334400)
+#define AUD_LOCKB_INT_CTRL ((0x000d << 2) + 0xfe334400)
+#define ROB_REF2IMCLK_CNT_L ((0x0010 << 2) + 0xfe334400)
+#define ROB_REF2IMCLK_CNT_H ((0x0011 << 2) + 0xfe334400)
+#define ROB_REF2OMCLK_CNT_L ((0x0012 << 2) + 0xfe334400)
+#define ROB_REF2OMCLK_CNT_H ((0x0013 << 2) + 0xfe334400)
+#define ROB_IMCLK2REF_CNT_L ((0x0014 << 2) + 0xfe334400)
+#define ROB_IMCLK2REF_CNT_H ((0x0015 << 2) + 0xfe334400)
+#define ROB_OMCLK2REF_CNT_L ((0x0016 << 2) + 0xfe334400)
+#define ROB_OMCLK2REF_CNT_H ((0x0017 << 2) + 0xfe334400)
+#define ROB_REFCLK_PKG_CNT ((0x0018 << 2) + 0xfe334400)
+#define ROB_IMCLK_PKG_CNT ((0x0019 << 2) + 0xfe334400)
+#define ROB_OMCLK_PKG_CNT ((0x001a << 2) + 0xfe334400)
+#define ROB_AUD_LOCK_INT_STATUS ((0x001b << 2) + 0xfe334400)
+//========================================================================
+// AUDIO VAD - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe331800
+// -----------------------------------------------
+//
+// Reading file: VAD_REG.h
+//
+#define VAD_TOP_CTRL0 ((0x0000 << 2) + 0xfe331800)
+#define VAD_TOP_CTRL1 ((0x0001 << 2) + 0xfe331800)
+#define VAD_TOP_CTRL2 ((0x0002 << 2) + 0xfe331800)
+#define VAD_FIR_CTRL ((0x0003 << 2) + 0xfe331800)
+#define VAD_FIR_EMP ((0x0004 << 2) + 0xfe331800)
+#define VAD_FIR_COEF0 ((0x0005 << 2) + 0xfe331800)
+#define VAD_FIR_COEF1 ((0x0006 << 2) + 0xfe331800)
+#define VAD_FIR_COEF2 ((0x0007 << 2) + 0xfe331800)
+#define VAD_FIR_COEF3 ((0x0008 << 2) + 0xfe331800)
+#define VAD_FIR_COEF4 ((0x0009 << 2) + 0xfe331800)
+#define VAD_FIR_COEF5 ((0x000a << 2) + 0xfe331800)
+#define VAD_FIR_COEF6 ((0x000b << 2) + 0xfe331800)
+#define VAD_FIR_COEF7 ((0x000c << 2) + 0xfe331800)
+#define VAD_FIR_COEF8 ((0x000d << 2) + 0xfe331800)
+#define VAD_FIR_COEF9 ((0x000e << 2) + 0xfe331800)
+#define VAD_FIR_COEF10 ((0x000f << 2) + 0xfe331800)
+#define VAD_FIR_COEF11 ((0x0010 << 2) + 0xfe331800)
+#define VAD_FIR_COEF12 ((0x0011 << 2) + 0xfe331800)
+#define VAD_FRAME_CTRL0 ((0x0012 << 2) + 0xfe331800)
+#define VAD_FRAME_CTRL1 ((0x0013 << 2) + 0xfe331800)
+#define VAD_FRAME_CTRL2 ((0x0014 << 2) + 0xfe331800)
+#define VAD_CEP_CTRL0 ((0x0015 << 2) + 0xfe331800)
+#define VAD_CEP_CTRL1 ((0x0016 << 2) + 0xfe331800)
+#define VAD_CEP_CTRL2 ((0x0017 << 2) + 0xfe331800)
+#define VAD_CEP_CTRL3 ((0x0018 << 2) + 0xfe331800)
+#define VAD_CEP_CTRL4 ((0x0019 << 2) + 0xfe331800)
+#define VAD_CEP_CTRL5 ((0x001a << 2) + 0xfe331800)
+#define VAD_DEC_CTRL ((0x001b << 2) + 0xfe331800)
+#define VAD_TOP_STS0 ((0x001c << 2) + 0xfe331800)
+#define VAD_TOP_STS1 ((0x001d << 2) + 0xfe331800)
+#define VAD_TOP_STS2 ((0x001e << 2) + 0xfe331800)
+#define VAD_FIR_STS0 ((0x001f << 2) + 0xfe331800)
+#define VAD_FIR_STS1 ((0x0020 << 2) + 0xfe331800)
+#define VAD_POW_STS0 ((0x0021 << 2) + 0xfe331800)
+#define VAD_POW_STS1 ((0x0022 << 2) + 0xfe331800)
+#define VAD_POW_STS2 ((0x0023 << 2) + 0xfe331800)
+#define VAD_FFT_STS0 ((0x0024 << 2) + 0xfe331800)
+#define VAD_FFT_STS1 ((0x0025 << 2) + 0xfe331800)
+#define VAD_SPE_STS0 ((0x0026 << 2) + 0xfe331800)
+#define VAD_SPE_STS1 ((0x0027 << 2) + 0xfe331800)
+#define VAD_SPE_STS2 ((0x0028 << 2) + 0xfe331800)
+#define VAD_SPE_STS3 ((0x0029 << 2) + 0xfe331800)
+#define VAD_DEC_STS0 ((0x002a << 2) + 0xfe331800)
+#define VAD_DEC_STS1 ((0x002b << 2) + 0xfe331800)
+#define VAD_LUT_CTRL ((0x002c << 2) + 0xfe331800)
+#define VAD_LUT_WR ((0x002d << 2) + 0xfe331800)
+#define VAD_LUT_RD ((0x002e << 2) + 0xfe331800)
+#define VAD_IN_SEL0 ((0x002f << 2) + 0xfe331800)
+#define VAD_IN_SEL1 ((0x0030 << 2) + 0xfe331800)
+#define VAD_TO_DDR ((0x0031 << 2) + 0xfe331800)
+#define VAD_SYNC_CTRL0 ((0x0032 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID0 ((0x0033 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID1 ((0x0034 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID2 ((0x0035 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID3 ((0x0036 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID4 ((0x0037 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID5 ((0x0038 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID6 ((0x0039 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID7 ((0x003a << 2) + 0xfe331800)
+//
+// Closing file: VAD_REG.h
+//
+//========================================================================
+// AUDIO RESAMPLEA - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe331c00
+// -----------------------------------------------
+//
+// Reading file: RESAMPLE.h
+//
+#define AUDIO_RSAMP_CTRL0 ((0x0000 << 2) + 0xfe331c00)
+//Bit 31:3 reserved
+//Bit 2 reg_lock_rst //unsigned , default =0;
+//Bit 1 reg_rsamp_rst //unsigned , default =0;
+//Bit 0 reg_sw_rst //unsigned , default =0;
+#define AUDIO_RSAMP_CTRL1 ((0x0001 << 2) + 0xfe331c00)
+//Bit 31:27 reg_in_lsb //unsigned , default =0;
+//Bit 26 reg_watchdog_en //unsigned , default =0;
+//Bit 25 reg_rsamp_rst_sel //unsigned , default =0;
+//Bit 24 reg_module_bypas //unsigned , default =0;
+//Bit 23:18 reg_gclk_ctrl //unsigned , default =0;
+//Bit 17:13 reg_in_msb //unsigned , default =23;
+//Bit 12 reg_output_en //unsigned , default =0;
+//Bit 11 reg_rsamp_en //unsigned , default =0;
+//Bit 10 reg_filt_en //unsigned , default =0;
+//Bit 9 reg_post_en //unsigned , default =0;
+//Bit 8 reg_inp_mux_mode //unsigned , default =0;
+//Bit 7:5 reserved //unsigned , default =2;
+//Bit 4:0 reg_inp_mux //unsigned , default =0;
+#define AUDIO_RSAMP_CTRL2 ((0x0002 << 2) + 0xfe331c00)
+//Bit 31:30 reserved //unsigned , default =0;
+//Bit 29:24 reg_chx_size //unsigned , default =2;
+//Bit 23:18 reserved //unsigned , default =0;
+//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4
+//Bit 15:8 reg_filt_tap //unsigned , default =63;
+//Bit 7:0 reg_intp_tap //unsigned , default =63;
+#define AUDIO_RSAMP_PHSINIT ((0x0003 << 2) + 0xfe331c00)
+//Bit 31:28 reserved //unsigned , default = 0;
+//Bit 27:0 reg_init_phs //unsigned , default = 0;
+#define AUDIO_RSAMP_PHSSTEP ((0x0004 << 2) + 0xfe331c00)
+//Bit 31 reserved //unsigned , default = 0;
+//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000
+#define AUDIO_RSAMP_SHIFT ((0x0005 << 2) + 0xfe331c00)
+//Bit 31:24 reg_rsft_iir //unsigned , default = 23;
+//Bit 23:16 reg_rsft_blnd //unsigned , default = 21;
+//Bit 15:8 reg_rsft_sinc //unsigned , default = 31;
+//Bit 7:0 reg_rsft_aa //unsigned , default = 31;
+#define AUDIO_RSAMP_ADJ_CTRL0 ((0x0006 << 2) + 0xfe331c00)
+//Bit 31:7 reserved //unsigned
+//Bit 6 reg_lock_vld_sel //unsigned , default = 0;
+//Bit 5 reg_loop_dif_clr_en //unsigned , default = 0;
+//Bit 4 reg_aout_force_en //unsigned , default = 0;
+//Bit 3 reserved //unsigned
+//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0;
+//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0;
+//Bit 0 reg_rsamp_adj_en //unsigned , default = 0;
+#define AUDIO_RSAMP_ADJ_CTRL1 ((0x0007 << 2) + 0xfe331c00)
+//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8;
+//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768;
+#define AUDIO_RSAMP_ADJ_SFT ((0x0008 << 2) + 0xfe331c00)
+//Bit 31:30 reserved //unsigned , default = 0;
+//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0;
+//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9;
+//Bit 23:21 reserved //unsigned , default = 0;
+//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1;
+//Bit 15:13 reserved //unsigned , default = 0;
+//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6;
+//Bit 7:6 reserved //unsigned , default = 0;
+//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12;
+#define AUDIO_RSAMP_ADJ_IDET_LEN ((0x0009 << 2) + 0xfe331c00)
+//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000;
+#define AUDIO_RSAMP_ADJ_FORCE ((0x000a << 2) + 0xfe331c00)
+//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8;
+#define AUDIO_RSAMP_ADJ_KI_FORCE ((0x000b << 2) + 0xfe331c00)
+//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0;
+#define AUDIO_RSAMP_WATCHDOG_THRD ((0x000c << 2) + 0xfe331c00)
+//Bit 31:0 reg_watchdog_thrd //signed , default = 32'h1000;
+#define AUDIO_RSAMP_DBG_INFO ((0x000d << 2) + 0xfe331c00)
+//Bit 31:16 reg_aout_force_hi //unsigned , default = 0;
+//Bit 15:7 reserved //unsigned , default = 0;
+//Bit 6 reg_rsamp_dbgcnt_clr //unsigned , default = 0;
+//Bit 5 reg_rsamp_dbgcnt_vldsel //unsigned , default = 0;
+//Bit 4 reg_rsamp_dbgcnt_en //unsigned , default = 0;
+//Bit 3 reserved //unsigned , default = 0;
+//Bit 2:0 reg_watchdog_rstsel //unsigned , default = 4;
+#define AUDIO_RSAMP_AOUT_FORCE ((0x000e << 2) + 0xfe331c00)
+//Bit 31:0 reg_aout_force_lo //unsigned , default = 0;
+#define AUDIO_RSAMP_IRQ_CTRL ((0x000f << 2) + 0xfe331c00)
+//Bit 31:16 reg_irq_thrd //unsigned , default = 0;
+//Bit 15:12 reserved //unsigned , default = 0;
+//Bit 11:8 reg_irq_sel //unsigned , default = 0;
+//Bit 7:4 reg_irq_clr //unsigned , default = 0;
+//Bit 3:0 reg_irq_en //unsigned , default = 0;
+#define AUDIO_RSAMP_RO_STATUS ((0x0010 << 2) + 0xfe331c00)
+//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]}
+#define AUDIO_RSAMP_RO_ADJ_FREQ ((0x0011 << 2) + 0xfe331c00)
+//Bit 31:0 ro_rsamp_adj_freq
+#define AUDIO_RSAMP_RO_ADJ_DIFF_BAK ((0x0012 << 2) + 0xfe331c00)
+//Bit 31:0 ro_det_diff_bak
+#define AUDIO_RSAMP_RO_ADJ_DIFF_DLT ((0x0013 << 2) + 0xfe331c00)
+//Bit 31:0 ro_det_diff_dlt
+#define AUDIO_RSAMP_RO_ADJ_PHS_ERR ((0x0014 << 2) + 0xfe331c00)
+//Bit 31:0 ro_det_phase_err
+#define AUDIO_RSAMP_RO_ADJ_KI_OUT ((0x0015 << 2) + 0xfe331c00)
+//Bit 31:0 ro_rsamp_ki_out
+#define AUDIO_RSAMP_RO_IN_CNT ((0x0016 << 2) + 0xfe331c00)
+//Bit 31:0 ro_rsamp_in_cnt
+#define AUDIO_RSAMP_RO_OUT_CNT ((0x0017 << 2) + 0xfe331c00)
+//Bit 31:0 ro_rsamp_out_cnt
+#define AUDIO_RSAMP_RO_ADJ_PHS_ERR_VAR ((0x0018 << 2) + 0xfe331c00)
+//Bit 31:0 ro_det_phase_err_var
+#define AUDIO_RSAMP_POST_COEF0 ((0x0020 << 2) + 0xfe331c00)
+//Bit 31:0 reg_post_coef0 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF1 ((0x0021 << 2) + 0xfe331c00)
+//Bit 31:0 reg_post_coef1 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF2 ((0x0022 << 2) + 0xfe331c00)
+//Bit 31:0 reg_post_coef2 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF3 ((0x0023 << 2) + 0xfe331c00)
+//Bit 31:0 reg_post_coef3 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF4 ((0x0024 << 2) + 0xfe331c00)
+//Bit 31:0 reg_post_coef4 //signed , default = 0;
+#define AUDIO_RSAMP_AA_COEF_ADDR ((0x0030 << 2) + 0xfe331c00)
+//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0;
+#define AUDIO_RSAMP_AA_COEF_DATA ((0x0031 << 2) + 0xfe331c00)
+//Bit 31:0 reg_aa_coef_data //signed , default = 0;
+#define AUDIO_RSAMP_SINC_COEF_ADDR ((0x0040 << 2) + 0xfe331c00)
+//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0;
+#define AUDIO_RSAMP_SINC_COEF_DATA ((0x0041 << 2) + 0xfe331c00)
+//Bit 31:0 reg_sinc_coef_data //signed , default = 0;
+//
+// Closing file: RESAMPLE.h
+//
+//========================================================================
+// AUDIO EARCTX_CMDC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe333000
+// -----------------------------------------------
+//
+// Reading file: earc_tx_cmdc.h
+//
+#define EARC_TX_CMDC_TOP_CTRL0 ((0x0030 << 2) + 0xfe333000)
+//Bit 31 , idle2_int unsigned, default = 0, 1: enable
+//Bit 30 , idle1_int unsigned, default = 0, 1: enable
+//Bit 29 , disc2_int unsigned, default = 0, 1: enable
+//Bit 28 , disc1_int unsigned, default = 0, 1: enable
+//Bit 27 , earc_int unsigned, default = 0, 1: enable
+//Bit 26 , hb_status_int unsigned, default = 0, 1: enable
+//Bit 25 , losthb_int unsigned, default = 0, 1: enable
+//Bit 24 , timeout_int unsigned, default = 0, 1: enable
+//Bit 23 , status_ch_int unsigned, default = 0, 1: enable
+//Bit 22 , int_recv_finished unsigned, default = 0, 1: enable
+//Bit 21 , int_rdata unsigned, default = 0, 1: enable
+//Bit 20 , int_recv_nack unsigned, default = 0, 1: enable
+//Bit 19 , int_recv_norsp unsigned, default = 0, 1: enable
+//Bit 18 , int_recv_unexp unsigned, default = 0, 1: enable
+//Bit 17 , int_recv_data unsigned, default = 0, 1: enable
+//Bit 16 , int_recv_ack unsigned, default = 0, 1: enable
+//Bit 15 , int_recv_ecc_err unsigned, default = 0, 1: enable
+//Bit 14 , int_recv_packet unsigned, default = 0, 1: enable
+//Bit 13:0 , reserved
+#define EARC_TX_CMDC_TOP_CTRL1 ((0x0031 << 2) + 0xfe333000)
+//Bit 31:0, cmdc_top_ctrl1 //unsigned, RW, default = 0,
+#define EARC_TX_CMDC_TOP_CTRL2 ((0x0032 << 2) + 0xfe333000)
+//Bit 31 , reset_idle2_int unsigned, default = 0, 1: enable
+//Bit 30 , reset_idle1_int unsigned, default = 0, 1: enable
+//Bit 29 , reset_disc2_int unsigned, default = 0, 1: enable
+//Bit 28 , reset_disc1_int unsigned, default = 0, 1: enable
+//Bit 27 , reset_earc_int unsigned, default = 0, 1: enable
+//Bit 26 , reset_hb_status_int unsigned, default = 0, 1: enable
+//Bit 25 , reset_losthb_int unsigned, default = 0, 1: enable
+//Bit 24 , reset_timeout_int unsigned, default = 0, 1: enable
+//Bit 23 , reset_status_ch_int unsigned, default = 0, 1: enable
+//Bit 22 , reset_int_recv_finished unsigned, default = 0, 1: enable
+//Bit 21 , reset_int_rdata unsigned, default = 0, 1: enable
+//Bit 20 , reset_int_recv_nack unsigned, default = 0, 1: enable
+//Bit 19 , reset_int_recv_norsp unsigned, default = 0, 1: enable
+//Bit 18 , reset_int_recv_unexp unsigned, default = 0, 1: enable
+//Bit 17 , reset_int_recv_data unsigned, default = 0, 1: enable
+//Bit 16 , reset_int_recv_ack unsigned, default = 0, 1: enable
+//Bit 15 , reset_int_recv_ecc_err unsigned, default = 0, 1: enable
+//Bit 14 , reset_int_recv_packet unsigned, default = 0, 1: enable
+//Bit 13:0 , reserved
+#define EARC_TX_CMDC_TIMER_CTRL0 ((0x0033 << 2) + 0xfe333000)
+//Bit 31:0, cmdc_timer_ctrl0 //unsigned, RW, default = 0,
+#define EARC_TX_CMDC_TIMER_CTRL1 ((0x0034 << 2) + 0xfe333000)
+//Bit 31:0, cmdc_timer_ctrl1 //unsigned, RW, default = 0,
+#define EARC_TX_CMDC_TIMER_CTRL2 ((0x0035 << 2) + 0xfe333000)
+//Bit 31:0, cmdc_timer_ctrl2 //unsigned, RW, default = 0,
+#define EARC_TX_CMDC_TIMER_CTRL3 ((0x0036 << 2) + 0xfe333000)
+//Bit 31:0, cmdc_timer_ctrl3 //unsigned, RW, default = 0,
+#define EARC_TX_CMDC_VSM_CTRL0 ((0x0037 << 2) + 0xfe333000)
+//Bit 31, sw_state_update unsigned, default = 0, XX
+//Bit 30:28, sw_state unsigned, default = 0, XX
+//Bit 27, arc_initiated unsigned, default = 0, XX
+//Bit 26, arc_terminated unsigned, default = 0, XX
+//Bit 25, arc_enable unsigned, default = 1, XX
+//Bit 24, man_hpd unsigned, default = 0, XX
+//Bit 23:22, hpd_sel unsigned, default = 0, XX
+//Bit 21:20, hpd_sel_earc unsigned, default = 0, XX
+//Bit 19, comma_cnt_rst unsigned, default = 0, XX
+//Bit 18, timeout_status_rst unsigned, default = 0, XX
+//Bit 17, losthb_status_rst unsigned, default = 0, XX
+//Bit 16, force_rst unsigned, default = 0, XX
+//Bit 15, auto_state_en unsigned, default = 0, XX
+//Bit 14, cmdc_state_en unsigned, default = 0, XX
+//Bit 13, noack_repeat_en unsigned, default = 0, XX
+//Bit 12:0, reserved
+#define EARC_TX_CMDC_VSM_CTRL1 ((0x0038 << 2) + 0xfe333000)
+//Bit 31:9, reserved
+//Bit 8, cntl_hpd_sel unsigned, default = 0, 0:sel hd_hpd,1:sel hdmirx_hpd
+//Bit 7:0, comma_cnt_th unsigned, default = 0, should bigger than 3 and small than 10
+#define EARC_TX_CMDC_VSM_CTRL2 ((0x0039 << 2) + 0xfe333000)
+//Bit 31:12, max_count_th unsigned, default = 0, disc1 hpd_val timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, disc1 hpd_val timing
+//Bit 6:4, time_sel unsigned, default = 0, disc1 hpd_val timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, disc1 hpd_val timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, disc1 hpd_val timing
+#define EARC_TX_CMDC_VSM_CTRL3 ((0x003a << 2) + 0xfe333000)
+//Bit 31:12, max_count_th unsigned, default = 0, disc2 heartbeat act timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, disc2 heartbeat act timing
+//Bit 6:4, time_sel unsigned, default = 0, disc2 heartbeat act timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, disc2 heartbeat act timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, disc2 heartbeat act timing
+#define EARC_TX_CMDC_VSM_CTRL4 ((0x003b << 2) + 0xfe333000)
+//Bit 31:12, max_count_th unsigned, default = 0, in disc2, no heartbeat ack timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, in disc2, no heartbeat ack timing
+//Bit 6:4, time_sel unsigned, default = 0, in disc2, no heartbeat ack timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, in disc2, no heartbeat ack timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, in disc2, no heartbeat ack timing
+#define EARC_TX_CMDC_VSM_CTRL5 ((0x003c << 2) + 0xfe333000)
+//Bit 31:12, max_count_th unsigned, default = 0, in disc1 and disc2 timing out
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, in disc1 and disc2 timing out
+//Bit 6:4, time_sel unsigned, default = 0, in disc1 and disc2 timing out
+//Bit 3:2, soft_rst_sel unsigned, default = 0, in disc1 and disc2 timing out
+//Bit 1:0, enable_ctrl unsigned, default = 0, in disc1 and disc2 timing out
+#define EARC_TX_CMDC_VSM_CTRL6 ((0x003d << 2) + 0xfe333000)
+//Bit 31:12, max_count_th unsigned, default = 0, in earc heartbeat act timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, in earc heartbeat act timing
+//Bit 6:4, time_sel unsigned, default = 0, in earc heartbeat act timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, in earc heartbeat act timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, in earc heartbeat act timing
+#define EARC_TX_CMDC_VSM_CTRL7 ((0x003e << 2) + 0xfe333000)
+//Bit 31:16, reserved
+//Bit 15:8, status_soft_val unsigned, default = 0, in earc heartbeat det timing
+//Bit 7, reg_soft_rst unsigned, default = 0, in earc heartbeat det timing
+//Bit 6, status_rst unsigned, default = 0, in earc heartbeat det timing
+//Bit 5:4, reserved
+//Bit 3:2, soft_rst_sel unsigned, default = 0, in earc heartbeat det timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, in earc heartbeat det timing
+#define EARC_TX_CMDC_VSM_CTRL8 ((0x003f << 2) + 0xfe333000)
+//Bit 31:0, cmdc_vsm_ctrl8 //unsigned, RW, default = 0,
+#define EARC_TX_CMDC_VSM_CTRL9 ((0x0041 << 2) + 0xfe333000)
+//Bit 31:0, cmdc_vsm_ctrl9 //unsigned, RW, default = 0
+#define EARC_TX_CMDC_SENDER_CTRL0 ((0x0042 << 2) + 0xfe333000)
+//Bit 31:2, sender_ctrl0 unsigned, default = 0,
+//Bit 1, hb_chg_conf_auto unsigned, default = 1,
+//Bit 0, hb_chg_auto unsigned, default = 0,
+#define EARC_TX_CMDC_PACKET_CTRL0 ((0x0043 << 2) + 0xfe333000)
+//Bit 31, packet_mode_enable unsigned, default = 0, packet control
+//Bit 30, free_enable unsigned, default = 0, packet control
+//Bit 29, soft_rst unsigned, default = 0, packet control
+//Bit 28:24, tx_ready_threshold unsigned, default = 0, packet control
+//Bit 23:20, reserved
+//Bit 19:8, send_pre_threshold unsigned, default = 0, packet control
+//Bit 7:6, reserved
+//Bit 5, state_auto_en unsigned, default = 0, packet control
+//Bit 4, sw_state_update_en unsigned, default = 0, packet control
+//Bit 3:0, sw_state_value unsigned, default = 0, packet control
+#define EARC_TX_CMDC_PACKET_CTRL1 ((0x0044 << 2) + 0xfe333000)
+//Bit 31, ecc_endian unsigned, default = 0, send
+//Bit 30, pre_start_value unsigned, default = 0, send
+//Bit 29:21, reserved
+//Bit 20:16, post_threshold unsigned, default = 0, send
+//Bit 15:14, reserved
+//Bit 13:8, pre_threshold unsigned, default = 0, XX
+//Bit 7:0, post_flag unsigned, default = 0, XX
+#define EARC_TX_CMDC_PACKET_CTRL2 ((0x0045 << 2) + 0xfe333000)
+//Bit 31:0, pre_flag unsigned, default = 0, XX
+#define EARC_TX_CMDC_PACKET_CTRL3 ((0x0046 << 2) + 0xfe333000)
+//Bit 31, recv_en unsigned, default = 0, XX
+//Bit 30, recv_parity_mask unsigned, default = 0, XX
+//Bit 29, recv_timeout_en unsigned, default = 0, XX
+//Bit 28, bch_ecc_en unsigned, default = 0, xx
+//Bit 27:16, reserved
+//Bit 15:0, recv_timeout_threshold unsigned, default = 0, XX
+#define EARC_TX_CMDC_PACKET_CTRL4 ((0x0047 << 2) + 0xfe333000)
+//Bit 31:20, reserved
+//Bit 19:0, recv_packet_head unsigned, default = 0, XX
+#define EARC_TX_CMDC_PACKET_CTRL5 ((0x0048 << 2) + 0xfe333000)
+//Bit 31:20, reserved
+//Bit 19:0, recv_packet_head_mask unsigned, default = 0, XX
+#define EARC_TX_CMDC_PACKET_CTRL6 ((0x0049 << 2) + 0xfe333000)
+//Bit 31:20, recv_pre_threshold unsigned, default = 0, packet control
+//Bit 19:7, reserved
+//Bit 6, recv_finished_int unsigned, default = 0, XX
+//Bit 5, recv_ecc_err_int unsigned, default = 0, XX
+//Bit 4, recv_ack_int unsigned, default = 0, XX
+//Bit 3, recv_data_int unsigned, default = 0, XX
+//Bit 2, recv_unexp_int unsigned, default = 0, XX
+//Bit 1, recv_norsp_int unsigned, default = 0, XX
+//Bit 0, recv_nack_int unsigned, default = 0, XX
+#define EARC_TX_CMDC_BIPHASE_CTRL0 ((0x004a << 2) + 0xfe333000)
+//Bit 31:24, reserved
+//Bit 23:16, ack delay threshold unsigned, default = 0, xx
+//Bit 15:10, reserved
+//Bit 9, send_ack_en unsigned, default = 0, xx
+//Bit 8, sq_val_en unsigned, default = 0, XX
+//Bit 7, biphase_send_soft_rst unsigned, default = 0, XX
+//Bit 6, comma_soft_rst unsigned, default = 0, XX
+//Bit 5, fifo_rst unsigned, default = 0, XX
+//Bit 4, receiver_no_sender unsigned, default = 0, XX
+//Bit 3, sender_free unsigned, default = 0, XX
+//Bit 2, receiver_send unsigned, default = 0, XX
+//Bit 1, receiver_earc unsigned, default = 0, XX
+//Bit 0, receiver_free unsigned, default = 0, XX
+#define EARC_TX_CMDC_BIPHASE_CTRL1 ((0x004b << 2) + 0xfe333000)
+//Bit 31:16, reserved
+//Bit 15, ack_enable unsigned, default = 0, send
+//Bit 14:8, reserved
+//Bit 7:0, wait_threshold before ack unsigned, default = 0, send
+#define EARC_TX_CMDC_BIPHASE_CTRL2 ((0x004c << 2) + 0xfe333000)
+//Bit 31, comma_detection_enable unsigned, default = 0, comma detection
+//Bit 30, manual_reset_enable unsigned, default = 0, manual reset select, 1: manual
+//Bit 29, manual_reset_value unsigned, default = 0, manual reset control
+//Bit 28:16, reserved
+//Bit 15:0, comma_detection_threshold unsigned, default = 0,
+#define EARC_TX_CMDC_BIPHASE_CTRL3 ((0x004d << 2) + 0xfe333000)
+//Bit 31:0, cmdc_biphase_ctrl3 unsigned, default = 0,
+#define EARC_TX_CMDC_DEVICE_ID_CTRL ((0x004e << 2) + 0xfe333000)
+//Bit 31, apb_write unsigned, default = 0, apb bus wr/read
+//Bit 30, apb_read unsigned, default = 0, apb bus wr/read
+//Bit 29, apb_rw_done unsigned, default = 0, apb bus wr/read
+//Bit 28, apb_rw_reset unsigned, default = 0, apb bus wr/read
+//Bit 27:17, reserved
+//Bit 16, hpb_rst_enable unsigned, default = 1, hpd rst enable
+//Bit 15:8, apb_rwid unsigned, default = 0, apb bus wr/read
+//Bit 7:0, apbrw_start_addr unsigned, default = 0, apb bus wr/read
+#define EARC_TX_CMDC_DEVICE_WDATA ((0x004f << 2) + 0xfe333000)
+//Bit 31:8, reserved
+//Bit 7:0, apb_write_data unsigned, default = 0, apb bus wr/read
+#define EARC_TX_CMDC_DEVICE_RDATA ((0x0050 << 2) + 0xfe333000)
+//Bit 31:8, reserved
+//Bit 7:0, apb_read_data unsigned, default = 0, apb bus wr/read
+#define EARC_TX_CMDC_MASTER_CTRL ((0x0051 << 2) + 0xfe333000)
+//Bit 31, master_cmd_rw unsigned, default = 0, 1 write 0 read
+//Bit 30, master_hb_ignore unsigned, default =0, 0:wait hb issued before pkt cmd, 1: pkt cmd issued immediately
+//Bit 29, master_idle unsigned, default = 0, master status
+//Bit 28, master_cmd_soft_rst unsigned, default= 0,
+//Bit 27:24, hb_cmd_cal_th unsigned, default= 0,
+//Bit 23:16, master_cmd_count unsigned, default = 0, cmd count -1
+//Bit 15:8, master_cmd_id unsigned, default = 0,
+//Bit 7:0, master_cmd_address unsigned, default = 0,
+#define EARC_TX_ANA_CTRL0 ((0x0052 << 2) + 0xfe333000)
+//Bit 31:0, reg_earctx_ana_ctrl0 //unsigned, RW, default = 0,
+#define EARC_TX_ANA_CTRL1 ((0x0053 << 2) + 0xfe333000)
+//Bit 31:0, reg_earctx_ana_ctrl1 //unsigned, RW, default = 0,
+#define EARC_TX_ANA_CTRL2 ((0x0054 << 2) + 0xfe333000)
+//Bit 31:0, reg_earctx_ana_ctrl2 //unsigned, RW, default = 0,
+#define EARC_TX_ANA_CTRL3 ((0x0055 << 2) + 0xfe333000)
+//Bit 31:0, reg_earctx_ana_ctrl3 //unsigned, RW, default = 0,
+#define EARC_TX_ANA_CTRL4 ((0x0056 << 2) + 0xfe333000)
+//Bit 31:0, reg_earctx_ana_ctrl4 //unsigned, RW, default = 0,
+#define EARC_TX_ANA_CTRL5 ((0x0057 << 2) + 0xfe333000)
+//Bit 31:0, reg_earctx_ana_ctrl5 //unsigned, RW, default = 0,
+#define EARC_TX_ANA_STAT0 ((0x0058 << 2) + 0xfe333000)
+//Bit 31:0, ro_ANA_status0 //unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS0 ((0x0059 << 2) + 0xfe333000)
+//Bit 31:0, ro_cmdc_status0 //unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS1 ((0x005a << 2) + 0xfe333000)
+//Bit 31:0, ro_cmdc_status1 ///unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS2 ((0x005b << 2) + 0xfe333000)
+//Bit 31:0, ro_cmdc_status2 ///unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS3 ((0x005c << 2) + 0xfe333000)
+//Bit 31:0, ro_cmdc_status3 ///unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS4 ((0x005d << 2) + 0xfe333000)
+//Bit 31:0, ro_cmdc_status4 ///unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS5 ((0x005e << 2) + 0xfe333000)
+//Bit 31:0, ro_cmdc_status5 ///unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS6 ((0x005f << 2) + 0xfe333000)
+//Bit 31 , ro_idle2_int unsigned, RO, default = 0
+//Bit 30 , ro_idle1_int unsigned, RO, default = 0
+//Bit 29 , ro_disc2_int unsigned, RO, default = 0
+//Bit 28 , ro_disc1_int unsigned, RO, default = 0
+//Bit 27 , ro_earc_int unsigned, RO, default = 0
+//Bit 26 , ro_hb_status_int unsigned, RO, default = 0
+//Bit 25 , ro_losthb_int unsigned, RO, default = 0
+//Bit 24 , ro_timeout_int unsigned, RO, default = 0
+//Bit 23 , ro_status_ch_int unsigned, RO, default = 0
+//Bit 22 , ro_int_recv_finished unsigned, RO, default = 0
+//Bit 21 , ro_int_rdata unsigned, RO, default = 0
+//Bit 20 , ro_int_recv_nack unsigned, RO, default = 0
+//Bit 19 , ro_int_recv_norsp unsigned, RO, default = 0
+//Bit 18 , ro_int_recv_unexp unsigned, RO, default = 0
+//Bit 17 , ro_int_recv_data unsigned, RO, default = 0
+//Bit 16 , ro_int_recv_ack unsigned, RO, default = 0
+//Bit 15 , ro_int_recv_ecc_err unsigned, RO, default = 0
+//Bit 14 , ro_int_recv_packet unsigned, RO, default = 0
+//Bit 13:0 , reserved
+//
+// Closing file: earc_tx_cmdc.h
+//
+//========================================================================
+// AUDIO EARCTX_DMAC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe333400
+// -----------------------------------------------
+//
+// Reading file: earctx_dmac.h
+//
+#define EARCTX_DMAC_TOP_CTRL0 ((0x0000 << 2) + 0xfe333400)
+//Bit 31, reg_top_reg_sync ,default = 0,Bit 3:0 sync to clk10m,pluse auto clear
+//Bit 30, reg_top_soft_rst ,default = 0
+//Bit 29:26, reserved
+//Bit 25:24, reg_debug_mux ,default = 0
+//Bit 23:21, reserved
+//Bit 20, reg_slow_sync_scan_reg ,default = 0
+//Bit 19, reg_fe_sf_scan_reg ,default = 0
+//Bit 18, reg_fe_slow_sync_scan_reg ,default = 0
+//Bit 17, reg_top_sf_scan_reg ,default = 0
+//Bit 16, reg_top_slow_sync_scan_reg ,default = 0
+//Bit 15:4, reserved
+//Bit 3, reg_spdif_tx_en_force ,default = 0,spdif_tx_en force enable
+//Bit 2, reg_spdif_tx_en_force_value ,default = 0,spdif_tx_en force value
+//Bit 1, reg_dmac_tx_en_force ,default = 0,dmac_tx_en force enable
+//Bit 0, reg_dmac_tx_en_force_value ,default = 0,dmac_tx_en force value
+#define EARCTX_MUTE_VAL ((0x0001 << 2) + 0xfe333400)
+//Bit 31:0, reg_spdif_mute_val ,default = 0,when biahpase encode mute,the channel value,with reg_mute_l/reg_mute_r
+#define EARCTX_SPDIFOUT_GAIN0 ((0x0002 << 2) + 0xfe333400)
+//Bit 31:24, reg_gain_ch3 ,default = 0,channel 3 gain
+//Bit 23:16, reg_gain_ch2 ,default = 0,channel 2 gain
+//Bit 15:8, reg_gain_ch1 ,default = 0,channel 1 gain
+//Bit 7:0, reg_gain_ch0 ,default = 0,channel 0 gain
+#define EARCTX_SPDIFOUT_GAIN1 ((0x0003 << 2) + 0xfe333400)
+//Bit 31:24, reg_gain_ch7 ,default = 0,channel 7 gain
+//Bit 23:16, reg_gain_ch6 ,default = 0,channel 6 gain
+//Bit 15:8, reg_gain_ch5 ,default = 0,channel 5 gain
+//Bit 7:0, reg_gain_ch4 ,default = 0,channel 4 gain
+#define EARCTX_SPDIFOUT_CTRL0 ((0x0004 << 2) + 0xfe333400)
+//Bit 31, reg_work_start ,default = 0,biphase work start,pluse
+//Bit 30, reg_work_clr ,default = 0,biphase work clear,pluse
+//Bit 29, reg_rst_afifo_out_n ,default = 0,afifo out reset
+//Bit 28, reg_rst_afifo_in_n ,default = 0,afifo in reset
+//Bit 27, reg_hold_for_tdm ,default = 0,add delay to mathc TDM out when share buff
+//Bit 26, reg_userdata_sel ,default = 0,user Bit select : 0 from reg_userdata_set 1 from data[29]
+//Bit 25, reg_userdata_set ,default = 0
+//Bit 24, reg_chdata_sel ,default = 0,0 :from reg_chstst 1 from data[30]
+//Bit 23, reserved
+//Bit 22, reg_mute_l ,default = 0,r channel mute ,with reg_mute_val
+//Bit 21, reg_mute_r ,default = 0,l channel mute ,with reg_mute_val
+//Bit 20, reg_data_sel ,default = 0,0 data from 31Bit 1 data from 27bit
+//Bit 19, reg_out_msb_first ,default = 0,0 lsb first 1 msb first
+//Bit 18, reg_valid_sel ,default = 0,biphase encode valid Bit value sel : 0 from data 1 from reg_valid_set
+//Bit 17, reg_valid_set ,default = 0,biphase encode valid Bit value
+//Bit 16, reg_mute_hold_init_en ,default = 0,when c_mute_hold_last_err_corrt valid,clear work enable, initial biphase encode
+//Bit 15:12, reserved
+//Bit 0, reg_parity_mask ,default = 0,Bit 0 is initial parity value
+#define EARCTX_SPDIFOUT_CTRL1 ((0x0005 << 2) + 0xfe333400)
+//Bit 31, reg_eq_drc_sel ,default = 0,set 1 select eq_drc data
+//Bit 30, reg_keep_req_ddr_init ,default = 0,reg_keep_req_ddr_init
+//Bit 29:28, reserved
+//Bit 27, reg_gain_en ,default = 0,gain enable
+//Bit 26:24, reg_frddr_sel ,default = 0,from ddr selet
+//Bit 23:16, reg_wait_cnt ,default = 0,wait some time when enalble set to 1
+//Bit 15:13, reserved
+//Bit 12:8, reg_frddr_msb ,default = 0,msb position of data
+//Bit 7, reg_force_start ,default = 0,set 1 no need ack from frddr to transmit channel status
+//Bit 6:4, reg_frddr_type ,default = 0
+//Bit 3:0, reserved
+#define EARCTX_SPDIFOUT_PREAMB ((0x0006 << 2) + 0xfe333400)
+//Bit 31, reg_premable_Z_set ,default = 0,user 8'b11101000 1 user 7:0
+//Bit 30, reg_premable_Y_set ,default = 0,user 8'b11100100 1 user 15:8
+//Bit 29, reg_premable_X_set ,default = 0,user 8'b11100010 1 user 23:16
+//Bit 28:24, reserved
+//Bit 23:16, reg_premable_X_value ,default = 0
+//Bit 15:8, reg_premable_Y_value ,default = 0
+//Bit 7:0, reg_premable_Z_value ,default = 0
+#define EARCTX_SPDIFOUT_SWAP ((0x0007 << 2) + 0xfe333400)
+//Bit 31:16, reg_hold_cnt ,default = 0,hold start cnt ,valid when reg_hold_for_tdm set 1
+//Bit 15, reg_init_send_en ,default = 0,send 01 squence some times after intial done from frddr set
+//Bit 14:0, reg_init_send_cnt ,default = 0,send 01 squence time ,valid when reg_init_send_en set 1
+#define EARCTX_ERR_CORRT_CTRL0 ((0x0008 << 2) + 0xfe333400)
+//Bit 31:24, reserved
+//Bit 23, reg_bch_in_reverse ,default = 0,bch input data generate in 24it data reverse
+//Bit 22, reg_bch_out_ecc_reverse ,default = 0,bch output ecc reverse
+//Bit 21, reg_bch_out_data_reverse ,default = 0,bch output data reverse
+//Bit 20, reg_bch_out_ecc_msb ,default = 0,bch output ecc position
+//Bit 19:17, reserved
+//Bit 16, reg_ubit_fifo_init_n,default = 0,fifo in initial
+//Bit 15:14, reserved
+//Bit 13:12, reg_gain_shift ,default = 0,gain x 1/2/4/8
+//Bit 11, reg_mix_lr ,default = 0,l/r mix
+//Bit 10:8, reg_spdifout_r_sel ,default = 0,r channel select
+//Bit 7, reserved
+//Bit 6:4, reg_spdifout_l_sel ,default = 0,l channel select
+//Bit 3:0, reg_iu_interval ,default = 0,iu transmit interval
+#define EARCTX_ERR_CORRT_CTRL1 ((0x0009 << 2) + 0xfe333400)
+//Bit 31, reg_ubit_fifo_wr ,default = 0,iu data write enable,pluse,auto clr in reg.v
+//Bit 30:8, reserved
+//Bit 7:0, reg_ubit_fifo_wdata ,default = 0,iu data
+#define EARCTX_ERR_CORRT_CTRL2 ((0x000a << 2) + 0xfe333400)
+//Bit 31, reg_mute_clear ,default = 0,mute clear,pluse,auto clr in reg.v
+//Bit 30, reg_mute_start ,default = 0,mute start,pluse,auto clr in reg.v
+//Bit 29:28, reserved
+//Bit 27:16, reg_mute_block_num ,default = 0,mute block number
+//Bit 15:8, reg_mute_ch_Bit ,default = 0,mute Bit at channel statue which bit
+//Bit 7:3, reserved
+//Bit 2, reg_mute_data_sel ,default = 0,mute data sel: 0 data 1 reg_mute_data_value
+//Bit 1:0, reg_mute_mode ,default = 0,0:always mute 1:mute block number and dis mute 2:mute bolck number and hold bus
+#define EARCTX_ERR_CORRT_CTRL3 ((0x000b << 2) + 0xfe333400)
+//Bit 31:30, reserved
+//Bit 29, reg_bch_en ,default = 0,bch generate enable
+//Bit 28:24, reg_bch_msb ,default = 0,bch data msb position in audio data
+//Bit 23:0, reg_mute_data_value ,default = 0,mute value,only for audio data part
+#define EARCTX_ERR_CORRT_CTRL4 ((0x000c << 2) + 0xfe333400)
+//Bit 31, reg_ubit_fifo_lr_swap ,default = 0,//user Bit lr swap
+//Bit 30, reg_ubit_fifo_lr_same ,default = 0,//l/r channel use same Bit user bit
+//Bit 29:25, reg_data_msb ,default = 0,audio data msb postion in input data
+//Bit 24, reg_data_rsv ,default = 0,audio data msb/lsb
+//Bit 23, reg_ubit_value ,default = 0,user Bit value
+//Bit 22, reg_vbit_value ,default = 0,valid Bit value
+//Bit 21, reg_data_sel ,default = 0,//data sel: 0 data 1 reg_mute_data_value
+//Bit 20:19, reg_ubit_sel ,default = 0,//userBit sel: 0 data 1 reg_value 2 fifo data
+//Bit 18, reg_vbit_sel ,default = 0,//validBit sel: 0 data 1 reg_value
+//Bit 17, reg_chst_sel ,default = 0,//chanel status sel: 0 data 1 reg_value
+//Bit 16, reg_ubit_fifo_less_irq_en ,default = 0,fifo_less_thd irq enable
+//Bit 15:8, reg_ubit_fifo_start_thd ,default = 0,start transmit iu after fifo level greater than this value
+//Bit 7:0, reg_ubit_fifo_less_thd ,default = 0,generate irq,when fifo level less than this value
+#define EARCTX_ERR_CORRT_STAT0 ((0x000d << 2) + 0xfe333400)
+//Bit 31:0, ro_err_corrt_stat0 ,default = 0,
+#define EARCTX_SPDIFOUT_CHSTS0 ((0x000e << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_a_status ,default =0,channel A status[31:0]
+#define EARCTX_SPDIFOUT_CHSTS1 ((0x000f << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_a_status ,default =0,channel A status[63:32]
+#define EARCTX_SPDIFOUT_CHSTS2 ((0x0010 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_a_status ,default =0,channel A status[95:64]
+#define EARCTX_SPDIFOUT_CHSTS3 ((0x0011 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_a_status ,default =0,channel A status[127:96]
+#define EARCTX_SPDIFOUT_CHSTS4 ((0x0012 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_a_status ,default =0,channel A status[159:128]
+#define EARCTX_SPDIFOUT_CHSTS5 ((0x0013 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_a_status ,default =0,channel A status[191:160]
+#define EARCTX_SPDIFOUT_CHSTS6 ((0x0014 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_b_status ,default =0,channel B status[31:0]
+#define EARCTX_SPDIFOUT_CHSTS7 ((0x0015 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_b_status ,default =0,channel B status[63:32]
+#define EARCTX_SPDIFOUT_CHSTS8 ((0x0016 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_b_status ,default =0,channel B status[95:64]
+#define EARCTX_SPDIFOUT_CHSTS9 ((0x0017 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_b_status ,default =0,channel B status[127:96]
+#define EARCTX_SPDIFOUT_CHSTSA ((0x0018 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_b_status ,default =0,channel B status[159:128]
+#define EARCTX_SPDIFOUT_CHSTSB ((0x0019 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_b_status ,default =0,channel B status[191:160]
+#define EARCTX_FE_CTRL0 ((0x001a << 2) + 0xfe333400)
+//Bit 31, reg_mute_hold_clr ,default = 0,clear mute hold statues,pluse, auto clr
+//Bit 30, reg_work_enable ,default = 0,wore enable
+//Bit 29, reg_dmac_invt ,default = 0,fe out invent
+//Bit 28, reg_hold_time_en ,default = 0,hold min time enable
+//Bit 27, reg_hold_soft_clr_en ,default = 0,0 auto clear hold at next valid 1 clear hold with reg_mute_hold_clr
+//Bit 26:24, reg_hold_time_tick_sel ,default = 0,hold min time tick select
+//Bit 23:0, reg_hold_min_time ,default = 0,hold min time
+#define EARCTX_FE_STAT0 ((0x001b << 2) + 0xfe333400)
+//Bit 31:0, ro_fe_stat0 ,default = 0,
+#define EARCTX_SPDIFOUT_STAT ((0x001c << 2) + 0xfe333400)
+//Bit 31:0, ro_spdifout_stat ,default = 0,
+#define EARCTX_SPDIFOUT_CTRL2 ((0x001d << 2) + 0xfe333400)
+//Bit 31:28, reserved
+//Bit 27:16, reg_clr_by_init ,default = 0,reg_clr_by_init
+//Bit 15:0 , reg_mask ,default = 0,reg_mask
+#define EARCTX_SPDIFOUT_GAIN2 ((0x001e << 2) + 0xfe333400)
+//Bit 31:0, spdifout_gain2 ,default = 0,spdifout gain2
+#define EARCTX_SPDIFOUT_GAIN3 ((0x001f << 2) + 0xfe333400)
+//Bit 31:0, spdifout_gain3 ,default = 0,spdifout gain3
+#define EARCTX_SPDIFOUT_GAIN4 ((0x0020 << 2) + 0xfe333400)
+//Bit 31:0, spdifout_gain4 ,default = 0,spdifout gain4
+#define EARCTX_SPDIFOUT_GAIN5 ((0x0021 << 2) + 0xfe333400)
+//Bit 31:0, spdifout_gain5 ,default = 0,spdifout gain5
+//
+//
+// Closing file: earctx_dmac.h
+//
+//========================================================================
+// AUDIO EARCTX_TOP - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xff603600
+// -----------------------------------------------
+//
+// Reading file: earctx_top.h
+//
+#define EARCTX_TOP_CTRL0 ((0x0000 << 2) + 0xff603600)
+//Bit 31:18, reserved
+//Bit 17:16, reg_earctx_debug_mux unsigned, default = 0, debug mux
+//Bit 15, reg_slow_sync_scan_reg unsigned, default = 0, reg_slow_sync_scan_reg
+//Bit 14:12, reserved
+//Bit 11, reg_hdmi_hpd_invt unsigned, default = 0, hdmi_hpd invent
+//Bit 10, reg_hdmi_hpd_value unsigned, default = 0, hdmi_hpd mux = 3,register value
+//Bit 9:8, reg_hdmi_hpd_mux unsigned, default = 0, hdmi_hpd mux
+//Bit 7, reg_earctx_hd_hpd_invt unsigned, default = 0, earctx_hd_hdp invent
+//Bit 6, reg_earctx_hd_hpd_value unsigned, default = 0, earctx_hd_hdp mux = 3,register value
+//Bit 5:4, reg_earctx_hd_hdp_mux unsigned, default = 0, earctx_hd_hdp mux
+//Bit 3:2, reserved
+//Bit 1, reg_earctx_force_mode_en unsigned, default = 0, force mode enale
+//Bit 0, reg_earctx_force_mode unsigned, default = 0, force mode value
+#define EARCTX_DMAC_INT_MASK ((0x0001 << 2) + 0xff603600)
+//Bit 31:6, reserved
+//Bit 5:0, reg_dmac_int_mask unsigned, default = 0, dmac int mask
+#define EARCTX_DMAC_INT_PENDING ((0x0002 << 2) + 0xff603600)
+//Bit 31:6, reserved
+//Bit 5:0, reg_dmac_int_mask unsigned, default = 0, dmac int pending,read only
+#define EARCTX_CMDC_INT_MASK ((0x0003 << 2) + 0xff603600)
+//Bit 31:18, reserved
+//Bit 17:0, reg_cmdc_int_mask unsigned, default = 0, cmdc int mask
+#define EARCTX_CMDC_INT_PENDING ((0x0004 << 2) + 0xff603600)
+//Bit 31:18, reserved
+//Bit 17:0, reg_cmdc_int_mask unsigned, default = 0, cmdc int pending,read only
+#define EARCTX_ANA_CTRL0 ((0x0005 << 2) + 0xff603600)
+//Bit 31:0, reg_earctx_ana_ctrl0 unsigned, default = 0
+#define EARCTX_ANA_CTRL1 ((0x0006 << 2) + 0xff603600)
+//Bit 31:0, reg_earctx_ana_ctrl0 unsigned, default = 0
+#define EARCTX_ANA_CTRL2 ((0x0007 << 2) + 0xff603600)
+//Bit 31:0, reg_earctx_ana_ctrl0 unsigned, default = 0
+#define EARCTX_ANA_STAT0 ((0x0008 << 2) + 0xff603600)
+//Bit 31:0, reg_earctx_ana_ctrl0 unsigned, default = 0
+//
+// Closing file: earctx_top.h
+//
+//========================================================================
+// AUDIO EARCRX_CMDC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe333800
+// -----------------------------------------------
+//
+// Reading file: earc_rx_cmdc.h
+//
+#define EARC_RX_CMDC_TOP_CTRL0 ((0x0000 << 2) + 0xfe333800)
+//Bit 31 , idle2_int unsigned, default = 0, 1: enable
+//Bit 30 , idle1_int unsigned, default = 0, 1: enable
+//Bit 29 , disc2_int unsigned, default = 0, 1: enable
+//Bit 28 , disc1_int unsigned, default = 0, 1: enable
+//Bit 27 , earc_int unsigned, default = 0, 1: enable
+//Bit 26 , hb_status_int unsigned, default = 0, 1: enable
+//Bit 25 , losthb_int unsigned, default = 0, 1: enable
+//Bit 24 , timeout_int unsigned, default = 0, 1: enable
+//Bit 23 , status_ch_int unsigned, default = 0, 1: enable
+//Bit 22 , int_rec_invalid_id unsigned, default = 0, 1: enable
+//Bit 21 , int_rec_invalid_offset unsigned, default = 0, 1: enable
+//Bit 20 , int_rec_unexp unsigned, default = 0, 1: enable
+//Bit 19 , int_rec_ecc_err unsigned, default = 0, 1: enable
+//Bit 18 , int_rec_parity_err unsigned, default = 0, 1: enable
+//Bit 17 , int_recv_packet unsigned, default = 0, 1: enable
+//Bit 16 , int_rec_time_out unsigned, default = 0, 1: enable
+//Bit 15 , cmdc_debug0 unsigned, default = 0, 1: enable
+//Bit 14 , cmdc_debug1 unsigned, default = 0, 1: enable
+//Bit 13 , cmdc_debug2 unsigned, default = 0, 1: enable
+//Bit 12:7 , reserved
+//Bit 6 , mute_select unsigned, default = 0, 1: use bit5, 0: earc off
+//Bit 5 , mute_contrl unsigned, default = 0, value of mannul mute control
+//Bit 4:0 , reserved
+#define EARC_RX_CMDC_TOP_CTRL1 ((0x0001 << 2) + 0xfe333800)
+//Bit 31:13, reserved
+//Bit 12:8, reg_scan_reg unsigned, RW, default = 0,
+//Bit 7:5, reserved
+//Bit 4:0, reg_top_soft_rst unsigned, RW, default = 0,
+#define EARC_RX_CMDC_TOP_CTRL2 ((0x0002 << 2) + 0xfe333800)
+//Bit 31, reset_idle2_int unsigned, default =0
+//Bit 30, reset_idle1_int unsigned, default =0
+//Bit 29, reset_disc2_int unsigned, default =0
+//Bit 28, reset_disc1_int unsigned, default =0
+//Bit 27, reset_earc_int unsigned, default =0
+//Bit 26, reset_hb_status_int unsigned, default =0
+//Bit 25, reset_losthb_int unsigned, default =0
+//Bit 24, reset_timeout_int unsigned, default =0
+//Bit 23, reset_status_ch_int unsigned, default =0
+//Bit 22, reset_int_rec_invalid_id unsigned, default =0
+//Bit 21, reset_int_rec_invalid_offset unsigned, default =0
+//Bit 20, reset_int_rec_unexp unsigned, default =0
+//Bit 19, reset_int_rec_ecc_err unsigned, default =0
+//Bit 18, reset_int_rec_parity_err unsigned, default =0
+//Bit 17, reset_int_recv_packet unsigned, default =0
+//Bit 16, reset_int_rec_time_out unsigned, default =0
+//Bit 15:0, reserved
+#define EARC_RX_CMDC_TIMER_CTRL0 ((0x0003 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_TIMER_CTRL1 ((0x0004 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_TIMER_CTRL2 ((0x0005 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_TIMER_CTRL3 ((0x0006 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_VSM_CTRL0 ((0x0007 << 2) + 0xfe333800)
+//Bit 31, sw_state_update unsigned, default = 0, XX
+//Bit 30:28, sw_state unsigned, default = 0, XX
+//Bit 27, arc_initiated unsigned, default = 0, XX
+//Bit 26, arc_terminated unsigned, default = 0, XX
+//Bit 25, arc_enable unsigned, default = 0, XX
+//Bit 24, man_hpd unsigned, default = 0, XX
+//Bit 23:22, hpd_sel unsigned, default = 0, XX
+//Bit 21:20, hpd_sel_earc unsigned, default = 0, XX
+//Bit 19, comma_cnt_rst unsigned, default = 0, XX
+//Bit 18, timeout_status_rst unsigned, default = 0, XX
+//Bit 17, losthb_status_rst unsigned, default = 0, XX
+//Bit 16, force_rst unsigned, default = 0, XX
+//Bit 15, auto_state unsigned, default = 0, XX
+//Bit 14, cmdc_state_en unsigned, default = 0, XX
+//Bit 13:0, reserved
+#define EARC_RX_CMDC_VSM_CTRL1 ((0x0008 << 2) + 0xfe333800)
+//Bit 31:12, max_count_th unsigned, default = 0, idle done timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, idle done timing
+//Bit 6:4, time_sel unsigned, default = 0, idle done timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, idle done timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, idle done timing
+#define EARC_RX_CMDC_VSM_CTRL2 ((0x0009 << 2) + 0xfe333800)
+//Bit 31:12, max_count_th unsigned, default = 0, comma off done timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, comma off done timing
+//Bit 6:4, time_sel unsigned, default = 0, comma off done timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, comma off done timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, comma off done timing
+#define EARC_RX_CMDC_VSM_CTRL3 ((0x000a << 2) + 0xfe333800)
+//Bit 31:12, max_count_th unsigned, default = 0, earc_time out timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, earc_time out timing
+//Bit 6:4, time_sel unsigned, default = 0, earc_time out timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, earc_time out timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, earc_time out timing
+#define EARC_RX_CMDC_VSM_CTRL4 ((0x000b << 2) + 0xfe333800)
+//Bit 31:12, max_count_th unsigned, default = 0, heartbeat lost timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, heartbeat lost timing
+//Bit 6:4, time_sel unsigned, default = 0, heartbeat lost timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, heartbeat lost timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, heartbeat lost timing
+#define EARC_RX_CMDC_VSM_CTRL5 ((0x000c << 2) + 0xfe333800)
+//Bit 31:16, reserved
+//Bit 15:8, status_soft unsigned, default = 0, in earc heartbeat det timing
+//Bit 7, reg_soft_rst unsigned, default = 0, in earc heartbeat det timing
+//Bit 6, status_rst unsigned, default = 0, in earc heartbeat det timing
+//Bit 5:4, reserved
+//Bit 3:2, soft_rst_sel unsigned, default = 0, in earc heartbeat det timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, in earc heartbeat det timing
+#define EARC_RX_CMDC_VSM_CTRL6 ((0x000d << 2) + 0xfe333800)
+//Bit 31:17, reserved
+//Bit 16, cntl_hpd_sel unsigned, default = 0, in earc heartbeat det timing
+//Bit 15:4, cntl_hpd_valid_width unsigned, default = 0, in earc heartbeat det timing
+//Bit 3:0, cntl_hpd_glitch_width unsigned, default = 0, in earc heartbeat det timing
+#define EARC_RX_CMDC_VSM_CTRL7 ((0x000e << 2) + 0xfe333800)
+//Bit 31:0, vsm_ctrl7 unsigned, default = 0,
+#define EARC_RX_CMDC_VSM_CTRL8 ((0x000f << 2) + 0xfe333800)
+//Bit 31:0, vsm_ctrl8 unsigned, default = 0,
+#define EARC_RX_CMDC_VSM_CTRL9 ((0x0010 << 2) + 0xfe333800)
+//Bit 31:0, vsm_ctrl9 unsigned, default = 0,
+#define EARC_RX_CMDC_SENDER_CTRL0 ((0x0011 << 2) + 0xfe333800)
+//Bit 31:2, reserved
+//Bit 1, hb_chg_conf_auto unsigned, default = 0,
+//Bit 0, hb_chg_auto unsigned, default = 1,
+#define EARC_RX_CMDC_PACKET_CTRL0 ((0x0012 << 2) + 0xfe333800)
+//Bit 31, packet_mode_enable unsigned, default = 0, packet control
+//Bit 30, free_enable unsigned, default = 0, packet control
+//Bit 29, soft_rst_man unsigned, default = 0, packet control
+//Bit 28:24, ready_th unsigned, default = 0, packet control
+//Bit 23:20, reserved
+//Bit 19:8, send_pre_th unsigned, default = 0, packet control
+//Bit 7:5, reserved
+//Bit 4, sw_state_update unsigned, default = 0, packet control
+//Bit 3:0, sw_state unsigned, default = 0, packet control
+#define EARC_RX_CMDC_PACKET_CTRL1 ((0x0013 << 2) + 0xfe333800)
+//Bit 31, ecc_endian unsigned, default = 0, send
+//Bit 30, pre_reg_st unsigned, default = 0, send
+//Bit 29:21, reserved
+//Bit 20:16, post_th unsigned, default = 0, send
+//Bit 15:14, reserved
+//Bit 13:8, pre_th unsigned, default = 0,
+//Bit 7:0, post_flag unsigned, default = 0,
+#define EARC_RX_CMDC_PACKET_CTRL2 ((0x0014 << 2) + 0xfe333800)
+//Bit 31:0, pre_flag unsigned, default = 0, X
+#define EARC_RX_CMDC_PACKET_CTRL3 ((0x0015 << 2) + 0xfe333800)
+//Bit 31, cmdc_en unsigned, default = 0, XX
+//Bit 30, cmdc_parity_mask unsigned, default = 0, XX
+//Bit 29, imeout_en unsigned, default = 0, XX
+//Bit 28, ecc_check_en unsigned, default = 0, XX
+//Bit 27, rev_debug_en unsigned, default = 0, XX
+//Bit 26:16, reserved
+//Bit 15:0, timeout_th unsigned, default = 0, X
+#define EARC_RX_CMDC_PACKET_CTRL4 ((0x0016 << 2) + 0xfe333800)
+//Bit 31, ack_ignore unsigned, default = 0, XX
+//Bit 30, cmdc_tail_check_mask unsigned, default = 0, XX
+//Bit 29:20, reserved
+//Bit 19:0, cmdc_packet_head unsigned, default = 0, XX
+#define EARC_RX_CMDC_PACKET_CTRL5 ((0x0017 << 2) + 0xfe333800)
+//Bit 31:24, rev_debug_mask unsigned, default = 0, XX
+//Bit 23:20, reserved
+//Bit 19:0, cmdc_packet_head_mask unsigned, default = 0, XX
+#define EARC_RX_CMDC_PACKET_CTRL6 ((0x0018 << 2) + 0xfe333800)
+//Bit 31:20, recv_pre_threshold unsigned, default = 0, packet control
+//Bit 19:9, reserved
+//Bit 8, rec_packet_d unsigned, default = 0, XX
+//Bit 7, rec_parity_err_cnt unsigned, default = 0, XX
+//Bit 6, rec_ecc_err_cnt unsigned, default = 0, XX
+//Bit 5, rec_unexp_cnt unsigned, default = 0, XX
+//Bit 4, rec_invalid_offset_cnt unsigned, default = 0, XX
+//Bit 3, rec_invalid_id_cnt unsigned, default = 0, XX
+//Bit 2, rec_timeout_cnt unsigned, default = 0, XX
+//Bit 1, rec_w_cnt unsigned, default = 0, XX
+//Bit 0, rec_r_cnt unsigned, default = 0, X
+#define EARC_RX_CMDC_BIPHASE_CTRL0 ((0x0019 << 2) + 0xfe333800)
+//Bit 31:24, reg_tns unsigned, default = 7, xx
+//Bit 23:16, delay_th unsigned, default = 0, xx
+//Bit 15:10, reserved
+//Bit 9, send_ack_en unsigned, default = 0, xx
+//Bit 8, sq_val_en unsigned, default = 0, XX
+//Bit 7, biphase_send_soft_rst unsigned, default = 0, XX
+//Bit 6, comma_soft_rst unsigned, default = 0, XX
+//Bit 5, fifo_rst unsigned, default = 0, XX
+//Bit 4, receiver_no_sender unsigned, default = 0, XX
+//Bit 3, sender_free unsigned, default = 0, XX
+//Bit 2, receiver_send unsigned, default = 0, XX
+//Bit 1, receiver_earc unsigned, default = 0, XX
+//Bit 0, receiver_free unsigned, default = 0, XX
+#define EARC_RX_CMDC_BIPHASE_CTRL1 ((0x001a << 2) + 0xfe333800)
+//Bit 31:16, reserved
+//Bit 15, ack_val_en unsigned, default = 0, send
+//Bit 14:8, reserved
+//Bit 7:0, width unsigned, default = 0, send
+#define EARC_RX_CMDC_BIPHASE_CTRL2 ((0x001b << 2) + 0xfe333800)
+//Bit 31, ack_val_en unsigned, default = 0, send
+//Bit 30:20, reserved
+//Bit 19:16, ack_rate unsigned, default = 0, comma send
+//Bit 15:0, width unsigned, default = 0, comma sen
+#define EARC_RX_CMDC_BIPHASE_CTRL3 ((0x001c << 2) + 0xfe333800)
+//Bit 31:0, biphase_ctrl3 unsigned, default = 0,
+#define EARC_RX_CMDC_DEVICE_ID_CTRL ((0x001d << 2) + 0xfe333800)
+//Bit 31, apb_write unsigned, default = 0, apb bus wr/read
+//Bit 30, apb_read unsigned, default = 0, apb bus wr/read
+//Bit 29, apb_w_r_done unsigned, default = 0, apb bus wr/read
+//Bit 28, apb_w_r_reset unsigned, default = 0, apb bus wr/read
+//Bit 27:16, reserved
+//Bit 15:8, apb_w_r_id unsigned, default = 0, apb bus wr/read
+//Bit 7:0, apb_w_r_start_addr unsigned, default = 0, apb bus wr/read
+#define EARC_RX_CMDC_DEVICE_WDATA ((0x001e << 2) + 0xfe333800)
+//Bit 31:8, reserved
+//Bit 7:0, apb_write_data unsigned, default = 0, apb bus wr/rea
+#define EARC_RX_CMDC_DEVICE_RDATA ((0x001f << 2) + 0xfe333800)
+//Bit 31:8, reserved
+//Bit 7:0, apb_read_data unsigned, default = 0, apb bus wr/rea
+#define EARC_RX_ANA_CTRL0 ((0x0020 << 2) + 0xfe333800)
+//Bit 31:0, ana_ctrl0 unsigned, default = 0,
+#define EARC_RX_ANA_CTRL1 ((0x0021 << 2) + 0xfe333800)
+//Bit 31:0, ana_ctrl1 unsigned, default = 0,
+#define EARC_RX_ANA_CTRL2 ((0x0022 << 2) + 0xfe333800)
+//Bit 31:0, ana_ctrl2 unsigned, default = 0,
+#define EARC_RX_ANA_CTRL3 ((0x0023 << 2) + 0xfe333800)
+//Bit 31:0, ana_ctrl3 unsigned, default = 0,
+#define EARC_RX_ANA_CTRL4 ((0x0024 << 2) + 0xfe333800)
+//Bit 31:0, ana_ctrl4 unsigned, default = 0,
+#define EARC_RX_ANA_CTRL5 ((0x0025 << 2) + 0xfe333800)
+//Bit 31:0, ana_ctrl5 unsigned, default = 0,
+#define EARC_RX_ANA_STAT0 ((0x0026 << 2) + 0xfe333800)
+//Bit 31:0, ro_ANA_status0 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS0 ((0x0027 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS1 ((0x0028 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status1 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS2 ((0x0029 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status2 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS3 ((0x002a << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status3 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS4 ((0x002b << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status4 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS5 ((0x002c << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status5 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS6 ((0x002d << 2) + 0xfe333800)
+//Bit 31, ro_idle2_int unsigned, RO, dfault =0
+//Bit 30, ro_idle1_int unsigned, RO, dfault =0
+//Bit 29, ro_disc2_int unsigned, RO, dfault =0
+//Bit 28, ro_disc1_int unsigned, RO, dfault =0
+//Bit 27, ro_earc_int unsigned, RO, dfault =0
+//Bit 26, ro_hb_status_int unsigned, RO, dfault =0
+//Bit 25, ro_losthb_int unsigned, RO, dfault =0
+//Bit 24, ro_timeout_int unsigned, RO, dfault =0
+//Bit 23, ro_status_ch_int unsigned, RO, dfault =0
+//Bit 22, ro_int_rec_invalid_id unsigned, RO, dfault =0
+//Bit 21, ro_int_rec_invalid_offset unsigned, RO, dfault =0
+//Bit 20, ro_int_rec_unexp unsigned, RO, dfault =0
+//Bit 19, ro_int_rec_ecc_err unsigned, RO, dfault =0
+//Bit 18, ro_int_rec_parity_err unsigned, RO, dfault =0
+//Bit 17, ro_int_recv_packet unsigned, RO, dfault =0
+//Bit 16, ro_int_rec_time_out unsigned, RO, dfault =0
+//Bit 15:0, reserved
+//
+// Closing file: earc_rx_cmdc.h
+//
+//========================================================================
+// AUDIO EARCRX_DMAC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe333c00
+// -----------------------------------------------
+//
+// Reading file: earcrx_dmac.h
+//
+#define EARCRX_DMAC_TOP_CTRL0 ((0x0000 << 2) + 0xfe333c00)
+//Bit 31, reg_top_work_en unsigned, default = 0, top work enable
+//Bit 30, reg_top_soft_rst unsigned, default = 0, top soft reset
+//Bit 29:23, reserved
+//Bit 22:20, reg_dmac_debug_sel unsigned, default = 0, dmac debug select
+//Bit 19:18, reserved
+//Bit 17, reg_dmac_valid_sel unsigned, default = 0, dmac sync without clk
+//Bit 16, reg_dmac_without_clk unsigned, default = 0, dmac sync without clk
+//Bit 15, reg_sf_sync_scan_reg unsigned, default = 0, rst_n soft reset scan reg
+//Bit 14, reserved
+//Bit 13, reg_slow_sync_scan_reg unsigned, default = 0, rst_n sync clk_slow scan reg
+//Bit 12, reg_a_sync_scan_reg unsigned, default = 0, rst_n sync clk_analog scan reg
+//Bit 11, reg_slow_auto_gate unsigned, default = 0, clk_slow auto gate
+//Bit 10, reg_a_auto_gate unsigned, default = 0, clk_analog auto gate
+//Bit 9:0, reserved
+#define EARCRX_DMAC_SYNC_CTRL0 ((0x0001 << 2) + 0xfe333c00)
+//Bit 31, reg_work_enable unsigned, default = 0, dmac sync module work enable
+//Bit 30, reg_rst_afifo_out_n unsigned, default = 0, afifo out reset
+//Bit 29, reg_rst_afifo_in_n unsigned, default = 0, afifo in reset
+//Bit 28:17, reserved
+//Bit 16, reg_ana_buf_data_sel_en unsigned, default = 0, data from analog delay enable
+//Bit 15, reserved
+//Bit 14:12, reg_ana_buf_data_sel unsigned, default = 0, delay cycles
+//Bit 11, reserved
+//Bit 10:8, reg_ana_clr_cnt unsigned, default = 0, valid last how many 0 will clear
+//Bit 7, reserved
+//Bit 6:4, reg_ana_set_cnt unsigned, default = 0, valid last how may 1 will set
+//Bit 3:1, reserved
+//Bit 0, reg_dmacin_phase unsigned, default = 0, dmac data invert
+#define EARCRX_DMAC_SYNC_STAT0 ((0x0002 << 2) + 0xfe333c00)
+//Bit 31:0, reg_dmac_sync_stat0 unsigned, default = 0
+#define EARCRX_SPDIFIN_SAMPLE_CTRL0 ((0x0003 << 2) + 0xfe333c00)
+//Bit 31, reg_work_enable unsigned, default = 0, spdif in sample enable
+//Bit 30, reg_spdifin_phase unsigned, default = 0, spdif in invert
+//Bit 29, reg_debug_en unsigned, default = 0, debug single enable
+//Bit 28, reg_width_sel unsigned, default = 0, 0 detect by max_width 1 detect by min_width
+//Bit 27:23, reserved
+//Bit 22:20, reg_sample_mode unsigned, default = 0, value
+//Bit 19:0, reg_base_timer unsigned, default = 0, base timer to detect sample mode change
+#define EARCRX_SPDIFIN_SAMPLE_CTRL1 ((0x0004 << 2) + 0xfe333c00)
+//Bit 31, reg_force_sample_mode unsigned, default = 0, 0 auto detect sample mode 1 force a fixed sample mode with reg_sample_mode
+//Bit 30, reserved
+//Bit 29:20, reg_sample_mode0_timer_th unsigned, default = 0, mode0 threathold time
+//Bit 19:10, reg_sample_mode1_timer_th unsigned, default = 0, mode1 threathold time
+//Bit 9:0, reg_sample_mode2_timer_th unsigned, default = 0, mode2 threathold time
+#define EARCRX_SPDIFIN_SAMPLE_CTRL2 ((0x0005 << 2) + 0xfe333c00)
+//Bit 31:30, reserved
+//Bit 29:20, reg_sample_mode3_timer_th unsigned, default = 0, mode3 threathold time
+//Bit 19:10, reg_sample_mode4_timer_th unsigned, default = 0, mode4 threathold time
+//Bit 9:0, reg_sample_mode5_timer_th unsigned, default = 0, mode5 threathold time
+#define EARCRX_SPDIFIN_SAMPLE_CTRL3 ((0x0006 << 2) + 0xfe333c00)
+//Bit 31:24, reg_sample_mode0_timer unsigned, default = 0, mode0 sample time
+//Bit 23:16, reg_sample_mode1_timer unsigned, default = 0, mode1 sample time
+//Bit 15:8, reg_sample_mode2_timer unsigned, default = 0, mode2 sample time
+//Bit 7:0, reg_sample_mode3_timer unsigned, default = 0, mode3 sample time
+#define EARCRX_SPDIFIN_SAMPLE_CTRL4 ((0x0007 << 2) + 0xfe333c00)
+//Bit 31:24, reg_sample_mode4_timer unsigned, default = 0, mode4 sample time
+//Bit 23:16, reg_sample_mode5_timer unsigned, default = 0, mode5 sample time
+//Bit 15:8, reg_sample_mode6_timer unsigned, default = 0, mode6 sample time
+//Bit 7:0, reserved
+#define EARCRX_SPDIFIN_SAMPLE_CTRL5 ((0x0008 << 2) + 0xfe333c00)
+//Bit 31, reg_sq_filt_en unsigned, default = 0, dmac_sqout filter enable
+//Bit 30, reg_spdif_sqout_phase unsigned, default = 0, dmac_sqout invert
+//Bit 29:27, reg_filter_tick_sel unsigned, default = 0, dmac_sqout filter tick select
+//Bit 26:24, reg_filter_sel unsigned, default = 0, dmac_sqout filter select
+//Bit 23:20, reserved
+//Bit 19:0, reg_sq_filt_timer unsigned, default = 0, dmac_sqout filter tick
+#define EARCRX_SPDIFIN_SAMPLE_STAT0 ((0x0009 << 2) + 0xfe333c00)
+//Bit 31:0, reg_spdifin_sample_stat0 unsigned, default = 0
+#define EARCRX_SPDIFIN_SAMPLE_STAT1 ((0x000a << 2) + 0xfe333c00)
+//Bit 31:0, reg_spdifin_sample_stat1 unsigned, default = 0
+#define EARCRX_SPDIFIN_MUTE_VAL ((0x000b << 2) + 0xfe333c00)
+//Bit 31:0, reg_spdifin_mute_val unsigned, default = 0, spdif in mute value
+#define EARCRX_SPDIFIN_CTRL0 ((0x000c << 2) + 0xfe333c00)
+//Bit 31, reg_work_enable unsigned, default = 0, spdifin wore enable
+//Bit 30, reg_chnum_sel unsigned, default = 0, 0 ch_num = 0~383 1 ch_num = 0~1
+//Bit 29:28, reserved
+//Bit 27, reg_debug_en unsigned, default = 0, debug enable
+//Bit 26, reg_chnum_en unsigned, default = 0, star add ch_cnt to ch_num
+//Bit 25, reg_findpapb_en unsigned, default = 0, papb check enalbe
+//Bit 24, reg_nonpcm2pcm_en unsigned, default = 0, nonpcm2pcm_th enable
+//Bit 23:12, reg_nonpcm2pcm_th unsigned, default = 0, if long time didn't detect PaPb again,will generate irq
+//Bit 11:8, reg_ch_status_sel unsigned, default = 0, for stat1/stat2
+//Bit 7, reg_mute_l unsigned, default = 0, mute channel l
+//Bit 6, reg_mute_r unsigned, default = 0, mute channel r
+//Bit 5:4, reserved
+//Bit 3, reg_check_valid unsigned, default = 0, valid check enable
+//Bit 2, reg_check_parity unsigned, default = 0, parity check enable
+//Bit 1, reg_invert_data unsigned, default = 0, spdif data invert
+//Bit 0, reserved
+#define EARCRX_SPDIFIN_CTRL1 ((0x000d << 2) + 0xfe333c00)
+//Bit 31:24, reserved
+//Bit 31:24, reg_clr_internal_sts unsigned, default = 0, internal irq status clear
+//Bit 23:12, reg_mute_block_check_thd unsigned, default = 0, mute block check time thd
+//Bit 11:9, reg_mute_block_check_tick_sel unsigned, default = 0, mute block check tick sel
+//Bit 8, reg_papb_ext_sync unsigned, default = 0, ext 0 sync check for papb
+//Bit 7:0, reg_papb_ext_mask unsigned, default = 0, sync 0 mask
+#define EARCRX_SPDIFIN_CTRL2 ((0x000e << 2) + 0xfe333c00)
+//Bit 31:24, reg_mute_bit unsigned, default = 0, mute bit in channel st
+//Bit 23:19, reg_mute_block_num unsigned, default = 0, mute min block number to declare
+//Bit 18, reg_mute_lr_ch_sel unsigned, default = 0, mute bit in channel st L or R
+//Bit 17, reg_mute_block_check_en unsigned, default = 0, mute block number check enable
+//Bit 16, reg_earc_cps_chst_clr_en unsigned, default = 0, auto clear compress mode when channel status not compress
+//Bit 15, reg_earc_cps_nonpcm2pcm_clr_en unsigned, default = 0, auto clear compress mode when nonpcm2pcm
+//Bit 14, reg_earc_auto unsigned, default = 0, auto change earc/arc
+//Bit 13, reg_earcin_papb_lr unsigned, default = 0, user l or r channle status to check papb
+//Bit 12, reg_earcin_check_papb unsigned, default = 0, 0:data valid after 1 block;1: in 1st block if exit papb ,data valid after papb
+//Bit 11, reg_earcin_start_papb unsigned, default = 0, start write toddr 1:from papb check,0 from preamble Z,valid when reg_earcin_check_papb set
+//Bit 10, reg_formatchange_auto_rst unsigned, default = 0, auto reset will detect format change
+//Bit 9, reg_earcin_cpsb_pcpd_sel unsigned, default = 0, compress B pcpd select : 1:next 4th subframe data 0:next sub frame data
+//Bit 8:4, reg_earc_papb_msb unsigned, default = 0, papb msb position in data
+//Bit 3, reg_earcin_spdif_force unsigned, default = 0, when in arc mode,spdif on force enable
+//Bit 2, reg_earcin_spdif_force_set unsigned, default = 0, force value
+//Bit 1, reg_earcin_mode_force unsigned, default = 0, earc mode force enable
+//Bit 0, reg_earcin_mode_force_set unsigned, default = 0, force value
+#define EARCRX_SPDIFIN_CTRL3 ((0x000f << 2) + 0xfe333c00)
+//Bit 31:16, reg_earc_pa_value unsigned, default = 0, earc mode pa value
+//Bit 15:0, reg_earc_pb_value unsigned, default = 0, earc mode pb value
+#define EARCRX_SPDIFIN_STAT0 ((0x0010 << 2) + 0xfe333c00)
+//Bit 31:0, reg_spdifin_stat0 unsigned, default = 0
+#define EARCRX_SPDIFIN_STAT1 ((0x0011 << 2) + 0xfe333c00)
+//Bit 31:0, reg_spdifin_stat1 unsigned, default = 0
+#define EARCRX_SPDIFIN_STAT2 ((0x0012 << 2) + 0xfe333c00)
+//Bit 31:0, reg_spdifin_stat2 unsigned, default = 0
+#define EARCRX_DMAC_UBIT_CTRL0 ((0x0013 << 2) + 0xfe333c00)
+//Bit 31, reg_work_enable unsigned, default = 0, dmac user bit decode enable
+//Bit 30:24, reg_iu_sync unsigned, default = 0, iu sync value
+//Bit 23:16, reg_fifo_thd unsigned, default = 0, generate irq when fifo level pass some threthold
+//Bit 15, reg_max_dist_en unsigned, default = 0, max distance bewteen IUs to set lost
+//Bit 14, reg_iu_sync_en unsigned, default = 0, iu sync code enable 0 : all iu to fifo 1 only sync iu packet to fifo
+//Bit 13:12, reg_user_lr unsigned, default = 0, 00 off 01 use l channel userbit 10 use r channel userbit 11 user lr channel userbit
+//Bit 11:8, reg_max_dist unsigned, default = 0, max distance bewteen IUs value
+//Bit 7, reg_fifo_thd_en unsigned, default = 0, fifo_thd irq enable
+//Bit 6, reg_fifo_lost_init_en unsigned, default = 0, when lost,initial fifo
+//Bit 5, reg_fifo_init unsigned, default = 0, fifo initial
+//Bit 4:0, reg_data_bit unsigned, default = 0, user bit position in data
+#define EARCRX_IU_RDATA ((0x0014 << 2) + 0xfe333c00)
+//Bit 31:8, reserved
+//Bit 7:0, i_iu_rdata unsigned, default = 0, iu data,read only
+#define EARCRX_DMAC_UBIT_STAT0 ((0x0015 << 2) + 0xfe333c00)
+//Bit 31:0, reg_dmac_ubit_stat0 unsigned, default = 0
+#define EARCRX_ERR_CORRECT_CTRL0 ((0x0016 << 2) + 0xfe333c00)
+//Bit 31, reg_work_enable unsigned, default = 0, err correct work enable
+//Bit 30, reserved
+//Bit 29, reg_rst_afifo_out_n unsigned, default = 0, reset afifo out side
+//Bit 28, reg_rst_afifo_in_n unsigned, default = 0, reset afifo in side
+//Bit 27, reg_lr_check unsigned, default = 0, enable lr_check
+//Bit 26:7, reserved
+//Bit 6, reg_bchout_data_ml unsigned, default = 0, bch output 16bit data msb is 27 or 19
+//Bit 5, reg_bchout_data_rsv unsigned, default = 0, bch output data revers
+//Bit 4, reg_bchin_ecc_ml unsigned, default = 0, bch input ecc msb/lsb
+//Bit 3, reg_bchin_ecc_rsv unsigned, default = 0, bch input ecc revers
+//Bit 2, reg_bchin_data_rsv unsigned, default = 0, bch input data revers
+//Bit 1, reg_force_set unsigned, default = 0, 0 off 1 compress audio mode
+//Bit 0, reg_force_en unsigned, default = 0, force work mode enable
+#define EARCRX_ERR_CORRECT_STAT0 ((0x0017 << 2) + 0xfe333c00)
+//Bit 31:0, reg_err_correct_stat0 unsigned, default = 0
+#define EARCRX_ANA_RST_CTRL0 ((0x0018 << 2) + 0xfe333c00)
+//Bit 31, reg_work_enable unsigned, default = 0, analog reset check work enable
+//Bit 30, reg_ana_rst_sf_en unsigned, default = 0, analog reset from register enable
+//Bit 29, reg_ana_rst_sf unsigned, default = 0, soft reset value
+//Bit 28, reserved
+//Bit 27:23, reg_new_format_pos_num unsigned, default = 0, when new format data in, hold reset after N posedge
+//Bit 22:20, reg_dmacrx_div2_thd_tick_sel unsigned, default = 0, earcrx_div2 hold thresthold tick select
+//Bit 19:0, reg_earcrx_div2_thd unsigned, default = 0, earcrx_div2 hold thresthold
+#define EARCRX_ANA_RST_CTRL1 ((0x0019 << 2) + 0xfe333c00)
+//Bit 31, reg_dmacrx_data_filt_en unsigned, default = 0, filter enable
+//Bit 30:28, reg_dmacrx_data_filter_sel unsigned, default = 0, filter select
+//Bit 27:25, reg_dmacrx_data_tick_sel unsigned, default = 0, filter tick sel
+//Bit 24:16, reg_dmacrx_data_time unsigned, default = 0, filter tick time
+//Bit 15, reg_dmacrx_sqout_filt_en unsigned, default = 0, filter enable
+//Bit 14:12, reg_dmacrx_sqout_filter_sel unsigned, default = 0, filter select
+//Bit 11:9, reg_dmacrx_sqout_tick_sel unsigned, default = 0, filter tick sel
+//Bit 8:0, reg_dmacrx_sqout_time unsigned, default = 0, filter tick time
+#define EARCRX_SPDIFIN_CTRL4 ((0x0020 << 2) + 0xfe333c00)
+//Bit 31, reserved
+//Bit 30, reg_add_ch_r unsigned, default = 0, reg_add_ch_r
+//Bit 29, reg_bc_val0_en unsigned, default = 0, reg_bc_val0_en
+//Bit 28:20, reg_stable_mask unsigned, default = 0, reg_stable_mask
+//Bit 19:16, reg_stable_zcnt unsigned, default = 0, reg_stable_zcnt
+//Bit 15:0 , reserved
+#define EARCRX_SPDIFIN_CTRL5 ((0x0021 << 2) + 0xfe333c00)
+//Bit 31, reg_st_timeout_sts_clr unsigned, default = 0, reg_st_timeout_sts_clr
+//Bit 30:28, reserved
+//Bit 27:16, reg_st_timeout_check_thd unsigned, default = 0, reg_st_timeout_check_thd
+//Bit 15, reserved
+//Bit 14:12, reg_st_timeout_check_tick_sel unsigned, default = 0, reg_st_timeout_check_tick_sel
+//Bit 11, reg_st_timeout_check_en unsigned, default = 0, reg_st_timeout_check_en
+//Bit 10:9, reserved
+//Bit 8:0, reg_stable_int_mask unsigned, default = 0, reg_stable_int_mask
+#define EARCRX_SPDIFIN_CTRL6 ((0x0022 << 2) + 0xfe333c00)
+//Bit 31:17, reserved
+//Bit 16, reg_check_time_en unsigned, default = 0, reg_check_time_en
+//Bit 15:0, reg_check_time_thd unsigned, default = 0, reg_check_time_thd
+#define EARCRX_DMAC_SYNC_CTRL1 ((0x0023 << 2) + 0xfe333c00)
+//Bit 31:19, reserved
+//Bit 18, reg_auto_neg_int_en unsigned, default = 0, reg_auto_neg_int_en
+//Bit 17, reg_auto_stable_clr unsigned, default = 0, reg_auto_stable_clr
+//Bit 16, reg_auto_stable_en unsigned, default = 0, reg_auto_stable_en
+//Bit 15:0, reg_auto_stable_thd unsigned, default = 0, reg_auto_stable_thd
+#define EARCRX_SPDIFIN_SAMPLE_CTRL6 ((0x0024 << 2) + 0xfe333c00)
+//Bit 31:18, reserved
+//Bit 17, reg_hold_tri_sample unsigned, default = 0, reg_hold_tri_sample
+//Bit 16, reg_sample_mode_filter_en unsigned, default = 0, reg_sample_mode_filter_en
+//Bit 15:8, reg_stable_cyc_min unsigned, default = 0, reg_stable_cyc_min
+//Bit 7:0, reg_stable_cyc_max unsigned, default = 0, reg_stable_cyc_max
+#define EARCRX_DMAC_SYNC_CTRL2 ((0x0025 << 2) + 0xfe333c00)
+//Bit 31, reg_unstable_t0_err_clr unsigned, default = 0, reg_unstable_t0_err_clr
+//Bit 30:20, reserved
+//Bit 19, reg_unstable_t0_check_en unsigned, default = 0, reg_unstable_t0_check_en
+//Bit 18:16, reg_unstable_t0_tick_sel unsigned, default = 0, reg_unstable_t0_tick_sel
+//Bit 15:0, reg_unstable_t0_thd unsigned, default = 0, reg_unstable_t0_thd
+#define EARCRX_DMAC_SYNC_CTRL3 ((0x0026 << 2) + 0xfe333c00)
+//Bit 31, reg_unstable_t1_err_clr unsigned, default = 0, reg_unstable_t1_err_clr
+//Bit 30:20, reserved
+//Bit 19, reg_unstable_t1_check_en unsigned, default = 0, reg_unstable_t1_check_en
+//Bit 18:16, reg_unstable_t1_tick_sel unsigned, default = 0, reg_unstable_t1_tick_sel
+//Bit 15:0, reg_unstable_t1_thd unsigned, default = 0, reg_unstable_t1_thd
+#define EARCRX_DMAC_SYNC_CTRL4 ((0x0027 << 2) + 0xfe333c00)
+//Bit 31, reg_unstable_t2_err_clr unsigned, default = 0, reg_unstable_t2_err_clr
+//Bit 30:20, reserved
+//Bit 19, reg_unstable_t2_check_en unsigned, default = 0, reg_unstable_t2_check_en
+//Bit 18:16, reg_unstable_t2_tick_sel unsigned, default = 0, reg_unstable_t2_tick_sel
+//Bit 15:0, reg_unstable_t2_thd unsigned, default = 0, reg_unstable_t2_thd
+#define EARCRX_DMAC_SYNC_STAT1 ((0x0028 << 2) + 0xfe333c00)
+//Bit 31:0, reg_dmac_sync_stat1 unsigned, default = 0
+#define EARCRX_DMAC_SYNC_STAT2 ((0x0029 << 2) + 0xfe333c00)
+//Bit 31:0, reg_dmac_sync_stat2 unsigned, default = 0
+#define EARCRX_DMAC_SYNC_STAT3 ((0x002a << 2) + 0xfe333c00)
+//Bit 31:0, reg_dmac_sync_stat3 unsigned, default = 0
+//
+// Closing file: earcrx_dmac.h
+//
+//========================================================================
+// AUDIO EARCRX_TOP - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe333e00
+// -----------------------------------------------
+//
+// Reading file: earcrx_top.h
+//
+#define EARCRX_TOP_CTRL0 ((0x0000 << 2) + 0xfe333e00)
+//Bit 31:10, reserved
+//Bit 9:8, reg_top_debug_sel unsigned, default = 0, top debug select
+//Bit 7, reg_spdif_rx_en_force unsigned, default = 0, force spdif_rx_en to reg_spdif_rx_en_force_value
+//Bit 6, reg_spdif_rx_en_force_value unsigned, default = 0, value
+//Bit 5, reg_spdif_rx_sqen_force unsigned, default = 0, force spdif_rx_sqen to reg_spdif_rx_sqe
+//Bit 4, reg_spdif_rx_sqen_force_value unsigned, default = 0, value
+//Bit 3, reg_dmacrx_en_force unsigned, default = 0, force dmacrx_en to reg_dmacrx_en_force_value
+//Bit 2, reg_dmacrx_en_force_value unsigned, default = 0, value
+//Bit 1, reg_dmacrx_sqen_force unsigned, default = 0, force dmacrx_sqen to reg_dmacrx_sqen_force_value
+//Bit 0, reg_dmacrx_sqen_force_value unsigned, default = 0, value
+#define EARCRX_DMAC_INT_MASK ((0x0001 << 2) + 0xfe333e00)
+//Bit 31:30, reserved
+//Bit 29:0, reg_dmac_int_mask unsigned, default = 0, dmac int mask
+#define EARCRX_DMAC_INT_PENDING ((0x0002 << 2) + 0xfe333e00)
+//Bit 31:30, reserved
+//Bit 29:0, reg_dmac_int_mask unsigned, default = 0, dmac int pending,read only
+#define EARCRX_CMDC_INT_MASK ((0x0003 << 2) + 0xfe333e00)
+//Bit 31:16, reserved
+//Bit 15:0, reg_cmdc_int_mask unsigned, default = 0, cmdc int mask
+#define EARCRX_CMDC_INT_PENDING ((0x0004 << 2) + 0xfe333e00)
+//Bit 31:18, reserved
+//Bit 17:0, reg_cmdc_int_mask unsigned, default = 0, cmdc int pending,read only
+#define EARCRX_ANA_CTRL0 ((0x0005 << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_ANA_CTRL1 ((0x0006 << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_ANA_STAT0 ((0x0007 << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_PLL_CTRL0 ((0x0008 << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_PLL_CTRL1 ((0x0009 << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_PLL_CTRL2 ((0x000a << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_PLL_CTRL3 ((0x000b << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_PLL_STAT0 ((0x000c << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+//
+// Closing file: earcrx_top.h
+//
+//========================================================================
+// AUDIO RESAMPLEB - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe334000
+// -----------------------------------------------
+//
+// Reading file: RESAMPLEB.h
+//
+#define AUDIO_RSAMPB_CTRL0 ((0x0000 << 2) + 0xfe334000)
+//Bit 31:3 reserved
+//Bit 2 reg_lock_rst //unsigned , default =0;
+//Bit 1 reg_rsamp_rst //unsigned , default =0;
+//Bit 0 reg_sw_rst //unsigned , default =0;
+#define AUDIO_RSAMPB_CTRL1 ((0x0001 << 2) + 0xfe334000)
+//Bit 31:27 reserved //unsigned , default =0;
+//Bit 26 reg_watchdog_en //unsigned , default =0;
+//Bit 25 reg_rsamp_rst_sel //unsigned , default =0;
+//Bit 24 reg_module_bypas //unsigned , default =0;
+//Bit 23:18 reg_gclk_ctrl //unsigned , default =0;
+//Bit 17:13 reg_in_msb //unsigned , default =23;
+//Bit 12 reg_output_en //unsigned , default =0;
+//Bit 11 reg_rsamp_en //unsigned , default =0;
+//Bit 10 reg_filt_en //unsigned , default =0;
+//Bit 9 reg_post_en //unsigned , default =0;
+//Bit 8 reg_inp_mux_mode //unsigned , default =0;
+//Bit 7:4 reserved //unsigned , default =2;
+//Bit 3:0 reg_inp_mux //unsigned , default =0;
+#define AUDIO_RSAMPB_CTRL2 ((0x0002 << 2) + 0xfe334000)
+//Bit 31:30 reserved //unsigned , default =0;
+//Bit 29:24 reg_chx_size //unsigned , default =2;
+//Bit 23:18 reserved //unsigned , default =0;
+//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4
+//Bit 15:8 reg_filt_tap //unsigned , default =63;
+//Bit 7:0 reg_intp_tap //unsigned , default =63;
+#define AUDIO_RSAMPB_PHSINIT ((0x0003 << 2) + 0xfe334000)
+//Bit 31:28 reserved //unsigned , default = 0;
+//Bit 27:0 reg_init_phs //unsigned , default = 0;
+#define AUDIO_RSAMPB_PHSSTEP ((0x0004 << 2) + 0xfe334000)
+//Bit 31 reserved //unsigned , default = 0;
+//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000
+#define AUDIO_RSAMPB_SHIFT ((0x0005 << 2) + 0xfe334000)
+//Bit 31:24 reg_rsft_iir //unsigned , default = 23;
+//Bit 23:16 reg_rsft_blnd //unsigned , default = 21;
+//Bit 15:8 reg_rsft_sinc //unsigned , default = 31;
+//Bit 7:0 reg_rsft_aa //unsigned , default = 31;
+#define AUDIO_RSAMPB_ADJ_CTRL0 ((0x0006 << 2) + 0xfe334000)
+//Bit 31:3 reserved //unsigned
+//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0;
+//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0;
+//Bit 0 reg_rsamp_adj_en //unsigned , default = 0;
+#define AUDIO_RSAMPB_ADJ_CTRL1 ((0x0007 << 2) + 0xfe334000)
+//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8;
+//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768;
+#define AUDIO_RSAMPB_ADJ_SFT ((0x0008 << 2) + 0xfe334000)
+//Bit 31:30 reserved //unsigned , default = 0;
+//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0;
+//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9;
+//Bit 23:21 reserved //unsigned , default = 0;
+//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1;
+//Bit 15:13 reserved //unsigned , default = 0;
+//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6;
+//Bit 7:6 reserved //unsigned , default = 0;
+//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12;
+#define AUDIO_RSAMPB_ADJ_IDET_LEN ((0x0009 << 2) + 0xfe334000)
+//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000;
+#define AUDIO_RSAMPB_ADJ_FORCE ((0x000a << 2) + 0xfe334000)
+//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8;
+#define AUDIO_RSAMPB_ADJ_KI_FORCE ((0x000b << 2) + 0xfe334000)
+//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0;
+#define AUDIO_RSAMPB_WATCHDOG_THRD ((0x000c << 2) + 0xfe334000)
+//Bit 31:0 reg_watchdog_thrd //signed , default = 32'h1000;
+#define AUDIO_RSAMPB_RO_STATUS ((0x0010 << 2) + 0xfe334000)
+//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]}
+#define AUDIO_RSAMPB_RO_ADJ_FREQ ((0x0011 << 2) + 0xfe334000)
+//Bit 31:0 ro_rsamp_adj_freq
+#define AUDIO_RSAMPB_RO_ADJ_DIFF_BAK ((0x0012 << 2) + 0xfe334000)
+//Bit 31:0 ro_det_diff_bak
+#define AUDIO_RSAMPB_RO_ADJ_DIFF_DLT ((0x0013 << 2) + 0xfe334000)
+//Bit 31:0 ro_det_diff_dlt
+#define AUDIO_RSAMPB_RO_ADJ_PHS_ERR ((0x0014 << 2) + 0xfe334000)
+//Bit 31:0 ro_det_phase_err
+#define AUDIO_RSAMPB_RO_ADJ_KI_OUT ((0x0015 << 2) + 0xfe334000)
+//Bit 31:0 ro_rsamp_ki_out
+#define AUDIO_RSAMPB_RO_IN_CNT ((0x0016 << 2) + 0xfe334000)
+//Bit 31:0 ro_rsamp_in_cnt
+#define AUDIO_RSAMPB_RO_OUT_CNT ((0x0017 << 2) + 0xfe334000)
+//Bit 31:0 ro_rsamp_out_cnt
+#define AUDIO_RSAMPB_RO_ADJ_PHS_ERR_VAR ((0x0018 << 2) + 0xfe334000)
+//Bit 31:0 ro_det_phase_err_var
+#define AUDIO_RSAMPB_POST_COEF0 ((0x0020 << 2) + 0xfe334000)
+//Bit 31:0 reg_post_coef0 //signed , default = 0;
+#define AUDIO_RSAMPB_POST_COEF1 ((0x0021 << 2) + 0xfe334000)
+//Bit 31:0 reg_post_coef1 //signed , default = 0;
+#define AUDIO_RSAMPB_POST_COEF2 ((0x0022 << 2) + 0xfe334000)
+//Bit 31:0 reg_post_coef2 //signed , default = 0;
+#define AUDIO_RSAMPB_POST_COEF3 ((0x0023 << 2) + 0xfe334000)
+//Bit 31:0 reg_post_coef3 //signed , default = 0;
+#define AUDIO_RSAMPB_POST_COEF4 ((0x0024 << 2) + 0xfe334000)
+//Bit 31:0 reg_post_coef4 //signed , default = 0;
+#define AUDIO_RSAMPB_AA_COEF_ADDR ((0x0030 << 2) + 0xfe334000)
+//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0;
+#define AUDIO_RSAMPB_AA_COEF_DATA ((0x0031 << 2) + 0xfe334000)
+//Bit 31:0 reg_aa_coef_data //signed , default = 0;
+#define AUDIO_RSAMPB_SINC_COEF_ADDR ((0x0040 << 2) + 0xfe334000)
+//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0;
+#define AUDIO_RSAMPB_SINC_COEF_DATA ((0x0041 << 2) + 0xfe334000)
+//Bit 31:0 reg_sinc_coef_data //signed , default = 0;
+//
+// Closing file: RESAMPLEB.h
+//
+//
+// Closing file: REG_LIST_AUDIO_RTL.h
+//
+//
+// Reading file: REG_LIST_DSP_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//========================================================================
+// DSPA - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe340000
+// -----------------------------------------------
+#define DSP_CFG0 ((0x0000 << 2) + 0xfe340000)
+#define DSP_CFG1 ((0x0001 << 2) + 0xfe340000)
+#define DSP_CFG2 ((0x0002 << 2) + 0xfe340000)
+#define DSP_IMPWIRE ((0x0003 << 2) + 0xfe340000)
+#define DSP_RESET_VEC ((0x0004 << 2) + 0xfe340000)
+#define DSP_SEC_CFG0 ((0x0006 << 2) + 0xfe340000)
+#define DSP_SEC_CFG1 ((0x0007 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL0 ((0x0010 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL1 ((0x0011 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL2 ((0x0012 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL3 ((0x0013 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL4 ((0x0014 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL5 ((0x0015 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL6 ((0x0016 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL7 ((0x0017 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL8 ((0x0018 << 2) + 0xfe340000)
+#define DSP_IRQ_STS ((0x001f << 2) + 0xfe340000)
+#define DSP_REMAP0 ((0x0020 << 2) + 0xfe340000)
+#define DSP_REMAP1 ((0x0021 << 2) + 0xfe340000)
+#define DSP_REMAP2 ((0x0022 << 2) + 0xfe340000)
+#define DSP_STS0 ((0x0040 << 2) + 0xfe340000)
+#define DSP_STS1 ((0x0041 << 2) + 0xfe340000)
+#define DSP_STS2 ((0x0042 << 2) + 0xfe340000)
+#define DSP_STS3 ((0x0043 << 2) + 0xfe340000)
+#define DSP_STS4 ((0x0044 << 2) + 0xfe340000)
+#define DSP_STS5 ((0x0045 << 2) + 0xfe340000)
+#define DSP_QIF_CTRL ((0x0080 << 2) + 0xfe340000)
+#define DSP_QIF_STS ((0x0081 << 2) + 0xfe340000)
+#define DSP_WRFIFO_TOCPUA ((0x0082 << 2) + 0xfe340000)
+#define DSP_WRFIFO_TOCPUB ((0x0083 << 2) + 0xfe340000)
+#define DSP_WRFIFO_TODSP ((0x0084 << 2) + 0xfe340000)
+#define DSP_RDFIFO_FRCPUA ((0x0088 << 2) + 0xfe340000)
+#define DSP_RDFIFO_FRCPUB ((0x0089 << 2) + 0xfe340000)
+#define DSP_RDFIFO_FRDSP ((0x008a << 2) + 0xfe340000)
+//========================================================================
+// DSPB - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe350000
+// -----------------------------------------------
+#define DSPB_CFG0 ((0x0000 << 2) + 0xfe350000)
+#define DSPB_CFG1 ((0x0001 << 2) + 0xfe350000)
+#define DSPB_CFG2 ((0x0002 << 2) + 0xfe350000)
+#define DSPB_IMPWIRE ((0x0003 << 2) + 0xfe350000)
+#define DSPB_RESET_VEC ((0x0004 << 2) + 0xfe350000)
+#define DSPB_SEC_CFG0 ((0x0006 << 2) + 0xfe350000)
+#define DSPB_SEC_CFG1 ((0x0007 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL0 ((0x0010 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL1 ((0x0011 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL2 ((0x0012 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL3 ((0x0013 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL4 ((0x0014 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL5 ((0x0015 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL6 ((0x0016 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL7 ((0x0017 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL8 ((0x0018 << 2) + 0xfe350000)
+#define DSPB_IRQ_STS ((0x001f << 2) + 0xfe350000)
+#define DSPB_REMAP0 ((0x0020 << 2) + 0xfe350000)
+#define DSPB_REMAP1 ((0x0021 << 2) + 0xfe350000)
+#define DSPB_REMAP2 ((0x0022 << 2) + 0xfe350000)
+#define DSPB_STS0 ((0x0040 << 2) + 0xfe350000)
+#define DSPB_STS1 ((0x0041 << 2) + 0xfe350000)
+#define DSPB_STS2 ((0x0042 << 2) + 0xfe350000)
+#define DSPB_STS3 ((0x0043 << 2) + 0xfe350000)
+#define DSPB_STS4 ((0x0044 << 2) + 0xfe350000)
+#define DSPB_STS5 ((0x0045 << 2) + 0xfe350000)
+#define DSPB_QIF_CTRL ((0x0080 << 2) + 0xfe350000)
+#define DSPB_QIF_STS ((0x0081 << 2) + 0xfe350000)
+#define DSPB_WRFIFO_TOCPUA ((0x0082 << 2) + 0xfe350000)
+#define DSPB_WRFIFO_TOCPUB ((0x0083 << 2) + 0xfe350000)
+#define DSPB_WRFIFO_TODSP ((0x0084 << 2) + 0xfe350000)
+#define DSPB_RDFIFO_FRCPUA ((0x0088 << 2) + 0xfe350000)
+#define DSPB_RDFIFO_FRCPUB ((0x0089 << 2) + 0xfe350000)
+#define DSPB_RDFIFO_FRDSP ((0x008a << 2) + 0xfe350000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: REG_LIST_DSP_RTL.h
+//
+//
+// Reading file: REG_LIST_SECURITY_RTL.h
+//
+//
+//***************************************************************************
+// Title: REG_LIST_SECURITY_RTL.h
+//
+// Author: shan.luan
+//
+// Created: 23:09:44 28/02/2020
+//
+// Description:
+//
+// Note:
+//
+// History:
+//
+//***************************************************************************
+//========================================================================
+// TS_DEMUX_REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe444000
+// -----------------------------------------------
+#define RCH_READY_CHANNEL_0 ((0x0000 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_1 ((0x0008 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_2 ((0x0010 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_3 ((0x0018 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_4 ((0x0020 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_5 ((0x0028 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_6 ((0x0030 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_7 ((0x0038 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_8 ((0x0040 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_9 ((0x0048 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_10 ((0x0050 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_11 ((0x0058 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_12 ((0x0060 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_13 ((0x0068 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_14 ((0x0070 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_15 ((0x0078 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_16 ((0x0080 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_17 ((0x0088 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_18 ((0x0090 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_19 ((0x0098 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_20 ((0x00a0 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_21 ((0x00a8 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_22 ((0x00b0 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_23 ((0x00b8 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_24 ((0x00c0 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_25 ((0x00c8 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_26 ((0x00d0 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_27 ((0x00d8 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_28 ((0x00e0 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_29 ((0x00e8 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_30 ((0x00f0 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_31 ((0x00f8 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_0 ((0x0001 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_1 ((0x0009 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_2 ((0x0011 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_3 ((0x0019 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_4 ((0x0021 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_5 ((0x0029 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_6 ((0x0031 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_7 ((0x0039 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_8 ((0x0041 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_9 ((0x0049 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_10 ((0x0051 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_11 ((0x0059 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_12 ((0x0061 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_13 ((0x0069 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_14 ((0x0071 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_15 ((0x0079 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_16 ((0x0081 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_17 ((0x0089 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_18 ((0x0091 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_19 ((0x0099 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_20 ((0x00a1 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_21 ((0x00a9 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_22 ((0x00b1 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_23 ((0x00b9 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_24 ((0x00c1 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_25 ((0x00c9 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_26 ((0x00d1 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_27 ((0x00d9 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_28 ((0x00e1 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_29 ((0x00e9 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_30 ((0x00f1 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_31 ((0x00f9 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_0 ((0x0002 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_1 ((0x000a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_2 ((0x0012 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_3 ((0x001a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_4 ((0x0022 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_5 ((0x002a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_6 ((0x0032 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_7 ((0x003a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_8 ((0x0042 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_9 ((0x004a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_10 ((0x0052 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_11 ((0x005a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_12 ((0x0062 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_13 ((0x006a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_14 ((0x0072 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_15 ((0x007a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_16 ((0x0082 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_17 ((0x008a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_18 ((0x0092 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_19 ((0x009a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_20 ((0x00a2 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_21 ((0x00aa << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_22 ((0x00b2 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_23 ((0x00ba << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_24 ((0x00c2 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_25 ((0x00ca << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_26 ((0x00d2 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_27 ((0x00da << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_28 ((0x00e2 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_29 ((0x00ea << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_30 ((0x00f2 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_31 ((0x00fa << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_0 ((0x0003 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_1 ((0x000b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_2 ((0x0013 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_3 ((0x001b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_4 ((0x0023 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_5 ((0x002b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_6 ((0x0033 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_7 ((0x003b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_8 ((0x0043 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_9 ((0x004b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_10 ((0x0053 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_11 ((0x005b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_12 ((0x0063 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_13 ((0x006b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_14 ((0x0073 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_15 ((0x007b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_16 ((0x0083 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_17 ((0x008b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_18 ((0x0093 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_19 ((0x009b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_20 ((0x00a3 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_21 ((0x00ab << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_22 ((0x00b3 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_23 ((0x00bb << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_24 ((0x00c3 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_25 ((0x00cb << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_26 ((0x00d3 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_27 ((0x00db << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_28 ((0x00e3 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_29 ((0x00eb << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_30 ((0x00f3 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_31 ((0x00fb << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_0 ((0x0004 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_1 ((0x000c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_2 ((0x0014 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_3 ((0x001c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_4 ((0x0024 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_5 ((0x002c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_6 ((0x0034 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_7 ((0x003c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_8 ((0x0044 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_9 ((0x004c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_10 ((0x0054 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_11 ((0x005c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_12 ((0x0064 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_13 ((0x006c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_14 ((0x0074 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_15 ((0x007c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_16 ((0x0084 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_17 ((0x008c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_18 ((0x0094 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_19 ((0x009c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_20 ((0x00a4 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_21 ((0x00ac << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_22 ((0x00b4 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_23 ((0x00bc << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_24 ((0x00c4 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_25 ((0x00cc << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_26 ((0x00d4 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_27 ((0x00dc << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_28 ((0x00e4 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_29 ((0x00ec << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_30 ((0x00f4 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_31 ((0x00fc << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_0 ((0x0005 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_1 ((0x000d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_2 ((0x0015 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_3 ((0x001d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_4 ((0x0025 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_5 ((0x002d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_6 ((0x0035 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_7 ((0x003d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_8 ((0x0045 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_9 ((0x004d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_10 ((0x0055 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_11 ((0x005d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_12 ((0x0065 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_13 ((0x006d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_14 ((0x0075 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_15 ((0x007d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_16 ((0x0085 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_17 ((0x008d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_18 ((0x0095 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_19 ((0x009d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_20 ((0x00a5 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_21 ((0x00ad << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_22 ((0x00b5 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_23 ((0x00bd << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_24 ((0x00c5 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_25 ((0x00cd << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_26 ((0x00d5 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_27 ((0x00dd << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_28 ((0x00e5 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_29 ((0x00ed << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_30 ((0x00f5 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_31 ((0x00fd << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_0 ((0x0006 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_1 ((0x000e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_2 ((0x0016 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_3 ((0x001e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_4 ((0x0026 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_5 ((0x002e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_6 ((0x0036 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_7 ((0x003e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_8 ((0x0046 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_9 ((0x004e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_10 ((0x0056 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_11 ((0x005e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_12 ((0x0066 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_13 ((0x006e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_14 ((0x0076 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_15 ((0x007e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_16 ((0x0086 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_17 ((0x008e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_18 ((0x0096 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_19 ((0x009e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_20 ((0x00a6 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_21 ((0x00ae << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_22 ((0x00b6 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_23 ((0x00be << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_24 ((0x00c6 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_25 ((0x00ce << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_26 ((0x00d6 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_27 ((0x00de << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_28 ((0x00e6 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_29 ((0x00ee << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_30 ((0x00f6 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_31 ((0x00fe << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_0 ((0x0007 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_1 ((0x000f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_2 ((0x0017 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_3 ((0x001f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_4 ((0x0027 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_5 ((0x002f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_6 ((0x0037 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_7 ((0x003f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_8 ((0x0047 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_9 ((0x004f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_10 ((0x0057 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_11 ((0x005f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_12 ((0x0067 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_13 ((0x006f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_14 ((0x0077 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_15 ((0x007f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_16 ((0x0087 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_17 ((0x008f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_18 ((0x0097 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_19 ((0x009f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_20 ((0x00a7 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_21 ((0x00af << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_22 ((0x00b7 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_23 ((0x00bf << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_24 ((0x00c7 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_25 ((0x00cf << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_26 ((0x00d7 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_27 ((0x00df << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_28 ((0x00e7 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_29 ((0x00ef << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_30 ((0x00f7 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_31 ((0x00ff << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_0 ((0x0400 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_1 ((0x0408 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_2 ((0x0410 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_3 ((0x0418 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_4 ((0x0420 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_5 ((0x0428 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_6 ((0x0430 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_7 ((0x0438 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_8 ((0x0440 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_9 ((0x0448 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_10 ((0x0450 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_11 ((0x0458 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_12 ((0x0460 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_13 ((0x0468 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_14 ((0x0470 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_15 ((0x0478 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_16 ((0x0480 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_17 ((0x0488 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_18 ((0x0490 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_19 ((0x0498 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_20 ((0x04a0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_21 ((0x04a8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_22 ((0x04b0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_23 ((0x04b8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_24 ((0x04c0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_25 ((0x04c8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_26 ((0x04d0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_27 ((0x04d8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_28 ((0x04e0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_29 ((0x04e8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_30 ((0x04f0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_31 ((0x04f8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_32 ((0x0500 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_33 ((0x0508 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_34 ((0x0510 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_35 ((0x0518 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_36 ((0x0520 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_37 ((0x0528 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_38 ((0x0530 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_39 ((0x0538 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_40 ((0x0540 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_41 ((0x0548 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_42 ((0x0550 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_43 ((0x0558 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_44 ((0x0560 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_45 ((0x0568 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_46 ((0x0570 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_47 ((0x0578 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_48 ((0x0580 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_49 ((0x0588 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_50 ((0x0590 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_51 ((0x0598 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_52 ((0x05a0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_53 ((0x05a8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_54 ((0x05b0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_55 ((0x05b8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_56 ((0x05c0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_57 ((0x05c8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_58 ((0x05d0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_59 ((0x05d8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_60 ((0x05e0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_61 ((0x05e8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_62 ((0x05f0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_63 ((0x05f8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_64 ((0x0600 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_65 ((0x0608 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_66 ((0x0610 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_67 ((0x0618 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_68 ((0x0620 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_69 ((0x0628 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_70 ((0x0630 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_71 ((0x0638 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_72 ((0x0640 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_73 ((0x0648 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_74 ((0x0650 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_75 ((0x0658 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_76 ((0x0660 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_77 ((0x0668 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_78 ((0x0670 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_79 ((0x0678 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_80 ((0x0680 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_81 ((0x0688 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_82 ((0x0690 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_83 ((0x0698 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_84 ((0x06a0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_85 ((0x06a8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_86 ((0x06b0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_87 ((0x06b8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_88 ((0x06c0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_89 ((0x06c8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_90 ((0x06d0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_91 ((0x06d8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_92 ((0x06e0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_93 ((0x06e8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_94 ((0x06f0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_95 ((0x06f8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_96 ((0x0700 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_97 ((0x0708 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_98 ((0x0710 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_99 ((0x0718 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_100 ((0x0720 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_101 ((0x0728 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_102 ((0x0730 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_103 ((0x0738 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_104 ((0x0740 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_105 ((0x0748 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_106 ((0x0750 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_107 ((0x0758 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_108 ((0x0760 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_109 ((0x0768 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_110 ((0x0770 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_111 ((0x0778 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_112 ((0x0780 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_113 ((0x0788 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_114 ((0x0790 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_115 ((0x0798 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_116 ((0x07a0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_117 ((0x07a8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_118 ((0x07b0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_119 ((0x07b8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_120 ((0x07c0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_121 ((0x07c8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_122 ((0x07d0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_123 ((0x07d8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_124 ((0x07e0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_125 ((0x07e8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_126 ((0x07f0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_127 ((0x07f8 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_0 ((0x0401 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_1 ((0x0409 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_2 ((0x0411 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_3 ((0x0419 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_4 ((0x0421 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_5 ((0x0429 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_6 ((0x0431 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_7 ((0x0439 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_8 ((0x0441 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_9 ((0x0449 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_10 ((0x0451 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_11 ((0x0459 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_12 ((0x0461 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_13 ((0x0469 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_14 ((0x0471 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_15 ((0x0479 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_16 ((0x0481 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_17 ((0x0489 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_18 ((0x0491 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_19 ((0x0499 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_20 ((0x04a1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_21 ((0x04a9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_22 ((0x04b1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_23 ((0x04b9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_24 ((0x04c1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_25 ((0x04c9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_26 ((0x04d1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_27 ((0x04d9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_28 ((0x04e1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_29 ((0x04e9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_30 ((0x04f1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_31 ((0x04f9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_32 ((0x0501 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_33 ((0x0509 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_34 ((0x0511 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_35 ((0x0519 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_36 ((0x0521 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_37 ((0x0529 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_38 ((0x0531 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_39 ((0x0539 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_40 ((0x0541 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_41 ((0x0549 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_42 ((0x0551 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_43 ((0x0559 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_44 ((0x0561 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_45 ((0x0569 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_46 ((0x0571 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_47 ((0x0579 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_48 ((0x0581 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_49 ((0x0589 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_50 ((0x0591 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_51 ((0x0599 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_52 ((0x05a1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_53 ((0x05a9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_54 ((0x05b1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_55 ((0x05b9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_56 ((0x05c1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_57 ((0x05c9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_58 ((0x05d1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_59 ((0x05d9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_60 ((0x05e1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_61 ((0x05e9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_62 ((0x05f1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_63 ((0x05f9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_64 ((0x0601 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_65 ((0x0609 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_66 ((0x0611 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_67 ((0x0619 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_68 ((0x0621 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_69 ((0x0629 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_70 ((0x0631 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_71 ((0x0639 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_72 ((0x0641 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_73 ((0x0649 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_74 ((0x0651 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_75 ((0x0659 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_76 ((0x0661 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_77 ((0x0669 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_78 ((0x0671 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_79 ((0x0679 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_80 ((0x0681 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_81 ((0x0689 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_82 ((0x0691 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_83 ((0x0699 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_84 ((0x06a1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_85 ((0x06a9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_86 ((0x06b1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_87 ((0x06b9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_88 ((0x06c1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_89 ((0x06c9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_90 ((0x06d1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_91 ((0x06d9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_92 ((0x06e1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_93 ((0x06e9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_94 ((0x06f1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_95 ((0x06f9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_96 ((0x0701 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_97 ((0x0709 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_98 ((0x0711 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_99 ((0x0719 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_100 ((0x0721 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_101 ((0x0729 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_102 ((0x0731 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_103 ((0x0739 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_104 ((0x0741 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_105 ((0x0749 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_106 ((0x0751 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_107 ((0x0759 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_108 ((0x0761 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_109 ((0x0769 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_110 ((0x0771 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_111 ((0x0779 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_112 ((0x0781 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_113 ((0x0789 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_114 ((0x0791 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_115 ((0x0799 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_116 ((0x07a1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_117 ((0x07a9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_118 ((0x07b1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_119 ((0x07b9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_120 ((0x07c1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_121 ((0x07c9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_122 ((0x07d1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_123 ((0x07d9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_124 ((0x07e1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_125 ((0x07e9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_126 ((0x07f1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_127 ((0x07f9 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_0 ((0x0402 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_1 ((0x040a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_2 ((0x0412 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_3 ((0x041a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_4 ((0x0422 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_5 ((0x042a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_6 ((0x0432 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_7 ((0x043a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_8 ((0x0442 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_9 ((0x044a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_10 ((0x0452 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_11 ((0x045a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_12 ((0x0462 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_13 ((0x046a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_14 ((0x0472 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_15 ((0x047a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_16 ((0x0482 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_17 ((0x048a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_18 ((0x0492 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_19 ((0x049a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_20 ((0x04a2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_21 ((0x04aa << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_22 ((0x04b2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_23 ((0x04ba << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_24 ((0x04c2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_25 ((0x04ca << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_26 ((0x04d2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_27 ((0x04da << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_28 ((0x04e2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_29 ((0x04ea << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_30 ((0x04f2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_31 ((0x04fa << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_32 ((0x0502 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_33 ((0x050a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_34 ((0x0512 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_35 ((0x051a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_36 ((0x0522 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_37 ((0x052a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_38 ((0x0532 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_39 ((0x053a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_40 ((0x0542 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_41 ((0x054a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_42 ((0x0552 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_43 ((0x055a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_44 ((0x0562 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_45 ((0x056a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_46 ((0x0572 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_47 ((0x057a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_48 ((0x0582 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_49 ((0x058a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_50 ((0x0592 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_51 ((0x059a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_52 ((0x05a2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_53 ((0x05aa << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_54 ((0x05b2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_55 ((0x05ba << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_56 ((0x05c2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_57 ((0x05ca << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_58 ((0x05d2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_59 ((0x05da << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_60 ((0x05e2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_61 ((0x05ea << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_62 ((0x05f2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_63 ((0x05fa << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_64 ((0x0602 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_65 ((0x060a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_66 ((0x0612 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_67 ((0x061a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_68 ((0x0622 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_69 ((0x062a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_70 ((0x0632 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_71 ((0x063a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_72 ((0x0642 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_73 ((0x064a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_74 ((0x0652 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_75 ((0x065a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_76 ((0x0662 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_77 ((0x066a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_78 ((0x0672 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_79 ((0x067a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_80 ((0x0682 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_81 ((0x068a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_82 ((0x0692 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_83 ((0x069a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_84 ((0x06a2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_85 ((0x06aa << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_86 ((0x06b2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_87 ((0x06ba << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_88 ((0x06c2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_89 ((0x06ca << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_90 ((0x06d2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_91 ((0x06da << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_92 ((0x06e2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_93 ((0x06ea << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_94 ((0x06f2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_95 ((0x06fa << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_96 ((0x0702 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_97 ((0x070a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_98 ((0x0712 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_99 ((0x071a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_100 ((0x0722 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_101 ((0x072a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_102 ((0x0732 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_103 ((0x073a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_104 ((0x0742 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_105 ((0x074a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_106 ((0x0752 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_107 ((0x075a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_108 ((0x0762 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_109 ((0x076a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_110 ((0x0772 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_111 ((0x077a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_112 ((0x0782 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_113 ((0x078a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_114 ((0x0792 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_115 ((0x079a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_116 ((0x07a2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_117 ((0x07aa << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_118 ((0x07b2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_119 ((0x07ba << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_120 ((0x07c2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_121 ((0x07ca << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_122 ((0x07d2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_123 ((0x07da << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_124 ((0x07e2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_125 ((0x07ea << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_126 ((0x07f2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_127 ((0x07fa << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_0 ((0x0403 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_1 ((0x040b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_2 ((0x0413 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_3 ((0x041b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_4 ((0x0423 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_5 ((0x042b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_6 ((0x0433 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_7 ((0x043b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_8 ((0x0443 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_9 ((0x044b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_10 ((0x0453 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_11 ((0x045b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_12 ((0x0463 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_13 ((0x046b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_14 ((0x0473 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_15 ((0x047b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_16 ((0x0483 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_17 ((0x048b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_18 ((0x0493 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_19 ((0x049b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_20 ((0x04a3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_21 ((0x04ab << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_22 ((0x04b3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_23 ((0x04bb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_24 ((0x04c3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_25 ((0x04cb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_26 ((0x04d3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_27 ((0x04db << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_28 ((0x04e3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_29 ((0x04eb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_30 ((0x04f3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_31 ((0x04fb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_32 ((0x0503 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_33 ((0x050b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_34 ((0x0513 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_35 ((0x051b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_36 ((0x0523 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_37 ((0x052b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_38 ((0x0533 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_39 ((0x053b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_40 ((0x0543 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_41 ((0x054b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_42 ((0x0553 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_43 ((0x055b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_44 ((0x0563 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_45 ((0x056b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_46 ((0x0573 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_47 ((0x057b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_48 ((0x0583 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_49 ((0x058b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_50 ((0x0593 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_51 ((0x059b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_52 ((0x05a3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_53 ((0x05ab << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_54 ((0x05b3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_55 ((0x05bb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_56 ((0x05c3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_57 ((0x05cb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_58 ((0x05d3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_59 ((0x05db << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_60 ((0x05e3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_61 ((0x05eb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_62 ((0x05f3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_63 ((0x05fb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_64 ((0x0603 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_65 ((0x060b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_66 ((0x0613 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_67 ((0x061b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_68 ((0x0623 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_69 ((0x062b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_70 ((0x0633 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_71 ((0x063b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_72 ((0x0643 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_73 ((0x064b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_74 ((0x0653 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_75 ((0x065b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_76 ((0x0663 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_77 ((0x066b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_78 ((0x0673 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_79 ((0x067b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_80 ((0x0683 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_81 ((0x068b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_82 ((0x0693 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_83 ((0x069b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_84 ((0x06a3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_85 ((0x06ab << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_86 ((0x06b3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_87 ((0x06bb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_88 ((0x06c3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_89 ((0x06cb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_90 ((0x06d3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_91 ((0x06db << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_92 ((0x06e3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_93 ((0x06eb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_94 ((0x06f3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_95 ((0x06fb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_96 ((0x0703 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_97 ((0x070b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_98 ((0x0713 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_99 ((0x071b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_100 ((0x0723 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_101 ((0x072b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_102 ((0x0733 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_103 ((0x073b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_104 ((0x0743 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_105 ((0x074b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_106 ((0x0753 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_107 ((0x075b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_108 ((0x0763 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_109 ((0x076b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_110 ((0x0773 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_111 ((0x077b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_112 ((0x0783 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_113 ((0x078b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_114 ((0x0793 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_115 ((0x079b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_116 ((0x07a3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_117 ((0x07ab << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_118 ((0x07b3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_119 ((0x07bb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_120 ((0x07c3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_121 ((0x07cb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_122 ((0x07d3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_123 ((0x07db << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_124 ((0x07e3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_125 ((0x07eb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_126 ((0x07f3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_127 ((0x07fb << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_0 ((0x0404 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_1 ((0x040c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_2 ((0x0414 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_3 ((0x041c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_4 ((0x0424 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_5 ((0x042c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_6 ((0x0434 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_7 ((0x043c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_8 ((0x0444 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_9 ((0x044c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_10 ((0x0454 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_11 ((0x045c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_12 ((0x0464 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_13 ((0x046c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_14 ((0x0474 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_15 ((0x047c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_16 ((0x0484 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_17 ((0x048c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_18 ((0x0494 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_19 ((0x049c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_20 ((0x04a4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_21 ((0x04ac << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_22 ((0x04b4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_23 ((0x04bc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_24 ((0x04c4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_25 ((0x04cc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_26 ((0x04d4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_27 ((0x04dc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_28 ((0x04e4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_29 ((0x04ec << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_30 ((0x04f4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_31 ((0x04fc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_32 ((0x0504 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_33 ((0x050c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_34 ((0x0514 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_35 ((0x051c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_36 ((0x0524 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_37 ((0x052c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_38 ((0x0534 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_39 ((0x053c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_40 ((0x0544 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_41 ((0x054c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_42 ((0x0554 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_43 ((0x055c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_44 ((0x0564 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_45 ((0x056c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_46 ((0x0574 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_47 ((0x057c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_48 ((0x0584 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_49 ((0x058c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_50 ((0x0594 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_51 ((0x059c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_52 ((0x05a4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_53 ((0x05ac << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_54 ((0x05b4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_55 ((0x05bc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_56 ((0x05c4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_57 ((0x05cc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_58 ((0x05d4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_59 ((0x05dc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_60 ((0x05e4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_61 ((0x05ec << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_62 ((0x05f4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_63 ((0x05fc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_64 ((0x0604 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_65 ((0x060c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_66 ((0x0614 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_67 ((0x061c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_68 ((0x0624 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_69 ((0x062c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_70 ((0x0634 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_71 ((0x063c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_72 ((0x0644 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_73 ((0x064c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_74 ((0x0654 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_75 ((0x065c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_76 ((0x0664 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_77 ((0x066c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_78 ((0x0674 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_79 ((0x067c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_80 ((0x0684 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_81 ((0x068c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_82 ((0x0694 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_83 ((0x069c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_84 ((0x06a4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_85 ((0x06ac << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_86 ((0x06b4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_87 ((0x06bc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_88 ((0x06c4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_89 ((0x06cc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_90 ((0x06d4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_91 ((0x06dc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_92 ((0x06e4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_93 ((0x06ec << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_94 ((0x06f4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_95 ((0x06fc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_96 ((0x0704 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_97 ((0x070c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_98 ((0x0714 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_99 ((0x071c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_100 ((0x0724 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_101 ((0x072c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_102 ((0x0734 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_103 ((0x073c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_104 ((0x0744 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_105 ((0x074c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_106 ((0x0754 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_107 ((0x075c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_108 ((0x0764 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_109 ((0x076c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_110 ((0x0774 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_111 ((0x077c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_112 ((0x0784 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_113 ((0x078c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_114 ((0x0794 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_115 ((0x079c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_116 ((0x07a4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_117 ((0x07ac << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_118 ((0x07b4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_119 ((0x07bc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_120 ((0x07c4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_121 ((0x07cc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_122 ((0x07d4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_123 ((0x07dc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_124 ((0x07e4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_125 ((0x07ec << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_126 ((0x07f4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_127 ((0x07fc << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_0 ((0x0405 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_1 ((0x040d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_2 ((0x0415 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_3 ((0x041d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_4 ((0x0425 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_5 ((0x042d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_6 ((0x0435 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_7 ((0x043d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_8 ((0x0445 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_9 ((0x044d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_10 ((0x0455 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_11 ((0x045d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_12 ((0x0465 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_13 ((0x046d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_14 ((0x0475 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_15 ((0x047d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_16 ((0x0485 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_17 ((0x048d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_18 ((0x0495 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_19 ((0x049d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_20 ((0x04a5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_21 ((0x04ad << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_22 ((0x04b5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_23 ((0x04bd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_24 ((0x04c5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_25 ((0x04cd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_26 ((0x04d5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_27 ((0x04dd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_28 ((0x04e5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_29 ((0x04ed << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_30 ((0x04f5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_31 ((0x04fd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_32 ((0x0505 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_33 ((0x050d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_34 ((0x0515 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_35 ((0x051d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_36 ((0x0525 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_37 ((0x052d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_38 ((0x0535 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_39 ((0x053d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_40 ((0x0545 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_41 ((0x054d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_42 ((0x0555 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_43 ((0x055d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_44 ((0x0565 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_45 ((0x056d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_46 ((0x0575 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_47 ((0x057d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_48 ((0x0585 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_49 ((0x058d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_50 ((0x0595 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_51 ((0x059d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_52 ((0x05a5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_53 ((0x05ad << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_54 ((0x05b5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_55 ((0x05bd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_56 ((0x05c5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_57 ((0x05cd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_58 ((0x05d5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_59 ((0x05dd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_60 ((0x05e5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_61 ((0x05ed << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_62 ((0x05f5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_63 ((0x05fd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_64 ((0x0605 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_65 ((0x060d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_66 ((0x0615 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_67 ((0x061d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_68 ((0x0625 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_69 ((0x062d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_70 ((0x0635 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_71 ((0x063d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_72 ((0x0645 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_73 ((0x064d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_74 ((0x0655 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_75 ((0x065d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_76 ((0x0665 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_77 ((0x066d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_78 ((0x0675 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_79 ((0x067d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_80 ((0x0685 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_81 ((0x068d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_82 ((0x0695 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_83 ((0x069d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_84 ((0x06a5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_85 ((0x06ad << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_86 ((0x06b5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_87 ((0x06bd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_88 ((0x06c5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_89 ((0x06cd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_90 ((0x06d5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_91 ((0x06dd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_92 ((0x06e5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_93 ((0x06ed << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_94 ((0x06f5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_95 ((0x06fd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_96 ((0x0705 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_97 ((0x070d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_98 ((0x0715 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_99 ((0x071d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_100 ((0x0725 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_101 ((0x072d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_102 ((0x0735 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_103 ((0x073d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_104 ((0x0745 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_105 ((0x074d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_106 ((0x0755 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_107 ((0x075d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_108 ((0x0765 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_109 ((0x076d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_110 ((0x0775 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_111 ((0x077d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_112 ((0x0785 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_113 ((0x078d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_114 ((0x0795 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_115 ((0x079d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_116 ((0x07a5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_117 ((0x07ad << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_118 ((0x07b5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_119 ((0x07bd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_120 ((0x07c5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_121 ((0x07cd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_122 ((0x07d5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_123 ((0x07dd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_124 ((0x07e5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_125 ((0x07ed << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_126 ((0x07f5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_127 ((0x07fd << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_0 ((0x0406 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_1 ((0x040e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_2 ((0x0416 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_3 ((0x041e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_4 ((0x0426 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_5 ((0x042e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_6 ((0x0436 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_7 ((0x043e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_8 ((0x0446 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_9 ((0x044e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_10 ((0x0456 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_11 ((0x045e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_12 ((0x0466 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_13 ((0x046e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_14 ((0x0476 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_15 ((0x047e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_16 ((0x0486 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_17 ((0x048e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_18 ((0x0496 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_19 ((0x049e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_20 ((0x04a6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_21 ((0x04ae << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_22 ((0x04b6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_23 ((0x04be << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_24 ((0x04c6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_25 ((0x04ce << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_26 ((0x04d6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_27 ((0x04de << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_28 ((0x04e6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_29 ((0x04ee << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_30 ((0x04f6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_31 ((0x04fe << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_32 ((0x0506 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_33 ((0x050e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_34 ((0x0516 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_35 ((0x051e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_36 ((0x0526 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_37 ((0x052e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_38 ((0x0536 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_39 ((0x053e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_40 ((0x0546 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_41 ((0x054e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_42 ((0x0556 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_43 ((0x055e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_44 ((0x0566 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_45 ((0x056e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_46 ((0x0576 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_47 ((0x057e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_48 ((0x0586 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_49 ((0x058e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_50 ((0x0596 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_51 ((0x059e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_52 ((0x05a6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_53 ((0x05ae << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_54 ((0x05b6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_55 ((0x05be << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_56 ((0x05c6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_57 ((0x05ce << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_58 ((0x05d6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_59 ((0x05de << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_60 ((0x05e6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_61 ((0x05ee << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_62 ((0x05f6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_63 ((0x05fe << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_64 ((0x0606 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_65 ((0x060e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_66 ((0x0616 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_67 ((0x061e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_68 ((0x0626 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_69 ((0x062e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_70 ((0x0636 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_71 ((0x063e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_72 ((0x0646 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_73 ((0x064e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_74 ((0x0656 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_75 ((0x065e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_76 ((0x0666 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_77 ((0x066e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_78 ((0x0676 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_79 ((0x067e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_80 ((0x0686 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_81 ((0x068e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_82 ((0x0696 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_83 ((0x069e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_84 ((0x06a6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_85 ((0x06ae << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_86 ((0x06b6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_87 ((0x06be << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_88 ((0x06c6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_89 ((0x06ce << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_90 ((0x06d6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_91 ((0x06de << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_92 ((0x06e6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_93 ((0x06ee << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_94 ((0x06f6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_95 ((0x06fe << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_96 ((0x0706 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_97 ((0x070e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_98 ((0x0716 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_99 ((0x071e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_100 ((0x0726 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_101 ((0x072e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_102 ((0x0736 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_103 ((0x073e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_104 ((0x0746 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_105 ((0x074e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_106 ((0x0756 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_107 ((0x075e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_108 ((0x0766 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_109 ((0x076e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_110 ((0x0776 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_111 ((0x077e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_112 ((0x0786 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_113 ((0x078e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_114 ((0x0796 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_115 ((0x079e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_116 ((0x07a6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_117 ((0x07ae << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_118 ((0x07b6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_119 ((0x07be << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_120 ((0x07c6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_121 ((0x07ce << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_122 ((0x07d6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_123 ((0x07de << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_124 ((0x07e6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_125 ((0x07ee << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_126 ((0x07f6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_127 ((0x07fe << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_0 ((0x0407 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_1 ((0x040f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_2 ((0x0417 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_3 ((0x041f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_4 ((0x0427 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_5 ((0x042f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_6 ((0x0437 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_7 ((0x043f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_8 ((0x0447 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_9 ((0x044f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_10 ((0x0457 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_11 ((0x045f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_12 ((0x0467 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_13 ((0x046f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_14 ((0x0477 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_15 ((0x047f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_16 ((0x0487 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_17 ((0x048f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_18 ((0x0497 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_19 ((0x049f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_20 ((0x04a7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_21 ((0x04af << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_22 ((0x04b7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_23 ((0x04bf << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_24 ((0x04c7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_25 ((0x04cf << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_26 ((0x04d7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_27 ((0x04df << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_28 ((0x04e7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_29 ((0x04ef << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_30 ((0x04f7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_31 ((0x04ff << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_32 ((0x0507 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_33 ((0x050f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_34 ((0x0517 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_35 ((0x051f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_36 ((0x0527 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_37 ((0x052f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_38 ((0x0537 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_39 ((0x053f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_40 ((0x0547 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_41 ((0x054f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_42 ((0x0557 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_43 ((0x055f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_44 ((0x0567 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_45 ((0x056f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_46 ((0x0577 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_47 ((0x057f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_48 ((0x0587 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_49 ((0x058f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_50 ((0x0597 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_51 ((0x059f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_52 ((0x05a7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_53 ((0x05af << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_54 ((0x05b7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_55 ((0x05bf << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_56 ((0x05c7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_57 ((0x05cf << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_58 ((0x05d7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_59 ((0x05df << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_60 ((0x05e7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_61 ((0x05ef << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_62 ((0x05f7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_63 ((0x05ff << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_64 ((0x0607 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_65 ((0x060f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_66 ((0x0617 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_67 ((0x061f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_68 ((0x0627 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_69 ((0x062f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_70 ((0x0637 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_71 ((0x063f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_72 ((0x0647 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_73 ((0x064f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_74 ((0x0657 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_75 ((0x065f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_76 ((0x0667 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_77 ((0x066f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_78 ((0x0677 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_79 ((0x067f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_80 ((0x0687 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_81 ((0x068f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_82 ((0x0697 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_83 ((0x069f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_84 ((0x06a7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_85 ((0x06af << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_86 ((0x06b7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_87 ((0x06bf << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_88 ((0x06c7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_89 ((0x06cf << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_90 ((0x06d7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_91 ((0x06df << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_92 ((0x06e7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_93 ((0x06ef << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_94 ((0x06f7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_95 ((0x06ff << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_96 ((0x0707 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_97 ((0x070f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_98 ((0x0717 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_99 ((0x071f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_100 ((0x0727 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_101 ((0x072f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_102 ((0x0737 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_103 ((0x073f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_104 ((0x0747 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_105 ((0x074f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_106 ((0x0757 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_107 ((0x075f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_108 ((0x0767 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_109 ((0x076f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_110 ((0x0777 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_111 ((0x077f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_112 ((0x0787 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_113 ((0x078f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_114 ((0x0797 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_115 ((0x079f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_116 ((0x07a7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_117 ((0x07af << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_118 ((0x07b7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_119 ((0x07bf << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_120 ((0x07c7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_121 ((0x07cf << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_122 ((0x07d7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_123 ((0x07df << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_124 ((0x07e7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_125 ((0x07ef << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_126 ((0x07f7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_127 ((0x07ff << 2) + 0xfe444000)
+#define DMX_RDMA_INT_MASK ((0x0800 << 2) + 0xfe444000)
+#define DMX_WDMA_INT_MASK_0 ((0x0801 << 2) + 0xfe444000)
+#define DMX_WDMA_INT_MASK_1 ((0x0802 << 2) + 0xfe444000)
+#define DMX_WDMA_INT_MASK_2 ((0x0803 << 2) + 0xfe444000)
+#define DMX_WDMA_INT_MASK_3 ((0x0804 << 2) + 0xfe444000)
+#define DMX_CLEAN_W_BATCH_0 ((0x0805 << 2) + 0xfe444000)
+#define DMX_CLEAN_W_BATCH_1 ((0x0806 << 2) + 0xfe444000)
+#define DMX_CLEAN_W_BATCH_2 ((0x0807 << 2) + 0xfe444000)
+#define DMX_CLEAN_W_BATCH_3 ((0x0808 << 2) + 0xfe444000)
+#define DMX_CLEAN_RDMA ((0x0809 << 2) + 0xfe444000)
+#define DMX_CLEAN_WDMA_0 ((0x080a << 2) + 0xfe444000)
+#define DMX_CLEAN_WDMA_1 ((0x080b << 2) + 0xfe444000)
+#define DMX_CLEAN_WDMA_2 ((0x080c << 2) + 0xfe444000)
+#define DMX_CLEAN_WDMA_3 ((0x080d << 2) + 0xfe444000)
+#define DMX_RDMA_ACTIVE ((0x080e << 2) + 0xfe444000)
+#define DMX_WDMA_ACTIVE_0 ((0x080f << 2) + 0xfe444000)
+#define DMX_WDMA_ACTIVE_1 ((0x0810 << 2) + 0xfe444000)
+#define DMX_WDMA_ACTIVE_2 ((0x0811 << 2) + 0xfe444000)
+#define DMX_WDMA_ACTIVE_3 ((0x0812 << 2) + 0xfe444000)
+#define DMX_DMA_RDONE ((0x0813 << 2) + 0xfe444000)
+#define DMX_DMA_WDONE_0 ((0x0814 << 2) + 0xfe444000)
+#define DMX_DMA_WDONE_1 ((0x0815 << 2) + 0xfe444000)
+#define DMX_DMA_WDONE_2 ((0x0816 << 2) + 0xfe444000)
+#define DMX_DMA_WDONE_3 ((0x0817 << 2) + 0xfe444000)
+#define DMX_RDES_ERR ((0x0818 << 2) + 0xfe444000)
+#define DMX_RDES_LEN_ERR ((0x0819 << 2) + 0xfe444000)
+#define DMX_WDES_ERR_0 ((0x081a << 2) + 0xfe444000)
+#define DMX_WDES_ERR_1 ((0x081b << 2) + 0xfe444000)
+#define DMX_WDES_ERR_2 ((0x081c << 2) + 0xfe444000)
+#define DMX_WDES_ERR_3 ((0x081d << 2) + 0xfe444000)
+#define DMX_DMA_BATCH_END_0 ((0x081e << 2) + 0xfe444000)
+#define DMX_DMA_BATCH_END_1 ((0x081f << 2) + 0xfe444000)
+#define DMX_DMA_BATCH_END_2 ((0x0820 << 2) + 0xfe444000)
+#define DMX_DMA_BATCH_END_3 ((0x0821 << 2) + 0xfe444000)
+#define DMX_WDES_EOC_DONE_0 ((0x0822 << 2) + 0xfe444000)
+#define DMX_WDES_EOC_DONE_1 ((0x0823 << 2) + 0xfe444000)
+#define DMX_WDES_EOC_DONE_2 ((0x0824 << 2) + 0xfe444000)
+#define DMX_WDES_EOC_DONE_3 ((0x0825 << 2) + 0xfe444000)
+#define DMX_WCH_RESP_ERR0 ((0x0826 << 2) + 0xfe444000)
+#define DMX_WCH_RESP_ERR1 ((0x0827 << 2) + 0xfe444000)
+#define DMX_WCH_RESP_ERR2 ((0x0828 << 2) + 0xfe444000)
+#define DMX_WCH_RESP_ERR3 ((0x0829 << 2) + 0xfe444000)
+#define DMX_UPDT_PKT_SYNC ((0x0830 << 2) + 0xfe444000)
+#define DMX_RCHN_CFG ((0x0831 << 2) + 0xfe444000)
+#define DMX_WCHN_CFG ((0x0832 << 2) + 0xfe444000)
+#define DMX_MEM_PD_CRTL ((0x0833 << 2) + 0xfe444000)
+#define DMX_DMA_BUS_CFG ((0x0834 << 2) + 0xfe444000)
+#define DMX_DMA_GMW_CFG ((0x0835 << 2) + 0xfe444000)
+#define DMX_DMA_GMR_CFG ((0x0836 << 2) + 0xfe444000)
+//========================================================================
+// TS OUTPUT REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe442c00
+// -----------------------------------------------
+#define TS_OUTPUT_PID_RDY ((0x0000 << 2) + 0xfe442c00)
+#define TS_OUTPUT_TEE_LOCK ((0x0001 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PID_CFG ((0x0002 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PID_DAT ((0x0003 << 2) + 0xfe442c00)
+#define TS_OUTPUT_OUT_CFG ((0x0004 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_0 ((0x0010 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_1 ((0x0011 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_2 ((0x0012 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_3 ((0x0013 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_4 ((0x0014 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_5 ((0x0015 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_6 ((0x0016 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_7 ((0x0017 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_8 ((0x0018 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_9 ((0x0019 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_10 ((0x001a << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_11 ((0x001b << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_12 ((0x001c << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_13 ((0x001d << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_14 ((0x001e << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_15 ((0x001f << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_0_1 ((0x0020 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_2_3 ((0x0021 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_4_5 ((0x0022 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_6_7 ((0x0023 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_8_9 ((0x0024 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_10_11 ((0x0025 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_12_13 ((0x0026 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_14_15 ((0x0027 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_16_17 ((0x0028 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_18_19 ((0x0029 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_20_21 ((0x002a << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_22_23 ((0x002b << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_24_25 ((0x002c << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_26_27 ((0x002d << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_28_29 ((0x002e << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_30_31 ((0x002f << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_32_33 ((0x0030 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_34_35 ((0x0031 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_36_37 ((0x0032 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_38_39 ((0x0033 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_40_41 ((0x0034 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_42_43 ((0x0035 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_44_45 ((0x0036 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_46_47 ((0x0037 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_48_49 ((0x0038 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_50_51 ((0x0039 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_52_53 ((0x003a << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_54_55 ((0x003b << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_56_57 ((0x003c << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_58_59 ((0x003d << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_60_61 ((0x003e << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_62_63 ((0x003f << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_0 ((0x0040 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_1 ((0x0041 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_2 ((0x0042 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_3 ((0x0043 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_4 ((0x0044 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_5 ((0x0045 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_6 ((0x0046 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_7 ((0x0047 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_8 ((0x0048 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_9 ((0x0049 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_10 ((0x004a << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_11 ((0x004b << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_12 ((0x004c << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_13 ((0x004d << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_14 ((0x004e << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_15 ((0x004f << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_16 ((0x0050 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_17 ((0x0051 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_18 ((0x0052 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_19 ((0x0053 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_20 ((0x0054 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_21 ((0x0055 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_22 ((0x0056 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_23 ((0x0057 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_24 ((0x0058 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_25 ((0x0059 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_26 ((0x005a << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_27 ((0x005b << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_28 ((0x005c << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_29 ((0x005d << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_30 ((0x005e << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_31 ((0x005f << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_32 ((0x0060 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_33 ((0x0061 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_34 ((0x0062 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_35 ((0x0063 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_36 ((0x0064 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_37 ((0x0065 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_38 ((0x0066 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_39 ((0x0067 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_40 ((0x0068 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_41 ((0x0069 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_42 ((0x006a << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_43 ((0x006b << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_44 ((0x006c << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_45 ((0x006d << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_46 ((0x006e << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_47 ((0x006f << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_48 ((0x0070 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_49 ((0x0071 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_50 ((0x0072 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_51 ((0x0073 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_52 ((0x0074 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_53 ((0x0075 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_54 ((0x0076 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_55 ((0x0077 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_56 ((0x0078 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_57 ((0x0079 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_58 ((0x007a << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_59 ((0x007b << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_60 ((0x007c << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_61 ((0x007d << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_62 ((0x007e << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_63 ((0x007f << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_0 ((0x0080 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_0 ((0x0081 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_1 ((0x0082 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_1 ((0x0083 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_2 ((0x0084 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_2 ((0x0085 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_3 ((0x0086 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_3 ((0x0087 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_4 ((0x0088 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_4 ((0x0089 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_5 ((0x008a << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_5 ((0x008b << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_6 ((0x008c << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_6 ((0x008d << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_7 ((0x008e << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_7 ((0x008f << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_8 ((0x0090 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_8 ((0x0091 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_9 ((0x0092 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_9 ((0x0093 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_10 ((0x0094 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_10 ((0x0095 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_11 ((0x0096 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_11 ((0x0097 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_12 ((0x0098 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_12 ((0x0099 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_13 ((0x009a << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_13 ((0x009b << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_14 ((0x009c << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_14 ((0x009d << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_15 ((0x009e << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_15 ((0x009f << 2) + 0xfe442c00)
+//========================================================================
+// TSD DESC AES REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe442000
+// -----------------------------------------------
+#define TSD_PID_RDY ((0x0000 << 2) + 0xfe442000)
+#define TSD_TEE_LOCK ((0x0001 << 2) + 0xfe442000)
+#define TSD_PID_STS ((0x0003 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_0 ((0x0004 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_0 ((0x0005 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_1 ((0x0006 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_1 ((0x0007 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_2 ((0x0008 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_2 ((0x0009 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_3 ((0x000a << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_3 ((0x000b << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_4 ((0x000c << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_4 ((0x000d << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_5 ((0x000e << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_5 ((0x000f << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_6 ((0x0010 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_6 ((0x0011 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_7 ((0x0012 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_7 ((0x0013 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_8 ((0x0014 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_8 ((0x0015 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_9 ((0x0016 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_9 ((0x0017 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_10 ((0x0018 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_10 ((0x0019 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_11 ((0x001a << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_11 ((0x001b << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_12 ((0x001c << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_12 ((0x001d << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_13 ((0x001e << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_13 ((0x001f << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_14 ((0x0020 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_14 ((0x0021 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_15 ((0x0022 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_15 ((0x0023 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_16 ((0x0024 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_16 ((0x0025 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_17 ((0x0026 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_17 ((0x0027 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_18 ((0x0028 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_18 ((0x0029 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_19 ((0x002a << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_19 ((0x002b << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_20 ((0x002c << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_20 ((0x002d << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_21 ((0x002e << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_21 ((0x002f << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_22 ((0x0030 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_22 ((0x0031 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_23 ((0x0032 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_23 ((0x0033 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_24 ((0x0034 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_24 ((0x0035 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_25 ((0x0036 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_25 ((0x0037 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_26 ((0x0038 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_26 ((0x0039 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_27 ((0x003a << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_27 ((0x003b << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_28 ((0x003c << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_28 ((0x003d << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_29 ((0x003e << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_29 ((0x003f << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_30 ((0x0040 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_30 ((0x0041 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_31 ((0x0042 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_31 ((0x0043 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_32 ((0x0044 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_32 ((0x0045 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_33 ((0x0046 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_33 ((0x0047 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_34 ((0x0048 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_34 ((0x0049 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_35 ((0x004a << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_35 ((0x004b << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_36 ((0x004c << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_36 ((0x004d << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_37 ((0x004e << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_37 ((0x004f << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_38 ((0x0050 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_38 ((0x0051 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_39 ((0x0052 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_39 ((0x0053 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_40 ((0x0054 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_40 ((0x0055 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_41 ((0x0056 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_41 ((0x0057 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_42 ((0x0058 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_42 ((0x0059 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_43 ((0x005a << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_43 ((0x005b << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_44 ((0x005c << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_44 ((0x005d << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_45 ((0x005e << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_45 ((0x005f << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_46 ((0x0060 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_46 ((0x0061 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_47 ((0x0062 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_47 ((0x0063 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_48 ((0x0064 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_48 ((0x0065 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_49 ((0x0066 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_49 ((0x0067 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_50 ((0x0068 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_50 ((0x0069 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_51 ((0x006a << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_51 ((0x006b << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_52 ((0x006c << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_52 ((0x006d << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_53 ((0x006e << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_53 ((0x006f << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_54 ((0x0070 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_54 ((0x0071 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_55 ((0x0072 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_55 ((0x0073 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_56 ((0x0074 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_56 ((0x0075 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_57 ((0x0076 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_57 ((0x0077 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_58 ((0x0078 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_58 ((0x0079 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_59 ((0x007a << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_59 ((0x007b << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_60 ((0x007c << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_60 ((0x007d << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_61 ((0x007e << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_61 ((0x007f << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_62 ((0x0080 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_62 ((0x0081 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_63 ((0x0082 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_63 ((0x0083 << 2) + 0xfe442000)
+//========================================================================
+// SECURE TOP REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe440300
+// -----------------------------------------------
+#define SEC_TOP_CFG_LOCKABLE ((0x0000 << 2) + 0xfe440300)
+#define SEC_TOP_CFG_LOCK ((0x0001 << 2) + 0xfe440300)
+#define SEC_TOP_CFG_WTO ((0x0002 << 2) + 0xfe440300)
+#define SEC_TOP_N2_GENOUT ((0x0003 << 2) + 0xfe440300)
+#define SEC_TOP_CFG_REG ((0x0004 << 2) + 0xfe440300)
+#define SEC_TOP_NSK_CTRL ((0x0005 << 2) + 0xfe440300)
+#define SEC_TOP_AKL_STS ((0x0006 << 2) + 0xfe440300)
+#define SEC_TOP_ND_STATUS ((0x0007 << 2) + 0xfe440300)
+#define SEC_TOP_CFG_DEMUX ((0x0008 << 2) + 0xfe440300)
+#define SEC_TOP_CFG_DIF ((0x000c << 2) + 0xfe440300)
+#define SEC_TOP_NSK_HASH0 ((0x0010 << 2) + 0xfe440300)
+#define SEC_TOP_NSK_HASH1 ((0x0011 << 2) + 0xfe440300)
+#define SEC_TOP_NSK_HASH2 ((0x0012 << 2) + 0xfe440300)
+#define SEC_TOP_NSK_HASH3 ((0x0013 << 2) + 0xfe440300)
+#define SEC_TOP_PATH0_CTRL ((0x0028 << 2) + 0xfe440300)
+#define SEC_TOP_PATH1_CTRL ((0x0029 << 2) + 0xfe440300)
+#define SEC_TOP_PATH2_CTRL ((0x002a << 2) + 0xfe440300)
+#define SEC_TOP_PATH3_CTRL ((0x002b << 2) + 0xfe440300)
+#define SEC_TOP_DEMOD_PKT_CFG0 ((0x002c << 2) + 0xfe440300)
+#define SEC_TOP_DEMOD_PKT_CFG1 ((0x002d << 2) + 0xfe440300)
+#define SEC_TOP_DEMOD_PKT_CFG2 ((0x002e << 2) + 0xfe440300)
+#define SEC_TOP_DEMOD_PKT_CFG3 ((0x002f << 2) + 0xfe440300)
+#define SEC_TOP_DEMOD_FIFO_CFG0 ((0x0030 << 2) + 0xfe440300)
+#define SEC_TOP_DEMOD_FIFO_CFG1 ((0x0031 << 2) + 0xfe440300)
+#define SEC_TOP_TS_O_PATH_CTRL ((0x0032 << 2) + 0xfe440300)
+#define SEC_TOP_CLEAN_DEMOD_INT ((0x0033 << 2) + 0xfe440300)
+#define SEC_TOP_DEMOD_INT_MASK ((0x0034 << 2) + 0xfe440300)
+#define SEC_TOP_DEMOD_INT_STATUS ((0x0035 << 2) + 0xfe440300)
+#define SEC_TOP_TS_CHN0_ERR_STATUS ((0x0036 << 2) + 0xfe440300)
+#define SEC_TOP_TS_CHN1_ERR_STATUS ((0x0037 << 2) + 0xfe440300)
+#define SEC_TOP_TS_CHN2_ERR_STATUS ((0x0038 << 2) + 0xfe440300)
+#define SEC_TOP_TS_CHN3_ERR_STATUS ((0x0039 << 2) + 0xfe440300)
+//========================================================================
+// TSE DESC AES REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe442800
+// -----------------------------------------------
+#define TSE_PID_RDY ((0x0000 << 2) + 0xfe442800)
+#define TSE_TEE_LOCK ((0x0001 << 2) + 0xfe442800)
+#define TSE_PID_STS ((0x0003 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_0 ((0x0004 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_0 ((0x0005 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_1 ((0x0006 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_1 ((0x0007 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_2 ((0x0008 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_2 ((0x0009 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_3 ((0x000a << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_3 ((0x000b << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_4 ((0x000c << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_4 ((0x000d << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_5 ((0x000e << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_5 ((0x000f << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_6 ((0x0010 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_6 ((0x0011 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_7 ((0x0012 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_7 ((0x0013 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_8 ((0x0014 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_8 ((0x0015 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_9 ((0x0016 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_9 ((0x0017 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_10 ((0x0018 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_10 ((0x0019 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_11 ((0x001a << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_11 ((0x001b << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_12 ((0x001c << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_12 ((0x001d << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_13 ((0x001e << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_13 ((0x001f << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_14 ((0x0020 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_14 ((0x0021 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_15 ((0x0022 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_15 ((0x0023 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_16 ((0x0024 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_16 ((0x0025 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_17 ((0x0026 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_17 ((0x0027 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_18 ((0x0028 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_18 ((0x0029 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_19 ((0x002a << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_19 ((0x002b << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_20 ((0x002c << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_20 ((0x002d << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_21 ((0x002e << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_21 ((0x002f << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_22 ((0x0030 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_22 ((0x0031 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_23 ((0x0032 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_23 ((0x0033 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_24 ((0x0034 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_24 ((0x0035 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_25 ((0x0036 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_25 ((0x0037 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_26 ((0x0038 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_26 ((0x0039 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_27 ((0x003a << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_27 ((0x003b << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_28 ((0x003c << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_28 ((0x003d << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_29 ((0x003e << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_29 ((0x003f << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_30 ((0x0040 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_30 ((0x0041 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_31 ((0x0042 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_31 ((0x0043 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_32 ((0x0044 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_32 ((0x0045 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_33 ((0x0046 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_33 ((0x0047 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_34 ((0x0048 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_34 ((0x0049 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_35 ((0x004a << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_35 ((0x004b << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_36 ((0x004c << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_36 ((0x004d << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_37 ((0x004e << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_37 ((0x004f << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_38 ((0x0050 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_38 ((0x0051 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_39 ((0x0052 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_39 ((0x0053 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_40 ((0x0054 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_40 ((0x0055 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_41 ((0x0056 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_41 ((0x0057 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_42 ((0x0058 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_42 ((0x0059 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_43 ((0x005a << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_43 ((0x005b << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_44 ((0x005c << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_44 ((0x005d << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_45 ((0x005e << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_45 ((0x005f << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_46 ((0x0060 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_46 ((0x0061 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_47 ((0x0062 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_47 ((0x0063 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_48 ((0x0064 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_48 ((0x0065 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_49 ((0x0066 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_49 ((0x0067 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_50 ((0x0068 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_50 ((0x0069 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_51 ((0x006a << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_51 ((0x006b << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_52 ((0x006c << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_52 ((0x006d << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_53 ((0x006e << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_53 ((0x006f << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_54 ((0x0070 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_54 ((0x0071 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_55 ((0x0072 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_55 ((0x0073 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_56 ((0x0074 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_56 ((0x0075 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_57 ((0x0076 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_57 ((0x0077 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_58 ((0x0078 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_58 ((0x0079 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_59 ((0x007a << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_59 ((0x007b << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_60 ((0x007c << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_60 ((0x007d << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_61 ((0x007e << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_61 ((0x007f << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_62 ((0x0080 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_62 ((0x0081 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_63 ((0x0082 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_63 ((0x0083 << 2) + 0xfe442800)
+//========================================================================
+// TSN DESC REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe442400
+// -----------------------------------------------
+#define TSN_PID_RDY ((0x0000 << 2) + 0xfe442400)
+#define TSN_TEE_LOCK ((0x0001 << 2) + 0xfe442400)
+#define TSN_PID_STS ((0x0003 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_0 ((0x0004 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_1 ((0x0005 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_2 ((0x0006 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_3 ((0x0007 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_4 ((0x0008 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_5 ((0x0009 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_6 ((0x000a << 2) + 0xfe442400)
+#define TSN_PID_TABLE_7 ((0x000b << 2) + 0xfe442400)
+#define TSN_PID_TABLE_8 ((0x000c << 2) + 0xfe442400)
+#define TSN_PID_TABLE_9 ((0x000d << 2) + 0xfe442400)
+#define TSN_PID_TABLE_10 ((0x000e << 2) + 0xfe442400)
+#define TSN_PID_TABLE_11 ((0x000f << 2) + 0xfe442400)
+#define TSN_PID_TABLE_12 ((0x0010 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_13 ((0x0011 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_14 ((0x0012 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_15 ((0x0013 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_16 ((0x0014 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_17 ((0x0015 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_18 ((0x0016 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_19 ((0x0017 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_20 ((0x0018 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_21 ((0x0019 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_22 ((0x001a << 2) + 0xfe442400)
+#define TSN_PID_TABLE_23 ((0x001b << 2) + 0xfe442400)
+#define TSN_PID_TABLE_24 ((0x001c << 2) + 0xfe442400)
+#define TSN_PID_TABLE_25 ((0x001d << 2) + 0xfe442400)
+#define TSN_PID_TABLE_26 ((0x001e << 2) + 0xfe442400)
+#define TSN_PID_TABLE_27 ((0x001f << 2) + 0xfe442400)
+#define TSN_PID_TABLE_28 ((0x0020 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_29 ((0x0021 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_30 ((0x0022 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_31 ((0x0023 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_32 ((0x0024 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_33 ((0x0025 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_34 ((0x0026 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_35 ((0x0027 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_36 ((0x0028 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_37 ((0x0029 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_38 ((0x002a << 2) + 0xfe442400)
+#define TSN_PID_TABLE_39 ((0x002b << 2) + 0xfe442400)
+#define TSN_PID_TABLE_40 ((0x002c << 2) + 0xfe442400)
+#define TSN_PID_TABLE_41 ((0x002d << 2) + 0xfe442400)
+#define TSN_PID_TABLE_42 ((0x002e << 2) + 0xfe442400)
+#define TSN_PID_TABLE_43 ((0x002f << 2) + 0xfe442400)
+#define TSN_PID_TABLE_44 ((0x0030 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_45 ((0x0031 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_46 ((0x0032 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_47 ((0x0033 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_48 ((0x0034 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_49 ((0x0035 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_50 ((0x0036 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_51 ((0x0037 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_52 ((0x0038 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_53 ((0x0039 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_54 ((0x003a << 2) + 0xfe442400)
+#define TSN_PID_TABLE_55 ((0x003b << 2) + 0xfe442400)
+#define TSN_PID_TABLE_56 ((0x003c << 2) + 0xfe442400)
+#define TSN_PID_TABLE_57 ((0x003d << 2) + 0xfe442400)
+#define TSN_PID_TABLE_58 ((0x003e << 2) + 0xfe442400)
+#define TSN_PID_TABLE_59 ((0x003f << 2) + 0xfe442400)
+#define TSN_PID_TABLE_60 ((0x0040 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_61 ((0x0041 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_62 ((0x0042 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_63 ((0x0043 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_64 ((0x0044 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_65 ((0x0045 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_66 ((0x0046 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_67 ((0x0047 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_68 ((0x0048 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_69 ((0x0049 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_70 ((0x004a << 2) + 0xfe442400)
+#define TSN_PID_TABLE_71 ((0x004b << 2) + 0xfe442400)
+#define TSN_PID_TABLE_72 ((0x004c << 2) + 0xfe442400)
+#define TSN_PID_TABLE_73 ((0x004d << 2) + 0xfe442400)
+#define TSN_PID_TABLE_74 ((0x004e << 2) + 0xfe442400)
+#define TSN_PID_TABLE_75 ((0x004f << 2) + 0xfe442400)
+#define TSN_PID_TABLE_76 ((0x0050 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_77 ((0x0051 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_78 ((0x0052 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_79 ((0x0053 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_80 ((0x0054 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_81 ((0x0055 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_82 ((0x0056 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_83 ((0x0057 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_84 ((0x0058 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_85 ((0x0059 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_86 ((0x005a << 2) + 0xfe442400)
+#define TSN_PID_TABLE_87 ((0x005b << 2) + 0xfe442400)
+#define TSN_PID_TABLE_88 ((0x005c << 2) + 0xfe442400)
+#define TSN_PID_TABLE_89 ((0x005d << 2) + 0xfe442400)
+#define TSN_PID_TABLE_90 ((0x005e << 2) + 0xfe442400)
+#define TSN_PID_TABLE_91 ((0x005f << 2) + 0xfe442400)
+#define TSN_PID_TABLE_92 ((0x0060 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_93 ((0x0061 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_94 ((0x0062 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_95 ((0x0063 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_96 ((0x0064 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_97 ((0x0065 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_98 ((0x0066 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_99 ((0x0067 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_100 ((0x0068 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_101 ((0x0069 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_102 ((0x006a << 2) + 0xfe442400)
+#define TSN_PID_TABLE_103 ((0x006b << 2) + 0xfe442400)
+#define TSN_PID_TABLE_104 ((0x006c << 2) + 0xfe442400)
+#define TSN_PID_TABLE_105 ((0x006d << 2) + 0xfe442400)
+#define TSN_PID_TABLE_106 ((0x006e << 2) + 0xfe442400)
+#define TSN_PID_TABLE_107 ((0x006f << 2) + 0xfe442400)
+#define TSN_PID_TABLE_108 ((0x0070 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_109 ((0x0071 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_110 ((0x0072 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_111 ((0x0073 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_112 ((0x0074 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_113 ((0x0075 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_114 ((0x0076 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_115 ((0x0077 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_116 ((0x0078 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_117 ((0x0079 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_118 ((0x007a << 2) + 0xfe442400)
+#define TSN_PID_TABLE_119 ((0x007b << 2) + 0xfe442400)
+#define TSN_PID_TABLE_120 ((0x007c << 2) + 0xfe442400)
+#define TSN_PID_TABLE_121 ((0x007d << 2) + 0xfe442400)
+#define TSN_PID_TABLE_122 ((0x007e << 2) + 0xfe442400)
+#define TSN_PID_TABLE_123 ((0x007f << 2) + 0xfe442400)
+#define TSN_PID_TABLE_124 ((0x0080 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_125 ((0x0081 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_126 ((0x0082 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_127 ((0x0083 << 2) + 0xfe442400)
+//========================================================================
+// RNG REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe440700
+// -----------------------------------------------
+#define RNG_TEE_READY ((0x0000 << 2) + 0xfe440700)
+#define RNG_TEE_LOCK ((0x0001 << 2) + 0xfe440700)
+#define RNG_TEE_CFG ((0x0002 << 2) + 0xfe440700)
+#define RNG_TEE_NIST_OUT ((0x0003 << 2) + 0xfe440700)
+#define RNG_TEE_OUT0 ((0x0004 << 2) + 0xfe440700)
+#define RNG_TEE_OUT1 ((0x0005 << 2) + 0xfe440700)
+#define RNG_TEE_OUT2 ((0x0006 << 2) + 0xfe440700)
+#define RNG_TEE_OUT3 ((0x0007 << 2) + 0xfe440700)
+#define RNG_CFG_RING ((0x0010 << 2) + 0xfe440700)
+#define RNG_CFG_RESEED ((0x0011 << 2) + 0xfe440700)
+#define RNG_CFG_HEALTH ((0x0012 << 2) + 0xfe440700)
+#define RNG_CFG_MISC ((0x0013 << 2) + 0xfe440700)
+#define RNG_REE_READY ((0x0020 << 2) + 0xfe440700)
+#define RNG_REE_DEBUG ((0x0021 << 2) + 0xfe440700)
+#define RNG_REE_CFG ((0x0022 << 2) + 0xfe440700)
+#define RNG_REE_OUT0 ((0x0024 << 2) + 0xfe440700)
+#define RNG_REE_OUT1 ((0x0025 << 2) + 0xfe440700)
+#define RNG_REE_OUT2 ((0x0026 << 2) + 0xfe440700)
+#define RNG_REE_OUT3 ((0x0027 << 2) + 0xfe440700)
+//========================================================================
+// OTP REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe440000
+// -----------------------------------------------
+#define OTP_TEE_RDY ((0x0000 << 2) + 0xfe440000)
+#define OTP_TEE_DEBUG ((0x0001 << 2) + 0xfe440000)
+#define OTP_TEE_CFG ((0x0002 << 2) + 0xfe440000)
+#define OTP_TEE_WR_DAT ((0x0004 << 2) + 0xfe440000)
+#define OTP_TEE_RD_DAT ((0x0008 << 2) + 0xfe440000)
+#define OTP_LIC ((0x0010 << 2) + 0xfe440000)
+#define OTP_AML_ID_L ((0x0020 << 2) + 0xfe440000)
+#define OTP_AML_ID_H ((0x0021 << 2) + 0xfe440000)
+#define OTP_ACGK_ID_L ((0x0022 << 2) + 0xfe440000)
+#define OTP_ACGK_ID_H ((0x0023 << 2) + 0xfe440000)
+#define OTP_DVGK_ID_L ((0x0024 << 2) + 0xfe440000)
+#define OTP_DVGK_ID_H ((0x0025 << 2) + 0xfe440000)
+#define OTP_DVUK_ID_L ((0x0026 << 2) + 0xfe440000)
+#define OTP_DVUK_ID_H ((0x0027 << 2) + 0xfe440000)
+#define OTP_DGPK_ID_L ((0x0028 << 2) + 0xfe440000)
+#define OTP_DGPK_ID_H ((0x0029 << 2) + 0xfe440000)
+#define OTP_SECPU_ID_L ((0x002a << 2) + 0xfe440000)
+#define OTP_SECPU_ID_H ((0x002b << 2) + 0xfe440000)
+#define OTP_ETSI012_ID_L ((0x002c << 2) + 0xfe440000)
+#define OTP_ETSI012_ID_H ((0x002d << 2) + 0xfe440000)
+#define OTP_ETSI3_ID_L ((0x002e << 2) + 0xfe440000)
+#define OTP_ETSI3_ID_H ((0x002f << 2) + 0xfe440000)
+#define OTP_MSR_ID_L ((0x0030 << 2) + 0xfe440000)
+#define OTP_MSR_ID_H ((0x0031 << 2) + 0xfe440000)
+#define OTP_VO_ID_L ((0x0032 << 2) + 0xfe440000)
+#define OTP_VO_ID_H ((0x0033 << 2) + 0xfe440000)
+#define OTP_NUID_ID_L ((0x0034 << 2) + 0xfe440000)
+#define OTP_NUID_ID_H ((0x0035 << 2) + 0xfe440000)
+#define OTP_CONAX_ID_L ((0x0036 << 2) + 0xfe440000)
+#define OTP_CONAX_ID_H ((0x0037 << 2) + 0xfe440000)
+#define OTP_NSK_ID_L ((0x0038 << 2) + 0xfe440000)
+#define OTP_NSK_ID_H ((0x0039 << 2) + 0xfe440000)
+#define OTP_REE_RDY ((0x0040 << 2) + 0xfe440000)
+#define OTP_REE_DEBUG ((0x0041 << 2) + 0xfe440000)
+#define OTP_REE_CFG ((0x0042 << 2) + 0xfe440000)
+#define OTP_MRK_CHKNUM ((0x0043 << 2) + 0xfe440000)
+#define OTP_REE_RD_DAT ((0x0048 << 2) + 0xfe440000)
+
+
+#define OTP_LIC00 (OTP_LIC + 0x00)
+#define OTP_LIC01 (OTP_LIC + 0x04)
+#define OTP_LIC02 (OTP_LIC + 0x08)
+#define OTP_LIC03 (OTP_LIC + 0x0C)
+
+#define OTP_LIC10 (OTP_LIC + 0x10)
+#define OTP_LIC11 (OTP_LIC + 0x14)
+#define OTP_LIC12 (OTP_LIC + 0x18)
+#define OTP_LIC13 (OTP_LIC + 0x1C)
+
+#define OTP_LIC20 (OTP_LIC + 0x20)
+#define OTP_LIC21 (OTP_LIC + 0x24)
+#define OTP_LIC22 (OTP_LIC + 0x28)
+#define OTP_LIC23 (OTP_LIC + 0x2C)
+
+#define OTP_LIC30 (OTP_LIC + 0x30)
+#define OTP_LIC31 (OTP_LIC + 0x34)
+#define OTP_LIC32 (OTP_LIC + 0x38)
+#define OTP_LIC33 (OTP_LIC + 0x3C)
+
+#define OTP_LIC0 (OTP_LIC00)
+
+//========================================================================
+// KL REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe440200
+// -----------------------------------------------
+#define MKL_TEE_RDY ((0x0000 << 2) + 0xfe440200)
+#define MKL_TEE_DEBUG ((0x0001 << 2) + 0xfe440200)
+#define MKL_TEE_CFG ((0x0002 << 2) + 0xfe440200)
+#define MKL_TEE_CMD ((0x0003 << 2) + 0xfe440200)
+#define MKL_TEE_EK ((0x0004 << 2) + 0xfe440200)
+#define MKL_TEE_CR_0 ((0x001c << 2) + 0xfe440200)
+#define MKL_TEE_CR_1 ((0x001d << 2) + 0xfe440200)
+#define MKL_TEE_CR_2 ((0x001e << 2) + 0xfe440200)
+#define MKL_TEE_CR_3 ((0x001f << 2) + 0xfe440200)
+#define MKL_REE_RDY ((0x0020 << 2) + 0xfe440200)
+#define MKL_REE_DEBUG ((0x0021 << 2) + 0xfe440200)
+#define MKL_REE_CFG ((0x0022 << 2) + 0xfe440200)
+#define MKL_REE_CMD ((0x0023 << 2) + 0xfe440200)
+#define MKL_REE_EK ((0x0024 << 2) + 0xfe440200)
+//========================================================================
+// DMA REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe440400
+// -----------------------------------------------
+#define DMA_CORE_DSC_0 ((0x0000 << 2) + 0xfe440400)
+#define DMA_CORE_DSC_1 ((0x0001 << 2) + 0xfe440400)
+#define DMA_CORE_DSC_2 ((0x0002 << 2) + 0xfe440400)
+#define DMA_CORE_DSC_3 ((0x0003 << 2) + 0xfe440400)
+#define DMA_CORE_DSC_4 ((0x0004 << 2) + 0xfe440400)
+#define DMA_CORE_DSC_5 ((0x0005 << 2) + 0xfe440400)
+#define DMA_CORE_IRQ_STS_0 ((0x0008 << 2) + 0xfe440400)
+#define DMA_CORE_IRQ_STS_1 ((0x0009 << 2) + 0xfe440400)
+#define DMA_CORE_IRQ_STS_2 ((0x000a << 2) + 0xfe440400)
+#define DMA_CORE_IRQ_STS_3 ((0x000b << 2) + 0xfe440400)
+#define DMA_CORE_IRQ_STS_4 ((0x000c << 2) + 0xfe440400)
+#define DMA_CORE_IRQ_STS_5 ((0x000d << 2) + 0xfe440400)
+#define DMA_CORE_CFG_REG ((0x0010 << 2) + 0xfe440400)
+#define DMA_CORE_CFG_SEC_LSB ((0x0011 << 2) + 0xfe440400)
+#define DMA_CORE_CFG_SEC_MSB ((0x0012 << 2) + 0xfe440400)
+//========================================================================
+// KT REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe440500
+// -----------------------------------------------
+#define KT_TEE_RDY ((0x0000 << 2) + 0xfe440500)
+#define KT_TEE_RDY2 ((0x0001 << 2) + 0xfe440500)
+#define KT_TEE_CFG ((0x0002 << 2) + 0xfe440500)
+#define KT_TEE_STS ((0x0003 << 2) + 0xfe440500)
+#define KT_TEE_KEY0 ((0x0004 << 2) + 0xfe440500)
+#define KT_TEE_KEY1 ((0x0005 << 2) + 0xfe440500)
+#define KT_TEE_KEY2 ((0x0006 << 2) + 0xfe440500)
+#define KT_TEE_KEY3 ((0x0007 << 2) + 0xfe440500)
+#define KT_REE_RDY ((0x0020 << 2) + 0xfe440500)
+#define KT_REE_RDY2 ((0x0021 << 2) + 0xfe440500)
+#define KT_REE_CFG ((0x0022 << 2) + 0xfe440500)
+#define KT_REE_STS ((0x0023 << 2) + 0xfe440500)
+#define KT_REE_KEY0 ((0x0024 << 2) + 0xfe440500)
+#define KT_REE_KEY1 ((0x0025 << 2) + 0xfe440500)
+#define KT_REE_KEY2 ((0x0026 << 2) + 0xfe440500)
+#define KT_REE_KEY3 ((0x0027 << 2) + 0xfe440500)
+//========================================================================
+// CERT REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe440600
+// -----------------------------------------------
+//========================================================================
+// SP REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe441000
+// -----------------------------------------------
+//ree domian
+#define REE_SCPU2REE_CSR_ADDR ((0x0300 << 2) + 0xfe441000)
+#define REE_SCPU2REE_DATA_ST_ADDR ((0x0380 << 2) + 0xfe441000)
+#define REE_SCPU2REE_DATA_ED_ADDR ((0x039f << 2) + 0xfe441000)
+#define REE_REE2SCPU_CSR_ADDR ((0x0200 << 2) + 0xfe441000)
+#define REE_REE2SCPU_DATA_ST_ADDR ((0x0280 << 2) + 0xfe441000)
+#define REE_REE2SCPU_DATA_ED_ADDR ((0x029f << 2) + 0xfe441000)
+//tee domian
+#define TEE_SCPU2TEE_CSR_ADDR ((0x0100 << 2) + 0xfe441000)
+#define TEE_SCPU2TEE_DATA_ST_ADDR ((0x0180 << 2) + 0xfe441000)
+#define TEE_SCPU2TEE_DATA_ED_ADDR ((0x019f << 2) + 0xfe441000)
+#define TEE_TEE2SCPU_CSR_ADDR ((0x0000 << 2) + 0xfe441000)
+#define TEE_TEE2SCPU_DATA_ST_ADDR ((0x0080 << 2) + 0xfe441000)
+#define TEE_TEE2SCPU_DATA_ED_ADDR ((0x009f << 2) + 0xfe441000)
+//========================================================================
+// NSK REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe450000
+// -----------------------------------------------
+//
+// Closing file: REG_LIST_SECURITY_RTL.h
+//
+//
+// Reading file: REG_LIST_DEMUX_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe034000
+// -----------------------------------------------
+// There are two instantiations under one CBUS slave. Each CBUS slave can support
+// 256 registers. Each demux is allocated 128 registers so set the offset in
+// the middle
+// Copy this define but don't add a base address
+#define SECOND_DEMUX_OFFSET_0 0x50
+#define THIRD_DEMUX_OFFSET_0 0xa0
+//========================================================================
+// STB TOP Registers (8'hf0 - 8'hf7)
+//========================================================================
+// Bit 5:4 -- fec_sel_demux_2
+// Bit 3:2 -- fec_sel_demux_1
+// Bit 1:0 -- fec_sel_demux_0
+#define TS_TOP_CONFIG1 ((0x004f << 2) + 0xfe034000)
+// Bit 31:24 -- file_m2ts_skip_bytes_hiu1
+// Bit 23:22 -- reserved
+// Bit 21 -- ts_hiu_enable_hiu1
+// Bit 20:16 -- fec_clk_div_hiu1
+// Bit 15:8 -- TS_package_length_sub_1_hiu1 (default : 187)
+// Bit 7:0 -- fec_sync_byte_hiu1 (default : 0x47)
+#define TS_HIU1_CONFIG ((0x004e << 2) + 0xfe034000)
+//bit[1:0]-- stb_recorder2_sel
+#define STB_RECORDER2_CNTL ((0x00ee << 2) + 0xfe034000)
+// bit [11]-- s2p2_disable
+// bit [10:7]-- s2p2_clk_div
+// bit [6:0]-- fec_serial_control_2
+#define STB_S2P2_CONFIG ((0x00ef << 2) + 0xfe034000)
+// bit 30:28 -- ciplus_o_sel
+// bit 27:26 -- ciplus_i_sel
+// bit 25 -- use FAIL fro TS2
+// bit 24 -- use FAIL fro TS1
+// bit 23 -- use FAIL fro TS0
+// bit 22 -- invert fec_error for S2P1
+// bit 21 -- invert fec_data for S2P1
+// bit 20 -- invert fec_sync for S2P1
+// bit 19 -- invert fec_valid for S2P1
+// bit 18 -- invert fec_clk for S2P1
+// bit 17:16 -- fec_s_sel for S2P1 00 - select TS0, 01 -- select TS1, 10 -- select TS2, 11 - reserved
+// Bit 15 -- enable_des_pl_clk
+// Bit 14 -- ts_out_select[3]
+// Bit 13 -- use FAIL for TS3
+// Bit 12:10 -- ts_out_select[2:0], 0-TS0, 1-TS1, 2-TS2, 3-TS3, 4-S2P2, 5-S2P1, 6-S2P0, 7-File, 8-File1
+// bit 9:8 -- des_i_sel 00 -- select_fec_0, 01 -- select_fec_1, 10 -- select_fec_2, 11 - reserved
+// bit 7 -- enable_des_pl
+// bit 6 -- invert fec_error for S2P0
+// bit 5 -- invert fec_data for S2P0
+// bit 4 -- invert fec_sync for S2P0
+// bit 3 -- invert fec_valid for S2P0
+// bit 2 -- invert fec_clk for S2P0
+// bit 1:0 -- fec_s_sel for S2P0 00 - select TS0, 01 -- select TS1, 10 -- select TS2, 11 - reserved
+#define STB_TOP_CONFIG ((0x00f0 << 2) + 0xfe034000)
+// 31:28 - s2p1_clk_div
+// 27:24 - s2p0_clk_div
+// 23 - s2p1_disable
+// 22 - s2p0_disable
+// 21 - Reserved
+// 20 -- TS_OUT_error_INVERT
+// 19 -- TS_OUT_data_INVERT
+// 18 -- TS_OUT_sync_INVERT
+// 17 -- TS_OUT_valid_INVERT
+// 16 -- TS_OUT_clk_INVERT
+// 15:8 -- TS_package_length_sub_1 (default : 187)
+// 7:0 -- fec_sync_byte (default : 0x47)
+#define TS_TOP_CONFIG ((0x00f1 << 2) + 0xfe034000)
+// Bit 25:24 -- transport_scrambling_control_odd_2 // should be 3
+// Bit 23:16 -- file_m2ts_skip_bytes
+// Bit 15:8 -- des_out_dly
+// Bit 7:6 -- transport_scrambling_control_odd // should be 3
+// Bit 5 -- ts_hiu_enable
+// Bit 4:0 -- fec_clk_div
+#define TS_FILE_CONFIG ((0x00f2 << 2) + 0xfe034000)
+// Bit 19:14 -- des_2 ts pl state -- Read Only
+// Bit 13:8 -- des ts pl state -- Read Only
+// Bit 3:0 PID index to 8 PID to get key-set
+// auto increse after TS_PL_PID_DATA read/write
+#define TS_PL_PID_INDEX ((0x00f3 << 2) + 0xfe034000)
+// Bit 13 -- PID match disble
+// Bit 12:0 -- PID
+#define TS_PL_PID_DATA ((0x00f4 << 2) + 0xfe034000)
+#define COMM_DESC_KEY0 ((0x00f5 << 2) + 0xfe034000)
+#define COMM_DESC_KEY1 ((0x00f6 << 2) + 0xfe034000)
+#define COMM_DESC_KEY_RW ((0x00f7 << 2) + 0xfe034000)
+// CI+ Register defines
+// Bits[31:0] of the key
+#define CIPLUS_KEY0 ((0x00f8 << 2) + 0xfe034000)
+// Bits[63:32] of the key
+#define CIPLUS_KEY1 ((0x00f9 << 2) + 0xfe034000)
+// Bits[95:64] of the key
+#define CIPLUS_KEY2 ((0x00fa << 2) + 0xfe034000)
+// Bits[127:96] of the key
+#define CIPLUS_KEY3 ((0x00fb << 2) + 0xfe034000)
+// bit[5] write AES IV B value
+// bit[4] write AES IV A value
+// bit[3] write AES B key
+// bit[2] write AES A key
+// bit[1] write DES B key
+// bit[0] write DES A key
+#define CIPLUS_KEY_WR ((0x00fc << 2) + 0xfe034000)
+// [15:8] TS out delay. This controls the rate at which the CIplus module drives TS out
+// [3] General enable for the ciplus module
+// [2] AES CBC disable (default should be 0 to enable AES CBC)
+// [1] AES Enable
+// [0] DES Eanble
+#define CIPLUS_CONFIG ((0x00fd << 2) + 0xfe034000)
+// bit[31:28] AES IV endian
+// bit[27:24] AES message out endian
+// bit[23:20] AES message in endian
+// bit[19:16] AES key endian
+// bit[15:11] unused
+// bit[10:8] DES message out endian
+// bit[6:4] DES message in endian
+// bit[2:0] DES key endian
+#define CIPLUS_ENDIAN ((0x00fe << 2) + 0xfe034000)
+// bit 15:8 - des_out_dly_2
+// bit 7 - reserved
+// Bit 6-- enable_des_pl_clk_2
+// bit 5 - enable_des_pl_2
+// bit 4:2 -- use_des_2 bit[2] -- demux0, bit[3] -- demux1, bit[4] -- demux2
+// bit 1:0 -- des_i_sel_2 00 -- select_fec_0, 01 -- select_fec_1, 10 -- select_fec_2, 11 - reserved
+#define COMM_DESC_2_CTL ((0x00ff << 2) + 0xfe034000)
+//
+// NOTE: Don't process the demux registers using the standard create_headers.... perl script.
+// Instead, since the demux has multiple instances (and many registers) use a separate
+// script to create a separate stb_define.h for C-code.
+//========================================================================
+// STB Registers (8'h00 - 8'h4f)
+//
+//========================================================================
+// STB registers are 8'h0x
+// Bit 15:0 -- version number : 0x0002 (v0.01)
+// Bit 16 -- fec_select[3]
+// Bit 15 -- fec_core_select 1 - select descramble output
+// Bit 14:12 - fec_select[2:0] 0-TS0, 1-TS1, 2-TS2, 3-TS3, 4-S2P2, 5-S2P1, 6-S2P0, 7-File, 8-File1
+// Bit 11 -- FEC_CLK
+// Bit 10 -- SOP
+// Bit 9 -- D_VALID
+// Bit 8 -- D_FAIL
+// Bit 7:0 -- D_DATA 7:0
+// bit 31 -- enable_free_clk_fec_data_valid
+// bit 30 -- enable_free_clk_stb_reg
+// bit 29 -- always_use_pes_package_length
+// bit 28 -- disable_pre_incomplete_section_fix
+// bit 27 -- pointer_field_multi_pre_en
+// bit 26 -- ignore_pre_incomplete_section
+// bit 25 -- video2_enable
+// bit 24:22 -- video2_type
+// bit 21 -- do_not_trust_pes_package_length
+// bit 20 (bit 4) -- Bypass use recoder path
+// bit 19 (bit 3) -- clear_PID_continuity_counter_valid
+// bit 18 (bit 2) -- Disable Splicing
+// bit 17 (bit 1) -- Insert PES_STRONG_SYNC in Audio PES
+// bit 16 (bit 0) -- Insert PES_STRONG_SYNC in Video PES
+// Bit 15 - do not trust section length
+// Bit 14 - om cmd push even zero
+// Bit 13 - set_buff_ready_even_not_busy
+// Bit 12 - SUB, OTHER PES interrupt at beginning of PES
+// Bit 11 - discard_av_package -- for ts_recorder use only
+// Bit 10 - ts_recorder_select 0:after PID filter 1:before PID filter
+// Bit 9 - ts_recorder_enable
+// Bit 8 - (table_id == 0xff) means section_end
+// Bit 7 - do not send uncomplete section
+// Bit 6 - do not discard duplicate package
+// Bit 5 - search SOP when trasport_error_indicator
+// Bit 4 - stb demux enable
+// Bit 3 - do not reset state machine on SOP
+// Bit 2 - search SOP when error happened ( when ignore_fail_n_sop, will have this case)
+// Bit 1 - do not use SOP input ( check FEC sync byte instead )
+// Bit 0 - ignore fec_error bit when non sop ( check error on SOP only)
+// bit 15:8 demux package length - 1 ( default : 187 )
+// bit 7:0 default is 0x47
+// bit 31:16 -- filter memory write data hi[31:16]
+// bit 15:0 -- filter memory write data low [15:0]
+// bit 31:24 -- advanced setting hi
+// bit 23:16 -- advanced setting low
+// bit 15 -- filter memory write data request
+// bit 7:0 -- filter memory write addr
+// bit 13:8 demux state -- read only
+// bit 7:4 -- maxnum section filter compare address
+// bit 3:0 -- maxnum PID filter compare address
+// bit 15 - transport_error_indicator
+// bit 14 - payload_unit_start_indicator
+// bit 13 - transport_priority
+// bit 12:0 - PID
+// bit 7:6 transport_scrambling_control
+// bit 5:4 adaptation_field_control
+// bit 3:0 continuity_counter
+// bit 15:12 -- om_cmd_count (read only)
+// bit 11:9 -- overflow_count // bit 11:9 -- om_cmd_wr_ptr (read only)
+// bit 8:6 -- om_overwrite_count // bit 8:6 -- om_cmd_rd_ptr (read only)
+// bit 5:3 -- type_stb_om_w_rd (read only)
+// bit 2 -- unit_start_stb_om_w_rd (read only)
+// bit 1 -- om_cmd_overflow (read only)
+// bit 0 -- om_cmd_pending (read)
+// bit 0 -- om_cmd_read_finished (write)
+// bit 15:9 // bit 14:8 -- count_stb_om_w_rd (read only)
+// bit 8:0 // bit 7:0 -- start_stb_om_wa_rd (read only)
+// bit 11:0 -- offset for section data
+// bit 31:16 -- base address for section buffer group 0 (*0x400 to get real address)
+// bit 15:0 -- base address for section buffer group 1 (*0x400 to get real address)
+// bit 31:16 -- ba2e address for section buffer group 2 (*0x400 to get real address)
+// bit 15:0 -- base address for section buffer group 3 (*0x400 to get real address)
+// bit 3:0 -- section buffer size for group 0 (bit used, for example, 10 means 1K)
+// bit 7:4 -- section buffer size for group 1
+// bit 11:8 -- section buffer size for group 2
+// bit 15:12 -- section buffer size for group 3
+// section buffer busy status for buff 31:0 ( Read Only )
+// section buffer write status for buff 31:0 -- Read
+// clear buffer status ( buff READY and BUSY ) -- write
+// bit 4:0 -- SEC_BUFFER_INDEX RW
+// bit 12:8 -- SEC_BUFFER_NUMBER for the INDEX buffer Read_Only
+// bit 14 -- output_section_buffer_valid
+// bit 15 -- section_reset_busy (Read Only)
+// bit 9:5 -- BYPASS PID number
+// bit 4:0 -- PCR PID number
+// bit 15:0 -- stream_id filter bit enable
+// bit 7:0 -- stream_id filter target
+// bit 12 -- PCR_EN
+// bit 11:0 -- PCR90K_DIV
+// bit 31:0 -- PCR[31:0] R/W
+// bit 31:0 -- VPTS[31:0] R/W
+// bit 31:0 -- VDTS[31:0] R/W
+// bit 31:0 -- APTS[31:0] R/W
+// bit 31:0 -- SPTS[31:0] R/W
+// read -- status, write 1 clear status
+// bit 15 -- SUB_PTS[32]
+// bit 14 -- AUDIO_PTS[32]
+// bit 13 -- VIDEO_DTS[32]
+// bit 12 -- VIDEO_PTS[32]
+// bit 3 -- sub_pts_ready
+// bit 2 -- audio_pts_ready
+// bit 1 -- video_dts_ready
+// bit 0 -- video_pts_ready
+// bit 3:0 --
+// 0 -- adaptation_field_length[7:0], adaption_field_byte_1[7:0]
+// 1 -- stream_id[7:0], pes_header_bytes_left[7:0]
+// 2 -- pes_package_bytes_left[15:0]
+// 3 -- pes_ctr_byte[7:0], pes_flag_byte[7:0]
+//
+// read only
+// bit[31] -- no_match_record_en
+// bit[30:16] - reserved
+// default : 0x807f
+// bit 15:9 -- MAX OM DMA COUNT (default: 0x40)
+// bit 8:0 -- LAST ADDR OF OM ADDR (default: 127)
+// 15:0 WRITE 1 CLEAR to clear interrupt source
+//12 -- INPUT_TIME_OUT
+//11 -- PCR_ready
+//10 -- audio_splicing_point
+// 9 -- video_splicing_point
+// 8 -- other_PES_int
+// 7 -- sub_PES_int
+// 6 -- discontinuity
+// 5 -- duplicated_pack_found
+// 4 -- New PDTS ready
+// 3 -- om_cmd_buffer ready for access
+// 2 -- section buffer ready
+// 1 -- transport_error_indicator
+// 0 -- TS ERROR PIN
+// Bit 5:3 - demux om write endian control for bypass
+// Bit 2:0 - demux om write endian control for section
+// When Bit 31 - 1 write will indicate all type use sepertate endian (Write Only)
+// Bit 23:21 - demux om write endian control for OTHER_PES_PACKET
+// Bit 20:18 - demux om write endian control for SCR_ONLY_PACKET
+// Bit 17:15 - demux om write endian control for SUB_PACKET
+// Bit 14:12 - demux om write endian control for AUDIO_PACKET
+// Bit 11:9 - demux om write endian control for VIDEO_PACKET
+//
+// When Bit 31 - 0 write will indicate all type else use Bit 8:6
+// Bit 8:6 - demux om write endian control for else
+// Bit 10:9 -- sel DPTS_wr_ptr: 00 from parserA ; 01 from parserB
+// Bit 8:7 -- use hi_bsf interface: 01 sel hiu0; 10 sel hiu1
+// Bit 6:2 - Reserved
+// Bit 1 - enable_halt_ts_hiu_fix
+// Bit 0 - enable_halt_ts_hiu
+// bit 15:0 -- base address for section buffer start (*0x10000 to get real base)
+// bit 11 -- mask bit for OTHER_PES_AHB_DMA_EN
+// bit 10 -- mask bit for SUB_AHB_DMA_EN
+// bit 9 -- mask bit for BYPASS_AHB_DMA_EN
+// bit 8 -- mask bit for SECTION_AHB_DMA_EN
+// bit 7 -- mask bit for recoder stream
+// bit 6:0 -- mask bit for each type
+// bit 31:0 -- vb_wr_ptr for video PDTS
+// bit 31:0 -- ab_wr_ptr for audio PDTS
+// bit 20:0 -- SB_WRITE_PTR (sb_wr_ptr << 3 == byte write position)
+// bit 19:0 -- SB_START (sb_start << 12 == byte address);
+// bit 20:0 -- SB_SIZE (sb_size << 3 == byte size, 16M maximun)
+// bit 31:0 -- sb_wr_ptr for sub PES
+// bit 31:16 -- ob_wr_ptr for other PES
+// bit 20:0 -- OB_WRITE_PTR (ob_wr_ptr << 3 == byte write position)
+// bit 19:0 -- OB_START (ob_start << 12 == byte address);
+// bit 20:0 -- OB_SIZE (ob_size << 3 == byte size, 16M maximun)
+// bit 31:0 -- ob_wr_ptr for sub PES
+// 15:0 DEMUX interrupt MASK
+// 9 -- splicing_point
+// 8 -- other_PES_int
+// 7 -- sub_PES_int
+// 6 -- discontinuity
+// 5 -- duplicated_pack_found
+// 4 -- New PDTS ready
+// 3 -- om_cmd_buffer ready for access
+// 2 -- section buffer ready
+// 1 -- transport_error_indicator
+// 0 -- TS ERROR PIN
+// 31:16 VIDEO PID filter data
+//15 -- splicing VIDEO PID change enable
+//14:10 -- VIDEO PID FILTER ADDRESS
+// 9 -- PES splicing active (Read Only)
+// 8 -- splicing active (Read Only)
+// 7:0 splicing countdown (Read Only)
+// 31:16 AUDIO PID filter data
+//15 -- splicing AUDIO PID change enable
+//14:10 -- AUDIO PID FILTER ADDRESS
+// 9 -- PES splicing active (Read Only)
+// 8 -- splicing active (Read Only)
+// 7:0 splicing countdown (Read Only)
+// 23:16 M2TS_SKIP_BYTES
+// 15:8 LAST TS PACKAGE BYTE COUNT (Read Only)
+// 7:0 PACKAGE BYTE COUNT (Read Only)
+// 15:0 2 bytes strong sync add to PES
+// bit 15 -- stb_om_ren
+// bit 14:11 -- reserved
+// bit 10:0 -- OM_DATA_RD_ADDR
+// bit 15:0 -- OM_DATA_RD
+// AUTO STOP SETTING for 32 channels
+// 4-nbits per channel
+// when write
+// bit 3 -- set section active
+// bit 2:0 -- auto stop after count (0 means never stop)
+// when read
+// bit 3 -- current active status (1 - active, 0 - stopped )
+// bit 2:0 -- count down to auto stop
+// section 31:24
+// section 23:16
+// section 15:8
+// section 7:0
+// bit 31:0 reset channel status - each bit reset each channel
+// read -- 32 channel status
+// bit 4 -- video_stamp_use_dts
+// bit 3 -- audio_stamp_sync_1_en
+// bit 2 -- audio_stamp_insert_en
+// bit 1 -- video_stamp_sync_1_en
+// bit 0 -- video_stamp_insert_en
+// Write : Bit[4:0] secter filter number for reset
+// Read : select according to output_section_buffer_valid :
+// per bit per section buffer valid status
+// or section_buffer_ignore
+// bit[31:0] - channel_reset_timeout_disable
+// bit[31] - no_match_reset_timeout_disable
+// bit[30:0] input_time_out_int_cnt (0 -- means disable) Wr-setting, Rd-count
+// bit[31:0] - channel_packet_count_disable
+// bit[31] - no_match_packet_count_disable
+// bit[30:0] input_packet_count
+// bit[31:0] channel_record_enable
+// bit[31:0] channel_process_enable
+// bit[31:24] small_sec_size ((n+1) * 256 Bytes)
+// bit[23:16] small_sec_rd_ptr
+// bit[15:8] small_sec_wr_ptr
+// bit[7:2] reserved
+// bit[1] small_sec_wr_ptr_wr_enable
+// bit[0] small_section_enable
+// bit[31:0] small_sec_start_addr
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: REG_LIST_DEMUX_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: ./REG_LIST_RTL.h
+//
+//
+// Reading file: ./vcbus_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+//===========================================================================
+//
+// Reading file: rdma_regs.h
+//
+//===========================================================================
+// RDMA registers 0x00 - 0xff
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: RDMA_VCBUS_BASE = 0x11
+// -----------------------------------------------
+// Bit 31: 0 RW AHB start address for manual start DMA
+#define RDMA_AHB_START_ADDR_MAN ((0x1100 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for manual start DMA
+#define RDMA_AHB_END_ADDR_MAN ((0x1101 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 1
+#define RDMA_AHB_START_ADDR_1 ((0x1102 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 1
+#define RDMA_AHB_END_ADDR_1 ((0x1103 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 2
+#define RDMA_AHB_START_ADDR_2 ((0x1104 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 2
+#define RDMA_AHB_END_ADDR_2 ((0x1105 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 3
+#define RDMA_AHB_START_ADDR_3 ((0x1106 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 3
+#define RDMA_AHB_END_ADDR_3 ((0x1107 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 4
+#define RDMA_AHB_START_ADDR_4 ((0x1108 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 4
+#define RDMA_AHB_END_ADDR_4 ((0x1109 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 5
+#define RDMA_AHB_START_ADDR_5 ((0x110a << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 5
+#define RDMA_AHB_END_ADDR_5 ((0x110b << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 6
+#define RDMA_AHB_START_ADDR_6 ((0x110c << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 6
+#define RDMA_AHB_END_ADDR_6 ((0x110d << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 7
+#define RDMA_AHB_START_ADDR_7 ((0x110e << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 7
+#define RDMA_AHB_END_ADDR_7 ((0x110f << 2) + 0xff000000)
+// Auto start DMA control:
+// Bit 31:24 RW ctrl_enable_int_3. Interrupt inputs enable mask for source 3.
+// Bit 23:16 RW ctrl_enable_int_2. Interrupt inputs enable mask for source 2.
+// Bit 15: 8 RW ctrl_enable_int_1. Interrupt inputs enable mask for source 1.
+// Bit 7 RW ctrl_cbus_write_3. Register read/write mode for auto-start 3. 1=Register write; 0=Register read.
+// Bit 6 RW ctrl_cbus_write_3. Register read/write mode for auto-start 2. 1=Register write; 0=Register read.
+// Bit 5 RW ctrl_cbus_write_3. Register read/write mode for auto-start 1. 1=Register write; 0=Register read.
+// Bit 4 R Rsrv.
+// Bit 3 RW ctrl_cbus_addr_incr_3. 1=Incremental register access for auto-start 3; 0=Non-incremental (individual) register access.
+// Bit 2 RW ctrl_cbus_addr_incr_2. 1=Incremental register access for auto-start 2; 0=Non-incremental (individual) register access.
+// Bit 1 RW ctrl_cbus_addr_incr_1. 1=Incremental register access for auto-start 1; 0=Non-incremental (individual) register access.
+// Bit 0 R Rsrv.
+#define RDMA_ACCESS_AUTO ((0x1110 << 2) + 0xff000000)
+#define RDMA_ACCESS_AUTO2 ((0x1111 << 2) + 0xff000000)
+// Manual start DMA control:
+// Bit 31: 3 R Rsrv.
+// Bit 2 RW ctrl_cbus_write_man. Register read/write mode for manual-start. 1=Register write; 0=Register read.
+// Bit 1 RW ctrl_cbus_addr_incr_man. 1=Incremental register access for manual-start; 0=Non-incremental (individual) register access.
+// Bit 0 W ctrl_start_man. Write 1 to this bit to manual-start DMA. This bit always read back 0.
+#define RDMA_ACCESS_MAN ((0x1113 << 2) + 0xff000000)
+// RDMA general control:
+// Bit 31:25 R Rsrv.
+// Bit 24 W ctrl_clr_rdma_done_int. Write 1 to reset rdma_int level to 0. No need to clear this bit.
+// Bit 23:19 R Rsrv.
+// Bit 18:13 R Rsrv.
+// Bit 12: 7 R Rsrv.
+// Bit 6 RW ctrl_ddr_urgent.
+// Bit 5: 4 RW ctrl_ahb_wr_burst_size. 0=ABH write request burst size 16;
+// 1=ABH write request burst size 24;
+// 2=ABH write request burst size 32;
+// 3=ABH write request burst size 48.
+// Bit 3: 2 RW ctrl_ahb_rd_burst_size. 0=ABH read request burst size 16;
+// 1=ABH read request burst size 24;
+// 2=ABH read request burst size 32;
+// 3=ABH read request burst size 48.
+// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logics except register.
+// Bit 0 RW ctrl_free_clk_enable. 0=Default, Enable clock gating. 1=No clock gating, enable free clock.
+#define RDMA_CTRL ((0x1114 << 2) + 0xff000000)
+// Read only.
+// Bit 31:29 R Rsrv.
+// Bit 28 R rdma_done_int.
+// Bit 27:25 R Rsrv.
+// Bit 24:18 R ahb_wrfifo_cnt. FIFO for buffering CBus read data to be sent to AHB
+// Bit 17:11 R ahb_rdfifo_cnt. FIFO for buffering data read from AHB.
+// Bit 10: 8 R ddr_req_st. =0 -- Idle; !=0 -- AHB interfacing ongoing.
+// Bit 7: 4 R curr_req. Latest requests that is being/been serviced. E.g. 0000=Idle; 0010=Latest serviced request is Req 1.
+// Bit 3: 0 R req_latch. Requests that are yet to be serviced. E.g. 0000=No request; 0001=Req 0 waiting; 1100=Req 2 and 3 waiting.
+#define RDMA_STATUS ((0x1115 << 2) + 0xff000000)
+#define RDMA_STATUS2 ((0x1116 << 2) + 0xff000000)
+#define RDMA_STATUS3 ((0x1117 << 2) + 0xff000000)
+#define RDMA_ACCESS_AUTO4 ((0x1118 << 2) + 0xff000000)
+#define RDMA_SRAM_CNTL ((0x1120 << 2) + 0xff000000)
+#define RDMA_SRAM_REGADDR ((0x1121 << 2) + 0xff000000)
+#define RDMA_SRAM_REGDATA ((0x1122 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC1_SEL ((0x1123 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC2_SEL ((0x1124 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC3_SEL ((0x1125 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC4_SEL ((0x1126 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC5_SEL ((0x1127 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC6_SEL ((0x1128 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC7_SEL ((0x1129 << 2) + 0xff000000)
+//
+// Closing file: rdma_regs.h
+//
+//
+// Reading file: vpu_vdin0_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+// VDIN
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VDIN0_VCBUS_BASE = 0x12
+// -----------------------------------------------
+//
+// Reading file: vpu_vdin_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+// VDIN
+//===========================================================================
+#define VDIN_SCALE_COEF_IDX ((0x1200 << 2) + 0xff000000)
+#define VDIN_SCALE_COEF ((0x1201 << 2) + 0xff000000)
+//bit 31, mpeg_to_vdin_sel, 0: mpeg source to NR directly, 1: mpeg source pass through here
+//bit 30, mpeg_field info which can be written by software
+//Bit 29, force go_field, pulse signal
+//Bit 28, force go_line, pulse signal
+//Bit 27, enable mpeg_go_field input signal
+//Bit 26:20, hold lines
+//Bit 19, delay go_field function enable
+//Bit 18:12, delay go_field line number
+//Bit 11:10, component2 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in
+//Bit 9:8, component1 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in
+//Bit 7:6, component0 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in
+//Bit 5, input window selection function enable
+//Bit 4, enable VDIN common data input, otherwise there will be no video data input
+//Bit 3:0 vdin selection, 1: mpeg_in from dram, 2: bt656 input, 3: component input, 4: tvdecoder input, 5: hdmi rx input, 6: digtial video input, 7: loopback from Viu1, 8: MIPI.
+#define VDIN_COM_CTRL0 ((0x1202 << 2) + 0xff000000)
+//Bit 28:16 active_max_pix_cnt, readonly
+//Bit 12:0 active_max_pix_cnt_shadow, readonly
+#define VDIN_ACTIVE_MAX_PIX_CNT_STATUS ((0x1203 << 2) + 0xff000000)
+//Bit 28:16 go_line_cnt, readonly
+//Bit 12:0 active_line_cnt, readonly
+#define VDIN_LCNT_STATUS ((0x1204 << 2) + 0xff000000)
+//Readonly
+//Bit [14:3] lfifo_buf_cnt
+//Bit 2, vdin_direct_done status
+//Bit 1, vdin_nr_done status
+//Bit 0, field
+#define VDIN_COM_STATUS0 ((0x1205 << 2) + 0xff000000)
+//Readonly
+//Bit 31, vdi4 fifo overflow
+//Bit 29:24, vdi3_asfifo_cnt
+//Bit 23, vdi3 fifo overflow
+//Bit 21:16, vdi3_asfifo_cnt
+//Bit 15, vdi2 fifo overflow
+//Bit 13:8, vdi2_asfifo_cnt
+//Bit 7, vdi1 fifo overflow
+//Bit 5:0, vdi1_asfifo_cnt
+#define VDIN_COM_STATUS1 ((0x1206 << 2) + 0xff000000)
+//Bit 28:16 go_line_cnt_shadow, readonly
+//Bit 12:0 active_line_cnt_shadow, readonly
+#define VDIN_LCNT_SHADOW_STATUS ((0x1207 << 2) + 0xff000000)
+//each 8bit asfifo_ctrl is following:
+//Bit 7, DE enable
+//Bit 6, go field enable
+//Bit 5, go line enable
+//Bit 4, if true, negative active input vsync
+//Bit 3, if true, negative active input hsync
+//Bit 2, vsync soft reset fifo enable
+//Bit 1, overflow status clear
+//Bit 0 asfifo soft reset, level signal
+//Bit 7:0 vdi1 asfifo_ctrl
+//Bit 23:16 vdi2 asfifo_ctrl
+#define VDIN_ASFIFO_CTRL0 ((0x1208 << 2) + 0xff000000)
+//Bit 7:0 vdi3 asfifo_ctrl
+//Bit 23:16 vdi4 asfifo_ctrl
+#define VDIN_ASFIFO_CTRL1 ((0x1209 << 2) + 0xff000000)
+//Bit 28:16 input width minus 1, after the window function
+//Bit 12:0 output width minus 1
+#define VDIN_WIDTHM1I_WIDTHM1O ((0x120a << 2) + 0xff000000)
+//Bit 20:17 prehsc_mode, bit 3:2, prehsc odd line interp mode, bit 1:0, prehsc even line interp mode,
+// each 2bit, 00: pix0+pix1/2, average, 01: pix1, 10: pix0
+//Bit 16:15 sp422_mode, special mode for the component1 and component2, 00: normal case, 01: 32 64 32, 10: 0 64 64 0, 11: 16 96 16
+//Bit 14:8, hsc_ini_pixi_ptr, signed data, only useful when short_lineo_en is true
+//Bit 7, prehsc_en
+//Bit 6, hsc_en,
+//Bit 5, hsc_short_lineo_en, short line output enable
+//Bit 4, hsc_nearest_en
+//Bit 3, hsc_phase0_always_en
+//Bit 2:0, hsc_bank_length
+#define VDIN_SC_MISC_CTRL ((0x120b << 2) + 0xff000000)
+//Bit 28:24, integer portion
+//Bit 23:0, fraction portion
+#define VDIN_HSC_PHASE_STEP ((0x120c << 2) + 0xff000000)
+//Bit 30:29 hscale rpt_p0_num
+//Bit 28:24 hscale ini_rcv_num
+//Bit 23:0 hscale ini_phase
+#define VDIN_HSC_INI_CTRL ((0x120d << 2) + 0xff000000)
+//Read only
+//Bit 23, vdi7 fifo overflow
+//Bit 21:16, vdi7_asfifo_cnt
+//Bit 15, vdi6 fifo overflow
+//Bit 13:8, vdi6_asfifo_cnt
+//Bit 7, vdi5 fifo overflow
+//Bit 5:0, vdi5_asfifo_cnt
+#define VDIN_COM_STATUS2 ((0x120e << 2) + 0xff000000)
+//Bit 25:16 asfifo decimate control
+//Bit 25, if true, decimation counter sync with first valid DE in the field,
+//otherwise the decimation counter is not sync with external signal
+//Bit 24, decimation de enable
+//Bit 23:20, decimation phase, which counter value use to decimate,
+//Bit 19:16, decimation number, 0: not decimation, 1: decimation 2, 2: decimation 3 ....
+//Bit 7:0 vdi5 asfifo_ctrl
+#define VDIN_ASFIFO_CTRL2 ((0x120f << 2) + 0xff000000)
+//Bit 7, highlight_en
+//Bit 6 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix
+//Bit 5:4 probe_sel, 00: select matrix 0, 01: select matrix 1, otherwise select nothing
+//Bit 3:2, matrix coef idx selection, 00: select mat0, 01: select mat1, otherwise slect nothing
+//Bit 1 mat1 conversion matrix enable
+//Bit 0 mat0 conversion matrix enable
+#define VDIN_MATRIX_CTRL ((0x1210 << 2) + 0xff000000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define VDIN_MATRIX_COEF00_01 ((0x1211 << 2) + 0xff000000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define VDIN_MATRIX_COEF02_10 ((0x1212 << 2) + 0xff000000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define VDIN_MATRIX_COEF11_12 ((0x1213 << 2) + 0xff000000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define VDIN_MATRIX_COEF20_21 ((0x1214 << 2) + 0xff000000)
+//BIt 18:16 conv_rs
+//Bit 12:0 coef22
+#define VDIN_MATRIX_COEF22 ((0x1215 << 2) + 0xff000000)
+//Bit 26:16 offset0
+//Bit 10:0 offset1
+#define VDIN_MATRIX_OFFSET0_1 ((0x1216 << 2) + 0xff000000)
+//Bit 10:0 offset2
+#define VDIN_MATRIX_OFFSET2 ((0x1217 << 2) + 0xff000000)
+//Bit 26:16 pre_offset0
+//Bit 10:0 pre_offset1
+#define VDIN_MATRIX_PRE_OFFSET0_1 ((0x1218 << 2) + 0xff000000)
+//Bit 10:0 pre_offset2
+#define VDIN_MATRIX_PRE_OFFSET2 ((0x1219 << 2) + 0xff000000)
+//12:0 lfifo_buf_size
+#define VDIN_LFIFO_CTRL ((0x121a << 2) + 0xff000000)
+#define VDIN_COM_GCLK_CTRL ((0x121b << 2) + 0xff000000)
+//12:0 VDIN input interface width minus 1, before the window function, after the de decimation
+#define VDIN_INTF_WIDTHM1 ((0x121c << 2) + 0xff000000)
+//Bit 15 //default== 0, urgent_ctrl_en
+//Bit 14 //default== 0, urgent_wr, if true for write buffer
+//Bit 13 //default== 0, out_inv_en
+//Bit 12 //default == 0, urgent_ini_value
+//Bit 11:6 //default == 0, up_th up threshold
+//Bit 5:0 //default == 0, dn_th dn threshold
+#define VDIN_LFIFO_URG_CTRL ((0x121e << 2) + 0xff000000)
+//Bit 8, 1: discard data before line fifo, 0: normal mode
+//Bit 7:0 Write chroma canvas address
+#define VDIN_WR_CTRL2 ((0x121f << 2) + 0xff000000)
+//Bit 31:30 hconv_mode, Applicable only to bit[13:12]=0 or 2. 0: Output every even pixels' CbCr;
+// 1: Output every odd pixels' CbCr;
+// 2: Output an average value per even&odd pair of pixels;
+// 3: Output all CbCr. (This does NOT apply to bit[13:12]=0 -- 4:2:2 mode.)
+//Bit 29 no_clk_gate: disable vid_wr_mif clock gating function.
+//Bit 28 clear write response counter in the vdin write memory interface
+//Bit 27 eol_sel, 1: use eol as the line end indication, 0: use width as line end indication in the vdin write memory interface
+//Bit 26 vcp_nr_en. Only used in VDIN0. NOT used in VDIN1.
+//Bit 25 vcp_wr_en. Only used in VDIN0. NOT used in VDIN1.
+//Bit 24 vcp_in_en. Only used in VDIN0. NOT used in VDIN1.
+//Bit 23 vdin frame reset enble, if true, it will provide frame reset during go_field(vsync) to the modules after that
+//Bit 22 vdin line fifo soft reset enable, meaning, if true line fifo will reset during go_field (vsync)
+//Bit 21 vdin direct write done status clear bit
+//Bit 20 vdin NR write done status clear bit
+//Bit 18 swap_cbcr. Applicable only to bit[13:12]=2. 0: Output CbCr (NV12); 1: Output CrCb (NV21).
+//Bit 17:16 vconv_mode, Applicable only to bit[13:12]=2. 0: Output every even lines' CbCr;
+// 1: Output every odd lines' CbCr;
+// 2: Reserved;
+// 3: Output all CbCr.
+//Bit 13:12 vdin write format, 0: 4:2:2 to luma canvas, 1: 4:4:4 to luma canvas,
+// 2: Y to luma canvas, CbCr to chroma canvas. For NV12/21, also define Bit 31:30, 17:16, and bit 18.
+//Bit 11 vdin write canvas double buffer enable, means the canvas address will be latched by vsync before using
+//Bit 10 1: disable ctrl_reg write pulse which will reset internal counter. when bit 11 is 1, this bit should be 1.
+//Bit 9 vdin write request urgent
+//Bit 8 vdin write request enable
+//Bit 7:0 Write luma canvas address
+#define VDIN_WR_CTRL ((0x1220 << 2) + 0xff000000)
+//Bit 29, if true, horizontal reverse
+//Bit 28:16 start
+//Bit 12:0 end
+#define VDIN_WR_H_START_END ((0x1221 << 2) + 0xff000000)
+//Bit 29, if true, vertical reverse
+//Bit 28:16 start
+//Bit 15:13 field mode, 0 frame mode, 4 for field mode botton field, 5 for field mode top field, , 6 for blank line mode
+//Bit 12:0 end
+#define VDIN_WR_V_START_END ((0x1222 << 2) + 0xff000000)
+//Bit 24:20, integer portion
+//Bit 19:0, fraction portion
+#define VDIN_VSC_PHASE_STEP ((0x1223 << 2) + 0xff000000)
+//Bit 23, vsc_en, vertical scaler enable
+//Bit 22 if true, repeat last line while scaling, otherwise use the dummy data to extend the input picture
+//Bit 21 vsc_phase0_always_en, when scale up, you have to set it to 1
+//Bit 20:16 ini skip_line_num
+//Bit 15:0 vscaler ini_phase
+#define VDIN_VSC_INI_CTRL ((0x1224 << 2) + 0xff000000)
+//Bit 28:16, vshrink input height minus 1
+//Bit 12:0, scaler input height minus 1
+#define VDIN_SCIN_HEIGHTM1 ((0x1225 << 2) + 0xff000000)
+//Bit 23:16, dummy component 0
+//Bit 15:8, dummy component 1
+//Bit 7:0, dummy component 2
+#define VDIN_DUMMY_DATA ((0x1226 << 2) + 0xff000000)
+//Read only
+//Bit 29:20 component 0
+//Bit 19:10 component 1
+//Bit 9:0 component 2
+#define VDIN_MATRIX_PROBE_COLOR ((0x1228 << 2) + 0xff000000)
+//Bit 23:16 component 0
+//Bit 15:8 component 1
+//Bit 7:0 component 2
+#define VDIN_MATRIX_HL_COLOR ((0x1229 << 2) + 0xff000000)
+//28:16 probe x, postion
+//12:0 probe y, position
+#define VDIN_MATRIX_PROBE_POS ((0x122a << 2) + 0xff000000)
+#define VDIN_CHROMA_ADDR_PORT ((0x122b << 2) + 0xff000000)
+#define VDIN_CHROMA_DATA_PORT ((0x122c << 2) + 0xff000000)
+//
+#define VDIN_CM_BRI_CON_CTRL ((0x122d << 2) + 0xff000000)
+//Bit 17 clk_cyc_cnt_clr, if true, clear this register
+//Bit 16 if true, use vpu clock to count one line, otherwise use actually hsync to count line_cnt
+//Bit 15:0 line width using vpu clk
+#define VDIN_GO_LINE_CTRL ((0x122f << 2) + 0xff000000)
+//Bit 31:24 hist_pix_white_th, larger than this th is counted as white pixel
+//Bit 23:16 hist_pix_black_th, less than this th is counted as black pixel
+//Bit 11 hist_34bin_only, 34 bin only mode, including white/black
+//Bit 10:9 ldim_stts_din_sel, 00: from matrix0 dout, 01: from vsc_dout, 10: from matrix1 dout, 11: form matrix1 din
+//Bit 8 ldim_stts_en
+//Bit 6:5 hist_dnlp_low the real pixels in each bins got by VDIN_DNLP_HISTXX should multiple with 2^(dnlp_low+3)
+//Bit 3:2 hist_din_sel the source used for hist statistics. 00: from matrix0 dout, 01: from vsc_dout, 10: from matrix1 dout, 11: form matrix1 din
+//Bit 1 hist_win_en 1'b0: hist used for full picture; 1'b1: hist used for pixels within hist window
+//Bit 0 hist_spl_en 1'b0: disable hist readback; 1'b1: enable hist readback
+#define VDIN_HIST_CTRL ((0x1230 << 2) + 0xff000000)
+//Bit 28:16 hist_hstart horizontal start value to define hist window
+//Bit 12:0 hist_hend horizontal end value to define hist window
+#define VDIN_HIST_H_START_END ((0x1231 << 2) + 0xff000000)
+//Bit 28:16 hist_vstart vertical start value to define hist window
+//Bit 12:0 hist_vend vertical end value to define hist window
+#define VDIN_HIST_V_START_END ((0x1232 << 2) + 0xff000000)
+//Bit 15:8 hist_max maximum value
+//Bit 7:0 hist_min minimum value
+//read only
+#define VDIN_HIST_MAX_MIN ((0x1233 << 2) + 0xff000000)
+//Bit 31:0 hist_spl_rd
+//counts for the total luma value
+//read only
+#define VDIN_HIST_SPL_VAL ((0x1234 << 2) + 0xff000000)
+//Bit 21:0 hist_spl_pixel_count
+//counts for the total calculated pixels
+//read only
+#define VDIN_HIST_SPL_PIX_CNT ((0x1235 << 2) + 0xff000000)
+//Bit 31:0 hist_chroma_sum
+//counts for the total chroma value
+//read only
+#define VDIN_HIST_CHROMA_SUM ((0x1236 << 2) + 0xff000000)
+//Bit 31:16 higher hist bin
+//Bit 15:0 lower hist bin
+//0-255 are splited to 64 bins evenly, and VDIN_DNLP_HISTXX
+//are the statistic number of pixels that within each bin.
+//VDIN_DNLP_HIST00[15:0] counts for the first bin
+//VDIN_DNLP_HIST00[31:16] counts for the second bin
+//VDIN_DNLP_HIST01[15:0] counts for the third bin
+//VDIN_DNLP_HIST01[31:16] counts for the fourth bin
+//etc...
+//read only
+#define VDIN_DNLP_HIST00 ((0x1237 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST01 ((0x1238 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST02 ((0x1239 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST03 ((0x123a << 2) + 0xff000000)
+#define VDIN_DNLP_HIST04 ((0x123b << 2) + 0xff000000)
+#define VDIN_DNLP_HIST05 ((0x123c << 2) + 0xff000000)
+#define VDIN_DNLP_HIST06 ((0x123d << 2) + 0xff000000)
+#define VDIN_DNLP_HIST07 ((0x123e << 2) + 0xff000000)
+#define VDIN_DNLP_HIST08 ((0x123f << 2) + 0xff000000)
+#define VDIN_DNLP_HIST09 ((0x1240 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST10 ((0x1241 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST11 ((0x1242 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST12 ((0x1243 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST13 ((0x1244 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST14 ((0x1245 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST15 ((0x1246 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST16 ((0x1247 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST17 ((0x1248 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST18 ((0x1249 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST19 ((0x124a << 2) + 0xff000000)
+#define VDIN_DNLP_HIST20 ((0x124b << 2) + 0xff000000)
+#define VDIN_DNLP_HIST21 ((0x124c << 2) + 0xff000000)
+#define VDIN_DNLP_HIST22 ((0x124d << 2) + 0xff000000)
+#define VDIN_DNLP_HIST23 ((0x124e << 2) + 0xff000000)
+#define VDIN_DNLP_HIST24 ((0x124f << 2) + 0xff000000)
+#define VDIN_DNLP_HIST25 ((0x1250 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST26 ((0x1251 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST27 ((0x1252 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST28 ((0x1253 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST29 ((0x1254 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST30 ((0x1255 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST31 ((0x1256 << 2) + 0xff000000)
+//Bit 31, local dimming statistic enable
+//Bit 28, eol enable
+//Bit 27:25, vertical line overlap number for max finding
+//Bit 24:22, horizontal pixel overlap number, 0: 17 pix, 1: 9 pix, 2: 5 pix, 3: 3 pix, 4: 0 pix
+//Bit 20, 1,2,1 low pass filter enable before max/hist statistic
+//Bit 19:16, region H/V position index, refer to VDIN_LDIM_STTS_HIST_SET_REGION
+//Bit 15, 1: region read index auto increase per read to VDIN_LDIM_STTS_HIST_READ_REGION
+//Bit 6:0, region read index
+//`define VDIN_LDIM_STTS_HIST_REGION_IDX 8'h57
+//Bit 28:0, if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h0: read/write hvstart0
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h1: read/write hend01
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h2: read/write vend01
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h3: read/write hend23
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h4: read/write vend23
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h5: read/write hend45
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h6: read/write vend45
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'd7: read/write hend67
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h8: read/write vend67
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h9: read/write hend89
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'ha: read/write vend89
+//hvstart0, Bit 28:16 row0 vstart, Bit 12:0 col0 hstart
+//hend01, Bit 28:16 col1 hend, Bit 12:0 col0 hend
+//vend01, Bit 28:16 row1 vend, Bit 12:0 row0 vend
+//hend23, Bit 28:16 col3 hend, Bit 12:0 col2 hend
+//vend23, Bit 28:16 row3 vend, Bit 12:0 row2 vend
+//hend45, Bit 28:16 col5 hend, Bit 12:0 col4 hend
+//vend45, Bit 28:16 row5 vend, Bit 12:0 row4 vend
+//hend67, Bit 28:16 col7 hend, Bit 12:0 col6 hend
+//vend67, Bit 28:16 row7 vend, Bit 12:0 row6 vend
+//hend89, Bit 28:16 col9 hend, Bit 12:0 col8 hend
+//vend89, Bit 28:16 row9 vend, Bit 12:0 row8 vend
+//`define VDIN_LDIM_STTS_HIST_SET_REGION 8'h58
+//REGION STATISTIC DATA READ OUT PORT, bit 29:20 max_comp2, bit 19:10 max_comp1, bit 9:0 max_comp0
+//`define VDIN_LDIM_STTS_HIST_READ_REGION 8'h59
+//Bit 18, reset bit, high active
+//Bit 17, if true, widen hs/vs pulse
+//Bit 16 vsync total counter always accumulating enable
+//Bit 14:12, select hs/vs of video input channel to measure, 0: no selection, 1: vdi1, 2: vid2, 3: vid3, 4:vid4, 5:vdi5, 6:vid6, 7:vdi7, 8: vdi8
+//Bit 11:4, vsync_span, define how many vsync span need to measure
+//Bit 2:0 meas_hs_index, index to select which HS counter/range
+#define VDIN_MEAS_CTRL0 ((0x125a << 2) + 0xff000000)
+//Read only
+//19:16 meas_ind_total_count_n, every number of sync_span vsyncs, this count add 1
+//15:0 high bit portion of vsync total counter
+#define VDIN_MEAS_VS_COUNT_HI ((0x125b << 2) + 0xff000000)
+//Read only
+//31:0, low bit portion of vsync total counter
+#define VDIN_MEAS_VS_COUNT_LO ((0x125c << 2) + 0xff000000)
+//according to the meas_hs_index in register VDIN_MEAS_CTRL0
+//meas_hs_index == 0, first hs range
+//meas_hs_index == 1, second hs range
+//meas_hs_index == 2, third hs range
+//meas_hs_index == 3, fourth hs range
+//bit 28:16 count_start
+//bit 12:0 count_end
+#define VDIN_MEAS_HS_RANGE ((0x125d << 2) + 0xff000000)
+//Read only
+//according to the meas_hs_index in register VDIN_MEAS_CTRL0,
+//meas_hs_index == 0, first range hs counter,
+//meas_hs_index == 1, second range hs coutner
+//meas_hs_index == 2, third range hs coutner
+//meas_hs_index == 3, fourth range hs coutner
+//23:0
+#define VDIN_MEAS_HS_COUNT ((0x125e << 2) + 0xff000000)
+//Bit 8 white_enable
+//Bit 7:0 blkbar_white_level
+#define VDIN_BLKBAR_CTRL1 ((0x125f << 2) + 0xff000000)
+// Bit 31:24 blkbar_black_level threshold to judge a black point
+// Bit 23:21 Reserved
+// Bit 20:8 blkbar_hwidth left and right region width
+// Bit 7:5 blkbar_comp_sel select yin or uin or vin to be the valid input
+// Bit 4 blkbar_sw_statistic_en enable software statistic of each block black points number
+// Bit 3 blkbar_det_en
+// Bit 2:1 blkbar_din_sel
+// bit blkbar_det_top_en
+#define VDIN_BLKBAR_CTRL0 ((0x1260 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 blkbar_hstart. Left region start
+// Bit 15:13 Reserved
+// Bit 12:0 blkbar_hend. Right region end
+#define VDIN_BLKBAR_H_START_END ((0x1261 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 blkbar_vstart
+// Bit 15:13 Reserved
+// Bit 12:0 blkbar_vend
+#define VDIN_BLKBAR_V_START_END ((0x1262 << 2) + 0xff000000)
+// Bit 31:20 Reserved
+// Bit 19:0 blkbar_cnt_threshold. threshold to judge whether a block is totally black
+#define VDIN_BLKBAR_CNT_THRESHOLD ((0x1263 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 blkbar_row_th1. //threshold of the top blackbar
+// Bit 15:13 Reserved
+// bit 12:0 blkbar_row_th2 //threshold of the bottom blackbar
+#define VDIN_BLKBAR_ROW_TH1_TH2 ((0x1264 << 2) + 0xff000000)
+//Readonly
+// Bit 31:29 Reserved
+// Bit 28:16 blkbar_ind_left_start. horizontal start of the left region in the current searching
+// Bit 15:13 Reserved
+// Bit 12:0 blkbar_ind_left_end. horizontal end of the left region in the current searching
+#define VDIN_BLKBAR_IND_LEFT_START_END ((0x1265 << 2) + 0xff000000)
+//Readonly
+// Bit 31:29 Reserved
+// Bit 28:16 blkbar_ind_right_start.horizontal start of the right region in the current searching
+// Bit 15:13 Reserved
+// Bit 12:0 blkbar_ind_right_end. horizontal end of the right region in the current searching
+#define VDIN_BLKBAR_IND_RIGHT_START_END ((0x1266 << 2) + 0xff000000)
+//Readonly
+// Bit 31:20 Reserved
+// Bit 19:0 blkbar_ind_left1_cnt. Black pixel counter. left part of the left region
+#define VDIN_BLKBAR_IND_LEFT1_CNT ((0x1267 << 2) + 0xff000000)
+//Readonly
+// Bit 31:20 Reserved
+// Bit 19:0 blkbar_ind_left2_cnt. Black pixel counter. right part of the left region
+#define VDIN_BLKBAR_IND_LEFT2_CNT ((0x1268 << 2) + 0xff000000)
+//Readonly
+// Bit 31:20 Reserved
+// Bit 19:0 blkbar_ind_right1_cnt. Black pixel counter. left part of the right region
+#define VDIN_BLKBAR_IND_RIGHT1_CNT ((0x1269 << 2) + 0xff000000)
+//Readonly
+// Bit 31:20 Reserved
+// Bit 19:0 blkbar_ind_right2_cnt. Black pixel counter. right part of the right region
+#define VDIN_BLKBAR_IND_RIGHT2_CNT ((0x126a << 2) + 0xff000000)
+//Readonly
+// Bit 31:30 Resersed
+// Bit 29 blkbar_ind_black_det_done. LEFT/RIGHT Black detection done
+// Bit 28:16 blkbar_top_pos. Top black bar position
+// Bit 15:13 Reserved.
+// Bit 12:0 blkbar_bot_pos. Bottom black bar position
+#define VDIN_BLKBAR_STATUS0 ((0x126b << 2) + 0xff000000)
+//Readonly
+// Bit 31:29 Reserved
+// Bit 28:16 blkbar_left_pos. Left black bar posiont
+// Bit 15:13 Reserved
+// Bit 12:0 blkbar_right_pos. Right black bar position
+#define VDIN_BLKBAR_STATUS1 ((0x126c << 2) + 0xff000000)
+//Bit 28:16 input window H start
+//Bit 12:0 input window H end
+#define VDIN_WIN_H_START_END ((0x126d << 2) + 0xff000000)
+//Bit 28:16 input window H start
+//Bit 12:0 input window V start
+#define VDIN_WIN_V_START_END ((0x126e << 2) + 0xff000000)
+//Bit 23:16 vdi8 asfifo_ctrl
+//Bit 15:8 vdi7 asfifo_ctrl
+//Bit 7:0 vdi6 asfifo_ctrl
+#define VDIN_ASFIFO_CTRL3 ((0x126f << 2) + 0xff000000)
+//Bit 3:2 vshrk_clk2_ctrl
+//Bit 1:0 vshrk_clk1_ctrl
+#define VDIN_COM_GCLK_CTRL2 ((0x1270 << 2) + 0xff000000)
+//Bit 27 vshrk_en
+//Bit 26:25 vshrk_mode
+//Bit 24 vshrk_lpf_mode
+//Bit 23:0 vshrk_dummy
+#define VDIN_VSHRK_CTRL ((0x1271 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST32 ((0x1272 << 2) + 0xff000000)
+//Read only
+//Bit 7, vdi9 fifo overflow
+//Bit 5:0, vdi9_asfifo_cnt
+#define VDIN_COM_STATUS3 ((0x1273 << 2) + 0xff000000)
+#define VDIN_SYNC_MASK ((0x1274 << 2) + 0xff000000)
+//Bit 7:0, hsync_mask_num
+//Bit 15:8, vsync_mask_num
+//Bit 16, hsync_mask_enable
+//Bit 17, vsync_mask_num
+//dolby vdin
+#define VDIN_DOLBY_DSC_CTRL0 ((0x1275 << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_CTRL1 ((0x1276 << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_CTRL2 ((0x1277 << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_CTRL3 ((0x1278 << 2) + 0xff000000)
+#define VDIN_DOLBY_AXI_CTRL0 ((0x1279 << 2) + 0xff000000)
+#define VDIN_DOLBY_AXI_CTRL1 ((0x127a << 2) + 0xff000000)
+#define VDIN_DOLBY_AXI_CTRL2 ((0x127b << 2) + 0xff000000)
+#define VDIN_DOLBY_AXI_CTRL3 ((0x127c << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_STATUS0 ((0x127d << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_STATUS1 ((0x127e << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_STATUS2 ((0x127f << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_STATUS3 ((0x121d << 2) + 0xff000000)
+//hdr2 0x80 - -0xc0
+#define VDIN_HDR2_CTRL ((0x1280 << 2) + 0xff000000)
+#define VDIN_HDR2_CLK_GATE ((0x1281 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF00_01 ((0x1282 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF02_10 ((0x1283 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF11_12 ((0x1284 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF20_21 ((0x1285 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF22 ((0x1286 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF30_31 ((0x1287 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF32_40 ((0x1288 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF41_42 ((0x1289 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_OFFSET0_1 ((0x128a << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_OFFSET2 ((0x128b << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x128c << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_PRE_OFFSET2 ((0x128d << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF00_01 ((0x128e << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF02_10 ((0x128f << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF11_12 ((0x1290 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF20_21 ((0x1291 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF22 ((0x1292 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF30_31 ((0x1293 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF32_40 ((0x1294 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF41_42 ((0x1295 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_OFFSET0_1 ((0x1296 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_OFFSET2 ((0x1297 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x1298 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_PRE_OFFSET2 ((0x1299 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_CLIP ((0x129a << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_CLIP ((0x129b << 2) + 0xff000000)
+#define VDIN_HDR2_CGAIN_OFFT ((0x129c << 2) + 0xff000000)
+#define VDIN_EOTF_LUT_ADDR_PORT ((0x129e << 2) + 0xff000000)
+#define VDIN_EOTF_LUT_DATA_PORT ((0x129f << 2) + 0xff000000)
+#define VDIN_OETF_LUT_ADDR_PORT ((0x12a0 << 2) + 0xff000000)
+#define VDIN_OETF_LUT_DATA_PORT ((0x12a1 << 2) + 0xff000000)
+#define VDIN_CGAIN_LUT_ADDR_PORT ((0x12a2 << 2) + 0xff000000)
+#define VDIN_CGAIN_LUT_DATA_PORT ((0x12a3 << 2) + 0xff000000)
+#define VDIN_HDR2_CGAIN_COEF0 ((0x12a4 << 2) + 0xff000000)
+#define VDIN_HDR2_CGAIN_COEF1 ((0x12a5 << 2) + 0xff000000)
+#define VDIN_OGAIN_LUT_ADDR_PORT ((0x12a6 << 2) + 0xff000000)
+#define VDIN_OGAIN_LUT_DATA_PORT ((0x12a7 << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_CTRL ((0x12a8 << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_ALPHA0 ((0x12a9 << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_ALPHA1 ((0x12aa << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_BETA0 ((0x12ab << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_BETA1 ((0x12ac << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_BETA2 ((0x12ad << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_COEF0 ((0x12ae << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_COEF1 ((0x12af << 2) + 0xff000000)
+#define VDIN_HDR2_GMUT_CTRL ((0x12b0 << 2) + 0xff000000)
+#define VDIN_HDR2_GMUT_COEF0 ((0x12b1 << 2) + 0xff000000)
+#define VDIN_HDR2_GMUT_COEF1 ((0x12b2 << 2) + 0xff000000)
+#define VDIN_HDR2_GMUT_COEF2 ((0x12b3 << 2) + 0xff000000)
+#define VDIN_HDR2_GMUT_COEF3 ((0x12b4 << 2) + 0xff000000)
+#define VDIN_HDR2_GMUT_COEF4 ((0x12b5 << 2) + 0xff000000)
+#define VDIN_HDR2_PIPE_CTRL1 ((0x12b6 << 2) + 0xff000000)
+#define VDIN_HDR2_PIPE_CTRL2 ((0x12b7 << 2) + 0xff000000)
+#define VDIN_HDR2_PIPE_CTRL3 ((0x12b8 << 2) + 0xff000000)
+#define VDIN_HDR2_PROC_WIN1 ((0x12b9 << 2) + 0xff000000)
+#define VDIN_HDR2_PROC_WIN2 ((0x12ba << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_EN_CTRL ((0x12bb << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_EN_CTRL ((0x12bc << 2) + 0xff000000)
+#define VDIN_HDR2_HIST_CTRL ((0x12bd << 2) + 0xff000000)
+#define VDIN_HDR2_HIST_H_START_END ((0x12be << 2) + 0xff000000)
+#define VDIN_HDR2_HIST_V_START_END ((0x12bf << 2) + 0xff000000)
+#define VDIN_HDR2_HIST_RD ((0x129d << 2) + 0xff000000)
+#define VDIN_WRARB_MODE ((0x12c0 << 2) + 0xff000000)
+#define VDIN_WRARB_REQEN_SLV ((0x12c1 << 2) + 0xff000000)
+#define VDIN_WRARB_WEIGH0_SLV ((0x12c2 << 2) + 0xff000000)
+#define VDIN_WRARB_WEIGH1_SLV ((0x12c3 << 2) + 0xff000000)
+#define VDIN_RDWR_ARB_STATUS ((0x12c4 << 2) + 0xff000000)
+#define VDIN_ARB_DBG_CTRL ((0x12c5 << 2) + 0xff000000)
+#define VDIN_ARB_DBG_STAT ((0x12c6 << 2) + 0xff000000)
+#define VDIN_DBG_AXI_CMD_CNT ((0x12c7 << 2) + 0xff000000)
+#define VDIN_DBG_AXI_DAT_CNT ((0x12c8 << 2) + 0xff000000)
+#define VDIN_CRC_CTRL ((0x12c9 << 2) + 0xff000000)
+#define VDIN_RO_CRC ((0x12ca << 2) + 0xff000000)
+#define VDIN_LINE_INT ((0x12cb << 2) + 0xff000000)
+#define VDIN_WR_URGENT_CTRL ((0x1257 << 2) + 0xff000000)
+#define VDIN_RO_WRMIF_STATUS ((0x1258 << 2) + 0xff000000)
+//for vdin dolby descramble start
+#define VDIN_DSC_CTRL ((0x12d0 << 2) + 0xff000000)
+//Bit 31:10 reserved
+//Bit 9:4 reg_dithout_switch ,uns, default = 36;//{2'h2,2'h1,2'h0}
+//Bit 3, reg_detunnel_en ,uns, default = 1;
+//Bit 2, reg_detunnel_u_start,uns, default = 0;
+//Bit 1, reg_vdin_dith_en ,uns, default = 1;
+//Bit 0, reg_descramble_en ,uns, default = 1;
+#define VDIN_CFMT_CTRL ((0x12d1 << 2) + 0xff000000)
+//Bit 31:9 reserved
+//Bit 8 reg_chfmt_rpt_pix uns, default = 0 ; // if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
+//Bit 7:4 reg_chfmt_ini_phase uns, default = 0 ; // horizontal formatter initial phase
+//Bit 3 reg_chfmt_rpt_p0_en uns, default = 0 ; // horizontal formatter repeat pixel 0 enable
+//Bit 2:1 reg_chfmt_yc_ratio uns, default = 1 ; // horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
+//Bit 0 reg_chfmt_en uns, default = 1 ; // horizontal formatter enable
+#define VDIN_CFMT_W ((0x12d2 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_chfmt_w uns, default = 1920 ;horizontal formatter width
+//Bit 15:13 reserved
+//Bit 12:0 reg_cvfmt_w uns, default = 960 ;vertical formatter width
+#define VDIN_SCB_CTRL0 ((0x12d3 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_444c422_gofield_en uns, default = 1;
+//Bit 10 reg_tunnel_en uns, default = 1;
+//Bit 9:4 reg_tunnel_outswitch uns, default = 36;//{2'h2,2'h1,2'h0}
+//Bit 3:2 reg_444c422_mode uns, default = 0; //0:left 1:right 2,3:avg
+//Bit 1 reg_444c422_bypass uns, default = 0; 1:bypass
+//Bit 0 reserved //pulse for frm_en
+#define VDIN_SCB_CTRL1 ((0x12d4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_444c422_hsize uns, default = 1920 ;horizontal size
+//Bit 15:13 reserved
+//Bit 12:0 reg_444c422_vsize uns, default = 960 ;vertical size
+#define VDIN_DSC_HSIZE ((0x12d5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_detunnel_hsize uns, default = 1920 ;
+//Bit 15:13 reserved
+//Bit 12:0 reg_dither_hsize uns, default = 1920 ;
+#define VDIN_DSC_DETUNNEL_SEL ((0x12d6 << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:0 reg_detunnel_sel uns, default = 34658; //{3'h1,3'h0,3'h3 ,3'h5,3'h4,3'h2}
+#define VDIN_DSC_TUNNEL_SEL ((0x12d7 << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:0 reg_tunnel_sel uns, default = 69868; //= {3'h2,3'h1 ,3'h0,3'h3 ,3'h5,3'h4};
+#define VDIN_HDR2_SIZE ((0x12d8 << 2) + 0xff000000)
+#define VDIN_VSHRK_SIZE_M1 ((0x12d9 << 2) + 0xff000000)
+//dither
+#define VDIN_DITH_CTRL ((0x12e0 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_1 ((0x12e1 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_2 ((0x12e2 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_3 ((0x12e3 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_4 ((0x12e4 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_5 ((0x12e5 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_6 ((0x12e6 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_7 ((0x12e7 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_8 ((0x12e8 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_9 ((0x12e9 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_10 ((0x12ea << 2) + 0xff000000)
+#define VDIN_DITH_LUT_11 ((0x12eb << 2) + 0xff000000)
+#define VDIN_DITH_LUT_12 ((0x12ec << 2) + 0xff000000)
+//for vdin dolby descramble end
+#define VDIN_HSK_CTRL ((0x12ef << 2) + 0xff000000)
+//Bit 31:23 reserved
+//Bit 22:16 reg_hsk_size ,uns, default = 4;
+//Bit 15:13 reserved
+//Bit 12:0 reg_frm_hsize ,uns, default = 1920;
+#define VDIN_HSK_COEF_0 ((0x12f0 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef00 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_1 ((0x12f1 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef01 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_2 ((0x12f2 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef02 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_3 ((0x12f3 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef03 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+//
+#define VDIN_HSK_COEF_4 ((0x12f4 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef04 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_5 ((0x12f5 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef05 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_6 ((0x12f6 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef06 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_7 ((0x12f7 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef07 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+//
+#define VDIN_HSK_COEF_8 ((0x12f8 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef08 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_9 ((0x12f9 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef09 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_A ((0x12fa << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef10 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_B ((0x12fb << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef11 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+//
+#define VDIN_HSK_COEF_C ((0x12fc << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef12 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_D ((0x12fd << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef13 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_E ((0x12fe << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef14 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_F ((0x12ff << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef15 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_vdin_regs.h
+//
+
+//8'h72 occupied by histogram 32
+//VDIN0 8'h00 - 8'h7f
+#define VDIN0_SCALE_COEF_IDX (VDIN_SCALE_COEF_IDX )
+#define VDIN0_SCALE_COEF (VDIN_SCALE_COEF )
+#define VDIN0_COM_CTRL0 (VDIN_COM_CTRL0 )
+#define VDIN0_ACTIVE_MAX_PIX_CNT_STATUS (VDIN_ACTIVE_MAX_PIX_CNT_STATUS )
+#define VDIN0_LCNT_STATUS (VDIN_LCNT_STATUS )
+#define VDIN0_COM_STATUS0 (VDIN_COM_STATUS0 )
+#define VDIN0_COM_STATUS1 (VDIN_COM_STATUS1 )
+#define VDIN0_LCNT_SHADOW_STATUS (VDIN_LCNT_SHADOW_STATUS )
+#define VDIN0_ASFIFO_CTRL0 (VDIN_ASFIFO_CTRL0 )
+#define VDIN0_ASFIFO_CTRL1 (VDIN_ASFIFO_CTRL1 )
+#define VDIN0_WIDTHM1I_WIDTHM1O (VDIN_WIDTHM1I_WIDTHM1O )
+#define VDIN0_SC_MISC_CTRL (VDIN_SC_MISC_CTRL )
+#define VDIN0_HSC_PHASE_STEP (VDIN_HSC_PHASE_STEP )
+#define VDIN0_HSC_INI_CTRL (VDIN_HSC_INI_CTRL )
+#define VDIN0_COM_STATUS2 (VDIN_COM_STATUS2 )
+#define VDIN0_COM_STATUS3 (VDIN_COM_STATUS3 )
+#define VDIN0_ASFIFO_CTRL2 (VDIN_ASFIFO_CTRL2 )
+#define VDIN0_MATRIX_CTRL (VDIN_MATRIX_CTRL )
+#define VDIN0_MATRIX_COEF00_01 (VDIN_MATRIX_COEF00_01 )
+#define VDIN0_MATRIX_COEF02_10 (VDIN_MATRIX_COEF02_10 )
+#define VDIN0_MATRIX_COEF11_12 (VDIN_MATRIX_COEF11_12 )
+#define VDIN0_MATRIX_COEF20_21 (VDIN_MATRIX_COEF20_21 )
+#define VDIN0_MATRIX_COEF22 (VDIN_MATRIX_COEF22 )
+#define VDIN0_MATRIX_OFFSET0_1 (VDIN_MATRIX_OFFSET0_1 )
+#define VDIN0_MATRIX_OFFSET2 (VDIN_MATRIX_OFFSET2 )
+#define VDIN0_MATRIX_PRE_OFFSET0_1 (VDIN_MATRIX_PRE_OFFSET0_1 )
+#define VDIN0_MATRIX_PRE_OFFSET2 (VDIN_MATRIX_PRE_OFFSET2 )
+#define VDIN0_LFIFO_CTRL (VDIN_LFIFO_CTRL )
+#define VDIN0_COM_GCLK_CTRL (VDIN_COM_GCLK_CTRL )
+#define VDIN0_INTF_WIDTHM1 (VDIN_INTF_WIDTHM1 )
+#define VDIN0_WR_CTRL2 (VDIN_WR_CTRL2 )
+#define VDIN0_WR_CTRL (VDIN_WR_CTRL )
+#define VDIN0_WR_H_START_END (VDIN_WR_H_START_END )
+#define VDIN0_WR_V_START_END (VDIN_WR_V_START_END )
+#define VDIN0_VSC_PHASE_STEP (VDIN_VSC_PHASE_STEP )
+#define VDIN0_VSC_INI_CTRL (VDIN_VSC_INI_CTRL )
+#define VDIN0_SCIN_HEIGHTM1 (VDIN_SCIN_HEIGHTM1 )
+#define VDIN0_DUMMY_DATA (VDIN_DUMMY_DATA )
+#define VDIN0_MATRIX_PROBE_COLOR (VDIN_MATRIX_PROBE_COLOR )
+#define VDIN0_MATRIX_HL_COLOR (VDIN_MATRIX_HL_COLOR )
+#define VDIN0_MATRIX_PROBE_POS (VDIN_MATRIX_PROBE_POS )
+#define VDIN0_CHROMA_ADDR_PORT (VDIN_CHROMA_ADDR_PORT )
+#define VDIN0_CHROMA_DATA_PORT (VDIN_CHROMA_DATA_PORT )
+#define VDIN0_CM_BRI_CON_CTRL (VDIN_CM_BRI_CON_CTRL )
+#define VDIN0_GO_LINE_CTRL (VDIN_GO_LINE_CTRL )
+#define VDIN0_HIST_CTRL (VDIN_HIST_CTRL )
+#define VDIN0_HIST_H_START_END (VDIN_HIST_H_START_END )
+#define VDIN0_HIST_V_START_END (VDIN_HIST_V_START_END )
+#define VDIN0_HIST_MAX_MIN (VDIN_HIST_MAX_MIN )
+#define VDIN0_HIST_SPL_VAL (VDIN_HIST_SPL_VAL )
+#define VDIN0_HIST_SPL_PIX_CNT (VDIN_HIST_SPL_PIX_CNT )
+#define VDIN0_HIST_CHROMA_SUM (VDIN_HIST_CHROMA_SUM )
+#define VDIN0_DNLP_HIST00 (VDIN_DNLP_HIST00 )
+#define VDIN0_DNLP_HIST01 (VDIN_DNLP_HIST01 )
+#define VDIN0_DNLP_HIST02 (VDIN_DNLP_HIST02 )
+#define VDIN0_DNLP_HIST03 (VDIN_DNLP_HIST03 )
+#define VDIN0_DNLP_HIST04 (VDIN_DNLP_HIST04 )
+#define VDIN0_DNLP_HIST05 (VDIN_DNLP_HIST05 )
+#define VDIN0_DNLP_HIST06 (VDIN_DNLP_HIST06 )
+#define VDIN0_DNLP_HIST07 (VDIN_DNLP_HIST07 )
+#define VDIN0_DNLP_HIST08 (VDIN_DNLP_HIST08 )
+#define VDIN0_DNLP_HIST09 (VDIN_DNLP_HIST09 )
+#define VDIN0_DNLP_HIST10 (VDIN_DNLP_HIST10 )
+#define VDIN0_DNLP_HIST11 (VDIN_DNLP_HIST11 )
+#define VDIN0_DNLP_HIST12 (VDIN_DNLP_HIST12 )
+#define VDIN0_DNLP_HIST13 (VDIN_DNLP_HIST13 )
+#define VDIN0_DNLP_HIST14 (VDIN_DNLP_HIST14 )
+#define VDIN0_DNLP_HIST15 (VDIN_DNLP_HIST15 )
+#define VDIN0_DNLP_HIST16 (VDIN_DNLP_HIST16 )
+#define VDIN0_DNLP_HIST17 (VDIN_DNLP_HIST17 )
+#define VDIN0_DNLP_HIST18 (VDIN_DNLP_HIST18 )
+#define VDIN0_DNLP_HIST19 (VDIN_DNLP_HIST19 )
+#define VDIN0_DNLP_HIST20 (VDIN_DNLP_HIST20 )
+#define VDIN0_DNLP_HIST21 (VDIN_DNLP_HIST21 )
+#define VDIN0_DNLP_HIST22 (VDIN_DNLP_HIST22 )
+#define VDIN0_DNLP_HIST23 (VDIN_DNLP_HIST23 )
+#define VDIN0_DNLP_HIST24 (VDIN_DNLP_HIST24 )
+#define VDIN0_DNLP_HIST25 (VDIN_DNLP_HIST25 )
+#define VDIN0_DNLP_HIST26 (VDIN_DNLP_HIST26 )
+#define VDIN0_DNLP_HIST27 (VDIN_DNLP_HIST27 )
+#define VDIN0_DNLP_HIST28 (VDIN_DNLP_HIST28 )
+#define VDIN0_DNLP_HIST29 (VDIN_DNLP_HIST29 )
+#define VDIN0_DNLP_HIST30 (VDIN_DNLP_HIST30 )
+#define VDIN0_DNLP_HIST31 (VDIN_DNLP_HIST31 )
+#define VDIN0_DNLP_HIST32 (VDIN_DNLP_HIST32 )
+#define VDIN0_MEAS_CTRL0 (VDIN_MEAS_CTRL0 )
+#define VDIN0_MEAS_VS_COUNT_HI (VDIN_MEAS_VS_COUNT_HI )
+#define VDIN0_MEAS_VS_COUNT_LO (VDIN_MEAS_VS_COUNT_LO )
+#define VDIN0_MEAS_HS_RANGE (VDIN_MEAS_HS_RANGE )
+#define VDIN0_MEAS_HS_COUNT (VDIN_MEAS_HS_COUNT )
+#define VDIN0_BLKBAR_CTRL1 (VDIN_BLKBAR_CTRL1 )
+#define VDIN0_BLKBAR_CTRL0 (VDIN_BLKBAR_CTRL0 )
+#define VDIN0_BLKBAR_H_START_END (VDIN_BLKBAR_H_START_END )
+#define VDIN0_BLKBAR_V_START_END (VDIN_BLKBAR_V_START_END )
+#define VDIN0_BLKBAR_CNT_THRESHOLD (VDIN_BLKBAR_CNT_THRESHOLD )
+#define VDIN0_BLKBAR_ROW_TH1_TH2 (VDIN_BLKBAR_ROW_TH1_TH2 )
+#define VDIN0_BLKBAR_IND_LEFT_START_END (VDIN_BLKBAR_IND_LEFT_START_END )
+#define VDIN0_BLKBAR_IND_RIGHT_START_END (VDIN_BLKBAR_IND_RIGHT_START_END )
+#define VDIN0_BLKBAR_IND_LEFT1_CNT (VDIN_BLKBAR_IND_LEFT1_CNT )
+#define VDIN0_BLKBAR_IND_LEFT2_CNT (VDIN_BLKBAR_IND_LEFT2_CNT )
+#define VDIN0_BLKBAR_IND_RIGHT1_CNT (VDIN_BLKBAR_IND_RIGHT1_CNT )
+#define VDIN0_BLKBAR_IND_RIGHT2_CNT (VDIN_BLKBAR_IND_RIGHT2_CNT )
+#define VDIN0_BLKBAR_STATUS0 (VDIN_BLKBAR_STATUS0 )
+#define VDIN0_BLKBAR_STATUS1 (VDIN_BLKBAR_STATUS1 )
+#define VDIN0_WIN_H_START_END (VDIN_WIN_H_START_END )
+#define VDIN0_WIN_V_START_END (VDIN_WIN_V_START_END )
+#define VDIN0_ASFIFO_CTRL3 (VDIN_ASFIFO_CTRL3 )
+#define VDIN0_LFIFO_URG_CTRL (VDIN_LFIFO_URG_CTRL )
+#define VDIN0_COM_GCLK_CTRL2 (VDIN_COM_GCLK_CTRL2 )
+#define VDIN0_VSHRK_CTRL (VDIN_VSHRK_CTRL )
+#define VDIN0_SYNC_MASK (VDIN_SYNC_MASK )
+#define VDIN0_DOLBY_DSC_CTRL0 (VDIN_DOLBY_DSC_CTRL0 )
+#define VDIN0_DOLBY_DSC_CTRL1 (VDIN_DOLBY_DSC_CTRL1 )
+#define VDIN0_DOLBY_DSC_CTRL2 (VDIN_DOLBY_DSC_CTRL2 )
+#define VDIN0_DOLBY_DSC_CTRL3 (VDIN_DOLBY_DSC_CTRL3 )
+#define VDIN0_DOLBY_AXI_CTRL0 (VDIN_DOLBY_AXI_CTRL0 )
+#define VDIN0_DOLBY_AXI_CTRL1 (VDIN_DOLBY_AXI_CTRL1 )
+#define VDIN0_DOLBY_AXI_CTRL2 (VDIN_DOLBY_AXI_CTRL2 )
+#define VDIN0_DOLBY_AXI_CTRL3 (VDIN_DOLBY_AXI_CTRL3 )
+#define VDIN0_DOLBY_DSC_STATUS0 (VDIN_DOLBY_DSC_STATUS0)
+#define VDIN0_DOLBY_DSC_STATUS1 (VDIN_DOLBY_DSC_STATUS1)
+#define VDIN0_DOLBY_DSC_STATUS2 (VDIN_DOLBY_DSC_STATUS2)
+#define VDIN0_DOLBY_DSC_STATUS3 (VDIN_DOLBY_DSC_STATUS3)
+#define VDIN0_HDR2_CTRL VDIN_HDR2_CTRL
+#define VDIN0_HDR2_CLK_GATE VDIN_HDR2_CLK_GATE
+#define VDIN0_HDR2_MATRIXI_COEF00_01 VDIN_HDR2_MATRIXI_COEF00_01
+#define VDIN0_HDR2_MATRIXI_COEF02_10 VDIN_HDR2_MATRIXI_COEF02_10
+#define VDIN0_HDR2_MATRIXI_COEF11_12 VDIN_HDR2_MATRIXI_COEF11_12
+#define VDIN0_HDR2_MATRIXI_COEF20_21 VDIN_HDR2_MATRIXI_COEF20_21
+#define VDIN0_HDR2_MATRIXI_COEF22 VDIN_HDR2_MATRIXI_COEF22
+#define VDIN0_HDR2_MATRIXI_COEF30_31 VDIN_HDR2_MATRIXI_COEF30_31
+#define VDIN0_HDR2_MATRIXI_COEF32_40 VDIN_HDR2_MATRIXI_COEF32_40
+#define VDIN0_HDR2_MATRIXI_COEF41_42 VDIN_HDR2_MATRIXI_COEF41_42
+#define VDIN0_HDR2_MATRIXI_OFFSET0_1 VDIN_HDR2_MATRIXI_OFFSET0_1
+#define VDIN0_HDR2_MATRIXI_OFFSET2 VDIN_HDR2_MATRIXI_OFFSET2
+#define VDIN0_HDR2_MATRIXI_PRE_OFFSET0_1 VDIN_HDR2_MATRIXI_PRE_OFFSET0_1
+#define VDIN0_HDR2_MATRIXI_PRE_OFFSET2 VDIN_HDR2_MATRIXI_PRE_OFFSET2
+#define VDIN0_HDR2_MATRIXO_COEF00_01 VDIN_HDR2_MATRIXO_COEF00_01
+#define VDIN0_HDR2_MATRIXO_COEF02_10 VDIN_HDR2_MATRIXO_COEF02_10
+#define VDIN0_HDR2_MATRIXO_COEF11_12 VDIN_HDR2_MATRIXO_COEF11_12
+#define VDIN0_HDR2_MATRIXO_COEF20_21 VDIN_HDR2_MATRIXO_COEF20_21
+#define VDIN0_HDR2_MATRIXO_COEF22 VDIN_HDR2_MATRIXO_COEF22
+#define VDIN0_HDR2_MATRIXO_COEF30_31 VDIN_HDR2_MATRIXO_COEF30_31
+#define VDIN0_HDR2_MATRIXO_COEF32_40 VDIN_HDR2_MATRIXO_COEF32_40
+#define VDIN0_HDR2_MATRIXO_COEF41_42 VDIN_HDR2_MATRIXO_COEF41_42
+#define VDIN0_HDR2_MATRIXO_OFFSET0_1 VDIN_HDR2_MATRIXO_OFFSET0_1
+#define VDIN0_HDR2_MATRIXO_OFFSET2 VDIN_HDR2_MATRIXO_OFFSET2
+#define VDIN0_HDR2_MATRIXO_PRE_OFFSET0_1 VDIN_HDR2_MATRIXO_PRE_OFFSET0_1
+#define VDIN0_HDR2_MATRIXO_PRE_OFFSET2 VDIN_HDR2_MATRIXO_PRE_OFFSET2
+#define VDIN0_HDR2_MATRIXI_CLIP VDIN_HDR2_MATRIXI_CLIP
+#define VDIN0_HDR2_MATRIXO_CLIP VDIN_HDR2_MATRIXO_CLIP
+#define VDIN0_HDR2_CGAIN_OFFT VDIN_HDR2_CGAIN_OFFT
+#define VDIN0_EOTF_LUT_ADDR_PORT VDIN_EOTF_LUT_ADDR_PORT
+#define VDIN0_EOTF_LUT_DATA_PORT VDIN_EOTF_LUT_DATA_PORT
+#define VDIN0_OETF_LUT_ADDR_PORT VDIN_OETF_LUT_ADDR_PORT
+#define VDIN0_OETF_LUT_DATA_PORT VDIN_OETF_LUT_DATA_PORT
+#define VDIN0_OGAIN_LUT_ADDR_PORT VDIN_OGAIN_LUT_ADDR_PORT
+#define VDIN0_OGAIN_LUT_DATA_PORT VDIN_OGAIN_LUT_DATA_PORT
+#define VDIN0_CGAIN_LUT_ADDR_PORT VDIN_CGAIN_LUT_ADDR_PORT
+#define VDIN0_CGAIN_LUT_DATA_PORT VDIN_CGAIN_LUT_DATA_PORT
+#define VDIN0_HDR2_CGAIN_COEF0 VDIN_HDR2_CGAIN_COEF0
+#define VDIN0_HDR2_CGAIN_COEF1 VDIN_HDR2_CGAIN_COEF1
+#define VDIN0_HDR2_ADPS_CTRL VDIN_HDR2_ADPS_CTRL
+#define VDIN0_HDR2_ADPS_ALPHA0 VDIN_HDR2_ADPS_ALPHA0
+#define VDIN0_HDR2_ADPS_ALPHA1 VDIN_HDR2_ADPS_ALPHA1
+#define VDIN0_HDR2_ADPS_BETA0 VDIN_HDR2_ADPS_BETA0
+#define VDIN0_HDR2_ADPS_BETA1 VDIN_HDR2_ADPS_BETA1
+#define VDIN0_HDR2_ADPS_BETA2 VDIN_HDR2_ADPS_BETA2
+#define VDIN0_HDR2_ADPS_COEF0 VDIN_HDR2_ADPS_COEF0
+#define VDIN0_HDR2_ADPS_COEF1 VDIN_HDR2_ADPS_COEF1
+#define VDIN0_HDR2_GMUT_CTRL VDIN_HDR2_GMUT_CTRL
+#define VDIN0_HDR2_GMUT_COEF0 VDIN_HDR2_GMUT_COEF0
+#define VDIN0_HDR2_GMUT_COEF1 VDIN_HDR2_GMUT_COEF1
+#define VDIN0_HDR2_GMUT_COEF2 VDIN_HDR2_GMUT_COEF2
+#define VDIN0_HDR2_GMUT_COEF3 VDIN_HDR2_GMUT_COEF3
+#define VDIN0_HDR2_GMUT_COEF4 VDIN_HDR2_GMUT_COEF4
+#define VDIN0_HDR2_PIPE_CTRL1 VDIN_HDR2_PIPE_CTRL1
+#define VDIN0_HDR2_PIPE_CTRL2 VDIN_HDR2_PIPE_CTRL2
+#define VDIN0_HDR2_PIPE_CTRL3 VDIN_HDR2_PIPE_CTRL3
+#define VDIN0_HDR2_PROC_WIN1 VDIN_HDR2_PROC_WIN1
+#define VDIN0_HDR2_PROC_WIN2 VDIN_HDR2_PROC_WIN2
+#define VDIN0_HDR2_MATRIXI_EN_CTRL VDIN_HDR2_MATRIXI_EN_CTRL
+#define VDIN0_HDR2_MATRIXO_EN_CTRL VDIN_HDR2_MATRIXO_EN_CTRL
+#define VDIN0_HDR2_HIST_CTRL VDIN_HDR2_HIST_CTRL
+#define VDIN0_HDR2_HIST_H_START_END VDIN_HDR2_HIST_H_START_END
+#define VDIN0_HDR2_HIST_V_START_END VDIN_HDR2_HIST_V_START_END
+#define VDIN0_HDR2_HIST_RD VDIN_HDR2_HIST_RD
+
+
+#define VDIN0_CRC_CTRL (VDIN_CRC_CTRL)
+#define VDIN0_RO_CRC (VDIN_RO_CRC )
+#define VDIN0_LINE_INT (VDIN_LINE_INT)
+#define VDIN0_WR_URGENT_CTRL (VDIN_WR_URGENT_CTRL)
+#define VDIN0_RO_WRMIF_STATUS (VDIN_RO_WRMIF_STATUS)
+
+#define VDIN0_DSC_CTRL VDIN_DSC_CTRL
+#define VDIN0_CFMT_CTRL VDIN_CFMT_CTRL
+#define VDIN0_CFMT_W VDIN_CFMT_W
+#define VDIN0_SCB_CTRL0 VDIN_SCB_CTRL0
+#define VDIN0_SCB_CTRL1 VDIN_SCB_CTRL1
+#define VDIN0_DSC_HSIZE VDIN_DSC_HSIZE
+#define VDIN0_DSC_DETUNNEL_SEL VDIN_DSC_DETUNNEL_SEL
+#define VDIN0_DSC_TUNNEL_SEL VDIN_DSC_TUNNEL_SEL
+#define VDIN0_DITH_CTRL VDIN_DITH_CTRL
+#define VDIN0_DITH_LUT_1 VDIN_DITH_LUT_1
+#define VDIN0_DITH_LUT_2 VDIN_DITH_LUT_2
+#define VDIN0_DITH_LUT_3 VDIN_DITH_LUT_3
+#define VDIN0_DITH_LUT_4 VDIN_DITH_LUT_4
+#define VDIN0_DITH_LUT_5 VDIN_DITH_LUT_5
+#define VDIN0_DITH_LUT_6 VDIN_DITH_LUT_6
+#define VDIN0_DITH_LUT_7 VDIN_DITH_LUT_7
+#define VDIN0_DITH_LUT_8 VDIN_DITH_LUT_8
+#define VDIN0_DITH_LUT_9 VDIN_DITH_LUT_9
+#define VDIN0_DITH_LUT_10 VDIN_DITH_LUT_10
+#define VDIN0_DITH_LUT_11 VDIN_DITH_LUT_11
+#define VDIN0_DITH_LUT_12 VDIN_DITH_LUT_12
+
+#define VDIN0_HSK_CTRL VDIN_HSK_CTRL
+#define VDIN0_HSK_COEF_0 VDIN_HSK_COEF_0
+#define VDIN0_HSK_COEF_1 VDIN_HSK_COEF_1
+#define VDIN0_HSK_COEF_2 VDIN_HSK_COEF_2
+#define VDIN0_HSK_COEF_3 VDIN_HSK_COEF_3
+#define VDIN0_HSK_COEF_4 VDIN_HSK_COEF_4
+#define VDIN0_HSK_COEF_5 VDIN_HSK_COEF_5
+#define VDIN0_HSK_COEF_6 VDIN_HSK_COEF_6
+#define VDIN0_HSK_COEF_7 VDIN_HSK_COEF_7
+#define VDIN0_HSK_COEF_8 VDIN_HSK_COEF_8
+#define VDIN0_HSK_COEF_9 VDIN_HSK_COEF_9
+#define VDIN0_HSK_COEF_A VDIN_HSK_COEF_A
+#define VDIN0_HSK_COEF_B VDIN_HSK_COEF_B
+#define VDIN0_HSK_COEF_C VDIN_HSK_COEF_C
+#define VDIN0_HSK_COEF_D VDIN_HSK_COEF_D
+#define VDIN0_HSK_COEF_E VDIN_HSK_COEF_E
+#define VDIN0_HSK_COEF_F VDIN_HSK_COEF_F
+
+#define VDIN0_HDR2_SIZE VDIN_HDR2_SIZE
+#define VDIN0_VSHRK_SIZE_M1 VDIN_VSHRK_SIZE_M1
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_vdin0_regs.h
+//
+//
+// Reading file: vpu_vdin1_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+// VDIN
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VDIN1_VCBUS_BASE = 0x13
+// -----------------------------------------------
+#define VDIN1_OFFSET (0x100)
+// `include "vpu_vdin_regs.h"
+//8'h72 occupied by histogram 32
+//VDIN1 8'h00 - 8'h7f
+#define VDIN1_SCALE_COEF_IDX ((VDIN1_OFFSET << 2) + VDIN_SCALE_COEF_IDX )
+#define VDIN1_SCALE_COEF ((VDIN1_OFFSET << 2) + VDIN_SCALE_COEF )
+#define VDIN1_COM_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_COM_CTRL0 )
+#define VDIN1_ACTIVE_MAX_PIX_CNT_STATUS ((VDIN1_OFFSET << 2) + VDIN_ACTIVE_MAX_PIX_CNT_STATUS )
+#define VDIN1_LCNT_STATUS ((VDIN1_OFFSET << 2) + VDIN_LCNT_STATUS )
+#define VDIN1_COM_STATUS0 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS0 )
+#define VDIN1_COM_STATUS1 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS1 )
+#define VDIN1_LCNT_SHADOW_STATUS ((VDIN1_OFFSET << 2) + VDIN_LCNT_SHADOW_STATUS )
+#define VDIN1_ASFIFO_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL0 )
+#define VDIN1_ASFIFO_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL1 )
+#define VDIN1_WIDTHM1I_WIDTHM1O ((VDIN1_OFFSET << 2) + VDIN_WIDTHM1I_WIDTHM1O )
+#define VDIN1_SC_MISC_CTRL ((VDIN1_OFFSET << 2) + VDIN_SC_MISC_CTRL )
+#define VDIN1_HSC_PHASE_STEP ((VDIN1_OFFSET << 2) + VDIN_HSC_PHASE_STEP )
+#define VDIN1_HSC_INI_CTRL ((VDIN1_OFFSET << 2) + VDIN_HSC_INI_CTRL )
+#define VDIN1_COM_STATUS2 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS2 )
+#define VDIN1_COM_STATUS3 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS3 )
+#define VDIN1_ASFIFO_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL2 )
+#define VDIN1_MATRIX_CTRL ((VDIN1_OFFSET << 2) + VDIN_MATRIX_CTRL )
+#define VDIN1_MATRIX_COEF00_01 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF00_01 )
+#define VDIN1_MATRIX_COEF02_10 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF02_10 )
+#define VDIN1_MATRIX_COEF11_12 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF11_12 )
+#define VDIN1_MATRIX_COEF20_21 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF20_21 )
+#define VDIN1_MATRIX_COEF22 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF22 )
+#define VDIN1_MATRIX_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_OFFSET0_1 )
+#define VDIN1_MATRIX_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_OFFSET2 )
+#define VDIN1_MATRIX_PRE_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PRE_OFFSET0_1 )
+#define VDIN1_MATRIX_PRE_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PRE_OFFSET2 )
+#define VDIN1_LFIFO_CTRL ((VDIN1_OFFSET << 2) + VDIN_LFIFO_CTRL )
+#define VDIN1_COM_GCLK_CTRL ((VDIN1_OFFSET << 2) + VDIN_COM_GCLK_CTRL )
+#define VDIN1_INTF_WIDTHM1 ((VDIN1_OFFSET << 2) + VDIN_INTF_WIDTHM1 )
+#define VDIN1_WR_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_WR_CTRL2 )
+#define VDIN1_WR_CTRL ((VDIN1_OFFSET << 2) + VDIN_WR_CTRL )
+#define VDIN1_WR_H_START_END ((VDIN1_OFFSET << 2) + VDIN_WR_H_START_END )
+#define VDIN1_WR_V_START_END ((VDIN1_OFFSET << 2) + VDIN_WR_V_START_END )
+#define VDIN1_VSC_PHASE_STEP ((VDIN1_OFFSET << 2) + VDIN_VSC_PHASE_STEP )
+#define VDIN1_VSC_INI_CTRL ((VDIN1_OFFSET << 2) + VDIN_VSC_INI_CTRL )
+#define VDIN1_SCIN_HEIGHTM1 ((VDIN1_OFFSET << 2) + VDIN_SCIN_HEIGHTM1 )
+#define VDIN1_DUMMY_DATA ((VDIN1_OFFSET << 2) + VDIN_DUMMY_DATA )
+#define VDIN1_MATRIX_PROBE_COLOR ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PROBE_COLOR )
+#define VDIN1_MATRIX_HL_COLOR ((VDIN1_OFFSET << 2) + VDIN_MATRIX_HL_COLOR )
+#define VDIN1_MATRIX_PROBE_POS ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PROBE_POS )
+#define VDIN1_CHROMA_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_CHROMA_ADDR_PORT )
+#define VDIN1_CHROMA_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_CHROMA_DATA_PORT )
+#define VDIN1_CM_BRI_CON_CTRL ((VDIN1_OFFSET << 2) + VDIN_CM_BRI_CON_CTRL )
+#define VDIN1_GO_LINE_CTRL ((VDIN1_OFFSET << 2) + VDIN_GO_LINE_CTRL )
+#define VDIN1_HIST_CTRL ((VDIN1_OFFSET << 2) + VDIN_HIST_CTRL )
+#define VDIN1_HIST_H_START_END ((VDIN1_OFFSET << 2) + VDIN_HIST_H_START_END )
+#define VDIN1_HIST_V_START_END ((VDIN1_OFFSET << 2) + VDIN_HIST_V_START_END )
+#define VDIN1_HIST_MAX_MIN ((VDIN1_OFFSET << 2) + VDIN_HIST_MAX_MIN )
+#define VDIN1_HIST_SPL_VAL ((VDIN1_OFFSET << 2) + VDIN_HIST_SPL_VAL )
+#define VDIN1_HIST_SPL_PIX_CNT ((VDIN1_OFFSET << 2) + VDIN_HIST_SPL_PIX_CNT )
+#define VDIN1_HIST_CHROMA_SUM ((VDIN1_OFFSET << 2) + VDIN_HIST_CHROMA_SUM )
+#define VDIN1_DNLP_HIST00 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST00 )
+#define VDIN1_DNLP_HIST01 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST01 )
+#define VDIN1_DNLP_HIST02 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST02 )
+#define VDIN1_DNLP_HIST03 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST03 )
+#define VDIN1_DNLP_HIST04 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST04 )
+#define VDIN1_DNLP_HIST05 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST05 )
+#define VDIN1_DNLP_HIST06 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST06 )
+#define VDIN1_DNLP_HIST07 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST07 )
+#define VDIN1_DNLP_HIST08 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST08 )
+#define VDIN1_DNLP_HIST09 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST09 )
+#define VDIN1_DNLP_HIST10 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST10 )
+#define VDIN1_DNLP_HIST11 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST11 )
+#define VDIN1_DNLP_HIST12 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST12 )
+#define VDIN1_DNLP_HIST13 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST13 )
+#define VDIN1_DNLP_HIST14 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST14 )
+#define VDIN1_DNLP_HIST15 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST15 )
+#define VDIN1_DNLP_HIST16 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST16 )
+#define VDIN1_DNLP_HIST17 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST17 )
+#define VDIN1_DNLP_HIST18 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST18 )
+#define VDIN1_DNLP_HIST19 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST19 )
+#define VDIN1_DNLP_HIST20 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST20 )
+#define VDIN1_DNLP_HIST21 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST21 )
+#define VDIN1_DNLP_HIST22 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST22 )
+#define VDIN1_DNLP_HIST23 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST23 )
+#define VDIN1_DNLP_HIST24 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST24 )
+#define VDIN1_DNLP_HIST25 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST25 )
+#define VDIN1_DNLP_HIST26 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST26 )
+#define VDIN1_DNLP_HIST27 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST27 )
+#define VDIN1_DNLP_HIST28 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST28 )
+#define VDIN1_DNLP_HIST29 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST29 )
+#define VDIN1_DNLP_HIST30 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST30 )
+#define VDIN1_DNLP_HIST31 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST31 )
+#define VDIN1_DNLP_HIST32 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST32 )
+#define VDIN1_MEAS_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_MEAS_CTRL0 )
+#define VDIN1_MEAS_VS_COUNT_HI ((VDIN1_OFFSET << 2) + VDIN_MEAS_VS_COUNT_HI )
+#define VDIN1_MEAS_VS_COUNT_LO ((VDIN1_OFFSET << 2) + VDIN_MEAS_VS_COUNT_LO )
+#define VDIN1_MEAS_HS_RANGE ((VDIN1_OFFSET << 2) + VDIN_MEAS_HS_RANGE )
+#define VDIN1_MEAS_HS_COUNT ((VDIN1_OFFSET << 2) + VDIN_MEAS_HS_COUNT )
+#define VDIN1_BLKBAR_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_CTRL1 )
+#define VDIN1_BLKBAR_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_CTRL0 )
+#define VDIN1_BLKBAR_H_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_H_START_END )
+#define VDIN1_BLKBAR_V_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_V_START_END )
+#define VDIN1_BLKBAR_CNT_THRESHOLD ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_CNT_THRESHOLD )
+#define VDIN1_BLKBAR_ROW_TH1_TH2 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_ROW_TH1_TH2 )
+#define VDIN1_BLKBAR_IND_LEFT_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_LEFT_START_END )
+#define VDIN1_BLKBAR_IND_RIGHT_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_RIGHT_START_END )
+#define VDIN1_BLKBAR_IND_LEFT1_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_LEFT1_CNT )
+#define VDIN1_BLKBAR_IND_LEFT2_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_LEFT2_CNT )
+#define VDIN1_BLKBAR_IND_RIGHT1_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_RIGHT1_CNT )
+#define VDIN1_BLKBAR_IND_RIGHT2_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_RIGHT2_CNT )
+#define VDIN1_BLKBAR_STATUS0 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_STATUS0 )
+#define VDIN1_BLKBAR_STATUS1 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_STATUS1 )
+#define VDIN1_WIN_H_START_END ((VDIN1_OFFSET << 2) + VDIN_WIN_H_START_END )
+#define VDIN1_WIN_V_START_END ((VDIN1_OFFSET << 2) + VDIN_WIN_V_START_END )
+#define VDIN1_ASFIFO_CTRL3 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL3 )
+#define VDIN1_LFIFO_URG_CTRL ((VDIN1_OFFSET << 2) + VDIN_LFIFO_URG_CTRL )
+#define VDIN1_COM_GCLK_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_COM_GCLK_CTRL2 )
+#define VDIN1_VSHRK_CTRL ((VDIN1_OFFSET << 2) + VDIN_VSHRK_CTRL )
+#define VDIN1_SYNC_MASK ((VDIN1_OFFSET << 2) + VDIN_SYNC_MASK )
+#define VDIN1_DOLBY_DSC_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL0 )
+#define VDIN1_DOLBY_DSC_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL1 )
+#define VDIN1_DOLBY_DSC_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL2 )
+#define VDIN1_DOLBY_DSC_CTRL3 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL3 )
+#define VDIN1_DOLBY_AXI_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL0 )
+#define VDIN1_DOLBY_AXI_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL1 )
+#define VDIN1_DOLBY_AXI_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL2 )
+#define VDIN1_DOLBY_AXI_CTRL3 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL3 )
+#define VDIN1_DOLBY_DSC_STATUS0 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS0)
+#define VDIN1_DOLBY_DSC_STATUS1 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS1)
+#define VDIN1_DOLBY_DSC_STATUS2 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS2)
+#define VDIN1_DOLBY_DSC_STATUS3 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS3)
+
+#define VDIN1_HDR2_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_CTRL )
+#define VDIN1_HDR2_CLK_GATE ((VDIN1_OFFSET << 2) + VDIN_HDR2_CLK_GATE )
+#define VDIN1_HDR2_MATRIXI_COEF00_01 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF00_01 )
+#define VDIN1_HDR2_MATRIXI_COEF02_10 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF02_10 )
+#define VDIN1_HDR2_MATRIXI_COEF11_12 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF11_12 )
+#define VDIN1_HDR2_MATRIXI_COEF20_21 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF20_21 )
+#define VDIN1_HDR2_MATRIXI_COEF22 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF22 )
+#define VDIN1_HDR2_MATRIXI_COEF30_31 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF30_31 )
+#define VDIN1_HDR2_MATRIXI_COEF32_40 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF32_40 )
+#define VDIN1_HDR2_MATRIXI_COEF41_42 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF41_42 )
+#define VDIN1_HDR2_MATRIXI_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_OFFSET0_1 )
+#define VDIN1_HDR2_MATRIXI_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_OFFSET2 )
+#define VDIN1_HDR2_MATRIXI_PRE_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_PRE_OFFSET0_1 )
+#define VDIN1_HDR2_MATRIXI_PRE_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_PRE_OFFSET2 )
+#define VDIN1_HDR2_MATRIXO_COEF00_01 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF00_01 )
+#define VDIN1_HDR2_MATRIXO_COEF02_10 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF02_10 )
+#define VDIN1_HDR2_MATRIXO_COEF11_12 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF11_12 )
+#define VDIN1_HDR2_MATRIXO_COEF20_21 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF20_21 )
+#define VDIN1_HDR2_MATRIXO_COEF22 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF22 )
+#define VDIN1_HDR2_MATRIXO_COEF30_31 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF30_31 )
+#define VDIN1_HDR2_MATRIXO_COEF32_40 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF32_40 )
+#define VDIN1_HDR2_MATRIXO_COEF41_42 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF41_42 )
+#define VDIN1_HDR2_MATRIXO_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_OFFSET0_1 )
+#define VDIN1_HDR2_MATRIXO_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_OFFSET2 )
+#define VDIN1_HDR2_MATRIXO_PRE_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_PRE_OFFSET0_1 )
+#define VDIN1_HDR2_MATRIXO_PRE_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_PRE_OFFSET2 )
+#define VDIN1_HDR2_MATRIXI_CLIP ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_CLIP )
+#define VDIN1_HDR2_MATRIXO_CLIP ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_CLIP )
+#define VDIN1_HDR2_CGAIN_OFFT ((VDIN1_OFFSET << 2) + VDIN_HDR2_CGAIN_OFFT )
+#define VDIN1_EOTF_LUT_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_EOTF_LUT_ADDR_PORT )
+#define VDIN1_EOTF_LUT_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_EOTF_LUT_DATA_PORT )
+#define VDIN1_OETF_LUT_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_OETF_LUT_ADDR_PORT )
+#define VDIN1_OETF_LUT_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_OETF_LUT_DATA_PORT )
+#define VDIN1_OGAIN_LUT_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_OGAIN_LUT_ADDR_PORT )
+#define VDIN1_OGAIN_LUT_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_OGAIN_LUT_DATA_PORT )
+#define VDIN1_CGAIN_LUT_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_CGAIN_LUT_ADDR_PORT )
+#define VDIN1_CGAIN_LUT_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_CGAIN_LUT_DATA_PORT )
+#define VDIN1_HDR2_CGAIN_COEF0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_CGAIN_COEF0 )
+#define VDIN1_HDR2_CGAIN_COEF1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_CGAIN_COEF1 )
+#define VDIN1_HDR2_ADPS_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_CTRL )
+#define VDIN1_HDR2_ADPS_ALPHA0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_ALPHA0 )
+#define VDIN1_HDR2_ADPS_ALPHA1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_ALPHA1 )
+#define VDIN1_HDR2_ADPS_BETA0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_BETA0 )
+#define VDIN1_HDR2_ADPS_BETA1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_BETA1 )
+#define VDIN1_HDR2_ADPS_BETA2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_BETA2 )
+#define VDIN1_HDR2_ADPS_COEF0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_COEF0 )
+#define VDIN1_HDR2_ADPS_COEF1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_COEF1 )
+#define VDIN1_HDR2_GMUT_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_CTRL )
+#define VDIN1_HDR2_GMUT_COEF0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF0 )
+#define VDIN1_HDR2_GMUT_COEF1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF1 )
+#define VDIN1_HDR2_GMUT_COEF2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF2 )
+#define VDIN1_HDR2_GMUT_COEF3 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF3 )
+#define VDIN1_HDR2_GMUT_COEF4 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF4 )
+#define VDIN1_HDR2_PIPE_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PIPE_CTRL1 )
+#define VDIN1_HDR2_PIPE_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PIPE_CTRL2 )
+#define VDIN1_HDR2_PIPE_CTRL3 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PIPE_CTRL3 )
+#define VDIN1_HDR2_PROC_WIN1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PROC_WIN1 )
+#define VDIN1_HDR2_PROC_WIN2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PROC_WIN2 )
+#define VDIN1_HDR2_MATRIXI_EN_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_EN_CTRL )
+#define VDIN1_HDR2_MATRIXO_EN_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_EN_CTRL )
+#define VDIN1_HDR2_HIST_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_HIST_CTRL )
+#define VDIN1_HDR2_HIST_H_START_END ((VDIN1_OFFSET << 2) + VDIN_HDR2_HIST_H_START_END )
+#define VDIN1_HDR2_HIST_V_START_END ((VDIN1_OFFSET << 2) + VDIN_HDR2_HIST_V_START_END )
+#define VDIN1_HDR2_HIST_RD ((VDIN1_OFFSET << 2) + VDIN_HDR2_HIST_RD )
+
+
+
+#define VDIN1_CRC_CTRL ((VDIN1_OFFSET << 2) + VDIN_CRC_CTRL)
+#define VDIN1_RO_CRC ((VDIN1_OFFSET << 2) + VDIN_RO_CRC )
+#define VDIN1_LINE_INT ((VDIN1_OFFSET << 2) + VDIN_LINE_INT)
+#define VDIN1_WR_URGENT_CTRL ((VDIN1_OFFSET << 2) + VDIN_WR_URGENT_CTRL)
+#define VDIN1_RO_WRMIF_STATUS ((VDIN1_OFFSET << 2) + VDIN_RO_WRMIF_STATUS)
+
+#define VDIN1_DSC_CTRL ((VDIN1_OFFSET << 2) + VDIN_DSC_CTRL )
+#define VDIN1_CFMT_CTRL ((VDIN1_OFFSET << 2) + VDIN_CFMT_CTRL )
+#define VDIN1_CFMT_W ((VDIN1_OFFSET << 2) + VDIN_CFMT_W )
+#define VDIN1_SCB_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_SCB_CTRL0 )
+#define VDIN1_SCB_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_SCB_CTRL1 )
+#define VDIN1_DSC_HSIZE ((VDIN1_OFFSET << 2) + VDIN_DSC_HSIZE )
+#define VDIN1_DSC_DETUNNEL_SEL ((VDIN1_OFFSET << 2) + VDIN_DSC_DETUNNEL_SEL)
+#define VDIN1_DSC_TUNNEL_SEL ((VDIN1_OFFSET << 2) + VDIN_DSC_TUNNEL_SEL)
+#define VDIN1_DITH_CTRL ((VDIN1_OFFSET << 2) + VDIN_DITH_CTRL )
+#define VDIN1_DITH_LUT_1 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_1 )
+#define VDIN1_DITH_LUT_2 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_2 )
+#define VDIN1_DITH_LUT_3 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_3 )
+#define VDIN1_DITH_LUT_4 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_4 )
+#define VDIN1_DITH_LUT_5 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_5 )
+#define VDIN1_DITH_LUT_6 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_6 )
+#define VDIN1_DITH_LUT_7 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_7 )
+#define VDIN1_DITH_LUT_8 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_8 )
+#define VDIN1_DITH_LUT_9 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_9 )
+#define VDIN1_DITH_LUT_10 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_10 )
+#define VDIN1_DITH_LUT_11 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_11 )
+#define VDIN1_DITH_LUT_12 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_12 )
+
+#define VDIN1_HSK_CTRL ((VDIN1_OFFSET << 2) + VDIN_HSK_CTRL )
+#define VDIN1_HSK_COEF_0 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_0 )
+#define VDIN1_HSK_COEF_1 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_1 )
+#define VDIN1_HSK_COEF_2 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_2 )
+#define VDIN1_HSK_COEF_3 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_3 )
+#define VDIN1_HSK_COEF_4 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_4 )
+#define VDIN1_HSK_COEF_5 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_5 )
+#define VDIN1_HSK_COEF_6 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_6 )
+#define VDIN1_HSK_COEF_7 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_7 )
+#define VDIN1_HSK_COEF_8 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_8 )
+#define VDIN1_HSK_COEF_9 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_9 )
+#define VDIN1_HSK_COEF_A ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_A )
+#define VDIN1_HSK_COEF_B ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_B )
+#define VDIN1_HSK_COEF_C ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_C )
+#define VDIN1_HSK_COEF_D ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_D )
+#define VDIN1_HSK_COEF_E ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_E )
+#define VDIN1_HSK_COEF_F ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_F )
+
+#define VDIN1_HDR2_SIZE ((VDIN1_OFFSET << 2) + VDIN_HDR2_SIZE )
+#define VDIN1_VSHRK_SIZE_M1 ((VDIN1_OFFSET << 2) + VDIN_VSHRK_SIZE_M1)
+
+
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_vdin1_regs.h
+//
+//
+// Reading file: lcd_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: LCD_VCBUS_BASE = 0x14
+// -----------------------------------------------
+//========================================================================
+//LCD DRV 12'h480~12'h4ef
+//=======================================================================
+#define L_GAMMA_CNTL_PORT ((0x1400 << 2) + 0xff000000)
+#define L_GAMMA_DATA_PORT ((0x1401 << 2) + 0xff000000)
+#define L_GAMMA_ADDR_PORT ((0x1402 << 2) + 0xff000000)
+#define L_GAMMA_VCOM_HSWITCH_ADDR ((0x1403 << 2) + 0xff000000)
+#define L_RGB_BASE_ADDR ((0x1405 << 2) + 0xff000000)
+#define L_RGB_COEFF_ADDR ((0x1406 << 2) + 0xff000000)
+#define L_POL_CNTL_ADDR ((0x1407 << 2) + 0xff000000)
+#define L_DITH_CNTL_ADDR ((0x1408 << 2) + 0xff000000)
+#define L_GAMMA_PROBE_CTRL ((0x1409 << 2) + 0xff000000)
+//read only
+#define L_GAMMA_PROBE_COLOR_L ((0x140a << 2) + 0xff000000)
+#define L_GAMMA_PROBE_COLOR_H ((0x140b << 2) + 0xff000000)
+#define L_GAMMA_PROBE_HL_COLOR ((0x140c << 2) + 0xff000000)
+#define L_GAMMA_PROBE_POS_X ((0x140d << 2) + 0xff000000)
+#define L_GAMMA_PROBE_POS_Y ((0x140e << 2) + 0xff000000)
+#define L_STH1_HS_ADDR ((0x1410 << 2) + 0xff000000)
+#define L_STH1_HE_ADDR ((0x1411 << 2) + 0xff000000)
+#define L_STH1_VS_ADDR ((0x1412 << 2) + 0xff000000)
+#define L_STH1_VE_ADDR ((0x1413 << 2) + 0xff000000)
+#define L_STH2_HS_ADDR ((0x1414 << 2) + 0xff000000)
+#define L_STH2_HE_ADDR ((0x1415 << 2) + 0xff000000)
+#define L_STH2_VS_ADDR ((0x1416 << 2) + 0xff000000)
+#define L_STH2_VE_ADDR ((0x1417 << 2) + 0xff000000)
+#define L_OEH_HS_ADDR ((0x1418 << 2) + 0xff000000)
+#define L_OEH_HE_ADDR ((0x1419 << 2) + 0xff000000)
+#define L_OEH_VS_ADDR ((0x141a << 2) + 0xff000000)
+#define L_OEH_VE_ADDR ((0x141b << 2) + 0xff000000)
+#define L_VCOM_HSWITCH_ADDR ((0x141c << 2) + 0xff000000)
+#define L_VCOM_VS_ADDR ((0x141d << 2) + 0xff000000)
+#define L_VCOM_VE_ADDR ((0x141e << 2) + 0xff000000)
+#define L_CPV1_HS_ADDR ((0x141f << 2) + 0xff000000)
+#define L_CPV1_HE_ADDR ((0x1420 << 2) + 0xff000000)
+#define L_CPV1_VS_ADDR ((0x1421 << 2) + 0xff000000)
+#define L_CPV1_VE_ADDR ((0x1422 << 2) + 0xff000000)
+#define L_CPV2_HS_ADDR ((0x1423 << 2) + 0xff000000)
+#define L_CPV2_HE_ADDR ((0x1424 << 2) + 0xff000000)
+#define L_CPV2_VS_ADDR ((0x1425 << 2) + 0xff000000)
+#define L_CPV2_VE_ADDR ((0x1426 << 2) + 0xff000000)
+#define L_STV1_HS_ADDR ((0x1427 << 2) + 0xff000000)
+#define L_STV1_HE_ADDR ((0x1428 << 2) + 0xff000000)
+#define L_STV1_VS_ADDR ((0x1429 << 2) + 0xff000000)
+#define L_STV1_VE_ADDR ((0x142a << 2) + 0xff000000)
+#define L_STV2_HS_ADDR ((0x142b << 2) + 0xff000000)
+#define L_STV2_HE_ADDR ((0x142c << 2) + 0xff000000)
+#define L_STV2_VS_ADDR ((0x142d << 2) + 0xff000000)
+#define L_STV2_VE_ADDR ((0x142e << 2) + 0xff000000)
+#define L_OEV1_HS_ADDR ((0x142f << 2) + 0xff000000)
+#define L_OEV1_HE_ADDR ((0x1430 << 2) + 0xff000000)
+#define L_OEV1_VS_ADDR ((0x1431 << 2) + 0xff000000)
+#define L_OEV1_VE_ADDR ((0x1432 << 2) + 0xff000000)
+#define L_OEV2_HS_ADDR ((0x1433 << 2) + 0xff000000)
+#define L_OEV2_HE_ADDR ((0x1434 << 2) + 0xff000000)
+#define L_OEV2_VS_ADDR ((0x1435 << 2) + 0xff000000)
+#define L_OEV2_VE_ADDR ((0x1436 << 2) + 0xff000000)
+#define L_OEV3_HS_ADDR ((0x1437 << 2) + 0xff000000)
+#define L_OEV3_HE_ADDR ((0x1438 << 2) + 0xff000000)
+#define L_OEV3_VS_ADDR ((0x1439 << 2) + 0xff000000)
+#define L_OEV3_VE_ADDR ((0x143a << 2) + 0xff000000)
+#define L_LCD_PWR_ADDR ((0x143b << 2) + 0xff000000)
+#define L_LCD_PWM0_LO_ADDR ((0x143c << 2) + 0xff000000)
+#define L_LCD_PWM0_HI_ADDR ((0x143d << 2) + 0xff000000)
+#define L_LCD_PWM1_LO_ADDR ((0x143e << 2) + 0xff000000)
+#define L_LCD_PWM1_HI_ADDR ((0x143f << 2) + 0xff000000)
+#define L_INV_CNT_ADDR ((0x1440 << 2) + 0xff000000)
+#define L_TCON_MISC_SEL_ADDR ((0x1441 << 2) + 0xff000000)
+#define L_DUAL_PORT_CNTL_ADDR ((0x1442 << 2) + 0xff000000)
+#define MLVDS_CLK_CTL1_HI ((0x1443 << 2) + 0xff000000)
+#define MLVDS_CLK_CTL1_LO ((0x1444 << 2) + 0xff000000)
+// [31:30] enable mlvds clocks
+// [24] mlvds_clk_half_delay 24 // Bit 0
+// [23:0] mlvds_clk_pattern 0 // Bit 23:0
+#define L_TCON_DOUBLE_CTL ((0x1449 << 2) + 0xff000000)
+#define L_TCON_PATTERN_HI ((0x144a << 2) + 0xff000000)
+#define L_TCON_PATTERN_LO ((0x144b << 2) + 0xff000000)
+#define LDIM_BL_ADDR_PORT ((0x144e << 2) + 0xff000000)
+#define LDIM_BL_DATA_PORT ((0x144f << 2) + 0xff000000)
+#define L_DE_HS_ADDR ((0x1451 << 2) + 0xff000000)
+#define L_DE_HE_ADDR ((0x1452 << 2) + 0xff000000)
+#define L_DE_VS_ADDR ((0x1453 << 2) + 0xff000000)
+#define L_DE_VE_ADDR ((0x1454 << 2) + 0xff000000)
+#define L_HSYNC_HS_ADDR ((0x1455 << 2) + 0xff000000)
+#define L_HSYNC_HE_ADDR ((0x1456 << 2) + 0xff000000)
+#define L_HSYNC_VS_ADDR ((0x1457 << 2) + 0xff000000)
+#define L_HSYNC_VE_ADDR ((0x1458 << 2) + 0xff000000)
+#define L_VSYNC_HS_ADDR ((0x1459 << 2) + 0xff000000)
+#define L_VSYNC_HE_ADDR ((0x145a << 2) + 0xff000000)
+#define L_VSYNC_VS_ADDR ((0x145b << 2) + 0xff000000)
+#define L_VSYNC_VE_ADDR ((0x145c << 2) + 0xff000000)
+// bit 8 -- vfifo_mcu_enable
+// bit 7 -- halt_vs_de
+// bit 6 -- R8G8B8_format
+// bit 5 -- R6G6B6_format (round to 6 bits)
+// bit 4 -- R5G6B5_format
+// bit 3 -- dac_dith_sel
+// bit 2 -- lcd_mcu_enable_de -- ReadOnly
+// bit 1 -- lcd_mcu_enable_vsync -- ReadOnly
+// bit 0 -- lcd_mcu_enable
+#define L_LCD_MCU_CTL ((0x145d << 2) + 0xff000000)
+//**************************************************************************
+//* Dual port mLVDS registers
+//**************************************************************************
+// bit 3 - enable_u_dual_mlvds_dp_clk
+// bit 2 - enable_u_map_mlvds_r_clk
+// bit 1 - enable_u_map_mlvds_l_clk
+// bit 0 - dual_mlvds_en
+//`define DUAL_MLVDS_CTL 8'h60
+// bit[12:0] - dual_mlvds_line_start
+//`define DUAL_MLVDS_LINE_START 8'h61
+// bit[12:0] - dual_mlvds_line_end
+//`define DUAL_MLVDS_LINE_END 8'h62
+// bit[12:0] - dual_mlvds_w_pixel_start_l
+//`define DUAL_MLVDS_PIXEL_W_START_L 8'h63
+// bit[12:0] - dual_mlvds_w_pixel_end_l
+//`define DUAL_MLVDS_PIXEL_W_END_L 8'h64
+// bit[12:0] - dual_mlvds_w_pixel_start_r
+//`define DUAL_MLVDS_PIXEL_W_START_R 8'h65
+// bit[12:0] - dual_mlvds_w_pixel_end_r
+//`define DUAL_MLVDS_PIXEL_W_END_R 8'h66
+// bit[12:0] - dual_mlvds_r_pixel_start_l
+//`define DUAL_MLVDS_PIXEL_R_START_L 8'h67
+// bit[12:0] - dual_mlvds_r_pixel_cnt_l
+//`define DUAL_MLVDS_PIXEL_R_CNT_L 8'h68
+// bit[12:0] - dual_mlvds_r_pixel_start_r
+//`define DUAL_MLVDS_PIXEL_R_START_R 8'h69
+// bit[12:0] - dual_mlvds_r_pixel_cnt_r
+//`define DUAL_MLVDS_PIXEL_R_CNT_R 8'h6a
+// bit[15] - v_inversion_en
+// bit[12:0] - v_inversion_pixel
+//`define V_INVERSION_PIXEL 8'h70
+// bit[15] - v_inversion_sync_en
+// bit[12:0] - v_inversion_line
+//`define V_INVERSION_LINE 8'h71
+// bit[15:12] - v_loop_r
+// bit[11:10] - v_pattern_1_r
+// bit[9:8] - v_pattern_0_r
+// bit[7:4] - v_loop_l
+// bit[3:2] - v_pattern_1_l
+// bit[1:0] - v_pattern_0_l
+//`define V_INVERSION_CONTROL 8'h72
+//`define MLVDS2_CONTROL 8'h74
+ #define mLVDS2_RESERVED 15 // 15
+ #define mLVDS2_double_pattern 14 // 14
+ #define mLVDS2_ins_reset 8 // 13:8 // each channel has one bit
+ #define mLVDS2_dual_gate 7
+ #define mLVDS2_bit_num 6 // 0-6Bits, 1-8Bits
+ #define mLVDS2_pair_num 5 // 0-3Pairs, 1-6Pairs
+ #define mLVDS2_msb_first 4
+ #define mLVDS2_PORT_SWAP 3
+ #define mLVDS2_MLSB_SWAP 2
+ #define mLVDS2_PN_SWAP 1
+ #define mLVDS2_en 0
+//`define MLVDS2_CONFIG_HI 8'h75
+//`define MLVDS2_CONFIG_LO 8'h76
+ #define mLVDS2_reset_offset 29 // Bit 31:29
+ #define mLVDS2_reset_length 23 // Bit 28:23
+ #define mLVDS2_config_reserved 20 // Bit 22:20
+ #define mLVDS2_reset_start_bit12 19 // Bit 19
+ #define mLVDS2_data_write_toggle 18
+ #define mLVDS2_data_write_ini 17
+ #define mLVDS2_data_latch_1_toggle 16
+ #define mLVDS2_data_latch_1_ini 15
+ #define mLVDS2_data_latch_0_toggle 14
+ #define mLVDS2_data_latch_0_ini 13
+ #define mLVDS2_reset_1_select 12 // 0 - same as reset_0, 1 - 1 clock delay of reset_0
+ #define mLVDS2_reset_start 0 // Bit 11:0
+//`define MLVDS2_DUAL_GATE_WR_START 8'h77
+// `define mlvds2_dual_gate_wr_start 0 // Bit 12:0
+//`define MLVDS2_DUAL_GATE_WR_END 8'h78
+// `define mlvds2_dual_gate_wr_end 0 // Bit 12:0
+//
+//`define MLVDS2_DUAL_GATE_RD_START 8'h79
+// `define mlvds2_dual_gate_rd_start 0 // Bit 12:0
+//`define MLVDS2_DUAL_GATE_RD_END 8'h7a
+// `define mlvds2_dual_gate_rd_end 0 // Bit 12:0
+//`define MLVDS2_SECOND_RESET_CTL 8'h7b
+// `define mLVDS2_2nd_reset_start 0 // Bit 12:0
+//
+//`define MLVDS2_DUAL_GATE_CTL_HI 8'h7c
+//`define MLVDS2_DUAL_GATE_CTL_LO 8'h7d
+// `define mlvds2_tcon_field_en 24 // Bit 7:0
+// `define mlvds2_dual_gate_reserved 21 // Bit 2:0
+// `define mlvds2_scan_mode_start_line_bit12 20 // Bit 0
+// `define mlvds2_scan_mode_odd 16 // Bit 3:0
+// `define mlvds2_scan_mode_even 12 // Bit 3:0
+// `define mlvds2_scan_mode_start_line 0 // Bit 11:0
+//
+//`define MLVDS2_RESET_CONFIG_HI 8'h7e
+//`define MLVDS2_RESET_CONFIG_LO 8'h7f
+// `define mLVDS2_reset_range_enable 31 // Bit 0
+// `define mLVDS2_reset_range_inv 30 // Bit 0
+// `define mLVDS2_reset_config_res1 29 // Bit 0
+// `define mLVDS2_reset_range_line_0 16 // Bit 11:0
+// `define mLVDS2_reset_config_res3 13 // Bit 2:0
+// `define mLVDS2_reset_range_line_1 0 // Bit 11:0
+//
+//**************************************************************************
+//* Vbyone registers (Note: no MinLVDS in G9tv, share the register)
+//**************************************************************************
+#define VBO_CTRL_L ((0x1460 << 2) + 0xff000000)
+#define VBO_CTRL_H ((0x1461 << 2) + 0xff000000)
+#define VBO_SOFT_RST ((0x1462 << 2) + 0xff000000)
+#define VBO_LANES ((0x1463 << 2) + 0xff000000)
+#define VBO_VIN_CTRL ((0x1464 << 2) + 0xff000000)
+#define VBO_ACT_VSIZE ((0x1465 << 2) + 0xff000000)
+#define VBO_REGION_00 ((0x1466 << 2) + 0xff000000)
+#define VBO_REGION_01 ((0x1467 << 2) + 0xff000000)
+#define VBO_REGION_02 ((0x1468 << 2) + 0xff000000)
+#define VBO_REGION_03 ((0x1469 << 2) + 0xff000000)
+#define VBO_VBK_CTRL_0 ((0x146a << 2) + 0xff000000)
+#define VBO_VBK_CTRL_1 ((0x146b << 2) + 0xff000000)
+#define VBO_HBK_CTRL ((0x146c << 2) + 0xff000000)
+#define VBO_PXL_CTRL ((0x146d << 2) + 0xff000000)
+#define VBO_LANE_SKEW_L ((0x146e << 2) + 0xff000000)
+#define VBO_LANE_SKEW_H ((0x146f << 2) + 0xff000000)
+#define VBO_GCLK_LANE_L ((0x1470 << 2) + 0xff000000)
+#define VBO_GCLK_LANE_H ((0x1471 << 2) + 0xff000000)
+#define VBO_GCLK_MAIN ((0x1472 << 2) + 0xff000000)
+#define VBO_STATUS_L ((0x1473 << 2) + 0xff000000)
+#define VBO_STATUS_H ((0x1474 << 2) + 0xff000000)
+#define VBO_LANE_OUTPUT ((0x1475 << 2) + 0xff000000)
+#define LCD_PORT_SWAP ((0x1476 << 2) + 0xff000000)
+#define VBO_TMCHK_THRD_L ((0x1478 << 2) + 0xff000000)
+#define VBO_TMCHK_THRD_H ((0x1479 << 2) + 0xff000000)
+#define VBO_FSM_HOLDER_L ((0x147a << 2) + 0xff000000)
+#define VBO_FSM_HOLDER_H ((0x147b << 2) + 0xff000000)
+#define VBO_INTR_STATE_CTRL ((0x147c << 2) + 0xff000000)
+#define VBO_INTR_UNMASK ((0x147d << 2) + 0xff000000)
+#define VBO_TMCHK_HSYNC_STATE_L ((0x147e << 2) + 0xff000000)
+#define VBO_TMCHK_HSYNC_STATE_H ((0x147f << 2) + 0xff000000)
+#define VBO_TMCHK_VSYNC_STATE_L ((0x14f4 << 2) + 0xff000000)
+#define VBO_TMCHK_VSYNC_STATE_H ((0x14f5 << 2) + 0xff000000)
+#define VBO_TMCHK_VDE_STATE_L ((0x14f6 << 2) + 0xff000000)
+#define VBO_TMCHK_VDE_STATE_H ((0x14f7 << 2) + 0xff000000)
+#define VBO_INTR_STATE ((0x14f8 << 2) + 0xff000000)
+#define VBO_INFILTER_CTRL ((0x14f9 << 2) + 0xff000000)
+#define VBO_INSGN_CTRL ((0x14fa << 2) + 0xff000000)
+#define VBO_INFILTER_CTRL_H ((0x1477 << 2) + 0xff000000)
+//**************************************************************************
+//* NOTE:: When Programming the Gamma, please turn off the IRQ service *
+//**************************************************************************
+#define GAMMA_CNTL_PORT ((0x1480 << 2) + 0xff000000)
+ #define GAMMA_VCOM_POL 7 //RW
+ #define GAMMA_RVS_OUT 6 //RW
+ #define ADR_RDY 5 //Read Only
+ #define WR_RDY 4 //Read Only
+ #define RD_RDY 3 //Read Only
+ #define GAMMA_TR 2 //RW
+ #define GAMMA_SET 1 //RW
+ #define GAMMA_EN 0 //RW
+#define GAMMA_DATA_PORT ((0x1481 << 2) + 0xff000000)
+#define GAMMA_ADDR_PORT ((0x1482 << 2) + 0xff000000)
+ #define H_RD 12
+ #define H_AUTO_INC 11
+ #define H_SEL_R 10
+ #define H_SEL_G 9
+ #define H_SEL_B 8
+ #define HADR_MSB 7 //7:0
+ #define HADR 0 //7:0
+#define GAMMA_VCOM_HSWITCH_ADDR ((0x1483 << 2) + 0xff000000)
+#define RGB_BASE_ADDR ((0x1485 << 2) + 0xff000000)
+#define RGB_COEFF_ADDR ((0x1486 << 2) + 0xff000000)
+#define POL_CNTL_ADDR ((0x1487 << 2) + 0xff000000)
+ #define DCLK_SEL 14 //FOR DCLK OUTPUT
+ #define TCON_VSYNC_SEL_DVI 11 //FOR RGB format DVI output
+ #define TCON_HSYNC_SEL_DVI 10 //FOR RGB format DVI output
+ #define TCON_DE_SEL_DVI 9 //FOR RGB format DVI output
+ #define CPH3_POL 8
+ #define CPH2_POL 7
+ #define CPH1_POL 6
+ #define TCON_DE_SEL 5
+ #define TCON_VS_SEL 4
+ #define TCON_HS_SEL 3
+ #define DE_POL 2
+ #define VS_POL 1
+ #define HS_POL 0
+#define DITH_CNTL_ADDR ((0x1488 << 2) + 0xff000000)
+ #define DITH10_EN 10
+ #define DITH8_EN 9
+ #define DITH_MD 8
+ #define DITH10_CNTL_MSB 7 //7:4
+ #define DITH10_CNTL 4 //7:4
+ #define DITH8_CNTL_MSB 3 //3:0
+ #define DITH8_CNTL 0 //3:0
+//Bit 1 highlight_en
+//Bit 0 probe_en
+#define GAMMA_PROBE_CTRL ((0x1489 << 2) + 0xff000000)
+//read only
+//Bit [15:0] probe_color[15:0]
+#define GAMMA_PROBE_COLOR_L ((0x148a << 2) + 0xff000000)
+//Read only
+//Bit 15: if true valid probed color
+//Bit [13:0] probe_color[29:16]
+#define GAMMA_PROBE_COLOR_H ((0x148b << 2) + 0xff000000)
+//bit 15:0, 5:6:5 color
+#define GAMMA_PROBE_HL_COLOR ((0x148c << 2) + 0xff000000)
+//12:0 pos_x
+#define GAMMA_PROBE_POS_X ((0x148d << 2) + 0xff000000)
+//12:0 pos_y
+#define GAMMA_PROBE_POS_Y ((0x148e << 2) + 0xff000000)
+#define STH1_HS_ADDR ((0x1490 << 2) + 0xff000000)
+#define STH1_HE_ADDR ((0x1491 << 2) + 0xff000000)
+#define STH1_VS_ADDR ((0x1492 << 2) + 0xff000000)
+#define STH1_VE_ADDR ((0x1493 << 2) + 0xff000000)
+#define STH2_HS_ADDR ((0x1494 << 2) + 0xff000000)
+#define STH2_HE_ADDR ((0x1495 << 2) + 0xff000000)
+#define STH2_VS_ADDR ((0x1496 << 2) + 0xff000000)
+#define STH2_VE_ADDR ((0x1497 << 2) + 0xff000000)
+#define OEH_HS_ADDR ((0x1498 << 2) + 0xff000000)
+#define OEH_HE_ADDR ((0x1499 << 2) + 0xff000000)
+#define OEH_VS_ADDR ((0x149a << 2) + 0xff000000)
+#define OEH_VE_ADDR ((0x149b << 2) + 0xff000000)
+#define VCOM_HSWITCH_ADDR ((0x149c << 2) + 0xff000000)
+#define VCOM_VS_ADDR ((0x149d << 2) + 0xff000000)
+#define VCOM_VE_ADDR ((0x149e << 2) + 0xff000000)
+#define CPV1_HS_ADDR ((0x149f << 2) + 0xff000000)
+#define CPV1_HE_ADDR ((0x14a0 << 2) + 0xff000000)
+#define CPV1_VS_ADDR ((0x14a1 << 2) + 0xff000000)
+#define CPV1_VE_ADDR ((0x14a2 << 2) + 0xff000000)
+#define CPV2_HS_ADDR ((0x14a3 << 2) + 0xff000000)
+#define CPV2_HE_ADDR ((0x14a4 << 2) + 0xff000000)
+#define CPV2_VS_ADDR ((0x14a5 << 2) + 0xff000000)
+#define CPV2_VE_ADDR ((0x14a6 << 2) + 0xff000000)
+#define STV1_HS_ADDR ((0x14a7 << 2) + 0xff000000)
+#define STV1_HE_ADDR ((0x14a8 << 2) + 0xff000000)
+#define STV1_VS_ADDR ((0x14a9 << 2) + 0xff000000)
+#define STV1_VE_ADDR ((0x14aa << 2) + 0xff000000)
+#define STV2_HS_ADDR ((0x14ab << 2) + 0xff000000)
+#define STV2_HE_ADDR ((0x14ac << 2) + 0xff000000)
+#define STV2_VS_ADDR ((0x14ad << 2) + 0xff000000)
+#define STV2_VE_ADDR ((0x14ae << 2) + 0xff000000)
+#define OEV1_HS_ADDR ((0x14af << 2) + 0xff000000)
+#define OEV1_HE_ADDR ((0x14b0 << 2) + 0xff000000)
+#define OEV1_VS_ADDR ((0x14b1 << 2) + 0xff000000)
+#define OEV1_VE_ADDR ((0x14b2 << 2) + 0xff000000)
+#define OEV2_HS_ADDR ((0x14b3 << 2) + 0xff000000)
+#define OEV2_HE_ADDR ((0x14b4 << 2) + 0xff000000)
+#define OEV2_VS_ADDR ((0x14b5 << 2) + 0xff000000)
+#define OEV2_VE_ADDR ((0x14b6 << 2) + 0xff000000)
+#define OEV3_HS_ADDR ((0x14b7 << 2) + 0xff000000)
+#define OEV3_HE_ADDR ((0x14b8 << 2) + 0xff000000)
+#define OEV3_VS_ADDR ((0x14b9 << 2) + 0xff000000)
+#define OEV3_VE_ADDR ((0x14ba << 2) + 0xff000000)
+#define LCD_PWR_ADDR ((0x14bb << 2) + 0xff000000)
+ #define LCD_VDD 5
+ #define LCD_VBL 4
+ #define LCD_GPI_MSB 3
+ #define LCD_GPIO 0
+#define LCD_PWM0_LO_ADDR ((0x14bc << 2) + 0xff000000)
+#define LCD_PWM0_HI_ADDR ((0x14bd << 2) + 0xff000000)
+#define LCD_PWM1_LO_ADDR ((0x14be << 2) + 0xff000000)
+#define LCD_PWM1_HI_ADDR ((0x14bf << 2) + 0xff000000)
+#define INV_CNT_ADDR ((0x14c0 << 2) + 0xff000000)
+ #define INV_EN 4
+ #define INV_CNT_MSB 3
+ #define INV_CNT 0
+#define TCON_MISC_SEL_ADDR ((0x14c1 << 2) + 0xff000000)
+ #define STH2_SEL 12
+ #define STH1_SEL 11
+ #define OEH_SEL 10
+ #define VCOM_SEL 9
+ #define DB_LINE_SW 8
+ #define CPV2_SEL 7
+ #define CPV1_SEL 6
+ #define STV2_SEL 5
+ #define STV1_SEL 4
+ #define OEV_UNITE 3
+ #define OEV3_SEL 2
+ #define OEV2_SEL 1
+ #define OEV1_SEL 0
+#define DUAL_PORT_CNTL_ADDR ((0x14c2 << 2) + 0xff000000)
+ #define OUTPUT_YUV 15
+ #define DUAL_IDF 12 // 14:12
+ #define DUAL_ISF 9 // 11:9
+ #define LCD_ANALOG_SEL_CPH3 8
+ #define LCD_ANALOG_3PHI_CLK_SEL 7
+ #define LCD_LVDS_SEL54 6
+ #define LCD_LVDS_SEL27 5
+ #define LCD_TTL_SEL 4
+ #define DUAL_LVDC_EN 3
+ #define PORT_SWP 2
+ #define RGB_SWP 1
+ #define BIT_SWP 0
+#define MLVDS_CONTROL ((0x14c3 << 2) + 0xff000000)
+ #define mLVDS_RESERVED 15 // 15
+ #define mLVDS_double_pattern 14 // 14
+ #define mLVDS_ins_reset 8 // 13:8 // each channel has one bit
+ #define mLVDS_dual_gate 7
+ #define mLVDS_bit_num 6 // 0-6Bits, 1-8Bits
+ #define mLVDS_pair_num 5 // 0-3Pairs, 1-6Pairs
+ #define mLVDS_msb_first 4
+ #define mLVDS_PORT_SWAP 3
+ #define mLVDS_MLSB_SWAP 2
+ #define mLVDS_PN_SWAP 1
+ #define mLVDS_en 0
+#define MLVDS_RESET_PATTERN_HI ((0x14c4 << 2) + 0xff000000)
+#define MLVDS_RESET_PATTERN_LO ((0x14c5 << 2) + 0xff000000)
+ #define mLVDS_reset_pattern 0 // Bit 47:16
+#define MLVDS_RESET_PATTERN_EXT ((0x14c6 << 2) + 0xff000000)
+ #define mLVDS_reset_pattern_ext 0 // Bit 15:0
+#define MLVDS_CONFIG_HI ((0x14c7 << 2) + 0xff000000)
+#define MLVDS_CONFIG_LO ((0x14c8 << 2) + 0xff000000)
+ #define mLVDS_reset_offset 29 // Bit 31:29
+ #define mLVDS_reset_length 23 // Bit 28:23
+ #define mLVDS_config_reserved 20 // Bit 22:20
+ #define mLVDS_reset_start_bit12 19 // Bit 19
+ #define mLVDS_data_write_toggle 18
+ #define mLVDS_data_write_ini 17
+ #define mLVDS_data_latch_1_toggle 16
+ #define mLVDS_data_latch_1_ini 15
+ #define mLVDS_data_latch_0_toggle 14
+ #define mLVDS_data_latch_0_ini 13
+ #define mLVDS_reset_1_select 12 // 0 - same as reset_0, 1 - 1 clock delay of reset_0
+ #define mLVDS_reset_start 0 // Bit 11:0
+#define TCON_DOUBLE_CTL ((0x14c9 << 2) + 0xff000000)
+ #define tcon_double_ini 8 // Bit 7:0
+ #define tcon_double_inv 0 // Bit 7:0
+#define TCON_PATTERN_HI ((0x14ca << 2) + 0xff000000)
+#define TCON_PATTERN_LO ((0x14cb << 2) + 0xff000000)
+ #define tcon_pattern_loop_data 16 // Bit 15:0
+ #define tcon_pattern_loop_start 12 // Bit 3:0
+ #define tcon_pattern_loop_end 8 // Bit 3:0
+ #define tcon_pattern_enable 0 // Bit 7:0
+#define TCON_CONTROL_HI ((0x14cc << 2) + 0xff000000)
+#define TCON_CONTROL_LO ((0x14cd << 2) + 0xff000000)
+ #define tcon_pclk_enable 26 // Bit 5:0 (enable pclk on TCON channel 7 to 2)
+ #define tcon_pclk_div 24 // Bit 1:0 (control phy clok divide 2,4,6,8)
+ #define tcon_delay 0 // Bit 23:0 (3 bit for each channel)
+#define LVDS_BLANK_DATA_HI ((0x14ce << 2) + 0xff000000)
+#define LVDS_BLANK_DATA_LO ((0x14cf << 2) + 0xff000000)
+ #define LVDS_blank_data_reserved 30 // 31:30
+ #define LVDS_blank_data_r 20 // 29:20
+ #define LVDS_blank_data_g 10 // 19:10
+ #define LVDS_blank_data_b 0 // 9:0
+#define LVDS_PACK_CNTL_ADDR ((0x14d0 << 2) + 0xff000000)
+ #define LVDS_USE_TCON 7
+ #define LVDS_DUAL 6
+ #define PN_SWP 5
+ #define LSB_FIRST 4
+ #define LVDS_RESV 3
+ #define ODD_EVEN_SWP 2
+ #define LVDS_REPACK 0
+// New from M3 :
+// Bit 15:12 -- Enable OFFSET Double Generate(TOCN7-TCON4)
+// Bit 11:0 -- de_hs(old tcon) second offset_hs (new tcon)
+#define DE_HS_ADDR ((0x14d1 << 2) + 0xff000000)
+// New from M3 :
+// Bit 15:12 -- Enable OFFSET Double Generate(TOCN3-TCON0)
+#define DE_HE_ADDR ((0x14d2 << 2) + 0xff000000)
+#define DE_VS_ADDR ((0x14d3 << 2) + 0xff000000)
+#define DE_VE_ADDR ((0x14d4 << 2) + 0xff000000)
+#define HSYNC_HS_ADDR ((0x14d5 << 2) + 0xff000000)
+#define HSYNC_HE_ADDR ((0x14d6 << 2) + 0xff000000)
+#define HSYNC_VS_ADDR ((0x14d7 << 2) + 0xff000000)
+#define HSYNC_VE_ADDR ((0x14d8 << 2) + 0xff000000)
+#define VSYNC_HS_ADDR ((0x14d9 << 2) + 0xff000000)
+#define VSYNC_HE_ADDR ((0x14da << 2) + 0xff000000)
+#define VSYNC_VS_ADDR ((0x14db << 2) + 0xff000000)
+#define VSYNC_VE_ADDR ((0x14dc << 2) + 0xff000000)
+// bit 8 -- vfifo_mcu_enable
+// bit 7 -- halt_vs_de
+// bit 6 -- R8G8B8_format
+// bit 5 -- R6G6B6_format (round to 6 bits)
+// bit 4 -- R5G6B5_format
+// bit 3 -- dac_dith_sel
+// bit 2 -- lcd_mcu_enable_de -- ReadOnly
+// bit 1 -- lcd_mcu_enable_vsync -- ReadOnly
+// bit 0 -- lcd_mcu_enable
+#define LCD_MCU_CTL ((0x14dd << 2) + 0xff000000)
+// ReadOnly
+// R5G6B5 when R5G6B5_format
+// G8R8 when R8G8B8_format
+// G5R10 Other
+#define LCD_MCU_DATA_0 ((0x14de << 2) + 0xff000000)
+// ReadOnly
+// G8B8 when R8G8B8_format
+// G5B10 Other
+#define LCD_MCU_DATA_1 ((0x14df << 2) + 0xff000000)
+// LVDS
+#define LVDS_GEN_CNTL ((0x14e0 << 2) + 0xff000000)
+//`define LVDS_PHY_CNTL0 8'he1
+//`define LVDS_PHY_CNTL1 8'he2
+//`define LVDS_PHY_CNTL2 8'he3
+//`define LVDS_PHY_CNTL3 8'he4
+//`define LVDS_PHY_CNTL4 8'he5
+//`define LVDS_PHY_CNTL5 8'he6
+#define LVDS_SRG_TEST ((0x14e8 << 2) + 0xff000000)
+#define LVDS_BIST_MUX0 ((0x14e9 << 2) + 0xff000000)
+#define LVDS_BIST_MUX1 ((0x14ea << 2) + 0xff000000)
+#define LVDS_BIST_FIXED0 ((0x14eb << 2) + 0xff000000)
+#define LVDS_BIST_FIXED1 ((0x14ec << 2) + 0xff000000)
+#define LVDS_BIST_CNTL0 ((0x14ed << 2) + 0xff000000)
+#define LVDS_CLKB_CLKA ((0x14ee << 2) + 0xff000000)
+#define LVDS_PHY_CLK_CNTL ((0x14ef << 2) + 0xff000000)
+#define LVDS_SER_EN ((0x14f0 << 2) + 0xff000000)
+//`define LVDS_PHY_CNTL6 8'hf1
+//`define LVDS_PHY_CNTL7 8'hf2
+//`define LVDS_PHY_CNTL8 8'hf3
+#define LVDS_CH_SWAP0 ((0x14e1 << 2) + 0xff000000)
+#define LVDS_CH_SWAP1 ((0x14e2 << 2) + 0xff000000)
+#define LVDS_CH_SWAP2 ((0x14e3 << 2) + 0xff000000)
+//`define MLVDS_CLK_CTL0_HI 8'hf4
+//`define MLVDS_CLK_CTL0_LO 8'hf5
+// `define mlvds_clk_pattern_reserved 31 // Bit 31
+// `define mpclk_dly 28 // Bit 2:0
+// `define mpclk_div 26 // Bit 1:0 (control phy clok divide 2,4,6,8)
+// `define use_mpclk 25 // Bit 0
+// `define mlvds_clk_half_delay 24 // Bit 0
+// `define mlvds_clk_pattern 0 // Bit 23:0
+//`define MLVDS_DUAL_GATE_WR_START 8'hf6
+// `define mlvds_dual_gate_wr_start 0 // Bit 12:0
+//`define MLVDS_DUAL_GATE_WR_END 8'hf7
+// `define mlvds_dual_gate_wr_end 0 // Bit 12:0
+//
+//`define MLVDS_DUAL_GATE_RD_START 8'hf8
+// `define mlvds_dual_gate_rd_start 0 // Bit 12:0
+//`define MLVDS_DUAL_GATE_RD_END 8'hf9
+// `define mlvds_dual_gate_rd_end 0 // Bit 12:0
+//`define MLVDS_SECOND_RESET_CTL 8'hfa
+// `define mLVDS_2nd_reset_start 0 // Bit 12:0
+//
+#define MLVDS_DUAL_GATE_CTL_HI ((0x14fb << 2) + 0xff000000)
+#define MLVDS_DUAL_GATE_CTL_LO ((0x14fc << 2) + 0xff000000)
+// `define mlvds_tcon_field_en 24 // Bit 7:0
+// `define mlvds_dual_gate_reserved 21 // Bit 2:0
+// `define mlvds_scan_mode_start_line_bit12 20 // Bit 0
+// `define mlvds_scan_mode_odd 16 // Bit 3:0
+// `define mlvds_scan_mode_even 12 // Bit 3:0
+// `define mlvds_scan_mode_start_line 0 // Bit 11:0
+//
+//`define MLVDS_RESET_CONFIG_HI 8'hfd
+//`define MLVDS_RESET_CONFIG_LO 8'hfe
+// `define mLVDS_reset_range_enable 31 // Bit 0
+// `define mLVDS_reset_range_inv 30 // Bit 0
+// `define mLVDS_reset_config_res1 29 // Bit 0
+// `define mLVDS_reset_range_line_0 16 // Bit 11:0
+// `define mLVDS_reset_config_res3 13 // Bit 2:0
+// `define mLVDS_reset_range_line_1 0 // Bit 11:0
+//===============================================================
+//LCD DRIVER BASE END
+//===============================================================
+//
+// Closing file: lcd_regs.h
+//
+//
+// Reading file: vpu_mad_regs.h
+//
+//DEINTERLACE module start from 8'h90 end to 8'hff
+// -----------------------------------------------
+// REG_BASE: MAD_VCBUS_BASE = 0x17
+// -----------------------------------------------
+#define DI_PRE_CTRL ((0x1700 << 2) + 0xff000000)
+// bit 31, cbus_pre_frame_rst
+// bit 30, cbus_pre_soft_rst
+// bit 29, pre_field_num
+// bit 27:26, mode_444c422
+// bit 25, di_cont_read_en
+// bit 24:23, mode_422c444
+// bit 22, mtn_after_nr
+// bit 21:16, pre_hold_fifo_lines
+// bit 15, nr_wr_by
+// bit 14, use_vdin_go_line
+// bit 13, di_prevdin_en
+// bit 12, di_pre_viu_link
+// bit 11, di_pre_repeat
+// bit 10, di_pre_drop_1st
+// bit 9, di_buf2_en
+// bit 8, di_chan2_en
+// bit 7, prenr_hist_en
+// bit 6, chan2_hist_en
+// bit 5, hist_check_en
+// bit 4, check_after_nr
+// bit 3, check222p_en
+// bit 2, check322p_en
+// bit 1, mtn_en
+// bit 0, nr_en
+#define DI_POST_CTRL ((0x1701 << 2) + 0xff000000)
+// bit 31, cbus_post_frame_rst
+// bit 30, cbus_post_soft_rst
+// bit 29, post_field_num
+// bit 21:16, post_hold_fifo_lines
+// bit 13, prepost_link
+// bit 12, di_post_viu_link
+// bit 11, di_post_repeat
+// bit 10, di_post_drop_1st
+// bit 9, mif0_to_vpp_en
+// bit 8, di_vpp_out_en
+// bit 7, di_wr_bk_en
+// bit 6, di_mux_en
+// bit 5, di_blend_en
+// bit 4, di_mtnp_read_en
+// bit 3, di_mtn_buf_en
+// bit 2, di_ei_en
+// bit 1, di_buf1_en
+// bit 0, di_buf0_en
+#define DI_POST_SIZE ((0x1702 << 2) + 0xff000000)
+//bit 31:29, diwr_field_mode field mode, 0 frame mode, 4 for field mode botton field, 5 for field mode top field, , 6 for blank line mode
+//bit 28:16, vsize1post
+//bit 12:0, hsize1post
+#define DI_PRE_SIZE ((0x1703 << 2) + 0xff000000)
+//bit 31:29, nrwr_field_mode field mode, 0 frame mode, 4 for field mode botton field, 5 for field mode top field, , 6 for blank line mode
+//bit 28:16, vsize1pre
+//bit 12:0, hsize1pre
+#define DI_EI_CTRL0 ((0x1704 << 2) + 0xff000000)
+//bit 23:16, ei0_filter[2:+] abs_diff_left>filter && ...right>filter && ...top>filter && ...bot>filter -> filter
+//bit 15:8, ei0_threshold[2:+]
+//bit 3, ei0_vertical
+//bit 2, ei0_bpscf2
+//bit 1, ei0_bpsfar1
+#define DI_EI_CTRL1 ((0x1705 << 2) + 0xff000000)
+//bit 31:24, ei0_diff
+//bit 23:16, ei0_angle45
+//bit 15:8, ei0_peak
+//bit 7:0, ei0_cross
+#define DI_EI_CTRL2 ((0x1706 << 2) + 0xff000000)
+//bit 31:24, ei0_close2
+//bit 23:16, ei0_close1
+//bit 15:8, ei0_far2
+//bit 7:0, ei0_far1
+//`define DI_NR_CTRL0 8'h07
+//bit 26, nr_cue_en
+//bit 25, nr2_en
+#define DI_NR_CTRL1 ((0x1708 << 2) + 0xff000000)
+//bit 31:30, mot_p1txtcore_mode
+//bit 29:24, mot_p1txtcore_clmt
+//bit 21:16, mot_p1txtcore_ylmt
+//bit 15:8, mot_p1txtcore_crate
+//bit 7:0, mot_p1txtcore_yrate
+#define DI_NR_CTRL2 ((0x1709 << 2) + 0xff000000)
+//bit 29:24, mot_curtxtcore_clmt
+//bit 21:16, mot_curtxtcore_ylmt
+//bit 15:8, mot_curtxtcore_crate
+//bit 7:0, mot_curtxtcore_yrate
+//`define DI_NR_CTRL3 8'h0a
+//no use
+//`define DI_MTN_CTRL 8'h0b
+//`define DI_CANVAS_URGENT0 8'h0a
+//`define DI_CANVAS_URGENT1 8'h0b
+#define DI_MTN_CTRL1 ((0x170c << 2) + 0xff000000)
+//bit 11:8, mtn_paramtnthd
+//bit 7:0, mtn_parafltthd
+#define DI_BLEND_CTRL ((0x170d << 2) + 0xff000000)
+//bit 31, blend_1_en
+//bit 30, blend_mtn_lpf
+//bit 28, post_mb_en
+//bit 27, blend_mtn3p_max
+//bit 26, blend_mtn3p_min
+//bit 25, blend_mtn3p_ave
+//bit 24, blend_mtn3p_maxtb
+//bit 23, blend_mtn_flt_en
+//bit 22, blend_data_flt_en
+//bit 21:20, blend_top_mode
+//bit 19, blend_reg3_enable
+//bit 18, blend_reg2_enable
+//bit 17, blend_reg1_enable
+//bit 16, blend_reg0_enable
+//bit 15:14, blend_reg3_mode
+//bit 13:12, blend_reg2_mode
+//bit 11:10, blend_reg1_mode
+//bit 9:8, blend_reg0_mode
+//bit 7:0, kdeint
+//`define DI_BLEND_CTRL1 8'h0e
+//no use
+//`define DI_CANVAS_URGENT2 8'h0e
+//`define DI_BLEND_CTRL2 8'h0f
+//no use
+#define DI_ARB_CTRL ((0x170f << 2) + 0xff000000)
+//bit 31:26, di_arb_thd1
+//bit 25:20, di_arb_thd0
+//bit 19, di_arb_tid_mode
+//bit 18, di_arb_arb_mode
+//bit 17, di_arb_acq_en
+//bit 16, di_arb_disable_clk
+//bit 15:0, di_arb_req_en
+#define DI_BLEND_REG0_X ((0x1710 << 2) + 0xff000000)
+//bit 27:16, blend_reg0_startx
+//bit 11:0, blend_reg0_endx
+#define DI_BLEND_REG0_Y ((0x1711 << 2) + 0xff000000)
+#define DI_BLEND_REG1_X ((0x1712 << 2) + 0xff000000)
+#define DI_BLEND_REG1_Y ((0x1713 << 2) + 0xff000000)
+#define DI_BLEND_REG2_X ((0x1714 << 2) + 0xff000000)
+#define DI_BLEND_REG2_Y ((0x1715 << 2) + 0xff000000)
+#define DI_BLEND_REG3_X ((0x1716 << 2) + 0xff000000)
+#define DI_BLEND_REG3_Y ((0x1717 << 2) + 0xff000000)
+#define DI_CLKG_CTRL ((0x1718 << 2) + 0xff000000)
+//bit 31:24, pre_gclk_ctrl no clk gate control. if ==1, module clk is not gated (always on). [3] for pulldown,[2] for mtn_1,[1] for mtn_0,[0] for nr
+//bit 23:16, post_gclk_ctrl no clk gate control. [4] for ei_1, [3] for ei_0,[2] for ei_top, [1] for blend_1, [0] for blend_0
+//bit 1, di_gate_all clk shut down. if ==1 , all di clock shut down
+//bit 0, di_no_clk_gate no clk gate control. if di_gated_all==0 and di_no_clk_gate ==1, all di clock is always working.
+#define DI_EI_CTRL3 ((0x1719 << 2) + 0xff000000)
+//bit 31, reg_ei_1
+//bit 30, reg_demon_en
+//bit 26:24, reg_demon_mux
+//bit 23:20, reg_right_win
+//bit 19:16, reg_left_win
+//bit 7:4, reg_ei_sadm_quatize_margin
+//bit 1:0, reg_ei_sad_relative_mode
+#define DI_EI_CTRL4 ((0x171a << 2) + 0xff000000)
+//bit 29, reg_ei_caldrt_ambliike2_biasvertical
+//bit 28:24, reg_ei_caldrt_addxla2list_drtmax
+//bit 22:20, reg_ei_caldrt_addxla2list_signm0th
+//bit 19, reg_ei_caldrt_addxla2list_mode
+//bit 18:16, reg_ei_signm_sad_cor_rate
+//bit 15:12, reg_ei_signm_sadi_cor_rate
+//bit 11:6, reg_ei_signm_sadi_cor_ofst
+//bit 5:0, reg_ei_signm_sad_ofst
+#define DI_EI_CTRL5 ((0x171b << 2) + 0xff000000)
+//bit 30:28, reg_ei_caldrt_cnflcctchk_frcverthrd
+//bit 26:24, reg_ei_caldrt_cnflctchk_mg
+//bit 23:22, reg_ei_caldrt_cnflctchk_ws
+//bit 21, reg_ei_caldrt_cnflctchk_en
+//bit 20, reg_ei_caldrt_verfrc_final_en
+//bit 19, reg_ei_caldrt_verfrc_retimflt_en
+//bit 18:16, reg_ei_caldrt_verftc_eithratemth
+//bit 15, reg_ei_caldrt_verfrc_retiming_en
+//bit 14:12, reg_ei_caldrt_verfrc_bothratemth
+//bit 11:9, reg_ei_caldrt_ver_thrd
+//bit 8:4, reg_ei_caldrt_addxla2list_drtmin
+//bit 3:0, reg_ei_caldrt_addxla2list_drtlimit
+#define DI_EI_CTRL6 ((0x171c << 2) + 0xff000000)
+//bit 31:24, reg_ei_caldrt_abext_sad12thhig
+//bit 23:16, reg_ei_caldrt_abext_sad00thlow
+//bit 15:8, reg_ei_caldrt_abext_sad12thlow
+//bit 6:4, reg_ei_caldrt_abext_ratemth
+//bit 2:0, reg_ei_caldrt_abext_drtthrd
+#define DI_EI_CTRL7 ((0x171d << 2) + 0xff000000)
+//bit 29, reg_ei_caldrt_xlanopeak_codien
+//bit 28:24, reg_ei_caldrt_xlanopeak_drtmax
+//bit 23, reg_ei_caldrt_xlanopeak_en
+//bit 28:24, reg_ei_caldrt_abext_monotrnd_alpha
+//bit 28:24, reg_ei_caldrt_abext_mononum12_thrd
+//bit 28:24, reg_ei_caldrt_abext_mononum00_thrd
+//bit 28:24, reg_ei_caldrt_abext_sad00rate
+//bit 28:24, reg_ei_caldrt_abext_sad12rate
+//bit 28:24, reg_ei_caldrt_abext_sad00thhig
+#define DI_EI_CTRL8 ((0x171e << 2) + 0xff000000)
+//bit 30:28, reg_ei_assign_headtail_magin
+//bit 26:24, reg_ei_retime_lastcurpncnfltchk_mode
+//bit 22:21, reg_ei_retime_lastcurpncnfltchk_drtth
+//bit 20, reg_ei_caldrt_histchk_cnfid
+//bit 19:16, reg_ei_caldrt_histchk_thrd
+//bit 15, reg_ei_caldrt_histchk_abext
+//bit 14, reg_ei_caldrt_histchk_npen
+//bit 13:11, reg_ei_caldrt_amblike2_drtmg
+//bit 10:8, reg_ei_caldrt_amblike2_valmg
+//bit 7:4, reg_ei_caldrt_amblike2_alpha
+//bit 3:0, reg_ei_caldrt_amblike2_drtth
+#define DI_EI_CTRL9 ((0x171f << 2) + 0xff000000)
+//bit 31:28, reg_ei_caldrt_hcnfcheck_frcvert_xla_th3
+//bit 27, reg_ei_caldrt_hcnfcheck_frcvert_xla_en
+//bit 26:24, reg_ei_caldrt_conf_drtth
+//bit 23:20, reg_ei_caldrt_conf_absdrtth
+//bit 19:18, reg_ei_caldrt_abcheck_mode1
+//bit 17:16, reg_ei_caldrt_abcheck_mode0
+//bit 15:12, reg_ei_caldrt_abcheck_drth1
+//bit 11:8, reg_ei_caldrt_abcheck_drth0
+//bit 6:4, reg_ei_caldrt_abpnchk1_th
+//bit 1, reg_ei_caldrt_abpnchk1_en
+//bit 0, reg_ei_caldrt_abpnchk0_en
+// DEINTERLACE mode check.
+#define DI_MC_REG0_X ((0x1720 << 2) + 0xff000000)
+//bit 27:16, mc_reg0_start_x
+//bit 11:0, mc_reg0_end_x
+#define DI_MC_REG0_Y ((0x1721 << 2) + 0xff000000)
+#define DI_MC_REG1_X ((0x1722 << 2) + 0xff000000)
+#define DI_MC_REG1_Y ((0x1723 << 2) + 0xff000000)
+#define DI_MC_REG2_X ((0x1724 << 2) + 0xff000000)
+#define DI_MC_REG2_Y ((0x1725 << 2) + 0xff000000)
+#define DI_MC_REG3_X ((0x1726 << 2) + 0xff000000)
+#define DI_MC_REG3_Y ((0x1727 << 2) + 0xff000000)
+#define DI_MC_REG4_X ((0x1728 << 2) + 0xff000000)
+#define DI_MC_REG4_Y ((0x1729 << 2) + 0xff000000)
+#define DI_MC_32LVL0 ((0x172a << 2) + 0xff000000)
+//bit 31:24, mc_reg2_32lvl
+//bit 23:16, mc_reg1_32lvl
+//bit 15:8, mc_reg0_32lvl
+//bit 7:0, field_32lvl
+#define DI_MC_32LVL1 ((0x172b << 2) + 0xff000000)
+//bit 15:8, mc_reg3_32lvl
+//bit 7:0, mc_reg4_32lvl
+#define DI_MC_22LVL0 ((0x172c << 2) + 0xff000000)
+//bit 31:16, mc_reg0_22lvl
+//bit 15:0, field_22lvl
+#define DI_MC_22LVL1 ((0x172d << 2) + 0xff000000)
+//bit 31:16, mc_reg2_22lvl
+//bit 15:0, mc_reg1_22lvl
+#define DI_MC_22LVL2 ((0x172e << 2) + 0xff000000)
+//bit 31:16, mc_reg4_22lvl
+//bit 15:0, mc_reg3_22lvl
+#define DI_MC_CTRL ((0x172f << 2) + 0xff000000)
+//bit 4, mc_reg4_en
+//bit 3, mc_reg3_en
+//bit 2, mc_reg2_en
+//bit 1, mc_reg1_en
+//bit 0, mc_reg0_en
+#define DI_INTR_CTRL ((0x1730 << 2) + 0xff000000)
+#define DI_INFO_ADDR ((0x1731 << 2) + 0xff000000)
+#define DI_INFO_DATA ((0x1732 << 2) + 0xff000000)
+#define DI_PRE_HOLD ((0x1733 << 2) + 0xff000000)
+//// DET 3D REG DEFINE BEGIN ////
+//// 8'h34~8'h3f
+// `define DET3D_MOTN_CFG 8'h34
+// //Bit 16, reg_det3d_intr_en Det3d interrupt enable
+// //Bit 9:8, reg_Det3D_Motion_Mode U2 Different mode for Motion Calculation of Luma and Chroma:
+// // 0: MotY, 1: (2*MotY + (MotU + MotV))/4; 2: Max(MotY, MotU,MotV); 3:Max(MotY, (MotU+MotV)/2)
+// //Bit 7:4, reg_Det3D_Motion_Core_Rate U4 K Rate to Edge (HV) details for coring of Motion Calculations, normalized to 32
+// //Bit 3:0, reg_Det3D_Motion_Core_Thrd U4 2X: static coring value for Motion Detection.
+//
+// `define DET3D_CB_CFG 8'h35
+// //Bit 7:4, reg_Det3D_ChessBd_NHV_ofst U4, Noise immune offset for NON-Horizotnal or vertical combing detection.
+// //Bit 3:0, reg_Det3D_ChessBd_HV_ofst U4, Noise immune offset for Horizotnal or vertical combing detection.
+//
+// `define DET3D_SPLT_CFG 8'h36
+// //Bit 7:4, reg_Det3D_SplitValid_ratio U4, Ratio between max_value and the avg_value of the edge mapping for split line valid detection.
+// // The smaller of this value, the easier of the split line detected.
+// //Bit 3:0, reg_Det3D_AvgIdx_ratio U4, Ratio to the avg_value of the edge mapping for split line position estimation.
+// // The smaller of this value, the more samples will be added to the estimation.
+//
+// `define DET3D_HV_MUTE 8'h37
+// //Bit 23:20, reg_Det3D_Edge_Ver_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Top and Bottom border part.
+// //Bit 19:16, reg_Det3D_Edge_Hor_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Left and right border part.
+// //Bit 15:12, reg_Det3D_ChessBd_Ver_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part
+// //Bit 11:8, reg_Det3D_ChessBd_Hor_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part
+// //Bit 7:4, reg_Det3D_STA8X8_Ver_Mute U4 1X: Vertical pixels to be mute from 8x8 statistics calculation in each block.
+// //Bit 3:0, reg_Det3D_STA8X8_Hor_Mute U4 1X: Horizontal pixels to be mute from 8x8 statistics calculation in each block.
+//
+// `define DET3D_MAT_STA_P1M1 8'h38
+// //Bit 31:24, reg_Det3D_STA8X8_P1_K0_R8 U8 SAD to SAI ratio to decide P1, normalized to 256 (0.8)
+// //Bit 23:16, reg_Det3D_STA8X8_P1_K1_R7 U8 SAD to ENG ratio to decide P1, normalized to 128 (0.5)
+// //Bit 15:8, reg_Det3D_STA8X8_M1_K0_R6 U8 SAD to SAI ratio to decide M1, normalized to 64 (1.1)
+// //Bit 7:0, reg_Det3D_STA8X8_M1_K1_R6 U8 SAD to ENG ratio to decide M1, normalized to 64 (0.8)
+//
+// `define DET3D_MAT_STA_P1TH 8'h39
+// //Bit 23:16, reg_Det3D_STAYUV_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (100)
+// //Bit 15:8, reg_Det3D_STAEDG_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (80)
+// //Bit 7:0, reg_Det3D_STAMOT_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (48)
+//
+// `define DET3D_MAT_STA_M1TH 8'h3a
+// //Bit 23:16, reg_Det3D_STAYUV_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (100)
+// //Bit 15:8, reg_Det3D_STAEDG_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (80)
+// //Bit 7:0, reg_Det3D_STAMOT_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (64)
+//
+// `define DET3D_MAT_STA_RSFT 8'h3b
+// //Bit 5:4, reg_Det3D_STAYUV_RSHFT U2 YUV statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
+// // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
+// //Bit 3:2, reg_Det3D_STAEDG_RSHFT U2 Horizontal and Vertical Edge Statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
+// // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
+// //Bit 1:0, reg_Det3D_STAMOT_RSHFT U2 Motion SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
+// // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
+//
+// `define DET3D_MAT_SYMTC_TH 8'h3c
+// //Bit 31:24, reg_Det3D_STALUM_symtc_Th U8 threshold to decide if the Luma statistics is TB or LR symmetric.
+// //Bit 23:16, reg_Det3D_STACHR_symtc_Th U8 threshold to decide if the Chroma (UV) statistics is TB or LR symmetric.
+// //Bit 15:8, reg_Det3D_STAEDG_symtc_Th U8 threshold to decide if the Horizontal and Vertical Edge statistics is TB or LR symmetric.
+// //Bit 7:0, reg_Det3D_STAMOT_symtc_Th U8 threshold to decide if the Motion statistics is TB or LR symmetric.
+//
+// `define DET3D_RO_DET_CB_HOR 8'h3d
+// //Bit 31:16, RO_Det3D_ChessBd_NHor_value U16 X64: number of Pixels of Horizontally Surely NOT matching Chessboard pattern.
+// //Bit 15:0, RO_Det3D_ChessBd_Hor_value U16 X64: number of Pixels of Horizontally Surely matching Chessboard pattern.
+//
+// `define DET3D_RO_DET_CB_VER 8'h3e
+// //Bit 31:16, RO_Det3D_ChessBd_NVer_value U16 X64: number of Pixels of Vertically Surely NOT matching Chessboard pattern.
+// //Bit 15:0, RO_Det3D_ChessBd_Ver_value U16 X64: number of Pixels of Vertically Surely matching Chessboard pattern.
+//
+// `define DET3D_RO_SPLT_HT 8'h3f
+// //Bit 24, RO_Det3D_Split_HT_valid U1 horizontal LR split border detected valid signal for top half picture
+// //Bit 20:16, RO_Det3D_Split_HT_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+// //Bit 9:0, RO_Det3D_Split_HT_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+//
+// //// DET 3D REG DEFINE END ////
+#define DI_MTN_1_CTRL1 ((0x1740 << 2) + 0xff000000)
+//bit 31, mtn_1_en
+//bit 30, mtn_init
+//bit 29, di2nr_txt_en
+//bit 28, reserved
+//bit 27:24, mtn_def
+//bit 23:16, mtn_adp_yc
+//bit 15:8, mtn_adp_2c
+//bit 7:0, mtn_adp_2y
+#define DI_MTN_1_CTRL2 ((0x1741 << 2) + 0xff000000)
+//bit 31:24, mtn_ykinter
+//bit 23:16, mtn_ckinter
+//bit 15:8, mtn_ykintra
+//bit 7:0, mtn_ckintra
+#define DI_MTN_1_CTRL3 ((0x1742 << 2) + 0xff000000)
+//bit 31:24, mtn_tyrate
+//bit 23:16, mtn_tcrate
+//bit 15: 8, mtn_mxcmby
+//bit 7: 0, mtn_mxcmbc
+#define DI_MTN_1_CTRL4 ((0x1743 << 2) + 0xff000000)
+//bit 31:24, mtn_tcorey
+//bit 23:16, mtn_tcorec
+//bit 15: 8, mtn_minth
+//bit 7: 0, mtn_maxth
+#define DI_MTN_1_CTRL5 ((0x1744 << 2) + 0xff000000)
+//bit 31:28, mtn_m1b_extnd
+//bit 27:24, mtn_m1b_errod
+//bit 21:20, mtn_mot_txt_mode
+//bit 19:18, mtn_replace_cbyy
+//bit 17:16, mtn_replace_ybyc
+//bit 15: 8, mtn_core_ykinter
+//bit 7: 0, mtn_core_ckinter
+//// NR2 REG DEFINE BEGIN////
+#define NR2_MET_NM_CTRL ((0x1745 << 2) + 0xff000000)
+//Bit 28, reg_NM_reset Reset to the status of the Loop filter.
+//Bit 27:24, reg_NM_calc_length Length mode of the Noise measurement sample number for statistics.
+// 0: 256 samples; 1: 512 samples; 2: 1024 samples; ¡X: 2^(8+x) samples
+//Bit 23:20, reg_NM_inc_step Loop filter input gain increase step.
+//Bit 19:16, reg_NM_dec_step Loop filter input gain decrease step.
+//Bit 15:8, reg_NM_YHPmot_thrd Luma channel HP portion motion for condition of pixels included in Luma Noise measurement.
+//Bit 7:0, reg_NM_CHPmot_thrd Chroma channel HP portion motion for condition of pixels included in Chroma Noise measurement.
+#define NR2_MET_NM_YCTRL ((0x1746 << 2) + 0xff000000)
+//Bit 31:28, reg_NM_YPLL_target Target rate of NM_Ynoise_thrd to mean of the Luma Noise
+//Bit 27:24, reg_NM_YLPmot_thrd Luma channel LP portion motion for condition of pixels included in Luma Noise measurement.
+//Bit 23:16, reg_NM_YHPmot_thrd_min Minimum threshold for Luma channel HP portion motion to decide whether the pixel will be included in Luma noise measurement.
+//Bit 15:8, reg_NM_YHPmot_thrd_max Maximum threshold for Luma channel HP portion motion to decide whether the pixel will be included in Luma noise measurement.
+//Bit 7:0, reg_NM_Ylock_rate Rate to decide whether the Luma noise measurement is lock or not.
+#define NR2_MET_NM_CCTRL ((0x1747 << 2) + 0xff000000)
+//Bit 31:28, reg_NM_CPLL_target Target rate of NM_Cnoise_thrd to mean of the Chroma Noise
+//Bit 27:24, reg_NM_CLPmot_thrd Chroma channel LP portion motion for condition of pixels included in Chroma Noise measurement.
+//Bit 23:16, reg_NM_CHPmot_thrd_min Minimum threshold for Chroma channel HP portion motion to decide whether the pixel will be included in Chroma noise measurement.
+//Bit 15:8, reg_NM_CHPmot_thrd_max Maximum threshold for Chroma channel HP portion motion to decide whether the pixel will be included in Chroma noise measurement.
+//Bit 7:0, reg_NM_Clock_rate Rate to decide whether the Chroma noise measurement is lock or not;
+#define NR2_MET_NM_TNR ((0x1748 << 2) + 0xff000000)
+//Bit 25, ro_NM_TNR_Ylock Read-only register to tell ifLuma channel noise measurement is locked or not.
+//Bit 24, ro_NM_TNR_Clock Read-only register to tell if Chroma channel noise measurement is locked or not.
+//Bit 23:12, ro_NM_TNR_Ylevel Read-only register to give Luma channel noise level. It was 16x of pixel difference in 8 bits of YHPmot.
+//Bit 11:0, ro_NM_TNR_Clevel Read-only register to give Chroma channel noise level. It was 16x of pixel difference in 8 bits of CHPmot.
+#define NR2_MET_NMFRM_TNR_YLEV ((0x1749 << 2) + 0xff000000)
+//Bit 28:0, ro_NMFrm_TNR_Ylevel Frame based Read-only register to give Luma channel noise level within one frame/field.
+#define NR2_MET_NMFRM_TNR_YCNT ((0x174a << 2) + 0xff000000)
+//Bit 23:0, ro_NMFrm_TNR_Ycount Number ofLuma channel pixels included in Frame/Field based noise level measurement.
+#define NR2_MET_NMFRM_TNR_CLEV ((0x174b << 2) + 0xff000000)
+//Bit 28:0, ro_NMFrm_TNR_Clevel Frame based Read-only register to give Chroma channel noise level within one frame/field.
+#define NR2_MET_NMFRM_TNR_CCNT ((0x174c << 2) + 0xff000000)
+//Bit 23:0, ro_NMFrm_TNR_Ccount Number of Chroma channel pixels included in Frame/Field based noise level measurement.
+#define NR2_3DEN_MODE ((0x174d << 2) + 0xff000000)
+//Bit 6:4, Blend_3dnr_en_r
+//Bit 2:0, Blend_3dnr_en_l
+// `define NR2_IIR_CTRL 8'h4e
+// //Bit 15:14, reg_LP_IIR_8bit_mode LP IIR membitwidth mode:0: 10bits will be store in memory;1: 9bits will be store in memory;
+// // 2: 8bits will be store in memory;3: 7bits will be store in memory;
+// //Bit 13:12, reg_LP_IIR_mute_mode Mode for the LP IIR mute,
+// //Bit 11:8, reg_LP_IIR_mute_thrd Threshold of LP IIR mute to avoid ghost:
+// //Bit 7:6, reg_HP_IIR_8bit_mode IIR membitwidth mode:0: 10bits will be store in memory;1: 9bits will be store in memory;
+// // 2: 8bits will be store in memory;3: 7bits will be store in memory;
+// //Bit 5:4, reg_HP_IIR_mute_mode Mode for theLP IIR mute
+// //Bit 3:0, reg_HP_IIR_mute_thrd Threshold of HP IIR mute to avoid ghost
+// //
+#define NR2_SW_EN ((0x174f << 2) + 0xff000000)
+//Bit 17:8, Clk_gate_ctrl
+//Bit 7, Cfr_enable
+//Bit 5, Det3d_en
+//Bit 4, Nr2_proc_en
+//Bit 0, Nr2_sw_en
+#define NR2_FRM_SIZE ((0x1750 << 2) + 0xff000000)
+//Bit 27:16, Frm_heigh Frame/field height
+//Bit 11: 0, Frm_width Frame/field width
+// `define NR2_SNR_SAD_CFG 8'h51
+// //Bit 12, reg_MATNR_SNR_SAD_CenRPL U1, Enable signal for Current pixel position SAD to be replaced by SAD_min.0: do not replace Current pixel position SAD by SAD_min;1: do replacements
+// //Bit 11:8, reg_MATNR_SNR_SAD_coring Coring value of the intra-frame SAD. sum = (sum - reg_MATNR_SNR_SAD_coring);sum = (sum<0) ? 0: (sum>255)? 255: sum;
+// //Bit 6:5, reg_MATNR_SNR_SAD_WinMod Unsigned, Intra-frame SAD matching window mode:0: 1x1; 1: [1 1 1] 2: [1 2 1]; 3: [1 2 2 2 1];
+// //Bit 4:0, Sad_coef_num Sad coeffient
+//
+// `define NR2_MATNR_SNR_OS 8'h52
+// //Bit 7:4, reg_MATNR_SNR_COS SNR Filter overshoot control margin for UV channel (X2 to u10 scale)
+// //Bit 3:0, reg_MATNR_SNR_YOS SNR Filter overshoot control margin for luma channel (X2 to u10 scale)
+//
+// `define NR2_MATNR_SNR_NRM_CFG 8'h53
+// //Bit 23:16, reg_MATNR_SNR_NRM_ofst Edge based SNR boosting normalization offset to SAD_max ;
+// //Bit 15:8, reg_MATNR_SNR_NRM_max Edge based SNR boosting normalization Max value
+// //Bit 7:0, reg_MATNR_SNR_NRM_min Edge based SNR boosting normalization Min value
+//
+// `define NR2_MATNR_SNR_NRM_GAIN 8'h54
+// //Bit 15:8, reg_MATNR_SNR_NRM_Cgain Edge based SNR boosting normalization Gain for Chrm channel (norm 32 as 1)
+// //Bit 7:0, reg_MATNR_SNR_NRM_Ygain Edge based SNR boosting normalization Gain for Luma channel (norm 32 as 1)
+//
+// `define NR2_MATNR_SNR_LPF_CFG 8'h55
+// //Bit 23:16,reg_MATNR_SNRLPF_SADmaxTH U8, Threshold to SADmax to use TNRLPF to replace SNRLPF. i.e.if (SAD_max<reg_MATNR_SNRLPF_SADmaxTH) SNRLPF_yuv[k] = TNRLPF_yuv[k];
+// //Bit 13:11,reg_MATNR_SNRLPF_Cmode LPF based SNR filtering mode on CHRM channel:
+// // 0: gradient LPF [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8; 3: gradient LPF [5 4 4 3]/16;
+// // 4: TNRLPF; 5 : CurLPF3x3_yuv[]; 6: CurLPF3o3_yuv[] 7: CurLPF3x5_yuv[]
+// //Bit 10:8, reg_MATNR_SNRLPF_Ymode LPF based SNR filtering mode on LUMA channel:
+// // 0: gradient LPF //Bit [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8;3: gradient LPF [5 4 4 3]/16;
+// // 4: TNRLPF; 5 : CurLPF3x3_yuv[]; 6: CurLPF3o3_yuv[] 7: CurLPF3x5_yuv[]
+// //Bit 7:4, reg_MATNR_SNRLPF_SADmin3TH Offset threshold to SAD_min to Discard SAD_min3 corresponding pixel in LPF SNR filtering. (X8 to u8 scale)
+// //Bit 3:0, reg_MATNR_SNRLPF_SADmin2TH Offset threshold to SAD_min to Discard SAD_min2 corresponding pixel in LPF SNR filtering. (X8 to u8 scale)
+//
+// `define NR2_MATNR_SNR_USF_GAIN 8'h56
+// //Bit 15:8, reg_MATNR_SNR_USF_Cgain Un-sharp (HP) compensate back Chrm portion gain, (norm 64 as 1)
+// //Bit 7:0, reg_MATNR_SNR_USF_Ygain Un-sharp (HP) compensate back Luma portion gain, (norm 64 as 1)
+//
+// `define NR2_MATNR_SNR_EDGE2B 8'h57
+// //Bit 15:8, reg_MATNR_SNR_Edge2Beta_ofst U8, Offset for Beta based on Edge.
+// //Bit 7:0, reg_MATNR_SNR_Edge2Beta_gain U8. Gain to SAD_min for Beta based on Edge. (norm 16 as 1)
+//
+// `define NR2_MATNR_BETA_EGAIN 8'h58
+// //Bit 15:8, reg_MATNR_CBeta_Egain U8, Gain to Edge based Beta for Chrm channel. (normalized to 32 as 1)
+// //Bit 7:0, reg_MATNR_YBeta_Egain U8, Gain to Edge based Beta for Luma channel. (normalized to 32 as 1)
+//
+// `define NR2_MATNR_BETA_BRT 8'h59
+// //Bit 31:28, reg_MATNR_beta_BRT_limt_hi U4, Beta adjustment based on Brightness high side Limit. (X16 to u8 scale)
+// //Bit 27:24, reg_MATNR_beta_BRT_slop_hi U4, Beta adjustment based on Brightness high side slope. Normalized to 16 as 1
+// //Bit 23:16, reg_MATNR_beta_BRT_thrd_hi U8, Beta adjustment based on Brightness high threshold.(u8 scale)
+// //Bit 15:12, reg_MATNR_beta_BRT_limt_lo U4, Beta adjustment based on Brightness low side Limit. (X16 to u8 scale)
+// //Bit 11:8, reg_MATNR_beta_BRT_slop_lo U4, Beta adjustment based on Brightness low side slope. Normalized to 16 as 1
+// //Bit 7:0, reg_MATNR_beta_BRT_thrd_lo U8, Beta adjustment based on Brightness low threshold.(u8 scale)
+// `define NR2_MATNR_XBETA_CFG 8'h5a
+// //Bit 19:18, reg_MATNR_CBeta_use_mode U2, Beta options (mux) from beta_motion and beta_edge for Chrm channel;
+// //Bit 17:16, reg_MATNR_YBeta_use_mode U2, Beta options (mux) from beta_motion and beta_edge for Luma channel;
+// //Bit 15: 8, reg_MATNR_CBeta_Ofst U8, Offset to Beta for Chrm channel.(after beta_edge and beta_motion mux)
+// //Bit 7: 0, reg_MATNR_YBeta_Ofst U8, Offset to Beta for Luma channel.(after beta_edge and beta_motion mux)
+// `define NR2_MATNR_YBETA_SCL 8'h5b
+// //Bit 31:24, reg_MATNR_YBeta_scale_min U8, Final step Beta scale low limit for Luma channel;
+// //Bit 23:16, reg_MATNR_YBeta_scale_max U8, Final step Beta scale high limit for Luma channe;
+// //Bit 15: 8, reg_MATNR_YBeta_scale_gain U8, Final step Beta scale Gain for Luma channel (normalized 32 to 1);
+// //Bit 7 : 0, reg_MATNR_YBeta_scale_ofst S8, Final step Beta scale offset for Luma channel ;
+// `define NR2_MATNR_CBETA_SCL 8'h5c
+// //Bit 31:24, reg_MATNR_CBeta_scale_min Final step Beta scale low limit for Chrm channel.Similar to Y
+// //Bit 23:16, reg_MATNR_CBeta_scale_max U8, Final step Beta scale high limit for Chrm channel.Similar to Y
+// //Bit 15: 8, reg_MATNR_CBeta_scale_gain U8, Final step Beta scale Gain for Chrm channel Similar to Y
+// //Bit 7: 0, reg_MATNR_CBeta_scale_ofst S8, Final step Beta scale offset for Chrm channel Similar to Y
+// `define NR2_SNR_MASK 8'h5d
+// //Bit 20:0, SAD_MSK Valid signal in the 3x7 SAD surface
+// `define NR2_SAD2NORM_LUT0 8'h5e
+// //Bit 31:24, reg_MATNR_SAD2Norm_LUT_3 SAD convert normal LUT node 3
+// //Bit 23:16, reg_MATNR_SAD2Norm_LUT_2 SAD convert normal LUT node 2
+// //Bit 15: 8, reg_MATNR_SAD2Norm_LUT_1 SAD convert normal LUT node 1
+// //Bit 7: 0, reg_MATNR_SAD2Norm_LUT_0 SAD convert normal LUT node 0
+// `define NR2_SAD2NORM_LUT1 8'h5f
+// //Bit 31:24, reg_MATNR_SAD2Norm_LUT_7 SAD convert normal LUT node 7
+// //Bit 23:16, reg_MATNR_SAD2Norm_LUT_6 SAD convert normal LUT node 6
+// //Bit 15: 8, reg_MATNR_SAD2Norm_LUT_5 SAD convert normal LUT node 5
+// //Bit 7: 0, reg_MATNR_SAD2Norm_LUT_4 SAD convert normal LUT node 4
+// `define NR2_SAD2NORM_LUT2 8'h60
+// //Bit 31:24, reg_MATNR_SAD2Norm_LUT_11 SAD convert normal LUT node 11
+// //Bit 23:16, reg_MATNR_SAD2Norm_LUT_10 SAD convert normal LUT node 10
+// //Bit 15: 8, reg_MATNR_SAD2Norm_LUT_9 SAD convert normal LUT node 9
+// //Bit 7: 0, reg_MATNR_SAD2Norm_LUT_8 SAD convert normal LUT node 8
+// `define NR2_SAD2NORM_LUT3 8'h61
+// //Bit 31:24, reg_MATNR_SAD2Norm_LUT_15 SAD convert normal LUT node 15
+// //Bit 23:16, reg_MATNR_SAD2Norm_LUT_14 SAD convert normal LUT node 14
+// //Bit 15:8, reg_MATNR_SAD2Norm_LUT_13 SAD convert normal LUT node 13
+// //Bit 7:0, reg_MATNR_SAD2Norm_LUT_12 SAD convert normal LUT node 12
+// `define NR2_EDGE2BETA_LUT0 8'h62
+// //Bit 31:24, reg_MATNR_Edge2Beta_LUT_3 Edge convert beta LUT node 3
+// //Bit 23:16, reg_MATNR_Edge2Beta_LUT_2 Edge convert beta LUT node 2
+// //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_1 Edge convert beta LUT node 1
+// //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_0 Edge convert beta LUT node 0
+// `define NR2_EDGE2BETA_LUT1 8'h63
+// //Bit 31:24, reg_MATNR_Edge2Beta_LUT_7 Edge convert beta LUT node 7
+// //Bit 23:16, reg_MATNR_Edge2Beta_LUT_6 Edge convert beta LUT node 6
+// //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_5 Edge convert beta LUT node 5
+// //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_4 Edge convert beta LUT node 4
+// `define NR2_EDGE2BETA_LUT2 8'h64
+// //Bit 31:24, reg_MATNR_Edge2Beta_LUT_11 Edge convert beta LUT node 11
+// //Bit 23:16, reg_MATNR_Edge2Beta_LUT_10 Edge convert beta LUT node 10
+// //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_9 Edge convert beta LUT node 9
+// //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_8 Edge convert beta LUT node 8
+// `define NR2_EDGE2BETA_LUT3 8'h65
+// //Bit 31:24, reg_MATNR_Edge2Beta_LUT_15 Edge convert beta LUT node 15
+// //Bit 23:16, reg_MATNR_Edge2Beta_LUT_14 Edge convert beta LUT node 14
+// //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_13 Edge convert beta LUT node 13
+// //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_12 Edge convert beta LUT node 12
+// `define NR2_MOTION2BETA_LUT0 8'h66
+// //Bit 31:24, reg_MATNR_Mot2Beta_LUT_3 Motion convert beta LUT node 3
+// //Bit 23:16, reg_MATNR_Mot2Beta_LUT_2 Motion convert beta LUT node 2
+// //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_1 Motion convert beta LUT node 1
+// //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_0 Motion convert beta LUT node 0
+// `define NR2_MOTION2BETA_LUT1 8'h67
+// //Bit 31:24, reg_MATNR_Mot2Beta_LUT_7 Motion convert beta LUT node 7
+// //Bit 23:16, reg_MATNR_Mot2Beta_LUT_6 Motion convert beta LUT node 6
+// //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_5 Motion convert beta LUT node 5
+// //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_4 Motion convert beta LUT node 4
+// `define NR2_MOTION2BETA_LUT2 8'h68
+// //Bit 31:24, reg_MATNR_Mot2Beta_LUT_11 Motion convert beta LUT node 11
+// //Bit 23:16, reg_MATNR_Mot2Beta_LUT_10 Motion convert beta LUT node 10
+// //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_9 Motion convert beta LUT node 9
+// //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_8 Motion convert beta LUT node 8
+// `define NR2_MOTION2BETA_LUT3 8'h69
+// //Bit 31:24, reg_MATNR_Mot2Beta_LUT_15 Motion convert beta LUT node 15
+// //Bit 23:16, reg_MATNR_Mot2Beta_LUT_14 Motion convert beta LUT node 14
+// //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_13 Motion convert beta LUT node 13
+// //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_12 Motion convert beta LUT node 12
+// `define NR2_MATNR_MTN_CRTL 8'h6a
+// //Bit 25:24, reg_MATNR_Vmtn_use_mode Motion_yuvV channel motion selection mode:0: Vmot;1:Ymot/2 + (Umot+Vmot)/4; 2:Ymot/2 + max(Umot,Vmot)/2; 3: max(Ymot,Umot, Vmot)
+// //Bit 21:20, reg_MATNR_Umtn_use_mode Motion_yuvU channel motion selection mode:0:Umot;1:Ymot/2 + (Umot+Vmot)/4; 2:Ymot/2 + max(Umot,Vmot)/2; 3: max(Ymot,Umot, Vmot)
+// //Bit 17:16, reg_MATNR_Ymtn_use_mode Motion_yuvLuma channel motion selection mode:0: Ymot, 1: Ymot/2 + (Umot+Vmot)/4; 2: Ymot/2 + max(Umot,Vmot)/2; 3: max(Ymot,Umot, Vmot)
+// //Bit 13:12, reg_MATNR_mtn_txt_mode Texture detection mode for adaptive coring of HP motion
+// //Bit 9: 8, reg_MATNR_mtn_cor_mode Coring selection mode based on texture detection;
+// //Bit 6: 4, reg_MATNR_mtn_hpf_mode video mode of current and previous frame/field for MotHPF_yuv[k] calculation:
+// //Bit 2: 0, reg_MATNR_mtn_lpf_mode LPF video mode of current and previous frame/field for MotLPF_yuv[k] calculation:
+// `define NR2_MATNR_MTN_CRTL2 8'h6b
+// //Bit 18:16, reg_MATNR_iir_BS_Ymode IIR TNR filter Band split filter mode for Luma LPF result generation (Cur and Prev);
+// //Bit 15: 8, reg_MATNR_mtnb_alpLP_Cgain Scale of motion_brthp_uv to motion_brtlp_uv, normalized to 32 as 1
+// //Bit 7: 0, reg_MATNR_mtnb_alpLP_Ygain Scale of motion_brthp_y to motion_brtlp_y, normalized to 32 as 1
+// `define NR2_MATNR_MTN_COR 8'h6c
+// //Bit 15:12, reg_MATNR_mtn_cor_Cofst Coring Offset for Chroma Motion.
+// //Bit 11: 8, reg_MATNR_mtn_cor_Cgain Gain to texture based coring for Chroma Motion. Normalized to 16 as 1
+// //Bit 7: 4, reg_MATNR_mtn_cor_Yofst Coring Offset for Luma Motion.
+// //Bit 3: 0, reg_MATNR_mtn_cor_Ygain Gain to texture based coring for Luma Motion. Normalized to 16 as 1
+// `define NR2_MATNR_MTN_GAIN 8'h6d
+// //Bit 31:24, reg_MATNR_mtn_hp_Cgain Gain to MotHPF_yuv[k] Chrm channel for motion calculation, normalized to 64 as 1
+// //Bit 23:16, reg_MATNR_mtn_hp_Ygain Gain to MotHPF_yuv[k] Luma channel for motion calculation, normalized to 64 as 1
+// //Bit 15: 8, reg_MATNR_mtn_lp_Cgain Gain to MotLPF_yuv[k] Chrm channel for motion calculation, normalized to 32 as 1
+// //Bit 7: 0, reg_MATNR_mtn_lp_Ygain Gain to MotLPF_yuv[k] Luma channel for motion calculation, normalized to 32 as 1
+// `define NR2_MATNR_DEGHOST 8'h6e
+// //Bit 8, reg_MATNR_DeGhost_En Enable signal for DeGhost function:0: disable; 1: enable
+// //Bit 7:4, reg_MATNR_DeGhost_COS DeGhost Overshoot margin for UV channel, (X2 to u10 scale)
+// //Bit 3:0, reg_MATNR_DeGhost_YOS DeGhost Overshoot margin for Luma channel, (X2 to u10 scale)
+//
+// `define NR2_MATNR_ALPHALP_LUT0 8'h6f
+// //Bit 31:24, reg_MATNR_AlphaLP_LUT_3 Matnr low-pass filter alpha LUT node 3
+// //Bit 23:16, reg_MATNR_AlphaLP_LUT_2 Matnr low-pass filter alpha LUT node 2
+// //Bit 15: 8, reg_MATNR_AlphaLP_LUT_1 Matnr low-pass filter alpha LUT node 1
+// //Bit 7: 0, reg_MATNR_AlphaLP_LUT_0 Matnr low-pass filter alpha LUT node 0
+// `define NR2_MATNR_ALPHALP_LUT1 8'h70
+// //Bit 31:24, reg_MATNR_AlphaLP_LUT_7 Matnr low-pass filter alpha LUT node 7
+// //Bit 23:16, reg_MATNR_AlphaLP_LUT_6 Matnr low-pass filter alpha LUT node 6
+// //Bit 15: 8, reg_MATNR_AlphaLP_LUT_5 Matnr low-pass filter alpha LUT node 5
+// //Bit 7: 0, reg_MATNR_AlphaLP_LUT_4 Matnr low-pass filter alpha LUT node 4
+// `define NR2_MATNR_ALPHALP_LUT2 8'h71
+// //Bit 31:24, reg_MATNR_AlphaLP_LUT_11 Matnr low-pass filter alpha LUT node 11
+// //Bit 23:16, reg_MATNR_AlphaLP_LUT_10 Matnr low-pass filter alpha LUT node 10
+// //Bit 15: 8, reg_MATNR_AlphaLP_LUT_9 Matnr low-pass filter alpha LUT node 9
+// //Bit 7: 0, reg_MATNR_AlphaLP_LUT_8 Matnr low-pass filter alpha LUT node 8
+// `define NR2_MATNR_ALPHALP_LUT3 8'h72
+// //Bit 31:24, reg_MATNR_AlphaLP_LUT_15 Matnr low-pass filter alpha LUT node 15
+// //Bit 23:16, reg_MATNR_AlphaLP_LUT_14 Matnr low-pass filter alpha LUT node 14
+// //Bit 15: 8, reg_MATNR_AlphaLP_LUT_13 Matnr low-pass filter alpha LUT node 13
+// //Bit 7: 0, reg_MATNR_AlphaLP_LUT_12 Matnr low-pass filter alpha LUT node 12
+// `define NR2_MATNR_ALPHAHP_LUT0 8'h73
+// //Bit 31:24, reg_MATNR_AlphaHP_LUT_3 Matnr high-pass filter alpha LUT node 3
+// //Bit 23:16, reg_MATNR_AlphaHP_LUT_2 Matnr high-pass filter alpha LUT node 2
+// //Bit 15: 8, reg_MATNR_AlphaHP_LUT_1 Matnr high-pass filter alpha LUT node 1
+// //Bit 7: 0, reg_MATNR_AlphaHP_LUT_0 Matnr high-pass filter alpha LUT node 0
+// `define NR2_MATNR_ALPHAHP_LUT1 8'h74
+// //Bit 31:24, reg_MATNR_AlphaHP_LUT_7 Matnr high-pass filter alpha LUT node 7
+// //Bit 23:16, reg_MATNR_AlphaHP_LUT_6 Matnr high-pass filter alpha LUT node 6
+// //Bit 15: 8, reg_MATNR_AlphaHP_LUT_5 Matnr high-pass filter alpha LUT node 5
+// //Bit 7: 0, reg_MATNR_AlphaHP_LUT_4 Matnr high-pass filter alpha LUT node 4
+// `define NR2_MATNR_ALPHAHP_LUT2 8'h75
+// //Bit 31:24, reg_MATNR_AlphaHP_LUT_11 Matnr high-pass filter alpha LUT node 11
+// //Bit 23:16, reg_MATNR_AlphaHP_LUT_10 Matnr high-pass filter alpha LUT node 10
+// //Bit 15: 8, reg_MATNR_AlphaHP_LUT_9 Matnr high-pass filter alpha LUT node 9
+// //Bit 7: 0, reg_MATNR_AlphaHP_LUT_8 Matnr high-pass filter alpha LUT node 8
+// `define NR2_MATNR_ALPHAHP_LUT3 8'h76
+// //Bit 31:24, reg_MATNR_AlphaHP_LUT_15 Matnr high-pass filter alpha LUT node 15
+// //Bit 23:16, reg_MATNR_AlphaHP_LUT_14 Matnr high-pass filter alpha LUT node 14
+// //Bit 15: 8, reg_MATNR_AlphaHP_LUT_13 Matnr high-pass filter alpha LUT node 13
+// //Bit 7: 0, reg_MATNR_AlphaHP_LUT_12 Matnr high-pass filter alpha LUT node 12
+//
+// `define NR2_MATNR_MTNB_BRT 8'h77
+// //Bit 31:28, reg_MATNR_mtnb_BRT_limt_hi Motion adjustment based on Brightness high side Limit. (X16 to u8 scale)
+// //Bit 27:24, reg_MATNR_mtnb_BRT_slop_hi Motion adjustment based on Brightness high side slope. Normalized to 16 as 1
+// //Bit 23:16, reg_MATNR_mtnb_BRT_thrd_hi Motion adjustment based on Brightness high threshold.(u8 scale)
+// //Bit 15:12, reg_MATNR_mtnb_BRT_limt_lo Motion adjustment based on Brightness low side Limit. (X16 to u8 scale)
+// //Bit 11: 8, reg_MATNR_mtnb_BRT_slop_lo Motion adjustment based on Brightness low side slope. Normalized to 16 as 1
+// //Bit 7: 0, reg_MATNR_mtnb_BRT_thrd_lo Motion adjustment based on Brightness low threshold.(u8 scale)
+// 0x51 - 0x69 | 0x4e | 0x6a - 0x77
+//
+// Reading file: vpu_nr2_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//========== nr2_snr_regs register begin ==========//
+#define NR2_SNR_SAD_CFG ((0x1751 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12 reg_matnr_snr_sad_cenrpl // unsigned , default = 1
+//Bit 11: 8 reg_matnr_snr_sad_coring // unsigned , default = 3
+//Bit 7 reserved
+//Bit 6: 5 reg_matnr_snr_sad_winmod // unsigned , default = 1 0: 1x1; 1: [1 1 1] 2: [1 2 1]; 3: [1 2 2 2 1];
+//Bit 4: 0 sad_coef_num // unsigned , default = 1 0: 1x1; 1: [1 1 1] 2: [1 2 1]; 3: [1 2 2 2 1];
+#define NR2_MATNR_SNR_OS ((0x1752 << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7: 4 reg_matnr_snr_cos // unsigned , default = 8
+//Bit 3: 0 reg_matnr_snr_yos // unsigned , default = 13
+#define NR2_MATNR_SNR_NRM_CFG ((0x1753 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_matnr_snr_nrm_ofst // signed , default = 64
+//Bit 15: 8 reg_matnr_snr_nrm_max // unsigned , default = 255
+//Bit 7: 0 reg_matnr_snr_nrm_min // unsigned , default = 0
+#define NR2_MATNR_SNR_NRM_GAIN ((0x1754 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_matnr_snr_nrm_cgain // unsigned , default = 0 norm 32
+//Bit 7: 0 reg_matnr_snr_nrm_ygain // unsigned , default = 32 norm 32
+#define NR2_MATNR_SNR_LPF_CFG ((0x1755 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_matnr_snrlpf_sadmaxth // unsigned , default = 12
+//Bit 15:14 reserved
+//Bit 13:11 reg_matnr_snrlpf_cmode // unsigned , default = 2 0: gradient LPF [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8; 3: gradient LPF [5 5 4 3]/16;
+//Bit 10: 8 reg_matnr_snrlpf_ymode // unsigned , default = 2 0: gradient LPF [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8; 3: gradient LPF [5 5 4 3]/16;
+//Bit 7: 4 reg_matnr_snrlpf_sadmin3th // unsigned , default = 6 X8
+//Bit 3: 0 reg_matnr_snrlpf_sadmin2th // unsigned , default = 4 X8
+#define NR2_MATNR_SNR_USF_GAIN ((0x1756 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_matnr_snr_usf_cgain // unsigned , default = 0 norm 64
+//Bit 7: 0 reg_matnr_snr_usf_ygain // unsigned , default = 0 norm 64
+#define NR2_MATNR_SNR_EDGE2B ((0x1757 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_matnr_snr_edge2beta_ofst // unsigned , default = 128
+//Bit 7: 0 reg_matnr_snr_edge2beta_gain // unsigned , default = 16
+#define NR2_MATNR_BETA_EGAIN ((0x1758 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_matnr_cbeta_egain // unsigned , default = 32 normalized to 32
+//Bit 7: 0 reg_matnr_ybeta_egain // unsigned , default = 32 normalized to 32
+#define NR2_MATNR_BETA_BRT ((0x1759 << 2) + 0xff000000)
+//Bit 31:28 reg_matnr_beta_brt_limt_hi // unsigned , default = 0
+//Bit 27:24 reg_matnr_beta_brt_slop_hi // unsigned , default = 0
+//Bit 23:16 reg_matnr_beta_brt_thrd_hi // unsigned , default = 160
+//Bit 15:12 reg_matnr_beta_brt_limt_lo // unsigned , default = 6
+//Bit 11: 8 reg_matnr_beta_brt_slop_lo // unsigned , default = 6
+//Bit 7: 0 reg_matnr_beta_brt_thrd_lo // unsigned , default = 100
+#define NR2_MATNR_XBETA_CFG ((0x175a << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:18 reg_matnr_cbeta_use_mode // unsigned , default = 0 0: beta_motion; 1: beta_edge; 2: min(beta_mot,beta_edge); 3: (beta_mot + beta_edge)/2
+//Bit 17:16 reg_matnr_ybeta_use_mode // unsigned , default = 0 0: beta_motion; 1: beta_edge; 2: min(beta_mot,beta_edge); 3: (beta_mot + beta_edge)/2;
+//Bit 15: 8 reg_matnr_cbeta_ofst // unsigned , default = 0
+//Bit 7: 0 reg_matnr_ybeta_ofst // unsigned , default = 0
+#define NR2_MATNR_YBETA_SCL ((0x175b << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_ybeta_scale_min // unsigned , default = 60
+//Bit 23:16 reg_matnr_ybeta_scale_max // unsigned , default = 255
+//Bit 15: 8 reg_matnr_ybeta_scale_gain // unsigned , default = 32 normalized 32 to 1.0
+//Bit 7: 0 reg_matnr_ybeta_scale_ofst // signed , default = 0
+#define NR2_MATNR_CBETA_SCL ((0x175c << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_cbeta_scale_min // unsigned , default = 0
+//Bit 23:16 reg_matnr_cbeta_scale_max // unsigned , default = 255
+//Bit 15: 8 reg_matnr_cbeta_scale_gain // unsigned , default = 32 normalized 32 to 1.0
+//Bit 7: 0 reg_matnr_cbeta_scale_ofst // signed , default = 0
+#define NR2_SNR_MASK ((0x175d << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20: 0 sad_msk // unsigned , default = 0x0f9f3e
+#define NR2_SAD2NORM_LUT0 ((0x175e << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_sad2norm_lut3 // unsigned , default = 114
+//Bit 23:16 reg_matnr_sad2norm_lut2 // unsigned , default = 146
+//Bit 15: 8 reg_matnr_sad2norm_lut1 // unsigned , default = 171
+//Bit 7: 0 reg_matnr_sad2norm_lut0 // unsigned , default = 205
+#define NR2_SAD2NORM_LUT1 ((0x175f << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_sad2norm_lut7 // unsigned , default = 28
+//Bit 23:16 reg_matnr_sad2norm_lut6 // unsigned , default = 35
+//Bit 15: 8 reg_matnr_sad2norm_lut5 // unsigned , default = 49
+//Bit 7: 0 reg_matnr_sad2norm_lut4 // unsigned , default = 79
+#define NR2_SAD2NORM_LUT2 ((0x1760 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_sad2norm_lut11 // unsigned , default = 15
+//Bit 23:16 reg_matnr_sad2norm_lut10 // unsigned , default = 17
+//Bit 15: 8 reg_matnr_sad2norm_lut9 // unsigned , default = 19
+//Bit 7: 0 reg_matnr_sad2norm_lut8 // unsigned , default = 23
+#define NR2_SAD2NORM_LUT3 ((0x1761 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_sad2norm_lut15 // unsigned , default = 8
+//Bit 23:16 reg_matnr_sad2norm_lut14 // unsigned , default = 9
+//Bit 15: 8 reg_matnr_sad2norm_lut13 // unsigned , default = 10
+//Bit 7: 0 reg_matnr_sad2norm_lut12 // unsigned , default = 12
+#define NR2_EDGE2BETA_LUT0 ((0x1762 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_edge2beta_lut3 // unsigned , default = 128
+//Bit 23:16 reg_matnr_edge2beta_lut2 // unsigned , default = 160
+//Bit 15: 8 reg_matnr_edge2beta_lut1 // unsigned , default = 224
+//Bit 7: 0 reg_matnr_edge2beta_lut0 // unsigned , default = 255
+#define NR2_EDGE2BETA_LUT1 ((0x1763 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_edge2beta_lut7 // unsigned , default = 4
+//Bit 23:16 reg_matnr_edge2beta_lut6 // unsigned , default = 16
+//Bit 15: 8 reg_matnr_edge2beta_lut5 // unsigned , default = 32
+//Bit 7: 0 reg_matnr_edge2beta_lut4 // unsigned , default = 80
+#define NR2_EDGE2BETA_LUT2 ((0x1764 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_edge2beta_lut11 // unsigned , default = 0
+//Bit 23:16 reg_matnr_edge2beta_lut10 // unsigned , default = 0
+//Bit 15: 8 reg_matnr_edge2beta_lut9 // unsigned , default = 0
+//Bit 7: 0 reg_matnr_edge2beta_lut8 // unsigned , default = 2
+#define NR2_EDGE2BETA_LUT3 ((0x1765 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_edge2beta_lut15 // unsigned , default = 0
+//Bit 23:16 reg_matnr_edge2beta_lut14 // unsigned , default = 0
+//Bit 15: 8 reg_matnr_edge2beta_lut13 // unsigned , default = 0
+//Bit 7: 0 reg_matnr_edge2beta_lut12 // unsigned , default = 0
+#define NR2_MOTION2BETA_LUT0 ((0x1766 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_mot2beta_lut3 // unsigned , default = 32
+//Bit 23:16 reg_matnr_mot2beta_lut2 // unsigned , default = 16
+//Bit 15: 8 reg_matnr_mot2beta_lut1 // unsigned , default = 4
+//Bit 7: 0 reg_matnr_mot2beta_lut0 // unsigned , default = 0
+#define NR2_MOTION2BETA_LUT1 ((0x1767 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_mot2beta_lut7 // unsigned , default = 196
+//Bit 23:16 reg_matnr_mot2beta_lut6 // unsigned , default = 128
+//Bit 15: 8 reg_matnr_mot2beta_lut5 // unsigned , default = 64
+//Bit 7: 0 reg_matnr_mot2beta_lut4 // unsigned , default = 48
+#define NR2_MOTION2BETA_LUT2 ((0x1768 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_mot2beta_lut11 // unsigned , default = 255
+//Bit 23:16 reg_matnr_mot2beta_lut10 // unsigned , default = 255
+//Bit 15: 8 reg_matnr_mot2beta_lut9 // unsigned , default = 240
+//Bit 7: 0 reg_matnr_mot2beta_lut8 // unsigned , default = 224
+#define NR2_MOTION2BETA_LUT3 ((0x1769 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_mot2beta_lut15 // unsigned , default = 255
+//Bit 23:16 reg_matnr_mot2beta_lut14 // unsigned , default = 255
+//Bit 15: 8 reg_matnr_mot2beta_lut13 // unsigned , default = 255
+//Bit 7: 0 reg_matnr_mot2beta_lut12 // unsigned , default = 255
+//========== nr2_snr_regs register end ==========//
+//========== nr2_tnr_regs register begin ==========//
+#define NR2_IIR_CTRL ((0x174e << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15:14 reg_lp_iir_8bit_mode // unsigned , default = 0 10bits; 1: 9bits; 2: 8bits 3: 7bits
+//Bit 13:12 reg_hp_iir_mute_mode // unsigned , default = 0
+//Bit 11: 8 reg_hp_iir_mute_thrd // unsigned , default = 0
+//Bit 7: 6 reg_hp_iir_8bit_mode // unsigned , default = 0
+//Bit 5: 4 reg_lp_iir_mute_mode // unsigned , default = 0
+//Bit 3: 0 reg_lp_iir_mute_thrd // unsigned , default = 0
+#define NR2_MATNR_MTN_CRTL ((0x176a << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:18 reg_matnr_vmtn_use_mode // unsigned , default = 0 0- Vmot, 1- Ymot/2 + (Umot+Vmot)/4; 2- Ymot/2 + max(Umot,Vmot)/2; 3- max(Ymot,Umot, Vmot)
+//Bit 17:16 reg_matnr_umtn_use_mode // unsigned , default = 0 0- Umot, 1- Ymot/2 + (Umot+Vmot)/4; 2- Ymot/2 + max(Umot,Vmot)/2; 3- max(Ymot,Umot, Vmot)
+//Bit 15:14 reg_matnr_ymtn_use_mode // unsigned , default = 0 0- Ymot, 1- Ymot/2 + (Umot+Vmot)/4; 2- Ymot/2 + max(Umot,Vmot)/2; 3- max(Ymot,Umot, Vmot)
+//Bit 13:12 reg_matnr_mtn_txt_mode // unsigned , default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_matnr_mtn_cor_mode // unsigned , default = 1 changes)
+//Bit 7: 4 reg_matnr_mtn_hpf_mode // unsigned , default = 8 extend to u4 for nr4, 0- 1x1; 1: 1x3; 2: 1x5; 3: 3x3; 4: 3o3; 5: 3x5, 6:3x3 SAD, 7: 5x3 SAD, 8-15: drt adaptive
+//Bit 3 reserved
+//Bit 2: 0 reg_matnr_mtn_lpf_mode // unsigned , default = 6 0- 1x1; 1: 1x3; 2: 1x5; 3: 3x3; 4: 3o3; 5: 3x5, 6,7: drt adaptive
+#define NR2_MATNR_MTN_CRTL2 ((0x176b << 2) + 0xff000000)
+//Bit 31:19 reserved
+//Bit 18:16 reg_matnr_iir_bs_ymode // unsigned , default = 6 LPF~~ 0- 1x1; 1: 1x3; 2: 1x5; 3: 3x3; 4: 3o3; 5: 3x5; 6/7: 0
+//Bit 15: 8 reg_matnr_mtnb_alplp_cgain // unsigned , default = 64 to 32
+//Bit 7: 0 reg_matnr_mtnb_alplp_ygain // unsigned , default = 64 to 32
+#define NR2_MATNR_MTN_COR ((0x176c << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15:12 reg_matnr_mtn_cor_cofst // unsigned , default = 3 Offset for Chroma Motion.
+//Bit 11: 8 reg_matnr_mtn_cor_cgain // unsigned , default = 3 to texture based coring for Chroma Motion. Normalized to 16 as 1
+//Bit 7: 4 reg_matnr_mtn_cor_yofst // unsigned , default = 3 Offset for Luma Motion.
+//Bit 3: 0 reg_matnr_mtn_cor_ygain // unsigned , default = 3 to texture based coring for Luma Motion. Normalized to 16 as 1
+#define NR2_MATNR_MTN_GAIN ((0x176d << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_mtn_hp_cgain // unsigned , default = 64 to MotHPF_yuv[k] Chrm channel for motion calculation, normalized to 64 as 1
+//Bit 23:16 reg_matnr_mtn_hp_ygain // unsigned , default = 64 to MotHPF_yuv[k] Luma channel for motion calculation, normalized to 64 as 1
+//Bit 15: 8 reg_matnr_mtn_lp_cgain // unsigned , default = 64 to MotLPF_yuv[k] Chrm channel for motion calculation, normalized to 32 as 1
+//Bit 7: 0 reg_matnr_mtn_lp_ygain // unsigned , default = 64 to MotLPF_yuv[k] Luma channel for motion calculation, normalized to 32 as 1
+#define NR2_MATNR_DEGHOST ((0x176e << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_matnr_deghost_mode // unsigned , default = 0 0:old_deghost; 1:soft_denoise & strong_deghost; 2:strong_denoise & soft_deghost; 3:strong_denoise & strong_deghost
+//Bit 27:25 reserved
+//Bit 24:20 reg_matnr_deghost_ygain // unsigned , default = 4
+//Bit 19:17 reserved
+//Bit 16:12 reg_matnr_deghost_cgain // unsigned , default = 4
+//Bit 11: 9 reserved
+//Bit 8 reg_matnr_deghost_en // unsigned , default = 1 0: disable; 1: enable Enable signal for DeGhost function:0: disable; 1: enable
+//Bit 7: 4 reg_matnr_deghost_cos // unsigned , default = 3 DeGhost Overshoot margin for UV channel, (X2 to u10 scale)
+//Bit 3: 0 reg_matnr_deghost_yos // unsigned , default = 3 DeGhost Overshoot margin for Luma channel, (X2 to u10 scale)
+#define NR2_MATNR_ALPHALP_LUT0 ((0x176f << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphalp_lut3 // unsigned , default = 64 low-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphalp_lut2 // unsigned , default = 128 low-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphalp_lut1 // unsigned , default = 128 low-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphalp_lut0 // unsigned , default = 128 low-pass filter alpha LUT
+#define NR2_MATNR_ALPHALP_LUT1 ((0x1770 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphalp_lut7 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphalp_lut6 // unsigned , default = 128 low-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphalp_lut5 // unsigned , default = 80 low-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphalp_lut4 // unsigned , default = 64 low-pass filter alpha LUT
+#define NR2_MATNR_ALPHALP_LUT2 ((0x1771 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphalp_lut11 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphalp_lut10 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphalp_lut9 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphalp_lut8 // unsigned , default = 255 low-pass filter alpha LUT
+#define NR2_MATNR_ALPHALP_LUT3 ((0x1772 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphalp_lut15 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphalp_lut14 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphalp_lut13 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphalp_lut12 // unsigned , default = 255 low-pass filter alpha LUT
+#define NR2_MATNR_ALPHAHP_LUT0 ((0x1773 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphahp_lut3 // unsigned , default = 64 high-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphahp_lut2 // unsigned , default = 128 high-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphahp_lut1 // unsigned , default = 128 high-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphahp_lut0 // unsigned , default = 128 high-pass filter alpha LUT
+#define NR2_MATNR_ALPHAHP_LUT1 ((0x1774 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphahp_lut7 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphahp_lut6 // unsigned , default = 128 high-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphahp_lut5 // unsigned , default = 80 high-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphahp_lut4 // unsigned , default = 64 high-pass filter alpha LUT
+#define NR2_MATNR_ALPHAHP_LUT2 ((0x1775 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphahp_lut11 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphahp_lut10 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphahp_lut9 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphahp_lut8 // unsigned , default = 255 high-pass filter alpha LUT
+#define NR2_MATNR_ALPHAHP_LUT3 ((0x1776 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphahp_lut15 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphahp_lut14 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphahp_lut13 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphahp_lut12 // unsigned , default = 255 high-pass filter alpha LUT
+#define NR2_MATNR_MTNB_BRT ((0x1777 << 2) + 0xff000000)
+//Bit 31:28 reg_matnr_mtnb_brt_limt_hi // unsigned , default = 0
+//Bit 27:24 reg_matnr_mtnb_brt_slop_hi // unsigned , default = 0
+//Bit 23:16 reg_matnr_mtnb_brt_thrd_hi // unsigned , default = 160
+//Bit 15:12 reg_matnr_mtnb_brt_limt_lo // unsigned , default = 6
+//Bit 11: 8 reg_matnr_mtnb_brt_slop_lo // unsigned , default = 6
+//Bit 7: 0 reg_matnr_mtnb_brt_thrd_lo // unsigned , default = 100
+//========== nr2_tnr_regs register end ==========//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_nr2_regs.h
+//
+//
+// Reading file: nr2_cue_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define NR2_CUE_MODE ((0x1778 << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19 reg_cue2_isabv_org_invert1 // unsigned , default = 0
+//Bit 18 reg_cue2_valid_condition // unsigned , default = 1
+//Bit 17:16 reg_cue2_orgline_flt_sel // unsigned , default = 1
+//Bit 15:12 reg_cue2_orgline_flt_alph // unsigned , default = 4
+//Bit 11 reg_cue2_isabv_org_invert // unsigned , default = 0
+//Bit 10 reg_cue2_iscur_org_invert // unsigned , default = 0
+//Bit 9 reg_cue_enable_r // unsigned , default = 1 right half frame enable
+//Bit 8 reg_cue_enable_l // unsigned , default = 1 left half frame enable
+//Bit 7 reserved
+//Bit 6: 4 reg_cue_con_rplc_mode // unsigned , default = 7 pixel chroma replace mode;
+//Bit 3: 0 reg_cue_chrm_flt_mode // unsigned , default = 5 improvement filter mode,
+#define NR2_CUE_CON_MOT_TH ((0x1779 << 2) + 0xff000000)
+//Bit 31:24 reg_cue_con_cmot_thrd2 // unsigned , default = 20 Detection threshold of up/down two rows, Chroma channel in Chroma Up-sampling Error (CUE) Detection (tighter).
+//Bit 23:16 reg_cue_con_ymot_thrd2 // unsigned , default = 20 Detection threshold of up/mid/down three rows, Luma channel in Chroma Up-sampling Error (CUE) Detection (tighter).
+//Bit 15: 8 reg_cue_con_cmot_thrd // unsigned , default = 20 Detection threshold of up/down two rows, Chroma channel in Chroma Up-sampling Error (CUE) Detection.
+//Bit 7: 0 reg_cue_con_ymot_thrd // unsigned , default = 20 Detection threshold of up/mid/down three rows, Luma channel in Chroma Up-sampling Error (CUE) Detection.
+#define NR2_CUE_CON_DIF0 ((0x177a << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_cue_con_difp1_thrd // unsigned , default = 20 field Intra-Field top/below line chroma difference threshold,
+//Bit 7: 0 reg_cue_con_difcur_thrd // unsigned , default = 0 Field/Frame Intra-Field up/down line chroma difference threshold,
+#define NR2_CUE_CON_DIF1 ((0x177b << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:16 reg_cue_con_rate0 // unsigned , default = 8 Krate to decide CUE by relationship between CUE_diflG and CUE_difEG
+//Bit 15: 8 reg_cue_con_difeg_thrd // unsigned , default = 0 to the difference between current Field/Frame middle line to down line color channel(CUE_difEG).
+//Bit 7: 0 reg_cue_con_diflg_thrd // unsigned , default = 100 to the difference between P1 field top line to current Field/Frame down line color channel (CUE_diflG).
+#define NR2_CUE_CON_DIF2 ((0x177c << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:16 reg_cue_con_rate1 // unsigned , default = 8 Krate to decide CUE by relationship between CUE_difnC and CUE_difEC
+//Bit 15: 8 reg_cue_con_difec_thrd // unsigned , default = 0 to the difference between current Field/Frame middle line to up line color channel(CUE_difEC).
+//Bit 7: 0 reg_cue_con_difnc_thrd // unsigned , default = 100 to the difference between P1 field bot line to current Field/Frame up line color channel (CUE_difnC).
+#define NR2_CUE_CON_DIF3 ((0x177d << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:16 reg_cue_con_rate2 // unsigned , default = 8 Krate to decide CUE by relationship between CUE_difP1 and CUE_difEP1
+//Bit 15: 8 reg_cue_con_difep1_thrd // unsigned , default = 10 top/below line to current field/frame middle line chroma difference (CUE_difEP1) threshold.
+//Bit 7: 0 reg_cue_con_difp1_thrd2 // unsigned , default = 10 field Intra-Field top/below line chroma difference threshold (tighter),
+#define NR2_CUE_PRG_DIF ((0x177e << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20 reg_cue_prg_enable // unsigned , default = 0 bit for progressive video CUE detection.If interlace input video,
+//Bit 19:16 reg_cue_prg_rate // unsigned , default = 4 Krate to decide CUE by relationship between CUE_difCur and (CUE_difEC+CUE_difEG)
+//Bit 15: 8 reg_cue_prg_difceg_thrd // unsigned , default = 40 Frame Intra-Field up-mid and mid-down line chroma difference threshold for progressive video CUE detection,
+//Bit 7: 0 reg_cue_prg_difcur_thrd // unsigned , default = 30 Frame Intra-Field up/down line chroma difference threshold,
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: nr2_cue_regs.h
+//
+#define NR2_CONV_MODE ((0x177f << 2) + 0xff000000)
+//Bit 3:2, Conv_c444_mode The format convert mode about 422 to 444 when data read out line buffer
+//Bit 1:0, Conv_c422_mode the format convert mode about 444 to 422 when data write to line buffer
+//// NR2 REG DEFINE END ////
+//// DET 3D REG DEFINE BEGIN ////
+//// 8'h34~8'h3f | 8'h80~8'h8f | 0x9a-0x9b
+//
+// Reading file: vpu_det3d_regs.h
+//
+//// DET 3D REG DEFINE BEGIN ////
+//// 8'h34~8'h3f
+//// DET 3D REG DEFINE END ////
+#define DET3D_MOTN_CFG ((0x1734 << 2) + 0xff000000)
+//Bit 16, reg_det3d_intr_en Det3d interrupt enable
+//Bit 9:8, reg_Det3D_Motion_Mode U2 Different mode for Motion Calculation of Luma and Chroma:
+// 0: MotY, 1: (2*MotY + (MotU + MotV))/4; 2: Max(MotY, MotU,MotV); 3:Max(MotY, (MotU+MotV)/2)
+//Bit 7:4, reg_Det3D_Motion_Core_Rate U4 K Rate to Edge (HV) details for coring of Motion Calculations, normalized to 32
+//Bit 3:0, reg_Det3D_Motion_Core_Thrd U4 2X: static coring value for Motion Detection.
+#define DET3D_CB_CFG ((0x1735 << 2) + 0xff000000)
+//Bit 7:4, reg_Det3D_ChessBd_HV_ofst U4, Noise immune offset for Horizotnal or vertical combing detection.
+//Bit 3:0, reg_Det3D_ChessBd_NHV_ofst U4, Noise immune offset for NON-Horizotnal or vertical combing detection.
+#define DET3D_SPLT_CFG ((0x1736 << 2) + 0xff000000)
+//Bit 7:4, reg_Det3D_SplitValid_ratio U4, Ratio between max_value and the avg_value of the edge mapping for split line valid detection.
+// The smaller of this value, the easier of the split line detected.
+//Bit 3:0, reg_Det3D_AvgIdx_ratio U4, Ratio to the avg_value of the edge mapping for split line position estimation.
+// The smaller of this value, the more samples will be added to the estimation.
+#define DET3D_HV_MUTE ((0x1737 << 2) + 0xff000000)
+//Bit 23:20, reg_Det3D_Edge_Ver_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Top and Bottom border part.
+//Bit 19:16, reg_Det3D_Edge_Hor_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Left and right border part.
+//Bit 15:12, reg_Det3D_ChessBd_Ver_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part
+//Bit 11:8, reg_Det3D_ChessBd_Hor_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part
+//Bit 7:4, reg_Det3D_STA8X8_Ver_Mute U4 1X: Vertical pixels to be mute from 8x8 statistics calculation in each block.
+//Bit 3:0, reg_Det3D_STA8X8_Hor_Mute U4 1X: Horizontal pixels to be mute from 8x8 statistics calculation in each block.
+#define DET3D_MAT_STA_P1M1 ((0x1738 << 2) + 0xff000000)
+//Bit 31:24, reg_Det3D_STA8X8_P1_K0_R8 U8 SAD to SAI ratio to decide P1, normalized to 256 (0.8)
+//Bit 23:16, reg_Det3D_STA8X8_P1_K1_R7 U8 SAD to ENG ratio to decide P1, normalized to 128 (0.5)
+//Bit 15:8, reg_Det3D_STA8X8_M1_K0_R6 U8 SAD to SAI ratio to decide M1, normalized to 64 (1.1)
+//Bit 7:0, reg_Det3D_STA8X8_M1_K1_R6 U8 SAD to ENG ratio to decide M1, normalized to 64 (0.8)
+#define DET3D_MAT_STA_P1TH ((0x1739 << 2) + 0xff000000)
+//Bit 23:16, reg_Det3D_STAYUV_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (100)
+//Bit 15:8, reg_Det3D_STAEDG_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (80)
+//Bit 7:0, reg_Det3D_STAMOT_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (48)
+#define DET3D_MAT_STA_M1TH ((0x173a << 2) + 0xff000000)
+//Bit 23:16, reg_Det3D_STAYUV_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (100)
+//Bit 15:8, reg_Det3D_STAEDG_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (80)
+//Bit 7:0, reg_Det3D_STAMOT_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (64)
+#define DET3D_MAT_STA_RSFT ((0x173b << 2) + 0xff000000)
+//Bit 5:4, reg_Det3D_STAYUV_RSHFT U2 YUV statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
+// 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
+//Bit 3:2, reg_Det3D_STAEDG_RSHFT U2 Horizontal and Vertical Edge Statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
+// 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
+//Bit 1:0, reg_Det3D_STAMOT_RSHFT U2 Motion SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
+// 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
+#define DET3D_MAT_SYMTC_TH ((0x173c << 2) + 0xff000000)
+//Bit 31:24, reg_Det3D_STALUM_symtc_Th U8 threshold to decide if the Luma statistics is TB or LR symmetric.
+//Bit 23:16, reg_Det3D_STACHR_symtc_Th U8 threshold to decide if the Chroma (UV) statistics is TB or LR symmetric.
+//Bit 15:8, reg_Det3D_STAEDG_symtc_Th U8 threshold to decide if the Horizontal and Vertical Edge statistics is TB or LR symmetric.
+//Bit 7:0, reg_Det3D_STAMOT_symtc_Th U8 threshold to decide if the Motion statistics is TB or LR symmetric.
+#define DET3D_RO_DET_CB_HOR ((0x173d << 2) + 0xff000000)
+//Bit 31:16, RO_Det3D_ChessBd_NHor_value U16 X64: number of Pixels of Horizontally Surely NOT matching Chessboard pattern.
+//Bit 15:0, RO_Det3D_ChessBd_Hor_value U16 X64: number of Pixels of Horizontally Surely matching Chessboard pattern.
+#define DET3D_RO_DET_CB_VER ((0x173e << 2) + 0xff000000)
+//Bit 31:16, RO_Det3D_ChessBd_NVer_value U16 X64: number of Pixels of Vertically Surely NOT matching Chessboard pattern.
+//Bit 15:0, RO_Det3D_ChessBd_Ver_value U16 X64: number of Pixels of Vertically Surely matching Chessboard pattern.
+#define DET3D_RO_SPLT_HT ((0x173f << 2) + 0xff000000)
+//Bit 24, RO_Det3D_Split_HT_valid U1 horizontal LR split border detected valid signal for top half picture
+//Bit 20:16, RO_Det3D_Split_HT_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+//Bit 9:0, RO_Det3D_Split_HT_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+//// DET 3D REG DEFINE BEGIN ////
+//// 8'h80~8'h8f
+#define DET3D_RO_SPLT_HB ((0x1780 << 2) + 0xff000000)
+//Bit 24, RO_Det3D_Split_HB_valid U1 horizontal LR split border detected valid signal for top half picture
+//Bit 20:16, RO_Det3D_Split_HB_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+//Bit 9: 0, RO_Det3D_Split_HB_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+#define DET3D_RO_SPLT_VL ((0x1781 << 2) + 0xff000000)
+//Bit 24, RO_Det3D_Split_VL_valid U1 horizontal LR split border detected valid signal for top half picture
+//Bit 20:16, RO_Det3D_Split_VL_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+//Bit 9: 0, RO_Det3D_Split_VL_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+#define DET3D_RO_SPLT_VR ((0x1782 << 2) + 0xff000000)
+//Bit 24 , RO_Det3D_Split_VR_valid U1 horizontal LR split border detected valid signal for top half picture
+//Bit 20:16, RO_Det3D_Split_VR_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+//Bit 9: 0, RO_Det3D_Split_VR_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+#define DET3D_RO_MAT_LUMA_LR ((0x1783 << 2) + 0xff000000)
+//Bit 15:0, RO_Luma_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically),
+// it can be -1/0/1:-1: most likely not LR symmetric 0: not sure 1: most likely LR symmetric
+//Bit 7:0, RO_Luma_LR_symtc U1*8 Luma statistics left right pure symmetric for each band (8bands vertically),
+// it can be 0/1: 0: not sure 1: most likely LR is pure symmetric
+//Bit 4:0, RO_Luma_LR_sum S5 Total score of 8x8 Luma statistics for LR like decision,
+// the larger this score, the more confidence that this is a LR 3D video. It is sum of RO_Luma_LR_score[0~7]
+#define DET3D_RO_MAT_LUMA_TB ((0x1784 << 2) + 0xff000000)
+//Bit 15:0, RO_Luma_TB_score S2*8 LUMA statistics Top/Bottom decision score for each band (8bands Horizontally),
+//Bit 7:0, RO_Luma_TB_symtc Luma statistics Top/Bottompure symmetric for each band (8bands Horizontally),
+//Bit 4:0, RO_Luma_TB_sum Total score of 8x8 Luma statistics for TB like decision,
+#define DET3D_RO_MAT_CHRU_LR ((0x1785 << 2) + 0xff000000)
+//Bit 15:0, RO_ChrU_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically),
+//Bit 7:0, RO_ChrU_LR_symtc CHRU statistics left right pure symmetric for each band (8bands vertically),
+//Bit 4:0, RO_ChrU_LR_sum Total score of 8x8 ChrU statistics for LR like decision,
+#define DET3D_RO_MAT_CHRU_TB ((0x1786 << 2) + 0xff000000)
+//Bit 15:0, RO_ChrU_TB_score S2*8 CHRU statistics Top/Bottom decision score for each band (8bands Horizontally)
+//Bit 7:0, RO_ChrU_TB_symtc CHRU statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+//Bit 4:0, RO_ChrU_TB_sum Total score of 8x8 ChrU statistics for TB like decision
+#define DET3D_RO_MAT_CHRV_LR ((0x1787 << 2) + 0xff000000)
+//Bit 15:0, RO_ChrV_LR_score S2*8 CHRUstatistics left right decision score for each band (8bands vertically)
+//Bit 7:0, RO_ChrV_LR_symtc CHRV statistics left right pure symmetric for each band (8bands vertically)
+//Bit 4:0, RO_ChrV_LR_sum Total score of 8x8 ChrV statistics for LR like decision
+#define DET3D_RO_MAT_CHRV_TB ((0x1788 << 2) + 0xff000000)
+//Bit 15:0, RO_ChrV_TB_score CHRV statistics Top/Bottom decision score for each band (8bands Horizontally)
+//Bit 7:0, RO_ChrV_TB_symtc CHRV statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+//Bit 4:0, RO_ChrV_TB_sum Total score of 8x8 ChrV statistics for TB like decision
+#define DET3D_RO_MAT_HEDG_LR ((0x1789 << 2) + 0xff000000)
+//Bit 15:0, RO_Hedg_LR_score Horizontal Edge statistics left right decision score for each band (8bands vertically)
+//Bit 7:0, RO_Hedg_LR_symtc Horizontal Edge statistics left right pure symmetric for each band (8bands vertically)
+//Bit 4:0, RO_Hedg_LR_sum Total score of 8x8 Hedg statistics for LR like decision
+#define DET3D_RO_MAT_HEDG_TB ((0x178a << 2) + 0xff000000)
+//Bit 15:0, RO_Hedg_TB_score Horizontal Edge statistics Top/Bottom decision score for each band (8bands Horizontally)
+//Bit 7:0, RO_Hedg_TB_symtc Horizontal Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+//Bit 4:0, RO_Hedg_TB_sum Total score of 8x8 Hedg statistics for TB like decision
+#define DET3D_RO_MAT_VEDG_LR ((0x178b << 2) + 0xff000000)
+//Bit 15:0, RO_Vedg_LR_score Vertical Edge statistics left right decision score for each band (8bands vertically)
+//Bit 7:0, RO_Vedg_LR_symtc Vertical Edge statistics left right pure symmetric for each band (8bands vertically)
+//Bit 4:0, RO_Vedg_LR_sum Total score of 8x8 Vedg statistics for LR like decision
+#define DET3D_RO_MAT_VEDG_TB ((0x178c << 2) + 0xff000000)
+//Bit 15:0, RO_Vedg_TB_score Vertical Edge statistics Top/Bottom decision score for each band (8bands Horizontally)
+//Bit 7:0, RO_Vedg_TB_symtc Vertical Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+//Bit 4:0, RO_Vedg_TB_sum Total score of 8x8 Vedg statistics for TB like decision
+#define DET3D_RO_MAT_MOTN_LR ((0x178d << 2) + 0xff000000)
+//Bit 15:0, RO_Motn_LR_score Motion statistics left right decision score for each band (8bands vertically)
+//Bit 7:0, RO_Motn_LR_symtc Motion statistics left right pure symmetric for each band (8bands vertically)
+//Bit 4:0, RO_Motn_LR_sum Total score of 8x8 Motion statistics for LR like decision
+#define DET3D_RO_MAT_MOTN_TB ((0x178e << 2) + 0xff000000)
+//Bit 15:0, RO_Motn_TB_score Motion statistics Top/Bottom decision score for each band (8bands Horizontally)
+//Bit 7:0, RO_Motn_TB_symtc Motion statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+//Bit 4:0, RO_Motn_TB_sum Total score of 8x8 Motion statistics for TB like decision
+#define DET3D_RO_FRM_MOTN ((0x178f << 2) + 0xff000000)
+//Bit 15:0, RO_Det3D_Frame_Motion U16 frame based motion value sum for still image decision in FW.
+/// mat ram read enter addr
+#define DET3D_RAMRD_ADDR_PORT ((0x179a << 2) + 0xff000000)
+#define DET3D_RAMRD_DATA_PORT ((0x179b << 2) + 0xff000000)
+//
+// Closing file: vpu_det3d_regs.h
+//
+// `define DET3D_RO_SPLT_HB 8'h80
+// //Bit 24, RO_Det3D_Split_HB_valid U1 horizontal LR split border detected valid signal for top half picture
+// //Bit 20:16, RO_Det3D_Split_HB_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+// //Bit 9: 0, RO_Det3D_Split_HB_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+// `define DET3D_RO_SPLT_VL 8'h81
+// //Bit 24, RO_Det3D_Split_VL_valid U1 horizontal LR split border detected valid signal for top half picture
+// //Bit 20:16, RO_Det3D_Split_VL_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+// //Bit 9: 0, RO_Det3D_Split_VL_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+// `define DET3D_RO_SPLT_VR 8'h82
+// //Bit 24 , RO_Det3D_Split_VR_valid U1 horizontal LR split border detected valid signal for top half picture
+// //Bit 20:16, RO_Det3D_Split_VR_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+// //Bit 9: 0, RO_Det3D_Split_VR_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+// `define DET3D_RO_MAT_LUMA_LR 8'h83
+// //Bit 15:0, RO_Luma_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically),
+// // it can be -1/0/1:-1: most likely not LR symmetric 0: not sure 1: most likely LR symmetric
+// //Bit 7:0, RO_Luma_LR_symtc U1*8 Luma statistics left right pure symmetric for each band (8bands vertically),
+// // it can be 0/1: 0: not sure 1: most likely LR is pure symmetric
+// //Bit 4:0, RO_Luma_LR_sum S5 Total score of 8x8 Luma statistics for LR like decision,
+// // the larger this score, the more confidence that this is a LR 3D video. It is sum of RO_Luma_LR_score[0~7]
+// `define DET3D_RO_MAT_LUMA_TB 8'h84
+// //Bit 15:0, RO_Luma_TB_score S2*8 LUMA statistics Top/Bottom decision score for each band (8bands Horizontally),
+// //Bit 7:0, RO_Luma_TB_symtc Luma statistics Top/Bottompure symmetric for each band (8bands Horizontally),
+// //Bit 4:0, RO_Luma_TB_sum Total score of 8x8 Luma statistics for TB like decision,
+// `define DET3D_RO_MAT_CHRU_LR 8'h85
+// //Bit 15:0, RO_ChrU_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically),
+// //Bit 7:0, RO_ChrU_LR_symtc CHRU statistics left right pure symmetric for each band (8bands vertically),
+// //Bit 4:0, RO_ChrU_LR_sum Total score of 8x8 ChrU statistics for LR like decision,
+// `define DET3D_RO_MAT_CHRU_TB 8'h86
+// //Bit 15:0, RO_ChrU_TB_score S2*8 CHRU statistics Top/Bottom decision score for each band (8bands Horizontally)
+// //Bit 7:0, RO_ChrU_TB_symtc CHRU statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+// //Bit 4:0, RO_ChrU_TB_sum Total score of 8x8 ChrU statistics for TB like decision
+// `define DET3D_RO_MAT_CHRV_LR 8'h87
+// //Bit 15:0, RO_ChrV_LR_score S2*8 CHRUstatistics left right decision score for each band (8bands vertically)
+// //Bit 7:0, RO_ChrV_LR_symtc CHRV statistics left right pure symmetric for each band (8bands vertically)
+// //Bit 4:0, RO_ChrV_LR_sum Total score of 8x8 ChrV statistics for LR like decision
+// `define DET3D_RO_MAT_CHRV_TB 8'h88
+// //Bit 15:0, RO_ChrV_TB_score CHRV statistics Top/Bottom decision score for each band (8bands Horizontally)
+// //Bit 7:0, RO_ChrV_TB_symtc CHRV statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+// //Bit 4:0, RO_ChrV_TB_sum Total score of 8x8 ChrV statistics for TB like decision
+// `define DET3D_RO_MAT_HEDG_LR 8'h89
+// //Bit 15:0, RO_Hedg_LR_score Horizontal Edge statistics left right decision score for each band (8bands vertically)
+// //Bit 7:0, RO_Hedg_LR_symtc Horizontal Edge statistics left right pure symmetric for each band (8bands vertically)
+// //Bit 4:0, RO_Hedg_LR_sum Total score of 8x8 Hedg statistics for LR like decision
+// `define DET3D_RO_MAT_HEDG_TB 8'h8a
+// //Bit 15:0, RO_Hedg_TB_score Horizontal Edge statistics Top/Bottom decision score for each band (8bands Horizontally)
+// //Bit 7:0, RO_Hedg_TB_symtc Horizontal Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+// //Bit 4:0, RO_Hedg_TB_sum Total score of 8x8 Hedg statistics for TB like decision
+// `define DET3D_RO_MAT_VEDG_LR 8'h8b
+// //Bit 15:0, RO_Vedg_LR_score Vertical Edge statistics left right decision score for each band (8bands vertically)
+// //Bit 7:0, RO_Vedg_LR_symtc Vertical Edge statistics left right pure symmetric for each band (8bands vertically)
+// //Bit 4:0, RO_Vedg_LR_sum Total score of 8x8 Vedg statistics for LR like decision
+// `define DET3D_RO_MAT_VEDG_TB 8'h8c
+// //Bit 15:0, RO_Vedg_TB_score Vertical Edge statistics Top/Bottom decision score for each band (8bands Horizontally)
+// //Bit 7:0, RO_Vedg_TB_symtc Vertical Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+// //Bit 4:0, RO_Vedg_TB_sum Total score of 8x8 Vedg statistics for TB like decision
+// `define DET3D_RO_MAT_MOTN_LR 8'h8d
+// //Bit 15:0, RO_Motn_LR_score Motion statistics left right decision score for each band (8bands vertically)
+// //Bit 7:0, RO_Motn_LR_symtc Motion statistics left right pure symmetric for each band (8bands vertically)
+// //Bit 4:0, RO_Motn_LR_sum Total score of 8x8 Motion statistics for LR like decision
+// `define DET3D_RO_MAT_MOTN_TB 8'h8e
+// //Bit 15:0, RO_Motn_TB_score Motion statistics Top/Bottom decision score for each band (8bands Horizontally)
+// //Bit 7:0, RO_Motn_TB_symtc Motion statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+// //Bit 4:0, RO_Motn_TB_sum Total score of 8x8 Motion statistics for TB like decision
+// `define DET3D_RO_FRM_MOTN 8'h8f
+// //Bit 15:0, RO_Det3D_Frame_Motion U16 frame based motion value sum for still image decision in FW.
+#define DI_EI_CTRL10 ((0x1793 << 2) + 0xff000000)
+//bit 31:28, reg_ei_caldrt_hstrrgchk_drtth
+//bit 27:24, reg_ei_caldrt_hstrrgchk_frcverthrd
+//bit 23:20, reg_ei_caldrt_hstrrgchk_mg
+//bit 19, reg_ei_caldrt_hstrrgchk_1sidnul
+//bit 18, reg_ei_caldrt_hstrrgchk_excpcnf
+//bit 17:16, reg_ei_caldrt_hstrrgchk_ws
+//bit 15, reg_ei_caldrt_hstrrgchk_en
+//bit 14:13, reg_ei_caldrt_hpncheck_mode
+//bit 12, reg_ei_caldrt_hpncheck_mute
+//bit 11:9, reg_ei_caldrt_hcnfcheck_mg2
+//bit 8:6, reg_ei_caldrt_hcnfcheck_mg1
+//bit 5:4, reg_ei_caldrt_hcnfcheck_mode
+//bit 3:0, reg_ei_caldrt_hcnfcheck_mg2
+#define DI_NR_1_CTRL0 ((0x1794 << 2) + 0xff000000)
+#define DI_NR_1_CTRL1 ((0x1795 << 2) + 0xff000000)
+#define DI_NR_1_CTRL2 ((0x1796 << 2) + 0xff000000)
+#define DI_NR_1_CTRL3 ((0x1797 << 2) + 0xff000000)
+#define DI_EI_XWIN0 ((0x1798 << 2) + 0xff000000)
+//bit 27:16, ei_xend0
+//bit 11:0, ei_xstart0
+#define DI_EI_XWIN1 ((0x1799 << 2) + 0xff000000)
+/// mat ram read enter addr
+// `define DET3D_RAMRD_ADDR_PORT 8'h9a
+// `define DET3D_RAMRD_DATA_PORT 8'h9b
+#define NR2_CFR_PARA_CFG0 ((0x179c << 2) + 0xff000000)
+//Bit 8, reg_CFR_CurDif_luma_mode Current Field Top/Bot line Luma difference calculation mode
+//Bit 7:6, reg_MACFR_frm_phase U2 This will be a field based phase register that need to be set by FW phase to phase:
+// this will be calculated based on dbdr_phase of the specific line of this frame.
+// u1: dbdr_phase=1, center line is DB in current line; dbdr_phase=2, center line is Dr in current line;
+//Bit 5:4, reg_CFR_CurDif_tran_mode U2 Current Field Top/Bot line Luma/Chroma transition level calculation mode,
+//Bit 3:2, reg_CFR_alpha_mode U2 Alpha selection mode for CFR block from curAlp and motAlp i.e. 0: motAlp; 1: (motAlp+curAlp)/2; 2: min(motAlp,curAlp); 3: max(motAlp,curAlp);
+//Bit 1:0, reg_CFR_Motion_Luma_mode U2 LumaMotion Calculation mode for MA-CFR. 0: top/bot Lumma motion; 1: middle Luma Motion 2: top/bot + middle motion; 3: max(top/tot motion, middle motion)
+#define NR2_CFR_PARA_CFG1 ((0x179d << 2) + 0xff000000)
+//Bit 23:16, reg_CFR_alpha_gain gain to map muxed curAlp and motAlp to alpha that will be used for final blending.
+//Bit 15: 8, reg_CFR_Motion_ofst Offset to Motion to calculate the motAlp, e,g:motAlp= reg_CFR_Motion_ofst- Motion;This register can be seen as the level of motion that we consider it at moving.
+//Bit 7: 0, reg_CFR_CurDif_gain gain to CurDif to map to alpha, normalized to 32;
+//// DET 3D REG DEFINE END ////
+#define DI_EI_CTRL11 ((0x179e << 2) + 0xff000000)
+//bit 30:29, reg_ei_amb_detect_mode
+//bit 28:24, reg_ei_amb_detect_winth
+//bit 23:21, reg_ei_amb_decide_rppth
+//bit 20:19, reg_ei_retime_lastmappncnfltchk_drtth
+//bit 18:16, reg_ei_retime_lastmappncnfltchk_mode
+//bit 15:14, reg_ei_retime_lastmapvertfrcchk_mode
+//bit 13:12, reg_ei_retime_lastvertfrcchk_mode
+//bit 11:8, reg_ei_retime_lastpnchk_drtth
+//bit 6, reg_ei_retime_lastpnchk_en
+//bit 5:4, reg_ei_retime_mode
+//bit 3, reg_ei_retime_last_en
+//bit 2, reg_ei_retime_ab_en
+//bit 1, reg_ei_caldrt_hstrvertfrcchk_en
+//bit 0, reg_ei_caldrt_hstrrgchk_mode
+#define DI_EI_CTRL12 ((0x179f << 2) + 0xff000000)
+//bit 31:28, reg_ei_drtdelay2_lmt
+//bit 27:26, reg_ei_drtdelay2_notver_lrwin
+//bit 25:24, reg_ei_drtdelay_mode
+//bit 23, reg_ei_drtdelay2_mode
+//bit 22:20, reg_ei_assign_xla_signm0th
+//bit 19, reg_ei_assign_pkbiasvert_en
+//bit 18, reg_ei_assign_xla_en
+//bit 17:16, reg_ei_assign_xla_mode
+//bit 15:12, reg_ei_assign_nlfilter_magin
+//bit 11:8, reg_ei_localsearch_maxrange
+//bit 7:4, reg_ei_xla_drtth
+//bit 3:0, reg_ei_flatmsad_thrd
+//`define DI_DIWR_CANVAS 8'ha0
+//`define DI_DIWR_URGENT 8'ha1
+//`define DI_NRWR_CANVAS 8'ha2
+//`define DI_NRWR_URGENT 8'ha7
+//`define DI_CONTWR_X 8'ha0
+//`define DI_CONTWR_Y 8'ha1
+//`define DI_CONTWR_CTRL 8'ha2
+//`define DI_CONTPRD_X 8'ha3
+//`define DI_CONTPRD_Y 8'ha4
+//`define DI_CONTP2RD_X 8'ha5
+//`define DI_CONTP2RD_Y 8'ha6
+#define DI_RO_PRE_FIELD_CNT0 ((0x17a3 << 2) + 0xff000000)
+#define DI_RO_PRE_FIELD_CNT1 ((0x17a4 << 2) + 0xff000000)
+#define DI_RO_POS_FRAME_CNT0 ((0x17a5 << 2) + 0xff000000)
+#define DI_RO_POS_FRAME_CNT1 ((0x17a6 << 2) + 0xff000000)
+//`define DI_CONTRD_CTRL 8'ha7
+#define DI_EI_CTRL13 ((0x17a8 << 2) + 0xff000000)
+//bit 27:24, reg_ei_int_drt2x_chrdrt_limit
+//bit 23:20, reg_ei_int_drt16x_core
+//bit 19:16, reg_ei_int_drtdelay2_notver_cancv
+//bit 15:8, reg_ei_int_drtdelay2_notver_sadth
+//bit 7:0, reg_ei_int_drtdelay2_vlddrt_sadth
+#define DI_MTN_1_CTRL6 ((0x17a9 << 2) + 0xff000000)
+//bit 31:24, mtn_m1b_extnd
+//bit 23:16, mtn_m1b_errod
+//bit 15: 8, mtn_core_ykinter
+//bit 7: 0, mtn_core_ckinter
+#define DI_MTN_1_CTRL7 ((0x17aa << 2) + 0xff000000)
+//bit 31:24, mtn_core_mxcmby
+//bit 23:16, mtn_core_mxcmbc
+//bit 15: 8, mtn_core_y
+//bit 7: 0, mtn_core_c
+#define DI_MTN_1_CTRL8 ((0x17ab << 2) + 0xff000000)
+//bit 31:24, mtn_fcore_ykinter
+//bit 23:16, mtn_fcore_ckinter
+//bit 15: 8, mtn_fcore_ykintra
+//bit 7: 0, mtn_fcore_ckintra
+#define DI_MTN_1_CTRL9 ((0x17ac << 2) + 0xff000000)
+//bit 31:24, mtn_fcore_2yrate
+//bit 23:16, mtn_fcore_2crate
+//bit 15: 8, mtn_fcore_y
+//bit 7: 0, mtn_fcore_c
+#define DI_MTN_1_CTRL10 ((0x17ad << 2) + 0xff000000)
+//bit 27:24, mtn_motfld0
+//bit 19:16, mtn_stlfld0
+//bit 11: 8, mtn_motfld1
+//bit 3: 0, mtn_stlfld1
+#define DI_MTN_1_CTRL11 ((0x17ae << 2) + 0xff000000)
+//bit 27:24, mtn_smotevn
+//bit 20:16, mtn_smotodd
+//bit 11: 8, mtn_sstlevn
+//bit 4: 0, mtn_sstlodd
+#define DI_MTN_1_CTRL12 ((0x17af << 2) + 0xff000000)
+//bit 31:24, mtn_mgain
+//bit 17:16, mtn_mmode
+//bit 15: 8, mtn_sthrd
+//bit 4: 0, mtn_sgain
+//`define DI_NRWR_X 8'hc0
+//`define DI_NRWR_Y 8'hc1
+//bit 31:30 nrwr_words_lim
+//bit 29 nrwr_rev_y
+//bit 28:16 nrwr_start_y
+//bit 15 nrwr_ext_en
+//bit 12:0 nrwr_end_y
+//`define DI_NRWR_CTRL 8'hc2
+//bit 31 pending_ddr_wrrsp_diwr
+//bit 30 nrwr_reg_swap
+//bit 29:26 nrwr_burst_lim
+//bit 25 nrwr_canvas_syncen
+//bit 24 nrwr_no_clk_gate
+//bit 23:22 nrwr_rgb_mode 0:422 to one canvas;1:4:4:4 to one canvas;
+ //2:Y to luma , CBCR to chroma canvas ,for nv12/21; 3 : reserved
+//bit 21:20 nrwr_hconv_mode
+//bit 19:18 nrwr_vconv_mode
+//bit 17 nrwr_swap_cbcr
+//bit 16 nrwr_urgent
+//bit 15:8 nrwr_canvas_index_chroma
+//bit 7:0 nrwr_canvas_index_luma
+//`define DI_MTNWR_X 8'hc3
+//`define DI_MTNWR_Y 8'hc4
+//`define DI_MTNWR_CTRL 8'hc5
+#define DI_RO_CRC_NRWR ((0x17c0 << 2) + 0xff000000)
+#define DI_RO_CRC_MTNWR ((0x17c1 << 2) + 0xff000000)
+#define DI_RO_CRC_DEINT ((0x17c2 << 2) + 0xff000000)
+#define DI_CRC_CHK0 ((0x17c3 << 2) + 0xff000000)
+#define DI_CRC_CHK1 ((0x17c4 << 2) + 0xff000000)
+//`define DI_DIWR_X 8'hc6
+//`define DI_DIWR_Y 8'hc7
+//bit 31:30 diwr_words_lim
+//bit 29 diwr_rev_y
+//bit 28:16 diwr_start_y
+//bit 15 diwr_ext_en
+//bit 12:0 diwr_end_y
+//`define DI_DIWR_CTRL 8'hc8
+//bit 31 pending_ddr_wrrsp_diwr
+//bit 30 diwr_reg_swap
+//bit 29:26 diwr_burst_lim
+//bit 25 diwr_canvas_syncen
+//bit 24 diwr_no_clk_gate
+//bit 23:22 diwr_rgb_mode 0:422 to one canvas;1:4:4:4 to one canvas;
+ //2:Y to luma , CBCR to chroma canvas ,for nv12/21; 3 : reserved
+//bit 21:20 diwr_hconv_mode
+//bit 19:18 diwr_vconv_mode
+//bit 17 diwr_swap_cbcr
+//bit 16 diwr_urgent
+//bit 15:8 diwr_canvas_index_chroma
+//bit 7:0 diwr_canvas_index_luma
+//`define DI_MTNCRD_X 8'hc9
+//`define DI_MTNCRD_Y 8'hca
+//`define DI_MTNPRD_X 8'hcb
+//`define DI_MTNPRD_Y 8'hcc
+//`define DI_MTNRD_CTRL 8'hcd
+#define DI_TOP_PRE_CTRL ((0x17c5 << 2) + 0xff000000)
+#define DI_TOP_POST_CTRL ((0x17c6 << 2) + 0xff000000)
+#define DI_PRE_GL_CTRL ((0x17c7 << 2) + 0xff000000)
+#define DI_PRE_GL_THD ((0x17c8 << 2) + 0xff000000)
+#define DI_POST_GL_CTRL ((0x17c9 << 2) + 0xff000000)
+#define DI_POST_GL_THD ((0x17ca << 2) + 0xff000000)
+#define DI_RO_PRE_DBG ((0x17cb << 2) + 0xff000000)
+#define DI_RO_POST_DBG ((0x17cc << 2) + 0xff000000)
+#define DI_TOP_CTRL ((0x17cd << 2) + 0xff000000)
+#define DI_AFBCD_GCLK0 ((0x17ce << 2) + 0xff000000)
+#define DI_AFBCD_GCLK1 ((0x17cf << 2) + 0xff000000)
+#define DI_RDMIF_DEPTH0 ((0x17d0 << 2) + 0xff000000)
+#define DI_RDMIF_DEPTH1 ((0x17d1 << 2) + 0xff000000)
+#define DI_RDMIF_DEPTH2 ((0x17d2 << 2) + 0xff000000)
+#define DI_TOP_CTRL1 ((0x17d3 << 2) + 0xff000000)
+#define DI_AFBCE0_HOLD_CTRL ((0x17d4 << 2) + 0xff000000)
+#define DI_AFBCE1_HOLD_CTRL ((0x17d5 << 2) + 0xff000000)
+// 0xe0 - 0xff
+//
+// Reading file: di_pd_grad_reg.h
+//
+#define DI_PD_GRAD_CTRL ((0x17e0 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11:4 reg_fd_min_grad_th // default 255 //u8, for cur/pre1 field. cur_min_grad_err > th, will be excluded of statistic
+//Bit 3 reg_fd_min_grad_th_adjust_en // default 1 //u1, reg_fd_min_grad_err_th adjustment enable/disable
+//Bit 2 reg_fd_err_grad_bf_flt_en // default 1 //u1, 1:comput err_grad_sum before horizontal filtering; 0: ...after...; default=1;
+//Bit 1 reg_fd_comb_field_sel // default 0 //u1, comb consists of 2 field; 0: cur-pre; 1:pre-pre2;
+//Bit 0 reg_fd_iscur_top_inver // default 0 //u1, current field is top flag invert; 0 no invert, 1, invert
+#define DI_PD_GRAD_TH_P ((0x17e1 << 2) + 0xff000000)
+//Bit 31:24 reg_fd_min_grad_th_p0 //default 2 //u8,
+//Bit 23:16 reg_fd_min_grad_th_p1 //default 4 //u8,
+//Bit 15:8 reg_fd_min_grad_th_p2 //default 8 //u8,
+//Bit 7:0 reg_fd_min_grad_th_p3 //default 12 //u8,
+#define DI_PD_GRAD_TH_N ((0x17e2 << 2) + 0xff000000)
+//Bit 31:24 reg_fd_min_grad_th_n0 //default 4 //u8,
+//Bit 23:16 reg_fd_min_grad_th_n1 //default 8 //u8,
+//Bit 15:8 reg_fd_min_grad_th_n2 //default 16 //u8,
+//Bit 7:0 reg_fd_min_grad_th_n3 //default 32 //u8,
+#define DI_PD_GRAD_GAIN_P ((0x17e3 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:24 reg_fd_min_grad_gain_p0 //default 16 //u5,
+//Bit 23:21 reserved
+//Bit 20:16 reg_fd_min_grad_gain_p1 //default 16 //u5,
+//Bit 15:13 reserved
+//Bit 12:8 reg_fd_min_grad_gain_p2 //default 16 //u5,
+//Bit 7:5 reserved
+//Bit 4:0 reg_fd_min_grad_gain_p3 //default 16 //u5,
+#define DI_PD_GRAD_GAIN_N ((0x17e4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:24 reg_fd_min_grad_gain_n0 //default 12 //u5,
+//Bit 23:21 reserved
+//Bit 20:16 reg_fd_min_grad_gain_n1 //default 12 //u5,
+//Bit 15:13 reserved
+//Bit 12:8 reg_fd_min_grad_gain_n2 //default 14 //u5,
+//Bit 7:5 reserved
+//Bit 4:0 reg_fd_min_grad_gain_n3 //default 15 //u5,
+#define DI_PD_RO_SUM_P_WIN0 ((0x17e5 << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_p0
+#define DI_PD_RO_SUM_P_WIN1 ((0x17e6 << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_p1
+#define DI_PD_RO_SUM_P_WIN2 ((0x17e7 << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_p2
+#define DI_PD_RO_SUM_P_WIN3 ((0x17e8 << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_p3
+#define DI_PD_RO_SUM_P_WIN4 ((0x17e9 << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_p4
+#define DI_PD_RO_SUM_N_WIN0 ((0x17ea << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_n0
+#define DI_PD_RO_SUM_N_WIN1 ((0x17eb << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_n1
+#define DI_PD_RO_SUM_N_WIN2 ((0x17ec << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_n2
+#define DI_PD_RO_SUM_N_WIN3 ((0x17ed << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_n3
+#define DI_PD_RO_SUM_N_WIN4 ((0x17ee << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_n4
+#define DI_PD_RO_CNT_P_WIN0 ((0x17ef << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_p0
+#define DI_PD_RO_CNT_P_WIN1 ((0x17f0 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_p1
+#define DI_PD_RO_CNT_P_WIN2 ((0x17f1 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_p2
+#define DI_PD_RO_CNT_P_WIN3 ((0x17f2 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_p3
+#define DI_PD_RO_CNT_P_WIN4 ((0x17f3 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_p4
+#define DI_PD_RO_CNT_N_WIN0 ((0x17f4 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_n0
+#define DI_PD_RO_CNT_N_WIN1 ((0x17f5 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_n1
+#define DI_PD_RO_CNT_N_WIN2 ((0x17f6 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_n2
+#define DI_PD_RO_CNT_N_WIN3 ((0x17f7 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_n3
+#define DI_PD_RO_CNT_N_WIN4 ((0x17f8 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_n4
+#define DI_PD_RO_SUM_P ((0x17f9 << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_p_glb
+#define DI_PD_RO_SUM_N ((0x17fa << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_n_glb
+#define DI_PD_RO_CNT_P ((0x17fb << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_p_glb
+#define DI_PD_RO_CNT_N ((0x17fc << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_n_glb
+//
+// Closing file: di_pd_grad_reg.h
+//
+//`define DI_INP_GEN_REG 8'hce
+//`define DI_INP_CANVAS0 8'hcf
+//`define DI_INP_LUMA_X0 8'hd0
+//`define DI_INP_LUMA_Y0 8'hd1
+//`define DI_INP_CHROMA_X0 8'hd2
+//`define DI_INP_CHROMA_Y0 8'hd3
+//`define DI_INP_RPT_LOOP 8'hd4
+//`define DI_INP_LUMA0_RPT_PAT 8'hd5
+//`define DI_INP_CHROMA0_RPT_PAT 8'hd6
+//`define DI_INP_DUMMY_PIXEL 8'hd7
+//`define DI_INP_LUMA_FIFO_SIZE 8'hd8
+//`define DI_INP_RANGE_MAP_Y 8'hba
+//`define DI_INP_RANGE_MAP_CB 8'hbb
+//`define DI_INP_RANGE_MAP_CR 8'hbc
+//`define DI_INP_GEN_REG2 8'h91
+//
+//`define DI_INP_FMT_CTRL 8'hd9
+//`define DI_INP_FMT_W 8'hda
+////
+//`define DI_MEM_GEN_REG 8'hdb
+//`define DI_MEM_CANVAS0 8'hdc
+//`define DI_MEM_LUMA_X0 8'hdd
+//`define DI_MEM_LUMA_Y0 8'hde
+//`define DI_MEM_CHROMA_X0 8'hdf
+//`define DI_MEM_CHROMA_Y0 8'he0
+//`define DI_MEM_RPT_LOOP 8'he1
+//`define DI_MEM_LUMA0_RPT_PAT 8'he2
+//`define DI_MEM_CHROMA0_RPT_PAT 8'he3
+//`define DI_MEM_DUMMY_PIXEL 8'he4
+//`define DI_MEM_LUMA_FIFO_SIZE 8'he5
+//`define DI_MEM_RANGE_MAP_Y 8'hbd
+//`define DI_MEM_RANGE_MAP_CB 8'hbe
+//`define DI_MEM_RANGE_MAP_CR 8'hbf
+//`define DI_MEM_GEN_REG2 8'h92
+//
+//`define DI_MEM_FMT_CTRL 8'he6
+//`define DI_MEM_FMT_W 8'he7
+//
+//`define DI_IF1_GEN_REG 8'he8
+//`define DI_IF1_CANVAS0 8'he9
+//`define DI_IF1_LUMA_X0 8'hea
+//`define DI_IF1_LUMA_Y0 8'heb
+//`define DI_IF1_CHROMA_X0 8'hec
+//`define DI_IF1_CHROMA_Y0 8'hed
+//`define DI_IF1_RPT_LOOP 8'hee
+//`define DI_IF1_LUMA0_RPT_PAT 8'hef
+//`define DI_IF1_CHROMA0_RPT_PAT 8'hf0
+//`define DI_IF1_DUMMY_PIXEL 8'hf1
+//`define DI_IF1_LUMA_FIFO_SIZE 8'hf2
+//`define DI_IF1_RANGE_MAP_Y 8'hfc
+//`define DI_IF1_RANGE_MAP_CB 8'hfd
+//`define DI_IF1_RANGE_MAP_CR 8'hfe
+//`define DI_IF1_GEN_REG2 8'h90
+//
+//`define DI_IF1_FMT_CTRL 8'hf3
+//`define DI_IF1_FMT_W 8'hf4
+//
+//
+//`define DI_CHAN2_GEN_REG 8'hf5
+//`define DI_CHAN2_CANVAS0 8'hf6
+//`define DI_CHAN2_LUMA_X0 8'hf7
+//`define DI_CHAN2_LUMA_Y0 8'hf8
+//`define DI_CHAN2_CHROMA_X0 8'hf9
+//`define DI_CHAN2_CHROMA_Y0 8'hfa
+//`define DI_CHAN2_RPT_LOOP 8'hfb
+//`define DI_CHAN2_LUMA0_RPT_PAT 8'hb0
+//`define DI_CHAN2_CHROMA0_RPT_PAT 8'hb1
+//`define DI_CHAN2_DUMMY_PIXEL 8'hb2
+//`define DI_CHAN2_LUMA_FIFO_SIZE 8'hb3
+//`define DI_CHAN2_RANGE_MAP_Y 8'hb4
+//`define DI_CHAN2_RANGE_MAP_CB 8'hb5
+//`define DI_CHAN2_RANGE_MAP_CR 8'hb6
+//`define DI_CHAN2_GEN_REG2 8'hb7
+//`define DI_CHAN2_FMT_CTRL 8'hb8
+//`define DI_CHAN2_FMT_W 8'hb9
+//
+// Closing file: vpu_mad_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: MADD_VCBUS_BASE = 0x18
+// -----------------------------------------------
+//
+// Reading file: di_dolby_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DOLBY_CORE1C_REG_START ((0x1800 << 2) + 0xff000000)
+#define DOLBY_CORE1C_CLKGATE_CTRL ((0x18f2 << 2) + 0xff000000)
+#define DOLBY_CORE1C_SWAP_CTRL0 ((0x18f3 << 2) + 0xff000000)
+#define DOLBY_CORE1C_SWAP_CTRL1 ((0x18f4 << 2) + 0xff000000)
+#define DOLBY_CORE1C_SWAP_CTRL2 ((0x18f5 << 2) + 0xff000000)
+#define DOLBY_CORE1C_SWAP_CTRL3 ((0x18f6 << 2) + 0xff000000)
+#define DOLBY_CORE1C_SWAP_CTRL4 ((0x18f7 << 2) + 0xff000000)
+#define DOLBY_CORE1C_SWAP_CTRL5 ((0x18f8 << 2) + 0xff000000)
+#define DOLBY_CORE1C_DMA_CTRL ((0x18f9 << 2) + 0xff000000)
+#define DOLBY_CORE1C_DMA_STATUS ((0x18fa << 2) + 0xff000000)
+#define DOLBY_CORE1C_STATUS0 ((0x18fb << 2) + 0xff000000)
+#define DOLBY_CORE1C_STATUS1 ((0x18fc << 2) + 0xff000000)
+#define DOLBY_CORE1C_STATUS2 ((0x18fd << 2) + 0xff000000)
+#define DOLBY_CORE1C_STATUS3 ((0x18fe << 2) + 0xff000000)
+#define DOLBY_CORE1C_DMA_PORT ((0x18ff << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: di_dolby_regs.h
+//
+//`include "di_inp_afbc_dec_regs.h"
+//`include "di_mem_afbc_dec_regs.h"
+//`include "fgrain_di_regs.h"
+// -----------------------------------------------
+// REG_BASE: VPP2_VCBUS_BASE = 0x19
+// -----------------------------------------------
+//`include "vpp2_regs.h"
+//
+// Reading file: vregs_clk2.h
+//
+//===========================================================================
+// Video Interface Registers 0xa00 - 0xaff
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VIU_VCBUS_BASE = 0x1a
+// -----------------------------------------------
+#define VIU_ADDR_START ((0x1a00 << 2) + 0xff000000)
+#define VIU_ADDR_END ((0x1aff << 2) + 0xff000000)
+//`define TRACE_REG 8'ff
+//------------------------------------------------------------------------------
+// VIU top-level registers
+//------------------------------------------------------------------------------
+// Bit 0 RW, osd1_reset
+// Bit 1 RW, osd2_reset
+// Bit 2 RW, vd1_reset
+// Bit 3 RW, vd1_fmt_reset
+// Bit 4 RW, vd2_reset
+// Bit 5 RW, vd2_fmt_reset
+// Bit 6 RW, di_dsr1to2_reset
+// Bit 7 RW, vpp_reset
+// Bit 8 RW, di_if1_reset
+// Bit 9 RW, di_if1_fmt_reset
+// Bit 10 RW, di_inp_reset
+// Bit 11 RW, di_inp_fmt_reset
+// Bit 12 RW, di_mem_reset
+// Bit 13 RW, di_mem_fmt_reset
+// Bit 14 RW, di_nr_wr_mif_reset
+// Bit 15 RW, dein_wr_mif_reset
+// Bit 16 RW, di_chan2_mif_reset
+// Bit 17 RW, di_mtn_wr_mif_reset
+// Bit 18 RW, di_mtn_rd_mif_reset
+// Bit 19 RW, di_mad_reset
+// Bit 20 RW, vdin0_reset
+// Bit 21 RW, vdin1_reset
+// Bit 22 RW, nrin_mux_reset
+// Bit 23 RW, vdin0_wr_reset
+// Bit 24 RW, vdin1_wr_reset
+// Bit 25 RW, reserved
+// Bit 26 RW, d2d3_reset
+// Bit 27 RW, di_cont_wr_mif_reset
+// Bit 28 RW, di_cont_rd_mif_reset
+#define VIU_SW_RESET ((0x1a01 << 2) + 0xff000000)
+#define VIU_SW_RESET0 ((0x1a02 << 2) + 0xff000000)
+// Bit 0 RW, software reset for mcvecrd_mif
+// Bit 1 RW, software reset for mcinfowr_mif
+// Bit 2 RW, software reset for mcinford_mif
+#define VIU_SECURE_REG ((0x1a04 << 2) + 0xff000000)
+// Bit 0 RW, dolby core1_tv secure w and r
+// Bit 1 RW, dolby core2 secure w and r
+// Bit 2 RW, dolby core3 secure w and r
+// Bit 3 RW, for osd1 secure read
+// Bit 4 RW, for osd2 secure read
+#define DOLBY_INT_STAT ((0x1a05 << 2) + 0xff000000)
+// todo
+//bit 15:12 osdbld_gclk_ctrl 3:2 regclk ctrl 1:0 blending clk control
+//bit 8 if true, vsync interrup is generate only field == 0
+//bit 7:0 fix_disable
+#define VIU_MISC_CTRL0 ((0x1a06 << 2) + 0xff000000)
+#define VIU_MISC_CTRL1 ((0x1a07 << 2) + 0xff000000)
+// Bit 15:14 mali_afbcd_gclk_ctrl mali_afbcd clock gate control[5:4]
+// Bit 12 osd1_afbcd_axi_mux 0 : use the osd mif as input; 1 : use afbcd as input
+// Bit 11:8 mali_afbcd_gclk_ctrl mali_afbcd clock gate control[3:0]
+// Bit 7:2 vd2_afbcd_gclk_ctrl vd2_afbcd clock gate control
+// Bit 1 vpp_vd2_din_sel 0: vpp vd2 sel the mif input; 1: vpp vd2 sel the dos afbcd
+// Bit 0 vd2_afbcd_out_sel 0: vd2_afbcd output to vpp; 1 : vd2_afbcd output to di inp
+#define VIU_SECURE_DUMMY ((0x1a08 << 2) + 0xff000000)
+#define VIU_SECURE_ST_RO ((0x1a09 << 2) + 0xff000000)
+// Bit 31:30 vdin0 dout splitter, bit 0 turns on vdin0 to old path, bit 1 turns on vdin0 to d2d3_intf vdin0 input path
+// Bit 29:28 vdin1 dout splitter, bit 0 turns on vdin1 to old path, bit 1 turns on vdin1 to d2d3_intf vdin1 input path
+// Bit 27:26 NR write dout splitter, bit 0 turns on NR write to old path, bit 1 turns on NR WR to d2d3_intf NR WR input path
+// Bit 23 if true, turn on clk_d2d3_reg (register clock)
+// Bit 22 if true, turn on clk_d2d3
+// Bit 21 reg_v1_go_line
+// Bit 20 reg_v1_go_field
+// Bit 19 reg_v0_go_field
+// Bit 18:16 v1_gofld_sel, 000: display go_field/go_line, 001: DI pre_frame_rst/go_line, 010: vdin0 go_field/go_line,
+//011: vdin1 go_field/go_line, otherwise: force go_field by reg_v1_go_field(bit20), force go_line by reg_v1_go_line(bit21)
+// Bit 15:13 v0_gofld_sel, 000: display go_field, 001: DI pre_frame_rst, 010: vdin0 go_field, 011: vdin1 go_field, otherwise: force go_field by
+// reg_v0_go_field(bit19)
+// Bit 12:6 hole_lines for d2d3 depth read interface
+// Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 fomart output), 2'b10: scale output, otherwise nothing as v1
+// Bit 3 use_vdin_eol, if true, use vdin eol as the v0_eol, otherwise using length to get the v0_eol
+// Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 fomart output), 101: vpp scale output
+//
+// `define D2D3_INTF_CTRL0 8'h09
+#define VD1_AFBCD0_MISC_CTRL ((0x1a0a << 2) + 0xff000000)
+#define VD2_AFBCD1_MISC_CTRL ((0x1a0b << 2) + 0xff000000)
+#define DOLBY_PATH_CTRL ((0x1a0c << 2) + 0xff000000)
+#define WR_BACK_MISC_CTRL ((0x1a0d << 2) + 0xff000000)
+#define OSD_PATH_MISC_CTRL ((0x1a0e << 2) + 0xff000000)
+#define MALI_AFBCD_TOP_CTRL ((0x1a0f << 2) + 0xff000000)
+#define VIU_DATA_SEC ((0x1a50 << 2) + 0xff000000)
+#define VIU_FRM_CTRL ((0x1a51 << 2) + 0xff000000)
+#define VIU_RDMIF_DEPTH ((0x1a52 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// OSD1 registers
+//------------------------------------------------------------------------------
+// Bit 31 Reserved
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// 0=use gated clock for low power.
+// Bit 29 R, test_rd_dsr
+// Bit 28 R, osd_done
+// Bit 27:24 R, osd_blk_mode
+// Bit 23:22 R, osd_blk_ptr
+// Bit 21 R, osd_enable
+//
+// Bit 20:12 RW, global_alpha
+// Bit 11 RW, test_rd_en
+// Bit 10: 9 Reserved for control signals
+// Bit 8: 5 RW, ctrl_mtch_y
+// Bit 4 RW, ctrl_422to444
+// Bit 3: 0 RW, osd_blk_enable. Bit 0 to enable block 0: 1=enable, 0=disable;
+// Bit 1 to enable block 1, and so on.
+#define VIU_OSD1_CTRL_STAT ((0x1a10 << 2) + 0xff000000)
+// Bit 31:26 Reserved
+// Bit 25:16 R, fifo_count
+// Bit 15 RW, osd_dpath_sel 0-osd1 mif 1-vpu mali afbcd
+// Bit 14 RW, replaced_alpha_en
+// Bit 13: 6 RW, replaced_alpha
+// Bit 5: 4 RW, hold_fifo_lines[6:5]
+// Bit 3 RW, rgb2yuv_full_range
+// Bit 2 RW, alpha_9b_mode
+// Bit 1 RW, reserved
+// Bit 0 RW, color_expand_mode
+#define VIU_OSD1_CTRL_STAT2 ((0x1a2d << 2) + 0xff000000)
+// Bit 31: 9 Reserved
+// Bit 8 RW, 0 = Write LUT, 1 = Read LUT
+// Bit 7: 0 RW, lut_addr
+#define VIU_OSD1_COLOR_ADDR ((0x1a11 << 2) + 0xff000000)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define VIU_OSD1_COLOR ((0x1a12 << 2) + 0xff000000)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define VIU_OSD1_TCOLOR_AG0 ((0x1a17 << 2) + 0xff000000)
+#define VIU_OSD1_TCOLOR_AG1 ((0x1a18 << 2) + 0xff000000)
+#define VIU_OSD1_TCOLOR_AG2 ((0x1a19 << 2) + 0xff000000)
+#define VIU_OSD1_TCOLOR_AG3 ((0x1a1a << 2) + 0xff000000)
+// Bit 31:30 Reserved
+// Bit 29 RW, y_rev: 0=normal read, 1=reverse read in Y direction
+// Bit 28 RW, x_rev: 0=normal read, 1=reverse read in X direction
+// Bit 27:24 Reserved
+// Bit 23:16 RW, tbl_addr
+// Bit 15 RW, little_endian: 0=big endian, 1=little endian
+// Bit 14 RW, rpt_y
+// Bit 13:12 RW, interp_ctrl. 0x=No interpolation; 10=Interpolate with previous
+// pixel; 11=Interpolate with the average value
+// between previous and next pixel.
+// Bit 11: 8 RW, osd_blk_mode
+// Bit 7 RW, rgb_en
+// Bit 6 RW, tc_alpha_en
+// Bit 5: 2 RW, color_matrix
+// Bit 1 RW, interlace_en
+// Bit 0 RW, interlace_sel_odd
+#define VIU_OSD1_BLK0_CFG_W0 ((0x1a1b << 2) + 0xff000000)
+#define VIU_OSD1_BLK1_CFG_W0 ((0x1a1f << 2) + 0xff000000)
+#define VIU_OSD1_BLK2_CFG_W0 ((0x1a23 << 2) + 0xff000000)
+#define VIU_OSD1_BLK3_CFG_W0 ((0x1a27 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, x_end
+// Bit 15:13 Reserved
+// Bit 12: 0 RW, x_start
+#define VIU_OSD1_BLK0_CFG_W1 ((0x1a1c << 2) + 0xff000000)
+#define VIU_OSD1_BLK1_CFG_W1 ((0x1a20 << 2) + 0xff000000)
+#define VIU_OSD1_BLK2_CFG_W1 ((0x1a24 << 2) + 0xff000000)
+#define VIU_OSD1_BLK3_CFG_W1 ((0x1a28 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, y_end
+// Bit 15:13 Reserved
+// Bit 12: 0 RW, y_start
+#define VIU_OSD1_BLK0_CFG_W2 ((0x1a1d << 2) + 0xff000000)
+#define VIU_OSD1_BLK1_CFG_W2 ((0x1a21 << 2) + 0xff000000)
+#define VIU_OSD1_BLK2_CFG_W2 ((0x1a25 << 2) + 0xff000000)
+#define VIU_OSD1_BLK3_CFG_W2 ((0x1a29 << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, h_end
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, h_start
+#define VIU_OSD1_BLK0_CFG_W3 ((0x1a1e << 2) + 0xff000000)
+#define VIU_OSD1_BLK1_CFG_W3 ((0x1a22 << 2) + 0xff000000)
+#define VIU_OSD1_BLK2_CFG_W3 ((0x1a26 << 2) + 0xff000000)
+#define VIU_OSD1_BLK3_CFG_W3 ((0x1a2a << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, v_end
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, v_start
+#define VIU_OSD1_BLK0_CFG_W4 ((0x1a13 << 2) + 0xff000000)
+#define VIU_OSD1_BLK1_CFG_W4 ((0x1a14 << 2) + 0xff000000)
+#define VIU_OSD1_BLK2_CFG_W4 ((0x1a15 << 2) + 0xff000000)
+#define VIU_OSD1_BLK3_CFG_W4 ((0x1a16 << 2) + 0xff000000)
+// Bit 31 RW, burst_len_sel[2] of [2:0]
+// Bit 30 RW, byte_swap: In addition to endian control, further define
+// whether to swap upper and lower byte within a 16-bit mem word.
+// 0=No swap; 1=Swap data[15:0] to be {data[7:0], data[15:8]}
+// Bit 29 RW, div_swap : swap the 2 64bits words in 128 bit word
+// Bit 28:24 RW, fifo_lim : when osd fifo is small than the fifo_lim*16, closed the rq port of osd_rd_mif
+// Bit 23:22 RW, fifo_ctrl: 00 : for 1 word in 1 burst , 01 : for 2words in 1burst, 10: for 4words in 1burst, 11: reserved
+// Bit 21:20 R, fifo_st. 0=IDLE, 1=FILL, 2=ABORT
+// Bit 19 R, fifo_overflow
+// Bit 18:12 RW, fifo_depth_val, max value=64: set actual fifo depth to fifo_depth_val*8.
+// Bit 11:10 RW, burst_len_sel[1:0] of [2:0]. 0=24(default), 1=32, 2=48, 3=64, 4=96, 5=128.
+// Bit 9: 5 RW, hold_fifo_lines[4:0]
+// Bit 4 RW, clear_err: one pulse to clear fifo_overflow
+// Bit 3 RW, fifo_sync_rst
+// Bit 2: 1 RW, endian
+// Bit 0 RW, urgent
+#define VIU_OSD1_FIFO_CTRL_STAT ((0x1a2b << 2) + 0xff000000)
+// Bit 31:24 R, Y or R
+// Bit 23:16 R, Cb or G
+// Bit 15: 8 R, Cr or B
+// Bit 7: 0 R, Output Alpha[8:1]
+#define VIU_OSD1_TEST_RDDATA ((0x1a2c << 2) + 0xff000000)
+// Bit 15 RW, prot_en: 1=Borrow PROT's FIFO storage, either for rotate or non-rotate.
+// Bit 12: 0 RW, effective FIFO size when prot_en=1.
+#define VIU_OSD1_PROT_CTRL ((0x1a2e << 2) + 0xff000000)
+//Bit 7, highlight_en
+//Bit 6 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix
+//Bit 5:4 probe_sel, 00: select matrix 0, 01: select matrix 1, otherwise select nothing
+//Bit 3:2, matrix coef idx selection, 00: select mat0, 01: select mat1, otherwise slect nothing
+//Bit 1 mat1 conversion matrix enable
+//Bit 0 mat0 conversion matrix enable
+#define VIU_OSD1_MATRIX_CTRL ((0x1a90 << 2) + 0xff000000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define VIU_OSD1_MATRIX_COEF00_01 ((0x1a91 << 2) + 0xff000000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define VIU_OSD1_MATRIX_COEF02_10 ((0x1a92 << 2) + 0xff000000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define VIU_OSD1_MATRIX_COEF11_12 ((0x1a93 << 2) + 0xff000000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define VIU_OSD1_MATRIX_COEF20_21 ((0x1a94 << 2) + 0xff000000)
+//Bit 31:30 mat_clmod
+//Bit 18:16 mat_convrs
+//Bit 12:0 mat_coef42
+#define VIU_OSD1_MATRIX_COLMOD_COEF42 ((0x1a95 << 2) + 0xff000000)
+//Bit 26:16 offset0
+//Bit 10:0 offset1
+#define VIU_OSD1_MATRIX_OFFSET0_1 ((0x1a96 << 2) + 0xff000000)
+//Bit 10:0 offset2
+#define VIU_OSD1_MATRIX_OFFSET2 ((0x1a97 << 2) + 0xff000000)
+//Bit 26:16 pre_offset0
+//Bit 10:0 pre_offset1
+#define VIU_OSD1_MATRIX_PRE_OFFSET0_1 ((0x1a98 << 2) + 0xff000000)
+//Bit 10:0 pre_offset2
+#define VIU_OSD1_MATRIX_PRE_OFFSET2 ((0x1a99 << 2) + 0xff000000)
+//Read only
+//Bit 29:20 component 0
+//Bit 19:10 component 1
+//Bit 9:0 component 2
+#define VIU_OSD1_MATRIX_PROBE_COLOR ((0x1a9a << 2) + 0xff000000)
+//Bit 23:16 component 0
+//Bit 15:8 component 1
+//Bit 7:0 component 2
+#define VIU_OSD1_MATRIX_HL_COLOR ((0x1a9b << 2) + 0xff000000)
+//28:16 probe x, postion
+//12:0 probe y, position
+#define VIU_OSD1_MATRIX_PROBE_POS ((0x1a9c << 2) + 0xff000000)
+//Bit 28:16 coef22
+//Bit 12:0 coef30
+#define VIU_OSD1_MATRIX_COEF22_30 ((0x1a9d << 2) + 0xff000000)
+//Bit 28:16 coef31
+//Bit 12:0 coef32
+#define VIU_OSD1_MATRIX_COEF31_32 ((0x1a9e << 2) + 0xff000000)
+//Bit 28:16 coef40
+//Bit 12:0 coef41
+#define VIU_OSD1_MATRIX_COEF40_41 ((0x1a9f << 2) + 0xff000000)
+//Bit 31:27 for all [31] for all eotf enable,[30] for matrix3x3 enable, [29:27] for eotf_ch0~3
+//Bit 17:6 for clock gating
+//Bit 5:4 pscale_mode ch2
+//Bit 3:2 pscale_mode ch1
+//Bit 1:0 pscale_mode ch0
+#define VIU_OSD1_EOTF_CTL ((0x1ad4 << 2) + 0xff000000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define VIU_OSD1_EOTF_COEF00_01 ((0x1ad5 << 2) + 0xff000000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define VIU_OSD1_EOTF_COEF02_10 ((0x1ad6 << 2) + 0xff000000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define VIU_OSD1_EOTF_COEF11_12 ((0x1ad7 << 2) + 0xff000000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define VIU_OSD1_EOTF_COEF20_21 ((0x1ad8 << 2) + 0xff000000)
+//Bit 28:16 coef22
+//Bit 2:0 coef_rs
+#define VIU_OSD1_EOTF_COEF22_RS ((0x1ad9 << 2) + 0xff000000)
+#define VIU_OSD1_EOTF_LUT_ADDR_PORT ((0x1ada << 2) + 0xff000000)
+#define VIU_OSD1_EOTF_LUT_DATA_PORT ((0x1adb << 2) + 0xff000000)
+//Bit 31:29 for OETF ch0~ch2
+//Bit 21:12 for clock gating
+//Bit 11:8 for oetf_scl_ch2
+//Bit 7:4 for oetf_scl_ch1
+//Bit 3:0 for oetf_scl_ch0
+#define VIU_OSD1_OETF_CTL ((0x1adc << 2) + 0xff000000)
+#define VIU_OSD1_OETF_LUT_ADDR_PORT ((0x1add << 2) + 0xff000000)
+#define VIU_OSD1_OETF_LUT_DATA_PORT ((0x1ade << 2) + 0xff000000)
+#define VIU_OSD1_OETF_3X3_OFST_0 ((0x1aa0 << 2) + 0xff000000)
+#define VIU_OSD1_OETF_3X3_OFST_1 ((0x1aa1 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// OSD2 registers
+//------------------------------------------------------------------------------
+// Bit 31 Reserved
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// 0=use gated clock for low power.
+// Bit 29 R, test_rd_dsr
+// Bit 28 R, osd_done
+// Bit 27:24 R, osd_blk_mode
+// Bit 23:22 R, osd_blk_ptr
+// Bit 21 R, osd_enable
+//
+// Bit 20:12 RW, global_alpha
+// Bit 11 RW, test_rd_en
+// Bit 10 RW, hl2_en
+// Bit 9 RW, hl1_en
+// Bit 8: 5 RW, ctrl_mtch_y
+// Bit 4 RW, ctrl_422to444
+// Bit 3: 0 RW, osd_blk_enable. Bit 0 to enable block 0: 1=enable, 0=disable;
+// Bit 1 to enable block 1, and so on.
+#define VIU_OSD2_CTRL_STAT ((0x1a30 << 2) + 0xff000000)
+// Bit 31:26 Reserved
+// Bit 25:16 R, fifo_count
+// Bit 15 Reserved
+// Bit 14 RW, replaced_alpha_en
+// Bit 13: 6 RW, replaced_alpha
+// Bit 5: 4 RW, hold_fifo_lines[6:5]
+// Bit 3 RW, rgb2yuv_full_range
+// Bit 2 RW, alpha_9b_mode
+// Bit 1 RW, reserved
+// Bit 0 RW, color_expand_mode
+#define VIU_OSD2_CTRL_STAT2 ((0x1a4d << 2) + 0xff000000)
+// Bit 31: 9 Reserved
+// Bit 8 RW, 0 = Write LUT, 1 = Read LUT
+// Bit 7: 0 RW, lut_addr
+#define VIU_OSD2_COLOR_ADDR ((0x1a31 << 2) + 0xff000000)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define VIU_OSD2_COLOR ((0x1a32 << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, hl[1-2]_h/v_start
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, hl[1-2]_h/v_end
+#define VIU_OSD2_HL1_H_START_END ((0x1a33 << 2) + 0xff000000)
+#define VIU_OSD2_HL1_V_START_END ((0x1a34 << 2) + 0xff000000)
+#define VIU_OSD2_HL2_H_START_END ((0x1a35 << 2) + 0xff000000)
+#define VIU_OSD2_HL2_V_START_END ((0x1a36 << 2) + 0xff000000)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define VIU_OSD2_TCOLOR_AG0 ((0x1a37 << 2) + 0xff000000)
+#define VIU_OSD2_TCOLOR_AG1 ((0x1a38 << 2) + 0xff000000)
+#define VIU_OSD2_TCOLOR_AG2 ((0x1a39 << 2) + 0xff000000)
+#define VIU_OSD2_TCOLOR_AG3 ((0x1a3a << 2) + 0xff000000)
+// Bit 31:24 Reserved
+// Bit 23:16 RW, tbl_addr
+// Bit 15 RW, little_endian: 0=big endian, 1=little endian
+// Bit 14 RW, rpt_y
+// Bit 13:12 RW, interp_ctrl. 0x=No interpolation; 10=Interpolate with previous
+// pixel; 11=Interpolate with the average value
+// between previous and next pixel.
+// Bit 11: 8 RW, osd_blk_mode
+// Bit 7 RW, rgb_en
+// Bit 6 RW, tc_alpha_en
+// Bit 5: 2 RW, color_matrix
+// Bit 1 RW, interlace_en
+// Bit 0 RW, interlace_sel_odd
+#define VIU_OSD2_BLK0_CFG_W0 ((0x1a3b << 2) + 0xff000000)
+#define VIU_OSD2_BLK1_CFG_W0 ((0x1a3f << 2) + 0xff000000)
+#define VIU_OSD2_BLK2_CFG_W0 ((0x1a43 << 2) + 0xff000000)
+#define VIU_OSD2_BLK3_CFG_W0 ((0x1a47 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, x_end
+// Bit 15:13 Reserved
+// Bit 12: 0 RW, x_start
+#define VIU_OSD2_BLK0_CFG_W1 ((0x1a3c << 2) + 0xff000000)
+#define VIU_OSD2_BLK1_CFG_W1 ((0x1a40 << 2) + 0xff000000)
+#define VIU_OSD2_BLK2_CFG_W1 ((0x1a44 << 2) + 0xff000000)
+#define VIU_OSD2_BLK3_CFG_W1 ((0x1a48 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, y_end
+// Bit 15:13 Reserved
+// Bit 12: 0 RW, y_start
+#define VIU_OSD2_BLK0_CFG_W2 ((0x1a3d << 2) + 0xff000000)
+#define VIU_OSD2_BLK1_CFG_W2 ((0x1a41 << 2) + 0xff000000)
+#define VIU_OSD2_BLK2_CFG_W2 ((0x1a45 << 2) + 0xff000000)
+#define VIU_OSD2_BLK3_CFG_W2 ((0x1a49 << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, h_end
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, h_start
+#define VIU_OSD2_BLK0_CFG_W3 ((0x1a3e << 2) + 0xff000000)
+#define VIU_OSD2_BLK1_CFG_W3 ((0x1a42 << 2) + 0xff000000)
+#define VIU_OSD2_BLK2_CFG_W3 ((0x1a46 << 2) + 0xff000000)
+#define VIU_OSD2_BLK3_CFG_W3 ((0x1a4a << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, v_end
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, v_start
+#define VIU_OSD2_BLK0_CFG_W4 ((0x1a64 << 2) + 0xff000000)
+#define VIU_OSD2_BLK1_CFG_W4 ((0x1a65 << 2) + 0xff000000)
+#define VIU_OSD2_BLK2_CFG_W4 ((0x1a66 << 2) + 0xff000000)
+#define VIU_OSD2_BLK3_CFG_W4 ((0x1a67 << 2) + 0xff000000)
+// Bit 31 RW, burst_len_sel[2] of [2:0]
+// Bit 30 RW, byte_swap: In addition to endian control, further define
+// whether to swap upper and lower byte within a 16-bit mem word.
+// 0=No swap; 1=Swap data[15:0] to be {data[7:0], data[15:8]}
+// Bit 29 RW, div_swap : swap the 2 64bits words in 128 bit word
+// Bit 28:24 RW, fifo_lim : when osd fifo is small than the fifo_lim*16, closed the rq port of osd_rd_mif
+// Bit 23:22 RW, fifo_ctrl: 00 : for 1 word in 1 burst , 01 : for 2words in 1burst, 10: for 4words in 1burst, 11: reserved
+// Bit 21:20 R, fifo_st. 0=IDLE, 1=FILL, 2=ABORT
+// Bit 19 R, fifo_overflow
+//
+// Bit 18:12 RW, fifo_depth_val, max value=64: set actual fifo depth to fifo_depth_val*8.
+// Bit 11:10 RW, burst_len_sel[1:0] of [2:0]. 0=24(default), 1=32, 2=48, 3=64, 4=96, 5=128.
+// Bit 9: 5 RW, hold_fifo_lines[4:0]
+// Bit 4 RW, clear_err: one pulse to clear fifo_overflow
+// Bit 3 RW, fifo_sync_rst
+// Bit 2: 1 RW, endian
+// Bit 0 RW, urgent
+#define VIU_OSD2_FIFO_CTRL_STAT ((0x1a4b << 2) + 0xff000000)
+// Bit 31:24 R, Y or R
+// Bit 23:16 R, Cb or G
+// Bit 15: 8 R, Cr or B
+// Bit 7: 0 R, Output Alpha[8:1]
+#define VIU_OSD2_TEST_RDDATA ((0x1a4c << 2) + 0xff000000)
+// Bit 15 RW, prot_en: 1=Borrow PROT's FIFO storage, either for rotate or non-rotate.
+// Bit 12: 0 RW, effective FIFO size when prot_en=1.
+#define VIU_OSD2_PROT_CTRL ((0x1a4e << 2) + 0xff000000)
+// //todo add comment
+#define LDIM_STTS_GCLK_CTRL0 ((0x1ac0 << 2) + 0xff000000)
+#define LDIM_STTS_CTRL0 ((0x1ac1 << 2) + 0xff000000)
+#define LDIM_STTS_WIDTHM1_HEIGHTM1 ((0x1ac2 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_COEF00_01 ((0x1ac3 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_COEF02_10 ((0x1ac4 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_COEF11_12 ((0x1ac5 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_COEF20_21 ((0x1ac6 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_COEF22 ((0x1ac7 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_OFFSET0_1 ((0x1ac8 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_OFFSET2 ((0x1ac9 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_PRE_OFFSET0_1 ((0x1aca << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_PRE_OFFSET2 ((0x1acb << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_HL_COLOR ((0x1acc << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_PROBE_POS ((0x1acd << 2) + 0xff000000)
+//
+// //read only
+#define LDIM_STTS_MATRIX_PROBE_COLOR ((0x1ace << 2) + 0xff000000)
+//
+// //Bit 31, local dimming statistic enable
+// //Bit 29, 1: output region histogram 16bit 0:output region histogram 20bit
+// //Bit 28, eol enable
+// //Bit 27:25, vertical line overlap number for max finding
+// //Bit 24:22, horizontal pixel overlap number, 0: 17 pix, 1: 9 pix, 2: 5 pix, 3: 3 pix, 4: 0 pix
+// //Bit 20, 1,2,1 low pass filter enable before max/hist statistic
+// //Bit 19:16, region H/V position index, refer to VDIN_LDIM_STTS_HIST_SET_REGION
+// //Bit 15:14, 1: region read index auto increase per block read finished to VDIN_LDIM_STTS_HIST_READ_REGION
+// // 2: region read index auto increase per read finished to VDIN_LDIM_STTS_HIST_READ_REGION
+// // 0/3: disable read index self increase
+// //Bit 13:8, region read sub index, which mux the hist & max-finding result to cbus port, refer to LDIM_STTS_HIST_READ_REGION
+// //Bit 6:0, region read index
+#define LDIM_STTS_HIST_REGION_IDX ((0x1ad0 << 2) + 0xff000000)
+//Bit 28:0, if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h0: read/write hvstart0
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h1: read/write hend01
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h2: read/write vend01
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h3: read/write hend23
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h4: read/write vend23
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h5: read/write hend45
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h6: read/write vend45
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'd7: read/write hend67
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h8: read/write vend67
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h9: read/write hend89
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'ha: read/write vend89
+// //hvstart0, Bit 28:16 row0 vstart, Bit 12:0 col0 hstart
+// //hend01, Bit 28:16 col1 hend, Bit 12:0 col0 hend
+// //vend01, Bit 28:16 row1 vend, Bit 12:0 row0 vend
+// //hend23, Bit 28:16 col3 hend, Bit 12:0 col2 hend
+// //vend23, Bit 28:16 row3 vend, Bit 12:0 row2 vend
+// //hend45, Bit 28:16 col5 hend, Bit 12:0 col4 hend
+// //vend45, Bit 28:16 row5 vend, Bit 12:0 row4 vend
+// //hend67, Bit 28:16 col7 hend, Bit 12:0 col6 hend
+// //vend67, Bit 28:16 row7 vend, Bit 12:0 row6 vend
+// //hend89, Bit 28:16 col9 hend, Bit 12:0 col8 hend
+// //vend89, Bit 28:16 row9 vend, Bit 12:0 row8 vend
+#define LDIM_STTS_HIST_SET_REGION ((0x1ad1 << 2) + 0xff000000)
+//
+// //if LDIM_STTS_HIST_REGION_IDX[29] == 0, that is output hist with 20bit data.
+// //if LDIM_STTS_HIST_REGION_IDX[21] == 0, that is output 16hist bins in comp 0.
+// //output sequence as rd_sub_idx from 0~47: {max_comp2, comp0_hist0}, {max_comp1, comp0_hist1}, {max_comp0, comp0_hist2},
+// // comp0_hist3 ... comp2_hist16
+// //if LDIM_STTS_HIST_REGION_IDX[29] == 1, that is output hist with 16bit data.
+// //if LDIM_STTS_HIST_REGION_IDX[21] == 0, that is output 16hist bins in comp 0.
+// //output sequence as rd_sub_idx from 0~47: {max_comp2, max_comp1, max_comp0}, comp0_hist0, comp0_hist1, comp0_hist2
+// // comp0_hist3 ... comp2_hist16
+// //if LDIM_STTS_HIST_REGION_IDX[29] == 0, that is output hist with 20bit data.
+// //if LDIM_STTS_HIST_REGION_IDX[21] == 1, that is output 32hist bins in comp 0.
+// //output sequence as rd_sub_idx from 0~47: {max_comp2, max_comp1, max_comp0}, comp0_hist0, comp0_hist1, comp0_hist2
+// // comp0_hist3 ...comp0_hist31 ... comp1_hist16
+//
+#define LDIM_STTS_HIST_READ_REGION ((0x1ad2 << 2) + 0xff000000)
+#define LDIM_STTS_HIST_START_RD_REGION ((0x1ad3 << 2) + 0xff000000)
+#define LDIM_STTS_PCTL_TH ((0x1aaf << 2) + 0xff000000)
+// //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di if1 chroma path
+// //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di if1 luma path
+// `define DI_IF1_URGENT_CTRL 8'ha3
+// //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path
+// //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path
+// `define DI_INP_URGENT_CTRL 8'ha4
+// //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di mem chroma path
+// //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di mem luma path
+// `define DI_MEM_URGENT_CTRL 8'ha5
+// //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di chan2 chroma path
+// //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di chan2 luma path
+// `define DI_CHAN2_URGENT_CTRL 8'ha6
+#define OSD_BLENDO_H_START_END ((0x1aa9 << 2) + 0xff000000)
+//OSD blending output horizontal start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define OSD_BLENDO_V_START_END ((0x1aaa << 2) + 0xff000000)
+//OSD blending output vertical start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define OSD_BLEND_GEN_CTRL0 ((0x1aab << 2) + 0xff000000)
+//Bit 31:23 const_out_alpha
+//Bit 22:14 const_op_alpha
+//Bit 13 if true, OSD2 foreground otherwise OSD1 foreground
+//Bit 12 OSD BLENDing enable
+//Bit 9:8 alpha_op_sel 00: output alpha use osd1_alpha, 01: use osd2_alpha, else use const_out_alpha
+//Bit 5:4 color_op_sel 00: use osd1_alpha, 01: use osd2_alpha, else use const_op_alpha
+//Bit 1 OSD2 enable
+//Bit 0 OSD1 enable
+#define OSD_BLEND_GEN_CTRL1 ((0x1aac << 2) + 0xff000000)
+//Bit 31 osd1_alpha_premult, if true, osd1 alpha is premultipiled
+//Bit 30 osd2_alpha_premult, if true, osd2 alpha is premultipiled
+//Bit 23:16 osd blending hold lines
+//Bit 13:0 osd blending h_size
+#define OSD_BLEND_DUMMY_DATA ((0x1aad << 2) + 0xff000000)
+//Bit 29:20 Y/R
+//Bit 19:10 CB/G
+//Bit 9:0 Cr/B
+#define OSD_BLEND_CURRENT_XY ((0x1aae << 2) + 0xff000000)
+//Bit 28:16 current_x
+//Bit 12:0 current_y
+//Bit 7, highlight_en
+//Bit 6 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix
+//Bit 5:4 probe_sel, 00: select matrix 0, 01: select matrix 1, otherwise select nothing
+//Bit 3:2, matrix coef idx selection, 00: select mat0, 01: select mat1, otherwise slect nothing
+//Bit 1 mat1 conversion matrix enable
+//Bit 0 mat0 conversion matrix enable
+#define VIU_OSD2_MATRIX_CTRL ((0x1ab0 << 2) + 0xff000000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define VIU_OSD2_MATRIX_COEF00_01 ((0x1ab1 << 2) + 0xff000000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define VIU_OSD2_MATRIX_COEF02_10 ((0x1ab2 << 2) + 0xff000000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define VIU_OSD2_MATRIX_COEF11_12 ((0x1ab3 << 2) + 0xff000000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define VIU_OSD2_MATRIX_COEF20_21 ((0x1ab4 << 2) + 0xff000000)
+#define VIU_OSD2_MATRIX_COEF22 ((0x1ab5 << 2) + 0xff000000)
+//Bit 26:16 offset0
+//Bit 10:0 offset1
+#define VIU_OSD2_MATRIX_OFFSET0_1 ((0x1ab6 << 2) + 0xff000000)
+//Bit 10:0 offset2
+#define VIU_OSD2_MATRIX_OFFSET2 ((0x1ab7 << 2) + 0xff000000)
+//Bit 26:16 pre_offset0
+//Bit 10:0 pre_offset1
+#define VIU_OSD2_MATRIX_PRE_OFFSET0_1 ((0x1ab8 << 2) + 0xff000000)
+//Bit 10:0 pre_offset2
+#define VIU_OSD2_MATRIX_PRE_OFFSET2 ((0x1ab9 << 2) + 0xff000000)
+//Read only
+//Bit 29:20 component 0
+//Bit 19:10 component 1
+//Bit 9:0 component 2
+#define VIU_OSD2_MATRIX_PROBE_COLOR ((0x1aba << 2) + 0xff000000)
+//Bit 23:16 component 0
+//Bit 15:8 component 1
+//Bit 7:0 component 2
+#define VIU_OSD2_MATRIX_HL_COLOR ((0x1abb << 2) + 0xff000000)
+//28:16 probe x, postion
+//12:0 probe y, position
+#define VIU_OSD2_MATRIX_PROBE_POS ((0x1abc << 2) + 0xff000000)
+////add for OSD1/2 mali_unpack
+#define VIU_OSD1_MALI_UNPACK_CTRL ((0x1a2f << 2) + 0xff000000)
+//`define VIU_OSD1_MALI_UNPACK_CTRL 8'h4f //todo
+//`define VIU_OSD1_MALI_UNPACK_CTRL 8'haf //todo
+#define VIU_OSD2_MALI_UNPACK_CTRL ((0x1abd << 2) + 0xff000000)
+//`define VIU_OSD2_MATRIX_HL_COLOR 8'hbe
+//`define VIU_OSD2_MATRIX_PROBE_POS 8'hbf
+//can use 8'hdf 8'hcf
+#define VIU_OSD1_DIMM_CTRL ((0x1adf << 2) + 0xff000000)
+#define VIU_OSD2_DIMM_CTRL ((0x1acf << 2) + 0xff000000)
+#define VIU_GCLK_CTRL ((0x1a4f << 2) + 0xff000000)
+//the segment of afbc dec is 8'he0-8'hfe
+//`define AFBC_DEC_OFFSET 8'he0
+//
+// Reading file: afbc_dec_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+//// reg
+////===============================////
+#define AFBC_ENABLE ((0x1ae0 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:23, reg_gclk_ctrl_core unsigned, default = 0
+//Bit 22, reg_fmt_size_sw_mode unsigned, default = 0, 0:hw mode 1:sw mode for format size
+//Bit 21, reg_addr_link_en unsigned, default = 1, 1:enable
+//Bit 20, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb
+//Bit 19, reg_dos_uncomp_mode unsigned , default = 0
+//Bit 18:16, soft_rst unsigned , default = 4
+//Bit 15:14, reserved
+//Bit 13:12, ddr_blk_size unsigned , default = 1
+//Bit 11:9, cmd_blk_size unsigend , default = 3
+//Bit 8, dec_enable unsigned , default = 0
+//Bit 7:2, reserved
+//Bit 1, head_len_sel unsigned , default = 1
+//Bit 0, dec_frm_start unsigned , default = 0
+#define AFBC_MODE ((0x1ae1 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29, ddr_sz_mode uns, default = 0 , 0: fixed block ddr size 1 : unfixed block ddr size;
+//Bit 28, blk_mem_mode uns, default = 0 , 0: fixed 16x128 size; 1 : fixed 12x128 size
+//Bit 27:26, rev_mode uns, default = 0 , reverse mode
+//Bit 25:24, mif_urgent uns, default = 3 , info mif and data mif urgent
+//Bit 23, reserved
+//Bit 22:16, hold_line_num uns, default = 4 ,
+//Bit 15:14, burst_len uns, default = 2, 0: burst1 1:burst2 2:burst4
+//Bit 13:8, compbits_yuv uns, default = 0 ,
+// bit 1:0,: y component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+// bit 3:2,: u component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+// bit 5:4,: v component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+//Bit 7:6, vert_skip_y uns, default = 0 , luma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 5:4, horz_skip_y uns, default = 0 , luma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 3:2, vert_skip_uv uns, default = 0 , chroma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 1:0, horz_skip_uv uns, default = 0 , chroma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+#define AFBC_SIZE_IN ((0x1ae2 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hsize_in uns, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_in uns, default = 1080 , pic vert size in unit: pixel
+#define AFBC_DEC_DEF_COLOR ((0x1ae3 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:20, def_color_y uns, default = 255, afbc dec y default setting value
+//Bit 19:10, def_color_u uns, default = 128, afbc dec u default setting value
+//Bit 9: 0, def_color_v uns, default = 128, afbc dec v default setting value
+#define AFBC_CONV_CTRL ((0x1ae4 << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13:12, fmt_mode uns, default = 2, 0:yuv444 1:yuv422 2:yuv420
+//Bit 11: 0, conv_lbuf_len uns, default = 256, unit=16 pixel need to set = 2^n
+#define AFBC_LBUF_DEPTH ((0x1ae5 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, dec_lbuf_depth uns, default = 128; // unit= 8 pixel
+//Bit 15:12, reserved
+//Bit 11:0, mif_lbuf_depth uns, default = 128;
+#define AFBC_HEAD_BADDR ((0x1ae6 << 2) + 0xff000000)
+//Bit 31:0, mif_info_baddr uns, default = 32'h0;
+#define AFBC_BODY_BADDR ((0x1ae7 << 2) + 0xff000000)
+//Bit 31:0, mif_data_baddr uns, default = 32'h00010000;
+#define AFBC_SIZE_OUT ((0x1ae8 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, hsize_out uns, default = 1920 ; // unit: 1 pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_out uns, default = 1080 ; // unit: 1 pixel
+#define AFBC_OUT_YSCOPE ((0x1ae9 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, out_vert_bgn uns, default = 0 ; // unit: 1 pixel
+//Bit 15:13, reserved
+//Bit 12:0, out_vert_end uns, default = 1079 ; // unit: 1 pixel
+#define AFBC_STAT ((0x1aea << 2) + 0xff000000)
+//Bit 31:0, ro_dbg_top_info uns,
+#define AFBC_VD_CFMT_CTRL ((0x1aeb << 2) + 0xff000000)
+//Bit 31 cfmt_gclk_bit_dis uns, default = 0 ; // it true, disable clock, otherwise enable clock
+//Bit 30 cfmt_soft_rst_bit uns, default = 0 ; // soft rst bit
+//Bit 29 reserved
+//Bit 28 chfmt_rpt_pix uns, default = 0 ; // if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
+//Bit 27:24 chfmt_ini_phase uns, default = 0 ; // horizontal formatter initial phase
+//Bit 23 chfmt_rpt_p0_en uns, default = 0 ; // horizontal formatter repeat pixel 0 enable
+//Bit 22:21 chfmt_yc_ratio uns, default = 0 ; // horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
+//Bit 20 chfmt_en uns, default = 0 ; // horizontal formatter enable
+//Bit 19 cvfmt_phase0_always_en uns, default = 0 ; //if true, always use phase0 while vertical formater, meaning always
+// repeat data, no interpolation
+//Bit 18 cvfmt_rpt_last_dis uns, default = 0 ; //if true, disable vertical formatter chroma repeat last line
+//Bit 17 cvfmt_phase0_nrpt_en uns, default = 0 ; //veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable
+//Bit 16 cvfmt_rpt_line0_en uns, default = 0 ; //veritcal formatter repeat line 0 enable
+//Bit 15:12 cvfmt_skip_line_num uns, default = 0 ; //vertical formatter skip line num at the beginning
+//Bit 11:8 cvfmt_ini_phase uns, default = 0 ; //vertical formatter initial phase
+//Bit 7:1 cvfmt_phase_step uns, default = 0 ; //vertical formatter phase step (3.4)
+//Bit 0 cvfmt_en uns, default = 0 ; //vertical formatter enable
+#define AFBC_VD_CFMT_W ((0x1aec << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 chfmt_w uns, default = 0 ;horizontal formatter width
+//Bit 15:13 reserved
+//Bit 12:0 cvfmt_w uns, default = 0 ;vertical formatter width
+#define AFBC_MIF_HOR_SCOPE ((0x1aed << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, mif_blk_bgn_h uns, default = 0 ; // unit: 32 pixel/block hor
+//Bit 15:10, reserved
+//Bit 9: 0, mif_blk_end_h uns, default = 59 ; // unit: 32 pixel/block hor
+#define AFBC_MIF_VER_SCOPE ((0x1aee << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, mif_blk_bgn_v uns, default = 0 ; // unit: 32 pixel/block ver
+//Bit 15:12, reserved
+//Bit 11: 0, mif_blk_end_v uns, default = 269; // unit: 32 pixel/block ver
+#define AFBC_PIXEL_HOR_SCOPE ((0x1aef << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, dec_pixel_bgn_h uns, default = 0 ; // unit: pixel
+//Bit 15:13, reserved
+//Bit 12: 0, dec_pixel_end_h uns, default = 1919 ; // unit: pixel
+#define AFBC_PIXEL_VER_SCOPE ((0x1af0 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, dec_pixel_bgn_v uns, default = 0 ; // unit: pixel
+//Bit 15:13, reserved
+//Bit 12: 0, dec_pixel_end_v uns, default = 1079 ; // unit: pixel
+#define AFBC_VD_CFMT_H ((0x1af1 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12:0 cfmt_h uns, default = 142 ; //vertical formatter height
+#define AFBCDEC_IQUANT_ENABLE ((0x1af2 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_quant_expand_en_1 //unsigned, RW, enable for quantization value expansion
+//Bit 10 reg_quant_expand_en_0 //unsigned, RW, enable for quantization value expansion
+//Bit 9: 8 reg_bcleav_ofst //signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1;
+//Bit 7: 5 reserved
+//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy
+//Bit 3: 1 reserved
+//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy
+#define AFBCDEC_IQUANT_LUT_1 ((0x1af3 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDEC_IQUANT_LUT_2 ((0x1af4 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDEC_IQUANT_LUT_3 ((0x1af5 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDEC_IQUANT_LUT_4 ((0x1af6 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: afbc_dec_regs.h
+//
+//
+// Closing file: vregs_clk2.h
+//
+//
+// Reading file: venc_regs.h
+//
+//===========================================================================
+// Video Interface Registers 0xa00 - 0xbff
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VENC_VCBUS_BASE = 0x1b
+// -----------------------------------------------
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 0 -- vfifo2vd_en
+#define ENCP_VFIFO2VD_CTL ((0x1b58 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCP_VFIFO2VD_PIXEL_START ((0x1b59 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCP_VFIFO2VD_PIXEL_END ((0x1b5a << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCP_VFIFO2VD_LINE_TOP_START ((0x1b5b << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCP_VFIFO2VD_LINE_TOP_END ((0x1b5c << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCP_VFIFO2VD_LINE_BOT_START ((0x1b5d << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCP_VFIFO2VD_LINE_BOT_END ((0x1b5e << 2) + 0xff000000)
+// Route the hsync and vsync signals round the chip. There are three
+// sources and users of these signals: VIU, internal video encoder, and
+// the pins on the chip. Some muxing is still being done in the VIU. It
+// was not moved to the venc module so that the same exact VIU code could
+// be used both in Twister and Twister2000.
+// Bit 2: venc_sync_source (1=>pins, 0=>viu)
+// Bit 1: viu_sync_source (1=>pins, 0=>venc)
+// Bit 0: vpins_sync_source (1=>venc, 0=>viu)
+#define VENC_SYNC_ROUTE ((0x1b60 << 2) + 0xff000000)
+ // encoder address space is assigned
+ // to the video encoder interface status
+ // register
+#define VENC_VIDEO_EXSRC ((0x1b61 << 2) + 0xff000000)
+#define VENC_DVI_SETTING ((0x1b62 << 2) + 0xff000000)
+#define VENC_C656_CTRL ((0x1b63 << 2) + 0xff000000)
+#define VENC_UPSAMPLE_CTRL0 ((0x1b64 << 2) + 0xff000000)
+#define VENC_UPSAMPLE_CTRL1 ((0x1b65 << 2) + 0xff000000)
+#define VENC_UPSAMPLE_CTRL2 ((0x1b66 << 2) + 0xff000000)
+// Invert control for tcon output
+// bit[15:14] -- vsync, hsync,
+// bit[13:0] -- oev3, oev2, cpv2, cph3, cph2, cph1, oeh, vcom, stv2, stv1, cpv1, oev1, sth1, sth2
+#define TCON_INVERT_CTL ((0x1b67 << 2) + 0xff000000)
+#define VENC_VIDEO_PROG_MODE ((0x1b68 << 2) + 0xff000000)
+//---- Venc pixel/line info
+#define VENC_ENCI_LINE ((0x1b69 << 2) + 0xff000000)
+#define VENC_ENCI_PIXEL ((0x1b6a << 2) + 0xff000000)
+#define VENC_ENCP_LINE ((0x1b6b << 2) + 0xff000000)
+#define VENC_ENCP_PIXEL ((0x1b6c << 2) + 0xff000000)
+//---- Status
+#define VENC_STATA ((0x1b6d << 2) + 0xff000000)
+//---- Interrupt setting
+#define VENC_INTCTRL ((0x1b6e << 2) + 0xff000000)
+#define VENC_INTFLAG ((0x1b6f << 2) + 0xff000000)
+//--------- Video test configuration
+#define VENC_VIDEO_TST_EN ((0x1b70 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_MDSEL ((0x1b71 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_Y ((0x1b72 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_CB ((0x1b73 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_CR ((0x1b74 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_CLRBAR_STRT ((0x1b75 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_CLRBAR_WIDTH ((0x1b76 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_VDCNT_STSET ((0x1b77 << 2) + 0xff000000)
+//----- Video dac setting
+#define VENC_VDAC_DACSEL0 ((0x1b78 << 2) + 0xff000000)
+#define VENC_VDAC_DACSEL1 ((0x1b79 << 2) + 0xff000000)
+#define VENC_VDAC_DACSEL2 ((0x1b7a << 2) + 0xff000000)
+#define VENC_VDAC_DACSEL3 ((0x1b7b << 2) + 0xff000000)
+#define VENC_VDAC_DACSEL4 ((0x1b7c << 2) + 0xff000000)
+#define VENC_VDAC_DACSEL5 ((0x1b7d << 2) + 0xff000000)
+#define VENC_VDAC_SETTING ((0x1b7e << 2) + 0xff000000)
+#define VENC_VDAC_TST_VAL ((0x1b7f << 2) + 0xff000000)
+#define VENC_VDAC_DAC0_GAINCTRL ((0x1bf0 << 2) + 0xff000000)
+#define VENC_VDAC_DAC0_OFFSET ((0x1bf1 << 2) + 0xff000000)
+#define VENC_VDAC_DAC1_GAINCTRL ((0x1bf2 << 2) + 0xff000000)
+#define VENC_VDAC_DAC1_OFFSET ((0x1bf3 << 2) + 0xff000000)
+#define VENC_VDAC_DAC2_GAINCTRL ((0x1bf4 << 2) + 0xff000000)
+#define VENC_VDAC_DAC2_OFFSET ((0x1bf5 << 2) + 0xff000000)
+#define VENC_VDAC_DAC3_GAINCTRL ((0x1bf6 << 2) + 0xff000000)
+#define VENC_VDAC_DAC3_OFFSET ((0x1bf7 << 2) + 0xff000000)
+#define VENC_VDAC_DAC4_GAINCTRL ((0x1bf8 << 2) + 0xff000000)
+#define VENC_VDAC_DAC4_OFFSET ((0x1bf9 << 2) + 0xff000000)
+#define VENC_VDAC_DAC5_GAINCTRL ((0x1bfa << 2) + 0xff000000)
+#define VENC_VDAC_DAC5_OFFSET ((0x1bfb << 2) + 0xff000000)
+#define VENC_VDAC_FIFO_CTRL ((0x1bfc << 2) + 0xff000000)
+#define ENCL_TCON_INVERT_CTL ((0x1bfd << 2) + 0xff000000)
+//
+// Closing file: venc_regs.h
+//
+//
+// Reading file: enc480p_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+// Video Encoder 480p Registers 0xb80 - 0xbef
+//===========================================================================
+//-------- Video basic setting
+#define ENCP_VIDEO_EN ((0x1b80 << 2) + 0xff000000)
+#define ENCP_VIDEO_SYNC_MODE ((0x1b81 << 2) + 0xff000000)
+#define ENCP_MACV_EN ((0x1b82 << 2) + 0xff000000)
+#define ENCP_VIDEO_Y_SCL ((0x1b83 << 2) + 0xff000000)
+#define ENCP_VIDEO_PB_SCL ((0x1b84 << 2) + 0xff000000)
+#define ENCP_VIDEO_PR_SCL ((0x1b85 << 2) + 0xff000000)
+#define ENCP_VIDEO_SYNC_SCL ((0x1b86 << 2) + 0xff000000)
+#define ENCP_VIDEO_MACV_SCL ((0x1b87 << 2) + 0xff000000)
+#define ENCP_VIDEO_Y_OFFST ((0x1b88 << 2) + 0xff000000)
+#define ENCP_VIDEO_PB_OFFST ((0x1b89 << 2) + 0xff000000)
+#define ENCP_VIDEO_PR_OFFST ((0x1b8a << 2) + 0xff000000)
+#define ENCP_VIDEO_SYNC_OFFST ((0x1b8b << 2) + 0xff000000)
+#define ENCP_VIDEO_MACV_OFFST ((0x1b8c << 2) + 0xff000000)
+//----- Video mode
+#define ENCP_VIDEO_MODE ((0x1b8d << 2) + 0xff000000)
+#define ENCP_VIDEO_MODE_ADV ((0x1b8e << 2) + 0xff000000)
+//--------------- Debug pins
+#define ENCP_DBG_PX_RST ((0x1b90 << 2) + 0xff000000)
+#define ENCP_DBG_LN_RST ((0x1b91 << 2) + 0xff000000)
+#define ENCP_DBG_PX_INT ((0x1b92 << 2) + 0xff000000)
+#define ENCP_DBG_LN_INT ((0x1b93 << 2) + 0xff000000)
+//----------- Video Advanced setting
+#define ENCP_VIDEO_YFP1_HTIME ((0x1b94 << 2) + 0xff000000)
+#define ENCP_VIDEO_YFP2_HTIME ((0x1b95 << 2) + 0xff000000)
+#define ENCP_VIDEO_YC_DLY ((0x1b96 << 2) + 0xff000000)
+#define ENCP_VIDEO_MAX_PXCNT ((0x1b97 << 2) + 0xff000000)
+#define ENCP_VIDEO_HSPULS_BEGIN ((0x1b98 << 2) + 0xff000000)
+#define ENCP_VIDEO_HSPULS_END ((0x1b99 << 2) + 0xff000000)
+#define ENCP_VIDEO_HSPULS_SWITCH ((0x1b9a << 2) + 0xff000000)
+#define ENCP_VIDEO_VSPULS_BEGIN ((0x1b9b << 2) + 0xff000000)
+#define ENCP_VIDEO_VSPULS_END ((0x1b9c << 2) + 0xff000000)
+#define ENCP_VIDEO_VSPULS_BLINE ((0x1b9d << 2) + 0xff000000)
+#define ENCP_VIDEO_VSPULS_ELINE ((0x1b9e << 2) + 0xff000000)
+#define ENCP_VIDEO_EQPULS_BEGIN ((0x1b9f << 2) + 0xff000000)
+#define ENCP_VIDEO_EQPULS_END ((0x1ba0 << 2) + 0xff000000)
+#define ENCP_VIDEO_EQPULS_BLINE ((0x1ba1 << 2) + 0xff000000)
+#define ENCP_VIDEO_EQPULS_ELINE ((0x1ba2 << 2) + 0xff000000)
+#define ENCP_VIDEO_HAVON_END ((0x1ba3 << 2) + 0xff000000)
+#define ENCP_VIDEO_HAVON_BEGIN ((0x1ba4 << 2) + 0xff000000)
+#define ENCP_VIDEO_VAVON_ELINE ((0x1baf << 2) + 0xff000000)
+#define ENCP_VIDEO_VAVON_BLINE ((0x1ba6 << 2) + 0xff000000)
+#define ENCP_VIDEO_HSO_BEGIN ((0x1ba7 << 2) + 0xff000000)
+#define ENCP_VIDEO_HSO_END ((0x1ba8 << 2) + 0xff000000)
+#define ENCP_VIDEO_VSO_BEGIN ((0x1ba9 << 2) + 0xff000000)
+#define ENCP_VIDEO_VSO_END ((0x1baa << 2) + 0xff000000)
+#define ENCP_VIDEO_VSO_BLINE ((0x1bab << 2) + 0xff000000)
+#define ENCP_VIDEO_VSO_ELINE ((0x1bac << 2) + 0xff000000)
+#define ENCP_VIDEO_SYNC_WAVE_CURVE ((0x1bad << 2) + 0xff000000)
+#define ENCP_VIDEO_MAX_LNCNT ((0x1bae << 2) + 0xff000000)
+#define ENCP_VIDEO_SY_VAL ((0x1bb0 << 2) + 0xff000000)
+#define ENCP_VIDEO_SY2_VAL ((0x1bb1 << 2) + 0xff000000)
+#define ENCP_VIDEO_BLANKY_VAL ((0x1bb2 << 2) + 0xff000000)
+#define ENCP_VIDEO_BLANKPB_VAL ((0x1bb3 << 2) + 0xff000000)
+#define ENCP_VIDEO_BLANKPR_VAL ((0x1bb4 << 2) + 0xff000000)
+#define ENCP_VIDEO_HOFFST ((0x1bb5 << 2) + 0xff000000)
+#define ENCP_VIDEO_VOFFST ((0x1bb6 << 2) + 0xff000000)
+#define ENCP_VIDEO_RGB_CTRL ((0x1bb7 << 2) + 0xff000000)
+#define ENCP_VIDEO_FILT_CTRL ((0x1bb8 << 2) + 0xff000000)
+#define ENCP_VIDEO_OFLD_VPEQ_OFST ((0x1bb9 << 2) + 0xff000000)
+#define ENCP_VIDEO_OFLD_VOAV_OFST ((0x1bba << 2) + 0xff000000)
+#define ENCP_VIDEO_MATRIX_CB ((0x1bbb << 2) + 0xff000000)
+#define ENCP_VIDEO_MATRIX_CR ((0x1bbc << 2) + 0xff000000)
+#define ENCP_VIDEO_RGBIN_CTRL ((0x1bbd << 2) + 0xff000000)
+//------------------Macrovision advanced setting
+#define ENCP_MACV_BLANKY_VAL ((0x1bc0 << 2) + 0xff000000)
+#define ENCP_MACV_MAXY_VAL ((0x1bc1 << 2) + 0xff000000)
+#define ENCP_MACV_1ST_PSSYNC_STRT ((0x1bc2 << 2) + 0xff000000)
+#define ENCP_MACV_PSSYNC_STRT ((0x1bc3 << 2) + 0xff000000)
+#define ENCP_MACV_AGC_STRT ((0x1bc4 << 2) + 0xff000000)
+#define ENCP_MACV_AGC_END ((0x1bc5 << 2) + 0xff000000)
+#define ENCP_MACV_WAVE_END ((0x1bc6 << 2) + 0xff000000)
+#define ENCP_MACV_STRTLINE ((0x1bc7 << 2) + 0xff000000)
+#define ENCP_MACV_ENDLINE ((0x1bc8 << 2) + 0xff000000)
+#define ENCP_MACV_TS_CNT_MAX_L ((0x1bc9 << 2) + 0xff000000)
+#define ENCP_MACV_TS_CNT_MAX_H ((0x1bca << 2) + 0xff000000)
+#define ENCP_MACV_TIME_DOWN ((0x1bcb << 2) + 0xff000000)
+#define ENCP_MACV_TIME_LO ((0x1bcc << 2) + 0xff000000)
+#define ENCP_MACV_TIME_UP ((0x1bcd << 2) + 0xff000000)
+#define ENCP_MACV_TIME_RST ((0x1bce << 2) + 0xff000000)
+//---------------- VBI control -------------------
+#define ENCP_VBI_CTRL ((0x1bd0 << 2) + 0xff000000)
+#define ENCP_VBI_SETTING ((0x1bd1 << 2) + 0xff000000)
+#define ENCP_VBI_BEGIN ((0x1bd2 << 2) + 0xff000000)
+#define ENCP_VBI_WIDTH ((0x1bd3 << 2) + 0xff000000)
+#define ENCP_VBI_HVAL ((0x1bd4 << 2) + 0xff000000)
+#define ENCP_VBI_DATA0 ((0x1bd5 << 2) + 0xff000000)
+#define ENCP_VBI_DATA1 ((0x1bd6 << 2) + 0xff000000)
+//----------------C656 OUT Control------------- Grant
+#define C656_HS_ST ((0x1be0 << 2) + 0xff000000)
+#define C656_HS_ED ((0x1be1 << 2) + 0xff000000)
+#define C656_VS_LNST_E ((0x1be2 << 2) + 0xff000000)
+#define C656_VS_LNST_O ((0x1be3 << 2) + 0xff000000)
+#define C656_VS_LNED_E ((0x1be4 << 2) + 0xff000000)
+#define C656_VS_LNED_O ((0x1be5 << 2) + 0xff000000)
+#define C656_FS_LNST ((0x1be6 << 2) + 0xff000000)
+#define C656_FS_LNED ((0x1be7 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: enc480p_regs.h
+//
+//
+// Reading file: enci_regs.h
+//
+//===========================================================================
+// Video Interface Registers 0xb00 - 0xb57
+//===========================================================================
+#define ENCI_VIDEO_MODE ((0x1b00 << 2) + 0xff000000)
+#define ENCI_VIDEO_MODE_ADV ((0x1b01 << 2) + 0xff000000)
+#define ENCI_VIDEO_FSC_ADJ ((0x1b02 << 2) + 0xff000000)
+#define ENCI_VIDEO_BRIGHT ((0x1b03 << 2) + 0xff000000)
+#define ENCI_VIDEO_CONT ((0x1b04 << 2) + 0xff000000)
+#define ENCI_VIDEO_SAT ((0x1b05 << 2) + 0xff000000)
+#define ENCI_VIDEO_HUE ((0x1b06 << 2) + 0xff000000)
+#define ENCI_VIDEO_SCH ((0x1b07 << 2) + 0xff000000)
+#define ENCI_SYNC_MODE ((0x1b08 << 2) + 0xff000000)
+#define ENCI_SYNC_CTRL ((0x1b09 << 2) + 0xff000000)
+#define ENCI_SYNC_HSO_BEGIN ((0x1b0a << 2) + 0xff000000)
+#define ENCI_SYNC_HSO_END ((0x1b0b << 2) + 0xff000000)
+#define ENCI_SYNC_VSO_EVN ((0x1b0c << 2) + 0xff000000)
+#define ENCI_SYNC_VSO_ODD ((0x1b0d << 2) + 0xff000000)
+#define ENCI_SYNC_VSO_EVNLN ((0x1b0e << 2) + 0xff000000)
+#define ENCI_SYNC_VSO_ODDLN ((0x1b0f << 2) + 0xff000000)
+#define ENCI_SYNC_HOFFST ((0x1b10 << 2) + 0xff000000)
+#define ENCI_SYNC_VOFFST ((0x1b11 << 2) + 0xff000000)
+#define ENCI_SYNC_ADJ ((0x1b12 << 2) + 0xff000000)
+#define ENCI_RGB_SETTING ((0x1b13 << 2) + 0xff000000)
+//`define ENCI_CMPN_MATRIX_CB 8'h14
+//`define ENCI_CMPN_MATRIX_CR 8'h15
+#define ENCI_DE_H_BEGIN ((0x1b16 << 2) + 0xff000000)
+#define ENCI_DE_H_END ((0x1b17 << 2) + 0xff000000)
+#define ENCI_DE_V_BEGIN_EVEN ((0x1b18 << 2) + 0xff000000)
+#define ENCI_DE_V_END_EVEN ((0x1b19 << 2) + 0xff000000)
+#define ENCI_DE_V_BEGIN_ODD ((0x1b1a << 2) + 0xff000000)
+#define ENCI_DE_V_END_ODD ((0x1b1b << 2) + 0xff000000)
+#define ENCI_VBI_SETTING ((0x1b20 << 2) + 0xff000000)
+#define ENCI_VBI_CCDT_EVN ((0x1b21 << 2) + 0xff000000)
+#define ENCI_VBI_CCDT_ODD ((0x1b22 << 2) + 0xff000000)
+#define ENCI_VBI_CC525_LN ((0x1b23 << 2) + 0xff000000)
+#define ENCI_VBI_CC625_LN ((0x1b24 << 2) + 0xff000000)
+#define ENCI_VBI_WSSDT ((0x1b25 << 2) + 0xff000000)
+#define ENCI_VBI_WSS_LN ((0x1b26 << 2) + 0xff000000)
+#define ENCI_VBI_CGMSDT_L ((0x1b27 << 2) + 0xff000000)
+#define ENCI_VBI_CGMSDT_H ((0x1b28 << 2) + 0xff000000)
+#define ENCI_VBI_CGMS_LN ((0x1b29 << 2) + 0xff000000)
+#define ENCI_VBI_TTX_HTIME ((0x1b2a << 2) + 0xff000000)
+#define ENCI_VBI_TTX_LN ((0x1b2b << 2) + 0xff000000)
+#define ENCI_VBI_TTXDT0 ((0x1b2c << 2) + 0xff000000)
+#define ENCI_VBI_TTXDT1 ((0x1b2d << 2) + 0xff000000)
+#define ENCI_VBI_TTXDT2 ((0x1b2e << 2) + 0xff000000)
+#define ENCI_VBI_TTXDT3 ((0x1b2f << 2) + 0xff000000)
+#define ENCI_MACV_N0 ((0x1b30 << 2) + 0xff000000)
+#define ENCI_MACV_N1 ((0x1b31 << 2) + 0xff000000)
+#define ENCI_MACV_N2 ((0x1b32 << 2) + 0xff000000)
+#define ENCI_MACV_N3 ((0x1b33 << 2) + 0xff000000)
+#define ENCI_MACV_N4 ((0x1b34 << 2) + 0xff000000)
+#define ENCI_MACV_N5 ((0x1b35 << 2) + 0xff000000)
+#define ENCI_MACV_N6 ((0x1b36 << 2) + 0xff000000)
+#define ENCI_MACV_N7 ((0x1b37 << 2) + 0xff000000)
+#define ENCI_MACV_N8 ((0x1b38 << 2) + 0xff000000)
+#define ENCI_MACV_N9 ((0x1b39 << 2) + 0xff000000)
+#define ENCI_MACV_N10 ((0x1b3a << 2) + 0xff000000)
+#define ENCI_MACV_N11 ((0x1b3b << 2) + 0xff000000)
+#define ENCI_MACV_N12 ((0x1b3c << 2) + 0xff000000)
+#define ENCI_MACV_N13 ((0x1b3d << 2) + 0xff000000)
+#define ENCI_MACV_N14 ((0x1b3e << 2) + 0xff000000)
+#define ENCI_MACV_N15 ((0x1b3f << 2) + 0xff000000)
+#define ENCI_MACV_N16 ((0x1b40 << 2) + 0xff000000)
+#define ENCI_MACV_N17 ((0x1b41 << 2) + 0xff000000)
+#define ENCI_MACV_N18 ((0x1b42 << 2) + 0xff000000)
+#define ENCI_MACV_N19 ((0x1b43 << 2) + 0xff000000)
+#define ENCI_MACV_N20 ((0x1b44 << 2) + 0xff000000)
+#define ENCI_MACV_N21 ((0x1b45 << 2) + 0xff000000)
+#define ENCI_MACV_N22 ((0x1b46 << 2) + 0xff000000)
+//`define ENCI_MACV_P_AGC 8'h47
+#define ENCI_DBG_PX_RST ((0x1b48 << 2) + 0xff000000)
+#define ENCI_DBG_FLDLN_RST ((0x1b49 << 2) + 0xff000000)
+#define ENCI_DBG_PX_INT ((0x1b4a << 2) + 0xff000000)
+#define ENCI_DBG_FLDLN_INT ((0x1b4b << 2) + 0xff000000)
+#define ENCI_DBG_MAXPX ((0x1b4c << 2) + 0xff000000)
+#define ENCI_DBG_MAXLN ((0x1b4d << 2) + 0xff000000)
+#define ENCI_MACV_MAX_AMP ((0x1b50 << 2) + 0xff000000)
+#define ENCI_MACV_PULSE_LO ((0x1b51 << 2) + 0xff000000)
+#define ENCI_MACV_PULSE_HI ((0x1b52 << 2) + 0xff000000)
+#define ENCI_MACV_BKP_MAX ((0x1b53 << 2) + 0xff000000)
+#define ENCI_CFILT_CTRL ((0x1b54 << 2) + 0xff000000)
+#define ENCI_CFILT7 ((0x1b55 << 2) + 0xff000000)
+#define ENCI_YC_DELAY ((0x1b56 << 2) + 0xff000000)
+#define ENCI_VIDEO_EN ((0x1b57 << 2) + 0xff000000)
+//
+// Closing file: enci_regs.h
+//
+//
+// Reading file: venc2_regs.h
+//
+//===========================================================================
+// Venc Registers (Cont.) 0xc00 - 0xcff (VENC registers 0xc00 - 0xcef)
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VENC2_VCBUS_BASE = 0x1c
+// -----------------------------------------------
+// Program video control signals from ENCI core to DVI/HDMI interface
+#define ENCI_DVI_HSO_BEGIN ((0x1c00 << 2) + 0xff000000)
+#define ENCI_DVI_HSO_END ((0x1c01 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_BLINE_EVN ((0x1c02 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_BLINE_ODD ((0x1c03 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_ELINE_EVN ((0x1c04 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_ELINE_ODD ((0x1c05 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_BEGIN_EVN ((0x1c06 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_BEGIN_ODD ((0x1c07 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_END_EVN ((0x1c08 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_END_ODD ((0x1c09 << 2) + 0xff000000)
+// Define cmpt and cvbs cb/cr delay after ENCI chroma filters
+// Bit 15:12 RW, enci_cb_cvbs_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+// Bit 11: 8 RW, enci_cr_cvbs_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+// Bit 7: 4 RW, enci_cb_cmpt_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+// Bit 3: 0 RW, enci_cr_cmpt_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+#define ENCI_CFILT_CTRL2 ((0x1c0a << 2) + 0xff000000)
+#define ENCI_DACSEL_0 ((0x1c0b << 2) + 0xff000000)
+#define ENCI_DACSEL_1 ((0x1c0c << 2) + 0xff000000)
+#define ENCP_DACSEL_0 ((0x1c0d << 2) + 0xff000000)
+#define ENCP_DACSEL_1 ((0x1c0e << 2) + 0xff000000)
+#define ENCP_MAX_LINE_SWITCH_POINT ((0x1c0f << 2) + 0xff000000)
+#define ENCI_TST_EN ((0x1c10 << 2) + 0xff000000)
+#define ENCI_TST_MDSEL ((0x1c11 << 2) + 0xff000000)
+#define ENCI_TST_Y ((0x1c12 << 2) + 0xff000000)
+#define ENCI_TST_CB ((0x1c13 << 2) + 0xff000000)
+#define ENCI_TST_CR ((0x1c14 << 2) + 0xff000000)
+#define ENCI_TST_CLRBAR_STRT ((0x1c15 << 2) + 0xff000000)
+#define ENCI_TST_CLRBAR_WIDTH ((0x1c16 << 2) + 0xff000000)
+#define ENCI_TST_VDCNT_STSET ((0x1c17 << 2) + 0xff000000)
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 7 -- vfifo2vd_drop
+// bit 6:1 -- vfifo2vd_delay
+// bit 0 -- vfifo2vd_en
+#define ENCI_VFIFO2VD_CTL ((0x1c18 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCI_VFIFO2VD_PIXEL_START ((0x1c19 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCI_VFIFO2VD_PIXEL_END ((0x1c1a << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCI_VFIFO2VD_LINE_TOP_START ((0x1c1b << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCI_VFIFO2VD_LINE_TOP_END ((0x1c1c << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCI_VFIFO2VD_LINE_BOT_START ((0x1c1d << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCI_VFIFO2VD_LINE_BOT_END ((0x1c1e << 2) + 0xff000000)
+#define ENCI_VFIFO2VD_CTL2 ((0x1c1f << 2) + 0xff000000)
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 7 -- vfifo2vd_drop
+// bit 6:1 -- vfifo2vd_delay
+// bit 0 -- vfifo2vd_en
+#define ENCT_VFIFO2VD_CTL ((0x1c20 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCT_VFIFO2VD_PIXEL_START ((0x1c21 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCT_VFIFO2VD_PIXEL_END ((0x1c22 << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCT_VFIFO2VD_LINE_TOP_START ((0x1c23 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCT_VFIFO2VD_LINE_TOP_END ((0x1c24 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCT_VFIFO2VD_LINE_BOT_START ((0x1c25 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCT_VFIFO2VD_LINE_BOT_END ((0x1c26 << 2) + 0xff000000)
+#define ENCT_VFIFO2VD_CTL2 ((0x1c27 << 2) + 0xff000000)
+#define ENCT_TST_EN ((0x1c28 << 2) + 0xff000000)
+#define ENCT_TST_MDSEL ((0x1c29 << 2) + 0xff000000)
+#define ENCT_TST_Y ((0x1c2a << 2) + 0xff000000)
+#define ENCT_TST_CB ((0x1c2b << 2) + 0xff000000)
+#define ENCT_TST_CR ((0x1c2c << 2) + 0xff000000)
+#define ENCT_TST_CLRBAR_STRT ((0x1c2d << 2) + 0xff000000)
+#define ENCT_TST_CLRBAR_WIDTH ((0x1c2e << 2) + 0xff000000)
+#define ENCT_TST_VDCNT_STSET ((0x1c2f << 2) + 0xff000000)
+// Program video control signals from ENCP core to DVI/HDMI interface
+#define ENCP_DVI_HSO_BEGIN ((0x1c30 << 2) + 0xff000000)
+#define ENCP_DVI_HSO_END ((0x1c31 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_BLINE_EVN ((0x1c32 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_BLINE_ODD ((0x1c33 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_ELINE_EVN ((0x1c34 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_ELINE_ODD ((0x1c35 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_BEGIN_EVN ((0x1c36 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_BEGIN_ODD ((0x1c37 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_END_EVN ((0x1c38 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_END_ODD ((0x1c39 << 2) + 0xff000000)
+#define ENCP_DE_H_BEGIN ((0x1c3a << 2) + 0xff000000)
+#define ENCP_DE_H_END ((0x1c3b << 2) + 0xff000000)
+#define ENCP_DE_V_BEGIN_EVEN ((0x1c3c << 2) + 0xff000000)
+#define ENCP_DE_V_END_EVEN ((0x1c3d << 2) + 0xff000000)
+#define ENCP_DE_V_BEGIN_ODD ((0x1c3e << 2) + 0xff000000)
+#define ENCP_DE_V_END_ODD ((0x1c3f << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCI_SYNC_LINE_LENGTH ((0x1c40 << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCI_SYNC_PIXEL_EN ((0x1c41 << 2) + 0xff000000)
+// Bit 15 - enci_sync_enable
+// Bit 14 - encp_sync_enable
+// Bit 13 - enct_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCI_SYNC_TO_LINE_EN ((0x1c42 << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCI_SYNC_TO_PIXEL ((0x1c43 << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCP_SYNC_LINE_LENGTH ((0x1c44 << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCP_SYNC_PIXEL_EN ((0x1c45 << 2) + 0xff000000)
+// Bit 15 - enci_sync_enable
+// Bit 14 - encp_sync_enable
+// Bit 13 - enct_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCP_SYNC_TO_LINE_EN ((0x1c46 << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCP_SYNC_TO_PIXEL ((0x1c47 << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCT_SYNC_LINE_LENGTH ((0x1c48 << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCT_SYNC_PIXEL_EN ((0x1c49 << 2) + 0xff000000)
+// Bit 15 - enci_sync_enable
+// Bit 14 - encp_sync_enable
+// Bit 13 - enct_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCT_SYNC_TO_LINE_EN ((0x1c4a << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCT_SYNC_TO_PIXEL ((0x1c4b << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCL_SYNC_LINE_LENGTH ((0x1c4c << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCL_SYNC_PIXEL_EN ((0x1c4d << 2) + 0xff000000)
+// Bit 15 - enci_sync_enable
+// Bit 14 - encp_sync_enable
+// Bit 13 - enct_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCL_SYNC_TO_LINE_EN ((0x1c4e << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCL_SYNC_TO_PIXEL ((0x1c4f << 2) + 0xff000000)
+// bit 3 cfg_encp_lcd_scaler_bypass. 1=Do not scale LCD input data;
+// 0=Scale LCD input data to y [16*4,235*4], c [16*4,240*4].
+// bit 2 cfg_encp_vadj_scaler_bypass. 1=Do not scale data to enc480p_vadj;
+// 0=Scale enc480p_vadj input data to y [16*4,235*4], c [16*4,240*4].
+// bit 1 cfg_vfifo2vd_out_scaler_bypass. 1=Do not scale vfifo2vd's output vdata;
+// 0=Scale vfifo2vd's output vdata to y [16,235], c [16,240].
+// bit 0 cfg_vfifo_din_full_range. 1=Data from viu fifo is full range [0,1023];
+// 0=Data from viu fifo is y [16*4,235*4], c [16*4,240*4].
+#define ENCP_VFIFO2VD_CTL2 ((0x1c50 << 2) + 0xff000000)
+// bit 15:1 Reserved.
+// bit 0 cfg_int_dvi_sel_rgb. Applicable for using on-chip hdmi tx module only. This bit controls correct bit-mapping from
+// Venc to hdmi_tx depending on whether YCbCr or RGB mode.
+// 1=Map data bit from Venc to hdmi_tx for RGB mode;
+// 0=Default. Map data bit from Venc to hdmi_tx for YCbCr mode.
+#define VENC_DVI_SETTING_MORE ((0x1c51 << 2) + 0xff000000)
+#define VENC_VDAC_DAC4_FILT_CTRL0 ((0x1c54 << 2) + 0xff000000)
+#define VENC_VDAC_DAC4_FILT_CTRL1 ((0x1c55 << 2) + 0xff000000)
+#define VENC_VDAC_DAC5_FILT_CTRL0 ((0x1c56 << 2) + 0xff000000)
+#define VENC_VDAC_DAC5_FILT_CTRL1 ((0x1c57 << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC_VDAC_DAC0_FILT_CTRL0 ((0x1c58 << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC_VDAC_DAC0_FILT_CTRL1 ((0x1c59 << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC_VDAC_DAC1_FILT_CTRL0 ((0x1c5a << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC_VDAC_DAC1_FILT_CTRL1 ((0x1c5b << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC_VDAC_DAC2_FILT_CTRL0 ((0x1c5c << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC_VDAC_DAC2_FILT_CTRL1 ((0x1c5d << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC_VDAC_DAC3_FILT_CTRL0 ((0x1c5e << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC_VDAC_DAC3_FILT_CTRL1 ((0x1c5f << 2) + 0xff000000)
+//===========================================================================
+// ENCT registers
+#define ENCT_VIDEO_EN ((0x1c60 << 2) + 0xff000000)
+#define ENCT_VIDEO_Y_SCL ((0x1c61 << 2) + 0xff000000)
+#define ENCT_VIDEO_PB_SCL ((0x1c62 << 2) + 0xff000000)
+#define ENCT_VIDEO_PR_SCL ((0x1c63 << 2) + 0xff000000)
+#define ENCT_VIDEO_Y_OFFST ((0x1c64 << 2) + 0xff000000)
+#define ENCT_VIDEO_PB_OFFST ((0x1c65 << 2) + 0xff000000)
+#define ENCT_VIDEO_PR_OFFST ((0x1c66 << 2) + 0xff000000)
+//----- Video mode
+#define ENCT_VIDEO_MODE ((0x1c67 << 2) + 0xff000000)
+#define ENCT_VIDEO_MODE_ADV ((0x1c68 << 2) + 0xff000000)
+//--------------- Debug pins
+#define ENCT_DBG_PX_RST ((0x1c69 << 2) + 0xff000000)
+#define ENCT_DBG_LN_RST ((0x1c6a << 2) + 0xff000000)
+#define ENCT_DBG_PX_INT ((0x1c6b << 2) + 0xff000000)
+#define ENCT_DBG_LN_INT ((0x1c6c << 2) + 0xff000000)
+//----------- Video Advanced setting
+#define ENCT_VIDEO_YFP1_HTIME ((0x1c6d << 2) + 0xff000000)
+#define ENCT_VIDEO_YFP2_HTIME ((0x1c6e << 2) + 0xff000000)
+#define ENCT_VIDEO_YC_DLY ((0x1c6f << 2) + 0xff000000)
+#define ENCT_VIDEO_MAX_PXCNT ((0x1c70 << 2) + 0xff000000)
+#define ENCT_VIDEO_HAVON_END ((0x1c71 << 2) + 0xff000000)
+#define ENCT_VIDEO_HAVON_BEGIN ((0x1c72 << 2) + 0xff000000)
+#define ENCT_VIDEO_VAVON_ELINE ((0x1c73 << 2) + 0xff000000)
+#define ENCT_VIDEO_VAVON_BLINE ((0x1c74 << 2) + 0xff000000)
+#define ENCT_VIDEO_HSO_BEGIN ((0x1c75 << 2) + 0xff000000)
+#define ENCT_VIDEO_HSO_END ((0x1c76 << 2) + 0xff000000)
+#define ENCT_VIDEO_VSO_BEGIN ((0x1c77 << 2) + 0xff000000)
+#define ENCT_VIDEO_VSO_END ((0x1c78 << 2) + 0xff000000)
+#define ENCT_VIDEO_VSO_BLINE ((0x1c79 << 2) + 0xff000000)
+#define ENCT_VIDEO_VSO_ELINE ((0x1c7a << 2) + 0xff000000)
+#define ENCT_VIDEO_MAX_LNCNT ((0x1c7b << 2) + 0xff000000)
+#define ENCT_VIDEO_BLANKY_VAL ((0x1c7c << 2) + 0xff000000)
+#define ENCT_VIDEO_BLANKPB_VAL ((0x1c7d << 2) + 0xff000000)
+#define ENCT_VIDEO_BLANKPR_VAL ((0x1c7e << 2) + 0xff000000)
+#define ENCT_VIDEO_HOFFST ((0x1c7f << 2) + 0xff000000)
+#define ENCT_VIDEO_VOFFST ((0x1c80 << 2) + 0xff000000)
+#define ENCT_VIDEO_RGB_CTRL ((0x1c81 << 2) + 0xff000000)
+#define ENCT_VIDEO_FILT_CTRL ((0x1c82 << 2) + 0xff000000)
+#define ENCT_VIDEO_OFLD_VPEQ_OFST ((0x1c83 << 2) + 0xff000000)
+#define ENCT_VIDEO_OFLD_VOAV_OFST ((0x1c84 << 2) + 0xff000000)
+#define ENCT_VIDEO_MATRIX_CB ((0x1c85 << 2) + 0xff000000)
+#define ENCT_VIDEO_MATRIX_CR ((0x1c86 << 2) + 0xff000000)
+#define ENCT_VIDEO_RGBIN_CTRL ((0x1c87 << 2) + 0xff000000)
+#define ENCT_MAX_LINE_SWITCH_POINT ((0x1c88 << 2) + 0xff000000)
+#define ENCT_DACSEL_0 ((0x1c89 << 2) + 0xff000000)
+#define ENCT_DACSEL_1 ((0x1c8a << 2) + 0xff000000)
+#define ENCT_INBUF_CNTL0 ((0x1c8b << 2) + 0xff000000)
+#define ENCT_INBUF_CNTL1 ((0x1c8c << 2) + 0xff000000)
+#define ENCT_INBUF_CNT ((0x1c8d << 2) + 0xff000000)
+#define ENCT_INBUF_HOLD_CNT ((0x1c8e << 2) + 0xff000000)
+#define ENCT_INBUF_FIX_PIX_NUM ((0x1c8f << 2) + 0xff000000)
+//===========================================================================
+// For ENCL
+//===========================================================================
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 7 -- vfifo2vd_drop
+// bit 6:1 -- vfifo2vd_delay
+// bit 0 -- vfifo2vd_en
+#define ENCL_VFIFO2VD_CTL ((0x1c90 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCL_VFIFO2VD_PIXEL_START ((0x1c91 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCL_VFIFO2VD_PIXEL_END ((0x1c92 << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCL_VFIFO2VD_LINE_TOP_START ((0x1c93 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCL_VFIFO2VD_LINE_TOP_END ((0x1c94 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCL_VFIFO2VD_LINE_BOT_START ((0x1c95 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCL_VFIFO2VD_LINE_BOT_END ((0x1c96 << 2) + 0xff000000)
+#define ENCL_VFIFO2VD_CTL2 ((0x1c97 << 2) + 0xff000000)
+#define ENCL_TST_EN ((0x1c98 << 2) + 0xff000000)
+#define ENCL_TST_MDSEL ((0x1c99 << 2) + 0xff000000)
+#define ENCL_TST_Y ((0x1c9a << 2) + 0xff000000)
+#define ENCL_TST_CB ((0x1c9b << 2) + 0xff000000)
+#define ENCL_TST_CR ((0x1c9c << 2) + 0xff000000)
+#define ENCL_TST_CLRBAR_STRT ((0x1c9d << 2) + 0xff000000)
+#define ENCL_TST_CLRBAR_WIDTH ((0x1c9e << 2) + 0xff000000)
+#define ENCL_TST_VDCNT_STSET ((0x1c9f << 2) + 0xff000000)
+//===========================================================================
+// ENCL registers
+#define ENCL_VIDEO_EN ((0x1ca0 << 2) + 0xff000000)
+#define ENCL_VIDEO_Y_SCL ((0x1ca1 << 2) + 0xff000000)
+#define ENCL_VIDEO_PB_SCL ((0x1ca2 << 2) + 0xff000000)
+#define ENCL_VIDEO_PR_SCL ((0x1ca3 << 2) + 0xff000000)
+#define ENCL_VIDEO_Y_OFFST ((0x1ca4 << 2) + 0xff000000)
+#define ENCL_VIDEO_PB_OFFST ((0x1ca5 << 2) + 0xff000000)
+#define ENCL_VIDEO_PR_OFFST ((0x1ca6 << 2) + 0xff000000)
+//----- Video mode
+#define ENCL_VIDEO_MODE ((0x1ca7 << 2) + 0xff000000)
+#define ENCL_VIDEO_MODE_ADV ((0x1ca8 << 2) + 0xff000000)
+//--------------- Debug pins
+#define ENCL_DBG_PX_RST ((0x1ca9 << 2) + 0xff000000)
+#define ENCL_DBG_LN_RST ((0x1caa << 2) + 0xff000000)
+#define ENCL_DBG_PX_INT ((0x1cab << 2) + 0xff000000)
+#define ENCL_DBG_LN_INT ((0x1cac << 2) + 0xff000000)
+//----------- Video Advanced setting
+#define ENCL_VIDEO_YFP1_HTIME ((0x1cad << 2) + 0xff000000)
+#define ENCL_VIDEO_YFP2_HTIME ((0x1cae << 2) + 0xff000000)
+#define ENCL_VIDEO_YC_DLY ((0x1caf << 2) + 0xff000000)
+#define ENCL_VIDEO_MAX_PXCNT ((0x1cb0 << 2) + 0xff000000)
+#define ENCL_VIDEO_HAVON_END ((0x1cb1 << 2) + 0xff000000)
+#define ENCL_VIDEO_HAVON_BEGIN ((0x1cb2 << 2) + 0xff000000)
+#define ENCL_VIDEO_VAVON_ELINE ((0x1cb3 << 2) + 0xff000000)
+#define ENCL_VIDEO_VAVON_BLINE ((0x1cb4 << 2) + 0xff000000)
+#define ENCL_VIDEO_HSO_BEGIN ((0x1cb5 << 2) + 0xff000000)
+#define ENCL_VIDEO_HSO_END ((0x1cb6 << 2) + 0xff000000)
+#define ENCL_VIDEO_VSO_BEGIN ((0x1cb7 << 2) + 0xff000000)
+#define ENCL_VIDEO_VSO_END ((0x1cb8 << 2) + 0xff000000)
+#define ENCL_VIDEO_VSO_BLINE ((0x1cb9 << 2) + 0xff000000)
+#define ENCL_VIDEO_VSO_ELINE ((0x1cba << 2) + 0xff000000)
+#define ENCL_VIDEO_MAX_LNCNT ((0x1cbb << 2) + 0xff000000)
+#define ENCL_VIDEO_BLANKY_VAL ((0x1cbc << 2) + 0xff000000)
+#define ENCL_VIDEO_BLANKPB_VAL ((0x1cbd << 2) + 0xff000000)
+#define ENCL_VIDEO_BLANKPR_VAL ((0x1cbe << 2) + 0xff000000)
+#define ENCL_VIDEO_HOFFST ((0x1cbf << 2) + 0xff000000)
+#define ENCL_VIDEO_VOFFST ((0x1cc0 << 2) + 0xff000000)
+#define ENCL_VIDEO_RGB_CTRL ((0x1cc1 << 2) + 0xff000000)
+#define ENCL_VIDEO_FILT_CTRL ((0x1cc2 << 2) + 0xff000000)
+#define ENCL_VIDEO_OFLD_VPEQ_OFST ((0x1cc3 << 2) + 0xff000000)
+#define ENCL_VIDEO_OFLD_VOAV_OFST ((0x1cc4 << 2) + 0xff000000)
+#define ENCL_VIDEO_MATRIX_CB ((0x1cc5 << 2) + 0xff000000)
+#define ENCL_VIDEO_MATRIX_CR ((0x1cc6 << 2) + 0xff000000)
+#define ENCL_VIDEO_RGBIN_CTRL ((0x1cc7 << 2) + 0xff000000)
+#define ENCL_MAX_LINE_SWITCH_POINT ((0x1cc8 << 2) + 0xff000000)
+#define ENCL_DACSEL_0 ((0x1cc9 << 2) + 0xff000000)
+#define ENCL_DACSEL_1 ((0x1cca << 2) + 0xff000000)
+#define ENCT_VIDEO_H_PRE_DE_END ((0x1ccb << 2) + 0xff000000)
+#define ENCT_VIDEO_H_PRE_DE_BEGIN ((0x1ccc << 2) + 0xff000000)
+#define ENCT_VIDEO_V_PRE_DE_ELINE ((0x1ccd << 2) + 0xff000000)
+#define ENCT_VIDEO_V_PRE_DE_BLINE ((0x1cce << 2) + 0xff000000)
+#define ENCL_VIDEO_H_PRE_DE_END ((0x1ccf << 2) + 0xff000000)
+#define ENCL_VIDEO_H_PRE_DE_BEGIN ((0x1cd0 << 2) + 0xff000000)
+#define ENCL_VIDEO_V_PRE_DE_ELINE ((0x1cd1 << 2) + 0xff000000)
+#define ENCL_VIDEO_V_PRE_DE_BLINE ((0x1cd2 << 2) + 0xff000000)
+#define ENCL_INBUF_CNTL0 ((0x1cd3 << 2) + 0xff000000)
+#define ENCL_INBUF_CNTL1 ((0x1cd4 << 2) + 0xff000000)
+#define ENCL_INBUF_CNT ((0x1cd5 << 2) + 0xff000000)
+#define ENCL_INBUF_HOLD_CNT ((0x1cd6 << 2) + 0xff000000)
+#define ENCL_INBUF_FIX_PIX_NUM ((0x1cd7 << 2) + 0xff000000)
+//
+// Closing file: venc2_regs.h
+//
+//
+// Reading file: vpp_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: VPP_VCBUS_BASE = 0x1d
+// -----------------------------------------------
+#define VPP_VD1_SC_OFFSET 0x00 //just used in vpp_vd1_scale
+//===========================================================================
+// Video postprocesing Registers
+//===========================================================================
+// dummy data used in the VPP preblend and scaler
+// Bit 23:16 Y
+// Bit 15:8 CB
+// Bit 7:0 CR
+#define VPP_DUMMY_DATA ((0x1d00 << 2) + 0xff000000)
+//input line length used in VPP
+#define VPP_LINE_IN_LENGTH ((0x1d01 << 2) + 0xff000000)
+//input Picture height used in VPP
+#define VPP_PIC_IN_HEIGHT ((0x1d02 << 2) + 0xff000000)
+//Because there are many coefficients used in the vertical filter and horizontal filters,
+//indirect access the coefficients of vertical filter and horizontal filter is used.
+//For vertical filter, there are 33x4 coefficients
+//For horizontal filter, there are 33x4 coefficients
+//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
+//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
+//Bit 13 if true, vertical separated coef enable
+//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
+//Bit 8:7 type of index, 00: vertical coef, 01: vertical chroma coef: 10: horizontal coef, 11: resevered
+//Bit 6:0 coef index
+#define VPP_SCALE_COEF_IDX ((0x1d03 << 2) + 0xff000000)
+//coefficients for vertical filter and horizontal filter
+#define VPP_SCALE_COEF ((0x1d04 << 2) + 0xff000000)
+//these following registers are the absolute line address pointer for output divided screen
+//The output divided screen is shown in the following:
+//
+// -------------------------- <------ line zero
+// .
+// .
+// . region0 <---------- nonlinear region or nonscaling region
+// .
+// ---------------------------
+// --------------------------- <------ region1_startp
+// .
+// . region1 <---------- nonlinear region
+// .
+// .
+// ---------------------------
+// --------------------------- <------ region2_startp
+// .
+// . region2 <---------- linear region
+// .
+// .
+// ---------------------------
+// --------------------------- <------ region3_startp
+// .
+// . region3 <---------- nonlinear region
+// .
+// .
+// ---------------------------
+// --------------------------- <------ region4_startp
+// .
+// . region4 <---------- nonlinear region or nonoscaling region
+// .
+// .
+// --------------------------- <------ region4_endp
+//Bit 28:16 region1 startp
+//Bit 12:0 region2 startp
+#define VPP_VSC_REGION12_STARTP ((0x1d05 << 2) + 0xff000000)
+//Bit 28:16 region3 startp
+//Bit 12:0 region4 startp
+#define VPP_VSC_REGION34_STARTP ((0x1d06 << 2) + 0xff000000)
+#define VPP_VSC_REGION4_ENDP ((0x1d07 << 2) + 0xff000000)
+//vertical start phase step, (source/dest)*(2^24)
+//Bit 27:24 integer part
+//Bit 23:0 fraction part
+#define VPP_VSC_START_PHASE_STEP ((0x1d08 << 2) + 0xff000000)
+//vertical scaler region0 phase slope, Bit24 signed bit
+#define VPP_VSC_REGION0_PHASE_SLOPE ((0x1d09 << 2) + 0xff000000)
+//vertical scaler region1 phase slope, Bit24 signed bit
+#define VPP_VSC_REGION1_PHASE_SLOPE ((0x1d0a << 2) + 0xff000000)
+//vertical scaler region3 phase slope, Bit24 signed bit
+#define VPP_VSC_REGION3_PHASE_SLOPE ((0x1d0b << 2) + 0xff000000)
+//vertical scaler region4 phase slope, Bit24 signed bit
+#define VPP_VSC_REGION4_PHASE_SLOPE ((0x1d0c << 2) + 0xff000000)
+//Bit 18:17 double line mode, input/output line width of vscaler becomes 2X,
+// so only 2 line buffer in this case, use for 3D line by line interleave scaling
+// bit1 true, double the input width and half input height, bit0 true, change line buffer 2 lines instead of 4 lines
+//Bit 16 0: progressive output, 1: interlace output
+//Bit 15 vertical scaler output line0 in advance or not for bottom field
+//Bit 14:13 vertical scaler initial repeat line0 number for bottom field
+//Bit 11:8 vertical scaler initial receiving number for bottom field
+//Bit 7 vertical scaler output line0 in advance or not for top field
+//Bit 6:5 vertical scaler initial repeat line0 number for top field
+//Bit 3:0 vertical scaler initial receiving number for top field
+#define VPP_VSC_PHASE_CTRL ((0x1d0d << 2) + 0xff000000)
+//Bit 31:16 vertical scaler field initial phase for bottom field
+//Bit 15:0 vertical scaler field initial phase for top field
+#define VPP_VSC_INI_PHASE ((0x1d0e << 2) + 0xff000000)
+//Bit 28:16 region1 startp
+//Bit 12:0 region2 startp
+#define VPP_HSC_REGION12_STARTP ((0x1d10 << 2) + 0xff000000)
+//Bit 28:16 region3 startp
+//Bit 12:0 region4 startp
+#define VPP_HSC_REGION34_STARTP ((0x1d11 << 2) + 0xff000000)
+#define VPP_HSC_REGION4_ENDP ((0x1d12 << 2) + 0xff000000)
+//horizontal start phase step, (source/dest)*(2^24)
+//Bit 27:24 integer part
+//Bit 23:0 fraction part
+#define VPP_HSC_START_PHASE_STEP ((0x1d13 << 2) + 0xff000000)
+//horizontal scaler region0 phase slope, Bit24 signed bit
+#define VPP_HSC_REGION0_PHASE_SLOPE ((0x1d14 << 2) + 0xff000000)
+//horizontal scaler region1 phase slope, Bit24 signed bit
+#define VPP_HSC_REGION1_PHASE_SLOPE ((0x1d15 << 2) + 0xff000000)
+//horizontal scaler region3 phase slope, Bit24 signed bit
+#define VPP_HSC_REGION3_PHASE_SLOPE ((0x1d16 << 2) + 0xff000000)
+//horizontal scaler region4 phase slope, Bit24 signed bit
+#define VPP_HSC_REGION4_PHASE_SLOPE ((0x1d17 << 2) + 0xff000000)
+//Bit 22:21 horizontal scaler initial repeat pixel0 number0
+//Bit 19:16 horizontal scaler initial receiving number0
+//Bit 15:0 horizontal scaler top field initial phase0
+#define VPP_HSC_PHASE_CTRL ((0x1d18 << 2) + 0xff000000)
+// Bit 22 if true, divide VSC line length 2 as the HSC input length, othwise VSC length length is the same as the VSC line length,
+// just for special usage, more flexibility
+// Bit 21 if true, prevsc uses lin buffer, otherwise prevsc does not use line buffer, it should be same as prevsc_en
+// Bit 20 prehsc_en
+// Bit 19 prevsc_en
+// Bit 18 vsc_en
+// Bit 17 hsc_en
+// Bit 16 scale_top_en
+// Bit 15 video1 scale out enable
+// Bit 12 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for horizontal scaler
+// Bit 10:8 horizontal scaler bank length
+// Bit 5, vertical scaler phase field mode, if true, disable the opposite parity line output, more bandwith needed if output 1080i
+// Bit 4 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for vertical scaler
+// Bit 2:0 vertical scaler bank length
+#define VPP_SC_MISC ((0x1d19 << 2) + 0xff000000)
+// preblend video1 horizontal start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_PREBLEND_VD1_H_START_END ((0x1d1a << 2) + 0xff000000)
+// preblend video1 vertical start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_PREBLEND_VD1_V_START_END ((0x1d1b << 2) + 0xff000000)
+// postblend video1 horizontal start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_POSTBLEND_VD1_H_START_END ((0x1d1c << 2) + 0xff000000)
+// postblend video1 vertical start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_POSTBLEND_VD1_V_START_END ((0x1d1d << 2) + 0xff000000)
+// preblend/postblend video2 horizontal start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_BLEND_VD2_H_START_END ((0x1d1e << 2) + 0xff000000)
+// preblend/postblend video2 vertical start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_BLEND_VD2_V_START_END ((0x1d1f << 2) + 0xff000000)
+// preblend horizontal size
+#define VPP_PREBLEND_H_SIZE ((0x1d20 << 2) + 0xff000000)
+// postblend horizontal size
+#define VPP_POSTBLEND_H_SIZE ((0x1d21 << 2) + 0xff000000)
+//VPP hold lines
+//Bit 29:24
+//Bit 21:16
+//Bit 15:8 preblend hold lines
+//Bit 7:0 postblend hold lines
+#define VPP_HOLD_LINES ((0x1d22 << 2) + 0xff000000)
+//Bit 26 if true, automatic change post blend output to one color if field ==1
+//Bit 25 if true, change screen to one color value for preblender
+//Bit 24 if true, change screen to one color value for postblender
+// Bit 23:16 one color Y
+// Bit 15:8 one color Cb
+// Bit 7:0 one color Cr
+#define VPP_BLEND_ONECOLOR_CTRL ((0x1d23 << 2) + 0xff000000)
+//Read Only, VPP preblend current_x, current_y
+//Bit 28:16 current_x
+//Bit 12:0 current_y
+#define VPP_PREBLEND_CURRENT_XY ((0x1d24 << 2) + 0xff000000)
+//Read Only, VPP postblend current_x, current_y
+//Bit 28:16 current_x
+//Bit 12:0 current_y
+#define VPP_POSTBLEND_CURRENT_XY ((0x1d25 << 2) + 0xff000000)
+// Bit 31 vd1_bgosd_exchange_en for preblend
+// Bit 30 vd1_bgosd_exchange_en for postblend
+// Bit 28 color management enable
+// Bit 27, if true, vd2 use viu2 output as the input, otherwise use normal vd2 from memory
+// Bit 26:18, vd2 alpha
+// Bit 17, osd2 enable for preblend
+// Bit 16, osd1 enable for preblend
+// Bit 15, vd2 enable for preblend
+// Bit 14, vd1 enable for preblend
+// Bit 13, osd2 enable for postblend
+// Bit 12, osd1 enable for postblend
+// Bit 11, vd2 enable for postblend
+// Bit 10, vd1 enable for postblend
+// Bit 9, if true, osd1 is alpha premultipiled
+// Bit 8, if true, osd2 is alpha premultipiled
+// Bit 7, postblend module enable
+// Bit 6, preblend module enable
+// Bit 5, if true, osd2 foreground compared with osd1 in preblend
+// Bit 4, if true, osd2 foreground compared with osd1 in postblend
+// Bit 3,
+// Bit 2, if true, disable resetting async fifo every vsync, otherwise every vsync
+// the aync fifo will be reseted.
+// Bit 1,
+// Bit 0 if true, the output result of VPP is saturated
+#define VPP_MISC ((0x1d26 << 2) + 0xff000000)
+//Bit 31:20 ofifo line length minus 1
+//Bit 19 if true invert input vs
+//Bit 18 if true invert input hs
+//Bit 17 force top/bottom field, enable
+//Bit 16 force top/bottom field, 0: top, 1: bottom
+//Bit 15 force one go_field, one pluse, write only
+//Bit 14 force one go_line, one pluse, write only
+//Bit 12:0 ofifo size (actually only bit 10:1 is valid), always even number
+#define VPP_OFIFO_SIZE ((0x1d27 << 2) + 0xff000000)
+//Read only
+//Bit 28:18 current scale out fifo counter
+//Bit 17:13 current afifo counter
+//Bit 12:0 current ofifo counter
+#define VPP_FIFO_STATUS ((0x1d28 << 2) + 0xff000000)
+// Bit 5 SMOKE3 postblend enable only when postblend vd2 is not enable
+// Bit 4 SMOKE3 preblend enable only when preblend vd2 is not enable
+// Bit 3 SMOKE2 postblend enable only when postblend osd2 is not enable
+// Bit 2 SMOKE2 preblend enable only when preblend osd2 is not enable
+// Bit 1 SMOKE1 postblend enable only when postblend osd1 is not enable
+// Bit 0 SMOKE1 preblend enable only when preblend osd1 is not enable
+#define VPP_SMOKE_CTRL ((0x1d29 << 2) + 0xff000000)
+//smoke can be used only when that blending is disable and then be used as smoke function
+//smoke1 for OSD1 chanel
+//smoke2 for OSD2 chanel
+//smoke3 for VD2 chanel
+//31:24 Y
+//23:16 Cb
+//15:8 Cr
+//7:0 Alpha
+#define VPP_SMOKE1_VAL ((0x1d2a << 2) + 0xff000000)
+#define VPP_SMOKE2_VAL ((0x1d2b << 2) + 0xff000000)
+#define VPP_SMOKE3_VAL ((0x1d2c << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_SMOKE1_H_START_END ((0x1d2d << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_SMOKE1_V_START_END ((0x1d2e << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_SMOKE2_H_START_END ((0x1d2f << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_SMOKE2_V_START_END ((0x1d30 << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_SMOKE3_H_START_END ((0x1d31 << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_SMOKE3_V_START_END ((0x1d32 << 2) + 0xff000000)
+//Bit 27:16 scale out fifo line length minus 1
+//Bit 12:0 scale out fifo size (actually only bit 11:1 is valid, 11:1, max 1024), always even number
+#define VPP_SCO_FIFO_CTRL ((0x1d33 << 2) + 0xff000000)
+//for 3D quincunx sub-sampling and horizontal pixel by pixel 3D interleaving
+//Bit 27:24, prehsc_mode, bit 3:2, prehsc odd line interp mode, bit 1:0, prehsc even line interp mode,
+// each 2bit, 00: pix0+pix1/2, average, 01: pix1, 10: pix0
+//Bit 23 horizontal scaler double pixel mode
+//Bit 22:21 horizontal scaler initial repeat pixel0 number1
+//Bit 19:16 horizontal scaler initial receiving number1
+//Bit 15:0 horizontal scaler top field initial phase1
+#define VPP_HSC_PHASE_CTRL1 ((0x1d34 << 2) + 0xff000000)
+//for 3D quincunx sub-sampling
+//31:24 prehsc pattern, each patten 1 bit, from lsb -> msb
+//22:20 prehsc pattern start
+//18:16 prehsc pattern end
+//15:8 hsc pattern, each patten 1 bit, from lsb -> msb
+//6:4 hsc pattern start
+//2:0 hsc pattern end
+#define VPP_HSC_INI_PAT_CTRL ((0x1d35 << 2) + 0xff000000)
+#define VPP_SC_GCLK_CTRL1 ((0x1d36 << 2) + 0xff000000)
+#define VPP_PREHSC_COEF ((0x1d37 << 2) + 0xff000000)
+#define VPP_PRE_SCALE_CTRL ((0x1d38 << 2) + 0xff000000)
+#define VPP_PREVSC_COEF ((0x1d39 << 2) + 0xff000000)
+#define VPP_PREHSC_COEF1 ((0x1d3a << 2) + 0xff000000)
+//Bit 3 minus black level enable for vadj2
+//Bit 2 Video adjustment enable for vadj2
+//Bit 1 minus black level enable for vadj1
+//Bit 0 Video adjustment enable for vadj1
+#define VPP_VADJ_CTRL ((0x1d40 << 2) + 0xff000000)
+//Bit 16:8 brightness, signed value
+//Bit 7:0 contrast, unsigned value, contrast from 0 <= contrast <2
+//`define VPP_VADJ1_Y 8'h41 //'h00080
+//cb' = cb*ma + cr*mb
+//cr' = cb*mc + cr*md
+//all are bit 9:0, signed value, -2 < ma/mb/mc/md < 2
+//`define VPP_VADJ1_MA_MB 8'h42 //26'h100_0000
+//`define VPP_VADJ1_MC_MD 8'h43 //26'h000_0100
+//Bit 16:8 brightness, signed value
+//Bit 7:0 contrast, unsigned value, contrast from 0 <= contrast <2
+//`define VPP_VADJ2_Y 8'h44 //'h00080
+//cb' = cb*ma + cr*mb
+//cr' = cb*mc + cr*md
+//all are bit 9:0, signed value, -2 < ma/mb/mc/md < 2
+//`define VPP_VADJ2_MA_MB 8'h45 //26'h100_0000
+//`define VPP_VADJ2_MC_MD 8'h46 //26'h000_0100
+//Bit 2 horizontal chroma sharp/blur selection, 0:sharp, 1: blur
+//Bit 1 horizontal luma sharp/blur selection, 0:sharp, 1: blur
+//Bit 0 horizontal sharpness enable
+#define VPP_HSHARP_CTRL ((0x1d50 << 2) + 0xff000000)
+//{1'b0,threhsold} < diff
+//Bit 26:16 luma threshold0
+//Bit 10:0 luma threshold1
+#define VPP_HSHARP_LUMA_THRESH01 ((0x1d51 << 2) + 0xff000000)
+//
+//Bit 26:16 luma threshold2
+//Bit 10:0 luma threshold3
+#define VPP_HSHARP_LUMA_THRESH23 ((0x1d52 << 2) + 0xff000000)
+//Bit 26:16 chroma threshold0
+//Bit 10:0 chroma threshold1
+#define VPP_HSHARP_CHROMA_THRESH01 ((0x1d53 << 2) + 0xff000000)
+//Bit 26:16 chroma threshold2
+//Bit 10:0 chroma threshold3
+#define VPP_HSHARP_CHROMA_THRESH23 ((0x1d54 << 2) + 0xff000000)
+//Bit 23:16 luma gain2
+//Bit 15:8 luma gain1
+//Bit 7:0 luma gain0
+#define VPP_HSHARP_LUMA_GAIN ((0x1d55 << 2) + 0xff000000)
+//
+//Bit 23:16 chroma gain2
+//Bit 15:8 chroma gain1
+//Bit 7:0 chroma gain0
+#define VPP_HSHARP_CHROMA_GAIN ((0x1d56 << 2) + 0xff000000)
+//Read only
+//Bit 31, if it is true, it means this probe is valid in the last field/frame
+//Bit 29:20 component 0
+//Bit 19:10 component 1
+//Bit 9:0 component 2
+#define VPP_MATRIX_PROBE_COLOR ((0x1d5c << 2) + 0xff000000)
+#define VPP_MATRIX_PROBE_COLOR1 ((0x1dd7 << 2) + 0xff000000)
+//Bit 23:16 component 0
+//Bit 15:8 component 1
+//Bit 7:0 component 2
+#define VPP_MATRIX_HL_COLOR ((0x1d5d << 2) + 0xff000000)
+//28:16 probe x, postion
+//12:0 probe y, position
+#define VPP_MATRIX_PROBE_POS ((0x1d5e << 2) + 0xff000000)
+//Bit 16, highlight_en
+//Bit 15 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix
+//Bit 14:12 probe_sel, 000: select post matrix, 001: select vd1 matrix, 010: select vd2 matrix
+//Bit 9:8 matrix coef idx selection, 00: select post matrix, 01: select vd1 matrix, 10: select vd2 matrix
+//Bit 5 vd1 conversion matrix enable
+//Bit 4 vd2 conversion matrix enable
+//Bit 2 output y/cb/cr saturation enable, only for post matrix (y saturate to 16-235, cb/cr saturate to 16-240)
+//Bit 1 input y/cb/cr saturation enable, only for post matrix (y saturate to 16-235, cb/cr saturate to 16-240)
+//Bit 0 post conversion matrix enable
+#define VPP_MATRIX_CTRL ((0x1d5f << 2) + 0xff000000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define VPP_MATRIX_COEF00_01 ((0x1d60 << 2) + 0xff000000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define VPP_MATRIX_COEF02_10 ((0x1d61 << 2) + 0xff000000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define VPP_MATRIX_COEF11_12 ((0x1d62 << 2) + 0xff000000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define VPP_MATRIX_COEF20_21 ((0x1d63 << 2) + 0xff000000)
+#define VPP_MATRIX_COEF22 ((0x1d64 << 2) + 0xff000000)
+//Bit 26:16 offset0
+//Bit 10:0 offset1
+#define VPP_MATRIX_OFFSET0_1 ((0x1d65 << 2) + 0xff000000)
+//Bit 10:0 offset2
+#define VPP_MATRIX_OFFSET2 ((0x1d66 << 2) + 0xff000000)
+//Bit 26:16 pre_offset0
+//Bit 10:0 pre_offset1
+#define VPP_MATRIX_PRE_OFFSET0_1 ((0x1d67 << 2) + 0xff000000)
+//Bit 10:0 pre_offset2
+#define VPP_MATRIX_PRE_OFFSET2 ((0x1d68 << 2) + 0xff000000)
+// dummy data used in the VPP postblend
+// Bit 23:16 Y
+// Bit 15:8 CB
+// Bit 7:0 CR
+#define VPP_DUMMY_DATA1 ((0x1d69 << 2) + 0xff000000)
+//Bit 31 gainoff module enable
+//Bit 26:16 gain0, 1.10 unsigned data
+//Bit 10:0 gain1, 1.10 unsigned dat
+#define VPP_GAINOFF_CTRL0 ((0x1d6a << 2) + 0xff000000)
+//Bit 26:16 gain2, 1.10 unsigned data
+//Bit 10:0, offset0, signed data
+#define VPP_GAINOFF_CTRL1 ((0x1d6b << 2) + 0xff000000)
+//Bit 26:16, offset1, signed data
+//Bit 10:0, offset2, signed data
+#define VPP_GAINOFF_CTRL2 ((0x1d6c << 2) + 0xff000000)
+//Bit 26:16, pre_offset0, signed data
+//Bit 10:0, pre_offset1, signed data
+#define VPP_GAINOFF_CTRL3 ((0x1d6d << 2) + 0xff000000)
+//Bit 10:0, pre_offset2, signed data
+#define VPP_GAINOFF_CTRL4 ((0x1d6e << 2) + 0xff000000)
+#define VPP_GAINOFF_GCLK_CTRL ((0x1d6f << 2) + 0xff000000)
+//only two registers used in the color management, which are defined in the chroma_reg.h
+//`define VPP_CHROMA_ADDR_PORT 8'h70
+//`define VPP_CHROMA_DATA_PORT 8'h71
+//
+// Reading file: chroma_reg.h
+//
+//**********************************************************************************
+//* Copyright (c) 2008, AMLOGIC Inc.
+//* All rights reserved
+//**********************************************************************************
+//* File : chroma_reg.v
+//* Author : Terrence Wang
+//* Date : Dec 2008
+//* Description :
+//*
+//**********************************************************************************
+//* Modification History:
+//* Date Modified By Reason
+//**********************************************************************************
+// synopsys translate_off
+// synopsys translate_on
+#define VPP_CHROMA_ADDR_PORT ((0x1d70 << 2) + 0xff000000)
+#define VPP_CHROMA_DATA_PORT ((0x1d71 << 2) + 0xff000000)
+//`define CHROMA_ADDR_PORT 8'h67
+//`define CHROMA_DATA_PORT 8'h68
+
+// CHROMA_GAIN_REG_XX(00-07)
+// hue gain, sat gain function control
+// Bit 31 reg_sat_en enable sat adjustment in current region
+// Bit 27 reg_sat_increase sat adjustment increase or decrease
+// 1'b1: increase 1'b0: decrease
+// Bit 26:25 reg_sat_central_en sat adjustment with central biggest or one side biggest
+// 2'b01 central biggest 2'b00 one side biggest
+// Bit 24 reg_sat_shape when sat adjustment one side biggest, define left or right
+// 1'b1: left side biggest 1'b0 right side biggest
+// Bit 23:16 reg_sat_gain define the sat gain when sat adjustment
+// 0x00-0xff
+// Bit 15 reg_hue_en enable hue adjustment in current region
+// Bit 11 reg_hue_clockwise hue adjustment clockwise or anti-clockwise
+// 1'b1: clockwise 1'b0: anti-clockwise
+// Bit 10:9 reg_hue_central_en when hue adjustment, parabola curve or non-symmetry curve
+// 1'b1: parabola curve 1'b0: non-symmetry curve
+// Bit 8 reg_hue_shape when non-symmetry curve, define which side change more
+// 1'b1: right side change more 1'b0: left side change more
+// Bit 7:0 reg_hue_gain define the hue gain when hue adjustment
+// 0x00-0x80, note: should be no bigger than 0x80
+
+ #define CHROMA_GAIN_REG00 0x00
+
+
+// HUE_HUE_RANGE_REG_XX(00-07)
+// hue range select
+// Bit 31:24 no use now
+// Bit 23:16 reg_hue_shift_range define the angle of target region
+// 0x00-0xff,(0x100 means 120 degree though it can not be set)
+// must be greater or equal than 8'd8
+// Bit 15 reg_symmetry_en this is used for create one symmetry region
+// the symmetry region hue_shift_start = reg_hue_hue_shift_start + reg_hue_shift_range<<5
+// the symmetry region hue_shift_range = reg_hue_shift_range
+// in symmetry region, all the sat and hue setting will be same with original region,
+// except reg_hue_shape, reg_sat_shape, reg_hue_clockwise will be reversed
+// Bit 14:0 reg_hue_hue_shift_start define the start angle of target region
+// 0x6000 means 360 degree
+// only region 0 and 1 can exceed 360 degrees.
+
+ #define HUE_HUE_RANGE_REG00 0x01
+
+
+// HUE_RANGE_INV_REG_XX
+// Calculation should be follow
+// HUE_RANGE_INV_REG0X[15:0] = ((1<<20)/HUE_HUE_RANGE_REG0X[23:16]+1)>>1
+// HUE_RANGE_INV_REG_XX is to used to save divider
+
+ #define HUE_RANGE_INV_REG00 0x02
+
+
+
+// for belowing each low, high, low_slope, high_slope group:
+// a_____________b
+// / \ a = low + 2^low_slope
+// / \ b = high - 2^high_slope
+// / \ low_slope <= 7; high_slope <= 7
+// / \ b >= a
+// ______/_____________________\________
+// low high
+//
+//
+// HUE_LUM_RANGE_REG_XX(00-07)
+// luma range selection for hue adjustment
+// Bit 31:24 reg_sat_lum_low define the low level of luma value for sat adjustment
+// 0x00-0xff
+// Bit 23:20 reg_hue_lum_high_slope define the slope area below high level of luma value for hue adjustment
+// 0x00-0x07
+// Bit 19:16 reg_hue_lum_low_slope define the slope area above low level of luma value for hue adjustment
+// 0x00-0x07
+// Bit 15:8 reg_hue_lum_high define the high level of luma value for hue adjustment
+// 0x00-0xff
+// Bit 7:0 reg_hue_lum_low define the low level of luma value for hue adjustment
+// 0x00-0xff
+
+ #define HUE_LUM_RANGE_REG00 0x03
+
+// HUE_SAT_RANGE_REG_XX(00-07)
+// sat range selection for hue adjustment
+// Bit 31:24 reg_sat_lum_high define the high level of luma value for sat adjustment
+// 0x00-0xff
+// Bit 23:20 reg_hue_sat_high_slope define the slope area below high level of sat value for hue adjustment
+// 0x00-0x07
+// Bit 19:16 reg_hue_sat_low_slope define the slope area above low level of sat value for hue adjustment
+// 0x00-0x07
+// Bit 15:8 reg_hue_sat_high define the high level of sat value for hue adjustment
+// 0x00-0xff
+// Bit 7:0 reg_hue_sat_low define the low level of sat value for hue adjustment
+// 0x00-0xff
+
+ #define HUE_SAT_RANGE_REG00 0x04
+
+// SAT_SAT_RANGE_REG_XX(00-07)
+// sat range selection for hue adjustment
+// Bit 31:28 reg_sat_lum_high_slope define the slope area below high level of luma value for sat adjustment
+// 0x00-0x07
+// Bit 27:24 reg_sat_lum_low_slope define the slope area above low level of luma value for sat adjustment
+// 0x00-0x07
+// Bit 23:20 reg_sat_sat_high_slope define the slope area below high level of sat value for sat adjustment
+// 0x00-0x07
+// Bit 19:16 reg_sat_sat_low_slope define the slope area above low level of sat value for sat adjustment
+// 0x00-0x07
+// Bit 15:8 reg_sat_sat_high define the high level of sat value for sat adjustment
+// 0x00-0xff
+// Bit 7:0 reg_sat_sat_low define the low level of sat value for sat adjustment
+// 0x00-0xff
+
+ #define SAT_SAT_RANGE_REG00 0x05
+
+
+ #define CHROMA_GAIN_REG01 0x06
+ #define HUE_HUE_RANGE_REG01 0x07
+ #define HUE_RANGE_INV_REG01 0x08
+ #define HUE_LUM_RANGE_REG01 0x09
+ #define HUE_SAT_RANGE_REG01 0x0a
+ #define SAT_SAT_RANGE_REG01 0x0b
+
+ #define CHROMA_GAIN_REG02 0x0c
+ #define HUE_HUE_RANGE_REG02 0x0d
+ #define HUE_RANGE_INV_REG02 0x0e
+ #define HUE_LUM_RANGE_REG02 0x0f
+ #define HUE_SAT_RANGE_REG02 0x10
+ #define SAT_SAT_RANGE_REG02 0x11
+
+
+ #define CHROMA_GAIN_REG03 0x12
+ #define HUE_HUE_RANGE_REG03 0x13
+ #define HUE_RANGE_INV_REG03 0x14
+ #define HUE_LUM_RANGE_REG03 0x15
+ #define HUE_SAT_RANGE_REG03 0x16
+ #define SAT_SAT_RANGE_REG03 0x17
+
+ #define CHROMA_GAIN_REG04 0x18
+ #define HUE_HUE_RANGE_REG04 0x19
+ #define HUE_RANGE_INV_REG04 0x1a
+ #define HUE_LUM_RANGE_REG04 0x1b
+ #define HUE_SAT_RANGE_REG04 0x1c
+ #define SAT_SAT_RANGE_REG04 0x1d
+
+ #define CHROMA_GAIN_REG05 0x1e
+ #define HUE_HUE_RANGE_REG05 0x1f
+ #define HUE_RANGE_INV_REG05 0x20
+ #define HUE_LUM_RANGE_REG05 0x21
+ #define HUE_SAT_RANGE_REG05 0x22
+ #define SAT_SAT_RANGE_REG05 0x23
+
+ #define CHROMA_GAIN_REG06 0x24
+ #define HUE_HUE_RANGE_REG06 0x25
+ #define HUE_RANGE_INV_REG06 0x26
+ #define HUE_LUM_RANGE_REG06 0x27
+ #define HUE_SAT_RANGE_REG06 0x28
+ #define SAT_SAT_RANGE_REG06 0x29
+
+ #define CHROMA_GAIN_REG07 0x2a
+ #define HUE_HUE_RANGE_REG07 0x2b
+ #define HUE_RANGE_INV_REG07 0x2c
+ #define HUE_LUM_RANGE_REG07 0x2d
+ #define HUE_SAT_RANGE_REG07 0x2e
+ #define SAT_SAT_RANGE_REG07 0x2f
+
+// REG_CHROMA_CONTROL
+// Bit 31 reg_chroma_en enable color manage function
+// 1'b1: enable 1'b0: bypass
+// Bit 6 sat_sel uv_max or u^2+v^2 selected as sat for reference
+// 1'b1: uv_max(default) 1'b0: u^2+v^2
+// Bit 5 uv_adj_en final uv_adjust enable
+// 1'b1: enable 1'b0: bypass
+// Bit 2 hue_en rgb to hue enable
+// 1'b1: enable(default) 1'b0: bypass
+// Bit 1:0 csc_sel define input YUV with different color type
+// 2'b00: 601(16-235) 2'b01: 709(16-235)
+// 2'b10: 601(0-255) 2'b11: 709(0-255)
+ #define REG_CHROMA_CONTROL 0x30 // default 32h'80000024
+ #define REG_DEMO_CENTER_BAR 0x31 // default 32h'0
+ #define REG_DEMO_HLIGHT_MODE 0x32 // default 32h'0
+ #define REG_DEMO_OWR_DATA 0x33 // default 32h'0
+
+
+////===========================================////
+//// CM2 ADDR
+////===========================================////
+
+ #define SAT_BYYB_NODE_REG0 0x200 // default 32'h0
+//Bit 31:24, sat_byyb_node3 the 4th node
+//Bit 23:16, sat_byyb_node2 the 3th node
+//Bit 15: 8, sat_byyb_node1 signed, the 2th node about saturation
+//Bit 7: 0, sat_byyb_node0 signed, the 1th node about saturation
+//gain offset along y coordinate,the gain normalized to 128 as "1"
+
+ #define SAT_BYYB_NODE_REG1 0x201 // default 32'h0
+//Bit 31:24, sat_byyb_node7 the 8th node
+//Bit 23:16, sat_byyb_node6 the 7th node
+//Bit 15: 8, sat_byyb_node5 signed, the 6th node about saturation
+//Bit 7: 0, sat_byyb_node4 signed, the 5th node about saturation
+//gain offset along y coordinate,the gain normalized to 128 as "1"
+
+ #define SAT_BYYB_NODE_REG2 0x202 // default 32'h0
+//Bit 31: 8, reserved
+//Bit 7: 0, sat_byyb_node4 signed, the 5th node about saturation
+
+
+ #define SAT_SRC_NODE_REG 0x203 // default 32'h0
+//Bit 31:28, reserved
+//Bit 27:16, sat_src_node1
+//Bit 15:12, reserved
+//Bit 11: 0, sat_src_node0 usigned, threshold of input saturation for first and second piece
+
+ #define CM_ENH_SFT_MODE_REG 0x204 // default 32'h0
+//Bit 31: 9, reserved
+//Bit 8: 6, hue_lsft_mode hue offset adjustments scale
+//Bit 5: 4, luma_lsft_mode luma offset adjustments scale for reg_cm2_adj_luma_via_hue
+//Bit 3: 2, sat_byy_rsft_mode saturation gain adjustments scale for reg_cm2_adj_sat_via_y
+//Bit 1: 0, sat_byhs_rsft_mode saturation gain adjustments scale for reg_cm2_adj_sat_via_hs[:][:] 0:no scale up/down 1:dnscale by 2(-128,127)/2
+
+ #define FRM_SIZE_REG 0x205 // default 32'h0
+//Bit 31:29, reserved
+//Bit 28:16, reg_frm_height the frame height size
+//Bit 15:13, reserved
+//Bit 12: 0, reg_frm_width the frame width size
+
+ #define FITLER_CFG_REG 0x206 // default 32'h0
+//Bit 31: 5, reserved
+//Bit 4: 4, inteleav_mod horizontal interleave filter(zero-padding) for 3D considerations 0:using non-zero padding lpf 1:using zero-padding lpf
+//Bit 3: 2, lpf_slt_uv apply cm on lp portion or original video pixels options
+//Bit 1: 0, lpf_slt_y apply cm on lp portion or original video pixels options
+
+ #define CM_GLOBAL_GAIN_REG 0x207 // default 32'h0
+//Bit 31:28, reserved
+//Bit 27:16, cm2_global_sat global saturation gain for general color adjustments(0~4095 <=> 0~8),512 normalized to "1"
+//Bit 15:12, reserved
+//Bit 11: 0, cm2_global_hue global hue offsets for general color adjustments(0~4095 <=> 0~360 degree)
+
+ #define CM_ENH_CTL_REG 0x208 // default 32'h0
+//Bit 31:7, reserved
+//Bit 6, hue_adj_en cm2 hue adjustments
+//Bit 5, sat_adj_en cm2 saturation adjustments
+//Bit 4, luma_adj_en enable siganl for cm2 luma adjustments
+//Bit 3, reserved
+//Bit 2, cm2_filt_en apply cm on lp portion enable
+//Bit 1, cm2_en cm2 enable siganl
+//Bit 0, cm1_en
+
+ #define ROI_X_SCOPE_REG 0x209 // default 32'h0
+//Bit 31:29, reserved
+//Bit 28:16, roi_x_end ending col index of the region of interest
+//Bit 15:13, reserved
+//Bit 12: 0, roi_x_beg start col index of the region of interest
+
+ #define ROI_Y_SCOPE_REG 0x20a // default 32'h0
+//Bit 31:29, reserved
+//Bit 28:16, roi_y_end ending row index of the region of interest
+//Bit 15:13, reserved
+//Bit 12: 0, roi_y_beg start row index of the region of interest
+
+ #define POI_XY_DIR_REG 0x20b // default 32'h0
+//Bit 31:29, reserved
+//Bit 28:16, poi_y_dir ending row index of the region of interest
+//Bit 15:13, reserved
+//Bit 12: 0, poi_x_dir start row index of the region of interest
+
+ #define COI_Y_SCOPE_REG 0x20c // default 32'h0
+//Bit 31:16, reserved
+//Bit 15: 8, coi_y_end
+//Bit 7: 0, coi_y_beg
+
+ #define COI_H_SCOPE_REG 0x20d // default 32'h0
+//Bit 31:28, reserved
+//Bit 27:16, coi_h_end
+//Bit 15:12, reserved
+//Bit 11: 0, coi_h_beg lower bound of hue value for color of interest ,12 bits precision
+
+ #define COI_S_SCOPE_REG 0x20e // default 32'h0
+//Bit 31:28, reserved
+//Bit 27:16, coi_s_end
+//Bit 15:12, reserved
+//Bit 11: 0, coi_s_beg lower bound of sat value for color of interest ,12 bits precision
+ #define IFO_MODE_REG 0x20f // default 32'h0
+//Bit 31:8, reserved
+//Bit 7:6, ifo_mode3
+//Bit 5:4, ifo_mode2
+//Bit 3:2, ifo_mode1
+//Bit 1:0, ifo_mode0
+ #define POI_RPL_MODE_REG 0x210 // default 32'h0
+//Bit 31:4, reserved
+//Bit 3:0, poi_rpl_mode enhance mode control of pixels inside and outside region of interest bit[3:2]control roi
+ #define DEMO_OWR_YHS_REG 0x211 // default 32'h0
+//Bit 31: 0, demo_owr_yhs
+
+ #define DEMO_POI_Y_REG 0x212 // default 32'h0
+//Bit 31: 8, reserved
+//Bit 7: 0, luma_data_poi_r only get locked higher 8bits
+ #define DEMO_POI_H_REG 0x213 // default 32'h0
+//Bit 31: 12, reserved
+//Bit 11: 0, hue_data_poi_r only get locked higher 12bits
+ #define DEMO_POI_S_REG 0x214 // default 32'h0
+//Bit 31: 12, reserved
+//Bit 11: 0, sat_data_poi_r only get locked higher 12bits
+ //`define LUMA_BYH_LIMT_REG 10'h215 // default 32'h0
+ #define LUMA_ADJ_LIMT_REG 0x215 // default 32'h0
+//Bit 31:24, reserved
+//Bit 23:16, luma_lmt_satslp slope to do the luma adjustment degrade
+//Bit 15:12, reserved
+//Bit 11:0, luma_lmt_satth threshold to saturation
+ #define SAT_ADJ_LIMT_REG 0x216 // default 32'h0
+//Bit 31:24, reserved
+//Bit 23:16, sat_lmt_satslp slope to do the adjustment degrade
+//Bit 15:12, reserved
+//Bit 11:0, sat_lmt_satth threshold to saturation
+ #define HUE_ADJ_LIMT_REG 0x217 // default 32'h0
+//Bit 31: 24, reserved
+//Bit 23: 16, hue_lmt_satslp slope to do the adjustment degrade
+//Bit 15: 12, reserved
+//Bit 11: 0, hue_lmt_satth threshold to saturation
+ #define UVHS_OFST_REG 0x218 // default 32'h0
+//Bit 31: 24, hs2uv_v_ofst
+//Bit 23: 16, hs2uv_u_ofst
+//Bit 15: 8, uv2hs_v_ofst
+//Bit 7: 0, uv2hs_u_ofst
+ #define HUE_CFG_PARA_REG 0x219 // default 32'h0
+//Bit 31: 17, reserved
+//Bit 16, hue_protect_en
+//Bit 15: 13, cm2_hue_byhs_mode
+//Bit 12, cm2_hue_div_mode
+//Bit 11: 0, cm2_before_hue_ofst
+ #define DEMO_SPLT_CFG_REG 0x21a // default 32'h0
+//Bit 31: 22, reserved
+//Bit 21: 20, demo_split_mode
+//Bit 19: 16, demo_split_width slope to do the adjustment degrade
+//Bit 15: 13, reserved
+//Bit 12: 0, demo_split_post threshold to saturation
+ #define DEMO_SPLT_YHS_REG 0x21b // default 32'h0
+//Bit 31: 0, demo_splt_yhs threshold to saturation
+
+ #define XVYCC_YSCP_REG 0x21c // default 32'h0
+//Bit 31: 28, reserved
+//Bit 27: 16, xvycc_y_max
+//Bit 15: 12, reserved
+//Bit 11: 0, xvycc_y_min
+ #define XVYCC_USCP_REG 0x21d // default 32'h0
+//Bit 31: 28, reserved
+//Bit 27: 16, xvycc_u_max
+//Bit 15: 12, reserved
+//Bit 11: 0, xvycc_u_min
+ #define XVYCC_VSCP_REG 0x21e // default 32'h0
+//Bit 31: 28, reserved
+//Bit 27: 16, xvycc_v_max
+//Bit 15: 12, reserved
+//Bit 11: 0, xvycc_v_min
+ #define LUMA_ADJ0_REG 0x21f // default 32'h0
+//Bit 21: 12, reg_cm_luma_blacklevel
+//Bit 11: 0, reg_cm_luma_contrast
+ #define LUMA_ADJ1_REG 0x220 // default 32'h0
+
+ #define STA_WIN_XYXY0_REG 0x221 // default 32'h0
+ #define STA_WIN_XYXY1_REG 0x222 // default 32'h0
+ #define STA_CFG_REG 0x223 // default 32'h0
+ #define STA_SAT_HIST0_REG 0x224 // default 32'h0
+ #define STA_SAT_HIST1_REG 0x225 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN0 0x226 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN1 0x227 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN2 0x228 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN3 0x229 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN4 0x22a // default 32'h0
+ #define RO_CM_HUE_HIST_BIN5 0x22b // default 32'h0
+ #define RO_CM_HUE_HIST_BIN6 0x22c // default 32'h0
+ #define RO_CM_HUE_HIST_BIN7 0x22d // default 32'h0
+ #define RO_CM_HUE_HIST_BIN8 0x22e // default 32'h0
+ #define RO_CM_HUE_HIST_BIN9 0x22f // default 32'h0
+ #define RO_CM_HUE_HIST_BIN10 0x230 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN11 0x231 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN12 0x232 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN13 0x233 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN14 0x234 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN15 0x235 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN16 0x236 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN17 0x237 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN18 0x238 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN19 0x239 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN20 0x23a // default 32'h0
+ #define RO_CM_HUE_HIST_BIN21 0x23b // default 32'h0
+ #define RO_CM_HUE_HIST_BIN22 0x23c // default 32'h0
+ #define RO_CM_HUE_HIST_BIN23 0x23d // default 32'h0
+ #define RO_CM_HUE_HIST_BIN24 0x23e // default 32'h0
+ #define RO_CM_HUE_HIST_BIN25 0x23f // default 32'h0
+ #define RO_CM_HUE_HIST_BIN26 0x240 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN27 0x241 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN28 0x242 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN29 0x243 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN30 0x244 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN31 0x245 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN0 0x246 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN1 0x247 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN2 0x248 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN3 0x249 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN4 0x24a // default 32'h0
+ #define RO_CM_SAT_HIST_BIN5 0x24b // default 32'h0
+ #define RO_CM_SAT_HIST_BIN6 0x24c // default 32'h0
+ #define RO_CM_SAT_HIST_BIN7 0x24d // default 32'h0
+ #define RO_CM_SAT_HIST_BIN8 0x24e // default 32'h0
+ #define RO_CM_SAT_HIST_BIN9 0x24f // default 32'h0
+ #define RO_CM_SAT_HIST_BIN10 0x250 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN11 0x251 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN12 0x252 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN13 0x253 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN14 0x254 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN15 0x255 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN16 0x256 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN17 0x257 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN18 0x258 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN19 0x259 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN20 0x25a // default 32'h0
+ #define RO_CM_SAT_HIST_BIN21 0x25b // default 32'h0
+ #define RO_CM_SAT_HIST_BIN22 0x25c // default 32'h0
+ #define RO_CM_SAT_HIST_BIN23 0x25d // default 32'h0
+ #define RO_CM_SAT_HIST_BIN24 0x25e // default 32'h0
+ #define RO_CM_SAT_HIST_BIN25 0x25f // default 32'h0
+ #define RO_CM_SAT_HIST_BIN26 0x260 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN27 0x261 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN28 0x262 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN29 0x263 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN30 0x264 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN31 0x265 // default 32'h0
+ #define RO_CM_BLK_BIN 0x266 // default 32'h0
+ #define RO_CM_BRT_BIN 0x267 // default 32'h0
+
+////========= NODE 0 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H00 0x100 // default 32'H0
+//Bit 31: 24, reg_cm2_adj_sat_via_hs_2
+//Bit 23: 16, reg_cm2_adj_sat_via_hs_1
+//Bit 15: 8, reg_cm2_adj_sat_via_hs_0
+//Bit 7: 0, reg_cm2_adj_luma_via_h
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H00 0x101 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H00 0x102 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H00 0x103 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H00 0x104 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 1 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H01 0x108 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H01 0x109 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H01 0x10a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H01 0x10b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H01 0x10c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 2 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H02 0x110 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H02 0x111 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H02 0x112 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H02 0x113 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H02 0x114 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 3 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H03 0x118 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H03 0x119 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H03 0x11a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H03 0x11b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H03 0x11c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 4 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H04 0x120 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H04 0x121 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H04 0x122 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H04 0x123 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H04 0x124 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 5 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H05 0x128 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H05 0x129 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H05 0x12a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H05 0x12b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H05 0x12c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 6 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H06 0x130 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H06 0x131 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H06 0x132 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H06 0x133 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H06 0x134 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 7 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H07 0x138 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H07 0x139 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H07 0x13a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H07 0x13b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H07 0x13c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 8 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H08 0x140 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H08 0x141 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H08 0x142 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H08 0x143 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H08 0x144 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 9 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H09 0x148 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H09 0x149 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H09 0x14a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H09 0x14b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H09 0x14c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 10 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H10 0x150 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H10 0x151 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H10 0x152 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H10 0x153 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H10 0x154 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 11 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H11 0x158 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H11 0x159 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H11 0x15a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H11 0x15b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H11 0x15c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 12 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H12 0x160 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H12 0x161 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H12 0x162 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H12 0x163 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H12 0x164 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 13 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H13 0x168 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H13 0x169 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H13 0x16a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H13 0x16b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H13 0x16c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+
+/* Constraints
+0)
+ there are 16 regions totally. 8 regions are for hue adjustment, 8 regions are for sat adjustment.
+ the hue range of the 16 regions can be set to overlap, but if overlap, the hue range(start and end) must be same.
+ the 8 regions for hue adjustment should not overlap. if corresponding reg_hue_en_00 - 07 == 1
+ the 8 regions for hue adjustment are defined by: (example are for region 0)
+ a) hue:
+ start: reg_hue_hue_shift_start_00[14:0]
+ end:
+ if reg_symmetry_en_00 == 0
+ reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<5)
+ if reg_symmetry_en_00 == 1
+ reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<6)
+ b) sat:
+ start: reg_hue_sat_low_00
+ end: reg_hue_sat_high_00
+
+ the 8 regions for sat adjustment should not overlap. if corresponding reg_sat_en_00 - 07 == 1
+ the 8 regions for sat adjustment are defined by: (example are for region 0)
+ a) hue: same as that for hue adjustment.
+ start: reg_hue_hue_shift_start_00[14:0]
+ end:
+ if reg_symmetry_en_00 == 0
+ reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<5)
+ if reg_symmetry_en_00 == 1
+ reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<6)
+ b) sat:
+ start: reg_sat_sat_low_00
+ end: reg_sat_sat_high_00
+
+1)
+ reg_hue_hue_shift_range_00[7:0]:
+ reg_hue_hue_shift_range_01[7:0]:
+ reg_hue_hue_shift_range_02[7:0]:
+ reg_hue_hue_shift_range_03[7:0]:
+ reg_hue_hue_shift_range_04[7:0]:
+ reg_hue_hue_shift_range_05[7:0]:
+ reg_hue_hue_shift_range_06[7:0]:
+ reg_hue_hue_shift_range_07[7:0]:
+ must be greater or equal than 8'd8, so as reg_hue_range_inv_regxx can be represented by 0.0000_0000_xxxx_xxxx_xxxx_xxxx
+
+2)
+ all regions of 0-7 should meet below requirement. below is just an example for region 7.
+ (reg_hue_lum_high_07 - reg_hue_lum_low_07) >=
+ (1<<reg_hue_lum_low_slope_07) + (1<<reg_hue_lum_high_slope_07)
+
+ (reg_hue_sat_high_07 - reg_hue_sat_low_07) >=
+ (1<<reg_hue_sat_low_slope_07) + (1<<reg_hue_sat_high_slope_07)
+
+ (reg_sat_lum_high_07 - reg_sat_lum_low_07) >=
+ (1<<reg_sat_lum_low_slope_07) + (1<<reg_sat_lum_high_slope_07)
+
+ (reg_sat_sat_high_07 - reg_sat_sat_low_07) >=
+ (1<<reg_sat_sat_low_slope_07) + (1<<reg_sat_sat_high_slope_07)
+
+3)
+ all of reg_hue_hue_shift_start_00[14:0] ~ 07[14:0] < 0x6000.
+ only region 0 and 1 can exceed 360 degrees. ie:
+ reg_hue_hue_shift_start_00 + (reg_hue_hue_shift_range_00<<5) can greater than 0x6000.
+ reg_hue_hue_shift_start_01 + (reg_hue_hue_shift_range_01<<5) can greater than 0x6000.
+ but below should be met:
+ reg_hue_hue_shift_start_00 + (reg_hue_hue_shift_range_00<<5) < 0x8000. if reg_symmetry_en_00 == 0
+ reg_hue_hue_shift_start_01 + (reg_hue_hue_shift_range_00<<5) < 0x8000. if reg_symmetry_en_00 == 0
+ reg_hue_hue_shift_start_00 + (reg_hue_hue_shift_range_00<<6) < 0x8000. if reg_symmetry_en_00 == 1
+ reg_hue_hue_shift_start_01 + (reg_hue_hue_shift_range_00<<6) < 0x8000. if reg_symmetry_en_00 == 1
+
+ others could not exceed 360 degrees. ie:
+ reg_hue_hue_shift_start_02(to 7) + (reg_hue_hue_shift_range_02 (to 7) <<5) < 0x6000. if reg_symmetry_en_02 (to 7) == 0.
+ reg_hue_hue_shift_start_02(to 7) + (reg_hue_hue_shift_range_02 (to 7) <<6) < 0x6000. if reg_symmetry_en_02 (to 7) == 1.
+
+4)
+ reg_hue_gain_00[7:0] <= 0x80.
+ reg_hue_gain_01[7:0] <= 0x80.
+ reg_hue_gain_02[7:0] <= 0x80.
+ reg_hue_gain_03[7:0] <= 0x80.
+ reg_hue_gain_04[7:0] <= 0x80.
+ reg_hue_gain_05[7:0] <= 0x80.
+ reg_hue_gain_06[7:0] <= 0x80.
+ reg_hue_gain_07[7:0] <= 0x80.
+
+5)
+ below registers can only have two setting: 00 and 01.
+ reg_hue_central_en_00[1:0] .. _07[1:0]
+ reg_sat_central_en_00[1:0] .. _07[1:0]
+
+6)
+ all reg_..._slope_00-07 should not be greater than 7, ie: maximum value is 7.
+ for example: below is for region 0:
+ reg_hue_lum_low_slope_00[3:0] <= 7
+ reg_hue_lum_high_slope_00[3:0] <= 7
+ reg_hue_sat_low_slope_00[3:0] <= 7
+ reg_hue_sat_high_slope_00[3:0] <= 7
+ reg_sat_lum_low_slope_00[3:0] <= 7
+ reg_sat_lum_high_slope_00[3:0] <= 7
+ reg_sat_sat_low_slope_00[3:0] <= 7
+ reg_sat_sat_high_slope_00[3:0] <= 7
+*/
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: chroma_reg.h
+//
+//(hsvsharp), (blue), gainoff, mat_vd1,mat_vd2, mat_post, prebld, postbld,(hsharp),sco_ff, vadj1, vadj2, ofifo, (chroma1), clk0(free_clk) vpp_reg
+//each item 2bits, for each 2bits, if bit 2*i+1 == 1, free clk, else if bit 2*i == 1 no clk, else auto gated clock
+//bit1 is not used, because I can not turn off vpp_reg clk because I can not turn on again
+//because the register itself canot be set again without clk
+//Bit 31:0
+#define VPP_GCLK_CTRL0 ((0x1d72 << 2) + 0xff000000)
+//(front_lti), (front_cti), Chroma2_filter, Chroma2, (Ccoring), (blackext), dnlp
+//Bit 13:0
+#define VPP_GCLK_CTRL1 ((0x1d73 << 2) + 0xff000000)
+//prehsc_clk, line_buf, prevsc, vsc, hsc_clk, clk0(free_clk)
+//Bit 11:0
+#define VPP_SC_GCLK_CTRL ((0x1d74 << 2) + 0xff000000)
+//Bit 17:9 VD1 alpha for preblend
+//Bit 8:0 VD1 alpha for postblend
+#define VPP_MISC1 ((0x1d76 << 2) + 0xff000000)
+//Bit 31:0 super scalar clock control
+#define VPP_SRSCL_GCLK_CTRL ((0x1d77 << 2) + 0xff000000)
+//Bit 31:0 OSD super scalar clock control
+#define VPP_OSDSR_GCLK_CTRL ((0x1d78 << 2) + 0xff000000)
+//Bit 31:0 vvycc clock control
+#define VPP_XVYCC_GCLK_CTRL ((0x1d79 << 2) + 0xff000000)
+//Bit 31:24 blackext_start
+//Bit 23:16 blackext_slope1
+//Bit 15:8 blackext_midpt
+//Bit 7:0 blackext_slope2
+#define VPP_BLACKEXT_CTRL ((0x1d80 << 2) + 0xff000000)
+//Bit 31:24 bottom of region03 output value
+//Bit 23:16 bottom of region02 output value
+//Bit 15:8 bottom of region01 output value
+//Bit 7:0 bottom of region00 output value
+#define VPP_DNLP_CTRL_00 ((0x1d81 << 2) + 0xff000000)
+//Bit 31:24 bottom of region07 output value
+//Bit 23:16 bottom of region06 output value
+//Bit 15:8 bottom of region05 output value
+//Bit 7:0 bottom of region04 output value
+#define VPP_DNLP_CTRL_01 ((0x1d82 << 2) + 0xff000000)
+//Bit 31:24 bottom of region11 output value
+//Bit 23:16 bottom of region10 output value
+//Bit 15:8 bottom of region09 output value
+//Bit 7:0 bottom of region08 output value
+#define VPP_DNLP_CTRL_02 ((0x1d83 << 2) + 0xff000000)
+//Bit 31:24 bottom of region15 output value
+//Bit 23:16 bottom of region14 output value
+//Bit 15:8 bottom of region13 output value
+//Bit 7:0 bottom of region12 output value
+#define VPP_DNLP_CTRL_03 ((0x1d84 << 2) + 0xff000000)
+//Bit 31:24 bottom of region19 output value
+//Bit 23:16 bottom of region18 output value
+//Bit 15:8 bottom of region17 output value
+//Bit 7:0 bottom of region16 output value
+#define VPP_DNLP_CTRL_04 ((0x1d85 << 2) + 0xff000000)
+//Bit 31:24 bottom of region23 output value
+//Bit 23:16 bottom of region22 output value
+//Bit 15:8 bottom of region21 output value
+//Bit 7:0 bottom of region20 output value
+#define VPP_DNLP_CTRL_05 ((0x1d86 << 2) + 0xff000000)
+//Bit 31:24 bottom of region27 output value
+//Bit 23:16 bottom of region26 output value
+//Bit 15:8 bottom of region25 output value
+//Bit 7:0 bottom of region24 output value
+#define VPP_DNLP_CTRL_06 ((0x1d87 << 2) + 0xff000000)
+//Bit 31:24 bottom of region31 output value
+//Bit 23:16 bottom of region30 output value
+//Bit 15:8 bottom of region29 output value
+//Bit 7:0 bottom of region28 output value
+#define VPP_DNLP_CTRL_07 ((0x1d88 << 2) + 0xff000000)
+//Bit 31:24 bottom of region35 output value
+//Bit 23:16 bottom of region34 output value
+//Bit 15:8 bottom of region33 output value
+//Bit 7:0 bottom of region32 output value
+#define VPP_DNLP_CTRL_08 ((0x1d89 << 2) + 0xff000000)
+//Bit 31:24 bottom of region39 output value
+//Bit 23:16 bottom of region38 output value
+//Bit 15:8 bottom of region37 output value
+//Bit 7:0 bottom of region36 output value
+#define VPP_DNLP_CTRL_09 ((0x1d8a << 2) + 0xff000000)
+//Bit 31:24 bottom of region43 output value
+//Bit 23:16 bottom of region42 output value
+//Bit 15:8 bottom of region41 output value
+//Bit 7:0 bottom of region40 output value
+#define VPP_DNLP_CTRL_10 ((0x1d8b << 2) + 0xff000000)
+//Bit 31:24 bottom of region47 output value
+//Bit 23:16 bottom of region46 output value
+//Bit 15:8 bottom of region45 output value
+//Bit 7:0 bottom of region44 output value
+#define VPP_DNLP_CTRL_11 ((0x1d8c << 2) + 0xff000000)
+//Bit 31:24 bottom of region51 output value
+//Bit 23:16 bottom of region50 output value
+//Bit 15:8 bottom of region49 output value
+//Bit 7:0 bottom of region48 output value
+#define VPP_DNLP_CTRL_12 ((0x1d8d << 2) + 0xff000000)
+//Bit 31:24 bottom of region55 output value
+//Bit 23:16 bottom of region54 output value
+//Bit 15:8 bottom of region53 output value
+//Bit 7:0 bottom of region52 output value
+#define VPP_DNLP_CTRL_13 ((0x1d8e << 2) + 0xff000000)
+//Bit 31:24 bottom of region59 output value
+//Bit 23:16 bottom of region58 output value
+//Bit 15:8 bottom of region57 output value
+//Bit 7:0 bottom of region56 output value
+#define VPP_DNLP_CTRL_14 ((0x1d8f << 2) + 0xff000000)
+//Bit 31:24 bottom of region63 output value
+//Bit 23:16 bottom of region62 output value
+//Bit 15:8 bottom of region61 output value
+//Bit 7:0 bottom of region60 output value
+#define VPP_DNLP_CTRL_15 ((0x1d90 << 2) + 0xff000000)
+// `define VPP_PEAKING_HGAIN 8'h91 //32'h0
+// `define VPP_PEAKING_VGAIN 8'h92 //32'h0
+// `define VPP_PEAKING_NLP_1 8'h93 //32'h0
+// `define VPP_PEAKING_NLP_2 8'h94 //32'h0
+// `define VPP_PEAKING_NLP_3 8'h95 //32'h0
+// `define VPP_PEAKING_NLP_4 8'h96 //32'h0
+// `define VPP_PEAKING_NLP_5 8'h97 //32'h0
+// `define VPP_SHARP_LIMIT 8'h98 //32'h0
+// `define VPP_VLTI_CTRL 8'h99 //32'h0
+// `define VPP_HLTI_CTRL 8'h9a //32'h0
+// `define VPP_CTI_CTRL 8'h9b //32'h0
+#define VPP_SRSHARP0_CTRL ((0x1d91 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 srsharp_demo_split_sz srsharp demo top/bot left/right width
+//Bit 15:6 reserved
+//Bit 5:4 srsharp_demo_disp_post srsharp demo display postion
+//Bit 3 srsharp_demo_en srsharp demo enable
+//Bit 2 srsharp_c444to422_en srsharp format444 convert 422 enable
+//Bit 1, srsharp_buf_en srsharp buffer enable
+//Bit 0, srsharp_en srsharp enable
+#define VPP_SRSHARP1_CTRL ((0x1d92 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 srsharp_demo_split_sz srsharp demo top/bot left/right width
+//Bit 15:6 reserved
+//Bit 5:4 srsharp_demo_disp_post srsharp demo display postion
+//Bit 3 srsharp_demo_en srsharp demo enable
+//Bit 2 srsharp_c444to422_en srsharp format444 convert 422 enable
+//Bit 1, srsharp_buf_en srsharp buffer enable
+//Bit 0, srsharp_en srsharp enable
+#define VPP_DOLBY_CTRL ((0x1d93 << 2) + 0xff000000)
+//todo
+#define VPP_DAT_CONV_PARA0 ((0x1d94 << 2) + 0xff000000)
+#define VPP_DAT_CONV_PARA1 ((0x1d95 << 2) + 0xff000000)
+//todo
+#define VPP_SYNC_SEL0 ((0x1d96 << 2) + 0xff000000)
+//`define VPP_VADJ1_BLACK_VAL 8'h97 //32'h0
+//`define VPP_VADJ2_BLACK_VAL 8'h98 //32'h0
+//Bit 29 blue_stretch_cb_inc
+//Bit 28 blue_stretch_cr_inc
+//Bit 27 the MSB of blue_stretch_error_crp_inv[11:0]
+//Bit 26 the MSB of blue_stretch_error_crn_inv[11:0]
+//Bit 25 the MSB of blue_stretch_error_cbp_inv[11:0]
+//Bit 24 the MSB of blue_stretch_error_cbn_inv[11:0]
+//Bit 23:16 blue_stretch_gain
+//Bit 15:8 blue_stretch_gain_cb4cr
+//Bit 7:0 blue_stretch_luma_high
+#define VPP_BLUE_STRETCH_1 ((0x1d9c << 2) + 0xff000000)
+//Bit 31:27 blue_stretch_error_crp
+//Bit 26:16 the 11 LSB of blue_stretch_error_crp_inv[11:0]
+//Bit 15:11 blue_stretch_error_crn
+//Bit 10:0 the 11 LSB of blue_stretch_error_crn_inv[11:0]
+#define VPP_BLUE_STRETCH_2 ((0x1d9d << 2) + 0xff000000)
+//Bit 31:27 blue_stretch_error_cbp
+//Bit 26:16 the 11 LSB of blue_stretch_error_cbp_inv[11:0]
+//Bit 15:11 blue_stretch_error_cbn
+//Bit 10:0 the 11 LSB of blue_stretch_error_cbn_inv[11:0]
+#define VPP_BLUE_STRETCH_3 ((0x1d9e << 2) + 0xff000000)
+#define VPP_CCORING_CTRL ((0x1da0 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_bypass_ccoring_ythd // unsigned , default = 0 bypass_ccoring_ythd
+//Bit 15:8 ccoring_th // unsigned , default = 0 Chroma coring threshold
+//Bit 7:0 reserved
+//Bit 3:0 ccoring_slope // unsigned , default = 0 Chroma coring slope
+#define VPP_VE_ENABLE_CTRL ((0x1da1 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20 demo_ccoring_enable // unsigned , default = 0 demo chroma coring enable
+//Bit 19 demo_blackext_enable // unsigned , default = 0 demo black enxtension enable
+//Bit 18 demo_dnlp_enable // unsigned , default = 0 demo dynamic nonlinear luma processing enable
+//Bit 17 demo_hsvsharp_enable // unsigned , default = 0 demo hsvsharp enable
+//Bit 16 demo_bluestretch_enable // unsigned , default = 0 demo bluestretch enable
+//Bit 15:14 demo_disp_position // unsigned , default = 0 2'b00: demo adjust on top, 2'b01: demo adjust on bottom, 2'b10: demo adjust on left, 2'b11: demo adjust on right
+//Bit 13:7 reserved
+//Bit 6 sr4c0_path_sel // unsigned , default = 0
+//Bit 5 srscl_path_sel // unsigned , default = 0
+//Bit 4 ccoring_en // unsigned , default = 0 chroma coring enable
+//Bit 3 blackext_en // unsigned , default = 0 black enxtension enable
+//Bit 2 dnlp_en // unsigned , default = 0 dynamic nonlinear luma processing enable
+//Bit 1 hsvsharp_en // unsigned , default = 0 hsvsharp enable
+//Bit 0 blue_stretch_en // unsigned , default = 0 bluestretch enable
+#define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH ((0x1da2 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 ve_demo_left_top_screen_width // unsigned , default = 0 demo left or top screen width
+#define VPP_VE_DEMO_CENTER_BAR ((0x1da3 << 2) + 0xff000000)
+ //Bit 31 ve_demo_center_bar // unsigned , default = 0 center bar enable
+ //Bit 27:24 ve_demo_center_bar // unsigned , default = 0 center bar width (*2)
+ //Bit 23:16 ve_demo_center_bar // unsigned , default = 0 center bar Cr (*4)
+ //Bit 15:8 ve_demo_center_bar // unsigned , default = 0 center bar Cb (*4)
+ //Bit 7:0 ve_demo_center_bar // unsigned , default = 0 center bar y (*4)
+#define VPP_VE_H_V_SIZE ((0x1da4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 ve_line_length // unsigned , default = 780 ve_line_length
+//Bit 15:13 reserved
+//Bit 12:0 ve_pic_height // unsigned , default = 438 ve_pic_height
+#define VPP_OUT_H_V_SIZE ((0x1da5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 vppout_line_length / unsigned , default = 780 vppout_line_length
+//Bit 15:13 reserved
+//Bit 12:0 vppout_pic_height // unsigned , default = 438 vppout_pic_height
+#define VPP_IN_H_V_SIZE ((0x1da6 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 vppin_line_length / unsigned , default = 780 vppout_line_length
+//Bit 15:13 reserved
+//Bit 12:0 vppin_pic_height // unsigned , default = 438 vppout_pic_height
+#define VPP_VDO_MEAS_CTRL ((0x1da8 << 2) + 0xff000000)
+//Bit 31:11 reserved
+//Bit 10:0 vdo_meas_ctrl // unsigned , default = 0 vdo_meas_ctrl
+//Read only
+//19:16 ind_meas_count_n, every number of sync_span vsyncs, this counter add 1
+//15:0, high bit portion of counter
+#define VPP_VDO_MEAS_VS_COUNT_HI ((0x1da9 << 2) + 0xff000000)
+//Read only
+//31:0, low bit portion of counter
+#define VPP_VDO_MEAS_VS_COUNT_LO ((0x1daa << 2) + 0xff000000)
+//bit 11:9 vd2_sel, 001: select vd1_din, 010: select vd2_din, 011: select d2d3_l_din, 100: d2d3_r_din, otherwise no selection
+//bit 8:6 vd1_l_sel, 001: select vd1_din, 010: select vd2_din, 011: select d2d3_l_din, 100: d2d3_r_din, otherwise no selection
+//bit 5:3 vd1_r_sel, 001: select vd1_din, 010: select vd2_din, 011: select d2d3_l_din, 100: d2d3_r_din, otherwise no selection
+//note: the source vd1_l_sel selected cannot be used as the source of vd1_r_sel or vd2_sel
+// vd1_r_sel is useful only vd1_interleave_mode is not 00. And the source vd1_r_sel used can not used for the vd2_sel any more.
+//bit 2:0 vd1_interleave_mode, 000: no interleave, 001: pixel interleaving, 010: line interleaving, 011: 2 pixel interleaving,
+// 100: 2 line interleaving
+#define VPP_INPUT_CTRL ((0x1dab << 2) + 0xff000000)
+//bit 25:24 cti_bpf_sel
+//bit 20:16 cti_blend_factor_gama
+//bit 12:8 cti_blend_factor_beta
+//bit 4:0 cti_blend_factor_alpha
+#define VPP_CTI_CTRL2 ((0x1dac << 2) + 0xff000000)
+// `define VPP_PEAKING_SAT_THD1 8'had
+// `define VPP_PEAKING_SAT_THD2 8'hae
+// `define VPP_PEAKING_SAT_THD3 8'haf
+// `define VPP_PEAKING_SAT_THD4 8'hb0
+// `define VPP_PEAKING_SAT_THD5 8'hb1
+// `define VPP_PEAKING_SAT_THD6 8'hb2
+// `define VPP_PEAKING_SAT_THD7 8'hb3
+// `define VPP_PEAKING_SAT_THD8 8'hb4
+// `define VPP_PEAKING_SAT_THD9 8'hb5
+// `define VPP_PEAKING_GAIN_ADD1 8'hb6
+// `define VPP_PEAKING_GAIN_ADD2 8'hb7
+#define VPP_WRBAK_CTRL_SEC ((0x1dad << 2) + 0xff000000)
+#define VD1_BLEND_SRC_CTRL_SEC ((0x1dae << 2) + 0xff000000)
+#define VD2_BLEND_SRC_CTRL_SEC ((0x1daf << 2) + 0xff000000)
+#define OSD1_BLEND_SRC_CTRL_SEC ((0x1db0 << 2) + 0xff000000)
+#define OSD2_BLEND_SRC_CTRL_SEC ((0x1db1 << 2) + 0xff000000)
+//crc check , new add
+#define VPP_RO_CRCSUM ((0x1db2 << 2) + 0xff000000)
+#define VPP_CRC_CHK ((0x1db3 << 2) + 0xff000000)
+//bit 23:16 peaking_dnlp_gain, u5.3, DNLP effect
+//bit 15:8 peaking_factor
+//bit 5 peaking_dnlp_demo_en
+//bit 4 peaking_dnlp_en
+//bit 3:0 peaking_filter_sel
+#define VPP_PEAKING_DNLP ((0x1db8 << 2) + 0xff000000)
+//bit 24 sharp_demo_win_en
+//bit 23:12 sharp_demo_win_vend
+//bit 11:0 sharp_demo_win_vstart
+#define VPP_SHARP_DEMO_WIN_CTRL1 ((0x1db9 << 2) + 0xff000000)
+//bit 23:12 sharp_demo_win_hend
+//bit 11:0 sharp_demo_win_hstart
+#define VPP_SHARP_DEMO_WIN_CTRL2 ((0x1dba << 2) + 0xff000000)
+//Bit 31:24 front_hlti_neg_gain
+//Bit 23:16 front_hlti_pos_gain
+//Bit 15:8 front_hlti_threshold
+//Bit 7:0 front_hlti_blend_factor
+#define VPP_FRONT_HLTI_CTRL ((0x1dbb << 2) + 0xff000000)
+//Bit 31 front_enable, enable the front LTI&CTI before scaler
+//Bit 26:24 front_cti_step2
+//Bit 23:21 front_cti_step
+//Bit 20:16 front_cti_blend_factor
+//Bit 15 front_cti_median_mode
+//Bit 14:8 front_cti_threshold
+//Bit 7:0 front_cti_gain
+#define VPP_FRONT_CTI_CTRL ((0x1dbc << 2) + 0xff000000)
+//bit 29:28 front_hlti_step
+//bit 25:24 front_cti_bpf_sel
+//bit 20:16 front_cti_blend_factor_gama
+//bit 12:8 front_cti_blend_factor_beta
+//bit 4:0 front_cti_blend_factor_alpha
+#define VPP_FRONT_CTI_CTRL2 ((0x1dbd << 2) + 0xff000000)
+//vertical scaler phase step
+//Bit 27:0, 4.24 format
+#define VPP_OSD_VSC_PHASE_STEP ((0x1dc0 << 2) + 0xff000000)
+//Bit 31:16, botttom vertical scaler initial phase
+//Bit 15:0, top vertical scaler initial phase
+#define VPP_OSD_VSC_INI_PHASE ((0x1dc1 << 2) + 0xff000000)
+//Bit 24 osd vertical Scaler enable
+//Bit 23 osd_prog_interlace 0: current field is progressive, 1: current field is interlace
+//Bit 22:21 osd_vsc_double_line_mode, bit1, double input width and half input height, bit0, change line buffer becomes 2 lines
+//Bit 20 osd_vsc_phase0_always_en
+//Bit 19 osd_vsc_nearest_en
+//Bit 17:16 osd_vsc_bot_rpt_l0_num
+//Bit 14:11 osd_vsc_bot_ini_rcv_num
+//Bit 9:8 osd_vsc_top_rpt_l0_num
+//Bit 6:3 osd_vsc_top_ini_rcv_num
+//Bit 2:0 osd_vsc_bank_length
+#define VPP_OSD_VSC_CTRL0 ((0x1dc2 << 2) + 0xff000000)
+//horizontal scaler phase step
+//Bit 27:0, 4.24 format
+#define VPP_OSD_HSC_PHASE_STEP ((0x1dc3 << 2) + 0xff000000)
+//Bit 31:16, horizontal scaler initial phase1
+//Bit 15:0, horizontal scaler initial phase0
+#define VPP_OSD_HSC_INI_PHASE ((0x1dc4 << 2) + 0xff000000)
+//Bit 22 osd horizontal scaler enable
+//Bit 21 osd_hsc_double_pix_mode
+//Bit 20 osd_hsc_phase0_always_en
+//Bit 19 osd_hsc_nearest_en
+//Bit 17:16 osd_hsc_rpt_p0_num1
+//Bit 14:11 osd_hsc_ini_rcv_num1
+//Bit 9:8 osd_hsc_rpt_p0_num0
+//Bit 6:3 osd_hsc_ini_rcv_num0
+//Bit 2:0 osd_hsc_bank_length
+#define VPP_OSD_HSC_CTRL0 ((0x1dc5 << 2) + 0xff000000)
+//for 3D quincunx sub-sampling
+//bit 15:8 pattern, each patten 1 bit, from lsb -> msb
+//bit 6:4 pattern start
+//bit 2:0 pattern end
+#define VPP_OSD_HSC_INI_PAT_CTRL ((0x1dc6 << 2) + 0xff000000)
+//bit 31:24, componet 0
+//bit 23:16, component 1
+//bit 15:8, component 2
+//bit 7:0 component 3, alpha
+#define VPP_OSD_SC_DUMMY_DATA ((0x1dc7 << 2) + 0xff000000)
+//Bit 14 osc_sc_din_osd1_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 13 osc_sc_din_osd2_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 12 osc_sc_dout_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 12 osc_sc_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 11:4 default alpha for vd1 or vd2 if they are selected as the source
+//Bit 3 osd scaler path enable
+//Bit 1:0 osd_sc_sel, 00: select osd1 input, 01: select osd2 input, 10: select vd1 input, 11: select vd2 input after matrix
+#define VPP_OSD_SC_CTRL0 ((0x1dc8 << 2) + 0xff000000)
+//Bit 28:16 OSD scaler input width minus 1
+//Bit 12:0 OSD scaler input height minus 1
+#define VPP_OSD_SCI_WH_M1 ((0x1dc9 << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output horizontal start
+//Bit 12:0 OSD scaler output horizontal end
+#define VPP_OSD_SCO_H_START_END ((0x1dca << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output vertical start
+//Bit 12:0 OSD scaler output vertical end
+#define VPP_OSD_SCO_V_START_END ((0x1dcb << 2) + 0xff000000)
+//Because there are many coefficients used in the vertical filter and horizontal filters,
+//indirect access the coefficients of vertical filter and horizontal filter is used.
+//For vertical filter, there are 33x4 coefficients
+//For horizontal filter, there are 33x4 coefficients
+//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
+//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
+//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
+//Bit 8 type of index, 0: vertical coef, 1: horizontal coef
+//Bit 6:0 coef index
+#define VPP_OSD_SCALE_COEF_IDX ((0x1dcc << 2) + 0xff000000)
+//coefficients for vertical filter and horizontal filter
+#define VPP_OSD_SCALE_COEF ((0x1dcd << 2) + 0xff000000)
+//Bit 12:0 line number use to generate interrupt when line == this number
+#define VPP_INT_LINE_NUM ((0x1dce << 2) + 0xff000000)
+#define VPP_XVYCC_MISC ((0x1dcf << 2) + 0xff000000)
+// new add lti/cti in 120924
+//Bit 3: 0 //default== 0 reg_hlti_dn_flt_coe[0]
+//Bit 7: 4 //default== 0 reg_hlti_dn_flt_coe[1]
+//Bit 11: 8 //default== 0 reg_hlti_dn_flt_coe[2]
+//Bit 15:12 //default== 2 reg_hlti_dn_flt_coe[3]
+//Bit 19:16 //default== 4 reg_hlti_dn_flt_coe[4]
+//Bit 22:20 //default== 3 reg_hlti_dn_flt_nrm u3: 3~7
+#define VPP_HLTI_DN_FLT ((0x1dd0 << 2) + 0xff000000)
+//Bit 7: 0 //default== 8 reg_hlti_bst_gain u8, norm 16 as "1"
+//Bit 15: 8 //default== 20 reg_hlti_bst_core u8, norm 32 as "1"
+//Bit 23:16 //default== 32 reg_hlti_oob_gain u8, norm 32 as "1"
+//Bit 28:24 //default== 0 reg_hlti_oob_core u5
+#define VPP_HLTI_GAIN ((0x1dd1 << 2) + 0xff000000)
+//Bit 7: 0 //default== 2 reg_hlti_clp_ofst u8,
+//Bit 8 //default== 0 reg_hlti_clp_mode u1,
+//Bit 11: 9 //default== 1 reg_hlti_clp_wind u3,
+//Bit 14:12 //default== 1 reg_hlti_bst_fltr u3,
+//Bit 15 //default== 1 reg_hlti_enable u1,
+#define VPP_HLTI_PARA ((0x1dd2 << 2) + 0xff000000)
+//Bit 3: 0 //default== 0 reg_hcti_dn_flt_coe[0]
+//Bit 7: 4 //default== 0 reg_hcti_dn_flt_coe[1]
+//Bit 11: 8 //default== 1 reg_hcti_dn_flt_coe[2]
+//Bit 15:12 //default== 2 reg_hcti_dn_flt_coe[3]
+//Bit 19:16 //default== 2 reg_hcti_dn_flt_coe[4]
+//Bit 22:20 //default== 3 reg_hcti_dn_flt_nrm u3: 3~7
+#define VPP_HCTI_DN_FLT ((0x1dd3 << 2) + 0xff000000)
+//Bit 7: 0 //default== 48 reg_hcti_bst_gain u8, norm 16 as "1"
+//Bit15: 8 //default== 17 reg_hcti_bst_core u8, norm 32 as "1"
+//Bit23:16 //default== 16 reg_hcti_oob_gain u8, norm 32 as "1"
+//Bit28:24 //default== 0 reg_hcti_oob_core u5
+#define VPP_HCTI_GAIN ((0x1dd4 << 2) + 0xff000000)
+//Bit 7: 0 //default== 0 reg_hcti_clp_ofst u8,
+//Bit 8 //default== 1 reg_hcti_clp_mode u1,
+//Bit 11: 9 //default== 3 reg_hcti_clp_wind u3,
+//Bit 14:12 //default== 6 reg_hcti_bst_fltr u3,
+//Bit 15 //default== 1 reg_hcti_enable u1,
+#define VPP_HCTI_PARA ((0x1dd5 << 2) + 0xff000000)
+//Bit 7: 0 //default== 48 reg_vcti_bst_gain u8, normalize 16 as "1"
+//Bit 15: 8 //default== 10 reg_vcti_bst_core u8
+//Bit 19:16 //default== 10 reg_vcti_clp_ofst u4
+//Bit 20 //default== 1 reg_vcti_clp_wind u1, 0: wind 3, 1: wind5
+#define VPP_VCTI_PARA ((0x1dd6 << 2) + 0xff000000)
+//`define VPP_MATRIX_PROBE_COLOR1 8'hd7 //defined before
+//Bit 31 //default== 0, urgent fifo hold enable
+//Bit 28:12 //default== 0, urgent fifo hold line threshold
+//Bit 15 //default== 0, urgent_ctrl_en
+//Bit 14 //default== 0, urgent_wr, if true for write buffer
+//Bit 13 //default== 0, out_inv_en
+//Bit 12 //default == 0, urgent_ini_value
+//Bit 11:6 //default == 0, up_th up threshold
+//Bit 5:0 //default == 0, dn_th dn threshold
+#define VPP_OFIFO_URG_CTRL ((0x1dd8 << 2) + 0xff000000)
+#define VPP_CLIP_MISC0 ((0x1dd9 << 2) + 0xff000000)
+//Bit 29:20 // default == 1023, final clip r channel top
+//Bit 19:10 // default == 1023, final clip g channel top
+//Bit 9: 0 // default == 1023, final clip b channel top
+#define VPP_CLIP_MISC1 ((0x1dda << 2) + 0xff000000)
+//Bit 29:20 // default == 0, final clip r channel bottom
+//Bit 19:10 // default == 0, final clip g channel bottom
+//Bit 9: 0 // default == 0, final clip b channel bottom
+#define VPP_MATRIX_COEF13_14 ((0x1ddb << 2) + 0xff000000)
+//Bit 28:16 // default == 0, matrix coef13
+//Bit 12:0 // default == 0, matrix coef14
+#define VPP_MATRIX_COEF23_24 ((0x1ddc << 2) + 0xff000000)
+//Bit 28:16 // default == 0, matrix coef23
+//Bit 12:0 // default == 0, matrix coef24
+#define VPP_MATRIX_COEF15_25 ((0x1ddd << 2) + 0xff000000)
+//Bit 28:16 // default == 0, matrix coef15
+//Bit 12:0 // default == 0, matrix coef25
+#define VPP_MATRIX_CLIP ((0x1dde << 2) + 0xff000000)
+//Bit 7:5 // default == 0, mat rs
+//Bit 4:3 // default == 0, mat clmod
+//Bit 2:0 // default == 0, mat clip enable
+#define VPP_XVYCC_MISC0 ((0x1ddf << 2) + 0xff000000)
+//Bit 29:20 // default == 1023, xvycc clip r channel top
+//Bit 19:10 // default == 1023, xvycc clip g channel top
+//Bit 9: 0 // default == 1023, xvycc clip b channel top
+#define VPP_XVYCC_MISC1 ((0x1de0 << 2) + 0xff000000)
+//Bit 29:20 // default == 0, xvycc clip r channel bottom
+//Bit 19:10 // default == 0, xvycc clip g channel bottom
+//Bit 9: 0 // default == 0, xvycc clip b channel bottom
+#define VPP_VD1_CLIP_MISC0 ((0x1de1 << 2) + 0xff000000)
+//Bit 29:20 // default == 1023, vd1 clip r channel top
+//Bit 19:10 // default == 1023, vd1 clip g channel top
+//Bit 9: 0 // default == 1023, vd1 clip b channel top
+#define VPP_VD1_CLIP_MISC1 ((0x1de2 << 2) + 0xff000000)
+//Bit 29:20 // default == 0, vd1 clip r channel bottom
+//Bit 19:10 // default == 0, vd1 clip g channel bottom
+//Bit 9: 0 // default == 0, vd1 clip b channel bottom
+#define VPP_VD2_CLIP_MISC0 ((0x1de3 << 2) + 0xff000000)
+//Bit 29:20 // default == 1023, vd2 clip r channel top
+//Bit 19:10 // default == 1023, vd2 clip g channel top
+//Bit 9: 0 // default == 1023, vd2 clip b channel top
+#define VPP_VD2_CLIP_MISC1 ((0x1de4 << 2) + 0xff000000)
+//Bit 29:20 // default == 0, vd2 clip r channel bottom
+//Bit 19:10 // default == 0, vd2 clip g channel bottom
+//Bit 9: 0 // default == 0, vd2 clip b channel bottom
+#define VPP_VD2_HDR_IN_SIZE ((0x1df0 << 2) + 0xff000000)
+//Bit 31:16 // default == 0
+//Bit 15:0 // default == 0
+#define VPP_OSD1_IN_SIZE ((0x1df1 << 2) + 0xff000000)
+//Bit 31:16 // default == 0
+//Bit 15:0 // default == 0
+#define VPP_GCLK_CTRL2 ((0x1df2 << 2) + 0xff000000)
+//`define VPP_BLEND_SRC_SEL 8'hf3
+#define VD2_PPS_DUMMY_DATA ((0x1df4 << 2) + 0xff000000)
+#define VPP_OSD1_BLD_H_SCOPE ((0x1df5 << 2) + 0xff000000)
+#define VPP_OSD1_BLD_V_SCOPE ((0x1df6 << 2) + 0xff000000)
+#define VPP_OSD2_BLD_H_SCOPE ((0x1df7 << 2) + 0xff000000)
+#define VPP_OSD2_BLD_V_SCOPE ((0x1df8 << 2) + 0xff000000)
+#define VPP_WRBAK_CTRL ((0x1df9 << 2) + 0xff000000)
+#define VPP_SLEEP_CTRL ((0x1dfa << 2) + 0xff000000)
+#define VD1_BLEND_SRC_CTRL ((0x1dfb << 2) + 0xff000000)
+#define VD2_BLEND_SRC_CTRL ((0x1dfc << 2) + 0xff000000)
+#define OSD1_BLEND_SRC_CTRL ((0x1dfd << 2) + 0xff000000)
+#define OSD2_BLEND_SRC_CTRL ((0x1dfe << 2) + 0xff000000)
+#define VPP_OSD_SCALE_CTRL ((0x1dff << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_regs.h
+//
+//`include "v2regs.h"
+//
+// Reading file: viu2_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: VIU2_VCBUS_BASE = 0x1e
+// -----------------------------------------------
+//------------------------------------------------------------------------------
+// VIU2 top-level registers
+//------------------------------------------------------------------------------
+// Bit 0 RW, osd1_reset
+// Bit 1 RW, OSD1_reset
+// Bit 2 RW, vd1_reset
+// Bit 3 RW, vd1_fmt_reset
+// Bit 7 RW, vpp_reset
+#define VIU2_SW_RESET ((0x1e01 << 2) + 0xff000000)
+#define VIU2_SW_RESET0 ((0x1e02 << 2) + 0xff000000)
+// Bit 0 RW, software reset for mcvecrd_mif
+// Bit 1 RW, software reset for mcinfowr_mif
+// Bit 2 RW, software reset for mcinford_mif
+#define VIU2_SECURE_REG ((0x1e05 << 2) + 0xff000000)
+//bit 8 if true, vsync interrup is generate only field == 0
+//bit 7:0 fix_disable
+#define VIU2_MISC_CTRL0 ((0x1e06 << 2) + 0xff000000)
+#define VIU2_DATA_SEC_IN ((0x1e07 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// VPP2 top-level registers
+//------------------------------------------------------------------------------
+// Bit 31 vd1_bgosd_exchange_en for preblend
+// Bit 30 vd1_bgosd_exchange_en for postblend
+// bit 28 color management enable
+// Bit 27, reserved
+// Bit 26:18, reserved
+// Bit 17, OSD1 enable for preblend
+// Bit 16, osd1 enable for preblend
+// Bit 15, reserved
+// Bit 14, vd1 enable for preblend
+// Bit 13, OSD1 enable for postblend
+// Bit 12, osd1 enable for postblend
+// Bit 11, reserved
+// Bit 10, vd1 enable for postblend
+// Bit 9, if true, osd1 is alpha premultipiled
+// Bit 8, if true, OSD1 is alpha premultipiled
+// Bit 7, postblend module enable
+// Bit 6, preblend module enable
+// Bit 5, if true, OSD1 foreground compared with osd1 in preblend
+// Bit 4, if true, OSD1 foreground compared with osd1 in postblend
+// Bit 3,
+// Bit 2, if true, disable resetting async fifo every vsync, otherwise every vsync
+// the aync fifo will be reseted.
+// Bit 1,
+// Bit 0 if true, the output result of VPP is saturated
+#define VPP2_MISC ((0x1e26 << 2) + 0xff000000)
+//Bit 31:20 ofifo line length minus 1
+//Bit 19 if true invert input vs
+//Bit 18 if true invert input hs
+//Bit 17 force top/bottom field, enable
+//Bit 16 force top/bottom field, 0: top, 1: bottom
+//Bit 15 force one go_field, one pluse, write only
+//Bit 14 force one go_line, one pluse, write only
+//Bit 12:0 ofifo size (actually only bit 10:1 is valid), always even number
+#define VPP2_OFIFO_SIZE ((0x1e27 << 2) + 0xff000000)
+//Read only
+//Bit 28:17 current scale out fifo counter
+//Bit 16:12 current afifo counter
+//Bit 11:0 current ofifo counter
+#define VPP2_FIFO_STATUS ((0x1e28 << 2) + 0xff000000)
+//Bit 12:0 line number use to generate interrupt when line == this number
+#define VPP2_INT_LINE_NUM ((0x1e20 << 2) + 0xff000000)
+#define VPP2_OFIFO_URG_CTRL ((0x1e21 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// OSD1 registers
+//------------------------------------------------------------------------------
+// Bit 31 Reserved
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// 0=use gated clock for low power.
+// Bit 29 R, test_rd_dsr
+// Bit 28 R, osd_done
+// Bit 27:24 R, osd_blk_mode
+// Bit 23:22 R, osd_blk_ptr
+// Bit 21 R, osd_enable
+//
+// Bit 20:12 RW, global_alpha
+// Bit 11 RW, test_rd_en
+// Bit 10 RW, hl2_en
+// Bit 9 RW, hl1_en
+// Bit 8: 5 RW, ctrl_mtch_y
+// Bit 4 RW, ctrl_422to444
+// Bit 3: 0 RW, osd_blk_enable. Bit 0 to enable block 0: 1=enable, 0=disable;
+// Bit 1 to enable block 1, and so on.
+#define VIU2_OSD1_CTRL_STAT ((0x1e30 << 2) + 0xff000000)
+// Bit 31:26 Reserved
+// Bit 25:16 R, fifo_count
+// Bit 15: 6 Reserved
+// Bit 5: 4 RW, hold_fifo_lines[6:5]
+// Bit 3 RW, rgb2yuv_full_range
+// Bit 2 RW, alpha_9b_mode
+// Bit 1 RW, reserved
+// Bit 0 RW, color_expand_mode
+#define VIU2_OSD1_CTRL_STAT2 ((0x1e4d << 2) + 0xff000000)
+// Bit 31: 9 Reserved
+// Bit 8 RW, 0 = Write LUT, 1 = Read LUT
+// Bit 7: 0 RW, lut_addr
+#define VIU2_OSD1_COLOR_ADDR ((0x1e31 << 2) + 0xff000000)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define VIU2_OSD1_COLOR ((0x1e32 << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, hl[1-2]_h/v_start
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, hl[1-2]_h/v_end
+#define VIU2_OSD1_HL1_H_START_END ((0x1e33 << 2) + 0xff000000)
+#define VIU2_OSD1_HL1_V_START_END ((0x1e34 << 2) + 0xff000000)
+#define VIU2_OSD1_HL2_H_START_END ((0x1e35 << 2) + 0xff000000)
+#define VIU2_OSD1_HL2_V_START_END ((0x1e36 << 2) + 0xff000000)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define VIU2_OSD1_TCOLOR_AG0 ((0x1e37 << 2) + 0xff000000)
+#define VIU2_OSD1_TCOLOR_AG1 ((0x1e38 << 2) + 0xff000000)
+#define VIU2_OSD1_TCOLOR_AG2 ((0x1e39 << 2) + 0xff000000)
+#define VIU2_OSD1_TCOLOR_AG3 ((0x1e3a << 2) + 0xff000000)
+// Bit 31:24 Reserved
+// Bit 23:16 RW, tbl_addr
+// Bit 15 RW, little_endian: 0=big endian, 1=little endian
+// Bit 14 RW, rpt_y
+// Bit 13:12 RW, interp_ctrl. 0x=No interpolation; 10=Interpolate with previous
+// pixel; 11=Interpolate with the average value
+// between previous and next pixel.
+// Bit 11: 8 RW, osd_blk_mode
+// Bit 7 RW, rgb_en
+// Bit 6 RW, tc_alpha_en
+// Bit 5: 2 RW, color_matrix
+// Bit 1 RW, interlace_en
+// Bit 0 RW, interlace_sel_odd
+#define VIU2_OSD1_BLK0_CFG_W0 ((0x1e3b << 2) + 0xff000000)
+#define VIU2_OSD1_BLK1_CFG_W0 ((0x1e3f << 2) + 0xff000000)
+#define VIU2_OSD1_BLK2_CFG_W0 ((0x1e43 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK3_CFG_W0 ((0x1e47 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, x_end
+// Bit 15:13 Reserved
+// Bit 12: 0 RW, x_start
+#define VIU2_OSD1_BLK0_CFG_W1 ((0x1e3c << 2) + 0xff000000)
+#define VIU2_OSD1_BLK1_CFG_W1 ((0x1e40 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK2_CFG_W1 ((0x1e44 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK3_CFG_W1 ((0x1e48 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, y_end
+// Bit 15:13 Reserved
+// Bit 12: 0 RW, y_start
+#define VIU2_OSD1_BLK0_CFG_W2 ((0x1e3d << 2) + 0xff000000)
+#define VIU2_OSD1_BLK1_CFG_W2 ((0x1e41 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK2_CFG_W2 ((0x1e45 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK3_CFG_W2 ((0x1e49 << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, h_end
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, h_start
+#define VIU2_OSD1_BLK0_CFG_W3 ((0x1e3e << 2) + 0xff000000)
+#define VIU2_OSD1_BLK1_CFG_W3 ((0x1e42 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK2_CFG_W3 ((0x1e46 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK3_CFG_W3 ((0x1e4a << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, v_end
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, v_start
+#define VIU2_OSD1_BLK0_CFG_W4 ((0x1e64 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK1_CFG_W4 ((0x1e65 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK2_CFG_W4 ((0x1e66 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK3_CFG_W4 ((0x1e67 << 2) + 0xff000000)
+// Bit 31 RW, burst_len_sel[2] of [2:0]
+// Bit 30 RW, byte_swap: In addition to endian control, further define
+// whether to swap upper and lower byte within a 16-bit mem word.
+// 0=No swap; 1=Swap data[15:0] to be {data[7:0], data[15:8]}
+// Bit 29 RW, div_swap : swap the 2 64bits words in 128 bit word
+// Bit 28:24 RW, fifo_lim : when osd fifo is small than the fifo_lim*16, closed the rq port of osd_rd_mif
+// Bit 23:22 RW, fifo_ctrl: 00 : for 1 word in 1 burst , 01 : for 2words in 1burst, 10: for 4words in 1burst, 11: reserved
+// Bit 21:20 R, fifo_st. 0=IDLE, 1=FILL, 2=ABORT
+// Bit 19 R, fifo_overflow
+// Bit 18:12 RW, fifo_depth_val, max value=64: set actual fifo depth to fifo_depth_val*8.
+// Bit 11:10 RW, burst_len_sel[1:0] of [2:0]. 0=24(default), 1=32, 2=48, 3=64, 4=96, 5=128.
+// Bit 9: 5 RW, hold_fifo_lines[4:0]
+// Bit 4 RW, clear_err: one pulse to clear fifo_overflow
+// Bit 3 RW, fifo_sync_rst
+// Bit 2: 1 RW, endian
+// Bit 0 RW, urgent
+#define VIU2_OSD1_FIFO_CTRL_STAT ((0x1e4b << 2) + 0xff000000)
+// Bit 31:24 R, Y or R
+// Bit 23:16 R, Cb or G
+// Bit 15: 8 R, Cr or B
+// Bit 7: 0 R, Output Alpha[8:1]
+#define VIU2_OSD1_TEST_RDDATA ((0x1e4c << 2) + 0xff000000)
+// Bit 15 RW, prot_en: 1=Borrow PROT's FIFO storage, either for rotate or non-rotate.
+// Bit 12: 0 RW, effective FIFO size when prot_en=1.
+#define VIU2_OSD1_PROT_CTRL ((0x1e4e << 2) + 0xff000000)
+#define VIU2_OSD1_MALI_UNPACK_CTRL ((0x1e4f << 2) + 0xff000000)
+#define VIU2_OSD1_DIMM_CTRL ((0x1e50 << 2) + 0xff000000)
+//`define VIU2_MATRIX_CTRL 8'h70
+#define VIU2_OSD1_MATRIX_COEF00_01 ((0x1e70 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_COEF02_10 ((0x1e71 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_COEF11_12 ((0x1e72 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_COEF20_21 ((0x1e73 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_COEF22 ((0x1e74 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_COEF13_14 ((0x1e75 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_COEF23_24 ((0x1e76 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_COEF15_25 ((0x1e77 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_CLIP ((0x1e78 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_OFFSET0_1 ((0x1e79 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_OFFSET2 ((0x1e7a << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_PRE_OFFSET0_1 ((0x1e7b << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_PRE_OFFSET2 ((0x1e7c << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_EN_CTRL ((0x1e7d << 2) + 0xff000000)
+#define VIU2_RMIF_CTRL0 ((0x1e80 << 2) + 0xff000000)
+#define VIU2_RMIF_CTRL1 ((0x1e81 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_sync_sel // unsigned , default = 0, axi canvas id sync with frm rst
+//Bit 23:16 reg_canvas_id // unsigned , default = 0, axi canvas id num
+//Bit 15 reserved
+//Bit 14:12 reg_cmd_intr_len // unsigned , default = 1, interrupt send cmd when how many series axi cmd,
+ // 0=12 1=16 2=24 3=32 4=40 5=48 6=56 7=64
+//Bit 11:10 reg_cmd_req_size // unsigned , default = 1, how many room fifo have, then axi send series req, 0=16 1=32 2=24 3=64
+//Bit 9:8 reg_burst_len // unsigned , default = 2, burst type: 0-single 1-bst2 2-bst4
+//Bit 7 reg_swap_64bit // unsigned , default = 0, 64bits of 128bit swap enable
+//Bit 6 reg_big_endian // unsigned , default = 0, big endian enable
+//Bit 5 reg_y_rev // unsigned , default = 0, vertical reverse enable
+//Bit 4 reg_x_rev // unsigned , default = 0, horizontal reverse enable
+//Bit 3 reserved
+//Bit 2:0 reg_pack_mode // unsigned , default = 1, 0:4bit 1:8bit 2:16bit 3:32bit 4:64bit 5:128bit
+#define VIU2_RMIF_CTRL2 ((0x1e82 << 2) + 0xff000000)
+//Bit 31 reg_sw_rst // unsigned , default = 0,
+//Bit 30:17 reserved
+//Bit 16:0 reg_urgent_ctrl // unsigned , default = 0, urgent control reg :
+ // 16 reg_ugt_init : urgent initial value
+ // 15 reg_ugt_en : urgent enable
+ // 14 reg_ugt_type : 1= wrmif 0=rdmif
+ // 7:4 reg_ugt_top_th: urgent top threshold
+ // 3:0 reg_ugt_bot_th: urgent bottom threshold
+#define VIU2_RMIF_SCOPE_X ((0x1e83 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_x_end // unsigned , default = 0, the canvas hor end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_x_start // unsigned , default = 0, the canvas hor start pixel position
+#define VIU2_RMIF_SCOPE_Y ((0x1e84 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_y_end // unsigned , default = 0, the canvas ver end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_y_start // unsigned , default = 0, the canvas ver start pixel positio
+#define VIU2_ROT_BLK_SIZE ((0x1e85 << 2) + 0xff000000)
+#define VIU2_ROT_LBUF_SIZE ((0x1e86 << 2) + 0xff000000)
+#define VIU2_ROT_FMT_CTRL ((0x1e87 << 2) + 0xff000000)
+#define VIU2_ROT_WIND_CTRL ((0x1e88 << 2) + 0xff000000)
+#define VIU2_ROT_OUT_VCROP ((0x1e89 << 2) + 0xff000000)
+#define VIU2_ROT_BUF_SIZE ((0x1e8a << 2) + 0xff000000)
+#define VIU2_ROT_RO_MIF0_STAT ((0x1e8b << 2) + 0xff000000)
+//Bit 15:0 reg_status // unsigned ,
+#define VIU2_ROT_RO_MIF1_STAT ((0x1e8c << 2) + 0xff000000)
+#define VIU2_ROT_RO_STAT ((0x1e8d << 2) + 0xff000000)
+#define VIU2_GAINOFF_GCLK_CTRL ((0x1ea0 << 2) + 0xff000000)
+#define VIU2_GAINOFF_CTRL0 ((0x1ea1 << 2) + 0xff000000)
+#define VIU2_GAINOFF_CTRL1 ((0x1ea2 << 2) + 0xff000000)
+#define VIU2_GAINOFF_CTRL2 ((0x1ea3 << 2) + 0xff000000)
+#define VIU2_GAINOFF_CTRL3 ((0x1ea4 << 2) + 0xff000000)
+#define VIU2_GAINOFF_CTRL4 ((0x1ea5 << 2) + 0xff000000)
+#define VPP2_CRC_CHK ((0x1eb0 << 2) + 0xff000000)
+#define VPP2_RO_CRCSUM ((0x1eb1 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: viu2_regs.h
+//
+//
+// Reading file: vregs_clk1.h
+//
+//===========================================================================
+// Video Interface Registers 0xa00 - 0xaff
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VIUB_VCBUS_BASE = 0x20
+// -----------------------------------------------
+#define VIUB_ADDR_START ((0x2000 << 2) + 0xff000000)
+#define VIUB_ADDR_END ((0x20ff << 2) + 0xff000000)
+//`define TRACE_REG 8'ff
+//------------------------------------------------------------------------------
+// VIU top-level registers
+//------------------------------------------------------------------------------
+// Bit 0 RW, osd1_reset
+// Bit 1 RW, osd2_reset
+// Bit 2 RW, vd1_reset
+// Bit 3 RW, vd1_fmt_reset
+// Bit 4 RW, vd2_reset
+// Bit 5 RW, vd2_fmt_reset
+// Bit 6 RW, di_dsr1to2_reset
+// Bit 7 RW, vpp_reset
+// Bit 8 RW, di_if1_reset
+// Bit 9 RW, di_if1_fmt_reset
+// Bit 10 RW, di_inp_reset
+// Bit 11 RW, di_inp_fmt_reset
+// Bit 12 RW, di_mem_reset
+// Bit 13 RW, di_mem_fmt_reset
+// Bit 14 RW, di_nr_wr_mif_reset
+// Bit 15 RW, dein_wr_mif_reset
+// Bit 16 RW, di_chan2_mif_reset
+// Bit 17 RW, di_mtn_wr_mif_reset
+// Bit 18 RW, di_mtn_rd_mif_reset
+// Bit 19 RW, di_mad_reset
+// Bit 20 RW, vdin0_reset
+// Bit 21 RW, vdin1_reset
+// Bit 22 RW, nrin_mux_reset
+// Bit 23 RW, vdin0_wr_reset
+// Bit 24 RW, vdin1_wr_reset
+// Bit 25 RW, reserved
+// Bit 26 RW, d2d3_reset
+// Bit 27 RW, di_cont_wr_mif_reset
+// Bit 28 RW, di_cont_rd_mif_reset
+#define VIUB_SW_RESET ((0x2001 << 2) + 0xff000000)
+#define VIUB_SW_RESET0 ((0x2002 << 2) + 0xff000000)
+// Bit 0 RW, software reset for mcvecrd_mif
+// Bit 1 RW, software reset for mcinfowr_mif
+// Bit 2 RW, software reset for mcinford_mif
+#define DI_AFBCE_CTRL ((0x2003 << 2) + 0xff000000)
+#define VIUB_SECURE_ST_RO ((0x2004 << 2) + 0xff000000)
+//bit 8 if true, vsync interrup is generate only field == 0
+//bit 7:0 fix_disable
+#define VIUB_MISC_CTRL0 ((0x2006 << 2) + 0xff000000)
+#define VIUB_GCLK_CTRL0 ((0x2007 << 2) + 0xff000000)
+//// gclk_ctrl0_gl[ 0] : def=1 di_top_wrap clk enable
+////
+//// gclk_ctrl0_gl[ 8] : def=0 mad pre clock enable, from mad clock
+//// gclk_ctrl0_gl[ 9] : def=0 mad post clock enable, from mad clock
+//// gclk_ctrl0_gl[10] : def=0 div clock enable, di slow clock including di&mcdi
+//// gclk_ctrl0_gl[11] : def=0 mcdi clock enable, from div clock
+//// gclk_ctrl0_gl[12] : def=0 di post clock enable, from div clock
+//// gclk_ctrl0_gl[13] : def=0 reserved
+//// gclk_ctrl0_gl[14] : def=1 di_no_clk_gate, for old di
+//// gclk_ctrl0_gl[15] : def=0 di_gate_all, for old di
+#define VIUB_GCLK_CTRL1 ((0x2008 << 2) + 0xff000000)
+//// gclk_ctrl1_gl[ 1: 0] : def=2'b00 mif-sub-arb clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[ 3: 2] : def=2'b00 if1 rdmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[ 5: 4] : def=2'b00 if2 rdmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[ 7: 6] : def=2'b00 de wrmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[ 9: 8] : def=2'b00 mtnrd post mif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[11:10] : def=2'b00 mcdi post mif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[17:16] : def=2'b00 inp rdmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[19:18] : def=2'b00 mem rdmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[21:20] : def=2'b00 chan rdmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[23:22] : def=2'b00 nr wrmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[25:24] : def=2'b00 mtn mif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[27:26] : def=2'b00 mcdi pre mif clock gate ctrl [1]: clock valid, [0]: clock close
+////
+#define VIUB_GCLK_CTRL2 ((0x2009 << 2) + 0xff000000)
+//// gclk_ctrl_pre[ 1: 0] : def=2'b00 nr clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_pre[ 3: 2] : def=2'b00 pd clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_pre[ 5: 4] : def=2'b00 mtn det clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_pre[ 7: 6] : def=2'b00 debanding clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_pre[ 9: 8] : def=2'b00 dnr clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_pre[11:10] : def=2'b00 nr&dnr blend clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_pre[13:12] : def=2'b00 mcdi clock gate ctrl [1]: clock valid, [0]: clock close
+#define VIUB_GCLK_CTRL3 ((0x200a << 2) + 0xff000000)
+//// gclk_ctrl_post[ 1: 0] : def=2'b00 di blend clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_post[ 3: 2] : def=2'b00 ei clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_post[ 5: 4] : def=2'b00 ei_0 clock gate ctrl [1]: clock valid, [0]: clock close
+#define DI_DBG_CTRL ((0x200b << 2) + 0xff000000)
+#define DI_DBG_CTRL1 ((0x200c << 2) + 0xff000000)
+#define DI_DBG_SRDY_INF ((0x200d << 2) + 0xff000000)
+#define DI_DBG_RRDY_INF ((0x200e << 2) + 0xff000000)
+#define VIUB_SECURE_REG ((0x200f << 2) + 0xff000000)
+#define DI_PRE_SEC_IN ((0x2010 << 2) + 0xff000000)
+#define DI_POST_SEC_IN ((0x2011 << 2) + 0xff000000)
+//`define DI_IF2_GEN_REG 8'h10
+//`define DI_IF2_CANVAS0 8'h11
+//`define DI_IF2_LUMA_X0 8'h12
+//`define DI_IF2_LUMA_Y0 8'h13
+//`define DI_IF2_CHROMA_X0 8'h14
+//`define DI_IF2_CHROMA_Y0 8'h15
+//`define DI_IF2_RPT_LOOP 8'h16
+//`define DI_IF2_LUMA0_RPT_PAT 8'h17
+//`define DI_IF2_CHROMA0_RPT_PAT 8'h18
+//`define DI_IF2_DUMMY_PIXEL 8'h19
+//`define DI_IF2_LUMA_FIFO_SIZE 8'h1a
+//`define DI_IF2_RANGE_MAP_Y 8'h1b
+//`define DI_IF2_RANGE_MAP_CB 8'h1c
+//`define DI_IF2_RANGE_MAP_CR 8'h1d
+//`define DI_IF2_GEN_REG2 8'h1e
+//`define DI_IF2_FMT_CTRL 8'h1f
+//`define DI_IF2_FMT_W 8'h20
+//
+//`define DI_IF2_URGENT_CTRL 8'h21
+//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path
+//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path
+//`define DI_IF2_GEN_REG3 8'h22
+//bit 31:1, reversed
+//bit 0, cntl_64bit_rev
+//==================================
+#define DI_EI_DRT_CTRL ((0x2028 << 2) + 0xff000000)
+//Bit 31, reg_rectg_en ;u1
+//Bit 30, reg_recbld_en ;u1
+//Bit 29:28, reg_rectg_ws ;u2
+//Bit 27, reserved
+//Bit 26:24, reg_abq_margin ;u3
+//Bit 23, reserved
+//Bit 22:20, reg_trend_mg ;u3
+//Bit 19:16, reg_int_d16xc1 ;u4
+//Bit 15:14, reserved
+//Bit 13: 8, reg_int_chlmt1 ;u6
+//Bit 7, reserved
+//Bit 6: 4, reg_nscheck_thrd ;u3
+//Bit 3, reserved
+//Bit 2: 0, reg_horsl_ws ;u3
+#define DI_EI_DRT_PIXTH ((0x2029 << 2) + 0xff000000)
+//Bit 31:24, reg_min_pix ;u8
+//Bit 23:16, reg_max_pix ;u8
+//Bit 15: 8, reg_dmaxmin_thrdma ;u8
+//Bit 7: 0, reg_dmaxmin_thrdmi ;u8
+#define DI_EI_DRT_CORRPIXTH ((0x202a << 2) + 0xff000000)
+//Bit 31:24, reg_newcorrpix_maxthrd ;u8
+//Bit 23:16, reg_corrpix_diffthrd ;u8
+//Bit 15: 8, reg_corrpix_minthrd ;u8
+//Bit 7: 0, reg_corrpix_maxthrd ;u8
+#define DI_EI_DRT_RECTG_WAVE ((0x202b << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_max_pixwave ;u5
+//Bit 23:21, reserved
+//Bit 20:16, reg_pix_wave ;u5
+//Bit 15:14, reserved
+//Bit 13: 8, reg_maxdrt_thrd ;u6
+//Bit 7: 0, reg_wave_thrd ;u8
+#define DI_EI_DRT_PIX_DIFFTH ((0x202c << 2) + 0xff000000)
+//Bit 31:24, reg_newraw_thrd ;u8
+//Bit 23:16, reg_tb_max_thrd ;u8
+//Bit 15: 8, reg_diffpix_thrd ;u8
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_bilt_trendnumt ;u8
+#define DI_EI_DRT_UNBITREND_TH ((0x202d << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_trend_numb ;u5
+//Bit 23:21, reserved
+//Bit 20:16, reg_bilt_trendnum ;u5
+//Bit 15:13, reserved
+//Bit 12: 8, reg_unil_trendnumt ;u5
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_trend_num ;u5
+//`define DI_IF0_GEN_REG 8'h30
+//`define DI_IF0_CANVAS0 8'h31
+//`define DI_IF0_LUMA_X0 8'h32
+//`define DI_IF0_LUMA_Y0 8'h33
+//`define DI_IF0_CHROMA_X0 8'h34
+//`define DI_IF0_CHROMA_Y0 8'h35
+//`define DI_IF0_RPT_LOOP 8'h36
+//`define DI_IF0_LUMA0_RPT_PAT 8'h37
+//`define DI_IF0_CHROMA0_RPT_PAT 8'h38
+//`define DI_IF0_DUMMY_PIXEL 8'h39
+//`define DI_IF0_LUMA_FIFO_SIZE 8'h3a
+//`define DI_IF0_RANGE_MAP_Y 8'h3b
+//`define DI_IF0_RANGE_MAP_CB 8'h3c
+//`define DI_IF0_RANGE_MAP_CR 8'h3d
+//`define DI_IF0_GEN_REG2 8'h3e
+//`define DI_IF0_FMT_CTRL 8'h3f
+//`define DI_IF0_FMT_W 8'h40
+//
+//`define DI_IF0_URGENT_CTRL 8'h41
+//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path
+//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path
+//`define DI_IF0_GEN_REG3 8'h42
+//bit 31:1, reversed
+//bit 0, cntl_64bit_rev
+// di arbtration :
+// the segment is 8'h50-8'h5f
+//
+// Reading file: di_arb_axi_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+//// reg
+////===============================////
+#define DI_RDARB_MODE_L1C1 ((0x2050 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, rdarb_sel uns, default = 0 ,
+// rdarb_sel[0]==0 slave dc0 connect master port0 rdarb_sel[0]==1 slave dc0 connect master port1
+// rdarb_sel[1]==0 slave dc1 connect master port0 rdarb_sel[1]==1 slave dc1 connect master port1
+// rdarb_sel[2]==0 slave dc2 connect master port0 rdarb_sel[2]==1 slave dc2 connect master port1
+// rdarb_sel[3]==0 slave dc3 connect master port0 rdarb_sel[3]==1 slave dc3 connect master port1
+// rdarb_sel[4]==0 slave dc4 connect master port0 rdarb_sel[4]==1 slave dc4 connect master port1
+// rdarb_sel[5]==0 slave dc5 connect master port0 rdarb_sel[5]==1 slave dc5 connect master port1
+//Bit 15:10, reserved
+//Bit 9:8, rdarb_arb_mode uns, default = 0 ,
+// rdarb_arb_mode[0] master port0 arb way,
+// rdarb_arb_mode[1] master port1 arb way,
+//Bit 7:4, reserved
+//Bit 3:0, rdarb_gate_clk_ctrl uns, default = 0 ,
+// rdarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// rdarb_gate_clk_ctrl[3:2] master port1 clk gate control
+#define DI_RDARB_REQEN_SLV_L1C1 ((0x2051 << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, rdarb_dc_req_en unsigned , default = 12'hfff
+// rdarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// rdarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// rdarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// rdarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// rdarb_dc_req_en[4]: the slv4 req to mst port0 enable,
+// rdarb_dc_req_en[5]: the slv5 req to mst port0 enable,
+// rdarb_dc_req_en[6]: the slv0 req to mst port1 enable,
+// rdarb_dc_req_en[7]: the slv1 req to mst port1 enable,
+// rdarb_dc_req_en[8]: the slv2 req to mst port1 enable,
+// rdarb_dc_req_en[9]: the slv3 req to mst port1 enable,
+// rdarb_dc_req_en[10]: the slv4 req to mst port1 enable,
+// rdarb_dc_req_en[11]: the slv5 req to mst port1 enable,
+#define DI_RDARB_WEIGH0_SLV_L1C1 ((0x2052 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// rddc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// rddc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// rddc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+// rddc_weigh_sxn[4*6+:6]: the slv4 req weigh number
+#define DI_RDARB_WEIGH1_SLV_L1C1 ((0x2053 << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[5*6+:6]: the slv5 req weigh number
+#define DI_WRARB_MODE_L1C1 ((0x2054 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, wrarb_sel uns, default = 0 ,
+// wrarb_sel[0]==0 slave dc0 connect master port0 wrarb_sel[0]==1 slave dc0 connect master port1
+// wrarb_sel[1]==0 slave dc1 connect master port0 wrarb_sel[1]==1 slave dc1 connect master port1
+// wrarb_sel[2]==0 slave dc2 connect master port0 wrarb_sel[2]==1 slave dc2 connect master port1
+// wrarb_sel[3]==0 slave dc3 connect master port0 wrarb_sel[3]==1 slave dc3 connect master port1
+// wrarb_sel[4]==0 slave dc4 connect master port0 wrarb_sel[4]==1 slave dc4 connect master port1
+// wrarb_sel[5]==0 slave dc5 connect master port0 wrarb_sel[5]==1 slave dc5 connect master port1
+//Bit 15:10, reserved
+//Bit 9:8, wrarb_arb_mode uns, default = 0 ,
+// wrarb_arb_mode[0] master port0 arb way,
+// wrarb_arb_mode[1] master port1 arb way,
+//Bit 7:4, reserved
+//Bit 3:0, wrarb_gate_clk_ctrl uns, default = 0 ,
+// wrarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// wrarb_gate_clk_ctrl[3:2] master port1 clk gate control
+#define DI_WRARB_REQEN_SLV_L1C1 ((0x2055 << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, wrarb_dc_req_en unsigned , default = 0
+// wrarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// wrarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// wrarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// wrarb_dc_req_en[4]: the slv4 req to mst port0 enable,
+// wrarb_dc_req_en[5]: the slv5 req to mst port0 enable,
+// wrarb_dc_req_en[0]: the slv0 req to mst port1 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port1 enable,
+// wrarb_dc_req_en[2]: the slv2 req to mst port1 enable,
+// wrarb_dc_req_en[3]: the slv3 req to mst port1 enable,
+// wrarb_dc_req_en[4]: the slv4 req to mst port1 enable,
+// wrarb_dc_req_en[5]: the slv5 req to mst port1 enable,
+#define DI_WRARB_WEIGH0_SLV_L1C1 ((0x2056 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// wrdc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// wrdc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+// wrdc_weigh_sxn[4*6+:6]: the slv4 req weigh number
+#define DI_WRARB_WEIGH1_SLV_L1C1 ((0x2057 << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[5*6+:6]: the slv5 req weigh number
+#define DI_RDWR_ARB_STATUS_L1C1 ((0x2058 << 2) + 0xff000000)
+//Bit 31:4, reserved
+//Bit 3:2, wrarb_arb_busy unsigned , default = 0
+//Bit 1:0, rdarb_arb_busy unsigned , default = 0
+#define DI_ARB_DBG_CTRL_L1C1 ((0x2059 << 2) + 0xff000000)
+#define DI_ARB_DBG_STAT_L1C1 ((0x205a << 2) + 0xff000000)
+#define DI_RDARB_UGT_L1C1 ((0x205b << 2) + 0xff000000)
+#define DI_RDARB_LIMT0_L1C1 ((0x205c << 2) + 0xff000000)
+#define DI_WRARB_UGT_L1C1 ((0x205d << 2) + 0xff000000)
+#define DI_ARB_AXIWR_PROT ((0x205e << 2) + 0xff000000)
+#define DI_ARB_AXIRD0_PROT ((0x205f << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: di_arb_axi_regs.h
+//
+// di afbc_enc
+// the segment is 8'h60-8'h8f
+//
+// Reading file: di_afbc_enc0_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DI_AFBCE_ENABLE ((0x2060 << 2) + 0xff000000)
+//Bit 31:20, gclk_ctrl unsigned , default = 0,
+//Bit 19:16, di_afbce_sync_sel unsigned , default = 0,
+//Bit 15:14, reserved
+//Bit 13, enc_rst_mode unsigned , default = 0,
+//Bit 12, enc_en_mode unsigned , default = 0,
+//Bit 11:9, reserved
+//Bit 8, enc_enable unsigned , default = 0,
+//Bit 7:1, reserved
+//Bit 0, reserved enc_frm_start pulse use this bit don't use
+#define DI_AFBCE_MODE ((0x2061 << 2) + 0xff000000)
+//Bit 31:29, soft_rst unsigned, default = 0 ,the use as go_field
+//Bit 28, reserved
+//Bit 27:26, rev_mode unsigned, default = 0 , reverse mode
+//Bit 25:24, mif_urgent unsigned, default = 3 , info mif and data mif urgent
+//Bit 23, reserved
+//Bit 22:16, hold_line_num unsigned, default = 4, 0: burst1 1:burst2 2:burst4
+//Bit 15:14, burst_mode unsigned, default = 1, 0: burst1 1:burst2 2:burst4
+//Bit 13:1, reserved
+//Bit 0, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb
+#define DI_AFBCE_SIZE_IN ((0x2062 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hsize_in unsigned, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_in unsigned, default = 1080 , pic vert size in unit: pixel
+#define DI_AFBCE_BLK_SIZE_IN ((0x2063 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hblk_size unsigned, default = 60 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vblk_size unsigned, default = 270, pic vert size in unit: pixel
+#define DI_AFBCE_HEAD_BADDR ((0x2064 << 2) + 0xff000000)
+//Bit 31:0, head_baddr unsigned, default = 32'h00;
+#define DI_AFBCE_MIF_SIZE ((0x2065 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:28, ddr_blk_size unsigned, default = 1;
+//Bit 27, reserved
+//Bit 26:24, cmd_blk_size unsigned, default = 3;
+//Bit 23:21, reserved
+//Bit 20:16, uncmp_size unsigned, default = 20;
+//Bit 15:0, mmu_page_size unsigned, default = 4096;
+#define DI_AFBCE_PIXEL_IN_HOR_SCOPE ((0x2066 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, enc_win_end_h unsigned, default = 1919 ; //
+//Bit 15:13, reserved
+//Bit 12:0, enc_win_bgn_h unsigned, default = 0 ; //
+#define DI_AFBCE_PIXEL_IN_VER_SCOPE ((0x2067 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, enc_win_end_v unsigned, default = 1079 ; //
+//Bit 15:13, reserved
+//Bit 12:0, enc_win_bgn_v unsigned, default = 0 ; //
+#define DI_AFBCE_CONV_CTRL ((0x2068 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, fmt_ybuf_depth unsigned, default = 2048
+//Bit 15:12, reserved
+//Bit 11: 0, lbuf_depth unsigned, default = 256, unit=16 pixel need to set = 2^n
+#define DI_AFBCE_MIF_HOR_SCOPE ((0x2069 << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, blk_end_h unsigned, default = 0 ; //
+//Bit 15:10, reserved
+//Bit 9:0, blk_bgn_h unsigned, default = 59 ; //
+#define DI_AFBCE_MIF_VER_SCOPE ((0x206a << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, blk_end_v unsigned, default = 0 ; //
+//Bit 15:12, reserved
+//Bit 11:0, blk_bgn_v unsigned, default = 269 ; //
+#define DI_AFBCE_STAT1 ((0x206b << 2) + 0xff000000)
+//Bit 31, ro_frm_end_pulse1 unsigned, RO,default = 0 ;frame end status
+//Bit 30:0, ro_dbg_top_info1 unsigned, RO,default = 0 ;
+#define DI_AFBCE_STAT2 ((0x206c << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30:0, ro_dbg_top_info2 unsigned, RO,default = 0 ;
+#define DI_AFBCE_FORMAT ((0x206d << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11:10 reserved
+//Bit 9: 8 reg_format_mode // unsigned , RW, default = 2 data format;0 : YUV444, 1:YUV422, 2:YUV420, 3:RGB
+//Bit 7: 4 reg_compbits_c // unsigned , RW, default = 10 chroma bitwidth
+//Bit 3: 0 reg_compbits_y // unsigned , RW, default = 10 luma bitwidth
+#define DI_AFBCE_MODE_EN ((0x206e << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 reserved
+//Bit 25 reg_adpt_interleave_ymode // unsigned , RW, default = 0 force 0 to disable it: no HW implementation
+//Bit 24 reg_adpt_interleave_cmode // unsigned , RW, default = 0 force 0 to disable it: not HW implementation
+//Bit 23 reg_adpt_yinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
+//Bit 22 reg_adpt_yinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
+//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
+//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
+//Bit 19 reserved
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 11 reserved
+//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
+//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
+//Bit 8 reg_uncompress_split_mode // unsigned , RW, default = 0 0: no split; 1: split
+//Bit 7: 6 reserved
+//Bit 5 reg_input_padding_uv128 // unsigned , RW, default = 0 input picture 32x4 block gap mode: 0: pad uv=0; 1: pad uv=128
+//Bit 4 reg_dwds_padding_uv128 // unsigned , RW, default = 0 downsampled image for double write 32x gap mode: 0: pad uv=0; 1: pad uv=128
+//Bit 3: 1 reg_force_order_mode_value // unsigned , RW, default = 0 force order mode 0~7
+//Bit 0 reg_force_order_mode_en // unsigned , RW, default = 0 force order mode enable: 0: no force; 1: forced to force_value
+#define DI_AFBCE_DWSCALAR ((0x206f << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7: 6 reg_dwscalar_w0 // unsigned , RW, default = 3 horizontal 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 5: 4 reg_dwscalar_w1 // unsigned , RW, default = 0 horizontal 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 3: 2 reg_dwscalar_h0 // unsigned , RW, default = 2 vertical 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 1: 0 reg_dwscalar_h1 // unsigned , RW, default = 3 vertical 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+#define DI_AFBCE_DEFCOLOR_1 ((0x2070 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_enc_defalutcolor_3 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr]
+//Bit 11: 0 reg_enc_defalutcolor_0 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr]
+#define DI_AFBCE_DEFCOLOR_2 ((0x2071 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_enc_defalutcolor_2 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr]
+//Bit 11: 0 reg_enc_defalutcolor_1 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr]
+#define DI_AFBCE_QUANT_ENABLE ((0x2072 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_quant_expand_en_1 // unsigned , RW, default = 0 enable for quantization value expansion
+//Bit 10 reg_quant_expand_en_0 // unsigned , RW, default = 0 enable for quantization value expansion
+//Bit 9: 8 reg_bcleav_ofst // signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1;
+//Bit 7: 5 reserved
+//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy
+//Bit 3: 1 reserved
+//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy
+#define DI_AFBCE_IQUANT_LUT_1 ((0x2073 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE_IQUANT_LUT_2 ((0x2074 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE_IQUANT_LUT_3 ((0x2075 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE_IQUANT_LUT_4 ((0x2076 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE_RQUANT_LUT_1 ((0x2077 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_rquant_yclut_0_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting)
+//Bit 27 reserved
+//Bit 26:24 reg_rquant_yclut_0_10 // unsigned , RW, default = 5
+//Bit 23 reserved
+//Bit 22:20 reg_rquant_yclut_0_9 // unsigned , RW, default = 4
+//Bit 19 reserved
+//Bit 18:16 reg_rquant_yclut_0_8 // unsigned , RW, default = 4
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_0_7 // unsigned , RW, default = 3
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_0_6 // unsigned , RW, default = 3
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_0_5 // unsigned , RW, default = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_0_4 // unsigned , RW, default = 2
+#define DI_AFBCE_RQUANT_LUT_2 ((0x2078 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_0_3 // unsigned , RW, default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_0_2 // unsigned , RW, default = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_0_1 // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_0_0 // unsigned , RW, default = 0
+#define DI_AFBCE_RQUANT_LUT_3 ((0x2079 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_rquant_yclut_1_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting)
+//Bit 27 reserved
+//Bit 26:24 reg_rquant_yclut_1_10 // unsigned , RW, default = 5
+//Bit 23 reserved
+//Bit 22:20 reg_rquant_yclut_1_9 // unsigned , RW, default = 4
+//Bit 19 reserved
+//Bit 18:16 reg_rquant_yclut_1_8 // unsigned , RW, default = 4
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_1_7 // unsigned , RW, default = 3
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_1_6 // unsigned , RW, default = 3
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_1_5 // unsigned , RW, default = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_1_4 // unsigned , RW, default = 2
+#define DI_AFBCE_RQUANT_LUT_4 ((0x207a << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_1_3 // unsigned , RW, default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_1_2 // unsigned , RW, default = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_1_1 // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_1_0 // unsigned , RW, default = 0
+#define DI_AFBCE_YUV_FORMAT_CONV_MODE ((0x207b << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7 reserved
+//Bit 6: 4 reg_444to422_mode // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_422to420_mode // unsigned , RW, default = 0
+#define DI_AFBCE_DUMMY_DATA ((0x207c << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29: 0 reg_dummy_data // unsigned , default = 0 ;
+#define DI_AFBCE_CLR_FLAG ((0x207d << 2) + 0xff000000)
+//Bit 31:0 reg_di_afbce_clr_flag // unsigned, default = 0 ;
+#define DI_AFBCE_STA_FLAGT ((0x207e << 2) + 0xff000000)
+//Bit 31:0 ro_di_afbce__sta_flag // unsigned, RO,default = 0 ;
+#define DI_AFBCE_MMU_NUM ((0x207f << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 0 ro_frm_mmu_num // unsigned, RO,default = 0 ;
+#define DI_AFBCE_MMU_RMIF_CTRL1 ((0x2080 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_sync_sel // unsigned , default = 0, axi canvas id sync with frm rst
+//Bit 23:16 reg_canvas_id // unsigned , default = 0, axi canvas id num
+//Bit 15 reserved
+//Bit 14:12 reg_cmd_intr_len // unsigned , default = 1, interrupt send cmd when how many series axi cmd,
+ // 0=12 1=16 2=24 3=32 4=40 5=48 6=56 7=64
+//Bit 11:10 reg_cmd_req_size // unsigned , default = 1, how many room fifo have, then axi send series req, 0=16 1=32 2=24 3=64
+//Bit 9:8 reg_burst_len // unsigned , default = 2, burst type: 0-single 1-bst2 2-bst4
+//Bit 7 reg_swap_64bit // unsigned , default = 0, 64bits of 128bit swap enable
+//Bit 6 reg_little_endian // unsigned , default = 0, big endian enable
+//Bit 5 reg_y_rev // unsigned , default = 0, vertical reverse enable
+//Bit 4 reg_x_rev // unsigned , default = 0, horizontal reverse enable
+//Bit 3 reserved
+//Bit 2:0 reg_pack_mode // unsigned , default = 3, 0:4bit 1:8bit 2:16bit 3:32bit 4:64bit 5:128bit
+#define DI_AFBCE_MMU_RMIF_CTRL2 ((0x2081 << 2) + 0xff000000)
+//Bit 31:30 reg_sw_rst // unsigned , default = 0,
+//Bit 29:24 reserved
+//Bit 23:18 reg_gclk_ctrl
+//Bit 17 reserved
+//Bit 16:0 reg_urgent_ctrl // unsigned , default = 0, urgent control reg :
+ // 16 reg_ugt_init : urgent initial value
+ // 15 reg_ugt_en : urgent enable
+ // 14 reg_ugt_type : 1= wrmif 0=rdmif
+ // 7:4 reg_ugt_top_th: urgent top threshold
+ // 3:0 reg_ugt_bot_th: urgent bottom threshold
+#define DI_AFBCE_MMU_RMIF_CTRL3 ((0x2082 << 2) + 0xff000000)
+//Bit 31:17 reserved
+//Bit 16 reg_acc_mode // unsigned , default = 1,
+//Bit 15:13 reserved
+//Bit 12:0 reg_stride // unsigned , default = 4096,
+#define DI_AFBCE_MMU_RMIF_CTRL4 ((0x2083 << 2) + 0xff000000)
+//Bit 31:0 reg_baddr // unsigned , default = 0,
+#define DI_AFBCE_MMU_RMIF_SCOPE_X ((0x2084 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_x_end // unsigned , default = 4095, the canvas hor end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_x_start // unsigned , default = 0, the canvas hor start pixel position
+#define DI_AFBCE_MMU_RMIF_SCOPE_Y ((0x2085 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_y_end // unsigned , default = 0, the canvas ver end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_y_start // unsigned , default = 0, the canvas ver start pixel positio
+#define DI_AFBCE_MMU_RMIF_RO_STAT ((0x2086 << 2) + 0xff000000)
+//Bit 15:0 reg_status // unsigned ,
+#define DI_AFBCE_PIP_CTRL ((0x208a << 2) + 0xff000000)
+//Bit 31:3 reserved
+//Bit 2 reg_enc_align_en //unsigned , RW,default = 1,
+//Bit 1 reg_pip_ini_ctrl //unsigned , RW,default = 0,
+//Bit 0 reg_pip_mode //unsigned , RW,default = 0,
+#define DI_AFBCE_ROT_CTRL ((0x208b << 2) + 0xff000000)
+//Bit 31:5 reserved
+//Bit 4 reg_rot_en //unsigned , RW,default = 0, rotation enable
+//Bit 3:0 reg_vstep //unsigned , RW,default = 8, rotation vstep ,setting acorrding rotation shrink mode
+#define DI_AFBCE_DIMM_CTRL ((0x208c << 2) + 0xff000000)
+//Bit 31 reg_dimm_layer_en //unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30 reserved
+//Bit 29:0 reg_dimm_data //unsigned , RW,default = 29'h00080200,dimm_layer data
+#define DI_AFBCE_BND_DEC_MISC ((0x208d << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 bnd_dec_rev_mode //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 25:24 bnd_dec_mif_urgent //unsigned , RW,default = 3 only pip mode use those bits,ususaly don't need configure
+//Bit 23:22 bnd_dec_burst_len //unsigned , RW,default = 2 only pip mode use those bits,ususaly don't need configure
+//Bit 21:20 bnd_dec_ddr_blk_size //unsigned , RW,default = 1 only pip mode use those bits,ususaly don't need configure
+//Bit 19 reserved
+//Bit 18:16 bnd_dec_cmd_blk_size //unsigned , RW,default = 3 only pip mode use those bits,ususaly don't need configure
+//Bit 15 reserved
+//Bit 14 bnd_dec_blk_mem_mode //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 13 bnd_dec_addr_link_en //unsigned , RW,default = 1 only pip mode use those bits,ususaly don't need configure
+//Bit 12 bnd_dec_always_body_rden //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 11:0 bnd_dec_mif_lbuf_depth //unsigned , RW,default = 128 only pip mode use those bits,ususaly don't need configure
+#define DI_AFBCE_RD_ARB_MISC ((0x208e << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12 reg_arb_sw_rst //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 11:10 reserved
+//Bit 9 reg_arb_arblk_last1 //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 8 reg_arb_arblk_last0 //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 7:4 reg_arb_weight_ch1 //unsigned , RW,default = 4 only pip mode use those bits,ususaly don't need configure
+//Bit 3:0 reg_arb_weight_ch0 //unsigned , RW,default = 10 only pip mode use those bits,ususaly don't need configure
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: di_afbc_enc0_regs.h
+//
+// the segment is 8'h90-8'h9f
+//
+// Reading file: di_wrmif0_regs.h
+//
+#define NRWR_DBG_AXI_CMD_CNT ((0x2090 << 2) + 0xff000000)
+#define NRWR_DBG_AXI_DAT_CNT ((0x2091 << 2) + 0xff000000)
+#define DI_NRWR_CANVAS ((0x2092 << 2) + 0xff000000)
+#define DI_NRWR_URGENT ((0x2093 << 2) + 0xff000000)
+#define DI_NRWR_X ((0x2094 << 2) + 0xff000000)
+#define DI_NRWR_Y ((0x2095 << 2) + 0xff000000)
+//bit 31:30 NRWR_words_lim
+//bit 29 NRWR_rev_y
+//bit 28:16 NRWR_start_y
+//bit 15 NRWR_ext_en
+//bit 12:0 NRWR_end_y
+#define DI_NRWR_CTRL ((0x2096 << 2) + 0xff000000)
+//bit 31 pending_ddr_wrrsp_NRWR
+//bit 30 NRWR_reg_swap
+//bit 29:26 NRWR_burst_lim
+//bit 25 NRWR_canvas_syncen
+//bit 24 NRWR_no_clk_gate
+//bit 23:22 NRWR_rgb_mode 0:422 to one canvas;1:4:4:4 to one canvas 2:Y to luma , CBCR to chroma canvas ,for nv12/21; 3 : reserved
+//bit 21:20 NRWR_hconv_mode
+//bit 19:18 NRWR_vconv_mode
+//bit 17 NRWR_swap_cbcr
+//bit 16 NRWR_urgent
+//bit 15:8 NRWR_canvas_index_chroma
+//bit 7:0 NRWR_canvas_index_luma
+#define DI_NRWR_SHRK_CTRL ((0x2097 << 2) + 0xff000000)
+//bit 31:10 reserved
+//bit 9:8 reg_vshrk_mode unsigned, default = 0, 0:1/2 horizonal shrink 1:1/4 horizonal shrink 2:1/8 horizonal shrink
+//bit 7:6 reg_hshrk_mode unsigned, default = 0, 0:1/2 vertical shrink 1:1/4 vertical shrink 2:1/8 vertical shrink
+//bit 5:2 reg_gclk_ctrl unsigned, default = 0
+//bit 1 reg_frm_rst unsigned, default = 0
+//bit 0 reg_shrk_en unsigned, default = 0
+#define DI_NRWR_SHRK_SIZE ((0x2098 << 2) + 0xff000000)
+//bit 31:26 reserved
+//bit 25:13 reg_frm_hsize unsigned, default = 1920, hsize in
+//bit 12:0 reg_frm_vsize unsigned, default = 1080, vsize in
+#define DI_NRWR_CROP_CTRL ((0x209a << 2) + 0xff000000)
+//Bit 31 reg_crop_en unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30:4 reserved
+//Bit 3:0 reg_hold_line unsigned , RW,default = 4,dimm_layer data
+#define DI_NRWR_CROP_DIMM_CTRL ((0x209b << 2) + 0xff000000)
+//Bit 31 reg_dimm_layer_en unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30 reserved
+//Bit 29:0 reg_dimm_data unsigned , RW,default = 29'h00080200,dimm_layer data
+#define DI_NRWR_CROP_SIZE_IN ((0x209c << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 reg_crop_hsize unsigned, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, reg_crop_vsize unsigned, default = 1080 , pic vert size in unit: pixel
+#define DI_NRWR_CROP_HSCOPE ((0x209d << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_cropwin_end_h unsigned, default = 1919 ;
+//Bit 15:13, reserved
+//Bit 12:0, reg_cropwin_bgn_h unsigned, default = 0 ;
+#define DI_NRWR_CROP_VSCOPE ((0x209e << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_cropwin_end_v unsigned, default = 1079 ;
+//Bit 15:13, reserved
+//Bit 12:0, reg_cropwin_bgn_v unsigned, default = 0 ;
+//
+// Closing file: di_wrmif0_regs.h
+//
+// the segment is 8'ha0-8'hbf
+//`define DI_IF1_URGENT_CTRL 8'ha3
+//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path
+//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path
+//`define DI_INP_URGENT_CTRL 8'ha4
+//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di mem chroma path
+//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di mem luma path
+//`define DI_MEM_URGENT_CTRL 8'ha5
+//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di chan2 chroma path
+//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di chan2 luma path
+//`define DI_CHAN2_URGENT_CTRL 8'ha6
+//`define DI_IF1_GEN_REG3 8'ha7
+//bit 31:1, reversed
+//bit 0, cntl_64bit_rev
+//`define DI_INP_GEN_REG3 8'ha8
+//bit 31:1, reversed
+//bit 0, cntl_64bit_rev
+//`define DI_MEM_GEN_REG3 8'ha9
+//bit 31:1, reversed
+//bit 0, cntl_64bit_rev
+//`define DI_CHAN2_GEN_REG3 8'haa
+//bit 31:1, reversed
+//bit 0, cntl_64bit_rev
+//`define DI_PRE_GL_CTRL 8'hab
+//bit 31,pre go field cnt enable
+//bit 30,pre go field cnt reset
+//bit 29:16, total pre go line
+//bit 13:0, total pre go frame
+//`define DI_PRE_GL_THD 8'hac
+//bit 31:0 go line size
+//`define DI_POST_GL_CTRL 8'had
+//bit 31,post go field cnt enable
+//bit 30,post go field cnt reset
+//bit 28:16, total post go line
+//bit 13:0, total post go frame
+//`define DI_POST_GL_THD 8'hae
+//bit 31:0 go line size
+//`define DI_IF0_AXI_CMD_CNT 8'hb0
+//`define DI_IF0_AXI_RDAT_CNT 8'hb1
+//
+//`define DI_IF1_AXI_CMD_CNT 8'hb2
+//`define DI_IF1_AXI_RDAT_CNT 8'hb3
+//
+//`define DI_IF2_AXI_CMD_CNT 8'hb4
+//`define DI_IF2_AXI_RDAT_CNT 8'hb5
+//
+//`define DI_INP_AXI_CMD_CNT 8'hb6
+//`define DI_INP_AXI_RDAT_CNT 8'hb7
+//
+//`define DI_MEM_AXI_CMD_CNT 8'hb8
+//`define DI_MEM_AXI_RDAT_CNT 8'hb9
+//
+//`define DI_CHAN2_AXI_CMD_CNT 8'hba
+//`define DI_CHAN2_AXI_RDAT_CNT 8'hbb
+// di afbc_enc
+// the segment is 8'hc0-8'hef
+//
+// Reading file: di_afbc_enc1_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DI_AFBCE1_ENABLE ((0x20c0 << 2) + 0xff000000)
+//Bit 31:20, gclk_ctrl unsigned , default = 0,
+//Bit 19:16, di_AFBCE1_sync_sel unsigned , default = 0,
+//Bit 15:14, reserved
+//Bit 13, enc_rst_mode unsigned , default = 0,
+//Bit 12, enc_en_mode unsigned , default = 0,
+//Bit 11:9, reserved
+//Bit 8, enc_enable unsigned , default = 0,
+//Bit 7:1, reserved
+//Bit 0, reserved enc_frm_start pulse use this bit don't use
+#define DI_AFBCE1_MODE ((0x20c1 << 2) + 0xff000000)
+//Bit 31:29, soft_rst unsigned, default = 0 ,the use as go_field
+//Bit 28, reserved unsigned, default = 0 , enable singal of crop
+//Bit 27:26, rev_mode unsigned, default = 0 , reverse mode
+//Bit 25:24, mif_urgent unsigned, default = 3 , info mif and data mif urgent
+//Bit 23, reserved
+//Bit 22:16, hold_line_num unsigned, default = 4, 0: burst1 1:burst2 2:burst4
+//Bit 15:14, burst_mode unsigned, default = 1, 0: burst1 1:burst2 2:burst4
+//Bit 13:1, reserved
+//Bit 0, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb
+#define DI_AFBCE1_SIZE_IN ((0x20c2 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hsize_in unsigned, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_in unsigned, default = 1080 , pic vert size in unit: pixel
+#define DI_AFBCE1_BLK_SIZE_IN ((0x20c3 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hblk_size unsigned, default = 60 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vblk_size unsigned, default = 270, pic vert size in unit: pixel
+#define DI_AFBCE1_HEAD_BADDR ((0x20c4 << 2) + 0xff000000)
+//Bit 31:0, head_baddr unsigned, default = 32'h00;
+#define DI_AFBCE1_MIF_SIZE ((0x20c5 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:28, ddr_blk_size unsigned, default = 1;
+//Bit 27, reserved
+//Bit 26:24, cmd_blk_size unsigned, default = 3;
+//Bit 23:21, reserved
+//Bit 20:16, uncmp_size unsigned, default = 20;
+//Bit 15:0, mmu_page_size unsigned, default = 4096;
+#define DI_AFBCE1_PIXEL_IN_HOR_SCOPE ((0x20c6 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, enc_win_end_h unsigned, default = 1919 ; //
+//Bit 15:13, reserved
+//Bit 12:0, enc_win_bgn_h unsigned, default = 0 ; //
+#define DI_AFBCE1_PIXEL_IN_VER_SCOPE ((0x20c7 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, enc_win_end_v unsigned, default = 1079 ; //
+//Bit 15:13, reserved
+//Bit 12:0, enc_win_bgn_v unsigned, default = 0 ; //
+#define DI_AFBCE1_CONV_CTRL ((0x20c8 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, fmt_ybuf_depth unsigned, default = 2048
+//Bit 15:12, reserved
+//Bit 11: 0, lbuf_depth unsigned, default = 256, unit=16 pixel need to set = 2^n
+#define DI_AFBCE1_MIF_HOR_SCOPE ((0x20c9 << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, blk_end_h unsigned, default = 0 ; //
+//Bit 15:10, reserved
+//Bit 9:0, blk_bgn_h unsigned, default = 59 ; //
+#define DI_AFBCE1_MIF_VER_SCOPE ((0x20ca << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, blk_end_v unsigned, default = 0 ; //
+//Bit 15:12, reserved
+//Bit 11:0, blk_bgn_v unsigned, default = 269 ; //
+#define DI_AFBCE1_STAT1 ((0x20cb << 2) + 0xff000000)
+//Bit 31, ro_frm_end_pulse1 unsigned, RO,default = 0 ;frame end status
+//Bit 30:0, ro_dbg_top_info1 unsigned, RO,default = 0 ;
+#define DI_AFBCE1_STAT2 ((0x20cc << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30:0, ro_dbg_top_info2 unsigned, RO,default = 0 ;
+#define DI_AFBCE1_FORMAT ((0x20cd << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11:10 reserved
+//Bit 9: 8 reg_format_mode // unsigned , RW, default = 2 data format;0 : YUV444, 1:YUV422, 2:YUV420, 3:RGB
+//Bit 7: 4 reg_compbits_c // unsigned , RW, default = 10 chroma bitwidth
+//Bit 3: 0 reg_compbits_y // unsigned , RW, default = 10 luma bitwidth
+#define DI_AFBCE1_MODE_EN ((0x20ce << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 reserved
+//Bit 25 reg_adpt_interleave_ymode // unsigned , RW, default = 0 force 0 to disable it: no HW implementation
+//Bit 24 reg_adpt_interleave_cmode // unsigned , RW, default = 0 force 0 to disable it: not HW implementation
+//Bit 23 reg_adpt_yinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
+//Bit 22 reg_adpt_yinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
+//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
+//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
+//Bit 19 reserved
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 11 reserved
+//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
+//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
+//Bit 8 reg_uncompress_split_mode // unsigned , RW, default = 0 0: no split; 1: split
+//Bit 7: 6 reserved
+//Bit 5 reg_input_padding_uv128 // unsigned , RW, default = 0 input picture 32x4 block gap mode: 0: pad uv=0; 1: pad uv=128
+//Bit 4 reg_dwds_padding_uv128 // unsigned , RW, default = 0 downsampled image for double write 32x gap mode: 0: pad uv=0; 1: pad uv=128
+//Bit 3: 1 reg_force_order_mode_value // unsigned , RW, default = 0 force order mode 0~7
+//Bit 0 reg_force_order_mode_en // unsigned , RW, default = 0 force order mode enable: 0: no force; 1: forced to force_value
+#define DI_AFBCE1_DWSCALAR ((0x20cf << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7: 6 reg_dwscalar_w0 // unsigned , RW, default = 3 horizontal 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 5: 4 reg_dwscalar_w1 // unsigned , RW, default = 0 horizontal 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 3: 2 reg_dwscalar_h0 // unsigned , RW, default = 2 vertical 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 1: 0 reg_dwscalar_h1 // unsigned , RW, default = 3 vertical 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+#define DI_AFBCE1_DEFCOLOR_1 ((0x20d0 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_enc_defalutcolor_3 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr]
+//Bit 11: 0 reg_enc_defalutcolor_0 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr]
+#define DI_AFBCE1_DEFCOLOR_2 ((0x20d1 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_enc_defalutcolor_2 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr]
+//Bit 11: 0 reg_enc_defalutcolor_1 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr]
+#define DI_AFBCE1_QUANT_ENABLE ((0x20d2 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_quant_expand_en_1 // unsigned , RW, default = 0 enable for quantization value expansion
+//Bit 10 reg_quant_expand_en_0 // unsigned , RW, default = 0 enable for quantization value expansion
+//Bit 9: 8 reg_bcleav_ofst // signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1;
+//Bit 7: 5 reserved
+//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy
+//Bit 3: 1 reserved
+//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy
+#define DI_AFBCE1_IQUANT_LUT_1 ((0x20d3 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE1_IQUANT_LUT_2 ((0x20d4 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE1_IQUANT_LUT_3 ((0x20d5 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE1_IQUANT_LUT_4 ((0x20d6 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE1_RQUANT_LUT_1 ((0x20d7 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_rquant_yclut_0_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting)
+//Bit 27 reserved
+//Bit 26:24 reg_rquant_yclut_0_10 // unsigned , RW, default = 5
+//Bit 23 reserved
+//Bit 22:20 reg_rquant_yclut_0_9 // unsigned , RW, default = 4
+//Bit 19 reserved
+//Bit 18:16 reg_rquant_yclut_0_8 // unsigned , RW, default = 4
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_0_7 // unsigned , RW, default = 3
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_0_6 // unsigned , RW, default = 3
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_0_5 // unsigned , RW, default = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_0_4 // unsigned , RW, default = 2
+#define DI_AFBCE1_RQUANT_LUT_2 ((0x20d8 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_0_3 // unsigned , RW, default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_0_2 // unsigned , RW, default = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_0_1 // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_0_0 // unsigned , RW, default = 0
+#define DI_AFBCE1_RQUANT_LUT_3 ((0x20d9 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_rquant_yclut_1_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting)
+//Bit 27 reserved
+//Bit 26:24 reg_rquant_yclut_1_10 // unsigned , RW, default = 5
+//Bit 23 reserved
+//Bit 22:20 reg_rquant_yclut_1_9 // unsigned , RW, default = 4
+//Bit 19 reserved
+//Bit 18:16 reg_rquant_yclut_1_8 // unsigned , RW, default = 4
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_1_7 // unsigned , RW, default = 3
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_1_6 // unsigned , RW, default = 3
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_1_5 // unsigned , RW, default = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_1_4 // unsigned , RW, default = 2
+#define DI_AFBCE1_RQUANT_LUT_4 ((0x20da << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_1_3 // unsigned , RW, default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_1_2 // unsigned , RW, default = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_1_1 // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_1_0 // unsigned , RW, default = 0
+#define DI_AFBCE1_YUV_FORMAT_CONV_MODE ((0x20db << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7 reserved
+//Bit 6: 4 reg_444to422_mode // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_422to420_mode // unsigned , RW, default = 0
+#define DI_AFBCE1_DUMMY_DATA ((0x20dc << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29: 0 reg_dummy_data // unsigned , default = 0 ;
+#define DI_AFBCE1_CLR_FLAG ((0x20dd << 2) + 0xff000000)
+//Bit 31:0 reg_di_AFBCE1_clr_flag // unsigned, default = 0 ;
+#define DI_AFBCE1_STA_FLAGT ((0x20de << 2) + 0xff000000)
+//Bit 31:0 ro_di_AFBCE1__sta_flag // unsigned, RO,default = 0 ;
+#define DI_AFBCE1_MMU_NUM ((0x20df << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 0 ro_frm_mmu_num // unsigned, RO,default = 0 ;
+#define DI_AFBCE1_MMU_RMIF_CTRL1 ((0x20e0 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_sync_sel // unsigned , default = 0, axi canvas id sync with frm rst
+//Bit 23:16 reg_canvas_id // unsigned , default = 0, axi canvas id num
+//Bit 15 reserved
+//Bit 14:12 reg_cmd_intr_len // unsigned , default = 1, interrupt send cmd when how many series axi cmd,
+ // 0=12 1=16 2=24 3=32 4=40 5=48 6=56 7=64
+//Bit 11:10 reg_cmd_req_size // unsigned , default = 1, how many room fifo have, then axi send series req, 0=16 1=32 2=24 3=64
+//Bit 9:8 reg_burst_len // unsigned , default = 2, burst type: 0-single 1-bst2 2-bst4
+//Bit 7 reg_swap_64bit // unsigned , default = 0, 64bits of 128bit swap enable
+//Bit 6 reg_little_endian // unsigned , default = 0, big endian enable
+//Bit 5 reg_y_rev // unsigned , default = 0, vertical reverse enable
+//Bit 4 reg_x_rev // unsigned , default = 0, horizontal reverse enable
+//Bit 3 reserved
+//Bit 2:0 reg_pack_mode // unsigned , default = 3, 0:4bit 1:8bit 2:16bit 3:32bit 4:64bit 5:128bit
+#define DI_AFBCE1_MMU_RMIF_CTRL2 ((0x20e1 << 2) + 0xff000000)
+//Bit 31:30 reg_sw_rst // unsigned , default = 0,
+//Bit 29:24 reserved
+//Bit 23:18 reg_gclk_ctrl
+//Bit 17 reserved
+//Bit 16:0 reg_urgent_ctrl // unsigned , default = 0, urgent control reg :
+ // 16 reg_ugt_init : urgent initial value
+ // 15 reg_ugt_en : urgent enable
+ // 14 reg_ugt_type : 1= wrmif 0=rdmif
+ // 7:4 reg_ugt_top_th: urgent top threshold
+ // 3:0 reg_ugt_bot_th: urgent bottom threshold
+#define DI_AFBCE1_MMU_RMIF_CTRL3 ((0x20e2 << 2) + 0xff000000)
+//Bit 31:17 reserved
+//Bit 16 reg_acc_mode // unsigned , default = 1,
+//Bit 15:13 reserved
+//Bit 12:0 reg_stride // unsigned , default = 4096,
+#define DI_AFBCE1_MMU_RMIF_CTRL4 ((0x20e3 << 2) + 0xff000000)
+//Bit 31:0 reg_baddr // unsigned , default = 0,
+#define DI_AFBCE1_MMU_RMIF_SCOPE_X ((0x20e4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_x_end // unsigned , default = 4095, the canvas hor end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_x_start // unsigned , default = 0, the canvas hor start pixel position
+#define DI_AFBCE1_MMU_RMIF_SCOPE_Y ((0x20e5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_y_end // unsigned , default = 0, the canvas ver end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_y_start // unsigned , default = 0, the canvas ver start pixel positio
+#define DI_AFBCE1_MMU_RMIF_RO_STAT ((0x20e6 << 2) + 0xff000000)
+//Bit 15:0 reg_status // unsigned ,
+#define DI_AFBCE1_PIP_CTRL ((0x20ea << 2) + 0xff000000)
+//Bit 31:3 reserved
+//Bit 2 reg_enc_align_en //unsigned , RW,default = 1,
+//Bit 1 reg_pip_ini_ctrl //unsigned , RW,default = 0,
+//Bit 0 reg_pip_mode //unsigned , RW,default = 0,
+#define DI_AFBCE1_ROT_CTRL ((0x20eb << 2) + 0xff000000)
+//Bit 31:5 reserved
+//Bit 4 reg_rot_en //unsigned , RW,default = 0, rotation enable
+//Bit 3:0 reg_vstep //unsigned , RW,default = 8, rotation vstep ,setting acorrding rotation shrink mode
+#define DI_AFBCE1_DIMM_CTRL ((0x20ec << 2) + 0xff000000)
+//Bit 31 reg_dimm_layer_en //unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30 reserved
+//Bit 29:0 reg_dimm_data //unsigned , RW,default = 29'h00080200,dimm_layer data
+#define DI_AFBCE1_BND_DEC_MISC ((0x20ed << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 bnd_dec_rev_mode //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 25:24 bnd_dec_mif_urgent //unsigned , RW,default = 3 only pip mode use those bits,ususaly don't need configure
+//Bit 23:22 bnd_dec_burst_len //unsigned , RW,default = 2 only pip mode use those bits,ususaly don't need configure
+//Bit 21:20 bnd_dec_ddr_blk_size //unsigned , RW,default = 1 only pip mode use those bits,ususaly don't need configure
+//Bit 19 reserved
+//Bit 18:16 bnd_dec_cmd_blk_size //unsigned , RW,default = 3 only pip mode use those bits,ususaly don't need configure
+//Bit 15 reserved
+//Bit 14 bnd_dec_blk_mem_mode //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 13 bnd_dec_addr_link_en //unsigned , RW,default = 1 only pip mode use those bits,ususaly don't need configure
+//Bit 12 bnd_dec_always_body_rden //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 11:0 bnd_dec_mif_lbuf_depth //unsigned , RW,default = 128 only pip mode use those bits,ususaly don't need configure
+#define DI_AFBCE1_RD_ARB_MISC ((0x20ee << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12 reg_arb_sw_rst //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 11:10 reserved
+//Bit 9 reg_arb_arblk_last1 //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 8 reg_arb_arblk_last0 //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 7:4 reg_arb_weight_ch1 //unsigned , RW,default = 4 only pip mode use those bits,ususaly don't need configure
+//Bit 3:0 reg_arb_weight_ch0 //unsigned , RW,default = 10 only pip mode use those bits,ususaly don't need configure
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: di_afbc_enc1_regs.h
+//
+// the segment is 8'hf0-8'hff
+//
+// Reading file: di_wrmif1_regs.h
+//
+#define DIWR_DBG_AXI_CMD_CNT ((0x20f0 << 2) + 0xff000000)
+#define DIWR_DBG_AXI_DAT_CNT ((0x20f1 << 2) + 0xff000000)
+#define DI_DIWR_CANVAS ((0x20f2 << 2) + 0xff000000)
+#define DI_DIWR_URGENT ((0x20f3 << 2) + 0xff000000)
+#define DI_DIWR_X ((0x20f4 << 2) + 0xff000000)
+#define DI_DIWR_Y ((0x20f5 << 2) + 0xff000000)
+//bit 31:30 diwr_words_lim
+//bit 29 diwr_rev_y
+//bit 28:16 diwr_start_y
+//bit 15 diwr_ext_en
+//bit 12:0 diwr_end_y
+#define DI_DIWR_CTRL ((0x20f6 << 2) + 0xff000000)
+//bit 31 pending_ddr_wrrsp_diwr
+//bit 30 diwr_reg_swap
+//bit 29:26 diwr_burst_lim
+//bit 25 diwr_canvas_syncen
+//bit 24 diwr_no_clk_gate
+//bit 23:22 diwr_rgb_mode 0:422 to one canvas;1:4:4:4 to one canvas 2:Y to luma , CBCR to chroma canvas ,for nv12/21; 3 : reserved
+//bit 21:20 diwr_hconv_mode
+//bit 19:18 diwr_vconv_mode
+//bit 17 diwr_swap_cbcr
+//bit 16 diwr_urgent
+//bit 15:8 diwr_canvas_index_chroma
+//bit 7:0 diwr_canvas_index_luma
+#define DI_DIWR_SHRK_CTRL ((0x20f7 << 2) + 0xff000000)
+//bit 31:10 reserved
+//bit 9:8 reg_vshrk_mode unsigned, default = 0, 0:1/2 horizonal shrink 1:1/4 horizonal shrink 2:1/8 horizonal shrink
+//bit 7:6 reg_hshrk_mode unsigned, default = 0, 0:1/2 vertical shrink 1:1/4 vertical shrink 2:1/8 vertical shrink
+//bit 5:2 reg_gclk_ctrl unsigned, default = 0
+//bit 1 reg_frm_rst unsigned, default = 0
+//bit 0 reg_shrk_en unsigned, default = 0
+#define DI_DIWR_SHRK_SIZE ((0x20f8 << 2) + 0xff000000)
+//bit 31:26 reserved
+//bit 25:13 reg_frm_hsize unsigned, default = 1920, hsize in
+//bit 12:0 reg_frm_vsize unsigned, default = 1080, vsize in
+#define DI_DIWR_CROP_CTRL ((0x20fa << 2) + 0xff000000)
+//Bit 31 reg_crop_en unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30:4 reserved
+//Bit 3:0 reg_hold_line unsigned , RW,default = 4,dimm_layer data
+#define DI_DIWR_CROP_DIMM_CTRL ((0x20fb << 2) + 0xff000000)
+//Bit 31 reg_dimm_layer_en unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30 reserved
+//Bit 29:0 reg_dimm_data unsigned , RW,default = 29'h00080200,dimm_layer data
+#define DI_DIWR_CROP_SIZE_IN ((0x20fc << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 reg_crop_hsize unsigned, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, reg_crop_vsize unsigned, default = 1080 , pic vert size in unit: pixel
+#define DI_DIWR_CROP_HSCOPE ((0x20fd << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_cropwin_end_h unsigned, default = 1919 ;
+//Bit 15:13, reserved
+//Bit 12:0, reg_cropwin_bgn_h unsigned, default = 0 ;
+#define DI_DIWR_CROP_VSCOPE ((0x20fe << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_cropwin_end_v unsigned, default = 1079 ;
+//Bit 15:13, reserved
+//Bit 12:0, reg_cropwin_bgn_v unsigned, default = 0 ;
+//
+// Closing file: di_wrmif1_regs.h
+//
+//
+// Closing file: vregs_clk1.h
+//
+//======================================================================
+// vpu register.
+//======================================================================
+//
+// Reading file: vpu_top_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//======================================================================
+// vpu register.
+//======================================================================
+// -----------------------------------------------
+// REG_BASE: VPU_VCBUS_BASE = 0x27
+// -----------------------------------------------
+//`define VPU_OSD1_MMC_CTRL 8'h01
+#define VPU_CRC_CTRL ((0x2701 << 2) + 0xff000000)
+#define VPU_RO_CRC0 ((0x2702 << 2) + 0xff000000)
+#define VPU_RO_CRC1 ((0x2703 << 2) + 0xff000000)
+#define VPU_RO_CRC2 ((0x2704 << 2) + 0xff000000)
+#define VPU_RO_CRC3 ((0x2705 << 2) + 0xff000000)
+#define VPU_RO_CRC4 ((0x2706 << 2) + 0xff000000)
+#define VPU_RO_CRC5 ((0x2707 << 2) + 0xff000000)
+#define VPU_RO_CRC6 ((0x2708 << 2) + 0xff000000)
+#define VPU_INTF_CTRL ((0x270a << 2) + 0xff000000)
+#define VPU_APB_PROT_CTRL ((0x270b << 2) + 0xff000000)
+#define VPU_ENC_ERROR ((0x270c << 2) + 0xff000000)
+#define VPU_SECURE_REG ((0x270d << 2) + 0xff000000)
+#define VPU_SECURE_ST_RO ((0x270e << 2) + 0xff000000)
+#define VPU_VDIN_SEC_IN ((0x270f << 2) + 0xff000000)
+//`define VPU_OSD2_MMC_CTRL 8'h02
+//`define VPU_VD1_MMC_CTRL 8'h03
+//`define VPU_VD2_MMC_CTRL 8'h04
+//`define VPU_DI_IF1_MMC_CTRL 8'h05
+//`define VPU_DI_MEM_MMC_CTRL 8'h06
+//`define VPU_DI_INP_MMC_CTRL 8'h07
+//`define VPU_DI_MTNRD_MMC_CTRL 8'h08
+//`define VPU_DI_CHAN2_MMC_CTRL 8'h09
+//`define VPU_DI_MTNWR_MMC_CTRL 8'h0a
+//`define VPU_DI_NRWR_MMC_CTRL 8'h0b
+//`define VPU_DI_DIWR_MMC_CTRL 8'h0c
+//`define VPU_VDIN0_MMC_CTRL 8'h0d
+//`define VPU_VDIN1_MMC_CTRL 8'h0e
+//`define VPU_BT656_MMC_CTRL 8'h0f
+//`define VPU_TVD3D_MMC_CTRL 8'h10
+//`define VPU_TVDVBI_MMC_CTRL 8'h11
+//Read only
+//`define VPU_TVDVBI_VSLATCH_ADDR 8'h12
+//Read only
+//`define VPU_TVDVBI_WRRSP_ADDR 8'h13
+#define VPU_VDIN_PRE_ARB_CTRL ((0x2714 << 2) + 0xff000000)
+#define VPU_VDISP_PRE_ARB_CTRL ((0x2715 << 2) + 0xff000000)
+#define VPU_VPUARB2_PRE_ARB_CTRL ((0x2716 << 2) + 0xff000000)
+#define VPU_OSD3_MMC_CTRL ((0x2717 << 2) + 0xff000000)
+#define VPU_OSD4_MMC_CTRL ((0x2718 << 2) + 0xff000000)
+#define VPU_VD3_MMC_CTRL ((0x2719 << 2) + 0xff000000)
+// [31:21] Reserved.
+// [20:18] cntl_encx_clk_sel
+// [17:16] cntl_vencl_dpi_sel_clk
+// [15: 8] Reserved
+// [ 6: 4] Reserved
+// [ 3: 2] cntl_viu2_sel_venc. Select which one of the encI/P/T that VIU2 connects to:
+// 0=No connection, 1=ENCI, 2=ENCP, 3=ENCT.
+// [ 1: 0] cntl_viu1_sel_venc. Select which one of the encI/P/T that VIU1 connects to:
+// 0=No connection, 1=ENCI, 2=ENCP, 3=ENCT.
+#define VPU_VIU_VENC_MUX_CTRL ((0x271a << 2) + 0xff000000)
+// [15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.
+// [11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.
+// [ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:
+// 0=output CrYCb(BRG);
+// 1=output YCbCr(RGB);
+// 2=output YCrCb(RBG);
+// 3=output CbCrY(GBR);
+// 4=output CbYCr(GRB);
+// 5=output CrCbY(BGR);
+// 6,7=Rsrv.
+// [ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).
+// [ 3] inv_vsync. 1=Invert Vsync polarity.
+// [ 2] inv_hsync. 1=Invert Hsync polarity.
+// [ 1: 0] src_sel. 0=Disable output to HDMI; 1=Select VENC_I output to HDMI; 2=Select VENC_P output.
+#define VPU_HDMI_SETTING ((0x271b << 2) + 0xff000000)
+#define ENCI_INFO_READ ((0x271c << 2) + 0xff000000)
+#define ENCP_INFO_READ ((0x271d << 2) + 0xff000000)
+#define ENCT_INFO_READ ((0x271e << 2) + 0xff000000)
+#define ENCL_INFO_READ ((0x271f << 2) + 0xff000000)
+// Bit 0 RW, viu_rst_n
+// Bit 1 RW, vdin_mmc_arb_rst_n
+// Bit 2 RW, vdisp_mmc_arb_rst_n
+// Bit 3 RW, vpuarb2_mmc_arb_rst_n
+#define VPU_SW_RESET ((0x2720 << 2) + 0xff000000)
+//Bit 30 d2d3_depr_req_sel, 0:vdisp_pre_arb, 1: vpuarb2_pre_arb
+//Bit 27:22 d2d3_depr_brst_num
+//Bit 21:16 d2d3_depr_id
+//Bit 14 d2d3_depw_req_sel, 0: vdin_pre_arb, 1: vdisp_pre_arb
+//Bit 11:6 d2d3_depw_brst_num
+//Bit 5:0 d2d3_depw_id
+#define VPU_D2D3_MMC_CTRL ((0x2721 << 2) + 0xff000000)
+//Bit 30 mtn_contrd_req_pre, 0:disp1_arb, 1: vdin_pre_arb
+//Bit 27:22 mtn_contrd_brst_num
+//Bit 21:16 mtn_contrd_id
+//Bit 14 mtn_contwr_req_pre, 0: vdisp1_arb, 1: vdin_pre_arb
+//Bit 11:6 mtn_contwr_brst_num
+//Bit 5:0 mtn_contwr_id
+#define VPU_CONT_MMC_CTRL ((0x2722 << 2) + 0xff000000)
+// Bit 6 RW, gclk_mpeg_vpu_misc
+// Bit 5 RW, gclk_mpeg_venc_l_top
+// Bit 4 RW, gclk_mpeg_vencl_int
+// Bit 3 RW, gclk_mpeg_vencp_int
+// Bit 2 RW, gclk_mpeg_vi2_top
+// Bit 1 RW, gclk_mpeg_vi_top
+// Bit 0 RW, gclk_mpeg_venc_p_top
+#define VPU_CLK_GATE ((0x2723 << 2) + 0xff000000)
+//Bit 12 RW, rdma_pre
+//Bit 11: 6 RW, rdma_num
+//Bit 5: 0 RW, rdma_id
+#define VPU_RDMA_MMC_CTRL ((0x2724 << 2) + 0xff000000)
+#define VPU_MEM_PD_REG0 ((0x2725 << 2) + 0xff000000)
+#define VPU_MEM_PD_REG1 ((0x2726 << 2) + 0xff000000)
+// [ 31] hdmi_data_ovr_en: 1=Enable overriding data input to HDMI TX with hdmi_data_ovr[29:0]. 0=No override. Default 0.
+// [ 30] Reserved. Default 0
+// [29: 0] hdmi_data_ovr. Default 0.
+#define VPU_HDMI_DATA_OVR ((0x2727 << 2) + 0xff000000)
+//Bit 15 RW, prot1_sel_osd4
+//Bit 14 RW, prot1_sel_osd3
+//Bit 13 RW, prot1_sel_osd2
+//Bit 12 RW, prot1_sel_osd1
+//Bit 11: 6 RW, prot1_brst_num
+//Bit 5: 0 RW, prot1_id
+#define VPU_PROT1_MMC_CTRL ((0x2728 << 2) + 0xff000000)
+//Bit 14 RW, prot2_sel_vd3
+//Bit 13 RW, prot2_sel_vd2
+//Bit 12 RW, prot2_sel_vd1
+//Bit 11: 6 RW, prot2_brst_num
+//Bit 5: 0 RW, prot2_id
+#define VPU_PROT2_MMC_CTRL ((0x2729 << 2) + 0xff000000)
+//Bit 14 RW, prot3_sel_vd3
+//Bit 13 RW, prot3_sel_vd2
+//Bit 12 RW, prot3_sel_vd1
+//Bit 11: 6 RW, prot3_brst_num
+//Bit 5: 0 RW, prot3_id
+#define VPU_PROT3_MMC_CTRL ((0x272a << 2) + 0xff000000)
+//Bit 29:24 RW, s3_brst_num
+//Bit 21:16 RW, s2_brst_num
+//Bit 13: 8 RW, s1_brst_num
+//Bit 5: 0 RW, s0_brst_num
+#define VPU_ARB4_V1_MMC_CTRL ((0x272b << 2) + 0xff000000)
+//Bit 29:24 RW, s3_brst_num
+//Bit 21:16 RW, s2_brst_num
+//Bit 13: 8 RW, s1_brst_num
+//Bit 5: 0 RW, s0_brst_num
+#define VPU_ARB4_V2_MMC_CTRL ((0x272c << 2) + 0xff000000)
+//Bit 27:22 RW, mcvecwr_num
+//Bit 21:16 RW, mcvecwr_id
+//Bit 11:6 RW, mcvecrd_num
+//Bit 5:0 RW, mcvecrd_id
+#define VPU_MCVEC_MMC_CTRL ((0x272d << 2) + 0xff000000)
+//Bit 27:22 RW, mcinfwr_num
+//Bit 21:16 RW, mcinfwr_id
+//Bit 11:6 RW, mcinfrd_num
+//Bit 5:0 RW, mcinfrd_id
+#define VPU_MCINF_MMC_CTRL ((0x272e << 2) + 0xff000000)
+//Bit 31 reg_vpu_pwm_inv, 1: invert the pwm signal, active low
+//Bit 30:29 reg_vpu_pwm_src_sel, 00: encl, enct, encp
+//Bit 28:16 reg_vpu_pwm_v_end0
+//Bit 12:0 reg_vpu_pwm_v_start0
+#define VPU_VPU_PWM_V0 ((0x2730 << 2) + 0xff000000)
+//Bit 28:16 reg_vpu_pwm_v_end1
+//Bit 12:0 reg_vpu_pwm_v_start1
+#define VPU_VPU_PWM_V1 ((0x2731 << 2) + 0xff000000)
+//Bit 28:16 reg_vpu_pwm_v_end2
+//Bit 12:0 reg_vpu_pwm_v_start2
+#define VPU_VPU_PWM_V2 ((0x2732 << 2) + 0xff000000)
+//Bit 28:16 reg_vpu_pwm_v_end3
+//Bit 12:0 reg_vpu_pwm_v_start3
+#define VPU_VPU_PWM_V3 ((0x2733 << 2) + 0xff000000)
+//Bit 28:16 reg_vpu_pwm_h_end0
+//Bit 12:0 reg_vpu_pwm_h_start0
+#define VPU_VPU_PWM_H0 ((0x2734 << 2) + 0xff000000)
+//Bit 28:16 reg_vpu_pwm_h_end1
+//Bit 12:0 reg_vpu_pwm_h_start1
+#define VPU_VPU_PWM_H1 ((0x2735 << 2) + 0xff000000)
+//Bit 28:16 reg_vpu_pwm_h_end2
+//Bit 12:0 reg_vpu_pwm_h_start2
+#define VPU_VPU_PWM_H2 ((0x2736 << 2) + 0xff000000)
+//Bit 28:16 reg_vpu_pwm_h_end3
+//Bit 12:0 reg_vpu_pwm_h_start3
+#define VPU_VPU_PWM_H3 ((0x2737 << 2) + 0xff000000)
+//Bit 18 reg_vpu_3d_go_high_fld_pol: 0: go high at field 0, 1: go high at field 1
+//Bit 17 reg_vpu_3d_sync_setting_vsync_latch
+//Bit 16 reg_vpu_3d_sync_enable
+//Bit 14:8 reg_vpu_3d_sync_v_end
+//Bit 6:0 reg_vpu_3d_sync_v_start
+#define VPU_VPU_3D_SYNC1 ((0x2738 << 2) + 0xff000000)
+//Bit 28:16 reg_vpu_3d_sync_h_end
+//Bit 12:0 reg_vpu_3d_sync_h_start
+#define VPU_VPU_3D_SYNC2 ((0x2739 << 2) + 0xff000000)
+//Bit 0, if true, force vencl clk enable, otherwise, it might auto turn off by mipi DSI
+#define VPU_MISC_CTRL ((0x2740 << 2) + 0xff000000)
+#define VPU_ISP_GCLK_CTRL0 ((0x2741 << 2) + 0xff000000)
+#define VPU_ISP_GCLK_CTRL1 ((0x2742 << 2) + 0xff000000)
+#define VPU_HDMI_FMT_CTRL ((0x2743 << 2) + 0xff000000)
+#define VPU_VDIN_ASYNC_HOLD_CTRL ((0x2744 << 2) + 0xff000000)
+#define VPU_VDISP_ASYNC_HOLD_CTRL ((0x2745 << 2) + 0xff000000)
+#define VPU_VPUARB2_ASYNC_HOLD_CTRL ((0x2746 << 2) + 0xff000000)
+// arb0_rd_urg_ctrl_o <= vpp_off_urg_ctrl & vpu_arb_urg_ctrl[0] |
+// rdma_ddr_req_busy_sync_d1 & vpu_arb_urg_ctrl[1]
+// ;
+//
+// arb1_rd_urg_ctrl_o <= vpp_off_urg_ctrl & vpu_arb_urg_ctrl[2] |
+// rdma_ddr_req_busy_sync_d1 & vpu_arb_urg_ctrl[3]
+// ;
+//
+// arb2_rd_urg_ctrl_o <= vpp_off_urg_ctrl & vpu_arb_urg_ctrl[4] |
+// rdma_ddr_req_busy_sync_d1 & vpu_arb_urg_ctrl[5]
+// ;
+//
+// arb0_wr_urg_ctrl_o <= vdin0_lff_urg_ctrl_sync_d1 & vpu_arb_urg_ctrl[6] |
+// vdin1_lff_urg_ctrl_sync_d1 & vpu_arb_urg_ctrl[7]
+// ;
+//
+// arb1_wr_urg_ctrl_o <= vdin0_lff_urg_ctrl_sync_d1 & vpu_arb_urg_ctrl[8] |
+// vdin1_lff_urg_ctrl_sync_d1 & vpu_arb_urg_ctrl[9]
+//
+#define VPU_ARB_URG_CTRL ((0x2747 << 2) + 0xff000000)
+#define VPU_SECURE_DUMMY ((0x2748 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_EN ((0x2749 << 2) + 0xff000000)
+// todo :
+#define VPU_422TO444_RST ((0x274a << 2) + 0xff000000)
+// todo :
+#define VPU_422TO444_CTRL0 ((0x274b << 2) + 0xff000000)
+// todo :
+#define VPU_422TO444_CTRL1 ((0x274c << 2) + 0xff000000)
+// todo :
+#define VPU_422TO444_CTRL2 ((0x274d << 2) + 0xff000000)
+// Picture Rotate (PROT) module 1 (for OSD) registers:
+//`define VPU_PROT1_CLK_GATE 8'h50
+//`define VPU_PROT1_GEN_CNTL 8'h51
+//`define VPU_PROT1_X_START_END 8'h52
+//`define VPU_PROT1_Y_START_END 8'h53
+//`define VPU_PROT1_Y_LEN_STEP 8'h54
+//`define VPU_PROT1_RPT_LOOP 8'h55
+//`define VPU_PROT1_RPT_PAT 8'h56
+//`define VPU_PROT1_DDR 8'h57
+//`define VPU_PROT1_RBUF_ROOM 8'h58
+//`define VPU_PROT1_STAT_0 8'h59
+//`define VPU_PROT1_STAT_1 8'h5a
+//`define VPU_PROT1_STAT_2 8'h5b
+//`define VPU_PROT1_REQ_ONOFF 8'h5c
+// Picture Rotate (PROT) module 2 (for VD) registers:
+//`define VPU_PROT2_CLK_GATE 8'h60
+//`define VPU_PROT2_GEN_CNTL 8'h61
+//`define VPU_PROT2_X_START_END 8'h62
+//`define VPU_PROT2_Y_START_END 8'h63
+//`define VPU_PROT2_Y_LEN_STEP 8'h64
+//`define VPU_PROT2_RPT_LOOP 8'h65
+//`define VPU_PROT2_RPT_PAT 8'h66
+//`define VPU_PROT2_DDR 8'h67
+//`define VPU_PROT2_RBUF_ROOM 8'h68
+//`define VPU_PROT2_STAT_0 8'h69
+//`define VPU_PROT2_STAT_1 8'h6a
+//`define VPU_PROT2_STAT_2 8'h6b
+//`define VPU_PROT2_REQ_ONOFF 8'h6c
+// Picture Rotate (PROT) module 3 (for VD) registers:
+//`define VPU_PROT3_CLK_GATE 8'h70
+//`define VPU_PROT3_GEN_CNTL 8'h71
+//`define VPU_PROT3_X_START_END 8'h72
+//`define VPU_PROT3_Y_START_END 8'h73
+//`define VPU_PROT3_Y_LEN_STEP 8'h74
+//`define VPU_PROT3_RPT_LOOP 8'h75
+//`define VPU_PROT3_RPT_PAT 8'h76
+//`define VPU_PROT3_DDR 8'h77
+//`define VPU_PROT3_RBUF_ROOM 8'h78
+//`define VPU_PROT3_STAT_0 8'h79
+//`define VPU_PROT3_STAT_1 8'h7a
+//`define VPU_PROT3_STAT_2 8'h7b
+//`define VPU_PROT3_REQ_ONOFF 8'h7c
+//Bit 20 reg_viu2vdin0_sw_reset: software reset
+//Bit 19:18 reg_viu2vdin0_dn_ratio: down-scale ratio; 0: no scale; 1: 1/2; 2:1/4; 3: reserved
+//Bit 17:16 reg_viu2vdin0_flt_mode: filter mode; 0: no filter; 1:[0 2 2 0]/4; 2:[1 1 1 1]/4; 3:[1 3 3 1]/8
+//Bit 15:14 reversed
+//Bit 13:0 reg_viu2vdin0_hsize: source horizontal size
+#define VPU_VIU2VDIN0_HDN_CTRL ((0x2780 << 2) + 0xff000000)
+#define VPU_VIU_ASYNC_MASK ((0x2781 << 2) + 0xff000000)
+#define VPU_VDIN_MISC_CTRL ((0x2782 << 2) + 0xff000000)
+// [31:29] Reserved.
+// [28:24] cntl_viu2vdin1_sel_data. Select VIU to VDIN data path, must clear it first before changing the path selection:
+// 5'b00000=Disable VIU to VDIN path;
+// 5'b00001=Enable VIU of ENC_I domain to VDIN;
+// 5'b00010=Enable VIU of ENC_P domain to VDIN;
+// 5'b00100=Enable VIU of ENC_T domain to VDIN;
+// 5'b01000=Enable VIU WriteBack 1 domain to VDIN;
+// 5'b10000=Enable VIU WriteBack 2 domain to VDIN;
+// [23:21] Reserved.
+// [20:16] cntl_viu2vdin1_sel_clk. Select which clock to VDIN path, must clear it first before changing the clock:
+// 5'b00000=Disable VIU to VDIN clock;
+// 5'b00001=Select encI clock to VDIN;
+// 5'b00010=Select encP clock to VDIN;
+// 5'b00100=Select encT clock to VDIN;
+// 5'b01000=Select VIU WriteBack 1 clock to VDIN;
+// 5'b10000=Select VIU WriteBack 2 clock to VDIN;
+// [15:13] Reserved.
+// [12: 8] cntl_viu2vdin0_sel_data. Select VIU to VDIN data path, must clear it first before changing the path selection:
+// 5'b00000=Disable VIU to VDIN path;
+// 5'b00001=Enable VIU of ENC_I domain to VDIN;
+// 5'b00010=Enable VIU of ENC_P domain to VDIN;
+// 5'b00100=Enable VIU of ENC_T domain to VDIN;
+// 5'b01000=Enable VIU WriteBack 1 domain to VDIN;
+// 5'b10000=Enable VIU WriteBack 2 domain to VDIN;
+// [ 7:5] Reserved.
+// [ 4: 0] cntl_viu2vdin0_sel_clk. Select which clock to VDIN path, must clear it first before changing the clock:
+// 5'b00000=Disable VIU to VDIN clock;
+// 5'b00001=Select encI clock to VDIN;
+// 5'b00010=Select encP clock to VDIN;
+// 5'b00100=Select encT clock to VDIN;
+// 5'b01000=Select VIU WriteBack 1 clock to VDIN;
+// 5'b10000=Select VIU WriteBack 2 clock to VDIN;
+#define VPU_VIU_VDIN_IF_MUX_CTRL ((0x2783 << 2) + 0xff000000)
+//Bit 20 reg_viu2vdin1_sw_reset: software reset
+//Bit 19:18 reg_viu2vdin1_dn_ratio: down-scale ratio; 0: no scale; 1: 1/2; 2:1/4; 3: reserved
+//Bit 17:16 reg_viu2vdin1_flt_mode: filter mode; 0: no filter; 1:[0 2 2 0]/4; 2:[1 1 1 1]/4; 3:[1 3 3 1]/8
+//Bit 15:14 reversed
+//Bit 13:0 reg_viu2vdin1_hsize: source horizontal size
+#define VPU_VIU2VDIN1_HDN_CTRL ((0x2784 << 2) + 0xff000000)
+#define VPU_VENCX_CLK_CTRL ((0x2785 << 2) + 0xff000000)
+//Bit 0 encp_afifo_clk
+//Bit 1 encl_afifo_clk
+//Bit 2 enci_afifo_clk
+// vpu arbtration :
+// the segment is 8'h90-8'hc8
+//
+// Reading file: vpu_arb_axi_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+//// reg
+////===============================////
+#define VPU_RDARB_MODE_L1C1 ((0x2790 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, rdarb_sel uns, default = 0 ,
+// rdarb_sel[0]==0 slave dc0 connect master port0 rdarb_sel[0]==1 slave dc0 connect master port1
+// rdarb_sel[1]==0 slave dc1 connect master port0 rdarb_sel[1]==1 slave dc1 connect master port1
+// rdarb_sel[2]==0 slave dc2 connect master port0 rdarb_sel[2]==1 slave dc2 connect master port1
+// rdarb_sel[3]==0 slave dc3 connect master port0 rdarb_sel[3]==1 slave dc3 connect master port1
+// rdarb_sel[4]==0 slave dc4 connect master port0 rdarb_sel[4]==1 slave dc4 connect master port1
+// rdarb_sel[5]==0 slave dc5 connect master port0 rdarb_sel[5]==1 slave dc5 connect master port1
+//Bit 15:10, reserved
+//Bit 9:8, rdarb_arb_mode uns, default = 0 ,
+// rdarb_arb_mode[0] master port0 arb way,
+// rdarb_arb_mode[1] master port1 arb way,
+//Bit 7:4, reserved
+//Bit 3:0, rdarb_gate_clk_ctrl uns, default = 0 ,
+// rdarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// rdarb_gate_clk_ctrl[3:2] master port1 clk gate control
+#define VPU_RDARB_REQEN_SLV_L1C1 ((0x2791 << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, rdarb_dc_req_en unsigned , default = 12'hfff
+// rdarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// rdarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// rdarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// rdarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// rdarb_dc_req_en[4]: the slv4 req to mst port0 enable,
+// rdarb_dc_req_en[5]: the slv5 req to mst port0 enable,
+// rdarb_dc_req_en[6]: the slv0 req to mst port1 enable,
+// rdarb_dc_req_en[7]: the slv1 req to mst port1 enable,
+// rdarb_dc_req_en[8]: the slv2 req to mst port1 enable,
+// rdarb_dc_req_en[9]: the slv3 req to mst port1 enable,
+// rdarb_dc_req_en[10]: the slv4 req to mst port1 enable,
+// rdarb_dc_req_en[11]: the slv5 req to mst port1 enable,
+#define VPU_RDARB_WEIGH0_SLV_L1C1 ((0x2792 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// rddc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// rddc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// rddc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+// rddc_weigh_sxn[4*6+:6]: the slv4 req weigh number
+#define VPU_RDARB_WEIGH1_SLV_L1C1 ((0x2793 << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[5*6+:6]: the slv5 req weigh number
+#define VPU_WRARB_MODE_L1C1 ((0x2794 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, wrarb_sel uns, default = 0 ,
+// wrarb_sel[0]==0 slave dc0 connect master port0 wrarb_sel[0]==1 slave dc0 connect master port1
+// wrarb_sel[1]==0 slave dc1 connect master port0 wrarb_sel[1]==1 slave dc1 connect master port1
+// wrarb_sel[2]==0 slave dc2 connect master port0 wrarb_sel[2]==1 slave dc2 connect master port1
+// wrarb_sel[3]==0 slave dc3 connect master port0 wrarb_sel[3]==1 slave dc3 connect master port1
+// wrarb_sel[4]==0 slave dc4 connect master port0 wrarb_sel[4]==1 slave dc4 connect master port1
+// wrarb_sel[5]==0 slave dc5 connect master port0 wrarb_sel[5]==1 slave dc5 connect master port1
+//Bit 15:10, reserved
+//Bit 9:8, wrarb_arb_mode uns, default = 0 ,
+// wrarb_arb_mode[0] master port0 arb way,
+// wrarb_arb_mode[1] master port1 arb way,
+//Bit 7:4, reserved
+//Bit 3:0, wrarb_gate_clk_ctrl uns, default = 0 ,
+// wrarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// wrarb_gate_clk_ctrl[3:2] master port1 clk gate control
+#define VPU_WRARB_REQEN_SLV_L1C1 ((0x2795 << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, wrarb_dc_req_en unsigned , default = 0
+// wrarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// wrarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// wrarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// wrarb_dc_req_en[4]: the slv4 req to mst port0 enable,
+// wrarb_dc_req_en[5]: the slv5 req to mst port0 enable,
+// wrarb_dc_req_en[0]: the slv0 req to mst port1 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port1 enable,
+// wrarb_dc_req_en[2]: the slv2 req to mst port1 enable,
+// wrarb_dc_req_en[3]: the slv3 req to mst port1 enable,
+// wrarb_dc_req_en[4]: the slv4 req to mst port1 enable,
+// wrarb_dc_req_en[5]: the slv5 req to mst port1 enable,
+#define VPU_WRARB_WEIGH0_SLV_L1C1 ((0x2796 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// wrdc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// wrdc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+// wrdc_weigh_sxn[4*6+:6]: the slv4 req weigh number
+#define VPU_WRARB_WEIGH1_SLV_L1C1 ((0x2797 << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[5*6+:6]: the slv5 req weigh number
+#define VPU_RDWR_ARB_STATUS_L1C1 ((0x2798 << 2) + 0xff000000)
+//Bit 31:4, reserved
+//Bit 3:2, wrarb_arb_busy unsigned , default = 0
+//Bit 1:0, rdarb_arb_busy unsigned , default = 0
+#define VPU_RDARB_MODE_L1C2 ((0x2799 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, rdarb_sel uns, default = 0 ,
+// rdarb_sel[0]==0 slave dc0 connect master port0 rdarb_sel[0]==1 slave dc0 connect master port1
+// rdarb_sel[1]==0 slave dc1 connect master port0 rdarb_sel[1]==1 slave dc1 connect master port1
+// rdarb_sel[2]==0 slave dc2 connect master port0 rdarb_sel[2]==1 slave dc2 connect master port1
+// rdarb_sel[3]==0 slave dc3 connect master port0 rdarb_sel[3]==1 slave dc3 connect master port1
+// rdarb_sel[4]==0 slave dc4 connect master port0 rdarb_sel[4]==1 slave dc4 connect master port1
+//Bit 15:10, reserved
+//Bit 9:8, rdarb_arb_mode uns, default = 0 ,
+// rdarb_arb_mode[0] master port0 arb way,
+// rdarb_arb_mode[1] master port1 arb way,
+//Bit 7:4, reserved
+//Bit 3:0, rdarb_gate_clk_ctrl uns, default = 0 ,
+// rdarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// rdarb_gate_clk_ctrl[3:2] master port0 clk gate control
+#define VPU_RDARB_REQEN_SLV_L1C2 ((0x279a << 2) + 0xff000000)
+//Bit 31:10, reserved
+//Bit 9:0, rdarb_dc_req_en unsigned , default = 0
+// rdarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// rdarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// rdarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// rdarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// rdarb_dc_req_en[4]: the slv4 req to mst port0 enable,
+// rdarb_dc_req_en[5]: the slv0 req to mst port1 enable,
+// rdarb_dc_req_en[6]: the slv1 req to mst port1 enable,
+// rdarb_dc_req_en[7]: the slv2 req to mst port1 enable,
+// rdarb_dc_req_en[8]: the slv3 req to mst port1 enable,
+// rdarb_dc_req_en[9]: the slv4 req to mst port1 enable,
+#define VPU_RDARB_WEIGH0_SLV_L1C2 ((0x279b << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// rddc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// rddc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// rddc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+// rddc_weigh_sxn[4*6+:6]: the slv4 req weigh number
+#define VPU_RDWR_ARB_STATUS_L1C2 ((0x279c << 2) + 0xff000000)
+//Bit 31:3, reserved
+//Bit 2, wrarb_arb_busy unsigned , default = 0
+//Bit 1:0, rdarb_arb_busy unsigned , default = 0
+#define VPU_RDARB_MODE_L2C1 ((0x279d << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, rdarb_sel uns, default = 0 ,
+// rdarb_sel[0]==0 slave dc0 connect master port0 rdarb_sel[0]==1 slave dc0 connect master port1
+// rdarb_sel[1]==0 slave dc1 connect master port0 rdarb_sel[1]==1 slave dc1 connect master port1
+// rdarb_sel[2]==0 slave dc2 connect master port0 rdarb_sel[2]==1 slave dc2 connect master port1
+// rdarb_sel[3]==0 slave dc3 connect master port0 rdarb_sel[3]==1 slave dc3 connect master port1
+// rdarb_sel[4]==0 slave dc4 connect master port0 rdarb_sel[4]==1 slave dc4 connect master port1
+// rdarb_sel[5]==0 slave dc5 connect master port0 rdarb_sel[5]==1 slave dc5 connect master port1
+//Bit 15:11, reserved
+//Bit 10:8, rdarb_arb_mode uns, default = 0 ,
+// rdarb_arb_mode[0] master port0 arb way,
+// rdarb_arb_mode[1] master port1 arb way,
+//Bit 7:6, reserved
+//Bit 5:0, rdarb_gate_clk_ctrl uns, default = 0 ,
+// rdarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// rdarb_gate_clk_ctrl[3:2] master port1 clk gate control
+// rdarb_gate_clk_ctrl[5:4] master port2 clk gate control
+#define VPU_RDARB_REQEN_SLV_L2C1 ((0x279e << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:0, rdarb_dc_req_en unsigned , default = 0
+// rdarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// rdarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// rdarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// rdarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// rdarb_dc_req_en[4]: the slv4 req to mst port0 enable,
+// rdarb_dc_req_en[5]: the slv5 req to mst port0 enable,
+// rdarb_dc_req_en[0]: the slv0 req to mst port1 enable,
+// rdarb_dc_req_en[1]: the slv1 req to mst port1 enable,
+// rdarb_dc_req_en[2]: the slv2 req to mst port1 enable,
+// rdarb_dc_req_en[3]: the slv3 req to mst port1 enable,
+// rdarb_dc_req_en[4]: the slv4 req to mst port1 enable,
+// rdarb_dc_req_en[5]: the slv5 req to mst port1 enable,
+#define VPU_RDARB_WEIGH0_SLV_L2C1 ((0x279f << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// rddc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// rddc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// rddc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+// rddc_weigh_sxn[4*6+:6]: the slv4 req weigh number
+#define VPU_RDARB_WEIGH1_SLV_L2C1 ((0x27a0 << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[5*6+:6]: the slv5 req weigh number
+#define VPU_RDWR_ARB_STATUS_L2C1 ((0x27a1 << 2) + 0xff000000)
+//Bit 31:4, reserved
+//Bit 3:2, wrarb_arb_busy unsigned , default = 0
+//Bit 1:0, rdarb_arb_busy unsigned , default = 0
+#define VPU_WRARB_MODE_L2C1 ((0x27a2 << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:16, wrarb_sel uns, default = 0 ,
+// wrarb_sel[0]==0 slave dc0 connect master port0 wrarb_sel[0]==1 slave dc0 connect master port1
+// wrarb_sel[1]==0 slave dc1 connect master port0 wrarb_sel[1]==1 slave dc1 connect master port1
+// wrarb_sel[2]==0 slave dc2 connect master port0 wrarb_sel[2]==1 slave dc2 connect master port1
+// wrarb_sel[3]==0 slave dc3 connect master port0 wrarb_sel[3]==1 slave dc3 connect master port1
+//Bit 15:10, reserved
+//Bit 9:8, wrarb_arb_mode uns, default = 0 ,
+// wrarb_arb_mode[0] master port0 arb way,
+// wrarb_arb_mode[1] master port1 arb way,
+//Bit 7:4, reserved
+//Bit 3:0, wrarb_gate_clk_ctrl uns, default = 0 ,
+// wrarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// wrarb_gate_clk_ctrl[3:2] master port0 clk gate control
+#define VPU_WRARB_REQEN_SLV_L2C1 ((0x27a3 << 2) + 0xff000000)
+//Bit 31:8, reserved
+//Bit 7:0, wrarb_dc_req_en unsigned , default = 0
+// wrarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// wrarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// wrarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// wrarb_dc_req_en[0]: the slv0 req to mst port1 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port1 enable,
+// wrarb_dc_req_en[2]: the slv2 req to mst port1 enable,
+// wrarb_dc_req_en[3]: the slv3 req to mst port1 enable,
+#define VPU_WRARB_WEIGH0_SLV_L2C1 ((0x27a4 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// wrdc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// wrdc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+#define VPU_ASYNC_RD_MODE0 ((0x27a5 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
+#define VPU_ASYNC_RD_MODE1 ((0x27a6 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
+#define VPU_ASYNC_RD_MODE2 ((0x27a7 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
+#define VPU_ASYNC_RD_MODE3 ((0x27a8 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
+#define VPU_ASYNC_RD_MODE4 ((0x27a9 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
+#define VPU_ASYNC_WR_MODE0 ((0x27aa << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
+#define VPU_ASYNC_WR_MODE1 ((0x27ab << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
+#define VPU_ASYNC_WR_MODE2 ((0x27ac << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
+#define VPU_ASYNC_STAT ((0x27ad << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, axiwr2_chan_idle unsigned , RO, axi write channel2 idle state
+//Bit 17, axiwr1_chan_idle unsigned , RO, axi write channel1 idle state
+//Bit 16, axiwr0_chan_idle unsigned , RO, axi write channel0 idle state
+//Bit 15:5, reserved
+//Bit 4, axird4_chan_idle unsigned , RO, axi read channel4 idle state
+//Bit 3, axird3_chan_idle unsigned , RO, axi read channel3 idle state
+//Bit 2, axird2_chan_idle unsigned , RO, axi read channel2 idle state
+//Bit 1, axird1_chan_idle unsigned , RO, axi read channel1 idle state
+//Bit 0, axird0_chan_idle unsigned , RO, axi read channel0 idle state
+#define VPU_WRARB_MODE_L1C2 ((0x27ae << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:16, wrarb_sel uns, default = 0 ,
+// wrarb_sel[0]==0 slave dc0 connect master port0 wrarb_sel[0]==1 slave dc0 connect master port1
+// wrarb_sel[1]==0 slave dc1 connect master port0 wrarb_sel[1]==1 slave dc1 connect master port1
+//Bit 15:9, reserved
+//Bit 8, wrarb_arb_mode uns, default = 0 ,
+// wrarb_arb_mode[0] master port0 arb way,
+//Bit 7:2, reserved
+//Bit 1:0, wrarb_gate_clk_ctrl uns, default = 0 ,
+// wrarb_gate_clk_ctrl[1:0] master port0 clk gate control
+#define VPU_WRARB_REQEN_SLV_L1C2 ((0x27af << 2) + 0xff000000)
+//Bit 31:2, reserved
+//Bit 1:0, wrarb_dc_req_en unsigned , default = 0
+// wrarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+#define VPU_WRARB_WEIGH0_SLV_L1C2 ((0x27b0 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// wrdc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[2*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[3*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[4*6+:6]: the slv1 req weigh number
+#define VPU_WRARB_WEIGH1_SLV_L1C2 ((0x27b1 << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[5*6+:6]: the slv0 req weigh number
+// wrdc_weigh_sxn[6*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[7*6+:6]: the slv1 req weigh number
+#define VPU_RDARB_WEIGH1_SLV_L1C2 ((0x27b2 << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[5*6+:6]: the slv0 req weigh number
+// rddc_weigh_sxn[6*6+:6]: the slv1 req weigh number
+// rddc_weigh_sxn[7*6+:6]: the slv2 req weigh number
+#define VPU_ARB_DBG_CTRL_L1C1 ((0x27b3 << 2) + 0xff000000)
+#define VPU_ARB_DBG_STAT_L1C1 ((0x27b4 << 2) + 0xff000000)
+#define VPU_ARB_DBG_CTRL_L1C2 ((0x27b5 << 2) + 0xff000000)
+#define VPU_ARB_DBG_STAT_L1C2 ((0x27b6 << 2) + 0xff000000)
+#define VPU_ARB_DBG_CTRL_L2C1 ((0x27b7 << 2) + 0xff000000)
+#define VPU_ARB_DBG_STAT_L2C1 ((0x27b8 << 2) + 0xff000000)
+#define VPU_ARB_PATH_CTRL ((0x27b9 << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP00 ((0x27ba << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP01 ((0x27bb << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP02 ((0x27bc << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP03 ((0x27bd << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP10 ((0x27be << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP11 ((0x27bf << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP12 ((0x27c0 << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP13 ((0x27c1 << 2) + 0xff000000)
+#define VPU_RDARB_UGT_L2C1 ((0x27c2 << 2) + 0xff000000)
+#define VPU_WRARB_UGT_L2C1 ((0x27c3 << 2) + 0xff000000)
+#define VPU_RDARB_LIMT0_L2C1 ((0x27c4 << 2) + 0xff000000)
+#define VPU_RDARB_LIMT1_L2C1 ((0x27c5 << 2) + 0xff000000)
+#define VPU_ARB_AXIWR_PROT ((0x27c6 << 2) + 0xff000000)
+#define VPU_ARB_AXIRD0_PROT ((0x27c7 << 2) + 0xff000000)
+#define VPU_ARB_AXIRD1_PROT ((0x27c8 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_arb_axi_regs.h
+//
+// vpu lut dma
+// the segment is 8'h50~8'h7f & 8'hca-8'hdf
+//
+// Reading file: vpu_lut_dma_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// 0x50~0x7f
+//
+// Reading file: viu_dma_top.h
+//
+#define VPU_DMA_RDMIF0_CTRL ((0x2750 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd0_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd0_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd0_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd0_enable_int // unsigned , RW , default = 0 channel0 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd0_stride // unsigned , RW , default = 512 channel0 send number
+#define VPU_DMA_RDMIF1_CTRL ((0x2751 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd1_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd1_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd1_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd1_enable_int // unsigned , RW , default = 0 channel1 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd1_stride // unsigned , RW , default = 512 channel1 send number
+#define VPU_DMA_RDMIF2_CTRL ((0x2752 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd2_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd2_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd2_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd2_enable_int // unsigned , RW , default = 0 channel2 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd2_stride // unsigned , RW , default = 512 channel2 send number
+#define VPU_DMA_RDMIF3_CTRL ((0x2753 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd3_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd3_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd3_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd3_enable_int // unsigned , RW , default = 0 channel3 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd3_stride // unsigned , RW , default = 512 channel3 send number
+#define VPU_DMA_RDMIF4_CTRL ((0x2754 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd4_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd4_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd4_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd4_enable_int // unsigned , RW , default = 0 channel4 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd4_stride // unsigned , RW , default = 512 channel4 send number
+#define VPU_DMA_RDMIF5_CTRL ((0x2755 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd5_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd5_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd5_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd5_enable_int // unsigned , RW , default = 0 channel5 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd5_stride // unsigned , RW , default = 512 channel5 send number
+#define VPU_DMA_RDMIF6_CTRL ((0x2756 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd6_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd6_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd6_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd6_enable_int // unsigned , RW , default = 0 channel6 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd6_stride // unsigned , RW , default = 512 channel6 send number
+#define VPU_DMA_RDMIF7_CTRL ((0x2757 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd7_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd7_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd7_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd7_enable_int // unsigned , RW , default = 0 channel7 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd7_stride // unsigned , RW , default = 512 channel7 send number
+#define VPU_DMA_RDMIF0_BADR0 ((0x2758 << 2) + 0xff000000)
+//Bit 31:0 lut0_reg_baddr0
+#define VPU_DMA_RDMIF0_BADR1 ((0x2759 << 2) + 0xff000000)
+//Bit 31:0 lut0_reg_baddr1
+#define VPU_DMA_RDMIF0_BADR2 ((0x275a << 2) + 0xff000000)
+//Bit 31:0 lut0_reg_baddr2
+#define VPU_DMA_RDMIF0_BADR3 ((0x275b << 2) + 0xff000000)
+//Bit 31:0 lut0_reg_baddr3
+#define VPU_DMA_RDMIF1_BADR0 ((0x275c << 2) + 0xff000000)
+//Bit 31:0 lut1_reg_baddr0
+#define VPU_DMA_RDMIF1_BADR1 ((0x275d << 2) + 0xff000000)
+//Bit 31:0 lut1_reg_baddr1
+#define VPU_DMA_RDMIF1_BADR2 ((0x275e << 2) + 0xff000000)
+//Bit 31:0 lut1_reg_baddr2
+#define VPU_DMA_RDMIF1_BADR3 ((0x275f << 2) + 0xff000000)
+//Bit 31:0 lut1_reg_baddr3
+#define VPU_DMA_RDMIF2_BADR0 ((0x2760 << 2) + 0xff000000)
+//Bit 31:0 lut2_reg_baddr0
+#define VPU_DMA_RDMIF2_BADR1 ((0x2761 << 2) + 0xff000000)
+//Bit 31:0 lut2_reg_baddr1
+#define VPU_DMA_RDMIF2_BADR2 ((0x2762 << 2) + 0xff000000)
+//Bit 31:0 lut2_reg_baddr2
+#define VPU_DMA_RDMIF2_BADR3 ((0x2763 << 2) + 0xff000000)
+//Bit 31:0 lut2_reg_baddr3
+#define VPU_DMA_RDMIF3_BADR0 ((0x2764 << 2) + 0xff000000)
+//Bit 31:0 lut3_reg_baddr0
+#define VPU_DMA_RDMIF3_BADR1 ((0x2765 << 2) + 0xff000000)
+//Bit 31:0 lut3_reg_baddr1
+#define VPU_DMA_RDMIF3_BADR2 ((0x2766 << 2) + 0xff000000)
+//Bit 31:0 lut3_reg_baddr2
+#define VPU_DMA_RDMIF3_BADR3 ((0x2767 << 2) + 0xff000000)
+//Bit 31:0 lut3_reg_baddr3
+#define VPU_DMA_RDMIF4_BADR0 ((0x2768 << 2) + 0xff000000)
+//Bit 31:0 lut4_reg_baddr0
+#define VPU_DMA_RDMIF4_BADR1 ((0x2769 << 2) + 0xff000000)
+//Bit 31:0 lut4_reg_baddr1
+#define VPU_DMA_RDMIF4_BADR2 ((0x276a << 2) + 0xff000000)
+//Bit 31:0 lut4_reg_baddr2
+#define VPU_DMA_RDMIF4_BADR3 ((0x276b << 2) + 0xff000000)
+//Bit 31:0 lut4_reg_baddr3
+#define VPU_DMA_RDMIF5_BADR0 ((0x276c << 2) + 0xff000000)
+//Bit 31:0 lut5_reg_baddr0
+#define VPU_DMA_RDMIF5_BADR1 ((0x276d << 2) + 0xff000000)
+//Bit 31:0 lut5_reg_baddr1
+#define VPU_DMA_RDMIF5_BADR2 ((0x276e << 2) + 0xff000000)
+//Bit 31:0 lut5_reg_baddr2
+#define VPU_DMA_RDMIF5_BADR3 ((0x276f << 2) + 0xff000000)
+//Bit 31:0 lut5_reg_baddr3
+#define VPU_DMA_RDMIF6_BADR0 ((0x2770 << 2) + 0xff000000)
+//Bit 31:0 lut6_reg_baddr0
+#define VPU_DMA_RDMIF6_BADR1 ((0x2771 << 2) + 0xff000000)
+//Bit 31:0 lut6_reg_baddr1
+#define VPU_DMA_RDMIF6_BADR2 ((0x2772 << 2) + 0xff000000)
+//Bit 31:0 lut6_reg_baddr2
+#define VPU_DMA_RDMIF6_BADR3 ((0x2773 << 2) + 0xff000000)
+//Bit 31:0 lut6_reg_baddr3
+#define VPU_DMA_RDMIF7_BADR0 ((0x2774 << 2) + 0xff000000)
+//Bit 31:0 lut7_reg_baddr0
+#define VPU_DMA_RDMIF7_BADR1 ((0x2775 << 2) + 0xff000000)
+//Bit 31:0 lut7_reg_baddr1
+#define VPU_DMA_RDMIF7_BADR2 ((0x2776 << 2) + 0xff000000)
+//Bit 31:0 lut7_reg_baddr2
+#define VPU_DMA_RDMIF7_BADR3 ((0x2777 << 2) + 0xff000000)
+//Bit 31:0 lut7_reg_baddr3
+//
+// Closing file: viu_dma_top.h
+//
+// 0x00~0x06
+//`include"viu_com_rdmif_regs.h"
+#define VPU_DMA_RDMIF_CTRL1 ((0x27ca << 2) + 0xff000000)
+#define VPU_DMA_RDMIF_CTRL2 ((0x27cb << 2) + 0xff000000)
+#define VPU_DMA_RDMIF_RO_STAT ((0x27d0 << 2) + 0xff000000)
+//0x07~0x0d
+//`include"viu_com_wrmif_regs.h"
+#define VPU_DMA_WRMIF_CTRL1 ((0x27d1 << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_CTRL2 ((0x27d2 << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_CTRL3 ((0x27d3 << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_BADDR0 ((0x27d4 << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_RO_STAT ((0x27d7 << 2) + 0xff000000)
+#define VPU_DMA_RDMIF_CTRL ((0x27d8 << 2) + 0xff000000)
+#define VPU_DMA_RDMIF_BADDR1 ((0x27d9 << 2) + 0xff000000)
+#define VPU_DMA_RDMIF_BADDR2 ((0x27da << 2) + 0xff000000)
+#define VPU_DMA_RDMIF_BADDR3 ((0x27db << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_CTRL ((0x27dc << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_BADDR1 ((0x27dd << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_BADDR2 ((0x27de << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_BADDR3 ((0x27df << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_lut_dma_regs.h
+//
+// the segment is 8'he0-8'hef
+#define VPU_VENCL_DITH_CTRL ((0x27e0 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_1 ((0x27e1 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_2 ((0x27e2 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_3 ((0x27e3 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_4 ((0x27e4 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_5 ((0x27e5 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_6 ((0x27e6 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_7 ((0x27e7 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_8 ((0x27e8 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_9 ((0x27e9 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_10 ((0x27ea << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_11 ((0x27eb << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_12 ((0x27ec << 2) + 0xff000000)
+//new added 4x4 dither
+// the segment is 8'hf0
+#define VPU_HDMI_DITH_01_04 ((0x27f0 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_01_15 ((0x27f1 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_01_26 ((0x27f2 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_01_37 ((0x27f3 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_10_04 ((0x27f4 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_10_15 ((0x27f5 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_10_26 ((0x27f6 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_10_37 ((0x27f7 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_11_04 ((0x27f8 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_11_15 ((0x27f9 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_11_26 ((0x27fa << 2) + 0xff000000)
+#define VPU_HDMI_DITH_11_37 ((0x27fb << 2) + 0xff000000)
+#define VPU_HDMI_DITH_CNTL ((0x27fc << 2) + 0xff000000)
+#define VPU_HDMI_TIMING_STAT ((0x27fd << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_top_regs.h
+//
+//========================================================================
+// MIPI CSI2 Controller Adaptor (16'h2a00 - 16'h2aff)
+//
+//========================================================================
+//`include "csi2_regs.h"
+//======================================================================
+// D2D3 registers
+//======================================================================
+//
+// Reading file: d2d3_regs.h
+//
+//===========================================================================
+// D2D3 Registers 0x - 0x
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: D2D3_VCBUS_BASE = 0x2b
+// -----------------------------------------------
+//------------------------------------------------------------------------------
+// D2D3 top-level registers
+//------------------------------------------------------------------------------
+// Bit 31 RW, rd_lock_en, 1 to allow update some read-only registers based on filed
+// Bit 30 RW, sw_rst_nobuf, 1 to reset the whole d2d3 unit
+// Bit 29:28 RW, clk_auto_dis, [29] DBR clock disable
+// [28] DPG clock disable
+// Bit 27:16 RW, clk_ctrl, [27:26] gated clock control for register unit
+// [25:24] gated clock control for DBR unit
+// [23:22] gated clock control for LBDG unit
+// [21:20] gated clock control for MBDG unit
+// [19:18] gated clock control for CBDG unit
+// [17:16] gated clock control for DBLD unit and SCD81 unit
+// Bit 15:12 Reserved
+// Bit 11 RW, lo_chroma_sign, 0: negate the u/v component of DBR left channel video output, 1: bypass
+// Bit 10 RW, ro_chroma_sign, 0: negate the u/v component of DBR right channel video output, 1: bypass
+// Bit 9 RW, vi0_chroma_sign, 0: negate the u/v component of DPG video input, 1: bypass
+// Bit 8 RW, vi1_chroma_sign, 0: negate the u/v component of DBR video input, 1: bypass
+// Bit 7:5 Reserved
+// Bit 4 RW, lg_en, Enable the LBDG unit and LBDG clock
+// Bit 3 RW, mg_en, Enable the MBDG unit and MBDG clock
+// Bit 2 RW, cg_en, Enable the CBDG unit and CBDG clock
+// Bit 1 RW, dbr_en, Enable the DBR unit and DBR clock
+// Bit 0 RW, dpg_en, Enable the DPG unit and clock except sub-unit CBDG, MBDG and LBDG
+#define D2D3_GLB_CTRL ((0x2b00 << 2) + 0xff000000)
+// Indicate the input picture size in DPG unit
+// Bit 31:16 RW, szx_vi_m1, The horizontal size minus 1
+// Bit 15:0 RW, szy_vi_m1, The vertical size minus 1
+#define D2D3_DPG_INPIC_SIZE ((0x2b01 << 2) + 0xff000000)
+// Indicate the output picture size in DBR unit
+// Bit 31:16 RW, szx_vo_m1, The horizontal size minus 1
+// Bit 15:0 RW, szy_vo_m1, The vertical size minus 1
+#define D2D3_DBR_OUTPIC_SIZE ((0x2b02 << 2) + 0xff000000)
+// Indicate the rectangular window to generate the "depth" in DPG unit
+// Bit 31:16 RW, dg_win_x_start, Horizontal start position, count from 0
+// Bit 15:0 RW, dg_win_x_end, Horizontal end position, count from 0
+#define D2D3_DGEN_WIN_HOR ((0x2b03 << 2) + 0xff000000)
+// Indicate the rectangular window to generate the "depth" in DPG unit
+// Bit 31:16 RW, dg_win_y_start, Vertical start position, count from 0
+// Bit 15:0 RW, dg_win_y_end, Vertical end position, count from 0
+#define D2D3_DGEN_WIN_VER ((0x2b04 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// CBDG SCU18 SCD81 SCD81_PRE registers
+// cg: color based depth generate module
+// scu18: scale up module
+// scd81: scale down module
+// scd81_pre: scd81 pre-scale-down module
+//------------------------------------------------------------------------------
+// Indicate parameters of pre-scale-down unit
+// Bit 31:16 RW, scd81_hphs_step, horizontal step
+// Bit 15:0 RW, scd81_hphs_ini, horizontal initial phase
+#define D2D3_PRE_SCD_H ((0x2b05 << 2) + 0xff000000)
+// Bit 31:16 RW, scu18_iniph, initial phase in SCU18,
+// [23:16] indicate the horizontal phase offset from the first data of every line
+// [31:24] indicate the vertical phase offset from the first line of every frame
+// Bit 15:12 Reserved
+// Bit 11 RW, scd81_predrop_en, 1 to enable scd81 pre-scale-down function
+// Bit 10:9 RW, cg_csc_sel, Color Space Conversion(CSC) matrix mode selector in CBDG
+// 0: BT.601 (16-235/240)
+// 1: BT.709 (16-235/240)
+// 2: BT.601 (0-255)
+// 3: BT.709 (0-255)
+// Bit 8 RW, scu18_rep_en, 1 to double each line of the SCU18 output
+// Bit 7:4 RW, scu18_factor, up-scale factor in SCU18 on DBR input depth data
+// [7:6] for vertical, 0->1:1, 1->1:2, 2->1:4, 3->1:8
+// [5:4] for horizontal, 0->1:1, 1->1:2, 2->1:4, 3->1:8
+// Bit 3:0 RW, scd81_factor, down-scale factor in SCD81 on DPG source video
+// [3:2] for vertical, 0->1:1, 1->2:1, 2->4:1, 3->8:1
+// [1:0] for horizontal, 0->1:1, 1->2:1, 2->4:1, 3->8:1
+#define D2D3_SCALER_CTRL ((0x2b06 << 2) + 0xff000000)
+// Bit 31:24 RW, cg_rpg_dth, the down |r-g| threshold for sky detect
+// Bit 23:16 RW, cg_rpg_uth, the up |r-g| threshold for sky detect
+// Bit 15:8 RW, cg_lum_dth, the down Y threshold for sky detect
+// Bit 7:0 RW, cg_lum_uth, the up Y threshold for sky detect
+#define D2D3_CG_THRESHOLD_1 ((0x2b07 << 2) + 0xff000000)
+// Bit 31:24 RW, cg_rpb_dth, the down |r-b| threshold for sky detect
+// Bit 23:16 RW, cg_rpb_uth, the up |r-b| threshold for sky detect
+// Bit 15:8 RW, cg_bpg_dth, the down |b-g| threshold for sky detect
+// Bit 7:0 RW, cg_bpg_uth, the up |b-g| threshold for sky detect
+#define D2D3_CG_THRESHOLD_2 ((0x2b08 << 2) + 0xff000000)
+// Bit 31:24 RW, cg_vp_rel_k, parameter to calculate vanish point reliability
+// Bit 23:16 RW, cg_vp_y_thr, the max limitation to calculate the vanish-point's vertical position
+// Bit 15:8 RW, cg_meet_dval, signed depth value in the sky-bitmap
+// Bit 7:0 RW, cg_unmt_dval, signed depth value not in the sky-bitmap
+#define D2D3_CG_PARAM_1 ((0x2b09 << 2) + 0xff000000)
+// Bit 31:16 RW, cg_vpos_thr, Maximal vertical limitation for sky-bit map when cg_vpos_en=1 and cg_vpos_adpt_en=0
+// Bit 15:8 Reserved
+// Bit 7 RW, cg_vpos_en, 1 to enable the max vertical limitation for sky-bitmap
+// Bit 6 RW, cg_vpos_adpt_en, 1 to enable the adaptive max vertical limitation for sky-bitmap.
+// It is only valid when cg_vpos_en=1.
+// The max vertical limitation is the previous field's vanish-point (vertical position) if cg_vpos_adpt_en=1.
+// Bit 5:4 RW, cg_lpf_bypass, bypass of low pass filter
+// [5]:Vertical bypass, 1: bypass the vertical LPF on the CBDG depth
+// [4]:Horizontal bypass, 1: bypass the horizontal LPF on the CBDG depth
+// Bit 3:0 RW, cg_vp_rel_s, parameter to calculate vanish point reliability
+#define D2D3_CG_PARAM_2 ((0x2b0a << 2) + 0xff000000)
+// Indicate parameters of pre-scale-down unit
+// Bit 31:16 RW, scd81_vphs_step, vertical step
+// Bit 15:0 RW, scd81_vphs_ini, vertical initial phase
+#define D2D3_PRE_SCD_V ((0x2b0b << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// D2P registers
+// d2p: depth to parallax transform module
+//------------------------------------------------------------------------------
+// Bit 31:24 RW, d2p_brdwid, Horizontal boundary width for parallax, the parallax value would be forced to 0 in boundary,
+// the d2p_brdwid should not 0 when D2P_WRAP is enabled
+// Bit 23:22 Reserved
+// Bit 21:20 RW, d2p_lomode, line output mode,
+// 0:whole line is left or right; 1:whole line is left or right;
+// 2:left/right pixel interleaved; 3:left/right half-line interleaved
+// Bit 19 RW, d2p_neg, 1 to exchange the left and right parallax value
+// Bit 18 Reserved
+// Bit 17 RW, d2p_wrap_en, 1 to enable D2P_WRAP unit
+// Bit 16 RW, d2p_lar, Indicate the first output for left or right, 0: left; 1: right
+// Bit 15 RW, d2p_lr_switch, enable left/right flag filed switch automatically, only valid when parallax output mode is field interleaved
+// Bit 14 RW, d2p_1dtolr, enable to generate 2 parallax data (left and right) from one depth
+// Bit 13:12 RW, d2p_out_mode, Parallax output mode
+// 0:left/right pixel interleaved; 1:line or half line interleaved; 2:field interleaved
+// Bit 11:8 RW, d2p_smode, Shift mode,
+// 0: no shift; 1: enable left shift;
+// 2: enable right shift; 3: both left and right shift are enabled
+// Bit 7:0 RW, d2p_offset, depth offset, signed,
+#define D2D3_D2P_PARAM_1 ((0x2b0c << 2) + 0xff000000)
+// Bit 31:24 RW, d2p_pg0, positive parallax gain when Parallax value < pt
+// Bit 23:16 RW, d2p_pg1, positive parallax gain when Parallax value >= pt
+// Bit 15:8 RW, d2p_pt, unsigned value used to separate the positive parallax range
+// Bit 7:0 RW, d2p_plimit, The limitation for positive parallax
+#define D2D3_D2P_PARAM_2 ((0x2b0d << 2) + 0xff000000)
+// Bit 31:24 RW, d2p_ng0, negative parallax gain when Parallax value > -nt
+// Bit 23:16 RW, d2p_ng1, negative parallax gain when Parallax value <= -nt
+// Bit 15:8 RW, d2p_nt, unsigned value used to separate the negative parallax range
+// Bit 7:0 RW, d2p_nlimit, The limitation for negative parallax
+#define D2D3_D2P_PARAM_3 ((0x2b0e << 2) + 0xff000000)
+// Indicate step parameters of SCU18 unit
+// Bit 31:17 Reserved
+// Bit 16 RW, scu18_step_en, step set enable in SCU18
+// Bit 15:8 RW, scu18_hphs_step, horizontal step in SCU18
+// Bit 7:0 RW, scu18_vphs_step, vertical step in SCU18
+#define D2D3_SCU18_STEP ((0x2b0f << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// LBDG and DBLD registers
+// lg: luma based depth generate module
+// db: depth blending module
+//------------------------------------------------------------------------------
+// Bit 31:22 Reserved
+// Bit 21:20 RW, db_lpf_bpcoeff, [21]:Vertical factor of low pass filter,
+// 1: Vfactor = 0/0/64/0/0, 0: Vfactor = {db_vf_a,db_vf_b,db_vf_c,db_vf_b,db_vf_a}, see D2D3_CTRL_15
+// [20]:Horizontal factor of low pass filter,
+// 1: Hfactor = 0/0/64/0/0, 0: Hfactor = {db_hf_a,db_hf_b,db_hf_c,db_hf_b,db_hf_a}, see D2D3_CTRL_14
+// Bit 19:18 RW, lg_lpf_bpcoeff, [19]:Vertical factor of low pass filter, 1: Vfactor = 0/64/0, 0: Vfactor = 20/24/20
+// [18]:Horizontal factor of low pass filter, 1: Hfactor = 0/64/0, 0: Hfactor = 16/32/16
+// Bit 17:16 RW, cg_lpf_bpcoeff, [17]:Vertical factor of low pass filter, 1: Vfactor = 0/64/0, 0: Vfactor = 20/24/20
+// [16]:Horizontal factor of low pass filter, 1: Hfactor = 0/64/0, 0: Hfactor = 16/32/16
+// Bit 15:10 Reserved
+// Bit 9:8 RW, db_lpf_bypass, [9] 1 to bypass the vertical LPF on the DBLD depth
+// [8] 1 to bypass the horizontal LPF on the DBLD depth
+// Bit 7:6 RW, lg_lpf_bypass, [7] 1 to bypass the vertical LPF on the LBDG depth
+// [6] 1 to bypass the horizontal LPF on the LBDG depth
+// Bit 5:0 RW, lg_kc, gain of CPL(v-u+256-y) to calculate the depth in LBDG
+#define D2D3_DPF_LPF_CTRL ((0x2b10 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// DBLD registers
+// db: depth blending module
+//------------------------------------------------------------------------------
+// Bit 31:24 RW, db_g2_cg, gain of CBDG depth in DBLD
+// Bit 23:16 RW, db_o2_cg, offset of CBDG depth in DBLD
+// Bit 15:8 RW, db_g1_cg, gain of CBDG depth using for summary in DBLD
+// Bit 7:0 RW, db_o1_cg, offset of CBDG depth using for summary in DBLD
+#define D2D3_DBLD_CG_PARAM ((0x2b11 << 2) + 0xff000000)
+// Bit 31:24 RW, db_g2_mg, gain of MBDG depth in DBLD
+// Bit 23:16 RW, db_o2_mg, offset of MBDG depth in DBLD
+// Bit 15:8 RW, db_g1_mg, gain of MBDG depth using for summary in DBLD
+// Bit 7:0 RW, db_o1_mg, offset of MBDG depth using for summary in DBLD
+#define D2D3_DBLD_MG_PARAM ((0x2b12 << 2) + 0xff000000)
+// Bit 31:24 RW, db_g2_lg, gain of LBDG depth in DBLD
+// Bit 23:16 RW, db_o2_lg, offset of LBDG depth in DBLD
+// Bit 15:8 RW, db_g1_lg, gain of LBDG depth using for summary in DBLD
+// Bit 7:0 RW, db_o1_lg, offset of LBDG depth using for summary in DBLD
+#define D2D3_DBLD_LG_PARAM ((0x2b13 << 2) + 0xff000000)
+// Bit 31:24 RW, db_factor, unsigned gain of difference in DBLD
+// Bit 23:16 RW, db_hf_a, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign
+// Bit 15:8 RW, db_hf_b, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign
+// Bit 7:0 RW, db_hf_c, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign
+#define D2D3_DBLD_LPF_HCOEFF ((0x2b14 << 2) + 0xff000000)
+// Bit 31:24 RW, db_owin_fill, signed depth value outside the rectangular window defined in register DGEN_WIN_HOR and DGEN_WIN_VER
+// Bit 23:16 RW, db_vf_a, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign
+// Bit 15:8 RW, db_vf_b, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign
+// Bit 7:0 RW, db_vf_c, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign
+#define D2D3_DBLD_LPF_VCOEFF ((0x2b15 << 2) + 0xff000000)
+// Bit 31:28 RW, hist_depth_idx,
+// Bit 27:26 Reserved
+// Bit 25 RW, mbdg_dep_neg, 1 to negate the output data of MBDG
+// Bit 24 RW, lbdg_dep_neg, 1 to negate the output data of LBDG
+// Bit 23:16 RW, db_f1_ctrl, MUX1 selector
+// [1:0] MUX1 path1 selector, 0:summary, 1:CBDG, 2:MBDG, 3:LBDG
+// [3:2] MUX1 path2 selector, 0:summary, 1:CBDG, 2:MBDG, 3:LBDG
+// [6:4] MUX1 out1 selector, 1:CBDG, 2:MBDG, 3:LBDG, 4:summary, 5:MUX1out0, others:summary
+// [7] MUX1OUT0 selector, 0:MIN (MUX1PATH1,MUX1Path2), 1:MAX (MUX1Path1,MUX1Path2)
+// Bit 15:8 RW, db_f2_ctrl, MUX2 selector
+// [1:0] MUX2 path1 selector, 0:MUX1OUT1, 1:CBDG, 2:MBDG, 3:LBDG
+// [3:2] MUX2 path2 selector, 0:MUX1OUT1, 1:CBDG, 2:MBDG, 3:LBDG
+// [6:4] MUX2 out1 selector, 1:CBDG, 2:MBDG, 3:LBDG, 4:summary, 5:MUX2out0, others:MUX2out0
+// [7] MUX2OUT0 selector, 0:MIN (MUX2PATH1,MUX2Path2), 1:MAX (MUX2Path1,MUX2Path2)
+// Bit 7:4 RW, db_fifo0_sel, the source input of FIFO0
+// 0: no use; 1:from CBDG; 2:from MBDG; 3:from LBDG others:reserved
+// Bit 3:0 RW, db_fifo1_sel, the source input of FIFO1
+// 0: no use; 1:from CBDG; 2:from MBDG; 3:from LBDG 4: from FIFO0; others:reserved
+#define D2D3_DBLD_PATH_CTRL ((0x2b16 << 2) + 0xff000000)
+// Indicate the input picture size in SCU18 unit
+// Bit 31:16 RW, szy_scui, The vertical size
+// Bit 15:0 RW, szx_scui, The horizontal size
+#define D2D3_SCU18_INPIC_SIZE ((0x2b17 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// MBDG registers
+// mg: model based depth generate module
+//------------------------------------------------------------------------------
+// Bit 31:18 Reserved
+// Bit 17 RW, mg_vp_en, mdg vanish point enable, not used
+// Bit 16 RW, mg_sw_en, 1 to use the software forced parameter for the point D, U and C in MBDG
+// Bit 15:8 RW, mg_owin_fill, Signed depth value outside the rectangular window defined in register DGEN_WIN_HOR and DGEN_WIN_VER
+// Bit 7 RW, mg_iir_en, 1 to enable the 2-taps IIR filter in MBDG
+// Bit 6:0 RW, mg_iir, [6]: 1 to bypass the 2-taps IIR filter in MBDG
+// [5:0]:Unsigned coefficient of the 2-taps IIR filter in MBDG
+// [6]:bypass, 1:bypass, 0:not bypass
+#define D2D3_MBDG_CTRL ((0x2b18 << 2) + 0xff000000)
+// Bit 31:28 RW, mg_dtl_pxl_left, Max pixel number (1<< mg_dtl_pxl_left) using in the left window for activities in MBDG
+// Bit 27:24 RW, mg_dtl_pxl_right, Max pixel number (1<< mg_dtl_pxl_right) using in the right window for activities in MBDG
+// Bit 23:16 RW, mg_cx_sw, Depth of point C in horizontal curve in MBDG for software forced
+// Bit 15:8 RW, mg_ux_sw, Depth of point U in horizontal curve in MBDG for software forced
+// Bit 7:0 RW, mg_dx_sw, Depth of point D in horizontal curve in MBDG for software forced
+#define D2D3_MBDG_PARAM_0 ((0x2b19 << 2) + 0xff000000)
+// Bit 31:28 RW, mg_dtl_pxl_up, Max pixel number (1<< mg_dtl_pxl_up) using in the top window for activities in MBDG
+// Bit 27:24 RW, mg_dtl_pxl_dn, Max pixel number (1<< mg_dtl_pxl_dn) using in the bottom window for activities in MBDG
+// Bit 23:16 RW, mg_cy_sw, Depth of point C in vertical curve in MBDG for software forced
+// Bit 15:8 RW, mg_uy_sw, Depth of point U in vertical curve in MBDG for software forced
+// Bit 7:0 RW, mg_dy_sw, Depth of point D in vertical curve in MBDG for software forced
+#define D2D3_MBDG_PARAM_1 ((0x2b1a << 2) + 0xff000000)
+// Bit 31:24 RW, mg_dtl_ln_up, Line number in the top window for activities in MBDG
+// Bit 23:16 RW, mg_dtl_ln_dn, Line number in the bottom window for activities in MBDG
+// Bit 15:8 RW, mg_dtl_ln_left, Column number in the left window for activities in MBDG
+// Bit 7:0 RW, mg_dtl_ln_right,Column number in the right window for activities in MBDG
+#define D2D3_MBDG_PARAM_2 ((0x2b1b << 2) + 0xff000000)
+// Bit 31:24 RW, mg_y_max, Software initial depth of point D and U in vertical curve
+// Bit 23:16 RW, mg_y_min, Software initial depth of point C in vertical curve
+// Bit 15:8 RW, mg_x_max, Software initial depth of point D and U in horizontal curve
+// Bit 7:0 RW, mg_x_min, Software initial depth of point C in horizontal curve
+#define D2D3_MBDG_PARAM_3 ((0x2b1c << 2) + 0xff000000)
+// Bit 31:27 Reserved
+// Bit 26 RW, mg_y_adapt_en, 1 to enable the adaptive mode for point U/D in vertical curve calculation
+// Bit 25 RW, mg_xmm_adapt_en, 1 to enable the XMM adaptive mode for point U/D in horizontal curve calculation
+// Bit 24 RW, mg_x_adapt_en, 1 to enable the adaptive mode for point U/D in horizontal curve calculation
+// Bit 23:20 RW, mg_ytrans_1, Shifter controller in vertical curve calculation, if mg_xtrans_1<0, right shift abs(mg_xtrans_1) bits, others left shift abs(mg_xtrans_1) bits
+// Bit 19:16 RW, mg_xtrans_1, Shifter controller in horizontal curve calculation, if mg_xtrans_1<0, right shift abs(mg_xtrans_1) bits, others left shift abs(mg_xtrans_1) bits
+// Bit 15:8 RW, mg_yk_0, The based activities value of the ACT for vertical curve
+// Bit 7:0 RW, mg_xk_0, The based activities value of the ACT for horizontal curve
+#define D2D3_MBDG_PARAM_4 ((0x2b1d << 2) + 0xff000000)
+// Bit 31:24 RW, mg_ysu3, Quantized value 3 in vertical curve adaptive calculation
+// Bit 23:16 RW, mg_ysu2, Quantized value 2 in vertical curve adaptive calculation
+// Bit 15:8 RW, mg_ysu1, Quantized value 1 in vertical curve adaptive calculation
+// Bit 7:0 RW, mg_ysu0, Quantized value 0 in vertical curve adaptive calculation
+#define D2D3_MBDG_PARAM_5 ((0x2b1e << 2) + 0xff000000)
+// Bit 31:24 RW, mg_xsu3, Quantized value 3 in horizontal curve adaptive calculation
+// Bit 23:16 RW, mg_xsu2, Quantized value 2 in horizontal curve adaptive calculation
+// Bit 15:8 RW, mg_xsu1, Quantized value 1 in horizontal curve adaptive calculation
+// Bit 7:0 RW, mg_xsu0, Quantized value 0 in horizontal curve adaptive calculation
+#define D2D3_MBDG_PARAM_6 ((0x2b1f << 2) + 0xff000000)
+// Bit 31:16 Reserved
+// Bit 15:8 RW, mg_xsu4, Quantized value 4 in horizontal curve adaptive calculation
+// Bit 7:0 RW, mg_ysu4, Quantized value 4 in vertical curve adaptive calculation
+#define D2D3_MBDG_PARAM_7 ((0x2b20 << 2) + 0xff000000)
+// Bit 31:28 RW, dbg_hscnt_sel see DBG_STATUS_2
+// Bit 27:25 Reserved
+// Bit 24 RW, dbg_dbr_en, 1 to enable debug mode in DBR
+// Bit 23:16 RW, dbg_force_data, Forced data in debug mode
+// Bit 15:12 RW, dbg_bld_ctrl, debug controller for DBLD
+// [12]:enable; [13]: 0 for passive mode, 0 for handshake mode
+// [15:14]: 0 for constant mode, 1 for step1 mode
+// Bit 11:8 RW, dbg_mg_ctrl, debug controller for MBDG
+// [8]:enable; [9]: 0 for passive mode, 0 for handshake mode
+// [11:10]: 0 for constant mode, 1 for step1 mode
+// Bit 7:4 RW, dbg_cg_ctrl, debug controller for CBDG
+// [4]:enable; [5]: 0 for passive mode, 0 for handshake mode
+// [7:6]: 0 for constant mode, 1 for step1 mode
+// Bit 3:0 RW, dbg_lg_ctrl, debug controller for LBDG
+// [0]:enable; [1]: 0 for passive mode, 0 for handshake mode
+// [3:2]: 0 for constant mode, 1 for step1 mode
+#define D2D3_DBG_CTRL ((0x2b23 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// DWMIF registers
+//------------------------------------------------------------------------------
+// Bit 31:18 Reserved
+// Bit 17 RW, dw_x_rev 0: Normal write data from left to right in horizontal
+// 1: Reversed write data from left to right in horizontal
+// Bit 16 RW, dw_y_rev 0: Normal write data from top to bottom in horizontal
+// 1: Reversed write data from bottom to top in horizontal
+// Bit 15 RW, dw_done_clr 1 to clear register depw_done (DWMIF_STATUS)
+// Bit 14 RW, dw_little_endian, 0: data is ordered in big-endian, 1: little endian
+// Bit 13:12 RW, dw_pic_struct, 0:read every line, 1:reserved, 2:read even line, 3:read odd line
+// Bit 11 RW, dw_urgent, urgent index
+// Bit 10 RW, dw_clr_wrrsp, 1:clear the write fifo counter
+// Bit 9 RW, dw_canvas_wr, canvas write initialization again
+// Bit 8 RW, dw_req_en, 1 to enable write request
+// Bit 7:0 RW, dw_canvas_index,Canvas index for the MSB of memory address for memory write
+#define D2D3_DWMIF_CTRL ((0x2b24 << 2) + 0xff000000)
+// Bit 31 Reserved
+// Bit 30:16 RW, dw_end_x, Horizontal end position for memory write, count by BYTE
+// Bit 15 Reserved
+// Bit 14:0 RW, dw_start_x, Horizontal start position for memory write, count by BYTE
+#define D2D3_DWMIF_HPOS ((0x2b25 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, dw_end_y, Vertical end position for memory write, count by BYTE
+// Bit 15:13 Reserved
+// Bit 12:0 RW, dw_start_y, Vertical start position for memory write, count by BYTE
+#define D2D3_DWMIF_VPOS ((0x2b26 << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, dw_vsizem1, Vertical size for memory write, equal the size minus 1
+// Bit 15:12 Reserved
+// Bit 11:0 RW, dw_hsizem1, Horizontal size for memory write, equal the size minus 1
+#define D2D3_DWMIF_SIZE ((0x2b27 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// DRMIF registers
+//------------------------------------------------------------------------------
+// Bit 31:18 Reserved
+// Bit 17 RW, dr_y_rev, 0: Normal Read data from top to bottom in horizontal
+// 1: Reversed read data from bottom to top in horizontal
+// Bit 16 RW, dr_x_rev, 0: Normal Read data from left to right in horizontal
+// 1: Reversed read data from right to left in horizontal
+// Bit 15 RW, dr_clr_fifo_error, 1 to clear the overflow flag of the sticky FIFO
+// Bit 14 RW, dr_little_endian, 0: data is ordered in big-endian; 1: little-endian
+// Bit 13:12 RW, dr_pic_struct, 0: progressive; 1: Reserved;
+// 2: interlaced, even line; 3: interlaced, odd line
+// Bit 11 RW, dr_urgent, urgent index, no use in this system
+// Bit 10:9 RW, dr_burst_size, Burst read length for each request; 0=24,1=32,2=48,3=64
+// Bit 8 RW, dr_req_en, 1 to enable read request
+// Bit 7:0 RW, dr_canvas_index, Canvas index for the MSB of memory address for memory read
+#define D2D3_DRMIF_CTRL ((0x2b28 << 2) + 0xff000000)
+// Bit 31 Reserved
+// Bit 30:16 RW, dr_end_x, Horizontal end position for memory read, count by BYTE
+// Bit 15 Reserved
+// Bit 14:0 RW, dr_start_x, Horizontal start position for memory read, count by BYTE
+#define D2D3_DRMIF_HPOS ((0x2b29 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, dr_end_y, Vertical end position for memory read, count by BYTE
+// Bit 15:13 Reserved
+// Bit 12:0 RW, dr_start_y, Vertical start position for memory read, count by BYTE
+#define D2D3_DRMIF_VPOS ((0x2b2a << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// PDR registers
+// ddd: parallax based render
+//------------------------------------------------------------------------------
+// Bit 31:8 Reserved
+// Bit 7 RW, ddd_brdlpf_en, 1 to enable the smooth filter on the depth around the boundary
+// Bit 6 RW, ddd_extn_black, 1 to enable the function to fill black colour when interpolated pixels is outside the picture in DBR
+// Bit 5 RW, ddd_wrap_en, Reserved
+// Bit 4 RW, ddd_hhalf, 1 to indicate the left/right line length is a half of original line.
+// Bit 3:2 RW, ddd_out_mode, Reserved
+// Bit 1:0 RW, ddd_lomode, wrap & pbr interleave mode:
+// 2'b0x: whole line is left or right;
+// 2'b10: d2p_lar=1(D2P_PARAM_1), rlrlrlrl inteleave in one line,
+// d2p_lar=0(D2P_PARAM_1), lrlrlrlr inteleave in one line,
+// 2'b11: d2p_lar=1(D2P_PARAM_1), rrrrrlllll, half line is right, another half is left,
+// d2p_lar=0(D2P_PARAM_1), lllllrrrrr, half line is left, another half is right,
+#define D2D3_DBR_DDD_CTRL ((0x2b2c << 2) + 0xff000000)
+// Bit 31:0 RW, ddd_dbg_ctrl, no use
+#define D2D3_DBR_DDD_DBG ((0x2b2d << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// LRDMX registers
+//------------------------------------------------------------------------------
+// Bit 31:9 Reserved
+// Bit 8 RW, lr_merge, 1: all the left/right input go to the left channel output
+// Bit 7:6 RW, lrd_ff0_sel, FF0 source selector
+// 0:from left input; 1:from right input; 2:from FF0; 3:no used
+// Bit 5:4 RW, lrd_ff1_sel, FF1 source selector
+// 0:from left input; 1:from right input; 2:from FF0; 3:no used
+// Bit 3:2 RW, lrd_lout_sel, left channel DEMUX
+// 00: ff0 01:ff1 10: left input 11:right input
+// Bit 1:0 RW, lrd_rout_sel, right channel DEMUX
+// 00: ff1 01:ff0 10: left input 11:right input
+#define D2D3_DBR_LRDMX_CTRL ((0x2b2f << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// Read Only registers
+//------------------------------------------------------------------------------
+// Bit 31:24 RO, ro_cg_vprel, vanish point's reliability in CBDG
+// Bit 23:12 RO, ro_cg_vpx, vanish point's X-Axis in CBDG
+// Bit 11:0 RO, ro_cg_vpy, vanish point's Y-Axis in CBDG
+#define D2D3_CBDG_STATUS_1 ((0x2b30 << 2) + 0xff000000)
+// Bit 31:24 RO, ro_mg_cx[7:0], X-Axis of point C in horizontal curve in MBDG
+// Bit 23:16 RO, ro_mg_ux, Depth value of point U in horizontal curve in MBDG
+// Bit 15:8 RO, ro_mg_dx, Depth value of point D in horizontal curve in MBDG
+// Bit 7:0 RO, ro_mg_minx, Depth value of point C in horizontal curve in MBDG
+#define D2D3_MBDG_STATUS_1 ((0x2b31 << 2) + 0xff000000)
+// Bit 31:24 RO, ro_mg_cy[7:0], X-Axis of point C in vertical curve in MBDG
+// Bit 23:16 RO, ro_mg_uy, Depth value of point U in vertical curve in MBDG
+// Bit 15:8 RO, ro_mg_dy, Depth value of point D in vertical curve in MBDG
+// Bit 7:0 RO, ro_mg_miny, Depth value of point C in vertical curve in MBDG
+#define D2D3_MBDG_STATUS_2 ((0x2b32 << 2) + 0xff000000)
+// Bit 31 RO, ro_wrap_status, 1 indicate the D2P_WRAP is busy to perform the initialization
+// Bit 30:8 Reserved
+// Bit 7:4 RO, ro_mg_cy[11:8], X-Axis of point C in vertical curve in MBDG
+// Bit 3:0 RO, ro_mg_cx[11:8], X-Axis of point C in horizontal curve in MBDG
+#define D2D3_MBDG_STATUS_3 ((0x2b33 << 2) + 0xff000000)
+// Bit 31:21 Reserved
+// Bit 20:0 RO, ro_mg_sum_u, ACT(top): activities of the top part
+#define D2D3_MBDG_STATUS_4 ((0x2b34 << 2) + 0xff000000)
+// Bit 31:21 Reserved
+// Bit 20:0 RO, ro_mg_sum_d, ACT(bottom): activities of the bottom part
+#define D2D3_MBDG_STATUS_5 ((0x2b35 << 2) + 0xff000000)
+// Bit 31:21 Reserved
+// Bit 20:0 RO, ro_mg_sum_l, ACT(left): activities of the left part
+#define D2D3_MBDG_STATUS_6 ((0x2b36 << 2) + 0xff000000)
+// Bit 31:21 Reserved
+// Bit 20:0 RO, ro_mg_sum_r, ACT(right): activities of the right part
+#define D2D3_MBDG_STATUS_7 ((0x2b37 << 2) + 0xff000000)
+// Bit 31:0 dbg_handshake_ro0, handshake signal for debug, internal srdy and rrdy
+#define D2D3_DBG_STATUS_1 ((0x2b38 << 2) + 0xff000000)
+// Bit 31:0 dbg_hscnt, dbg_hscnt_sel == 4'h0, output lg hscnt
+// dbg_hscnt_sel == 4'h1, output cg hscnt
+// dbg_hscnt_sel == 4'h2, output mg hscnt
+// dbg_hscnt_sel == 4'h3, output bld hscnt
+// dbg_hscnt_sel == other value, output 32'h0
+#define D2D3_DBG_STATUS_2 ((0x2b39 << 2) + 0xff000000)
+// Bit 31:0 RO, drmif_status, drmif module internal status
+#define D2D3_DRMIF_STATUS ((0x2b3a << 2) + 0xff000000)
+// Bit 31:2 RO, Reserved
+// Bit 1:0 RO, d2d3_status0, [1]: depw_done, one field depth write to ddr has done
+// [0]: dwmif_pending_ddr_wrrsp, 1 to indicate write response from ddr
+#define D2D3_DWMIF_STATUS ((0x2b3b << 2) + 0xff000000)
+// Bit 31:24 Reserved
+// Bit 23:0 RO, ro_meet_sum, register sumxy_sum_dbg in CBDG
+#define D2D3_CBDG_STATUS_2 ((0x2b3c << 2) + 0xff000000)
+// Bit 31:20 Reserved
+// Bit 19:0 RO, ro_hist_depth,
+#define D2D3_DBLD_STATUS ((0x2b3d << 2) + 0xff000000)
+// Bit 31:0 Reserved
+#define D2D3_RESEV_STATUS1 ((0x2b3e << 2) + 0xff000000)
+// Bit 31:0 Reserved
+#define D2D3_RESEV_STATUS2 ((0x2b3f << 2) + 0xff000000)
+//
+// Closing file: d2d3_regs.h
+//
+//========================================================================
+// MIPI DSI Host Controller (16'h2c00 - 16'h2cff)
+//
+//========================================================================
+//`include "dsi_regs.h"
+//========================================================================
+// ISP register (16'h2d00 - 16'h2dff)
+//========================================================================
+//`include "isp_reg.h"
+//
+// Reading file: vpu_dnr_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: MADB_VCBUS_BASE = 0x2d
+// -----------------------------------------------
+#define DNR_CTRL ((0x2d00 << 2) + 0xff000000)
+//Bit 31:17, reserved
+//Bit 16, reg_dnr_en , dnr enable . unsigned , default = 1
+//Bit 15, reg_dnr_db_vdbstep , vdb step, 0: 4, 1: 8 . unsigned , default = 1
+//Bit 14, reg_dnr_db_vdbprten , vdb protectoin enable . unsigned , default = 1
+//Bit 13, reg_dnr_gbs_difen , enable dif (between LR and LL/RR) condition for gbs stat.. unsigned , default = 0
+//Bit 12, reg_dnr_luma_en , enable ycbcr2luma module . unsigned , default = 1
+//Bit 11:10, reg_dnr_db_mod , deblocking mode, 0: disable, 1: horizontal deblocking, 2: vertical deblocking, 3: horizontal & vertical deblocking. unsigned , default = 3
+//Bit 9, reg_dnr_db_chrmen , enable chroma deblocking . unsigned , default = 1
+//Bit 8, reg_dnr_hvdif_mod , 0: calc. difs by original Y, 1: by new luma. unsigned , default = 1
+//Bit 7, reserved
+//Bit 6: 4, reg_dnr_demo_lften , b0: Y b1:U b2:V . unsigned , default = 7
+//Bit 3, reserved
+//Bit 2: 0, reg_dnr_demo_rgten , b0: Y b1:U b2:V . unsigned , default = 7
+#define DNR_HVSIZE ((0x2d01 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_dnr_hsize , hsize . unsigned , default = 0
+//Bit 15:13, reserved
+//Bit 12: 0, reg_dnr_vsize , vsize . unsigned , default = 0
+#define DNR_DBLK_BLANK_NUM ((0x2d02 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_dblk_hblank_num , deblock hor blank num . unsigned , default = 16
+//Bit 7: 0, reg_dblk_vblank_num , deblock ver blank num . unsigned , default = 45
+#define DNR_BLK_OFFST ((0x2d03 << 2) + 0xff000000)
+//Bit 31: 7, reserved
+//Bit 6: 4, reg_dnr_hbofst , horizontal block offset may provide by software calc.. unsigned , default = 0
+//Bit 3, reserved
+//Bit 2: 0, reg_dnr_vbofst , vertical block offset may provide by software calc.. unsigned , default = 0
+#define DNR_GBS ((0x2d04 << 2) + 0xff000000)
+//Bit 31: 2, reserved
+//Bit 1: 0, reg_dnr_gbs , global block strength may update by software calc.. unsigned , default = 0
+#define DNR_HBOFFST_STAT ((0x2d05 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_hbof_difthd , dif threshold (>=) between LR and LL/RR. unsigned , default = 2
+//Bit 23:16, reg_dnr_hbof_edgethd , edge threshold (<=) for LR . unsigned , default = 32
+//Bit 15: 8, reg_dnr_hbof_flatthd , flat threshold (>=) for LR . unsigned , default = 0
+//Bit 7, reserved
+//Bit 6: 4, reg_dnr_hbof_delta , delta for weighted bin accumulator. unsigned , default = 1
+//Bit 3, reserved
+//Bit 2: 0, reg_dnr_hbof_statmod , statistic mode for horizontal block offset, 0: count flags for 8-bin, 1: count LRs for 8-bin, 2: count difs for 8-bin, 3: count weighted flags for 8-bin, 4: count flags for first 32-bin, 5: count LRs for first 32-bin, 6 or 7: count difs for first 32-bin. unsigned , default = 2
+#define DNR_VBOFFST_STAT ((0x2d06 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_vbof_difthd , dif threshold (>=) between Up and Dw. unsigned , default = 1
+//Bit 23:16, reg_dnr_vbof_edgethd , edge threshold (<=) for Up/Dw. unsigned , default = 16
+//Bit 15: 8, reg_dnr_vbof_flatthd , flat threshold (>=) for Up/Dw. unsigned , default = 0
+//Bit 7, reserved
+//Bit 6: 4, reg_dnr_vbof_delta , delta for weighted bin accumulator. unsigned , default = 1
+//Bit 3, reserved
+//Bit 2: 0, reg_dnr_vbof_statmod , statistic mode for vertical block offset, 0: count flags for 8-bin, 1: count Ups for 8-bin, 2: count difs for 8-bin, 3: count weighted flags for 8-bin, 4: count flags for first 32-bin, 5: count Ups for first 32-bin, 6 or 7: count difs for first 32-bin. unsigned , default = 2
+#define DNR_GBS_STAT ((0x2d07 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_gbs_edgethd , edge threshold (<=) for LR . unsigned , default = 32
+//Bit 23:16, reg_dnr_gbs_flatthd , flat threshold (>=) for LR . unsigned , default = 0
+//Bit 15: 8, reg_dnr_gbs_varthd , variation threshold (<=) for Lvar/Rvar. unsigned , default = 16
+//Bit 7: 0, reg_dnr_gbs_difthd , dif threshold (>=) between LR and LL/RR. unsigned , default = 2
+#define DNR_STAT_X_START_END ((0x2d08 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:16, reg_dnr_stat_xst . unsigned , default = 24
+//Bit 15:14, reserved
+//Bit 13: 0, reg_dnr_stat_xed . unsigned , default = HSIZE - 25
+#define DNR_STAT_Y_START_END ((0x2d09 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:16, reg_dnr_stat_yst . unsigned , default = 24
+//Bit 15:14, reserved
+//Bit 13: 0, reg_dnr_stat_yed . unsigned , default = VSIZE - 25
+#define DNR_LUMA ((0x2d0a << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:24, reg_dnr_luma_sqrtshft , left shift for fast squart of chroma, [0, 4]. unsigned , default = 2
+//Bit 23:21, reserved
+//Bit 20:16, reg_dnr_luma_sqrtoffst , offset for fast squart of chroma. signed , default = 0
+//Bit 15, reserved
+//Bit 14:12, reg_dnr_luma_wcmod , theta related to warm/cool segment line, 0: 0, 1: 45, 2: 90, 3: 135, 4: 180, 5: 225, 6: 270, 7: 315. . unsigned , default = 3
+//Bit 11: 8, reg_dnr_luma_cshft , shift for calc. delta part, 0~8, . unsigned , default = 8
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_dnr_luma_cgain , final gain for delta part, 32 normalized to "1". unsigned , default = 4
+#define DNR_DB_YEDGE_THD ((0x2d0b << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_db_yedgethd0 , edge threshold0 for luma . unsigned , default = 12
+//Bit 23:16, reg_dnr_db_yedgethd1 , edge threshold1 for luma . unsigned , default = 15
+//Bit 15: 8, reg_dnr_db_yedgethd2 , edge threshold2 for luma . unsigned , default = 18
+//Bit 7: 0, reg_dnr_db_yedgethd3 , edge threshold3 for luma . unsigned , default = 25
+#define DNR_DB_CEDGE_THD ((0x2d0c << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_db_cedgethd0 , edge threshold0 for chroma . unsigned , default = 12
+//Bit 23:16, reg_dnr_db_cedgethd1 , edge threshold1 for chroma . unsigned , default = 15
+//Bit 15: 8, reg_dnr_db_cedgethd2 , edge threshold2 for chroma . unsigned , default = 18
+//Bit 7: 0, reg_dnr_db_cedgethd3 , edge threshold3 for chroma . unsigned , default = 25
+#define DNR_DB_HGAP ((0x2d0d << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_dnr_db_hgapthd , horizontal gap thd (<=) for very sure blockiness . unsigned , default = 8
+//Bit 15: 8, reg_dnr_db_hgapdifthd , dif thd between hgap and lft/rgt hdifs. unsigned , default = 1
+//Bit 7: 1, reserved
+//Bit 0, reg_dnr_db_hgapmod , horizontal gap calc. mode, 0: just use current col x, 1: find max between (x-1, x, x+1) . unsigned , default = 0
+#define DNR_DB_HBS ((0x2d0e << 2) + 0xff000000)
+//Bit 31: 6, reserved
+//Bit 5: 4, reg_dnr_db_hbsup , horizontal bs up value . unsigned , default = 1
+//Bit 3: 2, reg_dnr_db_hbsmax , max value of hbs for global control. unsigned , default = 3
+//Bit 1: 0, reg_dnr_db_hgbsthd , gbs thd (>=) for hbs calc. . unsigned , default = 1
+#define DNR_DB_HACT ((0x2d0f << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_dnr_db_hactthd0 , thd0 of hact, for block classification. unsigned , default = 10
+//Bit 7: 0, reg_dnr_db_hactthd1 , thd1 of hact, for block classification. unsigned , default = 32
+#define DNR_DB_YHDELTA_GAIN ((0x2d10 << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:24, reg_dnr_db_yhdeltagain1 , (p1-q1) gain for Y's delta calc. when bs=1, normalized 8 as "1" . unsigned , default = 2
+//Bit 23, reserved
+//Bit 22:20, reg_dnr_db_yhdeltagain2 , (p1-q1) gain for Y's delta calc. when bs=2, normalized 8 as "1" . unsigned , default = 0
+//Bit 19, reserved
+//Bit 18:16, reg_dnr_db_yhdeltagain3 , (p1-q1) gain for Y's delta calc. when bs=3, normalized 8 as "1" . unsigned , default = 0
+//Bit 15, reserved
+//Bit 14: 8, reg_dnr_db_yhdeltaadjoffst , offset for adjust Y's hdelta (-64, 63). signed , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_dnr_db_yhdeltaadjgain , gain for adjust Y's hdelta, normalized 32 as "1" . unsigned , default = 32
+#define DNR_DB_YHDELTA2_GAIN ((0x2d11 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_dnr_db_yhdelta2gain2 , gain for bs=2's adjust Y's hdelta2, normalized 64 as "1" . unsigned , default = 8
+//Bit 23:21, reserved
+//Bit 20:16, reg_dnr_db_yhdelta2offst2 , offset for bs=2's adjust Y's hdelta2 (-16, 15). signed , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_dnr_db_yhdelta2gain3 , gain for bs=3's adjust Y's hdelta2, normalized 64 as "1" . unsigned , default = 4
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_db_yhdelta2offst3 , offset for bs=3's adjust Y's hdelta2 (-16, 15). signed , default = 0
+#define DNR_DB_CHDELTA_GAIN ((0x2d12 << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:24, reg_dnr_db_chdeltagain1 , (p1-q1) gain for UV's delta calc. when bs=1, normalized 8 as "1". unsigned , default = 2
+//Bit 23, reserved
+//Bit 22:20, reg_dnr_db_chdeltagain2 , (p1-q1) gain for UV's delta calc. when bs=2, normalized 8 as "1". unsigned , default = 0
+//Bit 19, reserved
+//Bit 18:16, reg_dnr_db_chdeltagain3 , (p1-q1) gain for UV's delta calc. when bs=3, normalized 8 as "1". unsigned , default = 0
+//Bit 15, reserved
+//Bit 14: 8, reg_dnr_db_chdeltaadjoffst , offset for adjust UV's hdelta (-64, 63). signed , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_dnr_db_chdeltaadjgain , gain for adjust UV's hdelta, normalized 32 as "1". unsigned , default = 32
+#define DNR_DB_CHDELTA2_GAIN ((0x2d13 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_dnr_db_chdelta2gain2 , gain for bs=2's adjust UV's hdelta2, normalized 64 as "1" . unsigned , default = 8
+//Bit 23:21, reserved
+//Bit 20:16, reg_dnr_db_chdelta2offst2 , offset for bs=2's adjust UV's hdelta2 (-16, 15). signed , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_dnr_db_chdelta2gain3 , gain for bs=2's adjust UV's hdelta2, normalized 64 as "1" . unsigned , default = 4
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_db_chdelta2offst3 , offset for bs=2's adjust UV's hdelta2 (-16, 15). signed , default = 0
+#define DNR_DB_YC_VEDGE_THD ((0x2d14 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_dnr_db_yvedgethd , special Y's edge thd for vdb. unsigned , default = 12
+//Bit 7: 0, reg_dnr_db_cvedgethd , special UV's edge thd for vdb. unsigned , default = 12
+#define DNR_DB_VBS_MISC ((0x2d15 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_db_vgapthd , vertical gap thd (<=) for very sure blockiness . unsigned , default = 8
+//Bit 23:16, reg_dnr_db_vactthd , thd of vact, for block classification . unsigned , default = 10
+//Bit 15: 8, reg_dnr_db_vgapdifthd , dif thd between vgap and vact. unsigned , default = 4
+//Bit 7: 4, reserved
+//Bit 3: 2, reg_dnr_db_vbsmax , max value of vbs for global control. unsigned , default = 2
+//Bit 1: 0, reg_dnr_db_vgbsthd , gbs thd (>=) for vbs calc. . unsigned , default = 1
+#define DNR_DB_YVDELTA_GAIN ((0x2d16 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_dnr_db_yvdeltaadjgain , gain for adjust Y's vdelta, normalized 32 as "1". unsigned , default = 32
+//Bit 23, reserved
+//Bit 22:16, reg_dnr_db_yvdeltaadjoffst , offset for adjust Y's vdelta (-64, 63). signed , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_dnr_db_yvdelta2gain , gain for adjust Y's vdelta2, normalized 64 as "1". unsigned , default = 8
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_db_yvdelta2offst , offset for adjust Y's vdelta2 (-16, 15). signed , default = 0
+#define DNR_DB_CVDELTA_GAIN ((0x2d17 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_dnr_db_cvdeltaadjgain , gain for adjust UV's vdelta, normalized 32 as "1". unsigned , default = 32
+//Bit 23, reserved
+//Bit 22:16, reg_dnr_db_cvdeltaadjoffst , offset for adjust UV's vdelta (-64, 63). signed , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_dnr_db_cvdelta2gain , gain for adjust UV's vdelta2, normalized 64 as "1". unsigned , default = 8
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_db_cvdelta2offst , offset for adjust UV's vdelta2 (-16, 15). signed , default = 0
+#define DNR_RO_GBS_STAT_LR ((0x2d18 << 2) + 0xff000000)
+//Bit 31: 0, ro_gbs_stat_lr . unsigned , default = 0
+#define DNR_RO_GBS_STAT_LL ((0x2d19 << 2) + 0xff000000)
+//Bit 31: 0, ro_gbs_stat_ll . unsigned , default = 0
+#define DNR_RO_GBS_STAT_RR ((0x2d1a << 2) + 0xff000000)
+//Bit 31: 0, ro_gbs_stat_rr . unsigned , default = 0
+#define DNR_RO_GBS_STAT_DIF ((0x2d1b << 2) + 0xff000000)
+//Bit 31: 0, ro_gbs_stat_dif . unsigned , default = 0
+#define DNR_RO_GBS_STAT_CNT ((0x2d1c << 2) + 0xff000000)
+//Bit 31: 0, ro_gbs_stat_cnt . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_0 ((0x2d1d << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt0 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_1 ((0x2d1e << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt1 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_2 ((0x2d1f << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt2 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_3 ((0x2d20 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt3 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_4 ((0x2d21 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt4 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_5 ((0x2d22 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt5 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_6 ((0x2d23 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt6 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_7 ((0x2d24 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt7 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_8 ((0x2d25 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt8 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_9 ((0x2d26 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt9 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_10 ((0x2d27 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt10 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_11 ((0x2d28 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt11 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_12 ((0x2d29 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt12 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_13 ((0x2d2a << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt13 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_14 ((0x2d2b << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt14 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_15 ((0x2d2c << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt15 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_16 ((0x2d2d << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt16 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_17 ((0x2d2e << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt17 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_18 ((0x2d2f << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt18 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_19 ((0x2d30 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt19 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_20 ((0x2d31 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt20 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_21 ((0x2d32 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt21 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_22 ((0x2d33 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt22 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_23 ((0x2d34 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt23 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_24 ((0x2d35 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt24 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_25 ((0x2d36 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt25 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_26 ((0x2d37 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt26 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_27 ((0x2d38 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt27 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_28 ((0x2d39 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt28 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_29 ((0x2d3a << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt29 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_30 ((0x2d3b << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt30 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_31 ((0x2d3c << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt31 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_0 ((0x2d3d << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt0 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_1 ((0x2d3e << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt1 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_2 ((0x2d3f << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt2 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_3 ((0x2d40 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt3 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_4 ((0x2d41 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt4 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_5 ((0x2d42 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt5 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_6 ((0x2d43 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt6 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_7 ((0x2d44 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt7 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_8 ((0x2d45 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt8 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_9 ((0x2d46 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt9 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_10 ((0x2d47 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt10 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_11 ((0x2d48 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt11 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_12 ((0x2d49 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt12 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_13 ((0x2d4a << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt13 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_14 ((0x2d4b << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt14 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_15 ((0x2d4c << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt15 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_16 ((0x2d4d << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt16 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_17 ((0x2d4e << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt17 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_18 ((0x2d4f << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt18 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_19 ((0x2d50 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt19 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_20 ((0x2d51 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt20 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_21 ((0x2d52 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt21 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_22 ((0x2d53 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt22 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_23 ((0x2d54 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt23 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_24 ((0x2d55 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt24 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_25 ((0x2d56 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt25 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_26 ((0x2d57 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt26 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_27 ((0x2d58 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt27 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_28 ((0x2d59 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt28 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_29 ((0x2d5a << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt29 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_30 ((0x2d5b << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt30 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_31 ((0x2d5c << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt31 . unsigned , default = 0
+#define DNR_DM_ADP_EN ((0x2d5d << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7 reg_dnr_scene_change_flg // unsigned , default = 1 , scence change flag for dnr(dm);
+//Bit 6 reg_dnr_dm_lpf_en // unsigned , default = 1 , enable lpf for demosquito filter
+//Bit 5 reg_dnr_dm_adp_level_en // unsigned , default = 1 , enable adptive demosquito level
+//Bit 4 reg_dnr_dm_flg2bdif_en // unsigned , default = 1 , enable edge flg to blkdif calc.
+//Bit 3: 2 reg_dnr_dm_edgeiir // unsigned , default = 1 , edge flag iir mode, 0: cur, 1: max(pre, cur), 2: choice 0/1 by org mtn, 3: choice 0/1 by ref mtn
+//Bit 1 reg_dnr_dm_dirdifmod // unsigned , default = 1 , dif mode for direction calc, 0: abs(dif02), 1: (abs(dif01)+abs(dif21))/2
+//Bit 0 reg_dnr_dm_sur_dir_mod // unsigned , default = 0 , sure direction mode for cordif calc.
+#define DNR_DM_EDGE_DIR ((0x2d5e << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_dnr_dm_dirdifcor // unsigned , default = 2 , dif coring threshold for direction calc
+//Bit 15: 8 reg_dnr_dm_edgecordifthd // unsigned , default = 160 , edge flg down when cordif is large than threshold
+//Bit 7: 0 reg_dnr_dm_mtnrt // unsigned , default = 60 , motion ratio for mtn decision
+#define DNR_DM_CTRL ((0x2d60 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12, reg_dnr_dm_fedgeflg_en , enable edge flag calc. of each frame. unsigned , default = 1
+//Bit 11, reg_dnr_dm_fedgeflg_cl , clear frame edge flag if needed. unsigned , default = 1
+//Bit 10, reg_dnr_dm_fedgeflg_df , user defined edge when reg_dnr_dm_fedgeflg_en=0, default = 1
+//Bit 9, reg_dnr_dm_en , enable demosquito function . unsigned , default = 1
+//Bit 8, reg_dnr_dm_chrmen , enable chrome processing for demosquito. unsigned , default = 1
+//Bit 7: 6, reg_dnr_dm_level , demosquito level . unsigned , default = 3
+//Bit 5: 4, reg_dnr_dm_leveldw0 , level down when gbs is small. unsigned , default = 1
+//Bit 3: 2, reg_dnr_dm_leveldw1 , level down for no edge/flat blocks. unsigned , default = 1
+//Bit 1: 0, reg_dnr_dm_gbsthd , small/large threshold for gbs (<=). unsigned , default = 0
+#define DNR_DM_NR_BLND ((0x2d61 << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24, reg_dnr_dm_defalpen , enable user define alpha for dm & nr blend. unsigned , default = 0
+//Bit 23:16, reg_dnr_dm_defalp , user define alpha for dm & nr blend if enable. unsigned , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_dnr_dm_alpgain , gain for nr/dm alpha, normalized 32 as "1". unsigned , default = 32
+//Bit 7: 0, reg_dnr_dm_alpoffst , (-128, 127), offset for nr/dm alpha. signed , default = 0
+#define DNR_DM_RNG_THD ((0x2d62 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_dnr_dm_rngminthd . unsigned , default = 2
+//Bit 15: 8, reg_dnr_dm_rngmaxthd . unsigned , default = 64
+//Bit 7: 0, reg_dnr_dm_rngdifthd . unsigned , default = 4
+#define DNR_DM_RNG_GAIN_OFST ((0x2d63 << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13: 8, reg_dnr_dm_rnggain , normalized 16 as "1" . unsigned , default = 16
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_dnr_dm_rngofst . unsigned , default = 0
+#define DNR_DM_DIR_MISC ((0x2d64 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29, reg_dnr_dm_diralpen . unsigned , default = 1
+//Bit 28:24, reg_dnr_dm_diralpgain . unsigned , default = 0
+//Bit 23:22, reserved
+//Bit 21:16, reg_dnr_dm_diralpofst . unsigned , default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_diralpmin . unsigned , default = 0
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_diralpmax . unsigned , default = 31
+#define DNR_DM_COR_DIF ((0x2d65 << 2) + 0xff000000)
+//Bit 31: 4, reserved
+//Bit 3: 1, reg_dnr_dm_cordifshft . unsigned , default = 3
+//Bit 0, reg_dnr_dm_cordifmod , 0:use max dir dif as cordif, 1: use max3x3 - min3x3 as cordif. unsigned , default = 1
+#define DNR_DM_FLT_THD ((0x2d66 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_dm_fltthd00 , block flat threshold0 for block average difference when gbs is small, for flat block detection. unsigned , default = 4
+//Bit 23:16, reg_dnr_dm_fltthd01 , block flat threshold1 for block average difference when gbs is small, for flat block detection. unsigned , default = 6
+//Bit 15: 8, reg_dnr_dm_fltthd10 , block flat threshold0 for block average difference when gbs is large, for flat block detection. unsigned , default = 9
+//Bit 7: 0, reg_dnr_dm_fltthd11 , block flat threshold1 for block average difference when gbs is large, for flat block detection. unsigned , default = 12
+#define DNR_DM_VAR_THD ((0x2d67 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_dm_varthd00 , block variance threshold0 (>=) when gbs is small, for flat block detection. unsigned , default = 2
+//Bit 23:16, reg_dnr_dm_varthd01 , block variance threshold1 (<=) when gbs is small, for flat block detection. unsigned , default = 15
+//Bit 15: 8, reg_dnr_dm_varthd10 , block variance threshold0 (>=) when gbs is large, for flat block detection. unsigned , default = 3
+//Bit 7: 0, reg_dnr_dm_varthd11 , block variance threshold1 (<=) when gbs is large, for flat block detection. unsigned , default = 24
+#define DNR_DM_EDGE_DIF_THD ((0x2d68 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_dm_edgethd0 , block edge threshold (<=) when gbs is small, for flat block detection. unsigned , default = 32
+//Bit 23:16, reg_dnr_dm_edgethd1 , block edge threshold (<=) when gbs is large, for flat block detection. unsigned , default = 48
+//Bit 15: 8, reg_dnr_dm_difthd0 , block dif threshold (<=) when gbs is small, for flat block detection. unsigned , default = 48
+//Bit 7: 0, reg_dnr_dm_difthd1 , block dif threshold (<=) when gbs is large, for flat block detection. unsigned , default = 64
+#define DNR_DM_AVG_THD ((0x2d69 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_dnr_dm_avgthd0 , block average threshold (>=), for flat block detection. unsigned , default = 160
+//Bit 7: 0, reg_dnr_dm_avgthd1 , block average threshold (<=), for flat block detection. unsigned , default = 128
+#define DNR_DM_AVG_VAR_DIF_THD ((0x2d6a << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_dnr_dm_avgdifthd , block average dif threshold (<) between cur and up block, for flat block detection. unsigned , default = 12
+//Bit 7: 0, reg_dnr_dm_vardifthd , block variance dif threshold (>=) between cur and up block, for flat block detection. unsigned , default = 1
+#define DNR_DM_VAR_EDGE_DIF_THD2 ((0x2d6b << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_dnr_dm_varthd2 , block variance threshold (>=), for edge block detection. unsigned , default = 24
+//Bit 15: 8, reg_dnr_dm_edgethd2 , block edge threshold (>=), for edge block detection. unsigned , default = 40
+//Bit 7: 0, reg_dnr_dm_difthd2 , block dif threshold (>=), for edge block detection. unsigned , default = 80
+#define DNR_DM_DIF_FLT_MISC ((0x2d6c << 2) + 0xff000000)
+//Bit 31:28, reg_dnr_dm_ldifoob , pre-defined large dif when pixel out of blocks. unsigned , default = 0
+//Bit 27:24, reg_dnr_dm_bdifoob , pre-defined block dif when pixel out of blocks;. unsigned , default = 0
+//Bit 23:16, reg_dnr_dm_fltalp , pre-defined alpha for dm and nr blending, when block is flat with mos.. unsigned , default = 200
+//Bit 15:12, reserved
+//Bit 11: 8, reg_dnr_dm_fltminbdif , pre-defined min block dif for dm filter, when block is flat with mos.. unsigned , default = 12
+//Bit 7, reserved
+//Bit 6: 2, reg_dnr_dm_difnormgain , gain for pixel dif normalization for dm filter, normalized 16 as "1". unsigned , default = 16
+//Bit 1, reg_dnr_dm_difnormen , enable pixel dif normalization for dm filter. unsigned , default = 1
+//Bit 0, reg_dnr_dm_difupden , enable block dif update using max of left, cur, right difs. unsigned , default = 0
+#define DNR_DM_SDIF_LUT0_2 ((0x2d6d << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_sdiflut0 , normally 0-16 . unsigned , default = 16
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_sdiflut1 , normally 0-16 . unsigned , default = 14
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_sdiflut2 , normally 0-16 . unsigned , default = 13
+#define DNR_DM_SDIF_LUT3_5 ((0x2d6e << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_sdiflut3 , normally 0-16 . unsigned , default = 10
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_sdiflut4 , normally 0-16 . unsigned , default = 7
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_sdiflut5 , normally 0-16 . unsigned , default = 5
+#define DNR_DM_SDIF_LUT6_8 ((0x2d6f << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_sdiflut6 , normally 0-16 . unsigned , default = 3
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_sdiflut7 , normally 0-16 . unsigned , default = 1
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_sdiflut8 , normally 0-16 . unsigned , default = 0
+#define DNR_DM_LDIF_LUT0_2 ((0x2d70 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_ldiflut0 , normally 0-16 . unsigned , default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_ldiflut1 , normally 0-16 . unsigned , default = 4
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_ldiflut2 , normally 0-16 . unsigned , default = 12
+#define DNR_DM_LDIF_LUT3_5 ((0x2d71 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_ldiflut3 , normally 0-16 . unsigned , default = 14
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_ldiflut4 , normally 0-16 . unsigned , default = 15
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_ldiflut5 , normally 0-16 . unsigned , default = 16
+#define DNR_DM_LDIF_LUT6_8 ((0x2d72 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_ldiflut6 , normally 0-16 . unsigned , default = 16
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_ldiflut7 , normally 0-16 . unsigned , default = 16
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_ldiflut8 , normally 0-16 . unsigned , default = 16
+#define DNR_DM_DIF2NORM_LUT0_2 ((0x2d73 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_dif2normlut0 , normally 0-16 . unsigned , default = 16
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_dif2normlut1 , normally 0-16 . unsigned , default = 5
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_dif2normlut2 , normally 0-16 . unsigned , default = 3
+#define DNR_DM_DIF2NORM_LUT3_5 ((0x2d74 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_dif2normlut3 , normally 0-16 . unsigned , default = 2
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_dif2normlut4 , normally 0-16 . unsigned , default = 2
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_dif2normlut5 , normally 0-16 . unsigned , default = 1
+#define DNR_DM_DIF2NORM_LUT6_8 ((0x2d75 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_dif2normlut6 , normally 0-16 . unsigned , default = 1
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_dif2normlut7 , normally 0-16 . unsigned , default = 1
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_dif2normlut8 , normally 0-16 . unsigned , default = 1
+#define DNR_DM_GMS_THD ((0x2d76 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_gms_stat_thd0 . unsigned , default = 0
+//Bit 7: 0, reg_gms_stat_thd1 . unsigned , default = 128
+#define DNR_RO_DM_GMS_STAT_CNT ((0x2d77 << 2) + 0xff000000)
+//Bit 31: 0, ro_dm_gms_stat_cnt . unsigned , default = 0
+#define DNR_RO_DM_GMS_STAT_MS ((0x2d78 << 2) + 0xff000000)
+//Bit 31: 0, ro_dm_gms_stat_ms . unsigned , default = 0
+#define DNR_DM_EDGE_GAIN ((0x2d79 << 2) + 0xff000000)
+//Bit 31:24 reg_dnr_dm_alpedgegain0 // unsigned , default = 8 , edge based gain for alpha, normalized 16 as "1"
+//Bit 23:16 reg_dnr_dm_alpedgegain1 // unsigned , default = 16 , edge based gain for alpha, normalized 16 as "1"
+//Bit 15: 8 reg_dnr_dm_alpedgegain2 // unsigned , default = 24 , edge based gain for alpha, normalized 16 as "1"
+//Bit 7: 0 reg_dnr_dm_alpedgegain3 // unsigned , default = 32 , edge based gain for alpha, normalized 16 as "1"
+#define DNR_DM_FLG_BDIF ((0x2d7a << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:24 reg_dnr_dm_flg2bdif0 // unsigned , default = 0 , (0-16), edge flg to blkdif calc.
+//Bit 23:21 reserved
+//Bit 20:16 reg_dnr_dm_flg2bdif1 // unsigned , default = 6 , (0-16), edge flg to blkdif calc.
+//Bit 15:13 reserved
+//Bit 12: 8 reg_dnr_dm_flg2bdif2 // unsigned , default = 10 , (0-16), edge flg to blkdif calc.
+//Bit 7: 5 reserved
+//Bit 4: 0 reg_dnr_dm_flg2bdif3 // unsigned , default = 12 , (0-16), edge flg to blkdif calc.
+#define DNR_DM_GBS_RORM ((0x2d7b << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15:12 reg_dnr_dm_gbs4difnorm0 // unsigned , default = 0 , gbs=0 for dif norm calc.
+//Bit 11: 8 reg_dnr_dm_gbs4difnorm1 // unsigned , default = 1 , gbs=1 for dif norm calc.
+//Bit 7: 4 reg_dnr_dm_gbs4difnorm2 // unsigned , default = 4 , gbs=2 for dif norm calc.
+//Bit 3: 0 reg_dnr_dm_gbs4difnorm3 // unsigned , default = 6 , gbs=3 for dif norm calc.
+#define DNR_DM_FLG_LEV ((0x2d7c << 2) + 0xff000000)
+//Bit 31:14 reserved
+//Bit 13:12 reg_dnr_dm_flg2lev0 // unsigned , default = 1 , edge flg to filter level calc.
+//Bit 11:10 reserved
+//Bit 9: 8 reg_dnr_dm_flg2lev1 // unsigned , default = 3 , edge flg to filter level calc.
+//Bit 7: 6 reserved
+//Bit 5: 4 reg_dnr_dm_flg2lev2 // unsigned , default = 3 , edge flg to filter level calc.
+//Bit 3: 2 reserved
+//Bit 1: 0 reg_dnr_dm_flg2lev3 // unsigned , default = 3 , edge flg to filter level calc.
+#define DNR_DM_DIF_FLG_TH ((0x2d7d << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_dnr_dm_dif2flgthd1 // unsigned , default = 128 , dif to edge flg threshold 1
+//Bit 7: 0 reg_dnr_dm_dif2flgthd2 // unsigned , default = 192 , dif to edge flg threshold 2
+#define DNR_DM_CALP_GAIN_OFST ((0x2d7e << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:16 reg_dnr_dm_calpgain // unsigned , default = 16 , chroma gain for nr/dm alpha, normalized 32 as "1"
+//Bit 15: 9 reserved
+//Bit 8: 0 reg_dnr_dm_calpoffst // signed , default = -64 , (-255, 255), chroma offset for nr/dm alpha
+// 0x80-0x90
+//
+// Reading file: vpu_decomb_regs.h
+//
+ // defined registers
+#define DECOMB_DET_VERT_CON0 ((0x2d80 << 2) + 0xff000000)
+//Bit 31:24 reg_di_dcmb_det_vcon_thd0 default = 60 // u8
+//Bit 23:16 reg_di_dcmb_det_vcon_thd1 default = 80 // u8
+//Bit 15: 8 reg_di_dcmb_det_valp_lmt0 default = 63 // u8
+//Bit 7: 0 reg_di_dcmb_det_valp_lmt1 default = 4 // u8
+#define DECOMB_DET_VERT_CON1 ((0x2d81 << 2) + 0xff000000)
+//Bit 23:16 reg_di_dcmb_det_valp_lmt2 default = 0 // u8
+//Bit 15: 8 reg_di_dcmb_det_vrate0 default = 32 // u8
+//Bit 7: 0 reg_di_dcmb_det_vrate1 default = 4 // u8
+#define DECOMB_DET_EDGE_CON0 ((0x2d82 << 2) + 0xff000000)
+//Bit 31:24 reg_di_dcmb_det_econ_thd0 default = 60 // u8
+//Bit 23:16 reg_di_dcmb_det_econ_thd1 default = 80 // u8
+//Bit 15: 8 reg_di_dcmb_det_ealp_lmt0 default = 63 // u8
+//Bit 7: 0 reg_di_dcmb_det_ealp_lmt1 default = 4 // u8
+#define DECOMB_DET_EDGE_CON1 ((0x2d83 << 2) + 0xff000000)
+//Bit 23:16 reg_di_dcmb_det_ealp_lmt2 default = 0 // u8
+//Bit 15: 8 reg_di_dcmb_det_erate0 default = 32 // u8
+//Bit 7: 0 reg_di_dcmb_det_erate1 default = 4 // u8
+#define DECOMB_PARA ((0x2d84 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:28 reg_di_dcmb_cmb_lpf default = 1 // u2, 0:no lpf, 1:[1 2 1], 2,3: [1 2 2 2 1]
+//Bit 27:26 reg_di_dcmb_vedge_chk default = 0 // u2, vertical edge check, 0: no check, 1: vrt!=0, 2: vrt==3
+//Bit 25:24 reg_di_dcmb_nedge_chk default = 0 // u2, no idea edge check, 0, no check, 1, check
+//Bit 23:20 reg_di_dcmb_edge_min default = 0 // u4, min edge for edge cmb
+//Bit 19:16 reg_di_dcmb_edge_max default = 15 // u4, min edge for edge cmb
+//Bit 15:8 reg_di_dcmb_bld_alp default = 255 // u8, user defined alpha for di & decmb blend
+//Bit 7:0 reg_di_dcmb_bld_alp_beta default = 40 // u8, beta for mtn & cmb blend, for bld alpha calc.
+#define DECOMB_BLND_CON0 ((0x2d85 << 2) + 0xff000000)
+//Bit 31:24 reg_di_dcmb_bld_con_thd0 default = 100 // u8
+//Bit 23:16 reg_di_dcmb_bld_con_thd1 default = 120 // u8
+//Bit 15: 8 reg_di_dcmb_bld_alp_lmt0 default = 0 // u8
+//Bit 7: 0 reg_di_dcmb_bld_alp_lmt1 default = 128 // u8
+#define DECOMB_BLND_CON1 ((0x2d86 << 2) + 0xff000000)
+//Bit 23:16 reg_di_dcmb_bld_alp_lmt2 default = 255 // u8
+//Bit 15: 8 reg_di_dcmb_bld_rate0 default = 32 // u8
+//Bit 7: 0 reg_di_dcmb_bld_rate1 default = 32 // u8
+#define DECOMB_YC_THRD ((0x2d87 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_di_dcmb_ythd default = 2 // u8, default = 2
+//Bit 7: 0 reg_di_dcmb_cthd default = 2 // u8, default = 2
+#define DECOMB_MTN_GAIN_OFST ((0x2d88 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:16 reg_di_dcmb_mtn_alp_gain default = 16 // u6, 16 is normalized to '1'
+//Bit 15:9 reserved
+//Bit 8:0 reg_di_dcmb_mtn_alp_ofst default = 0 // s9, [-256, 255]
+#define DECOMB_CMB_SEL_GAIN_OFST ((0x2d89 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:16 reg_di_dcmb_cmb_sel_gain default = 48 // u6, 16 is normalized to '1'
+//Bit 15:9 reserved
+//Bit 8:0 reg_di_dcmb_cmb_sel_ofst default = 0 // s9, [-256, 255]
+#define DECOMB_WIND00 ((0x2d8a << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_di_dcmb_wnd00 default = 0 // u13, x0 for window 0, software control
+//Bit 15:13 reserved
+//Bit 12:0 reg_di_dcmb_wnd01 default = 719 // u13, x1 for window 0, HSIZE-1, software control
+#define DECOMB_WIND01 ((0x2d8b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_di_dcmb_wnd02 default = 0 // u13, y0 for window 0, software control
+//Bit 15:13 reserved
+//Bit 12:0 reg_di_dcmb_wnd03 default = 39 // u13, y1 for window 0, software control
+#define DECOMB_WIND10 ((0x2d8c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_di_dcmb_wnd10 default = 0 // u13, x0 for window 1, software control
+//Bit 15:13 reserved
+//Bit 12:0 reg_di_dcmb_wnd11 default = 719 // u13, x1 for window 1, HSIZE-1, software control
+#define DECOMB_WIND11 ((0x2d8d << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_di_dcmb_wnd12 default = 40 // u13, y0 for window 1, software control
+//Bit 15:13 reserved
+//Bit 12:0 reg_di_dcmb_wnd13 default = 239 // u13, y1 for window 1, VSIZE-1-40, software control
+#define DECOMB_MODE ((0x2d8e << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reg_di_dcmb_is_cmb_bef default = 1 // u1, 1: decide is_cmb before cmbing refine, 0: decide is_cmb after cmbing refine
+//Bit 14 reg_di_dcmb_en0 default = 1 // u1, enable decmobing for wind0
+//Bit 13 reg_di_dcmb_en1 default = 1 // u1, enable decmobing for wind1
+//Bit 12 reg_di_dcmb_en2 default = 1 // u1, enable decmobing for wind2
+//Bit 11:10 reg_di_dcmb_lpf_mod0 default = 2 // u2, get combing free pixels of wind0 by: 0, vertical lpf, 1, edge lpf, 2,3, ei data
+//Bit 9:8 reg_di_dcmb_lpf_mod1 default = 2 // u2, get combing free pixels of wind1 by: 0, vertical lpf, 1, edge lpf, 2,3, ei data
+//Bit 7:6 reg_di_dcmb_lpf_mod2 default = 0 // u2, get combing free pixels of wind2 by: 0, vertical lpf, 1, edge lpf, 2,3, ei data
+//Bit 5 reg_di_dcmb_cmb_sel0 default = 1 // u1, wind0 decmb based on: 0, vert cmb, 1, edge cmb
+//Bit 4 reg_di_dcmb_cmb_sel1 default = 1 // u1, wind1 decmb based on: 0, vert cmb, 1, edge cmb
+//Bit 3 reg_di_dcmb_cmb_sel2 default = 0 // u1, wind2 decmb based on: 0, vert cmb, 1, edge cmb
+//Bit 2 reg_di_dcmb_alp_mod0 default = 1 // u1, wind0 decmb alpha based on: 0, user-defined, 1, motion adaptive
+//Bit 1 reg_di_dcmb_alp_mod1 default = 1 // u1, wind1 decmb alpha based on: 0, user-defined, 1, motion adaptive
+//Bit 0 reg_di_dcmb_alp_mod2 default = 1 // u1, wind2 decmb alpha based on: 0, user-defined, 1, motion adaptive
+#define DECOMB_FRM_SIZE ((0x2d8f << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 hsize_in default = 1920 // u13, pic horz size in unit: pixel
+//Bit 15:13 reserved
+//Bit 12:0 vsize_in default = 1080 // u13, pic vert size in unit: pixel
+#define DECOMB_HV_BLANK ((0x2d90 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15:8 hblank_num default = 20 // u8, hor blank time
+//Bit 7:0 vblank_num default = 50 // u8, ver blank time
+//
+// Closing file: vpu_decomb_regs.h
+//
+// 0x98-0xa3
+//
+// Reading file: vpu_nr2_dpolar_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define NR2_POLAR3_MODE ((0x2d98 << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:18 reg_polar3_f02lpf_mod0 // unsigned , default = 3 low pass filter mode for field 0 and field2 before polar3 detection; 0 for no lpf, 1: [1 2 1]/4 vert lpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 no hlpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 [1 2 1]/4 hlpf
+//Bit 17:16 reg_polar3_f02lpf_mod1 // unsigned , default = 3 low pass filter mode for field 0 and field2 before polar3 detection; 0 for no lpf, 1: [1 2 1]/4 vert lpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 no hlpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 [1 2 1]/4 hlpf
+//Bit 15: 8 reg_polar3_dif02_thrd0 // unsigned , default = 5 threshold of dif for polar3 detection except for 32 detection, only do polar3 detection on obvious motion, [0] for luma, 1[1] for chroma
+//Bit 7: 0 reg_polar3_dif02_thrd1 // unsigned , default = 5 threshold of dif for polar3 detection except for 32 detection, only do polar3 detection on obvious motion, [0] for luma, 1[1] for chroma
+#define NR2_POLAR3_THRD ((0x2d99 << 2) + 0xff000000)
+//Bit 31:24 reg_polar3_txtf02_thrd0 // unsigned , default = 30 threshold to vertical f0f2 texture, if texture larger than this threshold, will not do the polar3 decision.
+//Bit 23:16 reg_polar3_txtf02_thrd1 // unsigned , default = 30 threshold to vertical f0f2 texture, if texture larger than this threshold, will not do the polar3 decision.
+//Bit 15: 8 reg_polar3_txtf1_thrd0 // unsigned , default = 20 threshold to vertical f1 texture, if texture larger than this threshold, will not do the polar3 decision.
+//Bit 7: 0 reg_polar3_txtf1_thrd1 // unsigned , default = 20 threshold to vertical f1 texture, if texture larger than this threshold, will not do the polar3 decision.
+#define NR2_POLAR3_PARA0 ((0x2d9a << 2) + 0xff000000)
+//Bit 31:28 reg_polar3_rate00 // unsigned , default = 6 delt = rate*dif02/32, e.g. f2<f0, if f1 within((f0+f2)/2 - delt), ((f0+f2)/2 + delt), then polar3_smoothmv++;
+//Bit 27:24 reg_polar3_rate01 // unsigned , default = 6 delt = rate*dif02/32, e.g. f2<f0, if f1 within((f0+f2)/2 - delt), ((f0+f2)/2 + delt), then polar3_smoothmv++;
+//Bit 23:20 reg_polar3_rate10 // unsigned , default = 8 delt = rate*dif02/32, e.g. f2-ofst1<f0, if f1<((f0+f2)/2 - delt), then polar3_m1++; if f1>((f0+f2)/2 + delt), then polar3_p1++;
+//Bit 19:16 reg_polar3_rate11 // unsigned , default = 8 delt = rate*dif02/32, e.g. f2-ofst1<f0, if f1<((f0+f2)/2 - delt), then polar3_m1++; if f1>((f0+f2)/2 + delt), then polar3_p1++;
+//Bit 15:12 reg_polar3_rate20 // unsigned , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset2), then polar3_m2++; if f1>((f0 + delt+ ofset2), then polar3_p2++;
+//Bit 11: 8 reg_polar3_rate21 // unsigned , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset2), then polar3_m2++; if f1>((f0 + delt+ ofset2), then polar3_p2++;
+//Bit 7: 1 reserved
+//Bit 0 reg_polar3_ro_reset // unsigned , default = 0 reset signal of the polar3 read only registers
+#define NR2_POLAR3_PARA1 ((0x2d9b << 2) + 0xff000000)
+//Bit 31:24 reg_polar3_rate30 // unsigned , default = 48 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset3) or f1>((f0 + delt+ofst3), then polar3_32++;
+//Bit 23:16 reg_polar3_rate31 // unsigned , default = 48 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset3) or f1>((f0 + delt+ofst3), then polar3_32++;
+//Bit 15:12 reg_polar3_ofst30 // signed , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt-ofst3) or f1>((f0 + delt+ofst3), then polar3_32++;
+//Bit 11: 8 reg_polar3_ofst31 // signed , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt-ofst3) or f1>((f0 + delt+ofst3), then polar3_32++;
+//Bit 7: 4 reg_polar3_ofst20 // signed , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset2), then polar3_m2++; if f1>((f0 + delt+ ofset2), then polar3_p2++;
+//Bit 3: 0 reg_polar3_ofst21 // signed , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset2), then polar3_m2++; if f1>((f0 + delt+ ofset2), then polar3_p2++;
+#define NR2_POLAR3_CTRL ((0x2d9c << 2) + 0xff000000)
+//Bit 31:24 reg_polar3_ofst10 // signed , default = 1
+//Bit 23:16 reg_polar3_ofst11 // signed , default = 1
+//Bit 15: 8 reg_polar3_h_mute // unsigned , default = 10 horizontal pixels to mute for left right sides for polar3 detection;
+//Bit 7: 0 reg_polar3_v_mute // unsigned , default = 10 vertical pixels to mute for top and bottom sides for polar3 detection;
+#define NR2_RO_POLAR3_NUMOFPIX ((0x2d9d << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_numofpix // unsigned , default = 0 number of pixels detected as polar3
+#define NR2_RO_POLAR3_SMOOTHMV ((0x2d9e << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_smoothmv // unsigned , default = 0 number of pixels with smooth mv, F(t) is close between avg of f(t-1) and f(t+1);
+#define NR2_RO_POLAR3_M1 ((0x2d9f << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_m1 // unsigned , default = 0 number of pixels with F(t) is close to f(t-1) instead of f(t+1), but in between [f(t-1), f(t+1)];
+#define NR2_RO_POLAR3_P1 ((0x2da0 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_p1 // unsigned , default = 0 number of pixels with F(t) is close to f(t+1) instead of f(t-1), but in between [f(t-1), f(t+1)];
+#define NR2_RO_POLAR3_M2 ((0x2da1 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_m2 // unsigned , default = 0 number of pixels with F(t) is close to f(t-1) instead of f(t+1), but out side of (f(t-1), f(t+1));
+#define NR2_RO_POLAR3_P2 ((0x2da2 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_p2 // unsigned , default = 0 number of pixels with F(t) is close to f(t+1) instead of f(t-1), but out side of (f(t-1), f(t+1));
+#define NR2_RO_POLAR3_32 ((0x2da3 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_32 // unsigned , default = 0 number of pixels with F(t) far from [f(t-1),f(t+1)] and f(t-1) is close to f(t+1);
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_nr2_dpolar_regs.h
+//
+// 0xa4-0xf7 / 0xff
+//
+// Reading file: vpu_nr4_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//========== nr4_drt_regs register begin ==========//
+#define NR4_DRT_CTRL ((0x2da4 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_ydrt_3line_ssd_gain // unsigned , default = 16 gain to max ssd normalized 16 as '1'
+//Bit 23:16 reg_nr4_ydrt_5line_ssd_gain // unsigned , default = 16 gain to max ssd normalized 16 as '1'
+//Bit 15 reserved
+//Bit 14:13 reg_nr4_drt_yhsad_mode // unsigned , default = 1 mode for luma horiztonal sad calc., 0: no vertical lpf, 1: vertical [1 2 1], 2 or 3: vertical [ 1 2 2 2 1] if 5 lines
+//Bit 12:11 reg_nr4_drt_chsad_mode // unsigned , default = 1 mode for chroma horiztonal sad calc., 0: no vertical lpf, 1: vertical [1 2 1], 2 or 3: vertical [ 1 2 2 2 1] if 5 lines
+//Bit 10 reg_nr4_drt_yhsad_hlpf // unsigned , default = 1 hlpf for luma hsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf
+//Bit 9 reg_nr4_drt_yvsad_hlpf // unsigned , default = 1 hlpf for luma vsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf
+//Bit 8 reg_nr4_drt_ydsad_hlpf // unsigned , default = 1 hlpf for luma dsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf
+//Bit 7 reg_nr4_drt_chsad_hlpf // unsigned , default = 1 hlpf for chrome hsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf
+//Bit 6 reg_nr4_drt_cvsad_hlpf // unsigned , default = 1 hlpf for chroma vsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf
+//Bit 5 reg_nr4_drt_cdsad_hlpf // unsigned , default = 1 hlpf for chroma dsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf
+//Bit 4 reg_nr4_ydrt_dif_mode // unsigned , default = 1 0:y_dif, 1: y_dif + (u_dif + v_dif)/2
+//Bit 3: 2 reg_nr4_cdrt_dif_mode // unsigned , default = 2 0:(u_dif + v_dif), 1: y_dif/4 + (u_dif + v_dif)*3/4, 2:y_dif/2 + (u_dif + v_dif)/2, 3: y_dif (not recommended)
+//Bit 1: 0 reserved
+#define NR4_DRT_YSAD_GAIN ((0x2da5 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_ysad_hrz_gain // unsigned , default = 16 gain for horizontal sad, 16 normalized to "1"
+//Bit 23:16 reg_nr4_ysad_diag_gain // unsigned , default = 20 gain for diagonal sad, 16 normalized to "1"
+//Bit 15: 8 reg_nr4_ysad_vrt_gain // unsigned , default = 16 gain for vertical sad, 16 normalized to "1"
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_drt_ysad_core_rate // unsigned , default = 6 rate of coring for sad(theta) - sad(theta+pi/2)*rate/64
+#define NR4_DRT_CSAD_GAIN ((0x2da6 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_csad_hrz_gain // unsigned , default = 16 gain for horizontal sad, 16 normalized to "1"
+//Bit 23:16 reg_nr4_csad_diag_gain // unsigned , default = 20 gain for diagonal sad, 16 normalized to "1"
+//Bit 15: 8 reg_nr4_csad_vrt_gain // unsigned , default = 16 gain for vertical sad, 16 normalized to "1"
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_drt_csad_core_rate // unsigned , default = 6 rate of coring for sad(theta) - sad(theta+pi/2)*rate/64
+#define NR4_DRT_SAD_ALP_CORE ((0x2da7 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:20 reg_nr4_ydrt_alp_core_rate // unsigned , default = 0 luma ratio to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 0/32
+//Bit 19:16 reg_nr4_cdrt_alp_core_rate // unsigned , default = 0 chroma ratio to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 0/32
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_ydrt_alp_core_ofst // unsigned , default = 10 luma offset to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 10
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_cdrt_alp_core_ofst // unsigned , default = 10 chroma offset to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 10
+#define NR4_DRT_ALP_MINMAX ((0x2da8 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_ydrt_alp_min // unsigned , default = 0 luma min value of alpha, dft = 0
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_ydrt_alp_max // unsigned , default = 63 luma max value of alpha, dft = 63
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_cdrt_alp_min // unsigned , default = 0 chroma min value of alpha, dft = 0
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_cdrt_alp_max // unsigned , default = 63 chroma max value of alpha, dft = 63
+//========== nr4_drt_regs register end ==========//
+//========== nr4_snr_regs register begin ==========//
+#define NR4_SNR_CTRL_REG ((0x2da9 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12 reg_nr4_bet2_sel // unsigned , default = 1
+//Bit 11: 9 reg_nr4_snr2_sel_mode // unsigned , default = 0 0: no filter, 1: adpgau, adp_drt_lpf blend; 2: adpgau, drt4_lpf blend; 3: adp_drt_lpf method, 4: drt4_lpf method, 5: adp_drt_ //original image blend, 6: drt4_lpf, original image blend, 7: adpgau method; dft=1
+//Bit 8 reg_nr4_snr2_gaulpf_mode // unsigned , default = 1 0: 3*5 or 5*5 gaussian lpf; 1: 3*3 (window size) gaussian lpf; dft=1
+//Bit 7: 6 reg_nr4_snr2_alpha0_sad_mode // unsigned , default = 3 0: max_sad*max_ssd; 1: max_sad*max_sad; 2: adp_max_sad*max_ssd; 3: adp_max_sad*adp_max_sad dft=3
+//Bit 5: 4 reg_nr4_snr2_alpha1_sad_mode // unsigned , default = 2 0: max_sad; 1: cross_max_sad; 2 or 3: adp_sad dft=2
+//Bit 3: 2 reserved
+//Bit 1: 0 reg_nr4_snr2_adp_drtlpf_mode // unsigned , default = 3 0: adp_drtlpf [2 1 1]/4, 1: adp_drtlpf [4 2 1 1]/8; 2: adp_drtlpf [2 2 2 1 1]/8; 3: adp_drtlpf [7 7 7 6 5]/32; dft=3;
+#define NR4_SNR_ALPHA0_MAX_MIN ((0x2daa << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:23 reg_nr4_snr2_alp0_ymin // unsigned , default = 127 normalized to 128 as '1'
+//Bit 22:16 reg_nr4_snr2_alp0_ymax // unsigned , default = 127 normalized to 128 as '1'
+//Bit 15:14 reserved
+//Bit 13: 7 reg_nr4_snr2_alp0_cmin // unsigned , default = 127 normalized to 128 as '1'
+//Bit 6: 0 reg_nr4_snr2_alp0_cmax // unsigned , default = 127 normalized to 128 as '1'
+#define NR4_ALP0C_ERR2CURV_LIMIT0 ((0x2dab << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_snr2_alp0_minerr_cpar0 // unsigned , default = 0 threshold0 of curve to map mierr to alp0 for chroma channel, this will be set value of flat region mierr that no need blur.
+//Bit 23:16 reg_nr4_snr2_alp0_minerr_cpar1 // unsigned , default = 25 threshold1 of curve to map mierr to alp0 for chroma channel,this will be set value of texture region mierr that can not blur.
+//Bit 15: 8 reg_nr4_snr2_alp0_minerr_cpar5 // unsigned , default = 40 rate0 (for mierr<th0) of curve to map mierr to alp0 for chroma channel. the larger of the value, the deep of the slope. 0~255.
+//Bit 7: 0 reg_nr4_snr2_alp0_minerr_cpar6 // unsigned , default = 40 rate1 (for mierr>th1) of curve to map mierr to alp0 for chroma channel. the larger of the value, the deep of the slope. 0~255.
+#define NR4_ALP0C_ERR2CURV_LIMIT1 ((0x2dac << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_snr2_alp0_minerr_cpar2 // unsigned , default = 127 level limit(for mierr<th0) of curve to map mierr to alp0 for chroma channel, that we can do for flat region. 0~255.
+//Bit 15: 8 reg_nr4_snr2_alp0_minerr_cpar3 // unsigned , default = 0 level limit(for th0<mierr<th1) of curve to map mierr to alp0 for chroma channel, that we can do for misc region. 0~255.
+//Bit 7: 0 reg_nr4_snr2_alp0_minerr_cpar4 // unsigned , default = 127 level limit(for mierr>th1) of curve to map mierr to alp0 for chroma channel, that we can do for texture region. 0~255.
+#define NR4_ALP0Y_ERR2CURV_LIMIT0 ((0x2dad << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_snr2_alp0_minerr_ypar0 // unsigned , default = 0 threshold0 of curve to map mierr to alp0 for luma channel, this will be set value of flat region mierr that no need blur. 0~255.
+//Bit 23:16 reg_nr4_snr2_alp0_minerr_ypar1 // unsigned , default = 25 threshold1 of curve to map mierr to alp0 for luma channel,this will be set value of texture region mierr that can not blur.
+//Bit 15: 8 reg_nr4_snr2_alp0_minerr_ypar5 // unsigned , default = 40 rate0 (for mierr<th0) of curve to map mierr to alp0 for luma channel. the larger of the value, the deep of the slope. 0~255.
+//Bit 7: 0 reg_nr4_snr2_alp0_minerr_ypar6 // unsigned , default = 40 rate1 (for mierr>th1) of curve to map mierr to alp0 for luma channel. the larger of the value, the deep of the slope. 0~255.
+#define NR4_ALP0Y_ERR2CURV_LIMIT1 ((0x2dae << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_snr2_alp0_minerr_ypar2 // unsigned , default = 127 level limit(for mierr<th0) of curve to map mierr to alp0 for luma channel, set to alp0 that we can do for flat region. 0~255.
+//Bit 15: 8 reg_nr4_snr2_alp0_minerr_ypar3 // unsigned , default = 0 level limit(for th0<mierr<th1) of curve to map mierr to alp0 for luma channel, alp0 that we can do for misc region. 0~255.
+//Bit 7: 0 reg_nr4_snr2_alp0_minerr_ypar4 // unsigned , default = 127 level limit(for mierr>th1) of curve to map mierr to alp0 for luma channel, alp0 that we can do for texture region. 0~255.
+#define NR4_SNR_ALPA1_RATE_AND_OFST ((0x2daf << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:18 reg_nr4_snr2_alp1_ycore_rate // unsigned , default = 0 normalized 64 as "1"
+//Bit 17:12 reg_nr4_snr2_alp1_ccore_rate // unsigned , default = 0 normalized 64 as "1"
+//Bit 11: 6 reg_nr4_snr2_alp1_ycore_ofst // signed , default = 3 normalized 64 as "1"
+//Bit 5: 0 reg_nr4_snr2_alp1_ccore_ofst // signed , default = 3 normalized 64 as "1"
+#define NR4_SNR_ALPHA1_MAX_MIN ((0x2db0 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:18 reg_nr4_snr2_alp1_ymin // unsigned , default = 0 normalized to 64 as '1'
+//Bit 17:12 reg_nr4_snr2_alp1_ymax // unsigned , default = 63 normalized to 64 as '1'
+//Bit 11: 6 reg_nr4_snr2_alp1_cmin // unsigned , default = 0 normalized to 64 as '1'
+//Bit 5: 0 reg_nr4_snr2_alp1_cmax // unsigned , default = 63 normalized to 64 as '1'
+#define NR4_ALP1C_ERR2CURV_LIMIT0 ((0x2db1 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_snr2_alp1_minerr_cpar0 // unsigned , default = 0 annel, this will be set value of flat region mierr that no need directional NR. 0~255.
+//Bit 23:16 reg_nr4_snr2_alp1_minerr_cpar1 // unsigned , default = 24 hannel,this will be set value of texture region mierr that can not do directional NR. 0~255.
+//Bit 15: 8 reg_nr4_snr2_alp1_minerr_cpar5 // unsigned , default = 0 a/chroma channel. the larger of the value, the deep of the slope.
+//Bit 7: 0 reg_nr4_snr2_alp1_minerr_cpar6 // unsigned , default = 20 a/chroma channel. the larger of the value, the deep of the slope. 0~255
+#define NR4_ALP1C_ERR2CURV_LIMIT1 ((0x2db2 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_snr2_alp1_minerr_cpar2 // unsigned , default = 0 will be set to alp1 that we can do for flat region. 0~255.
+//Bit 15: 8 reg_nr4_snr2_alp1_minerr_cpar3 // unsigned , default = 16 this will be set to alp1 that we can do for misc region. 0~255.
+//Bit 7: 0 reg_nr4_snr2_alp1_minerr_cpar4 // unsigned , default = 63 will be set to alp1 that we can do for texture region. 0~255.255 before
+#define NR4_ALP1Y_ERR2CURV_LIMIT0 ((0x2db3 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_snr2_alp1_minerr_ypar0 // unsigned , default = 0 thra/chroma channel, this will be set value of flat region mierr that no need directional NR. 0~255.
+//Bit 23:16 reg_nr4_snr2_alp1_minerr_ypar1 // unsigned , default = 24 thra/chroma channel,this will be set value of texture region mierr that can not do directional NR. 0~255.
+//Bit 15: 8 reg_nr4_snr2_alp1_minerr_ypar5 // unsigned , default = 0 ratlp1 for luma/chroma channel. the larger of the value, the deep of the slope.
+//Bit 7: 0 reg_nr4_snr2_alp1_minerr_ypar6 // unsigned , default = 20 ratlp1 for luma/chroma channel. the larger of the value, the deep of the slope. 0~255
+#define NR4_ALP1Y_ERR2CURV_LIMIT1 ((0x2db4 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_snr2_alp1_minerr_ypar2 // unsigned , default = 0 lev to alp1 for luma/chroma channel, this will be set to alp1 that we can do for flat region. 0~255.
+//Bit 15: 8 reg_nr4_snr2_alp1_minerr_ypar3 // unsigned , default = 16 levierr to alp1 for luma/chroma channel, this will be set to alp1 that we can do for misc region. 0~255.
+//Bit 7: 0 reg_nr4_snr2_alp1_minerr_ypar4 // unsigned , default = 63 lev to alp1 for luma/chroma channel, this will be set to alp1 that we can do for texture region. 0~255.255 before
+//========== nr4_snr_regs register end ==========//
+//========== nr4_tnr_regs register begin ==========//
+#define NR4_MTN_CTRL ((0x2db5 << 2) + 0xff000000)
+//Bit 31: 2 reserved
+//Bit 1 reg_nr4_mtn_ref_en // unsigned , default = 1 enable motion refinement, dft = 1
+//Bit 0 reg_nr4_mtn_ref_bet_sel // unsigned , default = 0 beta selection mode for motion refinement, 0: beta1, 1: beta2, dft = 0
+#define NR4_MTN_REF_PAR0 ((0x2db6 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_mtn_ref_par0 // unsigned , default = 24 par0 for beta to gain, dft =
+//Bit 23:16 reg_nr4_mtn_ref_par1 // unsigned , default = 60 par1 for beta to gain, dft =
+//Bit 15: 8 reg_nr4_mtn_ref_par2 // unsigned , default = 4 par2 for beta to gain, dft =
+//Bit 7: 0 reg_nr4_mtn_ref_par3 // unsigned , default = 32 par3 for beta to gain, dft =
+#define NR4_MTN_REF_PAR1 ((0x2db7 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_mtn_ref_par4 // unsigned , default = 128 par4 for beta to gain, dft =
+//Bit 15: 8 reg_nr4_mtn_ref_par5 // unsigned , default = 40 par5 for beta to gain, dft =
+//Bit 7: 0 reg_nr4_mtn_ref_par6 // unsigned , default = 20 par6 for beta to gain, dft =
+//========== nr4_tnr_regs register end ==========//
+//========== nr4_mcnr_regs register begin ==========//
+#define NR4_MCNR_LUMA_ENH_CTRL ((0x2db8 << 2) + 0xff000000)
+//Bit 31: 4 reserved
+//Bit 3 reg_nr4_luma_plus_en // unsigned , default = 1 enable luma enhancement, dft = 1
+//Bit 2 reg_nr4_luma_plus_wt_mode // unsigned , default = 1 luma weight calc mode, 0:sqrt(1+x^2), 1: 1+abs(x), dft = 0
+//Bit 1: 0 reg_nr4_luma_plus_orient_mode // unsigned , default = 1 0: only use previous orient for pre and cur luma plus, 1: 0: only use current orient for pre and cur luma plus
+#define NR4_MCNR_LUMA_STAT_LIMTX ((0x2db9 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_nr4_luma_plus_xst // unsigned , default = 8 start for luma plus statistic, dft = 8
+//Bit 15:14 reserved
+//Bit 13: 0 reg_nr4_luma_plus_xed // unsigned , default = 711 end for luma plus statistic, dft = HSIZE-8-1;
+#define NR4_MCNR_LUMA_STAT_LIMTY ((0x2dba << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_nr4_luma_plus_yst // unsigned , default = 8 start for luma plus statistic, dft = 8
+//Bit 15:14 reserved
+//Bit 13: 0 reg_nr4_luma_plus_yed // unsigned , default = 231 end for luma plus statistic, dft = VSIZE-8-1
+#define NR4_MCNR_LUMA_DIF_CALC ((0x2dbb << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_luma_plus_ugain // unsigned , default = 8 U's gain for luma enhancement, 16 normalized as '1'
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_luma_plus_vgain // unsigned , default = 8 V's gain for luma enhancement, 16 normalized as '1'
+//Bit 15: 8 reg_nr4_luma_plus_ycor_thd // unsigned , default = 2 Y coring threshold for difference calc., dft = 0
+//Bit 7: 0 reg_nr4_luma_plus_ccor_thd // unsigned , default = 0 C coring threshold for difference calc., dft = 0
+#define NR4_MCNR_LUMAPRE_CAL_PRAM ((0x2dbc << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_nr4_pre_u_orient // signed , default = 0 orientation of previous U, initial to 0, and will be updated by software
+//Bit 23:18 reserved
+//Bit 17:16 reg_nr4_pre_v_orient // signed , default = 0 orientation of previous V, initial to 0, and will be updated by software
+//Bit 15: 8 reg_nr4_pre_u_mean // unsigned , default = 0 mean of previous U, initial to 0, and will be updated by software
+//Bit 7: 0 reg_nr4_pre_v_mean // unsigned , default = 0 mean of previousV, initial to 0, and will be updated by software
+#define NR4_MCNR_LUMACUR_CAL_PRAM ((0x2dbd << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_nr4_cur_u_orient // signed , default = 0 orientation of current U, initial to 0, and will be updated by software
+//Bit 23:18 reserved
+//Bit 17:16 reg_nr4_cur_v_orient // signed , default = 0 orientation of current V, initial to 0, and will be updated by software
+//Bit 15: 8 reg_nr4_cur_u_mean // unsigned , default = 0 mean of current U, initial to 0, and will be updated by software
+//Bit 7: 0 reg_nr4_cur_v_mean // unsigned , default = 0 mean of current, initial to 0, and will be updated by software
+#define NR4_MCNR_MV_CTRL_REG ((0x2dbe << 2) + 0xff000000)
+//Bit 31:14 reserved
+//Bit 13:12 reg_nr4_sad_bitw // unsigned , default = 2 sad bit width (8 + x) before clip to u8, dft = 1
+//Bit 11: 4 reg_nr4_glb_gain // unsigned , default = 64 global gain calc. by software, 64 is normalized as '1'
+//Bit 3: 0 reg_nr4_mv_err_rsft // unsigned , default = 8 right shift for mv err calc., dft = 9
+#define NR4_MCNR_MV_GAIN0 ((0x2dbf << 2) + 0xff000000)
+//Bit 31:28 reg_nr4_lftmvx_gain // unsigned , default = 1 left mvx gain for err calc., dft = 1
+//Bit 27:24 reg_nr4_lftmvy_gain // unsigned , default = 1 left mvy gain for err calc., dft = 1
+//Bit 23:20 reg_nr4_zmvx_gain // unsigned , default = 5 zero mvx gain for err calc., dft = 2
+//Bit 19:16 reg_nr4_zmvy_gain // unsigned , default = 5 zero mvy gain for err calc., dft = 4
+//Bit 15:12 reg_nr4_lmvx0_gain // unsigned , default = 2 line mvx0 gain for err calc., dft = 1
+//Bit 11: 8 reg_nr4_lmvx1_gain // unsigned , default = 2 line mvx1 gain for err calc., dft = 1
+//Bit 7: 4 reg_nr4_lmvy0_gain // unsigned , default = 2 line mvy0 gain for err calc., dft = 1
+//Bit 3: 0 reg_nr4_lmvy1_gain // unsigned , default = 2 line mvy1 gain for err calc., dft = 1
+#define NR4_MCNR_LMV_PARM ((0x2dc0 << 2) + 0xff000000)
+//Bit 31:28 reg_nr4_lmv_rt0 // unsigned , default = 3 ratio of max lmv
+//Bit 27:24 reg_nr4_lmv_rt1 // unsigned , default = 3 ratio of second max lmv
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_lmv_num_lmt0 // unsigned , default = 16 lmv0 least/limit number of (total number - zero_bin)
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_lmv_num_lmt1 // unsigned , default = 8 lmv1 least/limit number of (total number - zero_bin - max0)
+//Bit 7: 2 reserved
+//Bit 1: 0 reg_nr4_max_sad_rng // unsigned , default = 1 search range of max2 sad in small region, dft = 1
+#define NR4_MCNR_ALP0_REG ((0x2dc1 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25 reg_nr4_alp0_fail_chk // unsigned , default = 1 enable check for alp0 fail status
+//Bit 24 reg_nr4_bet0_coef_ref_en // unsigned , default = 1 bet1 refinement by coef_blt
+//Bit 23:16 reg_nr4_alp0_posad_gain // unsigned , default = 255 the sad (norm) gain for pixel pointed by MV;
+//Bit 15:10 reserved
+//Bit 9: 8 reg_nr4_alp0_norm_mode // unsigned , default = 0 alp0 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_alp0_norm_gain // unsigned , default = 16 alp0 gain for sad norm, '32' as '1', dft = 1
+#define NR4_MCNR_ALP1_AND_BET0_REG ((0x2dc2 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_nr4_alp1_norm_mode // unsigned , default = 3 alp1 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_alp1_norm_gain // unsigned , default = 3 alp1 gain for sad norm, '32' as '1', dft = 1
+//Bit 15:10 reserved
+//Bit 9: 8 reg_nr4_bet0_norm_mode // unsigned , default = 3 bet0 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bet0_norm_gain // unsigned , default = 8 bet0 gain for sad norm, '32' as '1', dft = 1
+#define NR4_MCNR_BET1_AND_BET2_REG ((0x2dc3 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_nr4_bet1_norm_mode // unsigned , default = 3 bet1 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_bet1_norm_gain // unsigned , default = 8 bet1 gain for sad norm, '32' as '1', dft = 1
+//Bit 15:10 reserved
+//Bit 9: 8 reg_nr4_bet2_norm_mode // unsigned , default = 0 bet2 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bet2_norm_gain // unsigned , default = 16 bet2 gain for sad norm, '32' as '1', dft = 1
+#define NR4_MCNR_AC_DC_CRTL ((0x2dc4 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15:12 reserved
+//Bit 11 reg_nr4_dc_mode // unsigned , default = 1 mode for dc selection,0: Y_lpf, 1: Y_lpf + (U_Lpf+V_lpf)/2,
+//Bit 10 reg_nr4_ac_mode // unsigned , default = 1 mode for ac selection, 0: Y_abs_dif, 1: Y_abs_dif + (U_abs_dif + V_abs_dif)/2
+//Bit 9 reg_nr4_dc_sel // unsigned , default = 0 selection mode for dc value, 0: 3x5, 1: 5x5, dft = 1
+//Bit 8 reg_nr4_ac_sel // unsigned , default = 0 selection mode for ac value, 0: 3x5, 1: 5x5, dft = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_nr4_dc_shft // unsigned , default = 2 right shift for dc value, dft = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_nr4_ac_shft // unsigned , default = 0 right shift for ac value, dft = 2
+#define NR4_MCNR_CM_CTRL0 ((0x2dc5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28 reg_nr4_cm_skin_prc_bet0 // unsigned , default = 0 enable skin tone processing for mcnr bet0 calc., dft = 1
+//Bit 27:26 reg_nr4_cm_chrm_sel // unsigned , default = 1 chrome selection for color match, 0: 1x1, 1: 3X3LPF, 2: 3x5LPF, 3: 5x5LPF for 5lines, 3x5LPF for 3lines, dft = 3
+//Bit 25:24 reg_nr4_cm_luma_sel // unsigned , default = 1 luma selection for color match, 0: 1x1, 1: 3X3LPF, 2: 3x5LPF, 3: 5x5LPF for 5lines, 3x5LPF for 3lines, dft = 3
+//Bit 23:21 reg_nr4_cm_skin_rshft_bet0 // unsigned , default = 3 right shift for bet0's skin color gains, dft = 3
+//Bit 20 reg_nr4_cm_var_sel // unsigned , default = 1 variation selection for color match, 0: 3x5, 1: 5x5 for 5lines, 3x5 for 3lines, dft = 1
+//Bit 19 reg_nr4_cm_green_prc_bet0 // unsigned , default = 1 enable green processing for mcnr bet0 calc., dft = 1
+//Bit 18:16 reg_nr4_cm_green_rshft_bet0 // unsigned , default = 4 right shift for bet0's green color gains, dft = 4
+//Bit 15:14 reg_nr4_preflt_mod // unsigned , default = 2 pre filter mode in mcnr, 0: mv pointed pixel, 1: bilater filter
+//Bit 13:12 reg_nr4_alp1_mode // unsigned , default = 1 mode for alpha1's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad
+//Bit 11:10 reserved
+//Bit 9: 8 reg_nr4_bet0_mode // unsigned , default = 0 mode for bet0's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad, else: (co sad) - (min sad)
+//Bit 7: 6 reserved
+//Bit 5: 4 reg_nr4_bet1_mode // unsigned , default = 2 mode for bet1's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad, else: (co sad) - (min sad)
+//Bit 3: 2 reserved
+//Bit 1: 0 reg_nr4_bet2_mode // unsigned , default = 1 mode for bet2's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad, else: (co sad) - (min sad)
+#define NR4_MCNR_CM_PRAM ((0x2dc6 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29 reg_nr4_cm_blue_prc_alp0 // unsigned , default = 1 enable blue processing for mcnr alpha0 calc., dft = 1
+//Bit 28 reg_nr4_cm_blue_prc_alp1 // unsigned , default = 1 enable blue processing for mcnr alpha1 calc., dft = 1
+//Bit 27 reg_nr4_cm_skin_prc_alp0 // unsigned , default = 1 enable skin tone processing for mcnr alpha0 calc., dft = 1
+//Bit 26 reg_nr4_cm_green_prc_alp0 // unsigned , default = 1 enable green processing for mcnr alpha0 clac., dft = 1
+//Bit 25 reg_nr4_cm_skin_prc_alp1 // unsigned , default = 1 enable skin tone processing for mcnr alpha0 calc., dft = 1
+//Bit 24 reg_nr4_cm_green_prc_alp1 // unsigned , default = 1 enable green processing for mcnr alpha1 clac., dft = 1
+//Bit 23:20 reg_nr4_cm_blue_hue_st // unsigned , default = 13 hue start of blue, dft =
+//Bit 19:16 reg_nr4_cm_blue_hue_ed // unsigned , default = 15 hue end of blue, dft =
+//Bit 15:12 reg_nr4_cm_green_hue_st // unsigned , default = 7 hue start of green, dft =
+//Bit 11: 8 reg_nr4_cm_green_hue_ed // unsigned , default = 10 hue end of green, dft =
+//Bit 7: 4 reg_nr4_cm_skin_hue_st // unsigned , default = 5 hue start of skin, dft =
+//Bit 3: 0 reg_nr4_cm_skin_hue_ed // unsigned , default = 6 hue end of skin, dft =
+#define NR4_MCNR_CM_RSHFT_ALP0 ((0x2dc7 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:25 reg_nr4_cm_blue_rshft_bet0 // unsigned , default = 5 right shift for bet0's blue color gains, dft = 5
+//Bit 24 reg_nr4_cm_blue_prc_bet0 // unsigned , default = 1 enable blue processing for mcnr bet0 calc., dft = 1
+//Bit 23 reserved
+//Bit 22:20 reg_nr4_cm_blue_rshft_alp0 // unsigned , default = 5 right shift for alpha0/1's blue color gains, dft = 5
+//Bit 19 reserved
+//Bit 18:16 reg_nr4_cm_blue_rshft_alp1 // unsigned , default = 5 right shift for alpha0/1's blue color gains, dft = 5
+//Bit 15 reserved
+//Bit 14:12 reg_nr4_cm_green_rshft_alp0 // unsigned , default = 4 right shift for alpha0/1's green color gains, dft = 4
+//Bit 11 reserved
+//Bit 10: 8 reg_nr4_cm_green_rshft_alp1 // unsigned , default = 4 right shift for alpha0/1's green color gains, dft = 4
+//Bit 7 reserved
+//Bit 6: 4 reg_nr4_cm_skin_rshft_alp0 // unsigned , default = 3 right shift for alpha0/1's skin color gains, dft = 3
+//Bit 3 reserved
+//Bit 2: 0 reg_nr4_cm_skin_rshft_alp1 // unsigned , default = 3 right shift for alpha0/1's skin color gains, dft = 3
+#define NR4_MCNR_BLUE_CENT ((0x2dc8 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_blue_centx // unsigned , default = 157 x coordinate of center of blue, dft =
+//Bit 15: 8 reserved
+//Bit 7: 0 reg_nr4_cm_blue_centy // unsigned , default = 110 y coordinate of center of blue, dft =
+#define NR4_MCNR_BLUE_GAIN_PAR0 ((0x2dc9 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_cm_blue_gain_par0 // unsigned , default = 32 par0 for blue gain, dft =
+//Bit 23:16 reg_nr4_cm_blue_gain_par1 // unsigned , default = 255 par1 for blue gain, dft =
+//Bit 15: 8 reg_nr4_cm_blue_gain_par2 // unsigned , default = 4 par2 for blue gain, dft =
+//Bit 7: 0 reg_nr4_cm_blue_gain_par3 // unsigned , default = 32 par3 for blue gain, dft =
+#define NR4_MCNR_BLUE_GAIN_PAR1 ((0x2dca << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_blue_gain_par4 // unsigned , default = 32 par4 for blue gain, dft =
+//Bit 15: 8 reg_nr4_cm_blue_gain_par5 // unsigned , default = 32 par5 for blue gain, dft =
+//Bit 7: 0 reg_nr4_cm_blue_gain_par6 // unsigned , default = 0 par6 for blue gain, dft =
+#define NR4_MCNR_CM_BLUE_CLIP0 ((0x2dcb << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_blue_luma_min // unsigned , default = 40 luma min for blue color matching, dft =
+//Bit 15: 8 reserved
+//Bit 7: 0 reg_nr4_cm_blue_luma_max // unsigned , default = 180 luma max for blue color matching, dft =
+#define NR4_MCNR_CM_BLUE_CLIP1 ((0x2dcc << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_cm_blue_sat_min // unsigned , default = 5 saturation min for blue color matching, dft =
+//Bit 23:16 reg_nr4_cm_blue_sat_max // unsigned , default = 255 saturation max for blue color matching, dft =
+//Bit 15: 8 reg_nr4_cm_blue_var_min // unsigned , default = 0 variation min for blue color matching, dft =
+//Bit 7: 0 reg_nr4_cm_blue_var_max // unsigned , default = 12 variation max for blue color matching, dft =
+#define NR4_MCNR_GREEN_CENT ((0x2dcd << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_green_centx // unsigned , default = 114 x coordinate of center of green, dft =
+//Bit 15: 8 reserved
+//Bit 7: 0 reg_nr4_cm_green_centy // unsigned , default = 126 y coordinate of center of green, dft =
+#define NR4_MCNR_GREEN_GAIN_PAR0 ((0x2dce << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_cm_green_gain_par0 // unsigned , default = 16 par0 for green gain, dft =
+//Bit 23:16 reg_nr4_cm_green_gain_par1 // unsigned , default = 255 par1 for green gain, dft =
+//Bit 15: 8 reg_nr4_cm_green_gain_par2 // unsigned , default = 255 par2 for green gain, dft =
+//Bit 7: 0 reg_nr4_cm_green_gain_par3 // unsigned , default = 16 par3 for green gain, dft =
+#define NR4_MCNR_GREEN_GAIN_PAR1 ((0x2dcf << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_green_gain_par4 // unsigned , default = 16 par4 for green gain, dft =
+//Bit 15: 8 reg_nr4_cm_green_gain_par5 // unsigned , default = 128 par5 for green gain, dft =
+//Bit 7: 0 reg_nr4_cm_green_gain_par6 // unsigned , default = 0 par6 for green gain, dft =
+#define NR4_MCNR_GREEN_CLIP0 ((0x2dd0 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_green_luma_min // unsigned , default = 40 luma min for green color matching, dft =
+//Bit 15: 8 reserved
+//Bit 7: 0 reg_nr4_cm_green_luma_max // unsigned , default = 160 luma max for green color matching, dft =
+#define NR4_MCNR_GREEN_CLIP2 ((0x2dd1 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_cm_green_sat_min // unsigned , default = 4 saturation min for green color matching, dft =
+//Bit 23:16 reg_nr4_cm_green_sat_max // unsigned , default = 255 saturation max for green color matching, dft =
+//Bit 15: 8 reg_nr4_cm_green_var_min // unsigned , default = 0 variation min for green color matching, dft =
+//Bit 7: 0 reg_nr4_cm_green_var_max // unsigned , default = 12 variation max for green color matching, dft =
+#define NR4_MCNR_SKIN_CENT ((0x2dd2 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_skin_centx // unsigned , default = 112 x coordinate of center of skin tone, dft =
+//Bit 15: 8 reserved
+//Bit 7: 0 reg_nr4_cm_skin_centy // unsigned , default = 149 y coordinate of center of skin tone, dft =
+#define NR4_MCNR_SKIN_GAIN_PAR0 ((0x2dd3 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_cm_skin_gain_par0 // unsigned , default = 20 par0 for skin gain, dft =
+//Bit 23:16 reg_nr4_cm_skin_gain_par1 // unsigned , default = 255 par1 for skin gain, dft =
+//Bit 15: 8 reg_nr4_cm_skin_gain_par2 // unsigned , default = 255 par2 for skin gain, dft =
+//Bit 7: 0 reg_nr4_cm_skin_gain_par3 // unsigned , default = 8 par3 for skin gain, dft =
+#define NR4_MCNR_SKIN_GAIN_PAR1 ((0x2dd4 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_skin_gain_par4 // unsigned , default = 8 par4 for skin gain, dft =
+//Bit 15: 8 reg_nr4_cm_skin_gain_par5 // unsigned , default = 128 par5 for skin gain, dft =
+//Bit 7: 0 reg_nr4_cm_skin_gain_par6 // unsigned , default = 0 par6 for skin gain, dft =
+#define NR4_MCNR_SKIN_CLIP0 ((0x2dd5 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_skin_luma_min // unsigned , default = 40 luma min for skin color matching, dft =
+//Bit 15: 8 reserved
+//Bit 7: 0 reg_nr4_cm_skin_luma_max // unsigned , default = 180 luma max for skin color matching, dft =
+#define NR4_MCNR_SKIN_CLIP1 ((0x2dd6 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_cm_skin_sat_min // unsigned , default = 5 saturation min for skin color matching, dft =
+//Bit 23:16 reg_nr4_cm_skin_sat_max // unsigned , default = 255 saturation max for skin color matching, dft =
+//Bit 15: 8 reg_nr4_cm_skin_var_min // unsigned , default = 0 variation min for skin color matching, dft =
+//Bit 7: 0 reg_nr4_cm_skin_var_max // unsigned , default = 12 variation max for skin color matching, dft =
+#define NR4_MCNR_ALP1_GLB_CTRL ((0x2dd7 << 2) + 0xff000000)
+//Bit 31 reg_nr4_alp1_glb_gain_en // unsigned , default = 0 alp1 adjust by global gain, dft = 1
+//Bit 30:28 reg_nr4_alp1_glb_gain_lsft // unsigned , default = 6 alp1 left shift before combine with global gain
+//Bit 27 reg_nr4_bet0_glb_gain_en // unsigned , default = 1 bet0 adjust by global gain, dft = 1
+//Bit 26:24 reg_nr4_bet0_glb_gain_lsft // unsigned , default = 6 bet1 left shift before combine with global gain
+//Bit 23 reg_nr4_bet1_glb_gain_en // unsigned , default = 0 bet1 adjust by global gain, dft = 0
+//Bit 22:20 reg_nr4_bet1_glb_gain_lsft // unsigned , default = 6 bet1 left shift before combine with global gain
+//Bit 19 reg_nr4_bet2_glb_gain_en // unsigned , default = 1 bet2 adjust by global gain, dft = 1
+//Bit 18:16 reg_nr4_bet2_glb_gain_lsft // unsigned , default = 6 bet2 left shift before combine with global gain
+//Bit 15 reg_nr4_alp1_ac_en // unsigned , default = 1 alp1 adjust by ac, dft = 1
+//Bit 14:12 reg_nr4_alp1_ac_lsft // unsigned , default = 5 alp1 left shift before combine with ac
+//Bit 11 reg_nr4_bet0_ac_en // unsigned , default = 0 bet0 adjust by ac, dft = 1
+//Bit 10: 8 reg_nr4_bet0_ac_lsft // unsigned , default = 5 bet0 left shift before combine with ac
+//Bit 7 reg_nr4_bet1_ac_en // unsigned , default = 0 bet1 adjust by ac, dft = 1
+//Bit 6: 4 reg_nr4_bet1_ac_lsft // unsigned , default = 5 bet1 left shift before combine with ac
+//Bit 3 reg_nr4_bet2_ac_en // unsigned , default = 0 bet2 adjust by ac, dft = 1
+//Bit 2: 0 reg_nr4_bet2_ac_lsft // unsigned , default = 5 bet2 left shift before combine with ac
+#define NR4_MCNR_DC2NORM_LUT0 ((0x2dd8 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:24 reg_nr4_dc2norm_lut0 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+//Bit 23:21 reserved
+//Bit 20:16 reg_nr4_dc2norm_lut1 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+//Bit 15:13 reserved
+//Bit 12: 8 reg_nr4_dc2norm_lut2 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+//Bit 7: 5 reserved
+//Bit 4: 0 reg_nr4_dc2norm_lut3 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+#define NR4_MCNR_DC2NORM_LUT1 ((0x2dd9 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:24 reg_nr4_dc2norm_lut4 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+//Bit 23:21 reserved
+//Bit 20:16 reg_nr4_dc2norm_lut5 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+//Bit 15:13 reserved
+//Bit 12: 8 reg_nr4_dc2norm_lut6 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+//Bit 7: 5 reserved
+//Bit 4: 0 reg_nr4_dc2norm_lut7 // unsigned , default = 12 normal 0~16, dc to norm for alpha adjust, dft =
+#define NR4_MCNR_DC2NORM_LUT2 ((0x2dda << 2) + 0xff000000)
+//Bit 31: 5 reserved
+//Bit 4: 0 reg_nr4_dc2norm_lut8 // unsigned , default = 8 normal 0~16, dc to norm for alpha adjust, dft =
+#define NR4_MCNR_AC2NORM_LUT0 ((0x2ddb << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:24 reg_nr4_ac2norm_lut0 // unsigned , default = 2 normal 0~16, ac to norm for alpha adjust, dft =
+//Bit 23:21 reserved
+//Bit 20:16 reg_nr4_ac2norm_lut1 // unsigned , default = 16 normal 0~16, ac to norm for alpha adjust, dft =
+//Bit 15:13 reserved
+//Bit 12: 8 reg_nr4_ac2norm_lut2 // unsigned , default = 16 normal 0~16, ac to norm for alpha adjust, dft =
+//Bit 7: 5 reserved
+//Bit 4: 0 reg_nr4_ac2norm_lut3 // unsigned , default = 12 normal 0~16, ac to norm for alpha adjust, dft =
+#define NR4_MCNR_AC2NORM_LUT1 ((0x2ddc << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:24 reg_nr4_ac2norm_lut4 // unsigned , default = 4 normal 0~16, ac to norm for alpha adjust, dft =
+//Bit 23:21 reserved
+//Bit 20:16 reg_nr4_ac2norm_lut5 // unsigned , default = 2 normal 0~16, ac to norm for alpha adjust, dft =
+//Bit 15:13 reserved
+//Bit 12: 8 reg_nr4_ac2norm_lut6 // unsigned , default = 1 normal 0~16, ac to norm for alpha adjust, dft =
+//Bit 7: 5 reserved
+//Bit 4: 0 reg_nr4_ac2norm_lut7 // unsigned , default = 1 normal 0~16, ac to norm for alpha adjust, dft =
+#define NR4_MCNR_AC2NORM_LUT2 ((0x2ddd << 2) + 0xff000000)
+//Bit 31: 5 reserved
+//Bit 4: 0 reg_nr4_ac2norm_lut8 // unsigned , default = 1 normal 0~16, ac to norm for alpha adjust, dft =
+#define NR4_MCNR_SAD2ALP0_LUT0 ((0x2dde << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp0_lut0 // unsigned , default = 255 sad to alpha0 for temporal pixel value, dft = 255
+//Bit 23:16 reg_nr4_sad2alp0_lut1 // unsigned , default = 252 sad to alpha0 for temporal pixel value, dft = 252
+//Bit 15: 8 reg_nr4_sad2alp0_lut2 // unsigned , default = 249 sad to alpha0 for temporal pixel value, dft = 249
+//Bit 7: 0 reg_nr4_sad2alp0_lut3 // unsigned , default = 235 sad to alpha0 for temporal pixel value, dft = 70
+#define NR4_MCNR_SAD2ALP0_LUT1 ((0x2ddf << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp0_lut4 // unsigned , default = 185 sad to alpha0 for temporal pixel value, dft = 12
+//Bit 23:16 reg_nr4_sad2alp0_lut5 // unsigned , default = 70 sad to alpha0 for temporal pixel value, dft = 1
+//Bit 15: 8 reg_nr4_sad2alp0_lut6 // unsigned , default = 14 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 7: 0 reg_nr4_sad2alp0_lut7 // unsigned , default = 1 sad to alpha0 for temporal pixel value, dft = 0
+#define NR4_MCNR_SAD2ALP0_LUT2 ((0x2de0 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp0_lut8 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 23:16 reg_nr4_sad2alp0_lut9 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 15: 8 reg_nr4_sad2alp0_lut10 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 7: 0 reg_nr4_sad2alp0_lut11 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+#define NR4_MCNR_SAD2ALP0_LUT3 ((0x2de1 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp0_lut12 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 23:16 reg_nr4_sad2alp0_lut13 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 15: 8 reg_nr4_sad2alp0_lut14 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 7: 0 reg_nr4_sad2alp0_lut15 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+#define NR4_MCNR_SAD2ALP1_LUT0 ((0x2de2 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp1_lut0 // unsigned , default = 192 sad to alpha1 for temporal blending, dft = 128
+//Bit 23:16 reg_nr4_sad2alp1_lut1 // unsigned , default = 160 sad to alpha1 for temporal blending, dft = 128
+//Bit 15: 8 reg_nr4_sad2alp1_lut2 // unsigned , default = 128 sad to alpha1 for temporal blending, dft = 128
+//Bit 7: 0 reg_nr4_sad2alp1_lut3 // unsigned , default = 96 sad to alpha1 for temporal blending, dft = 64
+#define NR4_MCNR_SAD2ALP1_LUT1 ((0x2de3 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp1_lut4 // unsigned , default = 64 sad to alpha1 for temporal blending, dft = 64
+//Bit 23:16 reg_nr4_sad2alp1_lut5 // unsigned , default = 32 sad to alpha1 for temporal blending, dft = 128
+//Bit 15: 8 reg_nr4_sad2alp1_lut6 // unsigned , default = 16 sad to alpha1 for temporal blending, dft = 255
+//Bit 7: 0 reg_nr4_sad2alp1_lut7 // unsigned , default = 8 sad to alpha1 for temporal blending, dft = 255
+#define NR4_MCNR_SAD2ALP1_LUT2 ((0x2de4 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp1_lut8 // unsigned , default = 4 sad to alpha1 for temporal blending, dft = 255
+//Bit 23:16 reg_nr4_sad2alp1_lut9 // unsigned , default = 0 sad to alpha1 for temporal blending, dft = 255
+//Bit 15: 8 reg_nr4_sad2alp1_lut10 // unsigned , default = 16 sad to alpha1 for temporal blending, dft = 255
+//Bit 7: 0 reg_nr4_sad2alp1_lut11 // unsigned , default = 64 sad to alpha1 for temporal blending, dft = 255
+#define NR4_MCNR_SAD2ALP1_LUT3 ((0x2de5 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp1_lut12 // unsigned , default = 96 sad to alpha1 for temporal blending, dft = 255
+//Bit 23:16 reg_nr4_sad2alp1_lut13 // unsigned , default = 224 sad to alpha1 for temporal blending, dft = 255
+//Bit 15: 8 reg_nr4_sad2alp1_lut14 // unsigned , default = 255 sad to alpha1 for temporal blending, dft = 255
+//Bit 7: 0 reg_nr4_sad2alp1_lut15 // unsigned , default = 255 sad to alpha1 for temporal blending, dft = 255
+#define NR4_MCNR_SAD2BET0_LUT0 ((0x2de6 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet0_lut0 // unsigned , default = 0 sad to beta0 for tnr and mcnr blending, dft = 0
+//Bit 23:16 reg_nr4_sad2bet0_lut1 // unsigned , default = 2 sad to beta0 for tnr and mcnr blending, dft = 2
+//Bit 15: 8 reg_nr4_sad2bet0_lut2 // unsigned , default = 4 sad to beta0 for tnr and mcnr blending, dft = 4
+//Bit 7: 0 reg_nr4_sad2bet0_lut3 // unsigned , default = 8 sad to beta0 for tnr and mcnr blending, dft = 8
+#define NR4_MCNR_SAD2BET0_LUT1 ((0x2de7 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet0_lut4 // unsigned , default = 16 sad to beta0 for tnr and mcnr blending, dft = 16
+//Bit 23:16 reg_nr4_sad2bet0_lut5 // unsigned , default = 32 sad to beta0 for tnr and mcnr blending, dft = 32
+//Bit 15: 8 reg_nr4_sad2bet0_lut6 // unsigned , default = 48 sad to beta0 for tnr and mcnr blending, dft = 48
+//Bit 7: 0 reg_nr4_sad2bet0_lut7 // unsigned , default = 64 sad to beta0 for tnr and mcnr blending, dft = 64
+#define NR4_MCNR_SAD2BET0_LUT2 ((0x2de8 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet0_lut8 // unsigned , default = 80 sad to beta0 for tnr and mcnr blending, dft = 80
+//Bit 23:16 reg_nr4_sad2bet0_lut9 // unsigned , default = 96 sad to beta0 for tnr and mcnr blending, dft = 96
+//Bit 15: 8 reg_nr4_sad2bet0_lut10 // unsigned , default = 112 sad to beta0 for tnr and mcnr blending, dft = 112
+//Bit 7: 0 reg_nr4_sad2bet0_lut11 // unsigned , default = 128 sad to beta0 for tnr and mcnr blending, dft = 128
+#define NR4_MCNR_SAD2BET0_LUT3 ((0x2de9 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet0_lut12 // unsigned , default = 196 sad to beta0 for tnr and mcnr blending, dft = 160
+//Bit 23:16 reg_nr4_sad2bet0_lut13 // unsigned , default = 224 sad to beta0 for tnr and mcnr blending, dft = 192
+//Bit 15: 8 reg_nr4_sad2bet0_lut14 // unsigned , default = 255 sad to beta0 for tnr and mcnr blending, dft = 224
+//Bit 7: 0 reg_nr4_sad2bet0_lut15 // unsigned , default = 255 sad to beta0 for tnr and mcnr blending, dft = 255
+#define NR4_MCNR_SAD2BET1_LUT0 ((0x2dea << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet1_lut0 // unsigned , default = 0 sad to beta1 for deghost blending, dft = 0
+//Bit 23:16 reg_nr4_sad2bet1_lut1 // unsigned , default = 2 sad to beta1 for deghost blending, dft = 2
+//Bit 15: 8 reg_nr4_sad2bet1_lut2 // unsigned , default = 4 sad to beta1 for deghost blending, dft = 4
+//Bit 7: 0 reg_nr4_sad2bet1_lut3 // unsigned , default = 8 sad to beta1 for deghost blending, dft = 8
+#define NR4_MCNR_SAD2BET1_LUT1 ((0x2deb << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet1_lut4 // unsigned , default = 16 sad to beta1 for deghost blending, dft = 16
+//Bit 23:16 reg_nr4_sad2bet1_lut5 // unsigned , default = 32 sad to beta1 for deghost blending, dft = 32
+//Bit 15: 8 reg_nr4_sad2bet1_lut6 // unsigned , default = 48 sad to beta1 for deghost blending, dft = 48
+//Bit 7: 0 reg_nr4_sad2bet1_lut7 // unsigned , default = 64 sad to beta1 for deghost blending, dft = 64
+#define NR4_MCNR_SAD2BET1_LUT2 ((0x2dec << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet1_lut8 // unsigned , default = 80 sad to beta1 for deghost blending, dft = 80
+//Bit 23:16 reg_nr4_sad2bet1_lut9 // unsigned , default = 96 sad to beta1 for deghost blending, dft = 96
+//Bit 15: 8 reg_nr4_sad2bet1_lut10 // unsigned , default = 112 sad to beta1 for deghost blending, dft = 112
+//Bit 7: 0 reg_nr4_sad2bet1_lut11 // unsigned , default = 128 sad to beta1 for deghost blending, dft = 128
+#define NR4_MCNR_SAD2BET1_LUT3 ((0x2ded << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet1_lut12 // unsigned , default = 160 sad to beta1 for deghost blending, dft = 160
+//Bit 23:16 reg_nr4_sad2bet1_lut13 // unsigned , default = 192 sad to beta1 for deghost blending, dft = 192
+//Bit 15: 8 reg_nr4_sad2bet1_lut14 // unsigned , default = 224 sad to beta1 for deghost blending, dft = 224
+//Bit 7: 0 reg_nr4_sad2bet1_lut15 // unsigned , default = 255 sad to beta1 for deghost blending, dft = 255
+#define NR4_MCNR_SAD2BET2_LUT0 ((0x2dee << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet2_lut0 // unsigned , default = 0 sad to beta2 for snr and mcnr blending, dft = 0
+//Bit 23:16 reg_nr4_sad2bet2_lut1 // unsigned , default = 1 sad to beta2 for snr and mcnr blending, dft = 2
+//Bit 15: 8 reg_nr4_sad2bet2_lut2 // unsigned , default = 2 sad to beta2 for snr and mcnr blending, dft = 4
+//Bit 7: 0 reg_nr4_sad2bet2_lut3 // unsigned , default = 4 sad to beta2 for snr and mcnr blending, dft = 8
+#define NR4_MCNR_SAD2BET2_LUT1 ((0x2def << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet2_lut4 // unsigned , default = 8 sad to beta2 for snr and mcnr blending, dft = 16
+//Bit 23:16 reg_nr4_sad2bet2_lut5 // unsigned , default = 16 sad to beta2 for snr and mcnr blending, dft = 32
+//Bit 15: 8 reg_nr4_sad2bet2_lut6 // unsigned , default = 32 sad to beta2 for snr and mcnr blending, dft = 48
+//Bit 7: 0 reg_nr4_sad2bet2_lut7 // unsigned , default = 48 sad to beta2 for snr and mcnr blending, dft = 64
+#define NR4_MCNR_SAD2BET2_LUT2 ((0x2df0 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet2_lut8 // unsigned , default = 64 sad to beta2 for snr and mcnr blending, dft = 80
+//Bit 23:16 reg_nr4_sad2bet2_lut9 // unsigned , default = 80 sad to beta2 for snr and mcnr blending, dft = 96
+//Bit 15: 8 reg_nr4_sad2bet2_lut10 // unsigned , default = 96 sad to beta2 for snr and mcnr blending, dft = 112
+//Bit 7: 0 reg_nr4_sad2bet2_lut11 // unsigned , default = 112 sad to beta2 for snr and mcnr blending, dft = 128
+#define NR4_MCNR_SAD2BET2_LUT3 ((0x2df1 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet2_lut12 // unsigned , default = 128 sad to beta2 for snr and mcnr blending, dft = 160
+//Bit 23:16 reg_nr4_sad2bet2_lut13 // unsigned , default = 160 sad to beta2 for snr and mcnr blending, dft = 192
+//Bit 15: 8 reg_nr4_sad2bet2_lut14 // unsigned , default = 224 sad to beta2 for snr and mcnr blending, dft = 224
+//Bit 7: 0 reg_nr4_sad2bet2_lut15 // unsigned , default = 255 sad to beta2 for snr and mcnr blending, dft = 255
+#define NR4_MCNR_RO_U_SUM ((0x2df2 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_u_sum // unsigned , default = 0 sum of U of current field/frame
+#define NR4_MCNR_RO_V_SUM ((0x2df3 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_v_sum // unsigned , default = 0 sum of V of current field/frame
+#define NR4_MCNR_RO_GRDU_SUM ((0x2df4 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_grdu_sum // unsigned , default = 0 sum of gradient U of current field/frame
+#define NR4_MCNR_RO_GRDV_SUM ((0x2df5 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_grdv_sum // unsigned , default = 0 sum of gradient V of current field/frame
+#define NR4_TOP_CTRL ((0x2dff << 2) + 0xff000000)
+//Bit 31:20 reg_gclk_ctrl // unsigned , default = 0
+//Bit 19 reserved
+//Bit 18 reg_nr4_mcnr_en // unsigned , default = 1 ncnr enable or bypass, dft = 1
+//Bit 17 reg_nr2_en // unsigned , default = 1 nr2 enable, dft = 1
+//Bit 16 reg_nr4_en // unsigned , default = 1 nr4 enable, dft = 1
+//Bit 15 reg_nr2_proc_en // unsigned , default = 1
+//Bit 14 reg_det3d_en // unsigned , default = 1
+//Bit 13 di_polar_en // unsigned , default = 1 do does not have in C
+//Bit 12 reg_cfr_enable // unsigned , default = 0 0-disable; 1:enable
+//Bit 11: 9 reg_3dnr_enable_l // unsigned , default = 7 b0: Y b1:U b2:V
+//Bit 8: 6 reg_3dnr_enable_r // unsigned , default = 7 b0: Y b1:U b2:V
+//Bit 5 reg_nr4_lnbuf_ctrl // unsigned , default = 1 line buf ctrl for nr4: 0, 3lines, 1, 5lines, dft = 1
+//Bit 4 reg_nr4_snr2_en // unsigned , default = 0 snr2 enable, 0: use old snr, 1: use new snr2, dft = 1
+//Bit 3 reg_nr4_scene_change_en // unsigned , default = 1 enable scene change proc. dft = 1
+//Bit 2 nr2_sw_en // unsigned , default = 1 do does not have in C
+//Bit 1 reserved
+//Bit 0 reg_nr4_scene_change_flg // unsigned , default = 0 flags for scene change, dft = 0
+//========== nr4_mcnr_regs register end ==========//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_nr4_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_dnr_regs.h
+//
+//========================================================================
+// VI_HIST_SPL register (16'h2e00 - 16'h2eff)
+//========================================================================
+//
+// Reading file: vi_hist_spl_reg.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// ----------------------------
+// VI_HIST_SPL 0x2e
+// ----------------------------
+// -----------------------------------------------
+// REG_BASE: VI_HIST_SPL_VCBUS_BASE = 0x2e
+// -----------------------------------------------
+//BIT 14: 34bin only, 0&255 and other 32bins
+//Bit 13:11 hist_din_sel, 00: from vdin0 dout, 1: from vdin1, 2: from nr dout, 3: di output, 4: vpp output, 5: vd1_din, 6: vd2_din, 7:osd1_dout
+//Bit 10:8 hist_din_comp_mux, mux of [29:22], [19:12], [9:2] for hist detect
+//Bit 7:5 hist_dnlp_low the real pixels in each bins got by VI_DNLP_HISTXX should multiple with 2^(dnlp_low+3)
+//Bit 3:2 hist_din_sel the source used for hist statistics. 00: from matrix0 dout, 01: from vsc_dout, 10: from matrix1 dout, 11: form matrix1 din
+//Bit 1 hist_win_en 1'b0: hist used for full picture; 1'b1: hist used for pixels within hist window
+//Bit 0 hist_spl_en 1'b0: disable hist readback; 1'b1: enable hist readback
+#define VI_HIST_CTRL ((0x2e00 << 2) + 0xff000000)
+//Bit 28:16 hist_hstart horizontal start value to define hist window
+//Bit 12:0 hist_hend horizontal end value to define hist window
+#define VI_HIST_H_START_END ((0x2e01 << 2) + 0xff000000)
+//Bit 28:16 hist_vstart vertical start value to define hist window
+//Bit 12:0 hist_vend vertical end value to define hist window
+#define VI_HIST_V_START_END ((0x2e02 << 2) + 0xff000000)
+//Bit 15:8 hist_max maximum value
+//Bit 7:0 hist_min minimum value
+//read only
+#define VI_HIST_MAX_MIN ((0x2e03 << 2) + 0xff000000)
+//Bit 31:0 hist_spl_rd
+//counts for the total luma value
+//read only
+#define VI_HIST_SPL_VAL ((0x2e04 << 2) + 0xff000000)
+//Bit 21:0 hist_spl_pixel_count
+//counts for the total calculated pixels
+//read only
+#define VI_HIST_SPL_PIX_CNT ((0x2e05 << 2) + 0xff000000)
+//Bit 31:0 hist_chroma_sum
+//counts for the total chroma value
+//read only
+#define VI_HIST_CHROMA_SUM ((0x2e06 << 2) + 0xff000000)
+//Bit 31:16 higher hist bin
+//Bit 15:0 lower hist bin
+//0-255 are splited to 64 bins evenly, and VI_DNLP_HISTXX
+//are the statistic number of pixels that within each bin.
+//VI_DNLP_HIST00[15:0] counts for the first bin
+//VI_DNLP_HIST00[31:16] counts for the second bin
+//VI_DNLP_HIST01[15:0] counts for the third bin
+//VI_DNLP_HIST01[31:16] counts for the fourth bin
+//etc...
+//read only
+#define VI_DNLP_HIST00 ((0x2e07 << 2) + 0xff000000)
+#define VI_DNLP_HIST01 ((0x2e08 << 2) + 0xff000000)
+#define VI_DNLP_HIST02 ((0x2e09 << 2) + 0xff000000)
+#define VI_DNLP_HIST03 ((0x2e0a << 2) + 0xff000000)
+#define VI_DNLP_HIST04 ((0x2e0b << 2) + 0xff000000)
+#define VI_DNLP_HIST05 ((0x2e0c << 2) + 0xff000000)
+#define VI_DNLP_HIST06 ((0x2e0d << 2) + 0xff000000)
+#define VI_DNLP_HIST07 ((0x2e0e << 2) + 0xff000000)
+#define VI_DNLP_HIST08 ((0x2e0f << 2) + 0xff000000)
+#define VI_DNLP_HIST09 ((0x2e10 << 2) + 0xff000000)
+#define VI_DNLP_HIST10 ((0x2e11 << 2) + 0xff000000)
+#define VI_DNLP_HIST11 ((0x2e12 << 2) + 0xff000000)
+#define VI_DNLP_HIST12 ((0x2e13 << 2) + 0xff000000)
+#define VI_DNLP_HIST13 ((0x2e14 << 2) + 0xff000000)
+#define VI_DNLP_HIST14 ((0x2e15 << 2) + 0xff000000)
+#define VI_DNLP_HIST15 ((0x2e16 << 2) + 0xff000000)
+#define VI_DNLP_HIST16 ((0x2e17 << 2) + 0xff000000)
+#define VI_DNLP_HIST17 ((0x2e18 << 2) + 0xff000000)
+#define VI_DNLP_HIST18 ((0x2e19 << 2) + 0xff000000)
+#define VI_DNLP_HIST19 ((0x2e1a << 2) + 0xff000000)
+#define VI_DNLP_HIST20 ((0x2e1b << 2) + 0xff000000)
+#define VI_DNLP_HIST21 ((0x2e1c << 2) + 0xff000000)
+#define VI_DNLP_HIST22 ((0x2e1d << 2) + 0xff000000)
+#define VI_DNLP_HIST23 ((0x2e1e << 2) + 0xff000000)
+#define VI_DNLP_HIST24 ((0x2e1f << 2) + 0xff000000)
+#define VI_DNLP_HIST25 ((0x2e20 << 2) + 0xff000000)
+#define VI_DNLP_HIST26 ((0x2e21 << 2) + 0xff000000)
+#define VI_DNLP_HIST27 ((0x2e22 << 2) + 0xff000000)
+#define VI_DNLP_HIST28 ((0x2e23 << 2) + 0xff000000)
+#define VI_DNLP_HIST29 ((0x2e24 << 2) + 0xff000000)
+#define VI_DNLP_HIST30 ((0x2e25 << 2) + 0xff000000)
+#define VI_DNLP_HIST31 ((0x2e26 << 2) + 0xff000000)
+#define VI_DNLP_HIST32 ((0x2e27 << 2) + 0xff000000)
+//Bit 28:16 hist_pic_height active input data window height
+//Bit 12:0 hist_pic_width active input data window width
+#define VI_HIST_PIC_SIZE ((0x2e28 << 2) + 0xff000000)
+//Bit 15:8 hist_pix_white_value: >= this value will be white pixel
+//Bit 7:0 hist_pix_black_value: <= this value will be black pixel
+#define VI_HIST_BLACK_WHITE_VALUE ((0x2e29 << 2) + 0xff000000)
+#define VI_HIST_GCLK_CTRL ((0x2e2a << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vi_hist_spl_reg.h
+//
+//
+// Reading file: mcdi_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: MCDI_VCBUS_BASE = 0x2f
+// -----------------------------------------------
+////=================================================================////
+//// memc di core 0
+////=================================================================////
+#define MCDI_HV_SIZEIN ((0x2f00 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_mcdi_hsize image horizontal size (number of cols) default=1024
+//Bit 15:13, reserved
+//Bit 12: 0, reg_mcdi_vsize image vertical size (number of rows) default=1024
+#define MCDI_HV_BLKSIZEIN ((0x2f01 << 2) + 0xff000000)
+//Bit 31, reg_mcdi_vrev default = 0
+//Bit 30, reg_mcdi_hrev default = 0
+//Bit 29:28, reserved
+//Bit 27:16, reg_mcdi_blkhsize image horizontal blk size (number of cols) default=1024
+//Bit 15:13, reserved
+//Bit 11: 0, reg_mcdi_blkvsize image vertical blk size (number of rows) default=1024
+#define MCDI_BLKTOTAL ((0x2f02 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23: 0, reg_mcdi_blktotal
+#define MCDI_MOTINEN ((0x2f03 << 2) + 0xff000000)
+//Bit 31: 2, reserved
+//Bit 1, reg_mcdi_motionrefen. enable motion refinement of MA, default = 1
+//Bit 0, reg_mcdi_motionparadoxen. enable motion paradox detection, default = 1
+#define MCDI_CTRL_MODE ((0x2f04 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:26, reg_mcdi_lmvlocken 0:disable, 1: use max Lmv, 2: use no-zero Lmv, lmv lock enable mode, default = 2
+//Bit 25, reg_mcdi_reldetrptchken
+// 0: unable; 1: enable, enable repeat pattern check (not repeat mv detection) in rel det part, default = 1
+//Bit 24, reg_mcdi_reldetgmvpd22chken
+// 0: unable; 1: enable, enable pull-down 22 mode check in gmv lock mode for rel det, default = 1
+//Bit 23, reg_mcdi_pd22chken
+// 0: unable; 1: enable, enable pull-down 22 mode check (lock) function, default = 1
+//Bit 22, reg_mcdi_reldetlpfen
+// 0: unable; 1: enable, enable det value lpf, default = 1
+//Bit 21, reg_mcdi_reldetlmvpd22chken
+// 0: unable; 1: enable, enable pull-down 22 mode check in lmv lock mode for rel det, default = 1
+//Bit 20, reg_mcdi_reldetlmvdifchken
+// 0: unable; 1: enable, enable lmv dif check in lmv lock mode for rel det, default = 1
+//Bit 19, reg_mcdi_reldetgmvdifchken
+// 0: unable; 1: enable, enable lmv dif check in lmv lock mode for rel det, default = 1
+//Bit 18, reg_mcdi_reldetpd22chken
+// 0: unable; 1: enable, enable pull-down 22 mode check for rel det refinement, default = 1
+//Bit 17, reg_mcdi_reldetfrqchken
+// 0: unable; 1: enable, enable mv frequency check in rel det, default = 1
+//Bit 16, reg_mcdi_qmeen
+// 0: unable; 1: enable, enable quarter motion estimation, defautl = 1
+//Bit 15, reg_mcdi_refrptmven
+// 0: unable; 1: enable, use repeat mv in refinement, default = 1
+//Bit 14, reg_mcdi_refgmven
+// 0: unable; 1: enable, use gmv in refinement, default = 1
+//Bit 13, reg_mcdi_reflmven
+// 0: unable; 1: enable, use lmvs in refinement, default = 1
+//Bit 12, reg_mcdi_refnmven
+// 0: unable; 1: enable, use neighoring mvs in refinement, default = 1
+//Bit 11, reserved
+//Bit 10, reg_mcdi_referrfrqchken
+// 0: unable; 1: enable, enable mv frquency check while finding min err in ref, default = 1
+//Bit 9, reg_mcdi_refen
+// 0: unable; 1: enable, enable mv refinement, default = 1
+//Bit 8, reg_mcdi_horlineen
+// 0: unable; 1: enable,enable horizontal lines detection by sad map, default = 1
+//Bit 7, reg_mcdi_highvertfrqdeten
+// 0: unable; 1: enable, enable high vertical frequency pattern detection, default = 1
+//Bit 6, reg_mcdi_gmvlocken
+// 0: unable; 1: enable, enable gmv lock mode, default = 1
+//Bit 5, reg_mcdi_rptmven
+// 0: unable; 1: enable, enable repeat pattern detection, default = 1
+//Bit 4, reg_mcdi_gmven
+// 0: unable; 1: enable, enable global motion estimation, default = 1
+//Bit 3, reg_mcdi_lmven
+// 0: unable; 1: enable, enable line mv estimation for hme, default = 1
+//Bit 2, reg_mcdi_chkedgeen
+// 0: unable; 1: enable, enable check edge function, default = 1
+//Bit 1, reg_mcdi_txtdeten
+// 0: unable; 1: enable, enable texture detection, default = 1
+//Bit 0, reg_mcdi_memcen
+// 0: unable; 1: enable, enable of memc di, default = 1
+#define MCDI_UNI_MVDST ((0x2f05 << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:17, reg_mcdi_unimvdstabsseg0 segment0 for uni-mv abs, default = 1
+//Bit 16:12, reg_mcdi_unimvdstabsseg1 segment1 for uni-mv abs, default = 15
+//Bit 11: 8, reg_mcdi_unimvdstabsdifgain0 2/2, gain0 of uni-mv abs dif for segment0, normalized 2 to '1', default = 2
+//Bit 7: 5, reg_mcdi_unimvdstabsdifgain1 2/2, gain1 of uni-mv abs dif for segment1, normalized 2 to '1', default = 2
+//Bit 4: 2, reg_mcdi_unimvdstabsdifgain2 2/2, gain2 of uni-mv abs dif beyond segment1, normalized 2 to '1', default = 2
+//Bit 1: 0, reg_mcdi_unimvdstsgnshft shift for neighboring distance of uni-mv, default = 0
+#define MCDI_BI_MVDST ((0x2f06 << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:17, reg_mcdi_bimvdstabsseg0 segment0 for bi-mv abs, default = 1
+//Bit 16:12, reg_mcdi_bimvdstabsseg1 segment1 for bi-mv abs, default = 9
+//Bit 11: 8, reg_mcdi_bimvdstabsdifgain0 6/2, gain0 of bi-mv abs dif for segment0, normalized 2 to '1', default = 6
+//Bit 7: 5, reg_mcdi_bimvdstabsdifgain1 3/2, gain1 of bi-mvabs dif for segment1, normalized 2 to '1', default = 3
+//Bit 4: 2, reg_mcdi_bimvdstabsdifgain2 2/2, gain2 of bi-mvabs dif beyond segment1, normalized 2 to '1', default = 2
+//Bit 1: 0, reg_mcdi_bimvdstsgnshft shift for neighboring distance of bi-mv, default = 0
+#define MCDI_SAD_GAIN ((0x2f07 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18:17, reg_mcdi_unisadcorepxlgain uni-sad core pixels gain, default = 3
+//Bit 16, reg_mcdi_unisadcorepxlnormen enable uni-sad core pixels normalization, default = 0
+//Bit 15:11, reserved
+//Bit 10: 9, reg_mcdi_bisadcorepxlgain bi-sad core pixels gain, default = 3
+//Bit 8, reg_mcdi_bisadcorepxlnormen enable bi-sad core pixels normalization, default = 1
+//Bit 7: 3, reserved
+//Bit 2: 1, reg_mcdi_biqsadcorepxlgain bi-qsad core pixels gain, default = 3
+//Bit 0, reg_mcdi_biqsadcorepxlnormen enable bi-qsad core pixels normalization, default = 1
+#define MCDI_TXT_THD ((0x2f08 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_mcdi_txtminmaxdifthd, min max dif threshold (>=) for texture detection, default = 24
+//Bit 15: 8, reg_mcdi_txtmeandifthd, mean dif threshold (<) for texture detection, default = 9
+//Bit 7: 3, reserved
+//Bit 2: 0, reg_mcdi_txtdetthd, texture detecting threshold, 0~4, default = 2
+#define MCDI_FLT_MODESEL ((0x2f09 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28, reg_mcdi_flthorlineselmode mode for horizontal line detecting flat calculation, default = 1, same as below
+//Bit 27 reserved
+//Bit 26:24, reg_mcdi_fltgmvselmode mode for gmv flat calculation, default = 4, same as below
+//Bit 23, reserved
+//Bit 22:20, reg_mcdi_fltsadselmode mode for sad flat calculation, default = 2, same as below
+//Bit 19, reserved
+//Bit 18:16, reg_mcdi_fltbadwselmode mode for badw flat calculation, default = 3, same as below
+//Bit 15, reserved
+//Bit 14:12, reg_mcdi_fltrptmvselmode mode for repeat mv flat calculation, default = 4, same as below
+//Bit 11, reserved
+//Bit 10: 8, reg_mcdi_fltbadrelselmode mode for bad rel flat calculation, default = 4, same as below
+//Bit 7, reserved
+//Bit 6: 4, reg_mcdi_fltcolcfdselmode mode for col cfd flat calculation, default = 2, same as below
+//Bit 3, reserved
+//Bit 2: 0, reg_mcdi_fltpd22chkselmode mode for pd22 check flat calculation, default = 2, # 0:cur dif h, 1: cur dif v, 2: pre dif h, 3: pre dif v, 4: cur flt, 5: pre flt, 6: cur+pre, 7: max all(cur,pre)
+#define MCDI_CHK_EDGE_THD ((0x2f0a << 2) + 0xff000000)
+//Bit 23:28, reserved.
+//Bit 27:24, reg_mcdi_chkedgedifsadthd. thd (<=) for sad dif check, 0~8, default = 1
+//Bit 23:16, reserved.
+//Bit 15:12, reg_mcdi_chkedgemaxedgethd. max drt of edge, default = 15
+//Bit 11: 8, reg_mcdi_chkedgeminedgethd. min drt of edge, default = 2
+//Bit 7, reserved.
+//Bit 6: 0, reg_mcdi_chkedgevdifthd. thd for vertical dif in check edge, default = 14
+#define MCDI_CHK_EDGE_GAIN_OFFST ((0x2f0b << 2) + 0xff000000)
+//Bit 31:24, reserved.
+//Bit 23:20, reg_mcdi_chkedgedifthd1. thd1 for edge dif check (<=), default = 4
+//Bit 19:16, reg_mcdi_chkedgedifthd0. thd0 for edge dif check (>=), default = 15
+//Bit :15, reserved.
+//Bit 14:10, reg_mcdi_chkedgechklen. total check length for edge check, 1~24 (>0), default = 24
+//Bit 9: 8, reg_mcdi_chkedgeedgesel. final edge select mode, 0: original start edge, 1: lpf start edge, 2: orignal start+end edge, 3: lpf start+end edge, default = 1
+//Bit 7: 3, reg_mcdi_chkedgesaddstgain. distance gain for sad calc while getting edges, default = 4
+//Bit 2, reg_mcdi_chkedgechkmode. edge used in check mode, 0: original edge, 1: lpf edge, defautl = 1
+//Bit 1, reg_mcdi_chkedgestartedge. edge mode for start edge, 0: original edge, 1: lpf edge, defautl = 0
+//Bit 0, reg_mcdi_chkedgeedgelpf. edge lpf mode, 0:[0,2,4,2,0], 1:[1,2,2,2,1], default = 0
+#define MCDI_LMV_RT ((0x2f0c << 2) + 0xff000000)
+//BIt 31:15, reserved
+//Bit 14:12, reg_mcdi_lmvvalidmode valid mode for lmv calc., 100b: use char det, 010b: use flt, 001b: use hori flg
+//Bit 11:10, reg_mcdi_lmvgainmvmode four modes of mv selection for lmv weight calucluation, default = 1
+// 0: cur(x-3), lst(x-1,x,x+1); 1: cur(x-4,x-3), lst(x,x+1); 2: cur(x-5,x-4,x-3), lst(x-1,x,x+1,x+2,x+3); 3: cur(x-6,x-5,x-4,x-3), lst(x-1,x,x+1,x+2);
+//Bit 9, reg_mcdi_lmvinitmode initial lmvs at first row of input field, 0: intial value = 0; 1: inital = 32 (invalid), default = 0
+//Bit 8, reserved
+//Bit 7: 4, reg_mcdi_lmvrt0 ratio of max mv, default = 5
+//Bit 3: 0, reg_mcdi_lmvrt1 ratio of second max mv, default = 5
+#define MCDI_LMV_GAINTHD ((0x2f0d << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_lmvvxmaxgain max gain of lmv weight, default = 96
+//Bit 23, reserved
+//Bit 22:20, reg_mcdi_lmvdifthd0 dif threshold 0 (<) for small lmv, default = 1
+//Bit 19:17, reg_mcdi_lmvdifthd1 dif threshold 1 (<) for median lmv, default = 2
+//Bit 16:14, reg_mcdi_lmvdifthd2 dif threshold 2 (<) for large lmv, default = 3
+//Bit 13: 8, reg_mcdi_lmvnumlmt least/limit number of (total number - max0), default = 20
+//Bit 7: 0, reg_mcdi_lmvfltthd flt cnt thd (<) for lmv, default = 9
+#define MCDI_RPTMV_THD0 ((0x2f0e << 2) + 0xff000000)
+//Bit 31:25, reg_mcdi_rptmvslpthd2 slope thd (>=) between i and i+3/i-3 (i+4/i-4), default = 64
+//Bit 24:20, reg_mcdi_rptmvslpthd1 slope thd (>=) between i and i+2/i-2, default = 4
+//Bit 19:10, reg_mcdi_rptmvampthd2 amplitude thd (>=) between max and min, when count cycles, default = 300
+//Bit 9: 0, reg_mcdi_rptmvampthd1 amplitude thd (>=) between average of max and min, default = 400
+#define MCDI_RPTMV_THD1 ((0x2f0f << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:25, reg_mcdi_rptmvcyccntthd thd (>=) of total cycles count, default = 2
+//Bit 24:21, reg_mcdi_rptmvcycdifthd dif thd (<) of cycles length, default = 3
+//Bit 20:18, reg_mcdi_rptmvcycvldthd thd (>) of valid cycles number, default = 1
+//Bit 17:15, reg_mcdi_rptmvhalfcycminthd min length thd (>=) of half cycle, default = 2
+//Bit 14:11, reg_mcdi_rptmvhalfcycdifthd neighboring half cycle length dif thd (<), default = 5
+//Bit 10: 8, reg_mcdi_rptmvminmaxcntthd least number of valid max and min, default = 2
+//Bit 7: 5, reg_mcdi_rptmvcycminthd min length thd (>=) of cycles, default = 2
+//Bit 4: 0, reg_mcdi_rptmvcycmaxthd max length thd (<) of cycles, default = 17
+#define MCDI_RPTMV_THD2 ((0x2f10 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_mcdi_rptmvhdifthd0 higher hdif thd (>=) (vertical edge) for rpt detection, default = 8
+//Bit 15: 8, reg_mcdi_rptmvhdifthd1 hdif thd (>=) (slope edge) for rpt detection, default = 4
+//Bit 7: 0, reg_mcdi_rptmvvdifthd vdif thd (>=) (slope edge) for rpt detection, default = 1
+#define MCDI_RPTMV_SAD ((0x2f11 << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, reg_mcdi_rptmvsaddifthdgain 7x3x(16/16), gain for sad dif thd in rpt mv detection, 0~672, normalized 16 as '1', default = 336
+//Bit 15:10, reserved
+//Bit 9: 0, reg_mcdi_rptmvsaddifthdoffst offset for sad dif thd in rpt mv detection, -512~511, default = 16
+#define MCDI_RPTMV_FLG ((0x2f12 << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:16, reg_mcdi_rptmvmode select mode of mvs for repeat motion estimation, 0: hmv, 1: qmv/2, 2 or 3: qmv/4, default = 2
+//Bit 15: 8, reg_mcdi_rptmvflgcntthd thd (>=) of min count number for rptmv of whole field, for rptmv estimation, default = 64
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_rptmvflgcntrt 4/32, ratio for repeat mv flag count, normalized 32 as '1', set 31 to 32,
+#define MCDI_RPTMV_GAIN ((0x2f13 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_rptmvlftgain up repeat mv gain for hme, default = 96
+//Bit 23:16, reg_mcdi_rptmvuplftgain up left repeat mv gain for hme, default = 32
+//Bit 15: 8, reg_mcdi_rptmvupgain up repeat mv gain for hme, default = 64
+//Bit 7: 0, reg_mcdi_rptmvuprightgain up right repeat mv gain for hme, default = 32
+#define MCDI_GMV_RT ((0x2f14 << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30:24, reg_mcdi_gmvmtnrt0 ratio 0 for motion senario, set 127 to 128, normalized 128 as '1', default =32
+//Bit 23, reserved
+//Bit 22:16, reg_mcdi_gmvmtnrt1 ratio 1 for motion senario, set 127 to 128, normalized 128 as '1', default = 56
+//Bit 15, reserved
+//Bit 14: 8, reg_mcdi_gmvstlrt0 ratio 0 for still senario, set 127 to 128, normalized 128 as '1', default = 56
+//Bit 7, reserved
+//Bit 6: 0, reg_mcdi_gmvstlrt1 ratio 1 for still senario, set 127 to 128, normalized 128 as '1', default = 80
+#define MCDI_GMV_GAIN ((0x2f15 << 2) + 0xff000000)
+//Bit 31:25, reg_mcdi_gmvzeromvlockrt0 ratio 0 for locking zero mv, set 127 to 128, normalized 128 as '1', default = 100
+//Bit 24:18, reg_mcdi_gmvzeromvlockrt1 ratio 1 for locking zero mv, set 127 to 128, normalized 128 as '1', default = 112
+//Bit 17:16, reg_mcdi_gmvvalidmode valid mode for gmv calc., 10b: use flt, 01b: use hori flg, default = 3
+//Bit 15: 8, reg_mcdi_gmvvxgain gmv's vx gain when gmv locked for hme, default = 0
+//Bit 7: 0, reg_mcdi_gmvfltthd flat thd (<) for gmv calc. default = 3
+#define MCDI_HOR_SADOFST ((0x2f16 << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24:16, reg_mcdi_horsaddifthdgain 21*1/8, gain/divisor for sad dif threshold in hor line detection, normalized 8 as '1', default = 21
+//Bit 15: 8, reg_mcdi_horsaddifthdoffst offset for sad dif threshold in hor line detection, -128~127, default = 0
+//Bit 7: 0, reg_mcdi_horvdifthd threshold (>=) of vertical dif of next block for horizontal line detection, default = 24
+#define MCDI_REF_MV_NUM ((0x2f17 << 2) + 0xff000000)
+//Bit 31: 2, reserved
+//Bit 1: 0, reg_mcdi_refmcmode. motion compensated mode used in refinement, 0: pre, 1: next, 2: (pre+next)/2, default = 0
+#define MCDI_REF_BADW_THD_GAIN ((0x2f18 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:24, reg_mcdi_refbadwcnt2gain. gain for badwv count num==3, default = 6
+//Bit 23:20, reg_mcdi_refbadwcnt1gain. gain for badwv count num==2, default = 3
+//Bit 19:16, reg_mcdi_refbadwcnt0gain. gain for badwv count num==1, default = 1
+//Bit 15:12, reg_mcdi_refbadwthd3. threshold 3 for detect badweave with largest average luma, default = 4
+//Bit 11: 8, reg_mcdi_refbadwthd2. threshold 2 for detect badweave with third smallest average luma, default = 3
+//Bit 7: 4, reg_mcdi_refbadwthd1. threshold 1 for detect badweave with second smallest average luma, default = 2
+//Bit 3: 0, reg_mcdi_refbadwthd0. threshold 0 for detect badweave with smallest average luma, default = 1
+#define MCDI_REF_BADW_SUM_GAIN ((0x2f19 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12: 8, reg_mcdi_refbadwsumgain0. sum gain for r channel, 0~16, default = 8
+//Bit 7: 5, reserved
+//Bit 4, reg_mcdi_refbadwcalcmode. mode for badw calculation, 0:sum, 1:max, default = 0
+//Bit 3: 0, reserved
+#define MCDI_REF_BS_THD_GAIN ((0x2f1a << 2) + 0xff000000)
+//Bit 31:28, reg_mcdi_refbsudgain1. up & down block stregth gain1, normalized to 8 as '1', default = 2
+//Bit 27:24, reg_mcdi_refbsudgain0. up & down block stregth gain0, normalized to 8 as '1', default = 4
+//Bit 23:19, reserved
+//Bit 18:16, reg_mcdi_refbslftgain. left block strength gain, default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_refbsthd1. threshold 1 for detect block stregth in refinment, default = 16
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_refbsthd0. threshold 0 for detect block stregth in refinment, default = 8
+#define MCDI_REF_ERR_GAIN0 ((0x2f1b << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30:24, reg_mcdi_referrnbrdstgain. neighoring mv distances gain for err calc. in ref, normalized to 8 as '1', default = 48
+//Bit 23:20, reserved
+//Bit 19:16, reg_mcdi_referrbsgain. bs gain for err calc. in ref, normalized to 8 as '1', default = 4
+//Bit 15, reserved
+//Bit 14: 8, reg_mcdi_referrbadwgain. badw gain for err calc. in ref, normalized to 8 as '1', default = 64
+//Bit 7: 4, reserved
+//Bit 3: 0, reg_mcdi_referrsadgain. sad gain for err calc. in ref, normalized to 8 as '1', default = 4
+#define MCDI_REF_ERR_GAIN1 ((0x2f1c << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:16, reg_mcdi_referrchkedgegain. check edge gain for err calc. in ref, normalized to 8 as '1', default = 4
+//Bit 15:12, reserved
+//Bit 11: 8, reg_mcdi_referrlmvgain. (locked) lmv gain for err calc. in ref, normalized to 8 as '1', default = 0
+//Bit 7: 4, reserved
+//Bit 3: 0, reg_mcdi_referrgmvgain. (locked) gmv gain for err calc. in ref, normalized to 8 as '1', default = 0
+#define MCDI_REF_ERR_FRQ_CHK ((0x2f1d << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:24, reg_mcdi_referrfrqgain. gain for mv frquency, normalized to 4 as '1', default = 10
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_referrfrqmax. max gain for mv frquency check, default = 31
+//Bit 15, reserved
+//Bit 14:12, reg_mcdi_ref_errfrqmvdifthd2. mv dif threshold 2 (<) for mv frquency check, default = 3
+//Bit 11, reserved
+//Bit 10: 8, reg_mcdi_ref_errfrqmvdifthd1. mv dif threshold 1 (<) for mv frquency check, default = 2
+//Bit 7, reserved
+//Bit 6: 4, reg_mcdi_ref_errfrqmvdifthd0. mv dif threshold 0 (<) for mv frquency check, default = 1
+//Bit 3: 0, reserved
+#define MCDI_QME_LPF_MSK ((0x2f1e << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:24, reg_mcdi_qmechkedgelpfmsk0. lpf mask0 for chk edge in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7
+//Bit 23:20, reserved
+//Bit 19:16, reg_mcdi_qmebslpfmsk0. lpf mask0 for bs in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7
+//Bit 15:12, reserved
+//Bit 11: 8, reg_mcdi_qmebadwlpfmsk0. lpf mask0 for badw in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7
+//Bit 7: 4, reserved
+//Bit 3: 0, reg_mcdi_qmesadlpfmsk0. lpf mask0 for sad in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7
+#define MCDI_REL_DIF_THD_02 ((0x2f1f << 2) + 0xff000000)
+//Bit 31:24, reserved.
+//Bit 23:16, reg_mcdi_reldifthd2. thd (<) for (hdif+vdif), default = 9
+//Bit 15: 8, reg_mcdi_reldifthd1. thd (<) for (vdif), default = 5
+//Bit 7: 0, reg_mcdi_reldifthd0. thd (>=) for (hdif-vdif), default = 48
+#define MCDI_REL_DIF_THD_34 ((0x2f20 << 2) + 0xff000000)
+//Bit 31:16, reserved.
+//Bit 15: 8, reg_mcdi_reldifthd4. thd (<) for (hdif), default = 255
+//Bit 7: 0, reg_mcdi_reldifthd3. thd (>=) for (vdif-hdif), default = 48
+#define MCDI_REL_BADW_GAIN_OFFST_01 ((0x2f21 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_relbadwoffst1. offset for badw adj, for flat block, -128~127, default = 0
+//Bit 23:16, reg_mcdi_relbadwgain1. gain for badw adj, for flat block, default = 128
+//Bit 15: 8, reg_mcdi_relbadwoffst0. offset for badw adj, for vertical block, -128~127, default = 0
+//Bit 7: 0, reg_mcdi_relbadwgain0. gain for badw adj, for vertical block, default = 160
+#define MCDI_REL_BADW_GAIN_OFFST_23 ((0x2f22 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_relbadwoffst3. offset for badw adj, for other block, -128~127, default = 0
+//Bit 23:16, reg_mcdi_relbadwgain3. gain for badw adj, for other block, default = 48
+//Bit 15: 8, reg_mcdi_relbadwoffst2. offset for badw adj, for horizontal block, -128~127, default = 0
+//Bit 7: 0, reg_mcdi_relbadwgain2. gain for badw adj, for horizontal block, default = 48
+#define MCDI_REL_BADW_THD_GAIN_OFFST ((0x2f23 << 2) + 0xff000000)
+//Bit 31:23, reserved.
+//Bit 22:16, reg_mcdi_relbadwoffst. offset for badw thd adj, -64~63, default = 0
+//Bit 15: 8, reserved.
+//Bit 7: 0, reg_mcdi_relbadwthdgain. gain0 for badw thd adj, normalized to 16 as '1', default = 16
+#define MCDI_REL_BADW_THD_MIN_MAX ((0x2f24 << 2) + 0xff000000)
+//Bit 31:18, reserved.
+//Bit 17: 8, reg_mcdi_relbadwthdmax. max for badw thd adj, default = 256
+//Bit 7: 0, reg_mcdi_relbadwthdmin. min for badw thd adj, default = 16
+#define MCDI_REL_SAD_GAIN_OFFST_01 ((0x2f25 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_relsadoffst1. offset for sad adj, for flat block, -128~127, default = 0
+//Bit 23:20, reserved.
+//Bit 19:16, reg_mcdi_relsadgain1. gain for sad adj, for flat block, normalized to 8 as '1', default = 8
+//Bit 15: 8, reg_mcdi_relsadoffst0. offset for sad adj, for vertical block, -128~127, default = 0
+//Bit 7: 4, reserved.
+//Bit 3: 0, reg_mcdi_relsadgain0. gain for sad adj, for vertical block, normalized to 8 as '1', default = 6
+#define MCDI_REL_SAD_GAIN_OFFST_23 ((0x2f26 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_relsadoffst3. offset for sad adj, for other block, -128~127, default = 0
+//Bit 23:20, reserved.
+//Bit 19:16, reg_mcdi_relsadgain3. gain for sad adj, for other block, normalized to 8 as '1', default = 8
+//Bit 15: 8, reg_mcdi_relsadoffst2. offset for sad adj, for horizontal block, -128~127, default = 0
+//Bit 7: 4, reserved.
+//Bit 3: 0, reg_mcdi_relsadgain2. gain for sad adj, for horizontal block, normalized to 8 as '1', default = 12
+#define MCDI_REL_SAD_THD_GAIN_OFFST ((0x2f27 << 2) + 0xff000000)
+//Bit 31:24, reserved.
+//Bit 23:16, reg_mcdi_relsadoffst. offset for sad thd adj, -128~127, default = 0
+//Bit 15:10, reserved.
+//Bit 9: 0, reg_mcdi_relsadthdgain. gain for sad thd adj, 21*2/16, normalized to 16 as '1', default = 42
+#define MCDI_REL_SAD_THD_MIN_MAX ((0x2f28 << 2) + 0xff000000)
+//Bit 31:27, reserved.
+//Bit 26:16, reg_mcdi_relsadthdmax. max for sad thd adj, 21*32, default = 672
+//Bit 15: 9, reserved.
+//Bit 8: 0, reg_mcdi_relsadthdmin. min for sad thd adj, 21*2, default = 42
+#define MCDI_REL_DET_GAIN_00 ((0x2f29 << 2) + 0xff000000)
+//Bit 31:21, reserved.
+//Bit 20:16, reg_mcdi_reldetbsgain0. gain0 (gmv locked) for bs, for det. calc. normalized to 16 as '1', default = 8
+//Bit 15:14, reserved.
+//Bit 13: 8, reg_mcdi_reldetbadwgain0. gain0 (gmv locked) for badw, for det. calc. normalized to 16 as '1', default = 12
+//Bit 7: 5, reserved.
+//Bit 4: 0, reg_mcdi_reldetsadgain0. gain0 (gmv locked) for qsad, for det. calc. normalized to 16 as '1', default = 8
+#define MCDI_REL_DET_GAIN_01 ((0x2f2a << 2) + 0xff000000)
+//Bit 31:14, reserved.
+//Bit 12: 8, reg_mcdi_reldetchkedgegain0. gain0 (gmv locked) for chk_edge, for det. calc. normalized to 16 as '1', default = 2
+//Bit 7, reserved.
+//Bit 6: 0, reg_mcdi_reldetnbrdstgain0. gain0 (gmv locked) for neighoring dist, for det. calc. normalized to 16 as '1', default = 24
+#define MCDI_REL_DET_GAIN_10 ((0x2f2b << 2) + 0xff000000)
+//Bit 31:21, reserved.
+//Bit 20:16, reg_mcdi_reldetbsgain1. gain1 (lmv locked) for bs, for det. calc. normalized to 16 as '1', default = 0
+//Bit 15:14, reserved.
+//Bit 13: 8, reg_mcdi_reldetbadwgain1. gain1 (lmv locked) for badw, for det. calc. normalized to 16 as '1', default = 8
+//Bit 7: 5, reserved.
+//Bit 4: 0, reg_mcdi_reldetsadgain1. gain1 (lmv locked) for qsad, for det. calc. normalized to 16 as '1', default = 8
+#define MCDI_REL_DET_GAIN_11 ((0x2f2c << 2) + 0xff000000)
+//Bit 31:14, reserved.
+//Bit 12: 8, reg_mcdi_reldetchkedgegain1. gain1 (lmv locked) for chk_edge, for det. calc. normalized to 16 as '1', default = 0
+//Bit 7, reserved.
+//Bit 6: 0, reg_mcdi_reldetnbrdstgain1. gain1 (lmv locked) for neighoring dist, for det. calc. normalized to 16 as '1', default = 24
+#define MCDI_REL_DET_GAIN_20 ((0x2f2d << 2) + 0xff000000)
+//Bit 31:21, reserved.
+//Bit 20:16, reg_mcdi_reldetbsgain2. gain2 (no locked) for bs, for det. calc. normalized to 16 as '1', default = 12
+//Bit 15:14, reserved.
+//Bit 13: 8, reg_mcdi_reldetbadwgain2. gain2 (no locked) for badw, for det. calc. normalized to 16 as '1', default = 32
+//Bit 7: 5, reserved.
+//Bit 4: 0, reg_mcdi_reldetsadgain2. gain2 (no locked) for qsad, for det. calc. normalized to 16 as '1', default = 16
+#define MCDI_REL_DET_GAIN_21 ((0x2f2e << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, reg_mcdi_reldetoffst. offset for rel calculation, for det. calc. -512~511, default = 0
+//Bit 15:14, reserved.
+//Bit 12: 8, reg_mcdi_reldetchkedgegain2. gain2 (no locked) for chk_edge, for det. calc. normalized to 16 as '1', default = 10
+//Bit 7, reserved.
+//Bit 6: 0, reg_mcdi_reldetnbrdstgain2. gain2 (no locked) for neighoring dist, for det. calc. normalized to 16 as '1', default = 32
+#define MCDI_REL_DET_GMV_DIF_CHK ((0x2f2f << 2) + 0xff000000)
+//Bit 31:24, reserved.
+//Bit 23:16, reg_mcdi_reldetgmvfltthd. flat thd (>=) for gmv lock decision, default = 0
+//Bit 15, reserved.
+//Bit 14:12, reg_mcdi_reldetgmvdifthd. dif thd (>=) for current mv different from gmv for gmv dif check, actually used in Lmv lock check, default = 3
+//Bit 11, reserved.
+//Bit 10: 8, reg_mcdi_reldetgmvdifmin. min mv dif for gmv dif check, default = 1, note: dif between reg_mcdi_rel_det_gmv_dif_max and reg_mcdi_rel_det_gmv_dif_min should be; 0,1,3,7, not work for others
+//Bit 7: 4, reg_mcdi_reldetgmvdifmax. max mv dif for gmv dif check, default = 4
+//Bit 3: 1, reserved
+//Bit 0, reg_mcdi_reldetgmvdifmvmode. mv mode used for gmv dif check, 0: use refmv, 1: use qmv, default = 0
+#define MCDI_REL_DET_LMV_DIF_CHK ((0x2f30 << 2) + 0xff000000)
+//Bit 31:24, reserved.
+//Bit 23:16, reg_mcdi_reldetlmvfltthd. flat thd (>=) for lmv lock decision, default = 12
+//Bit 15:14, reserved.
+//Bit 13:12, reg_mcdi_reldetlmvlockchkmode. lmv lock check mode, 0:cur Lmv, 1: cur & (last | next), 2: last & cur & next Lmv, default = 1
+//Bit 11, reserved.
+//Bit 10: 8, reg_mcdi_reldetlmvdifmin. min mv dif for lmv dif check, default = 1, note: dif between reg_mcdi_rel_det_lmv_dif_max and reg_mcdi_rel_det_lmv_dif_min should be; 0,1,3,7, not work for others
+//Bit 7: 4, reg_mcdi_reldetlmvdifmax. max mv dif for lmv dif check, default = 4
+//Bit 3: 1, reserved
+//Bit 0, reg_mcdi_reldetlmvdifmvmode. mv mode used for lmv dif check, 0: use refmv, 1: use qmv, default = 0
+#define MCDI_REL_DET_FRQ_CHK ((0x2f31 << 2) + 0xff000000)
+//Bit 31:12, reserved.
+//Bit 11: 8, reg_mcdi_reldetfrqgain. gain for frequency check, normalized to 4 as '1', default = 10
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetfrqmax. max value for frequency check, default = 31
+#define MCDI_REL_DET_PD22_CHK ((0x2f32 << 2) + 0xff000000)
+//Bit 31:18, reserved.
+//Bit 17: 8, reg_mcdi_reldetpd22chkoffst. offset for pd22 check happened, default = 512
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetpd22chkgain. gain for pd22 check happened, normalized to 8 as '1', default = 12
+#define MCDI_REL_DET_RPT_CHK_ROW ((0x2f33 << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:16, reg_mcdi_reldetrptchkendrow. end row (<) number for repeat check, default = 2047
+//Bit 15:11, reserved
+//Bit 10: 0, reg_mcdi_reldetrptchkstartrow. start row (>=) number for repeat check, default = 0
+#define MCDI_REL_DET_RPT_CHK_GAIN_QMV ((0x2f34 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_mcdi_reldetrptchkqmvmax. max thd (<) of abs qmv for repeat check, default = 15, note that quarter mv's range is -63~63
+//Bit 23:22, reserved
+//Bit 21:16, reg_mcdi_reldetrptchkqmvmin. min thd (>=) of abs qmv for repeat check, default = 10, note that quarter mv's range is -63~63
+//Bit 15, reserved/
+//Bit 14: 4, reg_mcdi_reldetrptchkoffst. offset for repeat check, default = 512
+//Bit 3: 0, reg_mcdi_reldetrptchkgain. gain for repeat check, normalized to 8 as '1', default = 4
+#define MCDI_REL_DET_RPT_CHK_THD_0 ((0x2f35 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_mcdi_reldetrptchkzerosadthd. zero sad thd (<) for repeat check, default = 255
+//Bit 15:14, reserved.
+//Bit 13: 8, reg_mcdi_reldetrptchkzerobadwthd. zero badw thd (>=) for repeat check, default = 16
+//Bit 7: 4, reserved
+//Bit 3: 0, reg_mcdi_reldetrptchkfrqdifthd. frequency dif thd (<) for repeat check, 0~10, default = 5
+#define MCDI_REL_DET_RPT_CHK_THD_1 ((0x2f36 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_mcdi_reldetrptchkvdifthd. vertical dif thd (<) for repeat check, default = 16
+//Bit 7: 0, reg_mcdi_reldetrptchkhdifthd. horizontal dif thd (>=) for repeat check, default = 16
+#define MCDI_REL_DET_LPF_DIF_THD ((0x2f37 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetlpfdifthd3. hdif thd (<) for lpf selection of horizontal block, default = 9
+//Bit 23:16, reg_mcdi_reldetlpfdifthd2. vdif-hdif thd (>=) for lpf selection of horizontal block, default = 48
+//Bit 15: 8, reg_mcdi_reldetlpfdifthd1. vdif thd (<) for lpf selection of vertical block, default = 9
+//Bit 7: 0, reg_mcdi_reldetlpfdifthd0. hdif-vdif thd (>=) for lpf selection of vertical block, default = 48
+#define MCDI_REL_DET_LPF_MSK_00_03 ((0x2f38 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_mcdi_reldetlpfmsk03. det lpf mask03 for gmv/lmv locked mode, 0~16, default = 1
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_reldetlpfmsk02. det lpf mask02 for gmv/lmv locked mode, 0~16, default = 1
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_reldetlpfmsk01. det lpf mask01 for gmv/lmv locked mode, 0~16, default = 5
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetlpfmsk00. det lpf mask00 for gmv/lmv locked mode, 0~16, default = 8
+#define MCDI_REL_DET_LPF_MSK_04_12 ((0x2f39 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_mcdi_reldetlpfmsk12. det lpf mask12 for vertical blocks, 0~16, default = 0
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_reldetlpfmsk11. det lpf mask11 for vertical blocks, 0~16, default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_reldetlpfmsk10. det lpf mask10 for vertical blocks, 0~16, default = 16
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetlpfmsk04. det lpf mask04 for gmv/lmv locked mode, 0~16, default = 1
+#define MCDI_REL_DET_LPF_MSK_13_21 ((0x2f3a << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_mcdi_reldetlpfmsk21. det lpf mask21 for horizontal blocks, 0~16, default = 6
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_reldetlpfmsk20. det lpf mask20 for horizontal blocks, 0~16, default = 8
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_reldetlpfmsk14. det lpf mask14 for vertical blocks, 0~16, default = 0
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetlpfmsk13. det lpf mask13 for vertical blocks, 0~16, default = 0
+#define MCDI_REL_DET_LPF_MSK_22_30 ((0x2f3b << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_mcdi_reldetlpfmsk30. det lpf mask30 for other blocks, 0~16, default = 16
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_reldetlpfmsk24. det lpf mask24 for horizontal blocks, 0~16, default = 1
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_reldetlpfmsk23. det lpf mask23 for horizontal blocks, 0~16, default = 0
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetlpfmsk22. det lpf mask22 for horizontal blocks, 0~16, default = 1
+#define MCDI_REL_DET_LPF_MSK_31_34 ((0x2f3c << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_mcdi_reldetlpfmsk34. det lpf mask34 for other blocks, 0~16, default = 0
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_reldetlpfmsk33. det lpf mask33 for other blocks, 0~16, default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_reldetlpfmsk32. det lpf mask32 for other blocks, 0~16, default = 0
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetlpfmsk31. det lpf mask31 for other blocks, 0~16, default = 0
+//Note: there are four group lpf masks from addr 37~3b, each group sum equal to 16.
+#define MCDI_REL_DET_MIN ((0x2f3d << 2) + 0xff000000)
+//Bit 31: 7, reserved
+//Bit 6: 0, reg_mcdi_reldetmin. min of detected value, default = 16
+#define MCDI_REL_DET_LUT_0_3 ((0x2f3e << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetmaplut3. default = 8
+//Bit 23:16, reg_mcdi_reldetmaplut2. default = 4
+//Bit 15: 8, reg_mcdi_reldetmaplut1. default = 2
+//Bit 7: 0, reg_mcdi_reldetmaplut0. default = 0
+#define MCDI_REL_DET_LUT_4_7 ((0x2f3f << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetmaplut7. default = 64
+//Bit 23:16, reg_mcdi_reldetmaplut6. default = 48
+//Bit 15: 8, reg_mcdi_reldetmaplut5. default = 32
+//Bit 7: 0, reg_mcdi_reldetmaplut4. default = 16
+#define MCDI_REL_DET_LUT_8_11 ((0x2f40 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetmaplut11. default = 160
+//Bit 23:16, reg_mcdi_reldetmaplut10. default = 128
+//Bit 15: 8, reg_mcdi_reldetmaplut9. default = 96
+//Bit 7: 0, reg_mcdi_reldetmaplut8. default = 80
+#define MCDI_REL_DET_LUT_12_15 ((0x2f41 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetmaplut15. default = 255
+//Bit 23:16, reg_mcdi_reldetmaplut14. default = 240
+//Bit 15: 8, reg_mcdi_reldetmaplut13. default = 224
+//Bit 7: 0, reg_mcdi_reldetmaplut12. default = 192
+#define MCDI_REL_DET_COL_CFD_THD ((0x2f42 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetcolcfdfltthd. thd for flat smaller than (<) of column cofidence, default = 5
+//Bit 23:16, reg_mcdi_reldetcolcfdthd1. thd for rel larger than (>=) in rel calc. mode col confidence without gmv locking, default = 160
+//Bit 15: 8, reg_mcdi_reldetcolcfdthd0. thd for rel larger than (>=) in rel calc. mode col confidence when gmv locked, default = 100
+//Bit 7: 2, reg_mcdi_reldetcolcfdbadwthd. thd for badw larger than (>=) in qbadw calc. mode of column cofidence, default = 16
+//Bit 1, reserved
+//Bit 0, reg_mcdi_reldetcolcfdcalcmode. calc. mode for column cofidence, 0: use rel, 1: use qbadw, default = 0
+#define MCDI_REL_DET_COL_CFD_AVG_LUMA ((0x2f43 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetcolcfdavgmin1. avg luma min1 (>=) for column cofidence, valid between 16~235, default = 235
+//Bit 23:16, reg_mcdi_reldetcolcfdavgmax1. avg luma max1 (<) for column cofidence, valid between 16~235, default = 235
+//Bit 15: 8, reg_mcdi_reldetcolcfdavgmin0. avg luma min0 (>=) for column cofidence, valid between 16~235, default = 16
+//Bit 7: 0, reg_mcdi_reldetcolcfdavgmax0. avg luma max0 (<) for column cofidence, valid between 16~235, default = 21
+#define MCDI_REL_DET_BAD_THD_0 ((0x2f44 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_mcdi_reldetbadsadthd. thd (>=) for bad sad, default = 120 (480/4)
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_mcdi_reldetbadbadwthd. thd (>=) for bad badw, 0~42, default = 12
+#define MCDI_REL_DET_BAD_THD_1 ((0x2f45 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_mcdi_reldetbadrelfltthd. thd (>=) of flat for bad rel detection, default = 4
+//Bit 15: 8, reg_mcdi_reldetbadrelthd1. thd (>=) for bad rel without gmv/lmv locked, default = 160
+//Bit 7: 0, reg_mcdi_reldetbadrelthd0. thd (>=) for bad rel with gmv/lmv locked, default = 120
+#define MCDI_PD22_CHK_THD ((0x2f46 << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24:16, reg_mcdi_pd22chksaddifthd. sad dif thd (>=) for (pd22chksad - qsad) for pd22 check, default = 64
+//Bit 15:14, reserved
+//Bit 13: 8, reg_mcdi_pd22chkqmvthd. thd (>=) of abs qmv for pd22 check, default = 2
+//Bit 7: 0, reg_mcdi_pd22chkfltthd. thd (>=) of flat for pd22 check, default = 4
+#define MCDI_PD22_CHK_GAIN_OFFST_0 ((0x2f47 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_pd22chkedgeoffst0. offset0 of pd22chkedge from right film22 phase, -128~127, default = 0
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_pd22chkedgegain0. gain0 of pd22chkedge from right film22 phase, normalized to 16 as '1', default = 16
+//Bit 15:12, reserved
+//Bit 11: 8, reg_mcdi_pd22chkbadwoffst0. offset0 of pd22chkbadw from right film22 phase, -8~7, default = 0
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_pd22chkbadwgain0. gain0 of pd22chkbadw from right film22 phase, normalized to 16 as '1', default = 8
+#define MCDI_PD22_CHK_GAIN_OFFST_1 ((0x2f48 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_pd22chkedgeoffst1. offset1 of pd22chkedge from right film22 phase, -128~127, default = 0
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_pd22chkedgegain1. gain1 of pd22chkedge from right film22 phase, normalized to 16 as '1', default = 16
+//Bit 15:12, reserved
+//Bit 11: 8, reg_mcdi_pd22chkbadwoffst1. offset1 of pd22chkbadw from right film22 phase, -8~7, default = 0
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_pd22chkbadwgain1. gain1 of pd22chkbadw from right film22 phase, normalized to 16 as '1', default = 12
+#define MCDI_LMV_LOCK_CNT_THD_GAIN ((0x2f49 << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:16, reg_mcdi_lmvlockcntmax. max lmv lock count number, default = 6
+//Bit 15:12, reg_mcdi_lmvlockcntoffst. offset for lmv lock count, -8~7, default = 0
+//Bit 11: 8, reg_mcdi_lmvlockcntgain. gain for lmv lock count, normalized 8 as '1', 15 is set to 16, default = 8
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_lmvlockcntthd. lmv count thd (>=) before be locked, 1~31, default = 4
+#define MCDI_LMV_LOCK_ABS_DIF_THD ((0x2f4a << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:24, reg_mcdi_lmvlockdifthd2. lmv dif thd for third part, before locked, default = 1
+//Bit 23, reserved
+//Bit 22:20, reg_mcdi_lmvlockdifthd1. lmv dif thd for second part, before locked, default = 1
+//Bit 19, reserved
+//Bit 18:16, reg_mcdi_lmvlockdifthd0. lmv dif thd for first part, before locked, default = 1
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_lmvlockabsmax. max abs (<) of lmv to be locked, default = 24
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_lmvlockabsmin. min abs (>=) of lmv to be locked, default = 1
+#define MCDI_LMV_LOCK_ROW ((0x2f4b << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:16, reg_mcdi_lmvlockendrow. end row (<) for lmv lock, default = 2047
+//Bit 15:11, reserved
+//Bit 10: 0, reg_mcdi_lmvlockstartrow. start row (>=) for lmv lock, default = 0
+#define MCDI_LMV_LOCK_RT_MODE ((0x2f4c << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:24, reg_mcdi_lmvlockextmode. extend lines for lmv lock check, check how many lines for lmv locking, default = 2
+//Bit 23:16, reg_mcdi_lmvlockfltcntrt. ratio of flt cnt for lock check, normalized 256 as '1', 255 is set to 256, default = 32
+//Bit 15: 8, reg_mcdi_lmvlocklmvcntrt1. ratio when use non-zero lmv for lock check, normalized 256 as '1', 255 is set to 256, default = 48
+//Bit 7: 0, reg_mcdi_lmvlocklmvcntrt0. ratio when use max lmv for lock check, normalized 256 as '1', 255 is set to 256, default = 106
+#define MCDI_GMV_LOCK_CNT_THD_GAIN ((0x2f4d << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:16, reg_mcdi_gmvlockcntmax. max gmv lock count number, default = 6
+//Bit 15:12, reg_mcdi_gmvlockcntoffst. offset for gmv lock count, -8~7, default = 0
+//Bit 11: 8, reg_mcdi_gmvlockcntgain. gain for gmv lock count, normalized 8 as '1', 15 is set to 16, default = 8
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_gmvlockcntthd. gmv count thd (>=) before be locked, 1~31, default = 4
+#define MCDI_GMV_LOCK_ABS_DIF_THD ((0x2f4e << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:24, reg_mcdi_gmvlockdifthd2. gmv dif thd for third part, before locked, default = 3
+//Bit 23, reserved
+//Bit 22:20, reg_mcdi_gmvlockdifthd1. gmv dif thd for second part, before locked, default = 2
+//Bit 19, reserved
+//Bit 18:16, reg_mcdi_gmvlockdifthd0. gmv dif thd for first part, before locked, default = 1
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_gmvlockabsmax. max abs of gmv to be locked, default = 15
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_gmvlockabsmin. min abs of gmv to be locked, default = 1
+#define MCDI_HIGH_VERT_FRQ_DIF_THD ((0x2f4f << 2) + 0xff000000)
+//Bit 31: 0, reg_mcdi_highvertfrqfldavgdifthd. high_vert_frq field average luma dif thd (>=), 3*Blk_Width*Blk_Height, set by software, default = 103680
+#define MCDI_HIGH_VERT_FRQ_DIF_DIF_THD ((0x2f50 << 2) + 0xff000000)
+//Bit 31: 0, reg_mcdi_highvertfrqfldavgdifdifthd. high_vert_frq field average luma dif's dif thd (<), 3*Blk_Width*Blk_Height, set by software, default = 103680
+#define MCDI_HIGH_VERT_FRQ_RT_GAIN ((0x2f51 << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:16, reg_mcdi_highvertfrqcntthd. high_vert_frq count thd (>=) before locked, 1~31, default = 4
+//Bit 15: 8, reg_mcdi_highvertfrqbadsadrt. ratio for high_vert_frq bad sad count, normalized 256 as '1', 255 is set to 256, default = 24
+//Bit 7: 0, reg_mcdi_highvertfrqbadbadwrt. ratio for high_vert_frq badw count, normalized 256 as '1', 255 is set to 256, default = 130
+#define MCDI_MOTION_PARADOX_THD ((0x2f52 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_mcdi_motionparadoxcntthd. motion paradox count thd (>=) before locked, 1~31, default = 4
+//Bit 23:22, reserved
+//Bit 21:16, reg_mcdi_motionparadoxgmvthd. abs gmv thd (<) of motion paradox, 0~32, note that 32 means invalid gmv, be careful, default = 32
+//Bit 15: 0, reserved
+#define MCDI_MOTION_PARADOX_RT ((0x2f53 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_mcdi_motionparadoxbadsadrt. ratio for field bad sad count of motion paradox, normalized 256 as '1', 255 is set to 256, default = 24
+//Bit 15: 8, reg_mcdi_motionparadoxbadrelrt. ratio for field bad reliabilty count of motion paradox, normalized 256 as '1', 255 is set to 256, default = 120
+//Bit 7: 0, reg_mcdi_motionparadoxmtnrt. ratio for field motion count of motion paradox, normalized 256 as '1', 255 is set to 256, default = 218
+#define MCDI_MOTION_REF_THD ((0x2f54 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:20, reg_mcdi_motionrefoffst. motion ref additive offset, default = 15
+//Bit 19:16, reg_mcdi_motionrefgain. motion ref gain, normalized 8 as '1', default = 8
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_motionrefrptmvthd. abs thd (>=) of rpt mv (0~31, 32 means invalid) for motion ref, default = 1
+//Bit 7: 2, reg_mcdi_motionrefqmvthd. min thd (>=) of abs qmv for motion ref, note that quarter mv's range is -63~63, default = 2
+//Bit 1: 0, reg_mcdi_motionreflpfmode. Mv and (8 x repeat flg) 's lpf mode of motion refinement, 0: no lpf, 1: [1 2 1], 2: [1 2 2 2 1], default = 1
+#define MCDI_REL_COL_REF_RT ((0x2f55 << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_mcdi_relcolrefrt. ratio for column cofidence level against column number, for refinement, default = 135
+#define MCDI_PD22_CHK_THD_RT ((0x2f56 << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:16, reg_mcdi_pd22chkfltcntrt. ratio for flat count of field pulldown 22 check, normalized 2048 as '1', 2047 is set to 2048, default = 1
+//Bit 15: 8, reg_mcdi_pd22chkcntrt. ratio of pulldown 22 check count, normalized 256 as '1', 255 is set to 256, default = 100
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_pd22chkcntthd. thd (>=) for pd22 count before locked, 1~31, default = 4
+#define MCDI_CHAR_DET_DIF_THD ((0x2f57 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_mcdi_chardetminmaxdifthd. thd (>=) for dif between min and max value, default = 64
+//Bit 15: 8, reg_mcdi_chardetmaxdifthd. thd (<) for dif between max value, default = 17
+//Bit 7: 0, reg_mcdi_chardetmindifthd. thd (<) for dif between min value, default = 17
+#define MCDI_CHAR_DET_CNT_THD ((0x2f58 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_mcdi_chardettotcntthd. thd (>=) for total count, 0~21, default = 18
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_chardetmaxcntthd. thd (>=) for max count, 0~21, default = 1
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_chardetmincntthd. thd (>=) for min count, 0~21, default = 1
+//new add
+#define MCDI_PD_22_CHK_WND0_X ((0x2f59 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_mcdi_pd22chkwnd0_x1 u13, x1 for window 0, HSIZE-1, software control, default = 719
+//Bit 15:13, reserved
+//Bit 12: 0, reg_mcdi_pd22chkwnd0_x0 u13, x0 for window 0, software control, default = 0
+#define MCDI_PD_22_CHK_WND0_Y ((0x2f5a << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_mcdi_pd22chkwnd0_y1 u13, y1 for window 0 software control, default = 39
+//Bit 15:13, reserved
+//Bit 12: 0, reg_mcdi_pd22chkwnd0_y0 u13, y0 for window 0, software control, default = 0
+#define MCDI_PD_22_CHK_WND1_X ((0x2f5b << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_mcdi_pd22chkwnd1_x1 u13, x1 for window 1, HSIZE-1, software control, default = 719
+//Bit 15:13, reserved
+//Bit 12: 0, reg_mcdi_pd22chkwnd1_x0 u13, x0 for window 1, software control, default = 0
+#define MCDI_PD_22_CHK_WND1_Y ((0x2f5c << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_mcdi_pd22chkwnd1_y1 u13, y1 for window 1 software control, default = 199
+//Bit 15:13, reserved
+//Bit 12: 0, reg_mcdi_pd22chkwnd1_y0 u13, y0 for window 1, software control, default = 40
+#define MCDI_PD_22_CHK_FRC_LMV ((0x2f5d << 2) + 0xff000000)
+//Bit 31:11, reserved
+//Bit 10, reg_mcdi_pd22chklmvchk2 u1, lmv lock check while force vof for each windows, default = 1
+//Bit 9, reg_mcdi_pd22chklmvchk1 u1, lmv lock check while force vof for each windows, default = 0
+//Bit 8, reg_mcdi_pd22chklmvchk0 u1, lmv lock check while force vof for each windows, default = 0
+//Bit 7, reserved
+//Bit 6, reg_mcdi_pd22chkfrcpd2 u1, force pd flags for each windows, default = 0
+//Bit 5, reg_mcdi_pd22chkfrcpd1 u1, force pd flags for each windows, default = 0
+//Bit 4, reg_mcdi_pd22chkfrcpd0 u1, force pd flags for each windows, default = 0
+//Bit 3, reserved
+//Bit 2, reg_mcdi_pd22chkfrcvof2 u1, force vof flags for each windows, default = 1
+//Bit 1, reg_mcdi_pd22chkfrcvof1 u1, force vof flags for each windows, default = 0
+//Bit 0, reg_mcdi_pd22chkfrcvof0 u1, force vof flags for each windows, default = 0
+#define MCDI_PD_22_CHK_FLG_CNT ((0x2f5e << 2) + 0xff000000)
+//Bit 31:27, reserved.
+//Bit 26, reg_mcdi_pd22chkflg2. pull down 22 flag of prevoius one field. initial = 0
+//Bit 25, reg_mcdi_pd22chkflg1. pull down 22 flag of prevoius one field. initial = 0
+//Bit 24, reg_mcdi_pd22chkflg. pull down 22 flag of prevoius one field. initial = 0
+//Bit 23:16, reg_mcdi_pd22chkcnt2. pull down 22 count till prevoius one field. initial = 0
+//Bit 15: 8, reg_mcdi_pd22chkcnt1. pull down 22 count till prevoius one field. initial = 0
+//Bit 7: 0, reg_mcdi_pd22chkcnt. pull down 22 count till prevoius one field. initial = 0
+#define MCDI_RO_FLD_PD_22_PRE_CNT1 ((0x2fca << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22precnt1. prevoius pd22 check count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_FOR_CNT1 ((0x2fcb << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22forcnt1. forward pd22 check count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_FLT_CNT1 ((0x2fcc << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22fltcnt1. flat count (for pd22 check) of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_PRE_CNT2 ((0x2fcd << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22precnt2. prevoius pd22 check count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_FOR_CNT2 ((0x2fce << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22forcnt2. forward pd22 check count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_FLT_CNT2 ((0x2fcf << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22fltcnt2. flat count (for pd22 check) of whole pre one field (block based). initial = 0
+#define MCDI_FIELD_MV ((0x2f60 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_pd22chkcnt
+//Bit 23:16, reg_mcdi_fieldgmvcnt
+//Bit 15, reg_mcdi_pd22chkflg
+//Bit 14, reg_mcdi_fieldgmvlock
+//Bit 13: 8, reg_mcdi_fieldrptmv. last field rpt mv
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_mcdi_fieldgmv. last field gmv
+#define MCDI_FIELD_HVF_PRDX_CNT ((0x2f61 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_motionparadoxcnt.
+//Bit 23:17, reserved
+//Bit 16, reg_mcdi_motionparadoxflg.
+//Bit 15: 8, reg_mcdi_highvertfrqcnt.
+//Bit 7: 4, reserved
+//Bit 3: 2, reg_mcdi_highvertfrqphase.
+//Bit 1, reserved
+//Bit 0, reg_mcdi_highvertfrqflg.
+#define MCDI_FIELD_LUMA_AVG_SUM_0 ((0x2f62 << 2) + 0xff000000)
+//Bit 31: 0, reg_mcdi_fld_luma_avg_sum0.
+#define MCDI_FIELD_LUMA_AVG_SUM_1 ((0x2f63 << 2) + 0xff000000)
+//Bit 31: 0, reg_mcdi_fld_luma_avg_sum1.
+#define MCDI_YCBCR_BLEND_CRTL ((0x2f64 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_mcdi_ycbcrblendgain. ycbcr blending gain for cbcr in ycbcr. default = 0
+//Bit 7: 2, reserved.
+//Bit 1: 0, reg_mcdi_ycbcrblendmode. 0:y+cmb(cb,cr), 1:med(r,g,b), 2:max(r,g,b), default = 2
+#define MCDI_MCVECWR_CANVAS_SIZE ((0x2f65 << 2) + 0xff000000)
+#define MCDI_MCVECRD_CANVAS_SIZE ((0x2f66 << 2) + 0xff000000)
+#define MCDI_MCINFOWR_CANVAS_SIZE ((0x2f67 << 2) + 0xff000000)
+#define MCDI_MCINFORD_CANVAS_SIZE ((0x2f68 << 2) + 0xff000000)
+#define MCDI_MCVECWR_X ((0x2f92 << 2) + 0xff000000)
+#define MCDI_MCVECWR_Y ((0x2f93 << 2) + 0xff000000)
+#define MCDI_MCVECWR_CTRL ((0x2f94 << 2) + 0xff000000)
+#define MCDI_MCVECRD_X ((0x2f95 << 2) + 0xff000000)
+#define MCDI_MCVECRD_Y ((0x2f96 << 2) + 0xff000000)
+#define MCDI_MCVECRD_CTRL ((0x2f97 << 2) + 0xff000000)
+#define MCDI_MCINFOWR_X ((0x2f98 << 2) + 0xff000000)
+#define MCDI_MCINFOWR_Y ((0x2f99 << 2) + 0xff000000)
+#define MCDI_MCINFOWR_CTRL ((0x2f9a << 2) + 0xff000000)
+#define MCDI_MCINFORD_X ((0x2f9b << 2) + 0xff000000)
+#define MCDI_MCINFORD_Y ((0x2f9c << 2) + 0xff000000)
+#define MCDI_MCINFORD_CTRL ((0x2f9d << 2) + 0xff000000)
+#define MCDI_LMVLCKSTEXT_0 ((0x2f69 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, mcdi_lmvlckstext_1 lmv lck blog 1 line start
+//Bit 15:12, reserved
+//Bit 11: 0, mcdi_lmvlckstext_0 lmv lck blog 0 line start
+#define MCDI_LMVLCKSTEXT_1 ((0x2f6a << 2) + 0xff000000)
+//Bit 31 , mcdi_refnewmode new ref me mv array order
+//Bit 30 , mcdi_ref_lmv_lck_en use locked line mvs for ref
+//Bit 29:28, mcdi_lmvlckupdw_ext up/down extend lines for locked lmv line's
+//Bit 27:12, mcdi_lmvlckmin lmv lck blog height limit
+//Bit 15:12, reserved
+//Bit 11: 0, mcdi_lmvlckstext_2 lmv lck blog 2 line start
+#define MCDI_LMVLCKEDEXT_0 ((0x2f6b << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, mcdi_lmvlckedext_1 lmv lck blog 1 line end
+//Bit 15:12, reserved
+//Bit 11: 0, mcdi_lmvlckedext_0 lmv lck blog 0 line end
+#define MCDI_LMVLCKEDEXT_1 ((0x2f6c << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11: 0, mcdi_lmvlckedext_2 lmv lck blog 2 line end
+// ================================================================== MC registers ========================================================================================================
+#define MCDI_MC_CRTL ((0x2f70 << 2) + 0xff000000)
+//Bit 31: 9, reserved
+//Bit 8, reg_mcdi_mcpreflg. flag to use previous field for MC, 0:forward field, 1: previous field, default = 1
+//Bit 7, reg_mcdi_mcrelrefbycolcfden. enable rel refinement by column cofidence in mc blending, default = 1
+//Bit 6: 5, reg_mcdi_mclpfen. enable mc pixles/rel lpf, 0:disable, 1: lpf rel, 2: lpf mc pxls, 3: lpf both rel and mc pxls, default = 0
+//Bit 4: 2, reg_mcdi_mcdebugmode. enable mc debug mode, 0:disable, 1: split left/right, 2: split top/bottom, 3: debug mv, 4: debug rel, default = 0
+//Bit 1: 0, reg_mcdi_mcen. mcdi enable mode, 0:disable, 1: blend with ma, 2: full mc, default = 1
+#define MCDI_MC_LPF_MSK_0 ((0x2f71 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_mcdi_mclpfmsk02. mc lpf coef. 2 for pixel 0 of current block, normalized 16 as '1', default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_mclpfmsk01. mc lpf coef. 1 for pixel 0 of current block, normalized 16 as '1', default = 9
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_mclpfmsk00. mc lpf coef. 0 for pixel 0 of current block, normalized 16 as '1', default = 7
+#define MCDI_MC_LPF_MSK_1 ((0x2f72 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_mcdi_mclpfmsk12. mc lpf coef. 2 for pixel 1 of current block, 0~16, normalized 16 as '1', default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_mclpfmsk11. mc lpf coef. 1 for pixel 1 of current block, 0~16, normalized 16 as '1', default = 11
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_mclpfmsk10. mc lpf coef. 0 for pixel 1 of current block, 0~16, normalized 16 as '1', default = 5
+#define MCDI_MC_LPF_MSK_2 ((0x2f73 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_mcdi_mclpfmsk22. mc lpf coef. 2 for pixel 2 of current block, 0~16, normalized 16 as '1', default = 1
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_mclpfmsk21. mc lpf coef. 1 for pixel 2 of current block, 0~16, normalized 16 as '1', default = 14
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_mclpfmsk20. mc lpf coef. 0 for pixel 2 of current block, 0~16, normalized 16 as '1', default = 1
+#define MCDI_MC_LPF_MSK_3 ((0x2f74 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_mcdi_mclpfmsk32. mc lpf coef. 2 for pixel 3 of current block, 0~16, normalized 16 as '1', default = 5
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_mclpfmsk31. mc lpf coef. 1 for pixel 3 of current block, 0~16, normalized 16 as '1', default = 11
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_mclpfmsk30. mc lpf coef. 0 for pixel 3 of current block, 0~16, normalized 16 as '1', default = 0
+#define MCDI_MC_LPF_MSK_4 ((0x2f75 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_mcdi_mclpfmsk42. mc lpf coef. 2 for pixel 4 of current block, 0~16, normalized 16 as '1', default = 7
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_mclpfmsk41. mc lpf coef. 1 for pixel 4 of current block, 0~16, normalized 16 as '1', default = 9
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_mclpfmsk40. mc lpf coef. 0 for pixel 4 of current block, 0~16, normalized 16 as '1', default = 0
+#define MCDI_MC_REL_GAIN_OFFST_0 ((0x2f76 << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25, reg_mcdi_mcmotionparadoxflg. flag of motion paradox, initial with 0 and read from software, default = 0
+//Bit 24, reg_mcdi_mchighvertfrqflg. flag of high vert frq, initial with 0 and read from software, default = 0
+//Bit 23:16, reg_mcdi_mcmotionparadoxoffst. offset (rel + offset) for rel (MC blending coef.) refinement if motion paradox detected before MC blending before MC blending, default = 128
+//Bit 15:12, reserved
+//Bit 11: 8, reg_mcdi_mcmotionparadoxgain. gain for rel (MC blending coef.) refinement if motion paradox detected before MC blending, normalized 8 as '1', set 15 to 16, default = 8
+//Bit 7: 4, reg_mcdi_mchighvertfrqoffst. minus offset (alpha - offset) for motion (MA blending coef.) refinement if high vertical frequency detected before MA blending, default = 15
+//Bit 3: 0, reg_mcdi_mchighvertfrqgain. gain for motion (MA blending coef.) refinement if high vertical frequency detected before MA blending, normalized 8 as '1', set 15 to 16, default = 8
+#define MCDI_MC_REL_GAIN_OFFST_1 ((0x2f77 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_mcoutofboundrayoffst. offset (rel + offset) for rel (MC blending coef.) refinement if MC pointed out of boundray before MC blending before MC blending, default = 255
+//Bit 23:20, reserved
+//Bit 19:16, reg_mcdi_mcoutofboundraygain. gain for rel (MC blending coef.) refinement if MC pointed out of boundray before MC blending, normalized 8 as '1', set 15 to 16, default = 8
+//Bit 15: 8, reg_mcdi_mcrelrefbycolcfdoffst. offset (rel + offset) for rel (MC blending coef.) refinement if motion paradox detected before MC blending before MC blending, default = 255
+//Bit 7: 4, reserved.
+//Bit 3: 0, reg_mcdi_mcrelrefbycolcfdgain. gain for rel (MC blending coef.) refinement if column cofidence failed before MC blending, normalized 8 as '1', set 15 to 16, default = 8
+#define MCDI_MC_COL_CFD_0 ((0x2f78 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_0. column cofidence value 0 read from software. initial = 0
+#define MCDI_MC_COL_CFD_1 ((0x2f79 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_1. column cofidence value 1 read from software. initial = 0
+#define MCDI_MC_COL_CFD_2 ((0x2f7a << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_2. column cofidence value 2 read from software. initial = 0
+#define MCDI_MC_COL_CFD_3 ((0x2f7b << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_3. column cofidence value 3 read from software. initial = 0
+#define MCDI_MC_COL_CFD_4 ((0x2f7c << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_4. column cofidence value 4 read from software. initial = 0
+#define MCDI_MC_COL_CFD_5 ((0x2f7d << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_5. column cofidence value 5 read from software. initial = 0
+#define MCDI_MC_COL_CFD_6 ((0x2f7e << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_6. column cofidence value 6 read from software. initial = 0
+#define MCDI_MC_COL_CFD_7 ((0x2f7f << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_7. column cofidence value 7 read from software. initial = 0
+#define MCDI_MC_COL_CFD_8 ((0x2f80 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_8. column cofidence value 8 read from software. initial = 0
+#define MCDI_MC_COL_CFD_9 ((0x2f81 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_9. column cofidence value 9 read from software. initial = 0
+#define MCDI_MC_COL_CFD_10 ((0x2f82 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_10. column cofidence value 10 read from software. initial = 0
+#define MCDI_MC_COL_CFD_11 ((0x2f83 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_11. column cofidence value 11 read from software. initial = 0
+#define MCDI_MC_COL_CFD_12 ((0x2f84 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_12. column cofidence value 12 read from software. initial = 0
+#define MCDI_MC_COL_CFD_13 ((0x2f85 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_13. column cofidence value 13 read from software. initial = 0
+#define MCDI_MC_COL_CFD_14 ((0x2f86 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_14. column cofidence value 14 read from software. initial = 0
+#define MCDI_MC_COL_CFD_15 ((0x2f87 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_15. column cofidence value 15 read from software. initial = 0
+#define MCDI_MC_COL_CFD_16 ((0x2f88 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_16. column cofidence value 16 read from software. initial = 0
+#define MCDI_MC_COL_CFD_17 ((0x2f89 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_17. column cofidence value 17 read from software. initial = 0
+#define MCDI_MC_COL_CFD_18 ((0x2f8a << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_18. column cofidence value 18 read from software. initial = 0
+#define MCDI_MC_COL_CFD_19 ((0x2f8b << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_19. column cofidence value 19 read from software. initial = 0
+#define MCDI_MC_COL_CFD_20 ((0x2f8c << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_20. column cofidence value 20 read from software. initial = 0
+#define MCDI_MC_COL_CFD_21 ((0x2f8d << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_21. column cofidence value 21 read from software. initial = 0
+#define MCDI_MC_COL_CFD_22 ((0x2f8e << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_22. column cofidence value 22 read from software. initial = 0
+#define MCDI_MC_COL_CFD_23 ((0x2f8f << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_23. column cofidence value 23 read from software. initial = 0
+#define MCDI_MC_COL_CFD_24 ((0x2f90 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_24. column cofidence value 24 read from software. initial = 0
+#define MCDI_MC_COL_CFD_25 ((0x2f91 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_25. column cofidence value 25 read from software. initial = 0
+// ===================================================================================== PRE RO Registers ==========================================================================================
+#define MCDI_RO_FLD_LUMA_AVG_SUM ((0x2fa0 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldlumaavgsum. block's luma avg sum of current filed (block based). initial = 0
+#define MCDI_RO_GMV_VLD_CNT ((0x2fa1 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_gmvvldcnt. valid gmv's count of pre one filed (block based). initial = 0
+#define MCDI_RO_RPT_FLG_CNT ((0x2fa2 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_rptflgcnt. repeat mv's count of pre one filed (block based). initial = 0
+#define MCDI_RO_FLD_BAD_SAD_CNT ((0x2fa3 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldbadsadcnt. bad sad count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_BAD_BADW_CNT ((0x2fa4 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldbadbadwcnt. bad badw count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_BAD_REL_CNT ((0x2fa5 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldbadrelcnt. bad rel count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_MTN_CNT ((0x2fa6 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldmtncnt. motion count of whole pre one field (pixel based). initial = 0
+#define MCDI_RO_FLD_VLD_CNT ((0x2fa7 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldvldcnt. valid motion count of whole pre one field (pixel based). initial = 0
+#define MCDI_RO_FLD_PD_22_PRE_CNT ((0x2fa8 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22precnt. prevoius pd22 check count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_FOR_CNT ((0x2fa9 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22forcnt. forward pd22 check count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_FLT_CNT ((0x2faa << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22fltcnt. flat count (for pd22 check) of whole pre one field (block based). initial = 0
+#define MCDI_RO_HIGH_VERT_FRQ_FLG ((0x2fab << 2) + 0xff000000)
+//Bit 31:16, reserved.
+//Bit 15: 8, ro_mcdi_highvertfrqcnt. high vertical frequency count till prevoius one field. initial = 0
+//Bit 7: 3, reserved.
+//Bit 2: 1, ro_mcdi_highvertfrqphase. high vertical frequency phase of prevoius one field. initial = 2
+//Bit 0, ro_mcdi_highvertfrqflg. high vertical frequency flag of prevoius one field. initial = 0
+#define MCDI_RO_GMV_LOCK_FLG ((0x2fac << 2) + 0xff000000)
+//Bit 31:16, reserved.
+//Bit 15: 8, ro_mcdi_gmvlckcnt. global mv lock count till prevoius one field. initial = 0
+//Bit 7: 2, ro_mcdi_gmv. global mv of prevoius one field. -31~31, initial = 32 (invalid value)
+//Bit 1, ro_mcdi_zerogmvlckflg. zero global mv lock flag of prevoius one field. initial = 0
+//Bit 0, ro_mcdi_gmvlckflg. global mv lock flag of prevoius one field. initial = 0
+#define MCDI_RO_RPT_MV ((0x2fad << 2) + 0xff000000)
+//Bit 5: 0, ro_mcdi_rptmv. repeate mv of prevoius one field. -31~31, initial = 32 (invalid value)
+#define MCDI_RO_MOTION_PARADOX_FLG ((0x2fae << 2) + 0xff000000)
+//Bit 31:16, reserved.
+//Bit 15: 8, ro_mcdi_motionparadoxcnt. motion paradox count till prevoius one field. initial = 0
+//Bit 7: 1, reserved.
+//Bit 0, ro_mcdi_motionparadoxflg. motion paradox flag of prevoius one field. initial = 0
+#define MCDI_RO_PD_22_FLG ((0x2faf << 2) + 0xff000000)
+//Bit 31:27, reserved.
+//Bit 26, ro_mcdi_pd22flg2. pull down 22 flag of prevoius one field. initial = 0
+//Bit 25, ro_mcdi_pd22flg1. pull down 22 flag of prevoius one field. initial = 0
+//Bit 24, ro_mcdi_pd22flg. pull down 22 flag of prevoius one field. initial = 0
+//Bit 23:16, ro_mcdi_pd22cnt2. pull down 22 count till prevoius one field. initial = 0
+//Bit 15: 8, ro_mcdi_pd22cnt1. pull down 22 count till prevoius one field. initial = 0
+//Bit 7: 0, ro_mcdi_pd22cnt. pull down 22 count till prevoius one field. initial = 0
+#define MCDI_RO_COL_CFD_0 ((0x2fb0 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_0. column cofidence value 0. initial = 0
+#define MCDI_RO_COL_CFD_1 ((0x2fb1 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_1. column cofidence value 1. initial = 0
+#define MCDI_RO_COL_CFD_2 ((0x2fb2 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_2. column cofidence value 2. initial = 0
+#define MCDI_RO_COL_CFD_3 ((0x2fb3 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_3. column cofidence value 3. initial = 0
+#define MCDI_RO_COL_CFD_4 ((0x2fb4 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_4. column cofidence value 4. initial = 0
+#define MCDI_RO_COL_CFD_5 ((0x2fb5 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_5. column cofidence value 5. initial = 0
+#define MCDI_RO_COL_CFD_6 ((0x2fb6 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_6. column cofidence value 6. initial = 0
+#define MCDI_RO_COL_CFD_7 ((0x2fb7 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_7. column cofidence value 7. initial = 0
+#define MCDI_RO_COL_CFD_8 ((0x2fb8 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_8. column cofidence value 8. initial = 0
+#define MCDI_RO_COL_CFD_9 ((0x2fb9 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_9. column cofidence value 9. initial = 0
+#define MCDI_RO_COL_CFD_10 ((0x2fba << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_10. column cofidence value 10. initial = 0
+#define MCDI_RO_COL_CFD_11 ((0x2fbb << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_11. column cofidence value 11. initial = 0
+#define MCDI_RO_COL_CFD_12 ((0x2fbc << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_12. column cofidence value 12. initial = 0
+#define MCDI_RO_COL_CFD_13 ((0x2fbd << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_13. column cofidence value 13. initial = 0
+#define MCDI_RO_COL_CFD_14 ((0x2fbe << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_14. column cofidence value 14. initial = 0
+#define MCDI_RO_COL_CFD_15 ((0x2fbf << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_15. column cofidence value 15. initial = 0
+#define MCDI_RO_COL_CFD_16 ((0x2fc0 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_16. column cofidence value 16. initial = 0
+#define MCDI_RO_COL_CFD_17 ((0x2fc1 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_17. column cofidence value 17. initial = 0
+#define MCDI_RO_COL_CFD_18 ((0x2fc2 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_18. column cofidence value 18. initial = 0
+#define MCDI_RO_COL_CFD_19 ((0x2fc3 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_19. column cofidence value 19. initial = 0
+#define MCDI_RO_COL_CFD_20 ((0x2fc4 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_20. column cofidence value 20. initial = 0
+#define MCDI_RO_COL_CFD_21 ((0x2fc5 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_21. column cofidence value 21. initial = 0
+#define MCDI_RO_COL_CFD_22 ((0x2fc6 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_22. column cofidence value 22. initial = 0
+#define MCDI_RO_COL_CFD_23 ((0x2fc7 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_23. column cofidence value 23. initial = 0
+#define MCDI_RO_COL_CFD_24 ((0x2fc8 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_24. column cofidence value 24. initial = 0
+#define MCDI_RO_COL_CFD_25 ((0x2fc9 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_25. column cofidence value 25. initial = 0
+// add space 8'hd0-8'hef
+//
+// Reading file: dipd_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// using 8'he0-8'hef
+#define DIPD_COMB_CTRL0 ((0x2fd0 << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl0
+#define DIPD_COMB_CTRL1 ((0x2fd1 << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl1
+#define DIPD_COMB_CTRL2 ((0x2fd2 << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl2
+#define DIPD_COMB_CTRL3 ((0x2fd3 << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl3
+#define DIPD_COMB_CTRL4 ((0x2fd4 << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl4
+#define DIPD_COMB_CTRL5 ((0x2fd5 << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl5
+#define DIPD_RO_COMB_0 ((0x2fd6 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_0
+#define DIPD_RO_COMB_1 ((0x2fd7 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_1
+#define DIPD_RO_COMB_2 ((0x2fd8 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_2
+#define DIPD_RO_COMB_3 ((0x2fd9 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_3
+#define DIPD_RO_COMB_4 ((0x2fda << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_4
+#define DIPD_RO_COMB_5 ((0x2fdb << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_5
+#define DIPD_RO_COMB_6 ((0x2fdc << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_6
+#define DIPD_RO_COMB_7 ((0x2fdd << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_7
+#define DIPD_RO_COMB_8 ((0x2fde << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_8
+#define DIPD_RO_COMB_9 ((0x2fdf << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_9
+#define DIPD_RO_COMB_10 ((0x2fe0 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_10
+#define DIPD_RO_COMB_11 ((0x2fe1 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_11
+#define DIPD_RO_COMB_12 ((0x2fe2 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_12
+#define DIPD_RO_COMB_13 ((0x2fe3 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_13
+#define DIPD_RO_COMB_14 ((0x2fe4 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_14
+#define DIPD_RO_COMB_15 ((0x2fe5 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_15
+#define DIPD_RO_COMB_16 ((0x2fe6 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_16
+#define DIPD_RO_COMB_17 ((0x2fe7 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_17
+#define DIPD_RO_COMB_18 ((0x2fe8 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_18
+#define DIPD_RO_COMB_19 ((0x2fe9 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_19
+#define DIPD_RO_COMB_20 ((0x2fea << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_20
+#define DIPD_COMB_CTRL6 ((0x2feb << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl6
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dipd_regs.h
+//
+// addr space 8'hf0-8'hff
+//
+// Reading file: nr3_tnr_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define NR3_MODE ((0x2ff0 << 2) + 0xff000000)
+//Bit 31: 6 reserved
+//Bit 5 reg_nr3_vtxt_mode // unsigned , default = 0 0: avg; 1:MAX
+//Bit 4 reg_3dnr_nr3_cbyy_ignor_coop // unsigned , default = 0 ignore coop condition for cbyy motion decision
+//Bit 3 reg_3dnr_nr3_ybyc_ignor_cnoop // unsigned , default = 0 ignore cnoop condition for ybyc motion decision
+//Bit 2: 0 reg_3dnr_nr3_suremot_txt_mode // unsigned , default = 3 0: cur, 1:p2; 2: (cur+p2)/2; 3/up: min(cur,p2)
+#define NR3_COOP_PARA ((0x2ff1 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:20 reg_3dnr_nr3_coop_mode // unsigned , default = 2 0 original pixel 1: [1 2 1]/4 lpf; 2: [1 2 2 2 1]/8; 3: 3x3 lpf
+//Bit 19:16 reg_3dnr_nr3_coop_ratio // unsigned , default = 8 cur and p2 color oop decision ratio: (avg1<(dif1*ratio/8 + ofst));
+//Bit 15: 8 reg_3dnr_nr3_coop_ofset // signed , default = -1 cur and p2 color oop decision ofst: (avg1<(dif1*ratio/8 + ofst));
+//Bit 7: 0 reg_3dnr_nr3_coop_sat_thrd // unsigned , default = 0 cur and p2 color oop decision min(sat0,sat1) threshold;
+#define NR3_CNOOP_GAIN ((0x2ff2 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:20 reg_3dnr_nr3_cnoop_ratio0 // unsigned , default = 8 cur and p2 color noop decision ratio0: (avg1<(MAX(sat0,sat2)*ratio0/8 + ofst0));
+//Bit 19:16 reg_3dnr_nr3_cnoop_ratio1 // unsigned , default = 8 cur and p2 color noop decision ratio1: (dif1<(MIN(sat0,sat2)*ratio1/8 + ofst1));
+//Bit 15: 8 reg_3dnr_nr3_cnoop_ofset0 // signed , default = 25 cur and p2 color noop decision ofset0: (avg1<(MAX(sat0,sat2)*ratio0/8 + ofst0));
+//Bit 7: 0 reg_3dnr_nr3_cnoop_ofset1 // signed , default = 0 cur and p2 color noop decision ofset1: (dif1<(MIN(sat0,sat2)*ratio1/8 + ofst1));
+#define NR3_YMOT_PARA ((0x2ff3 << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19 reg_3dnr_nr3_ymot_only_en // unsigned , default = 1 enable signal for ignor chroma motion: (ytxt &coop)
+//Bit 18 reg_3dnr_nr3_ymot_only_cmtmode // unsigned , default = 1 0: cmot=ymot; 1: cmot = MIN(ymot, cmot)
+//Bit 17:16 reg_3dnr_nr3_ymot_only_txtmode // unsigned , default = 0 0, min(txt0,txt2); 1, max(txt0,txt2);2, (txt0+txt2)/2; 3: sat(txt0, txt2)
+//Bit 15: 8 reg_3dnr_nr3_ymot_only_txtthrd // unsigned , default = 10 threshold to luma texture to decide use ymot only
+//Bit 7: 0 reg_3dnr_nr3_ymot_only_motthrd // unsigned , default = 30 threshold to luma motion to decide use ymot only
+#define NR3_CMOT_PARA ((0x2ff4 << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19 reg_3dnr_nr3_cmot_only_en // unsigned , default = 1 enable signal for ignor luma motion: (ctxt &cnoop)
+//Bit 18 reg_3dnr_nr3_cmot_only_ymtmode // unsigned , default = 0 0: ymot=cmot+ymot/4; 1: ymot = MIN(ymot, cmot)
+//Bit 17:16 reg_3dnr_nr3_cmot_only_txtmode // unsigned , default = 0 0, min(txt0,txt2); 1, max(txt0,txt2);2, (txt0+txt2)/2; 3: sat(txt0, txt2)
+//Bit 15: 8 reg_3dnr_nr3_cmot_only_txtthrd // unsigned , default = 20 threshold to chroma texture to decide use cmot only
+//Bit 7: 0 reg_3dnr_nr3_cmot_only_motthrd // unsigned , default = 15 threshold to chroma motion to decide use cmot only
+#define NR3_SUREMOT_YGAIN ((0x2ff5 << 2) + 0xff000000)
+//Bit 31:24 reg_3dnr_nr3_suremot_dec_yrate // unsigned , default = 16 (norm 16)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+//Bit 23:16 reg_3dnr_nr3_suremot_dec_yofst // unsigned , default = 12 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+//Bit 15: 8 reg_3dnr_nr3_suremot_frc_ygain // unsigned , default = 64 (norm 8)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+//Bit 7: 0 reg_3dnr_nr3_suremot_frc_yofst // unsigned , default = 20 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+#define NR3_SUREMOT_CGAIN ((0x2ff6 << 2) + 0xff000000)
+//Bit 31:24 reg_3dnr_nr3_suremot_dec_crate // unsigned , default = 34 (norm 16)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+//Bit 23:16 reg_3dnr_nr3_suremot_dec_cofst // unsigned , default = 38 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+//Bit 15: 8 reg_3dnr_nr3_suremot_frc_cgain // unsigned , default = 64 (norm 8)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+//Bit 7: 0 reg_3dnr_nr3_suremot_frc_cofst // unsigned , default = 20 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: nr3_tnr_regs.h
+//
+#define LBUF_TOP_CTRL ((0x2fff << 2) + 0xff000000)
+//bit 23:22 mode_444c422
+//bit 21:20 mode_422c444
+//bit 17 lbuf_fmt444_mode
+//bit 16 lbuf_line5_mode
+//bit 12:0 pre_lbuf_size
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: mcdi_regs.h
+//
+// VPU_VLOCK register (16'h3000 - 16'h30ff)
+//========================================================================
+//
+// Reading file: vpu_vlock_reg.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// ----------------------------
+// VPU_VLOCK 0x30
+// ----------------------------
+// -----------------------------------------------
+// REG_BASE: VPU_VLOCK_VCBUS_BASE = 0x30
+// -----------------------------------------------
+#define VPU_VLOCK_CTRL ((0x3000 << 2) + 0xff000000)
+#define VPU_VLOCK_MISC_CTRL ((0x3001 << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP0_ACCUM_LMT ((0x3002 << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP0_CTRL0 ((0x3003 << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP1_CTRL0 ((0x3004 << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP1_IMISSYNC_MAX ((0x3005 << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP1_IMISSYNC_MIN ((0x3006 << 2) + 0xff000000)
+#define VPU_VLOCK_OVWRITE_ACCUM0 ((0x3007 << 2) + 0xff000000)
+#define VPU_VLOCK_OVWRITE_ACCUM1 ((0x3008 << 2) + 0xff000000)
+#define VPU_VLOCK_OUTPUT0_CAPT_LMT ((0x3009 << 2) + 0xff000000)
+#define VPU_VLOCK_OUTPUT0_PLL_LMT ((0x300a << 2) + 0xff000000)
+#define VPU_VLOCK_OUTPUT1_CAPT_LMT ((0x300b << 2) + 0xff000000)
+#define VPU_VLOCK_OUTPUT1_PLL_LMT ((0x300c << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP1_PHSDIF_TGT ((0x300d << 2) + 0xff000000)
+#define VPU_VLOCK_RO_LOOP0_ACCUM ((0x300e << 2) + 0xff000000)
+#define VPU_VLOCK_RO_LOOP1_ACCUM ((0x300f << 2) + 0xff000000)
+#define VPU_VLOCK_OROW_OCOL_MAX ((0x3010 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_VS_I_DIST ((0x3011 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_VS_O_DIST ((0x3012 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_LINE_PIX_ADJ ((0x3013 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_OUTPUT_00_01 ((0x3014 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_OUTPUT_10_11 ((0x3015 << 2) + 0xff000000)
+#define VPU_VLOCK_MX4096 ((0x3016 << 2) + 0xff000000)
+#define VPU_VLOCK_STBDET_WIN0_WIN1 ((0x3017 << 2) + 0xff000000)
+#define VPU_VLOCK_STBDET_CLP ((0x3018 << 2) + 0xff000000)
+#define VPU_VLOCK_STBDET_ABS_WIN0 ((0x3019 << 2) + 0xff000000)
+#define VPU_VLOCK_STBDET_ABS_WIN1 ((0x301a << 2) + 0xff000000)
+#define VPU_VLOCK_STBDET_SGN_WIN0 ((0x301b << 2) + 0xff000000)
+#define VPU_VLOCK_STBDET_SGN_WIN1 ((0x301c << 2) + 0xff000000)
+#define VPU_VLOCK_ADJ_EN_SYNC_CTRL ((0x301d << 2) + 0xff000000)
+#define VPU_VLOCK_GCLK_EN ((0x301e << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP1_ACCUM_LMT ((0x301f << 2) + 0xff000000)
+#define VPU_VLOCK_RO_M_INT_FRAC ((0x3020 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_PH_DIS ((0x3021 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_PH_ERR ((0x3022 << 2) + 0xff000000)
+#define VPU_VLOCK_LOCK_TH ((0x3023 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_LCK_FRM ((0x3024 << 2) + 0xff000000)
+#define VPU_VLOCK_WIN0_TH ((0x3025 << 2) + 0xff000000)
+#define VPU_VLOCK_WIN0_RATIO ((0x3026 << 2) + 0xff000000)
+#define VPU_VLOCK_WIN0_FILTER_CNTL ((0x3027 << 2) + 0xff000000)
+#define VPU_VLOCK_WIN1_TH ((0x3028 << 2) + 0xff000000)
+#define VPU_VLOCK_WIN1_RATIO ((0x3029 << 2) + 0xff000000)
+#define VPU_VLOCK_WIN1_FILTER_CNTL ((0x302a << 2) + 0xff000000)
+#define VPU_VLOCK_LOCK_TH1 ((0x302b << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP0_ERR_LMT ((0x302c << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP1_ERR_LMT ((0x302d << 2) + 0xff000000)
+#define VPU_VLOCK_ERR_CTRL0 ((0x302e << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_vlock_reg.h
+//
+//
+// Reading file: vpp_partb_reg.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: VPPB_VCBUS_BASE = 0x31
+// -----------------------------------------------
+////=================================================================////
+//// vkeystone
+////=================================================================////
+// 8'h00-8'h17
+//
+// Reading file: vkstone_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VKS_CTRL ((0x3100 << 2) + 0xff000000)
+//Bit 31 reg_vks_en // unsigned , default = 1 enable signal of the vks function
+//Bit 30 reg_vks_scl_mode0 // unsigned , default = 1 : b0 mode of vks ofset mode, 0: offset= offset; 1: offset= offset*step= ofset/scale;
+//Bit 29 reg_vks_scl_mode1 // unsigned , default = 1 : b0 mode of vks ofset mode, 0: offset= offset; 1: offset= offset*step= ofset/scale;
+//Bit 28 reg_vks_fill_mode // unsigned , default = 1 mode of out-of-boundary fill, 0 extension, 1: fill with the fill_value
+//Bit 27:26 reg_vks_row_inp_mode // unsigned , default = 1 , interpolation mode from 16pieces ofset/step to each line ofset and step; 0: linear interpolation; 1: cubic interpolation (using ccoef)
+//Bit 25 reg_vks_border_ext_mode0 // unsigned , default = 0 , extend mode of the border data of luma and chroma, 0: copy the most border one; 1: extropolate the border one
+//Bit 24 reg_vks_border_ext_mode1 // unsigned , default = 0 , extend mode of the border data of luma and chroma, 0: copy the most border one; 1: extropolate the border one
+//Bit 23 reg_vks_obuf_mode0 // unsigned , default = 1 , mode of output buffer left/right side. 0: no precalculate active pixels during output fill region; 1: precaclc active pixels during output fill regions
+//Bit 22 reg_vks_obuf_mode1 // unsigned , default = 1 , mode of output buffer left/right side. 0: no precalculate active pixels during output fill region; 1: precaclc active pixels during output fill regions
+//Bit 21:20 reg_vks_obuf_mrgn0 // unsigned , default = 3 , margin pixels for left right most active pixel to the fill pixels to avoid jump
+//Bit 19:18 reg_vks_obuf_mrgn1 // unsigned , default = 3 , margin pixels for left right most active pixel to the fill pixels to avoid jump
+//Bit 17:16 reg_vks_phs_qmode // unsigned , default = 2 , interpolation mode of the phase, 0: floor to 1/64 phase; 1: round to 1/64 phase; 2/3 linear intp
+//Bit 15: 0 reg_vks_row_scl // unsigned , default = 11651 , scale of row to make it fit to the 16 pieces, scl = (2^23)/RowMax
+#define VKS_OUT_WIN_SIZE ((0x3101 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_vks_ocolmax // unsigned , default = 1280 output outer window col number, decided by the projector
+//Bit 15:14 reserved
+//Bit 13: 0 reg_vks_orowmax // unsigned , default = 720 output outer window row number, decided by the projector
+#define VKS_PRELPF_YCOEF0 ((0x3102 << 2) + 0xff000000)
+//Bit 31:24 reg_vks_prelpf_ycoef0 // signed , default = -128 coef of horizontal luma prelpf for Keystone, normalized 128 as '1'
+//Bit 23:16 reg_vks_prelpf_ycoef1 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1'
+//Bit 15: 8 reg_vks_prelpf_ycoef2 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1'
+//Bit 7: 0 reg_vks_prelpf_ycoef3 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1'
+#define VKS_PRELPF_YCOEF1 ((0x3103 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_vks_prelpf_ycoef4 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1'
+//Bit 7: 0 reg_vks_prelpf_ycoef5 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1'
+#define VKS_PRELPF_CCOEF0 ((0x3104 << 2) + 0xff000000)
+//Bit 31:24 reg_vks_prelpf_ccoef0 // signed , default = -128 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1'
+//Bit 23:16 reg_vks_prelpf_ccoef1 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1'
+//Bit 15: 8 reg_vks_prelpf_ccoef2 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1'
+//Bit 7: 0 reg_vks_prelpf_ccoef3 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1'
+#define VKS_PRELPF_CCOEF1 ((0x3105 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_vks_prelpf_ccoef4 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1'
+//Bit 7: 0 reg_vks_prelpf_ccoef5 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1'
+#define VKS_FILL_VAL ((0x3106 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_vks_fill_value0 // unsigned , default = 0 , border fill color define. yuv: [0 128 128]; rgb:[0 0 0]
+//Bit 15: 8 reg_vks_fill_value1 // unsigned , default = 128 , border fill color define. yuv: [0 128 128]; rgb:[0 0 0]
+//Bit 7: 0 reg_vks_fill_value2 // unsigned , default = 128 , border fill color define. yuv: [0 128 128]; rgb:[0 0 0]
+#define VKS_IWIN_HSIZE ((0x3107 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_vks_iwinx0 // unsigned , default = 160 , input start-col and end-col;
+//Bit 15:14 reserved
+//Bit 13: 0 reg_vks_iwinx1 // unsigned , default = 1279 , input start-col and end-col;
+#define VKS_IWIN_VSIZE ((0x3108 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_vks_iwiny0 // unsigned , default = 0 , input start-row and end-row;
+//Bit 15:14 reserved
+//Bit 13: 0 reg_vks_iwiny1 // unsigned , default = 719 , input start-row and end-row;
+#define VKS_TOP_MISC ((0x3109 << 2) + 0xff000000)
+//Bit 31:19 reserved
+//Bit 18 reg_flt_en // unsigned , default = 1
+//Bit 17 reg_frm_rst // unsigned , default = 0
+//Bit 16 reg_ctrl_sync // unsigned , default = 0
+//Bit 15: 8 blank_num // unsigned , default = 4
+//Bit 7: 0 flt_blank_num // unsigned , default = 9
+#define VKS_START_CTRL ((0x310a << 2) + 0xff000000)
+//Bit 31:17 reserved
+//Bit 16 reg_vks_en_mode // unsigned , default = 0
+//Bit 15: 0 reg_hold_phnum // unsigned , default = 5
+#define VKS_LBUF_SIZE ((0x310b << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11: 0 reg_lbuf_depth // unsigned , default = 1024
+#define VKS_PARA_ADDR_PORT ((0x310e << 2) + 0xff000000)
+#define VKS_PARA_DATA_PORT ((0x310f << 2) + 0xff000000)
+
+ #define VKS_SCL_OFSET00 0x9 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset0 // unsigned , default = 118534 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET01 0xa //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset1 // unsigned , default = 111450 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET02 0xb //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset2 // unsigned , default = 104366 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET03 0xc //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset3 // unsigned , default = 97283 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET04 0xd //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset4 // unsigned , default = 90199 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET05 0xe //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset5 // unsigned , default = 83115 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET06 0xf //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset6 // unsigned , default = 76031 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET07 0x10 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset7 // unsigned , default = 68947 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET08 0x11 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset8 // unsigned , default = 61864 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET09 0x12 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset9 // unsigned , default = 54780 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET10 0x13 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset10 // unsigned , default = 47696 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET11 0x14 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset11 // unsigned , default = 40612 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET12 0x15 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset12 // unsigned , default = 33528 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET13 0x16 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset13 // unsigned , default = 26444 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET14 0x17 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset14 // unsigned , default = 19361 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET15 0x18 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset15 // unsigned , default = 12277 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET16 0x19 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset16 // unsigned , default = 5193 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_STEP00 0x1a //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step0 // unsigned , default = 331378 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP01 0x1b //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step1 // unsigned , default = 383191 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP02 0x1c //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step2 // unsigned , default = 435004 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP03 0x1d //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step3 // unsigned , default = 486818 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP04 0x1e //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step4 // unsigned , default = 538631 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP05 0x1f //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step5 // unsigned , default = 590444 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP06 0x20 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step6 // unsigned , default = 642257 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP07 0x21 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step7 // unsigned , default = 694070 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP08 0x22 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step8 // unsigned , default = 745884 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP09 0x23 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step9 // unsigned , default = 797697 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP10 0x24 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step10 // unsigned , default = 849510 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP11 0x25 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step11 // unsigned , default = 901323 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP12 0x26 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step12 // unsigned , default = 953136 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP13 0x27 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step13 // unsigned , default = 1004949 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP14 0x28 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step14 // unsigned , default = 1056763 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP15 0x29 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step15 // unsigned , default = 1108576 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP16 0x2a //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step16 // unsigned , default = 1160389 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_PPS_YCOEF00 0x2b //
+//Bit 31:24 reg_vks_ycoef0 // signed , default = 0 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef1 // signed , default = 128 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef2 // signed , default = 0 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef3 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF01 0x2c //
+//Bit 31:24 reg_vks_ycoef4 // signed , default = 0 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef5 // signed , default = 127 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef6 // signed , default = 1 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef7 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF02 0x2d //
+//Bit 31:24 reg_vks_ycoef8 // signed , default = -1 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef9 // signed , default = 127 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef10 // signed , default = 2 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef11 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF03 0x2e //
+//Bit 31:24 reg_vks_ycoef12 // signed , default = -2 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef13 // signed , default = 127 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef14 // signed , default = 3 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef15 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF04 0x2f //
+//Bit 31:24 reg_vks_ycoef16 // signed , default = -3 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef17 // signed , default = 126 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef18 // signed , default = 5 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef19 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF05 0x30 //
+//Bit 31:24 reg_vks_ycoef20 // signed , default = -4 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef21 // signed , default = 126 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef22 // signed , default = 6 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef23 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF06 0x31 //
+//Bit 31:24 reg_vks_ycoef24 // signed , default = -5 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef25 // signed , default = 125 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef26 // signed , default = 8 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef27 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF07 0x32 //
+//Bit 31:24 reg_vks_ycoef28 // signed , default = -5 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef29 // signed , default = 124 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef30 // signed , default = 9 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef31 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF08 0x33 //
+//Bit 31:24 reg_vks_ycoef32 // signed , default = -6 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef33 // signed , default = 123 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef34 // signed , default = 11 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef35 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF09 0x34 //
+//Bit 31:24 reg_vks_ycoef36 // signed , default = -6 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef37 // signed , default = 122 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef38 // signed , default = 13 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef39 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF10 0x35 //
+//Bit 31:24 reg_vks_ycoef40 // signed , default = -7 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef41 // signed , default = 121 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef42 // signed , default = 15 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef43 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF11 0x36 //
+//Bit 31:24 reg_vks_ycoef44 // signed , default = -7 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef45 // signed , default = 119 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef46 // signed , default = 17 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef47 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF12 0x37 //
+//Bit 31:24 reg_vks_ycoef48 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef49 // signed , default = 118 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef50 // signed , default = 19 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef51 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF13 0x38 //
+//Bit 31:24 reg_vks_ycoef52 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef53 // signed , default = 116 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef54 // signed , default = 22 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef55 // signed , default = -2 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF14 0x39 //
+//Bit 31:24 reg_vks_ycoef56 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef57 // signed , default = 114 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef58 // signed , default = 24 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef59 // signed , default = -2 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF15 0x3a //
+//Bit 31:24 reg_vks_ycoef60 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef61 // signed , default = 112 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef62 // signed , default = 26 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef63 // signed , default = -2 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF16 0x3b //
+//Bit 31:24 reg_vks_ycoef64 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef65 // signed , default = 111 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef66 // signed , default = 29 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef67 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF17 0x3c //
+//Bit 31:24 reg_vks_ycoef68 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef69 // signed , default = 109 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef70 // signed , default = 31 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef71 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF18 0x3d //
+//Bit 31:24 reg_vks_ycoef72 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef73 // signed , default = 107 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef74 // signed , default = 33 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef75 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF19 0x3e //
+//Bit 31:24 reg_vks_ycoef76 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef77 // signed , default = 104 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef78 // signed , default = 36 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef79 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF20 0x3f //
+//Bit 31:24 reg_vks_ycoef80 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef81 // signed , default = 102 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef82 // signed , default = 39 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef83 // signed , default = -4 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF21 0x40 //
+//Bit 31:24 reg_vks_ycoef84 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef85 // signed , default = 100 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef86 // signed , default = 41 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef87 // signed , default = -4 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF22 0x41 //
+//Bit 31:24 reg_vks_ycoef88 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef89 // signed , default = 97 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef90 // signed , default = 44 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef91 // signed , default = -4 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF23 0x42 //
+//Bit 31:24 reg_vks_ycoef92 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef93 // signed , default = 95 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef94 // signed , default = 47 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef95 // signed , default = -5 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF24 0x43 //
+//Bit 31:24 reg_vks_ycoef96 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef97 // signed , default = 93 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef98 // signed , default = 49 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef99 // signed , default = -5 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF25 0x44 //
+//Bit 31:24 reg_vks_ycoef100 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef101 // signed , default = 90 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef102 // signed , default = 52 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef103 // signed , default = -5 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF26 0x45 //
+//Bit 31:24 reg_vks_ycoef104 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef105 // signed , default = 88 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef106 // signed , default = 55 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef107 // signed , default = -6 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF27 0x46 //
+//Bit 31:24 reg_vks_ycoef108 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef109 // signed , default = 85 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef110 // signed , default = 58 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef111 // signed , default = -6 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF28 0x47 //
+//Bit 31:24 reg_vks_ycoef112 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef113 // signed , default = 82 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef114 // signed , default = 60 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef115 // signed , default = -6 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF29 0x48 //
+//Bit 31:24 reg_vks_ycoef116 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef117 // signed , default = 80 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef118 // signed , default = 63 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef119 // signed , default = -7 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF30 0x49 //
+//Bit 31:24 reg_vks_ycoef120 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef121 // signed , default = 77 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef122 // signed , default = 66 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef123 // signed , default = -7 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF31 0x4a //
+//Bit 31:24 reg_vks_ycoef124 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef125 // signed , default = 74 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef126 // signed , default = 69 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef127 // signed , default = -7 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF32 0x4b //
+//Bit 31:24 reg_vks_ycoef128 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef129 // signed , default = 72 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef130 // signed , default = 72 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef131 // signed , default = -8 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF00 0x4c //
+//Bit 31:24 reg_vks_ccoef0 // signed , default = 0 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef1 // signed , default = 128 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef2 // signed , default = 0 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef3 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF01 0x4d //
+//Bit 31:24 reg_vks_ccoef4 // signed , default = 0 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef5 // signed , default = 127 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef6 // signed , default = 1 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef7 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF02 0x4e //
+//Bit 31:24 reg_vks_ccoef8 // signed , default = -1 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef9 // signed , default = 127 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef10 // signed , default = 2 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef11 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF03 0x4f //
+//Bit 31:24 reg_vks_ccoef12 // signed , default = -2 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef13 // signed , default = 127 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef14 // signed , default = 3 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef15 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF04 0x50 //
+//Bit 31:24 reg_vks_ccoef16 // signed , default = -3 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef17 // signed , default = 126 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef18 // signed , default = 5 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef19 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF05 0x51 //
+//Bit 31:24 reg_vks_ccoef20 // signed , default = -4 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef21 // signed , default = 126 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef22 // signed , default = 6 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef23 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF06 0x52 //
+//Bit 31:24 reg_vks_ccoef24 // signed , default = -5 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef25 // signed , default = 125 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef26 // signed , default = 8 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef27 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF07 0x53 //
+//Bit 31:24 reg_vks_ccoef28 // signed , default = -5 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef29 // signed , default = 124 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef30 // signed , default = 9 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef31 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF08 0x54 //
+//Bit 31:24 reg_vks_ccoef32 // signed , default = -6 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef33 // signed , default = 123 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef34 // signed , default = 11 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef35 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF09 0x55 //
+//Bit 31:24 reg_vks_ccoef36 // signed , default = -6 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef37 // signed , default = 122 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef38 // signed , default = 13 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef39 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF10 0x56 //
+//Bit 31:24 reg_vks_ccoef40 // signed , default = -7 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef41 // signed , default = 121 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef42 // signed , default = 15 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef43 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF11 0x57 //
+//Bit 31:24 reg_vks_ccoef44 // signed , default = -7 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef45 // signed , default = 119 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef46 // signed , default = 17 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef47 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF12 0x58 //
+//Bit 31:24 reg_vks_ccoef48 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef49 // signed , default = 118 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef50 // signed , default = 19 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef51 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF13 0x59 //
+//Bit 31:24 reg_vks_ccoef52 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef53 // signed , default = 116 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef54 // signed , default = 22 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef55 // signed , default = -2 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF14 0x5a //
+//Bit 31:24 reg_vks_ccoef56 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef57 // signed , default = 114 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef58 // signed , default = 24 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef59 // signed , default = -2 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF15 0x5b //
+//Bit 31:24 reg_vks_ccoef60 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef61 // signed , default = 112 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef62 // signed , default = 26 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef63 // signed , default = -2 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF16 0x5c //
+//Bit 31:24 reg_vks_ccoef64 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef65 // signed , default = 111 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef66 // signed , default = 29 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef67 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF17 0x5d //
+//Bit 31:24 reg_vks_ccoef68 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef69 // signed , default = 109 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef70 // signed , default = 31 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef71 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF18 0x5e //
+//Bit 31:24 reg_vks_ccoef72 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef73 // signed , default = 107 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef74 // signed , default = 33 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef75 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF19 0x5f //
+//Bit 31:24 reg_vks_ccoef76 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef77 // signed , default = 104 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef78 // signed , default = 36 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef79 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF20 0x60 //
+//Bit 31:24 reg_vks_ccoef80 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef81 // signed , default = 102 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef82 // signed , default = 39 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef83 // signed , default = -4 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF21 0x61 //
+//Bit 31:24 reg_vks_ccoef84 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef85 // signed , default = 100 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef86 // signed , default = 41 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef87 // signed , default = -4 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF22 0x62 //
+//Bit 31:24 reg_vks_ccoef88 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef89 // signed , default = 97 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef90 // signed , default = 44 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef91 // signed , default = -4 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF23 0x63 //
+//Bit 31:24 reg_vks_ccoef92 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef93 // signed , default = 95 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef94 // signed , default = 47 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef95 // signed , default = -5 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF24 0x64 //
+//Bit 31:24 reg_vks_ccoef96 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef97 // signed , default = 93 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef98 // signed , default = 49 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef99 // signed , default = -5 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF25 0x65 //
+//Bit 31:24 reg_vks_ccoef100 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef101 // signed , default = 90 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef102 // signed , default = 52 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef103 // signed , default = -5 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF26 0x66 //
+//Bit 31:24 reg_vks_ccoef104 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef105 // signed , default = 88 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef106 // signed , default = 55 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef107 // signed , default = -6 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF27 0x67 //
+//Bit 31:24 reg_vks_ccoef108 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef109 // signed , default = 85 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef110 // signed , default = 58 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef111 // signed , default = -6 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF28 0x68 //
+//Bit 31:24 reg_vks_ccoef112 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef113 // signed , default = 82 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef114 // signed , default = 60 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef115 // signed , default = -6 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF29 0x69 //
+//Bit 31:24 reg_vks_ccoef116 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef117 // signed , default = 80 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef118 // signed , default = 63 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef119 // signed , default = -7 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF30 0x6a //
+//Bit 31:24 reg_vks_ccoef120 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef121 // signed , default = 77 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef122 // signed , default = 66 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef123 // signed , default = -7 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF31 0x6b //
+//Bit 31:24 reg_vks_ccoef124 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef125 // signed , default = 74 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef126 // signed , default = 69 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef127 // signed , default = -7 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF32 0x6c //
+//Bit 31:24 reg_vks_ccoef128 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef129 // signed , default = 72 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef130 // signed , default = 72 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef131 // signed , default = -8 poly-phase scalar coefs
+
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vkstone_regs.h
+//
+////=================================================================////
+//// vpp dither
+////=================================================================////
+// 8'h20-8'h3f
+//
+// Reading file: vpp_dither_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VPP_VE_DITHER_CTRL ((0x3120 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_1 ((0x3121 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_2 ((0x3122 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_3 ((0x3123 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_4 ((0x3124 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_5 ((0x3125 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_6 ((0x3126 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_7 ((0x3127 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_8 ((0x3128 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_9 ((0x3129 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_10 ((0x312a << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_11 ((0x312b << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_12 ((0x312c << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_CTRL ((0x3130 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_1 ((0x3131 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_2 ((0x3132 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_3 ((0x3133 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_4 ((0x3134 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_5 ((0x3135 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_6 ((0x3136 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_7 ((0x3137 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_8 ((0x3138 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_9 ((0x3139 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_10 ((0x313a << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_11 ((0x313b << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_12 ((0x313c << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_dither_regs.h
+//
+// 8'h40-8'h4f
+//
+// Reading file: osdsc_deband_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define OSD_DB_FLT_CTRL ((0x3140 << 2) + 0xff000000)
+//Bit 31:27 reserved
+//Bit 26 reg_nrdeband_reset1 // unsigned , default = 1 , 0 : no reload chrm seed 1: reload chrm seed
+//Bit 25 reg_nrdeband_reset0 // unsigned , default = 1 , 0 : no reload luma seed 1: reload luma seed
+//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 , 0 : yuv 1: RGB
+//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
+//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
+//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
+//Bit 16 reserved
+//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
+//Bit 12 reserved
+//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6
+//Bit 8 reserved
+//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 , debanding random hp portion xor, [0] for luma
+//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 , debanding random hp portion xor, [1] for chroma
+//Bit 5 reg_nrdeband_en1 // unsigned , default = 0 , debanding registers, for luma
+//Bit 4 reg_nrdeband_en0 // unsigned , default = 0 , debanding registers, for chroma
+//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+#define OSD_DB_FLT_CTRL1 ((0x3141 << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:16 reg_nrdeband_noise_rs // unsigned , default = 2
+//Bit 15:12 reg_nrdeband_randgain // unsigned , default = 8
+//Bit 11 reserved
+//Bit 10: 8 reg_nrdeband_bandrand5 // unsigned , default = 6
+//Bit 7 reserved
+//Bit 6: 4 reg_nrdeband_bandrand4 // unsigned , default = 6
+//Bit 3 reserved
+//Bit 2: 0 reg_nrdeband_bandrand3 // unsigned , default = 6
+#define OSD_DB_FLT_LUMA_THRD ((0x3142 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_luma_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_luma_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_luma_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_luma_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else
+#define OSD_DB_FLT_CHRM_THRD ((0x3143 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_chrm_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_chrm_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_chrm_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_chrm_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif
+#define OSD_DB_FLT_RANDLUT ((0x3144 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:21 reg_nrdeband_randslut7 // unsigned , default = 1 rand lut7
+//Bit 20:18 reg_nrdeband_randslut6 // unsigned , default = 1 rand lut6
+//Bit 17:15 reg_nrdeband_randslut5 // unsigned , default = 1 rand lut5
+//Bit 14:12 reg_nrdeband_randslut4 // unsigned , default = 1 rand lut4
+//Bit 11: 9 reg_nrdeband_randslut3 // unsigned , default = 1 rand lut3
+//Bit 8: 6 reg_nrdeband_randslut2 // unsigned , default = 1 rand lut2
+//Bit 5: 3 reg_nrdeband_randslut1 // unsigned , default = 1 rand lut1
+//Bit 2: 0 reg_nrdeband_randslut0 // unsigned , default = 1 rand lut0
+#define OSD_DB_FLT_PXI_THRD ((0x3145 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+//Bit 15:10 reserved
+//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+#define OSD_DB_FLT_SEED_Y ((0x3146 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 ,debanding noise adding seed for Y. seed[0]= 0x60a52f20; as default
+#define OSD_DB_FLT_SEED_U ((0x3147 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 ,debanding noise adding seed for U. seed[0]= 0x60a52f27; as default
+#define OSD_DB_FLT_SEED_V ((0x3148 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD_DB_FLT_SEED3 ((0x3149 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed3 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD_DB_FLT_SEED4 ((0x314a << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed4 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD_DB_FLT_SEED5 ((0x314b << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed5 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: osdsc_deband_regs.h
+//
+//register definition for xvycc
+// 8'h50-8'h7f
+//
+// Reading file: xvycc_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define XVYCC_INV_LUT_Y_ADDR_PORT ((0x3158 << 2) + 0xff000000)
+//Bit 31:7, reserved
+//Bit 6:0, xvycc_inv_lut_y_addr;
+#define XVYCC_INV_LUT_Y_DATA_PORT ((0x3159 << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, xvycc_inv_lut_y_data;
+#define XVYCC_INV_LUT_U_ADDR_PORT ((0x315a << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, xvycc_inv_lut_u_addr;
+#define XVYCC_INV_LUT_U_DATA_PORT ((0x315b << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, xvycc_inv_lut_u_data;
+#define XVYCC_INV_LUT_V_ADDR_PORT ((0x315c << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, xvycc_inv_lut_v_addr;
+#define XVYCC_INV_LUT_V_DATA_PORT ((0x315d << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, xvycc_inv_lut_v_data;
+#define XVYCC_LUT_R_ADDR_PORT ((0x315e << 2) + 0xff000000)
+//Bit 31:7, reserved
+//Bit 6:0, xvycc_lut_r_addr;
+#define XVYCC_LUT_R_DATA_PORT ((0x315f << 2) + 0xff000000)
+//Bit 31:10, reserved
+//Bit 9:0, xvycc_lut_r_data;
+#define XVYCC_LUT_G_ADDR_PORT ((0x3160 << 2) + 0xff000000)
+//Bit 31:7, reserved
+//Bit 6:0, xvycc_lut_g_addr;
+#define XVYCC_LUT_G_DATA_PORT ((0x3161 << 2) + 0xff000000)
+//Bit 31:10, reserved
+//Bit 9:0, xvycc_lut_g_data;
+#define XVYCC_LUT_B_ADDR_PORT ((0x3162 << 2) + 0xff000000)
+//Bit 31:7, reserved
+//Bit 6:0, xvycc_lut_b_addr;
+#define XVYCC_LUT_B_DATA_PORT ((0x3163 << 2) + 0xff000000)
+//Bit 31:10, reserved
+//Bit 9:0, xvycc_lut_b_data;
+#define XVYCC_INV_LUT_CTL ((0x3164 << 2) + 0xff000000)
+//Bit 31:15, reserved
+//Bit 14:12, reg_xvycc_cmpr_invlut_enable enable for xvycc compression inverse-lut [2] for Y, [1] for U, [0] for V default=0
+//Bit 11:10, reg_xvycc_cmpr_invlut_vscl_1 v LUT input scale for positive portion default=0
+//Bit 9: 8, reg_xvycc_cmpr_invlut_vscl_0 v LUT input scale for negative portion default=0
+//Bit 7: 6, reg_xvycc_cmpr_invlut_uscl_1 u LUT input scale for positive portion default=0
+//Bit 5: 4, reg_xvycc_cmpr_invlut_uscl_0 u LUT input scale for negative portion default=0
+//Bit 3: 2, reg_xvycc_cmpr_invlut_yscl_1 y LUT input scale for positive portion default=0
+//Bit 1: 0, reg_xvycc_cmpr_invlut_yscl_0 y LUT input scale for negative portion default=0
+#define XVYCC_LUT_CTL ((0x3165 << 2) + 0xff000000)
+//Bit 31: 7, reserved
+//Bit 6: 4, reg_xvycc_lut_enable LUT enable [6] for R, [5] for G, [4] for B default=0
+//Bit 3: 2, reg_xvycc_lut_scl_1 LUT input scale for positive portion default=0
+//Bit 1: 0, reg_xvycc_lut_scl_0 LUT input scale for negative portion default=0
+#define XVYCC_VADJ1_CURV_0 ((0x3166 << 2) + 0xff000000)
+//Bit 31:24, vadj1_softcon_curv0_ci default=0
+//Bit 23:12, vadj1_softcon_curv0_b default=0
+//Bit 11: 0, vadj1_softcon_curv0_a default=0
+#define XVYCC_VADJ1_CURV_1 ((0x3167 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12: 4, vadj1_softcon_curv0_g default=0
+//Bit 3, reserved
+//Bit 2: 0, vadj1_softcon_curv0_cs default=0
+#define XVYCC_VADJ1_CURV_2 ((0x3168 << 2) + 0xff000000)
+//Bit 31:24, vadj1_softcon_curv1_ci default=0
+//Bit 23:12, vadj1_softcon_curv1_b default=0
+//Bit 11: 0, vadj1_softcon_curv1_a default=0
+#define XVYCC_VADJ1_CURV_3 ((0x3169 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12: 4, vadj1_softcon_curv1_g default=0
+//Bit 3, reserved
+//Bit 2: 0, vadj1_softcon_curv1_cs default=0
+#define XVYCC_VADJ2_CURV_0 ((0x316a << 2) + 0xff000000)
+//Bit 31:24, vadj2_softcon_curv0_ci default=0
+//Bit 23:12, vadj2_softcon_curv0_b default=0
+//Bit 11: 0, vadj2_softcon_curv0_a default=0
+#define XVYCC_VADJ2_CURV_1 ((0x316b << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12: 4, vadj2_softcon_curv0_g default=0
+//Bit 3, reserved
+//Bit 2: 0, vadj2_softcon_curv0_cs default=0
+#define XVYCC_VADJ2_CURV_2 ((0x316c << 2) + 0xff000000)
+//Bit 31:24, vadj2_softcon_curv1_ci default=0
+//Bit 23:12, vadj2_softcon_curv1_b default=0
+//Bit 11: 0, vadj2_softcon_curv1_a default=0
+#define XVYCC_VADJ2_CURV_3 ((0x316d << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12: 4, vadj2_softcon_curv1_g default=0
+//Bit 3, reserved
+//Bit 2: 0, vadj2_softcon_curv1_cs default=0
+#define XVYCC_VD1_RGB_CTRST ((0x3170 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, reg_vd1_rgb_ctrst u12, contrast in rgb. default=1024
+//Bit 15:14, reserved
+//Bit 13: 4, reg_vd1_rgb_ctrst_blklvl u10, contrast blacklevel default=64
+//Bit 3: 2, reserved
+//Bit 1, reg_vd1_rgbbst_en u1, enable rgbbst default=0
+//Bit 0, reg_vd1_rgb_ctrst_prt u1, enable signal to protect saturation in rgb. default=1
+#define XVYCC_VD1_RGB_BRGHT ((0x3171 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 4, reg_vd1_rgb_brght s12, brightness level in rgb domain default=0
+//Bit 3: 2, reserved
+//Bit 1, reg_vd1_rgb_brght_prt u1, enalbe signal to protect saturation in rgb default=1
+//Bit 0, reg_vd1_rgbbst_dlut_x2 u1, enable signal to do x2 to the dlut cells before subtracting default=0
+#define XVYCC_VD1_RGB_DLUT_0_3 ((0x3172 << 2) + 0xff000000)
+//Bit 31:24, reg_vd1_rgbbst_dlut0 u8, default = 255
+//Bit 23:16, reg_vd1_rgbbst_dlut1 u8, default = 205
+//Bit 15: 8, reg_vd1_rgbbst_dlut2 u8, default = 171
+//Bit 7: 0, reg_vd1_rgbbst_dlut3 u8, default = 147
+#define XVYCC_VD1_RGB_DLUT_4_7 ((0x3173 << 2) + 0xff000000)
+//Bit 31:24, reg_vd1_rgbbst_dlut4 u8, default = 128
+//Bit 23:16, reg_vd1_rgbbst_dlut5 u8, default = 113
+//Bit 15: 8, reg_vd1_rgbbst_dlut6 u8, default = 102
+//Bit 7: 0, reg_vd1_rgbbst_dlut7 u8, default = 93
+#define XVYCC_VD1_RGB_DLUT_8_11 ((0x3174 << 2) + 0xff000000)
+//Bit 31:24, reg_vd1_rgbbst_dlut8 u8, default = 85
+//Bit 23:16, reg_vd1_rgbbst_dlut9 u8, default = 78
+//Bit 15: 8, reg_vd1_rgbbst_dlut10 u8, default = 73
+//Bit 7: 0, reg_vd1_rgbbst_dlut11 u8, default = 68
+#define XVYCC_POST_RGB_CTRST ((0x3175 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, reg_post_rgb_ctrst u12, contrast in rgb. default=1024
+//Bit 15:14, reserved
+//Bit 13: 4, reg_post_rgb_ctrst_blklvl u10, contrast blacklevel default=64
+//Bit 3: 2, reserved
+//Bit 1, reg_post_rgbbst_en u1, enable rgbbst default=0
+//Bit 0, reg_post_rgb_ctrst_prt u1, enable signal to protect saturation in rgb. default=1
+#define XVYCC_POST_RGB_BRGHT ((0x3176 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 4, reg_post_rgb_brght s12, brightness level in rgb domain default=0
+//Bit 3: 2, reserved
+//Bit 1, reg_post_rgb_brght_prt u1, enalbe signal to protect saturation in rgb default=1
+//Bit 0, reg_post_rgbbst_dlut_x2 u1, enable signal to do x2 to the dlut cells before subtracting default=0
+#define XVYCC_POST_RGB_DLUT_0_3 ((0x3177 << 2) + 0xff000000)
+//Bit 31:24, reg_post_rgbbst_dlut0 u8, default = 255
+//Bit 23:16, reg_post_rgbbst_dlut1 u8, default = 205
+//Bit 15: 8, reg_post_rgbbst_dlut2 u8, default = 171
+//Bit 7: 0, reg_post_rgbbst_dlut3 u8, default = 147
+#define XVYCC_POST_RGB_DLUT_4_7 ((0x3178 << 2) + 0xff000000)
+//Bit 31:24, reg_post_rgbbst_dlut4 u8, default = 128
+//Bit 23:16, reg_post_rgbbst_dlut5 u8, default = 113
+//Bit 15: 8, reg_post_rgbbst_dlut6 u8, default = 102
+//Bit 7: 0, reg_post_rgbbst_dlut7 u8, default = 93
+#define XVYCC_POST_RGB_DLUT_8_11 ((0x3179 << 2) + 0xff000000)
+//Bit 31:24, reg_post_rgbbst_dlut8 u8, default = 85
+//Bit 23:16, reg_post_rgbbst_dlut9 u8, default = 78
+//Bit 15: 8, reg_post_rgbbst_dlut10 u8, default = 73
+//Bit 7: 0, reg_post_rgbbst_dlut11 u8, default = 68
+#define ADAPTIVE_SCALE_REG0 ((0x3150 << 2) + 0xff000000)
+//Bit 31, reg_adaptive_scale_enable u1, default = 1
+//Bit 27:16, reg_adpscl_ys_coef_0 u12, default = 538
+//Bit 11: 0, reg_adpscl_ys_coef_1 u12, default = 1389
+#define ADAPTIVE_SCALE_REG1 ((0x3151 << 2) + 0xff000000)
+//Bit 27:16, reg_adpscl_ys_coef_2 u12, default = 121
+//Bit 11: 0, reg_adpscl_alpha_0 u12, default = 1024
+#define ADAPTIVE_SCALE_REG2 ((0x3152 << 2) + 0xff000000)
+//Bit 27:16, reg_adpscl_alpha_1 u12, default = 1024
+//Bit 11: 0, reg_adpscl_alpha_2 u12, default = 1024
+#define ADAPTIVE_SCALE_REG3 ((0x3153 << 2) + 0xff000000)
+//Bit 31:16, reg_adpscl_beta_0 u16, default = 0
+//Bit 15: 0, reg_adpscl_beta_1 u16, default = 0
+#define ADAPTIVE_SCALE_REG4 ((0x3154 << 2) + 0xff000000)
+//Bit 31:16, reg_adpscl_beta_2 u16, default = 0
+#define ADAPTIVE_SCALE_ADDR ((0x3155 << 2) + 0xff000000)
+//Bit 6:0, reg_lut_addr u7, default = 0
+#define ADAPTIVE_SCALE_DATA ((0x3156 << 2) + 0xff000000)
+//Bit 11:0, reg_lut_data u12, default = 0
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: xvycc_regs.h
+//
+//register definition for vd2 afbc dec
+// 8'h80-8'h9f
+//
+// Reading file: vd2_afbc_dec_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+//// reg
+////===============================////
+#define VD2_AFBC_ENABLE ((0x3180 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:23, reg_gclk_ctrl_core unsigned, default = 0
+//Bit 22, reg_fmt_size_sw_mode unsigned, default = 0, 0:hw mode 1:sw mode for format size
+//Bit 21, reg_addr_link_en unsigned, default = 1, 1:enable
+//Bit 20, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb
+//Bit 19, reg_dos_uncomp_mode unsigned , default = 0
+//Bit 18:16, soft_rst unsigned , default = 4
+//Bit 15:14, reserved
+//Bit 13:12, ddr_blk_size unsigned , default = 1
+//Bit 11:9, cmd_blk_size unsigend , default = 3
+//Bit 8, dec_enable unsigned , default = 0
+//Bit 7:2, reserved
+//Bit 1, head_len_sel unsigned , default = 1
+//Bit 0, dec_frm_start unsigned , default = 0
+#define VD2_AFBC_MODE ((0x3181 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29, ddr_sz_mode uns, default = 0 , 0: fixed block ddr size 1 : unfixed block ddr size;
+//Bit 28, blk_mem_mode uns, default = 0 , 0: fixed 16x128 size; 1 : fixed 12x128 size
+//Bit 27:26, rev_mode uns, default = 0 , reverse mode
+//Bit 25:24, mif_urgent uns, default = 3 , info mif and data mif urgent
+//Bit 23, reserved
+//Bit 22:16, hold_line_num uns, default = 4 ,
+//Bit 15:14, burst_len uns, default = 2, 0: burst1 1:burst2 2:burst4
+//Bit 13:8, compbits_yuv uns, default = 0 ,
+// bit 1:0,: y component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+// bit 3:2,: u component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+// bit 5:4,: v component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+//Bit 7:6, vert_skip_y uns, default = 0 , luma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 5:4, horz_skip_y uns, default = 0 , luma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 3:2, vert_skip_uv uns, default = 0 , chroma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 1:0, horz_skip_uv uns, default = 0 , chroma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+#define VD2_AFBC_SIZE_IN ((0x3182 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hsize_in uns, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_in uns, default = 1080 , pic vert size in unit: pixel
+#define VD2_AFBC_DEC_DEF_COLOR ((0x3183 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:20, def_color_y uns, default = 255, afbc dec y default setting value
+//Bit 19:10, def_color_u uns, default = 128, afbc dec u default setting value
+//Bit 9: 0, def_color_v uns, default = 128, afbc dec v default setting value
+#define VD2_AFBC_CONV_CTRL ((0x3184 << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13:12, fmt_mode uns, default = 2, 0:yuv444 1:yuv422 2:yuv420
+//Bit 11: 0, conv_lbuf_len uns, default = 256, unit=16 pixel need to set = 2^n
+#define VD2_AFBC_LBUF_DEPTH ((0x3185 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, dec_lbuf_depth uns, default = 128; // unit= 8 pixel
+//Bit 15:12, reserved
+//Bit 11:0, mif_lbuf_depth uns, default = 128;
+#define VD2_AFBC_HEAD_BADDR ((0x3186 << 2) + 0xff000000)
+//Bit 31:0, mif_info_baddr uns, default = 32'h0;
+#define VD2_AFBC_BODY_BADDR ((0x3187 << 2) + 0xff000000)
+//Bit 31:0, mif_data_baddr uns, default = 32'h00010000;
+#define VD2_AFBC_SIZE_OUT ((0x3188 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, hsize_out uns, default = 1920 ; // unit: 1 pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_out uns, default = 1080 ; // unit: 1 pixel
+#define VD2_AFBC_OUT_YSCOPE ((0x3189 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, out_vert_bgn uns, default = 0 ; // unit: 1 pixel
+//Bit 15:13, reserved
+//Bit 12:0, out_vert_end uns, default = 1079 ; // unit: 1 pixel
+#define VD2_AFBC_STAT ((0x318a << 2) + 0xff000000)
+//Bit 31:0, ro_dbg_top_info uns
+#define VD2_AFBC_VD_CFMT_CTRL ((0x318b << 2) + 0xff000000)
+//Bit 31 cfmt_gclk_bit_dis uns, default = 0 ; // it true, disable clock, otherwise enable clock
+//Bit 30 cfmt_soft_rst_bit uns, default = 0 ; // soft rst bit
+//Bit 29 reserved
+//Bit 28 chfmt_rpt_pix uns, default = 0 ; // if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
+//Bit 27:24 chfmt_ini_phase uns, default = 0 ; // horizontal formatter initial phase
+//Bit 23 chfmt_rpt_p0_en uns, default = 0 ; // horizontal formatter repeat pixel 0 enable
+//Bit 22:21 chfmt_yc_ratio uns, default = 0 ; // horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
+//Bit 20 chfmt_en uns, default = 0 ; // horizontal formatter enable
+//Bit 19 cvfmt_phase0_always_en uns, default = 0 ; //if true, always use phase0 while vertical formater, meaning always
+// repeat data, no interpolation
+//Bit 18 cvfmt_rpt_last_dis uns, default = 0 ; //if true, disable vertical formatter chroma repeat last line
+//Bit 17 cvfmt_phase0_nrpt_en uns, default = 0 ; //veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable
+//Bit 16 cvfmt_rpt_line0_en uns, default = 0 ; //veritcal formatter repeat line 0 enable
+//Bit 15:12 cvfmt_skip_line_num uns, default = 0 ; //vertical formatter skip line num at the beginning
+//Bit 11:8 cvfmt_ini_phase uns, default = 0 ; //vertical formatter initial phase
+//Bit 7:1 cvfmt_phase_step uns, default = 0 ; //vertical formatter phase step (3.4)
+//Bit 0 cvfmt_en uns, default = 0 ; //vertical formatter enable
+#define VD2_AFBC_VD_CFMT_W ((0x318c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 chfmt_w uns, default = 0 ;horizontal formatter width
+//Bit 15:13 reserved
+//Bit 12:0 cvfmt_w uns, default = 0 ;vertical formatter width
+#define VD2_AFBC_MIF_HOR_SCOPE ((0x318d << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, mif_blk_bgn_h uns, default = 0 ; // unit: 32 pixel/block hor
+//Bit 15:10, reserved
+//Bit 9: 0, mif_blk_end_h uns, default = 59 ; // unit: 32 pixel/block hor
+#define VD2_AFBC_MIF_VER_SCOPE ((0x318e << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, mif_blk_bgn_v uns, default = 0 ; // unit: 32 pixel/block ver
+//Bit 15:12, reserved
+//Bit 11: 0, mif_blk_end_v uns, default = 269; // unit: 32 pixel/block ver
+#define VD2_AFBC_PIXEL_HOR_SCOPE ((0x318f << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, dec_pixel_bgn_h uns, default = 0 ; // unit: pixel
+//Bit 15:13, reserved
+//Bit 12: 0, dec_pixel_end_h uns, default = 1919 ; // unit: pixel
+#define VD2_AFBC_PIXEL_VER_SCOPE ((0x3190 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, dec_pixel_bgn_v uns, default = 0 ; // unit: pixel
+//Bit 15:13, reserved
+//Bit 12: 0, dec_pixel_end_v uns, default = 1079 ; // unit: pixel
+#define VD2_AFBC_VD_CFMT_H ((0x3191 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12:0 cfmt_h uns, default = 142 ; //vertical formatter height
+#define VD2_AFBCDEC_IQUANT_ENABLE ((0x3192 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_quant_expand_en_1 //unsigned, RW, enable for quantization value expansion
+//Bit 10 reg_quant_expand_en_0 //unsigned, RW, enable for quantization value expansion
+//Bit 9: 8 reg_bcleav_ofst // signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1;
+//Bit 7: 5 reserved
+//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy
+//Bit 3: 1 reserved
+//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy
+#define VD2_AFBCDEC_IQUANT_LUT_1 ((0x3193 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define VD2_AFBCDEC_IQUANT_LUT_2 ((0x3194 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define VD2_AFBCDEC_IQUANT_LUT_3 ((0x3195 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define VD2_AFBCDEC_IQUANT_LUT_4 ((0x3196 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vd2_afbc_dec_regs.h
+//
+//register definition for osd1 afbcd dec
+// 8'ha0-8'haf
+//
+// Reading file: osd1_afbcd_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+//// reg
+////===============================////
+#define OSD1_AFBCD_ENABLE ((0x31a0 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:9, id_fifo_thrd unsigned , default = 64, axi id fifo threshold
+//Bit 8, dec_enable unsigned , default = 0
+//Bit 7:1, reserved
+//Bit 0, frm_start unsigned , default = 0
+#define OSD1_AFBCD_MODE ((0x31a1 << 2) + 0xff000000)
+//Bit 31, soft_reset the use as go_field
+//Bit 30:29, reserved
+//Bit 28, axi_reorder_mode default=0, the axi reorder mode, note : don't seting
+//Bit 27:26, reserved
+//Bit 25:24, mif_urgent uns, default = 3 , info mif and data mif urgent
+//Bit 22:16, hold_line_num
+//Bit 15:8, rgba_exchan_ctrl
+//Bit 7, reserved
+//Bit 6, hreg_block_split uns, default = 1 , Enable/disable block split mode in sparse allocation
+//Bit 5, hreg_half_block uns, default = 1 , Enable/disable half block decoding. 1=half block, 0=full block
+//Bit 4:0, hreg_pixel_packing_fmt uns, default = 5 , Pixel format
+#define OSD1_AFBCD_SIZE_IN ((0x31a2 << 2) + 0xff000000)
+//Bit 31:16 hreg_hsize_in uns, default = 1920 , pic horz size in unit: pixel
+//Bit 15:0, hreg_vsize_in uns, default = 1080 , pic vert size in unit: pixel
+#define OSD1_AFBCD_HDR_PTR ((0x31a3 << 2) + 0xff000000)
+//Bit 31:0 hreg_hdr_ptr uns, default = 0 ,
+#define OSD1_AFBCD_FRAME_PTR ((0x31a4 << 2) + 0xff000000)
+//Bit 31:0 hreg_frame_ptr uns, default = 0 , The start address of the target frame buffer.
+// For YUV format, this pointer specifies the luma buffer.
+#define OSD1_AFBCD_CHROMA_PTR ((0x31a5 << 2) + 0xff000000)
+//Bit 31:0 hreg_chroma_ptr uns, default = 0 , Only valid in YUV format, to specify the target chroma buffer.
+#define OSD1_AFBCD_CONV_CTRL ((0x31a6 << 2) + 0xff000000)
+//Bit 31:15, reserved
+//Bit 15: 0, conv_lbuf_len uns, default = 1024, unit=16 pixel need to set = 2^n
+#define OSD1_AFBCD_STATUS ((0x31a8 << 2) + 0xff000000)
+//Bit 30:4, reserved
+//Bit 3, hreg_dec_resp uns, default = 0 , Decoder error flage from the dec4x4 core
+//Bit 2, hreg_axi_bresp uns, default = 0 , Bus error flag for AXI write error
+//Bit 1, hreg_axi_rresp uns, default = 0 , Bus error flag for AXI read error
+//Bit 0, hreg_idle_n uns, default = 0 , Idle output, value 0 indicates the standalone decoder is free now and can start the next frame.
+#define OSD1_AFBCD_PIXEL_HSCOPE ((0x31a9 << 2) + 0xff000000)
+//Bit 31:16, dec_pixel_bgn_h uns, default = 0 ; // unit: pixel
+//Bit 15: 0, dec_pixel_end_h uns, default = 1919 ; // unit: pixel
+#define OSD1_AFBCD_PIXEL_VSCOPE ((0x31aa << 2) + 0xff000000)
+//Bit 31:16, dec_pixel_bgn_v uns, default = 0 ; // unit: pixel
+//Bit 15: 0, dec_pixel_end_v uns, default = 1079 ; // unit: pixel
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: osd1_afbcd_regs.h
+//
+//register definition for osd1 afbcd dec
+// 8'hb0-8'hca
+//
+// Reading file: vpp_vmx_wm_regs.h
+//
+//// synopsys translate_off
+//`ifdef VPP_WM_REGS_H
+//`else
+// `define VPP_WM_REGS_H
+//// synopsys translate_on
+#define WM_CTRL ((0x31b0 << 2) + 0xff000000)
+//Bit 31, int_mask default = 0
+//Bit 30:16, reserved
+//Bit 15:8, strength_multiply default =1
+//Bit 7:6, reserved
+//Bit 5, shift_en default = 0
+//Bit 4, background_embedding_on default =0
+//Bit 3, mark_en default =0
+//Bit 2, noise_en default =0
+//Bit 1, blend_en default =0
+//Bit 0, wm_en default =0
+#define WM_SPACE_RESOLUTION ((0x31b1 << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24:16, spacing_horz default =10
+//Bit 15:9, reserved
+//Bit 8:0, spacing_vert default =12
+#define WM_SYMBOLS_NUM ((0x31b2 << 2) + 0xff000000)
+//Bit 31:8, reserved
+//Bit 7:4, symbols_cols 1~10; default =5
+//Bit 3:0, symbols_rows 1~10; default =2
+#define WM_MARK_RESOLUTION ((0x31b3 << 2) + 0xff000000)
+//Bit 31:20, mark_hsize mark_buffer_width; default =1820
+//Bit 19:8, mark_vsize mark_buffer_height; default =1820 t =780
+//Bit 7:6, reserved
+//Bit 5:0, scale default =13 // scale up
+#define WM_FREQ_DIST_LEFT ((0x31b4 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:0, freq_dist_left default =21092 // frequency_distance [n][0] each is 7bits, there is 3 dist
+#define WM_FREQ_DIST_RIGHT ((0x31b5 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:0, freq_dist_right default =21092 // frequency_distance [n][0] each is 7bits, there is 3 dist
+#define WM_FREQ_DIST_TOP ((0x31b6 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:0, freq_dist_top default =21092 // frequency_distance [n][0] each is 7bits, there is 3 dist
+#define WM_SYMBOLS_XPOS ((0x31b7 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, symbols_xpos_start default =1536 // SYMBOLS_XPOS * h_res
+//Bit 15:13, reserved
+//Bit 12:0, symbols_xpos_end default =3356 // SYMBOLS_XPOS * h_res + mark_hsize
+#define WM_SYMBOLS_YPOS ((0x31b8 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, symbols_ypos_start default =756 // SYMBOLS_yPOS * y_res
+//Bit 15:13, reserved
+//Bit 12:0, symbols_ypos_end default =1536 // SYMBOLS_yPOS * y_res + mark_vsize
+#define WM_STORAGE_SETTING ((0x31b9 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, direction_max default = 80
+//Bit 15, reserved
+//Bit 14:8, storage_s default =18 // biggest is 72 S
+//Bit 7, reserved
+//Bit 6:0, storage_max_distance default =36 // biggest is 72 max_distance
+#define WM_VIDEO_RESOLUTION ((0x31ba << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, h_res default =3840 // video hsize
+//Bit 15:13, reserved
+//Bit 12:0, v_res default =2160 // video vsize
+#define WM_EMBEDDING_STRENGTH_THRESHOLD0 ((0x31bb << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_0 default =48
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_1 default =60
+#define WM_EMBEDDING_STRENGTH_THRESHOLD1 ((0x31bc << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_2 default = 68
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_3 default = 80
+#define WM_EMBEDDING_STRENGTH_THRESHOLD2 ((0x31bd << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_4 default = 88
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_5 default = 96
+#define WM_EMBEDDING_STRENGTH_THRESHOLD3 ((0x31be << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_6 default = 100
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_7 default = 108
+#define WM_EMBEDDING_STRENGTH_THRESHOLD4 ((0x31bf << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_8 default = 112
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_9 default = 116
+#define WM_EMBEDDING_STRENGTH_THRESHOLD5 ((0x31c0 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_10 default = 120
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_11 default = 124
+#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG0 ((0x31c1 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_bg_0 default =320
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_bg_1 default = 328
+#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG1 ((0x31c2 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_bg_2 default = 332
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_bg_3 default = 340
+#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG2 ((0x31c3 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_bg_4 default = 344
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_bg_5 default = 348
+#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG3 ((0x31c4 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_bg_6 default = 352
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_bg_7 default = 356
+#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG4 ((0x31c5 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_bg_8 default = 360
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_bg_9 default = 368
+#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG5 ((0x31c6 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_bg_10 default = 372
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_bg_11 default = 380
+#define WM_AM_LUT_DATA_PORT ((0x31c7 << 2) + 0xff000000)
+#define WM_AM_LUT_ADDR_PORT ((0x31c8 << 2) + 0xff000000)
+#define WM_STATUS_RO ((0x31c9 << 2) + 0xff000000)
+//Bit 31, ro_resolution_changed
+//Bit 30:29, reserved
+//Bit 30:16, ro_hsize_in
+//Bit 15:13, reserved
+//Bit 8:0, ro_vsize_in
+#define WM_STATUS_RAM_RO ((0x31ca << 2) + 0xff000000)
+//Bit 31:9, reserved
+//Bit 8:0, ro_ram_addr
+#define WM_THRES_ADDR_PORT ((0x31cb << 2) + 0xff000000)
+#define WM_THRES_DATA_PORT ((0x31cd << 2) + 0xff000000)
+//
+// Closing file: vpp_vmx_wm_regs.h
+//
+//
+// Reading file: ngptv_reg.h
+//
+//// synopsys translate_off
+//`ifdef VPP_WM_REGS_H
+//`else
+// `define VPP_WM_REGS_H
+//// synopsys translate_on
+#define REG_NGPTV_CTRL0 ((0x31ab << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24, bypass_latch
+//Bit 23, count_enable deafult=1
+//Bit 22, soft_rst
+//Bit 21, count_rst
+//Bit 20, bypass run
+//Bit 19:14, ochannel_sel deafult=0x24
+//Bit 13:8, ichannel_sel deafult=0x24
+//Bit 3, 8bit mode
+//Bit 2, 10bit mode
+//Bit 1, reg_sync enable
+//Bit 0, bypass
+#define REG_NGPTV_CTRL1 ((0x31ac << 2) + 0xff000000)
+//Bit 31:7 reserved
+//Bit 6 reset sw default=0
+//Bit 5:0 gclk_ctrl
+#define REG_NGPTV_CTRL2 ((0x31ad << 2) + 0xff000000)
+//Bit 31:8 reserved
+//Bit 7 SpareIn
+//Bit 6 NG_EnableServiceIn
+//Bit 5:4 reserved
+//Bit 3 NG_DebugEnableIn
+//Bit 2 reserved
+//Bit 1 NG_Payload24_56n
+//Bit 0 NG_YUVnRGBIn
+#define REG_NGPTV_CTRL3 ((0x31ce << 2) + 0xff000000)
+//Bit 31:0 NG_KeyIn default=0x01ac7f33
+#define REG_NGPTV_CTRL4 ((0x31cf << 2) + 0xff000000)
+//Bit 31:0 NG_PayloadDataIn[31:0] default=0x6789abcd
+#define REG_NGPTV_CTRL5 ((0x31f0 << 2) + 0xff000000)
+//Bit 31:26 Reserved
+//Bit 25:24 NG_FrameTypeIn default=3
+//Bit 23:0 NG_PayloadDataIn default=0x012345
+#define REG_NGPTV_CTRL6 ((0x31f1 << 2) + 0xff000000)
+//Bit 31:0 NG_SettingIn[31:0] default=0x18c6318c
+#define REG_NGPTV_CTRL7 ((0x31f2 << 2) + 0xff000000)
+//Bit 31:0 NG_SettingIn[63:32] default=0x84210842
+#define REG_NGPTV_CTRL8 ((0x31f3 << 2) + 0xff000000)
+//Bit 31:0 NG_SettingIn[95:64] default=0x21084210
+#define REG_NGPTV_CTRL9 ((0x31f4 << 2) + 0xff000000)
+//Bit 31:0 NG_SettingIn[127:96] default=0x8c631084
+#define REG_NGPTV_CTRL10 ((0x31f5 << 2) + 0xff000000)
+//Bit 31:0 NG_SettingIn[159:128] default=0x84210631
+#define REG_NGPTV_CTRL11 ((0x31f6 << 2) + 0xff000000)
+//Bit 31:16 Reserved
+//Bit 15:8 NG_FrameRateIn default=0x18
+//Bit 7 Reserved
+//Bit 6:5 NG_CoreIDIn default=0
+//Bit 4:0 NG_SettingIn[165:160] default=0x10
+#define REG_NGPTV_CTRL12 ((0x31f7 << 2) + 0xff000000)
+//Bit 31:29 Reserved
+//Bit 28:16 vsize default=0x438
+//Bit 16:13 Reserved
+//Bit 12:0 hsize default=0x780
+#define REG_NGPTV_CTRL13 ((0x31f8 << 2) + 0xff000000)
+//Bit 31:29 Reserved
+//Bit 28:16 reg_vphstart default=0x0
+//Bit 16:13 Reserved
+//Bit 12:0 reg_vphend default=0x437
+#define REG_NGPTV_CTRL14 ((0x31f9 << 2) + 0xff000000)
+//Bit 31:13 Reserved
+//Bit 12:0 reg_3d_right_st default=0x3c0
+#define REG_NGPTV_CTRL15 ((0x31fa << 2) + 0xff000000)
+//Bit 31:29 Reserved
+//Bit 28:16 reg_vpvstart0 default=0x0
+//Bit 16:13 Reserved
+//Bit 12:0 reg_vpvend0 default=0x437
+#define REG_NGPTV_CTRL16 ((0x31fb << 2) + 0xff000000)
+//Bit 31:29 Reserved
+//Bit 28:16 reg_vpvstart1 default=0
+//Bit 16:13 Reserved
+//Bit 12:0 reg_vpvend1 default=0
+#define REG_NGPTV_CTRL17 ((0x31fc << 2) + 0xff000000)
+//Bit 31:29 Reserved
+//Bit 28:16 reg_vpvstart2 default=0
+//Bit 16:13 Reserved
+//Bit 12:0 reg_vpvend2 default=0
+#define REG_NGPTV_CTRL18 ((0x31fd << 2) + 0xff000000)
+//Bit 31:29 Reserved
+//Bit 28:16 reg_vpvstart3 default=0
+//Bit 16:13 Reserved
+//Bit 12:0 reg_vpvend3 default=0
+#define RO_NGPTV_CTRL19 ((0x31fe << 2) + 0xff000000)
+//Bit 31 dat_val_in
+//Bit 30 in_hold
+//Bit 29 out_hold
+//Bit 28:16 vcnt
+//Bit 15:12 NG_ErrorOut
+//Bit 11:0 NG_VersionOut
+//
+// Closing file: ngptv_reg.h
+//
+// 8'hd0-8hef
+//
+// Reading file: bt2020_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//Bit 31:27 for all [31] for all eotf enable,[30] for matrix3x3 enable, [29:27] for eotf_ch0~3
+//Bit 17:6 for clock gating
+//Bit 5:4 pscale_mode ch2
+//Bit 3:2 pscale_mode ch1
+//Bit 1:0 pscale_mode ch0
+#define VPP_EOTF_CTL ((0x31d0 << 2) + 0xff000000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define VPP_EOTF_COEF00_01 ((0x31d1 << 2) + 0xff000000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define VPP_EOTF_COEF02_10 ((0x31d2 << 2) + 0xff000000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define VPP_EOTF_COEF11_12 ((0x31d3 << 2) + 0xff000000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define VPP_EOTF_COEF20_21 ((0x31d4 << 2) + 0xff000000)
+//Bit 28:16 coef22
+//Bit 2:0 coef_rs
+#define VPP_EOTF_COEF22_RS ((0x31d5 << 2) + 0xff000000)
+#define VPP_EOTF_LUT_ADDR_PORT ((0x31d6 << 2) + 0xff000000)
+#define VPP_EOTF_LUT_DATA_PORT ((0x31d7 << 2) + 0xff000000)
+#define VPP_EOTF_3X3_OFST_0 ((0x31d8 << 2) + 0xff000000)
+#define VPP_EOTF_3X3_OFST_1 ((0x31d9 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: bt2020_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_partb_reg.h
+//
+// -----------------------------------------------
+// REG_BASE: VPPD_VCBUS_BASE = 0x32
+// -----------------------------------------------
+//
+// Reading file: vpp_vadj_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//------------------------------------------------------------------------------
+// VD1 path
+//------------------------------------------------------------------------------
+//`define VD1_IF0_GEN_REG 8'h0
+//`define VD1_IF0_CANVAS0 8'h1
+//`define VD1_IF0_CANVAS1 8'h2
+//`define VD1_IF0_LUMA_X0 8'h3
+//`define VD1_IF0_LUMA_Y0 8'h4
+//`define VD1_IF0_CHROMA_X0 8'h5
+//`define VD1_IF0_CHROMA_Y0 8'h6
+//`define VD1_IF0_LUMA_X1 8'h7
+//`define VD1_IF0_LUMA_Y1 8'h8
+//`define VD1_IF0_CHROMA_X1 8'h9
+//`define VD1_IF0_CHROMA_Y1 8'ha
+//`define VD1_IF0_RPT_LOOP 8'hb
+//`define VD1_IF0_LUMA0_RPT_PAT 8'hc
+//`define VD1_IF0_CHROMA0_RPT_PAT 8'hd
+//`define VD1_IF0_LUMA1_RPT_PAT 8'he
+//`define VD1_IF0_CHROMA1_RPT_PAT 8'hf
+//`define VD1_IF0_LUMA_PSEL 8'h10
+//`define VD1_IF0_CHROMA_PSEL 8'h11
+//`define VD1_IF0_DUMMY_PIXEL 8'h12
+//`define VD1_IF0_LUMA_FIFO_SIZE 8'h13
+//`define VD1_IF0_AXI_CMD_CNT 8'h14
+//`define VD1_IF0_AXI_RDAT_CNT 8'h15
+//`define VD1_IF0_GEN_REG3 8'h16
+//Bit 31 it true, disable clock, otherwise enable clock
+//Bit 30 soft rst bit
+//Bit 28 if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
+//Bit 27:24 horizontal formatter initial phase
+//Bit 23 horizontal formatter repeat pixel 0 enable
+//Bit 22:21 horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
+//Bit 20 horizontal formatter enable
+//Bit 19 if true, always use phase0 while vertical formater, meaning always
+// repeat data, no interpolation
+//Bit 18 if true, disable vertical formatter chroma repeat last line
+//Bit 17 veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable
+//Bit 16 veritcal formatter repeat line 0 enable
+//Bit 15:12 vertical formatter skip line num at the beginning
+//Bit 11:8 vertical formatter initial phase
+//Bit 7:1 vertical formatter phase step (3.4)
+//Bit 0 vertical formatter enable
+//`define VIU_VD1_FMT_CTRL 8'h18 //29'h0
+//Bit 27:16 horizontal formatter width
+//Bit 11:0 vertical formatter width
+//`define VIU_VD1_FMT_W 8'h19 //28'h0
+//`define VD1_IF0_RANGE_MAP_Y 8'h1a
+//`define VD1_IF0_RANGE_MAP_CB 8'h1b
+//`define VD1_IF0_RANGE_MAP_CR 8'h1c
+//`define VD1_IF0_GEN_REG2 8'h1d
+//`define VD1_IF0_PROT_CNTL 8'h1e
+//`define VD1_IF0_URGENT_CTRL 8'h1f
+//------------------------------------------------------------------------------
+// VD2 path
+//------------------------------------------------------------------------------
+//`define VD2_IF0_GEN_REG 8'h20
+//`define VD2_IF0_CANVAS0 8'h21
+//`define VD2_IF0_CANVAS1 8'h22
+//`define VD2_IF0_LUMA_X0 8'h23
+//`define VD2_IF0_LUMA_Y0 8'h24
+//`define VD2_IF0_CHROMA_X0 8'h25
+//`define VD2_IF0_CHROMA_Y0 8'h26
+//`define VD2_IF0_LUMA_X1 8'h27
+//`define VD2_IF0_LUMA_Y1 8'h28
+//`define VD2_IF0_CHROMA_X1 8'h29
+//`define VD2_IF0_CHROMA_Y1 8'h2a
+//`define VD2_IF0_RPT_LOOP 8'h2b
+//`define VD2_IF0_LUMA0_RPT_PAT 8'h2c
+//`define VD2_IF0_CHROMA0_RPT_PAT 8'h2d
+//`define VD2_IF0_LUMA1_RPT_PAT 8'h2e
+//`define VD2_IF0_CHROMA1_RPT_PAT 8'h2f
+//`define VD2_IF0_LUMA_PSEL 8'h30
+//`define VD2_IF0_CHROMA_PSEL 8'h31
+//`define VD2_IF0_DUMMY_PIXEL 8'h32
+//`define VD2_IF0_LUMA_FIFO_SIZE 8'h33
+//`define VD2_IF0_AXI_CMD_CNT 8'h34
+//`define VD2_IF0_AXI_RDAT_CNT 8'h35
+//`define VD2_IF0_GEN_REG3 8'h36
+//Bit 31 it true, disable clock, otherwise enable clock
+//Bit 30 soft rst bit
+//Bit 28 if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
+//Bit 27:24 horizontal formatter initial phase
+//Bit 23 horizontal formatter repeat pixel 0 enable
+//Bit 22:21 horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
+//Bit 20 horizontal formatter enable
+//Bit 17 veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable
+//Bit 16 veritcal formatter repeat line 0 enable
+//Bit 15:12 vertical formatter skip line num at the beginning
+//Bit 11:8 vertical formatter initial phase
+//Bit 7:1 vertical formatter phase step (3.4)
+//Bit 0 vertical formatter enable
+//`define VIU_VD2_FMT_CTRL 8'h38 //29'h0
+//Bit 27:16 horizontal formatter width
+//Bit 11:0 vertical formatter width
+//`define VIU_VD2_FMT_W 8'h39 //28'h0
+//`define VD2_IF0_RANGE_MAP_Y 8'h3a
+//`define VD2_IF0_RANGE_MAP_CB 8'h3b
+//`define VD2_IF0_RANGE_MAP_CR 8'h3c
+//`define VD2_IF0_GEN_REG2 8'h3d
+//`define VD2_IF0_PROT_CNTL 8'h3e
+//`define VD2_IF0_URGENT_CTRL 8'h3f
+#define VPP_VADJ1_MISC ((0x3280 << 2) + 0xff000000)
+#define VPP_VADJ1_BLACK_VAL ((0x3281 << 2) + 0xff000000)
+#define VPP_VADJ1_Y ((0x3282 << 2) + 0xff000000)
+#define VPP_VADJ1_MA_MB ((0x3283 << 2) + 0xff000000)
+#define VPP_VADJ1_MC_MD ((0x3284 << 2) + 0xff000000)
+#define VPP_VADJ1_CURV_0 ((0x3285 << 2) + 0xff000000)
+#define VPP_VADJ1_CURV_1 ((0x3286 << 2) + 0xff000000)
+#define VPP_VADJ1_CURV_2 ((0x3287 << 2) + 0xff000000)
+#define VPP_VADJ1_CURV_3 ((0x3288 << 2) + 0xff000000)
+#define VPP_VD1_RGB_CTRST ((0x3289 << 2) + 0xff000000)
+#define VPP_VD1_RGB_BRGHT ((0x328a << 2) + 0xff000000)
+#define VPP_VD1_RGB_DLUT_0_3 ((0x328b << 2) + 0xff000000)
+#define VPP_VD1_RGB_DLUT_4_7 ((0x328c << 2) + 0xff000000)
+#define VPP_VD1_RGB_DLUT_8_11 ((0x328d << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF00_01 ((0x3290 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF02_10 ((0x3291 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF11_12 ((0x3292 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF20_21 ((0x3293 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF22 ((0x3294 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF13_14 ((0x3295 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF23_24 ((0x3296 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF15_25 ((0x3297 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_CLIP ((0x3298 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_OFFSET0_1 ((0x3299 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_OFFSET2 ((0x329a << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_PRE_OFFSET0_1 ((0x329b << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_PRE_OFFSET2 ((0x329c << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_EN_CTRL ((0x329d << 2) + 0xff000000)
+#define VPP_VADJ2_MISC ((0x32a0 << 2) + 0xff000000)
+#define VPP_VADJ2_BLACK_VAL ((0x32a1 << 2) + 0xff000000)
+#define VPP_VADJ2_Y ((0x32a2 << 2) + 0xff000000)
+#define VPP_VADJ2_MA_MB ((0x32a3 << 2) + 0xff000000)
+#define VPP_VADJ2_MC_MD ((0x32a4 << 2) + 0xff000000)
+#define VPP_VADJ2_CURV_0 ((0x32a5 << 2) + 0xff000000)
+#define VPP_VADJ2_CURV_1 ((0x32a6 << 2) + 0xff000000)
+#define VPP_VADJ2_CURV_2 ((0x32a7 << 2) + 0xff000000)
+#define VPP_VADJ2_CURV_3 ((0x32a8 << 2) + 0xff000000)
+#define VPP_POST_RGB_CTRST ((0x32a9 << 2) + 0xff000000)
+#define VPP_POST_RGB_BRGHT ((0x32aa << 2) + 0xff000000)
+#define VPP_POST_RGB_DLUT_0_3 ((0x32ab << 2) + 0xff000000)
+#define VPP_POST_RGB_DLUT_4_7 ((0x32ac << 2) + 0xff000000)
+#define VPP_POST_RGB_DLUT_8_11 ((0x32ad << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF00_01 ((0x32b0 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF02_10 ((0x32b1 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF11_12 ((0x32b2 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF20_21 ((0x32b3 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF22 ((0x32b4 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF13_14 ((0x32b5 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF23_24 ((0x32b6 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF15_25 ((0x32b7 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_CLIP ((0x32b8 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_OFFSET0_1 ((0x32b9 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_OFFSET2 ((0x32ba << 2) + 0xff000000)
+#define VPP_POST_MATRIX_PRE_OFFSET0_1 ((0x32bb << 2) + 0xff000000)
+#define VPP_POST_MATRIX_PRE_OFFSET2 ((0x32bc << 2) + 0xff000000)
+#define VPP_POST_MATRIX_EN_CTRL ((0x32bd << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_SAT ((0x32c0 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_SAT ((0x32c1 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_vadj_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: DOLBY1A_VCBUS_BASE = 0x33
+// -----------------------------------------------
+//
+// Reading file: dolby1a_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DOLBY_CORE1A_REG_START ((0x3300 << 2) + 0xff000000)
+#define DOLBY_CORE1A_CLKGATE_CTRL ((0x33f2 << 2) + 0xff000000)
+#define DOLBY_CORE1A_SWAP_CTRL0 ((0x33f3 << 2) + 0xff000000)
+#define DOLBY_CORE1A_SWAP_CTRL1 ((0x33f4 << 2) + 0xff000000)
+#define DOLBY_CORE1A_SWAP_CTRL2 ((0x33f5 << 2) + 0xff000000)
+#define DOLBY_CORE1A_SWAP_CTRL3 ((0x33f6 << 2) + 0xff000000)
+#define DOLBY_CORE1A_SWAP_CTRL4 ((0x33f7 << 2) + 0xff000000)
+#define DOLBY_CORE1A_SWAP_CTRL5 ((0x33f8 << 2) + 0xff000000)
+#define DOLBY_CORE1A_DMA_CTRL ((0x33f9 << 2) + 0xff000000)
+#define DOLBY_CORE1A_DMA_STATUS ((0x33fa << 2) + 0xff000000)
+#define DOLBY_CORE1A_STATUS0 ((0x33fb << 2) + 0xff000000)
+#define DOLBY_CORE1A_STATUS1 ((0x33fc << 2) + 0xff000000)
+#define DOLBY_CORE1A_STATUS2 ((0x33fd << 2) + 0xff000000)
+#define DOLBY_CORE1A_STATUS3 ((0x33fe << 2) + 0xff000000)
+#define DOLBY_CORE1A_DMA_PORT ((0x33ff << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dolby1a_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: DOLBY2A_VCBUS_BASE = 0x34
+// -----------------------------------------------
+//
+// Reading file: dolby2a_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DOLBY_CORE2A_REG_START ((0x3400 << 2) + 0xff000000)
+#define DOLBY_CORE2A_CLKGATE_CTRL ((0x3432 << 2) + 0xff000000)
+#define DOLBY_CORE2A_SWAP_CTRL0 ((0x3433 << 2) + 0xff000000)
+#define DOLBY_CORE2A_SWAP_CTRL1 ((0x3434 << 2) + 0xff000000)
+#define DOLBY_CORE2A_SWAP_CTRL2 ((0x3435 << 2) + 0xff000000)
+#define DOLBY_CORE2A_SWAP_CTRL3 ((0x3436 << 2) + 0xff000000)
+#define DOLBY_CORE2A_SWAP_CTRL4 ((0x3437 << 2) + 0xff000000)
+#define DOLBY_CORE2A_SWAP_CTRL5 ((0x3438 << 2) + 0xff000000)
+#define DOLBY_CORE2A_DMA_CTRL ((0x3439 << 2) + 0xff000000)
+#define DOLBY_CORE2A_DMA_STATUS ((0x343a << 2) + 0xff000000)
+#define DOLBY_CORE2A_STATUS0 ((0x343b << 2) + 0xff000000)
+#define DOLBY_CORE2A_STATUS1 ((0x343c << 2) + 0xff000000)
+#define DOLBY_CORE2A_STATUS2 ((0x343d << 2) + 0xff000000)
+#define DOLBY_CORE2A_STATUS3 ((0x343e << 2) + 0xff000000)
+#define DOLBY_CORE2A_DMA_PORT ((0x343f << 2) + 0xff000000)
+#define DOLBY_CORE2A_AXI2DMA_CTRL0 ((0x3440 << 2) + 0xff000000)
+#define DOLBY_CORE2A_AXI2DMA_CTRL1 ((0x3441 << 2) + 0xff000000)
+#define DOLBY_CORE2A_AXI2DMA_CTRL2 ((0x3442 << 2) + 0xff000000)
+#define DOLBY_CORE2A_AXI2DMA_CTRL3 ((0x3443 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dolby2a_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: DOLBY2B_VCBUS_BASE = 0x35
+// -----------------------------------------------
+//`include "dolby2b_regs.h"
+// -----------------------------------------------
+// REG_BASE: DOLBY3_VCBUS_BASE = 0x36
+// -----------------------------------------------
+//
+// Reading file: dolby3_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DOLBY_CORE3_REG_START ((0x3600 << 2) + 0xff000000)
+#define DOLBY_CORE3_CLKGATE_CTRL ((0x36f0 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL0 ((0x36f1 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL1 ((0x36f2 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL2 ((0x36f3 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL3 ((0x36f4 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL4 ((0x36f5 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL5 ((0x36f6 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL6 ((0x36f7 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL7 ((0x36f8 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL8 ((0x36f9 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL9 ((0x36fa << 2) + 0xff000000)
+#define DOLBY_CORE3_STATUS0 ((0x36fb << 2) + 0xff000000)
+#define DOLBY_CORE3_STATUS1 ((0x36fc << 2) + 0xff000000)
+#define DOLBY_CORE3_STATUS2 ((0x36fd << 2) + 0xff000000)
+#define DOLBY_CORE3_STATUS3 ((0x36fe << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dolby3_regs.h
+//
+//
+// Reading file: vpu_madc_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: MADC_VCBUS_BASE = 0x37
+// -----------------------------------------------
+// 0x00-0x28
+//
+// Reading file: nr4_nm_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define NR4_MCNR_SAD_GAIN ((0x3700 << 2) + 0xff000000)
+//Bit 31:25 reserved
+//Bit 24 reg_nr4_bld12vs3_usemaxsad // unsigned , default = 0 use minsad/maxsad instead of minsad/avgsad to decision if it was texture or flat region, 1: use minsad/maxsad
+//Bit 23:16 reg_nr4_bld12vs3_rate_gain // unsigned , default = 64 gain to minsad/maxsad or minsad/avgsad before LUT, 64 normalized as "1"
+//Bit 15: 8 reg_nr4_bld1vs2_rate_gain // unsigned , default = 32 gain to minsad/maxsad or minsad/avgsad before the LUT, 64 normalized as"1"
+//Bit 7: 0 reg_nr4_coefblt_gain // unsigned , default = 64 gain to final coefblt, normalized 64 as "1"
+#define NR4_MCNR_LPF_CTRL ((0x3701 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:22 reg_nr4_preflt_alpofst // signed , default = 0 pre filter alpha ofst
+//Bit 21:16 reg_nr4_preflt_alpgain // unsigned , default = 16 pre filter alpha gain
+//Bit 15:14 reg_nr4_preflt_alpsel // unsigned , default = 3 pre filter alpha selection for adaptive blending, 0: mv pointed sad, 1: weighted mv pointed sad, 2or3: coefblt
+//Bit 13: 8 reg_nr4_avgsad_gain // unsigned , default = 8 gain for avg sad before luts
+//Bit 7 reserved
+//Bit 6 reg_nr4_maxsad_mod // unsigned , default = 1 max sad select mode, 0: mx2_sad, 1: max sad
+//Bit 5 reg_nr4_minsad_mod // unsigned , default = 1 min sad select mode, 0: sad with min err, 1: min sad
+//Bit 4 reg_nr4_minmaxsad_lpf // unsigned , default = 1 mode of lpf for minmaxsad, 0: no LPF, 1: [1 2 1]/4
+//Bit 3 reg_nr4_avgsad_lpf // unsigned , default = 1 mode of lpf for avgsad, 0: no LPF, 1: [1 2 1]/4
+//Bit 2 reg_nr4_minavgsad_ratio_lpf // unsigned , default = 1 mode of lpf for minsad/avgsad and zmvsad/avgsad, 0: no LPF, 1: [1 2 1]/4
+//Bit 1 reg_nr4_bldvs_lut_lpf // unsigned , default = 1 mode of lpf for bld12vs3 and bld1vs2 LUT results, 0: no LPF, 1: [1 2 1]/4
+//Bit 0 reg_nr4_final_coef_lpf // unsigned , default = 1 mode of lpf for final coef_blt_blend123, 0: no LPF, 1: [1 2 1]/4
+#define NR4_MCNR_BLD_VS3LUT0 ((0x3702 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_bld12vs3_lut0 // unsigned , default = 0
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_bld12vs3_lut1 // unsigned , default = 8
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_bld12vs3_lut2 // unsigned , default = 10
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bld12vs3_lut3 // unsigned , default = 11
+#define NR4_MCNR_BLD_VS3LUT1 ((0x3703 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_bld12vs3_lut4 // unsigned , default = 12
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_bld12vs3_lut5 // unsigned , default = 14
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_bld12vs3_lut6 // unsigned , default = 16
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bld12vs3_lut7 // unsigned , default = 24
+#define NR4_MCNR_BLD_VS3LUT2 ((0x3704 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_bld12vs3_lut8 // unsigned , default = 50
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_bld12vs3_lut9 // unsigned , default = 58
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_bld12vs3_lut10 // unsigned , default = 63
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bld12vs3_lut11 // unsigned , default = 63
+#define NR4_MCNR_BLD_VS2LUT0 ((0x3705 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_bld1vs2_lut0 // unsigned , default = 63
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_bld1vs2_lut1 // unsigned , default = 32
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_bld1vs2_lut2 // unsigned , default = 16
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bld1vs2_lut3 // unsigned , default = 8
+#define NR4_MCNR_BLD_VS2LUT1 ((0x3706 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_bld1vs2_lut4 // unsigned , default = 4
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_bld1vs2_lut5 // unsigned , default = 2
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_bld1vs2_lut6 // unsigned , default = 1
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bld1vs2_lut7 // unsigned , default = 0
+#define NR4_COEFBLT_LUT10 ((0x3707 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut10 // signed , default = -128
+//Bit 23:16 reg_nr4_coefblt_lut11 // signed , default = -128
+//Bit 15: 8 reg_nr4_coefblt_lut12 // signed , default = -126
+//Bit 7: 0 reg_nr4_coefblt_lut13 // signed , default = -124
+#define NR4_COEFBLT_LUT11 ((0x3708 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut14 // signed , default = -120
+//Bit 23:16 reg_nr4_coefblt_lut15 // signed , default = -110
+//Bit 15: 8 reg_nr4_coefblt_lut16 // signed , default = -100
+//Bit 7: 0 reg_nr4_coefblt_lut17 // signed , default = -90
+#define NR4_COEFBLT_LUT12 ((0x3709 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut18 // signed , default = -56
+//Bit 23:16 reg_nr4_coefblt_lut19 // signed , default = -32
+//Bit 15: 8 reg_nr4_coefblt_lut110 // signed , default = -64
+//Bit 7: 0 reg_nr4_coefblt_lut111 // signed , default = -128
+#define NR4_COEFBLT_LUT20 ((0x370a << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut20 // signed , default = -128
+//Bit 23:16 reg_nr4_coefblt_lut21 // signed , default = -120
+//Bit 15: 8 reg_nr4_coefblt_lut22 // signed , default = -112
+//Bit 7: 0 reg_nr4_coefblt_lut23 // signed , default = -104
+#define NR4_COEFBLT_LUT21 ((0x370b << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut24 // signed , default = -96
+//Bit 23:16 reg_nr4_coefblt_lut25 // signed , default = -88
+//Bit 15: 8 reg_nr4_coefblt_lut26 // signed , default = -76
+//Bit 7: 0 reg_nr4_coefblt_lut27 // signed , default = -64
+#define NR4_COEFBLT_LUT22 ((0x370c << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut28 // signed , default = -48
+//Bit 23:16 reg_nr4_coefblt_lut29 // signed , default = -32
+//Bit 15: 8 reg_nr4_coefblt_lut210 // signed , default = -64
+//Bit 7: 0 reg_nr4_coefblt_lut211 // signed , default = -108
+#define NR4_COEFBLT_LUT30 ((0x370d << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut30 // signed , default = 8
+//Bit 23:16 reg_nr4_coefblt_lut31 // signed , default = 16
+//Bit 15: 8 reg_nr4_coefblt_lut32 // signed , default = 24
+//Bit 7: 0 reg_nr4_coefblt_lut33 // signed , default = 30
+#define NR4_COEFBLT_LUT31 ((0x370e << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut34 // signed , default = 36
+//Bit 23:16 reg_nr4_coefblt_lut35 // signed , default = 48
+//Bit 15: 8 reg_nr4_coefblt_lut36 // signed , default = 70
+//Bit 7: 0 reg_nr4_coefblt_lut37 // signed , default = 96
+#define NR4_COEFBLT_LUT32 ((0x370f << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut38 // signed , default = 120
+//Bit 23:16 reg_nr4_coefblt_lut39 // signed , default = 64
+//Bit 15: 8 reg_nr4_coefblt_lut310 // signed , default = 16
+//Bit 7: 0 reg_nr4_coefblt_lut311 // signed , default = -8
+#define NR4_COEFBLT_CONV ((0x3710 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_coefblt_convmin // unsigned , default = 0 minimum of coef. bilateral conversion
+//Bit 15: 8 reg_nr4_coefblt_convmax // unsigned , default = 255 maximum of coef. bilateral conversion
+//Bit 7: 0 reg_nr4_coefblt_convmid // unsigned , default = 128 value at midpoint of coef. bilateral conversion
+#define NR4_DBGWIN_YX0 ((0x3711 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_nr4_dgbwin_yx0 // unsigned , default = 100 ystart for debug window
+//Bit 15:14 reserved
+//Bit 13: 0 reg_nr4_dgbwin_yx1 // unsigned , default = 160 yend for debug window
+#define NR4_DBGWIN_YX1 ((0x3712 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_nr4_dgbwin_yx2 // unsigned , default = 200 xstart for debug window
+//Bit 15:14 reserved
+//Bit 13: 0 reg_nr4_dgbwin_yx3 // unsigned , default = 300 xend for debug window
+#define NR4_NM_X_CFG ((0x3713 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_nr4_nm_xst // unsigned , default = 8 start for noise meter statistic, dft = 8
+//Bit 15:14 reserved
+//Bit 13: 0 reg_nr4_nm_xed // unsigned , default = 711 end for noise meter statistic, dft = HSIZE-8-1;
+#define NR4_NM_Y_CFG ((0x3714 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_nr4_nm_yst // unsigned , default = 8 start for noise meter statistic, dft = 8;
+//Bit 15:14 reserved
+//Bit 13: 0 reg_nr4_nm_yed // unsigned , default = 231 end for noise meter statistic, dft = VSIZE-8-1;
+#define NR4_NM_SAD_THD ((0x3715 << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7: 0 reg_nr4_nm_sad_thd // unsigned , default = 255 threshold for (flat region) sad count, dft = 4
+#define NR4_MCNR_BANDSPLIT_PRAM ((0x3716 << 2) + 0xff000000)
+//Bit 31: 5 reserved
+//Bit 4 reg_nr4_mc_use_bandsplit // unsigned , default = 1 separate lp and us for mc IIR filter, 0: no BS used; 1: use BS
+//Bit 3 reg_nr4_mc_apply_on_lp // unsigned , default = 1 use mcnr only on lowpass portion;
+//Bit 2 reg_nr4_mc_apply_on_us // unsigned , default = 1 use mcnr only on lp complimentary portion;
+//Bit 1: 0 reg_nr4_mc_zmvbs_use_adplpf // unsigned , default = 1 use adapptive LPF for the zmv pointing data for MCNR, for abs(mvx)<th
+#define NR4_MCNR_ALP1_SGN_COR ((0x3717 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_mc_aph1_sgn_coring0 // unsigned , default = 10 coring to cur-pre before do sgn decision
+//Bit 23:16 reg_nr4_mc_aph1_sgn_coring1 // unsigned , default = 7 coring to cur-pre before do sgn decision
+//Bit 15: 8 reg_nr4_mc_aph1_sgn_core_max0 // unsigned , default = 90 maximum of coring, default = 30/15
+//Bit 7: 0 reg_nr4_mc_aph1_sgn_core_max1 // unsigned , default = 15 maximum of coring, default = 30/15
+#define NR4_MCNR_ALP1_SGN_PRAM ((0x3718 << 2) + 0xff000000)
+//Bit 31:11 reserved
+//Bit 10 reg_nr4_mc_alp1_sgn_half // unsigned , default = 1 half block sgn sum mode enable, 0: only use 3x5 whole block sum of sgns; 1: use max(sgn_3x5, sqrt(sgn_left+sgn_righ))
+//Bit 9 reg_nr4_mc_alp1_sgn_frczmv // unsigned , default = 1 force zmv to calculate the sign_sum;
+//Bit 8 reg_nr4_mc_alp1_sgnmvx_mode // unsigned , default = 1 blend mode of sgnlut and mvxlut blend mode: 0: sgnlut+ mvxlut; 1: max(sgnlut, mvxlut), default =1
+//Bit 7: 4 reg_nr4_mc_aph1_sgn_crate0 // unsigned , default = 4 rate to var, norm to 16 as 1, default = 2
+//Bit 3: 0 reg_nr4_mc_aph1_sgn_crate1 // unsigned , default = 2 rate to var, norm to 16 as 1, default = 2
+#define NR4_MCNR_ALP1_MVX_LUT1 ((0x3719 << 2) + 0xff000000)
+//Bit 31:28 reg_nr4_mc_alp1_mvx_luty3 // unsigned , default = 14 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 27:24 reg_nr4_mc_alp1_mvx_lutc3 // unsigned , default = 14 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 23:20 reg_nr4_mc_alp1_mvx_luty2 // unsigned , default = 12 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 19:16 reg_nr4_mc_alp1_mvx_lutc2 // unsigned , default = 12 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 15:12 reg_nr4_mc_alp1_mvx_luty1 // unsigned , default = 5 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 11: 8 reg_nr4_mc_alp1_mvx_lutc1 // unsigned , default = 5 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 7: 4 reg_nr4_mc_alp1_mvx_luty0 // unsigned , default = 3 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 3: 0 reg_nr4_mc_alp1_mvx_lutc0 // unsigned , default = 3 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+#define NR4_MCNR_ALP1_MVX_LUT2 ((0x371a << 2) + 0xff000000)
+//Bit 31:28 reg_nr4_mc_alp1_mvx_luty7 // unsigned , default = 15 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 27:24 reg_nr4_mc_alp1_mvx_lutc7 // unsigned , default = 15 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 23:20 reg_nr4_mc_alp1_mvx_luty6 // unsigned , default = 15 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 19:16 reg_nr4_mc_alp1_mvx_lutc6 // unsigned , default = 15 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 15:12 reg_nr4_mc_alp1_mvx_luty5 // unsigned , default = 15 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 11: 8 reg_nr4_mc_alp1_mvx_lutc5 // unsigned , default = 15 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 7: 4 reg_nr4_mc_alp1_mvx_luty4 // unsigned , default = 15 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 3: 0 reg_nr4_mc_alp1_mvx_lutc4 // unsigned , default = 15 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+#define NR4_MCNR_ALP1_MVX_LUT3 ((0x371b << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7: 4 reg_nr4_mc_alp1_mvx_luty8 // unsigned , default = 6 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 3: 0 reg_nr4_mc_alp1_mvx_lutc8 // unsigned , default = 6 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+#define NR4_MCNR_ALP1_LP_PRAM ((0x371c << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:16 reg_nr4_mc_alp1_lp_sel // unsigned , default = 1 mode for alp1_lp for lp portion IIR, 0: apha1, 1:dc_dif vs ac analysis; 2: gain/ofst of alp1; 3: max of #1/#2 results
+//Bit 15: 8 reg_nr4_mc_alp1_lp_gain // unsigned , default = 64 gain to alp1 to get the alp1_lp = alp1*gain/32 + ofset, default =64;
+//Bit 7: 0 reg_nr4_mc_alp1_lp_ofst // signed , default = 0 offset to alp1 to get the alp1_lp = alp1*gain/32 + ofset, default =10;
+#define NR4_MCNR_ALP1_SGN_LUT1 ((0x371d << 2) + 0xff000000)
+//Bit 31:28 reg_nr4_mc_alp1_sgn_lut0 // unsigned , default = 3 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 27:24 reg_nr4_mc_alp1_sgn_lut1 // unsigned , default = 3 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 23:20 reg_nr4_mc_alp1_sgn_lut2 // unsigned , default = 3 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 19:16 reg_nr4_mc_alp1_sgn_lut3 // unsigned , default = 4 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 15:12 reg_nr4_mc_alp1_sgn_lut4 // unsigned , default = 5 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 11: 8 reg_nr4_mc_alp1_sgn_lut5 // unsigned , default = 6 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 7: 4 reg_nr4_mc_alp1_sgn_lut6 // unsigned , default = 7 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 3: 0 reg_nr4_mc_alp1_sgn_lut7 // unsigned , default = 8 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+#define NR4_MCNR_ALP1_SGN_LUT2 ((0x371e << 2) + 0xff000000)
+//Bit 31:28 reg_nr4_mc_alp1_sgn_lut8 // unsigned , default = 9 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 27:24 reg_nr4_mc_alp1_sgn_lut9 // unsigned , default = 10 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 23:20 reg_nr4_mc_alp1_sgn_lut10 // unsigned , default = 11 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 19:16 reg_nr4_mc_alp1_sgn_lut11 // unsigned , default = 12 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 15:12 reg_nr4_mc_alp1_sgn_lut12 // unsigned , default = 13 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 11: 8 reg_nr4_mc_alp1_sgn_lut13 // unsigned , default = 14 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 7: 4 reg_nr4_mc_alp1_sgn_lut14 // unsigned , default = 15 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 3: 0 reg_nr4_mc_alp1_sgn_lut15 // unsigned , default = 15 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+#define NR4_RO_NM_SAD_SUM ((0x371f << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_nm_sad_sum // unsigned , default = 0 sum of sad, for scene change detectcion, in noise meter
+#define NR4_RO_NM_SAD_CNT ((0x3720 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_nm_sad_cnt // unsigned , default = 0 cnt of sad, for scene change detectcion, in noise meter
+#define NR4_RO_NM_VAR_SUM ((0x3721 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_nm_var_sum // unsigned , default = 0 sum of var, for noise level detection, in noise meter
+#define NR4_RO_NM_VAR_SCNT ((0x3722 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_nm_var_cnt // unsigned , default = 0 cnt of var, for noise level detection, in noise meter
+#define NR4_RO_NM_VAR_MIN_MAX ((0x3723 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:12 ro_nr4_nm_min_var // unsigned , default = 1023 min of var, for noise level detection, in noise meter
+//Bit 11:10 reserved
+//Bit 9: 0 ro_nr4_nm_max_var // unsigned , default = 0 max of var, for noise level detection, in noise meter
+#define NR4_RO_NR4_DBGPIX_NUM ((0x3724 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27: 0 ro_nr4_dbgpix_num // unsigned , default = 0 number of pixels statistic invoved (removed?)
+#define NR4_RO_NR4_BLDVS2_SUM ((0x3725 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_bld1vs2_sum // unsigned , default = 0 sum of blend_1vs2 with the debug window
+#define NR4_BLDVS3_SUM ((0x3726 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_bld12vs3_sum // unsigned , default = 0 sum of blend_12vs3 with the debug window
+#define NR4_COEF12_SUM ((0x3727 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_coef12_sum // signed , default = 0 sum of coef_blt_blend12 with the debug window, under 8 bits precision
+#define NR4_COEF123_SUM ((0x3728 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_coef123_sum // signed , default = 0 sum of coef_final with the debug window, under 8 bits precision
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: nr4_nm_regs.h
+//
+// 0x30-0x32
+//
+// Reading file: vpu_xlr_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define XLR_CTRL ((0x3730 << 2) + 0xff000000)
+//Bit 31:23 reserved
+//Bit 22 reg_xlr_en // unsigned , default = 1 enable bits for xlr function, 1: enable, 0: disable default = 1
+//Bit 21 reg_xlr_side_en // unsigned , default = 1 enable to filter the above and below lines with xlr filter, default = 1
+//Bit 20 reg_xlr_3lines // unsigned , default = 1 3 lines version enable default= 0
+//Bit 19:16 reg_xlr_simlp_gain // unsigned , default = 12 gain to simlp to decide if need the XLR, default= 12
+//Bit 15:14 reserved
+//Bit 13: 8 reg_xlr_ooplp_gain // unsigned , default = 6 gain to out-of-phase lp error to decide if need the XLR, birn to 16 as 1, default= 3
+//Bit 7: 0 reg_xlr_dislp_thrd // unsigned , default = 64 threshold to lp error to discard XLR. default= 80
+#define XLR_THRD ((0x3731 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:24 reg_xlr_txt_core // unsigned , default = 3 coring to texture default = 3, (3/32)
+//Bit 23:16 reg_xlr_err_thrd2 // unsigned , default = 5 threshold to error to decide blending coef, 0, 1/4, 1/2, 1.0, defaut= {20, 10, 5}
+//Bit 15: 8 reg_xlr_err_thrd1 // unsigned , default = 10 threshold to error to decide blending coef, 0, 1/4, 1/2, 1.0, defaut= {20, 10, 5}
+//Bit 7: 0 reg_xlr_err_thrd0 // unsigned , default = 20 threshold to error to decide blending coef, 0, 1/4, 1/2, 1.0, defaut= {20, 10, 5}
+#define XLR_HCT_THRD ((0x3732 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 reg_xlr_hct_step // unsigned , default = 1 horizontal chroma diff steps, 0: abs[-1 (2) -1]; 1: abs[-1 0 (2) 0 -1], 2: abs[-1 0 0 (2) 0 0 -1]; 3:abs[-1 0 0 0 (2) 0 0 0 -1]
+//Bit 25:24 reg_xlr_hct_lpf // unsigned , default = 1 horizontal chroma diff low-pass filter enable, 0: no HLPF; 1: [1 2 1]; 2: max[-1:1]; 3: max[-2:2]
+//Bit 23:16 reg_xlr_hct_thr // unsigned , default = 20 horizontal chroma diff threshold for xlr enable, to save the horozontal no color tran mode
+//Bit 15: 8 reg_xlr_sat_thr // unsigned , default = 8 saturation threshold for xlr enable, the smaller of the threshold , the more will do xlr;
+//Bit 7: 2 reg_xlr_hmargin // unsigned , default = 3 left/right number of pixels without xlr;
+//Bit 1 reserved
+//Bit 0 reg_xlr_hpf_only // unsigned , default = 0 enable for only do xlr filter on high pass portion of the data, instead full data
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_xlr_regs.h
+//
+// 0x38-0x3f
+//
+// Reading file: nr_deband_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define NR_DB_FLT_CTRL ((0x3738 << 2) + 0xff000000)
+//Bit 31:27 reserved
+//Bit 26 reg_nrdeband_reset1 // unsigned , default = 0 0 : no reset seed 1: reload chroma seed
+//Bit 25 reg_nrdeband_reset0 // unsigned , default = 0 0 : no reset seed 1: reload luma seed
+//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 0 : yuv 1: RGB
+//Bit 23 reg_nrdeband_en11 // unsigned , default = 1 debanding registers of side lines, [0] for luma, same for below
+//Bit 22 reg_nrdeband_en10 // unsigned , default = 1 debanding registers of side lines, [1] for chroma, same for below
+//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
+//Bit 16 reserved
+//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
+//Bit 12 reserved
+//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6
+//Bit 8 reserved
+//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 debanding random hp portion xor, [0] for luma
+//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 debanding random hp portion xor, [1] for chroma
+//Bit 5 reg_nrdeband_en1 // unsigned , default = 1 debanding registers, for luma
+//Bit 4 reg_nrdeband_en0 // unsigned , default = 1 debanding registers, for chroma
+//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+#define NR_DB_FLT_YC_THRD ((0x3739 << 2) + 0xff000000)
+//Bit 31:28 reg_nrdeband_luma_th3 // unsigned , default = 9 threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 27:24 reg_nrdeband_luma_th2 // unsigned , default = 7 elseif <th[1] use (lpf*3 + y)/4
+//Bit 23:20 reg_nrdeband_luma_th1 // unsigned , default = 6 elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 19:16 reg_nrdeband_luma_th0 // unsigned , default = 5 elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else
+//Bit 15:12 reg_nrdeband_chrm_th3 // unsigned , default = 9 threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 11: 8 reg_nrdeband_chrm_th2 // unsigned , default = 7 elseif <th[1] use (lpf*3 + y)/4
+//Bit 7: 4 reg_nrdeband_chrm_th1 // unsigned , default = 6 elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 3: 0 reg_nrdeband_chrm_th0 // unsigned , default = 5 elseif <th[1] use (lpf*3 + y)/4elseif elseif
+#define NR_DB_FLT_RANDLUT ((0x373a << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:21 reg_nrdeband_randslut7 // unsigned , default = 1 lut0
+//Bit 20:18 reg_nrdeband_randslut6 // unsigned , default = 1 lut0
+//Bit 17:15 reg_nrdeband_randslut5 // unsigned , default = 1 lut0
+//Bit 14:12 reg_nrdeband_randslut4 // unsigned , default = 1 lut0
+//Bit 11: 9 reg_nrdeband_randslut3 // unsigned , default = 1 lut0
+//Bit 8: 6 reg_nrdeband_randslut2 // unsigned , default = 1 lut0
+//Bit 5: 3 reg_nrdeband_randslut1 // unsigned , default = 1 lut0
+//Bit 2: 0 reg_nrdeband_randslut0 // unsigned , default = 1 lut0
+#define NR_DB_FLT_PXI_THRD ((0x373b << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 to luma/|u/v| for using the denoise
+//Bit 15:10 reserved
+//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 to luma/|u/v| for using the denoise
+#define NR_DB_FLT_SEED_Y ((0x373c << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 noise adding seed for Y. seed[0]= 0x60a52f20; as default
+#define NR_DB_FLT_SEED_U ((0x373d << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 noise adding seed for U. seed[0]= 0x60a52f27; as default
+#define NR_DB_FLT_SEED_V ((0x373e << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define NR_DB_FLT_SEED3 ((0x373f << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed3 // unsigned , default = 1621438242 noise adding seed for V. seed[0]= 0x60a52f22; as default
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: nr_deband_regs.h
+//
+// 0x40-0x43
+//
+// Reading file: nr_downscale_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define NR_DS_BUF_SIZE ((0x3740 << 2) + 0xff000000)
+//Bit 31:24 dsbuf_rowmax // unsigned , default = 96
+//Bit 23:16 dsbuf_colmax // unsigned , default = 128
+//Bit 15: 8 dsbuf_orow // unsigned , default = 128
+//Bit 7: 0 dsbuf_ocol // unsigned , default = 128
+#define NR_DS_CTRL ((0x3741 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_h_step // unsigned , default = 8 rand lut0
+//Bit 23:22 reserved
+//Bit 21:16 reg_v_step // unsigned , default = 8 rand lut0
+//Bit 15 reserved
+//Bit 14:12 reg_haa_sel // unsigned , default = 4
+//Bit 11 reserved
+//Bit 10: 8 reg_vaa_sel // unsigned , default = 4
+//Bit 7 reserved
+//Bit 6: 4 reg_use_hphase // unsigned , default = 1
+//Bit 3: 1 reserved
+//Bit 0 reg_yuv_bldmode // unsigned , default = 0
+#define NR_DS_OFFSET ((0x3742 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_h_ofst // signed , default = 0
+//Bit 15:10 reserved
+//Bit 9: 0 reg_v_ofst // signed , default = 0
+#define NR_DS_BLD_COEF ((0x3743 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_yuv_bldcoef2 // unsigned , default = 128
+//Bit 15: 8 reg_yuv_bldcoef1 // unsigned , default = 64
+//Bit 7: 0 reg_yuv_bldcoef0 // unsigned , default = 64
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: nr_downscale_regs.h
+//
+// 0x44-0xbf
+//
+// Reading file: di_scale_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DI_SCO_FIFO_CTRL ((0x374e << 2) + 0xff000000)
+#define DI_SC_TOP_CTRL ((0x374f << 2) + 0xff000000)
+// dummy data used in the DI preblend and scaler
+// Bit 23:16 Y
+// Bit 15:8 CB
+// Bit 7:0 CR
+#define DI_SC_DUMMY_DATA ((0x3750 << 2) + 0xff000000)
+//input line length used in DI
+#define DI_SC_LINE_IN_LENGTH ((0x3751 << 2) + 0xff000000)
+//input Picture height used in DI
+#define DI_SC_PIC_IN_HEIGHT ((0x3752 << 2) + 0xff000000)
+//Because there are many coefficients used in the vertical filter and horizontal filters,
+//indirect access the coefficients of vertical filter and horizontal filter is used.
+//For vertical filter, there are 33x4 coefficients
+//For horizontal filter, there are 33x4 coefficients
+//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
+//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
+//Bit 13 if true, vertical separated coef enable
+//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
+//Bit 8:7 type of index, 00: vertical coef, 01: vertical chroma coef: 10: horizontal coef, 11: resevered
+//Bit 6:0 coef index
+#define DI_SC_COEF_IDX ((0x3753 << 2) + 0xff000000)
+//coefficients for vertical filter and horizontal filter
+#define DI_SC_COEF ((0x3754 << 2) + 0xff000000)
+//these following registers are the absolute line address pointer for output divided screen
+//The output divided screen is shown in the following:
+//
+// -------------------------- <------ line zero
+// .
+// .
+// . region0 <---------- nonlinear region or nonscaling region
+// .
+// ---------------------------
+// --------------------------- <------ region1_startp
+// .
+// . region1 <---------- nonlinear region
+// .
+// .
+// ---------------------------
+// --------------------------- <------ region2_startp
+// .
+// . region2 <---------- linear region
+// .
+// .
+// ---------------------------
+// --------------------------- <------ region3_startp
+// .
+// . region3 <---------- nonlinear region
+// .
+// .
+// ---------------------------
+// --------------------------- <------ region4_startp
+// .
+// . region4 <---------- nonlinear region or nonoscaling region
+// .
+// .
+// --------------------------- <------ region4_endp
+//Bit 28:16 region1 startp
+//Bit 12:0 region2 startp
+#define DI_VSC_REGION12_STARTP ((0x3755 << 2) + 0xff000000)
+//Bit 28:16 region3 startp
+//Bit 12:0 region4 startp
+#define DI_VSC_REGION34_STARTP ((0x3756 << 2) + 0xff000000)
+#define DI_VSC_REGION4_ENDP ((0x3757 << 2) + 0xff000000)
+//vertical start phase step, (source/dest)*(2^24)
+//Bit 27:24 integer part
+//Bit 23:0 fraction part
+#define DI_VSC_START_PHASE_STEP ((0x3758 << 2) + 0xff000000)
+//vertical scaler region0 phase slope, Bit24 signed bit
+#define DI_VSC_REGION0_PHASE_SLOPE ((0x3759 << 2) + 0xff000000)
+//vertical scaler region1 phase slope, Bit24 signed bit
+#define DI_VSC_REGION1_PHASE_SLOPE ((0x375a << 2) + 0xff000000)
+//vertical scaler region3 phase slope, Bit24 signed bit
+#define DI_VSC_REGION3_PHASE_SLOPE ((0x375b << 2) + 0xff000000)
+//vertical scaler region4 phase slope, Bit24 signed bit
+#define DI_VSC_REGION4_PHASE_SLOPE ((0x375c << 2) + 0xff000000)
+//Bit 18:17 double line mode, input/output line width of vscaler becomes 2X,
+// so only 2 line buffer in this case, use for 3D line by line interleave scaling
+// bit1 true, double the input width and half input height, bit0 true, change line buffer 2 lines instead of 4 lines
+//Bit 16 0: progressive output, 1: interlace output
+//Bit 15 vertical scaler output line0 in advance or not for bottom field
+//Bit 14:13 vertical scaler initial repeat line0 number for bottom field
+//Bit 11:8 vertical scaler initial receiving number for bottom field
+//Bit 7 vertical scaler output line0 in advance or not for top field
+//Bit 6:5 vertical scaler initial repeat line0 number for top field
+//Bit 3:0 vertical scaler initial receiving number for top field
+#define DI_VSC_PHASE_CTRL ((0x375d << 2) + 0xff000000)
+//Bit 31:16 vertical scaler field initial phase for bottom field
+//Bit 15:0 vertical scaler field initial phase for top field
+#define DI_VSC_INI_PHASE ((0x375e << 2) + 0xff000000)
+//Bit 28:16 region1 startp
+//Bit 12:0 region2 startp
+#define DI_HSC_REGION12_STARTP ((0x3760 << 2) + 0xff000000)
+//Bit 28:16 region3 startp
+//Bit 12:0 region4 startp
+#define DI_HSC_REGION34_STARTP ((0x3761 << 2) + 0xff000000)
+#define DI_HSC_REGION4_ENDP ((0x3762 << 2) + 0xff000000)
+//horizontal start phase step, (source/dest)*(2^24)
+//Bit 27:24 integer part
+//Bit 23:0 fraction part
+#define DI_HSC_START_PHASE_STEP ((0x3763 << 2) + 0xff000000)
+//horizontal scaler region0 phase slope, Bit24 signed bit
+#define DI_HSC_REGION0_PHASE_SLOPE ((0x3764 << 2) + 0xff000000)
+//horizontal scaler region1 phase slope, Bit24 signed bit
+#define DI_HSC_REGION1_PHASE_SLOPE ((0x3765 << 2) + 0xff000000)
+//horizontal scaler region3 phase slope, Bit24 signed bit
+#define DI_HSC_REGION3_PHASE_SLOPE ((0x3766 << 2) + 0xff000000)
+//horizontal scaler region4 phase slope, Bit24 signed bit
+#define DI_HSC_REGION4_PHASE_SLOPE ((0x3767 << 2) + 0xff000000)
+//Bit 22:21 horizontal scaler initial repeat pixel0 number0
+//Bit 19:16 horizontal scaler initial receiving number0
+//Bit 15:0 horizontal scaler top field initial phase0
+#define DI_HSC_PHASE_CTRL ((0x3768 << 2) + 0xff000000)
+// Bit 31 if false, di_scale swap layer bypass
+// bit 30 if true, scale before diwr, else scaler before nrwr
+// Bit 22 if true, divide VSC line length 2 as the HSC input length, othwise VSC length length is the same as the VSC line length,
+// just for special usage, more flexibility
+// Bit 21 if true, prevsc uses lin buffer, otherwise prevsc does not use line buffer, it should be same as prevsc_en
+// Bit 20 prehsc_en
+// Bit 19 prevsc_en
+// Bit 18 vsc_en
+// Bit 17 hsc_en
+// Bit 16 scale_top_en
+// Bit 15 video1 scale out enable
+// Bit 12 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for horizontal scaler
+// Bit 10:8 horizontal scaler bank length
+// Bit 5, vertical scaler phase field mode, if true, disable the opposite parity line output, more bandwith needed if output 1080i
+// Bit 4 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for vertical scaler
+// Bit 2:0 vertical scaler bank length
+#define DI_SC_MISC ((0x3769 << 2) + 0xff000000)
+#define DI_HSC_PHASE_CTRL1 ((0x376a << 2) + 0xff000000)
+#define DI_HSC_INI_PAT_CTRL ((0x376b << 2) + 0xff000000)
+#define DI_SC_GCLK_CTRL ((0x376c << 2) + 0xff000000)
+#define DI_SC_HOLD_LINE ((0x376d << 2) + 0xff000000)
+#define DI_HDR_IN_HSIZE ((0x376e << 2) + 0xff000000)
+#define DI_HDR_IN_VSIZE ((0x376f << 2) + 0xff000000)
+#define DI_HDR_OFFSET 0x70
+#define DI_HDR2_CTRL ((0x3770 << 2) + 0xff000000)
+#define DI_HDR2_CLK_GATE ((0x3771 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF00_01 ((0x3772 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF02_10 ((0x3773 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF11_12 ((0x3774 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF20_21 ((0x3775 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF22 ((0x3776 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF30_31 ((0x3777 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF32_40 ((0x3778 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF41_42 ((0x3779 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_OFFSET0_1 ((0x377a << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_OFFSET2 ((0x377b << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x377c << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_PRE_OFFSET2 ((0x377d << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF00_01 ((0x377e << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF02_10 ((0x377f << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF11_12 ((0x3780 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF20_21 ((0x3781 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF22 ((0x3782 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF30_31 ((0x3783 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF32_40 ((0x3784 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF41_42 ((0x3785 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_OFFSET0_1 ((0x3786 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_OFFSET2 ((0x3787 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x3788 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_PRE_OFFSET2 ((0x3789 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_CLIP ((0x378a << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_CLIP ((0x378b << 2) + 0xff000000)
+#define DI_HDR2_CGAIN_OFFT ((0x378c << 2) + 0xff000000)
+#define DI_EOTF_LUT_ADDR_PORT ((0x378e << 2) + 0xff000000)
+#define DI_EOTF_LUT_DATA_PORT ((0x378f << 2) + 0xff000000)
+#define DI_OETF_LUT_ADDR_PORT ((0x3790 << 2) + 0xff000000)
+#define DI_OETF_LUT_DATA_PORT ((0x3791 << 2) + 0xff000000)
+#define DI_CGAIN_LUT_ADDR_PORT ((0x3792 << 2) + 0xff000000)
+#define DI_CGAIN_LUT_DATA_PORT ((0x3793 << 2) + 0xff000000)
+#define DI_HDR2_CGAIN_COEF0 ((0x3794 << 2) + 0xff000000)
+#define DI_HDR2_CGAIN_COEF1 ((0x3795 << 2) + 0xff000000)
+#define DI_OGAIN_LUT_ADDR_PORT ((0x3796 << 2) + 0xff000000)
+#define DI_OGAIN_LUT_DATA_PORT ((0x3797 << 2) + 0xff000000)
+#define DI_HDR2_ADPS_CTRL ((0x3798 << 2) + 0xff000000)
+#define DI_HDR2_ADPS_ALPHA0 ((0x3799 << 2) + 0xff000000)
+#define DI_HDR2_ADPS_ALPHA1 ((0x379a << 2) + 0xff000000)
+#define DI_HDR2_ADPS_BETA0 ((0x379b << 2) + 0xff000000)
+#define DI_HDR2_ADPS_BETA1 ((0x379c << 2) + 0xff000000)
+#define DI_HDR2_ADPS_BETA2 ((0x379d << 2) + 0xff000000)
+#define DI_HDR2_ADPS_COEF0 ((0x379e << 2) + 0xff000000)
+#define DI_HDR2_ADPS_COEF1 ((0x379f << 2) + 0xff000000)
+#define DI_HDR2_GMUT_CTRL ((0x37a0 << 2) + 0xff000000)
+#define DI_HDR2_GMUT_COEF0 ((0x37a1 << 2) + 0xff000000)
+#define DI_HDR2_GMUT_COEF1 ((0x37a2 << 2) + 0xff000000)
+#define DI_HDR2_GMUT_COEF2 ((0x37a3 << 2) + 0xff000000)
+#define DI_HDR2_GMUT_COEF3 ((0x37a4 << 2) + 0xff000000)
+#define DI_HDR2_GMUT_COEF4 ((0x37a5 << 2) + 0xff000000)
+#define DI_HDR2_PIPE_CTRL1 ((0x37a6 << 2) + 0xff000000)
+#define DI_HDR2_PIPE_CTRL2 ((0x37a7 << 2) + 0xff000000)
+#define DI_HDR2_PIPE_CTRL3 ((0x37a8 << 2) + 0xff000000)
+#define DI_HDR2_PROC_WIN1 ((0x37a9 << 2) + 0xff000000)
+#define DI_HDR2_PROC_WIN2 ((0x37aa << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_EN_CTRL ((0x37ab << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_EN_CTRL ((0x37ac << 2) + 0xff000000)
+#define DI_HDR2_HIST_CTRL ((0x37ad << 2) + 0xff000000)
+#define DI_HDR2_HIST_H_START_END ((0x37ae << 2) + 0xff000000)
+#define DI_HDR2_HIST_V_START_END ((0x37af << 2) + 0xff000000)
+#define DI_HDR2_HIST_RD ((0x378d << 2) + 0xff000000)
+#define DI_VIU_HSC_WIDTHM1 ((0x37b0 << 2) + 0xff000000)
+#define DI_VIU_HSC_PHASE_STEP ((0x37b1 << 2) + 0xff000000)
+#define DI_VIU_HSC_CTRL ((0x37b2 << 2) + 0xff000000)
+#define DI_VIU_HSC_PHASE_CTRL ((0x37b3 << 2) + 0xff000000)
+#define DI_VIU_HSC_COEF ((0x37b4 << 2) + 0xff000000)
+#define DI_VIU_HSC_COEF_IDX ((0x37b5 << 2) + 0xff000000)
+#define DI_SC_PREHSC_COEF ((0x37b9 << 2) + 0xff000000)
+#define DI_SC_PRE_SCALE_CTRL ((0x37ba << 2) + 0xff000000)
+#define DI_SC_PREVSC_COEF ((0x37bb << 2) + 0xff000000)
+#define DI_SC_PREHSC_COEF1 ((0x37bc << 2) + 0xff000000)
+#define DI_DITH_CTRL ((0x3744 << 2) + 0xff000000)
+#define DI_DITH_LUT_1 ((0x3745 << 2) + 0xff000000)
+#define DI_DITH_LUT_2 ((0x3746 << 2) + 0xff000000)
+#define DI_DITH_LUT_3 ((0x3747 << 2) + 0xff000000)
+#define DI_DITH_LUT_4 ((0x3748 << 2) + 0xff000000)
+#define DI_DITH_LUT_5 ((0x3749 << 2) + 0xff000000)
+#define DI_DITH_LUT_6 ((0x374a << 2) + 0xff000000)
+#define DI_DITH_LUT_7 ((0x374b << 2) + 0xff000000)
+#define DI_DITH_LUT_8 ((0x374c << 2) + 0xff000000)
+#define DI_DITH_LUT_9 ((0x374d << 2) + 0xff000000)
+#define DI_DITH_LUT_10 ((0x37b6 << 2) + 0xff000000)
+#define DI_DITH_LUT_11 ((0x37b7 << 2) + 0xff000000)
+#define DI_DITH_LUT_12 ((0x37b8 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: di_scale_regs.h
+//
+// 0xc0~0xff
+//
+// Reading file: di_arb_sub_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DI_SUB_RDARB_MODE ((0x37c0 << 2) + 0xff000000)
+#define DI_SUB_RDARB_REQEN_SLV ((0x37c1 << 2) + 0xff000000)
+#define DI_SUB_RDARB_WEIGH0_SLV ((0x37c2 << 2) + 0xff000000)
+#define DI_SUB_RDARB_WEIGH1_SLV ((0x37c3 << 2) + 0xff000000)
+#define DI_SUB_RDARB_UGT ((0x37c4 << 2) + 0xff000000)
+#define DI_SUB_RDARB_LIMT0 ((0x37c5 << 2) + 0xff000000)
+#define DI_SUB_WRARB_MODE ((0x37c6 << 2) + 0xff000000)
+#define DI_SUB_WRARB_REQEN_SLV ((0x37c7 << 2) + 0xff000000)
+#define DI_SUB_WRARB_WEIGH0_SLV ((0x37c8 << 2) + 0xff000000)
+#define DI_SUB_WRARB_WEIGH1_SLV ((0x37c9 << 2) + 0xff000000)
+#define DI_SUB_WRARB_UGT ((0x37ca << 2) + 0xff000000)
+#define DI_SUB_RDWR_ARB_STATUS ((0x37cb << 2) + 0xff000000)
+#define DI_SUB_ARB_DBG_CTRL ((0x37cc << 2) + 0xff000000)
+#define DI_SUB_ARB_DBG_STAT ((0x37cd << 2) + 0xff000000)
+#define CONTRD_CTRL1 ((0x37d0 << 2) + 0xff000000)
+#define CONTRD_CTRL2 ((0x37d1 << 2) + 0xff000000)
+#define CONTRD_SCOPE_X ((0x37d2 << 2) + 0xff000000)
+#define CONTRD_SCOPE_Y ((0x37d3 << 2) + 0xff000000)
+#define CONTRD_RO_STAT ((0x37d4 << 2) + 0xff000000)
+#define CONT2RD_CTRL1 ((0x37d5 << 2) + 0xff000000)
+#define CONT2RD_CTRL2 ((0x37d6 << 2) + 0xff000000)
+#define CONT2RD_SCOPE_X ((0x37d7 << 2) + 0xff000000)
+#define CONT2RD_SCOPE_Y ((0x37d8 << 2) + 0xff000000)
+#define CONT2RD_RO_STAT ((0x37d9 << 2) + 0xff000000)
+#define MTNRD_CTRL1 ((0x37da << 2) + 0xff000000)
+#define MTNRD_CTRL2 ((0x37db << 2) + 0xff000000)
+#define MTNRD_SCOPE_X ((0x37dc << 2) + 0xff000000)
+#define MTNRD_SCOPE_Y ((0x37dd << 2) + 0xff000000)
+#define MTNRD_RO_STAT ((0x37de << 2) + 0xff000000)
+#define MCVECRD_CTRL1 ((0x37df << 2) + 0xff000000)
+#define MCVECRD_CTRL2 ((0x37e0 << 2) + 0xff000000)
+#define MCVECRD_SCOPE_X ((0x37e1 << 2) + 0xff000000)
+#define MCVECRD_SCOPE_Y ((0x37e2 << 2) + 0xff000000)
+#define MCVECRD_RO_STAT ((0x37e3 << 2) + 0xff000000)
+#define MCINFRD_CTRL1 ((0x37e4 << 2) + 0xff000000)
+#define MCINFRD_CTRL2 ((0x37e5 << 2) + 0xff000000)
+#define MCINFRD_SCOPE_X ((0x37e6 << 2) + 0xff000000)
+#define MCINFRD_SCOPE_Y ((0x37e7 << 2) + 0xff000000)
+#define MCINFRD_RO_STAT ((0x37e8 << 2) + 0xff000000)
+#define CONTWR_X ((0x37e9 << 2) + 0xff000000)
+#define CONTWR_Y ((0x37ea << 2) + 0xff000000)
+#define CONTWR_CTRL ((0x37eb << 2) + 0xff000000)
+#define CONTWR_CAN_SIZE ((0x37ec << 2) + 0xff000000)
+#define MTNWR_X ((0x37ed << 2) + 0xff000000)
+#define MTNWR_Y ((0x37ee << 2) + 0xff000000)
+#define MTNWR_CTRL ((0x37ef << 2) + 0xff000000)
+#define MTNWR_CAN_SIZE ((0x37f0 << 2) + 0xff000000)
+#define MCVECWR_X ((0x37f1 << 2) + 0xff000000)
+#define MCVECWR_Y ((0x37f2 << 2) + 0xff000000)
+#define MCVECWR_CTRL ((0x37f3 << 2) + 0xff000000)
+#define MCVECWR_CAN_SIZE ((0x37f4 << 2) + 0xff000000)
+#define MCINFWR_X ((0x37f5 << 2) + 0xff000000)
+#define MCINFWR_Y ((0x37f6 << 2) + 0xff000000)
+#define MCINFWR_CTRL ((0x37f7 << 2) + 0xff000000)
+#define MCINFWR_CAN_SIZE ((0x37f8 << 2) + 0xff000000)
+#define NRDSWR_X ((0x37f9 << 2) + 0xff000000)
+#define NRDSWR_Y ((0x37fa << 2) + 0xff000000)
+#define NRDSWR_CTRL ((0x37fb << 2) + 0xff000000)
+#define NRDSWR_CAN_SIZE ((0x37fc << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: di_arb_sub_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_madc_regs.h
+//
+//
+// Reading file: vpp_hdr2_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: VPP_HDR2_VCBUS_BASE = 0x38
+// -----------------------------------------------
+#define VD1_HDR2_OFFSET 0x00
+#define VD2_HDR2_OFFSET 0x50
+#define OSD1_HDR2_OFFSET 0xa0
+//`include "hdr2_top_reg.h"
+//vd1 0x00 - -x35
+#define VD1_HDR2_CTRL ((0x3800 << 2) + 0xff000000)
+#define VD1_HDR2_CLK_GATE ((0x3801 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF00_01 ((0x3802 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF02_10 ((0x3803 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF11_12 ((0x3804 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF20_21 ((0x3805 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF22 ((0x3806 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF30_31 ((0x3807 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF32_40 ((0x3808 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF41_42 ((0x3809 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_OFFSET0_1 ((0x380a << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_OFFSET2 ((0x380b << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x380c << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_PRE_OFFSET2 ((0x380d << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF00_01 ((0x380e << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF02_10 ((0x380f << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF11_12 ((0x3810 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF20_21 ((0x3811 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF22 ((0x3812 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF30_31 ((0x3813 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF32_40 ((0x3814 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF41_42 ((0x3815 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_OFFSET0_1 ((0x3816 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_OFFSET2 ((0x3817 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x3818 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_PRE_OFFSET2 ((0x3819 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_CLIP ((0x381a << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_CLIP ((0x381b << 2) + 0xff000000)
+#define VD1_HDR2_CGAIN_OFFT ((0x381c << 2) + 0xff000000)
+#define VD1_EOTF_LUT_ADDR_PORT ((0x381e << 2) + 0xff000000)
+#define VD1_EOTF_LUT_DATA_PORT ((0x381f << 2) + 0xff000000)
+#define VD1_OETF_LUT_ADDR_PORT ((0x3820 << 2) + 0xff000000)
+#define VD1_OETF_LUT_DATA_PORT ((0x3821 << 2) + 0xff000000)
+#define VD1_CGAIN_LUT_ADDR_PORT ((0x3822 << 2) + 0xff000000)
+#define VD1_CGAIN_LUT_DATA_PORT ((0x3823 << 2) + 0xff000000)
+#define VD1_HDR2_CGAIN_COEF0 ((0x3824 << 2) + 0xff000000)
+#define VD1_HDR2_CGAIN_COEF1 ((0x3825 << 2) + 0xff000000)
+#define VD1_OGAIN_LUT_ADDR_PORT ((0x3826 << 2) + 0xff000000)
+#define VD1_OGAIN_LUT_DATA_PORT ((0x3827 << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_CTRL ((0x3828 << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_ALPHA0 ((0x3829 << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_ALPHA1 ((0x382a << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_BETA0 ((0x382b << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_BETA1 ((0x382c << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_BETA2 ((0x382d << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_COEF0 ((0x382e << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_COEF1 ((0x382f << 2) + 0xff000000)
+#define VD1_HDR2_GMUT_CTRL ((0x3830 << 2) + 0xff000000)
+#define VD1_HDR2_GMUT_COEF0 ((0x3831 << 2) + 0xff000000)
+#define VD1_HDR2_GMUT_COEF1 ((0x3832 << 2) + 0xff000000)
+#define VD1_HDR2_GMUT_COEF2 ((0x3833 << 2) + 0xff000000)
+#define VD1_HDR2_GMUT_COEF3 ((0x3834 << 2) + 0xff000000)
+#define VD1_HDR2_GMUT_COEF4 ((0x3835 << 2) + 0xff000000)
+#define VD1_HDR2_PIPE_CTRL1 ((0x3836 << 2) + 0xff000000)
+#define VD1_HDR2_PIPE_CTRL2 ((0x3837 << 2) + 0xff000000)
+#define VD1_HDR2_PIPE_CTRL3 ((0x3838 << 2) + 0xff000000)
+#define VD1_HDR2_PROC_WIN1 ((0x3839 << 2) + 0xff000000)
+#define VD1_HDR2_PROC_WIN2 ((0x383a << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_EN_CTRL ((0x383b << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_EN_CTRL ((0x383c << 2) + 0xff000000)
+#define VD1_HDR2_HIST_CTRL ((0x383d << 2) + 0xff000000)
+#define VD1_HDR2_HIST_H_START_END ((0x383e << 2) + 0xff000000)
+#define VD1_HDR2_HIST_V_START_END ((0x383f << 2) + 0xff000000)
+#define VD1_HDR2_HIST_RD ((0x381d << 2) + 0xff000000)
+//vd2 0x50 - 0x85
+#define VD2_HDR2_CTRL ((0x3850 << 2) + 0xff000000)
+#define VD2_HDR2_CLK_GATE ((0x3851 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF00_01 ((0x3852 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF02_10 ((0x3853 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF11_12 ((0x3854 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF20_21 ((0x3855 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF22 ((0x3856 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF30_31 ((0x3857 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF32_40 ((0x3858 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF41_42 ((0x3859 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_OFFSET0_1 ((0x385a << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_OFFSET2 ((0x385b << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x385c << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_PRE_OFFSET2 ((0x385d << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF00_01 ((0x385e << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF02_10 ((0x385f << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF11_12 ((0x3860 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF20_21 ((0x3861 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF22 ((0x3862 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF30_31 ((0x3863 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF32_40 ((0x3864 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF41_42 ((0x3865 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_OFFSET0_1 ((0x3866 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_OFFSET2 ((0x3867 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x3868 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_PRE_OFFSET2 ((0x3869 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_CLIP ((0x386a << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_CLIP ((0x386b << 2) + 0xff000000)
+#define VD2_HDR2_CGAIN_OFFT ((0x386c << 2) + 0xff000000)
+#define VD2_EOTF_LUT_ADDR_PORT ((0x386e << 2) + 0xff000000)
+#define VD2_EOTF_LUT_DATA_PORT ((0x386f << 2) + 0xff000000)
+#define VD2_OETF_LUT_ADDR_PORT ((0x3870 << 2) + 0xff000000)
+#define VD2_OETF_LUT_DATA_PORT ((0x3871 << 2) + 0xff000000)
+#define VD2_CGAIN_LUT_ADDR_PORT ((0x3872 << 2) + 0xff000000)
+#define VD2_CGAIN_LUT_DATA_PORT ((0x3873 << 2) + 0xff000000)
+#define VD2_HDR2_CGAIN_COEF0 ((0x3874 << 2) + 0xff000000)
+#define VD2_HDR2_CGAIN_COEF1 ((0x3875 << 2) + 0xff000000)
+#define VD2_OGAIN_LUT_ADDR_PORT ((0x3876 << 2) + 0xff000000)
+#define VD2_OGAIN_LUT_DATA_PORT ((0x3877 << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_CTRL ((0x3878 << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_ALPHA0 ((0x3879 << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_ALPHA1 ((0x387a << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_BETA0 ((0x387b << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_BETA1 ((0x387c << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_BETA2 ((0x387d << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_COEF0 ((0x387e << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_COEF1 ((0x387f << 2) + 0xff000000)
+#define VD2_HDR2_GMUT_CTRL ((0x3880 << 2) + 0xff000000)
+#define VD2_HDR2_GMUT_COEF0 ((0x3881 << 2) + 0xff000000)
+#define VD2_HDR2_GMUT_COEF1 ((0x3882 << 2) + 0xff000000)
+#define VD2_HDR2_GMUT_COEF2 ((0x3883 << 2) + 0xff000000)
+#define VD2_HDR2_GMUT_COEF3 ((0x3884 << 2) + 0xff000000)
+#define VD2_HDR2_GMUT_COEF4 ((0x3885 << 2) + 0xff000000)
+#define VD2_HDR2_PIPE_CTRL1 ((0x3886 << 2) + 0xff000000)
+#define VD2_HDR2_PIPE_CTRL2 ((0x3887 << 2) + 0xff000000)
+#define VD2_HDR2_PIPE_CTRL3 ((0x3888 << 2) + 0xff000000)
+#define VD2_HDR2_PROC_WIN1 ((0x3889 << 2) + 0xff000000)
+#define VD2_HDR2_PROC_WIN2 ((0x388a << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_EN_CTRL ((0x388b << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_EN_CTRL ((0x388c << 2) + 0xff000000)
+#define VD2_HDR2_HIST_CTRL ((0x388d << 2) + 0xff000000)
+#define VD2_HDR2_HIST_H_START_END ((0x388e << 2) + 0xff000000)
+#define VD2_HDR2_HIST_V_START_END ((0x388f << 2) + 0xff000000)
+#define VD2_HDR2_HIST_RD ((0x386d << 2) + 0xff000000)
+//osd1 0xa0 - 0xd5
+#define OSD1_HDR2_CTRL ((0x38a0 << 2) + 0xff000000)
+#define OSD1_HDR2_CLK_GATE ((0x38a1 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF00_01 ((0x38a2 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF02_10 ((0x38a3 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF11_12 ((0x38a4 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF20_21 ((0x38a5 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF22 ((0x38a6 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF30_31 ((0x38a7 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF32_40 ((0x38a8 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF41_42 ((0x38a9 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_OFFSET0_1 ((0x38aa << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_OFFSET2 ((0x38ab << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x38ac << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_PRE_OFFSET2 ((0x38ad << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF00_01 ((0x38ae << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF02_10 ((0x38af << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF11_12 ((0x38b0 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF20_21 ((0x38b1 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF22 ((0x38b2 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF30_31 ((0x38b3 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF32_40 ((0x38b4 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF41_42 ((0x38b5 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_OFFSET0_1 ((0x38b6 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_OFFSET2 ((0x38b7 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x38b8 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_PRE_OFFSET2 ((0x38b9 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_CLIP ((0x38ba << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_CLIP ((0x38bb << 2) + 0xff000000)
+#define OSD1_HDR2_CGAIN_OFFT ((0x38bc << 2) + 0xff000000)
+#define OSD1_EOTF_LUT_ADDR_PORT ((0x38be << 2) + 0xff000000)
+#define OSD1_EOTF_LUT_DATA_PORT ((0x38bf << 2) + 0xff000000)
+#define OSD1_OETF_LUT_ADDR_PORT ((0x38c0 << 2) + 0xff000000)
+#define OSD1_OETF_LUT_DATA_PORT ((0x38c1 << 2) + 0xff000000)
+#define OSD1_CGAIN_LUT_ADDR_PORT ((0x38c2 << 2) + 0xff000000)
+#define OSD1_CGAIN_LUT_DATA_PORT ((0x38c3 << 2) + 0xff000000)
+#define OSD1_HDR2_CGAIN_COEF0 ((0x38c4 << 2) + 0xff000000)
+#define OSD1_HDR2_CGAIN_COEF1 ((0x38c5 << 2) + 0xff000000)
+#define OSD1_OGAIN_LUT_ADDR_PORT ((0x38c6 << 2) + 0xff000000)
+#define OSD1_OGAIN_LUT_DATA_PORT ((0x38c7 << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_CTRL ((0x38c8 << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_ALPHA0 ((0x38c9 << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_ALPHA1 ((0x38ca << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_BETA0 ((0x38cb << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_BETA1 ((0x38cc << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_BETA2 ((0x38cd << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_COEF0 ((0x38ce << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_COEF1 ((0x38cf << 2) + 0xff000000)
+#define OSD1_HDR2_GMUT_CTRL ((0x38d0 << 2) + 0xff000000)
+#define OSD1_HDR2_GMUT_COEF0 ((0x38d1 << 2) + 0xff000000)
+#define OSD1_HDR2_GMUT_COEF1 ((0x38d2 << 2) + 0xff000000)
+#define OSD1_HDR2_GMUT_COEF2 ((0x38d3 << 2) + 0xff000000)
+#define OSD1_HDR2_GMUT_COEF3 ((0x38d4 << 2) + 0xff000000)
+#define OSD1_HDR2_GMUT_COEF4 ((0x38d5 << 2) + 0xff000000)
+#define OSD1_HDR2_PIPE_CTRL1 ((0x38d6 << 2) + 0xff000000)
+#define OSD1_HDR2_PIPE_CTRL2 ((0x38d7 << 2) + 0xff000000)
+#define OSD1_HDR2_PIPE_CTRL3 ((0x38d8 << 2) + 0xff000000)
+#define OSD1_HDR2_PROC_WIN1 ((0x38d9 << 2) + 0xff000000)
+#define OSD1_HDR2_PROC_WIN2 ((0x38da << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_EN_CTRL ((0x38db << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_EN_CTRL ((0x38dc << 2) + 0xff000000)
+#define OSD1_HDR2_HIST_CTRL ((0x38dd << 2) + 0xff000000)
+#define OSD1_HDR2_HIST_H_START_END ((0x38de << 2) + 0xff000000)
+#define OSD1_HDR2_HIST_V_START_END ((0x38df << 2) + 0xff000000)
+#define OSD1_HDR2_HIST_RD ((0x38bd << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_hdr2_regs.h
+//
+//
+// Reading file: vpp_misc_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: VPP_MISC_VCBUS_BASE = 0x39
+// -----------------------------------------------
+//0x01-0a
+//
+// Reading file: vpp_vd2_mat_3x3_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VPP_VD2_MATRIX_COEF00_01 ((0x3901 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_COEF02_10 ((0x3902 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_COEF11_12 ((0x3903 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_COEF20_21 ((0x3904 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_COEF22 ((0x3905 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_OFFSET0_1 ((0x3906 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_OFFSET2 ((0x3907 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_CLIP ((0x3908 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_PRE_OFFSET0_1 ((0x3909 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_PRE_OFFSET2 ((0x390a << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_EN_CTRL ((0x390b << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_vd2_mat_3x3_regs.h
+//
+//0x10-1c
+//
+// Reading file: vpp_osd1_mat_3x5_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VPP_OSD1_MATRIX_COEF00_01 ((0x3910 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef00 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef01 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF02_10 ((0x3911 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef02 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef10 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF11_12 ((0x3912 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef11 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef12 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF20_21 ((0x3913 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef20 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef21 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF22 ((0x3914 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 coef22 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF13_14 ((0x3915 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef13 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef14 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF23_24 ((0x3916 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef23 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef24 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF15_25 ((0x3917 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef15 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef25 //signed , default = 0
+#define VPP_OSD1_MATRIX_CLIP ((0x3918 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:8 comp_thrd0 // signed ,default == 0, mat clip enable
+//Bit 7:5 conv_rs // unsigned ,default == 0, mat rs
+//Bit 4:3 clmod // unsigned ,default == 0, mat clmod
+#define VPP_OSD1_MATRIX_OFFSET0_1 ((0x3919 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 offset0 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 offset1 //signed , default = 0
+#define VPP_OSD1_MATRIX_OFFSET2 ((0x391a << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 offset2 //signed , default = 0
+#define VPP_OSD1_MATRIX_PRE_OFFSET0_1 ((0x391b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 pre_offset0 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 pre_offset1 //signed , default = 0
+#define VPP_OSD1_MATRIX_PRE_OFFSET2 ((0x391c << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 pre_offset2 //signed , default = 0
+#define VPP_OSD1_MATRIX_EN_CTRL ((0x391d << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_osd1_mat_3x5_regs.h
+//
+//0x20-2c
+//
+// Reading file: vpp_osd2_mat_3x5_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VPP_OSD2_MATRIX_COEF00_01 ((0x3920 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef00 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef01 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF02_10 ((0x3921 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef02 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef10 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF11_12 ((0x3922 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef11 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef12 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF20_21 ((0x3923 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef20 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef21 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF22 ((0x3924 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 coef22 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF13_14 ((0x3925 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef13 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef14 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF23_24 ((0x3926 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef23 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef24 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF15_25 ((0x3927 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef15 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef25 //signed , default = 0
+#define VPP_OSD2_MATRIX_CLIP ((0x3928 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:8 comp_thrd0 // signed ,default == 0, mat clip enable
+//Bit 7:5 conv_rs // unsigned ,default == 0, mat rs
+//Bit 4:3 clmod // unsigned ,default == 0, mat clmod
+#define VPP_OSD2_MATRIX_OFFSET0_1 ((0x3929 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 offset0 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 offset1 //signed , default = 0
+#define VPP_OSD2_MATRIX_OFFSET2 ((0x392a << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 offset2 //signed , default = 0
+#define VPP_OSD2_MATRIX_PRE_OFFSET0_1 ((0x392b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 pre_offset0 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 pre_offset1 //signed , default = 0
+#define VPP_OSD2_MATRIX_PRE_OFFSET2 ((0x392c << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 pre_offset2 //signed , default = 0
+#define VPP_OSD2_MATRIX_EN_CTRL ((0x392d << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_osd2_mat_3x5_regs.h
+//
+//0x30-3c
+//`include "vpp_post_mat_3x5_regs.h"
+//0x40-0x5f
+//
+// Reading file: vpp_vd2_scale_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VD2_SCALE_COEF_IDX ((0x3943 << 2) + 0xff000000)
+#define VD2_SCALE_COEF ((0x3944 << 2) + 0xff000000)
+#define VD2_VSC_REGION12_STARTP ((0x3945 << 2) + 0xff000000)
+#define VD2_VSC_REGION34_STARTP ((0x3946 << 2) + 0xff000000)
+#define VD2_VSC_REGION4_ENDP ((0x3947 << 2) + 0xff000000)
+#define VD2_VSC_START_PHASE_STEP ((0x3948 << 2) + 0xff000000)
+#define VD2_VSC_REGION0_PHASE_SLOPE ((0x3949 << 2) + 0xff000000)
+#define VD2_VSC_REGION1_PHASE_SLOPE ((0x394a << 2) + 0xff000000)
+#define VD2_VSC_REGION3_PHASE_SLOPE ((0x394b << 2) + 0xff000000)
+#define VD2_VSC_REGION4_PHASE_SLOPE ((0x394c << 2) + 0xff000000)
+#define VD2_VSC_PHASE_CTRL ((0x394d << 2) + 0xff000000)
+#define VD2_VSC_INI_PHASE ((0x394e << 2) + 0xff000000)
+#define VD2_HSC_REGION12_STARTP ((0x394f << 2) + 0xff000000)
+#define VD2_HSC_REGION34_STARTP ((0x3950 << 2) + 0xff000000)
+#define VD2_HSC_REGION4_ENDP ((0x3951 << 2) + 0xff000000)
+#define VD2_HSC_START_PHASE_STEP ((0x3952 << 2) + 0xff000000)
+#define VD2_HSC_REGION0_PHASE_SLOPE ((0x3953 << 2) + 0xff000000)
+#define VD2_HSC_REGION1_PHASE_SLOPE ((0x3954 << 2) + 0xff000000)
+#define VD2_HSC_REGION3_PHASE_SLOPE ((0x3955 << 2) + 0xff000000)
+#define VD2_HSC_REGION4_PHASE_SLOPE ((0x3956 << 2) + 0xff000000)
+#define VD2_HSC_PHASE_CTRL ((0x3957 << 2) + 0xff000000)
+#define VD2_SC_MISC ((0x3958 << 2) + 0xff000000)
+#define VD2_SCO_FIFO_CTRL ((0x3959 << 2) + 0xff000000)
+#define VD2_HSC_PHASE_CTRL1 ((0x395a << 2) + 0xff000000)
+#define VD2_HSC_INI_PAT_CTRL ((0x395b << 2) + 0xff000000)
+#define VD2_SC_GCLK_CTRL ((0x395c << 2) + 0xff000000)
+#define VD2_PREHSC_COEF ((0x395d << 2) + 0xff000000)
+#define VD2_PRE_SCALE_CTRL ((0x395e << 2) + 0xff000000)
+#define VD2_PREVSC_COEF ((0x395f << 2) + 0xff000000)
+#define VD2_PREHSC_COEF1 ((0x3942 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_vd2_scale_regs.h
+//
+#define VPP_PRE_BLEND_CTRL ((0x3960 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:20 hold_lines //unsigned , default = 8'h4
+//Bit 19:16 din_premult_en //unsigned , default = 4'h0
+//Bit 15:0 din_reoder_sel //unsigned , default = 16'h1
+#define VPP_PRE_BLEND_BLEND_DUMMY_DATA ((0x3961 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 blend0_dummy_data_y //unsigned , default = 8'h10
+//Bit 15:8 blend0_dummy_data_cb //unsigned , default = 8'h80
+//Bit 7:0 blend0_dummy_data_cr //unsigned , default = 8'h0
+#define VPP_PRE_BLEND_DUMMY_ALPHA ((0x3962 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:20 blend0_dummy_alpha //unsigned , default = 9'h0
+//Bit 19:11 blend1_dummy_alpha //unsigned , default = 9'h0
+//Bit 8:0 blend2_dummy_alpha //unsigned , default = 9'h0
+#define VPP_PRE_BLEND2_RO_CURRENT_XY ((0x3963 << 2) + 0xff000000)
+//Bit 31:0 ro_blend2_current_xy //unsigned , default = 32'h0
+#define VPP_POST_BLEND_CTRL ((0x3967 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:20 hold_lines //unsigned , default = 8'h4
+//Bit 19:16 din_premult_en //unsigned , default = 4'h0
+//Bit 15:0 din_reoder_sel //unsigned , default = 16'h1
+#define VPP_POST_BLEND_BLEND_DUMMY_DATA ((0x3968 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 blend0_dummy_data_y //unsigned , default = 8'h10
+//Bit 15:8 blend0_dummy_data_cb //unsigned , default = 8'h80
+//Bit 7:0 blend0_dummy_data_cr //unsigned , default = 8'h0
+#define VPP_POST_BLEND_DUMMY_ALPHA ((0x3969 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:20 blend0_dummy_alpha //unsigned , default = 9'h0
+//Bit 19:11 blend1_dummy_alpha //unsigned , default = 9'h0
+//Bit 8:0 blend2_dummy_alpha //unsigned , default = 9'h0
+#define VPP_POST_BLEND2_RO_CURRENT_XY ((0x396a << 2) + 0xff000000)
+//Bit 31:0 ro_blend2_current_xy //unsigned , default = 32'h0
+#define VPP_AFBC_RDARB_MODE ((0x3970 << 2) + 0xff000000)
+#define VPP_AFBC_RDARB_REQEN_SLV ((0x3971 << 2) + 0xff000000)
+#define VPP_AFBC_RDARB_WEIGH0_SLV ((0x3972 << 2) + 0xff000000)
+#define VPP_AFBC_RDWR_ARB_STATUS ((0x3973 << 2) + 0xff000000)
+#define VPP_AFBC_ARB_DBG_CTRL ((0x3974 << 2) + 0xff000000)
+#define VPP_AFBC_ARB_DBG_STAT ((0x3975 << 2) + 0xff000000)
+#define VPP_RDARB_MODE ((0x3978 << 2) + 0xff000000)
+#define VPP_RDARB_REQEN_SLV ((0x3979 << 2) + 0xff000000)
+#define VPP_RDARB_WEIGH0_SLV ((0x397a << 2) + 0xff000000)
+#define VPP_RDARB_WEIGH1_SLV ((0x397b << 2) + 0xff000000)
+#define VPP_RDWR_ARB_STATUS ((0x397c << 2) + 0xff000000)
+#define VPP_ARB_DBG_CTRL ((0x397e << 2) + 0xff000000)
+#define VPP_ARB_DBG_STAT ((0x397f << 2) + 0xff000000)
+//ox80-0x9f & 0xe0-0xef
+//
+// Reading file: vpu_primesl_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define PRIMESL_LUTC_ADDR_PORT ((0x3980 << 2) + 0xff000000)
+#define PRIMESL_LUTC_DATA_PORT ((0x3981 << 2) + 0xff000000)
+#define PRIMESL_LUTP_ADDR_PORT ((0x3982 << 2) + 0xff000000)
+#define PRIMESL_LUTP_DATA_PORT ((0x3983 << 2) + 0xff000000)
+#define PRIMESL_LUTD_ADDR_PORT ((0x3984 << 2) + 0xff000000)
+#define PRIMESL_LUTD_DATA_PORT ((0x3985 << 2) + 0xff000000)
+#define PRIMESL_CTRL0 ((0x3990 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29 legacy_mode_en // unsigned , default = 0 = 'h0
+//Bit 28 clip_en // unsigned , default = 1 = 'h0
+//Bit 27 reserved
+//Bit 26:16 inv_chroma_ratio // unsigned , default = 0 = 'h0,
+//Bit 15 reserved
+//Bit 14: 4 inv_y_ratio // unsigned , default = 0 = 'h0,
+//Bit 3 reg_gclk_ctrl // unsigned , default = 0 = 'h0,
+//Bit 2: 1 gclk_ctrl // unsigned , default = 0 = 'h0,
+//Bit 0 primesl_en // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL1 ((0x3991 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 l_headroom // unsigned , default = 0 = 'h0,
+//Bit 15:10 reserved
+//Bit 9: 0 footroom // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL2 ((0x3992 << 2) + 0xff000000)
+//Bit 31:10 reserved
+//Bit 9: 0 c_headroom // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL3 ((0x3993 << 2) + 0xff000000)
+//Bit 31:16 mub // unsigned , default = 0 = 'h0,
+//Bit 15: 0 mua // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL4 ((0x3994 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 oct_7_1 // signed , default = 0 = 'h0,
+//Bit 15:10 reserved
+//Bit 9: 0 oct_7_0 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL5 ((0x3995 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 oct_7_3 // signed , default = 0 = 'h0,
+//Bit 15:10 reserved
+//Bit 9: 0 oct_7_2 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL6 ((0x3996 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 oct_7_5 // signed , default = 0 = 'h0,
+//Bit 15:10 reserved
+//Bit 9: 0 oct_7_4 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL7 ((0x3997 << 2) + 0xff000000)
+//Bit 31:10 reserved
+//Bit 9: 0 oct_7_6 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL8 ((0x3998 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 d_lut_threshold_3_1 // unsigned , default = 0 = 'h0,
+//Bit 15:13 reserved
+//Bit 12: 0 d_lut_threshold_3_0 // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL9 ((0x3999 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12: 0 d_lut_threshold_3_2 // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL10 ((0x399a << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15:12 d_lut_step_4_3 // unsigned , default = 0 = 'h0,
+//Bit 11: 8 d_lut_step_4_2 // unsigned , default = 0 = 'h0,
+//Bit 7: 4 d_lut_step_4_1 // unsigned , default = 0 = 'h0,
+//Bit 3: 0 d_lut_step_4_0 // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL11 ((0x399b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 rgb2yuv_9_0 // signed , default = 0 = 'h0,
+//Bit 15:13 reserved
+//Bit 12: 0 rgb2yuv_9_1 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL12 ((0x399c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 rgb2yuv_9_2 // signed , default = 0 = 'h0,
+//Bit 15:13 reserved
+//Bit 12: 0 rgb2yuv_9_3 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL13 ((0x399d << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 rgb2yuv_9_4 // signed , default = 0 = 'h0,
+//Bit 15:13 reserved
+//Bit 12: 0 rgb2yuv_9_5 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL14 ((0x399e << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 rgb2yuv_9_6 // signed , default = 0 = 'h0,
+//Bit 15:13 reserved
+//Bit 12: 0 rgb2yuv_9_7 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL15 ((0x399f << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12: 0 rgb2yuv_9_8 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL16 ((0x39e0 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30 byp_s_lut // unsigned , default = 0 = 'h0,
+//Bit 29 byp_d_lut // unsigned , default = 0 = 'h0,
+//Bit 28 byp_mat // unsigned , default = 0 = 'h0,
+//Bit 27 rgb_swap // unsigned , default = 0 = 'h0,
+//Bit 26:24 uv_shift // unsigned , default = 0 = 'h0,
+//Bit 23:22 rgb_shift // unsigned , default = 0 = 'h0,
+//Bit 21:20 rgb_clip // unsigned , default = 3 = 'h3,
+//Bit 19:18 reserved
+//Bit 17:16 rgb_rs // unsigned , default = 0 = 'h0,
+//Bit 15:14 reserved
+//Bit 13: 0 reg_s // signed , default = 1024 = 'h1024,
+#define PRIMESL_OMAT_OFFSET0 ((0x39e1 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 pre_offset0 // unsigned , default = 512 = 'h512
+//Bit 15:12 reserved
+//Bit 11: 0 pre_offset1 // unsigned , default = 512 = 'h512
+#define PRIMESL_OMAT_OFFSET1 ((0x39e2 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 pre_offset2 // unsigned , default = 512 = 'h512
+//Bit 15:12 reserved
+//Bit 11: 0 offset0 // unsigned , default = 256 = 'h256
+#define PRIMESL_OMAT_OFFSET2 ((0x39e3 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 offset1 // unsigned , default = 2048 = 'h2048
+//Bit 15:12 reserved
+//Bit 11: 0 offset2 // unsigned , default = 2048 = 'h2048
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_primesl_regs.h
+//
+//oxa0-0xaf
+//
+// Reading file: vpp_post2_mat_3x5_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VPP_POST2_MATRIX_COEF00_01 ((0x39a0 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef00 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef01 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF02_10 ((0x39a1 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef02 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef10 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF11_12 ((0x39a2 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef11 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef12 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF20_21 ((0x39a3 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef20 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef21 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF22 ((0x39a4 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 coef22 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF13_14 ((0x39a5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef13 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef14 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF23_24 ((0x39a6 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef23 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef24 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF15_25 ((0x39a7 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef15 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef25 //signed , default = 0
+#define VPP_POST2_MATRIX_CLIP ((0x39a8 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:8 comp_thrd0 // signed ,default == 0, mat clip enable
+//Bit 7:5 conv_rs // unsigned ,default == 0, mat rs
+//Bit 4:3 clmod // unsigned ,default == 0, mat clmod
+#define VPP_POST2_MATRIX_OFFSET0_1 ((0x39a9 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 offset0 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 offset1 //signed , default = 0
+#define VPP_POST2_MATRIX_OFFSET2 ((0x39aa << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 offset2 //signed , default = 0
+#define VPP_POST2_MATRIX_PRE_OFFSET0_1 ((0x39ab << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 pre_offset0 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 pre_offset1 //signed , default = 0
+#define VPP_POST2_MATRIX_PRE_OFFSET2 ((0x39ac << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 pre_offset2 //signed , default = 0
+#define VPP_POST2_MATRIX_EN_CTRL ((0x39ad << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_post2_mat_3x5_regs.h
+//
+//0xb0-0xcf
+//
+// Reading file: osd_blend_reg.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VIU_OSD_BLEND_CTRL ((0x39b0 << 2) + 0xff000000)
+//Bit 31:29 hold_lines //unsigned , default = 3'h0
+//Bit 28:27 blend2_premult_en //unsigned , default = 2'h3
+//Bit 26 din0_byp_blend //unsigned , default = 1'h1
+//Bit 25 din2_osd_sel //unsigned , default = 1'h1
+//Bit 24 din3_osd_sel //unsigned , default = 1'h1
+//Bit 23:20 blend_din_en //unsigned , default = 4'h5
+//Bit 19:16 din_premult_en //unsigned , default = 4'h0
+//Bit 15:0 din_reoder_sel //unsigned , default = 16'h2341
+#define VIU_OSD_BLEND_CTRL1 ((0x39c0 << 2) + 0xff000000)
+//Bit 31:6 reserved
+//Bit 5:4 reg_alp_mapping_mode
+//Bit 2:1 reg_div_gclk_en
+//Bit 0 reg_div_alpha_en
+#define VIU_OSD_BLEND_DIN0_SCOPE_H ((0x39b1 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din0_h_end ///unsigned , default = 13'h2d0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din0_h_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN0_SCOPE_V ((0x39b2 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din0_v_end ///unsigned , default = 13'h1e0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din0_v_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN1_SCOPE_H ((0x39b3 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din1_h_end ///unsigned , default = 13'h2d0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din1_h_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN1_SCOPE_V ((0x39b4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din1_v_end ///unsigned , default = 13'h1e0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din1_v_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN2_SCOPE_H ((0x39b5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din2_h_end ///unsigned , default = 13'h2d0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din2_h_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN2_SCOPE_V ((0x39b6 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din2_v_end ///unsigned , default = 13'h1e0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din2_v_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN3_SCOPE_H ((0x39b7 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din3_h_end ///unsigned , default = 13'h2d0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din3_h_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN3_SCOPE_V ((0x39b8 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din3_v_end ///unsigned , default = 13'h1e0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din3_v_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DUMMY_DATA0 ((0x39b9 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 23:16 blend0_dummy_data_y //unsigned , default = 8'h00
+//Bit 15:8 blend0_dummy_data_cb //unsigned , default = 8'h80
+//Bit 7:0 blend0_dummy_data_cr //unsigned , default = 8'h80
+#define VIU_OSD_BLEND_DUMMY_ALPHA ((0x39ba << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:20 blend0_dummy_alpha //unsigned , default = 9'h0
+//Bit 19:11 blend1_dummy_alpha //unsigned , default = 9'h0
+//Bit 8:0 blend2_dummy_alpha //unsigned , default = 9'h0
+#define VIU_OSD_BLEND_BLEND0_SIZE ((0x39bb << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 blend0_vsize //unsigned , default = 13'h1e0
+//Bit 15:13 reserved
+//Bit 12:0 blend0_hsize //unsigned , default = 13'h2d0
+#define VIU_OSD_BLEND_BLEND1_SIZE ((0x39bc << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 blend1_vsize //unsigned , default = 13'h1e0
+//Bit 15:13 reserved
+//Bit 12:0 blend1_hsize ///unsigned , default = 13'h2d0
+//`define VIU_OSD_BLEND_DOUT0_HV_START 8'hbd
+//Bit 31:29 reserved
+//Bit 28:0 osd_blend_dout0_hv_start //unsigned , default = 29'h0
+//`define VIU_OSD_BLEND_DOUT1_HV_START 8'hbe
+//Bit 31:29 reserved
+//Bit 28:0 osd_blend_dout1_hv_start //unsigned , default = 29'h0
+#define VIU_OSD_HOLD_LINE_HIGH_BITS ((0x39c1 << 2) + 0xff000000)
+//Bit 31:8 reserved
+//Bit 7:0 hold_line_high_bits //unsigned , default = 32'h0
+#define VIU_OSD_BLEND_RO_CURRENT_XY ((0x39bf << 2) + 0xff000000)
+//Bit 31:0 ro_blend2_current_xy //unsigned , default = 32'h0
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: osd_blend_reg.h
+//
+#define VPP_LUT3D_CTRL ((0x39d0 << 2) + 0xff000000)
+#define VPP_LUT3D_CBUS2RAM_CTRL ((0x39d1 << 2) + 0xff000000)
+#define VPP_LUT3D_RAM_ADDR ((0x39d2 << 2) + 0xff000000)
+#define VPP_LUT3D_RAM_DATA ((0x39d3 << 2) + 0xff000000)
+#define VPP_GAMMA_CTRL ((0x39d4 << 2) + 0xff000000)
+#define VPP_GAMMA_BIN_ADDR ((0x39d5 << 2) + 0xff000000)
+#define VPP_GAMMA_BIN_DATA ((0x39d6 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_misc_regs.h
+//
+//========================================================================
+// MALI AFBCD
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: VPP_AFBCD0_VCBUS_BASE = 0x3a
+// -----------------------------------------------
+//
+// Reading file: vpp_mali_tx300_afbc_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+ //0x00 - 0x80
+#define VPU_MAFBC_BLOCK_ID ((0x3a00 << 2) + 0xff000000)
+#define VPU_MAFBC_IRQ_RAW_STATUS ((0x3a01 << 2) + 0xff000000)
+#define VPU_MAFBC_IRQ_CLEAR ((0x3a02 << 2) + 0xff000000)
+#define VPU_MAFBC_IRQ_MASK ((0x3a03 << 2) + 0xff000000)
+#define VPU_MAFBC_IRQ_STATUS ((0x3a04 << 2) + 0xff000000)
+#define VPU_MAFBC_COMMAND ((0x3a05 << 2) + 0xff000000)
+#define VPU_MAFBC_STATUS ((0x3a06 << 2) + 0xff000000)
+#define VPU_MAFBC_SURFACE_CFG ((0x3a07 << 2) + 0xff000000)
+#define VPU_MAFBC_AXI_CFG ((0x3a08 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0 ((0x3a10 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0 ((0x3a11 << 2) + 0xff000000)
+#define VPU_MAFBC_FORMAT_SPECIFIER_S0 ((0x3a12 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_WIDTH_S0 ((0x3a13 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_HEIGHT_S0 ((0x3a14 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_START_S0 ((0x3a15 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_END_S0 ((0x3a16 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_START_S0 ((0x3a17 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_END_S0 ((0x3a18 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S0 ((0x3a19 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0 ((0x3a1a << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S0 ((0x3a1b << 2) + 0xff000000)
+#define VPU_MAFBC_PREFETCH_CFG_S0 ((0x3a1c << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_LOW_S0 ((0x3a1d << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_HIGH_S0 ((0x3a1e << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_LOW_S0 ((0x3a1f << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_HIGH_S0 ((0x3a20 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1 ((0x3a30 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S1 ((0x3a31 << 2) + 0xff000000)
+#define VPU_MAFBC_FORMAT_SPECIFIER_S1 ((0x3a32 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_WIDTH_S1 ((0x3a33 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_HEIGHT_S1 ((0x3a34 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_START_S1 ((0x3a35 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_END_S1 ((0x3a36 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_START_S1 ((0x3a37 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_END_S1 ((0x3a38 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S1 ((0x3a39 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S1 ((0x3a3a << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S1 ((0x3a3b << 2) + 0xff000000)
+#define VPU_MAFBC_PREFETCH_CFG_S1 ((0x3a3c << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_LOW_S1 ((0x3a3d << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_HIGH_S1 ((0x3a3e << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_LOW_S1 ((0x3a3f << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_HIGH_S1 ((0x3a40 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2 ((0x3a50 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S2 ((0x3a51 << 2) + 0xff000000)
+#define VPU_MAFBC_FORMAT_SPECIFIER_S2 ((0x3a52 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_WIDTH_S2 ((0x3a53 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_HEIGHT_S2 ((0x3a54 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_START_S2 ((0x3a55 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_END_S2 ((0x3a56 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_START_S2 ((0x3a57 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_END_S2 ((0x3a58 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S2 ((0x3a59 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S2 ((0x3a5a << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S2 ((0x3a5b << 2) + 0xff000000)
+#define VPU_MAFBC_PREFETCH_CFG_S2 ((0x3a5c << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_LOW_S2 ((0x3a5d << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_HIGH_S2 ((0x3a5e << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_LOW_S2 ((0x3a5f << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_HIGH_S2 ((0x3a60 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S3 ((0x3a70 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S3 ((0x3a71 << 2) + 0xff000000)
+#define VPU_MAFBC_FORMAT_SPECIFIER_S3 ((0x3a72 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_WIDTH_S3 ((0x3a73 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_HEIGHT_S3 ((0x3a74 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_START_S3 ((0x3a75 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_END_S3 ((0x3a76 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_START_S3 ((0x3a77 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_END_S3 ((0x3a78 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S3 ((0x3a79 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S3 ((0x3a7a << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S3 ((0x3a7b << 2) + 0xff000000)
+#define VPU_MAFBC_PREFETCH_CFG_S3 ((0x3a7c << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_LOW_S3 ((0x3a7d << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_HIGH_S3 ((0x3a7e << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_LOW_S3 ((0x3a7f << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_HIGH_S3 ((0x3a80 << 2) + 0xff000000)
+ // synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_mali_tx300_afbc_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: VPP_AFBCD1_VCBUS_BASE = 0x3b
+// -----------------------------------------------
+// -----------------------------------------------
+// REG_BASE: VPP_AFBCD2_VCBUS_BASE = 0x3c
+// -----------------------------------------------
+// -----------------------------------------------
+// REG_BASE: VPU_OSDSC_BLD_VCBUS_BASE = 0x3d
+// -----------------------------------------------
+//
+// Reading file: vpu_osdsc_bld_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//vertical scaler phase step
+//Bit 27:0, 4.24 format
+#define OSD2_VSC_PHASE_STEP ((0x3d00 << 2) + 0xff000000)
+//Bit 31:16, botttom vertical scaler initial phase
+//Bit 15:0, top vertical scaler initial phase
+#define OSD2_VSC_INI_PHASE ((0x3d01 << 2) + 0xff000000)
+//Bit 24 osd vertical Scaler enable
+//Bit 23 osd_prog_interlace 0: current field is progressive, 1: current field is interlace
+//Bit 22:21 osd_vsc_double_line_mode, bit1, double input width and half input height, bit0, change line buffer becomes 2 lines
+//Bit 20 osd_vsc_phase0_always_en
+//Bit 19 osd_vsc_nearest_en
+//Bit 17:16 osd_vsc_bot_rpt_l0_num
+//Bit 14:11 osd_vsc_bot_ini_rcv_num
+//Bit 9:8 osd_vsc_top_rpt_l0_num
+//Bit 6:3 osd_vsc_top_ini_rcv_num
+//Bit 2:0 osd_vsc_bank_length
+#define OSD2_VSC_CTRL0 ((0x3d02 << 2) + 0xff000000)
+//horizontal scaler phase step
+//Bit 27:0, 4.24 format
+#define OSD2_HSC_PHASE_STEP ((0x3d03 << 2) + 0xff000000)
+//Bit 31:16, horizontal scaler initial phase1
+//Bit 15:0, horizontal scaler initial phase0
+#define OSD2_HSC_INI_PHASE ((0x3d04 << 2) + 0xff000000)
+//Bit 22 osd horizontal scaler enable
+//Bit 21 osd_hsc_double_pix_mode
+//Bit 20 osd_hsc_phase0_always_en
+//Bit 19 osd_hsc_nearest_en
+//Bit 17:16 osd_hsc_rpt_p0_num1
+//Bit 14:11 osd_hsc_ini_rcv_num1
+//Bit 9:8 osd_hsc_rpt_p0_num0
+//Bit 6:3 osd_hsc_ini_rcv_num0
+//Bit 2:0 osd_hsc_bank_length
+#define OSD2_HSC_CTRL0 ((0x3d05 << 2) + 0xff000000)
+//for 3D quincunx sub-sampling
+//bit 15:8 pattern, each patten 1 bit, from lsb -> msb
+//bit 6:4 pattern start
+//bit 2:0 pattern end
+#define OSD2_HSC_INI_PAT_CTRL ((0x3d06 << 2) + 0xff000000)
+//bit 31:24, componet 0
+//bit 23:16, component 1
+//bit 15:8, component 2
+//bit 7:0 component 3, alpha
+#define OSD2_SC_DUMMY_DATA ((0x3d07 << 2) + 0xff000000)
+//Bit 14 osc_sc_din_osd1_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 13 osc_sc_din_osd2_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 12 osc_sc_dout_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 12 osc_sc_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 11:4 default alpha for vd1 or vd2 if they are selected as the source
+//Bit 3 osd scaler path enable
+//Bit 1:0 osd_sc_sel, 00: select osd1 input, 01: select osd2 input, 10: select vd1 input, 11: select vd2 input after matrix
+#define OSD2_SC_CTRL0 ((0x3d08 << 2) + 0xff000000)
+//Bit 28:16 OSD scaler input width minus 1
+//Bit 12:0 OSD scaler input height minus 1
+#define OSD2_SCI_WH_M1 ((0x3d09 << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output horizontal start
+//Bit 12:0 OSD scaler output horizontal end
+#define OSD2_SCO_H_START_END ((0x3d0a << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output vertical start
+//Bit 12:0 OSD scaler output vertical end
+#define OSD2_SCO_V_START_END ((0x3d0b << 2) + 0xff000000)
+#define OSD2_DB_FLT_CTRL ((0x3d0c << 2) + 0xff000000)
+//Bit 31:27 reserved
+//Bit 26 reg_nrdeband_reset1 // unsigned , default = 1 , 0 : no reload chrm seed 1: reload chrm seed
+//Bit 25 reg_nrdeband_reset0 // unsigned , default = 1 , 0 : no reload luma seed 1: reload luma seed
+//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 , 0 : yuv 1: RGB
+//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
+//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
+//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
+//Bit 16 reserved
+//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
+//Bit 12 reserved
+//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6
+//Bit 8 reserved
+//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 , debanding random hp portion xor, [0] for luma
+//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 , debanding random hp portion xor, [1] for chroma
+//Bit 5 reg_nrdeband_en1 // unsigned , default = 0 , debanding registers, for luma
+//Bit 4 reg_nrdeband_en0 // unsigned , default = 0 , debanding registers, for chroma
+//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+#define OSD2_DB_FLT_CTRL1 ((0x3d0d << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:16 reg_nrdeband_noise_rs // unsigned , default = 2
+//Bit 15:12 reg_nrdeband_randgain // unsigned , default = 8
+//Bit 11 reserved
+//Bit 10: 8 reg_nrdeband_bandrand5 // unsigned , default = 6
+//Bit 7 reserved
+//Bit 6: 4 reg_nrdeband_bandrand4 // unsigned , default = 6
+//Bit 3 reserved
+//Bit 2: 0 reg_nrdeband_bandrand3 // unsigned , default = 6
+#define OSD2_DB_FLT_LUMA_THRD ((0x3d0e << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_luma_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_luma_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_luma_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_luma_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else
+#define OSD2_DB_FLT_CHRM_THRD ((0x3d0f << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_chrm_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_chrm_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_chrm_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_chrm_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif
+#define OSD2_DB_FLT_RANDLUT ((0x3d10 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:21 reg_nrdeband_randslut7 // unsigned , default = 1 rand lut7
+//Bit 20:18 reg_nrdeband_randslut6 // unsigned , default = 1 rand lut6
+//Bit 17:15 reg_nrdeband_randslut5 // unsigned , default = 1 rand lut5
+//Bit 14:12 reg_nrdeband_randslut4 // unsigned , default = 1 rand lut4
+//Bit 11: 9 reg_nrdeband_randslut3 // unsigned , default = 1 rand lut3
+//Bit 8: 6 reg_nrdeband_randslut2 // unsigned , default = 1 rand lut2
+//Bit 5: 3 reg_nrdeband_randslut1 // unsigned , default = 1 rand lut1
+//Bit 2: 0 reg_nrdeband_randslut0 // unsigned , default = 1 rand lut0
+#define OSD2_DB_FLT_PXI_THRD ((0x3d11 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+//Bit 15:10 reserved
+//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+#define OSD2_DB_FLT_SEED_Y ((0x3d12 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 ,debanding noise adding seed for Y. seed[0]= 0x60a52f20; as default
+#define OSD2_DB_FLT_SEED_U ((0x3d13 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 ,debanding noise adding seed for U. seed[0]= 0x60a52f27; as default
+#define OSD2_DB_FLT_SEED_V ((0x3d14 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD2_DB_FLT_SEED3 ((0x3d15 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed3 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD2_DB_FLT_SEED4 ((0x3d16 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed4 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD2_DB_FLT_SEED5 ((0x3d17 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed5 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD2_SCALE_COEF_IDX ((0x3d18 << 2) + 0xff000000)
+//coefficients for vertical filter and horizontal filter
+#define OSD2_SCALE_COEF ((0x3d19 << 2) + 0xff000000)
+#define OSD34_SCALE_COEF_IDX ((0x3d1e << 2) + 0xff000000)
+//coefficients for vertical filter and horizontal filter
+#define OSD34_SCALE_COEF ((0x3d1f << 2) + 0xff000000)
+//vertical scaler phase step
+//Bit 27:0, 4.24 format
+#define OSD34_VSC_PHASE_STEP ((0x3d20 << 2) + 0xff000000)
+//Bit 31:16, botttom vertical scaler initial phase
+//Bit 15:0, top vertical scaler initial phase
+#define OSD34_VSC_INI_PHASE ((0x3d21 << 2) + 0xff000000)
+//Bit 24 osd vertical Scaler enable
+//Bit 23 osd_prog_interlace 0: current field is progressive, 1: current field is interlace
+//Bit 22:21 osd_vsc_double_line_mode, bit1, double input width and half input height, bit0, change line buffer becomes 2 lines
+//Bit 20 osd_vsc_phase0_always_en
+//Bit 19 osd_vsc_nearest_en
+//Bit 17:16 osd_vsc_bot_rpt_l0_num
+//Bit 14:11 osd_vsc_bot_ini_rcv_num
+//Bit 9:8 osd_vsc_top_rpt_l0_num
+//Bit 6:3 osd_vsc_top_ini_rcv_num
+//Bit 2:0 osd_vsc_bank_length
+#define OSD34_VSC_CTRL0 ((0x3d22 << 2) + 0xff000000)
+//horizontal scaler phase step
+//Bit 27:0, 4.24 format
+#define OSD34_HSC_PHASE_STEP ((0x3d23 << 2) + 0xff000000)
+//Bit 31:16, horizontal scaler initial phase1
+//Bit 15:0, horizontal scaler initial phase0
+#define OSD34_HSC_INI_PHASE ((0x3d24 << 2) + 0xff000000)
+//Bit 22 osd horizontal scaler enable
+//Bit 21 osd_hsc_double_pix_mode
+//Bit 20 osd_hsc_phase0_always_en
+//Bit 19 osd_hsc_nearest_en
+//Bit 17:16 osd_hsc_rpt_p0_num1
+//Bit 14:11 osd_hsc_ini_rcv_num1
+//Bit 9:8 osd_hsc_rpt_p0_num0
+//Bit 6:3 osd_hsc_ini_rcv_num0
+//Bit 2:0 osd_hsc_bank_length
+#define OSD34_HSC_CTRL0 ((0x3d25 << 2) + 0xff000000)
+//for 3D quincunx sub-sampling
+//bit 15:8 pattern, each patten 1 bit, from lsb -> msb
+//bit 6:4 pattern start
+//bit 2:0 pattern end
+#define OSD34_HSC_INI_PAT_CTRL ((0x3d26 << 2) + 0xff000000)
+//bit 31:24, componet 0
+//bit 23:16, component 1
+//bit 15:8, component 2
+//bit 7:0 component 3, alpha
+#define OSD34_SC_DUMMY_DATA ((0x3d27 << 2) + 0xff000000)
+//Bit 14 osc_sc_din_osd1_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 13 osc_sc_din_osd2_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 12 osc_sc_dout_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 12 osc_sc_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 11:4 default alpha for vd1 or vd2 if they are selected as the source
+//Bit 3 osd scaler path enable
+//Bit 1:0 osd_sc_sel, 00: select osd1 input, 01: select osd2 input, 10: select vd1 input, 11: select vd2 input after matrix
+#define OSD34_SC_CTRL0 ((0x3d28 << 2) + 0xff000000)
+//Bit 28:16 OSD scaler input width minus 1
+//Bit 12:0 OSD scaler input height minus 1
+#define OSD34_SCI_WH_M1 ((0x3d29 << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output horizontal start
+//Bit 12:0 OSD scaler output horizontal end
+#define OSD34_SCO_H_START_END ((0x3d2a << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output vertical start
+//Bit 12:0 OSD scaler output vertical end
+#define OSD34_SCO_V_START_END ((0x3d2b << 2) + 0xff000000)
+#define OSD34_DB_FLT_CTRL ((0x3d2c << 2) + 0xff000000)
+//Bit 31:27 reserved
+//Bit 26 reg_nrdeband_reset1 // unsigned , default = 1 , 0 : no reload chrm seed 1: reload chrm seed
+//Bit 25 reg_nrdeband_reset0 // unsigned , default = 1 , 0 : no reload luma seed 1: reload luma seed
+//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 , 0 : yuv 1: RGB
+//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
+//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
+//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
+//Bit 16 reserved
+//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
+//Bit 12 reserved
+//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6
+//Bit 8 reserved
+//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 , debanding random hp portion xor, [0] for luma
+//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 , debanding random hp portion xor, [1] for chroma
+//Bit 5 reg_nrdeband_en1 // unsigned , default = 0 , debanding registers, for luma
+//Bit 4 reg_nrdeband_en0 // unsigned , default = 0 , debanding registers, for chroma
+//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+#define OSD34_DB_FLT_CTRL1 ((0x3d2d << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:16 reg_nrdeband_noise_rs // unsigned , default = 2
+//Bit 15:12 reg_nrdeband_randgain // unsigned , default = 8
+//Bit 11 reserved
+//Bit 10: 8 reg_nrdeband_bandrand5 // unsigned , default = 6
+//Bit 7 reserved
+//Bit 6: 4 reg_nrdeband_bandrand4 // unsigned , default = 6
+//Bit 3 reserved
+//Bit 2: 0 reg_nrdeband_bandrand3 // unsigned , default = 6
+#define OSD34_DB_FLT_LUMA_THRD ((0x3d2e << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_luma_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_luma_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_luma_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_luma_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else
+#define OSD34_DB_FLT_CHRM_THRD ((0x3d2f << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_chrm_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_chrm_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_chrm_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_chrm_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif
+#define OSD34_DB_FLT_RANDLUT ((0x3d30 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:21 reg_nrdeband_randslut7 // unsigned , default = 1 rand lut7
+//Bit 20:18 reg_nrdeband_randslut6 // unsigned , default = 1 rand lut6
+//Bit 17:15 reg_nrdeband_randslut5 // unsigned , default = 1 rand lut5
+//Bit 14:12 reg_nrdeband_randslut4 // unsigned , default = 1 rand lut4
+//Bit 11: 9 reg_nrdeband_randslut3 // unsigned , default = 1 rand lut3
+//Bit 8: 6 reg_nrdeband_randslut2 // unsigned , default = 1 rand lut2
+//Bit 5: 3 reg_nrdeband_randslut1 // unsigned , default = 1 rand lut1
+//Bit 2: 0 reg_nrdeband_randslut0 // unsigned , default = 1 rand lut0
+#define OSD34_DB_FLT_PXI_THRD ((0x3d31 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+//Bit 15:10 reserved
+//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+#define OSD34_DB_FLT_SEED_Y ((0x3d32 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 ,debanding noise adding seed for Y. seed[0]= 0x60a52f20; as default
+#define OSD34_DB_FLT_SEED_U ((0x3d33 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 ,debanding noise adding seed for U. seed[0]= 0x60a52f27; as default
+#define OSD34_DB_FLT_SEED_V ((0x3d34 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD34_DB_FLT_SEED3 ((0x3d35 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed3 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD34_DB_FLT_SEED4 ((0x3d36 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed4 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD34_DB_FLT_SEED5 ((0x3d37 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed5 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+// for osd3 & osd4 blend
+#define OSD34_OUT_HSCOPE ((0x3d40 << 2) + 0xff000000)
+#define OSD34_OUT_VSCOPE ((0x3d41 << 2) + 0xff000000)
+#define OSD34_DUMMY_DATA ((0x3d42 << 2) + 0xff000000)
+#define OSD34_BLEND_CTRL0 ((0x3d43 << 2) + 0xff000000)
+#define OSD34_BLEND_CTRL1 ((0x3d44 << 2) + 0xff000000)
+#define OSD34_RO_HV_CNT ((0x3d45 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF00_01 ((0x3d60 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF02_10 ((0x3d61 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF11_12 ((0x3d62 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF20_21 ((0x3d63 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF22 ((0x3d64 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF13_14 ((0x3d65 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF23_24 ((0x3d66 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF15_25 ((0x3d67 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_CLIP ((0x3d68 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_OFFSET0_1 ((0x3d69 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_OFFSET2 ((0x3d6a << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1 ((0x3d6b << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2 ((0x3d6c << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_EN_CTRL ((0x3d6d << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF00_01 ((0x3d70 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF02_10 ((0x3d71 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF11_12 ((0x3d72 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF20_21 ((0x3d73 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF22 ((0x3d74 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF13_14 ((0x3d75 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF23_24 ((0x3d76 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF15_25 ((0x3d77 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_CLIP ((0x3d78 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_OFFSET0_1 ((0x3d79 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_OFFSET2 ((0x3d7a << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1 ((0x3d7b << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2 ((0x3d7c << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_EN_CTRL ((0x3d7d << 2) + 0xff000000)
+#define VIU_OSD3_CTRL_STAT ((0x3d80 << 2) + 0xff000000)
+#define VIU_OSD3_CTRL_STAT2 ((0x3d81 << 2) + 0xff000000)
+#define VIU_OSD3_COLOR_ADDR ((0x3d82 << 2) + 0xff000000)
+#define VIU_OSD3_COLOR ((0x3d83 << 2) + 0xff000000)
+#define VIU_OSD3_TCOLOR_AG0 ((0x3d84 << 2) + 0xff000000)
+#define VIU_OSD3_TCOLOR_AG1 ((0x3d85 << 2) + 0xff000000)
+#define VIU_OSD3_TCOLOR_AG2 ((0x3d86 << 2) + 0xff000000)
+#define VIU_OSD3_TCOLOR_AG3 ((0x3d87 << 2) + 0xff000000)
+#define VIU_OSD3_BLK0_CFG_W0 ((0x3d88 << 2) + 0xff000000)
+#define VIU_OSD3_BLK1_CFG_W0 ((0x3d89 << 2) + 0xff000000)
+#define VIU_OSD3_BLK2_CFG_W0 ((0x3d8a << 2) + 0xff000000)
+#define VIU_OSD3_BLK3_CFG_W0 ((0x3d8b << 2) + 0xff000000)
+#define VIU_OSD3_BLK0_CFG_W1 ((0x3d8c << 2) + 0xff000000)
+#define VIU_OSD3_BLK1_CFG_W1 ((0x3d8d << 2) + 0xff000000)
+#define VIU_OSD3_BLK2_CFG_W1 ((0x3d8e << 2) + 0xff000000)
+#define VIU_OSD3_BLK3_CFG_W1 ((0x3d8f << 2) + 0xff000000)
+#define VIU_OSD3_BLK0_CFG_W2 ((0x3d90 << 2) + 0xff000000)
+#define VIU_OSD3_BLK1_CFG_W2 ((0x3d91 << 2) + 0xff000000)
+#define VIU_OSD3_BLK2_CFG_W2 ((0x3d92 << 2) + 0xff000000)
+#define VIU_OSD3_BLK3_CFG_W2 ((0x3d93 << 2) + 0xff000000)
+#define VIU_OSD3_BLK0_CFG_W3 ((0x3d94 << 2) + 0xff000000)
+#define VIU_OSD3_BLK1_CFG_W3 ((0x3d95 << 2) + 0xff000000)
+#define VIU_OSD3_BLK2_CFG_W3 ((0x3d96 << 2) + 0xff000000)
+#define VIU_OSD3_BLK3_CFG_W3 ((0x3d97 << 2) + 0xff000000)
+#define VIU_OSD3_BLK0_CFG_W4 ((0x3d98 << 2) + 0xff000000)
+#define VIU_OSD3_BLK1_CFG_W4 ((0x3d99 << 2) + 0xff000000)
+#define VIU_OSD3_BLK2_CFG_W4 ((0x3d9a << 2) + 0xff000000)
+#define VIU_OSD3_BLK3_CFG_W4 ((0x3d9b << 2) + 0xff000000)
+#define VIU_OSD3_FIFO_CTRL_STAT ((0x3d9c << 2) + 0xff000000)
+#define VIU_OSD3_TEST_RDDATA ((0x3d9d << 2) + 0xff000000)
+#define VIU_OSD3_PROT_CTRL ((0x3d9e << 2) + 0xff000000)
+#define VIU_OSD3_MALI_UNPACK_CTRL ((0x3d9f << 2) + 0xff000000)
+#define VIU_OSD3_DIMM_CTRL ((0x3da0 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF00_01 ((0x3db0 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF02_10 ((0x3db1 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF11_12 ((0x3db2 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF20_21 ((0x3db3 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF22 ((0x3db4 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF13_14 ((0x3db5 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF23_24 ((0x3db6 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF15_25 ((0x3db7 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_CLIP ((0x3db8 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_OFFSET0_1 ((0x3db9 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_OFFSET2 ((0x3dba << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_PRE_OFFSET0_1 ((0x3dbb << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_PRE_OFFSET2 ((0x3dbc << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_EN_CTRL ((0x3dbd << 2) + 0xff000000)
+#define VIU_OSD4_CTRL_STAT ((0x3dc0 << 2) + 0xff000000)
+#define VIU_OSD4_CTRL_STAT2 ((0x3dc1 << 2) + 0xff000000)
+#define VIU_OSD4_COLOR_ADDR ((0x3dc2 << 2) + 0xff000000)
+#define VIU_OSD4_COLOR ((0x3dc3 << 2) + 0xff000000)
+#define VIU_OSD4_TCOLOR_AG0 ((0x3dc4 << 2) + 0xff000000)
+#define VIU_OSD4_TCOLOR_AG1 ((0x3dc5 << 2) + 0xff000000)
+#define VIU_OSD4_TCOLOR_AG2 ((0x3dc6 << 2) + 0xff000000)
+#define VIU_OSD4_TCOLOR_AG3 ((0x3dc7 << 2) + 0xff000000)
+#define VIU_OSD4_BLK0_CFG_W0 ((0x3dc8 << 2) + 0xff000000)
+#define VIU_OSD4_BLK1_CFG_W0 ((0x3dc9 << 2) + 0xff000000)
+#define VIU_OSD4_BLK2_CFG_W0 ((0x3dca << 2) + 0xff000000)
+#define VIU_OSD4_BLK3_CFG_W0 ((0x3dcb << 2) + 0xff000000)
+#define VIU_OSD4_BLK0_CFG_W1 ((0x3dcc << 2) + 0xff000000)
+#define VIU_OSD4_BLK1_CFG_W1 ((0x3dcd << 2) + 0xff000000)
+#define VIU_OSD4_BLK2_CFG_W1 ((0x3dce << 2) + 0xff000000)
+#define VIU_OSD4_BLK3_CFG_W1 ((0x3dcf << 2) + 0xff000000)
+#define VIU_OSD4_BLK0_CFG_W2 ((0x3dd0 << 2) + 0xff000000)
+#define VIU_OSD4_BLK1_CFG_W2 ((0x3dd1 << 2) + 0xff000000)
+#define VIU_OSD4_BLK2_CFG_W2 ((0x3dd2 << 2) + 0xff000000)
+#define VIU_OSD4_BLK3_CFG_W2 ((0x3dd3 << 2) + 0xff000000)
+#define VIU_OSD4_BLK0_CFG_W3 ((0x3dd4 << 2) + 0xff000000)
+#define VIU_OSD4_BLK1_CFG_W3 ((0x3dd5 << 2) + 0xff000000)
+#define VIU_OSD4_BLK2_CFG_W3 ((0x3dd6 << 2) + 0xff000000)
+#define VIU_OSD4_BLK3_CFG_W3 ((0x3dd7 << 2) + 0xff000000)
+#define VIU_OSD4_BLK0_CFG_W4 ((0x3dd8 << 2) + 0xff000000)
+#define VIU_OSD4_BLK1_CFG_W4 ((0x3dd9 << 2) + 0xff000000)
+#define VIU_OSD4_BLK2_CFG_W4 ((0x3dda << 2) + 0xff000000)
+#define VIU_OSD4_BLK3_CFG_W4 ((0x3ddb << 2) + 0xff000000)
+#define VIU_OSD4_FIFO_CTRL_STAT ((0x3ddc << 2) + 0xff000000)
+#define VIU_OSD4_TEST_RDDATA ((0x3ddd << 2) + 0xff000000)
+#define VIU_OSD4_PROT_CTRL ((0x3dde << 2) + 0xff000000)
+#define VIU_OSD4_MALI_UNPACK_CTRL ((0x3ddf << 2) + 0xff000000)
+#define VIU_OSD4_DIMM_CTRL ((0x3de0 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF00_01 ((0x3df0 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF02_10 ((0x3df1 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF11_12 ((0x3df2 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF20_21 ((0x3df3 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF22 ((0x3df4 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF13_14 ((0x3df5 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF23_24 ((0x3df6 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF15_25 ((0x3df7 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_CLIP ((0x3df8 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_OFFSET0_1 ((0x3df9 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_OFFSET2 ((0x3dfa << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_PRE_OFFSET0_1 ((0x3dfb << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_PRE_OFFSET2 ((0x3dfc << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_EN_CTRL ((0x3dfd << 2) + 0xff000000)
+ // synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_osdsc_bld_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: VPPF_VCBUS_BASE = 0x40
+// -----------------------------------------------
+//
+// Reading file: lc_stts_curve.h
+//
+#define LC_CURVE_CTRL ((0x4000 << 2) + 0xff000000)
+ //Bit 31 :12 reg_lc_misc U RW default = 'h0 None
+ //Bit 11 :10 reserved U RW default = 'h0 None
+ //Bit 9 :8 reg_lc_hist_curve_nodes_hlpf U RW default = 'h1 horizontal lpf of the ram_curve_nodes, 0: no LPF, 1= [1 2 1]; 2: [1 2 2 2 1]/8
+ //Bit 7 :6 reserved U RW default = 'h0 None
+ //Bit 5 :4 reg_lc_hist_curve_nodes_vlpf U RW default = 'h1 vertical lpf of the ram_curve_nodes, 0: no LPF, 1= [1 2 1]; 2: [1 2 2 2 1]/8
+ //Bit 3 :2 reserved U RW default = 'h0 None
+ //Bit 1 reg_lc_blackbar_mute_en U RW default = 'h1 mute the black bar corresponding bin, 0: no mute, 1: mute enable; default=1
+ //Bit 0 reg_lc_curve_en U RW default = 'h1 default=0
+#define LC_CURVE_HV_NUM ((0x4001 << 2) + 0xff000000)
+ //Bit 31 :13 reserved U RW default = 'h0 None
+ //Bit 12 :8 reg_lc_cur_blk_hnum U RW default = 'hc lc processing region number of V, maximum to (STA_LEN_V-1) (0~8), should be same as reg_lc_blk_hnum
+ //Bit 7 :5 reserved U RW default = 'h0 None
+ //Bit 4 :0 reg_lc_cur_blk_vnum U RW default = 'h8 lc processing region number of H, maximum to (STA_LEN_H-1) (0~12), should be same as reg_lc_blk_vnum
+#define LC_CURVE_LMT_RAT ((0x4002 << 2) + 0xff000000)
+ //Bit 31 :16 reserved U RW default = 'h0 None
+ //Bit 15 :8 reg_lmtrat_minmax U RW default = 'h6 x/1024 of amount
+ //Bit 7 :0 reg_lmtrat_valid U RW default = 'h14 x/1024 of amount
+#define LC_CURVE_CONTRAST_LH ((0x4003 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_contrast_low U RW default = 'h10 contrast gain to the lc for dark side, normalized 256 as "1", set adaptive TODO
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_contrast_hig U RW default = 'h18 contrast gain to the lc for bright side, normalized 256 as "1"
+#define LC_CURVE_CONTRAST__LMT_LH ((0x4004 << 2) + 0xff000000)
+ //Bit 31 :24 reg_lc_cntstlmt_low_0 U RW default = 'ha limit for the contrast low, delta_low = MIN(delta_low, MIN( MAX((minBV-min_val)*scl_low/8, lmt_low[0]),lmt_low[1]))
+ //Bit 23 :16 reg_lc_cntstlmt_hig_0 U RW default = 'h14 limit for the contrast high,delta_hig = MIN(delta_hig, MIN( MAX((max_val-maxBV)*scl_hig/8, lmt_hig[0]),lmt_hig[1]))
+ //Bit 15 :8 reg_lc_cntstlmt_low_1 U RW default = 'hff limit for the contrast low, delta_low = MIN(delta_low, MIN( MAX((minBV-min_val)*scl_low/8, lmt_low[0]),lmt_low[1]))
+ //Bit 7 :0 reg_lc_cntstlmt_hig_1 U RW default = 'hff limit for the contrast high,delta_hig = MIN(delta_hig, MIN( MAX((max_val-maxBV)*scl_hig/8, lmt_hig[0]),lmt_hig[1]))
+#define LC_CURVE_CONTRAST_SCL_LH ((0x4005 << 2) + 0xff000000)
+ //Bit 31 :16 reserved U RW default = 'h0 None
+ //Bit 15 :8 reg_lc_cntstscl_low U RW default = 'h40 scale for the contrast low, norm 8 as 1; delta_low = MIN(delta_low, MIN(MAX((minBV-min_val)*scl_low/8, lmt_low[0]),lmt_low[1]))
+ //Bit 7 :0 reg_lc_cntstscl_hig U RW default = 'h20 scale for the contrast high,norm 8 as 1; delta_hig = MIN(delta_hig, MIN(MAX((max_val-maxBV)*scl_hig/8, lmt_hig[0]),lmt_hig[1]))
+#define LC_CURVE_CONTRAST_BVN_LH ((0x4006 << 2) + 0xff000000)
+ //Bit 31 :16 reserved U RW default = 'h0 None
+ //Bit 15 :8 reg_lc_cntstbvn_low U RW default = 'h20 scale to num_m as limit of min_val to minBV distance, to protect mono-color, default = 32; min_val= MAX(min_val, minBV- MAX(num_m-1,0)*bvn_low)
+ //Bit 7 :0 reg_lc_cntstbvn_hig U RW default = 'h20 scale to num_m as limit of max_val to maxBV distance, to protect mono-color, default = 32; min_val= MIN(max_val, maxBV+ MAX(num_m-1,0)*bvn_lo
+#define LC_CURVE_MISC0 ((0x4007 << 2) + 0xff000000)
+ //Bit 31 :20 reserved U RW default = 'h0 None
+ //Bit 19 :16 reg_lc_num_m_coring U RW default = 'h1 coring to num_m, soft coring,default = 2;
+ //Bit 15 :8 reg_lc_vbin_min U RW default = 'h30 4x is min width of valid histogram bin num,
+ //Bit 7 :0 reg_lc_slope_max_face U RW default = 'h38 maximum slope for the pkBin-maxBV range curve to do face protection, normalized to 32 as 1, default= 48
+#define LC_CURVE_YPKBV_RAT ((0x4008 << 2) + 0xff000000)
+ //Bit 31 :24 reg_lc_ypkbv_ratio_0 U RW default = 'h8c x= ratio*(maxBv-minBv)+min_val as low bound of the ypkBV; normalized to 256 as 1
+ //Bit 23 :16 reg_lc_ypkbv_ratio_1 U RW default = 'ha0 x= ratio*(maxBv-minBv)+min_val as low bound of the ypkBV; normalized to 256 as 1
+ //Bit 15 :8 reg_lc_ypkbv_ratio_2 U RW default = 'h78 x= ratio*(maxBv-minBv)+min_val as low bound of the ypkBV; normalized to 256 as 1
+ //Bit 7 :0 reg_lc_ypkbv_ratio_3 U RW default = 'h60 x= ratio*(maxBv-minBv)+min_val as low bound of the ypkBV; normalized to 256 as 1
+#define LC_CURVE_YPKBV_SLP_LMT ((0x4009 << 2) + 0xff000000)
+ //Bit 31 :16 reserved U RW default = 'h0 None
+ //Bit 15 :8 reg_lc_ypkbv_slope_lmt_0 U RW default = 'hc min max slop for the curves to avoid artifacts, [0] for min_slope, [1] for max_slop, e.g.max_slope= limit*(pkBv-minBv)+min_val as high bound of the ypkBV; normalized to 32 as 1
+ //Bit 7 :0 reg_lc_ypkbv_slope_lmt_1 U RW default = 'h60 None
+#define LC_CURVE_YMINVAL_LMT_0_1 ((0x400a << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_0 U RW default = 'h30 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_1 U RW default = 'h50 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMINVAL_LMT_2_3 ((0x400b << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_2 U RW default = 'h78 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_3 U RW default = 'h80 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMINVAL_LMT_4_5 ((0x400c << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_4 U RW default = 'ha0 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_5 U RW default = 'hc4 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMINVAL_LMT_6_7 ((0x400d << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_6 U RW default = 'he0 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_7 U RW default = 'h100 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMINVAL_LMT_8_9 ((0x400e << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_8 U RW default = 'h120 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_9 U RW default = 'h140 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMINVAL_LMT_10_11 ((0x400f << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_10 U RW default = 'h160 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_11 U RW default = 'h190 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMAXVAL_LMT_0_1 ((0x4010 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_0 U RW default = 'h78 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_1 U RW default = 'h96 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_YMAXVAL_LMT_2_3 ((0x4011 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_2 U RW default = 'he6 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_3 U RW default = 'h112 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_YMAXVAL_LMT_4_5 ((0x4012 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_4 U RW default = 'h14a lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_5 U RW default = 'h180 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_YMAXVAL_LMT_6_7 ((0x4013 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_6 U RW default = 'h1d4 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_7 U RW default = 'h200 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_YMAXVAL_LMT_8_9 ((0x4014 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_8 U RW default = 'h240 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_9 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_YMAXVAL_LMT_10_11 ((0x4015 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_10 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_11 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_HISTVLD_THRD ((0x4016 << 2) + 0xff000000)
+ //Bit 31 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_histvld_thrd U RW default = 'h1fa threshold to compare to bin to get number of valid bins
+#define LC_CURVE_BB_MUTE_THRD ((0x4017 << 2) + 0xff000000)
+ //Bit 31 :24 reserved U RW default = 'h0 None
+ //Bit 23 :0 reg_lc_blackbar_mute_thrd U RW default = 'h2a30 1/8 of the region
+#define LC_CURVE_INT_STATUS ((0x4018 << 2) + 0xff000000)
+#define LC_CURVE_RAM_CTRL ((0x4020 << 2) + 0xff000000)
+#define LC_CURVE_RAM_ADDR ((0x4021 << 2) + 0xff000000)
+#define LC_CURVE_RAM_DATA ((0x4022 << 2) + 0xff000000)
+#define LC_CURVE_YMINVAL_LMT_12_13 ((0x4040 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_12 U RW default = 'h160 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_13 U RW default = 'h190 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMINVAL_LMT_14_15 ((0x4041 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_14 U RW default = 'h160 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_15 U RW default = 'h190 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMAXVAL_LMT_12_13 ((0x4042 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_12 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_13 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_YMAXVAL_LMT_14_15 ((0x4043 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_14 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_15 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+//u10, lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV])
+#define LC_CURVE_YPKBV_LMT_0_1 ((0x4044 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_0 U RW default = 'h78 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_1 U RW default = 'h96 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_2_3 ((0x4045 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_2 U RW default = 'he6 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_3 U RW default = 'h112 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_4_5 ((0x4046 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_4 U RW default = 'h14a lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_5 U RW default = 'h180 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_6_7 ((0x4047 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_6 U RW default = 'h1d4 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_7 U RW default = 'h200 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_8_9 ((0x4048 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_8 U RW default = 'h240 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_9 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_10_11 ((0x4049 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_10 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_11 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_12_13 ((0x404a << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_12 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_13 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_14_15 ((0x404b << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_14 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_15 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+//-------------------------------------------------------------
+#define LC_STTS_GCLK_CTRL0 ((0x4028 << 2) + 0xff000000)
+#define LC_STTS_CTRL0 ((0x4029 << 2) + 0xff000000)
+#define LC_STTS_WIDTHM1_HEIGHTM1 ((0x402a << 2) + 0xff000000)
+#define LC_STTS_MATRIX_COEF00_01 ((0x402b << 2) + 0xff000000)
+#define LC_STTS_MATRIX_COEF02_10 ((0x402c << 2) + 0xff000000)
+#define LC_STTS_MATRIX_COEF11_12 ((0x402d << 2) + 0xff000000)
+#define LC_STTS_MATRIX_COEF20_21 ((0x402e << 2) + 0xff000000)
+#define LC_STTS_MATRIX_COEF22 ((0x402f << 2) + 0xff000000)
+#define LC_STTS_MATRIX_OFFSET0_1 ((0x4030 << 2) + 0xff000000)
+#define LC_STTS_MATRIX_OFFSET2 ((0x4031 << 2) + 0xff000000)
+#define LC_STTS_MATRIX_PRE_OFFSET0_1 ((0x4032 << 2) + 0xff000000)
+#define LC_STTS_MATRIX_PRE_OFFSET2 ((0x4033 << 2) + 0xff000000)
+#define LC_STTS_MATRIX_HL_COLOR ((0x4034 << 2) + 0xff000000)
+#define LC_STTS_MATRIX_PROBE_POS ((0x4035 << 2) + 0xff000000)
+#define LC_STTS_MATRIX_PROBE_COLOR ((0x4036 << 2) + 0xff000000)
+#define LC_STTS_HIST_REGION_IDX ((0x4037 << 2) + 0xff000000)
+#define LC_STTS_HIST_SET_REGION ((0x4038 << 2) + 0xff000000)
+#define LC_STTS_HIST_READ_REGION ((0x4039 << 2) + 0xff000000)
+#define LC_STTS_HIST_START_RD_REGION ((0x403a << 2) + 0xff000000)
+#define LC_STTS_WHITE_INFO ((0x403b << 2) + 0xff000000)
+#define LC_STTS_BLACK_INFO ((0x403c << 2) + 0xff000000)
+//
+// Closing file: lc_stts_curve.h
+//
+// -----------------------------------------------
+// REG_BASE: VDIN_AFBCE_VCBUS_BASE = 0x41
+// -----------------------------------------------
+//
+// Reading file: vdin_afbce_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+// VDIN
+//===========================================================================
+#define VDIN2_WR_CTRL ((0x4101 << 2) + 0xff000000)
+#define VDIN2_WR_CTRL2 ((0x4102 << 2) + 0xff000000)
+#define VDIN2_WR_H_START_END ((0x4103 << 2) + 0xff000000)
+#define VDIN2_WR_V_START_END ((0x4104 << 2) + 0xff000000)
+#define VDIN2_DBG_AXI_CMD_CNT ((0x4105 << 2) + 0xff000000)
+#define VDIN2_DBG_AXI_DAT_CNT ((0x4106 << 2) + 0xff000000)
+#define VDIN2_WR_URGENT_CTRL ((0x4107 << 2) + 0xff000000)
+#define VDIN2_RO_WRMIF_STATUS ((0x4108 << 2) + 0xff000000)
+#define VDIN_TOP_SECURE0_ST_RO ((0x4109 << 2) + 0xff000000)
+#define VDIN_TOP_SECURE_DUMMY ((0x410a << 2) + 0xff000000)
+#define VDIN_TOP_DOUBLE_CTRL ((0x410b << 2) + 0xff000000)
+#define VDIN_TOP_SECURE1_ST_RO ((0x410c << 2) + 0xff000000)
+#define VDIN_TOP_MISC ((0x410d << 2) + 0xff000000)
+#define VDIN_TOP_SECURE_REG0 ((0x410e << 2) + 0xff000000)
+#define VDIN_TOP_SECURE_REG1 ((0x410f << 2) + 0xff000000)
+// 8'ha0 ~ 8'hc6
+//
+// Reading file: vdin_afbc_enc_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define AFBCE_ENABLE ((0x41a0 << 2) + 0xff000000)
+//Bit 31:20, gclk_ctrl unsigned , default = 0,
+//Bit 19:16, afbce_sync_sel unsigned , default = 0,
+//Bit 15:14, reserved
+//Bit 13, enc_rst_mode unsigned , default = 0,
+//Bit 12, enc_en_mode unsigned , default = 0,
+//Bit 11:9, reserved
+//Bit 8, enc_enable unsigned , default = 0,
+//Bit 7:1, reserved
+//Bit 0, reserved enc_frm_start pulse use this bit don't use
+#define AFBCE_MODE ((0x41a1 << 2) + 0xff000000)
+//Bit 31:29, soft_rst unsigned, default = 0 ,the use as go_field
+//Bit 28, reserved unsigned, default = 0 , enable singal of crop
+//Bit 27:26, rev_mode unsigned, default = 0 , reverse mode
+//Bit 25:24, mif_urgent unsigned, default = 3 , info mif and data mif urgent
+//Bit 23, reserved
+//Bit 22:16, hold_line_num unsigned, default = 4, 0: burst1 1:burst2 2:burst4
+//Bit 15:14, burst_mode unsigned, default = 1, 0: burst1 1:burst2 2:burst4
+//Bit 13:1, reserved
+//Bit 0, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb
+#define AFBCE_SIZE_IN ((0x41a2 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hsize_in unsigned, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_in unsigned, default = 1080 , pic vert size in unit: pixel
+#define AFBCE_BLK_SIZE_IN ((0x41a3 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hblk_size unsigned, default = 60 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vblk_size unsigned, default = 270, pic vert size in unit: pixel
+#define AFBCE_HEAD_BADDR ((0x41a4 << 2) + 0xff000000)
+//Bit 31:0, head_baddr unsigned, default = 32'h00;
+#define AFBCE_MIF_SIZE ((0x41a5 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:28, ddr_blk_size unsigned, default = 1;
+//Bit 27, reserved
+//Bit 26:24, cmd_blk_size unsigned, default = 3;
+//Bit 23:21, reserved
+//Bit 20:16, uncmp_size unsigned, default = 20;
+//Bit 15:0, mmu_page_size unsigned, default = 4096;
+#define AFBCE_PIXEL_IN_HOR_SCOPE ((0x41a6 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, enc_win_end_h unsigned, default = 1919 ; //
+//Bit 15:13, reserved
+//Bit 12:0, enc_win_bgn_h unsigned, default = 0 ; //
+#define AFBCE_PIXEL_IN_VER_SCOPE ((0x41a7 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, enc_win_end_v unsigned, default = 1079 ; //
+//Bit 15:13, reserved
+//Bit 12:0, enc_win_bgn_v unsigned, default = 0 ; //
+#define AFBCE_CONV_CTRL ((0x41a8 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, fmt_ybuf_depth unsigned, default = 2048
+//Bit 15:12, reserved
+//Bit 11: 0, lbuf_depth unsigned, default = 256, unit=16 pixel need to set = 2^n
+#define AFBCE_MIF_HOR_SCOPE ((0x41a9 << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, blk_end_h unsigned, default = 0 ; //
+//Bit 15:10, reserved
+//Bit 9:0, blk_bgn_h unsigned, default = 59 ; //
+#define AFBCE_MIF_VER_SCOPE ((0x41aa << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, blk_end_v unsigned, default = 0 ; //
+//Bit 15:12, reserved
+//Bit 11:0, blk_bgn_v unsigned, default = 269 ; //
+#define AFBCE_STAT1 ((0x41ab << 2) + 0xff000000)
+//Bit 31, ro_frm_end_pulse1 unsigned, RO,default = 0 ;frame end status
+//Bit 30:0, ro_dbg_top_info1 unsigned, RO,default = 0 ;
+#define AFBCE_STAT2 ((0x41ac << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30:0, ro_dbg_top_info2 unsigned, RO,default = 0 ;
+#define AFBCE_FORMAT ((0x41ad << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11:10 reserved
+//Bit 9: 8 reg_format_mode // unsigned , RW, default = 2 data format;0 : YUV444, 1:YUV422, 2:YUV420, 3:RGB
+//Bit 7: 4 reg_compbits_c // unsigned , RW, default = 10 chroma bitwidth
+//Bit 3: 0 reg_compbits_y // unsigned , RW, default = 10 luma bitwidth
+#define AFBCE_MODE_EN ((0x41ae << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 reserved
+//Bit 25 reg_adpt_interleave_ymode // unsigned , RW, default = 0 force 0 to disable it: no HW implementation
+//Bit 24 reg_adpt_interleave_cmode // unsigned , RW, default = 0 force 0 to disable it: not HW implementation
+//Bit 23 reg_adpt_yinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
+//Bit 22 reg_adpt_yinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
+//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
+//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
+//Bit 19 reserved
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 11 reserved
+//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
+//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
+//Bit 8 reg_uncompress_split_mode // unsigned , RW, default = 0 0: no split; 1: split
+//Bit 7: 6 reserved
+//Bit 5 reg_input_padding_uv128 // unsigned , RW, default = 0 input picture 32x4 block gap mode: 0: pad uv=0; 1: pad uv=128
+//Bit 4 reg_dwds_padding_uv128 // unsigned , RW, default = 0 downsampled image for double write 32x gap mode: 0: pad uv=0; 1: pad uv=128
+//Bit 3: 1 reg_force_order_mode_value // unsigned , RW, default = 0 force order mode 0~7
+//Bit 0 reg_force_order_mode_en // unsigned , RW, default = 0 force order mode enable: 0: no force; 1: forced to force_value
+#define AFBCE_DWSCALAR ((0x41af << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7: 6 reg_dwscalar_w0 // unsigned , RW, default = 3 horizontal 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 5: 4 reg_dwscalar_w1 // unsigned , RW, default = 0 horizontal 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 3: 2 reg_dwscalar_h0 // unsigned , RW, default = 2 vertical 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 1: 0 reg_dwscalar_h1 // unsigned , RW, default = 3 vertical 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+#define AFBCE_DEFCOLOR_1 ((0x41b0 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_enc_defalutcolor_3 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr]
+//Bit 11: 0 reg_enc_defalutcolor_0 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr]
+#define AFBCE_DEFCOLOR_2 ((0x41b1 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_enc_defalutcolor_2 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr]
+//Bit 11: 0 reg_enc_defalutcolor_1 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr]
+#define AFBCE_QUANT_ENABLE ((0x41b2 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_quant_expand_en_1 // unsigned , RW, default = 0 enable for quantization value expansion
+//Bit 10 reg_quant_expand_en_0 // unsigned , RW, default = 0 enable for quantization value expansion
+//Bit 9: 8 reg_bcleav_ofst // signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1;
+//Bit 7: 5 reserved
+//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy
+//Bit 3: 1 reserved
+//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy
+#define AFBCE_IQUANT_LUT_1 ((0x41b3 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCE_IQUANT_LUT_2 ((0x41b4 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCE_IQUANT_LUT_3 ((0x41b5 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCE_IQUANT_LUT_4 ((0x41b6 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCE_RQUANT_LUT_1 ((0x41b7 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_rquant_yclut_0_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting)
+//Bit 27 reserved
+//Bit 26:24 reg_rquant_yclut_0_10 // unsigned , RW, default = 5
+//Bit 23 reserved
+//Bit 22:20 reg_rquant_yclut_0_9 // unsigned , RW, default = 4
+//Bit 19 reserved
+//Bit 18:16 reg_rquant_yclut_0_8 // unsigned , RW, default = 4
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_0_7 // unsigned , RW, default = 3
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_0_6 // unsigned , RW, default = 3
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_0_5 // unsigned , RW, default = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_0_4 // unsigned , RW, default = 2
+#define AFBCE_RQUANT_LUT_2 ((0x41b8 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_0_3 // unsigned , RW, default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_0_2 // unsigned , RW, default = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_0_1 // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_0_0 // unsigned , RW, default = 0
+#define AFBCE_RQUANT_LUT_3 ((0x41b9 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_rquant_yclut_1_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting)
+//Bit 27 reserved
+//Bit 26:24 reg_rquant_yclut_1_10 // unsigned , RW, default = 5
+//Bit 23 reserved
+//Bit 22:20 reg_rquant_yclut_1_9 // unsigned , RW, default = 4
+//Bit 19 reserved
+//Bit 18:16 reg_rquant_yclut_1_8 // unsigned , RW, default = 4
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_1_7 // unsigned , RW, default = 3
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_1_6 // unsigned , RW, default = 3
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_1_5 // unsigned , RW, default = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_1_4 // unsigned , RW, default = 2
+#define AFBCE_RQUANT_LUT_4 ((0x41ba << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_1_3 // unsigned , RW, default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_1_2 // unsigned , RW, default = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_1_1 // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_1_0 // unsigned , RW, default = 0
+#define AFBCE_YUV_FORMAT_CONV_MODE ((0x41bb << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7 reserved
+//Bit 6: 4 reg_444to422_mode // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_422to420_mode // unsigned , RW, default = 0
+#define AFBCE_DUMMY_DATA ((0x41bc << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29: 0 reg_dummy_data // unsigned , default = 0 ;
+#define AFBCE_CLR_FLAG ((0x41bd << 2) + 0xff000000)
+//Bit 31:0 reg_afbce_clr_flag // unsigned, default = 0 ;
+#define AFBCE_STA_FLAGT ((0x41be << 2) + 0xff000000)
+//Bit 31:0 ro_afbce_sta_flag // unsigned, RO,default = 0 ;
+#define AFBCE_MMU_NUM ((0x41bf << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 0 ro_frm_mmu_num // unsigned, RO,default = 0 ;
+#define AFBCE_MMU_RMIF_CTRL1 ((0x41c0 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_sync_sel // unsigned , default = 0, axi canvas id sync with frm rst
+//Bit 23:16 reg_canvas_id // unsigned , default = 0, axi canvas id num
+//Bit 15 reserved
+//Bit 14:12 reg_cmd_intr_len // unsigned , default = 1, interrupt send cmd when how many series axi cmd,
+ // 0=12 1=16 2=24 3=32 4=40 5=48 6=56 7=64
+//Bit 11:10 reg_cmd_req_size // unsigned , default = 1, how many room fifo have, then axi send series req, 0=16 1=32 2=24 3=64
+//Bit 9:8 reg_burst_len // unsigned , default = 2, burst type: 0-single 1-bst2 2-bst4
+//Bit 7 reg_swap_64bit // unsigned , default = 0, 64bits of 128bit swap enable
+//Bit 6 reg_little_endian // unsigned , default = 0, big endian enable
+//Bit 5 reg_y_rev // unsigned , default = 0, vertical reverse enable
+//Bit 4 reg_x_rev // unsigned , default = 0, horizontal reverse enable
+//Bit 3 reserved
+//Bit 2:0 reg_pack_mode // unsigned , default = 3, 0:4bit 1:8bit 2:16bit 3:32bit 4:64bit 5:128bit
+#define AFBCE_MMU_RMIF_CTRL2 ((0x41c1 << 2) + 0xff000000)
+//Bit 31:30 reg_sw_rst // unsigned , default = 0,
+//Bit 29:24 reserved
+//Bit 23:18 reg_gclk_ctrl
+//Bit 17 reserved
+//Bit 16:0 reg_urgent_ctrl // unsigned , default = 0, urgent control reg :
+ // 16 reg_ugt_init : urgent initial value
+ // 15 reg_ugt_en : urgent enable
+ // 14 reg_ugt_type : 1= wrmif 0=rdmif
+ // 7:4 reg_ugt_top_th: urgent top threshold
+ // 3:0 reg_ugt_bot_th: urgent bottom threshold
+#define AFBCE_MMU_RMIF_CTRL3 ((0x41c2 << 2) + 0xff000000)
+//Bit 31:17 reserved
+//Bit 16 reg_acc_mode // unsigned , default = 1,
+//Bit 15:13 reserved
+//Bit 12:0 reg_stride // unsigned , default = 4096,
+#define AFBCE_MMU_RMIF_CTRL4 ((0x41c3 << 2) + 0xff000000)
+//Bit 31:0 reg_baddr // unsigned , default = 0,
+#define AFBCE_MMU_RMIF_SCOPE_X ((0x41c4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_x_end // unsigned , default = 4095, the canvas hor end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_x_start // unsigned , default = 0, the canvas hor start pixel position
+#define AFBCE_MMU_RMIF_SCOPE_Y ((0x41c5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_y_end // unsigned , default = 0, the canvas ver end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_y_start // unsigned , default = 0, the canvas ver start pixel positio
+#define AFBCE_MMU_RMIF_RO_STAT ((0x41c6 << 2) + 0xff000000)
+//Bit 15:0 reg_status // unsigned ,
+#define AFBCE_PIP_CTRL ((0x41ca << 2) + 0xff000000)
+//Bit 31:3 reserved
+//Bit 2 reg_enc_align_en //unsigned , RW,default = 1,
+//Bit 1 reg_pip_ini_ctrl //unsigned , RW,default = 0,
+//Bit 0 reg_pip_mode //unsigned , RW,default = 0,
+#define AFBCE_ROT_CTRL ((0x41cb << 2) + 0xff000000)
+//Bit 31:5 reserved
+//Bit 4 reg_rot_en //unsigned , RW,default = 0, rotation enable
+//Bit 3:0 reg_vstep //unsigned , RW,default = 8, rotation vstep ,setting acorrding rotation shrink mode
+#define AFBCE_DIMM_CTRL ((0x41cc << 2) + 0xff000000)
+//Bit 31 reg_dimm_layer_en //unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30 reserved
+//Bit 29:0 reg_dimm_data //unsigned , RW,default = 29'h00080200,dimm_layer data
+#define AFBCE_BND_DEC_MISC ((0x41cd << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 bnd_dec_rev_mode //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 25:24 bnd_dec_mif_urgent //unsigned , RW,default = 3 only pip mode use those bits,ususaly don't need configure
+//Bit 23:22 bnd_dec_burst_len //unsigned , RW,default = 2 only pip mode use those bits,ususaly don't need configure
+//Bit 21:20 bnd_dec_ddr_blk_size //unsigned , RW,default = 1 only pip mode use those bits,ususaly don't need configure
+//Bit 19 reserved
+//Bit 18:16 bnd_dec_cmd_blk_size //unsigned , RW,default = 3 only pip mode use those bits,ususaly don't need configure
+//Bit 15 reserved
+//Bit 14 bnd_dec_blk_mem_mode //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 13 bnd_dec_addr_link_en //unsigned , RW,default = 1 only pip mode use those bits,ususaly don't need configure
+//Bit 12 bnd_dec_always_body_rden //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 11:0 bnd_dec_mif_lbuf_depth //unsigned , RW,default = 128 only pip mode use those bits,ususaly don't need configure
+#define AFBCE_RD_ARB_MISC ((0x41ce << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12 reg_arb_sw_rst //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 11:10 reserved
+//Bit 9 reg_arb_arblk_last1 //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 8 reg_arb_arblk_last0 //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 7:4 reg_arb_weight_ch1 //unsigned , RW,default = 4 only pip mode use those bits,ususaly don't need configure
+//Bit 3:0 reg_arb_weight_ch0 //unsigned , RW,default = 10 only pip mode use those bits,ususaly don't need configure
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vdin_afbc_enc_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vdin_afbce_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: LCD2_VCBUS_BASE = 0x42
+// -----------------------------------------------
+//`include "a.h"
+// -----------------------------------------------
+// REG_BASE: DOLBYTV_VCBUS_BASE = 0x43
+// -----------------------------------------------
+//
+// Reading file: dolby_tv_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DOLBY_TV_REG_START ((0x4300 << 2) + 0xff000000)
+// dolby register address 0~0xDA
+#define DOLBY_TV_CLKGATE_CTRL ((0x43f1 << 2) + 0xff000000)
+//bit[9:8] R-RW 0~3 0 dma2axi_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock"
+//bit[7:6] R-RW 0~3 0 bl_dolby_swaps_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock"
+//bit[5:4] R-RW 0~3 0 el_swaps_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock"
+//bit[3:2] R-RW 0~3 0 el_buf_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock"
+//bit[1:0] R-RW 0~3 0 top_level_reg_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock"
+#define DOLBY_TV_SWAP_CTRL0 ((0x43f2 << 2) + 0xff000000)
+//bit[2] R-RW 0~1 0 el_41mode : 1 "bl resolution : el resolution = 4:1", 0 "bl_res : el_res = 1:1"
+//bit[1] R-RW 0~1 0 el_enable : 1 "enhancement layer is supported", 0 "el is not supported"
+//bit[0] R-RW 0~1 0 source_enable : 1 "base layer is supported", 0 "bl is not supported"
+#define DOLBY_TV_SWAP_CTRL1 ((0x43f3 << 2) + 0xff000000)
+//bit[28:16] R-RW 0~8191 0 htotal : total pixels number in each line
+//bit[21:0] R-RW 0~8191 0 vtotal : total line number in each frame (only support progress frame)
+#define DOLBY_TV_SWAP_CTRL2 ((0x43f4 << 2) + 0xff000000)
+//bit[28:16] R-RW 0~4096 0 hsize : active pixels number in each line
+//bit[21:0] R-RW 0~3840 0 vsize : active lines number in each frame
+#define DOLBY_TV_SWAP_CTRL3 ((0x43f5 << 2) + 0xff000000)
+//bit[28:16] R-RW 0~8191 0 hsync_width : hsync signal width (high effective)
+//bit[21:0] R-RW 0~8191 0 vsync_width : vysnc singal width (high effective)
+#define DOLBY_TV_SWAP_CTRL4 ((0x43f6 << 2) + 0xff000000)
+//bit[28:16] R-RW 0~8191 0 hsync_backporch : pixels number between hsync and h_active_duration
+//bit[21:0] R-RW 0~8191 0 vsync_backporch : lines number between vsync and v_active_duration
+#define DOLBY_TV_SWAP_CTRL5 ((0x43f7 << 2) + 0xff000000)
+//[25:8] R-RW : reg_tunnel_sel for tunnel bit match swap
+//bit[4] R-RW 0~1 0 bl_tunnel_mode : 1 "hdmi input, source is 12bit422 tunnel in 8bit444", 0 "opt mode, 10 bit 444"
+//bit[3:2] R-RW 0~3 0 bl_uv_mode : 3 "uv=in_u", 2 "uv[0]=u[0],uv[1]=v[0]", 1 "uv[0]=v[0],uv[1]=u[0]", 0 "uv=in_v"
+//bit[1:0] R-RW 0~3 0 el_uv_mode : 3 "uv=in_u", 2 "uv[0]=u[0],uv[1]=v[0]", 1 "uv[0]=v[0],uv[1]=u[0]", 0 "uv=in_v"
+#define DOLBY_TV_SWAP_CTRL6 ((0x43f8 << 2) + 0xff000000)
+//bit[31] R-RW 0~1 dm_uv_input : uv select
+//bit[23:16] R-RW 0~1 0 dump_ctrl : 1 "fixed output bitdepth as 12bit", 0 "output bitdepth based on vdr_bit_depth"
+//bit[15] R-RW 0~1 datapath_reset_n_enable : manual reset control
+//bit[14] R-RW 0~1 handshake_reset_n_enable : manual reset control
+//bit[13] R-RW 0~1 axi_reset_n_enable : manual reset control
+//bit[5:2] R-RW 0~15 vdr_bit_depth
+//bit[1:0] R-RW 0~3 reg_hdmi_mode
+#define DOLBY_TV_SWAP_CTRL7 ((0x43f9 << 2) + 0xff000000)
+//reserved
+#define DOLBY_TV_AXI2DMA_CTRL0 ((0x43fa << 2) + 0xff000000)
+//bit[31] R-RW 0~1 0 reg_req_en : enable req after line count
+//bit[30] R-RW 0~1 0 reg_id_check : check the id of data path and req path
+//bit[29] R-RW 0~1 0 reg_clear_fifo : manually reset bit
+//bit[28] R-RW 0~1 0 reg_vsync_rst : soft_rst auto reset enable
+//bit[27] R-RW 0~1 0 reg_update_addr : manually udpate start addr
+//bit[26] R-RW 0~1 0 reg_addr_auto : auto update start addr enable
+//bit[25] R-RW 0~1 0 reg_keep_receive : data path keep receive
+//bit[24:19] R-RW 0~63 0 reg_req_th : fifo_room > req_th, then send the request
+//bit[18:16] R-RW 0~7 0 reg_arsize : axi arsize
+//bit[14:12] R-RW 0~7 0 reg_arprot : axi arprot
+//bit[11:8] R-RW 0~15 0 reg_aruser : axi aruser
+//bit[5:4] R-RW 0~3 0 reg_arid : axi arid
+//bit[3:0] R-RW 0~2 0 reg_lens : default request lens, each burst has "reg_lens+1" data
+#define DOLBY_TV_AXI2DMA_CTRL1 ((0x43fb << 2) + 0xff000000)
+//bit[31] R-RW 0~1 0 axi_addr_mode : 1 "canvas mode", 0 "normal mode"
+//bit[27:16] R-RW 0~4095 0 dma_size0 : total data number in dma0
+//bit[11:0] R-RW 0~4095 0 dma_size1 : total data number in dma1
+#define DOLBY_TV_AXI2DMA_CTRL2 ((0x43fc << 2) + 0xff000000)
+//bit[31:0] R-RW 0~4294967295 0 axi_start_addr : axi start address
+#define DOLBY_TV_AXI2DMA_CTRL3 ((0x43fd << 2) + 0xff000000)
+//bit[11:0] R-RW 0~4095 0 hold_line : after hold_line the axi slave start requesting
+#define DOLBY_TV_STATUS0 ((0x43fe << 2) + 0xff000000)
+#define DOLBY_TV_STATUS1 ((0x43ff << 2) + 0xff000000)
+#define DOLBY_TV_ADAPTIVE_SCALE_REGADDR ((0x43e0 << 2) + 0xff000000)
+#define DOLBY_TV_ADAPTIVE_SCALE_REGDATA ((0x43e1 << 2) + 0xff000000)
+#define DOLBY_TV_ADAPTIVE_SCALE_LUTADDR ((0x43e2 << 2) + 0xff000000)
+#define DOLBY_TV_ADAPTIVE_SCALE_LUTDATA ((0x43e3 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dolby_tv_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: DOLBY1B_VCBUS_BASE = 0x44
+// -----------------------------------------------
+//
+// Reading file: dolby1b_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DOLBY_CORE1B_REG_START ((0x4400 << 2) + 0xff000000)
+#define DOLBY_CORE1B_CLKGATE_CTRL ((0x44f2 << 2) + 0xff000000)
+#define DOLBY_CORE1B_SWAP_CTRL0 ((0x44f3 << 2) + 0xff000000)
+#define DOLBY_CORE1B_SWAP_CTRL1 ((0x44f4 << 2) + 0xff000000)
+#define DOLBY_CORE1B_SWAP_CTRL2 ((0x44f5 << 2) + 0xff000000)
+#define DOLBY_CORE1B_SWAP_CTRL3 ((0x44f6 << 2) + 0xff000000)
+#define DOLBY_CORE1B_SWAP_CTRL4 ((0x44f7 << 2) + 0xff000000)
+#define DOLBY_CORE1B_SWAP_CTRL5 ((0x44f8 << 2) + 0xff000000)
+#define DOLBY_CORE1B_DMA_CTRL ((0x44f9 << 2) + 0xff000000)
+#define DOLBY_CORE1B_DMA_STATUS ((0x44fa << 2) + 0xff000000)
+#define DOLBY_CORE1B_STATUS0 ((0x44fb << 2) + 0xff000000)
+#define DOLBY_CORE1B_STATUS1 ((0x44fc << 2) + 0xff000000)
+#define DOLBY_CORE1B_STATUS2 ((0x44fd << 2) + 0xff000000)
+#define DOLBY_CORE1B_STATUS3 ((0x44fe << 2) + 0xff000000)
+#define DOLBY_CORE1B_DMA_PORT ((0x44ff << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dolby1b_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: FGRAIN_VCBUS_BASE = 0x48
+// -----------------------------------------------
+//`include "afbcd_mult_regs.h"
+//
+// Reading file: afbcd_vd_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+// reg addr map
+// 0 -3f : rdmif
+// 40-6f : afbcd
+// 70-7f : fgrain
+////===============================////
+#define VD1_IF0_GEN_REG ((0x4800 << 2) + 0xff000000)
+#define VD1_IF0_CANVAS0 ((0x4801 << 2) + 0xff000000)
+#define VD1_IF0_CANVAS1 ((0x4802 << 2) + 0xff000000)
+#define VD1_IF0_LUMA_X0 ((0x4803 << 2) + 0xff000000)
+#define VD1_IF0_LUMA_Y0 ((0x4804 << 2) + 0xff000000)
+#define VD1_IF0_CHROMA_X0 ((0x4805 << 2) + 0xff000000)
+#define VD1_IF0_CHROMA_Y0 ((0x4806 << 2) + 0xff000000)
+#define VD1_IF0_LUMA_X1 ((0x4807 << 2) + 0xff000000)
+#define VD1_IF0_LUMA_Y1 ((0x4808 << 2) + 0xff000000)
+#define VD1_IF0_CHROMA_X1 ((0x4809 << 2) + 0xff000000)
+#define VD1_IF0_CHROMA_Y1 ((0x480a << 2) + 0xff000000)
+#define VD1_IF0_RPT_LOOP ((0x480b << 2) + 0xff000000)
+#define VD1_IF0_LUMA0_RPT_PAT ((0x480c << 2) + 0xff000000)
+#define VD1_IF0_CHROMA0_RPT_PAT ((0x480d << 2) + 0xff000000)
+#define VD1_IF0_LUMA1_RPT_PAT ((0x480e << 2) + 0xff000000)
+#define VD1_IF0_CHROMA1_RPT_PAT ((0x480f << 2) + 0xff000000)
+#define VD1_IF0_LUMA_PSEL ((0x4810 << 2) + 0xff000000)
+#define VD1_IF0_CHROMA_PSEL ((0x4811 << 2) + 0xff000000)
+#define VD1_IF0_DUMMY_PIXEL ((0x4812 << 2) + 0xff000000)
+#define VD1_IF0_LUMA_FIFO_SIZE ((0x4813 << 2) + 0xff000000)
+#define VD1_IF0_AXI_CMD_CNT ((0x4814 << 2) + 0xff000000)
+#define VD1_IF0_AXI_RDAT_CNT ((0x4815 << 2) + 0xff000000)
+#define VD1_IF0_RANGE_MAP_Y ((0x4816 << 2) + 0xff000000)
+#define VD1_IF0_RANGE_MAP_CB ((0x4817 << 2) + 0xff000000)
+#define VD1_IF0_RANGE_MAP_CR ((0x4818 << 2) + 0xff000000)
+#define VD1_IF0_GEN_REG2 ((0x4819 << 2) + 0xff000000)
+#define VD1_IF0_PROT ((0x481a << 2) + 0xff000000)
+#define VD1_IF0_URGENT_CTRL ((0x481b << 2) + 0xff000000)
+#define VD1_IF0_GEN_REG3 ((0x481c << 2) + 0xff000000)
+#define VIU_VD1_FMT_CTRL ((0x481d << 2) + 0xff000000)
+#define VIU_VD1_FMT_W ((0x481e << 2) + 0xff000000)
+#define VD2_IF0_GEN_REG ((0x4880 << 2) + 0xff000000)
+#define VD2_IF0_CANVAS0 ((0x4881 << 2) + 0xff000000)
+#define VD2_IF0_CANVAS1 ((0x4882 << 2) + 0xff000000)
+#define VD2_IF0_LUMA_X0 ((0x4883 << 2) + 0xff000000)
+#define VD2_IF0_LUMA_Y0 ((0x4884 << 2) + 0xff000000)
+#define VD2_IF0_CHROMA_X0 ((0x4885 << 2) + 0xff000000)
+#define VD2_IF0_CHROMA_Y0 ((0x4886 << 2) + 0xff000000)
+#define VD2_IF0_LUMA_X1 ((0x4887 << 2) + 0xff000000)
+#define VD2_IF0_LUMA_Y1 ((0x4888 << 2) + 0xff000000)
+#define VD2_IF0_CHROMA_X1 ((0x4889 << 2) + 0xff000000)
+#define VD2_IF0_CHROMA_Y1 ((0x488a << 2) + 0xff000000)
+#define VD2_IF0_RPT_LOOP ((0x488b << 2) + 0xff000000)
+#define VD2_IF0_LUMA0_RPT_PAT ((0x488c << 2) + 0xff000000)
+#define VD2_IF0_CHROMA0_RPT_PAT ((0x488d << 2) + 0xff000000)
+#define VD2_IF0_LUMA1_RPT_PAT ((0x488e << 2) + 0xff000000)
+#define VD2_IF0_CHROMA1_RPT_PAT ((0x488f << 2) + 0xff000000)
+#define VD2_IF0_LUMA_PSEL ((0x4890 << 2) + 0xff000000)
+#define VD2_IF0_CHROMA_PSEL ((0x4891 << 2) + 0xff000000)
+#define VD2_IF0_DUMMY_PIXEL ((0x4892 << 2) + 0xff000000)
+#define VD2_IF0_LUMA_FIFO_SIZE ((0x4893 << 2) + 0xff000000)
+#define VD2_IF0_AXI_CMD_CNT ((0x4894 << 2) + 0xff000000)
+#define VD2_IF0_AXI_RDAT_CNT ((0x4895 << 2) + 0xff000000)
+#define VD2_IF0_RANGE_MAP_Y ((0x4896 << 2) + 0xff000000)
+#define VD2_IF0_RANGE_MAP_CB ((0x4897 << 2) + 0xff000000)
+#define VD2_IF0_RANGE_MAP_CR ((0x4898 << 2) + 0xff000000)
+#define VD2_IF0_GEN_REG2 ((0x4899 << 2) + 0xff000000)
+#define VD2_IF0_PROT ((0x489a << 2) + 0xff000000)
+#define VD2_IF0_URGENT_CTRL ((0x489b << 2) + 0xff000000)
+#define VD2_IF0_GEN_REG3 ((0x489c << 2) + 0xff000000)
+#define VIU_VD2_FMT_CTRL ((0x489d << 2) + 0xff000000)
+#define VIU_VD2_FMT_W ((0x489e << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: afbcd_vd_regs.h
+//
+//`include "fgrain_regs.h" //nouse
+// -----------------------------------------------
+// REG_BASE: VPPC_VCBUS_BASE = 0x50
+// -----------------------------------------------
+//
+// Reading file: srsharp_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//SRSHARP0 8'h00 - 8'hff
+//SRSHARP1 8'h100 - 8'1ff
+#define SRSHARP0_OFFSET (0x000<<2)
+#define SRSHARP1_OFFSET (0x200<<2)
+
+//
+// Reading file: sharp_regs.h
+//
+#define SHARP_HVSIZE ((0x5000 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_pknr_hsize . unsigned , default = 1920
+//Bit 15:13, reserved
+//Bit 12: 0, reg_pknr_vsize . unsigned , default = 1080
+#define SHARP_HVBLANK_NUM ((0x5001 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_deband_hblank
+//Bit 15: 8, reg_pknr_hblank_num . unsigned , default = 20
+//Bit 7: 0, reg_pknr_vblank_num . unsigned , default = 73
+#define NR_GAUSSIAN_MODE ((0x5002 << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13:12, reg_nr_gau_ynorm : C adpative coef norm, 0: 128, 1: 256, 2: 512, 3: 1024 . unsigned , default = 0
+//Bit 11:10, reserved
+//Bit 9: 8, reg_nr_gau_cnorm : C adpative coef norm, 0: 128, 1: 256, 2: 512, 3: 1024 . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 4, reg_nr_gau_ymode : 0 3x3 filter; 1: 5x5 filter; 2/3:adpative coef . unsigned , default = 1
+//Bit 3: 2, reserved
+//Bit 1: 0, reg_nr_gau_cmode : 0 3x3 filter; 1: 5x5 filter; 2/3:adpative coef . unsigned , default = 1
+#define PK_CON_2CIRHPGAIN_TH_RATE ((0x5005 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_cirhpcon2gain0 : threshold0 of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 25
+//Bit 23:16, reg_pk_cirhpcon2gain1 : threshold1 of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 60
+//Bit 15: 8, reg_pk_cirhpcon2gain5 : rate0 (for hpcon<th0) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 80
+//Bit 7: 0, reg_pk_cirhpcon2gain6 : rate1 (for hpcon>th1) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 20
+#define PK_CON_2CIRHPGAIN_LIMIT ((0x5006 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_cirhpcon2gain2 : level limit(for hpcon<th0) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 155
+//Bit 23:16, reg_pk_cirhpcon2gain3 : level limit(for th0<hpcon<th1) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 150
+//Bit 15: 8, reg_pk_cirhpcon2gain4 : level limit(for hpcon>th1) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 5
+//Bit 7: 0, reserved
+#define PK_CON_2CIRBPGAIN_TH_RATE ((0x5007 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_cirbpcon2gain0 : threshold0 of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 20
+//Bit 23:16, reg_pk_cirbpcon2gain1 : threshold1 of curve to map bpcon to bpgain for circle bp filter (all 8 direction same).. unsigned , default = 50
+//Bit 15: 8, reg_pk_cirbpcon2gain5 : rate0 (for bpcon<th0) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 50
+//Bit 7: 0, reg_pk_cirbpcon2gain6 : rate1 (for bpcon>th1) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 25
+#define PK_CON_2CIRBPGAIN_LIMIT ((0x5008 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_cirbpcon2gain2 : level limit(for bpcon<th0) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 155
+//Bit 23:16, reg_pk_cirbpcon2gain3 : level limit(for th0<bpcon<th1) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 150
+//Bit 15: 8, reg_pk_cirbpcon2gain4 : level limit(for bpcon>th1) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 5
+//Bit 7: 0, reserved
+#define PK_CON_2DRTHPGAIN_TH_RATE ((0x5009 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_drthpcon2gain0 : threshold0 of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 25
+//Bit 23:16, reg_pk_drthpcon2gain1 : threshold1 of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 60
+//Bit 15: 8, reg_pk_drthpcon2gain5 : rate0 (for hpcon<th0) of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 80
+//Bit 7: 0, reg_pk_drthpcon2gain6 : rate1 (for hpcon>th1) of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 20
+#define PK_CON_2DRTHPGAIN_LIMIT ((0x500a << 2) + 0xff000000)
+//Bit 31:24, reg_pk_drthpcon2gain2 : level limit(for hpcon<th0) of curve to map hpcon to hpgain for directional hp filter (best direction).. unsigned , default = 105
+//Bit 23:16, reg_pk_drthpcon2gain3 : level limit(for th0<hpcon<th1) of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 96
+//Bit 15: 8, reg_pk_drthpcon2gain4 : level limit(for hpcon>th1) of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 5
+//Bit 7: 0, reserved
+#define PK_CON_2DRTBPGAIN_TH_RATE ((0x500b << 2) + 0xff000000)
+//Bit 31:24, reg_pk_drtbpcon2gain0 : threshold0 of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 20
+//Bit 23:16, reg_pk_drtbpcon2gain1 : threshold1 of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 50
+//Bit 15: 8, reg_pk_drtbpcon2gain5 : rate0 (for bpcon<th0) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 50
+//Bit 7: 0, reg_pk_drtbpcon2gain6 : rate1 (for bpcon>th1) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 25
+#define PK_CON_2DRTBPGAIN_LIMIT ((0x500c << 2) + 0xff000000)
+//Bit 31:24, reg_pk_drtbpcon2gain2 : level limit(for bpcon<th0) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 55
+//Bit 23:16, reg_pk_drtbpcon2gain3 : level limit(for th0<bpcon<th1) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 40
+//Bit 15: 8, reg_pk_drtbpcon2gain4 : level limit(for bpcon>th1) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 5
+//Bit 7: 0, reserved
+#define PK_CIRFB_LPF_MODE ((0x500d << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:28, reg_cirhp_horz_mode : no horz filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1
+//Bit 27:26, reserved
+//Bit 25:24, reg_cirhp_vert_mode : no vert filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1
+//Bit 23:22, reserved
+//Bit 21:20, reg_cirhp_diag_mode : filter on HP; 1: [1 2 1]/4; . unsigned , default = 1
+//Bit 19:14, reserved
+//Bit 13:12, reg_cirbp_horz_mode : no horz filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1
+//Bit 11:10, reserved
+//Bit 9: 8, reg_cirbp_vert_mode : no vert filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1
+//Bit 7: 6, reserved
+//Bit 5: 4, reg_cirbp_diag_mode : filter on BP; 1: [1 2 1]/4; . unsigned , default = 1
+//Bit 3: 0, reserved
+#define PK_DRTFB_LPF_MODE ((0x500e << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:28, reg_drthp_horz_mode : no horz filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1
+//Bit 27:26, reserved
+//Bit 25:24, reg_drthp_vert_mode : no vert filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1
+//Bit 23:22, reserved
+//Bit 21:20, reg_drthp_diag_mode : filter on HP; 1: [1 2 1]/4; 1 . unsigned , default = 1
+//Bit 19:14, reserved
+//Bit 13:12, reg_drtbp_horz_mode : no horz filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1
+//Bit 11:10, reserved
+//Bit 9: 8, reg_drtbp_vert_mode : no vert filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1
+//Bit 7: 6, reserved
+//Bit 5: 4, reg_drtbp_diag_mode : filter on BP; 1: [1 2 1]/4; 1 . unsigned , default = 1
+//Bit 3: 0, reserved
+#define PK_CIRFB_HP_CORING ((0x500f << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, reg_cirhp_horz_core : coring of HP for Horz . unsigned , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_cirhp_vert_core : coring of HP for Vert . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_cirhp_diag_core : coring of HP for Diag . unsigned , default = 0
+#define PK_CIRFB_BP_CORING ((0x5010 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, reg_cirbp_horz_core : coring of HP for Horz . unsigned , default = 1
+//Bit 15:14, reserved
+//Bit 13: 8, reg_cirbp_vert_core : coring of HP for Vert . unsigned , default = 1
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_cirbp_diag_core : coring of HP for Diag . unsigned , default = 1
+#define PK_DRTFB_HP_CORING ((0x5011 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, reg_drthp_horz_core : coring of HP for Horz . unsigned , default = 1
+//Bit 15:14, reserved
+//Bit 13: 8, reg_drthp_vert_core : coring of HP for Vert . unsigned , default = 1
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_drthp_diag_core : coring of HP for Diag . unsigned , default = 1
+#define PK_DRTFB_BP_CORING ((0x5012 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, reg_drtbp_horz_core : coring of HP for Horz . unsigned , default = 1
+//Bit 15:14, reserved
+//Bit 13: 8, reg_drtbp_vert_core : coring of HP for Vert . unsigned , default = 1
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_drtbp_diag_core : coring of HP for Diag . unsigned , default = 1
+#define PK_CIRFB_BLEND_GAIN ((0x5013 << 2) + 0xff000000)
+//Bit 31:28, reg_hp_cir_hgain : normalized 8 as '1' . unsigned , default = 8
+//Bit 27:24, reg_hp_cir_vgain : normalized 8 as '1' . unsigned , default = 8
+//Bit 23:20, reg_hp_cir_dgain : normalized 8 as '1' . unsigned , default = 8
+//Bit 19:16, reserved
+//Bit 15:12, reg_bp_cir_hgain : normalized 8 as '1' . unsigned , default = 8
+//Bit 11: 8, reg_bp_cir_vgain : normalized 8 as '1' . unsigned , default = 8
+//Bit 7: 4, reg_bp_cir_dgain : normalized 8 as '1' . unsigned , default = 8
+//Bit 3: 0, reserved
+#define NR_ALPY_SSD_GAIN_OFST ((0x5014 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_nr_alp0_ssd_gain : gain to max ssd normalized 16 as '1' . unsigned , default = 16
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_nr_alp0_ssd_ofst : offset to ssd before dividing to min_err . signed , default = -2
+#define NR_ALP0Y_ERR2CURV_TH_RATE ((0x5015 << 2) + 0xff000000)
+//Bit 31:24, reg_nr_alp0_minerr_ypar0 : threshold0 of curve to map mierr to alp0 for luma channel, this will be set value of flat region mierr that no need blur. 0~255.. unsigned , default = 10
+//Bit 23:16, reg_nr_alp0_minerr_ypar1 : threshold1 of curve to map mierr to alp0 for luma channel,this will be set value of texture region mierr that can not blur.. unsigned , default = 25
+//Bit 15: 8, reg_nr_alp0_minerr_ypar5 : rate0 (for mierr<th0) of curve to map mierr to alp0 for luma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 80
+//Bit 7: 0, reg_nr_alp0_minerr_ypar6 : rate1 (for mierr>th1) of curve to map mierr to alp0 for luma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 64
+#define NR_ALP0Y_ERR2CURV_LIMIT ((0x5016 << 2) + 0xff000000)
+//Bit 31:24, reg_nr_alp0_minerr_ypar2 : level limit(for mierr<th0) of curve to map mierr to alp0 for luma channel, this will be set to alp0 that we can do for flat region. 0~255.. unsigned , default = 63
+//Bit 23:16, reg_nr_alp0_minerr_ypar3 : level limit(for th0<mierr<th1) of curve to map mierr to alp0 for luma channel, this will be set to alp0 that we can do for misc region. 0~255.. unsigned , default = 0
+//Bit 15: 8, reg_nr_alp0_minerr_ypar4 : level limit(for mierr>th1) of curve to map mierr to alp0 for luma channel, this will be set to alp0 that we can do for texture region. 0~255.. unsigned , default = 63
+//Bit 7: 0, reserved
+#define NR_ALP0C_ERR2CURV_TH_RATE ((0x5017 << 2) + 0xff000000)
+//Bit 31:24, reg_nr_alp0_minerr_cpar0 : threshold0 of curve to map mierr to alp0 for chroma channel, this will be set value of flat region mierr that no need blur.. unsigned , default = 10
+//Bit 23:16, reg_nr_alp0_minerr_cpar1 : threshold1 of curve to map mierr to alp0 for chroma channel,this will be set value of texture region mierr that can not blur.. unsigned , default = 25
+//Bit 15: 8, reg_nr_alp0_minerr_cpar5 : rate0 (for mierr<th0) of curve to map mierr to alp0 for chroma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 80
+//Bit 7: 0, reg_nr_alp0_minerr_cpar6 : rate1 (for mierr>th1) of curve to map mierr to alp0 for chroma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 64
+#define NR_ALP0C_ERR2CURV_LIMIT ((0x5018 << 2) + 0xff000000)
+//Bit 31:24, reg_nr_alp0_minerr_cpar2 : level limit(for mierr<th0) of curve to map mierr to alp0 for chroma channel, this will be set to alp0 that we can do for flat region. 0~255.. unsigned , default = 63
+//Bit 23:16, reg_nr_alp0_minerr_cpar3 : level limit(for th0<mierr<th1) of curve to map mierr to alp0 for chroma channel, this will be set to alp0 that we can do for misc region. 0~255.. unsigned , default = 0
+//Bit 15: 8, reg_nr_alp0_minerr_cpar4 : level limit(for mierr>th1) of curve to map mierr to alp0 for chroma channel, this will be set to alp0 that we can do for texture region. 0~255.. unsigned , default = 63
+//Bit 7: 0, reserved
+#define NR_ALP0_MIN_MAX ((0x5019 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_nr_alp0_ymin : normalized to 64 as '1' . unsigned , default = 0
+//Bit 23:22, reserved
+//Bit 21:16, reg_nr_alp0_ymax : normalized to 64 as '1' . unsigned , default = 63
+//Bit 15:14, reserved
+//Bit 13: 8, reg_nr_alp0_cmin : normalized to 64 as '1' . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_nr_alp0_cmax : normalized to 64 as '1' . unsigned , default = 63
+#define NR_ALP1_MIERR_CORING ((0x501a << 2) + 0xff000000)
+//Bit 31:17, reserved
+//Bit 16, reg_nr_alp1_maxerr_mode : 0 max err; 1: xerr . unsigned , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_nr_alp1_core_rate : normalized 64 as "1" . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_nr_alp1_core_ofst : normalized 64 as "1" . signed , default = 3
+#define NR_ALP1_ERR2CURV_TH_RATE ((0x501b << 2) + 0xff000000)
+//Bit 31:24, reg_nr_alp1_minerr_par0 : threshold0 of curve to map mierr to alp1 for luma/chroma channel, this will be set value of flat region mierr that no need directional NR. 0~255.. unsigned , default = 0
+//Bit 23:16, reg_nr_alp1_minerr_par1 : threshold1 of curve to map mierr to alp1 for luma/chroma channel,this will be set value of texture region mierr that can not do directional NR. 0~255.. unsigned , default = 24
+//Bit 15: 8, reg_nr_alp1_minerr_par5 : rate0 (for mierr<th0) of curve to map mierr to alp1 for luma/chroma channel. the larger of the value, the deep of the slope.. unsigned , default = 0
+//Bit 7: 0, reg_nr_alp1_minerr_par6 : rate1 (for mierr>th1) of curve to map mierr to alp1 for luma/chroma channel. the larger of the value, the deep of the slope. 0~255. unsigned , default = 20
+#define NR_ALP1_ERR2CURV_LIMIT ((0x501c << 2) + 0xff000000)
+//Bit 31:24, reg_nr_alp1_minerr_par2 : level limit(for mierr<th0) of curve to map mierr to alp1 for luma/chroma channel, this will be set to alp1 that we can do for flat region. 0~255.. unsigned , default = 0
+//Bit 23:16, reg_nr_alp1_minerr_par3 : level limit(for th0<mierr<th1) of curve to map mierr to alp1 for luma/chroma channel, this will be set to alp1 that we can do for misc region. 0~255.. unsigned , default = 16
+//Bit 15: 8, reg_nr_alp1_minerr_par4 : level limit(for mierr>th1) of curve to map mierr to alp1 for luma/chroma channel, this will be set to alp1 that we can do for texture region. 0~255.255 before. unsigned , default = 63
+//Bit 7: 0, reserved
+#define NR_ALP1_MIN_MAX ((0x501d << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_nr_alp1_ymin : normalized to 64 as '1' . unsigned , default = 0
+//Bit 23:22, reserved
+//Bit 21:16, reg_nr_alp1_ymax : normalized to 64 as '1' . unsigned , default = 63
+//Bit 15:14, reserved
+//Bit 13: 8, reg_nr_alp1_cmin : normalized to 64 as '1' . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_nr_alp1_cmax : normalized to 64 as '1' . unsigned , default = 63
+#define PK_ALP2_MIERR_CORING ((0x501e << 2) + 0xff000000)
+//Bit 31:17, reserved
+//Bit 16, reg_pk_alp2_maxerr_mode : 0 max err; 1: xerr . unsigned , default = 1
+//Bit 15:14, reserved
+//Bit 13: 8, reg_pk_alp2_core_rate : normalized 64 as "1" . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_pk_alp2_core_ofst : normalized 64 as "1" . signed , default = 1
+#define PK_ALP2_ERR2CURV_TH_RATE ((0x501f << 2) + 0xff000000)
+//Bit 31:24, reg_pk_alp2_minerr_par0 : threshold0 of curve to map mierr to alp2 for luma channel, this will be set value of flat region mierr that no need peaking.. unsigned , default = 0
+//Bit 23:16, reg_pk_alp2_minerr_par1 : threshold1 of curve to map mierr to alp2 for luma channel,this will be set value of texture region mierr that can not do peaking. 0~255.. unsigned , default = 24
+//Bit 15: 8, reg_pk_alp2_minerr_par5 : rate0 (for mierr<th0) of curve to map mierr to alp2 for luma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 0
+//Bit 7: 0, reg_pk_alp2_minerr_par6 : rate1 (for mierr>th1) of curve to map mierr to alp2 for luma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 20
+#define PK_ALP2_ERR2CURV_LIMIT ((0x5020 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_alp2_minerr_par2 : level limit(for mierr<th0) of curve to map mierr to alp2 for luma channel, this will be set to alp2 that we can do for flat region. 0~255.. unsigned , default = 0
+//Bit 23:16, reg_pk_alp2_minerr_par3 : level limit(for th0<mierr<th1) of curve to map mierr to alp2 for luma channel, this will be set to alp2 that we can do for misc region. 0~255.. unsigned , default = 16
+//Bit 15: 8, reg_pk_alp2_minerr_par4 : level limit(for mierr>th1) of curve to map mierr to alp2 for luma channel, this will be set to alp2 that we can do for texture region. 0~255. default = 32;. unsigned , default = 32
+//Bit 7: 0, reserved
+#define PK_ALP2_MIN_MAX ((0x5021 << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13: 8, reg_pk_alp2_min : normalized to 64 as '1' . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_pk_alp2_max : normalized to 64 as '1' . unsigned , default = 63
+#define PK_FINALGAIN_HP_BP ((0x5022 << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:16, reg_final_gain_rs : s2: right shift bits for the gain normalization, 0 normal to 32 as 1; 1 normalize to 64 as 1; -2 normalized to 8 as 1; -1 normalize 16 as 1. default = 0
+//Bit 15: 8, reg_hp_final_gain : gain to highpass boost result (including directional/circle blending), normalized 32 as '1', 0~255. 1.25 * 32. unsigned , default = 40
+//Bit 7: 0, reg_bp_final_gain : gain to bandpass boost result (including directional/circle blending), normalized 32 as '1', 0~255. 1.25 * 32. unsigned , default = 30
+#define PK_OS_HORZ_CORE_GAIN ((0x5023 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_os_hsidecore : side coring (not to current pixel) to adaptive overshoot margin in horizontal direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 8
+//Bit 23:16, reg_pk_os_hsidegain : side gain (not to current pixel) to adaptive overshoot margin in horizontal direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20
+//Bit 15: 8, reg_pk_os_hmidcore : midd coring (to current pixel) to adaptive overshoot margin in horizontal direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 2
+//Bit 7: 0, reg_pk_os_hmidgain : midd gain (to current pixel) to adaptive overshoot margin in horizontal direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20
+#define PK_OS_VERT_CORE_GAIN ((0x5024 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_os_vsidecore : side coring (not to current pixel) to adaptive overshoot margin in vertical direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 8
+//Bit 23:16, reg_pk_os_vsidegain : side gain (not to current pixel) to adaptive overshoot margin in vertical direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20
+//Bit 15: 8, reg_pk_os_vmidcore : midd coring (to current pixel) to adaptive overshoot margin in vertical direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 2
+//Bit 7: 0, reg_pk_os_vmidgain : midd gain (to current pixel) to adaptive overshoot margin in vertical direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20
+#define PK_OS_ADPT_MISC ((0x5025 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_os_minerr_core : coring to minerr for adaptive overshoot margin. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 40
+//Bit 23:16, reg_pk_os_minerr_gain : gain to minerr based adaptive overshoot margin. normalized to 64 as '1'. 0~255;. unsigned , default = 6
+//Bit 15: 8, reg_pk_os_adpt_max : maximum limit adaptive overshoot margin (4x). 0~255; . unsigned , default = 200
+//Bit 7: 0, reg_pk_os_adpt_min : minimun limit adaptive overshoot margin (1x). 0~255; . unsigned , default = 20
+#define PK_OS_STATIC ((0x5026 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:28, reg_pk_osh_mode : 0~3: (2x+1) window in H direction . unsigned , default = 2
+//Bit 27:26, reserved
+//Bit 25:24, reg_pk_osv_mode : 0~3: (2x+1) window in V direction . unsigned , default = 2
+//Bit 23:22, reserved
+//Bit 21:12, reg_pk_os_down : static negative overshoot margin. 0~1023; . unsigned , default = 200
+//Bit 11:10, reserved
+//Bit 9: 0, reg_pk_os_up : static positive overshoot margin. 0~1023; . unsigned , default = 200
+#define PK_NR_ENABLE ((0x5027 << 2) + 0xff000000)
+//Bit 31: 4, reserved
+//Bit 3: 2, reg_3d_mode , 0: no 3D; 1: L/R; 2: T/B; 3: horizontal interleaved, dft = 0 //. unsigned , default = 0
+//Bit 1, reg_pk_en . unsigned , default = 1
+//Bit 0, reg_nr_en . unsigned , default = 1
+#define PK_DRT_SAD_MISC ((0x5028 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_sad_ver_gain : gain to sad[4], 16 normalized to "1"; . unsigned , default = 32
+//Bit 23:16, reg_pk_sad_hor_gain : gain to sad[0], 16 normalized to "1"; . unsigned , default = 24
+//Bit 15:12, reserved
+//Bit 11 reserved
+//Bit 10: 9, reg_pk_bias_diag : bias towards diag . unsigned , default = 0
+//Bit 8, reserved
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_pk_drt_force : force direction of drt peaking filter, h2b: 0:hp drt force, 1: bp drt force; 2: bp+hp drt force, 3: no force;. unsigned , default = 24
+#define NR_TI_DNLP_BLEND ((0x5029 << 2) + 0xff000000)
+//Bit 31:11, reserved
+//Bit 10: 8, reg_dnlp_input_mode : dnlp input options. 0: org_y; 1: gau_y; 2: gauadp_y; 3: edgadplpf_y; 4: nr_y;5: lti_y; 6: pk_y (before os);7: pk_y (after os). unsigned , default = 4
+//Bit 7: 4, reserved
+//Bit 3: 2, reg_nr_cti_blend_mode : blend mode of nr and lti result: 0: nr; 1:cti; 2: (nr+cti)/2; 3:cti + dlt_nr . unsigned , default = 1
+//Bit 1: 0, reg_nr_lti_blend_mode : blend mode of nr and lti result: 0: nr; 1:lti; 2: (nr+lti)/2; 3:lti + dlt_nr . unsigned , default = 2
+////////////////////////////////////////////////////////////////////////////////
+// new ti regsters from here
+////////////////////////////////////////////////////////////////////////////////
+#define LTI_DIR_CORE_ALPHA ((0x502a << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_adp_lti_dir_alp_core_ofst : ofst to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=10. unsigned , default = 10
+//Bit 23:20, reserved
+//Bit 19:16, reg_adp_lti_dir_alp_core_rate : ofset to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=0/32. unsigned , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_adp_lti_dir_alpmin : min value of alpha, alpha = (min_err+x +ofst)/max_err*64; dft=10 . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_adp_lti_dir_alpmax : max value of alpha, alpha = (min_err+x +ofst)/max_err*64; dft=63 . unsigned , default = 63
+#define CTI_DIR_ALPHA ((0x502b << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_adp_cti_dir_alp_core_ofst : ofst to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=10. unsigned , default = 5
+//Bit 23:20, reserved
+//Bit 19:16, reg_adp_cti_dir_alp_core_rate : ofset to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=0/32. unsigned , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_adp_cti_dir_alpmin : min value of alpha, alpha = (min_err +x+ofst)/max_err*64; dft=10 . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_adp_cti_dir_alpmax : max value of alpha, alpha = (min_err +x+ofst)/max_err*64; dft=63 . unsigned , default = 63
+#define LTI_CTI_DF_GAIN ((0x502c << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_adp_lti_hdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12
+//Bit 23:22, reserved
+//Bit 21:16, reg_adp_lti_vdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12
+//Bit 15:14, reserved
+//Bit 13: 8, reg_adp_cti_hdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_adp_cti_vdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12
+#define LTI_CTI_DIR_AC_DBG ((0x502d << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30, reg_adp_lti_dir_lpf : 0: no lpf; 1: [1 2 2 2 1]/8 lpf . unsigned , default = 1
+//Bit 29, reserved
+//Bit 28, reg_adp_lti_dir_difmode : 0: y_dif; 1: y_dif + (u_dif+v_dif)/2; . unsigned , default = 1
+//Bit 27, reserved
+//Bit 26, reg_adp_cti_dir_lpf : 0: no lpf; 1: [1 2 2 2 1]/8 lpf dft=1 . unsigned , default = 1
+//Bit 25:24, reg_adp_cti_dir_difmode : 0: (u_dif+v_dif); 1: y_dif/2 + (u_dif+v_dif)*3/4; 2: y_dif + (u_dif+v_dif)/2; 3: y_dif*2 (not recomended). unsigned , default = 2
+//Bit 23:22, reg_adp_hvlti_dcblend_mode : 0: hlti_dc; 1:vlti_dc; 2: avg 3; blend on alpha . unsigned , default = 3
+//Bit 21:20, reg_adp_hvcti_dcblend_mode : 0: hcti_dc; 1:vcti_dc; 2: avg 3; blend on alpha . unsigned , default = 2
+//Bit 19:18, reg_adp_hvlti_acblend_mode : hlti_ac; 1:vlti_ac; 2: add 3;:adaptive to alpha . unsigned , default = 3
+//Bit 17:16, reg_adp_hvcti_acblend_mode : hcti_ac; 1:vcti_ac; 2: add 3;: adaptive to alpha . unsigned , default = 2
+//Bit 15, reserved
+//Bit 14:12, reg_adp_hlti_debug , for hlti debug, default = 0 . unsigned , default = 0
+//Bit 11, reserved
+//Bit 10: 8, reg_adp_vlti_debug , for vlti debug, default = 0 . unsigned , default = 0
+//Bit 7, reserved
+//Bit 6: 4, reg_adp_hcti_debug , for hcti debug, default = 0 . unsigned , default = 0
+//Bit 3, reserved
+//Bit 2: 0, reg_adp_vcti_debug , for vcti debug, default = 0 . unsigned , default = 0
+#define HCTI_FLT_CLP_DC ((0x502e << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28, reg_adp_hcti_en , 0: no cti, 1: new cti, default = 1 . unsigned , default = 1
+//Bit 27:26, reg_adp_hcti_vdn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 25:24, reg_adp_hcti_hdn_flt , 0: no lpf; 1:[0, 0, 0, 4, 8, 4, 0, 0, 0], 2:[0, 0, 2, 4, 4, 4, 2, 0, 0], 3: [1, 2, 2, 2, 2, 2, 2, 2, 1], default = 2. unsigned , default = 2
+//Bit 23:22, reg_adp_hcti_ddn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 21:20, reg_adp_hcti_lpf0_flt , 0:no filter; 1:sigma=0.75, 2: sigma = 1.0, 3: sigma = 1.5, default = 1 . unsigned , default = 1
+//Bit 19:18, reg_adp_hcti_lpf1_flt , 0:no filter; 1:sigma= 2.0, 2: sigma = 3.0, 3: sigma = 4.0, default = 1 . unsigned , default = 1
+//Bit 17:16, reg_adp_hcti_lpf2_flt , 0:no filter; 1:sigma=5.0, 2: sigma = 9.0, 3: sigma = 13.0, default = 1 . unsigned , default = 1
+//Bit 15:12, reg_adp_hcti_hard_clp_win , window size, 0~8, default = 5 . unsigned , default = 5
+//Bit 11: 8, reg_adp_hcti_hard_win_min , window size, 0~8, default = 3 . unsigned , default = 3
+//Bit 7: 5, reserved
+//Bit 4, reg_adp_hcti_clp_mode , 0: hard clip, 1: adaptive clip, default = 1 . unsigned , default = 1
+//Bit 3, reserved
+//Bit 2: 0, reg_adp_hcti_dc_mode , 0:dn, 1:lpf0, 2:lpf1, 3:lpf2, 4: lpf3: 5: vdn result; 6/7:org, default = 0 . unsigned , default = 0
+#define HCTI_BST_GAIN ((0x502f << 2) + 0xff000000)
+//Bit 31:24, reg_adp_hcti_bst_gain0 : gain of the bandpass 0 (lpf1-lpf2)- LBP, default = 80 . unsigned , default = 80
+//Bit 23:16, reg_adp_hcti_bst_gain1 : gain of the bandpass 1 (lpf0-lpf1)- BP, default = 96 . unsigned , default = 96
+//Bit 15: 8, reg_adp_hcti_bst_gain2 : gain of the bandpass 2 (hdn-lpf0)- HP, default = 64 . unsigned , default = 64
+//Bit 7: 0, reg_adp_hcti_bst_gain3 : gain of the unsharp band (yuvin-hdn) - US, default = 16 . unsigned , default = 16
+#define HCTI_BST_CORE ((0x5030 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_hcti_bst_core0 : core of the bandpass 0 (lpf1-lpf2)- LBP, default = 5 . unsigned , default = 5
+//Bit 23:16, reg_adp_hcti_bst_core1 : core of the bandpass 1 (lpf0-lpf1)- BP, default = 5 . unsigned , default = 5
+//Bit 15: 8, reg_adp_hcti_bst_core2 : core of the bandpass 2 (hdn-lpf0)- HP, default = 5 . unsigned , default = 5
+//Bit 7: 0, reg_adp_hcti_bst_core3 : core of the unsharp band (yuvin-hdn) - US, default = 3 . unsigned , default = 5
+#define HCTI_CON_2_GAIN_0 ((0x5031 << 2) + 0xff000000)
+//Bit 31:29, reg_adp_hcti_con_mode : con mode 0:[0, 0,-1, 1, 0, 0, 0]+[0, 0, 0, 1,-1, 0, 0], 1: [0, 0,-1, 0, 1, 0, 0], 2: [0,-1, 0, 0, 0, 1, 0], 3:[-1, 0, 0, 0, 0, 0, 1], 4: .... default = 1. unsigned , default = 1
+//Bit 28:26, reg_adp_hcti_dx_mode : dx mode 0: [-1 1 0]; 1~7: [-1 (2x+1)"0" 1], default = 2 . unsigned , default = 2
+//Bit 25:24, reg_adp_hcti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0
+//Bit 23:16, reg_adp_hcti_con_2_gain0 , default = 25 . unsigned , default = 25
+//Bit 15: 8, reg_adp_hcti_con_2_gain1 , default = 60 . unsigned , default = 60
+//Bit 7: 0, reg_adp_hcti_con_2_gain2 0;, default = 5 . unsigned , default = 5
+#define HCTI_CON_2_GAIN_1 ((0x5032 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_hcti_con_2_gain3 96;, default = 96 . unsigned , default = 96
+//Bit 23:16, reg_adp_hcti_con_2_gain4 5;, default = 5 . unsigned , default = 5
+//Bit 15: 8, reg_adp_hcti_con_2_gain5 80;, default = 80 . unsigned , default = 80
+//Bit 7: 0, reg_adp_hcti_con_2_gain6 20;, default = 20 . unsigned , default = 20
+#define HCTI_OS_MARGIN ((0x5033 << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_adp_hcti_os_margin : margin for hcti overshoot, default = 0 . unsigned , default = 0
+#define HLTI_FLT_CLP_DC ((0x5034 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28, reg_adp_hlti_en , 0: no cti, 1: new cti, default = 1 . unsigned , default = 1
+//Bit 27:26, reg_adp_hlti_vdn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 25:24, reg_adp_hlti_hdn_flt , 0: no lpf; 1:[0, 0, 0, 4, 8, 4, 0, 0, 0], 2:[0, 0, 2, 4, 4, 4, 2, 0, 0], 3: [1, 2, 2, 2, 2, 2, 2, 2, 1], default = 1. unsigned , default = 1
+//Bit 23:22, reg_adp_hlti_ddn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 1 . unsigned , default = 1
+//Bit 21:20, reg_adp_hlti_lpf0_flt , 0:no filter; 1:sigma=0.75, 2: sigma = 1.0, 3: sigma = 1.5, default = 1 . unsigned , default = 1
+//Bit 19:18, reg_adp_hlti_lpf1_flt , 0:no filter; 1:sigma= 2.0, 2: sigma = 3.0, 3: sigma = 4.0, default = 1 . unsigned , default = 1
+//Bit 17:16, reg_adp_hlti_lpf2_flt , 0:no filter; 1:sigma=5.0, 2: sigma = 9.0, 3: sigma = 13.0, default = 1 . unsigned , default = 1
+//Bit 15:12, reg_adp_hlti_hard_clp_win , window size, 0~8, default = 2 . unsigned , default = 2
+//Bit 11: 8, reg_adp_hlti_hard_win_min , window size, 0~8, default = 1 . unsigned , default = 1
+//Bit 7: 5, reserved
+//Bit 4, reg_adp_hlti_clp_mode , 0: hard clip, 1: adaptive clip, default = 0 . unsigned , default = 0
+//Bit 3, reserved
+//Bit 2: 0, reg_adp_hlti_dc_mode , 0:dn, 1:lpf0, 2:lpf1, 3:lpf2, 4: lpf3: 5: vdn result; 6/7:org, default = 4 . unsigned , default = 4
+#define HLTI_BST_GAIN ((0x5035 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_hlti_bst_gain0 : gain of the bandpass 0 (lpf1-lpf2)- LBP, default = 32 . unsigned , default = 32
+//Bit 23:16, reg_adp_hlti_bst_gain1 : gain of the bandpass 1 (lpf0-lpf1)- BP, default = 32 . unsigned , default = 32
+//Bit 15: 8, reg_adp_hlti_bst_gain2 : gain of the bandpass 2 (hdn-lpf0)- HP, default = 28 . unsigned , default = 28
+//Bit 7: 0, reg_adp_hlti_bst_gain3 : gain of the unsharp band (yuvin-hdn) - US, default = 12 . unsigned , default = 12
+#define HLTI_BST_CORE ((0x5036 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_hlti_bst_core0 : core of the bandpass 0 (lpf1-lpf2)- LBP, default = 5 . unsigned , default = 5
+//Bit 23:16, reg_adp_hlti_bst_core1 : core of the bandpass 1 (lpf0-lpf1)- BP, default = 5 . unsigned , default = 5
+//Bit 15: 8, reg_adp_hlti_bst_core2 : core of the bandpass 2 (hdn-lpf0)- HP, default = 5 . unsigned , default = 5
+//Bit 7: 0, reg_adp_hlti_bst_core3 : core of the unsharp band (yuvin-hdn) - US, default = 3 . unsigned , default = 3
+#define HLTI_CON_2_GAIN_0 ((0x5037 << 2) + 0xff000000)
+//Bit 31:29, reg_adp_hlti_con_mode : con mode 0:[0, 0,-1, 1, 0, 0, 0]+[0, 0, 0, 1,-1, 0, 0], 1: [0, 0,-1, 0, 1, 0, 0], 2: [0,-1, 0, 0, 0, 1, 0], 3:[-1, 0, 0, 0, 0, 0, 1], 4: ....., default = 1. unsigned , default = 1
+//Bit 28:26, reg_adp_hlti_dx_mode : dx mode 0: [-1 1 0]; 1~7: [-1 (2x+1)"0" 1], default = 1 . unsigned , default = 1
+//Bit 25:24, reg_adp_hlti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0
+//Bit 23:16, reg_adp_hlti_con_2_gain0 25;, default = 25 . unsigned , default = 25
+//Bit 15: 8, reg_adp_hlti_con_2_gain1 60;, default = 60 . unsigned , default = 60
+//Bit 7: 0, reg_adp_hlti_con_2_gain2 0;, default = 5 . unsigned , default = 5
+#define HLTI_CON_2_GAIN_1 ((0x5038 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_hlti_con_2_gain3 96;, default = 96 . unsigned , default = 96
+//Bit 23:16, reg_adp_hlti_con_2_gain4 5;, default = 95 . unsigned , default = 95
+//Bit 15: 8, reg_adp_hlti_con_2_gain5 80;, default = 80 . unsigned , default = 80
+//Bit 7: 0, reg_adp_hlti_con_2_gain6 20;, default = 20 . unsigned , default = 20
+#define HLTI_OS_MARGIN ((0x5039 << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_adp_hlti_os_margin : margin for hlti overshoot, default = 0 . unsigned , default = 0
+#define VLTI_FLT_CON_CLP ((0x503a << 2) + 0xff000000)
+//Bit 31:15, reserved
+//Bit 14, reg_adp_vlti_en : enable bit of vlti, default = 1 . unsigned , default = 1
+//Bit 13:12, reg_adp_vlti_hxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 11:10, reg_adp_vlti_dxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 9: 8, reg_adp_vlti_han_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 7: 6, reg_adp_vlti_dan_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 5: 4, reg_adp_vlti_dx_mode : 0:[-1 1] 1:[-1 0 -1]; 2/3: [-1 0 0 0 -1], default = 1 . unsigned , default = 1
+//Bit 3, reserved
+//Bit 2, reg_adp_vlti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0
+//Bit 1, reserved
+//Bit 0, reg_adp_vlti_hard_clp_win : window size; 0: 1x3 window; 1: 1x5 window, default = 0 . unsigned , default = 0
+#define VLTI_BST_GAIN ((0x503b << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_adp_vlti_bst_gain0 : gain to boost filter [-1 2 -1];, default = 32 . unsigned , default = 32
+//Bit 15: 8, reg_adp_vlti_bst_gain1 : gain to boost filter [-1 0 2 0 -1];, default = 32 . unsigned , default = 32
+//Bit 7: 0, reg_adp_vlti_bst_gain2 : gain to boost filter usf, default = 32 . unsigned , default = 32
+#define VLTI_BST_CORE ((0x503c << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_adp_vlti_bst_core0 : coring to boost filter [-1 2 -1];, default = 5 . unsigned , default = 5
+//Bit 15: 8, reg_adp_vlti_bst_core1 : coring to boost filter [-1 0 2 0 -1];, default = 5 . unsigned , default = 5
+//Bit 7: 0, reg_adp_vlti_bst_core2 : coring to boost filter usf, default = 3 . unsigned , default = 3
+#define VLTI_CON_2_GAIN_0 ((0x503d << 2) + 0xff000000)
+//Bit 31:24, reg_adp_vlti_con_2_gain0 25;, default = 25 . unsigned , default = 25
+//Bit 23:16, reg_adp_vlti_con_2_gain1 60;, default = 60 . unsigned , default = 60
+//Bit 15: 8, reg_adp_vlti_con_2_gain2 0;, default = 5 . unsigned , default = 5
+//Bit 7: 0, reg_adp_vlti_con_2_gain3 96;, default = 96 . unsigned , default = 96
+#define VLTI_CON_2_GAIN_1 ((0x503e << 2) + 0xff000000)
+//Bit 31:24, reg_adp_vlti_con_2_gain4 5;, default = 95 . unsigned , default = 95
+//Bit 23:16, reg_adp_vlti_con_2_gain5 80;, default = 80 . unsigned , default = 80
+//Bit 15: 8, reg_adp_vlti_con_2_gain6 20;, default = 20 . unsigned , default = 20
+//Bit 7: 0, reg_adp_vlti_os_margin : margin for vlti overshoot, default = 0 . unsigned , default = 0
+#define VCTI_FLT_CON_CLP ((0x503f << 2) + 0xff000000)
+//Bit 31:15, reserved
+//Bit 14, reg_adp_vcti_en : enable bit of vlti, default = 1 . unsigned , default = 1
+//Bit 13:12, reg_adp_vcti_hxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 11:10, reg_adp_vcti_dxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 9: 8, reg_adp_vcti_han_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 7: 6, reg_adp_vcti_dan_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 5: 4, reg_adp_vcti_dx_mode : 0:[-1 1] 1:[-1 0 -1]; 2/3: [-1 0 0 0 -1], default = 1 . unsigned , default = 1
+//Bit 3, reserved
+//Bit 2, reg_adp_vcti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0
+//Bit 1, reserved
+//Bit 0, reg_adp_vcti_hard_clp_win : window size; 0: 1x3 window; 1: 1x5 window, default = 0 . unsigned , default = 0
+#define VCTI_BST_GAIN ((0x5040 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_adp_vcti_bst_gain0 : gain to boost filter [-1 2 -1];, default = 16 . unsigned , default = 16
+//Bit 15: 8, reg_adp_vcti_bst_gain1 : gain to boost filter [-1 0 2 0 -1];, default = 16 . unsigned , default = 16
+//Bit 7: 0, reg_adp_vcti_bst_gain2 : gain to boost filter usf, default = 16 . unsigned , default = 16
+#define VCTI_BST_CORE ((0x5041 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_adp_vcti_bst_core0 : coring to boost filter [-1 2 -1];, default = 5 . unsigned , default = 5
+//Bit 15: 8, reg_adp_vcti_bst_core1 : coring to boost filter [-1 0 2 0 -1];, default = 5 . unsigned , default = 5
+//Bit 7: 0, reg_adp_vcti_bst_core2 : coring to boost filter usf, default = 3 . unsigned , default = 3
+#define VCTI_CON_2_GAIN_0 ((0x5042 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_vcti_con_2_gain0 25;, default = 25 . unsigned , default = 25
+//Bit 23:16, reg_adp_vcti_con_2_gain1 60;, default = 60 . unsigned , default = 60
+//Bit 15: 8, reg_adp_vcti_con_2_gain2 0;, default = 5 . unsigned , default = 5
+//Bit 7: 0, reg_adp_vcti_con_2_gain3 96;, default = 96 . unsigned , default = 96
+#define VCTI_CON_2_GAIN_1 ((0x5043 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_vcti_con_2_gain4 5;, default = 95 . unsigned , default = 95
+//Bit 23:16, reg_adp_vcti_con_2_gain5 80;, default = 80 . unsigned , default = 80
+//Bit 15: 8, reg_adp_vcti_con_2_gain6 20;, default = 20 . unsigned , default = 20
+//Bit 7: 0, reg_adp_vcti_os_margin : margin for vcti overshoot, default = 0 . unsigned , default = 0
+#define SHARP_3DLIMIT ((0x5044 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_3d_mid_width ,width of left part of 3d input, dft = half size of input width default = 0 . unsigned , default = 960
+//Bit 15:13, reserved
+//Bit 12: 0, reg_3d_mid_height ,height of left part of 3d input, dft = half size of input height default = 0 . unsigned , default = 540
+#define DNLP_EN ((0x5045 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_dnlp_hblank
+//Bit 7: 1, reserved
+//Bit 0, reg_dnlp_en . unsigned , default = 1
+#define DEMO_CRTL ((0x5056 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18:17, demo_disp_position . unsigned , default = 2
+//Bit 16, demo_hsvsharp_enable . unsigned , default = 0
+//Bit 15:13, reserved
+//Bit 12: 0, demo_left_top_screen_width : . unsigned , default = 360
+#define SHARP_SR2_CTRL ((0x5057 << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24 reg_sr2_bic_pknr_bypass :
+//Bit 23:22 reserved
+//Bit 21:16, reg_sr2_pk_la_err_dis_rate : . unsigned , low angle and high angle error should not be no less than nearby_error*rate/64; default = 24
+//Bit 15:8, reg_sr2_pk_sad_diag_gain : . unsigned , gain to sad[2] and sad[6], 16 normalized to "1"; default = 16
+//Bit 7, reg_sr2_vert_outphs : . unsigned , default = 0
+//Bit 6, reg_sr2_horz_outphs : . unsigned , default = 0
+//Bit 5, reg_sr2_vert_ratio : . unsigned , default = 0
+//Bit 4, reg_sr2_hori_ratio : . unsigned , default = 0
+//Bit 3, reg_sr2_bic_norm : . unsigned , default = 1
+//Bit 2, reg_sr2_enable : . unsigned , default = 0
+//Bit 1, reg_sr2_sharp_prc_lr_hbic : . unsigned , default = 0
+//Bit 0, reg_sr2_sharp_prc_lr : lti/cti/nr/peaking processing using LR grid, 0: on HR grid; 1:on LR grid, horizontally no upscale, but using simple bic . unsigned , default = 0
+#define SHARP_SR2_YBIC_HCOEF0 ((0x5058 << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_y_bic_hcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel Filter will be normalized to 128 as ‘1’; default=0
+//Bit 23:16, reg_sr2_y_bic_hcoef02 the same as above; default=0
+//Bit 15: 8, reg_sr2_y_bic_hcoef01 the same as above; default=64
+//Bit 7: 0, reg_sr2_y_bic_hcoef00 the same as above; default=0
+#define SHARP_SR2_YBIC_HCOEF1 ((0x5059 << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_y_bic_hcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channel,Filter will be normalized to 128 as ‘1’; default=-4
+//Bit 23:16, reg_sr2_y_bic_hcoef12 the same as above; default=36
+//Bit 15: 8, reg_sr2_y_bic_hcoef11 the same as above; default=36
+//Bit 7: 0, reg_sr2_y_bic_hcoef10 the same as above; default=-4
+#define SHARP_SR2_CBIC_HCOEF0 ((0x505a << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_c_bic_hcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel ,Filter will be normalized to 128 as ‘1’; default=0
+//Bit 23:16, reg_sr2_c_bic_hcoef02 the same as above; default=21
+//Bit 15: 8, reg_sr2_c_bic_hcoef01 the same as above; default=22
+//Bit 7: 0, reg_sr2_c_bic_hcoef00 the same as above; default=21
+#define SHARP_SR2_CBIC_HCOEF1 ((0x505b << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_c_bic_hcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channel,Filter will be normalized to 128 as ‘1’; default=-4
+//Bit 23:16, reg_sr2_c_bic_hcoef12 the same as above; default=36
+//Bit 15: 8, reg_sr2_c_bic_hcoef11 the same as above; default=36
+//Bit 7: 0, reg_sr2_c_bic_hcoef10 the same as above; default=-4
+#define SHARP_SR2_YBIC_VCOEF0 ((0x505c << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_y_bic_vcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel, Filter will be normalized to 128 as ‘1’; default=0
+//Bit 23:16, reg_sr2_y_bic_vcoef02 the same as above; default=0
+//Bit 15: 8, reg_sr2_y_bic_vcoef01 the same as above; default=64
+//Bit 7: 0, reg_sr2_y_bic_vcoef00 the same as above; default=0
+#define SHARP_SR2_YBIC_VCOEF1 ((0x505d << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_y_bic_vcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channe, lFilter will be normalized to 128 as ‘1’; default=-4
+//Bit 23:16, reg_sr2_y_bic_vcoef12 the same as above; default=36
+//Bit 15: 8, reg_sr2_y_bic_vcoef11 the same as above; default=36
+//Bit 7: 0, reg_sr2_y_bic_vcoef10 the same as above; default=-4
+#define SHARP_SR2_CBIC_VCOEF0 ((0x505e << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_c_bic_vcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel, Filter will be normalized to 128 as ‘1’; default=0
+//Bit 23:16, reg_sr2_c_bic_vcoef02 the same as above; default=21
+//Bit 15: 8, reg_sr2_c_bic_vcoef01 the same as above; default=22
+//Bit 7: 0, reg_sr2_c_bic_vcoef00 the same as above; default=21
+#define SHARP_SR2_CBIC_VCOEF1 ((0x505f << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_c_bic_vcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channel,Filter will be normalized to 128 as ‘1’; default=-4
+//Bit 23:16, reg_sr2_c_bic_vcoef12 the same as above; default=36
+//Bit 15: 8, reg_sr2_c_bic_vcoef11 the same as above; default=36
+//Bit 7: 0, reg_sr2_c_bic_vcoef10 the same as above; default=-4
+#define SHARP_SR2_MISC ((0x5060 << 2) + 0xff000000)
+//Bit 31:2, reserved
+//Bit 1, reg_sr2_cmpmux_bef : . unsigned , default = 0,0 no swap anf for YUV->YUV; 1, swapped and for RGB->GBR;
+//Bit 0, reg_sr2_cmpmux_aft : . unsigned , default = 0,0 no swap anf for YUV->YUV; 1, swapped and for GBR-RGB;
+#define SHARP_SR3_SAD_CTRL ((0x5061 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_sr3_pk_sad_core_rate // u6: rate of coring for sad(theta) - sad(theta+pi/2)*rate/64
+//Bit 23:22 reserved
+//Bit 21:16 reg_sr3_lti_sad_core_rate // u6: rate of coring for sad(theta) - sad(theta+pi/2)*rate/64 , default= 6
+//Bit 15:14 reserved
+//Bit 13:8 reg_sr3_cti_sad_core_rate // u6: rate of coring for sad(theta) - sad(theta+pi/2)*rate/64 , default= 6
+//Bit 7, reg_sr3_lti_hsad_mode // u1: mode for hsad of lti caluclation; 0: block based; 1:othor shape; default= 1
+//Bit 6, reg_sr3_cti_hsad_mode // u1: mode for hsad of cti caluclation; 0: block based; 1:othor shape; default= 1
+//Bit 5, reg_sr3_lti_dsad_mode // u1: mode for dsad of lti caluclation, 0: block based; 1:othor shape; default= 1
+//Bit 4, reg_sr3_cti_dsad_mode // u1: mode for dsad of cti caluclation, 0: block based; 1:othor shape; default= 1
+//Bit 3, reg_sr3_lti_vsad_mode // u1: mode for vsad of lti caluclation, 0: block based; 1:othor shape; default= 1
+//Bit 2, reg_sr3_cti_vsad_mode // u1: mode for vsad of cti caluclation, 0: block based; 1:othor shape; default= 1
+//Bit 1, reg_sr3_lti_hsad_hlpf // u1: hlpf for hsad of lti caluclation, 0: no hlpf; 1: with [1 2 1] hlpf; default= 1
+//Bit 0, reg_sr3_cti_hsad_hlpf // u1: hlpf for hsad of cti caluclation, 0: no hlpf; 1: with [1 2 1] hlpf; default= 1
+#define SHARP_SR3_PK_CTRL0 ((0x5062 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11, reg_sr3_pk_sad_mode // u1: mode for sad of peaking and noise reduction, 0: block based; 1:othor shape; default= 1
+//Bit 10, reg_sr3_pk_hsad_hlpf // u1: hlpf for hsad for peaking caluclation, 0: no hlpf; 1: with [1 2 2 2 1] hlpf; default= 1
+//Bit 9, reg_sr3_pk_vsad_hlpf // u1: hlpf for vsad for peaking caluclation, 0: no hlpf; 1: with [1 2 2 2 1] hlpf; default= 1
+//Bit 8, reg_sr3_pk_dsad_hlpf // u1: hlpf for dsad for peaking caluclation, 0: no hlpf; 1: with [1 2 2 2 1] hlpf; default= 1
+//Bit 7:6, reg_sr3_pk_hpdrt_mode // u2: mode for HPdrt filter: default= 3
+//Bit 5:4, reg_sr3_pk_bpdrt_mode // u2: mode for BPdrt filter: default= 3
+//Bit 3:2, reg_sr3_pk_drtbld_range // u2: range of the min2 and min direction distance; default =1
+//Bit 1, reserved
+//Bit 0, reg_sr3_pk_ti_blend_mode // u1: blend mode of the TI and PK results: default = 0;
+#define SHARP_SR3_PK_CTRL1 ((0x5063 << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30:28, reg_sr3_pk_hp_hvcon_replace8_maxsad //u3: replace HP hvcon by maxsad, default =1
+//Bit 27, reserved
+//Bit 26:24, reg_sr3_pk_bp_hvcon_replace8_maxsad //u3: replace HP hvcon by maxsad, default =1
+//Bit 23:16, reg_sr3_pk_hp_hvcon_replace8lv_gain //u8: gain to local variant before calculating the hv gain for peaking, normalized to 32 as "1" default = 32;
+//Bit 15:8, reg_sr3_pk_bp_hvcon_replace8lv_gain //u8: gain to local variant before calculating the hv gain for peaking, normalized to 32 as "1" default = 32;
+//Bit 7, reg_sr3_sad_intlev_mode //u1: interleave detection xerr mode: 0 max; 1:sum default=1
+//Bit 6, reg_sr3_sad_intlev_mode1 //u1: mode 1 of using diagonal protection: 0: no digonal protection; 1: with diagonal protection default=1
+//Bit 5:0, reg_sr3_sad_intlev_gain //u6: interleave detection for sad gain applied, normalized to 8 as 1 default=12
+#define SHARP_DEJ_CTRL ((0x5064 << 2) + 0xff000000)
+//Bit 31:4 reserved
+//Bit 15:8, reg_sr3_dejaggy_hblank // u8
+//Bit 7:4 reserved
+//Bit 3:2, reg_sr3_dejaggy_sameside_prtct // u2: enable of sr3 dejaggy same side curve protect from filter, [0] for proc, [1] for ctrl path, default=3
+//Bit 1, reg_sr3_dejaggy_sameside_mode // u1: mode of the sameside flag decision: default =1
+//Bit 0, reg_sr3_dejaggy_enable // u1: enable of sr3 dejaggy: default =0
+#define SHARP_DEJ_ALPHA ((0x5065 << 2) + 0xff000000)
+//Bit 31:28, reg_sr3_dejaggy_ctrlchrm_alpha_1 //u4: alpha for LR video LPF, default = 0
+//Bit 27:24, reg_sr3_dejaggy_ctrlchrm_alpha_0 //u4: alpha for LR video LPF, default = 15
+//Bit 23:20, reg_sr3_dejaggy_ctrlluma_alpha_1 //u4: alpha for LR video LPF, default = 0
+//Bit 19:16, reg_sr3_dejaggy_ctrlluma_alpha_0 //u4: alpha for LR video LPF, default = 15
+//Bit 15:12, reg_sr3_dejaggy_procchrm_alpha_1 //u4: alpha for LR video LPF, default = 4
+//Bit 11:8, reg_sr3_dejaggy_procchrm_alpha_0 //u4: alpha for LR video LPF, default = 6
+//Bit 7:4, reg_sr3_dejaggy_procluma_alpha_1 //u4: alpha for LR video LPF, default = 4
+//Bit 3:0, reg_sr3_dejaggy_procluma_alpha_0 //u4: alpha for LR video LPF, default = 6
+#define SHARP_SR3_DRTLPF_EN ((0x5066 << 2) + 0xff000000)
+//Bit 31:15 reserved
+//Bit 14:8, reg_pk_debug_edge . unsigned , default = 0
+//Bit 7, reserved
+//Bit 6:4, reg_sr3_drtlpf_theta_en //u1x3 theta (pure vertical and horizontal HF burst protection) enable. 0: not enable, 1:enable protection
+//Bit 3, reserved
+//Bit 2:0 reg_sr3_drtlpf_enable //u1x3 directional lpf on luma U and V channels, default = 7
+#define SHARP_SR3_DRTLPF_ALPHA_0 ((0x5067 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_sr3_drtlpf_alpha3 //u6: directional lpf alpha coef for min_sad/max_sad comparied, default = 9
+//Bit 23:22 reserved
+//Bit 21:16 reg_sr3_drtlpf_alpha2 //u6: default =10
+//Bit 15:14 reserved
+//Bit 13:8 reg_sr3_drtlpf_alpha1 //u6: default = 11
+//Bit 7:6 reserved
+//Bit 5:0 reg_sr3_drtlpf_alpha0 //u6: default = 12
+#define SHARP_SR3_DRTLPF_ALPHA_1 ((0x5068 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_sr3_drtlpf_alpha7 //u6: directional lpf alpha coef for min_sad/max_sad comparied, default = 1
+//Bit 23:22 reserved
+//Bit 21:16 reg_sr3_drtlpf_alpha6 //u6: default = 4
+//Bit 15:14 reserved
+//Bit 13:8 reg_sr3_drtlpf_alpha5 //u6: default = 7
+//Bit 7:6 reserved
+//Bit 5:0 reg_sr3_drtlpf_alpha4 //u6: default = 8
+#define SHARP_SR3_DRTLPF_ALPHA_2 ((0x5069 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_sr3_drtlpf_alpha11 //u6: directional lpf alpha coef for min_sad/max_sad comparied, default = 0
+//Bit 23:22 reserved
+//Bit 21:16 reg_sr3_drtlpf_alpha10 //u6: default = 0
+//Bit 15:14 reserved
+//Bit 13:8 reg_sr3_drtlpf_alpha9 //u6: default = 0
+//Bit 7:6 reserved
+//Bit 5:0 reg_sr3_drtlpf_alpha8 //u6: default = 0
+#define SHARP_SR3_DRTLPF_ALPHA_OFST ((0x506a << 2) + 0xff000000)
+//Bit 31:28 reg_sr3_drtlpf_alpha_ofst7 //s4: directional lpf alpha coef ofset of each directions, default = -8
+//Bit 27:24 reg_sr3_drtlpf_alpha_ofst6 //s4: default = -8
+//Bit 23:20 reg_sr3_drtlpf_alpha_ofst5 //s4: default = -8
+//Bit 19:16 reg_sr3_drtlpf_alpha_ofst4 //s4: default = -8
+//Bit 15:12 reg_sr3_drtlpf_alpha_ofst3 //s4: default = -8
+//Bit 11:8 reg_sr3_drtlpf_alpha_ofst2 //s4: default = -8
+//Bit 7:4 reg_sr3_drtlpf_alpha_ofst1 //s4: default = -8
+//Bit 3:0 reg_sr3_drtlpf_alpha_ofst0 //s4: default = -8
+#define SHARP_SR3_DERING_CTRL ((0x506b << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_sr3_dering_enable // u3: dering enable bits; default = 1
+//Bit 27 reserved
+//Bit 26:24 reg_sr3_dering_varlpf_mode // u3: local variant LPF mode: 0 no filter, 1, errosion 3x3; 2: 3x3 lpf; 3 and up: 3x3 errosion + lpf default = 3
+//Bit 23:20 reg_sr3_dering_maxrange // u4: maximum:range of dering in LR resolution, max to 12; default = 9
+//Bit 19:18 reserved
+//Bit 17:16 reg_sr3_dering_lcvar_blend_mode // u2: mode for lcvar calculation: 0: HVblend; 1: diagblend; 2: HVblend+V (for hring); 3: HVblend+ DiagBlend default = 2
+//Bit 15:8 reg_sr3_dering_lcvar_gain // u8: gain to local variant and normalized to 32 as "1" default = 64
+//Bit 7:0 reg_sr3_dering_lcvar_nearby_maxsad_th // u8: threshold to use nearer side maxsad if that side sad is larger than this threshold, ortherwise, use the max one default = 28
+#define SHARP_SR3_DERING_LUMA2PKGAIN_0TO3 ((0x506c << 2) + 0xff000000)
+//Bit 31:24 reg_sr3_dering_luma2pkgain3 // u8: level limit(for th0<bpcon<th1) of curve for dering pkgain based on LPF luma level. default=255
+//Bit 23:16 reg_sr3_dering_luma2pkgain2 // u8: level limit(for bpcon<th0) of curve for dering pkgain based on LPF luma level. default=255
+//Bit 15:8 reg_sr3_dering_luma2pkgain1 // u8: threshold1 of curve for dering pkgain based on LPF luma level default =200
+//Bit 7:0 reg_sr3_dering_luma2pkgain0 // u8: threshold0 of curve for dering pkgain based on LPF luma level. default =30
+#define SHARP_SR3_DERING_LUMA2PKGAIN_4TO6 ((0x506d << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_sr3_dering_luma2pkgain6 // u8: rate1 (for bpcon>th1) of curve for dering pkgain based on LPF luma level. default =24
+//Bit 15:8 reg_sr3_dering_luma2pkgain5 // u8: rate0 (for bpcon<th0) of curve for dering pkgain based on LPF luma level. dfault =50
+//Bit 7:0 reg_sr3_dering_luma2pkgain4 // u8: level limit(for bpcon>th1) of curve for dering pkgain based on LPF luma level. default =255
+#define SHARP_SR3_DERING_LUMA2PKOS_0TO3 ((0x506e << 2) + 0xff000000)
+//Bit 31:24 reg_sr3_dering_luma2pkos3 // u8: level limit(for th0<bpcon<th1) of curve for dering pkOS based on LPF luma level. default=255
+//Bit 23:16 reg_sr3_dering_luma2pkos2 // u8: level limit(for bpcon<th0) of curve for dering pkOS based on LPF luma level. default=255
+//Bit 15:8 reg_sr3_dering_luma2pkos1 // u8: threshold1 of curve for dering pkOS based on LPF luma level default =200
+//Bit 7:0 reg_sr3_dering_luma2pkos0 // u8: threshold0 of curve for dering pkOS based on LPF luma leve. default =30
+#define SHARP_SR3_DERING_LUMA2PKOS_4TO6 ((0x506f << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_sr3_dering_luma2pkos6 // u8: rate1 (for bpcon>th1) of curve for dering pkOS based on LPF luma level. default =24
+//Bit 15:8 reg_sr3_dering_luma2pkos5 // u8: rate0 (for bpcon<th0) of curve for dering pkOS based on LPF luma level. dfault =50
+//Bit 7:0 reg_sr3_dering_luma2pkos4 // u8: level limit(for bpcon>th1) of curve for dering pkOS based on LPF luma level. default =255
+#define SHARP_SR3_DERING_GAINVS_MADSAD ((0x5070 << 2) + 0xff000000)
+//Bit 31:28 reg_sr3_dering_gainvs_maxsad7 //u4: pkgain vs maxsad value, 8 node interpolations, default = 0
+//Bit 27:24 reg_sr3_dering_gainvs_maxsad6 //u4: default = 0
+//Bit 23:20 reg_sr3_dering_gainvs_maxsad5 //u4: default = 0
+//Bit 19:16 reg_sr3_dering_gainvs_maxsad4 //u4: default = 0
+//Bit 15:12 reg_sr3_dering_gainvs_maxsad3 //u4: default = 0
+//Bit 11:8 reg_sr3_dering_gainvs_maxsad2 //u4: default = 0
+//Bit 7:4 reg_sr3_dering_gainvs_maxsad1 //u4: default = 4
+//Bit 3:0 reg_sr3_dering_gainvs_maxsad0 //u4: default = 8
+#define SHARP_SR3_DERING_GAINVS_VR2MAX ((0x5071 << 2) + 0xff000000)
+//Bit 31:28 reg_sr3_dering_gainvs_vr2max7 //u4: pkgain vs ratio = max(local_var, floor)/maxsad nearby, default = 15
+//Bit 27:24 reg_sr3_dering_gainvs_vr2max6 //u4: default = 15
+//Bit 23:20 reg_sr3_dering_gainvs_vr2max5 //u4: default = 15
+//Bit 19:16 reg_sr3_dering_gainvs_vr2max4 //u4: default = 15
+//Bit 15:12 reg_sr3_dering_gainvs_vr2max3 //u4: default = 14
+//Bit 11:8 reg_sr3_dering_gainvs_vr2max2 //u4: default = 12
+//Bit 7:4 reg_sr3_dering_gainvs_vr2max1 //u4: default = 2
+//Bit 3:0 reg_sr3_dering_gainvs_vr2max0 //u4: default = 0
+#define SHARP_SR3_DERING_PARAM0 ((0x5072 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_sr3_dering_lcvar_floor //u8: local varianet no smaller than this value to calculate dgain max(localvar,x)/maxsad. default = 10
+//Bit 15:8 reg_sr3_dering_vr2max_gain //u8: gain to max(local_var, floor)/maxsad before feeding to LUT. default = 32
+//Bit 7:6 reserved
+//Bit 5:0 reg_sr3_dering_vr2max_limt //u6: limit of maxsad to max(local_var, floor)*(max(maxsad, lmit))/maxsad. default = 16
+#define SHARP_SR3_DRTLPF_THETA ((0x5073 << 2) + 0xff000000)
+//Bit 31:0 reg_sr3_drtlpf_theta //u4x8: directional lpf beta coef for min_sad/min2_sad compared to x=0:7 correspond to[1:8]/16; 0 means no drtLPF, 15: 100% alpha dependant drtLPF
+#define SHARP_SATPRT_CTRL ((0x5074 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 reg_satprt_sat_core //u8: 4x will be coring to cor(irgb_max-irgb_min) to calculate the oy_delt, the smaller the more protection to color, the larger only the rich color will be protected;
+//Bit 15:8 reg_satprt_sat_rate //u8: rate to cor(irgb_max-irgb_min) to calculate the oy_delt, the larger the more protection to rich color; norm 16 as 1
+//Bit 7:4 reserved
+//Bit 3:2 reg_satprt_csc_mode //u2: csc mode of current yuv input: 0:601, 1:709, 2:BT2020 NCL, 3:reserved
+//Bit 1 reg_satprt_is_lmt //u1: flag telling the YUV is limited range data or full range data, 0 full range, 1: limited range
+//Bit 0 reg_satprt_enable //u1: enable of saturation protection for dnlp adjustments
+#define SHARP_SATPRT_DIVM ((0x5075 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:0 reg_satprt_div_m //u8x3, 1/m, normalized to 128 as 1, default=1
+#define SHARP_DB_FLT_CTRL ((0x5077 << 2) + 0xff000000)
+//Bit 31:27 reserved
+//Bit 26 reg_nrdeband_reset1
+//Bit 25 reg_nrdeband_reset0
+//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 0:yuv 1:RGB
+//Bit 23 reg_nrdeband_en11 // unsigned , default = 1 debanding registers of side lines, [0] for luma, same for below
+//Bit 22 reg_nrdeband_en10 // unsigned , default = 1 debanding registers of side lines, [1] for chroma, same for below
+//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
+//Bit 16 reserved
+//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
+//Bit 12 reserved
+//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6
+//Bit 8 reserved
+//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 debanding random hp portion xor, [0] for luma
+//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 debanding random hp portion xor, [1] for chroma
+//Bit 5 reg_nrdeband_en1 // unsigned , default = 1 debanding registers, for luma
+//Bit 4 reg_nrdeband_en0 // unsigned , default = 1 debanding registers, for chroma
+//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+#define SHARP_DB_FLT_RANDLUT ((0x5079 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:21 reg_nrdebandslut7 // unsigned , default = 1 lut0
+//Bit 20:18 reg_nrdebandslut6 // unsigned , default = 1 lut0
+//Bit 17:15 reg_nrdebandslut5 // unsigned , default = 1 lut0
+//Bit 14:12 reg_nrdebandslut4 // unsigned , default = 1 lut0
+//Bit 11: 9 reg_nrdebandslut3 // unsigned , default = 1 lut0
+//Bit 8: 6 reg_nrdebandslut2 // unsigned , default = 1 lut0
+//Bit 5: 3 reg_nrdebandslut1 // unsigned , default = 1 lut0
+//Bit 2: 0 reg_nrdebandslut0 // unsigned , default = 1 lut0
+#define SHARP_DB_FLT_PXI_THRD ((0x507a << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 to luma/|u/v| for using the denoise
+//Bit 15:10 reserved
+//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 to luma/|u/v| for using the denoise
+#define SHARP_DB_FLT_SEED_Y ((0x507b << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 noise adding seed for Y. seed[0]= 0x60a52f20; as default
+#define SHARP_DB_FLT_SEED_U ((0x507c << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 noise adding seed for U. seed[0]= 0x60a52f27; as default
+#define SHARP_DB_FLT_SEED_V ((0x507d << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define SHARP_PKGAIN_VSLUMA_LUT_L ((0x507e << 2) + 0xff000000)
+//Bit 31:28 reg_pkgain_vsluma_lut7;
+//Bit 27:24 reg_pkgain_vsluma_lut6;
+//Bit 23:20 reg_pkgain_vsluma_lut5;
+//Bit 19:16 reg_pkgain_vsluma_lut4;
+//Bit 15:12 reg_pkgain_vsluma_lut3;
+//Bit 11: 8 reg_pkgain_vsluma_lut2;
+//Bit 7: 4 reg_pkgain_vsluma_lut1;
+//Bit 3: 0 reg_pkgain_vsluma_lut0;
+#define SHARP_PKGAIN_VSLUMA_LUT_H ((0x507f << 2) + 0xff000000)
+//Bit 31: 4 reserved;
+//Bit 3: 0 reg_pkgain_vsluma_lut8;
+#define SHARP_PKOSHT_VSLUMA_LUT_L ((0x5080 << 2) + 0xff000000)
+//Bit 31:28 reg_pkosht_vsluma_lut7;
+//Bit 27:24 reg_pkosht_vsluma_lut6;
+//Bit 23:20 reg_pkosht_vsluma_lut5;
+//Bit 19:16 reg_pkosht_vsluma_lut4;
+//Bit 15:12 reg_pkosht_vsluma_lut3;
+//Bit 11: 8 reg_pkosht_vsluma_lut2;
+//Bit 7: 4 reg_pkosht_vsluma_lut1;
+//Bit 3: 0 reg_pkosht_vsluma_lut0;
+#define SHARP_PKOSHT_VSLUMA_LUT_H ((0x5081 << 2) + 0xff000000)
+//Bit 31: 4 reserved;
+//Bit 3: 0 reg_pkosht_vsluma_lut8;
+#define SHARP_SATPRT_LMT_RGB1 ((0x5082 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 reg_satprt_lmt_g //u12x3, limit of the rgb channel, for limited range RGB, set to 960, otherwise set to 1023
+//Bit 15:12 reserved
+//Bit 11:0 reg_satprt_lmt_r //u12x3, limit of the rgb channel, for limited range RGB, set to 960, otherwise set to 1023
+#define SHARP_SATPRT_LMT_RGB2 ((0x5083 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11:0 reg_satprt_lmt_b //u12x3, limit of the rgb channel, for limited range RGB, set to 960, otherwise set to 1023
+#define SHARP_GATE_CLK_CTRL_0 ((0x5084 << 2) + 0xff000000)
+//Bit 31: 0 reg_gate_clk_ctrl_0
+#define SHARP_GATE_CLK_CTRL_1 ((0x5085 << 2) + 0xff000000)
+//Bit 31: 0 reg_gate_clk_ctrl_1
+#define SHARP_GATE_CLK_CTRL_2 ((0x5086 << 2) + 0xff000000)
+//Bit 31: 0 reg_gate_clk_ctrl_2
+#define SHARP_GATE_CLK_CTRL_3 ((0x5087 << 2) + 0xff000000)
+//Bit 31: 0 reg_gate_clk_ctrl_3
+#define SHARP_DPS_CTRL ((0x5088 << 2) + 0xff000000)
+//Bit 31: 0 reg_sharp_dps_ctrl
+#define DNLP_00 ((0x5090 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid0 : dnlp00 . unsigned , default = 32'h00008060
+#define DNLP_01 ((0x5091 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid1 : dnlp01 . unsigned , default = 32'h100e0c0a
+#define DNLP_02 ((0x5092 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid2 : dnlp02 . unsigned , default = 32'h1a171412
+#define DNLP_03 ((0x5093 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid3 : dnlp03 . unsigned , default = 32'h2824201d
+#define DNLP_04 ((0x5094 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid4 : dnlp04 . unsigned , default = 32'h3834302c
+#define DNLP_05 ((0x5095 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid5 : dnlp05 . unsigned , default = 32'h4b45403c
+#define DNLP_06 ((0x5096 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid6 : dnlp06 . unsigned , default = 32'h605b5550
+#define DNLP_07 ((0x5097 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid7 : dnlp07 . unsigned , default = 32'h80787068
+#define DNLP_08 ((0x5098 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid8 : dnlp08 . unsigned , default = 32'ha0989088
+#define DNLP_09 ((0x5099 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid9 : dnlp09 . unsigned , default = 32'hb8b2aca6
+#define DNLP_10 ((0x509a << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid10 : dnlp10 . unsigned , default = 32'hc8c4c0bc
+#define DNLP_11 ((0x509b << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid11 : dnlp11 . unsigned , default = 32'hd4d2cecb
+#define DNLP_12 ((0x509c << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid12 : dnlp12 . unsigned , default = 32'hdad8d7d6
+#define DNLP_13 ((0x509d << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid13 : dnlp13 . unsigned , default = 32'he2e0dedc
+#define DNLP_14 ((0x509e << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid14 : dnlp14 . unsigned , default = 32'hf0ece8e4
+#define DNLP_15 ((0x509f << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid15 : dnlp15 . unsigned , default = 32'hfffcf8f4
+#define DNLP_16 ((0x50a0 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid16 : dnlp16 . unsigned , default = 32'h08060402
+#define DNLP_17 ((0x50a1 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid17 : dnlp17 . unsigned , default = 32'h100e0c0a
+#define DNLP_18 ((0x50a2 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid18 : dnlp18 . unsigned , default = 32'h1a171412
+#define DNLP_19 ((0x50a3 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid19 : dnlp19 . unsigned , default = 32'h2824201d
+#define DNLP_20 ((0x50a4 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid20 : dnlp20 . unsigned , default = 32'h3834302c
+#define DNLP_21 ((0x50a5 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid21 : dnlp21 . unsigned , default = 32'h4b45403c
+#define DNLP_22 ((0x50a6 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid22 : dnlp22 . unsigned , default = 32'h605b5550
+#define DNLP_23 ((0x50a7 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid23 : dnlp23 . unsigned , default = 32'h80787068
+#define DNLP_24 ((0x50a8 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid24 : dnlp24 . unsigned , default = 32'ha0989088
+#define DNLP_25 ((0x50a9 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid25 : dnlp25 . unsigned , default = 32'hb8b2aca6
+#define DNLP_26 ((0x50aa << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid26 : dnlp26 . unsigned , default = 32'hc8c4c0bc
+#define DNLP_27 ((0x50ab << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid27 : dnlp27 . unsigned , default = 32'hd4d2cecb
+#define DNLP_28 ((0x50ac << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid28 : dnlp28 . unsigned , default = 32'hdad8d7d6
+#define DNLP_29 ((0x50ad << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid29 : dnlp29 . unsigned , default = 32'he2e0dedc
+#define DNLP_30 ((0x50ae << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid30 : dnlp30 . unsigned , default = 32'hf0ece8e4
+#define DNLP_31 ((0x50af << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid31 : dnlp31 . unsigned , default = 32'hfffcf8f4
+#define SHARP_SYNC_CTRL ((0x50b0 << 2) + 0xff000000)
+//Bit 15: 0, reg_sync_ctrl //reg_sync_ctrl: shaddow register control . unsigned , default = 0
+#define LC_INPUT_MUX ((0x50b1 << 2) + 0xff000000)
+//Bit 31:7 reserved
+//Bit 6:4 reg_lcinput_ysel //u3, local contrast luma input options 0: org_y; 1: gau_y; 2: gauadp_y; 3: edgadplpf_y; 4: nr_y;5: lti_y; 6: pk_y (before os);7: pk_y (after os) . unsigned , default = 5
+//Bit 3 reserved
+//Bit 2:0 reg_lcinput_csel //u3, local contrast chroma input options 0: org_c; 1: gau_c; 2: gauadp_c; 3: edgadplpf_c; 4: nr_c;5: cti_c; 6: pk_c . unsigned , default = 5
+#define NR_GAU_YH_COEF02 ((0x50b2 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:20 reg_nr_gau_yhcoef_0 //s10, luma's horizontal adaptive coef0 . signed , default = 32
+//Bit 19:10 reg_nr_gau_yhcoef_1 //s10, luma's horizontal adaptive coef1 . signed , default = 32
+//Bit 9: 0 reg_nr_gau_yhcoef_2 //s10, luma's horizontal adaptive coef2 . signed , default = 16
+#define NR_GAU_YH_COEF34 ((0x50b3 << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:10 reg_nr_gau_yhcoef_3 //s10, luma's horizontal adaptive coef3 . signed , default = 0
+//Bit 9: 0 reg_nr_gau_yhcoef_4 //s10, luma's horizontal adaptive coef4 . signed , default = 0
+#define NR_GAU_YV_COEF1 ((0x50b4 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:20 reg_nr_gau_yvcoef_0 //s10, luma's vertical adaptive coef0 . signed , default = 32
+//Bit 19:10 reg_nr_gau_yvcoef_1 //s10, luma's vertical adaptive coef1 . signed , default = 32
+//Bit 9: 0 reg_nr_gau_yvcoef_2 //s10, luma's vertical adaptive coef2 . signed , default = 16
+#define NR_GAU_CH_COEF02 ((0x50b5 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:20 reg_nr_gau_chcoef_0 //s10, chroma's horizontal adaptive coef0 . signed , default = 32
+//Bit 19:10 reg_nr_gau_chcoef_1 //s10, chroma's horizontal adaptive coef1 . signed , default = 32
+//Bit 9: 0 reg_nr_gau_chcoef_2 //s10, chroma's horizontal adaptive coef2 . signed , default = 16
+#define NR_GAU_CH_COEF34 ((0x50b6 << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:10 reg_nr_gau_chcoef_3 //s10, chroma's horizontal adaptive coef3 . signed , default = 0
+//Bit 9: 0 reg_nr_gau_chcoef_4 //s10, chroma's horizontal adaptive coef4 . signed , default = 0
+#define NR_GAU_CV_COEF1 ((0x50b7 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:20 reg_nr_gau_cvcoef_0 //s10, chroma's vertical adaptive coef0 . signed , default = 32
+//Bit 19:10 reg_nr_gau_cvcoef_1 //s10, chroma's vertical adaptive coef1 . signed , default = 32
+//Bit 9: 0 reg_nr_gau_cvcoef_2 //s10, chroma's vertical adaptive coef2 . signed , default = 16
+#define SHARP_DB_FLT_CTRL1 ((0x50b8 << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:16 reg_nrdeband_noise_rs // unsigned , default = 2
+//Bit 15:12 reg_nrdeband_randgain // unsigned , default = 8
+//Bit 11 reserved
+//Bit 10: 8 reserved
+//Bit 7 reserved
+//Bit 6: 4 reserved
+//Bit 3 reserved
+//Bit 2: 0 reserved
+#define SHARP_DB_FLT_LUMA_THRD ((0x50b9 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_luma_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_luma_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_luma_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_luma_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else
+#define SHARP_DB_FLT_CHRM_THRD ((0x50ba << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_chrm_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_chrm_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_chrm_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_chrm_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif
+#define LC_TOP_CTRL ((0x50c0 << 2) + 0xff000000)
+ //Bit 31 :8 reg_lc_misc U RW default = 'h0
+ //Bit 7 :5 reserved U RW default = 'h0 None
+ //Bit 4 reg_lc_enable U RW default = 'h1 enable signal for local contrast enhancement, 1-enable; 0 disable
+ //Bit 3 :1 reserved U RW default = 'h0 None
+ //Bit 0 reg_lc_blkblend_mode U RW default = 'h1 use bilinear interpolation between blocks, 0: no interpolation 1: blender enabled
+#define LC_HV_NUM ((0x50c1 << 2) + 0xff000000)
+ //Bit 31 :13 reserved U RW default = 'h0 None
+ //Bit 12 :8 reg_lc_blk_hnum U RW default = 'hc lc processing region number of V, maximum to (STA_LEN_V-1) (0~8)
+ //Bit 7 :5 reserved U RW default = 'h0 None
+ //Bit 4 :0 reg_lc_blk_vnum U RW default = 'h8 lc processing region number of H, maximum to (STA_LEN_H-1) (0~12)
+#define LC_SAT_LUT_0_1 ((0x50c2 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_0 U RW default = 'hc saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_1 U RW default = 'h20 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_2_3 ((0x50c3 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_2 U RW default = 'h38 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_3 U RW default = 'h54 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_4_5 ((0x50c4 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_4 U RW default = 'h73 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_5 U RW default = 'h95 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_6_7 ((0x50c5 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_6 U RW default = 'hb9 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_7 U RW default = 'hdf saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_8_9 ((0x50c6 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_8 U RW default = 'h107 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_9 U RW default = 'h131 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_10_11 ((0x50c7 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_10 U RW default = 'h15c saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_11 U RW default = 'h189 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_12_13 ((0x50c8 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_12 U RW default = 'h1b8 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_13 U RW default = 'h1e8 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_14_15 ((0x50c9 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_14 U RW default = 'h219 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_15 U RW default = 'h24c saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_16_17 ((0x50ca << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_16 U RW default = 'h280 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_17 U RW default = 'h2b6 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_18_19 ((0x50cb << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_18 U RW default = 'h2ec saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_19 U RW default = 'h324 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_20_21 ((0x50cc << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_20 U RW default = 'h35d saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_21 U RW default = 'h397 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_22_23 ((0x50cd << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_22 U RW default = 'h3d2 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_23 U RW default = 'h40e saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_24_25 ((0x50ce << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_24 U RW default = 'h44b saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_25 U RW default = 'h489 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_26_27 ((0x50cf << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_26 U RW default = 'h4c8 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_27 U RW default = 'h507 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_28_29 ((0x50d0 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_28 U RW default = 'h548 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_29 U RW default = 'h58a saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_30_31 ((0x50d1 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_30 U RW default = 'h5cd saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_31 U RW default = 'h610 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_32_33 ((0x50d2 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_32 U RW default = 'h654 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_33 U RW default = 'h69a saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_34_35 ((0x50d3 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_34 U RW default = 'h6e0 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_35 U RW default = 'h726 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_36_37 ((0x50d4 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_36 U RW default = 'h76e saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_37 U RW default = 'h7b6 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_38_39 ((0x50d5 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_38 U RW default = 'h7ff saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_39 U RW default = 'h849 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_40_41 ((0x50d6 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_40 U RW default = 'h894 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_41 U RW default = 'h8df saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_42_43 ((0x50d7 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_42 U RW default = 'h92b saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_43 U RW default = 'h978 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_44_45 ((0x50d8 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_44 U RW default = 'h9c6 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_45 U RW default = 'ha14 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_46_47 ((0x50d9 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_46 U RW default = 'ha63 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_47 U RW default = 'hab2 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_48_49 ((0x50da << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_48 U RW default = 'hb02 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_49 U RW default = 'hb53 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_50_51 ((0x50db << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_50 U RW default = 'hba5 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_51 U RW default = 'hbf7 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_52_53 ((0x50dc << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_52 U RW default = 'hc4a saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_53 U RW default = 'hc9d saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_54_55 ((0x50dd << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_54 U RW default = 'hcf1 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_55 U RW default = 'hd46 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_56_57 ((0x50de << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_56 U RW default = 'hd9b saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_57 U RW default = 'hdf1 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_58_59 ((0x50df << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_58 U RW default = 'he47 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_59 U RW default = 'he9e saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_60_61 ((0x50e0 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_60 U RW default = 'hef6 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_61 U RW default = 'hf4e saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_62 ((0x50e1 << 2) + 0xff000000)
+ //Bit 31 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_62 U RW default = 'hfa7 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_CURVE_BLK_HIDX_0_1 ((0x50e2 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_hidx_0 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_1 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_HIDX_2_3 ((0x50e3 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_hidx_2 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_3 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_HIDX_4_5 ((0x50e4 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_hidx_4 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_5 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_HIDX_6_7 ((0x50e5 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_hidx_6 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_7 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_HIDX_8_9 ((0x50e6 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_hidx_8 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_9 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_HIDX_10_11 ((0x50e7 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_hidx_10 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_11 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_HIDX_12 ((0x50e8 << 2) + 0xff000000)
+ //Bit 31 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_12 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_VIDX_0_1 ((0x50e9 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_vidx_0 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_vidx_1 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_VIDX_2_3 ((0x50ea << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_vidx_2 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_vidx_3 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_VIDX_4_5 ((0x50eb << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_vidx_4 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_vidx_5 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_VIDX_6_7 ((0x50ec << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_vidx_6 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_vidx_7 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_VIDX_8 ((0x50ed << 2) + 0xff000000)
+ //Bit 31 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_vidx_8 U RW default = 'h0 block boundary x-index
+#define LC_YUV2RGB_MAT_0_1 ((0x50ee << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_yuv2rgb_mat3x3_0 S RW default = 1192 yuv2rgb 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_1 S RW default = 'h0 yuv2rgb 3x3 matrix
+#define LC_YUV2RGB_MAT_2_3 ((0x50ef << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_yuv2rgb_mat3x3_2 S RW default = 1836 yuv2rgb 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_3 S RW default = 1192 yuv2rgb 3x3 matrix
+#define LC_YUV2RGB_MAT_4_5 ((0x50f0 << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_yuv2rgb_mat3x3_4 S RW default = -218 yuv2rgb 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_5 S RW default = -547 yuv2rgb 3x3 matrix
+#define LC_YUV2RGB_MAT_6_7 ((0x50f1 << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_yuv2rgb_mat3x3_6 S RW default = 1192 yuv2rgb 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_7 S RW default = '2166 yuv2rgb 3x3 matrix
+#define LC_YUV2RGB_MAT_8 ((0x50f2 << 2) + 0xff000000)
+ //Bit 31 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_8 S RW default = 'h0 yuv2rgb 3x3 matrix
+#define LC_RGB2YUV_MAT_0_1 ((0x50f3 << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_rgb2yuv_mat3x3_0 S RW default = 187 rgb2yuv 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_1 S RW default = 629 rgb2yuv 3x3 matrix
+#define LC_RGB2YUV_MAT_2_3 ((0x50f4 << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_rgb2yuv_mat3x3_2 S RW default = 63 rgb2yuv 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_3 S RW default = -103 rgb2yuv 3x3 matrix
+#define LC_RGB2YUV_MAT_4_5 ((0x50f5 << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_rgb2yuv_mat3x3_4 S RW default = -346 rgb2yuv 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_5 S RW default = 450 rgb2yuv 3x3 matrix
+#define LC_RGB2YUV_MAT_6_7 ((0x50f6 << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_rgb2yuv_mat3x3_6 S RW default = 450 rgb2yuv 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_7 S RW default = -409 rgb2yuv 3x3 matrix
+#define LC_RGB2YUV_MAT_8 ((0x50f7 << 2) + 0xff000000)
+ //Bit 31 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_8 S RW default = 41 rgb2yuv 3x3 matrix
+#define LC_YUV2RGB_OFST ((0x50f8 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_yuv2rgb_ofset_0 U RW default = 'h40 yuv2rgb pre-offset to yuv,
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_yuv2rgb_ofset_1 U RW default = 'h200 yuv2rgb pre-offset to yuv,
+#define LC_YUV2RGB_CLIP ((0x50f9 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :28 reg_lc_yuv2rgb_rs U RW default = 'h0 matrix normalization right shift extra bits, norm= (1<<(8+rs))
+ //Bit 27 :16 reg_lc_yuv2rgb_clip_0 U RW default = 'h0 yuv2rgb converted RGB clipping range
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_yuv2rgb_clip_1 U RW default = 'h3ff yuv2rgb converted RGB clipping range
+#define LC_RGB2YUV_OFST ((0x50fa << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_rgb2yuv_ofset_0 U RW default = 'h40 rgb2yuv post-offset to yuv,
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_rgb2yuv_ofset_1 U RW default = 'h200 rgb2yuv post-offset to yuv,
+#define LC_RGB2YUV_CLIP ((0x50fb << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :28 reg_lc_rgb2yuv_rs U RW default = 'h0 matrix normalization right shift extra bits, norm= (1<<(10+rs))
+ //Bit 27 :16 reg_lc_rgb2yuv_clip_0 U RW default = 'h0 rgb2yuv converted YUV clipping range
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_rgb2yuv_clip_1 U RW default = 'h3ff rgb2yuv converted YUV clipping range
+#define LC_MAP_RAM_CTRL ((0x50fc << 2) + 0xff000000)
+#define LC_MAP_RAM_ADDR ((0x50fd << 2) + 0xff000000)
+#define LC_MAP_RAM_DATA ((0x50fe << 2) + 0xff000000)
+#define SHARP_FMETER_CTRL ((0x5089 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11:10 reg_fmeter_vwin_mm //u2, vertical window size, 0:1 cloumn, 1:3cloumn, 2or3: 5cloumn .unsigned , default = 0
+//Bit 9 : 8 reg_fmeter_hwin_mm //u2, horizontal window size, 0:1x7, 1:1x9, 2or3: 1x11 .unsigned , default = 0
+//Bit 7 reg_fmeter_d2_mode //u1, selectino filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 6 reg_fmeter_v2_mode //u1, selectino filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 5: 4 reg_fmeter_h2_mode //u2, selection filter H2, 0: [0 0 0 -2 0 0 2 0 0], 1: [-2 0 0 0 2], 2or3: [0-2 0 0 0 0 0 2 0] .unsigned , default = 0
+//Bit 3: 1 reserved
+//Bit 0 reg_freq_meter_en //u1, freq meter enable .unsigned , default = 0
+#define SHARP_FMETER_WIN_HOR ((0x508a << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_fmeter_xwin_ed //u13, window location: hend .unsigned , default = 1920
+//Bit 15:13 reserved
+//Bit 12: 0 reg_fmeter_xwin_st //u13, window location: hstart .unsigned , default = 0
+#define SHARP_FMETER_WIN_VER ((0x508b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_fmeter_ywin_ed //u14, window location: vend .unsigned , default = 1080
+//Bit 15:13 reserved
+//Bit 12: 0 reg_fmeter_ywin_st //u14, window location: vstart .unsigned , default = 0
+#define SHARP_FMETER_CORING ((0x508c << 2) + 0xff000000)
+//Bit 31:24 reg_fmeter_low_bound //u8, low bound for threshold .unsigned , default = 4
+//Bit 23:16 reg_fmeter_coring_d //u8, coring of diff before compare with threhold for diagonal frequency .unsigned , default = 4
+//Bit 15:8 reg_fmeter_coring_v //u8, coring of diff before compare with threhold for vertical frequency .unsigned , default = 4
+//Bit 7: 0 reg_fmeter_coring_h //u8, coring of diff before compare with threhold for horizontal frequency .unsigned , default = 4
+#define SHARP_FMETER_RATIO_H ((0x508d << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:16 reg_fmeter_ratio_h2 //u6, ratio for threshold calc. for horizontal frequency, 16 is normalized as "1" .unsigned , default = 16
+//Bit 15:14 reserved
+//Bit 13: 8 reg_fmeter_ratio_h1 //u6, ratio for threshold calc. for horizontal frequency, 16 is normalized as "1" .unsigned , default = 16
+//Bit 7 : 6 reserved
+//Bit 5 : 0 reg_fmeter_ratio_h0 //u6, ratio for threshold calc. for horizontal frequency, 16 is normalized as "1" .unsigned , default = 16
+#define SHARP_FMETER_RATIO_V ((0x508e << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:16 reg_fmeter_ratio_v2 //u6, ratio for threshold calc. for vertical frequency, 16 is normalized as "1" .unsigned , default = 16
+//Bit 15:14 reserved
+//Bit 13: 8 reg_fmeter_ratio_v1 //u6, ratio for threshold calc. for vertical frequency, 16 is normalized as "1" .unsigned , default = 16
+//Bit 7 : 6 reserved
+//Bit 5 : 0 reg_fmeter_ratio_v0 //u6, ratio for threshold calc. for vertical frequency, 16 is normalized as "1" .unsigned , default = 16
+#define SHARP_FMETER_RATIO_D ((0x508f << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:16 reg_fmeter_ratio_d2 //u6, ratio for threshold calc. for diagonal frequency, 16 is normalized as "1" .unsigned , default = 16
+//Bit 15:14 reserved
+//Bit 13: 8 reg_fmeter_ratio_d1 //u6, ratio for threshold calc. for diagonal frequency, 16 is normalized as "1" .unsigned , default = 16
+//Bit 7 : 6 reserved
+//Bit 5 : 0 reg_fmeter_ratio_d0 //u6, ratio for threshold calc. for diagonal frequency, 16 is normalized as "1" .unsigned , default = 16
+#define SHARP_RO_FMETER_HCNT_TYPE0 ((0x5046 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_hcnt_type0 //u32, count for horizontal frequency
+#define SHARP_RO_FMETER_HCNT_TYPE1 ((0x5047 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_hcnt_type1 //u32, count for horizontal frequency
+#define SHARP_RO_FMETER_HCNT_TYPE2 ((0x5048 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_hcnt_type2 //u32, count for horizontal frequency
+#define SHARP_RO_FMETER_HCNT_TYPE3 ((0x5049 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_hcnt_type3 //u32, count for horizontal frequency
+#define SHARP_RO_FMETER_VCNT_TYPE0 ((0x504a << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_vcnt_type0 //u32, count for vertical frequency
+#define SHARP_RO_FMETER_VCNT_TYPE1 ((0x504b << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_vcnt_type1 //u32, count for vertical frequency
+#define SHARP_RO_FMETER_VCNT_TYPE2 ((0x504c << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_vcnt_type2 //u32, count for vertical frequency
+#define SHARP_RO_FMETER_VCNT_TYPE3 ((0x504d << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_vcnt_type3 //u32, count for vertical frequency
+#define SHARP_RO_FMETER_PDCNT_TYPE0 ((0x504e << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_pdcnt_type0 //u32, count for positive diagonal frequency
+#define SHARP_RO_FMETER_PDCNT_TYPE1 ((0x504f << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_pdcnt_type1 //u32, count for positive diagonal frequency
+#define SHARP_RO_FMETER_PDCNT_TYPE2 ((0x5050 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_pdcnt_type2 //u32, count for positive diagonal frequency
+#define SHARP_RO_FMETER_PDCNT_TYPE3 ((0x5051 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_pdcnt_type3 //u32, count for positive diagonal frequency
+#define SHARP_RO_FMETER_NDCNT_TYPE0 ((0x5052 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_ndcnt_type0 //u32, count for negitive diagonal frequency
+#define SHARP_RO_FMETER_NDCNT_TYPE1 ((0x5053 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_ndcnt_type1 //u32, count for negitive diagonal frequency
+#define SHARP_RO_FMETER_NDCNT_TYPE2 ((0x5054 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_ndcnt_type2 //u32, count for negitive diagonal frequency
+#define SHARP_RO_FMETER_NDCNT_TYPE3 ((0x5055 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_ndcnt_type3 //u32, count for negitive diagonal frequency
+//
+// Closing file: sharp_regs.h
+//
+
+#define SRSHARP0_SHARP_HVSIZE (SRSHARP0_OFFSET + SHARP_HVSIZE ) //0x00 //
+#define SRSHARP0_SHARP_HVBLANK_NUM (SRSHARP0_OFFSET + SHARP_HVBLANK_NUM ) //0x01 //
+#define SRSHARP0_NR_GAUSSIAN_MODE (SRSHARP0_OFFSET + NR_GAUSSIAN_MODE ) //0x02 //
+//`define SRSHARP0_PK_HVCON_LPF_MODE (`SRSHARP0_OFFSET + `PK_HVCON_LPF_MODE ) //8'h03 //
+//`define SRSHARP0_PK_CON_BLEND_GAIN (`SRSHARP0_OFFSET + `PK_CON_BLEND_GAIN ) //8'h04 //
+#define SRSHARP0_PK_CON_2CIRHPGAIN_TH_RATE (SRSHARP0_OFFSET + PK_CON_2CIRHPGAIN_TH_RATE ) //0x05 //
+#define SRSHARP0_PK_CON_2CIRHPGAIN_LIMIT (SRSHARP0_OFFSET + PK_CON_2CIRHPGAIN_LIMIT ) //0x06 //
+#define SRSHARP0_PK_CON_2CIRBPGAIN_TH_RATE (SRSHARP0_OFFSET + PK_CON_2CIRBPGAIN_TH_RATE ) //0x07 //
+#define SRSHARP0_PK_CON_2CIRBPGAIN_LIMIT (SRSHARP0_OFFSET + PK_CON_2CIRBPGAIN_LIMIT ) //0x08 //
+#define SRSHARP0_PK_CON_2DRTHPGAIN_TH_RATE (SRSHARP0_OFFSET + PK_CON_2DRTHPGAIN_TH_RATE ) //0x09 //
+#define SRSHARP0_PK_CON_2DRTHPGAIN_LIMIT (SRSHARP0_OFFSET + PK_CON_2DRTHPGAIN_LIMIT ) //0x0a //
+#define SRSHARP0_PK_CON_2DRTBPGAIN_TH_RATE (SRSHARP0_OFFSET + PK_CON_2DRTBPGAIN_TH_RATE ) //0x0b //
+#define SRSHARP0_PK_CON_2DRTBPGAIN_LIMIT (SRSHARP0_OFFSET + PK_CON_2DRTBPGAIN_LIMIT ) //0x0c //
+#define SRSHARP0_PK_CIRFB_LPF_MODE (SRSHARP0_OFFSET + PK_CIRFB_LPF_MODE ) //0x0d //
+#define SRSHARP0_PK_DRTFB_LPF_MODE (SRSHARP0_OFFSET + PK_DRTFB_LPF_MODE ) //0x0e //
+#define SRSHARP0_PK_CIRFB_HP_CORING (SRSHARP0_OFFSET + PK_CIRFB_HP_CORING ) //0x0f //
+#define SRSHARP0_PK_CIRFB_BP_CORING (SRSHARP0_OFFSET + PK_CIRFB_BP_CORING ) //0x10 //
+#define SRSHARP0_PK_DRTFB_HP_CORING (SRSHARP0_OFFSET + PK_DRTFB_HP_CORING ) //0x11 //
+#define SRSHARP0_PK_DRTFB_BP_CORING (SRSHARP0_OFFSET + PK_DRTFB_BP_CORING ) //0x12 //
+#define SRSHARP0_PK_CIRFB_BLEND_GAIN (SRSHARP0_OFFSET + PK_CIRFB_BLEND_GAIN ) //0x13 //
+#define SRSHARP0_NR_ALPY_SSD_GAIN_OFST (SRSHARP0_OFFSET + NR_ALPY_SSD_GAIN_OFST ) //0x14 //
+#define SRSHARP0_NR_ALP0Y_ERR2CURV_TH_RATE (SRSHARP0_OFFSET + NR_ALP0Y_ERR2CURV_TH_RATE ) //0x15 //
+#define SRSHARP0_NR_ALP0Y_ERR2CURV_LIMIT (SRSHARP0_OFFSET + NR_ALP0Y_ERR2CURV_LIMIT ) //0x16 //
+#define SRSHARP0_NR_ALP0C_ERR2CURV_TH_RATE (SRSHARP0_OFFSET + NR_ALP0C_ERR2CURV_TH_RATE ) //0x17 //
+#define SRSHARP0_NR_ALP0C_ERR2CURV_LIMIT (SRSHARP0_OFFSET + NR_ALP0C_ERR2CURV_LIMIT ) //0x18 //
+#define SRSHARP0_NR_ALP0_MIN_MAX (SRSHARP0_OFFSET + NR_ALP0_MIN_MAX ) //0x19 //
+#define SRSHARP0_NR_ALP1_MIERR_CORING (SRSHARP0_OFFSET + NR_ALP1_MIERR_CORING ) //0x1a //
+#define SRSHARP0_NR_ALP1_ERR2CURV_TH_RATE (SRSHARP0_OFFSET + NR_ALP1_ERR2CURV_TH_RATE ) //0x1b //
+#define SRSHARP0_NR_ALP1_ERR2CURV_LIMIT (SRSHARP0_OFFSET + NR_ALP1_ERR2CURV_LIMIT ) //0x1c //
+#define SRSHARP0_NR_ALP1_MIN_MAX (SRSHARP0_OFFSET + NR_ALP1_MIN_MAX ) //0x1d //
+#define SRSHARP0_PK_ALP2_MIERR_CORING (SRSHARP0_OFFSET + PK_ALP2_MIERR_CORING ) //0x1e //
+#define SRSHARP0_PK_ALP2_ERR2CURV_TH_RATE (SRSHARP0_OFFSET + PK_ALP2_ERR2CURV_TH_RATE ) //0x1f //
+#define SRSHARP0_PK_ALP2_ERR2CURV_LIMIT (SRSHARP0_OFFSET + PK_ALP2_ERR2CURV_LIMIT ) //0x20 //
+#define SRSHARP0_PK_ALP2_MIN_MAX (SRSHARP0_OFFSET + PK_ALP2_MIN_MAX ) //0x21 //
+#define SRSHARP0_PK_FINALGAIN_HP_BP (SRSHARP0_OFFSET + PK_FINALGAIN_HP_BP ) //0x22 //
+#define SRSHARP0_PK_OS_HORZ_CORE_GAIN (SRSHARP0_OFFSET + PK_OS_HORZ_CORE_GAIN ) //0x23 //
+#define SRSHARP0_PK_OS_VERT_CORE_GAIN (SRSHARP0_OFFSET + PK_OS_VERT_CORE_GAIN ) //0x24 //
+#define SRSHARP0_PK_OS_ADPT_MISC (SRSHARP0_OFFSET + PK_OS_ADPT_MISC ) //0x25 //
+#define SRSHARP0_PK_OS_STATIC (SRSHARP0_OFFSET + PK_OS_STATIC ) //0x26 //
+#define SRSHARP0_PK_NR_ENABLE (SRSHARP0_OFFSET + PK_NR_ENABLE ) //0x27 //
+#define SRSHARP0_PK_DRT_SAD_MISC (SRSHARP0_OFFSET + PK_DRT_SAD_MISC ) //0x28 //
+#define SRSHARP0_NR_TI_DNLP_BLEND (SRSHARP0_OFFSET + NR_TI_DNLP_BLEND ) //0x29 //
+#define SRSHARP0_LTI_DIR_CORE_ALPHA (SRSHARP0_OFFSET + LTI_DIR_CORE_ALPHA ) //0x2a //
+#define SRSHARP0_CTI_DIR_ALPHA (SRSHARP0_OFFSET + CTI_DIR_ALPHA ) //0x2b //
+#define SRSHARP0_LTI_CTI_DF_GAIN (SRSHARP0_OFFSET + LTI_CTI_DF_GAIN ) //0x2c //
+#define SRSHARP0_LTI_CTI_DIR_AC_DBG (SRSHARP0_OFFSET + LTI_CTI_DIR_AC_DBG ) //0x2d //
+#define SRSHARP0_HCTI_FLT_CLP_DC (SRSHARP0_OFFSET + HCTI_FLT_CLP_DC ) //0x2e //
+#define SRSHARP0_HCTI_BST_GAIN (SRSHARP0_OFFSET + HCTI_BST_GAIN ) //0x2f //
+#define SRSHARP0_HCTI_BST_CORE (SRSHARP0_OFFSET + HCTI_BST_CORE ) //0x30 //
+#define SRSHARP0_HCTI_CON_2_GAIN_0 (SRSHARP0_OFFSET + HCTI_CON_2_GAIN_0 ) //0x31 //
+#define SRSHARP0_HCTI_CON_2_GAIN_1 (SRSHARP0_OFFSET + HCTI_CON_2_GAIN_1 ) //0x32 //
+#define SRSHARP0_HCTI_OS_MARGIN (SRSHARP0_OFFSET + HCTI_OS_MARGIN ) //0x33 //
+#define SRSHARP0_HLTI_FLT_CLP_DC (SRSHARP0_OFFSET + HLTI_FLT_CLP_DC ) //0x34 //
+#define SRSHARP0_HLTI_BST_GAIN (SRSHARP0_OFFSET + HLTI_BST_GAIN ) //0x35 //
+#define SRSHARP0_HLTI_BST_CORE (SRSHARP0_OFFSET + HLTI_BST_CORE ) //0x36 //
+#define SRSHARP0_HLTI_CON_2_GAIN_0 (SRSHARP0_OFFSET + HLTI_CON_2_GAIN_0 ) //0x37 //
+#define SRSHARP0_HLTI_CON_2_GAIN_1 (SRSHARP0_OFFSET + HLTI_CON_2_GAIN_1 ) //0x38 //
+#define SRSHARP0_HLTI_OS_MARGIN (SRSHARP0_OFFSET + HLTI_OS_MARGIN ) //0x39 //
+#define SRSHARP0_VLTI_FLT_CON_CLP (SRSHARP0_OFFSET + VLTI_FLT_CON_CLP ) //0x3a //
+#define SRSHARP0_VLTI_BST_GAIN (SRSHARP0_OFFSET + VLTI_BST_GAIN ) //0x3b //
+#define SRSHARP0_VLTI_BST_CORE (SRSHARP0_OFFSET + VLTI_BST_CORE ) //0x3c //
+#define SRSHARP0_VLTI_CON_2_GAIN_0 (SRSHARP0_OFFSET + VLTI_CON_2_GAIN_0 ) //0x3d //
+#define SRSHARP0_VLTI_CON_2_GAIN_1 (SRSHARP0_OFFSET + VLTI_CON_2_GAIN_1 ) //0x3e //
+#define SRSHARP0_VCTI_FLT_CON_CLP (SRSHARP0_OFFSET + VCTI_FLT_CON_CLP ) //0x3f //
+#define SRSHARP0_VCTI_BST_GAIN (SRSHARP0_OFFSET + VCTI_BST_GAIN ) //0x40 //
+#define SRSHARP0_VCTI_BST_CORE (SRSHARP0_OFFSET + VCTI_BST_CORE ) //0x41 //
+#define SRSHARP0_VCTI_CON_2_GAIN_0 (SRSHARP0_OFFSET + VCTI_CON_2_GAIN_0 ) //0x42 //
+#define SRSHARP0_VCTI_CON_2_GAIN_1 (SRSHARP0_OFFSET + VCTI_CON_2_GAIN_1 ) //0x43 //
+#define SRSHARP0_SHARP_3DLIMIT (SRSHARP0_OFFSET + SHARP_3DLIMIT ) //0x44 //
+#define SRSHARP0_DNLP_EN (SRSHARP0_OFFSET + DNLP_EN ) //0x45 //
+//`define SRSHARP0_DNLP_00 (`SRSHARP0_OFFSET + `DNLP_00 ) //8'h46 //
+//`define SRSHARP0_DNLP_01 (`SRSHARP0_OFFSET + `DNLP_01 ) //8'h47 //
+//`define SRSHARP0_DNLP_02 (`SRSHARP0_OFFSET + `DNLP_02 ) //8'h48 //
+//`define SRSHARP0_DNLP_03 (`SRSHARP0_OFFSET + `DNLP_03 ) //8'h49 //
+//`define SRSHARP0_DNLP_04 (`SRSHARP0_OFFSET + `DNLP_04 ) //8'h4a //
+//`define SRSHARP0_DNLP_05 (`SRSHARP0_OFFSET + `DNLP_05 ) //8'h4b //
+//`define SRSHARP0_DNLP_06 (`SRSHARP0_OFFSET + `DNLP_06 ) //8'h4c //
+//`define SRSHARP0_DNLP_07 (`SRSHARP0_OFFSET + `DNLP_07 ) //8'h4d //
+//`define SRSHARP0_DNLP_08 (`SRSHARP0_OFFSET + `DNLP_08 ) //8'h4e //
+//`define SRSHARP0_DNLP_09 (`SRSHARP0_OFFSET + `DNLP_09 ) //8'h4f //
+//`define SRSHARP0_DNLP_10 (`SRSHARP0_OFFSET + `DNLP_10 ) //8'h50 //
+//`define SRSHARP0_DNLP_11 (`SRSHARP0_OFFSET + `DNLP_11 ) //8'h51 //
+//`define SRSHARP0_DNLP_12 (`SRSHARP0_OFFSET + `DNLP_12 ) //8'h52 //
+//`define SRSHARP0_DNLP_13 (`SRSHARP0_OFFSET + `DNLP_13 ) //8'h53 //
+//`define SRSHARP0_DNLP_14 (`SRSHARP0_OFFSET + `DNLP_14 ) //8'h54 //
+//`define SRSHARP0_DNLP_15 (`SRSHARP0_OFFSET + `DNLP_15 ) //8'h55 //
+#define SRSHARP0_DEMO_CRTL (SRSHARP0_OFFSET + DEMO_CRTL ) //0x56 //
+#define SRSHARP0_SHARP_SR2_CTRL (SRSHARP0_OFFSET + SHARP_SR2_CTRL ) //0x57 //
+#define SRSHARP0_SHARP_SR2_YBIC_HCOEF0 (SRSHARP0_OFFSET + SHARP_SR2_YBIC_HCOEF0 ) //0x58
+#define SRSHARP0_SHARP_SR2_YBIC_HCOEF1 (SRSHARP0_OFFSET + SHARP_SR2_YBIC_HCOEF1 ) //0x59 //
+#define SRSHARP0_SHARP_SR2_CBIC_HCOEF0 (SRSHARP0_OFFSET + SHARP_SR2_CBIC_HCOEF0 ) //0x5a //
+#define SRSHARP0_SHARP_SR2_CBIC_HCOEF1 (SRSHARP0_OFFSET + SHARP_SR2_CBIC_HCOEF1 ) //0x5b //
+#define SRSHARP0_SHARP_SR2_YBIC_VCOEF0 (SRSHARP0_OFFSET + SHARP_SR2_YBIC_VCOEF0 ) //0x5c //
+#define SRSHARP0_SHARP_SR2_YBIC_VCOEF1 (SRSHARP0_OFFSET + SHARP_SR2_YBIC_VCOEF1 ) //0x5d //
+#define SRSHARP0_SHARP_SR2_CBIC_VCOEF0 (SRSHARP0_OFFSET + SHARP_SR2_CBIC_VCOEF0 ) //0x5e //
+#define SRSHARP0_SHARP_SR2_CBIC_VCOEF1 (SRSHARP0_OFFSET + SHARP_SR2_CBIC_VCOEF1 ) //0x5f //
+#define SRSHARP0_SHARP_SR2_MISC (SRSHARP0_OFFSET + SHARP_SR2_MISC ) //0x60 //
+#define SRSHARP0_SR3_SAD_CTRL (SRSHARP0_OFFSET + SHARP_SR3_SAD_CTRL ) // 0x61 //
+#define SRSHARP0_SR3_PK_CTRL0 (SRSHARP0_OFFSET + SHARP_SR3_PK_CTRL0 ) // 0x62
+#define SRSHARP0_SR3_PK_CTRL1 (SRSHARP0_OFFSET + SHARP_SR3_PK_CTRL1 ) // 0x63
+#define SRSHARP0_DEJ_CTRL (SRSHARP0_OFFSET + SHARP_DEJ_CTRL ) // 0x64
+#define SRSHARP0_DEJ_ALPHA (SRSHARP0_OFFSET + SHARP_DEJ_ALPHA ) // 0x65
+#define SRSHARP0_SR3_DRTLPF_EN (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_EN ) // 0x66
+#define SRSHARP0_SR3_DRTLPF_ALPHA_0 (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_ALPHA_0 ) // 0x67
+#define SRSHARP0_SR3_DRTLPF_ALPHA_1 (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_ALPHA_1 ) // 0x68
+#define SRSHARP0_SR3_DRTLPF_ALPHA_2 (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_ALPHA_2 ) // 0x69
+#define SRSHARP0_SR3_DRTLPF_ALPHA_OFST (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_ALPHA_OFST ) // 0x6a
+#define SRSHARP0_SR3_DERING_CTRL (SRSHARP0_OFFSET + SHARP_SR3_DERING_CTRL ) // 0x6b
+#define SRSHARP0_SR3_DERING_LUMA2PKGAIN_0TO3 (SRSHARP0_OFFSET + SHARP_SR3_DERING_LUMA2PKGAIN_0TO3 ) // 0x6c
+#define SRSHARP0_SR3_DERING_LUMA2PKGAIN_4TO6 (SRSHARP0_OFFSET + SHARP_SR3_DERING_LUMA2PKGAIN_4TO6 ) // 0x6d
+#define SRSHARP0_SR3_DERING_LUMA2PKOS_0TO3 (SRSHARP0_OFFSET + SHARP_SR3_DERING_LUMA2PKOS_0TO3 ) // 0x6e
+#define SRSHARP0_SR3_DERING_LUMA2PKOS_4TO6 (SRSHARP0_OFFSET + SHARP_SR3_DERING_LUMA2PKOS_4TO6 ) // 0x6f
+#define SRSHARP0_SR3_DERING_GAINVS_MADSAD (SRSHARP0_OFFSET + SHARP_SR3_DERING_GAINVS_MADSAD ) // 0x70
+#define SRSHARP0_SR3_DERING_GAINVS_VR2MAX (SRSHARP0_OFFSET + SHARP_SR3_DERING_GAINVS_VR2MAX ) // 0x71
+#define SRSHARP0_SR3_DERING_PARAM0 (SRSHARP0_OFFSET + SHARP_SR3_DERING_PARAM0 ) // 0x72
+#define SRSHARP0_SR3_DRTLPF_THETA (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_THETA ) // 0x73
+#define SRSHARP0_SATPRT_CTRL (SRSHARP0_OFFSET + SHARP_SATPRT_CTRL ) // 0x74
+#define SRSHARP0_SATPRT_DIVM (SRSHARP0_OFFSET + SHARP_SATPRT_DIVM ) // 0x75
+#define SRSHARP0_DB_FLT_CTRL (SRSHARP0_OFFSET + SHARP_DB_FLT_CTRL ) // 0x77
+//`define SRSHARP0_DB_FLT_YC_THRD (`SRSHARP0_OFFSET + `SHARP_DB_FLT_YC_THRD ) // 8'h78
+#define SRSHARP0_DB_FLT_CTRL1 (SRSHARP0_OFFSET + SHARP_DB_FLT_CTRL1 ) // 0xb8
+#define SRSHARP0_DB_FLT_LUMA_THRD (SRSHARP0_OFFSET + SHARP_DB_FLT_LUMA_THRD ) // 0xb9
+#define SRSHARP0_DB_FLT_CHRM_THRD (SRSHARP0_OFFSET + SHARP_DB_FLT_CHRM_THRD ) // 0xba
+#define SRSHARP0_DB_FLT_RANDLUT (SRSHARP0_OFFSET + SHARP_DB_FLT_RANDLUT ) // 0x79
+#define SRSHARP0_DB_FLT_PXI_THRD (SRSHARP0_OFFSET + SHARP_DB_FLT_PXI_THRD ) // 0x7a
+#define SRSHARP0_DB_FLT_SEED_Y (SRSHARP0_OFFSET + SHARP_DB_FLT_SEED_Y ) // 0x7b
+#define SRSHARP0_DB_FLT_SEED_U (SRSHARP0_OFFSET + SHARP_DB_FLT_SEED_U ) // 0x7c
+#define SRSHARP0_DB_FLT_SEED_V (SRSHARP0_OFFSET + SHARP_DB_FLT_SEED_V ) // 0x7d
+#define SRSHARP0_PKGAIN_VSLUMA_LUT_L (SRSHARP0_OFFSET + SHARP_PKGAIN_VSLUMA_LUT_L ) // 0x7e
+#define SRSHARP0_PKGAIN_VSLUMA_LUT_H (SRSHARP0_OFFSET + SHARP_PKGAIN_VSLUMA_LUT_H ) // 0x7f
+#define SRSHARP0_PKOSHT_VSLUMA_LUT_L (SRSHARP0_OFFSET + SHARP_PKOSHT_VSLUMA_LUT_L ) // 0x80
+#define SRSHARP0_PKOSHT_VSLUMA_LUT_H (SRSHARP0_OFFSET + SHARP_PKOSHT_VSLUMA_LUT_H ) // 0x81
+#define SRSHARP0_SATPRT_LMT_RGB1 (SRSHARP0_OFFSET + SHARP_SATPRT_LMT_RGB1 ) // 0x82
+#define SRSHARP0_SATPRT_LMT_RGB2 (SRSHARP0_OFFSET + SHARP_SATPRT_LMT_RGB2 ) // 0x83
+#define SRSHARP0_SHARP_GATE_CLK_CTRL_0 (SRSHARP0_OFFSET + SHARP_GATE_CLK_CTRL_0 ) // 0x84
+#define SRSHARP0_SHARP_GATE_CLK_CTRL_1 (SRSHARP0_OFFSET + SHARP_GATE_CLK_CTRL_1 ) // 0x85
+#define SRSHARP0_SHARP_GATE_CLK_CTRL_2 (SRSHARP0_OFFSET + SHARP_GATE_CLK_CTRL_2 ) // 0x86
+#define SRSHARP0_SHARP_GATE_CLK_CTRL_3 (SRSHARP0_OFFSET + SHARP_GATE_CLK_CTRL_3 ) // 0x87
+#define SRSHARP0_SHARP_DPS_CTRL (SRSHARP0_OFFSET + SHARP_DPS_CTRL ) // 0x88
+#define SRSHARP0_DNLP_00 (SRSHARP0_OFFSET + DNLP_00 ) // 0x90 //
+#define SRSHARP0_DNLP_01 (SRSHARP0_OFFSET + DNLP_01 ) // 0x91 //
+#define SRSHARP0_DNLP_02 (SRSHARP0_OFFSET + DNLP_02 ) // 0x92 //
+#define SRSHARP0_DNLP_03 (SRSHARP0_OFFSET + DNLP_03 ) // 0x93 //
+#define SRSHARP0_DNLP_04 (SRSHARP0_OFFSET + DNLP_04 ) // 0x94 //
+#define SRSHARP0_DNLP_05 (SRSHARP0_OFFSET + DNLP_05 ) // 0x95 //
+#define SRSHARP0_DNLP_06 (SRSHARP0_OFFSET + DNLP_06 ) // 0x96 //
+#define SRSHARP0_DNLP_07 (SRSHARP0_OFFSET + DNLP_07 ) // 0x97 //
+#define SRSHARP0_DNLP_08 (SRSHARP0_OFFSET + DNLP_08 ) // 0x98 //
+#define SRSHARP0_DNLP_09 (SRSHARP0_OFFSET + DNLP_09 ) // 0x99 //
+#define SRSHARP0_DNLP_10 (SRSHARP0_OFFSET + DNLP_10 ) // 0x9a //
+#define SRSHARP0_DNLP_11 (SRSHARP0_OFFSET + DNLP_11 ) // 0x9b //
+#define SRSHARP0_DNLP_12 (SRSHARP0_OFFSET + DNLP_12 ) // 0x9c //
+#define SRSHARP0_DNLP_13 (SRSHARP0_OFFSET + DNLP_13 ) // 0x9d //
+#define SRSHARP0_DNLP_14 (SRSHARP0_OFFSET + DNLP_14 ) // 0x9e //
+#define SRSHARP0_DNLP_15 (SRSHARP0_OFFSET + DNLP_15 ) // 0x9f //
+#define SRSHARP0_DNLP_16 (SRSHARP0_OFFSET + DNLP_16 ) // 0xa0 //
+#define SRSHARP0_DNLP_17 (SRSHARP0_OFFSET + DNLP_17 ) // 0xa1 //
+#define SRSHARP0_DNLP_18 (SRSHARP0_OFFSET + DNLP_18 ) // 0xa2 //
+#define SRSHARP0_DNLP_19 (SRSHARP0_OFFSET + DNLP_19 ) // 0xa3 //
+#define SRSHARP0_DNLP_20 (SRSHARP0_OFFSET + DNLP_20 ) // 0xa4 //
+#define SRSHARP0_DNLP_21 (SRSHARP0_OFFSET + DNLP_21 ) // 0xa5 //
+#define SRSHARP0_DNLP_22 (SRSHARP0_OFFSET + DNLP_22 ) // 0xa6 //
+#define SRSHARP0_DNLP_23 (SRSHARP0_OFFSET + DNLP_23 ) // 0xa7 //
+#define SRSHARP0_DNLP_24 (SRSHARP0_OFFSET + DNLP_24 ) // 0xa8 //
+#define SRSHARP0_DNLP_25 (SRSHARP0_OFFSET + DNLP_25 ) // 0xa9 //
+#define SRSHARP0_DNLP_26 (SRSHARP0_OFFSET + DNLP_26 ) // 0xaa //
+#define SRSHARP0_DNLP_27 (SRSHARP0_OFFSET + DNLP_27 ) // 0xab //
+#define SRSHARP0_DNLP_28 (SRSHARP0_OFFSET + DNLP_28 ) // 0xac //
+#define SRSHARP0_DNLP_29 (SRSHARP0_OFFSET + DNLP_29 ) // 0xad //
+#define SRSHARP0_DNLP_30 (SRSHARP0_OFFSET + DNLP_30 ) // 0xae //
+#define SRSHARP0_DNLP_31 (SRSHARP0_OFFSET + DNLP_31 ) // 0xaf //
+#define SRSHARP0_SHARP_SYNC_CTRL (SRSHARP0_OFFSET + SHARP_SYNC_CTRL ) // 0xb0 //
+#define SRSHARP0_LC_INPUT_MUX (SRSHARP0_OFFSET + LC_INPUT_MUX ) // 0xb1 //
+#define SRSHARP0_NR_GAU_YH_COEF02 (SRSHARP0_OFFSET + NR_GAU_YH_COEF02 ) // 0xb2 //
+#define SRSHARP0_NR_GAU_YH_COEF34 (SRSHARP0_OFFSET + NR_GAU_YH_COEF34 ) // 0xb3 //
+#define SRSHARP0_NR_GAU_YV_COEF1 (SRSHARP0_OFFSET + NR_GAU_YV_COEF1 ) // 0xb4 //
+#define SRSHARP0_NR_GAU_CH_COEF02 (SRSHARP0_OFFSET + NR_GAU_CH_COEF02 ) // 0xb5 //
+#define SRSHARP0_NR_GAU_CH_COEF34 (SRSHARP0_OFFSET + NR_GAU_CH_COEF34 ) // 0xb6 //
+#define SRSHARP0_NR_GAU_CV_COEF1 (SRSHARP0_OFFSET + NR_GAU_CV_COEF1 ) // 0xb7 //
+#define SRSHARP0_LC_TOP_CTRL (SRSHARP0_OFFSET + LC_TOP_CTRL ) // 0xc0 //
+#define SRSHARP0_LC_HV_NUM (SRSHARP0_OFFSET + LC_HV_NUM ) // 0xc1
+#define SRSHARP0_LC_SAT_LUT_0_1 (SRSHARP0_OFFSET + LC_SAT_LUT_0_1 ) // 0xc2
+#define SRSHARP0_LC_SAT_LUT_2_3 (SRSHARP0_OFFSET + LC_SAT_LUT_2_3 ) // 0xc3
+#define SRSHARP0_LC_SAT_LUT_4_5 (SRSHARP0_OFFSET + LC_SAT_LUT_4_5 ) // 0xc4
+#define SRSHARP0_LC_SAT_LUT_6_7 (SRSHARP0_OFFSET + LC_SAT_LUT_6_7 ) // 0xc5
+#define SRSHARP0_LC_SAT_LUT_8_9 (SRSHARP0_OFFSET + LC_SAT_LUT_8_9 ) // 0xc6
+#define SRSHARP0_LC_SAT_LUT_10_11 (SRSHARP0_OFFSET + LC_SAT_LUT_10_11 ) // 0xc7
+#define SRSHARP0_LC_SAT_LUT_12_13 (SRSHARP0_OFFSET + LC_SAT_LUT_12_13 ) // 0xc8
+#define SRSHARP0_LC_SAT_LUT_14_15 (SRSHARP0_OFFSET + LC_SAT_LUT_14_15 ) // 0xc9
+#define SRSHARP0_LC_SAT_LUT_16_17 (SRSHARP0_OFFSET + LC_SAT_LUT_16_17 ) // 0xca
+#define SRSHARP0_LC_SAT_LUT_18_19 (SRSHARP0_OFFSET + LC_SAT_LUT_18_19 ) // 0xcb
+#define SRSHARP0_LC_SAT_LUT_20_21 (SRSHARP0_OFFSET + LC_SAT_LUT_20_21 ) // 0xcc
+#define SRSHARP0_LC_SAT_LUT_22_23 (SRSHARP0_OFFSET + LC_SAT_LUT_22_23 ) // 0xcd
+#define SRSHARP0_LC_SAT_LUT_24_25 (SRSHARP0_OFFSET + LC_SAT_LUT_24_25 ) // 0xce
+#define SRSHARP0_LC_SAT_LUT_26_27 (SRSHARP0_OFFSET + LC_SAT_LUT_26_27 ) // 0xcf
+#define SRSHARP0_LC_SAT_LUT_28_29 (SRSHARP0_OFFSET + LC_SAT_LUT_28_29 ) // 0xd0
+#define SRSHARP0_LC_SAT_LUT_30_31 (SRSHARP0_OFFSET + LC_SAT_LUT_30_31 ) // 0xd1
+#define SRSHARP0_LC_SAT_LUT_32_33 (SRSHARP0_OFFSET + LC_SAT_LUT_32_33 ) // 0xd2
+#define SRSHARP0_LC_SAT_LUT_34_35 (SRSHARP0_OFFSET + LC_SAT_LUT_34_35 ) // 0xd3
+#define SRSHARP0_LC_SAT_LUT_36_37 (SRSHARP0_OFFSET + LC_SAT_LUT_36_37 ) // 0xd4
+#define SRSHARP0_LC_SAT_LUT_38_39 (SRSHARP0_OFFSET + LC_SAT_LUT_38_39 ) // 0xd5
+#define SRSHARP0_LC_SAT_LUT_40_41 (SRSHARP0_OFFSET + LC_SAT_LUT_40_41 ) // 0xd6
+#define SRSHARP0_LC_SAT_LUT_42_43 (SRSHARP0_OFFSET + LC_SAT_LUT_42_43 ) // 0xd7
+#define SRSHARP0_LC_SAT_LUT_44_45 (SRSHARP0_OFFSET + LC_SAT_LUT_44_45 ) // 0xd8
+#define SRSHARP0_LC_SAT_LUT_46_47 (SRSHARP0_OFFSET + LC_SAT_LUT_46_47 ) // 0xd9
+#define SRSHARP0_LC_SAT_LUT_48_49 (SRSHARP0_OFFSET + LC_SAT_LUT_48_49 ) // 0xda
+#define SRSHARP0_LC_SAT_LUT_50_51 (SRSHARP0_OFFSET + LC_SAT_LUT_50_51 ) // 0xdb
+#define SRSHARP0_LC_SAT_LUT_52_53 (SRSHARP0_OFFSET + LC_SAT_LUT_52_53 ) // 0xdc
+#define SRSHARP0_LC_SAT_LUT_54_55 (SRSHARP0_OFFSET + LC_SAT_LUT_54_55 ) // 0xdd
+#define SRSHARP0_LC_SAT_LUT_56_57 (SRSHARP0_OFFSET + LC_SAT_LUT_56_57 ) // 0xde
+#define SRSHARP0_LC_SAT_LUT_58_59 (SRSHARP0_OFFSET + LC_SAT_LUT_58_59 ) // 0xdf
+#define SRSHARP0_LC_SAT_LUT_60_61 (SRSHARP0_OFFSET + LC_SAT_LUT_60_61 ) // 0xe0
+#define SRSHARP0_LC_SAT_LUT_62 (SRSHARP0_OFFSET + LC_SAT_LUT_62 ) // 0xe1
+#define SRSHARP0_LC_CURVE_BLK_HIDX_0_1 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_0_1 ) // 0xe2
+#define SRSHARP0_LC_CURVE_BLK_HIDX_2_3 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_2_3 ) // 0xe3
+#define SRSHARP0_LC_CURVE_BLK_HIDX_4_5 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_4_5 ) // 0xe4
+#define SRSHARP0_LC_CURVE_BLK_HIDX_6_7 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_6_7 ) // 0xe5
+#define SRSHARP0_LC_CURVE_BLK_HIDX_8_9 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_8_9 ) // 0xe6
+#define SRSHARP0_LC_CURVE_BLK_HIDX_10_11 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_10_11 ) // 0xe7
+#define SRSHARP0_LC_CURVE_BLK_HIDX_12 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_12 ) // 0xe8
+#define SRSHARP0_LC_CURVE_BLK_VIDX_0_1 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_0_1 ) // 0xe9
+#define SRSHARP0_LC_CURVE_BLK_VIDX_2_3 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_2_3 ) // 0xea
+#define SRSHARP0_LC_CURVE_BLK_VIDX_4_5 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_4_5 ) // 0xeb
+#define SRSHARP0_LC_CURVE_BLK_VIDX_6_7 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_6_7 ) // 0xec
+#define SRSHARP0_LC_CURVE_BLK_VIDX_8 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_8 ) // 0xed
+#define SRSHARP0_LC_YUV2RGB_MAT_0_1 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_0_1 ) // 0xee
+#define SRSHARP0_LC_YUV2RGB_MAT_2_3 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_2_3 ) // 0xef
+#define SRSHARP0_LC_YUV2RGB_MAT_4_5 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_4_5 ) // 0xf0
+#define SRSHARP0_LC_YUV2RGB_MAT_6_7 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_6_7 ) // 0xf1
+#define SRSHARP0_LC_YUV2RGB_MAT_8 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_8 ) // 0xf2
+#define SRSHARP0_LC_RGB2YUV_MAT_0_1 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_0_1 ) // 0xf3
+#define SRSHARP0_LC_RGB2YUV_MAT_2_3 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_2_3 ) // 0xf4
+#define SRSHARP0_LC_RGB2YUV_MAT_4_5 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_4_5 ) // 0xf5
+#define SRSHARP0_LC_RGB2YUV_MAT_6_7 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_6_7 ) // 0xf6
+#define SRSHARP0_LC_RGB2YUV_MAT_8 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_8 ) // 0xf7
+#define SRSHARP0_LC_YUV2RGB_OFST (SRSHARP0_OFFSET + LC_YUV2RGB_OFST ) // 0xf8
+#define SRSHARP0_LC_YUV2RGB_CLIP (SRSHARP0_OFFSET + LC_YUV2RGB_CLIP ) // 0xf9
+#define SRSHARP0_LC_RGB2YUV_OFST (SRSHARP0_OFFSET + LC_RGB2YUV_OFST ) // 0xfa
+#define SRSHARP0_LC_RGB2YUV_CLIP (SRSHARP0_OFFSET + LC_RGB2YUV_CLIP ) // 0xfb
+#define SRSHARP0_LC_MAP_RAM_CTRL (SRSHARP0_OFFSET + LC_MAP_RAM_CTRL ) // 0xfc
+#define SRSHARP0_LC_MAP_RAM_ADDR (SRSHARP0_OFFSET + LC_MAP_RAM_ADDR ) // 0xfd
+#define SRSHARP0_LC_MAP_RAM_DATA (SRSHARP0_OFFSET + LC_MAP_RAM_DATA ) // 0xfe
+
+#define SRSHARP0_FMETER_CTRL (SRSHARP0_OFFSET + SHARP_FMETER_CTRL ) // 0x89
+#define SRSHARP0_FMETER_WIN_HOR (SRSHARP0_OFFSET + SHARP_FMETER_WIN_HOR ) // 0x8a
+#define SRSHARP0_FMETER_WIN_VER (SRSHARP0_OFFSET + SHARP_FMETER_WIN_VER ) // 0x8b
+#define SRSHARP0_FMETER_CORING (SRSHARP0_OFFSET + SHARP_FMETER_CORING ) // 0x8c
+#define SRSHARP0_FMETER_RATIO_H (SRSHARP0_OFFSET + SHARP_FMETER_RATIO_H ) // 0x8d
+#define SRSHARP0_FMETER_RATIO_V (SRSHARP0_OFFSET + SHARP_FMETER_RATIO_V ) // 0x8e
+#define SRSHARP0_FMETER_RATIO_D (SRSHARP0_OFFSET + SHARP_FMETER_RATIO_D ) // 0x8f
+#define SRSHARP0_RO_FMETER_HCNT_TYPE0 (SRSHARP0_OFFSET + SHARP_RO_FMETER_HCNT_TYPE0 ) // 0x46
+#define SRSHARP0_RO_FMETER_HCNT_TYPE1 (SRSHARP0_OFFSET + SHARP_RO_FMETER_HCNT_TYPE1 ) // 0x47
+#define SRSHARP0_RO_FMETER_HCNT_TYPE2 (SRSHARP0_OFFSET + SHARP_RO_FMETER_HCNT_TYPE2 ) // 0x48
+#define SRSHARP0_RO_FMETER_HCNT_TYPE3 (SRSHARP0_OFFSET + SHARP_RO_FMETER_HCNT_TYPE3 ) // 0x49
+#define SRSHARP0_RO_FMETER_VCNT_TYPE0 (SRSHARP0_OFFSET + SHARP_RO_FMETER_VCNT_TYPE0 ) // 0x4a
+#define SRSHARP0_RO_FMETER_VCNT_TYPE1 (SRSHARP0_OFFSET + SHARP_RO_FMETER_VCNT_TYPE1 ) // 0x4b
+#define SRSHARP0_RO_FMETER_VCNT_TYPE2 (SRSHARP0_OFFSET + SHARP_RO_FMETER_VCNT_TYPE2 ) // 0x4c
+#define SRSHARP0_RO_FMETER_VCNT_TYPE3 (SRSHARP0_OFFSET + SHARP_RO_FMETER_VCNT_TYPE3 ) // 0x4d
+#define SRSHARP0_RO_FMETER_PDCNT_TYPE0 (SRSHARP0_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE0 ) // 0x4e
+#define SRSHARP0_RO_FMETER_PDCNT_TYPE1 (SRSHARP0_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE1 ) // 0x4f
+#define SRSHARP0_RO_FMETER_PDCNT_TYPE2 (SRSHARP0_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE2 ) // 0x50
+#define SRSHARP0_RO_FMETER_PDCNT_TYPE3 (SRSHARP0_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE3 ) // 0x51
+#define SRSHARP0_RO_FMETER_NDCNT_TYPE0 (SRSHARP0_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE0 ) // 0x52
+#define SRSHARP0_RO_FMETER_NDCNT_TYPE1 (SRSHARP0_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE1 ) // 0x53
+#define SRSHARP0_RO_FMETER_NDCNT_TYPE2 (SRSHARP0_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE2 ) // 0x54
+#define SRSHARP0_RO_FMETER_NDCNT_TYPE3 (SRSHARP0_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE3 ) // 0x55
+
+
+
+
+
+//// srsharp1 reg define
+
+#define SRSHARP1_SHARP_HVSIZE (SRSHARP1_OFFSET + SHARP_HVSIZE ) //0x00 //
+#define SRSHARP1_SHARP_HVBLANK_NUM (SRSHARP1_OFFSET + SHARP_HVBLANK_NUM ) //0x01 //
+#define SRSHARP1_NR_GAUSSIAN_MODE (SRSHARP1_OFFSET + NR_GAUSSIAN_MODE ) //0x02 //
+#define SRSHARP1_PK_CON_2CIRHPGAIN_TH_RATE (SRSHARP1_OFFSET + PK_CON_2CIRHPGAIN_TH_RATE ) //0x05 //
+#define SRSHARP1_PK_CON_2CIRHPGAIN_LIMIT (SRSHARP1_OFFSET + PK_CON_2CIRHPGAIN_LIMIT ) //0x06 //
+#define SRSHARP1_PK_CON_2CIRBPGAIN_TH_RATE (SRSHARP1_OFFSET + PK_CON_2CIRBPGAIN_TH_RATE ) //0x07 //
+#define SRSHARP1_PK_CON_2CIRBPGAIN_LIMIT (SRSHARP1_OFFSET + PK_CON_2CIRBPGAIN_LIMIT ) //0x08 //
+#define SRSHARP1_PK_CON_2DRTHPGAIN_TH_RATE (SRSHARP1_OFFSET + PK_CON_2DRTHPGAIN_TH_RATE ) //0x09 //
+#define SRSHARP1_PK_CON_2DRTHPGAIN_LIMIT (SRSHARP1_OFFSET + PK_CON_2DRTHPGAIN_LIMIT ) //0x0a //
+#define SRSHARP1_PK_CON_2DRTBPGAIN_TH_RATE (SRSHARP1_OFFSET + PK_CON_2DRTBPGAIN_TH_RATE ) //0x0b //
+#define SRSHARP1_PK_CON_2DRTBPGAIN_LIMIT (SRSHARP1_OFFSET + PK_CON_2DRTBPGAIN_LIMIT ) //0x0c //
+#define SRSHARP1_PK_CIRFB_LPF_MODE (SRSHARP1_OFFSET + PK_CIRFB_LPF_MODE ) //0x0d //
+#define SRSHARP1_PK_DRTFB_LPF_MODE (SRSHARP1_OFFSET + PK_DRTFB_LPF_MODE ) //0x0e //
+#define SRSHARP1_PK_CIRFB_HP_CORING (SRSHARP1_OFFSET + PK_CIRFB_HP_CORING ) //0x0f //
+#define SRSHARP1_PK_CIRFB_BP_CORING (SRSHARP1_OFFSET + PK_CIRFB_BP_CORING ) //0x10 //
+#define SRSHARP1_PK_DRTFB_HP_CORING (SRSHARP1_OFFSET + PK_DRTFB_HP_CORING ) //0x11 //
+#define SRSHARP1_PK_DRTFB_BP_CORING (SRSHARP1_OFFSET + PK_DRTFB_BP_CORING ) //0x12 //
+#define SRSHARP1_PK_CIRFB_BLEND_GAIN (SRSHARP1_OFFSET + PK_CIRFB_BLEND_GAIN ) //0x13 //
+#define SRSHARP1_NR_ALPY_SSD_GAIN_OFST (SRSHARP1_OFFSET + NR_ALPY_SSD_GAIN_OFST ) //0x14 //
+#define SRSHARP1_NR_ALP0Y_ERR2CURV_TH_RATE (SRSHARP1_OFFSET + NR_ALP0Y_ERR2CURV_TH_RATE ) //0x15 //
+#define SRSHARP1_NR_ALP0Y_ERR2CURV_LIMIT (SRSHARP1_OFFSET + NR_ALP0Y_ERR2CURV_LIMIT ) //0x16 //
+#define SRSHARP1_NR_ALP0C_ERR2CURV_TH_RATE (SRSHARP1_OFFSET + NR_ALP0C_ERR2CURV_TH_RATE ) //0x17 //
+#define SRSHARP1_NR_ALP0C_ERR2CURV_LIMIT (SRSHARP1_OFFSET + NR_ALP0C_ERR2CURV_LIMIT ) //0x18 //
+#define SRSHARP1_NR_ALP0_MIN_MAX (SRSHARP1_OFFSET + NR_ALP0_MIN_MAX ) //0x19 //
+#define SRSHARP1_NR_ALP1_MIERR_CORING (SRSHARP1_OFFSET + NR_ALP1_MIERR_CORING ) //0x1a //
+#define SRSHARP1_NR_ALP1_ERR2CURV_TH_RATE (SRSHARP1_OFFSET + NR_ALP1_ERR2CURV_TH_RATE ) //0x1b //
+#define SRSHARP1_NR_ALP1_ERR2CURV_LIMIT (SRSHARP1_OFFSET + NR_ALP1_ERR2CURV_LIMIT ) //0x1c //
+#define SRSHARP1_NR_ALP1_MIN_MAX (SRSHARP1_OFFSET + NR_ALP1_MIN_MAX ) //0x1d //
+#define SRSHARP1_PK_ALP2_MIERR_CORING (SRSHARP1_OFFSET + PK_ALP2_MIERR_CORING ) //0x1e //
+#define SRSHARP1_PK_ALP2_ERR2CURV_TH_RATE (SRSHARP1_OFFSET + PK_ALP2_ERR2CURV_TH_RATE ) //0x1f //
+#define SRSHARP1_PK_ALP2_ERR2CURV_LIMIT (SRSHARP1_OFFSET + PK_ALP2_ERR2CURV_LIMIT ) //0x20 //
+#define SRSHARP1_PK_ALP2_MIN_MAX (SRSHARP1_OFFSET + PK_ALP2_MIN_MAX ) //0x21 //
+#define SRSHARP1_PK_FINALGAIN_HP_BP (SRSHARP1_OFFSET + PK_FINALGAIN_HP_BP ) //0x22 //
+#define SRSHARP1_PK_OS_HORZ_CORE_GAIN (SRSHARP1_OFFSET + PK_OS_HORZ_CORE_GAIN ) //0x23 //
+#define SRSHARP1_PK_OS_VERT_CORE_GAIN (SRSHARP1_OFFSET + PK_OS_VERT_CORE_GAIN ) //0x24 //
+#define SRSHARP1_PK_OS_ADPT_MISC (SRSHARP1_OFFSET + PK_OS_ADPT_MISC ) //0x25 //
+#define SRSHARP1_PK_OS_STATIC (SRSHARP1_OFFSET + PK_OS_STATIC ) //0x26 //
+#define SRSHARP1_PK_NR_ENABLE (SRSHARP1_OFFSET + PK_NR_ENABLE ) //0x27 //
+#define SRSHARP1_PK_DRT_SAD_MISC (SRSHARP1_OFFSET + PK_DRT_SAD_MISC ) //0x28 //
+#define SRSHARP1_NR_TI_DNLP_BLEND (SRSHARP1_OFFSET + NR_TI_DNLP_BLEND ) //0x29 //
+#define SRSHARP1_LTI_DIR_CORE_ALPHA (SRSHARP1_OFFSET + LTI_DIR_CORE_ALPHA ) //0x2a //
+#define SRSHARP1_CTI_DIR_ALPHA (SRSHARP1_OFFSET + CTI_DIR_ALPHA ) //0x2b //
+#define SRSHARP1_LTI_CTI_DF_GAIN (SRSHARP1_OFFSET + LTI_CTI_DF_GAIN ) //0x2c //
+#define SRSHARP1_LTI_CTI_DIR_AC_DBG (SRSHARP1_OFFSET + LTI_CTI_DIR_AC_DBG ) //0x2d //
+#define SRSHARP1_HCTI_FLT_CLP_DC (SRSHARP1_OFFSET + HCTI_FLT_CLP_DC ) //0x2e //
+#define SRSHARP1_HCTI_BST_GAIN (SRSHARP1_OFFSET + HCTI_BST_GAIN ) //0x2f //
+#define SRSHARP1_HCTI_BST_CORE (SRSHARP1_OFFSET + HCTI_BST_CORE ) //0x30 //
+#define SRSHARP1_HCTI_CON_2_GAIN_0 (SRSHARP1_OFFSET + HCTI_CON_2_GAIN_0 ) //0x31 //
+#define SRSHARP1_HCTI_CON_2_GAIN_1 (SRSHARP1_OFFSET + HCTI_CON_2_GAIN_1 ) //0x32 //
+#define SRSHARP1_HCTI_OS_MARGIN (SRSHARP1_OFFSET + HCTI_OS_MARGIN ) //0x33 //
+#define SRSHARP1_HLTI_FLT_CLP_DC (SRSHARP1_OFFSET + HLTI_FLT_CLP_DC ) //0x34 //
+#define SRSHARP1_HLTI_BST_GAIN (SRSHARP1_OFFSET + HLTI_BST_GAIN ) //0x35 //
+#define SRSHARP1_HLTI_BST_CORE (SRSHARP1_OFFSET + HLTI_BST_CORE ) //0x36 //
+#define SRSHARP1_HLTI_CON_2_GAIN_0 (SRSHARP1_OFFSET + HLTI_CON_2_GAIN_0 ) //0x37 //
+#define SRSHARP1_HLTI_CON_2_GAIN_1 (SRSHARP1_OFFSET + HLTI_CON_2_GAIN_1 ) //0x38 //
+#define SRSHARP1_HLTI_OS_MARGIN (SRSHARP1_OFFSET + HLTI_OS_MARGIN ) //0x39 //
+#define SRSHARP1_VLTI_FLT_CON_CLP (SRSHARP1_OFFSET + VLTI_FLT_CON_CLP ) //0x3a //
+#define SRSHARP1_VLTI_BST_GAIN (SRSHARP1_OFFSET + VLTI_BST_GAIN ) //0x3b //
+#define SRSHARP1_VLTI_BST_CORE (SRSHARP1_OFFSET + VLTI_BST_CORE ) //0x3c //
+#define SRSHARP1_VLTI_CON_2_GAIN_0 (SRSHARP1_OFFSET + VLTI_CON_2_GAIN_0 ) //0x3d //
+#define SRSHARP1_VLTI_CON_2_GAIN_1 (SRSHARP1_OFFSET + VLTI_CON_2_GAIN_1 ) //0x3e //
+#define SRSHARP1_VCTI_FLT_CON_CLP (SRSHARP1_OFFSET + VCTI_FLT_CON_CLP ) //0x3f //
+#define SRSHARP1_VCTI_BST_GAIN (SRSHARP1_OFFSET + VCTI_BST_GAIN ) //0x40 //
+#define SRSHARP1_VCTI_BST_CORE (SRSHARP1_OFFSET + VCTI_BST_CORE ) //0x41 //
+#define SRSHARP1_VCTI_CON_2_GAIN_0 (SRSHARP1_OFFSET + VCTI_CON_2_GAIN_0 ) //0x42 //
+#define SRSHARP1_VCTI_CON_2_GAIN_1 (SRSHARP1_OFFSET + VCTI_CON_2_GAIN_1 ) //0x43 //
+#define SRSHARP1_SHARP_3DLIMIT (SRSHARP1_OFFSET + SHARP_3DLIMIT ) //0x44 //
+#define SRSHARP1_DNLP_EN (SRSHARP1_OFFSET + DNLP_EN ) //0x45 //
+//`define SRSHARP1_DNLP_00 (`SRSHARP1_OFFSET + `DNLP_00 ) //8'h46 //
+//`define SRSHARP1_DNLP_01 (`SRSHARP1_OFFSET + `DNLP_01 ) //8'h47 //
+//`define SRSHARP1_DNLP_02 (`SRSHARP1_OFFSET + `DNLP_02 ) //8'h48 //
+//`define SRSHARP1_DNLP_03 (`SRSHARP1_OFFSET + `DNLP_03 ) //8'h49 //
+//`define SRSHARP1_DNLP_04 (`SRSHARP1_OFFSET + `DNLP_04 ) //8'h4a //
+//`define SRSHARP1_DNLP_05 (`SRSHARP1_OFFSET + `DNLP_05 ) //8'h4b //
+//`define SRSHARP1_DNLP_06 (`SRSHARP1_OFFSET + `DNLP_06 ) //8'h4c //
+//`define SRSHARP1_DNLP_07 (`SRSHARP1_OFFSET + `DNLP_07 ) //8'h4d //
+//`define SRSHARP1_DNLP_08 (`SRSHARP1_OFFSET + `DNLP_08 ) //8'h4e //
+//`define SRSHARP1_DNLP_09 (`SRSHARP1_OFFSET + `DNLP_09 ) //8'h4f //
+//`define SRSHARP1_DNLP_10 (`SRSHARP1_OFFSET + `DNLP_10 ) //8'h50 //
+//`define SRSHARP1_DNLP_11 (`SRSHARP1_OFFSET + `DNLP_11 ) //8'h51 //
+//`define SRSHARP1_DNLP_12 (`SRSHARP1_OFFSET + `DNLP_12 ) //8'h52 //
+//`define SRSHARP1_DNLP_13 (`SRSHARP1_OFFSET + `DNLP_13 ) //8'h53 //
+//`define SRSHARP1_DNLP_14 (`SRSHARP1_OFFSET + `DNLP_14 ) //8'h54 //
+//`define SRSHARP1_DNLP_15 (`SRSHARP1_OFFSET + `DNLP_15 ) //8'h55 //
+#define SRSHARP1_DEMO_CRTL (SRSHARP1_OFFSET + DEMO_CRTL ) //0x56 //
+#define SRSHARP1_SHARP_SR2_CTRL (SRSHARP1_OFFSET + SHARP_SR2_CTRL ) //0x57 //
+#define SRSHARP1_SHARP_SR2_YBIC_HCOEF0 (SRSHARP1_OFFSET + SHARP_SR2_YBIC_HCOEF0 ) //0x58
+#define SRSHARP1_SHARP_SR2_YBIC_HCOEF1 (SRSHARP1_OFFSET + SHARP_SR2_YBIC_HCOEF1 ) //0x59 //
+#define SRSHARP1_SHARP_SR2_CBIC_HCOEF0 (SRSHARP1_OFFSET + SHARP_SR2_CBIC_HCOEF0 ) //0x5a //
+#define SRSHARP1_SHARP_SR2_CBIC_HCOEF1 (SRSHARP1_OFFSET + SHARP_SR2_CBIC_HCOEF1 ) //0x5b //
+#define SRSHARP1_SHARP_SR2_YBIC_VCOEF0 (SRSHARP1_OFFSET + SHARP_SR2_YBIC_VCOEF0 ) //0x5c //
+#define SRSHARP1_SHARP_SR2_YBIC_VCOEF1 (SRSHARP1_OFFSET + SHARP_SR2_YBIC_VCOEF1 ) //0x5d //
+#define SRSHARP1_SHARP_SR2_CBIC_VCOEF0 (SRSHARP1_OFFSET + SHARP_SR2_CBIC_VCOEF0 ) //0x5e //
+#define SRSHARP1_SHARP_SR2_CBIC_VCOEF1 (SRSHARP1_OFFSET + SHARP_SR2_CBIC_VCOEF1 ) //0x5f //
+#define SRSHARP1_SHARP_SR2_MISC (SRSHARP1_OFFSET + SHARP_SR2_MISC ) //0x60 //
+#define SRSHARP1_SR3_SAD_CTRL (SRSHARP1_OFFSET + SHARP_SR3_SAD_CTRL ) // 0x61 //
+#define SRSHARP1_SR3_PK_CTRL0 (SRSHARP1_OFFSET + SHARP_SR3_PK_CTRL0 ) // 0x62
+#define SRSHARP1_SR3_PK_CTRL1 (SRSHARP1_OFFSET + SHARP_SR3_PK_CTRL1 ) // 0x63
+#define SRSHARP1_DEJ_CTRL (SRSHARP1_OFFSET + SHARP_DEJ_CTRL ) // 0x64
+#define SRSHARP1_DEJ_ALPHA (SRSHARP1_OFFSET + SHARP_DEJ_ALPHA ) // 0x65
+#define SRSHARP1_SR3_DRTLPF_EN (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_EN ) // 0x66
+#define SRSHARP1_SR3_DRTLPF_ALPHA_0 (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_ALPHA_0 ) // 0x67
+#define SRSHARP1_SR3_DRTLPF_ALPHA_1 (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_ALPHA_1 ) // 0x68
+#define SRSHARP1_SR3_DRTLPF_ALPHA_2 (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_ALPHA_2 ) // 0x69
+#define SRSHARP1_SR3_DRTLPF_ALPHA_OFST (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_ALPHA_OFST ) // 0x6a
+#define SRSHARP1_SR3_DERING_CTRL (SRSHARP1_OFFSET + SHARP_SR3_DERING_CTRL ) // 0x6b
+#define SRSHARP1_SR3_DERING_LUMA2PKGAIN_0TO3 (SRSHARP1_OFFSET + SHARP_SR3_DERING_LUMA2PKGAIN_0TO3 ) // 0x6c
+#define SRSHARP1_SR3_DERING_LUMA2PKGAIN_4TO6 (SRSHARP1_OFFSET + SHARP_SR3_DERING_LUMA2PKGAIN_4TO6 ) // 0x6d
+#define SRSHARP1_SR3_DERING_LUMA2PKOS_0TO3 (SRSHARP1_OFFSET + SHARP_SR3_DERING_LUMA2PKOS_0TO3 ) // 0x6e
+#define SRSHARP1_SR3_DERING_LUMA2PKOS_4TO6 (SRSHARP1_OFFSET + SHARP_SR3_DERING_LUMA2PKOS_4TO6 ) // 0x6f
+#define SRSHARP1_SR3_DERING_GAINVS_MADSAD (SRSHARP1_OFFSET + SHARP_SR3_DERING_GAINVS_MADSAD ) // 0x70
+#define SRSHARP1_SR3_DERING_GAINVS_VR2MAX (SRSHARP1_OFFSET + SHARP_SR3_DERING_GAINVS_VR2MAX ) // 0x71
+#define SRSHARP1_SR3_DERING_PARAM0 (SRSHARP1_OFFSET + SHARP_SR3_DERING_PARAM0 ) // 0x72
+#define SRSHARP1_SR3_DRTLPF_THETA (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_THETA ) // 0x73
+#define SRSHARP1_SATPRT_CTRL (SRSHARP1_OFFSET + SHARP_SATPRT_CTRL ) // 0x74
+#define SRSHARP1_SATPRT_DIVM (SRSHARP1_OFFSET + SHARP_SATPRT_DIVM ) // 0x75
+#define SRSHARP1_DB_FLT_CTRL (SRSHARP1_OFFSET + SHARP_DB_FLT_CTRL ) // 0x77
+//`define SRSHARP1_DB_FLT_YC_THRD (`SRSHARP1_OFFSET + `SHARP_DB_FLT_YC_THRD ) // 8'h78
+#define SRSHARP1_DB_FLT_CTRL1 (SRSHARP1_OFFSET + SHARP_DB_FLT_CTRL1 ) // 0xb8
+#define SRSHARP1_DB_FLT_LUMA_THRD (SRSHARP1_OFFSET + SHARP_DB_FLT_LUMA_THRD ) // 0xb9
+#define SRSHARP1_DB_FLT_CHRM_THRD (SRSHARP1_OFFSET + SHARP_DB_FLT_CHRM_THRD ) // 0xba
+#define SRSHARP1_DB_FLT_RANDLUT (SRSHARP1_OFFSET + SHARP_DB_FLT_RANDLUT ) // 0x79
+#define SRSHARP1_DB_FLT_PXI_THRD (SRSHARP1_OFFSET + SHARP_DB_FLT_PXI_THRD ) // 0x7a
+#define SRSHARP1_DB_FLT_SEED_Y (SRSHARP1_OFFSET + SHARP_DB_FLT_SEED_Y ) // 0x7b
+#define SRSHARP1_DB_FLT_SEED_U (SRSHARP1_OFFSET + SHARP_DB_FLT_SEED_U ) // 0x7c
+#define SRSHARP1_DB_FLT_SEED_V (SRSHARP1_OFFSET + SHARP_DB_FLT_SEED_V ) // 0x7d
+#define SRSHARP1_PKGAIN_VSLUMA_LUT_L (SRSHARP1_OFFSET + SHARP_PKGAIN_VSLUMA_LUT_L ) // 0x7e
+#define SRSHARP1_PKGAIN_VSLUMA_LUT_H (SRSHARP1_OFFSET + SHARP_PKGAIN_VSLUMA_LUT_H ) // 0x7f
+#define SRSHARP1_PKOSHT_VSLUMA_LUT_L (SRSHARP1_OFFSET + SHARP_PKOSHT_VSLUMA_LUT_L ) // 0x80
+#define SRSHARP1_PKOSHT_VSLUMA_LUT_H (SRSHARP1_OFFSET + SHARP_PKOSHT_VSLUMA_LUT_H ) // 0x81
+#define SRSHARP1_SATPRT_LMT_RGB1 (SRSHARP1_OFFSET + SHARP_SATPRT_LMT_RGB1 ) // 0x82
+#define SRSHARP1_SATPRT_LMT_RGB2 (SRSHARP1_OFFSET + SHARP_SATPRT_LMT_RGB2 ) // 0x83
+#define SRSHARP1_SHARP_GATE_CLK_CTRL_0 (SRSHARP1_OFFSET + SHARP_GATE_CLK_CTRL_0 ) // 0x84
+#define SRSHARP1_SHARP_GATE_CLK_CTRL_1 (SRSHARP1_OFFSET + SHARP_GATE_CLK_CTRL_1 ) // 0x85
+#define SRSHARP1_SHARP_GATE_CLK_CTRL_2 (SRSHARP1_OFFSET + SHARP_GATE_CLK_CTRL_2 ) // 0x86
+#define SRSHARP1_SHARP_GATE_CLK_CTRL_3 (SRSHARP1_OFFSET + SHARP_GATE_CLK_CTRL_3 ) // 0x87
+#define SRSHARP1_SHARP_DPS_CTRL (SRSHARP1_OFFSET + SHARP_DPS_CTRL ) // 0x88
+#define SRSHARP1_DNLP_00 (SRSHARP1_OFFSET + DNLP_00 ) // 0x90 //
+#define SRSHARP1_DNLP_01 (SRSHARP1_OFFSET + DNLP_01 ) // 0x91 //
+#define SRSHARP1_DNLP_02 (SRSHARP1_OFFSET + DNLP_02 ) // 0x92 //
+#define SRSHARP1_DNLP_03 (SRSHARP1_OFFSET + DNLP_03 ) // 0x93 //
+#define SRSHARP1_DNLP_04 (SRSHARP1_OFFSET + DNLP_04 ) // 0x94 //
+#define SRSHARP1_DNLP_05 (SRSHARP1_OFFSET + DNLP_05 ) // 0x95 //
+#define SRSHARP1_DNLP_06 (SRSHARP1_OFFSET + DNLP_06 ) // 0x96 //
+#define SRSHARP1_DNLP_07 (SRSHARP1_OFFSET + DNLP_07 ) // 0x97 //
+#define SRSHARP1_DNLP_08 (SRSHARP1_OFFSET + DNLP_08 ) // 0x98 //
+#define SRSHARP1_DNLP_09 (SRSHARP1_OFFSET + DNLP_09 ) // 0x99 //
+#define SRSHARP1_DNLP_10 (SRSHARP1_OFFSET + DNLP_10 ) // 0x9a //
+#define SRSHARP1_DNLP_11 (SRSHARP1_OFFSET + DNLP_11 ) // 0x9b //
+#define SRSHARP1_DNLP_12 (SRSHARP1_OFFSET + DNLP_12 ) // 0x9c //
+#define SRSHARP1_DNLP_13 (SRSHARP1_OFFSET + DNLP_13 ) // 0x9d //
+#define SRSHARP1_DNLP_14 (SRSHARP1_OFFSET + DNLP_14 ) // 0x9e //
+#define SRSHARP1_DNLP_15 (SRSHARP1_OFFSET + DNLP_15 ) // 0x9f //
+#define SRSHARP1_DNLP_16 (SRSHARP1_OFFSET + DNLP_16 ) // 0xa0 //
+#define SRSHARP1_DNLP_17 (SRSHARP1_OFFSET + DNLP_17 ) // 0xa1 //
+#define SRSHARP1_DNLP_18 (SRSHARP1_OFFSET + DNLP_18 ) // 0xa2 //
+#define SRSHARP1_DNLP_19 (SRSHARP1_OFFSET + DNLP_19 ) // 0xa3 //
+#define SRSHARP1_DNLP_20 (SRSHARP1_OFFSET + DNLP_20 ) // 0xa4 //
+#define SRSHARP1_DNLP_21 (SRSHARP1_OFFSET + DNLP_21 ) // 0xa5 //
+#define SRSHARP1_DNLP_22 (SRSHARP1_OFFSET + DNLP_22 ) // 0xa6 //
+#define SRSHARP1_DNLP_23 (SRSHARP1_OFFSET + DNLP_23 ) // 0xa7 //
+#define SRSHARP1_DNLP_24 (SRSHARP1_OFFSET + DNLP_24 ) // 0xa8 //
+#define SRSHARP1_DNLP_25 (SRSHARP1_OFFSET + DNLP_25 ) // 0xa9 //
+#define SRSHARP1_DNLP_26 (SRSHARP1_OFFSET + DNLP_26 ) // 0xaa //
+#define SRSHARP1_DNLP_27 (SRSHARP1_OFFSET + DNLP_27 ) // 0xab //
+#define SRSHARP1_DNLP_28 (SRSHARP1_OFFSET + DNLP_28 ) // 0xac //
+#define SRSHARP1_DNLP_29 (SRSHARP1_OFFSET + DNLP_29 ) // 0xad //
+#define SRSHARP1_DNLP_30 (SRSHARP1_OFFSET + DNLP_30 ) // 0xae //
+#define SRSHARP1_DNLP_31 (SRSHARP1_OFFSET + DNLP_31 ) // 0xaf //
+#define SRSHARP1_SHARP_SYNC_CTRL (SRSHARP1_OFFSET + SHARP_SYNC_CTRL ) // 0xb0 //
+#define SRSHARP1_LC_INPUT_MUX (SRSHARP1_OFFSET + LC_INPUT_MUX ) // 0xb1 //
+#define SRSHARP1_NR_GAU_YH_COEF02 (SRSHARP1_OFFSET + NR_GAU_YH_COEF02 ) // 0xb2 //
+#define SRSHARP1_NR_GAU_YH_COEF34 (SRSHARP1_OFFSET + NR_GAU_YH_COEF34 ) // 0xb3 //
+#define SRSHARP1_NR_GAU_YV_COEF1 (SRSHARP1_OFFSET + NR_GAU_YV_COEF1 ) // 0xb4 //
+#define SRSHARP1_NR_GAU_CH_COEF02 (SRSHARP1_OFFSET + NR_GAU_CH_COEF02 ) // 0xb5 //
+#define SRSHARP1_NR_GAU_CH_COEF34 (SRSHARP1_OFFSET + NR_GAU_CH_COEF34 ) // 0xb6 //
+#define SRSHARP1_NR_GAU_CV_COEF1 (SRSHARP1_OFFSET + NR_GAU_CV_COEF1 ) // 0xb7 //
+#define SRSHARP1_LC_TOP_CTRL (SRSHARP1_OFFSET + LC_TOP_CTRL ) // 0xc0 //
+#define SRSHARP1_LC_HV_NUM (SRSHARP1_OFFSET + LC_HV_NUM ) // 0xc1
+#define SRSHARP1_LC_SAT_LUT_0_1 (SRSHARP1_OFFSET + LC_SAT_LUT_0_1 ) // 0xc2
+#define SRSHARP1_LC_SAT_LUT_2_3 (SRSHARP1_OFFSET + LC_SAT_LUT_2_3 ) // 0xc3
+#define SRSHARP1_LC_SAT_LUT_4_5 (SRSHARP1_OFFSET + LC_SAT_LUT_4_5 ) // 0xc4
+#define SRSHARP1_LC_SAT_LUT_6_7 (SRSHARP1_OFFSET + LC_SAT_LUT_6_7 ) // 0xc5
+#define SRSHARP1_LC_SAT_LUT_8_9 (SRSHARP1_OFFSET + LC_SAT_LUT_8_9 ) // 0xc6
+#define SRSHARP1_LC_SAT_LUT_10_11 (SRSHARP1_OFFSET + LC_SAT_LUT_10_11 ) // 0xc7
+#define SRSHARP1_LC_SAT_LUT_12_13 (SRSHARP1_OFFSET + LC_SAT_LUT_12_13 ) // 0xc8
+#define SRSHARP1_LC_SAT_LUT_14_15 (SRSHARP1_OFFSET + LC_SAT_LUT_14_15 ) // 0xc9
+#define SRSHARP1_LC_SAT_LUT_16_17 (SRSHARP1_OFFSET + LC_SAT_LUT_16_17 ) // 0xca
+#define SRSHARP1_LC_SAT_LUT_18_19 (SRSHARP1_OFFSET + LC_SAT_LUT_18_19 ) // 0xcb
+#define SRSHARP1_LC_SAT_LUT_20_21 (SRSHARP1_OFFSET + LC_SAT_LUT_20_21 ) // 0xcc
+#define SRSHARP1_LC_SAT_LUT_22_23 (SRSHARP1_OFFSET + LC_SAT_LUT_22_23 ) // 0xcd
+#define SRSHARP1_LC_SAT_LUT_24_25 (SRSHARP1_OFFSET + LC_SAT_LUT_24_25 ) // 0xce
+#define SRSHARP1_LC_SAT_LUT_26_27 (SRSHARP1_OFFSET + LC_SAT_LUT_26_27 ) // 0xcf
+#define SRSHARP1_LC_SAT_LUT_28_29 (SRSHARP1_OFFSET + LC_SAT_LUT_28_29 ) // 0xd0
+#define SRSHARP1_LC_SAT_LUT_30_31 (SRSHARP1_OFFSET + LC_SAT_LUT_30_31 ) // 0xd1
+#define SRSHARP1_LC_SAT_LUT_32_33 (SRSHARP1_OFFSET + LC_SAT_LUT_32_33 ) // 0xd2
+#define SRSHARP1_LC_SAT_LUT_34_35 (SRSHARP1_OFFSET + LC_SAT_LUT_34_35 ) // 0xd3
+#define SRSHARP1_LC_SAT_LUT_36_37 (SRSHARP1_OFFSET + LC_SAT_LUT_36_37 ) // 0xd4
+#define SRSHARP1_LC_SAT_LUT_38_39 (SRSHARP1_OFFSET + LC_SAT_LUT_38_39 ) // 0xd5
+#define SRSHARP1_LC_SAT_LUT_40_41 (SRSHARP1_OFFSET + LC_SAT_LUT_40_41 ) // 0xd6
+#define SRSHARP1_LC_SAT_LUT_42_43 (SRSHARP1_OFFSET + LC_SAT_LUT_42_43 ) // 0xd7
+#define SRSHARP1_LC_SAT_LUT_44_45 (SRSHARP1_OFFSET + LC_SAT_LUT_44_45 ) // 0xd8
+#define SRSHARP1_LC_SAT_LUT_46_47 (SRSHARP1_OFFSET + LC_SAT_LUT_46_47 ) // 0xd9
+#define SRSHARP1_LC_SAT_LUT_48_49 (SRSHARP1_OFFSET + LC_SAT_LUT_48_49 ) // 0xda
+#define SRSHARP1_LC_SAT_LUT_50_51 (SRSHARP1_OFFSET + LC_SAT_LUT_50_51 ) // 0xdb
+#define SRSHARP1_LC_SAT_LUT_52_53 (SRSHARP1_OFFSET + LC_SAT_LUT_52_53 ) // 0xdc
+#define SRSHARP1_LC_SAT_LUT_54_55 (SRSHARP1_OFFSET + LC_SAT_LUT_54_55 ) // 0xdd
+#define SRSHARP1_LC_SAT_LUT_56_57 (SRSHARP1_OFFSET + LC_SAT_LUT_56_57 ) // 0xde
+#define SRSHARP1_LC_SAT_LUT_58_59 (SRSHARP1_OFFSET + LC_SAT_LUT_58_59 ) // 0xdf
+#define SRSHARP1_LC_SAT_LUT_60_61 (SRSHARP1_OFFSET + LC_SAT_LUT_60_61 ) // 0xe0
+#define SRSHARP1_LC_SAT_LUT_62 (SRSHARP1_OFFSET + LC_SAT_LUT_62 ) // 0xe1
+#define SRSHARP1_LC_CURVE_BLK_HIDX_0_1 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_0_1 ) // 0xe2
+#define SRSHARP1_LC_CURVE_BLK_HIDX_2_3 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_2_3 ) // 0xe3
+#define SRSHARP1_LC_CURVE_BLK_HIDX_4_5 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_4_5 ) // 0xe4
+#define SRSHARP1_LC_CURVE_BLK_HIDX_6_7 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_6_7 ) // 0xe5
+#define SRSHARP1_LC_CURVE_BLK_HIDX_8_9 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_8_9 ) // 0xe6
+#define SRSHARP1_LC_CURVE_BLK_HIDX_10_11 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_10_11 ) // 0xe7
+#define SRSHARP1_LC_CURVE_BLK_HIDX_12 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_12 ) // 0xe8
+#define SRSHARP1_LC_CURVE_BLK_VIDX_0_1 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_0_1 ) // 0xe9
+#define SRSHARP1_LC_CURVE_BLK_VIDX_2_3 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_2_3 ) // 0xea
+#define SRSHARP1_LC_CURVE_BLK_VIDX_4_5 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_4_5 ) // 0xeb
+#define SRSHARP1_LC_CURVE_BLK_VIDX_6_7 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_6_7 ) // 0xec
+#define SRSHARP1_LC_CURVE_BLK_VIDX_8 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_8 ) // 0xed
+#define SRSHARP1_LC_YUV2RGB_MAT_0_1 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_0_1 ) // 0xee
+#define SRSHARP1_LC_YUV2RGB_MAT_2_3 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_2_3 ) // 0xef
+#define SRSHARP1_LC_YUV2RGB_MAT_4_5 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_4_5 ) // 0xf0
+#define SRSHARP1_LC_YUV2RGB_MAT_6_7 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_6_7 ) // 0xf1
+#define SRSHARP1_LC_YUV2RGB_MAT_8 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_8 ) // 0xf2
+#define SRSHARP1_LC_RGB2YUV_MAT_0_1 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_0_1 ) // 0xf3
+#define SRSHARP1_LC_RGB2YUV_MAT_2_3 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_2_3 ) // 0xf4
+#define SRSHARP1_LC_RGB2YUV_MAT_4_5 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_4_5 ) // 0xf5
+#define SRSHARP1_LC_RGB2YUV_MAT_6_7 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_6_7 ) // 0xf6
+#define SRSHARP1_LC_RGB2YUV_MAT_8 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_8 ) // 0xf7
+#define SRSHARP1_LC_YUV2RGB_OFST (SRSHARP1_OFFSET + LC_YUV2RGB_OFST ) // 0xf8
+#define SRSHARP1_LC_YUV2RGB_CLIP (SRSHARP1_OFFSET + LC_YUV2RGB_CLIP ) // 0xf9
+#define SRSHARP1_LC_RGB2YUV_OFST (SRSHARP1_OFFSET + LC_RGB2YUV_OFST ) // 0xfa
+#define SRSHARP1_LC_RGB2YUV_CLIP (SRSHARP1_OFFSET + LC_RGB2YUV_CLIP ) // 0xfb
+#define SRSHARP1_LC_MAP_RAM_CTRL (SRSHARP1_OFFSET + LC_MAP_RAM_CTRL ) // 0xfc
+#define SRSHARP1_LC_MAP_RAM_ADDR (SRSHARP1_OFFSET + LC_MAP_RAM_ADDR ) // 0xfd
+#define SRSHARP1_LC_MAP_RAM_DATA (SRSHARP1_OFFSET + LC_MAP_RAM_DATA ) // 0xfe
+
+#define SRSHARP1_FMETER_CTRL (SRSHARP1_OFFSET + SHARP_FMETER_CTRL ) // 0x89
+#define SRSHARP1_FMETER_WIN_HOR (SRSHARP1_OFFSET + SHARP_FMETER_WIN_HOR ) // 0x8a
+#define SRSHARP1_FMETER_WIN_VER (SRSHARP1_OFFSET + SHARP_FMETER_WIN_VER ) // 0x8b
+#define SRSHARP1_FMETER_CORING (SRSHARP1_OFFSET + SHARP_FMETER_CORING ) // 0x8c
+#define SRSHARP1_FMETER_RATIO_H (SRSHARP1_OFFSET + SHARP_FMETER_RATIO_H ) // 0x8d
+#define SRSHARP1_FMETER_RATIO_V (SRSHARP1_OFFSET + SHARP_FMETER_RATIO_V ) // 0x8e
+#define SRSHARP1_FMETER_RATIO_D (SRSHARP1_OFFSET + SHARP_FMETER_RATIO_D ) // 0x8f
+#define SRSHARP1_RO_FMETER_HCNT_TYPE0 (SRSHARP1_OFFSET + SHARP_RO_FMETER_HCNT_TYPE0 ) // 0x46
+#define SRSHARP1_RO_FMETER_HCNT_TYPE1 (SRSHARP1_OFFSET + SHARP_RO_FMETER_HCNT_TYPE1 ) // 0x47
+#define SRSHARP1_RO_FMETER_HCNT_TYPE2 (SRSHARP1_OFFSET + SHARP_RO_FMETER_HCNT_TYPE2 ) // 0x48
+#define SRSHARP1_RO_FMETER_HCNT_TYPE3 (SRSHARP1_OFFSET + SHARP_RO_FMETER_HCNT_TYPE3 ) // 0x49
+#define SRSHARP1_RO_FMETER_VCNT_TYPE0 (SRSHARP1_OFFSET + SHARP_RO_FMETER_VCNT_TYPE0 ) // 0x4a
+#define SRSHARP1_RO_FMETER_VCNT_TYPE1 (SRSHARP1_OFFSET + SHARP_RO_FMETER_VCNT_TYPE1 ) // 0x4b
+#define SRSHARP1_RO_FMETER_VCNT_TYPE2 (SRSHARP1_OFFSET + SHARP_RO_FMETER_VCNT_TYPE2 ) // 0x4c
+#define SRSHARP1_RO_FMETER_VCNT_TYPE3 (SRSHARP1_OFFSET + SHARP_RO_FMETER_VCNT_TYPE3 ) // 0x4d
+#define SRSHARP1_RO_FMETER_PDCNT_TYPE0 (SRSHARP1_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE0 ) // 0x4e
+#define SRSHARP1_RO_FMETER_PDCNT_TYPE1 (SRSHARP1_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE1 ) // 0x4f
+#define SRSHARP1_RO_FMETER_PDCNT_TYPE2 (SRSHARP1_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE2 ) // 0x50
+#define SRSHARP1_RO_FMETER_PDCNT_TYPE3 (SRSHARP1_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE3 ) // 0x51
+#define SRSHARP1_RO_FMETER_NDCNT_TYPE0 (SRSHARP1_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE0 ) // 0x52
+#define SRSHARP1_RO_FMETER_NDCNT_TYPE1 (SRSHARP1_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE1 ) // 0x53
+#define SRSHARP1_RO_FMETER_NDCNT_TYPE2 (SRSHARP1_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE2 ) // 0x54
+#define SRSHARP1_RO_FMETER_NDCNT_TYPE3 (SRSHARP1_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE3 ) // 0x55
+
+
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: srsharp_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: VPPE_VCBUS_BASE = 0x51
+// -----------------------------------------------
+// 8'h50/51/52/53 have used for srsharp_regs
+//
+// Reading file: srsharp_regs2.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//SRSHARP0 8'h00 - 8'hff
+//SRSHARP1 8'h100 - 8'1ff
+#define SRSHARP0_OFFSET (0x000<<2)
+#define SRSHARP1_OFFSET (0x200<<2)
+
+//
+// Reading file: sharp_regs2.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define SR7_DRTLPF_EN ((0x5100 << 2) + 0xff000000)
+//Bit 31:11, reserved
+//Bit 10, reg_sr7_drtlpf_beta_en2 : enable of direction ambiguity protection for drt_lpf, beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), 0, equivalent beta[i]=15, 1, enable. unsigned , default = 0
+//Bit 9, reg_sr7_drtlpf_beta_en1 : enable of direction ambiguity protection for drt_lpf, beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), 0, equivalent beta[i]=15, 1, enable. unsigned , default = 0
+//Bit 8, reg_sr7_drtlpf_beta_en0 : enable of direction ambiguity protection for drt_lpf, beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), 0, equivalent beta[i]=15, 1, enable. unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5, reg_sr7_drtlpf_edge_en2 : enable of direction lpf based on edge strength. unsigned , default = 0
+//Bit 4, reg_sr7_drtlpf_edge_en1 : enable of direction lpf based on edge strength. unsigned , default = 0
+//Bit 3, reg_sr7_drtlpf_edge_en0 : enable of direction lpf based on edge strength. unsigned , default = 0
+//Bit 2, reg_sr7_drtlpf_sdfd_en2 : sdfd gamma (HF burst compare to real edge protection) enable. 0: not enable, 1:enable protection. unsigned , default = 1
+//Bit 1, reg_sr7_drtlpf_sdfd_en1 : sdfd gamma (HF burst compare to real edge protection) enable. 0: not enable, 1:enable protection. unsigned , default = 1
+//Bit 0, reg_sr7_drtlpf_sdfd_en0 : sdfd gamma (HF burst compare to real edge protection) enable. 0: not enable, 1:enable protection. unsigned , default = 1
+#define SR7_DRTLPF_BETA ((0x5101 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_drtlpf_beta3 : beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo lpf. unsigned , default = 0
+//Bit 11: 8, reg_sr7_drtlpf_beta2 : beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo lpf. unsigned , default = 4
+//Bit 7: 4, reg_sr7_drtlpf_beta1 : beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo lpf. unsigned , default = 8
+//Bit 3: 0, reg_sr7_drtlpf_beta0 : beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo lpf. unsigned , default = 15
+#define SR7_PKBLD_BETA ((0x5102 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_pkdrtbld_beta3 : beta for drt and cir blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use cir wo drt. unsigned , default = 0
+//Bit 11: 8, reg_sr7_pkdrtbld_beta2 : beta for drt and cir blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use cir wo drt. unsigned , default = 4
+//Bit 7: 4, reg_sr7_pkdrtbld_beta1 : beta for drt and cir blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use cir wo drt. unsigned , default = 8
+//Bit 3: 0, reg_sr7_pkdrtbld_beta0 : beta for drt and cir blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use cir wo drt. unsigned , default = 15
+#define SR7_XLTIBLD_BETA ((0x5103 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_xlti_dcbld_beta3 : beta for denoise and org dc blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 0
+//Bit 11: 8, reg_sr7_xlti_dcbld_beta2 : beta for denoise and org dc blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 4
+//Bit 7: 4, reg_sr7_xlti_dcbld_beta1 : beta for denoise and org dc blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 8
+//Bit 3: 0, reg_sr7_xlti_dcbld_beta0 : beta for denoise and org dc blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 15
+#define SR7_DRTLPF_EDGE0 ((0x5104 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_drtlpf_edge7 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_drtlpf_edge6 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_drtlpf_edge5 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_drtlpf_edge4 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_drtlpf_edge3 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_drtlpf_edge2 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_drtlpf_edge1 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_drtlpf_edge0 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+#define SR7_DRTLPF_EDGE1 ((0x5105 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_drtlpf_edge15 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_drtlpf_edge14 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_drtlpf_edge13 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_drtlpf_edge12 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_drtlpf_edge11 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_drtlpf_edge10 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_drtlpf_edge9 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_drtlpf_edge8 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+#define SR7_DRTLPF_SDCOR0 ((0x5106 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_drtlpf_sdcor7 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_drtlpf_sdcor6 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_drtlpf_sdcor5 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_drtlpf_sdcor4 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_drtlpf_sdcor3 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_drtlpf_sdcor2 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_drtlpf_sdcor1 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_drtlpf_sdcor0 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+#define SR7_DRTLPF_SDCOR1 ((0x5107 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_drtlpf_sdcor15 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_drtlpf_sdcor14 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_drtlpf_sdcor13 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_drtlpf_sdcor12 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_drtlpf_sdcor11 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_drtlpf_sdcor10 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_drtlpf_sdcor9 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_drtlpf_sdcor8 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+#define SR7_CTIGAIN_SDCOR0 ((0x5108 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_ctigain_sdcor7 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_ctigain_sdcor6 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_ctigain_sdcor5 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_ctigain_sdcor4 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_ctigain_sdcor3 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_ctigain_sdcor2 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_ctigain_sdcor1 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_ctigain_sdcor0 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+#define SR7_CTIGAIN_SDCOR1 ((0x5109 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_ctigain_sdcor15 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_ctigain_sdcor14 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_ctigain_sdcor13 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_ctigain_sdcor12 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_ctigain_sdcor11 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_ctigain_sdcor10 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_ctigain_sdcor9 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_ctigain_sdcor8 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+#define SR7_LTIGAIN_SDCOR0 ((0x510a << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_ltigain_sdcor7 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_ltigain_sdcor6 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_ltigain_sdcor5 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_ltigain_sdcor4 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_ltigain_sdcor3 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_ltigain_sdcor2 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_ltigain_sdcor1 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_ltigain_sdcor0 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+#define SR7_LTIGAIN_SDCOR1 ((0x510b << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_ltigain_sdcor15 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_ltigain_sdcor14 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_ltigain_sdcor13 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_ltigain_sdcor12 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_ltigain_sdcor11 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_ltigain_sdcor10 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_ltigain_sdcor9 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_ltigain_sdcor8 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+#define SR7_HLTIBPF_TAP0 ((0x510c << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_hlti_bpf_tap153 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0
+//Bit 23:16, reg_sr7_hlti_bpf_tap152 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -34
+//Bit 15: 8, reg_sr7_hlti_bpf_tap151 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -1
+//Bit 7: 0, reg_sr7_hlti_bpf_tap150 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 120
+#define SR7_HLTIBPF_TAP1 ((0x510d << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_hlti_bpf_tap157 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 2
+//Bit 23:16, reg_sr7_hlti_bpf_tap156 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -7
+//Bit 15: 8, reg_sr7_hlti_bpf_tap155 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 1
+//Bit 7: 0, reg_sr7_hlti_bpf_tap154 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -21
+#define SR7_HCTIBPF_TAP0 ((0x510e << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_hcti_bpf_tap153 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0
+//Bit 23:16, reg_sr7_hcti_bpf_tap152 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -34
+//Bit 15: 8, reg_sr7_hcti_bpf_tap151 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -1
+//Bit 7: 0, reg_sr7_hcti_bpf_tap150 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 120
+#define SR7_HCTIBPF_TAP1 ((0x510f << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_hcti_bpf_tap157 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 2
+//Bit 23:16, reg_sr7_hcti_bpf_tap156 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -7
+//Bit 15: 8, reg_sr7_hcti_bpf_tap155 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 1
+//Bit 7: 0, reg_sr7_hcti_bpf_tap154 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -21
+#define SR7_PKLONGBPF_HTAP0 ((0x5110 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_bpf_hztap153 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -24
+//Bit 23:16, reg_sr7_pk_long_bpf_hztap152 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -19
+//Bit 15: 8, reg_sr7_pk_long_bpf_hztap151 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 31
+//Bit 7: 0, reg_sr7_pk_long_bpf_hztap150 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 66
+#define SR7_PKLONGBPF_HTAP1 ((0x5111 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_bpf_hztap157 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -6
+//Bit 23:16, reg_sr7_pk_long_bpf_hztap156 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -10
+//Bit 15: 8, reg_sr7_pk_long_bpf_hztap155 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -1
+//Bit 7: 0, reg_sr7_pk_long_bpf_hztap154 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -4
+#define SR7_PKLONGHPF_HTAP0 ((0x5112 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_hpf_hztap153 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 27
+//Bit 23:16, reg_sr7_pk_long_hpf_hztap152 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -15
+//Bit 15: 8, reg_sr7_pk_long_hpf_hztap151 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -32
+//Bit 7: 0, reg_sr7_pk_long_hpf_hztap150 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 58
+#define SR7_PKLONGHPF_HTAP1 ((0x5113 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_hpf_hztap157 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 8
+//Bit 23:16, reg_sr7_pk_long_hpf_hztap156 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -6
+//Bit 15: 8, reg_sr7_pk_long_hpf_hztap155 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -1
+//Bit 7: 0, reg_sr7_pk_long_hpf_hztap154 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -10
+#define SR7_VLTIBPF_TAP0 ((0x5114 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_vlti_bpf_tap093 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0
+//Bit 23:16, reg_sr7_vlti_bpf_tap092 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -41
+//Bit 15: 8, reg_sr7_vlti_bpf_tap091 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0
+//Bit 7: 0, reg_sr7_vlti_bpf_tap090 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 126
+#define SR7_VLTIBPF_TAP1 ((0x5115 << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_sr7_vlti_bpf_tap094 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -22
+#define SR7_VCTIBPF_TAP0 ((0x5116 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_vcti_bpf_tap093 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0
+//Bit 23:16, reg_sr7_vcti_bpf_tap092 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -41
+//Bit 15: 8, reg_sr7_vcti_bpf_tap091 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0
+//Bit 7: 0, reg_sr7_vcti_bpf_tap090 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 126
+#define SR7_VCTIBPF_TAP1 ((0x5117 << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_sr7_vcti_bpf_tap094 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -22
+#define SR7_PKLONGBPF_VTAP0 ((0x5118 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_bpf_vdtap093 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -32
+//Bit 23:16, reg_sr7_pk_long_bpf_vdtap092 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -28
+//Bit 15: 8, reg_sr7_pk_long_bpf_vdtap091 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 30
+//Bit 7: 0, reg_sr7_pk_long_bpf_vdtap090 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 68
+#define SR7_PKLONGBPF_VTAP1 ((0x5119 << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_sr7_pk_long_bpf_vdtap094 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -4
+#define SR7_PKLONGHPF_VTAP0 ((0x511a << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_hpf_vdtap093 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 30
+//Bit 23:16, reg_sr7_pk_long_hpf_vdtap092 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -28
+//Bit 15: 8, reg_sr7_pk_long_hpf_vdtap091 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -31
+//Bit 7: 0, reg_sr7_pk_long_hpf_vdtap090 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 68
+#define SR7_PKLONGHPF_VTAP1 ((0x511b << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_sr7_pk_long_hpf_vdtap094 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -5
+#define SR7_CIRBPLONG_ALP ((0x511c << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_cirbp_long_alpha3 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+//Bit 11: 8, reg_sr7_cirbp_long_alpha2 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+//Bit 7: 4, reg_sr7_cirbp_long_alpha1 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+//Bit 3: 0, reg_sr7_cirbp_long_alpha0 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+#define SR7_CIRHPLONG_ALP ((0x511d << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_cirhp_long_alpha3 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+//Bit 11: 8, reg_sr7_cirhp_long_alpha2 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+//Bit 7: 4, reg_sr7_cirhp_long_alpha1 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+//Bit 3: 0, reg_sr7_cirhp_long_alpha0 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+#define SR7_DRTBPLONG_ALP ((0x511e << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_drtbp_long_alpha7 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 27:24, reg_sr7_drtbp_long_alpha6 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 23:20, reg_sr7_drtbp_long_alpha5 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 19:16, reg_sr7_drtbp_long_alpha4 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 15:12, reg_sr7_drtbp_long_alpha3 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 11: 8, reg_sr7_drtbp_long_alpha2 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 7: 4, reg_sr7_drtbp_long_alpha1 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 3: 0, reg_sr7_drtbp_long_alpha0 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+#define SR7_DRTHPLONG_ALP ((0x511f << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_drthp_long_alpha7 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 27:24, reg_sr7_drthp_long_alpha6 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 23:20, reg_sr7_drthp_long_alpha5 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 19:16, reg_sr7_drthp_long_alpha4 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 15:12, reg_sr7_drthp_long_alpha3 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 11: 8, reg_sr7_drthp_long_alpha2 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 7: 4, reg_sr7_drthp_long_alpha1 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 3: 0, reg_sr7_drthp_long_alpha0 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+#define SR7_PKMINMAXCIR_BLD_LUT2D0 ((0x5120 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_cirbld_lut2d7 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0
+//Bit 27:24, reg_sr7_pk_mimaxerr2_cirbld_lut2d6 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0
+//Bit 23:20, reg_sr7_pk_mimaxerr2_cirbld_lut2d5 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 19:16, reg_sr7_pk_mimaxerr2_cirbld_lut2d4 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d3 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d2 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d1 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d0 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+#define SR7_PKMINMAXCIR_BLD_LUT2D1 ((0x5121 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_cirbld_lut2d15 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 27:24, reg_sr7_pk_mimaxerr2_cirbld_lut2d14 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0
+//Bit 23:20, reg_sr7_pk_mimaxerr2_cirbld_lut2d13 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 19:16, reg_sr7_pk_mimaxerr2_cirbld_lut2d12 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d11 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d10 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d9 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d8 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+#define SR7_PKMINMAXCIR_BLD_LUT2D2 ((0x5122 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_cirbld_lut2d23 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 27:24, reg_sr7_pk_mimaxerr2_cirbld_lut2d22 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 10
+//Bit 23:20, reg_sr7_pk_mimaxerr2_cirbld_lut2d21 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 19:16, reg_sr7_pk_mimaxerr2_cirbld_lut2d20 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d19 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d18 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d17 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d16 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12
+#define SR7_PKMINMAXCIR_BLD_LUT2D3 ((0x5123 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_cirbld_lut2d31 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 14
+//Bit 27:24, reg_sr7_pk_mimaxerr2_cirbld_lut2d30 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 23:20, reg_sr7_pk_mimaxerr2_cirbld_lut2d29 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 19:16, reg_sr7_pk_mimaxerr2_cirbld_lut2d28 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 8
+//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d27 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 10
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d26 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d25 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d24 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+#define SR7_PKMINMAXCIR_BLD_LUT2D4 ((0x5124 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d35 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d34 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d33 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d32 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12
+#define SR7_PKMINMAXLPF_BLD_LUT2D0 ((0x5125 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_lpfbld_lut2d7 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0
+//Bit 27:24, reg_sr7_pk_mimaxerr2_lpfbld_lut2d6 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0
+//Bit 23:20, reg_sr7_pk_mimaxerr2_lpfbld_lut2d5 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 19:16, reg_sr7_pk_mimaxerr2_lpfbld_lut2d4 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d3 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d2 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d1 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d0 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+#define SR7_PKMINMAXLPF_BLD_LUT2D1 ((0x5126 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_lpfbld_lut2d15 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 27:24, reg_sr7_pk_mimaxerr2_lpfbld_lut2d14 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0
+//Bit 23:20, reg_sr7_pk_mimaxerr2_lpfbld_lut2d13 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 19:16, reg_sr7_pk_mimaxerr2_lpfbld_lut2d12 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d11 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d10 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d9 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d8 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+#define SR7_PKMINMAXLPF_BLD_LUT2D2 ((0x5127 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_lpfbld_lut2d23 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 27:24, reg_sr7_pk_mimaxerr2_lpfbld_lut2d22 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 10
+//Bit 23:20, reg_sr7_pk_mimaxerr2_lpfbld_lut2d21 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 19:16, reg_sr7_pk_mimaxerr2_lpfbld_lut2d20 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d19 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d18 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d17 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d16 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12
+#define SR7_PKMINMAXLPF_BLD_LUT2D3 ((0x5128 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_lpfbld_lut2d31 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 14
+//Bit 27:24, reg_sr7_pk_mimaxerr2_lpfbld_lut2d30 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 23:20, reg_sr7_pk_mimaxerr2_lpfbld_lut2d29 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 19:16, reg_sr7_pk_mimaxerr2_lpfbld_lut2d28 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 8
+//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d27 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 10
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d26 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d25 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d24 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+#define SR7_PKMINMAXLPF_BLD_LUT2D4 ((0x5129 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d35 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d34 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d33 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d32 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12
+#define SR7_PKDRT_BLD_EN ((0x512a << 2) + 0xff000000)
+//Bit 31: 1, reserved
+//Bit 0, reg_sr7_pkdrtbld_beta_en : enable of direction ambiguity protection for drt and cir blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 0
+#define SR7_DRTDIF_TH ((0x512b << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_sr7_drtdif_min2sad_th1 : for min2_sad threshold for ambiguilty ignoring, if (min_sad<min2_sad/2 && min2_sad>thrd) drt_dif=1;. unsigned , default = 128
+//Bit 7: 0, reg_sr7_drtdif_min2sad_th0 : for min2_sad threshold for ambiguilty ignoring, if (min_sad<min2_sad/2 && min2_sad>thrd) drt_dif=1;. unsigned , default = 128
+#define SR7_TIBLD_PRT ((0x512c << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13, reg_sr7_hlti_dcbld_beta_en : enable of denoise protection for dc org and denoise blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 1
+//Bit 12, reg_sr7_vlti_dcbld_beta_en : enable of denoise protection for dc org and denoise blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 1
+//Bit 11: 8, reg_sr7_xcti_dcbld_beta1 : beta for denoise and org dc blend base on the x=cal_drt_dif4(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 0
+//Bit 7: 4, reg_sr7_xcti_dcbld_beta0 : beta for denoise and org dc blend base on the x=cal_drt_dif4(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 15
+//Bit 3, reg_sr7_hcti_dcbld_beta_en : enable of denoise protection for dc org and denoise blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 1
+//Bit 2, reg_sr7_vcti_dcbld_beta_en : enable of denoise protection for dc org and denoise blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 1
+//Bit 1, reg_sr7_hcti_dcbld_use_ybeta : enable to use beta from hlti, 0, use c-beta, 1, use y-beta. unsigned , default = 0
+//Bit 0, reg_sr7_vcti_dcbld_use_ybeta : enable to use beta from vlti, 0, use c-beta, 1, use y-beta. unsigned , default = 0
+#define SR7_HTI_OPT_FORCE ((0x512d << 2) + 0xff000000)
+//Bit 31: 6, reserved
+//Bit 5, reg_sr7_diag_force_hti1 : force hti for diagonal edges luma/chroma, 0: diagonal use vti, 1: diagonal use hti, default=1. unsigned , default = 1
+//Bit 4, reg_sr7_diag_force_hti0 : force hti for diagonal edges luma/chroma, 0: diagonal use vti, 1: diagonal use hti, default=1. unsigned , default = 1
+//Bit 3, reg_sr7_horz_force_vti1 : force vti for horizontal edges luma/chroma, 0: bias hti, 1: horizontal edge force 100% vti, default=1. unsigned , default = 1
+//Bit 2, reg_sr7_horz_force_vti0 : force vti for horizontal edges luma/chroma, 0: bias hti, 1: horizontal edge force 100% vti, default=1. unsigned , default = 1
+//Bit 1, reg_sr7_alph_force_hvsad1 : alpha = minsad*64/maxsad, force minsad=sad_h, maxsad=sad_v for alpha calculation, [0]for luma, [1] for chroma. if sad_h>sad_v alpha will be large, default=1. unsigned , default = 1
+//Bit 0, reg_sr7_alph_force_hvsad0 : alpha = minsad*64/maxsad, force minsad=sad_h, maxsad=sad_v for alpha calculation, [0]for luma, [1] for chroma. if sad_h>sad_v alpha will be large, default=1. unsigned , default = 1
+#define SR7_HVTI_FINALGAIN ((0x512e << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, reg_sr7_hvti_finalgain1 : final gain for HVTI boost, for easier level tunning for application, normalized to 256 as 1.0 default = 256. unsigned , default = 256
+//Bit 15:12, reserved
+//Bit 11: 0, reg_sr7_hvti_finalgain0 : final gain for HVTI boost, for easier level tunning for application, normalized to 256 as 1.0 default = 256. unsigned , default = 256
+#define SR7_TIOS_SDRATIO ((0x512f << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_sr7_hti_osmargin_sdratio1 : ratio for HTI OS margin adaptive to sd. osmargin= (sd*ratio)>>6; default=3. unsigned , default = 3
+//Bit 23:22, reserved
+//Bit 21:16, reg_sr7_hti_osmargin_sdratio0 : ratio for HTI OS margin adaptive to sd. osmargin= (sd*ratio)>>6; default=3. unsigned , default = 3
+//Bit 15:14, reserved
+//Bit 13: 8, reg_sr7_vti_osmargin_sdratio1 : ratio for VTI OS margin adaptive to sd. osmargin= (sd*ratio)>>6; default=3. unsigned , default = 3
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_sr7_vti_osmargin_sdratio0 : ratio for VTI OS margin adaptive to sd. osmargin= (sd*ratio)>>6; default=3. unsigned , default = 3
+#define SR7_XTI_SDFDEN ((0x5130 << 2) + 0xff000000)
+//Bit 31: 2, reserved
+//Bit 1, reg_sr7_xtigain_sdfd_en1 : adaptive gamma for cti boost gain enable.[0]for luma, [1] for chroma. 0: not enable, 1:enable, default = 1. unsigned , default = 1
+//Bit 0, reg_sr7_xtigain_sdfd_en0 : adaptive gamma for cti boost gain enable.[0]for luma, [1] for chroma. 0: not enable, 1:enable, default = 1. unsigned , default = 1
+#define SR7_FDSD_PARAM ((0x5131 << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25, reg_fdsd_vlpf_en : use vertical [1 2 1] lpf filter for the fd and sd derivativecalculations. unsigned , default = 1
+//Bit 24, reg_fdsd_hlpf_en : use horizontal [1 2 1] lpf filter for the fd and sd derivativecalculations. unsigned , default = 1
+//Bit 23:20, reg_sd_coring_th1 : coring to SD'= MAX(SD - FD*ratio - coring,0); default = 0. unsigned , default = 0
+//Bit 19:16, reg_sd_coring_th0 : coring to SD'= MAX(SD - FD*ratio - coring,0); default = 0. unsigned , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_sd_coring_ratio2fd1 : ratio to FD for adaptive coring to SD'= MAX(SD - FD*ratio - coring,0); normalized 64 as 1.0 default = 4. unsigned , default = 4
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_sd_coring_ratio2fd0 : ratio to FD for adaptive coring to SD'= MAX(SD - FD*ratio - coring,0); normalized 64 as 1.0 default = 4. unsigned , default = 4
+#define SR7_TI_BPF_EN ((0x5132 << 2) + 0xff000000)
+//Bit 31: 4, reserved
+//Bit 3, reg_sr7_hlti_bpf_en : enable of tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. unsigned , default = 1
+//Bit 2, reg_sr7_hcti_bpf_en : enable of tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. unsigned , default = 1
+//Bit 1, reg_sr7_vlti_bpf_en : enable of tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0, mainly for 2x2 UP case. unsigned , default = 1
+//Bit 0, reg_sr7_vcti_bpf_en : enable of tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0, mainly for 2x2 UP case. unsigned , default = 1
+#define SR7_PKLONG_PF_EN ((0x5133 << 2) + 0xff000000)
+//Bit 31: 2, reserved
+//Bit 1, reg_sr7_pk_long_bpf_en : enable of long BPF for peaking only store half of the filter normalized to 258 as 1.0. unsigned , default = 1
+//Bit 0, reg_sr7_pk_long_hpf_en : enable of long HPF for peaking only store half of the filter normalized to 258 as 1.0. unsigned , default = 1
+#define SR7_PKLONG_PF_GAIN ((0x5134 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_bpf_hzgain : gain to long horizontal BPF for peaking, normalized to 64 as 1.0. unsigned , default = 64
+//Bit 23:16, reg_sr7_pk_long_bpf_vdgain : gain to long vertical and diagonal BPF for peaking, normalized to 64 as 1.0. unsigned , default = 64
+//Bit 15: 8, reg_sr7_pk_long_hpf_hzgain : gain to long horizontal HPF for peaking, normalized to 64 as 1.0. unsigned , default = 64
+//Bit 7: 0, reg_sr7_pk_long_hpf_vdgain : gain to long vertical and diagonal HPF for peaking, normalized to 64 as 1.0. unsigned , default = 64
+#define SR7_PKMINMAX_BLD ((0x5135 << 2) + 0xff000000)
+//Bit 31: 4, reserved
+//Bit 3, reg_sr7_pk_mimaxerr2_cirbld_on_bp : enable to use adaptive blender of drtBP vs cirBP alpha2, the larger of cell, the more cirPK results, 0: alp2=lut2d(minerr, maxerr),1:alp2=min_err/maxerr,default = 1. unsigned , default = 1
+//Bit 2, reg_sr7_pk_mimaxerr2_cirbld_on_hp : enable to use adaptive blender of drtHP vs cirHP alpha2, the larger of cell, the more cirPK results, 0: alp2=lut2d(minerr, maxerr),1:alp2=min_err/maxerr,default = 1. unsigned , default = 1
+//Bit 1, reg_sr7_pk_mimaxerr2_lpfbld_on_bp : enable to use adaptive blender of BP result lpf along edge based on the mimaxsad relationship, default = 1. unsigned , default = 1
+//Bit 0, reg_sr7_pk_mimaxerr2_lpfbld_on_hp : enable to use adaptive blender of HP result lpf along edge based on the mimaxsad relationship, default = 1. unsigned , default = 1
+#define SR7_TI_CONMAXERR_GAIN ((0x5136 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_hti_conmaxerr_gain1 : con=max(con, maxerr) for the horizontal transition calculation, gain=0, same as s6 and prev, [0] for y and [1] for uv. unsigned , default = 8
+//Bit 11: 8, reg_sr7_hti_conmaxerr_gain0 : con=max(con, maxerr) for the horizontal transition calculation, gain=0, same as s6 and prev, [0] for y and [1] for uv. unsigned , default = 8
+//Bit 7: 4, reg_sr7_vti_conmaxerr_gain1 : con=max(con, maxerr) for the vertical transition calculation, gain=0, same as s6 and prev, [0] for y and [1] for uv. unsigned , default = 8
+//Bit 3: 0, reg_sr7_vti_conmaxerr_gain0 : con=max(con, maxerr) for the vertical transition calculation, gain=0, same as s6 and prev, [0] for y and [1] for uv. unsigned , default = 8
+#define SR7_CC_PK_ADJ ((0x5137 << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24, reg_sr7_cc_enable : color compensation enable, 0: no CC, 1: with CC, default = 1. unsigned , default = 1
+//Bit 23:22, reserved
+//Bit 21:20, reg_sr7_cc_yinp_sel : color compensation input luma selection, 0: org_y; 1: gau_y ; 2:gauadp_y; 3:edgeadp_y (same as dnlp input sel), default= 0. unsigned , default = 0
+//Bit 19:18, reg_sr7_cc_ydlt_sel : color compensation output luma selection, 0: peaking+lti output; 1: dnlp output; 2/3: peaking+lti+dnlp, default = 2. unsigned , default = 2
+//Bit 17:16, reg_sr7_cc_sat_norm : normalization of lut cell to saturation. 0: norm to 8 as 1.0, sat[0:23/8]; 1: norm to 16 as 1.0, sat[1/16:31/16]; 2: norm to 32 as 1.0, sat[17/32:47/32]; 3:norm to 64 as 1.0, sat[49/64:79/64]. unsigned , default = 1
+//Bit 15: 8, reg_sr7_cc_ydlt_pscl : prescale to the y-delta (if >0) before feeding to y-lumadlt, normalized 64 as 1.0. default = 64.. unsigned , default = 64
+//Bit 7: 0, reg_sr7_cc_ydlt_nscl : prescale to the y-delta (if <0) before feeding to y-lumadlt, normalized 64 as 1.0. default = 64.. unsigned , default = 64
+#define SR7_CC_LUT0 ((0x5138 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_cc_lut003 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=0, dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 27:24, reg_sr7_cc_lut002 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=0, dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 23:20, reg_sr7_cc_lut001 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=0, dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 19:16, reg_sr7_cc_lut000 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=0, dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 15:12, reg_sr7_cc_lut103 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=1/8 dft={1, 2, 4, 8}. unsigned , default = 8
+//Bit 11: 8, reg_sr7_cc_lut102 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=1/8 dft={1, 2, 4, 8}. unsigned , default = 4
+//Bit 7: 4, reg_sr7_cc_lut101 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=1/8 dft={1, 2, 4, 8}. unsigned , default = 2
+//Bit 3: 0, reg_sr7_cc_lut100 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=1/8 dft={1, 2, 4, 8}. unsigned , default = 1
+#define SR7_CC_LUT1 ((0x5139 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:24, reg_sr7_cc_lut202 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=2/8 dft={4, 8,12}. unsigned , default = 12
+//Bit 23:20, reg_sr7_cc_lut201 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=2/8 dft={4, 8,12}. unsigned , default = 8
+//Bit 19:16, reg_sr7_cc_lut200 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=2/8 dft={4, 8,12}. unsigned , default = 4
+//Bit 15:12, reserved
+//Bit 11: 8, reg_sr7_cc_lut302 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=3/8 dft={5,10,15}. unsigned , default = 15
+//Bit 7: 4, reg_sr7_cc_lut301 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=3/8 dft={5,10,15}. unsigned , default = 10
+//Bit 3: 0, reg_sr7_cc_lut300 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=3/8 dft={5,10,15}. unsigned , default = 5
+#define SR7_CC_LUT2 ((0x513a << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:20, reg_sr7_cc_lut401 : valid for y-lumadlt= 1/4, 1/2, ; of x-lumainput=4/8 dft={8,15}. unsigned , default = 15
+//Bit 19:16, reg_sr7_cc_lut400 : valid for y-lumadlt= 1/4, 1/2, ; of x-lumainput=4/8 dft={8,15}. unsigned , default = 8
+//Bit 15:12, reg_sr7_cc_lut501 : valid for y-lumadlt= 1/4, 1/2, ; of x-lumainput=5/8 dft={6,13}. unsigned , default = 13
+//Bit 11: 8, reg_sr7_cc_lut500 : valid for y-lumadlt= 1/4, 1/2, ; of x-lumainput=5/8 dft={6,13}. unsigned , default = 6
+//Bit 7: 4, reg_sr7_cc_lut600 : valid for y-lumadlt= 1/4, ; of x-lumainput=6/8 dft={5}. unsigned , default = 5
+//Bit 3: 0, reg_sr7_cc_lut700 : valid for y-lumadlt= 1/4, ; of x-lumainput=7/8 dft={4}. unsigned , default = 4
+#define SR7_CC_LUT3 ((0x513b << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:20, reg_sr7_cc_lut710 : valid for y-lumadlt= -1/4, ; of x-lumainput=1/8 dft={4}. unsigned , default = 4
+//Bit 19:16, reg_sr7_cc_lut610 : valid for y-lumadlt= -1/4, ; of x-lumainput=2/8 dft={5}. unsigned , default = 5
+//Bit 15:12, reg_sr7_cc_lut511 : valid for y-lumadlt= -1/4, -1/2, ; of x-lumainput=3/8 dft={6,13}. unsigned , default = 13
+//Bit 11: 8, reg_sr7_cc_lut510 : valid for y-lumadlt= -1/4, -1/2, ; of x-lumainput=3/8 dft={6,13}. unsigned , default = 6
+//Bit 7: 4, reg_sr7_cc_lut411 : valid for y-lumadlt= -1/4, -1/2, ; of x-lumainput=4/8 dft={8,15}. unsigned , default = 15
+//Bit 3: 0, reg_sr7_cc_lut410 : valid for y-lumadlt= -1/4, -1/2, ; of x-lumainput=4/8 dft={8,15}. unsigned , default = 8
+#define SR7_CC_LUT4 ((0x513c << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:20, reg_sr7_cc_lut312 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=5/8 dft={5,10,15}. unsigned , default = 15
+//Bit 19:16, reg_sr7_cc_lut311 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=5/8 dft={5,10,15}. unsigned , default = 10
+//Bit 15:12, reg_sr7_cc_lut310 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=5/8 dft={5,10,15}. unsigned , default = 5
+//Bit 11: 8, reg_sr7_cc_lut212 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=6/8 dft={4, 8,12}. unsigned , default = 12
+//Bit 7: 4, reg_sr7_cc_lut211 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=6/8 dft={4, 8,12}. unsigned , default = 8
+//Bit 3: 0, reg_sr7_cc_lut210 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=6/8 dft={4, 8,12}. unsigned , default = 4
+#define SR7_CC_LUT5 ((0x513d << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_cc_lut113 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=7/8 dft={1, 2, 4, 8}. unsigned , default = 8
+//Bit 27:24, reg_sr7_cc_lut112 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=7/8 dft={1, 2, 4, 8}. unsigned , default = 4
+//Bit 23:20, reg_sr7_cc_lut111 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=7/8 dft={1, 2, 4, 8}. unsigned , default = 2
+//Bit 19:16, reg_sr7_cc_lut110 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=7/8 dft={1, 2, 4, 8}. unsigned , default = 1
+//Bit 15:12, reg_sr7_cc_lut013 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=8/8 dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 11: 8, reg_sr7_cc_lut012 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=8/8 dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 7: 4, reg_sr7_cc_lut011 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=8/8 dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 3: 0, reg_sr7_cc_lut010 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=8/8 dft={0, 0, 0, 0}. unsigned , default = 0
+#define SR7_GRAPHIC_CTRL ((0x513e << 2) + 0xff000000)
+//Bit 31:11, reserved
+//Bit 10, reg_sr7_grph_en : enable graphic statistic . unsigned , default = 1
+//Bit 9, reg_sr7_grph_hflt : horizontal filter, 0: [0 1 -1], 1: [-1 2 -1]. unsigned , default = 1
+//Bit 8, reg_sr7_grph_vflt : vertical filter, 0: [0 1 -1], 1: [-1 2 -1]. unsigned , default = 1
+//Bit 7: 0, reg_sr7_grph_dif_cor : coring for dif while count for graphic. unsigned , default = 0
+#define SR7_GRAPHIC_THD_GAIN ((0x513f << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_grph_flt_thd : flat threshold for dif while count for graphic. unsigned , default = 2
+//Bit 23:16, reg_sr7_grph_dtl_thd : detail threshold for dif while count for graphic. unsigned , default = 40
+//Bit 15: 8, reg_sr7_grph_hgain : horizontal gain for fast squart of hp. unsigned , default = 32
+//Bit 7: 0, reg_sr7_grph_vgain : vertical gain for fast squart of hp. unsigned , default = 32
+#define SR7_RO_GRAPHIC_FLT_CNT ((0x5140 << 2) + 0xff000000)
+//Bit 31: 0, ro_sr7_grph_flt_cnt : flat count numbers for graphic. unsigned , default = 0
+#define SR7_RO_GRAPHIC_DTL_CNT ((0x5141 << 2) + 0xff000000)
+//Bit 31: 0, ro_sr7_grph_dtl_cnt : detail count numbers for graphic. unsigned , default = 0
+#define SR7_CLR_PRT_PARAM ((0x5142 << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:16, reg_sr7_clr_prct_inpsel : input UV selection for color protection, 0: org; 1: NRout; 2: CTIout; 3: (NR+TIout)/2. unsigned , default = 3
+//Bit 15: 8, reg_sr7_clr_prct_dnlp_gain : gain to de-boost of dnlp_dlt base on color region, norm to 64 as 1.0. set to 0 as disable. unsigned , default = 64
+//Bit 7: 0, reg_sr7_clr_prct_peak_gain : gain to de-boost of peak_dlt base on color region, norm to 64 as 1.0, set to 0 as disable. unsigned , default = 64
+#define SR7_CLR_PRT_LC_GAIN ((0x5143 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_sr7_clr_prct_lc_gain2 : gain to de-boost of lc_dlt (y/u/v) base on color region, norm to 64 as 1.0, set to 0 as disable. unsigned , default = 64
+//Bit 15: 8, reg_sr7_clr_prct_lc_gain1 : gain to de-boost of lc_dlt (y/u/v) base on color region, norm to 64 as 1.0, set to 0 as disable. unsigned , default = 64
+//Bit 7: 0, reg_sr7_clr_prct_lc_gain0 : gain to de-boost of lc_dlt (y/u/v) base on color region, norm to 64 as 1.0, set to 0 as disable. unsigned , default = 64
+#define SR7_CLR_PRT_LUT0 ((0x5144 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut7 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut6 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut5 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut4 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut3 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut2 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut1 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut0 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT1 ((0x5145 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut15 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut14 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut13 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut12 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut11 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut10 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut9 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut8 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT2 ((0x5146 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut23 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut22 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut21 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut20 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut19 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut18 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut17 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut16 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT3 ((0x5147 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut31 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut30 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut29 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut28 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut27 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut26 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut25 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut24 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT4 ((0x5148 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut39 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut38 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut37 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut36 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut35 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut34 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut33 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut32 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT5 ((0x5149 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut47 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut46 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut45 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut44 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut43 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut42 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut41 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut40 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT6 ((0x514a << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut55 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut54 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut53 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut52 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut51 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut50 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut49 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut48 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT7 ((0x514b << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut63 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut62 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut61 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut60 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut59 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut58 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut57 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut56 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT8 ((0x514c << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut71 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut70 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut69 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut68 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut67 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut66 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut65 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut64 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT9 ((0x514d << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut79 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut78 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut77 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut76 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut75 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut74 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut73 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut72 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT10 ((0x514e << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut87 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut86 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut85 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut84 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut83 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut82 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut81 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut80 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT11 ((0x514f << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut95 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut94 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut93 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut92 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut91 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut90 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut89 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut88 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT12 ((0x5150 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut103 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut102 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut101 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut100 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut99 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut98 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut97 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut96 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT13 ((0x5151 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut111 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut110 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut109 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut108 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut107 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut106 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut105 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut104 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT14 ((0x5152 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut119 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut118 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut117 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut116 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut115 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut114 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut113 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut112 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT15 ((0x5153 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut127 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut126 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut125 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut124 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut123 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut122 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut121 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut120 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT16 ((0x5154 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut135 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut134 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut133 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut132 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut131 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut130 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut129 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut128 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT17 ((0x5155 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut143 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut142 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut141 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut140 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut139 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut138 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut137 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut136 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT18 ((0x5156 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut151 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 27:24, reg_sr7_clr_prct_lut150 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 23:20, reg_sr7_clr_prct_lut149 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 19:16, reg_sr7_clr_prct_lut148 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut147 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut146 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut145 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut144 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT19 ((0x5157 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut159 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut158 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut157 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut156 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut155 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut154 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut153 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 3: 0, reg_sr7_clr_prct_lut152 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+#define SR7_CLR_PRT_LUT20 ((0x5158 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut167 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 27:24, reg_sr7_clr_prct_lut166 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 23:20, reg_sr7_clr_prct_lut165 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 19:16, reg_sr7_clr_prct_lut164 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut163 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut162 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut161 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut160 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT21 ((0x5159 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut175 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut174 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut173 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut172 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut171 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut170 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut169 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 3: 0, reg_sr7_clr_prct_lut168 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+#define SR7_CLR_PRT_LUT22 ((0x515a << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut183 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 27:24, reg_sr7_clr_prct_lut182 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 23:20, reg_sr7_clr_prct_lut181 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 19:16, reg_sr7_clr_prct_lut180 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut179 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut178 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut177 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut176 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT23 ((0x515b << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut191 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut190 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut189 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut188 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut187 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut186 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut185 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 3: 0, reg_sr7_clr_prct_lut184 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+#define SR7_CLR_PRT_LUT24 ((0x515c << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut199 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 27:24, reg_sr7_clr_prct_lut198 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 23:20, reg_sr7_clr_prct_lut197 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 19:16, reg_sr7_clr_prct_lut196 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut195 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut194 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut193 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut192 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT25 ((0x515d << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut207 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut206 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut205 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut204 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut203 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut202 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut201 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 3: 0, reg_sr7_clr_prct_lut200 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+#define SR7_CLR_PRT_LUT26 ((0x515e << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut215 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 27:24, reg_sr7_clr_prct_lut214 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 23:20, reg_sr7_clr_prct_lut213 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 19:16, reg_sr7_clr_prct_lut212 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut211 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut210 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut209 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut208 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT27 ((0x515f << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut223 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut222 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut221 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut220 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut219 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut218 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut217 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 3: 0, reg_sr7_clr_prct_lut216 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+#define SR7_CLR_PRT_LUT28 ((0x5160 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut231 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 27:24, reg_sr7_clr_prct_lut230 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 23:20, reg_sr7_clr_prct_lut229 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 19:16, reg_sr7_clr_prct_lut228 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut227 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut226 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut225 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut224 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT29 ((0x5161 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut239 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut238 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut237 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut236 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut235 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut234 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut233 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 3: 0, reg_sr7_clr_prct_lut232 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+#define SR7_CLR_PRT_LUT30 ((0x5162 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut247 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut246 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut245 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut244 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut243 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut242 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut241 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut240 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT31 ((0x5163 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut255 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut254 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut253 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut252 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut251 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut250 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut249 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut248 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: sharp_regs2.h
+//
+
+#define SRSHARP0_SR7_DRTLPF_EN (SRSHARP0_OFFSET + SR7_DRTLPF_EN )//
+#define SRSHARP0_SR7_DRTLPF_BETA (SRSHARP0_OFFSET + SR7_DRTLPF_BETA )//
+#define SRSHARP0_SR7_PKBLD_BETA (SRSHARP0_OFFSET + SR7_PKBLD_BETA )//
+#define SRSHARP0_SR7_XLTIBLD_BETA (SRSHARP0_OFFSET + SR7_XLTIBLD_BETA )//
+#define SRSHARP0_SR7_DRTLPF_EDGE0 (SRSHARP0_OFFSET + SR7_DRTLPF_EDGE0 )//
+#define SRSHARP0_SR7_DRTLPF_EDGE1 (SRSHARP0_OFFSET + SR7_DRTLPF_EDGE1 )//
+#define SRSHARP0_SR7_DRTLPF_SDCOR0 (SRSHARP0_OFFSET + SR7_DRTLPF_SDCOR0 )//
+#define SRSHARP0_SR7_DRTLPF_SDCOR1 (SRSHARP0_OFFSET + SR7_DRTLPF_SDCOR1 )//
+#define SRSHARP0_SR7_CTIGAIN_SDCOR0 (SRSHARP0_OFFSET + SR7_CTIGAIN_SDCOR0 )//
+#define SRSHARP0_SR7_CTIGAIN_SDCOR1 (SRSHARP0_OFFSET + SR7_CTIGAIN_SDCOR1 )//
+#define SRSHARP0_SR7_LTIGAIN_SDCOR0 (SRSHARP0_OFFSET + SR7_LTIGAIN_SDCOR0 )//
+#define SRSHARP0_SR7_LTIGAIN_SDCOR1 (SRSHARP0_OFFSET + SR7_LTIGAIN_SDCOR1 )//
+#define SRSHARP0_SR7_HLTIBPF_TAP0 (SRSHARP0_OFFSET + SR7_HLTIBPF_TAP0 )//
+#define SRSHARP0_SR7_HLTIBPF_TAP1 (SRSHARP0_OFFSET + SR7_HLTIBPF_TAP1 )//
+#define SRSHARP0_SR7_HCTIBPF_TAP0 (SRSHARP0_OFFSET + SR7_HCTIBPF_TAP0 )//
+#define SRSHARP0_SR7_HCTIBPF_TAP1 (SRSHARP0_OFFSET + SR7_HCTIBPF_TAP1 )//
+#define SRSHARP0_SR7_PKLONGBPF_HTAP0 (SRSHARP0_OFFSET + SR7_PKLONGBPF_HTAP0 ) //
+#define SRSHARP0_SR7_PKLONGBPF_HTAP1 (SRSHARP0_OFFSET + SR7_PKLONGBPF_HTAP1 ) //
+#define SRSHARP0_SR7_PKLONGHPF_HTAP0 (SRSHARP0_OFFSET + SR7_PKLONGHPF_HTAP0 ) //
+#define SRSHARP0_SR7_PKLONGHPF_HTAP1 (SRSHARP0_OFFSET + SR7_PKLONGHPF_HTAP1 ) //
+#define SRSHARP0_SR7_VLTIBPF_TAP0 (SRSHARP0_OFFSET + SR7_VLTIBPF_TAP0 ) //
+#define SRSHARP0_SR7_VLTIBPF_TAP1 (SRSHARP0_OFFSET + SR7_VLTIBPF_TAP1 ) //
+#define SRSHARP0_SR7_VCTIBPF_TAP0 (SRSHARP0_OFFSET + SR7_VCTIBPF_TAP0 ) //
+#define SRSHARP0_SR7_VCTIBPF_TAP1 (SRSHARP0_OFFSET + SR7_VCTIBPF_TAP1 ) //
+#define SRSHARP0_SR7_PKLONGBPF_VTAP0 (SRSHARP0_OFFSET + SR7_PKLONGBPF_VTAP0 ) //
+#define SRSHARP0_SR7_PKLONGBPF_VTAP1 (SRSHARP0_OFFSET + SR7_PKLONGBPF_VTAP1 ) //
+#define SRSHARP0_SR7_PKLONGHPF_VTAP0 (SRSHARP0_OFFSET + SR7_PKLONGHPF_VTAP0 ) //
+#define SRSHARP0_SR7_PKLONGHPF_VTAP1 (SRSHARP0_OFFSET + SR7_PKLONGHPF_VTAP1 ) //
+#define SRSHARP0_SR7_CIRBPLONG_ALP (SRSHARP0_OFFSET + SR7_CIRBPLONG_ALP ) //
+#define SRSHARP0_SR7_CIRHPLONG_ALP (SRSHARP0_OFFSET + SR7_CIRHPLONG_ALP ) //
+#define SRSHARP0_SR7_DRTBPLONG_ALP (SRSHARP0_OFFSET + SR7_DRTBPLONG_ALP ) //
+#define SRSHARP0_SR7_DRTHPLONG_ALP (SRSHARP0_OFFSET + SR7_DRTHPLONG_ALP ) //
+#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D0 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D0) //
+#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D1 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D1) //
+#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D2 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D2) //
+#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D3 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D3) //
+#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D4 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D4) //
+#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D0 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D0) //
+#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D1 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D1) //
+#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D2 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D2) //
+#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D3 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D3) //
+#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D4 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D4) //
+#define SRSHARP0_SR7_PKDRT_BLD_EN (SRSHARP0_OFFSET + SR7_PKDRT_BLD_EN ) //
+#define SRSHARP0_SR7_DRTDIF_TH (SRSHARP0_OFFSET + SR7_DRTDIF_TH ) //
+#define SRSHARP0_SR7_TIBLD_PRT (SRSHARP0_OFFSET + SR7_TIBLD_PRT ) //
+#define SRSHARP0_SR7_HTI_OPT_FORCE (SRSHARP0_OFFSET + SR7_HTI_OPT_FORCE ) //
+#define SRSHARP0_SR7_HVTI_FINALGAIN (SRSHARP0_OFFSET + SR7_HVTI_FINALGAIN ) //
+#define SRSHARP0_SR7_TIOS_SDRATIO (SRSHARP0_OFFSET + SR7_TIOS_SDRATIO ) //
+#define SRSHARP0_SR7_XTI_SDFDEN (SRSHARP0_OFFSET + SR7_XTI_SDFDEN ) //
+#define SRSHARP0_SR7_FDSD_PARAM (SRSHARP0_OFFSET + SR7_FDSD_PARAM ) //
+#define SRSHARP0_SR7_TI_BPF_EN (SRSHARP0_OFFSET + SR7_TI_BPF_EN ) //
+#define SRSHARP0_SR7_PKLONG_PF_EN (SRSHARP0_OFFSET + SR7_PKLONG_PF_EN ) //
+#define SRSHARP0_SR7_PKLONG_PF_GAIN (SRSHARP0_OFFSET + SR7_PKLONG_PF_GAIN ) //
+#define SRSHARP0_SR7_PKMINMAX_BLD (SRSHARP0_OFFSET + SR7_PKMINMAX_BLD ) //
+#define SRSHARP0_SR7_TI_CONMAXERR_GAIN (SRSHARP0_OFFSET + SR7_TI_CONMAXERR_GAIN ) //
+#define SRSHARP0_SR7_CC_PK_ADJ (SRSHARP0_OFFSET + SR7_CC_PK_ADJ ) //
+#define SRSHARP0_SR7_CC_LUT0 (SRSHARP0_OFFSET + SR7_CC_LUT0 ) //
+#define SRSHARP0_SR7_CC_LUT1 (SRSHARP0_OFFSET + SR7_CC_LUT1 ) //
+#define SRSHARP0_SR7_CC_LUT2 (SRSHARP0_OFFSET + SR7_CC_LUT2 ) //
+#define SRSHARP0_SR7_CC_LUT3 (SRSHARP0_OFFSET + SR7_CC_LUT3 ) //
+#define SRSHARP0_SR7_CC_LUT4 (SRSHARP0_OFFSET + SR7_CC_LUT4 ) //
+#define SRSHARP0_SR7_CC_LUT5 (SRSHARP0_OFFSET + SR7_CC_LUT5 ) //
+#define SRSHARP0_SR7_GRAPHIC_CTRL (SRSHARP0_OFFSET + SR7_GRAPHIC_CTRL ) //
+#define SRSHARP0_SR7_GRAPHIC_THD_GAIN (SRSHARP0_OFFSET + SR7_GRAPHIC_THD_GAIN ) //
+#define SRSHARP0_SR7_RO_GRAPHIC_FLT_CNT (SRSHARP0_OFFSET + SR7_RO_GRAPHIC_FLT_CNT ) //
+#define SRSHARP0_SR7_RO_GRAPHIC_DTL_CNT (SRSHARP0_OFFSET + SR7_RO_GRAPHIC_DTL_CNT ) //
+#define SRSHARP0_SR7_CLR_PRT_PARAM (SRSHARP0_OFFSET + SR7_CLR_PRT_PARAM ) //
+#define SRSHARP0_SR7_CLR_PRT_LC_GAIN (SRSHARP0_OFFSET + SR7_CLR_PRT_LC_GAIN ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT0 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT0 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT1 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT1 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT2 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT2 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT3 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT3 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT4 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT4 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT5 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT5 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT6 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT6 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT7 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT7 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT8 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT8 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT9 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT9 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT10 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT10 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT11 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT11 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT12 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT12 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT13 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT13 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT14 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT14 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT15 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT15 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT16 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT16 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT17 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT17 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT18 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT18 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT19 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT19 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT20 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT20 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT21 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT21 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT22 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT22 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT23 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT23 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT24 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT24 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT25 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT25 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT26 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT26 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT27 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT27 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT28 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT28 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT29 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT29 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT30 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT30 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT31 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT31 ) //
+
+
+//// srsharp1 reg define
+#define SRSHARP1_SR7_DRTLPF_EN (SRSHARP1_OFFSET + SR7_DRTLPF_EN )//
+#define SRSHARP1_SR7_DRTLPF_BETA (SRSHARP1_OFFSET + SR7_DRTLPF_BETA )//
+#define SRSHARP1_SR7_PKBLD_BETA (SRSHARP1_OFFSET + SR7_PKBLD_BETA )//
+#define SRSHARP1_SR7_XLTIBLD_BETA (SRSHARP1_OFFSET + SR7_XLTIBLD_BETA )//
+#define SRSHARP1_SR7_DRTLPF_EDGE0 (SRSHARP1_OFFSET + SR7_DRTLPF_EDGE0 )//
+#define SRSHARP1_SR7_DRTLPF_EDGE1 (SRSHARP1_OFFSET + SR7_DRTLPF_EDGE1 )//
+#define SRSHARP1_SR7_DRTLPF_SDCOR0 (SRSHARP1_OFFSET + SR7_DRTLPF_SDCOR0 )//
+#define SRSHARP1_SR7_DRTLPF_SDCOR1 (SRSHARP1_OFFSET + SR7_DRTLPF_SDCOR1 )//
+#define SRSHARP1_SR7_CTIGAIN_SDCOR0 (SRSHARP1_OFFSET + SR7_CTIGAIN_SDCOR0 )//
+#define SRSHARP1_SR7_CTIGAIN_SDCOR1 (SRSHARP1_OFFSET + SR7_CTIGAIN_SDCOR1 )//
+#define SRSHARP1_SR7_LTIGAIN_SDCOR0 (SRSHARP1_OFFSET + SR7_LTIGAIN_SDCOR0 )//
+#define SRSHARP1_SR7_LTIGAIN_SDCOR1 (SRSHARP1_OFFSET + SR7_LTIGAIN_SDCOR1 )//
+#define SRSHARP1_SR7_HLTIBPF_TAP0 (SRSHARP1_OFFSET + SR7_HLTIBPF_TAP0 )//
+#define SRSHARP1_SR7_HLTIBPF_TAP1 (SRSHARP1_OFFSET + SR7_HLTIBPF_TAP1 )//
+#define SRSHARP1_SR7_HCTIBPF_TAP0 (SRSHARP1_OFFSET + SR7_HCTIBPF_TAP0 )//
+#define SRSHARP1_SR7_HCTIBPF_TAP1 (SRSHARP1_OFFSET + SR7_HCTIBPF_TAP1 )//
+#define SRSHARP1_SR7_PKLONGBPF_HTAP0 (SRSHARP1_OFFSET + SR7_PKLONGBPF_HTAP0 ) //
+#define SRSHARP1_SR7_PKLONGBPF_HTAP1 (SRSHARP1_OFFSET + SR7_PKLONGBPF_HTAP1 ) //
+#define SRSHARP1_SR7_PKLONGHPF_HTAP0 (SRSHARP1_OFFSET + SR7_PKLONGHPF_HTAP0 ) //
+#define SRSHARP1_SR7_PKLONGHPF_HTAP1 (SRSHARP1_OFFSET + SR7_PKLONGHPF_HTAP1 ) //
+#define SRSHARP1_SR7_VLTIBPF_TAP0 (SRSHARP1_OFFSET + SR7_VLTIBPF_TAP0 ) //
+#define SRSHARP1_SR7_VLTIBPF_TAP1 (SRSHARP1_OFFSET + SR7_VLTIBPF_TAP1 ) //
+#define SRSHARP1_SR7_VCTIBPF_TAP0 (SRSHARP1_OFFSET + SR7_VCTIBPF_TAP0 ) //
+#define SRSHARP1_SR7_VCTIBPF_TAP1 (SRSHARP1_OFFSET + SR7_VCTIBPF_TAP1 ) //
+#define SRSHARP1_SR7_PKLONGBPF_VTAP0 (SRSHARP1_OFFSET + SR7_PKLONGBPF_VTAP0 ) //
+#define SRSHARP1_SR7_PKLONGBPF_VTAP1 (SRSHARP1_OFFSET + SR7_PKLONGBPF_VTAP1 ) //
+#define SRSHARP1_SR7_PKLONGHPF_VTAP0 (SRSHARP1_OFFSET + SR7_PKLONGHPF_VTAP0 ) //
+#define SRSHARP1_SR7_PKLONGHPF_VTAP1 (SRSHARP1_OFFSET + SR7_PKLONGHPF_VTAP1 ) //
+#define SRSHARP1_SR7_CIRBPLONG_ALP (SRSHARP1_OFFSET + SR7_CIRBPLONG_ALP ) //
+#define SRSHARP1_SR7_CIRHPLONG_ALP (SRSHARP1_OFFSET + SR7_CIRHPLONG_ALP ) //
+#define SRSHARP1_SR7_DRTBPLONG_ALP (SRSHARP1_OFFSET + SR7_DRTBPLONG_ALP ) //
+#define SRSHARP1_SR7_DRTHPLONG_ALP (SRSHARP1_OFFSET + SR7_DRTHPLONG_ALP ) //
+#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D0 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D0) //
+#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D1 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D1) //
+#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D2 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D2) //
+#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D3 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D3) //
+#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D4 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D4) //
+#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D0 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D0) //
+#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D1 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D1) //
+#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D2 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D2) //
+#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D3 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D3) //
+#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D4 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D4) //
+#define SRSHARP1_SR7_PKDRT_BLD_EN (SRSHARP1_OFFSET + SR7_PKDRT_BLD_EN ) //
+#define SRSHARP1_SR7_DRTDIF_TH (SRSHARP1_OFFSET + SR7_DRTDIF_TH ) //
+#define SRSHARP1_SR7_TIBLD_PRT (SRSHARP1_OFFSET + SR7_TIBLD_PRT ) //
+#define SRSHARP1_SR7_HTI_OPT_FORCE (SRSHARP1_OFFSET + SR7_HTI_OPT_FORCE ) //
+#define SRSHARP1_SR7_HVTI_FINALGAIN (SRSHARP1_OFFSET + SR7_HVTI_FINALGAIN ) //
+#define SRSHARP1_SR7_TIOS_SDRATIO (SRSHARP1_OFFSET + SR7_TIOS_SDRATIO ) //
+#define SRSHARP1_SR7_XTI_SDFDEN (SRSHARP1_OFFSET + SR7_XTI_SDFDEN ) //
+#define SRSHARP1_SR7_FDSD_PARAM (SRSHARP1_OFFSET + SR7_FDSD_PARAM ) //
+#define SRSHARP1_SR7_TI_BPF_EN (SRSHARP1_OFFSET + SR7_TI_BPF_EN ) //
+#define SRSHARP1_SR7_PKLONG_PF_EN (SRSHARP1_OFFSET + SR7_PKLONG_PF_EN ) //
+#define SRSHARP1_SR7_PKLONG_PF_GAIN (SRSHARP1_OFFSET + SR7_PKLONG_PF_GAIN ) //
+#define SRSHARP1_SR7_PKMINMAX_BLD (SRSHARP1_OFFSET + SR7_PKMINMAX_BLD ) //
+#define SRSHARP1_SR7_TI_CONMAXERR_GAIN (SRSHARP1_OFFSET + SR7_TI_CONMAXERR_GAIN ) //
+#define SRSHARP1_SR7_CC_PK_ADJ (SRSHARP1_OFFSET + SR7_CC_PK_ADJ ) //
+#define SRSHARP1_SR7_CC_LUT0 (SRSHARP1_OFFSET + SR7_CC_LUT0 ) //
+#define SRSHARP1_SR7_CC_LUT1 (SRSHARP1_OFFSET + SR7_CC_LUT1 ) //
+#define SRSHARP1_SR7_CC_LUT2 (SRSHARP1_OFFSET + SR7_CC_LUT2 ) //
+#define SRSHARP1_SR7_CC_LUT3 (SRSHARP1_OFFSET + SR7_CC_LUT3 ) //
+#define SRSHARP1_SR7_CC_LUT4 (SRSHARP1_OFFSET + SR7_CC_LUT4 ) //
+#define SRSHARP1_SR7_CC_LUT5 (SRSHARP1_OFFSET + SR7_CC_LUT5 ) //
+#define SRSHARP1_SR7_GRAPHIC_CTRL (SRSHARP1_OFFSET + SR7_GRAPHIC_CTRL ) //
+#define SRSHARP1_SR7_GRAPHIC_THD_GAIN (SRSHARP1_OFFSET + SR7_GRAPHIC_THD_GAIN ) //
+#define SRSHARP1_SR7_RO_GRAPHIC_FLT_CNT (SRSHARP1_OFFSET + SR7_RO_GRAPHIC_FLT_CNT ) //
+#define SRSHARP1_SR7_RO_GRAPHIC_DTL_CNT (SRSHARP1_OFFSET + SR7_RO_GRAPHIC_DTL_CNT ) //
+#define SRSHARP1_SR7_CLR_PRT_PARAM (SRSHARP1_OFFSET + SR7_CLR_PRT_PARAM ) //
+#define SRSHARP1_SR7_CLR_PRT_LC_GAIN (SRSHARP1_OFFSET + SR7_CLR_PRT_LC_GAIN ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT0 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT0 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT1 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT1 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT2 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT2 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT3 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT3 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT4 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT4 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT5 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT5 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT6 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT6 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT7 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT7 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT8 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT8 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT9 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT9 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT10 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT10 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT11 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT11 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT12 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT12 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT13 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT13 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT14 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT14 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT15 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT15 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT16 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT16 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT17 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT17 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT18 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT18 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT19 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT19 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT20 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT20 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT21 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT21 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT22 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT22 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT23 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT23 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT24 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT24 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT25 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT25 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT26 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT26 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT27 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT27 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT28 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT28 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT29 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT29 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT30 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT30 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT31 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT31 ) //
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: srsharp_regs2.h
+//
+// -----------------------------------------------
+// REG_BASE: VPPG_VCBUS_BASE = 0x52
+// -----------------------------------------------
+// 8'h50/51/52/53 have used for srsharp_regs
+// -----------------------------------------------
+// REG_BASE: VPPH_VCBUS_BASE = 0x53
+// -----------------------------------------------
+// 8'h50/51/52/53 have used for srsharp_regs
+//afbcd_multx6 use 3 reg_pages
+// -----------------------------------------------
+// REG_BASE: MADE_VCBUS_BASE = 0x54
+// -----------------------------------------------
+//
+// Reading file: afbcd_mult_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+// reg addr map
+// 8'h0 - 8'h3f : rdmif
+// 8'h40 - 8'h6f : afbcd
+// 8'h70 - 8'h7f : fgrain
+////===============================////
+#define RDMIFXN_GEN_REG ((0x5400 << 2) + 0xff000000)
+#define RDMIFXN_CANVAS0 ((0x5401 << 2) + 0xff000000)
+#define RDMIFXN_CANVAS1 ((0x5402 << 2) + 0xff000000)
+#define RDMIFXN_LUMA_X0 ((0x5403 << 2) + 0xff000000)
+#define RDMIFXN_LUMA_Y0 ((0x5404 << 2) + 0xff000000)
+#define RDMIFXN_CHROMA_X0 ((0x5405 << 2) + 0xff000000)
+#define RDMIFXN_CHROMA_Y0 ((0x5406 << 2) + 0xff000000)
+#define RDMIFXN_LUMA_X1 ((0x5407 << 2) + 0xff000000)
+#define RDMIFXN_LUMA_Y1 ((0x5408 << 2) + 0xff000000)
+#define RDMIFXN_CHROMA_X1 ((0x5409 << 2) + 0xff000000)
+#define RDMIFXN_CHROMA_Y1 ((0x540a << 2) + 0xff000000)
+#define RDMIFXN_RPT_LOOP ((0x540b << 2) + 0xff000000)
+#define RDMIFXN_LUMA0_RPT_PAT ((0x540c << 2) + 0xff000000)
+#define RDMIFXN_CHROMA0_RPT_PAT ((0x540d << 2) + 0xff000000)
+#define RDMIFXN_LUMA1_RPT_PAT ((0x540e << 2) + 0xff000000)
+#define RDMIFXN_CHROMA1_RPT_PAT ((0x540f << 2) + 0xff000000)
+#define RDMIFXN_LUMA_PSEL ((0x5410 << 2) + 0xff000000)
+#define RDMIFXN_CHROMA_PSEL ((0x5411 << 2) + 0xff000000)
+#define RDMIFXN_DUMMY_PIXEL ((0x5412 << 2) + 0xff000000)
+#define RDMIFXN_LUMA_FIFO_SIZE ((0x5413 << 2) + 0xff000000)
+#define RDMIFXN_AXI_CMD_CNT ((0x5414 << 2) + 0xff000000)
+#define RDMIFXN_AXI_RDAT_CNT ((0x5415 << 2) + 0xff000000)
+#define RDMIFXN_RANGE_MAP_Y ((0x5416 << 2) + 0xff000000)
+#define RDMIFXN_RANGE_MAP_CB ((0x5417 << 2) + 0xff000000)
+#define RDMIFXN_RANGE_MAP_CR ((0x5418 << 2) + 0xff000000)
+#define RDMIFXN_GEN_REG2 ((0x5419 << 2) + 0xff000000)
+#define RDMIFXN_PROT ((0x541a << 2) + 0xff000000)
+#define RDMIFXN_URGENT_CTRL ((0x541b << 2) + 0xff000000)
+#define RDMIFXN_GEN_REG3 ((0x541c << 2) + 0xff000000)
+#define RDMIFXN_CFMT_CTRL ((0x541d << 2) + 0xff000000)
+#define RDMIFXN_CFMT_W ((0x541e << 2) + 0xff000000)
+#define AFBCDM_ENABLE ((0x5440 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:23, reg_gclk_ctrl_core unsigned, default = 0
+//Bit 22, reg_fmt_size_sw_mode unsigned, default = 0, 0:hw mode 1:sw mode for format size
+//Bit 21, reg_addr_link_en unsigned, default = 1, 1:enable
+//Bit 20, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb
+//Bit 19, reg_dos_uncomp_mode unsigned , default = 0
+//Bit 18:16, soft_rst unsigned , default = 4
+//Bit 15:14, reserved
+//Bit 13:12, ddr_blk_size unsigned , default = 1
+//Bit 11:9, cmd_blk_size unsigend , default = 3
+//Bit 8, dec_enable unsigned , default = 0
+//Bit 7:2, reserved
+//Bit 1, head_len_sel unsigned , default = 1
+//Bit 0, dec_frm_start unsigned , default = 0
+#define AFBCDM_MODE ((0x5441 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29, ddr_sz_mode uns, default = 0 , 0: fixed block ddr size 1 : unfixed block ddr size;
+//Bit 28, blk_mem_mode uns, default = 0 , 0: fixed 16x128 size; 1 : fixed 12x128 size
+//Bit 27:26, rev_mode uns, default = 0 , reverse mode
+//Bit 25:24, mif_urgent uns, default = 3 , info mif and data mif urgent
+//Bit 23, reserved
+//Bit 22:16, hold_line_num uns, default = 0 ,
+//Bit 15:14, burst_len uns, default = 2, 0: burst1 1:burst2 2:burst4
+//Bit 13:8, compbits_yuv uns, default = 0 ,
+// bit 1:0,: y component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+// bit 3:2,: u component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+// bit 5:4,: v component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+//Bit 7:6, vert_skip_y uns, default = 0 , luma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 5:4, horz_skip_y uns, default = 0 , luma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 3:2, vert_skip_uv uns, default = 0 , chroma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 1:0, horz_skip_uv uns, default = 0 , chroma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+#define AFBCDM_SIZE_IN ((0x5442 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hsize_in uns, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_in uns, default = 1080 , pic vert size in unit: pixel
+#define AFBCDM_DEC_DEF_COLOR ((0x5443 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:20, def_color_y uns, default = 255, afbc dec y default setting value
+//Bit 19:10, def_color_u uns, default = 128, afbc dec u default setting value
+//Bit 9: 0, def_color_v uns, default = 128, afbc dec v default setting value
+#define AFBCDM_CONV_CTRL ((0x5444 << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13:12, fmt_mode uns, default = 2, 0:yuv444 1:yuv422 2:yuv420
+//Bit 11: 0, conv_lbuf_len uns, default = 256, unit=16 pixel need to set = 2^n
+#define AFBCDM_LBUF_DEPTH ((0x5445 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, dec_lbuf_depth uns, default = 128; // unit= 8 pixel
+//Bit 15:12, reserved
+//Bit 11:0, mif_lbuf_depth uns, default = 128;
+#define AFBCDM_HEAD_BADDR ((0x5446 << 2) + 0xff000000)
+//Bit 31:0, mif_info_baddr uns, default = 32'h0;
+#define AFBCDM_BODY_BADDR ((0x5447 << 2) + 0xff000000)
+//Bit 31:0, mif_data_baddr uns, default = 32'h00010000;
+#define AFBCDM_SIZE_OUT ((0x5448 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, hsize_out uns, default = 1920 ; // unit: 1 pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_out uns, default = 1080 ; // unit: 1 pixel
+#define AFBCDM_OUT_YSCOPE ((0x5449 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, out_vert_bgn uns, default = 0 ; // unit: 1 pixel
+//Bit 15:13, reserved
+//Bit 12:0, out_vert_end uns, default = 1079 ; // unit: 1 pixel
+#define AFBCDM_STAT ((0x544a << 2) + 0xff000000)
+//Bit 31:1, ro_dbg_top_info uns, default = 0
+//Bit 0, frm_end_stat uns, default = 0 frame end status
+#define AFBCDM_VD_CFMT_CTRL ((0x544b << 2) + 0xff000000)
+//Bit 31 cfmt_gclk_bit_dis uns, default = 0 ; // it true, disable clock, otherwise enable clock
+//Bit 30 cfmt_soft_rst_bit uns, default = 0 ; // soft rst bit
+//Bit 29 reserved
+//Bit 28 chfmt_rpt_pix uns, default = 0 ; // if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
+//Bit 27:24 chfmt_ini_phase uns, default = 0 ; // horizontal formatter initial phase
+//Bit 23 chfmt_rpt_p0_en uns, default = 0 ; // horizontal formatter repeat pixel 0 enable
+//Bit 22:21 chfmt_yc_ratio uns, default = 0 ; // horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
+//Bit 20 chfmt_en uns, default = 0 ; // horizontal formatter enable
+//Bit 19 cvfmt_phase0_always_en uns, default = 0 ; //if true, always use phase0 while vertical formater, meaning always
+// repeat data, no interpolation
+//Bit 18 cvfmt_rpt_last_dis uns, default = 0 ; //if true, disable vertical formatter chroma repeat last line
+//Bit 17 cvfmt_phase0_nrpt_en uns, default = 0 ; //veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable
+//Bit 16 cvfmt_rpt_line0_en uns, default = 0 ; //veritcal formatter repeat line 0 enable
+//Bit 15:12 cvfmt_skip_line_num uns, default = 0 ; //vertical formatter skip line num at the beginning
+//Bit 11:8 cvfmt_ini_phase uns, default = 0 ; //vertical formatter initial phase
+//Bit 7:1 cvfmt_phase_step uns, default = 0 ; //vertical formatter phase step (3.4)
+//Bit 0 cvfmt_en uns, default = 0 ; //vertical formatter enable
+#define AFBCDM_VD_CFMT_W ((0x544c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 chfmt_w uns, default = 0 ;horizontal formatter width
+//Bit 15:13 reserved
+//Bit 12:0 cvfmt_w uns, default = 0 ;vertical formatter width
+#define AFBCDM_MIF_HOR_SCOPE ((0x544d << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, mif_blk_bgn_h uns, default = 0 ; // unit: 32 pixel/block hor
+//Bit 15:10, reserved
+//Bit 9: 0, mif_blk_end_h uns, default = 59 ; // unit: 32 pixel/block hor
+#define AFBCDM_MIF_VER_SCOPE ((0x544e << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, mif_blk_bgn_v uns, default = 0 ; // unit: 32 pixel/block ver
+//Bit 15:12, reserved
+//Bit 11: 0, mif_blk_end_v uns, default = 269; // unit: 32 pixel/block ver
+#define AFBCDM_PIXEL_HOR_SCOPE ((0x544f << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, dec_pixel_bgn_h uns, default = 0 ; // unit: pixel
+//Bit 15:13, reserved
+//Bit 12: 0, dec_pixel_end_h uns, default = 1919 ; // unit: pixel
+#define AFBCDM_PIXEL_VER_SCOPE ((0x5450 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, dec_pixel_bgn_v uns, default = 0 ; // unit: pixel
+//Bit 15:13, reserved
+//Bit 12: 0, dec_pixel_end_v uns, default = 1079 ; // unit: pixel
+#define AFBCDM_VD_CFMT_H ((0x5451 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12:0 cfmt_h uns, default = 142 ; //vertical formatter height
+#define AFBCDM_IQUANT_ENABLE ((0x5452 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_quant_expand_en_1 //unsigned, RW, default = 0 enable for quantization value expansion
+//Bit 10 reg_quant_expand_en_0 //unsigned, RW, default = 0 enable for quantization value expansion
+//Bit 9: 8 reg_bcleav_ofst //signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1;
+//Bit 7: 5 reserved
+//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy
+//Bit 3: 1 reserved
+//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy
+#define AFBCDM_IQUANT_LUT_1 ((0x5453 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDM_IQUANT_LUT_2 ((0x5454 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDM_IQUANT_LUT_3 ((0x5455 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDM_IQUANT_LUT_4 ((0x5456 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDM_ROT_CTRL ((0x5460 << 2) + 0xff000000)
+//Bit 31:30 reg_rot_ohds2_mode //unsigned, RW, default = 0 , rot output format down hor drop mode,0:average 1:use 0 2:use 1
+//Bit 29:28 reg_rot_ovds2_mode //unsigned, RW, default = 0 , rot output format down ver drop mode,0:average 1:use 0 2:use 1
+//Bit 27 reg_pip_mode //unsigned, RW, default = 0 , 0:dec_src from vdin/dos 1:dec_src from pip
+//Bit 26:24 reg_rot_uv_vshrk_drop_mode //unsigned, RW, default = 0 , 0:average (1/2: 1:left 2:right) (1/4: 1:[0] 2:[1] 3:[2] 4:[3], 5:left_121 6:right_121)
+//Bit 23 reserved
+//Bit 22:20 reg_rot_uv_hshrk_drop_mode //unsigned, RW, default = 0 , 0:average (1/2: 1:left 2:right) (1/4: 1:[0] 2:[1] 3:[2] 4:[3], 5:left_121 6:right_121)
+//Bit 19:18 reg_rot_uv_vshrk_ratio //unsigned, RW, default = 0 , 0:no shrink 1:1/2 shrink 2:1/4 shrink
+//Bit 17:16 reg_rot_uv_hshrk_ratio //unsigned, RW, default = 0 , 0:no shrink 1:1/2 shrink 2:1/4 shrink
+//Bit 15 reserved
+//Bit 14:12 reg_rot_y_vshrk_drop_mode //unsigned, RW, default = 0 , 0:average (1/2: 1:left 2:right) (1/4: 1:[0] 2:[1] 3:[2] 4:[3], 5:left_121 6:right_121)
+//Bit 11 reserved
+//Bit 10:8 reg_rot_y_hshrk_drop_mode //unsigned, RW, default = 0 , 0:average (1/2: 1:left 2:right) (1/4: 1:[0] 2:[1] 3:[2] 4:[3], 5:left_121 6:right_121)
+//Bit 7:6 reg_rot_y_vshrk_ratio //unsigned, RW, default = 0 , 0:no shrink 1:1/2 shrink 2:1/4 shrink
+//Bit 5:4 reg_rot_y_hshrk_ratio //unsigned, RW, default = 0 , 0:no shrink 1:1/2 shrink 2:1/4 shrink
+//Bit 3:2 reg_rot_uv422_drop_mode //unsigned, RW, default = 0 , 0:average 1:left 2:right
+//Bit 1 reg_rot_uv422_omode //unsigned, RW, default = 0 , when rot input fmt422, 0:output_uv422 1:output_uv420
+//Bit 0 reg_rot_enable //unsigned, RW, default = 0 , rotation enable
+#define AFBCDM_ROT_SCOPE ((0x5461 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:20 reg_rot_debug_probe //unsigned, RW , default = 0, y:[2:0] uv:[5:3]; 0:iblk_size 1:oblk_size 2:iblk_cnt 3:oblk_cnt 4:hsize_in 5:vsize_in 6:vstep
+//Bit 19 reg_rot_dout_ds_mode_sw //unsigned, RW , default = 0, 0:use hardware mode 1:use software mode
+//Bit 18:17 reg_rot_dout_ds_mode //unsigned, RW , default = 0, rot output fmt_down mode: [0]:h_downscale [1]:v_downscale
+//Bit 16 reg_rot_ifmt_force444 //unsigned, RW , default = 1, 1: rot input fmt force as 444
+//Bit 15:14 reg_rot_ofmt_mode //unsigned, RW , default = 0, rot output fmt mode
+//Bit 13:12 reg_rot_compbits_out_y //unsigned, RW , default = 0, rot output compbit y
+//Bit 11:10 reg_rot_compbits_out_uv //unsigned, RW , default = 0, rot output compbit uv
+//Bit 9:8 reg_rot_wrbgn_v //unsigned, RW , default = 0, rot pic vert size window begin pixel
+//Bit 7:5 reserved
+//Bit 4:0 reg_rot_wrbgn_h //unsigned, RW , default = 0, rot pic hori size window begin pixel
+#define AFBCDM_RPLC_CTRL ((0x5462 << 2) + 0xff000000)
+//Bit 31 reg_rplc_inter_corr_en //unsigned, RW , default = 0 , //pip replace inte-frame edge correct enable
+//Bit 30 reg_rplc_dummy_corr_en //unsigned, RW , default = 0 , //pip replace outsize of real-pipframe edge correct enable
+//Bit 29 reg_rplc_byps //unsigned, RW , default = 1 , //pip replace module bypass
+//Bit 28:16 reg_rplc_vsize_in //unsigned, RW , default = 1080, //
+//Bit 15:13 reserved
+//Bit 12:0 reg_rplc_hsize_in //unsigned, RW , default = 1920,
+#define AFBCDM_RPLC_PICEN ((0x5463 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 reg_rplc_def_color_y //unsigned, RW , default =0 , //pip replace def_color_y
+//Bit 15:0 reg_rplc_pic_enable //unsigned, RW , default =16'hffff , //pip replace pip_picure enbale
+#define AFBCDM_RPLC_DEFCOL ((0x5464 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_rplc_def_color_v //unsigned, RW , default =0 , //pip replace def_color_v
+//Bit 11:0 reg_rplc_def_color_u //unsigned, RW , default =0 , //pip replace def_color_u
+#define AFBCDM_RPLC_SCPXN_ADDR ((0x5465 << 2) + 0xff000000)
+//Bit 31:0 reg_rplc_scpxn_addr //unsigned, RW , default =0 , //pip replace scopx16 addr
+#define AFBCDM_RPLC_SCPXN_DATA ((0x5466 << 2) + 0xff000000)
+//Bit 31:0 reg_rplc_scpxn_data //unsigned, RW , default =0 , //pip replace scopx16 data
+#define AFBCDM_ROT_RO_STAT ((0x5467 << 2) + 0xff000000)
+//Bit 31:0 ro_rot_debug //unsigned, RO , default = 0, rot some status
+#define AFBCDM_FGRAIN_CTRL ((0x5470 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_sync_ctrl // unsigned , RW, default = 0
+//Bit 23 reserved
+//Bit 22 reg_dma_st_clr // unsigned , RW, default = 0 clear DMA error status
+//Bit 21 reg_hold4dma_scale // unsigned , RW, default = 0 1 to wait DMA scale data ready before accept input data default = 0
+//Bit 20 reg_hold4dma_tbl // unsigned , RW, default = 0 1 to wait DMA grain table data ready before accept input data default = 0
+//Bit 19 reg_cin_uv_swap // unsigned , RW, default = 0 1 to swap U/V input
+//Bit 18 reg_cin_rev // unsigned , RW, default = 0 1 to reverse the U/V input order
+//Bit 17 reg_yin_rev // unsigned , RW, default = 0 1 to reverse the Y input order
+//Bit 16 reg_fgrain_ext_imode // unsigned , RW, default = 1 0 to indicate the input data is *4 in 8bit mode
+//Bit 15 reg_use_par_apply_fgrain // unsigned , RW, default = 0 1 to use apply_fgrain from DMA table
+//Bit 14 reg_fgrain_last_ln_mode // unsigned , RW, default = 0 1 to keep fgrain noise generator though the input is finished for rdmif.
+//Bit 13 reg_fgrain_use_sat4bp // unsigned , RW, default = 0 1 to use fgain_max/min for sat not {DW{1'b1}}/0
+//Bit 12 reg_apply_c_mode // unsigned , RW, default = 1 0 to following C
+//Bit 11 reg_fgrain_tbl_sign_mode // unsigned , RW, default = 1 0 to indicate signed bit is not extended in 8bit mode
+//Bit 10 reg_fgrain_tbl_ext_mode // unsigned , RW, default = 1 0 to indicate the grain table is *4 in 8bit mode
+//Bit 9: 8 reg_fmt_mode // unsigned , RW, default = 2 0:444; 1:422; 2:420; 3:reserved
+//Bit 7: 6 reg_comp_bits // unsigned , RW, default = 1 0:8bits; 1:10bits, else 12 bits
+//Bit 5: 4 reg_rev_mode // unsigned . RW, default = 0 0:h_rev; 1:v_rev;
+//Bit 3 reserved
+//Bit 2 reg_block_mode // unsigned , RW, default = 1
+//Bit 1 reg_fgrain_loc_en // unsigned , RW, default = 0 frame-based fgrain enable
+//Bit 0 reg_fgrain_glb_en // unsigned , RW, default = 0 global-based fgrain enable
+#define AFBCDM_FGRAIN_WIN_H ((0x5471 << 2) + 0xff000000)
+//Bit 31:16 reg_win_end_h .unsigned , default = 3812
+//Bit 15: 0, reg_win_bgn_h .unsigned , default = 0
+#define AFBCDM_FGRAIN_WIN_V ((0x5472 << 2) + 0xff000000)
+//Bit 31:16 reg_win_end_v .unsigned , default = 2156
+//Bit 15: 0, reg_win_bgn_v .unsigned , default = 0
+#define AFBCDM_FGRAIN_SW_Y_RANNGE ((0x5473 << 2) + 0xff000000)
+//Bit 31, reg_fgrain_sw_yrange .unsigned , default = 0
+//Bit 30:26, reserved
+//Bit 25:16, reg_fgrain_ymax .unsigned , default = 1023
+//Bit 15:10, reserved
+//Bit 9: 0, reg_fgrain_ymin .unsigned , default = 0
+#define AFBCDM_FGRAIN_SW_C_RANNGE ((0x5474 << 2) + 0xff000000)
+//Bit 31, reg_fgrain_sw_crange .unsigned , default = 0
+//Bit 30:26, reserved
+//Bit 25:16, reg_fgrain_cmax .unsigned , default = 1023
+//Bit 15:10, reserved
+//Bit 9: 0, reg_fgrain_cmin .unsigned , default = 0
+#define AFBCDM_FGRAIN_GCLK_CTRL_0 ((0x5475 << 2) + 0xff000000)
+//Bit 31:0, reg_fgrain_gclk_ctrl0 .unsigned , default = 0
+#define AFBCDM_FGRAIN_GCLK_CTRL_1 ((0x5476 << 2) + 0xff000000)
+//Bit 31:0, reg_fgrain_gclk_ctrl1 .unsigned , default = 0
+#define AFBCDM_FGRAIN_GCLK_CTRL_2 ((0x5477 << 2) + 0xff000000)
+//Bit 31:0, reg_fgrain_gclk_ctrl2 .unsigned , default = 0
+#define AFBCDM_FGRAIN_PARAM_ADDR ((0x5478 << 2) + 0xff000000)
+#define AFBCDM_FGRAIN_PARAM_DATA ((0x5479 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: afbcd_mult_regs.h
+//
+//afbcd_multx6 use 3 reg_pages
+// -----------------------------------------------
+// REG_BASE: MADF_VCBUS_BASE = 0x55
+// -----------------------------------------------
+//`include "afbcd_mult_regs.h"
+//afbcd_multx6 use 3 reg_pages
+// -----------------------------------------------
+// REG_BASE: MADG_VCBUS_BASE = 0x56
+// -----------------------------------------------
+//`include "afbcd_mult_regs.h"
+// -----------------------------------------------
+// REG_BASE: MADH_VCBUS_BASE = 0x57
+// -----------------------------------------------
+// -----------------------------------------------
+// REG_BASE: VPPI_VCBUS_BASE = 0x58
+// -----------------------------------------------
+//
+// Reading file: pip_alph_gen_regs.h
+//
+//
+// Reading file: vd1_pip_alph_gen_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+////===================================////
+////reg
+////===================================////
+#define VD1_PIP_ALPH_CTRL ((0x5880 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28 reg_alph_gen_dbg unsigned,default = 0 1 bit dbg_mode: output pic with alph_256 to check function
+//Bit 27:12 reg_pic_en unsigned,default = 16'h0 16bits decide which pics are enable
+//Bit 11:3 reg_alph0 unsigned,default = 0 9 bits alph0: alph value of those points which are out of the windows range
+//Bit 2:1 reg_alph_gen_mode unsigned, default = 0 2 bits out of window/border/inside of window: 0:original, 1: 0/0.5/1 alpha 2: 0/0.25/0.5/0.75/1 alph
+//Bit 0 reg_alph_gen_byps unsigned, default = 1 1 bit bypass mode
+#define VD1_PIP_ALPH_SCP_H_0 ((0x5881 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h0 unsigned,default = 0 13bits pic_0 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h0 unsigned,default = 0 13bits pic_0 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_1 ((0x5882 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h1 unsigned,default = 0 13bits pic_1 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h1 unsigned,default = 0 13bits pic_1 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_2 ((0x5883 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h2 unsigned,default = 0 13bits pic_2 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h2 unsigned,default = 0 13bits pic_2 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_3 ((0x5884 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h3 unsigned,default = 0 13bits pic_3 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h3 unsigned,default = 0 13bits pic_3 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_4 ((0x5885 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h4 unsigned,default = 0 13bits pic_4 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h4 unsigned,default = 0 13bits pic_4 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_5 ((0x5886 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h5 unsigned,default = 0 13bits pic_5 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h5 unsigned,default = 0 13bits pic_5 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_6 ((0x5887 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h6 unsigned,default = 0 13bits pic_6 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h6 unsigned,default = 0 13bits pic_6 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_7 ((0x5888 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h7 unsigned,default = 0 13bits pic_7 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h7 unsigned,default = 0 13bits pic_7 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_8 ((0x5889 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h8 unsigned,default = 0 13bits pic_8 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h8 unsigned,default = 0 13bits pic_8 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_9 ((0x588a << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h9 unsigned,default = 0 13bits pic_9 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h9 unsigned,default = 0 13bits pic_9 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_10 ((0x588b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h10 unsigned,default = 0 13bits pic_10 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h10 unsigned,default = 0 13bits pic_10 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_11 ((0x588c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h11 unsigned,default = 0 13bits pic_11 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h11 unsigned,default = 0 13bits pic_11 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_12 ((0x588d << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h12 unsigned,default = 0 13bits pic_12 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h12 unsigned,default = 0 13bits pic_12 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_13 ((0x588e << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h13 unsigned,default = 0 13bits pic_13 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h13 unsigned,default = 0 13bits pic_13 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_14 ((0x588f << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h14 unsigned,default = 0 13bits pic_14 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h14 unsigned,default = 0 13bits pic_14 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_15 ((0x5890 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h15 unsigned,default = 0 13bits pic_15 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h15 unsigned,default = 0 13bits pic_15 window horizontal begin
+#define VD1_PIP_ALPH_SCP_V_0 ((0x5891 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v0 unsigned,default = 0 13bits pic_0 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v0 unsigned,default = 0 13bits pic_0 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_1 ((0x5892 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v1 unsigned,default = 0 13bits pic_1 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v1 unsigned,default = 0 13bits pic_1 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_2 ((0x5893 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v2 unsigned,default = 0 13bits pic_2 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v2 unsigned,default = 0 13bits pic_2 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_3 ((0x5894 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v3 unsigned,default = 0 13bits pic_3 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v3 unsigned,default = 0 13bits pic_3 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_4 ((0x5895 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v4 unsigned,default = 0 13bits pic_4 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v4 unsigned,default = 0 13bits pic_4 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_5 ((0x5896 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v5 unsigned,default = 0 13bits pic_5 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v5 unsigned,default = 0 13bits pic_5 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_6 ((0x5897 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v6 unsigned,default = 0 13bits pic_6 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v6 unsigned,default = 0 13bits pic_6 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_7 ((0x5898 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v7 unsigned,default = 0 13bits pic_7 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v7 unsigned,default = 0 13bits pic_7 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_8 ((0x5899 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v8 unsigned,default = 0 13bits pic_8 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v8 unsigned,default = 0 13bits pic_8 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_9 ((0x589a << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v9 unsigned,default = 0 13bits pic_9 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v9 unsigned,default = 0 13bits pic_9 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_10 ((0x589b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v10 unsigned,default = 0 13bits pic_10 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v10 unsigned,default = 0 13bits pic_10 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_11 ((0x589c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v11 unsigned,default = 0 13bits pic_11 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v11 unsigned,default = 0 13bits pic_11 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_12 ((0x589d << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v12 unsigned,default = 0 13bits pic_12 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v12 unsigned,default = 0 13bits pic_12 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_13 ((0x589e << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v13 unsigned,default = 0 13bits pic_13 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v13 unsigned,default = 0 13bits pic_13 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_14 ((0x589f << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v14 unsigned,default = 0 13bits pic_14 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v14 unsigned,default = 0 13bits pic_14 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_15 ((0x58a0 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v15 unsigned,default = 0 13bits pic_15 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v15 unsigned,default = 0 13bits pic_15 window vertical begin
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vd1_pip_alph_gen_regs.h
+//
+//
+// Reading file: vd2_pip_alph_gen_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+////===================================////
+////reg
+////===================================////
+#define VD2_PIP_ALPH_CTRL ((0x58b0 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28 reg_alph_gen_dbg unsigned,default = 0 1 bit dbg_mode: output pic with alph_256 to check function
+//Bit 27:12 reg_pic_en unsigned,default = 16'h0 16bits decide which pics are enable
+//Bit 11:3 reg_alph0 unsigned,default = 0 9 bits alph0: alph value of those points which are out of the windows range
+//Bit 2:1 reg_alph_gen_mode unsigned, default = 0 2 bits out of window/border/inside of window: 0:original, 1: 0/0.5/1 alpha 2: 0/0.25/0.5/0.75/1 alph
+//Bit 0 reg_alph_gen_byps unsigned, default = 1 1 bit bypass mode
+#define VD2_PIP_ALPH_SCP_H_0 ((0x58b1 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h0 unsigned,default = 0 13bits pic_0 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h0 unsigned,default = 0 13bits pic_0 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_1 ((0x58b2 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h1 unsigned,default = 0 13bits pic_1 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h1 unsigned,default = 0 13bits pic_1 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_2 ((0x58b3 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h2 unsigned,default = 0 13bits pic_2 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h2 unsigned,default = 0 13bits pic_2 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_3 ((0x58b4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h3 unsigned,default = 0 13bits pic_3 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h3 unsigned,default = 0 13bits pic_3 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_4 ((0x58b5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h4 unsigned,default = 0 13bits pic_4 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h4 unsigned,default = 0 13bits pic_4 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_5 ((0x58b6 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h5 unsigned,default = 0 13bits pic_5 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h5 unsigned,default = 0 13bits pic_5 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_6 ((0x58b7 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h6 unsigned,default = 0 13bits pic_6 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h6 unsigned,default = 0 13bits pic_6 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_7 ((0x58b8 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h7 unsigned,default = 0 13bits pic_7 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h7 unsigned,default = 0 13bits pic_7 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_8 ((0x58b9 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h8 unsigned,default = 0 13bits pic_8 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h8 unsigned,default = 0 13bits pic_8 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_9 ((0x58ba << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h9 unsigned,default = 0 13bits pic_9 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h9 unsigned,default = 0 13bits pic_9 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_10 ((0x58bb << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h10 unsigned,default = 0 13bits pic_10 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h10 unsigned,default = 0 13bits pic_10 window horizontal begi
+#define VD2_PIP_ALPH_SCP_H_11 ((0x58bc << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h11 unsigned,default = 0 13bits pic_11 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h11 unsigned,default = 0 13bits pic_11 window horizontal begi
+#define VD2_PIP_ALPH_SCP_H_12 ((0x58bd << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h12 unsigned,default = 0 13bits pic_12 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h12 unsigned,default = 0 13bits pic_12 window horizontal begi
+#define VD2_PIP_ALPH_SCP_H_13 ((0x58be << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h13 unsigned,default = 0 13bits pic_13 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h13 unsigned,default = 0 13bits pic_13 window horizontal begi
+#define VD2_PIP_ALPH_SCP_H_14 ((0x58bf << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h14 unsigned,default = 0 13bits pic_14 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h14 unsigned,default = 0 13bits pic_14 window horizontal begi
+#define VD2_PIP_ALPH_SCP_H_15 ((0x58c0 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h15 unsigned,default = 0 13bits pic_15 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h15 unsigned,default = 0 13bits pic_15 window horizontal begi
+#define VD2_PIP_ALPH_SCP_V_0 ((0x58c1 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v0 unsigned,default = 0 13bits pic_0 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v0 unsigned,default = 0 13bits pic_0 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_1 ((0x58c2 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v1 unsigned,default = 0 13bits pic_1 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v1 unsigned,default = 0 13bits pic_1 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_2 ((0x58c3 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v2 unsigned,default = 0 13bits pic_2 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v2 unsigned,default = 0 13bits pic_2 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_3 ((0x58c4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v3 unsigned,default = 0 13bits pic_3 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v3 unsigned,default = 0 13bits pic_3 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_4 ((0x58c5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v4 unsigned,default = 0 13bits pic_4 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v4 unsigned,default = 0 13bits pic_4 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_5 ((0x58c6 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v5 unsigned,default = 0 13bits pic_5 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v5 unsigned,default = 0 13bits pic_5 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_6 ((0x58c7 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v6 unsigned,default = 0 13bits pic_6 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v6 unsigned,default = 0 13bits pic_6 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_7 ((0x58c8 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v7 unsigned,default = 0 13bits pic_7 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v7 unsigned,default = 0 13bits pic_7 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_8 ((0x58c9 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v8 unsigned,default = 0 13bits pic_8 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v8 unsigned,default = 0 13bits pic_8 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_9 ((0x58ca << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v9 unsigned,default = 0 13bits pic_9 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v9 unsigned,default = 0 13bits pic_9 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_10 ((0x58cb << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v10 unsigned,default = 0 13bits pic_10 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v10 unsigned,default = 0 13bits pic_10 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_11 ((0x58cc << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v11 unsigned,default = 0 13bits pic_11 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v11 unsigned,default = 0 13bits pic_11 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_12 ((0x58cd << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v12 unsigned,default = 0 13bits pic_12 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v12 unsigned,default = 0 13bits pic_12 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_13 ((0x58ce << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v13 unsigned,default = 0 13bits pic_13 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v13 unsigned,default = 0 13bits pic_13 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_14 ((0x58cf << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v14 unsigned,default = 0 13bits pic_14 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v14 unsigned,default = 0 13bits pic_14 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_15 ((0x58d0 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v15 unsigned,default = 0 13bits pic_15 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v15 unsigned,default = 0 13bits pic_15 window vertical begin
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vd2_pip_alph_gen_regs.h
+//
+//
+// Closing file: pip_alph_gen_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: ./vcbus_regs.h
+//
+//
+// Reading file: ./ge2d_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+////// GE2D Registers 0x8a0 - 0x8ff
+//address is 0xd016_0000 - 0xd0160000 - 0xd01603ff
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: GE2D_GCBUS_BASE = 0x00
+// -----------------------------------------------
+//Bit 31, destination bytemask only if destination bitmask is enable
+//Bit 30, destination bitmask enable
+//Bit 29, source2 key enable
+//Bit 28, source2 key mode, 0: mask data when match, 1: mask data when unmatch
+//Bit 27, source1 key enable
+//Bit 26, source1 key mode, 0: mask data when match, 1: mask data when unmatch
+//Bit 25:24, dst1 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 23 dst clip mode, 0: write inside clip window, 1: write outside clip window
+//Bit 22:17, reserved
+//Bit 16:15, src2 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 14 src2 fill mode, 0: repeat data, 1: fill default color
+//Bit 13:12 src2 picture struct, 00: frame, 10: even, 11: odd
+//Bit 11 src1 x direction yc ration, 0: 1:1, 1: 2:1
+//Bit 10 src1 y direction yc ration, 0: 1:1, 1: 2:1
+//Bit 9:7 reserved
+//Bit 6:5, src1 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 4 src1 fill mode, 0: repeat data, 1: fill default color
+//Bit 3 src1 lookup table enable
+//Bit 2:1 src1 picture struct, 00: frame, 10: even, 11: odd
+//Bit 0 src1 separate buffer enable
+#define GE2D_GEN_CTRL0 ((0x00a0 << 2) + 0xff040000)
+//Bit 31, soft rst
+//Bit 30, dst write response counter reset
+//Bit 29, disable adding dst write response count to busy bit
+//Bit 28:26, reserved
+//bit 25:24, interrupt control, if bit[0] true, generate interrupt when one command done,
+// if bit[1] true, generate interrupt when ge2d change from busy to not busy
+//Bit 23:22 src2 burst size control
+//Bit 21:16 src1 burst size control, 5:4, yfifo, 3:2, cbfifo, 1:0, crfifo
+// each 2bit, 00: 24 64bitword, 01: 32 64bitword, 10: 48 64bitwords, 11: 64 64bitwords
+//Bit 15:14, dst1 picture struct, 00: frame, 10:top, 11: bottom
+//Bit 13:12, bit 13 if true, force read src1, bit 12 if true, force read src2
+//Bit 11, dst2 request urgent enable
+//Bit 10, src1 request urgent enable
+//Bit 9, src2 request urgent enable
+//Bit 8, dst1 request urgent enable
+//Bit 7:0 src1 global alpha
+#define GE2D_GEN_CTRL1 ((0x00a1 << 2) + 0xff040000)
+//Bit31 alpha conversion mode in alu, 0: alpha_out = (alpha !=0) ? alpha +1 : 0;
+// otherwise, alpha_out = (alpha < 128) ? alpha: alpha + 1;
+//Bit30 color conversion mode in alu, 0: color_out = (color != 0) ? color +1: 0;
+// otherwise, color_out = (color < 128) ? color: color + 1;
+//Bit29 src1_gb_alpha_en, As = src1_gb_alpha_en ? Asr * Ag: Asr
+//Bit28 dst1_color_round_mode, 0: truncate, 1: + 0.5 rounding
+//Bit27 src2_color_expand_mode, 0: add 0, 1: add MSBs
+//Bit26 src2_alpha_expand_mode, 0: add 0, 1: add MSBs
+//Bit25 src1_color_expand_mode, 0: add 0, 1: add MSBs
+//Bit24 src1_alpha_expand_mode, 0: add 0, 1: add MSBs
+//Bit 23 if true, dst little endian, otherwise big endian
+//Bit 22:19 dst1 color_map
+// dst1_format=0 : output 8-bit;
+// dst1_format=1, dst1_color_map=1: output 16-bit YCbCr 655;
+// dst1_format=1, dst1_color_map=2: output 16-bit YCbCr 844;
+// dst1_format=1, dst1_color_map=3: output 16-bit YCbCrA 6442;
+// dst1_format=1, dst1_color_map=4: output 16-bit YCbCrA 4444;
+// dst1_format=1, dst1_color_map=5: output 16-bit YCbCr 565;
+// dst1_format=1, dst1_color_map=6: output 16-bit AYCbCr 4444;
+// dst1_format=1, dst1_color_map=7: output 16-bit AYCbCr 1555;
+// dst1_format=1, dst1_color_map=8: output 16-bit YCbCrA 4642;
+// dst1_format=1, dst1_color_map=9: output 16-bit CbCr 88;
+// dst1_format=1, dst1_color_map=10:output 16-bit CrCb 88;
+// dst1_format=2, dst1_color_map=0: output 24-bit YCbCr 888;
+// dst1_format=2, dst1_color_map=1: output 24-bit YCbCrA 5658;
+// dst1_format=2, dst1_color_map=2: output 24-bit AYCbCr 8565;
+// dst1_format=2, dst1_color_map=3: output 24-bit YCbCrA 6666;
+// dst1_format=2, dst1_color_map=4: output 24-bit AYCbCr 6666;
+// dst1_format=2, dst1_color_map=5: output 24-bit CrCbY 888;
+// dst1_format=3, dst1_color_map=0: output 32-bit YCbCrA 8888;
+// dst1_format=3, dst1_color_map=1: output 32-bit AYCbCr 8888;
+// dst1_format=3, dst1_color_map=2: output 32-bit ACrCbY 8888;
+// dst1_format=3, dst1_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 17:16 dst1_format, 00: 8bit, 01:16bit, 10:24bit, 11: 32bit
+//Bit 15 if true, src2 little endian, otherwise big endian
+//Bit 14:11 src2 color_map
+// src2_format=0 : output 8-bit;
+// src2_format=1, src2_color_map=1: output 16-bit YCbCr 655;
+// src2_format=1, src2_color_map=2: output 16-bit YCbCr 844;
+// src2_format=1, src2_color_map=3: output 16-bit YCbCrA 6442;
+// src2_format=1, src2_color_map=4: output 16-bit YCbCrA 4444;
+// src2_format=1, src2_color_map=5: output 16-bit YCbCr 565;
+// src2_format=1, src2_color_map=6: output 16-bit AYCbCr 4444;
+// src2_format=1, src2_color_map=7: output 16-bit AYCbCr 1555;
+// src2_format=1, src2_color_map=8: output 16-bit YCbCrA 4642;
+// src2_format=2, src2_color_map=0: output 24-bit YCbCr 888;
+// src2_format=2, src2_color_map=1: output 24-bit YCbCrA 5658;
+// src2_format=2, src2_color_map=2: output 24-bit AYCbCr 8565;
+// src2_format=2, src2_color_map=3: output 24-bit YCbCrA 6666;
+// src2_format=2, src2_color_map=4: output 24-bit AYCbCr 6666;
+// src2_format=2, src2_color_map=5: output 24-bit CrCbY 888;
+// src2_format=3, src2_color_map=0: output 32-bit YCbCrA 8888;
+// src2_format=3, src2_color_map=1: output 32-bit AYCbCr 8888;
+// src2_format=3, src2_color_map=2: output 32-bit ACrCbY 8888;
+// src2_format=3, src2_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 9:8 src2 format, 00: 8bit, 01:16bit, 10:24bit 11: 32bit
+//Bit 7 if true, src1 little endian, otherwise big endian
+//Bit 6:3 src1 color_map
+// src1_format=0 : output 8-bit;
+// src1_format=1, src1_color_map=0: output 4:2:2 (Y0Cb0Y1Cr0);
+// src1_format=1, src1_color_map=1: output 16-bit YCbCr 655;
+// src1_format=1, src1_color_map=2: output 16-bit YCbCr 844;
+// src1_format=1, src1_color_map=3: output 16-bit YCbCrA 6442;
+// src1_format=1, src1_color_map=4: output 16-bit YCbCrA 4444;
+// src1_format=1, src1_color_map=5: output 16-bit YCbCr 565;
+// src1_format=1, src1_color_map=6: output 16-bit AYCbCr 4444;
+// src1_format=1, src1_color_map=7: output 16-bit AYCbCr 1555;
+// src1_format=1, src2_color_map=8: output 16-bit YCbCrA 4642;
+// src1_format=2, src1_color_map=0: output 24-bit YCbCr 888;
+// src1_format=2, src1_color_map=1: output 24-bit YCbCrA 5658;
+// src1_format=2, src1_color_map=2: output 24-bit AYCbCr 8565;
+// src1_format=2, src1_color_map=3: output 24-bit YCbCrA 6666;
+// src1_format=2, src1_color_map=4: output 24-bit AYCbCr 6666;
+// src1_format=2, src1_color_map=5: output 24-bit CrCbY 888;
+// src1_format=2, src1_color_map=14:output 8-bit Y and 16-bit CbCr;
+// src1_format=2, src1_color_map=15:output 8-bit Y and 16-bit CrCb;
+// src1_format=3, src1_color_map=0: output 32-bit YCbCrA 8888;
+// src1_format=3, src1_color_map=1: output 32-bit AYCbCr 8888;
+// src1_format=3, src1_color_map=2: output 32-bit ACrCbY 8888;
+// src1_format=3, src1_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 1:0 src1 format, 00: 8bit, 01:16bit/4:2:2, 10:24bit 11: 32bit
+#define GE2D_GEN_CTRL2 ((0x00a2 << 2) + 0xff040000)
+//Bit 9 if true, all src2 data use default color
+//Bit 8 if true, all src1 data use default color
+//Bit 7 if true, dst x/y swap
+//Bit 6 if true, dst x direction reversely read
+//Bit 5 if true, dst y direction reversely read
+//Bit 4 if true, src2 x direction reversely read
+//Bit 3 if true, src2 y direction reversely read
+//Bit 2 if true, src1 x direction reversely read
+//Bit 1 if true, src1 y direction reversely read
+//Bit 0 cmd write
+#define GE2D_CMD_CTRL ((0x00a3 << 2) + 0xff040000)
+//Read only
+//Bit 28:17 dst write response counter, for debug only
+//Bit 16:7 ge2d_dp status, for debug only
+//Bit 6 read src1 cmd ready
+//Bit 5 read src2 cmd ready
+//Bit 4 pre dpcmd ready
+//Bit 3 ge2d dpcmd ready
+//Bit 2 ge2d buffer command valid
+//Bit 1 ge2d current command valid
+//Bit 0 ge2d busy
+#define GE2D_STATUS0 ((0x00a4 << 2) + 0xff040000)
+//
+//Read only
+// Bit 29:16 ge2d_dst1_status, for debug only
+// Bit 15 ge2d_rd_src2 core.fifo_empty
+// Bit 14 ge2d_rd_src2 core.fifo_overflow
+// Bit 13:12 ge2d_rd_src2 core.req_st
+// Bit 11 ge2d_rd_src2 cmd_if.cmd_err, true if cmd_format=1
+// Bit 10 ge2d_rd_src2 cmd_if.cmd_st, 0=IDLE state, 1=BUSY state
+// Bit 9 ge2d_rd_src1 luma_core(chroma_core).fifo_empty
+// Bit 8 ge2d_rd_src1 luma_core(chroma_core).fifo_overflow
+// Bit 7: 6 ge2d_rd_src1 chroma_core.req_st_cr
+// Bit 5: 4 ge2d_rd_src1 chroma_core.req_st_cb
+// Bit 3: 2 ge2d_rd_src1 luma_core.req_st_y
+// Bit 1 ge2d_rd_src1 cmd_if.stat_read_window_err, 1=reading/clipping window setting exceed limit
+// Bit 0 ge2d_rd_src1 cmd_if.cmd_st, 0=IDLE state, 1=BUSY state
+#define GE2D_STATUS1 ((0x00a5 << 2) + 0xff040000)
+//SRC1 default clolor
+//{Y,Cb,Cr,A}/{R,G,B,A}
+#define GE2D_SRC1_DEF_COLOR ((0x00a6 << 2) + 0xff040000)
+//Bit 31, SRC1 clip x start extra, if true, one more data is read for chroma
+//Bit 28:16, SRC1 clip x start
+//Bit 15, SRC1 clip x end extra, if true, one more data is read for chroma
+//Bit 12:0, SRC1 clip x end
+#define GE2D_SRC1_CLIPX_START_END ((0x00a7 << 2) + 0xff040000)
+//Bit 31, SRC1 clip y start extra, if true, one more data is read for chroma
+//Bit 28:16, SRC1 clip y start
+//Bit 15, SRC1 clip y end extra, if true, one more data is read for chroma
+//Bit 12:0, SRC1 clip y end
+#define GE2D_SRC1_CLIPY_START_END ((0x00a8 << 2) + 0xff040000)
+//Bit 31:24, SRC1 canvas address0
+//Bit 23:16, SRC1 canvas address1
+//Bit 15:8, SRC1 canvas address2
+#define GE2D_SRC1_CANVAS ((0x00a9 << 2) + 0xff040000)
+//Bit 31, SRC1 x start extra bit1, if true, one more chroma data is read for x even start chroma data when y/c ratio = 2
+// or x even/odd start chroma extra data when y/c ratio = 1
+//Bit 30, SRC1 x start extra bit0, if true, one more chroma data is read for x odd start chroma data when y/c ratio = 2
+//Bit 29:16, SRC1 x start, signed data
+//Bit 15, SRC1 x end extra bit1, if true, one more chroma data is read for x odd end chroma data when y/c ratio = 2
+// or x even/odd end chroma extra data when y/c ratio = 1
+//Bit 14, SRC1 x end extra bit0, if true, one more chroma data is read for x even end chroma data when y/c ratio = 2
+//Bit 13:0, SRC1 x end, signed data
+#define GE2D_SRC1_X_START_END ((0x00aa << 2) + 0xff040000)
+//Bit 31, SRC1 y start extra, if true, one more chroma data is read for y even start chroma data when y/c ratio = 2
+// or y even/odd start chroma extra data when y/c ratio = 1
+//Bit 30, SRC1 y start extra, if true, one more chroma data is read for x odd start chroma data when y/c ratio = 2
+//Bit 28:16, SRC1 y start
+//Bit 15, SRC1 y end extra bit1, if true, one more chroma data is read for y odd end chroma data when y/c ratio = 2
+// or y even/odd end chroma extra data when y/c ratio = 1
+//Bit 14, SRC1 y end extra bit0, if true, one more chroma data is read for y even end chroma data when y/c ratio = 2
+//Bit 12:0, SRC1 y end
+#define GE2D_SRC1_Y_START_END ((0x00ab << 2) + 0xff040000)
+// Bit 31: 9 Reserved
+// Bit 8 RW, 0 = Write LUT, 1 = Read LUT
+// Bit 7: 0 RW, lut_addr
+#define GE2D_SRC1_LUT_ADDR ((0x00ac << 2) + 0xff040000)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define GE2D_SRC1_LUT_DAT ((0x00ad << 2) + 0xff040000)
+//Bit 19, if true, horizontal formatter using repeat to get the pixel, otherwise using interpolation
+//Bit 18, horizontal formatter en
+//Bit 17, if true, vertical formatter using repeat to get the pixel, otherwise using interpolation
+//Bit 16, vertical formatter en
+//Bit 15:8 X direction chroma phase,
+// [7:4] for x direction even start/end chroma phase when y/c ratio = 2
+// or start/end even/odd chroma phase when y/c ratio = 1
+// [3:0] for x direction odd start/end chroma phase only when y/c ration = 2
+//Bit 7:0 Y direction chroma phase,
+// [7:4] for y direction even start/end chroma phase when y/c ratio = 2
+// or start/end even/odd chroma phase when y/c ratio = 1
+// [3:0] for y direction odd start/end chroma phase only when y/c ration = 2
+#define GE2D_SRC1_FMT_CTRL ((0x00ae << 2) + 0xff040000)
+//SRC2 default clolor
+//{Y,Cb,Cr,A}/{R,G,B,A}
+#define GE2D_SRC2_DEF_COLOR ((0x00af << 2) + 0xff040000)
+//Bit 28:16, SRC2 clip x start
+//Bit 12:0, SRC2 clip x end
+#define GE2D_SRC2_CLIPX_START_END ((0x00b0 << 2) + 0xff040000)
+//Bit 28:16, SRC2 clip y start
+//Bit 12:0, SRC2 clip y end
+#define GE2D_SRC2_CLIPY_START_END ((0x00b1 << 2) + 0xff040000)
+//Bit 28:16, SRC2 x start
+//Bit 12:0, SRC2 x end
+#define GE2D_SRC2_X_START_END ((0x00b2 << 2) + 0xff040000)
+//Bit 28:16, SRC2 y start
+//Bit 12:0, SRC2 y end
+#define GE2D_SRC2_Y_START_END ((0x00b3 << 2) + 0xff040000)
+//Bit 28:16, DST clip x start
+//Bit 12:0, DST clip x end
+#define GE2D_DST_CLIPX_START_END ((0x00b4 << 2) + 0xff040000)
+//
+//Bit 28:16, DST clip y start
+//Bit 12:0, DST clip y end
+#define GE2D_DST_CLIPY_START_END ((0x00b5 << 2) + 0xff040000)
+//Bit 28:16, DST x start
+//Bit 12:0, DST x end
+#define GE2D_DST_X_START_END ((0x00b6 << 2) + 0xff040000)
+//
+//Bit 28:16, DST x start
+//Bit 12:0, DST x end
+#define GE2D_DST_Y_START_END ((0x00b7 << 2) + 0xff040000)
+//Bit 23:16 DST2 canvas address
+//Bit 15:8 SRC2 canvas address
+//Bit 7:0 DST1 canvas address
+#define GE2D_SRC2_DST_CANVAS ((0x00b8 << 2) + 0xff040000)
+//vertical scaler phase step
+//Bit 28:0, 5.24 format
+#define GE2D_VSC_START_PHASE_STEP ((0x00b9 << 2) + 0xff040000)
+//phase slope
+//Bit 24:0, bit 24 signed bit
+#define GE2D_VSC_PHASE_SLOPE ((0x00ba << 2) + 0xff040000)
+//Bit 30:29, vertical repeat line0 number
+//Bit 23:0, vertical scaler initial phase
+#define GE2D_VSC_INI_CTRL ((0x00bb << 2) + 0xff040000)
+//horizontal scaler phase step
+//Bit 28:0, 5.24 format
+#define GE2D_HSC_START_PHASE_STEP ((0x00bc << 2) + 0xff040000)
+//phase slope
+//Bit 24:0, bit 24 signed bit
+#define GE2D_HSC_PHASE_SLOPE ((0x00bd << 2) + 0xff040000)
+//Bit 30:29, horizontal repeat line0 number
+//Bit 23:0, horizontal scaler initial phase
+#define GE2D_HSC_INI_CTRL ((0x00be << 2) + 0xff040000)
+//Bit 31:24, advance number in this round, if horizontal scaler is working on dividing mode
+//Bit 23:0, horizontal scaler advance phase in this round, if horizontal scaler is working on dividing mode
+#define GE2D_HSC_ADV_CTRL ((0x00bf << 2) + 0xff040000)
+//Bit 30, vertical nearest mode enable, must set vt_bank_length = 4
+//Bit 29, horizontal nearest mode enable, must set hz_bank_length = 4
+//Bit 28, horizontal scaler dividing mode enable
+//Bit 27:15, horizontal dividing length, if bit 28 is enable
+//Bit 14, pre horizontal scaler enable
+//Bit 13, pre vertical scale enable
+//Bit 12, vertical scale enable
+//Bit 11, horizontal scaler enable
+//Bit 9, if true, treat horizontal repeat line number(GE2D_HSC_INI_CTRL bit 30:29) as repeating line,
+// otherwise using treat horizontal repeat line number as minus line number.
+//Bit 8, if true, treat vertical repeat line number(GE2D_VSC_INI_CTRL bit 30:29) as repeating line,
+// otherwise using treat vertical repeat line number as minus line number.
+//Bit 7, if true, always use phase0 in vertical scaler
+//Bit 6:4, vertical scaler bank length
+//Bit 3, if true, always use phase0 in horizontal scaler
+//Bit 2:0, horizontal scaler bank length
+#define GE2D_SC_MISC_CTRL ((0x00c0 << 2) + 0xff040000)
+//Read only
+//vertical scaler next round integer pixel pointer, signed data
+//Bit 13:0
+#define GE2D_VSC_NRND_POINT ((0x00c1 << 2) + 0xff040000)
+//Read only
+//vertical scaler next round phase
+//bit 23:0
+#define GE2D_VSC_NRND_PHASE ((0x00c2 << 2) + 0xff040000)
+//Read only
+//horizontal scaler next round integer pixel pointer, signed data
+//Bit 13:0
+#define GE2D_HSC_NRND_POINT ((0x00c3 << 2) + 0xff040000)
+//Read only
+//horizontal scaler next round phase
+//bit 23:0
+#define GE2D_HSC_NRND_PHASE ((0x00c4 << 2) + 0xff040000)
+//
+//Bit 28:20, pre_offset0
+//Bit 18:10, pre_offset1
+//Bit 8:0, pre_offset2
+#define GE2D_MATRIX_PRE_OFFSET ((0x00c5 << 2) + 0xff040000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define GE2D_MATRIX_COEF00_01 ((0x00c6 << 2) + 0xff040000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define GE2D_MATRIX_COEF02_10 ((0x00c7 << 2) + 0xff040000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define GE2D_MATRIX_COEF11_12 ((0x00c8 << 2) + 0xff040000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define GE2D_MATRIX_COEF20_21 ((0x00c9 << 2) + 0xff040000)
+//Bit 28:16 coef22
+//Bit 7 input y/cb/cr saturation enable
+//Bit 0 conversion matrix enable
+#define GE2D_MATRIX_COEF22_CTRL ((0x00ca << 2) + 0xff040000)
+//Bit 28:20, offset0
+//Bit 18:10, offset1
+//Bit 8:0, offset2
+#define GE2D_MATRIX_OFFSET ((0x00cb << 2) + 0xff040000)
+//Bit 26:25, SRC1 color multiplier alpha selection
+// if 00, Cs = Csr
+// if 01, Cs = Csr * Asr * Ag (if source is not premultiplied)
+// if 10, Cs = Csr * Ag (if source is premultipied)
+//Bit 24 SRC2 color multiplier alpha selection
+// if 0, no multiplier, Cd = Cdr, otherwise, Cd = Cdr * Ad.
+//Bit 22:12 ALU color operation
+// bit10:8 Blending Mode Parameter
+// 3'b000: ADD Cs*Fs + Cd*Fd
+// 3'b001: SUBTRACT Cs*Fs - Cd*Fd
+// 3'b010: REVERSE SUBTRACT Cd*Fd - Cs*Fs
+// 3'b011: MIN min(Cs*Fs, Cd*Fd)
+// 3'b100: MAX max(Cs*Fs, Cd*Fd)
+// 3'b101: LOGIC OP Cs op Cd
+// bit7:4 Source Color Blending Factor CFs
+// 4'b0000: ZERO 0
+// 4'b0001: ONE 1
+// 4'b0010: SRC_COLOR Cs(RGBs)
+// 4'b0011: ONE_MINUS_SRC_COLOR 1 - Cs(RGBs)
+// 4'b0100: DST_COLOR Cd(RGBd)
+// 4'b0101: ONE_MINUS_DST_COLOR 1 - Cd(RGBd)
+// 4'b0110: SRC_ALPHA As
+// 4'b0111: ONE_MINUS_SRC_ALPHA 1 - As
+// 4'b1000: DST_ALPHA Ad
+// 4'b1001: ONE_MINUS_DST_ALPHA 1 - Ad
+// 4'b1010: CONST_COLOR Cc(RGBc)
+// 4'b1011: ONE_MINUS_CONST_COLOR 1 - Cc(RGBc)
+// 4'b1100: CONST_ALPHA Ac
+// 4'b1101: ONE_MINUS_CONST_ALPHA 1 - Ac
+// 4'b1110: SRC_ALPHA_SATURATE min(As,1-Ad)
+// bit3:0 dest Color Blending Factor CFd, when bit10:8 != LOGIC OP
+// 4'b0000: ZERO 0
+// 4'b0001: ONE 1
+// 4'b0010: SRC_COLOR Cs(RGBs)
+// 4'b0011: ONE_MINUS_SRC_COLOR 1 - Cs(RGBs)
+// 4'b0100: DST_COLOR Cd(RGBd)
+// 4'b0101: ONE_MINUS_DST_COLOR 1 - Cd(RGBd)
+// 4'b0110: SRC_ALPHA As
+// 4'b0111: ONE_MINUS_SRC_ALPHA 1 - As
+// 4'b1000: DST_ALPHA Ad
+// 4'b1001: ONE_MINUS_DST_ALPHA 1 - Ad
+// 4'b1010: CONST_COLOR Cc(RGBc)
+// 4'b1011: ONE_MINUS_CONST_COLOR 1 - Cc(RGBc)
+// 4'b1100: CONST_ALPHA Ac
+// 4'b1101: ONE_MINUS_CONST_ALPHA 1 - Ac
+// 4'b1110: SRC_ALPHA_SATURATE min(As,1-Ad)
+// bit3:0 logic operations, when bit10:8 == LOGIC OP
+// 4'b0000: CLEAR 0
+// 4'b0001: COPY s
+// 4'b0010: NOOP d
+// 4'b0011: SET 1
+// 4'b0100: COPY_INVERT ~s
+// 4'b0101: INVERT ~d
+// 4'b0110: AND_REVERSE s & ~d
+// 4'b0111: OR_REVERSE s | ~d
+// 4'b1000: AND s & d
+// 4'b1001: OR s | d
+// 4'b1010: NAND ~(s & d)
+// 4'b1011: NOR ~(s | d)
+// 4'b1100: XOR s ^ d
+// 4'b1101: EQUIV ~(s ^ d)
+// 4'b1110: AND_INVERTED ~s & d
+// 4'b1111: OR_INVERTED ~s | d
+//Bit 10:0 ALU alpha operation
+// bit10:8 Blending Equation Math Operation
+// 3'b000: ADD As*Fs + Ad*Fd
+// 3'b001: SUBTRACT As*Fs - Ad*Fd
+// 3'b010: REVERSE SUBTRACT Ad*Fd - As*Fs
+// 3'b011: MIN min(As*Fs, Ad*Fd)
+// 3'b100: MAX max(As*Fs, Ad*Fd)
+// 3'b101: LOGIC OP As op Ad
+// bit7:4 Source alpha Blending Factor AFs
+// 4'b0000 0
+// 4'b0001 1
+// 4'b0010 As
+// 4'b0011 1 - As
+// 4'b0100 Ad
+// 4'b0101 1 - Ad
+// 4'b0110 Ac
+// 4'b0111 1 - Ac
+// .... reserved
+// bit3:0 Destination alpha Blending Factor AFd, when bit10:8 != LOGIC OP
+// 4'b0000 0
+// 4'b0001 1
+// 4'b0010 As
+// 4'b0011 1 - As
+// 4'b0100 Ad
+// 4'b0101 1 - Ad
+// 4'b0110 Ac
+// 4'b0111 1 - Ac
+// .... reserved
+// bit3:0 logic operations, when bit10:8 == LOGIC OP
+// 4'b0000: CLEAR 0
+// 4'b0001: COPY s
+// 4'b0010: NOOP d
+// 4'b0011: SET 1
+// 4'b0100: COPY_INVERT ~s
+// 4'b0101: INVERT ~d
+// 4'b0110: AND_REVERSE s & ~d
+// 4'b0111: OR_REVERSE s | ~d
+// 4'b1000: AND s & d
+// 4'b1001: OR s | d
+// 4'b1010: NAND ~(s & d)
+// 4'b1011: NOR ~(s | d)
+// 4'b1100: XOR s ^ d
+// 4'b1101: EQUIV ~(s ^ d)
+// 4'b1110: AND_INVERTED ~s & d
+// 4'b1111: OR_INVERTED ~s | d
+#define GE2D_ALU_OP_CTRL ((0x00cc << 2) + 0xff040000)
+//bit 31:0 (RGBA,YCBCRA)
+#define GE2D_ALU_CONST_COLOR ((0x00cd << 2) + 0xff040000)
+//SRC1 Key
+//31:0
+#define GE2D_SRC1_KEY ((0x00ce << 2) + 0xff040000)
+//SRC1 Key Mask
+//31:0
+#define GE2D_SRC1_KEY_MASK ((0x00cf << 2) + 0xff040000)
+//SRC2 Key
+//31:0
+#define GE2D_SRC2_KEY ((0x00d0 << 2) + 0xff040000)
+//SRC2 Key Mask
+//31:0
+#define GE2D_SRC2_KEY_MASK ((0x00d1 << 2) + 0xff040000)
+//Destination Bit Mask
+//31:0
+#define GE2D_DST_BITMASK ((0x00d2 << 2) + 0xff040000)
+//Bit 31 DP onoff mode, 0: on_counter means how many pixels will output before ge2d turns off
+// 1: on_counter means how many clocks will ge2d turn on before ge2d turns off
+//Bit 30:16 DP on counter
+//Bit 15 0: vd_format doesnt have onoff mode, 1: vd format has onoff mode
+//Bit 14:0 DP off counter
+#define GE2D_DP_ONOFF_CTRL ((0x00d3 << 2) + 0xff040000)
+//Because there are many coefficients used in the vertical filter and horizontal filters,
+//indirect access the coefficients of vertical filter and horizontal filter is used.
+//For vertical filter, there are 33x4 coefficients
+//For horizontal filter, there are 33x4 coefficients
+//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
+//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
+//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
+//Bit 8 type of index, 0: vertical coef
+// 1: horizontal coef
+//Bit 6:0 coef index
+#define GE2D_SCALE_COEF_IDX ((0x00d4 << 2) + 0xff040000)
+//coefficients for vertical filter and horizontal filter
+#define GE2D_SCALE_COEF ((0x00d5 << 2) + 0xff040000)
+//Bit 24 src2 alpha fill mode: together with GE2D_GEN_CTRL0[4](fill_mode), define what alpha values are used
+// for the area outside the clipping window. As below:
+// fill_mode=0, alpha_fill_mode=0 : use inner alpha, (or default_alpha if src data have no alpha values);
+// fill_mode=0, alpha_fill_mode=1 : use outside_alpha;
+// fill_mode=1, alpha_fill_mode=0 : use default_alpha;
+// fill_mode=1, alpha_fill_mode=1 : use outside_alpha.
+//Bit 23:16 src2 outside alpha
+//Bit 8 src1 alpha fill mode, refer to src2 alpha fill mode above.
+//Bit 7:0 src1 outside alpha
+#define GE2D_SRC_OUTSIDE_ALPHA ((0x00d6 << 2) + 0xff040000)
+//Bit 31 antiflick enable
+//Bit 24 1: alpha value for the first line use repeated alpha, 0: use bit 23:16 as the first line alpha
+//Bit 23:16 register value for the first line alpha when bit 24 is 1
+//Bit 8 1: alpha value for the last line use repeated alpha, 0: use bit 7:0 as the last line alpha
+//Bit 7:0 register value for the last line alpha when bit 8 is 1
+#define GE2D_ANTIFLICK_CTRL0 ((0x00d8 << 2) + 0xff040000)
+//Bit 25, rgb_sel, 1: antiflick RGBA, 0: antiflick YCbCrA
+//Bit 24, cbcr_en, 1: also filter cbcr in case of antiflicking YCbCrA, 0: no filter on cbcr in case of antiflicking YCbCrA
+//Bit 23:16, R mult coef for converting RGB to Y
+//Bit 15:8, G mult coef for converting RGB to Y
+//Bit 7:0, B mult coef for converting RGB to Y
+//Y = (R * y_r + G * y_g + B * y_b) / 256
+#define GE2D_ANTIFLICK_CTRL1 ((0x00d9 << 2) + 0xff040000)
+//Bit 31:24, Y threhold1, when 0<Y<=th1, use filter0;
+//Bit 23:16, color antiflick filter0 n3
+//Bit 15:8, color antiflick filter0 n2
+//Bit 7:0, color antiflick filter0 n1
+//Y = (line_up * n1 + line_center * n2 + line_dn * n3) / 128
+#define GE2D_ANTIFLICK_COLOR_FILT0 ((0x00da << 2) + 0xff040000)
+//Bit 31:24, Y threhold2, when th1<Y<=th2, use filter1;
+//Bit 23:16, color antiflick filter1 n3
+//Bit 15:8, color antiflick filter1 n2
+//Bit 7:0, color antiflick filter1 n1
+#define GE2D_ANTIFLICK_COLOR_FILT1 ((0x00db << 2) + 0xff040000)
+//Bit 31:24, Y threhold3, when th2<Y<=th3, use filter2; Y>th3, use filter3
+//Bit 23:16, color antiflick filter2 n3
+//Bit 15:8, color antiflick filter2 n2
+//Bit 7:0, color antiflick filter2 n1
+#define GE2D_ANTIFLICK_COLOR_FILT2 ((0x00dc << 2) + 0xff040000)
+//Bit 23:16, color antiflick filter3 n3
+//Bit 15:8, color antiflick filter3 n2
+//Bit 7:0, color antiflick filter3 n1
+#define GE2D_ANTIFLICK_COLOR_FILT3 ((0x00dd << 2) + 0xff040000)
+//Bit 31:24, Alpha threhold1, when 0<Alpha<=th1, use filter0;
+//Bit 23:16, Alpha antiflick filter0 n3
+//Bit 15:8, Alpha antiflick filter0 n2
+//Bit 7:0, Alpha antiflick filter0 n1
+//Alpha = (line_up * n1 + line_center * n2 + line_dn * n3) / 128
+#define GE2D_ANTIFLICK_ALPHA_FILT0 ((0x00de << 2) + 0xff040000)
+//Bit 31:24, Alpha threhold2, when th1<Alpha<=th2, use filter1;
+//Bit 23:16, Alpha antiflick filter1 n3
+//Bit 15:8, Alpha antiflick filter1 n2
+//Bit 7:0, Alpha antiflick filter1 n1
+#define GE2D_ANTIFLICK_ALPHA_FILT1 ((0x00df << 2) + 0xff040000)
+//Bit 31:24, Alpha threhold3, when th2<Alpha<=th3, use filter2; Alpha>th3, use filter3
+//Bit 23:16, Alpha antiflick filter2 n3
+//Bit 15:8, Alpha antiflick filter2 n2
+//Bit 7:0, Alpha antiflick filter2 n1
+#define GE2D_ANTIFLICK_ALPHA_FILT2 ((0x00e0 << 2) + 0xff040000)
+//Bit 23:16, Alpha antiflick filter3 n3
+//Bit 15:8, Alpha antiflick filter3 n2
+//Bit 7:0, Alpha antiflick filter3 n1
+#define GE2D_ANTIFLICK_ALPHA_FILT3 ((0x00e1 << 2) + 0xff040000)
+//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset)
+//Bit 30:22 din_offset (signed data)
+//Bit 21:14 map_coef (unsigned data)
+//Bit 13:10 map_sr (unsigned data)
+//Bit 9:1 dout_offset (signed data)
+//Bit 0 enable
+#define GE2D_SRC1_RANGE_MAP_Y_CTRL ((0x00e3 << 2) + 0xff040000)
+//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset)
+//Bit 30:22 din_offset (signed data)
+//Bit 21:14 map_coef (unsigned data)
+//Bit 13:10 map_sr (unsigned data)
+//Bit 9:1 dout_offset (signed data)
+//Bit 0 enable
+#define GE2D_SRC1_RANGE_MAP_CB_CTRL ((0x00e4 << 2) + 0xff040000)
+//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset)
+//Bit 30:22 din_offset (signed data)
+//Bit 21:14 map_coef (unsigned data)
+//Bit 13:10 map_sr (unsigned data)
+//Bit 9:1 dout_offset (signed data)
+//Bit 0 enable
+#define GE2D_SRC1_RANGE_MAP_CR_CTRL ((0x00e5 << 2) + 0xff040000)
+//Bit 21:16 src1 prearbitor burst number
+//Bit 13:8 src2 prearbitor burst number
+//Bit 5:0 dst prearbitor burst number
+#define GE2D_ARB_BURST_NUM ((0x00e6 << 2) + 0xff040000)
+//each 6bit ID, high 4bit are thread ID, low 2bits are the token
+//Bit 21:16 src1 ID
+//Bit 13:8 src2 ID
+//Bit 5:0 dst ID
+#define GE2D_TID_TOKEN ((0x00e7 << 2) + 0xff040000)
+//Bit 31:28 dst2_bytemask_val. 1-bit mask for each byte (8-bit). Applicable only if both dst_bitmask_en=1 and dst_bytemask_only=1.
+//Bit 27:26, dst2 picture struct, 00: frame, 10:top, 11: bottom
+//Bit 25:24, dst2 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 22:19 dst2 color_map
+// dst2_format=0 : output 8-bit;
+// dst2_format=1, dst2_color_map=1: output 16-bit YCbCr 655;
+// dst2_format=1, dst2_color_map=2: output 16-bit YCbCr 844;
+// dst2_format=1, dst2_color_map=3: output 16-bit YCbCrA 6442;
+// dst2_format=1, dst2_color_map=4: output 16-bit YCbCrA 4444;
+// dst2_format=1, dst2_color_map=5: output 16-bit YCbCr 565;
+// dst2_format=1, dst2_color_map=6: output 16-bit AYCbCr 4444;
+// dst2_format=1, dst2_color_map=7: output 16-bit AYCbCr 1555;
+// dst2_format=1, dst2_color_map=8: output 16-bit YCbCrA 4642;
+// dst2_format=1, dst2_color_map=9: output 16-bit CbCr 88;
+// dst2_format=1, dst2_color_map=10:output 16-bit CrCb 88;
+// dst2_format=2, dst2_color_map=0: output 24-bit YCbCr 888;
+// dst2_format=2, dst2_color_map=1: output 24-bit YCbCrA 5658;
+// dst2_format=2, dst2_color_map=2: output 24-bit AYCbCr 8565;
+// dst2_format=2, dst2_color_map=3: output 24-bit YCbCrA 6666;
+// dst2_format=2, dst2_color_map=4: output 24-bit AYCbCr 6666;
+// dst2_format=2, dst2_color_map=5: output 24-bit CrCbY 888;
+// dst2_format=3, dst2_color_map=0: output 32-bit YCbCrA 8888;
+// dst2_format=3, dst2_color_map=1: output 32-bit AYCbCr 8888;
+// dst2_format=3, dst2_color_map=2: output 32-bit ACrCbY 8888;
+// dst2_format=3, dst2_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 17:16 dst2_format, 00: 8bit, 01:16bit, 10:24bit, 11: 32bit
+//Bit 15 reserved
+//Bit 14 dst2_color_round_mode, 0: truncate, 1: + 0.5 rounding
+//Bit 13:12, dst2_x_discard_mode. 00: no discard; 10=discard even x; 11=discard odd x. Note: x is post reverse/rotation.
+//Bit 11:10, dst2_y_discard_mode. 00: no discard; 10=discard even y; 11=discard odd y. Note: y is post reverse/rotation.
+//Bit 9 reserved
+//Bit 8, dst2_enable. 0: disable dst2 (default); 1=enable dst2.
+//Bit 7: 6 reserved
+//Bit 5: 4, dst1_x_discard_mode. 00: no discard; 10=discard even x; 11=discard odd x. Note: x is post reverse/rotation.
+//Bit 3: 2, dst1_y_discard_mode. 00: no discard; 10=discard even y; 11=discard odd y. Note: y is post reverse/rotation.
+//Bit 1 reserved
+//Bit 0, dst1_enable. 0: disable dst1; 1=enable dst1 (default).
+#define GE2D_GEN_CTRL3 ((0x00e8 << 2) + 0xff040000)
+//Read only
+// Bit 13:0 ge2d_dst2_status, for debug only
+#define GE2D_STATUS2 ((0x00e9 << 2) + 0xff040000)
+//Bit 27:26 src1 Y fifo size control, 00: 512, 01: 256, 10: 128 11: 96
+//Bit 25:24 src2 fifo size control, 00: 512, 01: 256, 10: 128 11: 96
+//Bit 23:22 dst1 fifo size control, 00: 512, 01: 256, 10: 128 11: 64
+//Bit 21:20 dst2 fifo size control, 00: 512, 01: 256, 10: 128 11: 64
+//Bit 19:18, dst1 fifo burst control, 00: 24x64, 01: 32x64, 10: 48x64, 11:64x64
+//Bit 17:16, dst2 fifo burst control, 00: 24x64, 01: 32x64, 10: 48x64, 11:64x64
+//Bit 15:1, top_wrap_ctrl
+//bit 0, if true, disable bug fix about the dp_out_done/scale_out_done(test1823) hang issue when scaling down ratio is high.
+#define GE2D_GEN_CTRL4 ((0x00ea << 2) + 0xff040000)
+#define GE2D_GCLK_CTRL0 ((0x00ef << 2) + 0xff040000)
+#define GE2D_GCLK_CTRL1 ((0x00f0 << 2) + 0xff040000)
+#define GE2D_GEN_CTRL5 ((0x00f1 << 2) + 0xff040000)
+//Bit 28:20, pre_offset0
+//Bit 18:10, pre_offset1
+//Bit 8:0, pre_offset2
+#define GE2D_MATRIX2_PRE_OFFSET ((0x0090 << 2) + 0xff040000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define GE2D_MATRIX2_COEF00_01 ((0x0091 << 2) + 0xff040000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define GE2D_MATRIX2_COEF02_10 ((0x0092 << 2) + 0xff040000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define GE2D_MATRIX2_COEF11_12 ((0x0093 << 2) + 0xff040000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define GE2D_MATRIX2_COEF20_21 ((0x0094 << 2) + 0xff040000)
+//Bit 28:16 coef22
+//Bit 7 input y/cb/cr saturation enable
+//Bit 0 conversion matrix enable
+#define GE2D_MATRIX2_COEF22_CTRL ((0x0095 << 2) + 0xff040000)
+//Bit 28:20, offset0
+//Bit 18:10, offset1
+//Bit 8:0, offset2
+#define GE2D_MATRIX2_OFFSET ((0x0096 << 2) + 0xff040000)
+//Bit 19:0, src2 stride size in 64bits
+//
+//
+//Bit 28:20, pre_offset0
+//Bit 18:10, pre_offset1
+//Bit 8:0, pre_offset2
+#define GE2D_MATRIX3_PRE_OFFSET ((0x0097 << 2) + 0xff040000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define GE2D_MATRIX3_COEF00_01 ((0x0098 << 2) + 0xff040000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define GE2D_MATRIX3_COEF02_10 ((0x0099 << 2) + 0xff040000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define GE2D_MATRIX3_COEF11_12 ((0x009a << 2) + 0xff040000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define GE2D_MATRIX3_COEF20_21 ((0x009b << 2) + 0xff040000)
+//Bit 28:16 coef22
+//Bit 7 input y/cb/cr saturation enable
+//Bit 0 conversion matrix enable
+#define GE2D_MATRIX3_COEF22_CTRL ((0x009c << 2) + 0xff040000)
+//Bit 28:20, offset0
+//Bit 18:10, offset1
+//Bit 8:0, offset2
+#define GE2D_MATRIX3_OFFSET ((0x009d << 2) + 0xff040000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: ./ge2d_regs.h
+//
+//
+// Reading file: ./parser_regs.h
+//
+//
+//***************************************************************************
+// Title: parser.h
+//
+// Author: chong.gu
+//
+// Created: 17:15:11 06/08/2019
+//
+// Description:
+//
+// Note:
+//
+// History:
+//
+//***************************************************************************
+//-----------------------------------------------------------
+// PARSER
+//-----------------------------------------------------------
+// -----------------------------------------------
+// REG_BASE: PARSER_PCBUS_BASE = 0x38
+// -----------------------------------------------
+// bit 31:8 -- es_pack_size
+// bit 7:6 -- es_type 00-Video, 01-Audio, 10-Subtitle
+// bit 5 -- es_write
+// bit 4 -- es_passthrough
+// bit 3 -- insert_before_es_write
+// bit 2 -- discard_cmd
+// bit 1 -- search_cmd
+// bit 0 -- Parser Busy
+#define PARSER_CONTROL ((0x3860 << 2) + 0xfdf00000)
+// Write
+// bit 31:0 begin address for parser fetch
+// Read
+// 32 bit current fetch address
+#define PARSER_FETCH_ADDR ((0x3861 << 2) + 0xfdf00000)
+// Write
+// bit 31 circle buffer indicator
+// bit 30 check_buffer_stop_addr
+// bit 29:27 fetch endian
+// bit 26:0 buffer size ( Bytes )
+// Special command:
+// when bit 26:0 == 27'h0
+// then bit 29 -- stream_passthrough_enable
+// bit 28:27 -- stream_passthrough_type
+// Read
+// 6:5 cmd_rd_ptr
+// 4:3 cmd_wr_ptr
+// 2:0 cmd_number
+#define PARSER_FETCH_CMD ((0x3862 << 2) + 0xfdf00000)
+// 31:0 stop_fetch_addr
+#define PARSER_FETCH_STOP_ADDR ((0x3863 << 2) + 0xfdf00000)
+// 31:0 stop_fetch_addr - current_write_addr // read only
+#define PARSER_FETCH_LEVEL ((0x3864 << 2) + 0xfdf00000)
+// bit 31 - fetch_dma_urgent
+// bit 30 - stream_dma_urgent
+// bit 29 - force_pfifo_ren
+// bit 28 - pfifo_peak_enable
+// bit 27 - enable_free_clk_parser_reg
+// bit 26 -
+// bit 25:24 - parser_src_sel (00 - fetch, 01 - aux1, 10 - aux2 11 - aux3)
+// bit 23:16 - pfifo_empty_count
+// bit 15:12 - max_es_write_cycle (x16x64bits)
+// 11:10 - start code width ( 00-8bits, 01-16bits, 10-24bits, 11-32bits )
+// 9:8 - pfifo data access width ( 00-8bits, 01-16bits, 10-24bits, 11-32bits )
+// 7:0 - empty room for fetch data ( max_fetch_cycle ) x64 bits
+#define PARSER_CONFIG ((0x3865 << 2) + 0xfdf00000)
+// bit 24:16 -- pfifo_level
+// bit 9:0 -- point to byte address
+#define PFIFO_WR_PTR ((0x3866 << 2) + 0xfdf00000)
+// bit 9:0 -- point to byte address
+#define PFIFO_RD_PTR ((0x3867 << 2) + 0xfdf00000)
+// bit 31:0 -- 8/16/24/32 bits data acording to pfifo_data_width
+#define PFIFO_DATA ((0x3868 << 2) + 0xfdf00000)
+// bit 31:0 -- parser search pattern
+#define PARSER_SEARCH_PATTERN ((0x3869 << 2) + 0xfdf00000)
+// bit 31:0 -- parser search mask ( 0 - disable bit match test )
+#define PARSER_SEARCH_MASK ((0x386a << 2) + 0xfdf00000)
+// bit 31:16 -- parser_int_disable_count
+// bit 15:8 -- Parser interrupt enable for host cpu
+// bit 7:0 -- Parser interrupt enable for Amrisc
+#define PARSER_INT_ENABLE ((0x386b << 2) + 0xfdf00000)
+// Bit 7 -- fetch_cmd_finished
+// Bit 6:5 -- reserved
+// Bit 4 -- parse finished
+// Bit 3 -- discard finished
+// Bit 2 -- insert zero finished
+// Bit 1 -- Action Finished Except Search Start Code
+// Bit 0 -- Search match interrupt (StartCode found)
+// Read 7:0 int status
+// Write will clear (bit based)
+#define PARSER_INT_STATUS ((0x386c << 2) + 0xfdf00000)
+// 15 - SCR_32_READ_OUT (Read Only)
+// 14 - SCR_32_data_valid
+// 13 - SCR_32_data
+// 12 - SCR_count_en
+// 11:0 - SCR90K_DIV
+#define PARSER_SCR_CTL ((0x386d << 2) + 0xfdf00000)
+// bit 31:0 SCR value
+#define PARSER_SCR ((0x386e << 2) + 0xfdf00000)
+// bit 31:24 -- insert_loop_number
+// bit 23:21 --
+// bit 20:16 -- insert_byte_number
+// bit 15:0 -- discard number
+#define PARSER_PARAMETER ((0x386f << 2) + 0xfdf00000)
+// bit 31:0 -- insert data // write only
+// write to PARSER_CONTROL will reset the write position
+// continous write to this address can write upto 16 bytes
+#define PARSER_INSERT_DATA ((0x3870 << 2) + 0xfdf00000)
+// Bit 31:24 -- Reserved Stream_ID
+// Bit 23:16 -- Sub Stream_ID
+// Bit 15:8 -- Audio Stream_ID
+// Bit 7:0 -- Video Stream_ID
+#define VAS_STREAM_ID ((0x3871 << 2) + 0xfdf00000)
+// Bit 31:0 -- VIDEO_DTS
+#define VIDEO_DTS ((0x3872 << 2) + 0xfdf00000)
+// Bit 31:0 -- VIDEO_PTS
+#define VIDEO_PTS ((0x3873 << 2) + 0xfdf00000)
+// Bit 31:0 -- VIDEO_PTS_DTS_WR_PTR
+#define VIDEO_PTS_DTS_WR_PTR ((0x3874 << 2) + 0xfdf00000)
+// Bit 31:0 -- AUDIO_PTS
+#define AUDIO_PTS ((0x3875 << 2) + 0xfdf00000)
+// Bit 31:0 -- AUDIO_PTS_WR_PTR
+#define AUDIO_PTS_WR_PTR ((0x3876 << 2) + 0xfdf00000)
+// bit 31:20 -- stream_es_count ( Read Only)
+// bit 19 -- req_pending ( parser ddr_A_fifo ) (Read Only)
+// bit 18 -- stream_es_passthrough_enable
+// bit 17:16 -- stream_es_passthrough_type
+// bit 15:13 -- VIDEO2 Ees_write Endian
+// bit 12 -- VIDEO2 using manual read point
+// bit 11:9 -- SUB Ees_write Endian
+// bit 8 -- SUB using manual read point
+// bit 7:5 -- AUDIO Ees_write Endian
+// bit 4 -- AUDIO using manual read point
+// bit 3:1 -- VIDEO Ees_write Endian
+// bit 0 -- VIDEO using manual read point
+#define PARSER_ES_CONTROL ((0x3877 << 2) + 0xfdf00000)
+// Bit 31:0 PFIFO_MONITOR
+#define PFIFO_MONITOR ((0x3878 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_VIDEO DDR Interface
+// --------------------------------------------
+// The PARSER_VIDEO start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_VIDEO_START_PTR ((0x3880 << 2) + 0xfdf00000)
+#define PARSER_VIDEO_END_PTR ((0x3881 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_VIDEO Buffer Level Manager
+// --------------------------------------------
+#define PARSER_VIDEO_WP ((0x3882 << 2) + 0xfdf00000)
+#define PARSER_VIDEO_RP ((0x3883 << 2) + 0xfdf00000)
+#define PARSER_VIDEO_HOLE ((0x3884 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_AUDIO DDR Interface
+// --------------------------------------------
+// The PARSER_AUDIO start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_AUDIO_START_PTR ((0x3885 << 2) + 0xfdf00000)
+#define PARSER_AUDIO_END_PTR ((0x3886 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_AUDIO Buffer Level Manager
+// --------------------------------------------
+#define PARSER_AUDIO_WP ((0x3887 << 2) + 0xfdf00000)
+#define PARSER_AUDIO_RP ((0x3888 << 2) + 0xfdf00000)
+#define PARSER_AUDIO_HOLE ((0x3889 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_SUB DDR Interface
+// --------------------------------------------
+// The PARSER_SUB start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_SUB_START_PTR ((0x388a << 2) + 0xfdf00000)
+#define PARSER_SUB_END_PTR ((0x388b << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_SUB Buffer Level Manager
+// --------------------------------------------
+#define PARSER_SUB_WP ((0x388c << 2) + 0xfdf00000)
+#define PARSER_SUB_RP ((0x388d << 2) + 0xfdf00000)
+#define PARSER_SUB_HOLE ((0x388e << 2) + 0xfdf00000)
+// Bit[31] dma_busy
+// Bit[30] cur_fetch_or_es_write
+// Bit[29:28] reserved
+// Bit[27:24] fetch_status
+// Bit[23:0] buffer_cycles_left
+#define PARSER_FETCH_INFO ((0x388f << 2) + 0xfdf00000)
+// Bit[31:28] ctl_status
+// Bit[27:24] insert_byte_offset
+// Bit[23:0] es_pack_left_cycle
+#define PARSER_STATUS ((0x3890 << 2) + 0xfdf00000)
+// Bit [31:16] AUDIO_wrap_count
+// Bit [15:0] VIDEO_wrap_count
+#define PARSER_AV_WRAP_COUNT ((0x3891 << 2) + 0xfdf00000)
+// bit[29:24] A_brst_num_parser
+// bit[21:16] A_id_parser
+// bit[11:0] wrrsp_count_parser
+#define WRRSP_PARSER ((0x3892 << 2) + 0xfdf00000)
+// `define CSS_cmd 12'h200 // address of css command and indirect register
+// `define CSS_cntl 12'h201 // css control register
+// `define CSS_data 12'h202 // indirect register
+// `define CSS_id1_data 12'h203 // ID data for the first and second bytes
+// `define CSS_id2_data 12'h204 // ID data for the third and fourth bytes
+//CPPM registers
+// `define CPPM_IFIFO_CTRL 12'h210 //CPPM input FIFO control
+// `define CPPM_C2BC_KEY 12'h211 //CPPM C2 Block Cipher Key register
+// `define CPPM_C2BC_DIN 12'h212 //CPPM C2 Block Cipher data input register
+// `define CPPM_C2BC_DOUT 12'h213 //CPPM C2 Block Cipher data result register
+// `define CPPM_CMD 12'h214 //CPPM command and control register
+// `define CPPM_CTRL_STATUS 12'h215 //CPPM control status, mainly for debug
+// `define CPPM_IFIFO_DATA 12'h216 //CPPM input FIFO data pop port, just for debug
+// --------------------------------------------
+// PARSER_VIDEO2 DDR Interface
+// --------------------------------------------
+// The PARSER_VIDEO2 start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_VIDEO2_START_PTR ((0x3893 << 2) + 0xfdf00000)
+#define PARSER_VIDEO2_END_PTR ((0x3894 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_VIDEO2 Buffer Level Manager
+// --------------------------------------------
+#define PARSER_VIDEO2_WP ((0x3895 << 2) + 0xfdf00000)
+#define PARSER_VIDEO2_RP ((0x3896 << 2) + 0xfdf00000)
+#define PARSER_VIDEO2_HOLE ((0x3897 << 2) + 0xfdf00000)
+// Bit [31:16] AUDIO_wrap_count
+// Bit [15:0] VIDEO2_wrap_count
+#define PARSER_AV2_WRAP_COUNT ((0x3898 << 2) + 0xfdf00000)
+//-----------------------------------------------------------
+// PARSER_B
+//-----------------------------------------------------------
+// -----------------------------------------------
+// REG_BASE: PARSER_B_PCBUS_BASE = 0x11
+// -----------------------------------------------
+#define PARSER_B_PARSER_CONTROL ((0x1160 << 2) + 0xfdf00000)
+// Write
+// bit 31:0 begin address for parser fetch
+// Read
+// 32 bit current fetch address
+#define PARSER_B_PARSER_FETCH_ADDR ((0x1161 << 2) + 0xfdf00000)
+// Write
+// bit 31 circle buffer indicator
+// bit 30 check_buffer_stop_addr
+// bit 29:27 fetch endian
+// bit 26:0 buffer size ( Bytes )
+// Special command:
+// when bit 26:0 == 27'h0
+// then bit 29 -- stream_passthrough_enable
+// bit 28:27 -- stream_passthrough_type
+// Read
+// 6:5 cmd_rd_ptr
+// 4:3 cmd_wr_ptr
+// 2:0 cmd_number
+#define PARSER_B_PARSER_FETCH_CMD ((0x1162 << 2) + 0xfdf00000)
+// 31:0 stop_fetch_addr
+#define PARSER_B_PARSER_FETCH_STOP_ADDR ((0x1163 << 2) + 0xfdf00000)
+// 31:0 stop_fetch_addr - current_write_addr // read only
+#define PARSER_B_PARSER_FETCH_LEVEL ((0x1164 << 2) + 0xfdf00000)
+// bit 31 - fetch_dma_urgent
+// bit 30 - stream_dma_urgent
+// bit 29 - force_pfifo_ren
+// bit 28 - pfifo_peak_enable
+// bit 27 - enable_free_clk_parser_reg
+// bit 26 -
+// bit 25:24 - parser_src_sel (00 - fetch, 01 - aux1, 10 - aux2 11 - aux3)
+// bit 23:16 - pfifo_empty_count
+// bit 15:12 - max_es_write_cycle (x16x64bits)
+// 11:10 - start code width ( 00-8bits, 01-16bits, 10-24bits, 11-32bits )
+// 9:8 - pfifo data access width ( 00-8bits, 01-16bits, 10-24bits, 11-32bits )
+// 7:0 - empty room for fetch data ( max_fetch_cycle ) x64 bits
+#define PARSER_B_PARSER_CONFIG ((0x1165 << 2) + 0xfdf00000)
+// bit 24:16 -- pfifo_level
+// bit 9:0 -- point to byte address
+#define PARSER_B_PFIFO_WR_PTR ((0x1166 << 2) + 0xfdf00000)
+// bit 9:0 -- point to byte address
+#define PARSER_B_PFIFO_RD_PTR ((0x1167 << 2) + 0xfdf00000)
+// bit 31:0 -- 8/16/24/32 bits data acording to pfifo_data_width
+#define PARSER_B_PFIFO_DATA ((0x1168 << 2) + 0xfdf00000)
+// bit 31:0 -- parser search pattern
+#define PARSER_B_PARSER_SEARCH_PATTERN ((0x1169 << 2) + 0xfdf00000)
+// bit 31:0 -- parser search mask ( 0 - disable bit match test )
+#define PARSER_B_PARSER_SEARCH_MASK ((0x116a << 2) + 0xfdf00000)
+// bit 31:16 -- parser_int_disable_count
+// bit 15:8 -- Parser interrupt enable for host cpu
+// bit 7:0 -- Parser interrupt enable for Amrisc
+#define PARSER_B_PARSER_INT_ENABLE ((0x116b << 2) + 0xfdf00000)
+// Bit 7 -- fetch_cmd_finished
+// Bit 6:5 -- reserved
+// Bit 4 -- parse finished
+// Bit 3 -- discard finished
+// Bit 2 -- insert zero finished
+// Bit 1 -- Action Finished Except Search Start Code
+// Bit 0 -- Search match interrupt (StartCode found)
+// Read 7:0 int status
+// Write will clear (bit based)
+#define PARSER_B_PARSER_INT_STATUS ((0x116c << 2) + 0xfdf00000)
+// 15 - SCR_32_READ_OUT (Read Only)
+// 14 - SCR_32_data_valid
+// 13 - SCR_32_data
+// 12 - SCR_count_en
+// 11:0 - SCR90K_DIV
+#define PARSER_B_PARSER_SCR_CTL ((0x116d << 2) + 0xfdf00000)
+// bit 31:0 SCR value
+#define PARSER_B_PARSER_SCR ((0x116e << 2) + 0xfdf00000)
+// bit 31:24 -- insert_loop_number
+// bit 23:21 --
+// bit 20:16 -- insert_byte_number
+// bit 15:0 -- discard number
+#define PARSER_B_PARSER_PARAMETER ((0x116f << 2) + 0xfdf00000)
+// bit 31:0 -- insert data // write only
+// write to PARSER_CONTROL will reset the write position
+// continous write to this address can write upto 16 bytes
+#define PARSER_B_PARSER_INSERT_DATA ((0x1170 << 2) + 0xfdf00000)
+// Bit 31:24 -- Reserved Stream_ID
+// Bit 23:16 -- Sub Stream_ID
+// Bit 15:8 -- Audio Stream_ID
+// Bit 7:0 -- Video Stream_ID
+#define PARSER_B_VAS_STREAM_ID ((0x1171 << 2) + 0xfdf00000)
+// Bit 31:0 -- VIDEO_DTS
+#define PARSER_B_VIDEO_DTS ((0x1172 << 2) + 0xfdf00000)
+// Bit 31:0 -- VIDEO_PTS
+#define PARSER_B_VIDEO_PTS ((0x1173 << 2) + 0xfdf00000)
+// Bit 31:0 -- VIDEO_PTS_DTS_WR_PTR
+#define PARSER_B_VIDEO_PTS_DTS_WR_PTR ((0x1174 << 2) + 0xfdf00000)
+// Bit 31:0 -- AUDIO_PTS
+#define PARSER_B_AUDIO_PTS ((0x1175 << 2) + 0xfdf00000)
+// Bit 31:0 -- AUDIO_PTS_WR_PTR
+#define PARSER_B_AUDIO_PTS_WR_PTR ((0x1176 << 2) + 0xfdf00000)
+// bit 31:20 -- stream_es_count ( Read Only)
+// bit 19 -- req_pending ( parser ddr_A_fifo ) (Read Only)
+// bit 18 -- stream_es_passthrough_enable
+// bit 17:16 -- stream_es_passthrough_type
+// bit 15:13 -- VIDEO2 Ees_write Endian
+// bit 12 -- VIDEO2 using manual read point
+// bit 11:9 -- SUB Ees_write Endian
+// bit 8 -- SUB using manual read point
+// bit 7:5 -- AUDIO Ees_write Endian
+// bit 4 -- AUDIO using manual read point
+// bit 3:1 -- VIDEO Ees_write Endian
+// bit 0 -- VIDEO using manual read point
+#define PARSER_B_PARSER_ES_CONTROL ((0x1177 << 2) + 0xfdf00000)
+// Bit 31:0 PFIFO_MONITOR
+#define PARSER_B_PFIFO_MONITOR ((0x1178 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_VIDEO DDR Interface
+// --------------------------------------------
+// The PARSER_VIDEO start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_B_PARSER_VIDEO_START_PTR ((0x1180 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_VIDEO_END_PTR ((0x1181 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_VIDEO Buffer Level Manager
+// --------------------------------------------
+#define PARSER_B_PARSER_VIDEO_WP ((0x1182 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_VIDEO_RP ((0x1183 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_VIDEO_HOLE ((0x1184 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_AUDIO DDR Interface
+// --------------------------------------------
+// The PARSER_AUDIO start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_B_PARSER_AUDIO_START_PTR ((0x1185 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_AUDIO_END_PTR ((0x1186 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_AUDIO Buffer Level Manager
+// --------------------------------------------
+#define PARSER_B_PARSER_AUDIO_WP ((0x1187 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_AUDIO_RP ((0x1188 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_AUDIO_HOLE ((0x1189 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_SUB DDR Interface
+// --------------------------------------------
+// The PARSER_SUB start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_B_PARSER_SUB_START_PTR ((0x118a << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_SUB_END_PTR ((0x118b << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_SUB Buffer Level Manager
+// --------------------------------------------
+#define PARSER_B_PARSER_SUB_WP ((0x118c << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_SUB_RP ((0x118d << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_SUB_HOLE ((0x118e << 2) + 0xfdf00000)
+// Bit[31] dma_busy
+// Bit[30] cur_fetch_or_es_write
+// Bit[29:28] reserved
+// Bit[27:24] fetch_status
+// Bit[23:0] buffer_cycles_left
+#define PARSER_B_PARSER_FETCH_INFO ((0x118f << 2) + 0xfdf00000)
+// Bit[31:28] ctl_status
+// Bit[27:24] insert_byte_offset
+// Bit[23:0] es_pack_left_cycle
+#define PARSER_B_PARSER_STATUS ((0x1190 << 2) + 0xfdf00000)
+// Bit [31:16] AUDIO_wrap_count
+// Bit [15:0] VIDEO_wrap_count
+#define PARSER_B_PARSER_AV_WRAP_COUNT ((0x1191 << 2) + 0xfdf00000)
+// bit[29:24] A_brst_num_parser
+// bit[21:16] A_id_parser
+// bit[11:0] wrrsp_count_parser
+#define PARSER_B_WRRSP_PARSER ((0x1192 << 2) + 0xfdf00000)
+// `define CSS_cmd 12'h200 // address of css command and indirect register
+// `define CSS_cntl 12'h201 // css control register
+// `define CSS_data 12'h202 // indirect register
+// `define CSS_id1_data 12'h203 // ID data for the first and second bytes
+// `define CSS_id2_data 12'h204 // ID data for the third and fourth bytes
+//CPPM registers
+// `define CPPM_IFIFO_CTRL 12'h210 //CPPM input FIFO control
+// `define CPPM_C2BC_KEY 12'h211 //CPPM C2 Block Cipher Key register
+// `define CPPM_C2BC_DIN 12'h212 //CPPM C2 Block Cipher data input register
+// `define CPPM_C2BC_DOUT 12'h213 //CPPM C2 Block Cipher data result register
+// `define CPPM_CMD 12'h214 //CPPM command and control register
+// `define CPPM_CTRL_STATUS 12'h215 //CPPM control status, mainly for debug
+// `define CPPM_IFIFO_DATA 12'h216 //CPPM input FIFO data pop port, just for debug
+// --------------------------------------------
+// PARSER_VIDEO2 DDR Interface
+// --------------------------------------------
+// The PARSER_VIDEO2 start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_B_PARSER_VIDEO2_START_PTR ((0x1193 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_VIDEO2_END_PTR ((0x1194 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_VIDEO2 Buffer Level Manager
+// --------------------------------------------
+#define PARSER_B_PARSER_VIDEO2_WP ((0x1195 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_VIDEO2_RP ((0x1196 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_VIDEO2_HOLE ((0x1197 << 2) + 0xfdf00000)
+// Bit [31:16] AUDIO_wrap_count
+// Bit [15:0] VIDEO2_wrap_count
+#define PARSER_B_PARSER_AV2_WRAP_COUNT ((0x1198 << 2) + 0xfdf00000)
+//
+// Closing file: ./parser_regs.h
+//
+
+#define REG_BASE_VCBUS (0xff000000L)
+
+#include "soc_def.h"
+#endif // REGISTER_H
+
diff --git a/arch/arm/include/asm/arch-s4/regs.h b/arch/arm/include/asm/arch-s4/regs.h
new file mode 100644
index 0000000..3d7b9d9
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/regs.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AML_REG_H__
+#define __AML_REG_H__
+/*
+ * all used regs
+ */
+/*
+ * ISA_TIMERE use SYSCTRL_TIMERE
+ * WATCHDOG_CNTL use RESETCTRL_WATCHDOG_CTRL0
+ * WATCHDOG_TCNT use RESETCTRL_WATCHDOG_CNT
+ * WATCHDOG_RESET use RESETCTRL_WATCHDOG_CLR
+ */
+#define ISA_TIMERE ((0x0041 << 2) + 0xfe005800)
+#define WATCHDOG_CNTL ((0x0040 << 2) + 0xfe000000)
+#define WATCHDOG_TCNT ((0x0042 << 2) + 0xfe000000)
+#define WATCHDOG_RESET ((0x0043 << 2) + 0xfe000000)
+
+/*
+ * SEC_AO_SEC_GP_CFG0 use SYSCTRL_SEC_STATUS_REG4
+ * AO_SEC_GP_CFG0 use SYSCTRL_SEC_STATUS_REG4
+ * AO_RTI_STATUS_REG3 use SYSCTRL_SEC_STICKY_REG1
+ * AO_SEC_SD_CFG15 use SYSCTRL_SEC_STATUS_REG2
+ */
+//#define SEC_AO_SEC_GP_CFG0 ((0x00c4 << 2) + 0xfe005800)
+#define AO_SEC_GP_CFG0 ((0x00c4 << 2) + 0xfe005800)
+#define AO_RTI_STATUS_REG3 ((0x00e1 << 2) + 0xfe005800)
+
+/* PREG_STICKY_REG8 use SYSCTRL_STICKY_REG7
+ * P_AO_SEC_GP_CFG12 use SYSCTRL_DEBUG_REG6
+ * P_AO_SEC_GP_CFG13 use SYSCTRL_DEBUG_REG7
+ */
+#define PREG_STICKY_REG8 ((0x00b7 << 2) + 0xfe005800)
+#define P_AO_SEC_GP_CFG12 (volatile uint32_t *)((0x0096 << 2) + 0xfe005800)
+#define P_AO_SEC_GP_CFG13 (volatile uint32_t *)((0x0097 << 2) + 0xfe005800)
+
+/*
+ * P_AO_RTI_PINMUX_REG0 use PADCTRL_PIN_MUX_REG0
+ * P_AO_TIMEBASE_CNTL1 use CLKTREE_TIMEBASE_CTRL1
+ * AO_UART_WFIFO use UART_B_WFIFO
+ */
+#define P_AO_RTI_PINMUX_REG0 ((0x0000 << 2) + 0xfe000400)
+#define P_AO_TIMEBASE_CNTL1 ((0x0016 << 2) + 0xfe000800)
+#define AO_UART_WFIFO ((0x0000 << 2) + 0xfe002000)
+
+/*
+ * Not AO watch dog
+ */
+#define P_WATCHDOG_CNTL (volatile uint32_t *)(WATCHDOG_CNTL)
+#define P_WATCHDOG_TCNT (volatile uint32_t *)(WATCHDOG_TCNT)
+#define P_WATCHDOG_RESET (volatile uint32_t *)(WATCHDOG_RESET)
+#define P_ISA_TIMERE (volatile uint32_t *)(ISA_TIMERE)
+
+#endif /* __AML_REG_H__ */
diff --git a/arch/arm/include/asm/arch-s4/romboot.h b/arch/arm/include/asm/arch-s4/romboot.h
new file mode 100644
index 0000000..2967fbb
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/romboot.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOOT_ROM_H_
+#define __BOOT_ROM_H_
+#ifndef __ASSEMBLY__
+//#include <stdint.h>
+//uint8_t simple_i2c(uint8_t adr);
+//void spi_pin_mux(void);
+//void spi_init(void);
+//uint32_t spi_read(uint32_t src, uint32_t mem, uint32_t size);
+//void udelay(uint32_t usec);
+//void boot_des_decrypt(uint8_t *ct, uint8_t *pt, uint32_t size);
+
+#endif /* ! __ASSEMBLY__ */
+#include "config.h"
+
+/* Magic number to "boot" up A53 */
+#define AO_SEC_SD_CFG10_CB 0x80000000
+
+/*BOOT device and ddr size*/
+/*31-28: boot device id, 27-24: boot device para, 23-20: reserved*/
+/*19-8: ddr size, 7-0: board revision*/
+//#define P_AO_SEC_GP_CFG0 0xDA100240 //defined in secure_apb.h
+#define AO_SEC_GP_CFG7_W0_BIT 8
+#define AO_SEC_GP_CFG7_W0 0x100
+
+#define BOOT_ID_RESERVED 0
+#define BOOT_ID_EMMC 1
+#define BOOT_ID_NAND 2
+#define BOOT_ID_SPI 3
+#define BOOT_ID_SDCARD 4
+#define BOOT_ID_USB 5
+
+#endif /* __BOOT_ROM_H_ */
diff --git a/arch/arm/include/asm/arch-s4/sd_emmc.h b/arch/arm/include/asm/arch-s4/sd_emmc.h
new file mode 100644
index 0000000..d11e801
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/sd_emmc.h
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __SD_EMMC_H__
+#define __SD_EMMC_H__
+
+#include <mmc.h>
+
+#define SDIO_PORT_A 0
+#define SDIO_PORT_B 1
+#define SDIO_PORT_C 2
+
+#define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */
+#define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */
+
+#define MESON_SD_EMMC_CLOCK 0x00
+#define CLK_MAX_DIV GENMASK(5, 0)
+#define CLK_MAX_SRC GENMASK(7, 6)
+#define Cfg_div 0
+#define Cfg_src 6
+#define Cfg_co_phase 8
+#define Cfg_tx_phase 10
+#define Cfg_rx_phase 12
+#define Cfg_sram_pd 14
+#define Cfg_tx_delay 16
+#define Cfg_rx_delay 22
+#define Cfg_always_on 28
+#define Cfg_irq_sdio_sleep 29
+#define Cfg_irq_sdio_sleep_ds 30
+
+#define MESON_SD_EMMC_DELAY1 0x4
+#define DLY_D0_MASK GENMASK(5, 0)
+#define DLY_D1_MASK GENMASK(11, 6)
+#define DLY_D2_MASK GENMASK(17, 12)
+#define DLY_D3_MASK GENMASK(23, 18)
+#define DLY_D4_MASK GENMASK(31, 24)
+#define Dly_d0 0
+#define Dly_d1 6
+#define Dly_d2 12
+#define Dly_d3 18
+#define Dly_d4 24
+
+#define MESON_SD_EMMC_DELAY2 0x8
+#define DLY_D5_MASK GENMASK(5, 0)
+#define DLY_D6_MASK GENMASK(11, 6)
+#define DLY_D7_MASK GENMASK(17, 12)
+#define DLY_D8_MASK GENMASK(23, 18)
+#define DLY_D9_MASK GENMASK(31, 24)
+#define Dly_d5 0
+#define Dly_d6 6
+#define Dly_d7 12
+#define Dly_d8 18
+#define Dly_d9 24
+
+#define MESON_SD_EMMC_ADJUST 0xC
+#define CALI_SEL_MASK GENMASK(11, 8)
+#define ADJ_DLY_MASK GENMASK(21, 16)
+#define Cfg_cali_sel 8
+#define Cfg_cali_en 12
+#define Cfg_adj_en 13
+#define Cfg_cali_rise 14
+#define Cfg_ds_en 15
+#define Cfg_adj_dly 16
+#define Cfg_adj_auto 22
+#define Cfg_adj_init 23
+
+#define MESON_SD_EMMC_START 0x40
+#define CFG_DESC_INIT BIT(0)
+#define CFG_DESC_BUSY BIT(1)
+#define CFG_DESC_ADDR 2
+
+#define MESON_SD_EMMC_CFG 0x44
+#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
+#define CFG_BUS_WIDTH_1 0
+#define CFG_BUS_WIDTH_4 1
+#define CFG_BUS_WIDTH_8 2
+#define CFG_DDR BIT(2)
+#define CFG_BL_LEN_MASK GENMASK(7, 4)
+#define CFG_BL_LEN_SHIFT 4
+#define CFG_BL_LEN_512 (9 << 4)
+#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
+#define CFG_RESP_TIMEOUT_256 (8 << 8)
+#define CFG_RC_CC_MASK GENMASK(15, 12)
+#define CFG_RC_CC_16 (4 << 12)
+#define CFG_SDCLK_ALWAYS_ON BIT(18)
+#define CFG_AUTO_CLK BIT(23)
+
+#define MESON_SD_EMMC_STATUS 0x48
+#define STATUS_MASK GENMASK(15, 0)
+#define STATUS_ERR_MASK GENMASK(12, 0)
+#define STATUS_RXD_ERR_MASK GENMASK(7, 0)
+#define STATUS_TXD_ERR BIT(8)
+#define STATUS_DESC_ERR BIT(9)
+#define STATUS_RESP_ERR BIT(10)
+#define STATUS_RESP_TIMEOUT BIT(11)
+#define STATUS_DESC_TIMEOUT BIT(12)
+#define STATUS_END_OF_CHAIN BIT(13)
+
+#define MESON_SD_EMMC_IRQ_EN 0x4c
+
+#define MESON_SD_EMMC_CMD_CFG 0x50
+#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
+#define CMD_CFG_BLOCK_MODE BIT(9)
+#define CMD_CFG_R1B BIT(10)
+#define CMD_CFG_END_OF_CHAIN BIT(11)
+#define CMD_CFG_TIMEOUT_4S (12 << 12)
+#define CMD_CFG_NO_RESP BIT(16)
+#define CMD_CFG_NO_CMD BIT(17)
+#define CMD_CFG_DATA_IO BIT(18)
+#define CMD_CFG_DATA_WR BIT(19)
+#define CMD_CFG_RESP_NOCRC BIT(20)
+#define CMD_CFG_RESP_128 BIT(21)
+#define CMD_CFG_RESP_NUM BIT(22)
+#define CMD_CFG_DATA_NUM BIT(23)
+#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
+#define CMD_CFG_CMD_INDEX_SHIFT 24
+#define CMD_CFG_ERR BIT(30)
+#define CMD_CFG_OWNER BIT(31)
+
+#define MESON_SD_EMMC_CMD_ARG 0x54
+#define MESON_SD_EMMC_CMD_DAT 0x58
+#define MESON_SD_EMMC_CMD_RSP 0x5c
+#define MESON_SD_EMMC_CMD_RSP1 0x60
+#define MESON_SD_EMMC_CMD_RSP2 0x64
+#define MESON_SD_EMMC_CMD_RSP3 0x68
+
+#define SD_EMMC_RXD_ERROR (1 << 0)
+#define SD_EMMC_TXD_ERROR (1 << 1)
+#define SD_EMMC_DESC_ERROR (1 << 2)
+#define SD_EMMC_RESP_CRC_ERROR (1 << 3)
+#define SD_EMMC_RESP_TIMEOUT_ERROR (1 << 4)
+#define SD_EMMC_DESC_TIMEOUT_ERROR (1 << 5)
+
+//boot from sd or emmc
+/*this macro of SEC_AO_SEC_GP_CFG0 was defined in ./arch/arm/include/asm/arch-s4/soc_def.h */
+//#define SEC_AO_SEC_GP_CFG0 (SYSCTRL_SEC_STATUS_REG4)
+#endif
diff --git a/arch/arm/include/asm/arch-s4/secure_apb.h b/arch/arm/include/asm/arch-s4/secure_apb.h
new file mode 100644
index 0000000..ff4a0e8
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/secure_apb.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/register.h>
+
+#define DMA_BASE (uint32_t)(0xfe440400)
+
+#define DMA_T0 (uint32_t)(DMA_BASE + 0x00)
+#define DMA_T1 (uint32_t)(DMA_BASE + 0x04)
+#define DMA_T2 (uint32_t)(DMA_BASE + 0x08)
+#define DMA_T3 (uint32_t)(DMA_BASE + 0x0c)
+#define DMA_T4 (uint32_t)(DMA_BASE + 0x10)
+#define DMA_T5 (uint32_t)(DMA_BASE + 0x14)
+#define DMA_STS0 (uint32_t)(DMA_BASE + 0x20)
+#define DMA_STS1 (uint32_t)(DMA_BASE + 0x24)
+#define DMA_STS2 (uint32_t)(DMA_BASE + 0x28)
+#define DMA_STS3 (uint32_t)(DMA_BASE + 0x2c)
+#define DMA_STS4 (uint32_t)(DMA_BASE + 0x30)
+#define DMA_STS5 (uint32_t)(DMA_BASE + 0x34)
+#define DMA_CFG (uint32_t)(DMA_BASE + 0x40)
+#define DMA_SEC (uint32_t)(DMA_BASE + 0x44)
+#define DMA_END (uint32_t)(DMA_BASE + 0x3ff)
+
+#define P_DMA_T0 (volatile uint32_t *)(DMA_BASE + 0x00)
+#define P_DMA_T1 (volatile uint32_t *)(DMA_BASE + 0x04)
+#define P_DMA_T2 (volatile uint32_t *)(DMA_BASE + 0x08)
+#define P_DMA_T3 (volatile uint32_t *)(DMA_BASE + 0x0c)
+#define P_DMA_T4 (volatile uint32_t *)(DMA_BASE + 0x10)
+#define P_DMA_T5 (volatile uint32_t *)(DMA_BASE + 0x14)
+#define P_DMA_STS0 (volatile uint32_t *)(DMA_BASE + 0x20)
+#define P_DMA_STS1 (volatile uint32_t *)(DMA_BASE + 0x24)
+#define P_DMA_STS2 (volatile uint32_t *)(DMA_BASE + 0x28)
+#define P_DMA_STS3 (volatile uint32_t *)(DMA_BASE + 0x2c)
+#define P_DMA_STS4 (volatile uint32_t *)(DMA_BASE + 0x30)
+#define P_DMA_STS5 (volatile uint32_t *)(DMA_BASE + 0x34)
+#define P_DMA_CFG (volatile uint32_t *)(DMA_BASE + 0x40)
+#define P_DMA_SEC (volatile uint32_t *)(DMA_BASE + 0x44)
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-s4/soc_def.h b/arch/arm/include/asm/arch-s4/soc_def.h
new file mode 100644
index 0000000..a752096
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/soc_def.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __SC2_DEF_H__
+#define __SC2_DEF_H__
+
+#include "secure_apb.h"
+
+
+#define SEC_SYS_CPU_CFG2 CPUCTRL_SYS_CPU_CFG2
+
+#define SEC_AO_SEC_GP_CFG0 SYSCTRL_SEC_STATUS_REG4
+#define SEC_AO_SEC_GP_CFG2 SYSCTRL_SEC_STATUS_REG6
+#define SEC_AO_SEC_GP_CFG3 SYSCTRL_SEC_STATUS_REG15
+#define SEC_AO_SEC_GP_CFG4 SYSCTRL_SEC_STATUS_REG16
+#define SEC_AO_SEC_GP_CFG5 SYSCTRL_SEC_STATUS_REG17
+#define SEC_AO_SEC_GP_CFG7 SYSCTRL_SEC_STATUS_REG2
+#define SEC_AO_SEC_GP_CFG8 SYSCTRL_SEC_STATUS_REG10
+#define SEC_AO_SEC_GP_CFG9 SYSCTRL_SEC_STATUS_REG11
+
+
+#define AO_SEC_GP_CFG8 SYSCTRL_SEC_STATUS_REG10
+#define AO_SEC_GP_CFG9 SYSCTRL_SEC_STATUS_REG11
+#define SEC_AO_SEC_SD_CFG15 SYSCTRL_SEC_STATUS_REG31
+
+#define SEC_AO_RTI_STATUS_REG3 SYSCTRL_SEC_STICKY_REG1
+
+
+#define AO_SEC_SD_CFG15 SEC_AO_SEC_SD_CFG15
+
+#endif /* __SC2_DEF_H__ */
diff --git a/arch/arm/include/asm/arch-s4/timer.h b/arch/arm/include/asm/arch-s4/timer.h
new file mode 100644
index 0000000..492cc8d
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/timer.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __TIMER_H
+#define __TIMER_H
+
+#include <asm/arch/romboot.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/io.h>
+
+/**
+ * Get the current timestamp from the system timer.
+ */
+uint32_t get_time(void);
+
+/**
+ * Busy-wait.
+ *
+ * @param us Number of microseconds to delay.
+ */
+void _udelay(unsigned int us);
+
+#endif /* __TIMER_H */
diff --git a/arch/arm/include/asm/arch-s4/timing.h b/arch/arm/include/asm/arch-s4/timing.h
new file mode 100644
index 0000000..646eb75
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/timing.h
@@ -0,0 +1,316 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AML_TIMING_H_
+#define __AML_TIMING_H_
+
+#include <asm/arch/ddr_define.h>
+#include <asm/arch/types.h>
+//#include <asm/arch/mnPmuSramMsgBlock_ddr3.h>
+//#include <asm/arch/mnPmuSramMsgBlock_ddr4.h>
+//#include <asm/arch/mnPmuSramMsgBlock_ddr4_2d.h>
+//#include <asm/arch/mnPmuSramMsgBlock_lpddr3.h>
+//#include <asm/arch/mnPmuSramMsgBlock_lpddr4.h>
+//#include <asm/arch/mnPmuSramMsgBlock_lpddr4_2d.h>
+#include <asm/arch/dev_parameter.h>
+
+#define BL2_INIT_STAGE_0 0
+#define BL2_INIT_STAGE_1 1
+#define BL2_INIT_STAGE_2 2
+#define BL2_INIT_STAGE_3 3
+#define BL2_INIT_STAGE_4 4
+#define BL2_INIT_STAGE_5 5
+#define BL2_INIT_STAGE_6 6
+#define BL2_INIT_STAGE_7 7
+#define BL2_INIT_STAGE_8 8
+#define BL2_INIT_STAGE_9 9
+
+typedef struct bl2_reg {
+ unsigned int reg;
+ unsigned int value;
+ unsigned int mask;
+ unsigned short udelay;
+ unsigned char flag;
+ unsigned char rsv_0;
+}__attribute__ ((packed)) bl2_reg_t;
+
+typedef struct training_delay_set_ps{
+ unsigned char ac_trace_delay[10];
+ unsigned char ac_trace_delay_rev[2];
+ unsigned char read_dqs_delay[16];
+ unsigned char read_dq_bit_delay[72];
+ unsigned short write_dqs_delay[16];
+// */
+ unsigned short write_dq_bit_delay[72];
+ unsigned short read_dqs_gate_delay[16];
+ unsigned char soc_bit_vref[36];
+ unsigned char dram_bit_vref[32];
+ ///*
+ unsigned char rever1;//read_dqs read_dq,write_dqs, write_dq
+ unsigned char dfi_mrl;
+ unsigned char dfi_hwtmrl;
+ unsigned char ARdPtrInitVal;
+ unsigned short csr_vrefinglobal;
+ unsigned short csr_dqsrcvcntrl[4];
+ unsigned short csr_pptdqscntinvtrntg0[4];
+ unsigned short csr_pptdqscntinvtrntg1[4];
+ unsigned short csr_seq0bgpr[9];
+ unsigned short csr_dllgainctl;
+ unsigned short csr_dlllockpara;
+// unsigned short rever2;
+}__attribute__ ((packed)) training_delay_set_ps_t;
+
+typedef struct ddr_mrs_reg {
+ unsigned int cfg_ddr_mr[8];
+ unsigned int cfg_ddr_mr11;
+ unsigned int cfg_ddr_mr12;
+ unsigned int cfg_ddr_mr13;
+ unsigned int cfg_ddr_mr14;
+ unsigned int cfg_ddr_mr16;
+ unsigned int cfg_ddr_mr17;
+ unsigned int cfg_ddr_mr22;
+ unsigned int cfg_ddr_mr24;
+}__attribute__ ((packed)) ddr_mrs_reg_t;
+
+typedef struct ddr_timing{
+ unsigned int identifier;
+ unsigned int cfg_ddr_mrd;
+ unsigned int cfg_ddr_rfcab;
+ unsigned int cfg_ddr_rfcpb;
+ unsigned int cfg_ddr_rpab;
+ unsigned int cfg_ddr_rppb;
+ unsigned int cfg_ddr_rtw;
+ unsigned int cfg_ddr_rl;
+ unsigned int cfg_ddr_wl;
+ unsigned int cfg_ddr_ras;
+ unsigned int cfg_ddr_rc;
+ unsigned int cfg_ddr_rcd;
+ unsigned int cfg_ddr_rrds;
+ unsigned int cfg_ddr_rrdl;
+ unsigned int cfg_ddr_faw;
+ unsigned int cfg_ddr_rtp;
+ unsigned int cfg_ddr_wr;
+ unsigned int cfg_ddr_wtrs;
+ unsigned int cfg_ddr_wtrl;
+ unsigned int cfg_ddr_ccds;
+ unsigned int cfg_ddr_ccdl;
+ unsigned int cfg_ddr_exsr;
+ unsigned int cfg_ddr_xs;
+ unsigned int cfg_ddr_xp;
+ unsigned int cfg_ddr_xpdll;
+ unsigned int cfg_ddr_zqcs;
+ unsigned int cfg_ddr_cksre;
+ unsigned int cfg_ddr_cksrx;
+ unsigned int cfg_ddr_cke;
+ unsigned int cfg_ddr_mod;
+ unsigned int cfg_ddr_dqs;
+ unsigned int cfg_ddr_rstl;
+ unsigned int cfg_ddr_zqlat;
+ unsigned int cfg_ddr_mrr;
+ unsigned int cfg_ddr_ckesr;
+ unsigned int cfg_ddr_dpd;
+ unsigned int cfg_ddr_ckeck;
+ unsigned int cfg_ddr_refi;
+ unsigned int cfg_ddr_sr;
+ unsigned int cfg_ddr_ccdmw;
+ unsigned int cfg_ddr_escke;
+ unsigned int cfg_ddr_refi_ddr3;
+ unsigned int cfg_ddr_dfictrldelay;
+ unsigned int cfg_ddr_dfiphywrdata;
+ unsigned int cfg_ddr_dfiphywrlat;
+ unsigned int cfg_ddr_dfiphyrddataen;
+ unsigned int cfg_ddr_dfiphyrdlat;
+ unsigned int cfg_ddr_dfictrlupdmin;
+ unsigned int cfg_ddr_dfictrlupdmax;
+ unsigned int cfg_ddr_dfimstrresp;
+ unsigned int cfg_ddr_dfirefmski;
+ unsigned int cfg_ddr_dfictrlupdi;
+ unsigned int cfg_ddr_dfidramclk;
+ unsigned int cfg_ddr_dfilpresp;
+ unsigned int cfg_ddr_dfiphymstr;
+ unsigned int cfg_ddr_rtodt;
+ unsigned int cfg_ddr_wlmrd;
+ unsigned int cfg_ddr_wlo;
+ unsigned int cfg_ddr_al;
+ unsigned int cfg_ddr_zqcl;
+ unsigned int cfg_ddr_zqcsi;
+ unsigned int cfg_ddr_zqreset;
+ unsigned int cfg_ddr_tdqsck_min;
+ unsigned int cfg_ddr_tdqsck_max;
+ //training_delay_set_ps_t cfg_ddr_training_delay_ps;
+ ddr_mrs_reg_t cfg_ddr_mrs_reg_ps[2];
+ unsigned int dfi_odt1_config_ps[2];
+ //ddr_mrs_reg_t cfg_ddr_mrs_reg_ps1;
+ #if 0
+ unsigned int cfg_ddr_mr[8];
+ unsigned int cfg_ddr_mr11;
+ unsigned int cfg_ddr_mr12;
+ unsigned int cfg_ddr_mr13;
+ unsigned int cfg_ddr_mr14;
+ unsigned int cfg_ddr_mr16;
+ unsigned int cfg_ddr_mr17;
+ unsigned int cfg_ddr_mr22;
+ unsigned int cfg_ddr_mr24;
+ unsigned int cfg_ddr_reserve[5];
+ #endif
+}__attribute__ ((packed)) ddr_timing_t;
+
+typedef struct ddr_phy_common_extra_set{
+ unsigned short csr_pllctrl3;
+ unsigned short csr_pptctlstatic[4];
+ unsigned short csr_trainingincdecdtsmen[4];
+ unsigned short csr_tsmbyte0[4];
+ unsigned short csr_hwtcamode;
+ unsigned short csr_hwtlpcsena;
+ unsigned short csr_hwtlpcsenb;
+ unsigned short csr_acsmctrl13;
+ unsigned short csr_acsmctrl23;
+ unsigned char csr_soc_vref_dac1_dfe[36];
+}__attribute__ ((packed)) ddr_phy_common_extra_set_t;
+
+typedef struct retraining_set{
+ ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t;
+ training_delay_set_ps_t cfg_ddr_training_delay_ps;
+}__attribute__ ((packed)) retraining_set_t;
+
+typedef struct board_common_setting
+{
+unsigned int timming_magic;
+unsigned short timming_max_valid_configs;
+unsigned short timming_struct_version;
+unsigned short timming_struct_org_size;
+unsigned short timming_struct_real_size;
+unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test enable
+unsigned int ddr_func;
+unsigned char board_id;
+unsigned char DramType;
+unsigned char dram_rank_config;
+unsigned char DisabledDbyte;
+unsigned int dram_cs0_base_add;
+unsigned int dram_cs1_base_add;
+unsigned short dram_cs0_size_MB;
+unsigned short dram_cs1_size_MB;
+unsigned char dram_x4x8x16_mode;
+unsigned char Is2Ttiming;
+unsigned char log_level;
+unsigned char ddr_rdbi_wr_enable;
+unsigned int pll_ssc_mode;
+unsigned short org_tdqs2dq;
+unsigned char reserve1_test_function[2];
+unsigned int ddr_dmc_remap[5];
+unsigned char ac_pinmux[35];
+unsigned char ddr_dqs_swap;
+unsigned char ddr_dq_remap[36];
+unsigned int ddr_vddee_setting[4];//add,default-value,default-voltage,step
+}__attribute__ ((packed)) board_common_setting_t;
+
+typedef struct board_SI_setting_ps
+{
+unsigned short DRAMFreq;
+unsigned char PllBypassEn;
+unsigned char training_SequenceCtrl;
+unsigned short ddr_odt_config;
+unsigned char clk_drv_ohm;
+unsigned char cs_drv_ohm;
+unsigned char ac_drv_ohm;
+unsigned char soc_data_drv_ohm_p;
+unsigned char soc_data_drv_ohm_n;
+unsigned char soc_data_odt_ohm_p;
+unsigned char soc_data_odt_ohm_n;
+unsigned char dram_data_drv_ohm;
+unsigned char dram_data_odt_ohm;
+unsigned char dram_data_wr_odt_ohm;
+unsigned char dram_ac_odt_ohm;
+unsigned char dram_data_drv_pull_up_calibration_ohm;
+unsigned char lpddr4_dram_vout_voltage_range_setting;
+unsigned char dfe_offset;
+unsigned short vref_ac_permil; //phy
+unsigned short vref_soc_data_permil; //soc
+unsigned short vref_dram_data_permil;
+unsigned short max_core_timmming_frequency;
+unsigned short training_phase_parameter[2];
+unsigned short ac_trace_delay_org[36];
+}__attribute__ ((packed)) board_SI_setting_ps_t;
+
+typedef struct board_phase_setting_ps
+{
+unsigned short ac_trace_delay[36];
+unsigned short write_dqs_delay[8];
+unsigned short write_dq_bit_delay[72];
+unsigned short read_dqs_gate_delay[8];
+unsigned char read_dqs_delay[8];
+unsigned char read_dq_bit_delay[72];
+unsigned char soc_bit_vref[44];
+unsigned char dram_bit_vref[36];
+unsigned char reserve_training_parameter[16];//0-7 write dqs offset,8-15 read dqs offset,MSB bit 7 use 0 mean right offset
+unsigned char soc_bit_vref_dac1[44];
+}__attribute__ ((packed)) board_phase_setting_ps_t;
+
+typedef struct ddr_set
+{
+ board_common_setting_t cfg_board_common_setting;
+ board_SI_setting_ps_t cfg_board_SI_setting_ps[2];
+ board_phase_setting_ps_t cfg_ddr_training_delay_ps[2];
+}__attribute__ ((packed)) ddr_set_t;
+
+typedef struct ddr_set_ps0_only {
+ board_common_setting_t cfg_board_common_setting;
+ board_SI_setting_ps_t cfg_board_SI_setting_ps;
+ board_phase_setting_ps_t cfg_ddr_training_delay_ps;
+} __attribute__ ((packed)) ddr_set_ps0_only_t;
+
+typedef struct board_clk_set{
+ unsigned short cpu_clk;
+ unsigned short dsu_clk;
+ unsigned short vddee;
+ unsigned short vcck;
+ unsigned short pxp;
+ unsigned char axi_clk_div;
+ unsigned char low_console_baud;
+ unsigned char szPad[1];
+}__attribute__ ((packed)) board_clk_set_t;
+
+typedef struct pll_ctrl{
+ /*Enable flag: 0xa1:need set pll in bl2
+ 0xa2:need set pll in bl2x
+ other: no need
+ */
+ unsigned char flag;
+ /* Delay time for timing sequence in 10us, range [0 .. 255]*/
+ unsigned char delay_10u;
+ /* PLL clock
+ * syspll [93 .. 6000]
+ * fixpll [93 .. 6000]
+ * gp0pll [93 .. 6000]
+ * gp1pll [93 .. 6000]
+ * hifipll [375 .. 6000]
+ */
+ unsigned short clkset;
+ unsigned int pll_para[8];
+ unsigned int reserve;
+} __attribute__ ((packed)) pll_ctrl_t;
+
+typedef struct pll_set{
+ /*new struct for sc2*/
+ pll_ctrl_t sys_pll_ctrl;
+ pll_ctrl_t fix_pll_ctrl;
+ pll_ctrl_t gp0_pll_ctrl;
+ pll_ctrl_t gp1_pll_ctrl;
+ pll_ctrl_t hifi_pll_ctrl;
+}__attribute__ ((packed)) pll_set_t;
+
+typedef struct bl2_sec_parameter{
+ /*new struct for sc2*/
+ uint32_t version;
+ uint32_t bl31_region_start;
+ uint32_t bl31_region_size;
+ uint32_t bl32_region_start;
+ uint32_t bl32_region_size;
+
+ uint32_t RFU[27];
+}__attribute__ ((packed)) sec_parameter_t;
+
+
+#endif //__AML_TIMING_H_
diff --git a/arch/arm/include/asm/arch-s4/tsensor.h b/arch/arm/include/asm/arch-s4/tsensor.h
new file mode 100644
index 0000000..8b365a4
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/tsensor.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __TSENSOR_H__
+#define __TSENSOR_H__
+
+
+struct tsensor_cali_data {
+ unsigned int cmd; /* R/W */
+ unsigned int offset;
+ unsigned int size;
+ unsigned long buffer_phy;
+ unsigned long retcnt_phy;
+};
+
+
+#define CONFIG_HIGH_TEMP_COOL 90
+
+#define T_AVG_NUM 16 /*read temp cnt*/
+#define T_VER_MASK 0x80
+#define T_VALUE_MIN 0x1500
+#define T_VALUE_MAX 0x3500
+#define T_DLY_TIME 4500 /*update sensor register need 4.2ms*/
+
+#define T_CONTROL_DATA 0x62b
+#define T_TSCLK_DATA 0x130
+
+#define ts_b 3159
+#define ts_a 9411
+#define ts_m 424
+#define ts_n 324
+
+#ifdef CONFIG_AML_TSENSOR
+int temp_read_entry(void);
+int temp_trim_entry(int tempbase, int tempver);
+int temp_cooling_entry(void);
+#else
+int temp_read_entry(void)
+{
+ return -1;
+}
+int temp_trim_entry(int tempbase, int tempver)
+{
+ return -1;
+}
+int temp_cooling_entry(void)
+{
+ return 0;
+}
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-s4/types.h b/arch/arm/include/asm/arch-s4/types.h
new file mode 100644
index 0000000..2d362b1
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/types.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __TYPES_H
+#define __TYPES_H
+
+#ifndef _INT8_T_DECLARED
+typedef char int8_t;
+#define _INT8_T_DECLARED
+#endif
+
+#ifndef _INT16_T_DECLARED
+typedef short int16_t;
+#define _INT16_T_DECLARED
+#endif
+
+#ifndef _INT32_T_DECLARED
+typedef int int32_t;
+#define _INT32_T_DECLARED
+#endif
+
+#ifndef _INT64_T_DECLARED
+typedef long int64_t;
+#define _INT64_T_DECLARED
+#endif
+
+#ifndef _UINT8_T_DECLARED
+typedef unsigned char uint8_t;
+#define _UINT8_T_DECLARED
+#endif
+
+#ifndef _UINT16_T_DECLARED
+typedef unsigned short uint16_t;
+#define _UINT16_T_DECLARED
+#endif
+
+#ifndef _UINT32_T_DECLARED
+typedef unsigned int uint32_t;
+#define _UINT32_T_DECLARED
+#endif
+
+#ifndef _UINT64_T_DECLARED
+typedef unsigned long uint64_t;
+#define _UINT64_T_DECLARED
+#endif
+
+#ifndef _INT8PTR_T_DECLARED
+typedef char * int8ptr_t;
+#define _INT8PTR_T_DECLARED
+#endif
+
+#ifndef _INT16PTR_T_DECLARED
+typedef short * int16ptr_t;
+#define _INT16PTR_T_DECLARED
+#endif
+
+#ifndef _INT32PTR_T_DECLARED
+typedef int * int32ptr_t;
+#define _INT32PTR_T_DECLARED
+#endif
+
+#ifndef _INT64PTR_T_DECLARED
+typedef long * int64ptr_t;
+#define _INT64PTR_T_DECLARED
+#endif
+
+#ifndef _UINT8PTR_T_DECLARED
+typedef unsigned char * uint8ptr_t;
+#define _UINT8PTR_T_DECLARED
+#endif
+
+#ifndef _UINT16PTR_T_DECLARED
+typedef unsigned short * uint16ptr_t;
+#define _UINT16PTR_T_DECLARED
+#endif
+
+#ifndef _UINT32PTR_T_DECLARED
+typedef unsigned int * uint32ptr_t;
+#define _UINT32PTR_T_DECLARED
+#endif
+
+#ifndef _UINT64PTR_T_DECLARED
+typedef unsigned long * uint64ptr_t;
+#define _UINT64PTR_T_DECLARED
+#endif
+
+#endif
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-s4/uart.h b/arch/arm/include/asm/arch-s4/uart.h
new file mode 100644
index 0000000..757dc91
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/uart.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __MESON_FIRM_UART_H_
+#define __MESON_FIRM_UART_H_
+#include <config.h>
+#include <common.h>
+#include "register.h"
+//#include "io.h"
+#include <asm/arch/secure_apb.h>
+
+#ifndef CONFIG_CONS_INDEX
+#error Please define CONFIG_CONS_INDEX==[0|1]
+#endif
+
+#if CONFIG_CONS_INDEX==0
+#define UART_PORT_CONS UART_PORT_0
+#elif CONFIG_CONS_INDEX==1
+#define UART_PORT_CONS UART_PORT_1
+#elif CONFIG_CONS_INDEX==2
+#define UART_PORT_CONS UART_PORT_AO
+#define USE_AO_UART 1
+#else
+#error Please define CONFIG_CONS_INDEX==[0|1]
+#endif
+/*
+#define UART_PORT_0 CBUS_REG_ADDR(UART0_WFIFO)
+#define UART_PORT_1 CBUS_REG_ADDR(UART1_WFIFO)
+#define UART_PORT_2 CBUS_REG_ADDR(UART2_WFIFO)
+#define UART_PORT_AO P_AO_UART_WFIFO
+
+#define UART_WFIFO (0<<2)
+#define UART_RFIFO (1<<2)
+#define UART_CONTROL (2<<2)
+#define UART_STATUS (3<<2)
+#define UART_MISC (4<<2)
+*/
+
+#include "clock.h"
+
+#define UART_CLK_SRC CLK81
+#define UART_PORT_0 0xfe001c00
+#define UART_PORT_1 0xfe001c00
+#define UART_PORT_AO 0xfe001c00
+#define UART_WFIFO 0
+#define UART_RFIFO 1
+#define UART_CONTROL 2
+#define UART_STATUS 3
+#define UART_MISC 4
+
+#if USE_AO_UART == 1
+#define P_UART(uart_base,reg) (uart_base + (reg<<2))
+#else
+#define P_UART(uart_base,reg) CBUS_REG_ADDR(uart_base+reg)
+#endif
+#define P_UART_WFIFO(uart_base) P_UART(uart_base,UART_WFIFO)
+#define P_UART_RFIFO(uart_base) P_UART(uart_base,UART_RFIFO)
+
+#define P_UART_CONTROL(uart_base) P_UART(uart_base,UART_CONTROL)
+ #define UART_CNTL_MASK_BAUD_RATE (0xfff)
+ #define UART_CNTL_MASK_TX_EN (1<<12)
+ #define UART_CNTL_MASK_RX_EN (1<<13)
+ #define UART_CNTL_MASK_2WIRE (1<<15)
+ #define UART_CNTL_MASK_STP_BITS (3<<16)
+ #define UART_CNTL_MASK_STP_1BIT (0<<16)
+ #define UART_CNTL_MASK_STP_2BIT (1<<16)
+ #define UART_CNTL_MASK_PRTY_EVEN (0<<18)
+ #define UART_CNTL_MASK_PRTY_ODD (1<<18)
+ #define UART_CNTL_MASK_PRTY_TYPE (1<<18)
+ #define UART_CNTL_MASK_PRTY_EN (1<<19)
+ #define UART_CNTL_MASK_CHAR_LEN (3<<20)
+ #define UART_CNTL_MASK_CHAR_8BIT (0<<20)
+ #define UART_CNTL_MASK_CHAR_7BIT (1<<20)
+ #define UART_CNTL_MASK_CHAR_6BIT (2<<20)
+ #define UART_CNTL_MASK_CHAR_5BIT (3<<20)
+ #define UART_CNTL_MASK_RST_TX (1<<22)
+ #define UART_CNTL_MASK_RST_RX (1<<23)
+ #define UART_CNTL_MASK_CLR_ERR (1<<24)
+ #define UART_CNTL_MASK_INV_RX (1<<25)
+ #define UART_CNTL_MASK_INV_TX (1<<26)
+ #define UART_CNTL_MASK_RINT_EN (1<<27)
+ #define UART_CNTL_MASK_TINT_EN (1<<28)
+ #define UART_CNTL_MASK_INV_CTS (1<<29)
+ #define UART_CNTL_MASK_MASK_ERR (1<<30)
+ #define UART_CNTL_MASK_INV_RTS (1<<31)
+#define P_UART_STATUS(uart_base) P_UART(uart_base,UART_STATUS )
+ #define UART_STAT_MASK_RFIFO_CNT (0x7f<<0)
+ #define UART_STAT_MASK_TFIFO_CNT (0x7f<<8)
+ #define UART_STAT_MASK_PRTY_ERR (1<<16)
+ #define UART_STAT_MASK_FRAM_ERR (1<<17)
+ #define UART_STAT_MASK_WFULL_ERR (1<<18)
+ #define UART_STAT_MASK_RFIFO_FULL (1<<19)
+ #define UART_STAT_MASK_RFIFO_EMPTY (1<<20)
+ #define UART_STAT_MASK_TFIFO_FULL (1<<21)
+ #define UART_STAT_MASK_TFIFO_EMPTY (1<<22)
+ #define UART_STAT_MASK_XMIT_BUSY (1<<25)
+ #define UART_STAT_MASK_RECV_BUSY (1<<26)
+#define P_UART_MISC(uart_base) P_UART(uart_base,UART_MISC )
+
+
+#ifndef CONFIG_SERIAL_STP_BITS
+#define CONFIG_SERIAL_STP_BITS 1 // 1 , 2
+#endif
+#if CONFIG_SERIAL_STP_BITS==1
+#define UART_STP_BIT UART_CNTL_MASK_STP_1BIT
+#elif CONFIG_SERIAL_STP_BITS==2
+#define UART_STP_BIT UART_CNTL_MASK_STP_2BIT
+#else
+#error CONFIG_SERIAL_STP_BITS wrong
+#endif
+
+
+#ifndef CONFIG_SERIAL_PRTY_TYPE
+#define CONFIG_SERIAL_PRTY_TYPE 0 //0 ,2 ,3
+#endif
+#if CONFIG_SERIAL_PRTY_TYPE==0
+#define UART_PRTY_BIT 0
+#elif CONFIG_SERIAL_PRTY_TYPE==2
+#define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_EVEN)
+#elif CONFIG_SERIAL_PRTY_TYPE==3
+#define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_ODD)
+#else
+#error CONFIG_SERIAL_PRTY_TYPE wrong
+#endif
+
+#ifndef CONFIG_SERIAL_CHAR_LEN
+#define CONFIG_SERIAL_CHAR_LEN 8 //5,6,7,8
+#endif
+#if CONFIG_SERIAL_CHAR_LEN==5
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_5BIT
+#elif CONFIG_SERIAL_CHAR_LEN==6
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_6BIT
+#elif CONFIG_SERIAL_CHAR_LEN==7
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_7BIT
+#elif CONFIG_SERIAL_CHAR_LEN==8
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_8BIT
+#else
+#error CONFIG_SERIAL_CHAR_LEN wrong
+#endif
+#define UART_CONTROL_SET(baud,clk81) \
+ (((clk81)/(baud*4) -1) \
+ | UART_STP_BIT \
+ | UART_PRTY_BIT \
+ | UART_CHAR_LEN \
+ | UART_CNTL_MASK_TX_EN \
+ | UART_CNTL_MASK_RX_EN \
+ | UART_CNTL_MASK_RST_TX \
+ | UART_CNTL_MASK_RST_RX \
+ | UART_CNTL_MASK_CLR_ERR )
+#endif
diff --git a/arch/arm/include/asm/arch-s4/usb.h b/arch/arm/include/asm/arch-s4/usb.h
new file mode 100644
index 0000000..f2669d5
--- /dev/null
+++ b/arch/arm/include/asm/arch-s4/usb.h
@@ -0,0 +1,246 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __ARCH_ARM_MESON_USB_H_U_BOOT__
+#define __ARCH_ARM_MESON_USB_H_U_BOOT__
+
+#include <common.h>
+#include <asm/types.h>
+#include <asm/arch/io.h>
+#include <asm/arch/secure_apb.h>
+#include <generic-phy.h>
+#include <asm-generic/gpio.h>
+
+#define USB_PHY_PORT_MAX 1
+/* Phy register MACRO definitions */
+
+#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
+#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
+#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27)
+
+#define PHYUTMI_OTGDISABLE (1 << 6)
+#define PHYUTMI_FORCESUSPEND (1 << 1)
+#define PHYUTMI_FORCESLEEP (1 << 0)
+
+#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
+#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
+
+#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
+#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
+
+#define PHYCLKRST_SSC_EN (0x1 << 20)
+#define PHYCLKRST_REF_SSP_EN (0x1 << 19)
+#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18)
+
+#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
+
+#define PHYCLKRST_FSEL_MASK (0x3f << 5)
+#define PHYCLKRST_FSEL(_x) ((_x) << 5)
+#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
+#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
+#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
+#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
+
+#define PHYCLKRST_RETENABLEN (0x1 << 4)
+
+#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
+#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
+#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
+
+#define PHYCLKRST_PORTRESET (0x1 << 1)
+#define PHYCLKRST_COMMONONN (0x1 << 0)
+
+#define PHYPARAM0_REF_USE_PAD (0x1 << 31)
+#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
+#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
+
+#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
+#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
+
+#define PHYTEST_POWERDOWN_SSP (0x1 << 3)
+#define PHYTEST_POWERDOWN_HSP (0x1 << 2)
+
+#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2)
+
+#define FSEL_CLKSEL_24M (0x5)
+
+#define USB_PHY2_ENABLE 0x10000000
+#define USB_PHY2_RESET 0x20000000
+
+/* XHCI PHY register structure */
+#define PHY_REGISTER_SIZE 0x20
+
+struct phy_aml_usb2_priv {
+ unsigned int base_addr;
+ unsigned int reset_addr;
+ unsigned int dwc2_a_addr;
+ unsigned int u2_port_num;
+ unsigned int usbphy_reset_bit[8];
+ unsigned int usb_phy2_pll_base_addr[4];
+};
+
+struct phy_aml_usb3_priv {
+ unsigned int base_addr;
+ unsigned int usb3_port_num;
+ struct gpio_desc desc;
+};
+
+/* Register definitions */
+typedef struct u2p_aml_regs {
+ volatile uint32_t u2p_r0;
+ volatile uint32_t u2p_r1;
+} u2p_aml_regs_t;
+
+typedef union u2p_r0 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned host_device:1;
+ unsigned power_ok:1;
+ unsigned hast_mode:1;
+ unsigned POR:1;
+ unsigned IDPULLUP0:1;
+ unsigned DRVVBUS0:1;
+ unsigned reserved:26;
+ } b;
+} u2p_r0_t;
+
+typedef union u2p_r1 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned phy_rdy:1;
+ unsigned IDDIG0:1;
+ unsigned OTGSESSVLD0:1;
+ unsigned VBUSVALID0:1;
+ unsigned reserved:28;
+ } b;
+} u2p_r1_t;
+
+
+typedef struct usb_aml_regs {
+ volatile uint32_t usb_r0;
+ volatile uint32_t usb_r1;
+ volatile uint32_t usb_r2;
+ volatile uint32_t usb_r3;
+ volatile uint32_t usb_r4;
+ volatile uint32_t usb_r5;
+} usb_aml_regs_t;
+
+typedef union usb_r0 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned reserved:17;
+ unsigned p30_lane0_tx2rx_loopback:1;
+ unsigned p30_lane0_ext_pclk_reg:1;
+ unsigned p30_pcs_rx_los_mask_val:10;
+ unsigned u2d_ss_scaledown_mode:2;
+ unsigned u2d_act:1;
+ } b;
+} usb_r0_t;
+
+typedef union usb_r1 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned u3h_bigendian_gs:1;
+ unsigned u3h_pme_en:1;
+ unsigned u3h_hub_port_overcurrent:3;
+ unsigned reserved_1:2;
+ unsigned u3h_hub_port_perm_attach:3;
+ unsigned reserved_2:2;
+ unsigned u3h_host_u2_port_disable:2;
+ unsigned reserved_3:2;
+ unsigned u3h_host_u3_port_disable:1;
+ unsigned u3h_host_port_power_control_present:1;
+ unsigned u3h_host_msi_enable:1;
+ unsigned u3h_fladj_30mhz_reg:6;
+ unsigned p30_pcs_tx_swing_full:7;
+ } b;
+} usb_r1_t;
+
+typedef union usb_r2 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned reserved:20;
+ unsigned p30_pcs_tx_deemph_3p5db:6;
+ unsigned p30_pcs_tx_deemph_6db:6;
+ } b;
+} usb_r2_t;
+
+typedef union usb_r3 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned p30_ssc_en:1;
+ unsigned p30_ssc_range:3;
+ unsigned p30_ssc_ref_clk_sel:9;
+ unsigned p30_ref_ssp_en:1;
+ unsigned reserved:18;
+ } b;
+} usb_r3_t;
+
+typedef union usb_r4 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned p21_PORTRESET0:1;
+ unsigned p21_SLEEPM0:1;
+ unsigned mem_pd:2;
+ unsigned p21_only:1;
+ unsigned reserved:27;
+ } b;
+} usb_r4_t;
+
+typedef union usb_r5 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned iddig_sync:1;
+ unsigned iddig_reg:1;
+ unsigned iddig_cfg:2;
+ unsigned iddig_en0:1;
+ unsigned iddig_en1:1;
+ unsigned iddig_curr:1;
+ unsigned usb_iddig_irq:1;
+ unsigned iddig_th:8;
+ unsigned iddig_cnt:8;
+ unsigned reserved:8;
+ } b;
+} usb_r5_t;
+
+/* usb id mode, only after M2
+ mode = 0 : HARDWARE
+ mode = 1 : SW_HOST
+ mode = 2 : SW_DEVICE
+ */
+#define USB_ID_MODE_HARDWARE (1)
+#define USB_ID_MODE_SW_HOST (2)
+#define USB_ID_MODE_SW_DEVICE (3)
+int usb2_phy_tuning(uint32_t phy2_pll_base, int port);
+void set_usb_pll(uint32_t phy2_pll_base);
+int usb_save_phy_dev (unsigned int number, struct phy *phy);
+int usb2_phy_init (struct phy *phy);
+unsigned int usb_get_dwc_a_base_addr(void);
+unsigned int usb_get_device_mode_phy_base(void);
+void usb_phy_tuning_reset(void);
+void usb_device_mode_init(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-sc2/acs.h b/arch/arm/include/asm/arch-sc2/acs.h
new file mode 100644
index 0000000..7727f14
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/acs.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __ACS_H
+#define __ACS_H
+
+#define CHIP_PARAM_MAGIC 0x50696863 //"chiP"
+#define DEV_PARAM_MAGIC 0x50766564 //"devP"
+
+#define CHIP_PARAM_VERSION 0x1
+#define DEV_PARAM_VERSION 0x1
+
+#ifndef __ASSEMBLY__
+
+typedef struct dev_param_hdr {
+ unsigned int magic;
+ unsigned int version;
+
+ char bl2_regs_magic[6];
+ unsigned short bl2_regs_length;
+
+ char board_clk_magic[6];
+ unsigned short board_clk_length;
+
+ char opt_reg_magic[6];
+ unsigned short opt_reg_length;
+
+ char sto_set_magic[6];
+ unsigned short sto_set_length;
+
+ char ddr_set_magic[6];
+ unsigned short ddr_set_length;
+
+ unsigned int RFU[4];
+} __attribute__ ((packed)) dev_param_hdr_t;
+
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-sc2/bl31_apis.h b/arch/arm/include/asm/arch-sc2/bl31_apis.h
new file mode 100644
index 0000000..4143f40
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/bl31_apis.h
@@ -0,0 +1,170 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ * Trustzone API
+ *
+ * Copyright (C) 2012 Amlogic, Inc.
+ *
+ * Author: Platform-SH@amlogic.com
+ *
+ */
+
+#ifndef __GXBB_BL31_APIS_H
+#define __GXBB_BL31_APIS_H
+
+#include <asm/arch/io.h>
+
+/*#define SRAM_READ 0x82000010
+#define CORE_RD_REV1 0x82000011
+#define SRAM_ACS_READ 0x82000012
+#define SRAM_ACS_INDIRECT_READ 0x82000013*/
+
+#define GET_SHARE_MEM_INPUT_BASE 0x82000020
+#define GET_SHARE_MEM_OUTPUT_BASE 0x82000021
+#define GET_REBOOT_REASON 0x82000022
+#define GET_SHARE_STORAGE_IN_BASE 0x82000023
+#define GET_SHARE_STORAGE_OUT_BASE 0x82000024
+#define GET_SHARE_STORAGE_BLOCK_BASE 0x82000025
+#define GET_SHARE_STORAGE_MESSAGE_BASE 0x82000026
+#define GET_SHARE_STORAGE_BLOCK_SIZE 0x82000027
+#define SET_STORAGE_INFO 0x82000028
+#define SET_STORAGE_BOOTSEQUENCE 0x82000029
+#define SET_REBOOT_REASON 0x82000049
+
+/* Set Reboot Reason then Reboot*/
+#define PSCI_SYS_REBOOT 0x84000009
+
+/* SECUREOS DEFINITION*/
+/* SMC Identifiers for non-secure world functions */
+#define CALL_TRUSTZONE_HAL_API 0x5
+
+/* EFUSE */
+#define EFUSE_READ 0x82000030
+#define EFUSE_WRITE 0x82000031
+#define EFUSE_WRITE_PATTERN 0x82000032
+#define EFUSE_USER_MAX 0x82000033
+
+#define DEBUG_EFUSE_WRITE_PATTERN 0x820000F0
+#define DEBUG_EFUSE_READ_PATTERN 0x820000F1
+
+/* JTAG*/
+#define JTAG_ON 0x82000040
+#define JTAG_OFF 0x82000041
+
+#define SET_USB_BOOT_FUNC 0x82000043
+ /* USB BOOT FUNC sub command list*/
+ #define CLEAR_USB_BOOT 1
+ #define FORCE_USB_BOOT 2
+ #define RUN_COMD_USB_BOOT 3
+ #define PANIC_DUMP_USB_BOOT 4
+
+#define GET_CHIP_ID 0x82000044
+
+/* tsensor calibration data */
+#define TSENSOR_CALI_SET 0x8200004C
+
+/*oscring efuse value get */
+#define OSCRING_EFUSE_GET 0x8200004D
+/* Security Key*/
+#define SECURITY_KEY_QUERY 0x82000060
+#define SECURITY_KEY_READ 0x82000061
+#define SECURITY_KEY_WRITE 0x82000062
+#define SECURITY_KEY_TELL 0x82000063
+#define SECURITY_KEY_VERIFY 0x82000064
+#define SECURITY_KEY_STATUS 0x82000065
+#define SECURITY_KEY_NOTIFY 0x82000066
+#define SECURITY_KEY_LIST 0x82000067
+#define SECURITY_KEY_REMOVE 0x82000068
+#define SECURITY_KEY_NOTIFY_EX 0x82000069
+#define SECURITY_KEY_SET_ENCTYPE 0x8200006A
+#define SECURITY_KEY_GET_ENCTYPE 0x8200006B
+#define SECURITY_KEY_VERSION 0x8200006C
+
+/*viu probe en*/
+#define VIU_PREOBE_EN 0x82000080
+/*set boot first timeout*/
+#define SET_BOOT_FIRST 0x82000087
+
+/* KEYMASTER */
+#define SET_BOOT_PARAMS 0x82000072
+#define SHA256_DIGEST_SIZE 32
+typedef struct {
+ uint32_t device_locked;
+ uint32_t verified_boot_state;
+ uint8_t verified_boot_key[SHA256_DIGEST_SIZE];
+ uint8_t verified_boot_hash[SHA256_DIGEST_SIZE];
+} keymaster_boot_params;
+
+/* Secure HAL APIs */
+#define TRUSTZONE_HAL_API_SRAM 0x400
+
+/*start hifi4 */
+#define START_HIFI4 0x82000090
+#define DSP_SEC_POWERSET 0x82000092
+
+
+#define SRAM_HAL_API_CHECK_EFUSE 0x403
+struct sram_hal_api_arg {
+ unsigned int cmd;
+ unsigned int req_len;
+ unsigned int res_len;
+ unsigned long req_phy_addr;
+ unsigned long res_phy_addr;
+ unsigned long ret_phy_addr;
+};
+
+#define JTAG_STATE_ON 0
+#define JTAG_STATE_OFF 1
+#define JTAG_M3_AO 0
+#define JTAG_M3_EE 1
+#define JTAG_A53_AO 2
+#define JTAG_A53_EE 3
+#define CLUSTER_BIT 2
+
+
+/* AVB2 */
+#define GET_AVBKEY_FROM_FIP 0x820000b0
+
+/////////////////////////////////////////////////////////////////////////////////
+#define AML_DATA_PROCESS (0x820000FF)
+ #define AML_D_P_W_EFUSE_SECURE_BOOT (0x10)
+ #define AML_D_P_W_EFUSE_PASSWORD (0x11)
+ #define AML_D_P_W_EFUSE_CUSTOMER_ID (0x12)
+ #define AML_D_P_W_EFUSE_AMLOGIC (0x20)
+ #define AML_D_P_IMG_DECRYPT (0x40)
+ #define AML_D_P_UPGRADE_CHECK (0x80)
+
+#define GXB_EFUSE_PATTERN_SIZE (0x5 << 9)
+#define GXB_IMG_SIZE (24<<20)
+#define GXB_IMG_LOAD_ADDR (0x1080000)
+ #define GXB_IMG_DEC_KNL (1<<0)
+ #define GXB_IMG_DEC_RMD (1<<1)
+ #define GXB_IMG_DEC_DTB (1<<2)
+ #define GXB_IMG_DEC_ALL (GXB_IMG_DEC_KNL|GXB_IMG_DEC_RMD|GXB_IMG_DEC_DTB)
+
+#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+void aml_set_jtag_state(unsigned state, unsigned select);
+unsigned aml_get_reboot_reason(void);
+unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2);
+void aml_set_bootsequence(uint32_t val);
+void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2);
+unsigned long aml_sec_boot_check(unsigned long ,unsigned long ,unsigned long,unsigned long );
+long get_sharemem_info(unsigned long);
+void set_usb_boot_function(unsigned long command);
+void aml_system_off(void);
+
+void bl31_get_chipid(unsigned int *, unsigned int *,
+ unsigned int *, unsigned int *);
+void set_viu_probe_enable(void);
+void wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value);
+void power_set_dsp(unsigned int id, unsigned int powerflag);
+void init_dsp(unsigned int id,unsigned int addr,unsigned int cfg0);
+void set_boot_first_timeout(uint64_t arg0);
+int bl31_get_cornerinfo(uint8_t *outbuf, int size);
+int32_t set_boot_params(const keymaster_boot_params*);
+int32_t get_avbkey_from_fip(uint8_t *buf, uint32_t buflen);
+#endif
diff --git a/arch/arm/include/asm/arch-sc2/board_id.h b/arch/arm/include/asm/arch-sc2/board_id.h
new file mode 100644
index 0000000..6488771
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/board_id.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+unsigned int get_board_id(void);
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-sc2/clk_measure_tab.h b/arch/arm/include/asm/arch-sc2/clk_measure_tab.h
new file mode 100644
index 0000000..7bf2819
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/clk_measure_tab.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _ARCH_MESON_SC2_MEASURE_H_
+#define _ARCH_MESON_SC2_MEASURE_H_
+
+static const char* clk_msr_table[] = {
+ [0] = "cts_sys_clk",
+ [1] = "cts_axi_clk",
+ [2] = "cts_rtc_clk",
+ [3] = "cts_dspa_clk",
+ [5] = "cts_mali_clk",
+ [6] = "sys_cpu_clk_div16",
+ [7] = "cts_ceca_clk",
+ [8] = "cts_cecb_clk",
+ [10] = "fclk_div5",
+ [11] = "mp0_clk_out",
+ [12] = "mp1_clk_out",
+ [13] = "mp2_clk_out",
+ [14] = "mp3_clk_out",
+ [15] = "mpll_clk_50m",
+ [16] = "pcie_clk_inp",
+ [17] = "pcie_clk_inn",
+ [18] = "mpll_clk_test_out",
+ [19] = "hifi_pll_clk",
+ [20] = "gp0_pll_clk",
+ [21] = "gp1_pll_clk",
+ [22] = "eth_mppll_50m_ckout",
+ [23] = "sys_pll_div16",
+ [24] = "ddr_dpll_pt_clk",
+ [25] = "earcrx_pll_ckout",
+ [30] = "mod_eth_phy_ref_clk",
+ [31] = "mod_eth_tx_clk",
+ [32] = "cts_eth_clk125Mhz",
+ [33] = "cts_eth_clk_rmii",
+ [34] = "co_clkin_to_mac",
+ [35] = "mod_eth_rx_clk_rmii",
+ [36] = "co_rx_clk",
+ [37] = "co_tx_clk",
+ [38] = "eth_phy_rxclk",
+ [39] = "eth_phy_plltxclk",
+ [40] = "ephy_test_clk",
+ [50] = "vid_pll_div_clk_out",
+ [51] = "cts_enci_clk",
+ [52] = "cts_encp_clk",
+ [53] = "cts_encl_clk",
+ [54] = "cts_vdac_clk",
+ [55] = "cts_cdac_clk_c",
+ [56] = "mod_tcon_clko",
+ [57] = "lcd_an_clk_ph2",
+ [58] = "lcd_an_clk_ph3",
+ [59] = "cts_hdmi_tx_pixel_clk",
+ [60] = "cts_vdin_meas_clk",
+ [61] = "cts_vpu_clk",
+ [62] = "cts_vpu_clkb",
+ [63] = "cts_vpu_clkb_tmp",
+ [64] = "cts_vpu_clkc",
+ [65] = "cts_vid_lock_clk",
+ [66] = "cts_vapbclk",
+ [67] = "cts_ge2d_clk",
+ [68] = "cts_hdcp22_esmclk",
+ [69] = "cts_hdcp22_skpclk",
+ [76] = "hdmitx_tmds_clk",
+ [77] = "cts_hdmitx_sys_clk",
+ [78] = "cts_hdmitx_fe_clk",
+ [79] = "cts_rama_clk",
+ [93] = "cts_vdec_clk",
+ [94] = "cts_wave420_aclk",
+ [95] = "cts_wave420_cclk",
+ [96] = "cts_wave420_bclk",
+ [97] = "cts_hcodec_clk",
+ [98] = "cts_hevcb_clk",
+ [99] = "cts_hevcf_clk",
+ [110] = "cts_sc_clk(smartcard)",
+ [111] = "cts_sar_adc_clk",
+ [113] = "cts_sd_emmc_C_clk(nand)",
+ [114] = "cts_sd_emmc_B_clk",
+ [115] = "cts_sd_emmc_A_clk",
+ [116] = "gpio_msr_clk",
+ [117] = "cts_spicc_1_clk",
+ [118] = "cts_spicc_0_clk",
+ [121] = "cts_ts_clk(temp sensor)",
+ [130] = "audio_vad_clk",
+ [131] = "acodec_dac_clk_x128",
+ [132] = "audio_locker_out_clk",
+ [133] = "audio_locker_in_clk",
+ [134] = "audio_tdmout_c_sclk",
+ [135] = "audio_tdmout_b_sclk",
+ [136] = "audio_tdmout_a_sclk",
+ [137] = "audio_tdmin_lb_sclk",
+ [138] = "audio_tdmin_c_sclk",
+ [139] = "audio_tdmin_b_sclk",
+ [140] = "audio_tdmin_a_sclk",
+ [141] = "audio_resamplea_clk",
+ [142] = "audio_pdm_sysclk",
+ [143] = "audio_spdifoutb_mst_clk",
+ [144] = "audio_spdifout_mst_clk",
+ [145] = "audio_spdifin_mst_clk",
+ [146] = "audio_pdm_dclk",
+ [147] = "audio_resampleb_clk",
+ [148] = "earcrx_pll_dmac_ck",
+ [160] = "pwm_j_clk",
+ [161] = "pwm_i_clk",
+ [162] = "pwm_h_clk",
+ [163] = "pwm_g_clk",
+ [164] = "pwm_f_clk",
+ [165] = "pwm_e_clk",
+ [166] = "pwm_d_clk",
+ [167] = "pwm_c_clk",
+ [168] = "pwm_b_clk",
+ [169] = "pwm_a_clk",
+ [176] = "rng_ring_0",
+ [177] = "rng_ring_1",
+ [178] = "rng_ring_2",
+ [179] = "rng_ring_3",
+ [180] = "dmc_osc_ring(LVT16)",
+ [181] = "gpu_osc_ring0(LVT16)",
+ [182] = "gpu_osc_ring1(ULVT16)",
+ [183] = "gpu_osc_ring2(SVT16)",
+ [184] = "vpu_osc_ring0(SVT24)",
+ [185] = "vpu_osc_ring1(LVT20)",
+ [186] = "vpu_osc_ring2(LVT16)",
+ [187] = "dos_osc_ring0(SVT24)",
+ [188] = "dos_osc_ring1(SVT16)",
+ [189] = "dos_osc_ring2(LVT16)",
+ [190] = "dos_osc_ring3(ULVT20)",
+ [191] = "ddr_osc_ring(LVT16)",
+ [192] = "sys_cpu_osc_ring0(ULVT16)",
+ [193] = "sys_cpu_osc_ring1(ULVT20)",
+ [194] = "sys_cpu_osc_ring2(ULVT16)",
+ [195] = "sys_cpu_osc_ring3(LVT16)",
+ [196] = "axi_sram_osc_ring(SVT16)",
+ [197] = "dspa_osc_ring(SVT16)",
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-sc2/clock.h b/arch/arm/include/asm/arch-sc2/clock.h
new file mode 100644
index 0000000..9c1e0d2
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/clock.h
@@ -0,0 +1,207 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __SC2_H
+#define __SC2_H
+
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe000000
+// -----------------------------------------------
+#define SC2_CLKCTRL_OSCIN_CTRL (0x0001 << 2)
+#define SC2_CLKCTRL_RTC_BY_OSCIN_CTRL0 (0x0002 << 2)
+#define SC2_CLKCTRL_RTC_BY_OSCIN_CTRL1 (0x0003 << 2)
+#define SC2_CLKCTRL_RTC_CTRL (0x0004 << 2)
+#define SC2_CLKCTRL_CHECK_CLK_RESULT (0x0005 << 2)
+#define SC2_CLKCTRL_MBIST_ATSPEED_CTRL (0x0006 << 2)
+#define SC2_CLKCTRL_LOCK_BIT_REG0 (0x0008 << 2)
+#define SC2_CLKCTRL_LOCK_BIT_REG1 (0x0009 << 2)
+#define SC2_CLKCTRL_LOCK_BIT_REG2 (0x000a << 2)
+#define SC2_CLKCTRL_LOCK_BIT_REG3 (0x000b << 2)
+#define SC2_CLKCTRL_PROT_BIT_REG0 (0x000c << 2)
+#define SC2_CLKCTRL_PROT_BIT_REG1 (0x000d << 2)
+#define SC2_CLKCTRL_PROT_BIT_REG2 (0x000e << 2)
+#define SC2_CLKCTRL_PROT_BIT_REG3 (0x000f << 2)
+#define SC2_CLKCTRL_SYS_CLK_CTRL0 (0x0010 << 2)
+#define SC2_CLKCTRL_SYS_CLK_EN0_REG0 (0x0011 << 2)
+#define SC2_CLKCTRL_SYS_CLK_EN0_REG1 (0x0012 << 2)
+#define SC2_CLKCTRL_SYS_CLK_EN0_REG2 (0x0013 << 2)
+#define SC2_CLKCTRL_SYS_CLK_EN0_REG3 (0x0014 << 2)
+#define SC2_CLKCTRL_SYS_CLK_EN1_REG0 (0x0015 << 2)
+#define SC2_CLKCTRL_SYS_CLK_EN1_REG1 (0x0016 << 2)
+#define SC2_CLKCTRL_SYS_CLK_EN1_REG2 (0x0017 << 2)
+#define SC2_CLKCTRL_SYS_CLK_EN1_REG3 (0x0018 << 2)
+#define SC2_CLKCTRL_SYS_CLK_VPU_EN0 (0x0019 << 2)
+#define SC2_CLKCTRL_SYS_CLK_VPU_EN1 (0x001a << 2)
+#define SC2_CLKCTRL_AXI_CLK_CTRL0 (0x001b << 2)
+#define SC2_CLKCTRL_TST_CTRL0 (0x0020 << 2)
+#define SC2_CLKCTRL_TST_CTRL1 (0x0021 << 2)
+#define SC2_CLKCTRL_CECA_CTRL0 (0x0022 << 2)
+#define SC2_CLKCTRL_CECA_CTRL1 (0x0023 << 2)
+#define SC2_CLKCTRL_CECB_CTRL0 (0x0024 << 2)
+#define SC2_CLKCTRL_CECB_CTRL1 (0x0025 << 2)
+#define SC2_CLKCTRL_SC_CLK_CTRL (0x0026 << 2)
+#define SC2_CLKCTRL_DSPA_CLK_CTRL0 (0x0027 << 2)
+#define SC2_CLKCTRL_DSPB_CLK_CTRL0 (0x0028 << 2)
+#define SC2_CLKCTRL_RAMA_CLK_CTRL0 (0x0029 << 2)
+#define SC2_CLKCTRL_CLK12_24_CTRL (0x002a << 2)
+#define SC2_CLKCTRL_VID_CLK_CTRL (0x0030 << 2)
+#define SC2_CLKCTRL_VID_CLK_CTRL2 (0x0031 << 2)
+#define SC2_CLKCTRL_VID_CLK_DIV (0x0032 << 2)
+#define SC2_CLKCTRL_VIID_CLK_DIV (0x0033 << 2)
+#define SC2_CLKCTRL_VIID_CLK_CTRL (0x0034 << 2)
+#define SC2_CLKCTRL_HDMI_CLK_CTRL (0x0038 << 2)
+#define SC2_CLKCTRL_VID_PLL_CLK_DIV (0x0039 << 2)
+#define SC2_CLKCTRL_VPU_CLK_CTRL (0x003a << 2)
+#define SC2_CLKCTRL_VPU_CLKB_CTRL (0x003b << 2)
+#define SC2_CLKCTRL_VPU_CLKC_CTRL (0x003c << 2)
+#define SC2_CLKCTRL_VID_LOCK_CLK_CTRL (0x003d << 2)
+#define SC2_CLKCTRL_VDIN_MEAS_CLK_CTRL (0x003e << 2)
+#define SC2_CLKCTRL_VAPBCLK_CTRL (0x003f << 2)
+#define SC2_CLKCTRL_HDCP22_CLK_CTRL (0x0040 << 2)
+#define SC2_CLKCTRL_MIPIDSI_PHY_CLK_CTRL (0x0041 << 2)
+#define SC2_CLKCTRL_CDAC_CLK_CTRL (0x0042 << 2)
+#define SC2_CLKCTRL_MIPI_CSI_PHY_CLK_CTRL (0x0043 << 2)
+#define SC2_CLKCTRL_CSI2_ADAPT_CLK_CTRL (0x0044 << 2)
+#define SC2_CLKCTRL_VDEC_CLK_CTRL (0x0050 << 2)
+#define SC2_CLKCTRL_VDEC2_CLK_CTRL (0x0051 << 2)
+#define SC2_CLKCTRL_VDEC3_CLK_CTRL (0x0052 << 2)
+#define SC2_CLKCTRL_VDEC4_CLK_CTRL (0x0053 << 2)
+#define SC2_CLKCTRL_WAVE420L_CLK_CTRL (0x0054 << 2)
+#define SC2_CLKCTRL_WAVE420L_CLK_CTRL2 (0x0055 << 2)
+#define SC2_CLKCTRL_TS_CLK_CTRL (0x0056 << 2)
+#define SC2_CLKCTRL_MALI_CLK_CTRL (0x0057 << 2)
+#define SC2_CLKCTRL_VIPNANOQ_CLK_CTRL (0x0058 << 2)
+#define SC2_CLKCTRL_ETH_CLK_CTRL (0x0059 << 2)
+#define SC2_CLKCTRL_NAND_CLK_CTRL (0x005a << 2)
+#define SC2_CLKCTRL_SD_EMMC_CLK_CTRL (0x005b << 2)
+#define SC2_CLKCTRL_BT656_CLK_CTRL (0x005c << 2)
+#define SC2_CLKCTRL_SPICC_CLK_CTRL (0x005d << 2)
+#define SC2_CLKCTRL_GEN_CLK_CTRL (0x005e << 2)
+#define SC2_CLKCTRL_SAR_CLK_CTRL0 (0x005f << 2)
+#define SC2_CLKCTRL_PWM_CLK_AB_CTRL (0x0060 << 2)
+#define SC2_CLKCTRL_PWM_CLK_CD_CTRL (0x0061 << 2)
+#define SC2_CLKCTRL_PWM_CLK_EF_CTRL (0x0062 << 2)
+#define SC2_CLKCTRL_PWM_CLK_GH_CTRL (0x0063 << 2)
+#define SC2_CLKCTRL_PWM_CLK_IJ_CTRL (0x0064 << 2)
+#define SC2_CLKCTRL_TIMESTAMP_CTRL (0x0100 << 2)
+#define SC2_CLKCTRL_TIMESTAMP_CTRL1 (0x0101 << 2)
+#define SC2_CLKCTRL_TIMESTAMP_CTRL2 (0x0103 << 2)
+#define SC2_CLKCTRL_TIMESTAMP_RD0 (0x0104 << 2)
+#define SC2_CLKCTRL_TIMESTAMP_RD1 (0x0105 << 2)
+#define SC2_CLKCTRL_TIMEBASE_CTRL0 (0x0106 << 2)
+#define SC2_CLKCTRL_TIMEBASE_CTRL1 (0x0107 << 2)
+#define SC2_CLKCTRL_EFUSE_CPU_CFG01 (0x0120 << 2)
+#define SC2_CLKCTRL_EFUSE_CPU_CFG2 (0x0121 << 2)
+#define SC2_CLKCTRL_EFUSE_ENCP_CFG0 (0x0122 << 2)
+#define SC2_CLKCTRL_EFUSE_MALI_CFG01 (0x0123 << 2)
+#define SC2_CLKCTRL_EFUSE_HEVCB_CFG01 (0x0124 << 2)
+#define SC2_CLKCTRL_EFUSE_HEVCB_CFG2 (0x0125 << 2)
+#define SC2_CLKCTRL_EFUSE_LOCK (0x0126 << 2)
+//========================================================================
+
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe008000
+// -----------------------------------------------
+#define SC2_ANACTRL_SYSPLL_CTRL0 ((0x00 << 2) + 0x8000)
+#define SC2_ANACTRL_SYSPLL_CTRL1 ((0x01 << 2) + 0x8000)
+#define SC2_ANACTRL_SYSPLL_CTRL2 ((0x02 << 2) + 0x8000)
+#define SC2_ANACTRL_SYSPLL_CTRL3 ((0x03 << 2) + 0x8000)
+#define SC2_ANACTRL_SYSPLL_CTRL4 ((0x04 << 2) + 0x8000)
+#define SC2_ANACTRL_SYSPLL_CTRL5 ((0x05 << 2) + 0x8000)
+#define SC2_ANACTRL_SYSPLL_CTRL6 ((0x06 << 2) + 0x8000)
+#define SC2_ANACTRL_SYSPLL_STS ((0x07 << 2) + 0x8000)
+#define SC2_ANACTRL_FIXPLL_CTRL0 ((0x10 << 2) + 0x8000)
+#define SC2_ANACTRL_FIXPLL_CTRL1 ((0x11 << 2) + 0x8000)
+#define SC2_ANACTRL_FIXPLL_CTRL2 ((0x12 << 2) + 0x8000)
+#define SC2_ANACTRL_FIXPLL_CTRL3 ((0x13 << 2) + 0x8000)
+#define SC2_ANACTRL_FIXPLL_CTRL4 ((0x14 << 2) + 0x8000)
+#define SC2_ANACTRL_FIXPLL_CTRL5 ((0x15 << 2) + 0x8000)
+#define SC2_ANACTRL_FIXPLL_CTRL6 ((0x16 << 2) + 0x8000)
+#define SC2_ANACTRL_FIXPLL_STS ((0x17 << 2) + 0x8000)
+#define SC2_ANACTRL_GP0PLL_CTRL0 ((0x20 << 2) + 0x8000)
+#define SC2_ANACTRL_GP0PLL_CTRL1 ((0x21 << 2) + 0x8000)
+#define SC2_ANACTRL_GP0PLL_CTRL2 ((0x22 << 2) + 0x8000)
+#define SC2_ANACTRL_GP0PLL_CTRL3 ((0x23 << 2) + 0x8000)
+#define SC2_ANACTRL_GP0PLL_CTRL4 ((0x24 << 2) + 0x8000)
+#define SC2_ANACTRL_GP0PLL_CTRL5 ((0x25 << 2) + 0x8000)
+#define SC2_ANACTRL_GP0PLL_CTRL6 ((0x26 << 2) + 0x8000)
+#define SC2_ANACTRL_GP0PLL_STS ((0x27 << 2) + 0x8000)
+#define SC2_ANACTRL_GP1PLL_CTRL0 ((0x30 << 2) + 0x8000)
+#define SC2_ANACTRL_GP1PLL_CTRL1 ((0x31 << 2) + 0x8000)
+#define SC2_ANACTRL_GP1PLL_CTRL2 ((0x32 << 2) + 0x8000)
+#define SC2_ANACTRL_GP1PLL_CTRL3 ((0x33 << 2) + 0x8000)
+#define SC2_ANACTRL_GP1PLL_CTRL4 ((0x34 << 2) + 0x8000)
+#define SC2_ANACTRL_GP1PLL_CTRL5 ((0x35 << 2) + 0x8000)
+#define SC2_ANACTRL_GP1PLL_CTRL6 ((0x36 << 2) + 0x8000)
+#define SC2_ANACTRL_GP1PLL_STS ((0x37 << 2) + 0x8000)
+#define SC2_ANACTRL_HIFIPLL_CTRL0 ((0x40 << 2) + 0x8000)
+#define SC2_ANACTRL_HIFIPLL_CTRL1 ((0x41 << 2) + 0x8000)
+#define SC2_ANACTRL_HIFIPLL_CTRL2 ((0x42 << 2) + 0x8000)
+#define SC2_ANACTRL_HIFIPLL_CTRL3 ((0x43 << 2) + 0x8000)
+#define SC2_ANACTRL_HIFIPLL_CTRL4 ((0x44 << 2) + 0x8000)
+#define SC2_ANACTRL_HIFIPLL_CTRL5 ((0x45 << 2) + 0x8000)
+#define SC2_ANACTRL_HIFIPLL_CTRL6 ((0x46 << 2) + 0x8000)
+#define SC2_ANACTRL_HIFIPLL_STS ((0x47 << 2) + 0x8000)
+#define SC2_ANACTRL_PCIEPLL_CTRL0 ((0x50 << 2) + 0x8000)
+#define SC2_ANACTRL_PCIEPLL_CTRL1 ((0x51 << 2) + 0x8000)
+#define SC2_ANACTRL_PCIEPLL_CTRL2 ((0x52 << 2) + 0x8000)
+#define SC2_ANACTRL_PCIEPLL_CTRL3 ((0x53 << 2) + 0x8000)
+#define SC2_ANACTRL_PCIEPLL_CTRL4 ((0x54 << 2) + 0x8000)
+#define SC2_ANACTRL_PCIEPLL_CTRL5 ((0x55 << 2) + 0x8000)
+#define SC2_ANACTRL_PCIEPLL_STS ((0x56 << 2) + 0x8000)
+#define SC2_ANACTRL_MPLL_CTRL0 ((0x60 << 2) + 0x8000)
+#define SC2_ANACTRL_MPLL_CTRL1 ((0x61 << 2) + 0x8000)
+#define SC2_ANACTRL_MPLL_CTRL2 ((0x62 << 2) + 0x8000)
+#define SC2_ANACTRL_MPLL_CTRL3 ((0x63 << 2) + 0x8000)
+#define SC2_ANACTRL_MPLL_CTRL4 ((0x64 << 2) + 0x8000)
+#define SC2_ANACTRL_MPLL_CTRL5 ((0x65 << 2) + 0x8000)
+#define SC2_ANACTRL_MPLL_CTRL6 ((0x66 << 2) + 0x8000)
+#define SC2_ANACTRL_MPLL_CTRL7 ((0x67 << 2) + 0x8000)
+#define SC2_ANACTRL_MPLL_CTRL8 ((0x68 << 2) + 0x8000)
+#define SC2_ANACTRL_MPLL_STS ((0x69 << 2) + 0x8000)
+#define SC2_ANACTRL_HDMIPLL_CTRL0 ((0x70 << 2) + 0x8000)
+#define SC2_ANACTRL_HDMIPLL_CTRL1 ((0x71 << 2) + 0x8000)
+#define SC2_ANACTRL_HDMIPLL_CTRL2 ((0x72 << 2) + 0x8000)
+#define SC2_ANACTRL_HDMIPLL_CTRL3 ((0x73 << 2) + 0x8000)
+#define SC2_ANACTRL_HDMIPLL_CTRL4 ((0x74 << 2) + 0x8000)
+#define SC2_ANACTRL_HDMIPLL_CTRL5 ((0x75 << 2) + 0x8000)
+#define SC2_ANACTRL_HDMIPLL_CTRL6 ((0x76 << 2) + 0x8000)
+#define SC2_ANACTRL_HDMIPLL_STS ((0x77 << 2) + 0x8000)
+#define SC2_ANACTRL_HDMIPLL_VLOCK ((0x79 << 2) + 0x8000)
+#define SC2_ANACTRL_HDMIPHY_CTRL0 ((0x80 << 2) + 0x8000)
+#define SC2_ANACTRL_HDMIPHY_CTRL1 ((0x81 << 2) + 0x8000)
+#define SC2_ANACTRL_HDMIPHY_CTRL2 ((0x82 << 2) + 0x8000)
+#define SC2_ANACTRL_HDMIPHY_CTRL3 ((0x83 << 2) + 0x8000)
+#define SC2_ANACTRL_HDMIPHY_CTRL4 ((0x84 << 2) + 0x8000)
+#define SC2_ANACTRL_HDMIPHY_CTRL5 ((0x85 << 2) + 0x8000)
+#define SC2_ANACTRL_HDMIPHY_STS ((0x86 << 2) + 0x8000)
+#define SC2_ANACTRL_MIPICSI_CTRL0 ((0x90 << 2) + 0x8000)
+#define SC2_ANACTRL_MIPICSI_CTRL1 ((0x91 << 2) + 0x8000)
+#define SC2_ANACTRL_MIPICSI_CTRL2 ((0x92 << 2) + 0x8000)
+#define SC2_ANACTRL_MIPICSI_CTRL3 ((0x93 << 2) + 0x8000)
+#define SC2_ANACTRL_MIPICSI_CTRL4 ((0x94 << 2) + 0x8000)
+#define SC2_ANACTRL_MIPICSI_CTRL5 ((0x95 << 2) + 0x8000)
+#define SC2_ANACTRL_MIPIDSI_CTRL0 ((0xa0 << 2) + 0x8000)
+#define SC2_ANACTRL_MIPIDSI_CTRL1 ((0xa1 << 2) + 0x8000)
+#define SC2_ANACTRL_MIPIDSI_CTRL2 ((0xa2 << 2) + 0x8000)
+#define SC2_ANACTRL_MIPIDSI_STS ((0xa3 << 2) + 0x8000)
+#define SC2_ANACTRL_VDAC_CTRL0 ((0xb0 << 2) + 0x8000)
+#define SC2_ANACTRL_VDAC_CTRL1 ((0xb1 << 2) + 0x8000)
+#define SC2_ANACTRL_POR_CTRL ((0xb6 << 2) + 0x8000)
+#define SC2_ANACTRL_LOCK_BIT ((0xb8 << 2) + 0x8000)
+#define SC2_ANACTRL_PROT_BIT ((0xb9 << 2) + 0x8000)
+//========================================================================
+
+/*
+ * CPU clok register offset
+ * APB_BASE: APB1_BASE_ADDR = 0xfe007400
+ */
+
+#include <dt-bindings/clock/sc2-clkc.h>
+#define NR_CLKS (CLKID_END_BASE)
+
+#endif /* __SC2_H */
diff --git a/arch/arm/include/asm/arch-sc2/core.h b/arch/arm/include/asm/arch-sc2/core.h
new file mode 100644
index 0000000..97fd220
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/core.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __CORE_H__
+#define __CORE_H__
+
+int get_core_mpidr(unsigned int cpuid);
+int get_core_idx(unsigned int mpidr);
+int get_core_max(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-sc2/cpu.h b/arch/arm/include/asm/arch-sc2/cpu.h
new file mode 100644
index 0000000..5ab0e45
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/cpu.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+/* #include <config.h> */
+/* #include <asm/plat-cpu.h> */
+/* #include <asm/arch/ddr.h> */
+
+#if 0
+#define CONFIG_AML_MESON 1
+#define CONFIG_AML_MESON_GX 1
+#define CONFIG_AML_MESON_G12A 1
+#endif
+
+/*enable viu probe*/
+#if 0
+#define CONFIG_CMD_VIU_PROBE 1
+#endif
+
+/* for uboot envrionment use */
+#define CONFIG_DDR_SIZE 2048
+
+/* dram */
+#define PHYS_SDRAM_1_BASE 0x00000000UL
+#define PHYS_SDRAM_1_SIZE 0x80000000UL
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1_BASE
+
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1_BASE + CONFIG_SYS_TEXT_BASE)
+
+/* define size */
+#define CONFIG_1G_SIZE (1<<30) /* 1G */
+#define CONFIG_2G_SIZE (2<<30) /* 2G */
+#define CONFIG_3G_SIZE (3<<30) /* 3G */
+#define CONFIG_DDR_MAX_SIZE (0XF1<<24) /* sc2 ddr max use interval [0~0xf1000000) */
+
+/* console/print buffer */
+#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
+
+/* use "hush" command parser */
+#if 0
+#define CONFIG_SYS_HUSH_PARSER
+#endif
+
+#if 0
+#define CONFIG_DTB_MEM_ADDR 0x1000000
+#endif
+
+#if 0
+#define CONFIG_AML_CUSTOMER_ID (0)
+#endif
+
+#define AML_CUSTOMER_ID (0)
+
+//#define CONFIG_SILENT_CONSOLE
+//#define CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC
+//#define CONFIG_SILENT_U_BOOT_ONLY
+
+/* 2018.03.19 new compress solution, only support BL33 LZ4 compress */
+#define CONFIG_AML_BL33_COMPRESS_ENABLE 1
+
+/* 2018.03.19 G12A only support v3 format for normal & secure boot */
+#define CONFIG_AML_SECURE_BOOT_V3 1
+
+#define NR_CPUS 4
+
+#define CPU_ID_REG SYSCTRL_SEC_STATUS_REG0
+#define PACKAGE_ID_MASK 0xFF
+
+/*C1 SoC secure boot solution default not support AES algorithm*/
+//#define CONFIG_AML_CRYPTO_AES 1
+
+
+/*Flag for enable AES key generate to EFUSE pattern, with this flag only
+AES key will be generated to EFUSE pattern, it can be used for use case
+like the AES key not ready when secure boot enabled for the first time.
+*/
+//#define CONFIG_AML_EFUSE_GEN_AES_ONLY 1
+
+#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-sc2/cpu_config.h b/arch/arm/include/asm/arch-sc2/cpu_config.h
new file mode 100644
index 0000000..edf7983
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/cpu_config.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _BOOT_ROM_CONFIG_H_
+#define _BOOT_ROM_CONFIG_H_
+
+/***********************************************************
+ * The following constants are GXBB definition
+ **********************************************************/
+#define ROMBOOT_START 0xD9040000
+#define ROM_SIZE (64*1024)
+#define ROMBOOT_END (ROMBOOT_START+ROM_SIZE)
+
+/***********************************************************
+ * AHB-SRAM Total Size 80KB, layout shown as below
+ *
+ * ROMCODE use the top 32KB
+ *
+ * [ 128] 0xD901_3F80 - 0xD901_3FFF Reserved
+ * [ 128] 0xD901_3F00 - 0xD901_3F7F CPUs Boot Entry
+ * [ 256] 0xD901_3E00 - 0xD901_3EFF Debug Info
+ * [ 512] 0xD901_3C00 - 0xD901_3DFF eFuse mirror
+ * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3)
+ * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) *
+ * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) *
+ * [ 26K] 0xD900_C800 - 0xD901_2FFF BL1 Stack, BSS
+ * [ 1K] 0xD900_C400 - 0xD900_C7FF NAND, USB Buffer
+ * [ 1K] 0xD900_C000 - 0xD900_C3FF Reserved
+ *
+ **********************************************************/
+#define RAM_START 0xD9000000
+#define RAM_SIZE (80 * 1024)
+#define BL1_RAM_START (RAM_START + 0xC000)
+#define BL1_RAM_SIZE (32 * 1024)
+#define BL1_RAM_END (BL1_RAM_START + BL1_RAM_SIZE)
+#define BSS_START (BL1_RAM_START + (2 * 1024))
+#define BSS_SIZE (18 * 1024)
+#define _STACK_END (BSS_START + BSS_SIZE + 8*1024)
+#define BL1_EFUSE_MIRROR (BL1_RAM_END - 1024)
+#define P_SHARED_EFUSE_MIRROR (volatile uint32_t *)(BL1_EFUSE_MIRROR)
+#define BL1_DEBUG_BUFFER (BL1_RAM_END - 512)
+#define CPU_BOOT_ENTRY (BL1_DEBUG_BUFFER + 256)
+#define P_SHARED_DEBUG_BUFF (volatile uint32_t *)(BL1_DEBUG_BUFFER)
+#define BL1_SEC_MBX (BL1_RAM_END - 2*1024)
+#define BL1_NAND_BUFF (BL1_RAM_START + 1024)
+#define BL1_USB_BUFF (BL1_NAND_BUFF)
+
+#define MEMORY_LOC RAM_START
+
+#define SRAM_DEBUG_BUFF_SIZE 256
+
+/* BL2 SPL size */
+#define BL2_SIZE (254 * 1024)
+
+//for signature test
+//#define CONFIG_AML_SIG_TEST_BUILD
+
+/* Software SHA2 */
+#define CONFIG_SHA2_SW
+
+/* Hardware SHA2 */
+#define CONFIG_SHA2_HW
+#define SHA2_HW_UPDATE_API
+
+/* Keep timer config in conf.h */
+#define CONFIG_TIMER
+
+/* Bootrom debug info */
+#define CONFIG_DEBUG_INFO
+
+/* Mincrypt RSA library */
+//#define CONFIG_MINCRYPT
+
+/* PolarSSL RSA library */
+#define CONFIG_POLARSSL_RSA
+
+#ifdef CONFIG_POLARSSL_RSA
+#ifndef CONFIG_MALLOC
+#define CONFIG_MALLOC
+#endif /* ! CONFIG_MALLOC */
+#endif /* CONFIG_POLARSSL_RSA */
+
+#endif /* _BOOT_ROM_CONFIG_H_ */
diff --git a/arch/arm/include/asm/arch-sc2/cpu_reset.h b/arch/arm/include/asm/arch-sc2/cpu_reset.h
new file mode 100644
index 0000000..46f9abf
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/cpu_reset.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _BOOT_ROM_WATCHDOG_H
+#define _BOOT_ROM_WATCHDOG_H
+#include <asm/arch/secure_apb.h>
+
+void reset_system(void);
+
+/* uboot reset interface */
+void reset_cpu(unsigned long flag);
+
+#endif /* _BOOT_ROM_WATCHDOG_H */
diff --git a/arch/arm/include/asm/arch-sc2/cpu_sdio.h b/arch/arm/include/asm/arch-sc2/cpu_sdio.h
new file mode 100644
index 0000000..46f366a
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/cpu_sdio.h
@@ -0,0 +1,239 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __CPU_SDIO_H__
+#define __CPU_SDIO_H__
+
+#define SD_EMMC_BASE_A 0xFFE03000
+#define SD_EMMC_BASE_B 0xFFE05000
+#define SD_EMMC_BASE_C 0xFFE07000
+
+#define SDIO_PORT_A 0
+#define SDIO_PORT_B 1
+#define SDIO_PORT_C 2
+
+struct sd_emmc_global_regs {
+ volatile uint32_t gclock; // 0x00
+ volatile uint32_t gdelay; // 0x04
+ volatile uint32_t gdelay1; //0x08
+ volatile uint32_t gadjust; // 0x0c
+ volatile uint32_t gcalout; // 0x10
+ volatile uint32_t reserved_14[11]; // 0x14~0x3c
+ volatile uint32_t gstart; // 0x40
+ volatile uint32_t gcfg; // 0x44
+ volatile uint32_t gstatus; // 0x48
+ volatile uint32_t girq_en; // 0x4c
+ volatile uint32_t gcmd_cfg; // 0x50
+ volatile uint32_t gcmd_arg; // 0x54
+ volatile uint32_t gcmd_dat; // 0x58
+ volatile uint32_t gcmd_rsp0; // 0x5c
+ volatile uint32_t gcmd_rsp1; // 0x60
+ volatile uint32_t gcmd_rsp2; // 0x64
+ volatile uint32_t gcmd_rsp3; // 0x68
+ volatile uint32_t reserved_6c; // 0x6c
+ volatile uint32_t gcurr_cfg; // 0x70
+ volatile uint32_t gcurr_arg; // 0x74
+ volatile uint32_t gcurr_dat; // 0x78
+ volatile uint32_t gcurr_rsp; // 0x7c
+ volatile uint32_t gnext_cfg; // 0x80
+ volatile uint32_t gnext_arg; // 0x84
+ volatile uint32_t gnext_dat; // 0x88
+ volatile uint32_t gnext_rsp; // 0x8c
+ volatile uint32_t grxd; // 0x90
+ volatile uint32_t gtxd; // 0x94
+ volatile uint32_t reserved_98[90]; // 0x98~0x1fc
+ volatile uint32_t gdesc[128]; // 0x200
+ volatile uint32_t gping[128]; // 0x400
+ volatile uint32_t gpong[128]; // 0x800
+};
+
+union sd_emmc_setup {
+ uint32_t d32;
+ struct {
+ unsigned bw:3;
+ unsigned fast:1;
+ unsigned par:3;
+ unsigned hcs:1;
+ unsigned sd:1;
+ unsigned sdhc:1;
+ unsigned type:6;
+ unsigned rca:16;
+ } b;
+};
+
+struct sd_emmc_desc_info{
+ uint32_t cmd_info;
+ uint32_t cmd_arg;
+ uint32_t data_addr;
+ uint32_t resp_addr;
+};
+
+struct cmd_cfg{
+ uint32_t length:9;
+ uint32_t block_mode:1;
+ uint32_t r1b:1;
+ uint32_t end_of_chain:1;
+ uint32_t timeout:4;
+ uint32_t no_resp:1;
+ uint32_t no_cmd:1;
+ uint32_t data_io:1;
+ uint32_t data_wr:1;
+ uint32_t resp_nocrc:1;
+ uint32_t resp_128:1;
+ uint32_t resp_num:1;
+ uint32_t data_num:1;
+ uint32_t cmd_index:6;
+ uint32_t error:1;
+ uint32_t owner:1;
+};
+
+struct sd_emmc_status{
+ uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire, for multiple block read, the CRC errors are ORed together.*/
+ uint32_t txd_err:1; /*[8] TX data CRC error, for multiple block write, any one of blocks CRC error. */
+ uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. The owner bit is ¡°0¡±, set cfg_ignore_owner to ignore this error.*/
+ uint32_t resp_err:1; /*[10] Response CRC error.*/
+ uint32_t resp_timeout:1; /*[11] No response received before time limit. The timeout limit is set by cfg_resp_timeout.*/
+ uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. The timeout limit is set by descriptor itself.*/
+ /* Consider the multiple block read/write, set the proper timeout limits.*/
+ uint32_t end_of_chain:1; /*[13] End of Chain IRQ, Normal IRQ. */
+ uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ, Normal IRQ, the descriptor chain execution keeps going on.*/
+ uint32_t irq_sdio:1; /*[15] SDIO device uses DAT[1] to request IRQ. */
+ uint32_t dat_i:8; /*[23:16] Input data signals. */
+ uint32_t cmd_i:1; /*[24] nput response signal. */
+ uint32_t ds:1; /*[25] Input data strobe. */
+ uint32_t bus_fsm:4; /*[29:26] BUS fsm */
+ uint32_t desc_wr_rdy:1; /*[30] Descriptor write back process is done and it is ready for CPU to read.*/
+ uint32_t core_rdy:1; /*[31] desc_busy or sd_emmc_irq or bus_fsm is not idle.*/
+};//__attribute__((__may_alias__));
+
+
+struct sd_emmc_clock{
+ uint32_t div:6; /*[5:0] Clock divider. Frequency = clock source/cfg_div, Maximum divider 63. */
+ /*Clock off: cfg_div==0, the clock is disabled */
+ /*Divider bypass: cfg_div==1, clock source is used as core clock without divider. */
+ uint32_t src:2; /*[7:6] Clock source, 0: Crystal 24MHz, 1: Fix PLL, 850MHz*/
+ /* 2: MPLL, <637MHz, used for 400MHz exactly. 3: different PLL */
+ uint32_t core_phase:2; /*[9:8] Core clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/
+ uint32_t tx_phase:2; /*[11:10] TX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/
+ uint32_t rx_phase:2; /*[13:12] RX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/
+ uint32_t reserved14:2;
+ uint32_t tx_delay:6; /*[21:16] TX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/
+ uint32_t rx_delay:6; /*[27:22] RX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/
+ uint32_t always_on:1; /*[28] 1: Keep clock always on. 0: Clock on/off controlled by activities. */
+ /*Any APB3 access or descriptor execution will keep clock on.*/
+ uint32_t irq_sdio_sleep:1; /*[29] 1: enable IRQ sdio when in sleep mode. */
+ uint32_t irq_sdio_sleep_ds:1;/*[30] 1:enable ds as irq*/
+ uint32_t reserved26:1;
+};
+
+struct sd_emmc_delay{
+ uint32_t dat0:6; /*[3:0] Data 0 delay line. */
+ uint32_t dat1:6; /*[7:4] Data 1 delay line. */
+ uint32_t dat2:6; /*[11:8] Data 2 delay line. */
+ uint32_t dat3:6; /*[15:12] Data 3 delay line. */
+ uint32_t dat4:6; /*[19:16] Data 4 delay line. */
+ uint32_t spare:2;
+};
+
+struct sd_emmc_delay1{
+ uint32_t dat5:6; /*[23:20] Data 5 delay line. */
+ uint32_t dat6:6; /*[27:24] Data 6 delay line. */
+ uint32_t dat7:6; /*[31:28] Data 7 delay line. */
+ uint32_t dat8:6; /*[31:28] Data 7 delay line. */
+ uint32_t dat9:6; /*[31:28] Data 7 delay line. */
+ uint32_t spare:2;
+};
+
+struct sd_emmc_adjust{
+ uint32_t cmd_delay:4; /*[3:0] Command delay line. */
+ uint32_t ds_delay:4; /*[7:4] DS delay line. */
+ uint32_t cali_sel:4; /*[11:8] Select one signal to be tested.*/
+ /*Signals are labeled from 0 to 9 the same as delay lines. */
+ uint32_t cali_enable:1; /*[12] Enable calibration. */
+ uint32_t adj_enable:1; /*[13] Adjust interface timing by resampling the input signals. */
+ uint32_t cali_rise:1; /*[14] 1: test the rising edge. 0: test the falling edge. */
+ uint32_t ds_enable:1; /*[15] Sampling the DAT based on DS in HS400 mode*/
+ uint32_t adj_delay:6; /*[21:16] Resample the input signals when clock index==adj_delay. */
+ uint32_t adj_auto:1; /*[22] Use cali_dut first falling edge to adjust the timing */
+ /*set cali_enable to 1 to use this function*/
+ uint32_t reserved23:9;
+};
+
+
+struct sd_emmc_calout{
+ uint32_t cali_idx:6; /*[5:0] Calibration reading. The event happens at this index. */
+ uint32_t reserved6:1;
+ uint32_t cali_vld:1; /*[7] The reading is valid. */
+ uint32_t cali_setup:8; /*[15:8] Copied from BASE+0x8 [15:8] include cali_sel, cali_enable, adj_enable, cali_rise. */
+ uint32_t reserved16:16;
+};
+
+
+struct sd_emmc_start{
+ uint32_t init:1; /*[0] 1: Read descriptor from internal SRAM, limited to 32 descriptors. */
+ /* 0: Read descriptor from external DDR */
+ uint32_t busy:1; /*[1] 1: Start command chain execution process. 0: Stop */
+ uint32_t addr:30; /*[31:2] Descriptor address, the last 2 bits are 0, 4 bytes aligned. */
+ /* When internal SRAM is used, the valid address range is from 0x200~0x3ff */
+ /* When external DDR is used, the valid address is anywhere in DDR, the length of chain is unlimited.*/
+};//__attribute__((__may_alias__));
+
+
+struct sd_emmc_config{
+ uint32_t bus_width:2; /*[1:0] 0: 1 bit, 1: 4 bits, 2: 8 bits, 3: 2 bits (not supported)*/
+ uint32_t ddr:1; /*[2] 1: DDR mode, 0: SDR mode */
+ uint32_t dc_ugt:1; /*[3] 1: DDR access urgent, 0: DDR access normal. */
+ uint32_t bl_len:4; /*[7:4] Block length 2^cfg_bl_len, because internal buffer size is limited to 512 bytes, the cfg_bl_len <=9. */
+ uint32_t resp_timeout:4; /*[11:8] Wait response till 2^cfg_resp_timeout core clock cycles. Maximum 32768 core cycles. */
+ uint32_t rc_cc:4; /*[15:12] Wait response-command, command-command gap before next command, 2^cfg_rc_cc core clock cycles. */
+ uint32_t out_fall:1; /*[16] DDR mode only. The command and TXD start from rising edge. Set 1 to start from falling edge. */
+ uint32_t blk_gap_ip:1; /*[17] 1: Enable SDIO data block gap interrupt period. 0: Disabled.*/
+ uint32_t spare:1; /*[18] Spare, ??? need check*/
+ uint32_t ignore_owner:1; /*[19] Use this descriptor even if its owner bit is ¡°0¡±.*/
+ uint32_t chk_ds:1; /*[20] Check data strobe in HS400.*/
+ uint32_t cmd_low:1; /*[21] Hold CMD as output Low, eMMC boot mode.*/
+ uint32_t stop_clk:1; /*[22] 1: stop clock. 0: normal clock.*/
+ /*In normal mode, the clock is automatically on/off during reading mode to back off reading in case of*/
+ /*DDR slow response, stop clock is used in voltage switch.*/
+ uint32_t auto_clk:1; /*[23] 1: when BUS is idle and no descriptor is available, turn off clock, to save power.*/
+ /* 0: core clock is always on.*/
+ uint32_t txd_add_err:1; /*[24] TXD add error test*/
+ /*Test feature, should not be used in normal condition.*/
+ /*It will inverted the first CRC bits of the 3rd block.*/
+ /*Block index starts from 0, 1, 2, ¡*/
+ uint32_t txd_retry:1; /*[25] When TXD CRC error, host sends the block again.*/
+ /*The total number of retries of one descriptor is limited to 15, */
+ /*after 15 retries, the TXD_err is set to high.*/
+ uint32_t revd:8; /*[31:26] reved*/
+};//__attribute__((__may_alias__));
+
+
+struct sd_emmc_irq_en{
+ uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire.*/
+ uint32_t txd_err:1; /*[8] TX data CRC error. */
+ uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. */
+ uint32_t resp_err:1; /*[10] Response CRC error.*/
+ uint32_t resp_timeout:1; /*[11] No response received before time limit. */
+ uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. */
+ uint32_t end_of_chain:1; /*[13] End of Chain IRQ. */
+ uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ. */
+ uint32_t irq_sdio:1; /*[15] Enable sdio interrupt. */
+ uint32_t revd:16; /*[31:16] reved*/
+};
+
+struct sd_emmc_data_info{
+ uint32_t cnt:10; /*[9:0] Rxd words received from BUS. Txd words received from DDR.*/
+ uint32_t blk:9; /*[24:16] Rxd Blocks received from BUS. Txd blocks received from DDR.*/
+ uint32_t revd:30; /*[31:17] Reved. */
+};
+
+
+struct sd_emmc_card_info{
+ uint32_t txd_cnt:10; /*[9:0] Txd BUS cycle counter. */
+ uint32_t txd_blk:9; /*[24:16] Txd BUS block counter.*/
+ uint32_t revd:30; /*[31:17] Reved. */
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-sc2/ddr.h b/arch/arm/include/asm/arch-sc2/ddr.h
new file mode 100644
index 0000000..ad27855
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/ddr.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <io.h>
+#include <stdint.h>
+#include <asm/arch/ddr_define.h>
+
+/* io defines */
+//#define wr_reg(addr, data) (*((volatile uint32_t *)addr))=(uint32_t)(uint64_t)(data)
+//#define rd_reg(addr) (*((volatile uint32_t *)(addr)))
+#define wr_reg(addr, data) writel(data, addr)
+#define rd_reg(addr) readl(addr)
+/*clear [mask] 0 bits in [addr], set these 0 bits with [value] corresponding bits*/
+#define modify_reg(addr, value, mask) wr_reg(addr, ((rd_reg(addr) & (mask)) | (value)))
+#define wait_set(addr, loc) do{}while(0 == (rd_reg(addr) & (1<<loc)));
+#define wait_clr(addr, loc) do{}while(1 == (rd_reg(addr) & (1<<loc)));
+#define wait_equal(addr, data) do{}while(data != (rd_reg(addr)));
+
+/* function defines */
+unsigned int ddr_init(void);
+unsigned int ddr_init_pll(void);
+unsigned int ddr_init_dmc(void);
+unsigned int ddr_init_pctl(void);
+unsigned int hot_boot(void);
+void ddr_print_info(void);
+void ddr_test(void);
+void ddr_pre_init(void);
+void ddr_debug(void);
+
+/* pctl status */
+#define UPCTL_STAT_MASK (7)
+#define UPCTL_STAT_INIT (0)
+#define UPCTL_STAT_CONFIG (1)
+#define UPCTL_STAT_ACCESS (3)
+#define UPCTL_STAT_LOW_POWER (5)
+
+/* pctl cmds */
+#define UPCTL_CMD_INIT (0)
+#define UPCTL_CMD_CONFIG (1)
+#define UPCTL_CMD_GO (2)
+#define UPCTL_CMD_SLEEP (3)
+#define UPCTL_CMD_WAKEUP (4)
+
+/* PUB PIR setting */
+#define PUB_PIR_INIT (1<<0)
+#define PUB_PIR_ZCAL (1<<1)
+#define PUB_PIR_CA (1<<2)
+#define PUB_PIR_PLLINIT (1<<4)
+#define PUB_PIR_DCAL (1<<5)
+#define PUB_PIR_PHYRST (1<<6)
+#define PUB_PIR_DRAMRST (1<<7)
+#define PUB_PIR_DRAMINIT (1<<8)
+#define PUB_PIR_WL (1<<9)
+#define PUB_PIR_QSGATE (1<<10)
+#define PUB_PIR_WLADJ (1<<11)
+#define PUB_PIR_RDDSKW (1<<12)
+#define PUB_PIR_WRDSKW (1<<13)
+#define PUB_PIR_RDEYE (1<<14)
+#define PUB_PIR_WREYE (1<<15)
+#define PUB_PIR_ICPC (1<<16)
+#define PUB_PIR_PLLBYP (1<<17)
+#define PUB_PIR_CTLDINIT (1<<18)
+#define PUB_PIR_RDIMMINIT (1<<19)
+#define PUB_PIR_CLRSR (1<<27)
+#define PUB_PIR_LOCKBYP (1<<28)
+#define PUB_PIR_DCALBYP (1<<29)
+#define PUB_PIR_ZCALBYP (1<<30)
+#define PUB_PIR_INITBYP (1<<31)
+
+/* PHY initialize register (PIR) */
+#define DDR_PIR ((PUB_PIR_ZCAL) |\
+ (PUB_PIR_PLLINIT) |\
+ (PUB_PIR_DCAL) |\
+ (PUB_PIR_PHYRST) |\
+ (PUB_PIR_DRAMRST) |\
+ (PUB_PIR_DRAMINIT) |\
+ (PUB_PIR_WL) |\
+ (PUB_PIR_QSGATE) |\
+ (PUB_PIR_WLADJ) |\
+ (PUB_PIR_RDDSKW) |\
+ (PUB_PIR_WRDSKW) |\
+ (PUB_PIR_RDEYE) |\
+ (PUB_PIR_WREYE) \
+ )
+
+/* PHY general status register (PGSR0) */
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+#define DDR_PGSR0_CHECK() ((rd_reg(DDR0_PUB_PGSR0) != 0xC0000fff) && \
+ (rd_reg(DDR0_PUB_PGSR0) != 0x80000fff))
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define DDR_PGSR0_CHECK()
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define DDR_PGSR0_CHECK()
+#endif
+
+/* other regs */
+#define SCRATCH0 0xC1107D3C
diff --git a/arch/arm/include/asm/arch-sc2/ddr_define.h b/arch/arm/include/asm/arch-sc2/ddr_define.h
new file mode 100644
index 0000000..2d2697e
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/ddr_define.h
@@ -0,0 +1,305 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#define CONFIG_BOARD_ID_MASK 0xFF
+#define CONFIG_DDR_TYPE_DDR3 0
+#define CONFIG_DDR_TYPE_DDR4 1
+#define CONFIG_DDR_TYPE_LPDDR4 2
+#define CONFIG_DDR_TYPE_LPDDR3 3
+#define CONFIG_DDR_TYPE_LPDDR2 4
+#define CONFIG_DDR_TYPE_AUTO 0xf
+
+/* ddr channel defines */
+#define CONFIG_DDR0_16BIT 1
+#define CONFIG_DDR0_RANK0 2
+#define CONFIG_DDR0_RANK01 3
+#define CONFIG_DDR0_16BIT_2 4
+/* CONFIG_DDR_CHL_AUTO mode support RANK0 and RANK0+1 mode auto detect */
+#define CONFIG_DDR_CHL_AUTO 0xF
+#define CONFIG_DDR0_16BIT_CH0 0x1
+#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7
+#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8
+
+#define CFG_DDR_BASE_ADDR 0X0
+#define CFG_DDR_START_OFFSET 0X00000000 //TXLX SKIP 0MB
+
+/* ddr type identifier */
+#define CONFIG_DDR_TIMMING_LPDDR2 0x02
+#define CONFIG_DDR_TIMMING_LPDDR3 0x03
+#define CONFIG_DDR_TIMMING_DDR3_7 0x07
+#define CONFIG_DDR_TIMMING_DDR3_9 0x09
+#define CONFIG_DDR_TIMMING_DDR3_11 0x0B
+#define CONFIG_DDR_TIMMING_DDR3_12 0x0C
+#define CONFIG_DDR_TIMMING_DDR3_13 0x0D
+#define CONFIG_DDR_TIMMING_DDR3_14 0x0E
+
+#define CONFIG_DDR_TIMMING_DDR4_1600 0x0F
+#define CONFIG_DDR_TIMMING_DDR4_1866 0x10
+#define CONFIG_DDR_TIMMING_DDR4_2133 0x11
+#define CONFIG_DDR_TIMMING_DDR4_2400 0x12
+#define CONFIG_DDR_TIMMING_DDR4_2666 0x13
+#define CONFIG_DDR_TIMMING_DDR4_3200 0x14
+
+#define LPDDR_DIE_ROW_COL_R13_C9 0
+#define LPDDR_DIE_ROW_COL_R14_C9 1
+#define LPDDR_DIE_ROW_COL_R14_C10 2
+#define LPDDR_DIE_ROW_COL_R13_C10 3
+#define LPDDR_DIE_ROW_COL_R14_C11 4
+
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE0 0
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE1 1
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE2 2
+#define CONFIG_LPDDR3_CA_TRAINING_USE_LANE3 3
+
+#define CONFIG_DDR_FUNC_TEST (1<<0)
+
+#define CONFIG_DDR_INIT_RETRY_TOTAL (10)
+#define CONFIG_DDR_PCTL_RETRY_TOTAL (100)
+
+#define DDR_USE_1_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK0) || \
+ (chl_set == CONFIG_DDR0_16BIT))
+#define DDR_USE_2_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK01))
+
+#define DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT 1<<5
+#define DMC_TEST_SLT_ENABLE_DDR_AUTO_WINDOW_TEST 1<<4
+/* DMC_DDR_CTRL defines */
+#define DDR_DDR4_ENABLE (1<<22)
+#define DDR_RANK1_ENABLE (1<<21)
+#define DDR_DDR4_BG_ENABLE (1<<20)
+#define DDR_16BIT_ENABLE (1<<16)
+
+#define DDR_RANK1_SIZE_CTRL (3)
+#define DDR_RANK0_SIZE_CTRL (0)
+
+/* dram cfg magic */
+#define DRAM_CFG_MAGIC 0x2e676663
+
+#define DMC_TEST_SLT_SCAN_FREQUENCY 1
+#define DMC_TEST_SLT_OFFSET_DELAY (1<<1)
+#define DMC_TEST_SLT_ENABLE_DDR_SKIP_TRAINING (1<<6)
+#define DMC_TEST_SLT_ENABLE_DDR_DVFS (1<<7)
+
+/* ddr configs */
+#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+
+#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+#define DDR_RFC_TYPE_LPDDR4_6Gbx1 12
+#define DDR_RFC_TYPE_LPDDR4_8Gbx1 13
+
+#define DDR_ENABLE_FINE_TUNE_FLAG_AC_DELAY (1<<0)
+#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQS (1<<1)
+#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS (1<<2)
+#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ (1<<3)
+#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ (1<<4)
+
+/* lpddr3 defines */
+#ifndef CONFIG_LPDDR_REMAP_SET
+#define CONFIG_LPDDR_REMAP_SET LPDDR_DIE_ROW_COL_R14_C9
+#endif
+
+/* how to add a new ddr function?
+ 1. add CONFIG_DDR_FUNC_XXX in (config).h file
+ 2. add define in this file.
+ 2.1 add
+ #ifndef CONFIG_DDR_FUNC_XXX
+ #define CONFIG_DDR_FUNC_XXX 0
+ #endif
+ 2.2 add
+ #define DDR_FUNC_XXX (CONFIG_FUNC_XXX<<X)
+ 2.3 add DDR_FUNC_XXX |\ in DDR_FUNC
+ 3. add same define and parser in bl2 code
+ */
+/* 2.1, 2,2, 2,3 example */
+/*
+#ifndef CONFIG_CMD_DDR_D2PLL
+#define CONFIG_CMD_DDR_D2PLL 0
+#endif
+#define DDR_FUNC_D2PLL (CONFIG_CMD_DDR_D2PLL<<0)
+#define DDR_FUNC (EXISTING_FUNCTIONS) |\
+ (DDR_FUNC_D2PLL)
+*/
+
+/* d2pll support */
+#ifndef CONFIG_CMD_DDR_D2PLL
+#define CONFIG_CMD_DDR_D2PLL 0
+#endif
+#define DDR_FUNC_D2PLL (CONFIG_CMD_DDR_D2PLL<<0)
+
+/* ddr low power function support */
+#ifndef CONFIG_DDR_LOW_POWER
+#define CONFIG_DDR_LOW_POWER 0
+#endif
+#define DDR_FUNC_LP (CONFIG_DDR_LOW_POWER<<1)
+
+/* ddr zq power down support */
+#ifndef CONFIG_DDR_ZQ_PD
+#define CONFIG_DDR_ZQ_PD 0
+#endif
+#define DDR_FUNC_ZQ_PD (CONFIG_DDR_ZQ_PD<<2)
+
+/* ddr vref function */
+#ifndef CONFIG_DDR_USE_EXT_VREF
+#define CONFIG_DDR_USE_EXT_VREF 0
+#endif
+#define DDR_FUNC_EXT_VREF (CONFIG_DDR_USE_EXT_VREF<<3)
+
+/* ddr4 timing test function */
+#ifndef CONFIG_DDR4_TIMING_TEST
+#define CONFIG_DDR4_TIMING_TEST 0
+#endif
+#define DDR_FUNC_DDR4_TIMING_TEST (CONFIG_DDR4_TIMING_TEST<<4)
+
+/* ddr pll bypass */
+#ifndef CONFIG_DDR_PLL_BYPASS
+#define CONFIG_DDR_PLL_BYPASS 0
+#endif
+#define DDR_FUNC_DDR_PLL_BYPASS (CONFIG_DDR_PLL_BYPASS<<5)
+
+/* ddr rdbi function */
+#ifndef CONFIG_DDR_FUNC_RDBI
+#define CONFIG_DDR_FUNC_RDBI 0
+#endif
+#define DDR_FUNC_RDBI (CONFIG_DDR_FUNC_RDBI<<6)
+
+/* lpddr3 ca trainingi function */
+#ifndef CONFIG_DDR_FUNC_LPDDR3_CA
+#define CONFIG_DDR_FUNC_LPDDR3_CA 0
+#endif
+#define DDR_FUNC_LPDDR3_CA (CONFIG_DDR_FUNC_LPDDR3_CA<<7)
+
+/* print ddr training window */
+#ifndef CONFIG_DDR_FUNC_PRINT_WINDOW
+#define CONFIG_DDR_FUNC_PRINT_WINDOW 0
+#endif
+#define DDR_FUNC_PRINT_WINDOW (CONFIG_DDR_FUNC_PRINT_WINDOW<<8)
+
+
+/* print ddr training window */
+//#ifndef CONFIG_DDR_FULL_TEST
+//#define CONFIG_DDR_FULL_TEST 0
+//#endif
+//#define DDR_FULL_TEST (CONFIG_DDR_FULL_TEST<<10)
+
+/* non-sec region scramble function */
+#ifndef CONFIG_DDR_NONSEC_SCRAMBLE
+#define CONFIG_DDR_NONSEC_SCRAMBLE 0
+#endif
+#define DDR_NONSEC_SCRAMBLE (CONFIG_DDR_NONSEC_SCRAMBLE<<11)
+
+#if(CONFIG_DDR_FUNC_LPDDR3_CA==1)
+#if (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE0)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21)
+#elif (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE1)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (1<<20)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21)
+#elif (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE2)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (1<<21)
+#elif (CONFIG_LPDDR3_CA_TRAINING_CA0==CONFIG_LPDDR3_CA_TRAINING_USE_LANE3)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (1<<20)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (1<<21)
+#endif
+#if (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE0)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (0<<22)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (0<<23)
+#elif (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE1)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (1<<22)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (0<<23)
+#elif (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE2)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (0<<22)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (1<<23)
+#elif (CONFIG_LPDDR3_CA_TRAINING_CA1==CONFIG_LPDDR3_CA_TRAINING_USE_LANE3)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (1<<22)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (1<<23)
+#endif
+#else /* CONFIG_DDR_FUNC_LPDDR3_CA != 1 */
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0 (0<<20)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1 (0<<21)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0 (0<<22)
+#define DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1 (0<<23)
+#endif /* CONFIG_DDR_FUNC_LPDDR3_CA */
+
+#if(CONFIG_DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP==1)
+#define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP (1<<25)
+#else
+#define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP (0<<25)
+#endif
+#define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1<<30)
+#define DDR_FUNC_CONFIG_DFE_FUNCTION (1<<29)
+#define DDR_FUNC_CONFIG_DDR_DVFS_FUNCTION (1<<28)
+#define DDR_FUNC (DDR_FUNC_D2PLL | \
+ DDR_FUNC_LP | \
+ DDR_FUNC_ZQ_PD | \
+ DDR_FUNC_EXT_VREF | \
+ DDR_FUNC_DDR4_TIMING_TEST | \
+ DDR_FUNC_DDR_PLL_BYPASS | \
+ DDR_FUNC_RDBI | \
+ DDR_FUNC_LPDDR3_CA | \
+ DDR_FUNC_PRINT_WINDOW | \
+ DDR_FULL_TEST | \
+ DDR_NONSEC_SCRAMBLE | \
+ DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0| \
+ DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1| \
+ DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0| \
+ DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1| \
+ DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP | \
+ (1 << 31) \
+ )
+
+
+
+
+/* bl2 reg override stages define */
+#define BL2_INIT_STAGE_0 0
+#define BL2_INIT_STAGE_1 1
+#define BL2_INIT_STAGE_2 2
+#define BL2_INIT_STAGE_3 3
+#define BL2_INIT_STAGE_4 4
+#define BL2_INIT_STAGE_5 5
+#define BL2_INIT_STAGE_6 6
+#define BL2_INIT_STAGE_7 7
+#define BL2_INIT_STAGE_8 8
+#define BL2_INIT_STAGE_9 9
+
+
+/* ddr reg override stages define */
+#define DDR_OVERRIDE_STAGE_DDR3_PRE_INIT 0x10
+#define DDR_OVERRIDE_STAGE_DDR3_DMC_INIT 0x11
+
+#define DDR_OVERRIDE_STAGE_DDR4_PRE_INIT 0x20
+#define DDR_OVERRIDE_STAGE_DDR4_DMC_INIT 0x21
+
+#define DDR_OVERRIDE_STAGE_LPDDR3_PRE_INIT 0x30
+#define DDR_OVERRIDE_STAGE_LPDDR3_DMC_INIT 0x31
+
+#define DDR_OVERRIDE_STAGE_LPDDR4_PRE_INIT 0x40
+#define DDR_OVERRIDE_STAGE_LPDDR4_DMC_INIT 0x41
+
+
+#define DWC_AC_PINMUX_TOTAL 28
+#define DWC_DFI_PINMUX_TOTAL 26
+#define DWC_DQ_PINMUX_TOTAL 32
+
+/* diagnose function defines */
+#define CONFIG_DIAGNOSE_DISABLE 0x0
+#define CONFIG_DIAGNOSE_1D 0x1
+#define CONFIG_DIAGNOSE_2D 0x2
+#define CONFIG_DIAGNOSE_1D_2D 0x3
diff --git a/arch/arm/include/asm/arch-sc2/dev_parameter.h b/arch/arm/include/asm/arch-sc2/dev_parameter.h
new file mode 100644
index 0000000..f78928e
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/dev_parameter.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __DEV_PARAMETER_H__
+#define __DEV_PARAMETER_H__
+
+/* gpio/pinmux/pwm */
+typedef struct _register_ops {
+ /* register address*/
+ uint32_t reg;
+ /* value to set*/
+ uint32_t value;
+ /* bitmask of the value setting */
+ uint32_t mask;
+ /* for HW stable consideration */
+ uint16_t udelay;
+ /* setting stage and etc. */
+ uint8_t flag;
+ /* reserved. */
+ uint8_t rsv_0;
+}__attribute__ ((packed)) register_ops_t;
+
+#define MAX_REG_OPS_ENTRIES (32)
+typedef struct pin_pwm_parameter {
+ register_ops_t pin_pwm[MAX_REG_OPS_ENTRIES];
+}__attribute__ ((packed)) pin_pwm_parameter_t;
+
+typedef struct common_storage_parameter {
+ /* version info of the common storage parameter */
+ uint32_t version;
+ /* fip sector counts */
+ uint32_t device_fip_container_size;
+ /* fip copies */
+ uint32_t device_fip_container_copies;
+ /*ddrfip size*/
+ uint32_t ddr_fip_container_size;
+ uint8_t reserved[16];
+}__attribute__ ((packed)) common_storage_parameter_t;
+
+
+typedef struct nand_parameter {
+ /* version info of the common storage parameter */
+ uint32_t version;
+ /* the same as bbt_start_block, tell the bbt size for scanning mechanism */
+ uint32_t bbt_pages;
+ /* for bl2 stage, it can quickly generate the small part of the fromt bbt table. 20 for start block of bbt scanning */
+ uint32_t bbt_start_block;
+ /* 1: bl2 and fip is stored separately in different area 0: bl2 and fip is stored in first 1024 pages. 1 for slc nand flash. */
+ uint32_t discrete_mode;
+ /* set the setup_data the same as rom code reading from page0. see union cmdinfo in nand.h. */
+ union {
+ uint32_t nand_setup_data;
+ uint32_t spi_nand_page_size;
+ } setup_data;
+ union {
+ uint32_t nand_reserved;
+ uint32_t spi_nand_planes_per_lun;
+ } reserved;
+ /* Block counts of the reserved area */
+ uint32_t reserved_area_blk_cnt;
+ /* Page number of each block */
+ uint32_t page_per_block;
+ /* Page list source of the bl2 NAND driver. 0: calculated in source code; 1: get from byte32~63 */
+ uint8_t use_param_page_list;
+ /* List of page addresses, 8-bit per entry */
+ uint8_t page_list[32];
+ uint8_t reserved1[63];
+}__attribute__ ((packed)) nand_parameter_t;
+
+
+typedef struct storage_parameter {
+ /* for all the storage media */
+ common_storage_parameter_t common;
+ /* for NAND and SPINAND */
+ nand_parameter_t nand;
+}__attribute__ ((packed)) storage_parameter_t;
+
+#endif //__AML_TIMING_H_
diff --git a/arch/arm/include/asm/arch-sc2/efuse.h b/arch/arm/include/asm/arch-sc2/efuse.h
new file mode 100644
index 0000000..4a68e88
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/efuse.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __EFUSE_H
+#define __EFUSE_H
+
+#include <config.h>
+#include <common.h>
+
+/* efuse HAL_API arg */
+struct efuse_hal_api_arg {
+ unsigned int cmd; /* R/W */
+ unsigned int offset;
+ unsigned int size;
+ unsigned long buffer_phy;
+ unsigned long retcnt_phy;
+};
+
+
+#define EFUSE_BYTES 512 /* (EFUSE_BITS/8) */
+
+#define EFUSE_HAL_API_READ 0
+#define EFUSE_HAL_API_WRITE 1
+#define EFUSE_HAL_API_WRITE_PATTERN 2
+#define EFUSE_HAL_API_USER_MAX 3
+
+#define EFUSE_USER_MASK (0x1 << 16)
+#define EFUSE_THERMAL_MASK (0x1 << 17)
+#define EFUSE_THERMAL_VERFLAG_MASK (0x1 << 18)
+#define EFUSE_ENCRYPT_MASK (0x1 << 19)
+
+//#define ASSIST_HW_REV 0x1f53
+
+int efuse_read_usr(char *buf, size_t count, loff_t *ppos);
+int efuse_write_usr(char *buf, size_t count, loff_t *ppos);
+uint32_t efuse_get_max(void);
+ssize_t efuse_read(char *buf, size_t count, loff_t *ppos);
+ssize_t efuse_write(const char *buf, size_t count, loff_t *ppos);
+
+int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg);
+int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg);
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-sc2/eth_setup.h b/arch/arm/include/asm/arch-sc2/eth_setup.h
new file mode 100644
index 0000000..6e643f6
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/eth_setup.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/io.h>
+
+/*
+ *board configuration interface.
+ * */
+struct eth_clock_conf{
+ int enable;
+ int clock_50MHZ_phase;
+ //add ... as you need.
+};
+
+struct eth_board_socket{
+char *name ;
+int (*eth_clock_configure)(struct eth_clock_conf);
+int (*eth_pinmux_setup)(void);
+int (*eth_hw_reset)(void);
+
+};
+
+
+
+/*
+ *clock define part
+ */
+
+#define ETH_BASE (0xff3f0000)
+#define ETH_PLL_CNTL CBUS_REG_ADDR(0x2050)
+ /* Ethernet ctrl */
+#define ETH_PLL_CNTL_DIVEN (1<<0)
+#define ETH_PLL_CNTL_MACSPD (1<<1)
+#define ETH_PLL_CNTL_DATEND (1<<2)
+#define ETH_PLL_CNTL_DESEND (1<<3)
+
+
+/*
+ please refer following doc for detail
+ @AppNote-M3-ClockTrees.docx
+
+ select clk: -> CBUS_REG(0x1076)
+
+ 7-sys_pll_div2
+ 6-vid2_pll_clk
+ 5-vid_pll_clk
+ 4-aud_pll_clk
+ 3-ddr_pll_clk
+ 2-misc_pll_clk
+ 1-sys_pll_clk
+ 0-XTAL
+
+ clk_freq:800MHz
+ output_clk:50MHz
+ aways,maybe changed for others?
+*/
+
+#define ETH_CLKSRC_XTAL (0)
+#define ETH_CLKSRC_SYS_PLL_CLK (1)
+#define ETH_CLKSRC_MISC_PLL_CLK (2)
+#define ETH_CLKSRC_DDR_PLL_CLK (3)
+#define ETH_CLKSRC_AUD_PLL_CLK (
+#define ETH_CLKSRC_VID_PLL_CLK (5)
+#define ETH_CLKSRC_VID2_PLL_CLK (6)
+#define ETH_CLKSRC_SYS_PLL_DIV2_CLK (7)
+#define CLK_1M (1000000)
+
+typedef union eth_aml_reg0 {
+ /** raw register data */
+ unsigned int d32;
+ /** register bits */
+ struct {
+ unsigned phy_intf_sel:3;
+ unsigned rx_clk_rmii_invert:1;
+ unsigned rgmii_tx_clk_src:1;
+ unsigned rgmii_tx_clk_phase:2;
+ unsigned rgmii_tx_clk_ratio:3;
+ unsigned phy_ref_clk_enable:1;
+ unsigned clk_rmii_i_invert:1;
+ unsigned clk_en:1;
+ unsigned adj_enable:1;
+ unsigned adj_setup:1;
+ unsigned adj_delay:5;
+ unsigned adj_skew:5;
+ unsigned cali_start:1;
+ unsigned cali_rise:1;
+ unsigned cali_sel:3;
+ unsigned rgmii_rx_reuse:1;
+ unsigned eth_urgent:1;
+ } b;
+} eth_aml_reg0_t;
+
+#define ETH_VALIDE_CLKSRC(clk,out_clk) ((clk%out_clk)==0)
+
+int eth_clk_set(int selectclk,unsigned long clk_freq,unsigned long out_clk);
+
diff --git a/arch/arm/include/asm/arch-sc2/fixme.h b/arch/arm/include/asm/arch-sc2/fixme.h
new file mode 100644
index 0000000..e7f638d
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/fixme.h
@@ -0,0 +1,107 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _ROM_FIXME_H_
+#define _ROM_FIXME_H_
+
+#define ROM_FIXME 1
+
+#ifdef ROM_FIXME
+
+/*OTP*/
+#define OTP_LIC0 (SYSCTRL_STICKY_REG0)
+#define OTP_LIC1 (SYSCTRL_STICKY_REG0)
+#define OTP_LIC2 (SYSCTRL_STICKY_REG0)
+#define OTP_LIC3 (SYSCTRL_STICKY_REG0)
+
+/*PLL*/
+#define HHI_GP1_PLL_CNTL0 (SYSCTRL_STICKY_REG0)
+#define HHI_GP1_PLL_CNTL1 (SYSCTRL_STICKY_REG0)
+#define HHI_GP1_PLL_CNTL2 (SYSCTRL_STICKY_REG0)
+#define HHI_GP1_PLL_CNTL3 (SYSCTRL_STICKY_REG0)
+#define HHI_GP1_PLL_CNTL4 (SYSCTRL_STICKY_REG0)
+#define HHI_GP1_PLL_CNTL5 (SYSCTRL_STICKY_REG0)
+#define HHI_GP1_PLL_CNTL6 (SYSCTRL_STICKY_REG0)
+
+#define HHI_SYS_CPU_CLK_CNTL0 (SYSCTRL_STICKY_REG0)
+#define HHI_SYS_CPU_CLK_CNTL1 (SYSCTRL_STICKY_REG0)
+#define HHI_SYS_CPU_CLK_CNTL2 (SYSCTRL_STICKY_REG0)
+#define HHI_SYS_CPU_CLK_CNTL3 (SYSCTRL_STICKY_REG0)
+#define HHI_SYS_CPU_CLK_CNTL4 (SYSCTRL_STICKY_REG0)
+#define HHI_SYS_CPU_CLK_CNTL5 (SYSCTRL_STICKY_REG0)
+#define HHI_SYS_CPU_CLK_CNTL6 (SYSCTRL_STICKY_REG0)
+
+#define HHI_FIX_PLL_CNTL0 (SYSCTRL_STICKY_REG0)
+#define HHI_FIX_PLL_CNTL1 (SYSCTRL_STICKY_REG0)
+#define HHI_FIX_PLL_CNTL2 (SYSCTRL_STICKY_REG0)
+#define HHI_FIX_PLL_CNTL3 (SYSCTRL_STICKY_REG0)
+#define HHI_FIX_PLL_CNTL4 (SYSCTRL_STICKY_REG0)
+#define HHI_FIX_PLL_CNTL5 (SYSCTRL_STICKY_REG0)
+#define HHI_FIX_PLL_CNTL6 (SYSCTRL_STICKY_REG0)
+#define P_HHI_FIX_PLL_CNTL0 (SYSCTRL_STICKY_REG0)
+
+#define P_HHI_MPEG_CLK_CNTL (SYSCTRL_STICKY_REG0)
+
+#define HHI_SYS_PLL_CNTL0 (SYSCTRL_STICKY_REG0)
+#define HHI_SYS_PLL_CNTL1 (SYSCTRL_STICKY_REG0)
+#define HHI_SYS_PLL_CNTL2 (SYSCTRL_STICKY_REG0)
+#define HHI_SYS_PLL_CNTL3 (SYSCTRL_STICKY_REG0)
+#define HHI_SYS_PLL_CNTL4 (SYSCTRL_STICKY_REG0)
+#define HHI_SYS_PLL_CNTL5 (SYSCTRL_STICKY_REG0)
+#define HHI_SYS_PLL_CNTL6 (SYSCTRL_STICKY_REG0)
+
+#define HHI_SYS_CPU_CLK_CNTL (SYSCTRL_STICKY_REG0)
+
+/*ADC*/
+#define P_AO_SAR_ADC_REG11 (volatile uint32_t *)(SYSCTRL_STICKY_REG0)
+#define P_AO_SAR_ADC_REG12 (volatile uint32_t *)(SYSCTRL_STICKY_REG0)
+#define P_AO_SAR_ADC_REG13 (volatile uint32_t *)(SYSCTRL_STICKY_REG0)
+#define P_AO_SAR_ADC_REG3 (volatile uint32_t *)(SYSCTRL_STICKY_REG0)
+#define P_AO_SAR_CLK (volatile uint32_t *)(SYSCTRL_STICKY_REG0)
+#define P_AO_SAR_ADC_REG0 (volatile uint32_t *)(SYSCTRL_STICKY_REG0)
+#define P_AO_SAR_ADC_CHAN_LIST (volatile uint32_t *)(SYSCTRL_STICKY_REG0)
+
+#define P_AO_SAR_ADC_AVG_CNTL (volatile uint32_t *)(SYSCTRL_STICKY_REG0)
+#define P_AO_SAR_ADC_DELAY (volatile uint32_t *)(SYSCTRL_STICKY_REG0)
+
+#define P_AO_SAR_ADC_AUX_SW (volatile uint32_t *)(SYSCTRL_STICKY_REG0)
+#define P_AO_SAR_ADC_CHAN_10_SW (volatile uint32_t *)(SYSCTRL_STICKY_REG0)
+#define P_AO_SAR_ADC_DETECT_IDLE_SW (volatile uint32_t *)(SYSCTRL_STICKY_REG0)
+#define P_AO_SAR_ADC_FIFO_RD (volatile uint32_t *)(SYSCTRL_STICKY_REG0)
+#define P_AO_SAR_ADC_AVG_CNTL (volatile uint32_t *)(SYSCTRL_STICKY_REG0)
+
+
+/*SPI*/
+#define SPI_START_ADDR (SYSCTRL_STICKY_REG0)
+
+#define P_PAD_PULL_UP_EN_REG0 (volatile uint32_t *)(SYSCTRL_STICKY_REG0)
+#define P_PERIPHS_PIN_MUX_0 (volatile uint32_t *)(SYSCTRL_STICKY_REG0)
+#define P_PERIPHS_PIN_MUX_1 (volatile uint32_t *)(SYSCTRL_STICKY_REG0)
+#define AO_RTI_PINMUX_REG0 (SYSCTRL_STICKY_REG0)
+#define AO_GPIO_O_EN_N (SYSCTRL_STICKY_REG0)
+#define AO_GPIO_I (SYSCTRL_STICKY_REG0)
+#define P_PAD_PULL_UP_REG0 (volatile uint32_t *)(SYSCTRL_STICKY_REG0)
+#define AO_RTI_PULL_UP_EN_REG (SYSCTRL_STICKY_REG0)
+#define AO_RTI_PULL_UP_REG (SYSCTRL_STICKY_REG0)
+#define P_AO_PAD_DS_B (SYSCTRL_STICKY_REG0)
+
+/*TIMER*/
+//#define ISA_TIMERE (SYSCTRL_STICKY_REG0)
+//#define P_ISA_TIMERE (SYSCTRL_STICKY_REG0)
+
+/*DMC*/
+#define P_PREG_STICKY_REG0 (SYSCTRL_STICKY_REG0)
+
+/*power*/
+#define HHI_MEM_PD_REG0 (SYSCTRL_STICKY_REG0)
+
+/*UART*/
+//#define P_AO_TIMEBASE_CNTL1 (SYSCTRL_STICKY_REG0)
+//#define P_AO_RTI_PINMUX_REG0 (SYSCTRL_STICKY_REG0)
+
+#endif
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-sc2/gpio.h b/arch/arm/include/asm/arch-sc2/gpio.h
new file mode 100644
index 0000000..2467368
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/gpio.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_ARCH_MESON_GPIO_H
+#define __ASM_ARCH_MESON_GPIO_H
+
+
+#endif /* __ASM_ARCH_MESON_GPIO_H */
diff --git a/arch/arm/include/asm/arch-sc2/i2c.h b/arch/arm/include/asm/arch-sc2/i2c.h
new file mode 100644
index 0000000..a93a09d
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/i2c.h
@@ -0,0 +1,280 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AML_MACH_I2C__
+#define __AML_MACH_I2C__
+
+#include <asm/io.h>
+#include <asm/arch/secure_apb.h>
+
+/**
+ * struct i2c_msg - an I2C transaction segment beginning with START
+ * @addr: Slave address, either seven or ten bits. When this is a ten
+ * bit address, I2C_M_TEN must be set in @flags and the adapter
+ * must support I2C_FUNC_10BIT_ADDR.
+ * @flags: I2C_M_RD is handled by all adapters. No other flags may be
+ * provided unless the adapter exported the relevant I2C_FUNC_*
+ * flags through i2c_check_functionality().
+ * @len: Number of data bytes in @buf being read from or written to the
+ * I2C slave address. For read transactions where I2C_M_RECV_LEN
+ * is set, the caller guarantees that this buffer can hold up to
+ * 32 bytes in addition to the initial length byte sent by the
+ * slave (plus, if used, the SMBus PEC); and this value will be
+ * incremented by the number of block data bytes received.
+ * @buf: The buffer into which data is read, or from which it's written.
+ *
+ * An i2c_msg is the low level representation of one segment of an I2C
+ * transaction. It is visible to drivers in the @i2c_transfer() procedure,
+ * to userspace from i2c-dev, and to I2C adapter drivers through the
+ * @i2c_adapter.@master_xfer() method.
+ *
+ * Except when I2C "protocol mangling" is used, all I2C adapters implement
+ * the standard rules for I2C transactions. Each transaction begins with a
+ * START. That is followed by the slave address, and a bit encoding read
+ * versus write. Then follow all the data bytes, possibly including a byte
+ * with SMBus PEC. The transfer terminates with a NAK, or when all those
+ * bytes have been transferred and ACKed. If this is the last message in a
+ * group, it is followed by a STOP. Otherwise it is followed by the next
+ * @i2c_msg transaction segment, beginning with a (repeated) START.
+ *
+ * Alternatively, when the adapter supports I2C_FUNC_PROTOCOL_MANGLING then
+ * passing certain @flags may have changed those standard protocol behaviors.
+ * Those flags are only for use with broken/nonconforming slaves, and with
+ * adapters which are known to support the specific mangling options they
+ * need (one or more of IGNORE_NAK, NO_RD_ACK, NOSTART, and REV_DIR_ADDR).
+ */
+struct i2c_msg {
+ __u16 addr; /* slave address */
+ __u16 flags;
+#define I2C_M_TEN 0x0010 /* this is a ten bit chip address */
+#define I2C_M_RD 0x0001 /* read data, from slave to master */
+#define I2C_M_NOSTART 0x4000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_REV_DIR_ADDR 0x2000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_IGNORE_NAK 0x1000 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_NO_RD_ACK 0x0800 /* if I2C_FUNC_PROTOCOL_MANGLING */
+#define I2C_M_RECV_LEN 0x0400 /* length will be first received byte */
+ __u16 len; /* msg length */
+ __u8 *buf; /* pointer to msg data */
+};
+
+#define MESON_I2C_MASTER_AO_START (AO_I2C_M_0_CONTROL_REG)
+//#define MESON_I2C_MASTER_AO_END (0xc810051c+5)
+
+#define MESON_I2C_MASTER_A_START CBUS_REG_ADDR(I2C_M_0_CONTROL_REG)
+#define MESON_I2C_MASTER_A_END (CBUS_REG_ADDR(I2C_M_0_RDATA_REG1+1)-1)
+
+#define MESON_I2C_MASTER_B_START CBUS_REG_ADDR(I2C_M_1_CONTROL_REG)
+#define MESON_I2C_MASTER_B_END (CBUS_REG_ADDR(I2C_M_1_RDATA_REG1+1)-1)
+
+#define MESON_I2C_MASTER_C_START CBUS_REG_ADDR(I2C_M_2_CONTROL_REG)
+#define MESON_I2C_MASTER_C_END (CBUS_REG_ADDR(I2C_M_2_RDATA_REG1+1)-1)
+
+#define MESON_I2C_MASTER_D_START CBUS_REG_ADDR(I2C_M_3_CONTROL_REG)
+#define MESON_I2C_MASTER_D_END (CBUS_REG_ADDR(I2C_M_3_RDATA_REG1+1)-1)
+
+#define MESON_I2C_SLAVE_START CBUS_REG_ADDR(I2C_S_CONTROL_REG)
+#define MESON_I2C_SLAVE_END (CBUS_REG_ADDR(I2C_S_CNTL1_REG+1)-1)
+
+
+#define AML_I2C_MASTER_AO 0
+#define AML_I2C_MASTER_A 1
+#define AML_I2C_MASTER_B 2
+#define AML_I2C_MASTER_C 3
+#define AML_I2C_MASTER_D 4
+
+
+#define AML_I2C_SLAVE_ADDR 0x6c
+
+/*M1 i2c pinmux
+ * I/O I2C_MASTER_A I2C_MASTER_B I2C_SLAVE
+ * GPIO_JTAG_TMS SCK_A REG1[12] SCK_A REG1[13]
+ * GPIO_JTAG_TDI SDA_A REG1[12] SDA_A REG1[13]
+ * GPIO_JTAG_TCK SCK_B REG1[16] SCK_A REG1[17]
+ * GPIO_JTAG_TDO SDA_B REG1[20] SDA_A REG1[21]
+ * GPIOB_0 SCK_B REG2[5] SCK_A REG2[6]
+ * GPIOB_1 SDA_B REG2[2] SDA_A REG2[3]
+ * GPIOB_2 SCK_A REGS[13] SCK_A REG2[14]
+ * GPIOB_3 SDA_A REG2[9] SDA_A REG2[10]
+ * GPIOC_13 SCK_B REG3[28] SCK_A REG3[29]
+ * GPIOC_14 SDA_B REG3[25] SDA_A REG3[26]
+ * GPIOC_21 SCK_A REG7[9] SCK_A REG7[10]
+ * GPIOC_22 SDA_A REG7[6] SDA_A REG7[7]
+ * GPIOE_16 SCK_B REG5[27] SCK_A REG5[28]
+ * GPIOE_17 SDA_B REG5[25] SDA_A REG5[26]
+*/
+
+/*i2c master a*/
+
+
+#define MESON_I2C_MASTER_A_GPIOZ_17_REG (PERIPHS_PIN_MUX_9)
+#define MESON_I2C_MASTER_A_GPIOZ_17_BIT (1<<7)
+#define MESON_I2C_MASTER_A_GPIOZ_18_REG (PERIPHS_PIN_MUX_9)
+#define MESON_I2C_MASTER_A_GPIOZ_18_BIT (1<<8)
+
+#define MESON_I2C_MASTER_A_GPIOW_0_REG (PERIPHS_PIN_MUX_5)
+#define MESON_I2C_MASTER_A_GPIOW_0_BIT (1<<22)
+#define MESON_I2C_MASTER_A_GPIOW_1_REG (PERIPHS_PIN_MUX_5)
+#define MESON_I2C_MASTER_A_GPIOW_1_BIT (1<<23)
+
+/*i2c master b*/
+
+
+#define MESON_I2C_MASTER_B_GPIOH_3_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_B_GPIOH_3_BIT (1<<6)
+#define MESON_I2C_MASTER_B_GPIOH_4_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_B_GPIOH_4_BIT (1<<7)
+
+#define MESON_I2C_MASTER_B_GPIOY_12_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_B_GPIOY_12_BIT (1<<14)
+#define MESON_I2C_MASTER_B_GPIOY_13_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_B_GPIOY_13_BIT (1<<15)
+
+/*i2c master c*/
+#define MESON_I2C_MASTER_C_GPIOY_7_REG (PERIPHS_PIN_MUX_4)
+#define MESON_I2C_MASTER_C_GPIOY_7_BIT (1<<28)
+#define MESON_I2C_MASTER_C_GPIOY_8_REG (PERIPHS_PIN_MUX_4)
+#define MESON_I2C_MASTER_C_GPIOY_8_BIT (1<<29)
+
+#define MESON_I2C_MASTER_C_GPIOX_0_REG (PERIPHS_PIN_MUX_1)
+#define MESON_I2C_MASTER_C_GPIOX_0_BIT (1<<22)
+#define MESON_I2C_MASTER_C_GPIOX_1_REG (PERIPHS_PIN_MUX_1)
+#define MESON_I2C_MASTER_C_GPIOX_1_BIT (1<<23)
+
+/*i2c master d*/
+
+
+#define MESON_I2C_MASTER_D_GPIOY_10_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_D_GPIOY_10_BIT (1<<10)
+#define MESON_I2C_MASTER_D_GPIOY_11_REG (PERIPHS_PIN_MUX_10)
+#define MESON_I2C_MASTER_D_GPIOY_11_BIT (1<<11)
+
+#define MESON_I2C_MASTER_D_GPIOH_5_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_D_GPIOH_5_BIT (1<<23)
+#define MESON_I2C_MASTER_D_GPIOH_6_REG (PERIPHS_PIN_MUX_7)
+#define MESON_I2C_MASTER_D_GPIOH_6_BIT (1<<24)
+
+/*i2c master AO*/
+
+
+#define MESON_I2C_MASTER_AO_GPIOAO_4_REG (P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */
+#define MESON_I2C_MASTER_AO_GPIOAO_4_BIT (1<<8)
+#define MESON_I2C_MASTER_AO_GPIOAO_5_REG (P_AO_RTI_PINMUX_REG0) /* P_AO_RTI_PIN_MUX_REG */
+#define MESON_I2C_MASTER_AO_GPIOAO_5_BIT (1<<9)
+
+/*i2c slave*/
+#define MESON_I2C_SLAVE_JTAG_TMS_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TMS_BIT (1<<13)
+#define MESON_I2C_SLAVE_JTAG_TDI_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TDI_BIT (1<<13)
+
+#define MESON_I2C_SLAVE_GPIOB_2_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_2_BIT (1<<14)
+#define MESON_I2C_SLAVE_GPIOB_3_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_3_BIT (1<<10)
+
+#define MESON_I2C_SLAVE_GPIOC_21_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_7)
+#define MESON_I2C_SLAVE_GPIOC_21_BIT (1<<10)
+#define MESON_I2C_SLAVE_GPIOC_22_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_7)
+#define MESON_I2C_SLAVE_GPIOC_22_BIT (1<<7)
+
+#define MESON_I2C_SLAVE_JTAG_TCK_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TCK_BIT (1<<17)
+#define MESON_I2C_SLAVE_JTAG_TDO_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_1)
+#define MESON_I2C_SLAVE_JTAG_TDO_BIT (1<<21)
+
+#define MESON_I2C_SLAVE_GPIOB_0_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_0_BIT (1<<6)
+#define MESON_I2C_SLAVE_GPIOB_1_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_2)
+#define MESON_I2C_SLAVE_GPIOB_1_BIT (1<<3)
+
+#define MESON_I2C_SLAVE_GPIOC_13_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_3)
+#define MESON_I2C_SLAVE_GPIOC_13_BIT (1<<29)
+#define MESON_I2C_SLAVE_GPIOC_14_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_3)
+#define MESON_I2C_SLAVE_GPIOC_14_BIT (1<<26)
+
+#define MESON_I2C_SLAVE_GPIOC_16_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_5)
+#define MESON_I2C_SLAVE_GPIOC_16_BIT (1<<28)
+#define MESON_I2C_SLAVE_GPIOC_17_REG CBUS_REG_ADDR(PERIPHS_PIN_MUX_5)
+#define MESON_I2C_SLAVE_GPIOC_17_BIT (1<<26)
+
+
+#define AML_I2C_SPPED_50K 50000
+#define AML_I2C_SPPED_100K 100000
+#define AML_I2C_SPPED_200K 200000
+#define AML_I2C_SPPED_300K 300000
+#define AML_I2C_SPPED_400K 400000
+
+struct aml_pinmux_reg_bit {
+ unsigned long scl_reg;
+ unsigned long sda_reg;
+ unsigned int scl_bit;
+ unsigned int sda_bit;
+};
+
+struct aml_i2c_platform{
+ unsigned int slave_addr;/*7bit addr*/
+ unsigned int wait_count;/*i2c wait ack timeout =
+ wait_count * wait_ack_interval */
+ unsigned int wait_ack_interval;
+ unsigned int wait_read_interval;
+ unsigned int wait_xfer_interval;
+ unsigned int master_no;
+ unsigned int use_pio;/*0: hardware i2c, 1: manual pio i2c*/
+ unsigned int master_i2c_speed;
+
+ /* only need 1 i2c master to comunicate with several devices,
+ * should I prepare 2 master interface to use simultaneously?*/
+ struct resource * resource;
+ struct aml_pinmux_reg_bit master_ao_pinmux;
+ struct aml_pinmux_reg_bit master_a_pinmux;
+ struct aml_pinmux_reg_bit master_b_pinmux;
+ struct aml_pinmux_reg_bit master_c_pinmux;
+ struct aml_pinmux_reg_bit master_d_pinmux;
+
+ struct aml_pinmux_reg_bit slave_reg_bit;
+};
+
+/**************i2c software gpio***************/
+
+#define MESON_I2C_PREG_GPIOC_OE CBUS_REG_ADDR(PREG_FGPIO_EN_N)
+#define MESON_I2C_PREG_GPIOC_OUTLVL CBUS_REG_ADDR(PREG_FGPIO_O)
+#define MESON_I2C_PREG_GPIOC_INLVL CBUS_REG_ADDR(PREG_FGPIO_I)
+
+#define MESON_I2C_PREG_GPIOE_OE CBUS_REG_ADDR(PREG_HGPIO_EN_N)
+#define MESON_I2C_PREG_GPIOE_OUTLVL CBUS_REG_ADDR(PREG_HGPIO_O)
+#define MESON_I2C_PREG_GPIOE_INLVL CBUS_REG_ADDR(PREG_HGPIO_I)
+
+#define MESON_I2C_PREG_GPIOA_OE CBUS_REG_ADDR(PREG_EGPIO_EN_N)
+#define MESON_I2C_PREG_GPIOA_OUTLVL CBUS_REG_ADDR(PREG_EGPIO_O)
+#define MESON_I2C_PREG_GPIOA_INLVL CBUS_REG_ADDR(PREG_EGPIO_I)
+
+struct aml_sw_i2c_pins
+{
+ unsigned int scl_reg_out;
+ unsigned int scl_reg_in;
+ unsigned int scl_bit;
+ unsigned int scl_oe;
+ unsigned int sda_reg_out;
+ unsigned int sda_reg_in;
+ unsigned int sda_bit;
+ unsigned int sda_oe;
+};
+
+
+struct aml_sw_i2c_platform {
+ struct aml_sw_i2c_pins sw_pins;
+
+ /* local settings */
+ int udelay; /* half clock cycle time in us,
+ minimum 2 us for fast-mode I2C,
+ minimum 5 us for standard-mode I2C and SMBus,
+ maximum 50 us for SMBus */
+ int timeout; /* in jiffies */
+};
+
+
+#endif //__AML_MACH_I2C__
+
+
diff --git a/arch/arm/include/asm/arch-sc2/io.h b/arch/arm/include/asm/arch-sc2/io.h
new file mode 100644
index 0000000..fd3981a
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/io.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __MACH_MESSON_REGS_IO_H
+#define __MACH_MESSON_REGS_IO_H
+
+#ifndef __ASSEMBLY__
+
+#include <asm/io.h>
+#define IO_CBUS_BASE (0xFFD00000L)
+#define IO_AXI_BUS_BASE (0xFFB00000L) /* gpv */
+#define IO_AHB_BUS_BASE (0xFF500000L) /* usb0 */
+#define IO_APB_BUS_BASE (0xFFFC0000L) /* AHB SRAM, sec/sys ahb? txlx_mem_map.xlsx */
+#define IO_APB_HDMI_BUS_BASE (0xFFE00000L) /* */
+#define IO_VPU_BUS_BASE (0xFF900000L) /* VPU */
+
+#define CBUS_REG_OFFSET(reg) ((reg) << 2)
+#define CBUS_REG_ADDR(reg) (IO_CBUS_BASE + CBUS_REG_OFFSET(reg))
+
+#define AXI_REG_OFFSET(reg) ((reg) << 2)
+#define AXI_REG_ADDR(reg) (IO_AXI_BUS_BASE + AXI_REG_OFFSET(reg))
+
+#define AHB_REG_OFFSET(reg) ((reg) << 2)
+#define AHB_REG_ADDR(reg) (IO_AHB_BUS_BASE + AHB_REG_OFFSET(reg))
+
+#define VPU_REG_OFFSET(reg) ((reg) << 2)
+#define VPU_REG_ADDR(reg) (IO_VPU_BUS_BASE + VPU_REG_OFFSET(reg))
+
+
+#define APB_REG_OFFSET(reg) (reg)
+#define APB_REG_ADDR(reg) (IO_APB_BUS_BASE + APB_REG_OFFSET(reg))
+#define APB_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0)
+
+#define APB_HDMI_REG_OFFSET(reg) (reg)
+#define APB_HDMI_REG_ADDR(reg) (IO_APB_HDMI_BUS_BASE + APB_HDMI_REG_OFFSET(reg))
+#define APB_HDMI_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0)
+
+
+#define WRITE_CBUS_REG(reg, val) __raw_writel(val, CBUS_REG_ADDR(reg))
+#define READ_CBUS_REG(reg) (__raw_readl(CBUS_REG_ADDR(reg)))
+#define WRITE_CBUS_REG_BITS(reg, val, start, len) \
+ WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_CBUS_REG_BITS(reg, start, len) \
+ ((READ_CBUS_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)&(~(mask))))
+#define SET_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)|(mask)))
+
+#define WRITE_AXI_REG(reg, val) __raw_writel(val, AXI_REG_ADDR(reg))
+#define READ_AXI_REG(reg) (__raw_readl(AXI_REG_ADDR(reg)))
+#define WRITE_AXI_REG_BITS(reg, val, start, len) \
+ WRITE_AXI_REG(reg, (READ_AXI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_AXI_REG_BITS(reg, start, len) \
+ ((READ_AXI_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)&(~(mask))))
+#define SET_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)|(mask)))
+
+#define WRITE_AHB_REG(reg, val) __raw_writel(val, AHB_REG_ADDR(reg))
+#define READ_AHB_REG(reg) (__raw_readl(AHB_REG_ADDR(reg)))
+#define WRITE_AHB_REG_BITS(reg, val, start, len) \
+ WRITE_AHB_REG(reg, (READ_AHB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_AHB_REG_BITS(reg, start, len) \
+ ((READ_AHB_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)&(~(mask))))
+#define SET_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)|(mask)))
+
+#define WRITE_APB_REG(reg, val) __raw_writel(val, APB_REG_ADDR(reg))
+#define READ_APB_REG(reg) (__raw_readl(APB_REG_ADDR(reg)))
+#define WRITE_APB_REG_BITS(reg, val, start, len) \
+ WRITE_APB_REG(reg, (READ_APB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_APB_REG_BITS(reg, start, len) \
+ ((READ_APB_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)&(~(mask))))
+#define SET_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)|(mask)))
+
+#define WRITE_APB_HDMI_REG(reg, val) __raw_writel(val, APB_HDMI_REG_ADDR(reg))
+#define READ_APB_HDMI_REG(reg) (__raw_readl(APB_HDMI_REG_ADDR(reg)))
+#define WRITE_APB_HDMI_REG_BITS(reg, val, start, len) \
+ WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_APB_HDMI_REG_BITS(reg, start, len) \
+ ((READ_APB_HDMI_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)&(~(mask))))
+#define SET_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)|(mask)))
+
+/* for back compatible alias */
+#define WRITE_MPEG_REG(reg, val) \
+ WRITE_CBUS_REG(reg, val)
+#define READ_MPEG_REG(reg) \
+ READ_CBUS_REG(reg)
+#define WRITE_MPEG_REG_BITS(reg, val, start, len) \
+ WRITE_CBUS_REG_BITS(reg, val, start, len)
+#define READ_MPEG_REG_BITS(reg, start, len) \
+ READ_CBUS_REG_BITS(reg, start, len)
+#define CLEAR_MPEG_REG_MASK(reg, mask) \
+ CLEAR_CBUS_REG_MASK(reg, mask)
+#define SET_MPEG_REG_MASK(reg, mask) \
+ SET_CBUS_REG_MASK(reg, mask)
+#endif
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-sc2/mailbox.h b/arch/arm/include/asm/arch-sc2/mailbox.h
new file mode 100644
index 0000000..259ae8f
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/mailbox.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+ /*
+ *
+ * Copyright (C) 2012 Amlogic, Inc.
+ *
+ * Author: Platform-SH@amlogic.com
+ *
+ */
+
+#ifndef __MAILBOX_H__
+#define __MAILBOX_H__
+#include <asm/arch/secure_apb.h>
+#include <common.h>
+
+#define REE2AO_SET_ADDR MAILBOX_SET_MBOX03
+#define REE2AO_STS_ADDR MAILBOX_STS_MBOX03
+#define REE2AO_CLR_ADDR MAILBOX_CLR_MBOX03
+#define REE2AO_WR_ADDR MAILBOX_WR_MBOX03
+#define REE2AO_RD_ADDR MAILBOX_RD_MBOX03
+#define REE2AO_IRQCLR_ADDR MAILBOX_IRQA_CLR
+
+#define MAILBOX_USER_DATA_SIZE 96
+
+#define MHU_SYNC (1 << 26)
+#define MHU_CMD_BUILD(command, size) \
+ (((command) & 0xffff) | (((size) & 0x1ff) << 16) | MHU_SYNC)
+#define MHU_ACK_MASK(mbox) (1 << ((mbox)*2 + 1))
+
+#define MHU_PAYLOAD_SIZE 0x80
+#define MHU_DATA_OFFSET 0x1c
+#define REE2AO_MBOX_ID 0x3
+/* ...Message composition with module(6bits), function(10bits) */
+#define __MBX_COMPOSE_MSG(mod, func) (((mod) << 10) | ((func) & 0x3FF))
+
+/*******************************************************************************
+ * Define moudle type here, 6bits valid
+ ******************************************************************************/
+#define MBX_SYSTEM 0x0
+
+/*******************************************************************************
+ * Define function here, 10bits valid
+ ******************************************************************************/
+ /*SYSTEM*/
+#define CMD_UNDEFINE 0x0
+#define CMD_TEST 0x6
+#define CMD_LED_INFO 0xF7
+
+/*******************************************************************************
+ * Mssage Comopsition
+ ******************************************************************************/
+#define MBX_CMD_TEST __MBX_COMPOSE_MSG(MBX_SYSTEM, CMD_TEST)
+enum {
+ HIFIA_REE_CHANNEL = 0,
+ HIFIB_REE_CHANNEL = 1,
+ SECPU_REE_CHANNEL = 2,
+ AOCPU_REE_CHANNEL = 3,
+};
+
+void mhu_init(void);
+/*message max size MAILBOX_USER_DATA_SIZE 96 byte*/
+int scpi_send_data(uint32_t chan, uint32_t command,
+ void *sendmessage, uint32_t sendsize,
+ void *revmessage, uint32_t revsize);
+#endif /* __SCPI_FIFO_H__ */
diff --git a/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_ddr3.h b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_ddr3.h
new file mode 100644
index 0000000..c067367
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_ddr3.h
@@ -0,0 +1,637 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief DDR3U_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_DDR3U_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Train vrefDAC0 During Read Deskew
+ // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] = MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] = SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] = SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] = RFU, must be zero (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero)
+ //
+ //
+ //
+ // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] = PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte
+ // 0x0 = All rank populated with all the byte (tyical configuration)
+ //
+ // MsgMisc[7] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware.
+ // Please reference this revision ID when filing support cases with Synopsys.
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Module Type:
+ // 0x01 = DDR3 unbuffered
+ // 0x02 = Reserved
+ // 0x03 = Reserved
+ // 0x04 = Reserved
+ // 0x05 = Reserved
+ //
+ uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7):
+ // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting)
+ uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ // Total number of DQ bits enabled in PHY
+ uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS.
+ //
+ // If the bit is set to 1, the CS is connected to DRAM.
+ // If the bit is set to 0, the CS is not connected to DRAM.
+ //
+ // CsPresent[0] = CS0 is populated with DRAM
+ // CsPresent[1] = CS1 is populated with DRAM
+ // CsPresent[2] = CS2 is populated with DRAM
+ // CsPresent[3] = CS3 is populated with DRAM
+ // CsPresent[7:4] = Reserved (must be programmed to 0)
+ //
+ //
+ uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 0
+ uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 1
+ uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ // Corresponds to CS[3:0]
+ // 1 = Address Mirror.
+ // 0 = No Address Mirror.
+ uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ // Additional mode bits.
+ //
+ // Bit fields:
+ // [0] SlowAccessMode :
+ // 1 = 2T Address Timing.
+ // 0 = 1T Address Timing.
+ // [7-1] RFU, must be zero
+ uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[10] = RFU, must be zero
+ // SequenceCtrl[11] = RFU, must be zero
+ // SequenceCtrl[12] = RFU, must be zero
+ // SequenceCtrl[13] = RFU, must be zero
+ // SequenceCtrl[15-14] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A
+
+
+
+ uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D training in: Rd2D, Wr2D
+ //
+ // Reserved1E[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1E[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR6
+ // 2 = limit to +/-4 %VDDQ from MR6
+ // …
+ // 15 = limit to +/-30% VDDQ from MR6
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A
+ // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset.
+ uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ // Value of DDR mode register MR0 for all ranks for current pstate
+ uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Value of DDR mode register MR1 for all ranks for current pstate
+ uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ // Value of DDR mode register MR2 for all ranks for current pstate
+ uint8_t Reserved64; // Byte offset 0x64, CSR Addr 0x54032, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved65; // Byte offset 0x65, CSR Addr 0x54032, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6E; // Byte offset 0x6e, CSR Addr 0x54037, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6F; // Byte offset 0x6f, CSR Addr 0x54037, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved71; // Byte offset 0x71, CSR Addr 0x54038, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved72; // Byte offset 0x72, CSR Addr 0x54039, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved73; // Byte offset 0x73, CSR Addr 0x54039, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl0; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl2; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl3; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl4; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl5; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl7; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7C; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7D; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A
+
+ uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A
+
+ uint8_t Reserved8A; // Byte offset 0x8a, CSR Addr 0x54045, Direction=N/A
+
+ uint8_t Reserved8B; // Byte offset 0x8b, CSR Addr 0x54045, Direction=N/A
+
+ uint8_t Reserved8C; // Byte offset 0x8c, CSR Addr 0x54046, Direction=N/A
+
+ uint8_t Reserved8D; // Byte offset 0x8d, CSR Addr 0x54046, Direction=N/A
+
+ uint8_t Reserved8E; // Byte offset 0x8e, CSR Addr 0x54047, Direction=N/A
+
+ uint8_t Reserved8F; // Byte offset 0x8f, CSR Addr 0x54047, Direction=N/A
+
+ uint8_t Reserved90; // Byte offset 0x90, CSR Addr 0x54048, Direction=N/A
+
+ uint8_t Reserved91; // Byte offset 0x91, CSR Addr 0x54048, Direction=N/A
+
+ uint8_t Reserved92; // Byte offset 0x92, CSR Addr 0x54049, Direction=N/A
+
+ uint8_t Reserved93; // Byte offset 0x93, CSR Addr 0x54049, Direction=N/A
+
+ uint8_t Reserved94; // Byte offset 0x94, CSR Addr 0x5404a, Direction=N/A
+
+ uint8_t Reserved95; // Byte offset 0x95, CSR Addr 0x5404a, Direction=N/A
+
+ uint8_t Reserved96; // Byte offset 0x96, CSR Addr 0x5404b, Direction=N/A
+
+ uint8_t Reserved97; // Byte offset 0x97, CSR Addr 0x5404b, Direction=N/A
+
+ uint8_t Reserved98; // Byte offset 0x98, CSR Addr 0x5404c, Direction=N/A
+
+ uint8_t Reserved99; // Byte offset 0x99, CSR Addr 0x5404c, Direction=N/A
+
+ uint8_t Reserved9A; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=N/A
+
+ uint8_t Reserved9B; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=N/A
+
+ uint8_t Reserved9C; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=N/A
+
+ uint8_t Reserved9D; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=N/A
+
+ uint8_t Reserved9E; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=N/A
+
+ uint8_t Reserved9F; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=N/A
+
+ uint8_t ReservedA0; // Byte offset 0xa0, CSR Addr 0x54050, Direction=N/A
+
+ uint8_t ReservedA1; // Byte offset 0xa1, CSR Addr 0x54050, Direction=N/A
+
+ uint8_t ReservedA2; // Byte offset 0xa2, CSR Addr 0x54051, Direction=N/A
+
+ uint8_t ReservedA3; // Byte offset 0xa3, CSR Addr 0x54051, Direction=N/A
+
+} __attribute__ ((packed)) PMU_SMB_DDR3U_1D_t;
diff --git a/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_ddr4.h b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_ddr4.h
new file mode 100644
index 0000000..6dfd4d0
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_ddr4.h
@@ -0,0 +1,2380 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief DDR4U_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_DDR4U_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Train vrefDAC0 During Read Deskew
+ // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] = MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] = SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] = SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D.
+ // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field
+ //
+ // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] = PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte
+ // 0x0 = All rank populated with all the byte (tyical configuration)
+ //
+ // MsgMisc[7] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware.
+ // Please reference this revision ID when filing support cases with Synopsys.
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Module Type:
+ // 0x01 = Reserved
+ // 0x02 = DDR4 unbuffered
+ // 0x03 = Reserved
+ // 0x04 = Reserved
+ // 0x05 = Reserved
+ //
+ uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7):
+ // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting)
+ uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ // Total number of DQ bits enabled in PHY
+ uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS.
+ //
+ // If the bit is set to 1, the CS is connected to DRAM.
+ // If the bit is set to 0, the CS is not connected to DRAM.
+ //
+ // CsPresent[0] = CS0 is populated with DRAM
+ // CsPresent[1] = CS1 is populated with DRAM
+ // CsPresent[2] = CS2 is populated with DRAM
+ // CsPresent[3] = CS3 is populated with DRAM
+ // CsPresent[7:4] = Reserved (must be programmed to 0)
+ //
+ //
+ uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 0
+ uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 1
+ uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ // Corresponds to CS[3:0]
+ // 1 = Address Mirror.
+ // 0 = No Address Mirror.
+ uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ // Additional mode bits.
+ //
+ // Bit fields:
+ // [0] SlowAccessMode :
+ // 1 = 2T Address Timing.
+ // 0 = 1T Address Timing.
+ // [7-1] RFU, must be zero
+ uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[10] = Run Reserved
+ // SequenceCtrl[11] = Run Reserved
+ // SequenceCtrl[12] = Run Reserved
+ // SequenceCtrl[13] = Run Reserved
+ // SequenceCtrl[15-14] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A
+
+
+
+ uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D training in: Rd2D, Wr2D
+ //
+ // Reserved1E[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1E[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR6
+ // 2 = limit to +/-4 %VDDQ from MR6
+ // …
+ // 15 = limit to +/-30% VDDQ from MR6
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A
+ // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset.
+ uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ // Value of DDR mode register MR0 for all ranks for current pstate
+ uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Value of DDR mode register MR1 for all ranks for current pstate
+ uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ // Value of DDR mode register MR2 for all ranks for current pstate
+ uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ // Value of DDR mode register MR3 for all ranks for current pstate
+ uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value of DDR mode register MR4 for all ranks for current pstate
+ uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value of DDR mode register MR5 for all ranks for current pstate
+ uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0.
+ uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // X16 device map. Corresponds to CS[3:0].
+ // X16Present[0] = CS0 is populated with X16 devices
+ // X16Present[1] = CS1 is populated with X16 devices
+ // X16Present[2] = CS2 is populated with X16 devices
+ // X16Present[3] = CS3 is populated with X16 devices
+ // X16Present[7:4] = Reserved (must be programmed to 0)
+ //
+ // Ranks may not contain mixed device types.
+ uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // controls timing of chip select signals when DDR4 gear-down mode is active
+ // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs
+ // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode
+ uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM:
+ // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0
+ // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0
+ // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0
+ uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM:
+ // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1
+ // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1
+ // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1
+ uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM:
+ // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2
+ // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2
+ // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2
+ uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM:
+ // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3
+ // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3
+ // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3
+ uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM:
+ // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4
+ // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4
+ // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4
+ uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM:
+ // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5
+ // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5
+ // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5
+ uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM:
+ // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6
+ // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6
+ // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6
+ uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM:
+ // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7
+ // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7
+ // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7
+ uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices.
+ uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices.
+ uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices.
+ uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices.
+ uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices.
+ uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices.
+ uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices.
+ uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices.
+ uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices.
+ uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices.
+ uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices.
+ uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices.
+ uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices.
+ uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices.
+ uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices.
+ uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices.
+ uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices.
+ uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices.
+ uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices.
+ uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices.
+ uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices.
+ uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices.
+ uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices.
+ uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices.
+ uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices.
+ uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices.
+ uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices.
+ uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices.
+ uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices.
+ uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices.
+ uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices.
+ uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices.
+ uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices.
+ uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices.
+ uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices.
+ uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices.
+ uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices.
+ uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices.
+ uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices.
+ uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices.
+ uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A
+
+ uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A
+
+ uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in
+ // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1).
+ // RdDBI is dynamically disabled in certain training steps,
+ // and so the [RdDBI disabled] CAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_CAS_L[0] == 0: use value in MR0
+ // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2]
+ // Other bits are ignored
+ uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In
+ // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1).
+ // 2tCK write prambles are dynamically disabled in certain training steps,
+ // and so the [1tCK write preamble] WCAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_WCAS_L[0] == 0: use value in MR2
+ // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3]
+ // Other bits are ignored
+ uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In
+ // Contains various options for training DDR4 Devices.
+ //
+ // Bit fields:
+ //
+ // D4Misc[7:1] RFU, must be zero
+ //
+ // D4Misc[0] = protect memory reset
+ // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training.
+ // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training
+} __attribute__ ((packed)) PMU_SMB_DDR4U_1D_t;
diff --git a/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_ddr4_2d.h b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_ddr4_2d.h
new file mode 100644
index 0000000..35b1e23
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_ddr4_2d.h
@@ -0,0 +1,2282 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief DDR4U_2D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_DDR4U_2D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Train vrefDAC0 During Read Deskew
+ // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] = MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] = SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] = SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D.
+ // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field
+ //
+ // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] = PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte
+ // 0x0 = All rank populated with all the byte (tyical configuration)
+ //
+ // MsgMisc[7] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware.
+ // Please reference this revision ID when filing support cases with Synopsys.
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Module Type:
+ // 0x01 = Reserved
+ // 0x02 = DDR4 unbuffered
+ // 0x03 = Reserved
+ // 0x04 = Reserved
+ // 0x05 = Reserved
+ //
+ uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7):
+ // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting)
+ uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ // Total number of DQ bits enabled in PHY
+ uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS.
+ //
+ // If the bit is set to 1, the CS is connected to DRAM.
+ // If the bit is set to 0, the CS is not connected to DRAM.
+ //
+ // CsPresent[0] = CS0 is populated with DRAM
+ // CsPresent[1] = CS1 is populated with DRAM
+ // CsPresent[2] = CS2 is populated with DRAM
+ // CsPresent[3] = CS3 is populated with DRAM
+ // CsPresent[7:4] = Reserved (must be programmed to 0)
+ //
+ //
+ uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 0
+ uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 1
+ uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ // Corresponds to CS[3:0]
+ // 1 = Address Mirror.
+ // 0 = No Address Mirror.
+ uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ // Additional mode bits.
+ //
+ // Bit fields:
+ // [0] SlowAccessMode :
+ // 1 = 2T Address Timing.
+ // 0 = 1T Address Timing.
+ // [7-1] RFU, must be zero
+ uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = RFU, must be zero
+ // SequenceCtrl[2] = RFU, must be zero
+ // SequenceCtrl[3] = RFU, must be zero
+ // SequenceCtrl[4] = RFU, must be zero
+ // SequenceCtrl[5] = Run rd2D - 2d read dqs training
+ // SequenceCtrl[6] = Run wr2D - 2d write dq training
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = RFU, must be zero
+ // SequenceCtrl[9] = RFU, must be zero
+ // SequenceCtrl[10] = RFU, must be zero
+ // SequenceCtrl[11] = RFU, must be zero
+ // SequenceCtrl[12] = RFU, must be zero
+ // SequenceCtrl[13] = RFU, must be zero
+ // SequenceCtrl[15-14] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t RX2D_TrainOpt; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In
+ // Bit fields, if 2D read training enabled, then use these additional options:
+ // [0] DFE
+ // 1 = Run rx2D with DFE
+ // 0 = Run rx2D with DFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5-7] RFU, must be zero
+ //
+ uint8_t TX2D_TrainOpt; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Bit fields, if 2D write training is enabled, then use these additional options:
+ // [0] FFE
+ // 1 = Train tx2D with FFE
+ // 0 = Train tx2D with FFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5] FFE Decision Algorithm Control
+ // 1 = FFE chooses the drive strength that maximizes the average eye-area across the entire phy.
+ // 0 = FFE chooses the drive strength that maximizes the smallest eye across the entire phy.
+ // [6-7] RFU, must be zero
+ //
+ uint8_t Share2DVrefResult; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // Bitmap that designates the phy's vref source for every pstate
+ // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock.
+ // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training.
+ uint8_t Delay_Weight2D; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye.
+ uint8_t Voltage_Weight2D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye.
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D training in: Rd2D, Wr2D
+ //
+ // Reserved1E[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1E[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR6
+ // 2 = limit to +/-4 %VDDQ from MR6
+ // …
+ // 15 = limit to +/-30% VDDQ from MR6
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ uint8_t R0_RxClkDly_Margin; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R0_VrefDac_Margin; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R0_TxDqDly_Margin; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R0_DeviceVref_Margin; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved29; // Byte offset 0x29, CSR Addr 0x54014, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2A; // Byte offset 0x2a, CSR Addr 0x54015, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2B; // Byte offset 0x2b, CSR Addr 0x54015, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2C; // Byte offset 0x2c, CSR Addr 0x54016, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2D; // Byte offset 0x2d, CSR Addr 0x54016, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2E; // Byte offset 0x2e, CSR Addr 0x54017, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2F; // Byte offset 0x2f, CSR Addr 0x54017, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved31; // Byte offset 0x31, CSR Addr 0x54018, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved32; // Byte offset 0x32, CSR Addr 0x54019, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t R1_RxClkDly_Margin; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R1_VrefDac_Margin; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R1_TxDqDly_Margin; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R1_DeviceVref_Margin; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved37; // Byte offset 0x37, CSR Addr 0x5401b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved39; // Byte offset 0x39, CSR Addr 0x5401c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3A; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3B; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3D; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3E; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3F; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t R2_RxClkDly_Margin; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R2_VrefDac_Margin; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R2_TxDqDly_Margin; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R2_DeviceVref_Margin; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved48; // Byte offset 0x48, CSR Addr 0x54024, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved49; // Byte offset 0x49, CSR Addr 0x54024, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4A; // Byte offset 0x4a, CSR Addr 0x54025, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t R3_RxClkDly_Margin; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R3_VrefDac_Margin; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R3_TxDqDly_Margin; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R3_DeviceVref_Margin; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved57; // Byte offset 0x57, CSR Addr 0x5402b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved58; // Byte offset 0x58, CSR Addr 0x5402c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved59; // Byte offset 0x59, CSR Addr 0x5402c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5B; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5C; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In
+ // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D.
+ //
+ // Reserved5D[0-3]: bitTimeControl
+ // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point.
+ // 0 = 1 kilobit per point (legacy behavior)
+ // 1 = 2 kilobits per point
+ // 2 = 4 kilobits per point
+ // …
+ // 15 = 32 megabits per point
+ //
+ // Reserved5D[4]: Exhaustive2D
+ // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior)
+ // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point.
+ //
+ // Reserved5D[5:7]: RFU, must be 0
+ uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ // Value of DDR mode register MR0 for all ranks for current pstate
+ uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Value of DDR mode register MR1 for all ranks for current pstate
+ uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ // Value of DDR mode register MR2 for all ranks for current pstate
+ uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ // Value of DDR mode register MR3 for all ranks for current pstate
+ uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value of DDR mode register MR4 for all ranks for current pstate
+ uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value of DDR mode register MR5 for all ranks for current pstate
+ uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0.
+ uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // X16 device map. Corresponds to CS[3:0].
+ // X16Present[0] = CS0 is populated with X16 devices
+ // X16Present[1] = CS1 is populated with X16 devices
+ // X16Present[2] = CS2 is populated with X16 devices
+ // X16Present[3] = CS3 is populated with X16 devices
+ // X16Present[7:4] = Reserved (must be programmed to 0)
+ //
+ // Ranks may not contain mixed device types.
+ uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // controls timing of chip select signals when DDR4 gear-down mode is active
+ // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs
+ // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode
+ uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM:
+ // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0
+ // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0
+ // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0
+ uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM:
+ // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1
+ // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1
+ // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1
+ uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM:
+ // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2
+ // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2
+ // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2
+ uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM:
+ // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3
+ // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3
+ // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3
+ uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM:
+ // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4
+ // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4
+ // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4
+ uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM:
+ // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5
+ // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5
+ // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5
+ uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM:
+ // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6
+ // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6
+ // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6
+ uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM:
+ // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7
+ // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7
+ // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7
+ uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices.
+ uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices.
+ uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices.
+ uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices.
+ uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices.
+ uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices.
+ uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices.
+ uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices.
+ uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices.
+ uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices.
+ uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices.
+ uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices.
+ uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices.
+ uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices.
+ uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices.
+ uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices.
+ uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices.
+ uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices.
+ uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices.
+ uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices.
+ uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices.
+ uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices.
+ uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices.
+ uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices.
+ uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices.
+ uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices.
+ uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices.
+ uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices.
+ uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices.
+ uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices.
+ uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices.
+ uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices.
+ uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices.
+ uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices.
+ uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices.
+ uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices.
+ uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices.
+ uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices.
+ uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices.
+ uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices.
+ uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A
+
+ uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A
+
+ uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in
+ // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1).
+ // RdDBI is dynamically disabled in certain training steps,
+ // and so the [RdDBI disabled] CAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_CAS_L[0] == 0: use value in MR0
+ // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2]
+ // Other bits are ignored
+ uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In
+ // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1).
+ // 2tCK write prambles are dynamically disabled in certain training steps,
+ // and so the [1tCK write preamble] WCAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_WCAS_L[0] == 0: use value in MR2
+ // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3]
+ // Other bits are ignored
+ uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In
+ // Contains various options for training DDR4 Devices.
+ //
+ // Bit fields:
+ //
+ // D4Misc[7:1] RFU, must be zero
+ //
+ // D4Misc[0] = protect memory reset
+ // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training.
+ // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training
+} __attribute__ ((packed)) PMU_SMB_DDR4U_2D_t;
diff --git a/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_lpddr3.h b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_lpddr3.h
new file mode 100644
index 0000000..6850d06
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_lpddr3.h
@@ -0,0 +1,434 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief LPDDR3_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_LPDDR3_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:5] RFU, must be zero
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] RFU, must be zero
+ //
+ // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[7-6] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t Reserved0D; // Byte offset 0x0d, CSR Addr 0x54006, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = RunWrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[10] = RFU, must be zero
+ // SequenceCtrl[11] = RFU, must be zero
+ // SequenceCtrl[12] = Run LPCA - CA Training
+ // SequenceCtrl[13] = RFU, must be zero
+ // SequenceCtrl[14] = RFU, must be zero
+ // SequenceCtrl[15] = RFU, must be zero
+ //
+ uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t DFIMRLMargin; // Byte offset 0x14, CSR Addr 0x5400a, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ //
+ // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system.
+ uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t UseBroadcastMR; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired.
+ //
+ // 0x0 = Use MR<0:17>_A0 for rank 0 channel A
+ // Use MR<0:17>_B0 for rank 0 channel B
+ // Use MR<0:17>_A1 for rank 1 channel A
+ // Use MR<0:17>_B1 for rank 1 channel B
+ //
+ // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks
+ //
+ // This should be set to 1 for all systems.
+ //
+ // Note: If setting this to 0, only mode register settings related to DRAM partial array self-refresh may be different between the ranks and channels. All other mode register settings must be the same for all ranks and channels.
+ uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t LogToPhyByteMap0; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // Physical Byte associated with Channel A logical Byte 0, depending on LogToPhyByteMap0[7] value:
+ // LogToPhyByteMap0[7]==0: Logical Byte 0 map on Physical Byte 0
+ // LogToPhyByteMap0[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap0[6:0]
+ uint8_t LogToPhyByteMap1; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In
+ // Physical Byte associated with Channel A logical Byte 1, depending on LogToPhyByteMap1[7] value:
+ // LogToPhyByteMap1[7]==0: Logical Byte 1 map on Physical Byte 1
+ // LogToPhyByteMap1[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap1[6:0]
+ uint8_t LogToPhyByteMap2; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Physical Byte associated with Channel A logical Byte 2, depending on LogToPhyByteMap2[7] value:
+ // LogToPhyByteMap2[7]==0: Logical Byte 2 map on Physical Byte 2
+ // LogToPhyByteMap2[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap2[6:0]
+ uint8_t LogToPhyByteMap3; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // Physical Byte associated with Channel A logical Byte 3, depending on LogToPhyByteMap3[7] value:
+ // LogToPhyByteMap3[7]==0: Logical Byte 3 map on Physical Byte 3
+ // LogToPhyByteMap3[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap3[6:0]
+ uint8_t LogToPhyByteMap4; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // Physical Byte associated with Channel B logical Byte 0, depending on LogToPhyByteMap4[7] value:
+ // LogToPhyByteMap4[7]==0: Logical Byte 0 map on Physical Byte 4
+ // LogToPhyByteMap4[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap4[6:0]
+ uint8_t LogToPhyByteMap5; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In
+ // Physical Byte associated with Channel B logical Byte 1, depending on LogToPhyByteMap5[7] value:
+ // LogToPhyByteMap5[7]==0: Logical Byte 1 map on Physical Byte 5
+ // LogToPhyByteMap5[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap5[6:0]
+ uint8_t LogToPhyByteMap6; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Physical Byte associated with Channel B logical Byte 2, depending on LogToPhyByteMap6[7] value:
+ // LogToPhyByteMap6[7]==0: Logical Byte 2 map on Physical Byte 6
+ // LogToPhyByteMap6[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap6[6:0]
+ uint8_t LogToPhyByteMap7; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In
+ // Physical Byte associated with Channel B logical Byte 3, depending on LogToPhyByteMap7[7] value:
+ // LogToPhyByteMap7[7]==0: Logical Byte 3 map on Physical Byte 7
+ // LogToPhyByteMap7[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap7[6:0]
+ uint8_t LogToPhyByteMap8; // Byte offset 0x20, CSR Addr 0x54010, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t LogToPhyByteMap9; // Byte offset 0x21, CSR Addr 0x54010, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t EnabledDQsChA; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Total number of DQ bits enabled in PHY Channel A
+ uint8_t CsPresentChA; // Byte offset 0x23, CSR Addr 0x54011, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel A.
+ //
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChA_RR_1_0; // Byte offset 0x24, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RR_0_1; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_1_0; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_0_1; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_A0; // Byte offset 0x31, CSR Addr 0x54018, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0}
+ uint8_t MR2_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0}
+ uint8_t MR3_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0}
+ uint8_t Reserved34; // Byte offset 0x34, CSR Addr 0x5401a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0}
+ uint8_t MR16_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0}
+ uint8_t MR17_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0}
+ uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_A1; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In
+ // Must be programmed the same as MR1_A0
+ uint8_t MR2_A1; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
+ // Must be programmed the same as MR2_A0
+ uint8_t MR3_A1; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
+ // Must be programmed the same as MR3_A0
+ uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_A1; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
+ // Must be programmed the same as MR11_A0
+ uint8_t MR16_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1}
+ uint8_t MR17_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1}
+ uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved41; // Byte offset 0x41, CSR Addr 0x54020, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved42; // Byte offset 0x42, CSR Addr 0x54021, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved43; // Byte offset 0x43, CSR Addr 0x54021, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved44; // Byte offset 0x44, CSR Addr 0x54022, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t EnabledDQsChB; // Byte offset 0x48, CSR Addr 0x54024, Direction=In
+ // Total number of DQ bits enabled in PHY Channel B
+ uint8_t CsPresentChB; // Byte offset 0x49, CSR Addr 0x54024, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel B.
+ //
+ // 0x0 = No chip selects are populated with DRAM
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChB_RR_1_0; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RR_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_1; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs01 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_1; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_1; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_0; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_1_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_0_1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_B0; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In
+ // Must be programmed the same as MR1_A0
+ uint8_t MR2_B0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In
+ // Must be programmed the same as MR2_A0
+ uint8_t MR3_B0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=In
+ // Must be programmed the same as MR3_A0
+ uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_B0; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=In
+ // Must be programmed the same as MR11_A0
+ uint8_t MR16_B0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0}
+ uint8_t MR17_B0; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0}
+ uint8_t Reserved5E; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_B1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=In
+ // Must be programmed the same as MR1_A0
+ uint8_t MR2_B1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Must be programmed the same as MR2_A0
+ uint8_t MR3_B1; // Byte offset 0x61, CSR Addr 0x54030, Direction=In
+ // Must be programmed the same as MR3_A0
+ uint8_t Reserved62; // Byte offset 0x62, CSR Addr 0x54031, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_B1; // Byte offset 0x63, CSR Addr 0x54031, Direction=In
+ // Must be programmed the same as MR11_A0
+ uint8_t MR16_B1; // Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1}
+ uint8_t MR17_B1; // Byte offset 0x65, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1}
+ uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+} __attribute__ ((packed)) PMU_SMB_LPDDR3_1D_t;
diff --git a/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_lpddr4.h b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_lpddr4.h
new file mode 100644
index 0000000..d194621
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_lpddr4.h
@@ -0,0 +1,557 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief LPDDR4_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_LPDDR4_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Quick Rd2D during 1D Training
+ // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] Disable Boot Clock
+ // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended)
+ // 0x0 = Use Boot Frequency Clock
+ //
+ // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[7-6] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.25*VDDQ, set this field to 0x20.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Lp4 specific options for training.
+ //
+ // Bit fields:
+ //
+ // Lp4Misc[0] Enable dfi_reset_n
+ //
+ // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training.
+ // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin.
+ //
+ // 0x1 = Enables dfi_reset_n to control memreset after training.
+ // PHY Internal registers control memreset during training only.
+ // To ensure that no glitches occur on BP_MEMRESET at the end of training,
+ // The MC must drive dfi_reset_n=1'b1 _prior to starting training_
+ //
+ // Lp4Misc[7-1] RFU, must be zero
+ uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D.
+ //
+ // Reserved0E[0:3]: bitTimeControl
+ // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point.
+ // 0 = 288 bits per point (legacy behavior)
+ // 1 = 576 bits per point
+ // 2 = 1.125 kilobits per point
+ // …
+ // 15 = 9 megabits per point
+ //
+ // Reserved0E[4]: Exhaustive2D
+ // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior)
+ // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point.
+ //
+ // Reserved0E[5:7]: RFU, must be 0
+ uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[11-10] = RFU, must be zero
+ // SequenceCtrl[12] = Run LPCA - CA Training
+ // SequenceCtrl[15-13] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ //
+ // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system.
+ uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired.
+ //
+ // 0x0 = Use MR<0:17>_A0 for rank 0 channel A
+ // Use MR<0:17>_B0 for rank 0 channel B
+ // Use MR<0:17>_A1 for rank 1 channel A
+ // Use MR<0:17>_B1 for rank 1 channel B
+ //
+ // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks
+ //
+ // It is recommended in most LPDDR4 system configurations to set this to 1.
+ //
+ // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels.
+ //
+ uint8_t Lp4Quickboot; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In
+ // Enable Quickboot.
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D stages: Rd2D, Wr2D
+ //
+ // Reserved1A[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1A[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR14
+ // 2 = limit to +/-4 %VDDQ from MR14
+ // …
+ // 15 = limit to +/-30% VDDQ from MR14
+ uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // CA training option bit field
+ // [0] CA VREF Training
+ // 1 = Enable CA VREF Training
+ // 0 = Disable CA VREF Training
+ // [1-7] RFU must be zero
+ uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // X8 mode configuration:
+ // 0x0 = x16 configuration for all devices
+ // 0xF = x8 configuration for all devices
+ // All other values are RFU
+ uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+
+
+
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Total number of DQ bits enabled in PHY Channel A
+ uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel A.
+ //
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0}
+ uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0}
+ uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0}
+ uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0}
+ uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0}
+ uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0}
+ uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0}
+ uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0}
+ uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0}
+ uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0}
+ uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0}
+ uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0}
+ uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1}
+ uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1}
+ uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1}
+ uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1}
+ uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1}
+ uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1}
+ uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1}
+ uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1}
+ uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1}
+ uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1}
+ uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1}
+ uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1}
+ uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In
+ // Terminating Rank for CA bus on Channel A
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A
+
+ uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A
+
+ uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A
+
+ uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A
+
+ uint8_t Reserved4F; // Byte offset 0x4f, CSR Addr 0x54027, Direction=N/A
+
+ uint8_t Reserved50; // Byte offset 0x50, CSR Addr 0x54028, Direction=N/A
+
+ uint8_t Reserved51; // Byte offset 0x51, CSR Addr 0x54028, Direction=N/A
+
+ uint8_t Reserved52; // Byte offset 0x52, CSR Addr 0x54029, Direction=N/A
+
+ uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A
+
+ uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A
+
+ uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A
+
+ uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A
+
+ uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In
+ // Total number of DQ bits enabled in PHY Channel B
+ uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel B.
+ //
+ // 0x0 = No chip selects are populated with DRAM
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs01 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0}
+ uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0}
+ uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0}
+ uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0}
+ uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0}
+ uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0}
+ uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0}
+ uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0}
+ uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0}
+ uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0}
+ uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0}
+ uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0}
+ uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1}
+ uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1}
+ uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1}
+ uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1}
+ uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1}
+ uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1}
+ uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1}
+ uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1}
+ uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1}
+ uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1}
+ uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1}
+ uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1}
+ uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In
+ // Terminating Rank for CA bus on Channel B
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A
+
+ uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A
+
+ uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A
+
+ uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A
+
+ uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A
+
+ uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A
+
+} __attribute__ ((packed)) PMU_SMB_LPDDR4_1D_t;
diff --git a/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_lpddr4_2d.h b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_lpddr4_2d.h
new file mode 100644
index 0000000..c6ab3d3
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/mnPmuSramMsgBlock_lpddr4_2d.h
@@ -0,0 +1,557 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief LPDDR4_2D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_LPDDR4_2D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Quick Rd2D during 1D Training
+ // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] Disable Boot Clock
+ // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended)
+ // 0x0 = Use Boot Frequency Clock
+ //
+ // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[7-6] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.25*VDDQ, set this field to 0x20.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Lp4 specific options for training.
+ //
+ // Bit fields:
+ //
+ // Lp4Misc[0] Enable dfi_reset_n
+ //
+ // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training.
+ // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin.
+ //
+ // 0x1 = Enables dfi_reset_n to control memreset after training.
+ // PHY Internal registers control memreset during training only.
+ // To ensure that no glitches occur on BP_MEMRESET at the end of training,
+ // The MC must drive dfi_reset_n=1'b1 _prior to starting training_
+ //
+ // Lp4Misc[7-1] RFU, must be zero
+ uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D.
+ //
+ // Reserved0E[0:3]: bitTimeControl
+ // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point.
+ // 0 = 288 bits per point (legacy behavior)
+ // 1 = 576 bits per point
+ // 2 = 1.125 kilobits per point
+ // …
+ // 15 = 9 megabits per point
+ //
+ // Reserved0E[4]: Exhaustive2D
+ // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior)
+ // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point.
+ //
+ // Reserved0E[5:7]: RFU, must be 0
+ uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = RFU, must be zero
+ // SequenceCtrl[2] = RFU, must be zero
+ // SequenceCtrl[3] = RFU, must be zero
+ // SequenceCtrl[4] = RFU, must be zero
+ // SequenceCtrl[5] = Run rd2D - 2d read dqs training
+ // SequenceCtrl[6] = Run wr2D - 2d write dq training
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = RFU, must be zero
+ // SequenceCtrl[9] = RFU, must be zero
+ // SequenceCtrl[11-10] = RFU, must be zero
+ // SequenceCtrl[12] = RFU, must be zero
+ // SequenceCtrl[15-13] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ //
+ // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system.
+ uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired.
+ //
+ // 0x0 = Use MR<0:17>_A0 for rank 0 channel A
+ // Use MR<0:17>_B0 for rank 0 channel B
+ // Use MR<0:17>_A1 for rank 1 channel A
+ // Use MR<0:17>_B1 for rank 1 channel B
+ //
+ // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks
+ //
+ // It is recommended in most LPDDR4 system configurations to set this to 1.
+ //
+ // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels.
+ //
+ uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A
+
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D stages: Rd2D, Wr2D
+ //
+ // Reserved1A[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1A[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR14
+ // 2 = limit to +/-4 %VDDQ from MR14
+ // …
+ // 15 = limit to +/-30% VDDQ from MR14
+ uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // CA training option bit field
+ // [0] CA VREF Setting
+ // 1 = Set MR12 from internal register
+ // 0 = Set MR12 from message block
+ // [1-7] RFU must be zero
+ uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // X8 mode configuration:
+ // 0x0 = x16 configuration for all devices
+ // 0xF = x8 configuration for all devices
+ // All other values are RFU
+ uint8_t RX2D_TrainOpt; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In
+ // Bit fields, if 2D read training enabled, then use these additional options:
+ // [0] DFE
+ // 1 = Run rx2D with DFE
+ // 0 = Run rx2D with DFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5-7] RFU, must be zero
+ //
+ uint8_t TX2D_TrainOpt; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Bit fields, if 2D write training is enabled, then use these additional options:
+ // [0] FFE
+ // 1 = Train tx2D with FFE
+ // 0 = Train tx2D with FFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5-7] RFU, must be zero
+ //
+ uint8_t Share2DVrefResult; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In
+ // Bitmap that designates the phy's vref source for every pstate
+ // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock.
+ // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training.
+ uint8_t Delay_Weight2D; // Byte offset 0x20, CSR Addr 0x54010, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye.
+ uint8_t Voltage_Weight2D; // Byte offset 0x21, CSR Addr 0x54010, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Total number of DQ bits enabled in PHY Channel A
+ uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel A.
+ //
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0}
+ uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0}
+ uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0}
+ uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0}
+ uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0}
+ uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0}
+ uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0}
+ uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0}
+ uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0}
+ uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0}
+ uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0}
+ uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0}
+ uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1}
+ uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1}
+ uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1}
+ uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1}
+ uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1}
+ uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1}
+ uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1}
+ uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1}
+ uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1}
+ uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1}
+ uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1}
+ uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1}
+ uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In
+ // Terminating Rank for CA bus on Channel A
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A
+
+ uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A
+
+ uint8_t TrainedVREFDQ_A0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // Trained DQ Vref setting for Ch A Rank 0
+ uint8_t TrainedVREFDQ_A1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // Trained DQ Vref setting for Ch A Rank 1
+ uint8_t RxClkDly_Margin_A0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_A0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_A0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_A0; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t RxClkDly_Margin_A1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_A1; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_A1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_A1; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In
+ // Total number of DQ bits enabled in PHY Channel B
+ uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel B.
+ //
+ // 0x0 = No chip selects are populated with DRAM
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs01 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0}
+ uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0}
+ uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0}
+ uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0}
+ uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0}
+ uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0}
+ uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0}
+ uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0}
+ uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0}
+ uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0}
+ uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0}
+ uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0}
+ uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1}
+ uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1}
+ uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1}
+ uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1}
+ uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1}
+ uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1}
+ uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1}
+ uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1}
+ uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1}
+ uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1}
+ uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1}
+ uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1}
+ uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In
+ // Terminating Rank for CA bus on Channel B
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t TrainedVREFDQ_B0; // Byte offset 0x80, CSR Addr 0x54040, Direction=Out
+ // Trained DQ Vref setting for Ch B Rank 0
+ uint8_t TrainedVREFDQ_B1; // Byte offset 0x81, CSR Addr 0x54040, Direction=Out
+ // Trained DQ Vref setting for Ch B Rank 1
+ uint8_t RxClkDly_Margin_B0; // Byte offset 0x82, CSR Addr 0x54041, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_B0; // Byte offset 0x83, CSR Addr 0x54041, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_B0; // Byte offset 0x84, CSR Addr 0x54042, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_B0; // Byte offset 0x85, CSR Addr 0x54042, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t RxClkDly_Margin_B1; // Byte offset 0x86, CSR Addr 0x54043, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_B1; // Byte offset 0x87, CSR Addr 0x54043, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_B1; // Byte offset 0x88, CSR Addr 0x54044, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_B1; // Byte offset 0x89, CSR Addr 0x54044, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+} __attribute__ ((packed)) PMU_SMB_LPDDR4_2D_t;
diff --git a/arch/arm/include/asm/arch-sc2/nand.h b/arch/arm/include/asm/arch-sc2/nand.h
new file mode 100644
index 0000000..91484ac
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/nand.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __NAND_H__
+#define __NAND_H__
+#include <asm/arch/cpu_config.h>
+
+#ifndef SD_EMMC_BASE_C
+#define SD_EMMC_BASE_C 0xd0074000
+#endif
+
+#define P_NAND_BASE (SD_EMMC_BASE_C | (1<<11))
+#define P_CLK_CNTL (volatile uint32_t *)(SD_EMMC_BASE_C)
+#define P_NAND_CMD (volatile uint32_t *)(P_NAND_BASE + 0x00)
+#define P_NAND_CFG (volatile uint32_t *)(P_NAND_BASE + 0x04)
+#define P_NAND_DADR (volatile uint32_t *)(P_NAND_BASE + 0x08)
+#define P_NAND_IADR (volatile uint32_t *)(P_NAND_BASE + 0x0c)
+#define P_NAND_BUF (volatile uint32_t *)(P_NAND_BASE + 0x10)
+#define P_NAND_INFO (volatile uint32_t *)(P_NAND_BASE + 0x14)
+#define P_NAND_DC (volatile uint32_t *)(P_NAND_BASE + 0x18)
+#define P_NAND_ADR (volatile uint32_t *)(P_NAND_BASE + 0x1c)
+#define P_NAND_DL (volatile uint32_t *)(P_NAND_BASE + 0x20)
+#define P_NAND_DH (volatile uint32_t *)(P_NAND_BASE + 0x24)
+#define P_NAND_CADR (volatile uint32_t *)(P_NAND_BASE + 0x28)
+#define P_NAND_SADR (volatile uint32_t *)(P_NAND_BASE + 0x2c)
+
+#define CEF (0xf<<10)
+#define CE0 (0xe<<10)
+#define CE1 (0xd<<10)
+#define CE2 (0xb<<10)
+#define CE3 (0x7<<10)
+
+#define IO4 ((0xe<<10)|(1<<18))
+#define IO5 ((0xd<<10)|(1<<18))
+#define IO6 ((0xb<<10)|(1<<18))
+
+#define CLE (0x5<<14)
+#define ALE (0x6<<14)
+#define DWR (0x4<<14)
+#define DRD (0x8<<14)
+#define IDLE (0xc<<14)
+#define RB (1<<20)
+
+#define M2N ((0<<17) | (2<<20) | (1<<19))
+#define N2M ((1<<17) | (2<<20) | (1<<19))
+#define STS ((3<<17) | (2<<20))
+#define ADL ((0<<16) | (3<<20))
+#define ADH ((1<<16) | (3<<20))
+#define AIL ((2<<16) | (3<<20))
+#define AIH ((3<<16) | (3<<20))
+#define ASL ((4<<16) | (3<<20))
+#define ASH ((5<<16) | (3<<20))
+#define SEED ((8<<16) | (3<<20))
+
+// NAND Flash Manufacturer ID Codes
+#define NAND_MFR_TOSHIBA 0x98
+#define NAND_MFR_SAMSUNG 0xec
+#define NAND_MFR_FUJITSU 0x04
+#define NAND_MFR_NATIONAL 0x8f
+#define NAND_MFR_RENESAS 0x07
+#define NAND_MFR_STMICRO 0x20
+#define NAND_MFR_HYNIX 0xad
+#define NAND_MFR_MICRON 0x2c
+#define NAND_MFR_AMD 0x01
+#define NAND_MFR_INTEL 0x89
+#define NAND_MFR_SANDISK 0x45
+#define NAND_MFR_USER 0x100
+#define NAND_MFR_EFUSE 0x101
+
+typedef struct nand_setup {
+ union {
+ uint32_t d32;
+ struct {
+ unsigned cmd:22;
+ unsigned large_page:1; // 22
+ unsigned no_rb:1; // 23 from efuse
+ unsigned a2:1; // 24
+ unsigned reserved25:1; // 25
+ unsigned page_list:1; // 26
+ unsigned sync_mode:2; // 27 from efuse
+ unsigned size:2; // 29 from efuse
+ unsigned active:1; // 31
+ } b;
+ } cfg;
+ uint16_t id;
+ uint16_t max; // id:0x100 user, max:0 disable.
+} nand_setup_t;
+
+typedef struct _nand_cmd{
+ unsigned char type;
+ unsigned char val;
+} nand_cmd_t;
+
+typedef struct _ext_info{
+ uint32_t read_info; //nand_read_info;
+ uint32_t new_type; //new_nand_type;
+ uint32_t page_per_blk; //pages_in_block;
+ uint32_t xlc; //slc=1, mlc=2, tlc=3.
+ uint32_t rsv1[5];
+} ext_info_t;
+
+typedef struct _nand_page0 {
+ nand_setup_t nand_setup; //8
+ unsigned char page_list[16]; //16
+ nand_cmd_t retry_usr[32]; //64 (32 cmd max I/F)
+ ext_info_t ext_info; //64
+} nand_page0_t; //384 bytes max.
+
+//#define NAND_PAGE0_BUF BL1_NAND_BUFF
+#define NAND_PAGE0_BUF (0x1800000)
+#define NAND_PAGE_LIST (NAND_PAGE0_BUF + sizeof(nand_setup_t))
+#define NAND_RETRY_USER (NAND_PAGE_LIST + 16)
+#define NAND_INFO_BUF (NAND_PAGE0_BUF + 512)
+#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1)
+//#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1)
+
+#define ERROR_MOD(mod,num) ((uint32_t)(((mod<<6)|num)))
+#define ERROR_NAND_TIMEOUT ERROR_MOD(2,1) //
+#define ERROR_NAND_ECC ERROR_MOD(2,2) //
+#define ERROR_NAND_MAGIC_WORD ERROR_MOD(2,3) //
+#define ERROR_NAND_INIT_READ ERROR_MOD(2,4) //
+#define ERROR_NAND_BLANK_PAGE ERROR_MOD(2,5) //
+#define ERROR_NAND_UNALIGN_SRC ERROR_MOD(2,6) //
+
+#define NAND_SECTOR_SIZE (512)
+#define NAND_MAX_PAGESIZE (0x4000) //16K
+#define SRC_ALIGN_SIZE (NAND_MAX_PAGESIZE)
+
+#define INFO_BYTE_PER_ECCPAGE (8)
+uint32_t nfio_init(void);
+uint32_t nf_read(uint32_t boot_device, uint32_t src, uint32_t des, uint32_t size);
+#endif /* __NAND_H__ */
+
diff --git a/arch/arm/include/asm/arch-sc2/oscring.h b/arch/arm/include/asm/arch-sc2/oscring.h
new file mode 100644
index 0000000..15e259e
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/oscring.h
@@ -0,0 +1,18 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __OSCRING_H__
+#define __OSCRING_H__
+
+#define OSCRING_CTL_REG0 SYSCTRL_OSC_RING_CTRL0
+#define OSCRING_CTL_DATA0 0x51555555 /*0:25*/
+#define OSCRING_CTL_REG1 SYSCTRL_OSC_RING_CTRL1
+#define OSCRING_CTL_DATA1 0x80000005 /*0:7*/
+
+#define RING_PWM_VCCK PWMIJ_PWM_B
+#define RING_PWM_EE PWMGH_PWM_B
+
+int ring_msr(int index);
+#endif
diff --git a/arch/arm/include/asm/arch-sc2/pinctrl_init.h b/arch/arm/include/asm/arch-sc2/pinctrl_init.h
new file mode 100644
index 0000000..cfbc42a
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/pinctrl_init.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _MESON_PINCTRL_INIT_H_
+#define _MESON_PINCTRL_INIT_H_
+
+#define PIN_CONTROLLER_NUM 2
+extern int pinctrl_devices_active(int pinctrl_num);
+
+#endif /* _MESON_PINCTRL_INIT_H_ */
diff --git a/arch/arm/include/asm/arch-sc2/pll.h b/arch/arm/include/asm/arch-sc2/pll.h
new file mode 100644
index 0000000..d89ab5e
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/pll.h
@@ -0,0 +1,167 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __PLL_H
+#define __PLL_H
+
+#define PLL_TEST_SYS_TOTAL 2
+#define PLL_TEST_HIFI_TOTAL 2
+#define PLL_TEST_GP0_TOTAL 2
+#define PLL_TEST_GP1_TOTAL 2
+#define PLL_TEST_HDMI_TOTAL 2
+
+typedef struct sys_pll_set_s {
+ unsigned int cpu_clk;
+ unsigned int pll_cntl;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+}sys_pll_set_t;
+
+typedef struct sys_pll_cfg_s {
+ sys_pll_set_t sys_pll[PLL_TEST_SYS_TOTAL];
+}sys_pll_cfg_t;
+
+typedef struct hdmi_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+}hdmi_pll_set_t;
+
+typedef struct hdmi_pll_cfg_s {
+ hdmi_pll_set_t hdmi_pll[PLL_TEST_HDMI_TOTAL];
+}hdmi_pll_cfg_t;
+
+typedef struct gpll_rate_table_s {
+ unsigned int rate;
+ unsigned int m;
+ unsigned int n;
+ unsigned int od;
+}gpll_rate_table_t;
+
+typedef struct hifipll_rate_table_s {
+ unsigned int rate;
+ unsigned int m;
+ unsigned int n;
+ unsigned int od;
+}hifipll_rate_table_t;
+
+typedef struct gp0_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+}gp0_pll_set_t;
+
+typedef struct gp0_pll_cfg_s {
+ gp0_pll_set_t gp0_pll[PLL_TEST_GP0_TOTAL];
+}gp0_pll_cfg_t;
+
+typedef struct gp1_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+}gp1_pll_set_t;
+
+typedef struct gp1_pll_cfg_s {
+ gp1_pll_set_t gp1_pll[PLL_TEST_GP1_TOTAL];
+}gp1_pll_cfg_t;
+
+typedef struct hifi_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+}hifi_pll_set_t;
+
+typedef struct hifi_pll_cfg_s {
+ hifi_pll_set_t hifi_pll[PLL_TEST_HIFI_TOTAL];
+}hifi_pll_cfg_t;
+
+typedef struct pcie_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+}pcie_pll_set_t;
+
+typedef struct ethphy_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+}ethphy_pll_set_t;
+
+typedef struct usbphy_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+ unsigned int pll_cntl7;
+}usbphy_pll_set_t;
+
+struct pciepll_rate_table {
+ u16 rate;
+ u16 m;
+ u16 n;
+ u16 od;
+ u16 od2;
+ u16 frac;
+};
+
+#define PLL_RATE(_r, _m, _n, _od) \
+ { \
+ .rate = (_r), \
+ .m = (_m), \
+ .n = (_n), \
+ .od = (_od), \
+ } \
+
+enum pll_enum {
+ PLL_SYS = 0,
+ PLL_FIX,
+ PLL_DDR,
+ PLL_HDMI,
+ PLL_GP0,
+ PLL_HIFI,
+ PLL_PCIE,
+ PLL_GP1,
+ PLL_USBPHY,
+ PLL_ENUM,
+
+};
+
+int pll_test(int argc, char * const argv[]);
+
+#endif /* __PLL_H */
diff --git a/arch/arm/include/asm/arch-sc2/pwr_ctrl.h b/arch/arm/include/asm/arch-sc2/pwr_ctrl.h
new file mode 100644
index 0000000..de3e1ed
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/pwr_ctrl.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#define PWR_ON 1
+#define PWR_OFF 0
+
+#define PM_DSP 0
+#define PM_DOS_HCODEC 1
+#define PM_DOS_HEVC 2
+#define PM_DOS_VDEC 3
+#define PM_DOS_WAVE 4
+#define PM_VPU_HDMI 5
+#define PM_USB_COMB 6
+#define PM_PCIE 7
+#define PM_GE2D 8
+#define PM_ETH 9
+#define PM_AUDIO 10
+
+unsigned long pwr_ctrl_psci_smc(unsigned int power_domain, bool power_control);
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-sc2/reboot.h b/arch/arm/include/asm/arch-sc2/reboot.h
new file mode 100644
index 0000000..e7fb8bd
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/reboot.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __REBOOT_H
+#define __REBOOT_H
+
+#include "soc_def.h"
+
+/*
+Reboot reason AND corresponding env setting:
+0: Cold boot cold_boot
+1: Normal boot normal
+2: Factory reset factory_reset
+3: Upgrade system update
+4: Fastboot fastboot
+5: Suspend suspend_off
+6: Hibernate hibernate
+7: Fastboot Bootloader bootloader
+8: Shutdown reboot shutdown_reboot
+9: RPMBP reboot rpmbp
+10: quiescent reboot quiescent reboot
+11 : rescueparty rollback in AB mode
+12: Kernel panic kernel_panic
+13: Watchdog reboot watchdog_reboot
+14: quiescent recovery reboot quiescent recovery
+15: reserved
+*/
+#define AMLOGIC_COLD_BOOT 0
+#define AMLOGIC_NORMAL_BOOT 1
+#define AMLOGIC_FACTORY_RESET_REBOOT 2
+#define AMLOGIC_UPDATE_REBOOT 3
+#define AMLOGIC_FASTBOOT_REBOOT 4
+#define AMLOGIC_SUSPEND_REBOOT 5
+#define AMLOGIC_HIBERNATE_REBOOT 6
+#define AMLOGIC_BOOTLOADER_REBOOT 7 /* fastboot bootloader */
+#define AMLOGIC_SHUTDOWN_REBOOT 8
+#define AMLOGIC_RPMBP_REBOOT 9
+#define AMLOGIC_QUIESCENT_REBOOT 10
+#define AMLOGIC_RESCUEPARTY_REBOOT 11
+#define AMLOGIC_KERNEL_PANIC 12
+#define AMLOGIC_WATCHDOG_REBOOT 13
+#define AMLOGIC_RECOVERY_QUIESCENT_REBOOT 14
+
+/*
+old version env
+0x01010101, normal
+0x02020202, factory_reset
+0x03030303, update
+0x09090909, usb_burning
+0x0b0b0b0b, suspend_off
+*/
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-sc2/register.h b/arch/arm/include/asm/arch-sc2/register.h
new file mode 100644
index 0000000..4d9db70
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/register.h
@@ -0,0 +1,28525 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifdef REGISTER_H
+#else
+#define REGISTER_H
+
+//
+// Reading file: ./REG_LIST_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_sec.vh
+//
+//`define DMC_SEC_REG_BASE 32'hfe037000
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe037000
+// -----------------------------------------------
+#define DMC_SEC_RANGE0_CTRL ((0x0000 << 2) + 0xfe037000)
+ //default : 32'hffff0000
+ //bit 31:16 | 0 | range0_eda | range 0 end address higher 16bits.
+ //bit 15:0 | 0 | range0_sta | range 0 start address higher 16bits.
+#define DMC_SEC_RANGE0_CTRL1 ((0x0001 << 2) + 0xfe037000)
+ //default : 32'h00000003
+ //bit 7:5 | 0 | range0_secrity_level | range0 secruity level for DMA and DEMUX only.
+ //bit 4 | 0 | range0_prot_en | range0 allow protect monitor function. 1: allowed. 0: not allowed.
+ //bit 3 | 0 | range0_local_des_en | range0 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES_EN to decide this region data describle enable or not.
+ //bit 2 | 0 | range0_lock | lock range 0 registers. write 1 to lock range 0 register. can't change anymore.
+ //bit 1 | 0 | range0_key_sel | range 0 data describle key selection. 1 : key1. 0 : key0.
+ //bit 0 | 0 | range0_en | range 0 enable bit. 1 : enable, 0 : disable.
+#define DMC_SEC_RANGE1_CTRL ((0x0002 << 2) + 0xfe037000)
+ //default : 32'hffffffff
+ //bit 31:16 | 0 | range1_eda | range 1 end address higher 16bits.
+ //bit 15:0 | 0 | range1_sta | range 1 start address higher 16bits.
+#define DMC_SEC_RANGE1_CTRL1 ((0x0003 << 2) + 0xfe037000)
+ //default : 0
+ //bit 7:5 | 0 | range1_secrity_level | range1 secruity level for DMA and DEMUX only.
+ //bit 4 | 0 | range1_prot_en | range1 allow protect monitor function. 1: allowed. 0: not allowed.
+ //bit 3 | 0 | range1_local_des_en | range1 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES_EN to decide this region data describle enable or not.
+ //bit 2 | 0 | range1_lock | lock range 1 registers. write 1 to lock range 1 register. can't change anymore.
+ //bit 1 | 0 | range1_key_sel | range 1 data describle key selection. 1 : key1. 1 : key0.
+ //bit 0 | 0 | range1_en | range 0 enable bit. 1 : enable, 0 : disable.
+#define DMC_SEC_RANGE2_CTRL ((0x0004 << 2) + 0xfe037000)
+ //default : 32'hffffffff
+ //bit 31:16 | 0 | range2_eda | range 2 end address higher 16bits.
+ //bit 15:0 | 0 | range2_sta | range 2 start address higher 16bits.
+#define DMC_SEC_RANGE2_CTRL1 ((0x0005 << 2) + 0xfe037000)
+ //default : 0
+ //bit 7:5 | 0 | range2_secrity_level | range2 secruity level for DMA and DEMUX only.
+ //bit 4 | 0 | range2_prot_en | range2 allow protect monitor function. 1: allowed. 0: not allowed.
+ //bit 3 | 0 | range2_local_des_en | range2 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES to decide this region data describle enable or not.
+ //bit 2 | 0 | range2_lock | lock range 2 registers. write 1 to lock range 2 register. can't change anymore.
+ //bit 1 | 0 | range2_key_sel | range 2 data describle key selection. 1 : key1. 1 : key0.
+ //bit 0 | 0 | range2_en | range 2 enable bit. 1 : enable, 0 : disable.
+#define DMC_SEC_RANGE3_CTRL ((0x0006 << 2) + 0xfe037000)
+ //default : 32'hffffffff
+ //bit 31:16 | 0 | range3_eda | range 3 end address higher 16bits.
+ //bit 15:0 | 0 | range3_sta | range 3 start address higher 16bits.
+#define DMC_SEC_RANGE3_CTRL1 ((0x0007 << 2) + 0xfe037000)
+ //default : 0
+ //bit 7:5 | 0 | range3_secrity_level | range3 secruity level for DMA and DEMUX only.
+ //bit 4 | 0 | range3_prot_en | range3 allow protect monitor function. 1: allowed. 0: not allowed.
+ //bit 3 | 0 | range3_local_des_en | range3 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES to decide this region data describle enable or not.
+ //bit 2 | 0 | range3_lock | lock range 3 registers. write 1 to lock range 3 related registers. can't change anymore.
+ //bit 1 | 0 | range3_key_sel | range 3 data describle key selection. 1 : key1. 1 : key0.
+ //bit 0 | 0 | range3_en | range 3 enable bit. 1 : enable, 0 : disable.
+#define DMC_SEC_RANGE4_CTRL ((0x0008 << 2) + 0xfe037000)
+ //default : 32'hffffffff
+ //bit 31:16 | 0 | range4_eda | range 4 end address higher 16bits.
+ //bit 15:0 | 0 | range4_sta | range 4 start address higher 16bits.
+#define DMC_SEC_RANGE4_CTRL1 ((0x0009 << 2) + 0xfe037000)
+ //default : 0
+ //bit 7:5 | 0 | range4_secrity_level | range4 secruity level for DMA and DEMUX only.
+ //bit 4 | 0 | range4_prot_en | range4 allow protect monitor function. 1: allowed. 0: not allowed.
+ //bit 3 | 0 | range4_local_des_en | range4 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES to decide this region data describle enable or not.
+ //bit 2 | 0 | range4_lock | lock range 4 registers. write 1 to lock range 4 related registers. can't change anymore.
+ //bit 1 | 0 | range4_key_sel | range 4 data describle key selection. 1 : key1. 1 : key0.
+ //bit 0 | 0 | range4_en | range 4 enable bit. 1 : enable, 0 : disable.
+#define DMC_SEC_RANGE5_CTRL ((0x000a << 2) + 0xfe037000)
+ //default : 32'hffffffff
+#define DMC_SEC_RANGE5_CTRL1 ((0x000b << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE6_CTRL ((0x000c << 2) + 0xfe037000)
+ //default : 32'hffffffff
+#define DMC_SEC_RANGE6_CTRL1 ((0x000d << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE7_CTRL ((0x000e << 2) + 0xfe037000)
+ //default : 32'hffffffff
+#define DMC_SEC_RANGE7_CTRL1 ((0x000f << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE8_CTRL ((0x0010 << 2) + 0xfe037000)
+ //default : 32'hffffffff
+#define DMC_SEC_RANGE8_CTRL1 ((0x0011 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE9_CTRL ((0x0012 << 2) + 0xfe037000)
+ //default : 32'hffffffff
+#define DMC_SEC_RANGE9_CTRL1 ((0x0013 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE10_CTRL ((0x0014 << 2) + 0xfe037000)
+ //default : 32'hffffffff
+#define DMC_SEC_RANGE10_CTRL1 ((0x0015 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE11_CTRL ((0x0016 << 2) + 0xfe037000)
+ //default : 32'hffffffff
+#define DMC_SEC_RANGE11_CTRL1 ((0x0017 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE12_CTRL ((0x0018 << 2) + 0xfe037000)
+ //default : 32'hffffffff
+#define DMC_SEC_RANGE12_CTRL1 ((0x0019 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE13_CTRL ((0x001a << 2) + 0xfe037000)
+ //default : 32'hffffffff
+#define DMC_SEC_RANGE13_CTRL1 ((0x001b << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE14_CTRL ((0x001c << 2) + 0xfe037000)
+ //default : 32'hffffffff
+#define DMC_SEC_RANGE14_CTRL1 ((0x001d << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE15_CTRL1 ((0x001f << 2) + 0xfe037000)
+ //default : 0
+ //bit 7:5 | 0 | range1_secrity_level | range1 secruity level for DMC and DEMUX only.
+ //bit 4 | 0 | range1_prot_en | range1 allow protect monitor function. 1: allowed. 0: not allowed.
+ //bit 3 | 0 | range1_local_des_en | range1 data describle enable. 1: enable. 0 : disable. this bit works together with GLOBAL_DES_EN to decide this region data describle enable or not.
+ //bit 2 | 0 | range1_lock | lock range 1 registers. write 1 to lock range 1 register. can't change anymore.
+ //bit 1 | 0 | range1_key_sel | range 1 data describle key selection. 1 : key1. 1 : key0.
+ //bit 0 | 0 | not used. range 15 is always enabled.
+//per range per sub ID access enable.
+//there's 128 of read id accessable control bits per range.
+// this 128bit are consist of {DMC_SEC_RANGEx_RID_CTRL3, DMC_SEC_RANGEx_RID_CTRL2, DMC_SEC_RANGEx_RID_CTRL1, DMC_SEC_RANGEx_RID_CTRL0}
+//there's 128 of write id accessable control bits per range.
+// this 128bit are consist of {DMC_SEC_RANGEx_WID_CTRL3, DMC_SEC_RANGEx_WID_CTRL2, DMC_SEC_RANGEx_WID_CTRL1, DMC_SEC_RANGEx_WID_CTRL0}
+//bit 127:112. HCODEC based 16 subids.
+//bit 111:96 VDEC based 16 subids.
+//bit 95:94 for RID control : VPU read axi port2 based vpu read port2 ARSEC. For WID control : not used.
+//bit 93:92 for RID control : VPU read axi port1 based vpu read port2 ARSEC. For WID control : VPU write axi port1 based on AWSEC.
+//bit 91:90 for RID control : VPU read axi port0 based vpu read port2 ARSEC. For WID control : VPU write axi port0 based on AWSEC.
+//bit 89:88 GE2D secruity control based ARSEC/AWSEC.
+//bit 87:80. Not used. Reserved for future.
+//bit 79. DSPB no-secure instruction access.
+//bit 78. DSPB secure instruction access.
+//bit 77. DSPB no-secure data access.
+//bit 76. DSPB secure data access.
+//bit 75. DSPA no-secure instruction access.
+//bit 74. DSPA secure instruction access.
+//bit 73. DSPA no-secure data access.
+//bit 72. DSPA secure data access.
+//bit 71~69. Not used. Reserved for future.
+//bit 68. DEMUX access enable bit. for write also need to check security level is matched.
+//bit 67:66. Wave. based instuction and data.
+//bit 65:64. NNA. ( not used in Sc2).
+//bit 63:56. HEVC backend based subid.
+//bit 55:40. Device based on subids.
+//bit 39:32. Audio based on subids
+//bit 31:24 DMA based on threadids. for write, also need to check security level is matched.
+//bit 22. USB access enable.
+//bit 21. DMC test access enable.
+//bit 20~12. HEVC frondend based subids.
+//bit 11:8. HDCP based subids.
+//bit 7. not used.
+//bit 6. PCIE access enable.
+//bit 5:4. GPU access enable based on GPU protection mode.
+//bit 3. CPU no-secure instruction access.
+//bit 2. CPU secure instruction access.
+//bit 1. CPU no-secure data access.
+//bit 0. CPU secure data access.
+#define DMC_SEC_RANGE0_RID_CTRL0 ((0x0020 << 2) + 0xfe037000)
+ //default : 0
+ //range_rd_sid_en[31:0];
+#define DMC_SEC_RANGE0_RID_CTRL1 ((0x0021 << 2) + 0xfe037000)
+ //default : 0
+ //range_rd_sid_en[63:32];
+#define DMC_SEC_RANGE0_RID_CTRL2 ((0x0022 << 2) + 0xfe037000)
+ //default : 0
+ //range_rd_sid_en[95:64];
+#define DMC_SEC_RANGE0_RID_CTRL3 ((0x0023 << 2) + 0xfe037000)
+ //default : 0
+ //range_rd_sid_en[127:96];
+#define DMC_SEC_RANGE0_RID_CTRL4 ((0x0024 << 2) + 0xfe037000)
+ //default : 0 not used in SC2
+#define DMC_SEC_RANGE1_RID_CTRL0 ((0x0026 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE1_RID_CTRL1 ((0x0027 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE1_RID_CTRL2 ((0x0028 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE1_RID_CTRL3 ((0x0029 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE1_RID_CTRL4 ((0x002a << 2) + 0xfe037000)
+ //default : 0 not used in SC2
+#define DMC_SEC_RANGE2_RID_CTRL0 ((0x002c << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE2_RID_CTRL1 ((0x002d << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE2_RID_CTRL2 ((0x002e << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE2_RID_CTRL3 ((0x002f << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE2_RID_CTRL4 ((0x0030 << 2) + 0xfe037000)
+ //default : 0 not used in SC2
+#define DMC_SEC_RANGE3_RID_CTRL0 ((0x0032 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE3_RID_CTRL1 ((0x0033 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE3_RID_CTRL2 ((0x0034 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE3_RID_CTRL3 ((0x0035 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE3_RID_CTRL4 ((0x0036 << 2) + 0xfe037000)
+ //default : 0 not used in SC2
+#define DMC_SEC_RANGE4_RID_CTRL0 ((0x0038 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE4_RID_CTRL1 ((0x0039 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE4_RID_CTRL2 ((0x003a << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE4_RID_CTRL3 ((0x003b << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE4_RID_CTRL4 ((0x003c << 2) + 0xfe037000)
+ //default : 0 not used in SC2
+#define DMC_SEC_RANGE5_RID_CTRL0 ((0x003e << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE5_RID_CTRL1 ((0x003f << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE5_RID_CTRL2 ((0x0040 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE5_RID_CTRL3 ((0x0041 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE5_RID_CTRL4 ((0x0042 << 2) + 0xfe037000)
+ //default : 0 not used in SC2
+#define DMC_SEC_RANGE6_RID_CTRL0 ((0x0044 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE6_RID_CTRL1 ((0x0045 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE6_RID_CTRL2 ((0x0046 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE6_RID_CTRL3 ((0x0047 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE6_RID_CTRL4 ((0x0048 << 2) + 0xfe037000)
+ //default : 0 not used in SC2
+#define DMC_SEC_RANGE7_RID_CTRL0 ((0x004a << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE7_RID_CTRL1 ((0x004b << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE7_RID_CTRL2 ((0x004c << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE7_RID_CTRL3 ((0x004d << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE7_RID_CTRL4 ((0x004e << 2) + 0xfe037000)
+ //default : 0 not used in SC2
+#define DMC_SEC_RANGE8_RID_CTRL0 ((0x0050 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE8_RID_CTRL1 ((0x0051 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE8_RID_CTRL2 ((0x0052 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE8_RID_CTRL3 ((0x0053 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE8_RID_CTRL4 ((0x0054 << 2) + 0xfe037000)
+ //default : 0 not used in SC2
+#define DMC_SEC_RANGE9_RID_CTRL0 ((0x0056 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE9_RID_CTRL1 ((0x0057 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE9_RID_CTRL2 ((0x0058 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE9_RID_CTRL3 ((0x0059 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE9_RID_CTRL4 ((0x005a << 2) + 0xfe037000)
+ //default : 0 not used in SC2
+#define DMC_SEC_RANGE10_RID_CTRL0 ((0x005c << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE10_RID_CTRL1 ((0x005d << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE10_RID_CTRL2 ((0x005e << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE10_RID_CTRL3 ((0x005f << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE10_RID_CTRL4 ((0x0060 << 2) + 0xfe037000)
+ //default : 0 not used in SC2
+#define DMC_SEC_RANGE11_RID_CTRL0 ((0x0062 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE11_RID_CTRL1 ((0x0063 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE11_RID_CTRL2 ((0x0064 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE11_RID_CTRL3 ((0x0065 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE11_RID_CTRL4 ((0x0066 << 2) + 0xfe037000)
+ //not used in SC2
+#define DMC_SEC_RANGE12_RID_CTRL0 ((0x0068 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE12_RID_CTRL1 ((0x0069 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE12_RID_CTRL2 ((0x006a << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE12_RID_CTRL3 ((0x006b << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE12_RID_CTRL4 ((0x006c << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+#define DMC_SEC_RANGE13_RID_CTRL0 ((0x006e << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE13_RID_CTRL1 ((0x006f << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE13_RID_CTRL2 ((0x0070 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE13_RID_CTRL3 ((0x0071 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE13_RID_CTRL4 ((0x0072 << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+#define DMC_SEC_RANGE14_RID_CTRL0 ((0x0074 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE14_RID_CTRL1 ((0x0075 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE14_RID_CTRL2 ((0x0076 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE14_RID_CTRL3 ((0x0077 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE14_RID_CTRL4 ((0x0078 << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+#define DMC_SEC_RANGE15_RID_CTRL0 ((0x007a << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE15_RID_CTRL1 ((0x007b << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE15_RID_CTRL2 ((0x007c << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE15_RID_CTRL3 ((0x007d << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE15_RID_CTRL4 ((0x007e << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+//per range per sub ID access enable.
+#define DMC_SEC_RANGE0_WID_CTRL0 ((0x0080 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE0_WID_CTRL1 ((0x0081 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE0_WID_CTRL2 ((0x0082 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE0_WID_CTRL3 ((0x0083 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE0_WID_CTRL4 ((0x0084 << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+#define DMC_SEC_RANGE1_WID_CTRL0 ((0x0086 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE1_WID_CTRL1 ((0x0087 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE1_WID_CTRL2 ((0x0088 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE1_WID_CTRL3 ((0x0089 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE1_WID_CTRL4 ((0x008a << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+#define DMC_SEC_RANGE2_WID_CTRL0 ((0x008c << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE2_WID_CTRL1 ((0x008d << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE2_WID_CTRL2 ((0x008e << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE2_WID_CTRL3 ((0x008f << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE2_WID_CTRL4 ((0x0090 << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+#define DMC_SEC_RANGE3_WID_CTRL0 ((0x0092 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE3_WID_CTRL1 ((0x0093 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE3_WID_CTRL2 ((0x0094 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE3_WID_CTRL3 ((0x0095 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE3_WID_CTRL4 ((0x0096 << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+#define DMC_SEC_RANGE4_WID_CTRL0 ((0x0098 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE4_WID_CTRL1 ((0x0099 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE4_WID_CTRL2 ((0x009a << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE4_WID_CTRL3 ((0x009b << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE4_WID_CTRL4 ((0x009c << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+#define DMC_SEC_RANGE5_WID_CTRL0 ((0x009e << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE5_WID_CTRL1 ((0x009f << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE5_WID_CTRL2 ((0x00a0 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE5_WID_CTRL3 ((0x00a1 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE5_WID_CTRL4 ((0x00a2 << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+#define DMC_SEC_RANGE6_WID_CTRL0 ((0x00a4 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE6_WID_CTRL1 ((0x00a5 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE6_WID_CTRL2 ((0x00a6 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE6_WID_CTRL3 ((0x00a7 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE6_WID_CTRL4 ((0x00a8 << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+#define DMC_SEC_RANGE7_WID_CTRL0 ((0x00aa << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE7_WID_CTRL1 ((0x00ab << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE7_WID_CTRL2 ((0x00ac << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE7_WID_CTRL3 ((0x00ad << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE7_WID_CTRL4 ((0x00ae << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+#define DMC_SEC_RANGE8_WID_CTRL0 ((0x00b0 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE8_WID_CTRL1 ((0x00b1 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE8_WID_CTRL2 ((0x00b2 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE8_WID_CTRL3 ((0x00b3 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE8_WID_CTRL4 ((0x00b4 << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+#define DMC_SEC_RANGE9_WID_CTRL0 ((0x00b6 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE9_WID_CTRL1 ((0x00b7 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE9_WID_CTRL2 ((0x00b8 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE9_WID_CTRL3 ((0x00b9 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE9_WID_CTRL4 ((0x00ba << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+#define DMC_SEC_RANGE10_WID_CTRL0 ((0x00bc << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE10_WID_CTRL1 ((0x00bd << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE10_WID_CTRL2 ((0x00be << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE10_WID_CTRL3 ((0x00bf << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE10_WID_CTRL4 ((0x00c0 << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+#define DMC_SEC_RANGE11_WID_CTRL0 ((0x00c2 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE11_WID_CTRL1 ((0x00c3 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE11_WID_CTRL2 ((0x00c4 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE11_WID_CTRL3 ((0x00c5 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE11_WID_CTRL4 ((0x00c6 << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+#define DMC_SEC_RANGE12_WID_CTRL0 ((0x00c8 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE12_WID_CTRL1 ((0x00c9 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE12_WID_CTRL2 ((0x00ca << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE12_WID_CTRL3 ((0x00cb << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE12_WID_CTRL4 ((0x00cc << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+#define DMC_SEC_RANGE13_WID_CTRL0 ((0x00ce << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE13_WID_CTRL1 ((0x00cf << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE13_WID_CTRL2 ((0x00d0 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE13_WID_CTRL3 ((0x00d1 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE13_WID_CTRL4 ((0x00d2 << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+#define DMC_SEC_RANGE14_WID_CTRL0 ((0x00d4 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE14_WID_CTRL1 ((0x00d5 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE14_WID_CTRL2 ((0x00d6 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE14_WID_CTRL3 ((0x00d7 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE14_WID_CTRL4 ((0x00d8 << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+#define DMC_SEC_RANGE15_WID_CTRL0 ((0x00da << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE15_WID_CTRL1 ((0x00db << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE15_WID_CTRL2 ((0x00dc << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE15_WID_CTRL3 ((0x00dd << 2) + 0xfe037000)
+ //default : 0
+#define DMC_SEC_RANGE15_WID_CTRL4 ((0x00de << 2) + 0xfe037000)
+ //not used in SC2
+ //default : 0
+#define DMC_DES_CTRL ((0x00e1 << 2) + 0xfe037000)
+ //default : 32'h00000002
+ //bit 31 : range15_des_en policy : 1 range15_des_en = range15_local_des_en && GLOBAL_DES_EN. 0 : range15_des_en = range15_local_des_en || GLOBAL_DES_EN.
+ //bit 30 : range14_des_en policy : 1 range14_des_en = range14_local_des_en && GLOBAL_DES_EN. 0 : range14_des_en = range14_local_des_en || GLOBAL_DES_EN.
+ //bit 29 : range13_des_en policy : 1 range13_des_en = range13_local_des_en && GLOBAL_DES_EN. 0 : range13_des_en = range13_local_des_en || GLOBAL_DES_EN.
+ //bit 28 : range12_des_en policy : 1 range12_des_en = range12_local_des_en && GLOBAL_DES_EN. 0 : range12_des_en = range12_local_des_en || GLOBAL_DES_EN.
+ //bit 27 : range11_des_en policy : 1 range11_des_en = range11_local_des_en && GLOBAL_DES_EN. 0 : range11_des_en = range11_local_des_en || GLOBAL_DES_EN.
+ //bit 26 : range10_des_en policy : 1 range11_des_en = range10_local_des_en && GLOBAL_DES_EN. 0 : range10_des_en = range10_local_des_en || GLOBAL_DES_EN.
+ //bit 25 : range9_des_en policy : 1 range9_des_en = range9_local_des_en && GLOBAL_DES_EN. 0 : range9_des_en = range9_local_des_en || GLOBAL_DES_EN.
+ //bit 24 : range8_des_en policy : 1 range8_des_en = range8_local_des_en && GLOBAL_DES_EN. 0 : range8_des_en = range8_local_des_en || GLOBAL_DES_EN.
+ //bit 23 : range7_des_en policy : 1 range7_des_en = range7_local_des_en && GLOBAL_DES_EN. 0 : range7_des_en = range7_local_des_en || GLOBAL_DES_EN.
+ //bit 22 : range6_des_en policy : 1 range6_des_en = range6_local_des_en && GLOBAL_DES_EN. 0 : range6_des_en = range6_local_des_en || GLOBAL_DES_EN.
+ //bit 21 : range5_des_en policy : 1 range5_des_en = range5_local_des_en && GLOBAL_DES_EN. 0 : range5_des_en = range5_local_des_en || GLOBAL_DES_EN.
+ //bit 20 : range4_des_en policy : 1 range4_des_en = range4_local_des_en && GLOBAL_DES_EN. 0 : range4_des_en = range4_local_des_en || GLOBAL_DES_EN.
+ //bit 19 : range3_des_en policy : 1 range3_des_en = range3_local_des_en && GLOBAL_DES_EN. 0 : range3_des_en = range3_local_des_en || GLOBAL_DES_EN.
+ //bit 18 : range2_des_en policy : 1 range2_des_en = range2_local_des_en && GLOBAL_DES_EN. 0 : range2_des_en = range2_local_des_en || GLOBAL_DES_EN.
+ //bit 17 : range1_des_en policy : 1 range1_des_en = range1_local_des_en && GLOBAL_DES_EN. 0 : range1_des_en = range1_local_des_en || GLOBAL_DES_EN.
+ //bit 16 : range0_des_en policy : 1 range0_des_en = range0_local_des_en && GLOBAL_DES_EN. 0 : range0_des_en = range0_local_des_en || GLOBAL_DES_EN.
+ //bit 1 | 0 | GLOBAL_DES_EN | 1: Global DES enable. 0 : global DES disable. default is 0.
+ //bit 0 | 0 | DES_lock | one time lock bit. after write 1 to this bit, DMC_DES_CTRL itself can't change but can be read, DMC_DES_PADDING DMC_DES_KEY*_REG* can't be write and read.
+//DES KEY registers and DES_PADDING can only be reset by pad reset. But it can be changed by software after watch dog reset.
+#define DMC_DES_KEY0_REG0 ((0x00e2 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_DES_KEY0_REG1 ((0x00e3 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_DES_KEY0_REG2 ((0x00e4 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_DES_KEY0_REG3 ((0x00e5 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_DES_KEY1_REG0 ((0x00e6 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_DES_KEY1_REG1 ((0x00e7 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_DES_KEY1_REG2 ((0x00e8 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_DES_KEY1_REG3 ((0x00e9 << 2) + 0xfe037000)
+ //default : 0
+#define DMC_DES_PADDING ((0x00e0 << 2) + 0xfe037000)
+ //default : 0
+ //bit 31:0 | 0 | des_pading | 32bits address padding used for DES dkey generation.
+//trap function: all the enable the port ID read access or enable PORT ID and subID read access must be in the predefine range. otherwire the read access would be blocked.
+// and an error will be generated.
+#define DMC_TRAP0_RANGE ((0x00ea << 2) + 0xfe037000)
+ //default : 0
+ // address trap0 range register.
+ //31:16. trap0 end address
+ //15:0 start0 address.
+#define DMC_TRAP0_CTRL ((0x00eb << 2) + 0xfe037000)
+ //default : 0
+ //bit 31 trap0 port ID 3 enable.
+ //bit 30 trap0 port ID 2 enable.
+ //bit 29 trap0 port ID 1 enable.
+ //bit 28 trap0 port ID 0 enable.
+ //bit 27 trap0 port ID 3 subid enable.
+ //bit 26 trap0 port ID 2 subid enable.
+ //bit 25 trap0 port ID 1 subid enable.
+ //bit 24 trap0 port ID 0 subid enable.
+ //bit 16:20. trap0 port ID 1 ID number.
+ //bit 14:11. trap0 port ID 1 subID ID number.
+ //bit 8:4. trap0 port ID 0 ID number.
+ //bit 3:0. trap0 port ID 0 subID ID number.
+#define DMC_TRAP0_CTRL2 ((0x00ec << 2) + 0xfe037000)
+ //default : 0
+ //bit 31:17. Not used.
+ //bit 16:20. trap0 port ID 3 ID number.
+ //bit 14:11. trap0 port ID 3 subID ID number.
+ //bit 8:4. trap0 port ID 2 ID number.
+ //bit 3:0. trap0 port ID 2 subID ID number.
+#define DMC_TRAP1_RANGE ((0x00ed << 2) + 0xfe037000)
+ //default : 0
+ //address trap range register.
+ //31:16. trap end address
+ //15:0 start address.
+#define DMC_TRAP1_CTRL ((0x00ee << 2) + 0xfe037000)
+ //default : 0
+ //bit 31 trap1 port ID 3 enable.
+ //bit 30 trap1 port ID 2 enable.
+ //bit 29 trap1 port ID 1 enable.
+ //bit 28 trap1 port ID 0 enable.
+ //bit 27 trap1 port ID 3 subid enable.
+ //bit 26 trap1 port ID 2 subid enable.
+ //bit 25 trap1 port ID 1 subid enable.
+ //bit 24 trap1 port ID 0 subid enable.
+ //bit 16:20. trap1 port ID 1 ID number.
+ //bit 14:11. trap1 port ID 1 subID ID number.
+ //bit 8:4. trap1 port ID 0 ID number.
+ //bit 3:0. trap1 port ID 0 subID ID number.
+#define DMC_TRAP1_CTRL2 ((0x00ef << 2) + 0xfe037000)
+ //default : 0
+ //bit 31:17. Not used.
+ //bit 16:20. trap1 port ID 1 ID number.
+ //bit 14:11. trap1 port ID 1 subID ID number.
+ //bit 8:4. trap1 port ID 0 ID number.
+ //bit 3:0. trap1 port ID 0 subID ID number.
+//FROM SC2, the APB bus provided Master ID through PUSER.
+ //bit 3. 1: lock bit to lock 3:0. if this bit = 1, the 3:0 are locked and cannot modified anymore.
+ //bit 7: lock bit. if this bit =1, bit[7:4] can't be modified.
+ //bit 5: PHY CPU IMEM disable. 1: IMEM output always = 0. 0: normal working mode.
+ //bit 4: PHY CPU DMEM disable. 1: DMEM output always = 0. 0: normal working mode.
+ //bit 3:0. APB secure control bits for DDR PHY register domain.
+//FROM SC2, the APB bus provided Master ID through PUSER signals.
+//there's total 8 master IDs could access DMC non-secure registers.
+//we assign 1 control bit for each APB Master and each DMC non-secure register domains
+//and we added one lock bits to lock this setting can't be modified any more.
+#define DDR_APB_SEC_CTRL0 ((0x00f0 << 2) + 0xfe037000)
+ // APB access control for dmc REQUEST control register access control register.
+ // default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL1 ((0x00f1 << 2) + 0xfe037000)
+ // APB access control for DMC DRAM timing parameter and DFI inteface registers.
+ //default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL2 ((0x00f2 << 2) + 0xfe037000)
+ // APB access control for DMC PLL clock frequency control regsiter.
+ //default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL3 ((0x00f3 << 2) + 0xfe037000)
+ // APB access control for DMC sticky control regsiter.
+ //default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL4 ((0x00f4 << 2) + 0xfe037000)
+ // APB access control for DMC test control regsiter.
+ //default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL5 ((0x00f5 << 2) + 0xfe037000)
+ // APB access control for DMC clk reset control regsiter.
+ //default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL6 ((0x00f6 << 2) + 0xfe037000)
+ // APB access control for DMC protection regsiter.
+ //default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL7 ((0x00f7 << 2) + 0xfe037000)
+ // APB access control for DMC normal regsiter.
+ //default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL8 ((0x00f8 << 2) + 0xfe037000)
+ // APB access control for DDR PHY group 0 regsiters.
+ //default : 0x0ff
+ //bit 10 PHY IMEM control 1: force PHY IMEM output 0. 0: normal working mode.
+ //bit 9 PHY DMEM control 1: force PHY DMEM output 0. 0: normal working mode.
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+#define DDR_APB_SEC_CTRL9 ((0x00f9 << 2) + 0xfe037000)
+ // APB access control for DMC canvas regsiter.
+ //default : 0x0ff
+ //bit 8 lock bit if this bit = 1, this register is locked and cannot modified anymore.
+ //bit 7:0. APB access enable for each APB user ID. one ID one bit. 1: enable. 0 disable.
+//registers to check the security protection and watch point error information.
+#define DMC_SEC_STATUS ((0x00fb << 2) + 0xfe037000)
+ //default : 0
+ //bit 31~2. not used.
+ //bit 6
+ //bit 5
+ //bit 4
+ //bit 3 1 : normal security register write violation.( APB bus WDATA not equre the register value when APB write). write 1 to clean this bit to 0.
+ //bit 2 sec_alert. 1 DMC secruity register alert function triggered. can't clean. only reset DMC can clear this bit.
+ //bit 1 write security violation.
+ //bit 0. read security violation.
+#define DMC_VIO_ADDR0 ((0x00fc << 2) + 0xfe037000)
+ //default : 0
+ //ddr0 write secure violation address.
+#define DMC_VIO_ADDR1 ((0x00fd << 2) + 0xfe037000)
+ //default : 0
+ //bit 31:24 . not used. always 0.
+ //24 ddr0 secure check violation.
+ //23 not used.
+ //22 not used.
+ //21 not used.
+ //20. not used.
+ //19 ddr0 write address overflow. write out of DDR size.
+ //18:16. ddr0 write violation AWPROT bits.
+ //15:0 ddr0_write violation ID.
+#define DMC_VIO_ADDR2 ((0x00fe << 2) + 0xfe037000)
+ //default : 0
+ //ddr0 read seure violation address
+#define DMC_VIO_ADDR3 ((0x00ff << 2) + 0xfe037000)
+ //default : 0
+ //24 ddr0 read secure check violation.
+ //23 not used.
+ //22 not used.
+ //21 ddr0 read trap1 violation
+ //20 ddr0 read trap0 violation
+ //19 ddr 0 read address overflow. write out of DDR size.
+ //18:16. ddr 0 read violation ARPROT bits.
+ //15:0 ddr 0 read violation ID.
+#define DMC_DDR_CTRL ((0x0100 << 2) + 0xfe037000)
+ //default : 0
+ //bit 27. 0 : cavnas use 64bytes boundary
+ // 1 : canvas use 32bytes boundary.
+ //bit 24:22 3'b000 : ddr3 mode.
+ //3'b001 : ddr4 mode.
+ //3'b010 : lpddr3 mode.
+ //3'b011 : lpddr4 mode.
+ //bit 21. rank1 enable bit. if 1, rank1 used the address map is as bit 5:3 defined.
+ //bit 20 DDR4 BG1 enable bit.
+ //bit 18: ddrphy_16b, DDR PHY DDR SDRAM data bits width. 1: 16bits. 0 : 32 bits.
+ //bit 16. ddr_16b, 1: only use 16bits data in a 32bits DDR PHY data interface. 0 : normal data interface.
+ //bit 7:4 : ddr1_size. DDR rank1 size control.
+ //4'b0000 : DDR rank 1 is 128Mbyte.
+ //4'b0001 : DDR rank 1 is 256Mbyte.
+ //4'b0010 : DDR rank 1 is 512Mbyte.
+ //4'b0011 : DDR rank 1 is 1Gbyte.
+ //4'b0100 : DDR rank 1 is 2Gbyte.
+ //4'b0101 : DDR rank 1 is 4Gbyte.
+ //4'b1000 : DDR rank 1 is 192Mbyte.
+ //4'b1001 : DDR rank 1 is 374Mbyte.
+ //4'b1010 : DDR rank 1 is 768Mbyte.
+ //4'b1011 : DDR rank 1 is 1.5Gbyte.
+ //4'b1100 : DDR rank 1 is 3Gbyte.
+ //others : reserved.
+ //bit 3:0 : ddr0_size. DDR rank0 size control.
+ //4'b0000 : DDR rank 0 is 128Mbyte.
+ //4'b0001 : DDR rank 0 is 256Mbyte.
+ //4'b0010 : DDR rank 0 is 512Mbyte.
+ //4'b0011 : DDR rank 0 is 1Gbyte.
+ //4'b0100 : DDR rank 0 is 2Gbyte.
+ //4'b0101 : DDR rank 0 is 4Gbyte.
+ //4'b1000 : DDR rank 1 is 192Mbyte.
+ //4'b1001 : DDR rank 1 is 374Mbyte.
+ //4'b1010 : DDR rank 1 is 768Mbyte.
+ //4'b1011 : DDR rank 1 is 1.5Gbyte.
+ //4'b1100 : DDR rank 1 is 3Gbyte.
+ //others : reserved.
+//DDR3/4 LPDDR3/4 SDRAM address to 32bits linear address address map:
+//DDR0_ADDRMAP is used to select RANK0 bank, row, col address selection.
+//DDR1_ADDRMAP is used to select RANK1 bank, row, col address selection.
+#define DDR0_ADDRMAP_0 ((0x0101 << 2) + 0xfe037000)
+ //default : 0
+ //29:25 ca8.
+ //24:20 ca7.
+ //19:15 ca6.
+ //14:10 ca5.
+ //9:5 ca4.
+ //4:0 ca3.
+#define DDR0_ADDRMAP_1 ((0x0102 << 2) + 0xfe037000)
+ //default : 0
+ //29:25 ra2.
+ //24:20 ra1.
+ //19:15 ra0.
+ //14:10 ca11.
+ //9:5 ca10.
+ //4:0 ca9.
+#define DDR0_ADDRMAP_2 ((0x0103 << 2) + 0xfe037000)
+ //default : 0
+ //29:25 ra8.
+ //24:20 ra7.
+ //19:15 ra6.
+ //14:10 ra5.
+ //9:5 ra4.
+ //4:0 ra3.
+#define DDR0_ADDRMAP_3 ((0x0104 << 2) + 0xfe037000)
+ //default : 0
+ //29:25 ra14.
+ //24:20 ra13.
+ //19:15 ra12.
+ //14:10 ra11.
+ //9:5 ra10.
+ //4:0 ra9.
+#define DDR0_ADDRMAP_4 ((0x0105 << 2) + 0xfe037000)
+ //default : 0
+ //29:25 ra16 for DDR4 SDRAM
+ //24:20 bg1 for DDR4 SDRAM.
+ //19:15 ba2. or bg0 for DDR4.
+ //14:10 ba1.
+ //9:5 ba0.
+ //4:0 ra15.
+#define DDR1_ADDRMAP_0 ((0x0106 << 2) + 0xfe037000)
+ //default : 0
+ //29:25 ca8.
+ //24:20 ca7.
+ //19:15 ca6.
+ //14:10 ca5.
+ //9:5 ca4.
+ //4:0 ca3.
+#define DDR1_ADDRMAP_1 ((0x0107 << 2) + 0xfe037000)
+ //default : 0
+ //29:25 ra2.
+ //24:20 ra1.
+ //19:15 ra0.
+ //14:10 ca11.
+ //9:5 ca10.
+ //4:0 ca9.
+#define DDR1_ADDRMAP_2 ((0x0108 << 2) + 0xfe037000)
+ //default : 0
+ //29:25 ra8.
+ //24:20 ra7.
+ //19:15 ra6.
+ //14:10 ra5.
+ //9:5 ra4.
+ //4:0 ra3.
+#define DDR1_ADDRMAP_3 ((0x0109 << 2) + 0xfe037000)
+ //default : 0
+ //29:25 ra14.
+ //24:20 ra13.
+ //19:15 ra12.
+ //14:10 ra11.
+ //9:5 ra10.
+ //4:0 ra9.
+#define DDR1_ADDRMAP_4 ((0x010a << 2) + 0xfe037000)
+ //default : 0
+ //29:25 ra16 for DDR4 SDRAM
+ //24:20 bg1 for DDR4 SDRAM.
+ //19:15 ba2 or bg0 for DDR4 SDRAM..
+ //14:10 ba1.
+ //9:5 ba0.
+ //4:0 ra15.
+#define DDR_MEM_PD_CTRL ((0x010b << 2) + 0xfe037000)
+ //default : 0
+ //bit 31:14 not used.
+ //2 bit control for each mem. 00 normal working. 11 power down.
+ //bit 13:12 wc_fifo
+ //bit 11:10 wd_mem
+ //bit 9:8 rd_mem
+ //bit 7:6 dfifo
+ //bit 5:4 cfifo
+ //bit 3:2 cav_ram
+ //bit 1:0 sticky ram
+#define DMC_AXI2DDR0 ((0x0120 << 2) + 0xfe037000)
+ //default : 0
+ //for AXI address first 256MB AXI ADDRESS[31:28] == 4'b0000.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR1 ((0x0121 << 2) + 0xfe037000)
+ //default : 0
+ //for AXI_ADDRESS[31:28] == 4'b0001.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR2 ((0x0122 << 2) + 0xfe037000)
+ //default : 0
+ //for AXI_ADDRESS[31:28] == 4'b0010.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR3 ((0x0123 << 2) + 0xfe037000)
+ //default : 0
+ //for AXI_ADDRESS[31:28] == 4'b0011.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR4 ((0x0124 << 2) + 0xfe037000)
+ //default : 0
+ //for AXI_ADDRESS[31:28] == 4'b0100.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR5 ((0x0125 << 2) + 0xfe037000)
+ //default : 0
+ //for AXI_ADDRESS[31:28] == 4'b0101.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR6 ((0x0126 << 2) + 0xfe037000)
+ //default : 0
+ //for AXI_ADDRESS[31:28] == 4'b0110.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR7 ((0x0127 << 2) + 0xfe037000)
+ //default : 0
+ //for AXI_ADDRESS[31:28] == 4'b0111.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR8 ((0x0128 << 2) + 0xfe037000)
+ //default : 0
+ //for AXI_ADDRESS[31:28] == 4'b1000.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDR9 ((0x0129 << 2) + 0xfe037000)
+ //default : 0
+ //for AXI_ADDRESS[31:28] == 4'b1001.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDRA ((0x012a << 2) + 0xfe037000)
+ //default : 0
+ //for AXI_ADDRESS[31:28] == 4'b1010.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDRB ((0x012b << 2) + 0xfe037000)
+ //default : 0
+ //for AXI_ADDRESS[31:28] == 4'b1011.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDRC ((0x012c << 2) + 0xfe037000)
+ //default : 0
+ //for AXI_ADDRESS[31:28] == 4'b1100.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDRD ((0x012d << 2) + 0xfe037000)
+ //default : 0
+ //for AXI_ADDRESS[31:28] == 4'b1101.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDRE ((0x012e << 2) + 0xfe037000)
+ //default : 0
+ //for AXI_ADDRESS[31:28] == 4'b1110.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_AXI2DDRF ((0x012f << 2) + 0xfe037000)
+ //default : 0
+ //for AXI_ADDRESS[31:28] == 4'b1111.
+ //bit 6 range_valid 1 : valid address 0 : not valid.
+ //bit 5 rank_sel, 0 : rank0. 1: rank1.
+ //bit 4 ddr_data_width, 0 : 32bits. 1: 16bits.
+ //bti 3:0. remap to one rank of DDR SDRAM linear address[31:28]
+#define DMC_DDR_CTRL1 ((0x0130 << 2) + 0xfe037000)
+ //default : 0
+ //bit 0. DMC_DDR_LOCK. 1: LOCK DMC_DDR_CTRL, DMC_DDR_CTRL1, DMC_AXI2DDRx, DDR0/1_ADDRMAP_x registers. those register can't modified any more.
+ // 0: all these regsiters can be read/write by secure APB access.
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_sec.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc_clk_freq/rtl/dmc_clk_freq.vh
+//
+//dmc pll and freqeucy domain control registers.
+//`define DMC_FREQ_REG_BASE 32'hfe036c00
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe036c00
+// -----------------------------------------------
+#define AM_DDR_PLL_CNTL0 ((0x0000 << 2) + 0xfe036c00)
+ //bit 31 : dpll_lock
+ //bit 29 : dpll_reset.
+ //bit 28 : dpll_en.
+ //bit 27:26 : dpll_clk_en
+ //bit 25 : dpll_inv_sel
+ //bit 20:19 : od1; if set ddr_freq_sel, it would replaced by ddr_pll_freq1_od[2:0]
+ //bit 18:16 : od; if set ddr_freq_sel, it would replaced by ddr_pll_freq1_od[5:4]
+ //bit 14:10 : dpll_ref_div_n
+ //bit 8:0 : dpll_int_num
+#define AM_DDR_PLL_CNTL1 ((0x0001 << 2) + 0xfe036c00)
+ //bit 18:0 : ddr_dpll_frac
+#define AM_DDR_PLL_CNTL2 ((0x0002 << 2) + 0xfe036c00)
+ //bit 22:20 : fref_sel
+ //bit 17:16 : os_ssc
+ //bit 15:12 : ssc_str_m
+ //bit 8 : ssc_en
+ //bit 7:4 : ssc_dep_sel
+ //bit 1:0 : dpll ss_mode.
+#define AM_DDR_PLL_CNTL3 ((0x0003 << 2) + 0xfe036c00)
+ //bit 31 : afc bypass
+ //bit 30 : afc clk sel
+ //bit 29 : code new
+ //bit 28 : dco_m_en
+ //bit 27 : dco_sdm_en
+ //bit 26 : div2
+ //bit 25 : div mode
+ //bit 24 : fast_lock mode
+ //bit 23 : fb_pre_div
+ //bit 22 : filter_mode
+ //bit 21 : fix_en
+ //bit 20 : freq_shift_en
+ //bit 19 : load
+ //bit 18 : load_en
+ //bit 17 : lock_f
+ //bit 16 : pulse_width_en
+ //bit 15 : sdmnc_en
+ //bit 14 : sdmnc_mode
+ //bit 13 : sdmnc_range
+ //bit 12 : tdc_en
+ //bit 11 : tdc_mode_sel
+ //bit 10 : wait_en
+#define AM_DDR_PLL_CNTL4 ((0x0004 << 2) + 0xfe036c00)
+ //bit 1:0 : pfd_gain
+ //bit 7:4 : filter_pvt1
+ //bit 11:8 : filter pvt2
+ //bit 13:12 : acq_gain
+ //bit 18:16 : lambda0
+ //bit 27:24 : rou
+ //bit 31:28 : alpha
+#define AM_DDR_PLL_CNTL5 ((0x0005 << 2) + 0xfe036c00)
+ //bit 15:0 : reve
+ //bit 21:16 : lm_s
+ //bit 27:24 : lm_w
+ //bit 30:28 : adj_vco_ldo
+#define AM_DDR_PLL_CNTL6 ((0x0006 << 2) + 0xfe036c00)
+ //bit 31:30 : afc_hold_t
+ //bit 29:28 : lkw_sel
+ //bit 27:26 : dco_sdm_clk_sel
+ //bit 25:24 : afc_in
+ //bit 23:22 : afc_nt
+ //bit 21:20 : vc_in
+ //bit 19:18 : lock_long
+ //bit 17:16 : freq_shift_v
+ //bit 15 : not used.
+ //bit 14:12 : data_sel
+ //bit 10:8 : sdmnc_ulms
+ //bit 6:0 : sdmnc_power
+#define AM_DDR_PLL_STS ((0x0007 << 2) + 0xfe036c00)
+ //bit 31 : DDR_PLL_LOCK
+ //bit 30 : lock_a
+ //bit 29 : afc_done
+ //bit 22:16 : sdmnc_monitor
+ //bit 9:0 : out_rsv
+#define DDR_CLK_CNTL ((0x0008 << 2) + 0xfe036c00)
+ //bit 31 ddr_pll_clk enable. enable the clock from DDR_PLL to clock generateion.
+ // whenever change the DDR_PLL frequency, disable the clock, after the DDR_PLL locked, then enable it again.
+ //bit 30. ddr_pll_prod_test_en. enable the clock to clock/32 which to clock frequency measurement and production test pin.
+ //bit 29. not used.
+ //bit 28. clock generation logic soft reset. 0 = reset.
+ //bit 27. phy_4xclk phase inverter..
+ //bit 26. pll_freq divide/2. 1: use pll div/2 clock as the n_clk. 0: use pll clock as n_clk. this setting is used for the synopsys DDR PHY PLL fast lock mode.
+ //bit 25. DDRPHY DfiClk/DfiCtlClk/DMC clock selection. 1: AM_PLL clk output /2. 0: directly output from AM_PLL .
+ //bit 24. enable AM_PLL CLK output /2 function. 1: enable. 0: disable. if try to use this clkoutput/2 function.
+ //bit 4. def_clk_sel 1: select reference clock as LPDDR4-PHY clock. 0: normal.
+ //bit 2. enable dmc_clk.
+ //bit 1. enable LPDDR4-PHY DfiClk.
+ //bit 0. enable LPDDR4-PHY DfiCtlClk.
+#define DDR_PHY_CTRL ((0x0009 << 2) + 0xfe036c00)
+ // LPDDR4 power on reset need to special combination of PwrOkIn and phy_reset_n.
+ // please check the PHY PUB data book for detail.
+ //bit 4. DDR PHY PwrOkIn pin.
+ //bit 1. DDR PHY APB soft reset_n.
+ //bit 0. phy_reset_n.
+#define AM_DDR_PLL_FREQ1_OD ((0x000c << 2) + 0xfe036c00)
+ //freqency set 1 PLL OD and OD1 setting. when change to freqency 1 will use this setting.
+//frequency set 0 use original DDR_PLL_CNTL0 setting.
+ //bit 8 currunt FREQ selection. it can forced to change to select which freqency to select, or it can auto changed by FREQ change hardware.
+ //bit 5:4 OD1.
+ //bit 2:0. OD.
+//
+// Closing file: ../mmc_lp4/dmc_clk_freq/rtl/dmc_clk_freq.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_reg.vh
+//
+//`define DMC_REG_BASE 32'hfe036000
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe036000
+// -----------------------------------------------
+//DMC REQ domain register. please check DMC_SEC_APB_CTRLx register for access details.
+#define DMC_REQ_CTRL ((0x0000 << 2) + 0xfe036000)
+ //bit 23. enable dmc request of ambus chan 7. Reserved for GE2D interface. Async interface.
+ //bit 22. enable dmc request of ambus chan 6. DOS HCODEC interface Sync interface.
+ //bit 21. enable dmc request of ambus chan 5. DOS VDEC interface Sync interface.
+ //bit 20. enable dmc request of ambus chan 4. VPU write interface 1 Sync interface.
+ //bit 19. enable dmc request of ambus chan 3. VPU write interface 0 Sync interface.
+ //bit 18. enable dmc request of ambus chan 2. VPU read interface 2. Sync interface.
+ //bit 17. enable dmc request of ambus chan 1. VPU read interface 1. Sync interface.
+ //bit 16. enable dmc request of ambus chan 0. VPU read interface 0. Sync interface.
+ //bit 9 enable dmc request of axibus chan 9. wave async interface.
+ //bit 8. enable dmc request of axibus chan 8 hevc_b async interface.
+ //bit 7. enable dmc request of axibus chan 7. DEVICE. Async interface.
+ //bit 6. enable dmc request of axibus chan 6. USB Async interface.
+ //bit 5. enable dmc request of axibus chan 5. reserved for dmc_test.
+ //bit 4. enable dmc request of axibus chan 4. hevc front Async interface.
+ //bit 3. enable dmc request of axibus chan 3. HDCP/HDMI Async interface.
+ //bit 2. enable dmc request of axibus chan 2. pcie async
+ //bit 1. enable dmc request of axibus chan 1. Mali . async interface.
+ //bit 0. enable dmc request of axibus chan 0. CPU/A53 async interface.
+//DMC CLK and RESET domain register. please check DMC_SEC_APB_CTRLx register for access details.
+#define DMC_SOFT_RST ((0x0001 << 2) + 0xfe036000)
+ //bit 31~24. reserved for future.
+ //bit 23:16 8 AMBUS input interface n_clk domain reset_n signal. 0 : reset. 1: normal working mode.
+ //bit 15:0. 16 AXI BUS input intefaces n_clk domain reset_n signal. 0: reset. 1: normal working mode. each bit for one interface.
+#define DMC_SOFT_RST1 ((0x0002 << 2) + 0xfe036000)
+ //To reset the Async interface, you need to disable the interface both clock domain, then reset both n_clk and m_clk domain
+ //bit 31~24 not used.
+ //bit 23.16 8 am bus interfaces master clock domain reset_n signal. 0 : reset : 1 normal working mode.
+ //bit 15:0. 16 AXI bus interfaces master clock domain reset_n signal. 0 : reset : 1 normal working mode.
+#define DMC_SOFT_RST2 ((0x0003 << 2) + 0xfe036000)
+ //bit 31~11. reserved for future.
+ //bit 10 DMC DFI cmd soft reset_n
+ //bit 9 DMC DFI MISC soft reset_n
+ //bit 8 DMC DFI data soft reset_n
+ //bit 7 DMC DFI dcu soft reset_n
+ //bit 6 DMC siu soft reset_n
+ //bit 5. DMC test soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 4. DMC low power control moudle soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 3. DMC QOS monitor module soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 2. DMC register modle soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 1. DMC canvas transfer module soft reset_n. 0 : reset. 1 : normal working mode.
+ //bit 0. DMC command buffers and command generation modules soft reset. 0 = reset. 1:
+#define DMC_RST_STS1 ((0x0004 << 2) + 0xfe036000)
+ //31~24. not used.
+ //23~0. Read only. the DMC_SOFT_RST1 signal in n_clk domain. the purpose of this register is when one of the 2 clocks is too slow or too fast, we can read this register to make sure another clock domain reset is done.
+#define DMC_VERSION ((0x0005 << 2) + 0xfe036000)
+ //read only 32'h000a0006. for TM2_REVB
+#define DMC_CLKG_CTRL0 ((0x0006 << 2) + 0xfe036000)
+ //bit 23:16. enable the 8 ambus interfaces both main and n_clk auto clock gating function. each 1 bit for one interface.
+ //bit 15:0. enable the 16 axi interfaces both main and n_clk auto clock gating function. each 1 bit for one interface.
+#define DMC_CLKG_CTRL1 ((0x0007 << 2) + 0xfe036000)
+ //bit 23:16. force to disable the 8 ambus interfaces both main and n_clk. each 1 bit for one interface.
+ //bit 15:0. force to disable the 16 axi interfaces both main and n_clk. each 1 bit for one interface.
+#define DMC_CLKG_CTRL2 ((0x0008 << 2) + 0xfe036000)
+ //bit 12 enalbe auto clock gating for awcmdfifo.
+ //bit 11 enalbe auto clock gating for arcmdfifo.
+ //bit 10 enable auto clock gating for dfi command generation
+ //bit 9 enable auto clock gating for dram cntroller
+ //bit 8 enable auto clock gating for dfi data path.
+ //bit 7. enalbe auto clock gating for write rsp generation.
+ //bit 6. enalbe auto clock gating for read rsp generation.
+ //bit 5. enalbe auto clock gating for ddr0 command filter.
+ //bit 4. enalbe auto clock gating for ddr0 write reorder buffer.
+ //bit 3. enalbe auto clock gating for ddr0 write data buffer.
+ //bit 2. enalbe auto clock gating for ddr0 read reorder buffer.
+ //bit 1. enalbe auto clock gating for read canvas.
+ //bit 0. enalbe auto clock gating for write canvas.
+#define DMC_CLKG_CTRL3 ((0x0009 << 2) + 0xfe036000)
+ //bit 12 force to disable the clock of awcmdfifo.
+ //bit 11 force to disable the clock of arcmdfifo.
+ //bit 10 force to disable the clock of dfi command generation
+ //bit 9 force to disable the clock of dram cntroller
+ //bit 8 force to disable the clock of dfi data path.
+ //bit 7. force to disalbe the clock of write rsp generation.
+ //bit 6. force to disalbe the clock of read rsp generation.
+ //bit 5. force to disalbe the clock of command filter.
+ //bit 4. force to disalbe the clock of write reorder buffer.
+ //bit 3. force to disalbe the clock of write data buffer.
+ //bit 2. force to disalbe the clock of read reorder buffer.
+ //bit 1. force to disalbe the clock of read canvas.
+ //bit 0. force to disalbe the clock of write canvas.
+// DMC CANVAS setting domain control regsiters.
+#define DC_CAV_LUT_DATAL ((0x0012 << 2) + 0xfe036000)
+ //low 32 bits of canvas data which need to be configured to canvas memory.
+#define DC_CAV_LUT_DATAH ((0x0013 << 2) + 0xfe036000)
+ //high 32bits of cavnas data which need to be configured to canvas memory.
+ //64bits CANVAS look up table
+ //bit 60:58 Endian control.
+ //3'b000: no endian change.
+ //3'b001:
+ //bit 57:56. Canvas block mode. 2 : 64x32, 1: 32x32; 0 : linear mode.
+ //bit 55: canvas Y direction wrap control. 1: wrap back in y. 0: not wrap back.
+ //bit 54: canvas X direction wrap control. 1: wrap back in X. 0: not wrap back.
+ //bit 53:41. canvas Hight.
+ //bit 40:29. canvas Width, unit: 8bytes. must in 32bytes boundary. that means last 2 bits must be 0.
+ //bit 28:0. cavnas start address. unit. 8 bytes. must be in 32bytes boundary. that means last 2bits must be 0.
+#define DC_CAV_LUT_ADDR ((0x0014 << 2) + 0xfe036000)
+ //bit 9:8. write 9:8 2'b10. the canvas data will saved in canvas memory with addres 7:0.
+ //bit 7:0. 256 canvas Look up table address.
+#define DC_CAV_LUT_RDATAL ((0x0015 << 2) + 0xfe036000)
+ // CBUS low 32bytes canvas read back data from LUT.
+#define DC_CAV_LUT_RDATAH ((0x0016 << 2) + 0xfe036000)
+ // Cbus high 32bytes canvas read back data from LUT.
+// there are total 256 canvas table, So we added a 256bits register to record the those canvas mode.
+// when we configure the canvas table and if the canvas mode is 32x32 blkmode, we'll mark this related bit.
+// we will use this bit to check the VPU canvas access. if it's in 32x32 blkmode, we need break the input in 32bytes boundary.
+// You can also use below register to read/write those bit.
+#define DC_CAV_BLK_CTRL0 ((0x0018 << 2) + 0xfe036000)
+ //canvas index 31:0 blkmode. 1 : 32x32. 0 : others.
+#define DC_CAV_BLK_CTRL1 ((0x0019 << 2) + 0xfe036000)
+ //canvas index 63:32 blkmode. 1 : 32x32. 0 : others.
+#define DC_CAV_BLK_CTRL2 ((0x001a << 2) + 0xfe036000)
+ //canvas index 95:64 blkmode. 1 : 32x32. 0 : others.
+#define DC_CAV_BLK_CTRL3 ((0x001b << 2) + 0xfe036000)
+ //canvas index 127:96 blkmode. 1 : 32x32. 0 : others.
+#define DC_CAV_BLK_CTRL4 ((0x001c << 2) + 0xfe036000)
+ //canvas index 159:128 blkmode. 1 : 32x32. 0 : others.
+#define DC_CAV_BLK_CTRL5 ((0x001d << 2) + 0xfe036000)
+ //canvas index 191:160 blkmode. 1 : 32x32. 0 : others.
+#define DC_CAV_BLK_CTRL6 ((0x001e << 2) + 0xfe036000)
+ //canvas index 223:192 blkmode. 1 : 32x32. 0 : others.
+#define DC_CAV_BLK_CTRL7 ((0x001f << 2) + 0xfe036000)
+ //canvas index 255:224 blkmode. 1 : 32x32. 0 : others.
+//dmc normal doman regsiters.
+#define DMC_MON_CTRL0 ((0x0020 << 2) + 0xfe036000)
+ //bit 31. qos_mon_en. write 1 to trigger the enable. polling this bit 0, means finished. or use interrupt to check finish.
+ //bit 30. qos_mon interrupt clear. clear the qos monitor result. read 1 = qos mon finish interrupt.
+ //bit 3. qos monitor 3 enable.
+ //bit 2. qos monitor 2 enable.
+ //bit 1. qos monitor 1 enable.
+ //bit 0. qos monitor 0 enable.
+#define DMC_MON_CTRL1 ((0x0021 << 2) + 0xfe036000)
+ //bit 23:0. qos monitor 0 channel select. 8 ambus port and 16 AXI port selection. 1 bit for one port.
+#define DMC_MON_CTRL2 ((0x0022 << 2) + 0xfe036000)
+ //bit 15:0. port select for the selected channel.
+#define DMC_MON_CTRL3 ((0x0023 << 2) + 0xfe036000)
+ //bit 23:0. qos monitor 0 channel select. 8 ambus port and 16 AXI port selection. 1 bit for one port.
+#define DMC_MON_CTRL4 ((0x0024 << 2) + 0xfe036000)
+ //bit 15:0. port select for the selected channel.
+#define DMC_MON_CTRL5 ((0x0025 << 2) + 0xfe036000)
+ //bit 23:0. qos monitor 0 channel select. 8 ambus port and 16 AXI port selection. 1 bit for one port.
+#define DMC_MON_CTRL6 ((0x0026 << 2) + 0xfe036000)
+ //bit 15:0. port select for the selected channel.
+#define DMC_MON_CTRL7 ((0x0027 << 2) + 0xfe036000)
+ //bit 23:0. qos monitor 0 channel select. 8 ambus port and 16 AXI port selection. 1 bit for one port.
+#define DMC_MON_CTRL8 ((0x0028 << 2) + 0xfe036000)
+ //bit 15:0. port select for the selected channel.
+#define DMC_MON_ALL_REQ_CNT ((0x0029 << 2) + 0xfe036000)
+ // at the test period, the whole MMC request time.
+#define DMC_MON_ALL_GRANT_CNT ((0x002a << 2) + 0xfe036000)
+ // at the test period, the whole MMC granted data cycles. 64bits unit.
+#define DMC_MON_ONE_GRANT_CNT ((0x002b << 2) + 0xfe036000)
+ // at the test period, the granted data cycles for the selected channel and ports.
+#define DMC_MON_SEC_GRANT_CNT ((0x002c << 2) + 0xfe036000)
+ // at the test period, the granted data cycles for the selected channel and ports.
+#define DMC_MON_THD_GRANT_CNT ((0x002d << 2) + 0xfe036000)
+ // at the test period, the granted data cycles for the selected channel and ports.
+#define DMC_MON_FOR_GRANT_CNT ((0x002e << 2) + 0xfe036000)
+ // at the test period, the granted data cycles for the selected channel and ports.
+#define DMC_MON_TIMER ((0x002f << 2) + 0xfe036000)
+ // timer for the monitor period.
+#define DMC_IRQ_STS ((0x003b << 2) + 0xfe036000)
+ //bit 31:3 Not used.
+ //bit 2 : QOS Monitor interrupt flag. 1: means there's QOS monitor interrup. write 1 to clean this interrupt.
+ //bit 1 : WRITE protection interrupt. 1: means there's write protection violation. need to write DMC_PROT_IRQ_CTRL bit 1to clean this bit.
+ //bit 0 : read protection interrupt. 1: means there's read protection violation. need to write DMC_PROT_IRQ_CTRL bit 0 to clean this bit.
+#define DMC_CHAN_STS ((0x003c << 2) + 0xfe036000)
+ //AXI0 is first CPU and Mali conbined channel from CCI-400 directly. The first 2Gbyte address will go through this channel.
+ //AXI10 is the second CPU, Mali channel combined with NNA from NIC-400. The upper 2Gbyte address will go through this channel.
+ // read only regsiter.
+ // the second mali and NNA channel IDLE.
+ // the second CPU channel IDLE.
+ // the first mali channel IDLE.
+ // the first CPU channel IDLE.
+ //bit 27 always 1
+ //bit 26 ddr0 write data buffer idle. 1 : idle 0: busy.
+ //bit 25 always 1.
+ //bit 24 ddr0 wbuf idle. 1 : idle 0: busy.
+ //bit 23:16 ambus channel idle. 1 : idle 0: busy.
+ //bit 15:0. axibus channel idle. 1 : idle 0: busy.
+#define DMC_2ARB_CTRL ((0x003d << 2) + 0xfe036000)
+ //32:24. Waiting limit to use the highest urgent level in the pipelines.
+ //22. 1: allow to increase 2 urgent levels if waiting time is doubled than inc_ugt_limit.
+ //21:12 inc_ugt_limit. if waiting time > inc_ugt_limit, increase the urgent level by one
+ //11:6. the final arbitration control from AXI bus(port channel 0~7).
+ //5:0. the final arbitration weight control for Ambus ( port channel 8~15).
+#define DMC_CMD_FILTER_CTRL1 ((0x0040 << 2) + 0xfe036000)
+ //not used.
+#define DMC_CMD_FILTER_CTRL2 ((0x0041 << 2) + 0xfe036000)
+ //31:24. keep the bank active if there's urgent level 3 read bank hit request.
+ //23:16. keep the bank active if there's urgent level 2 read bank hit request.
+ //15:8. keep the bank active if there's urgent level 1 read bank hit request.
+ //7:0. keep the bank active if there's urgent level 0 read bank hit request.
+#define DMC_CMD_FILTER_CTRL3 ((0x0042 << 2) + 0xfe036000)
+ //bit 31. force wbuf empty.
+ //bit 30:26 wbuf high level number
+ //bit 25:21 wbuf mid level number
+ //bit 20:16 wbuf low level number
+ //bit 14:10 rbuf high level number
+ //bit 9:5 rbuf middle level number
+ //bit 4:0 rbuf low level number
+#define DMC_CMD_FILTER_CTRL4 ((0x0043 << 2) + 0xfe036000)
+ //bit 29:25. tITW.long
+ //bit 24:20. tITW. short
+ //bit 19:12 tAP auto precharge the bank not used if idle that long time.
+ //bit 11:6 write to read accesses if there write hit request.
+ //bit 5:0 read to write accesses if there write hit request.
+#define DMC_CMD_FILTER_CTRL5 ((0x0044 << 2) + 0xfe036000)
+ //bit 31:24 Once ddr data bus switch to read, the maxmum read command number to give up the bus when there's write request pending for write buffer.
+ //bit 23:16 Once ddr data bus switch to write, the maxmum write command number to give up the bus when there's read request pending too long.
+ //bit 15:8. Once ddr data bus switch to read, the minimum read command number to transfer back to write stage if there's still pending read request.
+ //bit 7:0. Once ddr data bus switch to write, the minimum write command number to transfer back to read stage if there's still pending write request.
+#define DMC_CMD_FILTER_CTRL6 ((0x0045 << 2) + 0xfe036000)
+ //bit 31:24 write urgent 3 request pending hold num.
+ //bit 23:16 write urgent 2 request pending hold num.
+ //bit 15:8. write urgent 1 request pending hold num.
+ //bit 7:0. write urgent 0 request pending hold num.
+#define DMC_CMD_FILTER_CTRL7 ((0x0046 << 2) + 0xfe036000)
+ //bit 31:24. aw_req_pedning singal assertion after wbuf full.
+ //bit 23:16 aw_req_pending singal hold how long if wbuf not full.
+ //bit 15:8 write to read waiting cycles if there write hit request.
+ //bit 7:0 read to write waiting cycles if there write hit request.
+#define DMC_CMD_FILTER_CTRL8 ((0x0047 << 2) + 0xfe036000)
+ //bit 31:8 reserved.
+ //bit 7:0 rank limit to change to another rank.
+#define DMC_CMD_BUFFER_CTRL ((0x0048 << 2) + 0xfe036000)
+ //bit 31:26 total write buffer number. default 32.
+ //bit 25:20 total read buffer number. default 32.
+ //bit 19:8 reserved.
+ //bit 7:0 aw_pending_inc_num. incease write ugent level 1 when write command waiting to in write buffer that long.
+#define DMC_CMD_BUFFER_CTRL1 ((0x0049 << 2) + 0xfe036000)
+ //bit 29:24 read buffer number in non-urgent request.
+ //bit 23:16 read buffer bank miss watch dog threshold.
+ //bit 15:12 read buffer urgent level 3 counter inc weight.
+ //bit 11:8 read buffer urgent level 2 counter inc weight.
+ //bit 7:4 read buffer urgent level 1 counter inc weight.
+ //bit 3:0 read buffer urgent level 0 counter inc weight.
+#define DMC_AM0_CHAN_CTRL ((0x0060 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AM0_HOLD_CTRL ((0x0061 << 2) + 0xfe036000)
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AM0_CHAN_CTRL1 ((0x0062 << 2) + 0xfe036000)
+ //bit 31: side band signal used as block other request.
+ //bit 30 : side band urgent increase enable.
+ //bit 29 : side band urgent decrease urgent enable.
+ //bit 23:16 : when bit 31 enabled, block the ambus related bits read request.
+ //bit 15:0 : when bit 31 enabled, block the axi bus related bits read request.
+#define DMC_AM0_CHAN_CTRL2 ((0x0063 << 2) + 0xfe036000)
+ //bit 31:24 not used.
+ //bit 23:16 : when side band signal used as block other request, and side bank signal is high, block the ambus related bits write request.
+ //bit 15:0 : when side band signal used as block other request, and side bank signal is high, block the axi bus related bits write request.
+#define DMC_AM1_CHAN_CTRL ((0x0064 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AM1_HOLD_CTRL ((0x0065 << 2) + 0xfe036000)
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AM1_CHAN_CTRL1 ((0x0066 << 2) + 0xfe036000)
+ //bit 31: side band signal used as block other request.
+ //bit 30 : side band urgent increase enable.
+ //bit 29 : side band urgent decrease urgent enable.
+ //bit 23:16 : when bit 31 enabled, block the ambus related bits read request.
+ //bit 15:0 : when bit 31 enabled, block the axi bus related bits read request.
+#define DMC_AM1_CHAN_CTRL2 ((0x0067 << 2) + 0xfe036000)
+ //bit 31:24 not used.
+ //bit 23:16 : when side band signal used as block other request, and side bank signal is high, block the ambus related bits write request.
+ //bit 15:0 : when side band signal used as block other request, and side bank signal is high, block the axi bus related bits write request.
+#define DMC_AM2_CHAN_CTRL ((0x0068 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AM2_HOLD_CTRL ((0x0069 << 2) + 0xfe036000)
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AM2_CHAN_CTRL1 ((0x006a << 2) + 0xfe036000)
+ //bit 31: side band signal used as block other request.
+ //bit 30 : side band urgent increase enable.
+ //bit 29 : side band urgent decrease urgent enable.
+ //bit 23:16 : when bit 31 enabled, block the ambus related bits read request.
+ //bit 15:0 : when bit 31 enabled, block the axi bus related bits read request.
+#define DMC_AM2_CHAN_CTRL2 ((0x006b << 2) + 0xfe036000)
+ //bit 31:24 not used.
+ //bit 23:16 : when side band signal used as block other request, and side bank signal is high, block the ambus related bits write request.
+ //bit 15:0 : when side band signal used as block other request, and side bank signal is high, block the axi bus related bits write request.
+#define DMC_AM3_CHAN_CTRL ((0x006c << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AM3_HOLD_CTRL ((0x006d << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AM3_CHAN_CTRL1 ((0x006e << 2) + 0xfe036000)
+ //bit 31: side band signal used as block other request.
+ //bit 30 : side band urgent increase enable.
+ //bit 29 : side band urgent decrease urgent enable.
+ //bit 23:16 : when bit 31 enabled, block the ambus related bits read request.
+ //bit 15:0 : when bit 31 enabled, block the axi bus related bits read request.
+#define DMC_AM3_CHAN_CTRL2 ((0x006f << 2) + 0xfe036000)
+ //bit 31:24 not used.
+ //bit 23:16 : when side band signal used as block other request, and side bank signal is high, block the ambus related bits write request.
+ //bit 15:0 : when side band signal used as block other request, and side bank signal is high, block the axi bus related bits write request.
+#define DMC_AM4_CHAN_CTRL ((0x0070 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AM4_HOLD_CTRL ((0x0071 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AM4_CHAN_CTRL1 ((0x0072 << 2) + 0xfe036000)
+ //bit 31: side band signal used as block other request.
+ //bit 30 : side band urgent increase enable.
+ //bit 29 : side band urgent decrease urgent enable.
+ //bit 23:16 : when bit 31 enabled, block the ambus related bits read request.
+ //bit 15:0 : when bit 31 enabled, block the axi bus related bits read request.
+#define DMC_AM4_CHAN_CTRL2 ((0x0073 << 2) + 0xfe036000)
+ //bit 31:24 not used.
+ //bit 23:16 : when bit 31 enabled, block the ambus related bits write request.
+ //bit 15:0 : when bit 31 enabled, block the axi bus related bits write request.
+#define DMC_AM5_CHAN_CTRL ((0x0074 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AM5_HOLD_CTRL ((0x0075 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AM6_CHAN_CTRL ((0x0078 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AM6_HOLD_CTRL ((0x0079 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AM7_CHAN_CTRL ((0x007c << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AM7_HOLD_CTRL ((0x007d << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI0_CHAN_CTRL ((0x0080 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi0 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 arbiter weight
+#define DMC_AXI0_HOLD_CTRL ((0x0081 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI0_CHAN_CTRL1 ((0x0082 << 2) + 0xfe036000)
+ //bit 31:28. FIQ status
+ //bit 27:24. IRQ status.
+ //bit 22 use ACTIVE input as clock gating control.
+ //bit 21:20. chan0 QOS mode.
+ //bit 19:16. AXI0 QOS high limit.
+ //bit 15:12 AXI0 QOS mit limit.
+ //bit 11 ARM FIQ controlled super urgent enable.
+ //bit 10 ARM FIQ controlled urgent enable.
+ //bit 9. ARM IRQ controlled super urgent enable.
+ //bit 8. ARM IRQ controlled urgent enable.
+ //bit 7. IRQ/FIQ controll enable.
+ //bit 6:5. not used.
+ //bit 4. enable AXI0 auto urgent enable. When there's no other request, treat the AXI0 as super urgent request. other wise, use the bit3:0 to set the urgent.
+ //bit 3:2 A9 urgent if there's VIU request.
+ //bit 1:0 A9 urgent if there's request other than VIU
+#define DMC_AXI1_CHAN_CTRL ((0x0084 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI1_HOLD_CTRL ((0x0085 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI1_CHAN_CTRL1 ((0x0086 << 2) + 0xfe036000)
+ //bit 31:28. FIQ status
+ //bit 27:24. IRQ status.
+ //bit 21:20. Mali QOS mode.
+ //bit 19:16. mail QOS high limit.
+ //bit 15:12 mail QOS mit limit.
+ //bit 11 ARM FIQ controlled super urgent enable.
+ //bit 10 ARM FIQ controlled urgent enable.
+ //bit 9. ARM IRQ controlled super urgent enable.
+ //bit 8. ARM IRQ controlled urgent enable.
+ //bit 7. IRQ/FIQ controll enable.
+ //bit 6:0. not used.
+#define DMC_AXI2_CHAN_CTRL ((0x0088 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI2_HOLD_CTRL ((0x0089 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI3_CHAN_CTRL ((0x008c << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI3_HOLD_CTRL ((0x008d << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI4_CHAN_CTRL ((0x0090 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI4_HOLD_CTRL ((0x0091 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI5_CHAN_CTRL ((0x0094 << 2) + 0xfe036000)
+ //not used.
+#define DMC_AXI5_HOLD_CTRL ((0x0095 << 2) + 0xfe036000)
+ //not used.
+#define DMC_AXI6_CHAN_CTRL ((0x0098 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI6_HOLD_CTRL ((0x0099 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI7_CHAN_CTRL ((0x009c << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI7_HOLD_CTRL ((0x009d << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI8_CHAN_CTRL ((0x00a0 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI8_HOLD_CTRL ((0x00a1 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI9_CHAN_CTRL ((0x00a4 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI9_HOLD_CTRL ((0x00a5 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI10_CHAN_CTRL ((0x00a8 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI10_HOLD_CTRL ((0x00a9 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI10_CHAN_CTRL1 ((0x00aa << 2) + 0xfe036000)
+ //bit 11 Mali/NNA channel FIQ controlled super urgent enable.
+ //bit 10 Mali/NNA channel FIQ controlled urgent enable.
+ //bit 9. Mali/NNA channel IRQ controlled super urgent enable.
+ //bit 8. Mali/NNA channel IRQ controlled urgent enable.
+ //bit 7. IRQ/FIQ controll enable.
+ //bit 6:0. not used.
+#define DMC_AXI11_CHAN_CTRL ((0x00ac << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI11_HOLD_CTRL ((0x00ad << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI12_CHAN_CTRL ((0x00b0 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI12_HOLD_CTRL ((0x00b1 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+#define DMC_AXI13_CHAN_CTRL ((0x00b4 << 2) + 0xfe036000)
+ //bit 31 enable to incr 2 urgent levels if the pending cycles is doubled.
+ //bit 30 enable to incr 3 urgent levels.
+ //bit 29:20. write request pending cycle number to inc urgent level if not granted.
+ //bit 19. axi0 default urgent control : 1 use AWUGT/ARUGT pins in the port. 0 : use bit[15:14] of this register..
+ //bit 18. force this channel all request to be super urgent request.
+ //bit 17. force this channel all request to be urgent request.
+ //bit 16. force this channel all request to be non urgent request.
+ //bit 15:14 axi1 default urgent level.
+ //bit 13:4. read request pending cycle number to inc urgent level if not granted.
+ //bit 3:0 canvas arbiter arbiter weight
+#define DMC_AXI13_HOLD_CTRL ((0x00b5 << 2) + 0xfe036000)
+ //31:24 write hold num. max outstanding request number.
+ //23:16 write hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+ //15:8 read hold num. max outstanding request number.
+ //7:0 read hold release num. if the outstanding request == hold num, then hold this request unless the outstanding request number bellow the hold release number, then continue to request.
+//DMC protection function domain regsiter.
+#define DMC_PROT0_RANGE ((0x0030 << 2) + 0xfe036000)
+ //protection 0 address range. the range define is 64Kbyte boundary. current address [31:16] >= start address && current address [31:16] <= end address.
+ //bit 31:16 : range end address.
+ //bit 15:0 : range start address
+#define DMC_PROT0_CTRL ((0x0031 << 2) + 0xfe036000)
+ //bit 23:16. each bit to eanble one of the 8 ambus channal for the protection function.
+ //bit 15:0 each bit to enable one of the 15 channel input for the protection function.
+#define DMC_PROT0_CTRL1 ((0x0032 << 2) + 0xfe036000)
+ //bit 26. protection 0 read access protection enable.
+ //bit 25. protection 0 write access block function. if enabled, the access wouldn't write to the DDR SDRAM. if not enabled only generate a interrupt, but the access still wrote to DDR.
+ //bit 24. protection range 0 write access protection enable.
+#define DMC_PROT1_RANGE ((0x0033 << 2) + 0xfe036000)
+ //protection 1 address range. the range define is 64Kbyte boundary. current address [31:16] >= start address && current address [31:16] <= end address.
+ //bit 31:16 : range end address.
+ //bit 15:0 : range start address
+#define DMC_PROT1_CTRL ((0x0034 << 2) + 0xfe036000)
+ //bit 23:16. each bit to eanble one of the 8 ambus channal for the protection function.
+ //bit 15:0 each bit to enable one of the 15 channel input for the protection function.
+#define DMC_PROT1_CTRL1 ((0x0035 << 2) + 0xfe036000)
+ //bit 26. protection range 1 read access protection enable bit.
+ //bit 25. protection 1 write access block function. if enabled, the access wouldn't write to the DDR SDRAM. if not enabled only generate a interrupt, but the access still wrote to DDR.
+ //bit 24. protection range 1 write access protection enable bit.
+#define DMC_PROT_VIO_0 ((0x0036 << 2) + 0xfe036000)
+ //ddr0 write proection violation address.
+#define DMC_PROT_VIO_1 ((0x0037 << 2) + 0xfe036000)
+ //bit 31:21 . not used. always 0.
+ //20 ddr0 protection 1 vilation.
+ //19 ddr0 protection 0 vilation.
+ //18:16. ddr0 write violation AWPROT bits.
+ //15:0 ddr0_write violation ID.
+#define DMC_PROT_VIO_2 ((0x0038 << 2) + 0xfe036000)
+ //ddr0 read prot violation address
+#define DMC_PROT_VIO_3 ((0x0039 << 2) + 0xfe036000)
+ //bit 31:21 . not used. always 0.
+ //20 ddr0 read protection 1 violation.
+ //19 ddr0 read protection 0 violation.
+ //18:16. ddr0 read violation ARPROT bits.
+ //15:0 ddr0 read violation ID.
+#define DMC_PROT_IRQ_CTRL ((0x003a << 2) + 0xfe036000)
+ //bit 2 : protect function IRQ enable.
+ //bit 1 : write protection violation. write 1 to clean write protection vio registers.
+ //bit 0 : read protection violation. write 1 to clean read protection vio registers.
+// DMC test domain control registers.
+//`define DMC_TEST_REG_BASE 32'hfe037800
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe037800
+// -----------------------------------------------
+#define DMC_TEST_STA ((0x0000 << 2) + 0xfe037800)
+ //test start address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary.
+ // for sha mode, address must be in 64 bytes boundary. that mean the last 6 bits must be 0.
+#define DMC_TEST_EDA ((0x0001 << 2) + 0xfe037800)
+ //test end address. for non-sha mode, the last 5 bits would be ignored. the test address at 32bytes boundary.
+ // for sha mode, address must be in 64 bytes boundary. that mean the last 6bits must be 1.
+#define DMC_TEST_CTRL ((0x0002 << 2) + 0xfe037800)
+ //bit 31. enable test.
+ //bit 30. when enable test, enable the write to DDR function.
+ //bit 29. when enable test, enable the read from DDR function.
+ //bit 28. when enable test, enable the sha calculation function must be same as read enable but without write function.
+ //bit 27. enabe to compare data. when do the read enable to enable the error comparaion. suppose the read data should be same as the data in the write buffer.
+ //bit 26. 0: save sha result to test_sha_message registers. 1 : don't save.
+ //bit 25. address generation type. 0: continuous increase the address in the range of test start address and test end address.
+ // 1: test module would pick the random address from test start address and test end address.
+ //bit 24. done type. 0 : use the DMC_TEST_NUM register as the counter of test numbers.
+ // for write if the write command number == the DMC_TEST_NUM, the write is done.
+ // for read if the read command number == the DMC TEST_num, the read id done. for one read command can be repeated repeat number times.
+ // 1 : finshed at end address.
+ //bit 23. wdata type. 1 : the first write is {WD3, WD2,WD1,WD0}, then the latter is the previous data plus a pattern.( { + WD7, + WD6, + WD5, + WD4}).
+ // 0 : the WDATA is the data in write register.
+ //bit 23. 1 compare the sha result with the test sha message registers. 0 : dont compare the result.
+ //bit 22:20. read repeat times. for non-sha function, we can define multi times of the read. the test module would repeat the same adddress repeat times.
+ //bit 19. limit write. 0: no outstanding write request limitation.
+ // 1: limit the outstanding write commands to the number of bits [15:8]
+ //bit 18. limit read. 0. no outstanding read request limitation.
+ // 1. limit the read outstanding request to the number of bits[7:0].
+ //bit 17:16. sha mode for sha function enabled. 00 : not used. 01 : sha1. 2: sha2-256. 3: sha2_224. not used in GXL fixed to be Sha 2.
+ //bit 15:8. write outstanding commands limit.
+ //bit 7:0. read outstanding commands limit.
+#define DMC_TEST_NUM ((0x0003 << 2) + 0xfe037800)
+ // how many test command for the test if the DMC_TEST_CTRL bit 24 is 0.
+#define DMC_TEST_WDG ((0x0004 << 2) + 0xfe037800)
+ //31:16. write response watch dog.
+ //15:0. read response watch dog.
+#define DMC_TEST_COMP_MASK ((0x0005 << 2) + 0xfe037800)
+ //32bits for DMC TEST COMPARE bit enable.
+ //1 : to MASK this bit. 0: compare this bit.
+#define DMC_TEST_WSTRB0 ((0x0006 << 2) + 0xfe037800)
+ //MPC WR FIFO command DM bit write data
+ //bit 31:16 the second cycle.
+ //bit 15:0 the first cycle.
+#define DMC_TEST_WSTRB1 ((0x0007 << 2) + 0xfe037800)
+ //MPC WR FIFO command DM bit write data
+ //bit 31:16. the Forth cycle.
+ //bit 15:0. the third cycle.
+#define DMC_TEST_WD0 ((0x0010 << 2) + 0xfe037800)
+ // write data 0 for write command. also for read back data comparision.
+#define DMC_TEST_WD1 ((0x0011 << 2) + 0xfe037800)
+ // write data 1 for write command. also for read back data comparision.
+#define DMC_TEST_WD2 ((0x0012 << 2) + 0xfe037800)
+ // write data 2 for write command. also for read back data comparision.
+#define DMC_TEST_WD3 ((0x0013 << 2) + 0xfe037800)
+ // write data 3 for write command. also for read back data comparision.
+#define DMC_TEST_WD4 ((0x0014 << 2) + 0xfe037800)
+ // write data 4 for write command. also for read back data comparision.
+#define DMC_TEST_WD5 ((0x0015 << 2) + 0xfe037800)
+ // write data 5 for write command. also for read back data comparision.
+#define DMC_TEST_WD6 ((0x0016 << 2) + 0xfe037800)
+ // write data 6 for write command. also for read back data comparision.
+#define DMC_TEST_WD7 ((0x0017 << 2) + 0xfe037800)
+ // write data 7 for write command. also for read back data comparision.
+#define DMC_TEST_WD8 ((0x0018 << 2) + 0xfe037800)
+ // write data 8 for write command. also for read back data comparision.
+#define DMC_TEST_WD9 ((0x0019 << 2) + 0xfe037800)
+ // write data 9 for write command. also for read back data comparision.
+#define DMC_TEST_WD10 ((0x001a << 2) + 0xfe037800)
+ // write data 10 for write command. also for read back data comparision.
+#define DMC_TEST_WD11 ((0x001b << 2) + 0xfe037800)
+ // write data 11 for write command. also for read back data comparision.
+#define DMC_TEST_WD12 ((0x001c << 2) + 0xfe037800)
+ // write data 12 for write command. also for read back data comparision.
+#define DMC_TEST_WD13 ((0x001d << 2) + 0xfe037800)
+ // write data 13 for write command. also for read back data comparision.
+#define DMC_TEST_WD14 ((0x001e << 2) + 0xfe037800)
+ // write data 14 for write command. also for read back data comparision.
+#define DMC_TEST_WD15 ((0x001f << 2) + 0xfe037800)
+ // write data 15 for write command. also for read back data comparision.
+#define DMC_TEST_RD0 ((0x0020 << 2) + 0xfe037800)
+ // the read back data 0. if error happens, it would capture the first error data.
+#define DMC_TEST_RD1 ((0x0021 << 2) + 0xfe037800)
+ // the read back data 1. if error happens, it would capture the first error data.
+#define DMC_TEST_RD2 ((0x0022 << 2) + 0xfe037800)
+ // the read back data 2. if error happens, it would capture the first error data.
+#define DMC_TEST_RD3 ((0x0023 << 2) + 0xfe037800)
+ // the read back data 3. if error happens, it would capture the first error data.
+#define DMC_TEST_RD4 ((0x0024 << 2) + 0xfe037800)
+ // the read back data 4. if error happens, it would capture the first error data.
+#define DMC_TEST_RD5 ((0x0025 << 2) + 0xfe037800)
+ // the read back data 5. if error happens, it would capture the first error data.
+#define DMC_TEST_RD6 ((0x0026 << 2) + 0xfe037800)
+ // the read back data 6. if error happens, it would capture the first error data.
+#define DMC_TEST_RD7 ((0x0027 << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD8 ((0x0028 << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD9 ((0x0029 << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD10 ((0x002a << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD11 ((0x002b << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD12 ((0x002c << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD13 ((0x002d << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD14 ((0x002e << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_RD15 ((0x002f << 2) + 0xfe037800)
+ // the read back data 7. if error happens, it would capture the first error data.
+#define DMC_TEST_ERR_ADDR ((0x0040 << 2) + 0xfe037800)
+ //read only. it capature the first error address.
+#define DMC_TEST_ERR_CNT ((0x0041 << 2) + 0xfe037800)
+ //read only. how many data error happens in the whole test period.
+#define DMC_TEST_STS ((0x0042 << 2) + 0xfe037800)
+ //read only.
+ //bit 31, test done bit. write 1 to clean.
+ //bit 30, indicate address err
+ //bit 29~7. not used.
+ //bit 6. read data resp error(caused by security or rd latency).
+ //bit 5. test MRR/MPR rd latency error. write 1 clear
+ //bit 4, sha done. write 1 to clean.
+ //bit 3, write done. write 1 to clean.
+ //bit 2, read done. write 1 to clean
+ //bit 1, write watchdog triggered. write 1 to clean
+ //bit 0, read watchdog triggered. write 1 to clean.
+#define DMC_TEST_WRCMD_ADDR ((0x0043 << 2) + 0xfe037800)
+ //read only. the current write cmd address.
+#define DMC_TEST_RDCMD_ADDR ((0x0044 << 2) + 0xfe037800)
+ //read only. the current read command address.
+#define DMC_TEST_RDRSP_ADDR ((0x0045 << 2) + 0xfe037800)
+ //read only. the failed read response address(for error data )
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh
+//
+//DMC DDR dram timing and dfi timing domain control registers.
+//`define DMC_DRAM_REG_BASE 32'hfe036400
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe036400
+// -----------------------------------------------
+//there's 2 set of timing DDR timing parameter for 2 set of DDR freqency parameter.
+//when change frequency, the hardware would automatically select one of these two set of timing parameter
+//DMC_DRAM_* is for Frequency set 0.
+//DMC_NFQ_* is for Freqency set 1.
+#define DMC_DRAM_TMRD ((0x0000 << 2) + 0xfe036400)
+ //bit 4:0. tMRD. //MR command cycles, in DDR3/4. in LPDDR4, it should be value of tMRW
+#define DMC_DRAM_TRFC ((0x0001 << 2) + 0xfe036400)
+ //bit 9:0 tRFC
+#define DMC_DRAM_TRP ((0x0002 << 2) + 0xfe036400)
+ //bit 21:16. tRP for precharge all banks.
+ //bit 5:0. tRP for precharge one bank.
+#define DMC_DRAM_TRTW ((0x0003 << 2) + 0xfe036400)
+ //bit 5:0 tRTW
+ //In LPDDR4 . the total read command -> write command = RL +DQSCK_MAX + BL/2 - tODT_on + tWPRE +RD(tRPST) + tODT_on.
+ // tRTW = TDQSCK_MAX + tWPRE + tRD(tRPST) tODT_on + (delay margin)
+ //In DDR4 mode.
+#define DMC_DRAM_TCL ((0x0004 << 2) + 0xfe036400)
+ //bit 5:0 tCL/tRL. read latency.
+#define DMC_DRAM_TCWL ((0x0005 << 2) + 0xfe036400)
+ //bit 5:0. CWL: write latency.
+#define DMC_DRAM_TRAS ((0x0006 << 2) + 0xfe036400)
+ //bit 7:0. tRAS. minimum active to precharge time for same bank.
+#define DMC_DRAM_TRC ((0x0007 << 2) + 0xfe036400)
+ //bit 7:0. tRC. minimum active to active time for same bank.
+#define DMC_DRAM_TRCD ((0x0008 << 2) + 0xfe036400)
+ //bit 7:0 tRCD active to read/write timing for same bank.
+#define DMC_DRAM_TRRD ((0x0009 << 2) + 0xfe036400)
+ //bit 21:16. tRRD_l active bank A to active B in same band group for DDR4.
+ //bit 5:0. tRRD/tRRD_s active bank A to active bank b time.
+ //tRRD_s: active bank A to active bank b in different bank grousp for DDR4.
+#define DMC_DRAM_TFAW ((0x000a << 2) + 0xfe036400)
+ //bit 8:0 tFAW. four active command windows
+#define DMC_DRAM_TRTP ((0x000b << 2) + 0xfe036400)
+ //bit 5:0 tRTP.
+#define DMC_DRAM_TWR ((0x000c << 2) + 0xfe036400)
+ //bit 5:0 tWR.
+#define DMC_DRAM_TWTR ((0x000d << 2) + 0xfe036400)
+ //bit 5:0 tWTR.
+#define DMC_DRAM_TCCD ((0x000e << 2) + 0xfe036400)
+ //bit 19:16. tCCD/tCCD_l.
+ //bit 3:0 tCCD/tCCD_s read to read command time or write to write command time.
+#define DMC_DRAM_TEXSR ((0x000f << 2) + 0xfe036400)
+ //bit 12:0. tEXSR. EXIT SELF-REFRESH to read/write command.
+#define DMC_DRAM_TXS ((0x0010 << 2) + 0xfe036400)
+ //bit 9:0 tXS. EXIT SELF_REFRESH to other command time
+#define DMC_DRAM_TXP ((0x0011 << 2) + 0xfe036400)
+ //bit 3:0. tXP. EXIT power down to other command time
+#define DMC_DRAM_TXPDLL ((0x0012 << 2) + 0xfe036400)
+ //bit 12:0. tXPDLL, EXIT power down to read/write command time(need to relock PLL).
+#define DMC_DRAM_TZQCS ((0x0013 << 2) + 0xfe036400)
+ //bit 11:0. ZQCS command to other command time.
+#define DMC_DRAM_TCKSRE ((0x0014 << 2) + 0xfe036400)
+ //bit 4:0. enter self refresh to disable clock time.
+#define DMC_DRAM_TCKSRX ((0x0015 << 2) + 0xfe036400)
+ //bit 4:0. enable clock to exit self refresh time.
+#define DMC_DRAM_TCKE ((0x0016 << 2) + 0xfe036400)
+ //bit 4:0. CKE high or low minimum time.
+#define DMC_DRAM_TMOD ((0x0017 << 2) + 0xfe036400)
+ //bit 4:0 tMOD. MRR/MRW to other command time. in LPDDR4, still use this register but it called tMRD.
+#define DMC_DRAM_TDQS ((0x0018 << 2) + 0xfe036400)
+ //bit 31:28 reserved
+ //bit 27:24 tDQS. the delay for write after read in different rank.
+ //bit 23:20 reserved
+ //bit 19:16 tDQS. the delay for read after write in different rank.
+ //bit 15:12 reserved
+ //bit 11:8 tDQS. the delay for write after write in different rank.
+ //bit 7:4 reserved
+ //bit 3:0 tDQS. the delay for read after read in different rank.
+#define DMC_DRAM_TRSTL ((0x0019 << 2) + 0xfe036400)
+ //not used.
+#define DMC_DRAM_TZQLAT ((0x001a << 2) + 0xfe036400)
+ //bit 5:0 ZQ LATCH command to other comand timing in LPDDR4 mode.
+#define DMC_DRAM_TMRR ((0x001b << 2) + 0xfe036400)
+ //bit 7:0 tMRR not used in DMC.
+#define DMC_DRAM_TCKESR ((0x001c << 2) + 0xfe036400)
+ //bit 9:0 tCKESR. CKE low minimum pulse in self refresh mode.
+#define DMC_DRAM_TDPD ((0x001d << 2) + 0xfe036400)
+ //not support.
+#define DMC_DRAM_DFITCTRLDELAY ((0x001e << 2) + 0xfe036400)
+ //bit 3:0. DFI_t_ctrldealy
+#define DMC_DRAM_DFITPHYWRDATA ((0x001f << 2) + 0xfe036400)
+ //bit 5:0. dfi_t_phy_wrdata.
+#define DMC_DRAM_DFITPHYWRLAT ((0x0020 << 2) + 0xfe036400)
+ //bit 5:0. dfi_t_phy_wrlat. in DDR3/4/LPDDR3 mode: WL -5. in LPDDR4 mode: WL -5 + 2.
+#define DMC_DRAM_DFITRDDATAEN ((0x0021 << 2) + 0xfe036400)
+ //bit 5:0. dfi_t_rddata_en. in DDR3/4/LPDDR3 mode: RL -5. in LPDDR4 mode : RL -5 + 1.
+#define DMC_DRAM_DFITPHYRDLAT ((0x0022 << 2) + 0xfe036400)
+ //bit 5:0. dfi_t_rdlat.
+#define DMC_DRAM_DFITCTRLUPDMIN ((0x0023 << 2) + 0xfe036400)
+ //bit 7:0. CTRLUPD_MIN minimux clock cycle to maintain CTRLUPD_REQ.
+#define DMC_DRAM_DFITCTRLUPDMAX ((0x0024 << 2) + 0xfe036400)
+ //bit 7:0 CTRLUPD_MAX. maxmum clock cycle to maintain CTRLUPD_REQ if no CTRLUPD_ACK response.
+#define DMC_DRAM_DFITREFMSKI ((0x0026 << 2) + 0xfe036400)
+ //not used.
+#define DMC_DRAM_DFITCTRLUPDI ((0x0027 << 2) + 0xfe036400)
+ //not used.
+#define DMC_DRAM_DFITDRAMCLK ((0x0028 << 2) + 0xfe036400)
+//bit 17 dram clk1 enable.
+//bit 16 dram clk0 enable.
+//bit 15:8 DRAM CLK disable waiting time
+//bit 7:0 DRAM CLK enable enable timer
+#define DMC_DRAM_DFITLPRESP ((0x002a << 2) + 0xfe036400)
+ //bit 3:0. dfi_lp_ctrl_req response time. after dfi_lp_ctrl_req asserted, and after response time if there's still no dfi_lp_ack respone, then drop the dfi_lp_ctrl_req.
+#define DMC_DRAM_TCKECK ((0x002c << 2) + 0xfe036400)
+ //bit 4:0. tCKECK from CKE low to assert dfi_dram_clk_disable time. this time + dfi_t_ctrl_delay
+#define DMC_DRAM_TREFI ((0x002d << 2) + 0xfe036400)
+ //write this register will update the auto refresh related register to the auto refresh control logic.
+ //bit 31:24: tZQCI dmc send zqci period. unit is how much auto refresh period.
+ //bit 23:16 pvti dmc send dfi_ctrlupd_req period. unit is one auto refresh period.
+ //bit 15:8. tREFI.dmc send auto refresh command period. unit is 100ns.
+ //bit 7:0. t100ns period. unit is dmc clock cycles
+#define DMC_DRAM_TSR ((0x002e << 2) + 0xfe036400)
+ //bit 5:0 tSR. self resfresh enter to exit time.
+#define DMC_DRAM_TCCDMW ((0x002f << 2) + 0xfe036400)
+ //bit 5:0. 4*tCCD in LPDDR4 mask write.
+#define DMC_DRAM_TESCKE ((0x0030 << 2) + 0xfe036400)
+ //bit 5:0 tESCKE. enter self refresh to power time for LPDDR4.
+#define DMC_DRAM_TREFI_DDR3 ((0x0031 << 2) + 0xfe036400)
+ //7:0. DDR3 SDRAM tREFI single auto refresh time . the unit is t100ns.
+ //use this to check in 8*tREFI time, the DMC should not sent more than 16 auto REFRESH command.
+#define DMC_DRAM_TZQCAL ((0x0032 << 2) + 0xfe036400)
+ //11:0. ZQCAL for LPDDR4. ZQINIT/ZQoper for DDR3/4 ZQCL command.
+#define DMC_DRAM_T10US ((0x0033 << 2) + 0xfe036400)
+ //10us clock cycle number used for LP2 mode.
+#define DMC_DRAM_TMRRI ((0x0034 << 2) + 0xfe036400)
+//bit 7:0 tMRRI for MRR
+#define DMC_DRAM_TXS_FAST ((0x0035 << 2) + 0xfe036400)
+ //bit 9:0 DDR4 mode XS_FAST exit self_refrest to zqcl/zqcs/mrs command.
+#define DMC_DRAM_DFIODTCFG ((0x0036 << 2) + 0xfe036400)
+ //bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity.
+ //bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1.
+ //bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0.
+ //bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1.
+ //bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0.
+ //bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity.
+ //bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0.
+ //bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1.
+ //bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0.
+ //bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1.
+#define DMC_DRAM_DFIODTCFG1 ((0x0037 << 2) + 0xfe036400)
+ //bit 27:24 ODT length for BL8 read transfer.
+ //bit 19:16. ODT length for BL8 write transfer.
+ //bit 12:8. ODT latency for reads. suppose to be 0.
+ //bit 4:0. ODT latency for writes. suppose to be 0.
+#define DMC_DRAM_TWODTON ((0x0038 << 2) + 0xfe036400)
+ //bit 5:0 DRAM write access ODT on time.
+ // in DDR3/4 should be same as WL.
+ // in LPDDR4 = tODTLon + tODTon.min
+//timing paramter for frequency set 1.
+#define DMC_NFQ_TMRD ((0x0040 << 2) + 0xfe036400)
+#define DMC_NFQ_TRFC ((0x0041 << 2) + 0xfe036400)
+#define DMC_NFQ_TRP ((0x0042 << 2) + 0xfe036400)
+#define DMC_NFQ_TRTW ((0x0043 << 2) + 0xfe036400)
+#define DMC_NFQ_TCL ((0x0044 << 2) + 0xfe036400)
+#define DMC_NFQ_TCWL ((0x0045 << 2) + 0xfe036400)
+#define DMC_NFQ_TRAS ((0x0046 << 2) + 0xfe036400)
+#define DMC_NFQ_TRC ((0x0047 << 2) + 0xfe036400)
+#define DMC_NFQ_TRCD ((0x0048 << 2) + 0xfe036400)
+#define DMC_NFQ_TRRD ((0x0049 << 2) + 0xfe036400)
+#define DMC_NFQ_TFAW ((0x004a << 2) + 0xfe036400)
+#define DMC_NFQ_TRTP ((0x004b << 2) + 0xfe036400)
+#define DMC_NFQ_TWR ((0x004c << 2) + 0xfe036400)
+#define DMC_NFQ_TWTR ((0x004d << 2) + 0xfe036400)
+#define DMC_NFQ_TCCD ((0x004e << 2) + 0xfe036400)
+#define DMC_NFQ_TEXSR ((0x004f << 2) + 0xfe036400)
+#define DMC_NFQ_TXS ((0x0050 << 2) + 0xfe036400)
+#define DMC_NFQ_TXP ((0x0051 << 2) + 0xfe036400)
+#define DMC_NFQ_TXPDLL ((0x0052 << 2) + 0xfe036400)
+#define DMC_NFQ_TZQCS ((0x0053 << 2) + 0xfe036400)
+#define DMC_NFQ_TCKSRE ((0x0054 << 2) + 0xfe036400)
+#define DMC_NFQ_TCKSRX ((0x0055 << 2) + 0xfe036400)
+#define DMC_NFQ_TCKE ((0x0056 << 2) + 0xfe036400)
+#define DMC_NFQ_TMOD ((0x0057 << 2) + 0xfe036400)
+#define DMC_NFQ_TDQS ((0x0058 << 2) + 0xfe036400)
+#define DMC_NFQ_TRSTL ((0x0059 << 2) + 0xfe036400)
+#define DMC_NFQ_TZQLAT ((0x005a << 2) + 0xfe036400)
+#define DMC_NFQ_TMRR ((0x005b << 2) + 0xfe036400)
+#define DMC_NFQ_TCKESR ((0x005c << 2) + 0xfe036400)
+#define DMC_NFQ_TDPD ((0x005d << 2) + 0xfe036400)
+#define DMC_NFQ_DFITCTRLDELAY ((0x005e << 2) + 0xfe036400)
+#define DMC_NFQ_DFITPHYWRDATA ((0x005f << 2) + 0xfe036400)
+#define DMC_NFQ_DFITPHYWRLAT ((0x0060 << 2) + 0xfe036400)
+#define DMC_NFQ_DFITRDDATAEN ((0x0061 << 2) + 0xfe036400)
+#define DMC_NFQ_DFITPHYRDLAT ((0x0062 << 2) + 0xfe036400)
+#define DMC_NFQ_DFITCTRLUPDMIN ((0x0063 << 2) + 0xfe036400)
+#define DMC_NFQ_DFITCTRLUPDMAX ((0x0064 << 2) + 0xfe036400)
+#define DMC_NFQ_DFITREFMSKI ((0x0066 << 2) + 0xfe036400)
+#define DMC_NFQ_DFITCTRLUPDI ((0x0067 << 2) + 0xfe036400)
+#define DMC_NFQ_DFITDRAMCLK ((0x0068 << 2) + 0xfe036400)
+#define DMC_NFQ_DFITLPRESP ((0x006a << 2) + 0xfe036400)
+#define DMC_NFQ_TCKECK ((0x006c << 2) + 0xfe036400)
+#define DMC_NFQ_TREFI ((0x006d << 2) + 0xfe036400)
+#define DMC_NFQ_TSR ((0x006e << 2) + 0xfe036400)
+#define DMC_NFQ_TCCDMW ((0x006f << 2) + 0xfe036400)
+#define DMC_NFQ_TESCKE ((0x0070 << 2) + 0xfe036400)
+#define DMC_NFQ_TREFI_DDR3 ((0x0071 << 2) + 0xfe036400)
+#define DMC_NFQ_TZQCAL ((0x0072 << 2) + 0xfe036400)
+#define DMC_NFQ_T10US ((0x0073 << 2) + 0xfe036400)
+#define DMC_NFQ_TMRRI ((0x0074 << 2) + 0xfe036400)
+#define DMC_NFQ_TXS_FAST ((0x0075 << 2) + 0xfe036400)
+#define DMC_NFQ_DFIODTCFG ((0x0076 << 2) + 0xfe036400)
+#define DMC_NFQ_DFIODTCFG1 ((0x0077 << 2) + 0xfe036400)
+#define DMC_NFQ_TWODTON ((0x0078 << 2) + 0xfe036400)
+//end of second frequency timing parameter
+#define DMC_DRAM_DFITPHYUPDTYPE0 ((0x0080 << 2) + 0xfe036400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 0.
+#define DMC_DRAM_DFITPHYUPDTYPE1 ((0x0081 << 2) + 0xfe036400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 1.
+#define DMC_DRAM_DFITPHYUPDTYPE2 ((0x0082 << 2) + 0xfe036400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 2.
+#define DMC_DRAM_DFITPHYUPDTYPE3 ((0x0083 << 2) + 0xfe036400)
+ //dfi_phyupd_ack hold time for dfi_phyupd_req type = 3.
+#define DMC_DRAM_MCFG ((0x0086 << 2) + 0xfe036400)
+ //bit 17. in DDR3/4 mode, send ZQCL command after exit register triggered self refresh.
+ //bit 16. send refresh command after finish frequency change. 1 : enable. 0 : disable.
+ //bit 15. send refresh command after finish LPDDR4 retraining. 1 : enable. 0 : disable.
+ //bit 14. 1: cke init low. 0 : cke init high.
+ //bit 13 1: dbi write enable only for LPDDR4.
+ //bit 12. 1: dbi read inversion. 0: dbi read high inversion.
+ //bit 11. 1: dbi read enable. 0: dbi not enabled.
+ //bit 10 1: enable staggered chip select for 2 ranks DRAM.
+ //bit 9 1: enable send auto refresh command to DDR SDRAM when PCTL is in CFG/STOP state.
+ //bit 8 send auto refr cmd before enter register triggered self refresh
+ //bit 7 send auto refr cmd after exit regsiter triggered self refresh mode.
+ //bit 6 disable dram clock after enter register triggered self refresh.
+ //bit 5 send DFI_LP_REQ to PHY after enter register triggered elf refresh mode.
+ //bit 4 send DRAM to power down mode after enter self refresh. ONLY for LPDDR4.
+ //bit 3 send DFI_CTRLUPD_REQ after exit register triggered self refresh.
+ //bit 2 send ZQCS command after exit register triggered self refresh.
+ //bit 1 enable PHY triggered DFI_PHYUPD_REQ.
+ //bit 0 2T mode. always 1 in DDR3/4 mode.
+#define DMC_DRAM_DFI_CTRL ((0x0089 << 2) + 0xfe036400)
+ //bit 31 siu_dfi_lat err generation enable. 1: if dfi read latency violation, generate data error. 0 : disable.
+ //bit 15 siu_dfi1_lp_en
+ //bit 14 siu_dfi_lp_ack_and
+ //bit 13 siu_dfi_lp_ack_or
+ //bit 12 siu_dfi1_init_start_en
+ //bit 11 siu_dfi_init_com_and
+ //bit 10 siu_dfi_init_com_or
+ //bit 9 siu_dfi1_freq_en
+ //bit 8 siu_dfi1_dram_clk_dis_en
+ //bit 7 siu_dfi_phyupd_type_sel
+ //bit 6 siu_dfi1_phyupd_ack_en
+ //bit 5 siu_dfi_phyupd_req_and
+ //bit 4 siu_dfi_phyupd_req_or
+ //bit 3 siu_dfi_ctrlupd_ack_and
+ //bit 2 siu_dfi_ctrlupd_ack_or
+ //bit 1 siu_dfi1_ctrlupd_req_en
+ //bit 0 siu_dfi1_cmd_en
+#define DMC_DRAM_DFIINITCFG ((0x008a << 2) + 0xfe036400)
+ //bit 31. dfi_init_complete status. read only.
+ //bit 15:14. Frequency set 1 dfi_freq_ratio value.
+ //bit 12:8 Frequency set 1 dfi_freq value.
+ //bit 7:6 Frequency set 0 dfi_freq_ratio value.
+ //bit 5:1 Frequency set 0 dfi_freq value.
+ //bit 0. dfi_init_start value can be use manually config dfi_init_start signal.
+#define DMC_DRAM_ZQ_CTRL ((0x008b << 2) + 0xfe036400)
+ // only 1 bit can be enabled at same time.
+ //bit 2 send ZQCS command to RANK0 then send comand to RANK1.
+ //bit 1. send ZQCS command to both RANK0 and RANK1 together.
+ //bit 0. send ZQCS command to only rank0.
+#define DMC_DRAM_APD_CTRL ((0x008c << 2) + 0xfe036400)
+ //bit 19:16 DFI_LP_WAKEUP value in APD DFI_LP_REQ mode
+ //bit 12 1: exit power down slow mode(waiting PLL LOCK). 0 : fast mode.
+ //bit 11 enable DFI_LP_REQ when enter Auto power down mode.
+ //bit 10 disable DFI_clk_disable when enter auto power down mode.
+ //bit 9:0 0 disable auto power down mode.
+ //non zero value to enable auto power down when DMC is in idle state for this number of clock cycles.
+#define DMC_DRAM_ASR_CTRL ((0x008d << 2) + 0xfe036400)
+ //bit 30. in DDR3/4 mode, send ZQCL command after exit from auto self refresh mode.
+ //bit 29. enable PHY clock in LP2 mode. 1: enable. 0 : disable.
+ //bit 28. enable dmc wait 10us after LP2 mode exit if it's long time the PHY in LP2 mode..
+ //bit [27:24] DFI_LP_WAKEUP value in self refresh DFI_LP_REQ mode.
+ //bit 23 : send REFRESH command after exit from auto self refersh mode(ASR).
+ //bit 22 : send REFERSH command before enter to Auto self refresh mode(ASR).
+ //bit 21 : send ZQCS command after exit from Auto self refresh mode(ASR).
+ //bit 20 : send dfi_ctrl_upd after exit from ASR mode
+ //bit 19 : send power down command when enter ASR mode. //for LPDDR4 only.
+ //bit 18 : set the PHY enter LP2 mode after enter ASR mode.
+ //bit 17 : send DFI_LP_REQ after enter ASR mode.
+ //bit 16 : set DFI_CLK_DISABLE after enter ASR mode.
+ //bit 15:0. 0 disable auto ASR mode.
+ // Non-zero valule enable ASR mode. when DMC is in idle state for this number of clock cycles, the DMC will enter ASR mode.
+#define DMC_DRAM_REFR_CTRL ((0x0092 << 2) + 0xfe036400)
+ //bit 17:8 auto refresh request pending cnt if there's page hit request.
+ //bit 6 Disabled auto refresh command if over 16 auto refresh command sent in 2 TREFI_DDR3 period
+ //bit 5 enable dmc send ZQCS command .
+ //bit 4. enable dmc send DFI_CTRUPD_REQ.
+ //bit 3:1. how many refresh command send for one period. = this number + 1
+ //bit 0. enable dmc send auto refresh command.
+#define DMC_DRAM_FREQ_CTRL ((0x0093 << 2) + 0xfe036400)
+//bit 31 . wiret 1 to change freqency read 0: finished.
+//bit 30:9. not used.
+//bit 15. freq pre config_en. Before freq enter stop state let DMC configure DDR SDRAM.
+//bit 14. freq post config_en. After freq enter stop state let DMC configure DDR SDRAM.
+//bit 13. send zqcl after freq change in DDR3/4 mode.
+//bit 12. send zqcs after freq change. 1: enable. 0 not send.
+//bit 11. in AUTO MRW fucntion: the data format. 1: use USR_CMD format. 0: MRW format.
+//bit 10. AUTO MRW function: 1 use hardware auto MRW function. 0: don't do auto MRW.
+//bit 9. 1 : FREQ MRW done. let FREQ change machine continue.
+//bit 8 FREQ WAIT. 1 when freq change finishes, state machine stop at self refresh state in case there's something need to handle.
+ // 0 after freq change finishes the state machine go back to access state.
+//bit 7 when change PLL setting, disable dmc clock
+//bit 6 when change PLL setting, disable PHY DfiClk and DfiCtlClk.
+//bit 5 check vpu_sleep_en ==1 when do FREQ change. if vpu_sleep_en == 0, just wait.
+//bit 4 nxt frequency selection. 1 = freq1. 0 = freq0.
+//bit 3:1. not used.
+//bit 0. current frequency selection.
+#define DMC_DRAM_SCFG ((0x0094 << 2) + 0xfe036400)
+ // bit 2:0 only one bit can be high at same time.
+ // bit 2 1 : to ask PCTL enter ACCESS STATE. 0 : deassert the request.
+ // bit 1 1 : to ask PCTL enter SELF REFRESH STATE. 0 : deassert the request.
+ // bit 0 1 : to ask PCTL enter STOP/CONFIG STATE . 0 : deassert the request.
+#define DMC_DRAM_STAT ((0x0095 << 2) + 0xfe036400)
+ //bit 31 rd latency error. 1: means after dfiphytrdlat cycles, the read data still not back.
+ //bit 28:24 dram_sr_state
+ //bit 23:20 stop_st
+ //bit 19:15 sleep_st
+ //bit 14:12 ACCESS STATUS 0 : ACCESS is in normal working mode.
+ //1 : ACCESS sending precharege command.
+ //2 : ACCESS sending AUTO REFESH command.
+ //3 : ACCESS sending DIF_CTRLUPD_REQ command.
+ //4 : ACCESS sending ZQCS command to DDR DRAM(ZQCAL for LPDDR4).
+ //5 : ACCESS sending ZQLATCH command to LPDDR4 only.
+ //bit 11:8 APD STATUS: 0 : APD_IDLE
+ //1 : APD sending PRECHARGE command
+ //2 : APD sending CKE low command
+ //3 : APD sending DISABLE DRAM CLOCK command
+ //4 : APD sending DFI_LP_CTRL_REQ
+ //5 : APD in Auto Power down mode.
+ //6 : APD deassert DFI_LP_CTRL_REQ
+ //7 : APD sending enable DRAM CLOCK command
+ //8 : APD sending out CKE high command.
+ //bit 7:4: DRAM_STATUS: 0 : DRAM IDLE
+ //1 : DRAM_STOP/DRAM_CFG
+ //2 : DRAM_ACCESS
+ //3 : DRAM_SLEEP
+ //4 : DRAM APD(AUTO POWER DOWN).
+ //5 : IDLE -> STOP/CONFIG
+ //6 : STOP -> SLEEP
+ //7 : STOP -> ACCESS
+ //8 : ACCESS -> SLEEP.
+ //9 : ACCESS -> STOP
+ //A : ACCESS -> APD
+ //B : SLEEP -> STOP
+ //C : SLEEP -> ACCESS
+ //D : APD -> ACCESS
+ //bit 3 reserved.
+ //bit 2 1 : DRAM enter normal working state.
+ //bit 1 1 : DRAM enter sleep state. self refresh state.
+ //bit 0 1 : dram enter cfg state.
+#define DMC_DRAM_STAT1 ((0x0096 << 2) + 0xfe036400)
+ //bit 11:8 freq_st.
+ //4'h0 : IDLE
+ //4'h1 : FREQ_CHECK_VPU
+ //4'h2 : FREQ_WAITING_STOP
+ //4'h3 : FREQ_DRAM_CFG. waiting DMC/software to send special MRW/MPC command to configure DDR SDRAM either before Freq change or after freq change.
+ //4'h4 : FREQ_SELF_REFR_ST.
+ //4'h5 : FREQ_SET_DFI_FREQ.
+ //4'h6 : FREQ_DFI_INIT_START_HIGH.
+ //4'h7 : FREQ_CHANGE PLL_ST.
+ //4'h8 : FREQ_UPDATA REG.
+ //4'h9 : FREQ_DFI_INIT_START_LOW.
+ //4'ha : FREQ_WAITING_FINISH
+ //bit 7:5 train_st
+ //bit 4:0 dram_phy_st
+#define DMC_PHY_RETRAINING_CTRL ((0x0097 << 2) + 0xfe036400)
+ //bit 31 : phy_retraining enable.
+ //bit 30 : check vpu sleep_en.
+ //bit 25:24 : retraining dfi_freq[4:3], the [2:0] bit still use the dfi_freq bits to keep the frequency.
+ //bit 23:0: retraining period unit : 100ns.
+#define DMC_DFI_ERR_STAT ((0x0098 << 2) + 0xfe036400)
+ //LPDDR4 PHY DFI error infomation.
+ //bit 31:20. not used.
+ //bit 9. ddr0_dfi_error
+ //bit 8:5 ddr0_dfi_error_info.
+ //bit 4. ddr1_dfi_error.
+ //bit 3:0. ddr1_dfi_error_info.
+#define DMC_LP2_TIMER ((0x009a << 2) + 0xfe036400)
+//bit 15:0. timer setting to measure how long the chip is entered LP2 mode.
+//this timer is 40bits counter with DMC PCLK.
+//we use the high 16bits to compare this register. if the counter is large than this number, that means the PHY need addition 10us after wakeup the PHY and before exit self_refresh mode.
+#define DMC_DRAM_DFI_SWAP_0 ((0x00a0 << 2) + 0xfe036400)
+ //bit 5:0. dfi_act_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_1 ((0x00a1 << 2) + 0xfe036400)
+ //bit 5:0. dfi_ras_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_2 ((0x00a2 << 2) + 0xfe036400)
+ //bit 5:0. dfi_cas_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_3 ((0x00a3 << 2) + 0xfe036400)
+ //bit 5:0. dfi_we_n function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_4 ((0x00a4 << 2) + 0xfe036400)
+ //bit 5:0. dfi_bg0 function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_5 ((0x00a5 << 2) + 0xfe036400)
+ //bit 5:0. dfi_bg[1] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_6 ((0x00a6 << 2) + 0xfe036400)
+ //bit 5:0. dfi_ba[0] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_7 ((0x00a7 << 2) + 0xfe036400)
+ //bit 5:0. dfi_ba[1] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_8 ((0x00a8 << 2) + 0xfe036400)
+ //bit 5:0. dfi_ba[2] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_9 ((0x00a9 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[0] function select
+ // 6'h00 : the function itself.
+ // 6'h01 : act_n.
+ // 6'h02 : ras_n.
+ // 6'h03 : cas_n.
+ // 6'h04 : we_n.
+ // 6'h05 : bg[0].
+ // 6'h06 : bg[1].
+ // 6'h07 : ba[0].
+ // 6'h08 : ba[1].
+ // 6'h09 : ba[2].
+ // 6'h0a : a[0].
+ // 6'h0b : a[1].
+ // 6'h0c : a[2].
+ // 6'h0d : a[3].
+ // 6'h0e : a[4].
+ // 6'h0f : a[5].
+ // 6'h10 : a[6].
+ // 6'h11 : a[7].
+ // 6'h12 : a[8].
+ // 6'h13 : a[9].
+ // 6'h14 : a[10].
+ // 6'h15 : a[11].
+ // 6'h16 : a[12].
+ // 6'h17 : a[13].
+ // 6'h18 : a[14].
+ // 6'h19 : a[15].
+ // 6'h1a : a[16].
+ // 6'h1b : a[17].
+#define DMC_DRAM_DFI_SWAP_10 ((0x00aa << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[1] function select
+#define DMC_DRAM_DFI_SWAP_11 ((0x00ab << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[2] function select
+#define DMC_DRAM_DFI_SWAP_12 ((0x00ac << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[3] function select
+#define DMC_DRAM_DFI_SWAP_13 ((0x00ad << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[4] function select
+#define DMC_DRAM_DFI_SWAP_14 ((0x00ae << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[5] function select
+#define DMC_DRAM_DFI_SWAP_15 ((0x00af << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[6] function select
+#define DMC_DRAM_DFI_SWAP_16 ((0x00b0 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[7] function select
+#define DMC_DRAM_DFI_SWAP_17 ((0x00b1 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[8] function select
+#define DMC_DRAM_DFI_SWAP_18 ((0x00b2 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[9] function select
+#define DMC_DRAM_DFI_SWAP_19 ((0x00b3 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[10] function select
+#define DMC_DRAM_DFI_SWAP_20 ((0x00b4 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[11] function select
+#define DMC_DRAM_DFI_SWAP_21 ((0x00b5 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[12] function select
+#define DMC_DRAM_DFI_SWAP_22 ((0x00b6 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[13] function select
+#define DMC_DRAM_DFI_SWAP_23 ((0x00b7 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[14] function select
+#define DMC_DRAM_DFI_SWAP_24 ((0x00b8 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[15] function select
+#define DMC_DRAM_DFI_SWAP_25 ((0x00b9 << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[16] function select
+#define DMC_DRAM_DFI_SWAP_26 ((0x00ba << 2) + 0xfe036400)
+ //bit 5:0. dfi_a[17] function select
+#define DMC_DRAM_CMD ((0x00d0 << 2) + 0xfe036400)
+ //bit 31. cmd done. write 0 to clean.
+ //bit 30. data done. write 0 to clean.
+ //bit 5. user defined command.
+ //bit 4. LPDDR4 MPC write data command( MPC WR FIFO).
+ //bit 3. LPDDR4 MPC read data command (MPC RD Calibration and RD FIFO).
+ //bit 2. LPDDR4 MPC-1 command ( NOP, Start DQS interval ....)
+ //bit 1. mrr comand.
+ //bit 0. mrw command.
+#define DMC_DRAM_CMD_CODE ((0x00d1 << 2) + 0xfe036400)
+ //bit 31:28 user command case: = {act_n, ras_n, cas_n, we_n}
+ //bit 27:26. 128bits data cycles . 0: 1 clock cycles; 1: 2 clock cycles; 2: 3 clock cycles; 3:4 clock cycles.
+ // LPDDR4 4 clock cycles;
+ // DDR3/4/LPDDR3 : 2 clock cycles.
+ //bit 25 MRW/MRR/MPC command rank 1 select. 1: select. 0: not select.
+ //bit 24. MRW/MRR/MPC command rank 0 select. 1: select. 0: not select.
+ //bit 23:16 MR addr. DDR4 case : 18:16 ba[2:0]. 20:19 BG[1:0].
+ //bit 15:0 opcode.
+#define DMC_DRAM_CMD_TIME ((0x00d2 << 2) + 0xfe036400)
+//bit 31:16 PRE CMD timer. //delay how many cycle to start the command.
+//bit 15:0 POST CMD timer //delay how many cycle after the command execute.
+#define DMC_DRAM_WSTRB0 ((0x00d3 << 2) + 0xfe036400)
+#define DMC_DRAM_WSTRB1 ((0x00d4 << 2) + 0xfe036400)
+#define DMC_DRAM_RDBI0 ((0x00d5 << 2) + 0xfe036400)
+ //MPC RD FIFO command DBI read back data
+ //bit 31:16 the second cycle.
+ //bit 15:0 the first cycle.
+#define DMC_DRAM_RDBI1 ((0x00d6 << 2) + 0xfe036400)
+ //MPC RD FIFO command DBI read back data
+ //bit 31:16. the Forth cycle.
+ //bit 15:0. the third cycle.
+//WD0~16 and RD0~16 can be used as MRW command as Frequency change .
+//WD0~16 is for Freq1 DRAM MR setting, it would send to DRAM right before FREQ0-> FREQ1
+//RD0_16 is for Freq0 DRAM MR setting. it would send to DRAM right before FREQ1-> FREQ0.
+//each register can be one MRW command. So total 16 MRW command can be sent to DRAM.
+//The register formats:
+//bit 31. MRW/USER comand enable. 1: enabled command. 0 not enabled.
+//bit 30. last MRW/USER command. if this bit =1, After send this command, the DRAM controller will contine frequency next stage.
+//bit 29:26. USER COMMAND parameter: in DDR3/DDR4. {act_n, ras_n, cas_n, we_n} value for user command
+ //in LPDDR4. bit 16: 1 4 cycles command. 0 2 cycles command.
+//bit 25 MRW/USER command rank 1 select. 1: select. 0: not select.
+//bit 24. MRW/USER command rank 0 select. 1: select. 0: not select.
+//bit 23:0. USER command.
+ //DDR3: 18:16 bank address. 15:0: address.
+ //DDR4: 20:19 bank group address. 18:16: bank address. 15:0 address.
+ //LPDDR3: 9:0. rising edge address. 19:10. falling edge address.
+ //LPDDR4. 5:0, first edge address, 11:6 second edge address, 17:12: third edge address. 23:18, forth edge address.
+ //MRW command format:
+ //bit 23:16 MR addr. DDR4 case : 18:16 ba[2:0]. 20:19 BG[1:0].
+ //bit 15:0 opcode.
+#define DMC_DRAM_WD0 ((0x00e0 << 2) + 0xfe036400)
+#define DMC_DRAM_WD1 ((0x00e1 << 2) + 0xfe036400)
+#define DMC_DRAM_WD2 ((0x00e2 << 2) + 0xfe036400)
+#define DMC_DRAM_WD3 ((0x00e3 << 2) + 0xfe036400)
+#define DMC_DRAM_WD4 ((0x00e4 << 2) + 0xfe036400)
+#define DMC_DRAM_WD5 ((0x00e5 << 2) + 0xfe036400)
+#define DMC_DRAM_WD6 ((0x00e6 << 2) + 0xfe036400)
+#define DMC_DRAM_WD7 ((0x00e7 << 2) + 0xfe036400)
+#define DMC_DRAM_WD8 ((0x00e8 << 2) + 0xfe036400)
+#define DMC_DRAM_WD9 ((0x00e9 << 2) + 0xfe036400)
+#define DMC_DRAM_WD10 ((0x00ea << 2) + 0xfe036400)
+#define DMC_DRAM_WD11 ((0x00eb << 2) + 0xfe036400)
+#define DMC_DRAM_WD12 ((0x00ec << 2) + 0xfe036400)
+#define DMC_DRAM_WD13 ((0x00ed << 2) + 0xfe036400)
+#define DMC_DRAM_WD14 ((0x00ee << 2) + 0xfe036400)
+#define DMC_DRAM_WD15 ((0x00ef << 2) + 0xfe036400)
+#define DMC_DRAM_RD0 ((0x00f0 << 2) + 0xfe036400)
+#define DMC_DRAM_RD1 ((0x00f1 << 2) + 0xfe036400)
+#define DMC_DRAM_RD2 ((0x00f2 << 2) + 0xfe036400)
+#define DMC_DRAM_RD3 ((0x00f3 << 2) + 0xfe036400)
+#define DMC_DRAM_RD4 ((0x00f4 << 2) + 0xfe036400)
+#define DMC_DRAM_RD5 ((0x00f5 << 2) + 0xfe036400)
+#define DMC_DRAM_RD6 ((0x00f6 << 2) + 0xfe036400)
+#define DMC_DRAM_RD7 ((0x00f7 << 2) + 0xfe036400)
+#define DMC_DRAM_RD8 ((0x00f8 << 2) + 0xfe036400)
+#define DMC_DRAM_RD9 ((0x00f9 << 2) + 0xfe036400)
+#define DMC_DRAM_RD10 ((0x00fa << 2) + 0xfe036400)
+#define DMC_DRAM_RD11 ((0x00fb << 2) + 0xfe036400)
+#define DMC_DRAM_RD12 ((0x00fc << 2) + 0xfe036400)
+#define DMC_DRAM_RD13 ((0x00fd << 2) + 0xfe036400)
+#define DMC_DRAM_RD14 ((0x00fe << 2) + 0xfe036400)
+#define DMC_DRAM_RD15 ((0x00ff << 2) + 0xfe036400)
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_siu_reg.vh
+//
+//
+// Reading file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh
+//
+//dmc sticky domain regsiters.
+//`define DMC_STICKY_REG_BASE 32'hfe036800
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe036800
+// -----------------------------------------------
+//those register is for software save some tempary value. and because it's in RAM. it won't lose if DMC get reseted.
+//total DMC_STICKY registers is DMC_STICKY_0 ~ DMC_STICKY_127 total 128 regsiter. the address is from 0x00 ~0x80. here only list 64.
+#define DMC_STICKY_0 ((0x0000 << 2) + 0xfe036800)
+#define DMC_STICKY_1 ((0x0001 << 2) + 0xfe036800)
+#define DMC_STICKY_2 ((0x0002 << 2) + 0xfe036800)
+#define DMC_STICKY_3 ((0x0003 << 2) + 0xfe036800)
+#define DMC_STICKY_4 ((0x0004 << 2) + 0xfe036800)
+#define DMC_STICKY_5 ((0x0005 << 2) + 0xfe036800)
+#define DMC_STICKY_6 ((0x0006 << 2) + 0xfe036800)
+#define DMC_STICKY_7 ((0x0007 << 2) + 0xfe036800)
+#define DMC_STICKY_8 ((0x0008 << 2) + 0xfe036800)
+#define DMC_STICKY_9 ((0x0009 << 2) + 0xfe036800)
+#define DMC_STICKY_10 ((0x000a << 2) + 0xfe036800)
+#define DMC_STICKY_11 ((0x000b << 2) + 0xfe036800)
+#define DMC_STICKY_12 ((0x000c << 2) + 0xfe036800)
+#define DMC_STICKY_13 ((0x000d << 2) + 0xfe036800)
+#define DMC_STICKY_14 ((0x000e << 2) + 0xfe036800)
+#define DMC_STICKY_15 ((0x000f << 2) + 0xfe036800)
+#define DMC_STICKY_16 ((0x0010 << 2) + 0xfe036800)
+#define DMC_STICKY_17 ((0x0011 << 2) + 0xfe036800)
+#define DMC_STICKY_18 ((0x0012 << 2) + 0xfe036800)
+#define DMC_STICKY_19 ((0x0013 << 2) + 0xfe036800)
+#define DMC_STICKY_20 ((0x0014 << 2) + 0xfe036800)
+#define DMC_STICKY_21 ((0x0015 << 2) + 0xfe036800)
+#define DMC_STICKY_22 ((0x0016 << 2) + 0xfe036800)
+#define DMC_STICKY_23 ((0x0017 << 2) + 0xfe036800)
+#define DMC_STICKY_24 ((0x0018 << 2) + 0xfe036800)
+#define DMC_STICKY_25 ((0x0019 << 2) + 0xfe036800)
+#define DMC_STICKY_26 ((0x001a << 2) + 0xfe036800)
+#define DMC_STICKY_27 ((0x001b << 2) + 0xfe036800)
+#define DMC_STICKY_28 ((0x001c << 2) + 0xfe036800)
+#define DMC_STICKY_29 ((0x001d << 2) + 0xfe036800)
+#define DMC_STICKY_30 ((0x001e << 2) + 0xfe036800)
+#define DMC_STICKY_31 ((0x001f << 2) + 0xfe036800)
+#define DMC_STICKY_32 ((0x0020 << 2) + 0xfe036800)
+#define DMC_STICKY_33 ((0x0021 << 2) + 0xfe036800)
+#define DMC_STICKY_34 ((0x0022 << 2) + 0xfe036800)
+#define DMC_STICKY_35 ((0x0023 << 2) + 0xfe036800)
+#define DMC_STICKY_36 ((0x0024 << 2) + 0xfe036800)
+#define DMC_STICKY_37 ((0x0025 << 2) + 0xfe036800)
+#define DMC_STICKY_38 ((0x0026 << 2) + 0xfe036800)
+#define DMC_STICKY_39 ((0x0027 << 2) + 0xfe036800)
+#define DMC_STICKY_40 ((0x0028 << 2) + 0xfe036800)
+#define DMC_STICKY_41 ((0x0029 << 2) + 0xfe036800)
+#define DMC_STICKY_42 ((0x002a << 2) + 0xfe036800)
+#define DMC_STICKY_43 ((0x002b << 2) + 0xfe036800)
+#define DMC_STICKY_44 ((0x002c << 2) + 0xfe036800)
+#define DMC_STICKY_45 ((0x002d << 2) + 0xfe036800)
+#define DMC_STICKY_46 ((0x002e << 2) + 0xfe036800)
+#define DMC_STICKY_47 ((0x002f << 2) + 0xfe036800)
+#define DMC_STICKY_48 ((0x0030 << 2) + 0xfe036800)
+#define DMC_STICKY_49 ((0x0031 << 2) + 0xfe036800)
+#define DMC_STICKY_50 ((0x0032 << 2) + 0xfe036800)
+#define DMC_STICKY_51 ((0x0033 << 2) + 0xfe036800)
+#define DMC_STICKY_52 ((0x0034 << 2) + 0xfe036800)
+#define DMC_STICKY_53 ((0x0035 << 2) + 0xfe036800)
+#define DMC_STICKY_54 ((0x0036 << 2) + 0xfe036800)
+#define DMC_STICKY_55 ((0x0037 << 2) + 0xfe036800)
+#define DMC_STICKY_56 ((0x0038 << 2) + 0xfe036800)
+#define DMC_STICKY_57 ((0x0039 << 2) + 0xfe036800)
+#define DMC_STICKY_58 ((0x003a << 2) + 0xfe036800)
+#define DMC_STICKY_59 ((0x003b << 2) + 0xfe036800)
+#define DMC_STICKY_60 ((0x003c << 2) + 0xfe036800)
+#define DMC_STICKY_61 ((0x003d << 2) + 0xfe036800)
+#define DMC_STICKY_62 ((0x003e << 2) + 0xfe036800)
+#define DMC_STICKY_63 ((0x003f << 2) + 0xfe036800)
+//
+// Closing file: ../mmc_lp4/dmc/rtl/dmc_sticky_reg.vh
+//
+//========================================================================
+// STARTUP
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe02e000
+// -----------------------------------------------
+#define STARTUP_CTRL0 ((0x0000 << 2) + 0xfe02e000)
+#define STARTUP_CTRL1 ((0x0001 << 2) + 0xfe02e000)
+#define STARTUP_CTRL2 ((0x0002 << 2) + 0xfe02e000)
+//========================================================================
+// MIPI_DSI_PHY
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe01c000
+// -----------------------------------------------
+//`define MIPI_DSI_PHY_START 8'h00
+//`define MIPI_DSI_PHY_END 16'hffff
+#define MIPI_DSI_PHY_CTRL ((0x0000 << 2) + 0xfe01c000)
+ //bit 31. soft reset for the phy. 1 = reset. 0 = dessert the reset.
+ //bit 30. clock lane soft reset.
+ //bit 29. data byte lane 3 soft reset.
+ //bit 28. data byte lane 2 soft reset.
+ //bit 27. data byte lane 1 soft reset.
+ //bit 26. data byte lane 0 soft reset.
+ //bit 5. LPDT data endian. 1 = transfer the high bit first. 0 : transfer the low bit first.
+ //bit 4. HS data endian.
+ //bit 3. force data byte lane in stop mode.
+ //bit 2. force data byte lane 0 in reciever mode.
+ //bit 1. write 1 to sync the txclkesc input. the internal logic have to use txclkesc to decide Txvalid and Txready.
+ //bit 0. enalbe the MIPI DSI PHY TxDDRClk.
+#define MIPI_DSI_CHAN_CTRL ((0x0001 << 2) + 0xfe01c000)
+ //bit 31. clk lane tx_hs_en control selection. 1 = from register. 0 use clk lane state machine.
+ //bit 30. register bit for clock lane tx_hs_en.
+ //bit 29. clk lane tx_lp_en contrl selection. 1 = from register. 0 from clk lane state machine.
+ //bit 28. register bit for clock lane tx_lp_en.
+ //bit 27. chan0 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 26. register bit for chan0 tx_hs_en.
+ //bit 25. chan0 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 24. register bit from chan0 tx_lp_en.
+ //bit 23. chan0 rx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 22. register bit from chan0 rx_lp_en.
+ //bit 21. chan0 contention detection enable control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 20. register bit from chan0 contention dectection enable.
+ //bit 19. chan1 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 18. register bit for chan1 tx_hs_en.
+ //bit 17. chan1 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 16. register bit from chan1 tx_lp_en.
+ //bit 15. chan2 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 14. register bit for chan2 tx_hs_en.
+ //bit 13. chan2 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 12. register bit from chan2 tx_lp_en.
+ //bit 11. chan3 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 10. register bit for chan3 tx_hs_en.
+ //bit 9. chan3 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 8. register bit from chan3 tx_lp_en.
+ //bit 4. clk chan power down. this bit is also used as the power down of the whole MIPI_DSI_PHY.
+ //bit 3. chan3 power down.
+ //bit 2. chan2 power down.
+ //bit 1. chan1 power down.
+ //bit 0. chan0 power down.
+#define MIPI_DSI_CHAN_STS ((0x0002 << 2) + 0xfe01c000)
+ //bit 24. chan0 TX->RX turn can't accept the ACK command from slave watch dog triggered. write 1 to clear the status bit.
+ //bit 23. chan0 RX ESC command watch dog triggered. write 1 to clean this bit.
+ //bit
+#define MIPI_DSI_CLK_TIM ((0x0003 << 2) + 0xfe01c000)
+ //bit 31:24. TCLK_PREPARE.
+ //bit 23:16. TCLK_ZERO.
+ //bit 15:8. TCLK_POST.
+ //bit 7:0. TCLK_TRAIL.
+#define MIPI_DSI_HS_TIM ((0x0004 << 2) + 0xfe01c000)
+ //bit 31:24. THS_PREPARE.
+ //bit 23:16. THS_ZERO.
+ //bit 15:8. THS_TRAIL.
+ //bit 7:0. THS_EXIT.
+#define MIPI_DSI_LP_TIM ((0x0005 << 2) + 0xfe01c000)
+ //bit 31:24. tTA_GET.
+ //bit 23:16. tTA_GO.
+ //bit 15:8. tTA_SURE.
+ //bit 7:0. tLPX.
+#define MIPI_DSI_ANA_UP_TIM ((0x0006 << 2) + 0xfe01c000)
+ //wait time to MIPI DIS analog ready.
+#define MIPI_DSI_INIT_TIM ((0x0007 << 2) + 0xfe01c000)
+ // TINIT.
+#define MIPI_DSI_WAKEUP_TIM ((0x0008 << 2) + 0xfe01c000)
+ //TWAKEUP.
+#define MIPI_DSI_LPOK_TIM ((0x0009 << 2) + 0xfe01c000)
+ //bit 31:0 when in RxULPS state, RX reciever is in sleep mode.
+ //every MIPI_DSI_ULPS_CHECK period, the reciever would be enabled once, and waiting this timer period to get the stable input.
+#define MIPI_DSI_LP_WCHDOG ((0x000a << 2) + 0xfe01c000)
+ //bit 31:0 watch dog timer for MIPI DSI LP receive state.
+#define MIPI_DSI_ANA_CTRL ((0x000b << 2) + 0xfe01c000)
+ //bit 31:0 tMBIAS. timer to wait for analog mBIAS voltage stable.
+#define MIPI_DSI_CLK_TIM1 ((0x000c << 2) + 0xfe01c000)
+ //bit 31:8 not used.
+ //bit 7:0 tCLK_PRE
+#define MIPI_DSI_TURN_WCHDOG ((0x000d << 2) + 0xfe01c000)
+ //bit 31:0 watch dog timer for lane 0 LP turn around waiting time.
+#define MIPI_DSI_ULPS_CHECK ((0x000e << 2) + 0xfe01c000)
+ //bit 31:0 when Lane0 in LP recieve state, if the another side sent Low power command, using this timer to enable Tcheck the another size wakeup nor not.
+#define MIPI_DSI_TEST_CTRL0 ((0x000f << 2) + 0xfe01c000)
+#define MIPI_DSI_TEST_CTRL1 ((0x0010 << 2) + 0xfe01c000)
+//========================================================================
+// Temp sensor PLL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe020000
+// -----------------------------------------------
+#define TS_PLL_CFG_REG1 ((0x0001 << 2) + 0xfe020000)
+#define TS_PLL_CFG_REG2 ((0x0002 << 2) + 0xfe020000)
+#define TS_PLL_CFG_REG3 ((0x0003 << 2) + 0xfe020000)
+#define TS_PLL_CFG_REG4 ((0x0004 << 2) + 0xfe020000)
+#define TS_PLL_CFG_REG5 ((0x0005 << 2) + 0xfe020000)
+#define TS_PLL_CFG_REG6 ((0x0006 << 2) + 0xfe020000)
+#define TS_PLL_CFG_REG7 ((0x0007 << 2) + 0xfe020000)
+#define TS_PLL_STAT0 ((0x0010 << 2) + 0xfe020000)
+#define TS_PLL_STAT1 ((0x0011 << 2) + 0xfe020000)
+#define TS_PLL_STAT2 ((0x0012 << 2) + 0xfe020000)
+#define TS_PLL_STAT3 ((0x0013 << 2) + 0xfe020000)
+#define TS_PLL_STAT4 ((0x0014 << 2) + 0xfe020000)
+#define TS_PLL_STAT5 ((0x0015 << 2) + 0xfe020000)
+#define TS_PLL_STAT6 ((0x0016 << 2) + 0xfe020000)
+#define TS_PLL_STAT7 ((0x0017 << 2) + 0xfe020000)
+#define TS_PLL_STAT8 ((0x0018 << 2) + 0xfe020000)
+#define TS_PLL_STAT9 ((0x0019 << 2) + 0xfe020000)
+//========================================================================
+// Temp sensor DDR
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe022000
+// -----------------------------------------------
+#define TS_DDR_CFG_REG1 ((0x0001 << 2) + 0xfe022000)
+#define TS_DDR_CFG_REG2 ((0x0002 << 2) + 0xfe022000)
+#define TS_DDR_CFG_REG3 ((0x0003 << 2) + 0xfe022000)
+#define TS_DDR_CFG_REG4 ((0x0004 << 2) + 0xfe022000)
+#define TS_DDR_CFG_REG5 ((0x0005 << 2) + 0xfe022000)
+#define TS_DDR_CFG_REG6 ((0x0006 << 2) + 0xfe022000)
+#define TS_DDR_CFG_REG7 ((0x0007 << 2) + 0xfe022000)
+#define TS_DDR_STAT0 ((0x0010 << 2) + 0xfe022000)
+#define TS_DDR_STAT1 ((0x0011 << 2) + 0xfe022000)
+#define TS_DDR_STAT2 ((0x0012 << 2) + 0xfe022000)
+#define TS_DDR_STAT3 ((0x0013 << 2) + 0xfe022000)
+#define TS_DDR_STAT4 ((0x0014 << 2) + 0xfe022000)
+#define TS_DDR_STAT5 ((0x0015 << 2) + 0xfe022000)
+#define TS_DDR_STAT6 ((0x0016 << 2) + 0xfe022000)
+#define TS_DDR_STAT7 ((0x0017 << 2) + 0xfe022000)
+#define TS_DDR_STAT8 ((0x0018 << 2) + 0xfe022000)
+#define TS_DDR_STAT9 ((0x0019 << 2) + 0xfe022000)
+//========================================================================
+// Temp sensor GPU
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe035000
+// -----------------------------------------------
+//`define TS_GPU_CFG_REG1 8'h01
+//`define TS_GPU_CFG_REG2 8'h02
+//`define TS_GPU_CFG_REG3 8'h03
+//`define TS_GPU_CFG_REG4 8'h04
+//`define TS_GPU_CFG_REG5 8'h05
+//`define TS_GPU_CFG_REG6 8'h06
+//`define TS_GPU_CFG_REG7 8'h07
+//`define TS_GPU_STAT0 8'h10
+//`define TS_GPU_STAT1 8'h11
+//`define TS_GPU_STAT2 8'h12
+//`define TS_GPU_STAT3 8'h13
+//`define TS_GPU_STAT4 8'h14
+//`define TS_GPU_STAT5 8'h15
+//`define TS_GPU_STAT6 8'h16
+//`define TS_GPU_STAT7 8'h17
+//`define TS_GPU_STAT8 8'h18
+//`define TS_GPU_STAT9 8'h19
+//========================================================================
+// RNG
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe034000
+// -----------------------------------------------
+//========================================================================
+// ACODEC
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe01a000
+// -----------------------------------------------
+#define ACODEC_0 ((0x0000 << 2) + 0xfe01a000)
+#define ACODEC_1 ((0x0001 << 2) + 0xfe01a000)
+#define ACODEC_2 ((0x0002 << 2) + 0xfe01a000)
+#define ACODEC_3 ((0x0003 << 2) + 0xfe01a000)
+#define ACODEC_4 ((0x0004 << 2) + 0xfe01a000)
+#define ACODEC_5 ((0x0005 << 2) + 0xfe01a000)
+#define ACODEC_6 ((0x0006 << 2) + 0xfe01a000)
+#define ACODEC_7 ((0x0007 << 2) + 0xfe01a000)
+//========================================================================
+// AML USB PHY A
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe03c000
+// -----------------------------------------------
+#define AMLUSB_A0 ((0x0000 << 2) + 0xfe03c000)
+#define AMLUSB_A1 ((0x0001 << 2) + 0xfe03c000)
+#define AMLUSB_A2 ((0x0002 << 2) + 0xfe03c000)
+#define AMLUSB_A3 ((0x0003 << 2) + 0xfe03c000)
+#define AMLUSB_A4 ((0x0004 << 2) + 0xfe03c000)
+#define AMLUSB_A5 ((0x0005 << 2) + 0xfe03c000)
+#define AMLUSB_A6 ((0x0006 << 2) + 0xfe03c000)
+#define AMLUSB_A7 ((0x0007 << 2) + 0xfe03c000)
+#define AMLUSB_A8 ((0x0008 << 2) + 0xfe03c000)
+#define AMLUSB_A9 ((0x0009 << 2) + 0xfe03c000)
+#define AMLUSB_A10 ((0x000a << 2) + 0xfe03c000)
+#define AMLUSB_A11 ((0x000b << 2) + 0xfe03c000)
+#define AMLUSB_A12 ((0x000c << 2) + 0xfe03c000)
+#define AMLUSB_A13 ((0x000d << 2) + 0xfe03c000)
+#define AMLUSB_A14 ((0x000e << 2) + 0xfe03c000)
+#define AMLUSB_A15 ((0x000f << 2) + 0xfe03c000)
+#define AMLUSB_A16 ((0x0010 << 2) + 0xfe03c000)
+#define AMLUSB_A17 ((0x0011 << 2) + 0xfe03c000)
+#define AMLUSB_A18 ((0x0012 << 2) + 0xfe03c000)
+#define AMLUSB_A19 ((0x0013 << 2) + 0xfe03c000)
+#define AMLUSB_A20 ((0x0014 << 2) + 0xfe03c000)
+#define AMLUSB_A21 ((0x0015 << 2) + 0xfe03c000)
+#define AMLUSB_A22 ((0x0016 << 2) + 0xfe03c000)
+#define AMLUSB_A23 ((0x0017 << 2) + 0xfe03c000)
+#define AMLUSB_A24 ((0x0018 << 2) + 0xfe03c000)
+#define AMLUSB_A25 ((0x0019 << 2) + 0xfe03c000)
+#define AMLUSB_A26 ((0x001a << 2) + 0xfe03c000)
+#define AMLUSB_A27 ((0x001b << 2) + 0xfe03c000)
+#define AMLUSB_A28 ((0x001c << 2) + 0xfe03c000)
+#define AMLUSB_A29 ((0x001d << 2) + 0xfe03c000)
+#define AMLUSB_A30 ((0x001e << 2) + 0xfe03c000)
+#define AMLUSB_A31 ((0x001f << 2) + 0xfe03c000)
+//========================================================================
+// AML USB PHY B
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe03e000
+// -----------------------------------------------
+#define AMLUSB_B0 ((0x0000 << 2) + 0xfe03e000)
+#define AMLUSB_B1 ((0x0001 << 2) + 0xfe03e000)
+#define AMLUSB_B2 ((0x0002 << 2) + 0xfe03e000)
+#define AMLUSB_B3 ((0x0003 << 2) + 0xfe03e000)
+#define AMLUSB_B4 ((0x0004 << 2) + 0xfe03e000)
+#define AMLUSB_B5 ((0x0005 << 2) + 0xfe03e000)
+#define AMLUSB_B6 ((0x0006 << 2) + 0xfe03e000)
+#define AMLUSB_B7 ((0x0007 << 2) + 0xfe03e000)
+#define AMLUSB_B8 ((0x0008 << 2) + 0xfe03e000)
+#define AMLUSB_B9 ((0x0009 << 2) + 0xfe03e000)
+#define AMLUSB_B10 ((0x000a << 2) + 0xfe03e000)
+#define AMLUSB_B11 ((0x000b << 2) + 0xfe03e000)
+#define AMLUSB_B12 ((0x000c << 2) + 0xfe03e000)
+#define AMLUSB_B13 ((0x000d << 2) + 0xfe03e000)
+#define AMLUSB_B14 ((0x000e << 2) + 0xfe03e000)
+#define AMLUSB_B15 ((0x000f << 2) + 0xfe03e000)
+#define AMLUSB_B16 ((0x0010 << 2) + 0xfe03e000)
+#define AMLUSB_B17 ((0x0011 << 2) + 0xfe03e000)
+#define AMLUSB_B18 ((0x0012 << 2) + 0xfe03e000)
+#define AMLUSB_B19 ((0x0013 << 2) + 0xfe03e000)
+#define AMLUSB_B20 ((0x0014 << 2) + 0xfe03e000)
+#define AMLUSB_B21 ((0x0015 << 2) + 0xfe03e000)
+#define AMLUSB_B22 ((0x0016 << 2) + 0xfe03e000)
+#define AMLUSB_B23 ((0x0017 << 2) + 0xfe03e000)
+#define AMLUSB_B24 ((0x0018 << 2) + 0xfe03e000)
+#define AMLUSB_B25 ((0x0019 << 2) + 0xfe03e000)
+#define AMLUSB_B26 ((0x001a << 2) + 0xfe03e000)
+#define AMLUSB_B27 ((0x001b << 2) + 0xfe03e000)
+#define AMLUSB_B28 ((0x001c << 2) + 0xfe03e000)
+#define AMLUSB_B29 ((0x001d << 2) + 0xfe03e000)
+#define AMLUSB_B30 ((0x001e << 2) + 0xfe03e000)
+#define AMLUSB_B31 ((0x001f << 2) + 0xfe03e000)
+//========================================================================
+// PAD_CTRL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe004000
+// -----------------------------------------------
+#define PADCTRL_PIN_MUX_REG0 ((0x0000 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG1 ((0x0001 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG3 ((0x0003 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG4 ((0x0004 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG5 ((0x0005 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG6 ((0x0006 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG7 ((0x0007 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG8 ((0x0008 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG9 ((0x0009 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGA ((0x000a << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGB ((0x000b << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGC ((0x000c << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGD ((0x000d << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGE ((0x000e << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGF ((0x000f << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGG ((0x0010 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGH ((0x0011 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGI ((0x0012 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGJ ((0x0013 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL0 ((0x0020 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL1 ((0x0021 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL2 ((0x0022 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL3 ((0x0023 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL4 ((0x0024 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL5 ((0x0025 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL6 ((0x0026 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL7 ((0x0027 << 2) + 0xfe004000)
+#define PADCTRL_WORLD_SYNC_CTRL0 ((0x0028 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_MSR_CTRL0 ((0x0029 << 2) + 0xfe004000)
+#define PADCTRL_MISC_CTRL0 ((0x002a << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_I ((0x0030 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_O ((0x0031 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_OEN ((0x0032 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_PULL_EN ((0x0033 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_PULL_UP ((0x0034 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_LOCK ((0x0035 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_PROT ((0x0036 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_DS ((0x0037 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_I ((0x0040 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_O ((0x0041 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_OEN ((0x0042 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_PULL_EN ((0x0043 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_PULL_UP ((0x0044 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_LOCK ((0x0045 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_PROT ((0x0046 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_DS ((0x0047 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_DS_EXT ((0x0048 << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_I ((0x0050 << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_O ((0x0051 << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_OEN ((0x0052 << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_PULL_EN ((0x0053 << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_PULL_UP ((0x0054 << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_LOCK ((0x0055 << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_PROT ((0x0056 << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_DS ((0x0057 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_I ((0x0060 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_O ((0x0061 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_OEN ((0x0062 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_PULL_EN ((0x0063 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_PULL_UP ((0x0064 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_LOCK ((0x0065 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_PROT ((0x0066 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_DS ((0x0067 << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_I ((0x0070 << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_O ((0x0071 << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_OEN ((0x0072 << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_PULL_EN ((0x0073 << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_PULL_UP ((0x0074 << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_LOCK ((0x0075 << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_PROT ((0x0076 << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_DS ((0x0077 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_I ((0x0080 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_O ((0x0081 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_OEN ((0x0082 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_PULL_EN ((0x0083 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_PULL_UP ((0x0084 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_LOCK ((0x0085 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_PROT ((0x0086 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_DS ((0x0087 << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_I ((0x0090 << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_O ((0x0091 << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_OEN ((0x0092 << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_PULL_EN ((0x0093 << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_PULL_UP ((0x0094 << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_LOCK ((0x0095 << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_PROT ((0x0096 << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_DS ((0x0097 << 2) + 0xfe004000)
+#define PADCTRL_GPIOA_I ((0x00a0 << 2) + 0xfe004000)
+#define PADCTRL_GPIOA_O ((0x00a1 << 2) + 0xfe004000)
+#define PADCTRL_GPIOA_OEN ((0x00a2 << 2) + 0xfe004000)
+#define PADCTRL_GPIOA_PULL_EN ((0x00a3 << 2) + 0xfe004000)
+#define PADCTRL_GPIOA_PULL_UP ((0x00a4 << 2) + 0xfe004000)
+#define PADCTRL_GPIOA_LOCK ((0x00a5 << 2) + 0xfe004000)
+#define PADCTRL_GPIOA_PROT ((0x00a6 << 2) + 0xfe004000)
+#define PADCTRL_GPIOA_DS ((0x00a7 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_I ((0x00b0 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_O ((0x00b1 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_OEN ((0x00b2 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_PULL_EN ((0x00b3 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_PULL_UP ((0x00b4 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_LOCK ((0x00b5 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_PROT ((0x00b6 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_DS ((0x00b7 << 2) + 0xfe004000)
+#define PADCTRL_LOCK_PIN_MUX0 ((0x00d0 << 2) + 0xfe004000)
+#define PADCTRL_LOCK_PIN_MUX1 ((0x00d1 << 2) + 0xfe004000)
+#define PADCTRL_LOCK_PIN_MUX2 ((0x00d2 << 2) + 0xfe004000)
+#define PADCTRL_LOCK_PIN_MUX3 ((0x00d3 << 2) + 0xfe004000)
+#define PADCTRL_LOCK_PIN_MUX4 ((0x00d4 << 2) + 0xfe004000)
+#define PADCTRL_PROT_PIN_MUX0 ((0x00d8 << 2) + 0xfe004000)
+#define PADCTRL_PROT_PIN_MUX1 ((0x00d9 << 2) + 0xfe004000)
+#define PADCTRL_PROT_PIN_MUX2 ((0x00da << 2) + 0xfe004000)
+#define PADCTRL_PROT_PIN_MUX3 ((0x00db << 2) + 0xfe004000)
+#define PADCTRL_PROT_PIN_MUX4 ((0x00dc << 2) + 0xfe004000)
+#define PADCTRL_MUTE_CTRL ((0x00e0 << 2) + 0xfe004000)
+#define PADCTRL_MUTE_TDM_DISA ((0x00e1 << 2) + 0xfe004000)
+#define PADCTRL_DEBUG_SEL ((0x00e2 << 2) + 0xfe004000)
+//========================================================================
+// SYS_CTRL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe010000
+// -----------------------------------------------
+#define SYSCTRL_METAL_REV0 ((0x0000 << 2) + 0xfe010000)
+#define SYSCTRL_METAL_REV1 ((0x0001 << 2) + 0xfe010000)
+#define SYSCTRL_CHIP_ID ((0x000b << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE1_REG0 ((0x0010 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE1_STICKY_REG0 ((0x0011 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE1_SEC_REG0 ((0x0012 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE1_STICKY_SEC_REG0 ((0x0013 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE_REG0 ((0x0014 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE_REG1 ((0x0015 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE_SEC_REG0 ((0x0016 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE_STICKY_REG0 ((0x0017 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE_STICKY_REG1 ((0x0018 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE_STICKY_SEC_REG0 ((0x0019 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERA_CTRL ((0x0030 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERA ((0x0031 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERB_CTRL ((0x0032 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERB ((0x0033 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERC_CTRL ((0x0034 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERC ((0x0035 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERD_CTRL ((0x0036 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERD ((0x0037 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_TIMERA_CTRL ((0x0038 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_TIMERA ((0x0039 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERE_CTRL ((0x003a << 2) + 0xfe010000)
+#define SYSCTRL_TIMERE ((0x003b << 2) + 0xfe010000)
+#define SYSCTRL_TIMERE_HI ((0x003c << 2) + 0xfe010000)
+#define SYSCTRL_TIMERF_CTRL ((0x003d << 2) + 0xfe010000)
+#define SYSCTRL_TIMERF ((0x003e << 2) + 0xfe010000)
+#define SYSCTRL_TIMERF_HI ((0x003f << 2) + 0xfe010000)
+#define SYSCTRL_TIMERG_CTRL ((0x0040 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERG ((0x0041 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERH_CTRL ((0x0042 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERH ((0x0043 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERI_CTRL ((0x0044 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERI ((0x0045 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERJ_CTRL ((0x0046 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERJ ((0x0047 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_TIMERE_CTRL ((0x0048 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_TIMERE ((0x0049 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_TIMERE_HI ((0x004a << 2) + 0xfe010000)
+#define SYSCTRL_OSC_RING_CTRL0 ((0x0050 << 2) + 0xfe010000)
+#define SYSCTRL_OSC_RING_CTRL1 ((0x0051 << 2) + 0xfe010000)
+#define SYSCTRL_AM2AXI_CTRL0 ((0x0052 << 2) + 0xfe010000)
+#define SYSCTRL_AM2AXI_STS ((0x0053 << 2) + 0xfe010000)
+#define SYSCTRL_AXI_PIPE_CTRL0 ((0x0055 << 2) + 0xfe010000)
+#define SYSCTRL_AXI_PIPE_CTRL1 ((0x0056 << 2) + 0xfe010000)
+#define SYSCTRL_TIMER90K ((0x0057 << 2) + 0xfe010000)
+#define SYSCTRL_SCR ((0x0058 << 2) + 0xfe010000)
+#define SYSCTRL_HPG_TIMER ((0x0059 << 2) + 0xfe010000)
+//`define SYSCTRL_VIPNANOQ_CTRL0 10'h5A
+#define SYSCTRL_AHB2DDR_CTRL0 ((0x005b << 2) + 0xfe010000)
+#define SYSCTRL_AHB2DDR_CTRL1 ((0x005c << 2) + 0xfe010000)
+#define SYSCTRL_POC ((0x0060 << 2) + 0xfe010000)
+#define SYSCTRL_VPU_SECURE_REG0 ((0x0061 << 2) + 0xfe010000)
+#define SYSCTRL_VPU_SECURE_REG1 ((0x0062 << 2) + 0xfe010000)
+//`define SYSCTRL_NIC_CFG0 10'h63
+#define SYSCTRL_ALERT_STS ((0x0064 << 2) + 0xfe010000)
+#define SYSCTRL_ALERT_ENABLE ((0x0066 << 2) + 0xfe010000)
+#define SYSCTRL_ENABLE_SPIFC ((0x0068 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG0 ((0x0090 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG1 ((0x0091 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG2 ((0x0092 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG3 ((0x0093 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG4 ((0x0094 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG5 ((0x0095 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG6 ((0x0096 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG7 ((0x0097 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG0 ((0x00a0 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG1 ((0x00a1 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG2 ((0x00a2 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG3 ((0x00a3 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG4 ((0x00a4 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG5 ((0x00a5 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG6 ((0x00a6 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG7 ((0x00a7 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG0 ((0x00b0 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG1 ((0x00b1 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG2 ((0x00b2 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG3 ((0x00b3 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG4 ((0x00b4 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG5 ((0x00b5 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG6 ((0x00b6 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG7 ((0x00b7 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG0 ((0x00c0 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG1 ((0x00c1 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG2 ((0x00c2 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG3 ((0x00c3 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG4 ((0x00c4 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG5 ((0x00c5 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG6 ((0x00c6 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG7 ((0x00c7 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG8 ((0x00c8 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG9 ((0x00c9 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG10 ((0x00ca << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG11 ((0x00cb << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG12 ((0x00cc << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG13 ((0x00cd << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG14 ((0x00ce << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG15 ((0x00cf << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG16 ((0x00d0 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG17 ((0x00d1 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG18 ((0x00d2 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG19 ((0x00d3 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG20 ((0x00d4 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG21 ((0x00d5 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG22 ((0x00d6 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG23 ((0x00d7 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG24 ((0x00d8 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG25 ((0x00d9 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG26 ((0x00da << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG27 ((0x00db << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG28 ((0x00dc << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG29 ((0x00dd << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG30 ((0x00de << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG31 ((0x00df << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG0 ((0x00e0 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG1 ((0x00e1 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG2 ((0x00e2 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG3 ((0x00e3 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG4 ((0x00e4 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG5 ((0x00e5 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG6 ((0x00e6 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG7 ((0x00e7 << 2) + 0xfe010000)
+#define SYSCTRL_MSG_INDEX0_STICKY ((0x00f0 << 2) + 0xfe010000)
+#define SYSCTRL_MSG_INDEX1_STICKY ((0x00f1 << 2) + 0xfe010000)
+#define SYSCTRL_MSG_INDEX2_STICKY ((0x00f2 << 2) + 0xfe010000)
+#define SYSCTRL_MSG_INDEX3_STICKY ((0x00f3 << 2) + 0xfe010000)
+//========================================================================
+// CLK_CTRL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe000000
+// -----------------------------------------------
+#define CLKCTRL_OSCIN_CTRL ((0x0001 << 2) + 0xfe000000)
+#define CLKCTRL_RTC_BY_OSCIN_CTRL0 ((0x0002 << 2) + 0xfe000000)
+#define CLKCTRL_RTC_BY_OSCIN_CTRL1 ((0x0003 << 2) + 0xfe000000)
+#define CLKCTRL_RTC_CTRL ((0x0004 << 2) + 0xfe000000)
+#define CLKCTRL_CHECK_CLK_RESULT ((0x0005 << 2) + 0xfe000000)
+#define CLKCTRL_MBIST_ATSPEED_CTRL ((0x0006 << 2) + 0xfe000000)
+#define CLKCTRL_LOCK_BIT_REG0 ((0x0008 << 2) + 0xfe000000)
+#define CLKCTRL_LOCK_BIT_REG1 ((0x0009 << 2) + 0xfe000000)
+#define CLKCTRL_LOCK_BIT_REG2 ((0x000a << 2) + 0xfe000000)
+#define CLKCTRL_LOCK_BIT_REG3 ((0x000b << 2) + 0xfe000000)
+#define CLKCTRL_PROT_BIT_REG0 ((0x000c << 2) + 0xfe000000)
+#define CLKCTRL_PROT_BIT_REG1 ((0x000d << 2) + 0xfe000000)
+#define CLKCTRL_PROT_BIT_REG2 ((0x000e << 2) + 0xfe000000)
+#define CLKCTRL_PROT_BIT_REG3 ((0x000f << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_CTRL0 ((0x0010 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN0_REG0 ((0x0011 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN0_REG1 ((0x0012 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN0_REG2 ((0x0013 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN0_REG3 ((0x0014 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN1_REG0 ((0x0015 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN1_REG1 ((0x0016 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN1_REG2 ((0x0017 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN1_REG3 ((0x0018 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_VPU_EN0 ((0x0019 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_VPU_EN1 ((0x001a << 2) + 0xfe000000)
+#define CLKCTRL_AXI_CLK_CTRL0 ((0x001b << 2) + 0xfe000000)
+#define CLKCTRL_TST_CTRL0 ((0x0020 << 2) + 0xfe000000)
+#define CLKCTRL_TST_CTRL1 ((0x0021 << 2) + 0xfe000000)
+#define CLKCTRL_CECA_CTRL0 ((0x0022 << 2) + 0xfe000000)
+#define CLKCTRL_CECA_CTRL1 ((0x0023 << 2) + 0xfe000000)
+#define CLKCTRL_CECB_CTRL0 ((0x0024 << 2) + 0xfe000000)
+#define CLKCTRL_CECB_CTRL1 ((0x0025 << 2) + 0xfe000000)
+#define CLKCTRL_SC_CLK_CTRL ((0x0026 << 2) + 0xfe000000)
+#define CLKCTRL_DSPA_CLK_CTRL0 ((0x0027 << 2) + 0xfe000000)
+#define CLKCTRL_DSPB_CLK_CTRL0 ((0x0028 << 2) + 0xfe000000)
+#define CLKCTRL_RAMA_CLK_CTRL0 ((0x0029 << 2) + 0xfe000000)
+#define CLKCTRL_VID_CLK_CTRL ((0x0030 << 2) + 0xfe000000)
+#define CLKCTRL_VID_CLK_CTRL2 ((0x0031 << 2) + 0xfe000000)
+#define CLKCTRL_VID_CLK_DIV ((0x0032 << 2) + 0xfe000000)
+#define CLKCTRL_VIID_CLK_DIV ((0x0033 << 2) + 0xfe000000)
+#define CLKCTRL_VIID_CLK_CTRL ((0x0034 << 2) + 0xfe000000)
+#define CLKCTRL_HDMI_CLK_CTRL ((0x0038 << 2) + 0xfe000000)
+#define CLKCTRL_VID_PLL_CLK_DIV ((0x0039 << 2) + 0xfe000000)
+#define CLKCTRL_VPU_CLK_CTRL ((0x003a << 2) + 0xfe000000)
+#define CLKCTRL_VPU_CLKB_CTRL ((0x003b << 2) + 0xfe000000)
+#define CLKCTRL_VPU_CLKC_CTRL ((0x003c << 2) + 0xfe000000)
+#define CLKCTRL_VID_LOCK_CLK_CTRL ((0x003d << 2) + 0xfe000000)
+#define CLKCTRL_VDIN_MEAS_CLK_CTRL ((0x003e << 2) + 0xfe000000)
+#define CLKCTRL_VAPBCLK_CTRL ((0x003f << 2) + 0xfe000000)
+#define CLKCTRL_HDCP22_CLK_CTRL ((0x0040 << 2) + 0xfe000000)
+#define CLKCTRL_MIPIDSI_PHY_CLK_CTRL ((0x0041 << 2) + 0xfe000000)
+#define CLKCTRL_CDAC_CLK_CTRL ((0x0042 << 2) + 0xfe000000)
+#define CLKCTRL_MIPI_CSI_PHY_CLK_CTRL ((0x0043 << 2) + 0xfe000000)
+#define CLKCTRL_CSI2_ADAPT_CLK_CTRL ((0x0044 << 2) + 0xfe000000)
+#define CLKCTRL_VDEC_CLK_CTRL ((0x0050 << 2) + 0xfe000000)
+#define CLKCTRL_VDEC2_CLK_CTRL ((0x0051 << 2) + 0xfe000000)
+#define CLKCTRL_VDEC3_CLK_CTRL ((0x0052 << 2) + 0xfe000000)
+#define CLKCTRL_VDEC4_CLK_CTRL ((0x0053 << 2) + 0xfe000000)
+#define CLKCTRL_WAVE420L_CLK_CTRL ((0x0054 << 2) + 0xfe000000)
+#define CLKCTRL_WAVE420L_CLK_CTRL2 ((0x0055 << 2) + 0xfe000000)
+#define CLKCTRL_TS_CLK_CTRL ((0x0056 << 2) + 0xfe000000)
+#define CLKCTRL_MALI_CLK_CTRL ((0x0057 << 2) + 0xfe000000)
+#define CLKCTRL_VIPNANOQ_CLK_CTRL ((0x0058 << 2) + 0xfe000000)
+#define CLKCTRL_ETH_CLK_CTRL ((0x0059 << 2) + 0xfe000000)
+#define CLKCTRL_NAND_CLK_CTRL ((0x005a << 2) + 0xfe000000)
+#define CLKCTRL_SD_EMMC_CLK_CTRL ((0x005b << 2) + 0xfe000000)
+#define CLKCTRL_BT656_CLK_CTRL ((0x005c << 2) + 0xfe000000)
+#define CLKCTRL_SPICC_CLK_CTRL ((0x005d << 2) + 0xfe000000)
+#define CLKCTRL_GEN_CLK_CTRL ((0x005e << 2) + 0xfe000000)
+#define CLKCTRL_SAR_CLK_CTRL0 ((0x005f << 2) + 0xfe000000)
+#define CLKCTRL_PWM_CLK_AB_CTRL ((0x0060 << 2) + 0xfe000000)
+#define CLKCTRL_PWM_CLK_CD_CTRL ((0x0061 << 2) + 0xfe000000)
+#define CLKCTRL_PWM_CLK_EF_CTRL ((0x0062 << 2) + 0xfe000000)
+#define CLKCTRL_PWM_CLK_GH_CTRL ((0x0063 << 2) + 0xfe000000)
+#define CLKCTRL_PWM_CLK_IJ_CTRL ((0x0064 << 2) + 0xfe000000)
+#define CLKCTRL_TIMESTAMP_CTRL ((0x0100 << 2) + 0xfe000000)
+#define CLKCTRL_TIMESTAMP_CTRL1 ((0x0101 << 2) + 0xfe000000)
+#define CLKCTRL_TIMESTAMP_CTRL2 ((0x0103 << 2) + 0xfe000000)
+#define CLKCTRL_TIMESTAMP_RD0 ((0x0104 << 2) + 0xfe000000)
+#define CLKCTRL_TIMESTAMP_RD1 ((0x0105 << 2) + 0xfe000000)
+#define CLKCTRL_TIMEBASE_CTRL0 ((0x0106 << 2) + 0xfe000000)
+#define CLKCTRL_TIMEBASE_CTRL1 ((0x0107 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_CPU_CFG01 ((0x0120 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_CPU_CFG2 ((0x0121 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_ENCP_CFG0 ((0x0122 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_MALI_CFG01 ((0x0123 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_HEVCB_CFG01 ((0x0124 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_HEVCB_CFG2 ((0x0125 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_LOCK ((0x0126 << 2) + 0xfe000000)
+//========================================================================
+// PWR_CTRL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe00c000
+// -----------------------------------------------
+#define PWRCTRL_PWR_ACK0 ((0x0000 << 2) + 0xfe00c000)
+#define PWRCTRL_PWR_ACK1 ((0x0001 << 2) + 0xfe00c000)
+#define PWRCTRL_PWR_OFF0 ((0x0004 << 2) + 0xfe00c000)
+#define PWRCTRL_PWR_OFF1 ((0x0005 << 2) + 0xfe00c000)
+#define PWRCTRL_ISO_EN0 ((0x0008 << 2) + 0xfe00c000)
+#define PWRCTRL_ISO_EN1 ((0x0009 << 2) + 0xfe00c000)
+#define PWRCTRL_FOCRST0 ((0x000c << 2) + 0xfe00c000)
+#define PWRCTRL_FOCRST1 ((0x000d << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD0 ((0x0010 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD1 ((0x0011 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD2 ((0x0012 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD3 ((0x0013 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD4 ((0x0014 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD5 ((0x0015 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD6 ((0x0016 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD7 ((0x0017 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD8 ((0x0018 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD9 ((0x0019 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD10 ((0x001a << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD11 ((0x001b << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL0 ((0x0040 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL1 ((0x0041 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL2 ((0x0042 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL3 ((0x0043 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL4 ((0x0044 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_TIMER_TH_01 ((0x0048 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_TIMER_TH_23 ((0x0049 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_TIMER_TH_45 ((0x004a << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_TIMER_TH_67 ((0x004b << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_TIMER_TH_89 ((0x004c << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK0 ((0x0050 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK1 ((0x0051 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK2 ((0x0052 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK3 ((0x0053 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK4 ((0x0054 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK5 ((0x0055 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK6 ((0x0056 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK7 ((0x0057 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_INIT_SET ((0x0060 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_OFF_SET ((0x0061 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_ON_A_SET ((0x0062 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_ON_B_SET ((0x0063 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_ON_C_SET ((0x0064 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_ON_D_SET ((0x0065 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_STS ((0x0066 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_FSM_STS0 ((0x0067 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_FSM_STS1 ((0x0068 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_FSM_STS2 ((0x0069 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_FSM_START_OFF ((0x006d << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_FSM_START_ON ((0x006e << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_FSM_JUMP ((0x006f << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL0 ((0x0070 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL1 ((0x0071 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL2 ((0x0072 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL3 ((0x0073 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL4 ((0x0074 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_TIMER_TH_01 ((0x0078 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_TIMER_TH_23 ((0x0079 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_TIMER_TH_45 ((0x007a << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_TIMER_TH_67 ((0x007b << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_TIMER_TH_89 ((0x007c << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK0 ((0x0080 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK1 ((0x0081 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK2 ((0x0082 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK3 ((0x0083 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK4 ((0x0084 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK5 ((0x0085 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK6 ((0x0086 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK7 ((0x0087 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_INIT_SET ((0x0090 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_OFF_SET ((0x0091 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_ON_A_SET ((0x0092 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_ON_B_SET ((0x0093 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_ON_C_SET ((0x0094 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_ON_D_SET ((0x0095 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_STS ((0x0096 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_FSM_STS0 ((0x0097 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_FSM_STS1 ((0x0098 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_FSM_STS2 ((0x0099 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_FSM_START_OFF ((0x009d << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_FSM_START_ON ((0x009e << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_FSM_JUMP ((0x009f << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL0 ((0x00a0 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL1 ((0x00a1 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL2 ((0x00a2 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL3 ((0x00a3 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL4 ((0x00a4 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_TIMER_TH_01 ((0x00a8 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_TIMER_TH_23 ((0x00a9 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_TIMER_TH_45 ((0x00aa << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_TIMER_TH_67 ((0x00ab << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_TIMER_TH_89 ((0x00ac << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK0 ((0x00b0 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK1 ((0x00b1 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK2 ((0x00b2 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK3 ((0x00b3 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK4 ((0x00b4 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK5 ((0x00b5 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK6 ((0x00b6 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK7 ((0x00b7 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_INIT_SET ((0x00c0 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_OFF_SET ((0x00c1 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_ON_A_SET ((0x00c2 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_ON_B_SET ((0x00c3 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_ON_C_SET ((0x00c4 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_ON_D_SET ((0x00c5 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_STS ((0x00c6 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_FSM_STS0 ((0x00c7 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_FSM_STS1 ((0x00c8 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_FSM_STS2 ((0x00c9 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_FSM_START_OFF ((0x00cd << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_FSM_START_ON ((0x00ce << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_FSM_JUMP ((0x00cf << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL0 ((0x00d0 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL1 ((0x00d1 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL2 ((0x00d2 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL3 ((0x00d3 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL4 ((0x00d4 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_TIMER_TH_01 ((0x00d8 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_TIMER_TH_23 ((0x00d9 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_TIMER_TH_45 ((0x00da << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_TIMER_TH_67 ((0x00db << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_TIMER_TH_89 ((0x00dc << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK0 ((0x00e0 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK1 ((0x00e1 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK2 ((0x00e2 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK3 ((0x00e3 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK4 ((0x00e4 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK5 ((0x00e5 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK6 ((0x00e6 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK7 ((0x00e7 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_INIT_SET ((0x00f0 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_OFF_SET ((0x00f1 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_ON_A_SET ((0x00f2 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_ON_B_SET ((0x00f3 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_ON_C_SET ((0x00f4 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_ON_D_SET ((0x00f5 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_STS ((0x00f6 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_FSM_STS0 ((0x00f7 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_FSM_STS1 ((0x00f8 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_FSM_STS2 ((0x00f9 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_FSM_START_OFF ((0x00fd << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_FSM_START_ON ((0x00fe << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_FSM_JUMP ((0x00ff << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL0 ((0x0100 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL1 ((0x0101 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL2 ((0x0102 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL3 ((0x0103 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL4 ((0x0104 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_TIMER_TH_01 ((0x0108 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_TIMER_TH_23 ((0x0109 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_TIMER_TH_45 ((0x010a << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_TIMER_TH_67 ((0x010b << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_TIMER_TH_89 ((0x010c << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK0 ((0x0110 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK1 ((0x0111 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK2 ((0x0112 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK3 ((0x0113 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK4 ((0x0114 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK5 ((0x0115 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK6 ((0x0116 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK7 ((0x0117 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_INIT_SET ((0x0120 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_OFF_SET ((0x0121 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_ON_A_SET ((0x0122 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_ON_B_SET ((0x0123 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_ON_C_SET ((0x0124 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_ON_D_SET ((0x0125 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_STS ((0x0126 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_FSM_STS0 ((0x0127 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_FSM_STS1 ((0x0128 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_FSM_STS2 ((0x0129 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_FSM_START_OFF ((0x012d << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_FSM_START_ON ((0x012e << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_FSM_JUMP ((0x012f << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL0 ((0x0130 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL1 ((0x0131 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL2 ((0x0132 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL3 ((0x0133 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL4 ((0x0134 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_TIMER_TH_01 ((0x0138 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_TIMER_TH_23 ((0x0139 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_TIMER_TH_45 ((0x013a << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_TIMER_TH_67 ((0x013b << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_TIMER_TH_89 ((0x013c << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK0 ((0x0140 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK1 ((0x0141 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK2 ((0x0142 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK3 ((0x0143 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK4 ((0x0144 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK5 ((0x0145 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK6 ((0x0146 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK7 ((0x0147 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_INIT_SET ((0x0150 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_OFF_SET ((0x0151 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_ON_A_SET ((0x0152 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_ON_B_SET ((0x0153 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_ON_C_SET ((0x0154 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_ON_D_SET ((0x0155 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_STS ((0x0156 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_FSM_STS0 ((0x0157 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_FSM_STS1 ((0x0158 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_FSM_STS2 ((0x0159 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_FSM_START_OFF ((0x015d << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_FSM_START_ON ((0x015e << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_FSM_JUMP ((0x015f << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL0 ((0x0160 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL1 ((0x0161 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL2 ((0x0162 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL3 ((0x0163 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL4 ((0x0164 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_TIMER_TH_01 ((0x0168 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_TIMER_TH_23 ((0x0169 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_TIMER_TH_45 ((0x016a << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_TIMER_TH_67 ((0x016b << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_TIMER_TH_89 ((0x016c << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK0 ((0x0170 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK1 ((0x0171 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK2 ((0x0172 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK3 ((0x0173 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK4 ((0x0174 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK5 ((0x0175 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK6 ((0x0176 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK7 ((0x0177 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_INIT_SET ((0x0180 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_OFF_SET ((0x0181 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_ON_A_SET ((0x0182 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_ON_B_SET ((0x0183 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_ON_C_SET ((0x0184 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_ON_D_SET ((0x0185 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_STS ((0x0186 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_FSM_STS0 ((0x0187 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_FSM_STS1 ((0x0188 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_FSM_STS2 ((0x0189 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_FSM_START_OFF ((0x018d << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_FSM_START_ON ((0x018e << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_FSM_JUMP ((0x018f << 2) + 0xfe00c000)
+//========================================================================
+// RSA
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe042000
+// -----------------------------------------------
+//========================================================================
+// AOCPU
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe09c000
+// -----------------------------------------------
+#define AOCPU_CPU_CTRL0 ((0x0000 << 2) + 0xfe09c000)
+#define AOCPU_CPU_CTRL1 ((0x0001 << 2) + 0xfe09c000)
+#define AOCPU_CPU_CTRL2 ((0x0002 << 2) + 0xfe09c000)
+#define AOCPU_CPU_CTRL3 ((0x0003 << 2) + 0xfe09c000)
+#define AOCPU_CPU_CTRL4 ((0x0004 << 2) + 0xfe09c000)
+#define AOCPU_CPU_CTRL5 ((0x0005 << 2) + 0xfe09c000)
+#define AOCPU_CPU_STS0 ((0x000a << 2) + 0xfe09c000)
+#define AOCPU_CPU_STS1 ((0x000b << 2) + 0xfe09c000)
+#define AOCPU_CPU_STS2 ((0x000c << 2) + 0xfe09c000)
+#define AOCPU_CPU_STS3 ((0x000d << 2) + 0xfe09c000)
+#define AOCPU_CPU_VECTOR ((0x000f << 2) + 0xfe09c000)
+#define AOCPU_IRQ_SEL0 ((0x0010 << 2) + 0xfe09c000)
+#define AOCPU_IRQ_SEL1 ((0x0011 << 2) + 0xfe09c000)
+#define AOCPU_IRQ_SEL2 ((0x0012 << 2) + 0xfe09c000)
+#define AOCPU_IRQ_SEL3 ((0x0013 << 2) + 0xfe09c000)
+#define AOCPU_IRQ_SEL4 ((0x0014 << 2) + 0xfe09c000)
+#define AOCPU_IRQ_SEL5 ((0x0015 << 2) + 0xfe09c000)
+#define AOCPU_IRQ_SEL6 ((0x0016 << 2) + 0xfe09c000)
+#define AOCPU_IRQ_SEL7 ((0x0017 << 2) + 0xfe09c000)
+#define AOCPU_STS00_BYCPU ((0x0018 << 2) + 0xfe09c000)
+#define AOCPU_STS01_BYCPU ((0x0019 << 2) + 0xfe09c000)
+#define AOCPU_STS02_BYCPU ((0x001a << 2) + 0xfe09c000)
+#define AOCPU_STS03_BYCPU ((0x001b << 2) + 0xfe09c000)
+#define AOCPU_STS04_BYCPU ((0x001c << 2) + 0xfe09c000)
+#define AOCPU_STS05_BYCPU ((0x001d << 2) + 0xfe09c000)
+#define AOCPU_STS06_BYCPU ((0x001e << 2) + 0xfe09c000)
+#define AOCPU_STS07_BYCPU ((0x001f << 2) + 0xfe09c000)
+//========================================================================
+// AUCPU
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe09e000
+// -----------------------------------------------
+#define AUCPU_CPU_CTRL0 ((0x0000 << 2) + 0xfe09e000)
+#define AUCPU_CPU_CTRL1 ((0x0001 << 2) + 0xfe09e000)
+#define AUCPU_CPU_CTRL2 ((0x0002 << 2) + 0xfe09e000)
+#define AUCPU_CPU_CTRL3 ((0x0003 << 2) + 0xfe09e000)
+#define AUCPU_CPU_CTRL4 ((0x0004 << 2) + 0xfe09e000)
+#define AUCPU_CPU_CTRL5 ((0x0005 << 2) + 0xfe09e000)
+#define AUCPU_CPU_STS0 ((0x000a << 2) + 0xfe09e000)
+#define AUCPU_CPU_STS1 ((0x000b << 2) + 0xfe09e000)
+#define AUCPU_CPU_STS2 ((0x000c << 2) + 0xfe09e000)
+#define AUCPU_CPU_STS3 ((0x000d << 2) + 0xfe09e000)
+#define AUCPU_DMA_APB_SEL ((0x0010 << 2) + 0xfe09e000)
+#define AUCPU_IRQ_AP2RISCV ((0x0011 << 2) + 0xfe09e000)
+#define AUCPU_IRQ_RISCV2AP ((0x0012 << 2) + 0xfe09e000)
+#define AUCPU_STS00_BY_AP ((0x0020 << 2) + 0xfe09e000)
+#define AUCPU_STS01_BY_AP ((0x0021 << 2) + 0xfe09e000)
+#define AUCPU_STS02_BY_AP ((0x0022 << 2) + 0xfe09e000)
+#define AUCPU_STS03_BY_AP ((0x0023 << 2) + 0xfe09e000)
+#define AUCPU_STS04_BY_AP ((0x0024 << 2) + 0xfe09e000)
+#define AUCPU_STS05_BY_AP ((0x0025 << 2) + 0xfe09e000)
+#define AUCPU_STS06_BY_AP ((0x0026 << 2) + 0xfe09e000)
+#define AUCPU_STS07_BY_AP ((0x0027 << 2) + 0xfe09e000)
+#define AUCPU_STS08_BY_AP ((0x0028 << 2) + 0xfe09e000)
+#define AUCPU_STS09_BY_AP ((0x0029 << 2) + 0xfe09e000)
+#define AUCPU_STS10_BY_AP ((0x002a << 2) + 0xfe09e000)
+#define AUCPU_STS11_BY_AP ((0x002b << 2) + 0xfe09e000)
+#define AUCPU_STS12_BY_AP ((0x002c << 2) + 0xfe09e000)
+#define AUCPU_STS13_BY_AP ((0x002d << 2) + 0xfe09e000)
+#define AUCPU_STS14_BY_AP ((0x002e << 2) + 0xfe09e000)
+#define AUCPU_STS15_BY_AP ((0x002f << 2) + 0xfe09e000)
+#define AUCPU_STS16_BY_AP ((0x0030 << 2) + 0xfe09e000)
+#define AUCPU_STS17_BY_AP ((0x0031 << 2) + 0xfe09e000)
+#define AUCPU_STS18_BY_AP ((0x0032 << 2) + 0xfe09e000)
+#define AUCPU_STS19_BY_AP ((0x0033 << 2) + 0xfe09e000)
+#define AUCPU_STS20_BY_AP ((0x0034 << 2) + 0xfe09e000)
+#define AUCPU_STS21_BY_AP ((0x0035 << 2) + 0xfe09e000)
+#define AUCPU_STS22_BY_AP ((0x0036 << 2) + 0xfe09e000)
+#define AUCPU_STS23_BY_AP ((0x0037 << 2) + 0xfe09e000)
+#define AUCPU_STS24_BY_AP ((0x0038 << 2) + 0xfe09e000)
+#define AUCPU_STS25_BY_AP ((0x0039 << 2) + 0xfe09e000)
+#define AUCPU_STS26_BY_AP ((0x003a << 2) + 0xfe09e000)
+#define AUCPU_STS27_BY_AP ((0x003b << 2) + 0xfe09e000)
+#define AUCPU_STS28_BY_AP ((0x003c << 2) + 0xfe09e000)
+#define AUCPU_STS29_BY_AP ((0x003d << 2) + 0xfe09e000)
+#define AUCPU_STS30_BY_AP ((0x003e << 2) + 0xfe09e000)
+#define AUCPU_STS31_BY_AP ((0x003f << 2) + 0xfe09e000)
+#define AUCPU_STS00_BY_RISCV ((0x0040 << 2) + 0xfe09e000)
+#define AUCPU_STS01_BY_RISCV ((0x0041 << 2) + 0xfe09e000)
+#define AUCPU_STS02_BY_RISCV ((0x0042 << 2) + 0xfe09e000)
+#define AUCPU_STS03_BY_RISCV ((0x0043 << 2) + 0xfe09e000)
+#define AUCPU_STS04_BY_RISCV ((0x0044 << 2) + 0xfe09e000)
+#define AUCPU_STS05_BY_RISCV ((0x0045 << 2) + 0xfe09e000)
+#define AUCPU_STS06_BY_RISCV ((0x0046 << 2) + 0xfe09e000)
+#define AUCPU_STS07_BY_RISCV ((0x0047 << 2) + 0xfe09e000)
+#define AUCPU_STS08_BY_RISCV ((0x0048 << 2) + 0xfe09e000)
+#define AUCPU_STS09_BY_RISCV ((0x0049 << 2) + 0xfe09e000)
+#define AUCPU_STS10_BY_RISCV ((0x004a << 2) + 0xfe09e000)
+#define AUCPU_STS11_BY_RISCV ((0x004b << 2) + 0xfe09e000)
+#define AUCPU_STS12_BY_RISCV ((0x004c << 2) + 0xfe09e000)
+#define AUCPU_STS13_BY_RISCV ((0x004d << 2) + 0xfe09e000)
+#define AUCPU_STS14_BY_RISCV ((0x004e << 2) + 0xfe09e000)
+#define AUCPU_STS15_BY_RISCV ((0x004f << 2) + 0xfe09e000)
+#define AUCPU_STS16_BY_RISCV ((0x0050 << 2) + 0xfe09e000)
+#define AUCPU_STS17_BY_RISCV ((0x0051 << 2) + 0xfe09e000)
+#define AUCPU_STS18_BY_RISCV ((0x0052 << 2) + 0xfe09e000)
+#define AUCPU_STS19_BY_RISCV ((0x0053 << 2) + 0xfe09e000)
+#define AUCPU_STS20_BY_RISCV ((0x0054 << 2) + 0xfe09e000)
+#define AUCPU_STS21_BY_RISCV ((0x0055 << 2) + 0xfe09e000)
+#define AUCPU_STS22_BY_RISCV ((0x0056 << 2) + 0xfe09e000)
+#define AUCPU_STS23_BY_RISCV ((0x0057 << 2) + 0xfe09e000)
+#define AUCPU_STS24_BY_RISCV ((0x0058 << 2) + 0xfe09e000)
+#define AUCPU_STS25_BY_RISCV ((0x0059 << 2) + 0xfe09e000)
+#define AUCPU_STS26_BY_RISCV ((0x005a << 2) + 0xfe09e000)
+#define AUCPU_STS27_BY_RISCV ((0x005b << 2) + 0xfe09e000)
+#define AUCPU_STS28_BY_RISCV ((0x005c << 2) + 0xfe09e000)
+#define AUCPU_STS29_BY_RISCV ((0x005d << 2) + 0xfe09e000)
+#define AUCPU_STS30_BY_RISCV ((0x005e << 2) + 0xfe09e000)
+#define AUCPU_STS31_BY_RISCV ((0x005f << 2) + 0xfe09e000)
+#define AUCPU_DEMUX_STS_BY_RISCV ((0x0060 << 2) + 0xfe09e000)
+#define AUCPU_DEMUX_STS0 ((0x0061 << 2) + 0xfe09e000)
+#define AUCPU_DEMUX_STS1 ((0x0062 << 2) + 0xfe09e000)
+//========================================================================
+// AXI_SRAM
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe090000
+// -----------------------------------------------
+#define SRAM_RANGE0_STA ((0x0000 << 2) + 0xfe090000)
+#define SRAM_RANGE1_STA ((0x0001 << 2) + 0xfe090000)
+#define SRAM_RANGE2_STA ((0x0002 << 2) + 0xfe090000)
+#define SRAM_RANGE3_STA ((0x0003 << 2) + 0xfe090000)
+#define SRAM_RANGE4_STA ((0x0004 << 2) + 0xfe090000)
+#define SRAM_RANGE5_STA ((0x0005 << 2) + 0xfe090000)
+#define SRAM_RANGE6_STA ((0x0006 << 2) + 0xfe090000)
+#define SRAM_RANGE7_STA ((0x0007 << 2) + 0xfe090000)
+#define SRAM_RANGE8_STA ((0x0008 << 2) + 0xfe090000)
+#define SRAM_RANGE9_STA ((0x0009 << 2) + 0xfe090000)
+#define SRAM_RANGE10_STA ((0x000a << 2) + 0xfe090000)
+#define SRAM_RANGE11_STA ((0x000b << 2) + 0xfe090000)
+#define SRAM_RANGE12_STA ((0x000c << 2) + 0xfe090000)
+#define SRAM_RANGE13_STA ((0x000d << 2) + 0xfe090000)
+#define SRAM_RANGE14_STA ((0x000e << 2) + 0xfe090000)
+#define SRAM_RANGE0_EDA ((0x000f << 2) + 0xfe090000)
+#define SRAM_RANGE1_EDA ((0x0010 << 2) + 0xfe090000)
+#define SRAM_RANGE2_EDA ((0x0011 << 2) + 0xfe090000)
+#define SRAM_RANGE3_EDA ((0x0012 << 2) + 0xfe090000)
+#define SRAM_RANGE4_EDA ((0x0013 << 2) + 0xfe090000)
+#define SRAM_RANGE5_EDA ((0x0014 << 2) + 0xfe090000)
+#define SRAM_RANGE6_EDA ((0x0015 << 2) + 0xfe090000)
+#define SRAM_RANGE7_EDA ((0x0016 << 2) + 0xfe090000)
+#define SRAM_RANGE8_EDA ((0x0017 << 2) + 0xfe090000)
+#define SRAM_RANGE9_EDA ((0x0018 << 2) + 0xfe090000)
+#define SRAM_RANGE10_EDA ((0x0019 << 2) + 0xfe090000)
+#define SRAM_RANGE11_EDA ((0x001a << 2) + 0xfe090000)
+#define SRAM_RANGE12_EDA ((0x001b << 2) + 0xfe090000)
+#define SRAM_RANGE13_EDA ((0x001c << 2) + 0xfe090000)
+#define SRAM_RANGE14_EDA ((0x001d << 2) + 0xfe090000)
+#define SRAM_RANGE0_READ_CTRL0 ((0x001e << 2) + 0xfe090000)
+#define SRAM_RANGE1_READ_CTRL0 ((0x001f << 2) + 0xfe090000)
+#define SRAM_RANGE2_READ_CTRL0 ((0x0020 << 2) + 0xfe090000)
+#define SRAM_RANGE3_READ_CTRL0 ((0x0021 << 2) + 0xfe090000)
+#define SRAM_RANGE4_READ_CTRL0 ((0x0022 << 2) + 0xfe090000)
+#define SRAM_RANGE5_READ_CTRL0 ((0x0023 << 2) + 0xfe090000)
+#define SRAM_RANGE6_READ_CTRL0 ((0x0024 << 2) + 0xfe090000)
+#define SRAM_RANGE7_READ_CTRL0 ((0x0025 << 2) + 0xfe090000)
+#define SRAM_RANGE8_READ_CTRL0 ((0x0026 << 2) + 0xfe090000)
+#define SRAM_RANGE9_READ_CTRL0 ((0x0027 << 2) + 0xfe090000)
+#define SRAM_RANGE10_READ_CTRL0 ((0x0028 << 2) + 0xfe090000)
+#define SRAM_RANGE11_READ_CTRL0 ((0x0029 << 2) + 0xfe090000)
+#define SRAM_RANGE12_READ_CTRL0 ((0x002a << 2) + 0xfe090000)
+#define SRAM_RANGE13_READ_CTRL0 ((0x002b << 2) + 0xfe090000)
+#define SRAM_RANGE14_READ_CTRL0 ((0x002c << 2) + 0xfe090000)
+#define SRAM_RANGE15_READ_CTRL0 ((0x002d << 2) + 0xfe090000)
+#define SRAM_RANGE0_WRITE_CTRL0 ((0x002e << 2) + 0xfe090000)
+#define SRAM_RANGE1_WRITE_CTRL0 ((0x002f << 2) + 0xfe090000)
+#define SRAM_RANGE2_WRITE_CTRL0 ((0x0030 << 2) + 0xfe090000)
+#define SRAM_RANGE3_WRITE_CTRL0 ((0x0031 << 2) + 0xfe090000)
+#define SRAM_RANGE4_WRITE_CTRL0 ((0x0032 << 2) + 0xfe090000)
+#define SRAM_RANGE5_WRITE_CTRL0 ((0x0033 << 2) + 0xfe090000)
+#define SRAM_RANGE6_WRITE_CTRL0 ((0x0034 << 2) + 0xfe090000)
+#define SRAM_RANGE7_WRITE_CTRL0 ((0x0035 << 2) + 0xfe090000)
+#define SRAM_RANGE8_WRITE_CTRL0 ((0x0036 << 2) + 0xfe090000)
+#define SRAM_RANGE9_WRITE_CTRL0 ((0x0037 << 2) + 0xfe090000)
+#define SRAM_RANGE10_WRITE_CTRL0 ((0x0038 << 2) + 0xfe090000)
+#define SRAM_RANGE11_WRITE_CTRL0 ((0x0039 << 2) + 0xfe090000)
+#define SRAM_RANGE12_WRITE_CTRL0 ((0x003a << 2) + 0xfe090000)
+#define SRAM_RANGE13_WRITE_CTRL0 ((0x003b << 2) + 0xfe090000)
+#define SRAM_RANGE14_WRITE_CTRL0 ((0x003c << 2) + 0xfe090000)
+#define SRAM_RANGE15_WRITE_CTRL0 ((0x003d << 2) + 0xfe090000)
+#define SRAM_RANGE0_READ_CTRL1 ((0x003e << 2) + 0xfe090000)
+#define SRAM_RANGE1_READ_CTRL1 ((0x003f << 2) + 0xfe090000)
+#define SRAM_RANGE2_READ_CTRL1 ((0x0040 << 2) + 0xfe090000)
+#define SRAM_RANGE3_READ_CTRL1 ((0x0041 << 2) + 0xfe090000)
+#define SRAM_RANGE4_READ_CTRL1 ((0x0042 << 2) + 0xfe090000)
+#define SRAM_RANGE5_READ_CTRL1 ((0x0043 << 2) + 0xfe090000)
+#define SRAM_RANGE6_READ_CTRL1 ((0x0044 << 2) + 0xfe090000)
+#define SRAM_RANGE7_READ_CTRL1 ((0x0045 << 2) + 0xfe090000)
+#define SRAM_RANGE8_READ_CTRL1 ((0x0046 << 2) + 0xfe090000)
+#define SRAM_RANGE9_READ_CTRL1 ((0x0047 << 2) + 0xfe090000)
+#define SRAM_RANGE10_READ_CTRL1 ((0x0048 << 2) + 0xfe090000)
+#define SRAM_RANGE11_READ_CTRL1 ((0x0049 << 2) + 0xfe090000)
+#define SRAM_RANGE12_READ_CTRL1 ((0x004a << 2) + 0xfe090000)
+#define SRAM_RANGE13_READ_CTRL1 ((0x004b << 2) + 0xfe090000)
+#define SRAM_RANGE14_READ_CTRL1 ((0x004c << 2) + 0xfe090000)
+#define SRAM_RANGE15_READ_CTRL1 ((0x004d << 2) + 0xfe090000)
+#define SRAM_RANGE0_WRITE_CTRL1 ((0x004e << 2) + 0xfe090000)
+#define SRAM_RANGE1_WRITE_CTRL1 ((0x004f << 2) + 0xfe090000)
+#define SRAM_RANGE2_WRITE_CTRL1 ((0x0050 << 2) + 0xfe090000)
+#define SRAM_RANGE3_WRITE_CTRL1 ((0x0051 << 2) + 0xfe090000)
+#define SRAM_RANGE4_WRITE_CTRL1 ((0x0052 << 2) + 0xfe090000)
+#define SRAM_RANGE5_WRITE_CTRL1 ((0x0053 << 2) + 0xfe090000)
+#define SRAM_RANGE6_WRITE_CTRL1 ((0x0054 << 2) + 0xfe090000)
+#define SRAM_RANGE7_WRITE_CTRL1 ((0x0055 << 2) + 0xfe090000)
+#define SRAM_RANGE8_WRITE_CTRL1 ((0x0056 << 2) + 0xfe090000)
+#define SRAM_RANGE9_WRITE_CTRL1 ((0x0057 << 2) + 0xfe090000)
+#define SRAM_RANGE10_WRITE_CTRL1 ((0x0058 << 2) + 0xfe090000)
+#define SRAM_RANGE11_WRITE_CTRL1 ((0x0059 << 2) + 0xfe090000)
+#define SRAM_RANGE12_WRITE_CTRL1 ((0x005a << 2) + 0xfe090000)
+#define SRAM_RANGE13_WRITE_CTRL1 ((0x005b << 2) + 0xfe090000)
+#define SRAM_RANGE14_WRITE_CTRL1 ((0x005c << 2) + 0xfe090000)
+#define SRAM_RANGE15_WRITE_CTRL1 ((0x005d << 2) + 0xfe090000)
+#define SRAM_GLOBAL_READ_CTRL0 ((0x005e << 2) + 0xfe090000)
+#define SRAM_GLOBAL_READ_CTRL1 ((0x005f << 2) + 0xfe090000)
+#define SRAM_GLOBAL_WRITE_CTRL0 ((0x0060 << 2) + 0xfe090000)
+#define SRAM_GLOBAL_WRITE_CTRL1 ((0x0061 << 2) + 0xfe090000)
+#define SRAM_SEC_CTRL0 ((0x0062 << 2) + 0xfe090000)
+#define SRAM_REG_LOCK0 ((0x0063 << 2) + 0xfe090000)
+#define SRAM_REG_LOCK1 ((0x0064 << 2) + 0xfe090000)
+#define SRAM_REG_LOCK2 ((0x0065 << 2) + 0xfe090000)
+#define SRAM_GLOBAL_READ_CTRL0_LOCK ((0x0066 << 2) + 0xfe090000)
+#define SRAM_GLOBAL_READ_CTRL1_LOCK ((0x0067 << 2) + 0xfe090000)
+#define SRAM_GLOBAL_WRITE_CTRL0_LOCK ((0x0068 << 2) + 0xfe090000)
+#define SRAM_GLOBAL_WRITE_CTRL1_LOCK ((0x0069 << 2) + 0xfe090000)
+#define SRAM_SEC_CTRL0_LOCK ((0x006a << 2) + 0xfe090000)
+//========================================================================
+// MAILBOX
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe006000
+// -----------------------------------------------
+#define MAILBOX_WR_MBOX00 ((0x0000 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX01 ((0x0020 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX02 ((0x0040 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX03 ((0x0060 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX04 ((0x0080 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX05 ((0x00a0 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX06 ((0x00c0 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX07 ((0x00e0 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX08 ((0x0100 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX09 ((0x0120 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX10 ((0x0140 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX11 ((0x0160 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX12 ((0x0180 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX13 ((0x01a0 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX14 ((0x01c0 << 2) + 0xfe006000)
+#define MAILBOX_WR_MBOX15 ((0x01e0 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX00 ((0x0200 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX01 ((0x0220 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX02 ((0x0240 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX03 ((0x0260 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX04 ((0x0280 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX05 ((0x02a0 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX06 ((0x02c0 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX07 ((0x02e0 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX08 ((0x0300 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX09 ((0x0320 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX10 ((0x0340 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX11 ((0x0360 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX12 ((0x0380 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX13 ((0x03a0 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX14 ((0x03c0 << 2) + 0xfe006000)
+#define MAILBOX_RD_MBOX15 ((0x03e0 << 2) + 0xfe006000)
+#define MAILBOX_LOCK_BIT0 ((0x0400 << 2) + 0xfe006000)
+#define MAILBOX_LOCK_BIT1 ((0x0401 << 2) + 0xfe006000)
+#define MAILBOX_PROT_BIT0 ((0x0402 << 2) + 0xfe006000)
+#define MAILBOX_PROT_BIT1 ((0x0403 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_IRQA_CLR ((0x0404 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_IRQB_CLR ((0x0405 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_IRQC_CLR ((0x0406 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_IRQD_CLR ((0x0407 << 2) + 0xfe006000)
+#define MAILBOX_IRQA_MASK ((0x0408 << 2) + 0xfe006000)
+#define MAILBOX_IRQB_MASK ((0x0409 << 2) + 0xfe006000)
+#define MAILBOX_IRQC_MASK ((0x040a << 2) + 0xfe006000)
+#define MAILBOX_IRQD_MASK ((0x040b << 2) + 0xfe006000)
+#define MAILBOX_IRQ_TYPE ((0x040c << 2) + 0xfe006000)
+#define MAILBOX_IRQA_CLR ((0x0410 << 2) + 0xfe006000)
+#define MAILBOX_IRQB_CLR ((0x0411 << 2) + 0xfe006000)
+#define MAILBOX_IRQC_CLR ((0x0412 << 2) + 0xfe006000)
+#define MAILBOX_IRQD_CLR ((0x0413 << 2) + 0xfe006000)
+#define MAILBOX_IRQA_STS ((0x0414 << 2) + 0xfe006000)
+#define MAILBOX_IRQB_STS ((0x0415 << 2) + 0xfe006000)
+#define MAILBOX_IRQC_STS ((0x0416 << 2) + 0xfe006000)
+#define MAILBOX_IRQD_STS ((0x0417 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX00 ((0x0420 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX01 ((0x0421 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX02 ((0x0422 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX03 ((0x0423 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX04 ((0x0424 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX05 ((0x0425 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX06 ((0x0426 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX07 ((0x0427 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX08 ((0x0428 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX09 ((0x0429 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX10 ((0x042a << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX11 ((0x042b << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX12 ((0x042c << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX13 ((0x042d << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX14 ((0x042e << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX15 ((0x042f << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX00 ((0x0430 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX01 ((0x0431 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX02 ((0x0432 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX03 ((0x0433 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX04 ((0x0434 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX05 ((0x0435 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX06 ((0x0436 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX07 ((0x0437 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX08 ((0x0438 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX09 ((0x0439 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX10 ((0x043a << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX11 ((0x043b << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX12 ((0x043c << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX13 ((0x043d << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX14 ((0x043e << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX15 ((0x043f << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX00 ((0x0440 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX01 ((0x0441 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX02 ((0x0442 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX03 ((0x0443 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX04 ((0x0444 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX05 ((0x0445 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX06 ((0x0446 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX07 ((0x0447 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX08 ((0x0448 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX09 ((0x0449 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX10 ((0x044a << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX11 ((0x044b << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX12 ((0x044c << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX13 ((0x044d << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX14 ((0x044e << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX15 ((0x044f << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX00 ((0x0450 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX01 ((0x0451 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX02 ((0x0452 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX03 ((0x0453 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX04 ((0x0454 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX05 ((0x0455 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX06 ((0x0456 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX07 ((0x0457 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX08 ((0x0458 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX09 ((0x0459 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX10 ((0x045a << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX11 ((0x045b << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX12 ((0x045c << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX13 ((0x045d << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX14 ((0x045e << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX15 ((0x045f << 2) + 0xfe006000)
+//========================================================================
+// IRQ_CTRL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe00a000
+// -----------------------------------------------
+#define IRQCTRL_IRQ_INV0 ((0x0000 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV1 ((0x0001 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV2 ((0x0002 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV3 ((0x0003 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV4 ((0x0004 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV5 ((0x0005 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV6 ((0x0006 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV7 ((0x0007 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK0_GIC ((0x0010 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK1_GIC ((0x0011 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK2_GIC ((0x0012 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK3_GIC ((0x0013 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK4_GIC ((0x0014 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK5_GIC ((0x0015 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK6_GIC ((0x0016 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK7_GIC ((0x0017 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK0_DSP ((0x0020 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK1_DSP ((0x0021 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK2_DSP ((0x0022 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK3_DSP ((0x0023 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK4_DSP ((0x0024 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK5_DSP ((0x0025 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK6_DSP ((0x0026 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK7_DSP ((0x0027 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK0_PWRCTRL ((0x0030 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK1_PWRCTRL ((0x0031 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK2_PWRCTRL ((0x0032 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK3_PWRCTRL ((0x0033 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK4_PWRCTRL ((0x0034 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK5_PWRCTRL ((0x0035 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK6_PWRCTRL ((0x0036 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK7_PWRCTRL ((0x0037 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK0_AOCPU ((0x0040 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK1_AOCPU ((0x0041 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK2_AOCPU ((0x0042 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK3_AOCPU ((0x0043 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK4_AOCPU ((0x0044 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK5_AOCPU ((0x0045 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK6_AOCPU ((0x0046 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK7_AOCPU ((0x0047 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE0 ((0x0050 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE1 ((0x0051 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE2 ((0x0052 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE3 ((0x0053 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE4 ((0x0054 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE5 ((0x0055 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE6 ((0x0056 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE7 ((0x0057 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH0 ((0x0060 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH1 ((0x0061 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH2 ((0x0062 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH3 ((0x0063 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH4 ((0x0064 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH5 ((0x0065 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH6 ((0x0066 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH7 ((0x0067 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR0 ((0x0070 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR1 ((0x0071 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR2 ((0x0072 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR3 ((0x0073 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR4 ((0x0074 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR5 ((0x0075 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR6 ((0x0076 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR7 ((0x0077 << 2) + 0xfe00a000)
+#define IRQCTRL_LOCK_BIT ((0x0080 << 2) + 0xfe00a000)
+#define IRQCTRL_PROT_BIT ((0x0081 << 2) + 0xfe00a000)
+//========================================================================
+// RESET_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe002000
+// -----------------------------------------------
+#define RESETCTRL_RESET0 ((0x0000 << 2) + 0xfe002000)
+#define RESETCTRL_RESET1 ((0x0001 << 2) + 0xfe002000)
+#define RESETCTRL_RESET2 ((0x0002 << 2) + 0xfe002000)
+#define RESETCTRL_RESET3 ((0x0003 << 2) + 0xfe002000)
+#define RESETCTRL_RESET4 ((0x0004 << 2) + 0xfe002000)
+#define RESETCTRL_RESET5 ((0x0005 << 2) + 0xfe002000)
+#define RESETCTRL_RESET0_LEVEL ((0x0010 << 2) + 0xfe002000)
+#define RESETCTRL_RESET1_LEVEL ((0x0011 << 2) + 0xfe002000)
+#define RESETCTRL_RESET2_LEVEL ((0x0012 << 2) + 0xfe002000)
+#define RESETCTRL_RESET3_LEVEL ((0x0013 << 2) + 0xfe002000)
+#define RESETCTRL_RESET4_LEVEL ((0x0014 << 2) + 0xfe002000)
+#define RESETCTRL_RESET5_LEVEL ((0x0015 << 2) + 0xfe002000)
+#define RESETCTRL_RESET0_MASK ((0x0020 << 2) + 0xfe002000)
+#define RESETCTRL_RESET1_MASK ((0x0021 << 2) + 0xfe002000)
+#define RESETCTRL_RESET2_MASK ((0x0022 << 2) + 0xfe002000)
+#define RESETCTRL_RESET3_MASK ((0x0023 << 2) + 0xfe002000)
+#define RESETCTRL_RESET4_MASK ((0x0024 << 2) + 0xfe002000)
+#define RESETCTRL_RESET5_MASK ((0x0025 << 2) + 0xfe002000)
+#define RESETCTRL_RESET_HOLD_CYC ((0x0030 << 2) + 0xfe002000)
+#define RESETCTRL_WATCHDOG_CTRL0 ((0x0040 << 2) + 0xfe002000)
+#define RESETCTRL_WATCHDOG_CTRL1 ((0x0041 << 2) + 0xfe002000)
+#define RESETCTRL_WATCHDOG_CNT ((0x0042 << 2) + 0xfe002000)
+#define RESETCTRL_WATCHDOG_CLR ((0x0043 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_WATCHDOG_CTRL0 ((0x0044 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_WATCHDOG_CTRL1 ((0x0045 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_WATCHDOG_CNT ((0x0046 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_WATCHDOG_CLR ((0x0047 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET0 ((0x0050 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET1 ((0x0051 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET0_LEVEL ((0x0060 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET1_LEVEL ((0x0061 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET0_MASK ((0x0070 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET1_MASK ((0x0071 << 2) + 0xfe002000)
+#define RESETCTRL_RESET0_LOCK ((0x0080 << 2) + 0xfe002000)
+#define RESETCTRL_RESET1_LOCK ((0x0081 << 2) + 0xfe002000)
+#define RESETCTRL_RESET2_LOCK ((0x0082 << 2) + 0xfe002000)
+#define RESETCTRL_RESET3_LOCK ((0x0083 << 2) + 0xfe002000)
+#define RESETCTRL_RESET4_LOCK ((0x0084 << 2) + 0xfe002000)
+#define RESETCTRL_RESET5_LOCK ((0x0085 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET0_LOCK ((0x0088 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET1_LOCK ((0x0089 << 2) + 0xfe002000)
+#define RESETCTRL_RESET0_PROT ((0x0090 << 2) + 0xfe002000)
+#define RESETCTRL_RESET1_PROT ((0x0091 << 2) + 0xfe002000)
+#define RESETCTRL_RESET2_PROT ((0x0092 << 2) + 0xfe002000)
+#define RESETCTRL_RESET3_PROT ((0x0093 << 2) + 0xfe002000)
+#define RESETCTRL_RESET4_PROT ((0x0094 << 2) + 0xfe002000)
+#define RESETCTRL_RESET5_PROT ((0x0095 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET0_PROT ((0x0098 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET1_PROT ((0x0099 << 2) + 0xfe002000)
+//========================================================================
+// CPU_CTRL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe00e000
+// -----------------------------------------------
+#define CPUCTRL_SYS_CPU_RESET_CNTL ((0x0050 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CLK_CTRL ((0x0051 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CLK_CTRL1 ((0x0052 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CLK_CTRL2 ((0x0053 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CLK_CTRL3 ((0x0054 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CLK_CTRL4 ((0x0055 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CLK_CTRL5 ((0x0056 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CLK_CTRL6 ((0x0057 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CLK_RESULT ((0x0058 << 2) + 0xfe00e000)
+#define CPUCTRL_ROM_DISABLE ((0x0060 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_POR_CFG0 ((0x0090 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_POR_CFG1 ((0x0091 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG0 ((0x0092 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG1 ((0x0093 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG2 ((0x0094 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG3 ((0x0095 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG4 ((0x0096 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG5 ((0x0097 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG6 ((0x0098 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG7 ((0x0099 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG8 ((0x009a << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG9 ((0x009b << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG10 ((0x009c << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG11 ((0x009d << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG12 ((0x009e << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG13 ((0x009f << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS0 ((0x00a0 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS1 ((0x00a1 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS2 ((0x00a2 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS3 ((0x00a3 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS4 ((0x00a4 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS5 ((0x00a5 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS6 ((0x00a6 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS7 ((0x00a7 << 2) + 0xfe00e000)
+//========================================================================
+// SAR_ADC
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe026000
+// -----------------------------------------------
+#define SAR_ADC_REG0 ((0x0000 << 2) + 0xfe026000)
+#define SAR_ADC_CHAN_LIST ((0x0001 << 2) + 0xfe026000)
+#define SAR_ADC_AVG_CNTL ((0x0002 << 2) + 0xfe026000)
+#define SAR_ADC_REG3 ((0x0003 << 2) + 0xfe026000)
+#define SAR_ADC_DELAY ((0x0004 << 2) + 0xfe026000)
+#define SAR_ADC_LAST_RD ((0x0005 << 2) + 0xfe026000)
+#define SAR_ADC_FIFO_RD ((0x0006 << 2) + 0xfe026000)
+#define SAR_ADC_AUX_SW ((0x0007 << 2) + 0xfe026000)
+#define SAR_ADC_CHAN_10_SW ((0x0008 << 2) + 0xfe026000)
+#define SAR_ADC_DETECT_IDLE_SW ((0x0009 << 2) + 0xfe026000)
+#define SAR_ADC_DELTA_10 ((0x000a << 2) + 0xfe026000)
+#define SAR_ADC_REG11 ((0x000b << 2) + 0xfe026000)
+#define SAR_ADC_REG12 ((0x000c << 2) + 0xfe026000)
+#define SAR_ADC_REG13 ((0x000d << 2) + 0xfe026000)
+#define SAR_ADC_CHNL01 ((0x000e << 2) + 0xfe026000)
+#define SAR_ADC_CHNL23 ((0x000f << 2) + 0xfe026000)
+#define SAR_ADC_CHNL45 ((0x0010 << 2) + 0xfe026000)
+#define SAR_ADC_CHNL67 ((0x0011 << 2) + 0xfe026000)
+//========================================================================
+// ANA_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe008000
+// -----------------------------------------------
+#define ANACTRL_SYSPLL_CTRL0 ((0x0000 << 2) + 0xfe008000)
+#define ANACTRL_SYSPLL_CTRL1 ((0x0001 << 2) + 0xfe008000)
+#define ANACTRL_SYSPLL_CTRL2 ((0x0002 << 2) + 0xfe008000)
+#define ANACTRL_SYSPLL_CTRL3 ((0x0003 << 2) + 0xfe008000)
+#define ANACTRL_SYSPLL_CTRL4 ((0x0004 << 2) + 0xfe008000)
+#define ANACTRL_SYSPLL_CTRL5 ((0x0005 << 2) + 0xfe008000)
+#define ANACTRL_SYSPLL_CTRL6 ((0x0006 << 2) + 0xfe008000)
+#define ANACTRL_SYSPLL_STS ((0x0007 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL0 ((0x0010 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL1 ((0x0011 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL2 ((0x0012 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL3 ((0x0013 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL4 ((0x0014 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL5 ((0x0015 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL6 ((0x0016 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_STS ((0x0017 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL0 ((0x0020 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL1 ((0x0021 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL2 ((0x0022 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL3 ((0x0023 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL4 ((0x0024 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL5 ((0x0025 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL6 ((0x0026 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_STS ((0x0027 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_CTRL0 ((0x0030 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_CTRL1 ((0x0031 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_CTRL2 ((0x0032 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_CTRL3 ((0x0033 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_CTRL4 ((0x0034 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_CTRL5 ((0x0035 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_CTRL6 ((0x0036 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_STS ((0x0037 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL0 ((0x0040 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL1 ((0x0041 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL2 ((0x0042 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL3 ((0x0043 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL4 ((0x0044 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL5 ((0x0045 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL6 ((0x0046 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_STS ((0x0047 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_CTRL0 ((0x0050 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_CTRL1 ((0x0051 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_CTRL2 ((0x0052 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_CTRL3 ((0x0053 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_CTRL4 ((0x0054 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_CTRL5 ((0x0055 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_STS ((0x0056 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL0 ((0x0060 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL1 ((0x0061 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL2 ((0x0062 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL3 ((0x0063 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL4 ((0x0064 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL5 ((0x0065 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL6 ((0x0066 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL7 ((0x0067 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL8 ((0x0068 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_STS ((0x0069 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL0 ((0x0070 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL1 ((0x0071 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL2 ((0x0072 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL3 ((0x0073 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL4 ((0x0074 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL5 ((0x0075 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL6 ((0x0076 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_STS ((0x0077 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_VLOCK ((0x0079 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_CTRL0 ((0x0080 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_CTRL1 ((0x0081 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_CTRL2 ((0x0082 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_CTRL3 ((0x0083 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_CTRL4 ((0x0084 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_CTRL5 ((0x0085 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_STS ((0x0086 << 2) + 0xfe008000)
+#define ANACTRL_MIPICSI_CTRL0 ((0x0090 << 2) + 0xfe008000)
+#define ANACTRL_MIPICSI_CTRL1 ((0x0091 << 2) + 0xfe008000)
+#define ANACTRL_MIPICSI_CTRL2 ((0x0092 << 2) + 0xfe008000)
+#define ANACTRL_MIPICSI_CTRL3 ((0x0093 << 2) + 0xfe008000)
+#define ANACTRL_MIPICSI_CTRL4 ((0x0094 << 2) + 0xfe008000)
+#define ANACTRL_MIPICSI_CTRL5 ((0x0095 << 2) + 0xfe008000)
+#define ANACTRL_MIPIDSI_CTRL0 ((0x00a0 << 2) + 0xfe008000)
+#define ANACTRL_MIPIDSI_CTRL1 ((0x00a1 << 2) + 0xfe008000)
+#define ANACTRL_MIPIDSI_CTRL2 ((0x00a2 << 2) + 0xfe008000)
+#define ANACTRL_MIPIDSI_STS ((0x00a3 << 2) + 0xfe008000)
+#define ANACTRL_VDAC_CTRL0 ((0x00b0 << 2) + 0xfe008000)
+#define ANACTRL_VDAC_CTRL1 ((0x00b1 << 2) + 0xfe008000)
+#define ANACTRL_POR_CTRL ((0x00b6 << 2) + 0xfe008000)
+#define ANACTRL_LOCK_BIT ((0x00b8 << 2) + 0xfe008000)
+#define ANACTRL_PROT_BIT ((0x00b9 << 2) + 0xfe008000)
+//========================================================================
+// Ethernet Phy
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe028000
+// -----------------------------------------------
+#define ETH_PHY_DBG_CTL0 ((0x0000 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_CTL1 ((0x0001 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_CFG0 ((0x0002 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_CFG1 ((0x0003 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_CFG2 ((0x0004 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_CFG3 ((0x0005 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_CFG4 ((0x0006 << 2) + 0xfe028000)
+#define ETH_PLL_STS ((0x0010 << 2) + 0xfe028000)
+#define ETH_PLL_CTL0 ((0x0011 << 2) + 0xfe028000)
+#define ETH_PLL_CTL1 ((0x0012 << 2) + 0xfe028000)
+#define ETH_PLL_CTL2 ((0x0013 << 2) + 0xfe028000)
+#define ETH_PLL_CTL3 ((0x0014 << 2) + 0xfe028000)
+#define ETH_PLL_CTL4 ((0x0015 << 2) + 0xfe028000)
+#define ETH_PLL_CTL5 ((0x0016 << 2) + 0xfe028000)
+#define ETH_PLL_CTL6 ((0x0017 << 2) + 0xfe028000)
+#define ETH_PLL_CTL7 ((0x0018 << 2) + 0xfe028000)
+#define ETH_PHY_CNTL0 ((0x0020 << 2) + 0xfe028000)
+#define ETH_PHY_CNTL1 ((0x0021 << 2) + 0xfe028000)
+#define ETH_PHY_CNTL2 ((0x0022 << 2) + 0xfe028000)
+#define ETH_PHY_CNTL3 ((0x0023 << 2) + 0xfe028000)
+#define ETH_PHY_STS0 ((0x0025 << 2) + 0xfe028000)
+#define ETH_PHY_STS1 ((0x0026 << 2) + 0xfe028000)
+#define ETH_PHY_STS2 ((0x0027 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_REG ((0x0028 << 2) + 0xfe028000)
+//========================================================================
+// Ethernet TOP
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe024000
+// -----------------------------------------------
+#define ETHTOP_CNTL0 ((0x0000 << 2) + 0xfe024000)
+#define ETHTOP_CNTL1 ((0x0001 << 2) + 0xfe024000)
+//========================================================================
+// I2C Slave A
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe064000
+// -----------------------------------------------
+#define I2C_S_A_CONTROL_REG ((0x0000 << 2) + 0xfe064000)
+#define I2C_S_A_SEND_REG ((0x0001 << 2) + 0xfe064000)
+#define I2C_S_A_RECV_REG ((0x0002 << 2) + 0xfe064000)
+#define I2C_S_A_CNTL1_REG ((0x0003 << 2) + 0xfe064000)
+//========================================================================
+// IR RX/TX
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe084000
+// -----------------------------------------------
+#define IRCTRL_IR_DEC_LDR_ACTIVE ((0x0000 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_LDR_IDLE ((0x0001 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_LDR_REPEAT ((0x0002 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_BIT_0 ((0x0003 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_REG0 ((0x0004 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_FRAME ((0x0005 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_STATUS ((0x0006 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_REG1 ((0x0007 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_LDR_ACTIVE ((0x0010 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_LDR_IDLE ((0x0011 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_LDR_REPEAT ((0x0012 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_BIT_0 ((0x0013 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_REG0 ((0x0014 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_FRAME ((0x0015 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_STATUS ((0x0016 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_REG1 ((0x0017 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_REG2 ((0x0018 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_DURATN2 ((0x0019 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_DURATN3 ((0x001a << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_FRAME1 ((0x001b << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_STATUS1 ((0x001c << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_STATUS2 ((0x001d << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_REG3 ((0x001e << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_FRAME_RSV0 ((0x001f << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_FRAME_RSV1 ((0x0020 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_FILTE ((0x0021 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_IRQ_CTL ((0x0022 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_FIFO_CTL ((0x0023 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_WIDTH_NEW ((0x0024 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_REPEAT_DET ((0x0025 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_CNTL0 ((0x0030 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_CNTL1 ((0x0031 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_IIR_THD ((0x0032 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_THD0 ((0x0033 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_THD1 ((0x0034 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_SUM_CNT0 ((0x0035 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_SUM_CNT1 ((0x0036 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_CNT0 ((0x0037 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_CNT1 ((0x0038 << 2) + 0xfe084000)
+#define IRCTRL_IR_BLASTER_ADDR0 ((0x0043 << 2) + 0xfe084000)
+#define IRCTRL_IR_BLASTER_ADDR1 ((0x0044 << 2) + 0xfe084000)
+#define IRCTRL_IR_BLASTER_ADDR2 ((0x0045 << 2) + 0xfe084000)
+#define IRCTRL_IR_BLASTER_ADDR3 ((0x0046 << 2) + 0xfe084000)
+//========================================================================
+// I2C Master A
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe066000
+// -----------------------------------------------
+#define I2C_M_A_CONTROL_REG ((0x0000 << 2) + 0xfe066000)
+#define I2C_M_A_SLAVE_ADDR ((0x0001 << 2) + 0xfe066000)
+#define I2C_M_A_TOKEN_LIST0 ((0x0002 << 2) + 0xfe066000)
+#define I2C_M_A_TOKEN_LIST1 ((0x0003 << 2) + 0xfe066000)
+#define I2C_M_A_WDATA_REG0 ((0x0004 << 2) + 0xfe066000)
+#define I2C_M_A_WDATA_REG1 ((0x0005 << 2) + 0xfe066000)
+#define I2C_M_A_RDATA_REG0 ((0x0006 << 2) + 0xfe066000)
+#define I2C_M_A_RDATA_REG1 ((0x0007 << 2) + 0xfe066000)
+#define I2C_M_A_TIMEOUT_TH ((0x0008 << 2) + 0xfe066000)
+#define I2C_M_A_CNTL_DELY1 ((0x0009 << 2) + 0xfe066000)
+#define I2C_M_A_CNTL_DELY2 ((0x000a << 2) + 0xfe066000)
+#define I2C_M_A_LOW_DELY ((0x000b << 2) + 0xfe066000)
+#define I2C_M_A_HIGH_DELY ((0x000c << 2) + 0xfe066000)
+#define I2C_M_A_FIFO_CTRL_REG ((0x000d << 2) + 0xfe066000)
+#define I2C_M_A_STATE_REG ((0x000e << 2) + 0xfe066000)
+//========================================================================
+// I2C Master B
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe068000
+// -----------------------------------------------
+#define I2C_M_B_CONTROL_REG ((0x0000 << 2) + 0xfe068000)
+#define I2C_M_B_SLAVE_ADDR ((0x0001 << 2) + 0xfe068000)
+#define I2C_M_B_TOKEN_LIST0 ((0x0002 << 2) + 0xfe068000)
+#define I2C_M_B_TOKEN_LIST1 ((0x0003 << 2) + 0xfe068000)
+#define I2C_M_B_WDATA_REG0 ((0x0004 << 2) + 0xfe068000)
+#define I2C_M_B_WDATA_REG1 ((0x0005 << 2) + 0xfe068000)
+#define I2C_M_B_RDATA_REG0 ((0x0006 << 2) + 0xfe068000)
+#define I2C_M_B_RDATA_REG1 ((0x0007 << 2) + 0xfe068000)
+#define I2C_M_B_TIMEOUT_TH ((0x0008 << 2) + 0xfe068000)
+#define I2C_M_B_CNTL_DELY1 ((0x0009 << 2) + 0xfe068000)
+#define I2C_M_B_CNTL_DELY2 ((0x000a << 2) + 0xfe068000)
+#define I2C_M_B_LOW_DELY ((0x000b << 2) + 0xfe068000)
+#define I2C_M_B_HIGH_DELY ((0x000c << 2) + 0xfe068000)
+#define I2C_M_B_FIFO_CTRL_REG ((0x000d << 2) + 0xfe068000)
+#define I2C_M_B_STATE_REG ((0x000e << 2) + 0xfe068000)
+//========================================================================
+// I2C Master C
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe06a000
+// -----------------------------------------------
+#define I2C_M_C_CONTROL_REG ((0x0000 << 2) + 0xfe06a000)
+#define I2C_M_C_SLAVE_ADDR ((0x0001 << 2) + 0xfe06a000)
+#define I2C_M_C_TOKEN_LIST0 ((0x0002 << 2) + 0xfe06a000)
+#define I2C_M_C_TOKEN_LIST1 ((0x0003 << 2) + 0xfe06a000)
+#define I2C_M_C_WDATA_REG0 ((0x0004 << 2) + 0xfe06a000)
+#define I2C_M_C_WDATA_REG1 ((0x0005 << 2) + 0xfe06a000)
+#define I2C_M_C_RDATA_REG0 ((0x0006 << 2) + 0xfe06a000)
+#define I2C_M_C_RDATA_REG1 ((0x0007 << 2) + 0xfe06a000)
+#define I2C_M_C_TIMEOUT_TH ((0x0008 << 2) + 0xfe06a000)
+#define I2C_M_C_CNTL_DELY1 ((0x0009 << 2) + 0xfe06a000)
+#define I2C_M_C_CNTL_DELY2 ((0x000a << 2) + 0xfe06a000)
+#define I2C_M_C_LOW_DELY ((0x000b << 2) + 0xfe06a000)
+#define I2C_M_C_HIGH_DELY ((0x000c << 2) + 0xfe06a000)
+#define I2C_M_C_FIFO_CTRL_REG ((0x000d << 2) + 0xfe06a000)
+#define I2C_M_C_STATE_REG ((0x000e << 2) + 0xfe06a000)
+//========================================================================
+// I2C Master D
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe06c000
+// -----------------------------------------------
+#define I2C_M_D_CONTROL_REG ((0x0000 << 2) + 0xfe06c000)
+#define I2C_M_D_SLAVE_ADDR ((0x0001 << 2) + 0xfe06c000)
+#define I2C_M_D_TOKEN_LIST0 ((0x0002 << 2) + 0xfe06c000)
+#define I2C_M_D_TOKEN_LIST1 ((0x0003 << 2) + 0xfe06c000)
+#define I2C_M_D_WDATA_REG0 ((0x0004 << 2) + 0xfe06c000)
+#define I2C_M_D_WDATA_REG1 ((0x0005 << 2) + 0xfe06c000)
+#define I2C_M_D_RDATA_REG0 ((0x0006 << 2) + 0xfe06c000)
+#define I2C_M_D_RDATA_REG1 ((0x0007 << 2) + 0xfe06c000)
+#define I2C_M_D_TIMEOUT_TH ((0x0008 << 2) + 0xfe06c000)
+#define I2C_M_D_CNTL_DELY1 ((0x0009 << 2) + 0xfe06c000)
+#define I2C_M_D_CNTL_DELY2 ((0x000a << 2) + 0xfe06c000)
+#define I2C_M_D_LOW_DELY ((0x000b << 2) + 0xfe06c000)
+#define I2C_M_D_HIGH_DELY ((0x000c << 2) + 0xfe06c000)
+#define I2C_M_D_FIFO_CTRL_REG ((0x000d << 2) + 0xfe06c000)
+#define I2C_M_D_STATE_REG ((0x000e << 2) + 0xfe06c000)
+//========================================================================
+// I2C Master E
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe06e000
+// -----------------------------------------------
+#define I2C_M_E_CONTROL_REG ((0x0000 << 2) + 0xfe06e000)
+#define I2C_M_E_SLAVE_ADDR ((0x0001 << 2) + 0xfe06e000)
+#define I2C_M_E_TOKEN_LIST0 ((0x0002 << 2) + 0xfe06e000)
+#define I2C_M_E_TOKEN_LIST1 ((0x0003 << 2) + 0xfe06e000)
+#define I2C_M_E_WDATA_REG0 ((0x0004 << 2) + 0xfe06e000)
+#define I2C_M_E_WDATA_REG1 ((0x0005 << 2) + 0xfe06e000)
+#define I2C_M_E_RDATA_REG0 ((0x0006 << 2) + 0xfe06e000)
+#define I2C_M_E_RDATA_REG1 ((0x0007 << 2) + 0xfe06e000)
+#define I2C_M_E_TIMEOUT_TH ((0x0008 << 2) + 0xfe06e000)
+#define I2C_M_E_CNTL_DELY1 ((0x0009 << 2) + 0xfe06e000)
+#define I2C_M_E_CNTL_DELY2 ((0x000a << 2) + 0xfe06e000)
+#define I2C_M_E_LOW_DELY ((0x000b << 2) + 0xfe06e000)
+#define I2C_M_E_HIGH_DELY ((0x000c << 2) + 0xfe06e000)
+#define I2C_M_E_FIFO_CTRL_REG ((0x000d << 2) + 0xfe06e000)
+#define I2C_M_E_STATE_REG ((0x000e << 2) + 0xfe06e000)
+//========================================================================
+// I2C Master F
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe070000
+// -----------------------------------------------
+#define I2C_M_F_CONTROL_REG ((0x0000 << 2) + 0xfe070000)
+#define I2C_M_F_SLAVE_ADDR ((0x0001 << 2) + 0xfe070000)
+#define I2C_M_F_TOKEN_LIST0 ((0x0002 << 2) + 0xfe070000)
+#define I2C_M_F_TOKEN_LIST1 ((0x0003 << 2) + 0xfe070000)
+#define I2C_M_F_WDATA_REG0 ((0x0004 << 2) + 0xfe070000)
+#define I2C_M_F_WDATA_REG1 ((0x0005 << 2) + 0xfe070000)
+#define I2C_M_F_RDATA_REG0 ((0x0006 << 2) + 0xfe070000)
+#define I2C_M_F_RDATA_REG1 ((0x0007 << 2) + 0xfe070000)
+#define I2C_M_F_TIMEOUT_TH ((0x0008 << 2) + 0xfe070000)
+#define I2C_M_F_CNTL_DELY1 ((0x0009 << 2) + 0xfe070000)
+#define I2C_M_F_CNTL_DELY2 ((0x000a << 2) + 0xfe070000)
+#define I2C_M_F_LOW_DELY ((0x000b << 2) + 0xfe070000)
+#define I2C_M_F_HIGH_DELY ((0x000c << 2) + 0xfe070000)
+#define I2C_M_F_FIFO_CTRL_REG ((0x000d << 2) + 0xfe070000)
+#define I2C_M_F_STATE_REG ((0x000e << 2) + 0xfe070000)
+//========================================================================
+// APB0_UART_A - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe078000
+// -----------------------------------------------
+#define UART_A_WFIFO ((0x0000 << 2) + 0xfe078000)
+#define UART_A_RFIFO ((0x0001 << 2) + 0xfe078000)
+#define UART_A_CONTROL ((0x0002 << 2) + 0xfe078000)
+#define UART_A_STATUS ((0x0003 << 2) + 0xfe078000)
+#define UART_A_MISC ((0x0004 << 2) + 0xfe078000)
+#define UART_A_REG5 ((0x0005 << 2) + 0xfe078000)
+//========================================================================
+// APB0_UART_B - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe07a000
+// -----------------------------------------------
+#define UART_B_WFIFO ((0x0000 << 2) + 0xfe07a000)
+#define UART_B_RFIFO ((0x0001 << 2) + 0xfe07a000)
+#define UART_B_CONTROL ((0x0002 << 2) + 0xfe07a000)
+#define UART_B_STATUS ((0x0003 << 2) + 0xfe07a000)
+#define UART_B_MISC ((0x0004 << 2) + 0xfe07a000)
+#define UART_B_REG5 ((0x0005 << 2) + 0xfe07a000)
+//========================================================================
+// APB0_UART_C - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe07c000
+// -----------------------------------------------
+#define UART_C_WFIFO ((0x0000 << 2) + 0xfe07c000)
+#define UART_C_RFIFO ((0x0001 << 2) + 0xfe07c000)
+#define UART_C_CONTROL ((0x0002 << 2) + 0xfe07c000)
+#define UART_C_STATUS ((0x0003 << 2) + 0xfe07c000)
+#define UART_C_MISC ((0x0004 << 2) + 0xfe07c000)
+#define UART_C_REG5 ((0x0005 << 2) + 0xfe07c000)
+//========================================================================
+// APB0_UART_D - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe07e000
+// -----------------------------------------------
+#define UART_D_WFIFO ((0x0000 << 2) + 0xfe07e000)
+#define UART_D_RFIFO ((0x0001 << 2) + 0xfe07e000)
+#define UART_D_CONTROL ((0x0002 << 2) + 0xfe07e000)
+#define UART_D_STATUS ((0x0003 << 2) + 0xfe07e000)
+#define UART_D_MISC ((0x0004 << 2) + 0xfe07e000)
+#define UART_D_REG5 ((0x0005 << 2) + 0xfe07e000)
+//========================================================================
+// APB0_UART_E - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe080000
+// -----------------------------------------------
+#define UART_E_WFIFO ((0x0000 << 2) + 0xfe080000)
+#define UART_E_RFIFO ((0x0001 << 2) + 0xfe080000)
+#define UART_E_CONTROL ((0x0002 << 2) + 0xfe080000)
+#define UART_E_STATUS ((0x0003 << 2) + 0xfe080000)
+#define UART_E_MISC ((0x0004 << 2) + 0xfe080000)
+#define UART_E_REG5 ((0x0005 << 2) + 0xfe080000)
+//========================================================================
+// PWM_AB - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe058000
+// -----------------------------------------------
+#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe058000)
+#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe058000)
+#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe058000)
+#define PWMAB_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe058000)
+#define PWMAB_TIME_AB ((0x0004 << 2) + 0xfe058000)
+#define PWMAB_A2 ((0x0005 << 2) + 0xfe058000)
+#define PWMAB_B2 ((0x0006 << 2) + 0xfe058000)
+#define PWMAB_BLINK_AB ((0x0007 << 2) + 0xfe058000)
+#define PWMAB_LOCK_AB ((0x0008 << 2) + 0xfe058000)
+//========================================================================
+// PWM_CD - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe05a000
+// -----------------------------------------------
+#define PWMCD_PWM_A ((0x0000 << 2) + 0xfe05a000)
+#define PWMCD_PWM_B ((0x0001 << 2) + 0xfe05a000)
+#define PWMCD_MISC_REG_AB ((0x0002 << 2) + 0xfe05a000)
+#define PWMCD_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe05a000)
+#define PWMCD_TIME_AB ((0x0004 << 2) + 0xfe05a000)
+#define PWMCD_A2 ((0x0005 << 2) + 0xfe05a000)
+#define PWMCD_B2 ((0x0006 << 2) + 0xfe05a000)
+#define PWMCD_BLINK_AB ((0x0007 << 2) + 0xfe05a000)
+#define PWMCD_LOCK_AB ((0x0008 << 2) + 0xfe05a000)
+//========================================================================
+// PWM_EF - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe05c000
+// -----------------------------------------------
+#define PWMEF_PWM_A ((0x0000 << 2) + 0xfe05c000)
+#define PWMEF_PWM_B ((0x0001 << 2) + 0xfe05c000)
+#define PWMEF_MISC_REG_AB ((0x0002 << 2) + 0xfe05c000)
+#define PWMEF_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe05c000)
+#define PWMEF_TIME_AB ((0x0004 << 2) + 0xfe05c000)
+#define PWMEF_A2 ((0x0005 << 2) + 0xfe05c000)
+#define PWMEF_B2 ((0x0006 << 2) + 0xfe05c000)
+#define PWMEF_BLINK_AB ((0x0007 << 2) + 0xfe05c000)
+#define PWMEF_LOCK_AB ((0x0008 << 2) + 0xfe05c000)
+//========================================================================
+// PWM_GH - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe05e000
+// -----------------------------------------------
+#define PWMGH_PWM_A ((0x0000 << 2) + 0xfe05e000)
+#define PWMGH_PWM_B ((0x0001 << 2) + 0xfe05e000)
+#define PWMGH_MISC_REG_AB ((0x0002 << 2) + 0xfe05e000)
+#define PWMGH_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe05e000)
+#define PWMGH_TIME_AB ((0x0004 << 2) + 0xfe05e000)
+#define PWMGH_A2 ((0x0005 << 2) + 0xfe05e000)
+#define PWMGH_B2 ((0x0006 << 2) + 0xfe05e000)
+#define PWMGH_BLINK_AB ((0x0007 << 2) + 0xfe05e000)
+#define PWMGH_LOCK_AB ((0x0008 << 2) + 0xfe05e000)
+//========================================================================
+// PWM_IJ - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe060000
+// -----------------------------------------------
+#define PWMIJ_PWM_A ((0x0000 << 2) + 0xfe060000)
+#define PWMIJ_PWM_B ((0x0001 << 2) + 0xfe060000)
+#define PWMIJ_MISC_REG_AB ((0x0002 << 2) + 0xfe060000)
+#define PWMIJ_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe060000)
+#define PWMIJ_TIME_AB ((0x0004 << 2) + 0xfe060000)
+#define PWMIJ_A2 ((0x0005 << 2) + 0xfe060000)
+#define PWMIJ_B2 ((0x0006 << 2) + 0xfe060000)
+#define PWMIJ_BLINK_AB ((0x0007 << 2) + 0xfe060000)
+#define PWMIJ_LOCK_AB ((0x0008 << 2) + 0xfe060000)
+//========================================================================
+// SPICC_0
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe050000
+// -----------------------------------------------
+#define SPICC0_RXDATA ((0x0000 << 2) + 0xfe050000)
+#define SPICC0_TXDATA ((0x0001 << 2) + 0xfe050000)
+#define SPICC0_CONREG ((0x0002 << 2) + 0xfe050000)
+#define SPICC0_INTREG ((0x0003 << 2) + 0xfe050000)
+#define SPICC0_DMAREG ((0x0004 << 2) + 0xfe050000)
+#define SPICC0_STATREG ((0x0005 << 2) + 0xfe050000)
+#define SPICC0_PERIODREG ((0x0006 << 2) + 0xfe050000)
+#define SPICC0_TESTREG ((0x0007 << 2) + 0xfe050000)
+#define SPICC0_DRADDR ((0x0008 << 2) + 0xfe050000)
+#define SPICC0_DWADDR ((0x0009 << 2) + 0xfe050000)
+#define SPICC0_LD_CNTL0 ((0x000a << 2) + 0xfe050000)
+#define SPICC0_LD_CNTL1 ((0x000b << 2) + 0xfe050000)
+#define SPICC0_LD_RADDR ((0x000c << 2) + 0xfe050000)
+#define SPICC0_LD_WADDR ((0x000d << 2) + 0xfe050000)
+#define SPICC0_ENHANCE_CNTL ((0x000e << 2) + 0xfe050000)
+#define SPICC0_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe050000)
+#define SPICC0_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe050000)
+//========================================================================
+// SPICC_1
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe052000
+// -----------------------------------------------
+#define SPICC1_RXDATA ((0x0000 << 2) + 0xfe052000)
+#define SPICC1_TXDATA ((0x0001 << 2) + 0xfe052000)
+#define SPICC1_CONREG ((0x0002 << 2) + 0xfe052000)
+#define SPICC1_INTREG ((0x0003 << 2) + 0xfe052000)
+#define SPICC1_DMAREG ((0x0004 << 2) + 0xfe052000)
+#define SPICC1_STATREG ((0x0005 << 2) + 0xfe052000)
+#define SPICC1_PERIODREG ((0x0006 << 2) + 0xfe052000)
+#define SPICC1_TESTREG ((0x0007 << 2) + 0xfe052000)
+#define SPICC1_DRADDR ((0x0008 << 2) + 0xfe052000)
+#define SPICC1_DWADDR ((0x0009 << 2) + 0xfe052000)
+#define SPICC1_LD_CNTL0 ((0x000a << 2) + 0xfe052000)
+#define SPICC1_LD_CNTL1 ((0x000b << 2) + 0xfe052000)
+#define SPICC1_LD_RADDR ((0x000c << 2) + 0xfe052000)
+#define SPICC1_LD_WADDR ((0x000d << 2) + 0xfe052000)
+#define SPICC1_ENHANCE_CNTL ((0x000e << 2) + 0xfe052000)
+#define SPICC1_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe052000)
+#define SPICC1_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe052000)
+//========================================================================
+// AIFIFO - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe046000
+// -----------------------------------------------
+#define AIU_AIFIFO_CTRL ((0x0000 << 2) + 0xfe046000)
+#define AIU_AIFIFO_STATUS ((0x0001 << 2) + 0xfe046000)
+#define AIU_AIFIFO_GBIT ((0x0002 << 2) + 0xfe046000)
+#define AIU_AIFIFO_CLB ((0x0003 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_START_PTR ((0x0004 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_CURR_PTR ((0x0005 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_END_PTR ((0x0006 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_BYTES_AVAIL ((0x0007 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_CONTROL ((0x0008 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_MAN_WP ((0x0009 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_MAN_RP ((0x000a << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_LEVEL ((0x000b << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_BUF_CNTL ((0x000c << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_BUF_WRAP_COUNT ((0x000d << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_MEM_CTL ((0x000f << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_CNTL ((0x0010 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_SYNC_0 ((0x0011 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_SYNC_1 ((0x0012 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_0 ((0x0013 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_1 ((0x0014 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_2 ((0x0015 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_3 ((0x0016 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_LENGTH ((0x0017 << 2) + 0xfe046000)
+//========================================================================
+// MSR_CLK - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe048000
+// -----------------------------------------------
+#define MSR_CLK_REG0 ((0x0000 << 2) + 0xfe048000)
+#define MSR_CLK_REG1 ((0x0001 << 2) + 0xfe048000)
+#define MSR_CLK_REG2 ((0x0002 << 2) + 0xfe048000)
+#define MSR_CLK_REG3 ((0x0003 << 2) + 0xfe048000)
+#define MSR_CLK_REG4 ((0x0004 << 2) + 0xfe048000)
+#define MSR_CLK_REG5 ((0x0005 << 2) + 0xfe048000)
+#define MSR_CLK_DUTY ((0x0006 << 2) + 0xfe048000)
+//========================================================================
+// SPIFC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe056000
+// -----------------------------------------------
+#define SPI_FLASH_CMD ((0x0000 << 2) + 0xfe056000)
+ // SPI_FLASH_READ 31
+ // SPI_FLASH_WREN 30
+ // SPI_FLASH_WRDI 29
+ // SPI_FLASH_RDID 28
+ // SPI_FLASH_RDSR 27
+ // SPI_FLASH_WRSR 26
+ // SPI_FLASH_PP 25
+ // SPI_FLASH_SE 24
+ // SPI_FLASH_BE 23
+ // SPI_FLASH_CE 22
+ // SPI_FLASH_DP 21
+ // SPI_FLASH_RES 20
+ // SPI_HPM 19
+ // SPI_FLASH_USR 18
+ // SPI_FLASH_USR_ADDR 15
+ // SPI_FLASH_USR_DUMMY 14
+ // SPI_FLASH_USR_DIN 13
+ // SPI_FLASH_USR_DOUT 12
+ // SPI_FLASH_USR_DUMMY_BLEN 10
+ // SPI_FLASH_USR_CMD 0
+#define SPI_FLASH_ADDR ((0x0001 << 2) + 0xfe056000)
+ // SPI_FLASH_BYTES_LEN 24
+ // SPI_FLASH_ADDR_START 0
+#define SPI_FLASH_CTRL ((0x0002 << 2) + 0xfe056000)
+ // SPI_ENABLE_AHB 17
+ // SPI_SST_AAI 16
+ // SPI_RES_RID 15
+ // SPI_FREAD_DUAL 14
+ // SPI_READ_READ_EN 13
+ // SPI_CLK_DIV0 12
+ // SPI_CLKCNT_N 8
+ // SPI_CLKCNT_H 4
+ // SPI_CLKCNT_L 0
+#define SPI_FLASH_CTRL1 ((0x0003 << 2) + 0xfe056000)
+#define SPI_FLASH_STATUS ((0x0004 << 2) + 0xfe056000)
+#define SPI_FLASH_CTRL2 ((0x0005 << 2) + 0xfe056000)
+#define SPI_FLASH_CLOCK ((0x0006 << 2) + 0xfe056000)
+#define SPI_FLASH_USER ((0x0007 << 2) + 0xfe056000)
+#define SPI_FLASH_USER1 ((0x0008 << 2) + 0xfe056000)
+#define SPI_FLASH_USER2 ((0x0009 << 2) + 0xfe056000)
+#define SPI_FLASH_USER3 ((0x000a << 2) + 0xfe056000)
+#define SPI_FLASH_USER4 ((0x000b << 2) + 0xfe056000)
+#define SPI_FLASH_SLAVE ((0x000c << 2) + 0xfe056000)
+#define SPI_FLASH_SLAVE1 ((0x000d << 2) + 0xfe056000)
+#define SPI_FLASH_SLAVE2 ((0x000e << 2) + 0xfe056000)
+#define SPI_FLASH_SLAVE3 ((0x000f << 2) + 0xfe056000)
+#define SPI_FLASH_C0 ((0x0010 << 2) + 0xfe056000)
+#define SPI_FLASH_C1 ((0x0011 << 2) + 0xfe056000)
+#define SPI_FLASH_C2 ((0x0012 << 2) + 0xfe056000)
+#define SPI_FLASH_C3 ((0x0013 << 2) + 0xfe056000)
+#define SPI_FLASH_C4 ((0x0014 << 2) + 0xfe056000)
+#define SPI_FLASH_C5 ((0x0015 << 2) + 0xfe056000)
+#define SPI_FLASH_C6 ((0x0016 << 2) + 0xfe056000)
+#define SPI_FLASH_C7 ((0x0017 << 2) + 0xfe056000)
+#define SPI_FLASH_B8 ((0x0018 << 2) + 0xfe056000)
+#define SPI_FLASH_B9 ((0x0019 << 2) + 0xfe056000)
+#define SPI_FLASH_B10 ((0x001a << 2) + 0xfe056000)
+#define SPI_FLASH_B11 ((0x001b << 2) + 0xfe056000)
+#define SPI_FLASH_B12 ((0x001c << 2) + 0xfe056000)
+#define SPI_FLASH_B13 ((0x001d << 2) + 0xfe056000)
+#define SPI_FLASH_B14 ((0x001e << 2) + 0xfe056000)
+#define SPI_FLASH_B15 ((0x001f << 2) + 0xfe056000)
+//========================================================================
+// CEC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe044000
+// -----------------------------------------------
+#define CECA_GEN_CNTL ((0x0000 << 2) + 0xfe044000)
+#define CECA_RW_REG ((0x0001 << 2) + 0xfe044000)
+#define CECA_INTR_MASKN ((0x0002 << 2) + 0xfe044000)
+#define CECA_INTR_CLR ((0x0003 << 2) + 0xfe044000)
+#define CECA_INTR_STAT ((0x0004 << 2) + 0xfe044000)
+#define CECB_GEN_CNTL ((0x0010 << 2) + 0xfe044000)
+#define CECB_RW_REG ((0x0011 << 2) + 0xfe044000)
+#define CECB_INTR_MASKN ((0x0012 << 2) + 0xfe044000)
+#define CECB_INTR_CLR ((0x0013 << 2) + 0xfe044000)
+#define CECB_INTR_STAT ((0x0014 << 2) + 0xfe044000)
+//========================================================================
+// SMART CARD - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe038000
+// -----------------------------------------------
+#define SMARTCARD_REG0 ((0x0000 << 2) + 0xfe038000)
+#define SMARTCARD_REG1 ((0x0001 << 2) + 0xfe038000)
+#define SMARTCARD_REG2 ((0x0002 << 2) + 0xfe038000)
+#define SMARTCARD_STATUS ((0x0003 << 2) + 0xfe038000)
+#define SMARTCARD_INTR ((0x0004 << 2) + 0xfe038000)
+#define SMARTCARD_REG5 ((0x0005 << 2) + 0xfe038000)
+#define SMARTCARD_REG6 ((0x0006 << 2) + 0xfe038000)
+#define SMARTCARD_FIFO ((0x0007 << 2) + 0xfe038000)
+#define SMARTCARD_REG8 ((0x0008 << 2) + 0xfe038000)
+//========================================================================
+// CAPU
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe012000
+// -----------------------------------------------
+#define CAPU_ACCESS_EN_AHB_ETH ((0x00c2 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_AHB_USB0 ((0x00c1 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_AHB_USB1 ((0x00c0 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_16M_SLOT0 ((0x00b0 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_256K_SLOT1 ((0x00a1 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_256K_SLOT0 ((0x00a0 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT5 ((0x0085 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT4 ((0x0084 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT3 ((0x0083 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT2 ((0x0082 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT1 ((0x0081 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT0 ((0x0080 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT4F ((0x004f << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT4E ((0x004e << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT4D ((0x004d << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT4C ((0x004c << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT4B ((0x004b << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT4A ((0x004a << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT49 ((0x0049 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT48 ((0x0048 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT47 ((0x0047 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT46 ((0x0046 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT45 ((0x0045 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT44 ((0x0044 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT43 ((0x0043 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT42 ((0x0042 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT41 ((0x0041 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT40 ((0x0040 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT3F ((0x003f << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT3E ((0x003e << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT3D ((0x003d << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT3C ((0x003c << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT3B ((0x003b << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT3A ((0x003a << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT39 ((0x0039 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT38 ((0x0038 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT37 ((0x0037 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT36 ((0x0036 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT35 ((0x0035 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT34 ((0x0034 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT33 ((0x0033 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT32 ((0x0032 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT31 ((0x0031 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT30 ((0x0030 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT2F ((0x002f << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT2E ((0x002e << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT2D ((0x002d << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT2C ((0x002c << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT2B ((0x002b << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT2A ((0x002a << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT29 ((0x0029 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT28 ((0x0028 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT27 ((0x0027 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT26 ((0x0026 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT25 ((0x0025 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT24 ((0x0024 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT23 ((0x0023 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT22 ((0x0022 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT21 ((0x0021 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT20 ((0x0020 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT1F ((0x001f << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT1E ((0x001e << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT1D ((0x001d << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT1C ((0x001c << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT1B ((0x001b << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT1A ((0x001a << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT19 ((0x0019 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT18 ((0x0018 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT17 ((0x0017 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT16 ((0x0016 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT15 ((0x0015 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT14 ((0x0014 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT13 ((0x0013 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT12 ((0x0012 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT11 ((0x0011 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT10 ((0x0010 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT0F ((0x000f << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT0E ((0x000e << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT0D ((0x000d << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT0C ((0x000c << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT0B ((0x000b << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT0A ((0x000a << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT09 ((0x0009 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT08 ((0x0008 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT07 ((0x0007 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT06 ((0x0006 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT05 ((0x0005 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT04 ((0x0004 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT03 ((0x0003 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT02 ((0x0002 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT01 ((0x0001 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT00 ((0x0000 << 2) + 0xfe012000)
+//========================================================================
+// BT656
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe030000
+// -----------------------------------------------
+#define BT_CTRL ((0x0000 << 2) + 0xfe030000)
+ #define BT_SOFT_RESET 31 // Soft reset
+ #define BT_JPEG_START 30
+ #define BT_JPEG_IGNORE_BYTES 18 //20:18
+ #define BT_JPEG_IGNORE_LAST 17
+ #define BT_UPDATE_ST_SEL 16
+ #define BT_COLOR_REPEAT 15
+ #define BT_VIDEO_MODE 13 // 14:13
+ #define BT_AUTO_FMT 12
+ #define BT_PROG_MODE 11
+ #define BT_JPEG_MODE 10
+ #define BT_XCLK27_EN_BIT 9 // 1 : xclk27 is input. 0 : xclk27 is output.
+ #define BT_FID_EN_BIT 8 // 1 : enable use FID port.
+ #define BT_CLK27_SEL_BIT 7 // 1 : external xclk27 0 : internal clk27.
+ #define BT_CLK27_PHASE_BIT 6 // 1 : no inverted 0 : inverted.
+ #define BT_ACE_MODE_BIT 5 // 1 : auto cover error by hardware.
+ #define BT_SLICE_MODE_BIT 4 // 1 : no ancillay flag 0 : with ancillay flag.
+ #define BT_FMT_MODE_BIT 3 // 1 : ntsc 0 : pal.
+ #define BT_REF_MODE_BIT 2 // 1 : from bit stream. 0 : from ports.
+ #define BT_MODE_BIT 1 // 1 : BT656 model 0 : SAA7118 mode.
+ #define BT_EN_BIT 0 // 1 : enable.
+#define BT_VBISTART ((0x0001 << 2) + 0xfe030000)
+#define BT_VBIEND ((0x0002 << 2) + 0xfe030000)
+#define BT_FIELDSADR ((0x0003 << 2) + 0xfe030000)
+#define BT_LINECTRL ((0x0004 << 2) + 0xfe030000)
+#define BT_VIDEOSTART ((0x0005 << 2) + 0xfe030000)
+#define BT_VIDEOEND ((0x0006 << 2) + 0xfe030000)
+#define BT_SLICELINE0 ((0x0007 << 2) + 0xfe030000)
+#define BT_SLICELINE1 ((0x0008 << 2) + 0xfe030000)
+#define BT_PORT_CTRL ((0x0009 << 2) + 0xfe030000)
+ #define BT_HSYNC_PHASE 0
+ #define BT_VSYNC_PHASE 1
+ #define BT_HSYNC_PULSE 2
+ #define BT_VSYNC_PULSE 3
+ #define BT_FID_PHASE 4
+ #define BT_FID_HSVS 5
+ #define BT_IDQ_EN 6
+ #define BT_IDQ_PHASE 7
+ #define BT_D8B 8
+ #define BT_10BTO8B 9
+ #define BT_FID_DELAY 10 //12:10
+ #define BT_VSYNC_DELAY 13 //
+ #define BT_HSYNC_DELAY 16
+ #define BT_FID_HSVS_PCNT 19
+ #define BT_FID_HSVS_VS_RISING 20
+ #define BT_FID_HSVS_VS_FALLING 21
+ #define BT_VREF_FROM_VS_ONLY 22
+ #define BT_PORT_ACTIVE_HMODE 23
+ #define BT_DUAL_EDGE_CLK_EN 24
+ #define BT_CLK_INV_SEL 25
+ #define BT_DATA_ENDIAN 26
+#define BT_SWAP_CTRL ((0x000a << 2) + 0xfe030000)
+#define BT_601_CTRL0 ((0x000e << 2) + 0xfe030000)
+#define BT_601_CTRL1 ((0x000f << 2) + 0xfe030000)
+#define BT_601_CTRL2 ((0x0010 << 2) + 0xfe030000)
+#define BT_601_CTRL3 ((0x0011 << 2) + 0xfe030000)
+#define BT_FIELD_LUMA ((0x0012 << 2) + 0xfe030000)
+#define BT_RAW_CTRL ((0x0013 << 2) + 0xfe030000)
+#define BT_STATUS ((0x0014 << 2) + 0xfe030000)
+#define BT_INT_CTRL ((0x0015 << 2) + 0xfe030000)
+#define BT_VLINE_STATUS ((0x0017 << 2) + 0xfe030000)
+#define BT_ERR_CNT ((0x0019 << 2) + 0xfe030000)
+#define BT_LCNT_STATUS ((0x001a << 2) + 0xfe030000)
+#define BT_PCNT_STATUS ((0x001c << 2) + 0xfe030000)
+#define BT_DELAY_CTRL ((0x001d << 2) + 0xfe030000)
+#define BT_REF_000 ((0x0020 << 2) + 0xfe030000)
+#define BT_REF_001 ((0x0021 << 2) + 0xfe030000)
+#define BT_REF_010 ((0x0022 << 2) + 0xfe030000)
+#define BT_REF_011 ((0x0023 << 2) + 0xfe030000)
+#define BT_REF_100 ((0x0024 << 2) + 0xfe030000)
+#define BT_REF_101 ((0x0025 << 2) + 0xfe030000)
+#define BT_REF_110 ((0x0026 << 2) + 0xfe030000)
+#define BT_REF_111 ((0x0027 << 2) + 0xfe030000)
+//========================================================================
+// PDM
+//========================================================================
+//`include "../audio/rtl/pdm_reg.vh"
+//
+// Reading file: REG_LIST_AUDIO_RTL.h
+//
+//========================================================================
+// AUDIO - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe330000
+// -----------------------------------------------
+#define EE_AUDIO_CLK_GATE_EN0 ((0x0000 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_GATE_EN1 ((0x0001 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_A_CTRL ((0x0002 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_B_CTRL ((0x0003 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_C_CTRL ((0x0004 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_D_CTRL ((0x0005 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_E_CTRL ((0x0006 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_F_CTRL ((0x0007 << 2) + 0xfe330000)
+#define EE_AUDIO_SW_RESET0 ((0x000a << 2) + 0xfe330000)
+#define EE_AUDIO_SW_RESET1 ((0x000b << 2) + 0xfe330000)
+#define EE_AUDIO_CLK81_CTRL ((0x000c << 2) + 0xfe330000)
+#define EE_AUDIO_CLK81_EN ((0x000d << 2) + 0xfe330000)
+#define EE_AUDIO_MST_A_SCLK_CTRL0 ((0x0010 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_A_SCLK_CTRL1 ((0x0011 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_B_SCLK_CTRL0 ((0x0012 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_B_SCLK_CTRL1 ((0x0013 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_C_SCLK_CTRL0 ((0x0014 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_C_SCLK_CTRL1 ((0x0015 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_D_SCLK_CTRL0 ((0x0016 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_D_SCLK_CTRL1 ((0x0017 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_E_SCLK_CTRL0 ((0x0018 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_E_SCLK_CTRL1 ((0x0019 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_F_SCLK_CTRL0 ((0x001a << 2) + 0xfe330000)
+#define EE_AUDIO_MST_F_SCLK_CTRL1 ((0x001b << 2) + 0xfe330000)
+#define EE_AUDIO_MST_DLY_CTRL0 ((0x001c << 2) + 0xfe330000)
+#define EE_AUDIO_MST_DLY_CTRL1 ((0x001d << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMIN_A_CTRL ((0x0020 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMIN_B_CTRL ((0x0021 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMIN_C_CTRL ((0x0022 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMIN_LB_CTRL ((0x0023 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMOUT_A_CTRL ((0x0024 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMOUT_B_CTRL ((0x0025 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMOUT_C_CTRL ((0x0026 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_SPDIFIN_CTRL ((0x0027 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_SPDIFOUT_CTRL ((0x0028 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_RESAMPLEA_CTRL ((0x0029 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_LOCKER_CTRL ((0x002a << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_PDMIN_CTRL0 ((0x002b << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_PDMIN_CTRL1 ((0x002c << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_SPDIFOUT_B_CTRL ((0x002d << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_RESAMPLEB_CTRL ((0x002e << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_SPDIFIN_LB_CTRL ((0x002f << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_EQDRC_CTRL0 ((0x0030 << 2) + 0xfe330000)
+#define EE_AUDIO_VAD_CLK_CTRL ((0x0031 << 2) + 0xfe330000)
+#define EE_AUDIO_EARCTX_CMDC_CLK_CTRL ((0x0032 << 2) + 0xfe330000)
+#define EE_AUDIO_EARCTX_DMAC_CLK_CTRL ((0x0033 << 2) + 0xfe330000)
+#define EE_AUDIO_EARCRX_CMDC_CLK_CTRL ((0x0034 << 2) + 0xfe330000)
+#define EE_AUDIO_EARCRX_DMAC_CLK_CTRL ((0x0035 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_LOCKERB_CTRL ((0x0036 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CTRL0 ((0x0040 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CTRL1 ((0x0041 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_START_ADDR ((0x0042 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_FINISH_ADDR ((0x0043 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_INT_ADDR ((0x0044 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_STATUS1 ((0x0045 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_STATUS2 ((0x0046 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_START_ADDRB ((0x0047 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_FINISH_ADDRB ((0x0048 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_INIT_ADDR ((0x0049 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CTRL2 ((0x004a << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CTRL0 ((0x0050 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CTRL1 ((0x0051 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_START_ADDR ((0x0052 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_FINISH_ADDR ((0x0053 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_INT_ADDR ((0x0054 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_STATUS1 ((0x0055 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_STATUS2 ((0x0056 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_START_ADDRB ((0x0057 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_FINISH_ADDRB ((0x0058 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_INIT_ADDR ((0x0059 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CTRL2 ((0x005a << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CTRL0 ((0x0060 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CTRL1 ((0x0061 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_START_ADDR ((0x0062 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_FINISH_ADDR ((0x0063 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_INT_ADDR ((0x0064 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_STATUS1 ((0x0065 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_STATUS2 ((0x0066 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_START_ADDRB ((0x0067 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_FINISH_ADDRB ((0x0068 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_INIT_ADDR ((0x0069 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CTRL2 ((0x006a << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_CTRL0 ((0x0070 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_CTRL1 ((0x0071 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_START_ADDR ((0x0072 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_FINISH_ADDR ((0x0073 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_INT_ADDR ((0x0074 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_STATUS1 ((0x0075 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_STATUS2 ((0x0076 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_START_ADDRB ((0x0077 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_FINISH_ADDRB ((0x0078 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_INIT_ADDR ((0x0079 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_CTRL2 ((0x007a << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_CTRL0 ((0x0080 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_CTRL1 ((0x0081 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_START_ADDR ((0x0082 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_FINISH_ADDR ((0x0083 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_INT_ADDR ((0x0084 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_STATUS1 ((0x0085 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_STATUS2 ((0x0086 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_START_ADDRB ((0x0087 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_FINISH_ADDRB ((0x0088 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_INIT_ADDR ((0x0089 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_CTRL2 ((0x008a << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_CTRL0 ((0x0090 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_CTRL1 ((0x0091 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_START_ADDR ((0x0092 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_FINISH_ADDR ((0x0093 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_INT_ADDR ((0x0094 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_STATUS1 ((0x0095 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_STATUS2 ((0x0096 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_START_ADDRB ((0x0097 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_FINISH_ADDRB ((0x0098 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_INIT_ADDR ((0x0099 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_CTRL2 ((0x009a << 2) + 0xfe330000)
+#define EE_AUDIO_ARB_CTRL0 ((0x00a0 << 2) + 0xfe330000)
+#define EE_AUDIO_ARB_CTRL1 ((0x00a1 << 2) + 0xfe330000)
+#define EE_AUDIO_ARB_STS ((0x00a8 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CTRL0 ((0x00b0 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CTRL1 ((0x00b1 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CTRL2 ((0x00b2 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CTRL3 ((0x00b3 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_DAT_CH_ID0 ((0x00b4 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_DAT_CH_ID1 ((0x00b5 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_DAT_CH_ID2 ((0x00b6 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_DAT_CH_ID3 ((0x00b7 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_LB_CH_ID0 ((0x00b8 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_LB_CH_ID1 ((0x00b9 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_LB_CH_ID2 ((0x00ba << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_LB_CH_ID3 ((0x00bb << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_STS ((0x00bc << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CHSYNC_CTRL_INSERT ((0x00bd << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CHSYNC_CTRL_ORIG ((0x00be << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_CTRL ((0x00c0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_SWAP0 ((0x00c1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK0 ((0x00c2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK1 ((0x00c3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK2 ((0x00c4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK3 ((0x00c5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_STAT ((0x00c6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE_VAL ((0x00c7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE0 ((0x00c8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE1 ((0x00c9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE2 ((0x00ca << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE3 ((0x00cb << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_CTRL ((0x00d0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_SWAP0 ((0x00d1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK0 ((0x00d2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK1 ((0x00d3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK2 ((0x00d4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK3 ((0x00d5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_STAT ((0x00d6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE_VAL ((0x00d7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE0 ((0x00d8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE1 ((0x00d9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE2 ((0x00da << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE3 ((0x00db << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_CTRL ((0x00e0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_SWAP0 ((0x00e1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK0 ((0x00e2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK1 ((0x00e3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK2 ((0x00e4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK3 ((0x00e5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_STAT ((0x00e6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE_VAL ((0x00e7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE0 ((0x00e8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE1 ((0x00e9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE2 ((0x00ea << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE3 ((0x00eb << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_CTRL ((0x00f0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_SWAP0 ((0x00f1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK0 ((0x00f2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK1 ((0x00f3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK2 ((0x00f4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK3 ((0x00f5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_STAT ((0x00f6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE_VAL ((0x00f7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE0 ((0x00f8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE1 ((0x00f9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE2 ((0x00fa << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE3 ((0x00fb << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL0 ((0x0100 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL1 ((0x0101 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL2 ((0x0102 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL3 ((0x0103 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL4 ((0x0104 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL5 ((0x0105 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL6 ((0x0106 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_STAT0 ((0x0107 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_STAT1 ((0x0108 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_STAT2 ((0x0109 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_MUTE_VAL ((0x010a << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL7 ((0x010b << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_CTRL0 ((0x0110 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_CTRL1 ((0x0111 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_CTRL2 ((0x0112 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_CTRL3 ((0x0113 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_COEF0 ((0x0114 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_COEF1 ((0x0115 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_COEF2 ((0x0116 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_COEF3 ((0x0117 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_COEF4 ((0x0118 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_STATUS1 ((0x0119 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_STAT ((0x0120 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_GAIN0 ((0x0121 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_GAIN1 ((0x0122 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CTRL0 ((0x0123 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CTRL1 ((0x0124 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_PREAMB ((0x0125 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_SWAP ((0x0126 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS0 ((0x0127 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS1 ((0x0128 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS2 ((0x0129 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS3 ((0x012a << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS4 ((0x012b << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS5 ((0x012c << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS6 ((0x012d << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS7 ((0x012e << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS8 ((0x012f << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS9 ((0x0130 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTSA ((0x0131 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTSB ((0x0132 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_MUTE_VAL ((0x0133 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_GAIN2 ((0x0134 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_GAIN3 ((0x0135 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_GAIN_EN ((0x0136 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_GAIN_CTRL ((0x0137 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_CTRL0 ((0x0140 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_CTRL1 ((0x0141 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_SWAP0 ((0x0142 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK0 ((0x0143 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK1 ((0x0144 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK2 ((0x0145 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK3 ((0x0146 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_STAT ((0x0147 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_GAIN0 ((0x0148 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_GAIN1 ((0x0149 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE_VAL ((0x014a << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE0 ((0x014b << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE1 ((0x014c << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE2 ((0x014d << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE3 ((0x014e << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK_VAL ((0x014f << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_CTRL0 ((0x0150 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_CTRL1 ((0x0151 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_SWAP0 ((0x0152 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK0 ((0x0153 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK1 ((0x0154 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK2 ((0x0155 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK3 ((0x0156 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_STAT ((0x0157 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_GAIN0 ((0x0158 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_GAIN1 ((0x0159 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE_VAL ((0x015a << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE0 ((0x015b << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE1 ((0x015c << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE2 ((0x015d << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE3 ((0x015e << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK_VAL ((0x015f << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_CTRL0 ((0x0160 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_CTRL1 ((0x0161 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_SWAP0 ((0x0162 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK0 ((0x0163 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK1 ((0x0164 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK2 ((0x0165 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK3 ((0x0166 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_STAT ((0x0167 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_GAIN0 ((0x0168 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_GAIN1 ((0x0169 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE_VAL ((0x016a << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE0 ((0x016b << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE1 ((0x016c << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE2 ((0x016d << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE3 ((0x016e << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK_VAL ((0x016f << 2) + 0xfe330000)
+//`define EE_AUDIO_POW_DET_CTRL0 10'h180
+//`define EE_AUDIO_POW_DET_CTRL1 10'h181
+//`define EE_AUDIO_POW_DET_TH_HI 10'h182
+//`define EE_AUDIO_POW_DET_TH_LO 10'h183
+//`define EE_AUDIO_POW_DET_VALUE 10'h184
+#define EE_AUDIO_SECURITY_CTRL0 ((0x0190 << 2) + 0xfe330000)
+#define EE_AUDIO_SECURITY_CTRL1 ((0x0191 << 2) + 0xfe330000)
+#define EE_AUDIO_IRQ_FIFO_CNT ((0x0192 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_STAT ((0x01a0 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN0 ((0x01a1 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN1 ((0x01a2 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CTRL0 ((0x01a3 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CTRL1 ((0x01a4 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_PREAMB ((0x01a5 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_SWAP ((0x01a6 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS0 ((0x01a7 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS1 ((0x01a8 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS2 ((0x01a9 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS3 ((0x01aa << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS4 ((0x01ab << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS5 ((0x01ac << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS6 ((0x01ad << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS7 ((0x01ae << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS8 ((0x01af << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS9 ((0x01b0 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTSA ((0x01b1 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTSB ((0x01b2 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_MUTE_VAL ((0x01b3 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN2 ((0x01b4 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN3 ((0x01b5 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN_EN ((0x01b6 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN_CTRL ((0x01b7 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_CTRL0 ((0x01c0 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_CTRL1 ((0x01c1 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_START_ADDR ((0x01c2 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_FINISH_ADDR ((0x01c3 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_INT_ADDR ((0x01c4 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_STATUS1 ((0x01c5 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_STATUS2 ((0x01c6 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_INIT_ADDR ((0x01c7 << 2) + 0xfe330000)
+#define EE_AUDIO_TOACODEC_CTRL0 ((0x01d0 << 2) + 0xfe330000)
+#define EE_AUDIO_TOHDMITX_CTRL0 ((0x01d1 << 2) + 0xfe330000)
+#define EE_AUDIO_TOVAD_CTRL0 ((0x01d2 << 2) + 0xfe330000)
+#define EE_AUDIO_FRATV_CTRL0 ((0x01d3 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_CTRL0 ((0x01e0 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_CTRL1 ((0x01e1 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_CTRL2 ((0x01e2 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_CTRL3 ((0x01e3 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_COEF0 ((0x01e4 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_COEF1 ((0x01e5 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_COEF2 ((0x01e6 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_COEF3 ((0x01e7 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_COEF4 ((0x01e8 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_STATUS1 ((0x01e9 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_LB_CTRL0 ((0x01f0 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_LB_CTRL1 ((0x01f1 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_LB_CTRL6 ((0x01f6 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_LB_STAT0 ((0x01f7 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_LB_STAT1 ((0x01f8 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_LB_MUTE_VAL ((0x01fa << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL0 ((0x0200 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL1 ((0x0201 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL2 ((0x0202 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL3 ((0x0203 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL4 ((0x0204 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL5 ((0x0205 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL6 ((0x0206 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL7 ((0x0207 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_STAT0 ((0x020a << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_STAT1 ((0x020b << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CTRL0 ((0x0210 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CTRL1 ((0x0211 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_START_ADDR ((0x0212 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_FINISH_ADDR ((0x0213 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_INT_ADDR ((0x0214 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_STATUS1 ((0x0215 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_STATUS2 ((0x0216 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_START_ADDRB ((0x0217 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_FINISH_ADDRB ((0x0218 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_INIT_ADDR ((0x0219 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CTRL2 ((0x021a << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_CTRL0 ((0x0220 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_CTRL1 ((0x0221 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_START_ADDR ((0x0222 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_FINISH_ADDR ((0x0223 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_INT_ADDR ((0x0224 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_STATUS1 ((0x0225 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_STATUS2 ((0x0226 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_START_ADDRB ((0x0227 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_FINISH_ADDRB ((0x0228 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_INIT_ADDR ((0x0229 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_CTRL2 ((0x022a << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CTRL0 ((0x0230 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CTRL1 ((0x0231 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CTRL2 ((0x0232 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CTRL3 ((0x0233 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_DAT_CH_ID0 ((0x0234 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_DAT_CH_ID1 ((0x0235 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_DAT_CH_ID2 ((0x0236 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_DAT_CH_ID3 ((0x0237 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_LB_CH_ID0 ((0x0238 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_LB_CH_ID1 ((0x0239 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_LB_CH_ID2 ((0x023a << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_LB_CH_ID3 ((0x023b << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_STS ((0x023c << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CHSYNC_CTRL_INSERT ((0x023d << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CHSYNC_CTRL_ORIG ((0x023e << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CTRL0 ((0x0240 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CTRL1 ((0x0241 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_START_ADDR ((0x0242 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_FINISH_ADDR ((0x0243 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_INT_ADDR ((0x0244 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_STATUS1 ((0x0245 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_STATUS2 ((0x0246 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_START_ADDRB ((0x0247 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_FINISH_ADDRB ((0x0248 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_INIT_ADDR ((0x0249 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CTRL2 ((0x024a << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_CTRL0 ((0x0250 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_CTRL1 ((0x0251 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_START_ADDR ((0x0252 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_FINISH_ADDR ((0x0253 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_INT_ADDR ((0x0254 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_STATUS1 ((0x0255 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_STATUS2 ((0x0256 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_START_ADDRB ((0x0257 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_FINISH_ADDRB ((0x0258 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_INIT_ADDR ((0x0259 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_CTRL2 ((0x025a << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_SWAP1 ((0x0260 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK4 ((0x0261 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK5 ((0x0262 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK6 ((0x0263 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK7 ((0x0264 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE4 ((0x0265 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE5 ((0x0266 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE6 ((0x0267 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE7 ((0x0268 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_SWAP1 ((0x0270 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK4 ((0x0271 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK5 ((0x0272 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK6 ((0x0273 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK7 ((0x0274 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE4 ((0x0275 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE5 ((0x0276 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE6 ((0x0277 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE7 ((0x0278 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_SWAP1 ((0x0280 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK4 ((0x0281 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK5 ((0x0282 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK6 ((0x0283 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK7 ((0x0284 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE4 ((0x0285 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE5 ((0x0286 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE6 ((0x0287 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE7 ((0x0288 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_SWAP1 ((0x0290 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK4 ((0x0291 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK5 ((0x0292 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK6 ((0x0293 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK7 ((0x0294 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE4 ((0x0295 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE5 ((0x0296 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE6 ((0x0297 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE7 ((0x0298 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_CTRL2 ((0x02a0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_SWAP1 ((0x02a1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_GAIN2 ((0x02a2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_GAIN3 ((0x02a3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK4 ((0x02a4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK5 ((0x02a5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK6 ((0x02a6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK7 ((0x02a7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE4 ((0x02a8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE5 ((0x02a9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE6 ((0x02aa << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE7 ((0x02ab << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_GAIN_EN ((0x02ac << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_GAIN_CTRL ((0x02ad << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_CTRL2 ((0x02b0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_SWAP1 ((0x02b1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_GAIN2 ((0x02b2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_GAIN3 ((0x02b3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK4 ((0x02b4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK5 ((0x02b5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK6 ((0x02b6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK7 ((0x02b7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE4 ((0x02b8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE5 ((0x02b9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE6 ((0x02ba << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE7 ((0x02bb << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_GAIN_EN ((0x02bc << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_GAIN_CTRL ((0x02bd << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_CTRL2 ((0x02c0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_SWAP1 ((0x02c1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_GAIN2 ((0x02c2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_GAIN3 ((0x02c3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK4 ((0x02c4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK5 ((0x02c5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK6 ((0x02c6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK7 ((0x02c7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE4 ((0x02c8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE5 ((0x02c9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE6 ((0x02ca << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE7 ((0x02cb << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_GAIN_EN ((0x02cc << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_GAIN_CTRL ((0x02cd << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID0 ((0x0300 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID1 ((0x0301 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID2 ((0x0302 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID3 ((0x0303 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID4 ((0x0304 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID5 ((0x0305 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID6 ((0x0306 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID7 ((0x0307 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHSYNC_CTRL ((0x030f << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID0 ((0x0310 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID1 ((0x0311 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID2 ((0x0312 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID3 ((0x0313 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID4 ((0x0314 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID5 ((0x0315 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID6 ((0x0316 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID7 ((0x0317 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHSYNC_CTRL ((0x031f << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID0 ((0x0320 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID1 ((0x0321 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID2 ((0x0322 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID3 ((0x0323 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID4 ((0x0324 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID5 ((0x0325 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID6 ((0x0326 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID7 ((0x0327 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHSYNC_CTRL ((0x032f << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID0 ((0x0330 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID1 ((0x0331 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID2 ((0x0332 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID3 ((0x0333 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID4 ((0x0334 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID5 ((0x0335 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID6 ((0x0336 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID7 ((0x0337 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHSYNC_CTRL ((0x033f << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID0 ((0x0340 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID1 ((0x0341 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID2 ((0x0342 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID3 ((0x0343 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID4 ((0x0344 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID5 ((0x0345 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID6 ((0x0346 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID7 ((0x0347 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHSYNC_CTRL ((0x034f << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID0 ((0x0350 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID1 ((0x0351 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID2 ((0x0352 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID3 ((0x0353 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID4 ((0x0354 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID5 ((0x0355 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID6 ((0x0356 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID7 ((0x0357 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_CHSYNC_MASK ((0x035e << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHSYNC_CTRL ((0x035f << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID0 ((0x0360 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID1 ((0x0361 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID2 ((0x0362 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID3 ((0x0363 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID4 ((0x0364 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID5 ((0x0365 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID6 ((0x0366 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID7 ((0x0367 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHSYNC_CTRL ((0x036f << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID0 ((0x0370 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID1 ((0x0371 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID2 ((0x0372 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID3 ((0x0373 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID4 ((0x0374 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID5 ((0x0375 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID6 ((0x0376 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID7 ((0x0377 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHSYNC_CTRL ((0x037f << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_STS0 ((0x0380 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_STS1 ((0x0381 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_MASK0 ((0x0382 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_MASK1 ((0x0383 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_MODE0 ((0x0384 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_MODE1 ((0x0385 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_CLR0 ((0x0386 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_CLR1 ((0x0387 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_INV0 ((0x0388 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_INV1 ((0x0389 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL0 ((0x0390 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL1 ((0x0391 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL2 ((0x0392 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL3 ((0x0393 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL4 ((0x0394 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL5 ((0x0395 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL6 ((0x0396 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL7 ((0x0397 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL8 ((0x0398 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL9 ((0x0399 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRLA ((0x039a << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRLB ((0x039b << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRLC ((0x039c << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRLD ((0x039d << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRLE ((0x039e << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRLF ((0x039f << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_PAD_CTRL0 ((0x03a0 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_PAD_CTRL1 ((0x03a1 << 2) + 0xfe330000)
+#define EE_AUDIO_SCLK_PAD_CTRL0 ((0x03a2 << 2) + 0xfe330000)
+#define EE_AUDIO_LRCLK_PAD_CTRL0 ((0x03a3 << 2) + 0xfe330000)
+//========================================================================
+// PDM - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe331000
+// -----------------------------------------------
+#define PDM_CTRL ((0x0000 << 2) + 0xfe331000)
+ //bit 31: PDM enable.
+ //bit 30: invert the PDM_DCLK.
+ //bit 29: output mode: 1: 24bits. 0: 32 bits.
+ //bit 28: bypass mode. 1: bypass all filter. directly output the PDM input to DDR. 0: normal mode.
+ //bit 27~9: not used.
+ //bit 16:. PDM Asynchronous FIFO soft reset. write 1 to soft reset AFIFO.
+ //bit 15:8 PDM channel reset. 0: to reset each PDM channel. 1: normal mode.
+ //bit 7:0. PDM channel enable. each bit for one channel.
+#define PDM_HCIC_CTRL1 ((0x0001 << 2) + 0xfe331000)
+ //bit 31 hcic filter enable. 1 use sinc filter. 0 bypass input to output.
+ //bit 29:24. hcic final gain shift parameter.
+ //bit 23:16 hcic final gain multiplier.
+ //bit 8:4 hcic down sample rate.
+ //bit 3:0 hcic stage number. must be between 3 to 9.
+#define PDM_HCIC_CTRL2 ((0x0002 << 2) + 0xfe331000)
+ //Not used.
+#define PDM_F1_CTRL ((0x0003 << 2) + 0xfe331000)
+ //bit 31 . filter 1 enable.
+ //bit 16:15. f1 round mode. 2'b00 : sign bit at bit 49. 28bits output [49:22] round at bit 21. 32bits output [49:18]. 24bits output [49:26]
+ // 2'b01 : sign bit at bit 50. 28bits output [50:23] round at bit 22. 32bits output [49:18]. 24bits output [49:26]
+ // 2'b10 : sign bit at bit 51. 28bits output [51:24] round at bit 23 32bits output [49:18]. 24bits output [49:26].
+ //bit 15:12. filter 1 down sample rate.
+ //bit 8:0. filter 1 stage number.
+#define PDM_F2_CTRL ((0x0004 << 2) + 0xfe331000)
+ //bit 31 . filter 2 enable.
+ //bit 16:15. f2 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23.
+ //bit 15:12. filter 2 down sample rate.
+ //bit 8:0. filter 2 stage number.
+#define PDM_F3_CTRL ((0x0005 << 2) + 0xfe331000)
+ //bit 31 . filter 3 enable.
+ //bit 16:15. f3 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23.
+ //bit 15:12. filter 3 down sample rate.
+ //bit 8:0. filter 3 stage number.
+#define PDM_HPF_CTRL ((0x0006 << 2) + 0xfe331000)
+ //bit 31 High pass filter enable.
+ //bit 20:16 high pass filter shift steps. 6~19 steps.
+ //bit 15:0 high pass filter output factor.
+#define PDM_CHAN_CTRL ((0x0007 << 2) + 0xfe331000)
+ //bit 31:24. chan3 data sample pointer vs edge of the PDM_DCLK.
+ //bit 23:16 chan2 data sample pointer vs edge of the PDM_DCLK.
+ //bit 15:8. chan1 data sample pointer vs edge of the PDM_DCLK.
+ //bit 7:0 chan0 data sample pointer vs edge of the PDM_DCLK.
+#define PDM_CHAN_CTRL1 ((0x0008 << 2) + 0xfe331000)
+ //bit 31:24. chan7 data sample pointer vs edge of the PDM_DCLK.
+ //bit 23:16 chan6 data sample pointer vs edge of the PDM_DCLK.
+ //bit 15:8. chan5 data sample pointer vs edge of the PDM_DCLK.
+ //bit 7:0 chan4 data sample pointer vs edge of the PDM_DCLK.
+#define PDM_COEFF_ADDR ((0x0009 << 2) + 0xfe331000)
+ // address of the write/read of coeff data.
+#define PDM_COEFF_DATA ((0x000a << 2) + 0xfe331000)
+ //write/read data to coeff memory.
+#define PDM_CLKG_CTRL ((0x000b << 2) + 0xfe331000)
+ // auto clock gating control. 1: disable the clock gating function. the clock will awlays enabled. 0 : use RTL auto clock gating.
+ //31:7 not used.
+ //bit 6 filt_ctrl module auto clock gating control.
+ //bit 5 sinc fifo module auto clock gating control.
+ //bit 4 filter module auto clock gating control.
+ //bit 3 apb module auto clock gating control.
+ //bit 2 coeff memory module auto clock gating control.
+ //bit 1 each channel module auto clock gating control.
+ //bit 0 cts_pdm_clk auto clock gating control.
+#define PDM_STS ((0x000c << 2) + 0xfe331000)
+//bit 1 HPF filter output overflow. means the PCLK is too slow.
+//bit 0 HCIC filter output overflow. means the CTS_PDM_CLK is too slow. can't finished the filter function.
+#define PDM_MUTE_VALUE ((0x000d << 2) + 0xfe331000)
+#define PDM_MASK_NUM ((0x000e << 2) + 0xfe331000)
+//========================================================================
+// EQ DRC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe332000
+// -----------------------------------------------
+#define AED_COEF_RAM_CNTL ((0x0000 << 2) + 0xfe332000)
+#define AED_COEF_RAM_DATA ((0x0001 << 2) + 0xfe332000)
+#define AED_EQ_EN ((0x0002 << 2) + 0xfe332000)
+#define AED_EQ_TAP_CNTL ((0x0003 << 2) + 0xfe332000)
+#define AED_EQ_VOLUME ((0x0004 << 2) + 0xfe332000)
+#define AED_EQ_VOLUME_SLEW_CNT ((0x0005 << 2) + 0xfe332000)
+#define AED_MUTE ((0x0006 << 2) + 0xfe332000)
+#define AED_DRC_CNTL ((0x0007 << 2) + 0xfe332000)
+#define AED_DRC_RMS_COEF0 ((0x0008 << 2) + 0xfe332000)
+#define AED_DRC_RMS_COEF1 ((0x0009 << 2) + 0xfe332000)
+#define AED_DRC_THD0 ((0x000a << 2) + 0xfe332000)
+#define AED_DRC_THD1 ((0x000b << 2) + 0xfe332000)
+#define AED_DRC_THD2 ((0x000c << 2) + 0xfe332000)
+#define AED_DRC_THD3 ((0x000d << 2) + 0xfe332000)
+#define AED_DRC_THD4 ((0x000e << 2) + 0xfe332000)
+#define AED_DRC_K0 ((0x000f << 2) + 0xfe332000)
+#define AED_DRC_K1 ((0x0010 << 2) + 0xfe332000)
+#define AED_DRC_K2 ((0x0011 << 2) + 0xfe332000)
+#define AED_DRC_K3 ((0x0012 << 2) + 0xfe332000)
+#define AED_DRC_K4 ((0x0013 << 2) + 0xfe332000)
+#define AED_DRC_K5 ((0x0014 << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT0 ((0x0015 << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT1 ((0x0016 << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT2 ((0x0017 << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT3 ((0x0018 << 2) + 0xfe332000)
+#define AED_DRC_OFFSET ((0x0019 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF00 ((0x001a << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF01 ((0x001b << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF10 ((0x001c << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF11 ((0x001d << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF20 ((0x001e << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF21 ((0x001f << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF30 ((0x0020 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF31 ((0x0021 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF40 ((0x0022 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF41 ((0x0023 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF50 ((0x0024 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF51 ((0x0025 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF00 ((0x0026 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF01 ((0x0027 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF10 ((0x0028 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF11 ((0x0029 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF20 ((0x002a << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF21 ((0x002b << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF30 ((0x002c << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF31 ((0x002d << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF40 ((0x002e << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF41 ((0x002f << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF50 ((0x0030 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF51 ((0x0031 << 2) + 0xfe332000)
+#define AED_DRC_LOOPBACK_CNTL ((0x0032 << 2) + 0xfe332000)
+#define AED_MDRC_CNTL ((0x0033 << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF00 ((0x0034 << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF01 ((0x0035 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF00 ((0x0036 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF01 ((0x0037 << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF00 ((0x0038 << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF01 ((0x0039 << 2) + 0xfe332000)
+#define AED_MDRC_THD0 ((0x003a << 2) + 0xfe332000)
+#define AED_MDRC_K0 ((0x003b << 2) + 0xfe332000)
+#define AED_MDRC_LOW_GAIN ((0x003c << 2) + 0xfe332000)
+#define AED_MDRC_OFFSET0 ((0x003d << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF10 ((0x003e << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF11 ((0x003f << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF10 ((0x0040 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF11 ((0x0041 << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF10 ((0x0042 << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF11 ((0x0043 << 2) + 0xfe332000)
+#define AED_MDRC_THD1 ((0x0044 << 2) + 0xfe332000)
+#define AED_MDRC_K1 ((0x0045 << 2) + 0xfe332000)
+#define AED_MDRC_OFFSET1 ((0x0046 << 2) + 0xfe332000)
+#define AED_MDRC_MID_GAIN ((0x0047 << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF20 ((0x0048 << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF21 ((0x0049 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF20 ((0x004a << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF21 ((0x004b << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF20 ((0x004c << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF21 ((0x004d << 2) + 0xfe332000)
+#define AED_MDRC_THD2 ((0x004e << 2) + 0xfe332000)
+#define AED_MDRC_K2 ((0x004f << 2) + 0xfe332000)
+#define AED_MDRC_OFFSET2 ((0x0050 << 2) + 0xfe332000)
+#define AED_MDRC_HIGH_GAIN ((0x0051 << 2) + 0xfe332000)
+#define AED_ED_CNTL ((0x0052 << 2) + 0xfe332000)
+#define AED_DC_EN ((0x0053 << 2) + 0xfe332000)
+#define AED_ND_LOW_THD ((0x0054 << 2) + 0xfe332000)
+#define AED_ND_HIGH_THD ((0x0055 << 2) + 0xfe332000)
+#define AED_ND_CNT_THD ((0x0056 << 2) + 0xfe332000)
+#define AED_ND_SUM_NUM ((0x0057 << 2) + 0xfe332000)
+#define AED_ND_CZ_NUM ((0x0058 << 2) + 0xfe332000)
+#define AED_ND_SUM_THD0 ((0x0059 << 2) + 0xfe332000)
+#define AED_ND_SUM_THD1 ((0x005a << 2) + 0xfe332000)
+#define AED_ND_CZ_THD0 ((0x005b << 2) + 0xfe332000)
+#define AED_ND_CZ_THD1 ((0x005c << 2) + 0xfe332000)
+#define AED_ND_COND_CNTL ((0x005d << 2) + 0xfe332000)
+#define AED_ND_RELEASE_COEF0 ((0x005e << 2) + 0xfe332000)
+#define AED_ND_RELEASE_COEF1 ((0x005f << 2) + 0xfe332000)
+#define AED_ND_ATTACK_COEF0 ((0x0060 << 2) + 0xfe332000)
+#define AED_ND_ATTACK_COEF1 ((0x0061 << 2) + 0xfe332000)
+#define AED_ND_CNTL ((0x0062 << 2) + 0xfe332000)
+#define AED_MIX0_LL ((0x0063 << 2) + 0xfe332000)
+#define AED_MIX0_RL ((0x0064 << 2) + 0xfe332000)
+#define AED_MIX0_LR ((0x0065 << 2) + 0xfe332000)
+#define AED_MIX0_RR ((0x0066 << 2) + 0xfe332000)
+#define AED_CLIP_THD ((0x0067 << 2) + 0xfe332000)
+#define AED_CH1_ND_SUM_OUT ((0x0068 << 2) + 0xfe332000)
+#define AED_CH2_ND_SUM_OUT ((0x0069 << 2) + 0xfe332000)
+#define AED_CH1_ND_CZ_OUT ((0x006a << 2) + 0xfe332000)
+#define AED_CH2_ND_CZ_OUT ((0x006b << 2) + 0xfe332000)
+#define AED_NOISE_STATUS ((0x006c << 2) + 0xfe332000)
+#define AED_POW_CURRENT_S0 ((0x006d << 2) + 0xfe332000)
+#define AED_POW_CURRENT_S1 ((0x006e << 2) + 0xfe332000)
+#define AED_POW_CURRENT_S2 ((0x006f << 2) + 0xfe332000)
+#define AED_POW_OUT0 ((0x0070 << 2) + 0xfe332000)
+#define AED_POW_OUT1 ((0x0071 << 2) + 0xfe332000)
+#define AED_POW_OUT2 ((0x0072 << 2) + 0xfe332000)
+#define AED_POW_ADJ_INDEX0 ((0x0073 << 2) + 0xfe332000)
+#define AED_POW_ADJ_INDEX1 ((0x0074 << 2) + 0xfe332000)
+#define AED_POW_ADJ_INDEX2 ((0x0075 << 2) + 0xfe332000)
+#define AED_DRC_GAIN_INDEX0 ((0x0076 << 2) + 0xfe332000)
+#define AED_DRC_GAIN_INDEX1 ((0x0077 << 2) + 0xfe332000)
+#define AED_DRC_GAIN_INDEX2 ((0x0078 << 2) + 0xfe332000)
+#define AED_CH1_VOLUME_STATE ((0x0079 << 2) + 0xfe332000)
+#define AED_CH2_VOLUME_STATE ((0x007a << 2) + 0xfe332000)
+#define AED_CH1_VOLUME_GAIN ((0x007b << 2) + 0xfe332000)
+#define AED_CH2_VOLUME_GAIN ((0x007c << 2) + 0xfe332000)
+#define AED_FULL_POW_CURRENT ((0x007d << 2) + 0xfe332000)
+#define AED_FULL_POW_OUT ((0x007e << 2) + 0xfe332000)
+#define AED_FULL_POW_ADJ ((0x007f << 2) + 0xfe332000)
+#define AED_FULL_DRC_GAIN ((0x0080 << 2) + 0xfe332000)
+#define AED_MASTER_VOLUME_STATE ((0x0081 << 2) + 0xfe332000)
+#define AED_MASTER_VOLUME_GAIN ((0x0082 << 2) + 0xfe332000)
+#define AED_TOP_CTL0 ((0x0083 << 2) + 0xfe332000)
+#define AED_TOP_CTL1 ((0x0084 << 2) + 0xfe332000)
+#define AED_TOP_CTL2 ((0x0085 << 2) + 0xfe332000)
+#define AED_TOP_ST ((0x0086 << 2) + 0xfe332000)
+#define AED_EQDRC_DYNAMIC_CNTL ((0x0090 << 2) + 0xfe332000)
+#define AED_COEF_RAM_CNTL_B ((0x0091 << 2) + 0xfe332000)
+#define AED_COEF_RAM_DATA_B ((0x0092 << 2) + 0xfe332000)
+#define AED_DRC_RMS_COEF0_B ((0x0093 << 2) + 0xfe332000)
+#define AED_DRC_RMS_COEF1_B ((0x0094 << 2) + 0xfe332000)
+#define AED_DRC_THD0_B ((0x0095 << 2) + 0xfe332000)
+#define AED_DRC_THD1_B ((0x0096 << 2) + 0xfe332000)
+#define AED_DRC_THD2_B ((0x0097 << 2) + 0xfe332000)
+#define AED_DRC_THD3_B ((0x0098 << 2) + 0xfe332000)
+#define AED_DRC_THD4_B ((0x0099 << 2) + 0xfe332000)
+#define AED_DRC_K0_B ((0x009a << 2) + 0xfe332000)
+#define AED_DRC_K1_B ((0x009b << 2) + 0xfe332000)
+#define AED_DRC_K2_B ((0x009c << 2) + 0xfe332000)
+#define AED_DRC_K3_B ((0x009d << 2) + 0xfe332000)
+#define AED_DRC_K4_B ((0x009e << 2) + 0xfe332000)
+#define AED_DRC_K5_B ((0x009f << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT0_B ((0x00a0 << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT1_B ((0x00a1 << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT2_B ((0x00a2 << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT3_B ((0x00a3 << 2) + 0xfe332000)
+#define AED_DRC_OFFSET_B ((0x00a4 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF00_B ((0x00a5 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF01_B ((0x00a6 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF10_B ((0x00a7 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF11_B ((0x00a8 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF20_B ((0x00a9 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF21_B ((0x00aa << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF30_B ((0x00ab << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF31_B ((0x00ac << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF40_B ((0x00ad << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF41_B ((0x00ae << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF50_B ((0x00af << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF51_B ((0x00b0 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF00_B ((0x00b1 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF01_B ((0x00b2 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF10_B ((0x00b3 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF11_B ((0x00b4 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF20_B ((0x00b5 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF21_B ((0x00b6 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF30_B ((0x00b7 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF31_B ((0x00b8 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF40_B ((0x00b9 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF41_B ((0x00ba << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF50_B ((0x00bb << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF51_B ((0x00bc << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF00_B ((0x00bd << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF01_B ((0x00be << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF10_B ((0x00bf << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF11_B ((0x00c0 << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF20_B ((0x00c1 << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF21_B ((0x00c2 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF00_B ((0x00c3 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF01_B ((0x00c4 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF10_B ((0x00c5 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF11_B ((0x00c6 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF20_B ((0x00c7 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF21_B ((0x00c8 << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF00_B ((0x00c9 << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF01_B ((0x00ca << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF10_B ((0x00cb << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF11_B ((0x00cc << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF20_B ((0x00cd << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF21_B ((0x00ce << 2) + 0xfe332000)
+#define AED_MDRC_THD0_B ((0x00cf << 2) + 0xfe332000)
+#define AED_MDRC_THD1_B ((0x00d0 << 2) + 0xfe332000)
+#define AED_MDRC_THD2_B ((0x00d1 << 2) + 0xfe332000)
+#define AED_MDRC_K0_B ((0x00d2 << 2) + 0xfe332000)
+#define AED_MDRC_K1_B ((0x00d3 << 2) + 0xfe332000)
+#define AED_MDRC_K2_B ((0x00d4 << 2) + 0xfe332000)
+#define AED_MDRC_OFFSET0_B ((0x00d5 << 2) + 0xfe332000)
+#define AED_MDRC_OFFSET1_B ((0x00d6 << 2) + 0xfe332000)
+#define AED_MDRC_OFFSET2_B ((0x00d7 << 2) + 0xfe332000)
+#define AED_MDRC_LOW_GAIN_B ((0x00d8 << 2) + 0xfe332000)
+#define AED_MDRC_MID_GAIN_B ((0x00d9 << 2) + 0xfe332000)
+#define AED_MDRC_HIGH_GAIN_B ((0x00da << 2) + 0xfe332000)
+#define AED_DRC_CNTL_B ((0x00db << 2) + 0xfe332000)
+#define AED_DRC_LOOPBACK_CNTL_B ((0x00dc << 2) + 0xfe332000)
+#define AED_MDRC_CNTL_B ((0x00dd << 2) + 0xfe332000)
+#define AED_STATUS_REG ((0x00de << 2) + 0xfe332000)
+//========================================================================
+// AUDIO locker - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe331400
+// -----------------------------------------------
+#define AUD_LOCK_EN ((0x0000 << 2) + 0xfe331400)
+#define AUD_LOCK_SW_RESET ((0x0001 << 2) + 0xfe331400)
+#define AUD_LOCK_SW_LATCH ((0x0002 << 2) + 0xfe331400)
+#define AUD_LOCK_HW_LATCH ((0x0003 << 2) + 0xfe331400)
+#define AUD_LOCK_REFCLK_SRC ((0x0004 << 2) + 0xfe331400)
+#define AUD_LOCK_REFCLK_LAT_INT ((0x0005 << 2) + 0xfe331400)
+#define AUD_LOCK_IMCLK_LAT_INT ((0x0006 << 2) + 0xfe331400)
+#define AUD_LOCK_OMCLK_LAT_INT ((0x0007 << 2) + 0xfe331400)
+#define AUD_LOCK_REFCLK_DS_INT ((0x0008 << 2) + 0xfe331400)
+#define AUD_LOCK_IMCLK_DS_INT ((0x0009 << 2) + 0xfe331400)
+#define AUD_LOCK_OMCLK_DS_INT ((0x000a << 2) + 0xfe331400)
+#define AUD_LOCK_INT_CLR ((0x000b << 2) + 0xfe331400)
+#define AUD_LOCK_GCLK_CTRL ((0x000c << 2) + 0xfe331400)
+#define AUD_LOCK_INT_CTRL ((0x000d << 2) + 0xfe331400)
+#define RO_REF2IMCLK_CNT_L ((0x0010 << 2) + 0xfe331400)
+#define RO_REF2IMCLK_CNT_H ((0x0011 << 2) + 0xfe331400)
+#define RO_REF2OMCLK_CNT_L ((0x0012 << 2) + 0xfe331400)
+#define RO_REF2OMCLK_CNT_H ((0x0013 << 2) + 0xfe331400)
+#define RO_IMCLK2REF_CNT_L ((0x0014 << 2) + 0xfe331400)
+#define RO_IMCLK2REF_CNT_H ((0x0015 << 2) + 0xfe331400)
+#define RO_OMCLK2REF_CNT_L ((0x0016 << 2) + 0xfe331400)
+#define RO_OMCLK2REF_CNT_H ((0x0017 << 2) + 0xfe331400)
+#define RO_REFCLK_PKG_CNT ((0x0018 << 2) + 0xfe331400)
+#define RO_IMCLK_PKG_CNT ((0x0019 << 2) + 0xfe331400)
+#define RO_OMCLK_PKG_CNT ((0x001a << 2) + 0xfe331400)
+#define RO_AUD_LOCK_INT_STATUS ((0x001b << 2) + 0xfe331400)
+//========================================================================
+// AUDIO VAD - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe331800
+// -----------------------------------------------
+//
+// Reading file: VAD_REG.h
+//
+#define VAD_TOP_CTRL0 ((0x0000 << 2) + 0xfe331800)
+#define VAD_TOP_CTRL1 ((0x0001 << 2) + 0xfe331800)
+#define VAD_TOP_CTRL2 ((0x0002 << 2) + 0xfe331800)
+#define VAD_FIR_CTRL ((0x0003 << 2) + 0xfe331800)
+#define VAD_FIR_EMP ((0x0004 << 2) + 0xfe331800)
+#define VAD_FIR_COEF0 ((0x0005 << 2) + 0xfe331800)
+#define VAD_FIR_COEF1 ((0x0006 << 2) + 0xfe331800)
+#define VAD_FIR_COEF2 ((0x0007 << 2) + 0xfe331800)
+#define VAD_FIR_COEF3 ((0x0008 << 2) + 0xfe331800)
+#define VAD_FIR_COEF4 ((0x0009 << 2) + 0xfe331800)
+#define VAD_FIR_COEF5 ((0x000a << 2) + 0xfe331800)
+#define VAD_FIR_COEF6 ((0x000b << 2) + 0xfe331800)
+#define VAD_FIR_COEF7 ((0x000c << 2) + 0xfe331800)
+#define VAD_FIR_COEF8 ((0x000d << 2) + 0xfe331800)
+#define VAD_FIR_COEF9 ((0x000e << 2) + 0xfe331800)
+#define VAD_FIR_COEF10 ((0x000f << 2) + 0xfe331800)
+#define VAD_FIR_COEF11 ((0x0010 << 2) + 0xfe331800)
+#define VAD_FIR_COEF12 ((0x0011 << 2) + 0xfe331800)
+#define VAD_FRAME_CTRL0 ((0x0012 << 2) + 0xfe331800)
+#define VAD_FRAME_CTRL1 ((0x0013 << 2) + 0xfe331800)
+#define VAD_FRAME_CTRL2 ((0x0014 << 2) + 0xfe331800)
+#define VAD_CEP_CTRL0 ((0x0015 << 2) + 0xfe331800)
+#define VAD_CEP_CTRL1 ((0x0016 << 2) + 0xfe331800)
+#define VAD_CEP_CTRL2 ((0x0017 << 2) + 0xfe331800)
+#define VAD_CEP_CTRL3 ((0x0018 << 2) + 0xfe331800)
+#define VAD_CEP_CTRL4 ((0x0019 << 2) + 0xfe331800)
+#define VAD_CEP_CTRL5 ((0x001a << 2) + 0xfe331800)
+#define VAD_DEC_CTRL ((0x001b << 2) + 0xfe331800)
+#define VAD_TOP_STS0 ((0x001c << 2) + 0xfe331800)
+#define VAD_TOP_STS1 ((0x001d << 2) + 0xfe331800)
+#define VAD_TOP_STS2 ((0x001e << 2) + 0xfe331800)
+#define VAD_FIR_STS0 ((0x001f << 2) + 0xfe331800)
+#define VAD_FIR_STS1 ((0x0020 << 2) + 0xfe331800)
+#define VAD_POW_STS0 ((0x0021 << 2) + 0xfe331800)
+#define VAD_POW_STS1 ((0x0022 << 2) + 0xfe331800)
+#define VAD_POW_STS2 ((0x0023 << 2) + 0xfe331800)
+#define VAD_FFT_STS0 ((0x0024 << 2) + 0xfe331800)
+#define VAD_FFT_STS1 ((0x0025 << 2) + 0xfe331800)
+#define VAD_SPE_STS0 ((0x0026 << 2) + 0xfe331800)
+#define VAD_SPE_STS1 ((0x0027 << 2) + 0xfe331800)
+#define VAD_SPE_STS2 ((0x0028 << 2) + 0xfe331800)
+#define VAD_SPE_STS3 ((0x0029 << 2) + 0xfe331800)
+#define VAD_DEC_STS0 ((0x002a << 2) + 0xfe331800)
+#define VAD_DEC_STS1 ((0x002b << 2) + 0xfe331800)
+#define VAD_LUT_CTRL ((0x002c << 2) + 0xfe331800)
+#define VAD_LUT_WR ((0x002d << 2) + 0xfe331800)
+#define VAD_LUT_RD ((0x002e << 2) + 0xfe331800)
+#define VAD_IN_SEL0 ((0x002f << 2) + 0xfe331800)
+#define VAD_IN_SEL1 ((0x0030 << 2) + 0xfe331800)
+#define VAD_TO_DDR ((0x0031 << 2) + 0xfe331800)
+#define VAD_SYNC_CTRL0 ((0x0032 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID0 ((0x0033 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID1 ((0x0034 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID2 ((0x0035 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID3 ((0x0036 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID4 ((0x0037 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID5 ((0x0038 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID6 ((0x0039 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID7 ((0x003a << 2) + 0xfe331800)
+//
+// Closing file: VAD_REG.h
+//
+//========================================================================
+// AUDIO RESAMPLEA - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe331c00
+// -----------------------------------------------
+//
+// Reading file: RESAMPLE.h
+//
+#define AUDIO_RSAMP_CTRL0 ((0x0000 << 2) + 0xfe331c00)
+//Bit 31:3 reserved
+//Bit 2 reg_lock_rst //unsigned , default =0;
+//Bit 1 reg_rsamp_rst //unsigned , default =0;
+//Bit 0 reg_sw_rst //unsigned , default =0;
+#define AUDIO_RSAMP_CTRL1 ((0x0001 << 2) + 0xfe331c00)
+//Bit 31:27 reserved //unsigned , default =0;
+//Bit 26 reg_watchdog_en //unsigned , default =0;
+//Bit 25 reg_rsamp_rst_sel //unsigned , default =0;
+//Bit 24 reg_module_bypas //unsigned , default =0;
+//Bit 23:18 reg_gclk_ctrl //unsigned , default =0;
+//Bit 17:13 reg_in_msb //unsigned , default =23;
+//Bit 12 reg_output_en //unsigned , default =0;
+//Bit 11 reg_rsamp_en //unsigned , default =0;
+//Bit 10 reg_filt_en //unsigned , default =0;
+//Bit 9 reg_post_en //unsigned , default =0;
+//Bit 8 reg_inp_mux_mode //unsigned , default =0;
+//Bit 7:4 reserved //unsigned , default =2;
+//Bit 3:0 reg_inp_mux //unsigned , default =0;
+#define AUDIO_RSAMP_CTRL2 ((0x0002 << 2) + 0xfe331c00)
+//Bit 31:30 reserved //unsigned , default =0;
+//Bit 29:24 reg_chx_size //unsigned , default =2;
+//Bit 23:18 reserved //unsigned , default =0;
+//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4
+//Bit 15:8 reg_filt_tap //unsigned , default =63;
+//Bit 7:0 reg_intp_tap //unsigned , default =63;
+#define AUDIO_RSAMP_PHSINIT ((0x0003 << 2) + 0xfe331c00)
+//Bit 31:28 reserved //unsigned , default = 0;
+//Bit 27:0 reg_init_phs //unsigned , default = 0;
+#define AUDIO_RSAMP_PHSSTEP ((0x0004 << 2) + 0xfe331c00)
+//Bit 31 reserved //unsigned , default = 0;
+//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000
+#define AUDIO_RSAMP_SHIFT ((0x0005 << 2) + 0xfe331c00)
+//Bit 31:24 reg_rsft_iir //unsigned , default = 23;
+//Bit 23:16 reg_rsft_blnd //unsigned , default = 21;
+//Bit 15:8 reg_rsft_sinc //unsigned , default = 31;
+//Bit 7:0 reg_rsft_aa //unsigned , default = 31;
+#define AUDIO_RSAMP_ADJ_CTRL0 ((0x0006 << 2) + 0xfe331c00)
+//Bit 31:3 reserved //unsigned
+//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0;
+//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0;
+//Bit 0 reg_rsamp_adj_en //unsigned , default = 0;
+#define AUDIO_RSAMP_ADJ_CTRL1 ((0x0007 << 2) + 0xfe331c00)
+//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8;
+//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768;
+#define AUDIO_RSAMP_ADJ_SFT ((0x0008 << 2) + 0xfe331c00)
+//Bit 31:30 reserved //unsigned , default = 0;
+//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0;
+//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9;
+//Bit 23:21 reserved //unsigned , default = 0;
+//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1;
+//Bit 15:13 reserved //unsigned , default = 0;
+//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6;
+//Bit 7:6 reserved //unsigned , default = 0;
+//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12;
+#define AUDIO_RSAMP_ADJ_IDET_LEN ((0x0009 << 2) + 0xfe331c00)
+//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000;
+#define AUDIO_RSAMP_ADJ_FORCE ((0x000a << 2) + 0xfe331c00)
+//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8;
+#define AUDIO_RSAMP_ADJ_KI_FORCE ((0x000b << 2) + 0xfe331c00)
+//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0;
+#define AUDIO_RSAMP_WATCHDOG_THRD ((0x000c << 2) + 0xfe331c00)
+//Bit 31:0 reg_watchdog_thrd //signed , default = 32'h1000;
+#define AUDIO_RSAMP_RO_STATUS ((0x0010 << 2) + 0xfe331c00)
+//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]}
+#define AUDIO_RSAMP_RO_ADJ_FREQ ((0x0011 << 2) + 0xfe331c00)
+//Bit 31:0 ro_rsamp_adj_freq
+#define AUDIO_RSAMP_RO_ADJ_DIFF_BAK ((0x0012 << 2) + 0xfe331c00)
+//Bit 31:0 ro_det_diff_bak
+#define AUDIO_RSAMP_RO_ADJ_DIFF_DLT ((0x0013 << 2) + 0xfe331c00)
+//Bit 31:0 ro_det_diff_dlt
+#define AUDIO_RSAMP_RO_ADJ_PHS_ERR ((0x0014 << 2) + 0xfe331c00)
+//Bit 31:0 ro_det_phase_err
+#define AUDIO_RSAMP_RO_ADJ_KI_OUT ((0x0015 << 2) + 0xfe331c00)
+//Bit 31:0 ro_rsamp_ki_out
+#define AUDIO_RSAMP_RO_IN_CNT ((0x0016 << 2) + 0xfe331c00)
+//Bit 31:0 ro_rsamp_in_cnt
+#define AUDIO_RSAMP_RO_OUT_CNT ((0x0017 << 2) + 0xfe331c00)
+//Bit 31:0 ro_rsamp_out_cnt
+#define AUDIO_RSAMP_RO_ADJ_PHS_ERR_VAR ((0x0018 << 2) + 0xfe331c00)
+//Bit 31:0 ro_det_phase_err_var
+#define AUDIO_RSAMP_POST_COEF0 ((0x0020 << 2) + 0xfe331c00)
+//Bit 31:0 reg_post_coef0 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF1 ((0x0021 << 2) + 0xfe331c00)
+//Bit 31:0 reg_post_coef1 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF2 ((0x0022 << 2) + 0xfe331c00)
+//Bit 31:0 reg_post_coef2 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF3 ((0x0023 << 2) + 0xfe331c00)
+//Bit 31:0 reg_post_coef3 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF4 ((0x0024 << 2) + 0xfe331c00)
+//Bit 31:0 reg_post_coef4 //signed , default = 0;
+#define AUDIO_RSAMP_AA_COEF_ADDR ((0x0030 << 2) + 0xfe331c00)
+//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0;
+#define AUDIO_RSAMP_AA_COEF_DATA ((0x0031 << 2) + 0xfe331c00)
+//Bit 31:0 reg_aa_coef_data //signed , default = 0;
+#define AUDIO_RSAMP_SINC_COEF_ADDR ((0x0040 << 2) + 0xfe331c00)
+//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0;
+#define AUDIO_RSAMP_SINC_COEF_DATA ((0x0041 << 2) + 0xfe331c00)
+//Bit 31:0 reg_sinc_coef_data //signed , default = 0;
+//
+// Closing file: RESAMPLE.h
+//
+//========================================================================
+// AUDIO EARCTX_CMDC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe333000
+// -----------------------------------------------
+//
+// Reading file: earc_tx_cmdc.h
+//
+#define EARC_TX_CMDC_TOP_CTRL0 ((0x0030 << 2) + 0xfe333000)
+//Bit 31 , idle2_int unsigned, default = 0, 1: enable
+//Bit 30 , idle1_int unsigned, default = 0, 1: enable
+//Bit 29 , disc2_int unsigned, default = 0, 1: enable
+//Bit 28 , disc1_int unsigned, default = 0, 1: enable
+//Bit 27 , earc_int unsigned, default = 0, 1: enable
+//Bit 26 , hb_status_int unsigned, default = 0, 1: enable
+//Bit 25 , losthb_int unsigned, default = 0, 1: enable
+//Bit 24 , timeout_int unsigned, default = 0, 1: enable
+//Bit 23 , status_ch_int unsigned, default = 0, 1: enable
+//Bit 22 , int_recv_finished unsigned, default = 0, 1: enable
+//Bit 21 , int_rdata unsigned, default = 0, 1: enable
+//Bit 20 , int_recv_nack unsigned, default = 0, 1: enable
+//Bit 19 , int_recv_norsp unsigned, default = 0, 1: enable
+//Bit 18 , int_recv_unexp unsigned, default = 0, 1: enable
+//Bit 17 , int_recv_data unsigned, default = 0, 1: enable
+//Bit 16 , int_recv_ack unsigned, default = 0, 1: enable
+//Bit 15 , int_recv_ecc_err unsigned, default = 0, 1: enable
+//Bit 14 , int_recv_packet unsigned, default = 0, 1: enable
+//Bit 13:0 , reserved
+#define EARC_TX_CMDC_TOP_CTRL1 ((0x0031 << 2) + 0xfe333000)
+//Bit 31:0, cmdc_top_ctrl1 //unsigned, RW, default = 0,
+#define EARC_TX_CMDC_TOP_CTRL2 ((0x0032 << 2) + 0xfe333000)
+//Bit 31 , reset_idle2_int unsigned, default = 0, 1: enable
+//Bit 30 , reset_idle1_int unsigned, default = 0, 1: enable
+//Bit 29 , reset_disc2_int unsigned, default = 0, 1: enable
+//Bit 28 , reset_disc1_int unsigned, default = 0, 1: enable
+//Bit 27 , reset_earc_int unsigned, default = 0, 1: enable
+//Bit 26 , reset_hb_status_int unsigned, default = 0, 1: enable
+//Bit 25 , reset_losthb_int unsigned, default = 0, 1: enable
+//Bit 24 , reset_timeout_int unsigned, default = 0, 1: enable
+//Bit 23 , reset_status_ch_int unsigned, default = 0, 1: enable
+//Bit 22 , reset_int_recv_finished unsigned, default = 0, 1: enable
+//Bit 21 , reset_int_rdata unsigned, default = 0, 1: enable
+//Bit 20 , reset_int_recv_nack unsigned, default = 0, 1: enable
+//Bit 19 , reset_int_recv_norsp unsigned, default = 0, 1: enable
+//Bit 18 , reset_int_recv_unexp unsigned, default = 0, 1: enable
+//Bit 17 , reset_int_recv_data unsigned, default = 0, 1: enable
+//Bit 16 , reset_int_recv_ack unsigned, default = 0, 1: enable
+//Bit 15 , reset_int_recv_ecc_err unsigned, default = 0, 1: enable
+//Bit 14 , reset_int_recv_packet unsigned, default = 0, 1: enable
+//Bit 13:0 , reserved
+#define EARC_TX_CMDC_TIMER_CTRL0 ((0x0033 << 2) + 0xfe333000)
+//Bit 31:0, cmdc_timer_ctrl0 //unsigned, RW, default = 0,
+#define EARC_TX_CMDC_TIMER_CTRL1 ((0x0034 << 2) + 0xfe333000)
+//Bit 31:0, cmdc_timer_ctrl1 //unsigned, RW, default = 0,
+#define EARC_TX_CMDC_TIMER_CTRL2 ((0x0035 << 2) + 0xfe333000)
+//Bit 31:0, cmdc_timer_ctrl2 //unsigned, RW, default = 0,
+#define EARC_TX_CMDC_TIMER_CTRL3 ((0x0036 << 2) + 0xfe333000)
+//Bit 31:0, cmdc_timer_ctrl3 //unsigned, RW, default = 0,
+#define EARC_TX_CMDC_VSM_CTRL0 ((0x0037 << 2) + 0xfe333000)
+//Bit 31, sw_state_update unsigned, default = 0, XX
+//Bit 30:28, sw_state unsigned, default = 0, XX
+//Bit 27, arc_initiated unsigned, default = 0, XX
+//Bit 26, arc_terminated unsigned, default = 0, XX
+//Bit 25, arc_enable unsigned, default = 1, XX
+//Bit 24, man_hpd unsigned, default = 0, XX
+//Bit 23:22, hpd_sel unsigned, default = 0, XX
+//Bit 21:20, hpd_sel_earc unsigned, default = 0, XX
+//Bit 19, comma_cnt_rst unsigned, default = 0, XX
+//Bit 18, timeout_status_rst unsigned, default = 0, XX
+//Bit 17, losthb_status_rst unsigned, default = 0, XX
+//Bit 16, force_rst unsigned, default = 0, XX
+//Bit 15, auto_state_en unsigned, default = 0, XX
+//Bit 14, cmdc_state_en unsigned, default = 0, XX
+//Bit 13, noack_repeat_en unsigned, default = 0, XX
+//Bit 12:0, reserved
+#define EARC_TX_CMDC_VSM_CTRL1 ((0x0038 << 2) + 0xfe333000)
+//Bit 31:9, reserved
+//Bit 8, cntl_hpd_sel unsigned, default = 0, 0:sel hd_hpd,1:sel hdmirx_hpd
+//Bit 7:0, comma_cnt_th unsigned, default = 0, should bigger than 3 and small than 10
+#define EARC_TX_CMDC_VSM_CTRL2 ((0x0039 << 2) + 0xfe333000)
+//Bit 31:12, max_count_th unsigned, default = 0, disc1 hpd_val timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, disc1 hpd_val timing
+//Bit 6:4, time_sel unsigned, default = 0, disc1 hpd_val timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, disc1 hpd_val timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, disc1 hpd_val timing
+#define EARC_TX_CMDC_VSM_CTRL3 ((0x003a << 2) + 0xfe333000)
+//Bit 31:12, max_count_th unsigned, default = 0, disc2 heartbeat act timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, disc2 heartbeat act timing
+//Bit 6:4, time_sel unsigned, default = 0, disc2 heartbeat act timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, disc2 heartbeat act timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, disc2 heartbeat act timing
+#define EARC_TX_CMDC_VSM_CTRL4 ((0x003b << 2) + 0xfe333000)
+//Bit 31:12, max_count_th unsigned, default = 0, in disc2, no heartbeat ack timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, in disc2, no heartbeat ack timing
+//Bit 6:4, time_sel unsigned, default = 0, in disc2, no heartbeat ack timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, in disc2, no heartbeat ack timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, in disc2, no heartbeat ack timing
+#define EARC_TX_CMDC_VSM_CTRL5 ((0x003c << 2) + 0xfe333000)
+//Bit 31:12, max_count_th unsigned, default = 0, in disc1 and disc2 timing out
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, in disc1 and disc2 timing out
+//Bit 6:4, time_sel unsigned, default = 0, in disc1 and disc2 timing out
+//Bit 3:2, soft_rst_sel unsigned, default = 0, in disc1 and disc2 timing out
+//Bit 1:0, enable_ctrl unsigned, default = 0, in disc1 and disc2 timing out
+#define EARC_TX_CMDC_VSM_CTRL6 ((0x003d << 2) + 0xfe333000)
+//Bit 31:12, max_count_th unsigned, default = 0, in earc heartbeat act timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, in earc heartbeat act timing
+//Bit 6:4, time_sel unsigned, default = 0, in earc heartbeat act timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, in earc heartbeat act timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, in earc heartbeat act timing
+#define EARC_TX_CMDC_VSM_CTRL7 ((0x003e << 2) + 0xfe333000)
+//Bit 31:16, reserved
+//Bit 15:8, status_soft_val unsigned, default = 0, in earc heartbeat det timing
+//Bit 7, reg_soft_rst unsigned, default = 0, in earc heartbeat det timing
+//Bit 6, status_rst unsigned, default = 0, in earc heartbeat det timing
+//Bit 5:4, reserved
+//Bit 3:2, soft_rst_sel unsigned, default = 0, in earc heartbeat det timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, in earc heartbeat det timing
+#define EARC_TX_CMDC_VSM_CTRL8 ((0x003f << 2) + 0xfe333000)
+//Bit 31:0, cmdc_vsm_ctrl8 //unsigned, RW, default = 0,
+#define EARC_TX_CMDC_VSM_CTRL9 ((0x0041 << 2) + 0xfe333000)
+//Bit 31:0, cmdc_vsm_ctrl9 //unsigned, RW, default = 0
+#define EARC_TX_CMDC_SENDER_CTRL0 ((0x0042 << 2) + 0xfe333000)
+//Bit 31:2, sender_ctrl0 unsigned, default = 0,
+//Bit 1, hb_chg_conf_auto unsigned, default = 1,
+//Bit 0, hb_chg_auto unsigned, default = 0,
+#define EARC_TX_CMDC_PACKET_CTRL0 ((0x0043 << 2) + 0xfe333000)
+//Bit 31, packet_mode_enable unsigned, default = 0, packet control
+//Bit 30, free_enable unsigned, default = 0, packet control
+//Bit 29, soft_rst unsigned, default = 0, packet control
+//Bit 28:24, tx_ready_threshold unsigned, default = 0, packet control
+//Bit 23:20, reserved
+//Bit 19:8, send_pre_threshold unsigned, default = 0, packet control
+//Bit 7:6, reserved
+//Bit 5, state_auto_en unsigned, default = 0, packet control
+//Bit 4, sw_state_update_en unsigned, default = 0, packet control
+//Bit 3:0, sw_state_value unsigned, default = 0, packet control
+#define EARC_TX_CMDC_PACKET_CTRL1 ((0x0044 << 2) + 0xfe333000)
+//Bit 31, ecc_endian unsigned, default = 0, send
+//Bit 30, pre_start_value unsigned, default = 0, send
+//Bit 29:21, reserved
+//Bit 20:16, post_threshold unsigned, default = 0, send
+//Bit 15:14, reserved
+//Bit 13:8, pre_threshold unsigned, default = 0, XX
+//Bit 7:0, post_flag unsigned, default = 0, XX
+#define EARC_TX_CMDC_PACKET_CTRL2 ((0x0045 << 2) + 0xfe333000)
+//Bit 31:0, pre_flag unsigned, default = 0, XX
+#define EARC_TX_CMDC_PACKET_CTRL3 ((0x0046 << 2) + 0xfe333000)
+//Bit 31, recv_en unsigned, default = 0, XX
+//Bit 30, recv_parity_mask unsigned, default = 0, XX
+//Bit 29, recv_timeout_en unsigned, default = 0, XX
+//Bit 28, bch_ecc_en unsigned, default = 0, xx
+//Bit 27:16, reserved
+//Bit 15:0, recv_timeout_threshold unsigned, default = 0, XX
+#define EARC_TX_CMDC_PACKET_CTRL4 ((0x0047 << 2) + 0xfe333000)
+//Bit 31:20, reserved
+//Bit 19:0, recv_packet_head unsigned, default = 0, XX
+#define EARC_TX_CMDC_PACKET_CTRL5 ((0x0048 << 2) + 0xfe333000)
+//Bit 31:20, reserved
+//Bit 19:0, recv_packet_head_mask unsigned, default = 0, XX
+#define EARC_TX_CMDC_PACKET_CTRL6 ((0x0049 << 2) + 0xfe333000)
+//Bit 31:20, recv_pre_threshold unsigned, default = 0, packet control
+//Bit 19:7, reserved
+//Bit 6, recv_finished_int unsigned, default = 0, XX
+//Bit 5, recv_ecc_err_int unsigned, default = 0, XX
+//Bit 4, recv_ack_int unsigned, default = 0, XX
+//Bit 3, recv_data_int unsigned, default = 0, XX
+//Bit 2, recv_unexp_int unsigned, default = 0, XX
+//Bit 1, recv_norsp_int unsigned, default = 0, XX
+//Bit 0, recv_nack_int unsigned, default = 0, XX
+#define EARC_TX_CMDC_BIPHASE_CTRL0 ((0x004a << 2) + 0xfe333000)
+//Bit 31:24, reserved
+//Bit 23:16, ack delay threshold unsigned, default = 0, xx
+//Bit 15:10, reserved
+//Bit 9, send_ack_en unsigned, default = 0, xx
+//Bit 8, sq_val_en unsigned, default = 0, XX
+//Bit 7, biphase_send_soft_rst unsigned, default = 0, XX
+//Bit 6, comma_soft_rst unsigned, default = 0, XX
+//Bit 5, fifo_rst unsigned, default = 0, XX
+//Bit 4, receiver_no_sender unsigned, default = 0, XX
+//Bit 3, sender_free unsigned, default = 0, XX
+//Bit 2, receiver_send unsigned, default = 0, XX
+//Bit 1, receiver_earc unsigned, default = 0, XX
+//Bit 0, receiver_free unsigned, default = 0, XX
+#define EARC_TX_CMDC_BIPHASE_CTRL1 ((0x004b << 2) + 0xfe333000)
+//Bit 31:16, reserved
+//Bit 15, ack_enable unsigned, default = 0, send
+//Bit 14:8, reserved
+//Bit 7:0, wait_threshold before ack unsigned, default = 0, send
+#define EARC_TX_CMDC_BIPHASE_CTRL2 ((0x004c << 2) + 0xfe333000)
+//Bit 31, comma_detection_enable unsigned, default = 0, comma detection
+//Bit 30, manual_reset_enable unsigned, default = 0, manual reset select, 1: manual
+//Bit 29, manual_reset_value unsigned, default = 0, manual reset control
+//Bit 28:16, reserved
+//Bit 15:0, comma_detection_threshold unsigned, default = 0,
+#define EARC_TX_CMDC_BIPHASE_CTRL3 ((0x004d << 2) + 0xfe333000)
+//Bit 31:0, cmdc_biphase_ctrl3 unsigned, default = 0,
+#define EARC_TX_CMDC_DEVICE_ID_CTRL ((0x004e << 2) + 0xfe333000)
+//Bit 31, apb_write unsigned, default = 0, apb bus wr/read
+//Bit 30, apb_read unsigned, default = 0, apb bus wr/read
+//Bit 29, apb_rw_done unsigned, default = 0, apb bus wr/read
+//Bit 28, apb_rw_reset unsigned, default = 0, apb bus wr/read
+//Bit 27:17, reserved
+//Bit 16, hpb_rst_enable unsigned, default = 1, hpd rst enable
+//Bit 15:8, apb_rwid unsigned, default = 0, apb bus wr/read
+//Bit 7:0, apbrw_start_addr unsigned, default = 0, apb bus wr/read
+#define EARC_TX_CMDC_DEVICE_WDATA ((0x004f << 2) + 0xfe333000)
+//Bit 31:8, reserved
+//Bit 7:0, apb_write_data unsigned, default = 0, apb bus wr/read
+#define EARC_TX_CMDC_DEVICE_RDATA ((0x0050 << 2) + 0xfe333000)
+//Bit 31:8, reserved
+//Bit 7:0, apb_read_data unsigned, default = 0, apb bus wr/read
+#define EARC_TX_CMDC_MASTER_CTRL ((0x0051 << 2) + 0xfe333000)
+//Bit 31, master_cmd_rw unsigned, default = 0, 1 write 0 read
+//Bit 30, master_hb_ignore unsigned, default =0, 0:wait hb issued before pkt cmd, 1: pkt cmd issued immediately
+//Bit 29, master_idle unsigned, default = 0, master status
+//Bit 28, master_cmd_soft_rst unsigned, default= 0,
+//Bit 27:24, hb_cmd_cal_th unsigned, default= 0,
+//Bit 23:16, master_cmd_count unsigned, default = 0, cmd count -1
+//Bit 15:8, master_cmd_id unsigned, default = 0,
+//Bit 7:0, master_cmd_address unsigned, default = 0,
+#define EARC_TX_ANA_CTRL0 ((0x0052 << 2) + 0xfe333000)
+//Bit 31:0, reg_earctx_ana_ctrl0 //unsigned, RW, default = 0,
+#define EARC_TX_ANA_CTRL1 ((0x0053 << 2) + 0xfe333000)
+//Bit 31:0, reg_earctx_ana_ctrl1 //unsigned, RW, default = 0,
+#define EARC_TX_ANA_CTRL2 ((0x0054 << 2) + 0xfe333000)
+//Bit 31:0, reg_earctx_ana_ctrl2 //unsigned, RW, default = 0,
+#define EARC_TX_ANA_CTRL3 ((0x0055 << 2) + 0xfe333000)
+//Bit 31:0, reg_earctx_ana_ctrl3 //unsigned, RW, default = 0,
+#define EARC_TX_ANA_CTRL4 ((0x0056 << 2) + 0xfe333000)
+//Bit 31:0, reg_earctx_ana_ctrl4 //unsigned, RW, default = 0,
+#define EARC_TX_ANA_CTRL5 ((0x0057 << 2) + 0xfe333000)
+//Bit 31:0, reg_earctx_ana_ctrl5 //unsigned, RW, default = 0,
+#define EARC_TX_ANA_STAT0 ((0x0058 << 2) + 0xfe333000)
+//Bit 31:0, ro_ANA_status0 //unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS0 ((0x0059 << 2) + 0xfe333000)
+//Bit 31:0, ro_cmdc_status0 //unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS1 ((0x005a << 2) + 0xfe333000)
+//Bit 31:0, ro_cmdc_status1 ///unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS2 ((0x005b << 2) + 0xfe333000)
+//Bit 31:0, ro_cmdc_status2 ///unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS3 ((0x005c << 2) + 0xfe333000)
+//Bit 31:0, ro_cmdc_status3 ///unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS4 ((0x005d << 2) + 0xfe333000)
+//Bit 31:0, ro_cmdc_status4 ///unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS5 ((0x005e << 2) + 0xfe333000)
+//Bit 31:0, ro_cmdc_status5 ///unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS6 ((0x005f << 2) + 0xfe333000)
+//Bit 31 , ro_idle2_int unsigned, RO, default = 0
+//Bit 30 , ro_idle1_int unsigned, RO, default = 0
+//Bit 29 , ro_disc2_int unsigned, RO, default = 0
+//Bit 28 , ro_disc1_int unsigned, RO, default = 0
+//Bit 27 , ro_earc_int unsigned, RO, default = 0
+//Bit 26 , ro_hb_status_int unsigned, RO, default = 0
+//Bit 25 , ro_losthb_int unsigned, RO, default = 0
+//Bit 24 , ro_timeout_int unsigned, RO, default = 0
+//Bit 23 , ro_status_ch_int unsigned, RO, default = 0
+//Bit 22 , ro_int_recv_finished unsigned, RO, default = 0
+//Bit 21 , ro_int_rdata unsigned, RO, default = 0
+//Bit 20 , ro_int_recv_nack unsigned, RO, default = 0
+//Bit 19 , ro_int_recv_norsp unsigned, RO, default = 0
+//Bit 18 , ro_int_recv_unexp unsigned, RO, default = 0
+//Bit 17 , ro_int_recv_data unsigned, RO, default = 0
+//Bit 16 , ro_int_recv_ack unsigned, RO, default = 0
+//Bit 15 , ro_int_recv_ecc_err unsigned, RO, default = 0
+//Bit 14 , ro_int_recv_packet unsigned, RO, default = 0
+//Bit 13:0 , reserved
+//
+// Closing file: earc_tx_cmdc.h
+//
+//========================================================================
+// AUDIO EARCTX_DMAC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe333400
+// -----------------------------------------------
+//
+// Reading file: earctx_dmac.h
+//
+#define EARCTX_DMAC_TOP_CTRL0 ((0x0000 << 2) + 0xfe333400)
+//Bit 31, reg_top_reg_sync ,default = 0,Bit 3:0 sync to clk10m,pluse auto clear
+//Bit 30, reg_top_soft_rst ,default = 0
+//Bit 29:26, reserved
+//Bit 25:24, reg_debug_mux ,default = 0
+//Bit 23:21, reserved
+//Bit 20, reg_slow_sync_scan_reg ,default = 0
+//Bit 19, reg_fe_sf_scan_reg ,default = 0
+//Bit 18, reg_fe_slow_sync_scan_reg ,default = 0
+//Bit 17, reg_top_sf_scan_reg ,default = 0
+//Bit 16, reg_top_slow_sync_scan_reg ,default = 0
+//Bit 15:4, reserved
+//Bit 3, reg_spdif_tx_en_force ,default = 0,spdif_tx_en force enable
+//Bit 2, reg_spdif_tx_en_force_value ,default = 0,spdif_tx_en force value
+//Bit 1, reg_dmac_tx_en_force ,default = 0,dmac_tx_en force enable
+//Bit 0, reg_dmac_tx_en_force_value ,default = 0,dmac_tx_en force value
+#define EARCTX_MUTE_VAL ((0x0001 << 2) + 0xfe333400)
+//Bit 31:0, reg_spdif_mute_val ,default = 0,when biahpase encode mute,the channel value,with reg_mute_l/reg_mute_r
+#define EARCTX_SPDIFOUT_GAIN0 ((0x0002 << 2) + 0xfe333400)
+//Bit 31:24, reg_gain_ch3 ,default = 0,channel 3 gain
+//Bit 23:16, reg_gain_ch2 ,default = 0,channel 2 gain
+//Bit 15:8, reg_gain_ch1 ,default = 0,channel 1 gain
+//Bit 7:0, reg_gain_ch0 ,default = 0,channel 0 gain
+#define EARCTX_SPDIFOUT_GAIN1 ((0x0003 << 2) + 0xfe333400)
+//Bit 31:24, reg_gain_ch7 ,default = 0,channel 7 gain
+//Bit 23:16, reg_gain_ch6 ,default = 0,channel 6 gain
+//Bit 15:8, reg_gain_ch5 ,default = 0,channel 5 gain
+//Bit 7:0, reg_gain_ch4 ,default = 0,channel 4 gain
+#define EARCTX_SPDIFOUT_CTRL0 ((0x0004 << 2) + 0xfe333400)
+//Bit 31, reg_work_start ,default = 0,biphase work start,pluse
+//Bit 30, reg_work_clr ,default = 0,biphase work clear,pluse
+//Bit 29, reg_rst_afifo_out_n ,default = 0,afifo out reset
+//Bit 28, reg_rst_afifo_in_n ,default = 0,afifo in reset
+//Bit 27, reg_hold_for_tdm ,default = 0,add delay to mathc TDM out when share buff
+//Bit 26, reg_userdata_sel ,default = 0,user Bit select : 0 from reg_userdata_set 1 from data[29]
+//Bit 25, reg_userdata_set ,default = 0
+//Bit 24, reg_chdata_sel ,default = 0,0 :from reg_chstst 1 from data[30]
+//Bit 23, reserved
+//Bit 22, reg_mute_l ,default = 0,r channel mute ,with reg_mute_val
+//Bit 21, reg_mute_r ,default = 0,l channel mute ,with reg_mute_val
+//Bit 20, reg_data_sel ,default = 0,0 data from 31Bit 1 data from 27bit
+//Bit 19, reg_out_msb_first ,default = 0,0 lsb first 1 msb first
+//Bit 18, reg_valid_sel ,default = 0,biphase encode valid Bit value sel : 0 from data 1 from reg_valid_set
+//Bit 17, reg_valid_set ,default = 0,biphase encode valid Bit value
+//Bit 16, reg_mute_hold_init_en ,default = 0,when c_mute_hold_last_err_corrt valid,clear work enable, initial biphase encode
+//Bit 15:12, reserved
+//Bit 0, reg_parity_mask ,default = 0,Bit 0 is initial parity value
+#define EARCTX_SPDIFOUT_CTRL1 ((0x0005 << 2) + 0xfe333400)
+//Bit 31, reg_eq_drc_sel ,default = 0,set 1 select eq_drc data
+//Bit 30, reg_keep_req_ddr_init ,default = 0,reg_keep_req_ddr_init
+//Bit 29:28, reserved
+//Bit 27, reg_gain_en ,default = 0,gain enable
+//Bit 26:24, reg_frddr_sel ,default = 0,from ddr selet
+//Bit 23:16, reg_wait_cnt ,default = 0,wait some time when enalble set to 1
+//Bit 15:13, reserved
+//Bit 12:8, reg_frddr_msb ,default = 0,msb position of data
+//Bit 7, reg_force_start ,default = 0,set 1 no need ack from frddr to transmit channel status
+//Bit 6:4, reg_frddr_type ,default = 0
+//Bit 3:0, reserved
+#define EARCTX_SPDIFOUT_PREAMB ((0x0006 << 2) + 0xfe333400)
+//Bit 31, reg_premable_Z_set ,default = 0,user 8'b11101000 1 user 7:0
+//Bit 30, reg_premable_Y_set ,default = 0,user 8'b11100100 1 user 15:8
+//Bit 29, reg_premable_X_set ,default = 0,user 8'b11100010 1 user 23:16
+//Bit 28:24, reserved
+//Bit 23:16, reg_premable_X_value ,default = 0
+//Bit 15:8, reg_premable_Y_value ,default = 0
+//Bit 7:0, reg_premable_Z_value ,default = 0
+#define EARCTX_SPDIFOUT_SWAP ((0x0007 << 2) + 0xfe333400)
+//Bit 31:16, reg_hold_cnt ,default = 0,hold start cnt ,valid when reg_hold_for_tdm set 1
+//Bit 15, reg_init_send_en ,default = 0,send 01 squence some times after intial done from frddr set
+//Bit 14:0, reg_init_send_cnt ,default = 0,send 01 squence time ,valid when reg_init_send_en set 1
+#define EARCTX_ERR_CORRT_CTRL0 ((0x0008 << 2) + 0xfe333400)
+//Bit 31:24, reserved
+//Bit 23, reg_bch_in_reverse ,default = 0,bch input data generate in 24it data reverse
+//Bit 22, reg_bch_out_ecc_reverse ,default = 0,bch output ecc reverse
+//Bit 21, reg_bch_out_data_reverse ,default = 0,bch output data reverse
+//Bit 20, reg_bch_out_ecc_msb ,default = 0,bch output ecc position
+//Bit 19:17, reserved
+//Bit 16, reg_ubit_fifo_init_n,default = 0,fifo in initial
+//Bit 15:14, reserved
+//Bit 13:12, reg_gain_shift ,default = 0,gain x 1/2/4/8
+//Bit 11, reg_mix_lr ,default = 0,l/r mix
+//Bit 10:8, reg_spdifout_r_sel ,default = 0,r channel select
+//Bit 7, reserved
+//Bit 6:4, reg_spdifout_l_sel ,default = 0,l channel select
+//Bit 3:0, reg_iu_interval ,default = 0,iu transmit interval
+#define EARCTX_ERR_CORRT_CTRL1 ((0x0009 << 2) + 0xfe333400)
+//Bit 31, reg_ubit_fifo_wr ,default = 0,iu data write enable,pluse,auto clr in reg.v
+//Bit 30:8, reserved
+//Bit 7:0, reg_ubit_fifo_wdata ,default = 0,iu data
+#define EARCTX_ERR_CORRT_CTRL2 ((0x000a << 2) + 0xfe333400)
+//Bit 31, reg_mute_clear ,default = 0,mute clear,pluse,auto clr in reg.v
+//Bit 30, reg_mute_start ,default = 0,mute start,pluse,auto clr in reg.v
+//Bit 29:28, reserved
+//Bit 27:16, reg_mute_block_num ,default = 0,mute block number
+//Bit 15:8, reg_mute_ch_Bit ,default = 0,mute Bit at channel statue which bit
+//Bit 7:3, reserved
+//Bit 2, reg_mute_data_sel ,default = 0,mute data sel: 0 data 1 reg_mute_data_value
+//Bit 1:0, reg_mute_mode ,default = 0,0:always mute 1:mute block number and dis mute 2:mute bolck number and hold bus
+#define EARCTX_ERR_CORRT_CTRL3 ((0x000b << 2) + 0xfe333400)
+//Bit 31:30, reserved
+//Bit 29, reg_bch_en ,default = 0,bch generate enable
+//Bit 28:24, reg_bch_msb ,default = 0,bch data msb position in audio data
+//Bit 23:0, reg_mute_data_value ,default = 0,mute value,only for audio data part
+#define EARCTX_ERR_CORRT_CTRL4 ((0x000c << 2) + 0xfe333400)
+//Bit 31, reg_ubit_fifo_lr_swap ,default = 0,//user Bit lr swap
+//Bit 30, reg_ubit_fifo_lr_same ,default = 0,//l/r channel use same Bit user bit
+//Bit 29:25, reg_data_msb ,default = 0,audio data msb postion in input data
+//Bit 24, reg_data_rsv ,default = 0,audio data msb/lsb
+//Bit 23, reg_ubit_value ,default = 0,user Bit value
+//Bit 22, reg_vbit_value ,default = 0,valid Bit value
+//Bit 21, reg_data_sel ,default = 0,//data sel: 0 data 1 reg_mute_data_value
+//Bit 20:19, reg_ubit_sel ,default = 0,//userBit sel: 0 data 1 reg_value 2 fifo data
+//Bit 18, reg_vbit_sel ,default = 0,//validBit sel: 0 data 1 reg_value
+//Bit 17, reg_chst_sel ,default = 0,//chanel status sel: 0 data 1 reg_value
+//Bit 16, reg_ubit_fifo_less_irq_en ,default = 0,fifo_less_thd irq enable
+//Bit 15:8, reg_ubit_fifo_start_thd ,default = 0,start transmit iu after fifo level greater than this value
+//Bit 7:0, reg_ubit_fifo_less_thd ,default = 0,generate irq,when fifo level less than this value
+#define EARCTX_ERR_CORRT_STAT0 ((0x000d << 2) + 0xfe333400)
+//Bit 31:0, ro_err_corrt_stat0 ,default = 0,
+#define EARCTX_SPDIFOUT_CHSTS0 ((0x000e << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_a_status ,default =0,channel A status[31:0]
+#define EARCTX_SPDIFOUT_CHSTS1 ((0x000f << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_a_status ,default =0,channel A status[63:32]
+#define EARCTX_SPDIFOUT_CHSTS2 ((0x0010 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_a_status ,default =0,channel A status[95:64]
+#define EARCTX_SPDIFOUT_CHSTS3 ((0x0011 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_a_status ,default =0,channel A status[127:96]
+#define EARCTX_SPDIFOUT_CHSTS4 ((0x0012 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_a_status ,default =0,channel A status[159:128]
+#define EARCTX_SPDIFOUT_CHSTS5 ((0x0013 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_a_status ,default =0,channel A status[191:160]
+#define EARCTX_SPDIFOUT_CHSTS6 ((0x0014 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_b_status ,default =0,channel B status[31:0]
+#define EARCTX_SPDIFOUT_CHSTS7 ((0x0015 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_b_status ,default =0,channel B status[63:32]
+#define EARCTX_SPDIFOUT_CHSTS8 ((0x0016 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_b_status ,default =0,channel B status[95:64]
+#define EARCTX_SPDIFOUT_CHSTS9 ((0x0017 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_b_status ,default =0,channel B status[127:96]
+#define EARCTX_SPDIFOUT_CHSTSA ((0x0018 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_b_status ,default =0,channel B status[159:128]
+#define EARCTX_SPDIFOUT_CHSTSB ((0x0019 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_b_status ,default =0,channel B status[191:160]
+#define EARCTX_FE_CTRL0 ((0x001a << 2) + 0xfe333400)
+//Bit 31, reg_mute_hold_clr ,default = 0,clear mute hold statues,pluse, auto clr
+//Bit 30, reg_work_enable ,default = 0,wore enable
+//Bit 29, reg_dmac_invt ,default = 0,fe out invent
+//Bit 28, reg_hold_time_en ,default = 0,hold min time enable
+//Bit 27, reg_hold_soft_clr_en ,default = 0,0 auto clear hold at next valid 1 clear hold with reg_mute_hold_clr
+//Bit 26:24, reg_hold_time_tick_sel ,default = 0,hold min time tick select
+//Bit 23:0, reg_hold_min_time ,default = 0,hold min time
+#define EARCTX_FE_STAT0 ((0x001b << 2) + 0xfe333400)
+//Bit 31:0, ro_fe_stat0 ,default = 0,
+#define EARCTX_SPDIFOUT_STAT ((0x001c << 2) + 0xfe333400)
+//Bit 31:0, ro_spdifout_stat ,default = 0,
+#define EARCTX_SPDIFOUT_CTRL2 ((0x001d << 2) + 0xfe333400)
+//Bit 31:28, reserved
+//Bit 27:16, reg_clr_by_init ,default = 0,reg_clr_by_init
+//Bit 15:0 , reg_mask ,default = 0,reg_mask
+#define EARCTX_SPDIFOUT_GAIN2 ((0x001e << 2) + 0xfe333400)
+//Bit 31:0, spdifout_gain2 ,default = 0,spdifout gain2
+#define EARCTX_SPDIFOUT_GAIN3 ((0x001f << 2) + 0xfe333400)
+//Bit 31:0, spdifout_gain3 ,default = 0,spdifout gain3
+#define EARCTX_SPDIFOUT_GAIN4 ((0x0020 << 2) + 0xfe333400)
+//Bit 31:0, spdifout_gain4 ,default = 0,spdifout gain4
+#define EARCTX_SPDIFOUT_GAIN5 ((0x0021 << 2) + 0xfe333400)
+//Bit 31:0, spdifout_gain5 ,default = 0,spdifout gain5
+//
+//
+// Closing file: earctx_dmac.h
+//
+//========================================================================
+// AUDIO EARCTX_TOP - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xff603600
+// -----------------------------------------------
+//
+// Reading file: earctx_top.h
+//
+#define EARCTX_TOP_CTRL0 ((0x0000 << 2) + 0xff603600)
+//Bit 31:18, reserved
+//Bit 17:16, reg_earctx_debug_mux unsigned, default = 0, debug mux
+//Bit 15, reg_slow_sync_scan_reg unsigned, default = 0, reg_slow_sync_scan_reg
+//Bit 14:12, reserved
+//Bit 11, reg_hdmi_hpd_invt unsigned, default = 0, hdmi_hpd invent
+//Bit 10, reg_hdmi_hpd_value unsigned, default = 0, hdmi_hpd mux = 3,register value
+//Bit 9:8, reg_hdmi_hpd_mux unsigned, default = 0, hdmi_hpd mux
+//Bit 7, reg_earctx_hd_hpd_invt unsigned, default = 0, earctx_hd_hdp invent
+//Bit 6, reg_earctx_hd_hpd_value unsigned, default = 0, earctx_hd_hdp mux = 3,register value
+//Bit 5:4, reg_earctx_hd_hdp_mux unsigned, default = 0, earctx_hd_hdp mux
+//Bit 3:2, reserved
+//Bit 1, reg_earctx_force_mode_en unsigned, default = 0, force mode enale
+//Bit 0, reg_earctx_force_mode unsigned, default = 0, force mode value
+#define EARCTX_DMAC_INT_MASK ((0x0001 << 2) + 0xff603600)
+//Bit 31:6, reserved
+//Bit 5:0, reg_dmac_int_mask unsigned, default = 0, dmac int mask
+#define EARCTX_DMAC_INT_PENDING ((0x0002 << 2) + 0xff603600)
+//Bit 31:6, reserved
+//Bit 5:0, reg_dmac_int_mask unsigned, default = 0, dmac int pending,read only
+#define EARCTX_CMDC_INT_MASK ((0x0003 << 2) + 0xff603600)
+//Bit 31:18, reserved
+//Bit 17:0, reg_cmdc_int_mask unsigned, default = 0, cmdc int mask
+#define EARCTX_CMDC_INT_PENDING ((0x0004 << 2) + 0xff603600)
+//Bit 31:18, reserved
+//Bit 17:0, reg_cmdc_int_mask unsigned, default = 0, cmdc int pending,read only
+#define EARCTX_ANA_CTRL0 ((0x0005 << 2) + 0xff603600)
+//Bit 31:0, reg_earctx_ana_ctrl0 unsigned, default = 0
+#define EARCTX_ANA_CTRL1 ((0x0006 << 2) + 0xff603600)
+//Bit 31:0, reg_earctx_ana_ctrl0 unsigned, default = 0
+#define EARCTX_ANA_CTRL2 ((0x0007 << 2) + 0xff603600)
+//Bit 31:0, reg_earctx_ana_ctrl0 unsigned, default = 0
+#define EARCTX_ANA_STAT0 ((0x0008 << 2) + 0xff603600)
+//Bit 31:0, reg_earctx_ana_ctrl0 unsigned, default = 0
+//
+// Closing file: earctx_top.h
+//
+//========================================================================
+// AUDIO EARCRX_CMDC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe333800
+// -----------------------------------------------
+//
+// Reading file: earc_rx_cmdc.h
+//
+#define EARC_RX_CMDC_TOP_CTRL0 ((0x0000 << 2) + 0xfe333800)
+//Bit 31 , idle2_int unsigned, default = 0, 1: enable
+//Bit 30 , idle1_int unsigned, default = 0, 1: enable
+//Bit 29 , disc2_int unsigned, default = 0, 1: enable
+//Bit 28 , disc1_int unsigned, default = 0, 1: enable
+//Bit 27 , earc_int unsigned, default = 0, 1: enable
+//Bit 26 , hb_status_int unsigned, default = 0, 1: enable
+//Bit 25 , losthb_int unsigned, default = 0, 1: enable
+//Bit 24 , timeout_int unsigned, default = 0, 1: enable
+//Bit 23 , status_ch_int unsigned, default = 0, 1: enable
+//Bit 22 , int_rec_invalid_id unsigned, default = 0, 1: enable
+//Bit 21 , int_rec_invalid_offset unsigned, default = 0, 1: enable
+//Bit 20 , int_rec_unexp unsigned, default = 0, 1: enable
+//Bit 19 , int_rec_ecc_err unsigned, default = 0, 1: enable
+//Bit 18 , int_rec_parity_err unsigned, default = 0, 1: enable
+//Bit 17 , int_recv_packet unsigned, default = 0, 1: enable
+//Bit 16 , int_rec_time_out unsigned, default = 0, 1: enable
+//Bit 15 , cmdc_debug0 unsigned, default = 0, 1: enable
+//Bit 14 , cmdc_debug1 unsigned, default = 0, 1: enable
+//Bit 13 , cmdc_debug2 unsigned, default = 0, 1: enable
+//Bit 12:7 , reserved
+//Bit 6 , mute_select unsigned, default = 0, 1: use bit5, 0: earc off
+//Bit 5 , mute_contrl unsigned, default = 0, value of mannul mute control
+//Bit 4:0 , reserved
+#define EARC_RX_CMDC_TOP_CTRL1 ((0x0001 << 2) + 0xfe333800)
+//Bit 31:13, reserved
+//Bit 12:8, reg_scan_reg unsigned, RW, default = 0,
+//Bit 7:5, reserved
+//Bit 4:0, reg_top_soft_rst unsigned, RW, default = 0,
+#define EARC_RX_CMDC_TOP_CTRL2 ((0x0002 << 2) + 0xfe333800)
+//Bit 31, reset_idle2_int unsigned, default =0
+//Bit 30, reset_idle1_int unsigned, default =0
+//Bit 29, reset_disc2_int unsigned, default =0
+//Bit 28, reset_disc1_int unsigned, default =0
+//Bit 27, reset_earc_int unsigned, default =0
+//Bit 26, reset_hb_status_int unsigned, default =0
+//Bit 25, reset_losthb_int unsigned, default =0
+//Bit 24, reset_timeout_int unsigned, default =0
+//Bit 23, reset_status_ch_int unsigned, default =0
+//Bit 22, reset_int_rec_invalid_id unsigned, default =0
+//Bit 21, reset_int_rec_invalid_offset unsigned, default =0
+//Bit 20, reset_int_rec_unexp unsigned, default =0
+//Bit 19, reset_int_rec_ecc_err unsigned, default =0
+//Bit 18, reset_int_rec_parity_err unsigned, default =0
+//Bit 17, reset_int_recv_packet unsigned, default =0
+//Bit 16, reset_int_rec_time_out unsigned, default =0
+//Bit 15:0, reserved
+#define EARC_RX_CMDC_TIMER_CTRL0 ((0x0003 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_TIMER_CTRL1 ((0x0004 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_TIMER_CTRL2 ((0x0005 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_TIMER_CTRL3 ((0x0006 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_VSM_CTRL0 ((0x0007 << 2) + 0xfe333800)
+//Bit 31, sw_state_update unsigned, default = 0, XX
+//Bit 30:28, sw_state unsigned, default = 0, XX
+//Bit 27, arc_initiated unsigned, default = 0, XX
+//Bit 26, arc_terminated unsigned, default = 0, XX
+//Bit 25, arc_enable unsigned, default = 0, XX
+//Bit 24, man_hpd unsigned, default = 0, XX
+//Bit 23:22, hpd_sel unsigned, default = 0, XX
+//Bit 21:20, hpd_sel_earc unsigned, default = 0, XX
+//Bit 19, comma_cnt_rst unsigned, default = 0, XX
+//Bit 18, timeout_status_rst unsigned, default = 0, XX
+//Bit 17, losthb_status_rst unsigned, default = 0, XX
+//Bit 16, force_rst unsigned, default = 0, XX
+//Bit 15, auto_state unsigned, default = 0, XX
+//Bit 14, cmdc_state_en unsigned, default = 0, XX
+//Bit 13:0, reserved
+#define EARC_RX_CMDC_VSM_CTRL1 ((0x0008 << 2) + 0xfe333800)
+//Bit 31:12, max_count_th unsigned, default = 0, idle done timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, idle done timing
+//Bit 6:4, time_sel unsigned, default = 0, idle done timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, idle done timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, idle done timing
+#define EARC_RX_CMDC_VSM_CTRL2 ((0x0009 << 2) + 0xfe333800)
+//Bit 31:12, max_count_th unsigned, default = 0, comma off done timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, comma off done timing
+//Bit 6:4, time_sel unsigned, default = 0, comma off done timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, comma off done timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, comma off done timing
+#define EARC_RX_CMDC_VSM_CTRL3 ((0x000a << 2) + 0xfe333800)
+//Bit 31:12, max_count_th unsigned, default = 0, earc_time out timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, earc_time out timing
+//Bit 6:4, time_sel unsigned, default = 0, earc_time out timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, earc_time out timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, earc_time out timing
+#define EARC_RX_CMDC_VSM_CTRL4 ((0x000b << 2) + 0xfe333800)
+//Bit 31:12, max_count_th unsigned, default = 0, heartbeat lost timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, heartbeat lost timing
+//Bit 6:4, time_sel unsigned, default = 0, heartbeat lost timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, heartbeat lost timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, heartbeat lost timing
+#define EARC_RX_CMDC_VSM_CTRL5 ((0x000c << 2) + 0xfe333800)
+//Bit 31:16, reserved
+//Bit 15:8, status_soft unsigned, default = 0, in earc heartbeat det timing
+//Bit 7, reg_soft_rst unsigned, default = 0, in earc heartbeat det timing
+//Bit 6, status_rst unsigned, default = 0, in earc heartbeat det timing
+//Bit 5:4, reserved
+//Bit 3:2, soft_rst_sel unsigned, default = 0, in earc heartbeat det timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, in earc heartbeat det timing
+#define EARC_RX_CMDC_VSM_CTRL6 ((0x000d << 2) + 0xfe333800)
+//Bit 31:17, reserved
+//Bit 16, cntl_hpd_sel unsigned, default = 0, in earc heartbeat det timing
+//Bit 15:4, cntl_hpd_valid_width unsigned, default = 0, in earc heartbeat det timing
+//Bit 3:0, cntl_hpd_glitch_width unsigned, default = 0, in earc heartbeat det timing
+#define EARC_RX_CMDC_VSM_CTRL7 ((0x000e << 2) + 0xfe333800)
+//Bit 31:0, vsm_ctrl7 unsigned, default = 0,
+#define EARC_RX_CMDC_VSM_CTRL8 ((0x000f << 2) + 0xfe333800)
+//Bit 31:0, vsm_ctrl8 unsigned, default = 0,
+#define EARC_RX_CMDC_VSM_CTRL9 ((0x0010 << 2) + 0xfe333800)
+//Bit 31:0, vsm_ctrl9 unsigned, default = 0,
+#define EARC_RX_CMDC_SENDER_CTRL0 ((0x0011 << 2) + 0xfe333800)
+//Bit 31:2, reserved
+//Bit 1, hb_chg_conf_auto unsigned, default = 0,
+//Bit 0, hb_chg_auto unsigned, default = 1,
+#define EARC_RX_CMDC_PACKET_CTRL0 ((0x0012 << 2) + 0xfe333800)
+//Bit 31, packet_mode_enable unsigned, default = 0, packet control
+//Bit 30, free_enable unsigned, default = 0, packet control
+//Bit 29, soft_rst_man unsigned, default = 0, packet control
+//Bit 28:24, ready_th unsigned, default = 0, packet control
+//Bit 23:20, reserved
+//Bit 19:8, send_pre_th unsigned, default = 0, packet control
+//Bit 7:5, reserved
+//Bit 4, sw_state_update unsigned, default = 0, packet control
+//Bit 3:0, sw_state unsigned, default = 0, packet control
+#define EARC_RX_CMDC_PACKET_CTRL1 ((0x0013 << 2) + 0xfe333800)
+//Bit 31, ecc_endian unsigned, default = 0, send
+//Bit 30, pre_reg_st unsigned, default = 0, send
+//Bit 29:21, reserved
+//Bit 20:16, post_th unsigned, default = 0, send
+//Bit 15:14, reserved
+//Bit 13:8, pre_th unsigned, default = 0,
+//Bit 7:0, post_flag unsigned, default = 0,
+#define EARC_RX_CMDC_PACKET_CTRL2 ((0x0014 << 2) + 0xfe333800)
+//Bit 31:0, pre_flag unsigned, default = 0, X
+#define EARC_RX_CMDC_PACKET_CTRL3 ((0x0015 << 2) + 0xfe333800)
+//Bit 31, cmdc_en unsigned, default = 0, XX
+//Bit 30, cmdc_parity_mask unsigned, default = 0, XX
+//Bit 29, imeout_en unsigned, default = 0, XX
+//Bit 28, ecc_check_en unsigned, default = 0, XX
+//Bit 27, rev_debug_en unsigned, default = 0, XX
+//Bit 26:16, reserved
+//Bit 15:0, timeout_th unsigned, default = 0, X
+#define EARC_RX_CMDC_PACKET_CTRL4 ((0x0016 << 2) + 0xfe333800)
+//Bit 31, ack_ignore unsigned, default = 0, XX
+//Bit 30, cmdc_tail_check_mask unsigned, default = 0, XX
+//Bit 29:20, reserved
+//Bit 19:0, cmdc_packet_head unsigned, default = 0, XX
+#define EARC_RX_CMDC_PACKET_CTRL5 ((0x0017 << 2) + 0xfe333800)
+//Bit 31:24, rev_debug_mask unsigned, default = 0, XX
+//Bit 23:20, reserved
+//Bit 19:0, cmdc_packet_head_mask unsigned, default = 0, XX
+#define EARC_RX_CMDC_PACKET_CTRL6 ((0x0018 << 2) + 0xfe333800)
+//Bit 31:20, recv_pre_threshold unsigned, default = 0, packet control
+//Bit 19:9, reserved
+//Bit 8, rec_packet_d unsigned, default = 0, XX
+//Bit 7, rec_parity_err_cnt unsigned, default = 0, XX
+//Bit 6, rec_ecc_err_cnt unsigned, default = 0, XX
+//Bit 5, rec_unexp_cnt unsigned, default = 0, XX
+//Bit 4, rec_invalid_offset_cnt unsigned, default = 0, XX
+//Bit 3, rec_invalid_id_cnt unsigned, default = 0, XX
+//Bit 2, rec_timeout_cnt unsigned, default = 0, XX
+//Bit 1, rec_w_cnt unsigned, default = 0, XX
+//Bit 0, rec_r_cnt unsigned, default = 0, X
+#define EARC_RX_CMDC_BIPHASE_CTRL0 ((0x0019 << 2) + 0xfe333800)
+//Bit 31:24, reg_tns unsigned, default = 7, xx
+//Bit 23:16, delay_th unsigned, default = 0, xx
+//Bit 15:10, reserved
+//Bit 9, send_ack_en unsigned, default = 0, xx
+//Bit 8, sq_val_en unsigned, default = 0, XX
+//Bit 7, biphase_send_soft_rst unsigned, default = 0, XX
+//Bit 6, comma_soft_rst unsigned, default = 0, XX
+//Bit 5, fifo_rst unsigned, default = 0, XX
+//Bit 4, receiver_no_sender unsigned, default = 0, XX
+//Bit 3, sender_free unsigned, default = 0, XX
+//Bit 2, receiver_send unsigned, default = 0, XX
+//Bit 1, receiver_earc unsigned, default = 0, XX
+//Bit 0, receiver_free unsigned, default = 0, XX
+#define EARC_RX_CMDC_BIPHASE_CTRL1 ((0x001a << 2) + 0xfe333800)
+//Bit 31:16, reserved
+//Bit 15, ack_val_en unsigned, default = 0, send
+//Bit 14:8, reserved
+//Bit 7:0, width unsigned, default = 0, send
+#define EARC_RX_CMDC_BIPHASE_CTRL2 ((0x001b << 2) + 0xfe333800)
+//Bit 31, ack_val_en unsigned, default = 0, send
+//Bit 30:20, reserved
+//Bit 19:16, ack_rate unsigned, default = 0, comma send
+//Bit 15:0, width unsigned, default = 0, comma sen
+#define EARC_RX_CMDC_BIPHASE_CTRL3 ((0x001c << 2) + 0xfe333800)
+//Bit 31:0, biphase_ctrl3 unsigned, default = 0,
+#define EARC_RX_CMDC_DEVICE_ID_CTRL ((0x001d << 2) + 0xfe333800)
+//Bit 31, apb_write unsigned, default = 0, apb bus wr/read
+//Bit 30, apb_read unsigned, default = 0, apb bus wr/read
+//Bit 29, apb_w_r_done unsigned, default = 0, apb bus wr/read
+//Bit 28, apb_w_r_reset unsigned, default = 0, apb bus wr/read
+//Bit 27:16, reserved
+//Bit 15:8, apb_w_r_id unsigned, default = 0, apb bus wr/read
+//Bit 7:0, apb_w_r_start_addr unsigned, default = 0, apb bus wr/read
+#define EARC_RX_CMDC_DEVICE_WDATA ((0x001e << 2) + 0xfe333800)
+//Bit 31:8, reserved
+//Bit 7:0, apb_write_data unsigned, default = 0, apb bus wr/rea
+#define EARC_RX_CMDC_DEVICE_RDATA ((0x001f << 2) + 0xfe333800)
+//Bit 31:8, reserved
+//Bit 7:0, apb_read_data unsigned, default = 0, apb bus wr/rea
+#define EARC_RX_ANA_CTRL0 ((0x0020 << 2) + 0xfe333800)
+//Bit 31:0, ana_ctrl0 unsigned, default = 0,
+#define EARC_RX_ANA_CTRL1 ((0x0021 << 2) + 0xfe333800)
+//Bit 31:0, ana_ctrl1 unsigned, default = 0,
+#define EARC_RX_ANA_CTRL2 ((0x0022 << 2) + 0xfe333800)
+//Bit 31:0, ana_ctrl2 unsigned, default = 0,
+#define EARC_RX_ANA_CTRL3 ((0x0023 << 2) + 0xfe333800)
+//Bit 31:0, ana_ctrl3 unsigned, default = 0,
+#define EARC_RX_ANA_CTRL4 ((0x0024 << 2) + 0xfe333800)
+//Bit 31:0, ana_ctrl4 unsigned, default = 0,
+#define EARC_RX_ANA_CTRL5 ((0x0025 << 2) + 0xfe333800)
+//Bit 31:0, ana_ctrl5 unsigned, default = 0,
+#define EARC_RX_ANA_STAT0 ((0x0026 << 2) + 0xfe333800)
+//Bit 31:0, ro_ANA_status0 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS0 ((0x0027 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS1 ((0x0028 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status1 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS2 ((0x0029 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status2 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS3 ((0x002a << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status3 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS4 ((0x002b << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status4 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS5 ((0x002c << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status5 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS6 ((0x002d << 2) + 0xfe333800)
+//Bit 31, ro_idle2_int unsigned, RO, dfault =0
+//Bit 30, ro_idle1_int unsigned, RO, dfault =0
+//Bit 29, ro_disc2_int unsigned, RO, dfault =0
+//Bit 28, ro_disc1_int unsigned, RO, dfault =0
+//Bit 27, ro_earc_int unsigned, RO, dfault =0
+//Bit 26, ro_hb_status_int unsigned, RO, dfault =0
+//Bit 25, ro_losthb_int unsigned, RO, dfault =0
+//Bit 24, ro_timeout_int unsigned, RO, dfault =0
+//Bit 23, ro_status_ch_int unsigned, RO, dfault =0
+//Bit 22, ro_int_rec_invalid_id unsigned, RO, dfault =0
+//Bit 21, ro_int_rec_invalid_offset unsigned, RO, dfault =0
+//Bit 20, ro_int_rec_unexp unsigned, RO, dfault =0
+//Bit 19, ro_int_rec_ecc_err unsigned, RO, dfault =0
+//Bit 18, ro_int_rec_parity_err unsigned, RO, dfault =0
+//Bit 17, ro_int_recv_packet unsigned, RO, dfault =0
+//Bit 16, ro_int_rec_time_out unsigned, RO, dfault =0
+//Bit 15:0, reserved
+//
+// Closing file: earc_rx_cmdc.h
+//
+//========================================================================
+// AUDIO EARCRX_DMAC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe333c00
+// -----------------------------------------------
+//
+// Reading file: earcrx_dmac.h
+//
+#define EARCRX_DMAC_TOP_CTRL0 ((0x0000 << 2) + 0xfe333c00)
+//Bit 31, reg_top_work_en unsigned, default = 0, top work enable
+//Bit 30, reg_top_soft_rst unsigned, default = 0, top soft reset
+//Bit 29:23, reserved
+//Bit 22:20, reg_dmac_debug_sel unsigned, default = 0, dmac debug select
+//Bit 19:18, reserved
+//Bit 17, reg_dmac_valid_sel unsigned, default = 0, dmac sync without clk
+//Bit 16, reg_dmac_without_clk unsigned, default = 0, dmac sync without clk
+//Bit 15, reg_sf_sync_scan_reg unsigned, default = 0, rst_n soft reset scan reg
+//Bit 14, reserved
+//Bit 13, reg_slow_sync_scan_reg unsigned, default = 0, rst_n sync clk_slow scan reg
+//Bit 12, reg_a_sync_scan_reg unsigned, default = 0, rst_n sync clk_analog scan reg
+//Bit 11, reg_slow_auto_gate unsigned, default = 0, clk_slow auto gate
+//Bit 10, reg_a_auto_gate unsigned, default = 0, clk_analog auto gate
+//Bit 9:0, reserved
+#define EARCRX_DMAC_SYNC_CTRL0 ((0x0001 << 2) + 0xfe333c00)
+//Bit 31, reg_work_enable unsigned, default = 0, dmac sync module work enable
+//Bit 30, reg_rst_afifo_out_n unsigned, default = 0, afifo out reset
+//Bit 29, reg_rst_afifo_in_n unsigned, default = 0, afifo in reset
+//Bit 28:17, reserved
+//Bit 16, reg_ana_buf_data_sel_en unsigned, default = 0, data from analog delay enable
+//Bit 15, reserved
+//Bit 14:12, reg_ana_buf_data_sel unsigned, default = 0, delay cycles
+//Bit 11, reserved
+//Bit 10:8, reg_ana_clr_cnt unsigned, default = 0, valid last how many 0 will clear
+//Bit 7, reserved
+//Bit 6:4, reg_ana_set_cnt unsigned, default = 0, valid last how may 1 will set
+//Bit 3:1, reserved
+//Bit 0, reg_dmacin_phase unsigned, default = 0, dmac data invert
+#define EARCRX_DMAC_SYNC_STAT0 ((0x0002 << 2) + 0xfe333c00)
+//Bit 31:0, reg_dmac_sync_stat0 unsigned, default = 0
+#define EARCRX_SPDIFIN_SAMPLE_CTRL0 ((0x0003 << 2) + 0xfe333c00)
+//Bit 31, reg_work_enable unsigned, default = 0, spdif in sample enable
+//Bit 30, reg_spdifin_phase unsigned, default = 0, spdif in invert
+//Bit 29, reg_debug_en unsigned, default = 0, debug single enable
+//Bit 28, reg_width_sel unsigned, default = 0, 0 detect by max_width 1 detect by min_width
+//Bit 27:23, reserved
+//Bit 22:20, reg_sample_mode unsigned, default = 0, value
+//Bit 19:0, reg_base_timer unsigned, default = 0, base timer to detect sample mode change
+#define EARCRX_SPDIFIN_SAMPLE_CTRL1 ((0x0004 << 2) + 0xfe333c00)
+//Bit 31, reg_force_sample_mode unsigned, default = 0, 0 auto detect sample mode 1 force a fixed sample mode with reg_sample_mode
+//Bit 30, reserved
+//Bit 29:20, reg_sample_mode0_timer_th unsigned, default = 0, mode0 threathold time
+//Bit 19:10, reg_sample_mode1_timer_th unsigned, default = 0, mode1 threathold time
+//Bit 9:0, reg_sample_mode2_timer_th unsigned, default = 0, mode2 threathold time
+#define EARCRX_SPDIFIN_SAMPLE_CTRL2 ((0x0005 << 2) + 0xfe333c00)
+//Bit 31:30, reserved
+//Bit 29:20, reg_sample_mode3_timer_th unsigned, default = 0, mode3 threathold time
+//Bit 19:10, reg_sample_mode4_timer_th unsigned, default = 0, mode4 threathold time
+//Bit 9:0, reg_sample_mode5_timer_th unsigned, default = 0, mode5 threathold time
+#define EARCRX_SPDIFIN_SAMPLE_CTRL3 ((0x0006 << 2) + 0xfe333c00)
+//Bit 31:24, reg_sample_mode0_timer unsigned, default = 0, mode0 sample time
+//Bit 23:16, reg_sample_mode1_timer unsigned, default = 0, mode1 sample time
+//Bit 15:8, reg_sample_mode2_timer unsigned, default = 0, mode2 sample time
+//Bit 7:0, reg_sample_mode3_timer unsigned, default = 0, mode3 sample time
+#define EARCRX_SPDIFIN_SAMPLE_CTRL4 ((0x0007 << 2) + 0xfe333c00)
+//Bit 31:24, reg_sample_mode4_timer unsigned, default = 0, mode4 sample time
+//Bit 23:16, reg_sample_mode5_timer unsigned, default = 0, mode5 sample time
+//Bit 15:8, reg_sample_mode6_timer unsigned, default = 0, mode6 sample time
+//Bit 7:0, reserved
+#define EARCRX_SPDIFIN_SAMPLE_CTRL5 ((0x0008 << 2) + 0xfe333c00)
+//Bit 31, reg_sq_filt_en unsigned, default = 0, dmac_sqout filter enable
+//Bit 30, reg_spdif_sqout_phase unsigned, default = 0, dmac_sqout invert
+//Bit 29:27, reg_filter_tick_sel unsigned, default = 0, dmac_sqout filter tick select
+//Bit 26:24, reg_filter_sel unsigned, default = 0, dmac_sqout filter select
+//Bit 23:20, reserved
+//Bit 19:0, reg_sq_filt_timer unsigned, default = 0, dmac_sqout filter tick
+#define EARCRX_SPDIFIN_SAMPLE_STAT0 ((0x0009 << 2) + 0xfe333c00)
+//Bit 31:0, reg_spdifin_sample_stat0 unsigned, default = 0
+#define EARCRX_SPDIFIN_SAMPLE_STAT1 ((0x000a << 2) + 0xfe333c00)
+//Bit 31:0, reg_spdifin_sample_stat1 unsigned, default = 0
+#define EARCRX_SPDIFIN_MUTE_VAL ((0x000b << 2) + 0xfe333c00)
+//Bit 31:0, reg_spdifin_mute_val unsigned, default = 0, spdif in mute value
+#define EARCRX_SPDIFIN_CTRL0 ((0x000c << 2) + 0xfe333c00)
+//Bit 31, reg_work_enable unsigned, default = 0, spdifin wore enable
+//Bit 30, reg_chnum_sel unsigned, default = 0, 0 ch_num = 0~383 1 ch_num = 0~1
+//Bit 29:28, reserved
+//Bit 27, reg_debug_en unsigned, default = 0, debug enable
+//Bit 26, reg_chnum_en unsigned, default = 0, star add ch_cnt to ch_num
+//Bit 25, reg_findpapb_en unsigned, default = 0, papb check enalbe
+//Bit 24, reg_nonpcm2pcm_en unsigned, default = 0, nonpcm2pcm_th enable
+//Bit 23:12, reg_nonpcm2pcm_th unsigned, default = 0, if long time didn't detect PaPb again,will generate irq
+//Bit 11:8, reg_ch_status_sel unsigned, default = 0, for stat1/stat2
+//Bit 7, reg_mute_l unsigned, default = 0, mute channel l
+//Bit 6, reg_mute_r unsigned, default = 0, mute channel r
+//Bit 5:4, reserved
+//Bit 3, reg_check_valid unsigned, default = 0, valid check enable
+//Bit 2, reg_check_parity unsigned, default = 0, parity check enable
+//Bit 1, reg_invert_data unsigned, default = 0, spdif data invert
+//Bit 0, reserved
+#define EARCRX_SPDIFIN_CTRL1 ((0x000d << 2) + 0xfe333c00)
+//Bit 31:24, reserved
+//Bit 31:24, reg_clr_internal_sts unsigned, default = 0, internal irq status clear
+//Bit 23:12, reg_mute_block_check_thd unsigned, default = 0, mute block check time thd
+//Bit 11:9, reg_mute_block_check_tick_sel unsigned, default = 0, mute block check tick sel
+//Bit 8, reg_papb_ext_sync unsigned, default = 0, ext 0 sync check for papb
+//Bit 7:0, reg_papb_ext_mask unsigned, default = 0, sync 0 mask
+#define EARCRX_SPDIFIN_CTRL2 ((0x000e << 2) + 0xfe333c00)
+//Bit 31:24, reg_mute_bit unsigned, default = 0, mute bit in channel st
+//Bit 23:19, reg_mute_block_num unsigned, default = 0, mute min block number to declare
+//Bit 18, reg_mute_lr_ch_sel unsigned, default = 0, mute bit in channel st L or R
+//Bit 17, reg_mute_block_check_en unsigned, default = 0, mute block number check enable
+//Bit 16, reg_earc_cps_chst_clr_en unsigned, default = 0, auto clear compress mode when channel status not compress
+//Bit 15, reg_earc_cps_nonpcm2pcm_clr_en unsigned, default = 0, auto clear compress mode when nonpcm2pcm
+//Bit 14, reg_earc_auto unsigned, default = 0, auto change earc/arc
+//Bit 13, reg_earcin_papb_lr unsigned, default = 0, user l or r channle status to check papb
+//Bit 12, reg_earcin_check_papb unsigned, default = 0, 0:data valid after 1 block;1: in 1st block if exit papb ,data valid after papb
+//Bit 11, reg_earcin_start_papb unsigned, default = 0, start write toddr 1:from papb check,0 from preamble Z,valid when reg_earcin_check_papb set
+//Bit 10, reg_formatchange_auto_rst unsigned, default = 0, auto reset will detect format change
+//Bit 9, reg_earcin_cpsb_pcpd_sel unsigned, default = 0, compress B pcpd select : 1:next 4th subframe data 0:next sub frame data
+//Bit 8:4, reg_earc_papb_msb unsigned, default = 0, papb msb position in data
+//Bit 3, reg_earcin_spdif_force unsigned, default = 0, when in arc mode,spdif on force enable
+//Bit 2, reg_earcin_spdif_force_set unsigned, default = 0, force value
+//Bit 1, reg_earcin_mode_force unsigned, default = 0, earc mode force enable
+//Bit 0, reg_earcin_mode_force_set unsigned, default = 0, force value
+#define EARCRX_SPDIFIN_CTRL3 ((0x000f << 2) + 0xfe333c00)
+//Bit 31:16, reg_earc_pa_value unsigned, default = 0, earc mode pa value
+//Bit 15:0, reg_earc_pb_value unsigned, default = 0, earc mode pb value
+#define EARCRX_SPDIFIN_STAT0 ((0x0010 << 2) + 0xfe333c00)
+//Bit 31:0, reg_spdifin_stat0 unsigned, default = 0
+#define EARCRX_SPDIFIN_STAT1 ((0x0011 << 2) + 0xfe333c00)
+//Bit 31:0, reg_spdifin_stat1 unsigned, default = 0
+#define EARCRX_SPDIFIN_STAT2 ((0x0012 << 2) + 0xfe333c00)
+//Bit 31:0, reg_spdifin_stat2 unsigned, default = 0
+#define EARCRX_DMAC_UBIT_CTRL0 ((0x0013 << 2) + 0xfe333c00)
+//Bit 31, reg_work_enable unsigned, default = 0, dmac user bit decode enable
+//Bit 30:24, reg_iu_sync unsigned, default = 0, iu sync value
+//Bit 23:16, reg_fifo_thd unsigned, default = 0, generate irq when fifo level pass some threthold
+//Bit 15, reg_max_dist_en unsigned, default = 0, max distance bewteen IUs to set lost
+//Bit 14, reg_iu_sync_en unsigned, default = 0, iu sync code enable 0 : all iu to fifo 1 only sync iu packet to fifo
+//Bit 13:12, reg_user_lr unsigned, default = 0, 00 off 01 use l channel userbit 10 use r channel userbit 11 user lr channel userbit
+//Bit 11:8, reg_max_dist unsigned, default = 0, max distance bewteen IUs value
+//Bit 7, reg_fifo_thd_en unsigned, default = 0, fifo_thd irq enable
+//Bit 6, reg_fifo_lost_init_en unsigned, default = 0, when lost,initial fifo
+//Bit 5, reg_fifo_init unsigned, default = 0, fifo initial
+//Bit 4:0, reg_data_bit unsigned, default = 0, user bit position in data
+#define EARCRX_IU_RDATA ((0x0014 << 2) + 0xfe333c00)
+//Bit 31:8, reserved
+//Bit 7:0, i_iu_rdata unsigned, default = 0, iu data,read only
+#define EARCRX_DMAC_UBIT_STAT0 ((0x0015 << 2) + 0xfe333c00)
+//Bit 31:0, reg_dmac_ubit_stat0 unsigned, default = 0
+#define EARCRX_ERR_CORRECT_CTRL0 ((0x0016 << 2) + 0xfe333c00)
+//Bit 31, reg_work_enable unsigned, default = 0, err correct work enable
+//Bit 30, reserved
+//Bit 29, reg_rst_afifo_out_n unsigned, default = 0, reset afifo out side
+//Bit 28, reg_rst_afifo_in_n unsigned, default = 0, reset afifo in side
+//Bit 27, reg_lr_check unsigned, default = 0, enable lr_check
+//Bit 26:7, reserved
+//Bit 6, reg_bchout_data_ml unsigned, default = 0, bch output 16bit data msb is 27 or 19
+//Bit 5, reg_bchout_data_rsv unsigned, default = 0, bch output data revers
+//Bit 4, reg_bchin_ecc_ml unsigned, default = 0, bch input ecc msb/lsb
+//Bit 3, reg_bchin_ecc_rsv unsigned, default = 0, bch input ecc revers
+//Bit 2, reg_bchin_data_rsv unsigned, default = 0, bch input data revers
+//Bit 1, reg_force_set unsigned, default = 0, 0 off 1 compress audio mode
+//Bit 0, reg_force_en unsigned, default = 0, force work mode enable
+#define EARCRX_ERR_CORRECT_STAT0 ((0x0017 << 2) + 0xfe333c00)
+//Bit 31:0, reg_err_correct_stat0 unsigned, default = 0
+#define EARCRX_ANA_RST_CTRL0 ((0x0018 << 2) + 0xfe333c00)
+//Bit 31, reg_work_enable unsigned, default = 0, analog reset check work enable
+//Bit 30, reg_ana_rst_sf_en unsigned, default = 0, analog reset from register enable
+//Bit 29, reg_ana_rst_sf unsigned, default = 0, soft reset value
+//Bit 28, reserved
+//Bit 27:23, reg_new_format_pos_num unsigned, default = 0, when new format data in, hold reset after N posedge
+//Bit 22:20, reg_dmacrx_div2_thd_tick_sel unsigned, default = 0, earcrx_div2 hold thresthold tick select
+//Bit 19:0, reg_earcrx_div2_thd unsigned, default = 0, earcrx_div2 hold thresthold
+#define EARCRX_ANA_RST_CTRL1 ((0x0019 << 2) + 0xfe333c00)
+//Bit 31, reg_dmacrx_data_filt_en unsigned, default = 0, filter enable
+//Bit 30:28, reg_dmacrx_data_filter_sel unsigned, default = 0, filter select
+//Bit 27:25, reg_dmacrx_data_tick_sel unsigned, default = 0, filter tick sel
+//Bit 24:16, reg_dmacrx_data_time unsigned, default = 0, filter tick time
+//Bit 15, reg_dmacrx_sqout_filt_en unsigned, default = 0, filter enable
+//Bit 14:12, reg_dmacrx_sqout_filter_sel unsigned, default = 0, filter select
+//Bit 11:9, reg_dmacrx_sqout_tick_sel unsigned, default = 0, filter tick sel
+//Bit 8:0, reg_dmacrx_sqout_time unsigned, default = 0, filter tick time
+#define EARCRX_SPDIFIN_CTRL4 ((0x0020 << 2) + 0xfe333c00)
+//Bit 31, reserved
+//Bit 30, reg_add_ch_r unsigned, default = 0, reg_add_ch_r
+//Bit 30, reg_bc_val0_en unsigned, default = 0, reg_bc_val0_en
+//Bit 28:20, reg_stable_mask unsigned, default = 0, reg_stable_mask
+//Bit 19:16, reg_stable_zcnt unsigned, default = 0, reg_stable_zcnt
+//Bit 15:0 , reserved
+#define EARCRX_SPDIFIN_CTRL5 ((0x0021 << 2) + 0xfe333c00)
+//Bit 31, reg_st_timeout_sts_clr unsigned, default = 0, reg_st_timeout_sts_clr
+//Bit 30:28, reserved
+//Bit 27:16, reg_st_timeout_check_thd unsigned, default = 0, reg_st_timeout_check_thd
+//Bit 15, reserved
+//Bit 14:12, reg_st_timeout_check_tick_sel unsigned, default = 0, reg_st_timeout_check_tick_sel
+//Bit 11, reg_st_timeout_check_en unsigned, default = 0, reg_st_timeout_check_en
+//Bit 8:0, reg_stable_int_mask unsigned, default = 0, reg_stable_int_mask
+#define EARCRX_SPDIFIN_CTRL6 ((0x0022 << 2) + 0xfe333c00)
+//Bit 31:17, reserved
+//Bit 16, reg_check_time_en unsigned, default = 0, reg_check_time_en
+//Bit 15:0, reg_check_time_thd unsigned, default = 0, reg_check_time_thd
+#define EARCRX_DMAC_SYNC_CTRL1 ((0x0023 << 2) + 0xfe333c00)
+//Bit 31:19, reserved
+//Bit 18, reg_auto_neg_int_en unsigned, default = 0, reg_auto_neg_int_en
+//Bit 17, reg_auto_stable_clr unsigned, default = 0, reg_auto_stable_clr
+//Bit 16, reg_auto_stable_en unsigned, default = 0, reg_auto_stable_en
+//Bit 15:0, reg_auto_stable_thd unsigned, default = 0, reg_auto_stable_thd
+#define EARCRX_SPDIFIN_SAMPLE_CTRL6 ((0x0024 << 2) + 0xfe333c00)
+//Bit 31:18, reserved
+//Bit 17, reg_hold_tri_sample unsigned, default = 0, reg_hold_tri_sample
+//Bit 16, reg_sample_mode_filter_en unsigned, default = 0, reg_sample_mode_filter_en
+//Bit 15:8, reg_stable_cyc_min unsigned, default = 0, reg_stable_cyc_min
+//Bit 7:0, reg_stable_cyc_max unsigned, default = 0, reg_stable_cyc_max
+//
+// Closing file: earcrx_dmac.h
+//
+//========================================================================
+// AUDIO EARCRX_TOP - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe333e00
+// -----------------------------------------------
+//
+// Reading file: earcrx_top.h
+//
+#define EARCRX_TOP_CTRL0 ((0x0000 << 2) + 0xfe333e00)
+//Bit 31:10, reserved
+//Bit 9:8, reg_top_debug_sel unsigned, default = 0, top debug select
+//Bit 7, reg_spdif_rx_en_force unsigned, default = 0, force spdif_rx_en to reg_spdif_rx_en_force_value
+//Bit 6, reg_spdif_rx_en_force_value unsigned, default = 0, value
+//Bit 5, reg_spdif_rx_sqen_force unsigned, default = 0, force spdif_rx_sqen to reg_spdif_rx_sqe
+//Bit 4, reg_spdif_rx_sqen_force_value unsigned, default = 0, value
+//Bit 3, reg_dmacrx_en_force unsigned, default = 0, force dmacrx_en to reg_dmacrx_en_force_value
+//Bit 2, reg_dmacrx_en_force_value unsigned, default = 0, value
+//Bit 1, reg_dmacrx_sqen_force unsigned, default = 0, force dmacrx_sqen to reg_dmacrx_sqen_force_value
+//Bit 0, reg_dmacrx_sqen_force_value unsigned, default = 0, value
+#define EARCRX_DMAC_INT_MASK ((0x0001 << 2) + 0xfe333e00)
+//Bit 31:30, reserved
+//Bit 29:0, reg_dmac_int_mask unsigned, default = 0, dmac int mask
+#define EARCRX_DMAC_INT_PENDING ((0x0002 << 2) + 0xfe333e00)
+//Bit 31:30, reserved
+//Bit 29:0, reg_dmac_int_mask unsigned, default = 0, dmac int pending,read only
+#define EARCRX_CMDC_INT_MASK ((0x0003 << 2) + 0xfe333e00)
+//Bit 31:16, reserved
+//Bit 15:0, reg_cmdc_int_mask unsigned, default = 0, cmdc int mask
+#define EARCRX_CMDC_INT_PENDING ((0x0004 << 2) + 0xfe333e00)
+//Bit 31:18, reserved
+//Bit 17:0, reg_cmdc_int_mask unsigned, default = 0, cmdc int pending,read only
+#define EARCRX_ANA_CTRL0 ((0x0005 << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_ANA_CTRL1 ((0x0006 << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_ANA_STAT0 ((0x0007 << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_PLL_CTRL0 ((0x0008 << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_PLL_CTRL1 ((0x0009 << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_PLL_CTRL2 ((0x000a << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_PLL_CTRL3 ((0x000b << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_PLL_STAT0 ((0x000c << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+//
+// Closing file: earcrx_top.h
+//
+//========================================================================
+// AUDIO RESAMPLEB - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe334000
+// -----------------------------------------------
+//
+// Reading file: RESAMPLEB.h
+//
+#define AUDIO_RSAMPB_CTRL0 ((0x0000 << 2) + 0xfe334000)
+//Bit 31:3 reserved
+//Bit 2 reg_lock_rst //unsigned , default =0;
+//Bit 1 reg_rsamp_rst //unsigned , default =0;
+//Bit 0 reg_sw_rst //unsigned , default =0;
+#define AUDIO_RSAMPB_CTRL1 ((0x0001 << 2) + 0xfe334000)
+//Bit 31:27 reserved //unsigned , default =0;
+//Bit 26 reg_watchdog_en //unsigned , default =0;
+//Bit 25 reg_rsamp_rst_sel //unsigned , default =0;
+//Bit 24 reg_module_bypas //unsigned , default =0;
+//Bit 23:18 reg_gclk_ctrl //unsigned , default =0;
+//Bit 17:13 reg_in_msb //unsigned , default =23;
+//Bit 12 reg_output_en //unsigned , default =0;
+//Bit 11 reg_rsamp_en //unsigned , default =0;
+//Bit 10 reg_filt_en //unsigned , default =0;
+//Bit 9 reg_post_en //unsigned , default =0;
+//Bit 8 reg_inp_mux_mode //unsigned , default =0;
+//Bit 7:4 reserved //unsigned , default =2;
+//Bit 3:0 reg_inp_mux //unsigned , default =0;
+#define AUDIO_RSAMPB_CTRL2 ((0x0002 << 2) + 0xfe334000)
+//Bit 31:30 reserved //unsigned , default =0;
+//Bit 29:24 reg_chx_size //unsigned , default =2;
+//Bit 23:18 reserved //unsigned , default =0;
+//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4
+//Bit 15:8 reg_filt_tap //unsigned , default =63;
+//Bit 7:0 reg_intp_tap //unsigned , default =63;
+#define AUDIO_RSAMPB_PHSINIT ((0x0003 << 2) + 0xfe334000)
+//Bit 31:28 reserved //unsigned , default = 0;
+//Bit 27:0 reg_init_phs //unsigned , default = 0;
+#define AUDIO_RSAMPB_PHSSTEP ((0x0004 << 2) + 0xfe334000)
+//Bit 31 reserved //unsigned , default = 0;
+//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000
+#define AUDIO_RSAMPB_SHIFT ((0x0005 << 2) + 0xfe334000)
+//Bit 31:24 reg_rsft_iir //unsigned , default = 23;
+//Bit 23:16 reg_rsft_blnd //unsigned , default = 21;
+//Bit 15:8 reg_rsft_sinc //unsigned , default = 31;
+//Bit 7:0 reg_rsft_aa //unsigned , default = 31;
+#define AUDIO_RSAMPB_ADJ_CTRL0 ((0x0006 << 2) + 0xfe334000)
+//Bit 31:3 reserved //unsigned
+//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0;
+//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0;
+//Bit 0 reg_rsamp_adj_en //unsigned , default = 0;
+#define AUDIO_RSAMPB_ADJ_CTRL1 ((0x0007 << 2) + 0xfe334000)
+//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8;
+//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768;
+#define AUDIO_RSAMPB_ADJ_SFT ((0x0008 << 2) + 0xfe334000)
+//Bit 31:30 reserved //unsigned , default = 0;
+//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0;
+//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9;
+//Bit 23:21 reserved //unsigned , default = 0;
+//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1;
+//Bit 15:13 reserved //unsigned , default = 0;
+//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6;
+//Bit 7:6 reserved //unsigned , default = 0;
+//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12;
+#define AUDIO_RSAMPB_ADJ_IDET_LEN ((0x0009 << 2) + 0xfe334000)
+//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000;
+#define AUDIO_RSAMPB_ADJ_FORCE ((0x000a << 2) + 0xfe334000)
+//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8;
+#define AUDIO_RSAMPB_ADJ_KI_FORCE ((0x000b << 2) + 0xfe334000)
+//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0;
+#define AUDIO_RSAMPB_WATCHDOG_THRD ((0x000c << 2) + 0xfe334000)
+//Bit 31:0 reg_watchdog_thrd //signed , default = 32'h1000;
+#define AUDIO_RSAMPB_RO_STATUS ((0x0010 << 2) + 0xfe334000)
+//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]}
+#define AUDIO_RSAMPB_RO_ADJ_FREQ ((0x0011 << 2) + 0xfe334000)
+//Bit 31:0 ro_rsamp_adj_freq
+#define AUDIO_RSAMPB_RO_ADJ_DIFF_BAK ((0x0012 << 2) + 0xfe334000)
+//Bit 31:0 ro_det_diff_bak
+#define AUDIO_RSAMPB_RO_ADJ_DIFF_DLT ((0x0013 << 2) + 0xfe334000)
+//Bit 31:0 ro_det_diff_dlt
+#define AUDIO_RSAMPB_RO_ADJ_PHS_ERR ((0x0014 << 2) + 0xfe334000)
+//Bit 31:0 ro_det_phase_err
+#define AUDIO_RSAMPB_RO_ADJ_KI_OUT ((0x0015 << 2) + 0xfe334000)
+//Bit 31:0 ro_rsamp_ki_out
+#define AUDIO_RSAMPB_RO_IN_CNT ((0x0016 << 2) + 0xfe334000)
+//Bit 31:0 ro_rsamp_in_cnt
+#define AUDIO_RSAMPB_RO_OUT_CNT ((0x0017 << 2) + 0xfe334000)
+//Bit 31:0 ro_rsamp_out_cnt
+#define AUDIO_RSAMPB_RO_ADJ_PHS_ERR_VAR ((0x0018 << 2) + 0xfe334000)
+//Bit 31:0 ro_det_phase_err_var
+#define AUDIO_RSAMPB_POST_COEF0 ((0x0020 << 2) + 0xfe334000)
+//Bit 31:0 reg_post_coef0 //signed , default = 0;
+#define AUDIO_RSAMPB_POST_COEF1 ((0x0021 << 2) + 0xfe334000)
+//Bit 31:0 reg_post_coef1 //signed , default = 0;
+#define AUDIO_RSAMPB_POST_COEF2 ((0x0022 << 2) + 0xfe334000)
+//Bit 31:0 reg_post_coef2 //signed , default = 0;
+#define AUDIO_RSAMPB_POST_COEF3 ((0x0023 << 2) + 0xfe334000)
+//Bit 31:0 reg_post_coef3 //signed , default = 0;
+#define AUDIO_RSAMPB_POST_COEF4 ((0x0024 << 2) + 0xfe334000)
+//Bit 31:0 reg_post_coef4 //signed , default = 0;
+#define AUDIO_RSAMPB_AA_COEF_ADDR ((0x0030 << 2) + 0xfe334000)
+//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0;
+#define AUDIO_RSAMPB_AA_COEF_DATA ((0x0031 << 2) + 0xfe334000)
+//Bit 31:0 reg_aa_coef_data //signed , default = 0;
+#define AUDIO_RSAMPB_SINC_COEF_ADDR ((0x0040 << 2) + 0xfe334000)
+//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0;
+#define AUDIO_RSAMPB_SINC_COEF_DATA ((0x0041 << 2) + 0xfe334000)
+//Bit 31:0 reg_sinc_coef_data //signed , default = 0;
+//
+// Closing file: RESAMPLEB.h
+//
+//
+// Closing file: REG_LIST_AUDIO_RTL.h
+//
+//
+// Reading file: REG_LIST_DSP_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//========================================================================
+// DSPA - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe340000
+// -----------------------------------------------
+#define DSP_CFG0 ((0x0000 << 2) + 0xfe340000)
+#define DSP_CFG1 ((0x0001 << 2) + 0xfe340000)
+#define DSP_CFG2 ((0x0002 << 2) + 0xfe340000)
+#define DSP_IMPWIRE ((0x0003 << 2) + 0xfe340000)
+#define DSP_RESET_VEC ((0x0004 << 2) + 0xfe340000)
+#define DSP_SEC_CFG0 ((0x0006 << 2) + 0xfe340000)
+#define DSP_SEC_CFG1 ((0x0007 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL0 ((0x0010 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL1 ((0x0011 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL2 ((0x0012 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL3 ((0x0013 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL4 ((0x0014 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL5 ((0x0015 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL6 ((0x0016 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL7 ((0x0017 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL8 ((0x0018 << 2) + 0xfe340000)
+#define DSP_IRQ_STS ((0x001f << 2) + 0xfe340000)
+#define DSP_REMAP0 ((0x0020 << 2) + 0xfe340000)
+#define DSP_REMAP1 ((0x0021 << 2) + 0xfe340000)
+#define DSP_REMAP2 ((0x0022 << 2) + 0xfe340000)
+#define DSP_STS0 ((0x0040 << 2) + 0xfe340000)
+#define DSP_STS1 ((0x0041 << 2) + 0xfe340000)
+#define DSP_STS2 ((0x0042 << 2) + 0xfe340000)
+#define DSP_STS3 ((0x0043 << 2) + 0xfe340000)
+#define DSP_STS4 ((0x0044 << 2) + 0xfe340000)
+#define DSP_STS5 ((0x0045 << 2) + 0xfe340000)
+#define DSP_QIF_CTRL ((0x0080 << 2) + 0xfe340000)
+#define DSP_QIF_STS ((0x0081 << 2) + 0xfe340000)
+#define DSP_WRFIFO_TOCPUA ((0x0082 << 2) + 0xfe340000)
+#define DSP_WRFIFO_TOCPUB ((0x0083 << 2) + 0xfe340000)
+#define DSP_WRFIFO_TODSP ((0x0084 << 2) + 0xfe340000)
+#define DSP_RDFIFO_FRCPUA ((0x0088 << 2) + 0xfe340000)
+#define DSP_RDFIFO_FRCPUB ((0x0089 << 2) + 0xfe340000)
+#define DSP_RDFIFO_FRDSP ((0x008a << 2) + 0xfe340000)
+//========================================================================
+// DSPB - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe350000
+// -----------------------------------------------
+#define DSPB_CFG0 ((0x0000 << 2) + 0xfe350000)
+#define DSPB_CFG1 ((0x0001 << 2) + 0xfe350000)
+#define DSPB_CFG2 ((0x0002 << 2) + 0xfe350000)
+#define DSPB_IMPWIRE ((0x0003 << 2) + 0xfe350000)
+#define DSPB_RESET_VEC ((0x0004 << 2) + 0xfe350000)
+#define DSPB_SEC_CFG0 ((0x0006 << 2) + 0xfe350000)
+#define DSPB_SEC_CFG1 ((0x0007 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL0 ((0x0010 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL1 ((0x0011 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL2 ((0x0012 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL3 ((0x0013 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL4 ((0x0014 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL5 ((0x0015 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL6 ((0x0016 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL7 ((0x0017 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL8 ((0x0018 << 2) + 0xfe350000)
+#define DSPB_IRQ_STS ((0x001f << 2) + 0xfe350000)
+#define DSPB_REMAP0 ((0x0020 << 2) + 0xfe350000)
+#define DSPB_REMAP1 ((0x0021 << 2) + 0xfe350000)
+#define DSPB_REMAP2 ((0x0022 << 2) + 0xfe350000)
+#define DSPB_STS0 ((0x0040 << 2) + 0xfe350000)
+#define DSPB_STS1 ((0x0041 << 2) + 0xfe350000)
+#define DSPB_STS2 ((0x0042 << 2) + 0xfe350000)
+#define DSPB_STS3 ((0x0043 << 2) + 0xfe350000)
+#define DSPB_STS4 ((0x0044 << 2) + 0xfe350000)
+#define DSPB_STS5 ((0x0045 << 2) + 0xfe350000)
+#define DSPB_QIF_CTRL ((0x0080 << 2) + 0xfe350000)
+#define DSPB_QIF_STS ((0x0081 << 2) + 0xfe350000)
+#define DSPB_WRFIFO_TOCPUA ((0x0082 << 2) + 0xfe350000)
+#define DSPB_WRFIFO_TOCPUB ((0x0083 << 2) + 0xfe350000)
+#define DSPB_WRFIFO_TODSP ((0x0084 << 2) + 0xfe350000)
+#define DSPB_RDFIFO_FRCPUA ((0x0088 << 2) + 0xfe350000)
+#define DSPB_RDFIFO_FRCPUB ((0x0089 << 2) + 0xfe350000)
+#define DSPB_RDFIFO_FRDSP ((0x008a << 2) + 0xfe350000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: REG_LIST_DSP_RTL.h
+//
+//
+// Reading file: REG_LIST_DEMUX_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe034000
+// -----------------------------------------------
+// There are two instantiations under one CBUS slave. Each CBUS slave can support
+// 256 registers. Each demux is allocated 128 registers so set the offset in
+// the middle
+// Copy this define but don't add a base address
+#define SECOND_DEMUX_OFFSET_0 0x50
+#define THIRD_DEMUX_OFFSET_0 0xa0
+//========================================================================
+// STB TOP Registers (8'hf0 - 8'hf7)
+//========================================================================
+// Bit 5:4 -- fec_sel_demux_2
+// Bit 3:2 -- fec_sel_demux_1
+// Bit 1:0 -- fec_sel_demux_0
+#define TS_TOP_CONFIG1 ((0x004f << 2) + 0xfe034000)
+// Bit 31:24 -- file_m2ts_skip_bytes_hiu1
+// Bit 23:22 -- reserved
+// Bit 21 -- ts_hiu_enable_hiu1
+// Bit 20:16 -- fec_clk_div_hiu1
+// Bit 15:8 -- TS_package_length_sub_1_hiu1 (default : 187)
+// Bit 7:0 -- fec_sync_byte_hiu1 (default : 0x47)
+#define TS_HIU1_CONFIG ((0x004e << 2) + 0xfe034000)
+//bit[1:0]-- stb_recorder2_sel
+#define STB_RECORDER2_CNTL ((0x00ee << 2) + 0xfe034000)
+// bit [11]-- s2p2_disable
+// bit [10:7]-- s2p2_clk_div
+// bit [6:0]-- fec_serial_control_2
+#define STB_S2P2_CONFIG ((0x00ef << 2) + 0xfe034000)
+// bit 30:28 -- ciplus_o_sel
+// bit 27:26 -- ciplus_i_sel
+// bit 25 -- use FAIL fro TS2
+// bit 24 -- use FAIL fro TS1
+// bit 23 -- use FAIL fro TS0
+// bit 22 -- invert fec_error for S2P1
+// bit 21 -- invert fec_data for S2P1
+// bit 20 -- invert fec_sync for S2P1
+// bit 19 -- invert fec_valid for S2P1
+// bit 18 -- invert fec_clk for S2P1
+// bit 17:16 -- fec_s_sel for S2P1 00 - select TS0, 01 -- select TS1, 10 -- select TS2, 11 - reserved
+// Bit 15 -- enable_des_pl_clk
+// Bit 14 -- ts_out_select[3]
+// Bit 13 -- use FAIL for TS3
+// Bit 12:10 -- ts_out_select[2:0], 0-TS0, 1-TS1, 2-TS2, 3-TS3, 4-S2P2, 5-S2P1, 6-S2P0, 7-File, 8-File1
+// bit 9:8 -- des_i_sel 00 -- select_fec_0, 01 -- select_fec_1, 10 -- select_fec_2, 11 - reserved
+// bit 7 -- enable_des_pl
+// bit 6 -- invert fec_error for S2P0
+// bit 5 -- invert fec_data for S2P0
+// bit 4 -- invert fec_sync for S2P0
+// bit 3 -- invert fec_valid for S2P0
+// bit 2 -- invert fec_clk for S2P0
+// bit 1:0 -- fec_s_sel for S2P0 00 - select TS0, 01 -- select TS1, 10 -- select TS2, 11 - reserved
+#define STB_TOP_CONFIG ((0x00f0 << 2) + 0xfe034000)
+// 31:28 - s2p1_clk_div
+// 27:24 - s2p0_clk_div
+// 23 - s2p1_disable
+// 22 - s2p0_disable
+// 21 - Reserved
+// 20 -- TS_OUT_error_INVERT
+// 19 -- TS_OUT_data_INVERT
+// 18 -- TS_OUT_sync_INVERT
+// 17 -- TS_OUT_valid_INVERT
+// 16 -- TS_OUT_clk_INVERT
+// 15:8 -- TS_package_length_sub_1 (default : 187)
+// 7:0 -- fec_sync_byte (default : 0x47)
+#define TS_TOP_CONFIG ((0x00f1 << 2) + 0xfe034000)
+// Bit 25:24 -- transport_scrambling_control_odd_2 // should be 3
+// Bit 23:16 -- file_m2ts_skip_bytes
+// Bit 15:8 -- des_out_dly
+// Bit 7:6 -- transport_scrambling_control_odd // should be 3
+// Bit 5 -- ts_hiu_enable
+// Bit 4:0 -- fec_clk_div
+#define TS_FILE_CONFIG ((0x00f2 << 2) + 0xfe034000)
+// Bit 19:14 -- des_2 ts pl state -- Read Only
+// Bit 13:8 -- des ts pl state -- Read Only
+// Bit 3:0 PID index to 8 PID to get key-set
+// auto increse after TS_PL_PID_DATA read/write
+#define TS_PL_PID_INDEX ((0x00f3 << 2) + 0xfe034000)
+// Bit 13 -- PID match disble
+// Bit 12:0 -- PID
+#define TS_PL_PID_DATA ((0x00f4 << 2) + 0xfe034000)
+#define COMM_DESC_KEY0 ((0x00f5 << 2) + 0xfe034000)
+#define COMM_DESC_KEY1 ((0x00f6 << 2) + 0xfe034000)
+#define COMM_DESC_KEY_RW ((0x00f7 << 2) + 0xfe034000)
+// CI+ Register defines
+// Bits[31:0] of the key
+#define CIPLUS_KEY0 ((0x00f8 << 2) + 0xfe034000)
+// Bits[63:32] of the key
+#define CIPLUS_KEY1 ((0x00f9 << 2) + 0xfe034000)
+// Bits[95:64] of the key
+#define CIPLUS_KEY2 ((0x00fa << 2) + 0xfe034000)
+// Bits[127:96] of the key
+#define CIPLUS_KEY3 ((0x00fb << 2) + 0xfe034000)
+// bit[5] write AES IV B value
+// bit[4] write AES IV A value
+// bit[3] write AES B key
+// bit[2] write AES A key
+// bit[1] write DES B key
+// bit[0] write DES A key
+#define CIPLUS_KEY_WR ((0x00fc << 2) + 0xfe034000)
+// [15:8] TS out delay. This controls the rate at which the CIplus module drives TS out
+// [3] General enable for the ciplus module
+// [2] AES CBC disable (default should be 0 to enable AES CBC)
+// [1] AES Enable
+// [0] DES Eanble
+#define CIPLUS_CONFIG ((0x00fd << 2) + 0xfe034000)
+// bit[31:28] AES IV endian
+// bit[27:24] AES message out endian
+// bit[23:20] AES message in endian
+// bit[19:16] AES key endian
+// bit[15:11] unused
+// bit[10:8] DES message out endian
+// bit[6:4] DES message in endian
+// bit[2:0] DES key endian
+#define CIPLUS_ENDIAN ((0x00fe << 2) + 0xfe034000)
+// bit 15:8 - des_out_dly_2
+// bit 7 - reserved
+// Bit 6-- enable_des_pl_clk_2
+// bit 5 - enable_des_pl_2
+// bit 4:2 -- use_des_2 bit[2] -- demux0, bit[3] -- demux1, bit[4] -- demux2
+// bit 1:0 -- des_i_sel_2 00 -- select_fec_0, 01 -- select_fec_1, 10 -- select_fec_2, 11 - reserved
+#define COMM_DESC_2_CTL ((0x00ff << 2) + 0xfe034000)
+//
+// NOTE: Don't process the demux registers using the standard create_headers.... perl script.
+// Instead, since the demux has multiple instances (and many registers) use a separate
+// script to create a separate stb_define.h for C-code.
+//========================================================================
+// STB Registers (8'h00 - 8'h4f)
+//
+//========================================================================
+// STB registers are 8'h0x
+// Bit 15:0 -- version number : 0x0002 (v0.01)
+// Bit 16 -- fec_select[3]
+// Bit 15 -- fec_core_select 1 - select descramble output
+// Bit 14:12 - fec_select[2:0] 0-TS0, 1-TS1, 2-TS2, 3-TS3, 4-S2P2, 5-S2P1, 6-S2P0, 7-File, 8-File1
+// Bit 11 -- FEC_CLK
+// Bit 10 -- SOP
+// Bit 9 -- D_VALID
+// Bit 8 -- D_FAIL
+// Bit 7:0 -- D_DATA 7:0
+// bit 31 -- enable_free_clk_fec_data_valid
+// bit 30 -- enable_free_clk_stb_reg
+// bit 29 -- always_use_pes_package_length
+// bit 28 -- disable_pre_incomplete_section_fix
+// bit 27 -- pointer_field_multi_pre_en
+// bit 26 -- ignore_pre_incomplete_section
+// bit 25 -- video2_enable
+// bit 24:22 -- video2_type
+// bit 21 -- do_not_trust_pes_package_length
+// bit 20 (bit 4) -- Bypass use recoder path
+// bit 19 (bit 3) -- clear_PID_continuity_counter_valid
+// bit 18 (bit 2) -- Disable Splicing
+// bit 17 (bit 1) -- Insert PES_STRONG_SYNC in Audio PES
+// bit 16 (bit 0) -- Insert PES_STRONG_SYNC in Video PES
+// Bit 15 - do not trust section length
+// Bit 14 - om cmd push even zero
+// Bit 13 - set_buff_ready_even_not_busy
+// Bit 12 - SUB, OTHER PES interrupt at beginning of PES
+// Bit 11 - discard_av_package -- for ts_recorder use only
+// Bit 10 - ts_recorder_select 0:after PID filter 1:before PID filter
+// Bit 9 - ts_recorder_enable
+// Bit 8 - (table_id == 0xff) means section_end
+// Bit 7 - do not send uncomplete section
+// Bit 6 - do not discard duplicate package
+// Bit 5 - search SOP when trasport_error_indicator
+// Bit 4 - stb demux enable
+// Bit 3 - do not reset state machine on SOP
+// Bit 2 - search SOP when error happened ( when ignore_fail_n_sop, will have this case)
+// Bit 1 - do not use SOP input ( check FEC sync byte instead )
+// Bit 0 - ignore fec_error bit when non sop ( check error on SOP only)
+// bit 15:8 demux package length - 1 ( default : 187 )
+// bit 7:0 default is 0x47
+// bit 31:16 -- filter memory write data hi[31:16]
+// bit 15:0 -- filter memory write data low [15:0]
+// bit 31:24 -- advanced setting hi
+// bit 23:16 -- advanced setting low
+// bit 15 -- filter memory write data request
+// bit 7:0 -- filter memory write addr
+// bit 13:8 demux state -- read only
+// bit 7:4 -- maxnum section filter compare address
+// bit 3:0 -- maxnum PID filter compare address
+// bit 15 - transport_error_indicator
+// bit 14 - payload_unit_start_indicator
+// bit 13 - transport_priority
+// bit 12:0 - PID
+// bit 7:6 transport_scrambling_control
+// bit 5:4 adaptation_field_control
+// bit 3:0 continuity_counter
+// bit 15:12 -- om_cmd_count (read only)
+// bit 11:9 -- overflow_count // bit 11:9 -- om_cmd_wr_ptr (read only)
+// bit 8:6 -- om_overwrite_count // bit 8:6 -- om_cmd_rd_ptr (read only)
+// bit 5:3 -- type_stb_om_w_rd (read only)
+// bit 2 -- unit_start_stb_om_w_rd (read only)
+// bit 1 -- om_cmd_overflow (read only)
+// bit 0 -- om_cmd_pending (read)
+// bit 0 -- om_cmd_read_finished (write)
+// bit 15:9 // bit 14:8 -- count_stb_om_w_rd (read only)
+// bit 8:0 // bit 7:0 -- start_stb_om_wa_rd (read only)
+// bit 11:0 -- offset for section data
+// bit 31:16 -- base address for section buffer group 0 (*0x400 to get real address)
+// bit 15:0 -- base address for section buffer group 1 (*0x400 to get real address)
+// bit 31:16 -- ba2e address for section buffer group 2 (*0x400 to get real address)
+// bit 15:0 -- base address for section buffer group 3 (*0x400 to get real address)
+// bit 3:0 -- section buffer size for group 0 (bit used, for example, 10 means 1K)
+// bit 7:4 -- section buffer size for group 1
+// bit 11:8 -- section buffer size for group 2
+// bit 15:12 -- section buffer size for group 3
+// section buffer busy status for buff 31:0 ( Read Only )
+// section buffer write status for buff 31:0 -- Read
+// clear buffer status ( buff READY and BUSY ) -- write
+// bit 4:0 -- SEC_BUFFER_INDEX RW
+// bit 12:8 -- SEC_BUFFER_NUMBER for the INDEX buffer Read_Only
+// bit 14 -- output_section_buffer_valid
+// bit 15 -- section_reset_busy (Read Only)
+// bit 9:5 -- BYPASS PID number
+// bit 4:0 -- PCR PID number
+// bit 15:0 -- stream_id filter bit enable
+// bit 7:0 -- stream_id filter target
+// bit 12 -- PCR_EN
+// bit 11:0 -- PCR90K_DIV
+// bit 31:0 -- PCR[31:0] R/W
+// bit 31:0 -- VPTS[31:0] R/W
+// bit 31:0 -- VDTS[31:0] R/W
+// bit 31:0 -- APTS[31:0] R/W
+// bit 31:0 -- SPTS[31:0] R/W
+// read -- status, write 1 clear status
+// bit 15 -- SUB_PTS[32]
+// bit 14 -- AUDIO_PTS[32]
+// bit 13 -- VIDEO_DTS[32]
+// bit 12 -- VIDEO_PTS[32]
+// bit 3 -- sub_pts_ready
+// bit 2 -- audio_pts_ready
+// bit 1 -- video_dts_ready
+// bit 0 -- video_pts_ready
+// bit 3:0 --
+// 0 -- adaptation_field_length[7:0], adaption_field_byte_1[7:0]
+// 1 -- stream_id[7:0], pes_header_bytes_left[7:0]
+// 2 -- pes_package_bytes_left[15:0]
+// 3 -- pes_ctr_byte[7:0], pes_flag_byte[7:0]
+//
+// read only
+// bit[31] -- no_match_record_en
+// bit[30:16] - reserved
+// default : 0x807f
+// bit 15:9 -- MAX OM DMA COUNT (default: 0x40)
+// bit 8:0 -- LAST ADDR OF OM ADDR (default: 127)
+// 15:0 WRITE 1 CLEAR to clear interrupt source
+//12 -- INPUT_TIME_OUT
+//11 -- PCR_ready
+//10 -- audio_splicing_point
+// 9 -- video_splicing_point
+// 8 -- other_PES_int
+// 7 -- sub_PES_int
+// 6 -- discontinuity
+// 5 -- duplicated_pack_found
+// 4 -- New PDTS ready
+// 3 -- om_cmd_buffer ready for access
+// 2 -- section buffer ready
+// 1 -- transport_error_indicator
+// 0 -- TS ERROR PIN
+// Bit 5:3 - demux om write endian control for bypass
+// Bit 2:0 - demux om write endian control for section
+// When Bit 31 - 1 write will indicate all type use sepertate endian (Write Only)
+// Bit 23:21 - demux om write endian control for OTHER_PES_PACKET
+// Bit 20:18 - demux om write endian control for SCR_ONLY_PACKET
+// Bit 17:15 - demux om write endian control for SUB_PACKET
+// Bit 14:12 - demux om write endian control for AUDIO_PACKET
+// Bit 11:9 - demux om write endian control for VIDEO_PACKET
+//
+// When Bit 31 - 0 write will indicate all type else use Bit 8:6
+// Bit 8:6 - demux om write endian control for else
+// Bit 10:9 -- sel DPTS_wr_ptr: 00 from parserA ; 01 from parserB
+// Bit 8:7 -- use hi_bsf interface: 01 sel hiu0; 10 sel hiu1
+// Bit 6:2 - Reserved
+// Bit 1 - enable_halt_ts_hiu_fix
+// Bit 0 - enable_halt_ts_hiu
+// bit 15:0 -- base address for section buffer start (*0x10000 to get real base)
+// bit 11 -- mask bit for OTHER_PES_AHB_DMA_EN
+// bit 10 -- mask bit for SUB_AHB_DMA_EN
+// bit 9 -- mask bit for BYPASS_AHB_DMA_EN
+// bit 8 -- mask bit for SECTION_AHB_DMA_EN
+// bit 7 -- mask bit for recoder stream
+// bit 6:0 -- mask bit for each type
+// bit 31:0 -- vb_wr_ptr for video PDTS
+// bit 31:0 -- ab_wr_ptr for audio PDTS
+// bit 20:0 -- SB_WRITE_PTR (sb_wr_ptr << 3 == byte write position)
+// bit 19:0 -- SB_START (sb_start << 12 == byte address);
+// bit 20:0 -- SB_SIZE (sb_size << 3 == byte size, 16M maximun)
+// bit 31:0 -- sb_wr_ptr for sub PES
+// bit 31:16 -- ob_wr_ptr for other PES
+// bit 20:0 -- OB_WRITE_PTR (ob_wr_ptr << 3 == byte write position)
+// bit 19:0 -- OB_START (ob_start << 12 == byte address);
+// bit 20:0 -- OB_SIZE (ob_size << 3 == byte size, 16M maximun)
+// bit 31:0 -- ob_wr_ptr for sub PES
+// 15:0 DEMUX interrupt MASK
+// 9 -- splicing_point
+// 8 -- other_PES_int
+// 7 -- sub_PES_int
+// 6 -- discontinuity
+// 5 -- duplicated_pack_found
+// 4 -- New PDTS ready
+// 3 -- om_cmd_buffer ready for access
+// 2 -- section buffer ready
+// 1 -- transport_error_indicator
+// 0 -- TS ERROR PIN
+// 31:16 VIDEO PID filter data
+//15 -- splicing VIDEO PID change enable
+//14:10 -- VIDEO PID FILTER ADDRESS
+// 9 -- PES splicing active (Read Only)
+// 8 -- splicing active (Read Only)
+// 7:0 splicing countdown (Read Only)
+// 31:16 AUDIO PID filter data
+//15 -- splicing AUDIO PID change enable
+//14:10 -- AUDIO PID FILTER ADDRESS
+// 9 -- PES splicing active (Read Only)
+// 8 -- splicing active (Read Only)
+// 7:0 splicing countdown (Read Only)
+// 23:16 M2TS_SKIP_BYTES
+// 15:8 LAST TS PACKAGE BYTE COUNT (Read Only)
+// 7:0 PACKAGE BYTE COUNT (Read Only)
+// 15:0 2 bytes strong sync add to PES
+// bit 15 -- stb_om_ren
+// bit 14:11 -- reserved
+// bit 10:0 -- OM_DATA_RD_ADDR
+// bit 15:0 -- OM_DATA_RD
+// AUTO STOP SETTING for 32 channels
+// 4-nbits per channel
+// when write
+// bit 3 -- set section active
+// bit 2:0 -- auto stop after count (0 means never stop)
+// when read
+// bit 3 -- current active status (1 - active, 0 - stopped )
+// bit 2:0 -- count down to auto stop
+// section 31:24
+// section 23:16
+// section 15:8
+// section 7:0
+// bit 31:0 reset channel status - each bit reset each channel
+// read -- 32 channel status
+// bit 4 -- video_stamp_use_dts
+// bit 3 -- audio_stamp_sync_1_en
+// bit 2 -- audio_stamp_insert_en
+// bit 1 -- video_stamp_sync_1_en
+// bit 0 -- video_stamp_insert_en
+// Write : Bit[4:0] secter filter number for reset
+// Read : select according to output_section_buffer_valid :
+// per bit per section buffer valid status
+// or section_buffer_ignore
+// bit[31:0] - channel_reset_timeout_disable
+// bit[31] - no_match_reset_timeout_disable
+// bit[30:0] input_time_out_int_cnt (0 -- means disable) Wr-setting, Rd-count
+// bit[31:0] - channel_packet_count_disable
+// bit[31] - no_match_packet_count_disable
+// bit[30:0] input_packet_count
+// bit[31:0] channel_record_enable
+// bit[31:0] channel_process_enable
+// bit[31:24] small_sec_size ((n+1) * 256 Bytes)
+// bit[23:16] small_sec_rd_ptr
+// bit[15:8] small_sec_wr_ptr
+// bit[7:2] reserved
+// bit[1] small_sec_wr_ptr_wr_enable
+// bit[0] small_section_enable
+// bit[31:0] small_sec_start_addr
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: REG_LIST_DEMUX_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: ./REG_LIST_RTL.h
+//
+//
+// Reading file: ./vcbus_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+//===========================================================================
+//
+// Reading file: rdma_regs.h
+//
+//===========================================================================
+// RDMA registers 0x00 - 0xff
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: RDMA_VCBUS_BASE = 0x11
+// -----------------------------------------------
+// Bit 31: 0 RW AHB start address for manual start DMA
+#define RDMA_AHB_START_ADDR_MAN ((0x1100 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for manual start DMA
+#define RDMA_AHB_END_ADDR_MAN ((0x1101 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 1
+#define RDMA_AHB_START_ADDR_1 ((0x1102 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 1
+#define RDMA_AHB_END_ADDR_1 ((0x1103 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 2
+#define RDMA_AHB_START_ADDR_2 ((0x1104 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 2
+#define RDMA_AHB_END_ADDR_2 ((0x1105 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 3
+#define RDMA_AHB_START_ADDR_3 ((0x1106 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 3
+#define RDMA_AHB_END_ADDR_3 ((0x1107 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 4
+#define RDMA_AHB_START_ADDR_4 ((0x1108 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 4
+#define RDMA_AHB_END_ADDR_4 ((0x1109 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 5
+#define RDMA_AHB_START_ADDR_5 ((0x110a << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 5
+#define RDMA_AHB_END_ADDR_5 ((0x110b << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 6
+#define RDMA_AHB_START_ADDR_6 ((0x110c << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 6
+#define RDMA_AHB_END_ADDR_6 ((0x110d << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 7
+#define RDMA_AHB_START_ADDR_7 ((0x110e << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 7
+#define RDMA_AHB_END_ADDR_7 ((0x110f << 2) + 0xff000000)
+// Auto start DMA control:
+// Bit 31:24 RW ctrl_enable_int_3. Interrupt inputs enable mask for source 3.
+// Bit 23:16 RW ctrl_enable_int_2. Interrupt inputs enable mask for source 2.
+// Bit 15: 8 RW ctrl_enable_int_1. Interrupt inputs enable mask for source 1.
+// Bit 7 RW ctrl_cbus_write_3. Register read/write mode for auto-start 3. 1=Register write; 0=Register read.
+// Bit 6 RW ctrl_cbus_write_3. Register read/write mode for auto-start 2. 1=Register write; 0=Register read.
+// Bit 5 RW ctrl_cbus_write_3. Register read/write mode for auto-start 1. 1=Register write; 0=Register read.
+// Bit 4 R Rsrv.
+// Bit 3 RW ctrl_cbus_addr_incr_3. 1=Incremental register access for auto-start 3; 0=Non-incremental (individual) register access.
+// Bit 2 RW ctrl_cbus_addr_incr_2. 1=Incremental register access for auto-start 2; 0=Non-incremental (individual) register access.
+// Bit 1 RW ctrl_cbus_addr_incr_1. 1=Incremental register access for auto-start 1; 0=Non-incremental (individual) register access.
+// Bit 0 R Rsrv.
+#define RDMA_ACCESS_AUTO ((0x1110 << 2) + 0xff000000)
+#define RDMA_ACCESS_AUTO2 ((0x1111 << 2) + 0xff000000)
+// Manual start DMA control:
+// Bit 31: 3 R Rsrv.
+// Bit 2 RW ctrl_cbus_write_man. Register read/write mode for manual-start. 1=Register write; 0=Register read.
+// Bit 1 RW ctrl_cbus_addr_incr_man. 1=Incremental register access for manual-start; 0=Non-incremental (individual) register access.
+// Bit 0 W ctrl_start_man. Write 1 to this bit to manual-start DMA. This bit always read back 0.
+#define RDMA_ACCESS_MAN ((0x1113 << 2) + 0xff000000)
+// RDMA general control:
+// Bit 31:25 R Rsrv.
+// Bit 24 W ctrl_clr_rdma_done_int. Write 1 to reset rdma_int level to 0. No need to clear this bit.
+// Bit 23:19 R Rsrv.
+// Bit 18:13 R Rsrv.
+// Bit 12: 7 R Rsrv.
+// Bit 6 RW ctrl_ddr_urgent.
+// Bit 5: 4 RW ctrl_ahb_wr_burst_size. 0=ABH write request burst size 16;
+// 1=ABH write request burst size 24;
+// 2=ABH write request burst size 32;
+// 3=ABH write request burst size 48.
+// Bit 3: 2 RW ctrl_ahb_rd_burst_size. 0=ABH read request burst size 16;
+// 1=ABH read request burst size 24;
+// 2=ABH read request burst size 32;
+// 3=ABH read request burst size 48.
+// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logics except register.
+// Bit 0 RW ctrl_free_clk_enable. 0=Default, Enable clock gating. 1=No clock gating, enable free clock.
+#define RDMA_CTRL ((0x1114 << 2) + 0xff000000)
+// Read only.
+// Bit 31:29 R Rsrv.
+// Bit 28 R rdma_done_int.
+// Bit 27:25 R Rsrv.
+// Bit 24:18 R ahb_wrfifo_cnt. FIFO for buffering CBus read data to be sent to AHB
+// Bit 17:11 R ahb_rdfifo_cnt. FIFO for buffering data read from AHB.
+// Bit 10: 8 R ddr_req_st. =0 -- Idle; !=0 -- AHB interfacing ongoing.
+// Bit 7: 4 R curr_req. Latest requests that is being/been serviced. E.g. 0000=Idle; 0010=Latest serviced request is Req 1.
+// Bit 3: 0 R req_latch. Requests that are yet to be serviced. E.g. 0000=No request; 0001=Req 0 waiting; 1100=Req 2 and 3 waiting.
+#define RDMA_STATUS ((0x1115 << 2) + 0xff000000)
+#define RDMA_STATUS2 ((0x1116 << 2) + 0xff000000)
+#define RDMA_STATUS3 ((0x1117 << 2) + 0xff000000)
+#define RDMA_ACCESS_AUTO4 ((0x1118 << 2) + 0xff000000)
+#define RDMA_SRAM_CNTL ((0x1120 << 2) + 0xff000000)
+#define RDMA_SRAM_REGADDR ((0x1121 << 2) + 0xff000000)
+#define RDMA_SRAM_REGDATA ((0x1122 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC1_SEL ((0x1123 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC2_SEL ((0x1124 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC3_SEL ((0x1125 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC4_SEL ((0x1126 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC5_SEL ((0x1127 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC6_SEL ((0x1128 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC7_SEL ((0x1129 << 2) + 0xff000000)
+//
+// Closing file: rdma_regs.h
+//
+//
+// Reading file: vpu_vdin0_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+// VDIN
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VDIN0_VCBUS_BASE = 0x12
+// -----------------------------------------------
+//
+// Reading file: vpu_vdin_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+// VDIN
+//===========================================================================
+#define VDIN_SCALE_COEF_IDX ((0x1200 << 2) + 0xff000000)
+#define VDIN_SCALE_COEF ((0x1201 << 2) + 0xff000000)
+//bit 31, mpeg_to_vdin_sel, 0: mpeg source to NR directly, 1: mpeg source pass through here
+//bit 30, mpeg_field info which can be written by software
+//Bit 29, force go_field, pulse signal
+//Bit 28, force go_line, pulse signal
+//Bit 27, enable mpeg_go_field input signal
+//Bit 26:20, hold lines
+//Bit 19, delay go_field function enable
+//Bit 18:12, delay go_field line number
+//Bit 11:10, component2 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in
+//Bit 9:8, component1 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in
+//Bit 7:6, component0 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in
+//Bit 5, input window selection function enable
+//Bit 4, enable VDIN common data input, otherwise there will be no video data input
+//Bit 3:0 vdin selection, 1: mpeg_in from dram, 2: bt656 input, 3: component input, 4: tvdecoder input, 5: hdmi rx input, 6: digtial video input, 7: loopback from Viu1, 8: MIPI.
+#define VDIN_COM_CTRL0 ((0x1202 << 2) + 0xff000000)
+//Bit 28:16 active_max_pix_cnt, readonly
+//Bit 12:0 active_max_pix_cnt_shadow, readonly
+#define VDIN_ACTIVE_MAX_PIX_CNT_STATUS ((0x1203 << 2) + 0xff000000)
+//Bit 28:16 go_line_cnt, readonly
+//Bit 12:0 active_line_cnt, readonly
+#define VDIN_LCNT_STATUS ((0x1204 << 2) + 0xff000000)
+//Readonly
+//Bit [14:3] lfifo_buf_cnt
+//Bit 2, vdin_direct_done status
+//Bit 1, vdin_nr_done status
+//Bit 0, field
+#define VDIN_COM_STATUS0 ((0x1205 << 2) + 0xff000000)
+//Readonly
+//Bit 31, vdi4 fifo overflow
+//Bit 29:24, vdi3_asfifo_cnt
+//Bit 23, vdi3 fifo overflow
+//Bit 21:16, vdi3_asfifo_cnt
+//Bit 15, vdi2 fifo overflow
+//Bit 13:8, vdi2_asfifo_cnt
+//Bit 7, vdi1 fifo overflow
+//Bit 5:0, vdi1_asfifo_cnt
+#define VDIN_COM_STATUS1 ((0x1206 << 2) + 0xff000000)
+//Bit 28:16 go_line_cnt_shadow, readonly
+//Bit 12:0 active_line_cnt_shadow, readonly
+#define VDIN_LCNT_SHADOW_STATUS ((0x1207 << 2) + 0xff000000)
+//each 8bit asfifo_ctrl is following:
+//Bit 7, DE enable
+//Bit 6, go field enable
+//Bit 5, go line enable
+//Bit 4, if true, negative active input vsync
+//Bit 3, if true, negative active input hsync
+//Bit 2, vsync soft reset fifo enable
+//Bit 1, overflow status clear
+//Bit 0 asfifo soft reset, level signal
+//Bit 7:0 vdi1 asfifo_ctrl
+//Bit 23:16 vdi2 asfifo_ctrl
+#define VDIN_ASFIFO_CTRL0 ((0x1208 << 2) + 0xff000000)
+//Bit 7:0 vdi3 asfifo_ctrl
+//Bit 23:16 vdi4 asfifo_ctrl
+#define VDIN_ASFIFO_CTRL1 ((0x1209 << 2) + 0xff000000)
+//Bit 28:16 input width minus 1, after the window function
+//Bit 12:0 output width minus 1
+#define VDIN_WIDTHM1I_WIDTHM1O ((0x120a << 2) + 0xff000000)
+//Bit 20:17 prehsc_mode, bit 3:2, prehsc odd line interp mode, bit 1:0, prehsc even line interp mode,
+// each 2bit, 00: pix0+pix1/2, average, 01: pix1, 10: pix0
+//Bit 16:15 sp422_mode, special mode for the component1 and component2, 00: normal case, 01: 32 64 32, 10: 0 64 64 0, 11: 16 96 16
+//Bit 14:8, hsc_ini_pixi_ptr, signed data, only useful when short_lineo_en is true
+//Bit 7, prehsc_en
+//Bit 6, hsc_en,
+//Bit 5, hsc_short_lineo_en, short line output enable
+//Bit 4, hsc_nearest_en
+//Bit 3, hsc_phase0_always_en
+//Bit 2:0, hsc_bank_length
+#define VDIN_SC_MISC_CTRL ((0x120b << 2) + 0xff000000)
+//Bit 28:24, integer portion
+//Bit 23:0, fraction portion
+#define VDIN_HSC_PHASE_STEP ((0x120c << 2) + 0xff000000)
+//Bit 30:29 hscale rpt_p0_num
+//Bit 28:24 hscale ini_rcv_num
+//Bit 23:0 hscale ini_phase
+#define VDIN_HSC_INI_CTRL ((0x120d << 2) + 0xff000000)
+//Read only
+//Bit 23, vdi7 fifo overflow
+//Bit 21:16, vdi7_asfifo_cnt
+//Bit 15, vdi6 fifo overflow
+//Bit 13:8, vdi6_asfifo_cnt
+//Bit 7, vdi5 fifo overflow
+//Bit 5:0, vdi5_asfifo_cnt
+#define VDIN_COM_STATUS2 ((0x120e << 2) + 0xff000000)
+//Bit 25:16 asfifo decimate control
+//Bit 25, if true, decimation counter sync with first valid DE in the field,
+//otherwise the decimation counter is not sync with external signal
+//Bit 24, decimation de enable
+//Bit 23:20, decimation phase, which counter value use to decimate,
+//Bit 19:16, decimation number, 0: not decimation, 1: decimation 2, 2: decimation 3 ....
+//Bit 7:0 vdi5 asfifo_ctrl
+#define VDIN_ASFIFO_CTRL2 ((0x120f << 2) + 0xff000000)
+//Bit 7, highlight_en
+//Bit 6 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix
+//Bit 5:4 probe_sel, 00: select matrix 0, 01: select matrix 1, otherwise select nothing
+//Bit 3:2, matrix coef idx selection, 00: select mat0, 01: select mat1, otherwise slect nothing
+//Bit 1 mat1 conversion matrix enable
+//Bit 0 mat0 conversion matrix enable
+#define VDIN_MATRIX_CTRL ((0x1210 << 2) + 0xff000000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define VDIN_MATRIX_COEF00_01 ((0x1211 << 2) + 0xff000000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define VDIN_MATRIX_COEF02_10 ((0x1212 << 2) + 0xff000000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define VDIN_MATRIX_COEF11_12 ((0x1213 << 2) + 0xff000000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define VDIN_MATRIX_COEF20_21 ((0x1214 << 2) + 0xff000000)
+//BIt 18:16 conv_rs
+//Bit 12:0 coef22
+#define VDIN_MATRIX_COEF22 ((0x1215 << 2) + 0xff000000)
+//Bit 26:16 offset0
+//Bit 10:0 offset1
+#define VDIN_MATRIX_OFFSET0_1 ((0x1216 << 2) + 0xff000000)
+//Bit 10:0 offset2
+#define VDIN_MATRIX_OFFSET2 ((0x1217 << 2) + 0xff000000)
+//Bit 26:16 pre_offset0
+//Bit 10:0 pre_offset1
+#define VDIN_MATRIX_PRE_OFFSET0_1 ((0x1218 << 2) + 0xff000000)
+//Bit 10:0 pre_offset2
+#define VDIN_MATRIX_PRE_OFFSET2 ((0x1219 << 2) + 0xff000000)
+//12:0 lfifo_buf_size
+#define VDIN_LFIFO_CTRL ((0x121a << 2) + 0xff000000)
+#define VDIN_COM_GCLK_CTRL ((0x121b << 2) + 0xff000000)
+//12:0 VDIN input interface width minus 1, before the window function, after the de decimation
+#define VDIN_INTF_WIDTHM1 ((0x121c << 2) + 0xff000000)
+//Bit 15 //default== 0, urgent_ctrl_en
+//Bit 14 //default== 0, urgent_wr, if true for write buffer
+//Bit 13 //default== 0, out_inv_en
+//Bit 12 //default == 0, urgent_ini_value
+//Bit 11:6 //default == 0, up_th up threshold
+//Bit 5:0 //default == 0, dn_th dn threshold
+#define VDIN_LFIFO_URG_CTRL ((0x121e << 2) + 0xff000000)
+//Bit 8, 1: discard data before line fifo, 0: normal mode
+//Bit 7:0 Write chroma canvas address
+#define VDIN_WR_CTRL2 ((0x121f << 2) + 0xff000000)
+//Bit 31:30 hconv_mode, Applicable only to bit[13:12]=0 or 2. 0: Output every even pixels' CbCr;
+// 1: Output every odd pixels' CbCr;
+// 2: Output an average value per even&odd pair of pixels;
+// 3: Output all CbCr. (This does NOT apply to bit[13:12]=0 -- 4:2:2 mode.)
+//Bit 29 no_clk_gate: disable vid_wr_mif clock gating function.
+//Bit 28 clear write response counter in the vdin write memory interface
+//Bit 27 eol_sel, 1: use eol as the line end indication, 0: use width as line end indication in the vdin write memory interface
+//Bit 26 vcp_nr_en. Only used in VDIN0. NOT used in VDIN1.
+//Bit 25 vcp_wr_en. Only used in VDIN0. NOT used in VDIN1.
+//Bit 24 vcp_in_en. Only used in VDIN0. NOT used in VDIN1.
+//Bit 23 vdin frame reset enble, if true, it will provide frame reset during go_field(vsync) to the modules after that
+//Bit 22 vdin line fifo soft reset enable, meaning, if true line fifo will reset during go_field (vsync)
+//Bit 21 vdin direct write done status clear bit
+//Bit 20 vdin NR write done status clear bit
+//Bit 18 swap_cbcr. Applicable only to bit[13:12]=2. 0: Output CbCr (NV12); 1: Output CrCb (NV21).
+//Bit 17:16 vconv_mode, Applicable only to bit[13:12]=2. 0: Output every even lines' CbCr;
+// 1: Output every odd lines' CbCr;
+// 2: Reserved;
+// 3: Output all CbCr.
+//Bit 13:12 vdin write format, 0: 4:2:2 to luma canvas, 1: 4:4:4 to luma canvas,
+// 2: Y to luma canvas, CbCr to chroma canvas. For NV12/21, also define Bit 31:30, 17:16, and bit 18.
+//Bit 11 vdin write canvas double buffer enable, means the canvas address will be latched by vsync before using
+//Bit 10 1: disable ctrl_reg write pulse which will reset internal counter. when bit 11 is 1, this bit should be 1.
+//Bit 9 vdin write request urgent
+//Bit 8 vdin write request enable
+//Bit 7:0 Write luma canvas address
+#define VDIN_WR_CTRL ((0x1220 << 2) + 0xff000000)
+//Bit 29, if true, horizontal reverse
+//Bit 28:16 start
+//Bit 12:0 end
+#define VDIN_WR_H_START_END ((0x1221 << 2) + 0xff000000)
+//Bit 29, if true, vertical reverse
+//Bit 28:16 start
+//Bit 15:13 field mode, 0 frame mode, 4 for field mode botton field, 5 for field mode top field, , 6 for blank line mode
+//Bit 12:0 end
+#define VDIN_WR_V_START_END ((0x1222 << 2) + 0xff000000)
+//Bit 24:20, integer portion
+//Bit 19:0, fraction portion
+#define VDIN_VSC_PHASE_STEP ((0x1223 << 2) + 0xff000000)
+//Bit 23, vsc_en, vertical scaler enable
+//Bit 22 if true, repeat last line while scaling, otherwise use the dummy data to extend the input picture
+//Bit 21 vsc_phase0_always_en, when scale up, you have to set it to 1
+//Bit 20:16 ini skip_line_num
+//Bit 15:0 vscaler ini_phase
+#define VDIN_VSC_INI_CTRL ((0x1224 << 2) + 0xff000000)
+//Bit 28:16, vshrink input height minus 1
+//Bit 12:0, scaler input height minus 1
+#define VDIN_SCIN_HEIGHTM1 ((0x1225 << 2) + 0xff000000)
+//Bit 23:16, dummy component 0
+//Bit 15:8, dummy component 1
+//Bit 7:0, dummy component 2
+#define VDIN_DUMMY_DATA ((0x1226 << 2) + 0xff000000)
+//Read only
+//Bit 29:20 component 0
+//Bit 19:10 component 1
+//Bit 9:0 component 2
+#define VDIN_MATRIX_PROBE_COLOR ((0x1228 << 2) + 0xff000000)
+//Bit 23:16 component 0
+//Bit 15:8 component 1
+//Bit 7:0 component 2
+#define VDIN_MATRIX_HL_COLOR ((0x1229 << 2) + 0xff000000)
+//28:16 probe x, postion
+//12:0 probe y, position
+#define VDIN_MATRIX_PROBE_POS ((0x122a << 2) + 0xff000000)
+#define VDIN_CHROMA_ADDR_PORT ((0x122b << 2) + 0xff000000)
+#define VDIN_CHROMA_DATA_PORT ((0x122c << 2) + 0xff000000)
+//
+#define VDIN_CM_BRI_CON_CTRL ((0x122d << 2) + 0xff000000)
+//Bit 17 clk_cyc_cnt_clr, if true, clear this register
+//Bit 16 if true, use vpu clock to count one line, otherwise use actually hsync to count line_cnt
+//Bit 15:0 line width using vpu clk
+#define VDIN_GO_LINE_CTRL ((0x122f << 2) + 0xff000000)
+//Bit 31:24 hist_pix_white_th, larger than this th is counted as white pixel
+//Bit 23:16 hist_pix_black_th, less than this th is counted as black pixel
+//Bit 11 hist_34bin_only, 34 bin only mode, including white/black
+//Bit 10:9 ldim_stts_din_sel, 00: from matrix0 dout, 01: from vsc_dout, 10: from matrix1 dout, 11: form matrix1 din
+//Bit 8 ldim_stts_en
+//Bit 6:5 hist_dnlp_low the real pixels in each bins got by VDIN_DNLP_HISTXX should multiple with 2^(dnlp_low+3)
+//Bit 3:2 hist_din_sel the source used for hist statistics. 00: from matrix0 dout, 01: from vsc_dout, 10: from matrix1 dout, 11: form matrix1 din
+//Bit 1 hist_win_en 1'b0: hist used for full picture; 1'b1: hist used for pixels within hist window
+//Bit 0 hist_spl_en 1'b0: disable hist readback; 1'b1: enable hist readback
+#define VDIN_HIST_CTRL ((0x1230 << 2) + 0xff000000)
+//Bit 28:16 hist_hstart horizontal start value to define hist window
+//Bit 12:0 hist_hend horizontal end value to define hist window
+#define VDIN_HIST_H_START_END ((0x1231 << 2) + 0xff000000)
+//Bit 28:16 hist_vstart vertical start value to define hist window
+//Bit 12:0 hist_vend vertical end value to define hist window
+#define VDIN_HIST_V_START_END ((0x1232 << 2) + 0xff000000)
+//Bit 15:8 hist_max maximum value
+//Bit 7:0 hist_min minimum value
+//read only
+#define VDIN_HIST_MAX_MIN ((0x1233 << 2) + 0xff000000)
+//Bit 31:0 hist_spl_rd
+//counts for the total luma value
+//read only
+#define VDIN_HIST_SPL_VAL ((0x1234 << 2) + 0xff000000)
+//Bit 21:0 hist_spl_pixel_count
+//counts for the total calculated pixels
+//read only
+#define VDIN_HIST_SPL_PIX_CNT ((0x1235 << 2) + 0xff000000)
+//Bit 31:0 hist_chroma_sum
+//counts for the total chroma value
+//read only
+#define VDIN_HIST_CHROMA_SUM ((0x1236 << 2) + 0xff000000)
+//Bit 31:16 higher hist bin
+//Bit 15:0 lower hist bin
+//0-255 are splited to 64 bins evenly, and VDIN_DNLP_HISTXX
+//are the statistic number of pixels that within each bin.
+//VDIN_DNLP_HIST00[15:0] counts for the first bin
+//VDIN_DNLP_HIST00[31:16] counts for the second bin
+//VDIN_DNLP_HIST01[15:0] counts for the third bin
+//VDIN_DNLP_HIST01[31:16] counts for the fourth bin
+//etc...
+//read only
+#define VDIN_DNLP_HIST00 ((0x1237 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST01 ((0x1238 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST02 ((0x1239 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST03 ((0x123a << 2) + 0xff000000)
+#define VDIN_DNLP_HIST04 ((0x123b << 2) + 0xff000000)
+#define VDIN_DNLP_HIST05 ((0x123c << 2) + 0xff000000)
+#define VDIN_DNLP_HIST06 ((0x123d << 2) + 0xff000000)
+#define VDIN_DNLP_HIST07 ((0x123e << 2) + 0xff000000)
+#define VDIN_DNLP_HIST08 ((0x123f << 2) + 0xff000000)
+#define VDIN_DNLP_HIST09 ((0x1240 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST10 ((0x1241 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST11 ((0x1242 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST12 ((0x1243 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST13 ((0x1244 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST14 ((0x1245 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST15 ((0x1246 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST16 ((0x1247 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST17 ((0x1248 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST18 ((0x1249 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST19 ((0x124a << 2) + 0xff000000)
+#define VDIN_DNLP_HIST20 ((0x124b << 2) + 0xff000000)
+#define VDIN_DNLP_HIST21 ((0x124c << 2) + 0xff000000)
+#define VDIN_DNLP_HIST22 ((0x124d << 2) + 0xff000000)
+#define VDIN_DNLP_HIST23 ((0x124e << 2) + 0xff000000)
+#define VDIN_DNLP_HIST24 ((0x124f << 2) + 0xff000000)
+#define VDIN_DNLP_HIST25 ((0x1250 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST26 ((0x1251 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST27 ((0x1252 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST28 ((0x1253 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST29 ((0x1254 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST30 ((0x1255 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST31 ((0x1256 << 2) + 0xff000000)
+//Bit 31, local dimming statistic enable
+//Bit 28, eol enable
+//Bit 27:25, vertical line overlap number for max finding
+//Bit 24:22, horizontal pixel overlap number, 0: 17 pix, 1: 9 pix, 2: 5 pix, 3: 3 pix, 4: 0 pix
+//Bit 20, 1,2,1 low pass filter enable before max/hist statistic
+//Bit 19:16, region H/V position index, refer to VDIN_LDIM_STTS_HIST_SET_REGION
+//Bit 15, 1: region read index auto increase per read to VDIN_LDIM_STTS_HIST_READ_REGION
+//Bit 6:0, region read index
+//`define VDIN_LDIM_STTS_HIST_REGION_IDX 8'h57
+//Bit 28:0, if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h0: read/write hvstart0
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h1: read/write hend01
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h2: read/write vend01
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h3: read/write hend23
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h4: read/write vend23
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h5: read/write hend45
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h6: read/write vend45
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'd7: read/write hend67
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h8: read/write vend67
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h9: read/write hend89
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'ha: read/write vend89
+//hvstart0, Bit 28:16 row0 vstart, Bit 12:0 col0 hstart
+//hend01, Bit 28:16 col1 hend, Bit 12:0 col0 hend
+//vend01, Bit 28:16 row1 vend, Bit 12:0 row0 vend
+//hend23, Bit 28:16 col3 hend, Bit 12:0 col2 hend
+//vend23, Bit 28:16 row3 vend, Bit 12:0 row2 vend
+//hend45, Bit 28:16 col5 hend, Bit 12:0 col4 hend
+//vend45, Bit 28:16 row5 vend, Bit 12:0 row4 vend
+//hend67, Bit 28:16 col7 hend, Bit 12:0 col6 hend
+//vend67, Bit 28:16 row7 vend, Bit 12:0 row6 vend
+//hend89, Bit 28:16 col9 hend, Bit 12:0 col8 hend
+//vend89, Bit 28:16 row9 vend, Bit 12:0 row8 vend
+//`define VDIN_LDIM_STTS_HIST_SET_REGION 8'h58
+//REGION STATISTIC DATA READ OUT PORT, bit 29:20 max_comp2, bit 19:10 max_comp1, bit 9:0 max_comp0
+//`define VDIN_LDIM_STTS_HIST_READ_REGION 8'h59
+//Bit 18, reset bit, high active
+//Bit 17, if true, widen hs/vs pulse
+//Bit 16 vsync total counter always accumulating enable
+//Bit 14:12, select hs/vs of video input channel to measure, 0: no selection, 1: vdi1, 2: vid2, 3: vid3, 4:vid4, 5:vdi5, 6:vid6, 7:vdi7, 8: vdi8
+//Bit 11:4, vsync_span, define how many vsync span need to measure
+//Bit 2:0 meas_hs_index, index to select which HS counter/range
+#define VDIN_MEAS_CTRL0 ((0x125a << 2) + 0xff000000)
+//Read only
+//19:16 meas_ind_total_count_n, every number of sync_span vsyncs, this count add 1
+//15:0 high bit portion of vsync total counter
+#define VDIN_MEAS_VS_COUNT_HI ((0x125b << 2) + 0xff000000)
+//Read only
+//31:0, low bit portion of vsync total counter
+#define VDIN_MEAS_VS_COUNT_LO ((0x125c << 2) + 0xff000000)
+//according to the meas_hs_index in register VDIN_MEAS_CTRL0
+//meas_hs_index == 0, first hs range
+//meas_hs_index == 1, second hs range
+//meas_hs_index == 2, third hs range
+//meas_hs_index == 3, fourth hs range
+//bit 28:16 count_start
+//bit 12:0 count_end
+#define VDIN_MEAS_HS_RANGE ((0x125d << 2) + 0xff000000)
+//Read only
+//according to the meas_hs_index in register VDIN_MEAS_CTRL0,
+//meas_hs_index == 0, first range hs counter,
+//meas_hs_index == 1, second range hs coutner
+//meas_hs_index == 2, third range hs coutner
+//meas_hs_index == 3, fourth range hs coutner
+//23:0
+#define VDIN_MEAS_HS_COUNT ((0x125e << 2) + 0xff000000)
+//Bit 8 white_enable
+//Bit 7:0 blkbar_white_level
+#define VDIN_BLKBAR_CTRL1 ((0x125f << 2) + 0xff000000)
+// Bit 31:24 blkbar_black_level threshold to judge a black point
+// Bit 23:21 Reserved
+// Bit 20:8 blkbar_hwidth left and right region width
+// Bit 7:5 blkbar_comp_sel select yin or uin or vin to be the valid input
+// Bit 4 blkbar_sw_statistic_en enable software statistic of each block black points number
+// Bit 3 blkbar_det_en
+// Bit 2:1 blkbar_din_sel
+// bit blkbar_det_top_en
+#define VDIN_BLKBAR_CTRL0 ((0x1260 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 blkbar_hstart. Left region start
+// Bit 15:13 Reserved
+// Bit 12:0 blkbar_hend. Right region end
+#define VDIN_BLKBAR_H_START_END ((0x1261 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 blkbar_vstart
+// Bit 15:13 Reserved
+// Bit 12:0 blkbar_vend
+#define VDIN_BLKBAR_V_START_END ((0x1262 << 2) + 0xff000000)
+// Bit 31:20 Reserved
+// Bit 19:0 blkbar_cnt_threshold. threshold to judge whether a block is totally black
+#define VDIN_BLKBAR_CNT_THRESHOLD ((0x1263 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 blkbar_row_th1. //threshold of the top blackbar
+// Bit 15:13 Reserved
+// bit 12:0 blkbar_row_th2 //threshold of the bottom blackbar
+#define VDIN_BLKBAR_ROW_TH1_TH2 ((0x1264 << 2) + 0xff000000)
+//Readonly
+// Bit 31:29 Reserved
+// Bit 28:16 blkbar_ind_left_start. horizontal start of the left region in the current searching
+// Bit 15:13 Reserved
+// Bit 12:0 blkbar_ind_left_end. horizontal end of the left region in the current searching
+#define VDIN_BLKBAR_IND_LEFT_START_END ((0x1265 << 2) + 0xff000000)
+//Readonly
+// Bit 31:29 Reserved
+// Bit 28:16 blkbar_ind_right_start.horizontal start of the right region in the current searching
+// Bit 15:13 Reserved
+// Bit 12:0 blkbar_ind_right_end. horizontal end of the right region in the current searching
+#define VDIN_BLKBAR_IND_RIGHT_START_END ((0x1266 << 2) + 0xff000000)
+//Readonly
+// Bit 31:20 Reserved
+// Bit 19:0 blkbar_ind_left1_cnt. Black pixel counter. left part of the left region
+#define VDIN_BLKBAR_IND_LEFT1_CNT ((0x1267 << 2) + 0xff000000)
+//Readonly
+// Bit 31:20 Reserved
+// Bit 19:0 blkbar_ind_left2_cnt. Black pixel counter. right part of the left region
+#define VDIN_BLKBAR_IND_LEFT2_CNT ((0x1268 << 2) + 0xff000000)
+//Readonly
+// Bit 31:20 Reserved
+// Bit 19:0 blkbar_ind_right1_cnt. Black pixel counter. left part of the right region
+#define VDIN_BLKBAR_IND_RIGHT1_CNT ((0x1269 << 2) + 0xff000000)
+//Readonly
+// Bit 31:20 Reserved
+// Bit 19:0 blkbar_ind_right2_cnt. Black pixel counter. right part of the right region
+#define VDIN_BLKBAR_IND_RIGHT2_CNT ((0x126a << 2) + 0xff000000)
+//Readonly
+// Bit 31:30 Resersed
+// Bit 29 blkbar_ind_black_det_done. LEFT/RIGHT Black detection done
+// Bit 28:16 blkbar_top_pos. Top black bar position
+// Bit 15:13 Reserved.
+// Bit 12:0 blkbar_bot_pos. Bottom black bar position
+#define VDIN_BLKBAR_STATUS0 ((0x126b << 2) + 0xff000000)
+//Readonly
+// Bit 31:29 Reserved
+// Bit 28:16 blkbar_left_pos. Left black bar posiont
+// Bit 15:13 Reserved
+// Bit 12:0 blkbar_right_pos. Right black bar position
+#define VDIN_BLKBAR_STATUS1 ((0x126c << 2) + 0xff000000)
+//Bit 28:16 input window H start
+//Bit 12:0 input window H end
+#define VDIN_WIN_H_START_END ((0x126d << 2) + 0xff000000)
+//Bit 28:16 input window H start
+//Bit 12:0 input window V start
+#define VDIN_WIN_V_START_END ((0x126e << 2) + 0xff000000)
+//Bit 23:16 vdi8 asfifo_ctrl
+//Bit 15:8 vdi7 asfifo_ctrl
+//Bit 7:0 vdi6 asfifo_ctrl
+#define VDIN_ASFIFO_CTRL3 ((0x126f << 2) + 0xff000000)
+//Bit 3:2 vshrk_clk2_ctrl
+//Bit 1:0 vshrk_clk1_ctrl
+#define VDIN_COM_GCLK_CTRL2 ((0x1270 << 2) + 0xff000000)
+//Bit 27 vshrk_en
+//Bit 26:25 vshrk_mode
+//Bit 24 vshrk_lpf_mode
+//Bit 23:0 vshrk_dummy
+#define VDIN_VSHRK_CTRL ((0x1271 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST32 ((0x1272 << 2) + 0xff000000)
+//Read only
+//Bit 7, vdi9 fifo overflow
+//Bit 5:0, vdi9_asfifo_cnt
+#define VDIN_COM_STATUS3 ((0x1273 << 2) + 0xff000000)
+#define VDIN_SYNC_MASK ((0x1274 << 2) + 0xff000000)
+//Bit 7:0, hsync_mask_num
+//Bit 15:8, vsync_mask_num
+//Bit 16, hsync_mask_enable
+//Bit 17, vsync_mask_num
+//dolby vdin
+#define VDIN_DOLBY_DSC_CTRL0 ((0x1275 << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_CTRL1 ((0x1276 << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_CTRL2 ((0x1277 << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_CTRL3 ((0x1278 << 2) + 0xff000000)
+#define VDIN_DOLBY_AXI_CTRL0 ((0x1279 << 2) + 0xff000000)
+#define VDIN_DOLBY_AXI_CTRL1 ((0x127a << 2) + 0xff000000)
+#define VDIN_DOLBY_AXI_CTRL2 ((0x127b << 2) + 0xff000000)
+#define VDIN_DOLBY_AXI_CTRL3 ((0x127c << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_STATUS0 ((0x127d << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_STATUS1 ((0x127e << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_STATUS2 ((0x127f << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_STATUS3 ((0x121d << 2) + 0xff000000)
+//hdr2 0x80 - -0xc0
+#define VDIN_HDR2_CTRL ((0x1280 << 2) + 0xff000000)
+#define VDIN_HDR2_CLK_GATE ((0x1281 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF00_01 ((0x1282 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF02_10 ((0x1283 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF11_12 ((0x1284 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF20_21 ((0x1285 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF22 ((0x1286 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF30_31 ((0x1287 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF32_40 ((0x1288 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF41_42 ((0x1289 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_OFFSET0_1 ((0x128a << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_OFFSET2 ((0x128b << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x128c << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_PRE_OFFSET2 ((0x128d << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF00_01 ((0x128e << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF02_10 ((0x128f << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF11_12 ((0x1290 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF20_21 ((0x1291 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF22 ((0x1292 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF30_31 ((0x1293 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF32_40 ((0x1294 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF41_42 ((0x1295 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_OFFSET0_1 ((0x1296 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_OFFSET2 ((0x1297 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x1298 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_PRE_OFFSET2 ((0x1299 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_CLIP ((0x129a << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_CLIP ((0x129b << 2) + 0xff000000)
+#define VDIN_HDR2_CGAIN_OFFT ((0x129c << 2) + 0xff000000)
+#define VDIN_EOTF_LUT_ADDR_PORT ((0x129e << 2) + 0xff000000)
+#define VDIN_EOTF_LUT_DATA_PORT ((0x129f << 2) + 0xff000000)
+#define VDIN_OETF_LUT_ADDR_PORT ((0x12a0 << 2) + 0xff000000)
+#define VDIN_OETF_LUT_DATA_PORT ((0x12a1 << 2) + 0xff000000)
+#define VDIN_CGAIN_LUT_ADDR_PORT ((0x12a2 << 2) + 0xff000000)
+#define VDIN_CGAIN_LUT_DATA_PORT ((0x12a3 << 2) + 0xff000000)
+#define VDIN_HDR2_CGAIN_COEF0 ((0x12a4 << 2) + 0xff000000)
+#define VDIN_HDR2_CGAIN_COEF1 ((0x12a5 << 2) + 0xff000000)
+#define VDIN_OGAIN_LUT_ADDR_PORT ((0x12a6 << 2) + 0xff000000)
+#define VDIN_OGAIN_LUT_DATA_PORT ((0x12a7 << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_CTRL ((0x12a8 << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_ALPHA0 ((0x12a9 << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_ALPHA1 ((0x12aa << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_BETA0 ((0x12ab << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_BETA1 ((0x12ac << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_BETA2 ((0x12ad << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_COEF0 ((0x12ae << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_COEF1 ((0x12af << 2) + 0xff000000)
+#define VDIN_HDR2_GMUT_CTRL ((0x12b0 << 2) + 0xff000000)
+#define VDIN_HDR2_GMUT_COEF0 ((0x12b1 << 2) + 0xff000000)
+#define VDIN_HDR2_GMUT_COEF1 ((0x12b2 << 2) + 0xff000000)
+#define VDIN_HDR2_GMUT_COEF2 ((0x12b3 << 2) + 0xff000000)
+#define VDIN_HDR2_GMUT_COEF3 ((0x12b4 << 2) + 0xff000000)
+#define VDIN_HDR2_GMUT_COEF4 ((0x12b5 << 2) + 0xff000000)
+#define VDIN_HDR2_PIPE_CTRL1 ((0x12b6 << 2) + 0xff000000)
+#define VDIN_HDR2_PIPE_CTRL2 ((0x12b7 << 2) + 0xff000000)
+#define VDIN_HDR2_PIPE_CTRL3 ((0x12b8 << 2) + 0xff000000)
+#define VDIN_HDR2_PROC_WIN1 ((0x12b9 << 2) + 0xff000000)
+#define VDIN_HDR2_PROC_WIN2 ((0x12ba << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_EN_CTRL ((0x12bb << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_EN_CTRL ((0x12bc << 2) + 0xff000000)
+#define VDIN_HDR2_HIST_CTRL ((0x12bd << 2) + 0xff000000)
+#define VDIN_HDR2_HIST_H_START_END ((0x12be << 2) + 0xff000000)
+#define VDIN_HDR2_HIST_V_START_END ((0x12bf << 2) + 0xff000000)
+#define VDIN_HDR2_HIST_RD ((0x129d << 2) + 0xff000000)
+#define VDIN_WRARB_MODE ((0x12c0 << 2) + 0xff000000)
+#define VDIN_WRARB_REQEN_SLV ((0x12c1 << 2) + 0xff000000)
+#define VDIN_WRARB_WEIGH0_SLV ((0x12c2 << 2) + 0xff000000)
+#define VDIN_WRARB_WEIGH1_SLV ((0x12c3 << 2) + 0xff000000)
+#define VDIN_RDWR_ARB_STATUS ((0x12c4 << 2) + 0xff000000)
+#define VDIN_ARB_DBG_CTRL ((0x12c5 << 2) + 0xff000000)
+#define VDIN_ARB_DBG_STAT ((0x12c6 << 2) + 0xff000000)
+#define VDIN_DBG_AXI_CMD_CNT ((0x12c7 << 2) + 0xff000000)
+#define VDIN_DBG_AXI_DAT_CNT ((0x12c8 << 2) + 0xff000000)
+#define VDIN_CRC_CTRL ((0x12c9 << 2) + 0xff000000)
+#define VDIN_RO_CRC ((0x12ca << 2) + 0xff000000)
+#define VDIN_LINE_INT ((0x12cb << 2) + 0xff000000)
+#define VDIN_WR_URGENT_CTRL ((0x1257 << 2) + 0xff000000)
+#define VDIN_RO_WRMIF_STATUS ((0x1258 << 2) + 0xff000000)
+//for vdin dolby descramble start
+#define VDIN_DSC_CTRL ((0x12d0 << 2) + 0xff000000)
+//Bit 31:10 reserved
+//Bit 9:4 reg_dithout_switch ,uns, default = 36;//{2'h2,2'h1,2'h0}
+//Bit 3, reg_detunnel_en ,uns, default = 1;
+//Bit 2, reg_detunnel_u_start,uns, default = 0;
+//Bit 1, reg_vdin_dith_en ,uns, default = 1;
+//Bit 0, reg_descramble_en ,uns, default = 1;
+#define VDIN_CFMT_CTRL ((0x12d1 << 2) + 0xff000000)
+//Bit 31:9 reserved
+//Bit 8 reg_chfmt_rpt_pix uns, default = 0 ; // if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
+//Bit 7:4 reg_chfmt_ini_phase uns, default = 0 ; // horizontal formatter initial phase
+//Bit 3 reg_chfmt_rpt_p0_en uns, default = 0 ; // horizontal formatter repeat pixel 0 enable
+//Bit 2:1 reg_chfmt_yc_ratio uns, default = 1 ; // horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
+//Bit 0 reg_chfmt_en uns, default = 1 ; // horizontal formatter enable
+#define VDIN_CFMT_W ((0x12d2 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_chfmt_w uns, default = 1920 ;horizontal formatter width
+//Bit 15:13 reserved
+//Bit 12:0 reg_cvfmt_w uns, default = 960 ;vertical formatter width
+#define VDIN_SCB_CTRL0 ((0x12d3 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_444c422_gofield_en uns, default = 1;
+//Bit 10 reg_tunnel_en uns, default = 1;
+//Bit 9:4 reg_tunnel_outswitch uns, default = 36;//{2'h2,2'h1,2'h0}
+//Bit 3:2 reg_444c422_mode uns, default = 0; //0:left 1:right 2,3:avg
+//Bit 1 reg_444c422_bypass uns, default = 0; 1:bypass
+//Bit 0 reserved //pulse for frm_en
+#define VDIN_SCB_CTRL1 ((0x12d4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_444c422_hsize uns, default = 1920 ;horizontal size
+//Bit 15:13 reserved
+//Bit 12:0 reg_444c422_vsize uns, default = 960 ;vertical size
+#define VDIN_DSC_HSIZE ((0x12d5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_detunnel_hsize uns, default = 1920 ;
+//Bit 15:13 reserved
+//Bit 12:0 reg_dither_hsize uns, default = 1920 ;
+#define VDIN_DSC_DETUNNEL_SEL ((0x12d6 << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:0 reg_detunnel_sel uns, default = 34658; //{3'h1,3'h0,3'h3 ,3'h5,3'h4,3'h2}
+#define VDIN_DSC_TUNNEL_SEL ((0x12d7 << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:0 reg_tunnel_sel uns, default = 69868; //= {3'h2,3'h1 ,3'h0,3'h3 ,3'h5,3'h4};
+#define VDIN_HDR2_SIZE ((0x12d8 << 2) + 0xff000000)
+#define VDIN_VSHRK_SIZE_M1 ((0x12d9 << 2) + 0xff000000)
+//dither
+#define VDIN_DITH_CTRL ((0x12e0 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_1 ((0x12e1 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_2 ((0x12e2 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_3 ((0x12e3 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_4 ((0x12e4 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_5 ((0x12e5 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_6 ((0x12e6 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_7 ((0x12e7 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_8 ((0x12e8 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_9 ((0x12e9 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_10 ((0x12ea << 2) + 0xff000000)
+#define VDIN_DITH_LUT_11 ((0x12eb << 2) + 0xff000000)
+#define VDIN_DITH_LUT_12 ((0x12ec << 2) + 0xff000000)
+//for vdin dolby descramble end
+#define VDIN_HSK_CTRL ((0x12ef << 2) + 0xff000000)
+//Bit 31:23 reserved
+//Bit 22:16 reg_hsk_size ,uns, default = 4;
+//Bit 15:13 reserved
+//Bit 12:0 reg_frm_hsize ,uns, default = 1920;
+#define VDIN_HSK_COEF_0 ((0x12f0 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef00 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_1 ((0x12f1 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef01 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_2 ((0x12f2 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef02 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_3 ((0x12f3 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef03 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+//
+#define VDIN_HSK_COEF_4 ((0x12f4 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef04 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_5 ((0x12f5 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef05 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_6 ((0x12f6 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef06 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_7 ((0x12f7 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef07 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+//
+#define VDIN_HSK_COEF_8 ((0x12f8 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef08 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_9 ((0x12f9 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef09 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_A ((0x12fa << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef10 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_B ((0x12fb << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef11 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+//
+#define VDIN_HSK_COEF_C ((0x12fc << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef12 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_D ((0x12fd << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef13 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_E ((0x12fe << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef14 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_F ((0x12ff << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef15 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_vdin_regs.h
+//
+
+//8'h72 occupied by histogram 32
+//VDIN0 8'h00 - 8'h7f
+#define VDIN0_SCALE_COEF_IDX (VDIN_SCALE_COEF_IDX )
+#define VDIN0_SCALE_COEF (VDIN_SCALE_COEF )
+#define VDIN0_COM_CTRL0 (VDIN_COM_CTRL0 )
+#define VDIN0_ACTIVE_MAX_PIX_CNT_STATUS (VDIN_ACTIVE_MAX_PIX_CNT_STATUS )
+#define VDIN0_LCNT_STATUS (VDIN_LCNT_STATUS )
+#define VDIN0_COM_STATUS0 (VDIN_COM_STATUS0 )
+#define VDIN0_COM_STATUS1 (VDIN_COM_STATUS1 )
+#define VDIN0_LCNT_SHADOW_STATUS (VDIN_LCNT_SHADOW_STATUS )
+#define VDIN0_ASFIFO_CTRL0 (VDIN_ASFIFO_CTRL0 )
+#define VDIN0_ASFIFO_CTRL1 (VDIN_ASFIFO_CTRL1 )
+#define VDIN0_WIDTHM1I_WIDTHM1O (VDIN_WIDTHM1I_WIDTHM1O )
+#define VDIN0_SC_MISC_CTRL (VDIN_SC_MISC_CTRL )
+#define VDIN0_HSC_PHASE_STEP (VDIN_HSC_PHASE_STEP )
+#define VDIN0_HSC_INI_CTRL (VDIN_HSC_INI_CTRL )
+#define VDIN0_COM_STATUS2 (VDIN_COM_STATUS2 )
+#define VDIN0_COM_STATUS3 (VDIN_COM_STATUS3 )
+#define VDIN0_ASFIFO_CTRL2 (VDIN_ASFIFO_CTRL2 )
+#define VDIN0_MATRIX_CTRL (VDIN_MATRIX_CTRL )
+#define VDIN0_MATRIX_COEF00_01 (VDIN_MATRIX_COEF00_01 )
+#define VDIN0_MATRIX_COEF02_10 (VDIN_MATRIX_COEF02_10 )
+#define VDIN0_MATRIX_COEF11_12 (VDIN_MATRIX_COEF11_12 )
+#define VDIN0_MATRIX_COEF20_21 (VDIN_MATRIX_COEF20_21 )
+#define VDIN0_MATRIX_COEF22 (VDIN_MATRIX_COEF22 )
+#define VDIN0_MATRIX_OFFSET0_1 (VDIN_MATRIX_OFFSET0_1 )
+#define VDIN0_MATRIX_OFFSET2 (VDIN_MATRIX_OFFSET2 )
+#define VDIN0_MATRIX_PRE_OFFSET0_1 (VDIN_MATRIX_PRE_OFFSET0_1 )
+#define VDIN0_MATRIX_PRE_OFFSET2 (VDIN_MATRIX_PRE_OFFSET2 )
+#define VDIN0_LFIFO_CTRL (VDIN_LFIFO_CTRL )
+#define VDIN0_COM_GCLK_CTRL (VDIN_COM_GCLK_CTRL )
+#define VDIN0_INTF_WIDTHM1 (VDIN_INTF_WIDTHM1 )
+#define VDIN0_WR_CTRL2 (VDIN_WR_CTRL2 )
+#define VDIN0_WR_CTRL (VDIN_WR_CTRL )
+#define VDIN0_WR_H_START_END (VDIN_WR_H_START_END )
+#define VDIN0_WR_V_START_END (VDIN_WR_V_START_END )
+#define VDIN0_VSC_PHASE_STEP (VDIN_VSC_PHASE_STEP )
+#define VDIN0_VSC_INI_CTRL (VDIN_VSC_INI_CTRL )
+#define VDIN0_SCIN_HEIGHTM1 (VDIN_SCIN_HEIGHTM1 )
+#define VDIN0_DUMMY_DATA (VDIN_DUMMY_DATA )
+#define VDIN0_MATRIX_PROBE_COLOR (VDIN_MATRIX_PROBE_COLOR )
+#define VDIN0_MATRIX_HL_COLOR (VDIN_MATRIX_HL_COLOR )
+#define VDIN0_MATRIX_PROBE_POS (VDIN_MATRIX_PROBE_POS )
+#define VDIN0_CHROMA_ADDR_PORT (VDIN_CHROMA_ADDR_PORT )
+#define VDIN0_CHROMA_DATA_PORT (VDIN_CHROMA_DATA_PORT )
+#define VDIN0_CM_BRI_CON_CTRL (VDIN_CM_BRI_CON_CTRL )
+#define VDIN0_GO_LINE_CTRL (VDIN_GO_LINE_CTRL )
+#define VDIN0_HIST_CTRL (VDIN_HIST_CTRL )
+#define VDIN0_HIST_H_START_END (VDIN_HIST_H_START_END )
+#define VDIN0_HIST_V_START_END (VDIN_HIST_V_START_END )
+#define VDIN0_HIST_MAX_MIN (VDIN_HIST_MAX_MIN )
+#define VDIN0_HIST_SPL_VAL (VDIN_HIST_SPL_VAL )
+#define VDIN0_HIST_SPL_PIX_CNT (VDIN_HIST_SPL_PIX_CNT )
+#define VDIN0_HIST_CHROMA_SUM (VDIN_HIST_CHROMA_SUM )
+#define VDIN0_DNLP_HIST00 (VDIN_DNLP_HIST00 )
+#define VDIN0_DNLP_HIST01 (VDIN_DNLP_HIST01 )
+#define VDIN0_DNLP_HIST02 (VDIN_DNLP_HIST02 )
+#define VDIN0_DNLP_HIST03 (VDIN_DNLP_HIST03 )
+#define VDIN0_DNLP_HIST04 (VDIN_DNLP_HIST04 )
+#define VDIN0_DNLP_HIST05 (VDIN_DNLP_HIST05 )
+#define VDIN0_DNLP_HIST06 (VDIN_DNLP_HIST06 )
+#define VDIN0_DNLP_HIST07 (VDIN_DNLP_HIST07 )
+#define VDIN0_DNLP_HIST08 (VDIN_DNLP_HIST08 )
+#define VDIN0_DNLP_HIST09 (VDIN_DNLP_HIST09 )
+#define VDIN0_DNLP_HIST10 (VDIN_DNLP_HIST10 )
+#define VDIN0_DNLP_HIST11 (VDIN_DNLP_HIST11 )
+#define VDIN0_DNLP_HIST12 (VDIN_DNLP_HIST12 )
+#define VDIN0_DNLP_HIST13 (VDIN_DNLP_HIST13 )
+#define VDIN0_DNLP_HIST14 (VDIN_DNLP_HIST14 )
+#define VDIN0_DNLP_HIST15 (VDIN_DNLP_HIST15 )
+#define VDIN0_DNLP_HIST16 (VDIN_DNLP_HIST16 )
+#define VDIN0_DNLP_HIST17 (VDIN_DNLP_HIST17 )
+#define VDIN0_DNLP_HIST18 (VDIN_DNLP_HIST18 )
+#define VDIN0_DNLP_HIST19 (VDIN_DNLP_HIST19 )
+#define VDIN0_DNLP_HIST20 (VDIN_DNLP_HIST20 )
+#define VDIN0_DNLP_HIST21 (VDIN_DNLP_HIST21 )
+#define VDIN0_DNLP_HIST22 (VDIN_DNLP_HIST22 )
+#define VDIN0_DNLP_HIST23 (VDIN_DNLP_HIST23 )
+#define VDIN0_DNLP_HIST24 (VDIN_DNLP_HIST24 )
+#define VDIN0_DNLP_HIST25 (VDIN_DNLP_HIST25 )
+#define VDIN0_DNLP_HIST26 (VDIN_DNLP_HIST26 )
+#define VDIN0_DNLP_HIST27 (VDIN_DNLP_HIST27 )
+#define VDIN0_DNLP_HIST28 (VDIN_DNLP_HIST28 )
+#define VDIN0_DNLP_HIST29 (VDIN_DNLP_HIST29 )
+#define VDIN0_DNLP_HIST30 (VDIN_DNLP_HIST30 )
+#define VDIN0_DNLP_HIST31 (VDIN_DNLP_HIST31 )
+#define VDIN0_DNLP_HIST32 (VDIN_DNLP_HIST32 )
+#define VDIN0_MEAS_CTRL0 (VDIN_MEAS_CTRL0 )
+#define VDIN0_MEAS_VS_COUNT_HI (VDIN_MEAS_VS_COUNT_HI )
+#define VDIN0_MEAS_VS_COUNT_LO (VDIN_MEAS_VS_COUNT_LO )
+#define VDIN0_MEAS_HS_RANGE (VDIN_MEAS_HS_RANGE )
+#define VDIN0_MEAS_HS_COUNT (VDIN_MEAS_HS_COUNT )
+#define VDIN0_BLKBAR_CTRL1 (VDIN_BLKBAR_CTRL1 )
+#define VDIN0_BLKBAR_CTRL0 (VDIN_BLKBAR_CTRL0 )
+#define VDIN0_BLKBAR_H_START_END (VDIN_BLKBAR_H_START_END )
+#define VDIN0_BLKBAR_V_START_END (VDIN_BLKBAR_V_START_END )
+#define VDIN0_BLKBAR_CNT_THRESHOLD (VDIN_BLKBAR_CNT_THRESHOLD )
+#define VDIN0_BLKBAR_ROW_TH1_TH2 (VDIN_BLKBAR_ROW_TH1_TH2 )
+#define VDIN0_BLKBAR_IND_LEFT_START_END (VDIN_BLKBAR_IND_LEFT_START_END )
+#define VDIN0_BLKBAR_IND_RIGHT_START_END (VDIN_BLKBAR_IND_RIGHT_START_END )
+#define VDIN0_BLKBAR_IND_LEFT1_CNT (VDIN_BLKBAR_IND_LEFT1_CNT )
+#define VDIN0_BLKBAR_IND_LEFT2_CNT (VDIN_BLKBAR_IND_LEFT2_CNT )
+#define VDIN0_BLKBAR_IND_RIGHT1_CNT (VDIN_BLKBAR_IND_RIGHT1_CNT )
+#define VDIN0_BLKBAR_IND_RIGHT2_CNT (VDIN_BLKBAR_IND_RIGHT2_CNT )
+#define VDIN0_BLKBAR_STATUS0 (VDIN_BLKBAR_STATUS0 )
+#define VDIN0_BLKBAR_STATUS1 (VDIN_BLKBAR_STATUS1 )
+#define VDIN0_WIN_H_START_END (VDIN_WIN_H_START_END )
+#define VDIN0_WIN_V_START_END (VDIN_WIN_V_START_END )
+#define VDIN0_ASFIFO_CTRL3 (VDIN_ASFIFO_CTRL3 )
+#define VDIN0_LFIFO_URG_CTRL (VDIN_LFIFO_URG_CTRL )
+#define VDIN0_COM_GCLK_CTRL2 (VDIN_COM_GCLK_CTRL2 )
+#define VDIN0_VSHRK_CTRL (VDIN_VSHRK_CTRL )
+#define VDIN0_SYNC_MASK (VDIN_SYNC_MASK )
+#define VDIN0_DOLBY_DSC_CTRL0 (VDIN_DOLBY_DSC_CTRL0 )
+#define VDIN0_DOLBY_DSC_CTRL1 (VDIN_DOLBY_DSC_CTRL1 )
+#define VDIN0_DOLBY_DSC_CTRL2 (VDIN_DOLBY_DSC_CTRL2 )
+#define VDIN0_DOLBY_DSC_CTRL3 (VDIN_DOLBY_DSC_CTRL3 )
+#define VDIN0_DOLBY_AXI_CTRL0 (VDIN_DOLBY_AXI_CTRL0 )
+#define VDIN0_DOLBY_AXI_CTRL1 (VDIN_DOLBY_AXI_CTRL1 )
+#define VDIN0_DOLBY_AXI_CTRL2 (VDIN_DOLBY_AXI_CTRL2 )
+#define VDIN0_DOLBY_AXI_CTRL3 (VDIN_DOLBY_AXI_CTRL3 )
+#define VDIN0_DOLBY_DSC_STATUS0 (VDIN_DOLBY_DSC_STATUS0)
+#define VDIN0_DOLBY_DSC_STATUS1 (VDIN_DOLBY_DSC_STATUS1)
+#define VDIN0_DOLBY_DSC_STATUS2 (VDIN_DOLBY_DSC_STATUS2)
+#define VDIN0_DOLBY_DSC_STATUS3 (VDIN_DOLBY_DSC_STATUS3)
+#define VDIN0_HDR2_CTRL VDIN_HDR2_CTRL
+#define VDIN0_HDR2_CLK_GATE VDIN_HDR2_CLK_GATE
+#define VDIN0_HDR2_MATRIXI_COEF00_01 VDIN_HDR2_MATRIXI_COEF00_01
+#define VDIN0_HDR2_MATRIXI_COEF02_10 VDIN_HDR2_MATRIXI_COEF02_10
+#define VDIN0_HDR2_MATRIXI_COEF11_12 VDIN_HDR2_MATRIXI_COEF11_12
+#define VDIN0_HDR2_MATRIXI_COEF20_21 VDIN_HDR2_MATRIXI_COEF20_21
+#define VDIN0_HDR2_MATRIXI_COEF22 VDIN_HDR2_MATRIXI_COEF22
+#define VDIN0_HDR2_MATRIXI_COEF30_31 VDIN_HDR2_MATRIXI_COEF30_31
+#define VDIN0_HDR2_MATRIXI_COEF32_40 VDIN_HDR2_MATRIXI_COEF32_40
+#define VDIN0_HDR2_MATRIXI_COEF41_42 VDIN_HDR2_MATRIXI_COEF41_42
+#define VDIN0_HDR2_MATRIXI_OFFSET0_1 VDIN_HDR2_MATRIXI_OFFSET0_1
+#define VDIN0_HDR2_MATRIXI_OFFSET2 VDIN_HDR2_MATRIXI_OFFSET2
+#define VDIN0_HDR2_MATRIXI_PRE_OFFSET0_1 VDIN_HDR2_MATRIXI_PRE_OFFSET0_1
+#define VDIN0_HDR2_MATRIXI_PRE_OFFSET2 VDIN_HDR2_MATRIXI_PRE_OFFSET2
+#define VDIN0_HDR2_MATRIXO_COEF00_01 VDIN_HDR2_MATRIXO_COEF00_01
+#define VDIN0_HDR2_MATRIXO_COEF02_10 VDIN_HDR2_MATRIXO_COEF02_10
+#define VDIN0_HDR2_MATRIXO_COEF11_12 VDIN_HDR2_MATRIXO_COEF11_12
+#define VDIN0_HDR2_MATRIXO_COEF20_21 VDIN_HDR2_MATRIXO_COEF20_21
+#define VDIN0_HDR2_MATRIXO_COEF22 VDIN_HDR2_MATRIXO_COEF22
+#define VDIN0_HDR2_MATRIXO_COEF30_31 VDIN_HDR2_MATRIXO_COEF30_31
+#define VDIN0_HDR2_MATRIXO_COEF32_40 VDIN_HDR2_MATRIXO_COEF32_40
+#define VDIN0_HDR2_MATRIXO_COEF41_42 VDIN_HDR2_MATRIXO_COEF41_42
+#define VDIN0_HDR2_MATRIXO_OFFSET0_1 VDIN_HDR2_MATRIXO_OFFSET0_1
+#define VDIN0_HDR2_MATRIXO_OFFSET2 VDIN_HDR2_MATRIXO_OFFSET2
+#define VDIN0_HDR2_MATRIXO_PRE_OFFSET0_1 VDIN_HDR2_MATRIXO_PRE_OFFSET0_1
+#define VDIN0_HDR2_MATRIXO_PRE_OFFSET2 VDIN_HDR2_MATRIXO_PRE_OFFSET2
+#define VDIN0_HDR2_MATRIXI_CLIP VDIN_HDR2_MATRIXI_CLIP
+#define VDIN0_HDR2_MATRIXO_CLIP VDIN_HDR2_MATRIXO_CLIP
+#define VDIN0_HDR2_CGAIN_OFFT VDIN_HDR2_CGAIN_OFFT
+#define VDIN0_EOTF_LUT_ADDR_PORT VDIN_EOTF_LUT_ADDR_PORT
+#define VDIN0_EOTF_LUT_DATA_PORT VDIN_EOTF_LUT_DATA_PORT
+#define VDIN0_OETF_LUT_ADDR_PORT VDIN_OETF_LUT_ADDR_PORT
+#define VDIN0_OETF_LUT_DATA_PORT VDIN_OETF_LUT_DATA_PORT
+#define VDIN0_OGAIN_LUT_ADDR_PORT VDIN_OGAIN_LUT_ADDR_PORT
+#define VDIN0_OGAIN_LUT_DATA_PORT VDIN_OGAIN_LUT_DATA_PORT
+#define VDIN0_CGAIN_LUT_ADDR_PORT VDIN_CGAIN_LUT_ADDR_PORT
+#define VDIN0_CGAIN_LUT_DATA_PORT VDIN_CGAIN_LUT_DATA_PORT
+#define VDIN0_HDR2_CGAIN_COEF0 VDIN_HDR2_CGAIN_COEF0
+#define VDIN0_HDR2_CGAIN_COEF1 VDIN_HDR2_CGAIN_COEF1
+#define VDIN0_HDR2_ADPS_CTRL VDIN_HDR2_ADPS_CTRL
+#define VDIN0_HDR2_ADPS_ALPHA0 VDIN_HDR2_ADPS_ALPHA0
+#define VDIN0_HDR2_ADPS_ALPHA1 VDIN_HDR2_ADPS_ALPHA1
+#define VDIN0_HDR2_ADPS_BETA0 VDIN_HDR2_ADPS_BETA0
+#define VDIN0_HDR2_ADPS_BETA1 VDIN_HDR2_ADPS_BETA1
+#define VDIN0_HDR2_ADPS_BETA2 VDIN_HDR2_ADPS_BETA2
+#define VDIN0_HDR2_ADPS_COEF0 VDIN_HDR2_ADPS_COEF0
+#define VDIN0_HDR2_ADPS_COEF1 VDIN_HDR2_ADPS_COEF1
+#define VDIN0_HDR2_GMUT_CTRL VDIN_HDR2_GMUT_CTRL
+#define VDIN0_HDR2_GMUT_COEF0 VDIN_HDR2_GMUT_COEF0
+#define VDIN0_HDR2_GMUT_COEF1 VDIN_HDR2_GMUT_COEF1
+#define VDIN0_HDR2_GMUT_COEF2 VDIN_HDR2_GMUT_COEF2
+#define VDIN0_HDR2_GMUT_COEF3 VDIN_HDR2_GMUT_COEF3
+#define VDIN0_HDR2_GMUT_COEF4 VDIN_HDR2_GMUT_COEF4
+#define VDIN0_HDR2_PIPE_CTRL1 VDIN_HDR2_PIPE_CTRL1
+#define VDIN0_HDR2_PIPE_CTRL2 VDIN_HDR2_PIPE_CTRL2
+#define VDIN0_HDR2_PIPE_CTRL3 VDIN_HDR2_PIPE_CTRL3
+#define VDIN0_HDR2_PROC_WIN1 VDIN_HDR2_PROC_WIN1
+#define VDIN0_HDR2_PROC_WIN2 VDIN_HDR2_PROC_WIN2
+#define VDIN0_HDR2_MATRIXI_EN_CTRL VDIN_HDR2_MATRIXI_EN_CTRL
+#define VDIN0_HDR2_MATRIXO_EN_CTRL VDIN_HDR2_MATRIXO_EN_CTRL
+#define VDIN0_HDR2_HIST_CTRL VDIN_HDR2_HIST_CTRL
+#define VDIN0_HDR2_HIST_H_START_END VDIN_HDR2_HIST_H_START_END
+#define VDIN0_HDR2_HIST_V_START_END VDIN_HDR2_HIST_V_START_END
+#define VDIN0_HDR2_HIST_RD VDIN_HDR2_HIST_RD
+
+
+#define VDIN0_CRC_CTRL (VDIN_CRC_CTRL)
+#define VDIN0_RO_CRC (VDIN_RO_CRC )
+#define VDIN0_LINE_INT (VDIN_LINE_INT)
+#define VDIN0_WR_URGENT_CTRL (VDIN_WR_URGENT_CTRL)
+#define VDIN0_RO_WRMIF_STATUS (VDIN_RO_WRMIF_STATUS)
+
+#define VDIN0_DSC_CTRL VDIN_DSC_CTRL
+#define VDIN0_CFMT_CTRL VDIN_CFMT_CTRL
+#define VDIN0_CFMT_W VDIN_CFMT_W
+#define VDIN0_SCB_CTRL0 VDIN_SCB_CTRL0
+#define VDIN0_SCB_CTRL1 VDIN_SCB_CTRL1
+#define VDIN0_DSC_HSIZE VDIN_DSC_HSIZE
+#define VDIN0_DSC_DETUNNEL_SEL VDIN_DSC_DETUNNEL_SEL
+#define VDIN0_DSC_TUNNEL_SEL VDIN_DSC_TUNNEL_SEL
+#define VDIN0_DITH_CTRL VDIN_DITH_CTRL
+#define VDIN0_DITH_LUT_1 VDIN_DITH_LUT_1
+#define VDIN0_DITH_LUT_2 VDIN_DITH_LUT_2
+#define VDIN0_DITH_LUT_3 VDIN_DITH_LUT_3
+#define VDIN0_DITH_LUT_4 VDIN_DITH_LUT_4
+#define VDIN0_DITH_LUT_5 VDIN_DITH_LUT_5
+#define VDIN0_DITH_LUT_6 VDIN_DITH_LUT_6
+#define VDIN0_DITH_LUT_7 VDIN_DITH_LUT_7
+#define VDIN0_DITH_LUT_8 VDIN_DITH_LUT_8
+#define VDIN0_DITH_LUT_9 VDIN_DITH_LUT_9
+#define VDIN0_DITH_LUT_10 VDIN_DITH_LUT_10
+#define VDIN0_DITH_LUT_11 VDIN_DITH_LUT_11
+#define VDIN0_DITH_LUT_12 VDIN_DITH_LUT_12
+
+#define VDIN0_HSK_CTRL VDIN_HSK_CTRL
+#define VDIN0_HSK_COEF_0 VDIN_HSK_COEF_0
+#define VDIN0_HSK_COEF_1 VDIN_HSK_COEF_1
+#define VDIN0_HSK_COEF_2 VDIN_HSK_COEF_2
+#define VDIN0_HSK_COEF_3 VDIN_HSK_COEF_3
+#define VDIN0_HSK_COEF_4 VDIN_HSK_COEF_4
+#define VDIN0_HSK_COEF_5 VDIN_HSK_COEF_5
+#define VDIN0_HSK_COEF_6 VDIN_HSK_COEF_6
+#define VDIN0_HSK_COEF_7 VDIN_HSK_COEF_7
+#define VDIN0_HSK_COEF_8 VDIN_HSK_COEF_8
+#define VDIN0_HSK_COEF_9 VDIN_HSK_COEF_9
+#define VDIN0_HSK_COEF_A VDIN_HSK_COEF_A
+#define VDIN0_HSK_COEF_B VDIN_HSK_COEF_B
+#define VDIN0_HSK_COEF_C VDIN_HSK_COEF_C
+#define VDIN0_HSK_COEF_D VDIN_HSK_COEF_D
+#define VDIN0_HSK_COEF_E VDIN_HSK_COEF_E
+#define VDIN0_HSK_COEF_F VDIN_HSK_COEF_F
+
+#define VDIN0_HDR2_SIZE VDIN_HDR2_SIZE
+#define VDIN0_VSHRK_SIZE_M1 VDIN_VSHRK_SIZE_M1
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_vdin0_regs.h
+//
+//
+// Reading file: vpu_vdin1_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+// VDIN
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VDIN1_VCBUS_BASE = 0x13
+// -----------------------------------------------
+#define VDIN1_OFFSET (0x100)
+// `include "vpu_vdin_regs.h"
+//8'h72 occupied by histogram 32
+//VDIN1 8'h00 - 8'h7f
+#define VDIN1_SCALE_COEF_IDX ((VDIN1_OFFSET << 2) + VDIN_SCALE_COEF_IDX )
+#define VDIN1_SCALE_COEF ((VDIN1_OFFSET << 2) + VDIN_SCALE_COEF )
+#define VDIN1_COM_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_COM_CTRL0 )
+#define VDIN1_ACTIVE_MAX_PIX_CNT_STATUS ((VDIN1_OFFSET << 2) + VDIN_ACTIVE_MAX_PIX_CNT_STATUS )
+#define VDIN1_LCNT_STATUS ((VDIN1_OFFSET << 2) + VDIN_LCNT_STATUS )
+#define VDIN1_COM_STATUS0 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS0 )
+#define VDIN1_COM_STATUS1 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS1 )
+#define VDIN1_LCNT_SHADOW_STATUS ((VDIN1_OFFSET << 2) + VDIN_LCNT_SHADOW_STATUS )
+#define VDIN1_ASFIFO_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL0 )
+#define VDIN1_ASFIFO_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL1 )
+#define VDIN1_WIDTHM1I_WIDTHM1O ((VDIN1_OFFSET << 2) + VDIN_WIDTHM1I_WIDTHM1O )
+#define VDIN1_SC_MISC_CTRL ((VDIN1_OFFSET << 2) + VDIN_SC_MISC_CTRL )
+#define VDIN1_HSC_PHASE_STEP ((VDIN1_OFFSET << 2) + VDIN_HSC_PHASE_STEP )
+#define VDIN1_HSC_INI_CTRL ((VDIN1_OFFSET << 2) + VDIN_HSC_INI_CTRL )
+#define VDIN1_COM_STATUS2 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS2 )
+#define VDIN1_COM_STATUS3 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS3 )
+#define VDIN1_ASFIFO_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL2 )
+#define VDIN1_MATRIX_CTRL ((VDIN1_OFFSET << 2) + VDIN_MATRIX_CTRL )
+#define VDIN1_MATRIX_COEF00_01 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF00_01 )
+#define VDIN1_MATRIX_COEF02_10 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF02_10 )
+#define VDIN1_MATRIX_COEF11_12 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF11_12 )
+#define VDIN1_MATRIX_COEF20_21 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF20_21 )
+#define VDIN1_MATRIX_COEF22 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF22 )
+#define VDIN1_MATRIX_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_OFFSET0_1 )
+#define VDIN1_MATRIX_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_OFFSET2 )
+#define VDIN1_MATRIX_PRE_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PRE_OFFSET0_1 )
+#define VDIN1_MATRIX_PRE_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PRE_OFFSET2 )
+#define VDIN1_LFIFO_CTRL ((VDIN1_OFFSET << 2) + VDIN_LFIFO_CTRL )
+#define VDIN1_COM_GCLK_CTRL ((VDIN1_OFFSET << 2) + VDIN_COM_GCLK_CTRL )
+#define VDIN1_INTF_WIDTHM1 ((VDIN1_OFFSET << 2) + VDIN_INTF_WIDTHM1 )
+#define VDIN1_WR_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_WR_CTRL2 )
+#define VDIN1_WR_CTRL ((VDIN1_OFFSET << 2) + VDIN_WR_CTRL )
+#define VDIN1_WR_H_START_END ((VDIN1_OFFSET << 2) + VDIN_WR_H_START_END )
+#define VDIN1_WR_V_START_END ((VDIN1_OFFSET << 2) + VDIN_WR_V_START_END )
+#define VDIN1_VSC_PHASE_STEP ((VDIN1_OFFSET << 2) + VDIN_VSC_PHASE_STEP )
+#define VDIN1_VSC_INI_CTRL ((VDIN1_OFFSET << 2) + VDIN_VSC_INI_CTRL )
+#define VDIN1_SCIN_HEIGHTM1 ((VDIN1_OFFSET << 2) + VDIN_SCIN_HEIGHTM1 )
+#define VDIN1_DUMMY_DATA ((VDIN1_OFFSET << 2) + VDIN_DUMMY_DATA )
+#define VDIN1_MATRIX_PROBE_COLOR ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PROBE_COLOR )
+#define VDIN1_MATRIX_HL_COLOR ((VDIN1_OFFSET << 2) + VDIN_MATRIX_HL_COLOR )
+#define VDIN1_MATRIX_PROBE_POS ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PROBE_POS )
+#define VDIN1_CHROMA_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_CHROMA_ADDR_PORT )
+#define VDIN1_CHROMA_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_CHROMA_DATA_PORT )
+#define VDIN1_CM_BRI_CON_CTRL ((VDIN1_OFFSET << 2) + VDIN_CM_BRI_CON_CTRL )
+#define VDIN1_GO_LINE_CTRL ((VDIN1_OFFSET << 2) + VDIN_GO_LINE_CTRL )
+#define VDIN1_HIST_CTRL ((VDIN1_OFFSET << 2) + VDIN_HIST_CTRL )
+#define VDIN1_HIST_H_START_END ((VDIN1_OFFSET << 2) + VDIN_HIST_H_START_END )
+#define VDIN1_HIST_V_START_END ((VDIN1_OFFSET << 2) + VDIN_HIST_V_START_END )
+#define VDIN1_HIST_MAX_MIN ((VDIN1_OFFSET << 2) + VDIN_HIST_MAX_MIN )
+#define VDIN1_HIST_SPL_VAL ((VDIN1_OFFSET << 2) + VDIN_HIST_SPL_VAL )
+#define VDIN1_HIST_SPL_PIX_CNT ((VDIN1_OFFSET << 2) + VDIN_HIST_SPL_PIX_CNT )
+#define VDIN1_HIST_CHROMA_SUM ((VDIN1_OFFSET << 2) + VDIN_HIST_CHROMA_SUM )
+#define VDIN1_DNLP_HIST00 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST00 )
+#define VDIN1_DNLP_HIST01 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST01 )
+#define VDIN1_DNLP_HIST02 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST02 )
+#define VDIN1_DNLP_HIST03 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST03 )
+#define VDIN1_DNLP_HIST04 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST04 )
+#define VDIN1_DNLP_HIST05 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST05 )
+#define VDIN1_DNLP_HIST06 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST06 )
+#define VDIN1_DNLP_HIST07 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST07 )
+#define VDIN1_DNLP_HIST08 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST08 )
+#define VDIN1_DNLP_HIST09 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST09 )
+#define VDIN1_DNLP_HIST10 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST10 )
+#define VDIN1_DNLP_HIST11 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST11 )
+#define VDIN1_DNLP_HIST12 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST12 )
+#define VDIN1_DNLP_HIST13 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST13 )
+#define VDIN1_DNLP_HIST14 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST14 )
+#define VDIN1_DNLP_HIST15 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST15 )
+#define VDIN1_DNLP_HIST16 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST16 )
+#define VDIN1_DNLP_HIST17 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST17 )
+#define VDIN1_DNLP_HIST18 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST18 )
+#define VDIN1_DNLP_HIST19 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST19 )
+#define VDIN1_DNLP_HIST20 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST20 )
+#define VDIN1_DNLP_HIST21 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST21 )
+#define VDIN1_DNLP_HIST22 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST22 )
+#define VDIN1_DNLP_HIST23 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST23 )
+#define VDIN1_DNLP_HIST24 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST24 )
+#define VDIN1_DNLP_HIST25 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST25 )
+#define VDIN1_DNLP_HIST26 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST26 )
+#define VDIN1_DNLP_HIST27 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST27 )
+#define VDIN1_DNLP_HIST28 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST28 )
+#define VDIN1_DNLP_HIST29 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST29 )
+#define VDIN1_DNLP_HIST30 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST30 )
+#define VDIN1_DNLP_HIST31 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST31 )
+#define VDIN1_DNLP_HIST32 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST32 )
+#define VDIN1_MEAS_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_MEAS_CTRL0 )
+#define VDIN1_MEAS_VS_COUNT_HI ((VDIN1_OFFSET << 2) + VDIN_MEAS_VS_COUNT_HI )
+#define VDIN1_MEAS_VS_COUNT_LO ((VDIN1_OFFSET << 2) + VDIN_MEAS_VS_COUNT_LO )
+#define VDIN1_MEAS_HS_RANGE ((VDIN1_OFFSET << 2) + VDIN_MEAS_HS_RANGE )
+#define VDIN1_MEAS_HS_COUNT ((VDIN1_OFFSET << 2) + VDIN_MEAS_HS_COUNT )
+#define VDIN1_BLKBAR_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_CTRL1 )
+#define VDIN1_BLKBAR_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_CTRL0 )
+#define VDIN1_BLKBAR_H_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_H_START_END )
+#define VDIN1_BLKBAR_V_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_V_START_END )
+#define VDIN1_BLKBAR_CNT_THRESHOLD ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_CNT_THRESHOLD )
+#define VDIN1_BLKBAR_ROW_TH1_TH2 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_ROW_TH1_TH2 )
+#define VDIN1_BLKBAR_IND_LEFT_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_LEFT_START_END )
+#define VDIN1_BLKBAR_IND_RIGHT_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_RIGHT_START_END )
+#define VDIN1_BLKBAR_IND_LEFT1_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_LEFT1_CNT )
+#define VDIN1_BLKBAR_IND_LEFT2_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_LEFT2_CNT )
+#define VDIN1_BLKBAR_IND_RIGHT1_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_RIGHT1_CNT )
+#define VDIN1_BLKBAR_IND_RIGHT2_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_RIGHT2_CNT )
+#define VDIN1_BLKBAR_STATUS0 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_STATUS0 )
+#define VDIN1_BLKBAR_STATUS1 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_STATUS1 )
+#define VDIN1_WIN_H_START_END ((VDIN1_OFFSET << 2) + VDIN_WIN_H_START_END )
+#define VDIN1_WIN_V_START_END ((VDIN1_OFFSET << 2) + VDIN_WIN_V_START_END )
+#define VDIN1_ASFIFO_CTRL3 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL3 )
+#define VDIN1_LFIFO_URG_CTRL ((VDIN1_OFFSET << 2) + VDIN_LFIFO_URG_CTRL )
+#define VDIN1_COM_GCLK_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_COM_GCLK_CTRL2 )
+#define VDIN1_VSHRK_CTRL ((VDIN1_OFFSET << 2) + VDIN_VSHRK_CTRL )
+#define VDIN1_SYNC_MASK ((VDIN1_OFFSET << 2) + VDIN_SYNC_MASK )
+#define VDIN1_DOLBY_DSC_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL0 )
+#define VDIN1_DOLBY_DSC_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL1 )
+#define VDIN1_DOLBY_DSC_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL2 )
+#define VDIN1_DOLBY_DSC_CTRL3 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL3 )
+#define VDIN1_DOLBY_AXI_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL0 )
+#define VDIN1_DOLBY_AXI_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL1 )
+#define VDIN1_DOLBY_AXI_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL2 )
+#define VDIN1_DOLBY_AXI_CTRL3 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL3 )
+#define VDIN1_DOLBY_DSC_STATUS0 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS0)
+#define VDIN1_DOLBY_DSC_STATUS1 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS1)
+#define VDIN1_DOLBY_DSC_STATUS2 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS2)
+#define VDIN1_DOLBY_DSC_STATUS3 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS3)
+
+#define VDIN1_HDR2_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_CTRL )
+#define VDIN1_HDR2_CLK_GATE ((VDIN1_OFFSET << 2) + VDIN_HDR2_CLK_GATE )
+#define VDIN1_HDR2_MATRIXI_COEF00_01 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF00_01 )
+#define VDIN1_HDR2_MATRIXI_COEF02_10 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF02_10 )
+#define VDIN1_HDR2_MATRIXI_COEF11_12 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF11_12 )
+#define VDIN1_HDR2_MATRIXI_COEF20_21 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF20_21 )
+#define VDIN1_HDR2_MATRIXI_COEF22 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF22 )
+#define VDIN1_HDR2_MATRIXI_COEF30_31 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF30_31 )
+#define VDIN1_HDR2_MATRIXI_COEF32_40 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF32_40 )
+#define VDIN1_HDR2_MATRIXI_COEF41_42 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF41_42 )
+#define VDIN1_HDR2_MATRIXI_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_OFFSET0_1 )
+#define VDIN1_HDR2_MATRIXI_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_OFFSET2 )
+#define VDIN1_HDR2_MATRIXI_PRE_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_PRE_OFFSET0_1 )
+#define VDIN1_HDR2_MATRIXI_PRE_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_PRE_OFFSET2 )
+#define VDIN1_HDR2_MATRIXO_COEF00_01 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF00_01 )
+#define VDIN1_HDR2_MATRIXO_COEF02_10 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF02_10 )
+#define VDIN1_HDR2_MATRIXO_COEF11_12 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF11_12 )
+#define VDIN1_HDR2_MATRIXO_COEF20_21 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF20_21 )
+#define VDIN1_HDR2_MATRIXO_COEF22 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF22 )
+#define VDIN1_HDR2_MATRIXO_COEF30_31 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF30_31 )
+#define VDIN1_HDR2_MATRIXO_COEF32_40 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF32_40 )
+#define VDIN1_HDR2_MATRIXO_COEF41_42 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF41_42 )
+#define VDIN1_HDR2_MATRIXO_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_OFFSET0_1 )
+#define VDIN1_HDR2_MATRIXO_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_OFFSET2 )
+#define VDIN1_HDR2_MATRIXO_PRE_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_PRE_OFFSET0_1 )
+#define VDIN1_HDR2_MATRIXO_PRE_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_PRE_OFFSET2 )
+#define VDIN1_HDR2_MATRIXI_CLIP ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_CLIP )
+#define VDIN1_HDR2_MATRIXO_CLIP ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_CLIP )
+#define VDIN1_HDR2_CGAIN_OFFT ((VDIN1_OFFSET << 2) + VDIN_HDR2_CGAIN_OFFT )
+#define VDIN1_EOTF_LUT_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_EOTF_LUT_ADDR_PORT )
+#define VDIN1_EOTF_LUT_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_EOTF_LUT_DATA_PORT )
+#define VDIN1_OETF_LUT_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_OETF_LUT_ADDR_PORT )
+#define VDIN1_OETF_LUT_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_OETF_LUT_DATA_PORT )
+#define VDIN1_OGAIN_LUT_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_OGAIN_LUT_ADDR_PORT )
+#define VDIN1_OGAIN_LUT_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_OGAIN_LUT_DATA_PORT )
+#define VDIN1_CGAIN_LUT_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_CGAIN_LUT_ADDR_PORT )
+#define VDIN1_CGAIN_LUT_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_CGAIN_LUT_DATA_PORT )
+#define VDIN1_HDR2_CGAIN_COEF0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_CGAIN_COEF0 )
+#define VDIN1_HDR2_CGAIN_COEF1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_CGAIN_COEF1 )
+#define VDIN1_HDR2_ADPS_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_CTRL )
+#define VDIN1_HDR2_ADPS_ALPHA0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_ALPHA0 )
+#define VDIN1_HDR2_ADPS_ALPHA1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_ALPHA1 )
+#define VDIN1_HDR2_ADPS_BETA0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_BETA0 )
+#define VDIN1_HDR2_ADPS_BETA1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_BETA1 )
+#define VDIN1_HDR2_ADPS_BETA2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_BETA2 )
+#define VDIN1_HDR2_ADPS_COEF0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_COEF0 )
+#define VDIN1_HDR2_ADPS_COEF1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_COEF1 )
+#define VDIN1_HDR2_GMUT_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_CTRL )
+#define VDIN1_HDR2_GMUT_COEF0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF0 )
+#define VDIN1_HDR2_GMUT_COEF1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF1 )
+#define VDIN1_HDR2_GMUT_COEF2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF2 )
+#define VDIN1_HDR2_GMUT_COEF3 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF3 )
+#define VDIN1_HDR2_GMUT_COEF4 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF4 )
+#define VDIN1_HDR2_PIPE_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PIPE_CTRL1 )
+#define VDIN1_HDR2_PIPE_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PIPE_CTRL2 )
+#define VDIN1_HDR2_PIPE_CTRL3 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PIPE_CTRL3 )
+#define VDIN1_HDR2_PROC_WIN1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PROC_WIN1 )
+#define VDIN1_HDR2_PROC_WIN2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PROC_WIN2 )
+#define VDIN1_HDR2_MATRIXI_EN_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_EN_CTRL )
+#define VDIN1_HDR2_MATRIXO_EN_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_EN_CTRL )
+#define VDIN1_HDR2_HIST_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_HIST_CTRL )
+#define VDIN1_HDR2_HIST_H_START_END ((VDIN1_OFFSET << 2) + VDIN_HDR2_HIST_H_START_END )
+#define VDIN1_HDR2_HIST_V_START_END ((VDIN1_OFFSET << 2) + VDIN_HDR2_HIST_V_START_END )
+#define VDIN1_HDR2_HIST_RD ((VDIN1_OFFSET << 2) + VDIN_HDR2_HIST_RD )
+
+
+
+#define VDIN1_CRC_CTRL ((VDIN1_OFFSET << 2) + VDIN_CRC_CTRL)
+#define VDIN1_RO_CRC ((VDIN1_OFFSET << 2) + VDIN_RO_CRC )
+#define VDIN1_LINE_INT ((VDIN1_OFFSET << 2) + VDIN_LINE_INT)
+#define VDIN1_WR_URGENT_CTRL ((VDIN1_OFFSET << 2) + VDIN_WR_URGENT_CTRL)
+#define VDIN1_RO_WRMIF_STATUS ((VDIN1_OFFSET << 2) + VDIN_RO_WRMIF_STATUS)
+
+#define VDIN1_DSC_CTRL ((VDIN1_OFFSET << 2) + VDIN_DSC_CTRL )
+#define VDIN1_CFMT_CTRL ((VDIN1_OFFSET << 2) + VDIN_CFMT_CTRL )
+#define VDIN1_CFMT_W ((VDIN1_OFFSET << 2) + VDIN_CFMT_W )
+#define VDIN1_SCB_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_SCB_CTRL0 )
+#define VDIN1_SCB_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_SCB_CTRL1 )
+#define VDIN1_DSC_HSIZE ((VDIN1_OFFSET << 2) + VDIN_DSC_HSIZE )
+#define VDIN1_DSC_DETUNNEL_SEL ((VDIN1_OFFSET << 2) + VDIN_DSC_DETUNNEL_SEL)
+#define VDIN1_DSC_TUNNEL_SEL ((VDIN1_OFFSET << 2) + VDIN_DSC_TUNNEL_SEL)
+#define VDIN1_DITH_CTRL ((VDIN1_OFFSET << 2) + VDIN_DITH_CTRL )
+#define VDIN1_DITH_LUT_1 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_1 )
+#define VDIN1_DITH_LUT_2 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_2 )
+#define VDIN1_DITH_LUT_3 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_3 )
+#define VDIN1_DITH_LUT_4 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_4 )
+#define VDIN1_DITH_LUT_5 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_5 )
+#define VDIN1_DITH_LUT_6 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_6 )
+#define VDIN1_DITH_LUT_7 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_7 )
+#define VDIN1_DITH_LUT_8 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_8 )
+#define VDIN1_DITH_LUT_9 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_9 )
+#define VDIN1_DITH_LUT_10 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_10 )
+#define VDIN1_DITH_LUT_11 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_11 )
+#define VDIN1_DITH_LUT_12 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_12 )
+
+#define VDIN1_HSK_CTRL ((VDIN1_OFFSET << 2) + VDIN_HSK_CTRL )
+#define VDIN1_HSK_COEF_0 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_0 )
+#define VDIN1_HSK_COEF_1 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_1 )
+#define VDIN1_HSK_COEF_2 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_2 )
+#define VDIN1_HSK_COEF_3 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_3 )
+#define VDIN1_HSK_COEF_4 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_4 )
+#define VDIN1_HSK_COEF_5 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_5 )
+#define VDIN1_HSK_COEF_6 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_6 )
+#define VDIN1_HSK_COEF_7 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_7 )
+#define VDIN1_HSK_COEF_8 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_8 )
+#define VDIN1_HSK_COEF_9 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_9 )
+#define VDIN1_HSK_COEF_A ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_A )
+#define VDIN1_HSK_COEF_B ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_B )
+#define VDIN1_HSK_COEF_C ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_C )
+#define VDIN1_HSK_COEF_D ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_D )
+#define VDIN1_HSK_COEF_E ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_E )
+#define VDIN1_HSK_COEF_F ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_F )
+
+#define VDIN1_HDR2_SIZE ((VDIN1_OFFSET << 2) + VDIN_HDR2_SIZE )
+#define VDIN1_VSHRK_SIZE_M1 ((VDIN1_OFFSET << 2) + VDIN_VSHRK_SIZE_M1)
+
+
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_vdin1_regs.h
+//
+//
+// Reading file: lcd_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: LCD_VCBUS_BASE = 0x14
+// -----------------------------------------------
+//========================================================================
+//LCD DRV 12'h480~12'h4ef
+//=======================================================================
+#define L_GAMMA_CNTL_PORT ((0x1400 << 2) + 0xff000000)
+#define L_GAMMA_DATA_PORT ((0x1401 << 2) + 0xff000000)
+#define L_GAMMA_ADDR_PORT ((0x1402 << 2) + 0xff000000)
+#define L_GAMMA_VCOM_HSWITCH_ADDR ((0x1403 << 2) + 0xff000000)
+#define L_RGB_BASE_ADDR ((0x1405 << 2) + 0xff000000)
+#define L_RGB_COEFF_ADDR ((0x1406 << 2) + 0xff000000)
+#define L_POL_CNTL_ADDR ((0x1407 << 2) + 0xff000000)
+#define L_DITH_CNTL_ADDR ((0x1408 << 2) + 0xff000000)
+#define L_GAMMA_PROBE_CTRL ((0x1409 << 2) + 0xff000000)
+//read only
+#define L_GAMMA_PROBE_COLOR_L ((0x140a << 2) + 0xff000000)
+#define L_GAMMA_PROBE_COLOR_H ((0x140b << 2) + 0xff000000)
+#define L_GAMMA_PROBE_HL_COLOR ((0x140c << 2) + 0xff000000)
+#define L_GAMMA_PROBE_POS_X ((0x140d << 2) + 0xff000000)
+#define L_GAMMA_PROBE_POS_Y ((0x140e << 2) + 0xff000000)
+#define L_STH1_HS_ADDR ((0x1410 << 2) + 0xff000000)
+#define L_STH1_HE_ADDR ((0x1411 << 2) + 0xff000000)
+#define L_STH1_VS_ADDR ((0x1412 << 2) + 0xff000000)
+#define L_STH1_VE_ADDR ((0x1413 << 2) + 0xff000000)
+#define L_STH2_HS_ADDR ((0x1414 << 2) + 0xff000000)
+#define L_STH2_HE_ADDR ((0x1415 << 2) + 0xff000000)
+#define L_STH2_VS_ADDR ((0x1416 << 2) + 0xff000000)
+#define L_STH2_VE_ADDR ((0x1417 << 2) + 0xff000000)
+#define L_OEH_HS_ADDR ((0x1418 << 2) + 0xff000000)
+#define L_OEH_HE_ADDR ((0x1419 << 2) + 0xff000000)
+#define L_OEH_VS_ADDR ((0x141a << 2) + 0xff000000)
+#define L_OEH_VE_ADDR ((0x141b << 2) + 0xff000000)
+#define L_VCOM_HSWITCH_ADDR ((0x141c << 2) + 0xff000000)
+#define L_VCOM_VS_ADDR ((0x141d << 2) + 0xff000000)
+#define L_VCOM_VE_ADDR ((0x141e << 2) + 0xff000000)
+#define L_CPV1_HS_ADDR ((0x141f << 2) + 0xff000000)
+#define L_CPV1_HE_ADDR ((0x1420 << 2) + 0xff000000)
+#define L_CPV1_VS_ADDR ((0x1421 << 2) + 0xff000000)
+#define L_CPV1_VE_ADDR ((0x1422 << 2) + 0xff000000)
+#define L_CPV2_HS_ADDR ((0x1423 << 2) + 0xff000000)
+#define L_CPV2_HE_ADDR ((0x1424 << 2) + 0xff000000)
+#define L_CPV2_VS_ADDR ((0x1425 << 2) + 0xff000000)
+#define L_CPV2_VE_ADDR ((0x1426 << 2) + 0xff000000)
+#define L_STV1_HS_ADDR ((0x1427 << 2) + 0xff000000)
+#define L_STV1_HE_ADDR ((0x1428 << 2) + 0xff000000)
+#define L_STV1_VS_ADDR ((0x1429 << 2) + 0xff000000)
+#define L_STV1_VE_ADDR ((0x142a << 2) + 0xff000000)
+#define L_STV2_HS_ADDR ((0x142b << 2) + 0xff000000)
+#define L_STV2_HE_ADDR ((0x142c << 2) + 0xff000000)
+#define L_STV2_VS_ADDR ((0x142d << 2) + 0xff000000)
+#define L_STV2_VE_ADDR ((0x142e << 2) + 0xff000000)
+#define L_OEV1_HS_ADDR ((0x142f << 2) + 0xff000000)
+#define L_OEV1_HE_ADDR ((0x1430 << 2) + 0xff000000)
+#define L_OEV1_VS_ADDR ((0x1431 << 2) + 0xff000000)
+#define L_OEV1_VE_ADDR ((0x1432 << 2) + 0xff000000)
+#define L_OEV2_HS_ADDR ((0x1433 << 2) + 0xff000000)
+#define L_OEV2_HE_ADDR ((0x1434 << 2) + 0xff000000)
+#define L_OEV2_VS_ADDR ((0x1435 << 2) + 0xff000000)
+#define L_OEV2_VE_ADDR ((0x1436 << 2) + 0xff000000)
+#define L_OEV3_HS_ADDR ((0x1437 << 2) + 0xff000000)
+#define L_OEV3_HE_ADDR ((0x1438 << 2) + 0xff000000)
+#define L_OEV3_VS_ADDR ((0x1439 << 2) + 0xff000000)
+#define L_OEV3_VE_ADDR ((0x143a << 2) + 0xff000000)
+#define L_LCD_PWR_ADDR ((0x143b << 2) + 0xff000000)
+#define L_LCD_PWM0_LO_ADDR ((0x143c << 2) + 0xff000000)
+#define L_LCD_PWM0_HI_ADDR ((0x143d << 2) + 0xff000000)
+#define L_LCD_PWM1_LO_ADDR ((0x143e << 2) + 0xff000000)
+#define L_LCD_PWM1_HI_ADDR ((0x143f << 2) + 0xff000000)
+#define L_INV_CNT_ADDR ((0x1440 << 2) + 0xff000000)
+#define L_TCON_MISC_SEL_ADDR ((0x1441 << 2) + 0xff000000)
+#define L_DUAL_PORT_CNTL_ADDR ((0x1442 << 2) + 0xff000000)
+#define MLVDS_CLK_CTL1_HI ((0x1443 << 2) + 0xff000000)
+#define MLVDS_CLK_CTL1_LO ((0x1444 << 2) + 0xff000000)
+// [31:30] enable mlvds clocks
+// [24] mlvds_clk_half_delay 24 // Bit 0
+// [23:0] mlvds_clk_pattern 0 // Bit 23:0
+#define L_TCON_DOUBLE_CTL ((0x1449 << 2) + 0xff000000)
+#define L_TCON_PATTERN_HI ((0x144a << 2) + 0xff000000)
+#define L_TCON_PATTERN_LO ((0x144b << 2) + 0xff000000)
+#define LDIM_BL_ADDR_PORT ((0x144e << 2) + 0xff000000)
+#define LDIM_BL_DATA_PORT ((0x144f << 2) + 0xff000000)
+#define L_DE_HS_ADDR ((0x1451 << 2) + 0xff000000)
+#define L_DE_HE_ADDR ((0x1452 << 2) + 0xff000000)
+#define L_DE_VS_ADDR ((0x1453 << 2) + 0xff000000)
+#define L_DE_VE_ADDR ((0x1454 << 2) + 0xff000000)
+#define L_HSYNC_HS_ADDR ((0x1455 << 2) + 0xff000000)
+#define L_HSYNC_HE_ADDR ((0x1456 << 2) + 0xff000000)
+#define L_HSYNC_VS_ADDR ((0x1457 << 2) + 0xff000000)
+#define L_HSYNC_VE_ADDR ((0x1458 << 2) + 0xff000000)
+#define L_VSYNC_HS_ADDR ((0x1459 << 2) + 0xff000000)
+#define L_VSYNC_HE_ADDR ((0x145a << 2) + 0xff000000)
+#define L_VSYNC_VS_ADDR ((0x145b << 2) + 0xff000000)
+#define L_VSYNC_VE_ADDR ((0x145c << 2) + 0xff000000)
+// bit 8 -- vfifo_mcu_enable
+// bit 7 -- halt_vs_de
+// bit 6 -- R8G8B8_format
+// bit 5 -- R6G6B6_format (round to 6 bits)
+// bit 4 -- R5G6B5_format
+// bit 3 -- dac_dith_sel
+// bit 2 -- lcd_mcu_enable_de -- ReadOnly
+// bit 1 -- lcd_mcu_enable_vsync -- ReadOnly
+// bit 0 -- lcd_mcu_enable
+#define L_LCD_MCU_CTL ((0x145d << 2) + 0xff000000)
+//**************************************************************************
+//* Dual port mLVDS registers
+//**************************************************************************
+// bit 3 - enable_u_dual_mlvds_dp_clk
+// bit 2 - enable_u_map_mlvds_r_clk
+// bit 1 - enable_u_map_mlvds_l_clk
+// bit 0 - dual_mlvds_en
+//`define DUAL_MLVDS_CTL 8'h60
+// bit[12:0] - dual_mlvds_line_start
+//`define DUAL_MLVDS_LINE_START 8'h61
+// bit[12:0] - dual_mlvds_line_end
+//`define DUAL_MLVDS_LINE_END 8'h62
+// bit[12:0] - dual_mlvds_w_pixel_start_l
+//`define DUAL_MLVDS_PIXEL_W_START_L 8'h63
+// bit[12:0] - dual_mlvds_w_pixel_end_l
+//`define DUAL_MLVDS_PIXEL_W_END_L 8'h64
+// bit[12:0] - dual_mlvds_w_pixel_start_r
+//`define DUAL_MLVDS_PIXEL_W_START_R 8'h65
+// bit[12:0] - dual_mlvds_w_pixel_end_r
+//`define DUAL_MLVDS_PIXEL_W_END_R 8'h66
+// bit[12:0] - dual_mlvds_r_pixel_start_l
+//`define DUAL_MLVDS_PIXEL_R_START_L 8'h67
+// bit[12:0] - dual_mlvds_r_pixel_cnt_l
+//`define DUAL_MLVDS_PIXEL_R_CNT_L 8'h68
+// bit[12:0] - dual_mlvds_r_pixel_start_r
+//`define DUAL_MLVDS_PIXEL_R_START_R 8'h69
+// bit[12:0] - dual_mlvds_r_pixel_cnt_r
+//`define DUAL_MLVDS_PIXEL_R_CNT_R 8'h6a
+// bit[15] - v_inversion_en
+// bit[12:0] - v_inversion_pixel
+//`define V_INVERSION_PIXEL 8'h70
+// bit[15] - v_inversion_sync_en
+// bit[12:0] - v_inversion_line
+//`define V_INVERSION_LINE 8'h71
+// bit[15:12] - v_loop_r
+// bit[11:10] - v_pattern_1_r
+// bit[9:8] - v_pattern_0_r
+// bit[7:4] - v_loop_l
+// bit[3:2] - v_pattern_1_l
+// bit[1:0] - v_pattern_0_l
+//`define V_INVERSION_CONTROL 8'h72
+//`define MLVDS2_CONTROL 8'h74
+ #define mLVDS2_RESERVED 15 // 15
+ #define mLVDS2_double_pattern 14 // 14
+ #define mLVDS2_ins_reset 8 // 13:8 // each channel has one bit
+ #define mLVDS2_dual_gate 7
+ #define mLVDS2_bit_num 6 // 0-6Bits, 1-8Bits
+ #define mLVDS2_pair_num 5 // 0-3Pairs, 1-6Pairs
+ #define mLVDS2_msb_first 4
+ #define mLVDS2_PORT_SWAP 3
+ #define mLVDS2_MLSB_SWAP 2
+ #define mLVDS2_PN_SWAP 1
+ #define mLVDS2_en 0
+//`define MLVDS2_CONFIG_HI 8'h75
+//`define MLVDS2_CONFIG_LO 8'h76
+ #define mLVDS2_reset_offset 29 // Bit 31:29
+ #define mLVDS2_reset_length 23 // Bit 28:23
+ #define mLVDS2_config_reserved 20 // Bit 22:20
+ #define mLVDS2_reset_start_bit12 19 // Bit 19
+ #define mLVDS2_data_write_toggle 18
+ #define mLVDS2_data_write_ini 17
+ #define mLVDS2_data_latch_1_toggle 16
+ #define mLVDS2_data_latch_1_ini 15
+ #define mLVDS2_data_latch_0_toggle 14
+ #define mLVDS2_data_latch_0_ini 13
+ #define mLVDS2_reset_1_select 12 // 0 - same as reset_0, 1 - 1 clock delay of reset_0
+ #define mLVDS2_reset_start 0 // Bit 11:0
+//`define MLVDS2_DUAL_GATE_WR_START 8'h77
+// `define mlvds2_dual_gate_wr_start 0 // Bit 12:0
+//`define MLVDS2_DUAL_GATE_WR_END 8'h78
+// `define mlvds2_dual_gate_wr_end 0 // Bit 12:0
+//
+//`define MLVDS2_DUAL_GATE_RD_START 8'h79
+// `define mlvds2_dual_gate_rd_start 0 // Bit 12:0
+//`define MLVDS2_DUAL_GATE_RD_END 8'h7a
+// `define mlvds2_dual_gate_rd_end 0 // Bit 12:0
+//`define MLVDS2_SECOND_RESET_CTL 8'h7b
+// `define mLVDS2_2nd_reset_start 0 // Bit 12:0
+//
+//`define MLVDS2_DUAL_GATE_CTL_HI 8'h7c
+//`define MLVDS2_DUAL_GATE_CTL_LO 8'h7d
+// `define mlvds2_tcon_field_en 24 // Bit 7:0
+// `define mlvds2_dual_gate_reserved 21 // Bit 2:0
+// `define mlvds2_scan_mode_start_line_bit12 20 // Bit 0
+// `define mlvds2_scan_mode_odd 16 // Bit 3:0
+// `define mlvds2_scan_mode_even 12 // Bit 3:0
+// `define mlvds2_scan_mode_start_line 0 // Bit 11:0
+//
+//`define MLVDS2_RESET_CONFIG_HI 8'h7e
+//`define MLVDS2_RESET_CONFIG_LO 8'h7f
+// `define mLVDS2_reset_range_enable 31 // Bit 0
+// `define mLVDS2_reset_range_inv 30 // Bit 0
+// `define mLVDS2_reset_config_res1 29 // Bit 0
+// `define mLVDS2_reset_range_line_0 16 // Bit 11:0
+// `define mLVDS2_reset_config_res3 13 // Bit 2:0
+// `define mLVDS2_reset_range_line_1 0 // Bit 11:0
+//
+//**************************************************************************
+//* Vbyone registers (Note: no MinLVDS in G9tv, share the register)
+//**************************************************************************
+#define VBO_CTRL_L ((0x1460 << 2) + 0xff000000)
+#define VBO_CTRL_H ((0x1461 << 2) + 0xff000000)
+#define VBO_SOFT_RST ((0x1462 << 2) + 0xff000000)
+#define VBO_LANES ((0x1463 << 2) + 0xff000000)
+#define VBO_VIN_CTRL ((0x1464 << 2) + 0xff000000)
+#define VBO_ACT_VSIZE ((0x1465 << 2) + 0xff000000)
+#define VBO_REGION_00 ((0x1466 << 2) + 0xff000000)
+#define VBO_REGION_01 ((0x1467 << 2) + 0xff000000)
+#define VBO_REGION_02 ((0x1468 << 2) + 0xff000000)
+#define VBO_REGION_03 ((0x1469 << 2) + 0xff000000)
+#define VBO_VBK_CTRL_0 ((0x146a << 2) + 0xff000000)
+#define VBO_VBK_CTRL_1 ((0x146b << 2) + 0xff000000)
+#define VBO_HBK_CTRL ((0x146c << 2) + 0xff000000)
+#define VBO_PXL_CTRL ((0x146d << 2) + 0xff000000)
+#define VBO_LANE_SKEW_L ((0x146e << 2) + 0xff000000)
+#define VBO_LANE_SKEW_H ((0x146f << 2) + 0xff000000)
+#define VBO_GCLK_LANE_L ((0x1470 << 2) + 0xff000000)
+#define VBO_GCLK_LANE_H ((0x1471 << 2) + 0xff000000)
+#define VBO_GCLK_MAIN ((0x1472 << 2) + 0xff000000)
+#define VBO_STATUS_L ((0x1473 << 2) + 0xff000000)
+#define VBO_STATUS_H ((0x1474 << 2) + 0xff000000)
+#define VBO_LANE_OUTPUT ((0x1475 << 2) + 0xff000000)
+#define LCD_PORT_SWAP ((0x1476 << 2) + 0xff000000)
+#define VBO_TMCHK_THRD_L ((0x1478 << 2) + 0xff000000)
+#define VBO_TMCHK_THRD_H ((0x1479 << 2) + 0xff000000)
+#define VBO_FSM_HOLDER_L ((0x147a << 2) + 0xff000000)
+#define VBO_FSM_HOLDER_H ((0x147b << 2) + 0xff000000)
+#define VBO_INTR_STATE_CTRL ((0x147c << 2) + 0xff000000)
+#define VBO_INTR_UNMASK ((0x147d << 2) + 0xff000000)
+#define VBO_TMCHK_HSYNC_STATE_L ((0x147e << 2) + 0xff000000)
+#define VBO_TMCHK_HSYNC_STATE_H ((0x147f << 2) + 0xff000000)
+#define VBO_TMCHK_VSYNC_STATE_L ((0x14f4 << 2) + 0xff000000)
+#define VBO_TMCHK_VSYNC_STATE_H ((0x14f5 << 2) + 0xff000000)
+#define VBO_TMCHK_VDE_STATE_L ((0x14f6 << 2) + 0xff000000)
+#define VBO_TMCHK_VDE_STATE_H ((0x14f7 << 2) + 0xff000000)
+#define VBO_INTR_STATE ((0x14f8 << 2) + 0xff000000)
+#define VBO_INFILTER_CTRL ((0x14f9 << 2) + 0xff000000)
+#define VBO_INSGN_CTRL ((0x14fa << 2) + 0xff000000)
+#define VBO_INFILTER_CTRL_H ((0x1477 << 2) + 0xff000000)
+//**************************************************************************
+//* NOTE:: When Programming the Gamma, please turn off the IRQ service *
+//**************************************************************************
+#define GAMMA_CNTL_PORT ((0x1480 << 2) + 0xff000000)
+ #define GAMMA_VCOM_POL 7 //RW
+ #define GAMMA_RVS_OUT 6 //RW
+ #define ADR_RDY 5 //Read Only
+ #define WR_RDY 4 //Read Only
+ #define RD_RDY 3 //Read Only
+ #define GAMMA_TR 2 //RW
+ #define GAMMA_SET 1 //RW
+ #define GAMMA_EN 0 //RW
+#define GAMMA_DATA_PORT ((0x1481 << 2) + 0xff000000)
+#define GAMMA_ADDR_PORT ((0x1482 << 2) + 0xff000000)
+ #define H_RD 12
+ #define H_AUTO_INC 11
+ #define H_SEL_R 10
+ #define H_SEL_G 9
+ #define H_SEL_B 8
+ #define HADR_MSB 7 //7:0
+ #define HADR 0 //7:0
+#define GAMMA_VCOM_HSWITCH_ADDR ((0x1483 << 2) + 0xff000000)
+#define RGB_BASE_ADDR ((0x1485 << 2) + 0xff000000)
+#define RGB_COEFF_ADDR ((0x1486 << 2) + 0xff000000)
+#define POL_CNTL_ADDR ((0x1487 << 2) + 0xff000000)
+ #define DCLK_SEL 14 //FOR DCLK OUTPUT
+ #define TCON_VSYNC_SEL_DVI 11 //FOR RGB format DVI output
+ #define TCON_HSYNC_SEL_DVI 10 //FOR RGB format DVI output
+ #define TCON_DE_SEL_DVI 9 //FOR RGB format DVI output
+ #define CPH3_POL 8
+ #define CPH2_POL 7
+ #define CPH1_POL 6
+ #define TCON_DE_SEL 5
+ #define TCON_VS_SEL 4
+ #define TCON_HS_SEL 3
+ #define DE_POL 2
+ #define VS_POL 1
+ #define HS_POL 0
+#define DITH_CNTL_ADDR ((0x1488 << 2) + 0xff000000)
+ #define DITH10_EN 10
+ #define DITH8_EN 9
+ #define DITH_MD 8
+ #define DITH10_CNTL_MSB 7 //7:4
+ #define DITH10_CNTL 4 //7:4
+ #define DITH8_CNTL_MSB 3 //3:0
+ #define DITH8_CNTL 0 //3:0
+//Bit 1 highlight_en
+//Bit 0 probe_en
+#define GAMMA_PROBE_CTRL ((0x1489 << 2) + 0xff000000)
+//read only
+//Bit [15:0] probe_color[15:0]
+#define GAMMA_PROBE_COLOR_L ((0x148a << 2) + 0xff000000)
+//Read only
+//Bit 15: if true valid probed color
+//Bit [13:0] probe_color[29:16]
+#define GAMMA_PROBE_COLOR_H ((0x148b << 2) + 0xff000000)
+//bit 15:0, 5:6:5 color
+#define GAMMA_PROBE_HL_COLOR ((0x148c << 2) + 0xff000000)
+//12:0 pos_x
+#define GAMMA_PROBE_POS_X ((0x148d << 2) + 0xff000000)
+//12:0 pos_y
+#define GAMMA_PROBE_POS_Y ((0x148e << 2) + 0xff000000)
+#define STH1_HS_ADDR ((0x1490 << 2) + 0xff000000)
+#define STH1_HE_ADDR ((0x1491 << 2) + 0xff000000)
+#define STH1_VS_ADDR ((0x1492 << 2) + 0xff000000)
+#define STH1_VE_ADDR ((0x1493 << 2) + 0xff000000)
+#define STH2_HS_ADDR ((0x1494 << 2) + 0xff000000)
+#define STH2_HE_ADDR ((0x1495 << 2) + 0xff000000)
+#define STH2_VS_ADDR ((0x1496 << 2) + 0xff000000)
+#define STH2_VE_ADDR ((0x1497 << 2) + 0xff000000)
+#define OEH_HS_ADDR ((0x1498 << 2) + 0xff000000)
+#define OEH_HE_ADDR ((0x1499 << 2) + 0xff000000)
+#define OEH_VS_ADDR ((0x149a << 2) + 0xff000000)
+#define OEH_VE_ADDR ((0x149b << 2) + 0xff000000)
+#define VCOM_HSWITCH_ADDR ((0x149c << 2) + 0xff000000)
+#define VCOM_VS_ADDR ((0x149d << 2) + 0xff000000)
+#define VCOM_VE_ADDR ((0x149e << 2) + 0xff000000)
+#define CPV1_HS_ADDR ((0x149f << 2) + 0xff000000)
+#define CPV1_HE_ADDR ((0x14a0 << 2) + 0xff000000)
+#define CPV1_VS_ADDR ((0x14a1 << 2) + 0xff000000)
+#define CPV1_VE_ADDR ((0x14a2 << 2) + 0xff000000)
+#define CPV2_HS_ADDR ((0x14a3 << 2) + 0xff000000)
+#define CPV2_HE_ADDR ((0x14a4 << 2) + 0xff000000)
+#define CPV2_VS_ADDR ((0x14a5 << 2) + 0xff000000)
+#define CPV2_VE_ADDR ((0x14a6 << 2) + 0xff000000)
+#define STV1_HS_ADDR ((0x14a7 << 2) + 0xff000000)
+#define STV1_HE_ADDR ((0x14a8 << 2) + 0xff000000)
+#define STV1_VS_ADDR ((0x14a9 << 2) + 0xff000000)
+#define STV1_VE_ADDR ((0x14aa << 2) + 0xff000000)
+#define STV2_HS_ADDR ((0x14ab << 2) + 0xff000000)
+#define STV2_HE_ADDR ((0x14ac << 2) + 0xff000000)
+#define STV2_VS_ADDR ((0x14ad << 2) + 0xff000000)
+#define STV2_VE_ADDR ((0x14ae << 2) + 0xff000000)
+#define OEV1_HS_ADDR ((0x14af << 2) + 0xff000000)
+#define OEV1_HE_ADDR ((0x14b0 << 2) + 0xff000000)
+#define OEV1_VS_ADDR ((0x14b1 << 2) + 0xff000000)
+#define OEV1_VE_ADDR ((0x14b2 << 2) + 0xff000000)
+#define OEV2_HS_ADDR ((0x14b3 << 2) + 0xff000000)
+#define OEV2_HE_ADDR ((0x14b4 << 2) + 0xff000000)
+#define OEV2_VS_ADDR ((0x14b5 << 2) + 0xff000000)
+#define OEV2_VE_ADDR ((0x14b6 << 2) + 0xff000000)
+#define OEV3_HS_ADDR ((0x14b7 << 2) + 0xff000000)
+#define OEV3_HE_ADDR ((0x14b8 << 2) + 0xff000000)
+#define OEV3_VS_ADDR ((0x14b9 << 2) + 0xff000000)
+#define OEV3_VE_ADDR ((0x14ba << 2) + 0xff000000)
+#define LCD_PWR_ADDR ((0x14bb << 2) + 0xff000000)
+ #define LCD_VDD 5
+ #define LCD_VBL 4
+ #define LCD_GPI_MSB 3
+ #define LCD_GPIO 0
+#define LCD_PWM0_LO_ADDR ((0x14bc << 2) + 0xff000000)
+#define LCD_PWM0_HI_ADDR ((0x14bd << 2) + 0xff000000)
+#define LCD_PWM1_LO_ADDR ((0x14be << 2) + 0xff000000)
+#define LCD_PWM1_HI_ADDR ((0x14bf << 2) + 0xff000000)
+#define INV_CNT_ADDR ((0x14c0 << 2) + 0xff000000)
+ #define INV_EN 4
+ #define INV_CNT_MSB 3
+ #define INV_CNT 0
+#define TCON_MISC_SEL_ADDR ((0x14c1 << 2) + 0xff000000)
+ #define STH2_SEL 12
+ #define STH1_SEL 11
+ #define OEH_SEL 10
+ #define VCOM_SEL 9
+ #define DB_LINE_SW 8
+ #define CPV2_SEL 7
+ #define CPV1_SEL 6
+ #define STV2_SEL 5
+ #define STV1_SEL 4
+ #define OEV_UNITE 3
+ #define OEV3_SEL 2
+ #define OEV2_SEL 1
+ #define OEV1_SEL 0
+#define DUAL_PORT_CNTL_ADDR ((0x14c2 << 2) + 0xff000000)
+ #define OUTPUT_YUV 15
+ #define DUAL_IDF 12 // 14:12
+ #define DUAL_ISF 9 // 11:9
+ #define LCD_ANALOG_SEL_CPH3 8
+ #define LCD_ANALOG_3PHI_CLK_SEL 7
+ #define LCD_LVDS_SEL54 6
+ #define LCD_LVDS_SEL27 5
+ #define LCD_TTL_SEL 4
+ #define DUAL_LVDC_EN 3
+ #define PORT_SWP 2
+ #define RGB_SWP 1
+ #define BIT_SWP 0
+#define MLVDS_CONTROL ((0x14c3 << 2) + 0xff000000)
+ #define mLVDS_RESERVED 15 // 15
+ #define mLVDS_double_pattern 14 // 14
+ #define mLVDS_ins_reset 8 // 13:8 // each channel has one bit
+ #define mLVDS_dual_gate 7
+ #define mLVDS_bit_num 6 // 0-6Bits, 1-8Bits
+ #define mLVDS_pair_num 5 // 0-3Pairs, 1-6Pairs
+ #define mLVDS_msb_first 4
+ #define mLVDS_PORT_SWAP 3
+ #define mLVDS_MLSB_SWAP 2
+ #define mLVDS_PN_SWAP 1
+ #define mLVDS_en 0
+#define MLVDS_RESET_PATTERN_HI ((0x14c4 << 2) + 0xff000000)
+#define MLVDS_RESET_PATTERN_LO ((0x14c5 << 2) + 0xff000000)
+ #define mLVDS_reset_pattern 0 // Bit 47:16
+#define MLVDS_RESET_PATTERN_EXT ((0x14c6 << 2) + 0xff000000)
+ #define mLVDS_reset_pattern_ext 0 // Bit 15:0
+#define MLVDS_CONFIG_HI ((0x14c7 << 2) + 0xff000000)
+#define MLVDS_CONFIG_LO ((0x14c8 << 2) + 0xff000000)
+ #define mLVDS_reset_offset 29 // Bit 31:29
+ #define mLVDS_reset_length 23 // Bit 28:23
+ #define mLVDS_config_reserved 20 // Bit 22:20
+ #define mLVDS_reset_start_bit12 19 // Bit 19
+ #define mLVDS_data_write_toggle 18
+ #define mLVDS_data_write_ini 17
+ #define mLVDS_data_latch_1_toggle 16
+ #define mLVDS_data_latch_1_ini 15
+ #define mLVDS_data_latch_0_toggle 14
+ #define mLVDS_data_latch_0_ini 13
+ #define mLVDS_reset_1_select 12 // 0 - same as reset_0, 1 - 1 clock delay of reset_0
+ #define mLVDS_reset_start 0 // Bit 11:0
+#define TCON_DOUBLE_CTL ((0x14c9 << 2) + 0xff000000)
+ #define tcon_double_ini 8 // Bit 7:0
+ #define tcon_double_inv 0 // Bit 7:0
+#define TCON_PATTERN_HI ((0x14ca << 2) + 0xff000000)
+#define TCON_PATTERN_LO ((0x14cb << 2) + 0xff000000)
+ #define tcon_pattern_loop_data 16 // Bit 15:0
+ #define tcon_pattern_loop_start 12 // Bit 3:0
+ #define tcon_pattern_loop_end 8 // Bit 3:0
+ #define tcon_pattern_enable 0 // Bit 7:0
+#define TCON_CONTROL_HI ((0x14cc << 2) + 0xff000000)
+#define TCON_CONTROL_LO ((0x14cd << 2) + 0xff000000)
+ #define tcon_pclk_enable 26 // Bit 5:0 (enable pclk on TCON channel 7 to 2)
+ #define tcon_pclk_div 24 // Bit 1:0 (control phy clok divide 2,4,6,8)
+ #define tcon_delay 0 // Bit 23:0 (3 bit for each channel)
+#define LVDS_BLANK_DATA_HI ((0x14ce << 2) + 0xff000000)
+#define LVDS_BLANK_DATA_LO ((0x14cf << 2) + 0xff000000)
+ #define LVDS_blank_data_reserved 30 // 31:30
+ #define LVDS_blank_data_r 20 // 29:20
+ #define LVDS_blank_data_g 10 // 19:10
+ #define LVDS_blank_data_b 0 // 9:0
+#define LVDS_PACK_CNTL_ADDR ((0x14d0 << 2) + 0xff000000)
+ #define LVDS_USE_TCON 7
+ #define LVDS_DUAL 6
+ #define PN_SWP 5
+ #define LSB_FIRST 4
+ #define LVDS_RESV 3
+ #define ODD_EVEN_SWP 2
+ #define LVDS_REPACK 0
+// New from M3 :
+// Bit 15:12 -- Enable OFFSET Double Generate(TOCN7-TCON4)
+// Bit 11:0 -- de_hs(old tcon) second offset_hs (new tcon)
+#define DE_HS_ADDR ((0x14d1 << 2) + 0xff000000)
+// New from M3 :
+// Bit 15:12 -- Enable OFFSET Double Generate(TOCN3-TCON0)
+#define DE_HE_ADDR ((0x14d2 << 2) + 0xff000000)
+#define DE_VS_ADDR ((0x14d3 << 2) + 0xff000000)
+#define DE_VE_ADDR ((0x14d4 << 2) + 0xff000000)
+#define HSYNC_HS_ADDR ((0x14d5 << 2) + 0xff000000)
+#define HSYNC_HE_ADDR ((0x14d6 << 2) + 0xff000000)
+#define HSYNC_VS_ADDR ((0x14d7 << 2) + 0xff000000)
+#define HSYNC_VE_ADDR ((0x14d8 << 2) + 0xff000000)
+#define VSYNC_HS_ADDR ((0x14d9 << 2) + 0xff000000)
+#define VSYNC_HE_ADDR ((0x14da << 2) + 0xff000000)
+#define VSYNC_VS_ADDR ((0x14db << 2) + 0xff000000)
+#define VSYNC_VE_ADDR ((0x14dc << 2) + 0xff000000)
+// bit 8 -- vfifo_mcu_enable
+// bit 7 -- halt_vs_de
+// bit 6 -- R8G8B8_format
+// bit 5 -- R6G6B6_format (round to 6 bits)
+// bit 4 -- R5G6B5_format
+// bit 3 -- dac_dith_sel
+// bit 2 -- lcd_mcu_enable_de -- ReadOnly
+// bit 1 -- lcd_mcu_enable_vsync -- ReadOnly
+// bit 0 -- lcd_mcu_enable
+#define LCD_MCU_CTL ((0x14dd << 2) + 0xff000000)
+// ReadOnly
+// R5G6B5 when R5G6B5_format
+// G8R8 when R8G8B8_format
+// G5R10 Other
+#define LCD_MCU_DATA_0 ((0x14de << 2) + 0xff000000)
+// ReadOnly
+// G8B8 when R8G8B8_format
+// G5B10 Other
+#define LCD_MCU_DATA_1 ((0x14df << 2) + 0xff000000)
+// LVDS
+#define LVDS_GEN_CNTL ((0x14e0 << 2) + 0xff000000)
+//`define LVDS_PHY_CNTL0 8'he1
+//`define LVDS_PHY_CNTL1 8'he2
+//`define LVDS_PHY_CNTL2 8'he3
+//`define LVDS_PHY_CNTL3 8'he4
+//`define LVDS_PHY_CNTL4 8'he5
+//`define LVDS_PHY_CNTL5 8'he6
+#define LVDS_SRG_TEST ((0x14e8 << 2) + 0xff000000)
+#define LVDS_BIST_MUX0 ((0x14e9 << 2) + 0xff000000)
+#define LVDS_BIST_MUX1 ((0x14ea << 2) + 0xff000000)
+#define LVDS_BIST_FIXED0 ((0x14eb << 2) + 0xff000000)
+#define LVDS_BIST_FIXED1 ((0x14ec << 2) + 0xff000000)
+#define LVDS_BIST_CNTL0 ((0x14ed << 2) + 0xff000000)
+#define LVDS_CLKB_CLKA ((0x14ee << 2) + 0xff000000)
+#define LVDS_PHY_CLK_CNTL ((0x14ef << 2) + 0xff000000)
+#define LVDS_SER_EN ((0x14f0 << 2) + 0xff000000)
+//`define LVDS_PHY_CNTL6 8'hf1
+//`define LVDS_PHY_CNTL7 8'hf2
+//`define LVDS_PHY_CNTL8 8'hf3
+#define LVDS_CH_SWAP0 ((0x14e1 << 2) + 0xff000000)
+#define LVDS_CH_SWAP1 ((0x14e2 << 2) + 0xff000000)
+#define LVDS_CH_SWAP2 ((0x14e3 << 2) + 0xff000000)
+//`define MLVDS_CLK_CTL0_HI 8'hf4
+//`define MLVDS_CLK_CTL0_LO 8'hf5
+// `define mlvds_clk_pattern_reserved 31 // Bit 31
+// `define mpclk_dly 28 // Bit 2:0
+// `define mpclk_div 26 // Bit 1:0 (control phy clok divide 2,4,6,8)
+// `define use_mpclk 25 // Bit 0
+// `define mlvds_clk_half_delay 24 // Bit 0
+// `define mlvds_clk_pattern 0 // Bit 23:0
+//`define MLVDS_DUAL_GATE_WR_START 8'hf6
+// `define mlvds_dual_gate_wr_start 0 // Bit 12:0
+//`define MLVDS_DUAL_GATE_WR_END 8'hf7
+// `define mlvds_dual_gate_wr_end 0 // Bit 12:0
+//
+//`define MLVDS_DUAL_GATE_RD_START 8'hf8
+// `define mlvds_dual_gate_rd_start 0 // Bit 12:0
+//`define MLVDS_DUAL_GATE_RD_END 8'hf9
+// `define mlvds_dual_gate_rd_end 0 // Bit 12:0
+//`define MLVDS_SECOND_RESET_CTL 8'hfa
+// `define mLVDS_2nd_reset_start 0 // Bit 12:0
+//
+#define MLVDS_DUAL_GATE_CTL_HI ((0x14fb << 2) + 0xff000000)
+#define MLVDS_DUAL_GATE_CTL_LO ((0x14fc << 2) + 0xff000000)
+// `define mlvds_tcon_field_en 24 // Bit 7:0
+// `define mlvds_dual_gate_reserved 21 // Bit 2:0
+// `define mlvds_scan_mode_start_line_bit12 20 // Bit 0
+// `define mlvds_scan_mode_odd 16 // Bit 3:0
+// `define mlvds_scan_mode_even 12 // Bit 3:0
+// `define mlvds_scan_mode_start_line 0 // Bit 11:0
+//
+//`define MLVDS_RESET_CONFIG_HI 8'hfd
+//`define MLVDS_RESET_CONFIG_LO 8'hfe
+// `define mLVDS_reset_range_enable 31 // Bit 0
+// `define mLVDS_reset_range_inv 30 // Bit 0
+// `define mLVDS_reset_config_res1 29 // Bit 0
+// `define mLVDS_reset_range_line_0 16 // Bit 11:0
+// `define mLVDS_reset_config_res3 13 // Bit 2:0
+// `define mLVDS_reset_range_line_1 0 // Bit 11:0
+//===============================================================
+//LCD DRIVER BASE END
+//===============================================================
+//
+// Closing file: lcd_regs.h
+//
+//
+// Reading file: vpu_mad_regs.h
+//
+//DEINTERLACE module start from 8'h90 end to 8'hff
+// -----------------------------------------------
+// REG_BASE: MAD_VCBUS_BASE = 0x17
+// -----------------------------------------------
+#define DI_PRE_CTRL ((0x1700 << 2) + 0xff000000)
+// bit 31, cbus_pre_frame_rst
+// bit 30, cbus_pre_soft_rst
+// bit 29, pre_field_num
+// bit 27:26, mode_444c422
+// bit 25, di_cont_read_en
+// bit 24:23, mode_422c444
+// bit 22, mtn_after_nr
+// bit 21:16, pre_hold_fifo_lines
+// bit 15, nr_wr_by
+// bit 14, use_vdin_go_line
+// bit 13, di_prevdin_en
+// bit 12, di_pre_viu_link
+// bit 11, di_pre_repeat
+// bit 10, di_pre_drop_1st
+// bit 9, di_buf2_en
+// bit 8, di_chan2_en
+// bit 7, prenr_hist_en
+// bit 6, chan2_hist_en
+// bit 5, hist_check_en
+// bit 4, check_after_nr
+// bit 3, check222p_en
+// bit 2, check322p_en
+// bit 1, mtn_en
+// bit 0, nr_en
+#define DI_POST_CTRL ((0x1701 << 2) + 0xff000000)
+// bit 31, cbus_post_frame_rst
+// bit 30, cbus_post_soft_rst
+// bit 29, post_field_num
+// bit 21:16, post_hold_fifo_lines
+// bit 13, prepost_link
+// bit 12, di_post_viu_link
+// bit 11, di_post_repeat
+// bit 10, di_post_drop_1st
+// bit 9, mif0_to_vpp_en
+// bit 8, di_vpp_out_en
+// bit 7, di_wr_bk_en
+// bit 6, di_mux_en
+// bit 5, di_blend_en
+// bit 4, di_mtnp_read_en
+// bit 3, di_mtn_buf_en
+// bit 2, di_ei_en
+// bit 1, di_buf1_en
+// bit 0, di_buf0_en
+#define DI_POST_SIZE ((0x1702 << 2) + 0xff000000)
+//bit 31:29, diwr_field_mode field mode, 0 frame mode, 4 for field mode botton field, 5 for field mode top field, , 6 for blank line mode
+//bit 28:16, vsize1post
+//bit 12:0, hsize1post
+#define DI_PRE_SIZE ((0x1703 << 2) + 0xff000000)
+//bit 31:29, nrwr_field_mode field mode, 0 frame mode, 4 for field mode botton field, 5 for field mode top field, , 6 for blank line mode
+//bit 28:16, vsize1pre
+//bit 12:0, hsize1pre
+#define DI_EI_CTRL0 ((0x1704 << 2) + 0xff000000)
+//bit 23:16, ei0_filter[2:+] abs_diff_left>filter && ...right>filter && ...top>filter && ...bot>filter -> filter
+//bit 15:8, ei0_threshold[2:+]
+//bit 3, ei0_vertical
+//bit 2, ei0_bpscf2
+//bit 1, ei0_bpsfar1
+#define DI_EI_CTRL1 ((0x1705 << 2) + 0xff000000)
+//bit 31:24, ei0_diff
+//bit 23:16, ei0_angle45
+//bit 15:8, ei0_peak
+//bit 7:0, ei0_cross
+#define DI_EI_CTRL2 ((0x1706 << 2) + 0xff000000)
+//bit 31:24, ei0_close2
+//bit 23:16, ei0_close1
+//bit 15:8, ei0_far2
+//bit 7:0, ei0_far1
+//`define DI_NR_CTRL0 8'h07
+//bit 26, nr_cue_en
+//bit 25, nr2_en
+#define DI_NR_CTRL1 ((0x1708 << 2) + 0xff000000)
+//bit 31:30, mot_p1txtcore_mode
+//bit 29:24, mot_p1txtcore_clmt
+//bit 21:16, mot_p1txtcore_ylmt
+//bit 15:8, mot_p1txtcore_crate
+//bit 7:0, mot_p1txtcore_yrate
+#define DI_NR_CTRL2 ((0x1709 << 2) + 0xff000000)
+//bit 29:24, mot_curtxtcore_clmt
+//bit 21:16, mot_curtxtcore_ylmt
+//bit 15:8, mot_curtxtcore_crate
+//bit 7:0, mot_curtxtcore_yrate
+//`define DI_NR_CTRL3 8'h0a
+//no use
+//`define DI_MTN_CTRL 8'h0b
+//`define DI_CANVAS_URGENT0 8'h0a
+//`define DI_CANVAS_URGENT1 8'h0b
+#define DI_MTN_CTRL1 ((0x170c << 2) + 0xff000000)
+//bit 11:8, mtn_paramtnthd
+//bit 7:0, mtn_parafltthd
+#define DI_BLEND_CTRL ((0x170d << 2) + 0xff000000)
+//bit 31, blend_1_en
+//bit 30, blend_mtn_lpf
+//bit 28, post_mb_en
+//bit 27, blend_mtn3p_max
+//bit 26, blend_mtn3p_min
+//bit 25, blend_mtn3p_ave
+//bit 24, blend_mtn3p_maxtb
+//bit 23, blend_mtn_flt_en
+//bit 22, blend_data_flt_en
+//bit 21:20, blend_top_mode
+//bit 19, blend_reg3_enable
+//bit 18, blend_reg2_enable
+//bit 17, blend_reg1_enable
+//bit 16, blend_reg0_enable
+//bit 15:14, blend_reg3_mode
+//bit 13:12, blend_reg2_mode
+//bit 11:10, blend_reg1_mode
+//bit 9:8, blend_reg0_mode
+//bit 7:0, kdeint
+//`define DI_BLEND_CTRL1 8'h0e
+//no use
+//`define DI_CANVAS_URGENT2 8'h0e
+//`define DI_BLEND_CTRL2 8'h0f
+//no use
+#define DI_ARB_CTRL ((0x170f << 2) + 0xff000000)
+//bit 31:26, di_arb_thd1
+//bit 25:20, di_arb_thd0
+//bit 19, di_arb_tid_mode
+//bit 18, di_arb_arb_mode
+//bit 17, di_arb_acq_en
+//bit 16, di_arb_disable_clk
+//bit 15:0, di_arb_req_en
+#define DI_BLEND_REG0_X ((0x1710 << 2) + 0xff000000)
+//bit 27:16, blend_reg0_startx
+//bit 11:0, blend_reg0_endx
+#define DI_BLEND_REG0_Y ((0x1711 << 2) + 0xff000000)
+#define DI_BLEND_REG1_X ((0x1712 << 2) + 0xff000000)
+#define DI_BLEND_REG1_Y ((0x1713 << 2) + 0xff000000)
+#define DI_BLEND_REG2_X ((0x1714 << 2) + 0xff000000)
+#define DI_BLEND_REG2_Y ((0x1715 << 2) + 0xff000000)
+#define DI_BLEND_REG3_X ((0x1716 << 2) + 0xff000000)
+#define DI_BLEND_REG3_Y ((0x1717 << 2) + 0xff000000)
+#define DI_CLKG_CTRL ((0x1718 << 2) + 0xff000000)
+//bit 31:24, pre_gclk_ctrl no clk gate control. if ==1, module clk is not gated (always on). [3] for pulldown,[2] for mtn_1,[1] for mtn_0,[0] for nr
+//bit 23:16, post_gclk_ctrl no clk gate control. [4] for ei_1, [3] for ei_0,[2] for ei_top, [1] for blend_1, [0] for blend_0
+//bit 1, di_gate_all clk shut down. if ==1 , all di clock shut down
+//bit 0, di_no_clk_gate no clk gate control. if di_gated_all==0 and di_no_clk_gate ==1, all di clock is always working.
+#define DI_EI_CTRL3 ((0x1719 << 2) + 0xff000000)
+//bit 31, reg_ei_1
+//bit 30, reg_demon_en
+//bit 26:24, reg_demon_mux
+//bit 23:20, reg_right_win
+//bit 19:16, reg_left_win
+//bit 7:4, reg_ei_sadm_quatize_margin
+//bit 1:0, reg_ei_sad_relative_mode
+#define DI_EI_CTRL4 ((0x171a << 2) + 0xff000000)
+//bit 29, reg_ei_caldrt_ambliike2_biasvertical
+//bit 28:24, reg_ei_caldrt_addxla2list_drtmax
+//bit 22:20, reg_ei_caldrt_addxla2list_signm0th
+//bit 19, reg_ei_caldrt_addxla2list_mode
+//bit 18:16, reg_ei_signm_sad_cor_rate
+//bit 15:12, reg_ei_signm_sadi_cor_rate
+//bit 11:6, reg_ei_signm_sadi_cor_ofst
+//bit 5:0, reg_ei_signm_sad_ofst
+#define DI_EI_CTRL5 ((0x171b << 2) + 0xff000000)
+//bit 30:28, reg_ei_caldrt_cnflcctchk_frcverthrd
+//bit 26:24, reg_ei_caldrt_cnflctchk_mg
+//bit 23:22, reg_ei_caldrt_cnflctchk_ws
+//bit 21, reg_ei_caldrt_cnflctchk_en
+//bit 20, reg_ei_caldrt_verfrc_final_en
+//bit 19, reg_ei_caldrt_verfrc_retimflt_en
+//bit 18:16, reg_ei_caldrt_verftc_eithratemth
+//bit 15, reg_ei_caldrt_verfrc_retiming_en
+//bit 14:12, reg_ei_caldrt_verfrc_bothratemth
+//bit 11:9, reg_ei_caldrt_ver_thrd
+//bit 8:4, reg_ei_caldrt_addxla2list_drtmin
+//bit 3:0, reg_ei_caldrt_addxla2list_drtlimit
+#define DI_EI_CTRL6 ((0x171c << 2) + 0xff000000)
+//bit 31:24, reg_ei_caldrt_abext_sad12thhig
+//bit 23:16, reg_ei_caldrt_abext_sad00thlow
+//bit 15:8, reg_ei_caldrt_abext_sad12thlow
+//bit 6:4, reg_ei_caldrt_abext_ratemth
+//bit 2:0, reg_ei_caldrt_abext_drtthrd
+#define DI_EI_CTRL7 ((0x171d << 2) + 0xff000000)
+//bit 29, reg_ei_caldrt_xlanopeak_codien
+//bit 28:24, reg_ei_caldrt_xlanopeak_drtmax
+//bit 23, reg_ei_caldrt_xlanopeak_en
+//bit 28:24, reg_ei_caldrt_abext_monotrnd_alpha
+//bit 28:24, reg_ei_caldrt_abext_mononum12_thrd
+//bit 28:24, reg_ei_caldrt_abext_mononum00_thrd
+//bit 28:24, reg_ei_caldrt_abext_sad00rate
+//bit 28:24, reg_ei_caldrt_abext_sad12rate
+//bit 28:24, reg_ei_caldrt_abext_sad00thhig
+#define DI_EI_CTRL8 ((0x171e << 2) + 0xff000000)
+//bit 30:28, reg_ei_assign_headtail_magin
+//bit 26:24, reg_ei_retime_lastcurpncnfltchk_mode
+//bit 22:21, reg_ei_retime_lastcurpncnfltchk_drtth
+//bit 20, reg_ei_caldrt_histchk_cnfid
+//bit 19:16, reg_ei_caldrt_histchk_thrd
+//bit 15, reg_ei_caldrt_histchk_abext
+//bit 14, reg_ei_caldrt_histchk_npen
+//bit 13:11, reg_ei_caldrt_amblike2_drtmg
+//bit 10:8, reg_ei_caldrt_amblike2_valmg
+//bit 7:4, reg_ei_caldrt_amblike2_alpha
+//bit 3:0, reg_ei_caldrt_amblike2_drtth
+#define DI_EI_CTRL9 ((0x171f << 2) + 0xff000000)
+//bit 31:28, reg_ei_caldrt_hcnfcheck_frcvert_xla_th3
+//bit 27, reg_ei_caldrt_hcnfcheck_frcvert_xla_en
+//bit 26:24, reg_ei_caldrt_conf_drtth
+//bit 23:20, reg_ei_caldrt_conf_absdrtth
+//bit 19:18, reg_ei_caldrt_abcheck_mode1
+//bit 17:16, reg_ei_caldrt_abcheck_mode0
+//bit 15:12, reg_ei_caldrt_abcheck_drth1
+//bit 11:8, reg_ei_caldrt_abcheck_drth0
+//bit 6:4, reg_ei_caldrt_abpnchk1_th
+//bit 1, reg_ei_caldrt_abpnchk1_en
+//bit 0, reg_ei_caldrt_abpnchk0_en
+// DEINTERLACE mode check.
+#define DI_MC_REG0_X ((0x1720 << 2) + 0xff000000)
+//bit 27:16, mc_reg0_start_x
+//bit 11:0, mc_reg0_end_x
+#define DI_MC_REG0_Y ((0x1721 << 2) + 0xff000000)
+#define DI_MC_REG1_X ((0x1722 << 2) + 0xff000000)
+#define DI_MC_REG1_Y ((0x1723 << 2) + 0xff000000)
+#define DI_MC_REG2_X ((0x1724 << 2) + 0xff000000)
+#define DI_MC_REG2_Y ((0x1725 << 2) + 0xff000000)
+#define DI_MC_REG3_X ((0x1726 << 2) + 0xff000000)
+#define DI_MC_REG3_Y ((0x1727 << 2) + 0xff000000)
+#define DI_MC_REG4_X ((0x1728 << 2) + 0xff000000)
+#define DI_MC_REG4_Y ((0x1729 << 2) + 0xff000000)
+#define DI_MC_32LVL0 ((0x172a << 2) + 0xff000000)
+//bit 31:24, mc_reg2_32lvl
+//bit 23:16, mc_reg1_32lvl
+//bit 15:8, mc_reg0_32lvl
+//bit 7:0, field_32lvl
+#define DI_MC_32LVL1 ((0x172b << 2) + 0xff000000)
+//bit 15:8, mc_reg3_32lvl
+//bit 7:0, mc_reg4_32lvl
+#define DI_MC_22LVL0 ((0x172c << 2) + 0xff000000)
+//bit 31:16, mc_reg0_22lvl
+//bit 15:0, field_22lvl
+#define DI_MC_22LVL1 ((0x172d << 2) + 0xff000000)
+//bit 31:16, mc_reg2_22lvl
+//bit 15:0, mc_reg1_22lvl
+#define DI_MC_22LVL2 ((0x172e << 2) + 0xff000000)
+//bit 31:16, mc_reg4_22lvl
+//bit 15:0, mc_reg3_22lvl
+#define DI_MC_CTRL ((0x172f << 2) + 0xff000000)
+//bit 4, mc_reg4_en
+//bit 3, mc_reg3_en
+//bit 2, mc_reg2_en
+//bit 1, mc_reg1_en
+//bit 0, mc_reg0_en
+#define DI_INTR_CTRL ((0x1730 << 2) + 0xff000000)
+#define DI_INFO_ADDR ((0x1731 << 2) + 0xff000000)
+#define DI_INFO_DATA ((0x1732 << 2) + 0xff000000)
+#define DI_PRE_HOLD ((0x1733 << 2) + 0xff000000)
+//// DET 3D REG DEFINE BEGIN ////
+//// 8'h34~8'h3f
+// `define DET3D_MOTN_CFG 8'h34
+// //Bit 16, reg_det3d_intr_en Det3d interrupt enable
+// //Bit 9:8, reg_Det3D_Motion_Mode U2 Different mode for Motion Calculation of Luma and Chroma:
+// // 0: MotY, 1: (2*MotY + (MotU + MotV))/4; 2: Max(MotY, MotU,MotV); 3:Max(MotY, (MotU+MotV)/2)
+// //Bit 7:4, reg_Det3D_Motion_Core_Rate U4 K Rate to Edge (HV) details for coring of Motion Calculations, normalized to 32
+// //Bit 3:0, reg_Det3D_Motion_Core_Thrd U4 2X: static coring value for Motion Detection.
+//
+// `define DET3D_CB_CFG 8'h35
+// //Bit 7:4, reg_Det3D_ChessBd_NHV_ofst U4, Noise immune offset for NON-Horizotnal or vertical combing detection.
+// //Bit 3:0, reg_Det3D_ChessBd_HV_ofst U4, Noise immune offset for Horizotnal or vertical combing detection.
+//
+// `define DET3D_SPLT_CFG 8'h36
+// //Bit 7:4, reg_Det3D_SplitValid_ratio U4, Ratio between max_value and the avg_value of the edge mapping for split line valid detection.
+// // The smaller of this value, the easier of the split line detected.
+// //Bit 3:0, reg_Det3D_AvgIdx_ratio U4, Ratio to the avg_value of the edge mapping for split line position estimation.
+// // The smaller of this value, the more samples will be added to the estimation.
+//
+// `define DET3D_HV_MUTE 8'h37
+// //Bit 23:20, reg_Det3D_Edge_Ver_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Top and Bottom border part.
+// //Bit 19:16, reg_Det3D_Edge_Hor_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Left and right border part.
+// //Bit 15:12, reg_Det3D_ChessBd_Ver_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part
+// //Bit 11:8, reg_Det3D_ChessBd_Hor_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part
+// //Bit 7:4, reg_Det3D_STA8X8_Ver_Mute U4 1X: Vertical pixels to be mute from 8x8 statistics calculation in each block.
+// //Bit 3:0, reg_Det3D_STA8X8_Hor_Mute U4 1X: Horizontal pixels to be mute from 8x8 statistics calculation in each block.
+//
+// `define DET3D_MAT_STA_P1M1 8'h38
+// //Bit 31:24, reg_Det3D_STA8X8_P1_K0_R8 U8 SAD to SAI ratio to decide P1, normalized to 256 (0.8)
+// //Bit 23:16, reg_Det3D_STA8X8_P1_K1_R7 U8 SAD to ENG ratio to decide P1, normalized to 128 (0.5)
+// //Bit 15:8, reg_Det3D_STA8X8_M1_K0_R6 U8 SAD to SAI ratio to decide M1, normalized to 64 (1.1)
+// //Bit 7:0, reg_Det3D_STA8X8_M1_K1_R6 U8 SAD to ENG ratio to decide M1, normalized to 64 (0.8)
+//
+// `define DET3D_MAT_STA_P1TH 8'h39
+// //Bit 23:16, reg_Det3D_STAYUV_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (100)
+// //Bit 15:8, reg_Det3D_STAEDG_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (80)
+// //Bit 7:0, reg_Det3D_STAMOT_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (48)
+//
+// `define DET3D_MAT_STA_M1TH 8'h3a
+// //Bit 23:16, reg_Det3D_STAYUV_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (100)
+// //Bit 15:8, reg_Det3D_STAEDG_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (80)
+// //Bit 7:0, reg_Det3D_STAMOT_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (64)
+//
+// `define DET3D_MAT_STA_RSFT 8'h3b
+// //Bit 5:4, reg_Det3D_STAYUV_RSHFT U2 YUV statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
+// // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
+// //Bit 3:2, reg_Det3D_STAEDG_RSHFT U2 Horizontal and Vertical Edge Statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
+// // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
+// //Bit 1:0, reg_Det3D_STAMOT_RSHFT U2 Motion SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
+// // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
+//
+// `define DET3D_MAT_SYMTC_TH 8'h3c
+// //Bit 31:24, reg_Det3D_STALUM_symtc_Th U8 threshold to decide if the Luma statistics is TB or LR symmetric.
+// //Bit 23:16, reg_Det3D_STACHR_symtc_Th U8 threshold to decide if the Chroma (UV) statistics is TB or LR symmetric.
+// //Bit 15:8, reg_Det3D_STAEDG_symtc_Th U8 threshold to decide if the Horizontal and Vertical Edge statistics is TB or LR symmetric.
+// //Bit 7:0, reg_Det3D_STAMOT_symtc_Th U8 threshold to decide if the Motion statistics is TB or LR symmetric.
+//
+// `define DET3D_RO_DET_CB_HOR 8'h3d
+// //Bit 31:16, RO_Det3D_ChessBd_NHor_value U16 X64: number of Pixels of Horizontally Surely NOT matching Chessboard pattern.
+// //Bit 15:0, RO_Det3D_ChessBd_Hor_value U16 X64: number of Pixels of Horizontally Surely matching Chessboard pattern.
+//
+// `define DET3D_RO_DET_CB_VER 8'h3e
+// //Bit 31:16, RO_Det3D_ChessBd_NVer_value U16 X64: number of Pixels of Vertically Surely NOT matching Chessboard pattern.
+// //Bit 15:0, RO_Det3D_ChessBd_Ver_value U16 X64: number of Pixels of Vertically Surely matching Chessboard pattern.
+//
+// `define DET3D_RO_SPLT_HT 8'h3f
+// //Bit 24, RO_Det3D_Split_HT_valid U1 horizontal LR split border detected valid signal for top half picture
+// //Bit 20:16, RO_Det3D_Split_HT_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+// //Bit 9:0, RO_Det3D_Split_HT_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+//
+// //// DET 3D REG DEFINE END ////
+#define DI_MTN_1_CTRL1 ((0x1740 << 2) + 0xff000000)
+//bit 31, mtn_1_en
+//bit 30, mtn_init
+//bit 29, di2nr_txt_en
+//bit 28, reserved
+//bit 27:24, mtn_def
+//bit 23:16, mtn_adp_yc
+//bit 15:8, mtn_adp_2c
+//bit 7:0, mtn_adp_2y
+#define DI_MTN_1_CTRL2 ((0x1741 << 2) + 0xff000000)
+//bit 31:24, mtn_ykinter
+//bit 23:16, mtn_ckinter
+//bit 15:8, mtn_ykintra
+//bit 7:0, mtn_ckintra
+#define DI_MTN_1_CTRL3 ((0x1742 << 2) + 0xff000000)
+//bit 31:24, mtn_tyrate
+//bit 23:16, mtn_tcrate
+//bit 15: 8, mtn_mxcmby
+//bit 7: 0, mtn_mxcmbc
+#define DI_MTN_1_CTRL4 ((0x1743 << 2) + 0xff000000)
+//bit 31:24, mtn_tcorey
+//bit 23:16, mtn_tcorec
+//bit 15: 8, mtn_minth
+//bit 7: 0, mtn_maxth
+#define DI_MTN_1_CTRL5 ((0x1744 << 2) + 0xff000000)
+//bit 31:28, mtn_m1b_extnd
+//bit 27:24, mtn_m1b_errod
+//bit 21:20, mtn_mot_txt_mode
+//bit 19:18, mtn_replace_cbyy
+//bit 17:16, mtn_replace_ybyc
+//bit 15: 8, mtn_core_ykinter
+//bit 7: 0, mtn_core_ckinter
+//// NR2 REG DEFINE BEGIN////
+#define NR2_MET_NM_CTRL ((0x1745 << 2) + 0xff000000)
+//Bit 28, reg_NM_reset Reset to the status of the Loop filter.
+//Bit 27:24, reg_NM_calc_length Length mode of the Noise measurement sample number for statistics.
+// 0: 256 samples; 1: 512 samples; 2: 1024 samples; ¡X: 2^(8+x) samples
+//Bit 23:20, reg_NM_inc_step Loop filter input gain increase step.
+//Bit 19:16, reg_NM_dec_step Loop filter input gain decrease step.
+//Bit 15:8, reg_NM_YHPmot_thrd Luma channel HP portion motion for condition of pixels included in Luma Noise measurement.
+//Bit 7:0, reg_NM_CHPmot_thrd Chroma channel HP portion motion for condition of pixels included in Chroma Noise measurement.
+#define NR2_MET_NM_YCTRL ((0x1746 << 2) + 0xff000000)
+//Bit 31:28, reg_NM_YPLL_target Target rate of NM_Ynoise_thrd to mean of the Luma Noise
+//Bit 27:24, reg_NM_YLPmot_thrd Luma channel LP portion motion for condition of pixels included in Luma Noise measurement.
+//Bit 23:16, reg_NM_YHPmot_thrd_min Minimum threshold for Luma channel HP portion motion to decide whether the pixel will be included in Luma noise measurement.
+//Bit 15:8, reg_NM_YHPmot_thrd_max Maximum threshold for Luma channel HP portion motion to decide whether the pixel will be included in Luma noise measurement.
+//Bit 7:0, reg_NM_Ylock_rate Rate to decide whether the Luma noise measurement is lock or not.
+#define NR2_MET_NM_CCTRL ((0x1747 << 2) + 0xff000000)
+//Bit 31:28, reg_NM_CPLL_target Target rate of NM_Cnoise_thrd to mean of the Chroma Noise
+//Bit 27:24, reg_NM_CLPmot_thrd Chroma channel LP portion motion for condition of pixels included in Chroma Noise measurement.
+//Bit 23:16, reg_NM_CHPmot_thrd_min Minimum threshold for Chroma channel HP portion motion to decide whether the pixel will be included in Chroma noise measurement.
+//Bit 15:8, reg_NM_CHPmot_thrd_max Maximum threshold for Chroma channel HP portion motion to decide whether the pixel will be included in Chroma noise measurement.
+//Bit 7:0, reg_NM_Clock_rate Rate to decide whether the Chroma noise measurement is lock or not;
+#define NR2_MET_NM_TNR ((0x1748 << 2) + 0xff000000)
+//Bit 25, ro_NM_TNR_Ylock Read-only register to tell ifLuma channel noise measurement is locked or not.
+//Bit 24, ro_NM_TNR_Clock Read-only register to tell if Chroma channel noise measurement is locked or not.
+//Bit 23:12, ro_NM_TNR_Ylevel Read-only register to give Luma channel noise level. It was 16x of pixel difference in 8 bits of YHPmot.
+//Bit 11:0, ro_NM_TNR_Clevel Read-only register to give Chroma channel noise level. It was 16x of pixel difference in 8 bits of CHPmot.
+#define NR2_MET_NMFRM_TNR_YLEV ((0x1749 << 2) + 0xff000000)
+//Bit 28:0, ro_NMFrm_TNR_Ylevel Frame based Read-only register to give Luma channel noise level within one frame/field.
+#define NR2_MET_NMFRM_TNR_YCNT ((0x174a << 2) + 0xff000000)
+//Bit 23:0, ro_NMFrm_TNR_Ycount Number ofLuma channel pixels included in Frame/Field based noise level measurement.
+#define NR2_MET_NMFRM_TNR_CLEV ((0x174b << 2) + 0xff000000)
+//Bit 28:0, ro_NMFrm_TNR_Clevel Frame based Read-only register to give Chroma channel noise level within one frame/field.
+#define NR2_MET_NMFRM_TNR_CCNT ((0x174c << 2) + 0xff000000)
+//Bit 23:0, ro_NMFrm_TNR_Ccount Number of Chroma channel pixels included in Frame/Field based noise level measurement.
+#define NR2_3DEN_MODE ((0x174d << 2) + 0xff000000)
+//Bit 6:4, Blend_3dnr_en_r
+//Bit 2:0, Blend_3dnr_en_l
+// `define NR2_IIR_CTRL 8'h4e
+// //Bit 15:14, reg_LP_IIR_8bit_mode LP IIR membitwidth mode:0: 10bits will be store in memory;1: 9bits will be store in memory;
+// // 2: 8bits will be store in memory;3: 7bits will be store in memory;
+// //Bit 13:12, reg_LP_IIR_mute_mode Mode for the LP IIR mute,
+// //Bit 11:8, reg_LP_IIR_mute_thrd Threshold of LP IIR mute to avoid ghost:
+// //Bit 7:6, reg_HP_IIR_8bit_mode IIR membitwidth mode:0: 10bits will be store in memory;1: 9bits will be store in memory;
+// // 2: 8bits will be store in memory;3: 7bits will be store in memory;
+// //Bit 5:4, reg_HP_IIR_mute_mode Mode for theLP IIR mute
+// //Bit 3:0, reg_HP_IIR_mute_thrd Threshold of HP IIR mute to avoid ghost
+// //
+#define NR2_SW_EN ((0x174f << 2) + 0xff000000)
+//Bit 17:8, Clk_gate_ctrl
+//Bit 7, Cfr_enable
+//Bit 5, Det3d_en
+//Bit 4, Nr2_proc_en
+//Bit 0, Nr2_sw_en
+#define NR2_FRM_SIZE ((0x1750 << 2) + 0xff000000)
+//Bit 27:16, Frm_heigh Frame/field height
+//Bit 11: 0, Frm_width Frame/field width
+// `define NR2_SNR_SAD_CFG 8'h51
+// //Bit 12, reg_MATNR_SNR_SAD_CenRPL U1, Enable signal for Current pixel position SAD to be replaced by SAD_min.0: do not replace Current pixel position SAD by SAD_min;1: do replacements
+// //Bit 11:8, reg_MATNR_SNR_SAD_coring Coring value of the intra-frame SAD. sum = (sum - reg_MATNR_SNR_SAD_coring);sum = (sum<0) ? 0: (sum>255)? 255: sum;
+// //Bit 6:5, reg_MATNR_SNR_SAD_WinMod Unsigned, Intra-frame SAD matching window mode:0: 1x1; 1: [1 1 1] 2: [1 2 1]; 3: [1 2 2 2 1];
+// //Bit 4:0, Sad_coef_num Sad coeffient
+//
+// `define NR2_MATNR_SNR_OS 8'h52
+// //Bit 7:4, reg_MATNR_SNR_COS SNR Filter overshoot control margin for UV channel (X2 to u10 scale)
+// //Bit 3:0, reg_MATNR_SNR_YOS SNR Filter overshoot control margin for luma channel (X2 to u10 scale)
+//
+// `define NR2_MATNR_SNR_NRM_CFG 8'h53
+// //Bit 23:16, reg_MATNR_SNR_NRM_ofst Edge based SNR boosting normalization offset to SAD_max ;
+// //Bit 15:8, reg_MATNR_SNR_NRM_max Edge based SNR boosting normalization Max value
+// //Bit 7:0, reg_MATNR_SNR_NRM_min Edge based SNR boosting normalization Min value
+//
+// `define NR2_MATNR_SNR_NRM_GAIN 8'h54
+// //Bit 15:8, reg_MATNR_SNR_NRM_Cgain Edge based SNR boosting normalization Gain for Chrm channel (norm 32 as 1)
+// //Bit 7:0, reg_MATNR_SNR_NRM_Ygain Edge based SNR boosting normalization Gain for Luma channel (norm 32 as 1)
+//
+// `define NR2_MATNR_SNR_LPF_CFG 8'h55
+// //Bit 23:16,reg_MATNR_SNRLPF_SADmaxTH U8, Threshold to SADmax to use TNRLPF to replace SNRLPF. i.e.if (SAD_max<reg_MATNR_SNRLPF_SADmaxTH) SNRLPF_yuv[k] = TNRLPF_yuv[k];
+// //Bit 13:11,reg_MATNR_SNRLPF_Cmode LPF based SNR filtering mode on CHRM channel:
+// // 0: gradient LPF [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8; 3: gradient LPF [5 4 4 3]/16;
+// // 4: TNRLPF; 5 : CurLPF3x3_yuv[]; 6: CurLPF3o3_yuv[] 7: CurLPF3x5_yuv[]
+// //Bit 10:8, reg_MATNR_SNRLPF_Ymode LPF based SNR filtering mode on LUMA channel:
+// // 0: gradient LPF //Bit [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8;3: gradient LPF [5 4 4 3]/16;
+// // 4: TNRLPF; 5 : CurLPF3x3_yuv[]; 6: CurLPF3o3_yuv[] 7: CurLPF3x5_yuv[]
+// //Bit 7:4, reg_MATNR_SNRLPF_SADmin3TH Offset threshold to SAD_min to Discard SAD_min3 corresponding pixel in LPF SNR filtering. (X8 to u8 scale)
+// //Bit 3:0, reg_MATNR_SNRLPF_SADmin2TH Offset threshold to SAD_min to Discard SAD_min2 corresponding pixel in LPF SNR filtering. (X8 to u8 scale)
+//
+// `define NR2_MATNR_SNR_USF_GAIN 8'h56
+// //Bit 15:8, reg_MATNR_SNR_USF_Cgain Un-sharp (HP) compensate back Chrm portion gain, (norm 64 as 1)
+// //Bit 7:0, reg_MATNR_SNR_USF_Ygain Un-sharp (HP) compensate back Luma portion gain, (norm 64 as 1)
+//
+// `define NR2_MATNR_SNR_EDGE2B 8'h57
+// //Bit 15:8, reg_MATNR_SNR_Edge2Beta_ofst U8, Offset for Beta based on Edge.
+// //Bit 7:0, reg_MATNR_SNR_Edge2Beta_gain U8. Gain to SAD_min for Beta based on Edge. (norm 16 as 1)
+//
+// `define NR2_MATNR_BETA_EGAIN 8'h58
+// //Bit 15:8, reg_MATNR_CBeta_Egain U8, Gain to Edge based Beta for Chrm channel. (normalized to 32 as 1)
+// //Bit 7:0, reg_MATNR_YBeta_Egain U8, Gain to Edge based Beta for Luma channel. (normalized to 32 as 1)
+//
+// `define NR2_MATNR_BETA_BRT 8'h59
+// //Bit 31:28, reg_MATNR_beta_BRT_limt_hi U4, Beta adjustment based on Brightness high side Limit. (X16 to u8 scale)
+// //Bit 27:24, reg_MATNR_beta_BRT_slop_hi U4, Beta adjustment based on Brightness high side slope. Normalized to 16 as 1
+// //Bit 23:16, reg_MATNR_beta_BRT_thrd_hi U8, Beta adjustment based on Brightness high threshold.(u8 scale)
+// //Bit 15:12, reg_MATNR_beta_BRT_limt_lo U4, Beta adjustment based on Brightness low side Limit. (X16 to u8 scale)
+// //Bit 11:8, reg_MATNR_beta_BRT_slop_lo U4, Beta adjustment based on Brightness low side slope. Normalized to 16 as 1
+// //Bit 7:0, reg_MATNR_beta_BRT_thrd_lo U8, Beta adjustment based on Brightness low threshold.(u8 scale)
+// `define NR2_MATNR_XBETA_CFG 8'h5a
+// //Bit 19:18, reg_MATNR_CBeta_use_mode U2, Beta options (mux) from beta_motion and beta_edge for Chrm channel;
+// //Bit 17:16, reg_MATNR_YBeta_use_mode U2, Beta options (mux) from beta_motion and beta_edge for Luma channel;
+// //Bit 15: 8, reg_MATNR_CBeta_Ofst U8, Offset to Beta for Chrm channel.(after beta_edge and beta_motion mux)
+// //Bit 7: 0, reg_MATNR_YBeta_Ofst U8, Offset to Beta for Luma channel.(after beta_edge and beta_motion mux)
+// `define NR2_MATNR_YBETA_SCL 8'h5b
+// //Bit 31:24, reg_MATNR_YBeta_scale_min U8, Final step Beta scale low limit for Luma channel;
+// //Bit 23:16, reg_MATNR_YBeta_scale_max U8, Final step Beta scale high limit for Luma channe;
+// //Bit 15: 8, reg_MATNR_YBeta_scale_gain U8, Final step Beta scale Gain for Luma channel (normalized 32 to 1);
+// //Bit 7 : 0, reg_MATNR_YBeta_scale_ofst S8, Final step Beta scale offset for Luma channel ;
+// `define NR2_MATNR_CBETA_SCL 8'h5c
+// //Bit 31:24, reg_MATNR_CBeta_scale_min Final step Beta scale low limit for Chrm channel.Similar to Y
+// //Bit 23:16, reg_MATNR_CBeta_scale_max U8, Final step Beta scale high limit for Chrm channel.Similar to Y
+// //Bit 15: 8, reg_MATNR_CBeta_scale_gain U8, Final step Beta scale Gain for Chrm channel Similar to Y
+// //Bit 7: 0, reg_MATNR_CBeta_scale_ofst S8, Final step Beta scale offset for Chrm channel Similar to Y
+// `define NR2_SNR_MASK 8'h5d
+// //Bit 20:0, SAD_MSK Valid signal in the 3x7 SAD surface
+// `define NR2_SAD2NORM_LUT0 8'h5e
+// //Bit 31:24, reg_MATNR_SAD2Norm_LUT_3 SAD convert normal LUT node 3
+// //Bit 23:16, reg_MATNR_SAD2Norm_LUT_2 SAD convert normal LUT node 2
+// //Bit 15: 8, reg_MATNR_SAD2Norm_LUT_1 SAD convert normal LUT node 1
+// //Bit 7: 0, reg_MATNR_SAD2Norm_LUT_0 SAD convert normal LUT node 0
+// `define NR2_SAD2NORM_LUT1 8'h5f
+// //Bit 31:24, reg_MATNR_SAD2Norm_LUT_7 SAD convert normal LUT node 7
+// //Bit 23:16, reg_MATNR_SAD2Norm_LUT_6 SAD convert normal LUT node 6
+// //Bit 15: 8, reg_MATNR_SAD2Norm_LUT_5 SAD convert normal LUT node 5
+// //Bit 7: 0, reg_MATNR_SAD2Norm_LUT_4 SAD convert normal LUT node 4
+// `define NR2_SAD2NORM_LUT2 8'h60
+// //Bit 31:24, reg_MATNR_SAD2Norm_LUT_11 SAD convert normal LUT node 11
+// //Bit 23:16, reg_MATNR_SAD2Norm_LUT_10 SAD convert normal LUT node 10
+// //Bit 15: 8, reg_MATNR_SAD2Norm_LUT_9 SAD convert normal LUT node 9
+// //Bit 7: 0, reg_MATNR_SAD2Norm_LUT_8 SAD convert normal LUT node 8
+// `define NR2_SAD2NORM_LUT3 8'h61
+// //Bit 31:24, reg_MATNR_SAD2Norm_LUT_15 SAD convert normal LUT node 15
+// //Bit 23:16, reg_MATNR_SAD2Norm_LUT_14 SAD convert normal LUT node 14
+// //Bit 15:8, reg_MATNR_SAD2Norm_LUT_13 SAD convert normal LUT node 13
+// //Bit 7:0, reg_MATNR_SAD2Norm_LUT_12 SAD convert normal LUT node 12
+// `define NR2_EDGE2BETA_LUT0 8'h62
+// //Bit 31:24, reg_MATNR_Edge2Beta_LUT_3 Edge convert beta LUT node 3
+// //Bit 23:16, reg_MATNR_Edge2Beta_LUT_2 Edge convert beta LUT node 2
+// //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_1 Edge convert beta LUT node 1
+// //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_0 Edge convert beta LUT node 0
+// `define NR2_EDGE2BETA_LUT1 8'h63
+// //Bit 31:24, reg_MATNR_Edge2Beta_LUT_7 Edge convert beta LUT node 7
+// //Bit 23:16, reg_MATNR_Edge2Beta_LUT_6 Edge convert beta LUT node 6
+// //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_5 Edge convert beta LUT node 5
+// //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_4 Edge convert beta LUT node 4
+// `define NR2_EDGE2BETA_LUT2 8'h64
+// //Bit 31:24, reg_MATNR_Edge2Beta_LUT_11 Edge convert beta LUT node 11
+// //Bit 23:16, reg_MATNR_Edge2Beta_LUT_10 Edge convert beta LUT node 10
+// //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_9 Edge convert beta LUT node 9
+// //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_8 Edge convert beta LUT node 8
+// `define NR2_EDGE2BETA_LUT3 8'h65
+// //Bit 31:24, reg_MATNR_Edge2Beta_LUT_15 Edge convert beta LUT node 15
+// //Bit 23:16, reg_MATNR_Edge2Beta_LUT_14 Edge convert beta LUT node 14
+// //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_13 Edge convert beta LUT node 13
+// //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_12 Edge convert beta LUT node 12
+// `define NR2_MOTION2BETA_LUT0 8'h66
+// //Bit 31:24, reg_MATNR_Mot2Beta_LUT_3 Motion convert beta LUT node 3
+// //Bit 23:16, reg_MATNR_Mot2Beta_LUT_2 Motion convert beta LUT node 2
+// //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_1 Motion convert beta LUT node 1
+// //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_0 Motion convert beta LUT node 0
+// `define NR2_MOTION2BETA_LUT1 8'h67
+// //Bit 31:24, reg_MATNR_Mot2Beta_LUT_7 Motion convert beta LUT node 7
+// //Bit 23:16, reg_MATNR_Mot2Beta_LUT_6 Motion convert beta LUT node 6
+// //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_5 Motion convert beta LUT node 5
+// //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_4 Motion convert beta LUT node 4
+// `define NR2_MOTION2BETA_LUT2 8'h68
+// //Bit 31:24, reg_MATNR_Mot2Beta_LUT_11 Motion convert beta LUT node 11
+// //Bit 23:16, reg_MATNR_Mot2Beta_LUT_10 Motion convert beta LUT node 10
+// //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_9 Motion convert beta LUT node 9
+// //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_8 Motion convert beta LUT node 8
+// `define NR2_MOTION2BETA_LUT3 8'h69
+// //Bit 31:24, reg_MATNR_Mot2Beta_LUT_15 Motion convert beta LUT node 15
+// //Bit 23:16, reg_MATNR_Mot2Beta_LUT_14 Motion convert beta LUT node 14
+// //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_13 Motion convert beta LUT node 13
+// //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_12 Motion convert beta LUT node 12
+// `define NR2_MATNR_MTN_CRTL 8'h6a
+// //Bit 25:24, reg_MATNR_Vmtn_use_mode Motion_yuvV channel motion selection mode:0: Vmot;1:Ymot/2 + (Umot+Vmot)/4; 2:Ymot/2 + max(Umot,Vmot)/2; 3: max(Ymot,Umot, Vmot)
+// //Bit 21:20, reg_MATNR_Umtn_use_mode Motion_yuvU channel motion selection mode:0:Umot;1:Ymot/2 + (Umot+Vmot)/4; 2:Ymot/2 + max(Umot,Vmot)/2; 3: max(Ymot,Umot, Vmot)
+// //Bit 17:16, reg_MATNR_Ymtn_use_mode Motion_yuvLuma channel motion selection mode:0: Ymot, 1: Ymot/2 + (Umot+Vmot)/4; 2: Ymot/2 + max(Umot,Vmot)/2; 3: max(Ymot,Umot, Vmot)
+// //Bit 13:12, reg_MATNR_mtn_txt_mode Texture detection mode for adaptive coring of HP motion
+// //Bit 9: 8, reg_MATNR_mtn_cor_mode Coring selection mode based on texture detection;
+// //Bit 6: 4, reg_MATNR_mtn_hpf_mode video mode of current and previous frame/field for MotHPF_yuv[k] calculation:
+// //Bit 2: 0, reg_MATNR_mtn_lpf_mode LPF video mode of current and previous frame/field for MotLPF_yuv[k] calculation:
+// `define NR2_MATNR_MTN_CRTL2 8'h6b
+// //Bit 18:16, reg_MATNR_iir_BS_Ymode IIR TNR filter Band split filter mode for Luma LPF result generation (Cur and Prev);
+// //Bit 15: 8, reg_MATNR_mtnb_alpLP_Cgain Scale of motion_brthp_uv to motion_brtlp_uv, normalized to 32 as 1
+// //Bit 7: 0, reg_MATNR_mtnb_alpLP_Ygain Scale of motion_brthp_y to motion_brtlp_y, normalized to 32 as 1
+// `define NR2_MATNR_MTN_COR 8'h6c
+// //Bit 15:12, reg_MATNR_mtn_cor_Cofst Coring Offset for Chroma Motion.
+// //Bit 11: 8, reg_MATNR_mtn_cor_Cgain Gain to texture based coring for Chroma Motion. Normalized to 16 as 1
+// //Bit 7: 4, reg_MATNR_mtn_cor_Yofst Coring Offset for Luma Motion.
+// //Bit 3: 0, reg_MATNR_mtn_cor_Ygain Gain to texture based coring for Luma Motion. Normalized to 16 as 1
+// `define NR2_MATNR_MTN_GAIN 8'h6d
+// //Bit 31:24, reg_MATNR_mtn_hp_Cgain Gain to MotHPF_yuv[k] Chrm channel for motion calculation, normalized to 64 as 1
+// //Bit 23:16, reg_MATNR_mtn_hp_Ygain Gain to MotHPF_yuv[k] Luma channel for motion calculation, normalized to 64 as 1
+// //Bit 15: 8, reg_MATNR_mtn_lp_Cgain Gain to MotLPF_yuv[k] Chrm channel for motion calculation, normalized to 32 as 1
+// //Bit 7: 0, reg_MATNR_mtn_lp_Ygain Gain to MotLPF_yuv[k] Luma channel for motion calculation, normalized to 32 as 1
+// `define NR2_MATNR_DEGHOST 8'h6e
+// //Bit 8, reg_MATNR_DeGhost_En Enable signal for DeGhost function:0: disable; 1: enable
+// //Bit 7:4, reg_MATNR_DeGhost_COS DeGhost Overshoot margin for UV channel, (X2 to u10 scale)
+// //Bit 3:0, reg_MATNR_DeGhost_YOS DeGhost Overshoot margin for Luma channel, (X2 to u10 scale)
+//
+// `define NR2_MATNR_ALPHALP_LUT0 8'h6f
+// //Bit 31:24, reg_MATNR_AlphaLP_LUT_3 Matnr low-pass filter alpha LUT node 3
+// //Bit 23:16, reg_MATNR_AlphaLP_LUT_2 Matnr low-pass filter alpha LUT node 2
+// //Bit 15: 8, reg_MATNR_AlphaLP_LUT_1 Matnr low-pass filter alpha LUT node 1
+// //Bit 7: 0, reg_MATNR_AlphaLP_LUT_0 Matnr low-pass filter alpha LUT node 0
+// `define NR2_MATNR_ALPHALP_LUT1 8'h70
+// //Bit 31:24, reg_MATNR_AlphaLP_LUT_7 Matnr low-pass filter alpha LUT node 7
+// //Bit 23:16, reg_MATNR_AlphaLP_LUT_6 Matnr low-pass filter alpha LUT node 6
+// //Bit 15: 8, reg_MATNR_AlphaLP_LUT_5 Matnr low-pass filter alpha LUT node 5
+// //Bit 7: 0, reg_MATNR_AlphaLP_LUT_4 Matnr low-pass filter alpha LUT node 4
+// `define NR2_MATNR_ALPHALP_LUT2 8'h71
+// //Bit 31:24, reg_MATNR_AlphaLP_LUT_11 Matnr low-pass filter alpha LUT node 11
+// //Bit 23:16, reg_MATNR_AlphaLP_LUT_10 Matnr low-pass filter alpha LUT node 10
+// //Bit 15: 8, reg_MATNR_AlphaLP_LUT_9 Matnr low-pass filter alpha LUT node 9
+// //Bit 7: 0, reg_MATNR_AlphaLP_LUT_8 Matnr low-pass filter alpha LUT node 8
+// `define NR2_MATNR_ALPHALP_LUT3 8'h72
+// //Bit 31:24, reg_MATNR_AlphaLP_LUT_15 Matnr low-pass filter alpha LUT node 15
+// //Bit 23:16, reg_MATNR_AlphaLP_LUT_14 Matnr low-pass filter alpha LUT node 14
+// //Bit 15: 8, reg_MATNR_AlphaLP_LUT_13 Matnr low-pass filter alpha LUT node 13
+// //Bit 7: 0, reg_MATNR_AlphaLP_LUT_12 Matnr low-pass filter alpha LUT node 12
+// `define NR2_MATNR_ALPHAHP_LUT0 8'h73
+// //Bit 31:24, reg_MATNR_AlphaHP_LUT_3 Matnr high-pass filter alpha LUT node 3
+// //Bit 23:16, reg_MATNR_AlphaHP_LUT_2 Matnr high-pass filter alpha LUT node 2
+// //Bit 15: 8, reg_MATNR_AlphaHP_LUT_1 Matnr high-pass filter alpha LUT node 1
+// //Bit 7: 0, reg_MATNR_AlphaHP_LUT_0 Matnr high-pass filter alpha LUT node 0
+// `define NR2_MATNR_ALPHAHP_LUT1 8'h74
+// //Bit 31:24, reg_MATNR_AlphaHP_LUT_7 Matnr high-pass filter alpha LUT node 7
+// //Bit 23:16, reg_MATNR_AlphaHP_LUT_6 Matnr high-pass filter alpha LUT node 6
+// //Bit 15: 8, reg_MATNR_AlphaHP_LUT_5 Matnr high-pass filter alpha LUT node 5
+// //Bit 7: 0, reg_MATNR_AlphaHP_LUT_4 Matnr high-pass filter alpha LUT node 4
+// `define NR2_MATNR_ALPHAHP_LUT2 8'h75
+// //Bit 31:24, reg_MATNR_AlphaHP_LUT_11 Matnr high-pass filter alpha LUT node 11
+// //Bit 23:16, reg_MATNR_AlphaHP_LUT_10 Matnr high-pass filter alpha LUT node 10
+// //Bit 15: 8, reg_MATNR_AlphaHP_LUT_9 Matnr high-pass filter alpha LUT node 9
+// //Bit 7: 0, reg_MATNR_AlphaHP_LUT_8 Matnr high-pass filter alpha LUT node 8
+// `define NR2_MATNR_ALPHAHP_LUT3 8'h76
+// //Bit 31:24, reg_MATNR_AlphaHP_LUT_15 Matnr high-pass filter alpha LUT node 15
+// //Bit 23:16, reg_MATNR_AlphaHP_LUT_14 Matnr high-pass filter alpha LUT node 14
+// //Bit 15: 8, reg_MATNR_AlphaHP_LUT_13 Matnr high-pass filter alpha LUT node 13
+// //Bit 7: 0, reg_MATNR_AlphaHP_LUT_12 Matnr high-pass filter alpha LUT node 12
+//
+// `define NR2_MATNR_MTNB_BRT 8'h77
+// //Bit 31:28, reg_MATNR_mtnb_BRT_limt_hi Motion adjustment based on Brightness high side Limit. (X16 to u8 scale)
+// //Bit 27:24, reg_MATNR_mtnb_BRT_slop_hi Motion adjustment based on Brightness high side slope. Normalized to 16 as 1
+// //Bit 23:16, reg_MATNR_mtnb_BRT_thrd_hi Motion adjustment based on Brightness high threshold.(u8 scale)
+// //Bit 15:12, reg_MATNR_mtnb_BRT_limt_lo Motion adjustment based on Brightness low side Limit. (X16 to u8 scale)
+// //Bit 11: 8, reg_MATNR_mtnb_BRT_slop_lo Motion adjustment based on Brightness low side slope. Normalized to 16 as 1
+// //Bit 7: 0, reg_MATNR_mtnb_BRT_thrd_lo Motion adjustment based on Brightness low threshold.(u8 scale)
+// 0x51 - 0x69 | 0x4e | 0x6a - 0x77
+//
+// Reading file: vpu_nr2_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//========== nr2_snr_regs register begin ==========//
+#define NR2_SNR_SAD_CFG ((0x1751 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12 reg_matnr_snr_sad_cenrpl // unsigned , default = 1
+//Bit 11: 8 reg_matnr_snr_sad_coring // unsigned , default = 3
+//Bit 7 reserved
+//Bit 6: 5 reg_matnr_snr_sad_winmod // unsigned , default = 1 0: 1x1; 1: [1 1 1] 2: [1 2 1]; 3: [1 2 2 2 1];
+//Bit 4: 0 sad_coef_num // unsigned , default = 1 0: 1x1; 1: [1 1 1] 2: [1 2 1]; 3: [1 2 2 2 1];
+#define NR2_MATNR_SNR_OS ((0x1752 << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7: 4 reg_matnr_snr_cos // unsigned , default = 8
+//Bit 3: 0 reg_matnr_snr_yos // unsigned , default = 13
+#define NR2_MATNR_SNR_NRM_CFG ((0x1753 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_matnr_snr_nrm_ofst // signed , default = 64
+//Bit 15: 8 reg_matnr_snr_nrm_max // unsigned , default = 255
+//Bit 7: 0 reg_matnr_snr_nrm_min // unsigned , default = 0
+#define NR2_MATNR_SNR_NRM_GAIN ((0x1754 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_matnr_snr_nrm_cgain // unsigned , default = 0 norm 32
+//Bit 7: 0 reg_matnr_snr_nrm_ygain // unsigned , default = 32 norm 32
+#define NR2_MATNR_SNR_LPF_CFG ((0x1755 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_matnr_snrlpf_sadmaxth // unsigned , default = 12
+//Bit 15:14 reserved
+//Bit 13:11 reg_matnr_snrlpf_cmode // unsigned , default = 2 0: gradient LPF [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8; 3: gradient LPF [5 5 4 3]/16;
+//Bit 10: 8 reg_matnr_snrlpf_ymode // unsigned , default = 2 0: gradient LPF [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8; 3: gradient LPF [5 5 4 3]/16;
+//Bit 7: 4 reg_matnr_snrlpf_sadmin3th // unsigned , default = 6 X8
+//Bit 3: 0 reg_matnr_snrlpf_sadmin2th // unsigned , default = 4 X8
+#define NR2_MATNR_SNR_USF_GAIN ((0x1756 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_matnr_snr_usf_cgain // unsigned , default = 0 norm 64
+//Bit 7: 0 reg_matnr_snr_usf_ygain // unsigned , default = 0 norm 64
+#define NR2_MATNR_SNR_EDGE2B ((0x1757 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_matnr_snr_edge2beta_ofst // unsigned , default = 128
+//Bit 7: 0 reg_matnr_snr_edge2beta_gain // unsigned , default = 16
+#define NR2_MATNR_BETA_EGAIN ((0x1758 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_matnr_cbeta_egain // unsigned , default = 32 normalized to 32
+//Bit 7: 0 reg_matnr_ybeta_egain // unsigned , default = 32 normalized to 32
+#define NR2_MATNR_BETA_BRT ((0x1759 << 2) + 0xff000000)
+//Bit 31:28 reg_matnr_beta_brt_limt_hi // unsigned , default = 0
+//Bit 27:24 reg_matnr_beta_brt_slop_hi // unsigned , default = 0
+//Bit 23:16 reg_matnr_beta_brt_thrd_hi // unsigned , default = 160
+//Bit 15:12 reg_matnr_beta_brt_limt_lo // unsigned , default = 6
+//Bit 11: 8 reg_matnr_beta_brt_slop_lo // unsigned , default = 6
+//Bit 7: 0 reg_matnr_beta_brt_thrd_lo // unsigned , default = 100
+#define NR2_MATNR_XBETA_CFG ((0x175a << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:18 reg_matnr_cbeta_use_mode // unsigned , default = 0 0: beta_motion; 1: beta_edge; 2: min(beta_mot,beta_edge); 3: (beta_mot + beta_edge)/2
+//Bit 17:16 reg_matnr_ybeta_use_mode // unsigned , default = 0 0: beta_motion; 1: beta_edge; 2: min(beta_mot,beta_edge); 3: (beta_mot + beta_edge)/2;
+//Bit 15: 8 reg_matnr_cbeta_ofst // unsigned , default = 0
+//Bit 7: 0 reg_matnr_ybeta_ofst // unsigned , default = 0
+#define NR2_MATNR_YBETA_SCL ((0x175b << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_ybeta_scale_min // unsigned , default = 60
+//Bit 23:16 reg_matnr_ybeta_scale_max // unsigned , default = 255
+//Bit 15: 8 reg_matnr_ybeta_scale_gain // unsigned , default = 32 normalized 32 to 1.0
+//Bit 7: 0 reg_matnr_ybeta_scale_ofst // signed , default = 0
+#define NR2_MATNR_CBETA_SCL ((0x175c << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_cbeta_scale_min // unsigned , default = 0
+//Bit 23:16 reg_matnr_cbeta_scale_max // unsigned , default = 255
+//Bit 15: 8 reg_matnr_cbeta_scale_gain // unsigned , default = 32 normalized 32 to 1.0
+//Bit 7: 0 reg_matnr_cbeta_scale_ofst // signed , default = 0
+#define NR2_SNR_MASK ((0x175d << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20: 0 sad_msk // unsigned , default = 0x0f9f3e
+#define NR2_SAD2NORM_LUT0 ((0x175e << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_sad2norm_lut3 // unsigned , default = 114
+//Bit 23:16 reg_matnr_sad2norm_lut2 // unsigned , default = 146
+//Bit 15: 8 reg_matnr_sad2norm_lut1 // unsigned , default = 171
+//Bit 7: 0 reg_matnr_sad2norm_lut0 // unsigned , default = 205
+#define NR2_SAD2NORM_LUT1 ((0x175f << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_sad2norm_lut7 // unsigned , default = 28
+//Bit 23:16 reg_matnr_sad2norm_lut6 // unsigned , default = 35
+//Bit 15: 8 reg_matnr_sad2norm_lut5 // unsigned , default = 49
+//Bit 7: 0 reg_matnr_sad2norm_lut4 // unsigned , default = 79
+#define NR2_SAD2NORM_LUT2 ((0x1760 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_sad2norm_lut11 // unsigned , default = 15
+//Bit 23:16 reg_matnr_sad2norm_lut10 // unsigned , default = 17
+//Bit 15: 8 reg_matnr_sad2norm_lut9 // unsigned , default = 19
+//Bit 7: 0 reg_matnr_sad2norm_lut8 // unsigned , default = 23
+#define NR2_SAD2NORM_LUT3 ((0x1761 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_sad2norm_lut15 // unsigned , default = 8
+//Bit 23:16 reg_matnr_sad2norm_lut14 // unsigned , default = 9
+//Bit 15: 8 reg_matnr_sad2norm_lut13 // unsigned , default = 10
+//Bit 7: 0 reg_matnr_sad2norm_lut12 // unsigned , default = 12
+#define NR2_EDGE2BETA_LUT0 ((0x1762 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_edge2beta_lut3 // unsigned , default = 128
+//Bit 23:16 reg_matnr_edge2beta_lut2 // unsigned , default = 160
+//Bit 15: 8 reg_matnr_edge2beta_lut1 // unsigned , default = 224
+//Bit 7: 0 reg_matnr_edge2beta_lut0 // unsigned , default = 255
+#define NR2_EDGE2BETA_LUT1 ((0x1763 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_edge2beta_lut7 // unsigned , default = 4
+//Bit 23:16 reg_matnr_edge2beta_lut6 // unsigned , default = 16
+//Bit 15: 8 reg_matnr_edge2beta_lut5 // unsigned , default = 32
+//Bit 7: 0 reg_matnr_edge2beta_lut4 // unsigned , default = 80
+#define NR2_EDGE2BETA_LUT2 ((0x1764 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_edge2beta_lut11 // unsigned , default = 0
+//Bit 23:16 reg_matnr_edge2beta_lut10 // unsigned , default = 0
+//Bit 15: 8 reg_matnr_edge2beta_lut9 // unsigned , default = 0
+//Bit 7: 0 reg_matnr_edge2beta_lut8 // unsigned , default = 2
+#define NR2_EDGE2BETA_LUT3 ((0x1765 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_edge2beta_lut15 // unsigned , default = 0
+//Bit 23:16 reg_matnr_edge2beta_lut14 // unsigned , default = 0
+//Bit 15: 8 reg_matnr_edge2beta_lut13 // unsigned , default = 0
+//Bit 7: 0 reg_matnr_edge2beta_lut12 // unsigned , default = 0
+#define NR2_MOTION2BETA_LUT0 ((0x1766 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_mot2beta_lut3 // unsigned , default = 32
+//Bit 23:16 reg_matnr_mot2beta_lut2 // unsigned , default = 16
+//Bit 15: 8 reg_matnr_mot2beta_lut1 // unsigned , default = 4
+//Bit 7: 0 reg_matnr_mot2beta_lut0 // unsigned , default = 0
+#define NR2_MOTION2BETA_LUT1 ((0x1767 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_mot2beta_lut7 // unsigned , default = 196
+//Bit 23:16 reg_matnr_mot2beta_lut6 // unsigned , default = 128
+//Bit 15: 8 reg_matnr_mot2beta_lut5 // unsigned , default = 64
+//Bit 7: 0 reg_matnr_mot2beta_lut4 // unsigned , default = 48
+#define NR2_MOTION2BETA_LUT2 ((0x1768 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_mot2beta_lut11 // unsigned , default = 255
+//Bit 23:16 reg_matnr_mot2beta_lut10 // unsigned , default = 255
+//Bit 15: 8 reg_matnr_mot2beta_lut9 // unsigned , default = 240
+//Bit 7: 0 reg_matnr_mot2beta_lut8 // unsigned , default = 224
+#define NR2_MOTION2BETA_LUT3 ((0x1769 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_mot2beta_lut15 // unsigned , default = 255
+//Bit 23:16 reg_matnr_mot2beta_lut14 // unsigned , default = 255
+//Bit 15: 8 reg_matnr_mot2beta_lut13 // unsigned , default = 255
+//Bit 7: 0 reg_matnr_mot2beta_lut12 // unsigned , default = 255
+//========== nr2_snr_regs register end ==========//
+//========== nr2_tnr_regs register begin ==========//
+#define NR2_IIR_CTRL ((0x174e << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15:14 reg_lp_iir_8bit_mode // unsigned , default = 0 10bits; 1: 9bits; 2: 8bits 3: 7bits
+//Bit 13:12 reg_hp_iir_mute_mode // unsigned , default = 0
+//Bit 11: 8 reg_hp_iir_mute_thrd // unsigned , default = 0
+//Bit 7: 6 reg_hp_iir_8bit_mode // unsigned , default = 0
+//Bit 5: 4 reg_lp_iir_mute_mode // unsigned , default = 0
+//Bit 3: 0 reg_lp_iir_mute_thrd // unsigned , default = 0
+#define NR2_MATNR_MTN_CRTL ((0x176a << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:18 reg_matnr_vmtn_use_mode // unsigned , default = 0 0- Vmot, 1- Ymot/2 + (Umot+Vmot)/4; 2- Ymot/2 + max(Umot,Vmot)/2; 3- max(Ymot,Umot, Vmot)
+//Bit 17:16 reg_matnr_umtn_use_mode // unsigned , default = 0 0- Umot, 1- Ymot/2 + (Umot+Vmot)/4; 2- Ymot/2 + max(Umot,Vmot)/2; 3- max(Ymot,Umot, Vmot)
+//Bit 15:14 reg_matnr_ymtn_use_mode // unsigned , default = 0 0- Ymot, 1- Ymot/2 + (Umot+Vmot)/4; 2- Ymot/2 + max(Umot,Vmot)/2; 3- max(Ymot,Umot, Vmot)
+//Bit 13:12 reg_matnr_mtn_txt_mode // unsigned , default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_matnr_mtn_cor_mode // unsigned , default = 1 changes)
+//Bit 7: 4 reg_matnr_mtn_hpf_mode // unsigned , default = 8 extend to u4 for nr4, 0- 1x1; 1: 1x3; 2: 1x5; 3: 3x3; 4: 3o3; 5: 3x5, 6:3x3 SAD, 7: 5x3 SAD, 8-15: drt adaptive
+//Bit 3 reserved
+//Bit 2: 0 reg_matnr_mtn_lpf_mode // unsigned , default = 6 0- 1x1; 1: 1x3; 2: 1x5; 3: 3x3; 4: 3o3; 5: 3x5, 6,7: drt adaptive
+#define NR2_MATNR_MTN_CRTL2 ((0x176b << 2) + 0xff000000)
+//Bit 31:19 reserved
+//Bit 18:16 reg_matnr_iir_bs_ymode // unsigned , default = 6 LPF~~ 0- 1x1; 1: 1x3; 2: 1x5; 3: 3x3; 4: 3o3; 5: 3x5; 6/7: 0
+//Bit 15: 8 reg_matnr_mtnb_alplp_cgain // unsigned , default = 64 to 32
+//Bit 7: 0 reg_matnr_mtnb_alplp_ygain // unsigned , default = 64 to 32
+#define NR2_MATNR_MTN_COR ((0x176c << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15:12 reg_matnr_mtn_cor_cofst // unsigned , default = 3 Offset for Chroma Motion.
+//Bit 11: 8 reg_matnr_mtn_cor_cgain // unsigned , default = 3 to texture based coring for Chroma Motion. Normalized to 16 as 1
+//Bit 7: 4 reg_matnr_mtn_cor_yofst // unsigned , default = 3 Offset for Luma Motion.
+//Bit 3: 0 reg_matnr_mtn_cor_ygain // unsigned , default = 3 to texture based coring for Luma Motion. Normalized to 16 as 1
+#define NR2_MATNR_MTN_GAIN ((0x176d << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_mtn_hp_cgain // unsigned , default = 64 to MotHPF_yuv[k] Chrm channel for motion calculation, normalized to 64 as 1
+//Bit 23:16 reg_matnr_mtn_hp_ygain // unsigned , default = 64 to MotHPF_yuv[k] Luma channel for motion calculation, normalized to 64 as 1
+//Bit 15: 8 reg_matnr_mtn_lp_cgain // unsigned , default = 64 to MotLPF_yuv[k] Chrm channel for motion calculation, normalized to 32 as 1
+//Bit 7: 0 reg_matnr_mtn_lp_ygain // unsigned , default = 64 to MotLPF_yuv[k] Luma channel for motion calculation, normalized to 32 as 1
+#define NR2_MATNR_DEGHOST ((0x176e << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_matnr_deghost_mode // unsigned , default = 0 0:old_deghost; 1:soft_denoise & strong_deghost; 2:strong_denoise & soft_deghost; 3:strong_denoise & strong_deghost
+//Bit 27:25 reserved
+//Bit 24:20 reg_matnr_deghost_ygain // unsigned , default = 4
+//Bit 19:17 reserved
+//Bit 16:12 reg_matnr_deghost_cgain // unsigned , default = 4
+//Bit 11: 9 reserved
+//Bit 8 reg_matnr_deghost_en // unsigned , default = 1 0: disable; 1: enable Enable signal for DeGhost function:0: disable; 1: enable
+//Bit 7: 4 reg_matnr_deghost_cos // unsigned , default = 3 DeGhost Overshoot margin for UV channel, (X2 to u10 scale)
+//Bit 3: 0 reg_matnr_deghost_yos // unsigned , default = 3 DeGhost Overshoot margin for Luma channel, (X2 to u10 scale)
+#define NR2_MATNR_ALPHALP_LUT0 ((0x176f << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphalp_lut3 // unsigned , default = 64 low-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphalp_lut2 // unsigned , default = 128 low-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphalp_lut1 // unsigned , default = 128 low-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphalp_lut0 // unsigned , default = 128 low-pass filter alpha LUT
+#define NR2_MATNR_ALPHALP_LUT1 ((0x1770 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphalp_lut7 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphalp_lut6 // unsigned , default = 128 low-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphalp_lut5 // unsigned , default = 80 low-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphalp_lut4 // unsigned , default = 64 low-pass filter alpha LUT
+#define NR2_MATNR_ALPHALP_LUT2 ((0x1771 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphalp_lut11 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphalp_lut10 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphalp_lut9 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphalp_lut8 // unsigned , default = 255 low-pass filter alpha LUT
+#define NR2_MATNR_ALPHALP_LUT3 ((0x1772 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphalp_lut15 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphalp_lut14 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphalp_lut13 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphalp_lut12 // unsigned , default = 255 low-pass filter alpha LUT
+#define NR2_MATNR_ALPHAHP_LUT0 ((0x1773 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphahp_lut3 // unsigned , default = 64 high-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphahp_lut2 // unsigned , default = 128 high-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphahp_lut1 // unsigned , default = 128 high-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphahp_lut0 // unsigned , default = 128 high-pass filter alpha LUT
+#define NR2_MATNR_ALPHAHP_LUT1 ((0x1774 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphahp_lut7 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphahp_lut6 // unsigned , default = 128 high-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphahp_lut5 // unsigned , default = 80 high-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphahp_lut4 // unsigned , default = 64 high-pass filter alpha LUT
+#define NR2_MATNR_ALPHAHP_LUT2 ((0x1775 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphahp_lut11 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphahp_lut10 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphahp_lut9 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphahp_lut8 // unsigned , default = 255 high-pass filter alpha LUT
+#define NR2_MATNR_ALPHAHP_LUT3 ((0x1776 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphahp_lut15 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphahp_lut14 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphahp_lut13 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphahp_lut12 // unsigned , default = 255 high-pass filter alpha LUT
+#define NR2_MATNR_MTNB_BRT ((0x1777 << 2) + 0xff000000)
+//Bit 31:28 reg_matnr_mtnb_brt_limt_hi // unsigned , default = 0
+//Bit 27:24 reg_matnr_mtnb_brt_slop_hi // unsigned , default = 0
+//Bit 23:16 reg_matnr_mtnb_brt_thrd_hi // unsigned , default = 160
+//Bit 15:12 reg_matnr_mtnb_brt_limt_lo // unsigned , default = 6
+//Bit 11: 8 reg_matnr_mtnb_brt_slop_lo // unsigned , default = 6
+//Bit 7: 0 reg_matnr_mtnb_brt_thrd_lo // unsigned , default = 100
+//========== nr2_tnr_regs register end ==========//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_nr2_regs.h
+//
+//
+// Reading file: nr2_cue_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define NR2_CUE_MODE ((0x1778 << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19 reg_cue2_isabv_org_invert1 // unsigned , default = 0
+//Bit 18 reg_cue2_valid_condition // unsigned , default = 1
+//Bit 17:16 reg_cue2_orgline_flt_sel // unsigned , default = 1
+//Bit 15:12 reg_cue2_orgline_flt_alph // unsigned , default = 4
+//Bit 11 reg_cue2_isabv_org_invert // unsigned , default = 0
+//Bit 10 reg_cue2_iscur_org_invert // unsigned , default = 0
+//Bit 9 reg_cue_enable_r // unsigned , default = 1 right half frame enable
+//Bit 8 reg_cue_enable_l // unsigned , default = 1 left half frame enable
+//Bit 7 reserved
+//Bit 6: 4 reg_cue_con_rplc_mode // unsigned , default = 7 pixel chroma replace mode;
+//Bit 3: 0 reg_cue_chrm_flt_mode // unsigned , default = 5 improvement filter mode,
+#define NR2_CUE_CON_MOT_TH ((0x1779 << 2) + 0xff000000)
+//Bit 31:24 reg_cue_con_cmot_thrd2 // unsigned , default = 20 Detection threshold of up/down two rows, Chroma channel in Chroma Up-sampling Error (CUE) Detection (tighter).
+//Bit 23:16 reg_cue_con_ymot_thrd2 // unsigned , default = 20 Detection threshold of up/mid/down three rows, Luma channel in Chroma Up-sampling Error (CUE) Detection (tighter).
+//Bit 15: 8 reg_cue_con_cmot_thrd // unsigned , default = 20 Detection threshold of up/down two rows, Chroma channel in Chroma Up-sampling Error (CUE) Detection.
+//Bit 7: 0 reg_cue_con_ymot_thrd // unsigned , default = 20 Detection threshold of up/mid/down three rows, Luma channel in Chroma Up-sampling Error (CUE) Detection.
+#define NR2_CUE_CON_DIF0 ((0x177a << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_cue_con_difp1_thrd // unsigned , default = 20 field Intra-Field top/below line chroma difference threshold,
+//Bit 7: 0 reg_cue_con_difcur_thrd // unsigned , default = 0 Field/Frame Intra-Field up/down line chroma difference threshold,
+#define NR2_CUE_CON_DIF1 ((0x177b << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:16 reg_cue_con_rate0 // unsigned , default = 8 Krate to decide CUE by relationship between CUE_diflG and CUE_difEG
+//Bit 15: 8 reg_cue_con_difeg_thrd // unsigned , default = 0 to the difference between current Field/Frame middle line to down line color channel(CUE_difEG).
+//Bit 7: 0 reg_cue_con_diflg_thrd // unsigned , default = 100 to the difference between P1 field top line to current Field/Frame down line color channel (CUE_diflG).
+#define NR2_CUE_CON_DIF2 ((0x177c << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:16 reg_cue_con_rate1 // unsigned , default = 8 Krate to decide CUE by relationship between CUE_difnC and CUE_difEC
+//Bit 15: 8 reg_cue_con_difec_thrd // unsigned , default = 0 to the difference between current Field/Frame middle line to up line color channel(CUE_difEC).
+//Bit 7: 0 reg_cue_con_difnc_thrd // unsigned , default = 100 to the difference between P1 field bot line to current Field/Frame up line color channel (CUE_difnC).
+#define NR2_CUE_CON_DIF3 ((0x177d << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:16 reg_cue_con_rate2 // unsigned , default = 8 Krate to decide CUE by relationship between CUE_difP1 and CUE_difEP1
+//Bit 15: 8 reg_cue_con_difep1_thrd // unsigned , default = 10 top/below line to current field/frame middle line chroma difference (CUE_difEP1) threshold.
+//Bit 7: 0 reg_cue_con_difp1_thrd2 // unsigned , default = 10 field Intra-Field top/below line chroma difference threshold (tighter),
+#define NR2_CUE_PRG_DIF ((0x177e << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20 reg_cue_prg_enable // unsigned , default = 0 bit for progressive video CUE detection.If interlace input video,
+//Bit 19:16 reg_cue_prg_rate // unsigned , default = 4 Krate to decide CUE by relationship between CUE_difCur and (CUE_difEC+CUE_difEG)
+//Bit 15: 8 reg_cue_prg_difceg_thrd // unsigned , default = 40 Frame Intra-Field up-mid and mid-down line chroma difference threshold for progressive video CUE detection,
+//Bit 7: 0 reg_cue_prg_difcur_thrd // unsigned , default = 30 Frame Intra-Field up/down line chroma difference threshold,
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: nr2_cue_regs.h
+//
+#define NR2_CONV_MODE ((0x177f << 2) + 0xff000000)
+//Bit 3:2, Conv_c444_mode The format convert mode about 422 to 444 when data read out line buffer
+//Bit 1:0, Conv_c422_mode the format convert mode about 444 to 422 when data write to line buffer
+//// NR2 REG DEFINE END ////
+//// DET 3D REG DEFINE BEGIN ////
+//// 8'h34~8'h3f | 8'h80~8'h8f | 0x9a-0x9b
+//
+// Reading file: vpu_det3d_regs.h
+//
+//// DET 3D REG DEFINE BEGIN ////
+//// 8'h34~8'h3f
+//// DET 3D REG DEFINE END ////
+#define DET3D_MOTN_CFG ((0x1734 << 2) + 0xff000000)
+//Bit 16, reg_det3d_intr_en Det3d interrupt enable
+//Bit 9:8, reg_Det3D_Motion_Mode U2 Different mode for Motion Calculation of Luma and Chroma:
+// 0: MotY, 1: (2*MotY + (MotU + MotV))/4; 2: Max(MotY, MotU,MotV); 3:Max(MotY, (MotU+MotV)/2)
+//Bit 7:4, reg_Det3D_Motion_Core_Rate U4 K Rate to Edge (HV) details for coring of Motion Calculations, normalized to 32
+//Bit 3:0, reg_Det3D_Motion_Core_Thrd U4 2X: static coring value for Motion Detection.
+#define DET3D_CB_CFG ((0x1735 << 2) + 0xff000000)
+//Bit 7:4, reg_Det3D_ChessBd_HV_ofst U4, Noise immune offset for Horizotnal or vertical combing detection.
+//Bit 3:0, reg_Det3D_ChessBd_NHV_ofst U4, Noise immune offset for NON-Horizotnal or vertical combing detection.
+#define DET3D_SPLT_CFG ((0x1736 << 2) + 0xff000000)
+//Bit 7:4, reg_Det3D_SplitValid_ratio U4, Ratio between max_value and the avg_value of the edge mapping for split line valid detection.
+// The smaller of this value, the easier of the split line detected.
+//Bit 3:0, reg_Det3D_AvgIdx_ratio U4, Ratio to the avg_value of the edge mapping for split line position estimation.
+// The smaller of this value, the more samples will be added to the estimation.
+#define DET3D_HV_MUTE ((0x1737 << 2) + 0xff000000)
+//Bit 23:20, reg_Det3D_Edge_Ver_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Top and Bottom border part.
+//Bit 19:16, reg_Det3D_Edge_Hor_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Left and right border part.
+//Bit 15:12, reg_Det3D_ChessBd_Ver_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part
+//Bit 11:8, reg_Det3D_ChessBd_Hor_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part
+//Bit 7:4, reg_Det3D_STA8X8_Ver_Mute U4 1X: Vertical pixels to be mute from 8x8 statistics calculation in each block.
+//Bit 3:0, reg_Det3D_STA8X8_Hor_Mute U4 1X: Horizontal pixels to be mute from 8x8 statistics calculation in each block.
+#define DET3D_MAT_STA_P1M1 ((0x1738 << 2) + 0xff000000)
+//Bit 31:24, reg_Det3D_STA8X8_P1_K0_R8 U8 SAD to SAI ratio to decide P1, normalized to 256 (0.8)
+//Bit 23:16, reg_Det3D_STA8X8_P1_K1_R7 U8 SAD to ENG ratio to decide P1, normalized to 128 (0.5)
+//Bit 15:8, reg_Det3D_STA8X8_M1_K0_R6 U8 SAD to SAI ratio to decide M1, normalized to 64 (1.1)
+//Bit 7:0, reg_Det3D_STA8X8_M1_K1_R6 U8 SAD to ENG ratio to decide M1, normalized to 64 (0.8)
+#define DET3D_MAT_STA_P1TH ((0x1739 << 2) + 0xff000000)
+//Bit 23:16, reg_Det3D_STAYUV_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (100)
+//Bit 15:8, reg_Det3D_STAEDG_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (80)
+//Bit 7:0, reg_Det3D_STAMOT_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (48)
+#define DET3D_MAT_STA_M1TH ((0x173a << 2) + 0xff000000)
+//Bit 23:16, reg_Det3D_STAYUV_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (100)
+//Bit 15:8, reg_Det3D_STAEDG_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (80)
+//Bit 7:0, reg_Det3D_STAMOT_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (64)
+#define DET3D_MAT_STA_RSFT ((0x173b << 2) + 0xff000000)
+//Bit 5:4, reg_Det3D_STAYUV_RSHFT U2 YUV statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
+// 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
+//Bit 3:2, reg_Det3D_STAEDG_RSHFT U2 Horizontal and Vertical Edge Statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
+// 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
+//Bit 1:0, reg_Det3D_STAMOT_RSHFT U2 Motion SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
+// 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
+#define DET3D_MAT_SYMTC_TH ((0x173c << 2) + 0xff000000)
+//Bit 31:24, reg_Det3D_STALUM_symtc_Th U8 threshold to decide if the Luma statistics is TB or LR symmetric.
+//Bit 23:16, reg_Det3D_STACHR_symtc_Th U8 threshold to decide if the Chroma (UV) statistics is TB or LR symmetric.
+//Bit 15:8, reg_Det3D_STAEDG_symtc_Th U8 threshold to decide if the Horizontal and Vertical Edge statistics is TB or LR symmetric.
+//Bit 7:0, reg_Det3D_STAMOT_symtc_Th U8 threshold to decide if the Motion statistics is TB or LR symmetric.
+#define DET3D_RO_DET_CB_HOR ((0x173d << 2) + 0xff000000)
+//Bit 31:16, RO_Det3D_ChessBd_NHor_value U16 X64: number of Pixels of Horizontally Surely NOT matching Chessboard pattern.
+//Bit 15:0, RO_Det3D_ChessBd_Hor_value U16 X64: number of Pixels of Horizontally Surely matching Chessboard pattern.
+#define DET3D_RO_DET_CB_VER ((0x173e << 2) + 0xff000000)
+//Bit 31:16, RO_Det3D_ChessBd_NVer_value U16 X64: number of Pixels of Vertically Surely NOT matching Chessboard pattern.
+//Bit 15:0, RO_Det3D_ChessBd_Ver_value U16 X64: number of Pixels of Vertically Surely matching Chessboard pattern.
+#define DET3D_RO_SPLT_HT ((0x173f << 2) + 0xff000000)
+//Bit 24, RO_Det3D_Split_HT_valid U1 horizontal LR split border detected valid signal for top half picture
+//Bit 20:16, RO_Det3D_Split_HT_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+//Bit 9:0, RO_Det3D_Split_HT_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+//// DET 3D REG DEFINE BEGIN ////
+//// 8'h80~8'h8f
+#define DET3D_RO_SPLT_HB ((0x1780 << 2) + 0xff000000)
+//Bit 24, RO_Det3D_Split_HB_valid U1 horizontal LR split border detected valid signal for top half picture
+//Bit 20:16, RO_Det3D_Split_HB_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+//Bit 9: 0, RO_Det3D_Split_HB_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+#define DET3D_RO_SPLT_VL ((0x1781 << 2) + 0xff000000)
+//Bit 24, RO_Det3D_Split_VL_valid U1 horizontal LR split border detected valid signal for top half picture
+//Bit 20:16, RO_Det3D_Split_VL_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+//Bit 9: 0, RO_Det3D_Split_VL_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+#define DET3D_RO_SPLT_VR ((0x1782 << 2) + 0xff000000)
+//Bit 24 , RO_Det3D_Split_VR_valid U1 horizontal LR split border detected valid signal for top half picture
+//Bit 20:16, RO_Det3D_Split_VR_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+//Bit 9: 0, RO_Det3D_Split_VR_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+#define DET3D_RO_MAT_LUMA_LR ((0x1783 << 2) + 0xff000000)
+//Bit 15:0, RO_Luma_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically),
+// it can be -1/0/1:-1: most likely not LR symmetric 0: not sure 1: most likely LR symmetric
+//Bit 7:0, RO_Luma_LR_symtc U1*8 Luma statistics left right pure symmetric for each band (8bands vertically),
+// it can be 0/1: 0: not sure 1: most likely LR is pure symmetric
+//Bit 4:0, RO_Luma_LR_sum S5 Total score of 8x8 Luma statistics for LR like decision,
+// the larger this score, the more confidence that this is a LR 3D video. It is sum of RO_Luma_LR_score[0~7]
+#define DET3D_RO_MAT_LUMA_TB ((0x1784 << 2) + 0xff000000)
+//Bit 15:0, RO_Luma_TB_score S2*8 LUMA statistics Top/Bottom decision score for each band (8bands Horizontally),
+//Bit 7:0, RO_Luma_TB_symtc Luma statistics Top/Bottompure symmetric for each band (8bands Horizontally),
+//Bit 4:0, RO_Luma_TB_sum Total score of 8x8 Luma statistics for TB like decision,
+#define DET3D_RO_MAT_CHRU_LR ((0x1785 << 2) + 0xff000000)
+//Bit 15:0, RO_ChrU_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically),
+//Bit 7:0, RO_ChrU_LR_symtc CHRU statistics left right pure symmetric for each band (8bands vertically),
+//Bit 4:0, RO_ChrU_LR_sum Total score of 8x8 ChrU statistics for LR like decision,
+#define DET3D_RO_MAT_CHRU_TB ((0x1786 << 2) + 0xff000000)
+//Bit 15:0, RO_ChrU_TB_score S2*8 CHRU statistics Top/Bottom decision score for each band (8bands Horizontally)
+//Bit 7:0, RO_ChrU_TB_symtc CHRU statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+//Bit 4:0, RO_ChrU_TB_sum Total score of 8x8 ChrU statistics for TB like decision
+#define DET3D_RO_MAT_CHRV_LR ((0x1787 << 2) + 0xff000000)
+//Bit 15:0, RO_ChrV_LR_score S2*8 CHRUstatistics left right decision score for each band (8bands vertically)
+//Bit 7:0, RO_ChrV_LR_symtc CHRV statistics left right pure symmetric for each band (8bands vertically)
+//Bit 4:0, RO_ChrV_LR_sum Total score of 8x8 ChrV statistics for LR like decision
+#define DET3D_RO_MAT_CHRV_TB ((0x1788 << 2) + 0xff000000)
+//Bit 15:0, RO_ChrV_TB_score CHRV statistics Top/Bottom decision score for each band (8bands Horizontally)
+//Bit 7:0, RO_ChrV_TB_symtc CHRV statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+//Bit 4:0, RO_ChrV_TB_sum Total score of 8x8 ChrV statistics for TB like decision
+#define DET3D_RO_MAT_HEDG_LR ((0x1789 << 2) + 0xff000000)
+//Bit 15:0, RO_Hedg_LR_score Horizontal Edge statistics left right decision score for each band (8bands vertically)
+//Bit 7:0, RO_Hedg_LR_symtc Horizontal Edge statistics left right pure symmetric for each band (8bands vertically)
+//Bit 4:0, RO_Hedg_LR_sum Total score of 8x8 Hedg statistics for LR like decision
+#define DET3D_RO_MAT_HEDG_TB ((0x178a << 2) + 0xff000000)
+//Bit 15:0, RO_Hedg_TB_score Horizontal Edge statistics Top/Bottom decision score for each band (8bands Horizontally)
+//Bit 7:0, RO_Hedg_TB_symtc Horizontal Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+//Bit 4:0, RO_Hedg_TB_sum Total score of 8x8 Hedg statistics for TB like decision
+#define DET3D_RO_MAT_VEDG_LR ((0x178b << 2) + 0xff000000)
+//Bit 15:0, RO_Vedg_LR_score Vertical Edge statistics left right decision score for each band (8bands vertically)
+//Bit 7:0, RO_Vedg_LR_symtc Vertical Edge statistics left right pure symmetric for each band (8bands vertically)
+//Bit 4:0, RO_Vedg_LR_sum Total score of 8x8 Vedg statistics for LR like decision
+#define DET3D_RO_MAT_VEDG_TB ((0x178c << 2) + 0xff000000)
+//Bit 15:0, RO_Vedg_TB_score Vertical Edge statistics Top/Bottom decision score for each band (8bands Horizontally)
+//Bit 7:0, RO_Vedg_TB_symtc Vertical Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+//Bit 4:0, RO_Vedg_TB_sum Total score of 8x8 Vedg statistics for TB like decision
+#define DET3D_RO_MAT_MOTN_LR ((0x178d << 2) + 0xff000000)
+//Bit 15:0, RO_Motn_LR_score Motion statistics left right decision score for each band (8bands vertically)
+//Bit 7:0, RO_Motn_LR_symtc Motion statistics left right pure symmetric for each band (8bands vertically)
+//Bit 4:0, RO_Motn_LR_sum Total score of 8x8 Motion statistics for LR like decision
+#define DET3D_RO_MAT_MOTN_TB ((0x178e << 2) + 0xff000000)
+//Bit 15:0, RO_Motn_TB_score Motion statistics Top/Bottom decision score for each band (8bands Horizontally)
+//Bit 7:0, RO_Motn_TB_symtc Motion statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+//Bit 4:0, RO_Motn_TB_sum Total score of 8x8 Motion statistics for TB like decision
+#define DET3D_RO_FRM_MOTN ((0x178f << 2) + 0xff000000)
+//Bit 15:0, RO_Det3D_Frame_Motion U16 frame based motion value sum for still image decision in FW.
+/// mat ram read enter addr
+#define DET3D_RAMRD_ADDR_PORT ((0x179a << 2) + 0xff000000)
+#define DET3D_RAMRD_DATA_PORT ((0x179b << 2) + 0xff000000)
+//
+// Closing file: vpu_det3d_regs.h
+//
+// `define DET3D_RO_SPLT_HB 8'h80
+// //Bit 24, RO_Det3D_Split_HB_valid U1 horizontal LR split border detected valid signal for top half picture
+// //Bit 20:16, RO_Det3D_Split_HB_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+// //Bit 9: 0, RO_Det3D_Split_HB_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+// `define DET3D_RO_SPLT_VL 8'h81
+// //Bit 24, RO_Det3D_Split_VL_valid U1 horizontal LR split border detected valid signal for top half picture
+// //Bit 20:16, RO_Det3D_Split_VL_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+// //Bit 9: 0, RO_Det3D_Split_VL_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+// `define DET3D_RO_SPLT_VR 8'h82
+// //Bit 24 , RO_Det3D_Split_VR_valid U1 horizontal LR split border detected valid signal for top half picture
+// //Bit 20:16, RO_Det3D_Split_VR_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+// //Bit 9: 0, RO_Det3D_Split_VR_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+// `define DET3D_RO_MAT_LUMA_LR 8'h83
+// //Bit 15:0, RO_Luma_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically),
+// // it can be -1/0/1:-1: most likely not LR symmetric 0: not sure 1: most likely LR symmetric
+// //Bit 7:0, RO_Luma_LR_symtc U1*8 Luma statistics left right pure symmetric for each band (8bands vertically),
+// // it can be 0/1: 0: not sure 1: most likely LR is pure symmetric
+// //Bit 4:0, RO_Luma_LR_sum S5 Total score of 8x8 Luma statistics for LR like decision,
+// // the larger this score, the more confidence that this is a LR 3D video. It is sum of RO_Luma_LR_score[0~7]
+// `define DET3D_RO_MAT_LUMA_TB 8'h84
+// //Bit 15:0, RO_Luma_TB_score S2*8 LUMA statistics Top/Bottom decision score for each band (8bands Horizontally),
+// //Bit 7:0, RO_Luma_TB_symtc Luma statistics Top/Bottompure symmetric for each band (8bands Horizontally),
+// //Bit 4:0, RO_Luma_TB_sum Total score of 8x8 Luma statistics for TB like decision,
+// `define DET3D_RO_MAT_CHRU_LR 8'h85
+// //Bit 15:0, RO_ChrU_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically),
+// //Bit 7:0, RO_ChrU_LR_symtc CHRU statistics left right pure symmetric for each band (8bands vertically),
+// //Bit 4:0, RO_ChrU_LR_sum Total score of 8x8 ChrU statistics for LR like decision,
+// `define DET3D_RO_MAT_CHRU_TB 8'h86
+// //Bit 15:0, RO_ChrU_TB_score S2*8 CHRU statistics Top/Bottom decision score for each band (8bands Horizontally)
+// //Bit 7:0, RO_ChrU_TB_symtc CHRU statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+// //Bit 4:0, RO_ChrU_TB_sum Total score of 8x8 ChrU statistics for TB like decision
+// `define DET3D_RO_MAT_CHRV_LR 8'h87
+// //Bit 15:0, RO_ChrV_LR_score S2*8 CHRUstatistics left right decision score for each band (8bands vertically)
+// //Bit 7:0, RO_ChrV_LR_symtc CHRV statistics left right pure symmetric for each band (8bands vertically)
+// //Bit 4:0, RO_ChrV_LR_sum Total score of 8x8 ChrV statistics for LR like decision
+// `define DET3D_RO_MAT_CHRV_TB 8'h88
+// //Bit 15:0, RO_ChrV_TB_score CHRV statistics Top/Bottom decision score for each band (8bands Horizontally)
+// //Bit 7:0, RO_ChrV_TB_symtc CHRV statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+// //Bit 4:0, RO_ChrV_TB_sum Total score of 8x8 ChrV statistics for TB like decision
+// `define DET3D_RO_MAT_HEDG_LR 8'h89
+// //Bit 15:0, RO_Hedg_LR_score Horizontal Edge statistics left right decision score for each band (8bands vertically)
+// //Bit 7:0, RO_Hedg_LR_symtc Horizontal Edge statistics left right pure symmetric for each band (8bands vertically)
+// //Bit 4:0, RO_Hedg_LR_sum Total score of 8x8 Hedg statistics for LR like decision
+// `define DET3D_RO_MAT_HEDG_TB 8'h8a
+// //Bit 15:0, RO_Hedg_TB_score Horizontal Edge statistics Top/Bottom decision score for each band (8bands Horizontally)
+// //Bit 7:0, RO_Hedg_TB_symtc Horizontal Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+// //Bit 4:0, RO_Hedg_TB_sum Total score of 8x8 Hedg statistics for TB like decision
+// `define DET3D_RO_MAT_VEDG_LR 8'h8b
+// //Bit 15:0, RO_Vedg_LR_score Vertical Edge statistics left right decision score for each band (8bands vertically)
+// //Bit 7:0, RO_Vedg_LR_symtc Vertical Edge statistics left right pure symmetric for each band (8bands vertically)
+// //Bit 4:0, RO_Vedg_LR_sum Total score of 8x8 Vedg statistics for LR like decision
+// `define DET3D_RO_MAT_VEDG_TB 8'h8c
+// //Bit 15:0, RO_Vedg_TB_score Vertical Edge statistics Top/Bottom decision score for each band (8bands Horizontally)
+// //Bit 7:0, RO_Vedg_TB_symtc Vertical Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+// //Bit 4:0, RO_Vedg_TB_sum Total score of 8x8 Vedg statistics for TB like decision
+// `define DET3D_RO_MAT_MOTN_LR 8'h8d
+// //Bit 15:0, RO_Motn_LR_score Motion statistics left right decision score for each band (8bands vertically)
+// //Bit 7:0, RO_Motn_LR_symtc Motion statistics left right pure symmetric for each band (8bands vertically)
+// //Bit 4:0, RO_Motn_LR_sum Total score of 8x8 Motion statistics for LR like decision
+// `define DET3D_RO_MAT_MOTN_TB 8'h8e
+// //Bit 15:0, RO_Motn_TB_score Motion statistics Top/Bottom decision score for each band (8bands Horizontally)
+// //Bit 7:0, RO_Motn_TB_symtc Motion statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+// //Bit 4:0, RO_Motn_TB_sum Total score of 8x8 Motion statistics for TB like decision
+// `define DET3D_RO_FRM_MOTN 8'h8f
+// //Bit 15:0, RO_Det3D_Frame_Motion U16 frame based motion value sum for still image decision in FW.
+#define DI_EI_CTRL10 ((0x1793 << 2) + 0xff000000)
+//bit 31:28, reg_ei_caldrt_hstrrgchk_drtth
+//bit 27:24, reg_ei_caldrt_hstrrgchk_frcverthrd
+//bit 23:20, reg_ei_caldrt_hstrrgchk_mg
+//bit 19, reg_ei_caldrt_hstrrgchk_1sidnul
+//bit 18, reg_ei_caldrt_hstrrgchk_excpcnf
+//bit 17:16, reg_ei_caldrt_hstrrgchk_ws
+//bit 15, reg_ei_caldrt_hstrrgchk_en
+//bit 14:13, reg_ei_caldrt_hpncheck_mode
+//bit 12, reg_ei_caldrt_hpncheck_mute
+//bit 11:9, reg_ei_caldrt_hcnfcheck_mg2
+//bit 8:6, reg_ei_caldrt_hcnfcheck_mg1
+//bit 5:4, reg_ei_caldrt_hcnfcheck_mode
+//bit 3:0, reg_ei_caldrt_hcnfcheck_mg2
+#define DI_NR_1_CTRL0 ((0x1794 << 2) + 0xff000000)
+#define DI_NR_1_CTRL1 ((0x1795 << 2) + 0xff000000)
+#define DI_NR_1_CTRL2 ((0x1796 << 2) + 0xff000000)
+#define DI_NR_1_CTRL3 ((0x1797 << 2) + 0xff000000)
+#define DI_EI_XWIN0 ((0x1798 << 2) + 0xff000000)
+//bit 27:16, ei_xend0
+//bit 11:0, ei_xstart0
+#define DI_EI_XWIN1 ((0x1799 << 2) + 0xff000000)
+/// mat ram read enter addr
+// `define DET3D_RAMRD_ADDR_PORT 8'h9a
+// `define DET3D_RAMRD_DATA_PORT 8'h9b
+#define NR2_CFR_PARA_CFG0 ((0x179c << 2) + 0xff000000)
+//Bit 8, reg_CFR_CurDif_luma_mode Current Field Top/Bot line Luma difference calculation mode
+//Bit 7:6, reg_MACFR_frm_phase U2 This will be a field based phase register that need to be set by FW phase to phase:
+// this will be calculated based on dbdr_phase of the specific line of this frame.
+// u1: dbdr_phase=1, center line is DB in current line; dbdr_phase=2, center line is Dr in current line;
+//Bit 5:4, reg_CFR_CurDif_tran_mode U2 Current Field Top/Bot line Luma/Chroma transition level calculation mode,
+//Bit 3:2, reg_CFR_alpha_mode U2 Alpha selection mode for CFR block from curAlp and motAlp i.e. 0: motAlp; 1: (motAlp+curAlp)/2; 2: min(motAlp,curAlp); 3: max(motAlp,curAlp);
+//Bit 1:0, reg_CFR_Motion_Luma_mode U2 LumaMotion Calculation mode for MA-CFR. 0: top/bot Lumma motion; 1: middle Luma Motion 2: top/bot + middle motion; 3: max(top/tot motion, middle motion)
+#define NR2_CFR_PARA_CFG1 ((0x179d << 2) + 0xff000000)
+//Bit 23:16, reg_CFR_alpha_gain gain to map muxed curAlp and motAlp to alpha that will be used for final blending.
+//Bit 15: 8, reg_CFR_Motion_ofst Offset to Motion to calculate the motAlp, e,g:motAlp= reg_CFR_Motion_ofst- Motion;This register can be seen as the level of motion that we consider it at moving.
+//Bit 7: 0, reg_CFR_CurDif_gain gain to CurDif to map to alpha, normalized to 32;
+//// DET 3D REG DEFINE END ////
+#define DI_EI_CTRL11 ((0x179e << 2) + 0xff000000)
+//bit 30:29, reg_ei_amb_detect_mode
+//bit 28:24, reg_ei_amb_detect_winth
+//bit 23:21, reg_ei_amb_decide_rppth
+//bit 20:19, reg_ei_retime_lastmappncnfltchk_drtth
+//bit 18:16, reg_ei_retime_lastmappncnfltchk_mode
+//bit 15:14, reg_ei_retime_lastmapvertfrcchk_mode
+//bit 13:12, reg_ei_retime_lastvertfrcchk_mode
+//bit 11:8, reg_ei_retime_lastpnchk_drtth
+//bit 6, reg_ei_retime_lastpnchk_en
+//bit 5:4, reg_ei_retime_mode
+//bit 3, reg_ei_retime_last_en
+//bit 2, reg_ei_retime_ab_en
+//bit 1, reg_ei_caldrt_hstrvertfrcchk_en
+//bit 0, reg_ei_caldrt_hstrrgchk_mode
+#define DI_EI_CTRL12 ((0x179f << 2) + 0xff000000)
+//bit 31:28, reg_ei_drtdelay2_lmt
+//bit 27:26, reg_ei_drtdelay2_notver_lrwin
+//bit 25:24, reg_ei_drtdelay_mode
+//bit 23, reg_ei_drtdelay2_mode
+//bit 22:20, reg_ei_assign_xla_signm0th
+//bit 19, reg_ei_assign_pkbiasvert_en
+//bit 18, reg_ei_assign_xla_en
+//bit 17:16, reg_ei_assign_xla_mode
+//bit 15:12, reg_ei_assign_nlfilter_magin
+//bit 11:8, reg_ei_localsearch_maxrange
+//bit 7:4, reg_ei_xla_drtth
+//bit 3:0, reg_ei_flatmsad_thrd
+//`define DI_DIWR_CANVAS 8'ha0
+//`define DI_DIWR_URGENT 8'ha1
+//`define DI_NRWR_CANVAS 8'ha2
+//`define DI_NRWR_URGENT 8'ha7
+//`define DI_CONTWR_X 8'ha0
+//`define DI_CONTWR_Y 8'ha1
+//`define DI_CONTWR_CTRL 8'ha2
+//`define DI_CONTPRD_X 8'ha3
+//`define DI_CONTPRD_Y 8'ha4
+//`define DI_CONTP2RD_X 8'ha5
+//`define DI_CONTP2RD_Y 8'ha6
+#define DI_RO_PRE_FIELD_CNT0 ((0x17a3 << 2) + 0xff000000)
+#define DI_RO_PRE_FIELD_CNT1 ((0x17a4 << 2) + 0xff000000)
+#define DI_RO_POS_FRAME_CNT0 ((0x17a5 << 2) + 0xff000000)
+#define DI_RO_POS_FRAME_CNT1 ((0x17a6 << 2) + 0xff000000)
+//`define DI_CONTRD_CTRL 8'ha7
+#define DI_EI_CTRL13 ((0x17a8 << 2) + 0xff000000)
+//bit 27:24, reg_ei_int_drt2x_chrdrt_limit
+//bit 23:20, reg_ei_int_drt16x_core
+//bit 19:16, reg_ei_int_drtdelay2_notver_cancv
+//bit 15:8, reg_ei_int_drtdelay2_notver_sadth
+//bit 7:0, reg_ei_int_drtdelay2_vlddrt_sadth
+#define DI_MTN_1_CTRL6 ((0x17a9 << 2) + 0xff000000)
+//bit 31:24, mtn_m1b_extnd
+//bit 23:16, mtn_m1b_errod
+//bit 15: 8, mtn_core_ykinter
+//bit 7: 0, mtn_core_ckinter
+#define DI_MTN_1_CTRL7 ((0x17aa << 2) + 0xff000000)
+//bit 31:24, mtn_core_mxcmby
+//bit 23:16, mtn_core_mxcmbc
+//bit 15: 8, mtn_core_y
+//bit 7: 0, mtn_core_c
+#define DI_MTN_1_CTRL8 ((0x17ab << 2) + 0xff000000)
+//bit 31:24, mtn_fcore_ykinter
+//bit 23:16, mtn_fcore_ckinter
+//bit 15: 8, mtn_fcore_ykintra
+//bit 7: 0, mtn_fcore_ckintra
+#define DI_MTN_1_CTRL9 ((0x17ac << 2) + 0xff000000)
+//bit 31:24, mtn_fcore_2yrate
+//bit 23:16, mtn_fcore_2crate
+//bit 15: 8, mtn_fcore_y
+//bit 7: 0, mtn_fcore_c
+#define DI_MTN_1_CTRL10 ((0x17ad << 2) + 0xff000000)
+//bit 27:24, mtn_motfld0
+//bit 19:16, mtn_stlfld0
+//bit 11: 8, mtn_motfld1
+//bit 3: 0, mtn_stlfld1
+#define DI_MTN_1_CTRL11 ((0x17ae << 2) + 0xff000000)
+//bit 27:24, mtn_smotevn
+//bit 20:16, mtn_smotodd
+//bit 11: 8, mtn_sstlevn
+//bit 4: 0, mtn_sstlodd
+#define DI_MTN_1_CTRL12 ((0x17af << 2) + 0xff000000)
+//bit 31:24, mtn_mgain
+//bit 17:16, mtn_mmode
+//bit 15: 8, mtn_sthrd
+//bit 4: 0, mtn_sgain
+//`define DI_NRWR_X 8'hc0
+//`define DI_NRWR_Y 8'hc1
+//bit 31:30 nrwr_words_lim
+//bit 29 nrwr_rev_y
+//bit 28:16 nrwr_start_y
+//bit 15 nrwr_ext_en
+//bit 12:0 nrwr_end_y
+//`define DI_NRWR_CTRL 8'hc2
+//bit 31 pending_ddr_wrrsp_diwr
+//bit 30 nrwr_reg_swap
+//bit 29:26 nrwr_burst_lim
+//bit 25 nrwr_canvas_syncen
+//bit 24 nrwr_no_clk_gate
+//bit 23:22 nrwr_rgb_mode 0:422 to one canvas;1:4:4:4 to one canvas;
+ //2:Y to luma , CBCR to chroma canvas ,for nv12/21; 3 : reserved
+//bit 21:20 nrwr_hconv_mode
+//bit 19:18 nrwr_vconv_mode
+//bit 17 nrwr_swap_cbcr
+//bit 16 nrwr_urgent
+//bit 15:8 nrwr_canvas_index_chroma
+//bit 7:0 nrwr_canvas_index_luma
+//`define DI_MTNWR_X 8'hc3
+//`define DI_MTNWR_Y 8'hc4
+//`define DI_MTNWR_CTRL 8'hc5
+#define DI_RO_CRC_NRWR ((0x17c0 << 2) + 0xff000000)
+#define DI_RO_CRC_MTNWR ((0x17c1 << 2) + 0xff000000)
+#define DI_RO_CRC_DEINT ((0x17c2 << 2) + 0xff000000)
+#define DI_CRC_CHK0 ((0x17c3 << 2) + 0xff000000)
+#define DI_CRC_CHK1 ((0x17c4 << 2) + 0xff000000)
+//`define DI_DIWR_X 8'hc6
+//`define DI_DIWR_Y 8'hc7
+//bit 31:30 diwr_words_lim
+//bit 29 diwr_rev_y
+//bit 28:16 diwr_start_y
+//bit 15 diwr_ext_en
+//bit 12:0 diwr_end_y
+//`define DI_DIWR_CTRL 8'hc8
+//bit 31 pending_ddr_wrrsp_diwr
+//bit 30 diwr_reg_swap
+//bit 29:26 diwr_burst_lim
+//bit 25 diwr_canvas_syncen
+//bit 24 diwr_no_clk_gate
+//bit 23:22 diwr_rgb_mode 0:422 to one canvas;1:4:4:4 to one canvas;
+ //2:Y to luma , CBCR to chroma canvas ,for nv12/21; 3 : reserved
+//bit 21:20 diwr_hconv_mode
+//bit 19:18 diwr_vconv_mode
+//bit 17 diwr_swap_cbcr
+//bit 16 diwr_urgent
+//bit 15:8 diwr_canvas_index_chroma
+//bit 7:0 diwr_canvas_index_luma
+//`define DI_MTNCRD_X 8'hc9
+//`define DI_MTNCRD_Y 8'hca
+//`define DI_MTNPRD_X 8'hcb
+//`define DI_MTNPRD_Y 8'hcc
+//`define DI_MTNRD_CTRL 8'hcd
+#define DI_TOP_PRE_CTRL ((0x17c5 << 2) + 0xff000000)
+#define DI_TOP_POST_CTRL ((0x17c6 << 2) + 0xff000000)
+#define DI_PRE_GL_CTRL ((0x17c7 << 2) + 0xff000000)
+#define DI_PRE_GL_THD ((0x17c8 << 2) + 0xff000000)
+#define DI_POST_GL_CTRL ((0x17c9 << 2) + 0xff000000)
+#define DI_POST_GL_THD ((0x17ca << 2) + 0xff000000)
+#define DI_RO_PRE_DBG ((0x17cb << 2) + 0xff000000)
+#define DI_RO_POST_DBG ((0x17cc << 2) + 0xff000000)
+#define DI_TOP_CTRL ((0x17cd << 2) + 0xff000000)
+#define DI_AFBCD_GCLK0 ((0x17ce << 2) + 0xff000000)
+#define DI_AFBCD_GCLK1 ((0x17cf << 2) + 0xff000000)
+#define DI_RDMIF_DEPTH0 ((0x17d0 << 2) + 0xff000000)
+#define DI_RDMIF_DEPTH1 ((0x17d1 << 2) + 0xff000000)
+#define DI_RDMIF_DEPTH2 ((0x17d2 << 2) + 0xff000000)
+//`define DI_INP_GEN_REG 8'hce
+//`define DI_INP_CANVAS0 8'hcf
+//`define DI_INP_LUMA_X0 8'hd0
+//`define DI_INP_LUMA_Y0 8'hd1
+//`define DI_INP_CHROMA_X0 8'hd2
+//`define DI_INP_CHROMA_Y0 8'hd3
+//`define DI_INP_RPT_LOOP 8'hd4
+//`define DI_INP_LUMA0_RPT_PAT 8'hd5
+//`define DI_INP_CHROMA0_RPT_PAT 8'hd6
+//`define DI_INP_DUMMY_PIXEL 8'hd7
+//`define DI_INP_LUMA_FIFO_SIZE 8'hd8
+//`define DI_INP_RANGE_MAP_Y 8'hba
+//`define DI_INP_RANGE_MAP_CB 8'hbb
+//`define DI_INP_RANGE_MAP_CR 8'hbc
+//`define DI_INP_GEN_REG2 8'h91
+//
+//`define DI_INP_FMT_CTRL 8'hd9
+//`define DI_INP_FMT_W 8'hda
+////
+//`define DI_MEM_GEN_REG 8'hdb
+//`define DI_MEM_CANVAS0 8'hdc
+//`define DI_MEM_LUMA_X0 8'hdd
+//`define DI_MEM_LUMA_Y0 8'hde
+//`define DI_MEM_CHROMA_X0 8'hdf
+//`define DI_MEM_CHROMA_Y0 8'he0
+//`define DI_MEM_RPT_LOOP 8'he1
+//`define DI_MEM_LUMA0_RPT_PAT 8'he2
+//`define DI_MEM_CHROMA0_RPT_PAT 8'he3
+//`define DI_MEM_DUMMY_PIXEL 8'he4
+//`define DI_MEM_LUMA_FIFO_SIZE 8'he5
+//`define DI_MEM_RANGE_MAP_Y 8'hbd
+//`define DI_MEM_RANGE_MAP_CB 8'hbe
+//`define DI_MEM_RANGE_MAP_CR 8'hbf
+//`define DI_MEM_GEN_REG2 8'h92
+//
+//`define DI_MEM_FMT_CTRL 8'he6
+//`define DI_MEM_FMT_W 8'he7
+//
+//`define DI_IF1_GEN_REG 8'he8
+//`define DI_IF1_CANVAS0 8'he9
+//`define DI_IF1_LUMA_X0 8'hea
+//`define DI_IF1_LUMA_Y0 8'heb
+//`define DI_IF1_CHROMA_X0 8'hec
+//`define DI_IF1_CHROMA_Y0 8'hed
+//`define DI_IF1_RPT_LOOP 8'hee
+//`define DI_IF1_LUMA0_RPT_PAT 8'hef
+//`define DI_IF1_CHROMA0_RPT_PAT 8'hf0
+//`define DI_IF1_DUMMY_PIXEL 8'hf1
+//`define DI_IF1_LUMA_FIFO_SIZE 8'hf2
+//`define DI_IF1_RANGE_MAP_Y 8'hfc
+//`define DI_IF1_RANGE_MAP_CB 8'hfd
+//`define DI_IF1_RANGE_MAP_CR 8'hfe
+//`define DI_IF1_GEN_REG2 8'h90
+//
+//`define DI_IF1_FMT_CTRL 8'hf3
+//`define DI_IF1_FMT_W 8'hf4
+//
+//
+//`define DI_CHAN2_GEN_REG 8'hf5
+//`define DI_CHAN2_CANVAS0 8'hf6
+//`define DI_CHAN2_LUMA_X0 8'hf7
+//`define DI_CHAN2_LUMA_Y0 8'hf8
+//`define DI_CHAN2_CHROMA_X0 8'hf9
+//`define DI_CHAN2_CHROMA_Y0 8'hfa
+//`define DI_CHAN2_RPT_LOOP 8'hfb
+//`define DI_CHAN2_LUMA0_RPT_PAT 8'hb0
+//`define DI_CHAN2_CHROMA0_RPT_PAT 8'hb1
+//`define DI_CHAN2_DUMMY_PIXEL 8'hb2
+//`define DI_CHAN2_LUMA_FIFO_SIZE 8'hb3
+//`define DI_CHAN2_RANGE_MAP_Y 8'hb4
+//`define DI_CHAN2_RANGE_MAP_CB 8'hb5
+//`define DI_CHAN2_RANGE_MAP_CR 8'hb6
+//`define DI_CHAN2_GEN_REG2 8'hb7
+//`define DI_CHAN2_FMT_CTRL 8'hb8
+//`define DI_CHAN2_FMT_W 8'hb9
+//
+// Closing file: vpu_mad_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: MADD_VCBUS_BASE = 0x18
+// -----------------------------------------------
+//
+// Reading file: di_dolby_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DOLBY_CORE1C_REG_START ((0x1800 << 2) + 0xff000000)
+#define DOLBY_CORE1C_CLKGATE_CTRL ((0x18f2 << 2) + 0xff000000)
+#define DOLBY_CORE1C_SWAP_CTRL0 ((0x18f3 << 2) + 0xff000000)
+#define DOLBY_CORE1C_SWAP_CTRL1 ((0x18f4 << 2) + 0xff000000)
+#define DOLBY_CORE1C_SWAP_CTRL2 ((0x18f5 << 2) + 0xff000000)
+#define DOLBY_CORE1C_SWAP_CTRL3 ((0x18f6 << 2) + 0xff000000)
+#define DOLBY_CORE1C_SWAP_CTRL4 ((0x18f7 << 2) + 0xff000000)
+#define DOLBY_CORE1C_SWAP_CTRL5 ((0x18f8 << 2) + 0xff000000)
+#define DOLBY_CORE1C_DMA_CTRL ((0x18f9 << 2) + 0xff000000)
+#define DOLBY_CORE1C_DMA_STATUS ((0x18fa << 2) + 0xff000000)
+#define DOLBY_CORE1C_STATUS0 ((0x18fb << 2) + 0xff000000)
+#define DOLBY_CORE1C_STATUS1 ((0x18fc << 2) + 0xff000000)
+#define DOLBY_CORE1C_STATUS2 ((0x18fd << 2) + 0xff000000)
+#define DOLBY_CORE1C_STATUS3 ((0x18fe << 2) + 0xff000000)
+#define DOLBY_CORE1C_DMA_PORT ((0x18ff << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: di_dolby_regs.h
+//
+//`include "di_inp_afbc_dec_regs.h"
+//`include "di_mem_afbc_dec_regs.h"
+//`include "fgrain_di_regs.h"
+// -----------------------------------------------
+// REG_BASE: VPP2_VCBUS_BASE = 0x19
+// -----------------------------------------------
+//`include "vpp2_regs.h"
+//
+// Reading file: vregs_clk2.h
+//
+//===========================================================================
+// Video Interface Registers 0xa00 - 0xaff
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VIU_VCBUS_BASE = 0x1a
+// -----------------------------------------------
+#define VIU_ADDR_START ((0x1a00 << 2) + 0xff000000)
+#define VIU_ADDR_END ((0x1aff << 2) + 0xff000000)
+//`define TRACE_REG 8'ff
+//------------------------------------------------------------------------------
+// VIU top-level registers
+//------------------------------------------------------------------------------
+// Bit 0 RW, osd1_reset
+// Bit 1 RW, osd2_reset
+// Bit 2 RW, vd1_reset
+// Bit 3 RW, vd1_fmt_reset
+// Bit 4 RW, vd2_reset
+// Bit 5 RW, vd2_fmt_reset
+// Bit 6 RW, di_dsr1to2_reset
+// Bit 7 RW, vpp_reset
+// Bit 8 RW, di_if1_reset
+// Bit 9 RW, di_if1_fmt_reset
+// Bit 10 RW, di_inp_reset
+// Bit 11 RW, di_inp_fmt_reset
+// Bit 12 RW, di_mem_reset
+// Bit 13 RW, di_mem_fmt_reset
+// Bit 14 RW, di_nr_wr_mif_reset
+// Bit 15 RW, dein_wr_mif_reset
+// Bit 16 RW, di_chan2_mif_reset
+// Bit 17 RW, di_mtn_wr_mif_reset
+// Bit 18 RW, di_mtn_rd_mif_reset
+// Bit 19 RW, di_mad_reset
+// Bit 20 RW, vdin0_reset
+// Bit 21 RW, vdin1_reset
+// Bit 22 RW, nrin_mux_reset
+// Bit 23 RW, vdin0_wr_reset
+// Bit 24 RW, vdin1_wr_reset
+// Bit 25 RW, reserved
+// Bit 26 RW, d2d3_reset
+// Bit 27 RW, di_cont_wr_mif_reset
+// Bit 28 RW, di_cont_rd_mif_reset
+#define VIU_SW_RESET ((0x1a01 << 2) + 0xff000000)
+#define VIU_SW_RESET0 ((0x1a02 << 2) + 0xff000000)
+// Bit 0 RW, software reset for mcvecrd_mif
+// Bit 1 RW, software reset for mcinfowr_mif
+// Bit 2 RW, software reset for mcinford_mif
+#define VIU_SECURE_REG ((0x1a04 << 2) + 0xff000000)
+// Bit 0 RW, dolby core1_tv secure w and r
+// Bit 1 RW, dolby core2 secure w and r
+// Bit 2 RW, dolby core3 secure w and r
+// Bit 3 RW, for osd1 secure read
+// Bit 4 RW, for osd2 secure read
+#define DOLBY_INT_STAT ((0x1a05 << 2) + 0xff000000)
+// todo
+//bit 15:12 osdbld_gclk_ctrl 3:2 regclk ctrl 1:0 blending clk control
+//bit 8 if true, vsync interrup is generate only field == 0
+//bit 7:0 fix_disable
+#define VIU_MISC_CTRL0 ((0x1a06 << 2) + 0xff000000)
+#define VIU_MISC_CTRL1 ((0x1a07 << 2) + 0xff000000)
+// Bit 15:14 mali_afbcd_gclk_ctrl mali_afbcd clock gate control[5:4]
+// Bit 12 osd1_afbcd_axi_mux 0 : use the osd mif as input; 1 : use afbcd as input
+// Bit 11:8 mali_afbcd_gclk_ctrl mali_afbcd clock gate control[3:0]
+// Bit 7:2 vd2_afbcd_gclk_ctrl vd2_afbcd clock gate control
+// Bit 1 vpp_vd2_din_sel 0: vpp vd2 sel the mif input; 1: vpp vd2 sel the dos afbcd
+// Bit 0 vd2_afbcd_out_sel 0: vd2_afbcd output to vpp; 1 : vd2_afbcd output to di inp
+#define VIU_SECURE_DUMMY ((0x1a08 << 2) + 0xff000000)
+#define VIU_SECURE_ST_RO ((0x1a09 << 2) + 0xff000000)
+// Bit 31:30 vdin0 dout splitter, bit 0 turns on vdin0 to old path, bit 1 turns on vdin0 to d2d3_intf vdin0 input path
+// Bit 29:28 vdin1 dout splitter, bit 0 turns on vdin1 to old path, bit 1 turns on vdin1 to d2d3_intf vdin1 input path
+// Bit 27:26 NR write dout splitter, bit 0 turns on NR write to old path, bit 1 turns on NR WR to d2d3_intf NR WR input path
+// Bit 23 if true, turn on clk_d2d3_reg (register clock)
+// Bit 22 if true, turn on clk_d2d3
+// Bit 21 reg_v1_go_line
+// Bit 20 reg_v1_go_field
+// Bit 19 reg_v0_go_field
+// Bit 18:16 v1_gofld_sel, 000: display go_field/go_line, 001: DI pre_frame_rst/go_line, 010: vdin0 go_field/go_line,
+//011: vdin1 go_field/go_line, otherwise: force go_field by reg_v1_go_field(bit20), force go_line by reg_v1_go_line(bit21)
+// Bit 15:13 v0_gofld_sel, 000: display go_field, 001: DI pre_frame_rst, 010: vdin0 go_field, 011: vdin1 go_field, otherwise: force go_field by
+// reg_v0_go_field(bit19)
+// Bit 12:6 hole_lines for d2d3 depth read interface
+// Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 fomart output), 2'b10: scale output, otherwise nothing as v1
+// Bit 3 use_vdin_eol, if true, use vdin eol as the v0_eol, otherwise using length to get the v0_eol
+// Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 fomart output), 101: vpp scale output
+//
+// `define D2D3_INTF_CTRL0 8'h09
+#define VD1_AFBCD0_MISC_CTRL ((0x1a0a << 2) + 0xff000000)
+#define VD2_AFBCD1_MISC_CTRL ((0x1a0b << 2) + 0xff000000)
+#define DOLBY_PATH_CTRL ((0x1a0c << 2) + 0xff000000)
+#define WR_BACK_MISC_CTRL ((0x1a0d << 2) + 0xff000000)
+#define OSD_PATH_MISC_CTRL ((0x1a0e << 2) + 0xff000000)
+#define MALI_AFBCD_TOP_CTRL ((0x1a0f << 2) + 0xff000000)
+#define VIU_DATA_SEC ((0x1a50 << 2) + 0xff000000)
+#define VIU_FRM_CTRL ((0x1a51 << 2) + 0xff000000)
+#define VIU_RDMIF_DEPTH ((0x1a52 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// OSD1 registers
+//------------------------------------------------------------------------------
+// Bit 31 Reserved
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// 0=use gated clock for low power.
+// Bit 29 R, test_rd_dsr
+// Bit 28 R, osd_done
+// Bit 27:24 R, osd_blk_mode
+// Bit 23:22 R, osd_blk_ptr
+// Bit 21 R, osd_enable
+//
+// Bit 20:12 RW, global_alpha
+// Bit 11 RW, test_rd_en
+// Bit 10: 9 Reserved for control signals
+// Bit 8: 5 RW, ctrl_mtch_y
+// Bit 4 RW, ctrl_422to444
+// Bit 3: 0 RW, osd_blk_enable. Bit 0 to enable block 0: 1=enable, 0=disable;
+// Bit 1 to enable block 1, and so on.
+#define VIU_OSD1_CTRL_STAT ((0x1a10 << 2) + 0xff000000)
+// Bit 31:26 Reserved
+// Bit 25:16 R, fifo_count
+// Bit 15 RW, osd_dpath_sel 0-osd1 mif 1-vpu mali afbcd
+// Bit 14 RW, replaced_alpha_en
+// Bit 13: 6 RW, replaced_alpha
+// Bit 5: 4 RW, hold_fifo_lines[6:5]
+// Bit 3 RW, rgb2yuv_full_range
+// Bit 2 RW, alpha_9b_mode
+// Bit 1 RW, reserved
+// Bit 0 RW, color_expand_mode
+#define VIU_OSD1_CTRL_STAT2 ((0x1a2d << 2) + 0xff000000)
+// Bit 31: 9 Reserved
+// Bit 8 RW, 0 = Write LUT, 1 = Read LUT
+// Bit 7: 0 RW, lut_addr
+#define VIU_OSD1_COLOR_ADDR ((0x1a11 << 2) + 0xff000000)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define VIU_OSD1_COLOR ((0x1a12 << 2) + 0xff000000)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define VIU_OSD1_TCOLOR_AG0 ((0x1a17 << 2) + 0xff000000)
+#define VIU_OSD1_TCOLOR_AG1 ((0x1a18 << 2) + 0xff000000)
+#define VIU_OSD1_TCOLOR_AG2 ((0x1a19 << 2) + 0xff000000)
+#define VIU_OSD1_TCOLOR_AG3 ((0x1a1a << 2) + 0xff000000)
+// Bit 31:30 Reserved
+// Bit 29 RW, y_rev: 0=normal read, 1=reverse read in Y direction
+// Bit 28 RW, x_rev: 0=normal read, 1=reverse read in X direction
+// Bit 27:24 Reserved
+// Bit 23:16 RW, tbl_addr
+// Bit 15 RW, little_endian: 0=big endian, 1=little endian
+// Bit 14 RW, rpt_y
+// Bit 13:12 RW, interp_ctrl. 0x=No interpolation; 10=Interpolate with previous
+// pixel; 11=Interpolate with the average value
+// between previous and next pixel.
+// Bit 11: 8 RW, osd_blk_mode
+// Bit 7 RW, rgb_en
+// Bit 6 RW, tc_alpha_en
+// Bit 5: 2 RW, color_matrix
+// Bit 1 RW, interlace_en
+// Bit 0 RW, interlace_sel_odd
+#define VIU_OSD1_BLK0_CFG_W0 ((0x1a1b << 2) + 0xff000000)
+#define VIU_OSD1_BLK1_CFG_W0 ((0x1a1f << 2) + 0xff000000)
+#define VIU_OSD1_BLK2_CFG_W0 ((0x1a23 << 2) + 0xff000000)
+#define VIU_OSD1_BLK3_CFG_W0 ((0x1a27 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, x_end
+// Bit 15:13 Reserved
+// Bit 12: 0 RW, x_start
+#define VIU_OSD1_BLK0_CFG_W1 ((0x1a1c << 2) + 0xff000000)
+#define VIU_OSD1_BLK1_CFG_W1 ((0x1a20 << 2) + 0xff000000)
+#define VIU_OSD1_BLK2_CFG_W1 ((0x1a24 << 2) + 0xff000000)
+#define VIU_OSD1_BLK3_CFG_W1 ((0x1a28 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, y_end
+// Bit 15:13 Reserved
+// Bit 12: 0 RW, y_start
+#define VIU_OSD1_BLK0_CFG_W2 ((0x1a1d << 2) + 0xff000000)
+#define VIU_OSD1_BLK1_CFG_W2 ((0x1a21 << 2) + 0xff000000)
+#define VIU_OSD1_BLK2_CFG_W2 ((0x1a25 << 2) + 0xff000000)
+#define VIU_OSD1_BLK3_CFG_W2 ((0x1a29 << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, h_end
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, h_start
+#define VIU_OSD1_BLK0_CFG_W3 ((0x1a1e << 2) + 0xff000000)
+#define VIU_OSD1_BLK1_CFG_W3 ((0x1a22 << 2) + 0xff000000)
+#define VIU_OSD1_BLK2_CFG_W3 ((0x1a26 << 2) + 0xff000000)
+#define VIU_OSD1_BLK3_CFG_W3 ((0x1a2a << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, v_end
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, v_start
+#define VIU_OSD1_BLK0_CFG_W4 ((0x1a13 << 2) + 0xff000000)
+#define VIU_OSD1_BLK1_CFG_W4 ((0x1a14 << 2) + 0xff000000)
+#define VIU_OSD1_BLK2_CFG_W4 ((0x1a15 << 2) + 0xff000000)
+#define VIU_OSD1_BLK3_CFG_W4 ((0x1a16 << 2) + 0xff000000)
+// Bit 31 RW, burst_len_sel[2] of [2:0]
+// Bit 30 RW, byte_swap: In addition to endian control, further define
+// whether to swap upper and lower byte within a 16-bit mem word.
+// 0=No swap; 1=Swap data[15:0] to be {data[7:0], data[15:8]}
+// Bit 29 RW, div_swap : swap the 2 64bits words in 128 bit word
+// Bit 28:24 RW, fifo_lim : when osd fifo is small than the fifo_lim*16, closed the rq port of osd_rd_mif
+// Bit 23:22 RW, fifo_ctrl: 00 : for 1 word in 1 burst , 01 : for 2words in 1burst, 10: for 4words in 1burst, 11: reserved
+// Bit 21:20 R, fifo_st. 0=IDLE, 1=FILL, 2=ABORT
+// Bit 19 R, fifo_overflow
+// Bit 18:12 RW, fifo_depth_val, max value=64: set actual fifo depth to fifo_depth_val*8.
+// Bit 11:10 RW, burst_len_sel[1:0] of [2:0]. 0=24(default), 1=32, 2=48, 3=64, 4=96, 5=128.
+// Bit 9: 5 RW, hold_fifo_lines[4:0]
+// Bit 4 RW, clear_err: one pulse to clear fifo_overflow
+// Bit 3 RW, fifo_sync_rst
+// Bit 2: 1 RW, endian
+// Bit 0 RW, urgent
+#define VIU_OSD1_FIFO_CTRL_STAT ((0x1a2b << 2) + 0xff000000)
+// Bit 31:24 R, Y or R
+// Bit 23:16 R, Cb or G
+// Bit 15: 8 R, Cr or B
+// Bit 7: 0 R, Output Alpha[8:1]
+#define VIU_OSD1_TEST_RDDATA ((0x1a2c << 2) + 0xff000000)
+// Bit 15 RW, prot_en: 1=Borrow PROT's FIFO storage, either for rotate or non-rotate.
+// Bit 12: 0 RW, effective FIFO size when prot_en=1.
+#define VIU_OSD1_PROT_CTRL ((0x1a2e << 2) + 0xff000000)
+//Bit 7, highlight_en
+//Bit 6 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix
+//Bit 5:4 probe_sel, 00: select matrix 0, 01: select matrix 1, otherwise select nothing
+//Bit 3:2, matrix coef idx selection, 00: select mat0, 01: select mat1, otherwise slect nothing
+//Bit 1 mat1 conversion matrix enable
+//Bit 0 mat0 conversion matrix enable
+#define VIU_OSD1_MATRIX_CTRL ((0x1a90 << 2) + 0xff000000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define VIU_OSD1_MATRIX_COEF00_01 ((0x1a91 << 2) + 0xff000000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define VIU_OSD1_MATRIX_COEF02_10 ((0x1a92 << 2) + 0xff000000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define VIU_OSD1_MATRIX_COEF11_12 ((0x1a93 << 2) + 0xff000000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define VIU_OSD1_MATRIX_COEF20_21 ((0x1a94 << 2) + 0xff000000)
+//Bit 31:30 mat_clmod
+//Bit 18:16 mat_convrs
+//Bit 12:0 mat_coef42
+#define VIU_OSD1_MATRIX_COLMOD_COEF42 ((0x1a95 << 2) + 0xff000000)
+//Bit 26:16 offset0
+//Bit 10:0 offset1
+#define VIU_OSD1_MATRIX_OFFSET0_1 ((0x1a96 << 2) + 0xff000000)
+//Bit 10:0 offset2
+#define VIU_OSD1_MATRIX_OFFSET2 ((0x1a97 << 2) + 0xff000000)
+//Bit 26:16 pre_offset0
+//Bit 10:0 pre_offset1
+#define VIU_OSD1_MATRIX_PRE_OFFSET0_1 ((0x1a98 << 2) + 0xff000000)
+//Bit 10:0 pre_offset2
+#define VIU_OSD1_MATRIX_PRE_OFFSET2 ((0x1a99 << 2) + 0xff000000)
+//Read only
+//Bit 29:20 component 0
+//Bit 19:10 component 1
+//Bit 9:0 component 2
+#define VIU_OSD1_MATRIX_PROBE_COLOR ((0x1a9a << 2) + 0xff000000)
+//Bit 23:16 component 0
+//Bit 15:8 component 1
+//Bit 7:0 component 2
+#define VIU_OSD1_MATRIX_HL_COLOR ((0x1a9b << 2) + 0xff000000)
+//28:16 probe x, postion
+//12:0 probe y, position
+#define VIU_OSD1_MATRIX_PROBE_POS ((0x1a9c << 2) + 0xff000000)
+//Bit 28:16 coef22
+//Bit 12:0 coef30
+#define VIU_OSD1_MATRIX_COEF22_30 ((0x1a9d << 2) + 0xff000000)
+//Bit 28:16 coef31
+//Bit 12:0 coef32
+#define VIU_OSD1_MATRIX_COEF31_32 ((0x1a9e << 2) + 0xff000000)
+//Bit 28:16 coef40
+//Bit 12:0 coef41
+#define VIU_OSD1_MATRIX_COEF40_41 ((0x1a9f << 2) + 0xff000000)
+//Bit 31:27 for all [31] for all eotf enable,[30] for matrix3x3 enable, [29:27] for eotf_ch0~3
+//Bit 17:6 for clock gating
+//Bit 5:4 pscale_mode ch2
+//Bit 3:2 pscale_mode ch1
+//Bit 1:0 pscale_mode ch0
+#define VIU_OSD1_EOTF_CTL ((0x1ad4 << 2) + 0xff000000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define VIU_OSD1_EOTF_COEF00_01 ((0x1ad5 << 2) + 0xff000000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define VIU_OSD1_EOTF_COEF02_10 ((0x1ad6 << 2) + 0xff000000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define VIU_OSD1_EOTF_COEF11_12 ((0x1ad7 << 2) + 0xff000000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define VIU_OSD1_EOTF_COEF20_21 ((0x1ad8 << 2) + 0xff000000)
+//Bit 28:16 coef22
+//Bit 2:0 coef_rs
+#define VIU_OSD1_EOTF_COEF22_RS ((0x1ad9 << 2) + 0xff000000)
+#define VIU_OSD1_EOTF_LUT_ADDR_PORT ((0x1ada << 2) + 0xff000000)
+#define VIU_OSD1_EOTF_LUT_DATA_PORT ((0x1adb << 2) + 0xff000000)
+//Bit 31:29 for OETF ch0~ch2
+//Bit 21:12 for clock gating
+//Bit 11:8 for oetf_scl_ch2
+//Bit 7:4 for oetf_scl_ch1
+//Bit 3:0 for oetf_scl_ch0
+#define VIU_OSD1_OETF_CTL ((0x1adc << 2) + 0xff000000)
+#define VIU_OSD1_OETF_LUT_ADDR_PORT ((0x1add << 2) + 0xff000000)
+#define VIU_OSD1_OETF_LUT_DATA_PORT ((0x1ade << 2) + 0xff000000)
+#define VIU_OSD1_OETF_3X3_OFST_0 ((0x1aa0 << 2) + 0xff000000)
+#define VIU_OSD1_OETF_3X3_OFST_1 ((0x1aa1 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// OSD2 registers
+//------------------------------------------------------------------------------
+// Bit 31 Reserved
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// 0=use gated clock for low power.
+// Bit 29 R, test_rd_dsr
+// Bit 28 R, osd_done
+// Bit 27:24 R, osd_blk_mode
+// Bit 23:22 R, osd_blk_ptr
+// Bit 21 R, osd_enable
+//
+// Bit 20:12 RW, global_alpha
+// Bit 11 RW, test_rd_en
+// Bit 10 RW, hl2_en
+// Bit 9 RW, hl1_en
+// Bit 8: 5 RW, ctrl_mtch_y
+// Bit 4 RW, ctrl_422to444
+// Bit 3: 0 RW, osd_blk_enable. Bit 0 to enable block 0: 1=enable, 0=disable;
+// Bit 1 to enable block 1, and so on.
+#define VIU_OSD2_CTRL_STAT ((0x1a30 << 2) + 0xff000000)
+// Bit 31:26 Reserved
+// Bit 25:16 R, fifo_count
+// Bit 15 Reserved
+// Bit 14 RW, replaced_alpha_en
+// Bit 13: 6 RW, replaced_alpha
+// Bit 5: 4 RW, hold_fifo_lines[6:5]
+// Bit 3 RW, rgb2yuv_full_range
+// Bit 2 RW, alpha_9b_mode
+// Bit 1 RW, reserved
+// Bit 0 RW, color_expand_mode
+#define VIU_OSD2_CTRL_STAT2 ((0x1a4d << 2) + 0xff000000)
+// Bit 31: 9 Reserved
+// Bit 8 RW, 0 = Write LUT, 1 = Read LUT
+// Bit 7: 0 RW, lut_addr
+#define VIU_OSD2_COLOR_ADDR ((0x1a31 << 2) + 0xff000000)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define VIU_OSD2_COLOR ((0x1a32 << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, hl[1-2]_h/v_start
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, hl[1-2]_h/v_end
+#define VIU_OSD2_HL1_H_START_END ((0x1a33 << 2) + 0xff000000)
+#define VIU_OSD2_HL1_V_START_END ((0x1a34 << 2) + 0xff000000)
+#define VIU_OSD2_HL2_H_START_END ((0x1a35 << 2) + 0xff000000)
+#define VIU_OSD2_HL2_V_START_END ((0x1a36 << 2) + 0xff000000)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define VIU_OSD2_TCOLOR_AG0 ((0x1a37 << 2) + 0xff000000)
+#define VIU_OSD2_TCOLOR_AG1 ((0x1a38 << 2) + 0xff000000)
+#define VIU_OSD2_TCOLOR_AG2 ((0x1a39 << 2) + 0xff000000)
+#define VIU_OSD2_TCOLOR_AG3 ((0x1a3a << 2) + 0xff000000)
+// Bit 31:24 Reserved
+// Bit 23:16 RW, tbl_addr
+// Bit 15 RW, little_endian: 0=big endian, 1=little endian
+// Bit 14 RW, rpt_y
+// Bit 13:12 RW, interp_ctrl. 0x=No interpolation; 10=Interpolate with previous
+// pixel; 11=Interpolate with the average value
+// between previous and next pixel.
+// Bit 11: 8 RW, osd_blk_mode
+// Bit 7 RW, rgb_en
+// Bit 6 RW, tc_alpha_en
+// Bit 5: 2 RW, color_matrix
+// Bit 1 RW, interlace_en
+// Bit 0 RW, interlace_sel_odd
+#define VIU_OSD2_BLK0_CFG_W0 ((0x1a3b << 2) + 0xff000000)
+#define VIU_OSD2_BLK1_CFG_W0 ((0x1a3f << 2) + 0xff000000)
+#define VIU_OSD2_BLK2_CFG_W0 ((0x1a43 << 2) + 0xff000000)
+#define VIU_OSD2_BLK3_CFG_W0 ((0x1a47 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, x_end
+// Bit 15:13 Reserved
+// Bit 12: 0 RW, x_start
+#define VIU_OSD2_BLK0_CFG_W1 ((0x1a3c << 2) + 0xff000000)
+#define VIU_OSD2_BLK1_CFG_W1 ((0x1a40 << 2) + 0xff000000)
+#define VIU_OSD2_BLK2_CFG_W1 ((0x1a44 << 2) + 0xff000000)
+#define VIU_OSD2_BLK3_CFG_W1 ((0x1a48 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, y_end
+// Bit 15:13 Reserved
+// Bit 12: 0 RW, y_start
+#define VIU_OSD2_BLK0_CFG_W2 ((0x1a3d << 2) + 0xff000000)
+#define VIU_OSD2_BLK1_CFG_W2 ((0x1a41 << 2) + 0xff000000)
+#define VIU_OSD2_BLK2_CFG_W2 ((0x1a45 << 2) + 0xff000000)
+#define VIU_OSD2_BLK3_CFG_W2 ((0x1a49 << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, h_end
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, h_start
+#define VIU_OSD2_BLK0_CFG_W3 ((0x1a3e << 2) + 0xff000000)
+#define VIU_OSD2_BLK1_CFG_W3 ((0x1a42 << 2) + 0xff000000)
+#define VIU_OSD2_BLK2_CFG_W3 ((0x1a46 << 2) + 0xff000000)
+#define VIU_OSD2_BLK3_CFG_W3 ((0x1a4a << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, v_end
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, v_start
+#define VIU_OSD2_BLK0_CFG_W4 ((0x1a64 << 2) + 0xff000000)
+#define VIU_OSD2_BLK1_CFG_W4 ((0x1a65 << 2) + 0xff000000)
+#define VIU_OSD2_BLK2_CFG_W4 ((0x1a66 << 2) + 0xff000000)
+#define VIU_OSD2_BLK3_CFG_W4 ((0x1a67 << 2) + 0xff000000)
+// Bit 31 RW, burst_len_sel[2] of [2:0]
+// Bit 30 RW, byte_swap: In addition to endian control, further define
+// whether to swap upper and lower byte within a 16-bit mem word.
+// 0=No swap; 1=Swap data[15:0] to be {data[7:0], data[15:8]}
+// Bit 29 RW, div_swap : swap the 2 64bits words in 128 bit word
+// Bit 28:24 RW, fifo_lim : when osd fifo is small than the fifo_lim*16, closed the rq port of osd_rd_mif
+// Bit 23:22 RW, fifo_ctrl: 00 : for 1 word in 1 burst , 01 : for 2words in 1burst, 10: for 4words in 1burst, 11: reserved
+// Bit 21:20 R, fifo_st. 0=IDLE, 1=FILL, 2=ABORT
+// Bit 19 R, fifo_overflow
+//
+// Bit 18:12 RW, fifo_depth_val, max value=64: set actual fifo depth to fifo_depth_val*8.
+// Bit 11:10 RW, burst_len_sel[1:0] of [2:0]. 0=24(default), 1=32, 2=48, 3=64, 4=96, 5=128.
+// Bit 9: 5 RW, hold_fifo_lines[4:0]
+// Bit 4 RW, clear_err: one pulse to clear fifo_overflow
+// Bit 3 RW, fifo_sync_rst
+// Bit 2: 1 RW, endian
+// Bit 0 RW, urgent
+#define VIU_OSD2_FIFO_CTRL_STAT ((0x1a4b << 2) + 0xff000000)
+// Bit 31:24 R, Y or R
+// Bit 23:16 R, Cb or G
+// Bit 15: 8 R, Cr or B
+// Bit 7: 0 R, Output Alpha[8:1]
+#define VIU_OSD2_TEST_RDDATA ((0x1a4c << 2) + 0xff000000)
+// Bit 15 RW, prot_en: 1=Borrow PROT's FIFO storage, either for rotate or non-rotate.
+// Bit 12: 0 RW, effective FIFO size when prot_en=1.
+#define VIU_OSD2_PROT_CTRL ((0x1a4e << 2) + 0xff000000)
+// //todo add comment
+#define LDIM_STTS_GCLK_CTRL0 ((0x1ac0 << 2) + 0xff000000)
+#define LDIM_STTS_CTRL0 ((0x1ac1 << 2) + 0xff000000)
+#define LDIM_STTS_WIDTHM1_HEIGHTM1 ((0x1ac2 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_COEF00_01 ((0x1ac3 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_COEF02_10 ((0x1ac4 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_COEF11_12 ((0x1ac5 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_COEF20_21 ((0x1ac6 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_COEF22 ((0x1ac7 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_OFFSET0_1 ((0x1ac8 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_OFFSET2 ((0x1ac9 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_PRE_OFFSET0_1 ((0x1aca << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_PRE_OFFSET2 ((0x1acb << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_HL_COLOR ((0x1acc << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_PROBE_POS ((0x1acd << 2) + 0xff000000)
+//
+// //read only
+#define LDIM_STTS_MATRIX_PROBE_COLOR ((0x1ace << 2) + 0xff000000)
+//
+// //Bit 31, local dimming statistic enable
+// //Bit 29, 1: output region histogram 16bit 0:output region histogram 20bit
+// //Bit 28, eol enable
+// //Bit 27:25, vertical line overlap number for max finding
+// //Bit 24:22, horizontal pixel overlap number, 0: 17 pix, 1: 9 pix, 2: 5 pix, 3: 3 pix, 4: 0 pix
+// //Bit 20, 1,2,1 low pass filter enable before max/hist statistic
+// //Bit 19:16, region H/V position index, refer to VDIN_LDIM_STTS_HIST_SET_REGION
+// //Bit 15:14, 1: region read index auto increase per block read finished to VDIN_LDIM_STTS_HIST_READ_REGION
+// // 2: region read index auto increase per read finished to VDIN_LDIM_STTS_HIST_READ_REGION
+// // 0/3: disable read index self increase
+// //Bit 13:8, region read sub index, which mux the hist & max-finding result to cbus port, refer to LDIM_STTS_HIST_READ_REGION
+// //Bit 6:0, region read index
+#define LDIM_STTS_HIST_REGION_IDX ((0x1ad0 << 2) + 0xff000000)
+//Bit 28:0, if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h0: read/write hvstart0
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h1: read/write hend01
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h2: read/write vend01
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h3: read/write hend23
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h4: read/write vend23
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h5: read/write hend45
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h6: read/write vend45
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'd7: read/write hend67
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h8: read/write vend67
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h9: read/write hend89
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'ha: read/write vend89
+// //hvstart0, Bit 28:16 row0 vstart, Bit 12:0 col0 hstart
+// //hend01, Bit 28:16 col1 hend, Bit 12:0 col0 hend
+// //vend01, Bit 28:16 row1 vend, Bit 12:0 row0 vend
+// //hend23, Bit 28:16 col3 hend, Bit 12:0 col2 hend
+// //vend23, Bit 28:16 row3 vend, Bit 12:0 row2 vend
+// //hend45, Bit 28:16 col5 hend, Bit 12:0 col4 hend
+// //vend45, Bit 28:16 row5 vend, Bit 12:0 row4 vend
+// //hend67, Bit 28:16 col7 hend, Bit 12:0 col6 hend
+// //vend67, Bit 28:16 row7 vend, Bit 12:0 row6 vend
+// //hend89, Bit 28:16 col9 hend, Bit 12:0 col8 hend
+// //vend89, Bit 28:16 row9 vend, Bit 12:0 row8 vend
+#define LDIM_STTS_HIST_SET_REGION ((0x1ad1 << 2) + 0xff000000)
+//
+// //if LDIM_STTS_HIST_REGION_IDX[29] == 0, that is output hist with 20bit data.
+// //if LDIM_STTS_HIST_REGION_IDX[21] == 0, that is output 16hist bins in comp 0.
+// //output sequence as rd_sub_idx from 0~47: {max_comp2, comp0_hist0}, {max_comp1, comp0_hist1}, {max_comp0, comp0_hist2},
+// // comp0_hist3 ... comp2_hist16
+// //if LDIM_STTS_HIST_REGION_IDX[29] == 1, that is output hist with 16bit data.
+// //if LDIM_STTS_HIST_REGION_IDX[21] == 0, that is output 16hist bins in comp 0.
+// //output sequence as rd_sub_idx from 0~47: {max_comp2, max_comp1, max_comp0}, comp0_hist0, comp0_hist1, comp0_hist2
+// // comp0_hist3 ... comp2_hist16
+// //if LDIM_STTS_HIST_REGION_IDX[29] == 0, that is output hist with 20bit data.
+// //if LDIM_STTS_HIST_REGION_IDX[21] == 1, that is output 32hist bins in comp 0.
+// //output sequence as rd_sub_idx from 0~47: {max_comp2, max_comp1, max_comp0}, comp0_hist0, comp0_hist1, comp0_hist2
+// // comp0_hist3 ...comp0_hist31 ... comp1_hist16
+//
+#define LDIM_STTS_HIST_READ_REGION ((0x1ad2 << 2) + 0xff000000)
+#define LDIM_STTS_HIST_START_RD_REGION ((0x1ad3 << 2) + 0xff000000)
+#define LDIM_STTS_PCTL_TH ((0x1aaf << 2) + 0xff000000)
+// //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di if1 chroma path
+// //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di if1 luma path
+// `define DI_IF1_URGENT_CTRL 8'ha3
+// //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path
+// //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path
+// `define DI_INP_URGENT_CTRL 8'ha4
+// //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di mem chroma path
+// //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di mem luma path
+// `define DI_MEM_URGENT_CTRL 8'ha5
+// //bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di chan2 chroma path
+// //bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di chan2 luma path
+// `define DI_CHAN2_URGENT_CTRL 8'ha6
+#define OSD_BLENDO_H_START_END ((0x1aa9 << 2) + 0xff000000)
+//OSD blending output horizontal start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define OSD_BLENDO_V_START_END ((0x1aaa << 2) + 0xff000000)
+//OSD blending output vertical start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define OSD_BLEND_GEN_CTRL0 ((0x1aab << 2) + 0xff000000)
+//Bit 31:23 const_out_alpha
+//Bit 22:14 const_op_alpha
+//Bit 13 if true, OSD2 foreground otherwise OSD1 foreground
+//Bit 12 OSD BLENDing enable
+//Bit 9:8 alpha_op_sel 00: output alpha use osd1_alpha, 01: use osd2_alpha, else use const_out_alpha
+//Bit 5:4 color_op_sel 00: use osd1_alpha, 01: use osd2_alpha, else use const_op_alpha
+//Bit 1 OSD2 enable
+//Bit 0 OSD1 enable
+#define OSD_BLEND_GEN_CTRL1 ((0x1aac << 2) + 0xff000000)
+//Bit 31 osd1_alpha_premult, if true, osd1 alpha is premultipiled
+//Bit 30 osd2_alpha_premult, if true, osd2 alpha is premultipiled
+//Bit 23:16 osd blending hold lines
+//Bit 13:0 osd blending h_size
+#define OSD_BLEND_DUMMY_DATA ((0x1aad << 2) + 0xff000000)
+//Bit 29:20 Y/R
+//Bit 19:10 CB/G
+//Bit 9:0 Cr/B
+#define OSD_BLEND_CURRENT_XY ((0x1aae << 2) + 0xff000000)
+//Bit 28:16 current_x
+//Bit 12:0 current_y
+//Bit 7, highlight_en
+//Bit 6 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix
+//Bit 5:4 probe_sel, 00: select matrix 0, 01: select matrix 1, otherwise select nothing
+//Bit 3:2, matrix coef idx selection, 00: select mat0, 01: select mat1, otherwise slect nothing
+//Bit 1 mat1 conversion matrix enable
+//Bit 0 mat0 conversion matrix enable
+#define VIU_OSD2_MATRIX_CTRL ((0x1ab0 << 2) + 0xff000000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define VIU_OSD2_MATRIX_COEF00_01 ((0x1ab1 << 2) + 0xff000000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define VIU_OSD2_MATRIX_COEF02_10 ((0x1ab2 << 2) + 0xff000000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define VIU_OSD2_MATRIX_COEF11_12 ((0x1ab3 << 2) + 0xff000000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define VIU_OSD2_MATRIX_COEF20_21 ((0x1ab4 << 2) + 0xff000000)
+#define VIU_OSD2_MATRIX_COEF22 ((0x1ab5 << 2) + 0xff000000)
+//Bit 26:16 offset0
+//Bit 10:0 offset1
+#define VIU_OSD2_MATRIX_OFFSET0_1 ((0x1ab6 << 2) + 0xff000000)
+//Bit 10:0 offset2
+#define VIU_OSD2_MATRIX_OFFSET2 ((0x1ab7 << 2) + 0xff000000)
+//Bit 26:16 pre_offset0
+//Bit 10:0 pre_offset1
+#define VIU_OSD2_MATRIX_PRE_OFFSET0_1 ((0x1ab8 << 2) + 0xff000000)
+//Bit 10:0 pre_offset2
+#define VIU_OSD2_MATRIX_PRE_OFFSET2 ((0x1ab9 << 2) + 0xff000000)
+//Read only
+//Bit 29:20 component 0
+//Bit 19:10 component 1
+//Bit 9:0 component 2
+#define VIU_OSD2_MATRIX_PROBE_COLOR ((0x1aba << 2) + 0xff000000)
+//Bit 23:16 component 0
+//Bit 15:8 component 1
+//Bit 7:0 component 2
+#define VIU_OSD2_MATRIX_HL_COLOR ((0x1abb << 2) + 0xff000000)
+//28:16 probe x, postion
+//12:0 probe y, position
+#define VIU_OSD2_MATRIX_PROBE_POS ((0x1abc << 2) + 0xff000000)
+////add for OSD1/2 mali_unpack
+#define VIU_OSD1_MALI_UNPACK_CTRL ((0x1a2f << 2) + 0xff000000)
+//`define VIU_OSD1_MALI_UNPACK_CTRL 8'h4f //todo
+//`define VIU_OSD1_MALI_UNPACK_CTRL 8'haf //todo
+#define VIU_OSD2_MALI_UNPACK_CTRL ((0x1abd << 2) + 0xff000000)
+//`define VIU_OSD2_MATRIX_HL_COLOR 8'hbe
+//`define VIU_OSD2_MATRIX_PROBE_POS 8'hbf
+//can use 8'hdf 8'hcf
+#define VIU_OSD1_DIMM_CTRL ((0x1adf << 2) + 0xff000000)
+#define VIU_OSD2_DIMM_CTRL ((0x1acf << 2) + 0xff000000)
+#define VIU_GCLK_CTRL ((0x1a4f << 2) + 0xff000000)
+//the segment of afbc dec is 8'he0-8'hfe
+//`define AFBC_DEC_OFFSET 8'he0
+//
+// Reading file: afbc_dec_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+//// reg
+////===============================////
+#define AFBC_ENABLE ((0x1ae0 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:23, reg_gclk_ctrl_core unsigned, default = 0
+//Bit 22, reg_fmt_size_sw_mode unsigned, default = 0, 0:hw mode 1:sw mode for format size
+//Bit 21, reg_addr_link_en unsigned, default = 1, 1:enable
+//Bit 20, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb
+//Bit 19, reg_dos_uncomp_mode unsigned , default = 0
+//Bit 18:16, soft_rst unsigned , default = 4
+//Bit 15:14, reserved
+//Bit 13:12, ddr_blk_size unsigned , default = 1
+//Bit 11:9, cmd_blk_size unsigend , default = 3
+//Bit 8, dec_enable unsigned , default = 0
+//Bit 7:2, reserved
+//Bit 1, head_len_sel unsigned , default = 1
+//Bit 0, dec_frm_start unsigned , default = 0
+#define AFBC_MODE ((0x1ae1 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29, ddr_sz_mode uns, default = 0 , 0: fixed block ddr size 1 : unfixed block ddr size;
+//Bit 28, blk_mem_mode uns, default = 0 , 0: fixed 16x128 size; 1 : fixed 12x128 size
+//Bit 27:26, rev_mode uns, default = 0 , reverse mode
+//Bit 25:24, mif_urgent uns, default = 3 , info mif and data mif urgent
+//Bit 23, reserved
+//Bit 22:16, hold_line_num uns, default = 4 ,
+//Bit 15:14, burst_len uns, default = 2, 0: burst1 1:burst2 2:burst4
+//Bit 13:8, compbits_yuv uns, default = 0 ,
+// bit 1:0,: y component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+// bit 3:2,: u component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+// bit 5:4,: v component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+//Bit 7:6, vert_skip_y uns, default = 0 , luma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 5:4, horz_skip_y uns, default = 0 , luma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 3:2, vert_skip_uv uns, default = 0 , chroma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 1:0, horz_skip_uv uns, default = 0 , chroma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+#define AFBC_SIZE_IN ((0x1ae2 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hsize_in uns, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_in uns, default = 1080 , pic vert size in unit: pixel
+#define AFBC_DEC_DEF_COLOR ((0x1ae3 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:20, def_color_y uns, default = 255, afbc dec y default setting value
+//Bit 19:10, def_color_u uns, default = 128, afbc dec u default setting value
+//Bit 9: 0, def_color_v uns, default = 128, afbc dec v default setting value
+#define AFBC_CONV_CTRL ((0x1ae4 << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13:12, fmt_mode uns, default = 2, 0:yuv444 1:yuv422 2:yuv420
+//Bit 11: 0, conv_lbuf_len uns, default = 256, unit=16 pixel need to set = 2^n
+#define AFBC_LBUF_DEPTH ((0x1ae5 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, dec_lbuf_depth uns, default = 128; // unit= 8 pixel
+//Bit 15:12, reserved
+//Bit 11:0, mif_lbuf_depth uns, default = 128;
+#define AFBC_HEAD_BADDR ((0x1ae6 << 2) + 0xff000000)
+//Bit 31:0, mif_info_baddr uns, default = 32'h0;
+#define AFBC_BODY_BADDR ((0x1ae7 << 2) + 0xff000000)
+//Bit 31:0, mif_data_baddr uns, default = 32'h00010000;
+#define AFBC_SIZE_OUT ((0x1ae8 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, hsize_out uns, default = 1920 ; // unit: 1 pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_out uns, default = 1080 ; // unit: 1 pixel
+#define AFBC_OUT_YSCOPE ((0x1ae9 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, out_vert_bgn uns, default = 0 ; // unit: 1 pixel
+//Bit 15:13, reserved
+//Bit 12:0, out_vert_end uns, default = 1079 ; // unit: 1 pixel
+#define AFBC_STAT ((0x1aea << 2) + 0xff000000)
+//Bit 31:0, ro_dbg_top_info uns,
+#define AFBC_VD_CFMT_CTRL ((0x1aeb << 2) + 0xff000000)
+//Bit 31 cfmt_gclk_bit_dis uns, default = 0 ; // it true, disable clock, otherwise enable clock
+//Bit 30 cfmt_soft_rst_bit uns, default = 0 ; // soft rst bit
+//Bit 29 reserved
+//Bit 28 chfmt_rpt_pix uns, default = 0 ; // if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
+//Bit 27:24 chfmt_ini_phase uns, default = 0 ; // horizontal formatter initial phase
+//Bit 23 chfmt_rpt_p0_en uns, default = 0 ; // horizontal formatter repeat pixel 0 enable
+//Bit 22:21 chfmt_yc_ratio uns, default = 0 ; // horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
+//Bit 20 chfmt_en uns, default = 0 ; // horizontal formatter enable
+//Bit 19 cvfmt_phase0_always_en uns, default = 0 ; //if true, always use phase0 while vertical formater, meaning always
+// repeat data, no interpolation
+//Bit 18 cvfmt_rpt_last_dis uns, default = 0 ; //if true, disable vertical formatter chroma repeat last line
+//Bit 17 cvfmt_phase0_nrpt_en uns, default = 0 ; //veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable
+//Bit 16 cvfmt_rpt_line0_en uns, default = 0 ; //veritcal formatter repeat line 0 enable
+//Bit 15:12 cvfmt_skip_line_num uns, default = 0 ; //vertical formatter skip line num at the beginning
+//Bit 11:8 cvfmt_ini_phase uns, default = 0 ; //vertical formatter initial phase
+//Bit 7:1 cvfmt_phase_step uns, default = 0 ; //vertical formatter phase step (3.4)
+//Bit 0 cvfmt_en uns, default = 0 ; //vertical formatter enable
+#define AFBC_VD_CFMT_W ((0x1aec << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 chfmt_w uns, default = 0 ;horizontal formatter width
+//Bit 15:13 reserved
+//Bit 12:0 cvfmt_w uns, default = 0 ;vertical formatter width
+#define AFBC_MIF_HOR_SCOPE ((0x1aed << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, mif_blk_bgn_h uns, default = 0 ; // unit: 32 pixel/block hor
+//Bit 15:10, reserved
+//Bit 9: 0, mif_blk_end_h uns, default = 59 ; // unit: 32 pixel/block hor
+#define AFBC_MIF_VER_SCOPE ((0x1aee << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, mif_blk_bgn_v uns, default = 0 ; // unit: 32 pixel/block ver
+//Bit 15:12, reserved
+//Bit 11: 0, mif_blk_end_v uns, default = 269; // unit: 32 pixel/block ver
+#define AFBC_PIXEL_HOR_SCOPE ((0x1aef << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, dec_pixel_bgn_h uns, default = 0 ; // unit: pixel
+//Bit 15:13, reserved
+//Bit 12: 0, dec_pixel_end_h uns, default = 1919 ; // unit: pixel
+#define AFBC_PIXEL_VER_SCOPE ((0x1af0 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, dec_pixel_bgn_v uns, default = 0 ; // unit: pixel
+//Bit 15:13, reserved
+//Bit 12: 0, dec_pixel_end_v uns, default = 1079 ; // unit: pixel
+#define AFBC_VD_CFMT_H ((0x1af1 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12:0 cfmt_h uns, default = 142 ; //vertical formatter height
+#define AFBCDEC_IQUANT_ENABLE ((0x1af2 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_quant_expand_en_1 //unsigned, RW, enable for quantization value expansion
+//Bit 10 reg_quant_expand_en_0 //unsigned, RW, enable for quantization value expansion
+//Bit 9: 8 reg_bcleav_ofst //signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1;
+//Bit 7: 5 reserved
+//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy
+//Bit 3: 1 reserved
+//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy
+#define AFBCDEC_IQUANT_LUT_1 ((0x1af3 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDEC_IQUANT_LUT_2 ((0x1af4 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDEC_IQUANT_LUT_3 ((0x1af5 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDEC_IQUANT_LUT_4 ((0x1af6 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: afbc_dec_regs.h
+//
+//
+// Closing file: vregs_clk2.h
+//
+//
+// Reading file: venc_regs.h
+//
+//===========================================================================
+// Video Interface Registers 0xa00 - 0xbff
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VENC_VCBUS_BASE = 0x1b
+// -----------------------------------------------
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 0 -- vfifo2vd_en
+#define ENCP_VFIFO2VD_CTL ((0x1b58 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCP_VFIFO2VD_PIXEL_START ((0x1b59 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCP_VFIFO2VD_PIXEL_END ((0x1b5a << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCP_VFIFO2VD_LINE_TOP_START ((0x1b5b << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCP_VFIFO2VD_LINE_TOP_END ((0x1b5c << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCP_VFIFO2VD_LINE_BOT_START ((0x1b5d << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCP_VFIFO2VD_LINE_BOT_END ((0x1b5e << 2) + 0xff000000)
+// Route the hsync and vsync signals round the chip. There are three
+// sources and users of these signals: VIU, internal video encoder, and
+// the pins on the chip. Some muxing is still being done in the VIU. It
+// was not moved to the venc module so that the same exact VIU code could
+// be used both in Twister and Twister2000.
+// Bit 2: venc_sync_source (1=>pins, 0=>viu)
+// Bit 1: viu_sync_source (1=>pins, 0=>venc)
+// Bit 0: vpins_sync_source (1=>venc, 0=>viu)
+#define VENC_SYNC_ROUTE ((0x1b60 << 2) + 0xff000000)
+ // encoder address space is assigned
+ // to the video encoder interface status
+ // register
+#define VENC_VIDEO_EXSRC ((0x1b61 << 2) + 0xff000000)
+#define VENC_DVI_SETTING ((0x1b62 << 2) + 0xff000000)
+#define VENC_C656_CTRL ((0x1b63 << 2) + 0xff000000)
+#define VENC_UPSAMPLE_CTRL0 ((0x1b64 << 2) + 0xff000000)
+#define VENC_UPSAMPLE_CTRL1 ((0x1b65 << 2) + 0xff000000)
+#define VENC_UPSAMPLE_CTRL2 ((0x1b66 << 2) + 0xff000000)
+// Invert control for tcon output
+// bit[15:14] -- vsync, hsync,
+// bit[13:0] -- oev3, oev2, cpv2, cph3, cph2, cph1, oeh, vcom, stv2, stv1, cpv1, oev1, sth1, sth2
+#define TCON_INVERT_CTL ((0x1b67 << 2) + 0xff000000)
+#define VENC_VIDEO_PROG_MODE ((0x1b68 << 2) + 0xff000000)
+//---- Venc pixel/line info
+#define VENC_ENCI_LINE ((0x1b69 << 2) + 0xff000000)
+#define VENC_ENCI_PIXEL ((0x1b6a << 2) + 0xff000000)
+#define VENC_ENCP_LINE ((0x1b6b << 2) + 0xff000000)
+#define VENC_ENCP_PIXEL ((0x1b6c << 2) + 0xff000000)
+//---- Status
+#define VENC_STATA ((0x1b6d << 2) + 0xff000000)
+//---- Interrupt setting
+#define VENC_INTCTRL ((0x1b6e << 2) + 0xff000000)
+#define VENC_INTFLAG ((0x1b6f << 2) + 0xff000000)
+//--------- Video test configuration
+#define VENC_VIDEO_TST_EN ((0x1b70 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_MDSEL ((0x1b71 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_Y ((0x1b72 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_CB ((0x1b73 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_CR ((0x1b74 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_CLRBAR_STRT ((0x1b75 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_CLRBAR_WIDTH ((0x1b76 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_VDCNT_STSET ((0x1b77 << 2) + 0xff000000)
+//----- Video dac setting
+#define VENC_VDAC_DACSEL0 ((0x1b78 << 2) + 0xff000000)
+#define VENC_VDAC_DACSEL1 ((0x1b79 << 2) + 0xff000000)
+#define VENC_VDAC_DACSEL2 ((0x1b7a << 2) + 0xff000000)
+#define VENC_VDAC_DACSEL3 ((0x1b7b << 2) + 0xff000000)
+#define VENC_VDAC_DACSEL4 ((0x1b7c << 2) + 0xff000000)
+#define VENC_VDAC_DACSEL5 ((0x1b7d << 2) + 0xff000000)
+#define VENC_VDAC_SETTING ((0x1b7e << 2) + 0xff000000)
+#define VENC_VDAC_TST_VAL ((0x1b7f << 2) + 0xff000000)
+#define VENC_VDAC_DAC0_GAINCTRL ((0x1bf0 << 2) + 0xff000000)
+#define VENC_VDAC_DAC0_OFFSET ((0x1bf1 << 2) + 0xff000000)
+#define VENC_VDAC_DAC1_GAINCTRL ((0x1bf2 << 2) + 0xff000000)
+#define VENC_VDAC_DAC1_OFFSET ((0x1bf3 << 2) + 0xff000000)
+#define VENC_VDAC_DAC2_GAINCTRL ((0x1bf4 << 2) + 0xff000000)
+#define VENC_VDAC_DAC2_OFFSET ((0x1bf5 << 2) + 0xff000000)
+#define VENC_VDAC_DAC3_GAINCTRL ((0x1bf6 << 2) + 0xff000000)
+#define VENC_VDAC_DAC3_OFFSET ((0x1bf7 << 2) + 0xff000000)
+#define VENC_VDAC_DAC4_GAINCTRL ((0x1bf8 << 2) + 0xff000000)
+#define VENC_VDAC_DAC4_OFFSET ((0x1bf9 << 2) + 0xff000000)
+#define VENC_VDAC_DAC5_GAINCTRL ((0x1bfa << 2) + 0xff000000)
+#define VENC_VDAC_DAC5_OFFSET ((0x1bfb << 2) + 0xff000000)
+#define VENC_VDAC_FIFO_CTRL ((0x1bfc << 2) + 0xff000000)
+#define ENCL_TCON_INVERT_CTL ((0x1bfd << 2) + 0xff000000)
+//
+// Closing file: venc_regs.h
+//
+//
+// Reading file: enc480p_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+// Video Encoder 480p Registers 0xb80 - 0xbef
+//===========================================================================
+//-------- Video basic setting
+#define ENCP_VIDEO_EN ((0x1b80 << 2) + 0xff000000)
+#define ENCP_VIDEO_SYNC_MODE ((0x1b81 << 2) + 0xff000000)
+#define ENCP_MACV_EN ((0x1b82 << 2) + 0xff000000)
+#define ENCP_VIDEO_Y_SCL ((0x1b83 << 2) + 0xff000000)
+#define ENCP_VIDEO_PB_SCL ((0x1b84 << 2) + 0xff000000)
+#define ENCP_VIDEO_PR_SCL ((0x1b85 << 2) + 0xff000000)
+#define ENCP_VIDEO_SYNC_SCL ((0x1b86 << 2) + 0xff000000)
+#define ENCP_VIDEO_MACV_SCL ((0x1b87 << 2) + 0xff000000)
+#define ENCP_VIDEO_Y_OFFST ((0x1b88 << 2) + 0xff000000)
+#define ENCP_VIDEO_PB_OFFST ((0x1b89 << 2) + 0xff000000)
+#define ENCP_VIDEO_PR_OFFST ((0x1b8a << 2) + 0xff000000)
+#define ENCP_VIDEO_SYNC_OFFST ((0x1b8b << 2) + 0xff000000)
+#define ENCP_VIDEO_MACV_OFFST ((0x1b8c << 2) + 0xff000000)
+//----- Video mode
+#define ENCP_VIDEO_MODE ((0x1b8d << 2) + 0xff000000)
+#define ENCP_VIDEO_MODE_ADV ((0x1b8e << 2) + 0xff000000)
+//--------------- Debug pins
+#define ENCP_DBG_PX_RST ((0x1b90 << 2) + 0xff000000)
+#define ENCP_DBG_LN_RST ((0x1b91 << 2) + 0xff000000)
+#define ENCP_DBG_PX_INT ((0x1b92 << 2) + 0xff000000)
+#define ENCP_DBG_LN_INT ((0x1b93 << 2) + 0xff000000)
+//----------- Video Advanced setting
+#define ENCP_VIDEO_YFP1_HTIME ((0x1b94 << 2) + 0xff000000)
+#define ENCP_VIDEO_YFP2_HTIME ((0x1b95 << 2) + 0xff000000)
+#define ENCP_VIDEO_YC_DLY ((0x1b96 << 2) + 0xff000000)
+#define ENCP_VIDEO_MAX_PXCNT ((0x1b97 << 2) + 0xff000000)
+#define ENCP_VIDEO_HSPULS_BEGIN ((0x1b98 << 2) + 0xff000000)
+#define ENCP_VIDEO_HSPULS_END ((0x1b99 << 2) + 0xff000000)
+#define ENCP_VIDEO_HSPULS_SWITCH ((0x1b9a << 2) + 0xff000000)
+#define ENCP_VIDEO_VSPULS_BEGIN ((0x1b9b << 2) + 0xff000000)
+#define ENCP_VIDEO_VSPULS_END ((0x1b9c << 2) + 0xff000000)
+#define ENCP_VIDEO_VSPULS_BLINE ((0x1b9d << 2) + 0xff000000)
+#define ENCP_VIDEO_VSPULS_ELINE ((0x1b9e << 2) + 0xff000000)
+#define ENCP_VIDEO_EQPULS_BEGIN ((0x1b9f << 2) + 0xff000000)
+#define ENCP_VIDEO_EQPULS_END ((0x1ba0 << 2) + 0xff000000)
+#define ENCP_VIDEO_EQPULS_BLINE ((0x1ba1 << 2) + 0xff000000)
+#define ENCP_VIDEO_EQPULS_ELINE ((0x1ba2 << 2) + 0xff000000)
+#define ENCP_VIDEO_HAVON_END ((0x1ba3 << 2) + 0xff000000)
+#define ENCP_VIDEO_HAVON_BEGIN ((0x1ba4 << 2) + 0xff000000)
+#define ENCP_VIDEO_VAVON_ELINE ((0x1baf << 2) + 0xff000000)
+#define ENCP_VIDEO_VAVON_BLINE ((0x1ba6 << 2) + 0xff000000)
+#define ENCP_VIDEO_HSO_BEGIN ((0x1ba7 << 2) + 0xff000000)
+#define ENCP_VIDEO_HSO_END ((0x1ba8 << 2) + 0xff000000)
+#define ENCP_VIDEO_VSO_BEGIN ((0x1ba9 << 2) + 0xff000000)
+#define ENCP_VIDEO_VSO_END ((0x1baa << 2) + 0xff000000)
+#define ENCP_VIDEO_VSO_BLINE ((0x1bab << 2) + 0xff000000)
+#define ENCP_VIDEO_VSO_ELINE ((0x1bac << 2) + 0xff000000)
+#define ENCP_VIDEO_SYNC_WAVE_CURVE ((0x1bad << 2) + 0xff000000)
+#define ENCP_VIDEO_MAX_LNCNT ((0x1bae << 2) + 0xff000000)
+#define ENCP_VIDEO_SY_VAL ((0x1bb0 << 2) + 0xff000000)
+#define ENCP_VIDEO_SY2_VAL ((0x1bb1 << 2) + 0xff000000)
+#define ENCP_VIDEO_BLANKY_VAL ((0x1bb2 << 2) + 0xff000000)
+#define ENCP_VIDEO_BLANKPB_VAL ((0x1bb3 << 2) + 0xff000000)
+#define ENCP_VIDEO_BLANKPR_VAL ((0x1bb4 << 2) + 0xff000000)
+#define ENCP_VIDEO_HOFFST ((0x1bb5 << 2) + 0xff000000)
+#define ENCP_VIDEO_VOFFST ((0x1bb6 << 2) + 0xff000000)
+#define ENCP_VIDEO_RGB_CTRL ((0x1bb7 << 2) + 0xff000000)
+#define ENCP_VIDEO_FILT_CTRL ((0x1bb8 << 2) + 0xff000000)
+#define ENCP_VIDEO_OFLD_VPEQ_OFST ((0x1bb9 << 2) + 0xff000000)
+#define ENCP_VIDEO_OFLD_VOAV_OFST ((0x1bba << 2) + 0xff000000)
+#define ENCP_VIDEO_MATRIX_CB ((0x1bbb << 2) + 0xff000000)
+#define ENCP_VIDEO_MATRIX_CR ((0x1bbc << 2) + 0xff000000)
+#define ENCP_VIDEO_RGBIN_CTRL ((0x1bbd << 2) + 0xff000000)
+//------------------Macrovision advanced setting
+#define ENCP_MACV_BLANKY_VAL ((0x1bc0 << 2) + 0xff000000)
+#define ENCP_MACV_MAXY_VAL ((0x1bc1 << 2) + 0xff000000)
+#define ENCP_MACV_1ST_PSSYNC_STRT ((0x1bc2 << 2) + 0xff000000)
+#define ENCP_MACV_PSSYNC_STRT ((0x1bc3 << 2) + 0xff000000)
+#define ENCP_MACV_AGC_STRT ((0x1bc4 << 2) + 0xff000000)
+#define ENCP_MACV_AGC_END ((0x1bc5 << 2) + 0xff000000)
+#define ENCP_MACV_WAVE_END ((0x1bc6 << 2) + 0xff000000)
+#define ENCP_MACV_STRTLINE ((0x1bc7 << 2) + 0xff000000)
+#define ENCP_MACV_ENDLINE ((0x1bc8 << 2) + 0xff000000)
+#define ENCP_MACV_TS_CNT_MAX_L ((0x1bc9 << 2) + 0xff000000)
+#define ENCP_MACV_TS_CNT_MAX_H ((0x1bca << 2) + 0xff000000)
+#define ENCP_MACV_TIME_DOWN ((0x1bcb << 2) + 0xff000000)
+#define ENCP_MACV_TIME_LO ((0x1bcc << 2) + 0xff000000)
+#define ENCP_MACV_TIME_UP ((0x1bcd << 2) + 0xff000000)
+#define ENCP_MACV_TIME_RST ((0x1bce << 2) + 0xff000000)
+//---------------- VBI control -------------------
+#define ENCP_VBI_CTRL ((0x1bd0 << 2) + 0xff000000)
+#define ENCP_VBI_SETTING ((0x1bd1 << 2) + 0xff000000)
+#define ENCP_VBI_BEGIN ((0x1bd2 << 2) + 0xff000000)
+#define ENCP_VBI_WIDTH ((0x1bd3 << 2) + 0xff000000)
+#define ENCP_VBI_HVAL ((0x1bd4 << 2) + 0xff000000)
+#define ENCP_VBI_DATA0 ((0x1bd5 << 2) + 0xff000000)
+#define ENCP_VBI_DATA1 ((0x1bd6 << 2) + 0xff000000)
+//----------------C656 OUT Control------------- Grant
+#define C656_HS_ST ((0x1be0 << 2) + 0xff000000)
+#define C656_HS_ED ((0x1be1 << 2) + 0xff000000)
+#define C656_VS_LNST_E ((0x1be2 << 2) + 0xff000000)
+#define C656_VS_LNST_O ((0x1be3 << 2) + 0xff000000)
+#define C656_VS_LNED_E ((0x1be4 << 2) + 0xff000000)
+#define C656_VS_LNED_O ((0x1be5 << 2) + 0xff000000)
+#define C656_FS_LNST ((0x1be6 << 2) + 0xff000000)
+#define C656_FS_LNED ((0x1be7 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: enc480p_regs.h
+//
+//
+// Reading file: enci_regs.h
+//
+//===========================================================================
+// Video Interface Registers 0xb00 - 0xb57
+//===========================================================================
+#define ENCI_VIDEO_MODE ((0x1b00 << 2) + 0xff000000)
+#define ENCI_VIDEO_MODE_ADV ((0x1b01 << 2) + 0xff000000)
+#define ENCI_VIDEO_FSC_ADJ ((0x1b02 << 2) + 0xff000000)
+#define ENCI_VIDEO_BRIGHT ((0x1b03 << 2) + 0xff000000)
+#define ENCI_VIDEO_CONT ((0x1b04 << 2) + 0xff000000)
+#define ENCI_VIDEO_SAT ((0x1b05 << 2) + 0xff000000)
+#define ENCI_VIDEO_HUE ((0x1b06 << 2) + 0xff000000)
+#define ENCI_VIDEO_SCH ((0x1b07 << 2) + 0xff000000)
+#define ENCI_SYNC_MODE ((0x1b08 << 2) + 0xff000000)
+#define ENCI_SYNC_CTRL ((0x1b09 << 2) + 0xff000000)
+#define ENCI_SYNC_HSO_BEGIN ((0x1b0a << 2) + 0xff000000)
+#define ENCI_SYNC_HSO_END ((0x1b0b << 2) + 0xff000000)
+#define ENCI_SYNC_VSO_EVN ((0x1b0c << 2) + 0xff000000)
+#define ENCI_SYNC_VSO_ODD ((0x1b0d << 2) + 0xff000000)
+#define ENCI_SYNC_VSO_EVNLN ((0x1b0e << 2) + 0xff000000)
+#define ENCI_SYNC_VSO_ODDLN ((0x1b0f << 2) + 0xff000000)
+#define ENCI_SYNC_HOFFST ((0x1b10 << 2) + 0xff000000)
+#define ENCI_SYNC_VOFFST ((0x1b11 << 2) + 0xff000000)
+#define ENCI_SYNC_ADJ ((0x1b12 << 2) + 0xff000000)
+#define ENCI_RGB_SETTING ((0x1b13 << 2) + 0xff000000)
+//`define ENCI_CMPN_MATRIX_CB 8'h14
+//`define ENCI_CMPN_MATRIX_CR 8'h15
+#define ENCI_DE_H_BEGIN ((0x1b16 << 2) + 0xff000000)
+#define ENCI_DE_H_END ((0x1b17 << 2) + 0xff000000)
+#define ENCI_DE_V_BEGIN_EVEN ((0x1b18 << 2) + 0xff000000)
+#define ENCI_DE_V_END_EVEN ((0x1b19 << 2) + 0xff000000)
+#define ENCI_DE_V_BEGIN_ODD ((0x1b1a << 2) + 0xff000000)
+#define ENCI_DE_V_END_ODD ((0x1b1b << 2) + 0xff000000)
+#define ENCI_VBI_SETTING ((0x1b20 << 2) + 0xff000000)
+#define ENCI_VBI_CCDT_EVN ((0x1b21 << 2) + 0xff000000)
+#define ENCI_VBI_CCDT_ODD ((0x1b22 << 2) + 0xff000000)
+#define ENCI_VBI_CC525_LN ((0x1b23 << 2) + 0xff000000)
+#define ENCI_VBI_CC625_LN ((0x1b24 << 2) + 0xff000000)
+#define ENCI_VBI_WSSDT ((0x1b25 << 2) + 0xff000000)
+#define ENCI_VBI_WSS_LN ((0x1b26 << 2) + 0xff000000)
+#define ENCI_VBI_CGMSDT_L ((0x1b27 << 2) + 0xff000000)
+#define ENCI_VBI_CGMSDT_H ((0x1b28 << 2) + 0xff000000)
+#define ENCI_VBI_CGMS_LN ((0x1b29 << 2) + 0xff000000)
+#define ENCI_VBI_TTX_HTIME ((0x1b2a << 2) + 0xff000000)
+#define ENCI_VBI_TTX_LN ((0x1b2b << 2) + 0xff000000)
+#define ENCI_VBI_TTXDT0 ((0x1b2c << 2) + 0xff000000)
+#define ENCI_VBI_TTXDT1 ((0x1b2d << 2) + 0xff000000)
+#define ENCI_VBI_TTXDT2 ((0x1b2e << 2) + 0xff000000)
+#define ENCI_VBI_TTXDT3 ((0x1b2f << 2) + 0xff000000)
+#define ENCI_MACV_N0 ((0x1b30 << 2) + 0xff000000)
+#define ENCI_MACV_N1 ((0x1b31 << 2) + 0xff000000)
+#define ENCI_MACV_N2 ((0x1b32 << 2) + 0xff000000)
+#define ENCI_MACV_N3 ((0x1b33 << 2) + 0xff000000)
+#define ENCI_MACV_N4 ((0x1b34 << 2) + 0xff000000)
+#define ENCI_MACV_N5 ((0x1b35 << 2) + 0xff000000)
+#define ENCI_MACV_N6 ((0x1b36 << 2) + 0xff000000)
+#define ENCI_MACV_N7 ((0x1b37 << 2) + 0xff000000)
+#define ENCI_MACV_N8 ((0x1b38 << 2) + 0xff000000)
+#define ENCI_MACV_N9 ((0x1b39 << 2) + 0xff000000)
+#define ENCI_MACV_N10 ((0x1b3a << 2) + 0xff000000)
+#define ENCI_MACV_N11 ((0x1b3b << 2) + 0xff000000)
+#define ENCI_MACV_N12 ((0x1b3c << 2) + 0xff000000)
+#define ENCI_MACV_N13 ((0x1b3d << 2) + 0xff000000)
+#define ENCI_MACV_N14 ((0x1b3e << 2) + 0xff000000)
+#define ENCI_MACV_N15 ((0x1b3f << 2) + 0xff000000)
+#define ENCI_MACV_N16 ((0x1b40 << 2) + 0xff000000)
+#define ENCI_MACV_N17 ((0x1b41 << 2) + 0xff000000)
+#define ENCI_MACV_N18 ((0x1b42 << 2) + 0xff000000)
+#define ENCI_MACV_N19 ((0x1b43 << 2) + 0xff000000)
+#define ENCI_MACV_N20 ((0x1b44 << 2) + 0xff000000)
+#define ENCI_MACV_N21 ((0x1b45 << 2) + 0xff000000)
+#define ENCI_MACV_N22 ((0x1b46 << 2) + 0xff000000)
+//`define ENCI_MACV_P_AGC 8'h47
+#define ENCI_DBG_PX_RST ((0x1b48 << 2) + 0xff000000)
+#define ENCI_DBG_FLDLN_RST ((0x1b49 << 2) + 0xff000000)
+#define ENCI_DBG_PX_INT ((0x1b4a << 2) + 0xff000000)
+#define ENCI_DBG_FLDLN_INT ((0x1b4b << 2) + 0xff000000)
+#define ENCI_DBG_MAXPX ((0x1b4c << 2) + 0xff000000)
+#define ENCI_DBG_MAXLN ((0x1b4d << 2) + 0xff000000)
+#define ENCI_MACV_MAX_AMP ((0x1b50 << 2) + 0xff000000)
+#define ENCI_MACV_PULSE_LO ((0x1b51 << 2) + 0xff000000)
+#define ENCI_MACV_PULSE_HI ((0x1b52 << 2) + 0xff000000)
+#define ENCI_MACV_BKP_MAX ((0x1b53 << 2) + 0xff000000)
+#define ENCI_CFILT_CTRL ((0x1b54 << 2) + 0xff000000)
+#define ENCI_CFILT7 ((0x1b55 << 2) + 0xff000000)
+#define ENCI_YC_DELAY ((0x1b56 << 2) + 0xff000000)
+#define ENCI_VIDEO_EN ((0x1b57 << 2) + 0xff000000)
+//
+// Closing file: enci_regs.h
+//
+//
+// Reading file: venc2_regs.h
+//
+//===========================================================================
+// Venc Registers (Cont.) 0xc00 - 0xcff (VENC registers 0xc00 - 0xcef)
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VENC2_VCBUS_BASE = 0x1c
+// -----------------------------------------------
+// Program video control signals from ENCI core to DVI/HDMI interface
+#define ENCI_DVI_HSO_BEGIN ((0x1c00 << 2) + 0xff000000)
+#define ENCI_DVI_HSO_END ((0x1c01 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_BLINE_EVN ((0x1c02 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_BLINE_ODD ((0x1c03 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_ELINE_EVN ((0x1c04 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_ELINE_ODD ((0x1c05 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_BEGIN_EVN ((0x1c06 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_BEGIN_ODD ((0x1c07 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_END_EVN ((0x1c08 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_END_ODD ((0x1c09 << 2) + 0xff000000)
+// Define cmpt and cvbs cb/cr delay after ENCI chroma filters
+// Bit 15:12 RW, enci_cb_cvbs_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+// Bit 11: 8 RW, enci_cr_cvbs_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+// Bit 7: 4 RW, enci_cb_cmpt_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+// Bit 3: 0 RW, enci_cr_cmpt_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+#define ENCI_CFILT_CTRL2 ((0x1c0a << 2) + 0xff000000)
+#define ENCI_DACSEL_0 ((0x1c0b << 2) + 0xff000000)
+#define ENCI_DACSEL_1 ((0x1c0c << 2) + 0xff000000)
+#define ENCP_DACSEL_0 ((0x1c0d << 2) + 0xff000000)
+#define ENCP_DACSEL_1 ((0x1c0e << 2) + 0xff000000)
+#define ENCP_MAX_LINE_SWITCH_POINT ((0x1c0f << 2) + 0xff000000)
+#define ENCI_TST_EN ((0x1c10 << 2) + 0xff000000)
+#define ENCI_TST_MDSEL ((0x1c11 << 2) + 0xff000000)
+#define ENCI_TST_Y ((0x1c12 << 2) + 0xff000000)
+#define ENCI_TST_CB ((0x1c13 << 2) + 0xff000000)
+#define ENCI_TST_CR ((0x1c14 << 2) + 0xff000000)
+#define ENCI_TST_CLRBAR_STRT ((0x1c15 << 2) + 0xff000000)
+#define ENCI_TST_CLRBAR_WIDTH ((0x1c16 << 2) + 0xff000000)
+#define ENCI_TST_VDCNT_STSET ((0x1c17 << 2) + 0xff000000)
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 7 -- vfifo2vd_drop
+// bit 6:1 -- vfifo2vd_delay
+// bit 0 -- vfifo2vd_en
+#define ENCI_VFIFO2VD_CTL ((0x1c18 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCI_VFIFO2VD_PIXEL_START ((0x1c19 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCI_VFIFO2VD_PIXEL_END ((0x1c1a << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCI_VFIFO2VD_LINE_TOP_START ((0x1c1b << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCI_VFIFO2VD_LINE_TOP_END ((0x1c1c << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCI_VFIFO2VD_LINE_BOT_START ((0x1c1d << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCI_VFIFO2VD_LINE_BOT_END ((0x1c1e << 2) + 0xff000000)
+#define ENCI_VFIFO2VD_CTL2 ((0x1c1f << 2) + 0xff000000)
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 7 -- vfifo2vd_drop
+// bit 6:1 -- vfifo2vd_delay
+// bit 0 -- vfifo2vd_en
+#define ENCT_VFIFO2VD_CTL ((0x1c20 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCT_VFIFO2VD_PIXEL_START ((0x1c21 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCT_VFIFO2VD_PIXEL_END ((0x1c22 << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCT_VFIFO2VD_LINE_TOP_START ((0x1c23 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCT_VFIFO2VD_LINE_TOP_END ((0x1c24 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCT_VFIFO2VD_LINE_BOT_START ((0x1c25 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCT_VFIFO2VD_LINE_BOT_END ((0x1c26 << 2) + 0xff000000)
+#define ENCT_VFIFO2VD_CTL2 ((0x1c27 << 2) + 0xff000000)
+#define ENCT_TST_EN ((0x1c28 << 2) + 0xff000000)
+#define ENCT_TST_MDSEL ((0x1c29 << 2) + 0xff000000)
+#define ENCT_TST_Y ((0x1c2a << 2) + 0xff000000)
+#define ENCT_TST_CB ((0x1c2b << 2) + 0xff000000)
+#define ENCT_TST_CR ((0x1c2c << 2) + 0xff000000)
+#define ENCT_TST_CLRBAR_STRT ((0x1c2d << 2) + 0xff000000)
+#define ENCT_TST_CLRBAR_WIDTH ((0x1c2e << 2) + 0xff000000)
+#define ENCT_TST_VDCNT_STSET ((0x1c2f << 2) + 0xff000000)
+// Program video control signals from ENCP core to DVI/HDMI interface
+#define ENCP_DVI_HSO_BEGIN ((0x1c30 << 2) + 0xff000000)
+#define ENCP_DVI_HSO_END ((0x1c31 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_BLINE_EVN ((0x1c32 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_BLINE_ODD ((0x1c33 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_ELINE_EVN ((0x1c34 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_ELINE_ODD ((0x1c35 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_BEGIN_EVN ((0x1c36 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_BEGIN_ODD ((0x1c37 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_END_EVN ((0x1c38 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_END_ODD ((0x1c39 << 2) + 0xff000000)
+#define ENCP_DE_H_BEGIN ((0x1c3a << 2) + 0xff000000)
+#define ENCP_DE_H_END ((0x1c3b << 2) + 0xff000000)
+#define ENCP_DE_V_BEGIN_EVEN ((0x1c3c << 2) + 0xff000000)
+#define ENCP_DE_V_END_EVEN ((0x1c3d << 2) + 0xff000000)
+#define ENCP_DE_V_BEGIN_ODD ((0x1c3e << 2) + 0xff000000)
+#define ENCP_DE_V_END_ODD ((0x1c3f << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCI_SYNC_LINE_LENGTH ((0x1c40 << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCI_SYNC_PIXEL_EN ((0x1c41 << 2) + 0xff000000)
+// Bit 15 - enci_sync_enable
+// Bit 14 - encp_sync_enable
+// Bit 13 - enct_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCI_SYNC_TO_LINE_EN ((0x1c42 << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCI_SYNC_TO_PIXEL ((0x1c43 << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCP_SYNC_LINE_LENGTH ((0x1c44 << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCP_SYNC_PIXEL_EN ((0x1c45 << 2) + 0xff000000)
+// Bit 15 - enci_sync_enable
+// Bit 14 - encp_sync_enable
+// Bit 13 - enct_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCP_SYNC_TO_LINE_EN ((0x1c46 << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCP_SYNC_TO_PIXEL ((0x1c47 << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCT_SYNC_LINE_LENGTH ((0x1c48 << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCT_SYNC_PIXEL_EN ((0x1c49 << 2) + 0xff000000)
+// Bit 15 - enci_sync_enable
+// Bit 14 - encp_sync_enable
+// Bit 13 - enct_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCT_SYNC_TO_LINE_EN ((0x1c4a << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCT_SYNC_TO_PIXEL ((0x1c4b << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCL_SYNC_LINE_LENGTH ((0x1c4c << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCL_SYNC_PIXEL_EN ((0x1c4d << 2) + 0xff000000)
+// Bit 15 - enci_sync_enable
+// Bit 14 - encp_sync_enable
+// Bit 13 - enct_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCL_SYNC_TO_LINE_EN ((0x1c4e << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCL_SYNC_TO_PIXEL ((0x1c4f << 2) + 0xff000000)
+// bit 3 cfg_encp_lcd_scaler_bypass. 1=Do not scale LCD input data;
+// 0=Scale LCD input data to y [16*4,235*4], c [16*4,240*4].
+// bit 2 cfg_encp_vadj_scaler_bypass. 1=Do not scale data to enc480p_vadj;
+// 0=Scale enc480p_vadj input data to y [16*4,235*4], c [16*4,240*4].
+// bit 1 cfg_vfifo2vd_out_scaler_bypass. 1=Do not scale vfifo2vd's output vdata;
+// 0=Scale vfifo2vd's output vdata to y [16,235], c [16,240].
+// bit 0 cfg_vfifo_din_full_range. 1=Data from viu fifo is full range [0,1023];
+// 0=Data from viu fifo is y [16*4,235*4], c [16*4,240*4].
+#define ENCP_VFIFO2VD_CTL2 ((0x1c50 << 2) + 0xff000000)
+// bit 15:1 Reserved.
+// bit 0 cfg_int_dvi_sel_rgb. Applicable for using on-chip hdmi tx module only. This bit controls correct bit-mapping from
+// Venc to hdmi_tx depending on whether YCbCr or RGB mode.
+// 1=Map data bit from Venc to hdmi_tx for RGB mode;
+// 0=Default. Map data bit from Venc to hdmi_tx for YCbCr mode.
+#define VENC_DVI_SETTING_MORE ((0x1c51 << 2) + 0xff000000)
+#define VENC_VDAC_DAC4_FILT_CTRL0 ((0x1c54 << 2) + 0xff000000)
+#define VENC_VDAC_DAC4_FILT_CTRL1 ((0x1c55 << 2) + 0xff000000)
+#define VENC_VDAC_DAC5_FILT_CTRL0 ((0x1c56 << 2) + 0xff000000)
+#define VENC_VDAC_DAC5_FILT_CTRL1 ((0x1c57 << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC_VDAC_DAC0_FILT_CTRL0 ((0x1c58 << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC_VDAC_DAC0_FILT_CTRL1 ((0x1c59 << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC_VDAC_DAC1_FILT_CTRL0 ((0x1c5a << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC_VDAC_DAC1_FILT_CTRL1 ((0x1c5b << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC_VDAC_DAC2_FILT_CTRL0 ((0x1c5c << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC_VDAC_DAC2_FILT_CTRL1 ((0x1c5d << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC_VDAC_DAC3_FILT_CTRL0 ((0x1c5e << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC_VDAC_DAC3_FILT_CTRL1 ((0x1c5f << 2) + 0xff000000)
+//===========================================================================
+// ENCT registers
+#define ENCT_VIDEO_EN ((0x1c60 << 2) + 0xff000000)
+#define ENCT_VIDEO_Y_SCL ((0x1c61 << 2) + 0xff000000)
+#define ENCT_VIDEO_PB_SCL ((0x1c62 << 2) + 0xff000000)
+#define ENCT_VIDEO_PR_SCL ((0x1c63 << 2) + 0xff000000)
+#define ENCT_VIDEO_Y_OFFST ((0x1c64 << 2) + 0xff000000)
+#define ENCT_VIDEO_PB_OFFST ((0x1c65 << 2) + 0xff000000)
+#define ENCT_VIDEO_PR_OFFST ((0x1c66 << 2) + 0xff000000)
+//----- Video mode
+#define ENCT_VIDEO_MODE ((0x1c67 << 2) + 0xff000000)
+#define ENCT_VIDEO_MODE_ADV ((0x1c68 << 2) + 0xff000000)
+//--------------- Debug pins
+#define ENCT_DBG_PX_RST ((0x1c69 << 2) + 0xff000000)
+#define ENCT_DBG_LN_RST ((0x1c6a << 2) + 0xff000000)
+#define ENCT_DBG_PX_INT ((0x1c6b << 2) + 0xff000000)
+#define ENCT_DBG_LN_INT ((0x1c6c << 2) + 0xff000000)
+//----------- Video Advanced setting
+#define ENCT_VIDEO_YFP1_HTIME ((0x1c6d << 2) + 0xff000000)
+#define ENCT_VIDEO_YFP2_HTIME ((0x1c6e << 2) + 0xff000000)
+#define ENCT_VIDEO_YC_DLY ((0x1c6f << 2) + 0xff000000)
+#define ENCT_VIDEO_MAX_PXCNT ((0x1c70 << 2) + 0xff000000)
+#define ENCT_VIDEO_HAVON_END ((0x1c71 << 2) + 0xff000000)
+#define ENCT_VIDEO_HAVON_BEGIN ((0x1c72 << 2) + 0xff000000)
+#define ENCT_VIDEO_VAVON_ELINE ((0x1c73 << 2) + 0xff000000)
+#define ENCT_VIDEO_VAVON_BLINE ((0x1c74 << 2) + 0xff000000)
+#define ENCT_VIDEO_HSO_BEGIN ((0x1c75 << 2) + 0xff000000)
+#define ENCT_VIDEO_HSO_END ((0x1c76 << 2) + 0xff000000)
+#define ENCT_VIDEO_VSO_BEGIN ((0x1c77 << 2) + 0xff000000)
+#define ENCT_VIDEO_VSO_END ((0x1c78 << 2) + 0xff000000)
+#define ENCT_VIDEO_VSO_BLINE ((0x1c79 << 2) + 0xff000000)
+#define ENCT_VIDEO_VSO_ELINE ((0x1c7a << 2) + 0xff000000)
+#define ENCT_VIDEO_MAX_LNCNT ((0x1c7b << 2) + 0xff000000)
+#define ENCT_VIDEO_BLANKY_VAL ((0x1c7c << 2) + 0xff000000)
+#define ENCT_VIDEO_BLANKPB_VAL ((0x1c7d << 2) + 0xff000000)
+#define ENCT_VIDEO_BLANKPR_VAL ((0x1c7e << 2) + 0xff000000)
+#define ENCT_VIDEO_HOFFST ((0x1c7f << 2) + 0xff000000)
+#define ENCT_VIDEO_VOFFST ((0x1c80 << 2) + 0xff000000)
+#define ENCT_VIDEO_RGB_CTRL ((0x1c81 << 2) + 0xff000000)
+#define ENCT_VIDEO_FILT_CTRL ((0x1c82 << 2) + 0xff000000)
+#define ENCT_VIDEO_OFLD_VPEQ_OFST ((0x1c83 << 2) + 0xff000000)
+#define ENCT_VIDEO_OFLD_VOAV_OFST ((0x1c84 << 2) + 0xff000000)
+#define ENCT_VIDEO_MATRIX_CB ((0x1c85 << 2) + 0xff000000)
+#define ENCT_VIDEO_MATRIX_CR ((0x1c86 << 2) + 0xff000000)
+#define ENCT_VIDEO_RGBIN_CTRL ((0x1c87 << 2) + 0xff000000)
+#define ENCT_MAX_LINE_SWITCH_POINT ((0x1c88 << 2) + 0xff000000)
+#define ENCT_DACSEL_0 ((0x1c89 << 2) + 0xff000000)
+#define ENCT_DACSEL_1 ((0x1c8a << 2) + 0xff000000)
+#define ENCT_INBUF_CNTL0 ((0x1c8b << 2) + 0xff000000)
+#define ENCT_INBUF_CNTL1 ((0x1c8c << 2) + 0xff000000)
+#define ENCT_INBUF_CNT ((0x1c8d << 2) + 0xff000000)
+#define ENCT_INBUF_HOLD_CNT ((0x1c8e << 2) + 0xff000000)
+#define ENCT_INBUF_FIX_PIX_NUM ((0x1c8f << 2) + 0xff000000)
+//===========================================================================
+// For ENCL
+//===========================================================================
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 7 -- vfifo2vd_drop
+// bit 6:1 -- vfifo2vd_delay
+// bit 0 -- vfifo2vd_en
+#define ENCL_VFIFO2VD_CTL ((0x1c90 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCL_VFIFO2VD_PIXEL_START ((0x1c91 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCL_VFIFO2VD_PIXEL_END ((0x1c92 << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCL_VFIFO2VD_LINE_TOP_START ((0x1c93 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCL_VFIFO2VD_LINE_TOP_END ((0x1c94 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCL_VFIFO2VD_LINE_BOT_START ((0x1c95 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCL_VFIFO2VD_LINE_BOT_END ((0x1c96 << 2) + 0xff000000)
+#define ENCL_VFIFO2VD_CTL2 ((0x1c97 << 2) + 0xff000000)
+#define ENCL_TST_EN ((0x1c98 << 2) + 0xff000000)
+#define ENCL_TST_MDSEL ((0x1c99 << 2) + 0xff000000)
+#define ENCL_TST_Y ((0x1c9a << 2) + 0xff000000)
+#define ENCL_TST_CB ((0x1c9b << 2) + 0xff000000)
+#define ENCL_TST_CR ((0x1c9c << 2) + 0xff000000)
+#define ENCL_TST_CLRBAR_STRT ((0x1c9d << 2) + 0xff000000)
+#define ENCL_TST_CLRBAR_WIDTH ((0x1c9e << 2) + 0xff000000)
+#define ENCL_TST_VDCNT_STSET ((0x1c9f << 2) + 0xff000000)
+//===========================================================================
+// ENCL registers
+#define ENCL_VIDEO_EN ((0x1ca0 << 2) + 0xff000000)
+#define ENCL_VIDEO_Y_SCL ((0x1ca1 << 2) + 0xff000000)
+#define ENCL_VIDEO_PB_SCL ((0x1ca2 << 2) + 0xff000000)
+#define ENCL_VIDEO_PR_SCL ((0x1ca3 << 2) + 0xff000000)
+#define ENCL_VIDEO_Y_OFFST ((0x1ca4 << 2) + 0xff000000)
+#define ENCL_VIDEO_PB_OFFST ((0x1ca5 << 2) + 0xff000000)
+#define ENCL_VIDEO_PR_OFFST ((0x1ca6 << 2) + 0xff000000)
+//----- Video mode
+#define ENCL_VIDEO_MODE ((0x1ca7 << 2) + 0xff000000)
+#define ENCL_VIDEO_MODE_ADV ((0x1ca8 << 2) + 0xff000000)
+//--------------- Debug pins
+#define ENCL_DBG_PX_RST ((0x1ca9 << 2) + 0xff000000)
+#define ENCL_DBG_LN_RST ((0x1caa << 2) + 0xff000000)
+#define ENCL_DBG_PX_INT ((0x1cab << 2) + 0xff000000)
+#define ENCL_DBG_LN_INT ((0x1cac << 2) + 0xff000000)
+//----------- Video Advanced setting
+#define ENCL_VIDEO_YFP1_HTIME ((0x1cad << 2) + 0xff000000)
+#define ENCL_VIDEO_YFP2_HTIME ((0x1cae << 2) + 0xff000000)
+#define ENCL_VIDEO_YC_DLY ((0x1caf << 2) + 0xff000000)
+#define ENCL_VIDEO_MAX_PXCNT ((0x1cb0 << 2) + 0xff000000)
+#define ENCL_VIDEO_HAVON_END ((0x1cb1 << 2) + 0xff000000)
+#define ENCL_VIDEO_HAVON_BEGIN ((0x1cb2 << 2) + 0xff000000)
+#define ENCL_VIDEO_VAVON_ELINE ((0x1cb3 << 2) + 0xff000000)
+#define ENCL_VIDEO_VAVON_BLINE ((0x1cb4 << 2) + 0xff000000)
+#define ENCL_VIDEO_HSO_BEGIN ((0x1cb5 << 2) + 0xff000000)
+#define ENCL_VIDEO_HSO_END ((0x1cb6 << 2) + 0xff000000)
+#define ENCL_VIDEO_VSO_BEGIN ((0x1cb7 << 2) + 0xff000000)
+#define ENCL_VIDEO_VSO_END ((0x1cb8 << 2) + 0xff000000)
+#define ENCL_VIDEO_VSO_BLINE ((0x1cb9 << 2) + 0xff000000)
+#define ENCL_VIDEO_VSO_ELINE ((0x1cba << 2) + 0xff000000)
+#define ENCL_VIDEO_MAX_LNCNT ((0x1cbb << 2) + 0xff000000)
+#define ENCL_VIDEO_BLANKY_VAL ((0x1cbc << 2) + 0xff000000)
+#define ENCL_VIDEO_BLANKPB_VAL ((0x1cbd << 2) + 0xff000000)
+#define ENCL_VIDEO_BLANKPR_VAL ((0x1cbe << 2) + 0xff000000)
+#define ENCL_VIDEO_HOFFST ((0x1cbf << 2) + 0xff000000)
+#define ENCL_VIDEO_VOFFST ((0x1cc0 << 2) + 0xff000000)
+#define ENCL_VIDEO_RGB_CTRL ((0x1cc1 << 2) + 0xff000000)
+#define ENCL_VIDEO_FILT_CTRL ((0x1cc2 << 2) + 0xff000000)
+#define ENCL_VIDEO_OFLD_VPEQ_OFST ((0x1cc3 << 2) + 0xff000000)
+#define ENCL_VIDEO_OFLD_VOAV_OFST ((0x1cc4 << 2) + 0xff000000)
+#define ENCL_VIDEO_MATRIX_CB ((0x1cc5 << 2) + 0xff000000)
+#define ENCL_VIDEO_MATRIX_CR ((0x1cc6 << 2) + 0xff000000)
+#define ENCL_VIDEO_RGBIN_CTRL ((0x1cc7 << 2) + 0xff000000)
+#define ENCL_MAX_LINE_SWITCH_POINT ((0x1cc8 << 2) + 0xff000000)
+#define ENCL_DACSEL_0 ((0x1cc9 << 2) + 0xff000000)
+#define ENCL_DACSEL_1 ((0x1cca << 2) + 0xff000000)
+#define ENCT_VIDEO_H_PRE_DE_END ((0x1ccb << 2) + 0xff000000)
+#define ENCT_VIDEO_H_PRE_DE_BEGIN ((0x1ccc << 2) + 0xff000000)
+#define ENCT_VIDEO_V_PRE_DE_ELINE ((0x1ccd << 2) + 0xff000000)
+#define ENCT_VIDEO_V_PRE_DE_BLINE ((0x1cce << 2) + 0xff000000)
+#define ENCL_VIDEO_H_PRE_DE_END ((0x1ccf << 2) + 0xff000000)
+#define ENCL_VIDEO_H_PRE_DE_BEGIN ((0x1cd0 << 2) + 0xff000000)
+#define ENCL_VIDEO_V_PRE_DE_ELINE ((0x1cd1 << 2) + 0xff000000)
+#define ENCL_VIDEO_V_PRE_DE_BLINE ((0x1cd2 << 2) + 0xff000000)
+#define ENCL_INBUF_CNTL0 ((0x1cd3 << 2) + 0xff000000)
+#define ENCL_INBUF_CNTL1 ((0x1cd4 << 2) + 0xff000000)
+#define ENCL_INBUF_CNT ((0x1cd5 << 2) + 0xff000000)
+#define ENCL_INBUF_HOLD_CNT ((0x1cd6 << 2) + 0xff000000)
+#define ENCL_INBUF_FIX_PIX_NUM ((0x1cd7 << 2) + 0xff000000)
+//
+// Closing file: venc2_regs.h
+//
+//
+// Reading file: vpp_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: VPP_VCBUS_BASE = 0x1d
+// -----------------------------------------------
+#define VPP_VD1_SC_OFFSET 0x00 //just used in vpp_vd1_scale
+//===========================================================================
+// Video postprocesing Registers
+//===========================================================================
+// dummy data used in the VPP preblend and scaler
+// Bit 23:16 Y
+// Bit 15:8 CB
+// Bit 7:0 CR
+#define VPP_DUMMY_DATA ((0x1d00 << 2) + 0xff000000)
+//input line length used in VPP
+#define VPP_LINE_IN_LENGTH ((0x1d01 << 2) + 0xff000000)
+//input Picture height used in VPP
+#define VPP_PIC_IN_HEIGHT ((0x1d02 << 2) + 0xff000000)
+//Because there are many coefficients used in the vertical filter and horizontal filters,
+//indirect access the coefficients of vertical filter and horizontal filter is used.
+//For vertical filter, there are 33x4 coefficients
+//For horizontal filter, there are 33x4 coefficients
+//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
+//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
+//Bit 13 if true, vertical separated coef enable
+//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
+//Bit 8:7 type of index, 00: vertical coef, 01: vertical chroma coef: 10: horizontal coef, 11: resevered
+//Bit 6:0 coef index
+#define VPP_SCALE_COEF_IDX ((0x1d03 << 2) + 0xff000000)
+//coefficients for vertical filter and horizontal filter
+#define VPP_SCALE_COEF ((0x1d04 << 2) + 0xff000000)
+//these following registers are the absolute line address pointer for output divided screen
+//The output divided screen is shown in the following:
+//
+// -------------------------- <------ line zero
+// .
+// .
+// . region0 <---------- nonlinear region or nonscaling region
+// .
+// ---------------------------
+// --------------------------- <------ region1_startp
+// .
+// . region1 <---------- nonlinear region
+// .
+// .
+// ---------------------------
+// --------------------------- <------ region2_startp
+// .
+// . region2 <---------- linear region
+// .
+// .
+// ---------------------------
+// --------------------------- <------ region3_startp
+// .
+// . region3 <---------- nonlinear region
+// .
+// .
+// ---------------------------
+// --------------------------- <------ region4_startp
+// .
+// . region4 <---------- nonlinear region or nonoscaling region
+// .
+// .
+// --------------------------- <------ region4_endp
+//Bit 28:16 region1 startp
+//Bit 12:0 region2 startp
+#define VPP_VSC_REGION12_STARTP ((0x1d05 << 2) + 0xff000000)
+//Bit 28:16 region3 startp
+//Bit 12:0 region4 startp
+#define VPP_VSC_REGION34_STARTP ((0x1d06 << 2) + 0xff000000)
+#define VPP_VSC_REGION4_ENDP ((0x1d07 << 2) + 0xff000000)
+//vertical start phase step, (source/dest)*(2^24)
+//Bit 27:24 integer part
+//Bit 23:0 fraction part
+#define VPP_VSC_START_PHASE_STEP ((0x1d08 << 2) + 0xff000000)
+//vertical scaler region0 phase slope, Bit24 signed bit
+#define VPP_VSC_REGION0_PHASE_SLOPE ((0x1d09 << 2) + 0xff000000)
+//vertical scaler region1 phase slope, Bit24 signed bit
+#define VPP_VSC_REGION1_PHASE_SLOPE ((0x1d0a << 2) + 0xff000000)
+//vertical scaler region3 phase slope, Bit24 signed bit
+#define VPP_VSC_REGION3_PHASE_SLOPE ((0x1d0b << 2) + 0xff000000)
+//vertical scaler region4 phase slope, Bit24 signed bit
+#define VPP_VSC_REGION4_PHASE_SLOPE ((0x1d0c << 2) + 0xff000000)
+//Bit 18:17 double line mode, input/output line width of vscaler becomes 2X,
+// so only 2 line buffer in this case, use for 3D line by line interleave scaling
+// bit1 true, double the input width and half input height, bit0 true, change line buffer 2 lines instead of 4 lines
+//Bit 16 0: progressive output, 1: interlace output
+//Bit 15 vertical scaler output line0 in advance or not for bottom field
+//Bit 14:13 vertical scaler initial repeat line0 number for bottom field
+//Bit 11:8 vertical scaler initial receiving number for bottom field
+//Bit 7 vertical scaler output line0 in advance or not for top field
+//Bit 6:5 vertical scaler initial repeat line0 number for top field
+//Bit 3:0 vertical scaler initial receiving number for top field
+#define VPP_VSC_PHASE_CTRL ((0x1d0d << 2) + 0xff000000)
+//Bit 31:16 vertical scaler field initial phase for bottom field
+//Bit 15:0 vertical scaler field initial phase for top field
+#define VPP_VSC_INI_PHASE ((0x1d0e << 2) + 0xff000000)
+//Bit 28:16 region1 startp
+//Bit 12:0 region2 startp
+#define VPP_HSC_REGION12_STARTP ((0x1d10 << 2) + 0xff000000)
+//Bit 28:16 region3 startp
+//Bit 12:0 region4 startp
+#define VPP_HSC_REGION34_STARTP ((0x1d11 << 2) + 0xff000000)
+#define VPP_HSC_REGION4_ENDP ((0x1d12 << 2) + 0xff000000)
+//horizontal start phase step, (source/dest)*(2^24)
+//Bit 27:24 integer part
+//Bit 23:0 fraction part
+#define VPP_HSC_START_PHASE_STEP ((0x1d13 << 2) + 0xff000000)
+//horizontal scaler region0 phase slope, Bit24 signed bit
+#define VPP_HSC_REGION0_PHASE_SLOPE ((0x1d14 << 2) + 0xff000000)
+//horizontal scaler region1 phase slope, Bit24 signed bit
+#define VPP_HSC_REGION1_PHASE_SLOPE ((0x1d15 << 2) + 0xff000000)
+//horizontal scaler region3 phase slope, Bit24 signed bit
+#define VPP_HSC_REGION3_PHASE_SLOPE ((0x1d16 << 2) + 0xff000000)
+//horizontal scaler region4 phase slope, Bit24 signed bit
+#define VPP_HSC_REGION4_PHASE_SLOPE ((0x1d17 << 2) + 0xff000000)
+//Bit 22:21 horizontal scaler initial repeat pixel0 number0
+//Bit 19:16 horizontal scaler initial receiving number0
+//Bit 15:0 horizontal scaler top field initial phase0
+#define VPP_HSC_PHASE_CTRL ((0x1d18 << 2) + 0xff000000)
+// Bit 22 if true, divide VSC line length 2 as the HSC input length, othwise VSC length length is the same as the VSC line length,
+// just for special usage, more flexibility
+// Bit 21 if true, prevsc uses lin buffer, otherwise prevsc does not use line buffer, it should be same as prevsc_en
+// Bit 20 prehsc_en
+// Bit 19 prevsc_en
+// Bit 18 vsc_en
+// Bit 17 hsc_en
+// Bit 16 scale_top_en
+// Bit 15 video1 scale out enable
+// Bit 12 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for horizontal scaler
+// Bit 10:8 horizontal scaler bank length
+// Bit 5, vertical scaler phase field mode, if true, disable the opposite parity line output, more bandwith needed if output 1080i
+// Bit 4 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for vertical scaler
+// Bit 2:0 vertical scaler bank length
+#define VPP_SC_MISC ((0x1d19 << 2) + 0xff000000)
+// preblend video1 horizontal start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_PREBLEND_VD1_H_START_END ((0x1d1a << 2) + 0xff000000)
+// preblend video1 vertical start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_PREBLEND_VD1_V_START_END ((0x1d1b << 2) + 0xff000000)
+// postblend video1 horizontal start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_POSTBLEND_VD1_H_START_END ((0x1d1c << 2) + 0xff000000)
+// postblend video1 vertical start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_POSTBLEND_VD1_V_START_END ((0x1d1d << 2) + 0xff000000)
+// preblend/postblend video2 horizontal start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_BLEND_VD2_H_START_END ((0x1d1e << 2) + 0xff000000)
+// preblend/postblend video2 vertical start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_BLEND_VD2_V_START_END ((0x1d1f << 2) + 0xff000000)
+// preblend horizontal size
+#define VPP_PREBLEND_H_SIZE ((0x1d20 << 2) + 0xff000000)
+// postblend horizontal size
+#define VPP_POSTBLEND_H_SIZE ((0x1d21 << 2) + 0xff000000)
+//VPP hold lines
+//Bit 29:24
+//Bit 21:16
+//Bit 15:8 preblend hold lines
+//Bit 7:0 postblend hold lines
+#define VPP_HOLD_LINES ((0x1d22 << 2) + 0xff000000)
+//Bit 26 if true, automatic change post blend output to one color if field ==1
+//Bit 25 if true, change screen to one color value for preblender
+//Bit 24 if true, change screen to one color value for postblender
+// Bit 23:16 one color Y
+// Bit 15:8 one color Cb
+// Bit 7:0 one color Cr
+#define VPP_BLEND_ONECOLOR_CTRL ((0x1d23 << 2) + 0xff000000)
+//Read Only, VPP preblend current_x, current_y
+//Bit 28:16 current_x
+//Bit 12:0 current_y
+#define VPP_PREBLEND_CURRENT_XY ((0x1d24 << 2) + 0xff000000)
+//Read Only, VPP postblend current_x, current_y
+//Bit 28:16 current_x
+//Bit 12:0 current_y
+#define VPP_POSTBLEND_CURRENT_XY ((0x1d25 << 2) + 0xff000000)
+// Bit 31 vd1_bgosd_exchange_en for preblend
+// Bit 30 vd1_bgosd_exchange_en for postblend
+// Bit 28 color management enable
+// Bit 27, if true, vd2 use viu2 output as the input, otherwise use normal vd2 from memory
+// Bit 26:18, vd2 alpha
+// Bit 17, osd2 enable for preblend
+// Bit 16, osd1 enable for preblend
+// Bit 15, vd2 enable for preblend
+// Bit 14, vd1 enable for preblend
+// Bit 13, osd2 enable for postblend
+// Bit 12, osd1 enable for postblend
+// Bit 11, vd2 enable for postblend
+// Bit 10, vd1 enable for postblend
+// Bit 9, if true, osd1 is alpha premultipiled
+// Bit 8, if true, osd2 is alpha premultipiled
+// Bit 7, postblend module enable
+// Bit 6, preblend module enable
+// Bit 5, if true, osd2 foreground compared with osd1 in preblend
+// Bit 4, if true, osd2 foreground compared with osd1 in postblend
+// Bit 3,
+// Bit 2, if true, disable resetting async fifo every vsync, otherwise every vsync
+// the aync fifo will be reseted.
+// Bit 1,
+// Bit 0 if true, the output result of VPP is saturated
+#define VPP_MISC ((0x1d26 << 2) + 0xff000000)
+//Bit 31:20 ofifo line length minus 1
+//Bit 19 if true invert input vs
+//Bit 18 if true invert input hs
+//Bit 17 force top/bottom field, enable
+//Bit 16 force top/bottom field, 0: top, 1: bottom
+//Bit 15 force one go_field, one pluse, write only
+//Bit 14 force one go_line, one pluse, write only
+//Bit 12:0 ofifo size (actually only bit 10:1 is valid), always even number
+#define VPP_OFIFO_SIZE ((0x1d27 << 2) + 0xff000000)
+//Read only
+//Bit 28:18 current scale out fifo counter
+//Bit 17:13 current afifo counter
+//Bit 12:0 current ofifo counter
+#define VPP_FIFO_STATUS ((0x1d28 << 2) + 0xff000000)
+// Bit 5 SMOKE3 postblend enable only when postblend vd2 is not enable
+// Bit 4 SMOKE3 preblend enable only when preblend vd2 is not enable
+// Bit 3 SMOKE2 postblend enable only when postblend osd2 is not enable
+// Bit 2 SMOKE2 preblend enable only when preblend osd2 is not enable
+// Bit 1 SMOKE1 postblend enable only when postblend osd1 is not enable
+// Bit 0 SMOKE1 preblend enable only when preblend osd1 is not enable
+#define VPP_SMOKE_CTRL ((0x1d29 << 2) + 0xff000000)
+//smoke can be used only when that blending is disable and then be used as smoke function
+//smoke1 for OSD1 chanel
+//smoke2 for OSD2 chanel
+//smoke3 for VD2 chanel
+//31:24 Y
+//23:16 Cb
+//15:8 Cr
+//7:0 Alpha
+#define VPP_SMOKE1_VAL ((0x1d2a << 2) + 0xff000000)
+#define VPP_SMOKE2_VAL ((0x1d2b << 2) + 0xff000000)
+#define VPP_SMOKE3_VAL ((0x1d2c << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_SMOKE1_H_START_END ((0x1d2d << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_SMOKE1_V_START_END ((0x1d2e << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_SMOKE2_H_START_END ((0x1d2f << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_SMOKE2_V_START_END ((0x1d30 << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_SMOKE3_H_START_END ((0x1d31 << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_SMOKE3_V_START_END ((0x1d32 << 2) + 0xff000000)
+//Bit 27:16 scale out fifo line length minus 1
+//Bit 12:0 scale out fifo size (actually only bit 11:1 is valid, 11:1, max 1024), always even number
+#define VPP_SCO_FIFO_CTRL ((0x1d33 << 2) + 0xff000000)
+//for 3D quincunx sub-sampling and horizontal pixel by pixel 3D interleaving
+//Bit 27:24, prehsc_mode, bit 3:2, prehsc odd line interp mode, bit 1:0, prehsc even line interp mode,
+// each 2bit, 00: pix0+pix1/2, average, 01: pix1, 10: pix0
+//Bit 23 horizontal scaler double pixel mode
+//Bit 22:21 horizontal scaler initial repeat pixel0 number1
+//Bit 19:16 horizontal scaler initial receiving number1
+//Bit 15:0 horizontal scaler top field initial phase1
+#define VPP_HSC_PHASE_CTRL1 ((0x1d34 << 2) + 0xff000000)
+//for 3D quincunx sub-sampling
+//31:24 prehsc pattern, each patten 1 bit, from lsb -> msb
+//22:20 prehsc pattern start
+//18:16 prehsc pattern end
+//15:8 hsc pattern, each patten 1 bit, from lsb -> msb
+//6:4 hsc pattern start
+//2:0 hsc pattern end
+#define VPP_HSC_INI_PAT_CTRL ((0x1d35 << 2) + 0xff000000)
+#define VPP_SC_GCLK_CTRL1 ((0x1d36 << 2) + 0xff000000)
+//Bit 3 minus black level enable for vadj2
+//Bit 2 Video adjustment enable for vadj2
+//Bit 1 minus black level enable for vadj1
+//Bit 0 Video adjustment enable for vadj1
+#define VPP_VADJ_CTRL ((0x1d40 << 2) + 0xff000000)
+//Bit 16:8 brightness, signed value
+//Bit 7:0 contrast, unsigned value, contrast from 0 <= contrast <2
+//`define VPP_VADJ1_Y 8'h41 //'h00080
+//cb' = cb*ma + cr*mb
+//cr' = cb*mc + cr*md
+//all are bit 9:0, signed value, -2 < ma/mb/mc/md < 2
+//`define VPP_VADJ1_MA_MB 8'h42 //26'h100_0000
+//`define VPP_VADJ1_MC_MD 8'h43 //26'h000_0100
+//Bit 16:8 brightness, signed value
+//Bit 7:0 contrast, unsigned value, contrast from 0 <= contrast <2
+//`define VPP_VADJ2_Y 8'h44 //'h00080
+//cb' = cb*ma + cr*mb
+//cr' = cb*mc + cr*md
+//all are bit 9:0, signed value, -2 < ma/mb/mc/md < 2
+//`define VPP_VADJ2_MA_MB 8'h45 //26'h100_0000
+//`define VPP_VADJ2_MC_MD 8'h46 //26'h000_0100
+//Bit 2 horizontal chroma sharp/blur selection, 0:sharp, 1: blur
+//Bit 1 horizontal luma sharp/blur selection, 0:sharp, 1: blur
+//Bit 0 horizontal sharpness enable
+#define VPP_HSHARP_CTRL ((0x1d50 << 2) + 0xff000000)
+//{1'b0,threhsold} < diff
+//Bit 26:16 luma threshold0
+//Bit 10:0 luma threshold1
+#define VPP_HSHARP_LUMA_THRESH01 ((0x1d51 << 2) + 0xff000000)
+//
+//Bit 26:16 luma threshold2
+//Bit 10:0 luma threshold3
+#define VPP_HSHARP_LUMA_THRESH23 ((0x1d52 << 2) + 0xff000000)
+//Bit 26:16 chroma threshold0
+//Bit 10:0 chroma threshold1
+#define VPP_HSHARP_CHROMA_THRESH01 ((0x1d53 << 2) + 0xff000000)
+//Bit 26:16 chroma threshold2
+//Bit 10:0 chroma threshold3
+#define VPP_HSHARP_CHROMA_THRESH23 ((0x1d54 << 2) + 0xff000000)
+//Bit 23:16 luma gain2
+//Bit 15:8 luma gain1
+//Bit 7:0 luma gain0
+#define VPP_HSHARP_LUMA_GAIN ((0x1d55 << 2) + 0xff000000)
+//
+//Bit 23:16 chroma gain2
+//Bit 15:8 chroma gain1
+//Bit 7:0 chroma gain0
+#define VPP_HSHARP_CHROMA_GAIN ((0x1d56 << 2) + 0xff000000)
+//Read only
+//Bit 31, if it is true, it means this probe is valid in the last field/frame
+//Bit 29:20 component 0
+//Bit 19:10 component 1
+//Bit 9:0 component 2
+#define VPP_MATRIX_PROBE_COLOR ((0x1d5c << 2) + 0xff000000)
+#define VPP_MATRIX_PROBE_COLOR1 ((0x1dd7 << 2) + 0xff000000)
+//Bit 23:16 component 0
+//Bit 15:8 component 1
+//Bit 7:0 component 2
+#define VPP_MATRIX_HL_COLOR ((0x1d5d << 2) + 0xff000000)
+//28:16 probe x, postion
+//12:0 probe y, position
+#define VPP_MATRIX_PROBE_POS ((0x1d5e << 2) + 0xff000000)
+//Bit 16, highlight_en
+//Bit 15 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix
+//Bit 14:12 probe_sel, 000: select post matrix, 001: select vd1 matrix, 010: select vd2 matrix
+//Bit 9:8 matrix coef idx selection, 00: select post matrix, 01: select vd1 matrix, 10: select vd2 matrix
+//Bit 5 vd1 conversion matrix enable
+//Bit 4 vd2 conversion matrix enable
+//Bit 2 output y/cb/cr saturation enable, only for post matrix (y saturate to 16-235, cb/cr saturate to 16-240)
+//Bit 1 input y/cb/cr saturation enable, only for post matrix (y saturate to 16-235, cb/cr saturate to 16-240)
+//Bit 0 post conversion matrix enable
+#define VPP_MATRIX_CTRL ((0x1d5f << 2) + 0xff000000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define VPP_MATRIX_COEF00_01 ((0x1d60 << 2) + 0xff000000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define VPP_MATRIX_COEF02_10 ((0x1d61 << 2) + 0xff000000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define VPP_MATRIX_COEF11_12 ((0x1d62 << 2) + 0xff000000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define VPP_MATRIX_COEF20_21 ((0x1d63 << 2) + 0xff000000)
+#define VPP_MATRIX_COEF22 ((0x1d64 << 2) + 0xff000000)
+//Bit 26:16 offset0
+//Bit 10:0 offset1
+#define VPP_MATRIX_OFFSET0_1 ((0x1d65 << 2) + 0xff000000)
+//Bit 10:0 offset2
+#define VPP_MATRIX_OFFSET2 ((0x1d66 << 2) + 0xff000000)
+//Bit 26:16 pre_offset0
+//Bit 10:0 pre_offset1
+#define VPP_MATRIX_PRE_OFFSET0_1 ((0x1d67 << 2) + 0xff000000)
+//Bit 10:0 pre_offset2
+#define VPP_MATRIX_PRE_OFFSET2 ((0x1d68 << 2) + 0xff000000)
+// dummy data used in the VPP postblend
+// Bit 23:16 Y
+// Bit 15:8 CB
+// Bit 7:0 CR
+#define VPP_DUMMY_DATA1 ((0x1d69 << 2) + 0xff000000)
+//Bit 31 gainoff module enable
+//Bit 26:16 gain0, 1.10 unsigned data
+//Bit 10:0 gain1, 1.10 unsigned dat
+#define VPP_GAINOFF_CTRL0 ((0x1d6a << 2) + 0xff000000)
+//Bit 26:16 gain2, 1.10 unsigned data
+//Bit 10:0, offset0, signed data
+#define VPP_GAINOFF_CTRL1 ((0x1d6b << 2) + 0xff000000)
+//Bit 26:16, offset1, signed data
+//Bit 10:0, offset2, signed data
+#define VPP_GAINOFF_CTRL2 ((0x1d6c << 2) + 0xff000000)
+//Bit 26:16, pre_offset0, signed data
+//Bit 10:0, pre_offset1, signed data
+#define VPP_GAINOFF_CTRL3 ((0x1d6d << 2) + 0xff000000)
+//Bit 10:0, pre_offset2, signed data
+#define VPP_GAINOFF_CTRL4 ((0x1d6e << 2) + 0xff000000)
+#define VPP_GAINOFF_GCLK_CTRL ((0x1d6f << 2) + 0xff000000)
+//only two registers used in the color management, which are defined in the chroma_reg.h
+//`define VPP_CHROMA_ADDR_PORT 8'h70
+//`define VPP_CHROMA_DATA_PORT 8'h71
+//
+// Reading file: chroma_reg.h
+//
+//**********************************************************************************
+//* Copyright (c) 2008, AMLOGIC Inc.
+//* All rights reserved
+//**********************************************************************************
+//* File : chroma_reg.v
+//* Author : Terrence Wang
+//* Date : Dec 2008
+//* Description :
+//*
+//**********************************************************************************
+//* Modification History:
+//* Date Modified By Reason
+//**********************************************************************************
+// synopsys translate_off
+// synopsys translate_on
+#define VPP_CHROMA_ADDR_PORT ((0x1d70 << 2) + 0xff000000)
+#define VPP_CHROMA_DATA_PORT ((0x1d71 << 2) + 0xff000000)
+//`define CHROMA_ADDR_PORT 8'h67
+//`define CHROMA_DATA_PORT 8'h68
+
+// CHROMA_GAIN_REG_XX(00-07)
+// hue gain, sat gain function control
+// Bit 31 reg_sat_en enable sat adjustment in current region
+// Bit 27 reg_sat_increase sat adjustment increase or decrease
+// 1'b1: increase 1'b0: decrease
+// Bit 26:25 reg_sat_central_en sat adjustment with central biggest or one side biggest
+// 2'b01 central biggest 2'b00 one side biggest
+// Bit 24 reg_sat_shape when sat adjustment one side biggest, define left or right
+// 1'b1: left side biggest 1'b0 right side biggest
+// Bit 23:16 reg_sat_gain define the sat gain when sat adjustment
+// 0x00-0xff
+// Bit 15 reg_hue_en enable hue adjustment in current region
+// Bit 11 reg_hue_clockwise hue adjustment clockwise or anti-clockwise
+// 1'b1: clockwise 1'b0: anti-clockwise
+// Bit 10:9 reg_hue_central_en when hue adjustment, parabola curve or non-symmetry curve
+// 1'b1: parabola curve 1'b0: non-symmetry curve
+// Bit 8 reg_hue_shape when non-symmetry curve, define which side change more
+// 1'b1: right side change more 1'b0: left side change more
+// Bit 7:0 reg_hue_gain define the hue gain when hue adjustment
+// 0x00-0x80, note: should be no bigger than 0x80
+
+ #define CHROMA_GAIN_REG00 0x00
+
+
+// HUE_HUE_RANGE_REG_XX(00-07)
+// hue range select
+// Bit 31:24 no use now
+// Bit 23:16 reg_hue_shift_range define the angle of target region
+// 0x00-0xff,(0x100 means 120 degree though it can not be set)
+// must be greater or equal than 8'd8
+// Bit 15 reg_symmetry_en this is used for create one symmetry region
+// the symmetry region hue_shift_start = reg_hue_hue_shift_start + reg_hue_shift_range<<5
+// the symmetry region hue_shift_range = reg_hue_shift_range
+// in symmetry region, all the sat and hue setting will be same with original region,
+// except reg_hue_shape, reg_sat_shape, reg_hue_clockwise will be reversed
+// Bit 14:0 reg_hue_hue_shift_start define the start angle of target region
+// 0x6000 means 360 degree
+// only region 0 and 1 can exceed 360 degrees.
+
+ #define HUE_HUE_RANGE_REG00 0x01
+
+
+// HUE_RANGE_INV_REG_XX
+// Calculation should be follow
+// HUE_RANGE_INV_REG0X[15:0] = ((1<<20)/HUE_HUE_RANGE_REG0X[23:16]+1)>>1
+// HUE_RANGE_INV_REG_XX is to used to save divider
+
+ #define HUE_RANGE_INV_REG00 0x02
+
+
+
+// for belowing each low, high, low_slope, high_slope group:
+// a_____________b
+// / \ a = low + 2^low_slope
+// / \ b = high - 2^high_slope
+// / \ low_slope <= 7; high_slope <= 7
+// / \ b >= a
+// ______/_____________________\________
+// low high
+//
+//
+// HUE_LUM_RANGE_REG_XX(00-07)
+// luma range selection for hue adjustment
+// Bit 31:24 reg_sat_lum_low define the low level of luma value for sat adjustment
+// 0x00-0xff
+// Bit 23:20 reg_hue_lum_high_slope define the slope area below high level of luma value for hue adjustment
+// 0x00-0x07
+// Bit 19:16 reg_hue_lum_low_slope define the slope area above low level of luma value for hue adjustment
+// 0x00-0x07
+// Bit 15:8 reg_hue_lum_high define the high level of luma value for hue adjustment
+// 0x00-0xff
+// Bit 7:0 reg_hue_lum_low define the low level of luma value for hue adjustment
+// 0x00-0xff
+
+ #define HUE_LUM_RANGE_REG00 0x03
+
+// HUE_SAT_RANGE_REG_XX(00-07)
+// sat range selection for hue adjustment
+// Bit 31:24 reg_sat_lum_high define the high level of luma value for sat adjustment
+// 0x00-0xff
+// Bit 23:20 reg_hue_sat_high_slope define the slope area below high level of sat value for hue adjustment
+// 0x00-0x07
+// Bit 19:16 reg_hue_sat_low_slope define the slope area above low level of sat value for hue adjustment
+// 0x00-0x07
+// Bit 15:8 reg_hue_sat_high define the high level of sat value for hue adjustment
+// 0x00-0xff
+// Bit 7:0 reg_hue_sat_low define the low level of sat value for hue adjustment
+// 0x00-0xff
+
+ #define HUE_SAT_RANGE_REG00 0x04
+
+// SAT_SAT_RANGE_REG_XX(00-07)
+// sat range selection for hue adjustment
+// Bit 31:28 reg_sat_lum_high_slope define the slope area below high level of luma value for sat adjustment
+// 0x00-0x07
+// Bit 27:24 reg_sat_lum_low_slope define the slope area above low level of luma value for sat adjustment
+// 0x00-0x07
+// Bit 23:20 reg_sat_sat_high_slope define the slope area below high level of sat value for sat adjustment
+// 0x00-0x07
+// Bit 19:16 reg_sat_sat_low_slope define the slope area above low level of sat value for sat adjustment
+// 0x00-0x07
+// Bit 15:8 reg_sat_sat_high define the high level of sat value for sat adjustment
+// 0x00-0xff
+// Bit 7:0 reg_sat_sat_low define the low level of sat value for sat adjustment
+// 0x00-0xff
+
+ #define SAT_SAT_RANGE_REG00 0x05
+
+
+ #define CHROMA_GAIN_REG01 0x06
+ #define HUE_HUE_RANGE_REG01 0x07
+ #define HUE_RANGE_INV_REG01 0x08
+ #define HUE_LUM_RANGE_REG01 0x09
+ #define HUE_SAT_RANGE_REG01 0x0a
+ #define SAT_SAT_RANGE_REG01 0x0b
+
+ #define CHROMA_GAIN_REG02 0x0c
+ #define HUE_HUE_RANGE_REG02 0x0d
+ #define HUE_RANGE_INV_REG02 0x0e
+ #define HUE_LUM_RANGE_REG02 0x0f
+ #define HUE_SAT_RANGE_REG02 0x10
+ #define SAT_SAT_RANGE_REG02 0x11
+
+
+ #define CHROMA_GAIN_REG03 0x12
+ #define HUE_HUE_RANGE_REG03 0x13
+ #define HUE_RANGE_INV_REG03 0x14
+ #define HUE_LUM_RANGE_REG03 0x15
+ #define HUE_SAT_RANGE_REG03 0x16
+ #define SAT_SAT_RANGE_REG03 0x17
+
+ #define CHROMA_GAIN_REG04 0x18
+ #define HUE_HUE_RANGE_REG04 0x19
+ #define HUE_RANGE_INV_REG04 0x1a
+ #define HUE_LUM_RANGE_REG04 0x1b
+ #define HUE_SAT_RANGE_REG04 0x1c
+ #define SAT_SAT_RANGE_REG04 0x1d
+
+ #define CHROMA_GAIN_REG05 0x1e
+ #define HUE_HUE_RANGE_REG05 0x1f
+ #define HUE_RANGE_INV_REG05 0x20
+ #define HUE_LUM_RANGE_REG05 0x21
+ #define HUE_SAT_RANGE_REG05 0x22
+ #define SAT_SAT_RANGE_REG05 0x23
+
+ #define CHROMA_GAIN_REG06 0x24
+ #define HUE_HUE_RANGE_REG06 0x25
+ #define HUE_RANGE_INV_REG06 0x26
+ #define HUE_LUM_RANGE_REG06 0x27
+ #define HUE_SAT_RANGE_REG06 0x28
+ #define SAT_SAT_RANGE_REG06 0x29
+
+ #define CHROMA_GAIN_REG07 0x2a
+ #define HUE_HUE_RANGE_REG07 0x2b
+ #define HUE_RANGE_INV_REG07 0x2c
+ #define HUE_LUM_RANGE_REG07 0x2d
+ #define HUE_SAT_RANGE_REG07 0x2e
+ #define SAT_SAT_RANGE_REG07 0x2f
+
+// REG_CHROMA_CONTROL
+// Bit 31 reg_chroma_en enable color manage function
+// 1'b1: enable 1'b0: bypass
+// Bit 6 sat_sel uv_max or u^2+v^2 selected as sat for reference
+// 1'b1: uv_max(default) 1'b0: u^2+v^2
+// Bit 5 uv_adj_en final uv_adjust enable
+// 1'b1: enable 1'b0: bypass
+// Bit 2 hue_en rgb to hue enable
+// 1'b1: enable(default) 1'b0: bypass
+// Bit 1:0 csc_sel define input YUV with different color type
+// 2'b00: 601(16-235) 2'b01: 709(16-235)
+// 2'b10: 601(0-255) 2'b11: 709(0-255)
+ #define REG_CHROMA_CONTROL 0x30 // default 32h'80000024
+ #define REG_DEMO_CENTER_BAR 0x31 // default 32h'0
+ #define REG_DEMO_HLIGHT_MODE 0x32 // default 32h'0
+ #define REG_DEMO_OWR_DATA 0x33 // default 32h'0
+
+
+////===========================================////
+//// CM2 ADDR
+////===========================================////
+
+ #define SAT_BYYB_NODE_REG0 0x200 // default 32'h0
+//Bit 31:24, sat_byyb_node3 the 4th node
+//Bit 23:16, sat_byyb_node2 the 3th node
+//Bit 15: 8, sat_byyb_node1 signed, the 2th node about saturation
+//Bit 7: 0, sat_byyb_node0 signed, the 1th node about saturation
+//gain offset along y coordinate,the gain normalized to 128 as "1"
+
+ #define SAT_BYYB_NODE_REG1 0x201 // default 32'h0
+//Bit 31:24, sat_byyb_node7 the 8th node
+//Bit 23:16, sat_byyb_node6 the 7th node
+//Bit 15: 8, sat_byyb_node5 signed, the 6th node about saturation
+//Bit 7: 0, sat_byyb_node4 signed, the 5th node about saturation
+//gain offset along y coordinate,the gain normalized to 128 as "1"
+
+ #define SAT_BYYB_NODE_REG2 0x202 // default 32'h0
+//Bit 31: 8, reserved
+//Bit 7: 0, sat_byyb_node4 signed, the 5th node about saturation
+
+
+ #define SAT_SRC_NODE_REG 0x203 // default 32'h0
+//Bit 31:28, reserved
+//Bit 27:16, sat_src_node1
+//Bit 15:12, reserved
+//Bit 11: 0, sat_src_node0 usigned, threshold of input saturation for first and second piece
+
+ #define CM_ENH_SFT_MODE_REG 0x204 // default 32'h0
+//Bit 31: 9, reserved
+//Bit 8: 6, hue_lsft_mode hue offset adjustments scale
+//Bit 5: 4, luma_lsft_mode luma offset adjustments scale for reg_cm2_adj_luma_via_hue
+//Bit 3: 2, sat_byy_rsft_mode saturation gain adjustments scale for reg_cm2_adj_sat_via_y
+//Bit 1: 0, sat_byhs_rsft_mode saturation gain adjustments scale for reg_cm2_adj_sat_via_hs[:][:] 0:no scale up/down 1:dnscale by 2(-128,127)/2
+
+ #define FRM_SIZE_REG 0x205 // default 32'h0
+//Bit 31:29, reserved
+//Bit 28:16, reg_frm_height the frame height size
+//Bit 15:13, reserved
+//Bit 12: 0, reg_frm_width the frame width size
+
+ #define FITLER_CFG_REG 0x206 // default 32'h0
+//Bit 31: 5, reserved
+//Bit 4: 4, inteleav_mod horizontal interleave filter(zero-padding) for 3D considerations 0:using non-zero padding lpf 1:using zero-padding lpf
+//Bit 3: 2, lpf_slt_uv apply cm on lp portion or original video pixels options
+//Bit 1: 0, lpf_slt_y apply cm on lp portion or original video pixels options
+
+ #define CM_GLOBAL_GAIN_REG 0x207 // default 32'h0
+//Bit 31:28, reserved
+//Bit 27:16, cm2_global_sat global saturation gain for general color adjustments(0~4095 <=> 0~8),512 normalized to "1"
+//Bit 15:12, reserved
+//Bit 11: 0, cm2_global_hue global hue offsets for general color adjustments(0~4095 <=> 0~360 degree)
+
+ #define CM_ENH_CTL_REG 0x208 // default 32'h0
+//Bit 31:7, reserved
+//Bit 6, hue_adj_en cm2 hue adjustments
+//Bit 5, sat_adj_en cm2 saturation adjustments
+//Bit 4, luma_adj_en enable siganl for cm2 luma adjustments
+//Bit 3, reserved
+//Bit 2, cm2_filt_en apply cm on lp portion enable
+//Bit 1, cm2_en cm2 enable siganl
+//Bit 0, cm1_en
+
+ #define ROI_X_SCOPE_REG 0x209 // default 32'h0
+//Bit 31:29, reserved
+//Bit 28:16, roi_x_end ending col index of the region of interest
+//Bit 15:13, reserved
+//Bit 12: 0, roi_x_beg start col index of the region of interest
+
+ #define ROI_Y_SCOPE_REG 0x20a // default 32'h0
+//Bit 31:29, reserved
+//Bit 28:16, roi_y_end ending row index of the region of interest
+//Bit 15:13, reserved
+//Bit 12: 0, roi_y_beg start row index of the region of interest
+
+ #define POI_XY_DIR_REG 0x20b // default 32'h0
+//Bit 31:29, reserved
+//Bit 28:16, poi_y_dir ending row index of the region of interest
+//Bit 15:13, reserved
+//Bit 12: 0, poi_x_dir start row index of the region of interest
+
+ #define COI_Y_SCOPE_REG 0x20c // default 32'h0
+//Bit 31:16, reserved
+//Bit 15: 8, coi_y_end
+//Bit 7: 0, coi_y_beg
+
+ #define COI_H_SCOPE_REG 0x20d // default 32'h0
+//Bit 31:28, reserved
+//Bit 27:16, coi_h_end
+//Bit 15:12, reserved
+//Bit 11: 0, coi_h_beg lower bound of hue value for color of interest ,12 bits precision
+
+ #define COI_S_SCOPE_REG 0x20e // default 32'h0
+//Bit 31:28, reserved
+//Bit 27:16, coi_s_end
+//Bit 15:12, reserved
+//Bit 11: 0, coi_s_beg lower bound of sat value for color of interest ,12 bits precision
+ #define IFO_MODE_REG 0x20f // default 32'h0
+//Bit 31:8, reserved
+//Bit 7:6, ifo_mode3
+//Bit 5:4, ifo_mode2
+//Bit 3:2, ifo_mode1
+//Bit 1:0, ifo_mode0
+ #define POI_RPL_MODE_REG 0x210 // default 32'h0
+//Bit 31:4, reserved
+//Bit 3:0, poi_rpl_mode enhance mode control of pixels inside and outside region of interest bit[3:2]control roi
+ #define DEMO_OWR_YHS_REG 0x211 // default 32'h0
+//Bit 31: 0, demo_owr_yhs
+
+ #define DEMO_POI_Y_REG 0x212 // default 32'h0
+//Bit 31: 8, reserved
+//Bit 7: 0, luma_data_poi_r only get locked higher 8bits
+ #define DEMO_POI_H_REG 0x213 // default 32'h0
+//Bit 31: 12, reserved
+//Bit 11: 0, hue_data_poi_r only get locked higher 12bits
+ #define DEMO_POI_S_REG 0x214 // default 32'h0
+//Bit 31: 12, reserved
+//Bit 11: 0, sat_data_poi_r only get locked higher 12bits
+ //`define LUMA_BYH_LIMT_REG 10'h215 // default 32'h0
+ #define LUMA_ADJ_LIMT_REG 0x215 // default 32'h0
+//Bit 31:24, reserved
+//Bit 23:16, luma_lmt_satslp slope to do the luma adjustment degrade
+//Bit 15:12, reserved
+//Bit 11:0, luma_lmt_satth threshold to saturation
+ #define SAT_ADJ_LIMT_REG 0x216 // default 32'h0
+//Bit 31:24, reserved
+//Bit 23:16, sat_lmt_satslp slope to do the adjustment degrade
+//Bit 15:12, reserved
+//Bit 11:0, sat_lmt_satth threshold to saturation
+ #define HUE_ADJ_LIMT_REG 0x217 // default 32'h0
+//Bit 31: 24, reserved
+//Bit 23: 16, hue_lmt_satslp slope to do the adjustment degrade
+//Bit 15: 12, reserved
+//Bit 11: 0, hue_lmt_satth threshold to saturation
+ #define UVHS_OFST_REG 0x218 // default 32'h0
+//Bit 31: 24, hs2uv_v_ofst
+//Bit 23: 16, hs2uv_u_ofst
+//Bit 15: 8, uv2hs_v_ofst
+//Bit 7: 0, uv2hs_u_ofst
+ #define HUE_CFG_PARA_REG 0x219 // default 32'h0
+//Bit 31: 17, reserved
+//Bit 16, hue_protect_en
+//Bit 15: 13, cm2_hue_byhs_mode
+//Bit 12, cm2_hue_div_mode
+//Bit 11: 0, cm2_before_hue_ofst
+ #define DEMO_SPLT_CFG_REG 0x21a // default 32'h0
+//Bit 31: 22, reserved
+//Bit 21: 20, demo_split_mode
+//Bit 19: 16, demo_split_width slope to do the adjustment degrade
+//Bit 15: 13, reserved
+//Bit 12: 0, demo_split_post threshold to saturation
+ #define DEMO_SPLT_YHS_REG 0x21b // default 32'h0
+//Bit 31: 0, demo_splt_yhs threshold to saturation
+
+ #define XVYCC_YSCP_REG 0x21c // default 32'h0
+//Bit 31: 28, reserved
+//Bit 27: 16, xvycc_y_max
+//Bit 15: 12, reserved
+//Bit 11: 0, xvycc_y_min
+ #define XVYCC_USCP_REG 0x21d // default 32'h0
+//Bit 31: 28, reserved
+//Bit 27: 16, xvycc_u_max
+//Bit 15: 12, reserved
+//Bit 11: 0, xvycc_u_min
+ #define XVYCC_VSCP_REG 0x21e // default 32'h0
+//Bit 31: 28, reserved
+//Bit 27: 16, xvycc_v_max
+//Bit 15: 12, reserved
+//Bit 11: 0, xvycc_v_min
+ #define LUMA_ADJ0_REG 0x21f // default 32'h0
+//Bit 21: 12, reg_cm_luma_blacklevel
+//Bit 11: 0, reg_cm_luma_contrast
+ #define LUMA_ADJ1_REG 0x220 // default 32'h0
+
+ #define STA_WIN_XYXY0_REG 0x221 // default 32'h0
+ #define STA_WIN_XYXY1_REG 0x222 // default 32'h0
+ #define STA_CFG_REG 0x223 // default 32'h0
+ #define STA_SAT_HIST0_REG 0x224 // default 32'h0
+ #define STA_SAT_HIST1_REG 0x225 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN0 0x226 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN1 0x227 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN2 0x228 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN3 0x229 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN4 0x22a // default 32'h0
+ #define RO_CM_HUE_HIST_BIN5 0x22b // default 32'h0
+ #define RO_CM_HUE_HIST_BIN6 0x22c // default 32'h0
+ #define RO_CM_HUE_HIST_BIN7 0x22d // default 32'h0
+ #define RO_CM_HUE_HIST_BIN8 0x22e // default 32'h0
+ #define RO_CM_HUE_HIST_BIN9 0x22f // default 32'h0
+ #define RO_CM_HUE_HIST_BIN10 0x230 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN11 0x231 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN12 0x232 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN13 0x233 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN14 0x234 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN15 0x235 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN16 0x236 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN17 0x237 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN18 0x238 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN19 0x239 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN20 0x23a // default 32'h0
+ #define RO_CM_HUE_HIST_BIN21 0x23b // default 32'h0
+ #define RO_CM_HUE_HIST_BIN22 0x23c // default 32'h0
+ #define RO_CM_HUE_HIST_BIN23 0x23d // default 32'h0
+ #define RO_CM_HUE_HIST_BIN24 0x23e // default 32'h0
+ #define RO_CM_HUE_HIST_BIN25 0x23f // default 32'h0
+ #define RO_CM_HUE_HIST_BIN26 0x240 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN27 0x241 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN28 0x242 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN29 0x243 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN30 0x244 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN31 0x245 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN0 0x246 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN1 0x247 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN2 0x248 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN3 0x249 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN4 0x24a // default 32'h0
+ #define RO_CM_SAT_HIST_BIN5 0x24b // default 32'h0
+ #define RO_CM_SAT_HIST_BIN6 0x24c // default 32'h0
+ #define RO_CM_SAT_HIST_BIN7 0x24d // default 32'h0
+ #define RO_CM_SAT_HIST_BIN8 0x24e // default 32'h0
+ #define RO_CM_SAT_HIST_BIN9 0x24f // default 32'h0
+ #define RO_CM_SAT_HIST_BIN10 0x250 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN11 0x251 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN12 0x252 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN13 0x253 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN14 0x254 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN15 0x255 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN16 0x256 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN17 0x257 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN18 0x258 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN19 0x259 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN20 0x25a // default 32'h0
+ #define RO_CM_SAT_HIST_BIN21 0x25b // default 32'h0
+ #define RO_CM_SAT_HIST_BIN22 0x25c // default 32'h0
+ #define RO_CM_SAT_HIST_BIN23 0x25d // default 32'h0
+ #define RO_CM_SAT_HIST_BIN24 0x25e // default 32'h0
+ #define RO_CM_SAT_HIST_BIN25 0x25f // default 32'h0
+ #define RO_CM_SAT_HIST_BIN26 0x260 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN27 0x261 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN28 0x262 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN29 0x263 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN30 0x264 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN31 0x265 // default 32'h0
+ #define RO_CM_BLK_BIN 0x266 // default 32'h0
+ #define RO_CM_BRT_BIN 0x267 // default 32'h0
+
+////========= NODE 0 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H00 0x100 // default 32'H0
+//Bit 31: 24, reg_cm2_adj_sat_via_hs_2
+//Bit 23: 16, reg_cm2_adj_sat_via_hs_1
+//Bit 15: 8, reg_cm2_adj_sat_via_hs_0
+//Bit 7: 0, reg_cm2_adj_luma_via_h
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H00 0x101 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H00 0x102 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H00 0x103 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H00 0x104 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 1 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H01 0x108 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H01 0x109 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H01 0x10a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H01 0x10b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H01 0x10c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 2 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H02 0x110 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H02 0x111 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H02 0x112 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H02 0x113 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H02 0x114 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 3 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H03 0x118 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H03 0x119 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H03 0x11a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H03 0x11b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H03 0x11c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 4 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H04 0x120 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H04 0x121 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H04 0x122 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H04 0x123 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H04 0x124 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 5 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H05 0x128 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H05 0x129 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H05 0x12a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H05 0x12b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H05 0x12c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 6 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H06 0x130 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H06 0x131 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H06 0x132 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H06 0x133 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H06 0x134 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 7 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H07 0x138 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H07 0x139 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H07 0x13a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H07 0x13b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H07 0x13c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 8 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H08 0x140 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H08 0x141 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H08 0x142 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H08 0x143 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H08 0x144 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 9 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H09 0x148 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H09 0x149 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H09 0x14a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H09 0x14b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H09 0x14c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 10 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H10 0x150 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H10 0x151 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H10 0x152 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H10 0x153 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H10 0x154 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 11 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H11 0x158 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H11 0x159 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H11 0x15a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H11 0x15b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H11 0x15c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 12 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H12 0x160 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H12 0x161 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H12 0x162 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H12 0x163 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H12 0x164 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 13 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H13 0x168 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H13 0x169 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H13 0x16a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H13 0x16b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H13 0x16c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+
+/* Constraints
+0)
+ there are 16 regions totally. 8 regions are for hue adjustment, 8 regions are for sat adjustment.
+ the hue range of the 16 regions can be set to overlap, but if overlap, the hue range(start and end) must be same.
+ the 8 regions for hue adjustment should not overlap. if corresponding reg_hue_en_00 - 07 == 1
+ the 8 regions for hue adjustment are defined by: (example are for region 0)
+ a) hue:
+ start: reg_hue_hue_shift_start_00[14:0]
+ end:
+ if reg_symmetry_en_00 == 0
+ reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<5)
+ if reg_symmetry_en_00 == 1
+ reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<6)
+ b) sat:
+ start: reg_hue_sat_low_00
+ end: reg_hue_sat_high_00
+
+ the 8 regions for sat adjustment should not overlap. if corresponding reg_sat_en_00 - 07 == 1
+ the 8 regions for sat adjustment are defined by: (example are for region 0)
+ a) hue: same as that for hue adjustment.
+ start: reg_hue_hue_shift_start_00[14:0]
+ end:
+ if reg_symmetry_en_00 == 0
+ reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<5)
+ if reg_symmetry_en_00 == 1
+ reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<6)
+ b) sat:
+ start: reg_sat_sat_low_00
+ end: reg_sat_sat_high_00
+
+1)
+ reg_hue_hue_shift_range_00[7:0]:
+ reg_hue_hue_shift_range_01[7:0]:
+ reg_hue_hue_shift_range_02[7:0]:
+ reg_hue_hue_shift_range_03[7:0]:
+ reg_hue_hue_shift_range_04[7:0]:
+ reg_hue_hue_shift_range_05[7:0]:
+ reg_hue_hue_shift_range_06[7:0]:
+ reg_hue_hue_shift_range_07[7:0]:
+ must be greater or equal than 8'd8, so as reg_hue_range_inv_regxx can be represented by 0.0000_0000_xxxx_xxxx_xxxx_xxxx
+
+2)
+ all regions of 0-7 should meet below requirement. below is just an example for region 7.
+ (reg_hue_lum_high_07 - reg_hue_lum_low_07) >=
+ (1<<reg_hue_lum_low_slope_07) + (1<<reg_hue_lum_high_slope_07)
+
+ (reg_hue_sat_high_07 - reg_hue_sat_low_07) >=
+ (1<<reg_hue_sat_low_slope_07) + (1<<reg_hue_sat_high_slope_07)
+
+ (reg_sat_lum_high_07 - reg_sat_lum_low_07) >=
+ (1<<reg_sat_lum_low_slope_07) + (1<<reg_sat_lum_high_slope_07)
+
+ (reg_sat_sat_high_07 - reg_sat_sat_low_07) >=
+ (1<<reg_sat_sat_low_slope_07) + (1<<reg_sat_sat_high_slope_07)
+
+3)
+ all of reg_hue_hue_shift_start_00[14:0] ~ 07[14:0] < 0x6000.
+ only region 0 and 1 can exceed 360 degrees. ie:
+ reg_hue_hue_shift_start_00 + (reg_hue_hue_shift_range_00<<5) can greater than 0x6000.
+ reg_hue_hue_shift_start_01 + (reg_hue_hue_shift_range_01<<5) can greater than 0x6000.
+ but below should be met:
+ reg_hue_hue_shift_start_00 + (reg_hue_hue_shift_range_00<<5) < 0x8000. if reg_symmetry_en_00 == 0
+ reg_hue_hue_shift_start_01 + (reg_hue_hue_shift_range_00<<5) < 0x8000. if reg_symmetry_en_00 == 0
+ reg_hue_hue_shift_start_00 + (reg_hue_hue_shift_range_00<<6) < 0x8000. if reg_symmetry_en_00 == 1
+ reg_hue_hue_shift_start_01 + (reg_hue_hue_shift_range_00<<6) < 0x8000. if reg_symmetry_en_00 == 1
+
+ others could not exceed 360 degrees. ie:
+ reg_hue_hue_shift_start_02(to 7) + (reg_hue_hue_shift_range_02 (to 7) <<5) < 0x6000. if reg_symmetry_en_02 (to 7) == 0.
+ reg_hue_hue_shift_start_02(to 7) + (reg_hue_hue_shift_range_02 (to 7) <<6) < 0x6000. if reg_symmetry_en_02 (to 7) == 1.
+
+4)
+ reg_hue_gain_00[7:0] <= 0x80.
+ reg_hue_gain_01[7:0] <= 0x80.
+ reg_hue_gain_02[7:0] <= 0x80.
+ reg_hue_gain_03[7:0] <= 0x80.
+ reg_hue_gain_04[7:0] <= 0x80.
+ reg_hue_gain_05[7:0] <= 0x80.
+ reg_hue_gain_06[7:0] <= 0x80.
+ reg_hue_gain_07[7:0] <= 0x80.
+
+5)
+ below registers can only have two setting: 00 and 01.
+ reg_hue_central_en_00[1:0] .. _07[1:0]
+ reg_sat_central_en_00[1:0] .. _07[1:0]
+
+6)
+ all reg_..._slope_00-07 should not be greater than 7, ie: maximum value is 7.
+ for example: below is for region 0:
+ reg_hue_lum_low_slope_00[3:0] <= 7
+ reg_hue_lum_high_slope_00[3:0] <= 7
+ reg_hue_sat_low_slope_00[3:0] <= 7
+ reg_hue_sat_high_slope_00[3:0] <= 7
+ reg_sat_lum_low_slope_00[3:0] <= 7
+ reg_sat_lum_high_slope_00[3:0] <= 7
+ reg_sat_sat_low_slope_00[3:0] <= 7
+ reg_sat_sat_high_slope_00[3:0] <= 7
+*/
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: chroma_reg.h
+//
+//(hsvsharp), (blue), gainoff, mat_vd1,mat_vd2, mat_post, prebld, postbld,(hsharp),sco_ff, vadj1, vadj2, ofifo, (chroma1), clk0(free_clk) vpp_reg
+//each item 2bits, for each 2bits, if bit 2*i+1 == 1, free clk, else if bit 2*i == 1 no clk, else auto gated clock
+//bit1 is not used, because I can not turn off vpp_reg clk because I can not turn on again
+//because the register itself canot be set again without clk
+//Bit 31:0
+#define VPP_GCLK_CTRL0 ((0x1d72 << 2) + 0xff000000)
+//(front_lti), (front_cti), Chroma2_filter, Chroma2, (Ccoring), (blackext), dnlp
+//Bit 13:0
+#define VPP_GCLK_CTRL1 ((0x1d73 << 2) + 0xff000000)
+//prehsc_clk, line_buf, prevsc, vsc, hsc_clk, clk0(free_clk)
+//Bit 11:0
+#define VPP_SC_GCLK_CTRL ((0x1d74 << 2) + 0xff000000)
+//Bit 17:9 VD1 alpha for preblend
+//Bit 8:0 VD1 alpha for postblend
+#define VPP_MISC1 ((0x1d76 << 2) + 0xff000000)
+//Bit 31:0 super scalar clock control
+#define VPP_SRSCL_GCLK_CTRL ((0x1d77 << 2) + 0xff000000)
+//Bit 31:0 OSD super scalar clock control
+#define VPP_OSDSR_GCLK_CTRL ((0x1d78 << 2) + 0xff000000)
+//Bit 31:0 vvycc clock control
+#define VPP_XVYCC_GCLK_CTRL ((0x1d79 << 2) + 0xff000000)
+//Bit 31:24 blackext_start
+//Bit 23:16 blackext_slope1
+//Bit 15:8 blackext_midpt
+//Bit 7:0 blackext_slope2
+#define VPP_BLACKEXT_CTRL ((0x1d80 << 2) + 0xff000000)
+//Bit 31:24 bottom of region03 output value
+//Bit 23:16 bottom of region02 output value
+//Bit 15:8 bottom of region01 output value
+//Bit 7:0 bottom of region00 output value
+#define VPP_DNLP_CTRL_00 ((0x1d81 << 2) + 0xff000000)
+//Bit 31:24 bottom of region07 output value
+//Bit 23:16 bottom of region06 output value
+//Bit 15:8 bottom of region05 output value
+//Bit 7:0 bottom of region04 output value
+#define VPP_DNLP_CTRL_01 ((0x1d82 << 2) + 0xff000000)
+//Bit 31:24 bottom of region11 output value
+//Bit 23:16 bottom of region10 output value
+//Bit 15:8 bottom of region09 output value
+//Bit 7:0 bottom of region08 output value
+#define VPP_DNLP_CTRL_02 ((0x1d83 << 2) + 0xff000000)
+//Bit 31:24 bottom of region15 output value
+//Bit 23:16 bottom of region14 output value
+//Bit 15:8 bottom of region13 output value
+//Bit 7:0 bottom of region12 output value
+#define VPP_DNLP_CTRL_03 ((0x1d84 << 2) + 0xff000000)
+//Bit 31:24 bottom of region19 output value
+//Bit 23:16 bottom of region18 output value
+//Bit 15:8 bottom of region17 output value
+//Bit 7:0 bottom of region16 output value
+#define VPP_DNLP_CTRL_04 ((0x1d85 << 2) + 0xff000000)
+//Bit 31:24 bottom of region23 output value
+//Bit 23:16 bottom of region22 output value
+//Bit 15:8 bottom of region21 output value
+//Bit 7:0 bottom of region20 output value
+#define VPP_DNLP_CTRL_05 ((0x1d86 << 2) + 0xff000000)
+//Bit 31:24 bottom of region27 output value
+//Bit 23:16 bottom of region26 output value
+//Bit 15:8 bottom of region25 output value
+//Bit 7:0 bottom of region24 output value
+#define VPP_DNLP_CTRL_06 ((0x1d87 << 2) + 0xff000000)
+//Bit 31:24 bottom of region31 output value
+//Bit 23:16 bottom of region30 output value
+//Bit 15:8 bottom of region29 output value
+//Bit 7:0 bottom of region28 output value
+#define VPP_DNLP_CTRL_07 ((0x1d88 << 2) + 0xff000000)
+//Bit 31:24 bottom of region35 output value
+//Bit 23:16 bottom of region34 output value
+//Bit 15:8 bottom of region33 output value
+//Bit 7:0 bottom of region32 output value
+#define VPP_DNLP_CTRL_08 ((0x1d89 << 2) + 0xff000000)
+//Bit 31:24 bottom of region39 output value
+//Bit 23:16 bottom of region38 output value
+//Bit 15:8 bottom of region37 output value
+//Bit 7:0 bottom of region36 output value
+#define VPP_DNLP_CTRL_09 ((0x1d8a << 2) + 0xff000000)
+//Bit 31:24 bottom of region43 output value
+//Bit 23:16 bottom of region42 output value
+//Bit 15:8 bottom of region41 output value
+//Bit 7:0 bottom of region40 output value
+#define VPP_DNLP_CTRL_10 ((0x1d8b << 2) + 0xff000000)
+//Bit 31:24 bottom of region47 output value
+//Bit 23:16 bottom of region46 output value
+//Bit 15:8 bottom of region45 output value
+//Bit 7:0 bottom of region44 output value
+#define VPP_DNLP_CTRL_11 ((0x1d8c << 2) + 0xff000000)
+//Bit 31:24 bottom of region51 output value
+//Bit 23:16 bottom of region50 output value
+//Bit 15:8 bottom of region49 output value
+//Bit 7:0 bottom of region48 output value
+#define VPP_DNLP_CTRL_12 ((0x1d8d << 2) + 0xff000000)
+//Bit 31:24 bottom of region55 output value
+//Bit 23:16 bottom of region54 output value
+//Bit 15:8 bottom of region53 output value
+//Bit 7:0 bottom of region52 output value
+#define VPP_DNLP_CTRL_13 ((0x1d8e << 2) + 0xff000000)
+//Bit 31:24 bottom of region59 output value
+//Bit 23:16 bottom of region58 output value
+//Bit 15:8 bottom of region57 output value
+//Bit 7:0 bottom of region56 output value
+#define VPP_DNLP_CTRL_14 ((0x1d8f << 2) + 0xff000000)
+//Bit 31:24 bottom of region63 output value
+//Bit 23:16 bottom of region62 output value
+//Bit 15:8 bottom of region61 output value
+//Bit 7:0 bottom of region60 output value
+#define VPP_DNLP_CTRL_15 ((0x1d90 << 2) + 0xff000000)
+// `define VPP_PEAKING_HGAIN 8'h91 //32'h0
+// `define VPP_PEAKING_VGAIN 8'h92 //32'h0
+// `define VPP_PEAKING_NLP_1 8'h93 //32'h0
+// `define VPP_PEAKING_NLP_2 8'h94 //32'h0
+// `define VPP_PEAKING_NLP_3 8'h95 //32'h0
+// `define VPP_PEAKING_NLP_4 8'h96 //32'h0
+// `define VPP_PEAKING_NLP_5 8'h97 //32'h0
+// `define VPP_SHARP_LIMIT 8'h98 //32'h0
+// `define VPP_VLTI_CTRL 8'h99 //32'h0
+// `define VPP_HLTI_CTRL 8'h9a //32'h0
+// `define VPP_CTI_CTRL 8'h9b //32'h0
+#define VPP_SRSHARP0_CTRL ((0x1d91 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 srsharp_demo_split_sz srsharp demo top/bot left/right width
+//Bit 15:6 reserved
+//Bit 5:4 srsharp_demo_disp_post srsharp demo display postion
+//Bit 3 srsharp_demo_en srsharp demo enable
+//Bit 2 srsharp_c444to422_en srsharp format444 convert 422 enable
+//Bit 1, srsharp_buf_en srsharp buffer enable
+//Bit 0, srsharp_en srsharp enable
+#define VPP_SRSHARP1_CTRL ((0x1d92 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 srsharp_demo_split_sz srsharp demo top/bot left/right width
+//Bit 15:6 reserved
+//Bit 5:4 srsharp_demo_disp_post srsharp demo display postion
+//Bit 3 srsharp_demo_en srsharp demo enable
+//Bit 2 srsharp_c444to422_en srsharp format444 convert 422 enable
+//Bit 1, srsharp_buf_en srsharp buffer enable
+//Bit 0, srsharp_en srsharp enable
+#define VPP_DOLBY_CTRL ((0x1d93 << 2) + 0xff000000)
+//todo
+#define VPP_DAT_CONV_PARA0 ((0x1d94 << 2) + 0xff000000)
+#define VPP_DAT_CONV_PARA1 ((0x1d95 << 2) + 0xff000000)
+//todo
+#define VPP_SYNC_SEL0 ((0x1d96 << 2) + 0xff000000)
+//`define VPP_VADJ1_BLACK_VAL 8'h97 //32'h0
+//`define VPP_VADJ2_BLACK_VAL 8'h98 //32'h0
+//Bit 29 blue_stretch_cb_inc
+//Bit 28 blue_stretch_cr_inc
+//Bit 27 the MSB of blue_stretch_error_crp_inv[11:0]
+//Bit 26 the MSB of blue_stretch_error_crn_inv[11:0]
+//Bit 25 the MSB of blue_stretch_error_cbp_inv[11:0]
+//Bit 24 the MSB of blue_stretch_error_cbn_inv[11:0]
+//Bit 23:16 blue_stretch_gain
+//Bit 15:8 blue_stretch_gain_cb4cr
+//Bit 7:0 blue_stretch_luma_high
+#define VPP_BLUE_STRETCH_1 ((0x1d9c << 2) + 0xff000000)
+//Bit 31:27 blue_stretch_error_crp
+//Bit 26:16 the 11 LSB of blue_stretch_error_crp_inv[11:0]
+//Bit 15:11 blue_stretch_error_crn
+//Bit 10:0 the 11 LSB of blue_stretch_error_crn_inv[11:0]
+#define VPP_BLUE_STRETCH_2 ((0x1d9d << 2) + 0xff000000)
+//Bit 31:27 blue_stretch_error_cbp
+//Bit 26:16 the 11 LSB of blue_stretch_error_cbp_inv[11:0]
+//Bit 15:11 blue_stretch_error_cbn
+//Bit 10:0 the 11 LSB of blue_stretch_error_cbn_inv[11:0]
+#define VPP_BLUE_STRETCH_3 ((0x1d9e << 2) + 0xff000000)
+#define VPP_CCORING_CTRL ((0x1da0 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_bypass_ccoring_ythd // unsigned , default = 0 bypass_ccoring_ythd
+//Bit 15:8 ccoring_th // unsigned , default = 0 Chroma coring threshold
+//Bit 7:0 reserved
+//Bit 3:0 ccoring_slope // unsigned , default = 0 Chroma coring slope
+#define VPP_VE_ENABLE_CTRL ((0x1da1 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20 demo_ccoring_enable // unsigned , default = 0 demo chroma coring enable
+//Bit 19 demo_blackext_enable // unsigned , default = 0 demo black enxtension enable
+//Bit 18 demo_dnlp_enable // unsigned , default = 0 demo dynamic nonlinear luma processing enable
+//Bit 17 demo_hsvsharp_enable // unsigned , default = 0 demo hsvsharp enable
+//Bit 16 demo_bluestretch_enable // unsigned , default = 0 demo bluestretch enable
+//Bit 15:14 demo_disp_position // unsigned , default = 0 2'b00: demo adjust on top, 2'b01: demo adjust on bottom, 2'b10: demo adjust on left, 2'b11: demo adjust on right
+//Bit 13:7 reserved
+//Bit 6 sr4c0_path_sel // unsigned , default = 0
+//Bit 5 srscl_path_sel // unsigned , default = 0
+//Bit 4 ccoring_en // unsigned , default = 0 chroma coring enable
+//Bit 3 blackext_en // unsigned , default = 0 black enxtension enable
+//Bit 2 dnlp_en // unsigned , default = 0 dynamic nonlinear luma processing enable
+//Bit 1 hsvsharp_en // unsigned , default = 0 hsvsharp enable
+//Bit 0 blue_stretch_en // unsigned , default = 0 bluestretch enable
+#define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH ((0x1da2 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 ve_demo_left_top_screen_width // unsigned , default = 0 demo left or top screen width
+#define VPP_VE_DEMO_CENTER_BAR ((0x1da3 << 2) + 0xff000000)
+ //Bit 31 ve_demo_center_bar // unsigned , default = 0 center bar enable
+ //Bit 27:24 ve_demo_center_bar // unsigned , default = 0 center bar width (*2)
+ //Bit 23:16 ve_demo_center_bar // unsigned , default = 0 center bar Cr (*4)
+ //Bit 15:8 ve_demo_center_bar // unsigned , default = 0 center bar Cb (*4)
+ //Bit 7:0 ve_demo_center_bar // unsigned , default = 0 center bar y (*4)
+#define VPP_VE_H_V_SIZE ((0x1da4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 ve_line_length // unsigned , default = 780 ve_line_length
+//Bit 15:13 reserved
+//Bit 12:0 ve_pic_height // unsigned , default = 438 ve_pic_height
+#define VPP_OUT_H_V_SIZE ((0x1da5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 vppout_line_length / unsigned , default = 780 vppout_line_length
+//Bit 15:13 reserved
+//Bit 12:0 vppout_pic_height // unsigned , default = 438 vppout_pic_height
+#define VPP_IN_H_V_SIZE ((0x1da6 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 vppin_line_length / unsigned , default = 780 vppout_line_length
+//Bit 15:13 reserved
+//Bit 12:0 vppin_pic_height // unsigned , default = 438 vppout_pic_height
+#define VPP_VDO_MEAS_CTRL ((0x1da8 << 2) + 0xff000000)
+//Bit 31:11 reserved
+//Bit 10:0 vdo_meas_ctrl // unsigned , default = 0 vdo_meas_ctrl
+//Read only
+//19:16 ind_meas_count_n, every number of sync_span vsyncs, this counter add 1
+//15:0, high bit portion of counter
+#define VPP_VDO_MEAS_VS_COUNT_HI ((0x1da9 << 2) + 0xff000000)
+//Read only
+//31:0, low bit portion of counter
+#define VPP_VDO_MEAS_VS_COUNT_LO ((0x1daa << 2) + 0xff000000)
+//bit 11:9 vd2_sel, 001: select vd1_din, 010: select vd2_din, 011: select d2d3_l_din, 100: d2d3_r_din, otherwise no selection
+//bit 8:6 vd1_l_sel, 001: select vd1_din, 010: select vd2_din, 011: select d2d3_l_din, 100: d2d3_r_din, otherwise no selection
+//bit 5:3 vd1_r_sel, 001: select vd1_din, 010: select vd2_din, 011: select d2d3_l_din, 100: d2d3_r_din, otherwise no selection
+//note: the source vd1_l_sel selected cannot be used as the source of vd1_r_sel or vd2_sel
+// vd1_r_sel is useful only vd1_interleave_mode is not 00. And the source vd1_r_sel used can not used for the vd2_sel any more.
+//bit 2:0 vd1_interleave_mode, 000: no interleave, 001: pixel interleaving, 010: line interleaving, 011: 2 pixel interleaving,
+// 100: 2 line interleaving
+#define VPP_INPUT_CTRL ((0x1dab << 2) + 0xff000000)
+//bit 25:24 cti_bpf_sel
+//bit 20:16 cti_blend_factor_gama
+//bit 12:8 cti_blend_factor_beta
+//bit 4:0 cti_blend_factor_alpha
+#define VPP_CTI_CTRL2 ((0x1dac << 2) + 0xff000000)
+// `define VPP_PEAKING_SAT_THD1 8'had
+// `define VPP_PEAKING_SAT_THD2 8'hae
+// `define VPP_PEAKING_SAT_THD3 8'haf
+// `define VPP_PEAKING_SAT_THD4 8'hb0
+// `define VPP_PEAKING_SAT_THD5 8'hb1
+// `define VPP_PEAKING_SAT_THD6 8'hb2
+// `define VPP_PEAKING_SAT_THD7 8'hb3
+// `define VPP_PEAKING_SAT_THD8 8'hb4
+// `define VPP_PEAKING_SAT_THD9 8'hb5
+// `define VPP_PEAKING_GAIN_ADD1 8'hb6
+// `define VPP_PEAKING_GAIN_ADD2 8'hb7
+#define VPP_WRBAK_CTRL_SEC ((0x1dad << 2) + 0xff000000)
+#define VD1_BLEND_SRC_CTRL_SEC ((0x1dae << 2) + 0xff000000)
+#define VD2_BLEND_SRC_CTRL_SEC ((0x1daf << 2) + 0xff000000)
+#define OSD1_BLEND_SRC_CTRL_SEC ((0x1db0 << 2) + 0xff000000)
+#define OSD2_BLEND_SRC_CTRL_SEC ((0x1db1 << 2) + 0xff000000)
+//crc check , new add
+#define VPP_RO_CRCSUM ((0x1db2 << 2) + 0xff000000)
+#define VPP_CRC_CHK ((0x1db3 << 2) + 0xff000000)
+//bit 23:16 peaking_dnlp_gain, u5.3, DNLP effect
+//bit 15:8 peaking_factor
+//bit 5 peaking_dnlp_demo_en
+//bit 4 peaking_dnlp_en
+//bit 3:0 peaking_filter_sel
+#define VPP_PEAKING_DNLP ((0x1db8 << 2) + 0xff000000)
+//bit 24 sharp_demo_win_en
+//bit 23:12 sharp_demo_win_vend
+//bit 11:0 sharp_demo_win_vstart
+#define VPP_SHARP_DEMO_WIN_CTRL1 ((0x1db9 << 2) + 0xff000000)
+//bit 23:12 sharp_demo_win_hend
+//bit 11:0 sharp_demo_win_hstart
+#define VPP_SHARP_DEMO_WIN_CTRL2 ((0x1dba << 2) + 0xff000000)
+//Bit 31:24 front_hlti_neg_gain
+//Bit 23:16 front_hlti_pos_gain
+//Bit 15:8 front_hlti_threshold
+//Bit 7:0 front_hlti_blend_factor
+#define VPP_FRONT_HLTI_CTRL ((0x1dbb << 2) + 0xff000000)
+//Bit 31 front_enable, enable the front LTI&CTI before scaler
+//Bit 26:24 front_cti_step2
+//Bit 23:21 front_cti_step
+//Bit 20:16 front_cti_blend_factor
+//Bit 15 front_cti_median_mode
+//Bit 14:8 front_cti_threshold
+//Bit 7:0 front_cti_gain
+#define VPP_FRONT_CTI_CTRL ((0x1dbc << 2) + 0xff000000)
+//bit 29:28 front_hlti_step
+//bit 25:24 front_cti_bpf_sel
+//bit 20:16 front_cti_blend_factor_gama
+//bit 12:8 front_cti_blend_factor_beta
+//bit 4:0 front_cti_blend_factor_alpha
+#define VPP_FRONT_CTI_CTRL2 ((0x1dbd << 2) + 0xff000000)
+//vertical scaler phase step
+//Bit 27:0, 4.24 format
+#define VPP_OSD_VSC_PHASE_STEP ((0x1dc0 << 2) + 0xff000000)
+//Bit 31:16, botttom vertical scaler initial phase
+//Bit 15:0, top vertical scaler initial phase
+#define VPP_OSD_VSC_INI_PHASE ((0x1dc1 << 2) + 0xff000000)
+//Bit 24 osd vertical Scaler enable
+//Bit 23 osd_prog_interlace 0: current field is progressive, 1: current field is interlace
+//Bit 22:21 osd_vsc_double_line_mode, bit1, double input width and half input height, bit0, change line buffer becomes 2 lines
+//Bit 20 osd_vsc_phase0_always_en
+//Bit 19 osd_vsc_nearest_en
+//Bit 17:16 osd_vsc_bot_rpt_l0_num
+//Bit 14:11 osd_vsc_bot_ini_rcv_num
+//Bit 9:8 osd_vsc_top_rpt_l0_num
+//Bit 6:3 osd_vsc_top_ini_rcv_num
+//Bit 2:0 osd_vsc_bank_length
+#define VPP_OSD_VSC_CTRL0 ((0x1dc2 << 2) + 0xff000000)
+//horizontal scaler phase step
+//Bit 27:0, 4.24 format
+#define VPP_OSD_HSC_PHASE_STEP ((0x1dc3 << 2) + 0xff000000)
+//Bit 31:16, horizontal scaler initial phase1
+//Bit 15:0, horizontal scaler initial phase0
+#define VPP_OSD_HSC_INI_PHASE ((0x1dc4 << 2) + 0xff000000)
+//Bit 22 osd horizontal scaler enable
+//Bit 21 osd_hsc_double_pix_mode
+//Bit 20 osd_hsc_phase0_always_en
+//Bit 19 osd_hsc_nearest_en
+//Bit 17:16 osd_hsc_rpt_p0_num1
+//Bit 14:11 osd_hsc_ini_rcv_num1
+//Bit 9:8 osd_hsc_rpt_p0_num0
+//Bit 6:3 osd_hsc_ini_rcv_num0
+//Bit 2:0 osd_hsc_bank_length
+#define VPP_OSD_HSC_CTRL0 ((0x1dc5 << 2) + 0xff000000)
+//for 3D quincunx sub-sampling
+//bit 15:8 pattern, each patten 1 bit, from lsb -> msb
+//bit 6:4 pattern start
+//bit 2:0 pattern end
+#define VPP_OSD_HSC_INI_PAT_CTRL ((0x1dc6 << 2) + 0xff000000)
+//bit 31:24, componet 0
+//bit 23:16, component 1
+//bit 15:8, component 2
+//bit 7:0 component 3, alpha
+#define VPP_OSD_SC_DUMMY_DATA ((0x1dc7 << 2) + 0xff000000)
+//Bit 14 osc_sc_din_osd1_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 13 osc_sc_din_osd2_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 12 osc_sc_dout_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 12 osc_sc_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 11:4 default alpha for vd1 or vd2 if they are selected as the source
+//Bit 3 osd scaler path enable
+//Bit 1:0 osd_sc_sel, 00: select osd1 input, 01: select osd2 input, 10: select vd1 input, 11: select vd2 input after matrix
+#define VPP_OSD_SC_CTRL0 ((0x1dc8 << 2) + 0xff000000)
+//Bit 28:16 OSD scaler input width minus 1
+//Bit 12:0 OSD scaler input height minus 1
+#define VPP_OSD_SCI_WH_M1 ((0x1dc9 << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output horizontal start
+//Bit 12:0 OSD scaler output horizontal end
+#define VPP_OSD_SCO_H_START_END ((0x1dca << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output vertical start
+//Bit 12:0 OSD scaler output vertical end
+#define VPP_OSD_SCO_V_START_END ((0x1dcb << 2) + 0xff000000)
+//Because there are many coefficients used in the vertical filter and horizontal filters,
+//indirect access the coefficients of vertical filter and horizontal filter is used.
+//For vertical filter, there are 33x4 coefficients
+//For horizontal filter, there are 33x4 coefficients
+//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
+//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
+//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
+//Bit 8 type of index, 0: vertical coef, 1: horizontal coef
+//Bit 6:0 coef index
+#define VPP_OSD_SCALE_COEF_IDX ((0x1dcc << 2) + 0xff000000)
+//coefficients for vertical filter and horizontal filter
+#define VPP_OSD_SCALE_COEF ((0x1dcd << 2) + 0xff000000)
+//Bit 12:0 line number use to generate interrupt when line == this number
+#define VPP_INT_LINE_NUM ((0x1dce << 2) + 0xff000000)
+#define VPP_XVYCC_MISC ((0x1dcf << 2) + 0xff000000)
+// new add lti/cti in 120924
+//Bit 3: 0 //default== 0 reg_hlti_dn_flt_coe[0]
+//Bit 7: 4 //default== 0 reg_hlti_dn_flt_coe[1]
+//Bit 11: 8 //default== 0 reg_hlti_dn_flt_coe[2]
+//Bit 15:12 //default== 2 reg_hlti_dn_flt_coe[3]
+//Bit 19:16 //default== 4 reg_hlti_dn_flt_coe[4]
+//Bit 22:20 //default== 3 reg_hlti_dn_flt_nrm u3: 3~7
+#define VPP_HLTI_DN_FLT ((0x1dd0 << 2) + 0xff000000)
+//Bit 7: 0 //default== 8 reg_hlti_bst_gain u8, norm 16 as "1"
+//Bit 15: 8 //default== 20 reg_hlti_bst_core u8, norm 32 as "1"
+//Bit 23:16 //default== 32 reg_hlti_oob_gain u8, norm 32 as "1"
+//Bit 28:24 //default== 0 reg_hlti_oob_core u5
+#define VPP_HLTI_GAIN ((0x1dd1 << 2) + 0xff000000)
+//Bit 7: 0 //default== 2 reg_hlti_clp_ofst u8,
+//Bit 8 //default== 0 reg_hlti_clp_mode u1,
+//Bit 11: 9 //default== 1 reg_hlti_clp_wind u3,
+//Bit 14:12 //default== 1 reg_hlti_bst_fltr u3,
+//Bit 15 //default== 1 reg_hlti_enable u1,
+#define VPP_HLTI_PARA ((0x1dd2 << 2) + 0xff000000)
+//Bit 3: 0 //default== 0 reg_hcti_dn_flt_coe[0]
+//Bit 7: 4 //default== 0 reg_hcti_dn_flt_coe[1]
+//Bit 11: 8 //default== 1 reg_hcti_dn_flt_coe[2]
+//Bit 15:12 //default== 2 reg_hcti_dn_flt_coe[3]
+//Bit 19:16 //default== 2 reg_hcti_dn_flt_coe[4]
+//Bit 22:20 //default== 3 reg_hcti_dn_flt_nrm u3: 3~7
+#define VPP_HCTI_DN_FLT ((0x1dd3 << 2) + 0xff000000)
+//Bit 7: 0 //default== 48 reg_hcti_bst_gain u8, norm 16 as "1"
+//Bit15: 8 //default== 17 reg_hcti_bst_core u8, norm 32 as "1"
+//Bit23:16 //default== 16 reg_hcti_oob_gain u8, norm 32 as "1"
+//Bit28:24 //default== 0 reg_hcti_oob_core u5
+#define VPP_HCTI_GAIN ((0x1dd4 << 2) + 0xff000000)
+//Bit 7: 0 //default== 0 reg_hcti_clp_ofst u8,
+//Bit 8 //default== 1 reg_hcti_clp_mode u1,
+//Bit 11: 9 //default== 3 reg_hcti_clp_wind u3,
+//Bit 14:12 //default== 6 reg_hcti_bst_fltr u3,
+//Bit 15 //default== 1 reg_hcti_enable u1,
+#define VPP_HCTI_PARA ((0x1dd5 << 2) + 0xff000000)
+//Bit 7: 0 //default== 48 reg_vcti_bst_gain u8, normalize 16 as "1"
+//Bit 15: 8 //default== 10 reg_vcti_bst_core u8
+//Bit 19:16 //default== 10 reg_vcti_clp_ofst u4
+//Bit 20 //default== 1 reg_vcti_clp_wind u1, 0: wind 3, 1: wind5
+#define VPP_VCTI_PARA ((0x1dd6 << 2) + 0xff000000)
+//`define VPP_MATRIX_PROBE_COLOR1 8'hd7 //defined before
+//Bit 31 //default== 0, urgent fifo hold enable
+//Bit 28:12 //default== 0, urgent fifo hold line threshold
+//Bit 15 //default== 0, urgent_ctrl_en
+//Bit 14 //default== 0, urgent_wr, if true for write buffer
+//Bit 13 //default== 0, out_inv_en
+//Bit 12 //default == 0, urgent_ini_value
+//Bit 11:6 //default == 0, up_th up threshold
+//Bit 5:0 //default == 0, dn_th dn threshold
+#define VPP_OFIFO_URG_CTRL ((0x1dd8 << 2) + 0xff000000)
+#define VPP_CLIP_MISC0 ((0x1dd9 << 2) + 0xff000000)
+//Bit 29:20 // default == 1023, final clip r channel top
+//Bit 19:10 // default == 1023, final clip g channel top
+//Bit 9: 0 // default == 1023, final clip b channel top
+#define VPP_CLIP_MISC1 ((0x1dda << 2) + 0xff000000)
+//Bit 29:20 // default == 0, final clip r channel bottom
+//Bit 19:10 // default == 0, final clip g channel bottom
+//Bit 9: 0 // default == 0, final clip b channel bottom
+#define VPP_MATRIX_COEF13_14 ((0x1ddb << 2) + 0xff000000)
+//Bit 28:16 // default == 0, matrix coef13
+//Bit 12:0 // default == 0, matrix coef14
+#define VPP_MATRIX_COEF23_24 ((0x1ddc << 2) + 0xff000000)
+//Bit 28:16 // default == 0, matrix coef23
+//Bit 12:0 // default == 0, matrix coef24
+#define VPP_MATRIX_COEF15_25 ((0x1ddd << 2) + 0xff000000)
+//Bit 28:16 // default == 0, matrix coef15
+//Bit 12:0 // default == 0, matrix coef25
+#define VPP_MATRIX_CLIP ((0x1dde << 2) + 0xff000000)
+//Bit 7:5 // default == 0, mat rs
+//Bit 4:3 // default == 0, mat clmod
+//Bit 2:0 // default == 0, mat clip enable
+#define VPP_XVYCC_MISC0 ((0x1ddf << 2) + 0xff000000)
+//Bit 29:20 // default == 1023, xvycc clip r channel top
+//Bit 19:10 // default == 1023, xvycc clip g channel top
+//Bit 9: 0 // default == 1023, xvycc clip b channel top
+#define VPP_XVYCC_MISC1 ((0x1de0 << 2) + 0xff000000)
+//Bit 29:20 // default == 0, xvycc clip r channel bottom
+//Bit 19:10 // default == 0, xvycc clip g channel bottom
+//Bit 9: 0 // default == 0, xvycc clip b channel bottom
+#define VPP_VD1_CLIP_MISC0 ((0x1de1 << 2) + 0xff000000)
+//Bit 29:20 // default == 1023, vd1 clip r channel top
+//Bit 19:10 // default == 1023, vd1 clip g channel top
+//Bit 9: 0 // default == 1023, vd1 clip b channel top
+#define VPP_VD1_CLIP_MISC1 ((0x1de2 << 2) + 0xff000000)
+//Bit 29:20 // default == 0, vd1 clip r channel bottom
+//Bit 19:10 // default == 0, vd1 clip g channel bottom
+//Bit 9: 0 // default == 0, vd1 clip b channel bottom
+#define VPP_VD2_CLIP_MISC0 ((0x1de3 << 2) + 0xff000000)
+//Bit 29:20 // default == 1023, vd2 clip r channel top
+//Bit 19:10 // default == 1023, vd2 clip g channel top
+//Bit 9: 0 // default == 1023, vd2 clip b channel top
+#define VPP_VD2_CLIP_MISC1 ((0x1de4 << 2) + 0xff000000)
+//Bit 29:20 // default == 0, vd2 clip r channel bottom
+//Bit 19:10 // default == 0, vd2 clip g channel bottom
+//Bit 9: 0 // default == 0, vd2 clip b channel bottom
+#define VPP_VD2_HDR_IN_SIZE ((0x1df0 << 2) + 0xff000000)
+//Bit 31:16 // default == 0
+//Bit 15:0 // default == 0
+#define VPP_OSD1_IN_SIZE ((0x1df1 << 2) + 0xff000000)
+//Bit 31:16 // default == 0
+//Bit 15:0 // default == 0
+#define VPP_GCLK_CTRL2 ((0x1df2 << 2) + 0xff000000)
+//`define VPP_BLEND_SRC_SEL 8'hf3
+#define VD2_PPS_DUMMY_DATA ((0x1df4 << 2) + 0xff000000)
+#define VPP_OSD1_BLD_H_SCOPE ((0x1df5 << 2) + 0xff000000)
+#define VPP_OSD1_BLD_V_SCOPE ((0x1df6 << 2) + 0xff000000)
+#define VPP_OSD2_BLD_H_SCOPE ((0x1df7 << 2) + 0xff000000)
+#define VPP_OSD2_BLD_V_SCOPE ((0x1df8 << 2) + 0xff000000)
+#define VPP_WRBAK_CTRL ((0x1df9 << 2) + 0xff000000)
+#define VPP_SLEEP_CTRL ((0x1dfa << 2) + 0xff000000)
+#define VD1_BLEND_SRC_CTRL ((0x1dfb << 2) + 0xff000000)
+#define VD2_BLEND_SRC_CTRL ((0x1dfc << 2) + 0xff000000)
+#define OSD1_BLEND_SRC_CTRL ((0x1dfd << 2) + 0xff000000)
+#define OSD2_BLEND_SRC_CTRL ((0x1dfe << 2) + 0xff000000)
+#define VPP_OSD_SCALE_CTRL ((0x1dff << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_regs.h
+//
+//`include "v2regs.h"
+//
+// Reading file: viu2_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: VIU2_VCBUS_BASE = 0x1e
+// -----------------------------------------------
+//------------------------------------------------------------------------------
+// VIU2 top-level registers
+//------------------------------------------------------------------------------
+// Bit 0 RW, osd1_reset
+// Bit 1 RW, OSD1_reset
+// Bit 2 RW, vd1_reset
+// Bit 3 RW, vd1_fmt_reset
+// Bit 7 RW, vpp_reset
+#define VIU2_SW_RESET ((0x1e01 << 2) + 0xff000000)
+#define VIU2_SW_RESET0 ((0x1e02 << 2) + 0xff000000)
+// Bit 0 RW, software reset for mcvecrd_mif
+// Bit 1 RW, software reset for mcinfowr_mif
+// Bit 2 RW, software reset for mcinford_mif
+#define VIU2_SECURE_REG ((0x1e05 << 2) + 0xff000000)
+//bit 8 if true, vsync interrup is generate only field == 0
+//bit 7:0 fix_disable
+#define VIU2_MISC_CTRL0 ((0x1e06 << 2) + 0xff000000)
+#define VIU2_DATA_SEC_IN ((0x1e07 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// VPP2 top-level registers
+//------------------------------------------------------------------------------
+// Bit 31 vd1_bgosd_exchange_en for preblend
+// Bit 30 vd1_bgosd_exchange_en for postblend
+// bit 28 color management enable
+// Bit 27, reserved
+// Bit 26:18, reserved
+// Bit 17, OSD1 enable for preblend
+// Bit 16, osd1 enable for preblend
+// Bit 15, reserved
+// Bit 14, vd1 enable for preblend
+// Bit 13, OSD1 enable for postblend
+// Bit 12, osd1 enable for postblend
+// Bit 11, reserved
+// Bit 10, vd1 enable for postblend
+// Bit 9, if true, osd1 is alpha premultipiled
+// Bit 8, if true, OSD1 is alpha premultipiled
+// Bit 7, postblend module enable
+// Bit 6, preblend module enable
+// Bit 5, if true, OSD1 foreground compared with osd1 in preblend
+// Bit 4, if true, OSD1 foreground compared with osd1 in postblend
+// Bit 3,
+// Bit 2, if true, disable resetting async fifo every vsync, otherwise every vsync
+// the aync fifo will be reseted.
+// Bit 1,
+// Bit 0 if true, the output result of VPP is saturated
+#define VPP2_MISC ((0x1e26 << 2) + 0xff000000)
+//Bit 31:20 ofifo line length minus 1
+//Bit 19 if true invert input vs
+//Bit 18 if true invert input hs
+//Bit 17 force top/bottom field, enable
+//Bit 16 force top/bottom field, 0: top, 1: bottom
+//Bit 15 force one go_field, one pluse, write only
+//Bit 14 force one go_line, one pluse, write only
+//Bit 12:0 ofifo size (actually only bit 10:1 is valid), always even number
+#define VPP2_OFIFO_SIZE ((0x1e27 << 2) + 0xff000000)
+//Read only
+//Bit 28:17 current scale out fifo counter
+//Bit 16:12 current afifo counter
+//Bit 11:0 current ofifo counter
+#define VPP2_FIFO_STATUS ((0x1e28 << 2) + 0xff000000)
+//Bit 12:0 line number use to generate interrupt when line == this number
+#define VPP2_INT_LINE_NUM ((0x1e20 << 2) + 0xff000000)
+#define VPP2_OFIFO_URG_CTRL ((0x1e21 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// OSD1 registers
+//------------------------------------------------------------------------------
+// Bit 31 Reserved
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// 0=use gated clock for low power.
+// Bit 29 R, test_rd_dsr
+// Bit 28 R, osd_done
+// Bit 27:24 R, osd_blk_mode
+// Bit 23:22 R, osd_blk_ptr
+// Bit 21 R, osd_enable
+//
+// Bit 20:12 RW, global_alpha
+// Bit 11 RW, test_rd_en
+// Bit 10 RW, hl2_en
+// Bit 9 RW, hl1_en
+// Bit 8: 5 RW, ctrl_mtch_y
+// Bit 4 RW, ctrl_422to444
+// Bit 3: 0 RW, osd_blk_enable. Bit 0 to enable block 0: 1=enable, 0=disable;
+// Bit 1 to enable block 1, and so on.
+#define VIU2_OSD1_CTRL_STAT ((0x1e30 << 2) + 0xff000000)
+// Bit 31:26 Reserved
+// Bit 25:16 R, fifo_count
+// Bit 15: 6 Reserved
+// Bit 5: 4 RW, hold_fifo_lines[6:5]
+// Bit 3 RW, rgb2yuv_full_range
+// Bit 2 RW, alpha_9b_mode
+// Bit 1 RW, reserved
+// Bit 0 RW, color_expand_mode
+#define VIU2_OSD1_CTRL_STAT2 ((0x1e4d << 2) + 0xff000000)
+// Bit 31: 9 Reserved
+// Bit 8 RW, 0 = Write LUT, 1 = Read LUT
+// Bit 7: 0 RW, lut_addr
+#define VIU2_OSD1_COLOR_ADDR ((0x1e31 << 2) + 0xff000000)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define VIU2_OSD1_COLOR ((0x1e32 << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, hl[1-2]_h/v_start
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, hl[1-2]_h/v_end
+#define VIU2_OSD1_HL1_H_START_END ((0x1e33 << 2) + 0xff000000)
+#define VIU2_OSD1_HL1_V_START_END ((0x1e34 << 2) + 0xff000000)
+#define VIU2_OSD1_HL2_H_START_END ((0x1e35 << 2) + 0xff000000)
+#define VIU2_OSD1_HL2_V_START_END ((0x1e36 << 2) + 0xff000000)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define VIU2_OSD1_TCOLOR_AG0 ((0x1e37 << 2) + 0xff000000)
+#define VIU2_OSD1_TCOLOR_AG1 ((0x1e38 << 2) + 0xff000000)
+#define VIU2_OSD1_TCOLOR_AG2 ((0x1e39 << 2) + 0xff000000)
+#define VIU2_OSD1_TCOLOR_AG3 ((0x1e3a << 2) + 0xff000000)
+// Bit 31:24 Reserved
+// Bit 23:16 RW, tbl_addr
+// Bit 15 RW, little_endian: 0=big endian, 1=little endian
+// Bit 14 RW, rpt_y
+// Bit 13:12 RW, interp_ctrl. 0x=No interpolation; 10=Interpolate with previous
+// pixel; 11=Interpolate with the average value
+// between previous and next pixel.
+// Bit 11: 8 RW, osd_blk_mode
+// Bit 7 RW, rgb_en
+// Bit 6 RW, tc_alpha_en
+// Bit 5: 2 RW, color_matrix
+// Bit 1 RW, interlace_en
+// Bit 0 RW, interlace_sel_odd
+#define VIU2_OSD1_BLK0_CFG_W0 ((0x1e3b << 2) + 0xff000000)
+#define VIU2_OSD1_BLK1_CFG_W0 ((0x1e3f << 2) + 0xff000000)
+#define VIU2_OSD1_BLK2_CFG_W0 ((0x1e43 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK3_CFG_W0 ((0x1e47 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, x_end
+// Bit 15:13 Reserved
+// Bit 12: 0 RW, x_start
+#define VIU2_OSD1_BLK0_CFG_W1 ((0x1e3c << 2) + 0xff000000)
+#define VIU2_OSD1_BLK1_CFG_W1 ((0x1e40 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK2_CFG_W1 ((0x1e44 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK3_CFG_W1 ((0x1e48 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, y_end
+// Bit 15:13 Reserved
+// Bit 12: 0 RW, y_start
+#define VIU2_OSD1_BLK0_CFG_W2 ((0x1e3d << 2) + 0xff000000)
+#define VIU2_OSD1_BLK1_CFG_W2 ((0x1e41 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK2_CFG_W2 ((0x1e45 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK3_CFG_W2 ((0x1e49 << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, h_end
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, h_start
+#define VIU2_OSD1_BLK0_CFG_W3 ((0x1e3e << 2) + 0xff000000)
+#define VIU2_OSD1_BLK1_CFG_W3 ((0x1e42 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK2_CFG_W3 ((0x1e46 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK3_CFG_W3 ((0x1e4a << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, v_end
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, v_start
+#define VIU2_OSD1_BLK0_CFG_W4 ((0x1e64 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK1_CFG_W4 ((0x1e65 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK2_CFG_W4 ((0x1e66 << 2) + 0xff000000)
+#define VIU2_OSD1_BLK3_CFG_W4 ((0x1e67 << 2) + 0xff000000)
+// Bit 31 RW, burst_len_sel[2] of [2:0]
+// Bit 30 RW, byte_swap: In addition to endian control, further define
+// whether to swap upper and lower byte within a 16-bit mem word.
+// 0=No swap; 1=Swap data[15:0] to be {data[7:0], data[15:8]}
+// Bit 29 RW, div_swap : swap the 2 64bits words in 128 bit word
+// Bit 28:24 RW, fifo_lim : when osd fifo is small than the fifo_lim*16, closed the rq port of osd_rd_mif
+// Bit 23:22 RW, fifo_ctrl: 00 : for 1 word in 1 burst , 01 : for 2words in 1burst, 10: for 4words in 1burst, 11: reserved
+// Bit 21:20 R, fifo_st. 0=IDLE, 1=FILL, 2=ABORT
+// Bit 19 R, fifo_overflow
+// Bit 18:12 RW, fifo_depth_val, max value=64: set actual fifo depth to fifo_depth_val*8.
+// Bit 11:10 RW, burst_len_sel[1:0] of [2:0]. 0=24(default), 1=32, 2=48, 3=64, 4=96, 5=128.
+// Bit 9: 5 RW, hold_fifo_lines[4:0]
+// Bit 4 RW, clear_err: one pulse to clear fifo_overflow
+// Bit 3 RW, fifo_sync_rst
+// Bit 2: 1 RW, endian
+// Bit 0 RW, urgent
+#define VIU2_OSD1_FIFO_CTRL_STAT ((0x1e4b << 2) + 0xff000000)
+// Bit 31:24 R, Y or R
+// Bit 23:16 R, Cb or G
+// Bit 15: 8 R, Cr or B
+// Bit 7: 0 R, Output Alpha[8:1]
+#define VIU2_OSD1_TEST_RDDATA ((0x1e4c << 2) + 0xff000000)
+// Bit 15 RW, prot_en: 1=Borrow PROT's FIFO storage, either for rotate or non-rotate.
+// Bit 12: 0 RW, effective FIFO size when prot_en=1.
+#define VIU2_OSD1_PROT_CTRL ((0x1e4e << 2) + 0xff000000)
+#define VIU2_OSD1_MALI_UNPACK_CTRL ((0x1e4f << 2) + 0xff000000)
+#define VIU2_OSD1_DIMM_CTRL ((0x1e50 << 2) + 0xff000000)
+//`define VIU2_MATRIX_CTRL 8'h70
+#define VIU2_OSD1_MATRIX_COEF00_01 ((0x1e70 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_COEF02_10 ((0x1e71 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_COEF11_12 ((0x1e72 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_COEF20_21 ((0x1e73 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_COEF22 ((0x1e74 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_COEF13_14 ((0x1e75 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_COEF23_24 ((0x1e76 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_COEF15_25 ((0x1e77 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_CLIP ((0x1e78 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_OFFSET0_1 ((0x1e79 << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_OFFSET2 ((0x1e7a << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_PRE_OFFSET0_1 ((0x1e7b << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_PRE_OFFSET2 ((0x1e7c << 2) + 0xff000000)
+#define VIU2_OSD1_MATRIX_EN_CTRL ((0x1e7d << 2) + 0xff000000)
+#define VIU2_RMIF_CTRL0 ((0x1e80 << 2) + 0xff000000)
+#define VIU2_RMIF_CTRL1 ((0x1e81 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_sync_sel // unsigned , default = 0, axi canvas id sync with frm rst
+//Bit 23:16 reg_canvas_id // unsigned , default = 0, axi canvas id num
+//Bit 15 reserved
+//Bit 14:12 reg_cmd_intr_len // unsigned , default = 1, interrupt send cmd when how many series axi cmd,
+ // 0=12 1=16 2=24 3=32 4=40 5=48 6=56 7=64
+//Bit 11:10 reg_cmd_req_size // unsigned , default = 1, how many room fifo have, then axi send series req, 0=16 1=32 2=24 3=64
+//Bit 9:8 reg_burst_len // unsigned , default = 2, burst type: 0-single 1-bst2 2-bst4
+//Bit 7 reg_swap_64bit // unsigned , default = 0, 64bits of 128bit swap enable
+//Bit 6 reg_big_endian // unsigned , default = 0, big endian enable
+//Bit 5 reg_y_rev // unsigned , default = 0, vertical reverse enable
+//Bit 4 reg_x_rev // unsigned , default = 0, horizontal reverse enable
+//Bit 3 reserved
+//Bit 2:0 reg_pack_mode // unsigned , default = 1, 0:4bit 1:8bit 2:16bit 3:32bit 4:64bit 5:128bit
+#define VIU2_RMIF_CTRL2 ((0x1e82 << 2) + 0xff000000)
+//Bit 31 reg_sw_rst // unsigned , default = 0,
+//Bit 30:17 reserved
+//Bit 16:0 reg_urgent_ctrl // unsigned , default = 0, urgent control reg :
+ // 16 reg_ugt_init : urgent initial value
+ // 15 reg_ugt_en : urgent enable
+ // 14 reg_ugt_type : 1= wrmif 0=rdmif
+ // 7:4 reg_ugt_top_th: urgent top threshold
+ // 3:0 reg_ugt_bot_th: urgent bottom threshold
+#define VIU2_RMIF_SCOPE_X ((0x1e83 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_x_end // unsigned , default = 0, the canvas hor end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_x_start // unsigned , default = 0, the canvas hor start pixel position
+#define VIU2_RMIF_SCOPE_Y ((0x1e84 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_y_end // unsigned , default = 0, the canvas ver end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_y_start // unsigned , default = 0, the canvas ver start pixel positio
+#define VIU2_ROT_BLK_SIZE ((0x1e85 << 2) + 0xff000000)
+#define VIU2_ROT_LBUF_SIZE ((0x1e86 << 2) + 0xff000000)
+#define VIU2_ROT_FMT_CTRL ((0x1e87 << 2) + 0xff000000)
+#define VIU2_ROT_WIND_CTRL ((0x1e88 << 2) + 0xff000000)
+#define VIU2_ROT_OUT_VCROP ((0x1e89 << 2) + 0xff000000)
+#define VIU2_ROT_BUF_SIZE ((0x1e8a << 2) + 0xff000000)
+#define VIU2_ROT_RO_MIF0_STAT ((0x1e8b << 2) + 0xff000000)
+//Bit 15:0 reg_status // unsigned ,
+#define VIU2_ROT_RO_MIF1_STAT ((0x1e8c << 2) + 0xff000000)
+#define VIU2_ROT_RO_STAT ((0x1e8d << 2) + 0xff000000)
+#define VIU2_GAINOFF_GCLK_CTRL ((0x1ea0 << 2) + 0xff000000)
+#define VIU2_GAINOFF_CTRL0 ((0x1ea1 << 2) + 0xff000000)
+#define VIU2_GAINOFF_CTRL1 ((0x1ea2 << 2) + 0xff000000)
+#define VIU2_GAINOFF_CTRL2 ((0x1ea3 << 2) + 0xff000000)
+#define VIU2_GAINOFF_CTRL3 ((0x1ea4 << 2) + 0xff000000)
+#define VIU2_GAINOFF_CTRL4 ((0x1ea5 << 2) + 0xff000000)
+#define VPP2_CRC_CHK ((0x1eb0 << 2) + 0xff000000)
+#define VPP2_RO_CRCSUM ((0x1eb1 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: viu2_regs.h
+//
+//
+// Reading file: vregs_clk1.h
+//
+//===========================================================================
+// Video Interface Registers 0xa00 - 0xaff
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VIUB_VCBUS_BASE = 0x20
+// -----------------------------------------------
+#define VIUB_ADDR_START ((0x2000 << 2) + 0xff000000)
+#define VIUB_ADDR_END ((0x20ff << 2) + 0xff000000)
+//`define TRACE_REG 8'ff
+//------------------------------------------------------------------------------
+// VIU top-level registers
+//------------------------------------------------------------------------------
+// Bit 0 RW, osd1_reset
+// Bit 1 RW, osd2_reset
+// Bit 2 RW, vd1_reset
+// Bit 3 RW, vd1_fmt_reset
+// Bit 4 RW, vd2_reset
+// Bit 5 RW, vd2_fmt_reset
+// Bit 6 RW, di_dsr1to2_reset
+// Bit 7 RW, vpp_reset
+// Bit 8 RW, di_if1_reset
+// Bit 9 RW, di_if1_fmt_reset
+// Bit 10 RW, di_inp_reset
+// Bit 11 RW, di_inp_fmt_reset
+// Bit 12 RW, di_mem_reset
+// Bit 13 RW, di_mem_fmt_reset
+// Bit 14 RW, di_nr_wr_mif_reset
+// Bit 15 RW, dein_wr_mif_reset
+// Bit 16 RW, di_chan2_mif_reset
+// Bit 17 RW, di_mtn_wr_mif_reset
+// Bit 18 RW, di_mtn_rd_mif_reset
+// Bit 19 RW, di_mad_reset
+// Bit 20 RW, vdin0_reset
+// Bit 21 RW, vdin1_reset
+// Bit 22 RW, nrin_mux_reset
+// Bit 23 RW, vdin0_wr_reset
+// Bit 24 RW, vdin1_wr_reset
+// Bit 25 RW, reserved
+// Bit 26 RW, d2d3_reset
+// Bit 27 RW, di_cont_wr_mif_reset
+// Bit 28 RW, di_cont_rd_mif_reset
+#define VIUB_SW_RESET ((0x2001 << 2) + 0xff000000)
+#define VIUB_SW_RESET0 ((0x2002 << 2) + 0xff000000)
+// Bit 0 RW, software reset for mcvecrd_mif
+// Bit 1 RW, software reset for mcinfowr_mif
+// Bit 2 RW, software reset for mcinford_mif
+#define DI_AFBCE_CTRL ((0x2003 << 2) + 0xff000000)
+#define VIUB_SECURE_ST_RO ((0x2004 << 2) + 0xff000000)
+//bit 8 if true, vsync interrup is generate only field == 0
+//bit 7:0 fix_disable
+#define VIUB_MISC_CTRL0 ((0x2006 << 2) + 0xff000000)
+#define VIUB_GCLK_CTRL0 ((0x2007 << 2) + 0xff000000)
+//// gclk_ctrl0_gl[ 0] : def=1 di_top_wrap clk enable
+////
+//// gclk_ctrl0_gl[ 8] : def=0 mad pre clock enable, from mad clock
+//// gclk_ctrl0_gl[ 9] : def=0 mad post clock enable, from mad clock
+//// gclk_ctrl0_gl[10] : def=0 div clock enable, di slow clock including di&mcdi
+//// gclk_ctrl0_gl[11] : def=0 mcdi clock enable, from div clock
+//// gclk_ctrl0_gl[12] : def=0 di post clock enable, from div clock
+//// gclk_ctrl0_gl[13] : def=0 reserved
+//// gclk_ctrl0_gl[14] : def=1 di_no_clk_gate, for old di
+//// gclk_ctrl0_gl[15] : def=0 di_gate_all, for old di
+#define VIUB_GCLK_CTRL1 ((0x2008 << 2) + 0xff000000)
+//// gclk_ctrl1_gl[ 1: 0] : def=2'b00 mif-sub-arb clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[ 3: 2] : def=2'b00 if1 rdmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[ 5: 4] : def=2'b00 if2 rdmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[ 7: 6] : def=2'b00 de wrmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[ 9: 8] : def=2'b00 mtnrd post mif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[11:10] : def=2'b00 mcdi post mif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[17:16] : def=2'b00 inp rdmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[19:18] : def=2'b00 mem rdmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[21:20] : def=2'b00 chan rdmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[23:22] : def=2'b00 nr wrmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[25:24] : def=2'b00 mtn mif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[27:26] : def=2'b00 mcdi pre mif clock gate ctrl [1]: clock valid, [0]: clock close
+////
+#define VIUB_GCLK_CTRL2 ((0x2009 << 2) + 0xff000000)
+//// gclk_ctrl_pre[ 1: 0] : def=2'b00 nr clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_pre[ 3: 2] : def=2'b00 pd clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_pre[ 5: 4] : def=2'b00 mtn det clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_pre[ 7: 6] : def=2'b00 debanding clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_pre[ 9: 8] : def=2'b00 dnr clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_pre[11:10] : def=2'b00 nr&dnr blend clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_pre[13:12] : def=2'b00 mcdi clock gate ctrl [1]: clock valid, [0]: clock close
+#define VIUB_GCLK_CTRL3 ((0x200a << 2) + 0xff000000)
+//// gclk_ctrl_post[ 1: 0] : def=2'b00 di blend clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_post[ 3: 2] : def=2'b00 ei clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_post[ 5: 4] : def=2'b00 ei_0 clock gate ctrl [1]: clock valid, [0]: clock close
+#define DI_DBG_CTRL ((0x200b << 2) + 0xff000000)
+#define DI_DBG_CTRL1 ((0x200c << 2) + 0xff000000)
+#define DI_DBG_SRDY_INF ((0x200d << 2) + 0xff000000)
+#define DI_DBG_RRDY_INF ((0x200e << 2) + 0xff000000)
+#define VIUB_SECURE_REG ((0x200f << 2) + 0xff000000)
+#define DI_PRE_SEC_IN ((0x2010 << 2) + 0xff000000)
+#define DI_POST_SEC_IN ((0x2011 << 2) + 0xff000000)
+//`define DI_IF2_GEN_REG 8'h10
+//`define DI_IF2_CANVAS0 8'h11
+//`define DI_IF2_LUMA_X0 8'h12
+//`define DI_IF2_LUMA_Y0 8'h13
+//`define DI_IF2_CHROMA_X0 8'h14
+//`define DI_IF2_CHROMA_Y0 8'h15
+//`define DI_IF2_RPT_LOOP 8'h16
+//`define DI_IF2_LUMA0_RPT_PAT 8'h17
+//`define DI_IF2_CHROMA0_RPT_PAT 8'h18
+//`define DI_IF2_DUMMY_PIXEL 8'h19
+//`define DI_IF2_LUMA_FIFO_SIZE 8'h1a
+//`define DI_IF2_RANGE_MAP_Y 8'h1b
+//`define DI_IF2_RANGE_MAP_CB 8'h1c
+//`define DI_IF2_RANGE_MAP_CR 8'h1d
+//`define DI_IF2_GEN_REG2 8'h1e
+//`define DI_IF2_FMT_CTRL 8'h1f
+//`define DI_IF2_FMT_W 8'h20
+//
+//`define DI_IF2_URGENT_CTRL 8'h21
+//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path
+//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path
+//`define DI_IF2_GEN_REG3 8'h22
+//bit 31:1, reversed
+//bit 0, cntl_64bit_rev
+//==================================
+#define DI_EI_DRT_CTRL ((0x2028 << 2) + 0xff000000)
+//Bit 31, reg_rectg_en ;u1
+//Bit 30, reg_recbld_en ;u1
+//Bit 29:28, reg_rectg_ws ;u2
+//Bit 27, reserved
+//Bit 26:24, reg_abq_margin ;u3
+//Bit 23, reserved
+//Bit 22:20, reg_trend_mg ;u3
+//Bit 19:16, reg_int_d16xc1 ;u4
+//Bit 15:14, reserved
+//Bit 13: 8, reg_int_chlmt1 ;u6
+//Bit 7, reserved
+//Bit 6: 4, reg_nscheck_thrd ;u3
+//Bit 3, reserved
+//Bit 2: 0, reg_horsl_ws ;u3
+#define DI_EI_DRT_PIXTH ((0x2029 << 2) + 0xff000000)
+//Bit 31:24, reg_min_pix ;u8
+//Bit 23:16, reg_max_pix ;u8
+//Bit 15: 8, reg_dmaxmin_thrdma ;u8
+//Bit 7: 0, reg_dmaxmin_thrdmi ;u8
+#define DI_EI_DRT_CORRPIXTH ((0x202a << 2) + 0xff000000)
+//Bit 31:24, reg_newcorrpix_maxthrd ;u8
+//Bit 23:16, reg_corrpix_diffthrd ;u8
+//Bit 15: 8, reg_corrpix_minthrd ;u8
+//Bit 7: 0, reg_corrpix_maxthrd ;u8
+#define DI_EI_DRT_RECTG_WAVE ((0x202b << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_max_pixwave ;u5
+//Bit 23:21, reserved
+//Bit 20:16, reg_pix_wave ;u5
+//Bit 15:14, reserved
+//Bit 13: 8, reg_maxdrt_thrd ;u6
+//Bit 7: 0, reg_wave_thrd ;u8
+#define DI_EI_DRT_PIX_DIFFTH ((0x202c << 2) + 0xff000000)
+//Bit 31:24, reg_newraw_thrd ;u8
+//Bit 23:16, reg_tb_max_thrd ;u8
+//Bit 15: 8, reg_diffpix_thrd ;u8
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_bilt_trendnumt ;u8
+#define DI_EI_DRT_UNBITREND_TH ((0x202d << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_trend_numb ;u5
+//Bit 23:21, reserved
+//Bit 20:16, reg_bilt_trendnum ;u5
+//Bit 15:13, reserved
+//Bit 12: 8, reg_unil_trendnumt ;u5
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_trend_num ;u5
+//`define DI_IF0_GEN_REG 8'h30
+//`define DI_IF0_CANVAS0 8'h31
+//`define DI_IF0_LUMA_X0 8'h32
+//`define DI_IF0_LUMA_Y0 8'h33
+//`define DI_IF0_CHROMA_X0 8'h34
+//`define DI_IF0_CHROMA_Y0 8'h35
+//`define DI_IF0_RPT_LOOP 8'h36
+//`define DI_IF0_LUMA0_RPT_PAT 8'h37
+//`define DI_IF0_CHROMA0_RPT_PAT 8'h38
+//`define DI_IF0_DUMMY_PIXEL 8'h39
+//`define DI_IF0_LUMA_FIFO_SIZE 8'h3a
+//`define DI_IF0_RANGE_MAP_Y 8'h3b
+//`define DI_IF0_RANGE_MAP_CB 8'h3c
+//`define DI_IF0_RANGE_MAP_CR 8'h3d
+//`define DI_IF0_GEN_REG2 8'h3e
+//`define DI_IF0_FMT_CTRL 8'h3f
+//`define DI_IF0_FMT_W 8'h40
+//
+//`define DI_IF0_URGENT_CTRL 8'h41
+//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path
+//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path
+//`define DI_IF0_GEN_REG3 8'h42
+//bit 31:1, reversed
+//bit 0, cntl_64bit_rev
+// di arbtration :
+// the segment is 8'h50-8'h5f
+//
+// Reading file: di_arb_axi_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+//// reg
+////===============================////
+#define DI_RDARB_MODE_L1C1 ((0x2050 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, rdarb_sel uns, default = 0 ,
+// rdarb_sel[0]==0 slave dc0 connect master port0 rdarb_sel[0]==1 slave dc0 connect master port1
+// rdarb_sel[1]==0 slave dc1 connect master port0 rdarb_sel[1]==1 slave dc1 connect master port1
+// rdarb_sel[2]==0 slave dc2 connect master port0 rdarb_sel[2]==1 slave dc2 connect master port1
+// rdarb_sel[3]==0 slave dc3 connect master port0 rdarb_sel[3]==1 slave dc3 connect master port1
+// rdarb_sel[4]==0 slave dc4 connect master port0 rdarb_sel[4]==1 slave dc4 connect master port1
+// rdarb_sel[5]==0 slave dc5 connect master port0 rdarb_sel[5]==1 slave dc5 connect master port1
+//Bit 15:10, reserved
+//Bit 9:8, rdarb_arb_mode uns, default = 0 ,
+// rdarb_arb_mode[0] master port0 arb way,
+// rdarb_arb_mode[1] master port1 arb way,
+//Bit 7:4, reserved
+//Bit 3:0, rdarb_gate_clk_ctrl uns, default = 0 ,
+// rdarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// rdarb_gate_clk_ctrl[3:2] master port1 clk gate control
+#define DI_RDARB_REQEN_SLV_L1C1 ((0x2051 << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, rdarb_dc_req_en unsigned , default = 12'hfff
+// rdarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// rdarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// rdarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// rdarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// rdarb_dc_req_en[4]: the slv4 req to mst port0 enable,
+// rdarb_dc_req_en[5]: the slv5 req to mst port0 enable,
+// rdarb_dc_req_en[6]: the slv0 req to mst port1 enable,
+// rdarb_dc_req_en[7]: the slv1 req to mst port1 enable,
+// rdarb_dc_req_en[8]: the slv2 req to mst port1 enable,
+// rdarb_dc_req_en[9]: the slv3 req to mst port1 enable,
+// rdarb_dc_req_en[10]: the slv4 req to mst port1 enable,
+// rdarb_dc_req_en[11]: the slv5 req to mst port1 enable,
+#define DI_RDARB_WEIGH0_SLV_L1C1 ((0x2052 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// rddc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// rddc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// rddc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+// rddc_weigh_sxn[4*6+:6]: the slv4 req weigh number
+#define DI_RDARB_WEIGH1_SLV_L1C1 ((0x2053 << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[5*6+:6]: the slv5 req weigh number
+#define DI_WRARB_MODE_L1C1 ((0x2054 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, wrarb_sel uns, default = 0 ,
+// wrarb_sel[0]==0 slave dc0 connect master port0 wrarb_sel[0]==1 slave dc0 connect master port1
+// wrarb_sel[1]==0 slave dc1 connect master port0 wrarb_sel[1]==1 slave dc1 connect master port1
+// wrarb_sel[2]==0 slave dc2 connect master port0 wrarb_sel[2]==1 slave dc2 connect master port1
+// wrarb_sel[3]==0 slave dc3 connect master port0 wrarb_sel[3]==1 slave dc3 connect master port1
+// wrarb_sel[4]==0 slave dc4 connect master port0 wrarb_sel[4]==1 slave dc4 connect master port1
+// wrarb_sel[5]==0 slave dc5 connect master port0 wrarb_sel[5]==1 slave dc5 connect master port1
+//Bit 15:10, reserved
+//Bit 9:8, wrarb_arb_mode uns, default = 0 ,
+// wrarb_arb_mode[0] master port0 arb way,
+// wrarb_arb_mode[1] master port1 arb way,
+//Bit 7:4, reserved
+//Bit 3:0, wrarb_gate_clk_ctrl uns, default = 0 ,
+// wrarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// wrarb_gate_clk_ctrl[3:2] master port1 clk gate control
+#define DI_WRARB_REQEN_SLV_L1C1 ((0x2055 << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, wrarb_dc_req_en unsigned , default = 0
+// wrarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// wrarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// wrarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// wrarb_dc_req_en[4]: the slv4 req to mst port0 enable,
+// wrarb_dc_req_en[5]: the slv5 req to mst port0 enable,
+// wrarb_dc_req_en[0]: the slv0 req to mst port1 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port1 enable,
+// wrarb_dc_req_en[2]: the slv2 req to mst port1 enable,
+// wrarb_dc_req_en[3]: the slv3 req to mst port1 enable,
+// wrarb_dc_req_en[4]: the slv4 req to mst port1 enable,
+// wrarb_dc_req_en[5]: the slv5 req to mst port1 enable,
+#define DI_WRARB_WEIGH0_SLV_L1C1 ((0x2056 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// wrdc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// wrdc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+// wrdc_weigh_sxn[4*6+:6]: the slv4 req weigh number
+#define DI_WRARB_WEIGH1_SLV_L1C1 ((0x2057 << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[5*6+:6]: the slv5 req weigh number
+#define DI_RDWR_ARB_STATUS_L1C1 ((0x2058 << 2) + 0xff000000)
+//Bit 31:4, reserved
+//Bit 3:2, wrarb_arb_busy unsigned , default = 0
+//Bit 1:0, rdarb_arb_busy unsigned , default = 0
+#define DI_ARB_DBG_CTRL_L1C1 ((0x2059 << 2) + 0xff000000)
+#define DI_ARB_DBG_STAT_L1C1 ((0x205a << 2) + 0xff000000)
+#define DI_RDARB_UGT_L1C1 ((0x205b << 2) + 0xff000000)
+#define DI_RDARB_LIMT0_L1C1 ((0x205c << 2) + 0xff000000)
+#define DI_WRARB_UGT_L1C1 ((0x205d << 2) + 0xff000000)
+#define DI_ARB_AXIWR_PROT ((0x205e << 2) + 0xff000000)
+#define DI_ARB_AXIRD0_PROT ((0x205f << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: di_arb_axi_regs.h
+//
+// di afbc_enc
+// the segment is 8'h60-8'h8f
+//
+// Reading file: di_afbc_enc0_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DI_AFBCE_ENABLE ((0x2060 << 2) + 0xff000000)
+//Bit 31:20, gclk_ctrl unsigned , default = 0,
+//Bit 19:16, di_afbce_sync_sel unsigned , default = 0,
+//Bit 15:14, reserved
+//Bit 13, enc_rst_mode unsigned , default = 0,
+//Bit 12, enc_en_mode unsigned , default = 0,
+//Bit 11:9, reserved
+//Bit 8, enc_enable unsigned , default = 0,
+//Bit 7:1, reserved
+//Bit 0, reserved enc_frm_start pulse use this bit don't use
+#define DI_AFBCE_MODE ((0x2061 << 2) + 0xff000000)
+//Bit 31:29, soft_rst unsigned, default = 0 ,the use as go_field
+//Bit 28, reserved
+//Bit 27:26, rev_mode unsigned, default = 0 , reverse mode
+//Bit 25:24, mif_urgent unsigned, default = 3 , info mif and data mif urgent
+//Bit 23, reserved
+//Bit 22:16, hold_line_num unsigned, default = 4, 0: burst1 1:burst2 2:burst4
+//Bit 15:14, burst_mode unsigned, default = 1, 0: burst1 1:burst2 2:burst4
+//Bit 13:1, reserved
+//Bit 0, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb
+#define DI_AFBCE_SIZE_IN ((0x2062 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hsize_in unsigned, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_in unsigned, default = 1080 , pic vert size in unit: pixel
+#define DI_AFBCE_BLK_SIZE_IN ((0x2063 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hblk_size unsigned, default = 60 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vblk_size unsigned, default = 270, pic vert size in unit: pixel
+#define DI_AFBCE_HEAD_BADDR ((0x2064 << 2) + 0xff000000)
+//Bit 31:0, head_baddr unsigned, default = 32'h00;
+#define DI_AFBCE_MIF_SIZE ((0x2065 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:28, ddr_blk_size unsigned, default = 1;
+//Bit 27, reserved
+//Bit 26:24, cmd_blk_size unsigned, default = 3;
+//Bit 23:21, reserved
+//Bit 20:16, uncmp_size unsigned, default = 20;
+//Bit 15:0, mmu_page_size unsigned, default = 4096;
+#define DI_AFBCE_PIXEL_IN_HOR_SCOPE ((0x2066 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, enc_win_end_h unsigned, default = 1919 ; //
+//Bit 15:13, reserved
+//Bit 12:0, enc_win_bgn_h unsigned, default = 0 ; //
+#define DI_AFBCE_PIXEL_IN_VER_SCOPE ((0x2067 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, enc_win_end_v unsigned, default = 1079 ; //
+//Bit 15:13, reserved
+//Bit 12:0, enc_win_bgn_v unsigned, default = 0 ; //
+#define DI_AFBCE_CONV_CTRL ((0x2068 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, fmt_ybuf_depth unsigned, default = 2048
+//Bit 15:12, reserved
+//Bit 11: 0, lbuf_depth unsigned, default = 256, unit=16 pixel need to set = 2^n
+#define DI_AFBCE_MIF_HOR_SCOPE ((0x2069 << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, blk_end_h unsigned, default = 0 ; //
+//Bit 15:10, reserved
+//Bit 9:0, blk_bgn_h unsigned, default = 59 ; //
+#define DI_AFBCE_MIF_VER_SCOPE ((0x206a << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, blk_end_v unsigned, default = 0 ; //
+//Bit 15:12, reserved
+//Bit 11:0, blk_bgn_v unsigned, default = 269 ; //
+#define DI_AFBCE_STAT1 ((0x206b << 2) + 0xff000000)
+//Bit 31, ro_frm_end_pulse1 unsigned, RO,default = 0 ;frame end status
+//Bit 30:0, ro_dbg_top_info1 unsigned, RO,default = 0 ;
+#define DI_AFBCE_STAT2 ((0x206c << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30:0, ro_dbg_top_info2 unsigned, RO,default = 0 ;
+#define DI_AFBCE_FORMAT ((0x206d << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11:10 reserved
+//Bit 9: 8 reg_format_mode // unsigned , RW, default = 2 data format;0 : YUV444, 1:YUV422, 2:YUV420, 3:RGB
+//Bit 7: 4 reg_compbits_c // unsigned , RW, default = 10 chroma bitwidth
+//Bit 3: 0 reg_compbits_y // unsigned , RW, default = 10 luma bitwidth
+#define DI_AFBCE_MODE_EN ((0x206e << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 reserved
+//Bit 25 reg_adpt_interleave_ymode // unsigned , RW, default = 0 force 0 to disable it: no HW implementation
+//Bit 24 reg_adpt_interleave_cmode // unsigned , RW, default = 0 force 0 to disable it: not HW implementation
+//Bit 23 reg_adpt_yinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
+//Bit 22 reg_adpt_yinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
+//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
+//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
+//Bit 19 reserved
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 11 reserved
+//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
+//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
+//Bit 8 reg_uncompress_split_mode // unsigned , RW, default = 0 0: no split; 1: split
+//Bit 7: 6 reserved
+//Bit 5 reg_input_padding_uv128 // unsigned , RW, default = 0 input picture 32x4 block gap mode: 0: pad uv=0; 1: pad uv=128
+//Bit 4 reg_dwds_padding_uv128 // unsigned , RW, default = 0 downsampled image for double write 32x gap mode: 0: pad uv=0; 1: pad uv=128
+//Bit 3: 1 reg_force_order_mode_value // unsigned , RW, default = 0 force order mode 0~7
+//Bit 0 reg_force_order_mode_en // unsigned , RW, default = 0 force order mode enable: 0: no force; 1: forced to force_value
+#define DI_AFBCE_DWSCALAR ((0x206f << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7: 6 reg_dwscalar_w0 // unsigned , RW, default = 3 horizontal 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 5: 4 reg_dwscalar_w1 // unsigned , RW, default = 0 horizontal 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 3: 2 reg_dwscalar_h0 // unsigned , RW, default = 2 vertical 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 1: 0 reg_dwscalar_h1 // unsigned , RW, default = 3 vertical 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+#define DI_AFBCE_DEFCOLOR_1 ((0x2070 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_enc_defalutcolor_3 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr]
+//Bit 11: 0 reg_enc_defalutcolor_0 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr]
+#define DI_AFBCE_DEFCOLOR_2 ((0x2071 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_enc_defalutcolor_2 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr]
+//Bit 11: 0 reg_enc_defalutcolor_1 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr]
+#define DI_AFBCE_QUANT_ENABLE ((0x2072 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_quant_expand_en_1 // unsigned , RW, default = 0 enable for quantization value expansion
+//Bit 10 reg_quant_expand_en_0 // unsigned , RW, default = 0 enable for quantization value expansion
+//Bit 9: 8 reg_bcleav_ofst // signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1;
+//Bit 7: 5 reserved
+//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy
+//Bit 3: 1 reserved
+//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy
+#define DI_AFBCE_IQUANT_LUT_1 ((0x2073 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE_IQUANT_LUT_2 ((0x2074 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE_IQUANT_LUT_3 ((0x2075 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE_IQUANT_LUT_4 ((0x2076 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE_RQUANT_LUT_1 ((0x2077 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_rquant_yclut_0_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting)
+//Bit 27 reserved
+//Bit 26:24 reg_rquant_yclut_0_10 // unsigned , RW, default = 5
+//Bit 23 reserved
+//Bit 22:20 reg_rquant_yclut_0_9 // unsigned , RW, default = 4
+//Bit 19 reserved
+//Bit 18:16 reg_rquant_yclut_0_8 // unsigned , RW, default = 4
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_0_7 // unsigned , RW, default = 3
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_0_6 // unsigned , RW, default = 3
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_0_5 // unsigned , RW, default = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_0_4 // unsigned , RW, default = 2
+#define DI_AFBCE_RQUANT_LUT_2 ((0x2078 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_0_3 // unsigned , RW, default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_0_2 // unsigned , RW, default = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_0_1 // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_0_0 // unsigned , RW, default = 0
+#define DI_AFBCE_RQUANT_LUT_3 ((0x2079 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_rquant_yclut_1_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting)
+//Bit 27 reserved
+//Bit 26:24 reg_rquant_yclut_1_10 // unsigned , RW, default = 5
+//Bit 23 reserved
+//Bit 22:20 reg_rquant_yclut_1_9 // unsigned , RW, default = 4
+//Bit 19 reserved
+//Bit 18:16 reg_rquant_yclut_1_8 // unsigned , RW, default = 4
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_1_7 // unsigned , RW, default = 3
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_1_6 // unsigned , RW, default = 3
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_1_5 // unsigned , RW, default = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_1_4 // unsigned , RW, default = 2
+#define DI_AFBCE_RQUANT_LUT_4 ((0x207a << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_1_3 // unsigned , RW, default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_1_2 // unsigned , RW, default = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_1_1 // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_1_0 // unsigned , RW, default = 0
+#define DI_AFBCE_YUV_FORMAT_CONV_MODE ((0x207b << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7 reserved
+//Bit 6: 4 reg_444to422_mode // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_422to420_mode // unsigned , RW, default = 0
+#define DI_AFBCE_DUMMY_DATA ((0x207c << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29: 0 reg_dummy_data // unsigned , default = 0 ;
+#define DI_AFBCE_CLR_FLAG ((0x207d << 2) + 0xff000000)
+//Bit 31:0 reg_di_afbce_clr_flag // unsigned, default = 0 ;
+#define DI_AFBCE_STA_FLAGT ((0x207e << 2) + 0xff000000)
+//Bit 31:0 ro_di_afbce__sta_flag // unsigned, RO,default = 0 ;
+#define DI_AFBCE_MMU_NUM ((0x207f << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 0 ro_frm_mmu_num // unsigned, RO,default = 0 ;
+#define DI_AFBCE_MMU_RMIF_CTRL1 ((0x2080 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_sync_sel // unsigned , default = 0, axi canvas id sync with frm rst
+//Bit 23:16 reg_canvas_id // unsigned , default = 0, axi canvas id num
+//Bit 15 reserved
+//Bit 14:12 reg_cmd_intr_len // unsigned , default = 1, interrupt send cmd when how many series axi cmd,
+ // 0=12 1=16 2=24 3=32 4=40 5=48 6=56 7=64
+//Bit 11:10 reg_cmd_req_size // unsigned , default = 1, how many room fifo have, then axi send series req, 0=16 1=32 2=24 3=64
+//Bit 9:8 reg_burst_len // unsigned , default = 2, burst type: 0-single 1-bst2 2-bst4
+//Bit 7 reg_swap_64bit // unsigned , default = 0, 64bits of 128bit swap enable
+//Bit 6 reg_little_endian // unsigned , default = 0, big endian enable
+//Bit 5 reg_y_rev // unsigned , default = 0, vertical reverse enable
+//Bit 4 reg_x_rev // unsigned , default = 0, horizontal reverse enable
+//Bit 3 reserved
+//Bit 2:0 reg_pack_mode // unsigned , default = 3, 0:4bit 1:8bit 2:16bit 3:32bit 4:64bit 5:128bit
+#define DI_AFBCE_MMU_RMIF_CTRL2 ((0x2081 << 2) + 0xff000000)
+//Bit 31:30 reg_sw_rst // unsigned , default = 0,
+//Bit 29:24 reserved
+//Bit 23:18 reg_gclk_ctrl
+//Bit 17 reserved
+//Bit 16:0 reg_urgent_ctrl // unsigned , default = 0, urgent control reg :
+ // 16 reg_ugt_init : urgent initial value
+ // 15 reg_ugt_en : urgent enable
+ // 14 reg_ugt_type : 1= wrmif 0=rdmif
+ // 7:4 reg_ugt_top_th: urgent top threshold
+ // 3:0 reg_ugt_bot_th: urgent bottom threshold
+#define DI_AFBCE_MMU_RMIF_CTRL3 ((0x2082 << 2) + 0xff000000)
+//Bit 31:17 reserved
+//Bit 16 reg_acc_mode // unsigned , default = 1,
+//Bit 15:13 reserved
+//Bit 12:0 reg_stride // unsigned , default = 4096,
+#define DI_AFBCE_MMU_RMIF_CTRL4 ((0x2083 << 2) + 0xff000000)
+//Bit 31:0 reg_baddr // unsigned , default = 0,
+#define DI_AFBCE_MMU_RMIF_SCOPE_X ((0x2084 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_x_end // unsigned , default = 4095, the canvas hor end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_x_start // unsigned , default = 0, the canvas hor start pixel position
+#define DI_AFBCE_MMU_RMIF_SCOPE_Y ((0x2085 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_y_end // unsigned , default = 0, the canvas ver end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_y_start // unsigned , default = 0, the canvas ver start pixel positio
+#define DI_AFBCE_MMU_RMIF_RO_STAT ((0x2086 << 2) + 0xff000000)
+//Bit 15:0 reg_status // unsigned ,
+#define DI_AFBCE_PIP_CTRL ((0x208a << 2) + 0xff000000)
+//Bit 31:3 reserved
+//Bit 2 reg_enc_align_en //unsigned , RW,default = 1,
+//Bit 1 reg_pip_ini_ctrl //unsigned , RW,default = 0,
+//Bit 0 reg_pip_mode //unsigned , RW,default = 0,
+#define DI_AFBCE_ROT_CTRL ((0x208b << 2) + 0xff000000)
+//Bit 31:5 reserved
+//Bit 4 reg_rot_en //unsigned , RW,default = 0, rotation enable
+//Bit 3:0 reg_vstep //unsigned , RW,default = 8, rotation vstep ,setting acorrding rotation shrink mode
+#define DI_AFBCE_DIMM_CTRL ((0x208c << 2) + 0xff000000)
+//Bit 31 reg_dimm_layer_en //unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30 reserved
+//Bit 29:0 reg_dimm_data //unsigned , RW,default = 29'h00080200,dimm_layer data
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: di_afbc_enc0_regs.h
+//
+// the segment is 8'h90-8'h9f
+//
+// Reading file: di_wrmif0_regs.h
+//
+#define NRWR_DBG_AXI_CMD_CNT ((0x2090 << 2) + 0xff000000)
+#define NRWR_DBG_AXI_DAT_CNT ((0x2091 << 2) + 0xff000000)
+#define DI_NRWR_CANVAS ((0x2092 << 2) + 0xff000000)
+#define DI_NRWR_URGENT ((0x2093 << 2) + 0xff000000)
+#define DI_NRWR_X ((0x2094 << 2) + 0xff000000)
+#define DI_NRWR_Y ((0x2095 << 2) + 0xff000000)
+//bit 31:30 NRWR_words_lim
+//bit 29 NRWR_rev_y
+//bit 28:16 NRWR_start_y
+//bit 15 NRWR_ext_en
+//bit 12:0 NRWR_end_y
+#define DI_NRWR_CTRL ((0x2096 << 2) + 0xff000000)
+//bit 31 pending_ddr_wrrsp_NRWR
+//bit 30 NRWR_reg_swap
+//bit 29:26 NRWR_burst_lim
+//bit 25 NRWR_canvas_syncen
+//bit 24 NRWR_no_clk_gate
+//bit 23:22 NRWR_rgb_mode 0:422 to one canvas;1:4:4:4 to one canvas 2:Y to luma , CBCR to chroma canvas ,for nv12/21; 3 : reserved
+//bit 21:20 NRWR_hconv_mode
+//bit 19:18 NRWR_vconv_mode
+//bit 17 NRWR_swap_cbcr
+//bit 16 NRWR_urgent
+//bit 15:8 NRWR_canvas_index_chroma
+//bit 7:0 NRWR_canvas_index_luma
+#define DI_NRWR_SHRK_CTRL ((0x2097 << 2) + 0xff000000)
+//bit 31:10 reserved
+//bit 9:8 reg_vshrk_mode unsigned, default = 0, 0:1/2 horizonal shrink 1:1/4 horizonal shrink 2:1/8 horizonal shrink
+//bit 7:6 reg_hshrk_mode unsigned, default = 0, 0:1/2 vertical shrink 1:1/4 vertical shrink 2:1/8 vertical shrink
+//bit 5:2 reg_gclk_ctrl unsigned, default = 0
+//bit 1 reg_frm_rst unsigned, default = 0
+//bit 0 reg_shrk_en unsigned, default = 0
+#define DI_NRWR_SHRK_SIZE ((0x2098 << 2) + 0xff000000)
+//bit 31:26 reserved
+//bit 25:13 reg_frm_hsize unsigned, default = 1920, hsize in
+//bit 12:0 reg_frm_vsize unsigned, default = 1080, vsize in
+#define DI_NRWR_CROP_CTRL ((0x209a << 2) + 0xff000000)
+//Bit 31 reg_crop_en unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30:4 reserved
+//Bit 3:0 reg_hold_line unsigned , RW,default = 4,dimm_layer data
+#define DI_NRWR_CROP_DIMM_CTRL ((0x209b << 2) + 0xff000000)
+//Bit 31 reg_dimm_layer_en unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30 reserved
+//Bit 29:0 reg_dimm_data unsigned , RW,default = 29'h00080200,dimm_layer data
+#define DI_NRWR_CROP_SIZE_IN ((0x209c << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 reg_crop_hsize unsigned, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, reg_crop_vsize unsigned, default = 1080 , pic vert size in unit: pixel
+#define DI_NRWR_CROP_HSCOPE ((0x209d << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_cropwin_end_h unsigned, default = 1919 ;
+//Bit 15:13, reserved
+//Bit 12:0, reg_cropwin_bgn_h unsigned, default = 0 ;
+#define DI_NRWR_CROP_VSCOPE ((0x209e << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_cropwin_end_v unsigned, default = 1079 ;
+//Bit 15:13, reserved
+//Bit 12:0, reg_cropwin_bgn_v unsigned, default = 0 ;
+//
+// Closing file: di_wrmif0_regs.h
+//
+// the segment is 8'ha0-8'hbf
+//`define DI_IF1_URGENT_CTRL 8'ha3
+//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path
+//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path
+//`define DI_INP_URGENT_CTRL 8'ha4
+//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di mem chroma path
+//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di mem luma path
+//`define DI_MEM_URGENT_CTRL 8'ha5
+//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di chan2 chroma path
+//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di chan2 luma path
+//`define DI_CHAN2_URGENT_CTRL 8'ha6
+//`define DI_IF1_GEN_REG3 8'ha7
+//bit 31:1, reversed
+//bit 0, cntl_64bit_rev
+//`define DI_INP_GEN_REG3 8'ha8
+//bit 31:1, reversed
+//bit 0, cntl_64bit_rev
+//`define DI_MEM_GEN_REG3 8'ha9
+//bit 31:1, reversed
+//bit 0, cntl_64bit_rev
+//`define DI_CHAN2_GEN_REG3 8'haa
+//bit 31:1, reversed
+//bit 0, cntl_64bit_rev
+//`define DI_PRE_GL_CTRL 8'hab
+//bit 31,pre go field cnt enable
+//bit 30,pre go field cnt reset
+//bit 29:16, total pre go line
+//bit 13:0, total pre go frame
+//`define DI_PRE_GL_THD 8'hac
+//bit 31:0 go line size
+//`define DI_POST_GL_CTRL 8'had
+//bit 31,post go field cnt enable
+//bit 30,post go field cnt reset
+//bit 28:16, total post go line
+//bit 13:0, total post go frame
+//`define DI_POST_GL_THD 8'hae
+//bit 31:0 go line size
+//`define DI_IF0_AXI_CMD_CNT 8'hb0
+//`define DI_IF0_AXI_RDAT_CNT 8'hb1
+//
+//`define DI_IF1_AXI_CMD_CNT 8'hb2
+//`define DI_IF1_AXI_RDAT_CNT 8'hb3
+//
+//`define DI_IF2_AXI_CMD_CNT 8'hb4
+//`define DI_IF2_AXI_RDAT_CNT 8'hb5
+//
+//`define DI_INP_AXI_CMD_CNT 8'hb6
+//`define DI_INP_AXI_RDAT_CNT 8'hb7
+//
+//`define DI_MEM_AXI_CMD_CNT 8'hb8
+//`define DI_MEM_AXI_RDAT_CNT 8'hb9
+//
+//`define DI_CHAN2_AXI_CMD_CNT 8'hba
+//`define DI_CHAN2_AXI_RDAT_CNT 8'hbb
+// di afbc_enc
+// the segment is 8'hc0-8'hef
+//
+// Reading file: di_afbc_enc1_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DI_AFBCE1_ENABLE ((0x20c0 << 2) + 0xff000000)
+//Bit 31:20, gclk_ctrl unsigned , default = 0,
+//Bit 19:16, di_AFBCE1_sync_sel unsigned , default = 0,
+//Bit 15:14, reserved
+//Bit 13, enc_rst_mode unsigned , default = 0,
+//Bit 12, enc_en_mode unsigned , default = 0,
+//Bit 11:9, reserved
+//Bit 8, enc_enable unsigned , default = 0,
+//Bit 7:1, reserved
+//Bit 0, reserved enc_frm_start pulse use this bit don't use
+#define DI_AFBCE1_MODE ((0x20c1 << 2) + 0xff000000)
+//Bit 31:29, soft_rst unsigned, default = 0 ,the use as go_field
+//Bit 28, reserved unsigned, default = 0 , enable singal of crop
+//Bit 27:26, rev_mode unsigned, default = 0 , reverse mode
+//Bit 25:24, mif_urgent unsigned, default = 3 , info mif and data mif urgent
+//Bit 23, reserved
+//Bit 22:16, hold_line_num unsigned, default = 4, 0: burst1 1:burst2 2:burst4
+//Bit 15:14, burst_mode unsigned, default = 1, 0: burst1 1:burst2 2:burst4
+//Bit 13:1, reserved
+//Bit 0, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb
+#define DI_AFBCE1_SIZE_IN ((0x20c2 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hsize_in unsigned, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_in unsigned, default = 1080 , pic vert size in unit: pixel
+#define DI_AFBCE1_BLK_SIZE_IN ((0x20c3 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hblk_size unsigned, default = 60 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vblk_size unsigned, default = 270, pic vert size in unit: pixel
+#define DI_AFBCE1_HEAD_BADDR ((0x20c4 << 2) + 0xff000000)
+//Bit 31:0, head_baddr unsigned, default = 32'h00;
+#define DI_AFBCE1_MIF_SIZE ((0x20c5 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:28, ddr_blk_size unsigned, default = 1;
+//Bit 27, reserved
+//Bit 26:24, cmd_blk_size unsigned, default = 3;
+//Bit 23:21, reserved
+//Bit 20:16, uncmp_size unsigned, default = 20;
+//Bit 15:0, mmu_page_size unsigned, default = 4096;
+#define DI_AFBCE1_PIXEL_IN_HOR_SCOPE ((0x20c6 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, enc_win_end_h unsigned, default = 1919 ; //
+//Bit 15:13, reserved
+//Bit 12:0, enc_win_bgn_h unsigned, default = 0 ; //
+#define DI_AFBCE1_PIXEL_IN_VER_SCOPE ((0x20c7 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, enc_win_end_v unsigned, default = 1079 ; //
+//Bit 15:13, reserved
+//Bit 12:0, enc_win_bgn_v unsigned, default = 0 ; //
+#define DI_AFBCE1_CONV_CTRL ((0x20c8 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, fmt_ybuf_depth unsigned, default = 2048
+//Bit 15:12, reserved
+//Bit 11: 0, lbuf_depth unsigned, default = 256, unit=16 pixel need to set = 2^n
+#define DI_AFBCE1_MIF_HOR_SCOPE ((0x20c9 << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, blk_end_h unsigned, default = 0 ; //
+//Bit 15:10, reserved
+//Bit 9:0, blk_bgn_h unsigned, default = 59 ; //
+#define DI_AFBCE1_MIF_VER_SCOPE ((0x20ca << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, blk_end_v unsigned, default = 0 ; //
+//Bit 15:12, reserved
+//Bit 11:0, blk_bgn_v unsigned, default = 269 ; //
+#define DI_AFBCE1_STAT1 ((0x20cb << 2) + 0xff000000)
+//Bit 31, ro_frm_end_pulse1 unsigned, RO,default = 0 ;frame end status
+//Bit 30:0, ro_dbg_top_info1 unsigned, RO,default = 0 ;
+#define DI_AFBCE1_STAT2 ((0x20cc << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30:0, ro_dbg_top_info2 unsigned, RO,default = 0 ;
+#define DI_AFBCE1_FORMAT ((0x20cd << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11:10 reserved
+//Bit 9: 8 reg_format_mode // unsigned , RW, default = 2 data format;0 : YUV444, 1:YUV422, 2:YUV420, 3:RGB
+//Bit 7: 4 reg_compbits_c // unsigned , RW, default = 10 chroma bitwidth
+//Bit 3: 0 reg_compbits_y // unsigned , RW, default = 10 luma bitwidth
+#define DI_AFBCE1_MODE_EN ((0x20ce << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 reserved
+//Bit 25 reg_adpt_interleave_ymode // unsigned , RW, default = 0 force 0 to disable it: no HW implementation
+//Bit 24 reg_adpt_interleave_cmode // unsigned , RW, default = 0 force 0 to disable it: not HW implementation
+//Bit 23 reg_adpt_yinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
+//Bit 22 reg_adpt_yinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
+//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
+//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
+//Bit 19 reserved
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 11 reserved
+//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
+//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
+//Bit 8 reg_uncompress_split_mode // unsigned , RW, default = 0 0: no split; 1: split
+//Bit 7: 6 reserved
+//Bit 5 reg_input_padding_uv128 // unsigned , RW, default = 0 input picture 32x4 block gap mode: 0: pad uv=0; 1: pad uv=128
+//Bit 4 reg_dwds_padding_uv128 // unsigned , RW, default = 0 downsampled image for double write 32x gap mode: 0: pad uv=0; 1: pad uv=128
+//Bit 3: 1 reg_force_order_mode_value // unsigned , RW, default = 0 force order mode 0~7
+//Bit 0 reg_force_order_mode_en // unsigned , RW, default = 0 force order mode enable: 0: no force; 1: forced to force_value
+#define DI_AFBCE1_DWSCALAR ((0x20cf << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7: 6 reg_dwscalar_w0 // unsigned , RW, default = 3 horizontal 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 5: 4 reg_dwscalar_w1 // unsigned , RW, default = 0 horizontal 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 3: 2 reg_dwscalar_h0 // unsigned , RW, default = 2 vertical 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 1: 0 reg_dwscalar_h1 // unsigned , RW, default = 3 vertical 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+#define DI_AFBCE1_DEFCOLOR_1 ((0x20d0 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_enc_defalutcolor_3 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr]
+//Bit 11: 0 reg_enc_defalutcolor_0 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr]
+#define DI_AFBCE1_DEFCOLOR_2 ((0x20d1 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_enc_defalutcolor_2 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr]
+//Bit 11: 0 reg_enc_defalutcolor_1 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr]
+#define DI_AFBCE1_QUANT_ENABLE ((0x20d2 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_quant_expand_en_1 // unsigned , RW, default = 0 enable for quantization value expansion
+//Bit 10 reg_quant_expand_en_0 // unsigned , RW, default = 0 enable for quantization value expansion
+//Bit 9: 8 reg_bcleav_ofst // signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1;
+//Bit 7: 5 reserved
+//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy
+//Bit 3: 1 reserved
+//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy
+#define DI_AFBCE1_IQUANT_LUT_1 ((0x20d3 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE1_IQUANT_LUT_2 ((0x20d4 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE1_IQUANT_LUT_3 ((0x20d5 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE1_IQUANT_LUT_4 ((0x20d6 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE1_RQUANT_LUT_1 ((0x20d7 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_rquant_yclut_0_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting)
+//Bit 27 reserved
+//Bit 26:24 reg_rquant_yclut_0_10 // unsigned , RW, default = 5
+//Bit 23 reserved
+//Bit 22:20 reg_rquant_yclut_0_9 // unsigned , RW, default = 4
+//Bit 19 reserved
+//Bit 18:16 reg_rquant_yclut_0_8 // unsigned , RW, default = 4
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_0_7 // unsigned , RW, default = 3
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_0_6 // unsigned , RW, default = 3
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_0_5 // unsigned , RW, default = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_0_4 // unsigned , RW, default = 2
+#define DI_AFBCE1_RQUANT_LUT_2 ((0x20d8 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_0_3 // unsigned , RW, default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_0_2 // unsigned , RW, default = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_0_1 // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_0_0 // unsigned , RW, default = 0
+#define DI_AFBCE1_RQUANT_LUT_3 ((0x20d9 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_rquant_yclut_1_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting)
+//Bit 27 reserved
+//Bit 26:24 reg_rquant_yclut_1_10 // unsigned , RW, default = 5
+//Bit 23 reserved
+//Bit 22:20 reg_rquant_yclut_1_9 // unsigned , RW, default = 4
+//Bit 19 reserved
+//Bit 18:16 reg_rquant_yclut_1_8 // unsigned , RW, default = 4
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_1_7 // unsigned , RW, default = 3
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_1_6 // unsigned , RW, default = 3
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_1_5 // unsigned , RW, default = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_1_4 // unsigned , RW, default = 2
+#define DI_AFBCE1_RQUANT_LUT_4 ((0x20da << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_1_3 // unsigned , RW, default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_1_2 // unsigned , RW, default = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_1_1 // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_1_0 // unsigned , RW, default = 0
+#define DI_AFBCE1_YUV_FORMAT_CONV_MODE ((0x20db << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7 reserved
+//Bit 6: 4 reg_444to422_mode // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_422to420_mode // unsigned , RW, default = 0
+#define DI_AFBCE1_DUMMY_DATA ((0x20dc << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29: 0 reg_dummy_data // unsigned , default = 0 ;
+#define DI_AFBCE1_CLR_FLAG ((0x20dd << 2) + 0xff000000)
+//Bit 31:0 reg_di_AFBCE1_clr_flag // unsigned, default = 0 ;
+#define DI_AFBCE1_STA_FLAGT ((0x20de << 2) + 0xff000000)
+//Bit 31:0 ro_di_AFBCE1__sta_flag // unsigned, RO,default = 0 ;
+#define DI_AFBCE1_MMU_NUM ((0x20df << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 0 ro_frm_mmu_num // unsigned, RO,default = 0 ;
+#define DI_AFBCE1_MMU_RMIF_CTRL1 ((0x20e0 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_sync_sel // unsigned , default = 0, axi canvas id sync with frm rst
+//Bit 23:16 reg_canvas_id // unsigned , default = 0, axi canvas id num
+//Bit 15 reserved
+//Bit 14:12 reg_cmd_intr_len // unsigned , default = 1, interrupt send cmd when how many series axi cmd,
+ // 0=12 1=16 2=24 3=32 4=40 5=48 6=56 7=64
+//Bit 11:10 reg_cmd_req_size // unsigned , default = 1, how many room fifo have, then axi send series req, 0=16 1=32 2=24 3=64
+//Bit 9:8 reg_burst_len // unsigned , default = 2, burst type: 0-single 1-bst2 2-bst4
+//Bit 7 reg_swap_64bit // unsigned , default = 0, 64bits of 128bit swap enable
+//Bit 6 reg_little_endian // unsigned , default = 0, big endian enable
+//Bit 5 reg_y_rev // unsigned , default = 0, vertical reverse enable
+//Bit 4 reg_x_rev // unsigned , default = 0, horizontal reverse enable
+//Bit 3 reserved
+//Bit 2:0 reg_pack_mode // unsigned , default = 3, 0:4bit 1:8bit 2:16bit 3:32bit 4:64bit 5:128bit
+#define DI_AFBCE1_MMU_RMIF_CTRL2 ((0x20e1 << 2) + 0xff000000)
+//Bit 31:30 reg_sw_rst // unsigned , default = 0,
+//Bit 29:24 reserved
+//Bit 23:18 reg_gclk_ctrl
+//Bit 17 reserved
+//Bit 16:0 reg_urgent_ctrl // unsigned , default = 0, urgent control reg :
+ // 16 reg_ugt_init : urgent initial value
+ // 15 reg_ugt_en : urgent enable
+ // 14 reg_ugt_type : 1= wrmif 0=rdmif
+ // 7:4 reg_ugt_top_th: urgent top threshold
+ // 3:0 reg_ugt_bot_th: urgent bottom threshold
+#define DI_AFBCE1_MMU_RMIF_CTRL3 ((0x20e2 << 2) + 0xff000000)
+//Bit 31:17 reserved
+//Bit 16 reg_acc_mode // unsigned , default = 1,
+//Bit 15:13 reserved
+//Bit 12:0 reg_stride // unsigned , default = 4096,
+#define DI_AFBCE1_MMU_RMIF_CTRL4 ((0x20e3 << 2) + 0xff000000)
+//Bit 31:0 reg_baddr // unsigned , default = 0,
+#define DI_AFBCE1_MMU_RMIF_SCOPE_X ((0x20e4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_x_end // unsigned , default = 4095, the canvas hor end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_x_start // unsigned , default = 0, the canvas hor start pixel position
+#define DI_AFBCE1_MMU_RMIF_SCOPE_Y ((0x20e5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_y_end // unsigned , default = 0, the canvas ver end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_y_start // unsigned , default = 0, the canvas ver start pixel positio
+#define DI_AFBCE1_MMU_RMIF_RO_STAT ((0x20e6 << 2) + 0xff000000)
+//Bit 15:0 reg_status // unsigned ,
+#define DI_AFBCE1_PIP_CTRL ((0x20ea << 2) + 0xff000000)
+//Bit 31:3 reserved
+//Bit 2 reg_enc_align_en //unsigned , RW,default = 1,
+//Bit 1 reg_pip_ini_ctrl //unsigned , RW,default = 0,
+//Bit 0 reg_pip_mode //unsigned , RW,default = 0,
+#define DI_AFBCE1_ROT_CTRL ((0x20eb << 2) + 0xff000000)
+//Bit 31:5 reserved
+//Bit 4 reg_rot_en //unsigned , RW,default = 0, rotation enable
+//Bit 3:0 reg_vstep //unsigned , RW,default = 8, rotation vstep ,setting acorrding rotation shrink mode
+#define DI_AFBCE1_DIMM_CTRL ((0x20ec << 2) + 0xff000000)
+//Bit 31 reg_dimm_layer_en //unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30 reserved
+//Bit 29:0 reg_dimm_data //unsigned , RW,default = 29'h00080200,dimm_layer data
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: di_afbc_enc1_regs.h
+//
+// the segment is 8'hf0-8'hff
+//
+// Reading file: di_wrmif1_regs.h
+//
+#define DIWR_DBG_AXI_CMD_CNT ((0x20f0 << 2) + 0xff000000)
+#define DIWR_DBG_AXI_DAT_CNT ((0x20f1 << 2) + 0xff000000)
+#define DI_DIWR_CANVAS ((0x20f2 << 2) + 0xff000000)
+#define DI_DIWR_URGENT ((0x20f3 << 2) + 0xff000000)
+#define DI_DIWR_X ((0x20f4 << 2) + 0xff000000)
+#define DI_DIWR_Y ((0x20f5 << 2) + 0xff000000)
+//bit 31:30 diwr_words_lim
+//bit 29 diwr_rev_y
+//bit 28:16 diwr_start_y
+//bit 15 diwr_ext_en
+//bit 12:0 diwr_end_y
+#define DI_DIWR_CTRL ((0x20f6 << 2) + 0xff000000)
+//bit 31 pending_ddr_wrrsp_diwr
+//bit 30 diwr_reg_swap
+//bit 29:26 diwr_burst_lim
+//bit 25 diwr_canvas_syncen
+//bit 24 diwr_no_clk_gate
+//bit 23:22 diwr_rgb_mode 0:422 to one canvas;1:4:4:4 to one canvas 2:Y to luma , CBCR to chroma canvas ,for nv12/21; 3 : reserved
+//bit 21:20 diwr_hconv_mode
+//bit 19:18 diwr_vconv_mode
+//bit 17 diwr_swap_cbcr
+//bit 16 diwr_urgent
+//bit 15:8 diwr_canvas_index_chroma
+//bit 7:0 diwr_canvas_index_luma
+#define DI_DIWR_SHRK_CTRL ((0x20f7 << 2) + 0xff000000)
+//bit 31:10 reserved
+//bit 9:8 reg_vshrk_mode unsigned, default = 0, 0:1/2 horizonal shrink 1:1/4 horizonal shrink 2:1/8 horizonal shrink
+//bit 7:6 reg_hshrk_mode unsigned, default = 0, 0:1/2 vertical shrink 1:1/4 vertical shrink 2:1/8 vertical shrink
+//bit 5:2 reg_gclk_ctrl unsigned, default = 0
+//bit 1 reg_frm_rst unsigned, default = 0
+//bit 0 reg_shrk_en unsigned, default = 0
+#define DI_DIWR_SHRK_SIZE ((0x20f8 << 2) + 0xff000000)
+//bit 31:26 reserved
+//bit 25:13 reg_frm_hsize unsigned, default = 1920, hsize in
+//bit 12:0 reg_frm_vsize unsigned, default = 1080, vsize in
+#define DI_DIWR_CROP_CTRL ((0x20fa << 2) + 0xff000000)
+//Bit 31 reg_crop_en unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30:4 reserved
+//Bit 3:0 reg_hold_line unsigned , RW,default = 4,dimm_layer data
+#define DI_DIWR_CROP_DIMM_CTRL ((0x20fb << 2) + 0xff000000)
+//Bit 31 reg_dimm_layer_en unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30 reserved
+//Bit 29:0 reg_dimm_data unsigned , RW,default = 29'h00080200,dimm_layer data
+#define DI_DIWR_CROP_SIZE_IN ((0x20fc << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 reg_crop_hsize unsigned, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, reg_crop_vsize unsigned, default = 1080 , pic vert size in unit: pixel
+#define DI_DIWR_CROP_HSCOPE ((0x20fd << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_cropwin_end_h unsigned, default = 1919 ;
+//Bit 15:13, reserved
+//Bit 12:0, reg_cropwin_bgn_h unsigned, default = 0 ;
+#define DI_DIWR_CROP_VSCOPE ((0x20fe << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_cropwin_end_v unsigned, default = 1079 ;
+//Bit 15:13, reserved
+//Bit 12:0, reg_cropwin_bgn_v unsigned, default = 0 ;
+//
+// Closing file: di_wrmif1_regs.h
+//
+//
+// Closing file: vregs_clk1.h
+//
+//======================================================================
+// vpu register.
+//======================================================================
+//
+// Reading file: vpu_top_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//======================================================================
+// vpu register.
+//======================================================================
+// -----------------------------------------------
+// REG_BASE: VPU_VCBUS_BASE = 0x27
+// -----------------------------------------------
+//`define VPU_OSD1_MMC_CTRL 8'h01
+#define VPU_CRC_CTRL ((0x2701 << 2) + 0xff000000)
+#define VPU_RO_CRC0 ((0x2702 << 2) + 0xff000000)
+#define VPU_RO_CRC1 ((0x2703 << 2) + 0xff000000)
+#define VPU_RO_CRC2 ((0x2704 << 2) + 0xff000000)
+#define VPU_RO_CRC3 ((0x2705 << 2) + 0xff000000)
+#define VPU_RO_CRC4 ((0x2706 << 2) + 0xff000000)
+#define VPU_RO_CRC5 ((0x2707 << 2) + 0xff000000)
+#define VPU_RO_CRC6 ((0x2708 << 2) + 0xff000000)
+#define VPU_INTF_CTRL ((0x270a << 2) + 0xff000000)
+#define VPU_APB_PROT_CTRL ((0x270b << 2) + 0xff000000)
+#define VPU_ENC_ERROR ((0x270c << 2) + 0xff000000)
+#define VPU_SECURE_REG ((0x270d << 2) + 0xff000000)
+#define VPU_SECURE_ST_RO ((0x270e << 2) + 0xff000000)
+#define VPU_VDIN_SEC_IN ((0x270f << 2) + 0xff000000)
+//`define VPU_OSD2_MMC_CTRL 8'h02
+//`define VPU_VD1_MMC_CTRL 8'h03
+//`define VPU_VD2_MMC_CTRL 8'h04
+//`define VPU_DI_IF1_MMC_CTRL 8'h05
+//`define VPU_DI_MEM_MMC_CTRL 8'h06
+//`define VPU_DI_INP_MMC_CTRL 8'h07
+//`define VPU_DI_MTNRD_MMC_CTRL 8'h08
+//`define VPU_DI_CHAN2_MMC_CTRL 8'h09
+//`define VPU_DI_MTNWR_MMC_CTRL 8'h0a
+//`define VPU_DI_NRWR_MMC_CTRL 8'h0b
+//`define VPU_DI_DIWR_MMC_CTRL 8'h0c
+//`define VPU_VDIN0_MMC_CTRL 8'h0d
+//`define VPU_VDIN1_MMC_CTRL 8'h0e
+//`define VPU_BT656_MMC_CTRL 8'h0f
+//`define VPU_TVD3D_MMC_CTRL 8'h10
+//`define VPU_TVDVBI_MMC_CTRL 8'h11
+//Read only
+//`define VPU_TVDVBI_VSLATCH_ADDR 8'h12
+//Read only
+//`define VPU_TVDVBI_WRRSP_ADDR 8'h13
+#define VPU_VDIN_PRE_ARB_CTRL ((0x2714 << 2) + 0xff000000)
+#define VPU_VDISP_PRE_ARB_CTRL ((0x2715 << 2) + 0xff000000)
+#define VPU_VPUARB2_PRE_ARB_CTRL ((0x2716 << 2) + 0xff000000)
+#define VPU_OSD3_MMC_CTRL ((0x2717 << 2) + 0xff000000)
+#define VPU_OSD4_MMC_CTRL ((0x2718 << 2) + 0xff000000)
+#define VPU_VD3_MMC_CTRL ((0x2719 << 2) + 0xff000000)
+// [31:21] Reserved.
+// [20:18] cntl_encx_clk_sel
+// [17:16] cntl_vencl_dpi_sel_clk
+// [15: 8] Reserved
+// [ 6: 4] Reserved
+// [ 3: 2] cntl_viu2_sel_venc. Select which one of the encI/P/T that VIU2 connects to:
+// 0=No connection, 1=ENCI, 2=ENCP, 3=ENCT.
+// [ 1: 0] cntl_viu1_sel_venc. Select which one of the encI/P/T that VIU1 connects to:
+// 0=No connection, 1=ENCI, 2=ENCP, 3=ENCT.
+#define VPU_VIU_VENC_MUX_CTRL ((0x271a << 2) + 0xff000000)
+// [15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.
+// [11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.
+// [ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:
+// 0=output CrYCb(BRG);
+// 1=output YCbCr(RGB);
+// 2=output YCrCb(RBG);
+// 3=output CbCrY(GBR);
+// 4=output CbYCr(GRB);
+// 5=output CrCbY(BGR);
+// 6,7=Rsrv.
+// [ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).
+// [ 3] inv_vsync. 1=Invert Vsync polarity.
+// [ 2] inv_hsync. 1=Invert Hsync polarity.
+// [ 1: 0] src_sel. 0=Disable output to HDMI; 1=Select VENC_I output to HDMI; 2=Select VENC_P output.
+#define VPU_HDMI_SETTING ((0x271b << 2) + 0xff000000)
+#define ENCI_INFO_READ ((0x271c << 2) + 0xff000000)
+#define ENCP_INFO_READ ((0x271d << 2) + 0xff000000)
+#define ENCT_INFO_READ ((0x271e << 2) + 0xff000000)
+#define ENCL_INFO_READ ((0x271f << 2) + 0xff000000)
+// Bit 0 RW, viu_rst_n
+// Bit 1 RW, vdin_mmc_arb_rst_n
+// Bit 2 RW, vdisp_mmc_arb_rst_n
+// Bit 3 RW, vpuarb2_mmc_arb_rst_n
+#define VPU_SW_RESET ((0x2720 << 2) + 0xff000000)
+//Bit 30 d2d3_depr_req_sel, 0:vdisp_pre_arb, 1: vpuarb2_pre_arb
+//Bit 27:22 d2d3_depr_brst_num
+//Bit 21:16 d2d3_depr_id
+//Bit 14 d2d3_depw_req_sel, 0: vdin_pre_arb, 1: vdisp_pre_arb
+//Bit 11:6 d2d3_depw_brst_num
+//Bit 5:0 d2d3_depw_id
+#define VPU_D2D3_MMC_CTRL ((0x2721 << 2) + 0xff000000)
+//Bit 30 mtn_contrd_req_pre, 0:disp1_arb, 1: vdin_pre_arb
+//Bit 27:22 mtn_contrd_brst_num
+//Bit 21:16 mtn_contrd_id
+//Bit 14 mtn_contwr_req_pre, 0: vdisp1_arb, 1: vdin_pre_arb
+//Bit 11:6 mtn_contwr_brst_num
+//Bit 5:0 mtn_contwr_id
+#define VPU_CONT_MMC_CTRL ((0x2722 << 2) + 0xff000000)
+// Bit 6 RW, gclk_mpeg_vpu_misc
+// Bit 5 RW, gclk_mpeg_venc_l_top
+// Bit 4 RW, gclk_mpeg_vencl_int
+// Bit 3 RW, gclk_mpeg_vencp_int
+// Bit 2 RW, gclk_mpeg_vi2_top
+// Bit 1 RW, gclk_mpeg_vi_top
+// Bit 0 RW, gclk_mpeg_venc_p_top
+#define VPU_CLK_GATE ((0x2723 << 2) + 0xff000000)
+//Bit 12 RW, rdma_pre
+//Bit 11: 6 RW, rdma_num
+//Bit 5: 0 RW, rdma_id
+#define VPU_RDMA_MMC_CTRL ((0x2724 << 2) + 0xff000000)
+#define VPU_MEM_PD_REG0 ((0x2725 << 2) + 0xff000000)
+#define VPU_MEM_PD_REG1 ((0x2726 << 2) + 0xff000000)
+// [ 31] hdmi_data_ovr_en: 1=Enable overriding data input to HDMI TX with hdmi_data_ovr[29:0]. 0=No override. Default 0.
+// [ 30] Reserved. Default 0
+// [29: 0] hdmi_data_ovr. Default 0.
+#define VPU_HDMI_DATA_OVR ((0x2727 << 2) + 0xff000000)
+//Bit 15 RW, prot1_sel_osd4
+//Bit 14 RW, prot1_sel_osd3
+//Bit 13 RW, prot1_sel_osd2
+//Bit 12 RW, prot1_sel_osd1
+//Bit 11: 6 RW, prot1_brst_num
+//Bit 5: 0 RW, prot1_id
+#define VPU_PROT1_MMC_CTRL ((0x2728 << 2) + 0xff000000)
+//Bit 14 RW, prot2_sel_vd3
+//Bit 13 RW, prot2_sel_vd2
+//Bit 12 RW, prot2_sel_vd1
+//Bit 11: 6 RW, prot2_brst_num
+//Bit 5: 0 RW, prot2_id
+#define VPU_PROT2_MMC_CTRL ((0x2729 << 2) + 0xff000000)
+//Bit 14 RW, prot3_sel_vd3
+//Bit 13 RW, prot3_sel_vd2
+//Bit 12 RW, prot3_sel_vd1
+//Bit 11: 6 RW, prot3_brst_num
+//Bit 5: 0 RW, prot3_id
+#define VPU_PROT3_MMC_CTRL ((0x272a << 2) + 0xff000000)
+//Bit 29:24 RW, s3_brst_num
+//Bit 21:16 RW, s2_brst_num
+//Bit 13: 8 RW, s1_brst_num
+//Bit 5: 0 RW, s0_brst_num
+#define VPU_ARB4_V1_MMC_CTRL ((0x272b << 2) + 0xff000000)
+//Bit 29:24 RW, s3_brst_num
+//Bit 21:16 RW, s2_brst_num
+//Bit 13: 8 RW, s1_brst_num
+//Bit 5: 0 RW, s0_brst_num
+#define VPU_ARB4_V2_MMC_CTRL ((0x272c << 2) + 0xff000000)
+//Bit 27:22 RW, mcvecwr_num
+//Bit 21:16 RW, mcvecwr_id
+//Bit 11:6 RW, mcvecrd_num
+//Bit 5:0 RW, mcvecrd_id
+#define VPU_MCVEC_MMC_CTRL ((0x272d << 2) + 0xff000000)
+//Bit 27:22 RW, mcinfwr_num
+//Bit 21:16 RW, mcinfwr_id
+//Bit 11:6 RW, mcinfrd_num
+//Bit 5:0 RW, mcinfrd_id
+#define VPU_MCINF_MMC_CTRL ((0x272e << 2) + 0xff000000)
+//Bit 31 reg_vpu_pwm_inv, 1: invert the pwm signal, active low
+//Bit 30:29 reg_vpu_pwm_src_sel, 00: encl, enct, encp
+//Bit 28:16 reg_vpu_pwm_v_end0
+//Bit 12:0 reg_vpu_pwm_v_start0
+#define VPU_VPU_PWM_V0 ((0x2730 << 2) + 0xff000000)
+//Bit 28:16 reg_vpu_pwm_v_end1
+//Bit 12:0 reg_vpu_pwm_v_start1
+#define VPU_VPU_PWM_V1 ((0x2731 << 2) + 0xff000000)
+//Bit 28:16 reg_vpu_pwm_v_end2
+//Bit 12:0 reg_vpu_pwm_v_start2
+#define VPU_VPU_PWM_V2 ((0x2732 << 2) + 0xff000000)
+//Bit 28:16 reg_vpu_pwm_v_end3
+//Bit 12:0 reg_vpu_pwm_v_start3
+#define VPU_VPU_PWM_V3 ((0x2733 << 2) + 0xff000000)
+//Bit 28:16 reg_vpu_pwm_h_end0
+//Bit 12:0 reg_vpu_pwm_h_start0
+#define VPU_VPU_PWM_H0 ((0x2734 << 2) + 0xff000000)
+//Bit 28:16 reg_vpu_pwm_h_end1
+//Bit 12:0 reg_vpu_pwm_h_start1
+#define VPU_VPU_PWM_H1 ((0x2735 << 2) + 0xff000000)
+//Bit 28:16 reg_vpu_pwm_h_end2
+//Bit 12:0 reg_vpu_pwm_h_start2
+#define VPU_VPU_PWM_H2 ((0x2736 << 2) + 0xff000000)
+//Bit 28:16 reg_vpu_pwm_h_end3
+//Bit 12:0 reg_vpu_pwm_h_start3
+#define VPU_VPU_PWM_H3 ((0x2737 << 2) + 0xff000000)
+//Bit 18 reg_vpu_3d_go_high_fld_pol: 0: go high at field 0, 1: go high at field 1
+//Bit 17 reg_vpu_3d_sync_setting_vsync_latch
+//Bit 16 reg_vpu_3d_sync_enable
+//Bit 14:8 reg_vpu_3d_sync_v_end
+//Bit 6:0 reg_vpu_3d_sync_v_start
+#define VPU_VPU_3D_SYNC1 ((0x2738 << 2) + 0xff000000)
+//Bit 28:16 reg_vpu_3d_sync_h_end
+//Bit 12:0 reg_vpu_3d_sync_h_start
+#define VPU_VPU_3D_SYNC2 ((0x2739 << 2) + 0xff000000)
+//Bit 0, if true, force vencl clk enable, otherwise, it might auto turn off by mipi DSI
+#define VPU_MISC_CTRL ((0x2740 << 2) + 0xff000000)
+#define VPU_ISP_GCLK_CTRL0 ((0x2741 << 2) + 0xff000000)
+#define VPU_ISP_GCLK_CTRL1 ((0x2742 << 2) + 0xff000000)
+#define VPU_HDMI_FMT_CTRL ((0x2743 << 2) + 0xff000000)
+#define VPU_VDIN_ASYNC_HOLD_CTRL ((0x2744 << 2) + 0xff000000)
+#define VPU_VDISP_ASYNC_HOLD_CTRL ((0x2745 << 2) + 0xff000000)
+#define VPU_VPUARB2_ASYNC_HOLD_CTRL ((0x2746 << 2) + 0xff000000)
+// arb0_rd_urg_ctrl_o <= vpp_off_urg_ctrl & vpu_arb_urg_ctrl[0] |
+// rdma_ddr_req_busy_sync_d1 & vpu_arb_urg_ctrl[1]
+// ;
+//
+// arb1_rd_urg_ctrl_o <= vpp_off_urg_ctrl & vpu_arb_urg_ctrl[2] |
+// rdma_ddr_req_busy_sync_d1 & vpu_arb_urg_ctrl[3]
+// ;
+//
+// arb2_rd_urg_ctrl_o <= vpp_off_urg_ctrl & vpu_arb_urg_ctrl[4] |
+// rdma_ddr_req_busy_sync_d1 & vpu_arb_urg_ctrl[5]
+// ;
+//
+// arb0_wr_urg_ctrl_o <= vdin0_lff_urg_ctrl_sync_d1 & vpu_arb_urg_ctrl[6] |
+// vdin1_lff_urg_ctrl_sync_d1 & vpu_arb_urg_ctrl[7]
+// ;
+//
+// arb1_wr_urg_ctrl_o <= vdin0_lff_urg_ctrl_sync_d1 & vpu_arb_urg_ctrl[8] |
+// vdin1_lff_urg_ctrl_sync_d1 & vpu_arb_urg_ctrl[9]
+//
+#define VPU_ARB_URG_CTRL ((0x2747 << 2) + 0xff000000)
+#define VPU_SECURE_DUMMY ((0x2748 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_EN ((0x2749 << 2) + 0xff000000)
+// todo :
+#define VPU_422TO444_RST ((0x274a << 2) + 0xff000000)
+// todo :
+#define VPU_422TO444_CTRL0 ((0x274b << 2) + 0xff000000)
+// todo :
+#define VPU_422TO444_CTRL1 ((0x274c << 2) + 0xff000000)
+// todo :
+#define VPU_422TO444_CTRL2 ((0x274d << 2) + 0xff000000)
+// Picture Rotate (PROT) module 1 (for OSD) registers:
+#define VPU_PROT1_CLK_GATE ((0x2750 << 2) + 0xff900000)
+#define VPU_PROT1_GEN_CNTL ((0x2751 << 2) + 0xff900000)
+#define VPU_PROT1_X_START_END ((0x2752 << 2) + 0xff900000)
+#define VPU_PROT1_Y_START_END ((0x2753 << 2) + 0xff900000)
+#define VPU_PROT1_Y_LEN_STEP ((0x2754 << 2) + 0xff900000)
+#define VPU_PROT1_RPT_LOOP ((0x2755 << 2) + 0xff900000)
+#define VPU_PROT1_RPT_PAT ((0x2756 << 2) + 0xff900000)
+#define VPU_PROT1_DDR ((0x2757 << 2) + 0xff900000)
+#define VPU_PROT1_RBUF_ROOM ((0x2758 << 2) + 0xff900000)
+#define VPU_PROT1_STAT_0 ((0x2759 << 2) + 0xff900000)
+#define VPU_PROT1_STAT_1 ((0x275a << 2) + 0xff900000)
+#define VPU_PROT1_STAT_2 ((0x275b << 2) + 0xff900000)
+#define VPU_PROT1_REQ_ONOFF ((0x275c << 2) + 0xff900000)
+// Picture Rotate (PROT) module 2 (for VD) registers:
+#define VPU_PROT2_CLK_GATE ((0x2760 << 2) + 0xff900000)
+#define VPU_PROT2_GEN_CNTL ((0x2761 << 2) + 0xff900000)
+#define VPU_PROT2_X_START_END ((0x2762 << 2) + 0xff900000)
+#define VPU_PROT2_Y_START_END ((0x2763 << 2) + 0xff900000)
+#define VPU_PROT2_Y_LEN_STEP ((0x2764 << 2) + 0xff900000)
+#define VPU_PROT2_RPT_LOOP ((0x2765 << 2) + 0xff900000)
+#define VPU_PROT2_RPT_PAT ((0x2766 << 2) + 0xff900000)
+#define VPU_PROT2_DDR ((0x2767 << 2) + 0xff900000)
+#define VPU_PROT2_RBUF_ROOM ((0x2768 << 2) + 0xff900000)
+#define VPU_PROT2_STAT_0 ((0x2769 << 2) + 0xff900000)
+#define VPU_PROT2_STAT_1 ((0x276a << 2) + 0xff900000)
+#define VPU_PROT2_STAT_2 ((0x276b << 2) + 0xff900000)
+#define VPU_PROT2_REQ_ONOFF ((0x276c << 2) + 0xff900000)
+// Picture Rotate (PROT) module 3 (for VD) registers:
+#define VPU_PROT3_CLK_GATE ((0x2770 << 2) + 0xff900000)
+#define VPU_PROT3_GEN_CNTL ((0x2771 << 2) + 0xff900000)
+#define VPU_PROT3_X_START_END ((0x2772 << 2) + 0xff900000)
+#define VPU_PROT3_Y_START_END ((0x2773 << 2) + 0xff900000)
+#define VPU_PROT3_Y_LEN_STEP ((0x2774 << 2) + 0xff900000)
+#define VPU_PROT3_RPT_LOOP ((0x2775 << 2) + 0xff900000)
+#define VPU_PROT3_RPT_PAT ((0x2776 << 2) + 0xff900000)
+#define VPU_PROT3_DDR ((0x2777 << 2) + 0xff900000)
+#define VPU_PROT3_RBUF_ROOM ((0x2778 << 2) + 0xff900000)
+#define VPU_PROT3_STAT_0 ((0x2779 << 2) + 0xff900000)
+#define VPU_PROT3_STAT_1 ((0x277a << 2) + 0xff900000)
+#define VPU_PROT3_STAT_2 ((0x277b << 2) + 0xff900000)
+
+//Bit 20 reg_viu2vdin0_sw_reset: software reset
+//Bit 19:18 reg_viu2vdin0_dn_ratio: down-scale ratio; 0: no scale; 1: 1/2; 2:1/4; 3: reserved
+//Bit 17:16 reg_viu2vdin0_flt_mode: filter mode; 0: no filter; 1:[0 2 2 0]/4; 2:[1 1 1 1]/4; 3:[1 3 3 1]/8
+//Bit 15:14 reversed
+//Bit 13:0 reg_viu2vdin0_hsize: source horizontal size
+#define VPU_VIU2VDIN0_HDN_CTRL ((0x2780 << 2) + 0xff000000)
+#define VPU_VIU_ASYNC_MASK ((0x2781 << 2) + 0xff000000)
+#define VPU_VDIN_MISC_CTRL ((0x2782 << 2) + 0xff000000)
+// [31:29] Reserved.
+// [28:24] cntl_viu2vdin1_sel_data. Select VIU to VDIN data path, must clear it first before changing the path selection:
+// 5'b00000=Disable VIU to VDIN path;
+// 5'b00001=Enable VIU of ENC_I domain to VDIN;
+// 5'b00010=Enable VIU of ENC_P domain to VDIN;
+// 5'b00100=Enable VIU of ENC_T domain to VDIN;
+// 5'b01000=Enable VIU WriteBack 1 domain to VDIN;
+// 5'b10000=Enable VIU WriteBack 2 domain to VDIN;
+// [23:21] Reserved.
+// [20:16] cntl_viu2vdin1_sel_clk. Select which clock to VDIN path, must clear it first before changing the clock:
+// 5'b00000=Disable VIU to VDIN clock;
+// 5'b00001=Select encI clock to VDIN;
+// 5'b00010=Select encP clock to VDIN;
+// 5'b00100=Select encT clock to VDIN;
+// 5'b01000=Select VIU WriteBack 1 clock to VDIN;
+// 5'b10000=Select VIU WriteBack 2 clock to VDIN;
+// [15:13] Reserved.
+// [12: 8] cntl_viu2vdin0_sel_data. Select VIU to VDIN data path, must clear it first before changing the path selection:
+// 5'b00000=Disable VIU to VDIN path;
+// 5'b00001=Enable VIU of ENC_I domain to VDIN;
+// 5'b00010=Enable VIU of ENC_P domain to VDIN;
+// 5'b00100=Enable VIU of ENC_T domain to VDIN;
+// 5'b01000=Enable VIU WriteBack 1 domain to VDIN;
+// 5'b10000=Enable VIU WriteBack 2 domain to VDIN;
+// [ 7:5] Reserved.
+// [ 4: 0] cntl_viu2vdin0_sel_clk. Select which clock to VDIN path, must clear it first before changing the clock:
+// 5'b00000=Disable VIU to VDIN clock;
+// 5'b00001=Select encI clock to VDIN;
+// 5'b00010=Select encP clock to VDIN;
+// 5'b00100=Select encT clock to VDIN;
+// 5'b01000=Select VIU WriteBack 1 clock to VDIN;
+// 5'b10000=Select VIU WriteBack 2 clock to VDIN;
+#define VPU_VIU_VDIN_IF_MUX_CTRL ((0x2783 << 2) + 0xff000000)
+//Bit 20 reg_viu2vdin1_sw_reset: software reset
+//Bit 19:18 reg_viu2vdin1_dn_ratio: down-scale ratio; 0: no scale; 1: 1/2; 2:1/4; 3: reserved
+//Bit 17:16 reg_viu2vdin1_flt_mode: filter mode; 0: no filter; 1:[0 2 2 0]/4; 2:[1 1 1 1]/4; 3:[1 3 3 1]/8
+//Bit 15:14 reversed
+//Bit 13:0 reg_viu2vdin1_hsize: source horizontal size
+#define VPU_VIU2VDIN1_HDN_CTRL ((0x2784 << 2) + 0xff000000)
+#define VPU_VENCX_CLK_CTRL ((0x2785 << 2) + 0xff000000)
+//Bit 0 encp_afifo_clk
+//Bit 1 encl_afifo_clk
+//Bit 2 enci_afifo_clk
+// vpu arbtration :
+// the segment is 8'h90-8'hc8
+//
+// Reading file: vpu_arb_axi_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+//// reg
+////===============================////
+#define VPU_RDARB_MODE_L1C1 ((0x2790 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, rdarb_sel uns, default = 0 ,
+// rdarb_sel[0]==0 slave dc0 connect master port0 rdarb_sel[0]==1 slave dc0 connect master port1
+// rdarb_sel[1]==0 slave dc1 connect master port0 rdarb_sel[1]==1 slave dc1 connect master port1
+// rdarb_sel[2]==0 slave dc2 connect master port0 rdarb_sel[2]==1 slave dc2 connect master port1
+// rdarb_sel[3]==0 slave dc3 connect master port0 rdarb_sel[3]==1 slave dc3 connect master port1
+// rdarb_sel[4]==0 slave dc4 connect master port0 rdarb_sel[4]==1 slave dc4 connect master port1
+// rdarb_sel[5]==0 slave dc5 connect master port0 rdarb_sel[5]==1 slave dc5 connect master port1
+//Bit 15:10, reserved
+//Bit 9:8, rdarb_arb_mode uns, default = 0 ,
+// rdarb_arb_mode[0] master port0 arb way,
+// rdarb_arb_mode[1] master port1 arb way,
+//Bit 7:4, reserved
+//Bit 3:0, rdarb_gate_clk_ctrl uns, default = 0 ,
+// rdarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// rdarb_gate_clk_ctrl[3:2] master port1 clk gate control
+#define VPU_RDARB_REQEN_SLV_L1C1 ((0x2791 << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, rdarb_dc_req_en unsigned , default = 12'hfff
+// rdarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// rdarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// rdarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// rdarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// rdarb_dc_req_en[4]: the slv4 req to mst port0 enable,
+// rdarb_dc_req_en[5]: the slv5 req to mst port0 enable,
+// rdarb_dc_req_en[6]: the slv0 req to mst port1 enable,
+// rdarb_dc_req_en[7]: the slv1 req to mst port1 enable,
+// rdarb_dc_req_en[8]: the slv2 req to mst port1 enable,
+// rdarb_dc_req_en[9]: the slv3 req to mst port1 enable,
+// rdarb_dc_req_en[10]: the slv4 req to mst port1 enable,
+// rdarb_dc_req_en[11]: the slv5 req to mst port1 enable,
+#define VPU_RDARB_WEIGH0_SLV_L1C1 ((0x2792 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// rddc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// rddc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// rddc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+// rddc_weigh_sxn[4*6+:6]: the slv4 req weigh number
+#define VPU_RDARB_WEIGH1_SLV_L1C1 ((0x2793 << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[5*6+:6]: the slv5 req weigh number
+#define VPU_WRARB_MODE_L1C1 ((0x2794 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, wrarb_sel uns, default = 0 ,
+// wrarb_sel[0]==0 slave dc0 connect master port0 wrarb_sel[0]==1 slave dc0 connect master port1
+// wrarb_sel[1]==0 slave dc1 connect master port0 wrarb_sel[1]==1 slave dc1 connect master port1
+// wrarb_sel[2]==0 slave dc2 connect master port0 wrarb_sel[2]==1 slave dc2 connect master port1
+// wrarb_sel[3]==0 slave dc3 connect master port0 wrarb_sel[3]==1 slave dc3 connect master port1
+// wrarb_sel[4]==0 slave dc4 connect master port0 wrarb_sel[4]==1 slave dc4 connect master port1
+// wrarb_sel[5]==0 slave dc5 connect master port0 wrarb_sel[5]==1 slave dc5 connect master port1
+//Bit 15:10, reserved
+//Bit 9:8, wrarb_arb_mode uns, default = 0 ,
+// wrarb_arb_mode[0] master port0 arb way,
+// wrarb_arb_mode[1] master port1 arb way,
+//Bit 7:4, reserved
+//Bit 3:0, wrarb_gate_clk_ctrl uns, default = 0 ,
+// wrarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// wrarb_gate_clk_ctrl[3:2] master port1 clk gate control
+#define VPU_WRARB_REQEN_SLV_L1C1 ((0x2795 << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, wrarb_dc_req_en unsigned , default = 0
+// wrarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// wrarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// wrarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// wrarb_dc_req_en[4]: the slv4 req to mst port0 enable,
+// wrarb_dc_req_en[5]: the slv5 req to mst port0 enable,
+// wrarb_dc_req_en[0]: the slv0 req to mst port1 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port1 enable,
+// wrarb_dc_req_en[2]: the slv2 req to mst port1 enable,
+// wrarb_dc_req_en[3]: the slv3 req to mst port1 enable,
+// wrarb_dc_req_en[4]: the slv4 req to mst port1 enable,
+// wrarb_dc_req_en[5]: the slv5 req to mst port1 enable,
+#define VPU_WRARB_WEIGH0_SLV_L1C1 ((0x2796 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// wrdc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// wrdc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+// wrdc_weigh_sxn[4*6+:6]: the slv4 req weigh number
+#define VPU_WRARB_WEIGH1_SLV_L1C1 ((0x2797 << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[5*6+:6]: the slv5 req weigh number
+#define VPU_RDWR_ARB_STATUS_L1C1 ((0x2798 << 2) + 0xff000000)
+//Bit 31:4, reserved
+//Bit 3:2, wrarb_arb_busy unsigned , default = 0
+//Bit 1:0, rdarb_arb_busy unsigned , default = 0
+#define VPU_RDARB_MODE_L1C2 ((0x2799 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, rdarb_sel uns, default = 0 ,
+// rdarb_sel[0]==0 slave dc0 connect master port0 rdarb_sel[0]==1 slave dc0 connect master port1
+// rdarb_sel[1]==0 slave dc1 connect master port0 rdarb_sel[1]==1 slave dc1 connect master port1
+// rdarb_sel[2]==0 slave dc2 connect master port0 rdarb_sel[2]==1 slave dc2 connect master port1
+// rdarb_sel[3]==0 slave dc3 connect master port0 rdarb_sel[3]==1 slave dc3 connect master port1
+// rdarb_sel[4]==0 slave dc4 connect master port0 rdarb_sel[4]==1 slave dc4 connect master port1
+//Bit 15:10, reserved
+//Bit 9:8, rdarb_arb_mode uns, default = 0 ,
+// rdarb_arb_mode[0] master port0 arb way,
+// rdarb_arb_mode[1] master port1 arb way,
+//Bit 7:4, reserved
+//Bit 3:0, rdarb_gate_clk_ctrl uns, default = 0 ,
+// rdarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// rdarb_gate_clk_ctrl[3:2] master port0 clk gate control
+#define VPU_RDARB_REQEN_SLV_L1C2 ((0x279a << 2) + 0xff000000)
+//Bit 31:10, reserved
+//Bit 9:0, rdarb_dc_req_en unsigned , default = 0
+// rdarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// rdarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// rdarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// rdarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// rdarb_dc_req_en[4]: the slv4 req to mst port0 enable,
+// rdarb_dc_req_en[5]: the slv0 req to mst port1 enable,
+// rdarb_dc_req_en[6]: the slv1 req to mst port1 enable,
+// rdarb_dc_req_en[7]: the slv2 req to mst port1 enable,
+// rdarb_dc_req_en[8]: the slv3 req to mst port1 enable,
+// rdarb_dc_req_en[9]: the slv4 req to mst port1 enable,
+#define VPU_RDARB_WEIGH0_SLV_L1C2 ((0x279b << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// rddc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// rddc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// rddc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+// rddc_weigh_sxn[4*6+:6]: the slv4 req weigh number
+#define VPU_RDWR_ARB_STATUS_L1C2 ((0x279c << 2) + 0xff000000)
+//Bit 31:3, reserved
+//Bit 2, wrarb_arb_busy unsigned , default = 0
+//Bit 1:0, rdarb_arb_busy unsigned , default = 0
+#define VPU_RDARB_MODE_L2C1 ((0x279d << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, rdarb_sel uns, default = 0 ,
+// rdarb_sel[0]==0 slave dc0 connect master port0 rdarb_sel[0]==1 slave dc0 connect master port1
+// rdarb_sel[1]==0 slave dc1 connect master port0 rdarb_sel[1]==1 slave dc1 connect master port1
+// rdarb_sel[2]==0 slave dc2 connect master port0 rdarb_sel[2]==1 slave dc2 connect master port1
+// rdarb_sel[3]==0 slave dc3 connect master port0 rdarb_sel[3]==1 slave dc3 connect master port1
+// rdarb_sel[4]==0 slave dc4 connect master port0 rdarb_sel[4]==1 slave dc4 connect master port1
+// rdarb_sel[5]==0 slave dc5 connect master port0 rdarb_sel[5]==1 slave dc5 connect master port1
+//Bit 15:11, reserved
+//Bit 10:8, rdarb_arb_mode uns, default = 0 ,
+// rdarb_arb_mode[0] master port0 arb way,
+// rdarb_arb_mode[1] master port1 arb way,
+//Bit 7:6, reserved
+//Bit 5:0, rdarb_gate_clk_ctrl uns, default = 0 ,
+// rdarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// rdarb_gate_clk_ctrl[3:2] master port1 clk gate control
+// rdarb_gate_clk_ctrl[5:4] master port2 clk gate control
+#define VPU_RDARB_REQEN_SLV_L2C1 ((0x279e << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:0, rdarb_dc_req_en unsigned , default = 0
+// rdarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// rdarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// rdarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// rdarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// rdarb_dc_req_en[4]: the slv4 req to mst port0 enable,
+// rdarb_dc_req_en[5]: the slv5 req to mst port0 enable,
+// rdarb_dc_req_en[0]: the slv0 req to mst port1 enable,
+// rdarb_dc_req_en[1]: the slv1 req to mst port1 enable,
+// rdarb_dc_req_en[2]: the slv2 req to mst port1 enable,
+// rdarb_dc_req_en[3]: the slv3 req to mst port1 enable,
+// rdarb_dc_req_en[4]: the slv4 req to mst port1 enable,
+// rdarb_dc_req_en[5]: the slv5 req to mst port1 enable,
+#define VPU_RDARB_WEIGH0_SLV_L2C1 ((0x279f << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// rddc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// rddc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// rddc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+// rddc_weigh_sxn[4*6+:6]: the slv4 req weigh number
+#define VPU_RDARB_WEIGH1_SLV_L2C1 ((0x27a0 << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[5*6+:6]: the slv5 req weigh number
+#define VPU_RDWR_ARB_STATUS_L2C1 ((0x27a1 << 2) + 0xff000000)
+//Bit 31:4, reserved
+//Bit 3:2, wrarb_arb_busy unsigned , default = 0
+//Bit 1:0, rdarb_arb_busy unsigned , default = 0
+#define VPU_WRARB_MODE_L2C1 ((0x27a2 << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:16, wrarb_sel uns, default = 0 ,
+// wrarb_sel[0]==0 slave dc0 connect master port0 wrarb_sel[0]==1 slave dc0 connect master port1
+// wrarb_sel[1]==0 slave dc1 connect master port0 wrarb_sel[1]==1 slave dc1 connect master port1
+// wrarb_sel[2]==0 slave dc2 connect master port0 wrarb_sel[2]==1 slave dc2 connect master port1
+// wrarb_sel[3]==0 slave dc3 connect master port0 wrarb_sel[3]==1 slave dc3 connect master port1
+//Bit 15:10, reserved
+//Bit 9:8, wrarb_arb_mode uns, default = 0 ,
+// wrarb_arb_mode[0] master port0 arb way,
+// wrarb_arb_mode[1] master port1 arb way,
+//Bit 7:4, reserved
+//Bit 3:0, wrarb_gate_clk_ctrl uns, default = 0 ,
+// wrarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// wrarb_gate_clk_ctrl[3:2] master port0 clk gate control
+#define VPU_WRARB_REQEN_SLV_L2C1 ((0x27a3 << 2) + 0xff000000)
+//Bit 31:8, reserved
+//Bit 7:0, wrarb_dc_req_en unsigned , default = 0
+// wrarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// wrarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// wrarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// wrarb_dc_req_en[0]: the slv0 req to mst port1 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port1 enable,
+// wrarb_dc_req_en[2]: the slv2 req to mst port1 enable,
+// wrarb_dc_req_en[3]: the slv3 req to mst port1 enable,
+#define VPU_WRARB_WEIGH0_SLV_L2C1 ((0x27a4 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// wrdc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// wrdc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+#define VPU_ASYNC_RD_MODE0 ((0x27a5 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
+#define VPU_ASYNC_RD_MODE1 ((0x27a6 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
+#define VPU_ASYNC_RD_MODE2 ((0x27a7 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
+#define VPU_ASYNC_RD_MODE3 ((0x27a8 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
+#define VPU_ASYNC_RD_MODE4 ((0x27a9 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
+#define VPU_ASYNC_WR_MODE0 ((0x27aa << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
+#define VPU_ASYNC_WR_MODE1 ((0x27ab << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
+#define VPU_ASYNC_WR_MODE2 ((0x27ac << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
+#define VPU_ASYNC_STAT ((0x27ad << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, axiwr2_chan_idle unsigned , RO, axi write channel2 idle state
+//Bit 17, axiwr1_chan_idle unsigned , RO, axi write channel1 idle state
+//Bit 16, axiwr0_chan_idle unsigned , RO, axi write channel0 idle state
+//Bit 15:5, reserved
+//Bit 4, axird4_chan_idle unsigned , RO, axi read channel4 idle state
+//Bit 3, axird3_chan_idle unsigned , RO, axi read channel3 idle state
+//Bit 2, axird2_chan_idle unsigned , RO, axi read channel2 idle state
+//Bit 1, axird1_chan_idle unsigned , RO, axi read channel1 idle state
+//Bit 0, axird0_chan_idle unsigned , RO, axi read channel0 idle state
+#define VPU_WRARB_MODE_L1C2 ((0x27ae << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:16, wrarb_sel uns, default = 0 ,
+// wrarb_sel[0]==0 slave dc0 connect master port0 wrarb_sel[0]==1 slave dc0 connect master port1
+// wrarb_sel[1]==0 slave dc1 connect master port0 wrarb_sel[1]==1 slave dc1 connect master port1
+//Bit 15:9, reserved
+//Bit 8, wrarb_arb_mode uns, default = 0 ,
+// wrarb_arb_mode[0] master port0 arb way,
+//Bit 7:2, reserved
+//Bit 1:0, wrarb_gate_clk_ctrl uns, default = 0 ,
+// wrarb_gate_clk_ctrl[1:0] master port0 clk gate control
+#define VPU_WRARB_REQEN_SLV_L1C2 ((0x27af << 2) + 0xff000000)
+//Bit 31:2, reserved
+//Bit 1:0, wrarb_dc_req_en unsigned , default = 0
+// wrarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+#define VPU_WRARB_WEIGH0_SLV_L1C2 ((0x27b0 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// wrdc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[2*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[3*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[4*6+:6]: the slv1 req weigh number
+#define VPU_WRARB_WEIGH1_SLV_L1C2 ((0x27b1 << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[5*6+:6]: the slv0 req weigh number
+// wrdc_weigh_sxn[6*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[7*6+:6]: the slv1 req weigh number
+#define VPU_RDARB_WEIGH1_SLV_L1C2 ((0x27b2 << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[5*6+:6]: the slv0 req weigh number
+// rddc_weigh_sxn[6*6+:6]: the slv1 req weigh number
+// rddc_weigh_sxn[7*6+:6]: the slv2 req weigh number
+#define VPU_ARB_DBG_CTRL_L1C1 ((0x27b3 << 2) + 0xff000000)
+#define VPU_ARB_DBG_STAT_L1C1 ((0x27b4 << 2) + 0xff000000)
+#define VPU_ARB_DBG_CTRL_L1C2 ((0x27b5 << 2) + 0xff000000)
+#define VPU_ARB_DBG_STAT_L1C2 ((0x27b6 << 2) + 0xff000000)
+#define VPU_ARB_DBG_CTRL_L2C1 ((0x27b7 << 2) + 0xff000000)
+#define VPU_ARB_DBG_STAT_L2C1 ((0x27b8 << 2) + 0xff000000)
+#define VPU_ARB_PATH_CTRL ((0x27b9 << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP00 ((0x27ba << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP01 ((0x27bb << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP02 ((0x27bc << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP03 ((0x27bd << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP10 ((0x27be << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP11 ((0x27bf << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP12 ((0x27c0 << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP13 ((0x27c1 << 2) + 0xff000000)
+#define VPU_RDARB_UGT_L2C1 ((0x27c2 << 2) + 0xff000000)
+#define VPU_WRARB_UGT_L2C1 ((0x27c3 << 2) + 0xff000000)
+#define VPU_RDARB_LIMT0_L2C1 ((0x27c4 << 2) + 0xff000000)
+#define VPU_RDARB_LIMT1_L2C1 ((0x27c5 << 2) + 0xff000000)
+#define VPU_ARB_AXIWR_PROT ((0x27c6 << 2) + 0xff000000)
+#define VPU_ARB_AXIRD0_PROT ((0x27c7 << 2) + 0xff000000)
+#define VPU_ARB_AXIRD1_PROT ((0x27c8 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_arb_axi_regs.h
+//
+// vpu lut dma
+// the segment is 8'h50~8'h7f & 8'hca-8'hdf
+//
+// Reading file: vpu_lut_dma_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// 0x50~0x7f
+//
+// Reading file: viu_dma_top.h
+//
+#define VPU_DMA_RDMIF0_CTRL ((0x2750 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd0_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd0_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd0_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd0_enable_int // unsigned , RW , default = 0 channel0 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd0_stride // unsigned , RW , default = 512 channel0 send number
+#define VPU_DMA_RDMIF1_CTRL ((0x2751 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd1_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd1_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd1_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd1_enable_int // unsigned , RW , default = 0 channel1 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd1_stride // unsigned , RW , default = 512 channel1 send number
+#define VPU_DMA_RDMIF2_CTRL ((0x2752 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd2_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd2_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd2_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd2_enable_int // unsigned , RW , default = 0 channel2 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd2_stride // unsigned , RW , default = 512 channel2 send number
+#define VPU_DMA_RDMIF3_CTRL ((0x2753 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd3_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd3_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd3_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd3_enable_int // unsigned , RW , default = 0 channel3 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd3_stride // unsigned , RW , default = 512 channel3 send number
+#define VPU_DMA_RDMIF4_CTRL ((0x2754 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd4_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd4_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd4_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd4_enable_int // unsigned , RW , default = 0 channel4 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd4_stride // unsigned , RW , default = 512 channel4 send number
+#define VPU_DMA_RDMIF5_CTRL ((0x2755 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd5_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd5_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd5_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd5_enable_int // unsigned , RW , default = 0 channel5 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd5_stride // unsigned , RW , default = 512 channel5 send number
+#define VPU_DMA_RDMIF6_CTRL ((0x2756 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd6_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd6_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd6_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd6_enable_int // unsigned , RW , default = 0 channel6 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd6_stride // unsigned , RW , default = 512 channel6 send number
+#define VPU_DMA_RDMIF7_CTRL ((0x2757 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd7_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd7_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd7_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd7_enable_int // unsigned , RW , default = 0 channel7 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd7_stride // unsigned , RW , default = 512 channel7 send number
+#define VPU_DMA_RDMIF0_BADR0 ((0x2758 << 2) + 0xff000000)
+//Bit 31:0 lut0_reg_baddr0
+#define VPU_DMA_RDMIF0_BADR1 ((0x2759 << 2) + 0xff000000)
+//Bit 31:0 lut0_reg_baddr1
+#define VPU_DMA_RDMIF0_BADR2 ((0x275a << 2) + 0xff000000)
+//Bit 31:0 lut0_reg_baddr2
+#define VPU_DMA_RDMIF0_BADR3 ((0x275b << 2) + 0xff000000)
+//Bit 31:0 lut0_reg_baddr3
+#define VPU_DMA_RDMIF1_BADR0 ((0x275c << 2) + 0xff000000)
+//Bit 31:0 lut1_reg_baddr0
+#define VPU_DMA_RDMIF1_BADR1 ((0x275d << 2) + 0xff000000)
+//Bit 31:0 lut1_reg_baddr1
+#define VPU_DMA_RDMIF1_BADR2 ((0x275e << 2) + 0xff000000)
+//Bit 31:0 lut1_reg_baddr2
+#define VPU_DMA_RDMIF1_BADR3 ((0x275f << 2) + 0xff000000)
+//Bit 31:0 lut1_reg_baddr3
+#define VPU_DMA_RDMIF2_BADR0 ((0x2760 << 2) + 0xff000000)
+//Bit 31:0 lut2_reg_baddr0
+#define VPU_DMA_RDMIF2_BADR1 ((0x2761 << 2) + 0xff000000)
+//Bit 31:0 lut2_reg_baddr1
+#define VPU_DMA_RDMIF2_BADR2 ((0x2762 << 2) + 0xff000000)
+//Bit 31:0 lut2_reg_baddr2
+#define VPU_DMA_RDMIF2_BADR3 ((0x2763 << 2) + 0xff000000)
+//Bit 31:0 lut2_reg_baddr3
+#define VPU_DMA_RDMIF3_BADR0 ((0x2764 << 2) + 0xff000000)
+//Bit 31:0 lut3_reg_baddr0
+#define VPU_DMA_RDMIF3_BADR1 ((0x2765 << 2) + 0xff000000)
+//Bit 31:0 lut3_reg_baddr1
+#define VPU_DMA_RDMIF3_BADR2 ((0x2766 << 2) + 0xff000000)
+//Bit 31:0 lut3_reg_baddr2
+#define VPU_DMA_RDMIF3_BADR3 ((0x2767 << 2) + 0xff000000)
+//Bit 31:0 lut3_reg_baddr3
+#define VPU_DMA_RDMIF4_BADR0 ((0x2768 << 2) + 0xff000000)
+//Bit 31:0 lut4_reg_baddr0
+#define VPU_DMA_RDMIF4_BADR1 ((0x2769 << 2) + 0xff000000)
+//Bit 31:0 lut4_reg_baddr1
+#define VPU_DMA_RDMIF4_BADR2 ((0x276a << 2) + 0xff000000)
+//Bit 31:0 lut4_reg_baddr2
+#define VPU_DMA_RDMIF4_BADR3 ((0x276b << 2) + 0xff000000)
+//Bit 31:0 lut4_reg_baddr3
+#define VPU_DMA_RDMIF5_BADR0 ((0x276c << 2) + 0xff000000)
+//Bit 31:0 lut5_reg_baddr0
+#define VPU_DMA_RDMIF5_BADR1 ((0x276d << 2) + 0xff000000)
+//Bit 31:0 lut5_reg_baddr1
+#define VPU_DMA_RDMIF5_BADR2 ((0x276e << 2) + 0xff000000)
+//Bit 31:0 lut5_reg_baddr2
+#define VPU_DMA_RDMIF5_BADR3 ((0x276f << 2) + 0xff000000)
+//Bit 31:0 lut5_reg_baddr3
+#define VPU_DMA_RDMIF6_BADR0 ((0x2770 << 2) + 0xff000000)
+//Bit 31:0 lut6_reg_baddr0
+#define VPU_DMA_RDMIF6_BADR1 ((0x2771 << 2) + 0xff000000)
+//Bit 31:0 lut6_reg_baddr1
+#define VPU_DMA_RDMIF6_BADR2 ((0x2772 << 2) + 0xff000000)
+//Bit 31:0 lut6_reg_baddr2
+#define VPU_DMA_RDMIF6_BADR3 ((0x2773 << 2) + 0xff000000)
+//Bit 31:0 lut6_reg_baddr3
+#define VPU_DMA_RDMIF7_BADR0 ((0x2774 << 2) + 0xff000000)
+//Bit 31:0 lut7_reg_baddr0
+#define VPU_DMA_RDMIF7_BADR1 ((0x2775 << 2) + 0xff000000)
+//Bit 31:0 lut7_reg_baddr1
+#define VPU_DMA_RDMIF7_BADR2 ((0x2776 << 2) + 0xff000000)
+//Bit 31:0 lut7_reg_baddr2
+#define VPU_DMA_RDMIF7_BADR3 ((0x2777 << 2) + 0xff000000)
+//Bit 31:0 lut7_reg_baddr3
+//
+// Closing file: viu_dma_top.h
+//
+// 0x00~0x06
+//`include"viu_com_rdmif_regs.h"
+#define VPU_DMA_RDMIF_CTRL1 ((0x27ca << 2) + 0xff000000)
+#define VPU_DMA_RDMIF_CTRL2 ((0x27cb << 2) + 0xff000000)
+#define VPU_DMA_RDMIF_RO_STAT ((0x27d0 << 2) + 0xff000000)
+//0x07~0x0d
+//`include"viu_com_wrmif_regs.h"
+#define VPU_DMA_WRMIF_CTRL1 ((0x27d1 << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_CTRL2 ((0x27d2 << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_CTRL3 ((0x27d3 << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_BADDR0 ((0x27d4 << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_RO_STAT ((0x27d7 << 2) + 0xff000000)
+#define VPU_DMA_RDMIF_CTRL ((0x27d8 << 2) + 0xff000000)
+#define VPU_DMA_RDMIF_BADDR1 ((0x27d9 << 2) + 0xff000000)
+#define VPU_DMA_RDMIF_BADDR2 ((0x27da << 2) + 0xff000000)
+#define VPU_DMA_RDMIF_BADDR3 ((0x27db << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_CTRL ((0x27dc << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_BADDR1 ((0x27dd << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_BADDR2 ((0x27de << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_BADDR3 ((0x27df << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_lut_dma_regs.h
+//
+// the segment is 8'he0-8'hef
+#define VPU_VENCL_DITH_CTRL ((0x27e0 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_1 ((0x27e1 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_2 ((0x27e2 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_3 ((0x27e3 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_4 ((0x27e4 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_5 ((0x27e5 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_6 ((0x27e6 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_7 ((0x27e7 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_8 ((0x27e8 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_9 ((0x27e9 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_10 ((0x27ea << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_11 ((0x27eb << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_12 ((0x27ec << 2) + 0xff000000)
+//new added 4x4 dither
+// the segment is 8'hf0
+#define VPU_HDMI_DITH_01_04 ((0x27f0 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_01_15 ((0x27f1 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_01_26 ((0x27f2 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_01_37 ((0x27f3 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_10_04 ((0x27f4 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_10_15 ((0x27f5 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_10_26 ((0x27f6 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_10_37 ((0x27f7 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_11_04 ((0x27f8 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_11_15 ((0x27f9 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_11_26 ((0x27fa << 2) + 0xff000000)
+#define VPU_HDMI_DITH_11_37 ((0x27fb << 2) + 0xff000000)
+#define VPU_HDMI_DITH_CNTL ((0x27fc << 2) + 0xff000000)
+#define VPU_HDMI_TIMING_STAT ((0x27fd << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_top_regs.h
+//
+//========================================================================
+// MIPI CSI2 Controller Adaptor (16'h2a00 - 16'h2aff)
+//
+//========================================================================
+//`include "csi2_regs.h"
+//======================================================================
+// D2D3 registers
+//======================================================================
+//
+// Reading file: d2d3_regs.h
+//
+//===========================================================================
+// D2D3 Registers 0x - 0x
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: D2D3_VCBUS_BASE = 0x2b
+// -----------------------------------------------
+//------------------------------------------------------------------------------
+// D2D3 top-level registers
+//------------------------------------------------------------------------------
+// Bit 31 RW, rd_lock_en, 1 to allow update some read-only registers based on filed
+// Bit 30 RW, sw_rst_nobuf, 1 to reset the whole d2d3 unit
+// Bit 29:28 RW, clk_auto_dis, [29] DBR clock disable
+// [28] DPG clock disable
+// Bit 27:16 RW, clk_ctrl, [27:26] gated clock control for register unit
+// [25:24] gated clock control for DBR unit
+// [23:22] gated clock control for LBDG unit
+// [21:20] gated clock control for MBDG unit
+// [19:18] gated clock control for CBDG unit
+// [17:16] gated clock control for DBLD unit and SCD81 unit
+// Bit 15:12 Reserved
+// Bit 11 RW, lo_chroma_sign, 0: negate the u/v component of DBR left channel video output, 1: bypass
+// Bit 10 RW, ro_chroma_sign, 0: negate the u/v component of DBR right channel video output, 1: bypass
+// Bit 9 RW, vi0_chroma_sign, 0: negate the u/v component of DPG video input, 1: bypass
+// Bit 8 RW, vi1_chroma_sign, 0: negate the u/v component of DBR video input, 1: bypass
+// Bit 7:5 Reserved
+// Bit 4 RW, lg_en, Enable the LBDG unit and LBDG clock
+// Bit 3 RW, mg_en, Enable the MBDG unit and MBDG clock
+// Bit 2 RW, cg_en, Enable the CBDG unit and CBDG clock
+// Bit 1 RW, dbr_en, Enable the DBR unit and DBR clock
+// Bit 0 RW, dpg_en, Enable the DPG unit and clock except sub-unit CBDG, MBDG and LBDG
+#define D2D3_GLB_CTRL ((0x2b00 << 2) + 0xff000000)
+// Indicate the input picture size in DPG unit
+// Bit 31:16 RW, szx_vi_m1, The horizontal size minus 1
+// Bit 15:0 RW, szy_vi_m1, The vertical size minus 1
+#define D2D3_DPG_INPIC_SIZE ((0x2b01 << 2) + 0xff000000)
+// Indicate the output picture size in DBR unit
+// Bit 31:16 RW, szx_vo_m1, The horizontal size minus 1
+// Bit 15:0 RW, szy_vo_m1, The vertical size minus 1
+#define D2D3_DBR_OUTPIC_SIZE ((0x2b02 << 2) + 0xff000000)
+// Indicate the rectangular window to generate the "depth" in DPG unit
+// Bit 31:16 RW, dg_win_x_start, Horizontal start position, count from 0
+// Bit 15:0 RW, dg_win_x_end, Horizontal end position, count from 0
+#define D2D3_DGEN_WIN_HOR ((0x2b03 << 2) + 0xff000000)
+// Indicate the rectangular window to generate the "depth" in DPG unit
+// Bit 31:16 RW, dg_win_y_start, Vertical start position, count from 0
+// Bit 15:0 RW, dg_win_y_end, Vertical end position, count from 0
+#define D2D3_DGEN_WIN_VER ((0x2b04 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// CBDG SCU18 SCD81 SCD81_PRE registers
+// cg: color based depth generate module
+// scu18: scale up module
+// scd81: scale down module
+// scd81_pre: scd81 pre-scale-down module
+//------------------------------------------------------------------------------
+// Indicate parameters of pre-scale-down unit
+// Bit 31:16 RW, scd81_hphs_step, horizontal step
+// Bit 15:0 RW, scd81_hphs_ini, horizontal initial phase
+#define D2D3_PRE_SCD_H ((0x2b05 << 2) + 0xff000000)
+// Bit 31:16 RW, scu18_iniph, initial phase in SCU18,
+// [23:16] indicate the horizontal phase offset from the first data of every line
+// [31:24] indicate the vertical phase offset from the first line of every frame
+// Bit 15:12 Reserved
+// Bit 11 RW, scd81_predrop_en, 1 to enable scd81 pre-scale-down function
+// Bit 10:9 RW, cg_csc_sel, Color Space Conversion(CSC) matrix mode selector in CBDG
+// 0: BT.601 (16-235/240)
+// 1: BT.709 (16-235/240)
+// 2: BT.601 (0-255)
+// 3: BT.709 (0-255)
+// Bit 8 RW, scu18_rep_en, 1 to double each line of the SCU18 output
+// Bit 7:4 RW, scu18_factor, up-scale factor in SCU18 on DBR input depth data
+// [7:6] for vertical, 0->1:1, 1->1:2, 2->1:4, 3->1:8
+// [5:4] for horizontal, 0->1:1, 1->1:2, 2->1:4, 3->1:8
+// Bit 3:0 RW, scd81_factor, down-scale factor in SCD81 on DPG source video
+// [3:2] for vertical, 0->1:1, 1->2:1, 2->4:1, 3->8:1
+// [1:0] for horizontal, 0->1:1, 1->2:1, 2->4:1, 3->8:1
+#define D2D3_SCALER_CTRL ((0x2b06 << 2) + 0xff000000)
+// Bit 31:24 RW, cg_rpg_dth, the down |r-g| threshold for sky detect
+// Bit 23:16 RW, cg_rpg_uth, the up |r-g| threshold for sky detect
+// Bit 15:8 RW, cg_lum_dth, the down Y threshold for sky detect
+// Bit 7:0 RW, cg_lum_uth, the up Y threshold for sky detect
+#define D2D3_CG_THRESHOLD_1 ((0x2b07 << 2) + 0xff000000)
+// Bit 31:24 RW, cg_rpb_dth, the down |r-b| threshold for sky detect
+// Bit 23:16 RW, cg_rpb_uth, the up |r-b| threshold for sky detect
+// Bit 15:8 RW, cg_bpg_dth, the down |b-g| threshold for sky detect
+// Bit 7:0 RW, cg_bpg_uth, the up |b-g| threshold for sky detect
+#define D2D3_CG_THRESHOLD_2 ((0x2b08 << 2) + 0xff000000)
+// Bit 31:24 RW, cg_vp_rel_k, parameter to calculate vanish point reliability
+// Bit 23:16 RW, cg_vp_y_thr, the max limitation to calculate the vanish-point's vertical position
+// Bit 15:8 RW, cg_meet_dval, signed depth value in the sky-bitmap
+// Bit 7:0 RW, cg_unmt_dval, signed depth value not in the sky-bitmap
+#define D2D3_CG_PARAM_1 ((0x2b09 << 2) + 0xff000000)
+// Bit 31:16 RW, cg_vpos_thr, Maximal vertical limitation for sky-bit map when cg_vpos_en=1 and cg_vpos_adpt_en=0
+// Bit 15:8 Reserved
+// Bit 7 RW, cg_vpos_en, 1 to enable the max vertical limitation for sky-bitmap
+// Bit 6 RW, cg_vpos_adpt_en, 1 to enable the adaptive max vertical limitation for sky-bitmap.
+// It is only valid when cg_vpos_en=1.
+// The max vertical limitation is the previous field's vanish-point (vertical position) if cg_vpos_adpt_en=1.
+// Bit 5:4 RW, cg_lpf_bypass, bypass of low pass filter
+// [5]:Vertical bypass, 1: bypass the vertical LPF on the CBDG depth
+// [4]:Horizontal bypass, 1: bypass the horizontal LPF on the CBDG depth
+// Bit 3:0 RW, cg_vp_rel_s, parameter to calculate vanish point reliability
+#define D2D3_CG_PARAM_2 ((0x2b0a << 2) + 0xff000000)
+// Indicate parameters of pre-scale-down unit
+// Bit 31:16 RW, scd81_vphs_step, vertical step
+// Bit 15:0 RW, scd81_vphs_ini, vertical initial phase
+#define D2D3_PRE_SCD_V ((0x2b0b << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// D2P registers
+// d2p: depth to parallax transform module
+//------------------------------------------------------------------------------
+// Bit 31:24 RW, d2p_brdwid, Horizontal boundary width for parallax, the parallax value would be forced to 0 in boundary,
+// the d2p_brdwid should not 0 when D2P_WRAP is enabled
+// Bit 23:22 Reserved
+// Bit 21:20 RW, d2p_lomode, line output mode,
+// 0:whole line is left or right; 1:whole line is left or right;
+// 2:left/right pixel interleaved; 3:left/right half-line interleaved
+// Bit 19 RW, d2p_neg, 1 to exchange the left and right parallax value
+// Bit 18 Reserved
+// Bit 17 RW, d2p_wrap_en, 1 to enable D2P_WRAP unit
+// Bit 16 RW, d2p_lar, Indicate the first output for left or right, 0: left; 1: right
+// Bit 15 RW, d2p_lr_switch, enable left/right flag filed switch automatically, only valid when parallax output mode is field interleaved
+// Bit 14 RW, d2p_1dtolr, enable to generate 2 parallax data (left and right) from one depth
+// Bit 13:12 RW, d2p_out_mode, Parallax output mode
+// 0:left/right pixel interleaved; 1:line or half line interleaved; 2:field interleaved
+// Bit 11:8 RW, d2p_smode, Shift mode,
+// 0: no shift; 1: enable left shift;
+// 2: enable right shift; 3: both left and right shift are enabled
+// Bit 7:0 RW, d2p_offset, depth offset, signed,
+#define D2D3_D2P_PARAM_1 ((0x2b0c << 2) + 0xff000000)
+// Bit 31:24 RW, d2p_pg0, positive parallax gain when Parallax value < pt
+// Bit 23:16 RW, d2p_pg1, positive parallax gain when Parallax value >= pt
+// Bit 15:8 RW, d2p_pt, unsigned value used to separate the positive parallax range
+// Bit 7:0 RW, d2p_plimit, The limitation for positive parallax
+#define D2D3_D2P_PARAM_2 ((0x2b0d << 2) + 0xff000000)
+// Bit 31:24 RW, d2p_ng0, negative parallax gain when Parallax value > -nt
+// Bit 23:16 RW, d2p_ng1, negative parallax gain when Parallax value <= -nt
+// Bit 15:8 RW, d2p_nt, unsigned value used to separate the negative parallax range
+// Bit 7:0 RW, d2p_nlimit, The limitation for negative parallax
+#define D2D3_D2P_PARAM_3 ((0x2b0e << 2) + 0xff000000)
+// Indicate step parameters of SCU18 unit
+// Bit 31:17 Reserved
+// Bit 16 RW, scu18_step_en, step set enable in SCU18
+// Bit 15:8 RW, scu18_hphs_step, horizontal step in SCU18
+// Bit 7:0 RW, scu18_vphs_step, vertical step in SCU18
+#define D2D3_SCU18_STEP ((0x2b0f << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// LBDG and DBLD registers
+// lg: luma based depth generate module
+// db: depth blending module
+//------------------------------------------------------------------------------
+// Bit 31:22 Reserved
+// Bit 21:20 RW, db_lpf_bpcoeff, [21]:Vertical factor of low pass filter,
+// 1: Vfactor = 0/0/64/0/0, 0: Vfactor = {db_vf_a,db_vf_b,db_vf_c,db_vf_b,db_vf_a}, see D2D3_CTRL_15
+// [20]:Horizontal factor of low pass filter,
+// 1: Hfactor = 0/0/64/0/0, 0: Hfactor = {db_hf_a,db_hf_b,db_hf_c,db_hf_b,db_hf_a}, see D2D3_CTRL_14
+// Bit 19:18 RW, lg_lpf_bpcoeff, [19]:Vertical factor of low pass filter, 1: Vfactor = 0/64/0, 0: Vfactor = 20/24/20
+// [18]:Horizontal factor of low pass filter, 1: Hfactor = 0/64/0, 0: Hfactor = 16/32/16
+// Bit 17:16 RW, cg_lpf_bpcoeff, [17]:Vertical factor of low pass filter, 1: Vfactor = 0/64/0, 0: Vfactor = 20/24/20
+// [16]:Horizontal factor of low pass filter, 1: Hfactor = 0/64/0, 0: Hfactor = 16/32/16
+// Bit 15:10 Reserved
+// Bit 9:8 RW, db_lpf_bypass, [9] 1 to bypass the vertical LPF on the DBLD depth
+// [8] 1 to bypass the horizontal LPF on the DBLD depth
+// Bit 7:6 RW, lg_lpf_bypass, [7] 1 to bypass the vertical LPF on the LBDG depth
+// [6] 1 to bypass the horizontal LPF on the LBDG depth
+// Bit 5:0 RW, lg_kc, gain of CPL(v-u+256-y) to calculate the depth in LBDG
+#define D2D3_DPF_LPF_CTRL ((0x2b10 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// DBLD registers
+// db: depth blending module
+//------------------------------------------------------------------------------
+// Bit 31:24 RW, db_g2_cg, gain of CBDG depth in DBLD
+// Bit 23:16 RW, db_o2_cg, offset of CBDG depth in DBLD
+// Bit 15:8 RW, db_g1_cg, gain of CBDG depth using for summary in DBLD
+// Bit 7:0 RW, db_o1_cg, offset of CBDG depth using for summary in DBLD
+#define D2D3_DBLD_CG_PARAM ((0x2b11 << 2) + 0xff000000)
+// Bit 31:24 RW, db_g2_mg, gain of MBDG depth in DBLD
+// Bit 23:16 RW, db_o2_mg, offset of MBDG depth in DBLD
+// Bit 15:8 RW, db_g1_mg, gain of MBDG depth using for summary in DBLD
+// Bit 7:0 RW, db_o1_mg, offset of MBDG depth using for summary in DBLD
+#define D2D3_DBLD_MG_PARAM ((0x2b12 << 2) + 0xff000000)
+// Bit 31:24 RW, db_g2_lg, gain of LBDG depth in DBLD
+// Bit 23:16 RW, db_o2_lg, offset of LBDG depth in DBLD
+// Bit 15:8 RW, db_g1_lg, gain of LBDG depth using for summary in DBLD
+// Bit 7:0 RW, db_o1_lg, offset of LBDG depth using for summary in DBLD
+#define D2D3_DBLD_LG_PARAM ((0x2b13 << 2) + 0xff000000)
+// Bit 31:24 RW, db_factor, unsigned gain of difference in DBLD
+// Bit 23:16 RW, db_hf_a, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign
+// Bit 15:8 RW, db_hf_b, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign
+// Bit 7:0 RW, db_hf_c, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign
+#define D2D3_DBLD_LPF_HCOEFF ((0x2b14 << 2) + 0xff000000)
+// Bit 31:24 RW, db_owin_fill, signed depth value outside the rectangular window defined in register DGEN_WIN_HOR and DGEN_WIN_VER
+// Bit 23:16 RW, db_vf_a, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign
+// Bit 15:8 RW, db_vf_b, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign
+// Bit 7:0 RW, db_vf_c, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign
+#define D2D3_DBLD_LPF_VCOEFF ((0x2b15 << 2) + 0xff000000)
+// Bit 31:28 RW, hist_depth_idx,
+// Bit 27:26 Reserved
+// Bit 25 RW, mbdg_dep_neg, 1 to negate the output data of MBDG
+// Bit 24 RW, lbdg_dep_neg, 1 to negate the output data of LBDG
+// Bit 23:16 RW, db_f1_ctrl, MUX1 selector
+// [1:0] MUX1 path1 selector, 0:summary, 1:CBDG, 2:MBDG, 3:LBDG
+// [3:2] MUX1 path2 selector, 0:summary, 1:CBDG, 2:MBDG, 3:LBDG
+// [6:4] MUX1 out1 selector, 1:CBDG, 2:MBDG, 3:LBDG, 4:summary, 5:MUX1out0, others:summary
+// [7] MUX1OUT0 selector, 0:MIN (MUX1PATH1,MUX1Path2), 1:MAX (MUX1Path1,MUX1Path2)
+// Bit 15:8 RW, db_f2_ctrl, MUX2 selector
+// [1:0] MUX2 path1 selector, 0:MUX1OUT1, 1:CBDG, 2:MBDG, 3:LBDG
+// [3:2] MUX2 path2 selector, 0:MUX1OUT1, 1:CBDG, 2:MBDG, 3:LBDG
+// [6:4] MUX2 out1 selector, 1:CBDG, 2:MBDG, 3:LBDG, 4:summary, 5:MUX2out0, others:MUX2out0
+// [7] MUX2OUT0 selector, 0:MIN (MUX2PATH1,MUX2Path2), 1:MAX (MUX2Path1,MUX2Path2)
+// Bit 7:4 RW, db_fifo0_sel, the source input of FIFO0
+// 0: no use; 1:from CBDG; 2:from MBDG; 3:from LBDG others:reserved
+// Bit 3:0 RW, db_fifo1_sel, the source input of FIFO1
+// 0: no use; 1:from CBDG; 2:from MBDG; 3:from LBDG 4: from FIFO0; others:reserved
+#define D2D3_DBLD_PATH_CTRL ((0x2b16 << 2) + 0xff000000)
+// Indicate the input picture size in SCU18 unit
+// Bit 31:16 RW, szy_scui, The vertical size
+// Bit 15:0 RW, szx_scui, The horizontal size
+#define D2D3_SCU18_INPIC_SIZE ((0x2b17 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// MBDG registers
+// mg: model based depth generate module
+//------------------------------------------------------------------------------
+// Bit 31:18 Reserved
+// Bit 17 RW, mg_vp_en, mdg vanish point enable, not used
+// Bit 16 RW, mg_sw_en, 1 to use the software forced parameter for the point D, U and C in MBDG
+// Bit 15:8 RW, mg_owin_fill, Signed depth value outside the rectangular window defined in register DGEN_WIN_HOR and DGEN_WIN_VER
+// Bit 7 RW, mg_iir_en, 1 to enable the 2-taps IIR filter in MBDG
+// Bit 6:0 RW, mg_iir, [6]: 1 to bypass the 2-taps IIR filter in MBDG
+// [5:0]:Unsigned coefficient of the 2-taps IIR filter in MBDG
+// [6]:bypass, 1:bypass, 0:not bypass
+#define D2D3_MBDG_CTRL ((0x2b18 << 2) + 0xff000000)
+// Bit 31:28 RW, mg_dtl_pxl_left, Max pixel number (1<< mg_dtl_pxl_left) using in the left window for activities in MBDG
+// Bit 27:24 RW, mg_dtl_pxl_right, Max pixel number (1<< mg_dtl_pxl_right) using in the right window for activities in MBDG
+// Bit 23:16 RW, mg_cx_sw, Depth of point C in horizontal curve in MBDG for software forced
+// Bit 15:8 RW, mg_ux_sw, Depth of point U in horizontal curve in MBDG for software forced
+// Bit 7:0 RW, mg_dx_sw, Depth of point D in horizontal curve in MBDG for software forced
+#define D2D3_MBDG_PARAM_0 ((0x2b19 << 2) + 0xff000000)
+// Bit 31:28 RW, mg_dtl_pxl_up, Max pixel number (1<< mg_dtl_pxl_up) using in the top window for activities in MBDG
+// Bit 27:24 RW, mg_dtl_pxl_dn, Max pixel number (1<< mg_dtl_pxl_dn) using in the bottom window for activities in MBDG
+// Bit 23:16 RW, mg_cy_sw, Depth of point C in vertical curve in MBDG for software forced
+// Bit 15:8 RW, mg_uy_sw, Depth of point U in vertical curve in MBDG for software forced
+// Bit 7:0 RW, mg_dy_sw, Depth of point D in vertical curve in MBDG for software forced
+#define D2D3_MBDG_PARAM_1 ((0x2b1a << 2) + 0xff000000)
+// Bit 31:24 RW, mg_dtl_ln_up, Line number in the top window for activities in MBDG
+// Bit 23:16 RW, mg_dtl_ln_dn, Line number in the bottom window for activities in MBDG
+// Bit 15:8 RW, mg_dtl_ln_left, Column number in the left window for activities in MBDG
+// Bit 7:0 RW, mg_dtl_ln_right,Column number in the right window for activities in MBDG
+#define D2D3_MBDG_PARAM_2 ((0x2b1b << 2) + 0xff000000)
+// Bit 31:24 RW, mg_y_max, Software initial depth of point D and U in vertical curve
+// Bit 23:16 RW, mg_y_min, Software initial depth of point C in vertical curve
+// Bit 15:8 RW, mg_x_max, Software initial depth of point D and U in horizontal curve
+// Bit 7:0 RW, mg_x_min, Software initial depth of point C in horizontal curve
+#define D2D3_MBDG_PARAM_3 ((0x2b1c << 2) + 0xff000000)
+// Bit 31:27 Reserved
+// Bit 26 RW, mg_y_adapt_en, 1 to enable the adaptive mode for point U/D in vertical curve calculation
+// Bit 25 RW, mg_xmm_adapt_en, 1 to enable the XMM adaptive mode for point U/D in horizontal curve calculation
+// Bit 24 RW, mg_x_adapt_en, 1 to enable the adaptive mode for point U/D in horizontal curve calculation
+// Bit 23:20 RW, mg_ytrans_1, Shifter controller in vertical curve calculation, if mg_xtrans_1<0, right shift abs(mg_xtrans_1) bits, others left shift abs(mg_xtrans_1) bits
+// Bit 19:16 RW, mg_xtrans_1, Shifter controller in horizontal curve calculation, if mg_xtrans_1<0, right shift abs(mg_xtrans_1) bits, others left shift abs(mg_xtrans_1) bits
+// Bit 15:8 RW, mg_yk_0, The based activities value of the ACT for vertical curve
+// Bit 7:0 RW, mg_xk_0, The based activities value of the ACT for horizontal curve
+#define D2D3_MBDG_PARAM_4 ((0x2b1d << 2) + 0xff000000)
+// Bit 31:24 RW, mg_ysu3, Quantized value 3 in vertical curve adaptive calculation
+// Bit 23:16 RW, mg_ysu2, Quantized value 2 in vertical curve adaptive calculation
+// Bit 15:8 RW, mg_ysu1, Quantized value 1 in vertical curve adaptive calculation
+// Bit 7:0 RW, mg_ysu0, Quantized value 0 in vertical curve adaptive calculation
+#define D2D3_MBDG_PARAM_5 ((0x2b1e << 2) + 0xff000000)
+// Bit 31:24 RW, mg_xsu3, Quantized value 3 in horizontal curve adaptive calculation
+// Bit 23:16 RW, mg_xsu2, Quantized value 2 in horizontal curve adaptive calculation
+// Bit 15:8 RW, mg_xsu1, Quantized value 1 in horizontal curve adaptive calculation
+// Bit 7:0 RW, mg_xsu0, Quantized value 0 in horizontal curve adaptive calculation
+#define D2D3_MBDG_PARAM_6 ((0x2b1f << 2) + 0xff000000)
+// Bit 31:16 Reserved
+// Bit 15:8 RW, mg_xsu4, Quantized value 4 in horizontal curve adaptive calculation
+// Bit 7:0 RW, mg_ysu4, Quantized value 4 in vertical curve adaptive calculation
+#define D2D3_MBDG_PARAM_7 ((0x2b20 << 2) + 0xff000000)
+// Bit 31:28 RW, dbg_hscnt_sel see DBG_STATUS_2
+// Bit 27:25 Reserved
+// Bit 24 RW, dbg_dbr_en, 1 to enable debug mode in DBR
+// Bit 23:16 RW, dbg_force_data, Forced data in debug mode
+// Bit 15:12 RW, dbg_bld_ctrl, debug controller for DBLD
+// [12]:enable; [13]: 0 for passive mode, 0 for handshake mode
+// [15:14]: 0 for constant mode, 1 for step1 mode
+// Bit 11:8 RW, dbg_mg_ctrl, debug controller for MBDG
+// [8]:enable; [9]: 0 for passive mode, 0 for handshake mode
+// [11:10]: 0 for constant mode, 1 for step1 mode
+// Bit 7:4 RW, dbg_cg_ctrl, debug controller for CBDG
+// [4]:enable; [5]: 0 for passive mode, 0 for handshake mode
+// [7:6]: 0 for constant mode, 1 for step1 mode
+// Bit 3:0 RW, dbg_lg_ctrl, debug controller for LBDG
+// [0]:enable; [1]: 0 for passive mode, 0 for handshake mode
+// [3:2]: 0 for constant mode, 1 for step1 mode
+#define D2D3_DBG_CTRL ((0x2b23 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// DWMIF registers
+//------------------------------------------------------------------------------
+// Bit 31:18 Reserved
+// Bit 17 RW, dw_x_rev 0: Normal write data from left to right in horizontal
+// 1: Reversed write data from left to right in horizontal
+// Bit 16 RW, dw_y_rev 0: Normal write data from top to bottom in horizontal
+// 1: Reversed write data from bottom to top in horizontal
+// Bit 15 RW, dw_done_clr 1 to clear register depw_done (DWMIF_STATUS)
+// Bit 14 RW, dw_little_endian, 0: data is ordered in big-endian, 1: little endian
+// Bit 13:12 RW, dw_pic_struct, 0:read every line, 1:reserved, 2:read even line, 3:read odd line
+// Bit 11 RW, dw_urgent, urgent index
+// Bit 10 RW, dw_clr_wrrsp, 1:clear the write fifo counter
+// Bit 9 RW, dw_canvas_wr, canvas write initialization again
+// Bit 8 RW, dw_req_en, 1 to enable write request
+// Bit 7:0 RW, dw_canvas_index,Canvas index for the MSB of memory address for memory write
+#define D2D3_DWMIF_CTRL ((0x2b24 << 2) + 0xff000000)
+// Bit 31 Reserved
+// Bit 30:16 RW, dw_end_x, Horizontal end position for memory write, count by BYTE
+// Bit 15 Reserved
+// Bit 14:0 RW, dw_start_x, Horizontal start position for memory write, count by BYTE
+#define D2D3_DWMIF_HPOS ((0x2b25 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, dw_end_y, Vertical end position for memory write, count by BYTE
+// Bit 15:13 Reserved
+// Bit 12:0 RW, dw_start_y, Vertical start position for memory write, count by BYTE
+#define D2D3_DWMIF_VPOS ((0x2b26 << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, dw_vsizem1, Vertical size for memory write, equal the size minus 1
+// Bit 15:12 Reserved
+// Bit 11:0 RW, dw_hsizem1, Horizontal size for memory write, equal the size minus 1
+#define D2D3_DWMIF_SIZE ((0x2b27 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// DRMIF registers
+//------------------------------------------------------------------------------
+// Bit 31:18 Reserved
+// Bit 17 RW, dr_y_rev, 0: Normal Read data from top to bottom in horizontal
+// 1: Reversed read data from bottom to top in horizontal
+// Bit 16 RW, dr_x_rev, 0: Normal Read data from left to right in horizontal
+// 1: Reversed read data from right to left in horizontal
+// Bit 15 RW, dr_clr_fifo_error, 1 to clear the overflow flag of the sticky FIFO
+// Bit 14 RW, dr_little_endian, 0: data is ordered in big-endian; 1: little-endian
+// Bit 13:12 RW, dr_pic_struct, 0: progressive; 1: Reserved;
+// 2: interlaced, even line; 3: interlaced, odd line
+// Bit 11 RW, dr_urgent, urgent index, no use in this system
+// Bit 10:9 RW, dr_burst_size, Burst read length for each request; 0=24,1=32,2=48,3=64
+// Bit 8 RW, dr_req_en, 1 to enable read request
+// Bit 7:0 RW, dr_canvas_index, Canvas index for the MSB of memory address for memory read
+#define D2D3_DRMIF_CTRL ((0x2b28 << 2) + 0xff000000)
+// Bit 31 Reserved
+// Bit 30:16 RW, dr_end_x, Horizontal end position for memory read, count by BYTE
+// Bit 15 Reserved
+// Bit 14:0 RW, dr_start_x, Horizontal start position for memory read, count by BYTE
+#define D2D3_DRMIF_HPOS ((0x2b29 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, dr_end_y, Vertical end position for memory read, count by BYTE
+// Bit 15:13 Reserved
+// Bit 12:0 RW, dr_start_y, Vertical start position for memory read, count by BYTE
+#define D2D3_DRMIF_VPOS ((0x2b2a << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// PDR registers
+// ddd: parallax based render
+//------------------------------------------------------------------------------
+// Bit 31:8 Reserved
+// Bit 7 RW, ddd_brdlpf_en, 1 to enable the smooth filter on the depth around the boundary
+// Bit 6 RW, ddd_extn_black, 1 to enable the function to fill black colour when interpolated pixels is outside the picture in DBR
+// Bit 5 RW, ddd_wrap_en, Reserved
+// Bit 4 RW, ddd_hhalf, 1 to indicate the left/right line length is a half of original line.
+// Bit 3:2 RW, ddd_out_mode, Reserved
+// Bit 1:0 RW, ddd_lomode, wrap & pbr interleave mode:
+// 2'b0x: whole line is left or right;
+// 2'b10: d2p_lar=1(D2P_PARAM_1), rlrlrlrl inteleave in one line,
+// d2p_lar=0(D2P_PARAM_1), lrlrlrlr inteleave in one line,
+// 2'b11: d2p_lar=1(D2P_PARAM_1), rrrrrlllll, half line is right, another half is left,
+// d2p_lar=0(D2P_PARAM_1), lllllrrrrr, half line is left, another half is right,
+#define D2D3_DBR_DDD_CTRL ((0x2b2c << 2) + 0xff000000)
+// Bit 31:0 RW, ddd_dbg_ctrl, no use
+#define D2D3_DBR_DDD_DBG ((0x2b2d << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// LRDMX registers
+//------------------------------------------------------------------------------
+// Bit 31:9 Reserved
+// Bit 8 RW, lr_merge, 1: all the left/right input go to the left channel output
+// Bit 7:6 RW, lrd_ff0_sel, FF0 source selector
+// 0:from left input; 1:from right input; 2:from FF0; 3:no used
+// Bit 5:4 RW, lrd_ff1_sel, FF1 source selector
+// 0:from left input; 1:from right input; 2:from FF0; 3:no used
+// Bit 3:2 RW, lrd_lout_sel, left channel DEMUX
+// 00: ff0 01:ff1 10: left input 11:right input
+// Bit 1:0 RW, lrd_rout_sel, right channel DEMUX
+// 00: ff1 01:ff0 10: left input 11:right input
+#define D2D3_DBR_LRDMX_CTRL ((0x2b2f << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// Read Only registers
+//------------------------------------------------------------------------------
+// Bit 31:24 RO, ro_cg_vprel, vanish point's reliability in CBDG
+// Bit 23:12 RO, ro_cg_vpx, vanish point's X-Axis in CBDG
+// Bit 11:0 RO, ro_cg_vpy, vanish point's Y-Axis in CBDG
+#define D2D3_CBDG_STATUS_1 ((0x2b30 << 2) + 0xff000000)
+// Bit 31:24 RO, ro_mg_cx[7:0], X-Axis of point C in horizontal curve in MBDG
+// Bit 23:16 RO, ro_mg_ux, Depth value of point U in horizontal curve in MBDG
+// Bit 15:8 RO, ro_mg_dx, Depth value of point D in horizontal curve in MBDG
+// Bit 7:0 RO, ro_mg_minx, Depth value of point C in horizontal curve in MBDG
+#define D2D3_MBDG_STATUS_1 ((0x2b31 << 2) + 0xff000000)
+// Bit 31:24 RO, ro_mg_cy[7:0], X-Axis of point C in vertical curve in MBDG
+// Bit 23:16 RO, ro_mg_uy, Depth value of point U in vertical curve in MBDG
+// Bit 15:8 RO, ro_mg_dy, Depth value of point D in vertical curve in MBDG
+// Bit 7:0 RO, ro_mg_miny, Depth value of point C in vertical curve in MBDG
+#define D2D3_MBDG_STATUS_2 ((0x2b32 << 2) + 0xff000000)
+// Bit 31 RO, ro_wrap_status, 1 indicate the D2P_WRAP is busy to perform the initialization
+// Bit 30:8 Reserved
+// Bit 7:4 RO, ro_mg_cy[11:8], X-Axis of point C in vertical curve in MBDG
+// Bit 3:0 RO, ro_mg_cx[11:8], X-Axis of point C in horizontal curve in MBDG
+#define D2D3_MBDG_STATUS_3 ((0x2b33 << 2) + 0xff000000)
+// Bit 31:21 Reserved
+// Bit 20:0 RO, ro_mg_sum_u, ACT(top): activities of the top part
+#define D2D3_MBDG_STATUS_4 ((0x2b34 << 2) + 0xff000000)
+// Bit 31:21 Reserved
+// Bit 20:0 RO, ro_mg_sum_d, ACT(bottom): activities of the bottom part
+#define D2D3_MBDG_STATUS_5 ((0x2b35 << 2) + 0xff000000)
+// Bit 31:21 Reserved
+// Bit 20:0 RO, ro_mg_sum_l, ACT(left): activities of the left part
+#define D2D3_MBDG_STATUS_6 ((0x2b36 << 2) + 0xff000000)
+// Bit 31:21 Reserved
+// Bit 20:0 RO, ro_mg_sum_r, ACT(right): activities of the right part
+#define D2D3_MBDG_STATUS_7 ((0x2b37 << 2) + 0xff000000)
+// Bit 31:0 dbg_handshake_ro0, handshake signal for debug, internal srdy and rrdy
+#define D2D3_DBG_STATUS_1 ((0x2b38 << 2) + 0xff000000)
+// Bit 31:0 dbg_hscnt, dbg_hscnt_sel == 4'h0, output lg hscnt
+// dbg_hscnt_sel == 4'h1, output cg hscnt
+// dbg_hscnt_sel == 4'h2, output mg hscnt
+// dbg_hscnt_sel == 4'h3, output bld hscnt
+// dbg_hscnt_sel == other value, output 32'h0
+#define D2D3_DBG_STATUS_2 ((0x2b39 << 2) + 0xff000000)
+// Bit 31:0 RO, drmif_status, drmif module internal status
+#define D2D3_DRMIF_STATUS ((0x2b3a << 2) + 0xff000000)
+// Bit 31:2 RO, Reserved
+// Bit 1:0 RO, d2d3_status0, [1]: depw_done, one field depth write to ddr has done
+// [0]: dwmif_pending_ddr_wrrsp, 1 to indicate write response from ddr
+#define D2D3_DWMIF_STATUS ((0x2b3b << 2) + 0xff000000)
+// Bit 31:24 Reserved
+// Bit 23:0 RO, ro_meet_sum, register sumxy_sum_dbg in CBDG
+#define D2D3_CBDG_STATUS_2 ((0x2b3c << 2) + 0xff000000)
+// Bit 31:20 Reserved
+// Bit 19:0 RO, ro_hist_depth,
+#define D2D3_DBLD_STATUS ((0x2b3d << 2) + 0xff000000)
+// Bit 31:0 Reserved
+#define D2D3_RESEV_STATUS1 ((0x2b3e << 2) + 0xff000000)
+// Bit 31:0 Reserved
+#define D2D3_RESEV_STATUS2 ((0x2b3f << 2) + 0xff000000)
+//
+// Closing file: d2d3_regs.h
+//
+//========================================================================
+// MIPI DSI Host Controller (16'h2c00 - 16'h2cff)
+//
+//========================================================================
+//`include "dsi_regs.h"
+//========================================================================
+// ISP register (16'h2d00 - 16'h2dff)
+//========================================================================
+//`include "isp_reg.h"
+//
+// Reading file: vpu_dnr_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: MADB_VCBUS_BASE = 0x2d
+// -----------------------------------------------
+#define DNR_CTRL ((0x2d00 << 2) + 0xff000000)
+//Bit 31:17, reserved
+//Bit 16, reg_dnr_en , dnr enable . unsigned , default = 1
+//Bit 15, reg_dnr_db_vdbstep , vdb step, 0: 4, 1: 8 . unsigned , default = 1
+//Bit 14, reg_dnr_db_vdbprten , vdb protectoin enable . unsigned , default = 1
+//Bit 13, reg_dnr_gbs_difen , enable dif (between LR and LL/RR) condition for gbs stat.. unsigned , default = 0
+//Bit 12, reg_dnr_luma_en , enable ycbcr2luma module . unsigned , default = 1
+//Bit 11:10, reg_dnr_db_mod , deblocking mode, 0: disable, 1: horizontal deblocking, 2: vertical deblocking, 3: horizontal & vertical deblocking. unsigned , default = 3
+//Bit 9, reg_dnr_db_chrmen , enable chroma deblocking . unsigned , default = 1
+//Bit 8, reg_dnr_hvdif_mod , 0: calc. difs by original Y, 1: by new luma. unsigned , default = 1
+//Bit 7, reserved
+//Bit 6: 4, reg_dnr_demo_lften , b0: Y b1:U b2:V . unsigned , default = 7
+//Bit 3, reserved
+//Bit 2: 0, reg_dnr_demo_rgten , b0: Y b1:U b2:V . unsigned , default = 7
+#define DNR_HVSIZE ((0x2d01 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_dnr_hsize , hsize . unsigned , default = 0
+//Bit 15:13, reserved
+//Bit 12: 0, reg_dnr_vsize , vsize . unsigned , default = 0
+#define DNR_DBLK_BLANK_NUM ((0x2d02 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_dblk_hblank_num , deblock hor blank num . unsigned , default = 16
+//Bit 7: 0, reg_dblk_vblank_num , deblock ver blank num . unsigned , default = 45
+#define DNR_BLK_OFFST ((0x2d03 << 2) + 0xff000000)
+//Bit 31: 7, reserved
+//Bit 6: 4, reg_dnr_hbofst , horizontal block offset may provide by software calc.. unsigned , default = 0
+//Bit 3, reserved
+//Bit 2: 0, reg_dnr_vbofst , vertical block offset may provide by software calc.. unsigned , default = 0
+#define DNR_GBS ((0x2d04 << 2) + 0xff000000)
+//Bit 31: 2, reserved
+//Bit 1: 0, reg_dnr_gbs , global block strength may update by software calc.. unsigned , default = 0
+#define DNR_HBOFFST_STAT ((0x2d05 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_hbof_difthd , dif threshold (>=) between LR and LL/RR. unsigned , default = 2
+//Bit 23:16, reg_dnr_hbof_edgethd , edge threshold (<=) for LR . unsigned , default = 32
+//Bit 15: 8, reg_dnr_hbof_flatthd , flat threshold (>=) for LR . unsigned , default = 0
+//Bit 7, reserved
+//Bit 6: 4, reg_dnr_hbof_delta , delta for weighted bin accumulator. unsigned , default = 1
+//Bit 3, reserved
+//Bit 2: 0, reg_dnr_hbof_statmod , statistic mode for horizontal block offset, 0: count flags for 8-bin, 1: count LRs for 8-bin, 2: count difs for 8-bin, 3: count weighted flags for 8-bin, 4: count flags for first 32-bin, 5: count LRs for first 32-bin, 6 or 7: count difs for first 32-bin. unsigned , default = 2
+#define DNR_VBOFFST_STAT ((0x2d06 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_vbof_difthd , dif threshold (>=) between Up and Dw. unsigned , default = 1
+//Bit 23:16, reg_dnr_vbof_edgethd , edge threshold (<=) for Up/Dw. unsigned , default = 16
+//Bit 15: 8, reg_dnr_vbof_flatthd , flat threshold (>=) for Up/Dw. unsigned , default = 0
+//Bit 7, reserved
+//Bit 6: 4, reg_dnr_vbof_delta , delta for weighted bin accumulator. unsigned , default = 1
+//Bit 3, reserved
+//Bit 2: 0, reg_dnr_vbof_statmod , statistic mode for vertical block offset, 0: count flags for 8-bin, 1: count Ups for 8-bin, 2: count difs for 8-bin, 3: count weighted flags for 8-bin, 4: count flags for first 32-bin, 5: count Ups for first 32-bin, 6 or 7: count difs for first 32-bin. unsigned , default = 2
+#define DNR_GBS_STAT ((0x2d07 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_gbs_edgethd , edge threshold (<=) for LR . unsigned , default = 32
+//Bit 23:16, reg_dnr_gbs_flatthd , flat threshold (>=) for LR . unsigned , default = 0
+//Bit 15: 8, reg_dnr_gbs_varthd , variation threshold (<=) for Lvar/Rvar. unsigned , default = 16
+//Bit 7: 0, reg_dnr_gbs_difthd , dif threshold (>=) between LR and LL/RR. unsigned , default = 2
+#define DNR_STAT_X_START_END ((0x2d08 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:16, reg_dnr_stat_xst . unsigned , default = 24
+//Bit 15:14, reserved
+//Bit 13: 0, reg_dnr_stat_xed . unsigned , default = HSIZE - 25
+#define DNR_STAT_Y_START_END ((0x2d09 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:16, reg_dnr_stat_yst . unsigned , default = 24
+//Bit 15:14, reserved
+//Bit 13: 0, reg_dnr_stat_yed . unsigned , default = VSIZE - 25
+#define DNR_LUMA ((0x2d0a << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:24, reg_dnr_luma_sqrtshft , left shift for fast squart of chroma, [0, 4]. unsigned , default = 2
+//Bit 23:21, reserved
+//Bit 20:16, reg_dnr_luma_sqrtoffst , offset for fast squart of chroma. signed , default = 0
+//Bit 15, reserved
+//Bit 14:12, reg_dnr_luma_wcmod , theta related to warm/cool segment line, 0: 0, 1: 45, 2: 90, 3: 135, 4: 180, 5: 225, 6: 270, 7: 315. . unsigned , default = 3
+//Bit 11: 8, reg_dnr_luma_cshft , shift for calc. delta part, 0~8, . unsigned , default = 8
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_dnr_luma_cgain , final gain for delta part, 32 normalized to "1". unsigned , default = 4
+#define DNR_DB_YEDGE_THD ((0x2d0b << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_db_yedgethd0 , edge threshold0 for luma . unsigned , default = 12
+//Bit 23:16, reg_dnr_db_yedgethd1 , edge threshold1 for luma . unsigned , default = 15
+//Bit 15: 8, reg_dnr_db_yedgethd2 , edge threshold2 for luma . unsigned , default = 18
+//Bit 7: 0, reg_dnr_db_yedgethd3 , edge threshold3 for luma . unsigned , default = 25
+#define DNR_DB_CEDGE_THD ((0x2d0c << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_db_cedgethd0 , edge threshold0 for chroma . unsigned , default = 12
+//Bit 23:16, reg_dnr_db_cedgethd1 , edge threshold1 for chroma . unsigned , default = 15
+//Bit 15: 8, reg_dnr_db_cedgethd2 , edge threshold2 for chroma . unsigned , default = 18
+//Bit 7: 0, reg_dnr_db_cedgethd3 , edge threshold3 for chroma . unsigned , default = 25
+#define DNR_DB_HGAP ((0x2d0d << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_dnr_db_hgapthd , horizontal gap thd (<=) for very sure blockiness . unsigned , default = 8
+//Bit 15: 8, reg_dnr_db_hgapdifthd , dif thd between hgap and lft/rgt hdifs. unsigned , default = 1
+//Bit 7: 1, reserved
+//Bit 0, reg_dnr_db_hgapmod , horizontal gap calc. mode, 0: just use current col x, 1: find max between (x-1, x, x+1) . unsigned , default = 0
+#define DNR_DB_HBS ((0x2d0e << 2) + 0xff000000)
+//Bit 31: 6, reserved
+//Bit 5: 4, reg_dnr_db_hbsup , horizontal bs up value . unsigned , default = 1
+//Bit 3: 2, reg_dnr_db_hbsmax , max value of hbs for global control. unsigned , default = 3
+//Bit 1: 0, reg_dnr_db_hgbsthd , gbs thd (>=) for hbs calc. . unsigned , default = 1
+#define DNR_DB_HACT ((0x2d0f << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_dnr_db_hactthd0 , thd0 of hact, for block classification. unsigned , default = 10
+//Bit 7: 0, reg_dnr_db_hactthd1 , thd1 of hact, for block classification. unsigned , default = 32
+#define DNR_DB_YHDELTA_GAIN ((0x2d10 << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:24, reg_dnr_db_yhdeltagain1 , (p1-q1) gain for Y's delta calc. when bs=1, normalized 8 as "1" . unsigned , default = 2
+//Bit 23, reserved
+//Bit 22:20, reg_dnr_db_yhdeltagain2 , (p1-q1) gain for Y's delta calc. when bs=2, normalized 8 as "1" . unsigned , default = 0
+//Bit 19, reserved
+//Bit 18:16, reg_dnr_db_yhdeltagain3 , (p1-q1) gain for Y's delta calc. when bs=3, normalized 8 as "1" . unsigned , default = 0
+//Bit 15, reserved
+//Bit 14: 8, reg_dnr_db_yhdeltaadjoffst , offset for adjust Y's hdelta (-64, 63). signed , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_dnr_db_yhdeltaadjgain , gain for adjust Y's hdelta, normalized 32 as "1" . unsigned , default = 32
+#define DNR_DB_YHDELTA2_GAIN ((0x2d11 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_dnr_db_yhdelta2gain2 , gain for bs=2's adjust Y's hdelta2, normalized 64 as "1" . unsigned , default = 8
+//Bit 23:21, reserved
+//Bit 20:16, reg_dnr_db_yhdelta2offst2 , offset for bs=2's adjust Y's hdelta2 (-16, 15). signed , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_dnr_db_yhdelta2gain3 , gain for bs=3's adjust Y's hdelta2, normalized 64 as "1" . unsigned , default = 4
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_db_yhdelta2offst3 , offset for bs=3's adjust Y's hdelta2 (-16, 15). signed , default = 0
+#define DNR_DB_CHDELTA_GAIN ((0x2d12 << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:24, reg_dnr_db_chdeltagain1 , (p1-q1) gain for UV's delta calc. when bs=1, normalized 8 as "1". unsigned , default = 2
+//Bit 23, reserved
+//Bit 22:20, reg_dnr_db_chdeltagain2 , (p1-q1) gain for UV's delta calc. when bs=2, normalized 8 as "1". unsigned , default = 0
+//Bit 19, reserved
+//Bit 18:16, reg_dnr_db_chdeltagain3 , (p1-q1) gain for UV's delta calc. when bs=3, normalized 8 as "1". unsigned , default = 0
+//Bit 15, reserved
+//Bit 14: 8, reg_dnr_db_chdeltaadjoffst , offset for adjust UV's hdelta (-64, 63). signed , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_dnr_db_chdeltaadjgain , gain for adjust UV's hdelta, normalized 32 as "1". unsigned , default = 32
+#define DNR_DB_CHDELTA2_GAIN ((0x2d13 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_dnr_db_chdelta2gain2 , gain for bs=2's adjust UV's hdelta2, normalized 64 as "1" . unsigned , default = 8
+//Bit 23:21, reserved
+//Bit 20:16, reg_dnr_db_chdelta2offst2 , offset for bs=2's adjust UV's hdelta2 (-16, 15). signed , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_dnr_db_chdelta2gain3 , gain for bs=2's adjust UV's hdelta2, normalized 64 as "1" . unsigned , default = 4
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_db_chdelta2offst3 , offset for bs=2's adjust UV's hdelta2 (-16, 15). signed , default = 0
+#define DNR_DB_YC_VEDGE_THD ((0x2d14 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_dnr_db_yvedgethd , special Y's edge thd for vdb. unsigned , default = 12
+//Bit 7: 0, reg_dnr_db_cvedgethd , special UV's edge thd for vdb. unsigned , default = 12
+#define DNR_DB_VBS_MISC ((0x2d15 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_db_vgapthd , vertical gap thd (<=) for very sure blockiness . unsigned , default = 8
+//Bit 23:16, reg_dnr_db_vactthd , thd of vact, for block classification . unsigned , default = 10
+//Bit 15: 8, reg_dnr_db_vgapdifthd , dif thd between vgap and vact. unsigned , default = 4
+//Bit 7: 4, reserved
+//Bit 3: 2, reg_dnr_db_vbsmax , max value of vbs for global control. unsigned , default = 2
+//Bit 1: 0, reg_dnr_db_vgbsthd , gbs thd (>=) for vbs calc. . unsigned , default = 1
+#define DNR_DB_YVDELTA_GAIN ((0x2d16 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_dnr_db_yvdeltaadjgain , gain for adjust Y's vdelta, normalized 32 as "1". unsigned , default = 32
+//Bit 23, reserved
+//Bit 22:16, reg_dnr_db_yvdeltaadjoffst , offset for adjust Y's vdelta (-64, 63). signed , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_dnr_db_yvdelta2gain , gain for adjust Y's vdelta2, normalized 64 as "1". unsigned , default = 8
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_db_yvdelta2offst , offset for adjust Y's vdelta2 (-16, 15). signed , default = 0
+#define DNR_DB_CVDELTA_GAIN ((0x2d17 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_dnr_db_cvdeltaadjgain , gain for adjust UV's vdelta, normalized 32 as "1". unsigned , default = 32
+//Bit 23, reserved
+//Bit 22:16, reg_dnr_db_cvdeltaadjoffst , offset for adjust UV's vdelta (-64, 63). signed , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_dnr_db_cvdelta2gain , gain for adjust UV's vdelta2, normalized 64 as "1". unsigned , default = 8
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_db_cvdelta2offst , offset for adjust UV's vdelta2 (-16, 15). signed , default = 0
+#define DNR_RO_GBS_STAT_LR ((0x2d18 << 2) + 0xff000000)
+//Bit 31: 0, ro_gbs_stat_lr . unsigned , default = 0
+#define DNR_RO_GBS_STAT_LL ((0x2d19 << 2) + 0xff000000)
+//Bit 31: 0, ro_gbs_stat_ll . unsigned , default = 0
+#define DNR_RO_GBS_STAT_RR ((0x2d1a << 2) + 0xff000000)
+//Bit 31: 0, ro_gbs_stat_rr . unsigned , default = 0
+#define DNR_RO_GBS_STAT_DIF ((0x2d1b << 2) + 0xff000000)
+//Bit 31: 0, ro_gbs_stat_dif . unsigned , default = 0
+#define DNR_RO_GBS_STAT_CNT ((0x2d1c << 2) + 0xff000000)
+//Bit 31: 0, ro_gbs_stat_cnt . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_0 ((0x2d1d << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt0 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_1 ((0x2d1e << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt1 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_2 ((0x2d1f << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt2 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_3 ((0x2d20 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt3 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_4 ((0x2d21 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt4 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_5 ((0x2d22 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt5 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_6 ((0x2d23 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt6 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_7 ((0x2d24 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt7 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_8 ((0x2d25 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt8 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_9 ((0x2d26 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt9 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_10 ((0x2d27 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt10 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_11 ((0x2d28 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt11 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_12 ((0x2d29 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt12 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_13 ((0x2d2a << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt13 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_14 ((0x2d2b << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt14 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_15 ((0x2d2c << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt15 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_16 ((0x2d2d << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt16 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_17 ((0x2d2e << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt17 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_18 ((0x2d2f << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt18 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_19 ((0x2d30 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt19 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_20 ((0x2d31 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt20 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_21 ((0x2d32 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt21 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_22 ((0x2d33 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt22 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_23 ((0x2d34 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt23 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_24 ((0x2d35 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt24 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_25 ((0x2d36 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt25 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_26 ((0x2d37 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt26 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_27 ((0x2d38 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt27 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_28 ((0x2d39 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt28 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_29 ((0x2d3a << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt29 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_30 ((0x2d3b << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt30 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_31 ((0x2d3c << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt31 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_0 ((0x2d3d << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt0 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_1 ((0x2d3e << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt1 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_2 ((0x2d3f << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt2 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_3 ((0x2d40 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt3 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_4 ((0x2d41 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt4 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_5 ((0x2d42 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt5 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_6 ((0x2d43 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt6 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_7 ((0x2d44 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt7 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_8 ((0x2d45 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt8 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_9 ((0x2d46 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt9 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_10 ((0x2d47 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt10 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_11 ((0x2d48 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt11 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_12 ((0x2d49 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt12 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_13 ((0x2d4a << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt13 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_14 ((0x2d4b << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt14 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_15 ((0x2d4c << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt15 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_16 ((0x2d4d << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt16 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_17 ((0x2d4e << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt17 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_18 ((0x2d4f << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt18 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_19 ((0x2d50 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt19 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_20 ((0x2d51 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt20 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_21 ((0x2d52 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt21 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_22 ((0x2d53 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt22 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_23 ((0x2d54 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt23 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_24 ((0x2d55 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt24 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_25 ((0x2d56 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt25 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_26 ((0x2d57 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt26 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_27 ((0x2d58 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt27 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_28 ((0x2d59 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt28 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_29 ((0x2d5a << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt29 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_30 ((0x2d5b << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt30 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_31 ((0x2d5c << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt31 . unsigned , default = 0
+#define DNR_DM_ADP_EN ((0x2d5d << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7 reg_dnr_scene_change_flg // unsigned , default = 1 , scence change flag for dnr(dm);
+//Bit 6 reg_dnr_dm_lpf_en // unsigned , default = 1 , enable lpf for demosquito filter
+//Bit 5 reg_dnr_dm_adp_level_en // unsigned , default = 1 , enable adptive demosquito level
+//Bit 4 reg_dnr_dm_flg2bdif_en // unsigned , default = 1 , enable edge flg to blkdif calc.
+//Bit 3: 2 reg_dnr_dm_edgeiir // unsigned , default = 1 , edge flag iir mode, 0: cur, 1: max(pre, cur), 2: choice 0/1 by org mtn, 3: choice 0/1 by ref mtn
+//Bit 1 reg_dnr_dm_dirdifmod // unsigned , default = 1 , dif mode for direction calc, 0: abs(dif02), 1: (abs(dif01)+abs(dif21))/2
+//Bit 0 reg_dnr_dm_sur_dir_mod // unsigned , default = 0 , sure direction mode for cordif calc.
+#define DNR_DM_EDGE_DIR ((0x2d5e << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_dnr_dm_dirdifcor // unsigned , default = 2 , dif coring threshold for direction calc
+//Bit 15: 8 reg_dnr_dm_edgecordifthd // unsigned , default = 160 , edge flg down when cordif is large than threshold
+//Bit 7: 0 reg_dnr_dm_mtnrt // unsigned , default = 60 , motion ratio for mtn decision
+#define DNR_DM_CTRL ((0x2d60 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12, reg_dnr_dm_fedgeflg_en , enable edge flag calc. of each frame. unsigned , default = 1
+//Bit 11, reg_dnr_dm_fedgeflg_cl , clear frame edge flag if needed. unsigned , default = 1
+//Bit 10, reg_dnr_dm_fedgeflg_df , user defined edge when reg_dnr_dm_fedgeflg_en=0, default = 1
+//Bit 9, reg_dnr_dm_en , enable demosquito function . unsigned , default = 1
+//Bit 8, reg_dnr_dm_chrmen , enable chrome processing for demosquito. unsigned , default = 1
+//Bit 7: 6, reg_dnr_dm_level , demosquito level . unsigned , default = 3
+//Bit 5: 4, reg_dnr_dm_leveldw0 , level down when gbs is small. unsigned , default = 1
+//Bit 3: 2, reg_dnr_dm_leveldw1 , level down for no edge/flat blocks. unsigned , default = 1
+//Bit 1: 0, reg_dnr_dm_gbsthd , small/large threshold for gbs (<=). unsigned , default = 0
+#define DNR_DM_NR_BLND ((0x2d61 << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24, reg_dnr_dm_defalpen , enable user define alpha for dm & nr blend. unsigned , default = 0
+//Bit 23:16, reg_dnr_dm_defalp , user define alpha for dm & nr blend if enable. unsigned , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_dnr_dm_alpgain , gain for nr/dm alpha, normalized 32 as "1". unsigned , default = 32
+//Bit 7: 0, reg_dnr_dm_alpoffst , (-128, 127), offset for nr/dm alpha. signed , default = 0
+#define DNR_DM_RNG_THD ((0x2d62 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_dnr_dm_rngminthd . unsigned , default = 2
+//Bit 15: 8, reg_dnr_dm_rngmaxthd . unsigned , default = 64
+//Bit 7: 0, reg_dnr_dm_rngdifthd . unsigned , default = 4
+#define DNR_DM_RNG_GAIN_OFST ((0x2d63 << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13: 8, reg_dnr_dm_rnggain , normalized 16 as "1" . unsigned , default = 16
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_dnr_dm_rngofst . unsigned , default = 0
+#define DNR_DM_DIR_MISC ((0x2d64 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29, reg_dnr_dm_diralpen . unsigned , default = 1
+//Bit 28:24, reg_dnr_dm_diralpgain . unsigned , default = 0
+//Bit 23:22, reserved
+//Bit 21:16, reg_dnr_dm_diralpofst . unsigned , default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_diralpmin . unsigned , default = 0
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_diralpmax . unsigned , default = 31
+#define DNR_DM_COR_DIF ((0x2d65 << 2) + 0xff000000)
+//Bit 31: 4, reserved
+//Bit 3: 1, reg_dnr_dm_cordifshft . unsigned , default = 3
+//Bit 0, reg_dnr_dm_cordifmod , 0:use max dir dif as cordif, 1: use max3x3 - min3x3 as cordif. unsigned , default = 1
+#define DNR_DM_FLT_THD ((0x2d66 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_dm_fltthd00 , block flat threshold0 for block average difference when gbs is small, for flat block detection. unsigned , default = 4
+//Bit 23:16, reg_dnr_dm_fltthd01 , block flat threshold1 for block average difference when gbs is small, for flat block detection. unsigned , default = 6
+//Bit 15: 8, reg_dnr_dm_fltthd10 , block flat threshold0 for block average difference when gbs is large, for flat block detection. unsigned , default = 9
+//Bit 7: 0, reg_dnr_dm_fltthd11 , block flat threshold1 for block average difference when gbs is large, for flat block detection. unsigned , default = 12
+#define DNR_DM_VAR_THD ((0x2d67 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_dm_varthd00 , block variance threshold0 (>=) when gbs is small, for flat block detection. unsigned , default = 2
+//Bit 23:16, reg_dnr_dm_varthd01 , block variance threshold1 (<=) when gbs is small, for flat block detection. unsigned , default = 15
+//Bit 15: 8, reg_dnr_dm_varthd10 , block variance threshold0 (>=) when gbs is large, for flat block detection. unsigned , default = 3
+//Bit 7: 0, reg_dnr_dm_varthd11 , block variance threshold1 (<=) when gbs is large, for flat block detection. unsigned , default = 24
+#define DNR_DM_EDGE_DIF_THD ((0x2d68 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_dm_edgethd0 , block edge threshold (<=) when gbs is small, for flat block detection. unsigned , default = 32
+//Bit 23:16, reg_dnr_dm_edgethd1 , block edge threshold (<=) when gbs is large, for flat block detection. unsigned , default = 48
+//Bit 15: 8, reg_dnr_dm_difthd0 , block dif threshold (<=) when gbs is small, for flat block detection. unsigned , default = 48
+//Bit 7: 0, reg_dnr_dm_difthd1 , block dif threshold (<=) when gbs is large, for flat block detection. unsigned , default = 64
+#define DNR_DM_AVG_THD ((0x2d69 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_dnr_dm_avgthd0 , block average threshold (>=), for flat block detection. unsigned , default = 160
+//Bit 7: 0, reg_dnr_dm_avgthd1 , block average threshold (<=), for flat block detection. unsigned , default = 128
+#define DNR_DM_AVG_VAR_DIF_THD ((0x2d6a << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_dnr_dm_avgdifthd , block average dif threshold (<) between cur and up block, for flat block detection. unsigned , default = 12
+//Bit 7: 0, reg_dnr_dm_vardifthd , block variance dif threshold (>=) between cur and up block, for flat block detection. unsigned , default = 1
+#define DNR_DM_VAR_EDGE_DIF_THD2 ((0x2d6b << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_dnr_dm_varthd2 , block variance threshold (>=), for edge block detection. unsigned , default = 24
+//Bit 15: 8, reg_dnr_dm_edgethd2 , block edge threshold (>=), for edge block detection. unsigned , default = 40
+//Bit 7: 0, reg_dnr_dm_difthd2 , block dif threshold (>=), for edge block detection. unsigned , default = 80
+#define DNR_DM_DIF_FLT_MISC ((0x2d6c << 2) + 0xff000000)
+//Bit 31:28, reg_dnr_dm_ldifoob , pre-defined large dif when pixel out of blocks. unsigned , default = 0
+//Bit 27:24, reg_dnr_dm_bdifoob , pre-defined block dif when pixel out of blocks;. unsigned , default = 0
+//Bit 23:16, reg_dnr_dm_fltalp , pre-defined alpha for dm and nr blending, when block is flat with mos.. unsigned , default = 200
+//Bit 15:12, reserved
+//Bit 11: 8, reg_dnr_dm_fltminbdif , pre-defined min block dif for dm filter, when block is flat with mos.. unsigned , default = 12
+//Bit 7, reserved
+//Bit 6: 2, reg_dnr_dm_difnormgain , gain for pixel dif normalization for dm filter, normalized 16 as "1". unsigned , default = 16
+//Bit 1, reg_dnr_dm_difnormen , enable pixel dif normalization for dm filter. unsigned , default = 1
+//Bit 0, reg_dnr_dm_difupden , enable block dif update using max of left, cur, right difs. unsigned , default = 0
+#define DNR_DM_SDIF_LUT0_2 ((0x2d6d << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_sdiflut0 , normally 0-16 . unsigned , default = 16
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_sdiflut1 , normally 0-16 . unsigned , default = 14
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_sdiflut2 , normally 0-16 . unsigned , default = 13
+#define DNR_DM_SDIF_LUT3_5 ((0x2d6e << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_sdiflut3 , normally 0-16 . unsigned , default = 10
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_sdiflut4 , normally 0-16 . unsigned , default = 7
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_sdiflut5 , normally 0-16 . unsigned , default = 5
+#define DNR_DM_SDIF_LUT6_8 ((0x2d6f << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_sdiflut6 , normally 0-16 . unsigned , default = 3
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_sdiflut7 , normally 0-16 . unsigned , default = 1
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_sdiflut8 , normally 0-16 . unsigned , default = 0
+#define DNR_DM_LDIF_LUT0_2 ((0x2d70 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_ldiflut0 , normally 0-16 . unsigned , default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_ldiflut1 , normally 0-16 . unsigned , default = 4
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_ldiflut2 , normally 0-16 . unsigned , default = 12
+#define DNR_DM_LDIF_LUT3_5 ((0x2d71 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_ldiflut3 , normally 0-16 . unsigned , default = 14
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_ldiflut4 , normally 0-16 . unsigned , default = 15
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_ldiflut5 , normally 0-16 . unsigned , default = 16
+#define DNR_DM_LDIF_LUT6_8 ((0x2d72 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_ldiflut6 , normally 0-16 . unsigned , default = 16
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_ldiflut7 , normally 0-16 . unsigned , default = 16
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_ldiflut8 , normally 0-16 . unsigned , default = 16
+#define DNR_DM_DIF2NORM_LUT0_2 ((0x2d73 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_dif2normlut0 , normally 0-16 . unsigned , default = 16
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_dif2normlut1 , normally 0-16 . unsigned , default = 5
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_dif2normlut2 , normally 0-16 . unsigned , default = 3
+#define DNR_DM_DIF2NORM_LUT3_5 ((0x2d74 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_dif2normlut3 , normally 0-16 . unsigned , default = 2
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_dif2normlut4 , normally 0-16 . unsigned , default = 2
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_dif2normlut5 , normally 0-16 . unsigned , default = 1
+#define DNR_DM_DIF2NORM_LUT6_8 ((0x2d75 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_dif2normlut6 , normally 0-16 . unsigned , default = 1
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_dif2normlut7 , normally 0-16 . unsigned , default = 1
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_dif2normlut8 , normally 0-16 . unsigned , default = 1
+#define DNR_DM_GMS_THD ((0x2d76 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_gms_stat_thd0 . unsigned , default = 0
+//Bit 7: 0, reg_gms_stat_thd1 . unsigned , default = 128
+#define DNR_RO_DM_GMS_STAT_CNT ((0x2d77 << 2) + 0xff000000)
+//Bit 31: 0, ro_dm_gms_stat_cnt . unsigned , default = 0
+#define DNR_RO_DM_GMS_STAT_MS ((0x2d78 << 2) + 0xff000000)
+//Bit 31: 0, ro_dm_gms_stat_ms . unsigned , default = 0
+#define DNR_DM_EDGE_GAIN ((0x2d79 << 2) + 0xff000000)
+//Bit 31:24 reg_dnr_dm_alpedgegain0 // unsigned , default = 8 , edge based gain for alpha, normalized 16 as "1"
+//Bit 23:16 reg_dnr_dm_alpedgegain1 // unsigned , default = 16 , edge based gain for alpha, normalized 16 as "1"
+//Bit 15: 8 reg_dnr_dm_alpedgegain2 // unsigned , default = 24 , edge based gain for alpha, normalized 16 as "1"
+//Bit 7: 0 reg_dnr_dm_alpedgegain3 // unsigned , default = 32 , edge based gain for alpha, normalized 16 as "1"
+#define DNR_DM_FLG_BDIF ((0x2d7a << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:24 reg_dnr_dm_flg2bdif0 // unsigned , default = 0 , (0-16), edge flg to blkdif calc.
+//Bit 23:21 reserved
+//Bit 20:16 reg_dnr_dm_flg2bdif1 // unsigned , default = 6 , (0-16), edge flg to blkdif calc.
+//Bit 15:13 reserved
+//Bit 12: 8 reg_dnr_dm_flg2bdif2 // unsigned , default = 10 , (0-16), edge flg to blkdif calc.
+//Bit 7: 5 reserved
+//Bit 4: 0 reg_dnr_dm_flg2bdif3 // unsigned , default = 12 , (0-16), edge flg to blkdif calc.
+#define DNR_DM_GBS_RORM ((0x2d7b << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15:12 reg_dnr_dm_gbs4difnorm0 // unsigned , default = 0 , gbs=0 for dif norm calc.
+//Bit 11: 8 reg_dnr_dm_gbs4difnorm1 // unsigned , default = 1 , gbs=1 for dif norm calc.
+//Bit 7: 4 reg_dnr_dm_gbs4difnorm2 // unsigned , default = 4 , gbs=2 for dif norm calc.
+//Bit 3: 0 reg_dnr_dm_gbs4difnorm3 // unsigned , default = 6 , gbs=3 for dif norm calc.
+#define DNR_DM_FLG_LEV ((0x2d7c << 2) + 0xff000000)
+//Bit 31:14 reserved
+//Bit 13:12 reg_dnr_dm_flg2lev0 // unsigned , default = 1 , edge flg to filter level calc.
+//Bit 11:10 reserved
+//Bit 9: 8 reg_dnr_dm_flg2lev1 // unsigned , default = 3 , edge flg to filter level calc.
+//Bit 7: 6 reserved
+//Bit 5: 4 reg_dnr_dm_flg2lev2 // unsigned , default = 3 , edge flg to filter level calc.
+//Bit 3: 2 reserved
+//Bit 1: 0 reg_dnr_dm_flg2lev3 // unsigned , default = 3 , edge flg to filter level calc.
+#define DNR_DM_DIF_FLG_TH ((0x2d7d << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_dnr_dm_dif2flgthd1 // unsigned , default = 128 , dif to edge flg threshold 1
+//Bit 7: 0 reg_dnr_dm_dif2flgthd2 // unsigned , default = 192 , dif to edge flg threshold 2
+#define DNR_DM_CALP_GAIN_OFST ((0x2d7e << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:16 reg_dnr_dm_calpgain // unsigned , default = 16 , chroma gain for nr/dm alpha, normalized 32 as "1"
+//Bit 15: 9 reserved
+//Bit 8: 0 reg_dnr_dm_calpoffst // signed , default = -64 , (-255, 255), chroma offset for nr/dm alpha
+// 0x80-0x90
+//
+// Reading file: vpu_decomb_regs.h
+//
+ // defined registers
+#define DECOMB_DET_VERT_CON0 ((0x2d80 << 2) + 0xff000000)
+//Bit 31:24 reg_di_dcmb_det_vcon_thd0 default = 60 // u8
+//Bit 23:16 reg_di_dcmb_det_vcon_thd1 default = 80 // u8
+//Bit 15: 8 reg_di_dcmb_det_valp_lmt0 default = 63 // u8
+//Bit 7: 0 reg_di_dcmb_det_valp_lmt1 default = 4 // u8
+#define DECOMB_DET_VERT_CON1 ((0x2d81 << 2) + 0xff000000)
+//Bit 23:16 reg_di_dcmb_det_valp_lmt2 default = 0 // u8
+//Bit 15: 8 reg_di_dcmb_det_vrate0 default = 32 // u8
+//Bit 7: 0 reg_di_dcmb_det_vrate1 default = 4 // u8
+#define DECOMB_DET_EDGE_CON0 ((0x2d82 << 2) + 0xff000000)
+//Bit 31:24 reg_di_dcmb_det_econ_thd0 default = 60 // u8
+//Bit 23:16 reg_di_dcmb_det_econ_thd1 default = 80 // u8
+//Bit 15: 8 reg_di_dcmb_det_ealp_lmt0 default = 63 // u8
+//Bit 7: 0 reg_di_dcmb_det_ealp_lmt1 default = 4 // u8
+#define DECOMB_DET_EDGE_CON1 ((0x2d83 << 2) + 0xff000000)
+//Bit 23:16 reg_di_dcmb_det_ealp_lmt2 default = 0 // u8
+//Bit 15: 8 reg_di_dcmb_det_erate0 default = 32 // u8
+//Bit 7: 0 reg_di_dcmb_det_erate1 default = 4 // u8
+#define DECOMB_PARA ((0x2d84 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:28 reg_di_dcmb_cmb_lpf default = 1 // u2, 0:no lpf, 1:[1 2 1], 2,3: [1 2 2 2 1]
+//Bit 27:26 reg_di_dcmb_vedge_chk default = 0 // u2, vertical edge check, 0: no check, 1: vrt!=0, 2: vrt==3
+//Bit 25:24 reg_di_dcmb_nedge_chk default = 0 // u2, no idea edge check, 0, no check, 1, check
+//Bit 23:20 reg_di_dcmb_edge_min default = 0 // u4, min edge for edge cmb
+//Bit 19:16 reg_di_dcmb_edge_max default = 15 // u4, min edge for edge cmb
+//Bit 15:8 reg_di_dcmb_bld_alp default = 255 // u8, user defined alpha for di & decmb blend
+//Bit 7:0 reg_di_dcmb_bld_alp_beta default = 40 // u8, beta for mtn & cmb blend, for bld alpha calc.
+#define DECOMB_BLND_CON0 ((0x2d85 << 2) + 0xff000000)
+//Bit 31:24 reg_di_dcmb_bld_con_thd0 default = 100 // u8
+//Bit 23:16 reg_di_dcmb_bld_con_thd1 default = 120 // u8
+//Bit 15: 8 reg_di_dcmb_bld_alp_lmt0 default = 0 // u8
+//Bit 7: 0 reg_di_dcmb_bld_alp_lmt1 default = 128 // u8
+#define DECOMB_BLND_CON1 ((0x2d86 << 2) + 0xff000000)
+//Bit 23:16 reg_di_dcmb_bld_alp_lmt2 default = 255 // u8
+//Bit 15: 8 reg_di_dcmb_bld_rate0 default = 32 // u8
+//Bit 7: 0 reg_di_dcmb_bld_rate1 default = 32 // u8
+#define DECOMB_YC_THRD ((0x2d87 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_di_dcmb_ythd default = 2 // u8, default = 2
+//Bit 7: 0 reg_di_dcmb_cthd default = 2 // u8, default = 2
+#define DECOMB_MTN_GAIN_OFST ((0x2d88 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:16 reg_di_dcmb_mtn_alp_gain default = 16 // u6, 16 is normalized to '1'
+//Bit 15:9 reserved
+//Bit 8:0 reg_di_dcmb_mtn_alp_ofst default = 0 // s9, [-256, 255]
+#define DECOMB_CMB_SEL_GAIN_OFST ((0x2d89 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:16 reg_di_dcmb_cmb_sel_gain default = 48 // u6, 16 is normalized to '1'
+//Bit 15:9 reserved
+//Bit 8:0 reg_di_dcmb_cmb_sel_ofst default = 0 // s9, [-256, 255]
+#define DECOMB_WIND00 ((0x2d8a << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_di_dcmb_wnd00 default = 0 // u13, x0 for window 0, software control
+//Bit 15:13 reserved
+//Bit 12:0 reg_di_dcmb_wnd01 default = 719 // u13, x1 for window 0, HSIZE-1, software control
+#define DECOMB_WIND01 ((0x2d8b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_di_dcmb_wnd02 default = 0 // u13, y0 for window 0, software control
+//Bit 15:13 reserved
+//Bit 12:0 reg_di_dcmb_wnd03 default = 39 // u13, y1 for window 0, software control
+#define DECOMB_WIND10 ((0x2d8c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_di_dcmb_wnd10 default = 0 // u13, x0 for window 1, software control
+//Bit 15:13 reserved
+//Bit 12:0 reg_di_dcmb_wnd11 default = 719 // u13, x1 for window 1, HSIZE-1, software control
+#define DECOMB_WIND11 ((0x2d8d << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_di_dcmb_wnd12 default = 40 // u13, y0 for window 1, software control
+//Bit 15:13 reserved
+//Bit 12:0 reg_di_dcmb_wnd13 default = 239 // u13, y1 for window 1, VSIZE-1-40, software control
+#define DECOMB_MODE ((0x2d8e << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reg_di_dcmb_is_cmb_bef default = 1 // u1, 1: decide is_cmb before cmbing refine, 0: decide is_cmb after cmbing refine
+//Bit 14 reg_di_dcmb_en0 default = 1 // u1, enable decmobing for wind0
+//Bit 13 reg_di_dcmb_en1 default = 1 // u1, enable decmobing for wind1
+//Bit 12 reg_di_dcmb_en2 default = 1 // u1, enable decmobing for wind2
+//Bit 11:10 reg_di_dcmb_lpf_mod0 default = 2 // u2, get combing free pixels of wind0 by: 0, vertical lpf, 1, edge lpf, 2,3, ei data
+//Bit 9:8 reg_di_dcmb_lpf_mod1 default = 2 // u2, get combing free pixels of wind1 by: 0, vertical lpf, 1, edge lpf, 2,3, ei data
+//Bit 7:6 reg_di_dcmb_lpf_mod2 default = 0 // u2, get combing free pixels of wind2 by: 0, vertical lpf, 1, edge lpf, 2,3, ei data
+//Bit 5 reg_di_dcmb_cmb_sel0 default = 1 // u1, wind0 decmb based on: 0, vert cmb, 1, edge cmb
+//Bit 4 reg_di_dcmb_cmb_sel1 default = 1 // u1, wind1 decmb based on: 0, vert cmb, 1, edge cmb
+//Bit 3 reg_di_dcmb_cmb_sel2 default = 0 // u1, wind2 decmb based on: 0, vert cmb, 1, edge cmb
+//Bit 2 reg_di_dcmb_alp_mod0 default = 1 // u1, wind0 decmb alpha based on: 0, user-defined, 1, motion adaptive
+//Bit 1 reg_di_dcmb_alp_mod1 default = 1 // u1, wind1 decmb alpha based on: 0, user-defined, 1, motion adaptive
+//Bit 0 reg_di_dcmb_alp_mod2 default = 1 // u1, wind2 decmb alpha based on: 0, user-defined, 1, motion adaptive
+#define DECOMB_FRM_SIZE ((0x2d8f << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 hsize_in default = 1920 // u13, pic horz size in unit: pixel
+//Bit 15:13 reserved
+//Bit 12:0 vsize_in default = 1080 // u13, pic vert size in unit: pixel
+#define DECOMB_HV_BLANK ((0x2d90 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15:8 hblank_num default = 20 // u8, hor blank time
+//Bit 7:0 vblank_num default = 50 // u8, ver blank time
+//
+// Closing file: vpu_decomb_regs.h
+//
+// 0x98-0xa3
+//
+// Reading file: vpu_nr2_dpolar_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define NR2_POLAR3_MODE ((0x2d98 << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:18 reg_polar3_f02lpf_mod0 // unsigned , default = 3 low pass filter mode for field 0 and field2 before polar3 detection; 0 for no lpf, 1: [1 2 1]/4 vert lpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 no hlpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 [1 2 1]/4 hlpf
+//Bit 17:16 reg_polar3_f02lpf_mod1 // unsigned , default = 3 low pass filter mode for field 0 and field2 before polar3 detection; 0 for no lpf, 1: [1 2 1]/4 vert lpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 no hlpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 [1 2 1]/4 hlpf
+//Bit 15: 8 reg_polar3_dif02_thrd0 // unsigned , default = 5 threshold of dif for polar3 detection except for 32 detection, only do polar3 detection on obvious motion, [0] for luma, 1[1] for chroma
+//Bit 7: 0 reg_polar3_dif02_thrd1 // unsigned , default = 5 threshold of dif for polar3 detection except for 32 detection, only do polar3 detection on obvious motion, [0] for luma, 1[1] for chroma
+#define NR2_POLAR3_THRD ((0x2d99 << 2) + 0xff000000)
+//Bit 31:24 reg_polar3_txtf02_thrd0 // unsigned , default = 30 threshold to vertical f0f2 texture, if texture larger than this threshold, will not do the polar3 decision.
+//Bit 23:16 reg_polar3_txtf02_thrd1 // unsigned , default = 30 threshold to vertical f0f2 texture, if texture larger than this threshold, will not do the polar3 decision.
+//Bit 15: 8 reg_polar3_txtf1_thrd0 // unsigned , default = 20 threshold to vertical f1 texture, if texture larger than this threshold, will not do the polar3 decision.
+//Bit 7: 0 reg_polar3_txtf1_thrd1 // unsigned , default = 20 threshold to vertical f1 texture, if texture larger than this threshold, will not do the polar3 decision.
+#define NR2_POLAR3_PARA0 ((0x2d9a << 2) + 0xff000000)
+//Bit 31:28 reg_polar3_rate00 // unsigned , default = 6 delt = rate*dif02/32, e.g. f2<f0, if f1 within((f0+f2)/2 - delt), ((f0+f2)/2 + delt), then polar3_smoothmv++;
+//Bit 27:24 reg_polar3_rate01 // unsigned , default = 6 delt = rate*dif02/32, e.g. f2<f0, if f1 within((f0+f2)/2 - delt), ((f0+f2)/2 + delt), then polar3_smoothmv++;
+//Bit 23:20 reg_polar3_rate10 // unsigned , default = 8 delt = rate*dif02/32, e.g. f2-ofst1<f0, if f1<((f0+f2)/2 - delt), then polar3_m1++; if f1>((f0+f2)/2 + delt), then polar3_p1++;
+//Bit 19:16 reg_polar3_rate11 // unsigned , default = 8 delt = rate*dif02/32, e.g. f2-ofst1<f0, if f1<((f0+f2)/2 - delt), then polar3_m1++; if f1>((f0+f2)/2 + delt), then polar3_p1++;
+//Bit 15:12 reg_polar3_rate20 // unsigned , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset2), then polar3_m2++; if f1>((f0 + delt+ ofset2), then polar3_p2++;
+//Bit 11: 8 reg_polar3_rate21 // unsigned , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset2), then polar3_m2++; if f1>((f0 + delt+ ofset2), then polar3_p2++;
+//Bit 7: 1 reserved
+//Bit 0 reg_polar3_ro_reset // unsigned , default = 0 reset signal of the polar3 read only registers
+#define NR2_POLAR3_PARA1 ((0x2d9b << 2) + 0xff000000)
+//Bit 31:24 reg_polar3_rate30 // unsigned , default = 48 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset3) or f1>((f0 + delt+ofst3), then polar3_32++;
+//Bit 23:16 reg_polar3_rate31 // unsigned , default = 48 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset3) or f1>((f0 + delt+ofst3), then polar3_32++;
+//Bit 15:12 reg_polar3_ofst30 // signed , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt-ofst3) or f1>((f0 + delt+ofst3), then polar3_32++;
+//Bit 11: 8 reg_polar3_ofst31 // signed , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt-ofst3) or f1>((f0 + delt+ofst3), then polar3_32++;
+//Bit 7: 4 reg_polar3_ofst20 // signed , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset2), then polar3_m2++; if f1>((f0 + delt+ ofset2), then polar3_p2++;
+//Bit 3: 0 reg_polar3_ofst21 // signed , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset2), then polar3_m2++; if f1>((f0 + delt+ ofset2), then polar3_p2++;
+#define NR2_POLAR3_CTRL ((0x2d9c << 2) + 0xff000000)
+//Bit 31:24 reg_polar3_ofst10 // signed , default = 1
+//Bit 23:16 reg_polar3_ofst11 // signed , default = 1
+//Bit 15: 8 reg_polar3_h_mute // unsigned , default = 10 horizontal pixels to mute for left right sides for polar3 detection;
+//Bit 7: 0 reg_polar3_v_mute // unsigned , default = 10 vertical pixels to mute for top and bottom sides for polar3 detection;
+#define NR2_RO_POLAR3_NUMOFPIX ((0x2d9d << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_numofpix // unsigned , default = 0 number of pixels detected as polar3
+#define NR2_RO_POLAR3_SMOOTHMV ((0x2d9e << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_smoothmv // unsigned , default = 0 number of pixels with smooth mv, F(t) is close between avg of f(t-1) and f(t+1);
+#define NR2_RO_POLAR3_M1 ((0x2d9f << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_m1 // unsigned , default = 0 number of pixels with F(t) is close to f(t-1) instead of f(t+1), but in between [f(t-1), f(t+1)];
+#define NR2_RO_POLAR3_P1 ((0x2da0 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_p1 // unsigned , default = 0 number of pixels with F(t) is close to f(t+1) instead of f(t-1), but in between [f(t-1), f(t+1)];
+#define NR2_RO_POLAR3_M2 ((0x2da1 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_m2 // unsigned , default = 0 number of pixels with F(t) is close to f(t-1) instead of f(t+1), but out side of (f(t-1), f(t+1));
+#define NR2_RO_POLAR3_P2 ((0x2da2 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_p2 // unsigned , default = 0 number of pixels with F(t) is close to f(t+1) instead of f(t-1), but out side of (f(t-1), f(t+1));
+#define NR2_RO_POLAR3_32 ((0x2da3 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_32 // unsigned , default = 0 number of pixels with F(t) far from [f(t-1),f(t+1)] and f(t-1) is close to f(t+1);
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_nr2_dpolar_regs.h
+//
+// 0xa4-0xf7 / 0xff
+//
+// Reading file: vpu_nr4_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//========== nr4_drt_regs register begin ==========//
+#define NR4_DRT_CTRL ((0x2da4 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_ydrt_3line_ssd_gain // unsigned , default = 16 gain to max ssd normalized 16 as '1'
+//Bit 23:16 reg_nr4_ydrt_5line_ssd_gain // unsigned , default = 16 gain to max ssd normalized 16 as '1'
+//Bit 15 reserved
+//Bit 14:13 reg_nr4_drt_yhsad_mode // unsigned , default = 1 mode for luma horiztonal sad calc., 0: no vertical lpf, 1: vertical [1 2 1], 2 or 3: vertical [ 1 2 2 2 1] if 5 lines
+//Bit 12:11 reg_nr4_drt_chsad_mode // unsigned , default = 1 mode for chroma horiztonal sad calc., 0: no vertical lpf, 1: vertical [1 2 1], 2 or 3: vertical [ 1 2 2 2 1] if 5 lines
+//Bit 10 reg_nr4_drt_yhsad_hlpf // unsigned , default = 1 hlpf for luma hsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf
+//Bit 9 reg_nr4_drt_yvsad_hlpf // unsigned , default = 1 hlpf for luma vsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf
+//Bit 8 reg_nr4_drt_ydsad_hlpf // unsigned , default = 1 hlpf for luma dsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf
+//Bit 7 reg_nr4_drt_chsad_hlpf // unsigned , default = 1 hlpf for chrome hsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf
+//Bit 6 reg_nr4_drt_cvsad_hlpf // unsigned , default = 1 hlpf for chroma vsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf
+//Bit 5 reg_nr4_drt_cdsad_hlpf // unsigned , default = 1 hlpf for chroma dsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf
+//Bit 4 reg_nr4_ydrt_dif_mode // unsigned , default = 1 0:y_dif, 1: y_dif + (u_dif + v_dif)/2
+//Bit 3: 2 reg_nr4_cdrt_dif_mode // unsigned , default = 2 0:(u_dif + v_dif), 1: y_dif/4 + (u_dif + v_dif)*3/4, 2:y_dif/2 + (u_dif + v_dif)/2, 3: y_dif (not recommended)
+//Bit 1: 0 reserved
+#define NR4_DRT_YSAD_GAIN ((0x2da5 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_ysad_hrz_gain // unsigned , default = 16 gain for horizontal sad, 16 normalized to "1"
+//Bit 23:16 reg_nr4_ysad_diag_gain // unsigned , default = 20 gain for diagonal sad, 16 normalized to "1"
+//Bit 15: 8 reg_nr4_ysad_vrt_gain // unsigned , default = 16 gain for vertical sad, 16 normalized to "1"
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_drt_ysad_core_rate // unsigned , default = 6 rate of coring for sad(theta) - sad(theta+pi/2)*rate/64
+#define NR4_DRT_CSAD_GAIN ((0x2da6 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_csad_hrz_gain // unsigned , default = 16 gain for horizontal sad, 16 normalized to "1"
+//Bit 23:16 reg_nr4_csad_diag_gain // unsigned , default = 20 gain for diagonal sad, 16 normalized to "1"
+//Bit 15: 8 reg_nr4_csad_vrt_gain // unsigned , default = 16 gain for vertical sad, 16 normalized to "1"
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_drt_csad_core_rate // unsigned , default = 6 rate of coring for sad(theta) - sad(theta+pi/2)*rate/64
+#define NR4_DRT_SAD_ALP_CORE ((0x2da7 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:20 reg_nr4_ydrt_alp_core_rate // unsigned , default = 0 luma ratio to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 0/32
+//Bit 19:16 reg_nr4_cdrt_alp_core_rate // unsigned , default = 0 chroma ratio to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 0/32
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_ydrt_alp_core_ofst // unsigned , default = 10 luma offset to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 10
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_cdrt_alp_core_ofst // unsigned , default = 10 chroma offset to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 10
+#define NR4_DRT_ALP_MINMAX ((0x2da8 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_ydrt_alp_min // unsigned , default = 0 luma min value of alpha, dft = 0
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_ydrt_alp_max // unsigned , default = 63 luma max value of alpha, dft = 63
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_cdrt_alp_min // unsigned , default = 0 chroma min value of alpha, dft = 0
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_cdrt_alp_max // unsigned , default = 63 chroma max value of alpha, dft = 63
+//========== nr4_drt_regs register end ==========//
+//========== nr4_snr_regs register begin ==========//
+#define NR4_SNR_CTRL_REG ((0x2da9 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12 reg_nr4_bet2_sel // unsigned , default = 1
+//Bit 11: 9 reg_nr4_snr2_sel_mode // unsigned , default = 0 0: no filter, 1: adpgau, adp_drt_lpf blend; 2: adpgau, drt4_lpf blend; 3: adp_drt_lpf method, 4: drt4_lpf method, 5: adp_drt_ //original image blend, 6: drt4_lpf, original image blend, 7: adpgau method; dft=1
+//Bit 8 reg_nr4_snr2_gaulpf_mode // unsigned , default = 1 0: 3*5 or 5*5 gaussian lpf; 1: 3*3 (window size) gaussian lpf; dft=1
+//Bit 7: 6 reg_nr4_snr2_alpha0_sad_mode // unsigned , default = 3 0: max_sad*max_ssd; 1: max_sad*max_sad; 2: adp_max_sad*max_ssd; 3: adp_max_sad*adp_max_sad dft=3
+//Bit 5: 4 reg_nr4_snr2_alpha1_sad_mode // unsigned , default = 2 0: max_sad; 1: cross_max_sad; 2 or 3: adp_sad dft=2
+//Bit 3: 2 reserved
+//Bit 1: 0 reg_nr4_snr2_adp_drtlpf_mode // unsigned , default = 3 0: adp_drtlpf [2 1 1]/4, 1: adp_drtlpf [4 2 1 1]/8; 2: adp_drtlpf [2 2 2 1 1]/8; 3: adp_drtlpf [7 7 7 6 5]/32; dft=3;
+#define NR4_SNR_ALPHA0_MAX_MIN ((0x2daa << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:23 reg_nr4_snr2_alp0_ymin // unsigned , default = 127 normalized to 128 as '1'
+//Bit 22:16 reg_nr4_snr2_alp0_ymax // unsigned , default = 127 normalized to 128 as '1'
+//Bit 15:14 reserved
+//Bit 13: 7 reg_nr4_snr2_alp0_cmin // unsigned , default = 127 normalized to 128 as '1'
+//Bit 6: 0 reg_nr4_snr2_alp0_cmax // unsigned , default = 127 normalized to 128 as '1'
+#define NR4_ALP0C_ERR2CURV_LIMIT0 ((0x2dab << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_snr2_alp0_minerr_cpar0 // unsigned , default = 0 threshold0 of curve to map mierr to alp0 for chroma channel, this will be set value of flat region mierr that no need blur.
+//Bit 23:16 reg_nr4_snr2_alp0_minerr_cpar1 // unsigned , default = 25 threshold1 of curve to map mierr to alp0 for chroma channel,this will be set value of texture region mierr that can not blur.
+//Bit 15: 8 reg_nr4_snr2_alp0_minerr_cpar5 // unsigned , default = 40 rate0 (for mierr<th0) of curve to map mierr to alp0 for chroma channel. the larger of the value, the deep of the slope. 0~255.
+//Bit 7: 0 reg_nr4_snr2_alp0_minerr_cpar6 // unsigned , default = 40 rate1 (for mierr>th1) of curve to map mierr to alp0 for chroma channel. the larger of the value, the deep of the slope. 0~255.
+#define NR4_ALP0C_ERR2CURV_LIMIT1 ((0x2dac << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_snr2_alp0_minerr_cpar2 // unsigned , default = 127 level limit(for mierr<th0) of curve to map mierr to alp0 for chroma channel, that we can do for flat region. 0~255.
+//Bit 15: 8 reg_nr4_snr2_alp0_minerr_cpar3 // unsigned , default = 0 level limit(for th0<mierr<th1) of curve to map mierr to alp0 for chroma channel, that we can do for misc region. 0~255.
+//Bit 7: 0 reg_nr4_snr2_alp0_minerr_cpar4 // unsigned , default = 127 level limit(for mierr>th1) of curve to map mierr to alp0 for chroma channel, that we can do for texture region. 0~255.
+#define NR4_ALP0Y_ERR2CURV_LIMIT0 ((0x2dad << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_snr2_alp0_minerr_ypar0 // unsigned , default = 0 threshold0 of curve to map mierr to alp0 for luma channel, this will be set value of flat region mierr that no need blur. 0~255.
+//Bit 23:16 reg_nr4_snr2_alp0_minerr_ypar1 // unsigned , default = 25 threshold1 of curve to map mierr to alp0 for luma channel,this will be set value of texture region mierr that can not blur.
+//Bit 15: 8 reg_nr4_snr2_alp0_minerr_ypar5 // unsigned , default = 40 rate0 (for mierr<th0) of curve to map mierr to alp0 for luma channel. the larger of the value, the deep of the slope. 0~255.
+//Bit 7: 0 reg_nr4_snr2_alp0_minerr_ypar6 // unsigned , default = 40 rate1 (for mierr>th1) of curve to map mierr to alp0 for luma channel. the larger of the value, the deep of the slope. 0~255.
+#define NR4_ALP0Y_ERR2CURV_LIMIT1 ((0x2dae << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_snr2_alp0_minerr_ypar2 // unsigned , default = 127 level limit(for mierr<th0) of curve to map mierr to alp0 for luma channel, set to alp0 that we can do for flat region. 0~255.
+//Bit 15: 8 reg_nr4_snr2_alp0_minerr_ypar3 // unsigned , default = 0 level limit(for th0<mierr<th1) of curve to map mierr to alp0 for luma channel, alp0 that we can do for misc region. 0~255.
+//Bit 7: 0 reg_nr4_snr2_alp0_minerr_ypar4 // unsigned , default = 127 level limit(for mierr>th1) of curve to map mierr to alp0 for luma channel, alp0 that we can do for texture region. 0~255.
+#define NR4_SNR_ALPA1_RATE_AND_OFST ((0x2daf << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:18 reg_nr4_snr2_alp1_ycore_rate // unsigned , default = 0 normalized 64 as "1"
+//Bit 17:12 reg_nr4_snr2_alp1_ccore_rate // unsigned , default = 0 normalized 64 as "1"
+//Bit 11: 6 reg_nr4_snr2_alp1_ycore_ofst // signed , default = 3 normalized 64 as "1"
+//Bit 5: 0 reg_nr4_snr2_alp1_ccore_ofst // signed , default = 3 normalized 64 as "1"
+#define NR4_SNR_ALPHA1_MAX_MIN ((0x2db0 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:18 reg_nr4_snr2_alp1_ymin // unsigned , default = 0 normalized to 64 as '1'
+//Bit 17:12 reg_nr4_snr2_alp1_ymax // unsigned , default = 63 normalized to 64 as '1'
+//Bit 11: 6 reg_nr4_snr2_alp1_cmin // unsigned , default = 0 normalized to 64 as '1'
+//Bit 5: 0 reg_nr4_snr2_alp1_cmax // unsigned , default = 63 normalized to 64 as '1'
+#define NR4_ALP1C_ERR2CURV_LIMIT0 ((0x2db1 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_snr2_alp1_minerr_cpar0 // unsigned , default = 0 annel, this will be set value of flat region mierr that no need directional NR. 0~255.
+//Bit 23:16 reg_nr4_snr2_alp1_minerr_cpar1 // unsigned , default = 24 hannel,this will be set value of texture region mierr that can not do directional NR. 0~255.
+//Bit 15: 8 reg_nr4_snr2_alp1_minerr_cpar5 // unsigned , default = 0 a/chroma channel. the larger of the value, the deep of the slope.
+//Bit 7: 0 reg_nr4_snr2_alp1_minerr_cpar6 // unsigned , default = 20 a/chroma channel. the larger of the value, the deep of the slope. 0~255
+#define NR4_ALP1C_ERR2CURV_LIMIT1 ((0x2db2 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_snr2_alp1_minerr_cpar2 // unsigned , default = 0 will be set to alp1 that we can do for flat region. 0~255.
+//Bit 15: 8 reg_nr4_snr2_alp1_minerr_cpar3 // unsigned , default = 16 this will be set to alp1 that we can do for misc region. 0~255.
+//Bit 7: 0 reg_nr4_snr2_alp1_minerr_cpar4 // unsigned , default = 63 will be set to alp1 that we can do for texture region. 0~255.255 before
+#define NR4_ALP1Y_ERR2CURV_LIMIT0 ((0x2db3 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_snr2_alp1_minerr_ypar0 // unsigned , default = 0 thra/chroma channel, this will be set value of flat region mierr that no need directional NR. 0~255.
+//Bit 23:16 reg_nr4_snr2_alp1_minerr_ypar1 // unsigned , default = 24 thra/chroma channel,this will be set value of texture region mierr that can not do directional NR. 0~255.
+//Bit 15: 8 reg_nr4_snr2_alp1_minerr_ypar5 // unsigned , default = 0 ratlp1 for luma/chroma channel. the larger of the value, the deep of the slope.
+//Bit 7: 0 reg_nr4_snr2_alp1_minerr_ypar6 // unsigned , default = 20 ratlp1 for luma/chroma channel. the larger of the value, the deep of the slope. 0~255
+#define NR4_ALP1Y_ERR2CURV_LIMIT1 ((0x2db4 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_snr2_alp1_minerr_ypar2 // unsigned , default = 0 lev to alp1 for luma/chroma channel, this will be set to alp1 that we can do for flat region. 0~255.
+//Bit 15: 8 reg_nr4_snr2_alp1_minerr_ypar3 // unsigned , default = 16 levierr to alp1 for luma/chroma channel, this will be set to alp1 that we can do for misc region. 0~255.
+//Bit 7: 0 reg_nr4_snr2_alp1_minerr_ypar4 // unsigned , default = 63 lev to alp1 for luma/chroma channel, this will be set to alp1 that we can do for texture region. 0~255.255 before
+//========== nr4_snr_regs register end ==========//
+//========== nr4_tnr_regs register begin ==========//
+#define NR4_MTN_CTRL ((0x2db5 << 2) + 0xff000000)
+//Bit 31: 2 reserved
+//Bit 1 reg_nr4_mtn_ref_en // unsigned , default = 1 enable motion refinement, dft = 1
+//Bit 0 reg_nr4_mtn_ref_bet_sel // unsigned , default = 0 beta selection mode for motion refinement, 0: beta1, 1: beta2, dft = 0
+#define NR4_MTN_REF_PAR0 ((0x2db6 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_mtn_ref_par0 // unsigned , default = 24 par0 for beta to gain, dft =
+//Bit 23:16 reg_nr4_mtn_ref_par1 // unsigned , default = 60 par1 for beta to gain, dft =
+//Bit 15: 8 reg_nr4_mtn_ref_par2 // unsigned , default = 4 par2 for beta to gain, dft =
+//Bit 7: 0 reg_nr4_mtn_ref_par3 // unsigned , default = 32 par3 for beta to gain, dft =
+#define NR4_MTN_REF_PAR1 ((0x2db7 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_mtn_ref_par4 // unsigned , default = 128 par4 for beta to gain, dft =
+//Bit 15: 8 reg_nr4_mtn_ref_par5 // unsigned , default = 40 par5 for beta to gain, dft =
+//Bit 7: 0 reg_nr4_mtn_ref_par6 // unsigned , default = 20 par6 for beta to gain, dft =
+//========== nr4_tnr_regs register end ==========//
+//========== nr4_mcnr_regs register begin ==========//
+#define NR4_MCNR_LUMA_ENH_CTRL ((0x2db8 << 2) + 0xff000000)
+//Bit 31: 4 reserved
+//Bit 3 reg_nr4_luma_plus_en // unsigned , default = 1 enable luma enhancement, dft = 1
+//Bit 2 reg_nr4_luma_plus_wt_mode // unsigned , default = 1 luma weight calc mode, 0:sqrt(1+x^2), 1: 1+abs(x), dft = 0
+//Bit 1: 0 reg_nr4_luma_plus_orient_mode // unsigned , default = 1 0: only use previous orient for pre and cur luma plus, 1: 0: only use current orient for pre and cur luma plus
+#define NR4_MCNR_LUMA_STAT_LIMTX ((0x2db9 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_nr4_luma_plus_xst // unsigned , default = 8 start for luma plus statistic, dft = 8
+//Bit 15:14 reserved
+//Bit 13: 0 reg_nr4_luma_plus_xed // unsigned , default = 711 end for luma plus statistic, dft = HSIZE-8-1;
+#define NR4_MCNR_LUMA_STAT_LIMTY ((0x2dba << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_nr4_luma_plus_yst // unsigned , default = 8 start for luma plus statistic, dft = 8
+//Bit 15:14 reserved
+//Bit 13: 0 reg_nr4_luma_plus_yed // unsigned , default = 231 end for luma plus statistic, dft = VSIZE-8-1
+#define NR4_MCNR_LUMA_DIF_CALC ((0x2dbb << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_luma_plus_ugain // unsigned , default = 8 U's gain for luma enhancement, 16 normalized as '1'
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_luma_plus_vgain // unsigned , default = 8 V's gain for luma enhancement, 16 normalized as '1'
+//Bit 15: 8 reg_nr4_luma_plus_ycor_thd // unsigned , default = 2 Y coring threshold for difference calc., dft = 0
+//Bit 7: 0 reg_nr4_luma_plus_ccor_thd // unsigned , default = 0 C coring threshold for difference calc., dft = 0
+#define NR4_MCNR_LUMAPRE_CAL_PRAM ((0x2dbc << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_nr4_pre_u_orient // signed , default = 0 orientation of previous U, initial to 0, and will be updated by software
+//Bit 23:18 reserved
+//Bit 17:16 reg_nr4_pre_v_orient // signed , default = 0 orientation of previous V, initial to 0, and will be updated by software
+//Bit 15: 8 reg_nr4_pre_u_mean // unsigned , default = 0 mean of previous U, initial to 0, and will be updated by software
+//Bit 7: 0 reg_nr4_pre_v_mean // unsigned , default = 0 mean of previousV, initial to 0, and will be updated by software
+#define NR4_MCNR_LUMACUR_CAL_PRAM ((0x2dbd << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_nr4_cur_u_orient // signed , default = 0 orientation of current U, initial to 0, and will be updated by software
+//Bit 23:18 reserved
+//Bit 17:16 reg_nr4_cur_v_orient // signed , default = 0 orientation of current V, initial to 0, and will be updated by software
+//Bit 15: 8 reg_nr4_cur_u_mean // unsigned , default = 0 mean of current U, initial to 0, and will be updated by software
+//Bit 7: 0 reg_nr4_cur_v_mean // unsigned , default = 0 mean of current, initial to 0, and will be updated by software
+#define NR4_MCNR_MV_CTRL_REG ((0x2dbe << 2) + 0xff000000)
+//Bit 31:14 reserved
+//Bit 13:12 reg_nr4_sad_bitw // unsigned , default = 2 sad bit width (8 + x) before clip to u8, dft = 1
+//Bit 11: 4 reg_nr4_glb_gain // unsigned , default = 64 global gain calc. by software, 64 is normalized as '1'
+//Bit 3: 0 reg_nr4_mv_err_rsft // unsigned , default = 8 right shift for mv err calc., dft = 9
+#define NR4_MCNR_MV_GAIN0 ((0x2dbf << 2) + 0xff000000)
+//Bit 31:28 reg_nr4_lftmvx_gain // unsigned , default = 1 left mvx gain for err calc., dft = 1
+//Bit 27:24 reg_nr4_lftmvy_gain // unsigned , default = 1 left mvy gain for err calc., dft = 1
+//Bit 23:20 reg_nr4_zmvx_gain // unsigned , default = 5 zero mvx gain for err calc., dft = 2
+//Bit 19:16 reg_nr4_zmvy_gain // unsigned , default = 5 zero mvy gain for err calc., dft = 4
+//Bit 15:12 reg_nr4_lmvx0_gain // unsigned , default = 2 line mvx0 gain for err calc., dft = 1
+//Bit 11: 8 reg_nr4_lmvx1_gain // unsigned , default = 2 line mvx1 gain for err calc., dft = 1
+//Bit 7: 4 reg_nr4_lmvy0_gain // unsigned , default = 2 line mvy0 gain for err calc., dft = 1
+//Bit 3: 0 reg_nr4_lmvy1_gain // unsigned , default = 2 line mvy1 gain for err calc., dft = 1
+#define NR4_MCNR_LMV_PARM ((0x2dc0 << 2) + 0xff000000)
+//Bit 31:28 reg_nr4_lmv_rt0 // unsigned , default = 3 ratio of max lmv
+//Bit 27:24 reg_nr4_lmv_rt1 // unsigned , default = 3 ratio of second max lmv
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_lmv_num_lmt0 // unsigned , default = 16 lmv0 least/limit number of (total number - zero_bin)
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_lmv_num_lmt1 // unsigned , default = 8 lmv1 least/limit number of (total number - zero_bin - max0)
+//Bit 7: 2 reserved
+//Bit 1: 0 reg_nr4_max_sad_rng // unsigned , default = 1 search range of max2 sad in small region, dft = 1
+#define NR4_MCNR_ALP0_REG ((0x2dc1 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25 reg_nr4_alp0_fail_chk // unsigned , default = 1 enable check for alp0 fail status
+//Bit 24 reg_nr4_bet0_coef_ref_en // unsigned , default = 1 bet1 refinement by coef_blt
+//Bit 23:16 reg_nr4_alp0_posad_gain // unsigned , default = 255 the sad (norm) gain for pixel pointed by MV;
+//Bit 15:10 reserved
+//Bit 9: 8 reg_nr4_alp0_norm_mode // unsigned , default = 0 alp0 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_alp0_norm_gain // unsigned , default = 16 alp0 gain for sad norm, '32' as '1', dft = 1
+#define NR4_MCNR_ALP1_AND_BET0_REG ((0x2dc2 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_nr4_alp1_norm_mode // unsigned , default = 3 alp1 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_alp1_norm_gain // unsigned , default = 3 alp1 gain for sad norm, '32' as '1', dft = 1
+//Bit 15:10 reserved
+//Bit 9: 8 reg_nr4_bet0_norm_mode // unsigned , default = 3 bet0 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bet0_norm_gain // unsigned , default = 8 bet0 gain for sad norm, '32' as '1', dft = 1
+#define NR4_MCNR_BET1_AND_BET2_REG ((0x2dc3 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_nr4_bet1_norm_mode // unsigned , default = 3 bet1 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_bet1_norm_gain // unsigned , default = 8 bet1 gain for sad norm, '32' as '1', dft = 1
+//Bit 15:10 reserved
+//Bit 9: 8 reg_nr4_bet2_norm_mode // unsigned , default = 0 bet2 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bet2_norm_gain // unsigned , default = 16 bet2 gain for sad norm, '32' as '1', dft = 1
+#define NR4_MCNR_AC_DC_CRTL ((0x2dc4 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15:12 reserved
+//Bit 11 reg_nr4_dc_mode // unsigned , default = 1 mode for dc selection,0: Y_lpf, 1: Y_lpf + (U_Lpf+V_lpf)/2,
+//Bit 10 reg_nr4_ac_mode // unsigned , default = 1 mode for ac selection, 0: Y_abs_dif, 1: Y_abs_dif + (U_abs_dif + V_abs_dif)/2
+//Bit 9 reg_nr4_dc_sel // unsigned , default = 0 selection mode for dc value, 0: 3x5, 1: 5x5, dft = 1
+//Bit 8 reg_nr4_ac_sel // unsigned , default = 0 selection mode for ac value, 0: 3x5, 1: 5x5, dft = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_nr4_dc_shft // unsigned , default = 2 right shift for dc value, dft = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_nr4_ac_shft // unsigned , default = 0 right shift for ac value, dft = 2
+#define NR4_MCNR_CM_CTRL0 ((0x2dc5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28 reg_nr4_cm_skin_prc_bet0 // unsigned , default = 0 enable skin tone processing for mcnr bet0 calc., dft = 1
+//Bit 27:26 reg_nr4_cm_chrm_sel // unsigned , default = 1 chrome selection for color match, 0: 1x1, 1: 3X3LPF, 2: 3x5LPF, 3: 5x5LPF for 5lines, 3x5LPF for 3lines, dft = 3
+//Bit 25:24 reg_nr4_cm_luma_sel // unsigned , default = 1 luma selection for color match, 0: 1x1, 1: 3X3LPF, 2: 3x5LPF, 3: 5x5LPF for 5lines, 3x5LPF for 3lines, dft = 3
+//Bit 23:21 reg_nr4_cm_skin_rshft_bet0 // unsigned , default = 3 right shift for bet0's skin color gains, dft = 3
+//Bit 20 reg_nr4_cm_var_sel // unsigned , default = 1 variation selection for color match, 0: 3x5, 1: 5x5 for 5lines, 3x5 for 3lines, dft = 1
+//Bit 19 reg_nr4_cm_green_prc_bet0 // unsigned , default = 1 enable green processing for mcnr bet0 calc., dft = 1
+//Bit 18:16 reg_nr4_cm_green_rshft_bet0 // unsigned , default = 4 right shift for bet0's green color gains, dft = 4
+//Bit 15:14 reg_nr4_preflt_mod // unsigned , default = 2 pre filter mode in mcnr, 0: mv pointed pixel, 1: bilater filter
+//Bit 13:12 reg_nr4_alp1_mode // unsigned , default = 1 mode for alpha1's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad
+//Bit 11:10 reserved
+//Bit 9: 8 reg_nr4_bet0_mode // unsigned , default = 0 mode for bet0's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad, else: (co sad) - (min sad)
+//Bit 7: 6 reserved
+//Bit 5: 4 reg_nr4_bet1_mode // unsigned , default = 2 mode for bet1's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad, else: (co sad) - (min sad)
+//Bit 3: 2 reserved
+//Bit 1: 0 reg_nr4_bet2_mode // unsigned , default = 1 mode for bet2's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad, else: (co sad) - (min sad)
+#define NR4_MCNR_CM_PRAM ((0x2dc6 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29 reg_nr4_cm_blue_prc_alp0 // unsigned , default = 1 enable blue processing for mcnr alpha0 calc., dft = 1
+//Bit 28 reg_nr4_cm_blue_prc_alp1 // unsigned , default = 1 enable blue processing for mcnr alpha1 calc., dft = 1
+//Bit 27 reg_nr4_cm_skin_prc_alp0 // unsigned , default = 1 enable skin tone processing for mcnr alpha0 calc., dft = 1
+//Bit 26 reg_nr4_cm_green_prc_alp0 // unsigned , default = 1 enable green processing for mcnr alpha0 clac., dft = 1
+//Bit 25 reg_nr4_cm_skin_prc_alp1 // unsigned , default = 1 enable skin tone processing for mcnr alpha0 calc., dft = 1
+//Bit 24 reg_nr4_cm_green_prc_alp1 // unsigned , default = 1 enable green processing for mcnr alpha1 clac., dft = 1
+//Bit 23:20 reg_nr4_cm_blue_hue_st // unsigned , default = 13 hue start of blue, dft =
+//Bit 19:16 reg_nr4_cm_blue_hue_ed // unsigned , default = 15 hue end of blue, dft =
+//Bit 15:12 reg_nr4_cm_green_hue_st // unsigned , default = 7 hue start of green, dft =
+//Bit 11: 8 reg_nr4_cm_green_hue_ed // unsigned , default = 10 hue end of green, dft =
+//Bit 7: 4 reg_nr4_cm_skin_hue_st // unsigned , default = 5 hue start of skin, dft =
+//Bit 3: 0 reg_nr4_cm_skin_hue_ed // unsigned , default = 6 hue end of skin, dft =
+#define NR4_MCNR_CM_RSHFT_ALP0 ((0x2dc7 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:25 reg_nr4_cm_blue_rshft_bet0 // unsigned , default = 5 right shift for bet0's blue color gains, dft = 5
+//Bit 24 reg_nr4_cm_blue_prc_bet0 // unsigned , default = 1 enable blue processing for mcnr bet0 calc., dft = 1
+//Bit 23 reserved
+//Bit 22:20 reg_nr4_cm_blue_rshft_alp0 // unsigned , default = 5 right shift for alpha0/1's blue color gains, dft = 5
+//Bit 19 reserved
+//Bit 18:16 reg_nr4_cm_blue_rshft_alp1 // unsigned , default = 5 right shift for alpha0/1's blue color gains, dft = 5
+//Bit 15 reserved
+//Bit 14:12 reg_nr4_cm_green_rshft_alp0 // unsigned , default = 4 right shift for alpha0/1's green color gains, dft = 4
+//Bit 11 reserved
+//Bit 10: 8 reg_nr4_cm_green_rshft_alp1 // unsigned , default = 4 right shift for alpha0/1's green color gains, dft = 4
+//Bit 7 reserved
+//Bit 6: 4 reg_nr4_cm_skin_rshft_alp0 // unsigned , default = 3 right shift for alpha0/1's skin color gains, dft = 3
+//Bit 3 reserved
+//Bit 2: 0 reg_nr4_cm_skin_rshft_alp1 // unsigned , default = 3 right shift for alpha0/1's skin color gains, dft = 3
+#define NR4_MCNR_BLUE_CENT ((0x2dc8 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_blue_centx // unsigned , default = 157 x coordinate of center of blue, dft =
+//Bit 15: 8 reserved
+//Bit 7: 0 reg_nr4_cm_blue_centy // unsigned , default = 110 y coordinate of center of blue, dft =
+#define NR4_MCNR_BLUE_GAIN_PAR0 ((0x2dc9 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_cm_blue_gain_par0 // unsigned , default = 32 par0 for blue gain, dft =
+//Bit 23:16 reg_nr4_cm_blue_gain_par1 // unsigned , default = 255 par1 for blue gain, dft =
+//Bit 15: 8 reg_nr4_cm_blue_gain_par2 // unsigned , default = 4 par2 for blue gain, dft =
+//Bit 7: 0 reg_nr4_cm_blue_gain_par3 // unsigned , default = 32 par3 for blue gain, dft =
+#define NR4_MCNR_BLUE_GAIN_PAR1 ((0x2dca << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_blue_gain_par4 // unsigned , default = 32 par4 for blue gain, dft =
+//Bit 15: 8 reg_nr4_cm_blue_gain_par5 // unsigned , default = 32 par5 for blue gain, dft =
+//Bit 7: 0 reg_nr4_cm_blue_gain_par6 // unsigned , default = 0 par6 for blue gain, dft =
+#define NR4_MCNR_CM_BLUE_CLIP0 ((0x2dcb << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_blue_luma_min // unsigned , default = 40 luma min for blue color matching, dft =
+//Bit 15: 8 reserved
+//Bit 7: 0 reg_nr4_cm_blue_luma_max // unsigned , default = 180 luma max for blue color matching, dft =
+#define NR4_MCNR_CM_BLUE_CLIP1 ((0x2dcc << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_cm_blue_sat_min // unsigned , default = 5 saturation min for blue color matching, dft =
+//Bit 23:16 reg_nr4_cm_blue_sat_max // unsigned , default = 255 saturation max for blue color matching, dft =
+//Bit 15: 8 reg_nr4_cm_blue_var_min // unsigned , default = 0 variation min for blue color matching, dft =
+//Bit 7: 0 reg_nr4_cm_blue_var_max // unsigned , default = 12 variation max for blue color matching, dft =
+#define NR4_MCNR_GREEN_CENT ((0x2dcd << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_green_centx // unsigned , default = 114 x coordinate of center of green, dft =
+//Bit 15: 8 reserved
+//Bit 7: 0 reg_nr4_cm_green_centy // unsigned , default = 126 y coordinate of center of green, dft =
+#define NR4_MCNR_GREEN_GAIN_PAR0 ((0x2dce << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_cm_green_gain_par0 // unsigned , default = 16 par0 for green gain, dft =
+//Bit 23:16 reg_nr4_cm_green_gain_par1 // unsigned , default = 255 par1 for green gain, dft =
+//Bit 15: 8 reg_nr4_cm_green_gain_par2 // unsigned , default = 255 par2 for green gain, dft =
+//Bit 7: 0 reg_nr4_cm_green_gain_par3 // unsigned , default = 16 par3 for green gain, dft =
+#define NR4_MCNR_GREEN_GAIN_PAR1 ((0x2dcf << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_green_gain_par4 // unsigned , default = 16 par4 for green gain, dft =
+//Bit 15: 8 reg_nr4_cm_green_gain_par5 // unsigned , default = 128 par5 for green gain, dft =
+//Bit 7: 0 reg_nr4_cm_green_gain_par6 // unsigned , default = 0 par6 for green gain, dft =
+#define NR4_MCNR_GREEN_CLIP0 ((0x2dd0 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_green_luma_min // unsigned , default = 40 luma min for green color matching, dft =
+//Bit 15: 8 reserved
+//Bit 7: 0 reg_nr4_cm_green_luma_max // unsigned , default = 160 luma max for green color matching, dft =
+#define NR4_MCNR_GREEN_CLIP2 ((0x2dd1 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_cm_green_sat_min // unsigned , default = 4 saturation min for green color matching, dft =
+//Bit 23:16 reg_nr4_cm_green_sat_max // unsigned , default = 255 saturation max for green color matching, dft =
+//Bit 15: 8 reg_nr4_cm_green_var_min // unsigned , default = 0 variation min for green color matching, dft =
+//Bit 7: 0 reg_nr4_cm_green_var_max // unsigned , default = 12 variation max for green color matching, dft =
+#define NR4_MCNR_SKIN_CENT ((0x2dd2 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_skin_centx // unsigned , default = 112 x coordinate of center of skin tone, dft =
+//Bit 15: 8 reserved
+//Bit 7: 0 reg_nr4_cm_skin_centy // unsigned , default = 149 y coordinate of center of skin tone, dft =
+#define NR4_MCNR_SKIN_GAIN_PAR0 ((0x2dd3 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_cm_skin_gain_par0 // unsigned , default = 20 par0 for skin gain, dft =
+//Bit 23:16 reg_nr4_cm_skin_gain_par1 // unsigned , default = 255 par1 for skin gain, dft =
+//Bit 15: 8 reg_nr4_cm_skin_gain_par2 // unsigned , default = 255 par2 for skin gain, dft =
+//Bit 7: 0 reg_nr4_cm_skin_gain_par3 // unsigned , default = 8 par3 for skin gain, dft =
+#define NR4_MCNR_SKIN_GAIN_PAR1 ((0x2dd4 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_skin_gain_par4 // unsigned , default = 8 par4 for skin gain, dft =
+//Bit 15: 8 reg_nr4_cm_skin_gain_par5 // unsigned , default = 128 par5 for skin gain, dft =
+//Bit 7: 0 reg_nr4_cm_skin_gain_par6 // unsigned , default = 0 par6 for skin gain, dft =
+#define NR4_MCNR_SKIN_CLIP0 ((0x2dd5 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_skin_luma_min // unsigned , default = 40 luma min for skin color matching, dft =
+//Bit 15: 8 reserved
+//Bit 7: 0 reg_nr4_cm_skin_luma_max // unsigned , default = 180 luma max for skin color matching, dft =
+#define NR4_MCNR_SKIN_CLIP1 ((0x2dd6 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_cm_skin_sat_min // unsigned , default = 5 saturation min for skin color matching, dft =
+//Bit 23:16 reg_nr4_cm_skin_sat_max // unsigned , default = 255 saturation max for skin color matching, dft =
+//Bit 15: 8 reg_nr4_cm_skin_var_min // unsigned , default = 0 variation min for skin color matching, dft =
+//Bit 7: 0 reg_nr4_cm_skin_var_max // unsigned , default = 12 variation max for skin color matching, dft =
+#define NR4_MCNR_ALP1_GLB_CTRL ((0x2dd7 << 2) + 0xff000000)
+//Bit 31 reg_nr4_alp1_glb_gain_en // unsigned , default = 0 alp1 adjust by global gain, dft = 1
+//Bit 30:28 reg_nr4_alp1_glb_gain_lsft // unsigned , default = 6 alp1 left shift before combine with global gain
+//Bit 27 reg_nr4_bet0_glb_gain_en // unsigned , default = 1 bet0 adjust by global gain, dft = 1
+//Bit 26:24 reg_nr4_bet0_glb_gain_lsft // unsigned , default = 6 bet1 left shift before combine with global gain
+//Bit 23 reg_nr4_bet1_glb_gain_en // unsigned , default = 0 bet1 adjust by global gain, dft = 0
+//Bit 22:20 reg_nr4_bet1_glb_gain_lsft // unsigned , default = 6 bet1 left shift before combine with global gain
+//Bit 19 reg_nr4_bet2_glb_gain_en // unsigned , default = 1 bet2 adjust by global gain, dft = 1
+//Bit 18:16 reg_nr4_bet2_glb_gain_lsft // unsigned , default = 6 bet2 left shift before combine with global gain
+//Bit 15 reg_nr4_alp1_ac_en // unsigned , default = 1 alp1 adjust by ac, dft = 1
+//Bit 14:12 reg_nr4_alp1_ac_lsft // unsigned , default = 5 alp1 left shift before combine with ac
+//Bit 11 reg_nr4_bet0_ac_en // unsigned , default = 0 bet0 adjust by ac, dft = 1
+//Bit 10: 8 reg_nr4_bet0_ac_lsft // unsigned , default = 5 bet0 left shift before combine with ac
+//Bit 7 reg_nr4_bet1_ac_en // unsigned , default = 0 bet1 adjust by ac, dft = 1
+//Bit 6: 4 reg_nr4_bet1_ac_lsft // unsigned , default = 5 bet1 left shift before combine with ac
+//Bit 3 reg_nr4_bet2_ac_en // unsigned , default = 0 bet2 adjust by ac, dft = 1
+//Bit 2: 0 reg_nr4_bet2_ac_lsft // unsigned , default = 5 bet2 left shift before combine with ac
+#define NR4_MCNR_DC2NORM_LUT0 ((0x2dd8 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:24 reg_nr4_dc2norm_lut0 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+//Bit 23:21 reserved
+//Bit 20:16 reg_nr4_dc2norm_lut1 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+//Bit 15:13 reserved
+//Bit 12: 8 reg_nr4_dc2norm_lut2 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+//Bit 7: 5 reserved
+//Bit 4: 0 reg_nr4_dc2norm_lut3 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+#define NR4_MCNR_DC2NORM_LUT1 ((0x2dd9 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:24 reg_nr4_dc2norm_lut4 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+//Bit 23:21 reserved
+//Bit 20:16 reg_nr4_dc2norm_lut5 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+//Bit 15:13 reserved
+//Bit 12: 8 reg_nr4_dc2norm_lut6 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+//Bit 7: 5 reserved
+//Bit 4: 0 reg_nr4_dc2norm_lut7 // unsigned , default = 12 normal 0~16, dc to norm for alpha adjust, dft =
+#define NR4_MCNR_DC2NORM_LUT2 ((0x2dda << 2) + 0xff000000)
+//Bit 31: 5 reserved
+//Bit 4: 0 reg_nr4_dc2norm_lut8 // unsigned , default = 8 normal 0~16, dc to norm for alpha adjust, dft =
+#define NR4_MCNR_AC2NORM_LUT0 ((0x2ddb << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:24 reg_nr4_ac2norm_lut0 // unsigned , default = 2 normal 0~16, ac to norm for alpha adjust, dft =
+//Bit 23:21 reserved
+//Bit 20:16 reg_nr4_ac2norm_lut1 // unsigned , default = 16 normal 0~16, ac to norm for alpha adjust, dft =
+//Bit 15:13 reserved
+//Bit 12: 8 reg_nr4_ac2norm_lut2 // unsigned , default = 16 normal 0~16, ac to norm for alpha adjust, dft =
+//Bit 7: 5 reserved
+//Bit 4: 0 reg_nr4_ac2norm_lut3 // unsigned , default = 12 normal 0~16, ac to norm for alpha adjust, dft =
+#define NR4_MCNR_AC2NORM_LUT1 ((0x2ddc << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:24 reg_nr4_ac2norm_lut4 // unsigned , default = 4 normal 0~16, ac to norm for alpha adjust, dft =
+//Bit 23:21 reserved
+//Bit 20:16 reg_nr4_ac2norm_lut5 // unsigned , default = 2 normal 0~16, ac to norm for alpha adjust, dft =
+//Bit 15:13 reserved
+//Bit 12: 8 reg_nr4_ac2norm_lut6 // unsigned , default = 1 normal 0~16, ac to norm for alpha adjust, dft =
+//Bit 7: 5 reserved
+//Bit 4: 0 reg_nr4_ac2norm_lut7 // unsigned , default = 1 normal 0~16, ac to norm for alpha adjust, dft =
+#define NR4_MCNR_AC2NORM_LUT2 ((0x2ddd << 2) + 0xff000000)
+//Bit 31: 5 reserved
+//Bit 4: 0 reg_nr4_ac2norm_lut8 // unsigned , default = 1 normal 0~16, ac to norm for alpha adjust, dft =
+#define NR4_MCNR_SAD2ALP0_LUT0 ((0x2dde << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp0_lut0 // unsigned , default = 255 sad to alpha0 for temporal pixel value, dft = 255
+//Bit 23:16 reg_nr4_sad2alp0_lut1 // unsigned , default = 252 sad to alpha0 for temporal pixel value, dft = 252
+//Bit 15: 8 reg_nr4_sad2alp0_lut2 // unsigned , default = 249 sad to alpha0 for temporal pixel value, dft = 249
+//Bit 7: 0 reg_nr4_sad2alp0_lut3 // unsigned , default = 235 sad to alpha0 for temporal pixel value, dft = 70
+#define NR4_MCNR_SAD2ALP0_LUT1 ((0x2ddf << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp0_lut4 // unsigned , default = 185 sad to alpha0 for temporal pixel value, dft = 12
+//Bit 23:16 reg_nr4_sad2alp0_lut5 // unsigned , default = 70 sad to alpha0 for temporal pixel value, dft = 1
+//Bit 15: 8 reg_nr4_sad2alp0_lut6 // unsigned , default = 14 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 7: 0 reg_nr4_sad2alp0_lut7 // unsigned , default = 1 sad to alpha0 for temporal pixel value, dft = 0
+#define NR4_MCNR_SAD2ALP0_LUT2 ((0x2de0 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp0_lut8 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 23:16 reg_nr4_sad2alp0_lut9 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 15: 8 reg_nr4_sad2alp0_lut10 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 7: 0 reg_nr4_sad2alp0_lut11 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+#define NR4_MCNR_SAD2ALP0_LUT3 ((0x2de1 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp0_lut12 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 23:16 reg_nr4_sad2alp0_lut13 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 15: 8 reg_nr4_sad2alp0_lut14 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 7: 0 reg_nr4_sad2alp0_lut15 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+#define NR4_MCNR_SAD2ALP1_LUT0 ((0x2de2 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp1_lut0 // unsigned , default = 192 sad to alpha1 for temporal blending, dft = 128
+//Bit 23:16 reg_nr4_sad2alp1_lut1 // unsigned , default = 160 sad to alpha1 for temporal blending, dft = 128
+//Bit 15: 8 reg_nr4_sad2alp1_lut2 // unsigned , default = 128 sad to alpha1 for temporal blending, dft = 128
+//Bit 7: 0 reg_nr4_sad2alp1_lut3 // unsigned , default = 96 sad to alpha1 for temporal blending, dft = 64
+#define NR4_MCNR_SAD2ALP1_LUT1 ((0x2de3 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp1_lut4 // unsigned , default = 64 sad to alpha1 for temporal blending, dft = 64
+//Bit 23:16 reg_nr4_sad2alp1_lut5 // unsigned , default = 32 sad to alpha1 for temporal blending, dft = 128
+//Bit 15: 8 reg_nr4_sad2alp1_lut6 // unsigned , default = 16 sad to alpha1 for temporal blending, dft = 255
+//Bit 7: 0 reg_nr4_sad2alp1_lut7 // unsigned , default = 8 sad to alpha1 for temporal blending, dft = 255
+#define NR4_MCNR_SAD2ALP1_LUT2 ((0x2de4 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp1_lut8 // unsigned , default = 4 sad to alpha1 for temporal blending, dft = 255
+//Bit 23:16 reg_nr4_sad2alp1_lut9 // unsigned , default = 0 sad to alpha1 for temporal blending, dft = 255
+//Bit 15: 8 reg_nr4_sad2alp1_lut10 // unsigned , default = 16 sad to alpha1 for temporal blending, dft = 255
+//Bit 7: 0 reg_nr4_sad2alp1_lut11 // unsigned , default = 64 sad to alpha1 for temporal blending, dft = 255
+#define NR4_MCNR_SAD2ALP1_LUT3 ((0x2de5 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp1_lut12 // unsigned , default = 96 sad to alpha1 for temporal blending, dft = 255
+//Bit 23:16 reg_nr4_sad2alp1_lut13 // unsigned , default = 224 sad to alpha1 for temporal blending, dft = 255
+//Bit 15: 8 reg_nr4_sad2alp1_lut14 // unsigned , default = 255 sad to alpha1 for temporal blending, dft = 255
+//Bit 7: 0 reg_nr4_sad2alp1_lut15 // unsigned , default = 255 sad to alpha1 for temporal blending, dft = 255
+#define NR4_MCNR_SAD2BET0_LUT0 ((0x2de6 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet0_lut0 // unsigned , default = 0 sad to beta0 for tnr and mcnr blending, dft = 0
+//Bit 23:16 reg_nr4_sad2bet0_lut1 // unsigned , default = 2 sad to beta0 for tnr and mcnr blending, dft = 2
+//Bit 15: 8 reg_nr4_sad2bet0_lut2 // unsigned , default = 4 sad to beta0 for tnr and mcnr blending, dft = 4
+//Bit 7: 0 reg_nr4_sad2bet0_lut3 // unsigned , default = 8 sad to beta0 for tnr and mcnr blending, dft = 8
+#define NR4_MCNR_SAD2BET0_LUT1 ((0x2de7 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet0_lut4 // unsigned , default = 16 sad to beta0 for tnr and mcnr blending, dft = 16
+//Bit 23:16 reg_nr4_sad2bet0_lut5 // unsigned , default = 32 sad to beta0 for tnr and mcnr blending, dft = 32
+//Bit 15: 8 reg_nr4_sad2bet0_lut6 // unsigned , default = 48 sad to beta0 for tnr and mcnr blending, dft = 48
+//Bit 7: 0 reg_nr4_sad2bet0_lut7 // unsigned , default = 64 sad to beta0 for tnr and mcnr blending, dft = 64
+#define NR4_MCNR_SAD2BET0_LUT2 ((0x2de8 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet0_lut8 // unsigned , default = 80 sad to beta0 for tnr and mcnr blending, dft = 80
+//Bit 23:16 reg_nr4_sad2bet0_lut9 // unsigned , default = 96 sad to beta0 for tnr and mcnr blending, dft = 96
+//Bit 15: 8 reg_nr4_sad2bet0_lut10 // unsigned , default = 112 sad to beta0 for tnr and mcnr blending, dft = 112
+//Bit 7: 0 reg_nr4_sad2bet0_lut11 // unsigned , default = 128 sad to beta0 for tnr and mcnr blending, dft = 128
+#define NR4_MCNR_SAD2BET0_LUT3 ((0x2de9 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet0_lut12 // unsigned , default = 196 sad to beta0 for tnr and mcnr blending, dft = 160
+//Bit 23:16 reg_nr4_sad2bet0_lut13 // unsigned , default = 224 sad to beta0 for tnr and mcnr blending, dft = 192
+//Bit 15: 8 reg_nr4_sad2bet0_lut14 // unsigned , default = 255 sad to beta0 for tnr and mcnr blending, dft = 224
+//Bit 7: 0 reg_nr4_sad2bet0_lut15 // unsigned , default = 255 sad to beta0 for tnr and mcnr blending, dft = 255
+#define NR4_MCNR_SAD2BET1_LUT0 ((0x2dea << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet1_lut0 // unsigned , default = 0 sad to beta1 for deghost blending, dft = 0
+//Bit 23:16 reg_nr4_sad2bet1_lut1 // unsigned , default = 2 sad to beta1 for deghost blending, dft = 2
+//Bit 15: 8 reg_nr4_sad2bet1_lut2 // unsigned , default = 4 sad to beta1 for deghost blending, dft = 4
+//Bit 7: 0 reg_nr4_sad2bet1_lut3 // unsigned , default = 8 sad to beta1 for deghost blending, dft = 8
+#define NR4_MCNR_SAD2BET1_LUT1 ((0x2deb << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet1_lut4 // unsigned , default = 16 sad to beta1 for deghost blending, dft = 16
+//Bit 23:16 reg_nr4_sad2bet1_lut5 // unsigned , default = 32 sad to beta1 for deghost blending, dft = 32
+//Bit 15: 8 reg_nr4_sad2bet1_lut6 // unsigned , default = 48 sad to beta1 for deghost blending, dft = 48
+//Bit 7: 0 reg_nr4_sad2bet1_lut7 // unsigned , default = 64 sad to beta1 for deghost blending, dft = 64
+#define NR4_MCNR_SAD2BET1_LUT2 ((0x2dec << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet1_lut8 // unsigned , default = 80 sad to beta1 for deghost blending, dft = 80
+//Bit 23:16 reg_nr4_sad2bet1_lut9 // unsigned , default = 96 sad to beta1 for deghost blending, dft = 96
+//Bit 15: 8 reg_nr4_sad2bet1_lut10 // unsigned , default = 112 sad to beta1 for deghost blending, dft = 112
+//Bit 7: 0 reg_nr4_sad2bet1_lut11 // unsigned , default = 128 sad to beta1 for deghost blending, dft = 128
+#define NR4_MCNR_SAD2BET1_LUT3 ((0x2ded << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet1_lut12 // unsigned , default = 160 sad to beta1 for deghost blending, dft = 160
+//Bit 23:16 reg_nr4_sad2bet1_lut13 // unsigned , default = 192 sad to beta1 for deghost blending, dft = 192
+//Bit 15: 8 reg_nr4_sad2bet1_lut14 // unsigned , default = 224 sad to beta1 for deghost blending, dft = 224
+//Bit 7: 0 reg_nr4_sad2bet1_lut15 // unsigned , default = 255 sad to beta1 for deghost blending, dft = 255
+#define NR4_MCNR_SAD2BET2_LUT0 ((0x2dee << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet2_lut0 // unsigned , default = 0 sad to beta2 for snr and mcnr blending, dft = 0
+//Bit 23:16 reg_nr4_sad2bet2_lut1 // unsigned , default = 1 sad to beta2 for snr and mcnr blending, dft = 2
+//Bit 15: 8 reg_nr4_sad2bet2_lut2 // unsigned , default = 2 sad to beta2 for snr and mcnr blending, dft = 4
+//Bit 7: 0 reg_nr4_sad2bet2_lut3 // unsigned , default = 4 sad to beta2 for snr and mcnr blending, dft = 8
+#define NR4_MCNR_SAD2BET2_LUT1 ((0x2def << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet2_lut4 // unsigned , default = 8 sad to beta2 for snr and mcnr blending, dft = 16
+//Bit 23:16 reg_nr4_sad2bet2_lut5 // unsigned , default = 16 sad to beta2 for snr and mcnr blending, dft = 32
+//Bit 15: 8 reg_nr4_sad2bet2_lut6 // unsigned , default = 32 sad to beta2 for snr and mcnr blending, dft = 48
+//Bit 7: 0 reg_nr4_sad2bet2_lut7 // unsigned , default = 48 sad to beta2 for snr and mcnr blending, dft = 64
+#define NR4_MCNR_SAD2BET2_LUT2 ((0x2df0 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet2_lut8 // unsigned , default = 64 sad to beta2 for snr and mcnr blending, dft = 80
+//Bit 23:16 reg_nr4_sad2bet2_lut9 // unsigned , default = 80 sad to beta2 for snr and mcnr blending, dft = 96
+//Bit 15: 8 reg_nr4_sad2bet2_lut10 // unsigned , default = 96 sad to beta2 for snr and mcnr blending, dft = 112
+//Bit 7: 0 reg_nr4_sad2bet2_lut11 // unsigned , default = 112 sad to beta2 for snr and mcnr blending, dft = 128
+#define NR4_MCNR_SAD2BET2_LUT3 ((0x2df1 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet2_lut12 // unsigned , default = 128 sad to beta2 for snr and mcnr blending, dft = 160
+//Bit 23:16 reg_nr4_sad2bet2_lut13 // unsigned , default = 160 sad to beta2 for snr and mcnr blending, dft = 192
+//Bit 15: 8 reg_nr4_sad2bet2_lut14 // unsigned , default = 224 sad to beta2 for snr and mcnr blending, dft = 224
+//Bit 7: 0 reg_nr4_sad2bet2_lut15 // unsigned , default = 255 sad to beta2 for snr and mcnr blending, dft = 255
+#define NR4_MCNR_RO_U_SUM ((0x2df2 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_u_sum // unsigned , default = 0 sum of U of current field/frame
+#define NR4_MCNR_RO_V_SUM ((0x2df3 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_v_sum // unsigned , default = 0 sum of V of current field/frame
+#define NR4_MCNR_RO_GRDU_SUM ((0x2df4 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_grdu_sum // unsigned , default = 0 sum of gradient U of current field/frame
+#define NR4_MCNR_RO_GRDV_SUM ((0x2df5 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_grdv_sum // unsigned , default = 0 sum of gradient V of current field/frame
+#define NR4_TOP_CTRL ((0x2dff << 2) + 0xff000000)
+//Bit 31:20 reg_gclk_ctrl // unsigned , default = 0
+//Bit 19 reserved
+//Bit 18 reg_nr4_mcnr_en // unsigned , default = 1 ncnr enable or bypass, dft = 1
+//Bit 17 reg_nr2_en // unsigned , default = 1 nr2 enable, dft = 1
+//Bit 16 reg_nr4_en // unsigned , default = 1 nr4 enable, dft = 1
+//Bit 15 reg_nr2_proc_en // unsigned , default = 1
+//Bit 14 reg_det3d_en // unsigned , default = 1
+//Bit 13 di_polar_en // unsigned , default = 1 do does not have in C
+//Bit 12 reg_cfr_enable // unsigned , default = 0 0-disable; 1:enable
+//Bit 11: 9 reg_3dnr_enable_l // unsigned , default = 7 b0: Y b1:U b2:V
+//Bit 8: 6 reg_3dnr_enable_r // unsigned , default = 7 b0: Y b1:U b2:V
+//Bit 5 reg_nr4_lnbuf_ctrl // unsigned , default = 1 line buf ctrl for nr4: 0, 3lines, 1, 5lines, dft = 1
+//Bit 4 reg_nr4_snr2_en // unsigned , default = 0 snr2 enable, 0: use old snr, 1: use new snr2, dft = 1
+//Bit 3 reg_nr4_scene_change_en // unsigned , default = 1 enable scene change proc. dft = 1
+//Bit 2 nr2_sw_en // unsigned , default = 1 do does not have in C
+//Bit 1 reserved
+//Bit 0 reg_nr4_scene_change_flg // unsigned , default = 0 flags for scene change, dft = 0
+//========== nr4_mcnr_regs register end ==========//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_nr4_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_dnr_regs.h
+//
+//========================================================================
+// VI_HIST_SPL register (16'h2e00 - 16'h2eff)
+//========================================================================
+//
+// Reading file: vi_hist_spl_reg.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// ----------------------------
+// VI_HIST_SPL 0x2e
+// ----------------------------
+// -----------------------------------------------
+// REG_BASE: VI_HIST_SPL_VCBUS_BASE = 0x2e
+// -----------------------------------------------
+//BIT 14: 34bin only, 0&255 and other 32bins
+//Bit 13:11 hist_din_sel, 00: from vdin0 dout, 1: from vdin1, 2: from nr dout, 3: di output, 4: vpp output, 5: vd1_din, 6: vd2_din, 7:osd1_dout
+//Bit 10:8 hist_din_comp_mux, mux of [29:22], [19:12], [9:2] for hist detect
+//Bit 7:5 hist_dnlp_low the real pixels in each bins got by VI_DNLP_HISTXX should multiple with 2^(dnlp_low+3)
+//Bit 3:2 hist_din_sel the source used for hist statistics. 00: from matrix0 dout, 01: from vsc_dout, 10: from matrix1 dout, 11: form matrix1 din
+//Bit 1 hist_win_en 1'b0: hist used for full picture; 1'b1: hist used for pixels within hist window
+//Bit 0 hist_spl_en 1'b0: disable hist readback; 1'b1: enable hist readback
+#define VI_HIST_CTRL ((0x2e00 << 2) + 0xff000000)
+//Bit 28:16 hist_hstart horizontal start value to define hist window
+//Bit 12:0 hist_hend horizontal end value to define hist window
+#define VI_HIST_H_START_END ((0x2e01 << 2) + 0xff000000)
+//Bit 28:16 hist_vstart vertical start value to define hist window
+//Bit 12:0 hist_vend vertical end value to define hist window
+#define VI_HIST_V_START_END ((0x2e02 << 2) + 0xff000000)
+//Bit 15:8 hist_max maximum value
+//Bit 7:0 hist_min minimum value
+//read only
+#define VI_HIST_MAX_MIN ((0x2e03 << 2) + 0xff000000)
+//Bit 31:0 hist_spl_rd
+//counts for the total luma value
+//read only
+#define VI_HIST_SPL_VAL ((0x2e04 << 2) + 0xff000000)
+//Bit 21:0 hist_spl_pixel_count
+//counts for the total calculated pixels
+//read only
+#define VI_HIST_SPL_PIX_CNT ((0x2e05 << 2) + 0xff000000)
+//Bit 31:0 hist_chroma_sum
+//counts for the total chroma value
+//read only
+#define VI_HIST_CHROMA_SUM ((0x2e06 << 2) + 0xff000000)
+//Bit 31:16 higher hist bin
+//Bit 15:0 lower hist bin
+//0-255 are splited to 64 bins evenly, and VI_DNLP_HISTXX
+//are the statistic number of pixels that within each bin.
+//VI_DNLP_HIST00[15:0] counts for the first bin
+//VI_DNLP_HIST00[31:16] counts for the second bin
+//VI_DNLP_HIST01[15:0] counts for the third bin
+//VI_DNLP_HIST01[31:16] counts for the fourth bin
+//etc...
+//read only
+#define VI_DNLP_HIST00 ((0x2e07 << 2) + 0xff000000)
+#define VI_DNLP_HIST01 ((0x2e08 << 2) + 0xff000000)
+#define VI_DNLP_HIST02 ((0x2e09 << 2) + 0xff000000)
+#define VI_DNLP_HIST03 ((0x2e0a << 2) + 0xff000000)
+#define VI_DNLP_HIST04 ((0x2e0b << 2) + 0xff000000)
+#define VI_DNLP_HIST05 ((0x2e0c << 2) + 0xff000000)
+#define VI_DNLP_HIST06 ((0x2e0d << 2) + 0xff000000)
+#define VI_DNLP_HIST07 ((0x2e0e << 2) + 0xff000000)
+#define VI_DNLP_HIST08 ((0x2e0f << 2) + 0xff000000)
+#define VI_DNLP_HIST09 ((0x2e10 << 2) + 0xff000000)
+#define VI_DNLP_HIST10 ((0x2e11 << 2) + 0xff000000)
+#define VI_DNLP_HIST11 ((0x2e12 << 2) + 0xff000000)
+#define VI_DNLP_HIST12 ((0x2e13 << 2) + 0xff000000)
+#define VI_DNLP_HIST13 ((0x2e14 << 2) + 0xff000000)
+#define VI_DNLP_HIST14 ((0x2e15 << 2) + 0xff000000)
+#define VI_DNLP_HIST15 ((0x2e16 << 2) + 0xff000000)
+#define VI_DNLP_HIST16 ((0x2e17 << 2) + 0xff000000)
+#define VI_DNLP_HIST17 ((0x2e18 << 2) + 0xff000000)
+#define VI_DNLP_HIST18 ((0x2e19 << 2) + 0xff000000)
+#define VI_DNLP_HIST19 ((0x2e1a << 2) + 0xff000000)
+#define VI_DNLP_HIST20 ((0x2e1b << 2) + 0xff000000)
+#define VI_DNLP_HIST21 ((0x2e1c << 2) + 0xff000000)
+#define VI_DNLP_HIST22 ((0x2e1d << 2) + 0xff000000)
+#define VI_DNLP_HIST23 ((0x2e1e << 2) + 0xff000000)
+#define VI_DNLP_HIST24 ((0x2e1f << 2) + 0xff000000)
+#define VI_DNLP_HIST25 ((0x2e20 << 2) + 0xff000000)
+#define VI_DNLP_HIST26 ((0x2e21 << 2) + 0xff000000)
+#define VI_DNLP_HIST27 ((0x2e22 << 2) + 0xff000000)
+#define VI_DNLP_HIST28 ((0x2e23 << 2) + 0xff000000)
+#define VI_DNLP_HIST29 ((0x2e24 << 2) + 0xff000000)
+#define VI_DNLP_HIST30 ((0x2e25 << 2) + 0xff000000)
+#define VI_DNLP_HIST31 ((0x2e26 << 2) + 0xff000000)
+#define VI_DNLP_HIST32 ((0x2e27 << 2) + 0xff000000)
+//Bit 28:16 hist_pic_height active input data window height
+//Bit 12:0 hist_pic_width active input data window width
+#define VI_HIST_PIC_SIZE ((0x2e28 << 2) + 0xff000000)
+//Bit 15:8 hist_pix_white_value: >= this value will be white pixel
+//Bit 7:0 hist_pix_black_value: <= this value will be black pixel
+#define VI_HIST_BLACK_WHITE_VALUE ((0x2e29 << 2) + 0xff000000)
+#define VI_HIST_GCLK_CTRL ((0x2e2a << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vi_hist_spl_reg.h
+//
+//
+// Reading file: mcdi_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: MCDI_VCBUS_BASE = 0x2f
+// -----------------------------------------------
+////=================================================================////
+//// memc di core 0
+////=================================================================////
+#define MCDI_HV_SIZEIN ((0x2f00 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_mcdi_hsize image horizontal size (number of cols) default=1024
+//Bit 15:13, reserved
+//Bit 12: 0, reg_mcdi_vsize image vertical size (number of rows) default=1024
+#define MCDI_HV_BLKSIZEIN ((0x2f01 << 2) + 0xff000000)
+//Bit 31, reg_mcdi_vrev default = 0
+//Bit 30, reg_mcdi_hrev default = 0
+//Bit 29:28, reserved
+//Bit 27:16, reg_mcdi_blkhsize image horizontal blk size (number of cols) default=1024
+//Bit 15:13, reserved
+//Bit 11: 0, reg_mcdi_blkvsize image vertical blk size (number of rows) default=1024
+#define MCDI_BLKTOTAL ((0x2f02 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23: 0, reg_mcdi_blktotal
+#define MCDI_MOTINEN ((0x2f03 << 2) + 0xff000000)
+//Bit 31: 2, reserved
+//Bit 1, reg_mcdi_motionrefen. enable motion refinement of MA, default = 1
+//Bit 0, reg_mcdi_motionparadoxen. enable motion paradox detection, default = 1
+#define MCDI_CTRL_MODE ((0x2f04 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:26, reg_mcdi_lmvlocken 0:disable, 1: use max Lmv, 2: use no-zero Lmv, lmv lock enable mode, default = 2
+//Bit 25, reg_mcdi_reldetrptchken
+// 0: unable; 1: enable, enable repeat pattern check (not repeat mv detection) in rel det part, default = 1
+//Bit 24, reg_mcdi_reldetgmvpd22chken
+// 0: unable; 1: enable, enable pull-down 22 mode check in gmv lock mode for rel det, default = 1
+//Bit 23, reg_mcdi_pd22chken
+// 0: unable; 1: enable, enable pull-down 22 mode check (lock) function, default = 1
+//Bit 22, reg_mcdi_reldetlpfen
+// 0: unable; 1: enable, enable det value lpf, default = 1
+//Bit 21, reg_mcdi_reldetlmvpd22chken
+// 0: unable; 1: enable, enable pull-down 22 mode check in lmv lock mode for rel det, default = 1
+//Bit 20, reg_mcdi_reldetlmvdifchken
+// 0: unable; 1: enable, enable lmv dif check in lmv lock mode for rel det, default = 1
+//Bit 19, reg_mcdi_reldetgmvdifchken
+// 0: unable; 1: enable, enable lmv dif check in lmv lock mode for rel det, default = 1
+//Bit 18, reg_mcdi_reldetpd22chken
+// 0: unable; 1: enable, enable pull-down 22 mode check for rel det refinement, default = 1
+//Bit 17, reg_mcdi_reldetfrqchken
+// 0: unable; 1: enable, enable mv frequency check in rel det, default = 1
+//Bit 16, reg_mcdi_qmeen
+// 0: unable; 1: enable, enable quarter motion estimation, defautl = 1
+//Bit 15, reg_mcdi_refrptmven
+// 0: unable; 1: enable, use repeat mv in refinement, default = 1
+//Bit 14, reg_mcdi_refgmven
+// 0: unable; 1: enable, use gmv in refinement, default = 1
+//Bit 13, reg_mcdi_reflmven
+// 0: unable; 1: enable, use lmvs in refinement, default = 1
+//Bit 12, reg_mcdi_refnmven
+// 0: unable; 1: enable, use neighoring mvs in refinement, default = 1
+//Bit 11, reserved
+//Bit 10, reg_mcdi_referrfrqchken
+// 0: unable; 1: enable, enable mv frquency check while finding min err in ref, default = 1
+//Bit 9, reg_mcdi_refen
+// 0: unable; 1: enable, enable mv refinement, default = 1
+//Bit 8, reg_mcdi_horlineen
+// 0: unable; 1: enable,enable horizontal lines detection by sad map, default = 1
+//Bit 7, reg_mcdi_highvertfrqdeten
+// 0: unable; 1: enable, enable high vertical frequency pattern detection, default = 1
+//Bit 6, reg_mcdi_gmvlocken
+// 0: unable; 1: enable, enable gmv lock mode, default = 1
+//Bit 5, reg_mcdi_rptmven
+// 0: unable; 1: enable, enable repeat pattern detection, default = 1
+//Bit 4, reg_mcdi_gmven
+// 0: unable; 1: enable, enable global motion estimation, default = 1
+//Bit 3, reg_mcdi_lmven
+// 0: unable; 1: enable, enable line mv estimation for hme, default = 1
+//Bit 2, reg_mcdi_chkedgeen
+// 0: unable; 1: enable, enable check edge function, default = 1
+//Bit 1, reg_mcdi_txtdeten
+// 0: unable; 1: enable, enable texture detection, default = 1
+//Bit 0, reg_mcdi_memcen
+// 0: unable; 1: enable, enable of memc di, default = 1
+#define MCDI_UNI_MVDST ((0x2f05 << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:17, reg_mcdi_unimvdstabsseg0 segment0 for uni-mv abs, default = 1
+//Bit 16:12, reg_mcdi_unimvdstabsseg1 segment1 for uni-mv abs, default = 15
+//Bit 11: 8, reg_mcdi_unimvdstabsdifgain0 2/2, gain0 of uni-mv abs dif for segment0, normalized 2 to '1', default = 2
+//Bit 7: 5, reg_mcdi_unimvdstabsdifgain1 2/2, gain1 of uni-mv abs dif for segment1, normalized 2 to '1', default = 2
+//Bit 4: 2, reg_mcdi_unimvdstabsdifgain2 2/2, gain2 of uni-mv abs dif beyond segment1, normalized 2 to '1', default = 2
+//Bit 1: 0, reg_mcdi_unimvdstsgnshft shift for neighboring distance of uni-mv, default = 0
+#define MCDI_BI_MVDST ((0x2f06 << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:17, reg_mcdi_bimvdstabsseg0 segment0 for bi-mv abs, default = 1
+//Bit 16:12, reg_mcdi_bimvdstabsseg1 segment1 for bi-mv abs, default = 9
+//Bit 11: 8, reg_mcdi_bimvdstabsdifgain0 6/2, gain0 of bi-mv abs dif for segment0, normalized 2 to '1', default = 6
+//Bit 7: 5, reg_mcdi_bimvdstabsdifgain1 3/2, gain1 of bi-mvabs dif for segment1, normalized 2 to '1', default = 3
+//Bit 4: 2, reg_mcdi_bimvdstabsdifgain2 2/2, gain2 of bi-mvabs dif beyond segment1, normalized 2 to '1', default = 2
+//Bit 1: 0, reg_mcdi_bimvdstsgnshft shift for neighboring distance of bi-mv, default = 0
+#define MCDI_SAD_GAIN ((0x2f07 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18:17, reg_mcdi_unisadcorepxlgain uni-sad core pixels gain, default = 3
+//Bit 16, reg_mcdi_unisadcorepxlnormen enable uni-sad core pixels normalization, default = 0
+//Bit 15:11, reserved
+//Bit 10: 9, reg_mcdi_bisadcorepxlgain bi-sad core pixels gain, default = 3
+//Bit 8, reg_mcdi_bisadcorepxlnormen enable bi-sad core pixels normalization, default = 1
+//Bit 7: 3, reserved
+//Bit 2: 1, reg_mcdi_biqsadcorepxlgain bi-qsad core pixels gain, default = 3
+//Bit 0, reg_mcdi_biqsadcorepxlnormen enable bi-qsad core pixels normalization, default = 1
+#define MCDI_TXT_THD ((0x2f08 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_mcdi_txtminmaxdifthd, min max dif threshold (>=) for texture detection, default = 24
+//Bit 15: 8, reg_mcdi_txtmeandifthd, mean dif threshold (<) for texture detection, default = 9
+//Bit 7: 3, reserved
+//Bit 2: 0, reg_mcdi_txtdetthd, texture detecting threshold, 0~4, default = 2
+#define MCDI_FLT_MODESEL ((0x2f09 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28, reg_mcdi_flthorlineselmode mode for horizontal line detecting flat calculation, default = 1, same as below
+//Bit 27 reserved
+//Bit 26:24, reg_mcdi_fltgmvselmode mode for gmv flat calculation, default = 4, same as below
+//Bit 23, reserved
+//Bit 22:20, reg_mcdi_fltsadselmode mode for sad flat calculation, default = 2, same as below
+//Bit 19, reserved
+//Bit 18:16, reg_mcdi_fltbadwselmode mode for badw flat calculation, default = 3, same as below
+//Bit 15, reserved
+//Bit 14:12, reg_mcdi_fltrptmvselmode mode for repeat mv flat calculation, default = 4, same as below
+//Bit 11, reserved
+//Bit 10: 8, reg_mcdi_fltbadrelselmode mode for bad rel flat calculation, default = 4, same as below
+//Bit 7, reserved
+//Bit 6: 4, reg_mcdi_fltcolcfdselmode mode for col cfd flat calculation, default = 2, same as below
+//Bit 3, reserved
+//Bit 2: 0, reg_mcdi_fltpd22chkselmode mode for pd22 check flat calculation, default = 2, # 0:cur dif h, 1: cur dif v, 2: pre dif h, 3: pre dif v, 4: cur flt, 5: pre flt, 6: cur+pre, 7: max all(cur,pre)
+#define MCDI_CHK_EDGE_THD ((0x2f0a << 2) + 0xff000000)
+//Bit 23:28, reserved.
+//Bit 27:24, reg_mcdi_chkedgedifsadthd. thd (<=) for sad dif check, 0~8, default = 1
+//Bit 23:16, reserved.
+//Bit 15:12, reg_mcdi_chkedgemaxedgethd. max drt of edge, default = 15
+//Bit 11: 8, reg_mcdi_chkedgeminedgethd. min drt of edge, default = 2
+//Bit 7, reserved.
+//Bit 6: 0, reg_mcdi_chkedgevdifthd. thd for vertical dif in check edge, default = 14
+#define MCDI_CHK_EDGE_GAIN_OFFST ((0x2f0b << 2) + 0xff000000)
+//Bit 31:24, reserved.
+//Bit 23:20, reg_mcdi_chkedgedifthd1. thd1 for edge dif check (<=), default = 4
+//Bit 19:16, reg_mcdi_chkedgedifthd0. thd0 for edge dif check (>=), default = 15
+//Bit :15, reserved.
+//Bit 14:10, reg_mcdi_chkedgechklen. total check length for edge check, 1~24 (>0), default = 24
+//Bit 9: 8, reg_mcdi_chkedgeedgesel. final edge select mode, 0: original start edge, 1: lpf start edge, 2: orignal start+end edge, 3: lpf start+end edge, default = 1
+//Bit 7: 3, reg_mcdi_chkedgesaddstgain. distance gain for sad calc while getting edges, default = 4
+//Bit 2, reg_mcdi_chkedgechkmode. edge used in check mode, 0: original edge, 1: lpf edge, defautl = 1
+//Bit 1, reg_mcdi_chkedgestartedge. edge mode for start edge, 0: original edge, 1: lpf edge, defautl = 0
+//Bit 0, reg_mcdi_chkedgeedgelpf. edge lpf mode, 0:[0,2,4,2,0], 1:[1,2,2,2,1], default = 0
+#define MCDI_LMV_RT ((0x2f0c << 2) + 0xff000000)
+//BIt 31:15, reserved
+//Bit 14:12, reg_mcdi_lmvvalidmode valid mode for lmv calc., 100b: use char det, 010b: use flt, 001b: use hori flg
+//Bit 11:10, reg_mcdi_lmvgainmvmode four modes of mv selection for lmv weight calucluation, default = 1
+// 0: cur(x-3), lst(x-1,x,x+1); 1: cur(x-4,x-3), lst(x,x+1); 2: cur(x-5,x-4,x-3), lst(x-1,x,x+1,x+2,x+3); 3: cur(x-6,x-5,x-4,x-3), lst(x-1,x,x+1,x+2);
+//Bit 9, reg_mcdi_lmvinitmode initial lmvs at first row of input field, 0: intial value = 0; 1: inital = 32 (invalid), default = 0
+//Bit 8, reserved
+//Bit 7: 4, reg_mcdi_lmvrt0 ratio of max mv, default = 5
+//Bit 3: 0, reg_mcdi_lmvrt1 ratio of second max mv, default = 5
+#define MCDI_LMV_GAINTHD ((0x2f0d << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_lmvvxmaxgain max gain of lmv weight, default = 96
+//Bit 23, reserved
+//Bit 22:20, reg_mcdi_lmvdifthd0 dif threshold 0 (<) for small lmv, default = 1
+//Bit 19:17, reg_mcdi_lmvdifthd1 dif threshold 1 (<) for median lmv, default = 2
+//Bit 16:14, reg_mcdi_lmvdifthd2 dif threshold 2 (<) for large lmv, default = 3
+//Bit 13: 8, reg_mcdi_lmvnumlmt least/limit number of (total number - max0), default = 20
+//Bit 7: 0, reg_mcdi_lmvfltthd flt cnt thd (<) for lmv, default = 9
+#define MCDI_RPTMV_THD0 ((0x2f0e << 2) + 0xff000000)
+//Bit 31:25, reg_mcdi_rptmvslpthd2 slope thd (>=) between i and i+3/i-3 (i+4/i-4), default = 64
+//Bit 24:20, reg_mcdi_rptmvslpthd1 slope thd (>=) between i and i+2/i-2, default = 4
+//Bit 19:10, reg_mcdi_rptmvampthd2 amplitude thd (>=) between max and min, when count cycles, default = 300
+//Bit 9: 0, reg_mcdi_rptmvampthd1 amplitude thd (>=) between average of max and min, default = 400
+#define MCDI_RPTMV_THD1 ((0x2f0f << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:25, reg_mcdi_rptmvcyccntthd thd (>=) of total cycles count, default = 2
+//Bit 24:21, reg_mcdi_rptmvcycdifthd dif thd (<) of cycles length, default = 3
+//Bit 20:18, reg_mcdi_rptmvcycvldthd thd (>) of valid cycles number, default = 1
+//Bit 17:15, reg_mcdi_rptmvhalfcycminthd min length thd (>=) of half cycle, default = 2
+//Bit 14:11, reg_mcdi_rptmvhalfcycdifthd neighboring half cycle length dif thd (<), default = 5
+//Bit 10: 8, reg_mcdi_rptmvminmaxcntthd least number of valid max and min, default = 2
+//Bit 7: 5, reg_mcdi_rptmvcycminthd min length thd (>=) of cycles, default = 2
+//Bit 4: 0, reg_mcdi_rptmvcycmaxthd max length thd (<) of cycles, default = 17
+#define MCDI_RPTMV_THD2 ((0x2f10 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_mcdi_rptmvhdifthd0 higher hdif thd (>=) (vertical edge) for rpt detection, default = 8
+//Bit 15: 8, reg_mcdi_rptmvhdifthd1 hdif thd (>=) (slope edge) for rpt detection, default = 4
+//Bit 7: 0, reg_mcdi_rptmvvdifthd vdif thd (>=) (slope edge) for rpt detection, default = 1
+#define MCDI_RPTMV_SAD ((0x2f11 << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, reg_mcdi_rptmvsaddifthdgain 7x3x(16/16), gain for sad dif thd in rpt mv detection, 0~672, normalized 16 as '1', default = 336
+//Bit 15:10, reserved
+//Bit 9: 0, reg_mcdi_rptmvsaddifthdoffst offset for sad dif thd in rpt mv detection, -512~511, default = 16
+#define MCDI_RPTMV_FLG ((0x2f12 << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:16, reg_mcdi_rptmvmode select mode of mvs for repeat motion estimation, 0: hmv, 1: qmv/2, 2 or 3: qmv/4, default = 2
+//Bit 15: 8, reg_mcdi_rptmvflgcntthd thd (>=) of min count number for rptmv of whole field, for rptmv estimation, default = 64
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_rptmvflgcntrt 4/32, ratio for repeat mv flag count, normalized 32 as '1', set 31 to 32,
+#define MCDI_RPTMV_GAIN ((0x2f13 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_rptmvlftgain up repeat mv gain for hme, default = 96
+//Bit 23:16, reg_mcdi_rptmvuplftgain up left repeat mv gain for hme, default = 32
+//Bit 15: 8, reg_mcdi_rptmvupgain up repeat mv gain for hme, default = 64
+//Bit 7: 0, reg_mcdi_rptmvuprightgain up right repeat mv gain for hme, default = 32
+#define MCDI_GMV_RT ((0x2f14 << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30:24, reg_mcdi_gmvmtnrt0 ratio 0 for motion senario, set 127 to 128, normalized 128 as '1', default =32
+//Bit 23, reserved
+//Bit 22:16, reg_mcdi_gmvmtnrt1 ratio 1 for motion senario, set 127 to 128, normalized 128 as '1', default = 56
+//Bit 15, reserved
+//Bit 14: 8, reg_mcdi_gmvstlrt0 ratio 0 for still senario, set 127 to 128, normalized 128 as '1', default = 56
+//Bit 7, reserved
+//Bit 6: 0, reg_mcdi_gmvstlrt1 ratio 1 for still senario, set 127 to 128, normalized 128 as '1', default = 80
+#define MCDI_GMV_GAIN ((0x2f15 << 2) + 0xff000000)
+//Bit 31:25, reg_mcdi_gmvzeromvlockrt0 ratio 0 for locking zero mv, set 127 to 128, normalized 128 as '1', default = 100
+//Bit 24:18, reg_mcdi_gmvzeromvlockrt1 ratio 1 for locking zero mv, set 127 to 128, normalized 128 as '1', default = 112
+//Bit 17:16, reg_mcdi_gmvvalidmode valid mode for gmv calc., 10b: use flt, 01b: use hori flg, default = 3
+//Bit 15: 8, reg_mcdi_gmvvxgain gmv's vx gain when gmv locked for hme, default = 0
+//Bit 7: 0, reg_mcdi_gmvfltthd flat thd (<) for gmv calc. default = 3
+#define MCDI_HOR_SADOFST ((0x2f16 << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24:16, reg_mcdi_horsaddifthdgain 21*1/8, gain/divisor for sad dif threshold in hor line detection, normalized 8 as '1', default = 21
+//Bit 15: 8, reg_mcdi_horsaddifthdoffst offset for sad dif threshold in hor line detection, -128~127, default = 0
+//Bit 7: 0, reg_mcdi_horvdifthd threshold (>=) of vertical dif of next block for horizontal line detection, default = 24
+#define MCDI_REF_MV_NUM ((0x2f17 << 2) + 0xff000000)
+//Bit 31: 2, reserved
+//Bit 1: 0, reg_mcdi_refmcmode. motion compensated mode used in refinement, 0: pre, 1: next, 2: (pre+next)/2, default = 0
+#define MCDI_REF_BADW_THD_GAIN ((0x2f18 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:24, reg_mcdi_refbadwcnt2gain. gain for badwv count num==3, default = 6
+//Bit 23:20, reg_mcdi_refbadwcnt1gain. gain for badwv count num==2, default = 3
+//Bit 19:16, reg_mcdi_refbadwcnt0gain. gain for badwv count num==1, default = 1
+//Bit 15:12, reg_mcdi_refbadwthd3. threshold 3 for detect badweave with largest average luma, default = 4
+//Bit 11: 8, reg_mcdi_refbadwthd2. threshold 2 for detect badweave with third smallest average luma, default = 3
+//Bit 7: 4, reg_mcdi_refbadwthd1. threshold 1 for detect badweave with second smallest average luma, default = 2
+//Bit 3: 0, reg_mcdi_refbadwthd0. threshold 0 for detect badweave with smallest average luma, default = 1
+#define MCDI_REF_BADW_SUM_GAIN ((0x2f19 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12: 8, reg_mcdi_refbadwsumgain0. sum gain for r channel, 0~16, default = 8
+//Bit 7: 5, reserved
+//Bit 4, reg_mcdi_refbadwcalcmode. mode for badw calculation, 0:sum, 1:max, default = 0
+//Bit 3: 0, reserved
+#define MCDI_REF_BS_THD_GAIN ((0x2f1a << 2) + 0xff000000)
+//Bit 31:28, reg_mcdi_refbsudgain1. up & down block stregth gain1, normalized to 8 as '1', default = 2
+//Bit 27:24, reg_mcdi_refbsudgain0. up & down block stregth gain0, normalized to 8 as '1', default = 4
+//Bit 23:19, reserved
+//Bit 18:16, reg_mcdi_refbslftgain. left block strength gain, default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_refbsthd1. threshold 1 for detect block stregth in refinment, default = 16
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_refbsthd0. threshold 0 for detect block stregth in refinment, default = 8
+#define MCDI_REF_ERR_GAIN0 ((0x2f1b << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30:24, reg_mcdi_referrnbrdstgain. neighoring mv distances gain for err calc. in ref, normalized to 8 as '1', default = 48
+//Bit 23:20, reserved
+//Bit 19:16, reg_mcdi_referrbsgain. bs gain for err calc. in ref, normalized to 8 as '1', default = 4
+//Bit 15, reserved
+//Bit 14: 8, reg_mcdi_referrbadwgain. badw gain for err calc. in ref, normalized to 8 as '1', default = 64
+//Bit 7: 4, reserved
+//Bit 3: 0, reg_mcdi_referrsadgain. sad gain for err calc. in ref, normalized to 8 as '1', default = 4
+#define MCDI_REF_ERR_GAIN1 ((0x2f1c << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:16, reg_mcdi_referrchkedgegain. check edge gain for err calc. in ref, normalized to 8 as '1', default = 4
+//Bit 15:12, reserved
+//Bit 11: 8, reg_mcdi_referrlmvgain. (locked) lmv gain for err calc. in ref, normalized to 8 as '1', default = 0
+//Bit 7: 4, reserved
+//Bit 3: 0, reg_mcdi_referrgmvgain. (locked) gmv gain for err calc. in ref, normalized to 8 as '1', default = 0
+#define MCDI_REF_ERR_FRQ_CHK ((0x2f1d << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:24, reg_mcdi_referrfrqgain. gain for mv frquency, normalized to 4 as '1', default = 10
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_referrfrqmax. max gain for mv frquency check, default = 31
+//Bit 15, reserved
+//Bit 14:12, reg_mcdi_ref_errfrqmvdifthd2. mv dif threshold 2 (<) for mv frquency check, default = 3
+//Bit 11, reserved
+//Bit 10: 8, reg_mcdi_ref_errfrqmvdifthd1. mv dif threshold 1 (<) for mv frquency check, default = 2
+//Bit 7, reserved
+//Bit 6: 4, reg_mcdi_ref_errfrqmvdifthd0. mv dif threshold 0 (<) for mv frquency check, default = 1
+//Bit 3: 0, reserved
+#define MCDI_QME_LPF_MSK ((0x2f1e << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:24, reg_mcdi_qmechkedgelpfmsk0. lpf mask0 for chk edge in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7
+//Bit 23:20, reserved
+//Bit 19:16, reg_mcdi_qmebslpfmsk0. lpf mask0 for bs in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7
+//Bit 15:12, reserved
+//Bit 11: 8, reg_mcdi_qmebadwlpfmsk0. lpf mask0 for badw in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7
+//Bit 7: 4, reserved
+//Bit 3: 0, reg_mcdi_qmesadlpfmsk0. lpf mask0 for sad in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7
+#define MCDI_REL_DIF_THD_02 ((0x2f1f << 2) + 0xff000000)
+//Bit 31:24, reserved.
+//Bit 23:16, reg_mcdi_reldifthd2. thd (<) for (hdif+vdif), default = 9
+//Bit 15: 8, reg_mcdi_reldifthd1. thd (<) for (vdif), default = 5
+//Bit 7: 0, reg_mcdi_reldifthd0. thd (>=) for (hdif-vdif), default = 48
+#define MCDI_REL_DIF_THD_34 ((0x2f20 << 2) + 0xff000000)
+//Bit 31:16, reserved.
+//Bit 15: 8, reg_mcdi_reldifthd4. thd (<) for (hdif), default = 255
+//Bit 7: 0, reg_mcdi_reldifthd3. thd (>=) for (vdif-hdif), default = 48
+#define MCDI_REL_BADW_GAIN_OFFST_01 ((0x2f21 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_relbadwoffst1. offset for badw adj, for flat block, -128~127, default = 0
+//Bit 23:16, reg_mcdi_relbadwgain1. gain for badw adj, for flat block, default = 128
+//Bit 15: 8, reg_mcdi_relbadwoffst0. offset for badw adj, for vertical block, -128~127, default = 0
+//Bit 7: 0, reg_mcdi_relbadwgain0. gain for badw adj, for vertical block, default = 160
+#define MCDI_REL_BADW_GAIN_OFFST_23 ((0x2f22 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_relbadwoffst3. offset for badw adj, for other block, -128~127, default = 0
+//Bit 23:16, reg_mcdi_relbadwgain3. gain for badw adj, for other block, default = 48
+//Bit 15: 8, reg_mcdi_relbadwoffst2. offset for badw adj, for horizontal block, -128~127, default = 0
+//Bit 7: 0, reg_mcdi_relbadwgain2. gain for badw adj, for horizontal block, default = 48
+#define MCDI_REL_BADW_THD_GAIN_OFFST ((0x2f23 << 2) + 0xff000000)
+//Bit 31:23, reserved.
+//Bit 22:16, reg_mcdi_relbadwoffst. offset for badw thd adj, -64~63, default = 0
+//Bit 15: 8, reserved.
+//Bit 7: 0, reg_mcdi_relbadwthdgain. gain0 for badw thd adj, normalized to 16 as '1', default = 16
+#define MCDI_REL_BADW_THD_MIN_MAX ((0x2f24 << 2) + 0xff000000)
+//Bit 31:18, reserved.
+//Bit 17: 8, reg_mcdi_relbadwthdmax. max for badw thd adj, default = 256
+//Bit 7: 0, reg_mcdi_relbadwthdmin. min for badw thd adj, default = 16
+#define MCDI_REL_SAD_GAIN_OFFST_01 ((0x2f25 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_relsadoffst1. offset for sad adj, for flat block, -128~127, default = 0
+//Bit 23:20, reserved.
+//Bit 19:16, reg_mcdi_relsadgain1. gain for sad adj, for flat block, normalized to 8 as '1', default = 8
+//Bit 15: 8, reg_mcdi_relsadoffst0. offset for sad adj, for vertical block, -128~127, default = 0
+//Bit 7: 4, reserved.
+//Bit 3: 0, reg_mcdi_relsadgain0. gain for sad adj, for vertical block, normalized to 8 as '1', default = 6
+#define MCDI_REL_SAD_GAIN_OFFST_23 ((0x2f26 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_relsadoffst3. offset for sad adj, for other block, -128~127, default = 0
+//Bit 23:20, reserved.
+//Bit 19:16, reg_mcdi_relsadgain3. gain for sad adj, for other block, normalized to 8 as '1', default = 8
+//Bit 15: 8, reg_mcdi_relsadoffst2. offset for sad adj, for horizontal block, -128~127, default = 0
+//Bit 7: 4, reserved.
+//Bit 3: 0, reg_mcdi_relsadgain2. gain for sad adj, for horizontal block, normalized to 8 as '1', default = 12
+#define MCDI_REL_SAD_THD_GAIN_OFFST ((0x2f27 << 2) + 0xff000000)
+//Bit 31:24, reserved.
+//Bit 23:16, reg_mcdi_relsadoffst. offset for sad thd adj, -128~127, default = 0
+//Bit 15:10, reserved.
+//Bit 9: 0, reg_mcdi_relsadthdgain. gain for sad thd adj, 21*2/16, normalized to 16 as '1', default = 42
+#define MCDI_REL_SAD_THD_MIN_MAX ((0x2f28 << 2) + 0xff000000)
+//Bit 31:27, reserved.
+//Bit 26:16, reg_mcdi_relsadthdmax. max for sad thd adj, 21*32, default = 672
+//Bit 15: 9, reserved.
+//Bit 8: 0, reg_mcdi_relsadthdmin. min for sad thd adj, 21*2, default = 42
+#define MCDI_REL_DET_GAIN_00 ((0x2f29 << 2) + 0xff000000)
+//Bit 31:21, reserved.
+//Bit 20:16, reg_mcdi_reldetbsgain0. gain0 (gmv locked) for bs, for det. calc. normalized to 16 as '1', default = 8
+//Bit 15:14, reserved.
+//Bit 13: 8, reg_mcdi_reldetbadwgain0. gain0 (gmv locked) for badw, for det. calc. normalized to 16 as '1', default = 12
+//Bit 7: 5, reserved.
+//Bit 4: 0, reg_mcdi_reldetsadgain0. gain0 (gmv locked) for qsad, for det. calc. normalized to 16 as '1', default = 8
+#define MCDI_REL_DET_GAIN_01 ((0x2f2a << 2) + 0xff000000)
+//Bit 31:14, reserved.
+//Bit 12: 8, reg_mcdi_reldetchkedgegain0. gain0 (gmv locked) for chk_edge, for det. calc. normalized to 16 as '1', default = 2
+//Bit 7, reserved.
+//Bit 6: 0, reg_mcdi_reldetnbrdstgain0. gain0 (gmv locked) for neighoring dist, for det. calc. normalized to 16 as '1', default = 24
+#define MCDI_REL_DET_GAIN_10 ((0x2f2b << 2) + 0xff000000)
+//Bit 31:21, reserved.
+//Bit 20:16, reg_mcdi_reldetbsgain1. gain1 (lmv locked) for bs, for det. calc. normalized to 16 as '1', default = 0
+//Bit 15:14, reserved.
+//Bit 13: 8, reg_mcdi_reldetbadwgain1. gain1 (lmv locked) for badw, for det. calc. normalized to 16 as '1', default = 8
+//Bit 7: 5, reserved.
+//Bit 4: 0, reg_mcdi_reldetsadgain1. gain1 (lmv locked) for qsad, for det. calc. normalized to 16 as '1', default = 8
+#define MCDI_REL_DET_GAIN_11 ((0x2f2c << 2) + 0xff000000)
+//Bit 31:14, reserved.
+//Bit 12: 8, reg_mcdi_reldetchkedgegain1. gain1 (lmv locked) for chk_edge, for det. calc. normalized to 16 as '1', default = 0
+//Bit 7, reserved.
+//Bit 6: 0, reg_mcdi_reldetnbrdstgain1. gain1 (lmv locked) for neighoring dist, for det. calc. normalized to 16 as '1', default = 24
+#define MCDI_REL_DET_GAIN_20 ((0x2f2d << 2) + 0xff000000)
+//Bit 31:21, reserved.
+//Bit 20:16, reg_mcdi_reldetbsgain2. gain2 (no locked) for bs, for det. calc. normalized to 16 as '1', default = 12
+//Bit 15:14, reserved.
+//Bit 13: 8, reg_mcdi_reldetbadwgain2. gain2 (no locked) for badw, for det. calc. normalized to 16 as '1', default = 32
+//Bit 7: 5, reserved.
+//Bit 4: 0, reg_mcdi_reldetsadgain2. gain2 (no locked) for qsad, for det. calc. normalized to 16 as '1', default = 16
+#define MCDI_REL_DET_GAIN_21 ((0x2f2e << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, reg_mcdi_reldetoffst. offset for rel calculation, for det. calc. -512~511, default = 0
+//Bit 15:14, reserved.
+//Bit 12: 8, reg_mcdi_reldetchkedgegain2. gain2 (no locked) for chk_edge, for det. calc. normalized to 16 as '1', default = 10
+//Bit 7, reserved.
+//Bit 6: 0, reg_mcdi_reldetnbrdstgain2. gain2 (no locked) for neighoring dist, for det. calc. normalized to 16 as '1', default = 32
+#define MCDI_REL_DET_GMV_DIF_CHK ((0x2f2f << 2) + 0xff000000)
+//Bit 31:24, reserved.
+//Bit 23:16, reg_mcdi_reldetgmvfltthd. flat thd (>=) for gmv lock decision, default = 0
+//Bit 15, reserved.
+//Bit 14:12, reg_mcdi_reldetgmvdifthd. dif thd (>=) for current mv different from gmv for gmv dif check, actually used in Lmv lock check, default = 3
+//Bit 11, reserved.
+//Bit 10: 8, reg_mcdi_reldetgmvdifmin. min mv dif for gmv dif check, default = 1, note: dif between reg_mcdi_rel_det_gmv_dif_max and reg_mcdi_rel_det_gmv_dif_min should be; 0,1,3,7, not work for others
+//Bit 7: 4, reg_mcdi_reldetgmvdifmax. max mv dif for gmv dif check, default = 4
+//Bit 3: 1, reserved
+//Bit 0, reg_mcdi_reldetgmvdifmvmode. mv mode used for gmv dif check, 0: use refmv, 1: use qmv, default = 0
+#define MCDI_REL_DET_LMV_DIF_CHK ((0x2f30 << 2) + 0xff000000)
+//Bit 31:24, reserved.
+//Bit 23:16, reg_mcdi_reldetlmvfltthd. flat thd (>=) for lmv lock decision, default = 12
+//Bit 15:14, reserved.
+//Bit 13:12, reg_mcdi_reldetlmvlockchkmode. lmv lock check mode, 0:cur Lmv, 1: cur & (last | next), 2: last & cur & next Lmv, default = 1
+//Bit 11, reserved.
+//Bit 10: 8, reg_mcdi_reldetlmvdifmin. min mv dif for lmv dif check, default = 1, note: dif between reg_mcdi_rel_det_lmv_dif_max and reg_mcdi_rel_det_lmv_dif_min should be; 0,1,3,7, not work for others
+//Bit 7: 4, reg_mcdi_reldetlmvdifmax. max mv dif for lmv dif check, default = 4
+//Bit 3: 1, reserved
+//Bit 0, reg_mcdi_reldetlmvdifmvmode. mv mode used for lmv dif check, 0: use refmv, 1: use qmv, default = 0
+#define MCDI_REL_DET_FRQ_CHK ((0x2f31 << 2) + 0xff000000)
+//Bit 31:12, reserved.
+//Bit 11: 8, reg_mcdi_reldetfrqgain. gain for frequency check, normalized to 4 as '1', default = 10
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetfrqmax. max value for frequency check, default = 31
+#define MCDI_REL_DET_PD22_CHK ((0x2f32 << 2) + 0xff000000)
+//Bit 31:18, reserved.
+//Bit 17: 8, reg_mcdi_reldetpd22chkoffst. offset for pd22 check happened, default = 512
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetpd22chkgain. gain for pd22 check happened, normalized to 8 as '1', default = 12
+#define MCDI_REL_DET_RPT_CHK_ROW ((0x2f33 << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:16, reg_mcdi_reldetrptchkendrow. end row (<) number for repeat check, default = 2047
+//Bit 15:11, reserved
+//Bit 10: 0, reg_mcdi_reldetrptchkstartrow. start row (>=) number for repeat check, default = 0
+#define MCDI_REL_DET_RPT_CHK_GAIN_QMV ((0x2f34 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_mcdi_reldetrptchkqmvmax. max thd (<) of abs qmv for repeat check, default = 15, note that quarter mv's range is -63~63
+//Bit 23:22, reserved
+//Bit 21:16, reg_mcdi_reldetrptchkqmvmin. min thd (>=) of abs qmv for repeat check, default = 10, note that quarter mv's range is -63~63
+//Bit 15, reserved/
+//Bit 14: 4, reg_mcdi_reldetrptchkoffst. offset for repeat check, default = 512
+//Bit 3: 0, reg_mcdi_reldetrptchkgain. gain for repeat check, normalized to 8 as '1', default = 4
+#define MCDI_REL_DET_RPT_CHK_THD_0 ((0x2f35 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_mcdi_reldetrptchkzerosadthd. zero sad thd (<) for repeat check, default = 255
+//Bit 15:14, reserved.
+//Bit 13: 8, reg_mcdi_reldetrptchkzerobadwthd. zero badw thd (>=) for repeat check, default = 16
+//Bit 7: 4, reserved
+//Bit 3: 0, reg_mcdi_reldetrptchkfrqdifthd. frequency dif thd (<) for repeat check, 0~10, default = 5
+#define MCDI_REL_DET_RPT_CHK_THD_1 ((0x2f36 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_mcdi_reldetrptchkvdifthd. vertical dif thd (<) for repeat check, default = 16
+//Bit 7: 0, reg_mcdi_reldetrptchkhdifthd. horizontal dif thd (>=) for repeat check, default = 16
+#define MCDI_REL_DET_LPF_DIF_THD ((0x2f37 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetlpfdifthd3. hdif thd (<) for lpf selection of horizontal block, default = 9
+//Bit 23:16, reg_mcdi_reldetlpfdifthd2. vdif-hdif thd (>=) for lpf selection of horizontal block, default = 48
+//Bit 15: 8, reg_mcdi_reldetlpfdifthd1. vdif thd (<) for lpf selection of vertical block, default = 9
+//Bit 7: 0, reg_mcdi_reldetlpfdifthd0. hdif-vdif thd (>=) for lpf selection of vertical block, default = 48
+#define MCDI_REL_DET_LPF_MSK_00_03 ((0x2f38 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_mcdi_reldetlpfmsk03. det lpf mask03 for gmv/lmv locked mode, 0~16, default = 1
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_reldetlpfmsk02. det lpf mask02 for gmv/lmv locked mode, 0~16, default = 1
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_reldetlpfmsk01. det lpf mask01 for gmv/lmv locked mode, 0~16, default = 5
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetlpfmsk00. det lpf mask00 for gmv/lmv locked mode, 0~16, default = 8
+#define MCDI_REL_DET_LPF_MSK_04_12 ((0x2f39 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_mcdi_reldetlpfmsk12. det lpf mask12 for vertical blocks, 0~16, default = 0
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_reldetlpfmsk11. det lpf mask11 for vertical blocks, 0~16, default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_reldetlpfmsk10. det lpf mask10 for vertical blocks, 0~16, default = 16
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetlpfmsk04. det lpf mask04 for gmv/lmv locked mode, 0~16, default = 1
+#define MCDI_REL_DET_LPF_MSK_13_21 ((0x2f3a << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_mcdi_reldetlpfmsk21. det lpf mask21 for horizontal blocks, 0~16, default = 6
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_reldetlpfmsk20. det lpf mask20 for horizontal blocks, 0~16, default = 8
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_reldetlpfmsk14. det lpf mask14 for vertical blocks, 0~16, default = 0
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetlpfmsk13. det lpf mask13 for vertical blocks, 0~16, default = 0
+#define MCDI_REL_DET_LPF_MSK_22_30 ((0x2f3b << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_mcdi_reldetlpfmsk30. det lpf mask30 for other blocks, 0~16, default = 16
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_reldetlpfmsk24. det lpf mask24 for horizontal blocks, 0~16, default = 1
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_reldetlpfmsk23. det lpf mask23 for horizontal blocks, 0~16, default = 0
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetlpfmsk22. det lpf mask22 for horizontal blocks, 0~16, default = 1
+#define MCDI_REL_DET_LPF_MSK_31_34 ((0x2f3c << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_mcdi_reldetlpfmsk34. det lpf mask34 for other blocks, 0~16, default = 0
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_reldetlpfmsk33. det lpf mask33 for other blocks, 0~16, default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_reldetlpfmsk32. det lpf mask32 for other blocks, 0~16, default = 0
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetlpfmsk31. det lpf mask31 for other blocks, 0~16, default = 0
+//Note: there are four group lpf masks from addr 37~3b, each group sum equal to 16.
+#define MCDI_REL_DET_MIN ((0x2f3d << 2) + 0xff000000)
+//Bit 31: 7, reserved
+//Bit 6: 0, reg_mcdi_reldetmin. min of detected value, default = 16
+#define MCDI_REL_DET_LUT_0_3 ((0x2f3e << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetmaplut3. default = 8
+//Bit 23:16, reg_mcdi_reldetmaplut2. default = 4
+//Bit 15: 8, reg_mcdi_reldetmaplut1. default = 2
+//Bit 7: 0, reg_mcdi_reldetmaplut0. default = 0
+#define MCDI_REL_DET_LUT_4_7 ((0x2f3f << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetmaplut7. default = 64
+//Bit 23:16, reg_mcdi_reldetmaplut6. default = 48
+//Bit 15: 8, reg_mcdi_reldetmaplut5. default = 32
+//Bit 7: 0, reg_mcdi_reldetmaplut4. default = 16
+#define MCDI_REL_DET_LUT_8_11 ((0x2f40 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetmaplut11. default = 160
+//Bit 23:16, reg_mcdi_reldetmaplut10. default = 128
+//Bit 15: 8, reg_mcdi_reldetmaplut9. default = 96
+//Bit 7: 0, reg_mcdi_reldetmaplut8. default = 80
+#define MCDI_REL_DET_LUT_12_15 ((0x2f41 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetmaplut15. default = 255
+//Bit 23:16, reg_mcdi_reldetmaplut14. default = 240
+//Bit 15: 8, reg_mcdi_reldetmaplut13. default = 224
+//Bit 7: 0, reg_mcdi_reldetmaplut12. default = 192
+#define MCDI_REL_DET_COL_CFD_THD ((0x2f42 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetcolcfdfltthd. thd for flat smaller than (<) of column cofidence, default = 5
+//Bit 23:16, reg_mcdi_reldetcolcfdthd1. thd for rel larger than (>=) in rel calc. mode col confidence without gmv locking, default = 160
+//Bit 15: 8, reg_mcdi_reldetcolcfdthd0. thd for rel larger than (>=) in rel calc. mode col confidence when gmv locked, default = 100
+//Bit 7: 2, reg_mcdi_reldetcolcfdbadwthd. thd for badw larger than (>=) in qbadw calc. mode of column cofidence, default = 16
+//Bit 1, reserved
+//Bit 0, reg_mcdi_reldetcolcfdcalcmode. calc. mode for column cofidence, 0: use rel, 1: use qbadw, default = 0
+#define MCDI_REL_DET_COL_CFD_AVG_LUMA ((0x2f43 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetcolcfdavgmin1. avg luma min1 (>=) for column cofidence, valid between 16~235, default = 235
+//Bit 23:16, reg_mcdi_reldetcolcfdavgmax1. avg luma max1 (<) for column cofidence, valid between 16~235, default = 235
+//Bit 15: 8, reg_mcdi_reldetcolcfdavgmin0. avg luma min0 (>=) for column cofidence, valid between 16~235, default = 16
+//Bit 7: 0, reg_mcdi_reldetcolcfdavgmax0. avg luma max0 (<) for column cofidence, valid between 16~235, default = 21
+#define MCDI_REL_DET_BAD_THD_0 ((0x2f44 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_mcdi_reldetbadsadthd. thd (>=) for bad sad, default = 120 (480/4)
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_mcdi_reldetbadbadwthd. thd (>=) for bad badw, 0~42, default = 12
+#define MCDI_REL_DET_BAD_THD_1 ((0x2f45 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_mcdi_reldetbadrelfltthd. thd (>=) of flat for bad rel detection, default = 4
+//Bit 15: 8, reg_mcdi_reldetbadrelthd1. thd (>=) for bad rel without gmv/lmv locked, default = 160
+//Bit 7: 0, reg_mcdi_reldetbadrelthd0. thd (>=) for bad rel with gmv/lmv locked, default = 120
+#define MCDI_PD22_CHK_THD ((0x2f46 << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24:16, reg_mcdi_pd22chksaddifthd. sad dif thd (>=) for (pd22chksad - qsad) for pd22 check, default = 64
+//Bit 15:14, reserved
+//Bit 13: 8, reg_mcdi_pd22chkqmvthd. thd (>=) of abs qmv for pd22 check, default = 2
+//Bit 7: 0, reg_mcdi_pd22chkfltthd. thd (>=) of flat for pd22 check, default = 4
+#define MCDI_PD22_CHK_GAIN_OFFST_0 ((0x2f47 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_pd22chkedgeoffst0. offset0 of pd22chkedge from right film22 phase, -128~127, default = 0
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_pd22chkedgegain0. gain0 of pd22chkedge from right film22 phase, normalized to 16 as '1', default = 16
+//Bit 15:12, reserved
+//Bit 11: 8, reg_mcdi_pd22chkbadwoffst0. offset0 of pd22chkbadw from right film22 phase, -8~7, default = 0
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_pd22chkbadwgain0. gain0 of pd22chkbadw from right film22 phase, normalized to 16 as '1', default = 8
+#define MCDI_PD22_CHK_GAIN_OFFST_1 ((0x2f48 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_pd22chkedgeoffst1. offset1 of pd22chkedge from right film22 phase, -128~127, default = 0
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_pd22chkedgegain1. gain1 of pd22chkedge from right film22 phase, normalized to 16 as '1', default = 16
+//Bit 15:12, reserved
+//Bit 11: 8, reg_mcdi_pd22chkbadwoffst1. offset1 of pd22chkbadw from right film22 phase, -8~7, default = 0
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_pd22chkbadwgain1. gain1 of pd22chkbadw from right film22 phase, normalized to 16 as '1', default = 12
+#define MCDI_LMV_LOCK_CNT_THD_GAIN ((0x2f49 << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:16, reg_mcdi_lmvlockcntmax. max lmv lock count number, default = 6
+//Bit 15:12, reg_mcdi_lmvlockcntoffst. offset for lmv lock count, -8~7, default = 0
+//Bit 11: 8, reg_mcdi_lmvlockcntgain. gain for lmv lock count, normalized 8 as '1', 15 is set to 16, default = 8
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_lmvlockcntthd. lmv count thd (>=) before be locked, 1~31, default = 4
+#define MCDI_LMV_LOCK_ABS_DIF_THD ((0x2f4a << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:24, reg_mcdi_lmvlockdifthd2. lmv dif thd for third part, before locked, default = 1
+//Bit 23, reserved
+//Bit 22:20, reg_mcdi_lmvlockdifthd1. lmv dif thd for second part, before locked, default = 1
+//Bit 19, reserved
+//Bit 18:16, reg_mcdi_lmvlockdifthd0. lmv dif thd for first part, before locked, default = 1
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_lmvlockabsmax. max abs (<) of lmv to be locked, default = 24
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_lmvlockabsmin. min abs (>=) of lmv to be locked, default = 1
+#define MCDI_LMV_LOCK_ROW ((0x2f4b << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:16, reg_mcdi_lmvlockendrow. end row (<) for lmv lock, default = 2047
+//Bit 15:11, reserved
+//Bit 10: 0, reg_mcdi_lmvlockstartrow. start row (>=) for lmv lock, default = 0
+#define MCDI_LMV_LOCK_RT_MODE ((0x2f4c << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:24, reg_mcdi_lmvlockextmode. extend lines for lmv lock check, check how many lines for lmv locking, default = 2
+//Bit 23:16, reg_mcdi_lmvlockfltcntrt. ratio of flt cnt for lock check, normalized 256 as '1', 255 is set to 256, default = 32
+//Bit 15: 8, reg_mcdi_lmvlocklmvcntrt1. ratio when use non-zero lmv for lock check, normalized 256 as '1', 255 is set to 256, default = 48
+//Bit 7: 0, reg_mcdi_lmvlocklmvcntrt0. ratio when use max lmv for lock check, normalized 256 as '1', 255 is set to 256, default = 106
+#define MCDI_GMV_LOCK_CNT_THD_GAIN ((0x2f4d << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:16, reg_mcdi_gmvlockcntmax. max gmv lock count number, default = 6
+//Bit 15:12, reg_mcdi_gmvlockcntoffst. offset for gmv lock count, -8~7, default = 0
+//Bit 11: 8, reg_mcdi_gmvlockcntgain. gain for gmv lock count, normalized 8 as '1', 15 is set to 16, default = 8
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_gmvlockcntthd. gmv count thd (>=) before be locked, 1~31, default = 4
+#define MCDI_GMV_LOCK_ABS_DIF_THD ((0x2f4e << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:24, reg_mcdi_gmvlockdifthd2. gmv dif thd for third part, before locked, default = 3
+//Bit 23, reserved
+//Bit 22:20, reg_mcdi_gmvlockdifthd1. gmv dif thd for second part, before locked, default = 2
+//Bit 19, reserved
+//Bit 18:16, reg_mcdi_gmvlockdifthd0. gmv dif thd for first part, before locked, default = 1
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_gmvlockabsmax. max abs of gmv to be locked, default = 15
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_gmvlockabsmin. min abs of gmv to be locked, default = 1
+#define MCDI_HIGH_VERT_FRQ_DIF_THD ((0x2f4f << 2) + 0xff000000)
+//Bit 31: 0, reg_mcdi_highvertfrqfldavgdifthd. high_vert_frq field average luma dif thd (>=), 3*Blk_Width*Blk_Height, set by software, default = 103680
+#define MCDI_HIGH_VERT_FRQ_DIF_DIF_THD ((0x2f50 << 2) + 0xff000000)
+//Bit 31: 0, reg_mcdi_highvertfrqfldavgdifdifthd. high_vert_frq field average luma dif's dif thd (<), 3*Blk_Width*Blk_Height, set by software, default = 103680
+#define MCDI_HIGH_VERT_FRQ_RT_GAIN ((0x2f51 << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:16, reg_mcdi_highvertfrqcntthd. high_vert_frq count thd (>=) before locked, 1~31, default = 4
+//Bit 15: 8, reg_mcdi_highvertfrqbadsadrt. ratio for high_vert_frq bad sad count, normalized 256 as '1', 255 is set to 256, default = 24
+//Bit 7: 0, reg_mcdi_highvertfrqbadbadwrt. ratio for high_vert_frq badw count, normalized 256 as '1', 255 is set to 256, default = 130
+#define MCDI_MOTION_PARADOX_THD ((0x2f52 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_mcdi_motionparadoxcntthd. motion paradox count thd (>=) before locked, 1~31, default = 4
+//Bit 23:22, reserved
+//Bit 21:16, reg_mcdi_motionparadoxgmvthd. abs gmv thd (<) of motion paradox, 0~32, note that 32 means invalid gmv, be careful, default = 32
+//Bit 15: 0, reserved
+#define MCDI_MOTION_PARADOX_RT ((0x2f53 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_mcdi_motionparadoxbadsadrt. ratio for field bad sad count of motion paradox, normalized 256 as '1', 255 is set to 256, default = 24
+//Bit 15: 8, reg_mcdi_motionparadoxbadrelrt. ratio for field bad reliabilty count of motion paradox, normalized 256 as '1', 255 is set to 256, default = 120
+//Bit 7: 0, reg_mcdi_motionparadoxmtnrt. ratio for field motion count of motion paradox, normalized 256 as '1', 255 is set to 256, default = 218
+#define MCDI_MOTION_REF_THD ((0x2f54 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:20, reg_mcdi_motionrefoffst. motion ref additive offset, default = 15
+//Bit 19:16, reg_mcdi_motionrefgain. motion ref gain, normalized 8 as '1', default = 8
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_motionrefrptmvthd. abs thd (>=) of rpt mv (0~31, 32 means invalid) for motion ref, default = 1
+//Bit 7: 2, reg_mcdi_motionrefqmvthd. min thd (>=) of abs qmv for motion ref, note that quarter mv's range is -63~63, default = 2
+//Bit 1: 0, reg_mcdi_motionreflpfmode. Mv and (8 x repeat flg) 's lpf mode of motion refinement, 0: no lpf, 1: [1 2 1], 2: [1 2 2 2 1], default = 1
+#define MCDI_REL_COL_REF_RT ((0x2f55 << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_mcdi_relcolrefrt. ratio for column cofidence level against column number, for refinement, default = 135
+#define MCDI_PD22_CHK_THD_RT ((0x2f56 << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:16, reg_mcdi_pd22chkfltcntrt. ratio for flat count of field pulldown 22 check, normalized 2048 as '1', 2047 is set to 2048, default = 1
+//Bit 15: 8, reg_mcdi_pd22chkcntrt. ratio of pulldown 22 check count, normalized 256 as '1', 255 is set to 256, default = 100
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_pd22chkcntthd. thd (>=) for pd22 count before locked, 1~31, default = 4
+#define MCDI_CHAR_DET_DIF_THD ((0x2f57 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_mcdi_chardetminmaxdifthd. thd (>=) for dif between min and max value, default = 64
+//Bit 15: 8, reg_mcdi_chardetmaxdifthd. thd (<) for dif between max value, default = 17
+//Bit 7: 0, reg_mcdi_chardetmindifthd. thd (<) for dif between min value, default = 17
+#define MCDI_CHAR_DET_CNT_THD ((0x2f58 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_mcdi_chardettotcntthd. thd (>=) for total count, 0~21, default = 18
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_chardetmaxcntthd. thd (>=) for max count, 0~21, default = 1
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_chardetmincntthd. thd (>=) for min count, 0~21, default = 1
+//new add
+#define MCDI_PD_22_CHK_WND0_X ((0x2f59 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_mcdi_pd22chkwnd0_x1 u13, x1 for window 0, HSIZE-1, software control, default = 719
+//Bit 15:13, reserved
+//Bit 12: 0, reg_mcdi_pd22chkwnd0_x0 u13, x0 for window 0, software control, default = 0
+#define MCDI_PD_22_CHK_WND0_Y ((0x2f5a << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_mcdi_pd22chkwnd0_y1 u13, y1 for window 0 software control, default = 39
+//Bit 15:13, reserved
+//Bit 12: 0, reg_mcdi_pd22chkwnd0_y0 u13, y0 for window 0, software control, default = 0
+#define MCDI_PD_22_CHK_WND1_X ((0x2f5b << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_mcdi_pd22chkwnd1_x1 u13, x1 for window 1, HSIZE-1, software control, default = 719
+//Bit 15:13, reserved
+//Bit 12: 0, reg_mcdi_pd22chkwnd1_x0 u13, x0 for window 1, software control, default = 0
+#define MCDI_PD_22_CHK_WND1_Y ((0x2f5c << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_mcdi_pd22chkwnd1_y1 u13, y1 for window 1 software control, default = 199
+//Bit 15:13, reserved
+//Bit 12: 0, reg_mcdi_pd22chkwnd1_y0 u13, y0 for window 1, software control, default = 40
+#define MCDI_PD_22_CHK_FRC_LMV ((0x2f5d << 2) + 0xff000000)
+//Bit 31:11, reserved
+//Bit 10, reg_mcdi_pd22chklmvchk2 u1, lmv lock check while force vof for each windows, default = 1
+//Bit 9, reg_mcdi_pd22chklmvchk1 u1, lmv lock check while force vof for each windows, default = 0
+//Bit 8, reg_mcdi_pd22chklmvchk0 u1, lmv lock check while force vof for each windows, default = 0
+//Bit 7, reserved
+//Bit 6, reg_mcdi_pd22chkfrcpd2 u1, force pd flags for each windows, default = 0
+//Bit 5, reg_mcdi_pd22chkfrcpd1 u1, force pd flags for each windows, default = 0
+//Bit 4, reg_mcdi_pd22chkfrcpd0 u1, force pd flags for each windows, default = 0
+//Bit 3, reserved
+//Bit 2, reg_mcdi_pd22chkfrcvof2 u1, force vof flags for each windows, default = 1
+//Bit 1, reg_mcdi_pd22chkfrcvof1 u1, force vof flags for each windows, default = 0
+//Bit 0, reg_mcdi_pd22chkfrcvof0 u1, force vof flags for each windows, default = 0
+#define MCDI_PD_22_CHK_FLG_CNT ((0x2f5e << 2) + 0xff000000)
+//Bit 31:27, reserved.
+//Bit 26, reg_mcdi_pd22chkflg2. pull down 22 flag of prevoius one field. initial = 0
+//Bit 25, reg_mcdi_pd22chkflg1. pull down 22 flag of prevoius one field. initial = 0
+//Bit 24, reg_mcdi_pd22chkflg. pull down 22 flag of prevoius one field. initial = 0
+//Bit 23:16, reg_mcdi_pd22chkcnt2. pull down 22 count till prevoius one field. initial = 0
+//Bit 15: 8, reg_mcdi_pd22chkcnt1. pull down 22 count till prevoius one field. initial = 0
+//Bit 7: 0, reg_mcdi_pd22chkcnt. pull down 22 count till prevoius one field. initial = 0
+#define MCDI_RO_FLD_PD_22_PRE_CNT1 ((0x2fca << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22precnt1. prevoius pd22 check count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_FOR_CNT1 ((0x2fcb << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22forcnt1. forward pd22 check count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_FLT_CNT1 ((0x2fcc << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22fltcnt1. flat count (for pd22 check) of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_PRE_CNT2 ((0x2fcd << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22precnt2. prevoius pd22 check count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_FOR_CNT2 ((0x2fce << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22forcnt2. forward pd22 check count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_FLT_CNT2 ((0x2fcf << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22fltcnt2. flat count (for pd22 check) of whole pre one field (block based). initial = 0
+#define MCDI_FIELD_MV ((0x2f60 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_pd22chkcnt
+//Bit 23:16, reg_mcdi_fieldgmvcnt
+//Bit 15, reg_mcdi_pd22chkflg
+//Bit 14, reg_mcdi_fieldgmvlock
+//Bit 13: 8, reg_mcdi_fieldrptmv. last field rpt mv
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_mcdi_fieldgmv. last field gmv
+#define MCDI_FIELD_HVF_PRDX_CNT ((0x2f61 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_motionparadoxcnt.
+//Bit 23:17, reserved
+//Bit 16, reg_mcdi_motionparadoxflg.
+//Bit 15: 8, reg_mcdi_highvertfrqcnt.
+//Bit 7: 4, reserved
+//Bit 3: 2, reg_mcdi_highvertfrqphase.
+//Bit 1, reserved
+//Bit 0, reg_mcdi_highvertfrqflg.
+#define MCDI_FIELD_LUMA_AVG_SUM_0 ((0x2f62 << 2) + 0xff000000)
+//Bit 31: 0, reg_mcdi_fld_luma_avg_sum0.
+#define MCDI_FIELD_LUMA_AVG_SUM_1 ((0x2f63 << 2) + 0xff000000)
+//Bit 31: 0, reg_mcdi_fld_luma_avg_sum1.
+#define MCDI_YCBCR_BLEND_CRTL ((0x2f64 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_mcdi_ycbcrblendgain. ycbcr blending gain for cbcr in ycbcr. default = 0
+//Bit 7: 2, reserved.
+//Bit 1: 0, reg_mcdi_ycbcrblendmode. 0:y+cmb(cb,cr), 1:med(r,g,b), 2:max(r,g,b), default = 2
+#define MCDI_MCVECWR_CANVAS_SIZE ((0x2f65 << 2) + 0xff000000)
+#define MCDI_MCVECRD_CANVAS_SIZE ((0x2f66 << 2) + 0xff000000)
+#define MCDI_MCINFOWR_CANVAS_SIZE ((0x2f67 << 2) + 0xff000000)
+#define MCDI_MCINFORD_CANVAS_SIZE ((0x2f68 << 2) + 0xff000000)
+#define MCDI_MCVECWR_X ((0x2f92 << 2) + 0xff000000)
+#define MCDI_MCVECWR_Y ((0x2f93 << 2) + 0xff000000)
+#define MCDI_MCVECWR_CTRL ((0x2f94 << 2) + 0xff000000)
+#define MCDI_MCVECRD_X ((0x2f95 << 2) + 0xff000000)
+#define MCDI_MCVECRD_Y ((0x2f96 << 2) + 0xff000000)
+#define MCDI_MCVECRD_CTRL ((0x2f97 << 2) + 0xff000000)
+#define MCDI_MCINFOWR_X ((0x2f98 << 2) + 0xff000000)
+#define MCDI_MCINFOWR_Y ((0x2f99 << 2) + 0xff000000)
+#define MCDI_MCINFOWR_CTRL ((0x2f9a << 2) + 0xff000000)
+#define MCDI_MCINFORD_X ((0x2f9b << 2) + 0xff000000)
+#define MCDI_MCINFORD_Y ((0x2f9c << 2) + 0xff000000)
+#define MCDI_MCINFORD_CTRL ((0x2f9d << 2) + 0xff000000)
+#define MCDI_LMVLCKSTEXT_0 ((0x2f69 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, mcdi_lmvlckstext_1 lmv lck blog 1 line start
+//Bit 15:12, reserved
+//Bit 11: 0, mcdi_lmvlckstext_0 lmv lck blog 0 line start
+#define MCDI_LMVLCKSTEXT_1 ((0x2f6a << 2) + 0xff000000)
+//Bit 31 , mcdi_refnewmode new ref me mv array order
+//Bit 30 , mcdi_ref_lmv_lck_en use locked line mvs for ref
+//Bit 29:28, mcdi_lmvlckupdw_ext up/down extend lines for locked lmv line's
+//Bit 27:12, mcdi_lmvlckmin lmv lck blog height limit
+//Bit 15:12, reserved
+//Bit 11: 0, mcdi_lmvlckstext_2 lmv lck blog 2 line start
+#define MCDI_LMVLCKEDEXT_0 ((0x2f6b << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, mcdi_lmvlckedext_1 lmv lck blog 1 line end
+//Bit 15:12, reserved
+//Bit 11: 0, mcdi_lmvlckedext_0 lmv lck blog 0 line end
+#define MCDI_LMVLCKEDEXT_1 ((0x2f6c << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11: 0, mcdi_lmvlckedext_2 lmv lck blog 2 line end
+// ================================================================== MC registers ========================================================================================================
+#define MCDI_MC_CRTL ((0x2f70 << 2) + 0xff000000)
+//Bit 31: 9, reserved
+//Bit 8, reg_mcdi_mcpreflg. flag to use previous field for MC, 0:forward field, 1: previous field, default = 1
+//Bit 7, reg_mcdi_mcrelrefbycolcfden. enable rel refinement by column cofidence in mc blending, default = 1
+//Bit 6: 5, reg_mcdi_mclpfen. enable mc pixles/rel lpf, 0:disable, 1: lpf rel, 2: lpf mc pxls, 3: lpf both rel and mc pxls, default = 0
+//Bit 4: 2, reg_mcdi_mcdebugmode. enable mc debug mode, 0:disable, 1: split left/right, 2: split top/bottom, 3: debug mv, 4: debug rel, default = 0
+//Bit 1: 0, reg_mcdi_mcen. mcdi enable mode, 0:disable, 1: blend with ma, 2: full mc, default = 1
+#define MCDI_MC_LPF_MSK_0 ((0x2f71 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_mcdi_mclpfmsk02. mc lpf coef. 2 for pixel 0 of current block, normalized 16 as '1', default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_mclpfmsk01. mc lpf coef. 1 for pixel 0 of current block, normalized 16 as '1', default = 9
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_mclpfmsk00. mc lpf coef. 0 for pixel 0 of current block, normalized 16 as '1', default = 7
+#define MCDI_MC_LPF_MSK_1 ((0x2f72 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_mcdi_mclpfmsk12. mc lpf coef. 2 for pixel 1 of current block, 0~16, normalized 16 as '1', default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_mclpfmsk11. mc lpf coef. 1 for pixel 1 of current block, 0~16, normalized 16 as '1', default = 11
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_mclpfmsk10. mc lpf coef. 0 for pixel 1 of current block, 0~16, normalized 16 as '1', default = 5
+#define MCDI_MC_LPF_MSK_2 ((0x2f73 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_mcdi_mclpfmsk22. mc lpf coef. 2 for pixel 2 of current block, 0~16, normalized 16 as '1', default = 1
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_mclpfmsk21. mc lpf coef. 1 for pixel 2 of current block, 0~16, normalized 16 as '1', default = 14
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_mclpfmsk20. mc lpf coef. 0 for pixel 2 of current block, 0~16, normalized 16 as '1', default = 1
+#define MCDI_MC_LPF_MSK_3 ((0x2f74 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_mcdi_mclpfmsk32. mc lpf coef. 2 for pixel 3 of current block, 0~16, normalized 16 as '1', default = 5
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_mclpfmsk31. mc lpf coef. 1 for pixel 3 of current block, 0~16, normalized 16 as '1', default = 11
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_mclpfmsk30. mc lpf coef. 0 for pixel 3 of current block, 0~16, normalized 16 as '1', default = 0
+#define MCDI_MC_LPF_MSK_4 ((0x2f75 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_mcdi_mclpfmsk42. mc lpf coef. 2 for pixel 4 of current block, 0~16, normalized 16 as '1', default = 7
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_mclpfmsk41. mc lpf coef. 1 for pixel 4 of current block, 0~16, normalized 16 as '1', default = 9
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_mclpfmsk40. mc lpf coef. 0 for pixel 4 of current block, 0~16, normalized 16 as '1', default = 0
+#define MCDI_MC_REL_GAIN_OFFST_0 ((0x2f76 << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25, reg_mcdi_mcmotionparadoxflg. flag of motion paradox, initial with 0 and read from software, default = 0
+//Bit 24, reg_mcdi_mchighvertfrqflg. flag of high vert frq, initial with 0 and read from software, default = 0
+//Bit 23:16, reg_mcdi_mcmotionparadoxoffst. offset (rel + offset) for rel (MC blending coef.) refinement if motion paradox detected before MC blending before MC blending, default = 128
+//Bit 15:12, reserved
+//Bit 11: 8, reg_mcdi_mcmotionparadoxgain. gain for rel (MC blending coef.) refinement if motion paradox detected before MC blending, normalized 8 as '1', set 15 to 16, default = 8
+//Bit 7: 4, reg_mcdi_mchighvertfrqoffst. minus offset (alpha - offset) for motion (MA blending coef.) refinement if high vertical frequency detected before MA blending, default = 15
+//Bit 3: 0, reg_mcdi_mchighvertfrqgain. gain for motion (MA blending coef.) refinement if high vertical frequency detected before MA blending, normalized 8 as '1', set 15 to 16, default = 8
+#define MCDI_MC_REL_GAIN_OFFST_1 ((0x2f77 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_mcoutofboundrayoffst. offset (rel + offset) for rel (MC blending coef.) refinement if MC pointed out of boundray before MC blending before MC blending, default = 255
+//Bit 23:20, reserved
+//Bit 19:16, reg_mcdi_mcoutofboundraygain. gain for rel (MC blending coef.) refinement if MC pointed out of boundray before MC blending, normalized 8 as '1', set 15 to 16, default = 8
+//Bit 15: 8, reg_mcdi_mcrelrefbycolcfdoffst. offset (rel + offset) for rel (MC blending coef.) refinement if motion paradox detected before MC blending before MC blending, default = 255
+//Bit 7: 4, reserved.
+//Bit 3: 0, reg_mcdi_mcrelrefbycolcfdgain. gain for rel (MC blending coef.) refinement if column cofidence failed before MC blending, normalized 8 as '1', set 15 to 16, default = 8
+#define MCDI_MC_COL_CFD_0 ((0x2f78 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_0. column cofidence value 0 read from software. initial = 0
+#define MCDI_MC_COL_CFD_1 ((0x2f79 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_1. column cofidence value 1 read from software. initial = 0
+#define MCDI_MC_COL_CFD_2 ((0x2f7a << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_2. column cofidence value 2 read from software. initial = 0
+#define MCDI_MC_COL_CFD_3 ((0x2f7b << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_3. column cofidence value 3 read from software. initial = 0
+#define MCDI_MC_COL_CFD_4 ((0x2f7c << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_4. column cofidence value 4 read from software. initial = 0
+#define MCDI_MC_COL_CFD_5 ((0x2f7d << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_5. column cofidence value 5 read from software. initial = 0
+#define MCDI_MC_COL_CFD_6 ((0x2f7e << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_6. column cofidence value 6 read from software. initial = 0
+#define MCDI_MC_COL_CFD_7 ((0x2f7f << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_7. column cofidence value 7 read from software. initial = 0
+#define MCDI_MC_COL_CFD_8 ((0x2f80 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_8. column cofidence value 8 read from software. initial = 0
+#define MCDI_MC_COL_CFD_9 ((0x2f81 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_9. column cofidence value 9 read from software. initial = 0
+#define MCDI_MC_COL_CFD_10 ((0x2f82 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_10. column cofidence value 10 read from software. initial = 0
+#define MCDI_MC_COL_CFD_11 ((0x2f83 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_11. column cofidence value 11 read from software. initial = 0
+#define MCDI_MC_COL_CFD_12 ((0x2f84 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_12. column cofidence value 12 read from software. initial = 0
+#define MCDI_MC_COL_CFD_13 ((0x2f85 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_13. column cofidence value 13 read from software. initial = 0
+#define MCDI_MC_COL_CFD_14 ((0x2f86 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_14. column cofidence value 14 read from software. initial = 0
+#define MCDI_MC_COL_CFD_15 ((0x2f87 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_15. column cofidence value 15 read from software. initial = 0
+#define MCDI_MC_COL_CFD_16 ((0x2f88 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_16. column cofidence value 16 read from software. initial = 0
+#define MCDI_MC_COL_CFD_17 ((0x2f89 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_17. column cofidence value 17 read from software. initial = 0
+#define MCDI_MC_COL_CFD_18 ((0x2f8a << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_18. column cofidence value 18 read from software. initial = 0
+#define MCDI_MC_COL_CFD_19 ((0x2f8b << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_19. column cofidence value 19 read from software. initial = 0
+#define MCDI_MC_COL_CFD_20 ((0x2f8c << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_20. column cofidence value 20 read from software. initial = 0
+#define MCDI_MC_COL_CFD_21 ((0x2f8d << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_21. column cofidence value 21 read from software. initial = 0
+#define MCDI_MC_COL_CFD_22 ((0x2f8e << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_22. column cofidence value 22 read from software. initial = 0
+#define MCDI_MC_COL_CFD_23 ((0x2f8f << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_23. column cofidence value 23 read from software. initial = 0
+#define MCDI_MC_COL_CFD_24 ((0x2f90 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_24. column cofidence value 24 read from software. initial = 0
+#define MCDI_MC_COL_CFD_25 ((0x2f91 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_25. column cofidence value 25 read from software. initial = 0
+// ===================================================================================== PRE RO Registers ==========================================================================================
+#define MCDI_RO_FLD_LUMA_AVG_SUM ((0x2fa0 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldlumaavgsum. block's luma avg sum of current filed (block based). initial = 0
+#define MCDI_RO_GMV_VLD_CNT ((0x2fa1 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_gmvvldcnt. valid gmv's count of pre one filed (block based). initial = 0
+#define MCDI_RO_RPT_FLG_CNT ((0x2fa2 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_rptflgcnt. repeat mv's count of pre one filed (block based). initial = 0
+#define MCDI_RO_FLD_BAD_SAD_CNT ((0x2fa3 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldbadsadcnt. bad sad count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_BAD_BADW_CNT ((0x2fa4 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldbadbadwcnt. bad badw count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_BAD_REL_CNT ((0x2fa5 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldbadrelcnt. bad rel count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_MTN_CNT ((0x2fa6 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldmtncnt. motion count of whole pre one field (pixel based). initial = 0
+#define MCDI_RO_FLD_VLD_CNT ((0x2fa7 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldvldcnt. valid motion count of whole pre one field (pixel based). initial = 0
+#define MCDI_RO_FLD_PD_22_PRE_CNT ((0x2fa8 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22precnt. prevoius pd22 check count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_FOR_CNT ((0x2fa9 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22forcnt. forward pd22 check count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_FLT_CNT ((0x2faa << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22fltcnt. flat count (for pd22 check) of whole pre one field (block based). initial = 0
+#define MCDI_RO_HIGH_VERT_FRQ_FLG ((0x2fab << 2) + 0xff000000)
+//Bit 31:16, reserved.
+//Bit 15: 8, ro_mcdi_highvertfrqcnt. high vertical frequency count till prevoius one field. initial = 0
+//Bit 7: 3, reserved.
+//Bit 2: 1, ro_mcdi_highvertfrqphase. high vertical frequency phase of prevoius one field. initial = 2
+//Bit 0, ro_mcdi_highvertfrqflg. high vertical frequency flag of prevoius one field. initial = 0
+#define MCDI_RO_GMV_LOCK_FLG ((0x2fac << 2) + 0xff000000)
+//Bit 31:16, reserved.
+//Bit 15: 8, ro_mcdi_gmvlckcnt. global mv lock count till prevoius one field. initial = 0
+//Bit 7: 2, ro_mcdi_gmv. global mv of prevoius one field. -31~31, initial = 32 (invalid value)
+//Bit 1, ro_mcdi_zerogmvlckflg. zero global mv lock flag of prevoius one field. initial = 0
+//Bit 0, ro_mcdi_gmvlckflg. global mv lock flag of prevoius one field. initial = 0
+#define MCDI_RO_RPT_MV ((0x2fad << 2) + 0xff000000)
+//Bit 5: 0, ro_mcdi_rptmv. repeate mv of prevoius one field. -31~31, initial = 32 (invalid value)
+#define MCDI_RO_MOTION_PARADOX_FLG ((0x2fae << 2) + 0xff000000)
+//Bit 31:16, reserved.
+//Bit 15: 8, ro_mcdi_motionparadoxcnt. motion paradox count till prevoius one field. initial = 0
+//Bit 7: 1, reserved.
+//Bit 0, ro_mcdi_motionparadoxflg. motion paradox flag of prevoius one field. initial = 0
+#define MCDI_RO_PD_22_FLG ((0x2faf << 2) + 0xff000000)
+//Bit 31:27, reserved.
+//Bit 26, ro_mcdi_pd22flg2. pull down 22 flag of prevoius one field. initial = 0
+//Bit 25, ro_mcdi_pd22flg1. pull down 22 flag of prevoius one field. initial = 0
+//Bit 24, ro_mcdi_pd22flg. pull down 22 flag of prevoius one field. initial = 0
+//Bit 23:16, ro_mcdi_pd22cnt2. pull down 22 count till prevoius one field. initial = 0
+//Bit 15: 8, ro_mcdi_pd22cnt1. pull down 22 count till prevoius one field. initial = 0
+//Bit 7: 0, ro_mcdi_pd22cnt. pull down 22 count till prevoius one field. initial = 0
+#define MCDI_RO_COL_CFD_0 ((0x2fb0 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_0. column cofidence value 0. initial = 0
+#define MCDI_RO_COL_CFD_1 ((0x2fb1 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_1. column cofidence value 1. initial = 0
+#define MCDI_RO_COL_CFD_2 ((0x2fb2 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_2. column cofidence value 2. initial = 0
+#define MCDI_RO_COL_CFD_3 ((0x2fb3 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_3. column cofidence value 3. initial = 0
+#define MCDI_RO_COL_CFD_4 ((0x2fb4 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_4. column cofidence value 4. initial = 0
+#define MCDI_RO_COL_CFD_5 ((0x2fb5 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_5. column cofidence value 5. initial = 0
+#define MCDI_RO_COL_CFD_6 ((0x2fb6 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_6. column cofidence value 6. initial = 0
+#define MCDI_RO_COL_CFD_7 ((0x2fb7 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_7. column cofidence value 7. initial = 0
+#define MCDI_RO_COL_CFD_8 ((0x2fb8 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_8. column cofidence value 8. initial = 0
+#define MCDI_RO_COL_CFD_9 ((0x2fb9 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_9. column cofidence value 9. initial = 0
+#define MCDI_RO_COL_CFD_10 ((0x2fba << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_10. column cofidence value 10. initial = 0
+#define MCDI_RO_COL_CFD_11 ((0x2fbb << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_11. column cofidence value 11. initial = 0
+#define MCDI_RO_COL_CFD_12 ((0x2fbc << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_12. column cofidence value 12. initial = 0
+#define MCDI_RO_COL_CFD_13 ((0x2fbd << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_13. column cofidence value 13. initial = 0
+#define MCDI_RO_COL_CFD_14 ((0x2fbe << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_14. column cofidence value 14. initial = 0
+#define MCDI_RO_COL_CFD_15 ((0x2fbf << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_15. column cofidence value 15. initial = 0
+#define MCDI_RO_COL_CFD_16 ((0x2fc0 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_16. column cofidence value 16. initial = 0
+#define MCDI_RO_COL_CFD_17 ((0x2fc1 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_17. column cofidence value 17. initial = 0
+#define MCDI_RO_COL_CFD_18 ((0x2fc2 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_18. column cofidence value 18. initial = 0
+#define MCDI_RO_COL_CFD_19 ((0x2fc3 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_19. column cofidence value 19. initial = 0
+#define MCDI_RO_COL_CFD_20 ((0x2fc4 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_20. column cofidence value 20. initial = 0
+#define MCDI_RO_COL_CFD_21 ((0x2fc5 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_21. column cofidence value 21. initial = 0
+#define MCDI_RO_COL_CFD_22 ((0x2fc6 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_22. column cofidence value 22. initial = 0
+#define MCDI_RO_COL_CFD_23 ((0x2fc7 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_23. column cofidence value 23. initial = 0
+#define MCDI_RO_COL_CFD_24 ((0x2fc8 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_24. column cofidence value 24. initial = 0
+#define MCDI_RO_COL_CFD_25 ((0x2fc9 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_25. column cofidence value 25. initial = 0
+// add space 8'hd0-8'hef
+//
+// Reading file: dipd_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// using 8'he0-8'hef
+#define DIPD_COMB_CTRL0 ((0x2fd0 << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl0
+#define DIPD_COMB_CTRL1 ((0x2fd1 << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl1
+#define DIPD_COMB_CTRL2 ((0x2fd2 << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl2
+#define DIPD_COMB_CTRL3 ((0x2fd3 << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl3
+#define DIPD_COMB_CTRL4 ((0x2fd4 << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl4
+#define DIPD_COMB_CTRL5 ((0x2fd5 << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl5
+#define DIPD_RO_COMB_0 ((0x2fd6 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_0
+#define DIPD_RO_COMB_1 ((0x2fd7 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_1
+#define DIPD_RO_COMB_2 ((0x2fd8 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_2
+#define DIPD_RO_COMB_3 ((0x2fd9 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_3
+#define DIPD_RO_COMB_4 ((0x2fda << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_4
+#define DIPD_RO_COMB_5 ((0x2fdb << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_5
+#define DIPD_RO_COMB_6 ((0x2fdc << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_6
+#define DIPD_RO_COMB_7 ((0x2fdd << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_7
+#define DIPD_RO_COMB_8 ((0x2fde << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_8
+#define DIPD_RO_COMB_9 ((0x2fdf << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_9
+#define DIPD_RO_COMB_10 ((0x2fe0 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_10
+#define DIPD_RO_COMB_11 ((0x2fe1 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_11
+#define DIPD_RO_COMB_12 ((0x2fe2 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_12
+#define DIPD_RO_COMB_13 ((0x2fe3 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_13
+#define DIPD_RO_COMB_14 ((0x2fe4 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_14
+#define DIPD_RO_COMB_15 ((0x2fe5 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_15
+#define DIPD_RO_COMB_16 ((0x2fe6 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_16
+#define DIPD_RO_COMB_17 ((0x2fe7 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_17
+#define DIPD_RO_COMB_18 ((0x2fe8 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_18
+#define DIPD_RO_COMB_19 ((0x2fe9 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_19
+#define DIPD_RO_COMB_20 ((0x2fea << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_20
+#define DIPD_COMB_CTRL6 ((0x2feb << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl6
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dipd_regs.h
+//
+// addr space 8'hf0-8'hff
+//
+// Reading file: nr3_tnr_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define NR3_MODE ((0x2ff0 << 2) + 0xff000000)
+//Bit 31: 6 reserved
+//Bit 5 reg_nr3_vtxt_mode // unsigned , default = 0 0: avg; 1:MAX
+//Bit 4 reg_3dnr_nr3_cbyy_ignor_coop // unsigned , default = 0 ignore coop condition for cbyy motion decision
+//Bit 3 reg_3dnr_nr3_ybyc_ignor_cnoop // unsigned , default = 0 ignore cnoop condition for ybyc motion decision
+//Bit 2: 0 reg_3dnr_nr3_suremot_txt_mode // unsigned , default = 3 0: cur, 1:p2; 2: (cur+p2)/2; 3/up: min(cur,p2)
+#define NR3_COOP_PARA ((0x2ff1 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:20 reg_3dnr_nr3_coop_mode // unsigned , default = 2 0 original pixel 1: [1 2 1]/4 lpf; 2: [1 2 2 2 1]/8; 3: 3x3 lpf
+//Bit 19:16 reg_3dnr_nr3_coop_ratio // unsigned , default = 8 cur and p2 color oop decision ratio: (avg1<(dif1*ratio/8 + ofst));
+//Bit 15: 8 reg_3dnr_nr3_coop_ofset // signed , default = -1 cur and p2 color oop decision ofst: (avg1<(dif1*ratio/8 + ofst));
+//Bit 7: 0 reg_3dnr_nr3_coop_sat_thrd // unsigned , default = 0 cur and p2 color oop decision min(sat0,sat1) threshold;
+#define NR3_CNOOP_GAIN ((0x2ff2 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:20 reg_3dnr_nr3_cnoop_ratio0 // unsigned , default = 8 cur and p2 color noop decision ratio0: (avg1<(MAX(sat0,sat2)*ratio0/8 + ofst0));
+//Bit 19:16 reg_3dnr_nr3_cnoop_ratio1 // unsigned , default = 8 cur and p2 color noop decision ratio1: (dif1<(MIN(sat0,sat2)*ratio1/8 + ofst1));
+//Bit 15: 8 reg_3dnr_nr3_cnoop_ofset0 // signed , default = 25 cur and p2 color noop decision ofset0: (avg1<(MAX(sat0,sat2)*ratio0/8 + ofst0));
+//Bit 7: 0 reg_3dnr_nr3_cnoop_ofset1 // signed , default = 0 cur and p2 color noop decision ofset1: (dif1<(MIN(sat0,sat2)*ratio1/8 + ofst1));
+#define NR3_YMOT_PARA ((0x2ff3 << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19 reg_3dnr_nr3_ymot_only_en // unsigned , default = 1 enable signal for ignor chroma motion: (ytxt &coop)
+//Bit 18 reg_3dnr_nr3_ymot_only_cmtmode // unsigned , default = 1 0: cmot=ymot; 1: cmot = MIN(ymot, cmot)
+//Bit 17:16 reg_3dnr_nr3_ymot_only_txtmode // unsigned , default = 0 0, min(txt0,txt2); 1, max(txt0,txt2);2, (txt0+txt2)/2; 3: sat(txt0, txt2)
+//Bit 15: 8 reg_3dnr_nr3_ymot_only_txtthrd // unsigned , default = 10 threshold to luma texture to decide use ymot only
+//Bit 7: 0 reg_3dnr_nr3_ymot_only_motthrd // unsigned , default = 30 threshold to luma motion to decide use ymot only
+#define NR3_CMOT_PARA ((0x2ff4 << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19 reg_3dnr_nr3_cmot_only_en // unsigned , default = 1 enable signal for ignor luma motion: (ctxt &cnoop)
+//Bit 18 reg_3dnr_nr3_cmot_only_ymtmode // unsigned , default = 0 0: ymot=cmot+ymot/4; 1: ymot = MIN(ymot, cmot)
+//Bit 17:16 reg_3dnr_nr3_cmot_only_txtmode // unsigned , default = 0 0, min(txt0,txt2); 1, max(txt0,txt2);2, (txt0+txt2)/2; 3: sat(txt0, txt2)
+//Bit 15: 8 reg_3dnr_nr3_cmot_only_txtthrd // unsigned , default = 20 threshold to chroma texture to decide use cmot only
+//Bit 7: 0 reg_3dnr_nr3_cmot_only_motthrd // unsigned , default = 15 threshold to chroma motion to decide use cmot only
+#define NR3_SUREMOT_YGAIN ((0x2ff5 << 2) + 0xff000000)
+//Bit 31:24 reg_3dnr_nr3_suremot_dec_yrate // unsigned , default = 16 (norm 16)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+//Bit 23:16 reg_3dnr_nr3_suremot_dec_yofst // unsigned , default = 12 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+//Bit 15: 8 reg_3dnr_nr3_suremot_frc_ygain // unsigned , default = 64 (norm 8)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+//Bit 7: 0 reg_3dnr_nr3_suremot_frc_yofst // unsigned , default = 20 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+#define NR3_SUREMOT_CGAIN ((0x2ff6 << 2) + 0xff000000)
+//Bit 31:24 reg_3dnr_nr3_suremot_dec_crate // unsigned , default = 34 (norm 16)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+//Bit 23:16 reg_3dnr_nr3_suremot_dec_cofst // unsigned , default = 38 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+//Bit 15: 8 reg_3dnr_nr3_suremot_frc_cgain // unsigned , default = 64 (norm 8)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+//Bit 7: 0 reg_3dnr_nr3_suremot_frc_cofst // unsigned , default = 20 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: nr3_tnr_regs.h
+//
+#define LBUF_TOP_CTRL ((0x2fff << 2) + 0xff000000)
+//bit 23:22 mode_444c422
+//bit 21:20 mode_422c444
+//bit 17 lbuf_fmt444_mode
+//bit 16 lbuf_line5_mode
+//bit 12:0 pre_lbuf_size
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: mcdi_regs.h
+//
+// VPU_VLOCK register (16'h3000 - 16'h30ff)
+//========================================================================
+//
+// Reading file: vpu_vlock_reg.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// ----------------------------
+// VPU_VLOCK 0x30
+// ----------------------------
+// -----------------------------------------------
+// REG_BASE: VPU_VLOCK_VCBUS_BASE = 0x30
+// -----------------------------------------------
+#define VPU_VLOCK_CTRL ((0x3000 << 2) + 0xff000000)
+#define VPU_VLOCK_MISC_CTRL ((0x3001 << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP0_ACCUM_LMT ((0x3002 << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP0_CTRL0 ((0x3003 << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP1_CTRL0 ((0x3004 << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP1_IMISSYNC_MAX ((0x3005 << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP1_IMISSYNC_MIN ((0x3006 << 2) + 0xff000000)
+#define VPU_VLOCK_OVWRITE_ACCUM0 ((0x3007 << 2) + 0xff000000)
+#define VPU_VLOCK_OVWRITE_ACCUM1 ((0x3008 << 2) + 0xff000000)
+#define VPU_VLOCK_OUTPUT0_CAPT_LMT ((0x3009 << 2) + 0xff000000)
+#define VPU_VLOCK_OUTPUT0_PLL_LMT ((0x300a << 2) + 0xff000000)
+#define VPU_VLOCK_OUTPUT1_CAPT_LMT ((0x300b << 2) + 0xff000000)
+#define VPU_VLOCK_OUTPUT1_PLL_LMT ((0x300c << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP1_PHSDIF_TGT ((0x300d << 2) + 0xff000000)
+#define VPU_VLOCK_RO_LOOP0_ACCUM ((0x300e << 2) + 0xff000000)
+#define VPU_VLOCK_RO_LOOP1_ACCUM ((0x300f << 2) + 0xff000000)
+#define VPU_VLOCK_OROW_OCOL_MAX ((0x3010 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_VS_I_DIST ((0x3011 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_VS_O_DIST ((0x3012 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_LINE_PIX_ADJ ((0x3013 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_OUTPUT_00_01 ((0x3014 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_OUTPUT_10_11 ((0x3015 << 2) + 0xff000000)
+#define VPU_VLOCK_MX4096 ((0x3016 << 2) + 0xff000000)
+#define VPU_VLOCK_STBDET_WIN0_WIN1 ((0x3017 << 2) + 0xff000000)
+#define VPU_VLOCK_STBDET_CLP ((0x3018 << 2) + 0xff000000)
+#define VPU_VLOCK_STBDET_ABS_WIN0 ((0x3019 << 2) + 0xff000000)
+#define VPU_VLOCK_STBDET_ABS_WIN1 ((0x301a << 2) + 0xff000000)
+#define VPU_VLOCK_STBDET_SGN_WIN0 ((0x301b << 2) + 0xff000000)
+#define VPU_VLOCK_STBDET_SGN_WIN1 ((0x301c << 2) + 0xff000000)
+#define VPU_VLOCK_ADJ_EN_SYNC_CTRL ((0x301d << 2) + 0xff000000)
+#define VPU_VLOCK_GCLK_EN ((0x301e << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP1_ACCUM_LMT ((0x301f << 2) + 0xff000000)
+#define VPU_VLOCK_RO_M_INT_FRAC ((0x3020 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_PH_DIS ((0x3021 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_PH_ERR ((0x3022 << 2) + 0xff000000)
+#define VPU_VLOCK_LOCK_TH ((0x3023 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_LCK_FRM ((0x3024 << 2) + 0xff000000)
+#define VPU_VLOCK_WIN0_TH ((0x3025 << 2) + 0xff000000)
+#define VPU_VLOCK_WIN0_RATIO ((0x3026 << 2) + 0xff000000)
+#define VPU_VLOCK_WIN0_FILTER_CNTL ((0x3027 << 2) + 0xff000000)
+#define VPU_VLOCK_WIN1_TH ((0x3028 << 2) + 0xff000000)
+#define VPU_VLOCK_WIN1_RATIO ((0x3029 << 2) + 0xff000000)
+#define VPU_VLOCK_WIN1_FILTER_CNTL ((0x302a << 2) + 0xff000000)
+#define VPU_VLOCK_LOCK_TH1 ((0x302b << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP0_ERR_LMT ((0x302c << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP1_ERR_LMT ((0x302d << 2) + 0xff000000)
+#define VPU_VLOCK_ERR_CTRL0 ((0x302e << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_vlock_reg.h
+//
+//
+// Reading file: vpp_partb_reg.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: VPPB_VCBUS_BASE = 0x31
+// -----------------------------------------------
+////=================================================================////
+//// vkeystone
+////=================================================================////
+// 8'h00-8'h17
+//
+// Reading file: vkstone_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VKS_CTRL ((0x3100 << 2) + 0xff000000)
+//Bit 31 reg_vks_en // unsigned , default = 1 enable signal of the vks function
+//Bit 30 reg_vks_scl_mode0 // unsigned , default = 1 : b0 mode of vks ofset mode, 0: offset= offset; 1: offset= offset*step= ofset/scale;
+//Bit 29 reg_vks_scl_mode1 // unsigned , default = 1 : b0 mode of vks ofset mode, 0: offset= offset; 1: offset= offset*step= ofset/scale;
+//Bit 28 reg_vks_fill_mode // unsigned , default = 1 mode of out-of-boundary fill, 0 extension, 1: fill with the fill_value
+//Bit 27:26 reg_vks_row_inp_mode // unsigned , default = 1 , interpolation mode from 16pieces ofset/step to each line ofset and step; 0: linear interpolation; 1: cubic interpolation (using ccoef)
+//Bit 25 reg_vks_border_ext_mode0 // unsigned , default = 0 , extend mode of the border data of luma and chroma, 0: copy the most border one; 1: extropolate the border one
+//Bit 24 reg_vks_border_ext_mode1 // unsigned , default = 0 , extend mode of the border data of luma and chroma, 0: copy the most border one; 1: extropolate the border one
+//Bit 23 reg_vks_obuf_mode0 // unsigned , default = 1 , mode of output buffer left/right side. 0: no precalculate active pixels during output fill region; 1: precaclc active pixels during output fill regions
+//Bit 22 reg_vks_obuf_mode1 // unsigned , default = 1 , mode of output buffer left/right side. 0: no precalculate active pixels during output fill region; 1: precaclc active pixels during output fill regions
+//Bit 21:20 reg_vks_obuf_mrgn0 // unsigned , default = 3 , margin pixels for left right most active pixel to the fill pixels to avoid jump
+//Bit 19:18 reg_vks_obuf_mrgn1 // unsigned , default = 3 , margin pixels for left right most active pixel to the fill pixels to avoid jump
+//Bit 17:16 reg_vks_phs_qmode // unsigned , default = 2 , interpolation mode of the phase, 0: floor to 1/64 phase; 1: round to 1/64 phase; 2/3 linear intp
+//Bit 15: 0 reg_vks_row_scl // unsigned , default = 11651 , scale of row to make it fit to the 16 pieces, scl = (2^23)/RowMax
+#define VKS_OUT_WIN_SIZE ((0x3101 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_vks_ocolmax // unsigned , default = 1280 output outer window col number, decided by the projector
+//Bit 15:14 reserved
+//Bit 13: 0 reg_vks_orowmax // unsigned , default = 720 output outer window row number, decided by the projector
+#define VKS_PRELPF_YCOEF0 ((0x3102 << 2) + 0xff000000)
+//Bit 31:24 reg_vks_prelpf_ycoef0 // signed , default = -128 coef of horizontal luma prelpf for Keystone, normalized 128 as '1'
+//Bit 23:16 reg_vks_prelpf_ycoef1 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1'
+//Bit 15: 8 reg_vks_prelpf_ycoef2 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1'
+//Bit 7: 0 reg_vks_prelpf_ycoef3 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1'
+#define VKS_PRELPF_YCOEF1 ((0x3103 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_vks_prelpf_ycoef4 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1'
+//Bit 7: 0 reg_vks_prelpf_ycoef5 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1'
+#define VKS_PRELPF_CCOEF0 ((0x3104 << 2) + 0xff000000)
+//Bit 31:24 reg_vks_prelpf_ccoef0 // signed , default = -128 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1'
+//Bit 23:16 reg_vks_prelpf_ccoef1 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1'
+//Bit 15: 8 reg_vks_prelpf_ccoef2 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1'
+//Bit 7: 0 reg_vks_prelpf_ccoef3 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1'
+#define VKS_PRELPF_CCOEF1 ((0x3105 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_vks_prelpf_ccoef4 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1'
+//Bit 7: 0 reg_vks_prelpf_ccoef5 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1'
+#define VKS_FILL_VAL ((0x3106 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_vks_fill_value0 // unsigned , default = 0 , border fill color define. yuv: [0 128 128]; rgb:[0 0 0]
+//Bit 15: 8 reg_vks_fill_value1 // unsigned , default = 128 , border fill color define. yuv: [0 128 128]; rgb:[0 0 0]
+//Bit 7: 0 reg_vks_fill_value2 // unsigned , default = 128 , border fill color define. yuv: [0 128 128]; rgb:[0 0 0]
+#define VKS_IWIN_HSIZE ((0x3107 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_vks_iwinx0 // unsigned , default = 160 , input start-col and end-col;
+//Bit 15:14 reserved
+//Bit 13: 0 reg_vks_iwinx1 // unsigned , default = 1279 , input start-col and end-col;
+#define VKS_IWIN_VSIZE ((0x3108 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_vks_iwiny0 // unsigned , default = 0 , input start-row and end-row;
+//Bit 15:14 reserved
+//Bit 13: 0 reg_vks_iwiny1 // unsigned , default = 719 , input start-row and end-row;
+#define VKS_TOP_MISC ((0x3109 << 2) + 0xff000000)
+//Bit 31:19 reserved
+//Bit 18 reg_flt_en // unsigned , default = 1
+//Bit 17 reg_frm_rst // unsigned , default = 0
+//Bit 16 reg_ctrl_sync // unsigned , default = 0
+//Bit 15: 8 blank_num // unsigned , default = 4
+//Bit 7: 0 flt_blank_num // unsigned , default = 9
+#define VKS_START_CTRL ((0x310a << 2) + 0xff000000)
+//Bit 31:17 reserved
+//Bit 16 reg_vks_en_mode // unsigned , default = 0
+//Bit 15: 0 reg_hold_phnum // unsigned , default = 5
+#define VKS_LBUF_SIZE ((0x310b << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11: 0 reg_lbuf_depth // unsigned , default = 1024
+#define VKS_PARA_ADDR_PORT ((0x310e << 2) + 0xff000000)
+#define VKS_PARA_DATA_PORT ((0x310f << 2) + 0xff000000)
+
+ #define VKS_SCL_OFSET00 0x9 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset0 // unsigned , default = 118534 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET01 0xa //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset1 // unsigned , default = 111450 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET02 0xb //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset2 // unsigned , default = 104366 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET03 0xc //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset3 // unsigned , default = 97283 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET04 0xd //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset4 // unsigned , default = 90199 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET05 0xe //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset5 // unsigned , default = 83115 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET06 0xf //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset6 // unsigned , default = 76031 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET07 0x10 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset7 // unsigned , default = 68947 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET08 0x11 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset8 // unsigned , default = 61864 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET09 0x12 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset9 // unsigned , default = 54780 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET10 0x13 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset10 // unsigned , default = 47696 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET11 0x14 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset11 // unsigned , default = 40612 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET12 0x15 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset12 // unsigned , default = 33528 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET13 0x16 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset13 // unsigned , default = 26444 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET14 0x17 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset14 // unsigned , default = 19361 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET15 0x18 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset15 // unsigned , default = 12277 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET16 0x19 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset16 // unsigned , default = 5193 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_STEP00 0x1a //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step0 // unsigned , default = 331378 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP01 0x1b //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step1 // unsigned , default = 383191 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP02 0x1c //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step2 // unsigned , default = 435004 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP03 0x1d //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step3 // unsigned , default = 486818 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP04 0x1e //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step4 // unsigned , default = 538631 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP05 0x1f //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step5 // unsigned , default = 590444 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP06 0x20 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step6 // unsigned , default = 642257 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP07 0x21 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step7 // unsigned , default = 694070 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP08 0x22 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step8 // unsigned , default = 745884 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP09 0x23 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step9 // unsigned , default = 797697 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP10 0x24 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step10 // unsigned , default = 849510 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP11 0x25 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step11 // unsigned , default = 901323 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP12 0x26 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step12 // unsigned , default = 953136 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP13 0x27 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step13 // unsigned , default = 1004949 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP14 0x28 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step14 // unsigned , default = 1056763 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP15 0x29 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step15 // unsigned , default = 1108576 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP16 0x2a //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step16 // unsigned , default = 1160389 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_PPS_YCOEF00 0x2b //
+//Bit 31:24 reg_vks_ycoef0 // signed , default = 0 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef1 // signed , default = 128 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef2 // signed , default = 0 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef3 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF01 0x2c //
+//Bit 31:24 reg_vks_ycoef4 // signed , default = 0 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef5 // signed , default = 127 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef6 // signed , default = 1 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef7 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF02 0x2d //
+//Bit 31:24 reg_vks_ycoef8 // signed , default = -1 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef9 // signed , default = 127 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef10 // signed , default = 2 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef11 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF03 0x2e //
+//Bit 31:24 reg_vks_ycoef12 // signed , default = -2 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef13 // signed , default = 127 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef14 // signed , default = 3 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef15 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF04 0x2f //
+//Bit 31:24 reg_vks_ycoef16 // signed , default = -3 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef17 // signed , default = 126 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef18 // signed , default = 5 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef19 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF05 0x30 //
+//Bit 31:24 reg_vks_ycoef20 // signed , default = -4 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef21 // signed , default = 126 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef22 // signed , default = 6 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef23 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF06 0x31 //
+//Bit 31:24 reg_vks_ycoef24 // signed , default = -5 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef25 // signed , default = 125 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef26 // signed , default = 8 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef27 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF07 0x32 //
+//Bit 31:24 reg_vks_ycoef28 // signed , default = -5 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef29 // signed , default = 124 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef30 // signed , default = 9 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef31 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF08 0x33 //
+//Bit 31:24 reg_vks_ycoef32 // signed , default = -6 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef33 // signed , default = 123 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef34 // signed , default = 11 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef35 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF09 0x34 //
+//Bit 31:24 reg_vks_ycoef36 // signed , default = -6 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef37 // signed , default = 122 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef38 // signed , default = 13 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef39 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF10 0x35 //
+//Bit 31:24 reg_vks_ycoef40 // signed , default = -7 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef41 // signed , default = 121 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef42 // signed , default = 15 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef43 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF11 0x36 //
+//Bit 31:24 reg_vks_ycoef44 // signed , default = -7 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef45 // signed , default = 119 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef46 // signed , default = 17 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef47 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF12 0x37 //
+//Bit 31:24 reg_vks_ycoef48 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef49 // signed , default = 118 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef50 // signed , default = 19 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef51 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF13 0x38 //
+//Bit 31:24 reg_vks_ycoef52 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef53 // signed , default = 116 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef54 // signed , default = 22 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef55 // signed , default = -2 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF14 0x39 //
+//Bit 31:24 reg_vks_ycoef56 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef57 // signed , default = 114 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef58 // signed , default = 24 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef59 // signed , default = -2 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF15 0x3a //
+//Bit 31:24 reg_vks_ycoef60 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef61 // signed , default = 112 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef62 // signed , default = 26 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef63 // signed , default = -2 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF16 0x3b //
+//Bit 31:24 reg_vks_ycoef64 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef65 // signed , default = 111 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef66 // signed , default = 29 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef67 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF17 0x3c //
+//Bit 31:24 reg_vks_ycoef68 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef69 // signed , default = 109 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef70 // signed , default = 31 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef71 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF18 0x3d //
+//Bit 31:24 reg_vks_ycoef72 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef73 // signed , default = 107 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef74 // signed , default = 33 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef75 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF19 0x3e //
+//Bit 31:24 reg_vks_ycoef76 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef77 // signed , default = 104 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef78 // signed , default = 36 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef79 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF20 0x3f //
+//Bit 31:24 reg_vks_ycoef80 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef81 // signed , default = 102 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef82 // signed , default = 39 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef83 // signed , default = -4 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF21 0x40 //
+//Bit 31:24 reg_vks_ycoef84 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef85 // signed , default = 100 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef86 // signed , default = 41 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef87 // signed , default = -4 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF22 0x41 //
+//Bit 31:24 reg_vks_ycoef88 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef89 // signed , default = 97 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef90 // signed , default = 44 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef91 // signed , default = -4 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF23 0x42 //
+//Bit 31:24 reg_vks_ycoef92 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef93 // signed , default = 95 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef94 // signed , default = 47 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef95 // signed , default = -5 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF24 0x43 //
+//Bit 31:24 reg_vks_ycoef96 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef97 // signed , default = 93 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef98 // signed , default = 49 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef99 // signed , default = -5 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF25 0x44 //
+//Bit 31:24 reg_vks_ycoef100 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef101 // signed , default = 90 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef102 // signed , default = 52 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef103 // signed , default = -5 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF26 0x45 //
+//Bit 31:24 reg_vks_ycoef104 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef105 // signed , default = 88 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef106 // signed , default = 55 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef107 // signed , default = -6 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF27 0x46 //
+//Bit 31:24 reg_vks_ycoef108 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef109 // signed , default = 85 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef110 // signed , default = 58 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef111 // signed , default = -6 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF28 0x47 //
+//Bit 31:24 reg_vks_ycoef112 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef113 // signed , default = 82 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef114 // signed , default = 60 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef115 // signed , default = -6 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF29 0x48 //
+//Bit 31:24 reg_vks_ycoef116 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef117 // signed , default = 80 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef118 // signed , default = 63 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef119 // signed , default = -7 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF30 0x49 //
+//Bit 31:24 reg_vks_ycoef120 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef121 // signed , default = 77 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef122 // signed , default = 66 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef123 // signed , default = -7 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF31 0x4a //
+//Bit 31:24 reg_vks_ycoef124 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef125 // signed , default = 74 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef126 // signed , default = 69 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef127 // signed , default = -7 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF32 0x4b //
+//Bit 31:24 reg_vks_ycoef128 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef129 // signed , default = 72 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef130 // signed , default = 72 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef131 // signed , default = -8 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF00 0x4c //
+//Bit 31:24 reg_vks_ccoef0 // signed , default = 0 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef1 // signed , default = 128 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef2 // signed , default = 0 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef3 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF01 0x4d //
+//Bit 31:24 reg_vks_ccoef4 // signed , default = 0 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef5 // signed , default = 127 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef6 // signed , default = 1 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef7 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF02 0x4e //
+//Bit 31:24 reg_vks_ccoef8 // signed , default = -1 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef9 // signed , default = 127 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef10 // signed , default = 2 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef11 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF03 0x4f //
+//Bit 31:24 reg_vks_ccoef12 // signed , default = -2 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef13 // signed , default = 127 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef14 // signed , default = 3 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef15 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF04 0x50 //
+//Bit 31:24 reg_vks_ccoef16 // signed , default = -3 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef17 // signed , default = 126 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef18 // signed , default = 5 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef19 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF05 0x51 //
+//Bit 31:24 reg_vks_ccoef20 // signed , default = -4 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef21 // signed , default = 126 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef22 // signed , default = 6 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef23 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF06 0x52 //
+//Bit 31:24 reg_vks_ccoef24 // signed , default = -5 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef25 // signed , default = 125 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef26 // signed , default = 8 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef27 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF07 0x53 //
+//Bit 31:24 reg_vks_ccoef28 // signed , default = -5 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef29 // signed , default = 124 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef30 // signed , default = 9 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef31 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF08 0x54 //
+//Bit 31:24 reg_vks_ccoef32 // signed , default = -6 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef33 // signed , default = 123 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef34 // signed , default = 11 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef35 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF09 0x55 //
+//Bit 31:24 reg_vks_ccoef36 // signed , default = -6 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef37 // signed , default = 122 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef38 // signed , default = 13 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef39 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF10 0x56 //
+//Bit 31:24 reg_vks_ccoef40 // signed , default = -7 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef41 // signed , default = 121 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef42 // signed , default = 15 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef43 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF11 0x57 //
+//Bit 31:24 reg_vks_ccoef44 // signed , default = -7 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef45 // signed , default = 119 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef46 // signed , default = 17 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef47 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF12 0x58 //
+//Bit 31:24 reg_vks_ccoef48 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef49 // signed , default = 118 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef50 // signed , default = 19 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef51 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF13 0x59 //
+//Bit 31:24 reg_vks_ccoef52 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef53 // signed , default = 116 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef54 // signed , default = 22 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef55 // signed , default = -2 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF14 0x5a //
+//Bit 31:24 reg_vks_ccoef56 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef57 // signed , default = 114 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef58 // signed , default = 24 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef59 // signed , default = -2 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF15 0x5b //
+//Bit 31:24 reg_vks_ccoef60 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef61 // signed , default = 112 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef62 // signed , default = 26 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef63 // signed , default = -2 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF16 0x5c //
+//Bit 31:24 reg_vks_ccoef64 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef65 // signed , default = 111 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef66 // signed , default = 29 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef67 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF17 0x5d //
+//Bit 31:24 reg_vks_ccoef68 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef69 // signed , default = 109 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef70 // signed , default = 31 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef71 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF18 0x5e //
+//Bit 31:24 reg_vks_ccoef72 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef73 // signed , default = 107 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef74 // signed , default = 33 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef75 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF19 0x5f //
+//Bit 31:24 reg_vks_ccoef76 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef77 // signed , default = 104 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef78 // signed , default = 36 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef79 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF20 0x60 //
+//Bit 31:24 reg_vks_ccoef80 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef81 // signed , default = 102 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef82 // signed , default = 39 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef83 // signed , default = -4 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF21 0x61 //
+//Bit 31:24 reg_vks_ccoef84 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef85 // signed , default = 100 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef86 // signed , default = 41 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef87 // signed , default = -4 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF22 0x62 //
+//Bit 31:24 reg_vks_ccoef88 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef89 // signed , default = 97 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef90 // signed , default = 44 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef91 // signed , default = -4 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF23 0x63 //
+//Bit 31:24 reg_vks_ccoef92 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef93 // signed , default = 95 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef94 // signed , default = 47 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef95 // signed , default = -5 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF24 0x64 //
+//Bit 31:24 reg_vks_ccoef96 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef97 // signed , default = 93 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef98 // signed , default = 49 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef99 // signed , default = -5 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF25 0x65 //
+//Bit 31:24 reg_vks_ccoef100 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef101 // signed , default = 90 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef102 // signed , default = 52 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef103 // signed , default = -5 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF26 0x66 //
+//Bit 31:24 reg_vks_ccoef104 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef105 // signed , default = 88 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef106 // signed , default = 55 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef107 // signed , default = -6 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF27 0x67 //
+//Bit 31:24 reg_vks_ccoef108 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef109 // signed , default = 85 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef110 // signed , default = 58 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef111 // signed , default = -6 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF28 0x68 //
+//Bit 31:24 reg_vks_ccoef112 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef113 // signed , default = 82 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef114 // signed , default = 60 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef115 // signed , default = -6 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF29 0x69 //
+//Bit 31:24 reg_vks_ccoef116 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef117 // signed , default = 80 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef118 // signed , default = 63 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef119 // signed , default = -7 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF30 0x6a //
+//Bit 31:24 reg_vks_ccoef120 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef121 // signed , default = 77 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef122 // signed , default = 66 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef123 // signed , default = -7 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF31 0x6b //
+//Bit 31:24 reg_vks_ccoef124 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef125 // signed , default = 74 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef126 // signed , default = 69 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef127 // signed , default = -7 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF32 0x6c //
+//Bit 31:24 reg_vks_ccoef128 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef129 // signed , default = 72 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef130 // signed , default = 72 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef131 // signed , default = -8 poly-phase scalar coefs
+
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vkstone_regs.h
+//
+////=================================================================////
+//// vpp dither
+////=================================================================////
+// 8'h20-8'h3f
+//
+// Reading file: vpp_dither_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VPP_VE_DITHER_CTRL ((0x3120 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_1 ((0x3121 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_2 ((0x3122 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_3 ((0x3123 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_4 ((0x3124 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_5 ((0x3125 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_6 ((0x3126 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_7 ((0x3127 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_8 ((0x3128 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_9 ((0x3129 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_10 ((0x312a << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_11 ((0x312b << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_12 ((0x312c << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_CTRL ((0x3130 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_1 ((0x3131 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_2 ((0x3132 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_3 ((0x3133 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_4 ((0x3134 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_5 ((0x3135 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_6 ((0x3136 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_7 ((0x3137 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_8 ((0x3138 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_9 ((0x3139 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_10 ((0x313a << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_11 ((0x313b << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_12 ((0x313c << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_13 ((0x313d << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_14 ((0x313e << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_15 ((0x313f << 2) + 0xff000000)
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_dither_regs.h
+//
+// 8'h40-8'h4f
+//
+// Reading file: osdsc_deband_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define OSD_DB_FLT_CTRL ((0x3140 << 2) + 0xff000000)
+//Bit 31:27 reserved
+//Bit 26 reg_nrdeband_reset1 // unsigned , default = 1 , 0 : no reload chrm seed 1: reload chrm seed
+//Bit 25 reg_nrdeband_reset0 // unsigned , default = 1 , 0 : no reload luma seed 1: reload luma seed
+//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 , 0 : yuv 1: RGB
+//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
+//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
+//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
+//Bit 16 reserved
+//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
+//Bit 12 reserved
+//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6
+//Bit 8 reserved
+//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 , debanding random hp portion xor, [0] for luma
+//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 , debanding random hp portion xor, [1] for chroma
+//Bit 5 reg_nrdeband_en1 // unsigned , default = 0 , debanding registers, for luma
+//Bit 4 reg_nrdeband_en0 // unsigned , default = 0 , debanding registers, for chroma
+//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+#define OSD_DB_FLT_CTRL1 ((0x3141 << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:16 reg_nrdeband_noise_rs // unsigned , default = 2
+//Bit 15:12 reg_nrdeband_randgain // unsigned , default = 8
+//Bit 11 reserved
+//Bit 10: 8 reg_nrdeband_bandrand5 // unsigned , default = 6
+//Bit 7 reserved
+//Bit 6: 4 reg_nrdeband_bandrand4 // unsigned , default = 6
+//Bit 3 reserved
+//Bit 2: 0 reg_nrdeband_bandrand3 // unsigned , default = 6
+#define OSD_DB_FLT_LUMA_THRD ((0x3142 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_luma_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_luma_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_luma_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_luma_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else
+#define OSD_DB_FLT_CHRM_THRD ((0x3143 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_chrm_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_chrm_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_chrm_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_chrm_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif
+#define OSD_DB_FLT_RANDLUT ((0x3144 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:21 reg_nrdeband_randslut7 // unsigned , default = 1 rand lut7
+//Bit 20:18 reg_nrdeband_randslut6 // unsigned , default = 1 rand lut6
+//Bit 17:15 reg_nrdeband_randslut5 // unsigned , default = 1 rand lut5
+//Bit 14:12 reg_nrdeband_randslut4 // unsigned , default = 1 rand lut4
+//Bit 11: 9 reg_nrdeband_randslut3 // unsigned , default = 1 rand lut3
+//Bit 8: 6 reg_nrdeband_randslut2 // unsigned , default = 1 rand lut2
+//Bit 5: 3 reg_nrdeband_randslut1 // unsigned , default = 1 rand lut1
+//Bit 2: 0 reg_nrdeband_randslut0 // unsigned , default = 1 rand lut0
+#define OSD_DB_FLT_PXI_THRD ((0x3145 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+//Bit 15:10 reserved
+//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+#define OSD_DB_FLT_SEED_Y ((0x3146 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 ,debanding noise adding seed for Y. seed[0]= 0x60a52f20; as default
+#define OSD_DB_FLT_SEED_U ((0x3147 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 ,debanding noise adding seed for U. seed[0]= 0x60a52f27; as default
+#define OSD_DB_FLT_SEED_V ((0x3148 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD_DB_FLT_SEED3 ((0x3149 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed3 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD_DB_FLT_SEED4 ((0x314a << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed4 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD_DB_FLT_SEED5 ((0x314b << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed5 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: osdsc_deband_regs.h
+//
+//register definition for xvycc
+// 8'h50-8'h7f
+//
+// Reading file: xvycc_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define XVYCC_INV_LUT_Y_ADDR_PORT ((0x3158 << 2) + 0xff000000)
+//Bit 31:7, reserved
+//Bit 6:0, xvycc_inv_lut_y_addr;
+#define XVYCC_INV_LUT_Y_DATA_PORT ((0x3159 << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, xvycc_inv_lut_y_data;
+#define XVYCC_INV_LUT_U_ADDR_PORT ((0x315a << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, xvycc_inv_lut_u_addr;
+#define XVYCC_INV_LUT_U_DATA_PORT ((0x315b << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, xvycc_inv_lut_u_data;
+#define XVYCC_INV_LUT_V_ADDR_PORT ((0x315c << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, xvycc_inv_lut_v_addr;
+#define XVYCC_INV_LUT_V_DATA_PORT ((0x315d << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, xvycc_inv_lut_v_data;
+#define XVYCC_LUT_R_ADDR_PORT ((0x315e << 2) + 0xff000000)
+//Bit 31:7, reserved
+//Bit 6:0, xvycc_lut_r_addr;
+#define XVYCC_LUT_R_DATA_PORT ((0x315f << 2) + 0xff000000)
+//Bit 31:10, reserved
+//Bit 9:0, xvycc_lut_r_data;
+#define XVYCC_LUT_G_ADDR_PORT ((0x3160 << 2) + 0xff000000)
+//Bit 31:7, reserved
+//Bit 6:0, xvycc_lut_g_addr;
+#define XVYCC_LUT_G_DATA_PORT ((0x3161 << 2) + 0xff000000)
+//Bit 31:10, reserved
+//Bit 9:0, xvycc_lut_g_data;
+#define XVYCC_LUT_B_ADDR_PORT ((0x3162 << 2) + 0xff000000)
+//Bit 31:7, reserved
+//Bit 6:0, xvycc_lut_b_addr;
+#define XVYCC_LUT_B_DATA_PORT ((0x3163 << 2) + 0xff000000)
+//Bit 31:10, reserved
+//Bit 9:0, xvycc_lut_b_data;
+#define XVYCC_INV_LUT_CTL ((0x3164 << 2) + 0xff000000)
+//Bit 31:15, reserved
+//Bit 14:12, reg_xvycc_cmpr_invlut_enable enable for xvycc compression inverse-lut [2] for Y, [1] for U, [0] for V default=0
+//Bit 11:10, reg_xvycc_cmpr_invlut_vscl_1 v LUT input scale for positive portion default=0
+//Bit 9: 8, reg_xvycc_cmpr_invlut_vscl_0 v LUT input scale for negative portion default=0
+//Bit 7: 6, reg_xvycc_cmpr_invlut_uscl_1 u LUT input scale for positive portion default=0
+//Bit 5: 4, reg_xvycc_cmpr_invlut_uscl_0 u LUT input scale for negative portion default=0
+//Bit 3: 2, reg_xvycc_cmpr_invlut_yscl_1 y LUT input scale for positive portion default=0
+//Bit 1: 0, reg_xvycc_cmpr_invlut_yscl_0 y LUT input scale for negative portion default=0
+#define XVYCC_LUT_CTL ((0x3165 << 2) + 0xff000000)
+//Bit 31: 7, reserved
+//Bit 6: 4, reg_xvycc_lut_enable LUT enable [6] for R, [5] for G, [4] for B default=0
+//Bit 3: 2, reg_xvycc_lut_scl_1 LUT input scale for positive portion default=0
+//Bit 1: 0, reg_xvycc_lut_scl_0 LUT input scale for negative portion default=0
+#define XVYCC_VADJ1_CURV_0 ((0x3166 << 2) + 0xff000000)
+//Bit 31:24, vadj1_softcon_curv0_ci default=0
+//Bit 23:12, vadj1_softcon_curv0_b default=0
+//Bit 11: 0, vadj1_softcon_curv0_a default=0
+#define XVYCC_VADJ1_CURV_1 ((0x3167 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12: 4, vadj1_softcon_curv0_g default=0
+//Bit 3, reserved
+//Bit 2: 0, vadj1_softcon_curv0_cs default=0
+#define XVYCC_VADJ1_CURV_2 ((0x3168 << 2) + 0xff000000)
+//Bit 31:24, vadj1_softcon_curv1_ci default=0
+//Bit 23:12, vadj1_softcon_curv1_b default=0
+//Bit 11: 0, vadj1_softcon_curv1_a default=0
+#define XVYCC_VADJ1_CURV_3 ((0x3169 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12: 4, vadj1_softcon_curv1_g default=0
+//Bit 3, reserved
+//Bit 2: 0, vadj1_softcon_curv1_cs default=0
+#define XVYCC_VADJ2_CURV_0 ((0x316a << 2) + 0xff000000)
+//Bit 31:24, vadj2_softcon_curv0_ci default=0
+//Bit 23:12, vadj2_softcon_curv0_b default=0
+//Bit 11: 0, vadj2_softcon_curv0_a default=0
+#define XVYCC_VADJ2_CURV_1 ((0x316b << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12: 4, vadj2_softcon_curv0_g default=0
+//Bit 3, reserved
+//Bit 2: 0, vadj2_softcon_curv0_cs default=0
+#define XVYCC_VADJ2_CURV_2 ((0x316c << 2) + 0xff000000)
+//Bit 31:24, vadj2_softcon_curv1_ci default=0
+//Bit 23:12, vadj2_softcon_curv1_b default=0
+//Bit 11: 0, vadj2_softcon_curv1_a default=0
+#define XVYCC_VADJ2_CURV_3 ((0x316d << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12: 4, vadj2_softcon_curv1_g default=0
+//Bit 3, reserved
+//Bit 2: 0, vadj2_softcon_curv1_cs default=0
+#define XVYCC_VD1_RGB_CTRST ((0x3170 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, reg_vd1_rgb_ctrst u12, contrast in rgb. default=1024
+//Bit 15:14, reserved
+//Bit 13: 4, reg_vd1_rgb_ctrst_blklvl u10, contrast blacklevel default=64
+//Bit 3: 2, reserved
+//Bit 1, reg_vd1_rgbbst_en u1, enable rgbbst default=0
+//Bit 0, reg_vd1_rgb_ctrst_prt u1, enable signal to protect saturation in rgb. default=1
+#define XVYCC_VD1_RGB_BRGHT ((0x3171 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 4, reg_vd1_rgb_brght s12, brightness level in rgb domain default=0
+//Bit 3: 2, reserved
+//Bit 1, reg_vd1_rgb_brght_prt u1, enalbe signal to protect saturation in rgb default=1
+//Bit 0, reg_vd1_rgbbst_dlut_x2 u1, enable signal to do x2 to the dlut cells before subtracting default=0
+#define XVYCC_VD1_RGB_DLUT_0_3 ((0x3172 << 2) + 0xff000000)
+//Bit 31:24, reg_vd1_rgbbst_dlut0 u8, default = 255
+//Bit 23:16, reg_vd1_rgbbst_dlut1 u8, default = 205
+//Bit 15: 8, reg_vd1_rgbbst_dlut2 u8, default = 171
+//Bit 7: 0, reg_vd1_rgbbst_dlut3 u8, default = 147
+#define XVYCC_VD1_RGB_DLUT_4_7 ((0x3173 << 2) + 0xff000000)
+//Bit 31:24, reg_vd1_rgbbst_dlut4 u8, default = 128
+//Bit 23:16, reg_vd1_rgbbst_dlut5 u8, default = 113
+//Bit 15: 8, reg_vd1_rgbbst_dlut6 u8, default = 102
+//Bit 7: 0, reg_vd1_rgbbst_dlut7 u8, default = 93
+#define XVYCC_VD1_RGB_DLUT_8_11 ((0x3174 << 2) + 0xff000000)
+//Bit 31:24, reg_vd1_rgbbst_dlut8 u8, default = 85
+//Bit 23:16, reg_vd1_rgbbst_dlut9 u8, default = 78
+//Bit 15: 8, reg_vd1_rgbbst_dlut10 u8, default = 73
+//Bit 7: 0, reg_vd1_rgbbst_dlut11 u8, default = 68
+#define XVYCC_POST_RGB_CTRST ((0x3175 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, reg_post_rgb_ctrst u12, contrast in rgb. default=1024
+//Bit 15:14, reserved
+//Bit 13: 4, reg_post_rgb_ctrst_blklvl u10, contrast blacklevel default=64
+//Bit 3: 2, reserved
+//Bit 1, reg_post_rgbbst_en u1, enable rgbbst default=0
+//Bit 0, reg_post_rgb_ctrst_prt u1, enable signal to protect saturation in rgb. default=1
+#define XVYCC_POST_RGB_BRGHT ((0x3176 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 4, reg_post_rgb_brght s12, brightness level in rgb domain default=0
+//Bit 3: 2, reserved
+//Bit 1, reg_post_rgb_brght_prt u1, enalbe signal to protect saturation in rgb default=1
+//Bit 0, reg_post_rgbbst_dlut_x2 u1, enable signal to do x2 to the dlut cells before subtracting default=0
+#define XVYCC_POST_RGB_DLUT_0_3 ((0x3177 << 2) + 0xff000000)
+//Bit 31:24, reg_post_rgbbst_dlut0 u8, default = 255
+//Bit 23:16, reg_post_rgbbst_dlut1 u8, default = 205
+//Bit 15: 8, reg_post_rgbbst_dlut2 u8, default = 171
+//Bit 7: 0, reg_post_rgbbst_dlut3 u8, default = 147
+#define XVYCC_POST_RGB_DLUT_4_7 ((0x3178 << 2) + 0xff000000)
+//Bit 31:24, reg_post_rgbbst_dlut4 u8, default = 128
+//Bit 23:16, reg_post_rgbbst_dlut5 u8, default = 113
+//Bit 15: 8, reg_post_rgbbst_dlut6 u8, default = 102
+//Bit 7: 0, reg_post_rgbbst_dlut7 u8, default = 93
+#define XVYCC_POST_RGB_DLUT_8_11 ((0x3179 << 2) + 0xff000000)
+//Bit 31:24, reg_post_rgbbst_dlut8 u8, default = 85
+//Bit 23:16, reg_post_rgbbst_dlut9 u8, default = 78
+//Bit 15: 8, reg_post_rgbbst_dlut10 u8, default = 73
+//Bit 7: 0, reg_post_rgbbst_dlut11 u8, default = 68
+#define ADAPTIVE_SCALE_REG0 ((0x3150 << 2) + 0xff000000)
+//Bit 31, reg_adaptive_scale_enable u1, default = 1
+//Bit 27:16, reg_adpscl_ys_coef_0 u12, default = 538
+//Bit 11: 0, reg_adpscl_ys_coef_1 u12, default = 1389
+#define ADAPTIVE_SCALE_REG1 ((0x3151 << 2) + 0xff000000)
+//Bit 27:16, reg_adpscl_ys_coef_2 u12, default = 121
+//Bit 11: 0, reg_adpscl_alpha_0 u12, default = 1024
+#define ADAPTIVE_SCALE_REG2 ((0x3152 << 2) + 0xff000000)
+//Bit 27:16, reg_adpscl_alpha_1 u12, default = 1024
+//Bit 11: 0, reg_adpscl_alpha_2 u12, default = 1024
+#define ADAPTIVE_SCALE_REG3 ((0x3153 << 2) + 0xff000000)
+//Bit 31:16, reg_adpscl_beta_0 u16, default = 0
+//Bit 15: 0, reg_adpscl_beta_1 u16, default = 0
+#define ADAPTIVE_SCALE_REG4 ((0x3154 << 2) + 0xff000000)
+//Bit 31:16, reg_adpscl_beta_2 u16, default = 0
+#define ADAPTIVE_SCALE_ADDR ((0x3155 << 2) + 0xff000000)
+//Bit 6:0, reg_lut_addr u7, default = 0
+#define ADAPTIVE_SCALE_DATA ((0x3156 << 2) + 0xff000000)
+//Bit 11:0, reg_lut_data u12, default = 0
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: xvycc_regs.h
+//
+//register definition for vd2 afbc dec
+// 8'h80-8'h9f
+//
+// Reading file: vd2_afbc_dec_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+//// reg
+////===============================////
+#define VD2_AFBC_ENABLE ((0x3180 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:23, reg_gclk_ctrl_core unsigned, default = 0
+//Bit 22, reg_fmt_size_sw_mode unsigned, default = 0, 0:hw mode 1:sw mode for format size
+//Bit 21, reg_addr_link_en unsigned, default = 1, 1:enable
+//Bit 20, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb
+//Bit 19, reg_dos_uncomp_mode unsigned , default = 0
+//Bit 18:16, soft_rst unsigned , default = 4
+//Bit 15:14, reserved
+//Bit 13:12, ddr_blk_size unsigned , default = 1
+//Bit 11:9, cmd_blk_size unsigend , default = 3
+//Bit 8, dec_enable unsigned , default = 0
+//Bit 7:2, reserved
+//Bit 1, head_len_sel unsigned , default = 1
+//Bit 0, dec_frm_start unsigned , default = 0
+#define VD2_AFBC_MODE ((0x3181 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29, ddr_sz_mode uns, default = 0 , 0: fixed block ddr size 1 : unfixed block ddr size;
+//Bit 28, blk_mem_mode uns, default = 0 , 0: fixed 16x128 size; 1 : fixed 12x128 size
+//Bit 27:26, rev_mode uns, default = 0 , reverse mode
+//Bit 25:24, mif_urgent uns, default = 3 , info mif and data mif urgent
+//Bit 23, reserved
+//Bit 22:16, hold_line_num uns, default = 4 ,
+//Bit 15:14, burst_len uns, default = 2, 0: burst1 1:burst2 2:burst4
+//Bit 13:8, compbits_yuv uns, default = 0 ,
+// bit 1:0,: y component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+// bit 3:2,: u component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+// bit 5:4,: v component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+//Bit 7:6, vert_skip_y uns, default = 0 , luma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 5:4, horz_skip_y uns, default = 0 , luma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 3:2, vert_skip_uv uns, default = 0 , chroma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 1:0, horz_skip_uv uns, default = 0 , chroma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+#define VD2_AFBC_SIZE_IN ((0x3182 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hsize_in uns, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_in uns, default = 1080 , pic vert size in unit: pixel
+#define VD2_AFBC_DEC_DEF_COLOR ((0x3183 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:20, def_color_y uns, default = 255, afbc dec y default setting value
+//Bit 19:10, def_color_u uns, default = 128, afbc dec u default setting value
+//Bit 9: 0, def_color_v uns, default = 128, afbc dec v default setting value
+#define VD2_AFBC_CONV_CTRL ((0x3184 << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13:12, fmt_mode uns, default = 2, 0:yuv444 1:yuv422 2:yuv420
+//Bit 11: 0, conv_lbuf_len uns, default = 256, unit=16 pixel need to set = 2^n
+#define VD2_AFBC_LBUF_DEPTH ((0x3185 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, dec_lbuf_depth uns, default = 128; // unit= 8 pixel
+//Bit 15:12, reserved
+//Bit 11:0, mif_lbuf_depth uns, default = 128;
+#define VD2_AFBC_HEAD_BADDR ((0x3186 << 2) + 0xff000000)
+//Bit 31:0, mif_info_baddr uns, default = 32'h0;
+#define VD2_AFBC_BODY_BADDR ((0x3187 << 2) + 0xff000000)
+//Bit 31:0, mif_data_baddr uns, default = 32'h00010000;
+#define VD2_AFBC_SIZE_OUT ((0x3188 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, hsize_out uns, default = 1920 ; // unit: 1 pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_out uns, default = 1080 ; // unit: 1 pixel
+#define VD2_AFBC_OUT_YSCOPE ((0x3189 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, out_vert_bgn uns, default = 0 ; // unit: 1 pixel
+//Bit 15:13, reserved
+//Bit 12:0, out_vert_end uns, default = 1079 ; // unit: 1 pixel
+#define VD2_AFBC_STAT ((0x318a << 2) + 0xff000000)
+//Bit 31:0, ro_dbg_top_info uns
+#define VD2_AFBC_VD_CFMT_CTRL ((0x318b << 2) + 0xff000000)
+//Bit 31 cfmt_gclk_bit_dis uns, default = 0 ; // it true, disable clock, otherwise enable clock
+//Bit 30 cfmt_soft_rst_bit uns, default = 0 ; // soft rst bit
+//Bit 29 reserved
+//Bit 28 chfmt_rpt_pix uns, default = 0 ; // if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
+//Bit 27:24 chfmt_ini_phase uns, default = 0 ; // horizontal formatter initial phase
+//Bit 23 chfmt_rpt_p0_en uns, default = 0 ; // horizontal formatter repeat pixel 0 enable
+//Bit 22:21 chfmt_yc_ratio uns, default = 0 ; // horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
+//Bit 20 chfmt_en uns, default = 0 ; // horizontal formatter enable
+//Bit 19 cvfmt_phase0_always_en uns, default = 0 ; //if true, always use phase0 while vertical formater, meaning always
+// repeat data, no interpolation
+//Bit 18 cvfmt_rpt_last_dis uns, default = 0 ; //if true, disable vertical formatter chroma repeat last line
+//Bit 17 cvfmt_phase0_nrpt_en uns, default = 0 ; //veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable
+//Bit 16 cvfmt_rpt_line0_en uns, default = 0 ; //veritcal formatter repeat line 0 enable
+//Bit 15:12 cvfmt_skip_line_num uns, default = 0 ; //vertical formatter skip line num at the beginning
+//Bit 11:8 cvfmt_ini_phase uns, default = 0 ; //vertical formatter initial phase
+//Bit 7:1 cvfmt_phase_step uns, default = 0 ; //vertical formatter phase step (3.4)
+//Bit 0 cvfmt_en uns, default = 0 ; //vertical formatter enable
+#define VD2_AFBC_VD_CFMT_W ((0x318c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 chfmt_w uns, default = 0 ;horizontal formatter width
+//Bit 15:13 reserved
+//Bit 12:0 cvfmt_w uns, default = 0 ;vertical formatter width
+#define VD2_AFBC_MIF_HOR_SCOPE ((0x318d << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, mif_blk_bgn_h uns, default = 0 ; // unit: 32 pixel/block hor
+//Bit 15:10, reserved
+//Bit 9: 0, mif_blk_end_h uns, default = 59 ; // unit: 32 pixel/block hor
+#define VD2_AFBC_MIF_VER_SCOPE ((0x318e << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, mif_blk_bgn_v uns, default = 0 ; // unit: 32 pixel/block ver
+//Bit 15:12, reserved
+//Bit 11: 0, mif_blk_end_v uns, default = 269; // unit: 32 pixel/block ver
+#define VD2_AFBC_PIXEL_HOR_SCOPE ((0x318f << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, dec_pixel_bgn_h uns, default = 0 ; // unit: pixel
+//Bit 15:13, reserved
+//Bit 12: 0, dec_pixel_end_h uns, default = 1919 ; // unit: pixel
+#define VD2_AFBC_PIXEL_VER_SCOPE ((0x3190 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, dec_pixel_bgn_v uns, default = 0 ; // unit: pixel
+//Bit 15:13, reserved
+//Bit 12: 0, dec_pixel_end_v uns, default = 1079 ; // unit: pixel
+#define VD2_AFBC_VD_CFMT_H ((0x3191 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12:0 cfmt_h uns, default = 142 ; //vertical formatter height
+#define VD2_AFBCDEC_IQUANT_ENABLE ((0x3192 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_quant_expand_en_1 //unsigned, RW, enable for quantization value expansion
+//Bit 10 reg_quant_expand_en_0 //unsigned, RW, enable for quantization value expansion
+//Bit 9: 8 reg_bcleav_ofst // signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1;
+//Bit 7: 5 reserved
+//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy
+//Bit 3: 1 reserved
+//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy
+#define VD2_AFBCDEC_IQUANT_LUT_1 ((0x3193 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define VD2_AFBCDEC_IQUANT_LUT_2 ((0x3194 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define VD2_AFBCDEC_IQUANT_LUT_3 ((0x3195 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define VD2_AFBCDEC_IQUANT_LUT_4 ((0x3196 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vd2_afbc_dec_regs.h
+//
+//register definition for osd1 afbcd dec
+// 8'ha0-8'haf
+//
+// Reading file: osd1_afbcd_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+//// reg
+////===============================////
+#define OSD1_AFBCD_ENABLE ((0x31a0 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:9, id_fifo_thrd unsigned , default = 64, axi id fifo threshold
+//Bit 8, dec_enable unsigned , default = 0
+//Bit 7:1, reserved
+//Bit 0, frm_start unsigned , default = 0
+#define OSD1_AFBCD_MODE ((0x31a1 << 2) + 0xff000000)
+//Bit 31, soft_reset the use as go_field
+//Bit 30:29, reserved
+//Bit 28, axi_reorder_mode default=0, the axi reorder mode, note : don't seting
+//Bit 27:26, reserved
+//Bit 25:24, mif_urgent uns, default = 3 , info mif and data mif urgent
+//Bit 22:16, hold_line_num
+//Bit 15:8, rgba_exchan_ctrl
+//Bit 7, reserved
+//Bit 6, hreg_block_split uns, default = 1 , Enable/disable block split mode in sparse allocation
+//Bit 5, hreg_half_block uns, default = 1 , Enable/disable half block decoding. 1=half block, 0=full block
+//Bit 4:0, hreg_pixel_packing_fmt uns, default = 5 , Pixel format
+#define OSD1_AFBCD_SIZE_IN ((0x31a2 << 2) + 0xff000000)
+//Bit 31:16 hreg_hsize_in uns, default = 1920 , pic horz size in unit: pixel
+//Bit 15:0, hreg_vsize_in uns, default = 1080 , pic vert size in unit: pixel
+#define OSD1_AFBCD_HDR_PTR ((0x31a3 << 2) + 0xff000000)
+//Bit 31:0 hreg_hdr_ptr uns, default = 0 ,
+#define OSD1_AFBCD_FRAME_PTR ((0x31a4 << 2) + 0xff000000)
+//Bit 31:0 hreg_frame_ptr uns, default = 0 , The start address of the target frame buffer.
+// For YUV format, this pointer specifies the luma buffer.
+#define OSD1_AFBCD_CHROMA_PTR ((0x31a5 << 2) + 0xff000000)
+//Bit 31:0 hreg_chroma_ptr uns, default = 0 , Only valid in YUV format, to specify the target chroma buffer.
+#define OSD1_AFBCD_CONV_CTRL ((0x31a6 << 2) + 0xff000000)
+//Bit 31:15, reserved
+//Bit 15: 0, conv_lbuf_len uns, default = 1024, unit=16 pixel need to set = 2^n
+#define OSD1_AFBCD_STATUS ((0x31a8 << 2) + 0xff000000)
+//Bit 30:4, reserved
+//Bit 3, hreg_dec_resp uns, default = 0 , Decoder error flage from the dec4x4 core
+//Bit 2, hreg_axi_bresp uns, default = 0 , Bus error flag for AXI write error
+//Bit 1, hreg_axi_rresp uns, default = 0 , Bus error flag for AXI read error
+//Bit 0, hreg_idle_n uns, default = 0 , Idle output, value 0 indicates the standalone decoder is free now and can start the next frame.
+#define OSD1_AFBCD_PIXEL_HSCOPE ((0x31a9 << 2) + 0xff000000)
+//Bit 31:16, dec_pixel_bgn_h uns, default = 0 ; // unit: pixel
+//Bit 15: 0, dec_pixel_end_h uns, default = 1919 ; // unit: pixel
+#define OSD1_AFBCD_PIXEL_VSCOPE ((0x31aa << 2) + 0xff000000)
+//Bit 31:16, dec_pixel_bgn_v uns, default = 0 ; // unit: pixel
+//Bit 15: 0, dec_pixel_end_v uns, default = 1079 ; // unit: pixel
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: osd1_afbcd_regs.h
+//
+//register definition for osd1 afbcd dec
+// 8'hb0-8'hca
+//
+// Reading file: vpp_vmx_wm_regs.h
+//
+//// synopsys translate_off
+//`ifdef VPP_WM_REGS_H
+//`else
+// `define VPP_WM_REGS_H
+//// synopsys translate_on
+#define WM_CTRL ((0x31b0 << 2) + 0xff000000)
+//Bit 31, int_mask default = 0
+//Bit 30:16, reserved
+//Bit 15:8, strength_multiply default =1
+//Bit 7:6, reserved
+//Bit 5, shift_en default = 0
+//Bit 4, background_embedding_on default =0
+//Bit 3, mark_en default =0
+//Bit 2, noise_en default =0
+//Bit 1, blend_en default =0
+//Bit 0, wm_en default =0
+#define WM_SPACE_RESOLUTION ((0x31b1 << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24:16, spacing_horz default =10
+//Bit 15:9, reserved
+//Bit 8:0, spacing_vert default =12
+#define WM_SYMBOLS_NUM ((0x31b2 << 2) + 0xff000000)
+//Bit 31:8, reserved
+//Bit 7:4, symbols_cols 1~10; default =5
+//Bit 3:0, symbols_rows 1~10; default =2
+#define WM_MARK_RESOLUTION ((0x31b3 << 2) + 0xff000000)
+//Bit 31:20, mark_hsize mark_buffer_width; default =1820
+//Bit 19:8, mark_vsize mark_buffer_height; default =1820 t =780
+//Bit 7:6, reserved
+//Bit 5:0, scale default =13 // scale up
+#define WM_FREQ_DIST_LEFT ((0x31b4 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:0, freq_dist_left default =21092 // frequency_distance [n][0] each is 7bits, there is 3 dist
+#define WM_FREQ_DIST_RIGHT ((0x31b5 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:0, freq_dist_right default =21092 // frequency_distance [n][0] each is 7bits, there is 3 dist
+#define WM_FREQ_DIST_TOP ((0x31b6 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:0, freq_dist_top default =21092 // frequency_distance [n][0] each is 7bits, there is 3 dist
+#define WM_SYMBOLS_XPOS ((0x31b7 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, symbols_xpos_start default =1536 // SYMBOLS_XPOS * h_res
+//Bit 15:13, reserved
+//Bit 12:0, symbols_xpos_end default =3356 // SYMBOLS_XPOS * h_res + mark_hsize
+#define WM_SYMBOLS_YPOS ((0x31b8 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, symbols_ypos_start default =756 // SYMBOLS_yPOS * y_res
+//Bit 15:13, reserved
+//Bit 12:0, symbols_ypos_end default =1536 // SYMBOLS_yPOS * y_res + mark_vsize
+#define WM_STORAGE_SETTING ((0x31b9 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, direction_max default = 80
+//Bit 15, reserved
+//Bit 14:8, storage_s default =18 // biggest is 72 S
+//Bit 7, reserved
+//Bit 6:0, storage_max_distance default =36 // biggest is 72 max_distance
+#define WM_VIDEO_RESOLUTION ((0x31ba << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, h_res default =3840 // video hsize
+//Bit 15:13, reserved
+//Bit 12:0, v_res default =2160 // video vsize
+#define WM_EMBEDDING_STRENGTH_THRESHOLD0 ((0x31bb << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_0 default =48
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_1 default =60
+#define WM_EMBEDDING_STRENGTH_THRESHOLD1 ((0x31bc << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_2 default = 68
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_3 default = 80
+#define WM_EMBEDDING_STRENGTH_THRESHOLD2 ((0x31bd << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_4 default = 88
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_5 default = 96
+#define WM_EMBEDDING_STRENGTH_THRESHOLD3 ((0x31be << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_6 default = 100
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_7 default = 108
+#define WM_EMBEDDING_STRENGTH_THRESHOLD4 ((0x31bf << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_8 default = 112
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_9 default = 116
+#define WM_EMBEDDING_STRENGTH_THRESHOLD5 ((0x31c0 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_10 default = 120
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_11 default = 124
+#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG0 ((0x31c1 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_bg_0 default =320
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_bg_1 default = 328
+#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG1 ((0x31c2 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_bg_2 default = 332
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_bg_3 default = 340
+#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG2 ((0x31c3 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_bg_4 default = 344
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_bg_5 default = 348
+#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG3 ((0x31c4 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_bg_6 default = 352
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_bg_7 default = 356
+#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG4 ((0x31c5 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_bg_8 default = 360
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_bg_9 default = 368
+#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG5 ((0x31c6 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_bg_10 default = 372
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_bg_11 default = 380
+#define WM_AM_LUT_DATA_PORT ((0x31c7 << 2) + 0xff000000)
+#define WM_AM_LUT_ADDR_PORT ((0x31c8 << 2) + 0xff000000)
+#define WM_STATUS_RO ((0x31c9 << 2) + 0xff000000)
+//Bit 31, ro_resolution_changed
+//Bit 30:29, reserved
+//Bit 30:16, ro_hsize_in
+//Bit 15:13, reserved
+//Bit 8:0, ro_vsize_in
+#define WM_STATUS_RAM_RO ((0x31ca << 2) + 0xff000000)
+//Bit 31:9, reserved
+//Bit 8:0, ro_ram_addr
+#define WM_THRES_ADDR_PORT ((0x31cb << 2) + 0xff000000)
+#define WM_THRES_DATA_PORT ((0x31cd << 2) + 0xff000000)
+//
+// Closing file: vpp_vmx_wm_regs.h
+//
+//
+// Reading file: ngptv_reg.h
+//
+//// synopsys translate_off
+//`ifdef VPP_WM_REGS_H
+//`else
+// `define VPP_WM_REGS_H
+//// synopsys translate_on
+#define REG_NGPTV_CTRL0 ((0x31ab << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24, bypass_latch
+//Bit 23, count_enable deafult=1
+//Bit 22, soft_rst
+//Bit 21, count_rst
+//Bit 20, bypass run
+//Bit 19:14, ochannel_sel deafult=0x24
+//Bit 13:8, ichannel_sel deafult=0x24
+//Bit 3, 8bit mode
+//Bit 2, 10bit mode
+//Bit 1, reg_sync enable
+//Bit 0, bypass
+#define REG_NGPTV_CTRL1 ((0x31ac << 2) + 0xff000000)
+//Bit 31:7 reserved
+//Bit 6 reset sw default=0
+//Bit 5:0 gclk_ctrl
+#define REG_NGPTV_CTRL2 ((0x31ad << 2) + 0xff000000)
+//Bit 31:8 reserved
+//Bit 7 SpareIn
+//Bit 6 NG_EnableServiceIn
+//Bit 5:4 reserved
+//Bit 3 NG_DebugEnableIn
+//Bit 2 reserved
+//Bit 1 NG_Payload24_56n
+//Bit 0 NG_YUVnRGBIn
+#define REG_NGPTV_CTRL3 ((0x31ce << 2) + 0xff000000)
+//Bit 31:0 NG_KeyIn default=0x01ac7f33
+#define REG_NGPTV_CTRL4 ((0x31cf << 2) + 0xff000000)
+//Bit 31:0 NG_PayloadDataIn[31:0] default=0x6789abcd
+#define REG_NGPTV_CTRL5 ((0x31f0 << 2) + 0xff000000)
+//Bit 31:26 Reserved
+//Bit 25:24 NG_FrameTypeIn default=3
+//Bit 23:0 NG_PayloadDataIn default=0x012345
+#define REG_NGPTV_CTRL6 ((0x31f1 << 2) + 0xff000000)
+//Bit 31:0 NG_SettingIn[31:0] default=0x18c6318c
+#define REG_NGPTV_CTRL7 ((0x31f2 << 2) + 0xff000000)
+//Bit 31:0 NG_SettingIn[63:32] default=0x84210842
+#define REG_NGPTV_CTRL8 ((0x31f3 << 2) + 0xff000000)
+//Bit 31:0 NG_SettingIn[95:64] default=0x21084210
+#define REG_NGPTV_CTRL9 ((0x31f4 << 2) + 0xff000000)
+//Bit 31:0 NG_SettingIn[127:96] default=0x8c631084
+#define REG_NGPTV_CTRL10 ((0x31f5 << 2) + 0xff000000)
+//Bit 31:0 NG_SettingIn[159:128] default=0x84210631
+#define REG_NGPTV_CTRL11 ((0x31f6 << 2) + 0xff000000)
+//Bit 31:16 Reserved
+//Bit 15:8 NG_FrameRateIn default=0x18
+//Bit 7 Reserved
+//Bit 6:5 NG_CoreIDIn default=0
+//Bit 4:0 NG_SettingIn[165:160] default=0x10
+#define REG_NGPTV_CTRL12 ((0x31f7 << 2) + 0xff000000)
+//Bit 31:29 Reserved
+//Bit 28:16 vsize default=0x438
+//Bit 16:13 Reserved
+//Bit 12:0 hsize default=0x780
+#define REG_NGPTV_CTRL13 ((0x31f8 << 2) + 0xff000000)
+//Bit 31:29 Reserved
+//Bit 28:16 reg_vphstart default=0x0
+//Bit 16:13 Reserved
+//Bit 12:0 reg_vphend default=0x437
+#define REG_NGPTV_CTRL14 ((0x31f9 << 2) + 0xff000000)
+//Bit 31:13 Reserved
+//Bit 12:0 reg_3d_right_st default=0x3c0
+#define REG_NGPTV_CTRL15 ((0x31fa << 2) + 0xff000000)
+//Bit 31:29 Reserved
+//Bit 28:16 reg_vpvstart0 default=0x0
+//Bit 16:13 Reserved
+//Bit 12:0 reg_vpvend0 default=0x437
+#define REG_NGPTV_CTRL16 ((0x31fb << 2) + 0xff000000)
+//Bit 31:29 Reserved
+//Bit 28:16 reg_vpvstart1 default=0
+//Bit 16:13 Reserved
+//Bit 12:0 reg_vpvend1 default=0
+#define REG_NGPTV_CTRL17 ((0x31fc << 2) + 0xff000000)
+//Bit 31:29 Reserved
+//Bit 28:16 reg_vpvstart2 default=0
+//Bit 16:13 Reserved
+//Bit 12:0 reg_vpvend2 default=0
+#define REG_NGPTV_CTRL18 ((0x31fd << 2) + 0xff000000)
+//Bit 31:29 Reserved
+//Bit 28:16 reg_vpvstart3 default=0
+//Bit 16:13 Reserved
+//Bit 12:0 reg_vpvend3 default=0
+#define RO_NGPTV_CTRL19 ((0x31fe << 2) + 0xff000000)
+//Bit 31 dat_val_in
+//Bit 30 in_hold
+//Bit 29 out_hold
+//Bit 28:16 vcnt
+//Bit 15:12 NG_ErrorOut
+//Bit 11:0 NG_VersionOut
+//
+// Closing file: ngptv_reg.h
+//
+// 8'hd0-8hef
+//
+// Reading file: bt2020_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//Bit 31:27 for all [31] for all eotf enable,[30] for matrix3x3 enable, [29:27] for eotf_ch0~3
+//Bit 17:6 for clock gating
+//Bit 5:4 pscale_mode ch2
+//Bit 3:2 pscale_mode ch1
+//Bit 1:0 pscale_mode ch0
+#define VPP_EOTF_CTL ((0x31d0 << 2) + 0xff000000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define VPP_EOTF_COEF00_01 ((0x31d1 << 2) + 0xff000000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define VPP_EOTF_COEF02_10 ((0x31d2 << 2) + 0xff000000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define VPP_EOTF_COEF11_12 ((0x31d3 << 2) + 0xff000000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define VPP_EOTF_COEF20_21 ((0x31d4 << 2) + 0xff000000)
+//Bit 28:16 coef22
+//Bit 2:0 coef_rs
+#define VPP_EOTF_COEF22_RS ((0x31d5 << 2) + 0xff000000)
+#define VPP_EOTF_LUT_ADDR_PORT ((0x31d6 << 2) + 0xff000000)
+#define VPP_EOTF_LUT_DATA_PORT ((0x31d7 << 2) + 0xff000000)
+#define VPP_EOTF_3X3_OFST_0 ((0x31d8 << 2) + 0xff000000)
+#define VPP_EOTF_3X3_OFST_1 ((0x31d9 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: bt2020_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_partb_reg.h
+//
+// -----------------------------------------------
+// REG_BASE: VPPD_VCBUS_BASE = 0x32
+// -----------------------------------------------
+//
+// Reading file: vpp_vadj_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//------------------------------------------------------------------------------
+// VD1 path
+//------------------------------------------------------------------------------
+//`define VD1_IF0_GEN_REG 8'h0
+//`define VD1_IF0_CANVAS0 8'h1
+//`define VD1_IF0_CANVAS1 8'h2
+//`define VD1_IF0_LUMA_X0 8'h3
+//`define VD1_IF0_LUMA_Y0 8'h4
+//`define VD1_IF0_CHROMA_X0 8'h5
+//`define VD1_IF0_CHROMA_Y0 8'h6
+//`define VD1_IF0_LUMA_X1 8'h7
+//`define VD1_IF0_LUMA_Y1 8'h8
+//`define VD1_IF0_CHROMA_X1 8'h9
+//`define VD1_IF0_CHROMA_Y1 8'ha
+//`define VD1_IF0_RPT_LOOP 8'hb
+//`define VD1_IF0_LUMA0_RPT_PAT 8'hc
+//`define VD1_IF0_CHROMA0_RPT_PAT 8'hd
+//`define VD1_IF0_LUMA1_RPT_PAT 8'he
+//`define VD1_IF0_CHROMA1_RPT_PAT 8'hf
+//`define VD1_IF0_LUMA_PSEL 8'h10
+//`define VD1_IF0_CHROMA_PSEL 8'h11
+//`define VD1_IF0_DUMMY_PIXEL 8'h12
+//`define VD1_IF0_LUMA_FIFO_SIZE 8'h13
+//`define VD1_IF0_AXI_CMD_CNT 8'h14
+//`define VD1_IF0_AXI_RDAT_CNT 8'h15
+//`define VD1_IF0_GEN_REG3 8'h16
+//Bit 31 it true, disable clock, otherwise enable clock
+//Bit 30 soft rst bit
+//Bit 28 if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
+//Bit 27:24 horizontal formatter initial phase
+//Bit 23 horizontal formatter repeat pixel 0 enable
+//Bit 22:21 horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
+//Bit 20 horizontal formatter enable
+//Bit 19 if true, always use phase0 while vertical formater, meaning always
+// repeat data, no interpolation
+//Bit 18 if true, disable vertical formatter chroma repeat last line
+//Bit 17 veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable
+//Bit 16 veritcal formatter repeat line 0 enable
+//Bit 15:12 vertical formatter skip line num at the beginning
+//Bit 11:8 vertical formatter initial phase
+//Bit 7:1 vertical formatter phase step (3.4)
+//Bit 0 vertical formatter enable
+//`define VIU_VD1_FMT_CTRL 8'h18 //29'h0
+//Bit 27:16 horizontal formatter width
+//Bit 11:0 vertical formatter width
+//`define VIU_VD1_FMT_W 8'h19 //28'h0
+//`define VD1_IF0_RANGE_MAP_Y 8'h1a
+//`define VD1_IF0_RANGE_MAP_CB 8'h1b
+//`define VD1_IF0_RANGE_MAP_CR 8'h1c
+//`define VD1_IF0_GEN_REG2 8'h1d
+//`define VD1_IF0_PROT_CNTL 8'h1e
+//`define VD1_IF0_URGENT_CTRL 8'h1f
+//------------------------------------------------------------------------------
+// VD2 path
+//------------------------------------------------------------------------------
+//`define VD2_IF0_GEN_REG 8'h20
+//`define VD2_IF0_CANVAS0 8'h21
+//`define VD2_IF0_CANVAS1 8'h22
+//`define VD2_IF0_LUMA_X0 8'h23
+//`define VD2_IF0_LUMA_Y0 8'h24
+//`define VD2_IF0_CHROMA_X0 8'h25
+//`define VD2_IF0_CHROMA_Y0 8'h26
+//`define VD2_IF0_LUMA_X1 8'h27
+//`define VD2_IF0_LUMA_Y1 8'h28
+//`define VD2_IF0_CHROMA_X1 8'h29
+//`define VD2_IF0_CHROMA_Y1 8'h2a
+//`define VD2_IF0_RPT_LOOP 8'h2b
+//`define VD2_IF0_LUMA0_RPT_PAT 8'h2c
+//`define VD2_IF0_CHROMA0_RPT_PAT 8'h2d
+//`define VD2_IF0_LUMA1_RPT_PAT 8'h2e
+//`define VD2_IF0_CHROMA1_RPT_PAT 8'h2f
+//`define VD2_IF0_LUMA_PSEL 8'h30
+//`define VD2_IF0_CHROMA_PSEL 8'h31
+//`define VD2_IF0_DUMMY_PIXEL 8'h32
+//`define VD2_IF0_LUMA_FIFO_SIZE 8'h33
+//`define VD2_IF0_AXI_CMD_CNT 8'h34
+//`define VD2_IF0_AXI_RDAT_CNT 8'h35
+//`define VD2_IF0_GEN_REG3 8'h36
+//Bit 31 it true, disable clock, otherwise enable clock
+//Bit 30 soft rst bit
+//Bit 28 if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
+//Bit 27:24 horizontal formatter initial phase
+//Bit 23 horizontal formatter repeat pixel 0 enable
+//Bit 22:21 horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
+//Bit 20 horizontal formatter enable
+//Bit 17 veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable
+//Bit 16 veritcal formatter repeat line 0 enable
+//Bit 15:12 vertical formatter skip line num at the beginning
+//Bit 11:8 vertical formatter initial phase
+//Bit 7:1 vertical formatter phase step (3.4)
+//Bit 0 vertical formatter enable
+//`define VIU_VD2_FMT_CTRL 8'h38 //29'h0
+//Bit 27:16 horizontal formatter width
+//Bit 11:0 vertical formatter width
+//`define VIU_VD2_FMT_W 8'h39 //28'h0
+//`define VD2_IF0_RANGE_MAP_Y 8'h3a
+//`define VD2_IF0_RANGE_MAP_CB 8'h3b
+//`define VD2_IF0_RANGE_MAP_CR 8'h3c
+//`define VD2_IF0_GEN_REG2 8'h3d
+//`define VD2_IF0_PROT_CNTL 8'h3e
+//`define VD2_IF0_URGENT_CTRL 8'h3f
+#define VPP_VADJ1_MISC ((0x3280 << 2) + 0xff000000)
+#define VPP_VADJ1_BLACK_VAL ((0x3281 << 2) + 0xff000000)
+#define VPP_VADJ1_Y ((0x3282 << 2) + 0xff000000)
+#define VPP_VADJ1_MA_MB ((0x3283 << 2) + 0xff000000)
+#define VPP_VADJ1_MC_MD ((0x3284 << 2) + 0xff000000)
+#define VPP_VADJ1_CURV_0 ((0x3285 << 2) + 0xff000000)
+#define VPP_VADJ1_CURV_1 ((0x3286 << 2) + 0xff000000)
+#define VPP_VADJ1_CURV_2 ((0x3287 << 2) + 0xff000000)
+#define VPP_VADJ1_CURV_3 ((0x3288 << 2) + 0xff000000)
+#define VPP_VD1_RGB_CTRST ((0x3289 << 2) + 0xff000000)
+#define VPP_VD1_RGB_BRGHT ((0x328a << 2) + 0xff000000)
+#define VPP_VD1_RGB_DLUT_0_3 ((0x328b << 2) + 0xff000000)
+#define VPP_VD1_RGB_DLUT_4_7 ((0x328c << 2) + 0xff000000)
+#define VPP_VD1_RGB_DLUT_8_11 ((0x328d << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF00_01 ((0x3290 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF02_10 ((0x3291 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF11_12 ((0x3292 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF20_21 ((0x3293 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF22 ((0x3294 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF13_14 ((0x3295 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF23_24 ((0x3296 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF15_25 ((0x3297 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_CLIP ((0x3298 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_OFFSET0_1 ((0x3299 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_OFFSET2 ((0x329a << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_PRE_OFFSET0_1 ((0x329b << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_PRE_OFFSET2 ((0x329c << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_EN_CTRL ((0x329d << 2) + 0xff000000)
+#define VPP_VADJ2_MISC ((0x32a0 << 2) + 0xff000000)
+#define VPP_VADJ2_BLACK_VAL ((0x32a1 << 2) + 0xff000000)
+#define VPP_VADJ2_Y ((0x32a2 << 2) + 0xff000000)
+#define VPP_VADJ2_MA_MB ((0x32a3 << 2) + 0xff000000)
+#define VPP_VADJ2_MC_MD ((0x32a4 << 2) + 0xff000000)
+#define VPP_VADJ2_CURV_0 ((0x32a5 << 2) + 0xff000000)
+#define VPP_VADJ2_CURV_1 ((0x32a6 << 2) + 0xff000000)
+#define VPP_VADJ2_CURV_2 ((0x32a7 << 2) + 0xff000000)
+#define VPP_VADJ2_CURV_3 ((0x32a8 << 2) + 0xff000000)
+#define VPP_POST_RGB_CTRST ((0x32a9 << 2) + 0xff000000)
+#define VPP_POST_RGB_BRGHT ((0x32aa << 2) + 0xff000000)
+#define VPP_POST_RGB_DLUT_0_3 ((0x32ab << 2) + 0xff000000)
+#define VPP_POST_RGB_DLUT_4_7 ((0x32ac << 2) + 0xff000000)
+#define VPP_POST_RGB_DLUT_8_11 ((0x32ad << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF00_01 ((0x32b0 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF02_10 ((0x32b1 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF11_12 ((0x32b2 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF20_21 ((0x32b3 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF22 ((0x32b4 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF13_14 ((0x32b5 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF23_24 ((0x32b6 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF15_25 ((0x32b7 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_CLIP ((0x32b8 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_OFFSET0_1 ((0x32b9 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_OFFSET2 ((0x32ba << 2) + 0xff000000)
+#define VPP_POST_MATRIX_PRE_OFFSET0_1 ((0x32bb << 2) + 0xff000000)
+#define VPP_POST_MATRIX_PRE_OFFSET2 ((0x32bc << 2) + 0xff000000)
+#define VPP_POST_MATRIX_EN_CTRL ((0x32bd << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_SAT ((0x32c0 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_SAT ((0x32c1 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_vadj_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: DOLBY1A_VCBUS_BASE = 0x33
+// -----------------------------------------------
+//
+// Reading file: dolby1a_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DOLBY_CORE1A_REG_START ((0x3300 << 2) + 0xff000000)
+#define DOLBY_CORE1A_CLKGATE_CTRL ((0x33f2 << 2) + 0xff000000)
+#define DOLBY_CORE1A_SWAP_CTRL0 ((0x33f3 << 2) + 0xff000000)
+#define DOLBY_CORE1A_SWAP_CTRL1 ((0x33f4 << 2) + 0xff000000)
+#define DOLBY_CORE1A_SWAP_CTRL2 ((0x33f5 << 2) + 0xff000000)
+#define DOLBY_CORE1A_SWAP_CTRL3 ((0x33f6 << 2) + 0xff000000)
+#define DOLBY_CORE1A_SWAP_CTRL4 ((0x33f7 << 2) + 0xff000000)
+#define DOLBY_CORE1A_SWAP_CTRL5 ((0x33f8 << 2) + 0xff000000)
+#define DOLBY_CORE1A_DMA_CTRL ((0x33f9 << 2) + 0xff000000)
+#define DOLBY_CORE1A_DMA_STATUS ((0x33fa << 2) + 0xff000000)
+#define DOLBY_CORE1A_STATUS0 ((0x33fb << 2) + 0xff000000)
+#define DOLBY_CORE1A_STATUS1 ((0x33fc << 2) + 0xff000000)
+#define DOLBY_CORE1A_STATUS2 ((0x33fd << 2) + 0xff000000)
+#define DOLBY_CORE1A_STATUS3 ((0x33fe << 2) + 0xff000000)
+#define DOLBY_CORE1A_DMA_PORT ((0x33ff << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dolby1a_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: DOLBY2A_VCBUS_BASE = 0x34
+// -----------------------------------------------
+//
+// Reading file: dolby2a_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DOLBY_CORE2A_REG_START ((0x3400 << 2) + 0xff000000)
+#define DOLBY_CORE2A_CTRL ((0x3401 << 2) + 0xff000000)
+#define DOLBY_CORE2A_Metadata_Start ((0x3402 << 2) + 0xff000000)
+#define DOLBY_CORE2A_Metadata_End ((0x3403 << 2) + 0xff000000)
+#define DOLBY_CORE2A_Interrupt_Raw ((0x3404 << 2) + 0xff000000)
+#define DOLBY_CORE2A_Interrupt_Enable ((0x3405 << 2) + 0xff000000)
+#define DOLBY_CORE2A_CLKGATE_CTRL ((0x3432 << 2) + 0xff000000)
+#define DOLBY_CORE2A_SWAP_CTRL0 ((0x3433 << 2) + 0xff000000)
+#define DOLBY_CORE2A_SWAP_CTRL1 ((0x3434 << 2) + 0xff000000)
+#define DOLBY_CORE2A_SWAP_CTRL2 ((0x3435 << 2) + 0xff000000)
+#define DOLBY_CORE2A_SWAP_CTRL3 ((0x3436 << 2) + 0xff000000)
+#define DOLBY_CORE2A_SWAP_CTRL4 ((0x3437 << 2) + 0xff000000)
+#define DOLBY_CORE2A_SWAP_CTRL5 ((0x3438 << 2) + 0xff000000)
+#define DOLBY_CORE2A_DMA_CTRL ((0x3439 << 2) + 0xff000000)
+#define DOLBY_CORE2A_DMA_STATUS ((0x343a << 2) + 0xff000000)
+#define DOLBY_CORE2A_STATUS0 ((0x343b << 2) + 0xff000000)
+#define DOLBY_CORE2A_STATUS1 ((0x343c << 2) + 0xff000000)
+#define DOLBY_CORE2A_STATUS2 ((0x343d << 2) + 0xff000000)
+#define DOLBY_CORE2A_STATUS3 ((0x343e << 2) + 0xff000000)
+#define DOLBY_CORE2A_DMA_PORT ((0x343f << 2) + 0xff000000)
+#define DOLBY_CORE2A_AXI2DMA_CTRL0 ((0x3440 << 2) + 0xff000000)
+#define DOLBY_CORE2A_AXI2DMA_CTRL1 ((0x3441 << 2) + 0xff000000)
+#define DOLBY_CORE2A_AXI2DMA_CTRL2 ((0x3442 << 2) + 0xff000000)
+#define DOLBY_CORE2A_AXI2DMA_CTRL3 ((0x3443 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dolby2a_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: DOLBY2B_VCBUS_BASE = 0x35
+// -----------------------------------------------
+//`include "dolby2b_regs.h"
+// -----------------------------------------------
+// REG_BASE: DOLBY3_VCBUS_BASE = 0x36
+// -----------------------------------------------
+//
+// Reading file: dolby3_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DOLBY_CORE3_REG_START ((0x3600 << 2) + 0xff000000)
+#define DOLBY_CORE3_CTRL ((0x3601 << 2) + 0xff000000)
+#define DOLBY_CORE3_Metadata_Start ((0x3602 << 2) + 0xff000000)
+#define DOLBY_CORE3_Metadata_End ((0x3603 << 2) + 0xff000000)
+#define DOLBY_CORE3_Interrupt_Raw ((0x3604 << 2) + 0xff000000)
+#define DOLBY_CORE3_Interrupt_Enable ((0x3605 << 2) + 0xff000000)
+#define DOLBY_CORE3_CLKGATE_CTRL ((0x36f0 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL0 ((0x36f1 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL1 ((0x36f2 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL2 ((0x36f3 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL3 ((0x36f4 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL4 ((0x36f5 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL5 ((0x36f6 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL6 ((0x36f7 << 2) + 0xff000000)
+#define DOLBY_CORE3_DIAG_CTRL ((0x36f8 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL8 ((0x36f9 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL9 ((0x36fa << 2) + 0xff000000)
+#define DOLBY_CORE3_CRC_CTRL ((0x36fb << 2) + 0xff000000)
+#define DOLBY_CORE3_INPUT_CSC_CRC ((0x36fc << 2) + 0xff000000)
+#define DOLBY_CORE3_OUTPUT_CSC_CRC ((0x36fd << 2) + 0xff000000)
+#define DOLBY_CORE3_STATUS3 ((0x36fe << 2) + 0xff000000)
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dolby3_regs.h
+//
+//
+// Reading file: vpu_madc_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: MADC_VCBUS_BASE = 0x37
+// -----------------------------------------------
+// 0x00-0x28
+//
+// Reading file: nr4_nm_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define NR4_MCNR_SAD_GAIN ((0x3700 << 2) + 0xff000000)
+//Bit 31:25 reserved
+//Bit 24 reg_nr4_bld12vs3_usemaxsad // unsigned , default = 0 use minsad/maxsad instead of minsad/avgsad to decision if it was texture or flat region, 1: use minsad/maxsad
+//Bit 23:16 reg_nr4_bld12vs3_rate_gain // unsigned , default = 64 gain to minsad/maxsad or minsad/avgsad before LUT, 64 normalized as "1"
+//Bit 15: 8 reg_nr4_bld1vs2_rate_gain // unsigned , default = 32 gain to minsad/maxsad or minsad/avgsad before the LUT, 64 normalized as"1"
+//Bit 7: 0 reg_nr4_coefblt_gain // unsigned , default = 64 gain to final coefblt, normalized 64 as "1"
+#define NR4_MCNR_LPF_CTRL ((0x3701 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:22 reg_nr4_preflt_alpofst // signed , default = 0 pre filter alpha ofst
+//Bit 21:16 reg_nr4_preflt_alpgain // unsigned , default = 16 pre filter alpha gain
+//Bit 15:14 reg_nr4_preflt_alpsel // unsigned , default = 3 pre filter alpha selection for adaptive blending, 0: mv pointed sad, 1: weighted mv pointed sad, 2or3: coefblt
+//Bit 13: 8 reg_nr4_avgsad_gain // unsigned , default = 8 gain for avg sad before luts
+//Bit 7 reserved
+//Bit 6 reg_nr4_maxsad_mod // unsigned , default = 1 max sad select mode, 0: mx2_sad, 1: max sad
+//Bit 5 reg_nr4_minsad_mod // unsigned , default = 1 min sad select mode, 0: sad with min err, 1: min sad
+//Bit 4 reg_nr4_minmaxsad_lpf // unsigned , default = 1 mode of lpf for minmaxsad, 0: no LPF, 1: [1 2 1]/4
+//Bit 3 reg_nr4_avgsad_lpf // unsigned , default = 1 mode of lpf for avgsad, 0: no LPF, 1: [1 2 1]/4
+//Bit 2 reg_nr4_minavgsad_ratio_lpf // unsigned , default = 1 mode of lpf for minsad/avgsad and zmvsad/avgsad, 0: no LPF, 1: [1 2 1]/4
+//Bit 1 reg_nr4_bldvs_lut_lpf // unsigned , default = 1 mode of lpf for bld12vs3 and bld1vs2 LUT results, 0: no LPF, 1: [1 2 1]/4
+//Bit 0 reg_nr4_final_coef_lpf // unsigned , default = 1 mode of lpf for final coef_blt_blend123, 0: no LPF, 1: [1 2 1]/4
+#define NR4_MCNR_BLD_VS3LUT0 ((0x3702 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_bld12vs3_lut0 // unsigned , default = 0
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_bld12vs3_lut1 // unsigned , default = 8
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_bld12vs3_lut2 // unsigned , default = 10
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bld12vs3_lut3 // unsigned , default = 11
+#define NR4_MCNR_BLD_VS3LUT1 ((0x3703 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_bld12vs3_lut4 // unsigned , default = 12
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_bld12vs3_lut5 // unsigned , default = 14
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_bld12vs3_lut6 // unsigned , default = 16
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bld12vs3_lut7 // unsigned , default = 24
+#define NR4_MCNR_BLD_VS3LUT2 ((0x3704 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_bld12vs3_lut8 // unsigned , default = 50
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_bld12vs3_lut9 // unsigned , default = 58
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_bld12vs3_lut10 // unsigned , default = 63
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bld12vs3_lut11 // unsigned , default = 63
+#define NR4_MCNR_BLD_VS2LUT0 ((0x3705 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_bld1vs2_lut0 // unsigned , default = 63
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_bld1vs2_lut1 // unsigned , default = 32
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_bld1vs2_lut2 // unsigned , default = 16
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bld1vs2_lut3 // unsigned , default = 8
+#define NR4_MCNR_BLD_VS2LUT1 ((0x3706 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_bld1vs2_lut4 // unsigned , default = 4
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_bld1vs2_lut5 // unsigned , default = 2
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_bld1vs2_lut6 // unsigned , default = 1
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bld1vs2_lut7 // unsigned , default = 0
+#define NR4_COEFBLT_LUT10 ((0x3707 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut10 // signed , default = -128
+//Bit 23:16 reg_nr4_coefblt_lut11 // signed , default = -128
+//Bit 15: 8 reg_nr4_coefblt_lut12 // signed , default = -126
+//Bit 7: 0 reg_nr4_coefblt_lut13 // signed , default = -124
+#define NR4_COEFBLT_LUT11 ((0x3708 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut14 // signed , default = -120
+//Bit 23:16 reg_nr4_coefblt_lut15 // signed , default = -110
+//Bit 15: 8 reg_nr4_coefblt_lut16 // signed , default = -100
+//Bit 7: 0 reg_nr4_coefblt_lut17 // signed , default = -90
+#define NR4_COEFBLT_LUT12 ((0x3709 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut18 // signed , default = -56
+//Bit 23:16 reg_nr4_coefblt_lut19 // signed , default = -32
+//Bit 15: 8 reg_nr4_coefblt_lut110 // signed , default = -64
+//Bit 7: 0 reg_nr4_coefblt_lut111 // signed , default = -128
+#define NR4_COEFBLT_LUT20 ((0x370a << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut20 // signed , default = -128
+//Bit 23:16 reg_nr4_coefblt_lut21 // signed , default = -120
+//Bit 15: 8 reg_nr4_coefblt_lut22 // signed , default = -112
+//Bit 7: 0 reg_nr4_coefblt_lut23 // signed , default = -104
+#define NR4_COEFBLT_LUT21 ((0x370b << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut24 // signed , default = -96
+//Bit 23:16 reg_nr4_coefblt_lut25 // signed , default = -88
+//Bit 15: 8 reg_nr4_coefblt_lut26 // signed , default = -76
+//Bit 7: 0 reg_nr4_coefblt_lut27 // signed , default = -64
+#define NR4_COEFBLT_LUT22 ((0x370c << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut28 // signed , default = -48
+//Bit 23:16 reg_nr4_coefblt_lut29 // signed , default = -32
+//Bit 15: 8 reg_nr4_coefblt_lut210 // signed , default = -64
+//Bit 7: 0 reg_nr4_coefblt_lut211 // signed , default = -108
+#define NR4_COEFBLT_LUT30 ((0x370d << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut30 // signed , default = 8
+//Bit 23:16 reg_nr4_coefblt_lut31 // signed , default = 16
+//Bit 15: 8 reg_nr4_coefblt_lut32 // signed , default = 24
+//Bit 7: 0 reg_nr4_coefblt_lut33 // signed , default = 30
+#define NR4_COEFBLT_LUT31 ((0x370e << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut34 // signed , default = 36
+//Bit 23:16 reg_nr4_coefblt_lut35 // signed , default = 48
+//Bit 15: 8 reg_nr4_coefblt_lut36 // signed , default = 70
+//Bit 7: 0 reg_nr4_coefblt_lut37 // signed , default = 96
+#define NR4_COEFBLT_LUT32 ((0x370f << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut38 // signed , default = 120
+//Bit 23:16 reg_nr4_coefblt_lut39 // signed , default = 64
+//Bit 15: 8 reg_nr4_coefblt_lut310 // signed , default = 16
+//Bit 7: 0 reg_nr4_coefblt_lut311 // signed , default = -8
+#define NR4_COEFBLT_CONV ((0x3710 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_coefblt_convmin // unsigned , default = 0 minimum of coef. bilateral conversion
+//Bit 15: 8 reg_nr4_coefblt_convmax // unsigned , default = 255 maximum of coef. bilateral conversion
+//Bit 7: 0 reg_nr4_coefblt_convmid // unsigned , default = 128 value at midpoint of coef. bilateral conversion
+#define NR4_DBGWIN_YX0 ((0x3711 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_nr4_dgbwin_yx0 // unsigned , default = 100 ystart for debug window
+//Bit 15:14 reserved
+//Bit 13: 0 reg_nr4_dgbwin_yx1 // unsigned , default = 160 yend for debug window
+#define NR4_DBGWIN_YX1 ((0x3712 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_nr4_dgbwin_yx2 // unsigned , default = 200 xstart for debug window
+//Bit 15:14 reserved
+//Bit 13: 0 reg_nr4_dgbwin_yx3 // unsigned , default = 300 xend for debug window
+#define NR4_NM_X_CFG ((0x3713 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_nr4_nm_xst // unsigned , default = 8 start for noise meter statistic, dft = 8
+//Bit 15:14 reserved
+//Bit 13: 0 reg_nr4_nm_xed // unsigned , default = 711 end for noise meter statistic, dft = HSIZE-8-1;
+#define NR4_NM_Y_CFG ((0x3714 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_nr4_nm_yst // unsigned , default = 8 start for noise meter statistic, dft = 8;
+//Bit 15:14 reserved
+//Bit 13: 0 reg_nr4_nm_yed // unsigned , default = 231 end for noise meter statistic, dft = VSIZE-8-1;
+#define NR4_NM_SAD_THD ((0x3715 << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7: 0 reg_nr4_nm_sad_thd // unsigned , default = 255 threshold for (flat region) sad count, dft = 4
+#define NR4_MCNR_BANDSPLIT_PRAM ((0x3716 << 2) + 0xff000000)
+//Bit 31: 5 reserved
+//Bit 4 reg_nr4_mc_use_bandsplit // unsigned , default = 1 separate lp and us for mc IIR filter, 0: no BS used; 1: use BS
+//Bit 3 reg_nr4_mc_apply_on_lp // unsigned , default = 1 use mcnr only on lowpass portion;
+//Bit 2 reg_nr4_mc_apply_on_us // unsigned , default = 1 use mcnr only on lp complimentary portion;
+//Bit 1: 0 reg_nr4_mc_zmvbs_use_adplpf // unsigned , default = 1 use adapptive LPF for the zmv pointing data for MCNR, for abs(mvx)<th
+#define NR4_MCNR_ALP1_SGN_COR ((0x3717 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_mc_aph1_sgn_coring0 // unsigned , default = 10 coring to cur-pre before do sgn decision
+//Bit 23:16 reg_nr4_mc_aph1_sgn_coring1 // unsigned , default = 7 coring to cur-pre before do sgn decision
+//Bit 15: 8 reg_nr4_mc_aph1_sgn_core_max0 // unsigned , default = 90 maximum of coring, default = 30/15
+//Bit 7: 0 reg_nr4_mc_aph1_sgn_core_max1 // unsigned , default = 15 maximum of coring, default = 30/15
+#define NR4_MCNR_ALP1_SGN_PRAM ((0x3718 << 2) + 0xff000000)
+//Bit 31:11 reserved
+//Bit 10 reg_nr4_mc_alp1_sgn_half // unsigned , default = 1 half block sgn sum mode enable, 0: only use 3x5 whole block sum of sgns; 1: use max(sgn_3x5, sqrt(sgn_left+sgn_righ))
+//Bit 9 reg_nr4_mc_alp1_sgn_frczmv // unsigned , default = 1 force zmv to calculate the sign_sum;
+//Bit 8 reg_nr4_mc_alp1_sgnmvx_mode // unsigned , default = 1 blend mode of sgnlut and mvxlut blend mode: 0: sgnlut+ mvxlut; 1: max(sgnlut, mvxlut), default =1
+//Bit 7: 4 reg_nr4_mc_aph1_sgn_crate0 // unsigned , default = 4 rate to var, norm to 16 as 1, default = 2
+//Bit 3: 0 reg_nr4_mc_aph1_sgn_crate1 // unsigned , default = 2 rate to var, norm to 16 as 1, default = 2
+#define NR4_MCNR_ALP1_MVX_LUT1 ((0x3719 << 2) + 0xff000000)
+//Bit 31:28 reg_nr4_mc_alp1_mvx_luty3 // unsigned , default = 14 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 27:24 reg_nr4_mc_alp1_mvx_lutc3 // unsigned , default = 14 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 23:20 reg_nr4_mc_alp1_mvx_luty2 // unsigned , default = 12 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 19:16 reg_nr4_mc_alp1_mvx_lutc2 // unsigned , default = 12 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 15:12 reg_nr4_mc_alp1_mvx_luty1 // unsigned , default = 5 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 11: 8 reg_nr4_mc_alp1_mvx_lutc1 // unsigned , default = 5 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 7: 4 reg_nr4_mc_alp1_mvx_luty0 // unsigned , default = 3 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 3: 0 reg_nr4_mc_alp1_mvx_lutc0 // unsigned , default = 3 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+#define NR4_MCNR_ALP1_MVX_LUT2 ((0x371a << 2) + 0xff000000)
+//Bit 31:28 reg_nr4_mc_alp1_mvx_luty7 // unsigned , default = 15 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 27:24 reg_nr4_mc_alp1_mvx_lutc7 // unsigned , default = 15 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 23:20 reg_nr4_mc_alp1_mvx_luty6 // unsigned , default = 15 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 19:16 reg_nr4_mc_alp1_mvx_lutc6 // unsigned , default = 15 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 15:12 reg_nr4_mc_alp1_mvx_luty5 // unsigned , default = 15 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 11: 8 reg_nr4_mc_alp1_mvx_lutc5 // unsigned , default = 15 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 7: 4 reg_nr4_mc_alp1_mvx_luty4 // unsigned , default = 15 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 3: 0 reg_nr4_mc_alp1_mvx_lutc4 // unsigned , default = 15 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+#define NR4_MCNR_ALP1_MVX_LUT3 ((0x371b << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7: 4 reg_nr4_mc_alp1_mvx_luty8 // unsigned , default = 6 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 3: 0 reg_nr4_mc_alp1_mvx_lutc8 // unsigned , default = 6 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+#define NR4_MCNR_ALP1_LP_PRAM ((0x371c << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:16 reg_nr4_mc_alp1_lp_sel // unsigned , default = 1 mode for alp1_lp for lp portion IIR, 0: apha1, 1:dc_dif vs ac analysis; 2: gain/ofst of alp1; 3: max of #1/#2 results
+//Bit 15: 8 reg_nr4_mc_alp1_lp_gain // unsigned , default = 64 gain to alp1 to get the alp1_lp = alp1*gain/32 + ofset, default =64;
+//Bit 7: 0 reg_nr4_mc_alp1_lp_ofst // signed , default = 0 offset to alp1 to get the alp1_lp = alp1*gain/32 + ofset, default =10;
+#define NR4_MCNR_ALP1_SGN_LUT1 ((0x371d << 2) + 0xff000000)
+//Bit 31:28 reg_nr4_mc_alp1_sgn_lut0 // unsigned , default = 3 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 27:24 reg_nr4_mc_alp1_sgn_lut1 // unsigned , default = 3 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 23:20 reg_nr4_mc_alp1_sgn_lut2 // unsigned , default = 3 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 19:16 reg_nr4_mc_alp1_sgn_lut3 // unsigned , default = 4 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 15:12 reg_nr4_mc_alp1_sgn_lut4 // unsigned , default = 5 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 11: 8 reg_nr4_mc_alp1_sgn_lut5 // unsigned , default = 6 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 7: 4 reg_nr4_mc_alp1_sgn_lut6 // unsigned , default = 7 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 3: 0 reg_nr4_mc_alp1_sgn_lut7 // unsigned , default = 8 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+#define NR4_MCNR_ALP1_SGN_LUT2 ((0x371e << 2) + 0xff000000)
+//Bit 31:28 reg_nr4_mc_alp1_sgn_lut8 // unsigned , default = 9 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 27:24 reg_nr4_mc_alp1_sgn_lut9 // unsigned , default = 10 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 23:20 reg_nr4_mc_alp1_sgn_lut10 // unsigned , default = 11 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 19:16 reg_nr4_mc_alp1_sgn_lut11 // unsigned , default = 12 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 15:12 reg_nr4_mc_alp1_sgn_lut12 // unsigned , default = 13 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 11: 8 reg_nr4_mc_alp1_sgn_lut13 // unsigned , default = 14 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 7: 4 reg_nr4_mc_alp1_sgn_lut14 // unsigned , default = 15 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 3: 0 reg_nr4_mc_alp1_sgn_lut15 // unsigned , default = 15 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+#define NR4_RO_NM_SAD_SUM ((0x371f << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_nm_sad_sum // unsigned , default = 0 sum of sad, for scene change detectcion, in noise meter
+#define NR4_RO_NM_SAD_CNT ((0x3720 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_nm_sad_cnt // unsigned , default = 0 cnt of sad, for scene change detectcion, in noise meter
+#define NR4_RO_NM_VAR_SUM ((0x3721 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_nm_var_sum // unsigned , default = 0 sum of var, for noise level detection, in noise meter
+#define NR4_RO_NM_VAR_SCNT ((0x3722 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_nm_var_cnt // unsigned , default = 0 cnt of var, for noise level detection, in noise meter
+#define NR4_RO_NM_VAR_MIN_MAX ((0x3723 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:12 ro_nr4_nm_min_var // unsigned , default = 1023 min of var, for noise level detection, in noise meter
+//Bit 11:10 reserved
+//Bit 9: 0 ro_nr4_nm_max_var // unsigned , default = 0 max of var, for noise level detection, in noise meter
+#define NR4_RO_NR4_DBGPIX_NUM ((0x3724 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27: 0 ro_nr4_dbgpix_num // unsigned , default = 0 number of pixels statistic invoved (removed?)
+#define NR4_RO_NR4_BLDVS2_SUM ((0x3725 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_bld1vs2_sum // unsigned , default = 0 sum of blend_1vs2 with the debug window
+#define NR4_BLDVS3_SUM ((0x3726 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_bld12vs3_sum // unsigned , default = 0 sum of blend_12vs3 with the debug window
+#define NR4_COEF12_SUM ((0x3727 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_coef12_sum // signed , default = 0 sum of coef_blt_blend12 with the debug window, under 8 bits precision
+#define NR4_COEF123_SUM ((0x3728 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_coef123_sum // signed , default = 0 sum of coef_final with the debug window, under 8 bits precision
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: nr4_nm_regs.h
+//
+// 0x30-0x32
+//
+// Reading file: vpu_xlr_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define XLR_CTRL ((0x3730 << 2) + 0xff000000)
+//Bit 31:23 reserved
+//Bit 22 reg_xlr_en // unsigned , default = 1 enable bits for xlr function, 1: enable, 0: disable default = 1
+//Bit 21 reg_xlr_side_en // unsigned , default = 1 enable to filter the above and below lines with xlr filter, default = 1
+//Bit 20 reg_xlr_3lines // unsigned , default = 1 3 lines version enable default= 0
+//Bit 19:16 reg_xlr_simlp_gain // unsigned , default = 12 gain to simlp to decide if need the XLR, default= 12
+//Bit 15:14 reserved
+//Bit 13: 8 reg_xlr_ooplp_gain // unsigned , default = 6 gain to out-of-phase lp error to decide if need the XLR, birn to 16 as 1, default= 3
+//Bit 7: 0 reg_xlr_dislp_thrd // unsigned , default = 64 threshold to lp error to discard XLR. default= 80
+#define XLR_THRD ((0x3731 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:24 reg_xlr_txt_core // unsigned , default = 3 coring to texture default = 3, (3/32)
+//Bit 23:16 reg_xlr_err_thrd2 // unsigned , default = 5 threshold to error to decide blending coef, 0, 1/4, 1/2, 1.0, defaut= {20, 10, 5}
+//Bit 15: 8 reg_xlr_err_thrd1 // unsigned , default = 10 threshold to error to decide blending coef, 0, 1/4, 1/2, 1.0, defaut= {20, 10, 5}
+//Bit 7: 0 reg_xlr_err_thrd0 // unsigned , default = 20 threshold to error to decide blending coef, 0, 1/4, 1/2, 1.0, defaut= {20, 10, 5}
+#define XLR_HCT_THRD ((0x3732 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 reg_xlr_hct_step // unsigned , default = 1 horizontal chroma diff steps, 0: abs[-1 (2) -1]; 1: abs[-1 0 (2) 0 -1], 2: abs[-1 0 0 (2) 0 0 -1]; 3:abs[-1 0 0 0 (2) 0 0 0 -1]
+//Bit 25:24 reg_xlr_hct_lpf // unsigned , default = 1 horizontal chroma diff low-pass filter enable, 0: no HLPF; 1: [1 2 1]; 2: max[-1:1]; 3: max[-2:2]
+//Bit 23:16 reg_xlr_hct_thr // unsigned , default = 20 horizontal chroma diff threshold for xlr enable, to save the horozontal no color tran mode
+//Bit 15: 8 reg_xlr_sat_thr // unsigned , default = 8 saturation threshold for xlr enable, the smaller of the threshold , the more will do xlr;
+//Bit 7: 2 reg_xlr_hmargin // unsigned , default = 3 left/right number of pixels without xlr;
+//Bit 1 reserved
+//Bit 0 reg_xlr_hpf_only // unsigned , default = 0 enable for only do xlr filter on high pass portion of the data, instead full data
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_xlr_regs.h
+//
+// 0x38-0x3f
+//
+// Reading file: nr_deband_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define NR_DB_FLT_CTRL ((0x3738 << 2) + 0xff000000)
+//Bit 31:27 reserved
+//Bit 26 reg_nrdeband_reset1 // unsigned , default = 0 0 : no reset seed 1: reload chroma seed
+//Bit 25 reg_nrdeband_reset0 // unsigned , default = 0 0 : no reset seed 1: reload luma seed
+//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 0 : yuv 1: RGB
+//Bit 23 reg_nrdeband_en11 // unsigned , default = 1 debanding registers of side lines, [0] for luma, same for below
+//Bit 22 reg_nrdeband_en10 // unsigned , default = 1 debanding registers of side lines, [1] for chroma, same for below
+//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
+//Bit 16 reserved
+//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
+//Bit 12 reserved
+//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6
+//Bit 8 reserved
+//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 debanding random hp portion xor, [0] for luma
+//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 debanding random hp portion xor, [1] for chroma
+//Bit 5 reg_nrdeband_en1 // unsigned , default = 1 debanding registers, for luma
+//Bit 4 reg_nrdeband_en0 // unsigned , default = 1 debanding registers, for chroma
+//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+#define NR_DB_FLT_YC_THRD ((0x3739 << 2) + 0xff000000)
+//Bit 31:28 reg_nrdeband_luma_th3 // unsigned , default = 9 threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 27:24 reg_nrdeband_luma_th2 // unsigned , default = 7 elseif <th[1] use (lpf*3 + y)/4
+//Bit 23:20 reg_nrdeband_luma_th1 // unsigned , default = 6 elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 19:16 reg_nrdeband_luma_th0 // unsigned , default = 5 elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else
+//Bit 15:12 reg_nrdeband_chrm_th3 // unsigned , default = 9 threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 11: 8 reg_nrdeband_chrm_th2 // unsigned , default = 7 elseif <th[1] use (lpf*3 + y)/4
+//Bit 7: 4 reg_nrdeband_chrm_th1 // unsigned , default = 6 elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 3: 0 reg_nrdeband_chrm_th0 // unsigned , default = 5 elseif <th[1] use (lpf*3 + y)/4elseif elseif
+#define NR_DB_FLT_RANDLUT ((0x373a << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:21 reg_nrdeband_randslut7 // unsigned , default = 1 lut0
+//Bit 20:18 reg_nrdeband_randslut6 // unsigned , default = 1 lut0
+//Bit 17:15 reg_nrdeband_randslut5 // unsigned , default = 1 lut0
+//Bit 14:12 reg_nrdeband_randslut4 // unsigned , default = 1 lut0
+//Bit 11: 9 reg_nrdeband_randslut3 // unsigned , default = 1 lut0
+//Bit 8: 6 reg_nrdeband_randslut2 // unsigned , default = 1 lut0
+//Bit 5: 3 reg_nrdeband_randslut1 // unsigned , default = 1 lut0
+//Bit 2: 0 reg_nrdeband_randslut0 // unsigned , default = 1 lut0
+#define NR_DB_FLT_PXI_THRD ((0x373b << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 to luma/|u/v| for using the denoise
+//Bit 15:10 reserved
+//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 to luma/|u/v| for using the denoise
+#define NR_DB_FLT_SEED_Y ((0x373c << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 noise adding seed for Y. seed[0]= 0x60a52f20; as default
+#define NR_DB_FLT_SEED_U ((0x373d << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 noise adding seed for U. seed[0]= 0x60a52f27; as default
+#define NR_DB_FLT_SEED_V ((0x373e << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define NR_DB_FLT_SEED3 ((0x373f << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed3 // unsigned , default = 1621438242 noise adding seed for V. seed[0]= 0x60a52f22; as default
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: nr_deband_regs.h
+//
+// 0x40-0x43
+//
+// Reading file: nr_downscale_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define NR_DS_BUF_SIZE ((0x3740 << 2) + 0xff000000)
+//Bit 31:24 dsbuf_rowmax // unsigned , default = 96
+//Bit 23:16 dsbuf_colmax // unsigned , default = 128
+//Bit 15: 8 dsbuf_orow // unsigned , default = 128
+//Bit 7: 0 dsbuf_ocol // unsigned , default = 128
+#define NR_DS_CTRL ((0x3741 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_h_step // unsigned , default = 8 rand lut0
+//Bit 23:22 reserved
+//Bit 21:16 reg_v_step // unsigned , default = 8 rand lut0
+//Bit 15 reserved
+//Bit 14:12 reg_haa_sel // unsigned , default = 4
+//Bit 11 reserved
+//Bit 10: 8 reg_vaa_sel // unsigned , default = 4
+//Bit 7 reserved
+//Bit 6: 4 reg_use_hphase // unsigned , default = 1
+//Bit 3: 1 reserved
+//Bit 0 reg_yuv_bldmode // unsigned , default = 0
+#define NR_DS_OFFSET ((0x3742 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_h_ofst // signed , default = 0
+//Bit 15:10 reserved
+//Bit 9: 0 reg_v_ofst // signed , default = 0
+#define NR_DS_BLD_COEF ((0x3743 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_yuv_bldcoef2 // unsigned , default = 128
+//Bit 15: 8 reg_yuv_bldcoef1 // unsigned , default = 64
+//Bit 7: 0 reg_yuv_bldcoef0 // unsigned , default = 64
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: nr_downscale_regs.h
+//
+// 0x44-0xbf
+//
+// Reading file: di_scale_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DI_SCO_FIFO_CTRL ((0x374e << 2) + 0xff000000)
+#define DI_SC_TOP_CTRL ((0x374f << 2) + 0xff000000)
+// dummy data used in the DI preblend and scaler
+// Bit 23:16 Y
+// Bit 15:8 CB
+// Bit 7:0 CR
+#define DI_SC_DUMMY_DATA ((0x3750 << 2) + 0xff000000)
+//input line length used in DI
+#define DI_SC_LINE_IN_LENGTH ((0x3751 << 2) + 0xff000000)
+//input Picture height used in DI
+#define DI_SC_PIC_IN_HEIGHT ((0x3752 << 2) + 0xff000000)
+//Because there are many coefficients used in the vertical filter and horizontal filters,
+//indirect access the coefficients of vertical filter and horizontal filter is used.
+//For vertical filter, there are 33x4 coefficients
+//For horizontal filter, there are 33x4 coefficients
+//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
+//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
+//Bit 13 if true, vertical separated coef enable
+//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
+//Bit 8:7 type of index, 00: vertical coef, 01: vertical chroma coef: 10: horizontal coef, 11: resevered
+//Bit 6:0 coef index
+#define DI_SC_COEF_IDX ((0x3753 << 2) + 0xff000000)
+//coefficients for vertical filter and horizontal filter
+#define DI_SC_COEF ((0x3754 << 2) + 0xff000000)
+//these following registers are the absolute line address pointer for output divided screen
+//The output divided screen is shown in the following:
+//
+// -------------------------- <------ line zero
+// .
+// .
+// . region0 <---------- nonlinear region or nonscaling region
+// .
+// ---------------------------
+// --------------------------- <------ region1_startp
+// .
+// . region1 <---------- nonlinear region
+// .
+// .
+// ---------------------------
+// --------------------------- <------ region2_startp
+// .
+// . region2 <---------- linear region
+// .
+// .
+// ---------------------------
+// --------------------------- <------ region3_startp
+// .
+// . region3 <---------- nonlinear region
+// .
+// .
+// ---------------------------
+// --------------------------- <------ region4_startp
+// .
+// . region4 <---------- nonlinear region or nonoscaling region
+// .
+// .
+// --------------------------- <------ region4_endp
+//Bit 28:16 region1 startp
+//Bit 12:0 region2 startp
+#define DI_VSC_REGION12_STARTP ((0x3755 << 2) + 0xff000000)
+//Bit 28:16 region3 startp
+//Bit 12:0 region4 startp
+#define DI_VSC_REGION34_STARTP ((0x3756 << 2) + 0xff000000)
+#define DI_VSC_REGION4_ENDP ((0x3757 << 2) + 0xff000000)
+//vertical start phase step, (source/dest)*(2^24)
+//Bit 27:24 integer part
+//Bit 23:0 fraction part
+#define DI_VSC_START_PHASE_STEP ((0x3758 << 2) + 0xff000000)
+//vertical scaler region0 phase slope, Bit24 signed bit
+#define DI_VSC_REGION0_PHASE_SLOPE ((0x3759 << 2) + 0xff000000)
+//vertical scaler region1 phase slope, Bit24 signed bit
+#define DI_VSC_REGION1_PHASE_SLOPE ((0x375a << 2) + 0xff000000)
+//vertical scaler region3 phase slope, Bit24 signed bit
+#define DI_VSC_REGION3_PHASE_SLOPE ((0x375b << 2) + 0xff000000)
+//vertical scaler region4 phase slope, Bit24 signed bit
+#define DI_VSC_REGION4_PHASE_SLOPE ((0x375c << 2) + 0xff000000)
+//Bit 18:17 double line mode, input/output line width of vscaler becomes 2X,
+// so only 2 line buffer in this case, use for 3D line by line interleave scaling
+// bit1 true, double the input width and half input height, bit0 true, change line buffer 2 lines instead of 4 lines
+//Bit 16 0: progressive output, 1: interlace output
+//Bit 15 vertical scaler output line0 in advance or not for bottom field
+//Bit 14:13 vertical scaler initial repeat line0 number for bottom field
+//Bit 11:8 vertical scaler initial receiving number for bottom field
+//Bit 7 vertical scaler output line0 in advance or not for top field
+//Bit 6:5 vertical scaler initial repeat line0 number for top field
+//Bit 3:0 vertical scaler initial receiving number for top field
+#define DI_VSC_PHASE_CTRL ((0x375d << 2) + 0xff000000)
+//Bit 31:16 vertical scaler field initial phase for bottom field
+//Bit 15:0 vertical scaler field initial phase for top field
+#define DI_VSC_INI_PHASE ((0x375e << 2) + 0xff000000)
+//Bit 28:16 region1 startp
+//Bit 12:0 region2 startp
+#define DI_HSC_REGION12_STARTP ((0x3760 << 2) + 0xff000000)
+//Bit 28:16 region3 startp
+//Bit 12:0 region4 startp
+#define DI_HSC_REGION34_STARTP ((0x3761 << 2) + 0xff000000)
+#define DI_HSC_REGION4_ENDP ((0x3762 << 2) + 0xff000000)
+//horizontal start phase step, (source/dest)*(2^24)
+//Bit 27:24 integer part
+//Bit 23:0 fraction part
+#define DI_HSC_START_PHASE_STEP ((0x3763 << 2) + 0xff000000)
+//horizontal scaler region0 phase slope, Bit24 signed bit
+#define DI_HSC_REGION0_PHASE_SLOPE ((0x3764 << 2) + 0xff000000)
+//horizontal scaler region1 phase slope, Bit24 signed bit
+#define DI_HSC_REGION1_PHASE_SLOPE ((0x3765 << 2) + 0xff000000)
+//horizontal scaler region3 phase slope, Bit24 signed bit
+#define DI_HSC_REGION3_PHASE_SLOPE ((0x3766 << 2) + 0xff000000)
+//horizontal scaler region4 phase slope, Bit24 signed bit
+#define DI_HSC_REGION4_PHASE_SLOPE ((0x3767 << 2) + 0xff000000)
+//Bit 22:21 horizontal scaler initial repeat pixel0 number0
+//Bit 19:16 horizontal scaler initial receiving number0
+//Bit 15:0 horizontal scaler top field initial phase0
+#define DI_HSC_PHASE_CTRL ((0x3768 << 2) + 0xff000000)
+// Bit 31 if false, di_scale swap layer bypass
+// bit 30 if true, scale before diwr, else scaler before nrwr
+// Bit 22 if true, divide VSC line length 2 as the HSC input length, othwise VSC length length is the same as the VSC line length,
+// just for special usage, more flexibility
+// Bit 21 if true, prevsc uses lin buffer, otherwise prevsc does not use line buffer, it should be same as prevsc_en
+// Bit 20 prehsc_en
+// Bit 19 prevsc_en
+// Bit 18 vsc_en
+// Bit 17 hsc_en
+// Bit 16 scale_top_en
+// Bit 15 video1 scale out enable
+// Bit 12 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for horizontal scaler
+// Bit 10:8 horizontal scaler bank length
+// Bit 5, vertical scaler phase field mode, if true, disable the opposite parity line output, more bandwith needed if output 1080i
+// Bit 4 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for vertical scaler
+// Bit 2:0 vertical scaler bank length
+#define DI_SC_MISC ((0x3769 << 2) + 0xff000000)
+#define DI_HSC_PHASE_CTRL1 ((0x376a << 2) + 0xff000000)
+#define DI_HSC_INI_PAT_CTRL ((0x376b << 2) + 0xff000000)
+#define DI_SC_GCLK_CTRL ((0x376c << 2) + 0xff000000)
+#define DI_SC_HOLD_LINE ((0x376d << 2) + 0xff000000)
+#define DI_HDR_IN_HSIZE ((0x376e << 2) + 0xff000000)
+#define DI_HDR_IN_VSIZE ((0x376f << 2) + 0xff000000)
+#define DI_HDR_OFFSET 0x70
+#define DI_HDR2_CTRL ((0x3770 << 2) + 0xff000000)
+#define DI_HDR2_CLK_GATE ((0x3771 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF00_01 ((0x3772 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF02_10 ((0x3773 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF11_12 ((0x3774 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF20_21 ((0x3775 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF22 ((0x3776 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF30_31 ((0x3777 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF32_40 ((0x3778 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF41_42 ((0x3779 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_OFFSET0_1 ((0x377a << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_OFFSET2 ((0x377b << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x377c << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_PRE_OFFSET2 ((0x377d << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF00_01 ((0x377e << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF02_10 ((0x377f << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF11_12 ((0x3780 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF20_21 ((0x3781 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF22 ((0x3782 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF30_31 ((0x3783 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF32_40 ((0x3784 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF41_42 ((0x3785 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_OFFSET0_1 ((0x3786 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_OFFSET2 ((0x3787 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x3788 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_PRE_OFFSET2 ((0x3789 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_CLIP ((0x378a << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_CLIP ((0x378b << 2) + 0xff000000)
+#define DI_HDR2_CGAIN_OFFT ((0x378c << 2) + 0xff000000)
+#define DI_EOTF_LUT_ADDR_PORT ((0x378e << 2) + 0xff000000)
+#define DI_EOTF_LUT_DATA_PORT ((0x378f << 2) + 0xff000000)
+#define DI_OETF_LUT_ADDR_PORT ((0x3790 << 2) + 0xff000000)
+#define DI_OETF_LUT_DATA_PORT ((0x3791 << 2) + 0xff000000)
+#define DI_CGAIN_LUT_ADDR_PORT ((0x3792 << 2) + 0xff000000)
+#define DI_CGAIN_LUT_DATA_PORT ((0x3793 << 2) + 0xff000000)
+#define DI_HDR2_CGAIN_COEF0 ((0x3794 << 2) + 0xff000000)
+#define DI_HDR2_CGAIN_COEF1 ((0x3795 << 2) + 0xff000000)
+#define DI_OGAIN_LUT_ADDR_PORT ((0x3796 << 2) + 0xff000000)
+#define DI_OGAIN_LUT_DATA_PORT ((0x3797 << 2) + 0xff000000)
+#define DI_HDR2_ADPS_CTRL ((0x3798 << 2) + 0xff000000)
+#define DI_HDR2_ADPS_ALPHA0 ((0x3799 << 2) + 0xff000000)
+#define DI_HDR2_ADPS_ALPHA1 ((0x379a << 2) + 0xff000000)
+#define DI_HDR2_ADPS_BETA0 ((0x379b << 2) + 0xff000000)
+#define DI_HDR2_ADPS_BETA1 ((0x379c << 2) + 0xff000000)
+#define DI_HDR2_ADPS_BETA2 ((0x379d << 2) + 0xff000000)
+#define DI_HDR2_ADPS_COEF0 ((0x379e << 2) + 0xff000000)
+#define DI_HDR2_ADPS_COEF1 ((0x379f << 2) + 0xff000000)
+#define DI_HDR2_GMUT_CTRL ((0x37a0 << 2) + 0xff000000)
+#define DI_HDR2_GMUT_COEF0 ((0x37a1 << 2) + 0xff000000)
+#define DI_HDR2_GMUT_COEF1 ((0x37a2 << 2) + 0xff000000)
+#define DI_HDR2_GMUT_COEF2 ((0x37a3 << 2) + 0xff000000)
+#define DI_HDR2_GMUT_COEF3 ((0x37a4 << 2) + 0xff000000)
+#define DI_HDR2_GMUT_COEF4 ((0x37a5 << 2) + 0xff000000)
+#define DI_HDR2_PIPE_CTRL1 ((0x37a6 << 2) + 0xff000000)
+#define DI_HDR2_PIPE_CTRL2 ((0x37a7 << 2) + 0xff000000)
+#define DI_HDR2_PIPE_CTRL3 ((0x37a8 << 2) + 0xff000000)
+#define DI_HDR2_PROC_WIN1 ((0x37a9 << 2) + 0xff000000)
+#define DI_HDR2_PROC_WIN2 ((0x37aa << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_EN_CTRL ((0x37ab << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_EN_CTRL ((0x37ac << 2) + 0xff000000)
+#define DI_HDR2_HIST_CTRL ((0x37ad << 2) + 0xff000000)
+#define DI_HDR2_HIST_H_START_END ((0x37ae << 2) + 0xff000000)
+#define DI_HDR2_HIST_V_START_END ((0x37af << 2) + 0xff000000)
+#define DI_HDR2_HIST_RD ((0x378d << 2) + 0xff000000)
+#define DI_VIU_HSC_WIDTHM1 ((0x37b0 << 2) + 0xff000000)
+#define DI_VIU_HSC_PHASE_STEP ((0x37b1 << 2) + 0xff000000)
+#define DI_VIU_HSC_CTRL ((0x37b2 << 2) + 0xff000000)
+#define DI_VIU_HSC_PHASE_CTRL ((0x37b3 << 2) + 0xff000000)
+#define DI_VIU_HSC_COEF ((0x37b4 << 2) + 0xff000000)
+#define DI_VIU_HSC_COEF_IDX ((0x37b5 << 2) + 0xff000000)
+#define DI_DITH_CTRL ((0x3744 << 2) + 0xff000000)
+#define DI_DITH_LUT_1 ((0x3745 << 2) + 0xff000000)
+#define DI_DITH_LUT_2 ((0x3746 << 2) + 0xff000000)
+#define DI_DITH_LUT_3 ((0x3747 << 2) + 0xff000000)
+#define DI_DITH_LUT_4 ((0x3748 << 2) + 0xff000000)
+#define DI_DITH_LUT_5 ((0x3749 << 2) + 0xff000000)
+#define DI_DITH_LUT_6 ((0x374a << 2) + 0xff000000)
+#define DI_DITH_LUT_7 ((0x374b << 2) + 0xff000000)
+#define DI_DITH_LUT_8 ((0x374c << 2) + 0xff000000)
+#define DI_DITH_LUT_9 ((0x374d << 2) + 0xff000000)
+#define DI_DITH_LUT_10 ((0x37b6 << 2) + 0xff000000)
+#define DI_DITH_LUT_11 ((0x37b7 << 2) + 0xff000000)
+#define DI_DITH_LUT_12 ((0x37b8 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: di_scale_regs.h
+//
+// 0xc0~0xff
+//
+// Reading file: di_arb_sub_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DI_SUB_RDARB_MODE ((0x37c0 << 2) + 0xff000000)
+#define DI_SUB_RDARB_REQEN_SLV ((0x37c1 << 2) + 0xff000000)
+#define DI_SUB_RDARB_WEIGH0_SLV ((0x37c2 << 2) + 0xff000000)
+#define DI_SUB_RDARB_WEIGH1_SLV ((0x37c3 << 2) + 0xff000000)
+#define DI_SUB_RDARB_UGT ((0x37c4 << 2) + 0xff000000)
+#define DI_SUB_RDARB_LIMT0 ((0x37c5 << 2) + 0xff000000)
+#define DI_SUB_WRARB_MODE ((0x37c6 << 2) + 0xff000000)
+#define DI_SUB_WRARB_REQEN_SLV ((0x37c7 << 2) + 0xff000000)
+#define DI_SUB_WRARB_WEIGH0_SLV ((0x37c8 << 2) + 0xff000000)
+#define DI_SUB_WRARB_WEIGH1_SLV ((0x37c9 << 2) + 0xff000000)
+#define DI_SUB_WRARB_UGT ((0x37ca << 2) + 0xff000000)
+#define DI_SUB_RDWR_ARB_STATUS ((0x37cb << 2) + 0xff000000)
+#define DI_SUB_ARB_DBG_CTRL ((0x37cc << 2) + 0xff000000)
+#define DI_SUB_ARB_DBG_STAT ((0x37cd << 2) + 0xff000000)
+#define CONTRD_CTRL1 ((0x37d0 << 2) + 0xff000000)
+#define CONTRD_CTRL2 ((0x37d1 << 2) + 0xff000000)
+#define CONTRD_SCOPE_X ((0x37d2 << 2) + 0xff000000)
+#define CONTRD_SCOPE_Y ((0x37d3 << 2) + 0xff000000)
+#define CONTRD_RO_STAT ((0x37d4 << 2) + 0xff000000)
+#define CONT2RD_CTRL1 ((0x37d5 << 2) + 0xff000000)
+#define CONT2RD_CTRL2 ((0x37d6 << 2) + 0xff000000)
+#define CONT2RD_SCOPE_X ((0x37d7 << 2) + 0xff000000)
+#define CONT2RD_SCOPE_Y ((0x37d8 << 2) + 0xff000000)
+#define CONT2RD_RO_STAT ((0x37d9 << 2) + 0xff000000)
+#define MTNRD_CTRL1 ((0x37da << 2) + 0xff000000)
+#define MTNRD_CTRL2 ((0x37db << 2) + 0xff000000)
+#define MTNRD_SCOPE_X ((0x37dc << 2) + 0xff000000)
+#define MTNRD_SCOPE_Y ((0x37dd << 2) + 0xff000000)
+#define MTNRD_RO_STAT ((0x37de << 2) + 0xff000000)
+#define MCVECRD_CTRL1 ((0x37df << 2) + 0xff000000)
+#define MCVECRD_CTRL2 ((0x37e0 << 2) + 0xff000000)
+#define MCVECRD_SCOPE_X ((0x37e1 << 2) + 0xff000000)
+#define MCVECRD_SCOPE_Y ((0x37e2 << 2) + 0xff000000)
+#define MCVECRD_RO_STAT ((0x37e3 << 2) + 0xff000000)
+#define MCINFRD_CTRL1 ((0x37e4 << 2) + 0xff000000)
+#define MCINFRD_CTRL2 ((0x37e5 << 2) + 0xff000000)
+#define MCINFRD_SCOPE_X ((0x37e6 << 2) + 0xff000000)
+#define MCINFRD_SCOPE_Y ((0x37e7 << 2) + 0xff000000)
+#define MCINFRD_RO_STAT ((0x37e8 << 2) + 0xff000000)
+#define CONTWR_X ((0x37e9 << 2) + 0xff000000)
+#define CONTWR_Y ((0x37ea << 2) + 0xff000000)
+#define CONTWR_CTRL ((0x37eb << 2) + 0xff000000)
+#define CONTWR_CAN_SIZE ((0x37ec << 2) + 0xff000000)
+#define MTNWR_X ((0x37ed << 2) + 0xff000000)
+#define MTNWR_Y ((0x37ee << 2) + 0xff000000)
+#define MTNWR_CTRL ((0x37ef << 2) + 0xff000000)
+#define MTNWR_CAN_SIZE ((0x37f0 << 2) + 0xff000000)
+#define MCVECWR_X ((0x37f1 << 2) + 0xff000000)
+#define MCVECWR_Y ((0x37f2 << 2) + 0xff000000)
+#define MCVECWR_CTRL ((0x37f3 << 2) + 0xff000000)
+#define MCVECWR_CAN_SIZE ((0x37f4 << 2) + 0xff000000)
+#define MCINFWR_X ((0x37f5 << 2) + 0xff000000)
+#define MCINFWR_Y ((0x37f6 << 2) + 0xff000000)
+#define MCINFWR_CTRL ((0x37f7 << 2) + 0xff000000)
+#define MCINFWR_CAN_SIZE ((0x37f8 << 2) + 0xff000000)
+#define NRDSWR_X ((0x37f9 << 2) + 0xff000000)
+#define NRDSWR_Y ((0x37fa << 2) + 0xff000000)
+#define NRDSWR_CTRL ((0x37fb << 2) + 0xff000000)
+#define NRDSWR_CAN_SIZE ((0x37fc << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: di_arb_sub_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_madc_regs.h
+//
+//
+// Reading file: vpp_hdr2_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: VPP_HDR2_VCBUS_BASE = 0x38
+// -----------------------------------------------
+#define VD1_HDR2_OFFSET 0x00
+#define VD2_HDR2_OFFSET 0x50
+#define OSD1_HDR2_OFFSET 0xa0
+//`include "hdr2_top_reg.h"
+//vd1 0x00 - -x35
+#define VD1_HDR2_CTRL ((0x3800 << 2) + 0xff000000)
+#define VD1_HDR2_CLK_GATE ((0x3801 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF00_01 ((0x3802 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF02_10 ((0x3803 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF11_12 ((0x3804 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF20_21 ((0x3805 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF22 ((0x3806 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF30_31 ((0x3807 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF32_40 ((0x3808 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF41_42 ((0x3809 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_OFFSET0_1 ((0x380a << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_OFFSET2 ((0x380b << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x380c << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_PRE_OFFSET2 ((0x380d << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF00_01 ((0x380e << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF02_10 ((0x380f << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF11_12 ((0x3810 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF20_21 ((0x3811 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF22 ((0x3812 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF30_31 ((0x3813 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF32_40 ((0x3814 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF41_42 ((0x3815 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_OFFSET0_1 ((0x3816 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_OFFSET2 ((0x3817 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x3818 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_PRE_OFFSET2 ((0x3819 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_CLIP ((0x381a << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_CLIP ((0x381b << 2) + 0xff000000)
+#define VD1_HDR2_CGAIN_OFFT ((0x381c << 2) + 0xff000000)
+#define VD1_EOTF_LUT_ADDR_PORT ((0x381e << 2) + 0xff000000)
+#define VD1_EOTF_LUT_DATA_PORT ((0x381f << 2) + 0xff000000)
+#define VD1_OETF_LUT_ADDR_PORT ((0x3820 << 2) + 0xff000000)
+#define VD1_OETF_LUT_DATA_PORT ((0x3821 << 2) + 0xff000000)
+#define VD1_CGAIN_LUT_ADDR_PORT ((0x3822 << 2) + 0xff000000)
+#define VD1_CGAIN_LUT_DATA_PORT ((0x3823 << 2) + 0xff000000)
+#define VD1_HDR2_CGAIN_COEF0 ((0x3824 << 2) + 0xff000000)
+#define VD1_HDR2_CGAIN_COEF1 ((0x3825 << 2) + 0xff000000)
+#define VD1_OGAIN_LUT_ADDR_PORT ((0x3826 << 2) + 0xff000000)
+#define VD1_OGAIN_LUT_DATA_PORT ((0x3827 << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_CTRL ((0x3828 << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_ALPHA0 ((0x3829 << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_ALPHA1 ((0x382a << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_BETA0 ((0x382b << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_BETA1 ((0x382c << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_BETA2 ((0x382d << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_COEF0 ((0x382e << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_COEF1 ((0x382f << 2) + 0xff000000)
+#define VD1_HDR2_GMUT_CTRL ((0x3830 << 2) + 0xff000000)
+#define VD1_HDR2_GMUT_COEF0 ((0x3831 << 2) + 0xff000000)
+#define VD1_HDR2_GMUT_COEF1 ((0x3832 << 2) + 0xff000000)
+#define VD1_HDR2_GMUT_COEF2 ((0x3833 << 2) + 0xff000000)
+#define VD1_HDR2_GMUT_COEF3 ((0x3834 << 2) + 0xff000000)
+#define VD1_HDR2_GMUT_COEF4 ((0x3835 << 2) + 0xff000000)
+#define VD1_HDR2_PIPE_CTRL1 ((0x3836 << 2) + 0xff000000)
+#define VD1_HDR2_PIPE_CTRL2 ((0x3837 << 2) + 0xff000000)
+#define VD1_HDR2_PIPE_CTRL3 ((0x3838 << 2) + 0xff000000)
+#define VD1_HDR2_PROC_WIN1 ((0x3839 << 2) + 0xff000000)
+#define VD1_HDR2_PROC_WIN2 ((0x383a << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_EN_CTRL ((0x383b << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_EN_CTRL ((0x383c << 2) + 0xff000000)
+#define VD1_HDR2_HIST_CTRL ((0x383d << 2) + 0xff000000)
+#define VD1_HDR2_HIST_H_START_END ((0x383e << 2) + 0xff000000)
+#define VD1_HDR2_HIST_V_START_END ((0x383f << 2) + 0xff000000)
+#define VD1_HDR2_HIST_RD ((0x381d << 2) + 0xff000000)
+//vd2 0x50 - 0x85
+#define VD2_HDR2_CTRL ((0x3850 << 2) + 0xff000000)
+#define VD2_HDR2_CLK_GATE ((0x3851 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF00_01 ((0x3852 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF02_10 ((0x3853 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF11_12 ((0x3854 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF20_21 ((0x3855 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF22 ((0x3856 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF30_31 ((0x3857 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF32_40 ((0x3858 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF41_42 ((0x3859 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_OFFSET0_1 ((0x385a << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_OFFSET2 ((0x385b << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x385c << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_PRE_OFFSET2 ((0x385d << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF00_01 ((0x385e << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF02_10 ((0x385f << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF11_12 ((0x3860 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF20_21 ((0x3861 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF22 ((0x3862 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF30_31 ((0x3863 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF32_40 ((0x3864 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF41_42 ((0x3865 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_OFFSET0_1 ((0x3866 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_OFFSET2 ((0x3867 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x3868 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_PRE_OFFSET2 ((0x3869 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_CLIP ((0x386a << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_CLIP ((0x386b << 2) + 0xff000000)
+#define VD2_HDR2_CGAIN_OFFT ((0x386c << 2) + 0xff000000)
+#define VD2_EOTF_LUT_ADDR_PORT ((0x386e << 2) + 0xff000000)
+#define VD2_EOTF_LUT_DATA_PORT ((0x386f << 2) + 0xff000000)
+#define VD2_OETF_LUT_ADDR_PORT ((0x3870 << 2) + 0xff000000)
+#define VD2_OETF_LUT_DATA_PORT ((0x3871 << 2) + 0xff000000)
+#define VD2_CGAIN_LUT_ADDR_PORT ((0x3872 << 2) + 0xff000000)
+#define VD2_CGAIN_LUT_DATA_PORT ((0x3873 << 2) + 0xff000000)
+#define VD2_HDR2_CGAIN_COEF0 ((0x3874 << 2) + 0xff000000)
+#define VD2_HDR2_CGAIN_COEF1 ((0x3875 << 2) + 0xff000000)
+#define VD2_OGAIN_LUT_ADDR_PORT ((0x3876 << 2) + 0xff000000)
+#define VD2_OGAIN_LUT_DATA_PORT ((0x3877 << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_CTRL ((0x3878 << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_ALPHA0 ((0x3879 << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_ALPHA1 ((0x387a << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_BETA0 ((0x387b << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_BETA1 ((0x387c << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_BETA2 ((0x387d << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_COEF0 ((0x387e << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_COEF1 ((0x387f << 2) + 0xff000000)
+#define VD2_HDR2_GMUT_CTRL ((0x3880 << 2) + 0xff000000)
+#define VD2_HDR2_GMUT_COEF0 ((0x3881 << 2) + 0xff000000)
+#define VD2_HDR2_GMUT_COEF1 ((0x3882 << 2) + 0xff000000)
+#define VD2_HDR2_GMUT_COEF2 ((0x3883 << 2) + 0xff000000)
+#define VD2_HDR2_GMUT_COEF3 ((0x3884 << 2) + 0xff000000)
+#define VD2_HDR2_GMUT_COEF4 ((0x3885 << 2) + 0xff000000)
+#define VD2_HDR2_PIPE_CTRL1 ((0x3886 << 2) + 0xff000000)
+#define VD2_HDR2_PIPE_CTRL2 ((0x3887 << 2) + 0xff000000)
+#define VD2_HDR2_PIPE_CTRL3 ((0x3888 << 2) + 0xff000000)
+#define VD2_HDR2_PROC_WIN1 ((0x3889 << 2) + 0xff000000)
+#define VD2_HDR2_PROC_WIN2 ((0x388a << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_EN_CTRL ((0x388b << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_EN_CTRL ((0x388c << 2) + 0xff000000)
+#define VD2_HDR2_HIST_CTRL ((0x388d << 2) + 0xff000000)
+#define VD2_HDR2_HIST_H_START_END ((0x388e << 2) + 0xff000000)
+#define VD2_HDR2_HIST_V_START_END ((0x388f << 2) + 0xff000000)
+#define VD2_HDR2_HIST_RD ((0x386d << 2) + 0xff000000)
+//osd1 0xa0 - 0xd5
+#define OSD1_HDR2_CTRL ((0x38a0 << 2) + 0xff000000)
+#define OSD1_HDR2_CLK_GATE ((0x38a1 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF00_01 ((0x38a2 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF02_10 ((0x38a3 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF11_12 ((0x38a4 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF20_21 ((0x38a5 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF22 ((0x38a6 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF30_31 ((0x38a7 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF32_40 ((0x38a8 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF41_42 ((0x38a9 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_OFFSET0_1 ((0x38aa << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_OFFSET2 ((0x38ab << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x38ac << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_PRE_OFFSET2 ((0x38ad << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF00_01 ((0x38ae << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF02_10 ((0x38af << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF11_12 ((0x38b0 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF20_21 ((0x38b1 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF22 ((0x38b2 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF30_31 ((0x38b3 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF32_40 ((0x38b4 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF41_42 ((0x38b5 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_OFFSET0_1 ((0x38b6 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_OFFSET2 ((0x38b7 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x38b8 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_PRE_OFFSET2 ((0x38b9 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_CLIP ((0x38ba << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_CLIP ((0x38bb << 2) + 0xff000000)
+#define OSD1_HDR2_CGAIN_OFFT ((0x38bc << 2) + 0xff000000)
+#define OSD1_EOTF_LUT_ADDR_PORT ((0x38be << 2) + 0xff000000)
+#define OSD1_EOTF_LUT_DATA_PORT ((0x38bf << 2) + 0xff000000)
+#define OSD1_OETF_LUT_ADDR_PORT ((0x38c0 << 2) + 0xff000000)
+#define OSD1_OETF_LUT_DATA_PORT ((0x38c1 << 2) + 0xff000000)
+#define OSD1_CGAIN_LUT_ADDR_PORT ((0x38c2 << 2) + 0xff000000)
+#define OSD1_CGAIN_LUT_DATA_PORT ((0x38c3 << 2) + 0xff000000)
+#define OSD1_HDR2_CGAIN_COEF0 ((0x38c4 << 2) + 0xff000000)
+#define OSD1_HDR2_CGAIN_COEF1 ((0x38c5 << 2) + 0xff000000)
+#define OSD1_OGAIN_LUT_ADDR_PORT ((0x38c6 << 2) + 0xff000000)
+#define OSD1_OGAIN_LUT_DATA_PORT ((0x38c7 << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_CTRL ((0x38c8 << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_ALPHA0 ((0x38c9 << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_ALPHA1 ((0x38ca << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_BETA0 ((0x38cb << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_BETA1 ((0x38cc << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_BETA2 ((0x38cd << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_COEF0 ((0x38ce << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_COEF1 ((0x38cf << 2) + 0xff000000)
+#define OSD1_HDR2_GMUT_CTRL ((0x38d0 << 2) + 0xff000000)
+#define OSD1_HDR2_GMUT_COEF0 ((0x38d1 << 2) + 0xff000000)
+#define OSD1_HDR2_GMUT_COEF1 ((0x38d2 << 2) + 0xff000000)
+#define OSD1_HDR2_GMUT_COEF2 ((0x38d3 << 2) + 0xff000000)
+#define OSD1_HDR2_GMUT_COEF3 ((0x38d4 << 2) + 0xff000000)
+#define OSD1_HDR2_GMUT_COEF4 ((0x38d5 << 2) + 0xff000000)
+#define OSD1_HDR2_PIPE_CTRL1 ((0x38d6 << 2) + 0xff000000)
+#define OSD1_HDR2_PIPE_CTRL2 ((0x38d7 << 2) + 0xff000000)
+#define OSD1_HDR2_PIPE_CTRL3 ((0x38d8 << 2) + 0xff000000)
+#define OSD1_HDR2_PROC_WIN1 ((0x38d9 << 2) + 0xff000000)
+#define OSD1_HDR2_PROC_WIN2 ((0x38da << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_EN_CTRL ((0x38db << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_EN_CTRL ((0x38dc << 2) + 0xff000000)
+#define OSD1_HDR2_HIST_CTRL ((0x38dd << 2) + 0xff000000)
+#define OSD1_HDR2_HIST_H_START_END ((0x38de << 2) + 0xff000000)
+#define OSD1_HDR2_HIST_V_START_END ((0x38df << 2) + 0xff000000)
+#define OSD1_HDR2_HIST_RD ((0x38bd << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_hdr2_regs.h
+//
+//
+// Reading file: vpp_misc_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: VPP_MISC_VCBUS_BASE = 0x39
+// -----------------------------------------------
+//0x01-0a
+//
+// Reading file: vpp_vd2_mat_3x3_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VPP_VD2_MATRIX_COEF00_01 ((0x3901 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_COEF02_10 ((0x3902 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_COEF11_12 ((0x3903 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_COEF20_21 ((0x3904 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_COEF22 ((0x3905 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_OFFSET0_1 ((0x3906 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_OFFSET2 ((0x3907 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_CLIP ((0x3908 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_PRE_OFFSET0_1 ((0x3909 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_PRE_OFFSET2 ((0x390a << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_EN_CTRL ((0x390b << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_vd2_mat_3x3_regs.h
+//
+//0x10-1c
+//
+// Reading file: vpp_osd1_mat_3x5_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VPP_OSD1_MATRIX_COEF00_01 ((0x3910 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef00 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef01 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF02_10 ((0x3911 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef02 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef10 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF11_12 ((0x3912 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef11 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef12 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF20_21 ((0x3913 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef20 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef21 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF22 ((0x3914 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 coef22 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF13_14 ((0x3915 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef13 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef14 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF23_24 ((0x3916 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef23 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef24 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF15_25 ((0x3917 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef15 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef25 //signed , default = 0
+#define VPP_OSD1_MATRIX_CLIP ((0x3918 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:8 comp_thrd0 // signed ,default == 0, mat clip enable
+//Bit 7:5 conv_rs // unsigned ,default == 0, mat rs
+//Bit 4:3 clmod // unsigned ,default == 0, mat clmod
+#define VPP_OSD1_MATRIX_OFFSET0_1 ((0x3919 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 offset0 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 offset1 //signed , default = 0
+#define VPP_OSD1_MATRIX_OFFSET2 ((0x391a << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 offset2 //signed , default = 0
+#define VPP_OSD1_MATRIX_PRE_OFFSET0_1 ((0x391b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 pre_offset0 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 pre_offset1 //signed , default = 0
+#define VPP_OSD1_MATRIX_PRE_OFFSET2 ((0x391c << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 pre_offset2 //signed , default = 0
+#define VPP_OSD1_MATRIX_EN_CTRL ((0x391d << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_osd1_mat_3x5_regs.h
+//
+//0x20-2c
+//
+// Reading file: vpp_osd2_mat_3x5_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VPP_OSD2_MATRIX_COEF00_01 ((0x3920 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef00 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef01 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF02_10 ((0x3921 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef02 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef10 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF11_12 ((0x3922 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef11 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef12 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF20_21 ((0x3923 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef20 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef21 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF22 ((0x3924 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 coef22 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF13_14 ((0x3925 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef13 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef14 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF23_24 ((0x3926 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef23 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef24 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF15_25 ((0x3927 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef15 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef25 //signed , default = 0
+#define VPP_OSD2_MATRIX_CLIP ((0x3928 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:8 comp_thrd0 // signed ,default == 0, mat clip enable
+//Bit 7:5 conv_rs // unsigned ,default == 0, mat rs
+//Bit 4:3 clmod // unsigned ,default == 0, mat clmod
+#define VPP_OSD2_MATRIX_OFFSET0_1 ((0x3929 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 offset0 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 offset1 //signed , default = 0
+#define VPP_OSD2_MATRIX_OFFSET2 ((0x392a << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 offset2 //signed , default = 0
+#define VPP_OSD2_MATRIX_PRE_OFFSET0_1 ((0x392b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 pre_offset0 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 pre_offset1 //signed , default = 0
+#define VPP_OSD2_MATRIX_PRE_OFFSET2 ((0x392c << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 pre_offset2 //signed , default = 0
+#define VPP_OSD2_MATRIX_EN_CTRL ((0x392d << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_osd2_mat_3x5_regs.h
+//
+//0x30-3c
+//`include "vpp_post_mat_3x5_regs.h"
+//0x43-0x5b
+//
+// Reading file: vpp_vd2_scale_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VD2_SCALE_COEF_IDX ((0x3943 << 2) + 0xff000000)
+#define VD2_SCALE_COEF ((0x3944 << 2) + 0xff000000)
+#define VD2_VSC_REGION12_STARTP ((0x3945 << 2) + 0xff000000)
+#define VD2_VSC_REGION34_STARTP ((0x3946 << 2) + 0xff000000)
+#define VD2_VSC_REGION4_ENDP ((0x3947 << 2) + 0xff000000)
+#define VD2_VSC_START_PHASE_STEP ((0x3948 << 2) + 0xff000000)
+#define VD2_VSC_REGION0_PHASE_SLOPE ((0x3949 << 2) + 0xff000000)
+#define VD2_VSC_REGION1_PHASE_SLOPE ((0x394a << 2) + 0xff000000)
+#define VD2_VSC_REGION3_PHASE_SLOPE ((0x394b << 2) + 0xff000000)
+#define VD2_VSC_REGION4_PHASE_SLOPE ((0x394c << 2) + 0xff000000)
+#define VD2_VSC_PHASE_CTRL ((0x394d << 2) + 0xff000000)
+#define VD2_VSC_INI_PHASE ((0x394e << 2) + 0xff000000)
+#define VD2_HSC_REGION12_STARTP ((0x394f << 2) + 0xff000000)
+#define VD2_HSC_REGION34_STARTP ((0x3950 << 2) + 0xff000000)
+#define VD2_HSC_REGION4_ENDP ((0x3951 << 2) + 0xff000000)
+#define VD2_HSC_START_PHASE_STEP ((0x3952 << 2) + 0xff000000)
+#define VD2_HSC_REGION0_PHASE_SLOPE ((0x3953 << 2) + 0xff000000)
+#define VD2_HSC_REGION1_PHASE_SLOPE ((0x3954 << 2) + 0xff000000)
+#define VD2_HSC_REGION3_PHASE_SLOPE ((0x3955 << 2) + 0xff000000)
+#define VD2_HSC_REGION4_PHASE_SLOPE ((0x3956 << 2) + 0xff000000)
+#define VD2_HSC_PHASE_CTRL ((0x3957 << 2) + 0xff000000)
+#define VD2_SC_MISC ((0x3958 << 2) + 0xff000000)
+#define VD2_SCO_FIFO_CTRL ((0x3959 << 2) + 0xff000000)
+#define VD2_HSC_PHASE_CTRL1 ((0x395a << 2) + 0xff000000)
+#define VD2_HSC_INI_PAT_CTRL ((0x395b << 2) + 0xff000000)
+#define VD2_SC_GCLK_CTRL ((0x395c << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_vd2_scale_regs.h
+//
+#define VPP_PRE_BLEND_CTRL ((0x3960 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:20 hold_lines //unsigned , default = 8'h4
+//Bit 19:16 din_premult_en //unsigned , default = 4'h0
+//Bit 15:0 din_reoder_sel //unsigned , default = 16'h1
+#define VPP_PRE_BLEND_BLEND_DUMMY_DATA ((0x3961 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 blend0_dummy_data_y //unsigned , default = 8'h10
+//Bit 15:8 blend0_dummy_data_cb //unsigned , default = 8'h80
+//Bit 7:0 blend0_dummy_data_cr //unsigned , default = 8'h0
+#define VPP_PRE_BLEND_DUMMY_ALPHA ((0x3962 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:20 blend0_dummy_alpha //unsigned , default = 9'h0
+//Bit 19:11 blend1_dummy_alpha //unsigned , default = 9'h0
+//Bit 8:0 blend2_dummy_alpha //unsigned , default = 9'h0
+#define VPP_PRE_BLEND2_RO_CURRENT_XY ((0x3963 << 2) + 0xff000000)
+//Bit 31:0 ro_blend2_current_xy //unsigned , default = 32'h0
+#define VPP_POST_BLEND_CTRL ((0x3967 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:20 hold_lines //unsigned , default = 8'h4
+//Bit 19:16 din_premult_en //unsigned , default = 4'h0
+//Bit 15:0 din_reoder_sel //unsigned , default = 16'h1
+#define VPP_POST_BLEND_BLEND_DUMMY_DATA ((0x3968 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 blend0_dummy_data_y //unsigned , default = 8'h10
+//Bit 15:8 blend0_dummy_data_cb //unsigned , default = 8'h80
+//Bit 7:0 blend0_dummy_data_cr //unsigned , default = 8'h0
+#define VPP_POST_BLEND_DUMMY_ALPHA ((0x3969 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:20 blend0_dummy_alpha //unsigned , default = 9'h0
+//Bit 19:11 blend1_dummy_alpha //unsigned , default = 9'h0
+//Bit 8:0 blend2_dummy_alpha //unsigned , default = 9'h0
+#define VPP_POST_BLEND2_RO_CURRENT_XY ((0x396a << 2) + 0xff000000)
+//Bit 31:0 ro_blend2_current_xy //unsigned , default = 32'h0
+#define VPP_AFBC_RDARB_MODE ((0x3970 << 2) + 0xff000000)
+#define VPP_AFBC_RDARB_REQEN_SLV ((0x3971 << 2) + 0xff000000)
+#define VPP_AFBC_RDARB_WEIGH0_SLV ((0x3972 << 2) + 0xff000000)
+#define VPP_AFBC_RDWR_ARB_STATUS ((0x3973 << 2) + 0xff000000)
+#define VPP_AFBC_ARB_DBG_CTRL ((0x3974 << 2) + 0xff000000)
+#define VPP_AFBC_ARB_DBG_STAT ((0x3975 << 2) + 0xff000000)
+#define VPP_RDARB_MODE ((0x3978 << 2) + 0xff000000)
+#define VPP_RDARB_REQEN_SLV ((0x3979 << 2) + 0xff000000)
+#define VPP_RDARB_WEIGH0_SLV ((0x397a << 2) + 0xff000000)
+#define VPP_RDARB_WEIGH1_SLV ((0x397b << 2) + 0xff000000)
+#define VPP_RDWR_ARB_STATUS ((0x397c << 2) + 0xff000000)
+#define VPP_ARB_DBG_CTRL ((0x397e << 2) + 0xff000000)
+#define VPP_ARB_DBG_STAT ((0x397f << 2) + 0xff000000)
+//ox80-0x9f & 0xe0-0xef
+//
+// Reading file: vpu_primesl_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define PRIMESL_LUTC_ADDR_PORT ((0x3980 << 2) + 0xff000000)
+#define PRIMESL_LUTC_DATA_PORT ((0x3981 << 2) + 0xff000000)
+#define PRIMESL_LUTP_ADDR_PORT ((0x3982 << 2) + 0xff000000)
+#define PRIMESL_LUTP_DATA_PORT ((0x3983 << 2) + 0xff000000)
+#define PRIMESL_LUTD_ADDR_PORT ((0x3984 << 2) + 0xff000000)
+#define PRIMESL_LUTD_DATA_PORT ((0x3985 << 2) + 0xff000000)
+#define PRIMESL_CTRL0 ((0x3990 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29 legacy_mode_en // unsigned , default = 0 = 'h0
+//Bit 28 clip_en // unsigned , default = 1 = 'h0
+//Bit 27 reserved
+//Bit 26:16 inv_chroma_ratio // unsigned , default = 0 = 'h0,
+//Bit 15 reserved
+//Bit 14: 4 inv_y_ratio // unsigned , default = 0 = 'h0,
+//Bit 3 reg_gclk_ctrl // unsigned , default = 0 = 'h0,
+//Bit 2: 1 gclk_ctrl // unsigned , default = 0 = 'h0,
+//Bit 0 primesl_en // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL1 ((0x3991 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 l_headroom // unsigned , default = 0 = 'h0,
+//Bit 15:10 reserved
+//Bit 9: 0 footroom // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL2 ((0x3992 << 2) + 0xff000000)
+//Bit 31:10 reserved
+//Bit 9: 0 c_headroom // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL3 ((0x3993 << 2) + 0xff000000)
+//Bit 31:16 mub // unsigned , default = 0 = 'h0,
+//Bit 15: 0 mua // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL4 ((0x3994 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 oct_7_1 // signed , default = 0 = 'h0,
+//Bit 15:10 reserved
+//Bit 9: 0 oct_7_0 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL5 ((0x3995 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 oct_7_3 // signed , default = 0 = 'h0,
+//Bit 15:10 reserved
+//Bit 9: 0 oct_7_2 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL6 ((0x3996 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 oct_7_5 // signed , default = 0 = 'h0,
+//Bit 15:10 reserved
+//Bit 9: 0 oct_7_4 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL7 ((0x3997 << 2) + 0xff000000)
+//Bit 31:10 reserved
+//Bit 9: 0 oct_7_6 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL8 ((0x3998 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 d_lut_threshold_3_1 // unsigned , default = 0 = 'h0,
+//Bit 15:13 reserved
+//Bit 12: 0 d_lut_threshold_3_0 // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL9 ((0x3999 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12: 0 d_lut_threshold_3_2 // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL10 ((0x399a << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15:12 d_lut_step_4_3 // unsigned , default = 0 = 'h0,
+//Bit 11: 8 d_lut_step_4_2 // unsigned , default = 0 = 'h0,
+//Bit 7: 4 d_lut_step_4_1 // unsigned , default = 0 = 'h0,
+//Bit 3: 0 d_lut_step_4_0 // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL11 ((0x399b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 rgb2yuv_9_0 // signed , default = 0 = 'h0,
+//Bit 15:13 reserved
+//Bit 12: 0 rgb2yuv_9_1 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL12 ((0x399c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 rgb2yuv_9_2 // signed , default = 0 = 'h0,
+//Bit 15:13 reserved
+//Bit 12: 0 rgb2yuv_9_3 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL13 ((0x399d << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 rgb2yuv_9_4 // signed , default = 0 = 'h0,
+//Bit 15:13 reserved
+//Bit 12: 0 rgb2yuv_9_5 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL14 ((0x399e << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 rgb2yuv_9_6 // signed , default = 0 = 'h0,
+//Bit 15:13 reserved
+//Bit 12: 0 rgb2yuv_9_7 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL15 ((0x399f << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12: 0 rgb2yuv_9_8 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL16 ((0x39e0 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30 byp_s_lut // unsigned , default = 0 = 'h0,
+//Bit 29 byp_d_lut // unsigned , default = 0 = 'h0,
+//Bit 28 byp_mat // unsigned , default = 0 = 'h0,
+//Bit 27 rgb_swap // unsigned , default = 0 = 'h0,
+//Bit 26:24 uv_shift // unsigned , default = 0 = 'h0,
+//Bit 23:22 rgb_shift // unsigned , default = 0 = 'h0,
+//Bit 21:20 rgb_clip // unsigned , default = 3 = 'h3,
+//Bit 19:18 reserved
+//Bit 17:16 rgb_rs // unsigned , default = 0 = 'h0,
+//Bit 15:14 reserved
+//Bit 13: 0 reg_s // signed , default = 1024 = 'h1024,
+#define PRIMESL_OMAT_OFFSET0 ((0x39e1 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 pre_offset0 // unsigned , default = 512 = 'h512
+//Bit 15:12 reserved
+//Bit 11: 0 pre_offset1 // unsigned , default = 512 = 'h512
+#define PRIMESL_OMAT_OFFSET1 ((0x39e2 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 pre_offset2 // unsigned , default = 512 = 'h512
+//Bit 15:12 reserved
+//Bit 11: 0 offset0 // unsigned , default = 256 = 'h256
+#define PRIMESL_OMAT_OFFSET2 ((0x39e3 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 offset1 // unsigned , default = 2048 = 'h2048
+//Bit 15:12 reserved
+//Bit 11: 0 offset2 // unsigned , default = 2048 = 'h2048
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_primesl_regs.h
+//
+//oxa0-0xaf
+//
+// Reading file: vpp_post2_mat_3x5_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VPP_POST2_MATRIX_COEF00_01 ((0x39a0 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef00 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef01 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF02_10 ((0x39a1 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef02 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef10 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF11_12 ((0x39a2 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef11 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef12 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF20_21 ((0x39a3 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef20 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef21 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF22 ((0x39a4 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 coef22 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF13_14 ((0x39a5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef13 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef14 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF23_24 ((0x39a6 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef23 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef24 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF15_25 ((0x39a7 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef15 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef25 //signed , default = 0
+#define VPP_POST2_MATRIX_CLIP ((0x39a8 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:8 comp_thrd0 // signed ,default == 0, mat clip enable
+//Bit 7:5 conv_rs // unsigned ,default == 0, mat rs
+//Bit 4:3 clmod // unsigned ,default == 0, mat clmod
+#define VPP_POST2_MATRIX_OFFSET0_1 ((0x39a9 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 offset0 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 offset1 //signed , default = 0
+#define VPP_POST2_MATRIX_OFFSET2 ((0x39aa << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 offset2 //signed , default = 0
+#define VPP_POST2_MATRIX_PRE_OFFSET0_1 ((0x39ab << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 pre_offset0 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 pre_offset1 //signed , default = 0
+#define VPP_POST2_MATRIX_PRE_OFFSET2 ((0x39ac << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 pre_offset2 //signed , default = 0
+#define VPP_POST2_MATRIX_EN_CTRL ((0x39ad << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_post2_mat_3x5_regs.h
+//
+//0xb0-0xcf
+//
+// Reading file: osd_blend_reg.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VIU_OSD_BLEND_CTRL ((0x39b0 << 2) + 0xff000000)
+//Bit 31:29 hold_lines //unsigned , default = 3'h0
+//Bit 28:27 blend2_premult_en //unsigned , default = 2'h3
+//Bit 26 din0_byp_blend //unsigned , default = 1'h1
+//Bit 25 din2_osd_sel //unsigned , default = 1'h1
+//Bit 24 din3_osd_sel //unsigned , default = 1'h1
+//Bit 23:20 blend_din_en //unsigned , default = 4'h5
+//Bit 19:16 din_premult_en //unsigned , default = 4'h0
+//Bit 15:0 din_reoder_sel //unsigned , default = 16'h2341
+#define VIU_OSD_BLEND_CTRL1 ((0x39c0 << 2) + 0xff000000)
+//Bit 31:6 reserved
+//Bit 5:4 reg_alp_mapping_mode
+//Bit 2:1 reg_div_gclk_en
+//Bit 0 reg_div_alpha_en
+#define VIU_OSD_BLEND_DIN0_SCOPE_H ((0x39b1 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din0_h_end ///unsigned , default = 13'h2d0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din0_h_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN0_SCOPE_V ((0x39b2 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din0_v_end ///unsigned , default = 13'h1e0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din0_v_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN1_SCOPE_H ((0x39b3 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din1_h_end ///unsigned , default = 13'h2d0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din1_h_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN1_SCOPE_V ((0x39b4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din1_v_end ///unsigned , default = 13'h1e0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din1_v_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN2_SCOPE_H ((0x39b5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din2_h_end ///unsigned , default = 13'h2d0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din2_h_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN2_SCOPE_V ((0x39b6 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din2_v_end ///unsigned , default = 13'h1e0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din2_v_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN3_SCOPE_H ((0x39b7 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din3_h_end ///unsigned , default = 13'h2d0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din3_h_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN3_SCOPE_V ((0x39b8 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din3_v_end ///unsigned , default = 13'h1e0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din3_v_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DUMMY_DATA0 ((0x39b9 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 23:16 blend0_dummy_data_y //unsigned , default = 8'h00
+//Bit 15:8 blend0_dummy_data_cb //unsigned , default = 8'h80
+//Bit 7:0 blend0_dummy_data_cr //unsigned , default = 8'h80
+#define VIU_OSD_BLEND_DUMMY_ALPHA ((0x39ba << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:20 blend0_dummy_alpha //unsigned , default = 9'h0
+//Bit 19:11 blend1_dummy_alpha //unsigned , default = 9'h0
+//Bit 8:0 blend2_dummy_alpha //unsigned , default = 9'h0
+#define VIU_OSD_BLEND_BLEND0_SIZE ((0x39bb << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 blend0_vsize //unsigned , default = 13'h1e0
+//Bit 15:13 reserved
+//Bit 12:0 blend0_hsize //unsigned , default = 13'h2d0
+#define VIU_OSD_BLEND_BLEND1_SIZE ((0x39bc << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 blend1_vsize //unsigned , default = 13'h1e0
+//Bit 15:13 reserved
+//Bit 12:0 blend1_hsize ///unsigned , default = 13'h2d0
+//`define VIU_OSD_BLEND_DOUT0_HV_START 8'hbd
+//Bit 31:29 reserved
+//Bit 28:0 osd_blend_dout0_hv_start //unsigned , default = 29'h0
+//`define VIU_OSD_BLEND_DOUT1_HV_START 8'hbe
+//Bit 31:29 reserved
+//Bit 28:0 osd_blend_dout1_hv_start //unsigned , default = 29'h0
+#define VIU_OSD_HOLD_LINE_HIGH_BITS ((0x39c1 << 2) + 0xff000000)
+//Bit 31:8 reserved
+//Bit 7:0 hold_line_high_bits //unsigned , default = 32'h0
+#define VIU_OSD_BLEND_RO_CURRENT_XY ((0x39bf << 2) + 0xff000000)
+//Bit 31:0 ro_blend2_current_xy //unsigned , default = 32'h0
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: osd_blend_reg.h
+//
+#define VPP_LUT3D_CTRL ((0x39d0 << 2) + 0xff000000)
+#define VPP_LUT3D_CBUS2RAM_CTRL ((0x39d1 << 2) + 0xff000000)
+#define VPP_LUT3D_RAM_ADDR ((0x39d2 << 2) + 0xff000000)
+#define VPP_LUT3D_RAM_DATA ((0x39d3 << 2) + 0xff000000)
+#define VPP_GAMMA_CTRL ((0x39d4 << 2) + 0xff000000)
+#define VPP_GAMMA_BIN_ADDR ((0x39d5 << 2) + 0xff000000)
+#define VPP_GAMMA_BIN_DATA ((0x39d6 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_misc_regs.h
+//
+//========================================================================
+// MALI AFBCD
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: VPP_AFBCD0_VCBUS_BASE = 0x3a
+// -----------------------------------------------
+//
+// Reading file: vpp_mali_tx300_afbc_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+ //0x00 - 0x80
+#define VPU_MAFBC_BLOCK_ID ((0x3a00 << 2) + 0xff000000)
+#define VPU_MAFBC_IRQ_RAW_STATUS ((0x3a01 << 2) + 0xff000000)
+#define VPU_MAFBC_IRQ_CLEAR ((0x3a02 << 2) + 0xff000000)
+#define VPU_MAFBC_IRQ_MASK ((0x3a03 << 2) + 0xff000000)
+#define VPU_MAFBC_IRQ_STATUS ((0x3a04 << 2) + 0xff000000)
+#define VPU_MAFBC_COMMAND ((0x3a05 << 2) + 0xff000000)
+#define VPU_MAFBC_STATUS ((0x3a06 << 2) + 0xff000000)
+#define VPU_MAFBC_SURFACE_CFG ((0x3a07 << 2) + 0xff000000)
+#define VPU_MAFBC_AXI_CFG ((0x3a08 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0 ((0x3a10 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0 ((0x3a11 << 2) + 0xff000000)
+#define VPU_MAFBC_FORMAT_SPECIFIER_S0 ((0x3a12 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_WIDTH_S0 ((0x3a13 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_HEIGHT_S0 ((0x3a14 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_START_S0 ((0x3a15 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_END_S0 ((0x3a16 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_START_S0 ((0x3a17 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_END_S0 ((0x3a18 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S0 ((0x3a19 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0 ((0x3a1a << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S0 ((0x3a1b << 2) + 0xff000000)
+#define VPU_MAFBC_PREFETCH_CFG_S0 ((0x3a1c << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_LOW_S0 ((0x3a1d << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_HIGH_S0 ((0x3a1e << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_LOW_S0 ((0x3a1f << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_HIGH_S0 ((0x3a20 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1 ((0x3a30 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S1 ((0x3a31 << 2) + 0xff000000)
+#define VPU_MAFBC_FORMAT_SPECIFIER_S1 ((0x3a32 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_WIDTH_S1 ((0x3a33 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_HEIGHT_S1 ((0x3a34 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_START_S1 ((0x3a35 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_END_S1 ((0x3a36 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_START_S1 ((0x3a37 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_END_S1 ((0x3a38 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S1 ((0x3a39 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S1 ((0x3a3a << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S1 ((0x3a3b << 2) + 0xff000000)
+#define VPU_MAFBC_PREFETCH_CFG_S1 ((0x3a3c << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_LOW_S1 ((0x3a3d << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_HIGH_S1 ((0x3a3e << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_LOW_S1 ((0x3a3f << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_HIGH_S1 ((0x3a40 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2 ((0x3a50 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S2 ((0x3a51 << 2) + 0xff000000)
+#define VPU_MAFBC_FORMAT_SPECIFIER_S2 ((0x3a52 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_WIDTH_S2 ((0x3a53 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_HEIGHT_S2 ((0x3a54 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_START_S2 ((0x3a55 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_END_S2 ((0x3a56 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_START_S2 ((0x3a57 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_END_S2 ((0x3a58 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S2 ((0x3a59 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S2 ((0x3a5a << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S2 ((0x3a5b << 2) + 0xff000000)
+#define VPU_MAFBC_PREFETCH_CFG_S2 ((0x3a5c << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_LOW_S2 ((0x3a5d << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_HIGH_S2 ((0x3a5e << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_LOW_S2 ((0x3a5f << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_HIGH_S2 ((0x3a60 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S3 ((0x3a70 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S3 ((0x3a71 << 2) + 0xff000000)
+#define VPU_MAFBC_FORMAT_SPECIFIER_S3 ((0x3a72 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_WIDTH_S3 ((0x3a73 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_HEIGHT_S3 ((0x3a74 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_START_S3 ((0x3a75 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_END_S3 ((0x3a76 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_START_S3 ((0x3a77 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_END_S3 ((0x3a78 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S3 ((0x3a79 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S3 ((0x3a7a << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S3 ((0x3a7b << 2) + 0xff000000)
+#define VPU_MAFBC_PREFETCH_CFG_S3 ((0x3a7c << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_LOW_S3 ((0x3a7d << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_HIGH_S3 ((0x3a7e << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_LOW_S3 ((0x3a7f << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_HIGH_S3 ((0x3a80 << 2) + 0xff000000)
+ // synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_mali_tx300_afbc_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: VPP_AFBCD1_VCBUS_BASE = 0x3b
+// -----------------------------------------------
+// -----------------------------------------------
+// REG_BASE: VPP_AFBCD2_VCBUS_BASE = 0x3c
+// -----------------------------------------------
+// -----------------------------------------------
+// REG_BASE: VPU_OSDSC_BLD_VCBUS_BASE = 0x3d
+// -----------------------------------------------
+//
+// Reading file: vpu_osdsc_bld_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//vertical scaler phase step
+//Bit 27:0, 4.24 format
+#define OSD2_VSC_PHASE_STEP ((0x3d00 << 2) + 0xff000000)
+//Bit 31:16, botttom vertical scaler initial phase
+//Bit 15:0, top vertical scaler initial phase
+#define OSD2_VSC_INI_PHASE ((0x3d01 << 2) + 0xff000000)
+//Bit 24 osd vertical Scaler enable
+//Bit 23 osd_prog_interlace 0: current field is progressive, 1: current field is interlace
+//Bit 22:21 osd_vsc_double_line_mode, bit1, double input width and half input height, bit0, change line buffer becomes 2 lines
+//Bit 20 osd_vsc_phase0_always_en
+//Bit 19 osd_vsc_nearest_en
+//Bit 17:16 osd_vsc_bot_rpt_l0_num
+//Bit 14:11 osd_vsc_bot_ini_rcv_num
+//Bit 9:8 osd_vsc_top_rpt_l0_num
+//Bit 6:3 osd_vsc_top_ini_rcv_num
+//Bit 2:0 osd_vsc_bank_length
+#define OSD2_VSC_CTRL0 ((0x3d02 << 2) + 0xff000000)
+//horizontal scaler phase step
+//Bit 27:0, 4.24 format
+#define OSD2_HSC_PHASE_STEP ((0x3d03 << 2) + 0xff000000)
+//Bit 31:16, horizontal scaler initial phase1
+//Bit 15:0, horizontal scaler initial phase0
+#define OSD2_HSC_INI_PHASE ((0x3d04 << 2) + 0xff000000)
+//Bit 22 osd horizontal scaler enable
+//Bit 21 osd_hsc_double_pix_mode
+//Bit 20 osd_hsc_phase0_always_en
+//Bit 19 osd_hsc_nearest_en
+//Bit 17:16 osd_hsc_rpt_p0_num1
+//Bit 14:11 osd_hsc_ini_rcv_num1
+//Bit 9:8 osd_hsc_rpt_p0_num0
+//Bit 6:3 osd_hsc_ini_rcv_num0
+//Bit 2:0 osd_hsc_bank_length
+#define OSD2_HSC_CTRL0 ((0x3d05 << 2) + 0xff000000)
+//for 3D quincunx sub-sampling
+//bit 15:8 pattern, each patten 1 bit, from lsb -> msb
+//bit 6:4 pattern start
+//bit 2:0 pattern end
+#define OSD2_HSC_INI_PAT_CTRL ((0x3d06 << 2) + 0xff000000)
+//bit 31:24, componet 0
+//bit 23:16, component 1
+//bit 15:8, component 2
+//bit 7:0 component 3, alpha
+#define OSD2_SC_DUMMY_DATA ((0x3d07 << 2) + 0xff000000)
+//Bit 14 osc_sc_din_osd1_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 13 osc_sc_din_osd2_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 12 osc_sc_dout_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 12 osc_sc_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 11:4 default alpha for vd1 or vd2 if they are selected as the source
+//Bit 3 osd scaler path enable
+//Bit 1:0 osd_sc_sel, 00: select osd1 input, 01: select osd2 input, 10: select vd1 input, 11: select vd2 input after matrix
+#define OSD2_SC_CTRL0 ((0x3d08 << 2) + 0xff000000)
+//Bit 28:16 OSD scaler input width minus 1
+//Bit 12:0 OSD scaler input height minus 1
+#define OSD2_SCI_WH_M1 ((0x3d09 << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output horizontal start
+//Bit 12:0 OSD scaler output horizontal end
+#define OSD2_SCO_H_START_END ((0x3d0a << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output vertical start
+//Bit 12:0 OSD scaler output vertical end
+#define OSD2_SCO_V_START_END ((0x3d0b << 2) + 0xff000000)
+#define OSD2_DB_FLT_CTRL ((0x3d0c << 2) + 0xff000000)
+//Bit 31:27 reserved
+//Bit 26 reg_nrdeband_reset1 // unsigned , default = 1 , 0 : no reload chrm seed 1: reload chrm seed
+//Bit 25 reg_nrdeband_reset0 // unsigned , default = 1 , 0 : no reload luma seed 1: reload luma seed
+//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 , 0 : yuv 1: RGB
+//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
+//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
+//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
+//Bit 16 reserved
+//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
+//Bit 12 reserved
+//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6
+//Bit 8 reserved
+//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 , debanding random hp portion xor, [0] for luma
+//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 , debanding random hp portion xor, [1] for chroma
+//Bit 5 reg_nrdeband_en1 // unsigned , default = 0 , debanding registers, for luma
+//Bit 4 reg_nrdeband_en0 // unsigned , default = 0 , debanding registers, for chroma
+//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+#define OSD2_DB_FLT_CTRL1 ((0x3d0d << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:16 reg_nrdeband_noise_rs // unsigned , default = 2
+//Bit 15:12 reg_nrdeband_randgain // unsigned , default = 8
+//Bit 11 reserved
+//Bit 10: 8 reg_nrdeband_bandrand5 // unsigned , default = 6
+//Bit 7 reserved
+//Bit 6: 4 reg_nrdeband_bandrand4 // unsigned , default = 6
+//Bit 3 reserved
+//Bit 2: 0 reg_nrdeband_bandrand3 // unsigned , default = 6
+#define OSD2_DB_FLT_LUMA_THRD ((0x3d0e << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_luma_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_luma_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_luma_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_luma_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else
+#define OSD2_DB_FLT_CHRM_THRD ((0x3d0f << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_chrm_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_chrm_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_chrm_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_chrm_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif
+#define OSD2_DB_FLT_RANDLUT ((0x3d10 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:21 reg_nrdeband_randslut7 // unsigned , default = 1 rand lut7
+//Bit 20:18 reg_nrdeband_randslut6 // unsigned , default = 1 rand lut6
+//Bit 17:15 reg_nrdeband_randslut5 // unsigned , default = 1 rand lut5
+//Bit 14:12 reg_nrdeband_randslut4 // unsigned , default = 1 rand lut4
+//Bit 11: 9 reg_nrdeband_randslut3 // unsigned , default = 1 rand lut3
+//Bit 8: 6 reg_nrdeband_randslut2 // unsigned , default = 1 rand lut2
+//Bit 5: 3 reg_nrdeband_randslut1 // unsigned , default = 1 rand lut1
+//Bit 2: 0 reg_nrdeband_randslut0 // unsigned , default = 1 rand lut0
+#define OSD2_DB_FLT_PXI_THRD ((0x3d11 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+//Bit 15:10 reserved
+//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+#define OSD2_DB_FLT_SEED_Y ((0x3d12 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 ,debanding noise adding seed for Y. seed[0]= 0x60a52f20; as default
+#define OSD2_DB_FLT_SEED_U ((0x3d13 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 ,debanding noise adding seed for U. seed[0]= 0x60a52f27; as default
+#define OSD2_DB_FLT_SEED_V ((0x3d14 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD2_DB_FLT_SEED3 ((0x3d15 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed3 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD2_DB_FLT_SEED4 ((0x3d16 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed4 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD2_DB_FLT_SEED5 ((0x3d17 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed5 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD2_SCALE_COEF_IDX ((0x3d18 << 2) + 0xff000000)
+//coefficients for vertical filter and horizontal filter
+#define OSD2_SCALE_COEF ((0x3d19 << 2) + 0xff000000)
+#define OSD34_SCALE_COEF_IDX ((0x3d1e << 2) + 0xff000000)
+//coefficients for vertical filter and horizontal filter
+#define OSD34_SCALE_COEF ((0x3d1f << 2) + 0xff000000)
+//vertical scaler phase step
+//Bit 27:0, 4.24 format
+#define OSD34_VSC_PHASE_STEP ((0x3d20 << 2) + 0xff000000)
+//Bit 31:16, botttom vertical scaler initial phase
+//Bit 15:0, top vertical scaler initial phase
+#define OSD34_VSC_INI_PHASE ((0x3d21 << 2) + 0xff000000)
+//Bit 24 osd vertical Scaler enable
+//Bit 23 osd_prog_interlace 0: current field is progressive, 1: current field is interlace
+//Bit 22:21 osd_vsc_double_line_mode, bit1, double input width and half input height, bit0, change line buffer becomes 2 lines
+//Bit 20 osd_vsc_phase0_always_en
+//Bit 19 osd_vsc_nearest_en
+//Bit 17:16 osd_vsc_bot_rpt_l0_num
+//Bit 14:11 osd_vsc_bot_ini_rcv_num
+//Bit 9:8 osd_vsc_top_rpt_l0_num
+//Bit 6:3 osd_vsc_top_ini_rcv_num
+//Bit 2:0 osd_vsc_bank_length
+#define OSD34_VSC_CTRL0 ((0x3d22 << 2) + 0xff000000)
+//horizontal scaler phase step
+//Bit 27:0, 4.24 format
+#define OSD34_HSC_PHASE_STEP ((0x3d23 << 2) + 0xff000000)
+//Bit 31:16, horizontal scaler initial phase1
+//Bit 15:0, horizontal scaler initial phase0
+#define OSD34_HSC_INI_PHASE ((0x3d24 << 2) + 0xff000000)
+//Bit 22 osd horizontal scaler enable
+//Bit 21 osd_hsc_double_pix_mode
+//Bit 20 osd_hsc_phase0_always_en
+//Bit 19 osd_hsc_nearest_en
+//Bit 17:16 osd_hsc_rpt_p0_num1
+//Bit 14:11 osd_hsc_ini_rcv_num1
+//Bit 9:8 osd_hsc_rpt_p0_num0
+//Bit 6:3 osd_hsc_ini_rcv_num0
+//Bit 2:0 osd_hsc_bank_length
+#define OSD34_HSC_CTRL0 ((0x3d25 << 2) + 0xff000000)
+//for 3D quincunx sub-sampling
+//bit 15:8 pattern, each patten 1 bit, from lsb -> msb
+//bit 6:4 pattern start
+//bit 2:0 pattern end
+#define OSD34_HSC_INI_PAT_CTRL ((0x3d26 << 2) + 0xff000000)
+//bit 31:24, componet 0
+//bit 23:16, component 1
+//bit 15:8, component 2
+//bit 7:0 component 3, alpha
+#define OSD34_SC_DUMMY_DATA ((0x3d27 << 2) + 0xff000000)
+//Bit 14 osc_sc_din_osd1_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 13 osc_sc_din_osd2_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 12 osc_sc_dout_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 12 osc_sc_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 11:4 default alpha for vd1 or vd2 if they are selected as the source
+//Bit 3 osd scaler path enable
+//Bit 1:0 osd_sc_sel, 00: select osd1 input, 01: select osd2 input, 10: select vd1 input, 11: select vd2 input after matrix
+#define OSD34_SC_CTRL0 ((0x3d28 << 2) + 0xff000000)
+//Bit 28:16 OSD scaler input width minus 1
+//Bit 12:0 OSD scaler input height minus 1
+#define OSD34_SCI_WH_M1 ((0x3d29 << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output horizontal start
+//Bit 12:0 OSD scaler output horizontal end
+#define OSD34_SCO_H_START_END ((0x3d2a << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output vertical start
+//Bit 12:0 OSD scaler output vertical end
+#define OSD34_SCO_V_START_END ((0x3d2b << 2) + 0xff000000)
+#define OSD34_DB_FLT_CTRL ((0x3d2c << 2) + 0xff000000)
+//Bit 31:27 reserved
+//Bit 26 reg_nrdeband_reset1 // unsigned , default = 1 , 0 : no reload chrm seed 1: reload chrm seed
+//Bit 25 reg_nrdeband_reset0 // unsigned , default = 1 , 0 : no reload luma seed 1: reload luma seed
+//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 , 0 : yuv 1: RGB
+//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
+//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
+//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
+//Bit 16 reserved
+//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
+//Bit 12 reserved
+//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6
+//Bit 8 reserved
+//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 , debanding random hp portion xor, [0] for luma
+//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 , debanding random hp portion xor, [1] for chroma
+//Bit 5 reg_nrdeband_en1 // unsigned , default = 0 , debanding registers, for luma
+//Bit 4 reg_nrdeband_en0 // unsigned , default = 0 , debanding registers, for chroma
+//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+#define OSD34_DB_FLT_CTRL1 ((0x3d2d << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:16 reg_nrdeband_noise_rs // unsigned , default = 2
+//Bit 15:12 reg_nrdeband_randgain // unsigned , default = 8
+//Bit 11 reserved
+//Bit 10: 8 reg_nrdeband_bandrand5 // unsigned , default = 6
+//Bit 7 reserved
+//Bit 6: 4 reg_nrdeband_bandrand4 // unsigned , default = 6
+//Bit 3 reserved
+//Bit 2: 0 reg_nrdeband_bandrand3 // unsigned , default = 6
+#define OSD34_DB_FLT_LUMA_THRD ((0x3d2e << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_luma_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_luma_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_luma_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_luma_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else
+#define OSD34_DB_FLT_CHRM_THRD ((0x3d2f << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_chrm_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_chrm_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_chrm_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_chrm_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif
+#define OSD34_DB_FLT_RANDLUT ((0x3d30 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:21 reg_nrdeband_randslut7 // unsigned , default = 1 rand lut7
+//Bit 20:18 reg_nrdeband_randslut6 // unsigned , default = 1 rand lut6
+//Bit 17:15 reg_nrdeband_randslut5 // unsigned , default = 1 rand lut5
+//Bit 14:12 reg_nrdeband_randslut4 // unsigned , default = 1 rand lut4
+//Bit 11: 9 reg_nrdeband_randslut3 // unsigned , default = 1 rand lut3
+//Bit 8: 6 reg_nrdeband_randslut2 // unsigned , default = 1 rand lut2
+//Bit 5: 3 reg_nrdeband_randslut1 // unsigned , default = 1 rand lut1
+//Bit 2: 0 reg_nrdeband_randslut0 // unsigned , default = 1 rand lut0
+#define OSD34_DB_FLT_PXI_THRD ((0x3d31 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+//Bit 15:10 reserved
+//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+#define OSD34_DB_FLT_SEED_Y ((0x3d32 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 ,debanding noise adding seed for Y. seed[0]= 0x60a52f20; as default
+#define OSD34_DB_FLT_SEED_U ((0x3d33 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 ,debanding noise adding seed for U. seed[0]= 0x60a52f27; as default
+#define OSD34_DB_FLT_SEED_V ((0x3d34 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD34_DB_FLT_SEED3 ((0x3d35 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed3 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD34_DB_FLT_SEED4 ((0x3d36 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed4 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD34_DB_FLT_SEED5 ((0x3d37 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed5 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+// for osd3 & osd4 blend
+#define OSD34_OUT_HSCOPE ((0x3d40 << 2) + 0xff000000)
+#define OSD34_OUT_VSCOPE ((0x3d41 << 2) + 0xff000000)
+#define OSD34_DUMMY_DATA ((0x3d42 << 2) + 0xff000000)
+#define OSD34_BLEND_CTRL0 ((0x3d43 << 2) + 0xff000000)
+#define OSD34_BLEND_CTRL1 ((0x3d44 << 2) + 0xff000000)
+#define OSD34_RO_HV_CNT ((0x3d45 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF00_01 ((0x3d60 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF02_10 ((0x3d61 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF11_12 ((0x3d62 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF20_21 ((0x3d63 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF22 ((0x3d64 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF13_14 ((0x3d65 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF23_24 ((0x3d66 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF15_25 ((0x3d67 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_CLIP ((0x3d68 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_OFFSET0_1 ((0x3d69 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_OFFSET2 ((0x3d6a << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1 ((0x3d6b << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2 ((0x3d6c << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_EN_CTRL ((0x3d6d << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF00_01 ((0x3d70 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF02_10 ((0x3d71 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF11_12 ((0x3d72 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF20_21 ((0x3d73 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF22 ((0x3d74 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF13_14 ((0x3d75 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF23_24 ((0x3d76 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF15_25 ((0x3d77 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_CLIP ((0x3d78 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_OFFSET0_1 ((0x3d79 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_OFFSET2 ((0x3d7a << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1 ((0x3d7b << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2 ((0x3d7c << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_EN_CTRL ((0x3d7d << 2) + 0xff000000)
+#define VIU_OSD3_CTRL_STAT ((0x3d80 << 2) + 0xff000000)
+#define VIU_OSD3_CTRL_STAT2 ((0x3d81 << 2) + 0xff000000)
+#define VIU_OSD3_COLOR_ADDR ((0x3d82 << 2) + 0xff000000)
+#define VIU_OSD3_COLOR ((0x3d83 << 2) + 0xff000000)
+#define VIU_OSD3_TCOLOR_AG0 ((0x3d84 << 2) + 0xff000000)
+#define VIU_OSD3_TCOLOR_AG1 ((0x3d85 << 2) + 0xff000000)
+#define VIU_OSD3_TCOLOR_AG2 ((0x3d86 << 2) + 0xff000000)
+#define VIU_OSD3_TCOLOR_AG3 ((0x3d87 << 2) + 0xff000000)
+#define VIU_OSD3_BLK0_CFG_W0 ((0x3d88 << 2) + 0xff000000)
+#define VIU_OSD3_BLK1_CFG_W0 ((0x3d89 << 2) + 0xff000000)
+#define VIU_OSD3_BLK2_CFG_W0 ((0x3d8a << 2) + 0xff000000)
+#define VIU_OSD3_BLK3_CFG_W0 ((0x3d8b << 2) + 0xff000000)
+#define VIU_OSD3_BLK0_CFG_W1 ((0x3d8c << 2) + 0xff000000)
+#define VIU_OSD3_BLK1_CFG_W1 ((0x3d8d << 2) + 0xff000000)
+#define VIU_OSD3_BLK2_CFG_W1 ((0x3d8e << 2) + 0xff000000)
+#define VIU_OSD3_BLK3_CFG_W1 ((0x3d8f << 2) + 0xff000000)
+#define VIU_OSD3_BLK0_CFG_W2 ((0x3d90 << 2) + 0xff000000)
+#define VIU_OSD3_BLK1_CFG_W2 ((0x3d91 << 2) + 0xff000000)
+#define VIU_OSD3_BLK2_CFG_W2 ((0x3d92 << 2) + 0xff000000)
+#define VIU_OSD3_BLK3_CFG_W2 ((0x3d93 << 2) + 0xff000000)
+#define VIU_OSD3_BLK0_CFG_W3 ((0x3d94 << 2) + 0xff000000)
+#define VIU_OSD3_BLK1_CFG_W3 ((0x3d95 << 2) + 0xff000000)
+#define VIU_OSD3_BLK2_CFG_W3 ((0x3d96 << 2) + 0xff000000)
+#define VIU_OSD3_BLK3_CFG_W3 ((0x3d97 << 2) + 0xff000000)
+#define VIU_OSD3_BLK0_CFG_W4 ((0x3d98 << 2) + 0xff000000)
+#define VIU_OSD3_BLK1_CFG_W4 ((0x3d99 << 2) + 0xff000000)
+#define VIU_OSD3_BLK2_CFG_W4 ((0x3d9a << 2) + 0xff000000)
+#define VIU_OSD3_BLK3_CFG_W4 ((0x3d9b << 2) + 0xff000000)
+#define VIU_OSD3_FIFO_CTRL_STAT ((0x3d9c << 2) + 0xff000000)
+#define VIU_OSD3_TEST_RDDATA ((0x3d9d << 2) + 0xff000000)
+#define VIU_OSD3_PROT_CTRL ((0x3d9e << 2) + 0xff000000)
+#define VIU_OSD3_MALI_UNPACK_CTRL ((0x3d9f << 2) + 0xff000000)
+#define VIU_OSD3_DIMM_CTRL ((0x3da0 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF00_01 ((0x3db0 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF02_10 ((0x3db1 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF11_12 ((0x3db2 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF20_21 ((0x3db3 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF22 ((0x3db4 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF13_14 ((0x3db5 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF23_24 ((0x3db6 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF15_25 ((0x3db7 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_CLIP ((0x3db8 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_OFFSET0_1 ((0x3db9 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_OFFSET2 ((0x3dba << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_PRE_OFFSET0_1 ((0x3dbb << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_PRE_OFFSET2 ((0x3dbc << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_EN_CTRL ((0x3dbd << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_COEF00_01 ((0x3db0 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_COEF02_10 ((0x3db1 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_COEF11_12 ((0x3db2 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_COEF20_21 ((0x3db3 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_COEF22 ((0x3db4 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_COEF13_14 ((0x3db5 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_COEF23_24 ((0x3db6 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_COEF15_25 ((0x3db7 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_CLIP ((0x3db8 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_OFFSET0_1 ((0x3db9 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_OFFSET2 ((0x3dba << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1 ((0x3dbb << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 ((0x3dbc << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_EN_CTRL ((0x3dbd << 2) + 0xff000000)
+#define VIU_OSD4_CTRL_STAT ((0x3dc0 << 2) + 0xff000000)
+#define VIU_OSD4_CTRL_STAT2 ((0x3dc1 << 2) + 0xff000000)
+#define VIU_OSD4_COLOR_ADDR ((0x3dc2 << 2) + 0xff000000)
+#define VIU_OSD4_COLOR ((0x3dc3 << 2) + 0xff000000)
+#define VIU_OSD4_TCOLOR_AG0 ((0x3dc4 << 2) + 0xff000000)
+#define VIU_OSD4_TCOLOR_AG1 ((0x3dc5 << 2) + 0xff000000)
+#define VIU_OSD4_TCOLOR_AG2 ((0x3dc6 << 2) + 0xff000000)
+#define VIU_OSD4_TCOLOR_AG3 ((0x3dc7 << 2) + 0xff000000)
+#define VIU_OSD4_BLK0_CFG_W0 ((0x3dc8 << 2) + 0xff000000)
+#define VIU_OSD4_BLK1_CFG_W0 ((0x3dc9 << 2) + 0xff000000)
+#define VIU_OSD4_BLK2_CFG_W0 ((0x3dca << 2) + 0xff000000)
+#define VIU_OSD4_BLK3_CFG_W0 ((0x3dcb << 2) + 0xff000000)
+#define VIU_OSD4_BLK0_CFG_W1 ((0x3dcc << 2) + 0xff000000)
+#define VIU_OSD4_BLK1_CFG_W1 ((0x3dcd << 2) + 0xff000000)
+#define VIU_OSD4_BLK2_CFG_W1 ((0x3dce << 2) + 0xff000000)
+#define VIU_OSD4_BLK3_CFG_W1 ((0x3dcf << 2) + 0xff000000)
+#define VIU_OSD4_BLK0_CFG_W2 ((0x3dd0 << 2) + 0xff000000)
+#define VIU_OSD4_BLK1_CFG_W2 ((0x3dd1 << 2) + 0xff000000)
+#define VIU_OSD4_BLK2_CFG_W2 ((0x3dd2 << 2) + 0xff000000)
+#define VIU_OSD4_BLK3_CFG_W2 ((0x3dd3 << 2) + 0xff000000)
+#define VIU_OSD4_BLK0_CFG_W3 ((0x3dd4 << 2) + 0xff000000)
+#define VIU_OSD4_BLK1_CFG_W3 ((0x3dd5 << 2) + 0xff000000)
+#define VIU_OSD4_BLK2_CFG_W3 ((0x3dd6 << 2) + 0xff000000)
+#define VIU_OSD4_BLK3_CFG_W3 ((0x3dd7 << 2) + 0xff000000)
+#define VIU_OSD4_BLK0_CFG_W4 ((0x3dd8 << 2) + 0xff000000)
+#define VIU_OSD4_BLK1_CFG_W4 ((0x3dd9 << 2) + 0xff000000)
+#define VIU_OSD4_BLK2_CFG_W4 ((0x3dda << 2) + 0xff000000)
+#define VIU_OSD4_BLK3_CFG_W4 ((0x3ddb << 2) + 0xff000000)
+#define VIU_OSD4_FIFO_CTRL_STAT ((0x3ddc << 2) + 0xff000000)
+#define VIU_OSD4_TEST_RDDATA ((0x3ddd << 2) + 0xff000000)
+#define VIU_OSD4_PROT_CTRL ((0x3dde << 2) + 0xff000000)
+#define VIU_OSD4_MALI_UNPACK_CTRL ((0x3ddf << 2) + 0xff000000)
+#define VIU_OSD4_DIMM_CTRL ((0x3de0 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF00_01 ((0x3df0 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF02_10 ((0x3df1 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF11_12 ((0x3df2 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF20_21 ((0x3df3 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF22 ((0x3df4 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF13_14 ((0x3df5 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF23_24 ((0x3df6 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF15_25 ((0x3df7 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_CLIP ((0x3df8 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_OFFSET0_1 ((0x3df9 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_OFFSET2 ((0x3dfa << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_PRE_OFFSET0_1 ((0x3dfb << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_PRE_OFFSET2 ((0x3dfc << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_EN_CTRL ((0x3dfd << 2) + 0xff000000)
+ // synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_osdsc_bld_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: VPPF_VCBUS_BASE = 0x40
+// -----------------------------------------------
+//
+// Reading file: lc_stts_curve.h
+//
+#define LC_CURVE_CTRL ((0x4000 << 2) + 0xff000000)
+ //Bit 31 :12 reg_lc_misc U RW default = 'h0 None
+ //Bit 11 :10 reserved U RW default = 'h0 None
+ //Bit 9 :8 reg_lc_hist_curve_nodes_hlpf U RW default = 'h1 horizontal lpf of the ram_curve_nodes, 0: no LPF, 1= [1 2 1]; 2: [1 2 2 2 1]/8
+ //Bit 7 :6 reserved U RW default = 'h0 None
+ //Bit 5 :4 reg_lc_hist_curve_nodes_vlpf U RW default = 'h1 vertical lpf of the ram_curve_nodes, 0: no LPF, 1= [1 2 1]; 2: [1 2 2 2 1]/8
+ //Bit 3 :2 reserved U RW default = 'h0 None
+ //Bit 1 reg_lc_blackbar_mute_en U RW default = 'h1 mute the black bar corresponding bin, 0: no mute, 1: mute enable; default=1
+ //Bit 0 reg_lc_curve_en U RW default = 'h1 default=0
+#define LC_CURVE_HV_NUM ((0x4001 << 2) + 0xff000000)
+ //Bit 31 :13 reserved U RW default = 'h0 None
+ //Bit 12 :8 reg_lc_cur_blk_hnum U RW default = 'hc lc processing region number of V, maximum to (STA_LEN_V-1) (0~8), should be same as reg_lc_blk_hnum
+ //Bit 7 :5 reserved U RW default = 'h0 None
+ //Bit 4 :0 reg_lc_cur_blk_vnum U RW default = 'h8 lc processing region number of H, maximum to (STA_LEN_H-1) (0~12), should be same as reg_lc_blk_vnum
+#define LC_CURVE_LMT_RAT ((0x4002 << 2) + 0xff000000)
+ //Bit 31 :16 reserved U RW default = 'h0 None
+ //Bit 15 :8 reg_lmtrat_minmax U RW default = 'h6 x/1024 of amount
+ //Bit 7 :0 reg_lmtrat_valid U RW default = 'h14 x/1024 of amount
+#define LC_CURVE_CONTRAST_LH ((0x4003 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_contrast_low U RW default = 'h10 contrast gain to the lc for dark side, normalized 256 as "1", set adaptive TODO
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_contrast_hig U RW default = 'h18 contrast gain to the lc for bright side, normalized 256 as "1"
+#define LC_CURVE_CONTRAST__LMT_LH ((0x4004 << 2) + 0xff000000)
+ //Bit 31 :24 reg_lc_cntstlmt_low_0 U RW default = 'ha limit for the contrast low, delta_low = MIN(delta_low, MIN( MAX((minBV-min_val)*scl_low/8, lmt_low[0]),lmt_low[1]))
+ //Bit 23 :16 reg_lc_cntstlmt_hig_0 U RW default = 'h14 limit for the contrast high,delta_hig = MIN(delta_hig, MIN( MAX((max_val-maxBV)*scl_hig/8, lmt_hig[0]),lmt_hig[1]))
+ //Bit 15 :8 reg_lc_cntstlmt_low_1 U RW default = 'hff limit for the contrast low, delta_low = MIN(delta_low, MIN( MAX((minBV-min_val)*scl_low/8, lmt_low[0]),lmt_low[1]))
+ //Bit 7 :0 reg_lc_cntstlmt_hig_1 U RW default = 'hff limit for the contrast high,delta_hig = MIN(delta_hig, MIN( MAX((max_val-maxBV)*scl_hig/8, lmt_hig[0]),lmt_hig[1]))
+#define LC_CURVE_CONTRAST_SCL_LH ((0x4005 << 2) + 0xff000000)
+ //Bit 31 :16 reserved U RW default = 'h0 None
+ //Bit 15 :8 reg_lc_cntstscl_low U RW default = 'h40 scale for the contrast low, norm 8 as 1; delta_low = MIN(delta_low, MIN(MAX((minBV-min_val)*scl_low/8, lmt_low[0]),lmt_low[1]))
+ //Bit 7 :0 reg_lc_cntstscl_hig U RW default = 'h20 scale for the contrast high,norm 8 as 1; delta_hig = MIN(delta_hig, MIN(MAX((max_val-maxBV)*scl_hig/8, lmt_hig[0]),lmt_hig[1]))
+#define LC_CURVE_CONTRAST_BVN_LH ((0x4006 << 2) + 0xff000000)
+ //Bit 31 :16 reserved U RW default = 'h0 None
+ //Bit 15 :8 reg_lc_cntstbvn_low U RW default = 'h20 scale to num_m as limit of min_val to minBV distance, to protect mono-color, default = 32; min_val= MAX(min_val, minBV- MAX(num_m-1,0)*bvn_low)
+ //Bit 7 :0 reg_lc_cntstbvn_hig U RW default = 'h20 scale to num_m as limit of max_val to maxBV distance, to protect mono-color, default = 32; min_val= MIN(max_val, maxBV+ MAX(num_m-1,0)*bvn_lo
+#define LC_CURVE_MISC0 ((0x4007 << 2) + 0xff000000)
+ //Bit 31 :20 reserved U RW default = 'h0 None
+ //Bit 19 :16 reg_lc_num_m_coring U RW default = 'h1 coring to num_m, soft coring,default = 2;
+ //Bit 15 :8 reg_lc_vbin_min U RW default = 'h30 4x is min width of valid histogram bin num,
+ //Bit 7 :0 reg_lc_slope_max_face U RW default = 'h38 maximum slope for the pkBin-maxBV range curve to do face protection, normalized to 32 as 1, default= 48
+#define LC_CURVE_YPKBV_RAT ((0x4008 << 2) + 0xff000000)
+ //Bit 31 :24 reg_lc_ypkbv_ratio_0 U RW default = 'h8c x= ratio*(maxBv-minBv)+min_val as low bound of the ypkBV; normalized to 256 as 1
+ //Bit 23 :16 reg_lc_ypkbv_ratio_1 U RW default = 'ha0 x= ratio*(maxBv-minBv)+min_val as low bound of the ypkBV; normalized to 256 as 1
+ //Bit 15 :8 reg_lc_ypkbv_ratio_2 U RW default = 'h78 x= ratio*(maxBv-minBv)+min_val as low bound of the ypkBV; normalized to 256 as 1
+ //Bit 7 :0 reg_lc_ypkbv_ratio_3 U RW default = 'h60 x= ratio*(maxBv-minBv)+min_val as low bound of the ypkBV; normalized to 256 as 1
+#define LC_CURVE_YPKBV_SLP_LMT ((0x4009 << 2) + 0xff000000)
+ //Bit 31 :16 reserved U RW default = 'h0 None
+ //Bit 15 :8 reg_lc_ypkbv_slope_lmt_0 U RW default = 'hc min max slop for the curves to avoid artifacts, [0] for min_slope, [1] for max_slop, e.g.max_slope= limit*(pkBv-minBv)+min_val as high bound of the ypkBV; normalized to 32 as 1
+ //Bit 7 :0 reg_lc_ypkbv_slope_lmt_1 U RW default = 'h60 None
+#define LC_CURVE_YMINVAL_LMT_0_1 ((0x400a << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_0 U RW default = 'h30 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_1 U RW default = 'h50 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMINVAL_LMT_2_3 ((0x400b << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_2 U RW default = 'h78 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_3 U RW default = 'h80 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMINVAL_LMT_4_5 ((0x400c << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_4 U RW default = 'ha0 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_5 U RW default = 'hc4 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMINVAL_LMT_6_7 ((0x400d << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_6 U RW default = 'he0 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_7 U RW default = 'h100 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMINVAL_LMT_8_9 ((0x400e << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_8 U RW default = 'h120 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_9 U RW default = 'h140 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMINVAL_LMT_10_11 ((0x400f << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_10 U RW default = 'h160 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_11 U RW default = 'h190 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMAXVAL_LMT_0_1 ((0x4010 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_0 U RW default = 'h78 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_1 U RW default = 'h96 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_YMAXVAL_LMT_2_3 ((0x4011 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_2 U RW default = 'he6 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_3 U RW default = 'h112 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_YMAXVAL_LMT_4_5 ((0x4012 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_4 U RW default = 'h14a lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_5 U RW default = 'h180 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_YMAXVAL_LMT_6_7 ((0x4013 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_6 U RW default = 'h1d4 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_7 U RW default = 'h200 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_YMAXVAL_LMT_8_9 ((0x4014 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_8 U RW default = 'h240 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_9 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_YMAXVAL_LMT_10_11 ((0x4015 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_10 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_11 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_HISTVLD_THRD ((0x4016 << 2) + 0xff000000)
+ //Bit 31 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_histvld_thrd U RW default = 'h1fa threshold to compare to bin to get number of valid bins
+#define LC_CURVE_BB_MUTE_THRD ((0x4017 << 2) + 0xff000000)
+ //Bit 31 :24 reserved U RW default = 'h0 None
+ //Bit 23 :0 reg_lc_blackbar_mute_thrd U RW default = 'h2a30 1/8 of the region
+#define LC_CURVE_INT_STATUS ((0x4018 << 2) + 0xff000000)
+#define LC_CURVE_RAM_CTRL ((0x4020 << 2) + 0xff000000)
+#define LC_CURVE_RAM_ADDR ((0x4021 << 2) + 0xff000000)
+#define LC_CURVE_RAM_DATA ((0x4022 << 2) + 0xff000000)
+#define LC_CURVE_YMINVAL_LMT_12_13 ((0x4040 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_12 U RW default = 'h160 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_13 U RW default = 'h190 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMINVAL_LMT_14_15 ((0x4041 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_14 U RW default = 'h160 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_15 U RW default = 'h190 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMAXVAL_LMT_12_13 ((0x4042 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_12 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_13 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_YMAXVAL_LMT_14_15 ((0x4043 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_14 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_15 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+//u10, lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV])
+#define LC_CURVE_YPKBV_LMT_0_1 ((0x4044 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_0 U RW default = 'h78 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_1 U RW default = 'h96 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_2_3 ((0x4045 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_2 U RW default = 'he6 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_3 U RW default = 'h112 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_4_5 ((0x4046 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_4 U RW default = 'h14a lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_5 U RW default = 'h180 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_6_7 ((0x4047 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_6 U RW default = 'h1d4 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_7 U RW default = 'h200 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_8_9 ((0x4048 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_8 U RW default = 'h240 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_9 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_10_11 ((0x4049 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_10 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_11 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_12_13 ((0x404a << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_12 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_13 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_14_15 ((0x404b << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_14 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_15 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+//-------------------------------------------------------------
+#define LC_STTS_GCLK_CTRL0 ((0x4028 << 2) + 0xff000000)
+#define LC_STTS_CTRL0 ((0x4029 << 2) + 0xff000000)
+#define LC_STTS_WIDTHM1_HEIGHTM1 ((0x402a << 2) + 0xff000000)
+#define LC_STTS_MATRIX_COEF00_01 ((0x402b << 2) + 0xff000000)
+#define LC_STTS_MATRIX_COEF02_10 ((0x402c << 2) + 0xff000000)
+#define LC_STTS_MATRIX_COEF11_12 ((0x402d << 2) + 0xff000000)
+#define LC_STTS_MATRIX_COEF20_21 ((0x402e << 2) + 0xff000000)
+#define LC_STTS_MATRIX_COEF22 ((0x402f << 2) + 0xff000000)
+#define LC_STTS_MATRIX_OFFSET0_1 ((0x4030 << 2) + 0xff000000)
+#define LC_STTS_MATRIX_OFFSET2 ((0x4031 << 2) + 0xff000000)
+#define LC_STTS_MATRIX_PRE_OFFSET0_1 ((0x4032 << 2) + 0xff000000)
+#define LC_STTS_MATRIX_PRE_OFFSET2 ((0x4033 << 2) + 0xff000000)
+#define LC_STTS_MATRIX_HL_COLOR ((0x4034 << 2) + 0xff000000)
+#define LC_STTS_MATRIX_PROBE_POS ((0x4035 << 2) + 0xff000000)
+#define LC_STTS_MATRIX_PROBE_COLOR ((0x4036 << 2) + 0xff000000)
+#define LC_STTS_HIST_REGION_IDX ((0x4037 << 2) + 0xff000000)
+#define LC_STTS_HIST_SET_REGION ((0x4038 << 2) + 0xff000000)
+#define LC_STTS_HIST_READ_REGION ((0x4039 << 2) + 0xff000000)
+#define LC_STTS_HIST_START_RD_REGION ((0x403a << 2) + 0xff000000)
+#define LC_STTS_WHITE_INFO ((0x403b << 2) + 0xff000000)
+#define LC_STTS_BLACK_INFO ((0x403c << 2) + 0xff000000)
+//
+// Closing file: lc_stts_curve.h
+//
+// -----------------------------------------------
+// REG_BASE: VDIN_AFBCE_VCBUS_BASE = 0x41
+// -----------------------------------------------
+//
+// Reading file: vdin_afbce_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+// VDIN
+//===========================================================================
+#define VDIN2_WR_CTRL ((0x4101 << 2) + 0xff000000)
+#define VDIN2_WR_CTRL2 ((0x4102 << 2) + 0xff000000)
+#define VDIN2_WR_H_START_END ((0x4103 << 2) + 0xff000000)
+#define VDIN2_WR_V_START_END ((0x4104 << 2) + 0xff000000)
+#define VDIN2_DBG_AXI_CMD_CNT ((0x4105 << 2) + 0xff000000)
+#define VDIN2_DBG_AXI_DAT_CNT ((0x4106 << 2) + 0xff000000)
+#define VDIN2_WR_URGENT_CTRL ((0x4107 << 2) + 0xff000000)
+#define VDIN2_RO_WRMIF_STATUS ((0x4108 << 2) + 0xff000000)
+#define VDIN_TOP_SECURE0_ST_RO ((0x4109 << 2) + 0xff000000)
+#define VDIN_TOP_SECURE_DUMMY ((0x410a << 2) + 0xff000000)
+#define VDIN_TOP_DOUBLE_CTRL ((0x410b << 2) + 0xff000000)
+#define VDIN_TOP_SECURE1_ST_RO ((0x410c << 2) + 0xff000000)
+#define VDIN_TOP_MISC ((0x410d << 2) + 0xff000000)
+#define VDIN_TOP_SECURE_REG0 ((0x410e << 2) + 0xff000000)
+#define VDIN_TOP_SECURE_REG1 ((0x410f << 2) + 0xff000000)
+// 8'ha0 ~ 8'hc6
+//
+// Reading file: vdin_afbc_enc_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define AFBCE_ENABLE ((0x41a0 << 2) + 0xff000000)
+//Bit 31:20, gclk_ctrl unsigned , default = 0,
+//Bit 19:16, afbce_sync_sel unsigned , default = 0,
+//Bit 15:14, reserved
+//Bit 13, enc_rst_mode unsigned , default = 0,
+//Bit 12, enc_en_mode unsigned , default = 0,
+//Bit 11:9, reserved
+//Bit 8, enc_enable unsigned , default = 0,
+//Bit 7:1, reserved
+//Bit 0, reserved enc_frm_start pulse use this bit don't use
+#define AFBCE_MODE ((0x41a1 << 2) + 0xff000000)
+//Bit 31:29, soft_rst unsigned, default = 0 ,the use as go_field
+//Bit 28, reserved unsigned, default = 0 , enable singal of crop
+//Bit 27:26, rev_mode unsigned, default = 0 , reverse mode
+//Bit 25:24, mif_urgent unsigned, default = 3 , info mif and data mif urgent
+//Bit 23, reserved
+//Bit 22:16, hold_line_num unsigned, default = 4, 0: burst1 1:burst2 2:burst4
+//Bit 15:14, burst_mode unsigned, default = 1, 0: burst1 1:burst2 2:burst4
+//Bit 13:1, reserved
+//Bit 0, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb
+#define AFBCE_SIZE_IN ((0x41a2 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hsize_in unsigned, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_in unsigned, default = 1080 , pic vert size in unit: pixel
+#define AFBCE_BLK_SIZE_IN ((0x41a3 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hblk_size unsigned, default = 60 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vblk_size unsigned, default = 270, pic vert size in unit: pixel
+#define AFBCE_HEAD_BADDR ((0x41a4 << 2) + 0xff000000)
+//Bit 31:0, head_baddr unsigned, default = 32'h00;
+#define AFBCE_MIF_SIZE ((0x41a5 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:28, ddr_blk_size unsigned, default = 1;
+//Bit 27, reserved
+//Bit 26:24, cmd_blk_size unsigned, default = 3;
+//Bit 23:21, reserved
+//Bit 20:16, uncmp_size unsigned, default = 20;
+//Bit 15:0, mmu_page_size unsigned, default = 4096;
+#define AFBCE_PIXEL_IN_HOR_SCOPE ((0x41a6 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, enc_win_end_h unsigned, default = 1919 ; //
+//Bit 15:13, reserved
+//Bit 12:0, enc_win_bgn_h unsigned, default = 0 ; //
+#define AFBCE_PIXEL_IN_VER_SCOPE ((0x41a7 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, enc_win_end_v unsigned, default = 1079 ; //
+//Bit 15:13, reserved
+//Bit 12:0, enc_win_bgn_v unsigned, default = 0 ; //
+#define AFBCE_CONV_CTRL ((0x41a8 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, fmt_ybuf_depth unsigned, default = 2048
+//Bit 15:12, reserved
+//Bit 11: 0, lbuf_depth unsigned, default = 256, unit=16 pixel need to set = 2^n
+#define AFBCE_MIF_HOR_SCOPE ((0x41a9 << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, blk_end_h unsigned, default = 0 ; //
+//Bit 15:10, reserved
+//Bit 9:0, blk_bgn_h unsigned, default = 59 ; //
+#define AFBCE_MIF_VER_SCOPE ((0x41aa << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, blk_end_v unsigned, default = 0 ; //
+//Bit 15:12, reserved
+//Bit 11:0, blk_bgn_v unsigned, default = 269 ; //
+#define AFBCE_STAT1 ((0x41ab << 2) + 0xff000000)
+//Bit 31, ro_frm_end_pulse1 unsigned, RO,default = 0 ;frame end status
+//Bit 30:0, ro_dbg_top_info1 unsigned, RO,default = 0 ;
+#define AFBCE_STAT2 ((0x41ac << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30:0, ro_dbg_top_info2 unsigned, RO,default = 0 ;
+#define AFBCE_FORMAT ((0x41ad << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11:10 reserved
+//Bit 9: 8 reg_format_mode // unsigned , RW, default = 2 data format;0 : YUV444, 1:YUV422, 2:YUV420, 3:RGB
+//Bit 7: 4 reg_compbits_c // unsigned , RW, default = 10 chroma bitwidth
+//Bit 3: 0 reg_compbits_y // unsigned , RW, default = 10 luma bitwidth
+#define AFBCE_MODE_EN ((0x41ae << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 reserved
+//Bit 25 reg_adpt_interleave_ymode // unsigned , RW, default = 0 force 0 to disable it: no HW implementation
+//Bit 24 reg_adpt_interleave_cmode // unsigned , RW, default = 0 force 0 to disable it: not HW implementation
+//Bit 23 reg_adpt_yinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
+//Bit 22 reg_adpt_yinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
+//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
+//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
+//Bit 19 reserved
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 11 reserved
+//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
+//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
+//Bit 8 reg_uncompress_split_mode // unsigned , RW, default = 0 0: no split; 1: split
+//Bit 7: 6 reserved
+//Bit 5 reg_input_padding_uv128 // unsigned , RW, default = 0 input picture 32x4 block gap mode: 0: pad uv=0; 1: pad uv=128
+//Bit 4 reg_dwds_padding_uv128 // unsigned , RW, default = 0 downsampled image for double write 32x gap mode: 0: pad uv=0; 1: pad uv=128
+//Bit 3: 1 reg_force_order_mode_value // unsigned , RW, default = 0 force order mode 0~7
+//Bit 0 reg_force_order_mode_en // unsigned , RW, default = 0 force order mode enable: 0: no force; 1: forced to force_value
+#define AFBCE_DWSCALAR ((0x41af << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7: 6 reg_dwscalar_w0 // unsigned , RW, default = 3 horizontal 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 5: 4 reg_dwscalar_w1 // unsigned , RW, default = 0 horizontal 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 3: 2 reg_dwscalar_h0 // unsigned , RW, default = 2 vertical 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 1: 0 reg_dwscalar_h1 // unsigned , RW, default = 3 vertical 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+#define AFBCE_DEFCOLOR_1 ((0x41b0 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_enc_defalutcolor_3 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr]
+//Bit 11: 0 reg_enc_defalutcolor_0 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr]
+#define AFBCE_DEFCOLOR_2 ((0x41b1 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_enc_defalutcolor_2 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr]
+//Bit 11: 0 reg_enc_defalutcolor_1 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr]
+#define AFBCE_QUANT_ENABLE ((0x41b2 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_quant_expand_en_1 // unsigned , RW, default = 0 enable for quantization value expansion
+//Bit 10 reg_quant_expand_en_0 // unsigned , RW, default = 0 enable for quantization value expansion
+//Bit 9: 8 reg_bcleav_ofst // signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1;
+//Bit 7: 5 reserved
+//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy
+//Bit 3: 1 reserved
+//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy
+#define AFBCE_IQUANT_LUT_1 ((0x41b3 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCE_IQUANT_LUT_2 ((0x41b4 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCE_IQUANT_LUT_3 ((0x41b5 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCE_IQUANT_LUT_4 ((0x41b6 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCE_RQUANT_LUT_1 ((0x41b7 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_rquant_yclut_0_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting)
+//Bit 27 reserved
+//Bit 26:24 reg_rquant_yclut_0_10 // unsigned , RW, default = 5
+//Bit 23 reserved
+//Bit 22:20 reg_rquant_yclut_0_9 // unsigned , RW, default = 4
+//Bit 19 reserved
+//Bit 18:16 reg_rquant_yclut_0_8 // unsigned , RW, default = 4
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_0_7 // unsigned , RW, default = 3
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_0_6 // unsigned , RW, default = 3
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_0_5 // unsigned , RW, default = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_0_4 // unsigned , RW, default = 2
+#define AFBCE_RQUANT_LUT_2 ((0x41b8 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_0_3 // unsigned , RW, default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_0_2 // unsigned , RW, default = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_0_1 // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_0_0 // unsigned , RW, default = 0
+#define AFBCE_RQUANT_LUT_3 ((0x41b9 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_rquant_yclut_1_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting)
+//Bit 27 reserved
+//Bit 26:24 reg_rquant_yclut_1_10 // unsigned , RW, default = 5
+//Bit 23 reserved
+//Bit 22:20 reg_rquant_yclut_1_9 // unsigned , RW, default = 4
+//Bit 19 reserved
+//Bit 18:16 reg_rquant_yclut_1_8 // unsigned , RW, default = 4
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_1_7 // unsigned , RW, default = 3
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_1_6 // unsigned , RW, default = 3
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_1_5 // unsigned , RW, default = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_1_4 // unsigned , RW, default = 2
+#define AFBCE_RQUANT_LUT_4 ((0x41ba << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_1_3 // unsigned , RW, default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_1_2 // unsigned , RW, default = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_1_1 // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_1_0 // unsigned , RW, default = 0
+#define AFBCE_YUV_FORMAT_CONV_MODE ((0x41bb << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7 reserved
+//Bit 6: 4 reg_444to422_mode // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_422to420_mode // unsigned , RW, default = 0
+#define AFBCE_DUMMY_DATA ((0x41bc << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29: 0 reg_dummy_data // unsigned , default = 0 ;
+#define AFBCE_CLR_FLAG ((0x41bd << 2) + 0xff000000)
+//Bit 31:0 reg_afbce_clr_flag // unsigned, default = 0 ;
+#define AFBCE_STA_FLAGT ((0x41be << 2) + 0xff000000)
+//Bit 31:0 ro_afbce_sta_flag // unsigned, RO,default = 0 ;
+#define AFBCE_MMU_NUM ((0x41bf << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 0 ro_frm_mmu_num // unsigned, RO,default = 0 ;
+#define AFBCE_MMU_RMIF_CTRL1 ((0x41c0 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_sync_sel // unsigned , default = 0, axi canvas id sync with frm rst
+//Bit 23:16 reg_canvas_id // unsigned , default = 0, axi canvas id num
+//Bit 15 reserved
+//Bit 14:12 reg_cmd_intr_len // unsigned , default = 1, interrupt send cmd when how many series axi cmd,
+ // 0=12 1=16 2=24 3=32 4=40 5=48 6=56 7=64
+//Bit 11:10 reg_cmd_req_size // unsigned , default = 1, how many room fifo have, then axi send series req, 0=16 1=32 2=24 3=64
+//Bit 9:8 reg_burst_len // unsigned , default = 2, burst type: 0-single 1-bst2 2-bst4
+//Bit 7 reg_swap_64bit // unsigned , default = 0, 64bits of 128bit swap enable
+//Bit 6 reg_little_endian // unsigned , default = 0, big endian enable
+//Bit 5 reg_y_rev // unsigned , default = 0, vertical reverse enable
+//Bit 4 reg_x_rev // unsigned , default = 0, horizontal reverse enable
+//Bit 3 reserved
+//Bit 2:0 reg_pack_mode // unsigned , default = 3, 0:4bit 1:8bit 2:16bit 3:32bit 4:64bit 5:128bit
+#define AFBCE_MMU_RMIF_CTRL2 ((0x41c1 << 2) + 0xff000000)
+//Bit 31:30 reg_sw_rst // unsigned , default = 0,
+//Bit 29:24 reserved
+//Bit 23:18 reg_gclk_ctrl
+//Bit 17 reserved
+//Bit 16:0 reg_urgent_ctrl // unsigned , default = 0, urgent control reg :
+ // 16 reg_ugt_init : urgent initial value
+ // 15 reg_ugt_en : urgent enable
+ // 14 reg_ugt_type : 1= wrmif 0=rdmif
+ // 7:4 reg_ugt_top_th: urgent top threshold
+ // 3:0 reg_ugt_bot_th: urgent bottom threshold
+#define AFBCE_MMU_RMIF_CTRL3 ((0x41c2 << 2) + 0xff000000)
+//Bit 31:17 reserved
+//Bit 16 reg_acc_mode // unsigned , default = 1,
+//Bit 15:13 reserved
+//Bit 12:0 reg_stride // unsigned , default = 4096,
+#define AFBCE_MMU_RMIF_CTRL4 ((0x41c3 << 2) + 0xff000000)
+//Bit 31:0 reg_baddr // unsigned , default = 0,
+#define AFBCE_MMU_RMIF_SCOPE_X ((0x41c4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_x_end // unsigned , default = 4095, the canvas hor end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_x_start // unsigned , default = 0, the canvas hor start pixel position
+#define AFBCE_MMU_RMIF_SCOPE_Y ((0x41c5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_y_end // unsigned , default = 0, the canvas ver end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_y_start // unsigned , default = 0, the canvas ver start pixel positio
+#define AFBCE_MMU_RMIF_RO_STAT ((0x41c6 << 2) + 0xff000000)
+//Bit 15:0 reg_status // unsigned ,
+#define AFBCE_PIP_CTRL ((0x41ca << 2) + 0xff000000)
+//Bit 31:3 reserved
+//Bit 2 reg_enc_align_en //unsigned , RW,default = 1,
+//Bit 1 reg_pip_ini_ctrl //unsigned , RW,default = 0,
+//Bit 0 reg_pip_mode //unsigned , RW,default = 0,
+#define AFBCE_ROT_CTRL ((0x41cb << 2) + 0xff000000)
+//Bit 31:5 reserved
+//Bit 4 reg_rot_en //unsigned , RW,default = 0, rotation enable
+//Bit 3:0 reg_vstep //unsigned , RW,default = 8, rotation vstep ,setting acorrding rotation shrink mode
+#define AFBCE_DIMM_CTRL ((0x41cc << 2) + 0xff000000)
+//Bit 31 reg_dimm_layer_en //unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30 reserved
+//Bit 29:0 reg_dimm_data //unsigned , RW,default = 29'h00080200,dimm_layer data
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vdin_afbc_enc_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vdin_afbce_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: LCD2_VCBUS_BASE = 0x42
+// -----------------------------------------------
+//`include "a.h"
+// -----------------------------------------------
+// REG_BASE: DOLBYTV_VCBUS_BASE = 0x43
+// -----------------------------------------------
+//
+// Reading file: dolby_tv_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DOLBY_TV_REG_START ((0x4300 << 2) + 0xff000000)
+// dolby register address 0~0xDA
+#define DOLBY_TV_CLKGATE_CTRL ((0x43f1 << 2) + 0xff000000)
+//bit[9:8] R-RW 0~3 0 dma2axi_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock"
+//bit[7:6] R-RW 0~3 0 bl_dolby_swaps_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock"
+//bit[5:4] R-RW 0~3 0 el_swaps_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock"
+//bit[3:2] R-RW 0~3 0 el_buf_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock"
+//bit[1:0] R-RW 0~3 0 top_level_reg_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock"
+#define DOLBY_TV_SWAP_CTRL0 ((0x43f2 << 2) + 0xff000000)
+//bit[2] R-RW 0~1 0 el_41mode : 1 "bl resolution : el resolution = 4:1", 0 "bl_res : el_res = 1:1"
+//bit[1] R-RW 0~1 0 el_enable : 1 "enhancement layer is supported", 0 "el is not supported"
+//bit[0] R-RW 0~1 0 source_enable : 1 "base layer is supported", 0 "bl is not supported"
+#define DOLBY_TV_SWAP_CTRL1 ((0x43f3 << 2) + 0xff000000)
+//bit[28:16] R-RW 0~8191 0 htotal : total pixels number in each line
+//bit[21:0] R-RW 0~8191 0 vtotal : total line number in each frame (only support progress frame)
+#define DOLBY_TV_SWAP_CTRL2 ((0x43f4 << 2) + 0xff000000)
+//bit[28:16] R-RW 0~4096 0 hsize : active pixels number in each line
+//bit[21:0] R-RW 0~3840 0 vsize : active lines number in each frame
+#define DOLBY_TV_SWAP_CTRL3 ((0x43f5 << 2) + 0xff000000)
+//bit[28:16] R-RW 0~8191 0 hsync_width : hsync signal width (high effective)
+//bit[21:0] R-RW 0~8191 0 vsync_width : vysnc singal width (high effective)
+#define DOLBY_TV_SWAP_CTRL4 ((0x43f6 << 2) + 0xff000000)
+//bit[28:16] R-RW 0~8191 0 hsync_backporch : pixels number between hsync and h_active_duration
+//bit[21:0] R-RW 0~8191 0 vsync_backporch : lines number between vsync and v_active_duration
+#define DOLBY_TV_SWAP_CTRL5 ((0x43f7 << 2) + 0xff000000)
+//[25:8] R-RW : reg_tunnel_sel for tunnel bit match swap
+//bit[4] R-RW 0~1 0 bl_tunnel_mode : 1 "hdmi input, source is 12bit422 tunnel in 8bit444", 0 "opt mode, 10 bit 444"
+//bit[3:2] R-RW 0~3 0 bl_uv_mode : 3 "uv=in_u", 2 "uv[0]=u[0],uv[1]=v[0]", 1 "uv[0]=v[0],uv[1]=u[0]", 0 "uv=in_v"
+//bit[1:0] R-RW 0~3 0 el_uv_mode : 3 "uv=in_u", 2 "uv[0]=u[0],uv[1]=v[0]", 1 "uv[0]=v[0],uv[1]=u[0]", 0 "uv=in_v"
+#define DOLBY_TV_SWAP_CTRL6 ((0x43f8 << 2) + 0xff000000)
+//bit[31] R-RW 0~1 dm_uv_input : uv select
+//bit[23:16] R-RW 0~1 0 dump_ctrl : 1 "fixed output bitdepth as 12bit", 0 "output bitdepth based on vdr_bit_depth"
+//bit[15] R-RW 0~1 datapath_reset_n_enable : manual reset control
+//bit[14] R-RW 0~1 handshake_reset_n_enable : manual reset control
+//bit[13] R-RW 0~1 axi_reset_n_enable : manual reset control
+//bit[5:2] R-RW 0~15 vdr_bit_depth
+//bit[1:0] R-RW 0~3 reg_hdmi_mode
+#define DOLBY_TV_SWAP_CTRL7 ((0x43f9 << 2) + 0xff000000)
+//reserved
+#define DOLBY_TV_AXI2DMA_CTRL0 ((0x43fa << 2) + 0xff000000)
+//bit[31] R-RW 0~1 0 reg_req_en : enable req after line count
+//bit[30] R-RW 0~1 0 reg_id_check : check the id of data path and req path
+//bit[29] R-RW 0~1 0 reg_clear_fifo : manually reset bit
+//bit[28] R-RW 0~1 0 reg_vsync_rst : soft_rst auto reset enable
+//bit[27] R-RW 0~1 0 reg_update_addr : manually udpate start addr
+//bit[26] R-RW 0~1 0 reg_addr_auto : auto update start addr enable
+//bit[25] R-RW 0~1 0 reg_keep_receive : data path keep receive
+//bit[24:19] R-RW 0~63 0 reg_req_th : fifo_room > req_th, then send the request
+//bit[18:16] R-RW 0~7 0 reg_arsize : axi arsize
+//bit[14:12] R-RW 0~7 0 reg_arprot : axi arprot
+//bit[11:8] R-RW 0~15 0 reg_aruser : axi aruser
+//bit[5:4] R-RW 0~3 0 reg_arid : axi arid
+//bit[3:0] R-RW 0~2 0 reg_lens : default request lens, each burst has "reg_lens+1" data
+#define DOLBY_TV_AXI2DMA_CTRL1 ((0x43fb << 2) + 0xff000000)
+//bit[31] R-RW 0~1 0 axi_addr_mode : 1 "canvas mode", 0 "normal mode"
+//bit[27:16] R-RW 0~4095 0 dma_size0 : total data number in dma0
+//bit[11:0] R-RW 0~4095 0 dma_size1 : total data number in dma1
+#define DOLBY_TV_AXI2DMA_CTRL2 ((0x43fc << 2) + 0xff000000)
+//bit[31:0] R-RW 0~4294967295 0 axi_start_addr : axi start address
+#define DOLBY_TV_AXI2DMA_CTRL3 ((0x43fd << 2) + 0xff000000)
+//bit[11:0] R-RW 0~4095 0 hold_line : after hold_line the axi slave start requesting
+#define DOLBY_TV_STATUS0 ((0x43fe << 2) + 0xff000000)
+#define DOLBY_TV_STATUS1 ((0x43ff << 2) + 0xff000000)
+#define DOLBY_TV_ADAPTIVE_SCALE_REGADDR ((0x43e0 << 2) + 0xff000000)
+#define DOLBY_TV_ADAPTIVE_SCALE_REGDATA ((0x43e1 << 2) + 0xff000000)
+#define DOLBY_TV_ADAPTIVE_SCALE_LUTADDR ((0x43e2 << 2) + 0xff000000)
+#define DOLBY_TV_ADAPTIVE_SCALE_LUTDATA ((0x43e3 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dolby_tv_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: DOLBY1B_VCBUS_BASE = 0x44
+// -----------------------------------------------
+//
+// Reading file: dolby1b_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DOLBY_CORE1B_REG_START ((0x4400 << 2) + 0xff000000)
+#define DOLBY_CORE1B_CLKGATE_CTRL ((0x44f2 << 2) + 0xff000000)
+#define DOLBY_CORE1B_SWAP_CTRL0 ((0x44f3 << 2) + 0xff000000)
+#define DOLBY_CORE1B_SWAP_CTRL1 ((0x44f4 << 2) + 0xff000000)
+#define DOLBY_CORE1B_SWAP_CTRL2 ((0x44f5 << 2) + 0xff000000)
+#define DOLBY_CORE1B_SWAP_CTRL3 ((0x44f6 << 2) + 0xff000000)
+#define DOLBY_CORE1B_SWAP_CTRL4 ((0x44f7 << 2) + 0xff000000)
+#define DOLBY_CORE1B_SWAP_CTRL5 ((0x44f8 << 2) + 0xff000000)
+#define DOLBY_CORE1B_DMA_CTRL ((0x44f9 << 2) + 0xff000000)
+#define DOLBY_CORE1B_DMA_STATUS ((0x44fa << 2) + 0xff000000)
+#define DOLBY_CORE1B_STATUS0 ((0x44fb << 2) + 0xff000000)
+#define DOLBY_CORE1B_STATUS1 ((0x44fc << 2) + 0xff000000)
+#define DOLBY_CORE1B_STATUS2 ((0x44fd << 2) + 0xff000000)
+#define DOLBY_CORE1B_STATUS3 ((0x44fe << 2) + 0xff000000)
+#define DOLBY_CORE1B_DMA_PORT ((0x44ff << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dolby1b_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: FGRAIN_VCBUS_BASE = 0x48
+// -----------------------------------------------
+//`include "afbcd_mult_regs.h"
+//
+// Reading file: afbcd_vd_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+// reg addr map
+// 0 -3f : rdmif
+// 40-6f : afbcd
+// 70-7f : fgrain
+////===============================////
+#define VD1_IF0_GEN_REG ((0x4800 << 2) + 0xff000000)
+#define VD1_IF0_CANVAS0 ((0x4801 << 2) + 0xff000000)
+#define VD1_IF0_CANVAS1 ((0x4802 << 2) + 0xff000000)
+#define VD1_IF0_LUMA_X0 ((0x4803 << 2) + 0xff000000)
+#define VD1_IF0_LUMA_Y0 ((0x4804 << 2) + 0xff000000)
+#define VD1_IF0_CHROMA_X0 ((0x4805 << 2) + 0xff000000)
+#define VD1_IF0_CHROMA_Y0 ((0x4806 << 2) + 0xff000000)
+#define VD1_IF0_LUMA_X1 ((0x4807 << 2) + 0xff000000)
+#define VD1_IF0_LUMA_Y1 ((0x4808 << 2) + 0xff000000)
+#define VD1_IF0_CHROMA_X1 ((0x4809 << 2) + 0xff000000)
+#define VD1_IF0_CHROMA_Y1 ((0x480a << 2) + 0xff000000)
+#define VD1_IF0_RPT_LOOP ((0x480b << 2) + 0xff000000)
+#define VD1_IF0_LUMA0_RPT_PAT ((0x480c << 2) + 0xff000000)
+#define VD1_IF0_CHROMA0_RPT_PAT ((0x480d << 2) + 0xff000000)
+#define VD1_IF0_LUMA1_RPT_PAT ((0x480e << 2) + 0xff000000)
+#define VD1_IF0_CHROMA1_RPT_PAT ((0x480f << 2) + 0xff000000)
+#define VD1_IF0_LUMA_PSEL ((0x4810 << 2) + 0xff000000)
+#define VD1_IF0_CHROMA_PSEL ((0x4811 << 2) + 0xff000000)
+#define VD1_IF0_DUMMY_PIXEL ((0x4812 << 2) + 0xff000000)
+#define VD1_IF0_LUMA_FIFO_SIZE ((0x4813 << 2) + 0xff000000)
+#define VD1_IF0_AXI_CMD_CNT ((0x4814 << 2) + 0xff000000)
+#define VD1_IF0_AXI_RDAT_CNT ((0x4815 << 2) + 0xff000000)
+#define VD1_IF0_RANGE_MAP_Y ((0x4816 << 2) + 0xff000000)
+#define VD1_IF0_RANGE_MAP_CB ((0x4817 << 2) + 0xff000000)
+#define VD1_IF0_RANGE_MAP_CR ((0x4818 << 2) + 0xff000000)
+#define VD1_IF0_GEN_REG2 ((0x4819 << 2) + 0xff000000)
+#define VD1_IF0_PROT ((0x481a << 2) + 0xff000000)
+#define VD1_IF0_URGENT_CTRL ((0x481b << 2) + 0xff000000)
+#define VD1_IF0_GEN_REG3 ((0x481c << 2) + 0xff000000)
+#define VIU_VD1_FMT_CTRL ((0x481d << 2) + 0xff000000)
+#define VIU_VD1_FMT_W ((0x481e << 2) + 0xff000000)
+#define VD2_IF0_GEN_REG ((0x4880 << 2) + 0xff000000)
+#define VD2_IF0_CANVAS0 ((0x4881 << 2) + 0xff000000)
+#define VD2_IF0_CANVAS1 ((0x4882 << 2) + 0xff000000)
+#define VD2_IF0_LUMA_X0 ((0x4883 << 2) + 0xff000000)
+#define VD2_IF0_LUMA_Y0 ((0x4884 << 2) + 0xff000000)
+#define VD2_IF0_CHROMA_X0 ((0x4885 << 2) + 0xff000000)
+#define VD2_IF0_CHROMA_Y0 ((0x4886 << 2) + 0xff000000)
+#define VD2_IF0_LUMA_X1 ((0x4887 << 2) + 0xff000000)
+#define VD2_IF0_LUMA_Y1 ((0x4888 << 2) + 0xff000000)
+#define VD2_IF0_CHROMA_X1 ((0x4889 << 2) + 0xff000000)
+#define VD2_IF0_CHROMA_Y1 ((0x488a << 2) + 0xff000000)
+#define VD2_IF0_RPT_LOOP ((0x488b << 2) + 0xff000000)
+#define VD2_IF0_LUMA0_RPT_PAT ((0x488c << 2) + 0xff000000)
+#define VD2_IF0_CHROMA0_RPT_PAT ((0x488d << 2) + 0xff000000)
+#define VD2_IF0_LUMA1_RPT_PAT ((0x488e << 2) + 0xff000000)
+#define VD2_IF0_CHROMA1_RPT_PAT ((0x488f << 2) + 0xff000000)
+#define VD2_IF0_LUMA_PSEL ((0x4890 << 2) + 0xff000000)
+#define VD2_IF0_CHROMA_PSEL ((0x4891 << 2) + 0xff000000)
+#define VD2_IF0_DUMMY_PIXEL ((0x4892 << 2) + 0xff000000)
+#define VD2_IF0_LUMA_FIFO_SIZE ((0x4893 << 2) + 0xff000000)
+#define VD2_IF0_AXI_CMD_CNT ((0x4894 << 2) + 0xff000000)
+#define VD2_IF0_AXI_RDAT_CNT ((0x4895 << 2) + 0xff000000)
+#define VD2_IF0_RANGE_MAP_Y ((0x4896 << 2) + 0xff000000)
+#define VD2_IF0_RANGE_MAP_CB ((0x4897 << 2) + 0xff000000)
+#define VD2_IF0_RANGE_MAP_CR ((0x4898 << 2) + 0xff000000)
+#define VD2_IF0_GEN_REG2 ((0x4899 << 2) + 0xff000000)
+#define VD2_IF0_PROT ((0x489a << 2) + 0xff000000)
+#define VD2_IF0_URGENT_CTRL ((0x489b << 2) + 0xff000000)
+#define VD2_IF0_GEN_REG3 ((0x489c << 2) + 0xff000000)
+#define VIU_VD2_FMT_CTRL ((0x489d << 2) + 0xff000000)
+#define VIU_VD2_FMT_W ((0x489e << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: afbcd_vd_regs.h
+//
+//`include "fgrain_regs.h" //nouse
+// -----------------------------------------------
+// REG_BASE: VPPC_VCBUS_BASE = 0x50
+// -----------------------------------------------
+//
+// Reading file: srsharp_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//SRSHARP0 8'h00 - 8'hff
+//SRSHARP1 8'h100 - 8'1ff
+#define SRSHARP0_OFFSET (0x000<<2)
+#define SRSHARP1_OFFSET (0x200<<2)
+
+//
+// Reading file: sharp_regs.h
+//
+#define SHARP_HVSIZE ((0x5000 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_pknr_hsize . unsigned , default = 1920
+//Bit 15:13, reserved
+//Bit 12: 0, reg_pknr_vsize . unsigned , default = 1080
+#define SHARP_HVBLANK_NUM ((0x5001 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_deband_hblank
+//Bit 15: 8, reg_pknr_hblank_num . unsigned , default = 20
+//Bit 7: 0, reg_pknr_vblank_num . unsigned , default = 73
+#define NR_GAUSSIAN_MODE ((0x5002 << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13:12, reg_nr_gau_ynorm : C adpative coef norm, 0: 128, 1: 256, 2: 512, 3: 1024 . unsigned , default = 0
+//Bit 11:10, reserved
+//Bit 9: 8, reg_nr_gau_cnorm : C adpative coef norm, 0: 128, 1: 256, 2: 512, 3: 1024 . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 4, reg_nr_gau_ymode : 0 3x3 filter; 1: 5x5 filter; 2/3:adpative coef . unsigned , default = 1
+//Bit 3: 2, reserved
+//Bit 1: 0, reg_nr_gau_cmode : 0 3x3 filter; 1: 5x5 filter; 2/3:adpative coef . unsigned , default = 1
+#define PK_CON_2CIRHPGAIN_TH_RATE ((0x5005 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_cirhpcon2gain0 : threshold0 of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 25
+//Bit 23:16, reg_pk_cirhpcon2gain1 : threshold1 of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 60
+//Bit 15: 8, reg_pk_cirhpcon2gain5 : rate0 (for hpcon<th0) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 80
+//Bit 7: 0, reg_pk_cirhpcon2gain6 : rate1 (for hpcon>th1) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 20
+#define PK_CON_2CIRHPGAIN_LIMIT ((0x5006 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_cirhpcon2gain2 : level limit(for hpcon<th0) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 155
+//Bit 23:16, reg_pk_cirhpcon2gain3 : level limit(for th0<hpcon<th1) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 150
+//Bit 15: 8, reg_pk_cirhpcon2gain4 : level limit(for hpcon>th1) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 5
+//Bit 7: 0, reserved
+#define PK_CON_2CIRBPGAIN_TH_RATE ((0x5007 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_cirbpcon2gain0 : threshold0 of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 20
+//Bit 23:16, reg_pk_cirbpcon2gain1 : threshold1 of curve to map bpcon to bpgain for circle bp filter (all 8 direction same).. unsigned , default = 50
+//Bit 15: 8, reg_pk_cirbpcon2gain5 : rate0 (for bpcon<th0) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 50
+//Bit 7: 0, reg_pk_cirbpcon2gain6 : rate1 (for bpcon>th1) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 25
+#define PK_CON_2CIRBPGAIN_LIMIT ((0x5008 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_cirbpcon2gain2 : level limit(for bpcon<th0) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 155
+//Bit 23:16, reg_pk_cirbpcon2gain3 : level limit(for th0<bpcon<th1) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 150
+//Bit 15: 8, reg_pk_cirbpcon2gain4 : level limit(for bpcon>th1) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 5
+//Bit 7: 0, reserved
+#define PK_CON_2DRTHPGAIN_TH_RATE ((0x5009 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_drthpcon2gain0 : threshold0 of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 25
+//Bit 23:16, reg_pk_drthpcon2gain1 : threshold1 of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 60
+//Bit 15: 8, reg_pk_drthpcon2gain5 : rate0 (for hpcon<th0) of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 80
+//Bit 7: 0, reg_pk_drthpcon2gain6 : rate1 (for hpcon>th1) of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 20
+#define PK_CON_2DRTHPGAIN_LIMIT ((0x500a << 2) + 0xff000000)
+//Bit 31:24, reg_pk_drthpcon2gain2 : level limit(for hpcon<th0) of curve to map hpcon to hpgain for directional hp filter (best direction).. unsigned , default = 105
+//Bit 23:16, reg_pk_drthpcon2gain3 : level limit(for th0<hpcon<th1) of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 96
+//Bit 15: 8, reg_pk_drthpcon2gain4 : level limit(for hpcon>th1) of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 5
+//Bit 7: 0, reserved
+#define PK_CON_2DRTBPGAIN_TH_RATE ((0x500b << 2) + 0xff000000)
+//Bit 31:24, reg_pk_drtbpcon2gain0 : threshold0 of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 20
+//Bit 23:16, reg_pk_drtbpcon2gain1 : threshold1 of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 50
+//Bit 15: 8, reg_pk_drtbpcon2gain5 : rate0 (for bpcon<th0) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 50
+//Bit 7: 0, reg_pk_drtbpcon2gain6 : rate1 (for bpcon>th1) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 25
+#define PK_CON_2DRTBPGAIN_LIMIT ((0x500c << 2) + 0xff000000)
+//Bit 31:24, reg_pk_drtbpcon2gain2 : level limit(for bpcon<th0) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 55
+//Bit 23:16, reg_pk_drtbpcon2gain3 : level limit(for th0<bpcon<th1) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 40
+//Bit 15: 8, reg_pk_drtbpcon2gain4 : level limit(for bpcon>th1) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 5
+//Bit 7: 0, reserved
+#define PK_CIRFB_LPF_MODE ((0x500d << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:28, reg_cirhp_horz_mode : no horz filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1
+//Bit 27:26, reserved
+//Bit 25:24, reg_cirhp_vert_mode : no vert filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1
+//Bit 23:22, reserved
+//Bit 21:20, reg_cirhp_diag_mode : filter on HP; 1: [1 2 1]/4; . unsigned , default = 1
+//Bit 19:14, reserved
+//Bit 13:12, reg_cirbp_horz_mode : no horz filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1
+//Bit 11:10, reserved
+//Bit 9: 8, reg_cirbp_vert_mode : no vert filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1
+//Bit 7: 6, reserved
+//Bit 5: 4, reg_cirbp_diag_mode : filter on BP; 1: [1 2 1]/4; . unsigned , default = 1
+//Bit 3: 0, reserved
+#define PK_DRTFB_LPF_MODE ((0x500e << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:28, reg_drthp_horz_mode : no horz filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1
+//Bit 27:26, reserved
+//Bit 25:24, reg_drthp_vert_mode : no vert filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1
+//Bit 23:22, reserved
+//Bit 21:20, reg_drthp_diag_mode : filter on HP; 1: [1 2 1]/4; 1 . unsigned , default = 1
+//Bit 19:14, reserved
+//Bit 13:12, reg_drtbp_horz_mode : no horz filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1
+//Bit 11:10, reserved
+//Bit 9: 8, reg_drtbp_vert_mode : no vert filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1
+//Bit 7: 6, reserved
+//Bit 5: 4, reg_drtbp_diag_mode : filter on BP; 1: [1 2 1]/4; 1 . unsigned , default = 1
+//Bit 3: 0, reserved
+#define PK_CIRFB_HP_CORING ((0x500f << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, reg_cirhp_horz_core : coring of HP for Horz . unsigned , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_cirhp_vert_core : coring of HP for Vert . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_cirhp_diag_core : coring of HP for Diag . unsigned , default = 0
+#define PK_CIRFB_BP_CORING ((0x5010 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, reg_cirbp_horz_core : coring of HP for Horz . unsigned , default = 1
+//Bit 15:14, reserved
+//Bit 13: 8, reg_cirbp_vert_core : coring of HP for Vert . unsigned , default = 1
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_cirbp_diag_core : coring of HP for Diag . unsigned , default = 1
+#define PK_DRTFB_HP_CORING ((0x5011 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, reg_drthp_horz_core : coring of HP for Horz . unsigned , default = 1
+//Bit 15:14, reserved
+//Bit 13: 8, reg_drthp_vert_core : coring of HP for Vert . unsigned , default = 1
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_drthp_diag_core : coring of HP for Diag . unsigned , default = 1
+#define PK_DRTFB_BP_CORING ((0x5012 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, reg_drtbp_horz_core : coring of HP for Horz . unsigned , default = 1
+//Bit 15:14, reserved
+//Bit 13: 8, reg_drtbp_vert_core : coring of HP for Vert . unsigned , default = 1
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_drtbp_diag_core : coring of HP for Diag . unsigned , default = 1
+#define PK_CIRFB_BLEND_GAIN ((0x5013 << 2) + 0xff000000)
+//Bit 31:28, reg_hp_cir_hgain : normalized 8 as '1' . unsigned , default = 8
+//Bit 27:24, reg_hp_cir_vgain : normalized 8 as '1' . unsigned , default = 8
+//Bit 23:20, reg_hp_cir_dgain : normalized 8 as '1' . unsigned , default = 8
+//Bit 19:16, reserved
+//Bit 15:12, reg_bp_cir_hgain : normalized 8 as '1' . unsigned , default = 8
+//Bit 11: 8, reg_bp_cir_vgain : normalized 8 as '1' . unsigned , default = 8
+//Bit 7: 4, reg_bp_cir_dgain : normalized 8 as '1' . unsigned , default = 8
+//Bit 3: 0, reserved
+#define NR_ALPY_SSD_GAIN_OFST ((0x5014 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_nr_alp0_ssd_gain : gain to max ssd normalized 16 as '1' . unsigned , default = 16
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_nr_alp0_ssd_ofst : offset to ssd before dividing to min_err . signed , default = -2
+#define NR_ALP0Y_ERR2CURV_TH_RATE ((0x5015 << 2) + 0xff000000)
+//Bit 31:24, reg_nr_alp0_minerr_ypar0 : threshold0 of curve to map mierr to alp0 for luma channel, this will be set value of flat region mierr that no need blur. 0~255.. unsigned , default = 10
+//Bit 23:16, reg_nr_alp0_minerr_ypar1 : threshold1 of curve to map mierr to alp0 for luma channel,this will be set value of texture region mierr that can not blur.. unsigned , default = 25
+//Bit 15: 8, reg_nr_alp0_minerr_ypar5 : rate0 (for mierr<th0) of curve to map mierr to alp0 for luma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 80
+//Bit 7: 0, reg_nr_alp0_minerr_ypar6 : rate1 (for mierr>th1) of curve to map mierr to alp0 for luma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 64
+#define NR_ALP0Y_ERR2CURV_LIMIT ((0x5016 << 2) + 0xff000000)
+//Bit 31:24, reg_nr_alp0_minerr_ypar2 : level limit(for mierr<th0) of curve to map mierr to alp0 for luma channel, this will be set to alp0 that we can do for flat region. 0~255.. unsigned , default = 63
+//Bit 23:16, reg_nr_alp0_minerr_ypar3 : level limit(for th0<mierr<th1) of curve to map mierr to alp0 for luma channel, this will be set to alp0 that we can do for misc region. 0~255.. unsigned , default = 0
+//Bit 15: 8, reg_nr_alp0_minerr_ypar4 : level limit(for mierr>th1) of curve to map mierr to alp0 for luma channel, this will be set to alp0 that we can do for texture region. 0~255.. unsigned , default = 63
+//Bit 7: 0, reserved
+#define NR_ALP0C_ERR2CURV_TH_RATE ((0x5017 << 2) + 0xff000000)
+//Bit 31:24, reg_nr_alp0_minerr_cpar0 : threshold0 of curve to map mierr to alp0 for chroma channel, this will be set value of flat region mierr that no need blur.. unsigned , default = 10
+//Bit 23:16, reg_nr_alp0_minerr_cpar1 : threshold1 of curve to map mierr to alp0 for chroma channel,this will be set value of texture region mierr that can not blur.. unsigned , default = 25
+//Bit 15: 8, reg_nr_alp0_minerr_cpar5 : rate0 (for mierr<th0) of curve to map mierr to alp0 for chroma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 80
+//Bit 7: 0, reg_nr_alp0_minerr_cpar6 : rate1 (for mierr>th1) of curve to map mierr to alp0 for chroma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 64
+#define NR_ALP0C_ERR2CURV_LIMIT ((0x5018 << 2) + 0xff000000)
+//Bit 31:24, reg_nr_alp0_minerr_cpar2 : level limit(for mierr<th0) of curve to map mierr to alp0 for chroma channel, this will be set to alp0 that we can do for flat region. 0~255.. unsigned , default = 63
+//Bit 23:16, reg_nr_alp0_minerr_cpar3 : level limit(for th0<mierr<th1) of curve to map mierr to alp0 for chroma channel, this will be set to alp0 that we can do for misc region. 0~255.. unsigned , default = 0
+//Bit 15: 8, reg_nr_alp0_minerr_cpar4 : level limit(for mierr>th1) of curve to map mierr to alp0 for chroma channel, this will be set to alp0 that we can do for texture region. 0~255.. unsigned , default = 63
+//Bit 7: 0, reserved
+#define NR_ALP0_MIN_MAX ((0x5019 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_nr_alp0_ymin : normalized to 64 as '1' . unsigned , default = 0
+//Bit 23:22, reserved
+//Bit 21:16, reg_nr_alp0_ymax : normalized to 64 as '1' . unsigned , default = 63
+//Bit 15:14, reserved
+//Bit 13: 8, reg_nr_alp0_cmin : normalized to 64 as '1' . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_nr_alp0_cmax : normalized to 64 as '1' . unsigned , default = 63
+#define NR_ALP1_MIERR_CORING ((0x501a << 2) + 0xff000000)
+//Bit 31:17, reserved
+//Bit 16, reg_nr_alp1_maxerr_mode : 0 max err; 1: xerr . unsigned , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_nr_alp1_core_rate : normalized 64 as "1" . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_nr_alp1_core_ofst : normalized 64 as "1" . signed , default = 3
+#define NR_ALP1_ERR2CURV_TH_RATE ((0x501b << 2) + 0xff000000)
+//Bit 31:24, reg_nr_alp1_minerr_par0 : threshold0 of curve to map mierr to alp1 for luma/chroma channel, this will be set value of flat region mierr that no need directional NR. 0~255.. unsigned , default = 0
+//Bit 23:16, reg_nr_alp1_minerr_par1 : threshold1 of curve to map mierr to alp1 for luma/chroma channel,this will be set value of texture region mierr that can not do directional NR. 0~255.. unsigned , default = 24
+//Bit 15: 8, reg_nr_alp1_minerr_par5 : rate0 (for mierr<th0) of curve to map mierr to alp1 for luma/chroma channel. the larger of the value, the deep of the slope.. unsigned , default = 0
+//Bit 7: 0, reg_nr_alp1_minerr_par6 : rate1 (for mierr>th1) of curve to map mierr to alp1 for luma/chroma channel. the larger of the value, the deep of the slope. 0~255. unsigned , default = 20
+#define NR_ALP1_ERR2CURV_LIMIT ((0x501c << 2) + 0xff000000)
+//Bit 31:24, reg_nr_alp1_minerr_par2 : level limit(for mierr<th0) of curve to map mierr to alp1 for luma/chroma channel, this will be set to alp1 that we can do for flat region. 0~255.. unsigned , default = 0
+//Bit 23:16, reg_nr_alp1_minerr_par3 : level limit(for th0<mierr<th1) of curve to map mierr to alp1 for luma/chroma channel, this will be set to alp1 that we can do for misc region. 0~255.. unsigned , default = 16
+//Bit 15: 8, reg_nr_alp1_minerr_par4 : level limit(for mierr>th1) of curve to map mierr to alp1 for luma/chroma channel, this will be set to alp1 that we can do for texture region. 0~255.255 before. unsigned , default = 63
+//Bit 7: 0, reserved
+#define NR_ALP1_MIN_MAX ((0x501d << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_nr_alp1_ymin : normalized to 64 as '1' . unsigned , default = 0
+//Bit 23:22, reserved
+//Bit 21:16, reg_nr_alp1_ymax : normalized to 64 as '1' . unsigned , default = 63
+//Bit 15:14, reserved
+//Bit 13: 8, reg_nr_alp1_cmin : normalized to 64 as '1' . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_nr_alp1_cmax : normalized to 64 as '1' . unsigned , default = 63
+#define PK_ALP2_MIERR_CORING ((0x501e << 2) + 0xff000000)
+//Bit 31:17, reserved
+//Bit 16, reg_pk_alp2_maxerr_mode : 0 max err; 1: xerr . unsigned , default = 1
+//Bit 15:14, reserved
+//Bit 13: 8, reg_pk_alp2_core_rate : normalized 64 as "1" . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_pk_alp2_core_ofst : normalized 64 as "1" . signed , default = 1
+#define PK_ALP2_ERR2CURV_TH_RATE ((0x501f << 2) + 0xff000000)
+//Bit 31:24, reg_pk_alp2_minerr_par0 : threshold0 of curve to map mierr to alp2 for luma channel, this will be set value of flat region mierr that no need peaking.. unsigned , default = 0
+//Bit 23:16, reg_pk_alp2_minerr_par1 : threshold1 of curve to map mierr to alp2 for luma channel,this will be set value of texture region mierr that can not do peaking. 0~255.. unsigned , default = 24
+//Bit 15: 8, reg_pk_alp2_minerr_par5 : rate0 (for mierr<th0) of curve to map mierr to alp2 for luma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 0
+//Bit 7: 0, reg_pk_alp2_minerr_par6 : rate1 (for mierr>th1) of curve to map mierr to alp2 for luma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 20
+#define PK_ALP2_ERR2CURV_LIMIT ((0x5020 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_alp2_minerr_par2 : level limit(for mierr<th0) of curve to map mierr to alp2 for luma channel, this will be set to alp2 that we can do for flat region. 0~255.. unsigned , default = 0
+//Bit 23:16, reg_pk_alp2_minerr_par3 : level limit(for th0<mierr<th1) of curve to map mierr to alp2 for luma channel, this will be set to alp2 that we can do for misc region. 0~255.. unsigned , default = 16
+//Bit 15: 8, reg_pk_alp2_minerr_par4 : level limit(for mierr>th1) of curve to map mierr to alp2 for luma channel, this will be set to alp2 that we can do for texture region. 0~255. default = 32;. unsigned , default = 32
+//Bit 7: 0, reserved
+#define PK_ALP2_MIN_MAX ((0x5021 << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13: 8, reg_pk_alp2_min : normalized to 64 as '1' . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_pk_alp2_max : normalized to 64 as '1' . unsigned , default = 63
+#define PK_FINALGAIN_HP_BP ((0x5022 << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:16, reg_final_gain_rs : s2: right shift bits for the gain normalization, 0 normal to 32 as 1; 1 normalize to 64 as 1; -2 normalized to 8 as 1; -1 normalize 16 as 1. default = 0
+//Bit 15: 8, reg_hp_final_gain : gain to highpass boost result (including directional/circle blending), normalized 32 as '1', 0~255. 1.25 * 32. unsigned , default = 40
+//Bit 7: 0, reg_bp_final_gain : gain to bandpass boost result (including directional/circle blending), normalized 32 as '1', 0~255. 1.25 * 32. unsigned , default = 30
+#define PK_OS_HORZ_CORE_GAIN ((0x5023 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_os_hsidecore : side coring (not to current pixel) to adaptive overshoot margin in horizontal direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 8
+//Bit 23:16, reg_pk_os_hsidegain : side gain (not to current pixel) to adaptive overshoot margin in horizontal direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20
+//Bit 15: 8, reg_pk_os_hmidcore : midd coring (to current pixel) to adaptive overshoot margin in horizontal direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 2
+//Bit 7: 0, reg_pk_os_hmidgain : midd gain (to current pixel) to adaptive overshoot margin in horizontal direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20
+#define PK_OS_VERT_CORE_GAIN ((0x5024 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_os_vsidecore : side coring (not to current pixel) to adaptive overshoot margin in vertical direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 8
+//Bit 23:16, reg_pk_os_vsidegain : side gain (not to current pixel) to adaptive overshoot margin in vertical direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20
+//Bit 15: 8, reg_pk_os_vmidcore : midd coring (to current pixel) to adaptive overshoot margin in vertical direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 2
+//Bit 7: 0, reg_pk_os_vmidgain : midd gain (to current pixel) to adaptive overshoot margin in vertical direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20
+#define PK_OS_ADPT_MISC ((0x5025 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_os_minerr_core : coring to minerr for adaptive overshoot margin. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 40
+//Bit 23:16, reg_pk_os_minerr_gain : gain to minerr based adaptive overshoot margin. normalized to 64 as '1'. 0~255;. unsigned , default = 6
+//Bit 15: 8, reg_pk_os_adpt_max : maximum limit adaptive overshoot margin (4x). 0~255; . unsigned , default = 200
+//Bit 7: 0, reg_pk_os_adpt_min : minimun limit adaptive overshoot margin (1x). 0~255; . unsigned , default = 20
+#define PK_OS_STATIC ((0x5026 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:28, reg_pk_osh_mode : 0~3: (2x+1) window in H direction . unsigned , default = 2
+//Bit 27:26, reserved
+//Bit 25:24, reg_pk_osv_mode : 0~3: (2x+1) window in V direction . unsigned , default = 2
+//Bit 23:22, reserved
+//Bit 21:12, reg_pk_os_down : static negative overshoot margin. 0~1023; . unsigned , default = 200
+//Bit 11:10, reserved
+//Bit 9: 0, reg_pk_os_up : static positive overshoot margin. 0~1023; . unsigned , default = 200
+#define PK_NR_ENABLE ((0x5027 << 2) + 0xff000000)
+//Bit 31: 4, reserved
+//Bit 3: 2, reg_3d_mode , 0: no 3D; 1: L/R; 2: T/B; 3: horizontal interleaved, dft = 0 //. unsigned , default = 0
+//Bit 1, reg_pk_en . unsigned , default = 1
+//Bit 0, reg_nr_en . unsigned , default = 1
+#define PK_DRT_SAD_MISC ((0x5028 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_sad_ver_gain : gain to sad[4], 16 normalized to "1"; . unsigned , default = 32
+//Bit 23:16, reg_pk_sad_hor_gain : gain to sad[0], 16 normalized to "1"; . unsigned , default = 24
+//Bit 15:12, reserved
+//Bit 11 reserved
+//Bit 10: 9, reg_pk_bias_diag : bias towards diag . unsigned , default = 0
+//Bit 8, reserved
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_pk_drt_force : force direction of drt peaking filter, h2b: 0:hp drt force, 1: bp drt force; 2: bp+hp drt force, 3: no force;. unsigned , default = 24
+#define NR_TI_DNLP_BLEND ((0x5029 << 2) + 0xff000000)
+//Bit 31:11, reserved
+//Bit 10: 8, reg_dnlp_input_mode : dnlp input options. 0: org_y; 1: gau_y; 2: gauadp_y; 3: edgadplpf_y; 4: nr_y;5: lti_y; 6: pk_y (before os);7: pk_y (after os). unsigned , default = 4
+//Bit 7: 4, reserved
+//Bit 3: 2, reg_nr_cti_blend_mode : blend mode of nr and lti result: 0: nr; 1:cti; 2: (nr+cti)/2; 3:cti + dlt_nr . unsigned , default = 1
+//Bit 1: 0, reg_nr_lti_blend_mode : blend mode of nr and lti result: 0: nr; 1:lti; 2: (nr+lti)/2; 3:lti + dlt_nr . unsigned , default = 2
+////////////////////////////////////////////////////////////////////////////////
+// new ti regsters from here
+////////////////////////////////////////////////////////////////////////////////
+#define LTI_DIR_CORE_ALPHA ((0x502a << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_adp_lti_dir_alp_core_ofst : ofst to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=10. unsigned , default = 10
+//Bit 23:20, reserved
+//Bit 19:16, reg_adp_lti_dir_alp_core_rate : ofset to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=0/32. unsigned , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_adp_lti_dir_alpmin : min value of alpha, alpha = (min_err+x +ofst)/max_err*64; dft=10 . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_adp_lti_dir_alpmax : max value of alpha, alpha = (min_err+x +ofst)/max_err*64; dft=63 . unsigned , default = 63
+#define CTI_DIR_ALPHA ((0x502b << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_adp_cti_dir_alp_core_ofst : ofst to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=10. unsigned , default = 5
+//Bit 23:20, reserved
+//Bit 19:16, reg_adp_cti_dir_alp_core_rate : ofset to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=0/32. unsigned , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_adp_cti_dir_alpmin : min value of alpha, alpha = (min_err +x+ofst)/max_err*64; dft=10 . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_adp_cti_dir_alpmax : max value of alpha, alpha = (min_err +x+ofst)/max_err*64; dft=63 . unsigned , default = 63
+#define LTI_CTI_DF_GAIN ((0x502c << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_adp_lti_hdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12
+//Bit 23:22, reserved
+//Bit 21:16, reg_adp_lti_vdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12
+//Bit 15:14, reserved
+//Bit 13: 8, reg_adp_cti_hdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_adp_cti_vdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12
+#define LTI_CTI_DIR_AC_DBG ((0x502d << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30, reg_adp_lti_dir_lpf : 0: no lpf; 1: [1 2 2 2 1]/8 lpf . unsigned , default = 1
+//Bit 29, reserved
+//Bit 28, reg_adp_lti_dir_difmode : 0: y_dif; 1: y_dif + (u_dif+v_dif)/2; . unsigned , default = 1
+//Bit 27, reserved
+//Bit 26, reg_adp_cti_dir_lpf : 0: no lpf; 1: [1 2 2 2 1]/8 lpf dft=1 . unsigned , default = 1
+//Bit 25:24, reg_adp_cti_dir_difmode : 0: (u_dif+v_dif); 1: y_dif/2 + (u_dif+v_dif)*3/4; 2: y_dif + (u_dif+v_dif)/2; 3: y_dif*2 (not recomended). unsigned , default = 2
+//Bit 23:22, reg_adp_hvlti_dcblend_mode : 0: hlti_dc; 1:vlti_dc; 2: avg 3; blend on alpha . unsigned , default = 3
+//Bit 21:20, reg_adp_hvcti_dcblend_mode : 0: hcti_dc; 1:vcti_dc; 2: avg 3; blend on alpha . unsigned , default = 2
+//Bit 19:18, reg_adp_hvlti_acblend_mode : hlti_ac; 1:vlti_ac; 2: add 3;:adaptive to alpha . unsigned , default = 3
+//Bit 17:16, reg_adp_hvcti_acblend_mode : hcti_ac; 1:vcti_ac; 2: add 3;: adaptive to alpha . unsigned , default = 2
+//Bit 15, reserved
+//Bit 14:12, reg_adp_hlti_debug , for hlti debug, default = 0 . unsigned , default = 0
+//Bit 11, reserved
+//Bit 10: 8, reg_adp_vlti_debug , for vlti debug, default = 0 . unsigned , default = 0
+//Bit 7, reserved
+//Bit 6: 4, reg_adp_hcti_debug , for hcti debug, default = 0 . unsigned , default = 0
+//Bit 3, reserved
+//Bit 2: 0, reg_adp_vcti_debug , for vcti debug, default = 0 . unsigned , default = 0
+#define HCTI_FLT_CLP_DC ((0x502e << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28, reg_adp_hcti_en , 0: no cti, 1: new cti, default = 1 . unsigned , default = 1
+//Bit 27:26, reg_adp_hcti_vdn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 25:24, reg_adp_hcti_hdn_flt , 0: no lpf; 1:[0, 0, 0, 4, 8, 4, 0, 0, 0], 2:[0, 0, 2, 4, 4, 4, 2, 0, 0], 3: [1, 2, 2, 2, 2, 2, 2, 2, 1], default = 2. unsigned , default = 2
+//Bit 23:22, reg_adp_hcti_ddn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 21:20, reg_adp_hcti_lpf0_flt , 0:no filter; 1:sigma=0.75, 2: sigma = 1.0, 3: sigma = 1.5, default = 1 . unsigned , default = 1
+//Bit 19:18, reg_adp_hcti_lpf1_flt , 0:no filter; 1:sigma= 2.0, 2: sigma = 3.0, 3: sigma = 4.0, default = 1 . unsigned , default = 1
+//Bit 17:16, reg_adp_hcti_lpf2_flt , 0:no filter; 1:sigma=5.0, 2: sigma = 9.0, 3: sigma = 13.0, default = 1 . unsigned , default = 1
+//Bit 15:12, reg_adp_hcti_hard_clp_win , window size, 0~8, default = 5 . unsigned , default = 5
+//Bit 11: 8, reg_adp_hcti_hard_win_min , window size, 0~8, default = 3 . unsigned , default = 3
+//Bit 7: 5, reserved
+//Bit 4, reg_adp_hcti_clp_mode , 0: hard clip, 1: adaptive clip, default = 1 . unsigned , default = 1
+//Bit 3, reserved
+//Bit 2: 0, reg_adp_hcti_dc_mode , 0:dn, 1:lpf0, 2:lpf1, 3:lpf2, 4: lpf3: 5: vdn result; 6/7:org, default = 0 . unsigned , default = 0
+#define HCTI_BST_GAIN ((0x502f << 2) + 0xff000000)
+//Bit 31:24, reg_adp_hcti_bst_gain0 : gain of the bandpass 0 (lpf1-lpf2)- LBP, default = 80 . unsigned , default = 80
+//Bit 23:16, reg_adp_hcti_bst_gain1 : gain of the bandpass 1 (lpf0-lpf1)- BP, default = 96 . unsigned , default = 96
+//Bit 15: 8, reg_adp_hcti_bst_gain2 : gain of the bandpass 2 (hdn-lpf0)- HP, default = 64 . unsigned , default = 64
+//Bit 7: 0, reg_adp_hcti_bst_gain3 : gain of the unsharp band (yuvin-hdn) - US, default = 16 . unsigned , default = 16
+#define HCTI_BST_CORE ((0x5030 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_hcti_bst_core0 : core of the bandpass 0 (lpf1-lpf2)- LBP, default = 5 . unsigned , default = 5
+//Bit 23:16, reg_adp_hcti_bst_core1 : core of the bandpass 1 (lpf0-lpf1)- BP, default = 5 . unsigned , default = 5
+//Bit 15: 8, reg_adp_hcti_bst_core2 : core of the bandpass 2 (hdn-lpf0)- HP, default = 5 . unsigned , default = 5
+//Bit 7: 0, reg_adp_hcti_bst_core3 : core of the unsharp band (yuvin-hdn) - US, default = 3 . unsigned , default = 5
+#define HCTI_CON_2_GAIN_0 ((0x5031 << 2) + 0xff000000)
+//Bit 31:29, reg_adp_hcti_con_mode : con mode 0:[0, 0,-1, 1, 0, 0, 0]+[0, 0, 0, 1,-1, 0, 0], 1: [0, 0,-1, 0, 1, 0, 0], 2: [0,-1, 0, 0, 0, 1, 0], 3:[-1, 0, 0, 0, 0, 0, 1], 4: .... default = 1. unsigned , default = 1
+//Bit 28:26, reg_adp_hcti_dx_mode : dx mode 0: [-1 1 0]; 1~7: [-1 (2x+1)"0" 1], default = 2 . unsigned , default = 2
+//Bit 25:24, reg_adp_hcti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0
+//Bit 23:16, reg_adp_hcti_con_2_gain0 , default = 25 . unsigned , default = 25
+//Bit 15: 8, reg_adp_hcti_con_2_gain1 , default = 60 . unsigned , default = 60
+//Bit 7: 0, reg_adp_hcti_con_2_gain2 0;, default = 5 . unsigned , default = 5
+#define HCTI_CON_2_GAIN_1 ((0x5032 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_hcti_con_2_gain3 96;, default = 96 . unsigned , default = 96
+//Bit 23:16, reg_adp_hcti_con_2_gain4 5;, default = 5 . unsigned , default = 5
+//Bit 15: 8, reg_adp_hcti_con_2_gain5 80;, default = 80 . unsigned , default = 80
+//Bit 7: 0, reg_adp_hcti_con_2_gain6 20;, default = 20 . unsigned , default = 20
+#define HCTI_OS_MARGIN ((0x5033 << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_adp_hcti_os_margin : margin for hcti overshoot, default = 0 . unsigned , default = 0
+#define HLTI_FLT_CLP_DC ((0x5034 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28, reg_adp_hlti_en , 0: no cti, 1: new cti, default = 1 . unsigned , default = 1
+//Bit 27:26, reg_adp_hlti_vdn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 25:24, reg_adp_hlti_hdn_flt , 0: no lpf; 1:[0, 0, 0, 4, 8, 4, 0, 0, 0], 2:[0, 0, 2, 4, 4, 4, 2, 0, 0], 3: [1, 2, 2, 2, 2, 2, 2, 2, 1], default = 1. unsigned , default = 1
+//Bit 23:22, reg_adp_hlti_ddn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 1 . unsigned , default = 1
+//Bit 21:20, reg_adp_hlti_lpf0_flt , 0:no filter; 1:sigma=0.75, 2: sigma = 1.0, 3: sigma = 1.5, default = 1 . unsigned , default = 1
+//Bit 19:18, reg_adp_hlti_lpf1_flt , 0:no filter; 1:sigma= 2.0, 2: sigma = 3.0, 3: sigma = 4.0, default = 1 . unsigned , default = 1
+//Bit 17:16, reg_adp_hlti_lpf2_flt , 0:no filter; 1:sigma=5.0, 2: sigma = 9.0, 3: sigma = 13.0, default = 1 . unsigned , default = 1
+//Bit 15:12, reg_adp_hlti_hard_clp_win , window size, 0~8, default = 2 . unsigned , default = 2
+//Bit 11: 8, reg_adp_hlti_hard_win_min , window size, 0~8, default = 1 . unsigned , default = 1
+//Bit 7: 5, reserved
+//Bit 4, reg_adp_hlti_clp_mode , 0: hard clip, 1: adaptive clip, default = 0 . unsigned , default = 0
+//Bit 3, reserved
+//Bit 2: 0, reg_adp_hlti_dc_mode , 0:dn, 1:lpf0, 2:lpf1, 3:lpf2, 4: lpf3: 5: vdn result; 6/7:org, default = 4 . unsigned , default = 4
+#define HLTI_BST_GAIN ((0x5035 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_hlti_bst_gain0 : gain of the bandpass 0 (lpf1-lpf2)- LBP, default = 32 . unsigned , default = 32
+//Bit 23:16, reg_adp_hlti_bst_gain1 : gain of the bandpass 1 (lpf0-lpf1)- BP, default = 32 . unsigned , default = 32
+//Bit 15: 8, reg_adp_hlti_bst_gain2 : gain of the bandpass 2 (hdn-lpf0)- HP, default = 28 . unsigned , default = 28
+//Bit 7: 0, reg_adp_hlti_bst_gain3 : gain of the unsharp band (yuvin-hdn) - US, default = 12 . unsigned , default = 12
+#define HLTI_BST_CORE ((0x5036 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_hlti_bst_core0 : core of the bandpass 0 (lpf1-lpf2)- LBP, default = 5 . unsigned , default = 5
+//Bit 23:16, reg_adp_hlti_bst_core1 : core of the bandpass 1 (lpf0-lpf1)- BP, default = 5 . unsigned , default = 5
+//Bit 15: 8, reg_adp_hlti_bst_core2 : core of the bandpass 2 (hdn-lpf0)- HP, default = 5 . unsigned , default = 5
+//Bit 7: 0, reg_adp_hlti_bst_core3 : core of the unsharp band (yuvin-hdn) - US, default = 3 . unsigned , default = 3
+#define HLTI_CON_2_GAIN_0 ((0x5037 << 2) + 0xff000000)
+//Bit 31:29, reg_adp_hlti_con_mode : con mode 0:[0, 0,-1, 1, 0, 0, 0]+[0, 0, 0, 1,-1, 0, 0], 1: [0, 0,-1, 0, 1, 0, 0], 2: [0,-1, 0, 0, 0, 1, 0], 3:[-1, 0, 0, 0, 0, 0, 1], 4: ....., default = 1. unsigned , default = 1
+//Bit 28:26, reg_adp_hlti_dx_mode : dx mode 0: [-1 1 0]; 1~7: [-1 (2x+1)"0" 1], default = 1 . unsigned , default = 1
+//Bit 25:24, reg_adp_hlti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0
+//Bit 23:16, reg_adp_hlti_con_2_gain0 25;, default = 25 . unsigned , default = 25
+//Bit 15: 8, reg_adp_hlti_con_2_gain1 60;, default = 60 . unsigned , default = 60
+//Bit 7: 0, reg_adp_hlti_con_2_gain2 0;, default = 5 . unsigned , default = 5
+#define HLTI_CON_2_GAIN_1 ((0x5038 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_hlti_con_2_gain3 96;, default = 96 . unsigned , default = 96
+//Bit 23:16, reg_adp_hlti_con_2_gain4 5;, default = 95 . unsigned , default = 95
+//Bit 15: 8, reg_adp_hlti_con_2_gain5 80;, default = 80 . unsigned , default = 80
+//Bit 7: 0, reg_adp_hlti_con_2_gain6 20;, default = 20 . unsigned , default = 20
+#define HLTI_OS_MARGIN ((0x5039 << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_adp_hlti_os_margin : margin for hlti overshoot, default = 0 . unsigned , default = 0
+#define VLTI_FLT_CON_CLP ((0x503a << 2) + 0xff000000)
+//Bit 31:15, reserved
+//Bit 14, reg_adp_vlti_en : enable bit of vlti, default = 1 . unsigned , default = 1
+//Bit 13:12, reg_adp_vlti_hxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 11:10, reg_adp_vlti_dxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 9: 8, reg_adp_vlti_han_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 7: 6, reg_adp_vlti_dan_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 5: 4, reg_adp_vlti_dx_mode : 0:[-1 1] 1:[-1 0 -1]; 2/3: [-1 0 0 0 -1], default = 1 . unsigned , default = 1
+//Bit 3, reserved
+//Bit 2, reg_adp_vlti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0
+//Bit 1, reserved
+//Bit 0, reg_adp_vlti_hard_clp_win : window size; 0: 1x3 window; 1: 1x5 window, default = 0 . unsigned , default = 0
+#define VLTI_BST_GAIN ((0x503b << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_adp_vlti_bst_gain0 : gain to boost filter [-1 2 -1];, default = 32 . unsigned , default = 32
+//Bit 15: 8, reg_adp_vlti_bst_gain1 : gain to boost filter [-1 0 2 0 -1];, default = 32 . unsigned , default = 32
+//Bit 7: 0, reg_adp_vlti_bst_gain2 : gain to boost filter usf, default = 32 . unsigned , default = 32
+#define VLTI_BST_CORE ((0x503c << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_adp_vlti_bst_core0 : coring to boost filter [-1 2 -1];, default = 5 . unsigned , default = 5
+//Bit 15: 8, reg_adp_vlti_bst_core1 : coring to boost filter [-1 0 2 0 -1];, default = 5 . unsigned , default = 5
+//Bit 7: 0, reg_adp_vlti_bst_core2 : coring to boost filter usf, default = 3 . unsigned , default = 3
+#define VLTI_CON_2_GAIN_0 ((0x503d << 2) + 0xff000000)
+//Bit 31:24, reg_adp_vlti_con_2_gain0 25;, default = 25 . unsigned , default = 25
+//Bit 23:16, reg_adp_vlti_con_2_gain1 60;, default = 60 . unsigned , default = 60
+//Bit 15: 8, reg_adp_vlti_con_2_gain2 0;, default = 5 . unsigned , default = 5
+//Bit 7: 0, reg_adp_vlti_con_2_gain3 96;, default = 96 . unsigned , default = 96
+#define VLTI_CON_2_GAIN_1 ((0x503e << 2) + 0xff000000)
+//Bit 31:24, reg_adp_vlti_con_2_gain4 5;, default = 95 . unsigned , default = 95
+//Bit 23:16, reg_adp_vlti_con_2_gain5 80;, default = 80 . unsigned , default = 80
+//Bit 15: 8, reg_adp_vlti_con_2_gain6 20;, default = 20 . unsigned , default = 20
+//Bit 7: 0, reg_adp_vlti_os_margin : margin for vlti overshoot, default = 0 . unsigned , default = 0
+#define VCTI_FLT_CON_CLP ((0x503f << 2) + 0xff000000)
+//Bit 31:15, reserved
+//Bit 14, reg_adp_vcti_en : enable bit of vlti, default = 1 . unsigned , default = 1
+//Bit 13:12, reg_adp_vcti_hxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 11:10, reg_adp_vcti_dxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 9: 8, reg_adp_vcti_han_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 7: 6, reg_adp_vcti_dan_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 5: 4, reg_adp_vcti_dx_mode : 0:[-1 1] 1:[-1 0 -1]; 2/3: [-1 0 0 0 -1], default = 1 . unsigned , default = 1
+//Bit 3, reserved
+//Bit 2, reg_adp_vcti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0
+//Bit 1, reserved
+//Bit 0, reg_adp_vcti_hard_clp_win : window size; 0: 1x3 window; 1: 1x5 window, default = 0 . unsigned , default = 0
+#define VCTI_BST_GAIN ((0x5040 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_adp_vcti_bst_gain0 : gain to boost filter [-1 2 -1];, default = 16 . unsigned , default = 16
+//Bit 15: 8, reg_adp_vcti_bst_gain1 : gain to boost filter [-1 0 2 0 -1];, default = 16 . unsigned , default = 16
+//Bit 7: 0, reg_adp_vcti_bst_gain2 : gain to boost filter usf, default = 16 . unsigned , default = 16
+#define VCTI_BST_CORE ((0x5041 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_adp_vcti_bst_core0 : coring to boost filter [-1 2 -1];, default = 5 . unsigned , default = 5
+//Bit 15: 8, reg_adp_vcti_bst_core1 : coring to boost filter [-1 0 2 0 -1];, default = 5 . unsigned , default = 5
+//Bit 7: 0, reg_adp_vcti_bst_core2 : coring to boost filter usf, default = 3 . unsigned , default = 3
+#define VCTI_CON_2_GAIN_0 ((0x5042 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_vcti_con_2_gain0 25;, default = 25 . unsigned , default = 25
+//Bit 23:16, reg_adp_vcti_con_2_gain1 60;, default = 60 . unsigned , default = 60
+//Bit 15: 8, reg_adp_vcti_con_2_gain2 0;, default = 5 . unsigned , default = 5
+//Bit 7: 0, reg_adp_vcti_con_2_gain3 96;, default = 96 . unsigned , default = 96
+#define VCTI_CON_2_GAIN_1 ((0x5043 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_vcti_con_2_gain4 5;, default = 95 . unsigned , default = 95
+//Bit 23:16, reg_adp_vcti_con_2_gain5 80;, default = 80 . unsigned , default = 80
+//Bit 15: 8, reg_adp_vcti_con_2_gain6 20;, default = 20 . unsigned , default = 20
+//Bit 7: 0, reg_adp_vcti_os_margin : margin for vcti overshoot, default = 0 . unsigned , default = 0
+#define SHARP_3DLIMIT ((0x5044 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_3d_mid_width ,width of left part of 3d input, dft = half size of input width default = 0 . unsigned , default = 960
+//Bit 15:13, reserved
+//Bit 12: 0, reg_3d_mid_height ,height of left part of 3d input, dft = half size of input height default = 0 . unsigned , default = 540
+#define DNLP_EN ((0x5045 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_dnlp_hblank
+//Bit 7: 1, reserved
+//Bit 0, reg_dnlp_en . unsigned , default = 1
+#define DEMO_CRTL ((0x5056 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18:17, demo_disp_position . unsigned , default = 2
+//Bit 16, demo_hsvsharp_enable . unsigned , default = 0
+//Bit 15:13, reserved
+//Bit 12: 0, demo_left_top_screen_width : . unsigned , default = 360
+#define SHARP_SR2_CTRL ((0x5057 << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24 reg_sr2_bic_pknr_bypass :
+//Bit 23:22 reserved
+//Bit 21:16, reg_sr2_pk_la_err_dis_rate : . unsigned , low angle and high angle error should not be no less than nearby_error*rate/64; default = 24
+//Bit 15:8, reg_sr2_pk_sad_diag_gain : . unsigned , gain to sad[2] and sad[6], 16 normalized to "1"; default = 16
+//Bit 7, reg_sr2_vert_outphs : . unsigned , default = 0
+//Bit 6, reg_sr2_horz_outphs : . unsigned , default = 0
+//Bit 5, reg_sr2_vert_ratio : . unsigned , default = 0
+//Bit 4, reg_sr2_hori_ratio : . unsigned , default = 0
+//Bit 3, reg_sr2_bic_norm : . unsigned , default = 1
+//Bit 2, reg_sr2_enable : . unsigned , default = 0
+//Bit 1, reg_sr2_sharp_prc_lr_hbic : . unsigned , default = 0
+//Bit 0, reg_sr2_sharp_prc_lr : lti/cti/nr/peaking processing using LR grid, 0: on HR grid; 1:on LR grid, horizontally no upscale, but using simple bic . unsigned , default = 0
+#define SHARP_SR2_YBIC_HCOEF0 ((0x5058 << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_y_bic_hcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel Filter will be normalized to 128 as â?â? default=0
+//Bit 23:16, reg_sr2_y_bic_hcoef02 the same as above; default=0
+//Bit 15: 8, reg_sr2_y_bic_hcoef01 the same as above; default=64
+//Bit 7: 0, reg_sr2_y_bic_hcoef00 the same as above; default=0
+#define SHARP_SR2_YBIC_HCOEF1 ((0x5059 << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_y_bic_hcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channel,Filter will be normalized to 128 as â?â? default=-4
+//Bit 23:16, reg_sr2_y_bic_hcoef12 the same as above; default=36
+//Bit 15: 8, reg_sr2_y_bic_hcoef11 the same as above; default=36
+//Bit 7: 0, reg_sr2_y_bic_hcoef10 the same as above; default=-4
+#define SHARP_SR2_CBIC_HCOEF0 ((0x505a << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_c_bic_hcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel ,Filter will be normalized to 128 as â?â? default=0
+//Bit 23:16, reg_sr2_c_bic_hcoef02 the same as above; default=21
+//Bit 15: 8, reg_sr2_c_bic_hcoef01 the same as above; default=22
+//Bit 7: 0, reg_sr2_c_bic_hcoef00 the same as above; default=21
+#define SHARP_SR2_CBIC_HCOEF1 ((0x505b << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_c_bic_hcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channel,Filter will be normalized to 128 as â?â? default=-4
+//Bit 23:16, reg_sr2_c_bic_hcoef12 the same as above; default=36
+//Bit 15: 8, reg_sr2_c_bic_hcoef11 the same as above; default=36
+//Bit 7: 0, reg_sr2_c_bic_hcoef10 the same as above; default=-4
+#define SHARP_SR2_YBIC_VCOEF0 ((0x505c << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_y_bic_vcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel, Filter will be normalized to 128 as â?â? default=0
+//Bit 23:16, reg_sr2_y_bic_vcoef02 the same as above; default=0
+//Bit 15: 8, reg_sr2_y_bic_vcoef01 the same as above; default=64
+//Bit 7: 0, reg_sr2_y_bic_vcoef00 the same as above; default=0
+#define SHARP_SR2_YBIC_VCOEF1 ((0x505d << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_y_bic_vcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channe, lFilter will be normalized to 128 as â?â? default=-4
+//Bit 23:16, reg_sr2_y_bic_vcoef12 the same as above; default=36
+//Bit 15: 8, reg_sr2_y_bic_vcoef11 the same as above; default=36
+//Bit 7: 0, reg_sr2_y_bic_vcoef10 the same as above; default=-4
+#define SHARP_SR2_CBIC_VCOEF0 ((0x505e << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_c_bic_vcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel, Filter will be normalized to 128 as â?â? default=0
+//Bit 23:16, reg_sr2_c_bic_vcoef02 the same as above; default=21
+//Bit 15: 8, reg_sr2_c_bic_vcoef01 the same as above; default=22
+//Bit 7: 0, reg_sr2_c_bic_vcoef00 the same as above; default=21
+#define SHARP_SR2_CBIC_VCOEF1 ((0x505f << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_c_bic_vcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channel,Filter will be normalized to 128 as â?â? default=-4
+//Bit 23:16, reg_sr2_c_bic_vcoef12 the same as above; default=36
+//Bit 15: 8, reg_sr2_c_bic_vcoef11 the same as above; default=36
+//Bit 7: 0, reg_sr2_c_bic_vcoef10 the same as above; default=-4
+#define SHARP_SR2_MISC ((0x5060 << 2) + 0xff000000)
+//Bit 31:2, reserved
+//Bit 1, reg_sr2_cmpmux_bef : . unsigned , default = 0,0 no swap anf for YUV->YUV; 1, swapped and for RGB->GBR;
+//Bit 0, reg_sr2_cmpmux_aft : . unsigned , default = 0,0 no swap anf for YUV->YUV; 1, swapped and for GBR-RGB;
+#define SHARP_SR3_SAD_CTRL ((0x5061 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_sr3_pk_sad_core_rate // u6: rate of coring for sad(theta) - sad(theta+pi/2)*rate/64
+//Bit 23:22 reserved
+//Bit 21:16 reg_sr3_lti_sad_core_rate // u6: rate of coring for sad(theta) - sad(theta+pi/2)*rate/64 , default= 6
+//Bit 15:14 reserved
+//Bit 13:8 reg_sr3_cti_sad_core_rate // u6: rate of coring for sad(theta) - sad(theta+pi/2)*rate/64 , default= 6
+//Bit 7, reg_sr3_lti_hsad_mode // u1: mode for hsad of lti caluclation; 0: block based; 1:othor shape; default= 1
+//Bit 6, reg_sr3_cti_hsad_mode // u1: mode for hsad of cti caluclation; 0: block based; 1:othor shape; default= 1
+//Bit 5, reg_sr3_lti_dsad_mode // u1: mode for dsad of lti caluclation, 0: block based; 1:othor shape; default= 1
+//Bit 4, reg_sr3_cti_dsad_mode // u1: mode for dsad of cti caluclation, 0: block based; 1:othor shape; default= 1
+//Bit 3, reg_sr3_lti_vsad_mode // u1: mode for vsad of lti caluclation, 0: block based; 1:othor shape; default= 1
+//Bit 2, reg_sr3_cti_vsad_mode // u1: mode for vsad of cti caluclation, 0: block based; 1:othor shape; default= 1
+//Bit 1, reg_sr3_lti_hsad_hlpf // u1: hlpf for hsad of lti caluclation, 0: no hlpf; 1: with [1 2 1] hlpf; default= 1
+//Bit 0, reg_sr3_cti_hsad_hlpf // u1: hlpf for hsad of cti caluclation, 0: no hlpf; 1: with [1 2 1] hlpf; default= 1
+#define SHARP_SR3_PK_CTRL0 ((0x5062 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11, reg_sr3_pk_sad_mode // u1: mode for sad of peaking and noise reduction, 0: block based; 1:othor shape; default= 1
+//Bit 10, reg_sr3_pk_hsad_hlpf // u1: hlpf for hsad for peaking caluclation, 0: no hlpf; 1: with [1 2 2 2 1] hlpf; default= 1
+//Bit 9, reg_sr3_pk_vsad_hlpf // u1: hlpf for vsad for peaking caluclation, 0: no hlpf; 1: with [1 2 2 2 1] hlpf; default= 1
+//Bit 8, reg_sr3_pk_dsad_hlpf // u1: hlpf for dsad for peaking caluclation, 0: no hlpf; 1: with [1 2 2 2 1] hlpf; default= 1
+//Bit 7:6, reg_sr3_pk_hpdrt_mode // u2: mode for HPdrt filter: default= 3
+//Bit 5:4, reg_sr3_pk_bpdrt_mode // u2: mode for BPdrt filter: default= 3
+//Bit 3:2, reg_sr3_pk_drtbld_range // u2: range of the min2 and min direction distance; default =1
+//Bit 1, reserved
+//Bit 0, reg_sr3_pk_ti_blend_mode // u1: blend mode of the TI and PK results: default = 0;
+#define SHARP_SR3_PK_CTRL1 ((0x5063 << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30:28, reg_sr3_pk_hp_hvcon_replace8_maxsad //u3: replace HP hvcon by maxsad, default =1
+//Bit 27, reserved
+//Bit 26:24, reg_sr3_pk_bp_hvcon_replace8_maxsad //u3: replace HP hvcon by maxsad, default =1
+//Bit 23:16, reg_sr3_pk_hp_hvcon_replace8lv_gain //u8: gain to local variant before calculating the hv gain for peaking, normalized to 32 as "1" default = 32;
+//Bit 15:8, reg_sr3_pk_bp_hvcon_replace8lv_gain //u8: gain to local variant before calculating the hv gain for peaking, normalized to 32 as "1" default = 32;
+//Bit 7, reg_sr3_sad_intlev_mode //u1: interleave detection xerr mode: 0 max; 1:sum default=1
+//Bit 6, reg_sr3_sad_intlev_mode1 //u1: mode 1 of using diagonal protection: 0: no digonal protection; 1: with diagonal protection default=1
+//Bit 5:0, reg_sr3_sad_intlev_gain //u6: interleave detection for sad gain applied, normalized to 8 as 1 default=12
+#define SHARP_DEJ_CTRL ((0x5064 << 2) + 0xff000000)
+//Bit 31:4 reserved
+//Bit 15:8, reg_sr3_dejaggy_hblank // u8
+//Bit 7:4 reserved
+//Bit 3:2, reg_sr3_dejaggy_sameside_prtct // u2: enable of sr3 dejaggy same side curve protect from filter, [0] for proc, [1] for ctrl path, default=3
+//Bit 1, reg_sr3_dejaggy_sameside_mode // u1: mode of the sameside flag decision: default =1
+//Bit 0, reg_sr3_dejaggy_enable // u1: enable of sr3 dejaggy: default =0
+#define SHARP_DEJ_ALPHA ((0x5065 << 2) + 0xff000000)
+//Bit 31:28, reg_sr3_dejaggy_ctrlchrm_alpha_1 //u4: alpha for LR video LPF, default = 0
+//Bit 27:24, reg_sr3_dejaggy_ctrlchrm_alpha_0 //u4: alpha for LR video LPF, default = 15
+//Bit 23:20, reg_sr3_dejaggy_ctrlluma_alpha_1 //u4: alpha for LR video LPF, default = 0
+//Bit 19:16, reg_sr3_dejaggy_ctrlluma_alpha_0 //u4: alpha for LR video LPF, default = 15
+//Bit 15:12, reg_sr3_dejaggy_procchrm_alpha_1 //u4: alpha for LR video LPF, default = 4
+//Bit 11:8, reg_sr3_dejaggy_procchrm_alpha_0 //u4: alpha for LR video LPF, default = 6
+//Bit 7:4, reg_sr3_dejaggy_procluma_alpha_1 //u4: alpha for LR video LPF, default = 4
+//Bit 3:0, reg_sr3_dejaggy_procluma_alpha_0 //u4: alpha for LR video LPF, default = 6
+#define SHARP_SR3_DRTLPF_EN ((0x5066 << 2) + 0xff000000)
+//Bit 31:15 reserved
+//Bit 14:8, reg_pk_debug_edge . unsigned , default = 0
+//Bit 7, reserved
+//Bit 6:4, reg_sr3_drtlpf_theta_en //u1x3 theta (pure vertical and horizontal HF burst protection) enable. 0: not enable, 1:enable protection
+//Bit 3, reserved
+//Bit 2:0 reg_sr3_drtlpf_enable //u1x3 directional lpf on luma U and V channels, default = 7
+#define SHARP_SR3_DRTLPF_ALPHA_0 ((0x5067 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_sr3_drtlpf_alpha3 //u6: directional lpf alpha coef for min_sad/max_sad comparied, default = 9
+//Bit 23:22 reserved
+//Bit 21:16 reg_sr3_drtlpf_alpha2 //u6: default =10
+//Bit 15:14 reserved
+//Bit 13:8 reg_sr3_drtlpf_alpha1 //u6: default = 11
+//Bit 7:6 reserved
+//Bit 5:0 reg_sr3_drtlpf_alpha0 //u6: default = 12
+#define SHARP_SR3_DRTLPF_ALPHA_1 ((0x5068 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_sr3_drtlpf_alpha7 //u6: directional lpf alpha coef for min_sad/max_sad comparied, default = 1
+//Bit 23:22 reserved
+//Bit 21:16 reg_sr3_drtlpf_alpha6 //u6: default = 4
+//Bit 15:14 reserved
+//Bit 13:8 reg_sr3_drtlpf_alpha5 //u6: default = 7
+//Bit 7:6 reserved
+//Bit 5:0 reg_sr3_drtlpf_alpha4 //u6: default = 8
+#define SHARP_SR3_DRTLPF_ALPHA_2 ((0x5069 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_sr3_drtlpf_alpha11 //u6: directional lpf alpha coef for min_sad/max_sad comparied, default = 0
+//Bit 23:22 reserved
+//Bit 21:16 reg_sr3_drtlpf_alpha10 //u6: default = 0
+//Bit 15:14 reserved
+//Bit 13:8 reg_sr3_drtlpf_alpha9 //u6: default = 0
+//Bit 7:6 reserved
+//Bit 5:0 reg_sr3_drtlpf_alpha8 //u6: default = 0
+#define SHARP_SR3_DRTLPF_ALPHA_OFST ((0x506a << 2) + 0xff000000)
+//Bit 31:28 reg_sr3_drtlpf_alpha_ofst7 //s4: directional lpf alpha coef ofset of each directions, default = -8
+//Bit 27:24 reg_sr3_drtlpf_alpha_ofst6 //s4: default = -8
+//Bit 23:20 reg_sr3_drtlpf_alpha_ofst5 //s4: default = -8
+//Bit 19:16 reg_sr3_drtlpf_alpha_ofst4 //s4: default = -8
+//Bit 15:12 reg_sr3_drtlpf_alpha_ofst3 //s4: default = -8
+//Bit 11:8 reg_sr3_drtlpf_alpha_ofst2 //s4: default = -8
+//Bit 7:4 reg_sr3_drtlpf_alpha_ofst1 //s4: default = -8
+//Bit 3:0 reg_sr3_drtlpf_alpha_ofst0 //s4: default = -8
+#define SHARP_SR3_DERING_CTRL ((0x506b << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_sr3_dering_enable // u3: dering enable bits; default = 1
+//Bit 27 reserved
+//Bit 26:24 reg_sr3_dering_varlpf_mode // u3: local variant LPF mode: 0 no filter, 1, errosion 3x3; 2: 3x3 lpf; 3 and up: 3x3 errosion + lpf default = 3
+//Bit 23:20 reg_sr3_dering_maxrange // u4: maximum:range of dering in LR resolution, max to 12; default = 9
+//Bit 19:18 reserved
+//Bit 17:16 reg_sr3_dering_lcvar_blend_mode // u2: mode for lcvar calculation: 0: HVblend; 1: diagblend; 2: HVblend+V (for hring); 3: HVblend+ DiagBlend default = 2
+//Bit 15:8 reg_sr3_dering_lcvar_gain // u8: gain to local variant and normalized to 32 as "1" default = 64
+//Bit 7:0 reg_sr3_dering_lcvar_nearby_maxsad_th // u8: threshold to use nearer side maxsad if that side sad is larger than this threshold, ortherwise, use the max one default = 28
+#define SHARP_SR3_DERING_LUMA2PKGAIN_0TO3 ((0x506c << 2) + 0xff000000)
+//Bit 31:24 reg_sr3_dering_luma2pkgain3 // u8: level limit(for th0<bpcon<th1) of curve for dering pkgain based on LPF luma level. default=255
+//Bit 23:16 reg_sr3_dering_luma2pkgain2 // u8: level limit(for bpcon<th0) of curve for dering pkgain based on LPF luma level. default=255
+//Bit 15:8 reg_sr3_dering_luma2pkgain1 // u8: threshold1 of curve for dering pkgain based on LPF luma level default =200
+//Bit 7:0 reg_sr3_dering_luma2pkgain0 // u8: threshold0 of curve for dering pkgain based on LPF luma level. default =30
+#define SHARP_SR3_DERING_LUMA2PKGAIN_4TO6 ((0x506d << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_sr3_dering_luma2pkgain6 // u8: rate1 (for bpcon>th1) of curve for dering pkgain based on LPF luma level. default =24
+//Bit 15:8 reg_sr3_dering_luma2pkgain5 // u8: rate0 (for bpcon<th0) of curve for dering pkgain based on LPF luma level. dfault =50
+//Bit 7:0 reg_sr3_dering_luma2pkgain4 // u8: level limit(for bpcon>th1) of curve for dering pkgain based on LPF luma level. default =255
+#define SHARP_SR3_DERING_LUMA2PKOS_0TO3 ((0x506e << 2) + 0xff000000)
+//Bit 31:24 reg_sr3_dering_luma2pkos3 // u8: level limit(for th0<bpcon<th1) of curve for dering pkOS based on LPF luma level. default=255
+//Bit 23:16 reg_sr3_dering_luma2pkos2 // u8: level limit(for bpcon<th0) of curve for dering pkOS based on LPF luma level. default=255
+//Bit 15:8 reg_sr3_dering_luma2pkos1 // u8: threshold1 of curve for dering pkOS based on LPF luma level default =200
+//Bit 7:0 reg_sr3_dering_luma2pkos0 // u8: threshold0 of curve for dering pkOS based on LPF luma leve. default =30
+#define SHARP_SR3_DERING_LUMA2PKOS_4TO6 ((0x506f << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_sr3_dering_luma2pkos6 // u8: rate1 (for bpcon>th1) of curve for dering pkOS based on LPF luma level. default =24
+//Bit 15:8 reg_sr3_dering_luma2pkos5 // u8: rate0 (for bpcon<th0) of curve for dering pkOS based on LPF luma level. dfault =50
+//Bit 7:0 reg_sr3_dering_luma2pkos4 // u8: level limit(for bpcon>th1) of curve for dering pkOS based on LPF luma level. default =255
+#define SHARP_SR3_DERING_GAINVS_MADSAD ((0x5070 << 2) + 0xff000000)
+//Bit 31:28 reg_sr3_dering_gainvs_maxsad7 //u4: pkgain vs maxsad value, 8 node interpolations, default = 0
+//Bit 27:24 reg_sr3_dering_gainvs_maxsad6 //u4: default = 0
+//Bit 23:20 reg_sr3_dering_gainvs_maxsad5 //u4: default = 0
+//Bit 19:16 reg_sr3_dering_gainvs_maxsad4 //u4: default = 0
+//Bit 15:12 reg_sr3_dering_gainvs_maxsad3 //u4: default = 0
+//Bit 11:8 reg_sr3_dering_gainvs_maxsad2 //u4: default = 0
+//Bit 7:4 reg_sr3_dering_gainvs_maxsad1 //u4: default = 4
+//Bit 3:0 reg_sr3_dering_gainvs_maxsad0 //u4: default = 8
+#define SHARP_SR3_DERING_GAINVS_VR2MAX ((0x5071 << 2) + 0xff000000)
+//Bit 31:28 reg_sr3_dering_gainvs_vr2max7 //u4: pkgain vs ratio = max(local_var, floor)/maxsad nearby, default = 15
+//Bit 27:24 reg_sr3_dering_gainvs_vr2max6 //u4: default = 15
+//Bit 23:20 reg_sr3_dering_gainvs_vr2max5 //u4: default = 15
+//Bit 19:16 reg_sr3_dering_gainvs_vr2max4 //u4: default = 15
+//Bit 15:12 reg_sr3_dering_gainvs_vr2max3 //u4: default = 14
+//Bit 11:8 reg_sr3_dering_gainvs_vr2max2 //u4: default = 12
+//Bit 7:4 reg_sr3_dering_gainvs_vr2max1 //u4: default = 2
+//Bit 3:0 reg_sr3_dering_gainvs_vr2max0 //u4: default = 0
+#define SHARP_SR3_DERING_PARAM0 ((0x5072 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_sr3_dering_lcvar_floor //u8: local varianet no smaller than this value to calculate dgain max(localvar,x)/maxsad. default = 10
+//Bit 15:8 reg_sr3_dering_vr2max_gain //u8: gain to max(local_var, floor)/maxsad before feeding to LUT. default = 32
+//Bit 7:6 reserved
+//Bit 5:0 reg_sr3_dering_vr2max_limt //u6: limit of maxsad to max(local_var, floor)*(max(maxsad, lmit))/maxsad. default = 16
+#define SHARP_SR3_DRTLPF_THETA ((0x5073 << 2) + 0xff000000)
+//Bit 31:0 reg_sr3_drtlpf_theta //u4x8: directional lpf beta coef for min_sad/min2_sad compared to x=0:7 correspond to[1:8]/16; 0 means no drtLPF, 15: 100% alpha dependant drtLPF
+#define SHARP_SATPRT_CTRL ((0x5074 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 reg_satprt_sat_core //u8: 4x will be coring to cor(irgb_max-irgb_min) to calculate the oy_delt, the smaller the more protection to color, the larger only the rich color will be protected;
+//Bit 15:8 reg_satprt_sat_rate //u8: rate to cor(irgb_max-irgb_min) to calculate the oy_delt, the larger the more protection to rich color; norm 16 as 1
+//Bit 7:4 reserved
+//Bit 3:2 reg_satprt_csc_mode //u2: csc mode of current yuv input: 0:601, 1:709, 2:BT2020 NCL, 3:reserved
+//Bit 1 reg_satprt_is_lmt //u1: flag telling the YUV is limited range data or full range data, 0 full range, 1: limited range
+//Bit 0 reg_satprt_enable //u1: enable of saturation protection for dnlp adjustments
+#define SHARP_SATPRT_DIVM ((0x5075 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:0 reg_satprt_div_m //u8x3, 1/m, normalized to 128 as 1, default=1
+#define SHARP_DB_FLT_CTRL ((0x5077 << 2) + 0xff000000)
+//Bit 31:27 reserved
+//Bit 26 reg_nrdeband_reset1
+//Bit 25 reg_nrdeband_reset0
+//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 0:yuv 1:RGB
+//Bit 23 reg_nrdeband_en11 // unsigned , default = 1 debanding registers of side lines, [0] for luma, same for below
+//Bit 22 reg_nrdeband_en10 // unsigned , default = 1 debanding registers of side lines, [1] for chroma, same for below
+//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
+//Bit 16 reserved
+//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
+//Bit 12 reserved
+//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6
+//Bit 8 reserved
+//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 debanding random hp portion xor, [0] for luma
+//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 debanding random hp portion xor, [1] for chroma
+//Bit 5 reg_nrdeband_en1 // unsigned , default = 1 debanding registers, for luma
+//Bit 4 reg_nrdeband_en0 // unsigned , default = 1 debanding registers, for chroma
+//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+#define SHARP_DB_FLT_RANDLUT ((0x5079 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:21 reg_nrdebandslut7 // unsigned , default = 1 lut0
+//Bit 20:18 reg_nrdebandslut6 // unsigned , default = 1 lut0
+//Bit 17:15 reg_nrdebandslut5 // unsigned , default = 1 lut0
+//Bit 14:12 reg_nrdebandslut4 // unsigned , default = 1 lut0
+//Bit 11: 9 reg_nrdebandslut3 // unsigned , default = 1 lut0
+//Bit 8: 6 reg_nrdebandslut2 // unsigned , default = 1 lut0
+//Bit 5: 3 reg_nrdebandslut1 // unsigned , default = 1 lut0
+//Bit 2: 0 reg_nrdebandslut0 // unsigned , default = 1 lut0
+#define SHARP_DB_FLT_PXI_THRD ((0x507a << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 to luma/|u/v| for using the denoise
+//Bit 15:10 reserved
+//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 to luma/|u/v| for using the denoise
+#define SHARP_DB_FLT_SEED_Y ((0x507b << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 noise adding seed for Y. seed[0]= 0x60a52f20; as default
+#define SHARP_DB_FLT_SEED_U ((0x507c << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 noise adding seed for U. seed[0]= 0x60a52f27; as default
+#define SHARP_DB_FLT_SEED_V ((0x507d << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define SHARP_PKGAIN_VSLUMA_LUT_L ((0x507e << 2) + 0xff000000)
+//Bit 31:28 reg_pkgain_vsluma_lut7;
+//Bit 27:24 reg_pkgain_vsluma_lut6;
+//Bit 23:20 reg_pkgain_vsluma_lut5;
+//Bit 19:16 reg_pkgain_vsluma_lut4;
+//Bit 15:12 reg_pkgain_vsluma_lut3;
+//Bit 11: 8 reg_pkgain_vsluma_lut2;
+//Bit 7: 4 reg_pkgain_vsluma_lut1;
+//Bit 3: 0 reg_pkgain_vsluma_lut0;
+#define SHARP_PKGAIN_VSLUMA_LUT_H ((0x507f << 2) + 0xff000000)
+//Bit 31: 4 reserved;
+//Bit 3: 0 reg_pkgain_vsluma_lut8;
+#define SHARP_PKOSHT_VSLUMA_LUT_L ((0x5080 << 2) + 0xff000000)
+//Bit 31:28 reg_pkosht_vsluma_lut7;
+//Bit 27:24 reg_pkosht_vsluma_lut6;
+//Bit 23:20 reg_pkosht_vsluma_lut5;
+//Bit 19:16 reg_pkosht_vsluma_lut4;
+//Bit 15:12 reg_pkosht_vsluma_lut3;
+//Bit 11: 8 reg_pkosht_vsluma_lut2;
+//Bit 7: 4 reg_pkosht_vsluma_lut1;
+//Bit 3: 0 reg_pkosht_vsluma_lut0;
+#define SHARP_PKOSHT_VSLUMA_LUT_H ((0x5081 << 2) + 0xff000000)
+//Bit 31: 4 reserved;
+//Bit 3: 0 reg_pkosht_vsluma_lut8;
+#define SHARP_SATPRT_LMT_RGB1 ((0x5082 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 reg_satprt_lmt_g //u12x3, limit of the rgb channel, for limited range RGB, set to 960, otherwise set to 1023
+//Bit 15:12 reserved
+//Bit 11:0 reg_satprt_lmt_r //u12x3, limit of the rgb channel, for limited range RGB, set to 960, otherwise set to 1023
+#define SHARP_SATPRT_LMT_RGB2 ((0x5083 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11:0 reg_satprt_lmt_b //u12x3, limit of the rgb channel, for limited range RGB, set to 960, otherwise set to 1023
+#define SHARP_GATE_CLK_CTRL_0 ((0x5084 << 2) + 0xff000000)
+//Bit 31: 0 reg_gate_clk_ctrl_0
+#define SHARP_GATE_CLK_CTRL_1 ((0x5085 << 2) + 0xff000000)
+//Bit 31: 0 reg_gate_clk_ctrl_1
+#define SHARP_GATE_CLK_CTRL_2 ((0x5086 << 2) + 0xff000000)
+//Bit 31: 0 reg_gate_clk_ctrl_2
+#define SHARP_GATE_CLK_CTRL_3 ((0x5087 << 2) + 0xff000000)
+//Bit 31: 0 reg_gate_clk_ctrl_3
+#define SHARP_DPS_CTRL ((0x5088 << 2) + 0xff000000)
+//Bit 31: 0 reg_sharp_dps_ctrl
+#define DNLP_00 ((0x5090 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid0 : dnlp00 . unsigned , default = 32'h00008060
+#define DNLP_01 ((0x5091 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid1 : dnlp01 . unsigned , default = 32'h100e0c0a
+#define DNLP_02 ((0x5092 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid2 : dnlp02 . unsigned , default = 32'h1a171412
+#define DNLP_03 ((0x5093 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid3 : dnlp03 . unsigned , default = 32'h2824201d
+#define DNLP_04 ((0x5094 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid4 : dnlp04 . unsigned , default = 32'h3834302c
+#define DNLP_05 ((0x5095 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid5 : dnlp05 . unsigned , default = 32'h4b45403c
+#define DNLP_06 ((0x5096 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid6 : dnlp06 . unsigned , default = 32'h605b5550
+#define DNLP_07 ((0x5097 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid7 : dnlp07 . unsigned , default = 32'h80787068
+#define DNLP_08 ((0x5098 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid8 : dnlp08 . unsigned , default = 32'ha0989088
+#define DNLP_09 ((0x5099 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid9 : dnlp09 . unsigned , default = 32'hb8b2aca6
+#define DNLP_10 ((0x509a << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid10 : dnlp10 . unsigned , default = 32'hc8c4c0bc
+#define DNLP_11 ((0x509b << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid11 : dnlp11 . unsigned , default = 32'hd4d2cecb
+#define DNLP_12 ((0x509c << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid12 : dnlp12 . unsigned , default = 32'hdad8d7d6
+#define DNLP_13 ((0x509d << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid13 : dnlp13 . unsigned , default = 32'he2e0dedc
+#define DNLP_14 ((0x509e << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid14 : dnlp14 . unsigned , default = 32'hf0ece8e4
+#define DNLP_15 ((0x509f << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid15 : dnlp15 . unsigned , default = 32'hfffcf8f4
+#define DNLP_16 ((0x50a0 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid16 : dnlp16 . unsigned , default = 32'h08060402
+#define DNLP_17 ((0x50a1 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid17 : dnlp17 . unsigned , default = 32'h100e0c0a
+#define DNLP_18 ((0x50a2 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid18 : dnlp18 . unsigned , default = 32'h1a171412
+#define DNLP_19 ((0x50a3 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid19 : dnlp19 . unsigned , default = 32'h2824201d
+#define DNLP_20 ((0x50a4 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid20 : dnlp20 . unsigned , default = 32'h3834302c
+#define DNLP_21 ((0x50a5 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid21 : dnlp21 . unsigned , default = 32'h4b45403c
+#define DNLP_22 ((0x50a6 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid22 : dnlp22 . unsigned , default = 32'h605b5550
+#define DNLP_23 ((0x50a7 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid23 : dnlp23 . unsigned , default = 32'h80787068
+#define DNLP_24 ((0x50a8 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid24 : dnlp24 . unsigned , default = 32'ha0989088
+#define DNLP_25 ((0x50a9 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid25 : dnlp25 . unsigned , default = 32'hb8b2aca6
+#define DNLP_26 ((0x50aa << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid26 : dnlp26 . unsigned , default = 32'hc8c4c0bc
+#define DNLP_27 ((0x50ab << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid27 : dnlp27 . unsigned , default = 32'hd4d2cecb
+#define DNLP_28 ((0x50ac << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid28 : dnlp28 . unsigned , default = 32'hdad8d7d6
+#define DNLP_29 ((0x50ad << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid29 : dnlp29 . unsigned , default = 32'he2e0dedc
+#define DNLP_30 ((0x50ae << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid30 : dnlp30 . unsigned , default = 32'hf0ece8e4
+#define DNLP_31 ((0x50af << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid31 : dnlp31 . unsigned , default = 32'hfffcf8f4
+#define SHARP_SYNC_CTRL ((0x50b0 << 2) + 0xff000000)
+//Bit 15: 0, reg_sync_ctrl //reg_sync_ctrl: shaddow register control . unsigned , default = 0
+#define LC_INPUT_MUX ((0x50b1 << 2) + 0xff000000)
+//Bit 31:7 reserved
+//Bit 6:4 reg_lcinput_ysel //u3, local contrast luma input options 0: org_y; 1: gau_y; 2: gauadp_y; 3: edgadplpf_y; 4: nr_y;5: lti_y; 6: pk_y (before os);7: pk_y (after os) . unsigned , default = 5
+//Bit 3 reserved
+//Bit 2:0 reg_lcinput_csel //u3, local contrast chroma input options 0: org_c; 1: gau_c; 2: gauadp_c; 3: edgadplpf_c; 4: nr_c;5: cti_c; 6: pk_c . unsigned , default = 5
+#define NR_GAU_YH_COEF02 ((0x50b2 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:20 reg_nr_gau_yhcoef_0 //s10, luma's horizontal adaptive coef0 . signed , default = 32
+//Bit 19:10 reg_nr_gau_yhcoef_1 //s10, luma's horizontal adaptive coef1 . signed , default = 32
+//Bit 9: 0 reg_nr_gau_yhcoef_2 //s10, luma's horizontal adaptive coef2 . signed , default = 16
+#define NR_GAU_YH_COEF34 ((0x50b3 << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:10 reg_nr_gau_yhcoef_3 //s10, luma's horizontal adaptive coef3 . signed , default = 0
+//Bit 9: 0 reg_nr_gau_yhcoef_4 //s10, luma's horizontal adaptive coef4 . signed , default = 0
+#define NR_GAU_YV_COEF1 ((0x50b4 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:20 reg_nr_gau_yvcoef_0 //s10, luma's vertical adaptive coef0 . signed , default = 32
+//Bit 19:10 reg_nr_gau_yvcoef_1 //s10, luma's vertical adaptive coef1 . signed , default = 32
+//Bit 9: 0 reg_nr_gau_yvcoef_2 //s10, luma's vertical adaptive coef2 . signed , default = 16
+#define NR_GAU_CH_COEF02 ((0x50b5 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:20 reg_nr_gau_chcoef_0 //s10, chroma's horizontal adaptive coef0 . signed , default = 32
+//Bit 19:10 reg_nr_gau_chcoef_1 //s10, chroma's horizontal adaptive coef1 . signed , default = 32
+//Bit 9: 0 reg_nr_gau_chcoef_2 //s10, chroma's horizontal adaptive coef2 . signed , default = 16
+#define NR_GAU_CH_COEF34 ((0x50b6 << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:10 reg_nr_gau_chcoef_3 //s10, chroma's horizontal adaptive coef3 . signed , default = 0
+//Bit 9: 0 reg_nr_gau_chcoef_4 //s10, chroma's horizontal adaptive coef4 . signed , default = 0
+#define NR_GAU_CV_COEF1 ((0x50b7 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:20 reg_nr_gau_cvcoef_0 //s10, chroma's vertical adaptive coef0 . signed , default = 32
+//Bit 19:10 reg_nr_gau_cvcoef_1 //s10, chroma's vertical adaptive coef1 . signed , default = 32
+//Bit 9: 0 reg_nr_gau_cvcoef_2 //s10, chroma's vertical adaptive coef2 . signed , default = 16
+#define SHARP_DB_FLT_CTRL1 ((0x50b8 << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:16 reg_nrdeband_noise_rs // unsigned , default = 2
+//Bit 15:12 reg_nrdeband_randgain // unsigned , default = 8
+//Bit 11 reserved
+//Bit 10: 8 reserved
+//Bit 7 reserved
+//Bit 6: 4 reserved
+//Bit 3 reserved
+//Bit 2: 0 reserved
+#define SHARP_DB_FLT_LUMA_THRD ((0x50b9 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_luma_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_luma_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_luma_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_luma_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else
+#define SHARP_DB_FLT_CHRM_THRD ((0x50ba << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_chrm_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_chrm_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_chrm_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_chrm_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif
+#define LC_TOP_CTRL ((0x50c0 << 2) + 0xff000000)
+ //Bit 31 :8 reg_lc_misc U RW default = 'h0
+ //Bit 7 :5 reserved U RW default = 'h0 None
+ //Bit 4 reg_lc_enable U RW default = 'h1 enable signal for local contrast enhancement, 1-enable; 0 disable
+ //Bit 3 :1 reserved U RW default = 'h0 None
+ //Bit 0 reg_lc_blkblend_mode U RW default = 'h1 use bilinear interpolation between blocks, 0: no interpolation 1: blender enabled
+#define LC_HV_NUM ((0x50c1 << 2) + 0xff000000)
+ //Bit 31 :13 reserved U RW default = 'h0 None
+ //Bit 12 :8 reg_lc_blk_hnum U RW default = 'hc lc processing region number of V, maximum to (STA_LEN_V-1) (0~8)
+ //Bit 7 :5 reserved U RW default = 'h0 None
+ //Bit 4 :0 reg_lc_blk_vnum U RW default = 'h8 lc processing region number of H, maximum to (STA_LEN_H-1) (0~12)
+#define LC_SAT_LUT_0_1 ((0x50c2 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_0 U RW default = 'hc saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_1 U RW default = 'h20 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_2_3 ((0x50c3 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_2 U RW default = 'h38 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_3 U RW default = 'h54 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_4_5 ((0x50c4 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_4 U RW default = 'h73 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_5 U RW default = 'h95 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_6_7 ((0x50c5 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_6 U RW default = 'hb9 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_7 U RW default = 'hdf saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_8_9 ((0x50c6 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_8 U RW default = 'h107 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_9 U RW default = 'h131 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_10_11 ((0x50c7 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_10 U RW default = 'h15c saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_11 U RW default = 'h189 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_12_13 ((0x50c8 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_12 U RW default = 'h1b8 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_13 U RW default = 'h1e8 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_14_15 ((0x50c9 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_14 U RW default = 'h219 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_15 U RW default = 'h24c saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_16_17 ((0x50ca << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_16 U RW default = 'h280 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_17 U RW default = 'h2b6 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_18_19 ((0x50cb << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_18 U RW default = 'h2ec saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_19 U RW default = 'h324 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_20_21 ((0x50cc << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_20 U RW default = 'h35d saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_21 U RW default = 'h397 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_22_23 ((0x50cd << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_22 U RW default = 'h3d2 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_23 U RW default = 'h40e saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_24_25 ((0x50ce << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_24 U RW default = 'h44b saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_25 U RW default = 'h489 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_26_27 ((0x50cf << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_26 U RW default = 'h4c8 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_27 U RW default = 'h507 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_28_29 ((0x50d0 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_28 U RW default = 'h548 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_29 U RW default = 'h58a saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_30_31 ((0x50d1 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_30 U RW default = 'h5cd saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_31 U RW default = 'h610 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_32_33 ((0x50d2 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_32 U RW default = 'h654 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_33 U RW default = 'h69a saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_34_35 ((0x50d3 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_34 U RW default = 'h6e0 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_35 U RW default = 'h726 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_36_37 ((0x50d4 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_36 U RW default = 'h76e saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_37 U RW default = 'h7b6 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_38_39 ((0x50d5 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_38 U RW default = 'h7ff saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_39 U RW default = 'h849 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_40_41 ((0x50d6 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_40 U RW default = 'h894 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_41 U RW default = 'h8df saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_42_43 ((0x50d7 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_42 U RW default = 'h92b saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_43 U RW default = 'h978 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_44_45 ((0x50d8 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_44 U RW default = 'h9c6 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_45 U RW default = 'ha14 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_46_47 ((0x50d9 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_46 U RW default = 'ha63 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_47 U RW default = 'hab2 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_48_49 ((0x50da << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_48 U RW default = 'hb02 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_49 U RW default = 'hb53 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_50_51 ((0x50db << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_50 U RW default = 'hba5 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_51 U RW default = 'hbf7 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_52_53 ((0x50dc << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_52 U RW default = 'hc4a saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_53 U RW default = 'hc9d saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_54_55 ((0x50dd << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_54 U RW default = 'hcf1 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_55 U RW default = 'hd46 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_56_57 ((0x50de << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_56 U RW default = 'hd9b saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_57 U RW default = 'hdf1 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_58_59 ((0x50df << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_58 U RW default = 'he47 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_59 U RW default = 'he9e saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_60_61 ((0x50e0 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_60 U RW default = 'hef6 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_61 U RW default = 'hf4e saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_62 ((0x50e1 << 2) + 0xff000000)
+ //Bit 31 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_62 U RW default = 'hfa7 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_CURVE_BLK_HIDX_0_1 ((0x50e2 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_hidx_0 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_1 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_HIDX_2_3 ((0x50e3 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_hidx_2 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_3 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_HIDX_4_5 ((0x50e4 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_hidx_4 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_5 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_HIDX_6_7 ((0x50e5 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_hidx_6 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_7 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_HIDX_8_9 ((0x50e6 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_hidx_8 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_9 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_HIDX_10_11 ((0x50e7 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_hidx_10 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_11 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_HIDX_12 ((0x50e8 << 2) + 0xff000000)
+ //Bit 31 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_12 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_VIDX_0_1 ((0x50e9 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_vidx_0 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_vidx_1 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_VIDX_2_3 ((0x50ea << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_vidx_2 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_vidx_3 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_VIDX_4_5 ((0x50eb << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_vidx_4 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_vidx_5 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_VIDX_6_7 ((0x50ec << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_vidx_6 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_vidx_7 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_VIDX_8 ((0x50ed << 2) + 0xff000000)
+ //Bit 31 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_vidx_8 U RW default = 'h0 block boundary x-index
+#define LC_YUV2RGB_MAT_0_1 ((0x50ee << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_yuv2rgb_mat3x3_0 S RW default = 1192 yuv2rgb 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_1 S RW default = 'h0 yuv2rgb 3x3 matrix
+#define LC_YUV2RGB_MAT_2_3 ((0x50ef << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_yuv2rgb_mat3x3_2 S RW default = 1836 yuv2rgb 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_3 S RW default = 1192 yuv2rgb 3x3 matrix
+#define LC_YUV2RGB_MAT_4_5 ((0x50f0 << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_yuv2rgb_mat3x3_4 S RW default = -218 yuv2rgb 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_5 S RW default = -547 yuv2rgb 3x3 matrix
+#define LC_YUV2RGB_MAT_6_7 ((0x50f1 << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_yuv2rgb_mat3x3_6 S RW default = 1192 yuv2rgb 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_7 S RW default = '2166 yuv2rgb 3x3 matrix
+#define LC_YUV2RGB_MAT_8 ((0x50f2 << 2) + 0xff000000)
+ //Bit 31 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_8 S RW default = 'h0 yuv2rgb 3x3 matrix
+#define LC_RGB2YUV_MAT_0_1 ((0x50f3 << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_rgb2yuv_mat3x3_0 S RW default = 187 rgb2yuv 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_1 S RW default = 629 rgb2yuv 3x3 matrix
+#define LC_RGB2YUV_MAT_2_3 ((0x50f4 << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_rgb2yuv_mat3x3_2 S RW default = 63 rgb2yuv 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_3 S RW default = -103 rgb2yuv 3x3 matrix
+#define LC_RGB2YUV_MAT_4_5 ((0x50f5 << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_rgb2yuv_mat3x3_4 S RW default = -346 rgb2yuv 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_5 S RW default = 450 rgb2yuv 3x3 matrix
+#define LC_RGB2YUV_MAT_6_7 ((0x50f6 << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_rgb2yuv_mat3x3_6 S RW default = 450 rgb2yuv 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_7 S RW default = -409 rgb2yuv 3x3 matrix
+#define LC_RGB2YUV_MAT_8 ((0x50f7 << 2) + 0xff000000)
+ //Bit 31 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_8 S RW default = 41 rgb2yuv 3x3 matrix
+#define LC_YUV2RGB_OFST ((0x50f8 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_yuv2rgb_ofset_0 U RW default = 'h40 yuv2rgb pre-offset to yuv,
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_yuv2rgb_ofset_1 U RW default = 'h200 yuv2rgb pre-offset to yuv,
+#define LC_YUV2RGB_CLIP ((0x50f9 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :28 reg_lc_yuv2rgb_rs U RW default = 'h0 matrix normalization right shift extra bits, norm= (1<<(8+rs))
+ //Bit 27 :16 reg_lc_yuv2rgb_clip_0 U RW default = 'h0 yuv2rgb converted RGB clipping range
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_yuv2rgb_clip_1 U RW default = 'h3ff yuv2rgb converted RGB clipping range
+#define LC_RGB2YUV_OFST ((0x50fa << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_rgb2yuv_ofset_0 U RW default = 'h40 rgb2yuv post-offset to yuv,
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_rgb2yuv_ofset_1 U RW default = 'h200 rgb2yuv post-offset to yuv,
+#define LC_RGB2YUV_CLIP ((0x50fb << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :28 reg_lc_rgb2yuv_rs U RW default = 'h0 matrix normalization right shift extra bits, norm= (1<<(10+rs))
+ //Bit 27 :16 reg_lc_rgb2yuv_clip_0 U RW default = 'h0 rgb2yuv converted YUV clipping range
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_rgb2yuv_clip_1 U RW default = 'h3ff rgb2yuv converted YUV clipping range
+#define LC_MAP_RAM_CTRL ((0x50fc << 2) + 0xff000000)
+#define LC_MAP_RAM_ADDR ((0x50fd << 2) + 0xff000000)
+#define LC_MAP_RAM_DATA ((0x50fe << 2) + 0xff000000)
+#define SHARP_FMETER_CTRL ((0x5089 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11:10 reg_fmeter_vwin_mm //u2, vertical window size, 0:1 cloumn, 1:3cloumn, 2or3: 5cloumn .unsigned , default = 0
+//Bit 9 : 8 reg_fmeter_hwin_mm //u2, horizontal window size, 0:1x7, 1:1x9, 2or3: 1x11 .unsigned , default = 0
+//Bit 7 reg_fmeter_d2_mode //u1, selectino filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 6 reg_fmeter_v2_mode //u1, selectino filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 5: 4 reg_fmeter_h2_mode //u2, selection filter H2, 0: [0 0 0 -2 0 0 2 0 0], 1: [-2 0 0 0 2], 2or3: [0-2 0 0 0 0 0 2 0] .unsigned , default = 0
+//Bit 3: 1 reserved
+//Bit 0 reg_freq_meter_en //u1, freq meter enable .unsigned , default = 0
+#define SHARP_FMETER_WIN_HOR ((0x508a << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_fmeter_xwin_ed //u13, window location: hend .unsigned , default = 1920
+//Bit 15:13 reserved
+//Bit 12: 0 reg_fmeter_xwin_st //u13, window location: hstart .unsigned , default = 0
+#define SHARP_FMETER_WIN_VER ((0x508b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_fmeter_ywin_ed //u14, window location: vend .unsigned , default = 1080
+//Bit 15:13 reserved
+//Bit 12: 0 reg_fmeter_ywin_st //u14, window location: vstart .unsigned , default = 0
+#define SHARP_FMETER_CORING ((0x508c << 2) + 0xff000000)
+//Bit 31:24 reg_fmeter_low_bound //u8, low bound for threshold .unsigned , default = 4
+//Bit 23:16 reg_fmeter_coring_d //u8, coring of diff before compare with threhold for diagonal frequency .unsigned , default = 4
+//Bit 15:8 reg_fmeter_coring_v //u8, coring of diff before compare with threhold for vertical frequency .unsigned , default = 4
+//Bit 7: 0 reg_fmeter_coring_h //u8, coring of diff before compare with threhold for horizontal frequency .unsigned , default = 4
+#define SHARP_FMETER_RATIO_H ((0x508d << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:16 reg_fmeter_ratio_h2 //u6, ratio for threshold calc. for horizontal frequency, 16 is normalized as "1" .unsigned , default = 16
+//Bit 15:14 reserved
+//Bit 13: 8 reg_fmeter_ratio_h1 //u6, ratio for threshold calc. for horizontal frequency, 16 is normalized as "1" .unsigned , default = 16
+//Bit 7 : 6 reserved
+//Bit 5 : 0 reg_fmeter_ratio_h0 //u6, ratio for threshold calc. for horizontal frequency, 16 is normalized as "1" .unsigned , default = 16
+#define SHARP_FMETER_RATIO_V ((0x508e << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:16 reg_fmeter_ratio_v2 //u6, ratio for threshold calc. for vertical frequency, 16 is normalized as "1" .unsigned , default = 16
+//Bit 15:14 reserved
+//Bit 13: 8 reg_fmeter_ratio_v1 //u6, ratio for threshold calc. for vertical frequency, 16 is normalized as "1" .unsigned , default = 16
+//Bit 7 : 6 reserved
+//Bit 5 : 0 reg_fmeter_ratio_v0 //u6, ratio for threshold calc. for vertical frequency, 16 is normalized as "1" .unsigned , default = 16
+#define SHARP_FMETER_RATIO_D ((0x508f << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:16 reg_fmeter_ratio_d2 //u6, ratio for threshold calc. for diagonal frequency, 16 is normalized as "1" .unsigned , default = 16
+//Bit 15:14 reserved
+//Bit 13: 8 reg_fmeter_ratio_d1 //u6, ratio for threshold calc. for diagonal frequency, 16 is normalized as "1" .unsigned , default = 16
+//Bit 7 : 6 reserved
+//Bit 5 : 0 reg_fmeter_ratio_d0 //u6, ratio for threshold calc. for diagonal frequency, 16 is normalized as "1" .unsigned , default = 16
+#define SHARP_RO_FMETER_HCNT_TYPE0 ((0x5046 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_hcnt_type0 //u32, count for horizontal frequency
+#define SHARP_RO_FMETER_HCNT_TYPE1 ((0x5047 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_hcnt_type1 //u32, count for horizontal frequency
+#define SHARP_RO_FMETER_HCNT_TYPE2 ((0x5048 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_hcnt_type2 //u32, count for horizontal frequency
+#define SHARP_RO_FMETER_HCNT_TYPE3 ((0x5049 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_hcnt_type3 //u32, count for horizontal frequency
+#define SHARP_RO_FMETER_VCNT_TYPE0 ((0x504a << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_vcnt_type0 //u32, count for vertical frequency
+#define SHARP_RO_FMETER_VCNT_TYPE1 ((0x504b << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_vcnt_type1 //u32, count for vertical frequency
+#define SHARP_RO_FMETER_VCNT_TYPE2 ((0x504c << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_vcnt_type2 //u32, count for vertical frequency
+#define SHARP_RO_FMETER_VCNT_TYPE3 ((0x504d << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_vcnt_type3 //u32, count for vertical frequency
+#define SHARP_RO_FMETER_PDCNT_TYPE0 ((0x504e << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_pdcnt_type0 //u32, count for positive diagonal frequency
+#define SHARP_RO_FMETER_PDCNT_TYPE1 ((0x504f << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_pdcnt_type1 //u32, count for positive diagonal frequency
+#define SHARP_RO_FMETER_PDCNT_TYPE2 ((0x5050 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_pdcnt_type2 //u32, count for positive diagonal frequency
+#define SHARP_RO_FMETER_PDCNT_TYPE3 ((0x5051 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_pdcnt_type3 //u32, count for positive diagonal frequency
+#define SHARP_RO_FMETER_NDCNT_TYPE0 ((0x5052 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_ndcnt_type0 //u32, count for negitive diagonal frequency
+#define SHARP_RO_FMETER_NDCNT_TYPE1 ((0x5053 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_ndcnt_type1 //u32, count for negitive diagonal frequency
+#define SHARP_RO_FMETER_NDCNT_TYPE2 ((0x5054 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_ndcnt_type2 //u32, count for negitive diagonal frequency
+#define SHARP_RO_FMETER_NDCNT_TYPE3 ((0x5055 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_ndcnt_type3 //u32, count for negitive diagonal frequency
+//
+// Closing file: sharp_regs.h
+//
+
+#define SRSHARP0_SHARP_HVSIZE (SRSHARP0_OFFSET + SHARP_HVSIZE ) //0x00 //
+#define SRSHARP0_SHARP_HVBLANK_NUM (SRSHARP0_OFFSET + SHARP_HVBLANK_NUM ) //0x01 //
+#define SRSHARP0_NR_GAUSSIAN_MODE (SRSHARP0_OFFSET + NR_GAUSSIAN_MODE ) //0x02 //
+//`define SRSHARP0_PK_HVCON_LPF_MODE (`SRSHARP0_OFFSET + `PK_HVCON_LPF_MODE ) //8'h03 //
+//`define SRSHARP0_PK_CON_BLEND_GAIN (`SRSHARP0_OFFSET + `PK_CON_BLEND_GAIN ) //8'h04 //
+#define SRSHARP0_PK_CON_2CIRHPGAIN_TH_RATE (SRSHARP0_OFFSET + PK_CON_2CIRHPGAIN_TH_RATE ) //0x05 //
+#define SRSHARP0_PK_CON_2CIRHPGAIN_LIMIT (SRSHARP0_OFFSET + PK_CON_2CIRHPGAIN_LIMIT ) //0x06 //
+#define SRSHARP0_PK_CON_2CIRBPGAIN_TH_RATE (SRSHARP0_OFFSET + PK_CON_2CIRBPGAIN_TH_RATE ) //0x07 //
+#define SRSHARP0_PK_CON_2CIRBPGAIN_LIMIT (SRSHARP0_OFFSET + PK_CON_2CIRBPGAIN_LIMIT ) //0x08 //
+#define SRSHARP0_PK_CON_2DRTHPGAIN_TH_RATE (SRSHARP0_OFFSET + PK_CON_2DRTHPGAIN_TH_RATE ) //0x09 //
+#define SRSHARP0_PK_CON_2DRTHPGAIN_LIMIT (SRSHARP0_OFFSET + PK_CON_2DRTHPGAIN_LIMIT ) //0x0a //
+#define SRSHARP0_PK_CON_2DRTBPGAIN_TH_RATE (SRSHARP0_OFFSET + PK_CON_2DRTBPGAIN_TH_RATE ) //0x0b //
+#define SRSHARP0_PK_CON_2DRTBPGAIN_LIMIT (SRSHARP0_OFFSET + PK_CON_2DRTBPGAIN_LIMIT ) //0x0c //
+#define SRSHARP0_PK_CIRFB_LPF_MODE (SRSHARP0_OFFSET + PK_CIRFB_LPF_MODE ) //0x0d //
+#define SRSHARP0_PK_DRTFB_LPF_MODE (SRSHARP0_OFFSET + PK_DRTFB_LPF_MODE ) //0x0e //
+#define SRSHARP0_PK_CIRFB_HP_CORING (SRSHARP0_OFFSET + PK_CIRFB_HP_CORING ) //0x0f //
+#define SRSHARP0_PK_CIRFB_BP_CORING (SRSHARP0_OFFSET + PK_CIRFB_BP_CORING ) //0x10 //
+#define SRSHARP0_PK_DRTFB_HP_CORING (SRSHARP0_OFFSET + PK_DRTFB_HP_CORING ) //0x11 //
+#define SRSHARP0_PK_DRTFB_BP_CORING (SRSHARP0_OFFSET + PK_DRTFB_BP_CORING ) //0x12 //
+#define SRSHARP0_PK_CIRFB_BLEND_GAIN (SRSHARP0_OFFSET + PK_CIRFB_BLEND_GAIN ) //0x13 //
+#define SRSHARP0_NR_ALPY_SSD_GAIN_OFST (SRSHARP0_OFFSET + NR_ALPY_SSD_GAIN_OFST ) //0x14 //
+#define SRSHARP0_NR_ALP0Y_ERR2CURV_TH_RATE (SRSHARP0_OFFSET + NR_ALP0Y_ERR2CURV_TH_RATE ) //0x15 //
+#define SRSHARP0_NR_ALP0Y_ERR2CURV_LIMIT (SRSHARP0_OFFSET + NR_ALP0Y_ERR2CURV_LIMIT ) //0x16 //
+#define SRSHARP0_NR_ALP0C_ERR2CURV_TH_RATE (SRSHARP0_OFFSET + NR_ALP0C_ERR2CURV_TH_RATE ) //0x17 //
+#define SRSHARP0_NR_ALP0C_ERR2CURV_LIMIT (SRSHARP0_OFFSET + NR_ALP0C_ERR2CURV_LIMIT ) //0x18 //
+#define SRSHARP0_NR_ALP0_MIN_MAX (SRSHARP0_OFFSET + NR_ALP0_MIN_MAX ) //0x19 //
+#define SRSHARP0_NR_ALP1_MIERR_CORING (SRSHARP0_OFFSET + NR_ALP1_MIERR_CORING ) //0x1a //
+#define SRSHARP0_NR_ALP1_ERR2CURV_TH_RATE (SRSHARP0_OFFSET + NR_ALP1_ERR2CURV_TH_RATE ) //0x1b //
+#define SRSHARP0_NR_ALP1_ERR2CURV_LIMIT (SRSHARP0_OFFSET + NR_ALP1_ERR2CURV_LIMIT ) //0x1c //
+#define SRSHARP0_NR_ALP1_MIN_MAX (SRSHARP0_OFFSET + NR_ALP1_MIN_MAX ) //0x1d //
+#define SRSHARP0_PK_ALP2_MIERR_CORING (SRSHARP0_OFFSET + PK_ALP2_MIERR_CORING ) //0x1e //
+#define SRSHARP0_PK_ALP2_ERR2CURV_TH_RATE (SRSHARP0_OFFSET + PK_ALP2_ERR2CURV_TH_RATE ) //0x1f //
+#define SRSHARP0_PK_ALP2_ERR2CURV_LIMIT (SRSHARP0_OFFSET + PK_ALP2_ERR2CURV_LIMIT ) //0x20 //
+#define SRSHARP0_PK_ALP2_MIN_MAX (SRSHARP0_OFFSET + PK_ALP2_MIN_MAX ) //0x21 //
+#define SRSHARP0_PK_FINALGAIN_HP_BP (SRSHARP0_OFFSET + PK_FINALGAIN_HP_BP ) //0x22 //
+#define SRSHARP0_PK_OS_HORZ_CORE_GAIN (SRSHARP0_OFFSET + PK_OS_HORZ_CORE_GAIN ) //0x23 //
+#define SRSHARP0_PK_OS_VERT_CORE_GAIN (SRSHARP0_OFFSET + PK_OS_VERT_CORE_GAIN ) //0x24 //
+#define SRSHARP0_PK_OS_ADPT_MISC (SRSHARP0_OFFSET + PK_OS_ADPT_MISC ) //0x25 //
+#define SRSHARP0_PK_OS_STATIC (SRSHARP0_OFFSET + PK_OS_STATIC ) //0x26 //
+#define SRSHARP0_PK_NR_ENABLE (SRSHARP0_OFFSET + PK_NR_ENABLE ) //0x27 //
+#define SRSHARP0_PK_DRT_SAD_MISC (SRSHARP0_OFFSET + PK_DRT_SAD_MISC ) //0x28 //
+#define SRSHARP0_NR_TI_DNLP_BLEND (SRSHARP0_OFFSET + NR_TI_DNLP_BLEND ) //0x29 //
+#define SRSHARP0_LTI_DIR_CORE_ALPHA (SRSHARP0_OFFSET + LTI_DIR_CORE_ALPHA ) //0x2a //
+#define SRSHARP0_CTI_DIR_ALPHA (SRSHARP0_OFFSET + CTI_DIR_ALPHA ) //0x2b //
+#define SRSHARP0_LTI_CTI_DF_GAIN (SRSHARP0_OFFSET + LTI_CTI_DF_GAIN ) //0x2c //
+#define SRSHARP0_LTI_CTI_DIR_AC_DBG (SRSHARP0_OFFSET + LTI_CTI_DIR_AC_DBG ) //0x2d //
+#define SRSHARP0_HCTI_FLT_CLP_DC (SRSHARP0_OFFSET + HCTI_FLT_CLP_DC ) //0x2e //
+#define SRSHARP0_HCTI_BST_GAIN (SRSHARP0_OFFSET + HCTI_BST_GAIN ) //0x2f //
+#define SRSHARP0_HCTI_BST_CORE (SRSHARP0_OFFSET + HCTI_BST_CORE ) //0x30 //
+#define SRSHARP0_HCTI_CON_2_GAIN_0 (SRSHARP0_OFFSET + HCTI_CON_2_GAIN_0 ) //0x31 //
+#define SRSHARP0_HCTI_CON_2_GAIN_1 (SRSHARP0_OFFSET + HCTI_CON_2_GAIN_1 ) //0x32 //
+#define SRSHARP0_HCTI_OS_MARGIN (SRSHARP0_OFFSET + HCTI_OS_MARGIN ) //0x33 //
+#define SRSHARP0_HLTI_FLT_CLP_DC (SRSHARP0_OFFSET + HLTI_FLT_CLP_DC ) //0x34 //
+#define SRSHARP0_HLTI_BST_GAIN (SRSHARP0_OFFSET + HLTI_BST_GAIN ) //0x35 //
+#define SRSHARP0_HLTI_BST_CORE (SRSHARP0_OFFSET + HLTI_BST_CORE ) //0x36 //
+#define SRSHARP0_HLTI_CON_2_GAIN_0 (SRSHARP0_OFFSET + HLTI_CON_2_GAIN_0 ) //0x37 //
+#define SRSHARP0_HLTI_CON_2_GAIN_1 (SRSHARP0_OFFSET + HLTI_CON_2_GAIN_1 ) //0x38 //
+#define SRSHARP0_HLTI_OS_MARGIN (SRSHARP0_OFFSET + HLTI_OS_MARGIN ) //0x39 //
+#define SRSHARP0_VLTI_FLT_CON_CLP (SRSHARP0_OFFSET + VLTI_FLT_CON_CLP ) //0x3a //
+#define SRSHARP0_VLTI_BST_GAIN (SRSHARP0_OFFSET + VLTI_BST_GAIN ) //0x3b //
+#define SRSHARP0_VLTI_BST_CORE (SRSHARP0_OFFSET + VLTI_BST_CORE ) //0x3c //
+#define SRSHARP0_VLTI_CON_2_GAIN_0 (SRSHARP0_OFFSET + VLTI_CON_2_GAIN_0 ) //0x3d //
+#define SRSHARP0_VLTI_CON_2_GAIN_1 (SRSHARP0_OFFSET + VLTI_CON_2_GAIN_1 ) //0x3e //
+#define SRSHARP0_VCTI_FLT_CON_CLP (SRSHARP0_OFFSET + VCTI_FLT_CON_CLP ) //0x3f //
+#define SRSHARP0_VCTI_BST_GAIN (SRSHARP0_OFFSET + VCTI_BST_GAIN ) //0x40 //
+#define SRSHARP0_VCTI_BST_CORE (SRSHARP0_OFFSET + VCTI_BST_CORE ) //0x41 //
+#define SRSHARP0_VCTI_CON_2_GAIN_0 (SRSHARP0_OFFSET + VCTI_CON_2_GAIN_0 ) //0x42 //
+#define SRSHARP0_VCTI_CON_2_GAIN_1 (SRSHARP0_OFFSET + VCTI_CON_2_GAIN_1 ) //0x43 //
+#define SRSHARP0_SHARP_3DLIMIT (SRSHARP0_OFFSET + SHARP_3DLIMIT ) //0x44 //
+#define SRSHARP0_DNLP_EN (SRSHARP0_OFFSET + DNLP_EN ) //0x45 //
+//`define SRSHARP0_DNLP_00 (`SRSHARP0_OFFSET + `DNLP_00 ) //8'h46 //
+//`define SRSHARP0_DNLP_01 (`SRSHARP0_OFFSET + `DNLP_01 ) //8'h47 //
+//`define SRSHARP0_DNLP_02 (`SRSHARP0_OFFSET + `DNLP_02 ) //8'h48 //
+//`define SRSHARP0_DNLP_03 (`SRSHARP0_OFFSET + `DNLP_03 ) //8'h49 //
+//`define SRSHARP0_DNLP_04 (`SRSHARP0_OFFSET + `DNLP_04 ) //8'h4a //
+//`define SRSHARP0_DNLP_05 (`SRSHARP0_OFFSET + `DNLP_05 ) //8'h4b //
+//`define SRSHARP0_DNLP_06 (`SRSHARP0_OFFSET + `DNLP_06 ) //8'h4c //
+//`define SRSHARP0_DNLP_07 (`SRSHARP0_OFFSET + `DNLP_07 ) //8'h4d //
+//`define SRSHARP0_DNLP_08 (`SRSHARP0_OFFSET + `DNLP_08 ) //8'h4e //
+//`define SRSHARP0_DNLP_09 (`SRSHARP0_OFFSET + `DNLP_09 ) //8'h4f //
+//`define SRSHARP0_DNLP_10 (`SRSHARP0_OFFSET + `DNLP_10 ) //8'h50 //
+//`define SRSHARP0_DNLP_11 (`SRSHARP0_OFFSET + `DNLP_11 ) //8'h51 //
+//`define SRSHARP0_DNLP_12 (`SRSHARP0_OFFSET + `DNLP_12 ) //8'h52 //
+//`define SRSHARP0_DNLP_13 (`SRSHARP0_OFFSET + `DNLP_13 ) //8'h53 //
+//`define SRSHARP0_DNLP_14 (`SRSHARP0_OFFSET + `DNLP_14 ) //8'h54 //
+//`define SRSHARP0_DNLP_15 (`SRSHARP0_OFFSET + `DNLP_15 ) //8'h55 //
+#define SRSHARP0_DEMO_CRTL (SRSHARP0_OFFSET + DEMO_CRTL ) //0x56 //
+#define SRSHARP0_SHARP_SR2_CTRL (SRSHARP0_OFFSET + SHARP_SR2_CTRL ) //0x57 //
+#define SRSHARP0_SHARP_SR2_YBIC_HCOEF0 (SRSHARP0_OFFSET + SHARP_SR2_YBIC_HCOEF0 ) //0x58
+#define SRSHARP0_SHARP_SR2_YBIC_HCOEF1 (SRSHARP0_OFFSET + SHARP_SR2_YBIC_HCOEF1 ) //0x59 //
+#define SRSHARP0_SHARP_SR2_CBIC_HCOEF0 (SRSHARP0_OFFSET + SHARP_SR2_CBIC_HCOEF0 ) //0x5a //
+#define SRSHARP0_SHARP_SR2_CBIC_HCOEF1 (SRSHARP0_OFFSET + SHARP_SR2_CBIC_HCOEF1 ) //0x5b //
+#define SRSHARP0_SHARP_SR2_YBIC_VCOEF0 (SRSHARP0_OFFSET + SHARP_SR2_YBIC_VCOEF0 ) //0x5c //
+#define SRSHARP0_SHARP_SR2_YBIC_VCOEF1 (SRSHARP0_OFFSET + SHARP_SR2_YBIC_VCOEF1 ) //0x5d //
+#define SRSHARP0_SHARP_SR2_CBIC_VCOEF0 (SRSHARP0_OFFSET + SHARP_SR2_CBIC_VCOEF0 ) //0x5e //
+#define SRSHARP0_SHARP_SR2_CBIC_VCOEF1 (SRSHARP0_OFFSET + SHARP_SR2_CBIC_VCOEF1 ) //0x5f //
+#define SRSHARP0_SHARP_SR2_MISC (SRSHARP0_OFFSET + SHARP_SR2_MISC ) //0x60 //
+#define SRSHARP0_SR3_SAD_CTRL (SRSHARP0_OFFSET + SHARP_SR3_SAD_CTRL ) // 0x61 //
+#define SRSHARP0_SR3_PK_CTRL0 (SRSHARP0_OFFSET + SHARP_SR3_PK_CTRL0 ) // 0x62
+#define SRSHARP0_SR3_PK_CTRL1 (SRSHARP0_OFFSET + SHARP_SR3_PK_CTRL1 ) // 0x63
+#define SRSHARP0_DEJ_CTRL (SRSHARP0_OFFSET + SHARP_DEJ_CTRL ) // 0x64
+#define SRSHARP0_DEJ_ALPHA (SRSHARP0_OFFSET + SHARP_DEJ_ALPHA ) // 0x65
+#define SRSHARP0_SR3_DRTLPF_EN (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_EN ) // 0x66
+#define SRSHARP0_SR3_DRTLPF_ALPHA_0 (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_ALPHA_0 ) // 0x67
+#define SRSHARP0_SR3_DRTLPF_ALPHA_1 (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_ALPHA_1 ) // 0x68
+#define SRSHARP0_SR3_DRTLPF_ALPHA_2 (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_ALPHA_2 ) // 0x69
+#define SRSHARP0_SR3_DRTLPF_ALPHA_OFST (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_ALPHA_OFST ) // 0x6a
+#define SRSHARP0_SR3_DERING_CTRL (SRSHARP0_OFFSET + SHARP_SR3_DERING_CTRL ) // 0x6b
+#define SRSHARP0_SR3_DERING_LUMA2PKGAIN_0TO3 (SRSHARP0_OFFSET + SHARP_SR3_DERING_LUMA2PKGAIN_0TO3 ) // 0x6c
+#define SRSHARP0_SR3_DERING_LUMA2PKGAIN_4TO6 (SRSHARP0_OFFSET + SHARP_SR3_DERING_LUMA2PKGAIN_4TO6 ) // 0x6d
+#define SRSHARP0_SR3_DERING_LUMA2PKOS_0TO3 (SRSHARP0_OFFSET + SHARP_SR3_DERING_LUMA2PKOS_0TO3 ) // 0x6e
+#define SRSHARP0_SR3_DERING_LUMA2PKOS_4TO6 (SRSHARP0_OFFSET + SHARP_SR3_DERING_LUMA2PKOS_4TO6 ) // 0x6f
+#define SRSHARP0_SR3_DERING_GAINVS_MADSAD (SRSHARP0_OFFSET + SHARP_SR3_DERING_GAINVS_MADSAD ) // 0x70
+#define SRSHARP0_SR3_DERING_GAINVS_VR2MAX (SRSHARP0_OFFSET + SHARP_SR3_DERING_GAINVS_VR2MAX ) // 0x71
+#define SRSHARP0_SR3_DERING_PARAM0 (SRSHARP0_OFFSET + SHARP_SR3_DERING_PARAM0 ) // 0x72
+#define SRSHARP0_SR3_DRTLPF_THETA (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_THETA ) // 0x73
+#define SRSHARP0_SATPRT_CTRL (SRSHARP0_OFFSET + SHARP_SATPRT_CTRL ) // 0x74
+#define SRSHARP0_SATPRT_DIVM (SRSHARP0_OFFSET + SHARP_SATPRT_DIVM ) // 0x75
+#define SRSHARP0_DB_FLT_CTRL (SRSHARP0_OFFSET + SHARP_DB_FLT_CTRL ) // 0x77
+//`define SRSHARP0_DB_FLT_YC_THRD (`SRSHARP0_OFFSET + `SHARP_DB_FLT_YC_THRD ) // 8'h78
+#define SRSHARP0_DB_FLT_CTRL1 (SRSHARP0_OFFSET + SHARP_DB_FLT_CTRL1 ) // 0xb8
+#define SRSHARP0_DB_FLT_LUMA_THRD (SRSHARP0_OFFSET + SHARP_DB_FLT_LUMA_THRD ) // 0xb9
+#define SRSHARP0_DB_FLT_CHRM_THRD (SRSHARP0_OFFSET + SHARP_DB_FLT_CHRM_THRD ) // 0xba
+#define SRSHARP0_DB_FLT_RANDLUT (SRSHARP0_OFFSET + SHARP_DB_FLT_RANDLUT ) // 0x79
+#define SRSHARP0_DB_FLT_PXI_THRD (SRSHARP0_OFFSET + SHARP_DB_FLT_PXI_THRD ) // 0x7a
+#define SRSHARP0_DB_FLT_SEED_Y (SRSHARP0_OFFSET + SHARP_DB_FLT_SEED_Y ) // 0x7b
+#define SRSHARP0_DB_FLT_SEED_U (SRSHARP0_OFFSET + SHARP_DB_FLT_SEED_U ) // 0x7c
+#define SRSHARP0_DB_FLT_SEED_V (SRSHARP0_OFFSET + SHARP_DB_FLT_SEED_V ) // 0x7d
+#define SRSHARP0_PKGAIN_VSLUMA_LUT_L (SRSHARP0_OFFSET + SHARP_PKGAIN_VSLUMA_LUT_L ) // 0x7e
+#define SRSHARP0_PKGAIN_VSLUMA_LUT_H (SRSHARP0_OFFSET + SHARP_PKGAIN_VSLUMA_LUT_H ) // 0x7f
+#define SRSHARP0_PKOSHT_VSLUMA_LUT_L (SRSHARP0_OFFSET + SHARP_PKOSHT_VSLUMA_LUT_L ) // 0x80
+#define SRSHARP0_PKOSHT_VSLUMA_LUT_H (SRSHARP0_OFFSET + SHARP_PKOSHT_VSLUMA_LUT_H ) // 0x81
+#define SRSHARP0_SATPRT_LMT_RGB1 (SRSHARP0_OFFSET + SHARP_SATPRT_LMT_RGB1 ) // 0x82
+#define SRSHARP0_SATPRT_LMT_RGB2 (SRSHARP0_OFFSET + SHARP_SATPRT_LMT_RGB2 ) // 0x83
+#define SRSHARP0_SHARP_GATE_CLK_CTRL_0 (SRSHARP0_OFFSET + SHARP_GATE_CLK_CTRL_0 ) // 0x84
+#define SRSHARP0_SHARP_GATE_CLK_CTRL_1 (SRSHARP0_OFFSET + SHARP_GATE_CLK_CTRL_1 ) // 0x85
+#define SRSHARP0_SHARP_GATE_CLK_CTRL_2 (SRSHARP0_OFFSET + SHARP_GATE_CLK_CTRL_2 ) // 0x86
+#define SRSHARP0_SHARP_GATE_CLK_CTRL_3 (SRSHARP0_OFFSET + SHARP_GATE_CLK_CTRL_3 ) // 0x87
+#define SRSHARP0_SHARP_DPS_CTRL (SRSHARP0_OFFSET + SHARP_DPS_CTRL ) // 0x88
+#define SRSHARP0_DNLP_00 (SRSHARP0_OFFSET + DNLP_00 ) // 0x90 //
+#define SRSHARP0_DNLP_01 (SRSHARP0_OFFSET + DNLP_01 ) // 0x91 //
+#define SRSHARP0_DNLP_02 (SRSHARP0_OFFSET + DNLP_02 ) // 0x92 //
+#define SRSHARP0_DNLP_03 (SRSHARP0_OFFSET + DNLP_03 ) // 0x93 //
+#define SRSHARP0_DNLP_04 (SRSHARP0_OFFSET + DNLP_04 ) // 0x94 //
+#define SRSHARP0_DNLP_05 (SRSHARP0_OFFSET + DNLP_05 ) // 0x95 //
+#define SRSHARP0_DNLP_06 (SRSHARP0_OFFSET + DNLP_06 ) // 0x96 //
+#define SRSHARP0_DNLP_07 (SRSHARP0_OFFSET + DNLP_07 ) // 0x97 //
+#define SRSHARP0_DNLP_08 (SRSHARP0_OFFSET + DNLP_08 ) // 0x98 //
+#define SRSHARP0_DNLP_09 (SRSHARP0_OFFSET + DNLP_09 ) // 0x99 //
+#define SRSHARP0_DNLP_10 (SRSHARP0_OFFSET + DNLP_10 ) // 0x9a //
+#define SRSHARP0_DNLP_11 (SRSHARP0_OFFSET + DNLP_11 ) // 0x9b //
+#define SRSHARP0_DNLP_12 (SRSHARP0_OFFSET + DNLP_12 ) // 0x9c //
+#define SRSHARP0_DNLP_13 (SRSHARP0_OFFSET + DNLP_13 ) // 0x9d //
+#define SRSHARP0_DNLP_14 (SRSHARP0_OFFSET + DNLP_14 ) // 0x9e //
+#define SRSHARP0_DNLP_15 (SRSHARP0_OFFSET + DNLP_15 ) // 0x9f //
+#define SRSHARP0_DNLP_16 (SRSHARP0_OFFSET + DNLP_16 ) // 0xa0 //
+#define SRSHARP0_DNLP_17 (SRSHARP0_OFFSET + DNLP_17 ) // 0xa1 //
+#define SRSHARP0_DNLP_18 (SRSHARP0_OFFSET + DNLP_18 ) // 0xa2 //
+#define SRSHARP0_DNLP_19 (SRSHARP0_OFFSET + DNLP_19 ) // 0xa3 //
+#define SRSHARP0_DNLP_20 (SRSHARP0_OFFSET + DNLP_20 ) // 0xa4 //
+#define SRSHARP0_DNLP_21 (SRSHARP0_OFFSET + DNLP_21 ) // 0xa5 //
+#define SRSHARP0_DNLP_22 (SRSHARP0_OFFSET + DNLP_22 ) // 0xa6 //
+#define SRSHARP0_DNLP_23 (SRSHARP0_OFFSET + DNLP_23 ) // 0xa7 //
+#define SRSHARP0_DNLP_24 (SRSHARP0_OFFSET + DNLP_24 ) // 0xa8 //
+#define SRSHARP0_DNLP_25 (SRSHARP0_OFFSET + DNLP_25 ) // 0xa9 //
+#define SRSHARP0_DNLP_26 (SRSHARP0_OFFSET + DNLP_26 ) // 0xaa //
+#define SRSHARP0_DNLP_27 (SRSHARP0_OFFSET + DNLP_27 ) // 0xab //
+#define SRSHARP0_DNLP_28 (SRSHARP0_OFFSET + DNLP_28 ) // 0xac //
+#define SRSHARP0_DNLP_29 (SRSHARP0_OFFSET + DNLP_29 ) // 0xad //
+#define SRSHARP0_DNLP_30 (SRSHARP0_OFFSET + DNLP_30 ) // 0xae //
+#define SRSHARP0_DNLP_31 (SRSHARP0_OFFSET + DNLP_31 ) // 0xaf //
+#define SRSHARP0_SHARP_SYNC_CTRL (SRSHARP0_OFFSET + SHARP_SYNC_CTRL ) // 0xb0 //
+#define SRSHARP0_LC_INPUT_MUX (SRSHARP0_OFFSET + LC_INPUT_MUX ) // 0xb1 //
+#define SRSHARP0_NR_GAU_YH_COEF02 (SRSHARP0_OFFSET + NR_GAU_YH_COEF02 ) // 0xb2 //
+#define SRSHARP0_NR_GAU_YH_COEF34 (SRSHARP0_OFFSET + NR_GAU_YH_COEF34 ) // 0xb3 //
+#define SRSHARP0_NR_GAU_YV_COEF1 (SRSHARP0_OFFSET + NR_GAU_YV_COEF1 ) // 0xb4 //
+#define SRSHARP0_NR_GAU_CH_COEF02 (SRSHARP0_OFFSET + NR_GAU_CH_COEF02 ) // 0xb5 //
+#define SRSHARP0_NR_GAU_CH_COEF34 (SRSHARP0_OFFSET + NR_GAU_CH_COEF34 ) // 0xb6 //
+#define SRSHARP0_NR_GAU_CV_COEF1 (SRSHARP0_OFFSET + NR_GAU_CV_COEF1 ) // 0xb7 //
+#define SRSHARP0_LC_TOP_CTRL (SRSHARP0_OFFSET + LC_TOP_CTRL ) // 0xc0 //
+#define SRSHARP0_LC_HV_NUM (SRSHARP0_OFFSET + LC_HV_NUM ) // 0xc1
+#define SRSHARP0_LC_SAT_LUT_0_1 (SRSHARP0_OFFSET + LC_SAT_LUT_0_1 ) // 0xc2
+#define SRSHARP0_LC_SAT_LUT_2_3 (SRSHARP0_OFFSET + LC_SAT_LUT_2_3 ) // 0xc3
+#define SRSHARP0_LC_SAT_LUT_4_5 (SRSHARP0_OFFSET + LC_SAT_LUT_4_5 ) // 0xc4
+#define SRSHARP0_LC_SAT_LUT_6_7 (SRSHARP0_OFFSET + LC_SAT_LUT_6_7 ) // 0xc5
+#define SRSHARP0_LC_SAT_LUT_8_9 (SRSHARP0_OFFSET + LC_SAT_LUT_8_9 ) // 0xc6
+#define SRSHARP0_LC_SAT_LUT_10_11 (SRSHARP0_OFFSET + LC_SAT_LUT_10_11 ) // 0xc7
+#define SRSHARP0_LC_SAT_LUT_12_13 (SRSHARP0_OFFSET + LC_SAT_LUT_12_13 ) // 0xc8
+#define SRSHARP0_LC_SAT_LUT_14_15 (SRSHARP0_OFFSET + LC_SAT_LUT_14_15 ) // 0xc9
+#define SRSHARP0_LC_SAT_LUT_16_17 (SRSHARP0_OFFSET + LC_SAT_LUT_16_17 ) // 0xca
+#define SRSHARP0_LC_SAT_LUT_18_19 (SRSHARP0_OFFSET + LC_SAT_LUT_18_19 ) // 0xcb
+#define SRSHARP0_LC_SAT_LUT_20_21 (SRSHARP0_OFFSET + LC_SAT_LUT_20_21 ) // 0xcc
+#define SRSHARP0_LC_SAT_LUT_22_23 (SRSHARP0_OFFSET + LC_SAT_LUT_22_23 ) // 0xcd
+#define SRSHARP0_LC_SAT_LUT_24_25 (SRSHARP0_OFFSET + LC_SAT_LUT_24_25 ) // 0xce
+#define SRSHARP0_LC_SAT_LUT_26_27 (SRSHARP0_OFFSET + LC_SAT_LUT_26_27 ) // 0xcf
+#define SRSHARP0_LC_SAT_LUT_28_29 (SRSHARP0_OFFSET + LC_SAT_LUT_28_29 ) // 0xd0
+#define SRSHARP0_LC_SAT_LUT_30_31 (SRSHARP0_OFFSET + LC_SAT_LUT_30_31 ) // 0xd1
+#define SRSHARP0_LC_SAT_LUT_32_33 (SRSHARP0_OFFSET + LC_SAT_LUT_32_33 ) // 0xd2
+#define SRSHARP0_LC_SAT_LUT_34_35 (SRSHARP0_OFFSET + LC_SAT_LUT_34_35 ) // 0xd3
+#define SRSHARP0_LC_SAT_LUT_36_37 (SRSHARP0_OFFSET + LC_SAT_LUT_36_37 ) // 0xd4
+#define SRSHARP0_LC_SAT_LUT_38_39 (SRSHARP0_OFFSET + LC_SAT_LUT_38_39 ) // 0xd5
+#define SRSHARP0_LC_SAT_LUT_40_41 (SRSHARP0_OFFSET + LC_SAT_LUT_40_41 ) // 0xd6
+#define SRSHARP0_LC_SAT_LUT_42_43 (SRSHARP0_OFFSET + LC_SAT_LUT_42_43 ) // 0xd7
+#define SRSHARP0_LC_SAT_LUT_44_45 (SRSHARP0_OFFSET + LC_SAT_LUT_44_45 ) // 0xd8
+#define SRSHARP0_LC_SAT_LUT_46_47 (SRSHARP0_OFFSET + LC_SAT_LUT_46_47 ) // 0xd9
+#define SRSHARP0_LC_SAT_LUT_48_49 (SRSHARP0_OFFSET + LC_SAT_LUT_48_49 ) // 0xda
+#define SRSHARP0_LC_SAT_LUT_50_51 (SRSHARP0_OFFSET + LC_SAT_LUT_50_51 ) // 0xdb
+#define SRSHARP0_LC_SAT_LUT_52_53 (SRSHARP0_OFFSET + LC_SAT_LUT_52_53 ) // 0xdc
+#define SRSHARP0_LC_SAT_LUT_54_55 (SRSHARP0_OFFSET + LC_SAT_LUT_54_55 ) // 0xdd
+#define SRSHARP0_LC_SAT_LUT_56_57 (SRSHARP0_OFFSET + LC_SAT_LUT_56_57 ) // 0xde
+#define SRSHARP0_LC_SAT_LUT_58_59 (SRSHARP0_OFFSET + LC_SAT_LUT_58_59 ) // 0xdf
+#define SRSHARP0_LC_SAT_LUT_60_61 (SRSHARP0_OFFSET + LC_SAT_LUT_60_61 ) // 0xe0
+#define SRSHARP0_LC_SAT_LUT_62 (SRSHARP0_OFFSET + LC_SAT_LUT_62 ) // 0xe1
+#define SRSHARP0_LC_CURVE_BLK_HIDX_0_1 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_0_1 ) // 0xe2
+#define SRSHARP0_LC_CURVE_BLK_HIDX_2_3 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_2_3 ) // 0xe3
+#define SRSHARP0_LC_CURVE_BLK_HIDX_4_5 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_4_5 ) // 0xe4
+#define SRSHARP0_LC_CURVE_BLK_HIDX_6_7 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_6_7 ) // 0xe5
+#define SRSHARP0_LC_CURVE_BLK_HIDX_8_9 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_8_9 ) // 0xe6
+#define SRSHARP0_LC_CURVE_BLK_HIDX_10_11 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_10_11 ) // 0xe7
+#define SRSHARP0_LC_CURVE_BLK_HIDX_12 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_12 ) // 0xe8
+#define SRSHARP0_LC_CURVE_BLK_VIDX_0_1 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_0_1 ) // 0xe9
+#define SRSHARP0_LC_CURVE_BLK_VIDX_2_3 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_2_3 ) // 0xea
+#define SRSHARP0_LC_CURVE_BLK_VIDX_4_5 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_4_5 ) // 0xeb
+#define SRSHARP0_LC_CURVE_BLK_VIDX_6_7 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_6_7 ) // 0xec
+#define SRSHARP0_LC_CURVE_BLK_VIDX_8 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_8 ) // 0xed
+#define SRSHARP0_LC_YUV2RGB_MAT_0_1 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_0_1 ) // 0xee
+#define SRSHARP0_LC_YUV2RGB_MAT_2_3 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_2_3 ) // 0xef
+#define SRSHARP0_LC_YUV2RGB_MAT_4_5 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_4_5 ) // 0xf0
+#define SRSHARP0_LC_YUV2RGB_MAT_6_7 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_6_7 ) // 0xf1
+#define SRSHARP0_LC_YUV2RGB_MAT_8 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_8 ) // 0xf2
+#define SRSHARP0_LC_RGB2YUV_MAT_0_1 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_0_1 ) // 0xf3
+#define SRSHARP0_LC_RGB2YUV_MAT_2_3 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_2_3 ) // 0xf4
+#define SRSHARP0_LC_RGB2YUV_MAT_4_5 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_4_5 ) // 0xf5
+#define SRSHARP0_LC_RGB2YUV_MAT_6_7 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_6_7 ) // 0xf6
+#define SRSHARP0_LC_RGB2YUV_MAT_8 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_8 ) // 0xf7
+#define SRSHARP0_LC_YUV2RGB_OFST (SRSHARP0_OFFSET + LC_YUV2RGB_OFST ) // 0xf8
+#define SRSHARP0_LC_YUV2RGB_CLIP (SRSHARP0_OFFSET + LC_YUV2RGB_CLIP ) // 0xf9
+#define SRSHARP0_LC_RGB2YUV_OFST (SRSHARP0_OFFSET + LC_RGB2YUV_OFST ) // 0xfa
+#define SRSHARP0_LC_RGB2YUV_CLIP (SRSHARP0_OFFSET + LC_RGB2YUV_CLIP ) // 0xfb
+#define SRSHARP0_LC_MAP_RAM_CTRL (SRSHARP0_OFFSET + LC_MAP_RAM_CTRL ) // 0xfc
+#define SRSHARP0_LC_MAP_RAM_ADDR (SRSHARP0_OFFSET + LC_MAP_RAM_ADDR ) // 0xfd
+#define SRSHARP0_LC_MAP_RAM_DATA (SRSHARP0_OFFSET + LC_MAP_RAM_DATA ) // 0xfe
+
+#define SRSHARP0_FMETER_CTRL (SRSHARP0_OFFSET + SHARP_FMETER_CTRL ) // 0x89
+#define SRSHARP0_FMETER_WIN_HOR (SRSHARP0_OFFSET + SHARP_FMETER_WIN_HOR ) // 0x8a
+#define SRSHARP0_FMETER_WIN_VER (SRSHARP0_OFFSET + SHARP_FMETER_WIN_VER ) // 0x8b
+#define SRSHARP0_FMETER_CORING (SRSHARP0_OFFSET + SHARP_FMETER_CORING ) // 0x8c
+#define SRSHARP0_FMETER_RATIO_H (SRSHARP0_OFFSET + SHARP_FMETER_RATIO_H ) // 0x8d
+#define SRSHARP0_FMETER_RATIO_V (SRSHARP0_OFFSET + SHARP_FMETER_RATIO_V ) // 0x8e
+#define SRSHARP0_FMETER_RATIO_D (SRSHARP0_OFFSET + SHARP_FMETER_RATIO_D ) // 0x8f
+#define SRSHARP0_RO_FMETER_HCNT_TYPE0 (SRSHARP0_OFFSET + SHARP_RO_FMETER_HCNT_TYPE0 ) // 0x46
+#define SRSHARP0_RO_FMETER_HCNT_TYPE1 (SRSHARP0_OFFSET + SHARP_RO_FMETER_HCNT_TYPE1 ) // 0x47
+#define SRSHARP0_RO_FMETER_HCNT_TYPE2 (SRSHARP0_OFFSET + SHARP_RO_FMETER_HCNT_TYPE2 ) // 0x48
+#define SRSHARP0_RO_FMETER_HCNT_TYPE3 (SRSHARP0_OFFSET + SHARP_RO_FMETER_HCNT_TYPE3 ) // 0x49
+#define SRSHARP0_RO_FMETER_VCNT_TYPE0 (SRSHARP0_OFFSET + SHARP_RO_FMETER_VCNT_TYPE0 ) // 0x4a
+#define SRSHARP0_RO_FMETER_VCNT_TYPE1 (SRSHARP0_OFFSET + SHARP_RO_FMETER_VCNT_TYPE1 ) // 0x4b
+#define SRSHARP0_RO_FMETER_VCNT_TYPE2 (SRSHARP0_OFFSET + SHARP_RO_FMETER_VCNT_TYPE2 ) // 0x4c
+#define SRSHARP0_RO_FMETER_VCNT_TYPE3 (SRSHARP0_OFFSET + SHARP_RO_FMETER_VCNT_TYPE3 ) // 0x4d
+#define SRSHARP0_RO_FMETER_PDCNT_TYPE0 (SRSHARP0_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE0 ) // 0x4e
+#define SRSHARP0_RO_FMETER_PDCNT_TYPE1 (SRSHARP0_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE1 ) // 0x4f
+#define SRSHARP0_RO_FMETER_PDCNT_TYPE2 (SRSHARP0_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE2 ) // 0x50
+#define SRSHARP0_RO_FMETER_PDCNT_TYPE3 (SRSHARP0_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE3 ) // 0x51
+#define SRSHARP0_RO_FMETER_NDCNT_TYPE0 (SRSHARP0_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE0 ) // 0x52
+#define SRSHARP0_RO_FMETER_NDCNT_TYPE1 (SRSHARP0_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE1 ) // 0x53
+#define SRSHARP0_RO_FMETER_NDCNT_TYPE2 (SRSHARP0_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE2 ) // 0x54
+#define SRSHARP0_RO_FMETER_NDCNT_TYPE3 (SRSHARP0_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE3 ) // 0x55
+
+
+
+
+
+//// srsharp1 reg define
+
+#define SRSHARP1_SHARP_HVSIZE (SRSHARP1_OFFSET + SHARP_HVSIZE ) //0x00 //
+#define SRSHARP1_SHARP_HVBLANK_NUM (SRSHARP1_OFFSET + SHARP_HVBLANK_NUM ) //0x01 //
+#define SRSHARP1_NR_GAUSSIAN_MODE (SRSHARP1_OFFSET + NR_GAUSSIAN_MODE ) //0x02 //
+#define SRSHARP1_PK_CON_2CIRHPGAIN_TH_RATE (SRSHARP1_OFFSET + PK_CON_2CIRHPGAIN_TH_RATE ) //0x05 //
+#define SRSHARP1_PK_CON_2CIRHPGAIN_LIMIT (SRSHARP1_OFFSET + PK_CON_2CIRHPGAIN_LIMIT ) //0x06 //
+#define SRSHARP1_PK_CON_2CIRBPGAIN_TH_RATE (SRSHARP1_OFFSET + PK_CON_2CIRBPGAIN_TH_RATE ) //0x07 //
+#define SRSHARP1_PK_CON_2CIRBPGAIN_LIMIT (SRSHARP1_OFFSET + PK_CON_2CIRBPGAIN_LIMIT ) //0x08 //
+#define SRSHARP1_PK_CON_2DRTHPGAIN_TH_RATE (SRSHARP1_OFFSET + PK_CON_2DRTHPGAIN_TH_RATE ) //0x09 //
+#define SRSHARP1_PK_CON_2DRTHPGAIN_LIMIT (SRSHARP1_OFFSET + PK_CON_2DRTHPGAIN_LIMIT ) //0x0a //
+#define SRSHARP1_PK_CON_2DRTBPGAIN_TH_RATE (SRSHARP1_OFFSET + PK_CON_2DRTBPGAIN_TH_RATE ) //0x0b //
+#define SRSHARP1_PK_CON_2DRTBPGAIN_LIMIT (SRSHARP1_OFFSET + PK_CON_2DRTBPGAIN_LIMIT ) //0x0c //
+#define SRSHARP1_PK_CIRFB_LPF_MODE (SRSHARP1_OFFSET + PK_CIRFB_LPF_MODE ) //0x0d //
+#define SRSHARP1_PK_DRTFB_LPF_MODE (SRSHARP1_OFFSET + PK_DRTFB_LPF_MODE ) //0x0e //
+#define SRSHARP1_PK_CIRFB_HP_CORING (SRSHARP1_OFFSET + PK_CIRFB_HP_CORING ) //0x0f //
+#define SRSHARP1_PK_CIRFB_BP_CORING (SRSHARP1_OFFSET + PK_CIRFB_BP_CORING ) //0x10 //
+#define SRSHARP1_PK_DRTFB_HP_CORING (SRSHARP1_OFFSET + PK_DRTFB_HP_CORING ) //0x11 //
+#define SRSHARP1_PK_DRTFB_BP_CORING (SRSHARP1_OFFSET + PK_DRTFB_BP_CORING ) //0x12 //
+#define SRSHARP1_PK_CIRFB_BLEND_GAIN (SRSHARP1_OFFSET + PK_CIRFB_BLEND_GAIN ) //0x13 //
+#define SRSHARP1_NR_ALPY_SSD_GAIN_OFST (SRSHARP1_OFFSET + NR_ALPY_SSD_GAIN_OFST ) //0x14 //
+#define SRSHARP1_NR_ALP0Y_ERR2CURV_TH_RATE (SRSHARP1_OFFSET + NR_ALP0Y_ERR2CURV_TH_RATE ) //0x15 //
+#define SRSHARP1_NR_ALP0Y_ERR2CURV_LIMIT (SRSHARP1_OFFSET + NR_ALP0Y_ERR2CURV_LIMIT ) //0x16 //
+#define SRSHARP1_NR_ALP0C_ERR2CURV_TH_RATE (SRSHARP1_OFFSET + NR_ALP0C_ERR2CURV_TH_RATE ) //0x17 //
+#define SRSHARP1_NR_ALP0C_ERR2CURV_LIMIT (SRSHARP1_OFFSET + NR_ALP0C_ERR2CURV_LIMIT ) //0x18 //
+#define SRSHARP1_NR_ALP0_MIN_MAX (SRSHARP1_OFFSET + NR_ALP0_MIN_MAX ) //0x19 //
+#define SRSHARP1_NR_ALP1_MIERR_CORING (SRSHARP1_OFFSET + NR_ALP1_MIERR_CORING ) //0x1a //
+#define SRSHARP1_NR_ALP1_ERR2CURV_TH_RATE (SRSHARP1_OFFSET + NR_ALP1_ERR2CURV_TH_RATE ) //0x1b //
+#define SRSHARP1_NR_ALP1_ERR2CURV_LIMIT (SRSHARP1_OFFSET + NR_ALP1_ERR2CURV_LIMIT ) //0x1c //
+#define SRSHARP1_NR_ALP1_MIN_MAX (SRSHARP1_OFFSET + NR_ALP1_MIN_MAX ) //0x1d //
+#define SRSHARP1_PK_ALP2_MIERR_CORING (SRSHARP1_OFFSET + PK_ALP2_MIERR_CORING ) //0x1e //
+#define SRSHARP1_PK_ALP2_ERR2CURV_TH_RATE (SRSHARP1_OFFSET + PK_ALP2_ERR2CURV_TH_RATE ) //0x1f //
+#define SRSHARP1_PK_ALP2_ERR2CURV_LIMIT (SRSHARP1_OFFSET + PK_ALP2_ERR2CURV_LIMIT ) //0x20 //
+#define SRSHARP1_PK_ALP2_MIN_MAX (SRSHARP1_OFFSET + PK_ALP2_MIN_MAX ) //0x21 //
+#define SRSHARP1_PK_FINALGAIN_HP_BP (SRSHARP1_OFFSET + PK_FINALGAIN_HP_BP ) //0x22 //
+#define SRSHARP1_PK_OS_HORZ_CORE_GAIN (SRSHARP1_OFFSET + PK_OS_HORZ_CORE_GAIN ) //0x23 //
+#define SRSHARP1_PK_OS_VERT_CORE_GAIN (SRSHARP1_OFFSET + PK_OS_VERT_CORE_GAIN ) //0x24 //
+#define SRSHARP1_PK_OS_ADPT_MISC (SRSHARP1_OFFSET + PK_OS_ADPT_MISC ) //0x25 //
+#define SRSHARP1_PK_OS_STATIC (SRSHARP1_OFFSET + PK_OS_STATIC ) //0x26 //
+#define SRSHARP1_PK_NR_ENABLE (SRSHARP1_OFFSET + PK_NR_ENABLE ) //0x27 //
+#define SRSHARP1_PK_DRT_SAD_MISC (SRSHARP1_OFFSET + PK_DRT_SAD_MISC ) //0x28 //
+#define SRSHARP1_NR_TI_DNLP_BLEND (SRSHARP1_OFFSET + NR_TI_DNLP_BLEND ) //0x29 //
+#define SRSHARP1_LTI_DIR_CORE_ALPHA (SRSHARP1_OFFSET + LTI_DIR_CORE_ALPHA ) //0x2a //
+#define SRSHARP1_CTI_DIR_ALPHA (SRSHARP1_OFFSET + CTI_DIR_ALPHA ) //0x2b //
+#define SRSHARP1_LTI_CTI_DF_GAIN (SRSHARP1_OFFSET + LTI_CTI_DF_GAIN ) //0x2c //
+#define SRSHARP1_LTI_CTI_DIR_AC_DBG (SRSHARP1_OFFSET + LTI_CTI_DIR_AC_DBG ) //0x2d //
+#define SRSHARP1_HCTI_FLT_CLP_DC (SRSHARP1_OFFSET + HCTI_FLT_CLP_DC ) //0x2e //
+#define SRSHARP1_HCTI_BST_GAIN (SRSHARP1_OFFSET + HCTI_BST_GAIN ) //0x2f //
+#define SRSHARP1_HCTI_BST_CORE (SRSHARP1_OFFSET + HCTI_BST_CORE ) //0x30 //
+#define SRSHARP1_HCTI_CON_2_GAIN_0 (SRSHARP1_OFFSET + HCTI_CON_2_GAIN_0 ) //0x31 //
+#define SRSHARP1_HCTI_CON_2_GAIN_1 (SRSHARP1_OFFSET + HCTI_CON_2_GAIN_1 ) //0x32 //
+#define SRSHARP1_HCTI_OS_MARGIN (SRSHARP1_OFFSET + HCTI_OS_MARGIN ) //0x33 //
+#define SRSHARP1_HLTI_FLT_CLP_DC (SRSHARP1_OFFSET + HLTI_FLT_CLP_DC ) //0x34 //
+#define SRSHARP1_HLTI_BST_GAIN (SRSHARP1_OFFSET + HLTI_BST_GAIN ) //0x35 //
+#define SRSHARP1_HLTI_BST_CORE (SRSHARP1_OFFSET + HLTI_BST_CORE ) //0x36 //
+#define SRSHARP1_HLTI_CON_2_GAIN_0 (SRSHARP1_OFFSET + HLTI_CON_2_GAIN_0 ) //0x37 //
+#define SRSHARP1_HLTI_CON_2_GAIN_1 (SRSHARP1_OFFSET + HLTI_CON_2_GAIN_1 ) //0x38 //
+#define SRSHARP1_HLTI_OS_MARGIN (SRSHARP1_OFFSET + HLTI_OS_MARGIN ) //0x39 //
+#define SRSHARP1_VLTI_FLT_CON_CLP (SRSHARP1_OFFSET + VLTI_FLT_CON_CLP ) //0x3a //
+#define SRSHARP1_VLTI_BST_GAIN (SRSHARP1_OFFSET + VLTI_BST_GAIN ) //0x3b //
+#define SRSHARP1_VLTI_BST_CORE (SRSHARP1_OFFSET + VLTI_BST_CORE ) //0x3c //
+#define SRSHARP1_VLTI_CON_2_GAIN_0 (SRSHARP1_OFFSET + VLTI_CON_2_GAIN_0 ) //0x3d //
+#define SRSHARP1_VLTI_CON_2_GAIN_1 (SRSHARP1_OFFSET + VLTI_CON_2_GAIN_1 ) //0x3e //
+#define SRSHARP1_VCTI_FLT_CON_CLP (SRSHARP1_OFFSET + VCTI_FLT_CON_CLP ) //0x3f //
+#define SRSHARP1_VCTI_BST_GAIN (SRSHARP1_OFFSET + VCTI_BST_GAIN ) //0x40 //
+#define SRSHARP1_VCTI_BST_CORE (SRSHARP1_OFFSET + VCTI_BST_CORE ) //0x41 //
+#define SRSHARP1_VCTI_CON_2_GAIN_0 (SRSHARP1_OFFSET + VCTI_CON_2_GAIN_0 ) //0x42 //
+#define SRSHARP1_VCTI_CON_2_GAIN_1 (SRSHARP1_OFFSET + VCTI_CON_2_GAIN_1 ) //0x43 //
+#define SRSHARP1_SHARP_3DLIMIT (SRSHARP1_OFFSET + SHARP_3DLIMIT ) //0x44 //
+#define SRSHARP1_DNLP_EN (SRSHARP1_OFFSET + DNLP_EN ) //0x45 //
+//`define SRSHARP1_DNLP_00 (`SRSHARP1_OFFSET + `DNLP_00 ) //8'h46 //
+//`define SRSHARP1_DNLP_01 (`SRSHARP1_OFFSET + `DNLP_01 ) //8'h47 //
+//`define SRSHARP1_DNLP_02 (`SRSHARP1_OFFSET + `DNLP_02 ) //8'h48 //
+//`define SRSHARP1_DNLP_03 (`SRSHARP1_OFFSET + `DNLP_03 ) //8'h49 //
+//`define SRSHARP1_DNLP_04 (`SRSHARP1_OFFSET + `DNLP_04 ) //8'h4a //
+//`define SRSHARP1_DNLP_05 (`SRSHARP1_OFFSET + `DNLP_05 ) //8'h4b //
+//`define SRSHARP1_DNLP_06 (`SRSHARP1_OFFSET + `DNLP_06 ) //8'h4c //
+//`define SRSHARP1_DNLP_07 (`SRSHARP1_OFFSET + `DNLP_07 ) //8'h4d //
+//`define SRSHARP1_DNLP_08 (`SRSHARP1_OFFSET + `DNLP_08 ) //8'h4e //
+//`define SRSHARP1_DNLP_09 (`SRSHARP1_OFFSET + `DNLP_09 ) //8'h4f //
+//`define SRSHARP1_DNLP_10 (`SRSHARP1_OFFSET + `DNLP_10 ) //8'h50 //
+//`define SRSHARP1_DNLP_11 (`SRSHARP1_OFFSET + `DNLP_11 ) //8'h51 //
+//`define SRSHARP1_DNLP_12 (`SRSHARP1_OFFSET + `DNLP_12 ) //8'h52 //
+//`define SRSHARP1_DNLP_13 (`SRSHARP1_OFFSET + `DNLP_13 ) //8'h53 //
+//`define SRSHARP1_DNLP_14 (`SRSHARP1_OFFSET + `DNLP_14 ) //8'h54 //
+//`define SRSHARP1_DNLP_15 (`SRSHARP1_OFFSET + `DNLP_15 ) //8'h55 //
+#define SRSHARP1_DEMO_CRTL (SRSHARP1_OFFSET + DEMO_CRTL ) //0x56 //
+#define SRSHARP1_SHARP_SR2_CTRL (SRSHARP1_OFFSET + SHARP_SR2_CTRL ) //0x57 //
+#define SRSHARP1_SHARP_SR2_YBIC_HCOEF0 (SRSHARP1_OFFSET + SHARP_SR2_YBIC_HCOEF0 ) //0x58
+#define SRSHARP1_SHARP_SR2_YBIC_HCOEF1 (SRSHARP1_OFFSET + SHARP_SR2_YBIC_HCOEF1 ) //0x59 //
+#define SRSHARP1_SHARP_SR2_CBIC_HCOEF0 (SRSHARP1_OFFSET + SHARP_SR2_CBIC_HCOEF0 ) //0x5a //
+#define SRSHARP1_SHARP_SR2_CBIC_HCOEF1 (SRSHARP1_OFFSET + SHARP_SR2_CBIC_HCOEF1 ) //0x5b //
+#define SRSHARP1_SHARP_SR2_YBIC_VCOEF0 (SRSHARP1_OFFSET + SHARP_SR2_YBIC_VCOEF0 ) //0x5c //
+#define SRSHARP1_SHARP_SR2_YBIC_VCOEF1 (SRSHARP1_OFFSET + SHARP_SR2_YBIC_VCOEF1 ) //0x5d //
+#define SRSHARP1_SHARP_SR2_CBIC_VCOEF0 (SRSHARP1_OFFSET + SHARP_SR2_CBIC_VCOEF0 ) //0x5e //
+#define SRSHARP1_SHARP_SR2_CBIC_VCOEF1 (SRSHARP1_OFFSET + SHARP_SR2_CBIC_VCOEF1 ) //0x5f //
+#define SRSHARP1_SHARP_SR2_MISC (SRSHARP1_OFFSET + SHARP_SR2_MISC ) //0x60 //
+#define SRSHARP1_SR3_SAD_CTRL (SRSHARP1_OFFSET + SHARP_SR3_SAD_CTRL ) // 0x61 //
+#define SRSHARP1_SR3_PK_CTRL0 (SRSHARP1_OFFSET + SHARP_SR3_PK_CTRL0 ) // 0x62
+#define SRSHARP1_SR3_PK_CTRL1 (SRSHARP1_OFFSET + SHARP_SR3_PK_CTRL1 ) // 0x63
+#define SRSHARP1_DEJ_CTRL (SRSHARP1_OFFSET + SHARP_DEJ_CTRL ) // 0x64
+#define SRSHARP1_DEJ_ALPHA (SRSHARP1_OFFSET + SHARP_DEJ_ALPHA ) // 0x65
+#define SRSHARP1_SR3_DRTLPF_EN (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_EN ) // 0x66
+#define SRSHARP1_SR3_DRTLPF_ALPHA_0 (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_ALPHA_0 ) // 0x67
+#define SRSHARP1_SR3_DRTLPF_ALPHA_1 (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_ALPHA_1 ) // 0x68
+#define SRSHARP1_SR3_DRTLPF_ALPHA_2 (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_ALPHA_2 ) // 0x69
+#define SRSHARP1_SR3_DRTLPF_ALPHA_OFST (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_ALPHA_OFST ) // 0x6a
+#define SRSHARP1_SR3_DERING_CTRL (SRSHARP1_OFFSET + SHARP_SR3_DERING_CTRL ) // 0x6b
+#define SRSHARP1_SR3_DERING_LUMA2PKGAIN_0TO3 (SRSHARP1_OFFSET + SHARP_SR3_DERING_LUMA2PKGAIN_0TO3 ) // 0x6c
+#define SRSHARP1_SR3_DERING_LUMA2PKGAIN_4TO6 (SRSHARP1_OFFSET + SHARP_SR3_DERING_LUMA2PKGAIN_4TO6 ) // 0x6d
+#define SRSHARP1_SR3_DERING_LUMA2PKOS_0TO3 (SRSHARP1_OFFSET + SHARP_SR3_DERING_LUMA2PKOS_0TO3 ) // 0x6e
+#define SRSHARP1_SR3_DERING_LUMA2PKOS_4TO6 (SRSHARP1_OFFSET + SHARP_SR3_DERING_LUMA2PKOS_4TO6 ) // 0x6f
+#define SRSHARP1_SR3_DERING_GAINVS_MADSAD (SRSHARP1_OFFSET + SHARP_SR3_DERING_GAINVS_MADSAD ) // 0x70
+#define SRSHARP1_SR3_DERING_GAINVS_VR2MAX (SRSHARP1_OFFSET + SHARP_SR3_DERING_GAINVS_VR2MAX ) // 0x71
+#define SRSHARP1_SR3_DERING_PARAM0 (SRSHARP1_OFFSET + SHARP_SR3_DERING_PARAM0 ) // 0x72
+#define SRSHARP1_SR3_DRTLPF_THETA (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_THETA ) // 0x73
+#define SRSHARP1_SATPRT_CTRL (SRSHARP1_OFFSET + SHARP_SATPRT_CTRL ) // 0x74
+#define SRSHARP1_SATPRT_DIVM (SRSHARP1_OFFSET + SHARP_SATPRT_DIVM ) // 0x75
+#define SRSHARP1_DB_FLT_CTRL (SRSHARP1_OFFSET + SHARP_DB_FLT_CTRL ) // 0x77
+//`define SRSHARP1_DB_FLT_YC_THRD (`SRSHARP1_OFFSET + `SHARP_DB_FLT_YC_THRD ) // 8'h78
+#define SRSHARP1_DB_FLT_CTRL1 (SRSHARP1_OFFSET + SHARP_DB_FLT_CTRL1 ) // 0xb8
+#define SRSHARP1_DB_FLT_LUMA_THRD (SRSHARP1_OFFSET + SHARP_DB_FLT_LUMA_THRD ) // 0xb9
+#define SRSHARP1_DB_FLT_CHRM_THRD (SRSHARP1_OFFSET + SHARP_DB_FLT_CHRM_THRD ) // 0xba
+#define SRSHARP1_DB_FLT_RANDLUT (SRSHARP1_OFFSET + SHARP_DB_FLT_RANDLUT ) // 0x79
+#define SRSHARP1_DB_FLT_PXI_THRD (SRSHARP1_OFFSET + SHARP_DB_FLT_PXI_THRD ) // 0x7a
+#define SRSHARP1_DB_FLT_SEED_Y (SRSHARP1_OFFSET + SHARP_DB_FLT_SEED_Y ) // 0x7b
+#define SRSHARP1_DB_FLT_SEED_U (SRSHARP1_OFFSET + SHARP_DB_FLT_SEED_U ) // 0x7c
+#define SRSHARP1_DB_FLT_SEED_V (SRSHARP1_OFFSET + SHARP_DB_FLT_SEED_V ) // 0x7d
+#define SRSHARP1_PKGAIN_VSLUMA_LUT_L (SRSHARP1_OFFSET + SHARP_PKGAIN_VSLUMA_LUT_L ) // 0x7e
+#define SRSHARP1_PKGAIN_VSLUMA_LUT_H (SRSHARP1_OFFSET + SHARP_PKGAIN_VSLUMA_LUT_H ) // 0x7f
+#define SRSHARP1_PKOSHT_VSLUMA_LUT_L (SRSHARP1_OFFSET + SHARP_PKOSHT_VSLUMA_LUT_L ) // 0x80
+#define SRSHARP1_PKOSHT_VSLUMA_LUT_H (SRSHARP1_OFFSET + SHARP_PKOSHT_VSLUMA_LUT_H ) // 0x81
+#define SRSHARP1_SATPRT_LMT_RGB1 (SRSHARP1_OFFSET + SHARP_SATPRT_LMT_RGB1 ) // 0x82
+#define SRSHARP1_SATPRT_LMT_RGB2 (SRSHARP1_OFFSET + SHARP_SATPRT_LMT_RGB2 ) // 0x83
+#define SRSHARP1_SHARP_GATE_CLK_CTRL_0 (SRSHARP1_OFFSET + SHARP_GATE_CLK_CTRL_0 ) // 0x84
+#define SRSHARP1_SHARP_GATE_CLK_CTRL_1 (SRSHARP1_OFFSET + SHARP_GATE_CLK_CTRL_1 ) // 0x85
+#define SRSHARP1_SHARP_GATE_CLK_CTRL_2 (SRSHARP1_OFFSET + SHARP_GATE_CLK_CTRL_2 ) // 0x86
+#define SRSHARP1_SHARP_GATE_CLK_CTRL_3 (SRSHARP1_OFFSET + SHARP_GATE_CLK_CTRL_3 ) // 0x87
+#define SRSHARP1_SHARP_DPS_CTRL (SRSHARP1_OFFSET + SHARP_DPS_CTRL ) // 0x88
+#define SRSHARP1_DNLP_00 (SRSHARP1_OFFSET + DNLP_00 ) // 0x90 //
+#define SRSHARP1_DNLP_01 (SRSHARP1_OFFSET + DNLP_01 ) // 0x91 //
+#define SRSHARP1_DNLP_02 (SRSHARP1_OFFSET + DNLP_02 ) // 0x92 //
+#define SRSHARP1_DNLP_03 (SRSHARP1_OFFSET + DNLP_03 ) // 0x93 //
+#define SRSHARP1_DNLP_04 (SRSHARP1_OFFSET + DNLP_04 ) // 0x94 //
+#define SRSHARP1_DNLP_05 (SRSHARP1_OFFSET + DNLP_05 ) // 0x95 //
+#define SRSHARP1_DNLP_06 (SRSHARP1_OFFSET + DNLP_06 ) // 0x96 //
+#define SRSHARP1_DNLP_07 (SRSHARP1_OFFSET + DNLP_07 ) // 0x97 //
+#define SRSHARP1_DNLP_08 (SRSHARP1_OFFSET + DNLP_08 ) // 0x98 //
+#define SRSHARP1_DNLP_09 (SRSHARP1_OFFSET + DNLP_09 ) // 0x99 //
+#define SRSHARP1_DNLP_10 (SRSHARP1_OFFSET + DNLP_10 ) // 0x9a //
+#define SRSHARP1_DNLP_11 (SRSHARP1_OFFSET + DNLP_11 ) // 0x9b //
+#define SRSHARP1_DNLP_12 (SRSHARP1_OFFSET + DNLP_12 ) // 0x9c //
+#define SRSHARP1_DNLP_13 (SRSHARP1_OFFSET + DNLP_13 ) // 0x9d //
+#define SRSHARP1_DNLP_14 (SRSHARP1_OFFSET + DNLP_14 ) // 0x9e //
+#define SRSHARP1_DNLP_15 (SRSHARP1_OFFSET + DNLP_15 ) // 0x9f //
+#define SRSHARP1_DNLP_16 (SRSHARP1_OFFSET + DNLP_16 ) // 0xa0 //
+#define SRSHARP1_DNLP_17 (SRSHARP1_OFFSET + DNLP_17 ) // 0xa1 //
+#define SRSHARP1_DNLP_18 (SRSHARP1_OFFSET + DNLP_18 ) // 0xa2 //
+#define SRSHARP1_DNLP_19 (SRSHARP1_OFFSET + DNLP_19 ) // 0xa3 //
+#define SRSHARP1_DNLP_20 (SRSHARP1_OFFSET + DNLP_20 ) // 0xa4 //
+#define SRSHARP1_DNLP_21 (SRSHARP1_OFFSET + DNLP_21 ) // 0xa5 //
+#define SRSHARP1_DNLP_22 (SRSHARP1_OFFSET + DNLP_22 ) // 0xa6 //
+#define SRSHARP1_DNLP_23 (SRSHARP1_OFFSET + DNLP_23 ) // 0xa7 //
+#define SRSHARP1_DNLP_24 (SRSHARP1_OFFSET + DNLP_24 ) // 0xa8 //
+#define SRSHARP1_DNLP_25 (SRSHARP1_OFFSET + DNLP_25 ) // 0xa9 //
+#define SRSHARP1_DNLP_26 (SRSHARP1_OFFSET + DNLP_26 ) // 0xaa //
+#define SRSHARP1_DNLP_27 (SRSHARP1_OFFSET + DNLP_27 ) // 0xab //
+#define SRSHARP1_DNLP_28 (SRSHARP1_OFFSET + DNLP_28 ) // 0xac //
+#define SRSHARP1_DNLP_29 (SRSHARP1_OFFSET + DNLP_29 ) // 0xad //
+#define SRSHARP1_DNLP_30 (SRSHARP1_OFFSET + DNLP_30 ) // 0xae //
+#define SRSHARP1_DNLP_31 (SRSHARP1_OFFSET + DNLP_31 ) // 0xaf //
+#define SRSHARP1_SHARP_SYNC_CTRL (SRSHARP1_OFFSET + SHARP_SYNC_CTRL ) // 0xb0 //
+#define SRSHARP1_LC_INPUT_MUX (SRSHARP1_OFFSET + LC_INPUT_MUX ) // 0xb1 //
+#define SRSHARP1_NR_GAU_YH_COEF02 (SRSHARP1_OFFSET + NR_GAU_YH_COEF02 ) // 0xb2 //
+#define SRSHARP1_NR_GAU_YH_COEF34 (SRSHARP1_OFFSET + NR_GAU_YH_COEF34 ) // 0xb3 //
+#define SRSHARP1_NR_GAU_YV_COEF1 (SRSHARP1_OFFSET + NR_GAU_YV_COEF1 ) // 0xb4 //
+#define SRSHARP1_NR_GAU_CH_COEF02 (SRSHARP1_OFFSET + NR_GAU_CH_COEF02 ) // 0xb5 //
+#define SRSHARP1_NR_GAU_CH_COEF34 (SRSHARP1_OFFSET + NR_GAU_CH_COEF34 ) // 0xb6 //
+#define SRSHARP1_NR_GAU_CV_COEF1 (SRSHARP1_OFFSET + NR_GAU_CV_COEF1 ) // 0xb7 //
+#define SRSHARP1_LC_TOP_CTRL (SRSHARP1_OFFSET + LC_TOP_CTRL ) // 0xc0 //
+#define SRSHARP1_LC_HV_NUM (SRSHARP1_OFFSET + LC_HV_NUM ) // 0xc1
+#define SRSHARP1_LC_SAT_LUT_0_1 (SRSHARP1_OFFSET + LC_SAT_LUT_0_1 ) // 0xc2
+#define SRSHARP1_LC_SAT_LUT_2_3 (SRSHARP1_OFFSET + LC_SAT_LUT_2_3 ) // 0xc3
+#define SRSHARP1_LC_SAT_LUT_4_5 (SRSHARP1_OFFSET + LC_SAT_LUT_4_5 ) // 0xc4
+#define SRSHARP1_LC_SAT_LUT_6_7 (SRSHARP1_OFFSET + LC_SAT_LUT_6_7 ) // 0xc5
+#define SRSHARP1_LC_SAT_LUT_8_9 (SRSHARP1_OFFSET + LC_SAT_LUT_8_9 ) // 0xc6
+#define SRSHARP1_LC_SAT_LUT_10_11 (SRSHARP1_OFFSET + LC_SAT_LUT_10_11 ) // 0xc7
+#define SRSHARP1_LC_SAT_LUT_12_13 (SRSHARP1_OFFSET + LC_SAT_LUT_12_13 ) // 0xc8
+#define SRSHARP1_LC_SAT_LUT_14_15 (SRSHARP1_OFFSET + LC_SAT_LUT_14_15 ) // 0xc9
+#define SRSHARP1_LC_SAT_LUT_16_17 (SRSHARP1_OFFSET + LC_SAT_LUT_16_17 ) // 0xca
+#define SRSHARP1_LC_SAT_LUT_18_19 (SRSHARP1_OFFSET + LC_SAT_LUT_18_19 ) // 0xcb
+#define SRSHARP1_LC_SAT_LUT_20_21 (SRSHARP1_OFFSET + LC_SAT_LUT_20_21 ) // 0xcc
+#define SRSHARP1_LC_SAT_LUT_22_23 (SRSHARP1_OFFSET + LC_SAT_LUT_22_23 ) // 0xcd
+#define SRSHARP1_LC_SAT_LUT_24_25 (SRSHARP1_OFFSET + LC_SAT_LUT_24_25 ) // 0xce
+#define SRSHARP1_LC_SAT_LUT_26_27 (SRSHARP1_OFFSET + LC_SAT_LUT_26_27 ) // 0xcf
+#define SRSHARP1_LC_SAT_LUT_28_29 (SRSHARP1_OFFSET + LC_SAT_LUT_28_29 ) // 0xd0
+#define SRSHARP1_LC_SAT_LUT_30_31 (SRSHARP1_OFFSET + LC_SAT_LUT_30_31 ) // 0xd1
+#define SRSHARP1_LC_SAT_LUT_32_33 (SRSHARP1_OFFSET + LC_SAT_LUT_32_33 ) // 0xd2
+#define SRSHARP1_LC_SAT_LUT_34_35 (SRSHARP1_OFFSET + LC_SAT_LUT_34_35 ) // 0xd3
+#define SRSHARP1_LC_SAT_LUT_36_37 (SRSHARP1_OFFSET + LC_SAT_LUT_36_37 ) // 0xd4
+#define SRSHARP1_LC_SAT_LUT_38_39 (SRSHARP1_OFFSET + LC_SAT_LUT_38_39 ) // 0xd5
+#define SRSHARP1_LC_SAT_LUT_40_41 (SRSHARP1_OFFSET + LC_SAT_LUT_40_41 ) // 0xd6
+#define SRSHARP1_LC_SAT_LUT_42_43 (SRSHARP1_OFFSET + LC_SAT_LUT_42_43 ) // 0xd7
+#define SRSHARP1_LC_SAT_LUT_44_45 (SRSHARP1_OFFSET + LC_SAT_LUT_44_45 ) // 0xd8
+#define SRSHARP1_LC_SAT_LUT_46_47 (SRSHARP1_OFFSET + LC_SAT_LUT_46_47 ) // 0xd9
+#define SRSHARP1_LC_SAT_LUT_48_49 (SRSHARP1_OFFSET + LC_SAT_LUT_48_49 ) // 0xda
+#define SRSHARP1_LC_SAT_LUT_50_51 (SRSHARP1_OFFSET + LC_SAT_LUT_50_51 ) // 0xdb
+#define SRSHARP1_LC_SAT_LUT_52_53 (SRSHARP1_OFFSET + LC_SAT_LUT_52_53 ) // 0xdc
+#define SRSHARP1_LC_SAT_LUT_54_55 (SRSHARP1_OFFSET + LC_SAT_LUT_54_55 ) // 0xdd
+#define SRSHARP1_LC_SAT_LUT_56_57 (SRSHARP1_OFFSET + LC_SAT_LUT_56_57 ) // 0xde
+#define SRSHARP1_LC_SAT_LUT_58_59 (SRSHARP1_OFFSET + LC_SAT_LUT_58_59 ) // 0xdf
+#define SRSHARP1_LC_SAT_LUT_60_61 (SRSHARP1_OFFSET + LC_SAT_LUT_60_61 ) // 0xe0
+#define SRSHARP1_LC_SAT_LUT_62 (SRSHARP1_OFFSET + LC_SAT_LUT_62 ) // 0xe1
+#define SRSHARP1_LC_CURVE_BLK_HIDX_0_1 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_0_1 ) // 0xe2
+#define SRSHARP1_LC_CURVE_BLK_HIDX_2_3 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_2_3 ) // 0xe3
+#define SRSHARP1_LC_CURVE_BLK_HIDX_4_5 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_4_5 ) // 0xe4
+#define SRSHARP1_LC_CURVE_BLK_HIDX_6_7 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_6_7 ) // 0xe5
+#define SRSHARP1_LC_CURVE_BLK_HIDX_8_9 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_8_9 ) // 0xe6
+#define SRSHARP1_LC_CURVE_BLK_HIDX_10_11 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_10_11 ) // 0xe7
+#define SRSHARP1_LC_CURVE_BLK_HIDX_12 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_12 ) // 0xe8
+#define SRSHARP1_LC_CURVE_BLK_VIDX_0_1 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_0_1 ) // 0xe9
+#define SRSHARP1_LC_CURVE_BLK_VIDX_2_3 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_2_3 ) // 0xea
+#define SRSHARP1_LC_CURVE_BLK_VIDX_4_5 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_4_5 ) // 0xeb
+#define SRSHARP1_LC_CURVE_BLK_VIDX_6_7 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_6_7 ) // 0xec
+#define SRSHARP1_LC_CURVE_BLK_VIDX_8 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_8 ) // 0xed
+#define SRSHARP1_LC_YUV2RGB_MAT_0_1 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_0_1 ) // 0xee
+#define SRSHARP1_LC_YUV2RGB_MAT_2_3 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_2_3 ) // 0xef
+#define SRSHARP1_LC_YUV2RGB_MAT_4_5 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_4_5 ) // 0xf0
+#define SRSHARP1_LC_YUV2RGB_MAT_6_7 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_6_7 ) // 0xf1
+#define SRSHARP1_LC_YUV2RGB_MAT_8 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_8 ) // 0xf2
+#define SRSHARP1_LC_RGB2YUV_MAT_0_1 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_0_1 ) // 0xf3
+#define SRSHARP1_LC_RGB2YUV_MAT_2_3 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_2_3 ) // 0xf4
+#define SRSHARP1_LC_RGB2YUV_MAT_4_5 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_4_5 ) // 0xf5
+#define SRSHARP1_LC_RGB2YUV_MAT_6_7 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_6_7 ) // 0xf6
+#define SRSHARP1_LC_RGB2YUV_MAT_8 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_8 ) // 0xf7
+#define SRSHARP1_LC_YUV2RGB_OFST (SRSHARP1_OFFSET + LC_YUV2RGB_OFST ) // 0xf8
+#define SRSHARP1_LC_YUV2RGB_CLIP (SRSHARP1_OFFSET + LC_YUV2RGB_CLIP ) // 0xf9
+#define SRSHARP1_LC_RGB2YUV_OFST (SRSHARP1_OFFSET + LC_RGB2YUV_OFST ) // 0xfa
+#define SRSHARP1_LC_RGB2YUV_CLIP (SRSHARP1_OFFSET + LC_RGB2YUV_CLIP ) // 0xfb
+#define SRSHARP1_LC_MAP_RAM_CTRL (SRSHARP1_OFFSET + LC_MAP_RAM_CTRL ) // 0xfc
+#define SRSHARP1_LC_MAP_RAM_ADDR (SRSHARP1_OFFSET + LC_MAP_RAM_ADDR ) // 0xfd
+#define SRSHARP1_LC_MAP_RAM_DATA (SRSHARP1_OFFSET + LC_MAP_RAM_DATA ) // 0xfe
+
+#define SRSHARP1_FMETER_CTRL (SRSHARP1_OFFSET + SHARP_FMETER_CTRL ) // 0x89
+#define SRSHARP1_FMETER_WIN_HOR (SRSHARP1_OFFSET + SHARP_FMETER_WIN_HOR ) // 0x8a
+#define SRSHARP1_FMETER_WIN_VER (SRSHARP1_OFFSET + SHARP_FMETER_WIN_VER ) // 0x8b
+#define SRSHARP1_FMETER_CORING (SRSHARP1_OFFSET + SHARP_FMETER_CORING ) // 0x8c
+#define SRSHARP1_FMETER_RATIO_H (SRSHARP1_OFFSET + SHARP_FMETER_RATIO_H ) // 0x8d
+#define SRSHARP1_FMETER_RATIO_V (SRSHARP1_OFFSET + SHARP_FMETER_RATIO_V ) // 0x8e
+#define SRSHARP1_FMETER_RATIO_D (SRSHARP1_OFFSET + SHARP_FMETER_RATIO_D ) // 0x8f
+#define SRSHARP1_RO_FMETER_HCNT_TYPE0 (SRSHARP1_OFFSET + SHARP_RO_FMETER_HCNT_TYPE0 ) // 0x46
+#define SRSHARP1_RO_FMETER_HCNT_TYPE1 (SRSHARP1_OFFSET + SHARP_RO_FMETER_HCNT_TYPE1 ) // 0x47
+#define SRSHARP1_RO_FMETER_HCNT_TYPE2 (SRSHARP1_OFFSET + SHARP_RO_FMETER_HCNT_TYPE2 ) // 0x48
+#define SRSHARP1_RO_FMETER_HCNT_TYPE3 (SRSHARP1_OFFSET + SHARP_RO_FMETER_HCNT_TYPE3 ) // 0x49
+#define SRSHARP1_RO_FMETER_VCNT_TYPE0 (SRSHARP1_OFFSET + SHARP_RO_FMETER_VCNT_TYPE0 ) // 0x4a
+#define SRSHARP1_RO_FMETER_VCNT_TYPE1 (SRSHARP1_OFFSET + SHARP_RO_FMETER_VCNT_TYPE1 ) // 0x4b
+#define SRSHARP1_RO_FMETER_VCNT_TYPE2 (SRSHARP1_OFFSET + SHARP_RO_FMETER_VCNT_TYPE2 ) // 0x4c
+#define SRSHARP1_RO_FMETER_VCNT_TYPE3 (SRSHARP1_OFFSET + SHARP_RO_FMETER_VCNT_TYPE3 ) // 0x4d
+#define SRSHARP1_RO_FMETER_PDCNT_TYPE0 (SRSHARP1_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE0 ) // 0x4e
+#define SRSHARP1_RO_FMETER_PDCNT_TYPE1 (SRSHARP1_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE1 ) // 0x4f
+#define SRSHARP1_RO_FMETER_PDCNT_TYPE2 (SRSHARP1_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE2 ) // 0x50
+#define SRSHARP1_RO_FMETER_PDCNT_TYPE3 (SRSHARP1_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE3 ) // 0x51
+#define SRSHARP1_RO_FMETER_NDCNT_TYPE0 (SRSHARP1_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE0 ) // 0x52
+#define SRSHARP1_RO_FMETER_NDCNT_TYPE1 (SRSHARP1_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE1 ) // 0x53
+#define SRSHARP1_RO_FMETER_NDCNT_TYPE2 (SRSHARP1_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE2 ) // 0x54
+#define SRSHARP1_RO_FMETER_NDCNT_TYPE3 (SRSHARP1_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE3 ) // 0x55
+
+
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: srsharp_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: VPPE_VCBUS_BASE = 0x51
+// -----------------------------------------------
+// 8'h50/51/52/53 have used for srsharp_regs
+//
+// Reading file: srsharp_regs2.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//SRSHARP0 8'h00 - 8'hff
+//SRSHARP1 8'h100 - 8'1ff
+#define SRSHARP0_OFFSET (0x000<<2)
+#define SRSHARP1_OFFSET (0x200<<2)
+
+//
+// Reading file: sharp_regs2.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define SR7_DRTLPF_EN ((0x5100 << 2) + 0xff000000)
+//Bit 31:11, reserved
+//Bit 10, reg_sr7_drtlpf_beta_en2 : enable of direction ambiguity protection for drt_lpf, beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), 0, equivalent beta[i]=15, 1, enable. unsigned , default = 0
+//Bit 9, reg_sr7_drtlpf_beta_en1 : enable of direction ambiguity protection for drt_lpf, beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), 0, equivalent beta[i]=15, 1, enable. unsigned , default = 0
+//Bit 8, reg_sr7_drtlpf_beta_en0 : enable of direction ambiguity protection for drt_lpf, beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), 0, equivalent beta[i]=15, 1, enable. unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5, reg_sr7_drtlpf_edge_en2 : enable of direction lpf based on edge strength. unsigned , default = 0
+//Bit 4, reg_sr7_drtlpf_edge_en1 : enable of direction lpf based on edge strength. unsigned , default = 0
+//Bit 3, reg_sr7_drtlpf_edge_en0 : enable of direction lpf based on edge strength. unsigned , default = 0
+//Bit 2, reg_sr7_drtlpf_sdfd_en2 : sdfd gamma (HF burst compare to real edge protection) enable. 0: not enable, 1:enable protection. unsigned , default = 1
+//Bit 1, reg_sr7_drtlpf_sdfd_en1 : sdfd gamma (HF burst compare to real edge protection) enable. 0: not enable, 1:enable protection. unsigned , default = 1
+//Bit 0, reg_sr7_drtlpf_sdfd_en0 : sdfd gamma (HF burst compare to real edge protection) enable. 0: not enable, 1:enable protection. unsigned , default = 1
+#define SR7_DRTLPF_BETA ((0x5101 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_drtlpf_beta3 : beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo lpf. unsigned , default = 0
+//Bit 11: 8, reg_sr7_drtlpf_beta2 : beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo lpf. unsigned , default = 4
+//Bit 7: 4, reg_sr7_drtlpf_beta1 : beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo lpf. unsigned , default = 8
+//Bit 3: 0, reg_sr7_drtlpf_beta0 : beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo lpf. unsigned , default = 15
+#define SR7_PKBLD_BETA ((0x5102 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_pkdrtbld_beta3 : beta for drt and cir blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use cir wo drt. unsigned , default = 0
+//Bit 11: 8, reg_sr7_pkdrtbld_beta2 : beta for drt and cir blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use cir wo drt. unsigned , default = 4
+//Bit 7: 4, reg_sr7_pkdrtbld_beta1 : beta for drt and cir blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use cir wo drt. unsigned , default = 8
+//Bit 3: 0, reg_sr7_pkdrtbld_beta0 : beta for drt and cir blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use cir wo drt. unsigned , default = 15
+#define SR7_XLTIBLD_BETA ((0x5103 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_xlti_dcbld_beta3 : beta for denoise and org dc blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 0
+//Bit 11: 8, reg_sr7_xlti_dcbld_beta2 : beta for denoise and org dc blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 4
+//Bit 7: 4, reg_sr7_xlti_dcbld_beta1 : beta for denoise and org dc blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 8
+//Bit 3: 0, reg_sr7_xlti_dcbld_beta0 : beta for denoise and org dc blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 15
+#define SR7_DRTLPF_EDGE0 ((0x5104 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_drtlpf_edge7 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_drtlpf_edge6 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_drtlpf_edge5 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_drtlpf_edge4 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_drtlpf_edge3 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_drtlpf_edge2 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_drtlpf_edge1 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_drtlpf_edge0 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+#define SR7_DRTLPF_EDGE1 ((0x5105 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_drtlpf_edge15 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_drtlpf_edge14 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_drtlpf_edge13 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_drtlpf_edge12 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_drtlpf_edge11 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_drtlpf_edge10 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_drtlpf_edge9 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_drtlpf_edge8 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+#define SR7_DRTLPF_SDCOR0 ((0x5106 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_drtlpf_sdcor7 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_drtlpf_sdcor6 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_drtlpf_sdcor5 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_drtlpf_sdcor4 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_drtlpf_sdcor3 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_drtlpf_sdcor2 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_drtlpf_sdcor1 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_drtlpf_sdcor0 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+#define SR7_DRTLPF_SDCOR1 ((0x5107 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_drtlpf_sdcor15 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_drtlpf_sdcor14 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_drtlpf_sdcor13 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_drtlpf_sdcor12 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_drtlpf_sdcor11 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_drtlpf_sdcor10 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_drtlpf_sdcor9 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_drtlpf_sdcor8 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+#define SR7_CTIGAIN_SDCOR0 ((0x5108 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_ctigain_sdcor7 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_ctigain_sdcor6 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_ctigain_sdcor5 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_ctigain_sdcor4 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_ctigain_sdcor3 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_ctigain_sdcor2 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_ctigain_sdcor1 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_ctigain_sdcor0 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+#define SR7_CTIGAIN_SDCOR1 ((0x5109 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_ctigain_sdcor15 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_ctigain_sdcor14 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_ctigain_sdcor13 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_ctigain_sdcor12 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_ctigain_sdcor11 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_ctigain_sdcor10 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_ctigain_sdcor9 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_ctigain_sdcor8 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+#define SR7_LTIGAIN_SDCOR0 ((0x510a << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_ltigain_sdcor7 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_ltigain_sdcor6 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_ltigain_sdcor5 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_ltigain_sdcor4 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_ltigain_sdcor3 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_ltigain_sdcor2 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_ltigain_sdcor1 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_ltigain_sdcor0 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+#define SR7_LTIGAIN_SDCOR1 ((0x510b << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_ltigain_sdcor15 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_ltigain_sdcor14 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_ltigain_sdcor13 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_ltigain_sdcor12 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_ltigain_sdcor11 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_ltigain_sdcor10 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_ltigain_sdcor9 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_ltigain_sdcor8 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+#define SR7_HLTIBPF_TAP0 ((0x510c << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_hlti_bpf_tap153 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0
+//Bit 23:16, reg_sr7_hlti_bpf_tap152 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -34
+//Bit 15: 8, reg_sr7_hlti_bpf_tap151 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -1
+//Bit 7: 0, reg_sr7_hlti_bpf_tap150 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 120
+#define SR7_HLTIBPF_TAP1 ((0x510d << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_hlti_bpf_tap157 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 2
+//Bit 23:16, reg_sr7_hlti_bpf_tap156 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -7
+//Bit 15: 8, reg_sr7_hlti_bpf_tap155 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 1
+//Bit 7: 0, reg_sr7_hlti_bpf_tap154 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -21
+#define SR7_HCTIBPF_TAP0 ((0x510e << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_hcti_bpf_tap153 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0
+//Bit 23:16, reg_sr7_hcti_bpf_tap152 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -34
+//Bit 15: 8, reg_sr7_hcti_bpf_tap151 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -1
+//Bit 7: 0, reg_sr7_hcti_bpf_tap150 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 120
+#define SR7_HCTIBPF_TAP1 ((0x510f << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_hcti_bpf_tap157 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 2
+//Bit 23:16, reg_sr7_hcti_bpf_tap156 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -7
+//Bit 15: 8, reg_sr7_hcti_bpf_tap155 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 1
+//Bit 7: 0, reg_sr7_hcti_bpf_tap154 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -21
+#define SR7_PKLONGBPF_HTAP0 ((0x5110 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_bpf_hztap153 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -24
+//Bit 23:16, reg_sr7_pk_long_bpf_hztap152 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -19
+//Bit 15: 8, reg_sr7_pk_long_bpf_hztap151 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 31
+//Bit 7: 0, reg_sr7_pk_long_bpf_hztap150 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 66
+#define SR7_PKLONGBPF_HTAP1 ((0x5111 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_bpf_hztap157 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -6
+//Bit 23:16, reg_sr7_pk_long_bpf_hztap156 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -10
+//Bit 15: 8, reg_sr7_pk_long_bpf_hztap155 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -1
+//Bit 7: 0, reg_sr7_pk_long_bpf_hztap154 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -4
+#define SR7_PKLONGHPF_HTAP0 ((0x5112 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_hpf_hztap153 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 27
+//Bit 23:16, reg_sr7_pk_long_hpf_hztap152 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -15
+//Bit 15: 8, reg_sr7_pk_long_hpf_hztap151 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -32
+//Bit 7: 0, reg_sr7_pk_long_hpf_hztap150 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 58
+#define SR7_PKLONGHPF_HTAP1 ((0x5113 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_hpf_hztap157 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 8
+//Bit 23:16, reg_sr7_pk_long_hpf_hztap156 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -6
+//Bit 15: 8, reg_sr7_pk_long_hpf_hztap155 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -1
+//Bit 7: 0, reg_sr7_pk_long_hpf_hztap154 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -10
+#define SR7_VLTIBPF_TAP0 ((0x5114 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_vlti_bpf_tap093 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0
+//Bit 23:16, reg_sr7_vlti_bpf_tap092 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -41
+//Bit 15: 8, reg_sr7_vlti_bpf_tap091 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0
+//Bit 7: 0, reg_sr7_vlti_bpf_tap090 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 126
+#define SR7_VLTIBPF_TAP1 ((0x5115 << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_sr7_vlti_bpf_tap094 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -22
+#define SR7_VCTIBPF_TAP0 ((0x5116 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_vcti_bpf_tap093 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0
+//Bit 23:16, reg_sr7_vcti_bpf_tap092 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -41
+//Bit 15: 8, reg_sr7_vcti_bpf_tap091 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0
+//Bit 7: 0, reg_sr7_vcti_bpf_tap090 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 126
+#define SR7_VCTIBPF_TAP1 ((0x5117 << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_sr7_vcti_bpf_tap094 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -22
+#define SR7_PKLONGBPF_VTAP0 ((0x5118 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_bpf_vdtap093 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -32
+//Bit 23:16, reg_sr7_pk_long_bpf_vdtap092 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -28
+//Bit 15: 8, reg_sr7_pk_long_bpf_vdtap091 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 30
+//Bit 7: 0, reg_sr7_pk_long_bpf_vdtap090 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 68
+#define SR7_PKLONGBPF_VTAP1 ((0x5119 << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_sr7_pk_long_bpf_vdtap094 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -4
+#define SR7_PKLONGHPF_VTAP0 ((0x511a << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_hpf_vdtap093 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 30
+//Bit 23:16, reg_sr7_pk_long_hpf_vdtap092 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -28
+//Bit 15: 8, reg_sr7_pk_long_hpf_vdtap091 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -31
+//Bit 7: 0, reg_sr7_pk_long_hpf_vdtap090 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 68
+#define SR7_PKLONGHPF_VTAP1 ((0x511b << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_sr7_pk_long_hpf_vdtap094 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -5
+#define SR7_CIRBPLONG_ALP ((0x511c << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_cirbp_long_alpha3 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+//Bit 11: 8, reg_sr7_cirbp_long_alpha2 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+//Bit 7: 4, reg_sr7_cirbp_long_alpha1 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+//Bit 3: 0, reg_sr7_cirbp_long_alpha0 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+#define SR7_CIRHPLONG_ALP ((0x511d << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_cirhp_long_alpha3 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+//Bit 11: 8, reg_sr7_cirhp_long_alpha2 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+//Bit 7: 4, reg_sr7_cirhp_long_alpha1 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+//Bit 3: 0, reg_sr7_cirhp_long_alpha0 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+#define SR7_DRTBPLONG_ALP ((0x511e << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_drtbp_long_alpha7 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 27:24, reg_sr7_drtbp_long_alpha6 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 23:20, reg_sr7_drtbp_long_alpha5 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 19:16, reg_sr7_drtbp_long_alpha4 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 15:12, reg_sr7_drtbp_long_alpha3 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 11: 8, reg_sr7_drtbp_long_alpha2 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 7: 4, reg_sr7_drtbp_long_alpha1 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 3: 0, reg_sr7_drtbp_long_alpha0 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+#define SR7_DRTHPLONG_ALP ((0x511f << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_drthp_long_alpha7 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 27:24, reg_sr7_drthp_long_alpha6 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 23:20, reg_sr7_drthp_long_alpha5 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 19:16, reg_sr7_drthp_long_alpha4 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 15:12, reg_sr7_drthp_long_alpha3 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 11: 8, reg_sr7_drthp_long_alpha2 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 7: 4, reg_sr7_drthp_long_alpha1 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 3: 0, reg_sr7_drthp_long_alpha0 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+#define SR7_PKMINMAXCIR_BLD_LUT2D0 ((0x5120 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_cirbld_lut2d7 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0
+//Bit 27:24, reg_sr7_pk_mimaxerr2_cirbld_lut2d6 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0
+//Bit 23:20, reg_sr7_pk_mimaxerr2_cirbld_lut2d5 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 19:16, reg_sr7_pk_mimaxerr2_cirbld_lut2d4 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d3 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d2 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d1 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d0 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+#define SR7_PKMINMAXCIR_BLD_LUT2D1 ((0x5121 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_cirbld_lut2d15 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 27:24, reg_sr7_pk_mimaxerr2_cirbld_lut2d14 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0
+//Bit 23:20, reg_sr7_pk_mimaxerr2_cirbld_lut2d13 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 19:16, reg_sr7_pk_mimaxerr2_cirbld_lut2d12 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d11 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d10 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d9 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d8 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+#define SR7_PKMINMAXCIR_BLD_LUT2D2 ((0x5122 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_cirbld_lut2d23 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 27:24, reg_sr7_pk_mimaxerr2_cirbld_lut2d22 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 10
+//Bit 23:20, reg_sr7_pk_mimaxerr2_cirbld_lut2d21 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 19:16, reg_sr7_pk_mimaxerr2_cirbld_lut2d20 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d19 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d18 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d17 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d16 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12
+#define SR7_PKMINMAXCIR_BLD_LUT2D3 ((0x5123 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_cirbld_lut2d31 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 14
+//Bit 27:24, reg_sr7_pk_mimaxerr2_cirbld_lut2d30 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 23:20, reg_sr7_pk_mimaxerr2_cirbld_lut2d29 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 19:16, reg_sr7_pk_mimaxerr2_cirbld_lut2d28 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 8
+//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d27 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 10
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d26 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d25 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d24 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+#define SR7_PKMINMAXCIR_BLD_LUT2D4 ((0x5124 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d35 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d34 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d33 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d32 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12
+#define SR7_PKMINMAXLPF_BLD_LUT2D0 ((0x5125 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_lpfbld_lut2d7 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0
+//Bit 27:24, reg_sr7_pk_mimaxerr2_lpfbld_lut2d6 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0
+//Bit 23:20, reg_sr7_pk_mimaxerr2_lpfbld_lut2d5 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 19:16, reg_sr7_pk_mimaxerr2_lpfbld_lut2d4 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d3 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d2 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d1 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d0 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+#define SR7_PKMINMAXLPF_BLD_LUT2D1 ((0x5126 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_lpfbld_lut2d15 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 27:24, reg_sr7_pk_mimaxerr2_lpfbld_lut2d14 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0
+//Bit 23:20, reg_sr7_pk_mimaxerr2_lpfbld_lut2d13 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 19:16, reg_sr7_pk_mimaxerr2_lpfbld_lut2d12 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d11 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d10 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d9 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d8 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+#define SR7_PKMINMAXLPF_BLD_LUT2D2 ((0x5127 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_lpfbld_lut2d23 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 27:24, reg_sr7_pk_mimaxerr2_lpfbld_lut2d22 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 10
+//Bit 23:20, reg_sr7_pk_mimaxerr2_lpfbld_lut2d21 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 19:16, reg_sr7_pk_mimaxerr2_lpfbld_lut2d20 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d19 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d18 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d17 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d16 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12
+#define SR7_PKMINMAXLPF_BLD_LUT2D3 ((0x5128 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_lpfbld_lut2d31 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 14
+//Bit 27:24, reg_sr7_pk_mimaxerr2_lpfbld_lut2d30 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 23:20, reg_sr7_pk_mimaxerr2_lpfbld_lut2d29 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 19:16, reg_sr7_pk_mimaxerr2_lpfbld_lut2d28 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 8
+//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d27 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 10
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d26 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d25 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d24 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+#define SR7_PKMINMAXLPF_BLD_LUT2D4 ((0x5129 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d35 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d34 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d33 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d32 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12
+#define SR7_PKDRT_BLD_EN ((0x512a << 2) + 0xff000000)
+//Bit 31: 1, reserved
+//Bit 0, reg_sr7_pkdrtbld_beta_en : enable of direction ambiguity protection for drt and cir blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 0
+#define SR7_DRTDIF_TH ((0x512b << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_sr7_drtdif_min2sad_th1 : for min2_sad threshold for ambiguilty ignoring, if (min_sad<min2_sad/2 && min2_sad>thrd) drt_dif=1;. unsigned , default = 128
+//Bit 7: 0, reg_sr7_drtdif_min2sad_th0 : for min2_sad threshold for ambiguilty ignoring, if (min_sad<min2_sad/2 && min2_sad>thrd) drt_dif=1;. unsigned , default = 128
+#define SR7_TIBLD_PRT ((0x512c << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13, reg_sr7_hlti_dcbld_beta_en : enable of denoise protection for dc org and denoise blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 1
+//Bit 12, reg_sr7_vlti_dcbld_beta_en : enable of denoise protection for dc org and denoise blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 1
+//Bit 11: 8, reg_sr7_xcti_dcbld_beta1 : beta for denoise and org dc blend base on the x=cal_drt_dif4(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 0
+//Bit 7: 4, reg_sr7_xcti_dcbld_beta0 : beta for denoise and org dc blend base on the x=cal_drt_dif4(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 15
+//Bit 3, reg_sr7_hcti_dcbld_beta_en : enable of denoise protection for dc org and denoise blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 1
+//Bit 2, reg_sr7_vcti_dcbld_beta_en : enable of denoise protection for dc org and denoise blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 1
+//Bit 1, reg_sr7_hcti_dcbld_use_ybeta : enable to use beta from hlti, 0, use c-beta, 1, use y-beta. unsigned , default = 0
+//Bit 0, reg_sr7_vcti_dcbld_use_ybeta : enable to use beta from vlti, 0, use c-beta, 1, use y-beta. unsigned , default = 0
+#define SR7_HTI_OPT_FORCE ((0x512d << 2) + 0xff000000)
+//Bit 31: 6, reserved
+//Bit 5, reg_sr7_diag_force_hti1 : force hti for diagonal edges luma/chroma, 0: diagonal use vti, 1: diagonal use hti, default=1. unsigned , default = 1
+//Bit 4, reg_sr7_diag_force_hti0 : force hti for diagonal edges luma/chroma, 0: diagonal use vti, 1: diagonal use hti, default=1. unsigned , default = 1
+//Bit 3, reg_sr7_horz_force_vti1 : force vti for horizontal edges luma/chroma, 0: bias hti, 1: horizontal edge force 100% vti, default=1. unsigned , default = 1
+//Bit 2, reg_sr7_horz_force_vti0 : force vti for horizontal edges luma/chroma, 0: bias hti, 1: horizontal edge force 100% vti, default=1. unsigned , default = 1
+//Bit 1, reg_sr7_alph_force_hvsad1 : alpha = minsad*64/maxsad, force minsad=sad_h, maxsad=sad_v for alpha calculation, [0]for luma, [1] for chroma. if sad_h>sad_v alpha will be large, default=1. unsigned , default = 1
+//Bit 0, reg_sr7_alph_force_hvsad0 : alpha = minsad*64/maxsad, force minsad=sad_h, maxsad=sad_v for alpha calculation, [0]for luma, [1] for chroma. if sad_h>sad_v alpha will be large, default=1. unsigned , default = 1
+#define SR7_HVTI_FINALGAIN ((0x512e << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, reg_sr7_hvti_finalgain1 : final gain for HVTI boost, for easier level tunning for application, normalized to 256 as 1.0 default = 256. unsigned , default = 256
+//Bit 15:12, reserved
+//Bit 11: 0, reg_sr7_hvti_finalgain0 : final gain for HVTI boost, for easier level tunning for application, normalized to 256 as 1.0 default = 256. unsigned , default = 256
+#define SR7_TIOS_SDRATIO ((0x512f << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_sr7_hti_osmargin_sdratio1 : ratio for HTI OS margin adaptive to sd. osmargin= (sd*ratio)>>6; default=3. unsigned , default = 3
+//Bit 23:22, reserved
+//Bit 21:16, reg_sr7_hti_osmargin_sdratio0 : ratio for HTI OS margin adaptive to sd. osmargin= (sd*ratio)>>6; default=3. unsigned , default = 3
+//Bit 15:14, reserved
+//Bit 13: 8, reg_sr7_vti_osmargin_sdratio1 : ratio for VTI OS margin adaptive to sd. osmargin= (sd*ratio)>>6; default=3. unsigned , default = 3
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_sr7_vti_osmargin_sdratio0 : ratio for VTI OS margin adaptive to sd. osmargin= (sd*ratio)>>6; default=3. unsigned , default = 3
+#define SR7_XTI_SDFDEN ((0x5130 << 2) + 0xff000000)
+//Bit 31: 2, reserved
+//Bit 1, reg_sr7_xtigain_sdfd_en1 : adaptive gamma for cti boost gain enable.[0]for luma, [1] for chroma. 0: not enable, 1:enable, default = 1. unsigned , default = 1
+//Bit 0, reg_sr7_xtigain_sdfd_en0 : adaptive gamma for cti boost gain enable.[0]for luma, [1] for chroma. 0: not enable, 1:enable, default = 1. unsigned , default = 1
+#define SR7_FDSD_PARAM ((0x5131 << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25, reg_fdsd_vlpf_en : use vertical [1 2 1] lpf filter for the fd and sd derivativecalculations. unsigned , default = 1
+//Bit 24, reg_fdsd_hlpf_en : use horizontal [1 2 1] lpf filter for the fd and sd derivativecalculations. unsigned , default = 1
+//Bit 23:20, reg_sd_coring_th1 : coring to SD'= MAX(SD - FD*ratio - coring,0); default = 0. unsigned , default = 0
+//Bit 19:16, reg_sd_coring_th0 : coring to SD'= MAX(SD - FD*ratio - coring,0); default = 0. unsigned , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_sd_coring_ratio2fd1 : ratio to FD for adaptive coring to SD'= MAX(SD - FD*ratio - coring,0); normalized 64 as 1.0 default = 4. unsigned , default = 4
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_sd_coring_ratio2fd0 : ratio to FD for adaptive coring to SD'= MAX(SD - FD*ratio - coring,0); normalized 64 as 1.0 default = 4. unsigned , default = 4
+#define SR7_TI_BPF_EN ((0x5132 << 2) + 0xff000000)
+//Bit 31: 4, reserved
+//Bit 3, reg_sr7_hlti_bpf_en : enable of tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. unsigned , default = 1
+//Bit 2, reg_sr7_hcti_bpf_en : enable of tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. unsigned , default = 1
+//Bit 1, reg_sr7_vlti_bpf_en : enable of tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0, mainly for 2x2 UP case. unsigned , default = 1
+//Bit 0, reg_sr7_vcti_bpf_en : enable of tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0, mainly for 2x2 UP case. unsigned , default = 1
+#define SR7_PKLONG_PF_EN ((0x5133 << 2) + 0xff000000)
+//Bit 31: 2, reserved
+//Bit 1, reg_sr7_pk_long_bpf_en : enable of long BPF for peaking only store half of the filter normalized to 258 as 1.0. unsigned , default = 1
+//Bit 0, reg_sr7_pk_long_hpf_en : enable of long HPF for peaking only store half of the filter normalized to 258 as 1.0. unsigned , default = 1
+#define SR7_PKLONG_PF_GAIN ((0x5134 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_bpf_hzgain : gain to long horizontal BPF for peaking, normalized to 64 as 1.0. unsigned , default = 64
+//Bit 23:16, reg_sr7_pk_long_bpf_vdgain : gain to long vertical and diagonal BPF for peaking, normalized to 64 as 1.0. unsigned , default = 64
+//Bit 15: 8, reg_sr7_pk_long_hpf_hzgain : gain to long horizontal HPF for peaking, normalized to 64 as 1.0. unsigned , default = 64
+//Bit 7: 0, reg_sr7_pk_long_hpf_vdgain : gain to long vertical and diagonal HPF for peaking, normalized to 64 as 1.0. unsigned , default = 64
+#define SR7_PKMINMAX_BLD ((0x5135 << 2) + 0xff000000)
+//Bit 31: 4, reserved
+//Bit 3, reg_sr7_pk_mimaxerr2_cirbld_on_bp : enable to use adaptive blender of drtBP vs cirBP alpha2, the larger of cell, the more cirPK results, 0: alp2=lut2d(minerr, maxerr),1:alp2=min_err/maxerr,default = 1. unsigned , default = 1
+//Bit 2, reg_sr7_pk_mimaxerr2_cirbld_on_hp : enable to use adaptive blender of drtHP vs cirHP alpha2, the larger of cell, the more cirPK results, 0: alp2=lut2d(minerr, maxerr),1:alp2=min_err/maxerr,default = 1. unsigned , default = 1
+//Bit 1, reg_sr7_pk_mimaxerr2_lpfbld_on_bp : enable to use adaptive blender of BP result lpf along edge based on the mimaxsad relationship, default = 1. unsigned , default = 1
+//Bit 0, reg_sr7_pk_mimaxerr2_lpfbld_on_hp : enable to use adaptive blender of HP result lpf along edge based on the mimaxsad relationship, default = 1. unsigned , default = 1
+#define SR7_TI_CONMAXERR_GAIN ((0x5136 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_hti_conmaxerr_gain1 : con=max(con, maxerr) for the horizontal transition calculation, gain=0, same as s6 and prev, [0] for y and [1] for uv. unsigned , default = 8
+//Bit 11: 8, reg_sr7_hti_conmaxerr_gain0 : con=max(con, maxerr) for the horizontal transition calculation, gain=0, same as s6 and prev, [0] for y and [1] for uv. unsigned , default = 8
+//Bit 7: 4, reg_sr7_vti_conmaxerr_gain1 : con=max(con, maxerr) for the vertical transition calculation, gain=0, same as s6 and prev, [0] for y and [1] for uv. unsigned , default = 8
+//Bit 3: 0, reg_sr7_vti_conmaxerr_gain0 : con=max(con, maxerr) for the vertical transition calculation, gain=0, same as s6 and prev, [0] for y and [1] for uv. unsigned , default = 8
+#define SR7_CC_PK_ADJ ((0x5137 << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24, reg_sr7_cc_enable : color compensation enable, 0: no CC, 1: with CC, default = 1. unsigned , default = 1
+//Bit 23:22, reserved
+//Bit 21:20, reg_sr7_cc_yinp_sel : color compensation input luma selection, 0: org_y; 1: gau_y ; 2:gauadp_y; 3:edgeadp_y (same as dnlp input sel), default= 0. unsigned , default = 0
+//Bit 19:18, reg_sr7_cc_ydlt_sel : color compensation output luma selection, 0: peaking+lti output; 1: dnlp output; 2/3: peaking+lti+dnlp, default = 2. unsigned , default = 2
+//Bit 17:16, reg_sr7_cc_sat_norm : normalization of lut cell to saturation. 0: norm to 8 as 1.0, sat[0:23/8]; 1: norm to 16 as 1.0, sat[1/16:31/16]; 2: norm to 32 as 1.0, sat[17/32:47/32]; 3:norm to 64 as 1.0, sat[49/64:79/64]. unsigned , default = 1
+//Bit 15: 8, reg_sr7_cc_ydlt_pscl : prescale to the y-delta (if >0) before feeding to y-lumadlt, normalized 64 as 1.0. default = 64.. unsigned , default = 64
+//Bit 7: 0, reg_sr7_cc_ydlt_nscl : prescale to the y-delta (if <0) before feeding to y-lumadlt, normalized 64 as 1.0. default = 64.. unsigned , default = 64
+#define SR7_CC_LUT0 ((0x5138 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_cc_lut003 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=0, dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 27:24, reg_sr7_cc_lut002 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=0, dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 23:20, reg_sr7_cc_lut001 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=0, dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 19:16, reg_sr7_cc_lut000 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=0, dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 15:12, reg_sr7_cc_lut103 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=1/8 dft={1, 2, 4, 8}. unsigned , default = 8
+//Bit 11: 8, reg_sr7_cc_lut102 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=1/8 dft={1, 2, 4, 8}. unsigned , default = 4
+//Bit 7: 4, reg_sr7_cc_lut101 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=1/8 dft={1, 2, 4, 8}. unsigned , default = 2
+//Bit 3: 0, reg_sr7_cc_lut100 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=1/8 dft={1, 2, 4, 8}. unsigned , default = 1
+#define SR7_CC_LUT1 ((0x5139 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:24, reg_sr7_cc_lut202 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=2/8 dft={4, 8,12}. unsigned , default = 12
+//Bit 23:20, reg_sr7_cc_lut201 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=2/8 dft={4, 8,12}. unsigned , default = 8
+//Bit 19:16, reg_sr7_cc_lut200 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=2/8 dft={4, 8,12}. unsigned , default = 4
+//Bit 15:12, reserved
+//Bit 11: 8, reg_sr7_cc_lut302 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=3/8 dft={5,10,15}. unsigned , default = 15
+//Bit 7: 4, reg_sr7_cc_lut301 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=3/8 dft={5,10,15}. unsigned , default = 10
+//Bit 3: 0, reg_sr7_cc_lut300 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=3/8 dft={5,10,15}. unsigned , default = 5
+#define SR7_CC_LUT2 ((0x513a << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:20, reg_sr7_cc_lut401 : valid for y-lumadlt= 1/4, 1/2, ; of x-lumainput=4/8 dft={8,15}. unsigned , default = 15
+//Bit 19:16, reg_sr7_cc_lut400 : valid for y-lumadlt= 1/4, 1/2, ; of x-lumainput=4/8 dft={8,15}. unsigned , default = 8
+//Bit 15:12, reg_sr7_cc_lut501 : valid for y-lumadlt= 1/4, 1/2, ; of x-lumainput=5/8 dft={6,13}. unsigned , default = 13
+//Bit 11: 8, reg_sr7_cc_lut500 : valid for y-lumadlt= 1/4, 1/2, ; of x-lumainput=5/8 dft={6,13}. unsigned , default = 6
+//Bit 7: 4, reg_sr7_cc_lut600 : valid for y-lumadlt= 1/4, ; of x-lumainput=6/8 dft={5}. unsigned , default = 5
+//Bit 3: 0, reg_sr7_cc_lut700 : valid for y-lumadlt= 1/4, ; of x-lumainput=7/8 dft={4}. unsigned , default = 4
+#define SR7_CC_LUT3 ((0x513b << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:20, reg_sr7_cc_lut710 : valid for y-lumadlt= -1/4, ; of x-lumainput=1/8 dft={4}. unsigned , default = 4
+//Bit 19:16, reg_sr7_cc_lut610 : valid for y-lumadlt= -1/4, ; of x-lumainput=2/8 dft={5}. unsigned , default = 5
+//Bit 15:12, reg_sr7_cc_lut511 : valid for y-lumadlt= -1/4, -1/2, ; of x-lumainput=3/8 dft={6,13}. unsigned , default = 13
+//Bit 11: 8, reg_sr7_cc_lut510 : valid for y-lumadlt= -1/4, -1/2, ; of x-lumainput=3/8 dft={6,13}. unsigned , default = 6
+//Bit 7: 4, reg_sr7_cc_lut411 : valid for y-lumadlt= -1/4, -1/2, ; of x-lumainput=4/8 dft={8,15}. unsigned , default = 15
+//Bit 3: 0, reg_sr7_cc_lut410 : valid for y-lumadlt= -1/4, -1/2, ; of x-lumainput=4/8 dft={8,15}. unsigned , default = 8
+#define SR7_CC_LUT4 ((0x513c << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:20, reg_sr7_cc_lut312 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=5/8 dft={5,10,15}. unsigned , default = 15
+//Bit 19:16, reg_sr7_cc_lut311 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=5/8 dft={5,10,15}. unsigned , default = 10
+//Bit 15:12, reg_sr7_cc_lut310 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=5/8 dft={5,10,15}. unsigned , default = 5
+//Bit 11: 8, reg_sr7_cc_lut212 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=6/8 dft={4, 8,12}. unsigned , default = 12
+//Bit 7: 4, reg_sr7_cc_lut211 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=6/8 dft={4, 8,12}. unsigned , default = 8
+//Bit 3: 0, reg_sr7_cc_lut210 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=6/8 dft={4, 8,12}. unsigned , default = 4
+#define SR7_CC_LUT5 ((0x513d << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_cc_lut113 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=7/8 dft={1, 2, 4, 8}. unsigned , default = 8
+//Bit 27:24, reg_sr7_cc_lut112 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=7/8 dft={1, 2, 4, 8}. unsigned , default = 4
+//Bit 23:20, reg_sr7_cc_lut111 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=7/8 dft={1, 2, 4, 8}. unsigned , default = 2
+//Bit 19:16, reg_sr7_cc_lut110 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=7/8 dft={1, 2, 4, 8}. unsigned , default = 1
+//Bit 15:12, reg_sr7_cc_lut013 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=8/8 dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 11: 8, reg_sr7_cc_lut012 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=8/8 dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 7: 4, reg_sr7_cc_lut011 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=8/8 dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 3: 0, reg_sr7_cc_lut010 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=8/8 dft={0, 0, 0, 0}. unsigned , default = 0
+#define SR7_GRAPHIC_CTRL ((0x513e << 2) + 0xff000000)
+//Bit 31:11, reserved
+//Bit 10, reg_sr7_grph_en : enable graphic statistic . unsigned , default = 1
+//Bit 9, reg_sr7_grph_hflt : horizontal filter, 0: [0 1 -1], 1: [-1 2 -1]. unsigned , default = 1
+//Bit 8, reg_sr7_grph_vflt : vertical filter, 0: [0 1 -1], 1: [-1 2 -1]. unsigned , default = 1
+//Bit 7: 0, reg_sr7_grph_dif_cor : coring for dif while count for graphic. unsigned , default = 0
+#define SR7_GRAPHIC_THD_GAIN ((0x513f << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_grph_flt_thd : flat threshold for dif while count for graphic. unsigned , default = 2
+//Bit 23:16, reg_sr7_grph_dtl_thd : detail threshold for dif while count for graphic. unsigned , default = 40
+//Bit 15: 8, reg_sr7_grph_hgain : horizontal gain for fast squart of hp. unsigned , default = 32
+//Bit 7: 0, reg_sr7_grph_vgain : vertical gain for fast squart of hp. unsigned , default = 32
+#define SR7_RO_GRAPHIC_FLT_CNT ((0x5140 << 2) + 0xff000000)
+//Bit 31: 0, ro_sr7_grph_flt_cnt : flat count numbers for graphic. unsigned , default = 0
+#define SR7_RO_GRAPHIC_DTL_CNT ((0x5141 << 2) + 0xff000000)
+//Bit 31: 0, ro_sr7_grph_dtl_cnt : detail count numbers for graphic. unsigned , default = 0
+#define SR7_CLR_PRT_PARAM ((0x5142 << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:16, reg_sr7_clr_prct_inpsel : input UV selection for color protection, 0: org; 1: NRout; 2: CTIout; 3: (NR+TIout)/2. unsigned , default = 3
+//Bit 15: 8, reg_sr7_clr_prct_dnlp_gain : gain to de-boost of dnlp_dlt base on color region, norm to 64 as 1.0. set to 0 as disable. unsigned , default = 64
+//Bit 7: 0, reg_sr7_clr_prct_peak_gain : gain to de-boost of peak_dlt base on color region, norm to 64 as 1.0, set to 0 as disable. unsigned , default = 64
+#define SR7_CLR_PRT_LC_GAIN ((0x5143 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_sr7_clr_prct_lc_gain2 : gain to de-boost of lc_dlt (y/u/v) base on color region, norm to 64 as 1.0, set to 0 as disable. unsigned , default = 64
+//Bit 15: 8, reg_sr7_clr_prct_lc_gain1 : gain to de-boost of lc_dlt (y/u/v) base on color region, norm to 64 as 1.0, set to 0 as disable. unsigned , default = 64
+//Bit 7: 0, reg_sr7_clr_prct_lc_gain0 : gain to de-boost of lc_dlt (y/u/v) base on color region, norm to 64 as 1.0, set to 0 as disable. unsigned , default = 64
+#define SR7_CLR_PRT_LUT0 ((0x5144 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut7 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut6 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut5 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut4 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut3 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut2 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut1 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut0 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT1 ((0x5145 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut15 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut14 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut13 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut12 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut11 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut10 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut9 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut8 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT2 ((0x5146 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut23 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut22 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut21 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut20 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut19 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut18 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut17 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut16 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT3 ((0x5147 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut31 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut30 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut29 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut28 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut27 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut26 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut25 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut24 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT4 ((0x5148 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut39 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut38 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut37 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut36 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut35 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut34 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut33 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut32 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT5 ((0x5149 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut47 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut46 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut45 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut44 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut43 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut42 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut41 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut40 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT6 ((0x514a << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut55 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut54 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut53 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut52 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut51 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut50 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut49 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut48 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT7 ((0x514b << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut63 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut62 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut61 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut60 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut59 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut58 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut57 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut56 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT8 ((0x514c << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut71 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut70 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut69 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut68 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut67 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut66 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut65 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut64 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT9 ((0x514d << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut79 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut78 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut77 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut76 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut75 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut74 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut73 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut72 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT10 ((0x514e << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut87 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut86 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut85 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut84 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut83 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut82 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut81 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut80 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT11 ((0x514f << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut95 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut94 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut93 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut92 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut91 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut90 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut89 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut88 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT12 ((0x5150 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut103 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut102 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut101 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut100 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut99 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut98 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut97 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut96 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT13 ((0x5151 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut111 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut110 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut109 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut108 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut107 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut106 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut105 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut104 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT14 ((0x5152 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut119 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut118 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut117 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut116 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut115 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut114 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut113 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut112 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT15 ((0x5153 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut127 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut126 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut125 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut124 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut123 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut122 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut121 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut120 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT16 ((0x5154 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut135 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut134 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut133 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut132 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut131 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut130 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut129 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut128 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT17 ((0x5155 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut143 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut142 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut141 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut140 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut139 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut138 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut137 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut136 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT18 ((0x5156 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut151 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 27:24, reg_sr7_clr_prct_lut150 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 23:20, reg_sr7_clr_prct_lut149 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 19:16, reg_sr7_clr_prct_lut148 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut147 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut146 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut145 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut144 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT19 ((0x5157 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut159 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut158 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut157 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut156 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut155 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut154 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut153 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 3: 0, reg_sr7_clr_prct_lut152 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+#define SR7_CLR_PRT_LUT20 ((0x5158 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut167 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 27:24, reg_sr7_clr_prct_lut166 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 23:20, reg_sr7_clr_prct_lut165 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 19:16, reg_sr7_clr_prct_lut164 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut163 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut162 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut161 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut160 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT21 ((0x5159 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut175 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut174 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut173 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut172 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut171 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut170 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut169 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 3: 0, reg_sr7_clr_prct_lut168 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+#define SR7_CLR_PRT_LUT22 ((0x515a << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut183 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 27:24, reg_sr7_clr_prct_lut182 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 23:20, reg_sr7_clr_prct_lut181 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 19:16, reg_sr7_clr_prct_lut180 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut179 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut178 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut177 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut176 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT23 ((0x515b << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut191 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut190 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut189 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut188 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut187 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut186 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut185 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 3: 0, reg_sr7_clr_prct_lut184 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+#define SR7_CLR_PRT_LUT24 ((0x515c << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut199 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 27:24, reg_sr7_clr_prct_lut198 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 23:20, reg_sr7_clr_prct_lut197 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 19:16, reg_sr7_clr_prct_lut196 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut195 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut194 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut193 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut192 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT25 ((0x515d << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut207 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut206 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut205 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut204 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut203 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut202 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut201 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 3: 0, reg_sr7_clr_prct_lut200 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+#define SR7_CLR_PRT_LUT26 ((0x515e << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut215 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 27:24, reg_sr7_clr_prct_lut214 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 23:20, reg_sr7_clr_prct_lut213 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 19:16, reg_sr7_clr_prct_lut212 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut211 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut210 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut209 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut208 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT27 ((0x515f << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut223 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut222 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut221 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut220 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut219 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut218 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut217 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 3: 0, reg_sr7_clr_prct_lut216 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+#define SR7_CLR_PRT_LUT28 ((0x5160 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut231 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 27:24, reg_sr7_clr_prct_lut230 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 23:20, reg_sr7_clr_prct_lut229 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 19:16, reg_sr7_clr_prct_lut228 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut227 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut226 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut225 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut224 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT29 ((0x5161 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut239 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut238 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut237 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut236 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut235 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut234 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut233 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 3: 0, reg_sr7_clr_prct_lut232 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+#define SR7_CLR_PRT_LUT30 ((0x5162 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut247 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut246 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut245 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut244 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut243 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut242 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut241 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut240 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT31 ((0x5163 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut255 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut254 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut253 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut252 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut251 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut250 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut249 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut248 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: sharp_regs2.h
+//
+
+#define SRSHARP0_SR7_DRTLPF_EN (SRSHARP0_OFFSET + SR7_DRTLPF_EN )//
+#define SRSHARP0_SR7_DRTLPF_BETA (SRSHARP0_OFFSET + SR7_DRTLPF_BETA )//
+#define SRSHARP0_SR7_PKBLD_BETA (SRSHARP0_OFFSET + SR7_PKBLD_BETA )//
+#define SRSHARP0_SR7_XLTIBLD_BETA (SRSHARP0_OFFSET + SR7_XLTIBLD_BETA )//
+#define SRSHARP0_SR7_DRTLPF_EDGE0 (SRSHARP0_OFFSET + SR7_DRTLPF_EDGE0 )//
+#define SRSHARP0_SR7_DRTLPF_EDGE1 (SRSHARP0_OFFSET + SR7_DRTLPF_EDGE1 )//
+#define SRSHARP0_SR7_DRTLPF_SDCOR0 (SRSHARP0_OFFSET + SR7_DRTLPF_SDCOR0 )//
+#define SRSHARP0_SR7_DRTLPF_SDCOR1 (SRSHARP0_OFFSET + SR7_DRTLPF_SDCOR1 )//
+#define SRSHARP0_SR7_CTIGAIN_SDCOR0 (SRSHARP0_OFFSET + SR7_CTIGAIN_SDCOR0 )//
+#define SRSHARP0_SR7_CTIGAIN_SDCOR1 (SRSHARP0_OFFSET + SR7_CTIGAIN_SDCOR1 )//
+#define SRSHARP0_SR7_LTIGAIN_SDCOR0 (SRSHARP0_OFFSET + SR7_LTIGAIN_SDCOR0 )//
+#define SRSHARP0_SR7_LTIGAIN_SDCOR1 (SRSHARP0_OFFSET + SR7_LTIGAIN_SDCOR1 )//
+#define SRSHARP0_SR7_HLTIBPF_TAP0 (SRSHARP0_OFFSET + SR7_HLTIBPF_TAP0 )//
+#define SRSHARP0_SR7_HLTIBPF_TAP1 (SRSHARP0_OFFSET + SR7_HLTIBPF_TAP1 )//
+#define SRSHARP0_SR7_HCTIBPF_TAP0 (SRSHARP0_OFFSET + SR7_HCTIBPF_TAP0 )//
+#define SRSHARP0_SR7_HCTIBPF_TAP1 (SRSHARP0_OFFSET + SR7_HCTIBPF_TAP1 )//
+#define SRSHARP0_SR7_PKLONGBPF_HTAP0 (SRSHARP0_OFFSET + SR7_PKLONGBPF_HTAP0 ) //
+#define SRSHARP0_SR7_PKLONGBPF_HTAP1 (SRSHARP0_OFFSET + SR7_PKLONGBPF_HTAP1 ) //
+#define SRSHARP0_SR7_PKLONGHPF_HTAP0 (SRSHARP0_OFFSET + SR7_PKLONGHPF_HTAP0 ) //
+#define SRSHARP0_SR7_PKLONGHPF_HTAP1 (SRSHARP0_OFFSET + SR7_PKLONGHPF_HTAP1 ) //
+#define SRSHARP0_SR7_VLTIBPF_TAP0 (SRSHARP0_OFFSET + SR7_VLTIBPF_TAP0 ) //
+#define SRSHARP0_SR7_VLTIBPF_TAP1 (SRSHARP0_OFFSET + SR7_VLTIBPF_TAP1 ) //
+#define SRSHARP0_SR7_VCTIBPF_TAP0 (SRSHARP0_OFFSET + SR7_VCTIBPF_TAP0 ) //
+#define SRSHARP0_SR7_VCTIBPF_TAP1 (SRSHARP0_OFFSET + SR7_VCTIBPF_TAP1 ) //
+#define SRSHARP0_SR7_PKLONGBPF_VTAP0 (SRSHARP0_OFFSET + SR7_PKLONGBPF_VTAP0 ) //
+#define SRSHARP0_SR7_PKLONGBPF_VTAP1 (SRSHARP0_OFFSET + SR7_PKLONGBPF_VTAP1 ) //
+#define SRSHARP0_SR7_PKLONGHPF_VTAP0 (SRSHARP0_OFFSET + SR7_PKLONGHPF_VTAP0 ) //
+#define SRSHARP0_SR7_PKLONGHPF_VTAP1 (SRSHARP0_OFFSET + SR7_PKLONGHPF_VTAP1 ) //
+#define SRSHARP0_SR7_CIRBPLONG_ALP (SRSHARP0_OFFSET + SR7_CIRBPLONG_ALP ) //
+#define SRSHARP0_SR7_CIRHPLONG_ALP (SRSHARP0_OFFSET + SR7_CIRHPLONG_ALP ) //
+#define SRSHARP0_SR7_DRTBPLONG_ALP (SRSHARP0_OFFSET + SR7_DRTBPLONG_ALP ) //
+#define SRSHARP0_SR7_DRTHPLONG_ALP (SRSHARP0_OFFSET + SR7_DRTHPLONG_ALP ) //
+#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D0 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D0) //
+#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D1 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D1) //
+#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D2 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D2) //
+#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D3 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D3) //
+#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D4 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D4) //
+#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D0 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D0) //
+#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D1 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D1) //
+#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D2 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D2) //
+#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D3 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D3) //
+#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D4 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D4) //
+#define SRSHARP0_SR7_PKDRT_BLD_EN (SRSHARP0_OFFSET + SR7_PKDRT_BLD_EN ) //
+#define SRSHARP0_SR7_DRTDIF_TH (SRSHARP0_OFFSET + SR7_DRTDIF_TH ) //
+#define SRSHARP0_SR7_TIBLD_PRT (SRSHARP0_OFFSET + SR7_TIBLD_PRT ) //
+#define SRSHARP0_SR7_HTI_OPT_FORCE (SRSHARP0_OFFSET + SR7_HTI_OPT_FORCE ) //
+#define SRSHARP0_SR7_HVTI_FINALGAIN (SRSHARP0_OFFSET + SR7_HVTI_FINALGAIN ) //
+#define SRSHARP0_SR7_TIOS_SDRATIO (SRSHARP0_OFFSET + SR7_TIOS_SDRATIO ) //
+#define SRSHARP0_SR7_XTI_SDFDEN (SRSHARP0_OFFSET + SR7_XTI_SDFDEN ) //
+#define SRSHARP0_SR7_FDSD_PARAM (SRSHARP0_OFFSET + SR7_FDSD_PARAM ) //
+#define SRSHARP0_SR7_TI_BPF_EN (SRSHARP0_OFFSET + SR7_TI_BPF_EN ) //
+#define SRSHARP0_SR7_PKLONG_PF_EN (SRSHARP0_OFFSET + SR7_PKLONG_PF_EN ) //
+#define SRSHARP0_SR7_PKLONG_PF_GAIN (SRSHARP0_OFFSET + SR7_PKLONG_PF_GAIN ) //
+#define SRSHARP0_SR7_PKMINMAX_BLD (SRSHARP0_OFFSET + SR7_PKMINMAX_BLD ) //
+#define SRSHARP0_SR7_TI_CONMAXERR_GAIN (SRSHARP0_OFFSET + SR7_TI_CONMAXERR_GAIN ) //
+#define SRSHARP0_SR7_CC_PK_ADJ (SRSHARP0_OFFSET + SR7_CC_PK_ADJ ) //
+#define SRSHARP0_SR7_CC_LUT0 (SRSHARP0_OFFSET + SR7_CC_LUT0 ) //
+#define SRSHARP0_SR7_CC_LUT1 (SRSHARP0_OFFSET + SR7_CC_LUT1 ) //
+#define SRSHARP0_SR7_CC_LUT2 (SRSHARP0_OFFSET + SR7_CC_LUT2 ) //
+#define SRSHARP0_SR7_CC_LUT3 (SRSHARP0_OFFSET + SR7_CC_LUT3 ) //
+#define SRSHARP0_SR7_CC_LUT4 (SRSHARP0_OFFSET + SR7_CC_LUT4 ) //
+#define SRSHARP0_SR7_CC_LUT5 (SRSHARP0_OFFSET + SR7_CC_LUT5 ) //
+#define SRSHARP0_SR7_GRAPHIC_CTRL (SRSHARP0_OFFSET + SR7_GRAPHIC_CTRL ) //
+#define SRSHARP0_SR7_GRAPHIC_THD_GAIN (SRSHARP0_OFFSET + SR7_GRAPHIC_THD_GAIN ) //
+#define SRSHARP0_SR7_RO_GRAPHIC_FLT_CNT (SRSHARP0_OFFSET + SR7_RO_GRAPHIC_FLT_CNT ) //
+#define SRSHARP0_SR7_RO_GRAPHIC_DTL_CNT (SRSHARP0_OFFSET + SR7_RO_GRAPHIC_DTL_CNT ) //
+#define SRSHARP0_SR7_CLR_PRT_PARAM (SRSHARP0_OFFSET + SR7_CLR_PRT_PARAM ) //
+#define SRSHARP0_SR7_CLR_PRT_LC_GAIN (SRSHARP0_OFFSET + SR7_CLR_PRT_LC_GAIN ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT0 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT0 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT1 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT1 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT2 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT2 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT3 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT3 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT4 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT4 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT5 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT5 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT6 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT6 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT7 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT7 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT8 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT8 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT9 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT9 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT10 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT10 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT11 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT11 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT12 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT12 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT13 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT13 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT14 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT14 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT15 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT15 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT16 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT16 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT17 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT17 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT18 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT18 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT19 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT19 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT20 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT20 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT21 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT21 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT22 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT22 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT23 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT23 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT24 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT24 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT25 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT25 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT26 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT26 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT27 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT27 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT28 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT28 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT29 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT29 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT30 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT30 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT31 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT31 ) //
+
+
+//// srsharp1 reg define
+#define SRSHARP1_SR7_DRTLPF_EN (SRSHARP1_OFFSET + SR7_DRTLPF_EN )//
+#define SRSHARP1_SR7_DRTLPF_BETA (SRSHARP1_OFFSET + SR7_DRTLPF_BETA )//
+#define SRSHARP1_SR7_PKBLD_BETA (SRSHARP1_OFFSET + SR7_PKBLD_BETA )//
+#define SRSHARP1_SR7_XLTIBLD_BETA (SRSHARP1_OFFSET + SR7_XLTIBLD_BETA )//
+#define SRSHARP1_SR7_DRTLPF_EDGE0 (SRSHARP1_OFFSET + SR7_DRTLPF_EDGE0 )//
+#define SRSHARP1_SR7_DRTLPF_EDGE1 (SRSHARP1_OFFSET + SR7_DRTLPF_EDGE1 )//
+#define SRSHARP1_SR7_DRTLPF_SDCOR0 (SRSHARP1_OFFSET + SR7_DRTLPF_SDCOR0 )//
+#define SRSHARP1_SR7_DRTLPF_SDCOR1 (SRSHARP1_OFFSET + SR7_DRTLPF_SDCOR1 )//
+#define SRSHARP1_SR7_CTIGAIN_SDCOR0 (SRSHARP1_OFFSET + SR7_CTIGAIN_SDCOR0 )//
+#define SRSHARP1_SR7_CTIGAIN_SDCOR1 (SRSHARP1_OFFSET + SR7_CTIGAIN_SDCOR1 )//
+#define SRSHARP1_SR7_LTIGAIN_SDCOR0 (SRSHARP1_OFFSET + SR7_LTIGAIN_SDCOR0 )//
+#define SRSHARP1_SR7_LTIGAIN_SDCOR1 (SRSHARP1_OFFSET + SR7_LTIGAIN_SDCOR1 )//
+#define SRSHARP1_SR7_HLTIBPF_TAP0 (SRSHARP1_OFFSET + SR7_HLTIBPF_TAP0 )//
+#define SRSHARP1_SR7_HLTIBPF_TAP1 (SRSHARP1_OFFSET + SR7_HLTIBPF_TAP1 )//
+#define SRSHARP1_SR7_HCTIBPF_TAP0 (SRSHARP1_OFFSET + SR7_HCTIBPF_TAP0 )//
+#define SRSHARP1_SR7_HCTIBPF_TAP1 (SRSHARP1_OFFSET + SR7_HCTIBPF_TAP1 )//
+#define SRSHARP1_SR7_PKLONGBPF_HTAP0 (SRSHARP1_OFFSET + SR7_PKLONGBPF_HTAP0 ) //
+#define SRSHARP1_SR7_PKLONGBPF_HTAP1 (SRSHARP1_OFFSET + SR7_PKLONGBPF_HTAP1 ) //
+#define SRSHARP1_SR7_PKLONGHPF_HTAP0 (SRSHARP1_OFFSET + SR7_PKLONGHPF_HTAP0 ) //
+#define SRSHARP1_SR7_PKLONGHPF_HTAP1 (SRSHARP1_OFFSET + SR7_PKLONGHPF_HTAP1 ) //
+#define SRSHARP1_SR7_VLTIBPF_TAP0 (SRSHARP1_OFFSET + SR7_VLTIBPF_TAP0 ) //
+#define SRSHARP1_SR7_VLTIBPF_TAP1 (SRSHARP1_OFFSET + SR7_VLTIBPF_TAP1 ) //
+#define SRSHARP1_SR7_VCTIBPF_TAP0 (SRSHARP1_OFFSET + SR7_VCTIBPF_TAP0 ) //
+#define SRSHARP1_SR7_VCTIBPF_TAP1 (SRSHARP1_OFFSET + SR7_VCTIBPF_TAP1 ) //
+#define SRSHARP1_SR7_PKLONGBPF_VTAP0 (SRSHARP1_OFFSET + SR7_PKLONGBPF_VTAP0 ) //
+#define SRSHARP1_SR7_PKLONGBPF_VTAP1 (SRSHARP1_OFFSET + SR7_PKLONGBPF_VTAP1 ) //
+#define SRSHARP1_SR7_PKLONGHPF_VTAP0 (SRSHARP1_OFFSET + SR7_PKLONGHPF_VTAP0 ) //
+#define SRSHARP1_SR7_PKLONGHPF_VTAP1 (SRSHARP1_OFFSET + SR7_PKLONGHPF_VTAP1 ) //
+#define SRSHARP1_SR7_CIRBPLONG_ALP (SRSHARP1_OFFSET + SR7_CIRBPLONG_ALP ) //
+#define SRSHARP1_SR7_CIRHPLONG_ALP (SRSHARP1_OFFSET + SR7_CIRHPLONG_ALP ) //
+#define SRSHARP1_SR7_DRTBPLONG_ALP (SRSHARP1_OFFSET + SR7_DRTBPLONG_ALP ) //
+#define SRSHARP1_SR7_DRTHPLONG_ALP (SRSHARP1_OFFSET + SR7_DRTHPLONG_ALP ) //
+#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D0 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D0) //
+#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D1 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D1) //
+#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D2 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D2) //
+#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D3 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D3) //
+#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D4 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D4) //
+#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D0 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D0) //
+#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D1 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D1) //
+#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D2 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D2) //
+#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D3 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D3) //
+#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D4 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D4) //
+#define SRSHARP1_SR7_PKDRT_BLD_EN (SRSHARP1_OFFSET + SR7_PKDRT_BLD_EN ) //
+#define SRSHARP1_SR7_DRTDIF_TH (SRSHARP1_OFFSET + SR7_DRTDIF_TH ) //
+#define SRSHARP1_SR7_TIBLD_PRT (SRSHARP1_OFFSET + SR7_TIBLD_PRT ) //
+#define SRSHARP1_SR7_HTI_OPT_FORCE (SRSHARP1_OFFSET + SR7_HTI_OPT_FORCE ) //
+#define SRSHARP1_SR7_HVTI_FINALGAIN (SRSHARP1_OFFSET + SR7_HVTI_FINALGAIN ) //
+#define SRSHARP1_SR7_TIOS_SDRATIO (SRSHARP1_OFFSET + SR7_TIOS_SDRATIO ) //
+#define SRSHARP1_SR7_XTI_SDFDEN (SRSHARP1_OFFSET + SR7_XTI_SDFDEN ) //
+#define SRSHARP1_SR7_FDSD_PARAM (SRSHARP1_OFFSET + SR7_FDSD_PARAM ) //
+#define SRSHARP1_SR7_TI_BPF_EN (SRSHARP1_OFFSET + SR7_TI_BPF_EN ) //
+#define SRSHARP1_SR7_PKLONG_PF_EN (SRSHARP1_OFFSET + SR7_PKLONG_PF_EN ) //
+#define SRSHARP1_SR7_PKLONG_PF_GAIN (SRSHARP1_OFFSET + SR7_PKLONG_PF_GAIN ) //
+#define SRSHARP1_SR7_PKMINMAX_BLD (SRSHARP1_OFFSET + SR7_PKMINMAX_BLD ) //
+#define SRSHARP1_SR7_TI_CONMAXERR_GAIN (SRSHARP1_OFFSET + SR7_TI_CONMAXERR_GAIN ) //
+#define SRSHARP1_SR7_CC_PK_ADJ (SRSHARP1_OFFSET + SR7_CC_PK_ADJ ) //
+#define SRSHARP1_SR7_CC_LUT0 (SRSHARP1_OFFSET + SR7_CC_LUT0 ) //
+#define SRSHARP1_SR7_CC_LUT1 (SRSHARP1_OFFSET + SR7_CC_LUT1 ) //
+#define SRSHARP1_SR7_CC_LUT2 (SRSHARP1_OFFSET + SR7_CC_LUT2 ) //
+#define SRSHARP1_SR7_CC_LUT3 (SRSHARP1_OFFSET + SR7_CC_LUT3 ) //
+#define SRSHARP1_SR7_CC_LUT4 (SRSHARP1_OFFSET + SR7_CC_LUT4 ) //
+#define SRSHARP1_SR7_CC_LUT5 (SRSHARP1_OFFSET + SR7_CC_LUT5 ) //
+#define SRSHARP1_SR7_GRAPHIC_CTRL (SRSHARP1_OFFSET + SR7_GRAPHIC_CTRL ) //
+#define SRSHARP1_SR7_GRAPHIC_THD_GAIN (SRSHARP1_OFFSET + SR7_GRAPHIC_THD_GAIN ) //
+#define SRSHARP1_SR7_RO_GRAPHIC_FLT_CNT (SRSHARP1_OFFSET + SR7_RO_GRAPHIC_FLT_CNT ) //
+#define SRSHARP1_SR7_RO_GRAPHIC_DTL_CNT (SRSHARP1_OFFSET + SR7_RO_GRAPHIC_DTL_CNT ) //
+#define SRSHARP1_SR7_CLR_PRT_PARAM (SRSHARP1_OFFSET + SR7_CLR_PRT_PARAM ) //
+#define SRSHARP1_SR7_CLR_PRT_LC_GAIN (SRSHARP1_OFFSET + SR7_CLR_PRT_LC_GAIN ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT0 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT0 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT1 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT1 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT2 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT2 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT3 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT3 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT4 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT4 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT5 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT5 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT6 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT6 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT7 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT7 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT8 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT8 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT9 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT9 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT10 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT10 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT11 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT11 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT12 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT12 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT13 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT13 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT14 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT14 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT15 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT15 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT16 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT16 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT17 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT17 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT18 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT18 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT19 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT19 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT20 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT20 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT21 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT21 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT22 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT22 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT23 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT23 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT24 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT24 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT25 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT25 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT26 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT26 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT27 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT27 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT28 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT28 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT29 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT29 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT30 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT30 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT31 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT31 ) //
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: srsharp_regs2.h
+//
+// -----------------------------------------------
+// REG_BASE: VPPG_VCBUS_BASE = 0x52
+// -----------------------------------------------
+// 8'h50/51/52/53 have used for srsharp_regs
+// -----------------------------------------------
+// REG_BASE: VPPH_VCBUS_BASE = 0x53
+// -----------------------------------------------
+// 8'h50/51/52/53 have used for srsharp_regs
+//afbcd_multx6 use 3 reg_pages
+// -----------------------------------------------
+// REG_BASE: MADE_VCBUS_BASE = 0x54
+// -----------------------------------------------
+//
+// Reading file: afbcd_mult_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+// reg addr map
+// 8'h0 - 8'h3f : rdmif
+// 8'h40 - 8'h6f : afbcd
+// 8'h70 - 8'h7f : fgrain
+////===============================////
+#define RDMIFXN_GEN_REG ((0x5400 << 2) + 0xff000000)
+#define RDMIFXN_CANVAS0 ((0x5401 << 2) + 0xff000000)
+#define RDMIFXN_CANVAS1 ((0x5402 << 2) + 0xff000000)
+#define RDMIFXN_LUMA_X0 ((0x5403 << 2) + 0xff000000)
+#define RDMIFXN_LUMA_Y0 ((0x5404 << 2) + 0xff000000)
+#define RDMIFXN_CHROMA_X0 ((0x5405 << 2) + 0xff000000)
+#define RDMIFXN_CHROMA_Y0 ((0x5406 << 2) + 0xff000000)
+#define RDMIFXN_LUMA_X1 ((0x5407 << 2) + 0xff000000)
+#define RDMIFXN_LUMA_Y1 ((0x5408 << 2) + 0xff000000)
+#define RDMIFXN_CHROMA_X1 ((0x5409 << 2) + 0xff000000)
+#define RDMIFXN_CHROMA_Y1 ((0x540a << 2) + 0xff000000)
+#define RDMIFXN_RPT_LOOP ((0x540b << 2) + 0xff000000)
+#define RDMIFXN_LUMA0_RPT_PAT ((0x540c << 2) + 0xff000000)
+#define RDMIFXN_CHROMA0_RPT_PAT ((0x540d << 2) + 0xff000000)
+#define RDMIFXN_LUMA1_RPT_PAT ((0x540e << 2) + 0xff000000)
+#define RDMIFXN_CHROMA1_RPT_PAT ((0x540f << 2) + 0xff000000)
+#define RDMIFXN_LUMA_PSEL ((0x5410 << 2) + 0xff000000)
+#define RDMIFXN_CHROMA_PSEL ((0x5411 << 2) + 0xff000000)
+#define RDMIFXN_DUMMY_PIXEL ((0x5412 << 2) + 0xff000000)
+#define RDMIFXN_LUMA_FIFO_SIZE ((0x5413 << 2) + 0xff000000)
+#define RDMIFXN_AXI_CMD_CNT ((0x5414 << 2) + 0xff000000)
+#define RDMIFXN_AXI_RDAT_CNT ((0x5415 << 2) + 0xff000000)
+#define RDMIFXN_RANGE_MAP_Y ((0x5416 << 2) + 0xff000000)
+#define RDMIFXN_RANGE_MAP_CB ((0x5417 << 2) + 0xff000000)
+#define RDMIFXN_RANGE_MAP_CR ((0x5418 << 2) + 0xff000000)
+#define RDMIFXN_GEN_REG2 ((0x5419 << 2) + 0xff000000)
+#define RDMIFXN_PROT ((0x541a << 2) + 0xff000000)
+#define RDMIFXN_URGENT_CTRL ((0x541b << 2) + 0xff000000)
+#define RDMIFXN_GEN_REG3 ((0x541c << 2) + 0xff000000)
+#define RDMIFXN_CFMT_CTRL ((0x541d << 2) + 0xff000000)
+#define RDMIFXN_CFMT_W ((0x541e << 2) + 0xff000000)
+#define AFBCDM_ENABLE ((0x5440 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:23, reg_gclk_ctrl_core unsigned, default = 0
+//Bit 22, reg_fmt_size_sw_mode unsigned, default = 0, 0:hw mode 1:sw mode for format size
+//Bit 21, reg_addr_link_en unsigned, default = 1, 1:enable
+//Bit 20, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb
+//Bit 19, reg_dos_uncomp_mode unsigned , default = 0
+//Bit 18:16, soft_rst unsigned , default = 4
+//Bit 15:14, reserved
+//Bit 13:12, ddr_blk_size unsigned , default = 1
+//Bit 11:9, cmd_blk_size unsigend , default = 3
+//Bit 8, dec_enable unsigned , default = 0
+//Bit 7:2, reserved
+//Bit 1, head_len_sel unsigned , default = 1
+//Bit 0, dec_frm_start unsigned , default = 0
+#define AFBCDM_MODE ((0x5441 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29, ddr_sz_mode uns, default = 0 , 0: fixed block ddr size 1 : unfixed block ddr size;
+//Bit 28, blk_mem_mode uns, default = 0 , 0: fixed 16x128 size; 1 : fixed 12x128 size
+//Bit 27:26, rev_mode uns, default = 0 , reverse mode
+//Bit 25:24, mif_urgent uns, default = 3 , info mif and data mif urgent
+//Bit 23, reserved
+//Bit 22:16, hold_line_num uns, default = 4 ,
+//Bit 15:14, burst_len uns, default = 2, 0: burst1 1:burst2 2:burst4
+//Bit 13:8, compbits_yuv uns, default = 0 ,
+// bit 1:0,: y component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+// bit 3:2,: u component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+// bit 5:4,: v component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+//Bit 7:6, vert_skip_y uns, default = 0 , luma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 5:4, horz_skip_y uns, default = 0 , luma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 3:2, vert_skip_uv uns, default = 0 , chroma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 1:0, horz_skip_uv uns, default = 0 , chroma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+#define AFBCDM_SIZE_IN ((0x5442 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hsize_in uns, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_in uns, default = 1080 , pic vert size in unit: pixel
+#define AFBCDM_DEC_DEF_COLOR ((0x5443 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:20, def_color_y uns, default = 255, afbc dec y default setting value
+//Bit 19:10, def_color_u uns, default = 128, afbc dec u default setting value
+//Bit 9: 0, def_color_v uns, default = 128, afbc dec v default setting value
+#define AFBCDM_CONV_CTRL ((0x5444 << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13:12, fmt_mode uns, default = 2, 0:yuv444 1:yuv422 2:yuv420
+//Bit 11: 0, conv_lbuf_len uns, default = 256, unit=16 pixel need to set = 2^n
+#define AFBCDM_LBUF_DEPTH ((0x5445 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, dec_lbuf_depth uns, default = 128; // unit= 8 pixel
+//Bit 15:12, reserved
+//Bit 11:0, mif_lbuf_depth uns, default = 128;
+#define AFBCDM_HEAD_BADDR ((0x5446 << 2) + 0xff000000)
+//Bit 31:0, mif_info_baddr uns, default = 32'h0;
+#define AFBCDM_BODY_BADDR ((0x5447 << 2) + 0xff000000)
+//Bit 31:0, mif_data_baddr uns, default = 32'h00010000;
+#define AFBCDM_SIZE_OUT ((0x5448 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, hsize_out uns, default = 1920 ; // unit: 1 pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_out uns, default = 1080 ; // unit: 1 pixel
+#define AFBCDM_OUT_YSCOPE ((0x5449 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, out_vert_bgn uns, default = 0 ; // unit: 1 pixel
+//Bit 15:13, reserved
+//Bit 12:0, out_vert_end uns, default = 1079 ; // unit: 1 pixel
+#define AFBCDM_STAT ((0x544a << 2) + 0xff000000)
+//Bit 31:1, ro_dbg_top_info uns, default = 0
+//Bit 0, frm_end_stat uns, default = 0 frame end status
+#define AFBCDM_VD_CFMT_CTRL ((0x544b << 2) + 0xff000000)
+//Bit 31 cfmt_gclk_bit_dis uns, default = 0 ; // it true, disable clock, otherwise enable clock
+//Bit 30 cfmt_soft_rst_bit uns, default = 0 ; // soft rst bit
+//Bit 29 reserved
+//Bit 28 chfmt_rpt_pix uns, default = 0 ; // if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
+//Bit 27:24 chfmt_ini_phase uns, default = 0 ; // horizontal formatter initial phase
+//Bit 23 chfmt_rpt_p0_en uns, default = 0 ; // horizontal formatter repeat pixel 0 enable
+//Bit 22:21 chfmt_yc_ratio uns, default = 0 ; // horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
+//Bit 20 chfmt_en uns, default = 0 ; // horizontal formatter enable
+//Bit 19 cvfmt_phase0_always_en uns, default = 0 ; //if true, always use phase0 while vertical formater, meaning always
+// repeat data, no interpolation
+//Bit 18 cvfmt_rpt_last_dis uns, default = 0 ; //if true, disable vertical formatter chroma repeat last line
+//Bit 17 cvfmt_phase0_nrpt_en uns, default = 0 ; //veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable
+//Bit 16 cvfmt_rpt_line0_en uns, default = 0 ; //veritcal formatter repeat line 0 enable
+//Bit 15:12 cvfmt_skip_line_num uns, default = 0 ; //vertical formatter skip line num at the beginning
+//Bit 11:8 cvfmt_ini_phase uns, default = 0 ; //vertical formatter initial phase
+//Bit 7:1 cvfmt_phase_step uns, default = 0 ; //vertical formatter phase step (3.4)
+//Bit 0 cvfmt_en uns, default = 0 ; //vertical formatter enable
+#define AFBCDM_VD_CFMT_W ((0x544c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 chfmt_w uns, default = 0 ;horizontal formatter width
+//Bit 15:13 reserved
+//Bit 12:0 cvfmt_w uns, default = 0 ;vertical formatter width
+#define AFBCDM_MIF_HOR_SCOPE ((0x544d << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, mif_blk_bgn_h uns, default = 0 ; // unit: 32 pixel/block hor
+//Bit 15:10, reserved
+//Bit 9: 0, mif_blk_end_h uns, default = 59 ; // unit: 32 pixel/block hor
+#define AFBCDM_MIF_VER_SCOPE ((0x544e << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, mif_blk_bgn_v uns, default = 0 ; // unit: 32 pixel/block ver
+//Bit 15:12, reserved
+//Bit 11: 0, mif_blk_end_v uns, default = 269; // unit: 32 pixel/block ver
+#define AFBCDM_PIXEL_HOR_SCOPE ((0x544f << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, dec_pixel_bgn_h uns, default = 0 ; // unit: pixel
+//Bit 15:13, reserved
+//Bit 12: 0, dec_pixel_end_h uns, default = 1919 ; // unit: pixel
+#define AFBCDM_PIXEL_VER_SCOPE ((0x5450 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, dec_pixel_bgn_v uns, default = 0 ; // unit: pixel
+//Bit 15:13, reserved
+//Bit 12: 0, dec_pixel_end_v uns, default = 1079 ; // unit: pixel
+#define AFBCDM_VD_CFMT_H ((0x5451 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12:0 cfmt_h uns, default = 142 ; //vertical formatter height
+#define AFBCDM_IQUANT_ENABLE ((0x5452 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_quant_expand_en_1 //unsigned, RW, default = 0 enable for quantization value expansion
+//Bit 10 reg_quant_expand_en_0 //unsigned, RW, default = 0 enable for quantization value expansion
+//Bit 9: 8 reg_bcleav_ofst //signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1;
+//Bit 7: 5 reserved
+//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy
+//Bit 3: 1 reserved
+//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy
+#define AFBCDM_IQUANT_LUT_1 ((0x5453 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDM_IQUANT_LUT_2 ((0x5454 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDM_IQUANT_LUT_3 ((0x5455 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDM_IQUANT_LUT_4 ((0x5456 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDM_ROT_CTRL ((0x5460 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_pip_mode //unsigned, RW, default = 0 , 0:dec_src from vdin/dos 1:dec_src from pip
+//Bit 26:24 reg_rot_uv_vshrk_drop_mode //unsigned, RW, default = 0 , 0:average (1/2: 1:left 2:right) (1/4: 1:[0] 2:[1] 3:[2] 4:[3], 5:left_121 6:right_121)
+//Bit 23 reserved
+//Bit 22:20 reg_rot_uv_hshrk_drop_mode //unsigned, RW, default = 0 , 0:average (1/2: 1:left 2:right) (1/4: 1:[0] 2:[1] 3:[2] 4:[3], 5:left_121 6:right_121)
+//Bit 19:18 reg_rot_uv_vshrk_ratio //unsigned, RW, default = 0 , 0:no shrink 1:1/2 shrink 2:1/4 shrink
+//Bit 17:16 reg_rot_uv_hshrk_ratio //unsigned, RW, default = 0 , 0:no shrink 1:1/2 shrink 2:1/4 shrink
+//Bit 15 reserved
+//Bit 14:12 reg_rot_y_vshrk_drop_mode //unsigned, RW, default = 0 , 0:average (1/2: 1:left 2:right) (1/4: 1:[0] 2:[1] 3:[2] 4:[3], 5:left_121 6:right_121)
+//Bit 11 reserved
+//Bit 10:8 reg_rot_y_hshrk_drop_mode //unsigned, RW, default = 0 , 0:average (1/2: 1:left 2:right) (1/4: 1:[0] 2:[1] 3:[2] 4:[3], 5:left_121 6:right_121)
+//Bit 7:6 reg_rot_y_vshrk_ratio //unsigned, RW, default = 0 , 0:no shrink 1:1/2 shrink 2:1/4 shrink
+//Bit 5:4 reg_rot_y_hshrk_ratio //unsigned, RW, default = 0 , 0:no shrink 1:1/2 shrink 2:1/4 shrink
+//Bit 3:2 reg_rot_uv422_drop_mode //unsigned, RW, default = 0 , 0:average 1:left 2:right
+//Bit 1 reg_rot_uv422_omode //unsigned, RW, default = 0 , when rot input fmt422, 0:output_uv422 1:output_uv420
+//Bit 0 reg_rot_enable //unsigned, RW, default = 0 , rotation enable
+#define AFBCDM_ROT_SCOPE ((0x5461 << 2) + 0xff000000)
+//Bit 31:17 reserved
+//Bit 16 reg_rot_ifmt_force444 //unsigned, RW , default = 1, 1: rot input fmt force as 444
+//Bit 15:14 reg_rot_ofmt_mode //unsigned, RW , default = 0, rot output fmt mode
+//Bit 13:12 reg_rot_compbits_out_y //unsigned, RW , default = 0, rot output compbit y
+//Bit 11:10 reg_rot_compbits_out_uv //unsigned, RW , default = 0, rot output compbit uv
+//Bit 9:8 reg_rot_wrbgn_v //unsigned, RW , default = 0, rot pic vert size window begin pixel
+//Bit 7:5 reserved
+//Bit 4:0 reg_rot_wrbgn_h //unsigned, RW , default = 0, rot pic hori size window begin pixel
+#define AFBCDM_RPLC_CTRL ((0x5462 << 2) + 0xff000000)
+//Bit 31 reg_rplc_inter_corr_en //unsigned, RW , default = 0 , //pip replace inte-frame edge correct enable
+//Bit 30 reg_rplc_dummy_corr_en //unsigned, RW , default = 0 , //pip replace outsize of real-pipframe edge correct enable
+//Bit 29 reg_rplc_byps //unsigned, RW , default = 1 , //pip replace module bypass
+//Bit 28:16 reg_rplc_vsize_in //unsigned, RW , default = 1080, //
+//Bit 15:13 reserved
+//Bit 12:0 reg_rplc_hsize_in //unsigned, RW , default = 1920,
+#define AFBCDM_RPLC_PICEN ((0x5463 << 2) + 0xff000000)
+//Bit 27:16 reg_rplc_def_color_y //unsigned, RW , default =0 , //pip replace def_color_y
+//Bit 15:0 reg_rplc_pic_enable //unsigned, RW , default =16'hffff , //pip replace pip_picure enbale
+#define AFBCDM_RPLC_DEFCOL ((0x5464 << 2) + 0xff000000)
+//Bit 23:12 reg_rplc_def_color_v //unsigned, RW , default =0 , //pip replace def_color_v
+//Bit 11:0 reg_rplc_def_color_u //unsigned, RW , default =0 , //pip replace def_color_u
+#define AFBCDM_RPLC_SCPXN_ADDR ((0x5465 << 2) + 0xff000000)
+//Bit 31:0 reg_rplc_scpxn_addr //unsigned, RW , default =0 , //pip replace scopx16 addr
+#define AFBCDM_RPLC_SCPXN_DATA ((0x5466 << 2) + 0xff000000)
+//Bit 31:0 reg_rplc_scpxn_data //unsigned, RW , default =0 , //pip replace scopx16 data
+#define AFBCDM_FGRAIN_CTRL ((0x5470 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_sync_ctrl // unsigned , RW, default = 0
+//Bit 23 reserved
+//Bit 22 reg_dma_st_clr // unsigned , RW, default = 0 clear DMA error status
+//Bit 21 reg_hold4dma_scale // unsigned , RW, default = 0 1 to wait DMA scale data ready before accept input data default = 0
+//Bit 20 reg_hold4dma_tbl // unsigned , RW, default = 0 1 to wait DMA grain table data ready before accept input data default = 0
+//Bit 19 reg_cin_uv_swap // unsigned , RW, default = 0 1 to swap U/V input
+//Bit 18 reg_cin_rev // unsigned , RW, default = 0 1 to reverse the U/V input order
+//Bit 17 reg_yin_rev // unsigned , RW, default = 0 1 to reverse the Y input order
+//Bit 16 reg_fgrain_ext_imode // unsigned , RW, default = 1 0 to indicate the input data is *4 in 8bit mode
+//Bit 15 reg_use_par_apply_fgrain // unsigned , RW, default = 0 1 to use apply_fgrain from DMA table
+//Bit 14 reg_fgrain_last_ln_mode // unsigned , RW, default = 0 1 to keep fgrain noise generator though the input is finished for rdmif.
+//Bit 13 reg_fgrain_use_sat4bp // unsigned , RW, default = 0 1 to use fgain_max/min for sat not {DW{1'b1}}/0
+//Bit 12 reg_apply_c_mode // unsigned , RW, default = 1 0 to following C
+//Bit 11 reg_fgrain_tbl_sign_mode // unsigned , RW, default = 1 0 to indicate signed bit is not extended in 8bit mode
+//Bit 10 reg_fgrain_tbl_ext_mode // unsigned , RW, default = 1 0 to indicate the grain table is *4 in 8bit mode
+//Bit 9: 8 reg_fmt_mode // unsigned , RW, default = 2 0:444; 1:422; 2:420; 3:reserved
+//Bit 7: 6 reg_comp_bits // unsigned , RW, default = 1 0:8bits; 1:10bits, else 12 bits
+//Bit 5: 4 reg_rev_mode // unsigned . RW, default = 0 0:h_rev; 1:v_rev;
+//Bit 3 reserved
+//Bit 2 reg_block_mode // unsigned , RW, default = 1
+//Bit 1 reg_fgrain_loc_en // unsigned , RW, default = 0 frame-based fgrain enable
+//Bit 0 reg_fgrain_glb_en // unsigned , RW, default = 0 global-based fgrain enable
+#define AFBCDM_FGRAIN_WIN_H ((0x5471 << 2) + 0xff000000)
+//Bit 31:16 reg_win_end_h .unsigned , default = 3812
+//Bit 15: 0, reg_win_bgn_h .unsigned , default = 0
+#define AFBCDM_FGRAIN_WIN_V ((0x5472 << 2) + 0xff000000)
+//Bit 31:16 reg_win_end_v .unsigned , default = 2156
+//Bit 15: 0, reg_win_bgn_v .unsigned , default = 0
+#define AFBCDM_FGRAIN_SW_Y_RANNGE ((0x5473 << 2) + 0xff000000)
+//Bit 31, reg_fgrain_sw_yrange .unsigned , default = 0
+//Bit 30:26, reserved
+//Bit 25:16, reg_fgrain_ymax .unsigned , default = 1023
+//Bit 15:10, reserved
+//Bit 9: 0, reg_fgrain_ymin .unsigned , default = 0
+#define AFBCDM_FGRAIN_SW_C_RANNGE ((0x5474 << 2) + 0xff000000)
+//Bit 31, reg_fgrain_sw_crange .unsigned , default = 0
+//Bit 30:26, reserved
+//Bit 25:16, reg_fgrain_cmax .unsigned , default = 1023
+//Bit 15:10, reserved
+//Bit 9: 0, reg_fgrain_cmin .unsigned , default = 0
+#define AFBCDM_FGRAIN_GCLK_CTRL_0 ((0x5475 << 2) + 0xff000000)
+//Bit 31:0, reg_fgrain_gclk_ctrl0 .unsigned , default = 0
+#define AFBCDM_FGRAIN_GCLK_CTRL_1 ((0x5476 << 2) + 0xff000000)
+//Bit 31:0, reg_fgrain_gclk_ctrl1 .unsigned , default = 0
+#define AFBCDM_FGRAIN_GCLK_CTRL_2 ((0x5477 << 2) + 0xff000000)
+//Bit 31:0, reg_fgrain_gclk_ctrl2 .unsigned , default = 0
+#define AFBCDM_FGRAIN_PARAM_ADDR ((0x5478 << 2) + 0xff000000)
+#define AFBCDM_FGRAIN_PARAM_DATA ((0x5479 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: afbcd_mult_regs.h
+//
+//afbcd_multx6 use 3 reg_pages
+// -----------------------------------------------
+// REG_BASE: MADF_VCBUS_BASE = 0x55
+// -----------------------------------------------
+//`include "afbcd_mult_regs.h"
+//afbcd_multx6 use 3 reg_pages
+// -----------------------------------------------
+// REG_BASE: MADG_VCBUS_BASE = 0x56
+// -----------------------------------------------
+//`include "afbcd_mult_regs.h"
+// -----------------------------------------------
+// REG_BASE: MADH_VCBUS_BASE = 0x57
+// -----------------------------------------------
+// -----------------------------------------------
+// REG_BASE: VPPI_VCBUS_BASE = 0x58
+// -----------------------------------------------
+//
+// Reading file: pip_alph_gen_regs.h
+//
+//
+// Reading file: vd1_pip_alph_gen_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+////===================================////
+////reg
+////===================================////
+#define VD1_PIP_ALPH_CTRL ((0x5880 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28 reg_alph_gen_dbg unsigned,default = 0
+//Bit 27:12 reg_pic_en unsigned,default = 16'h0
+//Bit 11:3 reg_alph0 unsigned,default = 0
+//Bit 2:1 reg_alph_gen_mode unsigned, default = 0 0:original, 1: 0.5 alpha 2: 0.25/0.5/0.75 alph
+//Bit 0 reg_alph_gen_byps unsigned, default = 1
+#define VD1_PIP_ALPH_SCP_H_0 ((0x5881 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h0 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h0 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_H_1 ((0x5882 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h1 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h1 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_H_2 ((0x5883 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h2 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h2 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_H_3 ((0x5884 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h3 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h3 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_H_4 ((0x5885 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h4 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h4 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_H_5 ((0x5886 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h5 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h5 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_H_6 ((0x5887 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h6 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h6 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_H_7 ((0x5888 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h7 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h7 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_H_8 ((0x5889 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h8 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h8 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_H_9 ((0x588a << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h9 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h9 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_H_10 ((0x588b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h10 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h10 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_H_11 ((0x588c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h11 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h11 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_H_12 ((0x588d << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h12 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h12 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_H_13 ((0x588e << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h13 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h13 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_H_14 ((0x588f << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h14 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h14 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_H_15 ((0x5890 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h15 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h15 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_V_0 ((0x5891 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v0 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v0 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_V_1 ((0x5892 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v1 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v1 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_V_2 ((0x5893 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v2 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v2 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_V_3 ((0x5894 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v3 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v3 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_V_4 ((0x5895 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v4 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v4 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_V_5 ((0x5896 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v5 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v5 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_V_6 ((0x5897 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v6 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v6 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_V_7 ((0x5898 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v7 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v7 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_V_8 ((0x5899 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v8 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v8 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_V_9 ((0x589a << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v9 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v9 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_V_10 ((0x589b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v10 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v10 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_V_11 ((0x589c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v11 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v11 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_V_12 ((0x589d << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v12 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v12 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_V_13 ((0x589e << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v13 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v13 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_V_14 ((0x589f << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v14 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v14 unsigned,default = 0
+#define VD1_PIP_ALPH_SCP_V_15 ((0x58a0 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v15 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v15 unsigned,default = 0
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vd1_pip_alph_gen_regs.h
+//
+//
+// Reading file: vd2_pip_alph_gen_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+////===================================////
+////reg
+////===================================////
+#define VD2_PIP_ALPH_CTRL ((0x58b0 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28 reg_alph_gen_dbg unsigned,default = 0
+//Bit 27:12 reg_pic_en unsigned,default = 16'h
+//Bit 11:3 reg_alph0 unsigned,default = 0
+//Bit 2:1 reg_alph_gen_mode unsigned, default = 0 0:original, 1: 0.5 alpha 2: 0.25/0.5/0.75 alph
+//Bit 0 reg_alph_gen_byps unsigned, default = 1
+#define VD2_PIP_ALPH_SCP_H_0 ((0x58b1 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h0 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h0 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_H_1 ((0x58b2 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h1 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h1 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_H_2 ((0x58b3 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h2 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h2 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_H_3 ((0x58b4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h3 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h3 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_H_4 ((0x58b5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h4 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h4 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_H_5 ((0x58b6 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h5 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h5 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_H_6 ((0x58b7 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h6 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h6 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_H_7 ((0x58b8 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h7 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h7 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_H_8 ((0x58b9 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h8 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h8 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_H_9 ((0x58ba << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h9 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h9 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_H_10 ((0x58bb << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h10 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h10 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_H_11 ((0x58bc << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h11 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h11 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_H_12 ((0x58bd << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h12 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h12 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_H_13 ((0x58be << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h13 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h13 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_H_14 ((0x58bf << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h14 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h14 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_H_15 ((0x58c0 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h15 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h15 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_V_0 ((0x58c1 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v0 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v0 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_V_1 ((0x58c2 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v1 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v1 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_V_2 ((0x58c3 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v2 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v2 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_V_3 ((0x58c4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v3 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v3 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_V_4 ((0x58c5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v4 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v4 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_V_5 ((0x58c6 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v5 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v5 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_V_6 ((0x58c7 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v6 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v6 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_V_7 ((0x58c8 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v7 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v7 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_V_8 ((0x58c9 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v8 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v8 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_V_9 ((0x58ca << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v9 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v9 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_V_10 ((0x58cb << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v10 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v10 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_V_11 ((0x58cc << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v11 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v11 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_V_12 ((0x58cd << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v12 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v12 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_V_13 ((0x58ce << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v13 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v13 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_V_14 ((0x58cf << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v14 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v14 unsigned,default = 0
+#define VD2_PIP_ALPH_SCP_V_15 ((0x58d0 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v15 unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v15 unsigned,default = 0
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vd2_pip_alph_gen_regs.h
+//
+//
+// Closing file: pip_alph_gen_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: ./vcbus_regs.h
+//
+//
+// Reading file: ./ge2d_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+////// GE2D Registers 0x8a0 - 0x8ff
+//address is 0xd016_0000 - 0xd0160000 - 0xd01603ff
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: GE2D_GCBUS_BASE = 0x00
+// -----------------------------------------------
+//Bit 31, destination bytemask only if destination bitmask is enable
+//Bit 30, destination bitmask enable
+//Bit 29, source2 key enable
+//Bit 28, source2 key mode, 0: mask data when match, 1: mask data when unmatch
+//Bit 27, source1 key enable
+//Bit 26, source1 key mode, 0: mask data when match, 1: mask data when unmatch
+//Bit 25:24, dst1 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 23 dst clip mode, 0: write inside clip window, 1: write outside clip window
+//Bit 22:17, reserved
+//Bit 16:15, src2 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 14 src2 fill mode, 0: repeat data, 1: fill default color
+//Bit 13:12 src2 picture struct, 00: frame, 10: even, 11: odd
+//Bit 11 src1 x direction yc ration, 0: 1:1, 1: 2:1
+//Bit 10 src1 y direction yc ration, 0: 1:1, 1: 2:1
+//Bit 9:7 reserved
+//Bit 6:5, src1 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 4 src1 fill mode, 0: repeat data, 1: fill default color
+//Bit 3 src1 lookup table enable
+//Bit 2:1 src1 picture struct, 00: frame, 10: even, 11: odd
+//Bit 0 src1 separate buffer enable
+#define GE2D_GEN_CTRL0 ((0x00a0 << 2) + 0xff040000)
+//Bit 31, soft rst
+//Bit 30, dst write response counter reset
+//Bit 29, disable adding dst write response count to busy bit
+//Bit 28:26, reserved
+//bit 25:24, interrupt control, if bit[0] true, generate interrupt when one command done,
+// if bit[1] true, generate interrupt when ge2d change from busy to not busy
+//Bit 23:22 src2 burst size control
+//Bit 21:16 src1 burst size control, 5:4, yfifo, 3:2, cbfifo, 1:0, crfifo
+// each 2bit, 00: 24 64bitword, 01: 32 64bitword, 10: 48 64bitwords, 11: 64 64bitwords
+//Bit 15:14, dst1 picture struct, 00: frame, 10:top, 11: bottom
+//Bit 13:12, bit 13 if true, force read src1, bit 12 if true, force read src2
+//Bit 11, dst2 request urgent enable
+//Bit 10, src1 request urgent enable
+//Bit 9, src2 request urgent enable
+//Bit 8, dst1 request urgent enable
+//Bit 7:0 src1 global alpha
+#define GE2D_GEN_CTRL1 ((0x00a1 << 2) + 0xff040000)
+//Bit31 alpha conversion mode in alu, 0: alpha_out = (alpha !=0) ? alpha +1 : 0;
+// otherwise, alpha_out = (alpha < 128) ? alpha: alpha + 1;
+//Bit30 color conversion mode in alu, 0: color_out = (color != 0) ? color +1: 0;
+// otherwise, color_out = (color < 128) ? color: color + 1;
+//Bit29 src1_gb_alpha_en, As = src1_gb_alpha_en ? Asr * Ag: Asr
+//Bit28 dst1_color_round_mode, 0: truncate, 1: + 0.5 rounding
+//Bit27 src2_color_expand_mode, 0: add 0, 1: add MSBs
+//Bit26 src2_alpha_expand_mode, 0: add 0, 1: add MSBs
+//Bit25 src1_color_expand_mode, 0: add 0, 1: add MSBs
+//Bit24 src1_alpha_expand_mode, 0: add 0, 1: add MSBs
+//Bit 23 if true, dst little endian, otherwise big endian
+//Bit 22:19 dst1 color_map
+// dst1_format=0 : output 8-bit;
+// dst1_format=1, dst1_color_map=1: output 16-bit YCbCr 655;
+// dst1_format=1, dst1_color_map=2: output 16-bit YCbCr 844;
+// dst1_format=1, dst1_color_map=3: output 16-bit YCbCrA 6442;
+// dst1_format=1, dst1_color_map=4: output 16-bit YCbCrA 4444;
+// dst1_format=1, dst1_color_map=5: output 16-bit YCbCr 565;
+// dst1_format=1, dst1_color_map=6: output 16-bit AYCbCr 4444;
+// dst1_format=1, dst1_color_map=7: output 16-bit AYCbCr 1555;
+// dst1_format=1, dst1_color_map=8: output 16-bit YCbCrA 4642;
+// dst1_format=1, dst1_color_map=9: output 16-bit CbCr 88;
+// dst1_format=1, dst1_color_map=10:output 16-bit CrCb 88;
+// dst1_format=2, dst1_color_map=0: output 24-bit YCbCr 888;
+// dst1_format=2, dst1_color_map=1: output 24-bit YCbCrA 5658;
+// dst1_format=2, dst1_color_map=2: output 24-bit AYCbCr 8565;
+// dst1_format=2, dst1_color_map=3: output 24-bit YCbCrA 6666;
+// dst1_format=2, dst1_color_map=4: output 24-bit AYCbCr 6666;
+// dst1_format=2, dst1_color_map=5: output 24-bit CrCbY 888;
+// dst1_format=3, dst1_color_map=0: output 32-bit YCbCrA 8888;
+// dst1_format=3, dst1_color_map=1: output 32-bit AYCbCr 8888;
+// dst1_format=3, dst1_color_map=2: output 32-bit ACrCbY 8888;
+// dst1_format=3, dst1_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 17:16 dst1_format, 00: 8bit, 01:16bit, 10:24bit, 11: 32bit
+//Bit 15 if true, src2 little endian, otherwise big endian
+//Bit 14:11 src2 color_map
+// src2_format=0 : output 8-bit;
+// src2_format=1, src2_color_map=1: output 16-bit YCbCr 655;
+// src2_format=1, src2_color_map=2: output 16-bit YCbCr 844;
+// src2_format=1, src2_color_map=3: output 16-bit YCbCrA 6442;
+// src2_format=1, src2_color_map=4: output 16-bit YCbCrA 4444;
+// src2_format=1, src2_color_map=5: output 16-bit YCbCr 565;
+// src2_format=1, src2_color_map=6: output 16-bit AYCbCr 4444;
+// src2_format=1, src2_color_map=7: output 16-bit AYCbCr 1555;
+// src2_format=1, src2_color_map=8: output 16-bit YCbCrA 4642;
+// src2_format=2, src2_color_map=0: output 24-bit YCbCr 888;
+// src2_format=2, src2_color_map=1: output 24-bit YCbCrA 5658;
+// src2_format=2, src2_color_map=2: output 24-bit AYCbCr 8565;
+// src2_format=2, src2_color_map=3: output 24-bit YCbCrA 6666;
+// src2_format=2, src2_color_map=4: output 24-bit AYCbCr 6666;
+// src2_format=2, src2_color_map=5: output 24-bit CrCbY 888;
+// src2_format=3, src2_color_map=0: output 32-bit YCbCrA 8888;
+// src2_format=3, src2_color_map=1: output 32-bit AYCbCr 8888;
+// src2_format=3, src2_color_map=2: output 32-bit ACrCbY 8888;
+// src2_format=3, src2_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 9:8 src2 format, 00: 8bit, 01:16bit, 10:24bit 11: 32bit
+//Bit 7 if true, src1 little endian, otherwise big endian
+//Bit 6:3 src1 color_map
+// src1_format=0 : output 8-bit;
+// src1_format=1, src1_color_map=0: output 4:2:2 (Y0Cb0Y1Cr0);
+// src1_format=1, src1_color_map=1: output 16-bit YCbCr 655;
+// src1_format=1, src1_color_map=2: output 16-bit YCbCr 844;
+// src1_format=1, src1_color_map=3: output 16-bit YCbCrA 6442;
+// src1_format=1, src1_color_map=4: output 16-bit YCbCrA 4444;
+// src1_format=1, src1_color_map=5: output 16-bit YCbCr 565;
+// src1_format=1, src1_color_map=6: output 16-bit AYCbCr 4444;
+// src1_format=1, src1_color_map=7: output 16-bit AYCbCr 1555;
+// src1_format=1, src2_color_map=8: output 16-bit YCbCrA 4642;
+// src1_format=2, src1_color_map=0: output 24-bit YCbCr 888;
+// src1_format=2, src1_color_map=1: output 24-bit YCbCrA 5658;
+// src1_format=2, src1_color_map=2: output 24-bit AYCbCr 8565;
+// src1_format=2, src1_color_map=3: output 24-bit YCbCrA 6666;
+// src1_format=2, src1_color_map=4: output 24-bit AYCbCr 6666;
+// src1_format=2, src1_color_map=5: output 24-bit CrCbY 888;
+// src1_format=2, src1_color_map=14:output 8-bit Y and 16-bit CbCr;
+// src1_format=2, src1_color_map=15:output 8-bit Y and 16-bit CrCb;
+// src1_format=3, src1_color_map=0: output 32-bit YCbCrA 8888;
+// src1_format=3, src1_color_map=1: output 32-bit AYCbCr 8888;
+// src1_format=3, src1_color_map=2: output 32-bit ACrCbY 8888;
+// src1_format=3, src1_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 1:0 src1 format, 00: 8bit, 01:16bit/4:2:2, 10:24bit 11: 32bit
+#define GE2D_GEN_CTRL2 ((0x00a2 << 2) + 0xff040000)
+//Bit 9 if true, all src2 data use default color
+//Bit 8 if true, all src1 data use default color
+//Bit 7 if true, dst x/y swap
+//Bit 6 if true, dst x direction reversely read
+//Bit 5 if true, dst y direction reversely read
+//Bit 4 if true, src2 x direction reversely read
+//Bit 3 if true, src2 y direction reversely read
+//Bit 2 if true, src1 x direction reversely read
+//Bit 1 if true, src1 y direction reversely read
+//Bit 0 cmd write
+#define GE2D_CMD_CTRL ((0x00a3 << 2) + 0xff040000)
+//Read only
+//Bit 28:17 dst write response counter, for debug only
+//Bit 16:7 ge2d_dp status, for debug only
+//Bit 6 read src1 cmd ready
+//Bit 5 read src2 cmd ready
+//Bit 4 pre dpcmd ready
+//Bit 3 ge2d dpcmd ready
+//Bit 2 ge2d buffer command valid
+//Bit 1 ge2d current command valid
+//Bit 0 ge2d busy
+#define GE2D_STATUS0 ((0x00a4 << 2) + 0xff040000)
+//
+//Read only
+// Bit 29:16 ge2d_dst1_status, for debug only
+// Bit 15 ge2d_rd_src2 core.fifo_empty
+// Bit 14 ge2d_rd_src2 core.fifo_overflow
+// Bit 13:12 ge2d_rd_src2 core.req_st
+// Bit 11 ge2d_rd_src2 cmd_if.cmd_err, true if cmd_format=1
+// Bit 10 ge2d_rd_src2 cmd_if.cmd_st, 0=IDLE state, 1=BUSY state
+// Bit 9 ge2d_rd_src1 luma_core(chroma_core).fifo_empty
+// Bit 8 ge2d_rd_src1 luma_core(chroma_core).fifo_overflow
+// Bit 7: 6 ge2d_rd_src1 chroma_core.req_st_cr
+// Bit 5: 4 ge2d_rd_src1 chroma_core.req_st_cb
+// Bit 3: 2 ge2d_rd_src1 luma_core.req_st_y
+// Bit 1 ge2d_rd_src1 cmd_if.stat_read_window_err, 1=reading/clipping window setting exceed limit
+// Bit 0 ge2d_rd_src1 cmd_if.cmd_st, 0=IDLE state, 1=BUSY state
+#define GE2D_STATUS1 ((0x00a5 << 2) + 0xff040000)
+//SRC1 default clolor
+//{Y,Cb,Cr,A}/{R,G,B,A}
+#define GE2D_SRC1_DEF_COLOR ((0x00a6 << 2) + 0xff040000)
+//Bit 31, SRC1 clip x start extra, if true, one more data is read for chroma
+//Bit 28:16, SRC1 clip x start
+//Bit 15, SRC1 clip x end extra, if true, one more data is read for chroma
+//Bit 12:0, SRC1 clip x end
+#define GE2D_SRC1_CLIPX_START_END ((0x00a7 << 2) + 0xff040000)
+//Bit 31, SRC1 clip y start extra, if true, one more data is read for chroma
+//Bit 28:16, SRC1 clip y start
+//Bit 15, SRC1 clip y end extra, if true, one more data is read for chroma
+//Bit 12:0, SRC1 clip y end
+#define GE2D_SRC1_CLIPY_START_END ((0x00a8 << 2) + 0xff040000)
+//Bit 31:24, SRC1 canvas address0
+//Bit 23:16, SRC1 canvas address1
+//Bit 15:8, SRC1 canvas address2
+#define GE2D_SRC1_CANVAS ((0x00a9 << 2) + 0xff040000)
+//Bit 31, SRC1 x start extra bit1, if true, one more chroma data is read for x even start chroma data when y/c ratio = 2
+// or x even/odd start chroma extra data when y/c ratio = 1
+//Bit 30, SRC1 x start extra bit0, if true, one more chroma data is read for x odd start chroma data when y/c ratio = 2
+//Bit 29:16, SRC1 x start, signed data
+//Bit 15, SRC1 x end extra bit1, if true, one more chroma data is read for x odd end chroma data when y/c ratio = 2
+// or x even/odd end chroma extra data when y/c ratio = 1
+//Bit 14, SRC1 x end extra bit0, if true, one more chroma data is read for x even end chroma data when y/c ratio = 2
+//Bit 13:0, SRC1 x end, signed data
+#define GE2D_SRC1_X_START_END ((0x00aa << 2) + 0xff040000)
+//Bit 31, SRC1 y start extra, if true, one more chroma data is read for y even start chroma data when y/c ratio = 2
+// or y even/odd start chroma extra data when y/c ratio = 1
+//Bit 30, SRC1 y start extra, if true, one more chroma data is read for x odd start chroma data when y/c ratio = 2
+//Bit 28:16, SRC1 y start
+//Bit 15, SRC1 y end extra bit1, if true, one more chroma data is read for y odd end chroma data when y/c ratio = 2
+// or y even/odd end chroma extra data when y/c ratio = 1
+//Bit 14, SRC1 y end extra bit0, if true, one more chroma data is read for y even end chroma data when y/c ratio = 2
+//Bit 12:0, SRC1 y end
+#define GE2D_SRC1_Y_START_END ((0x00ab << 2) + 0xff040000)
+// Bit 31: 9 Reserved
+// Bit 8 RW, 0 = Write LUT, 1 = Read LUT
+// Bit 7: 0 RW, lut_addr
+#define GE2D_SRC1_LUT_ADDR ((0x00ac << 2) + 0xff040000)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define GE2D_SRC1_LUT_DAT ((0x00ad << 2) + 0xff040000)
+//Bit 19, if true, horizontal formatter using repeat to get the pixel, otherwise using interpolation
+//Bit 18, horizontal formatter en
+//Bit 17, if true, vertical formatter using repeat to get the pixel, otherwise using interpolation
+//Bit 16, vertical formatter en
+//Bit 15:8 X direction chroma phase,
+// [7:4] for x direction even start/end chroma phase when y/c ratio = 2
+// or start/end even/odd chroma phase when y/c ratio = 1
+// [3:0] for x direction odd start/end chroma phase only when y/c ration = 2
+//Bit 7:0 Y direction chroma phase,
+// [7:4] for y direction even start/end chroma phase when y/c ratio = 2
+// or start/end even/odd chroma phase when y/c ratio = 1
+// [3:0] for y direction odd start/end chroma phase only when y/c ration = 2
+#define GE2D_SRC1_FMT_CTRL ((0x00ae << 2) + 0xff040000)
+//SRC2 default clolor
+//{Y,Cb,Cr,A}/{R,G,B,A}
+#define GE2D_SRC2_DEF_COLOR ((0x00af << 2) + 0xff040000)
+//Bit 28:16, SRC2 clip x start
+//Bit 12:0, SRC2 clip x end
+#define GE2D_SRC2_CLIPX_START_END ((0x00b0 << 2) + 0xff040000)
+//Bit 28:16, SRC2 clip y start
+//Bit 12:0, SRC2 clip y end
+#define GE2D_SRC2_CLIPY_START_END ((0x00b1 << 2) + 0xff040000)
+//Bit 28:16, SRC2 x start
+//Bit 12:0, SRC2 x end
+#define GE2D_SRC2_X_START_END ((0x00b2 << 2) + 0xff040000)
+//Bit 28:16, SRC2 y start
+//Bit 12:0, SRC2 y end
+#define GE2D_SRC2_Y_START_END ((0x00b3 << 2) + 0xff040000)
+//Bit 28:16, DST clip x start
+//Bit 12:0, DST clip x end
+#define GE2D_DST_CLIPX_START_END ((0x00b4 << 2) + 0xff040000)
+//
+//Bit 28:16, DST clip y start
+//Bit 12:0, DST clip y end
+#define GE2D_DST_CLIPY_START_END ((0x00b5 << 2) + 0xff040000)
+//Bit 28:16, DST x start
+//Bit 12:0, DST x end
+#define GE2D_DST_X_START_END ((0x00b6 << 2) + 0xff040000)
+//
+//Bit 28:16, DST x start
+//Bit 12:0, DST x end
+#define GE2D_DST_Y_START_END ((0x00b7 << 2) + 0xff040000)
+//Bit 23:16 DST2 canvas address
+//Bit 15:8 SRC2 canvas address
+//Bit 7:0 DST1 canvas address
+#define GE2D_SRC2_DST_CANVAS ((0x00b8 << 2) + 0xff040000)
+//vertical scaler phase step
+//Bit 28:0, 5.24 format
+#define GE2D_VSC_START_PHASE_STEP ((0x00b9 << 2) + 0xff040000)
+//phase slope
+//Bit 24:0, bit 24 signed bit
+#define GE2D_VSC_PHASE_SLOPE ((0x00ba << 2) + 0xff040000)
+//Bit 30:29, vertical repeat line0 number
+//Bit 23:0, vertical scaler initial phase
+#define GE2D_VSC_INI_CTRL ((0x00bb << 2) + 0xff040000)
+//horizontal scaler phase step
+//Bit 28:0, 5.24 format
+#define GE2D_HSC_START_PHASE_STEP ((0x00bc << 2) + 0xff040000)
+//phase slope
+//Bit 24:0, bit 24 signed bit
+#define GE2D_HSC_PHASE_SLOPE ((0x00bd << 2) + 0xff040000)
+//Bit 30:29, horizontal repeat line0 number
+//Bit 23:0, horizontal scaler initial phase
+#define GE2D_HSC_INI_CTRL ((0x00be << 2) + 0xff040000)
+//Bit 31:24, advance number in this round, if horizontal scaler is working on dividing mode
+//Bit 23:0, horizontal scaler advance phase in this round, if horizontal scaler is working on dividing mode
+#define GE2D_HSC_ADV_CTRL ((0x00bf << 2) + 0xff040000)
+//Bit 30, vertical nearest mode enable, must set vt_bank_length = 4
+//Bit 29, horizontal nearest mode enable, must set hz_bank_length = 4
+//Bit 28, horizontal scaler dividing mode enable
+//Bit 27:15, horizontal dividing length, if bit 28 is enable
+//Bit 14, pre horizontal scaler enable
+//Bit 13, pre vertical scale enable
+//Bit 12, vertical scale enable
+//Bit 11, horizontal scaler enable
+//Bit 9, if true, treat horizontal repeat line number(GE2D_HSC_INI_CTRL bit 30:29) as repeating line,
+// otherwise using treat horizontal repeat line number as minus line number.
+//Bit 8, if true, treat vertical repeat line number(GE2D_VSC_INI_CTRL bit 30:29) as repeating line,
+// otherwise using treat vertical repeat line number as minus line number.
+//Bit 7, if true, always use phase0 in vertical scaler
+//Bit 6:4, vertical scaler bank length
+//Bit 3, if true, always use phase0 in horizontal scaler
+//Bit 2:0, horizontal scaler bank length
+#define GE2D_SC_MISC_CTRL ((0x00c0 << 2) + 0xff040000)
+//Read only
+//vertical scaler next round integer pixel pointer, signed data
+//Bit 13:0
+#define GE2D_VSC_NRND_POINT ((0x00c1 << 2) + 0xff040000)
+//Read only
+//vertical scaler next round phase
+//bit 23:0
+#define GE2D_VSC_NRND_PHASE ((0x00c2 << 2) + 0xff040000)
+//Read only
+//horizontal scaler next round integer pixel pointer, signed data
+//Bit 13:0
+#define GE2D_HSC_NRND_POINT ((0x00c3 << 2) + 0xff040000)
+//Read only
+//horizontal scaler next round phase
+//bit 23:0
+#define GE2D_HSC_NRND_PHASE ((0x00c4 << 2) + 0xff040000)
+//
+//Bit 28:20, pre_offset0
+//Bit 18:10, pre_offset1
+//Bit 8:0, pre_offset2
+#define GE2D_MATRIX_PRE_OFFSET ((0x00c5 << 2) + 0xff040000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define GE2D_MATRIX_COEF00_01 ((0x00c6 << 2) + 0xff040000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define GE2D_MATRIX_COEF02_10 ((0x00c7 << 2) + 0xff040000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define GE2D_MATRIX_COEF11_12 ((0x00c8 << 2) + 0xff040000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define GE2D_MATRIX_COEF20_21 ((0x00c9 << 2) + 0xff040000)
+//Bit 28:16 coef22
+//Bit 7 input y/cb/cr saturation enable
+//Bit 0 conversion matrix enable
+#define GE2D_MATRIX_COEF22_CTRL ((0x00ca << 2) + 0xff040000)
+//Bit 28:20, offset0
+//Bit 18:10, offset1
+//Bit 8:0, offset2
+#define GE2D_MATRIX_OFFSET ((0x00cb << 2) + 0xff040000)
+//Bit 26:25, SRC1 color multiplier alpha selection
+// if 00, Cs = Csr
+// if 01, Cs = Csr * Asr * Ag (if source is not premultiplied)
+// if 10, Cs = Csr * Ag (if source is premultipied)
+//Bit 24 SRC2 color multiplier alpha selection
+// if 0, no multiplier, Cd = Cdr, otherwise, Cd = Cdr * Ad.
+//Bit 22:12 ALU color operation
+// bit10:8 Blending Mode Parameter
+// 3'b000: ADD Cs*Fs + Cd*Fd
+// 3'b001: SUBTRACT Cs*Fs - Cd*Fd
+// 3'b010: REVERSE SUBTRACT Cd*Fd - Cs*Fs
+// 3'b011: MIN min(Cs*Fs, Cd*Fd)
+// 3'b100: MAX max(Cs*Fs, Cd*Fd)
+// 3'b101: LOGIC OP Cs op Cd
+// bit7:4 Source Color Blending Factor CFs
+// 4'b0000: ZERO 0
+// 4'b0001: ONE 1
+// 4'b0010: SRC_COLOR Cs(RGBs)
+// 4'b0011: ONE_MINUS_SRC_COLOR 1 - Cs(RGBs)
+// 4'b0100: DST_COLOR Cd(RGBd)
+// 4'b0101: ONE_MINUS_DST_COLOR 1 - Cd(RGBd)
+// 4'b0110: SRC_ALPHA As
+// 4'b0111: ONE_MINUS_SRC_ALPHA 1 - As
+// 4'b1000: DST_ALPHA Ad
+// 4'b1001: ONE_MINUS_DST_ALPHA 1 - Ad
+// 4'b1010: CONST_COLOR Cc(RGBc)
+// 4'b1011: ONE_MINUS_CONST_COLOR 1 - Cc(RGBc)
+// 4'b1100: CONST_ALPHA Ac
+// 4'b1101: ONE_MINUS_CONST_ALPHA 1 - Ac
+// 4'b1110: SRC_ALPHA_SATURATE min(As,1-Ad)
+// bit3:0 dest Color Blending Factor CFd, when bit10:8 != LOGIC OP
+// 4'b0000: ZERO 0
+// 4'b0001: ONE 1
+// 4'b0010: SRC_COLOR Cs(RGBs)
+// 4'b0011: ONE_MINUS_SRC_COLOR 1 - Cs(RGBs)
+// 4'b0100: DST_COLOR Cd(RGBd)
+// 4'b0101: ONE_MINUS_DST_COLOR 1 - Cd(RGBd)
+// 4'b0110: SRC_ALPHA As
+// 4'b0111: ONE_MINUS_SRC_ALPHA 1 - As
+// 4'b1000: DST_ALPHA Ad
+// 4'b1001: ONE_MINUS_DST_ALPHA 1 - Ad
+// 4'b1010: CONST_COLOR Cc(RGBc)
+// 4'b1011: ONE_MINUS_CONST_COLOR 1 - Cc(RGBc)
+// 4'b1100: CONST_ALPHA Ac
+// 4'b1101: ONE_MINUS_CONST_ALPHA 1 - Ac
+// 4'b1110: SRC_ALPHA_SATURATE min(As,1-Ad)
+// bit3:0 logic operations, when bit10:8 == LOGIC OP
+// 4'b0000: CLEAR 0
+// 4'b0001: COPY s
+// 4'b0010: NOOP d
+// 4'b0011: SET 1
+// 4'b0100: COPY_INVERT ~s
+// 4'b0101: INVERT ~d
+// 4'b0110: AND_REVERSE s & ~d
+// 4'b0111: OR_REVERSE s | ~d
+// 4'b1000: AND s & d
+// 4'b1001: OR s | d
+// 4'b1010: NAND ~(s & d)
+// 4'b1011: NOR ~(s | d)
+// 4'b1100: XOR s ^ d
+// 4'b1101: EQUIV ~(s ^ d)
+// 4'b1110: AND_INVERTED ~s & d
+// 4'b1111: OR_INVERTED ~s | d
+//Bit 10:0 ALU alpha operation
+// bit10:8 Blending Equation Math Operation
+// 3'b000: ADD As*Fs + Ad*Fd
+// 3'b001: SUBTRACT As*Fs - Ad*Fd
+// 3'b010: REVERSE SUBTRACT Ad*Fd - As*Fs
+// 3'b011: MIN min(As*Fs, Ad*Fd)
+// 3'b100: MAX max(As*Fs, Ad*Fd)
+// 3'b101: LOGIC OP As op Ad
+// bit7:4 Source alpha Blending Factor AFs
+// 4'b0000 0
+// 4'b0001 1
+// 4'b0010 As
+// 4'b0011 1 - As
+// 4'b0100 Ad
+// 4'b0101 1 - Ad
+// 4'b0110 Ac
+// 4'b0111 1 - Ac
+// .... reserved
+// bit3:0 Destination alpha Blending Factor AFd, when bit10:8 != LOGIC OP
+// 4'b0000 0
+// 4'b0001 1
+// 4'b0010 As
+// 4'b0011 1 - As
+// 4'b0100 Ad
+// 4'b0101 1 - Ad
+// 4'b0110 Ac
+// 4'b0111 1 - Ac
+// .... reserved
+// bit3:0 logic operations, when bit10:8 == LOGIC OP
+// 4'b0000: CLEAR 0
+// 4'b0001: COPY s
+// 4'b0010: NOOP d
+// 4'b0011: SET 1
+// 4'b0100: COPY_INVERT ~s
+// 4'b0101: INVERT ~d
+// 4'b0110: AND_REVERSE s & ~d
+// 4'b0111: OR_REVERSE s | ~d
+// 4'b1000: AND s & d
+// 4'b1001: OR s | d
+// 4'b1010: NAND ~(s & d)
+// 4'b1011: NOR ~(s | d)
+// 4'b1100: XOR s ^ d
+// 4'b1101: EQUIV ~(s ^ d)
+// 4'b1110: AND_INVERTED ~s & d
+// 4'b1111: OR_INVERTED ~s | d
+#define GE2D_ALU_OP_CTRL ((0x00cc << 2) + 0xff040000)
+//bit 31:0 (RGBA,YCBCRA)
+#define GE2D_ALU_CONST_COLOR ((0x00cd << 2) + 0xff040000)
+//SRC1 Key
+//31:0
+#define GE2D_SRC1_KEY ((0x00ce << 2) + 0xff040000)
+//SRC1 Key Mask
+//31:0
+#define GE2D_SRC1_KEY_MASK ((0x00cf << 2) + 0xff040000)
+//SRC2 Key
+//31:0
+#define GE2D_SRC2_KEY ((0x00d0 << 2) + 0xff040000)
+//SRC2 Key Mask
+//31:0
+#define GE2D_SRC2_KEY_MASK ((0x00d1 << 2) + 0xff040000)
+//Destination Bit Mask
+//31:0
+#define GE2D_DST_BITMASK ((0x00d2 << 2) + 0xff040000)
+//Bit 31 DP onoff mode, 0: on_counter means how many pixels will output before ge2d turns off
+// 1: on_counter means how many clocks will ge2d turn on before ge2d turns off
+//Bit 30:16 DP on counter
+//Bit 15 0: vd_format doesnt have onoff mode, 1: vd format has onoff mode
+//Bit 14:0 DP off counter
+#define GE2D_DP_ONOFF_CTRL ((0x00d3 << 2) + 0xff040000)
+//Because there are many coefficients used in the vertical filter and horizontal filters,
+//indirect access the coefficients of vertical filter and horizontal filter is used.
+//For vertical filter, there are 33x4 coefficients
+//For horizontal filter, there are 33x4 coefficients
+//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
+//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
+//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
+//Bit 8 type of index, 0: vertical coef
+// 1: horizontal coef
+//Bit 6:0 coef index
+#define GE2D_SCALE_COEF_IDX ((0x00d4 << 2) + 0xff040000)
+//coefficients for vertical filter and horizontal filter
+#define GE2D_SCALE_COEF ((0x00d5 << 2) + 0xff040000)
+//Bit 24 src2 alpha fill mode: together with GE2D_GEN_CTRL0[4](fill_mode), define what alpha values are used
+// for the area outside the clipping window. As below:
+// fill_mode=0, alpha_fill_mode=0 : use inner alpha, (or default_alpha if src data have no alpha values);
+// fill_mode=0, alpha_fill_mode=1 : use outside_alpha;
+// fill_mode=1, alpha_fill_mode=0 : use default_alpha;
+// fill_mode=1, alpha_fill_mode=1 : use outside_alpha.
+//Bit 23:16 src2 outside alpha
+//Bit 8 src1 alpha fill mode, refer to src2 alpha fill mode above.
+//Bit 7:0 src1 outside alpha
+#define GE2D_SRC_OUTSIDE_ALPHA ((0x00d6 << 2) + 0xff040000)
+//Bit 31 antiflick enable
+//Bit 24 1: alpha value for the first line use repeated alpha, 0: use bit 23:16 as the first line alpha
+//Bit 23:16 register value for the first line alpha when bit 24 is 1
+//Bit 8 1: alpha value for the last line use repeated alpha, 0: use bit 7:0 as the last line alpha
+//Bit 7:0 register value for the last line alpha when bit 8 is 1
+#define GE2D_ANTIFLICK_CTRL0 ((0x00d8 << 2) + 0xff040000)
+//Bit 25, rgb_sel, 1: antiflick RGBA, 0: antiflick YCbCrA
+//Bit 24, cbcr_en, 1: also filter cbcr in case of antiflicking YCbCrA, 0: no filter on cbcr in case of antiflicking YCbCrA
+//Bit 23:16, R mult coef for converting RGB to Y
+//Bit 15:8, G mult coef for converting RGB to Y
+//Bit 7:0, B mult coef for converting RGB to Y
+//Y = (R * y_r + G * y_g + B * y_b) / 256
+#define GE2D_ANTIFLICK_CTRL1 ((0x00d9 << 2) + 0xff040000)
+//Bit 31:24, Y threhold1, when 0<Y<=th1, use filter0;
+//Bit 23:16, color antiflick filter0 n3
+//Bit 15:8, color antiflick filter0 n2
+//Bit 7:0, color antiflick filter0 n1
+//Y = (line_up * n1 + line_center * n2 + line_dn * n3) / 128
+#define GE2D_ANTIFLICK_COLOR_FILT0 ((0x00da << 2) + 0xff040000)
+//Bit 31:24, Y threhold2, when th1<Y<=th2, use filter1;
+//Bit 23:16, color antiflick filter1 n3
+//Bit 15:8, color antiflick filter1 n2
+//Bit 7:0, color antiflick filter1 n1
+#define GE2D_ANTIFLICK_COLOR_FILT1 ((0x00db << 2) + 0xff040000)
+//Bit 31:24, Y threhold3, when th2<Y<=th3, use filter2; Y>th3, use filter3
+//Bit 23:16, color antiflick filter2 n3
+//Bit 15:8, color antiflick filter2 n2
+//Bit 7:0, color antiflick filter2 n1
+#define GE2D_ANTIFLICK_COLOR_FILT2 ((0x00dc << 2) + 0xff040000)
+//Bit 23:16, color antiflick filter3 n3
+//Bit 15:8, color antiflick filter3 n2
+//Bit 7:0, color antiflick filter3 n1
+#define GE2D_ANTIFLICK_COLOR_FILT3 ((0x00dd << 2) + 0xff040000)
+//Bit 31:24, Alpha threhold1, when 0<Alpha<=th1, use filter0;
+//Bit 23:16, Alpha antiflick filter0 n3
+//Bit 15:8, Alpha antiflick filter0 n2
+//Bit 7:0, Alpha antiflick filter0 n1
+//Alpha = (line_up * n1 + line_center * n2 + line_dn * n3) / 128
+#define GE2D_ANTIFLICK_ALPHA_FILT0 ((0x00de << 2) + 0xff040000)
+//Bit 31:24, Alpha threhold2, when th1<Alpha<=th2, use filter1;
+//Bit 23:16, Alpha antiflick filter1 n3
+//Bit 15:8, Alpha antiflick filter1 n2
+//Bit 7:0, Alpha antiflick filter1 n1
+#define GE2D_ANTIFLICK_ALPHA_FILT1 ((0x00df << 2) + 0xff040000)
+//Bit 31:24, Alpha threhold3, when th2<Alpha<=th3, use filter2; Alpha>th3, use filter3
+//Bit 23:16, Alpha antiflick filter2 n3
+//Bit 15:8, Alpha antiflick filter2 n2
+//Bit 7:0, Alpha antiflick filter2 n1
+#define GE2D_ANTIFLICK_ALPHA_FILT2 ((0x00e0 << 2) + 0xff040000)
+//Bit 23:16, Alpha antiflick filter3 n3
+//Bit 15:8, Alpha antiflick filter3 n2
+//Bit 7:0, Alpha antiflick filter3 n1
+#define GE2D_ANTIFLICK_ALPHA_FILT3 ((0x00e1 << 2) + 0xff040000)
+//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset)
+//Bit 30:22 din_offset (signed data)
+//Bit 21:14 map_coef (unsigned data)
+//Bit 13:10 map_sr (unsigned data)
+//Bit 9:1 dout_offset (signed data)
+//Bit 0 enable
+#define GE2D_SRC1_RANGE_MAP_Y_CTRL ((0x00e3 << 2) + 0xff040000)
+//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset)
+//Bit 30:22 din_offset (signed data)
+//Bit 21:14 map_coef (unsigned data)
+//Bit 13:10 map_sr (unsigned data)
+//Bit 9:1 dout_offset (signed data)
+//Bit 0 enable
+#define GE2D_SRC1_RANGE_MAP_CB_CTRL ((0x00e4 << 2) + 0xff040000)
+//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset)
+//Bit 30:22 din_offset (signed data)
+//Bit 21:14 map_coef (unsigned data)
+//Bit 13:10 map_sr (unsigned data)
+//Bit 9:1 dout_offset (signed data)
+//Bit 0 enable
+#define GE2D_SRC1_RANGE_MAP_CR_CTRL ((0x00e5 << 2) + 0xff040000)
+//Bit 21:16 src1 prearbitor burst number
+//Bit 13:8 src2 prearbitor burst number
+//Bit 5:0 dst prearbitor burst number
+#define GE2D_ARB_BURST_NUM ((0x00e6 << 2) + 0xff040000)
+//each 6bit ID, high 4bit are thread ID, low 2bits are the token
+//Bit 21:16 src1 ID
+//Bit 13:8 src2 ID
+//Bit 5:0 dst ID
+#define GE2D_TID_TOKEN ((0x00e7 << 2) + 0xff040000)
+//Bit 31:28 dst2_bytemask_val. 1-bit mask for each byte (8-bit). Applicable only if both dst_bitmask_en=1 and dst_bytemask_only=1.
+//Bit 27:26, dst2 picture struct, 00: frame, 10:top, 11: bottom
+//Bit 25:24, dst2 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 22:19 dst2 color_map
+// dst2_format=0 : output 8-bit;
+// dst2_format=1, dst2_color_map=1: output 16-bit YCbCr 655;
+// dst2_format=1, dst2_color_map=2: output 16-bit YCbCr 844;
+// dst2_format=1, dst2_color_map=3: output 16-bit YCbCrA 6442;
+// dst2_format=1, dst2_color_map=4: output 16-bit YCbCrA 4444;
+// dst2_format=1, dst2_color_map=5: output 16-bit YCbCr 565;
+// dst2_format=1, dst2_color_map=6: output 16-bit AYCbCr 4444;
+// dst2_format=1, dst2_color_map=7: output 16-bit AYCbCr 1555;
+// dst2_format=1, dst2_color_map=8: output 16-bit YCbCrA 4642;
+// dst2_format=1, dst2_color_map=9: output 16-bit CbCr 88;
+// dst2_format=1, dst2_color_map=10:output 16-bit CrCb 88;
+// dst2_format=2, dst2_color_map=0: output 24-bit YCbCr 888;
+// dst2_format=2, dst2_color_map=1: output 24-bit YCbCrA 5658;
+// dst2_format=2, dst2_color_map=2: output 24-bit AYCbCr 8565;
+// dst2_format=2, dst2_color_map=3: output 24-bit YCbCrA 6666;
+// dst2_format=2, dst2_color_map=4: output 24-bit AYCbCr 6666;
+// dst2_format=2, dst2_color_map=5: output 24-bit CrCbY 888;
+// dst2_format=3, dst2_color_map=0: output 32-bit YCbCrA 8888;
+// dst2_format=3, dst2_color_map=1: output 32-bit AYCbCr 8888;
+// dst2_format=3, dst2_color_map=2: output 32-bit ACrCbY 8888;
+// dst2_format=3, dst2_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 17:16 dst2_format, 00: 8bit, 01:16bit, 10:24bit, 11: 32bit
+//Bit 15 reserved
+//Bit 14 dst2_color_round_mode, 0: truncate, 1: + 0.5 rounding
+//Bit 13:12, dst2_x_discard_mode. 00: no discard; 10=discard even x; 11=discard odd x. Note: x is post reverse/rotation.
+//Bit 11:10, dst2_y_discard_mode. 00: no discard; 10=discard even y; 11=discard odd y. Note: y is post reverse/rotation.
+//Bit 9 reserved
+//Bit 8, dst2_enable. 0: disable dst2 (default); 1=enable dst2.
+//Bit 7: 6 reserved
+//Bit 5: 4, dst1_x_discard_mode. 00: no discard; 10=discard even x; 11=discard odd x. Note: x is post reverse/rotation.
+//Bit 3: 2, dst1_y_discard_mode. 00: no discard; 10=discard even y; 11=discard odd y. Note: y is post reverse/rotation.
+//Bit 1 reserved
+//Bit 0, dst1_enable. 0: disable dst1; 1=enable dst1 (default).
+#define GE2D_GEN_CTRL3 ((0x00e8 << 2) + 0xff040000)
+//Read only
+// Bit 13:0 ge2d_dst2_status, for debug only
+#define GE2D_STATUS2 ((0x00e9 << 2) + 0xff040000)
+//Bit 27:26 src1 Y fifo size control, 00: 512, 01: 256, 10: 128 11: 96
+//Bit 25:24 src2 fifo size control, 00: 512, 01: 256, 10: 128 11: 96
+//Bit 23:22 dst1 fifo size control, 00: 512, 01: 256, 10: 128 11: 64
+//Bit 21:20 dst2 fifo size control, 00: 512, 01: 256, 10: 128 11: 64
+//Bit 19:18, dst1 fifo burst control, 00: 24x64, 01: 32x64, 10: 48x64, 11:64x64
+//Bit 17:16, dst2 fifo burst control, 00: 24x64, 01: 32x64, 10: 48x64, 11:64x64
+//Bit 15:1, top_wrap_ctrl
+//bit 0, if true, disable bug fix about the dp_out_done/scale_out_done(test1823) hang issue when scaling down ratio is high.
+#define GE2D_GEN_CTRL4 ((0x00ea << 2) + 0xff040000)
+#define GE2D_GCLK_CTRL0 ((0x00ef << 2) + 0xff040000)
+#define GE2D_GCLK_CTRL1 ((0x00f0 << 2) + 0xff040000)
+#define GE2D_GEN_CTRL5 ((0x00f1 << 2) + 0xff040000)
+//Bit 28:20, pre_offset0
+//Bit 18:10, pre_offset1
+//Bit 8:0, pre_offset2
+#define GE2D_MATRIX2_PRE_OFFSET ((0x0090 << 2) + 0xff040000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define GE2D_MATRIX2_COEF00_01 ((0x0091 << 2) + 0xff040000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define GE2D_MATRIX2_COEF02_10 ((0x0092 << 2) + 0xff040000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define GE2D_MATRIX2_COEF11_12 ((0x0093 << 2) + 0xff040000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define GE2D_MATRIX2_COEF20_21 ((0x0094 << 2) + 0xff040000)
+//Bit 28:16 coef22
+//Bit 7 input y/cb/cr saturation enable
+//Bit 0 conversion matrix enable
+#define GE2D_MATRIX2_COEF22_CTRL ((0x0095 << 2) + 0xff040000)
+//Bit 28:20, offset0
+//Bit 18:10, offset1
+//Bit 8:0, offset2
+#define GE2D_MATRIX2_OFFSET ((0x0096 << 2) + 0xff040000)
+//Bit 19:0, src2 stride size in 64bits
+//
+//
+//Bit 28:20, pre_offset0
+//Bit 18:10, pre_offset1
+//Bit 8:0, pre_offset2
+#define GE2D_MATRIX3_PRE_OFFSET ((0x0097 << 2) + 0xff040000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define GE2D_MATRIX3_COEF00_01 ((0x0098 << 2) + 0xff040000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define GE2D_MATRIX3_COEF02_10 ((0x0099 << 2) + 0xff040000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define GE2D_MATRIX3_COEF11_12 ((0x009a << 2) + 0xff040000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define GE2D_MATRIX3_COEF20_21 ((0x009b << 2) + 0xff040000)
+//Bit 28:16 coef22
+//Bit 7 input y/cb/cr saturation enable
+//Bit 0 conversion matrix enable
+#define GE2D_MATRIX3_COEF22_CTRL ((0x009c << 2) + 0xff040000)
+//Bit 28:20, offset0
+//Bit 18:10, offset1
+//Bit 8:0, offset2
+#define GE2D_MATRIX3_OFFSET ((0x009d << 2) + 0xff040000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: ./ge2d_regs.h
+//
+//
+// Reading file: ./parser_regs.h
+//
+//
+//***************************************************************************
+// Title: parser.h
+//
+// Author: chong.gu
+//
+// Created: 17:15:11 06/08/2019
+//
+// Description:
+//
+// Note:
+//
+// History:
+//
+//***************************************************************************
+//-----------------------------------------------------------
+// PARSER
+//-----------------------------------------------------------
+// -----------------------------------------------
+// REG_BASE: PARSER_PCBUS_BASE = 0x38
+// -----------------------------------------------
+// bit 31:8 -- es_pack_size
+// bit 7:6 -- es_type 00-Video, 01-Audio, 10-Subtitle
+// bit 5 -- es_write
+// bit 4 -- es_passthrough
+// bit 3 -- insert_before_es_write
+// bit 2 -- discard_cmd
+// bit 1 -- search_cmd
+// bit 0 -- Parser Busy
+#define PARSER_CONTROL ((0x3860 << 2) + 0xfdf00000)
+// Write
+// bit 31:0 begin address for parser fetch
+// Read
+// 32 bit current fetch address
+#define PARSER_FETCH_ADDR ((0x3861 << 2) + 0xfdf00000)
+// Write
+// bit 31 circle buffer indicator
+// bit 30 check_buffer_stop_addr
+// bit 29:27 fetch endian
+// bit 26:0 buffer size ( Bytes )
+// Special command:
+// when bit 26:0 == 27'h0
+// then bit 29 -- stream_passthrough_enable
+// bit 28:27 -- stream_passthrough_type
+// Read
+// 6:5 cmd_rd_ptr
+// 4:3 cmd_wr_ptr
+// 2:0 cmd_number
+#define PARSER_FETCH_CMD ((0x3862 << 2) + 0xfdf00000)
+// 31:0 stop_fetch_addr
+#define PARSER_FETCH_STOP_ADDR ((0x3863 << 2) + 0xfdf00000)
+// 31:0 stop_fetch_addr - current_write_addr // read only
+#define PARSER_FETCH_LEVEL ((0x3864 << 2) + 0xfdf00000)
+// bit 31 - fetch_dma_urgent
+// bit 30 - stream_dma_urgent
+// bit 29 - force_pfifo_ren
+// bit 28 - pfifo_peak_enable
+// bit 27 - enable_free_clk_parser_reg
+// bit 26 -
+// bit 25:24 - parser_src_sel (00 - fetch, 01 - aux1, 10 - aux2 11 - aux3)
+// bit 23:16 - pfifo_empty_count
+// bit 15:12 - max_es_write_cycle (x16x64bits)
+// 11:10 - start code width ( 00-8bits, 01-16bits, 10-24bits, 11-32bits )
+// 9:8 - pfifo data access width ( 00-8bits, 01-16bits, 10-24bits, 11-32bits )
+// 7:0 - empty room for fetch data ( max_fetch_cycle ) x64 bits
+#define PARSER_CONFIG ((0x3865 << 2) + 0xfdf00000)
+// bit 24:16 -- pfifo_level
+// bit 9:0 -- point to byte address
+#define PFIFO_WR_PTR ((0x3866 << 2) + 0xfdf00000)
+// bit 9:0 -- point to byte address
+#define PFIFO_RD_PTR ((0x3867 << 2) + 0xfdf00000)
+// bit 31:0 -- 8/16/24/32 bits data acording to pfifo_data_width
+#define PFIFO_DATA ((0x3868 << 2) + 0xfdf00000)
+// bit 31:0 -- parser search pattern
+#define PARSER_SEARCH_PATTERN ((0x3869 << 2) + 0xfdf00000)
+// bit 31:0 -- parser search mask ( 0 - disable bit match test )
+#define PARSER_SEARCH_MASK ((0x386a << 2) + 0xfdf00000)
+// bit 31:16 -- parser_int_disable_count
+// bit 15:8 -- Parser interrupt enable for host cpu
+// bit 7:0 -- Parser interrupt enable for Amrisc
+#define PARSER_INT_ENABLE ((0x386b << 2) + 0xfdf00000)
+// Bit 7 -- fetch_cmd_finished
+// Bit 6:5 -- reserved
+// Bit 4 -- parse finished
+// Bit 3 -- discard finished
+// Bit 2 -- insert zero finished
+// Bit 1 -- Action Finished Except Search Start Code
+// Bit 0 -- Search match interrupt (StartCode found)
+// Read 7:0 int status
+// Write will clear (bit based)
+#define PARSER_INT_STATUS ((0x386c << 2) + 0xfdf00000)
+// 15 - SCR_32_READ_OUT (Read Only)
+// 14 - SCR_32_data_valid
+// 13 - SCR_32_data
+// 12 - SCR_count_en
+// 11:0 - SCR90K_DIV
+#define PARSER_SCR_CTL ((0x386d << 2) + 0xfdf00000)
+// bit 31:0 SCR value
+#define PARSER_SCR ((0x386e << 2) + 0xfdf00000)
+// bit 31:24 -- insert_loop_number
+// bit 23:21 --
+// bit 20:16 -- insert_byte_number
+// bit 15:0 -- discard number
+#define PARSER_PARAMETER ((0x386f << 2) + 0xfdf00000)
+// bit 31:0 -- insert data // write only
+// write to PARSER_CONTROL will reset the write position
+// continous write to this address can write upto 16 bytes
+#define PARSER_INSERT_DATA ((0x3870 << 2) + 0xfdf00000)
+// Bit 31:24 -- Reserved Stream_ID
+// Bit 23:16 -- Sub Stream_ID
+// Bit 15:8 -- Audio Stream_ID
+// Bit 7:0 -- Video Stream_ID
+#define VAS_STREAM_ID ((0x3871 << 2) + 0xfdf00000)
+// Bit 31:0 -- VIDEO_DTS
+#define VIDEO_DTS ((0x3872 << 2) + 0xfdf00000)
+// Bit 31:0 -- VIDEO_PTS
+#define VIDEO_PTS ((0x3873 << 2) + 0xfdf00000)
+// Bit 31:0 -- VIDEO_PTS_DTS_WR_PTR
+#define VIDEO_PTS_DTS_WR_PTR ((0x3874 << 2) + 0xfdf00000)
+// Bit 31:0 -- AUDIO_PTS
+#define AUDIO_PTS ((0x3875 << 2) + 0xfdf00000)
+// Bit 31:0 -- AUDIO_PTS_WR_PTR
+#define AUDIO_PTS_WR_PTR ((0x3876 << 2) + 0xfdf00000)
+// bit 31:20 -- stream_es_count ( Read Only)
+// bit 19 -- req_pending ( parser ddr_A_fifo ) (Read Only)
+// bit 18 -- stream_es_passthrough_enable
+// bit 17:16 -- stream_es_passthrough_type
+// bit 15:13 -- VIDEO2 Ees_write Endian
+// bit 12 -- VIDEO2 using manual read point
+// bit 11:9 -- SUB Ees_write Endian
+// bit 8 -- SUB using manual read point
+// bit 7:5 -- AUDIO Ees_write Endian
+// bit 4 -- AUDIO using manual read point
+// bit 3:1 -- VIDEO Ees_write Endian
+// bit 0 -- VIDEO using manual read point
+#define PARSER_ES_CONTROL ((0x3877 << 2) + 0xfdf00000)
+// Bit 31:0 PFIFO_MONITOR
+#define PFIFO_MONITOR ((0x3878 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_VIDEO DDR Interface
+// --------------------------------------------
+// The PARSER_VIDEO start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_VIDEO_START_PTR ((0x3880 << 2) + 0xfdf00000)
+#define PARSER_VIDEO_END_PTR ((0x3881 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_VIDEO Buffer Level Manager
+// --------------------------------------------
+#define PARSER_VIDEO_WP ((0x3882 << 2) + 0xfdf00000)
+#define PARSER_VIDEO_RP ((0x3883 << 2) + 0xfdf00000)
+#define PARSER_VIDEO_HOLE ((0x3884 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_AUDIO DDR Interface
+// --------------------------------------------
+// The PARSER_AUDIO start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_AUDIO_START_PTR ((0x3885 << 2) + 0xfdf00000)
+#define PARSER_AUDIO_END_PTR ((0x3886 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_AUDIO Buffer Level Manager
+// --------------------------------------------
+#define PARSER_AUDIO_WP ((0x3887 << 2) + 0xfdf00000)
+#define PARSER_AUDIO_RP ((0x3888 << 2) + 0xfdf00000)
+#define PARSER_AUDIO_HOLE ((0x3889 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_SUB DDR Interface
+// --------------------------------------------
+// The PARSER_SUB start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_SUB_START_PTR ((0x388a << 2) + 0xfdf00000)
+#define PARSER_SUB_END_PTR ((0x388b << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_SUB Buffer Level Manager
+// --------------------------------------------
+#define PARSER_SUB_WP ((0x388c << 2) + 0xfdf00000)
+#define PARSER_SUB_RP ((0x388d << 2) + 0xfdf00000)
+#define PARSER_SUB_HOLE ((0x388e << 2) + 0xfdf00000)
+// Bit[31] dma_busy
+// Bit[30] cur_fetch_or_es_write
+// Bit[29:28] reserved
+// Bit[27:24] fetch_status
+// Bit[23:0] buffer_cycles_left
+#define PARSER_FETCH_INFO ((0x388f << 2) + 0xfdf00000)
+// Bit[31:28] ctl_status
+// Bit[27:24] insert_byte_offset
+// Bit[23:0] es_pack_left_cycle
+#define PARSER_STATUS ((0x3890 << 2) + 0xfdf00000)
+// Bit [31:16] AUDIO_wrap_count
+// Bit [15:0] VIDEO_wrap_count
+#define PARSER_AV_WRAP_COUNT ((0x3891 << 2) + 0xfdf00000)
+// bit[29:24] A_brst_num_parser
+// bit[21:16] A_id_parser
+// bit[11:0] wrrsp_count_parser
+#define WRRSP_PARSER ((0x3892 << 2) + 0xfdf00000)
+// `define CSS_cmd 12'h200 // address of css command and indirect register
+// `define CSS_cntl 12'h201 // css control register
+// `define CSS_data 12'h202 // indirect register
+// `define CSS_id1_data 12'h203 // ID data for the first and second bytes
+// `define CSS_id2_data 12'h204 // ID data for the third and fourth bytes
+//CPPM registers
+// `define CPPM_IFIFO_CTRL 12'h210 //CPPM input FIFO control
+// `define CPPM_C2BC_KEY 12'h211 //CPPM C2 Block Cipher Key register
+// `define CPPM_C2BC_DIN 12'h212 //CPPM C2 Block Cipher data input register
+// `define CPPM_C2BC_DOUT 12'h213 //CPPM C2 Block Cipher data result register
+// `define CPPM_CMD 12'h214 //CPPM command and control register
+// `define CPPM_CTRL_STATUS 12'h215 //CPPM control status, mainly for debug
+// `define CPPM_IFIFO_DATA 12'h216 //CPPM input FIFO data pop port, just for debug
+// --------------------------------------------
+// PARSER_VIDEO2 DDR Interface
+// --------------------------------------------
+// The PARSER_VIDEO2 start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_VIDEO2_START_PTR ((0x3893 << 2) + 0xfdf00000)
+#define PARSER_VIDEO2_END_PTR ((0x3894 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_VIDEO2 Buffer Level Manager
+// --------------------------------------------
+#define PARSER_VIDEO2_WP ((0x3895 << 2) + 0xfdf00000)
+#define PARSER_VIDEO2_RP ((0x3896 << 2) + 0xfdf00000)
+#define PARSER_VIDEO2_HOLE ((0x3897 << 2) + 0xfdf00000)
+// Bit [31:16] AUDIO_wrap_count
+// Bit [15:0] VIDEO2_wrap_count
+#define PARSER_AV2_WRAP_COUNT ((0x3898 << 2) + 0xfdf00000)
+//-----------------------------------------------------------
+// PARSER_B
+//-----------------------------------------------------------
+// -----------------------------------------------
+// REG_BASE: PARSER_B_PCBUS_BASE = 0x11
+// -----------------------------------------------
+#define PARSER_B_PARSER_CONTROL ((0x1160 << 2) + 0xfdf00000)
+// Write
+// bit 31:0 begin address for parser fetch
+// Read
+// 32 bit current fetch address
+#define PARSER_B_PARSER_FETCH_ADDR ((0x1161 << 2) + 0xfdf00000)
+// Write
+// bit 31 circle buffer indicator
+// bit 30 check_buffer_stop_addr
+// bit 29:27 fetch endian
+// bit 26:0 buffer size ( Bytes )
+// Special command:
+// when bit 26:0 == 27'h0
+// then bit 29 -- stream_passthrough_enable
+// bit 28:27 -- stream_passthrough_type
+// Read
+// 6:5 cmd_rd_ptr
+// 4:3 cmd_wr_ptr
+// 2:0 cmd_number
+#define PARSER_B_PARSER_FETCH_CMD ((0x1162 << 2) + 0xfdf00000)
+// 31:0 stop_fetch_addr
+#define PARSER_B_PARSER_FETCH_STOP_ADDR ((0x1163 << 2) + 0xfdf00000)
+// 31:0 stop_fetch_addr - current_write_addr // read only
+#define PARSER_B_PARSER_FETCH_LEVEL ((0x1164 << 2) + 0xfdf00000)
+// bit 31 - fetch_dma_urgent
+// bit 30 - stream_dma_urgent
+// bit 29 - force_pfifo_ren
+// bit 28 - pfifo_peak_enable
+// bit 27 - enable_free_clk_parser_reg
+// bit 26 -
+// bit 25:24 - parser_src_sel (00 - fetch, 01 - aux1, 10 - aux2 11 - aux3)
+// bit 23:16 - pfifo_empty_count
+// bit 15:12 - max_es_write_cycle (x16x64bits)
+// 11:10 - start code width ( 00-8bits, 01-16bits, 10-24bits, 11-32bits )
+// 9:8 - pfifo data access width ( 00-8bits, 01-16bits, 10-24bits, 11-32bits )
+// 7:0 - empty room for fetch data ( max_fetch_cycle ) x64 bits
+#define PARSER_B_PARSER_CONFIG ((0x1165 << 2) + 0xfdf00000)
+// bit 24:16 -- pfifo_level
+// bit 9:0 -- point to byte address
+#define PARSER_B_PFIFO_WR_PTR ((0x1166 << 2) + 0xfdf00000)
+// bit 9:0 -- point to byte address
+#define PARSER_B_PFIFO_RD_PTR ((0x1167 << 2) + 0xfdf00000)
+// bit 31:0 -- 8/16/24/32 bits data acording to pfifo_data_width
+#define PARSER_B_PFIFO_DATA ((0x1168 << 2) + 0xfdf00000)
+// bit 31:0 -- parser search pattern
+#define PARSER_B_PARSER_SEARCH_PATTERN ((0x1169 << 2) + 0xfdf00000)
+// bit 31:0 -- parser search mask ( 0 - disable bit match test )
+#define PARSER_B_PARSER_SEARCH_MASK ((0x116a << 2) + 0xfdf00000)
+// bit 31:16 -- parser_int_disable_count
+// bit 15:8 -- Parser interrupt enable for host cpu
+// bit 7:0 -- Parser interrupt enable for Amrisc
+#define PARSER_B_PARSER_INT_ENABLE ((0x116b << 2) + 0xfdf00000)
+// Bit 7 -- fetch_cmd_finished
+// Bit 6:5 -- reserved
+// Bit 4 -- parse finished
+// Bit 3 -- discard finished
+// Bit 2 -- insert zero finished
+// Bit 1 -- Action Finished Except Search Start Code
+// Bit 0 -- Search match interrupt (StartCode found)
+// Read 7:0 int status
+// Write will clear (bit based)
+#define PARSER_B_PARSER_INT_STATUS ((0x116c << 2) + 0xfdf00000)
+// 15 - SCR_32_READ_OUT (Read Only)
+// 14 - SCR_32_data_valid
+// 13 - SCR_32_data
+// 12 - SCR_count_en
+// 11:0 - SCR90K_DIV
+#define PARSER_B_PARSER_SCR_CTL ((0x116d << 2) + 0xfdf00000)
+// bit 31:0 SCR value
+#define PARSER_B_PARSER_SCR ((0x116e << 2) + 0xfdf00000)
+// bit 31:24 -- insert_loop_number
+// bit 23:21 --
+// bit 20:16 -- insert_byte_number
+// bit 15:0 -- discard number
+#define PARSER_B_PARSER_PARAMETER ((0x116f << 2) + 0xfdf00000)
+// bit 31:0 -- insert data // write only
+// write to PARSER_CONTROL will reset the write position
+// continous write to this address can write upto 16 bytes
+#define PARSER_B_PARSER_INSERT_DATA ((0x1170 << 2) + 0xfdf00000)
+// Bit 31:24 -- Reserved Stream_ID
+// Bit 23:16 -- Sub Stream_ID
+// Bit 15:8 -- Audio Stream_ID
+// Bit 7:0 -- Video Stream_ID
+#define PARSER_B_VAS_STREAM_ID ((0x1171 << 2) + 0xfdf00000)
+// Bit 31:0 -- VIDEO_DTS
+#define PARSER_B_VIDEO_DTS ((0x1172 << 2) + 0xfdf00000)
+// Bit 31:0 -- VIDEO_PTS
+#define PARSER_B_VIDEO_PTS ((0x1173 << 2) + 0xfdf00000)
+// Bit 31:0 -- VIDEO_PTS_DTS_WR_PTR
+#define PARSER_B_VIDEO_PTS_DTS_WR_PTR ((0x1174 << 2) + 0xfdf00000)
+// Bit 31:0 -- AUDIO_PTS
+#define PARSER_B_AUDIO_PTS ((0x1175 << 2) + 0xfdf00000)
+// Bit 31:0 -- AUDIO_PTS_WR_PTR
+#define PARSER_B_AUDIO_PTS_WR_PTR ((0x1176 << 2) + 0xfdf00000)
+// bit 31:20 -- stream_es_count ( Read Only)
+// bit 19 -- req_pending ( parser ddr_A_fifo ) (Read Only)
+// bit 18 -- stream_es_passthrough_enable
+// bit 17:16 -- stream_es_passthrough_type
+// bit 15:13 -- VIDEO2 Ees_write Endian
+// bit 12 -- VIDEO2 using manual read point
+// bit 11:9 -- SUB Ees_write Endian
+// bit 8 -- SUB using manual read point
+// bit 7:5 -- AUDIO Ees_write Endian
+// bit 4 -- AUDIO using manual read point
+// bit 3:1 -- VIDEO Ees_write Endian
+// bit 0 -- VIDEO using manual read point
+#define PARSER_B_PARSER_ES_CONTROL ((0x1177 << 2) + 0xfdf00000)
+// Bit 31:0 PFIFO_MONITOR
+#define PARSER_B_PFIFO_MONITOR ((0x1178 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_VIDEO DDR Interface
+// --------------------------------------------
+// The PARSER_VIDEO start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_B_PARSER_VIDEO_START_PTR ((0x1180 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_VIDEO_END_PTR ((0x1181 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_VIDEO Buffer Level Manager
+// --------------------------------------------
+#define PARSER_B_PARSER_VIDEO_WP ((0x1182 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_VIDEO_RP ((0x1183 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_VIDEO_HOLE ((0x1184 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_AUDIO DDR Interface
+// --------------------------------------------
+// The PARSER_AUDIO start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_B_PARSER_AUDIO_START_PTR ((0x1185 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_AUDIO_END_PTR ((0x1186 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_AUDIO Buffer Level Manager
+// --------------------------------------------
+#define PARSER_B_PARSER_AUDIO_WP ((0x1187 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_AUDIO_RP ((0x1188 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_AUDIO_HOLE ((0x1189 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_SUB DDR Interface
+// --------------------------------------------
+// The PARSER_SUB start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_B_PARSER_SUB_START_PTR ((0x118a << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_SUB_END_PTR ((0x118b << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_SUB Buffer Level Manager
+// --------------------------------------------
+#define PARSER_B_PARSER_SUB_WP ((0x118c << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_SUB_RP ((0x118d << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_SUB_HOLE ((0x118e << 2) + 0xfdf00000)
+// Bit[31] dma_busy
+// Bit[30] cur_fetch_or_es_write
+// Bit[29:28] reserved
+// Bit[27:24] fetch_status
+// Bit[23:0] buffer_cycles_left
+#define PARSER_B_PARSER_FETCH_INFO ((0x118f << 2) + 0xfdf00000)
+// Bit[31:28] ctl_status
+// Bit[27:24] insert_byte_offset
+// Bit[23:0] es_pack_left_cycle
+#define PARSER_B_PARSER_STATUS ((0x1190 << 2) + 0xfdf00000)
+// Bit [31:16] AUDIO_wrap_count
+// Bit [15:0] VIDEO_wrap_count
+#define PARSER_B_PARSER_AV_WRAP_COUNT ((0x1191 << 2) + 0xfdf00000)
+// bit[29:24] A_brst_num_parser
+// bit[21:16] A_id_parser
+// bit[11:0] wrrsp_count_parser
+#define PARSER_B_WRRSP_PARSER ((0x1192 << 2) + 0xfdf00000)
+// `define CSS_cmd 12'h200 // address of css command and indirect register
+// `define CSS_cntl 12'h201 // css control register
+// `define CSS_data 12'h202 // indirect register
+// `define CSS_id1_data 12'h203 // ID data for the first and second bytes
+// `define CSS_id2_data 12'h204 // ID data for the third and fourth bytes
+//CPPM registers
+// `define CPPM_IFIFO_CTRL 12'h210 //CPPM input FIFO control
+// `define CPPM_C2BC_KEY 12'h211 //CPPM C2 Block Cipher Key register
+// `define CPPM_C2BC_DIN 12'h212 //CPPM C2 Block Cipher data input register
+// `define CPPM_C2BC_DOUT 12'h213 //CPPM C2 Block Cipher data result register
+// `define CPPM_CMD 12'h214 //CPPM command and control register
+// `define CPPM_CTRL_STATUS 12'h215 //CPPM control status, mainly for debug
+// `define CPPM_IFIFO_DATA 12'h216 //CPPM input FIFO data pop port, just for debug
+// --------------------------------------------
+// PARSER_VIDEO2 DDR Interface
+// --------------------------------------------
+// The PARSER_VIDEO2 start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_B_PARSER_VIDEO2_START_PTR ((0x1193 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_VIDEO2_END_PTR ((0x1194 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_VIDEO2 Buffer Level Manager
+// --------------------------------------------
+#define PARSER_B_PARSER_VIDEO2_WP ((0x1195 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_VIDEO2_RP ((0x1196 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_VIDEO2_HOLE ((0x1197 << 2) + 0xfdf00000)
+// Bit [31:16] AUDIO_wrap_count
+// Bit [15:0] VIDEO2_wrap_count
+#define PARSER_B_PARSER_AV2_WRAP_COUNT ((0x1198 << 2) + 0xfdf00000)
+
+
+/*OTP*/
+#define OTP_TEE_REG_BASE (0xFE440000)
+
+#define OTP_TEE_RDY (0x00 + OTP_TEE_REG_BASE)
+#define OTP_TEE_RDY_1 (0x04 + OTP_TEE_REG_BASE)
+
+#define OTP_TEE_CFG (0x08 + OTP_TEE_REG_BASE)
+
+#define OTP_TEE_WR_DAT0 (0x10 + OTP_TEE_REG_BASE)
+#define OTP_TEE_WR_DAT1 (0x14 + OTP_TEE_REG_BASE)
+#define OTP_TEE_WR_DAT2 (0x18 + OTP_TEE_REG_BASE)
+#define OTP_TEE_WR_DAT3 (0x1c + OTP_TEE_REG_BASE)
+
+#define OTP_TEE_RD_DAT0 (0x20 + OTP_TEE_REG_BASE)
+#define OTP_TEE_RD_DAT1 (0x24 + OTP_TEE_REG_BASE)
+#define OTP_TEE_RD_DAT2 (0x28 + OTP_TEE_REG_BASE)
+#define OTP_TEE_RD_DAT3 (0x2c + OTP_TEE_REG_BASE)
+
+
+#define OTP_LIC00 (0x40 + OTP_TEE_REG_BASE)
+#define OTP_LIC01 (0x44 + OTP_TEE_REG_BASE)
+#define OTP_LIC02 (0x48 + OTP_TEE_REG_BASE)
+#define OTP_LIC03 (0x4c + OTP_TEE_REG_BASE)
+
+#define OTP_LIC10 (0x50 + OTP_TEE_REG_BASE)
+#define OTP_LIC11 (0x54 + OTP_TEE_REG_BASE)
+#define OTP_LIC12 (0x58 + OTP_TEE_REG_BASE)
+#define OTP_LIC13 (0x5c + OTP_TEE_REG_BASE)
+
+#define OTP_LIC20 (0x60 + OTP_TEE_REG_BASE)
+#define OTP_LIC21 (0x64 + OTP_TEE_REG_BASE)
+#define OTP_LIC22 (0x68 + OTP_TEE_REG_BASE)
+#define OTP_LIC23 (0x6C + OTP_TEE_REG_BASE)
+
+#define OTP_LIC30 (0x70 + OTP_TEE_REG_BASE)
+#define OTP_LIC31 (0x74 + OTP_TEE_REG_BASE)
+#define OTP_LIC32 (0x78 + OTP_TEE_REG_BASE)
+#define OTP_LIC33 (0x7c + OTP_TEE_REG_BASE)
+
+
+//
+// Closing file: ./parser_regs.h
+//
+#include "fixme.h"
+#include "soc_def.h"
+#endif // REGISTER_H
+
diff --git a/arch/arm/include/asm/arch-sc2/regs.h b/arch/arm/include/asm/arch-sc2/regs.h
new file mode 100644
index 0000000..74abe2b
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/regs.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AML_REG_H__
+#define __AML_REG_H__
+/*
+ * all used regs
+ */
+/*
+ * ISA_TIMERE use SYSCTRL_TIMERE
+ * WATCHDOG_CNTL use RESETCTRL_WATCHDOG_CTRL0
+ * WATCHDOG_TCNT use RESETCTRL_WATCHDOG_CNT
+ * WATCHDOG_RST use RESETCTRL_WATCHDOG_CLR
+ */
+#define ISA_TIMERE ((0x0041 << 2) + 0xfe005800)
+#define WATCHDOG_CNTL ((0x0040 << 2) + 0xfe000000)
+#define WATCHDOG_TCNT ((0x0042 << 2) + 0xfe000000)
+#define WATCHDOG_RST ((0x0043 << 2) + 0xfe000000)
+
+/*
+ * SEC_AO_SEC_GP_CFG0 use SYSCTRL_SEC_STATUS_REG4
+ * AO_SEC_GP_CFG0 use SYSCTRL_SEC_STATUS_REG4
+ * AO_RTI_STATUS_REG3 use SYSCTRL_SEC_STICKY_REG1
+ * AO_SEC_SD_CFG15 use SYSCTRL_SEC_STATUS_REG2
+ */
+//#define SEC_AO_SEC_GP_CFG0 ((0x00c4 << 2) + 0xfe005800)
+#define AO_SEC_GP_CFG0 ((0x00c4 << 2) + 0xfe005800)
+#define AO_RTI_STATUS_REG3 ((0x00e1 << 2) + 0xfe005800)
+//#define AO_SEC_SD_CFG15 ((0x00c2 << 2) + 0xfe005800)
+
+/* PREG_STICKY_REG8 use SYSCTRL_STICKY_REG7
+ * P_AO_SEC_GP_CFG12 use SYSCTRL_DEBUG_REG6
+ * P_AO_SEC_GP_CFG13 use SYSCTRL_DEBUG_REG7
+ */
+#define PREG_STICKY_REG8 ((0x00b7 << 2) + 0xfe005800)
+#define P_AO_SEC_GP_CFG12 (volatile uint32_t *)((0x0096 << 2) + 0xfe005800)
+#define P_AO_SEC_GP_CFG13 (volatile uint32_t *)((0x0097 << 2) + 0xfe005800)
+
+/*
+ * P_AO_RTI_PINMUX_REG0 use PADCTRL_PIN_MUX_REG0
+ * P_AO_TIMEBASE_CNTL1 use CLKTREE_TIMEBASE_CTRL1
+ * AO_UART_WFIFO use UART_B_WFIFO
+ */
+#define P_AO_RTI_PINMUX_REG0 ((0x0000 << 2) + 0xfe000400)
+#define P_AO_TIMEBASE_CNTL1 ((0x0016 << 2) + 0xfe000800)
+#define AO_UART_WFIFO ((0x0000 << 2) + 0xfe002000)
+
+/*
+ * Not AO watch dog
+ */
+#define P_WATCHDOG_CNTL (volatile uint32_t *)(WATCHDOG_CNTL)
+#define P_WATCHDOG_TCNT (volatile uint32_t *)(WATCHDOG_TCNT)
+#define P_WATCHDOG_RST (volatile uint32_t *)(WATCHDOG_RST)
+#define P_ISA_TIMERE (volatile uint32_t *)(ISA_TIMERE)
+
+#endif /* __AML_REG_H__ */
diff --git a/arch/arm/include/asm/arch-sc2/romboot.h b/arch/arm/include/asm/arch-sc2/romboot.h
new file mode 100644
index 0000000..102562d
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/romboot.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOOT_ROM_H_
+#define __BOOT_ROM_H_
+#ifndef __ASSEMBLY__
+//#include <stdint.h>
+//uint8_t simple_i2c(uint8_t adr);
+//void spi_pin_mux(void);
+//void spi_init(void);
+//uint32_t spi_read(uint32_t src, uint32_t mem, uint32_t size);
+//void udelay(uint32_t usec);
+//void boot_des_decrypt(uint8_t *ct, uint8_t *pt, uint32_t size);
+
+#endif /* ! __ASSEMBLY__ */
+#include "config.h"
+
+/* Magic number to "boot" up A53 */
+#define AO_SEC_SD_CFG10_CB 0x80000000
+
+/*BOOT device and ddr size*/
+/*31-28: boot device id, 27-24: boot device para, 23-20: reserved*/
+/*19-8: ddr size, 7-0: board revision*/
+//#define P_AO_SEC_GP_CFG0 0xDA100240 //defined in secure_apb.h
+#define AO_SEC_GP_CFG7_W0_BIT 8
+#define AO_SEC_GP_CFG7_W0 0x100
+
+#define BOOT_ID_RESERVED 0
+#define BOOT_ID_EMMC 1
+#define BOOT_ID_NAND 2
+#define BOOT_ID_SPI 3
+#define BOOT_ID_SDCARD 4
+#define BOOT_ID_USB 5
+#define BOOT_ID_SPI_NAND (6)
+#define BOOT_ID_MAX (7)
+
+#endif /* __BOOT_ROM_H_ */
diff --git a/arch/arm/include/asm/arch-sc2/sd_emmc.h b/arch/arm/include/asm/arch-sc2/sd_emmc.h
new file mode 100644
index 0000000..82d4fb2
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/sd_emmc.h
@@ -0,0 +1,138 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __SD_EMMC_H__
+#define __SD_EMMC_H__
+
+#include <mmc.h>
+
+#define SDIO_PORT_A 0
+#define SDIO_PORT_B 1
+#define SDIO_PORT_C 2
+
+#define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */
+#define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */
+
+#define MESON_SD_EMMC_CLOCK 0x00
+#define CLK_MAX_DIV GENMASK(5, 0)
+#define CLK_MAX_SRC GENMASK(7, 6)
+#define Cfg_div 0
+#define Cfg_src 6
+#define Cfg_co_phase 8
+#define Cfg_tx_phase 10
+#define Cfg_rx_phase 12
+#define Cfg_sram_pd 14
+#define Cfg_tx_delay 16
+#define Cfg_rx_delay 22
+#define Cfg_always_on 28
+#define Cfg_irq_sdio_sleep 29
+#define Cfg_irq_sdio_sleep_ds 30
+
+#define MESON_SD_EMMC_DELAY1 0x4
+#define DLY_D0_MASK GENMASK(5, 0)
+#define DLY_D1_MASK GENMASK(11, 6)
+#define DLY_D2_MASK GENMASK(17, 12)
+#define DLY_D3_MASK GENMASK(23, 18)
+#define DLY_D4_MASK GENMASK(31, 24)
+#define Dly_d0 0
+#define Dly_d1 6
+#define Dly_d2 12
+#define Dly_d3 18
+#define Dly_d4 24
+
+#define MESON_SD_EMMC_DELAY2 0x8
+#define DLY_D5_MASK GENMASK(5, 0)
+#define DLY_D6_MASK GENMASK(11, 6)
+#define DLY_D7_MASK GENMASK(17, 12)
+#define DLY_D8_MASK GENMASK(23, 18)
+#define DLY_D9_MASK GENMASK(31, 24)
+#define Dly_d5 0
+#define Dly_d6 6
+#define Dly_d7 12
+#define Dly_d8 18
+#define Dly_d9 24
+
+#define MESON_SD_EMMC_ADJUST 0xC
+#define CALI_SEL_MASK GENMASK(11, 8)
+#define ADJ_DLY_MASK GENMASK(21, 16)
+#define Cfg_cali_sel 8
+#define Cfg_cali_en 12
+#define Cfg_adj_en 13
+#define Cfg_cali_rise 14
+#define Cfg_ds_en 15
+#define Cfg_adj_dly 16
+#define Cfg_adj_auto 22
+#define Cfg_adj_init 23
+
+#define MESON_SD_EMMC_START 0x40
+#define CFG_DESC_INIT BIT(0)
+#define CFG_DESC_BUSY BIT(1)
+#define CFG_DESC_ADDR 2
+
+#define MESON_SD_EMMC_CFG 0x44
+#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
+#define CFG_BUS_WIDTH_1 0
+#define CFG_BUS_WIDTH_4 1
+#define CFG_BUS_WIDTH_8 2
+#define CFG_DDR BIT(2)
+#define CFG_BL_LEN_MASK GENMASK(7, 4)
+#define CFG_BL_LEN_SHIFT 4
+#define CFG_BL_LEN_512 (9 << 4)
+#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
+#define CFG_RESP_TIMEOUT_256 (8 << 8)
+#define CFG_RC_CC_MASK GENMASK(15, 12)
+#define CFG_RC_CC_16 (4 << 12)
+#define CFG_SDCLK_ALWAYS_ON BIT(18)
+#define CFG_AUTO_CLK BIT(23)
+
+#define MESON_SD_EMMC_STATUS 0x48
+#define STATUS_MASK GENMASK(15, 0)
+#define STATUS_ERR_MASK GENMASK(12, 0)
+#define STATUS_RXD_ERR_MASK GENMASK(7, 0)
+#define STATUS_TXD_ERR BIT(8)
+#define STATUS_DESC_ERR BIT(9)
+#define STATUS_RESP_ERR BIT(10)
+#define STATUS_RESP_TIMEOUT BIT(11)
+#define STATUS_DESC_TIMEOUT BIT(12)
+#define STATUS_END_OF_CHAIN BIT(13)
+
+#define MESON_SD_EMMC_IRQ_EN 0x4c
+
+#define MESON_SD_EMMC_CMD_CFG 0x50
+#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
+#define CMD_CFG_BLOCK_MODE BIT(9)
+#define CMD_CFG_R1B BIT(10)
+#define CMD_CFG_END_OF_CHAIN BIT(11)
+#define CMD_CFG_TIMEOUT_4S (12 << 12)
+#define CMD_CFG_NO_RESP BIT(16)
+#define CMD_CFG_NO_CMD BIT(17)
+#define CMD_CFG_DATA_IO BIT(18)
+#define CMD_CFG_DATA_WR BIT(19)
+#define CMD_CFG_RESP_NOCRC BIT(20)
+#define CMD_CFG_RESP_128 BIT(21)
+#define CMD_CFG_RESP_NUM BIT(22)
+#define CMD_CFG_DATA_NUM BIT(23)
+#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
+#define CMD_CFG_CMD_INDEX_SHIFT 24
+#define CMD_CFG_ERR BIT(30)
+#define CMD_CFG_OWNER BIT(31)
+
+#define MESON_SD_EMMC_CMD_ARG 0x54
+#define MESON_SD_EMMC_CMD_DAT 0x58
+#define MESON_SD_EMMC_CMD_RSP 0x5c
+#define MESON_SD_EMMC_CMD_RSP1 0x60
+#define MESON_SD_EMMC_CMD_RSP2 0x64
+#define MESON_SD_EMMC_CMD_RSP3 0x68
+
+#define SD_EMMC_RXD_ERROR (1 << 0)
+#define SD_EMMC_TXD_ERROR (1 << 1)
+#define SD_EMMC_DESC_ERROR (1 << 2)
+#define SD_EMMC_RESP_CRC_ERROR (1 << 3)
+#define SD_EMMC_RESP_TIMEOUT_ERROR (1 << 4)
+#define SD_EMMC_DESC_TIMEOUT_ERROR (1 << 5)
+
+//boot from sd or emmc
+#define SEC_AO_SEC_GP_CFG0 (SYSCTRL_SEC_STATUS_REG4)
+#endif
diff --git a/arch/arm/include/asm/arch-sc2/secure_apb.h b/arch/arm/include/asm/arch-sc2/secure_apb.h
new file mode 100644
index 0000000..bf0eef7
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/secure_apb.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/regs.h>
+#include <asm/arch/register.h>
+
+#define DMA_BASE (uint32_t)(0xfe440400)
+
+#define DMA_T0 (uint32_t)(DMA_BASE + 0x00)
+#define DMA_T1 (uint32_t)(DMA_BASE + 0x04)
+#define DMA_T2 (uint32_t)(DMA_BASE + 0x08)
+#define DMA_T3 (uint32_t)(DMA_BASE + 0x0c)
+#define DMA_T4 (uint32_t)(DMA_BASE + 0x10)
+#define DMA_T5 (uint32_t)(DMA_BASE + 0x14)
+#define DMA_STS0 (uint32_t)(DMA_BASE + 0x20)
+#define DMA_STS1 (uint32_t)(DMA_BASE + 0x24)
+#define DMA_STS2 (uint32_t)(DMA_BASE + 0x28)
+#define DMA_STS3 (uint32_t)(DMA_BASE + 0x2c)
+#define DMA_STS4 (uint32_t)(DMA_BASE + 0x30)
+#define DMA_STS5 (uint32_t)(DMA_BASE + 0x34)
+#define DMA_CFG (uint32_t)(DMA_BASE + 0x40)
+#define DMA_SEC (uint32_t)(DMA_BASE + 0x44)
+#define DMA_END (uint32_t)(DMA_BASE + 0x3ff)
+
+#define P_DMA_T0 (volatile uint32_t *)(DMA_BASE + 0x00)
+#define P_DMA_T1 (volatile uint32_t *)(DMA_BASE + 0x04)
+#define P_DMA_T2 (volatile uint32_t *)(DMA_BASE + 0x08)
+#define P_DMA_T3 (volatile uint32_t *)(DMA_BASE + 0x0c)
+#define P_DMA_T4 (volatile uint32_t *)(DMA_BASE + 0x10)
+#define P_DMA_T5 (volatile uint32_t *)(DMA_BASE + 0x14)
+#define P_DMA_STS0 (volatile uint32_t *)(DMA_BASE + 0x20)
+#define P_DMA_STS1 (volatile uint32_t *)(DMA_BASE + 0x24)
+#define P_DMA_STS2 (volatile uint32_t *)(DMA_BASE + 0x28)
+#define P_DMA_STS3 (volatile uint32_t *)(DMA_BASE + 0x2c)
+#define P_DMA_STS4 (volatile uint32_t *)(DMA_BASE + 0x30)
+#define P_DMA_STS5 (volatile uint32_t *)(DMA_BASE + 0x34)
+#define P_DMA_CFG (volatile uint32_t *)(DMA_BASE + 0x40)
+#define P_DMA_SEC (volatile uint32_t *)(DMA_BASE + 0x44)
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-sc2/soc_def.h b/arch/arm/include/asm/arch-sc2/soc_def.h
new file mode 100644
index 0000000..d718d32
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/soc_def.h
@@ -0,0 +1,24 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __SC2_DEF_H__
+#define __SC2_DEF_H__
+
+#include "secure_apb.h"
+
+
+#define SEC_AO_SEC_GP_CFG2 SYSCTRL_SEC_STATUS_REG6
+#define SEC_AO_SEC_SD_CFG15 SYSCTRL_SEC_STATUS_REG31
+
+#define SEC_AO_RTI_STATUS_REG3 SYSCTRL_SEC_STICKY_REG1
+
+
+#define AO_SEC_SD_CFG15 SEC_AO_SEC_SD_CFG15
+
+/*for SC2 DSP compatible*/
+#define CLKTREE_DSPA_CLK_CTRL0 CLKCTRL_DSPA_CLK_CTRL0
+#define CLKTREE_DSPB_CLK_CTRL0 CLKCTRL_DSPB_CLK_CTRL0
+
+#endif /* __SC2_DEF_H__ */
diff --git a/arch/arm/include/asm/arch-sc2/timer.h b/arch/arm/include/asm/arch-sc2/timer.h
new file mode 100644
index 0000000..492cc8d
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/timer.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __TIMER_H
+#define __TIMER_H
+
+#include <asm/arch/romboot.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/io.h>
+
+/**
+ * Get the current timestamp from the system timer.
+ */
+uint32_t get_time(void);
+
+/**
+ * Busy-wait.
+ *
+ * @param us Number of microseconds to delay.
+ */
+void _udelay(unsigned int us);
+
+#endif /* __TIMER_H */
diff --git a/arch/arm/include/asm/arch-sc2/timing.h b/arch/arm/include/asm/arch-sc2/timing.h
new file mode 100644
index 0000000..aa0e4db
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/timing.h
@@ -0,0 +1,433 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AML_TIMING_H_
+#define __AML_TIMING_H_
+
+#include <asm/arch/ddr_define.h>
+#include <asm/arch/types.h>
+#include <asm/arch/mnPmuSramMsgBlock_ddr3.h>
+#include <asm/arch/mnPmuSramMsgBlock_ddr4.h>
+#include <asm/arch/mnPmuSramMsgBlock_ddr4_2d.h>
+#include <asm/arch/mnPmuSramMsgBlock_lpddr3.h>
+#include <asm/arch/mnPmuSramMsgBlock_lpddr4.h>
+#include <asm/arch/mnPmuSramMsgBlock_lpddr4_2d.h>
+#include <asm/arch/dev_parameter.h>
+
+#define BL2_INIT_STAGE_0 0
+#define BL2_INIT_STAGE_1 1
+#define BL2_INIT_STAGE_2 2
+#define BL2_INIT_STAGE_3 3
+#define BL2_INIT_STAGE_4 4
+#define BL2_INIT_STAGE_5 5
+#define BL2_INIT_STAGE_6 6
+#define BL2_INIT_STAGE_7 7
+#define BL2_INIT_STAGE_8 8
+#define BL2_INIT_STAGE_9 9
+
+typedef struct bl2_reg {
+ unsigned int reg;
+ unsigned int value;
+ unsigned int mask;
+ unsigned int flag;
+ unsigned short udelay;
+ unsigned short rsv_0;
+}__attribute__ ((packed)) bl2_reg_t;
+
+typedef struct training_delay_set_ps{
+ unsigned char ac_trace_delay[10];
+ unsigned char ac_trace_delay_rev[2];
+ unsigned char read_dqs_delay[16];
+ unsigned char read_dq_bit_delay[72];
+ unsigned short write_dqs_delay[16];
+// */
+ unsigned short write_dq_bit_delay[72];
+ unsigned short read_dqs_gate_delay[16];
+ unsigned char soc_bit_vref[36];
+ unsigned char dram_bit_vref[32];
+ ///*
+ unsigned char rever1;//read_dqs read_dq,write_dqs, write_dq
+ unsigned char dfi_mrl;
+ unsigned char dfi_hwtmrl;
+ unsigned char ARdPtrInitVal;
+ unsigned short csr_vrefinglobal;
+ unsigned short csr_dqsrcvcntrl[4];
+ unsigned short csr_pptdqscntinvtrntg0[4];
+ unsigned short csr_pptdqscntinvtrntg1[4];
+ unsigned short csr_seq0bgpr[9];
+ unsigned short csr_dllgainctl;
+ unsigned short csr_dlllockpara;
+// unsigned short rever2;
+}__attribute__ ((packed)) training_delay_set_ps_t;
+
+typedef struct ddr_mrs_reg {
+ unsigned int cfg_ddr_mr[8];
+ unsigned int cfg_ddr_mr11;
+ unsigned int cfg_ddr_mr12;
+ unsigned int cfg_ddr_mr13;
+ unsigned int cfg_ddr_mr14;
+ unsigned int cfg_ddr_mr16;
+ unsigned int cfg_ddr_mr17;
+ unsigned int cfg_ddr_mr22;
+ unsigned int cfg_ddr_mr24;
+}__attribute__ ((packed)) ddr_mrs_reg_t;
+
+typedef struct ddr_timing{
+ unsigned int identifier;
+ unsigned int cfg_ddr_mrd;
+ unsigned int cfg_ddr_rfcab;
+ unsigned int cfg_ddr_rfcpb;
+ unsigned int cfg_ddr_rpab;
+ unsigned int cfg_ddr_rppb;
+ unsigned int cfg_ddr_rtw;
+ unsigned int cfg_ddr_rl;
+ unsigned int cfg_ddr_wl;
+ unsigned int cfg_ddr_ras;
+ unsigned int cfg_ddr_rc;
+ unsigned int cfg_ddr_rcd;
+ unsigned int cfg_ddr_rrds;
+ unsigned int cfg_ddr_rrdl;
+ unsigned int cfg_ddr_faw;
+ unsigned int cfg_ddr_rtp;
+ unsigned int cfg_ddr_wr;
+ unsigned int cfg_ddr_wtrs;
+ unsigned int cfg_ddr_wtrl;
+ unsigned int cfg_ddr_ccds;
+ unsigned int cfg_ddr_ccdl;
+ unsigned int cfg_ddr_exsr;
+ unsigned int cfg_ddr_xs;
+ unsigned int cfg_ddr_xp;
+ unsigned int cfg_ddr_xpdll;
+ unsigned int cfg_ddr_zqcs;
+ unsigned int cfg_ddr_cksre;
+ unsigned int cfg_ddr_cksrx;
+ unsigned int cfg_ddr_cke;
+ unsigned int cfg_ddr_mod;
+ unsigned int cfg_ddr_dqs;
+ unsigned int cfg_ddr_rstl;
+ unsigned int cfg_ddr_zqlat;
+ unsigned int cfg_ddr_mrr;
+ unsigned int cfg_ddr_ckesr;
+ unsigned int cfg_ddr_dpd;
+ unsigned int cfg_ddr_ckeck;
+ unsigned int cfg_ddr_refi;
+ unsigned int cfg_ddr_sr;
+ unsigned int cfg_ddr_ccdmw;
+ unsigned int cfg_ddr_escke;
+ unsigned int cfg_ddr_refi_ddr3;
+ unsigned int cfg_ddr_dfictrldelay;
+ unsigned int cfg_ddr_dfiphywrdata;
+ unsigned int cfg_ddr_dfiphywrlat;
+ unsigned int cfg_ddr_dfiphyrddataen;
+ unsigned int cfg_ddr_dfiphyrdlat;
+ unsigned int cfg_ddr_dfictrlupdmin;
+ unsigned int cfg_ddr_dfictrlupdmax;
+ unsigned int cfg_ddr_dfimstrresp;
+ unsigned int cfg_ddr_dfirefmski;
+ unsigned int cfg_ddr_dfictrlupdi;
+ unsigned int cfg_ddr_dfidramclk;
+ unsigned int cfg_ddr_dfilpresp;
+ unsigned int cfg_ddr_dfiphymstr;
+ unsigned int cfg_ddr_rtodt;
+ unsigned int cfg_ddr_wlmrd;
+ unsigned int cfg_ddr_wlo;
+ unsigned int cfg_ddr_al;
+ unsigned int cfg_ddr_zqcl;
+ unsigned int cfg_ddr_zqcsi;
+ unsigned int cfg_ddr_zqreset;
+ unsigned int cfg_ddr_tdqsck_min;
+ unsigned int cfg_ddr_tdqsck_max;
+ //training_delay_set_ps_t cfg_ddr_training_delay_ps;
+ ddr_mrs_reg_t cfg_ddr_mrs_reg_ps[2];
+ unsigned int dfi_odt1_config_ps[2];
+ //ddr_mrs_reg_t cfg_ddr_mrs_reg_ps1;
+ #if 0
+ unsigned int cfg_ddr_mr[8];
+ unsigned int cfg_ddr_mr11;
+ unsigned int cfg_ddr_mr12;
+ unsigned int cfg_ddr_mr13;
+ unsigned int cfg_ddr_mr14;
+ unsigned int cfg_ddr_mr16;
+ unsigned int cfg_ddr_mr17;
+ unsigned int cfg_ddr_mr22;
+ unsigned int cfg_ddr_mr24;
+ unsigned int cfg_ddr_reserve[5];
+ #endif
+}__attribute__ ((packed)) ddr_timing_t;
+
+typedef struct ddr_phy_common_extra_set{
+ unsigned short csr_pllctrl3;
+ unsigned short csr_pptctlstatic[4];
+ unsigned short csr_trainingincdecdtsmen[4];
+ unsigned short csr_tsmbyte0[4];
+ unsigned short csr_hwtcamode;
+ unsigned short csr_hwtlpcsena;
+ unsigned short csr_hwtlpcsenb;
+ unsigned short csr_acsmctrl13;
+ unsigned short csr_acsmctrl23;
+ unsigned char csr_soc_vref_dac1_dfe[36];
+}__attribute__ ((packed)) ddr_phy_common_extra_set_t;
+
+typedef struct retraining_set{
+ ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t;
+ training_delay_set_ps_t cfg_ddr_training_delay_ps;
+}__attribute__ ((packed)) retraining_set_t;
+
+typedef struct ddr_set{
+ unsigned int magic;
+ unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test
+ //unsigned int rsv_int0;
+ unsigned int ddr_func;
+ unsigned char board_id;
+ //board id reserve,,do not modify
+ unsigned char version;
+ // firmware reserve version,,do not modify
+ unsigned char DramType;
+ //support DramType should confirm with amlogic
+ //#define CONFIG_DDR_TYPE_DDR3 0
+ //#define CONFIG_DDR_TYPE_DDR4 1
+ //#define CONFIG_DDR_TYPE_LPDDR4 2
+ //#define CONFIG_DDR_TYPE_LPDDR3 3
+ //#define CONFIG_DDR_TYPE_LPDDR2 4
+ unsigned char DisabledDbyte;
+ //use for dram bus 16bit or 32bit,if use 16bit mode ,should disable bit 2,3
+ //bit 0 ---use byte 0 ,1 disable byte 0,
+ //bit 1 ---use byte 1 ,1 disable byte 1,
+ //bit 2 ---use byte 2 ,1 disable byte 2,
+ //bit 3 ---use byte 3 ,1 disable byte 3,
+ unsigned char Is2Ttiming;
+ //ddr3/ddr3 use 2t timing,now only support 2t timming
+ unsigned char HdtCtrl;
+ //training information control,do not modify
+ unsigned char dram_rank_config;
+ //support Dram connection type should confirm with amlogic
+ //#define CONFIG_DDR0_16BIT_CH0 0x1 //dram total bus width 16bit only use cs0
+ //#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 //dram total bus width 16bit use cs0 cs1
+ //#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 //dram total bus width 32bit use cs0
+ //#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 //only for lpddr4,dram total bus width 32bit use chanel a cs0 cs1 chanel b cs0 cs1
+ //#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 //dram total bus width 32bit only use cs0,but high address use 16bit mode
+ //#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 //dram total bus width 32bit use cs0 cs1,but cs1 use 16bit mode ,current phy not support reserve
+ //#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7 //dram total bus width 32bit use cs0 cs1
+ //#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8 //only for lpddr4,dram total bus width 32bit use chanel a cs0 chanel b cs0
+
+ /* rsv_char0. update for diagnose type define */
+ unsigned char diagnose;
+
+ unsigned short soc_data_drv_ohm_ps1;
+ unsigned short dram_data_drv_ohm_ps1;
+ unsigned short soc_data_odt_ohm_ps1;
+ unsigned short dram_data_odt_ohm_ps1;
+ unsigned short dram_data_wr_odt_ohm_ps1;
+ #if 0
+ /* imem/dmem define */
+ unsigned int imem_load_addr;
+ //system reserve,do not modify
+ unsigned int dmem_load_addr;
+ //system reserve,do not modify
+ unsigned short imem_load_size;
+ #endif
+ //system reserve,do not modify
+ unsigned short dmem_load_size;
+ //system reserve,do not modify
+ unsigned int ddr_base_addr;
+ //system reserve,do not modify
+ unsigned int ddr_start_offset;
+ //system reserve,do not modify
+
+ unsigned short dram_cs0_size_MB;
+ //config cs0 dram size ,like 1G DRAM ,setting 1024
+ unsigned short dram_cs1_size_MB;
+ //config cs1 dram size,like 512M DRAM ,setting 512
+ /* align8 */
+
+ unsigned short training_SequenceCtrl[2];
+ //system reserve,do not modify
+ unsigned char phy_odt_config_rank[2];
+ //unsigned char rever1;
+ //unsigned char rever2;
+ unsigned short rank1_ca_vref_permil;
+ //training odt config ,only use for training
+ // [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ // [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ unsigned int dfi_odt_config;
+ //normal go status od config,use for normal status
+ //bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity.
+ //bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1.
+ //bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0.
+ //bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1.
+ //bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0.
+ //bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity.
+ //bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0.
+ //bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1.
+ //bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0.
+ //bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1.
+ unsigned short DRAMFreq[4];
+ //config dram frequency,use DRAMFreq[0],ohter reserve
+ unsigned char PllBypassEn;
+ //system reserve,do not modify
+ unsigned char ddr_rdbi_wr_enable;
+ //system reserve,do not modify
+ unsigned char ddr_rfc_type;
+ //config dram rfc type,according dram type,also can use same dram type max config
+ //#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+ //#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+ //#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+ //#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+ //#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+ //#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+ //#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+ //#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+ //#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+ //#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+ //#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+ //#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+ unsigned char enable_lpddr4x_mode;
+ //system reserve,do not modify
+ /* align8 */
+
+ unsigned int pll_ssc_mode;
+ //
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ unsigned short clk_drv_ohm;
+ //config soc clk pin signal driver stength ,select 20,30,40,60ohm
+ unsigned short cs_drv_ohm;
+ //config soc cs0 cs1 pin signal driver stength ,select 20,30,40,60ohm
+ unsigned short ac_drv_ohm;
+ //config soc normal address command pin driver stength ,select 20,30,40,60ohm
+ unsigned short soc_data_drv_ohm_p;
+ //config soc data pin pull up driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short soc_data_drv_ohm_n;
+ //config soc data pin pull down driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short soc_data_odt_ohm_p;
+ //config soc data pin odt pull up stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short soc_data_odt_ohm_n;
+ //config soc data pin odt pull down stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short dram_data_drv_ohm;
+ //config dram data pin pull up pull down driver stength,ddr3 select 34,40ohm,ddr4 select 34,48ohm,lpddr4 select 40,48,60,80,120,240ohm
+ unsigned short dram_data_odt_ohm;
+ //config dram data pin odt pull up down stength,ddr3 select 40,60,120ohm,ddr4 select 34,40,48,60,120,240ohm,lpddr4 select 40,48,60,80,120,240ohm
+ unsigned short dram_ac_odt_ohm;
+ //config dram ac pin odt pull up down stength,use for lpddr4, select 40,48,60,80,120,240ohm
+ unsigned short soc_clk_slew_rate;
+ //system reserve,do not modify
+ unsigned short soc_cs_slew_rate;
+ //system reserve,do not modify
+ unsigned short soc_ac_slew_rate;
+ //system reserve,do not modify
+ unsigned short soc_data_slew_rate;
+ //system reserve,do not modify
+ unsigned short vref_output_permil; //phy
+ //setting same with vref_dram_permil
+ unsigned short vref_receiver_permil; //soc
+ //soc init SOC receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
+ unsigned short vref_dram_permil;
+ //soc init DRAM receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
+ unsigned short max_core_timmming_frequency;
+ //use for limited ddr speed core timmming parameter,for some old dram maybe have no over speed register
+ /* align8 */
+
+ unsigned char ac_trace_delay[10];
+ unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting;
+ //use for lpddr4 read vout voltage setting 0 --->2/5VDDQ ,1--->1/3VDDQ
+ unsigned char lpddr4_x8_mode;
+ unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function
+ //[1],slt test parameter ,use for force delay line offset
+ //system reserve,do not modify
+ unsigned short tdqs2dq;
+ unsigned char dram_data_wr_odt_ohm;
+ unsigned char bitTimeControl_2d;
+ //system reserve,do not modify
+ /* align8 */
+ unsigned char char_rev1;
+ unsigned char training_offset;//char_rev2;
+ unsigned int ddr_dmc_remap[5];
+ unsigned int dram_rtt_nom_wr_park[2];
+ //system reserve,do not modify
+ /* align8 */
+ unsigned char ddr_lpddr34_ca_remap[4];
+ ////use for lpddr3 /lpddr4 ca training data byte lane remap
+ unsigned char ddr_lpddr34_dq_remap[32];
+ ////use for lpddr3 /lpddr4 ca pinmux remap
+ unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL];
+ //use for lpddr3 /lpddr4 ca pinmux remap
+ unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL];
+ unsigned char char_rev3;
+ unsigned char char_rev4;
+ ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t;
+ training_delay_set_ps_t cfg_ddr_training_delay_ps[2];
+
+ //override read bit delay
+}__attribute__ ((packed)) ddr_set_t;
+
+typedef struct board_clk_set{
+ unsigned short cpu_clk;
+ unsigned short dsu_clk;
+ unsigned short vddee;
+ unsigned short vcck;
+ unsigned short pxp;
+ unsigned char szPad[2];
+}__attribute__ ((packed)) board_clk_set_t;
+
+typedef struct pll_ctrl{
+ /*Enable flag: 0xa1:need set pll in bl2
+ 0xa2:need set pll in bl2x
+ other: no need
+ */
+ unsigned char flag;
+ /* Delay time for timing sequence in 10us, range [0 .. 255]*/
+ unsigned char delay_10u;
+ /* PLL clock
+ * syspll [93 .. 6000]
+ * fixpll [93 .. 6000]
+ * gp0pll [93 .. 6000]
+ * gp1pll [93 .. 6000]
+ * hifipll [375 .. 6000]
+ */
+ unsigned short clkset;
+ unsigned int pll_para[8];
+ unsigned int reserve;
+} __attribute__ ((packed)) pll_ctrl_t;
+
+typedef struct pll_set{
+ /*new struct for sc2*/
+ pll_ctrl_t sys_pll_ctrl;
+ pll_ctrl_t fix_pll_ctrl;
+ pll_ctrl_t gp0_pll_ctrl;
+ pll_ctrl_t gp1_pll_ctrl;
+ pll_ctrl_t hifi_pll_ctrl;
+}__attribute__ ((packed)) pll_set_t;
+
+typedef struct bl2_sec_parameter{
+ /*new struct for sc2*/
+ uint32_t version;
+ uint32_t bl31_region_start;
+ uint32_t bl31_region_size;
+ uint32_t bl32_region_start;
+ uint32_t bl32_region_size;
+
+ uint32_t RFU[27];
+}__attribute__ ((packed)) sec_parameter_t;
+
+typedef struct dmem_cfg {
+ PMU_SMB_DDR3U_1D_t ddr3u;
+ PMU_SMB_DDR4U_1D_t ddr4u;
+ PMU_SMB_DDR4U_2D_t ddr4u_2d;
+ PMU_SMB_LPDDR3_1D_t lpddr3u;
+ PMU_SMB_LPDDR4_1D_t lpddr4u;
+ PMU_SMB_LPDDR4_2D_t lpddr4u_2d;
+} dmem_cfg_t;
+
+#endif //__AML_TIMING_H_
diff --git a/arch/arm/include/asm/arch-sc2/tsensor.h b/arch/arm/include/asm/arch-sc2/tsensor.h
new file mode 100644
index 0000000..8b365a4
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/tsensor.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __TSENSOR_H__
+#define __TSENSOR_H__
+
+
+struct tsensor_cali_data {
+ unsigned int cmd; /* R/W */
+ unsigned int offset;
+ unsigned int size;
+ unsigned long buffer_phy;
+ unsigned long retcnt_phy;
+};
+
+
+#define CONFIG_HIGH_TEMP_COOL 90
+
+#define T_AVG_NUM 16 /*read temp cnt*/
+#define T_VER_MASK 0x80
+#define T_VALUE_MIN 0x1500
+#define T_VALUE_MAX 0x3500
+#define T_DLY_TIME 4500 /*update sensor register need 4.2ms*/
+
+#define T_CONTROL_DATA 0x62b
+#define T_TSCLK_DATA 0x130
+
+#define ts_b 3159
+#define ts_a 9411
+#define ts_m 424
+#define ts_n 324
+
+#ifdef CONFIG_AML_TSENSOR
+int temp_read_entry(void);
+int temp_trim_entry(int tempbase, int tempver);
+int temp_cooling_entry(void);
+#else
+int temp_read_entry(void)
+{
+ return -1;
+}
+int temp_trim_entry(int tempbase, int tempver)
+{
+ return -1;
+}
+int temp_cooling_entry(void)
+{
+ return 0;
+}
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-sc2/types.h b/arch/arm/include/asm/arch-sc2/types.h
new file mode 100644
index 0000000..2d362b1
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/types.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __TYPES_H
+#define __TYPES_H
+
+#ifndef _INT8_T_DECLARED
+typedef char int8_t;
+#define _INT8_T_DECLARED
+#endif
+
+#ifndef _INT16_T_DECLARED
+typedef short int16_t;
+#define _INT16_T_DECLARED
+#endif
+
+#ifndef _INT32_T_DECLARED
+typedef int int32_t;
+#define _INT32_T_DECLARED
+#endif
+
+#ifndef _INT64_T_DECLARED
+typedef long int64_t;
+#define _INT64_T_DECLARED
+#endif
+
+#ifndef _UINT8_T_DECLARED
+typedef unsigned char uint8_t;
+#define _UINT8_T_DECLARED
+#endif
+
+#ifndef _UINT16_T_DECLARED
+typedef unsigned short uint16_t;
+#define _UINT16_T_DECLARED
+#endif
+
+#ifndef _UINT32_T_DECLARED
+typedef unsigned int uint32_t;
+#define _UINT32_T_DECLARED
+#endif
+
+#ifndef _UINT64_T_DECLARED
+typedef unsigned long uint64_t;
+#define _UINT64_T_DECLARED
+#endif
+
+#ifndef _INT8PTR_T_DECLARED
+typedef char * int8ptr_t;
+#define _INT8PTR_T_DECLARED
+#endif
+
+#ifndef _INT16PTR_T_DECLARED
+typedef short * int16ptr_t;
+#define _INT16PTR_T_DECLARED
+#endif
+
+#ifndef _INT32PTR_T_DECLARED
+typedef int * int32ptr_t;
+#define _INT32PTR_T_DECLARED
+#endif
+
+#ifndef _INT64PTR_T_DECLARED
+typedef long * int64ptr_t;
+#define _INT64PTR_T_DECLARED
+#endif
+
+#ifndef _UINT8PTR_T_DECLARED
+typedef unsigned char * uint8ptr_t;
+#define _UINT8PTR_T_DECLARED
+#endif
+
+#ifndef _UINT16PTR_T_DECLARED
+typedef unsigned short * uint16ptr_t;
+#define _UINT16PTR_T_DECLARED
+#endif
+
+#ifndef _UINT32PTR_T_DECLARED
+typedef unsigned int * uint32ptr_t;
+#define _UINT32PTR_T_DECLARED
+#endif
+
+#ifndef _UINT64PTR_T_DECLARED
+typedef unsigned long * uint64ptr_t;
+#define _UINT64PTR_T_DECLARED
+#endif
+
+#endif
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-sc2/uart.h b/arch/arm/include/asm/arch-sc2/uart.h
new file mode 100644
index 0000000..757dc91
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/uart.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __MESON_FIRM_UART_H_
+#define __MESON_FIRM_UART_H_
+#include <config.h>
+#include <common.h>
+#include "register.h"
+//#include "io.h"
+#include <asm/arch/secure_apb.h>
+
+#ifndef CONFIG_CONS_INDEX
+#error Please define CONFIG_CONS_INDEX==[0|1]
+#endif
+
+#if CONFIG_CONS_INDEX==0
+#define UART_PORT_CONS UART_PORT_0
+#elif CONFIG_CONS_INDEX==1
+#define UART_PORT_CONS UART_PORT_1
+#elif CONFIG_CONS_INDEX==2
+#define UART_PORT_CONS UART_PORT_AO
+#define USE_AO_UART 1
+#else
+#error Please define CONFIG_CONS_INDEX==[0|1]
+#endif
+/*
+#define UART_PORT_0 CBUS_REG_ADDR(UART0_WFIFO)
+#define UART_PORT_1 CBUS_REG_ADDR(UART1_WFIFO)
+#define UART_PORT_2 CBUS_REG_ADDR(UART2_WFIFO)
+#define UART_PORT_AO P_AO_UART_WFIFO
+
+#define UART_WFIFO (0<<2)
+#define UART_RFIFO (1<<2)
+#define UART_CONTROL (2<<2)
+#define UART_STATUS (3<<2)
+#define UART_MISC (4<<2)
+*/
+
+#include "clock.h"
+
+#define UART_CLK_SRC CLK81
+#define UART_PORT_0 0xfe001c00
+#define UART_PORT_1 0xfe001c00
+#define UART_PORT_AO 0xfe001c00
+#define UART_WFIFO 0
+#define UART_RFIFO 1
+#define UART_CONTROL 2
+#define UART_STATUS 3
+#define UART_MISC 4
+
+#if USE_AO_UART == 1
+#define P_UART(uart_base,reg) (uart_base + (reg<<2))
+#else
+#define P_UART(uart_base,reg) CBUS_REG_ADDR(uart_base+reg)
+#endif
+#define P_UART_WFIFO(uart_base) P_UART(uart_base,UART_WFIFO)
+#define P_UART_RFIFO(uart_base) P_UART(uart_base,UART_RFIFO)
+
+#define P_UART_CONTROL(uart_base) P_UART(uart_base,UART_CONTROL)
+ #define UART_CNTL_MASK_BAUD_RATE (0xfff)
+ #define UART_CNTL_MASK_TX_EN (1<<12)
+ #define UART_CNTL_MASK_RX_EN (1<<13)
+ #define UART_CNTL_MASK_2WIRE (1<<15)
+ #define UART_CNTL_MASK_STP_BITS (3<<16)
+ #define UART_CNTL_MASK_STP_1BIT (0<<16)
+ #define UART_CNTL_MASK_STP_2BIT (1<<16)
+ #define UART_CNTL_MASK_PRTY_EVEN (0<<18)
+ #define UART_CNTL_MASK_PRTY_ODD (1<<18)
+ #define UART_CNTL_MASK_PRTY_TYPE (1<<18)
+ #define UART_CNTL_MASK_PRTY_EN (1<<19)
+ #define UART_CNTL_MASK_CHAR_LEN (3<<20)
+ #define UART_CNTL_MASK_CHAR_8BIT (0<<20)
+ #define UART_CNTL_MASK_CHAR_7BIT (1<<20)
+ #define UART_CNTL_MASK_CHAR_6BIT (2<<20)
+ #define UART_CNTL_MASK_CHAR_5BIT (3<<20)
+ #define UART_CNTL_MASK_RST_TX (1<<22)
+ #define UART_CNTL_MASK_RST_RX (1<<23)
+ #define UART_CNTL_MASK_CLR_ERR (1<<24)
+ #define UART_CNTL_MASK_INV_RX (1<<25)
+ #define UART_CNTL_MASK_INV_TX (1<<26)
+ #define UART_CNTL_MASK_RINT_EN (1<<27)
+ #define UART_CNTL_MASK_TINT_EN (1<<28)
+ #define UART_CNTL_MASK_INV_CTS (1<<29)
+ #define UART_CNTL_MASK_MASK_ERR (1<<30)
+ #define UART_CNTL_MASK_INV_RTS (1<<31)
+#define P_UART_STATUS(uart_base) P_UART(uart_base,UART_STATUS )
+ #define UART_STAT_MASK_RFIFO_CNT (0x7f<<0)
+ #define UART_STAT_MASK_TFIFO_CNT (0x7f<<8)
+ #define UART_STAT_MASK_PRTY_ERR (1<<16)
+ #define UART_STAT_MASK_FRAM_ERR (1<<17)
+ #define UART_STAT_MASK_WFULL_ERR (1<<18)
+ #define UART_STAT_MASK_RFIFO_FULL (1<<19)
+ #define UART_STAT_MASK_RFIFO_EMPTY (1<<20)
+ #define UART_STAT_MASK_TFIFO_FULL (1<<21)
+ #define UART_STAT_MASK_TFIFO_EMPTY (1<<22)
+ #define UART_STAT_MASK_XMIT_BUSY (1<<25)
+ #define UART_STAT_MASK_RECV_BUSY (1<<26)
+#define P_UART_MISC(uart_base) P_UART(uart_base,UART_MISC )
+
+
+#ifndef CONFIG_SERIAL_STP_BITS
+#define CONFIG_SERIAL_STP_BITS 1 // 1 , 2
+#endif
+#if CONFIG_SERIAL_STP_BITS==1
+#define UART_STP_BIT UART_CNTL_MASK_STP_1BIT
+#elif CONFIG_SERIAL_STP_BITS==2
+#define UART_STP_BIT UART_CNTL_MASK_STP_2BIT
+#else
+#error CONFIG_SERIAL_STP_BITS wrong
+#endif
+
+
+#ifndef CONFIG_SERIAL_PRTY_TYPE
+#define CONFIG_SERIAL_PRTY_TYPE 0 //0 ,2 ,3
+#endif
+#if CONFIG_SERIAL_PRTY_TYPE==0
+#define UART_PRTY_BIT 0
+#elif CONFIG_SERIAL_PRTY_TYPE==2
+#define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_EVEN)
+#elif CONFIG_SERIAL_PRTY_TYPE==3
+#define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_ODD)
+#else
+#error CONFIG_SERIAL_PRTY_TYPE wrong
+#endif
+
+#ifndef CONFIG_SERIAL_CHAR_LEN
+#define CONFIG_SERIAL_CHAR_LEN 8 //5,6,7,8
+#endif
+#if CONFIG_SERIAL_CHAR_LEN==5
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_5BIT
+#elif CONFIG_SERIAL_CHAR_LEN==6
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_6BIT
+#elif CONFIG_SERIAL_CHAR_LEN==7
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_7BIT
+#elif CONFIG_SERIAL_CHAR_LEN==8
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_8BIT
+#else
+#error CONFIG_SERIAL_CHAR_LEN wrong
+#endif
+#define UART_CONTROL_SET(baud,clk81) \
+ (((clk81)/(baud*4) -1) \
+ | UART_STP_BIT \
+ | UART_PRTY_BIT \
+ | UART_CHAR_LEN \
+ | UART_CNTL_MASK_TX_EN \
+ | UART_CNTL_MASK_RX_EN \
+ | UART_CNTL_MASK_RST_TX \
+ | UART_CNTL_MASK_RST_RX \
+ | UART_CNTL_MASK_CLR_ERR )
+#endif
diff --git a/arch/arm/include/asm/arch-sc2/usb.h b/arch/arm/include/asm/arch-sc2/usb.h
new file mode 100644
index 0000000..f2669d5
--- /dev/null
+++ b/arch/arm/include/asm/arch-sc2/usb.h
@@ -0,0 +1,246 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __ARCH_ARM_MESON_USB_H_U_BOOT__
+#define __ARCH_ARM_MESON_USB_H_U_BOOT__
+
+#include <common.h>
+#include <asm/types.h>
+#include <asm/arch/io.h>
+#include <asm/arch/secure_apb.h>
+#include <generic-phy.h>
+#include <asm-generic/gpio.h>
+
+#define USB_PHY_PORT_MAX 1
+/* Phy register MACRO definitions */
+
+#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
+#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
+#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27)
+
+#define PHYUTMI_OTGDISABLE (1 << 6)
+#define PHYUTMI_FORCESUSPEND (1 << 1)
+#define PHYUTMI_FORCESLEEP (1 << 0)
+
+#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
+#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
+
+#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
+#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
+
+#define PHYCLKRST_SSC_EN (0x1 << 20)
+#define PHYCLKRST_REF_SSP_EN (0x1 << 19)
+#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18)
+
+#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
+
+#define PHYCLKRST_FSEL_MASK (0x3f << 5)
+#define PHYCLKRST_FSEL(_x) ((_x) << 5)
+#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
+#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
+#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
+#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
+
+#define PHYCLKRST_RETENABLEN (0x1 << 4)
+
+#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
+#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
+#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
+
+#define PHYCLKRST_PORTRESET (0x1 << 1)
+#define PHYCLKRST_COMMONONN (0x1 << 0)
+
+#define PHYPARAM0_REF_USE_PAD (0x1 << 31)
+#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
+#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
+
+#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
+#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
+
+#define PHYTEST_POWERDOWN_SSP (0x1 << 3)
+#define PHYTEST_POWERDOWN_HSP (0x1 << 2)
+
+#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2)
+
+#define FSEL_CLKSEL_24M (0x5)
+
+#define USB_PHY2_ENABLE 0x10000000
+#define USB_PHY2_RESET 0x20000000
+
+/* XHCI PHY register structure */
+#define PHY_REGISTER_SIZE 0x20
+
+struct phy_aml_usb2_priv {
+ unsigned int base_addr;
+ unsigned int reset_addr;
+ unsigned int dwc2_a_addr;
+ unsigned int u2_port_num;
+ unsigned int usbphy_reset_bit[8];
+ unsigned int usb_phy2_pll_base_addr[4];
+};
+
+struct phy_aml_usb3_priv {
+ unsigned int base_addr;
+ unsigned int usb3_port_num;
+ struct gpio_desc desc;
+};
+
+/* Register definitions */
+typedef struct u2p_aml_regs {
+ volatile uint32_t u2p_r0;
+ volatile uint32_t u2p_r1;
+} u2p_aml_regs_t;
+
+typedef union u2p_r0 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned host_device:1;
+ unsigned power_ok:1;
+ unsigned hast_mode:1;
+ unsigned POR:1;
+ unsigned IDPULLUP0:1;
+ unsigned DRVVBUS0:1;
+ unsigned reserved:26;
+ } b;
+} u2p_r0_t;
+
+typedef union u2p_r1 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned phy_rdy:1;
+ unsigned IDDIG0:1;
+ unsigned OTGSESSVLD0:1;
+ unsigned VBUSVALID0:1;
+ unsigned reserved:28;
+ } b;
+} u2p_r1_t;
+
+
+typedef struct usb_aml_regs {
+ volatile uint32_t usb_r0;
+ volatile uint32_t usb_r1;
+ volatile uint32_t usb_r2;
+ volatile uint32_t usb_r3;
+ volatile uint32_t usb_r4;
+ volatile uint32_t usb_r5;
+} usb_aml_regs_t;
+
+typedef union usb_r0 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned reserved:17;
+ unsigned p30_lane0_tx2rx_loopback:1;
+ unsigned p30_lane0_ext_pclk_reg:1;
+ unsigned p30_pcs_rx_los_mask_val:10;
+ unsigned u2d_ss_scaledown_mode:2;
+ unsigned u2d_act:1;
+ } b;
+} usb_r0_t;
+
+typedef union usb_r1 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned u3h_bigendian_gs:1;
+ unsigned u3h_pme_en:1;
+ unsigned u3h_hub_port_overcurrent:3;
+ unsigned reserved_1:2;
+ unsigned u3h_hub_port_perm_attach:3;
+ unsigned reserved_2:2;
+ unsigned u3h_host_u2_port_disable:2;
+ unsigned reserved_3:2;
+ unsigned u3h_host_u3_port_disable:1;
+ unsigned u3h_host_port_power_control_present:1;
+ unsigned u3h_host_msi_enable:1;
+ unsigned u3h_fladj_30mhz_reg:6;
+ unsigned p30_pcs_tx_swing_full:7;
+ } b;
+} usb_r1_t;
+
+typedef union usb_r2 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned reserved:20;
+ unsigned p30_pcs_tx_deemph_3p5db:6;
+ unsigned p30_pcs_tx_deemph_6db:6;
+ } b;
+} usb_r2_t;
+
+typedef union usb_r3 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned p30_ssc_en:1;
+ unsigned p30_ssc_range:3;
+ unsigned p30_ssc_ref_clk_sel:9;
+ unsigned p30_ref_ssp_en:1;
+ unsigned reserved:18;
+ } b;
+} usb_r3_t;
+
+typedef union usb_r4 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned p21_PORTRESET0:1;
+ unsigned p21_SLEEPM0:1;
+ unsigned mem_pd:2;
+ unsigned p21_only:1;
+ unsigned reserved:27;
+ } b;
+} usb_r4_t;
+
+typedef union usb_r5 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned iddig_sync:1;
+ unsigned iddig_reg:1;
+ unsigned iddig_cfg:2;
+ unsigned iddig_en0:1;
+ unsigned iddig_en1:1;
+ unsigned iddig_curr:1;
+ unsigned usb_iddig_irq:1;
+ unsigned iddig_th:8;
+ unsigned iddig_cnt:8;
+ unsigned reserved:8;
+ } b;
+} usb_r5_t;
+
+/* usb id mode, only after M2
+ mode = 0 : HARDWARE
+ mode = 1 : SW_HOST
+ mode = 2 : SW_DEVICE
+ */
+#define USB_ID_MODE_HARDWARE (1)
+#define USB_ID_MODE_SW_HOST (2)
+#define USB_ID_MODE_SW_DEVICE (3)
+int usb2_phy_tuning(uint32_t phy2_pll_base, int port);
+void set_usb_pll(uint32_t phy2_pll_base);
+int usb_save_phy_dev (unsigned int number, struct phy *phy);
+int usb2_phy_init (struct phy *phy);
+unsigned int usb_get_dwc_a_base_addr(void);
+unsigned int usb_get_device_mode_phy_base(void);
+void usb_phy_tuning_reset(void);
+void usb_device_mode_init(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-t7/acs.h b/arch/arm/include/asm/arch-t7/acs.h
new file mode 100644
index 0000000..7727f14
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/acs.h
@@ -0,0 +1,40 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __ACS_H
+#define __ACS_H
+
+#define CHIP_PARAM_MAGIC 0x50696863 //"chiP"
+#define DEV_PARAM_MAGIC 0x50766564 //"devP"
+
+#define CHIP_PARAM_VERSION 0x1
+#define DEV_PARAM_VERSION 0x1
+
+#ifndef __ASSEMBLY__
+
+typedef struct dev_param_hdr {
+ unsigned int magic;
+ unsigned int version;
+
+ char bl2_regs_magic[6];
+ unsigned short bl2_regs_length;
+
+ char board_clk_magic[6];
+ unsigned short board_clk_length;
+
+ char opt_reg_magic[6];
+ unsigned short opt_reg_length;
+
+ char sto_set_magic[6];
+ unsigned short sto_set_length;
+
+ char ddr_set_magic[6];
+ unsigned short ddr_set_length;
+
+ unsigned int RFU[4];
+} __attribute__ ((packed)) dev_param_hdr_t;
+
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-t7/bl31_apis.h b/arch/arm/include/asm/arch-t7/bl31_apis.h
new file mode 100644
index 0000000..4c3204f
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/bl31_apis.h
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ * Trustzone API
+ *
+ * Copyright (C) 2012 Amlogic, Inc.
+ *
+ * Author: Platform-SH@amlogic.com
+ *
+ */
+
+#ifndef __GXBB_BL31_APIS_H
+#define __GXBB_BL31_APIS_H
+
+#include <asm/arch/io.h>
+
+/*#define SRAM_READ 0x82000010
+#define CORE_RD_REV1 0x82000011
+#define SRAM_ACS_READ 0x82000012
+#define SRAM_ACS_INDIRECT_READ 0x82000013*/
+
+#define GET_SHARE_MEM_INPUT_BASE 0x82000020
+#define GET_SHARE_MEM_OUTPUT_BASE 0x82000021
+#define GET_REBOOT_REASON 0x82000022
+#define GET_SHARE_STORAGE_IN_BASE 0x82000023
+#define GET_SHARE_STORAGE_OUT_BASE 0x82000024
+#define GET_SHARE_STORAGE_BLOCK_BASE 0x82000025
+#define GET_SHARE_STORAGE_MESSAGE_BASE 0x82000026
+#define GET_SHARE_STORAGE_BLOCK_SIZE 0x82000027
+#define SET_STORAGE_INFO 0x82000028
+#define SET_STORAGE_BOOTSEQUENCE 0x82000029
+#define SET_REBOOT_REASON 0x82000049
+
+/* Set Reboot Reason then Reboot*/
+#define PSCI_SYS_REBOOT 0x84000009
+
+/* SECUREOS DEFINITION*/
+/* SMC Identifiers for non-secure world functions */
+#define CALL_TRUSTZONE_HAL_API 0x5
+
+/* EFUSE */
+#define EFUSE_READ 0x82000030
+#define EFUSE_WRITE 0x82000031
+#define EFUSE_WRITE_PATTERN 0x82000032
+#define EFUSE_USER_MAX 0x82000033
+
+#define DEBUG_EFUSE_WRITE_PATTERN 0x820000F0
+#define DEBUG_EFUSE_READ_PATTERN 0x820000F1
+
+/* JTAG*/
+#define JTAG_ON 0x82000040
+#define JTAG_OFF 0x82000041
+
+#define SET_USB_BOOT_FUNC 0x82000043
+ /* USB BOOT FUNC sub command list*/
+ #define CLEAR_USB_BOOT 1
+ #define FORCE_USB_BOOT 2
+ #define RUN_COMD_USB_BOOT 3
+ #define PANIC_DUMP_USB_BOOT 4
+
+#define GET_CHIP_ID 0x82000044
+
+/* tsensor calibration data */
+#define TSENSOR_CALI_SET 0x8200004C
+#define TSENSOR_CALI_READ 0x82000047
+
+/*oscring efuse value get */
+#define OSCRING_EFUSE_GET 0x8200004D
+/* Security Key*/
+#define SECURITY_KEY_QUERY 0x82000060
+#define SECURITY_KEY_READ 0x82000061
+#define SECURITY_KEY_WRITE 0x82000062
+#define SECURITY_KEY_TELL 0x82000063
+#define SECURITY_KEY_VERIFY 0x82000064
+#define SECURITY_KEY_STATUS 0x82000065
+#define SECURITY_KEY_NOTIFY 0x82000066
+#define SECURITY_KEY_LIST 0x82000067
+#define SECURITY_KEY_REMOVE 0x82000068
+#define SECURITY_KEY_NOTIFY_EX 0x82000069
+#define SECURITY_KEY_SET_ENCTYPE 0x8200006A
+#define SECURITY_KEY_GET_ENCTYPE 0x8200006B
+#define SECURITY_KEY_VERSION 0x8200006C
+
+/*viu probe en*/
+#define VIU_PREOBE_EN 0x82000080
+/*set boot first timeout*/
+#define SET_BOOT_FIRST 0x82000087
+
+/* KEYMASTER */
+#define SET_BOOT_PARAMS 0x82000072
+#define SHA256_DIGEST_SIZE 32
+typedef struct {
+ uint32_t device_locked;
+ uint32_t verified_boot_state;
+ uint8_t verified_boot_key[SHA256_DIGEST_SIZE];
+ uint8_t verified_boot_hash[SHA256_DIGEST_SIZE];
+} keymaster_boot_params;
+
+/* Secure HAL APIs */
+#define TRUSTZONE_HAL_API_SRAM 0x400
+
+/*start hifi4 */
+#define START_HIFI4 0x82000090
+#define DSP_SEC_POWERSET 0x82000092
+
+
+#define SRAM_HAL_API_CHECK_EFUSE 0x403
+struct sram_hal_api_arg {
+ unsigned int cmd;
+ unsigned int req_len;
+ unsigned int res_len;
+ unsigned long req_phy_addr;
+ unsigned long res_phy_addr;
+ unsigned long ret_phy_addr;
+};
+
+#define JTAG_STATE_ON 0
+#define JTAG_STATE_OFF 1
+#define JTAG_M3_AO 0
+#define JTAG_M3_EE 1
+#define JTAG_A53_AO 2
+#define JTAG_A53_EE 3
+#define CLUSTER_BIT 2
+
+
+/* AVB2 */
+#define GET_AVBKEY_FROM_FIP 0x820000b0
+
+/////////////////////////////////////////////////////////////////////////////////
+#define AML_DATA_PROCESS (0x820000FF)
+ #define AML_D_P_W_EFUSE_SECURE_BOOT (0x10)
+ #define AML_D_P_W_EFUSE_PASSWORD (0x11)
+ #define AML_D_P_W_EFUSE_CUSTOMER_ID (0x12)
+ #define AML_D_P_W_EFUSE_AMLOGIC (0x20)
+ #define AML_D_P_IMG_DECRYPT (0x40)
+ #define AML_D_P_UPGRADE_CHECK (0x80)
+
+#define GXB_EFUSE_PATTERN_SIZE (0x2 << 9)
+#define GXB_IMG_SIZE (24<<20)
+#define GXB_IMG_LOAD_ADDR (0x1080000)
+ #define GXB_IMG_DEC_KNL (1<<0)
+ #define GXB_IMG_DEC_RMD (1<<1)
+ #define GXB_IMG_DEC_DTB (1<<2)
+ #define GXB_IMG_DEC_ALL (GXB_IMG_DEC_KNL|GXB_IMG_DEC_RMD|GXB_IMG_DEC_DTB)
+
+#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+void aml_set_jtag_state(unsigned state, unsigned select);
+unsigned aml_get_reboot_reason(void);
+unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2);
+void aml_set_bootsequence(uint32_t val);
+void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2);
+unsigned long aml_sec_boot_check(unsigned long ,unsigned long ,unsigned long,unsigned long );
+long get_sharemem_info(unsigned long);
+void set_usb_boot_function(unsigned long command);
+void aml_system_off(void);
+
+void bl31_get_chipid(unsigned int *, unsigned int *,
+ unsigned int *, unsigned int *);
+void set_viu_probe_enable(void);
+void wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value);
+void power_set_dsp(unsigned int id, unsigned int powerflag);
+void init_dsp(unsigned int id,unsigned int addr,unsigned int cfg0);
+void set_boot_first_timeout(uint64_t arg0);
+int bl31_get_cornerinfo(uint8_t *outbuf, int size);
+int32_t set_boot_params(const keymaster_boot_params*);
+int32_t get_avbkey_from_fip(uint8_t *buf, uint32_t buflen);
+#endif
diff --git a/arch/arm/include/asm/arch-t7/board_id.h b/arch/arm/include/asm/arch-t7/board_id.h
new file mode 100644
index 0000000..6488771
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/board_id.h
@@ -0,0 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+unsigned int get_board_id(void);
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-t7/clk_measure_tab.h b/arch/arm/include/asm/arch-t7/clk_measure_tab.h
new file mode 100644
index 0000000..a072ee8
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/clk_measure_tab.h
@@ -0,0 +1,205 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _ARCH_MESON_T7_MEASURE_H_
+#define _ARCH_MESON_T7_MEASURE_H_
+
+static const char* clk_msr_table[] = {
+ [0] = "cts_sys_clk",
+ [1] = "cts_axi_clk",
+ [2] = "cts_rtc_clk",
+ [3] = "cts_dspa_clk",
+ [4] = "cts_dspb_clk",
+ [5] = "cts_mali_clk",
+ [6] = "sys_cpu_clk_div16",
+ [7] = "cts_ceca_clk",
+ [8] = "cts_cecb_clk",
+ [10] = "fclk_div5",
+ [11] = "mp0_clk_out",
+ [12] = "mp1_clk_out",
+ [13] = "mp2_clk_out",
+ [14] = "mp3_clk_out",
+ [15] = "mpll_clk_50m",
+ [16] = "pcie_clk_inp",
+ [17] = "pcie_clk_inn",
+ [18] = "mpll_clk_test_out",
+ [19] = "hifi_pll_clk",
+ [20] = "gp0_pll_clk",
+ [21] = "gp1_pll_clk",
+ [22] = "eth_mppll_50m_ckout",
+ [23] = "sys_pll_div16",
+ [24] = "ddr_dpll_pt_clk",
+ [25] = "earcrx_pll_ckout",
+ [26] = "paie1_clk_inp",
+ [27] = "paie1_clk_inn",
+ [28] = "cts_amlgdc_clk",
+ [29] = "cts_gdc_clk",
+ [30] = "mod_eth_phy_ref_clk",
+ [31] = "mod_eth_tx_clk",
+ [32] = "cts_eth_clk125Mhz",
+ [33] = "cts_eth_clk_rmii",
+ [34] = "co_clkin_to_mac",
+ [35] = "mod_eth_rx_clk_rmii",
+ [36] = "co_rx_clk",
+ [37] = "co_tx_clk",
+ [38] = "eth_phy_rxclk",
+ [39] = "eth_phy_plltxclk",
+ [40] = "ephy_test_clk",
+ [41] = "cts_dsi_b_meas_clk",
+ [42] = "hdmirx_apll_clk_out",
+ [43] = "hdmirx_tmds_clk",
+ [44] = "hdmirx_cable_clk",
+ [45] = "hdmirx_apll_clk_audio",
+ [46] = "hdmirx_5m_clk",
+ [47] = "hdmirx_2m_clk",
+ [48] = "hdmirx_cfg_clk",
+ [49] = "hdmirx_hdcp2x_eclk",
+ [50] = "vid_pll0_div_clk_out",
+ [51] = "hdmi_vid_pll_clk",
+ [54] = "cts_vdac_clk",
+ [55] = "cts_vpu_clk_buf",
+ [56] = "mod_tcon_clko",
+ [57] = "lcd_an_clk_ph2",
+ [58] = "lcd_an_clk_ph3",
+ [59] = "cts_hdmi_tx_pixel_clk",
+ [60] = "cts_vdin_meas_clk",
+ [61] = "cts_vpu_clk",
+ [62] = "cts_vpu_clkb",
+ [63] = "cts_vpu_clkb_tmp",
+ [64] = "cts_vpu_clkc",
+ [65] = "cts_vid_lock_clk",
+ [66] = "cts_vapbclk",
+ [67] = "cts_ge2d_clk",
+ [68] = "cts_aud_pll_clk",
+ [69] = "cts_aud_sck",
+ [70] = "cts_dsi_a_meas_clk",
+ [72] = "cts_mipi_csi_phy",
+ [73] = "cts_mipi_isp_clk",
+ [76] = "hdmitx_tmds_clk",
+ [77] = "cts_hdmitx_sys_clk",
+ [78] = "cts_hdmitx_fe_clk",
+ [80] = "cts_hdmitx_prif_clk",
+ [81] = "cts_hdmitx_200m_clk",
+ [82] = "cts_hdmitx_aud_clk",
+ [83] = "cts_hdmitx_pnx_clk",
+ [84] = "cts_spicc5",
+ [85] = "cts_spicc4",
+ [86] = "cts_spicc3",
+ [87] = "cts_spicc2",
+ [93] = "cts_vdec_clk",
+ [94] = "cts_wave521_aclk",
+ [95] = "cts_wave521_cclk",
+ [96] = "cts_wave521_bclk",
+ [97] = "cts_hcodec_clk",
+ [98] = "cts_hevcb_clk",
+ [99] = "cts_hevcf_clk",
+ [100] = "cts_hdmi_aud_pll_clk",
+ [101] = "cts_hdmi_acr_ref_clk",
+ [102] = "cts_hdmi_meter_clk",
+ [103] = "cts_hdmi_vid_clk",
+ [104] = "cts_hdmi_aud_clk",
+ [105] = "cts_hdmi_dsd_clk",
+ [108] = "cts_dsi1_phy_clk",
+ [109] = "cts_dsi0_phy_clk",
+ [110] = "cts_sc_clk(smartcard",
+ [111] = "cts_sar_adc_clk",
+ [113] = "cts_sd_emmc_C_clk(nand",
+ [114] = "cts_sd_emmc_B_clk",
+ [115] = "cts_sd_emmc_A_clk",
+ [116] = "gpio_msr_clk",
+ [117] = "cts_spicc_1_clk",
+ [118] = "cts_spicc_0_clk",
+ [118] = "cts_anakin_clk",
+ [121] = "cts_ts_clk(temp sensor",
+ [122] = "ts_a73_clk",
+ [123] = "ts_a53_clk",
+ [124] = "ts_nna_clk",
+ [130] = "audio_vad_clk",
+ [131] = "acodec_dac_clk_x128",
+ [132] = "audio_locker_out_clk",
+ [133] = "audio_locker_in_clk",
+ [134] = "audio_tdmout_c_sclk",
+ [135] = "audio_tdmout_b_sclk",
+ [136] = "audio_tdmout_a_sclk",
+ [137] = "audio_tdmin_lb_sclk",
+ [138] = "audio_tdmin_c_sclk",
+ [139] = "audio_tdmin_b_sclk",
+ [140] = "audio_tdmin_a_sclk",
+ [141] = "audio_resamplea_clk",
+ [142] = "audio_pdm_sysclk",
+ [143] = "audio_spdifoutb_mst_clk",
+ [144] = "audio_spdifout_mst_clk",
+ [145] = "audio_spdifin_mst_clk",
+ [146] = "audio_pdm_dclk",
+ [147] = "audio_resampleb_clk",
+ [148] = "earcrx_pll_dmac_ck",
+ [156] = "pwm_ao_h_clk",
+ [157] = "pwm_ao_g_clk",
+ [158] = "pwm_ao_f_clk",
+ [159] = "pwm_ao_e_clk",
+ [160] = "pwm_ao_d_clk",
+ [161] = "pwm_ao_c_clk",
+ [162] = "pwm_ao_b_clk",
+ [163] = "pwm_ao_a_clk",
+ [164] = "pwm_f_clk",
+ [165] = "pwm_e_clk",
+ [166] = "pwm_d_clk",
+ [167] = "pwm_c_clk",
+ [168] = "pwm_b_clk",
+ [169] = "pwm_a_clk",
+ [170] = "cts_ACLKM",
+ [171] = "mclk_pll_clk",
+ [172] = "a73_sys_pll_div16",
+ [173] = "a73_cpu_clk_div16",
+ [176] = "rng_ring_0",
+ [177] = "rng_ring_1",
+ [178] = "rng_ring_2",
+ [179] = "rng_ring_3",
+ [180] = "am_ring_out0",
+ [181] = "am_ring_out1",
+ [182] = "am_ring_out2",
+ [183] = "am_ring_out3",
+ [184] = "am_ring_out4",
+ [185] = "am_ring_out5",
+ [186] = "am_ring_out6",
+ [187] = "am_ring_out7",
+ [188] = "am_ring_out8",
+ [189] = "am_ring_out9",
+ [190] = "am_ring_out10",
+ [191] = "am_ring_out11",
+ [192] = "am_ring_out12",
+ [193] = "am_ring_out13",
+ [194] = "am_ring_out14",
+ [195] = "am_ring_out15",
+ [196] = "am_ring_out16",
+ [197] = "am_ring_out17",
+ [198] = "am_ring_out18",
+ [199] = "am_ring_out19",
+ [200] = "mipi_csi_phy0",
+ [201] = "mipi_csi_phy1",
+ [202] = "mipi_csi_phy2",
+ [203] = "mipi_csi_phy3",
+ [204] = "vid_pll1_div_clk",
+ [205] = "vid_pll2_div_clk",
+ [206] = "am_ring_out20",
+ [207] = "am_ring_out21",
+ [208] = "am_ring_out22",
+ [209] = "am_ring_out23",
+ [210] = "am_ring_out24",
+ [211] = "am_ring_out25",
+ [212] = "am_ring_out26",
+ [213] = "am_ring_out27",
+ [214] = "am_ring_out28",
+ [215] = "am_ring_out29",
+ [216] = "am_ring_out30",
+ [217] = "am_ring_out31",
+ [218] = "am_ring_out32",
+ [219] = "cts_enc0_if_clk",
+ [220] = "cts_enc2_clk",
+ [221] = "cts_enc1_clk",
+ [222] = "cts_enc0_clk"
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-t7/clock.h b/arch/arm/include/asm/arch-t7/clock.h
new file mode 100644
index 0000000..2de3146
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/clock.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __CLOCK_T7_H
+#define __CLOCK_T7_H
+
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe000000
+// -----------------------------------------------
+#define T7_CLKCTRL_NAND_CLK_CTRL (0x005a << 2)
+#define T7_CLKCTRL_SD_EMMC_CLK_CTRL (0x005b << 2)
+#define T7_CLKCTRL_SPICC_CLK_CTRL (0x005d << 2)
+#define T7_CLKCTRL_SAR_CLK_CTRL0 (0x005f << 2)
+#define T7_CLKCTRL_SPICC_CLK_CTRL1 (0x0070 << 2)
+#define T7_CLKCTRL_SPICC_CLK_CTRL2 (0x0071 << 2)
+
+//========================================================================
+
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe008000
+// -----------------------------------------------
+#define T7_ANACTRL_SYSPLL_CTRL0 ((0x00 << 2) + 0x8000)
+#define T7_ANACTRL_SYSPLL_CTRL1 ((0x01 << 2) + 0x8000)
+#define T7_ANACTRL_SYSPLL_CTRL2 ((0x02 << 2) + 0x8000)
+#define T7_ANACTRL_SYSPLL_CTRL3 ((0x03 << 2) + 0x8000)
+#define T7_ANACTRL_SYSPLL_CTRL4 ((0x04 << 2) + 0x8000)
+#define T7_ANACTRL_SYSPLL_CTRL5 ((0x05 << 2) + 0x8000)
+#define T7_ANACTRL_SYSPLL_CTRL6 ((0x06 << 2) + 0x8000)
+#define T7_ANACTRL_SYSPLL_STS ((0x07 << 2) + 0x8000)
+#define T7_ANACTRL_FIXPLL_CTRL0 ((0x10 << 2) + 0x8000)
+#define T7_ANACTRL_FIXPLL_CTRL1 ((0x11 << 2) + 0x8000)
+#define T7_ANACTRL_FIXPLL_CTRL2 ((0x12 << 2) + 0x8000)
+#define T7_ANACTRL_FIXPLL_CTRL3 ((0x13 << 2) + 0x8000)
+#define T7_ANACTRL_FIXPLL_CTRL4 ((0x14 << 2) + 0x8000)
+#define T7_ANACTRL_FIXPLL_CTRL5 ((0x15 << 2) + 0x8000)
+#define T7_ANACTRL_FIXPLL_CTRL6 ((0x16 << 2) + 0x8000)
+#define T7_ANACTRL_FIXPLL_STS ((0x17 << 2) + 0x8000)
+#define T7_ANACTRL_GP0PLL_CTRL0 ((0x20 << 2) + 0x8000)
+//========================================================================
+
+/*
+ * CPU clok register offset
+ * APB_BASE: APB1_BASE_ADDR = 0xfe007400
+ */
+
+#include <dt-bindings/clock/t7-clkc.h>
+#define NR_CLKS (CLKID_END_BASE)
+
+#endif /* __CLOCK_T7_H */
diff --git a/arch/arm/include/asm/arch-t7/core.h b/arch/arm/include/asm/arch-t7/core.h
new file mode 100644
index 0000000..97fd220
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/core.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __CORE_H__
+#define __CORE_H__
+
+int get_core_mpidr(unsigned int cpuid);
+int get_core_idx(unsigned int mpidr);
+int get_core_max(void);
+
+#endif
diff --git a/arch/arm/include/asm/arch-t7/cpu.h b/arch/arm/include/asm/arch-t7/cpu.h
new file mode 100644
index 0000000..06b5341
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/cpu.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _CPU_H
+#define _CPU_H
+/* #include <config.h> */
+/* #include <asm/plat-cpu.h> */
+/* #include <asm/arch/ddr.h> */
+
+#if 0
+#define CONFIG_AML_MESON 1
+#define CONFIG_AML_MESON_GX 1
+#define CONFIG_AML_MESON_G12A 1
+#endif
+
+/*enable viu probe*/
+#if 0
+#define CONFIG_CMD_VIU_PROBE 1
+#endif
+
+/* for uboot envrionment use */
+#define CONFIG_DDR_SIZE 2048
+
+/* dram */
+#define PHYS_SDRAM_1_BASE 0x00000000UL
+#define PHYS_SDRAM_1_SIZE 0x80000000UL
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1_BASE
+
+#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1_BASE + CONFIG_SYS_TEXT_BASE)
+
+/* console/print buffer */
+#define CONFIG_SYS_CBSIZE 512
+#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
+
+/* Generic Timer Definitions */
+#define COUNTER_FREQUENCY (0x1800000) /* 24MHz */
+
+/* use "hush" command parser */
+#if 0
+#define CONFIG_SYS_HUSH_PARSER
+#endif
+
+#if 0
+#define CONFIG_DTB_MEM_ADDR 0x1000000
+#endif
+
+#if 0
+#define CONFIG_AML_CUSTOMER_ID (0)
+#endif
+
+#define AML_CUSTOMER_ID (0)
+
+//#define CONFIG_SILENT_CONSOLE
+//#define CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC
+//#define CONFIG_SILENT_U_BOOT_ONLY
+
+/* 2018.03.19 new compress solution, only support BL33 LZ4 compress */
+#define CONFIG_AML_BL33_COMPRESS_ENABLE 1
+
+/* 2018.03.19 G12A only support v3 format for normal & secure boot */
+#define CONFIG_AML_SECURE_BOOT_V3 1
+
+#define NR_CPUS 4
+
+#define CPU_ID_REG SYSCTRL_SEC_STATUS_REG0
+#define PACKAGE_ID_MASK 0xFF
+
+#define MIPI_DSI_REGISTER 1
+#define MIPI_DSI_BASE 0xfe074000L
+#define MIPI_DSI_PHY_BASE 0xfe014000L
+#define MIPI_DSI_B_BASE 0xfe072000L
+#define MIPI_DSI_B_PHY_BASE 0xfe016000L
+#define EDPTX0_BASE 0xfe0b0000L
+#define EDPTX1_BASE 0xfe0b2000L
+
+/*C1 SoC secure boot solution default not support AES algorithm*/
+//#define CONFIG_AML_CRYPTO_AES 1
+
+
+/*Flag for enable AES key generate to EFUSE pattern, with this flag only
+AES key will be generated to EFUSE pattern, it can be used for use case
+like the AES key not ready when secure boot enabled for the first time.
+*/
+//#define CONFIG_AML_EFUSE_GEN_AES_ONLY 1
+
+#endif /* _CPU_H */
diff --git a/arch/arm/include/asm/arch-t7/cpu_config.h b/arch/arm/include/asm/arch-t7/cpu_config.h
new file mode 100644
index 0000000..edf7983
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/cpu_config.h
@@ -0,0 +1,85 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _BOOT_ROM_CONFIG_H_
+#define _BOOT_ROM_CONFIG_H_
+
+/***********************************************************
+ * The following constants are GXBB definition
+ **********************************************************/
+#define ROMBOOT_START 0xD9040000
+#define ROM_SIZE (64*1024)
+#define ROMBOOT_END (ROMBOOT_START+ROM_SIZE)
+
+/***********************************************************
+ * AHB-SRAM Total Size 80KB, layout shown as below
+ *
+ * ROMCODE use the top 32KB
+ *
+ * [ 128] 0xD901_3F80 - 0xD901_3FFF Reserved
+ * [ 128] 0xD901_3F00 - 0xD901_3F7F CPUs Boot Entry
+ * [ 256] 0xD901_3E00 - 0xD901_3EFF Debug Info
+ * [ 512] 0xD901_3C00 - 0xD901_3DFF eFuse mirror
+ * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3)
+ * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) *
+ * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) *
+ * [ 26K] 0xD900_C800 - 0xD901_2FFF BL1 Stack, BSS
+ * [ 1K] 0xD900_C400 - 0xD900_C7FF NAND, USB Buffer
+ * [ 1K] 0xD900_C000 - 0xD900_C3FF Reserved
+ *
+ **********************************************************/
+#define RAM_START 0xD9000000
+#define RAM_SIZE (80 * 1024)
+#define BL1_RAM_START (RAM_START + 0xC000)
+#define BL1_RAM_SIZE (32 * 1024)
+#define BL1_RAM_END (BL1_RAM_START + BL1_RAM_SIZE)
+#define BSS_START (BL1_RAM_START + (2 * 1024))
+#define BSS_SIZE (18 * 1024)
+#define _STACK_END (BSS_START + BSS_SIZE + 8*1024)
+#define BL1_EFUSE_MIRROR (BL1_RAM_END - 1024)
+#define P_SHARED_EFUSE_MIRROR (volatile uint32_t *)(BL1_EFUSE_MIRROR)
+#define BL1_DEBUG_BUFFER (BL1_RAM_END - 512)
+#define CPU_BOOT_ENTRY (BL1_DEBUG_BUFFER + 256)
+#define P_SHARED_DEBUG_BUFF (volatile uint32_t *)(BL1_DEBUG_BUFFER)
+#define BL1_SEC_MBX (BL1_RAM_END - 2*1024)
+#define BL1_NAND_BUFF (BL1_RAM_START + 1024)
+#define BL1_USB_BUFF (BL1_NAND_BUFF)
+
+#define MEMORY_LOC RAM_START
+
+#define SRAM_DEBUG_BUFF_SIZE 256
+
+/* BL2 SPL size */
+#define BL2_SIZE (254 * 1024)
+
+//for signature test
+//#define CONFIG_AML_SIG_TEST_BUILD
+
+/* Software SHA2 */
+#define CONFIG_SHA2_SW
+
+/* Hardware SHA2 */
+#define CONFIG_SHA2_HW
+#define SHA2_HW_UPDATE_API
+
+/* Keep timer config in conf.h */
+#define CONFIG_TIMER
+
+/* Bootrom debug info */
+#define CONFIG_DEBUG_INFO
+
+/* Mincrypt RSA library */
+//#define CONFIG_MINCRYPT
+
+/* PolarSSL RSA library */
+#define CONFIG_POLARSSL_RSA
+
+#ifdef CONFIG_POLARSSL_RSA
+#ifndef CONFIG_MALLOC
+#define CONFIG_MALLOC
+#endif /* ! CONFIG_MALLOC */
+#endif /* CONFIG_POLARSSL_RSA */
+
+#endif /* _BOOT_ROM_CONFIG_H_ */
diff --git a/arch/arm/include/asm/arch-t7/cpu_reset.h b/arch/arm/include/asm/arch-t7/cpu_reset.h
new file mode 100644
index 0000000..46f9abf
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/cpu_reset.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _BOOT_ROM_WATCHDOG_H
+#define _BOOT_ROM_WATCHDOG_H
+#include <asm/arch/secure_apb.h>
+
+void reset_system(void);
+
+/* uboot reset interface */
+void reset_cpu(unsigned long flag);
+
+#endif /* _BOOT_ROM_WATCHDOG_H */
diff --git a/arch/arm/include/asm/arch-t7/cpu_sdio.h b/arch/arm/include/asm/arch-t7/cpu_sdio.h
new file mode 100644
index 0000000..46f366a
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/cpu_sdio.h
@@ -0,0 +1,239 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __CPU_SDIO_H__
+#define __CPU_SDIO_H__
+
+#define SD_EMMC_BASE_A 0xFFE03000
+#define SD_EMMC_BASE_B 0xFFE05000
+#define SD_EMMC_BASE_C 0xFFE07000
+
+#define SDIO_PORT_A 0
+#define SDIO_PORT_B 1
+#define SDIO_PORT_C 2
+
+struct sd_emmc_global_regs {
+ volatile uint32_t gclock; // 0x00
+ volatile uint32_t gdelay; // 0x04
+ volatile uint32_t gdelay1; //0x08
+ volatile uint32_t gadjust; // 0x0c
+ volatile uint32_t gcalout; // 0x10
+ volatile uint32_t reserved_14[11]; // 0x14~0x3c
+ volatile uint32_t gstart; // 0x40
+ volatile uint32_t gcfg; // 0x44
+ volatile uint32_t gstatus; // 0x48
+ volatile uint32_t girq_en; // 0x4c
+ volatile uint32_t gcmd_cfg; // 0x50
+ volatile uint32_t gcmd_arg; // 0x54
+ volatile uint32_t gcmd_dat; // 0x58
+ volatile uint32_t gcmd_rsp0; // 0x5c
+ volatile uint32_t gcmd_rsp1; // 0x60
+ volatile uint32_t gcmd_rsp2; // 0x64
+ volatile uint32_t gcmd_rsp3; // 0x68
+ volatile uint32_t reserved_6c; // 0x6c
+ volatile uint32_t gcurr_cfg; // 0x70
+ volatile uint32_t gcurr_arg; // 0x74
+ volatile uint32_t gcurr_dat; // 0x78
+ volatile uint32_t gcurr_rsp; // 0x7c
+ volatile uint32_t gnext_cfg; // 0x80
+ volatile uint32_t gnext_arg; // 0x84
+ volatile uint32_t gnext_dat; // 0x88
+ volatile uint32_t gnext_rsp; // 0x8c
+ volatile uint32_t grxd; // 0x90
+ volatile uint32_t gtxd; // 0x94
+ volatile uint32_t reserved_98[90]; // 0x98~0x1fc
+ volatile uint32_t gdesc[128]; // 0x200
+ volatile uint32_t gping[128]; // 0x400
+ volatile uint32_t gpong[128]; // 0x800
+};
+
+union sd_emmc_setup {
+ uint32_t d32;
+ struct {
+ unsigned bw:3;
+ unsigned fast:1;
+ unsigned par:3;
+ unsigned hcs:1;
+ unsigned sd:1;
+ unsigned sdhc:1;
+ unsigned type:6;
+ unsigned rca:16;
+ } b;
+};
+
+struct sd_emmc_desc_info{
+ uint32_t cmd_info;
+ uint32_t cmd_arg;
+ uint32_t data_addr;
+ uint32_t resp_addr;
+};
+
+struct cmd_cfg{
+ uint32_t length:9;
+ uint32_t block_mode:1;
+ uint32_t r1b:1;
+ uint32_t end_of_chain:1;
+ uint32_t timeout:4;
+ uint32_t no_resp:1;
+ uint32_t no_cmd:1;
+ uint32_t data_io:1;
+ uint32_t data_wr:1;
+ uint32_t resp_nocrc:1;
+ uint32_t resp_128:1;
+ uint32_t resp_num:1;
+ uint32_t data_num:1;
+ uint32_t cmd_index:6;
+ uint32_t error:1;
+ uint32_t owner:1;
+};
+
+struct sd_emmc_status{
+ uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire, for multiple block read, the CRC errors are ORed together.*/
+ uint32_t txd_err:1; /*[8] TX data CRC error, for multiple block write, any one of blocks CRC error. */
+ uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. The owner bit is ¡°0¡±, set cfg_ignore_owner to ignore this error.*/
+ uint32_t resp_err:1; /*[10] Response CRC error.*/
+ uint32_t resp_timeout:1; /*[11] No response received before time limit. The timeout limit is set by cfg_resp_timeout.*/
+ uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. The timeout limit is set by descriptor itself.*/
+ /* Consider the multiple block read/write, set the proper timeout limits.*/
+ uint32_t end_of_chain:1; /*[13] End of Chain IRQ, Normal IRQ. */
+ uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ, Normal IRQ, the descriptor chain execution keeps going on.*/
+ uint32_t irq_sdio:1; /*[15] SDIO device uses DAT[1] to request IRQ. */
+ uint32_t dat_i:8; /*[23:16] Input data signals. */
+ uint32_t cmd_i:1; /*[24] nput response signal. */
+ uint32_t ds:1; /*[25] Input data strobe. */
+ uint32_t bus_fsm:4; /*[29:26] BUS fsm */
+ uint32_t desc_wr_rdy:1; /*[30] Descriptor write back process is done and it is ready for CPU to read.*/
+ uint32_t core_rdy:1; /*[31] desc_busy or sd_emmc_irq or bus_fsm is not idle.*/
+};//__attribute__((__may_alias__));
+
+
+struct sd_emmc_clock{
+ uint32_t div:6; /*[5:0] Clock divider. Frequency = clock source/cfg_div, Maximum divider 63. */
+ /*Clock off: cfg_div==0, the clock is disabled */
+ /*Divider bypass: cfg_div==1, clock source is used as core clock without divider. */
+ uint32_t src:2; /*[7:6] Clock source, 0: Crystal 24MHz, 1: Fix PLL, 850MHz*/
+ /* 2: MPLL, <637MHz, used for 400MHz exactly. 3: different PLL */
+ uint32_t core_phase:2; /*[9:8] Core clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/
+ uint32_t tx_phase:2; /*[11:10] TX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/
+ uint32_t rx_phase:2; /*[13:12] RX clock phase. 0: 0 phase, 1: 90 phase, 2: 180 phase, 3: 270 phase.*/
+ uint32_t reserved14:2;
+ uint32_t tx_delay:6; /*[21:16] TX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/
+ uint32_t rx_delay:6; /*[27:22] RX clock delay line. 0: no delay, n: delay n*200ps. Maximum delay 3ns.*/
+ uint32_t always_on:1; /*[28] 1: Keep clock always on. 0: Clock on/off controlled by activities. */
+ /*Any APB3 access or descriptor execution will keep clock on.*/
+ uint32_t irq_sdio_sleep:1; /*[29] 1: enable IRQ sdio when in sleep mode. */
+ uint32_t irq_sdio_sleep_ds:1;/*[30] 1:enable ds as irq*/
+ uint32_t reserved26:1;
+};
+
+struct sd_emmc_delay{
+ uint32_t dat0:6; /*[3:0] Data 0 delay line. */
+ uint32_t dat1:6; /*[7:4] Data 1 delay line. */
+ uint32_t dat2:6; /*[11:8] Data 2 delay line. */
+ uint32_t dat3:6; /*[15:12] Data 3 delay line. */
+ uint32_t dat4:6; /*[19:16] Data 4 delay line. */
+ uint32_t spare:2;
+};
+
+struct sd_emmc_delay1{
+ uint32_t dat5:6; /*[23:20] Data 5 delay line. */
+ uint32_t dat6:6; /*[27:24] Data 6 delay line. */
+ uint32_t dat7:6; /*[31:28] Data 7 delay line. */
+ uint32_t dat8:6; /*[31:28] Data 7 delay line. */
+ uint32_t dat9:6; /*[31:28] Data 7 delay line. */
+ uint32_t spare:2;
+};
+
+struct sd_emmc_adjust{
+ uint32_t cmd_delay:4; /*[3:0] Command delay line. */
+ uint32_t ds_delay:4; /*[7:4] DS delay line. */
+ uint32_t cali_sel:4; /*[11:8] Select one signal to be tested.*/
+ /*Signals are labeled from 0 to 9 the same as delay lines. */
+ uint32_t cali_enable:1; /*[12] Enable calibration. */
+ uint32_t adj_enable:1; /*[13] Adjust interface timing by resampling the input signals. */
+ uint32_t cali_rise:1; /*[14] 1: test the rising edge. 0: test the falling edge. */
+ uint32_t ds_enable:1; /*[15] Sampling the DAT based on DS in HS400 mode*/
+ uint32_t adj_delay:6; /*[21:16] Resample the input signals when clock index==adj_delay. */
+ uint32_t adj_auto:1; /*[22] Use cali_dut first falling edge to adjust the timing */
+ /*set cali_enable to 1 to use this function*/
+ uint32_t reserved23:9;
+};
+
+
+struct sd_emmc_calout{
+ uint32_t cali_idx:6; /*[5:0] Calibration reading. The event happens at this index. */
+ uint32_t reserved6:1;
+ uint32_t cali_vld:1; /*[7] The reading is valid. */
+ uint32_t cali_setup:8; /*[15:8] Copied from BASE+0x8 [15:8] include cali_sel, cali_enable, adj_enable, cali_rise. */
+ uint32_t reserved16:16;
+};
+
+
+struct sd_emmc_start{
+ uint32_t init:1; /*[0] 1: Read descriptor from internal SRAM, limited to 32 descriptors. */
+ /* 0: Read descriptor from external DDR */
+ uint32_t busy:1; /*[1] 1: Start command chain execution process. 0: Stop */
+ uint32_t addr:30; /*[31:2] Descriptor address, the last 2 bits are 0, 4 bytes aligned. */
+ /* When internal SRAM is used, the valid address range is from 0x200~0x3ff */
+ /* When external DDR is used, the valid address is anywhere in DDR, the length of chain is unlimited.*/
+};//__attribute__((__may_alias__));
+
+
+struct sd_emmc_config{
+ uint32_t bus_width:2; /*[1:0] 0: 1 bit, 1: 4 bits, 2: 8 bits, 3: 2 bits (not supported)*/
+ uint32_t ddr:1; /*[2] 1: DDR mode, 0: SDR mode */
+ uint32_t dc_ugt:1; /*[3] 1: DDR access urgent, 0: DDR access normal. */
+ uint32_t bl_len:4; /*[7:4] Block length 2^cfg_bl_len, because internal buffer size is limited to 512 bytes, the cfg_bl_len <=9. */
+ uint32_t resp_timeout:4; /*[11:8] Wait response till 2^cfg_resp_timeout core clock cycles. Maximum 32768 core cycles. */
+ uint32_t rc_cc:4; /*[15:12] Wait response-command, command-command gap before next command, 2^cfg_rc_cc core clock cycles. */
+ uint32_t out_fall:1; /*[16] DDR mode only. The command and TXD start from rising edge. Set 1 to start from falling edge. */
+ uint32_t blk_gap_ip:1; /*[17] 1: Enable SDIO data block gap interrupt period. 0: Disabled.*/
+ uint32_t spare:1; /*[18] Spare, ??? need check*/
+ uint32_t ignore_owner:1; /*[19] Use this descriptor even if its owner bit is ¡°0¡±.*/
+ uint32_t chk_ds:1; /*[20] Check data strobe in HS400.*/
+ uint32_t cmd_low:1; /*[21] Hold CMD as output Low, eMMC boot mode.*/
+ uint32_t stop_clk:1; /*[22] 1: stop clock. 0: normal clock.*/
+ /*In normal mode, the clock is automatically on/off during reading mode to back off reading in case of*/
+ /*DDR slow response, stop clock is used in voltage switch.*/
+ uint32_t auto_clk:1; /*[23] 1: when BUS is idle and no descriptor is available, turn off clock, to save power.*/
+ /* 0: core clock is always on.*/
+ uint32_t txd_add_err:1; /*[24] TXD add error test*/
+ /*Test feature, should not be used in normal condition.*/
+ /*It will inverted the first CRC bits of the 3rd block.*/
+ /*Block index starts from 0, 1, 2, ¡*/
+ uint32_t txd_retry:1; /*[25] When TXD CRC error, host sends the block again.*/
+ /*The total number of retries of one descriptor is limited to 15, */
+ /*after 15 retries, the TXD_err is set to high.*/
+ uint32_t revd:8; /*[31:26] reved*/
+};//__attribute__((__may_alias__));
+
+
+struct sd_emmc_irq_en{
+ uint32_t rxd_err:8; /*[7:0] RX data CRC error per wire.*/
+ uint32_t txd_err:1; /*[8] TX data CRC error. */
+ uint32_t desc_err:1; /*[9] SD/eMMC controller doesn¡¯t own descriptor. */
+ uint32_t resp_err:1; /*[10] Response CRC error.*/
+ uint32_t resp_timeout:1; /*[11] No response received before time limit. */
+ uint32_t desc_timeout:1; /*[12] Descriptor execution time over time limit. */
+ uint32_t end_of_chain:1; /*[13] End of Chain IRQ. */
+ uint32_t desc_irq:1; /*[14] This descriptor requests an IRQ. */
+ uint32_t irq_sdio:1; /*[15] Enable sdio interrupt. */
+ uint32_t revd:16; /*[31:16] reved*/
+};
+
+struct sd_emmc_data_info{
+ uint32_t cnt:10; /*[9:0] Rxd words received from BUS. Txd words received from DDR.*/
+ uint32_t blk:9; /*[24:16] Rxd Blocks received from BUS. Txd blocks received from DDR.*/
+ uint32_t revd:30; /*[31:17] Reved. */
+};
+
+
+struct sd_emmc_card_info{
+ uint32_t txd_cnt:10; /*[9:0] Txd BUS cycle counter. */
+ uint32_t txd_blk:9; /*[24:16] Txd BUS block counter.*/
+ uint32_t revd:30; /*[31:17] Reved. */
+};
+
+#endif
diff --git a/arch/arm/include/asm/arch-t7/ddr.h b/arch/arm/include/asm/arch-t7/ddr.h
new file mode 100644
index 0000000..ad27855
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/ddr.h
@@ -0,0 +1,100 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <io.h>
+#include <stdint.h>
+#include <asm/arch/ddr_define.h>
+
+/* io defines */
+//#define wr_reg(addr, data) (*((volatile uint32_t *)addr))=(uint32_t)(uint64_t)(data)
+//#define rd_reg(addr) (*((volatile uint32_t *)(addr)))
+#define wr_reg(addr, data) writel(data, addr)
+#define rd_reg(addr) readl(addr)
+/*clear [mask] 0 bits in [addr], set these 0 bits with [value] corresponding bits*/
+#define modify_reg(addr, value, mask) wr_reg(addr, ((rd_reg(addr) & (mask)) | (value)))
+#define wait_set(addr, loc) do{}while(0 == (rd_reg(addr) & (1<<loc)));
+#define wait_clr(addr, loc) do{}while(1 == (rd_reg(addr) & (1<<loc)));
+#define wait_equal(addr, data) do{}while(data != (rd_reg(addr)));
+
+/* function defines */
+unsigned int ddr_init(void);
+unsigned int ddr_init_pll(void);
+unsigned int ddr_init_dmc(void);
+unsigned int ddr_init_pctl(void);
+unsigned int hot_boot(void);
+void ddr_print_info(void);
+void ddr_test(void);
+void ddr_pre_init(void);
+void ddr_debug(void);
+
+/* pctl status */
+#define UPCTL_STAT_MASK (7)
+#define UPCTL_STAT_INIT (0)
+#define UPCTL_STAT_CONFIG (1)
+#define UPCTL_STAT_ACCESS (3)
+#define UPCTL_STAT_LOW_POWER (5)
+
+/* pctl cmds */
+#define UPCTL_CMD_INIT (0)
+#define UPCTL_CMD_CONFIG (1)
+#define UPCTL_CMD_GO (2)
+#define UPCTL_CMD_SLEEP (3)
+#define UPCTL_CMD_WAKEUP (4)
+
+/* PUB PIR setting */
+#define PUB_PIR_INIT (1<<0)
+#define PUB_PIR_ZCAL (1<<1)
+#define PUB_PIR_CA (1<<2)
+#define PUB_PIR_PLLINIT (1<<4)
+#define PUB_PIR_DCAL (1<<5)
+#define PUB_PIR_PHYRST (1<<6)
+#define PUB_PIR_DRAMRST (1<<7)
+#define PUB_PIR_DRAMINIT (1<<8)
+#define PUB_PIR_WL (1<<9)
+#define PUB_PIR_QSGATE (1<<10)
+#define PUB_PIR_WLADJ (1<<11)
+#define PUB_PIR_RDDSKW (1<<12)
+#define PUB_PIR_WRDSKW (1<<13)
+#define PUB_PIR_RDEYE (1<<14)
+#define PUB_PIR_WREYE (1<<15)
+#define PUB_PIR_ICPC (1<<16)
+#define PUB_PIR_PLLBYP (1<<17)
+#define PUB_PIR_CTLDINIT (1<<18)
+#define PUB_PIR_RDIMMINIT (1<<19)
+#define PUB_PIR_CLRSR (1<<27)
+#define PUB_PIR_LOCKBYP (1<<28)
+#define PUB_PIR_DCALBYP (1<<29)
+#define PUB_PIR_ZCALBYP (1<<30)
+#define PUB_PIR_INITBYP (1<<31)
+
+/* PHY initialize register (PIR) */
+#define DDR_PIR ((PUB_PIR_ZCAL) |\
+ (PUB_PIR_PLLINIT) |\
+ (PUB_PIR_DCAL) |\
+ (PUB_PIR_PHYRST) |\
+ (PUB_PIR_DRAMRST) |\
+ (PUB_PIR_DRAMINIT) |\
+ (PUB_PIR_WL) |\
+ (PUB_PIR_QSGATE) |\
+ (PUB_PIR_WLADJ) |\
+ (PUB_PIR_RDDSKW) |\
+ (PUB_PIR_WRDSKW) |\
+ (PUB_PIR_RDEYE) |\
+ (PUB_PIR_WREYE) \
+ )
+
+/* PHY general status register (PGSR0) */
+#if (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_DDR3)
+#define DDR_PGSR0_CHECK() ((rd_reg(DDR0_PUB_PGSR0) != 0xC0000fff) && \
+ (rd_reg(DDR0_PUB_PGSR0) != 0x80000fff))
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR2)
+#define DDR_PGSR0_CHECK()
+#elif (CONFIG_DDR_TYPE == CONFIG_DDR_TYPE_LPDDR3)
+#define DDR_PGSR0_CHECK()
+#endif
+
+/* other regs */
+#define SCRATCH0 0xC1107D3C
diff --git a/arch/arm/include/asm/arch-t7/ddr_define.h b/arch/arm/include/asm/arch-t7/ddr_define.h
new file mode 100644
index 0000000..ec3f2a2
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/ddr_define.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#define CONFIG_BOARD_ID_MASK 0xFF
+#define CONFIG_DDR_TYPE_DDR3 0
+#define CONFIG_DDR_TYPE_DDR4 1
+#define CONFIG_DDR_TYPE_LPDDR4 2
+#define CONFIG_DDR_TYPE_LPDDR3 3
+#define CONFIG_DDR_TYPE_LPDDR2 4
+#define CONFIG_DDR_TYPE_AUTO 0xf
+
+/* ddr channel defines */
+#define CONFIG_DDR0_16BIT 1
+#define CONFIG_DDR0_RANK0 2
+#define CONFIG_DDR0_RANK01 3
+#define CONFIG_DDR0_16BIT_2 4
+/* CONFIG_DDR_CHL_AUTO mode support RANK0 and RANK0+1 mode auto detect */
+#define CONFIG_DDR_CHL_AUTO 0xF
+#define CONFIG_DDR0_16BIT_CH0 0x1
+#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7
+#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8
+
+//CONFIG_CH0_CS0_BYTE_01_SIZE_256 0 mean disable ,1 mean 256M 2 mean 512M 3 mean 768M,...0xf mean auto size det
+#define CONFIG_CH0_CS0_BYTE_01_SIZE_256_ID_OFFSET 0
+#define CONFIG_CH0_CS0_BYTE_23_SIZE_256_ID_OFFSET 4
+#define CONFIG_CH0_CS1_BYTE_01_SIZE_256_ID_OFFSET 8
+#define CONFIG_CH0_CS1_BYTE_23_SIZE_256_ID_OFFSET 12
+#define CONFIG_CH1_CS0_BYTE_01_SIZE_256_ID_OFFSET 16
+#define CONFIG_CH1_CS0_BYTE_23_SIZE_256_ID_OFFSET 20
+#define CONFIG_CH1_CS1_BYTE_01_SIZE_256_ID_OFFSET 24
+#define CONFIG_CH1_CS1_BYTE_23_SIZE_256_ID_OFFSET 28
+#define CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET 0
+#define CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET 4
+#define CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET 8
+#define CONFIG_CS1_BYTE_23_SIZE_256_ID_OFFSET 12
+
+#define DRAM_SIZE_ID_256MBX0 0
+#define DRAM_SIZE_ID_256MBX1 1
+#define DRAM_SIZE_ID_256MBX2 2
+#define DRAM_SIZE_ID_256MBX3 3
+#define DRAM_SIZE_ID_256MBX4 4
+#define DRAM_SIZE_ID_256MBX5 5
+#define DRAM_SIZE_ID_256MBX6 6
+#define DRAM_SIZE_ID_256MBX7 7
+#define DRAM_SIZE_ID_256MBX8 8
+#define DRAM_SIZE_ID_256MBX9 9
+#define DRAM_SIZE_ID_256MBX10 10
+#define DRAM_SIZE_ID_256MBX11 11
+#define DRAM_SIZE_ID_256MBX12 12
+#define DRAM_SIZE_ID_256MBX13 13
+#define DRAM_SIZE_ID_256MBX14 14
+#define DRAM_SIZE_ID_256MBXAUTO 15
+
+#define CFG_DDR_BASE_ADDR 0X0
+#define CFG_DDR_START_OFFSET 0X00000000 //TXLX SKIP 0MB
+
+/* ddr type identifier */
+#define CONFIG_DDR_TIMMING_LPDDR2 0x02
+#define CONFIG_DDR_TIMMING_LPDDR3 0x03
+#define CONFIG_DDR_TIMMING_DDR3_7 0x07
+#define CONFIG_DDR_TIMMING_DDR3_9 0x09
+#define CONFIG_DDR_TIMMING_DDR3_11 0x0B
+#define CONFIG_DDR_TIMMING_DDR3_12 0x0C
+#define CONFIG_DDR_TIMMING_DDR3_13 0x0D
+#define CONFIG_DDR_TIMMING_DDR3_14 0x0E
+
+#define CONFIG_DDR_TIMMING_DDR4_1600 0x0F
+#define CONFIG_DDR_TIMMING_DDR4_1866 0x10
+#define CONFIG_DDR_TIMMING_DDR4_2133 0x11
+#define CONFIG_DDR_TIMMING_DDR4_2400 0x12
+#define CONFIG_DDR_TIMMING_DDR4_2666 0x13
+#define CONFIG_DDR_TIMMING_DDR4_3200 0x14
+
+#define CONFIG_DDR_FUNC_TEST (1<<0)
+
+#define CONFIG_DDR_INIT_RETRY_TOTAL (10)
+#define CONFIG_DDR_PCTL_RETRY_TOTAL (100)
+
+#define DDR_USE_1_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK0) || \
+ (chl_set == CONFIG_DDR0_16BIT))
+#define DDR_USE_2_RANK(chl_set) ((chl_set == CONFIG_DDR0_RANK01))
+
+#define DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT 1<<5
+#define DMC_TEST_SLT_ENABLE_DDR_AUTO_WINDOW_TEST 1<<4
+/* DMC_DDR_CTRL defines */
+#define DDR_DDR4_ENABLE (1<<22)
+#define DDR_RANK1_ENABLE (1<<21)
+#define DDR_DDR4_BG_ENABLE (1<<20)
+#define DDR_16BIT_ENABLE (1<<16)
+
+#define DDR_RANK1_SIZE_CTRL (3)
+#define DDR_RANK0_SIZE_CTRL (0)
+
+/* ddr functions */
+/*
+#define DDR_FUNC_D2PLL (1<<0)
+#define DDR_FUNC_LP (1<<1)
+#define DDR_FUNC_ZQ_PD (1<<2)
+#define DDR_FUNC_EXT_VREF (1<<3)
+#define DDR_FUNC_DDR4_TIMING_TEST (1<<4)
+#define DDR_FUNC_DDR_PLL_BYPASS (1<<5)
+#define DDR_FUNC_RDBI (1<<6)
+#define DDR_FUNC_LPDDR3_CA (1<<7)
+#define DDR_FUNC_PRINT_WINDOW (1<<8)
+#define DDR_FUNC_FULL_TEST (1<<10)
+#define DDR_FUNC_NONSEC_SCRAMBLE (1<<11)
+#define DDR_FUNC_LPDDR3_CA_CA0_BIT0 (1<<20)
+#define DDR_FUNC_LPDDR3_CA_CA0_BIT1 (1<<21)
+#define DDR_FUNC_LPDDR3_CA_CA1_BIT0 (1<<22)
+#define DDR_FUNC_LPDDR3_CA_CA1_BIT1 (1<<23)
+#define DDR_FUNC_LPDDR3_CA_CA0_OFFSET (20)
+#define DDR_FUNC_LPDDR3_CA_CA1_OFFSET (22)
+#define DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP (1<<25)
+#define DDR_FUNC (DDR_FUNC_D2PLL | \
+ DDR_FUNC_LP | \
+ DDR_FUNC_ZQ_PD | \
+ DDR_FUNC_EXT_VREF | \
+ DDR_FUNC_DDR4_TIMING_TEST | \
+ DDR_FUNC_DDR_PLL_BYPASS | \
+ DDR_FUNC_RDBI | \
+ DDR_FUNC_LPDDR3_CA | \
+ DDR_FUNC_PRINT_WINDOW | \
+ DDR_FULL_TEST | \
+ DDR_NONSEC_SCRAMBLE | \
+ DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT0| \
+ DDR_FUNC_LPDDR3_CA_TRAINING_CA0_BIT1| \
+ DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT0| \
+ DDR_FUNC_LPDDR3_CA_TRAINING_CA1_BIT1| \
+ DDR_FUNC_LPDDR3_SOC_ODT_ONLY_UP | \
+ (1 << 31) \
+ )
+*/
+#define DDR_FUNC_COPY_CHANNEL_CFG (1<<0)
+
+#define DDR_FUNC_CONFIG_AXI_NOC_MODE_6 (1<<24)
+#define DDR_FUNC_FORCE_DDR_WINDOW_TEST_ON_POWER_OFF_STAGE (1<<25)
+#define DDR_FUNC_CONFIG_DISABLE_FORCE_TRAINING_DQ_INIT_DELAY_VALUE_FUNCTION (1<<26)
+#define DDR_FUNC_CONFIG_DISABLE_FORCE_TRAINING_1D_DEV_INIT_FUNCTION (1<<27)
+#define DDR_FUNC_CONFIG_DDR_DVFS_FUNCTION (1<<28)
+#define DDR_FUNC_CONFIG_DFE_FUNCTION (1<<29)
+#define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1<<30)
+#define DDR_FUNC_SCRAMBLE (1<<31)
+#define DDR_FUNC (0)
+/* dram cfg magic */
+#define DRAM_CFG_MAGIC 0x2e676663
+
+#define DMC_TEST_SLT_SCAN_FREQUENCY 1
+#define DMC_TEST_SLT_OFFSET_DELAY (1<<1)
+#define DMC_TEST_SLT_ENABLE_DDR_SKIP_TRAINING (1<<6)
+#define DMC_TEST_SLT_ENABLE_DDR_DVFS (1<<7)
+
+/* ddr configs */
+#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+
+#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+#define DDR_RFC_TYPE_LPDDR4_6Gbx1 12
+#define DDR_RFC_TYPE_LPDDR4_8Gbx1 13
+
+#define DDR_ENABLE_FINE_TUNE_FLAG_AC_DELAY (1<<0)
+#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQS (1<<1)
+#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQS (1<<2)
+#define DDR_ENABLE_FINE_TUNE_FLAG_WRITE_DQ (1<<3)
+#define DDR_ENABLE_FINE_TUNE_FLAG_READ_DQ (1<<4)
+
+
+/* bl2 reg override stages define */
+#define BL2_INIT_STAGE_0 0
+#define BL2_INIT_STAGE_1 1
+#define BL2_INIT_STAGE_2 2
+#define BL2_INIT_STAGE_3 3
+#define BL2_INIT_STAGE_4 4
+#define BL2_INIT_STAGE_5 5
+#define BL2_INIT_STAGE_6 6
+#define BL2_INIT_STAGE_7 7
+#define BL2_INIT_STAGE_8 8
+#define BL2_INIT_STAGE_9 9
+
+
+/* ddr reg override stages define */
+#define DDR_OVERRIDE_STAGE_DDR3_PRE_INIT 0x10
+#define DDR_OVERRIDE_STAGE_DDR3_DMC_INIT 0x11
+
+#define DDR_OVERRIDE_STAGE_DDR4_PRE_INIT 0x20
+#define DDR_OVERRIDE_STAGE_DDR4_DMC_INIT 0x21
+
+#define DDR_OVERRIDE_STAGE_LPDDR3_PRE_INIT 0x30
+#define DDR_OVERRIDE_STAGE_LPDDR3_DMC_INIT 0x31
+
+#define DDR_OVERRIDE_STAGE_LPDDR4_PRE_INIT 0x40
+#define DDR_OVERRIDE_STAGE_LPDDR4_DMC_INIT 0x41
+
+
+#define DWC_AC_PINMUX_TOTAL 28
+#define DWC_DFI_PINMUX_TOTAL 26
+#define DWC_DQ_PINMUX_TOTAL 32
+
+/* diagnose function defines */
+#define CONFIG_DIAGNOSE_DISABLE 0x0
+#define CONFIG_DIAGNOSE_1D 0x1
+#define CONFIG_DIAGNOSE_2D 0x2
+#define CONFIG_DIAGNOSE_1D_2D 0x3
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-t7/dev_parameter.h b/arch/arm/include/asm/arch-t7/dev_parameter.h
new file mode 100644
index 0000000..f78928e
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/dev_parameter.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __DEV_PARAMETER_H__
+#define __DEV_PARAMETER_H__
+
+/* gpio/pinmux/pwm */
+typedef struct _register_ops {
+ /* register address*/
+ uint32_t reg;
+ /* value to set*/
+ uint32_t value;
+ /* bitmask of the value setting */
+ uint32_t mask;
+ /* for HW stable consideration */
+ uint16_t udelay;
+ /* setting stage and etc. */
+ uint8_t flag;
+ /* reserved. */
+ uint8_t rsv_0;
+}__attribute__ ((packed)) register_ops_t;
+
+#define MAX_REG_OPS_ENTRIES (32)
+typedef struct pin_pwm_parameter {
+ register_ops_t pin_pwm[MAX_REG_OPS_ENTRIES];
+}__attribute__ ((packed)) pin_pwm_parameter_t;
+
+typedef struct common_storage_parameter {
+ /* version info of the common storage parameter */
+ uint32_t version;
+ /* fip sector counts */
+ uint32_t device_fip_container_size;
+ /* fip copies */
+ uint32_t device_fip_container_copies;
+ /*ddrfip size*/
+ uint32_t ddr_fip_container_size;
+ uint8_t reserved[16];
+}__attribute__ ((packed)) common_storage_parameter_t;
+
+
+typedef struct nand_parameter {
+ /* version info of the common storage parameter */
+ uint32_t version;
+ /* the same as bbt_start_block, tell the bbt size for scanning mechanism */
+ uint32_t bbt_pages;
+ /* for bl2 stage, it can quickly generate the small part of the fromt bbt table. 20 for start block of bbt scanning */
+ uint32_t bbt_start_block;
+ /* 1: bl2 and fip is stored separately in different area 0: bl2 and fip is stored in first 1024 pages. 1 for slc nand flash. */
+ uint32_t discrete_mode;
+ /* set the setup_data the same as rom code reading from page0. see union cmdinfo in nand.h. */
+ union {
+ uint32_t nand_setup_data;
+ uint32_t spi_nand_page_size;
+ } setup_data;
+ union {
+ uint32_t nand_reserved;
+ uint32_t spi_nand_planes_per_lun;
+ } reserved;
+ /* Block counts of the reserved area */
+ uint32_t reserved_area_blk_cnt;
+ /* Page number of each block */
+ uint32_t page_per_block;
+ /* Page list source of the bl2 NAND driver. 0: calculated in source code; 1: get from byte32~63 */
+ uint8_t use_param_page_list;
+ /* List of page addresses, 8-bit per entry */
+ uint8_t page_list[32];
+ uint8_t reserved1[63];
+}__attribute__ ((packed)) nand_parameter_t;
+
+
+typedef struct storage_parameter {
+ /* for all the storage media */
+ common_storage_parameter_t common;
+ /* for NAND and SPINAND */
+ nand_parameter_t nand;
+}__attribute__ ((packed)) storage_parameter_t;
+
+#endif //__AML_TIMING_H_
diff --git a/arch/arm/include/asm/arch-t7/efuse.h b/arch/arm/include/asm/arch-t7/efuse.h
new file mode 100644
index 0000000..4a68e88
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/efuse.h
@@ -0,0 +1,46 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __EFUSE_H
+#define __EFUSE_H
+
+#include <config.h>
+#include <common.h>
+
+/* efuse HAL_API arg */
+struct efuse_hal_api_arg {
+ unsigned int cmd; /* R/W */
+ unsigned int offset;
+ unsigned int size;
+ unsigned long buffer_phy;
+ unsigned long retcnt_phy;
+};
+
+
+#define EFUSE_BYTES 512 /* (EFUSE_BITS/8) */
+
+#define EFUSE_HAL_API_READ 0
+#define EFUSE_HAL_API_WRITE 1
+#define EFUSE_HAL_API_WRITE_PATTERN 2
+#define EFUSE_HAL_API_USER_MAX 3
+
+#define EFUSE_USER_MASK (0x1 << 16)
+#define EFUSE_THERMAL_MASK (0x1 << 17)
+#define EFUSE_THERMAL_VERFLAG_MASK (0x1 << 18)
+#define EFUSE_ENCRYPT_MASK (0x1 << 19)
+
+//#define ASSIST_HW_REV 0x1f53
+
+int efuse_read_usr(char *buf, size_t count, loff_t *ppos);
+int efuse_write_usr(char *buf, size_t count, loff_t *ppos);
+uint32_t efuse_get_max(void);
+ssize_t efuse_read(char *buf, size_t count, loff_t *ppos);
+ssize_t efuse_write(const char *buf, size_t count, loff_t *ppos);
+
+int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg);
+int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg);
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-t7/eth_setup.h b/arch/arm/include/asm/arch-t7/eth_setup.h
new file mode 100644
index 0000000..6e643f6
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/eth_setup.h
@@ -0,0 +1,98 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/io.h>
+
+/*
+ *board configuration interface.
+ * */
+struct eth_clock_conf{
+ int enable;
+ int clock_50MHZ_phase;
+ //add ... as you need.
+};
+
+struct eth_board_socket{
+char *name ;
+int (*eth_clock_configure)(struct eth_clock_conf);
+int (*eth_pinmux_setup)(void);
+int (*eth_hw_reset)(void);
+
+};
+
+
+
+/*
+ *clock define part
+ */
+
+#define ETH_BASE (0xff3f0000)
+#define ETH_PLL_CNTL CBUS_REG_ADDR(0x2050)
+ /* Ethernet ctrl */
+#define ETH_PLL_CNTL_DIVEN (1<<0)
+#define ETH_PLL_CNTL_MACSPD (1<<1)
+#define ETH_PLL_CNTL_DATEND (1<<2)
+#define ETH_PLL_CNTL_DESEND (1<<3)
+
+
+/*
+ please refer following doc for detail
+ @AppNote-M3-ClockTrees.docx
+
+ select clk: -> CBUS_REG(0x1076)
+
+ 7-sys_pll_div2
+ 6-vid2_pll_clk
+ 5-vid_pll_clk
+ 4-aud_pll_clk
+ 3-ddr_pll_clk
+ 2-misc_pll_clk
+ 1-sys_pll_clk
+ 0-XTAL
+
+ clk_freq:800MHz
+ output_clk:50MHz
+ aways,maybe changed for others?
+*/
+
+#define ETH_CLKSRC_XTAL (0)
+#define ETH_CLKSRC_SYS_PLL_CLK (1)
+#define ETH_CLKSRC_MISC_PLL_CLK (2)
+#define ETH_CLKSRC_DDR_PLL_CLK (3)
+#define ETH_CLKSRC_AUD_PLL_CLK (
+#define ETH_CLKSRC_VID_PLL_CLK (5)
+#define ETH_CLKSRC_VID2_PLL_CLK (6)
+#define ETH_CLKSRC_SYS_PLL_DIV2_CLK (7)
+#define CLK_1M (1000000)
+
+typedef union eth_aml_reg0 {
+ /** raw register data */
+ unsigned int d32;
+ /** register bits */
+ struct {
+ unsigned phy_intf_sel:3;
+ unsigned rx_clk_rmii_invert:1;
+ unsigned rgmii_tx_clk_src:1;
+ unsigned rgmii_tx_clk_phase:2;
+ unsigned rgmii_tx_clk_ratio:3;
+ unsigned phy_ref_clk_enable:1;
+ unsigned clk_rmii_i_invert:1;
+ unsigned clk_en:1;
+ unsigned adj_enable:1;
+ unsigned adj_setup:1;
+ unsigned adj_delay:5;
+ unsigned adj_skew:5;
+ unsigned cali_start:1;
+ unsigned cali_rise:1;
+ unsigned cali_sel:3;
+ unsigned rgmii_rx_reuse:1;
+ unsigned eth_urgent:1;
+ } b;
+} eth_aml_reg0_t;
+
+#define ETH_VALIDE_CLKSRC(clk,out_clk) ((clk%out_clk)==0)
+
+int eth_clk_set(int selectclk,unsigned long clk_freq,unsigned long out_clk);
+
diff --git a/arch/arm/include/asm/arch-t7/gpio.h b/arch/arm/include/asm/arch-t7/gpio.h
new file mode 100644
index 0000000..2467368
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/gpio.h
@@ -0,0 +1,10 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __ASM_ARCH_MESON_GPIO_H
+#define __ASM_ARCH_MESON_GPIO_H
+
+
+#endif /* __ASM_ARCH_MESON_GPIO_H */
diff --git a/arch/arm/include/asm/arch-t7/io.h b/arch/arm/include/asm/arch-t7/io.h
new file mode 100644
index 0000000..fd3981a
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/io.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __MACH_MESSON_REGS_IO_H
+#define __MACH_MESSON_REGS_IO_H
+
+#ifndef __ASSEMBLY__
+
+#include <asm/io.h>
+#define IO_CBUS_BASE (0xFFD00000L)
+#define IO_AXI_BUS_BASE (0xFFB00000L) /* gpv */
+#define IO_AHB_BUS_BASE (0xFF500000L) /* usb0 */
+#define IO_APB_BUS_BASE (0xFFFC0000L) /* AHB SRAM, sec/sys ahb? txlx_mem_map.xlsx */
+#define IO_APB_HDMI_BUS_BASE (0xFFE00000L) /* */
+#define IO_VPU_BUS_BASE (0xFF900000L) /* VPU */
+
+#define CBUS_REG_OFFSET(reg) ((reg) << 2)
+#define CBUS_REG_ADDR(reg) (IO_CBUS_BASE + CBUS_REG_OFFSET(reg))
+
+#define AXI_REG_OFFSET(reg) ((reg) << 2)
+#define AXI_REG_ADDR(reg) (IO_AXI_BUS_BASE + AXI_REG_OFFSET(reg))
+
+#define AHB_REG_OFFSET(reg) ((reg) << 2)
+#define AHB_REG_ADDR(reg) (IO_AHB_BUS_BASE + AHB_REG_OFFSET(reg))
+
+#define VPU_REG_OFFSET(reg) ((reg) << 2)
+#define VPU_REG_ADDR(reg) (IO_VPU_BUS_BASE + VPU_REG_OFFSET(reg))
+
+
+#define APB_REG_OFFSET(reg) (reg)
+#define APB_REG_ADDR(reg) (IO_APB_BUS_BASE + APB_REG_OFFSET(reg))
+#define APB_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0)
+
+#define APB_HDMI_REG_OFFSET(reg) (reg)
+#define APB_HDMI_REG_ADDR(reg) (IO_APB_HDMI_BUS_BASE + APB_HDMI_REG_OFFSET(reg))
+#define APB_HDMI_REG_ADDR_VALID(reg) (((unsigned long)(reg) & 3) == 0)
+
+
+#define WRITE_CBUS_REG(reg, val) __raw_writel(val, CBUS_REG_ADDR(reg))
+#define READ_CBUS_REG(reg) (__raw_readl(CBUS_REG_ADDR(reg)))
+#define WRITE_CBUS_REG_BITS(reg, val, start, len) \
+ WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_CBUS_REG_BITS(reg, start, len) \
+ ((READ_CBUS_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)&(~(mask))))
+#define SET_CBUS_REG_MASK(reg, mask) WRITE_CBUS_REG(reg, (READ_CBUS_REG(reg)|(mask)))
+
+#define WRITE_AXI_REG(reg, val) __raw_writel(val, AXI_REG_ADDR(reg))
+#define READ_AXI_REG(reg) (__raw_readl(AXI_REG_ADDR(reg)))
+#define WRITE_AXI_REG_BITS(reg, val, start, len) \
+ WRITE_AXI_REG(reg, (READ_AXI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_AXI_REG_BITS(reg, start, len) \
+ ((READ_AXI_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)&(~(mask))))
+#define SET_AXI_REG_MASK(reg, mask) WRITE_AXI_REG(reg, (READ_AXI_REG(reg)|(mask)))
+
+#define WRITE_AHB_REG(reg, val) __raw_writel(val, AHB_REG_ADDR(reg))
+#define READ_AHB_REG(reg) (__raw_readl(AHB_REG_ADDR(reg)))
+#define WRITE_AHB_REG_BITS(reg, val, start, len) \
+ WRITE_AHB_REG(reg, (READ_AHB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_AHB_REG_BITS(reg, start, len) \
+ ((READ_AHB_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)&(~(mask))))
+#define SET_AHB_REG_MASK(reg, mask) WRITE_AHB_REG(reg, (READ_AHB_REG(reg)|(mask)))
+
+#define WRITE_APB_REG(reg, val) __raw_writel(val, APB_REG_ADDR(reg))
+#define READ_APB_REG(reg) (__raw_readl(APB_REG_ADDR(reg)))
+#define WRITE_APB_REG_BITS(reg, val, start, len) \
+ WRITE_APB_REG(reg, (READ_APB_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_APB_REG_BITS(reg, start, len) \
+ ((READ_APB_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)&(~(mask))))
+#define SET_APB_REG_MASK(reg, mask) WRITE_APB_REG(reg, (READ_APB_REG(reg)|(mask)))
+
+#define WRITE_APB_HDMI_REG(reg, val) __raw_writel(val, APB_HDMI_REG_ADDR(reg))
+#define READ_APB_HDMI_REG(reg) (__raw_readl(APB_HDMI_REG_ADDR(reg)))
+#define WRITE_APB_HDMI_REG_BITS(reg, val, start, len) \
+ WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg) & ~(((1L<<(len))-1)<<(start)) )| ((unsigned)((val)&((1L<<(len))-1)) << (start)))
+#define READ_APB_HDMI_REG_BITS(reg, start, len) \
+ ((READ_APB_HDMI_REG(reg) >> (start)) & ((1L<<(len))-1))
+#define CLEAR_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)&(~(mask))))
+#define SET_APB_HDMI_REG_MASK(reg, mask) WRITE_APB_HDMI_REG(reg, (READ_APB_HDMI_REG(reg)|(mask)))
+
+/* for back compatible alias */
+#define WRITE_MPEG_REG(reg, val) \
+ WRITE_CBUS_REG(reg, val)
+#define READ_MPEG_REG(reg) \
+ READ_CBUS_REG(reg)
+#define WRITE_MPEG_REG_BITS(reg, val, start, len) \
+ WRITE_CBUS_REG_BITS(reg, val, start, len)
+#define READ_MPEG_REG_BITS(reg, start, len) \
+ READ_CBUS_REG_BITS(reg, start, len)
+#define CLEAR_MPEG_REG_MASK(reg, mask) \
+ CLEAR_CBUS_REG_MASK(reg, mask)
+#define SET_MPEG_REG_MASK(reg, mask) \
+ SET_CBUS_REG_MASK(reg, mask)
+#endif
+
+
+#endif
diff --git a/arch/arm/include/asm/arch-t7/mailbox.h b/arch/arm/include/asm/arch-t7/mailbox.h
new file mode 100644
index 0000000..64a125d
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/mailbox.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+ /*
+ *
+ * Copyright (C) 2012 Amlogic, Inc.
+ *
+ * Author: Platform-SH@amlogic.com
+ *
+ */
+
+#ifndef __MAILBOX_H__
+#define __MAILBOX_H__
+#include <asm/arch/secure_apb.h>
+
+#define REE2AO_SET_ADDR MAILBOX_SET_MBOX03
+#define REE2AO_STS_ADDR MAILBOX_STS_MBOX03
+#define REE2AO_CLR_ADDR MAILBOX_CLR_MBOX03
+#define REE2AO_WR_ADDR MAILBOX_BUF_MBOX03
+#define REE2AO_RD_ADDR MAILBOX_BUF_MBOX03
+#define REE2AO_IRQCLR_ADDR MAILBOX_IRQA_CLR0
+#define REE2AO_IRQCLR_ADDR1 MAILBOX_IRQA_CLR1
+
+#define MAILBOX_USER_DATA_SIZE 96
+
+#define MHU_SYNC (1 << 26)
+#define MHU_CMD_BUILD(command, size) \
+ (((command) & 0xffff) | (((size) & 0x1ff) << 16) | MHU_SYNC)
+#define MHU_ACK_MASK(mbox) (1 << ((mbox)*2 + 1))
+
+#define MHU_PAYLOAD_SIZE 0x80
+#define MHU_DATA_OFFSET 0x1c
+#define REE2AO_MBOX_ID 0x3
+/* ...Message composition with module(6bits), function(10bits) */
+#define __MBX_COMPOSE_MSG(mod, func) (((mod) << 10) | ((func) & 0x3FF))
+
+/*******************************************************************************
+ * Define moudle type here, 6bits valid
+ ******************************************************************************/
+#define MBX_SYSTEM 0x0
+
+/*******************************************************************************
+ * Define function here, 10bits valid
+ ******************************************************************************/
+ /*SYSTEM*/
+#define CMD_UNDEFINE 0x0
+#define CMD_TEST 0x6
+#define CMD_LED_INFO 0xF7
+
+/*******************************************************************************
+ * Mssage Comopsition
+ ******************************************************************************/
+#define MBX_CMD_TEST __MBX_COMPOSE_MSG(MBX_SYSTEM, CMD_TEST)
+enum {
+ HIFIA_REE_CHANNEL = 0,
+ HIFIB_REE_CHANNEL = 1,
+ SECPU_REE_CHANNEL = 2,
+ AOCPU_REE_CHANNEL = 3,
+};
+
+void mhu_init(void);
+/*message max size MAILBOX_USER_DATA_SIZE 96 byte*/
+int scpi_send_data(uint32_t chan, uint32_t command,
+ void *sendmessage, uint32_t sendsize,
+ void *revmessage, uint32_t revsize);
+#endif /* __SCPI_FIFO_H__ */
diff --git a/arch/arm/include/asm/arch-t7/mnPmuSramMsgBlock_ddr3.h b/arch/arm/include/asm/arch-t7/mnPmuSramMsgBlock_ddr3.h
new file mode 100644
index 0000000..c067367
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/mnPmuSramMsgBlock_ddr3.h
@@ -0,0 +1,637 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief DDR3U_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_DDR3U_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Train vrefDAC0 During Read Deskew
+ // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] = MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] = SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] = SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] = RFU, must be zero (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero)
+ //
+ //
+ //
+ // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] = PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte
+ // 0x0 = All rank populated with all the byte (tyical configuration)
+ //
+ // MsgMisc[7] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware.
+ // Please reference this revision ID when filing support cases with Synopsys.
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Module Type:
+ // 0x01 = DDR3 unbuffered
+ // 0x02 = Reserved
+ // 0x03 = Reserved
+ // 0x04 = Reserved
+ // 0x05 = Reserved
+ //
+ uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7):
+ // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting)
+ uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ // Total number of DQ bits enabled in PHY
+ uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS.
+ //
+ // If the bit is set to 1, the CS is connected to DRAM.
+ // If the bit is set to 0, the CS is not connected to DRAM.
+ //
+ // CsPresent[0] = CS0 is populated with DRAM
+ // CsPresent[1] = CS1 is populated with DRAM
+ // CsPresent[2] = CS2 is populated with DRAM
+ // CsPresent[3] = CS3 is populated with DRAM
+ // CsPresent[7:4] = Reserved (must be programmed to 0)
+ //
+ //
+ uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 0
+ uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 1
+ uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ // Corresponds to CS[3:0]
+ // 1 = Address Mirror.
+ // 0 = No Address Mirror.
+ uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ // Additional mode bits.
+ //
+ // Bit fields:
+ // [0] SlowAccessMode :
+ // 1 = 2T Address Timing.
+ // 0 = 1T Address Timing.
+ // [7-1] RFU, must be zero
+ uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[10] = RFU, must be zero
+ // SequenceCtrl[11] = RFU, must be zero
+ // SequenceCtrl[12] = RFU, must be zero
+ // SequenceCtrl[13] = RFU, must be zero
+ // SequenceCtrl[15-14] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A
+
+
+
+ uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D training in: Rd2D, Wr2D
+ //
+ // Reserved1E[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1E[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR6
+ // 2 = limit to +/-4 %VDDQ from MR6
+ // …
+ // 15 = limit to +/-30% VDDQ from MR6
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A
+ // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset.
+ uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ // Value of DDR mode register MR0 for all ranks for current pstate
+ uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Value of DDR mode register MR1 for all ranks for current pstate
+ uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ // Value of DDR mode register MR2 for all ranks for current pstate
+ uint8_t Reserved64; // Byte offset 0x64, CSR Addr 0x54032, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved65; // Byte offset 0x65, CSR Addr 0x54032, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6E; // Byte offset 0x6e, CSR Addr 0x54037, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6F; // Byte offset 0x6f, CSR Addr 0x54037, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved71; // Byte offset 0x71, CSR Addr 0x54038, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved72; // Byte offset 0x72, CSR Addr 0x54039, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved73; // Byte offset 0x73, CSR Addr 0x54039, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl0; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl2; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl3; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl4; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl5; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t AcsmOdtCtrl7; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7C; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7D; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A
+
+ uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A
+
+ uint8_t Reserved8A; // Byte offset 0x8a, CSR Addr 0x54045, Direction=N/A
+
+ uint8_t Reserved8B; // Byte offset 0x8b, CSR Addr 0x54045, Direction=N/A
+
+ uint8_t Reserved8C; // Byte offset 0x8c, CSR Addr 0x54046, Direction=N/A
+
+ uint8_t Reserved8D; // Byte offset 0x8d, CSR Addr 0x54046, Direction=N/A
+
+ uint8_t Reserved8E; // Byte offset 0x8e, CSR Addr 0x54047, Direction=N/A
+
+ uint8_t Reserved8F; // Byte offset 0x8f, CSR Addr 0x54047, Direction=N/A
+
+ uint8_t Reserved90; // Byte offset 0x90, CSR Addr 0x54048, Direction=N/A
+
+ uint8_t Reserved91; // Byte offset 0x91, CSR Addr 0x54048, Direction=N/A
+
+ uint8_t Reserved92; // Byte offset 0x92, CSR Addr 0x54049, Direction=N/A
+
+ uint8_t Reserved93; // Byte offset 0x93, CSR Addr 0x54049, Direction=N/A
+
+ uint8_t Reserved94; // Byte offset 0x94, CSR Addr 0x5404a, Direction=N/A
+
+ uint8_t Reserved95; // Byte offset 0x95, CSR Addr 0x5404a, Direction=N/A
+
+ uint8_t Reserved96; // Byte offset 0x96, CSR Addr 0x5404b, Direction=N/A
+
+ uint8_t Reserved97; // Byte offset 0x97, CSR Addr 0x5404b, Direction=N/A
+
+ uint8_t Reserved98; // Byte offset 0x98, CSR Addr 0x5404c, Direction=N/A
+
+ uint8_t Reserved99; // Byte offset 0x99, CSR Addr 0x5404c, Direction=N/A
+
+ uint8_t Reserved9A; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=N/A
+
+ uint8_t Reserved9B; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=N/A
+
+ uint8_t Reserved9C; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=N/A
+
+ uint8_t Reserved9D; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=N/A
+
+ uint8_t Reserved9E; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=N/A
+
+ uint8_t Reserved9F; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=N/A
+
+ uint8_t ReservedA0; // Byte offset 0xa0, CSR Addr 0x54050, Direction=N/A
+
+ uint8_t ReservedA1; // Byte offset 0xa1, CSR Addr 0x54050, Direction=N/A
+
+ uint8_t ReservedA2; // Byte offset 0xa2, CSR Addr 0x54051, Direction=N/A
+
+ uint8_t ReservedA3; // Byte offset 0xa3, CSR Addr 0x54051, Direction=N/A
+
+} __attribute__ ((packed)) PMU_SMB_DDR3U_1D_t;
diff --git a/arch/arm/include/asm/arch-t7/mnPmuSramMsgBlock_ddr4.h b/arch/arm/include/asm/arch-t7/mnPmuSramMsgBlock_ddr4.h
new file mode 100644
index 0000000..6dfd4d0
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/mnPmuSramMsgBlock_ddr4.h
@@ -0,0 +1,2380 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief DDR4U_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_DDR4U_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Train vrefDAC0 During Read Deskew
+ // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] = MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] = SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] = SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D.
+ // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field
+ //
+ // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] = PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte
+ // 0x0 = All rank populated with all the byte (tyical configuration)
+ //
+ // MsgMisc[7] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware.
+ // Please reference this revision ID when filing support cases with Synopsys.
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Module Type:
+ // 0x01 = Reserved
+ // 0x02 = DDR4 unbuffered
+ // 0x03 = Reserved
+ // 0x04 = Reserved
+ // 0x05 = Reserved
+ //
+ uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7):
+ // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting)
+ uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ // Total number of DQ bits enabled in PHY
+ uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS.
+ //
+ // If the bit is set to 1, the CS is connected to DRAM.
+ // If the bit is set to 0, the CS is not connected to DRAM.
+ //
+ // CsPresent[0] = CS0 is populated with DRAM
+ // CsPresent[1] = CS1 is populated with DRAM
+ // CsPresent[2] = CS2 is populated with DRAM
+ // CsPresent[3] = CS3 is populated with DRAM
+ // CsPresent[7:4] = Reserved (must be programmed to 0)
+ //
+ //
+ uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 0
+ uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 1
+ uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ // Corresponds to CS[3:0]
+ // 1 = Address Mirror.
+ // 0 = No Address Mirror.
+ uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ // Additional mode bits.
+ //
+ // Bit fields:
+ // [0] SlowAccessMode :
+ // 1 = 2T Address Timing.
+ // 0 = 1T Address Timing.
+ // [7-1] RFU, must be zero
+ uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[10] = Run Reserved
+ // SequenceCtrl[11] = Run Reserved
+ // SequenceCtrl[12] = Run Reserved
+ // SequenceCtrl[13] = Run Reserved
+ // SequenceCtrl[15-14] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1B; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=N/A
+
+
+
+ uint8_t Reserved1C; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A
+
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D training in: Rd2D, Wr2D
+ //
+ // Reserved1E[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1E[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR6
+ // 2 = limit to +/-4 %VDDQ from MR6
+ // …
+ // 15 = limit to +/-30% VDDQ from MR6
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ int8_t CDD_RR_3_2; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_3_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_3; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_1; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_2_0; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_3; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_2; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_3; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_2; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RR_0_1; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_2; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_1; // Byte offset 0x32, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_3_0; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_3; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_1; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_2_0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_3; // Byte offset 0x37, CSR Addr 0x5401b, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_2; // Byte offset 0x38, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_1_0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_3; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_2; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WW_0_1; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_3; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_2; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_3_0; // Byte offset 0x40, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_3; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_2; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_1; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_2_0; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_3; // Byte offset 0x45, CSR Addr 0x54022, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_2; // Byte offset 0x46, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_1; // Byte offset 0x47, CSR Addr 0x54023, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_1_0; // Byte offset 0x48, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_3; // Byte offset 0x49, CSR Addr 0x54024, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_2; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_RW_0_0; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_3; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_2; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_1; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_3_0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 3 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_3; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_2; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_2_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 2 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_3; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_2; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_1; // Byte offset 0x57, CSR Addr 0x5402b, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_1_0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_3; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 3
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_2; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 2
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_WR_0_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=N/A
+ // This field is ignored if 0. If larger than 0, this value is used as is as the offset in fine-step applied at the end of DDR4 RxEnable training, instead of the default offset.
+ uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ // Value of DDR mode register MR0 for all ranks for current pstate
+ uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Value of DDR mode register MR1 for all ranks for current pstate
+ uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ // Value of DDR mode register MR2 for all ranks for current pstate
+ uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ // Value of DDR mode register MR3 for all ranks for current pstate
+ uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value of DDR mode register MR4 for all ranks for current pstate
+ uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value of DDR mode register MR5 for all ranks for current pstate
+ uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0.
+ uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // X16 device map. Corresponds to CS[3:0].
+ // X16Present[0] = CS0 is populated with X16 devices
+ // X16Present[1] = CS1 is populated with X16 devices
+ // X16Present[2] = CS2 is populated with X16 devices
+ // X16Present[3] = CS3 is populated with X16 devices
+ // X16Present[7:4] = Reserved (must be programmed to 0)
+ //
+ // Ranks may not contain mixed device types.
+ uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // controls timing of chip select signals when DDR4 gear-down mode is active
+ // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs
+ // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode
+ uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM:
+ // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0
+ // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0
+ // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0
+ uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM:
+ // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1
+ // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1
+ // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1
+ uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM:
+ // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2
+ // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2
+ // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2
+ uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM:
+ // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3
+ // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3
+ // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3
+ uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM:
+ // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4
+ // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4
+ // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4
+ uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM:
+ // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5
+ // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5
+ // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5
+ uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM:
+ // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6
+ // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6
+ // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6
+ uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM:
+ // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7
+ // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7
+ // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7
+ uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices.
+ uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices.
+ uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices.
+ uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices.
+ uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices.
+ uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices.
+ uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices.
+ uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices.
+ uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices.
+ uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices.
+ uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices.
+ uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices.
+ uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices.
+ uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices.
+ uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices.
+ uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices.
+ uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices.
+ uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices.
+ uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices.
+ uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices.
+ uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices.
+ uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices.
+ uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices.
+ uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices.
+ uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices.
+ uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices.
+ uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices.
+ uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices.
+ uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices.
+ uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices.
+ uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices.
+ uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices.
+ uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices.
+ uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices.
+ uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices.
+ uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices.
+ uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices.
+ uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices.
+ uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices.
+ uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices.
+ uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A
+
+ uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A
+
+ uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in
+ // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1).
+ // RdDBI is dynamically disabled in certain training steps,
+ // and so the [RdDBI disabled] CAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_CAS_L[0] == 0: use value in MR0
+ // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2]
+ // Other bits are ignored
+ uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In
+ // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1).
+ // 2tCK write prambles are dynamically disabled in certain training steps,
+ // and so the [1tCK write preamble] WCAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_WCAS_L[0] == 0: use value in MR2
+ // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3]
+ // Other bits are ignored
+ uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In
+ // Contains various options for training DDR4 Devices.
+ //
+ // Bit fields:
+ //
+ // D4Misc[7:1] RFU, must be zero
+ //
+ // D4Misc[0] = protect memory reset
+ // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training.
+ // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training
+} __attribute__ ((packed)) PMU_SMB_DDR4U_1D_t;
diff --git a/arch/arm/include/asm/arch-t7/mnPmuSramMsgBlock_ddr4_2d.h b/arch/arm/include/asm/arch-t7/mnPmuSramMsgBlock_ddr4_2d.h
new file mode 100644
index 0000000..35b1e23
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/mnPmuSramMsgBlock_ddr4_2d.h
@@ -0,0 +1,2282 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief DDR4U_2D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_DDR4U_2D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Train vrefDAC0 During Read Deskew
+ // 0x1 = Read Deskew will begin by enabling and roughly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting will work for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] = MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] = SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] = SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] = UseDdr4PerDeviceVrefDq (DDR4 UDIMM and RDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Program user characterized Vref DQ values per DDR4 DRAM device. The message block VrefDqR*Nib* fields must be populated with the desired per device Vref DQs when using this option. Note: this option is not applicable in 2D training because these values are explicitly trained in 2D.
+ // 0x0 = Program Vref DQ for all DDR4 devices with the single value provided in MR6 message block field
+ //
+ // MsgMisc[4] = Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] = PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[6] = PartialRank (DDR3 UDIMM and DDR4 UDIMM only, otherwise RFU, must be zero)
+ // 0x1 = Support rank populated with a subset of byte, but where even-odd pair of rank support all the byte
+ // 0x0 = All rank populated with all the byte (tyical configuration)
+ //
+ // MsgMisc[7] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware.
+ // Please reference this revision ID when filing support cases with Synopsys.
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t DramType; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Module Type:
+ // 0x01 = Reserved
+ // 0x02 = DDR4 unbuffered
+ // 0x03 = Reserved
+ // 0x04 = Reserved
+ // 0x05 = Reserved
+ //
+ uint8_t DisabledDbyte; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bitmap to indicate which Dbyte are not connected (for DByte 0 to 7):
+ // Set DisabledDbyte[i] to 1 only to specify that DByte i not need to be trained (DByte 8 can be disabled via EnabledDQs setting)
+ uint8_t EnabledDQs; // Byte offset 0x0f, CSR Addr 0x54007, Direction=In
+ // Total number of DQ bits enabled in PHY
+ uint8_t CsPresent; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY. Each bit corresponds to a logical CS.
+ //
+ // If the bit is set to 1, the CS is connected to DRAM.
+ // If the bit is set to 0, the CS is not connected to DRAM.
+ //
+ // CsPresent[0] = CS0 is populated with DRAM
+ // CsPresent[1] = CS1 is populated with DRAM
+ // CsPresent[2] = CS2 is populated with DRAM
+ // CsPresent[3] = CS3 is populated with DRAM
+ // CsPresent[7:4] = Reserved (must be programmed to 0)
+ //
+ //
+ uint8_t CsPresentD0; // Byte offset 0x11, CSR Addr 0x54008, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 0
+ uint8_t CsPresentD1; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // The CS signals from field CsPresent that are routed to DIMM connector 1
+ uint8_t AddrMirror; // Byte offset 0x13, CSR Addr 0x54009, Direction=In
+ // Corresponds to CS[3:0]
+ // 1 = Address Mirror.
+ // 0 = No Address Mirror.
+ uint8_t CsTestFail; // Byte offset 0x14, CSR Addr 0x5400a, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint8_t PhyCfg; // Byte offset 0x15, CSR Addr 0x5400a, Direction=In
+ // Additional mode bits.
+ //
+ // Bit fields:
+ // [0] SlowAccessMode :
+ // 1 = 2T Address Timing.
+ // 0 = 1T Address Timing.
+ // [7-1] RFU, must be zero
+ uint16_t SequenceCtrl; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = RFU, must be zero
+ // SequenceCtrl[2] = RFU, must be zero
+ // SequenceCtrl[3] = RFU, must be zero
+ // SequenceCtrl[4] = RFU, must be zero
+ // SequenceCtrl[5] = Run rd2D - 2d read dqs training
+ // SequenceCtrl[6] = Run wr2D - 2d write dq training
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = RFU, must be zero
+ // SequenceCtrl[9] = RFU, must be zero
+ // SequenceCtrl[10] = RFU, must be zero
+ // SequenceCtrl[11] = RFU, must be zero
+ // SequenceCtrl[12] = RFU, must be zero
+ // SequenceCtrl[13] = RFU, must be zero
+ // SequenceCtrl[15-14] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t RX2D_TrainOpt; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In
+ // Bit fields, if 2D read training enabled, then use these additional options:
+ // [0] DFE
+ // 1 = Run rx2D with DFE
+ // 0 = Run rx2D with DFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5-7] RFU, must be zero
+ //
+ uint8_t TX2D_TrainOpt; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Bit fields, if 2D write training is enabled, then use these additional options:
+ // [0] FFE
+ // 1 = Train tx2D with FFE
+ // 0 = Train tx2D with FFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5] FFE Decision Algorithm Control
+ // 1 = FFE chooses the drive strength that maximizes the average eye-area across the entire phy.
+ // 0 = FFE chooses the drive strength that maximizes the smallest eye across the entire phy.
+ // [6-7] RFU, must be zero
+ //
+ uint8_t Share2DVrefResult; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // Bitmap that designates the phy's vref source for every pstate
+ // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock.
+ // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training.
+ uint8_t Delay_Weight2D; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye.
+ uint8_t Voltage_Weight2D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye.
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D training in: Rd2D, Wr2D
+ //
+ // Reserved1E[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1E[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR6
+ // 2 = limit to +/-4 %VDDQ from MR6
+ // …
+ // 15 = limit to +/-30% VDDQ from MR6
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t DFIMRLMargin; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ uint8_t R0_RxClkDly_Margin; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R0_VrefDac_Margin; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R0_TxDqDly_Margin; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R0_DeviceVref_Margin; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved29; // Byte offset 0x29, CSR Addr 0x54014, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2A; // Byte offset 0x2a, CSR Addr 0x54015, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2B; // Byte offset 0x2b, CSR Addr 0x54015, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2C; // Byte offset 0x2c, CSR Addr 0x54016, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2D; // Byte offset 0x2d, CSR Addr 0x54016, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2E; // Byte offset 0x2e, CSR Addr 0x54017, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved2F; // Byte offset 0x2f, CSR Addr 0x54017, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved31; // Byte offset 0x31, CSR Addr 0x54018, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved32; // Byte offset 0x32, CSR Addr 0x54019, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t R1_RxClkDly_Margin; // Byte offset 0x33, CSR Addr 0x54019, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R1_VrefDac_Margin; // Byte offset 0x34, CSR Addr 0x5401a, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R1_TxDqDly_Margin; // Byte offset 0x35, CSR Addr 0x5401a, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R1_DeviceVref_Margin; // Byte offset 0x36, CSR Addr 0x5401b, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved37; // Byte offset 0x37, CSR Addr 0x5401b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved39; // Byte offset 0x39, CSR Addr 0x5401c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3A; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3B; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3D; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3E; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved3F; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t R2_RxClkDly_Margin; // Byte offset 0x41, CSR Addr 0x54020, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R2_VrefDac_Margin; // Byte offset 0x42, CSR Addr 0x54021, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R2_TxDqDly_Margin; // Byte offset 0x43, CSR Addr 0x54021, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R2_DeviceVref_Margin; // Byte offset 0x44, CSR Addr 0x54022, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved48; // Byte offset 0x48, CSR Addr 0x54024, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved49; // Byte offset 0x49, CSR Addr 0x54024, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4A; // Byte offset 0x4a, CSR Addr 0x54025, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t R3_RxClkDly_Margin; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R3_VrefDac_Margin; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R3_TxDqDly_Margin; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t R3_DeviceVref_Margin; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved57; // Byte offset 0x57, CSR Addr 0x5402b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved58; // Byte offset 0x58, CSR Addr 0x5402c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved59; // Byte offset 0x59, CSR Addr 0x5402c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5B; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5C; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved5D; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In
+ // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D.
+ //
+ // Reserved5D[0-3]: bitTimeControl
+ // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point.
+ // 0 = 1 kilobit per point (legacy behavior)
+ // 1 = 2 kilobits per point
+ // 2 = 4 kilobits per point
+ // …
+ // 15 = 32 megabits per point
+ //
+ // Reserved5D[4]: Exhaustive2D
+ // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior)
+ // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point.
+ //
+ // Reserved5D[5:7]: RFU, must be 0
+ uint16_t MR0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=In
+ // Value of DDR mode register MR0 for all ranks for current pstate
+ uint16_t MR1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Value of DDR mode register MR1 for all ranks for current pstate
+ uint16_t MR2; // Byte offset 0x62, CSR Addr 0x54031, Direction=In
+ // Value of DDR mode register MR2 for all ranks for current pstate
+ uint16_t MR3; // Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ // Value of DDR mode register MR3 for all ranks for current pstate
+ uint16_t MR4; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value of DDR mode register MR4 for all ranks for current pstate
+ uint16_t MR5; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value of DDR mode register MR5 for all ranks for current pstate
+ uint16_t MR6; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value of DDR mode register MR6 for all ranks for current pstate. Note: The initial VrefDq value and range must be set in A6:A0.
+ uint8_t X16Present; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // X16 device map. Corresponds to CS[3:0].
+ // X16Present[0] = CS0 is populated with X16 devices
+ // X16Present[1] = CS1 is populated with X16 devices
+ // X16Present[2] = CS2 is populated with X16 devices
+ // X16Present[3] = CS3 is populated with X16 devices
+ // X16Present[7:4] = Reserved (must be programmed to 0)
+ //
+ // Ranks may not contain mixed device types.
+ uint8_t CsSetupGDDec; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // controls timing of chip select signals when DDR4 gear-down mode is active
+ // 0 - Leave delay of chip select timing group signal the same both before and after gear-down sync occurs
+ // 1 - Add 1UI of delay to chip select timing group signals when geardown-mode is active. This allows CS signals to have equal setup and hold time in gear-down mode
+ uint16_t RTT_NOM_WR_PARK0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 0 DRAM:
+ // RTT_NOM_WR_PARK0[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK0[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 0
+ // RTT_NOM_WR_PARK0[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 0
+ // RTT_NOM_WR_PARK0[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 0
+ uint16_t RTT_NOM_WR_PARK1; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 1 DRAM:
+ // RTT_NOM_WR_PARK1[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK1[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 1
+ // RTT_NOM_WR_PARK1[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 1
+ // RTT_NOM_WR_PARK1[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 1
+ uint16_t RTT_NOM_WR_PARK2; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 2 DRAM:
+ // RTT_NOM_WR_PARK2[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK2[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 2
+ // RTT_NOM_WR_PARK2[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 2
+ // RTT_NOM_WR_PARK2[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 2
+ uint16_t RTT_NOM_WR_PARK3; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 3 DRAM:
+ // RTT_NOM_WR_PARK3[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK3[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 3
+ // RTT_NOM_WR_PARK3[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 3
+ // RTT_NOM_WR_PARK3[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 3
+ uint16_t RTT_NOM_WR_PARK4; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 4 DRAM:
+ // RTT_NOM_WR_PARK4[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK4[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 4
+ // RTT_NOM_WR_PARK4[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 4
+ // RTT_NOM_WR_PARK4[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 4
+ uint16_t RTT_NOM_WR_PARK5; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 5 DRAM:
+ // RTT_NOM_WR_PARK5[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK5[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 5
+ // RTT_NOM_WR_PARK5[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 5
+ // RTT_NOM_WR_PARK5[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 5
+ uint16_t RTT_NOM_WR_PARK6; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 6 DRAM:
+ // RTT_NOM_WR_PARK6[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK6[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 6
+ // RTT_NOM_WR_PARK6[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 6
+ // RTT_NOM_WR_PARK6[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 6
+ uint16_t RTT_NOM_WR_PARK7; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Optional RTT_NOM, RTT_WR and RTT_PARK values for rank 7 DRAM:
+ // RTT_NOM_WR_PARK7[0] = 1: Option is enable (otherwise, remaining bit fields are don't care)
+ // RTT_NOM_WR_PARK7[5:3]: Optional RTT_NOM value to be used in MR1[10:8] for rank 7
+ // RTT_NOM_WR_PARK7[11:9]: Optional RTT_WR value to be used in MR2[11:9] for rank 7
+ // RTT_NOM_WR_PARK7[8:6]: Optional RTT_PARK value to be used in MR5[8:6] for rank 7
+ uint8_t AcsmOdtCtrl0; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl1; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=In
+ // Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl2; // Byte offset 0x80, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 2. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl3; // Byte offset 0x81, CSR Addr 0x54040, Direction=In
+ // Odt pattern for accesses targeting rank 3. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl4; // Byte offset 0x82, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 4. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl5; // Byte offset 0x83, CSR Addr 0x54041, Direction=In
+ // Odt pattern for accesses targeting rank 5. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl6; // Byte offset 0x84, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 6. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t AcsmOdtCtrl7; // Byte offset 0x85, CSR Addr 0x54042, Direction=In
+ // Odt pattern for accesses targeting rank 7. [3:0] is used for write ODT [7:4] is used for read ODT
+ uint8_t VrefDqR0Nib0; // Byte offset 0x86, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib1; // Byte offset 0x87, CSR Addr 0x54043, Direction=InOut
+ // VrefDq for rank 0 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib2; // Byte offset 0x88, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices.
+ uint8_t VrefDqR0Nib3; // Byte offset 0x89, CSR Addr 0x54044, Direction=InOut
+ // VrefDq for rank 0 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR0Nib0 for x16 devices, or VrefDqR0Nib2 for x8 devices.
+ uint8_t VrefDqR0Nib4; // Byte offset 0x8a, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib5; // Byte offset 0x8b, CSR Addr 0x54045, Direction=InOut
+ // VrefDq for rank 0 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib6; // Byte offset 0x8c, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices.
+ uint8_t VrefDqR0Nib7; // Byte offset 0x8d, CSR Addr 0x54046, Direction=InOut
+ // VrefDq for rank 0 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR0Nib4 for x16 devices, or VrefDqR0Nib6 for x8 devices.
+ uint8_t VrefDqR0Nib8; // Byte offset 0x8e, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib9; // Byte offset 0x8f, CSR Addr 0x54047, Direction=InOut
+ // VrefDq for rank 0 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib10; // Byte offset 0x90, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices.
+ uint8_t VrefDqR0Nib11; // Byte offset 0x91, CSR Addr 0x54048, Direction=InOut
+ // VrefDq for rank 0 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR0Nib8 for x16 devices, or VrefDqR0Nib10 for x8 devices.
+ uint8_t VrefDqR0Nib12; // Byte offset 0x92, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib13; // Byte offset 0x93, CSR Addr 0x54049, Direction=InOut
+ // VrefDq for rank 0 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib14; // Byte offset 0x94, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices.
+ uint8_t VrefDqR0Nib15; // Byte offset 0x95, CSR Addr 0x5404a, Direction=InOut
+ // VrefDq for rank 0 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR0Nib12 for x16 devices, or VrefDqR0Nib14 for x8 devices.
+ uint8_t VrefDqR0Nib16; // Byte offset 0x96, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR0Nib17; // Byte offset 0x97, CSR Addr 0x5404b, Direction=InOut
+ // VrefDq for rank 0 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR0Nib18; // Byte offset 0x98, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices.
+ uint8_t VrefDqR0Nib19; // Byte offset 0x99, CSR Addr 0x5404c, Direction=InOut
+ // VrefDq for rank 0 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR0Nib16 for x16 devices, or VrefDqR0Nib18 for x8 devices.
+ uint8_t VrefDqR1Nib0; // Byte offset 0x9a, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib1; // Byte offset 0x9b, CSR Addr 0x5404d, Direction=InOut
+ // VrefDq for rank 1 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib2; // Byte offset 0x9c, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices.
+ uint8_t VrefDqR1Nib3; // Byte offset 0x9d, CSR Addr 0x5404e, Direction=InOut
+ // VrefDq for rank 1 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR1Nib0 for x16 devices, or VrefDqR1Nib2 for x8 devices.
+ uint8_t VrefDqR1Nib4; // Byte offset 0x9e, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib5; // Byte offset 0x9f, CSR Addr 0x5404f, Direction=InOut
+ // VrefDq for rank 1 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib6; // Byte offset 0xa0, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices.
+ uint8_t VrefDqR1Nib7; // Byte offset 0xa1, CSR Addr 0x54050, Direction=InOut
+ // VrefDq for rank 1 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR1Nib4 for x16 devices, or VrefDqR1Nib6 for x8 devices.
+ uint8_t VrefDqR1Nib8; // Byte offset 0xa2, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib9; // Byte offset 0xa3, CSR Addr 0x54051, Direction=InOut
+ // VrefDq for rank 1 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib10; // Byte offset 0xa4, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices.
+ uint8_t VrefDqR1Nib11; // Byte offset 0xa5, CSR Addr 0x54052, Direction=InOut
+ // VrefDq for rank 1 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR1Nib8 for x16 devices, or VrefDqR1Nib10 for x8 devices.
+ uint8_t VrefDqR1Nib12; // Byte offset 0xa6, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib13; // Byte offset 0xa7, CSR Addr 0x54053, Direction=InOut
+ // VrefDq for rank 1 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib14; // Byte offset 0xa8, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices.
+ uint8_t VrefDqR1Nib15; // Byte offset 0xa9, CSR Addr 0x54054, Direction=InOut
+ // VrefDq for rank 1 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR1Nib12 for x16 devices, or VrefDqR1Nib14 for x8 devices.
+ uint8_t VrefDqR1Nib16; // Byte offset 0xaa, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR1Nib17; // Byte offset 0xab, CSR Addr 0x54055, Direction=InOut
+ // VrefDq for rank 1 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR1Nib18; // Byte offset 0xac, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices.
+ uint8_t VrefDqR1Nib19; // Byte offset 0xad, CSR Addr 0x54056, Direction=InOut
+ // VrefDq for rank 1 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR1Nib16 for x16 devices, or VrefDqR1Nib18 for x8 devices.
+ uint8_t VrefDqR2Nib0; // Byte offset 0xae, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib1; // Byte offset 0xaf, CSR Addr 0x54057, Direction=InOut
+ // VrefDq for rank 2 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib2; // Byte offset 0xb0, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices.
+ uint8_t VrefDqR2Nib3; // Byte offset 0xb1, CSR Addr 0x54058, Direction=InOut
+ // VrefDq for rank 2 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR2Nib0 for x16 devices, or VrefDqR2Nib2 for x8 devices.
+ uint8_t VrefDqR2Nib4; // Byte offset 0xb2, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib5; // Byte offset 0xb3, CSR Addr 0x54059, Direction=InOut
+ // VrefDq for rank 2 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib6; // Byte offset 0xb4, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices.
+ uint8_t VrefDqR2Nib7; // Byte offset 0xb5, CSR Addr 0x5405a, Direction=InOut
+ // VrefDq for rank 2 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR2Nib4 for x16 devices, or VrefDqR2Nib6 for x8 devices.
+ uint8_t VrefDqR2Nib8; // Byte offset 0xb6, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib9; // Byte offset 0xb7, CSR Addr 0x5405b, Direction=InOut
+ // VrefDq for rank 2 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib10; // Byte offset 0xb8, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices.
+ uint8_t VrefDqR2Nib11; // Byte offset 0xb9, CSR Addr 0x5405c, Direction=InOut
+ // VrefDq for rank 2 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR2Nib8 for x16 devices, or VrefDqR2Nib10 for x8 devices.
+ uint8_t VrefDqR2Nib12; // Byte offset 0xba, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib13; // Byte offset 0xbb, CSR Addr 0x5405d, Direction=InOut
+ // VrefDq for rank 2 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib14; // Byte offset 0xbc, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices.
+ uint8_t VrefDqR2Nib15; // Byte offset 0xbd, CSR Addr 0x5405e, Direction=InOut
+ // VrefDq for rank 2 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR2Nib12 for x16 devices, or VrefDqR2Nib14 for x8 devices.
+ uint8_t VrefDqR2Nib16; // Byte offset 0xbe, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR2Nib17; // Byte offset 0xbf, CSR Addr 0x5405f, Direction=InOut
+ // VrefDq for rank 2 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR2Nib18; // Byte offset 0xc0, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices.
+ uint8_t VrefDqR2Nib19; // Byte offset 0xc1, CSR Addr 0x54060, Direction=InOut
+ // VrefDq for rank 2 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR2Nib16 for x16 devices, or VrefDqR2Nib18 for x8 devices.
+ uint8_t VrefDqR3Nib0; // Byte offset 0xc2, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 0. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib1; // Byte offset 0xc3, CSR Addr 0x54061, Direction=InOut
+ // VrefDq for rank 3 nibble 1. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib2; // Byte offset 0xc4, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 2. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices.
+ uint8_t VrefDqR3Nib3; // Byte offset 0xc5, CSR Addr 0x54062, Direction=InOut
+ // VrefDq for rank 3 nibble 3. Specifies MR6[6:0]. Identical to VrefDqR3Nib0 for x16 devices, or VrefDqR3Nib2 for x8 devices.
+ uint8_t VrefDqR3Nib4; // Byte offset 0xc6, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 4. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib5; // Byte offset 0xc7, CSR Addr 0x54063, Direction=InOut
+ // VrefDq for rank 3 nibble 5. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib6; // Byte offset 0xc8, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 6. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices.
+ uint8_t VrefDqR3Nib7; // Byte offset 0xc9, CSR Addr 0x54064, Direction=InOut
+ // VrefDq for rank 3 nibble 7. Specifies MR6[6:0]. Identical to VrefDqR3Nib4 for x16 devices, or VrefDqR3Nib6 for x8 devices.
+ uint8_t VrefDqR3Nib8; // Byte offset 0xca, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 8. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib9; // Byte offset 0xcb, CSR Addr 0x54065, Direction=InOut
+ // VrefDq for rank 3 nibble 9. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib10; // Byte offset 0xcc, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 10. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices.
+ uint8_t VrefDqR3Nib11; // Byte offset 0xcd, CSR Addr 0x54066, Direction=InOut
+ // VrefDq for rank 3 nibble 11. Specifies MR6[6:0]. Identical to VrefDqR3Nib8 for x16 devices, or VrefDqR3Nib10 for x8 devices.
+ uint8_t VrefDqR3Nib12; // Byte offset 0xce, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 12. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib13; // Byte offset 0xcf, CSR Addr 0x54067, Direction=InOut
+ // VrefDq for rank 3 nibble 13. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib14; // Byte offset 0xd0, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 14. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices.
+ uint8_t VrefDqR3Nib15; // Byte offset 0xd1, CSR Addr 0x54068, Direction=InOut
+ // VrefDq for rank 3 nibble 15. Specifies MR6[6:0]. Identical to VrefDqR3Nib12 for x16 devices, or VrefDqR3Nib14 for x8 devices.
+ uint8_t VrefDqR3Nib16; // Byte offset 0xd2, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 16. Specifies MR6[6:0]
+ uint8_t VrefDqR3Nib17; // Byte offset 0xd3, CSR Addr 0x54069, Direction=InOut
+ // VrefDq for rank 3 nibble 17. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x8 or x16 devices.
+ uint8_t VrefDqR3Nib18; // Byte offset 0xd4, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 18. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices.
+ uint8_t VrefDqR3Nib19; // Byte offset 0xd5, CSR Addr 0x5406a, Direction=InOut
+ // VrefDq for rank 3 nibble 19. Specifies MR6[6:0]. Identical to VrefDqR3Nib16 for x16 devices, or VrefDqR3Nib18 for x8 devices.
+ uint8_t ReservedD6; // Byte offset 0xd6, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD7; // Byte offset 0xd7, CSR Addr 0x5406b, Direction=N/A
+
+ uint8_t ReservedD8; // Byte offset 0xd8, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedD9; // Byte offset 0xd9, CSR Addr 0x5406c, Direction=N/A
+
+ uint8_t ReservedDA; // Byte offset 0xda, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDB; // Byte offset 0xdb, CSR Addr 0x5406d, Direction=N/A
+
+ uint8_t ReservedDC; // Byte offset 0xdc, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDD; // Byte offset 0xdd, CSR Addr 0x5406e, Direction=N/A
+
+ uint8_t ReservedDE; // Byte offset 0xde, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedDF; // Byte offset 0xdf, CSR Addr 0x5406f, Direction=N/A
+
+ uint8_t ReservedE0; // Byte offset 0xe0, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE1; // Byte offset 0xe1, CSR Addr 0x54070, Direction=N/A
+
+ uint8_t ReservedE2; // Byte offset 0xe2, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE3; // Byte offset 0xe3, CSR Addr 0x54071, Direction=N/A
+
+ uint8_t ReservedE4; // Byte offset 0xe4, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE5; // Byte offset 0xe5, CSR Addr 0x54072, Direction=N/A
+
+ uint8_t ReservedE6; // Byte offset 0xe6, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE7; // Byte offset 0xe7, CSR Addr 0x54073, Direction=N/A
+
+ uint8_t ReservedE8; // Byte offset 0xe8, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedE9; // Byte offset 0xe9, CSR Addr 0x54074, Direction=N/A
+
+ uint8_t ReservedEA; // Byte offset 0xea, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEB; // Byte offset 0xeb, CSR Addr 0x54075, Direction=N/A
+
+ uint8_t ReservedEC; // Byte offset 0xec, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedED; // Byte offset 0xed, CSR Addr 0x54076, Direction=N/A
+
+ uint8_t ReservedEE; // Byte offset 0xee, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedEF; // Byte offset 0xef, CSR Addr 0x54077, Direction=N/A
+
+ uint8_t ReservedF0; // Byte offset 0xf0, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF1; // Byte offset 0xf1, CSR Addr 0x54078, Direction=N/A
+
+ uint8_t ReservedF2; // Byte offset 0xf2, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF3; // Byte offset 0xf3, CSR Addr 0x54079, Direction=N/A
+
+ uint8_t ReservedF4; // Byte offset 0xf4, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF5; // Byte offset 0xf5, CSR Addr 0x5407a, Direction=N/A
+
+ uint8_t ReservedF6; // Byte offset 0xf6, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF7; // Byte offset 0xf7, CSR Addr 0x5407b, Direction=N/A
+
+ uint8_t ReservedF8; // Byte offset 0xf8, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedF9; // Byte offset 0xf9, CSR Addr 0x5407c, Direction=N/A
+
+ uint8_t ReservedFA; // Byte offset 0xfa, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFB; // Byte offset 0xfb, CSR Addr 0x5407d, Direction=N/A
+
+ uint8_t ReservedFC; // Byte offset 0xfc, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFD; // Byte offset 0xfd, CSR Addr 0x5407e, Direction=N/A
+
+ uint8_t ReservedFE; // Byte offset 0xfe, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t ReservedFF; // Byte offset 0xff, CSR Addr 0x5407f, Direction=N/A
+
+ uint8_t Reserved100; // Byte offset 0x100, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved101; // Byte offset 0x101, CSR Addr 0x54080, Direction=N/A
+
+ uint8_t Reserved102; // Byte offset 0x102, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved103; // Byte offset 0x103, CSR Addr 0x54081, Direction=N/A
+
+ uint8_t Reserved104; // Byte offset 0x104, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved105; // Byte offset 0x105, CSR Addr 0x54082, Direction=N/A
+
+ uint8_t Reserved106; // Byte offset 0x106, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved107; // Byte offset 0x107, CSR Addr 0x54083, Direction=N/A
+
+ uint8_t Reserved108; // Byte offset 0x108, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved109; // Byte offset 0x109, CSR Addr 0x54084, Direction=N/A
+
+ uint8_t Reserved10A; // Byte offset 0x10a, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10B; // Byte offset 0x10b, CSR Addr 0x54085, Direction=N/A
+
+ uint8_t Reserved10C; // Byte offset 0x10c, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10D; // Byte offset 0x10d, CSR Addr 0x54086, Direction=N/A
+
+ uint8_t Reserved10E; // Byte offset 0x10e, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved10F; // Byte offset 0x10f, CSR Addr 0x54087, Direction=N/A
+
+ uint8_t Reserved110; // Byte offset 0x110, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved111; // Byte offset 0x111, CSR Addr 0x54088, Direction=N/A
+
+ uint8_t Reserved112; // Byte offset 0x112, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved113; // Byte offset 0x113, CSR Addr 0x54089, Direction=N/A
+
+ uint8_t Reserved114; // Byte offset 0x114, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved115; // Byte offset 0x115, CSR Addr 0x5408a, Direction=N/A
+
+ uint8_t Reserved116; // Byte offset 0x116, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved117; // Byte offset 0x117, CSR Addr 0x5408b, Direction=N/A
+
+ uint8_t Reserved118; // Byte offset 0x118, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved119; // Byte offset 0x119, CSR Addr 0x5408c, Direction=N/A
+
+ uint8_t Reserved11A; // Byte offset 0x11a, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11B; // Byte offset 0x11b, CSR Addr 0x5408d, Direction=N/A
+
+ uint8_t Reserved11C; // Byte offset 0x11c, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11D; // Byte offset 0x11d, CSR Addr 0x5408e, Direction=N/A
+
+ uint8_t Reserved11E; // Byte offset 0x11e, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved11F; // Byte offset 0x11f, CSR Addr 0x5408f, Direction=N/A
+
+ uint8_t Reserved120; // Byte offset 0x120, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved121; // Byte offset 0x121, CSR Addr 0x54090, Direction=N/A
+
+ uint8_t Reserved122; // Byte offset 0x122, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved123; // Byte offset 0x123, CSR Addr 0x54091, Direction=N/A
+
+ uint8_t Reserved124; // Byte offset 0x124, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved125; // Byte offset 0x125, CSR Addr 0x54092, Direction=N/A
+
+ uint8_t Reserved126; // Byte offset 0x126, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved127; // Byte offset 0x127, CSR Addr 0x54093, Direction=N/A
+
+ uint8_t Reserved128; // Byte offset 0x128, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved129; // Byte offset 0x129, CSR Addr 0x54094, Direction=N/A
+
+ uint8_t Reserved12A; // Byte offset 0x12a, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12B; // Byte offset 0x12b, CSR Addr 0x54095, Direction=N/A
+
+ uint8_t Reserved12C; // Byte offset 0x12c, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12D; // Byte offset 0x12d, CSR Addr 0x54096, Direction=N/A
+
+ uint8_t Reserved12E; // Byte offset 0x12e, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved12F; // Byte offset 0x12f, CSR Addr 0x54097, Direction=N/A
+
+ uint8_t Reserved130; // Byte offset 0x130, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved131; // Byte offset 0x131, CSR Addr 0x54098, Direction=N/A
+
+ uint8_t Reserved132; // Byte offset 0x132, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved133; // Byte offset 0x133, CSR Addr 0x54099, Direction=N/A
+
+ uint8_t Reserved134; // Byte offset 0x134, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved135; // Byte offset 0x135, CSR Addr 0x5409a, Direction=N/A
+
+ uint8_t Reserved136; // Byte offset 0x136, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved137; // Byte offset 0x137, CSR Addr 0x5409b, Direction=N/A
+
+ uint8_t Reserved138; // Byte offset 0x138, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved139; // Byte offset 0x139, CSR Addr 0x5409c, Direction=N/A
+
+ uint8_t Reserved13A; // Byte offset 0x13a, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13B; // Byte offset 0x13b, CSR Addr 0x5409d, Direction=N/A
+
+ uint8_t Reserved13C; // Byte offset 0x13c, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13D; // Byte offset 0x13d, CSR Addr 0x5409e, Direction=N/A
+
+ uint8_t Reserved13E; // Byte offset 0x13e, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved13F; // Byte offset 0x13f, CSR Addr 0x5409f, Direction=N/A
+
+ uint8_t Reserved140; // Byte offset 0x140, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved141; // Byte offset 0x141, CSR Addr 0x540a0, Direction=N/A
+
+ uint8_t Reserved142; // Byte offset 0x142, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved143; // Byte offset 0x143, CSR Addr 0x540a1, Direction=N/A
+
+ uint8_t Reserved144; // Byte offset 0x144, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved145; // Byte offset 0x145, CSR Addr 0x540a2, Direction=N/A
+
+ uint8_t Reserved146; // Byte offset 0x146, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved147; // Byte offset 0x147, CSR Addr 0x540a3, Direction=N/A
+
+ uint8_t Reserved148; // Byte offset 0x148, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved149; // Byte offset 0x149, CSR Addr 0x540a4, Direction=N/A
+
+ uint8_t Reserved14A; // Byte offset 0x14a, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14B; // Byte offset 0x14b, CSR Addr 0x540a5, Direction=N/A
+
+ uint8_t Reserved14C; // Byte offset 0x14c, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14D; // Byte offset 0x14d, CSR Addr 0x540a6, Direction=N/A
+
+ uint8_t Reserved14E; // Byte offset 0x14e, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved14F; // Byte offset 0x14f, CSR Addr 0x540a7, Direction=N/A
+
+ uint8_t Reserved150; // Byte offset 0x150, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved151; // Byte offset 0x151, CSR Addr 0x540a8, Direction=N/A
+
+ uint8_t Reserved152; // Byte offset 0x152, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved153; // Byte offset 0x153, CSR Addr 0x540a9, Direction=N/A
+
+ uint8_t Reserved154; // Byte offset 0x154, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved155; // Byte offset 0x155, CSR Addr 0x540aa, Direction=N/A
+
+ uint8_t Reserved156; // Byte offset 0x156, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved157; // Byte offset 0x157, CSR Addr 0x540ab, Direction=N/A
+
+ uint8_t Reserved158; // Byte offset 0x158, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved159; // Byte offset 0x159, CSR Addr 0x540ac, Direction=N/A
+
+ uint8_t Reserved15A; // Byte offset 0x15a, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15B; // Byte offset 0x15b, CSR Addr 0x540ad, Direction=N/A
+
+ uint8_t Reserved15C; // Byte offset 0x15c, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15D; // Byte offset 0x15d, CSR Addr 0x540ae, Direction=N/A
+
+ uint8_t Reserved15E; // Byte offset 0x15e, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved15F; // Byte offset 0x15f, CSR Addr 0x540af, Direction=N/A
+
+ uint8_t Reserved160; // Byte offset 0x160, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved161; // Byte offset 0x161, CSR Addr 0x540b0, Direction=N/A
+
+ uint8_t Reserved162; // Byte offset 0x162, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved163; // Byte offset 0x163, CSR Addr 0x540b1, Direction=N/A
+
+ uint8_t Reserved164; // Byte offset 0x164, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved165; // Byte offset 0x165, CSR Addr 0x540b2, Direction=N/A
+
+ uint8_t Reserved166; // Byte offset 0x166, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved167; // Byte offset 0x167, CSR Addr 0x540b3, Direction=N/A
+
+ uint8_t Reserved168; // Byte offset 0x168, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved169; // Byte offset 0x169, CSR Addr 0x540b4, Direction=N/A
+
+ uint8_t Reserved16A; // Byte offset 0x16a, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16B; // Byte offset 0x16b, CSR Addr 0x540b5, Direction=N/A
+
+ uint8_t Reserved16C; // Byte offset 0x16c, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16D; // Byte offset 0x16d, CSR Addr 0x540b6, Direction=N/A
+
+ uint8_t Reserved16E; // Byte offset 0x16e, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved16F; // Byte offset 0x16f, CSR Addr 0x540b7, Direction=N/A
+
+ uint8_t Reserved170; // Byte offset 0x170, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved171; // Byte offset 0x171, CSR Addr 0x540b8, Direction=N/A
+
+ uint8_t Reserved172; // Byte offset 0x172, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved173; // Byte offset 0x173, CSR Addr 0x540b9, Direction=N/A
+
+ uint8_t Reserved174; // Byte offset 0x174, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved175; // Byte offset 0x175, CSR Addr 0x540ba, Direction=N/A
+
+ uint8_t Reserved176; // Byte offset 0x176, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved177; // Byte offset 0x177, CSR Addr 0x540bb, Direction=N/A
+
+ uint8_t Reserved178; // Byte offset 0x178, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved179; // Byte offset 0x179, CSR Addr 0x540bc, Direction=N/A
+
+ uint8_t Reserved17A; // Byte offset 0x17a, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17B; // Byte offset 0x17b, CSR Addr 0x540bd, Direction=N/A
+
+ uint8_t Reserved17C; // Byte offset 0x17c, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17D; // Byte offset 0x17d, CSR Addr 0x540be, Direction=N/A
+
+ uint8_t Reserved17E; // Byte offset 0x17e, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved17F; // Byte offset 0x17f, CSR Addr 0x540bf, Direction=N/A
+
+ uint8_t Reserved180; // Byte offset 0x180, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved181; // Byte offset 0x181, CSR Addr 0x540c0, Direction=N/A
+
+ uint8_t Reserved182; // Byte offset 0x182, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved183; // Byte offset 0x183, CSR Addr 0x540c1, Direction=N/A
+
+ uint8_t Reserved184; // Byte offset 0x184, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved185; // Byte offset 0x185, CSR Addr 0x540c2, Direction=N/A
+
+ uint8_t Reserved186; // Byte offset 0x186, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved187; // Byte offset 0x187, CSR Addr 0x540c3, Direction=N/A
+
+ uint8_t Reserved188; // Byte offset 0x188, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved189; // Byte offset 0x189, CSR Addr 0x540c4, Direction=N/A
+
+ uint8_t Reserved18A; // Byte offset 0x18a, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18B; // Byte offset 0x18b, CSR Addr 0x540c5, Direction=N/A
+
+ uint8_t Reserved18C; // Byte offset 0x18c, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18D; // Byte offset 0x18d, CSR Addr 0x540c6, Direction=N/A
+
+ uint8_t Reserved18E; // Byte offset 0x18e, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved18F; // Byte offset 0x18f, CSR Addr 0x540c7, Direction=N/A
+
+ uint8_t Reserved190; // Byte offset 0x190, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved191; // Byte offset 0x191, CSR Addr 0x540c8, Direction=N/A
+
+ uint8_t Reserved192; // Byte offset 0x192, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved193; // Byte offset 0x193, CSR Addr 0x540c9, Direction=N/A
+
+ uint8_t Reserved194; // Byte offset 0x194, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved195; // Byte offset 0x195, CSR Addr 0x540ca, Direction=N/A
+
+ uint8_t Reserved196; // Byte offset 0x196, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved197; // Byte offset 0x197, CSR Addr 0x540cb, Direction=N/A
+
+ uint8_t Reserved198; // Byte offset 0x198, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved199; // Byte offset 0x199, CSR Addr 0x540cc, Direction=N/A
+
+ uint8_t Reserved19A; // Byte offset 0x19a, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19B; // Byte offset 0x19b, CSR Addr 0x540cd, Direction=N/A
+
+ uint8_t Reserved19C; // Byte offset 0x19c, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19D; // Byte offset 0x19d, CSR Addr 0x540ce, Direction=N/A
+
+ uint8_t Reserved19E; // Byte offset 0x19e, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved19F; // Byte offset 0x19f, CSR Addr 0x540cf, Direction=N/A
+
+ uint8_t Reserved1A0; // Byte offset 0x1a0, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A1; // Byte offset 0x1a1, CSR Addr 0x540d0, Direction=N/A
+
+ uint8_t Reserved1A2; // Byte offset 0x1a2, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A3; // Byte offset 0x1a3, CSR Addr 0x540d1, Direction=N/A
+
+ uint8_t Reserved1A4; // Byte offset 0x1a4, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A5; // Byte offset 0x1a5, CSR Addr 0x540d2, Direction=N/A
+
+ uint8_t Reserved1A6; // Byte offset 0x1a6, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A7; // Byte offset 0x1a7, CSR Addr 0x540d3, Direction=N/A
+
+ uint8_t Reserved1A8; // Byte offset 0x1a8, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1A9; // Byte offset 0x1a9, CSR Addr 0x540d4, Direction=N/A
+
+ uint8_t Reserved1AA; // Byte offset 0x1aa, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AB; // Byte offset 0x1ab, CSR Addr 0x540d5, Direction=N/A
+
+ uint8_t Reserved1AC; // Byte offset 0x1ac, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AD; // Byte offset 0x1ad, CSR Addr 0x540d6, Direction=N/A
+
+ uint8_t Reserved1AE; // Byte offset 0x1ae, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1AF; // Byte offset 0x1af, CSR Addr 0x540d7, Direction=N/A
+
+ uint8_t Reserved1B0; // Byte offset 0x1b0, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B1; // Byte offset 0x1b1, CSR Addr 0x540d8, Direction=N/A
+
+ uint8_t Reserved1B2; // Byte offset 0x1b2, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B3; // Byte offset 0x1b3, CSR Addr 0x540d9, Direction=N/A
+
+ uint8_t Reserved1B4; // Byte offset 0x1b4, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B5; // Byte offset 0x1b5, CSR Addr 0x540da, Direction=N/A
+
+ uint8_t Reserved1B6; // Byte offset 0x1b6, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B7; // Byte offset 0x1b7, CSR Addr 0x540db, Direction=N/A
+
+ uint8_t Reserved1B8; // Byte offset 0x1b8, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1B9; // Byte offset 0x1b9, CSR Addr 0x540dc, Direction=N/A
+
+ uint8_t Reserved1BA; // Byte offset 0x1ba, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BB; // Byte offset 0x1bb, CSR Addr 0x540dd, Direction=N/A
+
+ uint8_t Reserved1BC; // Byte offset 0x1bc, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BD; // Byte offset 0x1bd, CSR Addr 0x540de, Direction=N/A
+
+ uint8_t Reserved1BE; // Byte offset 0x1be, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1BF; // Byte offset 0x1bf, CSR Addr 0x540df, Direction=N/A
+
+ uint8_t Reserved1C0; // Byte offset 0x1c0, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C1; // Byte offset 0x1c1, CSR Addr 0x540e0, Direction=N/A
+
+ uint8_t Reserved1C2; // Byte offset 0x1c2, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C3; // Byte offset 0x1c3, CSR Addr 0x540e1, Direction=N/A
+
+ uint8_t Reserved1C4; // Byte offset 0x1c4, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C5; // Byte offset 0x1c5, CSR Addr 0x540e2, Direction=N/A
+
+ uint8_t Reserved1C6; // Byte offset 0x1c6, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C7; // Byte offset 0x1c7, CSR Addr 0x540e3, Direction=N/A
+
+ uint8_t Reserved1C8; // Byte offset 0x1c8, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1C9; // Byte offset 0x1c9, CSR Addr 0x540e4, Direction=N/A
+
+ uint8_t Reserved1CA; // Byte offset 0x1ca, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CB; // Byte offset 0x1cb, CSR Addr 0x540e5, Direction=N/A
+
+ uint8_t Reserved1CC; // Byte offset 0x1cc, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CD; // Byte offset 0x1cd, CSR Addr 0x540e6, Direction=N/A
+
+ uint8_t Reserved1CE; // Byte offset 0x1ce, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1CF; // Byte offset 0x1cf, CSR Addr 0x540e7, Direction=N/A
+
+ uint8_t Reserved1D0; // Byte offset 0x1d0, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D1; // Byte offset 0x1d1, CSR Addr 0x540e8, Direction=N/A
+
+ uint8_t Reserved1D2; // Byte offset 0x1d2, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D3; // Byte offset 0x1d3, CSR Addr 0x540e9, Direction=N/A
+
+ uint8_t Reserved1D4; // Byte offset 0x1d4, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D5; // Byte offset 0x1d5, CSR Addr 0x540ea, Direction=N/A
+
+ uint8_t Reserved1D6; // Byte offset 0x1d6, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D7; // Byte offset 0x1d7, CSR Addr 0x540eb, Direction=N/A
+
+ uint8_t Reserved1D8; // Byte offset 0x1d8, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1D9; // Byte offset 0x1d9, CSR Addr 0x540ec, Direction=N/A
+
+ uint8_t Reserved1DA; // Byte offset 0x1da, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DB; // Byte offset 0x1db, CSR Addr 0x540ed, Direction=N/A
+
+ uint8_t Reserved1DC; // Byte offset 0x1dc, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DD; // Byte offset 0x1dd, CSR Addr 0x540ee, Direction=N/A
+
+ uint8_t Reserved1DE; // Byte offset 0x1de, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1DF; // Byte offset 0x1df, CSR Addr 0x540ef, Direction=N/A
+
+ uint8_t Reserved1E0; // Byte offset 0x1e0, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E1; // Byte offset 0x1e1, CSR Addr 0x540f0, Direction=N/A
+
+ uint8_t Reserved1E2; // Byte offset 0x1e2, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E3; // Byte offset 0x1e3, CSR Addr 0x540f1, Direction=N/A
+
+ uint8_t Reserved1E4; // Byte offset 0x1e4, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E5; // Byte offset 0x1e5, CSR Addr 0x540f2, Direction=N/A
+
+ uint8_t Reserved1E6; // Byte offset 0x1e6, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E7; // Byte offset 0x1e7, CSR Addr 0x540f3, Direction=N/A
+
+ uint8_t Reserved1E8; // Byte offset 0x1e8, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1E9; // Byte offset 0x1e9, CSR Addr 0x540f4, Direction=N/A
+
+ uint8_t Reserved1EA; // Byte offset 0x1ea, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EB; // Byte offset 0x1eb, CSR Addr 0x540f5, Direction=N/A
+
+ uint8_t Reserved1EC; // Byte offset 0x1ec, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1ED; // Byte offset 0x1ed, CSR Addr 0x540f6, Direction=N/A
+
+ uint8_t Reserved1EE; // Byte offset 0x1ee, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1EF; // Byte offset 0x1ef, CSR Addr 0x540f7, Direction=N/A
+
+ uint8_t Reserved1F0; // Byte offset 0x1f0, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F1; // Byte offset 0x1f1, CSR Addr 0x540f8, Direction=N/A
+
+ uint8_t Reserved1F2; // Byte offset 0x1f2, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F3; // Byte offset 0x1f3, CSR Addr 0x540f9, Direction=N/A
+
+ uint8_t Reserved1F4; // Byte offset 0x1f4, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F5; // Byte offset 0x1f5, CSR Addr 0x540fa, Direction=N/A
+
+ uint8_t Reserved1F6; // Byte offset 0x1f6, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F7; // Byte offset 0x1f7, CSR Addr 0x540fb, Direction=N/A
+
+ uint8_t Reserved1F8; // Byte offset 0x1f8, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1F9; // Byte offset 0x1f9, CSR Addr 0x540fc, Direction=N/A
+
+ uint8_t Reserved1FA; // Byte offset 0x1fa, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FB; // Byte offset 0x1fb, CSR Addr 0x540fd, Direction=N/A
+
+ uint8_t Reserved1FC; // Byte offset 0x1fc, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FD; // Byte offset 0x1fd, CSR Addr 0x540fe, Direction=N/A
+
+ uint8_t Reserved1FE; // Byte offset 0x1fe, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved1FF; // Byte offset 0x1ff, CSR Addr 0x540ff, Direction=N/A
+
+ uint8_t Reserved200; // Byte offset 0x200, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved201; // Byte offset 0x201, CSR Addr 0x54100, Direction=N/A
+
+ uint8_t Reserved202; // Byte offset 0x202, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved203; // Byte offset 0x203, CSR Addr 0x54101, Direction=N/A
+
+ uint8_t Reserved204; // Byte offset 0x204, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved205; // Byte offset 0x205, CSR Addr 0x54102, Direction=N/A
+
+ uint8_t Reserved206; // Byte offset 0x206, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved207; // Byte offset 0x207, CSR Addr 0x54103, Direction=N/A
+
+ uint8_t Reserved208; // Byte offset 0x208, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved209; // Byte offset 0x209, CSR Addr 0x54104, Direction=N/A
+
+ uint8_t Reserved20A; // Byte offset 0x20a, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20B; // Byte offset 0x20b, CSR Addr 0x54105, Direction=N/A
+
+ uint8_t Reserved20C; // Byte offset 0x20c, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20D; // Byte offset 0x20d, CSR Addr 0x54106, Direction=N/A
+
+ uint8_t Reserved20E; // Byte offset 0x20e, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved20F; // Byte offset 0x20f, CSR Addr 0x54107, Direction=N/A
+
+ uint8_t Reserved210; // Byte offset 0x210, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved211; // Byte offset 0x211, CSR Addr 0x54108, Direction=N/A
+
+ uint8_t Reserved212; // Byte offset 0x212, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved213; // Byte offset 0x213, CSR Addr 0x54109, Direction=N/A
+
+ uint8_t Reserved214; // Byte offset 0x214, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved215; // Byte offset 0x215, CSR Addr 0x5410a, Direction=N/A
+
+ uint8_t Reserved216; // Byte offset 0x216, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved217; // Byte offset 0x217, CSR Addr 0x5410b, Direction=N/A
+
+ uint8_t Reserved218; // Byte offset 0x218, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved219; // Byte offset 0x219, CSR Addr 0x5410c, Direction=N/A
+
+ uint8_t Reserved21A; // Byte offset 0x21a, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21B; // Byte offset 0x21b, CSR Addr 0x5410d, Direction=N/A
+
+ uint8_t Reserved21C; // Byte offset 0x21c, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21D; // Byte offset 0x21d, CSR Addr 0x5410e, Direction=N/A
+
+ uint8_t Reserved21E; // Byte offset 0x21e, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved21F; // Byte offset 0x21f, CSR Addr 0x5410f, Direction=N/A
+
+ uint8_t Reserved220; // Byte offset 0x220, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved221; // Byte offset 0x221, CSR Addr 0x54110, Direction=N/A
+
+ uint8_t Reserved222; // Byte offset 0x222, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved223; // Byte offset 0x223, CSR Addr 0x54111, Direction=N/A
+
+ uint8_t Reserved224; // Byte offset 0x224, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved225; // Byte offset 0x225, CSR Addr 0x54112, Direction=N/A
+
+ uint8_t Reserved226; // Byte offset 0x226, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved227; // Byte offset 0x227, CSR Addr 0x54113, Direction=N/A
+
+ uint8_t Reserved228; // Byte offset 0x228, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved229; // Byte offset 0x229, CSR Addr 0x54114, Direction=N/A
+
+ uint8_t Reserved22A; // Byte offset 0x22a, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22B; // Byte offset 0x22b, CSR Addr 0x54115, Direction=N/A
+
+ uint8_t Reserved22C; // Byte offset 0x22c, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22D; // Byte offset 0x22d, CSR Addr 0x54116, Direction=N/A
+
+ uint8_t Reserved22E; // Byte offset 0x22e, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved22F; // Byte offset 0x22f, CSR Addr 0x54117, Direction=N/A
+
+ uint8_t Reserved230; // Byte offset 0x230, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved231; // Byte offset 0x231, CSR Addr 0x54118, Direction=N/A
+
+ uint8_t Reserved232; // Byte offset 0x232, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved233; // Byte offset 0x233, CSR Addr 0x54119, Direction=N/A
+
+ uint8_t Reserved234; // Byte offset 0x234, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved235; // Byte offset 0x235, CSR Addr 0x5411a, Direction=N/A
+
+ uint8_t Reserved236; // Byte offset 0x236, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved237; // Byte offset 0x237, CSR Addr 0x5411b, Direction=N/A
+
+ uint8_t Reserved238; // Byte offset 0x238, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved239; // Byte offset 0x239, CSR Addr 0x5411c, Direction=N/A
+
+ uint8_t Reserved23A; // Byte offset 0x23a, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23B; // Byte offset 0x23b, CSR Addr 0x5411d, Direction=N/A
+
+ uint8_t Reserved23C; // Byte offset 0x23c, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23D; // Byte offset 0x23d, CSR Addr 0x5411e, Direction=N/A
+
+ uint8_t Reserved23E; // Byte offset 0x23e, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved23F; // Byte offset 0x23f, CSR Addr 0x5411f, Direction=N/A
+
+ uint8_t Reserved240; // Byte offset 0x240, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved241; // Byte offset 0x241, CSR Addr 0x54120, Direction=N/A
+
+ uint8_t Reserved242; // Byte offset 0x242, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved243; // Byte offset 0x243, CSR Addr 0x54121, Direction=N/A
+
+ uint8_t Reserved244; // Byte offset 0x244, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved245; // Byte offset 0x245, CSR Addr 0x54122, Direction=N/A
+
+ uint8_t Reserved246; // Byte offset 0x246, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved247; // Byte offset 0x247, CSR Addr 0x54123, Direction=N/A
+
+ uint8_t Reserved248; // Byte offset 0x248, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved249; // Byte offset 0x249, CSR Addr 0x54124, Direction=N/A
+
+ uint8_t Reserved24A; // Byte offset 0x24a, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24B; // Byte offset 0x24b, CSR Addr 0x54125, Direction=N/A
+
+ uint8_t Reserved24C; // Byte offset 0x24c, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24D; // Byte offset 0x24d, CSR Addr 0x54126, Direction=N/A
+
+ uint8_t Reserved24E; // Byte offset 0x24e, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved24F; // Byte offset 0x24f, CSR Addr 0x54127, Direction=N/A
+
+ uint8_t Reserved250; // Byte offset 0x250, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved251; // Byte offset 0x251, CSR Addr 0x54128, Direction=N/A
+
+ uint8_t Reserved252; // Byte offset 0x252, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved253; // Byte offset 0x253, CSR Addr 0x54129, Direction=N/A
+
+ uint8_t Reserved254; // Byte offset 0x254, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved255; // Byte offset 0x255, CSR Addr 0x5412a, Direction=N/A
+
+ uint8_t Reserved256; // Byte offset 0x256, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved257; // Byte offset 0x257, CSR Addr 0x5412b, Direction=N/A
+
+ uint8_t Reserved258; // Byte offset 0x258, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved259; // Byte offset 0x259, CSR Addr 0x5412c, Direction=N/A
+
+ uint8_t Reserved25A; // Byte offset 0x25a, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25B; // Byte offset 0x25b, CSR Addr 0x5412d, Direction=N/A
+
+ uint8_t Reserved25C; // Byte offset 0x25c, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25D; // Byte offset 0x25d, CSR Addr 0x5412e, Direction=N/A
+
+ uint8_t Reserved25E; // Byte offset 0x25e, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved25F; // Byte offset 0x25f, CSR Addr 0x5412f, Direction=N/A
+
+ uint8_t Reserved260; // Byte offset 0x260, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved261; // Byte offset 0x261, CSR Addr 0x54130, Direction=N/A
+
+ uint8_t Reserved262; // Byte offset 0x262, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved263; // Byte offset 0x263, CSR Addr 0x54131, Direction=N/A
+
+ uint8_t Reserved264; // Byte offset 0x264, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved265; // Byte offset 0x265, CSR Addr 0x54132, Direction=N/A
+
+ uint8_t Reserved266; // Byte offset 0x266, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved267; // Byte offset 0x267, CSR Addr 0x54133, Direction=N/A
+
+ uint8_t Reserved268; // Byte offset 0x268, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved269; // Byte offset 0x269, CSR Addr 0x54134, Direction=N/A
+
+ uint8_t Reserved26A; // Byte offset 0x26a, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26B; // Byte offset 0x26b, CSR Addr 0x54135, Direction=N/A
+
+ uint8_t Reserved26C; // Byte offset 0x26c, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26D; // Byte offset 0x26d, CSR Addr 0x54136, Direction=N/A
+
+ uint8_t Reserved26E; // Byte offset 0x26e, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved26F; // Byte offset 0x26f, CSR Addr 0x54137, Direction=N/A
+
+ uint8_t Reserved270; // Byte offset 0x270, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved271; // Byte offset 0x271, CSR Addr 0x54138, Direction=N/A
+
+ uint8_t Reserved272; // Byte offset 0x272, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved273; // Byte offset 0x273, CSR Addr 0x54139, Direction=N/A
+
+ uint8_t Reserved274; // Byte offset 0x274, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved275; // Byte offset 0x275, CSR Addr 0x5413a, Direction=N/A
+
+ uint8_t Reserved276; // Byte offset 0x276, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved277; // Byte offset 0x277, CSR Addr 0x5413b, Direction=N/A
+
+ uint8_t Reserved278; // Byte offset 0x278, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved279; // Byte offset 0x279, CSR Addr 0x5413c, Direction=N/A
+
+ uint8_t Reserved27A; // Byte offset 0x27a, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27B; // Byte offset 0x27b, CSR Addr 0x5413d, Direction=N/A
+
+ uint8_t Reserved27C; // Byte offset 0x27c, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27D; // Byte offset 0x27d, CSR Addr 0x5413e, Direction=N/A
+
+ uint8_t Reserved27E; // Byte offset 0x27e, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved27F; // Byte offset 0x27f, CSR Addr 0x5413f, Direction=N/A
+
+ uint8_t Reserved280; // Byte offset 0x280, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved281; // Byte offset 0x281, CSR Addr 0x54140, Direction=N/A
+
+ uint8_t Reserved282; // Byte offset 0x282, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved283; // Byte offset 0x283, CSR Addr 0x54141, Direction=N/A
+
+ uint8_t Reserved284; // Byte offset 0x284, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved285; // Byte offset 0x285, CSR Addr 0x54142, Direction=N/A
+
+ uint8_t Reserved286; // Byte offset 0x286, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved287; // Byte offset 0x287, CSR Addr 0x54143, Direction=N/A
+
+ uint8_t Reserved288; // Byte offset 0x288, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved289; // Byte offset 0x289, CSR Addr 0x54144, Direction=N/A
+
+ uint8_t Reserved28A; // Byte offset 0x28a, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28B; // Byte offset 0x28b, CSR Addr 0x54145, Direction=N/A
+
+ uint8_t Reserved28C; // Byte offset 0x28c, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28D; // Byte offset 0x28d, CSR Addr 0x54146, Direction=N/A
+
+ uint8_t Reserved28E; // Byte offset 0x28e, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved28F; // Byte offset 0x28f, CSR Addr 0x54147, Direction=N/A
+
+ uint8_t Reserved290; // Byte offset 0x290, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved291; // Byte offset 0x291, CSR Addr 0x54148, Direction=N/A
+
+ uint8_t Reserved292; // Byte offset 0x292, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved293; // Byte offset 0x293, CSR Addr 0x54149, Direction=N/A
+
+ uint8_t Reserved294; // Byte offset 0x294, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved295; // Byte offset 0x295, CSR Addr 0x5414a, Direction=N/A
+
+ uint8_t Reserved296; // Byte offset 0x296, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved297; // Byte offset 0x297, CSR Addr 0x5414b, Direction=N/A
+
+ uint8_t Reserved298; // Byte offset 0x298, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved299; // Byte offset 0x299, CSR Addr 0x5414c, Direction=N/A
+
+ uint8_t Reserved29A; // Byte offset 0x29a, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29B; // Byte offset 0x29b, CSR Addr 0x5414d, Direction=N/A
+
+ uint8_t Reserved29C; // Byte offset 0x29c, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29D; // Byte offset 0x29d, CSR Addr 0x5414e, Direction=N/A
+
+ uint8_t Reserved29E; // Byte offset 0x29e, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved29F; // Byte offset 0x29f, CSR Addr 0x5414f, Direction=N/A
+
+ uint8_t Reserved2A0; // Byte offset 0x2a0, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A1; // Byte offset 0x2a1, CSR Addr 0x54150, Direction=N/A
+
+ uint8_t Reserved2A2; // Byte offset 0x2a2, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A3; // Byte offset 0x2a3, CSR Addr 0x54151, Direction=N/A
+
+ uint8_t Reserved2A4; // Byte offset 0x2a4, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A5; // Byte offset 0x2a5, CSR Addr 0x54152, Direction=N/A
+
+ uint8_t Reserved2A6; // Byte offset 0x2a6, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A7; // Byte offset 0x2a7, CSR Addr 0x54153, Direction=N/A
+
+ uint8_t Reserved2A8; // Byte offset 0x2a8, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2A9; // Byte offset 0x2a9, CSR Addr 0x54154, Direction=N/A
+
+ uint8_t Reserved2AA; // Byte offset 0x2aa, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AB; // Byte offset 0x2ab, CSR Addr 0x54155, Direction=N/A
+
+ uint8_t Reserved2AC; // Byte offset 0x2ac, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AD; // Byte offset 0x2ad, CSR Addr 0x54156, Direction=N/A
+
+ uint8_t Reserved2AE; // Byte offset 0x2ae, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2AF; // Byte offset 0x2af, CSR Addr 0x54157, Direction=N/A
+
+ uint8_t Reserved2B0; // Byte offset 0x2b0, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B1; // Byte offset 0x2b1, CSR Addr 0x54158, Direction=N/A
+
+ uint8_t Reserved2B2; // Byte offset 0x2b2, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B3; // Byte offset 0x2b3, CSR Addr 0x54159, Direction=N/A
+
+ uint8_t Reserved2B4; // Byte offset 0x2b4, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B5; // Byte offset 0x2b5, CSR Addr 0x5415a, Direction=N/A
+
+ uint8_t Reserved2B6; // Byte offset 0x2b6, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B7; // Byte offset 0x2b7, CSR Addr 0x5415b, Direction=N/A
+
+ uint8_t Reserved2B8; // Byte offset 0x2b8, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2B9; // Byte offset 0x2b9, CSR Addr 0x5415c, Direction=N/A
+
+ uint8_t Reserved2BA; // Byte offset 0x2ba, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BB; // Byte offset 0x2bb, CSR Addr 0x5415d, Direction=N/A
+
+ uint8_t Reserved2BC; // Byte offset 0x2bc, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BD; // Byte offset 0x2bd, CSR Addr 0x5415e, Direction=N/A
+
+ uint8_t Reserved2BE; // Byte offset 0x2be, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2BF; // Byte offset 0x2bf, CSR Addr 0x5415f, Direction=N/A
+
+ uint8_t Reserved2C0; // Byte offset 0x2c0, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C1; // Byte offset 0x2c1, CSR Addr 0x54160, Direction=N/A
+
+ uint8_t Reserved2C2; // Byte offset 0x2c2, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C3; // Byte offset 0x2c3, CSR Addr 0x54161, Direction=N/A
+
+ uint8_t Reserved2C4; // Byte offset 0x2c4, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C5; // Byte offset 0x2c5, CSR Addr 0x54162, Direction=N/A
+
+ uint8_t Reserved2C6; // Byte offset 0x2c6, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C7; // Byte offset 0x2c7, CSR Addr 0x54163, Direction=N/A
+
+ uint8_t Reserved2C8; // Byte offset 0x2c8, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2C9; // Byte offset 0x2c9, CSR Addr 0x54164, Direction=N/A
+
+ uint8_t Reserved2CA; // Byte offset 0x2ca, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CB; // Byte offset 0x2cb, CSR Addr 0x54165, Direction=N/A
+
+ uint8_t Reserved2CC; // Byte offset 0x2cc, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CD; // Byte offset 0x2cd, CSR Addr 0x54166, Direction=N/A
+
+ uint8_t Reserved2CE; // Byte offset 0x2ce, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2CF; // Byte offset 0x2cf, CSR Addr 0x54167, Direction=N/A
+
+ uint8_t Reserved2D0; // Byte offset 0x2d0, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D1; // Byte offset 0x2d1, CSR Addr 0x54168, Direction=N/A
+
+ uint8_t Reserved2D2; // Byte offset 0x2d2, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D3; // Byte offset 0x2d3, CSR Addr 0x54169, Direction=N/A
+
+ uint8_t Reserved2D4; // Byte offset 0x2d4, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D5; // Byte offset 0x2d5, CSR Addr 0x5416a, Direction=N/A
+
+ uint8_t Reserved2D6; // Byte offset 0x2d6, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D7; // Byte offset 0x2d7, CSR Addr 0x5416b, Direction=N/A
+
+ uint8_t Reserved2D8; // Byte offset 0x2d8, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2D9; // Byte offset 0x2d9, CSR Addr 0x5416c, Direction=N/A
+
+ uint8_t Reserved2DA; // Byte offset 0x2da, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DB; // Byte offset 0x2db, CSR Addr 0x5416d, Direction=N/A
+
+ uint8_t Reserved2DC; // Byte offset 0x2dc, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DD; // Byte offset 0x2dd, CSR Addr 0x5416e, Direction=N/A
+
+ uint8_t Reserved2DE; // Byte offset 0x2de, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2DF; // Byte offset 0x2df, CSR Addr 0x5416f, Direction=N/A
+
+ uint8_t Reserved2E0; // Byte offset 0x2e0, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E1; // Byte offset 0x2e1, CSR Addr 0x54170, Direction=N/A
+
+ uint8_t Reserved2E2; // Byte offset 0x2e2, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E3; // Byte offset 0x2e3, CSR Addr 0x54171, Direction=N/A
+
+ uint8_t Reserved2E4; // Byte offset 0x2e4, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E5; // Byte offset 0x2e5, CSR Addr 0x54172, Direction=N/A
+
+ uint8_t Reserved2E6; // Byte offset 0x2e6, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E7; // Byte offset 0x2e7, CSR Addr 0x54173, Direction=N/A
+
+ uint8_t Reserved2E8; // Byte offset 0x2e8, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2E9; // Byte offset 0x2e9, CSR Addr 0x54174, Direction=N/A
+
+ uint8_t Reserved2EA; // Byte offset 0x2ea, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EB; // Byte offset 0x2eb, CSR Addr 0x54175, Direction=N/A
+
+ uint8_t Reserved2EC; // Byte offset 0x2ec, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2ED; // Byte offset 0x2ed, CSR Addr 0x54176, Direction=N/A
+
+ uint8_t Reserved2EE; // Byte offset 0x2ee, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2EF; // Byte offset 0x2ef, CSR Addr 0x54177, Direction=N/A
+
+ uint8_t Reserved2F0; // Byte offset 0x2f0, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F1; // Byte offset 0x2f1, CSR Addr 0x54178, Direction=N/A
+
+ uint8_t Reserved2F2; // Byte offset 0x2f2, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F3; // Byte offset 0x2f3, CSR Addr 0x54179, Direction=N/A
+
+ uint8_t Reserved2F4; // Byte offset 0x2f4, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F5; // Byte offset 0x2f5, CSR Addr 0x5417a, Direction=N/A
+
+ uint8_t Reserved2F6; // Byte offset 0x2f6, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F7; // Byte offset 0x2f7, CSR Addr 0x5417b, Direction=N/A
+
+ uint8_t Reserved2F8; // Byte offset 0x2f8, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2F9; // Byte offset 0x2f9, CSR Addr 0x5417c, Direction=N/A
+
+ uint8_t Reserved2FA; // Byte offset 0x2fa, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FB; // Byte offset 0x2fb, CSR Addr 0x5417d, Direction=N/A
+
+ uint8_t Reserved2FC; // Byte offset 0x2fc, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FD; // Byte offset 0x2fd, CSR Addr 0x5417e, Direction=N/A
+
+ uint8_t Reserved2FE; // Byte offset 0x2fe, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved2FF; // Byte offset 0x2ff, CSR Addr 0x5417f, Direction=N/A
+
+ uint8_t Reserved300; // Byte offset 0x300, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved301; // Byte offset 0x301, CSR Addr 0x54180, Direction=N/A
+
+ uint8_t Reserved302; // Byte offset 0x302, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved303; // Byte offset 0x303, CSR Addr 0x54181, Direction=N/A
+
+ uint8_t Reserved304; // Byte offset 0x304, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved305; // Byte offset 0x305, CSR Addr 0x54182, Direction=N/A
+
+ uint8_t Reserved306; // Byte offset 0x306, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved307; // Byte offset 0x307, CSR Addr 0x54183, Direction=N/A
+
+ uint8_t Reserved308; // Byte offset 0x308, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved309; // Byte offset 0x309, CSR Addr 0x54184, Direction=N/A
+
+ uint8_t Reserved30A; // Byte offset 0x30a, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30B; // Byte offset 0x30b, CSR Addr 0x54185, Direction=N/A
+
+ uint8_t Reserved30C; // Byte offset 0x30c, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30D; // Byte offset 0x30d, CSR Addr 0x54186, Direction=N/A
+
+ uint8_t Reserved30E; // Byte offset 0x30e, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved30F; // Byte offset 0x30f, CSR Addr 0x54187, Direction=N/A
+
+ uint8_t Reserved310; // Byte offset 0x310, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved311; // Byte offset 0x311, CSR Addr 0x54188, Direction=N/A
+
+ uint8_t Reserved312; // Byte offset 0x312, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved313; // Byte offset 0x313, CSR Addr 0x54189, Direction=N/A
+
+ uint8_t Reserved314; // Byte offset 0x314, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved315; // Byte offset 0x315, CSR Addr 0x5418a, Direction=N/A
+
+ uint8_t Reserved316; // Byte offset 0x316, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved317; // Byte offset 0x317, CSR Addr 0x5418b, Direction=N/A
+
+ uint8_t Reserved318; // Byte offset 0x318, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved319; // Byte offset 0x319, CSR Addr 0x5418c, Direction=N/A
+
+ uint8_t Reserved31A; // Byte offset 0x31a, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31B; // Byte offset 0x31b, CSR Addr 0x5418d, Direction=N/A
+
+ uint8_t Reserved31C; // Byte offset 0x31c, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31D; // Byte offset 0x31d, CSR Addr 0x5418e, Direction=N/A
+
+ uint8_t Reserved31E; // Byte offset 0x31e, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved31F; // Byte offset 0x31f, CSR Addr 0x5418f, Direction=N/A
+
+ uint8_t Reserved320; // Byte offset 0x320, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved321; // Byte offset 0x321, CSR Addr 0x54190, Direction=N/A
+
+ uint8_t Reserved322; // Byte offset 0x322, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved323; // Byte offset 0x323, CSR Addr 0x54191, Direction=N/A
+
+ uint8_t Reserved324; // Byte offset 0x324, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved325; // Byte offset 0x325, CSR Addr 0x54192, Direction=N/A
+
+ uint8_t Reserved326; // Byte offset 0x326, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved327; // Byte offset 0x327, CSR Addr 0x54193, Direction=N/A
+
+ uint8_t Reserved328; // Byte offset 0x328, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved329; // Byte offset 0x329, CSR Addr 0x54194, Direction=N/A
+
+ uint8_t Reserved32A; // Byte offset 0x32a, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32B; // Byte offset 0x32b, CSR Addr 0x54195, Direction=N/A
+
+ uint8_t Reserved32C; // Byte offset 0x32c, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32D; // Byte offset 0x32d, CSR Addr 0x54196, Direction=N/A
+
+ uint8_t Reserved32E; // Byte offset 0x32e, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved32F; // Byte offset 0x32f, CSR Addr 0x54197, Direction=N/A
+
+ uint8_t Reserved330; // Byte offset 0x330, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved331; // Byte offset 0x331, CSR Addr 0x54198, Direction=N/A
+
+ uint8_t Reserved332; // Byte offset 0x332, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved333; // Byte offset 0x333, CSR Addr 0x54199, Direction=N/A
+
+ uint8_t Reserved334; // Byte offset 0x334, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved335; // Byte offset 0x335, CSR Addr 0x5419a, Direction=N/A
+
+ uint8_t Reserved336; // Byte offset 0x336, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved337; // Byte offset 0x337, CSR Addr 0x5419b, Direction=N/A
+
+ uint8_t Reserved338; // Byte offset 0x338, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved339; // Byte offset 0x339, CSR Addr 0x5419c, Direction=N/A
+
+ uint8_t Reserved33A; // Byte offset 0x33a, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33B; // Byte offset 0x33b, CSR Addr 0x5419d, Direction=N/A
+
+ uint8_t Reserved33C; // Byte offset 0x33c, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33D; // Byte offset 0x33d, CSR Addr 0x5419e, Direction=N/A
+
+ uint8_t Reserved33E; // Byte offset 0x33e, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved33F; // Byte offset 0x33f, CSR Addr 0x5419f, Direction=N/A
+
+ uint8_t Reserved340; // Byte offset 0x340, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved341; // Byte offset 0x341, CSR Addr 0x541a0, Direction=N/A
+
+ uint8_t Reserved342; // Byte offset 0x342, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved343; // Byte offset 0x343, CSR Addr 0x541a1, Direction=N/A
+
+ uint8_t Reserved344; // Byte offset 0x344, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved345; // Byte offset 0x345, CSR Addr 0x541a2, Direction=N/A
+
+ uint8_t Reserved346; // Byte offset 0x346, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved347; // Byte offset 0x347, CSR Addr 0x541a3, Direction=N/A
+
+ uint8_t Reserved348; // Byte offset 0x348, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved349; // Byte offset 0x349, CSR Addr 0x541a4, Direction=N/A
+
+ uint8_t Reserved34A; // Byte offset 0x34a, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34B; // Byte offset 0x34b, CSR Addr 0x541a5, Direction=N/A
+
+ uint8_t Reserved34C; // Byte offset 0x34c, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34D; // Byte offset 0x34d, CSR Addr 0x541a6, Direction=N/A
+
+ uint8_t Reserved34E; // Byte offset 0x34e, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved34F; // Byte offset 0x34f, CSR Addr 0x541a7, Direction=N/A
+
+ uint8_t Reserved350; // Byte offset 0x350, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved351; // Byte offset 0x351, CSR Addr 0x541a8, Direction=N/A
+
+ uint8_t Reserved352; // Byte offset 0x352, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved353; // Byte offset 0x353, CSR Addr 0x541a9, Direction=N/A
+
+ uint8_t Reserved354; // Byte offset 0x354, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved355; // Byte offset 0x355, CSR Addr 0x541aa, Direction=N/A
+
+ uint8_t Reserved356; // Byte offset 0x356, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved357; // Byte offset 0x357, CSR Addr 0x541ab, Direction=N/A
+
+ uint8_t Reserved358; // Byte offset 0x358, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved359; // Byte offset 0x359, CSR Addr 0x541ac, Direction=N/A
+
+ uint8_t Reserved35A; // Byte offset 0x35a, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35B; // Byte offset 0x35b, CSR Addr 0x541ad, Direction=N/A
+
+ uint8_t Reserved35C; // Byte offset 0x35c, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35D; // Byte offset 0x35d, CSR Addr 0x541ae, Direction=N/A
+
+ uint8_t Reserved35E; // Byte offset 0x35e, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved35F; // Byte offset 0x35f, CSR Addr 0x541af, Direction=N/A
+
+ uint8_t Reserved360; // Byte offset 0x360, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved361; // Byte offset 0x361, CSR Addr 0x541b0, Direction=N/A
+
+ uint8_t Reserved362; // Byte offset 0x362, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved363; // Byte offset 0x363, CSR Addr 0x541b1, Direction=N/A
+
+ uint8_t Reserved364; // Byte offset 0x364, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved365; // Byte offset 0x365, CSR Addr 0x541b2, Direction=N/A
+
+ uint8_t Reserved366; // Byte offset 0x366, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved367; // Byte offset 0x367, CSR Addr 0x541b3, Direction=N/A
+
+ uint8_t Reserved368; // Byte offset 0x368, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved369; // Byte offset 0x369, CSR Addr 0x541b4, Direction=N/A
+
+ uint8_t Reserved36A; // Byte offset 0x36a, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36B; // Byte offset 0x36b, CSR Addr 0x541b5, Direction=N/A
+
+ uint8_t Reserved36C; // Byte offset 0x36c, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36D; // Byte offset 0x36d, CSR Addr 0x541b6, Direction=N/A
+
+ uint8_t Reserved36E; // Byte offset 0x36e, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved36F; // Byte offset 0x36f, CSR Addr 0x541b7, Direction=N/A
+
+ uint8_t Reserved370; // Byte offset 0x370, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved371; // Byte offset 0x371, CSR Addr 0x541b8, Direction=N/A
+
+ uint8_t Reserved372; // Byte offset 0x372, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved373; // Byte offset 0x373, CSR Addr 0x541b9, Direction=N/A
+
+ uint8_t Reserved374; // Byte offset 0x374, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved375; // Byte offset 0x375, CSR Addr 0x541ba, Direction=N/A
+
+ uint8_t Reserved376; // Byte offset 0x376, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved377; // Byte offset 0x377, CSR Addr 0x541bb, Direction=N/A
+
+ uint8_t Reserved378; // Byte offset 0x378, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved379; // Byte offset 0x379, CSR Addr 0x541bc, Direction=N/A
+
+ uint8_t Reserved37A; // Byte offset 0x37a, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37B; // Byte offset 0x37b, CSR Addr 0x541bd, Direction=N/A
+
+ uint8_t Reserved37C; // Byte offset 0x37c, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37D; // Byte offset 0x37d, CSR Addr 0x541be, Direction=N/A
+
+ uint8_t Reserved37E; // Byte offset 0x37e, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved37F; // Byte offset 0x37f, CSR Addr 0x541bf, Direction=N/A
+
+ uint8_t Reserved380; // Byte offset 0x380, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved381; // Byte offset 0x381, CSR Addr 0x541c0, Direction=N/A
+
+ uint8_t Reserved382; // Byte offset 0x382, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved383; // Byte offset 0x383, CSR Addr 0x541c1, Direction=N/A
+
+ uint8_t Reserved384; // Byte offset 0x384, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved385; // Byte offset 0x385, CSR Addr 0x541c2, Direction=N/A
+
+ uint8_t Reserved386; // Byte offset 0x386, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved387; // Byte offset 0x387, CSR Addr 0x541c3, Direction=N/A
+
+ uint8_t Reserved388; // Byte offset 0x388, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved389; // Byte offset 0x389, CSR Addr 0x541c4, Direction=N/A
+
+ uint8_t Reserved38A; // Byte offset 0x38a, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38B; // Byte offset 0x38b, CSR Addr 0x541c5, Direction=N/A
+
+ uint8_t Reserved38C; // Byte offset 0x38c, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38D; // Byte offset 0x38d, CSR Addr 0x541c6, Direction=N/A
+
+ uint8_t Reserved38E; // Byte offset 0x38e, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved38F; // Byte offset 0x38f, CSR Addr 0x541c7, Direction=N/A
+
+ uint8_t Reserved390; // Byte offset 0x390, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved391; // Byte offset 0x391, CSR Addr 0x541c8, Direction=N/A
+
+ uint8_t Reserved392; // Byte offset 0x392, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved393; // Byte offset 0x393, CSR Addr 0x541c9, Direction=N/A
+
+ uint8_t Reserved394; // Byte offset 0x394, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved395; // Byte offset 0x395, CSR Addr 0x541ca, Direction=N/A
+
+ uint8_t Reserved396; // Byte offset 0x396, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved397; // Byte offset 0x397, CSR Addr 0x541cb, Direction=N/A
+
+ uint8_t Reserved398; // Byte offset 0x398, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved399; // Byte offset 0x399, CSR Addr 0x541cc, Direction=N/A
+
+ uint8_t Reserved39A; // Byte offset 0x39a, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39B; // Byte offset 0x39b, CSR Addr 0x541cd, Direction=N/A
+
+ uint8_t Reserved39C; // Byte offset 0x39c, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39D; // Byte offset 0x39d, CSR Addr 0x541ce, Direction=N/A
+
+ uint8_t Reserved39E; // Byte offset 0x39e, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved39F; // Byte offset 0x39f, CSR Addr 0x541cf, Direction=N/A
+
+ uint8_t Reserved3A0; // Byte offset 0x3a0, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A1; // Byte offset 0x3a1, CSR Addr 0x541d0, Direction=N/A
+
+ uint8_t Reserved3A2; // Byte offset 0x3a2, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A3; // Byte offset 0x3a3, CSR Addr 0x541d1, Direction=N/A
+
+ uint8_t Reserved3A4; // Byte offset 0x3a4, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A5; // Byte offset 0x3a5, CSR Addr 0x541d2, Direction=N/A
+
+ uint8_t Reserved3A6; // Byte offset 0x3a6, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A7; // Byte offset 0x3a7, CSR Addr 0x541d3, Direction=N/A
+
+ uint8_t Reserved3A8; // Byte offset 0x3a8, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3A9; // Byte offset 0x3a9, CSR Addr 0x541d4, Direction=N/A
+
+ uint8_t Reserved3AA; // Byte offset 0x3aa, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AB; // Byte offset 0x3ab, CSR Addr 0x541d5, Direction=N/A
+
+ uint8_t Reserved3AC; // Byte offset 0x3ac, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AD; // Byte offset 0x3ad, CSR Addr 0x541d6, Direction=N/A
+
+ uint8_t Reserved3AE; // Byte offset 0x3ae, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3AF; // Byte offset 0x3af, CSR Addr 0x541d7, Direction=N/A
+
+ uint8_t Reserved3B0; // Byte offset 0x3b0, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B1; // Byte offset 0x3b1, CSR Addr 0x541d8, Direction=N/A
+
+ uint8_t Reserved3B2; // Byte offset 0x3b2, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B3; // Byte offset 0x3b3, CSR Addr 0x541d9, Direction=N/A
+
+ uint8_t Reserved3B4; // Byte offset 0x3b4, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B5; // Byte offset 0x3b5, CSR Addr 0x541da, Direction=N/A
+
+ uint8_t Reserved3B6; // Byte offset 0x3b6, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B7; // Byte offset 0x3b7, CSR Addr 0x541db, Direction=N/A
+
+ uint8_t Reserved3B8; // Byte offset 0x3b8, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3B9; // Byte offset 0x3b9, CSR Addr 0x541dc, Direction=N/A
+
+ uint8_t Reserved3BA; // Byte offset 0x3ba, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BB; // Byte offset 0x3bb, CSR Addr 0x541dd, Direction=N/A
+
+ uint8_t Reserved3BC; // Byte offset 0x3bc, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BD; // Byte offset 0x3bd, CSR Addr 0x541de, Direction=N/A
+
+ uint8_t Reserved3BE; // Byte offset 0x3be, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3BF; // Byte offset 0x3bf, CSR Addr 0x541df, Direction=N/A
+
+ uint8_t Reserved3C0; // Byte offset 0x3c0, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C1; // Byte offset 0x3c1, CSR Addr 0x541e0, Direction=N/A
+
+ uint8_t Reserved3C2; // Byte offset 0x3c2, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C3; // Byte offset 0x3c3, CSR Addr 0x541e1, Direction=N/A
+
+ uint8_t Reserved3C4; // Byte offset 0x3c4, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C5; // Byte offset 0x3c5, CSR Addr 0x541e2, Direction=N/A
+
+ uint8_t Reserved3C6; // Byte offset 0x3c6, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C7; // Byte offset 0x3c7, CSR Addr 0x541e3, Direction=N/A
+
+ uint8_t Reserved3C8; // Byte offset 0x3c8, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3C9; // Byte offset 0x3c9, CSR Addr 0x541e4, Direction=N/A
+
+ uint8_t Reserved3CA; // Byte offset 0x3ca, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CB; // Byte offset 0x3cb, CSR Addr 0x541e5, Direction=N/A
+
+ uint8_t Reserved3CC; // Byte offset 0x3cc, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CD; // Byte offset 0x3cd, CSR Addr 0x541e6, Direction=N/A
+
+ uint8_t Reserved3CE; // Byte offset 0x3ce, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3CF; // Byte offset 0x3cf, CSR Addr 0x541e7, Direction=N/A
+
+ uint8_t Reserved3D0; // Byte offset 0x3d0, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D1; // Byte offset 0x3d1, CSR Addr 0x541e8, Direction=N/A
+
+ uint8_t Reserved3D2; // Byte offset 0x3d2, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D3; // Byte offset 0x3d3, CSR Addr 0x541e9, Direction=N/A
+
+ uint8_t Reserved3D4; // Byte offset 0x3d4, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D5; // Byte offset 0x3d5, CSR Addr 0x541ea, Direction=N/A
+
+ uint8_t Reserved3D6; // Byte offset 0x3d6, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D7; // Byte offset 0x3d7, CSR Addr 0x541eb, Direction=N/A
+
+ uint8_t Reserved3D8; // Byte offset 0x3d8, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3D9; // Byte offset 0x3d9, CSR Addr 0x541ec, Direction=N/A
+
+ uint8_t Reserved3DA; // Byte offset 0x3da, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DB; // Byte offset 0x3db, CSR Addr 0x541ed, Direction=N/A
+
+ uint8_t Reserved3DC; // Byte offset 0x3dc, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DD; // Byte offset 0x3dd, CSR Addr 0x541ee, Direction=N/A
+
+ uint8_t Reserved3DE; // Byte offset 0x3de, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3DF; // Byte offset 0x3df, CSR Addr 0x541ef, Direction=N/A
+
+ uint8_t Reserved3E0; // Byte offset 0x3e0, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E1; // Byte offset 0x3e1, CSR Addr 0x541f0, Direction=N/A
+
+ uint8_t Reserved3E2; // Byte offset 0x3e2, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E3; // Byte offset 0x3e3, CSR Addr 0x541f1, Direction=N/A
+
+ uint8_t Reserved3E4; // Byte offset 0x3e4, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E5; // Byte offset 0x3e5, CSR Addr 0x541f2, Direction=N/A
+
+ uint8_t Reserved3E6; // Byte offset 0x3e6, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E7; // Byte offset 0x3e7, CSR Addr 0x541f3, Direction=N/A
+
+ uint8_t Reserved3E8; // Byte offset 0x3e8, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3E9; // Byte offset 0x3e9, CSR Addr 0x541f4, Direction=N/A
+
+ uint8_t Reserved3EA; // Byte offset 0x3ea, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EB; // Byte offset 0x3eb, CSR Addr 0x541f5, Direction=N/A
+
+ uint8_t Reserved3EC; // Byte offset 0x3ec, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3ED; // Byte offset 0x3ed, CSR Addr 0x541f6, Direction=N/A
+
+ uint8_t Reserved3EE; // Byte offset 0x3ee, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3EF; // Byte offset 0x3ef, CSR Addr 0x541f7, Direction=N/A
+
+ uint8_t Reserved3F0; // Byte offset 0x3f0, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F1; // Byte offset 0x3f1, CSR Addr 0x541f8, Direction=N/A
+
+ uint8_t Reserved3F2; // Byte offset 0x3f2, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F3; // Byte offset 0x3f3, CSR Addr 0x541f9, Direction=N/A
+
+ uint8_t Reserved3F4; // Byte offset 0x3f4, CSR Addr 0x541fa, Direction=N/A
+
+ uint8_t Reserved3F5; // Byte offset 0x3f5, CSR Addr 0x541fa, Direction=N/A
+
+ uint16_t ALT_CAS_L; // Byte offset 0x3f6, CSR Addr 0x541fb, Direction=in
+ // This field must be populated if RdDBI is enabled (applicable when MR5[A12] == 1).
+ // RdDBI is dynamically disabled in certain training steps,
+ // and so the [RdDBI disabled] CAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_CAS_L[0] == 0: use value in MR0
+ // ALT_CAS_L[0] == 1: use value in ALT_CAS_L, i.e., MR0{A[12],A[6],A[5],A[4],A[2]} = ALT_CAS_L[12,6,5,4,2]
+ // Other bits are ignored
+ uint8_t ALT_WCAS_L; // Byte offset 0x3f8, CSR Addr 0x541fc, Direction=In
+ // This field must be populated if 2tCK write preambles are enabled (applicable when MR4[A12] == 1).
+ // 2tCK write prambles are dynamically disabled in certain training steps,
+ // and so the [1tCK write preamble] WCAS Latency must be provided in this field.
+ // The required encoding is as follows:
+ // ALT_WCAS_L[0] == 0: use value in MR2
+ // ALT_WCAS_L[0] == 1: use value in ALT_WCAS_L, i.e., MR2{A[5],A[4],A[3]} = ALT_WCAS_L[5,4,3]
+ // Other bits are ignored
+ uint8_t D4Misc; // Byte offset 0x3f9, CSR Addr 0x541fc, Direction=In
+ // Contains various options for training DDR4 Devices.
+ //
+ // Bit fields:
+ //
+ // D4Misc[7:1] RFU, must be zero
+ //
+ // D4Misc[0] = protect memory reset
+ // 0x1 = dfi_reset_n cannot control BP_MEMRESERT_L to devices after training.
+ // 0x0 = dfi_resert_n can control BP_MEMRESERT_L to devices after training
+} __attribute__ ((packed)) PMU_SMB_DDR4U_2D_t;
diff --git a/arch/arm/include/asm/arch-t7/mnPmuSramMsgBlock_lpddr3.h b/arch/arm/include/asm/arch-t7/mnPmuSramMsgBlock_lpddr3.h
new file mode 100644
index 0000000..6850d06
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/mnPmuSramMsgBlock_lpddr3.h
@@ -0,0 +1,434 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief LPDDR3_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_LPDDR3_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:5] RFU, must be zero
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] RFU, must be zero
+ //
+ // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[7-6] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.75*VDDQ, set this field to 0x60.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t Reserved0D; // Byte offset 0x0d, CSR Addr 0x54006, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = RunWrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[10] = RFU, must be zero
+ // SequenceCtrl[11] = RFU, must be zero
+ // SequenceCtrl[12] = Run LPCA - CA Training
+ // SequenceCtrl[13] = RFU, must be zero
+ // SequenceCtrl[14] = RFU, must be zero
+ // SequenceCtrl[15] = RFU, must be zero
+ //
+ uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t DFIMRLMargin; // Byte offset 0x14, CSR Addr 0x5400a, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ //
+ // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system.
+ uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t UseBroadcastMR; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired.
+ //
+ // 0x0 = Use MR<0:17>_A0 for rank 0 channel A
+ // Use MR<0:17>_B0 for rank 0 channel B
+ // Use MR<0:17>_A1 for rank 1 channel A
+ // Use MR<0:17>_B1 for rank 1 channel B
+ //
+ // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks
+ //
+ // This should be set to 1 for all systems.
+ //
+ // Note: If setting this to 0, only mode register settings related to DRAM partial array self-refresh may be different between the ranks and channels. All other mode register settings must be the same for all ranks and channels.
+ uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t LogToPhyByteMap0; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // Physical Byte associated with Channel A logical Byte 0, depending on LogToPhyByteMap0[7] value:
+ // LogToPhyByteMap0[7]==0: Logical Byte 0 map on Physical Byte 0
+ // LogToPhyByteMap0[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap0[6:0]
+ uint8_t LogToPhyByteMap1; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In
+ // Physical Byte associated with Channel A logical Byte 1, depending on LogToPhyByteMap1[7] value:
+ // LogToPhyByteMap1[7]==0: Logical Byte 1 map on Physical Byte 1
+ // LogToPhyByteMap1[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap1[6:0]
+ uint8_t LogToPhyByteMap2; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Physical Byte associated with Channel A logical Byte 2, depending on LogToPhyByteMap2[7] value:
+ // LogToPhyByteMap2[7]==0: Logical Byte 2 map on Physical Byte 2
+ // LogToPhyByteMap2[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap2[6:0]
+ uint8_t LogToPhyByteMap3; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // Physical Byte associated with Channel A logical Byte 3, depending on LogToPhyByteMap3[7] value:
+ // LogToPhyByteMap3[7]==0: Logical Byte 3 map on Physical Byte 3
+ // LogToPhyByteMap3[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap3[6:0]
+ uint8_t LogToPhyByteMap4; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // Physical Byte associated with Channel B logical Byte 0, depending on LogToPhyByteMap4[7] value:
+ // LogToPhyByteMap4[7]==0: Logical Byte 0 map on Physical Byte 4
+ // LogToPhyByteMap4[7]==1: Logical Byte 0 map on Physical Byte LogToPhyByteMap4[6:0]
+ uint8_t LogToPhyByteMap5; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In
+ // Physical Byte associated with Channel B logical Byte 1, depending on LogToPhyByteMap5[7] value:
+ // LogToPhyByteMap5[7]==0: Logical Byte 1 map on Physical Byte 5
+ // LogToPhyByteMap5[7]==1: Logical Byte 1 map on Physical Byte LogToPhyByteMap5[6:0]
+ uint8_t LogToPhyByteMap6; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Physical Byte associated with Channel B logical Byte 2, depending on LogToPhyByteMap6[7] value:
+ // LogToPhyByteMap6[7]==0: Logical Byte 2 map on Physical Byte 6
+ // LogToPhyByteMap6[7]==1: Logical Byte 2 map on Physical Byte LogToPhyByteMap6[6:0]
+ uint8_t LogToPhyByteMap7; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In
+ // Physical Byte associated with Channel B logical Byte 3, depending on LogToPhyByteMap7[7] value:
+ // LogToPhyByteMap7[7]==0: Logical Byte 3 map on Physical Byte 7
+ // LogToPhyByteMap7[7]==1: Logical Byte 3 map on Physical Byte LogToPhyByteMap7[6:0]
+ uint8_t LogToPhyByteMap8; // Byte offset 0x20, CSR Addr 0x54010, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t LogToPhyByteMap9; // Byte offset 0x21, CSR Addr 0x54010, Direction=In
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t EnabledDQsChA; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Total number of DQ bits enabled in PHY Channel A
+ uint8_t CsPresentChA; // Byte offset 0x23, CSR Addr 0x54011, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel A.
+ //
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChA_RR_1_0; // Byte offset 0x24, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RR_0_1; // Byte offset 0x25, CSR Addr 0x54012, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_1; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_0; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_1_0; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_0_1; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved30; // Byte offset 0x30, CSR Addr 0x54018, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_A0; // Byte offset 0x31, CSR Addr 0x54018, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0}
+ uint8_t MR2_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0}
+ uint8_t MR3_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0}
+ uint8_t Reserved34; // Byte offset 0x34, CSR Addr 0x5401a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0}
+ uint8_t MR16_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0}
+ uint8_t MR17_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0}
+ uint8_t Reserved38; // Byte offset 0x38, CSR Addr 0x5401c, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_A1; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In
+ // Must be programmed the same as MR1_A0
+ uint8_t MR2_A1; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
+ // Must be programmed the same as MR2_A0
+ uint8_t MR3_A1; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
+ // Must be programmed the same as MR3_A0
+ uint8_t Reserved3C; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_A1; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
+ // Must be programmed the same as MR11_A0
+ uint8_t MR16_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1}
+ uint8_t MR17_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1}
+ uint8_t Reserved40; // Byte offset 0x40, CSR Addr 0x54020, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved41; // Byte offset 0x41, CSR Addr 0x54020, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved42; // Byte offset 0x42, CSR Addr 0x54021, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved43; // Byte offset 0x43, CSR Addr 0x54021, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved44; // Byte offset 0x44, CSR Addr 0x54022, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved45; // Byte offset 0x45, CSR Addr 0x54022, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved46; // Byte offset 0x46, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved47; // Byte offset 0x47, CSR Addr 0x54023, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t EnabledDQsChB; // Byte offset 0x48, CSR Addr 0x54024, Direction=In
+ // Total number of DQ bits enabled in PHY Channel B
+ uint8_t CsPresentChB; // Byte offset 0x49, CSR Addr 0x54024, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel B.
+ //
+ // 0x0 = No chip selects are populated with DRAM
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChB_RR_1_0; // Byte offset 0x4a, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RR_0_1; // Byte offset 0x4b, CSR Addr 0x54025, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_1; // Byte offset 0x4c, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs01 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_1; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_1; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_0; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_1_0; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_0_1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_B0; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In
+ // Must be programmed the same as MR1_A0
+ uint8_t MR2_B0; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In
+ // Must be programmed the same as MR2_A0
+ uint8_t MR3_B0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=In
+ // Must be programmed the same as MR3_A0
+ uint8_t Reserved5A; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_B0; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=In
+ // Must be programmed the same as MR11_A0
+ uint8_t MR16_B0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0}
+ uint8_t MR17_B0; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0}
+ uint8_t Reserved5E; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR1_B1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=In
+ // Must be programmed the same as MR1_A0
+ uint8_t MR2_B1; // Byte offset 0x60, CSR Addr 0x54030, Direction=In
+ // Must be programmed the same as MR2_A0
+ uint8_t MR3_B1; // Byte offset 0x61, CSR Addr 0x54030, Direction=In
+ // Must be programmed the same as MR3_A0
+ uint8_t Reserved62; // Byte offset 0x62, CSR Addr 0x54031, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t MR11_B1; // Byte offset 0x63, CSR Addr 0x54031, Direction=In
+ // Must be programmed the same as MR11_A0
+ uint8_t MR16_B1; // Byte offset 0x64, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1}
+ uint8_t MR17_B1; // Byte offset 0x65, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1}
+ uint8_t Reserved66; // Byte offset 0x66, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved67; // Byte offset 0x67, CSR Addr 0x54033, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved68; // Byte offset 0x68, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved69; // Byte offset 0x69, CSR Addr 0x54034, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6A; // Byte offset 0x6a, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6B; // Byte offset 0x6b, CSR Addr 0x54035, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6C; // Byte offset 0x6c, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved6D; // Byte offset 0x6d, CSR Addr 0x54036, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint16_t PhyConfigOverride; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t Reserved70; // Byte offset 0x70, CSR Addr 0x54038, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+} __attribute__ ((packed)) PMU_SMB_LPDDR3_1D_t;
diff --git a/arch/arm/include/asm/arch-t7/mnPmuSramMsgBlock_lpddr4.h b/arch/arm/include/asm/arch-t7/mnPmuSramMsgBlock_lpddr4.h
new file mode 100644
index 0000000..d194621
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/mnPmuSramMsgBlock_lpddr4.h
@@ -0,0 +1,557 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief LPDDR4_1D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_LPDDR4_1D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Quick Rd2D during 1D Training
+ // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] Disable Boot Clock
+ // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended)
+ // 0x0 = Use Boot Frequency Clock
+ //
+ // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[7-6] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.25*VDDQ, set this field to 0x20.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Lp4 specific options for training.
+ //
+ // Bit fields:
+ //
+ // Lp4Misc[0] Enable dfi_reset_n
+ //
+ // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training.
+ // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin.
+ //
+ // 0x1 = Enables dfi_reset_n to control memreset after training.
+ // PHY Internal registers control memreset during training only.
+ // To ensure that no glitches occur on BP_MEMRESET at the end of training,
+ // The MC must drive dfi_reset_n=1'b1 _prior to starting training_
+ //
+ // Lp4Misc[7-1] RFU, must be zero
+ uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D.
+ //
+ // Reserved0E[0:3]: bitTimeControl
+ // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point.
+ // 0 = 288 bits per point (legacy behavior)
+ // 1 = 576 bits per point
+ // 2 = 1.125 kilobits per point
+ // …
+ // 15 = 9 megabits per point
+ //
+ // Reserved0E[4]: Exhaustive2D
+ // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior)
+ // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point.
+ //
+ // Reserved0E[5:7]: RFU, must be 0
+ uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = Run WrLvl - Write leveling
+ // SequenceCtrl[2] = Run RxEn - Read gate training
+ // SequenceCtrl[3] = Run RdDQS1D - 1d read dqs training
+ // SequenceCtrl[4] = Run WrDQ1D - 1d write dq training
+ // SequenceCtrl[5] = RFU, must be zero
+ // SequenceCtrl[6] = RFU, must be zero
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = Run RdDeskew - Per lane read dq deskew training
+ // SequenceCtrl[9] = Run MxRdLat - Max read latency training
+ // SequenceCtrl[11-10] = RFU, must be zero
+ // SequenceCtrl[12] = Run LPCA - CA Training
+ // SequenceCtrl[15-13] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ //
+ // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system.
+ uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired.
+ //
+ // 0x0 = Use MR<0:17>_A0 for rank 0 channel A
+ // Use MR<0:17>_B0 for rank 0 channel B
+ // Use MR<0:17>_A1 for rank 1 channel A
+ // Use MR<0:17>_B1 for rank 1 channel B
+ //
+ // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks
+ //
+ // It is recommended in most LPDDR4 system configurations to set this to 1.
+ //
+ // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels.
+ //
+ uint8_t Lp4Quickboot; // Byte offset 0x19, CSR Addr 0x5400c, Direction=In
+ // Enable Quickboot.
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D stages: Rd2D, Wr2D
+ //
+ // Reserved1A[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1A[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR14
+ // 2 = limit to +/-4 %VDDQ from MR14
+ // …
+ // 15 = limit to +/-30% VDDQ from MR14
+ uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // CA training option bit field
+ // [0] CA VREF Training
+ // 1 = Enable CA VREF Training
+ // 0 = Disable CA VREF Training
+ // [1-7] RFU must be zero
+ uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // X8 mode configuration:
+ // 0x0 = x16 configuration for all devices
+ // 0xF = x8 configuration for all devices
+ // All other values are RFU
+ uint8_t Reserved1D; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1E; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=N/A
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+ uint8_t Reserved1F; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=N/A
+
+
+
+ uint8_t Reserved20; // Byte offset 0x20, CSR Addr 0x54010, Direction=N/A
+
+ uint8_t Reserved21; // Byte offset 0x21, CSR Addr 0x54010, Direction=N/A
+
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Total number of DQ bits enabled in PHY Channel A
+ uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel A.
+ //
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0}
+ uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0}
+ uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0}
+ uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0}
+ uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0}
+ uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0}
+ uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0}
+ uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0}
+ uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0}
+ uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0}
+ uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0}
+ uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0}
+ uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1}
+ uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1}
+ uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1}
+ uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1}
+ uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1}
+ uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1}
+ uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1}
+ uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1}
+ uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1}
+ uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1}
+ uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1}
+ uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1}
+ uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In
+ // Terminating Rank for CA bus on Channel A
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A
+
+ uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A
+
+ uint8_t Reserved4D; // Byte offset 0x4d, CSR Addr 0x54026, Direction=N/A
+
+ uint8_t Reserved4E; // Byte offset 0x4e, CSR Addr 0x54027, Direction=N/A
+
+ uint8_t Reserved4F; // Byte offset 0x4f, CSR Addr 0x54027, Direction=N/A
+
+ uint8_t Reserved50; // Byte offset 0x50, CSR Addr 0x54028, Direction=N/A
+
+ uint8_t Reserved51; // Byte offset 0x51, CSR Addr 0x54028, Direction=N/A
+
+ uint8_t Reserved52; // Byte offset 0x52, CSR Addr 0x54029, Direction=N/A
+
+ uint8_t Reserved53; // Byte offset 0x53, CSR Addr 0x54029, Direction=N/A
+
+ uint8_t Reserved54; // Byte offset 0x54, CSR Addr 0x5402a, Direction=N/A
+
+ uint8_t Reserved55; // Byte offset 0x55, CSR Addr 0x5402a, Direction=N/A
+
+ uint8_t Reserved56; // Byte offset 0x56, CSR Addr 0x5402b, Direction=N/A
+
+ uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In
+ // Total number of DQ bits enabled in PHY Channel B
+ uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel B.
+ //
+ // 0x0 = No chip selects are populated with DRAM
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs01 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0}
+ uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0}
+ uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0}
+ uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0}
+ uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0}
+ uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0}
+ uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0}
+ uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0}
+ uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0}
+ uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0}
+ uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0}
+ uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0}
+ uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1}
+ uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1}
+ uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1}
+ uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1}
+ uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1}
+ uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1}
+ uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1}
+ uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1}
+ uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1}
+ uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1}
+ uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1}
+ uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1}
+ uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In
+ // Terminating Rank for CA bus on Channel B
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t Reserved80; // Byte offset 0x80, CSR Addr 0x54040, Direction=N/A
+
+ uint8_t Reserved81; // Byte offset 0x81, CSR Addr 0x54040, Direction=N/A
+
+ uint8_t Reserved82; // Byte offset 0x82, CSR Addr 0x54041, Direction=N/A
+
+ uint8_t Reserved83; // Byte offset 0x83, CSR Addr 0x54041, Direction=N/A
+
+ uint8_t Reserved84; // Byte offset 0x84, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved85; // Byte offset 0x85, CSR Addr 0x54042, Direction=N/A
+
+ uint8_t Reserved86; // Byte offset 0x86, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved87; // Byte offset 0x87, CSR Addr 0x54043, Direction=N/A
+
+ uint8_t Reserved88; // Byte offset 0x88, CSR Addr 0x54044, Direction=N/A
+
+ uint8_t Reserved89; // Byte offset 0x89, CSR Addr 0x54044, Direction=N/A
+
+} __attribute__ ((packed)) PMU_SMB_LPDDR4_1D_t;
diff --git a/arch/arm/include/asm/arch-t7/mnPmuSramMsgBlock_lpddr4_2d.h b/arch/arm/include/asm/arch-t7/mnPmuSramMsgBlock_lpddr4_2d.h
new file mode 100644
index 0000000..c6ab3d3
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/mnPmuSramMsgBlock_lpddr4_2d.h
@@ -0,0 +1,557 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/** \brief LPDDR4_2D training firmware message block structure
+ *
+ * Please refer to the Training Firmware App Note for futher information about
+ * the usage for Message Block.
+ */
+typedef struct _PMU_SMB_LPDDR4_2D_t {
+ uint8_t Reserved00; // Byte offset 0x00, CSR Addr 0x54000, Direction=In
+ // Reserved00[0:4] RFU, must be zero
+ //
+ // Reserved00[5] = Quick Rd2D during 1D Training
+ // 0x1 = Read Deskew will begin by enabling and quickly training the phy’s per-lane reference voltages. Training the vrefDACs CSRs will increase the maximum 1D training time by around half a millisecond, but will improve 1D training accuracy on systems with significant voltage-offsets between lane read eyes.
+ // 0X0 = Read Deskew will assume the messageblock’s phyVref setting is optimal for all lanes.
+ //
+ // Reserved00[6] = Enable High Effort WrDQ1D
+ // 0x1 = WrDQ1D will conditionally retry training at several extra RxClkDly Timings. This will increase the maximum 1D training time by up to 4 extra iterations of WrDQ1D. This is only required in systems that suffer from very large, asymmetric eye-collapse when receiving PRBS patterns.
+ // 0x0 = WrDQ1D assume rxClkDly values found by SI Friendly RdDqs1D will work for receiving PRBS patterns
+ //
+ // Reserved00[7] = Optimize for the special hard macros in TSMC28.
+ // 0x1 = set if the phy being trained was manufactured in any TSMC28 process node.
+ // 0x0 = otherwise, when not training a TSMC28 phy, leave this field as 0.
+ uint8_t MsgMisc; // Byte offset 0x01, CSR Addr 0x54000, Direction=In
+ // Contains various global options for training.
+ //
+ // Bit fields:
+ //
+ // MsgMisc[0] MTESTEnable
+ // 0x1 = Pulse primary digital test output bump at the end of each major training stage. This enables observation of training stage completion by observing the digital test output.
+ // 0x0 = Do not pulse primary digital test output bump
+ //
+ // MsgMisc[1] SimulationOnlyReset
+ // 0x1 = Verilog only simulation option to shorten duration of DRAM reset pulse length to 1ns.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use reset pulse length specifed by JEDEC standard
+ //
+ // MsgMisc[2] SimulationOnlyTraining
+ // 0x1 = Verilog only simulation option to shorten the duration of the training steps by performing fewer iterations.
+ // Must never be set to 1 in silicon.
+ // 0x0 = Use standard training duration.
+ //
+ // MsgMisc[3] Disable Boot Clock
+ // 0x1 = Disable boot frequency clock when initializing DRAM. (not recommended)
+ // 0x0 = Use Boot Frequency Clock
+ //
+ // MsgMisc[4] Suppress streaming messages, including assertions, regardless of HdtCtrl setting.
+ // Stage Completion messages, as well as training completion and error messages are
+ // Still sent depending on HdtCtrl setting.
+ //
+ // MsgMisc[5] PerByteMaxRdLat
+ // 0x1 = Each DBYTE will return dfi_rddata_valid at the lowest possible latency. This may result in unaligned data between bytes to be returned to the DFI.
+ // 0x0 = Every DBYTE will return dfi_rddata_valid simultaneously. This will ensure that data bytes will return aligned accesses to the DFI.
+ //
+ // MsgMisc[7-6] RFU, must be zero
+ //
+ // Notes:
+ //
+ // - SimulationOnlyReset and SimulationOnlyTraining can be used to speed up simulation run times, and must never be used in real silicon. Some VIPs may have checks on DRAM reset parameters that may need to be disabled when using SimulationOnlyReset.
+ uint16_t PmuRevision; // Byte offset 0x02, CSR Addr 0x54001, Direction=Out
+ // PMU firmware revision ID
+ // After training is run, this address will contain the revision ID of the firmware
+ uint8_t Pstate; // Byte offset 0x04, CSR Addr 0x54002, Direction=In
+ // Must be set to the target Pstate to be trained
+ // 0x0 = Pstate 0
+ // 0x1 = Pstate 1
+ // 0x2 = Pstate 2
+ // 0x3 = Pstate 3
+ // All other encodings are reserved
+ uint8_t PllBypassEn; // Byte offset 0x05, CSR Addr 0x54002, Direction=In
+ // Set according to whether target Pstate uses PHY PLL bypass
+ // 0x0 = PHY PLL is enabled for target Pstate
+ // 0x1 = PHY PLL is bypassed for target Pstate
+ uint16_t DRAMFreq; // Byte offset 0x06, CSR Addr 0x54003, Direction=In
+ // DDR data rate for the target Pstate in units of MT/s.
+ // For example enter 0x0640 for DDR1600.
+ uint8_t DfiFreqRatio; // Byte offset 0x08, CSR Addr 0x54004, Direction=In
+ // Frequency ratio betwen DfiCtlClk and SDRAM memclk.
+ // 0x1 = 1:1
+ // 0x2 = 1:2
+ // 0x4 = 1:4
+ uint8_t BPZNResVal ; // Byte offset 0x09, CSR Addr 0x54004, Direction=In
+ // Must be programmed to match the precision resistor connected to Phy BP_ZN
+ // 0x00 = Do not program. Use current CSR value.
+ // 0xf0 = 240 Ohm (recommended value)
+ // 0x78 = 120 Ohm
+ // 0x28 = 40 Ohm
+ // All other values are reserved.
+ //
+ uint8_t PhyOdtImpedance; // Byte offset 0x0a, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the termination impedance in ohms used by PHY during reads.
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal termination impedance values.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyDrvImpedance; // Byte offset 0x0b, CSR Addr 0x54005, Direction=In
+ // Must be programmed to the driver impedance in ohms used by PHY during writes for all DBYTE drivers (DQ/DM/DBI/DQS).
+ //
+ // 0x0 = Firmware skips programming (must be manually programmed by user prior to training start)
+ //
+ // See PHY databook for legal R_on driver impedance values.
+ //
+ // For digital simulation, any value can be used that is not Hi-Z. For silicon, the users must determine the correct value through SI simulation or other methods.
+ uint8_t PhyVref; // Byte offset 0x0c, CSR Addr 0x54006, Direction=In
+ // Must be programmed with the Vref level to be used by the PHY during reads
+ //
+ // The units of this field are a percentage of VDDQ according to the following equation:
+ //
+ // Receiver Vref = VDDQ*PhyVref[6:0]/128
+ //
+ // For example to set Vref at 0.25*VDDQ, set this field to 0x20.
+ //
+ // For digital simulation, any legal value can be used. For silicon, the users must calculate the analytical Vref by using the impedances, terminations, and series resistance present in the system.
+ uint8_t Lp4Misc; // Byte offset 0x0d, CSR Addr 0x54006, Direction=In
+ // Lp4 specific options for training.
+ //
+ // Bit fields:
+ //
+ // Lp4Misc[0] Enable dfi_reset_n
+ //
+ // 0x0 = (Recommended) PHY internal registers control memreset during training, and also after training.
+ // dfi_reset_n cannot control the PHY BP_MEMRESET_L pin.
+ //
+ // 0x1 = Enables dfi_reset_n to control memreset after training.
+ // PHY Internal registers control memreset during training only.
+ // To ensure that no glitches occur on BP_MEMRESET at the end of training,
+ // The MC must drive dfi_reset_n=1'b1 _prior to starting training_
+ //
+ // Lp4Misc[7-1] RFU, must be zero
+ uint8_t Reserved0E; // Byte offset 0x0e, CSR Addr 0x54007, Direction=In
+ // Bit Field for enabling optional 2D training features that impact both Rx2D and Tx2D.
+ //
+ // Reserved0E[0:3]: bitTimeControl
+ // Input for increasing the number of data-comparisons 2D runs per (delay,voltage) point. Every time this input increases by 1, the number of 2D data comparisons is doubled. The 2D run time will increase proportionally to the number of bit times requested per point.
+ // 0 = 288 bits per point (legacy behavior)
+ // 1 = 576 bits per point
+ // 2 = 1.125 kilobits per point
+ // …
+ // 15 = 9 megabits per point
+ //
+ // Reserved0E[4]: Exhaustive2D
+ // 0 = 2D’s optimization assumes the optimal trained point is near the 1D trained point (legacy behavior)
+ // 1 = 2D’s optimization searches the entire passing region at the cost of run time. Recommended for optimal results any time the optimal trained point is expected to be near the edges of the eyes instead of near the 1D trained point.
+ //
+ // Reserved0E[5:7]: RFU, must be 0
+ uint8_t CsTestFail; // Byte offset 0x0f, CSR Addr 0x54007, Direction=Out
+ // This field will be set if training fails on any rank.
+ // 0x0 = No failures
+ // non-zero = one or more ranks failed training
+ uint16_t SequenceCtrl; // Byte offset 0x10, CSR Addr 0x54008, Direction=In
+ // Controls the training steps to be run. Each bit corresponds to a training step.
+ //
+ // If the bit is set to 1, the training step will run.
+ // If the bit is set to 0, the training step will be skipped.
+ //
+ // Training step to bit mapping:
+ // SequenceCtrl[0] = Run DevInit - Device/phy initialization. Should always be set.
+ // SequenceCtrl[1] = RFU, must be zero
+ // SequenceCtrl[2] = RFU, must be zero
+ // SequenceCtrl[3] = RFU, must be zero
+ // SequenceCtrl[4] = RFU, must be zero
+ // SequenceCtrl[5] = Run rd2D - 2d read dqs training
+ // SequenceCtrl[6] = Run wr2D - 2d write dq training
+ // SequenceCtrl[7] = RFU, must be zero
+ // SequenceCtrl[8] = RFU, must be zero
+ // SequenceCtrl[9] = RFU, must be zero
+ // SequenceCtrl[11-10] = RFU, must be zero
+ // SequenceCtrl[12] = RFU, must be zero
+ // SequenceCtrl[15-13] = RFU, must be zero
+ uint8_t HdtCtrl; // Byte offset 0x12, CSR Addr 0x54009, Direction=In
+ // To control the total number of debug messages, a verbosity subfield (HdtCtrl, Hardware Debug Trace Control) exists in the message block. Every message has a verbosity level associated with it, and as the HdtCtrl value is increased, less important s messages stop being sent through the mailboxes. The meanings of several major HdtCtrl thresholds are explained below:
+ //
+ // 0x05 = Detailed debug messages (e.g. Eye delays)
+ // 0x0A = Coarse debug messages (e.g. rank information)
+ // 0xC8 = Stage completion
+ // 0xC9 = Assertion messages
+ // 0xFF = Firmware completion messages only
+ //
+ // See Training App Note for more detailed information on what messages are included for each threshold.
+ //
+ uint8_t Reserved13; // Byte offset 0x13, CSR Addr 0x54009, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved14; // Byte offset 0x14, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t Reserved15; // Byte offset 0x15, CSR Addr 0x5400a, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t DFIMRLMargin; // Byte offset 0x16, CSR Addr 0x5400b, Direction=In
+ // Margin added to smallest passing trained DFI Max Read Latency value, in units of DFI clocks. Recommended to be >= 1. See the Training App Note for more details on the training process and the use of this value.
+ //
+ // This margin must include the maximum positive drift expected in tDQSCK over the target temperature and voltage range of the users system.
+ uint8_t Reserved17; // Byte offset 0x17, CSR Addr 0x5400b, Direction=N/A
+ // This field is reserved and must be programmed to 0x00.
+ uint8_t UseBroadcastMR; // Byte offset 0x18, CSR Addr 0x5400c, Direction=In
+ // Training firmware can optionally set per rank mode register values for DRAM partial array self-refresh features if desired.
+ //
+ // 0x0 = Use MR<0:17>_A0 for rank 0 channel A
+ // Use MR<0:17>_B0 for rank 0 channel B
+ // Use MR<0:17>_A1 for rank 1 channel A
+ // Use MR<0:17>_B1 for rank 1 channel B
+ //
+ // 0x1 = Use MR<0:17>_A0 setting for all channels/ranks
+ //
+ // It is recommended in most LPDDR4 system configurations to set this to 1.
+ //
+ // Note: When set to 0, only mode registers associated with Vref CA, Vref DQ, and DRAM partial array self-refresh may differ between ranks and channels.
+ //
+ uint8_t Reserved19; // Byte offset 0x19, CSR Addr 0x5400c, Direction=N/A
+
+ uint8_t Reserved1A; // Byte offset 0x1a, CSR Addr 0x5400d, Direction=In
+ // Input for constraining the range of vref(DQ) values training will collect data for, usually reducing training time. However, too large of a voltage range may cause longer 2D training times while too small of a voltage range may truncate passing regions. When in doubt, leave this field set to 0.
+ // Used by 2D stages: Rd2D, Wr2D
+ //
+ // Reserved1A[0-3]: Rd2D Voltage Range
+ // 0 = Training will search all phy vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from phyVref
+ // 2 = limit to +/-4 %VDDQ from phyVref
+ // …
+ // 15 = limit to +/-30% VDDQ from phyVref
+ //
+ // Reserved1A[4-7]: Wr2D Voltage Range
+ // 0 = Training will search all dram vref(DQ) settings
+ // 1 = limit to +/-2 %VDDQ from MR14
+ // 2 = limit to +/-4 %VDDQ from MR14
+ // …
+ // 15 = limit to +/-30% VDDQ from MR14
+ uint8_t CATrainOpt; // Byte offset 0x1b, CSR Addr 0x5400d, Direction=In
+ // CA training option bit field
+ // [0] CA VREF Setting
+ // 1 = Set MR12 from internal register
+ // 0 = Set MR12 from message block
+ // [1-7] RFU must be zero
+ uint8_t X8Mode; // Byte offset 0x1c, CSR Addr 0x5400e, Direction=In
+ // X8 mode configuration:
+ // 0x0 = x16 configuration for all devices
+ // 0xF = x8 configuration for all devices
+ // All other values are RFU
+ uint8_t RX2D_TrainOpt; // Byte offset 0x1d, CSR Addr 0x5400e, Direction=In
+ // Bit fields, if 2D read training enabled, then use these additional options:
+ // [0] DFE
+ // 1 = Run rx2D with DFE
+ // 0 = Run rx2D with DFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5-7] RFU, must be zero
+ //
+ uint8_t TX2D_TrainOpt; // Byte offset 0x1e, CSR Addr 0x5400f, Direction=In
+ // Bit fields, if 2D write training is enabled, then use these additional options:
+ // [0] FFE
+ // 1 = Train tx2D with FFE
+ // 0 = Train tx2D with FFE off
+ // [1-2] Voltage Step Size (2^n)
+ // 3 = 8 DAC settings between checked values
+ // 2 = 4 DAC settings between checked values
+ // 1 = 2 DAC settings between checked values
+ // 0 = 1 DAC settings between checked values
+ // [3-4] Delay Step Size (2^n)
+ // 3 = 8 LCDL delays between checked values
+ // 2 = 4 LCDL delays between checked values
+ // 1 = 2 LCDL delays between checked values
+ // 0 = 1 LCDL delays between checked values
+ // [5-7] RFU, must be zero
+ //
+ uint8_t Share2DVrefResult; // Byte offset 0x1f, CSR Addr 0x5400f, Direction=In
+ // Bitmap that designates the phy's vref source for every pstate
+ // If Share2DVrefResult[x] = 0, then after 2D training, pstate x will continue using the phyVref provided in pstate x’s 1D messageblock.
+ // If Share2DVrefResult[x] = 1, then after 2D training, pstate x will use the per-lane VrefDAC0/1 CSRs trained by 2d training.
+ uint8_t Delay_Weight2D; // Byte offset 0x20, CSR Addr 0x54010, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable delay margin is compared to voltage margin. delay_weight2D sets the value, or weight, of one step of delay margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 32 delay steps in a perfect eye.
+ uint8_t Voltage_Weight2D; // Byte offset 0x21, CSR Addr 0x54010, Direction=In
+ // During 2D training, the ideal eye center changes depending on how valuable voltage margin is compared to delay margin. voltage_weight2D sets the value, or weight, of one step of voltage margin. The ratio of voltage_weight2D to delay_weight2D will be used by 2D training to choose your preferred center point. There are 128 voltage steps in a perfect eye.
+ uint16_t PhyConfigOverride; // Byte offset 0x22, CSR Addr 0x54011, Direction=In
+ // Override PhyConfig csr.
+ // 0x0: Use hardware csr value for PhyConfing (recommended)
+ // Other values: Use value for PhyConfig instead of Hardware value.
+ //
+ uint8_t EnabledDQsChA; // Byte offset 0x24, CSR Addr 0x54012, Direction=In
+ // Total number of DQ bits enabled in PHY Channel A
+ uint8_t CsPresentChA; // Byte offset 0x25, CSR Addr 0x54012, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel A.
+ //
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChA_RR_1_0; // Byte offset 0x26, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RR_0_1; // Byte offset 0x27, CSR Addr 0x54013, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_1; // Byte offset 0x28, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_1_0; // Byte offset 0x29, CSR Addr 0x54014, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_1; // Byte offset 0x2a, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_RW_0_0; // Byte offset 0x2b, CSR Addr 0x54015, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_1; // Byte offset 0x2c, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_1_0; // Byte offset 0x2d, CSR Addr 0x54016, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_1; // Byte offset 0x2e, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WR_0_0; // Byte offset 0x2f, CSR Addr 0x54017, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_1_0; // Byte offset 0x30, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChA_WW_0_1; // Byte offset 0x31, CSR Addr 0x54018, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel A
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_A0; // Byte offset 0x32, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 0}
+ uint8_t MR2_A0; // Byte offset 0x33, CSR Addr 0x54019, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 0}
+ uint8_t MR3_A0; // Byte offset 0x34, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 0}
+ uint8_t MR4_A0; // Byte offset 0x35, CSR Addr 0x5401a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 0}
+ uint8_t MR11_A0; // Byte offset 0x36, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 0}
+ uint8_t MR12_A0; // Byte offset 0x37, CSR Addr 0x5401b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 0}
+ uint8_t MR13_A0; // Byte offset 0x38, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 0}
+ uint8_t MR14_A0; // Byte offset 0x39, CSR Addr 0x5401c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 0}
+ uint8_t MR16_A0; // Byte offset 0x3a, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 0}
+ uint8_t MR17_A0; // Byte offset 0x3b, CSR Addr 0x5401d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 0}
+ uint8_t MR22_A0; // Byte offset 0x3c, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 0}
+ uint8_t MR24_A0; // Byte offset 0x3d, CSR Addr 0x5401e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 0}
+ uint8_t MR1_A1; // Byte offset 0x3e, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel A, Rank 1}
+ uint8_t MR2_A1; // Byte offset 0x3f, CSR Addr 0x5401f, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel A, Rank 1}
+ uint8_t MR3_A1; // Byte offset 0x40, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel A, Rank 1}
+ uint8_t MR4_A1; // Byte offset 0x41, CSR Addr 0x54020, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel A, Rank 1}
+ uint8_t MR11_A1; // Byte offset 0x42, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel A, Rank 1}
+ uint8_t MR12_A1; // Byte offset 0x43, CSR Addr 0x54021, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel A, Rank 1}
+ uint8_t MR13_A1; // Byte offset 0x44, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel A, Rank 1}
+ uint8_t MR14_A1; // Byte offset 0x45, CSR Addr 0x54022, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel A, Rank 1}
+ uint8_t MR16_A1; // Byte offset 0x46, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel A, Rank 1}
+ uint8_t MR17_A1; // Byte offset 0x47, CSR Addr 0x54023, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel A, Rank 1}
+ uint8_t MR22_A1; // Byte offset 0x48, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel A, Rank 1}
+ uint8_t MR24_A1; // Byte offset 0x49, CSR Addr 0x54024, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel A, Rank 1}
+ uint8_t CATerminatingRankChA; // Byte offset 0x4a, CSR Addr 0x54025, Direction=In
+ // Terminating Rank for CA bus on Channel A
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved4B; // Byte offset 0x4b, CSR Addr 0x54025, Direction=N/A
+
+ uint8_t Reserved4C; // Byte offset 0x4c, CSR Addr 0x54026, Direction=N/A
+
+ uint8_t TrainedVREFDQ_A0; // Byte offset 0x4d, CSR Addr 0x54026, Direction=Out
+ // Trained DQ Vref setting for Ch A Rank 0
+ uint8_t TrainedVREFDQ_A1; // Byte offset 0x4e, CSR Addr 0x54027, Direction=Out
+ // Trained DQ Vref setting for Ch A Rank 1
+ uint8_t RxClkDly_Margin_A0; // Byte offset 0x4f, CSR Addr 0x54027, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_A0; // Byte offset 0x50, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_A0; // Byte offset 0x51, CSR Addr 0x54028, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_A0; // Byte offset 0x52, CSR Addr 0x54029, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t RxClkDly_Margin_A1; // Byte offset 0x53, CSR Addr 0x54029, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_A1; // Byte offset 0x54, CSR Addr 0x5402a, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_A1; // Byte offset 0x55, CSR Addr 0x5402a, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_A1; // Byte offset 0x56, CSR Addr 0x5402b, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t EnabledDQsChB; // Byte offset 0x57, CSR Addr 0x5402b, Direction=In
+ // Total number of DQ bits enabled in PHY Channel B
+ uint8_t CsPresentChB; // Byte offset 0x58, CSR Addr 0x5402c, Direction=In
+ // Indicates presence of DRAM at each chip select for PHY channel B.
+ //
+ // 0x0 = No chip selects are populated with DRAM
+ // 0x1 = CS0 is populated with DRAM
+ // 0x3 = CS0 and CS1 are populated with DRAM
+ //
+ // All other encodings are illegal
+ //
+ int8_t CDD_ChB_RR_1_0; // Byte offset 0x59, CSR Addr 0x5402c, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RR_0_1; // Byte offset 0x5a, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_1; // Byte offset 0x5b, CSR Addr 0x5402d, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_1_0; // Byte offset 0x5c, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_1; // Byte offset 0x5d, CSR Addr 0x5402e, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_RW_0_0; // Byte offset 0x5e, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Read to write critical delay difference from cs01 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_1; // Byte offset 0x5f, CSR Addr 0x5402f, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_1_0; // Byte offset 0x60, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_1; // Byte offset 0x61, CSR Addr 0x54030, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WR_0_0; // Byte offset 0x62, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to read critical delay difference from cs 0 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_1_0; // Byte offset 0x63, CSR Addr 0x54031, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 1 to cs 0 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ int8_t CDD_ChB_WW_0_1; // Byte offset 0x64, CSR Addr 0x54032, Direction=Out
+ // This is a signed integer value.
+ // Write to write critical delay difference from cs 0 to cs 1 on Channel B
+ // See PUB Databook section 8.2 for details on use of CDD values.
+ uint8_t MR1_B0; // Byte offset 0x65, CSR Addr 0x54032, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 0}
+ uint8_t MR2_B0; // Byte offset 0x66, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 0}
+ uint8_t MR3_B0; // Byte offset 0x67, CSR Addr 0x54033, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 0}
+ uint8_t MR4_B0; // Byte offset 0x68, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 0}
+ uint8_t MR11_B0; // Byte offset 0x69, CSR Addr 0x54034, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 0}
+ uint8_t MR12_B0; // Byte offset 0x6a, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 0}
+ uint8_t MR13_B0; // Byte offset 0x6b, CSR Addr 0x54035, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 0}
+ uint8_t MR14_B0; // Byte offset 0x6c, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 0}
+ uint8_t MR16_B0; // Byte offset 0x6d, CSR Addr 0x54036, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 0}
+ uint8_t MR17_B0; // Byte offset 0x6e, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 0}
+ uint8_t MR22_B0; // Byte offset 0x6f, CSR Addr 0x54037, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 0}
+ uint8_t MR24_B0; // Byte offset 0x70, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 0}
+ uint8_t MR1_B1; // Byte offset 0x71, CSR Addr 0x54038, Direction=In
+ // Value to be programmed in DRAM Mode Register 1 {Channel B, Rank 1}
+ uint8_t MR2_B1; // Byte offset 0x72, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 2 {Channel B, Rank 1}
+ uint8_t MR3_B1; // Byte offset 0x73, CSR Addr 0x54039, Direction=In
+ // Value to be programmed in DRAM Mode Register 3 {Channel B, Rank 1}
+ uint8_t MR4_B1; // Byte offset 0x74, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 4 {Channel B, Rank 1}
+ uint8_t MR11_B1; // Byte offset 0x75, CSR Addr 0x5403a, Direction=In
+ // Value to be programmed in DRAM Mode Register 11 {Channel B, Rank 1}
+ uint8_t MR12_B1; // Byte offset 0x76, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 12 {Channel B, Rank 1}
+ uint8_t MR13_B1; // Byte offset 0x77, CSR Addr 0x5403b, Direction=In
+ // Value to be programmed in DRAM Mode Register 13 {Channel B, Rank 1}
+ uint8_t MR14_B1; // Byte offset 0x78, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 14 {Channel B, Rank 1}
+ uint8_t MR16_B1; // Byte offset 0x79, CSR Addr 0x5403c, Direction=In
+ // Value to be programmed in DRAM Mode Register 16 {Channel B, Rank 1}
+ uint8_t MR17_B1; // Byte offset 0x7a, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 17 {Channel B, Rank 1}
+ uint8_t MR22_B1; // Byte offset 0x7b, CSR Addr 0x5403d, Direction=In
+ // Value to be programmed in DRAM Mode Register 22 {Channel B, Rank 1}
+ uint8_t MR24_B1; // Byte offset 0x7c, CSR Addr 0x5403e, Direction=In
+ // Value to be programmed in DRAM Mode Register 24 {Channel B, Rank 1}
+ uint8_t CATerminatingRankChB; // Byte offset 0x7d, CSR Addr 0x5403e, Direction=In
+ // Terminating Rank for CA bus on Channel B
+ // 0x0 = Rank 0 is terminating rank
+ // 0x1 = Rank 1 is terminating rank
+ uint8_t Reserved7E; // Byte offset 0x7e, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t Reserved7F; // Byte offset 0x7f, CSR Addr 0x5403f, Direction=N/A
+
+ uint8_t TrainedVREFDQ_B0; // Byte offset 0x80, CSR Addr 0x54040, Direction=Out
+ // Trained DQ Vref setting for Ch B Rank 0
+ uint8_t TrainedVREFDQ_B1; // Byte offset 0x81, CSR Addr 0x54040, Direction=Out
+ // Trained DQ Vref setting for Ch B Rank 1
+ uint8_t RxClkDly_Margin_B0; // Byte offset 0x82, CSR Addr 0x54041, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_B0; // Byte offset 0x83, CSR Addr 0x54041, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_B0; // Byte offset 0x84, CSR Addr 0x54042, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_B0; // Byte offset 0x85, CSR Addr 0x54042, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t RxClkDly_Margin_B1; // Byte offset 0x86, CSR Addr 0x54043, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t VrefDac_Margin_B1; // Byte offset 0x87, CSR Addr 0x54043, Direction=Out
+ // Distance from the trained center to the closest failing region in phy DAC steps. This value is the minimum of all eyes in this timing group.
+ uint8_t TxDqDly_Margin_B1; // Byte offset 0x88, CSR Addr 0x54044, Direction=Out
+ // Distance from the trained center to the closest failing region in DLL steps. This value is the minimum of all eyes in this timing group.
+ uint8_t DeviceVref_Margin_B1; // Byte offset 0x89, CSR Addr 0x54044, Direction=Out
+ // Distance from the trained center to the closest failing region in device DAC steps. This value is the minimum of all eyes in this timing group.
+} __attribute__ ((packed)) PMU_SMB_LPDDR4_2D_t;
diff --git a/arch/arm/include/asm/arch-t7/nand.h b/arch/arm/include/asm/arch-t7/nand.h
new file mode 100644
index 0000000..91484ac
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/nand.h
@@ -0,0 +1,135 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __NAND_H__
+#define __NAND_H__
+#include <asm/arch/cpu_config.h>
+
+#ifndef SD_EMMC_BASE_C
+#define SD_EMMC_BASE_C 0xd0074000
+#endif
+
+#define P_NAND_BASE (SD_EMMC_BASE_C | (1<<11))
+#define P_CLK_CNTL (volatile uint32_t *)(SD_EMMC_BASE_C)
+#define P_NAND_CMD (volatile uint32_t *)(P_NAND_BASE + 0x00)
+#define P_NAND_CFG (volatile uint32_t *)(P_NAND_BASE + 0x04)
+#define P_NAND_DADR (volatile uint32_t *)(P_NAND_BASE + 0x08)
+#define P_NAND_IADR (volatile uint32_t *)(P_NAND_BASE + 0x0c)
+#define P_NAND_BUF (volatile uint32_t *)(P_NAND_BASE + 0x10)
+#define P_NAND_INFO (volatile uint32_t *)(P_NAND_BASE + 0x14)
+#define P_NAND_DC (volatile uint32_t *)(P_NAND_BASE + 0x18)
+#define P_NAND_ADR (volatile uint32_t *)(P_NAND_BASE + 0x1c)
+#define P_NAND_DL (volatile uint32_t *)(P_NAND_BASE + 0x20)
+#define P_NAND_DH (volatile uint32_t *)(P_NAND_BASE + 0x24)
+#define P_NAND_CADR (volatile uint32_t *)(P_NAND_BASE + 0x28)
+#define P_NAND_SADR (volatile uint32_t *)(P_NAND_BASE + 0x2c)
+
+#define CEF (0xf<<10)
+#define CE0 (0xe<<10)
+#define CE1 (0xd<<10)
+#define CE2 (0xb<<10)
+#define CE3 (0x7<<10)
+
+#define IO4 ((0xe<<10)|(1<<18))
+#define IO5 ((0xd<<10)|(1<<18))
+#define IO6 ((0xb<<10)|(1<<18))
+
+#define CLE (0x5<<14)
+#define ALE (0x6<<14)
+#define DWR (0x4<<14)
+#define DRD (0x8<<14)
+#define IDLE (0xc<<14)
+#define RB (1<<20)
+
+#define M2N ((0<<17) | (2<<20) | (1<<19))
+#define N2M ((1<<17) | (2<<20) | (1<<19))
+#define STS ((3<<17) | (2<<20))
+#define ADL ((0<<16) | (3<<20))
+#define ADH ((1<<16) | (3<<20))
+#define AIL ((2<<16) | (3<<20))
+#define AIH ((3<<16) | (3<<20))
+#define ASL ((4<<16) | (3<<20))
+#define ASH ((5<<16) | (3<<20))
+#define SEED ((8<<16) | (3<<20))
+
+// NAND Flash Manufacturer ID Codes
+#define NAND_MFR_TOSHIBA 0x98
+#define NAND_MFR_SAMSUNG 0xec
+#define NAND_MFR_FUJITSU 0x04
+#define NAND_MFR_NATIONAL 0x8f
+#define NAND_MFR_RENESAS 0x07
+#define NAND_MFR_STMICRO 0x20
+#define NAND_MFR_HYNIX 0xad
+#define NAND_MFR_MICRON 0x2c
+#define NAND_MFR_AMD 0x01
+#define NAND_MFR_INTEL 0x89
+#define NAND_MFR_SANDISK 0x45
+#define NAND_MFR_USER 0x100
+#define NAND_MFR_EFUSE 0x101
+
+typedef struct nand_setup {
+ union {
+ uint32_t d32;
+ struct {
+ unsigned cmd:22;
+ unsigned large_page:1; // 22
+ unsigned no_rb:1; // 23 from efuse
+ unsigned a2:1; // 24
+ unsigned reserved25:1; // 25
+ unsigned page_list:1; // 26
+ unsigned sync_mode:2; // 27 from efuse
+ unsigned size:2; // 29 from efuse
+ unsigned active:1; // 31
+ } b;
+ } cfg;
+ uint16_t id;
+ uint16_t max; // id:0x100 user, max:0 disable.
+} nand_setup_t;
+
+typedef struct _nand_cmd{
+ unsigned char type;
+ unsigned char val;
+} nand_cmd_t;
+
+typedef struct _ext_info{
+ uint32_t read_info; //nand_read_info;
+ uint32_t new_type; //new_nand_type;
+ uint32_t page_per_blk; //pages_in_block;
+ uint32_t xlc; //slc=1, mlc=2, tlc=3.
+ uint32_t rsv1[5];
+} ext_info_t;
+
+typedef struct _nand_page0 {
+ nand_setup_t nand_setup; //8
+ unsigned char page_list[16]; //16
+ nand_cmd_t retry_usr[32]; //64 (32 cmd max I/F)
+ ext_info_t ext_info; //64
+} nand_page0_t; //384 bytes max.
+
+//#define NAND_PAGE0_BUF BL1_NAND_BUFF
+#define NAND_PAGE0_BUF (0x1800000)
+#define NAND_PAGE_LIST (NAND_PAGE0_BUF + sizeof(nand_setup_t))
+#define NAND_RETRY_USER (NAND_PAGE_LIST + 16)
+#define NAND_INFO_BUF (NAND_PAGE0_BUF + 512)
+#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1)
+//#define DEFAULT_ECC_MODE ((1<<23) |(1<<22) | (2<<20) |(1<<19) |(1<<17)|(7<<14)|(1<<13)|(48<<6)|1)
+
+#define ERROR_MOD(mod,num) ((uint32_t)(((mod<<6)|num)))
+#define ERROR_NAND_TIMEOUT ERROR_MOD(2,1) //
+#define ERROR_NAND_ECC ERROR_MOD(2,2) //
+#define ERROR_NAND_MAGIC_WORD ERROR_MOD(2,3) //
+#define ERROR_NAND_INIT_READ ERROR_MOD(2,4) //
+#define ERROR_NAND_BLANK_PAGE ERROR_MOD(2,5) //
+#define ERROR_NAND_UNALIGN_SRC ERROR_MOD(2,6) //
+
+#define NAND_SECTOR_SIZE (512)
+#define NAND_MAX_PAGESIZE (0x4000) //16K
+#define SRC_ALIGN_SIZE (NAND_MAX_PAGESIZE)
+
+#define INFO_BYTE_PER_ECCPAGE (8)
+uint32_t nfio_init(void);
+uint32_t nf_read(uint32_t boot_device, uint32_t src, uint32_t des, uint32_t size);
+#endif /* __NAND_H__ */
+
diff --git a/arch/arm/include/asm/arch-t7/oscring.h b/arch/arm/include/asm/arch-t7/oscring.h
new file mode 100644
index 0000000..80f332b
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/oscring.h
@@ -0,0 +1,21 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __OSCRING_H__
+#define __OSCRING_H__
+
+#define OSCRING_CTL_REG0 SYSCTRL_OSC_RING_CTRL0
+#define OSCRING_CTL_DATA0 0x55555555 /*0:25*/
+#define OSCRING_CTL_REG1 SYSCTRL_OSC_RING_CTRL1
+#define OSCRING_CTL_DATA1 0x80001555 /*0:13*/
+#define OSCRING_CTL_REG2 SYSCTRL_OSC_RING_CTRL2
+#define OSCRING_CTL_DATA2 0x55555555 /*0:25*/
+
+#define RING_PWM_VCCK_A PWM_AO_CD_PWM_B
+#define RING_PWM_VCCK_B PWM_AO_AB_PWM_B
+#define RING_PWM_EE PWM_AO_AB_PWM_A
+
+int ring_msr(int index);
+#endif
diff --git a/arch/arm/include/asm/arch-t7/pinctrl_init.h b/arch/arm/include/asm/arch-t7/pinctrl_init.h
new file mode 100644
index 0000000..cfbc42a
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/pinctrl_init.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _MESON_PINCTRL_INIT_H_
+#define _MESON_PINCTRL_INIT_H_
+
+#define PIN_CONTROLLER_NUM 2
+extern int pinctrl_devices_active(int pinctrl_num);
+
+#endif /* _MESON_PINCTRL_INIT_H_ */
diff --git a/arch/arm/include/asm/arch-t7/pll.h b/arch/arm/include/asm/arch-t7/pll.h
new file mode 100644
index 0000000..d89ab5e
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/pll.h
@@ -0,0 +1,167 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __PLL_H
+#define __PLL_H
+
+#define PLL_TEST_SYS_TOTAL 2
+#define PLL_TEST_HIFI_TOTAL 2
+#define PLL_TEST_GP0_TOTAL 2
+#define PLL_TEST_GP1_TOTAL 2
+#define PLL_TEST_HDMI_TOTAL 2
+
+typedef struct sys_pll_set_s {
+ unsigned int cpu_clk;
+ unsigned int pll_cntl;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+}sys_pll_set_t;
+
+typedef struct sys_pll_cfg_s {
+ sys_pll_set_t sys_pll[PLL_TEST_SYS_TOTAL];
+}sys_pll_cfg_t;
+
+typedef struct hdmi_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+}hdmi_pll_set_t;
+
+typedef struct hdmi_pll_cfg_s {
+ hdmi_pll_set_t hdmi_pll[PLL_TEST_HDMI_TOTAL];
+}hdmi_pll_cfg_t;
+
+typedef struct gpll_rate_table_s {
+ unsigned int rate;
+ unsigned int m;
+ unsigned int n;
+ unsigned int od;
+}gpll_rate_table_t;
+
+typedef struct hifipll_rate_table_s {
+ unsigned int rate;
+ unsigned int m;
+ unsigned int n;
+ unsigned int od;
+}hifipll_rate_table_t;
+
+typedef struct gp0_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+}gp0_pll_set_t;
+
+typedef struct gp0_pll_cfg_s {
+ gp0_pll_set_t gp0_pll[PLL_TEST_GP0_TOTAL];
+}gp0_pll_cfg_t;
+
+typedef struct gp1_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+}gp1_pll_set_t;
+
+typedef struct gp1_pll_cfg_s {
+ gp1_pll_set_t gp1_pll[PLL_TEST_GP1_TOTAL];
+}gp1_pll_cfg_t;
+
+typedef struct hifi_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+}hifi_pll_set_t;
+
+typedef struct hifi_pll_cfg_s {
+ hifi_pll_set_t hifi_pll[PLL_TEST_HIFI_TOTAL];
+}hifi_pll_cfg_t;
+
+typedef struct pcie_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+}pcie_pll_set_t;
+
+typedef struct ethphy_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+}ethphy_pll_set_t;
+
+typedef struct usbphy_pll_set_s {
+ unsigned int pll_clk;
+ unsigned int pll_cntl0;
+ unsigned int pll_cntl1;
+ unsigned int pll_cntl2;
+ unsigned int pll_cntl3;
+ unsigned int pll_cntl4;
+ unsigned int pll_cntl5;
+ unsigned int pll_cntl6;
+ unsigned int pll_cntl7;
+}usbphy_pll_set_t;
+
+struct pciepll_rate_table {
+ u16 rate;
+ u16 m;
+ u16 n;
+ u16 od;
+ u16 od2;
+ u16 frac;
+};
+
+#define PLL_RATE(_r, _m, _n, _od) \
+ { \
+ .rate = (_r), \
+ .m = (_m), \
+ .n = (_n), \
+ .od = (_od), \
+ } \
+
+enum pll_enum {
+ PLL_SYS = 0,
+ PLL_FIX,
+ PLL_DDR,
+ PLL_HDMI,
+ PLL_GP0,
+ PLL_HIFI,
+ PLL_PCIE,
+ PLL_GP1,
+ PLL_USBPHY,
+ PLL_ENUM,
+
+};
+
+int pll_test(int argc, char * const argv[]);
+
+#endif /* __PLL_H */
diff --git a/arch/arm/include/asm/arch-t7/pmic_bd71837.h b/arch/arm/include/asm/arch-t7/pmic_bd71837.h
new file mode 100644
index 0000000..e89d3fb
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/pmic_bd71837.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _MESON_PMIC_BD71837_H_
+#define _MESON_PMIC_BD71837_H_
+
+#define I2C_BUS_ID 6
+#define BD71837_CHIP_DEV 0x4b
+#define BD71837_REG_MUXSW_EN 0x30
+
+void bd71837_set_muxsw_switch(int enable);
+void pmic_bd71837_init(void);
+#endif /*_MESON_PMIC_BD71837_H_*/
diff --git a/arch/arm/include/asm/arch-t7/pwr_ctrl.h b/arch/arm/include/asm/arch-t7/pwr_ctrl.h
new file mode 100644
index 0000000..7087fde
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/pwr_ctrl.h
@@ -0,0 +1,65 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#define PWR_ON 1
+#define PWR_OFF 0
+
+#define PM_DSPA 0
+#define PM_DSPB 1
+#define PM_DOS_HCODEC 2
+#define PM_DOS_HEVC 3
+#define PM_DOS_VDEC 4
+#define PM_DOS_WAVE 5
+#define PM_VPU_HDMI 6
+#define PM_USB_COMB 7
+#define PM_PCIE 8
+#define PM_GE2D 9
+#define PM_SRAMA 10
+#define PM_SRAMB 11
+#define PM_HDMIRX 12
+#define PM_VI_CLK1 13
+#define PM_VI_CLK2 14
+#define PM_ETH 15
+#define PM_ISP 16
+#define PM_MIPI_ISP 17
+#define PM_GDC 18
+#define PM_DEWARP 19
+#define PM_SDIO_A 20
+#define PM_SDIO_B 21
+#define PM_EMMC 22
+#define PM_MALI_SC0 23
+#define PM_MALI_SC1 24
+#define PM_MALI_SC2 25
+#define PM_MALI_SC3 26
+#define PM_MALI_TOP 27
+#define PM_NNA_CORE0 28
+#define PM_NNA_CORE1 29
+#define PM_NNA_CORE2 30
+#define PM_NNA_CORE3 31
+#define PM_NNA_TOP 32
+#define PM_DDR0 33
+#define PM_DDR1 34
+#define PM_DMC0 35
+#define PM_DMC1 36
+#define PM_NOC 37
+#define PM_NIC2 38
+#define PM_NIC3 39
+#define PM_CCI 40
+#define PM_MIPI_DSI0 41
+#define PM_SPICC0 42
+#define PM_SPICC1 43
+#define PM_SPICC2 44
+#define PM_SPICC3 45
+#define PM_SPICC4 46
+#define PM_SPICC5 47
+#define PM_EDP0 48
+#define PM_EDP1 49
+#define PM_MIPI_DSI1 50
+#define PM_AUDIO 51
+
+#define PM_MAX 52
+
+unsigned long pwr_ctrl_psci_smc(unsigned int power_domain, bool power_control);
+unsigned long pwr_ctrl_status_psci_smc(unsigned int power_domain);
diff --git a/arch/arm/include/asm/arch-t7/reboot.h b/arch/arm/include/asm/arch-t7/reboot.h
new file mode 100644
index 0000000..e7fb8bd
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/reboot.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __REBOOT_H
+#define __REBOOT_H
+
+#include "soc_def.h"
+
+/*
+Reboot reason AND corresponding env setting:
+0: Cold boot cold_boot
+1: Normal boot normal
+2: Factory reset factory_reset
+3: Upgrade system update
+4: Fastboot fastboot
+5: Suspend suspend_off
+6: Hibernate hibernate
+7: Fastboot Bootloader bootloader
+8: Shutdown reboot shutdown_reboot
+9: RPMBP reboot rpmbp
+10: quiescent reboot quiescent reboot
+11 : rescueparty rollback in AB mode
+12: Kernel panic kernel_panic
+13: Watchdog reboot watchdog_reboot
+14: quiescent recovery reboot quiescent recovery
+15: reserved
+*/
+#define AMLOGIC_COLD_BOOT 0
+#define AMLOGIC_NORMAL_BOOT 1
+#define AMLOGIC_FACTORY_RESET_REBOOT 2
+#define AMLOGIC_UPDATE_REBOOT 3
+#define AMLOGIC_FASTBOOT_REBOOT 4
+#define AMLOGIC_SUSPEND_REBOOT 5
+#define AMLOGIC_HIBERNATE_REBOOT 6
+#define AMLOGIC_BOOTLOADER_REBOOT 7 /* fastboot bootloader */
+#define AMLOGIC_SHUTDOWN_REBOOT 8
+#define AMLOGIC_RPMBP_REBOOT 9
+#define AMLOGIC_QUIESCENT_REBOOT 10
+#define AMLOGIC_RESCUEPARTY_REBOOT 11
+#define AMLOGIC_KERNEL_PANIC 12
+#define AMLOGIC_WATCHDOG_REBOOT 13
+#define AMLOGIC_RECOVERY_QUIESCENT_REBOOT 14
+
+/*
+old version env
+0x01010101, normal
+0x02020202, factory_reset
+0x03030303, update
+0x09090909, usb_burning
+0x0b0b0b0b, suspend_off
+*/
+
+#endif
+
diff --git a/arch/arm/include/asm/arch-t7/register.h b/arch/arm/include/asm/arch-t7/register.h
new file mode 100644
index 0000000..6bee9d3
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/register.h
@@ -0,0 +1,35845 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifdef REGISTER_H
+#else
+#define REGISTER_H
+
+#if 0
+#ifndef VERIFICATION
+ #define Wr64(addr, data) *(volatile uint64_t *)(addr)=(data)
+ #define Rd64(addr) *(volatile uint64_t *)(addr)
+ #define Wr(addr, data) *(volatile uint32_t *)(addr)=(data)
+ #define Rd(addr) *(volatile uint32_t *)(addr)
+ #define Wr_reg_bits(reg, val, start, len) \
+ Wr(reg, ((Rd(reg) & ~(((1L<<(len))-1)<<(start))) | ((uint32_t)(val) << (start))))
+#else
+ #include "dpi.h"
+#endif
+#endif
+//
+// Reading file: ./REG_LIST_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+//
+// Reading file: ../mmc_lp4/dmc_clk_freq/rtl/dmc_clk_freq.vh
+//
+//dmc pll and freqeucy domain control registers.
+//`define DMC_FREQ_REG_BASE 32'hfe0a0000
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe0a0000
+// -----------------------------------------------
+#define AM_DDR_PLL_CNTL0 ((0x0000 << 2) + 0xfe0a0000)
+ //bit 31 : dpll_lock
+ //bit 29 : dpll_reset.
+ //bit 28 : dpll_en.
+ //bit 27:26 : dpll_clk_en
+ //bit 25 : dpll_inv_sel
+ //bit 21:19 : od1; if set ddr_freq_sel, it would replaced by ddr_pll_freq1[6:4]
+ //bit 18:16 : od; if set ddr_freq_sel, it would replaced by ddr_pll_freq1_od[2:0]
+ //bit 14:10 : dpll_ref_div_n
+ //bit 8:0 : dpll_int_num
+#define AM_DDR_PLL_CNTL1 ((0x0001 << 2) + 0xfe0a0000)
+ //bit 18:0 : ddr_dpll_frac
+#define AM_DDR_PLL_CNTL2 ((0x0002 << 2) + 0xfe0a0000)
+ //bit 22:20 : fref_sel
+ //bit 17:16 : os_ssc
+ //bit 15:12 : ssc_str_m
+ //bit 8 : ssc_en
+ //bit 7:4 : ssc_dep_sel
+ //bit 1:0 : dpll ss_mode.
+#define AM_DDR_PLL_CNTL3 ((0x0003 << 2) + 0xfe0a0000)
+ //bit 31 : afc bypass
+ //bit 30 : afc clk sel
+ //bit 29 : code new
+ //bit 28 : dco_m_en
+ //bit 27 : dco_sdm_en
+ //bit 26 : div2
+ //bit 25 : div mode
+ //bit 24 : fast_lock mode
+ //bit 23 : fb_pre_div
+ //bit 22 : filter_mode
+ //bit 21 : fix_en
+ //bit 20 : freq_shift_en
+ //bit 19 : load
+ //bit 18 : load_en
+ //bit 17 : lock_f
+ //bit 16 : pulse_width_en
+ //bit 15 : sdmnc_en
+ //bit 14 : sdmnc_mode
+ //bit 13 : sdmnc_range
+ //bit 12 : tdc_en
+ //bit 11 : tdc_mode_sel
+ //bit 10 : wait_en
+#define AM_DDR_PLL_CNTL4 ((0x0004 << 2) + 0xfe0a0000)
+ //bit 1:0 : pfd_gain
+ //bit 7:4 : filter_pvt1
+ //bit 11:8 : filter pvt2
+ //bit 13:12 : acq_gain
+ //bit 18:16 : lambda0
+ //bit 27:24 : rou
+ //bit 31:28 : alpha
+#define AM_DDR_PLL_CNTL5 ((0x0005 << 2) + 0xfe0a0000)
+ //bit 15:0 : reve
+ //bit 21:16 : lm_s
+ //bit 27:24 : lm_w
+ //bit 30:28 : adj_vco_ldo
+#define AM_DDR_PLL_CNTL6 ((0x0006 << 2) + 0xfe0a0000)
+ //bit 31:30 : afc_hold_t
+ //bit 29:28 : lkw_sel
+ //bit 27:26 : dco_sdm_clk_sel
+ //bit 25:24 : afc_in
+ //bit 23:22 : afc_nt
+ //bit 21:20 : vc_in
+ //bit 19:18 : lock_long
+ //bit 17:16 : freq_shift_v
+ //bit 15 : not used.
+ //bit 14:12 : data_sel
+ //bit 10:8 : sdmnc_ulms
+ //bit 6:0 : sdmnc_power
+#define AM_DDR_PLL_STS ((0x0007 << 2) + 0xfe0a0000)
+ //bit 31 : DDR_PLL_LOCK
+ //bit 30 : lock_a
+ //bit 29 : afc_done
+ //bit 22:16 : sdmnc_monitor
+ //bit 9:0 : out_rsv
+#define AM_DDR_CLK_CNTL ((0x0008 << 2) + 0xfe0a0000)
+ //bit 31 Channel 0 ddr_pll_clk enable. enable the clock from DDR_PLL to clock generateion.
+ // whenever change the DDR_PLL frequency, disable the clock, after the DDR_PLL locked, then enable it again.
+ //bit 30. channel 0 ddr_pll_prod_test_en. enable the clock to clock/32 which to clock frequency measurement and production test pin.
+ //bit 29. not used.
+ //bit 28. clock generation logic soft reset_n. 0: reset. 1: normal mode.
+ //bit 27. channel 0 phy_4xclk phase inverter..
+ //bit 25. Channel 0 DDRPHY DfiClk/DfiCtlClk/DMC clock selection. 1: AM_PLL clk output /2. 0: directly output from AM_PLL .
+ //bit 24. Channel 0 AM_PLL CLK output /2 function. 1: enable. 0: disable. if try to use this clkoutput/2 function.
+ //bit 23 Channel 1 ddr_pll_clk enable. enable the clock from DDR_PLL to clock generateion.
+ // whenever change the DDR_PLL frequency, disable the clock, after the DDR_PLL locked, then enable it again.
+ //bit 22. channel 1 ddr_pll_prod_test_en. enable the clock to clock/32 which to clock frequency measurement and production test pin.
+ //bit 21:20. not used.
+ //bit 19. channel 1 phy_4xclk phase inverter..
+ //bit 17. Channel 1 DDRPHY DfiClk/DfiCtlClk/DMC clock selection. 1: AM_PLL clk output /2. 0: directly output from AM_PLL .
+ //bit 16. Channel 1 AM_PLL CLK output /2 function. 1: enable. 0: disable. if try to use this clkoutput/2 function.
+ //bit 12. ddr1 def_clk_sel 1: select reference clock as LPDDR4-PHY clock. 0: normal.
+ //bit 11. ddr1 default clock enable. enable PCLK as LPDDR4_PHY clock. 0: disable.
+ //bit 10. enable ddr channel 1 dmc_clk.
+ //bit 9. enable LPDDR4-PHY channel 1 DfiClk.
+ //bit 8. enable LPDDR4-PHY channel 1 DfiCtlClk.
+ //bit 4. ddr0 def_clk_sel 1: select reference clock as LPDDR4-PHY clock. 0: normal.
+ //bit 3. ddr0 default clock enable. enable PCLK as LPDDR4_PHY clock. 0: disable.
+ //bit 2. enable ddr channel 0 dmc_clk.
+ //bit 1. enable LPDDR4-PHY channel 0 DfiClk.
+ //bit 0. enable LPDDR4-PHY channel 0 DfiCtlClk.
+#define AM_DDR_PHY_CTRL ((0x0009 << 2) + 0xfe0a0000)
+ // LPDDR4 power on reset need to special combination of PwrOkIn and phy_reset_n.
+ // please check the PHY PUB data book for detail.
+ //bit 31:8. Not used.
+ //bit 7. use dmc_clk_freq to control DDR-PHY channel 1 refresh/retrainning/freqency change/phy power etc.
+ //bit 6. use dmc_clk_freq to control DDR-PHY channel 0 refresh/retrainning/freqency change/phy power etc.
+ //bit 5. DDR_PHY 1 PwrOkIn pin.
+ //bit 4. DDR_PHY 0 PwrOkIn pin.
+ //bit 3. DDR_PHY 1 APB soft reset_n.
+ //bit 2. DDR_PHY 1 phy_reset_n.
+ //bit 1. DDR_PHY 0 APB soft reset_n.
+ //bit 0. DDR_PHY 0 phy_reset_n.
+#define AM_DDR_FREQ_CTRL ((0x000c << 2) + 0xfe0a0000)
+ //bit 31. write trigger the DDR frequency change prodeure. read =0 the freqency change done.
+ //bit 30 currunt FREQ selection. it can forced to change to select which freqency to select, or it can auto changed by FREQ change hardware.
+ //bit 29 next freq for frequency change.
+ //bit 23:8. pll_reseve in frequency1. pll_reseve[5:4] used to tune 2 DMC channel clock phase.
+ //bit 6:4 OD1 number in frequency 1.
+ //bit 2:0. OD number in frequency 1.
+#define AM_DDR_TIMING_F0 ((0x000d << 2) + 0xfe0a0000)
+ //freqency 0 auto refresh timing.
+ //bit 7:0. T100ns. how many clock cycle for 100ns.
+ //bit15:8. refresh period in 100ns.
+#define AM_DDR_TIMING_F1 ((0x000e << 2) + 0xfe0a0000)
+ //freqency 1 auto refresh timing.
+ //bit 7:0. T100ns. how many clock cycle for 100ns.
+ //bit15:8. refresh period in 100ns.
+#define AM_DDR_TIMING_CFG ((0x000f << 2) + 0xfe0a0000)
+ //bit 31. cfg ddr timing. write 1 to save the timing parameters to ddr clock domain.
+ //bit 30. dmc_clk_freq control the LPDDR4 retraining.
+ //bit 29. dmc_clk_freq control the auto refresh timing.
+ //bit 28:24. not use.
+ //bit 23:0. lpddr4 phy retraining timer counter in 100ns.
+//
+// Closing file: ../mmc_lp4/dmc_clk_freq/rtl/dmc_clk_freq.vh
+//
+//========================================================================
+// STARTUP
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe02e000
+// -----------------------------------------------
+#define STARTUP_LOCK ((0x0000 << 2) + 0xfe02e000)
+#define STARTUP_DFU_STS ((0x0004 << 2) + 0xfe02e000)
+#define STARTUP_BOOT_SRC ((0x0008 << 2) + 0xfe02e000)
+#define STARTUP_TEE_REQ_DFU ((0x0009 << 2) + 0xfe02e000)
+#define STARTUP_BOOT_OVERRIDE ((0x000a << 2) + 0xfe02e000)
+#define STARTUP_COLD_BOOT_CNT ((0x000b << 2) + 0xfe02e000)
+#define STARTUP_KEY_PRESERVE ((0x000c << 2) + 0xfe02e000)
+//========================================================================
+// MIPI_DSI_PHY
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe014000
+// -----------------------------------------------
+//`define MIPI_DSI_PHY_START 8'h00
+//`define MIPI_DSI_PHY_END 16'hffff
+#define MIPI_DSI_PHY_CTRL ((0x0000 << 2) + 0xfe014000)
+ //bit 31. soft reset for the phy. 1 = reset. 0 = dessert the reset.
+ //bit 30. clock lane soft reset.
+ //bit 29. data byte lane 3 soft reset.
+ //bit 28. data byte lane 2 soft reset.
+ //bit 27. data byte lane 1 soft reset.
+ //bit 26. data byte lane 0 soft reset.
+ //bit 5. LPDT data endian. 1 = transfer the high bit first. 0 : transfer the low bit first.
+ //bit 4. HS data endian.
+ //bit 3. force data byte lane in stop mode.
+ //bit 2. force data byte lane 0 in reciever mode.
+ //bit 1. write 1 to sync the txclkesc input. the internal logic have to use txclkesc to decide Txvalid and Txready.
+ //bit 0. enalbe the MIPI DSI PHY TxDDRClk.
+#define MIPI_DSI_CHAN_CTRL ((0x0001 << 2) + 0xfe014000)
+ //bit 31. clk lane tx_hs_en control selection. 1 = from register. 0 use clk lane state machine.
+ //bit 30. register bit for clock lane tx_hs_en.
+ //bit 29. clk lane tx_lp_en contrl selection. 1 = from register. 0 from clk lane state machine.
+ //bit 28. register bit for clock lane tx_lp_en.
+ //bit 27. chan0 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 26. register bit for chan0 tx_hs_en.
+ //bit 25. chan0 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 24. register bit from chan0 tx_lp_en.
+ //bit 23. chan0 rx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 22. register bit from chan0 rx_lp_en.
+ //bit 21. chan0 contention detection enable control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 20. register bit from chan0 contention dectection enable.
+ //bit 19. chan1 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 18. register bit for chan1 tx_hs_en.
+ //bit 17. chan1 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 16. register bit from chan1 tx_lp_en.
+ //bit 15. chan2 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 14. register bit for chan2 tx_hs_en.
+ //bit 13. chan2 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 12. register bit from chan2 tx_lp_en.
+ //bit 11. chan3 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 10. register bit for chan3 tx_hs_en.
+ //bit 9. chan3 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 8. register bit from chan3 tx_lp_en.
+ //bit 4. clk chan power down. this bit is also used as the power down of the whole MIPI_DSI_PHY.
+ //bit 3. chan3 power down.
+ //bit 2. chan2 power down.
+ //bit 1. chan1 power down.
+ //bit 0. chan0 power down.
+#define MIPI_DSI_CHAN_STS ((0x0002 << 2) + 0xfe014000)
+ //bit 24. chan0 TX->RX turn can't accept the ACK command from slave watch dog triggered. write 1 to clear the status bit.
+ //bit 23. chan0 RX ESC command watch dog triggered. write 1 to clean this bit.
+ //bit
+#define MIPI_DSI_CLK_TIM ((0x0003 << 2) + 0xfe014000)
+ //bit 31:24. TCLK_PREPARE.
+ //bit 23:16. TCLK_ZERO.
+ //bit 15:8. TCLK_POST.
+ //bit 7:0. TCLK_TRAIL.
+#define MIPI_DSI_HS_TIM ((0x0004 << 2) + 0xfe014000)
+ //bit 31:24. THS_PREPARE.
+ //bit 23:16. THS_ZERO.
+ //bit 15:8. THS_TRAIL.
+ //bit 7:0. THS_EXIT.
+#define MIPI_DSI_LP_TIM ((0x0005 << 2) + 0xfe014000)
+ //bit 31:24. tTA_GET.
+ //bit 23:16. tTA_GO.
+ //bit 15:8. tTA_SURE.
+ //bit 7:0. tLPX.
+#define MIPI_DSI_ANA_UP_TIM ((0x0006 << 2) + 0xfe014000)
+ //wait time to MIPI DIS analog ready.
+#define MIPI_DSI_INIT_TIM ((0x0007 << 2) + 0xfe014000)
+ // TINIT.
+#define MIPI_DSI_WAKEUP_TIM ((0x0008 << 2) + 0xfe014000)
+ //TWAKEUP.
+#define MIPI_DSI_LPOK_TIM ((0x0009 << 2) + 0xfe014000)
+ //bit 31:0 when in RxULPS state, RX reciever is in sleep mode.
+ //every MIPI_DSI_ULPS_CHECK period, the reciever would be enabled once, and waiting this timer period to get the stable input.
+#define MIPI_DSI_LP_WCHDOG ((0x000a << 2) + 0xfe014000)
+ //bit 31:0 watch dog timer for MIPI DSI LP receive state.
+#define MIPI_DSI_ANA_CTRL ((0x000b << 2) + 0xfe014000)
+ //bit 31:0 tMBIAS. timer to wait for analog mBIAS voltage stable.
+#define MIPI_DSI_CLK_TIM1 ((0x000c << 2) + 0xfe014000)
+ //bit 31:8 not used.
+ //bit 7:0 tCLK_PRE
+#define MIPI_DSI_TURN_WCHDOG ((0x000d << 2) + 0xfe014000)
+ //bit 31:0 watch dog timer for lane 0 LP turn around waiting time.
+#define MIPI_DSI_ULPS_CHECK ((0x000e << 2) + 0xfe014000)
+ //bit 31:0 when Lane0 in LP recieve state, if the another side sent Low power command, using this timer to enable Tcheck the another size wakeup nor not.
+#define MIPI_DSI_TEST_CTRL0 ((0x000f << 2) + 0xfe014000)
+#define MIPI_DSI_TEST_CTRL1 ((0x0010 << 2) + 0xfe014000)
+//========================================================================
+// MIPI_DSI_PHY B
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe016000
+// -----------------------------------------------
+//`define MIPI_DSI_PHY_START 8'h00
+//`define MIPI_DSI_PHY_END 16'hffff
+#define MIPI_DSI_B_PHY_CTRL ((0x0000 << 2) + 0xfe016000)
+ //bit 31. soft reset for the phy. 1 = reset. 0 = dessert the reset.
+ //bit 30. clock lane soft reset.
+ //bit 29. data byte lane 3 soft reset.
+ //bit 28. data byte lane 2 soft reset.
+ //bit 27. data byte lane 1 soft reset.
+ //bit 26. data byte lane 0 soft reset.
+ //bit 5. LPDT data endian. 1 = transfer the high bit first. 0 : transfer the low bit first.
+ //bit 4. HS data endian.
+ //bit 3. force data byte lane in stop mode.
+ //bit 2. force data byte lane 0 in reciever mode.
+ //bit 1. write 1 to sync the txclkesc input. the internal logic have to use txclkesc to decide Txvalid and Txready.
+ //bit 0. enalbe the MIPI DSI PHY TxDDRClk.
+#define MIPI_DSI_B_CHAN_CTRL ((0x0001 << 2) + 0xfe016000)
+ //bit 31. clk lane tx_hs_en control selection. 1 = from register. 0 use clk lane state machine.
+ //bit 30. register bit for clock lane tx_hs_en.
+ //bit 29. clk lane tx_lp_en contrl selection. 1 = from register. 0 from clk lane state machine.
+ //bit 28. register bit for clock lane tx_lp_en.
+ //bit 27. chan0 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 26. register bit for chan0 tx_hs_en.
+ //bit 25. chan0 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 24. register bit from chan0 tx_lp_en.
+ //bit 23. chan0 rx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 22. register bit from chan0 rx_lp_en.
+ //bit 21. chan0 contention detection enable control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 20. register bit from chan0 contention dectection enable.
+ //bit 19. chan1 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 18. register bit for chan1 tx_hs_en.
+ //bit 17. chan1 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 16. register bit from chan1 tx_lp_en.
+ //bit 15. chan2 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 14. register bit for chan2 tx_hs_en.
+ //bit 13. chan2 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 12. register bit from chan2 tx_lp_en.
+ //bit 11. chan3 tx_hs_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 10. register bit for chan3 tx_hs_en.
+ //bit 9. chan3 tx_lp_en control selection. 1 = from register. 0 from chan0 state machine.
+ //bit 8. register bit from chan3 tx_lp_en.
+ //bit 4. clk chan power down. this bit is also used as the power down of the whole MIPI_DSI_PHY.
+ //bit 3. chan3 power down.
+ //bit 2. chan2 power down.
+ //bit 1. chan1 power down.
+ //bit 0. chan0 power down.
+#define MIPI_DSI_B_CHAN_STS ((0x0002 << 2) + 0xfe016000)
+ //bit 24. chan0 TX->RX turn can't accept the ACK command from slave watch dog triggered. write 1 to clear the status bit.
+ //bit 23. chan0 RX ESC command watch dog triggered. write 1 to clean this bit.
+ //bit
+#define MIPI_DSI_B_CLK_TIM ((0x0003 << 2) + 0xfe016000)
+ //bit 31:24. TCLK_PREPARE.
+ //bit 23:16. TCLK_ZERO.
+ //bit 15:8. TCLK_POST.
+ //bit 7:0. TCLK_TRAIL.
+#define MIPI_DSI_B_HS_TIM ((0x0004 << 2) + 0xfe016000)
+ //bit 31:24. THS_PREPARE.
+ //bit 23:16. THS_ZERO.
+ //bit 15:8. THS_TRAIL.
+ //bit 7:0. THS_EXIT.
+#define MIPI_DSI_B_LP_TIM ((0x0005 << 2) + 0xfe016000)
+ //bit 31:24. tTA_GET.
+ //bit 23:16. tTA_GO.
+ //bit 15:8. tTA_SURE.
+ //bit 7:0. tLPX.
+#define MIPI_DSI_B_ANA_UP_TIM ((0x0006 << 2) + 0xfe016000)
+ //wait time to MIPI DIS analog ready.
+#define MIPI_DSI_B_INIT_TIM ((0x0007 << 2) + 0xfe016000)
+ // TINIT.
+#define MIPI_DSI_B_WAKEUP_TIM ((0x0008 << 2) + 0xfe016000)
+ //TWAKEUP.
+#define MIPI_DSI_B_LPOK_TIM ((0x0009 << 2) + 0xfe016000)
+ //bit 31:0 when in RxULPS state, RX reciever is in sleep mode.
+ //every MIPI_DSI_ULPS_CHECK period, the reciever would be enabled once, and waiting this timer period to get the stable input.
+#define MIPI_DSI_B_LP_WCHDOG ((0x000a << 2) + 0xfe016000)
+ //bit 31:0 watch dog timer for MIPI DSI LP receive state.
+#define MIPI_DSI_B_ANA_CTRL ((0x000b << 2) + 0xfe016000)
+ //bit 31:0 tMBIAS. timer to wait for analog mBIAS voltage stable.
+#define MIPI_DSI_B_CLK_TIM1 ((0x000c << 2) + 0xfe016000)
+ //bit 31:8 not used.
+ //bit 7:0 tCLK_PRE
+#define MIPI_DSI_B_TURN_WCHDOG ((0x000d << 2) + 0xfe016000)
+ //bit 31:0 watch dog timer for lane 0 LP turn around waiting time.
+#define MIPI_DSI_B_ULPS_CHECK ((0x000e << 2) + 0xfe016000)
+ //bit 31:0 when Lane0 in LP recieve state, if the another side sent Low power command, using this timer to enable Tcheck the another size wakeup nor not.
+#define MIPI_DSI_B_TEST_CTRL0 ((0x000f << 2) + 0xfe016000)
+#define MIPI_DSI_B_TEST_CTRL1 ((0x0010 << 2) + 0xfe016000)
+//========================================================================
+// Temp sensor: A73
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe020000
+// -----------------------------------------------
+#define TS_A73_CFG_REG1 ((0x0001 << 2) + 0xfe020000)
+#define TS_A73_CFG_REG2 ((0x0002 << 2) + 0xfe020000)
+#define TS_A73_CFG_REG3 ((0x0003 << 2) + 0xfe020000)
+#define TS_A73_CFG_REG4 ((0x0004 << 2) + 0xfe020000)
+#define TS_A73_CFG_REG5 ((0x0005 << 2) + 0xfe020000)
+#define TS_A73_CFG_REG6 ((0x0006 << 2) + 0xfe020000)
+#define TS_A73_CFG_REG7 ((0x0007 << 2) + 0xfe020000)
+#define TS_A73_STAT0 ((0x0010 << 2) + 0xfe020000)
+#define TS_A73_STAT1 ((0x0011 << 2) + 0xfe020000)
+#define TS_A73_STAT2 ((0x0012 << 2) + 0xfe020000)
+#define TS_A73_STAT3 ((0x0013 << 2) + 0xfe020000)
+#define TS_A73_STAT4 ((0x0014 << 2) + 0xfe020000)
+#define TS_A73_STAT5 ((0x0015 << 2) + 0xfe020000)
+#define TS_A73_STAT6 ((0x0016 << 2) + 0xfe020000)
+#define TS_A73_STAT7 ((0x0017 << 2) + 0xfe020000)
+#define TS_A73_STAT8 ((0x0018 << 2) + 0xfe020000)
+#define TS_A73_STAT9 ((0x0019 << 2) + 0xfe020000)
+//========================================================================
+// Temp sensor: A53
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe022000
+// -----------------------------------------------
+#define TS_A53_CFG_REG1 ((0x0001 << 2) + 0xfe022000)
+#define TS_A53_CFG_REG2 ((0x0002 << 2) + 0xfe022000)
+#define TS_A53_CFG_REG3 ((0x0003 << 2) + 0xfe022000)
+#define TS_A53_CFG_REG4 ((0x0004 << 2) + 0xfe022000)
+#define TS_A53_CFG_REG5 ((0x0005 << 2) + 0xfe022000)
+#define TS_A53_CFG_REG6 ((0x0006 << 2) + 0xfe022000)
+#define TS_A53_CFG_REG7 ((0x0007 << 2) + 0xfe022000)
+#define TS_A53_STAT0 ((0x0010 << 2) + 0xfe022000)
+#define TS_A53_STAT1 ((0x0011 << 2) + 0xfe022000)
+#define TS_A53_STAT2 ((0x0012 << 2) + 0xfe022000)
+#define TS_A53_STAT3 ((0x0013 << 2) + 0xfe022000)
+#define TS_A53_STAT4 ((0x0014 << 2) + 0xfe022000)
+#define TS_A53_STAT5 ((0x0015 << 2) + 0xfe022000)
+#define TS_A53_STAT6 ((0x0016 << 2) + 0xfe022000)
+#define TS_A53_STAT7 ((0x0017 << 2) + 0xfe022000)
+#define TS_A53_STAT8 ((0x0018 << 2) + 0xfe022000)
+#define TS_A53_STAT9 ((0x0019 << 2) + 0xfe022000)
+//========================================================================
+// Temp sensor GPU
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe094000
+// -----------------------------------------------
+#define TS_GPU_CFG_REG1 ((0x0001 << 2) + 0xfe094000)
+#define TS_GPU_CFG_REG2 ((0x0002 << 2) + 0xfe094000)
+#define TS_GPU_CFG_REG3 ((0x0003 << 2) + 0xfe094000)
+#define TS_GPU_CFG_REG4 ((0x0004 << 2) + 0xfe094000)
+#define TS_GPU_CFG_REG5 ((0x0005 << 2) + 0xfe094000)
+#define TS_GPU_CFG_REG6 ((0x0006 << 2) + 0xfe094000)
+#define TS_GPU_CFG_REG7 ((0x0007 << 2) + 0xfe094000)
+#define TS_GPU_STAT0 ((0x0010 << 2) + 0xfe094000)
+#define TS_GPU_STAT1 ((0x0011 << 2) + 0xfe094000)
+#define TS_GPU_STAT2 ((0x0012 << 2) + 0xfe094000)
+#define TS_GPU_STAT3 ((0x0013 << 2) + 0xfe094000)
+#define TS_GPU_STAT4 ((0x0014 << 2) + 0xfe094000)
+#define TS_GPU_STAT5 ((0x0015 << 2) + 0xfe094000)
+#define TS_GPU_STAT6 ((0x0016 << 2) + 0xfe094000)
+#define TS_GPU_STAT7 ((0x0017 << 2) + 0xfe094000)
+#define TS_GPU_STAT8 ((0x0018 << 2) + 0xfe094000)
+#define TS_GPU_STAT9 ((0x0019 << 2) + 0xfe094000)
+//========================================================================
+// Temp sensor NNA
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe096000
+// -----------------------------------------------
+#define TS_NNA_CFG_REG1 ((0x0001 << 2) + 0xfe096000)
+#define TS_NNA_CFG_REG2 ((0x0002 << 2) + 0xfe096000)
+#define TS_NNA_CFG_REG3 ((0x0003 << 2) + 0xfe096000)
+#define TS_NNA_CFG_REG4 ((0x0004 << 2) + 0xfe096000)
+#define TS_NNA_CFG_REG5 ((0x0005 << 2) + 0xfe096000)
+#define TS_NNA_CFG_REG6 ((0x0006 << 2) + 0xfe096000)
+#define TS_NNA_CFG_REG7 ((0x0007 << 2) + 0xfe096000)
+#define TS_NNA_STAT0 ((0x0010 << 2) + 0xfe096000)
+#define TS_NNA_STAT1 ((0x0011 << 2) + 0xfe096000)
+#define TS_NNA_STAT2 ((0x0012 << 2) + 0xfe096000)
+#define TS_NNA_STAT3 ((0x0013 << 2) + 0xfe096000)
+#define TS_NNA_STAT4 ((0x0014 << 2) + 0xfe096000)
+#define TS_NNA_STAT5 ((0x0015 << 2) + 0xfe096000)
+#define TS_NNA_STAT6 ((0x0016 << 2) + 0xfe096000)
+#define TS_NNA_STAT7 ((0x0017 << 2) + 0xfe096000)
+#define TS_NNA_STAT8 ((0x0018 << 2) + 0xfe096000)
+#define TS_NNA_STAT9 ((0x0019 << 2) + 0xfe096000)
+//========================================================================
+// Temp sensor VPU
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe098000
+// -----------------------------------------------
+#define TS_VPU_CFG_REG1 ((0x0001 << 2) + 0xfe098000)
+#define TS_VPU_CFG_REG2 ((0x0002 << 2) + 0xfe098000)
+#define TS_VPU_CFG_REG3 ((0x0003 << 2) + 0xfe098000)
+#define TS_VPU_CFG_REG4 ((0x0004 << 2) + 0xfe098000)
+#define TS_VPU_CFG_REG5 ((0x0005 << 2) + 0xfe098000)
+#define TS_VPU_CFG_REG6 ((0x0006 << 2) + 0xfe098000)
+#define TS_VPU_CFG_REG7 ((0x0007 << 2) + 0xfe098000)
+#define TS_VPU_STAT0 ((0x0010 << 2) + 0xfe098000)
+#define TS_VPU_STAT1 ((0x0011 << 2) + 0xfe098000)
+#define TS_VPU_STAT2 ((0x0012 << 2) + 0xfe098000)
+#define TS_VPU_STAT3 ((0x0013 << 2) + 0xfe098000)
+#define TS_VPU_STAT4 ((0x0014 << 2) + 0xfe098000)
+#define TS_VPU_STAT5 ((0x0015 << 2) + 0xfe098000)
+#define TS_VPU_STAT6 ((0x0016 << 2) + 0xfe098000)
+#define TS_VPU_STAT7 ((0x0017 << 2) + 0xfe098000)
+#define TS_VPU_STAT8 ((0x0018 << 2) + 0xfe098000)
+#define TS_VPU_STAT9 ((0x0019 << 2) + 0xfe098000)
+//========================================================================
+// Temp sensor HEVC
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe09a000
+// -----------------------------------------------
+#define TS_HEVC_CFG_REG1 ((0x0001 << 2) + 0xfe09a000)
+#define TS_HEVC_CFG_REG2 ((0x0002 << 2) + 0xfe09a000)
+#define TS_HEVC_CFG_REG3 ((0x0003 << 2) + 0xfe09a000)
+#define TS_HEVC_CFG_REG4 ((0x0004 << 2) + 0xfe09a000)
+#define TS_HEVC_CFG_REG5 ((0x0005 << 2) + 0xfe09a000)
+#define TS_HEVC_CFG_REG6 ((0x0006 << 2) + 0xfe09a000)
+#define TS_HEVC_CFG_REG7 ((0x0007 << 2) + 0xfe09a000)
+#define TS_HEVC_STAT0 ((0x0010 << 2) + 0xfe09a000)
+#define TS_HEVC_STAT1 ((0x0011 << 2) + 0xfe09a000)
+#define TS_HEVC_STAT2 ((0x0012 << 2) + 0xfe09a000)
+#define TS_HEVC_STAT3 ((0x0013 << 2) + 0xfe09a000)
+#define TS_HEVC_STAT4 ((0x0014 << 2) + 0xfe09a000)
+#define TS_HEVC_STAT5 ((0x0015 << 2) + 0xfe09a000)
+#define TS_HEVC_STAT6 ((0x0016 << 2) + 0xfe09a000)
+#define TS_HEVC_STAT7 ((0x0017 << 2) + 0xfe09a000)
+#define TS_HEVC_STAT8 ((0x0018 << 2) + 0xfe09a000)
+#define TS_HEVC_STAT9 ((0x0019 << 2) + 0xfe09a000)
+//========================================================================
+// RNG
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe034000
+// -----------------------------------------------
+//========================================================================
+// ACODEC
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe01a000
+// -----------------------------------------------
+#define ACODEC_0 ((0x0000 << 2) + 0xfe01a000)
+#define ACODEC_1 ((0x0001 << 2) + 0xfe01a000)
+#define ACODEC_2 ((0x0002 << 2) + 0xfe01a000)
+#define ACODEC_3 ((0x0003 << 2) + 0xfe01a000)
+#define ACODEC_4 ((0x0004 << 2) + 0xfe01a000)
+#define ACODEC_5 ((0x0005 << 2) + 0xfe01a000)
+#define ACODEC_6 ((0x0006 << 2) + 0xfe01a000)
+#define ACODEC_7 ((0x0007 << 2) + 0xfe01a000)
+//========================================================================
+// AML USB PHY A
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe03c000
+// -----------------------------------------------
+#define AMLUSB_A0 ((0x0000 << 2) + 0xfe03c000)
+#define AMLUSB_A1 ((0x0001 << 2) + 0xfe03c000)
+#define AMLUSB_A2 ((0x0002 << 2) + 0xfe03c000)
+#define AMLUSB_A3 ((0x0003 << 2) + 0xfe03c000)
+#define AMLUSB_A4 ((0x0004 << 2) + 0xfe03c000)
+#define AMLUSB_A5 ((0x0005 << 2) + 0xfe03c000)
+#define AMLUSB_A6 ((0x0006 << 2) + 0xfe03c000)
+#define AMLUSB_A7 ((0x0007 << 2) + 0xfe03c000)
+#define AMLUSB_A8 ((0x0008 << 2) + 0xfe03c000)
+#define AMLUSB_A9 ((0x0009 << 2) + 0xfe03c000)
+#define AMLUSB_A10 ((0x000a << 2) + 0xfe03c000)
+#define AMLUSB_A11 ((0x000b << 2) + 0xfe03c000)
+#define AMLUSB_A12 ((0x000c << 2) + 0xfe03c000)
+#define AMLUSB_A13 ((0x000d << 2) + 0xfe03c000)
+#define AMLUSB_A14 ((0x000e << 2) + 0xfe03c000)
+#define AMLUSB_A15 ((0x000f << 2) + 0xfe03c000)
+#define AMLUSB_A16 ((0x0010 << 2) + 0xfe03c000)
+#define AMLUSB_A17 ((0x0011 << 2) + 0xfe03c000)
+#define AMLUSB_A18 ((0x0012 << 2) + 0xfe03c000)
+#define AMLUSB_A19 ((0x0013 << 2) + 0xfe03c000)
+#define AMLUSB_A20 ((0x0014 << 2) + 0xfe03c000)
+#define AMLUSB_A21 ((0x0015 << 2) + 0xfe03c000)
+#define AMLUSB_A22 ((0x0016 << 2) + 0xfe03c000)
+#define AMLUSB_A23 ((0x0017 << 2) + 0xfe03c000)
+#define AMLUSB_A24 ((0x0018 << 2) + 0xfe03c000)
+#define AMLUSB_A25 ((0x0019 << 2) + 0xfe03c000)
+#define AMLUSB_A26 ((0x001a << 2) + 0xfe03c000)
+#define AMLUSB_A27 ((0x001b << 2) + 0xfe03c000)
+#define AMLUSB_A28 ((0x001c << 2) + 0xfe03c000)
+#define AMLUSB_A29 ((0x001d << 2) + 0xfe03c000)
+#define AMLUSB_A30 ((0x001e << 2) + 0xfe03c000)
+#define AMLUSB_A31 ((0x001f << 2) + 0xfe03c000)
+//========================================================================
+// AML USB PHY B
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe03e000
+// -----------------------------------------------
+#define AMLUSB_B0 ((0x0000 << 2) + 0xfe03e000)
+#define AMLUSB_B1 ((0x0001 << 2) + 0xfe03e000)
+#define AMLUSB_B2 ((0x0002 << 2) + 0xfe03e000)
+#define AMLUSB_B3 ((0x0003 << 2) + 0xfe03e000)
+#define AMLUSB_B4 ((0x0004 << 2) + 0xfe03e000)
+#define AMLUSB_B5 ((0x0005 << 2) + 0xfe03e000)
+#define AMLUSB_B6 ((0x0006 << 2) + 0xfe03e000)
+#define AMLUSB_B7 ((0x0007 << 2) + 0xfe03e000)
+#define AMLUSB_B8 ((0x0008 << 2) + 0xfe03e000)
+#define AMLUSB_B9 ((0x0009 << 2) + 0xfe03e000)
+#define AMLUSB_B10 ((0x000a << 2) + 0xfe03e000)
+#define AMLUSB_B11 ((0x000b << 2) + 0xfe03e000)
+#define AMLUSB_B12 ((0x000c << 2) + 0xfe03e000)
+#define AMLUSB_B13 ((0x000d << 2) + 0xfe03e000)
+#define AMLUSB_B14 ((0x000e << 2) + 0xfe03e000)
+#define AMLUSB_B15 ((0x000f << 2) + 0xfe03e000)
+#define AMLUSB_B16 ((0x0010 << 2) + 0xfe03e000)
+#define AMLUSB_B17 ((0x0011 << 2) + 0xfe03e000)
+#define AMLUSB_B18 ((0x0012 << 2) + 0xfe03e000)
+#define AMLUSB_B19 ((0x0013 << 2) + 0xfe03e000)
+#define AMLUSB_B20 ((0x0014 << 2) + 0xfe03e000)
+#define AMLUSB_B21 ((0x0015 << 2) + 0xfe03e000)
+#define AMLUSB_B22 ((0x0016 << 2) + 0xfe03e000)
+#define AMLUSB_B23 ((0x0017 << 2) + 0xfe03e000)
+#define AMLUSB_B24 ((0x0018 << 2) + 0xfe03e000)
+#define AMLUSB_B25 ((0x0019 << 2) + 0xfe03e000)
+#define AMLUSB_B26 ((0x001a << 2) + 0xfe03e000)
+#define AMLUSB_B27 ((0x001b << 2) + 0xfe03e000)
+#define AMLUSB_B28 ((0x001c << 2) + 0xfe03e000)
+#define AMLUSB_B29 ((0x001d << 2) + 0xfe03e000)
+#define AMLUSB_B30 ((0x001e << 2) + 0xfe03e000)
+#define AMLUSB_B31 ((0x001f << 2) + 0xfe03e000)
+//========================================================================
+// PAD_CTRL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe004000
+// -----------------------------------------------
+#define PADCTRL_PIN_MUX_REG0 ((0x0000 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG1 ((0x0001 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG3 ((0x0003 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG4 ((0x0004 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG5 ((0x0005 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG6 ((0x0006 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG7 ((0x0007 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG8 ((0x0008 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REG9 ((0x0009 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGA ((0x000a << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGB ((0x000b << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGC ((0x000c << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGD ((0x000d << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGE ((0x000e << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGF ((0x000f << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGG ((0x0010 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGH ((0x0011 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGI ((0x0012 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGJ ((0x0013 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGK ((0x0014 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGL ((0x0015 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGM ((0x0016 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGN ((0x0017 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGO ((0x0018 << 2) + 0xfe004000)
+#define PADCTRL_PIN_MUX_REGP ((0x0019 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL0 ((0x0020 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL1 ((0x0021 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL2 ((0x0022 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL3 ((0x0023 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL4 ((0x0024 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL5 ((0x0025 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL6 ((0x0026 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_IRQ_CTRL7 ((0x0027 << 2) + 0xfe004000)
+#define PADCTRL_WORLD_SYNC_CTRL0 ((0x0028 << 2) + 0xfe004000)
+#define PADCTRL_GPIO_MSR_CTRL0 ((0x0029 << 2) + 0xfe004000)
+#define PADCTRL_MISC_CTRL0 ((0x002a << 2) + 0xfe004000)
+#define PADCTRL_WD_RSTO_CTRL ((0x002b << 2) + 0xfe004000)
+#define PADCTRL_BL_CTRL ((0x002c << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_I ((0x0030 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_O ((0x0031 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_OEN ((0x0032 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_PULL_EN ((0x0033 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_PULL_UP ((0x0034 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_LOCK ((0x0035 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_PROT ((0x0036 << 2) + 0xfe004000)
+#define PADCTRL_GPIOD_DS ((0x0037 << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_I ((0x0038 << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_O ((0x0039 << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_OEN ((0x003a << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_PULL_EN ((0x003b << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_PULL_UP ((0x003c << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_LOCK ((0x003d << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_PROT ((0x003e << 2) + 0xfe004000)
+#define PADCTRL_GPIOE_DS ((0x003f << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_I ((0x0040 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_O ((0x0041 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_OEN ((0x0042 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_PULL_EN ((0x0043 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_PULL_UP ((0x0044 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_LOCK ((0x0045 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_PROT ((0x0046 << 2) + 0xfe004000)
+#define PADCTRL_GPIOZ_DS ((0x0047 << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_I ((0x0048 << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_O ((0x0049 << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_OEN ((0x004a << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_PULL_EN ((0x004b << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_PULL_UP ((0x004c << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_LOCK ((0x004d << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_PROT ((0x004e << 2) + 0xfe004000)
+#define PADCTRL_GPIOH_DS ((0x004f << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_I ((0x0050 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_O ((0x0051 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_OEN ((0x0052 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_PULL_EN ((0x0053 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_PULL_UP ((0x0054 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_LOCK ((0x0055 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_PROT ((0x0056 << 2) + 0xfe004000)
+#define PADCTRL_GPIOC_DS ((0x0057 << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_I ((0x0058 << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_O ((0x0059 << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_OEN ((0x005a << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_PULL_EN ((0x005b << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_PULL_UP ((0x005c << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_LOCK ((0x005d << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_PROT ((0x005e << 2) + 0xfe004000)
+#define PADCTRL_GPIOB_DS ((0x005f << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_I ((0x0060 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_O ((0x0061 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_OEN ((0x0062 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_PULL_EN ((0x0063 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_PULL_UP ((0x0064 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_LOCK ((0x0065 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_PROT ((0x0066 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_DS ((0x0067 << 2) + 0xfe004000)
+#define PADCTRL_GPIOX_DS_EXT ((0x0068 << 2) + 0xfe004000)
+#define PADCTRL_GPIOT_I ((0x0070 << 2) + 0xfe004000)
+#define PADCTRL_GPIOT_O ((0x0071 << 2) + 0xfe004000)
+#define PADCTRL_GPIOT_OEN ((0x0072 << 2) + 0xfe004000)
+#define PADCTRL_GPIOT_PULL_EN ((0x0073 << 2) + 0xfe004000)
+#define PADCTRL_GPIOT_PULL_UP ((0x0074 << 2) + 0xfe004000)
+#define PADCTRL_GPIOT_LOCK ((0x0075 << 2) + 0xfe004000)
+#define PADCTRL_GPIOT_PROT ((0x0076 << 2) + 0xfe004000)
+#define PADCTRL_GPIOT_DS ((0x0077 << 2) + 0xfe004000)
+#define PADCTRL_GPIOT_DS_EXT ((0x0078 << 2) + 0xfe004000)
+#define PADCTRL_GPIOY_I ((0x0080 << 2) + 0xfe004000)
+#define PADCTRL_GPIOY_O ((0x0081 << 2) + 0xfe004000)
+#define PADCTRL_GPIOY_OEN ((0x0082 << 2) + 0xfe004000)
+#define PADCTRL_GPIOY_PULL_EN ((0x0083 << 2) + 0xfe004000)
+#define PADCTRL_GPIOY_PULL_UP ((0x0084 << 2) + 0xfe004000)
+#define PADCTRL_GPIOY_LOCK ((0x0085 << 2) + 0xfe004000)
+#define PADCTRL_GPIOY_PROT ((0x0086 << 2) + 0xfe004000)
+#define PADCTRL_GPIOY_DS ((0x0087 << 2) + 0xfe004000)
+#define PADCTRL_GPIOY_DS_EXT ((0x0088 << 2) + 0xfe004000)
+#define PADCTRL_GPIOW_I ((0x0090 << 2) + 0xfe004000)
+#define PADCTRL_GPIOW_O ((0x0091 << 2) + 0xfe004000)
+#define PADCTRL_GPIOW_OEN ((0x0092 << 2) + 0xfe004000)
+#define PADCTRL_GPIOW_PULL_EN ((0x0093 << 2) + 0xfe004000)
+#define PADCTRL_GPIOW_PULL_UP ((0x0094 << 2) + 0xfe004000)
+#define PADCTRL_GPIOW_LOCK ((0x0095 << 2) + 0xfe004000)
+#define PADCTRL_GPIOW_PROT ((0x0096 << 2) + 0xfe004000)
+#define PADCTRL_GPIOW_DS ((0x0097 << 2) + 0xfe004000)
+#define PADCTRL_GPIOW_DS_EXT ((0x0098 << 2) + 0xfe004000)
+#define PADCTRL_GPIOM_I ((0x00a0 << 2) + 0xfe004000)
+#define PADCTRL_GPIOM_O ((0x00a1 << 2) + 0xfe004000)
+#define PADCTRL_GPIOM_OEN ((0x00a2 << 2) + 0xfe004000)
+#define PADCTRL_GPIOM_PULL_EN ((0x00a3 << 2) + 0xfe004000)
+#define PADCTRL_GPIOM_PULL_UP ((0x00a4 << 2) + 0xfe004000)
+#define PADCTRL_GPIOM_LOCK ((0x00a5 << 2) + 0xfe004000)
+#define PADCTRL_GPIOM_PROT ((0x00a6 << 2) + 0xfe004000)
+#define PADCTRL_GPIOM_DS ((0x00a7 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_I ((0x00b0 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_O ((0x00b1 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_OEN ((0x00b2 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_PULL_EN ((0x00b3 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_PULL_UP ((0x00b4 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_LOCK ((0x00b5 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_PROT ((0x00b6 << 2) + 0xfe004000)
+#define PADCTRL_TESTN_DS ((0x00b7 << 2) + 0xfe004000)
+#define PADCTRL_LOCK_PIN_MUX0 ((0x00d0 << 2) + 0xfe004000)
+#define PADCTRL_LOCK_PIN_MUX1 ((0x00d1 << 2) + 0xfe004000)
+#define PADCTRL_LOCK_PIN_MUX2 ((0x00d2 << 2) + 0xfe004000)
+#define PADCTRL_LOCK_PIN_MUX3 ((0x00d3 << 2) + 0xfe004000)
+#define PADCTRL_LOCK_PIN_MUX4 ((0x00d4 << 2) + 0xfe004000)
+#define PADCTRL_LOCK_PIN_MUX5 ((0x00d5 << 2) + 0xfe004000)
+#define PADCTRL_LOCK_PIN_MUX6 ((0x00d6 << 2) + 0xfe004000)
+#define PADCTRL_PROT_PIN_MUX0 ((0x00d8 << 2) + 0xfe004000)
+#define PADCTRL_PROT_PIN_MUX1 ((0x00d9 << 2) + 0xfe004000)
+#define PADCTRL_PROT_PIN_MUX2 ((0x00da << 2) + 0xfe004000)
+#define PADCTRL_PROT_PIN_MUX3 ((0x00db << 2) + 0xfe004000)
+#define PADCTRL_PROT_PIN_MUX4 ((0x00dc << 2) + 0xfe004000)
+#define PADCTRL_PROT_PIN_MUX5 ((0x00dd << 2) + 0xfe004000)
+#define PADCTRL_PROT_PIN_MUX6 ((0x00de << 2) + 0xfe004000)
+#define PADCTRL_MUTE_CTRL ((0x00e0 << 2) + 0xfe004000)
+#define PADCTRL_MUTE_TDM_DISA ((0x00e1 << 2) + 0xfe004000)
+#define PADCTRL_DEBUG_SEL ((0x00e2 << 2) + 0xfe004000)
+//========================================================================
+// SYS_CTRL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe010000
+// -----------------------------------------------
+#define SYSCTRL_METAL_REV0 ((0x0000 << 2) + 0xfe010000)
+#define SYSCTRL_METAL_REV1 ((0x0001 << 2) + 0xfe010000)
+#define SYSCTRL_METAL_REV2 ((0x0002 << 2) + 0xfe010000)
+#define SYSCTRL_CHIP_ID ((0x000b << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE1_REG0 ((0x0010 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE1_STICKY_REG0 ((0x0011 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE1_SEC_REG0 ((0x0012 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE1_STICKY_SEC_REG0 ((0x0013 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE_REG0 ((0x0014 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE_REG1 ((0x0015 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE_SEC_REG0 ((0x0016 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE_STICKY_REG0 ((0x0017 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE_STICKY_REG1 ((0x0018 << 2) + 0xfe010000)
+#define SYSCTRL_WRITEONCE_STICKY_SEC_REG0 ((0x0019 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERA_CTRL ((0x0030 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERA ((0x0031 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERB_CTRL ((0x0032 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERB ((0x0033 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERC_CTRL ((0x0034 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERC ((0x0035 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERD_CTRL ((0x0036 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERD ((0x0037 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_TIMERA_CTRL ((0x0038 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_TIMERA ((0x0039 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERE_CTRL ((0x003a << 2) + 0xfe010000)
+#define SYSCTRL_TIMERE ((0x003b << 2) + 0xfe010000)
+#define SYSCTRL_TIMERE_HI ((0x003c << 2) + 0xfe010000)
+#define SYSCTRL_TIMERF_CTRL ((0x003d << 2) + 0xfe010000)
+#define SYSCTRL_TIMERF ((0x003e << 2) + 0xfe010000)
+#define SYSCTRL_TIMERF_HI ((0x003f << 2) + 0xfe010000)
+#define SYSCTRL_TIMERG_CTRL ((0x0040 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERG ((0x0041 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERH_CTRL ((0x0042 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERH ((0x0043 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERI_CTRL ((0x0044 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERI ((0x0045 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERJ_CTRL ((0x0046 << 2) + 0xfe010000)
+#define SYSCTRL_TIMERJ ((0x0047 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_TIMERE_CTRL ((0x0048 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_TIMERE ((0x0049 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_TIMERE_HI ((0x004a << 2) + 0xfe010000)
+#define SYSCTRL_OSC_RING_CTRL0 ((0x0050 << 2) + 0xfe010000)
+#define SYSCTRL_OSC_RING_CTRL1 ((0x0051 << 2) + 0xfe010000)
+#define SYSCTRL_AM2AXI_CTRL0 ((0x0052 << 2) + 0xfe010000)
+#define SYSCTRL_AM2AXI_STS ((0x0053 << 2) + 0xfe010000)
+#define SYSCTRL_AXI_PIPE_CTRL0 ((0x0055 << 2) + 0xfe010000)
+#define SYSCTRL_AXI_PIPE_CTRL1 ((0x0056 << 2) + 0xfe010000)
+#define SYSCTRL_TIMER90K ((0x0057 << 2) + 0xfe010000)
+#define SYSCTRL_SCR ((0x0058 << 2) + 0xfe010000)
+#define SYSCTRL_HPG_TIMER ((0x0059 << 2) + 0xfe010000)
+//`define SYSCTRL_VIPNANOQ_CTRL0 10'h5A
+#define SYSCTRL_AHB2DDR_CTRL0 ((0x005b << 2) + 0xfe010000)
+#define SYSCTRL_AHB2DDR_CTRL1 ((0x005c << 2) + 0xfe010000)
+#define SYSCTRL_POC ((0x0060 << 2) + 0xfe010000)
+#define SYSCTRL_VPU_SECURE_REG0 ((0x0061 << 2) + 0xfe010000)
+#define SYSCTRL_VPU_SECURE_REG1 ((0x0062 << 2) + 0xfe010000)
+#define SYSCTRL_DEWARP_SECURE_REG ((0x0063 << 2) + 0xfe010000)
+//`define SYSCTRL_NIC_CFG0 10'h63
+#define SYSCTRL_ALERT_STS_STICKY ((0x0064 << 2) + 0xfe010000)
+#define SYSCTRL_ALERT_ENABLE ((0x0066 << 2) + 0xfe010000)
+#define SYSCTRL_ENABLE_SPIFC ((0x0068 << 2) + 0xfe010000)
+#define SYSCTRL_OSC_RING_CTRL2 ((0x0069 << 2) + 0xfe010000)
+#define SYSCTRL_AXI_PIPE_CTRL2 ((0x006a << 2) + 0xfe010000)
+#define SYSCTRL_AXI_PIPE_CTRL3 ((0x006b << 2) + 0xfe010000)
+#define SYSCTRL_AXI_PIPE_CTRL4 ((0x006c << 2) + 0xfe010000)
+#define SYSCTRL_AXI_PIPE_CTRL5 ((0x006d << 2) + 0xfe010000)
+#define SYSCTRL_AXI_PIPE_CTRL6 ((0x006e << 2) + 0xfe010000)
+#define SYSCTRL_EDP_TEST_CTRL0 ((0x0070 << 2) + 0xfe010000)
+#define SYSCTRL_EDP_TEST_CTRL1 ((0x0071 << 2) + 0xfe010000)
+#define SYSCTRL_HDMIRXPLL_TEST_CTRL ((0x0072 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG0 ((0x0090 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG1 ((0x0091 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG2 ((0x0092 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG3 ((0x0093 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG4 ((0x0094 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG5 ((0x0095 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG6 ((0x0096 << 2) + 0xfe010000)
+#define SYSCTRL_DEBUG_REG7 ((0x0097 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG0 ((0x00a0 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG1 ((0x00a1 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG2 ((0x00a2 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG3 ((0x00a3 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG4 ((0x00a4 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG5 ((0x00a5 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG6 ((0x00a6 << 2) + 0xfe010000)
+#define SYSCTRL_STATUS_REG7 ((0x00a7 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG0 ((0x00b0 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG1 ((0x00b1 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG2 ((0x00b2 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG3 ((0x00b3 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG4 ((0x00b4 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG5 ((0x00b5 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG6 ((0x00b6 << 2) + 0xfe010000)
+#define SYSCTRL_STICKY_REG7 ((0x00b7 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG0 ((0x00c0 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG1 ((0x00c1 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG2 ((0x00c2 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG3 ((0x00c3 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG4 ((0x00c4 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG5 ((0x00c5 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG6 ((0x00c6 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG7 ((0x00c7 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG8 ((0x00c8 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG9 ((0x00c9 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG10 ((0x00ca << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG11 ((0x00cb << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG12 ((0x00cc << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG13 ((0x00cd << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG14 ((0x00ce << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG15 ((0x00cf << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG16 ((0x00d0 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG17 ((0x00d1 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG18 ((0x00d2 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG19 ((0x00d3 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG20 ((0x00d4 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG21 ((0x00d5 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG22 ((0x00d6 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG23 ((0x00d7 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG24 ((0x00d8 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG25 ((0x00d9 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG26 ((0x00da << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG27 ((0x00db << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG28 ((0x00dc << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG29 ((0x00dd << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG30 ((0x00de << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STATUS_REG31 ((0x00df << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG0 ((0x00e0 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG1 ((0x00e1 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG2 ((0x00e2 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG3 ((0x00e3 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG4 ((0x00e4 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG5 ((0x00e5 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG6 ((0x00e6 << 2) + 0xfe010000)
+#define SYSCTRL_SEC_STICKY_REG7 ((0x00e7 << 2) + 0xfe010000)
+#define SYSCTRL_MSG_INDEX0_STICKY ((0x00f0 << 2) + 0xfe010000)
+#define SYSCTRL_MSG_INDEX1_STICKY ((0x00f1 << 2) + 0xfe010000)
+#define SYSCTRL_MSG_INDEX2_STICKY ((0x00f2 << 2) + 0xfe010000)
+#define SYSCTRL_MSG_INDEX3_STICKY ((0x00f3 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_CFG0 ((0x0100 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_CFG1 ((0x0101 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_CFG2 ((0x0102 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_CFG3 ((0x0103 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_CFG4 ((0x0104 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_CFG5 ((0x0105 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_CFG6 ((0x0106 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_CFG7 ((0x0107 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_CFG8 ((0x0108 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_CFG9 ((0x0109 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_CFG10 ((0x010a << 2) + 0xfe010000)
+#define SYSCTRL_CCI_STS0 ((0x0110 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_STS1 ((0x0111 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_STS2 ((0x0112 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_STS3 ((0x0113 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_STS4 ((0x0114 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_STS5 ((0x0115 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_STS6 ((0x0116 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_STS7 ((0x0117 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_STS8 ((0x0118 << 2) + 0xfe010000)
+#define SYSCTRL_CCI_STS9 ((0x0119 << 2) + 0xfe010000)
+#define SYSCTRL_MALI_CFG0 ((0x0120 << 2) + 0xfe010000)
+#define SYSCTRL_SPICC_CTRL0 ((0x0124 << 2) + 0xfe010000)
+#define SYSCTRL_AXISRAM_CFG0 ((0x0128 << 2) + 0xfe010000)
+#define SYSCTRL_BUS_CFG0 ((0x0130 << 2) + 0xfe010000)
+#define SYSCTRL_BUS_CFG1 ((0x0131 << 2) + 0xfe010000)
+#define SYSCTRL_BUS_CFG2 ((0x0132 << 2) + 0xfe010000)
+#define SYSCTRL_BUS_CFG3 ((0x0133 << 2) + 0xfe010000)
+#define SYSCTRL_BUS_CFG4 ((0x0134 << 2) + 0xfe010000)
+#define SYSCTRL_BUS_CFG5 ((0x0135 << 2) + 0xfe010000)
+#define SYSCTRL_BUS_CFG6 ((0x0136 << 2) + 0xfe010000)
+#define SYSCTRL_BUS_CFG7 ((0x0137 << 2) + 0xfe010000)
+#define SYSCTRL_BUS_CFG8 ((0x0138 << 2) + 0xfe010000)
+#define SYSCTRL_BUS_CFG9 ((0x0139 << 2) + 0xfe010000)
+#define SYSCTRL_BUS_CFG10 ((0x013a << 2) + 0xfe010000)
+#define SYSCTRL_NOC_CFG0 ((0x0140 << 2) + 0xfe010000)
+#define SYSCTRL_NOC_STS0 ((0x0148 << 2) + 0xfe010000)
+#define SYSCTRL_NOC_STS1 ((0x0149 << 2) + 0xfe010000)
+#define SYSCTRL_LOCK_BUS_CFG0 ((0x0150 << 2) + 0xfe010000)
+#define SYSCTRL_LOCK_BUS_CFG1 ((0x0151 << 2) + 0xfe010000)
+#define SYSCTRL_PROT_BUS_CFG0 ((0x0152 << 2) + 0xfe010000)
+#define SYSCTRL_PROT_BUS_CFG1 ((0x0153 << 2) + 0xfe010000)
+//========================================================================
+// CLK_CTRL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe000000
+// -----------------------------------------------
+#define CLKCTRL_OSCIN_CTRL ((0x0001 << 2) + 0xfe000000)
+#define CLKCTRL_RTC_BY_OSCIN_CTRL0 ((0x0002 << 2) + 0xfe000000)
+#define CLKCTRL_RTC_BY_OSCIN_CTRL1 ((0x0003 << 2) + 0xfe000000)
+#define CLKCTRL_RTC_CTRL ((0x0004 << 2) + 0xfe000000)
+#define CLKCTRL_CHECK_CLK_RESULT ((0x0005 << 2) + 0xfe000000)
+#define CLKCTRL_MBIST_ATSPEED_CTRL ((0x0006 << 2) + 0xfe000000)
+#define CLKCTRL_LOCK_BIT_REG0 ((0x0008 << 2) + 0xfe000000)
+#define CLKCTRL_LOCK_BIT_REG1 ((0x0009 << 2) + 0xfe000000)
+#define CLKCTRL_LOCK_BIT_REG2 ((0x000a << 2) + 0xfe000000)
+#define CLKCTRL_LOCK_BIT_REG3 ((0x000b << 2) + 0xfe000000)
+#define CLKCTRL_PROT_BIT_REG0 ((0x000c << 2) + 0xfe000000)
+#define CLKCTRL_PROT_BIT_REG1 ((0x000d << 2) + 0xfe000000)
+#define CLKCTRL_PROT_BIT_REG2 ((0x000e << 2) + 0xfe000000)
+#define CLKCTRL_PROT_BIT_REG3 ((0x000f << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_CTRL0 ((0x0010 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN0_REG0 ((0x0011 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN0_REG1 ((0x0012 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN0_REG2 ((0x0013 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN0_REG3 ((0x0014 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN1_REG0 ((0x0015 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN1_REG1 ((0x0016 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN1_REG2 ((0x0017 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_EN1_REG3 ((0x0018 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_VPU_EN0 ((0x0019 << 2) + 0xfe000000)
+#define CLKCTRL_SYS_CLK_VPU_EN1 ((0x001a << 2) + 0xfe000000)
+#define CLKCTRL_AXI_CLK_CTRL0 ((0x001b << 2) + 0xfe000000)
+#define CLKCTRL_TST_CTRL0 ((0x0020 << 2) + 0xfe000000)
+#define CLKCTRL_TST_CTRL1 ((0x0021 << 2) + 0xfe000000)
+#define CLKCTRL_CECA_CTRL0 ((0x0022 << 2) + 0xfe000000)
+#define CLKCTRL_CECA_CTRL1 ((0x0023 << 2) + 0xfe000000)
+#define CLKCTRL_CECB_CTRL0 ((0x0024 << 2) + 0xfe000000)
+#define CLKCTRL_CECB_CTRL1 ((0x0025 << 2) + 0xfe000000)
+#define CLKCTRL_SC_CLK_CTRL ((0x0026 << 2) + 0xfe000000)
+#define CLKCTRL_DSPA_CLK_CTRL0 ((0x0027 << 2) + 0xfe000000)
+#define CLKCTRL_DSPB_CLK_CTRL0 ((0x0028 << 2) + 0xfe000000)
+#define CLKCTRL_CLK12_24_CTRL ((0x002a << 2) + 0xfe000000)
+#define CLKCTRL_ANAKIN_CLK_CTRL ((0x002b << 2) + 0xfe000000)
+#define CLKCTRL_GDC_CLK_CTRL ((0x002c << 2) + 0xfe000000)
+#define CLKCTRL_AMLGDC_CLK_CTRL ((0x002d << 2) + 0xfe000000)
+#define CLKCTRL_VID_CLK0_CTRL ((0x0030 << 2) + 0xfe000000)
+#define CLKCTRL_VID_CLK0_CTRL2 ((0x0031 << 2) + 0xfe000000)
+#define CLKCTRL_VID_CLK0_DIV ((0x0032 << 2) + 0xfe000000)
+#define CLKCTRL_VIID_CLK0_DIV ((0x0033 << 2) + 0xfe000000)
+#define CLKCTRL_VIID_CLK0_CTRL ((0x0034 << 2) + 0xfe000000)
+#define CLKCTRL_ENC0_HDMI_CLK_CTRL ((0x0035 << 2) + 0xfe000000)
+#define CLKCTRL_ENC2_HDMI_CLK_CTRL ((0x0036 << 2) + 0xfe000000)
+#define CLKCTRL_ENC_HDMI_CLK_CTRL ((0x0037 << 2) + 0xfe000000)
+#define CLKCTRL_HDMI_CLK_CTRL ((0x0038 << 2) + 0xfe000000)
+#define CLKCTRL_VID_PLL_CLK0_DIV ((0x0039 << 2) + 0xfe000000)
+#define CLKCTRL_VPU_CLK_CTRL ((0x003a << 2) + 0xfe000000)
+#define CLKCTRL_VPU_CLKB_CTRL ((0x003b << 2) + 0xfe000000)
+#define CLKCTRL_VPU_CLKC_CTRL ((0x003c << 2) + 0xfe000000)
+#define CLKCTRL_VID_LOCK_CLK_CTRL ((0x003d << 2) + 0xfe000000)
+#define CLKCTRL_VDIN_MEAS_CLK_CTRL ((0x003e << 2) + 0xfe000000)
+#define CLKCTRL_VAPBCLK_CTRL ((0x003f << 2) + 0xfe000000)
+#define CLKCTRL_MIPIDSI_PHY_CLK_CTRL ((0x0041 << 2) + 0xfe000000)
+//`define CLKCTRL_CDAC_CLK_CTRL 10'h42
+#define CLKCTRL_MIPI_CSI_PHY_CLK_CTRL ((0x0043 << 2) + 0xfe000000)
+#define CLKCTRL_MIPI_ISP_CLK_CTRL ((0x0044 << 2) + 0xfe000000)
+#define CLKCTRL_WAVE420L_CLK_CTRL ((0x0045 << 2) + 0xfe000000)
+#define CLKCTRL_WAVE420L_CLK_CTRL2 ((0x0046 << 2) + 0xfe000000)
+#define CLKCTRL_HTX_CLK_CTRL0 ((0x0047 << 2) + 0xfe000000)
+#define CLKCTRL_HTX_CLK_CTRL1 ((0x0048 << 2) + 0xfe000000)
+#define CLKCTRL_HRX_CLK_CTRL0 ((0x004a << 2) + 0xfe000000)
+#define CLKCTRL_HRX_CLK_CTRL1 ((0x004b << 2) + 0xfe000000)
+#define CLKCTRL_HRX_CLK_CTRL2 ((0x004c << 2) + 0xfe000000)
+#define CLKCTRL_HRX_CLK_CTRL3 ((0x004d << 2) + 0xfe000000)
+#define CLKCTRL_VDEC_CLK_CTRL ((0x0050 << 2) + 0xfe000000)
+#define CLKCTRL_VDEC2_CLK_CTRL ((0x0051 << 2) + 0xfe000000)
+#define CLKCTRL_VDEC3_CLK_CTRL ((0x0052 << 2) + 0xfe000000)
+#define CLKCTRL_VDEC4_CLK_CTRL ((0x0053 << 2) + 0xfe000000)
+#define CLKCTRL_WAVE521_CLK_CTRL ((0x0054 << 2) + 0xfe000000)
+#define CLKCTRL_WAVE521_CLK_CTRL2 ((0x0055 << 2) + 0xfe000000)
+#define CLKCTRL_TS_CLK_CTRL ((0x0056 << 2) + 0xfe000000)
+#define CLKCTRL_MALI_CLK_CTRL ((0x0057 << 2) + 0xfe000000)
+#define CLKCTRL_VIPNANOQ_CLK_CTRL ((0x0058 << 2) + 0xfe000000)
+#define CLKCTRL_ETH_CLK_CTRL ((0x0059 << 2) + 0xfe000000)
+#define CLKCTRL_NAND_CLK_CTRL ((0x005a << 2) + 0xfe000000)
+#define CLKCTRL_SD_EMMC_CLK_CTRL ((0x005b << 2) + 0xfe000000)
+#define CLKCTRL_BT656_CLK_CTRL ((0x005c << 2) + 0xfe000000)
+#define CLKCTRL_SPICC_CLK_CTRL ((0x005d << 2) + 0xfe000000)
+#define CLKCTRL_GEN_CLK_CTRL ((0x005e << 2) + 0xfe000000)
+#define CLKCTRL_SAR_CLK_CTRL0 ((0x005f << 2) + 0xfe000000)
+#define CLKCTRL_PWM_CLK_AB_CTRL ((0x0060 << 2) + 0xfe000000)
+#define CLKCTRL_PWM_CLK_CD_CTRL ((0x0061 << 2) + 0xfe000000)
+#define CLKCTRL_PWM_CLK_EF_CTRL ((0x0062 << 2) + 0xfe000000)
+//`define CLKCTRL_PWM_CLK_GH_CTRL 10'h63
+//`define CLKCTRL_PWM_CLK_IJ_CTRL 10'h64
+#define CLKCTRL_PWM_CLK_AO_AB_CTRL ((0x0068 << 2) + 0xfe000000)
+#define CLKCTRL_PWM_CLK_AO_CD_CTRL ((0x0069 << 2) + 0xfe000000)
+#define CLKCTRL_PWM_CLK_AO_EF_CTRL ((0x006a << 2) + 0xfe000000)
+#define CLKCTRL_PWM_CLK_AO_GH_CTRL ((0x006b << 2) + 0xfe000000)
+#define CLKCTRL_SPICC_CLK_CTRL1 ((0x0070 << 2) + 0xfe000000)
+#define CLKCTRL_SPICC_CLK_CTRL2 ((0x0071 << 2) + 0xfe000000)
+//`define CLKCTRL_SPICC_CLK_CTRL3 10'h72
+#define CLKCTRL_VID_CLK1_CTRL ((0x0073 << 2) + 0xfe000000)
+#define CLKCTRL_VID_CLK1_CTRL2 ((0x0074 << 2) + 0xfe000000)
+#define CLKCTRL_VID_CLK1_DIV ((0x0075 << 2) + 0xfe000000)
+#define CLKCTRL_VIID_CLK1_DIV ((0x0076 << 2) + 0xfe000000)
+#define CLKCTRL_VIID_CLK1_CTRL ((0x0077 << 2) + 0xfe000000)
+#define CLKCTRL_VID_CLK2_CTRL ((0x0078 << 2) + 0xfe000000)
+#define CLKCTRL_VID_CLK2_CTRL2 ((0x0079 << 2) + 0xfe000000)
+#define CLKCTRL_VID_CLK2_DIV ((0x007a << 2) + 0xfe000000)
+#define CLKCTRL_VIID_CLK2_DIV ((0x007b << 2) + 0xfe000000)
+#define CLKCTRL_VIID_CLK2_CTRL ((0x007c << 2) + 0xfe000000)
+#define CLKCTRL_VID_PLL_CLK1_DIV ((0x007d << 2) + 0xfe000000)
+#define CLKCTRL_VID_PLL_CLK2_DIV ((0x007e << 2) + 0xfe000000)
+#define CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL ((0x0080 << 2) + 0xfe000000)
+#define CLKCTRL_TIMESTAMP_CTRL ((0x0100 << 2) + 0xfe000000)
+#define CLKCTRL_TIMESTAMP_CTRL1 ((0x0101 << 2) + 0xfe000000)
+#define CLKCTRL_TIMESTAMP_CTRL2 ((0x0103 << 2) + 0xfe000000)
+#define CLKCTRL_TIMESTAMP_RD0 ((0x0104 << 2) + 0xfe000000)
+#define CLKCTRL_TIMESTAMP_RD1 ((0x0105 << 2) + 0xfe000000)
+#define CLKCTRL_TIMEBASE_CTRL0 ((0x0106 << 2) + 0xfe000000)
+#define CLKCTRL_TIMEBASE_CTRL1 ((0x0107 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_CPU_CFG01 ((0x0120 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_CPU_CFG2 ((0x0121 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_ENCP_CFG0 ((0x0122 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_MALI_CFG01 ((0x0123 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_HEVCB_CFG01 ((0x0124 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_HEVCB_CFG2 ((0x0125 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_LOCK ((0x0126 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_A73_CFG01 ((0x0127 << 2) + 0xfe000000)
+#define CLKCTRL_EFUSE_A73_CFG2 ((0x0128 << 2) + 0xfe000000)
+//========================================================================
+// PWR_CTRL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe00c000
+// -----------------------------------------------
+#define PWRCTRL_PWR_ACK0 ((0x0000 << 2) + 0xfe00c000)
+#define PWRCTRL_PWR_ACK1 ((0x0001 << 2) + 0xfe00c000)
+#define PWRCTRL_PWR_OFF0 ((0x0004 << 2) + 0xfe00c000)
+#define PWRCTRL_PWR_OFF1 ((0x0005 << 2) + 0xfe00c000)
+#define PWRCTRL_ISO_EN0 ((0x0008 << 2) + 0xfe00c000)
+#define PWRCTRL_ISO_EN1 ((0x0009 << 2) + 0xfe00c000)
+#define PWRCTRL_FOCRST0 ((0x000c << 2) + 0xfe00c000)
+#define PWRCTRL_FOCRST1 ((0x000d << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD0 ((0x0010 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD1 ((0x0011 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD2 ((0x0012 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD3 ((0x0013 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD4 ((0x0014 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD5 ((0x0015 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD6 ((0x0016 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD7 ((0x0017 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD8 ((0x0018 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD9 ((0x0019 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD10 ((0x001a << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD11 ((0x001b << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD12 ((0x001c << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD13 ((0x001d << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD14 ((0x001e << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD15 ((0x001f << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD16 ((0x0020 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD17 ((0x0021 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD18 ((0x0022 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD19 ((0x0023 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD20 ((0x0024 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD21 ((0x0025 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD22 ((0x0026 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD23 ((0x0027 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD24 ((0x0028 << 2) + 0xfe00c000)
+#define PWRCTRL_MEM_PD25 ((0x0029 << 2) + 0xfe00c000)
+#define PWRCTRL_IRQ_EN ((0x0030 << 2) + 0xfe00c000)
+#define PWRCTRL_IRQ_STS ((0x0031 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL0 ((0x0040 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL1 ((0x0041 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL2 ((0x0042 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL3 ((0x0043 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL4 ((0x0044 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_AUTO_OFF_CTRL5 ((0x0045 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_TIMER_TH_01 ((0x0048 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_TIMER_TH_23 ((0x0049 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_TIMER_TH_45 ((0x004a << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_TIMER_TH_67 ((0x004b << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_TIMER_TH_89 ((0x004c << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK0 ((0x0050 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK1 ((0x0051 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK2 ((0x0052 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK3 ((0x0053 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK4 ((0x0054 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK5 ((0x0055 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK6 ((0x0056 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK7 ((0x0057 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK8 ((0x0058 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK9 ((0x0059 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK10 ((0x005a << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK11 ((0x005b << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK12 ((0x005c << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK13 ((0x005d << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK14 ((0x005e << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_IRQ_MASK15 ((0x005f << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_INIT_SET ((0x0060 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_OFF_SET ((0x0061 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_ON_A_SET ((0x0062 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_ON_B_SET ((0x0063 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_ON_C_SET ((0x0064 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_ON_D_SET ((0x0065 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_MEMPD_STS ((0x0066 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_FSM_STS0 ((0x0067 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_FSM_STS1 ((0x0068 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_FSM_STS2 ((0x0069 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_FSM_START_OFF ((0x006d << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_FSM_START_ON ((0x006e << 2) + 0xfe00c000)
+#define PWRCTRL_CPU0_FSM_JUMP ((0x006f << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL0 ((0x0070 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL1 ((0x0071 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL2 ((0x0072 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL3 ((0x0073 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL4 ((0x0074 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_AUTO_OFF_CTRL5 ((0x0075 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_TIMER_TH_01 ((0x0078 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_TIMER_TH_23 ((0x0079 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_TIMER_TH_45 ((0x007a << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_TIMER_TH_67 ((0x007b << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_TIMER_TH_89 ((0x007c << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK0 ((0x0080 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK1 ((0x0081 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK2 ((0x0082 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK3 ((0x0083 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK4 ((0x0084 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK5 ((0x0085 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK6 ((0x0086 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK7 ((0x0087 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK8 ((0x0088 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK9 ((0x0089 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK10 ((0x008a << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK11 ((0x008b << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK12 ((0x008c << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK13 ((0x008d << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK14 ((0x008e << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_IRQ_MASK15 ((0x008f << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_INIT_SET ((0x0090 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_OFF_SET ((0x0091 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_ON_A_SET ((0x0092 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_ON_B_SET ((0x0093 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_ON_C_SET ((0x0094 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_ON_D_SET ((0x0095 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_MEMPD_STS ((0x0096 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_FSM_STS0 ((0x0097 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_FSM_STS1 ((0x0098 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_FSM_STS2 ((0x0099 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_FSM_START_OFF ((0x009d << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_FSM_START_ON ((0x009e << 2) + 0xfe00c000)
+#define PWRCTRL_CPU1_FSM_JUMP ((0x009f << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL0 ((0x00a0 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL1 ((0x00a1 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL2 ((0x00a2 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL3 ((0x00a3 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL4 ((0x00a4 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_AUTO_OFF_CTRL5 ((0x00a5 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_TIMER_TH_01 ((0x00a8 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_TIMER_TH_23 ((0x00a9 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_TIMER_TH_45 ((0x00aa << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_TIMER_TH_67 ((0x00ab << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_TIMER_TH_89 ((0x00ac << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK0 ((0x00b0 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK1 ((0x00b1 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK2 ((0x00b2 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK3 ((0x00b3 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK4 ((0x00b4 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK5 ((0x00b5 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK6 ((0x00b6 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK7 ((0x00b7 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK8 ((0x00b8 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK9 ((0x00b9 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK10 ((0x00ba << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK11 ((0x00bb << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK12 ((0x00bc << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK13 ((0x00bd << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK14 ((0x00be << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_IRQ_MASK15 ((0x00bf << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_INIT_SET ((0x00c0 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_OFF_SET ((0x00c1 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_ON_A_SET ((0x00c2 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_ON_B_SET ((0x00c3 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_ON_C_SET ((0x00c4 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_ON_D_SET ((0x00c5 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_MEMPD_STS ((0x00c6 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_FSM_STS0 ((0x00c7 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_FSM_STS1 ((0x00c8 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_FSM_STS2 ((0x00c9 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_FSM_START_OFF ((0x00cd << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_FSM_START_ON ((0x00ce << 2) + 0xfe00c000)
+#define PWRCTRL_CPU2_FSM_JUMP ((0x00cf << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL0 ((0x00d0 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL1 ((0x00d1 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL2 ((0x00d2 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL3 ((0x00d3 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL4 ((0x00d4 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_AUTO_OFF_CTRL5 ((0x00d5 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_TIMER_TH_01 ((0x00d8 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_TIMER_TH_23 ((0x00d9 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_TIMER_TH_45 ((0x00da << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_TIMER_TH_67 ((0x00db << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_TIMER_TH_89 ((0x00dc << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK0 ((0x00e0 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK1 ((0x00e1 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK2 ((0x00e2 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK3 ((0x00e3 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK4 ((0x00e4 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK5 ((0x00e5 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK6 ((0x00e6 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK7 ((0x00e7 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK8 ((0x00e8 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK9 ((0x00e9 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK10 ((0x00ea << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK11 ((0x00eb << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK12 ((0x00ec << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK13 ((0x00ed << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK14 ((0x00ee << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_IRQ_MASK15 ((0x00ef << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_INIT_SET ((0x00f0 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_OFF_SET ((0x00f1 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_ON_A_SET ((0x00f2 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_ON_B_SET ((0x00f3 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_ON_C_SET ((0x00f4 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_ON_D_SET ((0x00f5 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_MEMPD_STS ((0x00f6 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_FSM_STS0 ((0x00f7 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_FSM_STS1 ((0x00f8 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_FSM_STS2 ((0x00f9 << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_FSM_START_OFF ((0x00fd << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_FSM_START_ON ((0x00fe << 2) + 0xfe00c000)
+#define PWRCTRL_CPU3_FSM_JUMP ((0x00ff << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL0 ((0x0100 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL1 ((0x0101 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL2 ((0x0102 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL3 ((0x0103 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL4 ((0x0104 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_AUTO_OFF_CTRL5 ((0x0105 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_TIMER_TH_01 ((0x0108 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_TIMER_TH_23 ((0x0109 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_TIMER_TH_45 ((0x010a << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_TIMER_TH_67 ((0x010b << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_TIMER_TH_89 ((0x010c << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK0 ((0x0110 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK1 ((0x0111 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK2 ((0x0112 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK3 ((0x0113 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK4 ((0x0114 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK5 ((0x0115 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK6 ((0x0116 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK7 ((0x0117 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK8 ((0x0118 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK9 ((0x0119 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK10 ((0x011a << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK11 ((0x011b << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK12 ((0x011c << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK13 ((0x011d << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK14 ((0x011e << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_IRQ_MASK15 ((0x011f << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_INIT_SET ((0x0120 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_OFF_SET ((0x0121 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_ON_A_SET ((0x0122 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_ON_B_SET ((0x0123 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_ON_C_SET ((0x0124 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_ON_D_SET ((0x0125 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_MEMPD_STS ((0x0126 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_FSM_STS0 ((0x0127 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_FSM_STS1 ((0x0128 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_FSM_STS2 ((0x0129 << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_FSM_START_OFF ((0x012d << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_FSM_START_ON ((0x012e << 2) + 0xfe00c000)
+#define PWRCTRL_CPUTOP_FSM_JUMP ((0x012f << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL0 ((0x0130 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL1 ((0x0131 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL2 ((0x0132 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL3 ((0x0133 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL4 ((0x0134 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_AUTO_OFF_CTRL5 ((0x0135 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_TIMER_TH_01 ((0x0138 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_TIMER_TH_23 ((0x0139 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_TIMER_TH_45 ((0x013a << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_TIMER_TH_67 ((0x013b << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_TIMER_TH_89 ((0x013c << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK0 ((0x0140 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK1 ((0x0141 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK2 ((0x0142 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK3 ((0x0143 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK4 ((0x0144 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK5 ((0x0145 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK6 ((0x0146 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK7 ((0x0147 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK8 ((0x0148 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK9 ((0x0149 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK10 ((0x014a << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK11 ((0x014b << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK12 ((0x014c << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK13 ((0x014d << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK14 ((0x014e << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_IRQ_MASK15 ((0x014f << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_INIT_SET ((0x0150 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_OFF_SET ((0x0151 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_ON_A_SET ((0x0152 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_ON_B_SET ((0x0153 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_ON_C_SET ((0x0154 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_ON_D_SET ((0x0155 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_MEMPD_STS ((0x0156 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_FSM_STS0 ((0x0157 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_FSM_STS1 ((0x0158 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_FSM_STS2 ((0x0159 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_FSM_START_OFF ((0x015d << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_FSM_START_ON ((0x015e << 2) + 0xfe00c000)
+#define PWRCTRL_DSPA_FSM_JUMP ((0x015f << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL0 ((0x0160 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL1 ((0x0161 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL2 ((0x0162 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL3 ((0x0163 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL4 ((0x0164 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_AUTO_OFF_CTRL5 ((0x0165 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_TIMER_TH_01 ((0x0168 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_TIMER_TH_23 ((0x0169 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_TIMER_TH_45 ((0x016a << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_TIMER_TH_67 ((0x016b << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_TIMER_TH_89 ((0x016c << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK0 ((0x0170 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK1 ((0x0171 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK2 ((0x0172 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK3 ((0x0173 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK4 ((0x0174 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK5 ((0x0175 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK6 ((0x0176 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK7 ((0x0177 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK8 ((0x0178 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK9 ((0x0179 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK10 ((0x017a << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK11 ((0x017b << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK12 ((0x017c << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK13 ((0x017d << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK14 ((0x017e << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_IRQ_MASK15 ((0x017f << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_INIT_SET ((0x0180 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_OFF_SET ((0x0181 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_ON_A_SET ((0x0182 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_ON_B_SET ((0x0183 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_ON_C_SET ((0x0184 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_ON_D_SET ((0x0185 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_MEMPD_STS ((0x0186 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_FSM_STS0 ((0x0187 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_FSM_STS1 ((0x0188 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_FSM_STS2 ((0x0189 << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_FSM_START_OFF ((0x018d << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_FSM_START_ON ((0x018e << 2) + 0xfe00c000)
+#define PWRCTRL_DSPB_FSM_JUMP ((0x018f << 2) + 0xfe00c000)
+#define PWRCTRL_A730_AUTO_OFF_CTRL0 ((0x0190 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_AUTO_OFF_CTRL1 ((0x0191 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_AUTO_OFF_CTRL2 ((0x0192 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_AUTO_OFF_CTRL3 ((0x0193 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_AUTO_OFF_CTRL4 ((0x0194 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_AUTO_OFF_CTRL5 ((0x0195 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_TIMER_TH_01 ((0x0198 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_TIMER_TH_23 ((0x0199 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_TIMER_TH_45 ((0x019a << 2) + 0xfe00c000)
+#define PWRCTRL_A730_TIMER_TH_67 ((0x019b << 2) + 0xfe00c000)
+#define PWRCTRL_A730_TIMER_TH_89 ((0x019c << 2) + 0xfe00c000)
+#define PWRCTRL_A730_IRQ_MASK0 ((0x01a0 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_IRQ_MASK1 ((0x01a1 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_IRQ_MASK2 ((0x01a2 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_IRQ_MASK3 ((0x01a3 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_IRQ_MASK4 ((0x01a4 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_IRQ_MASK5 ((0x01a5 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_IRQ_MASK6 ((0x01a6 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_IRQ_MASK7 ((0x01a7 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_IRQ_MASK8 ((0x01a8 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_IRQ_MASK9 ((0x01a9 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_IRQ_MASK10 ((0x01aa << 2) + 0xfe00c000)
+#define PWRCTRL_A730_IRQ_MASK11 ((0x01ab << 2) + 0xfe00c000)
+#define PWRCTRL_A730_IRQ_MASK12 ((0x01ac << 2) + 0xfe00c000)
+#define PWRCTRL_A730_IRQ_MASK13 ((0x01ad << 2) + 0xfe00c000)
+#define PWRCTRL_A730_IRQ_MASK14 ((0x01ae << 2) + 0xfe00c000)
+#define PWRCTRL_A730_IRQ_MASK15 ((0x01af << 2) + 0xfe00c000)
+#define PWRCTRL_A730_MEMPD_INIT_SET ((0x01b0 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_MEMPD_OFF_SET ((0x01b1 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_MEMPD_ON_A_SET ((0x01b2 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_MEMPD_ON_B_SET ((0x01b3 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_MEMPD_ON_C_SET ((0x01b4 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_MEMPD_ON_D_SET ((0x01b5 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_MEMPD_STS ((0x01b6 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_FSM_STS0 ((0x01b7 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_FSM_STS1 ((0x01b8 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_FSM_STS2 ((0x01b9 << 2) + 0xfe00c000)
+#define PWRCTRL_A730_FSM_START_OFF ((0x01bd << 2) + 0xfe00c000)
+#define PWRCTRL_A730_FSM_START_ON ((0x01be << 2) + 0xfe00c000)
+#define PWRCTRL_A730_FSM_JUMP ((0x01bf << 2) + 0xfe00c000)
+#define PWRCTRL_A731_AUTO_OFF_CTRL0 ((0x01c0 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_AUTO_OFF_CTRL1 ((0x01c1 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_AUTO_OFF_CTRL2 ((0x01c2 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_AUTO_OFF_CTRL3 ((0x01c3 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_AUTO_OFF_CTRL4 ((0x01c4 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_AUTO_OFF_CTRL5 ((0x01c5 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_TIMER_TH_01 ((0x01c8 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_TIMER_TH_23 ((0x01c9 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_TIMER_TH_45 ((0x01ca << 2) + 0xfe00c000)
+#define PWRCTRL_A731_TIMER_TH_67 ((0x01cb << 2) + 0xfe00c000)
+#define PWRCTRL_A731_TIMER_TH_89 ((0x01cc << 2) + 0xfe00c000)
+#define PWRCTRL_A731_IRQ_MASK0 ((0x01d0 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_IRQ_MASK1 ((0x01d1 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_IRQ_MASK2 ((0x01d2 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_IRQ_MASK3 ((0x01d3 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_IRQ_MASK4 ((0x01d4 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_IRQ_MASK5 ((0x01d5 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_IRQ_MASK6 ((0x01d6 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_IRQ_MASK7 ((0x01d7 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_IRQ_MASK8 ((0x01d8 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_IRQ_MASK9 ((0x01d9 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_IRQ_MASK10 ((0x01da << 2) + 0xfe00c000)
+#define PWRCTRL_A731_IRQ_MASK11 ((0x01db << 2) + 0xfe00c000)
+#define PWRCTRL_A731_IRQ_MASK12 ((0x01dc << 2) + 0xfe00c000)
+#define PWRCTRL_A731_IRQ_MASK13 ((0x01dd << 2) + 0xfe00c000)
+#define PWRCTRL_A731_IRQ_MASK14 ((0x01de << 2) + 0xfe00c000)
+#define PWRCTRL_A731_IRQ_MASK15 ((0x01df << 2) + 0xfe00c000)
+#define PWRCTRL_A731_MEMPD_INIT_SET ((0x01e0 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_MEMPD_OFF_SET ((0x01e1 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_MEMPD_ON_A_SET ((0x01e2 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_MEMPD_ON_B_SET ((0x01e3 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_MEMPD_ON_C_SET ((0x01e4 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_MEMPD_ON_D_SET ((0x01e5 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_MEMPD_STS ((0x01e6 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_FSM_STS0 ((0x01e7 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_FSM_STS1 ((0x01e8 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_FSM_STS2 ((0x01e9 << 2) + 0xfe00c000)
+#define PWRCTRL_A731_FSM_START_OFF ((0x01ed << 2) + 0xfe00c000)
+#define PWRCTRL_A731_FSM_START_ON ((0x01ee << 2) + 0xfe00c000)
+#define PWRCTRL_A731_FSM_JUMP ((0x01ef << 2) + 0xfe00c000)
+#define PWRCTRL_A732_AUTO_OFF_CTRL0 ((0x01f0 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_AUTO_OFF_CTRL1 ((0x01f1 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_AUTO_OFF_CTRL2 ((0x01f2 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_AUTO_OFF_CTRL3 ((0x01f3 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_AUTO_OFF_CTRL4 ((0x01f4 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_AUTO_OFF_CTRL5 ((0x01f5 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_TIMER_TH_01 ((0x01f8 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_TIMER_TH_23 ((0x01f9 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_TIMER_TH_45 ((0x01fa << 2) + 0xfe00c000)
+#define PWRCTRL_A732_TIMER_TH_67 ((0x01fb << 2) + 0xfe00c000)
+#define PWRCTRL_A732_TIMER_TH_89 ((0x01fc << 2) + 0xfe00c000)
+#define PWRCTRL_A732_IRQ_MASK0 ((0x0200 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_IRQ_MASK1 ((0x0201 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_IRQ_MASK2 ((0x0202 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_IRQ_MASK3 ((0x0203 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_IRQ_MASK4 ((0x0204 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_IRQ_MASK5 ((0x0205 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_IRQ_MASK6 ((0x0206 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_IRQ_MASK7 ((0x0207 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_IRQ_MASK8 ((0x0208 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_IRQ_MASK9 ((0x0209 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_IRQ_MASK10 ((0x020a << 2) + 0xfe00c000)
+#define PWRCTRL_A732_IRQ_MASK11 ((0x020b << 2) + 0xfe00c000)
+#define PWRCTRL_A732_IRQ_MASK12 ((0x020c << 2) + 0xfe00c000)
+#define PWRCTRL_A732_IRQ_MASK13 ((0x020d << 2) + 0xfe00c000)
+#define PWRCTRL_A732_IRQ_MASK14 ((0x020e << 2) + 0xfe00c000)
+#define PWRCTRL_A732_IRQ_MASK15 ((0x020f << 2) + 0xfe00c000)
+#define PWRCTRL_A732_MEMPD_INIT_SET ((0x0210 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_MEMPD_OFF_SET ((0x0211 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_MEMPD_ON_A_SET ((0x0212 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_MEMPD_ON_B_SET ((0x0213 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_MEMPD_ON_C_SET ((0x0214 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_MEMPD_ON_D_SET ((0x0215 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_MEMPD_STS ((0x0216 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_FSM_STS0 ((0x0217 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_FSM_STS1 ((0x0218 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_FSM_STS2 ((0x0219 << 2) + 0xfe00c000)
+#define PWRCTRL_A732_FSM_START_OFF ((0x021d << 2) + 0xfe00c000)
+#define PWRCTRL_A732_FSM_START_ON ((0x021e << 2) + 0xfe00c000)
+#define PWRCTRL_A732_FSM_JUMP ((0x021f << 2) + 0xfe00c000)
+#define PWRCTRL_A733_AUTO_OFF_CTRL0 ((0x0220 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_AUTO_OFF_CTRL1 ((0x0221 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_AUTO_OFF_CTRL2 ((0x0222 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_AUTO_OFF_CTRL3 ((0x0223 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_AUTO_OFF_CTRL4 ((0x0224 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_AUTO_OFF_CTRL5 ((0x0225 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_TIMER_TH_01 ((0x0228 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_TIMER_TH_23 ((0x0229 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_TIMER_TH_45 ((0x022a << 2) + 0xfe00c000)
+#define PWRCTRL_A733_TIMER_TH_67 ((0x022b << 2) + 0xfe00c000)
+#define PWRCTRL_A733_TIMER_TH_89 ((0x022c << 2) + 0xfe00c000)
+#define PWRCTRL_A733_IRQ_MASK0 ((0x0230 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_IRQ_MASK1 ((0x0231 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_IRQ_MASK2 ((0x0232 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_IRQ_MASK3 ((0x0233 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_IRQ_MASK4 ((0x0234 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_IRQ_MASK5 ((0x0235 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_IRQ_MASK6 ((0x0236 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_IRQ_MASK7 ((0x0237 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_IRQ_MASK8 ((0x0238 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_IRQ_MASK9 ((0x0239 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_IRQ_MASK10 ((0x023a << 2) + 0xfe00c000)
+#define PWRCTRL_A733_IRQ_MASK11 ((0x023b << 2) + 0xfe00c000)
+#define PWRCTRL_A733_IRQ_MASK12 ((0x023c << 2) + 0xfe00c000)
+#define PWRCTRL_A733_IRQ_MASK13 ((0x023d << 2) + 0xfe00c000)
+#define PWRCTRL_A733_IRQ_MASK14 ((0x023e << 2) + 0xfe00c000)
+#define PWRCTRL_A733_IRQ_MASK15 ((0x023f << 2) + 0xfe00c000)
+#define PWRCTRL_A733_MEMPD_INIT_SET ((0x0240 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_MEMPD_OFF_SET ((0x0241 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_MEMPD_ON_A_SET ((0x0242 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_MEMPD_ON_B_SET ((0x0243 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_MEMPD_ON_C_SET ((0x0244 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_MEMPD_ON_D_SET ((0x0245 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_MEMPD_STS ((0x0246 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_FSM_STS0 ((0x0247 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_FSM_STS1 ((0x0248 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_FSM_STS2 ((0x0249 << 2) + 0xfe00c000)
+#define PWRCTRL_A733_FSM_START_OFF ((0x024d << 2) + 0xfe00c000)
+#define PWRCTRL_A733_FSM_START_ON ((0x024e << 2) + 0xfe00c000)
+#define PWRCTRL_A733_FSM_JUMP ((0x024f << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_AUTO_OFF_CTRL0 ((0x0250 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_AUTO_OFF_CTRL1 ((0x0251 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_AUTO_OFF_CTRL2 ((0x0252 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_AUTO_OFF_CTRL3 ((0x0253 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_AUTO_OFF_CTRL4 ((0x0254 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_AUTO_OFF_CTRL5 ((0x0255 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_TIMER_TH_01 ((0x0258 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_TIMER_TH_23 ((0x0259 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_TIMER_TH_45 ((0x025a << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_TIMER_TH_67 ((0x025b << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_TIMER_TH_89 ((0x025c << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_IRQ_MASK0 ((0x0260 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_IRQ_MASK1 ((0x0261 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_IRQ_MASK2 ((0x0262 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_IRQ_MASK3 ((0x0263 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_IRQ_MASK4 ((0x0264 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_IRQ_MASK5 ((0x0265 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_IRQ_MASK6 ((0x0266 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_IRQ_MASK7 ((0x0267 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_IRQ_MASK8 ((0x0268 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_IRQ_MASK9 ((0x0269 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_IRQ_MASK10 ((0x026a << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_IRQ_MASK11 ((0x026b << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_IRQ_MASK12 ((0x026c << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_IRQ_MASK13 ((0x026d << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_IRQ_MASK14 ((0x026e << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_IRQ_MASK15 ((0x026f << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_MEMPD_INIT_SET ((0x0270 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_MEMPD_OFF_SET ((0x0271 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_MEMPD_ON_A_SET ((0x0272 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_MEMPD_ON_B_SET ((0x0273 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_MEMPD_ON_C_SET ((0x0274 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_MEMPD_ON_D_SET ((0x0275 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_MEMPD_STS ((0x0276 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_FSM_STS0 ((0x0277 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_FSM_STS1 ((0x0278 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_FSM_STS2 ((0x0279 << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_FSM_START_OFF ((0x027d << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_FSM_START_ON ((0x027e << 2) + 0xfe00c000)
+#define PWRCTRL_A73TOP_FSM_JUMP ((0x027f << 2) + 0xfe00c000)
+//========================================================================
+// RSA
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe042000
+// -----------------------------------------------
+#define RSA_BASE ((0x0000 << 2) + 0xfe042000)
+//========================================================================
+// AOCPU
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe09c000
+// -----------------------------------------------
+#define AOCPU_CPU_CTRL0 ((0x0000 << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_CPU_CTRL1 ((0x0001 << 2) + 0xfe09c000)
+//Bit 31:11- 0 - n205 address shift, 1: 0x8000_0000~0x4000_0000
+//Bit 30:11- 0 - reserved
+//Bit 10 - 0 - gate by sleep, 1: gate, 0: free run
+//Bit 9 - 0 - RXEV for riscv input refer riscv doc
+//Bit 8 - 0 - reserved
+//Bit 7:6- 0 - n205_debug_sel,aocpu_core_status0 info select
+//Bit 5:2- 0 - reserved
+//Bit 1 - 0 - n205_i_dbg_stop
+//Bit 0 - 0 - n205_pc_enable
+#define AOCPU_CPU_CTRL2 ((0x0002 << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_CPU_CTRL3 ((0x0003 << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_CPU_CTRL4 ((0x0004 << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_CPU_CTRL5 ((0x0005 << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_CPU_STS0 ((0x000a << 2) + 0xfe09c000)
+//Bit 31:0 - 0 - n205_debug_sel==0 : n205_trace_casuse, 1:n205_trace_tval, 2:n205_trace_iaddr, 3:n205_trace_instr
+#define AOCPU_CPU_STS1 ((0x000b << 2) + 0xfe09c000)
+//Bit 31 - 0 - n205_core_sleep_value
+//Bit 30:29- 0 - n205_trace_priv
+//Bit 28:20- 0 - reserved
+//Bit 19 - 0 - n205_core_wfi_mode
+//Bit 18 - 0 - n205_trace_ivalid
+//Bit 17 - 0 - n205_trace_iexception
+//Bit 16 - 0 - n205_trace_interrupt
+//Bit 15:0 - 0 - reserved
+#define AOCPU_CPU_STS2 ((0x000c << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_CPU_STS3 ((0x000d << 2) + 0xfe09c000)
+//Bit 31 - 0 - n205_hart_halted
+//Bit 30 - 0 - n205_ndmreset
+//Bit 29 - 0 - n205_dmactive
+//Bit 28:0 - 0 - reserved
+#define AOCPU_CPU_VECTOR ((0x000f << 2) + 0xfe09c000)
+//Bit 31:0- 0x1000_0000 - reserved
+#define AOCPU_IRQ_SEL0 ((0x0010 << 2) + 0xfe09c000)
+//Bit 24:16- 0 - INTISR01 interrupt source select in int_map
+//Bit 8:0 - 0 - INTISR00 interrupt source select in int_map
+#define AOCPU_IRQ_SEL1 ((0x0011 << 2) + 0xfe09c000)
+//Bit 24:16- 0 - INTISR03 interrupt source select in int_map
+//Bit 8:0 - 0 - INTISR02 interrupt source select in int_map
+#define AOCPU_IRQ_SEL2 ((0x0012 << 2) + 0xfe09c000)
+//Bit 24:16- 0 - INTISR05 interrupt source select in int_map
+//Bit 8:0 - 0 - INTISR04 interrupt source select in int_map
+#define AOCPU_IRQ_SEL3 ((0x0013 << 2) + 0xfe09c000)
+//Bit 24:16- 0 - INTISR07 interrupt source select in int_map
+//Bit 8:0 - 0 - INTISR06 interrupt source select in int_map
+#define AOCPU_IRQ_SEL4 ((0x0014 << 2) + 0xfe09c000)
+//Bit 24:16- 0 - INTISR09 interrupt source select in int_map
+//Bit 8:0 - 0 - INTISR08 interrupt source select in int_map
+#define AOCPU_IRQ_SEL5 ((0x0015 << 2) + 0xfe09c000)
+//Bit 24:16- 0 - INTISR11 interrupt source select in int_map
+//Bit 8:0 - 0 - INTISR10 interrupt source select in int_map
+#define AOCPU_IRQ_SEL6 ((0x0016 << 2) + 0xfe09c000)
+//Bit 24:16- 0 - INTISR13 interrupt source select in int_map
+//Bit 8:0 - 0 - INTISR12 interrupt source select in int_map
+#define AOCPU_IRQ_SEL7 ((0x0017 << 2) + 0xfe09c000)
+//Bit 24:16- 0 - INTISR15 interrupt source select in int_map
+//Bit 8:0 - 0 - INTISR14 interrupt source select in int_map
+#define AOCPU_STS00_BYCPU ((0x0018 << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_STS01_BYCPU ((0x0019 << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_STS02_BYCPU ((0x001a << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_STS03_BYCPU ((0x001b << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_STS04_BYCPU ((0x001c << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_STS05_BYCPU ((0x001d << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_STS06_BYCPU ((0x001e << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_STS07_BYCPU ((0x001f << 2) + 0xfe09c000)
+//Bit 31:0- 0 - reserved
+#define AOCPU_IRQ_SEL8 ((0x0020 << 2) + 0xfe09c000)
+//Bit 24:16- 0 - INTISR17 interrupt source select in int_map
+//Bit 8:0 - 0 - INTISR16 interrupt source select in int_map
+#define AOCPU_IRQ_SEL9 ((0x0021 << 2) + 0xfe09c000)
+//Bit 24:16- 0 - INTISR19 interrupt source select in int_map
+//Bit 8:0 - 0 - INTISR18 interrupt source select in int_map
+#define AOCPU_IRQ_SEL10 ((0x0022 << 2) + 0xfe09c000)
+//Bit 24:16- 0 - INTISR21 interrupt source select in int_map
+//Bit 8:0 - 0 - INTISR20 interrupt source select in int_map
+#define AOCPU_IRQ_SEL11 ((0x0023 << 2) + 0xfe09c000)
+//Bit 24:16- 0 - INTISR23 interrupt source select in int_map
+//Bit 8:0 - 0 - INTISR22 interrupt source select in int_map
+#define AOCPU_IRQ_SEL12 ((0x0024 << 2) + 0xfe09c000)
+//Bit 24:16- 0 - INTISR25 interrupt source select in int_map
+//Bit 8:0 - 0 - INTISR24 interrupt source select in int_map
+#define AOCPU_IRQ_SEL13 ((0x0025 << 2) + 0xfe09c000)
+//Bit 24:16- 0 - INTISR27 interrupt source select in int_map
+//Bit 8:0 - 0 - INTISR26 interrupt source select in int_map
+#define AOCPU_IRQ_SEL14 ((0x0026 << 2) + 0xfe09c000)
+//Bit 24:16- 0 - INTISR29 interrupt source select in int_map
+//Bit 8:0 - 0 - INTISR28 interrupt source select in int_map
+#define AOCPU_IRQ_SEL15 ((0x0027 << 2) + 0xfe09c000)
+//Bit 24:16- 0 - INTISR31 interrupt source select in int_map
+//Bit 8:0 - 0 - INTISR30 interrupt source select in int_map
+//========================================================================
+// AUCPU
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe09e000
+// -----------------------------------------------
+#define AUCPU_CPU_CTRL0 ((0x0000 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_CPU_CTRL1 ((0x0001 << 2) + 0xfe09e000)
+//Bit 31:11- 0 - reserved
+//Bit 10 - 0 - gate by sleep
+//Bit 9 - 0 - RXEV
+//Bit 8 - 0 - reserved
+//Bit 7:6 - 0 - n205_debug_sel,aucpu_core_status0 info select
+//Bit 5:2 - 0 - reserved
+//Bit 1 - 0 - n205_i_dbg_stop
+//Bit 0 - 0 - n205_pc_enable
+#define AUCPU_CPU_CTRL2 ((0x0002 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_CPU_CTRL3 ((0x0003 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_CPU_CTRL4 ((0x0004 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_CPU_CTRL5 ((0x0005 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_CPU_STS0 ((0x000a << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - n205_debug_sel==0 : n205_trace_casuse, 1:n205_trace_tval, 2:n205_trace_iaddr, 3:n205_trace_instr
+#define AUCPU_CPU_STS1 ((0x000b << 2) + 0xfe09e000)
+//Bit 31 - 0 - n205_core_sleep_value
+//Bit 30:29- 0 - n205_trace_priv
+//Bit 28:20- 0 - reserved
+//Bit 19 - 0 - n205_core_wfi_mode
+//Bit 18 - 0 - n205_trace_ivalid
+//Bit 17 - 0 - n205_trace_iexception
+//Bit 16 - 0 - n205_trace_interrupt
+//Bit 15:0 - 0 - reserved
+#define AUCPU_CPU_STS2 ((0x000c << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_CPU_STS3 ((0x000d << 2) + 0xfe09e000)
+//Bit 31 - 0 - n205_hart_halted
+//Bit 30 - 0 - n205_ndmreset
+//Bit 29 - 0 - n205_dmactive
+//Bit 28:0 - 0 - reserved
+#define AUCPU_DMA_APB_SEL ((0x0010 << 2) + 0xfe09e000)
+//Bit 31:30- 0 - reserved
+//Bit 0 - 0 - 1: riscv control dma, 0: ap control dma
+#define AUCPU_IRQ_AP2RISCV ((0x0011 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - AP cpu send irq to riscv
+#define AUCPU_IRQ_RISCV2AP ((0x0012 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - riscv send irq to AP
+#define AUCPU_STS00_BY_AP ((0x0020 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS01_BY_AP ((0x0021 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS02_BY_AP ((0x0022 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS03_BY_AP ((0x0023 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS04_BY_AP ((0x0024 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS05_BY_AP ((0x0025 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS06_BY_AP ((0x0026 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS07_BY_AP ((0x0027 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS08_BY_AP ((0x0028 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS09_BY_AP ((0x0029 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS10_BY_AP ((0x002a << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS11_BY_AP ((0x002b << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS12_BY_AP ((0x002c << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS13_BY_AP ((0x002d << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS14_BY_AP ((0x002e << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS15_BY_AP ((0x002f << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS16_BY_AP ((0x0030 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS17_BY_AP ((0x0031 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS18_BY_AP ((0x0032 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS19_BY_AP ((0x0033 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS20_BY_AP ((0x0034 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS21_BY_AP ((0x0035 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS22_BY_AP ((0x0036 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS23_BY_AP ((0x0037 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS24_BY_AP ((0x0038 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS25_BY_AP ((0x0039 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS26_BY_AP ((0x003a << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS27_BY_AP ((0x003b << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS28_BY_AP ((0x003c << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS29_BY_AP ((0x003d << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS30_BY_AP ((0x003e << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS31_BY_AP ((0x003f << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS00_BY_RISCV ((0x0040 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS01_BY_RISCV ((0x0041 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS02_BY_RISCV ((0x0042 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS03_BY_RISCV ((0x0043 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS04_BY_RISCV ((0x0044 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS05_BY_RISCV ((0x0045 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS06_BY_RISCV ((0x0046 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS07_BY_RISCV ((0x0047 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS08_BY_RISCV ((0x0048 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS09_BY_RISCV ((0x0049 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS10_BY_RISCV ((0x004a << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS11_BY_RISCV ((0x004b << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS12_BY_RISCV ((0x004c << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS13_BY_RISCV ((0x004d << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS14_BY_RISCV ((0x004e << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS15_BY_RISCV ((0x004f << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS16_BY_RISCV ((0x0050 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS17_BY_RISCV ((0x0051 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS18_BY_RISCV ((0x0052 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS19_BY_RISCV ((0x0053 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS20_BY_RISCV ((0x0054 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS21_BY_RISCV ((0x0055 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS22_BY_RISCV ((0x0056 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS23_BY_RISCV ((0x0057 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS24_BY_RISCV ((0x0058 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS25_BY_RISCV ((0x0059 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS26_BY_RISCV ((0x005a << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS27_BY_RISCV ((0x005b << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS28_BY_RISCV ((0x005c << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS29_BY_RISCV ((0x005d << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS30_BY_RISCV ((0x005e << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_STS31_BY_RISCV ((0x005f << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - reserved
+#define AUCPU_DEMUX_STS_BY_RISCV ((0x0060 << 2) + 0xfe09e000)
+//Bit 31 - 0 - read only, demux status updated
+//Bit 31:8 - 0 - reserved
+//Bit 7:0 - 0 - read demux chn select
+#define AUCPU_DEMUX_STS0 ((0x0061 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - demux status 0
+#define AUCPU_DEMUX_STS1 ((0x0062 << 2) + 0xfe09e000)
+//Bit 31:0 - 0 - demux status 1
+//========================================================================
+// AXI_SRAM
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe090000
+// -----------------------------------------------
+#define SRAM_RANGE0_STA ((0x0000 << 2) + 0xfe090000)
+#define SRAM_RANGE1_STA ((0x0001 << 2) + 0xfe090000)
+#define SRAM_RANGE2_STA ((0x0002 << 2) + 0xfe090000)
+#define SRAM_RANGE3_STA ((0x0003 << 2) + 0xfe090000)
+#define SRAM_RANGE4_STA ((0x0004 << 2) + 0xfe090000)
+#define SRAM_RANGE5_STA ((0x0005 << 2) + 0xfe090000)
+#define SRAM_RANGE6_STA ((0x0006 << 2) + 0xfe090000)
+#define SRAM_RANGE7_STA ((0x0007 << 2) + 0xfe090000)
+#define SRAM_RANGE8_STA ((0x0008 << 2) + 0xfe090000)
+#define SRAM_RANGE9_STA ((0x0009 << 2) + 0xfe090000)
+#define SRAM_RANGE10_STA ((0x000a << 2) + 0xfe090000)
+#define SRAM_RANGE11_STA ((0x000b << 2) + 0xfe090000)
+#define SRAM_RANGE12_STA ((0x000c << 2) + 0xfe090000)
+#define SRAM_RANGE13_STA ((0x000d << 2) + 0xfe090000)
+#define SRAM_RANGE14_STA ((0x000e << 2) + 0xfe090000)
+#define SRAM_RANGE0_EDA ((0x000f << 2) + 0xfe090000)
+#define SRAM_RANGE1_EDA ((0x0010 << 2) + 0xfe090000)
+#define SRAM_RANGE2_EDA ((0x0011 << 2) + 0xfe090000)
+#define SRAM_RANGE3_EDA ((0x0012 << 2) + 0xfe090000)
+#define SRAM_RANGE4_EDA ((0x0013 << 2) + 0xfe090000)
+#define SRAM_RANGE5_EDA ((0x0014 << 2) + 0xfe090000)
+#define SRAM_RANGE6_EDA ((0x0015 << 2) + 0xfe090000)
+#define SRAM_RANGE7_EDA ((0x0016 << 2) + 0xfe090000)
+#define SRAM_RANGE8_EDA ((0x0017 << 2) + 0xfe090000)
+#define SRAM_RANGE9_EDA ((0x0018 << 2) + 0xfe090000)
+#define SRAM_RANGE10_EDA ((0x0019 << 2) + 0xfe090000)
+#define SRAM_RANGE11_EDA ((0x001a << 2) + 0xfe090000)
+#define SRAM_RANGE12_EDA ((0x001b << 2) + 0xfe090000)
+#define SRAM_RANGE13_EDA ((0x001c << 2) + 0xfe090000)
+#define SRAM_RANGE14_EDA ((0x001d << 2) + 0xfe090000)
+#define SRAM_RANGE0_READ_CTRL0 ((0x001e << 2) + 0xfe090000)
+#define SRAM_RANGE1_READ_CTRL0 ((0x001f << 2) + 0xfe090000)
+#define SRAM_RANGE2_READ_CTRL0 ((0x0020 << 2) + 0xfe090000)
+#define SRAM_RANGE3_READ_CTRL0 ((0x0021 << 2) + 0xfe090000)
+#define SRAM_RANGE4_READ_CTRL0 ((0x0022 << 2) + 0xfe090000)
+#define SRAM_RANGE5_READ_CTRL0 ((0x0023 << 2) + 0xfe090000)
+#define SRAM_RANGE6_READ_CTRL0 ((0x0024 << 2) + 0xfe090000)
+#define SRAM_RANGE7_READ_CTRL0 ((0x0025 << 2) + 0xfe090000)
+#define SRAM_RANGE8_READ_CTRL0 ((0x0026 << 2) + 0xfe090000)
+#define SRAM_RANGE9_READ_CTRL0 ((0x0027 << 2) + 0xfe090000)
+#define SRAM_RANGE10_READ_CTRL0 ((0x0028 << 2) + 0xfe090000)
+#define SRAM_RANGE11_READ_CTRL0 ((0x0029 << 2) + 0xfe090000)
+#define SRAM_RANGE12_READ_CTRL0 ((0x002a << 2) + 0xfe090000)
+#define SRAM_RANGE13_READ_CTRL0 ((0x002b << 2) + 0xfe090000)
+#define SRAM_RANGE14_READ_CTRL0 ((0x002c << 2) + 0xfe090000)
+#define SRAM_RANGE15_READ_CTRL0 ((0x002d << 2) + 0xfe090000)
+#define SRAM_RANGE0_WRITE_CTRL0 ((0x002e << 2) + 0xfe090000)
+#define SRAM_RANGE1_WRITE_CTRL0 ((0x002f << 2) + 0xfe090000)
+#define SRAM_RANGE2_WRITE_CTRL0 ((0x0030 << 2) + 0xfe090000)
+#define SRAM_RANGE3_WRITE_CTRL0 ((0x0031 << 2) + 0xfe090000)
+#define SRAM_RANGE4_WRITE_CTRL0 ((0x0032 << 2) + 0xfe090000)
+#define SRAM_RANGE5_WRITE_CTRL0 ((0x0033 << 2) + 0xfe090000)
+#define SRAM_RANGE6_WRITE_CTRL0 ((0x0034 << 2) + 0xfe090000)
+#define SRAM_RANGE7_WRITE_CTRL0 ((0x0035 << 2) + 0xfe090000)
+#define SRAM_RANGE8_WRITE_CTRL0 ((0x0036 << 2) + 0xfe090000)
+#define SRAM_RANGE9_WRITE_CTRL0 ((0x0037 << 2) + 0xfe090000)
+#define SRAM_RANGE10_WRITE_CTRL0 ((0x0038 << 2) + 0xfe090000)
+#define SRAM_RANGE11_WRITE_CTRL0 ((0x0039 << 2) + 0xfe090000)
+#define SRAM_RANGE12_WRITE_CTRL0 ((0x003a << 2) + 0xfe090000)
+#define SRAM_RANGE13_WRITE_CTRL0 ((0x003b << 2) + 0xfe090000)
+#define SRAM_RANGE14_WRITE_CTRL0 ((0x003c << 2) + 0xfe090000)
+#define SRAM_RANGE15_WRITE_CTRL0 ((0x003d << 2) + 0xfe090000)
+#define SRAM_RANGE0_READ_CTRL1 ((0x003e << 2) + 0xfe090000)
+#define SRAM_RANGE1_READ_CTRL1 ((0x003f << 2) + 0xfe090000)
+#define SRAM_RANGE2_READ_CTRL1 ((0x0040 << 2) + 0xfe090000)
+#define SRAM_RANGE3_READ_CTRL1 ((0x0041 << 2) + 0xfe090000)
+#define SRAM_RANGE4_READ_CTRL1 ((0x0042 << 2) + 0xfe090000)
+#define SRAM_RANGE5_READ_CTRL1 ((0x0043 << 2) + 0xfe090000)
+#define SRAM_RANGE6_READ_CTRL1 ((0x0044 << 2) + 0xfe090000)
+#define SRAM_RANGE7_READ_CTRL1 ((0x0045 << 2) + 0xfe090000)
+#define SRAM_RANGE8_READ_CTRL1 ((0x0046 << 2) + 0xfe090000)
+#define SRAM_RANGE9_READ_CTRL1 ((0x0047 << 2) + 0xfe090000)
+#define SRAM_RANGE10_READ_CTRL1 ((0x0048 << 2) + 0xfe090000)
+#define SRAM_RANGE11_READ_CTRL1 ((0x0049 << 2) + 0xfe090000)
+#define SRAM_RANGE12_READ_CTRL1 ((0x004a << 2) + 0xfe090000)
+#define SRAM_RANGE13_READ_CTRL1 ((0x004b << 2) + 0xfe090000)
+#define SRAM_RANGE14_READ_CTRL1 ((0x004c << 2) + 0xfe090000)
+#define SRAM_RANGE15_READ_CTRL1 ((0x004d << 2) + 0xfe090000)
+#define SRAM_RANGE0_WRITE_CTRL1 ((0x004e << 2) + 0xfe090000)
+#define SRAM_RANGE1_WRITE_CTRL1 ((0x004f << 2) + 0xfe090000)
+#define SRAM_RANGE2_WRITE_CTRL1 ((0x0050 << 2) + 0xfe090000)
+#define SRAM_RANGE3_WRITE_CTRL1 ((0x0051 << 2) + 0xfe090000)
+#define SRAM_RANGE4_WRITE_CTRL1 ((0x0052 << 2) + 0xfe090000)
+#define SRAM_RANGE5_WRITE_CTRL1 ((0x0053 << 2) + 0xfe090000)
+#define SRAM_RANGE6_WRITE_CTRL1 ((0x0054 << 2) + 0xfe090000)
+#define SRAM_RANGE7_WRITE_CTRL1 ((0x0055 << 2) + 0xfe090000)
+#define SRAM_RANGE8_WRITE_CTRL1 ((0x0056 << 2) + 0xfe090000)
+#define SRAM_RANGE9_WRITE_CTRL1 ((0x0057 << 2) + 0xfe090000)
+#define SRAM_RANGE10_WRITE_CTRL1 ((0x0058 << 2) + 0xfe090000)
+#define SRAM_RANGE11_WRITE_CTRL1 ((0x0059 << 2) + 0xfe090000)
+#define SRAM_RANGE12_WRITE_CTRL1 ((0x005a << 2) + 0xfe090000)
+#define SRAM_RANGE13_WRITE_CTRL1 ((0x005b << 2) + 0xfe090000)
+#define SRAM_RANGE14_WRITE_CTRL1 ((0x005c << 2) + 0xfe090000)
+#define SRAM_RANGE15_WRITE_CTRL1 ((0x005d << 2) + 0xfe090000)
+#define SRAM_GLOBAL_READ_CTRL0 ((0x005e << 2) + 0xfe090000)
+#define SRAM_GLOBAL_READ_CTRL1 ((0x005f << 2) + 0xfe090000)
+#define SRAM_GLOBAL_WRITE_CTRL0 ((0x0060 << 2) + 0xfe090000)
+#define SRAM_GLOBAL_WRITE_CTRL1 ((0x0061 << 2) + 0xfe090000)
+#define SRAM_SEC_CTRL0 ((0x0062 << 2) + 0xfe090000)
+#define SRAM_REG_LOCK0 ((0x0063 << 2) + 0xfe090000)
+#define SRAM_REG_LOCK1 ((0x0064 << 2) + 0xfe090000)
+#define SRAM_REG_LOCK2 ((0x0065 << 2) + 0xfe090000)
+#define SRAM_GLOBAL_READ_CTRL0_LOCK ((0x0066 << 2) + 0xfe090000)
+#define SRAM_GLOBAL_READ_CTRL1_LOCK ((0x0067 << 2) + 0xfe090000)
+#define SRAM_GLOBAL_WRITE_CTRL0_LOCK ((0x0068 << 2) + 0xfe090000)
+#define SRAM_GLOBAL_WRITE_CTRL1_LOCK ((0x0069 << 2) + 0xfe090000)
+#define SRAM_SEC_CTRL0_LOCK ((0x006a << 2) + 0xfe090000)
+#define SRAM_STATUS_REG ((0x006b << 2) + 0xfe090000)
+//========================================================================
+// AXI_SRAM B
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe092000
+// -----------------------------------------------
+#define SRAM_B_RANGE0_STA ((0x0000 << 2) + 0xfe092000)
+#define SRAM_B_RANGE1_STA ((0x0001 << 2) + 0xfe092000)
+#define SRAM_B_RANGE2_STA ((0x0002 << 2) + 0xfe092000)
+#define SRAM_B_RANGE3_STA ((0x0003 << 2) + 0xfe092000)
+#define SRAM_B_RANGE4_STA ((0x0004 << 2) + 0xfe092000)
+#define SRAM_B_RANGE5_STA ((0x0005 << 2) + 0xfe092000)
+#define SRAM_B_RANGE6_STA ((0x0006 << 2) + 0xfe092000)
+#define SRAM_B_RANGE7_STA ((0x0007 << 2) + 0xfe092000)
+#define SRAM_B_RANGE8_STA ((0x0008 << 2) + 0xfe092000)
+#define SRAM_B_RANGE9_STA ((0x0009 << 2) + 0xfe092000)
+#define SRAM_B_RANGE10_STA ((0x000a << 2) + 0xfe092000)
+#define SRAM_B_RANGE11_STA ((0x000b << 2) + 0xfe092000)
+#define SRAM_B_RANGE12_STA ((0x000c << 2) + 0xfe092000)
+#define SRAM_B_RANGE13_STA ((0x000d << 2) + 0xfe092000)
+#define SRAM_B_RANGE14_STA ((0x000e << 2) + 0xfe092000)
+#define SRAM_B_RANGE0_EDA ((0x000f << 2) + 0xfe092000)
+#define SRAM_B_RANGE1_EDA ((0x0010 << 2) + 0xfe092000)
+#define SRAM_B_RANGE2_EDA ((0x0011 << 2) + 0xfe092000)
+#define SRAM_B_RANGE3_EDA ((0x0012 << 2) + 0xfe092000)
+#define SRAM_B_RANGE4_EDA ((0x0013 << 2) + 0xfe092000)
+#define SRAM_B_RANGE5_EDA ((0x0014 << 2) + 0xfe092000)
+#define SRAM_B_RANGE6_EDA ((0x0015 << 2) + 0xfe092000)
+#define SRAM_B_RANGE7_EDA ((0x0016 << 2) + 0xfe092000)
+#define SRAM_B_RANGE8_EDA ((0x0017 << 2) + 0xfe092000)
+#define SRAM_B_RANGE9_EDA ((0x0018 << 2) + 0xfe092000)
+#define SRAM_B_RANGE10_EDA ((0x0019 << 2) + 0xfe092000)
+#define SRAM_B_RANGE11_EDA ((0x001a << 2) + 0xfe092000)
+#define SRAM_B_RANGE12_EDA ((0x001b << 2) + 0xfe092000)
+#define SRAM_B_RANGE13_EDA ((0x001c << 2) + 0xfe092000)
+#define SRAM_B_RANGE14_EDA ((0x001d << 2) + 0xfe092000)
+#define SRAM_B_RANGE0_READ_CTRL0 ((0x001e << 2) + 0xfe092000)
+#define SRAM_B_RANGE1_READ_CTRL0 ((0x001f << 2) + 0xfe092000)
+#define SRAM_B_RANGE2_READ_CTRL0 ((0x0020 << 2) + 0xfe092000)
+#define SRAM_B_RANGE3_READ_CTRL0 ((0x0021 << 2) + 0xfe092000)
+#define SRAM_B_RANGE4_READ_CTRL0 ((0x0022 << 2) + 0xfe092000)
+#define SRAM_B_RANGE5_READ_CTRL0 ((0x0023 << 2) + 0xfe092000)
+#define SRAM_B_RANGE6_READ_CTRL0 ((0x0024 << 2) + 0xfe092000)
+#define SRAM_B_RANGE7_READ_CTRL0 ((0x0025 << 2) + 0xfe092000)
+#define SRAM_B_RANGE8_READ_CTRL0 ((0x0026 << 2) + 0xfe092000)
+#define SRAM_B_RANGE9_READ_CTRL0 ((0x0027 << 2) + 0xfe092000)
+#define SRAM_B_RANGE10_READ_CTRL0 ((0x0028 << 2) + 0xfe092000)
+#define SRAM_B_RANGE11_READ_CTRL0 ((0x0029 << 2) + 0xfe092000)
+#define SRAM_B_RANGE12_READ_CTRL0 ((0x002a << 2) + 0xfe092000)
+#define SRAM_B_RANGE13_READ_CTRL0 ((0x002b << 2) + 0xfe092000)
+#define SRAM_B_RANGE14_READ_CTRL0 ((0x002c << 2) + 0xfe092000)
+#define SRAM_B_RANGE15_READ_CTRL0 ((0x002d << 2) + 0xfe092000)
+#define SRAM_B_RANGE0_WRITE_CTRL0 ((0x002e << 2) + 0xfe092000)
+#define SRAM_B_RANGE1_WRITE_CTRL0 ((0x002f << 2) + 0xfe092000)
+#define SRAM_B_RANGE2_WRITE_CTRL0 ((0x0030 << 2) + 0xfe092000)
+#define SRAM_B_RANGE3_WRITE_CTRL0 ((0x0031 << 2) + 0xfe092000)
+#define SRAM_B_RANGE4_WRITE_CTRL0 ((0x0032 << 2) + 0xfe092000)
+#define SRAM_B_RANGE5_WRITE_CTRL0 ((0x0033 << 2) + 0xfe092000)
+#define SRAM_B_RANGE6_WRITE_CTRL0 ((0x0034 << 2) + 0xfe092000)
+#define SRAM_B_RANGE7_WRITE_CTRL0 ((0x0035 << 2) + 0xfe092000)
+#define SRAM_B_RANGE8_WRITE_CTRL0 ((0x0036 << 2) + 0xfe092000)
+#define SRAM_B_RANGE9_WRITE_CTRL0 ((0x0037 << 2) + 0xfe092000)
+#define SRAM_B_RANGE10_WRITE_CTRL0 ((0x0038 << 2) + 0xfe092000)
+#define SRAM_B_RANGE11_WRITE_CTRL0 ((0x0039 << 2) + 0xfe092000)
+#define SRAM_B_RANGE12_WRITE_CTRL0 ((0x003a << 2) + 0xfe092000)
+#define SRAM_B_RANGE13_WRITE_CTRL0 ((0x003b << 2) + 0xfe092000)
+#define SRAM_B_RANGE14_WRITE_CTRL0 ((0x003c << 2) + 0xfe092000)
+#define SRAM_B_RANGE15_WRITE_CTRL0 ((0x003d << 2) + 0xfe092000)
+#define SRAM_B_RANGE0_READ_CTRL1 ((0x003e << 2) + 0xfe092000)
+#define SRAM_B_RANGE1_READ_CTRL1 ((0x003f << 2) + 0xfe092000)
+#define SRAM_B_RANGE2_READ_CTRL1 ((0x0040 << 2) + 0xfe092000)
+#define SRAM_B_RANGE3_READ_CTRL1 ((0x0041 << 2) + 0xfe092000)
+#define SRAM_B_RANGE4_READ_CTRL1 ((0x0042 << 2) + 0xfe092000)
+#define SRAM_B_RANGE5_READ_CTRL1 ((0x0043 << 2) + 0xfe092000)
+#define SRAM_B_RANGE6_READ_CTRL1 ((0x0044 << 2) + 0xfe092000)
+#define SRAM_B_RANGE7_READ_CTRL1 ((0x0045 << 2) + 0xfe092000)
+#define SRAM_B_RANGE8_READ_CTRL1 ((0x0046 << 2) + 0xfe092000)
+#define SRAM_B_RANGE9_READ_CTRL1 ((0x0047 << 2) + 0xfe092000)
+#define SRAM_B_RANGE10_READ_CTRL1 ((0x0048 << 2) + 0xfe092000)
+#define SRAM_B_RANGE11_READ_CTRL1 ((0x0049 << 2) + 0xfe092000)
+#define SRAM_B_RANGE12_READ_CTRL1 ((0x004a << 2) + 0xfe092000)
+#define SRAM_B_RANGE13_READ_CTRL1 ((0x004b << 2) + 0xfe092000)
+#define SRAM_B_RANGE14_READ_CTRL1 ((0x004c << 2) + 0xfe092000)
+#define SRAM_B_RANGE15_READ_CTRL1 ((0x004d << 2) + 0xfe092000)
+#define SRAM_B_RANGE0_WRITE_CTRL1 ((0x004e << 2) + 0xfe092000)
+#define SRAM_B_RANGE1_WRITE_CTRL1 ((0x004f << 2) + 0xfe092000)
+#define SRAM_B_RANGE2_WRITE_CTRL1 ((0x0050 << 2) + 0xfe092000)
+#define SRAM_B_RANGE3_WRITE_CTRL1 ((0x0051 << 2) + 0xfe092000)
+#define SRAM_B_RANGE4_WRITE_CTRL1 ((0x0052 << 2) + 0xfe092000)
+#define SRAM_B_RANGE5_WRITE_CTRL1 ((0x0053 << 2) + 0xfe092000)
+#define SRAM_B_RANGE6_WRITE_CTRL1 ((0x0054 << 2) + 0xfe092000)
+#define SRAM_B_RANGE7_WRITE_CTRL1 ((0x0055 << 2) + 0xfe092000)
+#define SRAM_B_RANGE8_WRITE_CTRL1 ((0x0056 << 2) + 0xfe092000)
+#define SRAM_B_RANGE9_WRITE_CTRL1 ((0x0057 << 2) + 0xfe092000)
+#define SRAM_B_RANGE10_WRITE_CTRL1 ((0x0058 << 2) + 0xfe092000)
+#define SRAM_B_RANGE11_WRITE_CTRL1 ((0x0059 << 2) + 0xfe092000)
+#define SRAM_B_RANGE12_WRITE_CTRL1 ((0x005a << 2) + 0xfe092000)
+#define SRAM_B_RANGE13_WRITE_CTRL1 ((0x005b << 2) + 0xfe092000)
+#define SRAM_B_RANGE14_WRITE_CTRL1 ((0x005c << 2) + 0xfe092000)
+#define SRAM_B_RANGE15_WRITE_CTRL1 ((0x005d << 2) + 0xfe092000)
+#define SRAM_B_GLOBAL_READ_CTRL0 ((0x005e << 2) + 0xfe092000)
+#define SRAM_B_GLOBAL_READ_CTRL1 ((0x005f << 2) + 0xfe092000)
+#define SRAM_B_GLOBAL_WRITE_CTRL0 ((0x0060 << 2) + 0xfe092000)
+#define SRAM_B_GLOBAL_WRITE_CTRL1 ((0x0061 << 2) + 0xfe092000)
+#define SRAM_B_SEC_CTRL0 ((0x0062 << 2) + 0xfe092000)
+#define SRAM_B_REG_LOCK0 ((0x0063 << 2) + 0xfe092000)
+#define SRAM_B_REG_LOCK1 ((0x0064 << 2) + 0xfe092000)
+#define SRAM_B_REG_LOCK2 ((0x0065 << 2) + 0xfe092000)
+#define SRAM_B_GLOBAL_READ_CTRL0_LOCK ((0x0066 << 2) + 0xfe092000)
+#define SRAM_B_GLOBAL_READ_CTRL1_LOCK ((0x0067 << 2) + 0xfe092000)
+#define SRAM_B_GLOBAL_WRITE_CTRL0_LOCK ((0x0068 << 2) + 0xfe092000)
+#define SRAM_B_GLOBAL_WRITE_CTRL1_LOCK ((0x0069 << 2) + 0xfe092000)
+#define SRAM_B_SEC_CTRL0_LOCK ((0x006a << 2) + 0xfe092000)
+#define SRAM_B_STATUS_REG ((0x006b << 2) + 0xfe092000)
+//========================================================================
+// MAILBOX
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe006000
+// -----------------------------------------------
+#define MAILBOX_BUF_MBOX00 ((0x0000 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX01 ((0x0020 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX02 ((0x0040 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX03 ((0x0060 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX04 ((0x0080 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX05 ((0x00a0 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX06 ((0x00c0 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX07 ((0x00e0 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX08 ((0x0100 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX09 ((0x0120 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX10 ((0x0140 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX11 ((0x0160 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX12 ((0x0180 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX13 ((0x01a0 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX14 ((0x01c0 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX15 ((0x01e0 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX16 ((0x0200 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX17 ((0x0220 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX18 ((0x0240 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX19 ((0x0260 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX20 ((0x0280 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX21 ((0x02a0 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX22 ((0x02c0 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX23 ((0x02e0 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX24 ((0x0300 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX25 ((0x0320 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX26 ((0x0340 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX27 ((0x0360 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX28 ((0x0380 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX29 ((0x03a0 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX30 ((0x03c0 << 2) + 0xfe006000)
+#define MAILBOX_BUF_MBOX31 ((0x03e0 << 2) + 0xfe006000)
+#define MAILBOX_LOCK_BIT0 ((0x0400 << 2) + 0xfe006000)
+#define MAILBOX_LOCK_BIT1 ((0x0401 << 2) + 0xfe006000)
+#define MAILBOX_LOCK_BIT2 ((0x0402 << 2) + 0xfe006000)
+#define MAILBOX_LOCK_BIT3 ((0x0403 << 2) + 0xfe006000)
+#define MAILBOX_PROT_BIT0 ((0x0404 << 2) + 0xfe006000)
+#define MAILBOX_PROT_BIT1 ((0x0405 << 2) + 0xfe006000)
+#define MAILBOX_PROT_BIT2 ((0x0406 << 2) + 0xfe006000)
+#define MAILBOX_PROT_BIT3 ((0x0407 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_IRQA_CLR ((0x0408 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_IRQB_CLR ((0x0409 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_IRQC_CLR ((0x040a << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_IRQD_CLR ((0x040b << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_IRQE_CLR ((0x040c << 2) + 0xfe006000)
+#define MAILBOX_IRQ_TYPE0 ((0x040d << 2) + 0xfe006000)
+#define MAILBOX_IRQ_TYPE1 ((0x040e << 2) + 0xfe006000)
+#define MAILBOX_IRQA_MASK0 ((0x0410 << 2) + 0xfe006000)
+#define MAILBOX_IRQA_MASK1 ((0x0411 << 2) + 0xfe006000)
+#define MAILBOX_IRQB_MASK0 ((0x0412 << 2) + 0xfe006000)
+#define MAILBOX_IRQB_MASK1 ((0x0413 << 2) + 0xfe006000)
+#define MAILBOX_IRQC_MASK0 ((0x0414 << 2) + 0xfe006000)
+#define MAILBOX_IRQC_MASK1 ((0x0415 << 2) + 0xfe006000)
+#define MAILBOX_IRQD_MASK0 ((0x0416 << 2) + 0xfe006000)
+#define MAILBOX_IRQD_MASK1 ((0x0417 << 2) + 0xfe006000)
+#define MAILBOX_IRQE_MASK0 ((0x0418 << 2) + 0xfe006000)
+#define MAILBOX_IRQE_MASK1 ((0x0419 << 2) + 0xfe006000)
+#define MAILBOX_IRQA_CLR0 ((0x0420 << 2) + 0xfe006000)
+#define MAILBOX_IRQA_CLR1 ((0x0421 << 2) + 0xfe006000)
+#define MAILBOX_IRQB_CLR0 ((0x0422 << 2) + 0xfe006000)
+#define MAILBOX_IRQB_CLR1 ((0x0423 << 2) + 0xfe006000)
+#define MAILBOX_IRQC_CLR0 ((0x0424 << 2) + 0xfe006000)
+#define MAILBOX_IRQC_CLR1 ((0x0425 << 2) + 0xfe006000)
+#define MAILBOX_IRQD_CLR0 ((0x0426 << 2) + 0xfe006000)
+#define MAILBOX_IRQD_CLR1 ((0x0427 << 2) + 0xfe006000)
+#define MAILBOX_IRQE_CLR0 ((0x0428 << 2) + 0xfe006000)
+#define MAILBOX_IRQE_CLR1 ((0x0429 << 2) + 0xfe006000)
+#define MAILBOX_IRQA_STS0 ((0x0430 << 2) + 0xfe006000)
+#define MAILBOX_IRQA_STS1 ((0x0431 << 2) + 0xfe006000)
+#define MAILBOX_IRQB_STS0 ((0x0432 << 2) + 0xfe006000)
+#define MAILBOX_IRQB_STS1 ((0x0433 << 2) + 0xfe006000)
+#define MAILBOX_IRQC_STS0 ((0x0434 << 2) + 0xfe006000)
+#define MAILBOX_IRQC_STS1 ((0x0435 << 2) + 0xfe006000)
+#define MAILBOX_IRQD_STS0 ((0x0436 << 2) + 0xfe006000)
+#define MAILBOX_IRQD_STS1 ((0x0437 << 2) + 0xfe006000)
+#define MAILBOX_IRQE_STS0 ((0x0438 << 2) + 0xfe006000)
+#define MAILBOX_IRQE_STS1 ((0x0439 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX00 ((0x0440 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX01 ((0x0441 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX02 ((0x0442 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX03 ((0x0443 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX04 ((0x0444 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX05 ((0x0445 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX06 ((0x0446 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX07 ((0x0447 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX08 ((0x0448 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX09 ((0x0449 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX10 ((0x044a << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX11 ((0x044b << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX12 ((0x044c << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX13 ((0x044d << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX14 ((0x044e << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX15 ((0x044f << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX16 ((0x0450 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX17 ((0x0451 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX18 ((0x0452 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX19 ((0x0453 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX20 ((0x0454 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX21 ((0x0455 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX22 ((0x0456 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX23 ((0x0457 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX24 ((0x0458 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX25 ((0x0459 << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX26 ((0x045a << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX27 ((0x045b << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX28 ((0x045c << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX29 ((0x045d << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX30 ((0x045e << 2) + 0xfe006000)
+#define MAILBOX_ACCESS_EN_MBOX31 ((0x045f << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX00 ((0x0460 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX01 ((0x0461 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX02 ((0x0462 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX03 ((0x0463 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX04 ((0x0464 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX05 ((0x0465 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX06 ((0x0466 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX07 ((0x0467 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX08 ((0x0468 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX09 ((0x0469 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX10 ((0x046a << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX11 ((0x046b << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX12 ((0x046c << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX13 ((0x046d << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX14 ((0x046e << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX15 ((0x046f << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX16 ((0x0470 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX17 ((0x0471 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX18 ((0x0472 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX19 ((0x0473 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX20 ((0x0474 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX21 ((0x0475 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX22 ((0x0476 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX23 ((0x0477 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX24 ((0x0478 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX25 ((0x0479 << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX26 ((0x047a << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX27 ((0x047b << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX28 ((0x047c << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX29 ((0x047d << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX30 ((0x047e << 2) + 0xfe006000)
+#define MAILBOX_SET_MBOX31 ((0x047f << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX00 ((0x0480 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX01 ((0x0481 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX02 ((0x0482 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX03 ((0x0483 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX04 ((0x0484 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX05 ((0x0485 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX06 ((0x0486 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX07 ((0x0487 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX08 ((0x0488 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX09 ((0x0489 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX10 ((0x048a << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX11 ((0x048b << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX12 ((0x048c << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX13 ((0x048d << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX14 ((0x048e << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX15 ((0x048f << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX16 ((0x0490 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX17 ((0x0491 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX18 ((0x0492 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX19 ((0x0493 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX20 ((0x0494 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX21 ((0x0495 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX22 ((0x0496 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX23 ((0x0497 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX24 ((0x0498 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX25 ((0x0499 << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX26 ((0x049a << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX27 ((0x049b << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX28 ((0x049c << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX29 ((0x049d << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX30 ((0x049e << 2) + 0xfe006000)
+#define MAILBOX_CLR_MBOX31 ((0x049f << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX00 ((0x04a0 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX01 ((0x04a1 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX02 ((0x04a2 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX03 ((0x04a3 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX04 ((0x04a4 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX05 ((0x04a5 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX06 ((0x04a6 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX07 ((0x04a7 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX08 ((0x04a8 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX09 ((0x04a9 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX10 ((0x04aa << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX11 ((0x04ab << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX12 ((0x04ac << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX13 ((0x04ad << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX14 ((0x04ae << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX15 ((0x04af << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX16 ((0x04b0 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX17 ((0x04b1 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX18 ((0x04b2 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX19 ((0x04b3 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX20 ((0x04b4 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX21 ((0x04b5 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX22 ((0x04b6 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX23 ((0x04b7 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX24 ((0x04b8 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX25 ((0x04b9 << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX26 ((0x04ba << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX27 ((0x04bb << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX28 ((0x04bc << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX29 ((0x04bd << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX30 ((0x04be << 2) + 0xfe006000)
+#define MAILBOX_STS_MBOX31 ((0x04bf << 2) + 0xfe006000)
+//========================================================================
+// IRQ_CTRL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe00a000
+// -----------------------------------------------
+#define IRQCTRL_IRQ_INV0 ((0x0000 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV1 ((0x0001 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV2 ((0x0002 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV3 ((0x0003 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV4 ((0x0004 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV5 ((0x0005 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV6 ((0x0006 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV7 ((0x0007 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV8 ((0x0008 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV9 ((0x0009 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_INV10 ((0x000a << 2) + 0xfe00a000)
+#define IRQCTRL_MASK0_GIC ((0x0010 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK1_GIC ((0x0011 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK2_GIC ((0x0012 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK3_GIC ((0x0013 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK4_GIC ((0x0014 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK5_GIC ((0x0015 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK6_GIC ((0x0016 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK7_GIC ((0x0017 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK8_GIC ((0x0018 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK9_GIC ((0x0019 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK10_GIC ((0x001a << 2) + 0xfe00a000)
+#define IRQCTRL_MASK0_DSP ((0x0020 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK1_DSP ((0x0021 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK2_DSP ((0x0022 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK3_DSP ((0x0023 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK4_DSP ((0x0024 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK5_DSP ((0x0025 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK6_DSP ((0x0026 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK7_DSP ((0x0027 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK8_DSP ((0x0028 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK9_DSP ((0x0029 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK10_DSP ((0x002a << 2) + 0xfe00a000)
+#define IRQCTRL_MASK0_PWRCTRL ((0x0030 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK1_PWRCTRL ((0x0031 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK2_PWRCTRL ((0x0032 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK3_PWRCTRL ((0x0033 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK4_PWRCTRL ((0x0034 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK5_PWRCTRL ((0x0035 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK6_PWRCTRL ((0x0036 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK7_PWRCTRL ((0x0037 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK8_PWRCTRL ((0x0038 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK9_PWRCTRL ((0x0039 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK10_PWRCTRL ((0x003a << 2) + 0xfe00a000)
+#define IRQCTRL_MASK0_AOCPU ((0x0040 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK1_AOCPU ((0x0041 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK2_AOCPU ((0x0042 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK3_AOCPU ((0x0043 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK4_AOCPU ((0x0044 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK5_AOCPU ((0x0045 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK6_AOCPU ((0x0046 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK7_AOCPU ((0x0047 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK8_AOCPU ((0x0048 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK9_AOCPU ((0x0049 << 2) + 0xfe00a000)
+#define IRQCTRL_MASK10_AOCPU ((0x004a << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE0 ((0x0050 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE1 ((0x0051 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE2 ((0x0052 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE3 ((0x0053 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE4 ((0x0054 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE5 ((0x0055 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE6 ((0x0056 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE7 ((0x0057 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE8 ((0x0058 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE9 ((0x0059 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_MODE10 ((0x005a << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH0 ((0x0060 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH1 ((0x0061 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH2 ((0x0062 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH3 ((0x0063 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH4 ((0x0064 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH5 ((0x0065 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH6 ((0x0066 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH7 ((0x0067 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH8 ((0x0068 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH9 ((0x0069 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH10 ((0x006a << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR0 ((0x0070 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR1 ((0x0071 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR2 ((0x0072 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR3 ((0x0073 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR4 ((0x0074 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR5 ((0x0075 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR6 ((0x0076 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR7 ((0x0077 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR8 ((0x0078 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR9 ((0x0079 << 2) + 0xfe00a000)
+#define IRQCTRL_IRQ_LATCH_CLR10 ((0x007a << 2) + 0xfe00a000)
+#define IRQCTRL_LOCK_BIT ((0x0080 << 2) + 0xfe00a000)
+#define IRQCTRL_PROT_BIT ((0x0081 << 2) + 0xfe00a000)
+#define IRQCTRL_SOFT_IRQ ((0x0088 << 2) + 0xfe00a000)
+//========================================================================
+// RESET_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe002000
+// -----------------------------------------------
+#define RESETCTRL_RESET0 ((0x0000 << 2) + 0xfe002000)
+#define RESETCTRL_RESET1 ((0x0001 << 2) + 0xfe002000)
+#define RESETCTRL_RESET2 ((0x0002 << 2) + 0xfe002000)
+#define RESETCTRL_RESET3 ((0x0003 << 2) + 0xfe002000)
+#define RESETCTRL_RESET4 ((0x0004 << 2) + 0xfe002000)
+#define RESETCTRL_RESET5 ((0x0005 << 2) + 0xfe002000)
+#define RESETCTRL_RESET6 ((0x0006 << 2) + 0xfe002000)
+#define RESETCTRL_RESET0_LEVEL ((0x0010 << 2) + 0xfe002000)
+#define RESETCTRL_RESET1_LEVEL ((0x0011 << 2) + 0xfe002000)
+#define RESETCTRL_RESET2_LEVEL ((0x0012 << 2) + 0xfe002000)
+#define RESETCTRL_RESET3_LEVEL ((0x0013 << 2) + 0xfe002000)
+#define RESETCTRL_RESET4_LEVEL ((0x0014 << 2) + 0xfe002000)
+#define RESETCTRL_RESET5_LEVEL ((0x0015 << 2) + 0xfe002000)
+#define RESETCTRL_RESET6_LEVEL ((0x0016 << 2) + 0xfe002000)
+#define RESETCTRL_RESET0_MASK ((0x0020 << 2) + 0xfe002000)
+#define RESETCTRL_RESET1_MASK ((0x0021 << 2) + 0xfe002000)
+#define RESETCTRL_RESET2_MASK ((0x0022 << 2) + 0xfe002000)
+#define RESETCTRL_RESET3_MASK ((0x0023 << 2) + 0xfe002000)
+#define RESETCTRL_RESET4_MASK ((0x0024 << 2) + 0xfe002000)
+#define RESETCTRL_RESET5_MASK ((0x0025 << 2) + 0xfe002000)
+#define RESETCTRL_RESET6_MASK ((0x0026 << 2) + 0xfe002000)
+#define RESETCTRL_RESET_HOLD_CYC ((0x0030 << 2) + 0xfe002000)
+#define RESETCTRL_WATCHDOG_CTRL0 ((0x0040 << 2) + 0xfe002000)
+#define RESETCTRL_WATCHDOG_CTRL1 ((0x0041 << 2) + 0xfe002000)
+#define RESETCTRL_WATCHDOG_CNT ((0x0042 << 2) + 0xfe002000)
+#define RESETCTRL_WATCHDOG_CLR ((0x0043 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_WATCHDOG_CTRL0 ((0x0044 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_WATCHDOG_CTRL1 ((0x0045 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_WATCHDOG_CNT ((0x0046 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_WATCHDOG_CLR ((0x0047 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET0 ((0x0050 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET1 ((0x0051 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET2 ((0x0052 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET0_LEVEL ((0x0060 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET1_LEVEL ((0x0061 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET2_LEVEL ((0x0062 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET0_MASK ((0x0070 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET1_MASK ((0x0071 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET2_MASK ((0x0072 << 2) + 0xfe002000)
+#define RESETCTRL_RESET0_LOCK ((0x0080 << 2) + 0xfe002000)
+#define RESETCTRL_RESET1_LOCK ((0x0081 << 2) + 0xfe002000)
+#define RESETCTRL_RESET2_LOCK ((0x0082 << 2) + 0xfe002000)
+#define RESETCTRL_RESET3_LOCK ((0x0083 << 2) + 0xfe002000)
+#define RESETCTRL_RESET4_LOCK ((0x0084 << 2) + 0xfe002000)
+#define RESETCTRL_RESET5_LOCK ((0x0085 << 2) + 0xfe002000)
+#define RESETCTRL_RESET6_LOCK ((0x0086 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET0_LOCK ((0x0088 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET1_LOCK ((0x0089 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET2_LOCK ((0x008a << 2) + 0xfe002000)
+#define RESETCTRL_RESET0_PROT ((0x0090 << 2) + 0xfe002000)
+#define RESETCTRL_RESET1_PROT ((0x0091 << 2) + 0xfe002000)
+#define RESETCTRL_RESET2_PROT ((0x0092 << 2) + 0xfe002000)
+#define RESETCTRL_RESET3_PROT ((0x0093 << 2) + 0xfe002000)
+#define RESETCTRL_RESET4_PROT ((0x0094 << 2) + 0xfe002000)
+#define RESETCTRL_RESET5_PROT ((0x0095 << 2) + 0xfe002000)
+#define RESETCTRL_RESET6_PROT ((0x0096 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET0_PROT ((0x0098 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET1_PROT ((0x0099 << 2) + 0xfe002000)
+#define RESETCTRL_SEC_RESET2_PROT ((0x009a << 2) + 0xfe002000)
+//========================================================================
+// CPU_CTRL
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe00e000
+// -----------------------------------------------
+#define CPUCTRL_SYS_A73_RESET_CNTL ((0x0040 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_CLK_CTRL0 ((0x0041 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_CLK_CTRL1 ((0x0042 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_CLK_CTRL2 ((0x0043 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_RESET_CNTL ((0x0050 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CLK_CTRL0 ((0x0051 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CLK_CTRL1 ((0x0052 << 2) + 0xfe00e000)
+//`define CPUCTRL_SYS_CPU_CLK_CTRL4 8'h55
+//`define CPUCTRL_SYS_CPU_CLK_CTRL5 8'h56
+//`define CPUCTRL_SYS_CPU_CLK_CTRL6 8'h57
+#define CPUCTRL_SYS_CPU_CLK_RESULT ((0x0058 << 2) + 0xfe00e000)
+#define CPUCTRL_ROM_DISABLE ((0x0060 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_PERIPHBASE ((0x0080 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_TARGETID ((0x0081 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_POR_CFG0 ((0x0090 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_POR_CFG1 ((0x0091 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG0 ((0x0092 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG1 ((0x0093 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG2 ((0x0094 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG3 ((0x0095 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG4 ((0x0096 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG5 ((0x0097 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG6 ((0x0098 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG7 ((0x0099 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG8 ((0x009a << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_CFG9 ((0x009b << 2) + 0xfe00e000)
+//`define CPUCTRL_SYS_CPU_CFG10 8'h9c
+//`define CPUCTRL_SYS_CPU_CFG11 8'h9d
+//`define CPUCTRL_SYS_CPU_CFG12 8'h9e
+//`define CPUCTRL_SYS_CPU_CFG13 8'h9f
+#define CPUCTRL_SYS_CPU_STATUS0 ((0x00a0 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS1 ((0x00a1 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS2 ((0x00a2 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS3 ((0x00a3 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS4 ((0x00a4 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_CPU_STATUS5 ((0x00a5 << 2) + 0xfe00e000)
+//`define CPUCTRL_SYS_CPU_STATUS6 8'ha6
+//`define CPUCTRL_SYS_CPU_STATUS7 8'ha7
+#define CPUCTRL_SYS_A73_PERIPHBASE ((0x00b0 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_POR_CFG0 ((0x00c0 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_POR_CFG1 ((0x00c1 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_CFG0 ((0x00c2 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_CFG1 ((0x00c3 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_CFG2 ((0x00c4 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_CFG3 ((0x00c5 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_CFG4 ((0x00c6 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_CFG5 ((0x00c7 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_CFG6 ((0x00c8 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_CFG7 ((0x00c9 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_CFG8 ((0x00ca << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_CFG9 ((0x00cb << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_STATUS0 ((0x00d0 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_STATUS1 ((0x00d1 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_STATUS2 ((0x00d2 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_STATUS3 ((0x00d3 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_STATUS4 ((0x00d4 << 2) + 0xfe00e000)
+#define CPUCTRL_SYS_A73_STATUS5 ((0x00d5 << 2) + 0xfe00e000)
+//========================================================================
+// SAR_ADC
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe026000
+// -----------------------------------------------
+#define SAR_ADC_REG0 ((0x0000 << 2) + 0xfe026000)
+#define SAR_ADC_CHAN_LIST ((0x0001 << 2) + 0xfe026000)
+#define SAR_ADC_AVG_CNTL ((0x0002 << 2) + 0xfe026000)
+#define SAR_ADC_REG3 ((0x0003 << 2) + 0xfe026000)
+#define SAR_ADC_DELAY ((0x0004 << 2) + 0xfe026000)
+#define SAR_ADC_LAST_RD ((0x0005 << 2) + 0xfe026000)
+#define SAR_ADC_FIFO_RD ((0x0006 << 2) + 0xfe026000)
+#define SAR_ADC_AUX_SW ((0x0007 << 2) + 0xfe026000)
+#define SAR_ADC_CHAN_10_SW ((0x0008 << 2) + 0xfe026000)
+#define SAR_ADC_DETECT_IDLE_SW ((0x0009 << 2) + 0xfe026000)
+#define SAR_ADC_DELTA_10 ((0x000a << 2) + 0xfe026000)
+#define SAR_ADC_REG11 ((0x000b << 2) + 0xfe026000)
+#define SAR_ADC_REG12 ((0x000c << 2) + 0xfe026000)
+#define SAR_ADC_REG13 ((0x000d << 2) + 0xfe026000)
+#define SAR_ADC_CHNL01 ((0x000e << 2) + 0xfe026000)
+#define SAR_ADC_CHNL23 ((0x000f << 2) + 0xfe026000)
+#define SAR_ADC_CHNL45 ((0x0010 << 2) + 0xfe026000)
+#define SAR_ADC_CHNL67 ((0x0011 << 2) + 0xfe026000)
+//========================================================================
+// ANA_CTRL - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe008000
+// -----------------------------------------------
+#define ANACTRL_SYS0PLL_CTRL0 ((0x0000 << 2) + 0xfe008000)
+#define ANACTRL_SYS0PLL_CTRL1 ((0x0001 << 2) + 0xfe008000)
+#define ANACTRL_SYS0PLL_CTRL2 ((0x0002 << 2) + 0xfe008000)
+#define ANACTRL_SYS0PLL_CTRL3 ((0x0003 << 2) + 0xfe008000)
+#define ANACTRL_SYS0PLL_STS ((0x0004 << 2) + 0xfe008000)
+#define ANACTRL_SYS1PLL_CTRL0 ((0x0008 << 2) + 0xfe008000)
+#define ANACTRL_SYS1PLL_CTRL1 ((0x0009 << 2) + 0xfe008000)
+#define ANACTRL_SYS1PLL_CTRL2 ((0x000a << 2) + 0xfe008000)
+#define ANACTRL_SYS1PLL_CTRL3 ((0x000b << 2) + 0xfe008000)
+#define ANACTRL_SYS1PLL_STS ((0x000c << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL0 ((0x0010 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL1 ((0x0011 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL2 ((0x0012 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL3 ((0x0013 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL4 ((0x0014 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL5 ((0x0015 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_CTRL6 ((0x0016 << 2) + 0xfe008000)
+#define ANACTRL_FIXPLL_STS ((0x0017 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL0 ((0x0020 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL1 ((0x0021 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL2 ((0x0022 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL3 ((0x0023 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL4 ((0x0024 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL5 ((0x0025 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_CTRL6 ((0x0026 << 2) + 0xfe008000)
+#define ANACTRL_GP0PLL_STS ((0x0027 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_CTRL0 ((0x0030 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_CTRL1 ((0x0031 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_CTRL2 ((0x0032 << 2) + 0xfe008000)
+#define ANACTRL_GP1PLL_CTRL3 ((0x0033 << 2) + 0xfe008000)
+//`define ANACTRL_GP1PLL_CTRL4 8'h34
+//`define ANACTRL_GP1PLL_CTRL5 8'h35
+//`define ANACTRL_GP1PLL_CTRL6 8'h36
+#define ANACTRL_GP1PLL_STS ((0x0037 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL0 ((0x0040 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL1 ((0x0041 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL2 ((0x0042 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL3 ((0x0043 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL4 ((0x0044 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL5 ((0x0045 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_CTRL6 ((0x0046 << 2) + 0xfe008000)
+#define ANACTRL_HIFIPLL_STS ((0x0047 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_CTRL0 ((0x0050 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_CTRL1 ((0x0051 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_CTRL2 ((0x0052 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_CTRL3 ((0x0053 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_CTRL4 ((0x0054 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_CTRL5 ((0x0055 << 2) + 0xfe008000)
+#define ANACTRL_PCIEPLL_STS ((0x0056 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL0 ((0x0060 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL1 ((0x0061 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL2 ((0x0062 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL3 ((0x0063 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL4 ((0x0064 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL5 ((0x0065 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL6 ((0x0066 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL7 ((0x0067 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_CTRL8 ((0x0068 << 2) + 0xfe008000)
+#define ANACTRL_MPLL_STS ((0x0069 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL0 ((0x0070 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL1 ((0x0071 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL2 ((0x0072 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL3 ((0x0073 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL4 ((0x0074 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL5 ((0x0075 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_CTRL6 ((0x0076 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_STS ((0x0077 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPLL_VLOCK ((0x0079 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_CTRL0 ((0x0080 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_CTRL1 ((0x0081 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_CTRL2 ((0x0082 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_CTRL3 ((0x0083 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_CTRL4 ((0x0084 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_CTRL5 ((0x0085 << 2) + 0xfe008000)
+#define ANACTRL_HDMIPHY_STS ((0x0086 << 2) + 0xfe008000)
+#define ANACTRL_MIPICSI_CTRL0 ((0x0090 << 2) + 0xfe008000)
+#define ANACTRL_MIPICSI_CTRL1 ((0x0091 << 2) + 0xfe008000)
+#define ANACTRL_MIPICSI_CTRL2 ((0x0092 << 2) + 0xfe008000)
+#define ANACTRL_MIPICSI_CTRL3 ((0x0093 << 2) + 0xfe008000)
+#define ANACTRL_MIPICSI_CTRL4 ((0x0094 << 2) + 0xfe008000)
+#define ANACTRL_MIPICSI_CTRL5 ((0x0095 << 2) + 0xfe008000)
+#define ANACTRL_MIPIDSI_CTRL0 ((0x00a0 << 2) + 0xfe008000)
+#define ANACTRL_MIPIDSI_CTRL1 ((0x00a1 << 2) + 0xfe008000)
+#define ANACTRL_MIPIDSI_CTRL2 ((0x00a2 << 2) + 0xfe008000)
+#define ANACTRL_MIPIDSI_STS ((0x00a3 << 2) + 0xfe008000)
+//`define ANACTRL_VDAC_CTRL0 8'hB0
+//`define ANACTRL_VDAC_CTRL1 8'hB1
+#define ANACTRL_POR_CTRL ((0x00b6 << 2) + 0xfe008000)
+#define ANACTRL_LOCK_BIT ((0x00b8 << 2) + 0xfe008000)
+#define ANACTRL_PROT_BIT ((0x00b9 << 2) + 0xfe008000)
+#define ANACTRL_MCLK_PLL_CNTL0 ((0x00c0 << 2) + 0xfe008000)
+#define ANACTRL_MCLK_PLL_CNTL1 ((0x00c1 << 2) + 0xfe008000)
+#define ANACTRL_MCLK_PLL_CNTL2 ((0x00c2 << 2) + 0xfe008000)
+#define ANACTRL_MCLK_PLL_CNTL3 ((0x00c3 << 2) + 0xfe008000)
+#define ANACTRL_MCLK_PLL_CNTL4 ((0x00c4 << 2) + 0xfe008000)
+#define ANACTRL_MCLK_PLL_STS ((0x00c5 << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL1 ((0x00c8 << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL2 ((0x00c9 << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL3 ((0x00ca << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL4 ((0x00cb << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL5 ((0x00cc << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL6 ((0x00cd << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL7 ((0x00ce << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL8 ((0x00cf << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL9 ((0x00d0 << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL10 ((0x00d1 << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL11 ((0x00d2 << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL12 ((0x00d3 << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL13 ((0x00d4 << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL14 ((0x00d5 << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL15 ((0x00d6 << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL16 ((0x00d7 << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL17 ((0x00d8 << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL18 ((0x00d9 << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL19 ((0x00da << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL20 ((0x00db << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_CNTL21 ((0x00dc << 2) + 0xfe008000)
+#define ANACTRL_TCON_PLL0_CNTL0 ((0x00e0 << 2) + 0xfe008000)
+#define ANACTRL_TCON_PLL0_CNTL1 ((0x00e1 << 2) + 0xfe008000)
+#define ANACTRL_TCON_PLL0_CNTL2 ((0x00e2 << 2) + 0xfe008000)
+#define ANACTRL_TCON_PLL0_CNTL3 ((0x00e3 << 2) + 0xfe008000)
+#define ANACTRL_TCON_PLL0_CNTL4 ((0x00e4 << 2) + 0xfe008000)
+#define ANACTRL_TCON_PLL1_CNTL0 ((0x00e5 << 2) + 0xfe008000)
+#define ANACTRL_TCON_PLL1_CNTL1 ((0x00e6 << 2) + 0xfe008000)
+#define ANACTRL_TCON_PLL1_CNTL2 ((0x00e7 << 2) + 0xfe008000)
+#define ANACTRL_TCON_PLL1_CNTL3 ((0x00e8 << 2) + 0xfe008000)
+#define ANACTRL_TCON_PLL1_CNTL4 ((0x00e9 << 2) + 0xfe008000)
+#define ANACTRL_TCON_PLL2_CNTL0 ((0x00ea << 2) + 0xfe008000)
+#define ANACTRL_TCON_PLL2_CNTL1 ((0x00eb << 2) + 0xfe008000)
+#define ANACTRL_TCON_PLL2_CNTL2 ((0x00ec << 2) + 0xfe008000)
+#define ANACTRL_TCON_PLL2_CNTL3 ((0x00ed << 2) + 0xfe008000)
+#define ANACTRL_TCON_PLL2_CNTL4 ((0x00ee << 2) + 0xfe008000)
+#define ANACTRL_TCON_PLL0_STS ((0x00ef << 2) + 0xfe008000)
+#define ANACTRL_TCON_PLL1_STS ((0x00f0 << 2) + 0xfe008000)
+#define ANACTRL_TCON_PLL2_STS ((0x00f1 << 2) + 0xfe008000)
+#define ANACTRL_TCON_PLL_VLOCK ((0x00f2 << 2) + 0xfe008000)
+#define ANACTRL_DIF_PHY_STS ((0x00f3 << 2) + 0xfe008000)
+//========================================================================
+// Ethernet Phy
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe028000
+// -----------------------------------------------
+#define ETH_PHY_DBG_CTL0 ((0x0000 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_CTL1 ((0x0001 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_CFG0 ((0x0002 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_CFG1 ((0x0003 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_CFG2 ((0x0004 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_CFG3 ((0x0005 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_CFG4 ((0x0006 << 2) + 0xfe028000)
+#define ETH_PLL_STS ((0x0010 << 2) + 0xfe028000)
+#define ETH_PLL_CTL0 ((0x0011 << 2) + 0xfe028000)
+#define ETH_PLL_CTL1 ((0x0012 << 2) + 0xfe028000)
+#define ETH_PLL_CTL2 ((0x0013 << 2) + 0xfe028000)
+#define ETH_PLL_CTL3 ((0x0014 << 2) + 0xfe028000)
+#define ETH_PLL_CTL4 ((0x0015 << 2) + 0xfe028000)
+#define ETH_PLL_CTL5 ((0x0016 << 2) + 0xfe028000)
+#define ETH_PLL_CTL6 ((0x0017 << 2) + 0xfe028000)
+#define ETH_PLL_CTL7 ((0x0018 << 2) + 0xfe028000)
+#define ETH_PHY_CNTL0 ((0x0020 << 2) + 0xfe028000)
+#define ETH_PHY_CNTL1 ((0x0021 << 2) + 0xfe028000)
+#define ETH_PHY_CNTL2 ((0x0022 << 2) + 0xfe028000)
+#define ETH_PHY_CNTL3 ((0x0023 << 2) + 0xfe028000)
+#define ETH_PHY_STS0 ((0x0025 << 2) + 0xfe028000)
+#define ETH_PHY_STS1 ((0x0026 << 2) + 0xfe028000)
+#define ETH_PHY_STS2 ((0x0027 << 2) + 0xfe028000)
+#define ETH_PHY_DBG_REG ((0x0028 << 2) + 0xfe028000)
+//========================================================================
+// Ethernet TOP
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe024000
+// -----------------------------------------------
+#define ETHTOP_CNTL0 ((0x0000 << 2) + 0xfe024000)
+#define ETHTOP_CNTL1 ((0x0001 << 2) + 0xfe024000)
+#define ETHTOP_CNTL2 ((0x0002 << 2) + 0xfe024000)
+#define ETHTOP_CNTL3 ((0x0003 << 2) + 0xfe024000)
+#define ETHTOP_STS0 ((0x0008 << 2) + 0xfe024000)
+#define ETHTOP_STS1 ((0x0009 << 2) + 0xfe024000)
+#define ETHTOP_STS2 ((0x000a << 2) + 0xfe024000)
+#define ETHTOP_STS3 ((0x000b << 2) + 0xfe024000)
+//========================================================================
+// I2C Slave A
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe064000
+// -----------------------------------------------
+#define I2C_S_A_CONTROL_REG ((0x0000 << 2) + 0xfe064000)
+#define I2C_S_A_SEND_REG ((0x0001 << 2) + 0xfe064000)
+#define I2C_S_A_RECV_REG ((0x0002 << 2) + 0xfe064000)
+#define I2C_S_A_CNTL1_REG ((0x0003 << 2) + 0xfe064000)
+//========================================================================
+// IR RX/TX
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe084000
+// -----------------------------------------------
+#define IRCTRL_IR_DEC_LDR_ACTIVE ((0x0000 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_LDR_IDLE ((0x0001 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_LDR_REPEAT ((0x0002 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_BIT_0 ((0x0003 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_REG0 ((0x0004 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_FRAME ((0x0005 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_STATUS ((0x0006 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_REG1 ((0x0007 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_LDR_ACTIVE ((0x0010 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_LDR_IDLE ((0x0011 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_LDR_REPEAT ((0x0012 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_BIT_0 ((0x0013 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_REG0 ((0x0014 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_FRAME ((0x0015 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_STATUS ((0x0016 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_REG1 ((0x0017 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_REG2 ((0x0018 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_DURATN2 ((0x0019 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_DURATN3 ((0x001a << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_FRAME1 ((0x001b << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_STATUS1 ((0x001c << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_STATUS2 ((0x001d << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_REG3 ((0x001e << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_FRAME_RSV0 ((0x001f << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_FRAME_RSV1 ((0x0020 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_FILTE ((0x0021 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_IRQ_CTL ((0x0022 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_FIFO_CTL ((0x0023 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_WIDTH_NEW ((0x0024 << 2) + 0xfe084000)
+#define IRCTRL_MF_IR_DEC_REPEAT_DET ((0x0025 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_CNTL0 ((0x0030 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_CNTL1 ((0x0031 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_IIR_THD ((0x0032 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_THD0 ((0x0033 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_THD1 ((0x0034 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_SUM_CNT0 ((0x0035 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_SUM_CNT1 ((0x0036 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_CNT0 ((0x0037 << 2) + 0xfe084000)
+#define IRCTRL_IR_DEC_DEMOD_CNT1 ((0x0038 << 2) + 0xfe084000)
+#define IRCTRL_IR_BLASTER_ADDR0 ((0x0043 << 2) + 0xfe084000)
+#define IRCTRL_IR_BLASTER_ADDR1 ((0x0044 << 2) + 0xfe084000)
+#define IRCTRL_IR_BLASTER_ADDR2 ((0x0045 << 2) + 0xfe084000)
+#define IRCTRL_IR_BLASTER_ADDR3 ((0x0046 << 2) + 0xfe084000)
+//========================================================================
+// I2C Master AO_A
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe076000
+// -----------------------------------------------
+#define I2C_M_AO_A_CONTROL_REG ((0x0000 << 2) + 0xfe076000)
+#define I2C_M_AO_A_SLAVE_ADDR ((0x0001 << 2) + 0xfe076000)
+#define I2C_M_AO_A_TOKEN_LIST0 ((0x0002 << 2) + 0xfe076000)
+#define I2C_M_AO_A_TOKEN_LIST1 ((0x0003 << 2) + 0xfe076000)
+#define I2C_M_AO_A_WDATA_REG0 ((0x0004 << 2) + 0xfe076000)
+#define I2C_M_AO_A_WDATA_REG1 ((0x0005 << 2) + 0xfe076000)
+#define I2C_M_AO_A_RDATA_REG0 ((0x0006 << 2) + 0xfe076000)
+#define I2C_M_AO_A_RDATA_REG1 ((0x0007 << 2) + 0xfe076000)
+#define I2C_M_AO_A_TIMEOUT_TH ((0x0008 << 2) + 0xfe076000)
+#define I2C_M_AO_A_CNTL_DELY1 ((0x0009 << 2) + 0xfe076000)
+#define I2C_M_AO_A_CNTL_DELY2 ((0x000a << 2) + 0xfe076000)
+#define I2C_M_AO_A_LOW_DELY ((0x000b << 2) + 0xfe076000)
+#define I2C_M_AO_A_HIGH_DELY ((0x000c << 2) + 0xfe076000)
+#define I2C_M_AO_A_FIFO_CTRL0 ((0x000d << 2) + 0xfe076000)
+#define I2C_M_AO_A_FIFO_CTRL1 ((0x000e << 2) + 0xfe076000)
+#define I2C_M_AO_A_FIFO_PENDING ((0x000f << 2) + 0xfe076000)
+#define I2C_M_AO_A_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe076000)
+#define I2C_M_AO_A_FIFO_ST0 ((0x0011 << 2) + 0xfe076000)
+//========================================================================
+// I2C Master AO_B
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe086000
+// -----------------------------------------------
+#define I2C_M_AO_B_CONTROL_REG ((0x0000 << 2) + 0xfe086000)
+#define I2C_M_AO_B_SLAVE_ADDR ((0x0001 << 2) + 0xfe086000)
+#define I2C_M_AO_B_TOKEN_LIST0 ((0x0002 << 2) + 0xfe086000)
+#define I2C_M_AO_B_TOKEN_LIST1 ((0x0003 << 2) + 0xfe086000)
+#define I2C_M_AO_B_WDATA_REG0 ((0x0004 << 2) + 0xfe086000)
+#define I2C_M_AO_B_WDATA_REG1 ((0x0005 << 2) + 0xfe086000)
+#define I2C_M_AO_B_RDATA_REG0 ((0x0006 << 2) + 0xfe086000)
+#define I2C_M_AO_B_RDATA_REG1 ((0x0007 << 2) + 0xfe086000)
+#define I2C_M_AO_B_TIMEOUT_TH ((0x0008 << 2) + 0xfe086000)
+#define I2C_M_AO_B_CNTL_DELY1 ((0x0009 << 2) + 0xfe086000)
+#define I2C_M_AO_B_CNTL_DELY2 ((0x000a << 2) + 0xfe086000)
+#define I2C_M_AO_B_LOW_DELY ((0x000b << 2) + 0xfe086000)
+#define I2C_M_AO_B_HIGH_DELY ((0x000c << 2) + 0xfe086000)
+#define I2C_M_AO_B_FIFO_CTRL0 ((0x000d << 2) + 0xfe086000)
+#define I2C_M_AO_B_FIFO_CTRL1 ((0x000e << 2) + 0xfe086000)
+#define I2C_M_AO_B_FIFO_PENDING ((0x000f << 2) + 0xfe086000)
+#define I2C_M_AO_B_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe086000)
+#define I2C_M_AO_B_FIFO_ST0 ((0x0011 << 2) + 0xfe086000)
+//========================================================================
+// I2C Master A
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe066000
+// -----------------------------------------------
+#define I2C_M_A_CONTROL_REG ((0x0000 << 2) + 0xfe066000)
+#define I2C_M_A_SLAVE_ADDR ((0x0001 << 2) + 0xfe066000)
+#define I2C_M_A_TOKEN_LIST0 ((0x0002 << 2) + 0xfe066000)
+#define I2C_M_A_TOKEN_LIST1 ((0x0003 << 2) + 0xfe066000)
+#define I2C_M_A_WDATA_REG0 ((0x0004 << 2) + 0xfe066000)
+#define I2C_M_A_WDATA_REG1 ((0x0005 << 2) + 0xfe066000)
+#define I2C_M_A_RDATA_REG0 ((0x0006 << 2) + 0xfe066000)
+#define I2C_M_A_RDATA_REG1 ((0x0007 << 2) + 0xfe066000)
+#define I2C_M_A_TIMEOUT_TH ((0x0008 << 2) + 0xfe066000)
+#define I2C_M_A_CNTL_DELY1 ((0x0009 << 2) + 0xfe066000)
+#define I2C_M_A_CNTL_DELY2 ((0x000a << 2) + 0xfe066000)
+#define I2C_M_A_LOW_DELY ((0x000b << 2) + 0xfe066000)
+#define I2C_M_A_HIGH_DELY ((0x000c << 2) + 0xfe066000)
+#define I2C_M_A_FIFO_CTRL0 ((0x000d << 2) + 0xfe066000)
+#define I2C_M_A_FIFO_CTRL1 ((0x000e << 2) + 0xfe066000)
+#define I2C_M_A_FIFO_PENDING ((0x000f << 2) + 0xfe066000)
+#define I2C_M_A_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe066000)
+#define I2C_M_A_FIFO_ST0 ((0x0011 << 2) + 0xfe066000)
+//========================================================================
+// I2C Master B
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe068000
+// -----------------------------------------------
+#define I2C_M_B_CONTROL_REG ((0x0000 << 2) + 0xfe068000)
+#define I2C_M_B_SLAVE_ADDR ((0x0001 << 2) + 0xfe068000)
+#define I2C_M_B_TOKEN_LIST0 ((0x0002 << 2) + 0xfe068000)
+#define I2C_M_B_TOKEN_LIST1 ((0x0003 << 2) + 0xfe068000)
+#define I2C_M_B_WDATA_REG0 ((0x0004 << 2) + 0xfe068000)
+#define I2C_M_B_WDATA_REG1 ((0x0005 << 2) + 0xfe068000)
+#define I2C_M_B_RDATA_REG0 ((0x0006 << 2) + 0xfe068000)
+#define I2C_M_B_RDATA_REG1 ((0x0007 << 2) + 0xfe068000)
+#define I2C_M_B_TIMEOUT_TH ((0x0008 << 2) + 0xfe068000)
+#define I2C_M_B_CNTL_DELY1 ((0x0009 << 2) + 0xfe068000)
+#define I2C_M_B_CNTL_DELY2 ((0x000a << 2) + 0xfe068000)
+#define I2C_M_B_LOW_DELY ((0x000b << 2) + 0xfe068000)
+#define I2C_M_B_HIGH_DELY ((0x000c << 2) + 0xfe068000)
+#define I2C_M_B_FIFO_CTRL0 ((0x000d << 2) + 0xfe068000)
+#define I2C_M_B_FIFO_CTRL1 ((0x000e << 2) + 0xfe068000)
+#define I2C_M_B_FIFO_PENDING ((0x000f << 2) + 0xfe068000)
+#define I2C_M_B_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe068000)
+#define I2C_M_B_FIFO_ST0 ((0x0011 << 2) + 0xfe068000)
+//========================================================================
+// I2C Master C
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe06a000
+// -----------------------------------------------
+#define I2C_M_C_CONTROL_REG ((0x0000 << 2) + 0xfe06a000)
+#define I2C_M_C_SLAVE_ADDR ((0x0001 << 2) + 0xfe06a000)
+#define I2C_M_C_TOKEN_LIST0 ((0x0002 << 2) + 0xfe06a000)
+#define I2C_M_C_TOKEN_LIST1 ((0x0003 << 2) + 0xfe06a000)
+#define I2C_M_C_WDATA_REG0 ((0x0004 << 2) + 0xfe06a000)
+#define I2C_M_C_WDATA_REG1 ((0x0005 << 2) + 0xfe06a000)
+#define I2C_M_C_RDATA_REG0 ((0x0006 << 2) + 0xfe06a000)
+#define I2C_M_C_RDATA_REG1 ((0x0007 << 2) + 0xfe06a000)
+#define I2C_M_C_TIMEOUT_TH ((0x0008 << 2) + 0xfe06a000)
+#define I2C_M_C_CNTL_DELY1 ((0x0009 << 2) + 0xfe06a000)
+#define I2C_M_C_CNTL_DELY2 ((0x000a << 2) + 0xfe06a000)
+#define I2C_M_C_LOW_DELY ((0x000b << 2) + 0xfe06a000)
+#define I2C_M_C_HIGH_DELY ((0x000c << 2) + 0xfe06a000)
+#define I2C_M_C_FIFO_CTRL0 ((0x000d << 2) + 0xfe06a000)
+#define I2C_M_C_FIFO_CTRL1 ((0x000e << 2) + 0xfe06a000)
+#define I2C_M_C_FIFO_PENDING ((0x000f << 2) + 0xfe06a000)
+#define I2C_M_C_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe06a000)
+#define I2C_M_C_FIFO_ST0 ((0x0011 << 2) + 0xfe06a000)
+//========================================================================
+// I2C Master D
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe06c000
+// -----------------------------------------------
+#define I2C_M_D_CONTROL_REG ((0x0000 << 2) + 0xfe06c000)
+#define I2C_M_D_SLAVE_ADDR ((0x0001 << 2) + 0xfe06c000)
+#define I2C_M_D_TOKEN_LIST0 ((0x0002 << 2) + 0xfe06c000)
+#define I2C_M_D_TOKEN_LIST1 ((0x0003 << 2) + 0xfe06c000)
+#define I2C_M_D_WDATA_REG0 ((0x0004 << 2) + 0xfe06c000)
+#define I2C_M_D_WDATA_REG1 ((0x0005 << 2) + 0xfe06c000)
+#define I2C_M_D_RDATA_REG0 ((0x0006 << 2) + 0xfe06c000)
+#define I2C_M_D_RDATA_REG1 ((0x0007 << 2) + 0xfe06c000)
+#define I2C_M_D_TIMEOUT_TH ((0x0008 << 2) + 0xfe06c000)
+#define I2C_M_D_CNTL_DELY1 ((0x0009 << 2) + 0xfe06c000)
+#define I2C_M_D_CNTL_DELY2 ((0x000a << 2) + 0xfe06c000)
+#define I2C_M_D_LOW_DELY ((0x000b << 2) + 0xfe06c000)
+#define I2C_M_D_HIGH_DELY ((0x000c << 2) + 0xfe06c000)
+#define I2C_M_D_FIFO_CTRL0 ((0x000d << 2) + 0xfe06c000)
+#define I2C_M_D_FIFO_CTRL1 ((0x000e << 2) + 0xfe06c000)
+#define I2C_M_D_FIFO_PENDING ((0x000f << 2) + 0xfe06c000)
+#define I2C_M_D_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe06c000)
+#define I2C_M_D_FIFO_ST0 ((0x0011 << 2) + 0xfe06c000)
+//========================================================================
+// I2C Master E
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe06e000
+// -----------------------------------------------
+#define I2C_M_E_CONTROL_REG ((0x0000 << 2) + 0xfe06e000)
+#define I2C_M_E_SLAVE_ADDR ((0x0001 << 2) + 0xfe06e000)
+#define I2C_M_E_TOKEN_LIST0 ((0x0002 << 2) + 0xfe06e000)
+#define I2C_M_E_TOKEN_LIST1 ((0x0003 << 2) + 0xfe06e000)
+#define I2C_M_E_WDATA_REG0 ((0x0004 << 2) + 0xfe06e000)
+#define I2C_M_E_WDATA_REG1 ((0x0005 << 2) + 0xfe06e000)
+#define I2C_M_E_RDATA_REG0 ((0x0006 << 2) + 0xfe06e000)
+#define I2C_M_E_RDATA_REG1 ((0x0007 << 2) + 0xfe06e000)
+#define I2C_M_E_TIMEOUT_TH ((0x0008 << 2) + 0xfe06e000)
+#define I2C_M_E_CNTL_DELY1 ((0x0009 << 2) + 0xfe06e000)
+#define I2C_M_E_CNTL_DELY2 ((0x000a << 2) + 0xfe06e000)
+#define I2C_M_E_LOW_DELY ((0x000b << 2) + 0xfe06e000)
+#define I2C_M_E_HIGH_DELY ((0x000c << 2) + 0xfe06e000)
+#define I2C_M_E_FIFO_CTRL0 ((0x000d << 2) + 0xfe06e000)
+#define I2C_M_E_FIFO_CTRL1 ((0x000e << 2) + 0xfe06e000)
+#define I2C_M_E_FIFO_PENDING ((0x000f << 2) + 0xfe06e000)
+#define I2C_M_E_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe06e000)
+#define I2C_M_E_FIFO_ST0 ((0x0011 << 2) + 0xfe06e000)
+//========================================================================
+// I2C Master F
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe070000
+// -----------------------------------------------
+#define I2C_M_F_CONTROL_REG ((0x0000 << 2) + 0xfe070000)
+#define I2C_M_F_SLAVE_ADDR ((0x0001 << 2) + 0xfe070000)
+#define I2C_M_F_TOKEN_LIST0 ((0x0002 << 2) + 0xfe070000)
+#define I2C_M_F_TOKEN_LIST1 ((0x0003 << 2) + 0xfe070000)
+#define I2C_M_F_WDATA_REG0 ((0x0004 << 2) + 0xfe070000)
+#define I2C_M_F_WDATA_REG1 ((0x0005 << 2) + 0xfe070000)
+#define I2C_M_F_RDATA_REG0 ((0x0006 << 2) + 0xfe070000)
+#define I2C_M_F_RDATA_REG1 ((0x0007 << 2) + 0xfe070000)
+#define I2C_M_F_TIMEOUT_TH ((0x0008 << 2) + 0xfe070000)
+#define I2C_M_F_CNTL_DELY1 ((0x0009 << 2) + 0xfe070000)
+#define I2C_M_F_CNTL_DELY2 ((0x000a << 2) + 0xfe070000)
+#define I2C_M_F_LOW_DELY ((0x000b << 2) + 0xfe070000)
+#define I2C_M_F_HIGH_DELY ((0x000c << 2) + 0xfe070000)
+#define I2C_M_F_FIFO_CTRL0 ((0x000d << 2) + 0xfe070000)
+#define I2C_M_F_FIFO_CTRL1 ((0x000e << 2) + 0xfe070000)
+#define I2C_M_F_FIFO_PENDING ((0x000f << 2) + 0xfe070000)
+#define I2C_M_F_FIFO_PENDING_MASK ((0x0010 << 2) + 0xfe070000)
+#define I2C_M_F_FIFO_ST0 ((0x0011 << 2) + 0xfe070000)
+//========================================================================
+// APB0_UART_A - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe078000
+// -----------------------------------------------
+#define UART_A_WFIFO ((0x0000 << 2) + 0xfe078000)
+#define UART_A_RFIFO ((0x0001 << 2) + 0xfe078000)
+#define UART_A_CONTROL ((0x0002 << 2) + 0xfe078000)
+#define UART_A_STATUS ((0x0003 << 2) + 0xfe078000)
+#define UART_A_MISC ((0x0004 << 2) + 0xfe078000)
+#define UART_A_REG5 ((0x0005 << 2) + 0xfe078000)
+//========================================================================
+// APB0_UART_B - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe07a000
+// -----------------------------------------------
+#define UART_B_WFIFO ((0x0000 << 2) + 0xfe07a000)
+#define UART_B_RFIFO ((0x0001 << 2) + 0xfe07a000)
+#define UART_B_CONTROL ((0x0002 << 2) + 0xfe07a000)
+#define UART_B_STATUS ((0x0003 << 2) + 0xfe07a000)
+#define UART_B_MISC ((0x0004 << 2) + 0xfe07a000)
+#define UART_B_REG5 ((0x0005 << 2) + 0xfe07a000)
+//========================================================================
+// APB0_UART_C - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe07c000
+// -----------------------------------------------
+#define UART_C_WFIFO ((0x0000 << 2) + 0xfe07c000)
+#define UART_C_RFIFO ((0x0001 << 2) + 0xfe07c000)
+#define UART_C_CONTROL ((0x0002 << 2) + 0xfe07c000)
+#define UART_C_STATUS ((0x0003 << 2) + 0xfe07c000)
+#define UART_C_MISC ((0x0004 << 2) + 0xfe07c000)
+#define UART_C_REG5 ((0x0005 << 2) + 0xfe07c000)
+//========================================================================
+// APB0_UART_D - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe07e000
+// -----------------------------------------------
+#define UART_D_WFIFO ((0x0000 << 2) + 0xfe07e000)
+#define UART_D_RFIFO ((0x0001 << 2) + 0xfe07e000)
+#define UART_D_CONTROL ((0x0002 << 2) + 0xfe07e000)
+#define UART_D_STATUS ((0x0003 << 2) + 0xfe07e000)
+#define UART_D_MISC ((0x0004 << 2) + 0xfe07e000)
+#define UART_D_REG5 ((0x0005 << 2) + 0xfe07e000)
+//========================================================================
+// APB0_UART_E - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe080000
+// -----------------------------------------------
+#define UART_E_WFIFO ((0x0000 << 2) + 0xfe080000)
+#define UART_E_RFIFO ((0x0001 << 2) + 0xfe080000)
+#define UART_E_CONTROL ((0x0002 << 2) + 0xfe080000)
+#define UART_E_STATUS ((0x0003 << 2) + 0xfe080000)
+#define UART_E_MISC ((0x0004 << 2) + 0xfe080000)
+#define UART_E_REG5 ((0x0005 << 2) + 0xfe080000)
+//========================================================================
+// APB0_UART_F - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe082000
+// -----------------------------------------------
+#define UART_F_WFIFO ((0x0000 << 2) + 0xfe082000)
+#define UART_F_RFIFO ((0x0001 << 2) + 0xfe082000)
+#define UART_F_CONTROL ((0x0002 << 2) + 0xfe082000)
+#define UART_F_STATUS ((0x0003 << 2) + 0xfe082000)
+#define UART_F_MISC ((0x0004 << 2) + 0xfe082000)
+#define UART_F_REG5 ((0x0005 << 2) + 0xfe082000)
+//========================================================================
+// PWM_AB - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe058000
+// -----------------------------------------------
+#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe058000)
+#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe058000)
+#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe058000)
+#define PWMAB_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe058000)
+#define PWMAB_TIME_AB ((0x0004 << 2) + 0xfe058000)
+#define PWMAB_A2 ((0x0005 << 2) + 0xfe058000)
+#define PWMAB_B2 ((0x0006 << 2) + 0xfe058000)
+#define PWMAB_BLINK_AB ((0x0007 << 2) + 0xfe058000)
+#define PWMAB_LOCK_AB ((0x0008 << 2) + 0xfe058000)
+//========================================================================
+// PWM_CD - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe05a000
+// -----------------------------------------------
+#define PWMCD_PWM_A ((0x0000 << 2) + 0xfe05a000)
+#define PWMCD_PWM_B ((0x0001 << 2) + 0xfe05a000)
+#define PWMCD_MISC_REG_AB ((0x0002 << 2) + 0xfe05a000)
+#define PWMCD_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe05a000)
+#define PWMCD_TIME_AB ((0x0004 << 2) + 0xfe05a000)
+#define PWMCD_A2 ((0x0005 << 2) + 0xfe05a000)
+#define PWMCD_B2 ((0x0006 << 2) + 0xfe05a000)
+#define PWMCD_BLINK_AB ((0x0007 << 2) + 0xfe05a000)
+#define PWMCD_LOCK_AB ((0x0008 << 2) + 0xfe05a000)
+//========================================================================
+// PWM_EF - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe05c000
+// -----------------------------------------------
+#define PWMEF_PWM_A ((0x0000 << 2) + 0xfe05c000)
+#define PWMEF_PWM_B ((0x0001 << 2) + 0xfe05c000)
+#define PWMEF_MISC_REG_AB ((0x0002 << 2) + 0xfe05c000)
+#define PWMEF_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe05c000)
+#define PWMEF_TIME_AB ((0x0004 << 2) + 0xfe05c000)
+#define PWMEF_A2 ((0x0005 << 2) + 0xfe05c000)
+#define PWMEF_B2 ((0x0006 << 2) + 0xfe05c000)
+#define PWMEF_BLINK_AB ((0x0007 << 2) + 0xfe05c000)
+#define PWMEF_LOCK_AB ((0x0008 << 2) + 0xfe05c000)
+//========================================================================
+// PWM_AO_AB - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe05e000
+// -----------------------------------------------
+#define PWM_AO_AB_PWM_A ((0x0000 << 2) + 0xfe05e000)
+#define PWM_AO_AB_PWM_B ((0x0001 << 2) + 0xfe05e000)
+#define PWM_AO_AB_MISC_REG_AB ((0x0002 << 2) + 0xfe05e000)
+#define PWM_AO_AB_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe05e000)
+#define PWM_AO_AB_TIME_AB ((0x0004 << 2) + 0xfe05e000)
+#define PWM_AO_AB_A2 ((0x0005 << 2) + 0xfe05e000)
+#define PWM_AO_AB_B2 ((0x0006 << 2) + 0xfe05e000)
+#define PWM_AO_AB_BLINK_AB ((0x0007 << 2) + 0xfe05e000)
+#define PWM_AO_AB_LOCK_AB ((0x0008 << 2) + 0xfe05e000)
+//========================================================================
+// PWM_AO_CD - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe060000
+// -----------------------------------------------
+#define PWM_AO_CD_PWM_A ((0x0000 << 2) + 0xfe060000)
+#define PWM_AO_CD_PWM_B ((0x0001 << 2) + 0xfe060000)
+#define PWM_AO_CD_MISC_REG_AB ((0x0002 << 2) + 0xfe060000)
+#define PWM_AO_CD_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe060000)
+#define PWM_AO_CD_TIME_AB ((0x0004 << 2) + 0xfe060000)
+#define PWM_AO_CD_A2 ((0x0005 << 2) + 0xfe060000)
+#define PWM_AO_CD_B2 ((0x0006 << 2) + 0xfe060000)
+#define PWM_AO_CD_BLINK_AB ((0x0007 << 2) + 0xfe060000)
+#define PWM_AO_CD_LOCK_AB ((0x0008 << 2) + 0xfe060000)
+//========================================================================
+// PWM_AO_EF - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe030000
+// -----------------------------------------------
+#define PWM_AO_EF_PWM_A ((0x0000 << 2) + 0xfe030000)
+#define PWM_AO_EF_PWM_B ((0x0001 << 2) + 0xfe030000)
+#define PWM_AO_EF_MISC_REG_AB ((0x0002 << 2) + 0xfe030000)
+#define PWM_AO_EF_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe030000)
+#define PWM_AO_EF_TIME_AB ((0x0004 << 2) + 0xfe030000)
+#define PWM_AO_EF_A2 ((0x0005 << 2) + 0xfe030000)
+#define PWM_AO_EF_B2 ((0x0006 << 2) + 0xfe030000)
+#define PWM_AO_EF_BLINK_AB ((0x0007 << 2) + 0xfe030000)
+#define PWM_AO_EF_LOCK_AB ((0x0008 << 2) + 0xfe030000)
+//========================================================================
+// PWM_AO_GH - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe032000
+// -----------------------------------------------
+#define PWM_AO_GH_PWM_A ((0x0000 << 2) + 0xfe032000)
+#define PWM_AO_GH_PWM_B ((0x0001 << 2) + 0xfe032000)
+#define PWM_AO_GH_MISC_REG_AB ((0x0002 << 2) + 0xfe032000)
+#define PWM_AO_GH_DELTA_SIGMA_AB ((0x0003 << 2) + 0xfe032000)
+#define PWM_AO_GH_TIME_AB ((0x0004 << 2) + 0xfe032000)
+#define PWM_AO_GH_A2 ((0x0005 << 2) + 0xfe032000)
+#define PWM_AO_GH_B2 ((0x0006 << 2) + 0xfe032000)
+#define PWM_AO_GH_BLINK_AB ((0x0007 << 2) + 0xfe032000)
+#define PWM_AO_GH_LOCK_AB ((0x0008 << 2) + 0xfe032000)
+//========================================================================
+// SPICC_0
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe050000
+// -----------------------------------------------
+#define SPICC0_RXDATA ((0x0000 << 2) + 0xfe050000)
+#define SPICC0_TXDATA ((0x0001 << 2) + 0xfe050000)
+#define SPICC0_CONREG ((0x0002 << 2) + 0xfe050000)
+#define SPICC0_INTREG ((0x0003 << 2) + 0xfe050000)
+#define SPICC0_DMAREG ((0x0004 << 2) + 0xfe050000)
+#define SPICC0_STATREG ((0x0005 << 2) + 0xfe050000)
+#define SPICC0_PERIODREG ((0x0006 << 2) + 0xfe050000)
+#define SPICC0_TESTREG ((0x0007 << 2) + 0xfe050000)
+#define SPICC0_DRADDR ((0x0008 << 2) + 0xfe050000)
+#define SPICC0_DWADDR ((0x0009 << 2) + 0xfe050000)
+#define SPICC0_LD_CNTL0 ((0x000a << 2) + 0xfe050000)
+#define SPICC0_LD_CNTL1 ((0x000b << 2) + 0xfe050000)
+#define SPICC0_LD_RADDR ((0x000c << 2) + 0xfe050000)
+#define SPICC0_LD_WADDR ((0x000d << 2) + 0xfe050000)
+#define SPICC0_ENHANCE_CNTL ((0x000e << 2) + 0xfe050000)
+#define SPICC0_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe050000)
+#define SPICC0_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe050000)
+//========================================================================
+// SPICC_1
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe052000
+// -----------------------------------------------
+#define SPICC1_RXDATA ((0x0000 << 2) + 0xfe052000)
+#define SPICC1_TXDATA ((0x0001 << 2) + 0xfe052000)
+#define SPICC1_CONREG ((0x0002 << 2) + 0xfe052000)
+#define SPICC1_INTREG ((0x0003 << 2) + 0xfe052000)
+#define SPICC1_DMAREG ((0x0004 << 2) + 0xfe052000)
+#define SPICC1_STATREG ((0x0005 << 2) + 0xfe052000)
+#define SPICC1_PERIODREG ((0x0006 << 2) + 0xfe052000)
+#define SPICC1_TESTREG ((0x0007 << 2) + 0xfe052000)
+#define SPICC1_DRADDR ((0x0008 << 2) + 0xfe052000)
+#define SPICC1_DWADDR ((0x0009 << 2) + 0xfe052000)
+#define SPICC1_LD_CNTL0 ((0x000a << 2) + 0xfe052000)
+#define SPICC1_LD_CNTL1 ((0x000b << 2) + 0xfe052000)
+#define SPICC1_LD_RADDR ((0x000c << 2) + 0xfe052000)
+#define SPICC1_LD_WADDR ((0x000d << 2) + 0xfe052000)
+#define SPICC1_ENHANCE_CNTL ((0x000e << 2) + 0xfe052000)
+#define SPICC1_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe052000)
+#define SPICC1_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe052000)
+//========================================================================
+// SPICC_2
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe054000
+// -----------------------------------------------
+#define SPICC2_RXDATA ((0x0000 << 2) + 0xfe054000)
+#define SPICC2_TXDATA ((0x0001 << 2) + 0xfe054000)
+#define SPICC2_CONREG ((0x0002 << 2) + 0xfe054000)
+#define SPICC2_INTREG ((0x0003 << 2) + 0xfe054000)
+#define SPICC2_DMAREG ((0x0004 << 2) + 0xfe054000)
+#define SPICC2_STATREG ((0x0005 << 2) + 0xfe054000)
+#define SPICC2_PERIODREG ((0x0006 << 2) + 0xfe054000)
+#define SPICC2_TESTREG ((0x0007 << 2) + 0xfe054000)
+#define SPICC2_DRADDR ((0x0008 << 2) + 0xfe054000)
+#define SPICC2_DWADDR ((0x0009 << 2) + 0xfe054000)
+#define SPICC2_LD_CNTL0 ((0x000a << 2) + 0xfe054000)
+#define SPICC2_LD_CNTL1 ((0x000b << 2) + 0xfe054000)
+#define SPICC2_LD_RADDR ((0x000c << 2) + 0xfe054000)
+#define SPICC2_LD_WADDR ((0x000d << 2) + 0xfe054000)
+#define SPICC2_ENHANCE_CNTL ((0x000e << 2) + 0xfe054000)
+#define SPICC2_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe054000)
+#define SPICC2_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe054000)
+//========================================================================
+// SPICC_3
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe04a000
+// -----------------------------------------------
+#define SPICC3_RXDATA ((0x0000 << 2) + 0xfe04a000)
+#define SPICC3_TXDATA ((0x0001 << 2) + 0xfe04a000)
+#define SPICC3_CONREG ((0x0002 << 2) + 0xfe04a000)
+#define SPICC3_INTREG ((0x0003 << 2) + 0xfe04a000)
+#define SPICC3_DMAREG ((0x0004 << 2) + 0xfe04a000)
+#define SPICC3_STATREG ((0x0005 << 2) + 0xfe04a000)
+#define SPICC3_PERIODREG ((0x0006 << 2) + 0xfe04a000)
+#define SPICC3_TESTREG ((0x0007 << 2) + 0xfe04a000)
+#define SPICC3_DRADDR ((0x0008 << 2) + 0xfe04a000)
+#define SPICC3_DWADDR ((0x0009 << 2) + 0xfe04a000)
+#define SPICC3_LD_CNTL0 ((0x000a << 2) + 0xfe04a000)
+#define SPICC3_LD_CNTL1 ((0x000b << 2) + 0xfe04a000)
+#define SPICC3_LD_RADDR ((0x000c << 2) + 0xfe04a000)
+#define SPICC3_LD_WADDR ((0x000d << 2) + 0xfe04a000)
+#define SPICC3_ENHANCE_CNTL ((0x000e << 2) + 0xfe04a000)
+#define SPICC3_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe04a000)
+#define SPICC3_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe04a000)
+//========================================================================
+// SPICC_4
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe04c000
+// -----------------------------------------------
+#define SPICC4_RXDATA ((0x0000 << 2) + 0xfe04c000)
+#define SPICC4_TXDATA ((0x0001 << 2) + 0xfe04c000)
+#define SPICC4_CONREG ((0x0002 << 2) + 0xfe04c000)
+#define SPICC4_INTREG ((0x0003 << 2) + 0xfe04c000)
+#define SPICC4_DMAREG ((0x0004 << 2) + 0xfe04c000)
+#define SPICC4_STATREG ((0x0005 << 2) + 0xfe04c000)
+#define SPICC4_PERIODREG ((0x0006 << 2) + 0xfe04c000)
+#define SPICC4_TESTREG ((0x0007 << 2) + 0xfe04c000)
+#define SPICC4_DRADDR ((0x0008 << 2) + 0xfe04c000)
+#define SPICC4_DWADDR ((0x0009 << 2) + 0xfe04c000)
+#define SPICC4_LD_CNTL0 ((0x000a << 2) + 0xfe04c000)
+#define SPICC4_LD_CNTL1 ((0x000b << 2) + 0xfe04c000)
+#define SPICC4_LD_RADDR ((0x000c << 2) + 0xfe04c000)
+#define SPICC4_LD_WADDR ((0x000d << 2) + 0xfe04c000)
+#define SPICC4_ENHANCE_CNTL ((0x000e << 2) + 0xfe04c000)
+#define SPICC4_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe04c000)
+#define SPICC4_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe04c000)
+//========================================================================
+// SPICC_5
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe04e000
+// -----------------------------------------------
+#define SPICC5_RXDATA ((0x0000 << 2) + 0xfe04e000)
+#define SPICC5_TXDATA ((0x0001 << 2) + 0xfe04e000)
+#define SPICC5_CONREG ((0x0002 << 2) + 0xfe04e000)
+#define SPICC5_INTREG ((0x0003 << 2) + 0xfe04e000)
+#define SPICC5_DMAREG ((0x0004 << 2) + 0xfe04e000)
+#define SPICC5_STATREG ((0x0005 << 2) + 0xfe04e000)
+#define SPICC5_PERIODREG ((0x0006 << 2) + 0xfe04e000)
+#define SPICC5_TESTREG ((0x0007 << 2) + 0xfe04e000)
+#define SPICC5_DRADDR ((0x0008 << 2) + 0xfe04e000)
+#define SPICC5_DWADDR ((0x0009 << 2) + 0xfe04e000)
+#define SPICC5_LD_CNTL0 ((0x000a << 2) + 0xfe04e000)
+#define SPICC5_LD_CNTL1 ((0x000b << 2) + 0xfe04e000)
+#define SPICC5_LD_RADDR ((0x000c << 2) + 0xfe04e000)
+#define SPICC5_LD_WADDR ((0x000d << 2) + 0xfe04e000)
+#define SPICC5_ENHANCE_CNTL ((0x000e << 2) + 0xfe04e000)
+#define SPICC5_ENHANCE_CNTL1 ((0x000f << 2) + 0xfe04e000)
+#define SPICC5_ENHANCE_CNTL2 ((0x0010 << 2) + 0xfe04e000)
+//========================================================================
+// AIFIFO - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe046000
+// -----------------------------------------------
+#define AIU_AIFIFO_CTRL ((0x0000 << 2) + 0xfe046000)
+#define AIU_AIFIFO_STATUS ((0x0001 << 2) + 0xfe046000)
+#define AIU_AIFIFO_GBIT ((0x0002 << 2) + 0xfe046000)
+#define AIU_AIFIFO_CLB ((0x0003 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_START_PTR ((0x0004 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_CURR_PTR ((0x0005 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_END_PTR ((0x0006 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_BYTES_AVAIL ((0x0007 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_CONTROL ((0x0008 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_MAN_WP ((0x0009 << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_MAN_RP ((0x000a << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_LEVEL ((0x000b << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_BUF_CNTL ((0x000c << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_BUF_WRAP_COUNT ((0x000d << 2) + 0xfe046000)
+#define AIU_MEM_AIFIFO_MEM_CTL ((0x000f << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_CNTL ((0x0010 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_SYNC_0 ((0x0011 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_SYNC_1 ((0x0012 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_0 ((0x0013 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_1 ((0x0014 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_2 ((0x0015 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_3 ((0x0016 << 2) + 0xfe046000)
+#define AIFIFO_TIME_STAMP_LENGTH ((0x0017 << 2) + 0xfe046000)
+//========================================================================
+// MSR_CLK - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe048000
+// -----------------------------------------------
+#define MSR_CLK_REG0 ((0x0000 << 2) + 0xfe048000)
+#define MSR_CLK_REG1 ((0x0001 << 2) + 0xfe048000)
+#define MSR_CLK_REG2 ((0x0002 << 2) + 0xfe048000)
+#define MSR_CLK_REG3 ((0x0003 << 2) + 0xfe048000)
+#define MSR_CLK_REG4 ((0x0004 << 2) + 0xfe048000)
+#define MSR_CLK_REG5 ((0x0005 << 2) + 0xfe048000)
+#define MSR_CLK_DUTY ((0x0006 << 2) + 0xfe048000)
+//========================================================================
+// SPIFC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe056000
+// -----------------------------------------------
+#define SPI_FLASH_CMD ((0x0000 << 2) + 0xfe056000)
+ // SPI_FLASH_READ 31
+ // SPI_FLASH_WREN 30
+ // SPI_FLASH_WRDI 29
+ // SPI_FLASH_RDID 28
+ // SPI_FLASH_RDSR 27
+ // SPI_FLASH_WRSR 26
+ // SPI_FLASH_PP 25
+ // SPI_FLASH_SE 24
+ // SPI_FLASH_BE 23
+ // SPI_FLASH_CE 22
+ // SPI_FLASH_DP 21
+ // SPI_FLASH_RES 20
+ // SPI_HPM 19
+ // SPI_FLASH_USR 18
+ // SPI_FLASH_USR_ADDR 15
+ // SPI_FLASH_USR_DUMMY 14
+ // SPI_FLASH_USR_DIN 13
+ // SPI_FLASH_USR_DOUT 12
+ // SPI_FLASH_USR_DUMMY_BLEN 10
+ // SPI_FLASH_USR_CMD 0
+#define SPI_FLASH_ADDR ((0x0001 << 2) + 0xfe056000)
+ // SPI_FLASH_BYTES_LEN 24
+ // SPI_FLASH_ADDR_START 0
+#define SPI_FLASH_CTRL ((0x0002 << 2) + 0xfe056000)
+ // SPI_ENABLE_AHB 17
+ // SPI_SST_AAI 16
+ // SPI_RES_RID 15
+ // SPI_FREAD_DUAL 14
+ // SPI_READ_READ_EN 13
+ // SPI_CLK_DIV0 12
+ // SPI_CLKCNT_N 8
+ // SPI_CLKCNT_H 4
+ // SPI_CLKCNT_L 0
+#define SPI_FLASH_CTRL1 ((0x0003 << 2) + 0xfe056000)
+#define SPI_FLASH_STATUS ((0x0004 << 2) + 0xfe056000)
+#define SPI_FLASH_CTRL2 ((0x0005 << 2) + 0xfe056000)
+#define SPI_FLASH_CLOCK ((0x0006 << 2) + 0xfe056000)
+#define SPI_FLASH_USER ((0x0007 << 2) + 0xfe056000)
+#define SPI_FLASH_USER1 ((0x0008 << 2) + 0xfe056000)
+#define SPI_FLASH_USER2 ((0x0009 << 2) + 0xfe056000)
+#define SPI_FLASH_USER3 ((0x000a << 2) + 0xfe056000)
+#define SPI_FLASH_USER4 ((0x000b << 2) + 0xfe056000)
+#define SPI_FLASH_SLAVE ((0x000c << 2) + 0xfe056000)
+#define SPI_FLASH_SLAVE1 ((0x000d << 2) + 0xfe056000)
+#define SPI_FLASH_SLAVE2 ((0x000e << 2) + 0xfe056000)
+#define SPI_FLASH_SLAVE3 ((0x000f << 2) + 0xfe056000)
+#define SPI_FLASH_C0 ((0x0010 << 2) + 0xfe056000)
+#define SPI_FLASH_C1 ((0x0011 << 2) + 0xfe056000)
+#define SPI_FLASH_C2 ((0x0012 << 2) + 0xfe056000)
+#define SPI_FLASH_C3 ((0x0013 << 2) + 0xfe056000)
+#define SPI_FLASH_C4 ((0x0014 << 2) + 0xfe056000)
+#define SPI_FLASH_C5 ((0x0015 << 2) + 0xfe056000)
+#define SPI_FLASH_C6 ((0x0016 << 2) + 0xfe056000)
+#define SPI_FLASH_C7 ((0x0017 << 2) + 0xfe056000)
+#define SPI_FLASH_B8 ((0x0018 << 2) + 0xfe056000)
+#define SPI_FLASH_B9 ((0x0019 << 2) + 0xfe056000)
+#define SPI_FLASH_B10 ((0x001a << 2) + 0xfe056000)
+#define SPI_FLASH_B11 ((0x001b << 2) + 0xfe056000)
+#define SPI_FLASH_B12 ((0x001c << 2) + 0xfe056000)
+#define SPI_FLASH_B13 ((0x001d << 2) + 0xfe056000)
+#define SPI_FLASH_B14 ((0x001e << 2) + 0xfe056000)
+#define SPI_FLASH_B15 ((0x001f << 2) + 0xfe056000)
+//========================================================================
+// CEC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe044000
+// -----------------------------------------------
+#define CECA_GEN_CNTL ((0x0000 << 2) + 0xfe044000)
+#define CECA_RW_REG ((0x0001 << 2) + 0xfe044000)
+#define CECA_INTR_MASKN ((0x0002 << 2) + 0xfe044000)
+#define CECA_INTR_CLR ((0x0003 << 2) + 0xfe044000)
+#define CECA_INTR_STAT ((0x0004 << 2) + 0xfe044000)
+#define CECB_GEN_CNTL ((0x0010 << 2) + 0xfe044000)
+#define CECB_RW_REG ((0x0011 << 2) + 0xfe044000)
+#define CECB_INTR_MASKN ((0x0012 << 2) + 0xfe044000)
+#define CECB_INTR_CLR ((0x0013 << 2) + 0xfe044000)
+#define CECB_INTR_STAT ((0x0014 << 2) + 0xfe044000)
+//========================================================================
+// SMART CARD - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe038000
+// -----------------------------------------------
+#define SMARTCARD_REG0 ((0x0000 << 2) + 0xfe038000)
+#define SMARTCARD_REG1 ((0x0001 << 2) + 0xfe038000)
+#define SMARTCARD_REG2 ((0x0002 << 2) + 0xfe038000)
+#define SMARTCARD_STATUS ((0x0003 << 2) + 0xfe038000)
+#define SMARTCARD_INTR ((0x0004 << 2) + 0xfe038000)
+#define SMARTCARD_REG5 ((0x0005 << 2) + 0xfe038000)
+#define SMARTCARD_REG6 ((0x0006 << 2) + 0xfe038000)
+#define SMARTCARD_FIFO ((0x0007 << 2) + 0xfe038000)
+#define SMARTCARD_REG8 ((0x0008 << 2) + 0xfe038000)
+//========================================================================
+// CAPU
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe012000
+// -----------------------------------------------
+#define CAPU_ACCESS_EN_AHB_ETH ((0x00c2 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_AHB_USB0 ((0x00c1 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_AHB_USB1 ((0x00c0 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_16M_SLOT1 ((0x00b1 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_16M_SLOT0 ((0x00b0 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_1M_SLOT0 ((0x00a8 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_256K_SLOT1 ((0x00a1 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_256K_SLOT0 ((0x00a0 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOTB ((0x008b << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOTA ((0x008a << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT9 ((0x0089 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT8 ((0x0088 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT7 ((0x0087 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT6 ((0x0086 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT5 ((0x0085 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT4 ((0x0084 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT3 ((0x0083 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT2 ((0x0082 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT1 ((0x0081 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_64K_SLOT0 ((0x0080 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT5F ((0x005f << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT5E ((0x005e << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT5D ((0x005d << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT5C ((0x005c << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT5B ((0x005b << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT5A ((0x005a << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT59 ((0x0059 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT58 ((0x0058 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT57 ((0x0057 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT56 ((0x0056 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT55 ((0x0055 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT54 ((0x0054 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT53 ((0x0053 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT52 ((0x0052 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT51 ((0x0051 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT50 ((0x0050 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT4F ((0x004f << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT4E ((0x004e << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT4D ((0x004d << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT4C ((0x004c << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT4B ((0x004b << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT4A ((0x004a << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT49 ((0x0049 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT48 ((0x0048 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT47 ((0x0047 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT46 ((0x0046 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT45 ((0x0045 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT44 ((0x0044 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT43 ((0x0043 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT42 ((0x0042 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT41 ((0x0041 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT40 ((0x0040 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT3F ((0x003f << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT3E ((0x003e << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT3D ((0x003d << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT3C ((0x003c << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT3B ((0x003b << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT3A ((0x003a << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT39 ((0x0039 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT38 ((0x0038 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT37 ((0x0037 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT36 ((0x0036 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT35 ((0x0035 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT34 ((0x0034 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT33 ((0x0033 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT32 ((0x0032 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT31 ((0x0031 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT30 ((0x0030 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT2F ((0x002f << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT2E ((0x002e << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT2D ((0x002d << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT2C ((0x002c << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT2B ((0x002b << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT2A ((0x002a << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT29 ((0x0029 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT28 ((0x0028 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT27 ((0x0027 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT26 ((0x0026 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT25 ((0x0025 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT24 ((0x0024 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT23 ((0x0023 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT22 ((0x0022 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT21 ((0x0021 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT20 ((0x0020 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT1F ((0x001f << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT1E ((0x001e << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT1D ((0x001d << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT1C ((0x001c << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT1B ((0x001b << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT1A ((0x001a << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT19 ((0x0019 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT18 ((0x0018 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT17 ((0x0017 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT16 ((0x0016 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT15 ((0x0015 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT14 ((0x0014 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT13 ((0x0013 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT12 ((0x0012 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT11 ((0x0011 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT10 ((0x0010 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT0F ((0x000f << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT0E ((0x000e << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT0D ((0x000d << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT0C ((0x000c << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT0B ((0x000b << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT0A ((0x000a << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT09 ((0x0009 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT08 ((0x0008 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT07 ((0x0007 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT06 ((0x0006 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT05 ((0x0005 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT04 ((0x0004 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT03 ((0x0003 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT02 ((0x0002 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT01 ((0x0001 << 2) + 0xfe012000)
+#define CAPU_ACCESS_EN_8K_SLOT00 ((0x0000 << 2) + 0xfe012000)
+//========================================================================
+// HDMI20_AES
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe01e000
+// -----------------------------------------------
+// RW [ 31] freeclk_en: 0=Gated clocks; 1=free-run clocks. Default 0.
+// RW [ 3] htx_sel: 0=Program for RX keys; 1=Program for TX keys. Default 0.
+// RW [ 2: 1] endian. Default 0.
+// WO [ 0] start: write 1 to reset internal counters. Read back 0.
+#define HDMI20_AES_CNTL0 ((0x0000 << 2) + 0xfe01e000)
+// RW [31: 0] encrypted HDCP data, 4-byte each, endian optional. Default 0.
+#define HDMI20_AES_DATA ((0x0001 << 2) + 0xfe01e000)
+// RO [26:16] nxt_otp_addr for either TX or RX
+// RO [ 12] secure_access
+// RO [ 11] aes_out128b_vld
+// RO [ 10] aes_din128b_vld
+// RO [ 9] aes_rdy
+// RO [ 8] aes_key_vld
+// RO [ 5] hrx_aes_rdy: 1=16-byte data are programmed into RX
+// RO [ 4] 1=RX aes_key is ready
+// RO [ 1] htx_aes_rdy: 1=16-byte data are programmed into TX
+// RO [ 0] 1=TX aes_key is ready
+#define HDMI20_AES_STAT0 ((0x0002 << 2) + 0xfe01e000)
+// RW [ 0] sw_reset. 0=No reset; 1=Reset. Default 0.
+#define HDMI20_AES_RESET ((0x0003 << 2) + 0xfe01e000)
+//========================================================================
+// HDMIRX_PHY
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe39c000
+// -----------------------------------------------
+#define HDMIRX_APLL_CNTL0 ((0x0000 << 2) + 0xfe39c000)
+#define HDMIRX_APLL_CNTL1 ((0x0001 << 2) + 0xfe39c000)
+#define HDMIRX_APLL_CNTL2 ((0x0002 << 2) + 0xfe39c000)
+#define HDMIRX_APLL_CNTL3 ((0x0003 << 2) + 0xfe39c000)
+#define HDMIRX_APLL_CNTL4 ((0x0004 << 2) + 0xfe39c000)
+#define HDMIRX_PHY_MISC0 ((0x0005 << 2) + 0xfe39c000)
+#define HDMIRX_PHY_MISC1 ((0x0006 << 2) + 0xfe39c000)
+#define HDMIRX_PHY_MISC2 ((0x0007 << 2) + 0xfe39c000)
+#define HDMIRX_PHY_MISC3 ((0x0008 << 2) + 0xfe39c000)
+#define HDMIRX_PHY_DCHA_CNTL0 ((0x0009 << 2) + 0xfe39c000)
+#define HDMIRX_PHY_DCHA_CNTL1 ((0x000a << 2) + 0xfe39c000)
+#define HDMIRX_PHY_DCHA_CNTL2 ((0x000b << 2) + 0xfe39c000)
+#define HDMIRX_PHY_DCHA_CNTL3 ((0x000c << 2) + 0xfe39c000)
+#define HDMIRX_PHY_DCHD_CNTL0 ((0x000d << 2) + 0xfe39c000)
+#define HDMIRX_PHY_DCHD_CNTL1 ((0x000e << 2) + 0xfe39c000)
+#define HDMIRX_PHY_DCHD_CNTL2 ((0x000f << 2) + 0xfe39c000)
+#define HDMIRX_PHY_DCHD_CNTL3 ((0x0010 << 2) + 0xfe39c000)
+#define HDMIRX_PHY_DCHD_CNTL4 ((0x0011 << 2) + 0xfe39c000)
+#define HDMIRX_PHY_MISC_STAT ((0x0012 << 2) + 0xfe39c000)
+#define HDMIRX_PHY_DCHD_STAT ((0x0013 << 2) + 0xfe39c000)
+#define HDMIRX_AUD_PLL_CNTL ((0x0020 << 2) + 0xfe39c000)
+#define HDMIRX_AUD_PLL_CNTL2 ((0x0021 << 2) + 0xfe39c000)
+#define HDMIRX_AUD_PLL_CNTL3 ((0x0022 << 2) + 0xfe39c000)
+#define HDMIRX_AUD_PLL_CNTL_I ((0x0023 << 2) + 0xfe39c000)
+#define HDMIRX_AUD_PLL4X_CNTL ((0x0024 << 2) + 0xfe39c000)
+#define HDMIRX_PHY_PROD_TEST0 ((0x0030 << 2) + 0xfe39c000)
+#define HDMIRX_PHY_PROD_TEST1 ((0x0031 << 2) + 0xfe39c000)
+#define HDMIRX_EARCTX_CNTL0 ((0x0040 << 2) + 0xfe39c000)
+#define HDMIRX_EARCTX_CNTL1 ((0x0041 << 2) + 0xfe39c000)
+#define HDMIRX_ARC_CNTL ((0x0042 << 2) + 0xfe39c000)
+//========================================================================
+// COMBO_DPHY DSI_LVDS_EDP_VX1
+//========================================================================
+//
+// Reading file: combo_dphy_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe018000
+// -----------------------------------------------
+#define COMBO_DPHY_CNTL0 ((0x0000 << 2) + 0xfe018000)
+//Bit 31:7 reserved
+//Bit 6 reg_phy2_pll_sel // unsigned , RW, default = 0
+//Bit 5 reg_phy1_pll_sel // unsigned , RW, default = 0
+//Bit 4 reg_phy2_din_sel_lvds // unsigned , RW, default = 0
+//Bit 3 reg_phy1_din_sel_edp // unsigned , RW, default = 0
+//Bit 2 reg_phy1_din_sel_lvds_vx1 // unsigned , RW, default = 0
+//Bit 1 reg_phy0_din_sel_edp // unsigned , RW, default = 0
+//Bit 0 reg_phy0_din_sel_lvds_vx1 // unsigned , RW, default = 0
+#define COMBO_DPHY_CNTL1 ((0x0001 << 2) + 0xfe018000)
+//Bit 31:30 reg_lane15_sel // unsigned , RW, default = 0
+//Bit 29:28 reg_lane14_sel // unsigned , RW, default = 0
+//Bit 27:26 reg_lane13_sel // unsigned , RW, default = 0
+//Bit 25:24 reg_lane12_sel // unsigned , RW, default = 0
+//Bit 23:22 reg_lane11_sel // unsigned , RW, default = 0
+//Bit 21:20 reg_lane10_sel // unsigned , RW, default = 0
+//Bit 19:18 reg_lane9_sel // unsigned , RW, default = 0
+//Bit 17:16 reg_lane8_sel // unsigned , RW, default = 0
+//Bit 15:14 reg_lane7_sel // unsigned , RW, default = 0
+//Bit 13:12 reg_lane6_sel // unsigned , RW, default = 0
+//Bit 11:10 reg_lane5_sel // unsigned , RW, default = 0
+//Bit 9:8 reg_lane4_sel // unsigned , RW, default = 0
+//Bit 7:6 reg_lane3_sel // unsigned , RW, default = 0
+//Bit 5:4 reg_lane2_sel // unsigned , RW, default = 0
+//Bit 3:2 reg_lane1_sel // unsigned , RW, default = 0
+//Bit 1:0 reg_lane0_sel // unsigned , RW, default = 0
+#define COMBO_DPHY_VID_PLL0_DIV ((0x0002 << 2) + 0xfe018000)
+//Bit 31:24 reserved
+//Bit 23:0 reg_hi_vid_pll0_clk_div // unsigned , RW, default = 0
+//Bit 19 clk_final_en //final stage enable
+//Bit 18 clk_div1 //bypass
+//Bit 17:16 clk_sel //2'b0: select div12, 2'b1:select div14, 2'b10:select div15, 2'b11:select div25
+//Bit 15 set_preset //load the clk pattern in shift registers
+//Bit 14:0 shift_preset //clk pattern in shifter registers
+#define COMBO_DPHY_VID_PLL1_DIV ((0x0003 << 2) + 0xfe018000)
+//Bit 31:24 reserved
+//Bit 23:0 reg_hi_vid_pll1_clk_div // unsigned , RW, default = 0
+//Bit 19 clk_final_en //final stage enable
+//Bit 18 clk_div1 //bypass
+//Bit 17:16 clk_sel //2'b0: select div12, 2'b1:select div14, 2'b10:select div15, 2'b11:select div25
+//Bit 15 set_preset //load the clk pattern in shift registers
+//Bit 14:0 shift_preset //clk pattern in shifter registers
+#define COMBO_DPHY_VID_PLL2_DIV ((0x0004 << 2) + 0xfe018000)
+//Bit 31:24 reserved
+//Bit 23:0 reg_hi_vid_pll2_clk_div // unsigned , RW, default = 0
+//Bit 19 clk_final_en //final stage enable
+//Bit 18 clk_div1 //bypass
+//Bit 17:16 clk_sel //2'b0: select div12, 2'b1:select div14, 2'b10:select div15, 2'b11:select div25
+//Bit 15 set_preset //load the clk pattern in shift registers
+//Bit 14:0 shift_preset //clk pattern in shifter registers
+#define COMBO_DPHY_EDP_PIXEL_CLK_DIV ((0x0005 << 2) + 0xfe018000)
+//Bit 31:27 reserved
+//Bit 26 reg_edp2_div_clk_en // unsigned , RW, default = 0 , useless
+//Bit 25 reg_edp1_div_clk_en // unsigned , RW, default = 0
+//Bit 24 reg_edp0_div_clk_en // unsigned , RW, default = 0
+//Bit 23:0 reg_hi_edp_pixel_clk_div // unsigned , RW, default = 0
+//Bit 15:12 edp1_clk_div_clk1_sel
+//Bit 11:8 edp1_clk_div_clk0_sel
+//Bit 7:4 edp0_clk_div_clk1_sel
+//Bit 3:0 edp0_clk_div_clk0_sel
+#define COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0 ((0x0006 << 2) + 0xfe018000)
+//Bit 31:0 reg_hi_edp_lvds_tx_phy0_cntl0 // unsigned , RW, default = 0
+//Bit 23:16 cntl_ser_en // ff: enable all 8 channel. 01: enable channel 0.
+//Bit 13 cntl_prbs_en // 1: enable prbs
+//Bit 12 cntl_prbs_err_en
+//Bit 11:10 cntl_mode_set_high // force channel output high
+//Bit 9:8 cntl_mode_set_low // force channel output low
+//Bit 7:5 fifo_clk_sel // 0: div6, 1: div7, 2: div8, 3: div10, else: div20
+//Bit 3 mode_bit_rev // swap lanes from 01234567 to 76543210
+//Bit 2 mode_inv_p_n // invert all lane PN
+//Bit 0 soft_reset // soft reset PHY
+#define COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL0 ((0x0007 << 2) + 0xfe018000)
+//Bit 31:0 reg_hi_edp_lvds_tx_phy1_cntl0 // unsigned , RW, default = 0
+//Bit 23:16 cntl_ser_en // ff: enable all 8 channel. 01: enable channel 0.
+//Bit 13 cntl_prbs_en // 1: enable prbs
+//Bit 12 cntl_prbs_err_en
+//Bit 11:10 cntl_mode_set_high // force channel output high
+//Bit 9:8 cntl_mode_set_low // force channel output low
+//Bit 7:5 fifo_clk_sel // 0: div6, 1: div7, 2: div8, 3: div10, else: div20
+//Bit 3 mode_bit_rev // swap lanes from 01234567 to 76543210
+//Bit 2 mode_inv_p_n // invert all lane PN
+//Bit 0 soft_reset // soft reset PHY
+#define COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL0 ((0x0008 << 2) + 0xfe018000)
+//Bit 31:0 reg_hi_edp_lvds_tx_phy2_cntl0 // unsigned , RW, default = 0
+//Bit 25:16 cntl_ser_en // ff: enable all 10 channel. 01: enable channel 0.
+//Bit 13 cntl_prbs_en // 1: enable prbs
+//Bit 12 cntl_prbs_err_en
+//Bit 11:10 cntl_mode_set_high // force channel output high
+//Bit 9:8 cntl_mode_set_low // force channel output low
+//Bit 7:5 fifo_clk_sel // 0: div6, 1: div7, 2: div8, 3: div10, else: div20
+//Bit 3 mode_bit_rev // swap lanes from 01234567 to 76543210
+//Bit 2 mode_inv_p_n // invert all lane PN
+//Bit 0 soft_reset // soft reset PHY
+#define COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1 ((0x0009 << 2) + 0xfe018000)
+//Bit 31:8 reserved
+//Bit 7:0 reg_hi_edp_lvds_tx_phy0_cntl1 // unsigned , RW, default = 0
+//Bit 7 wr_enable // start to write de-couple fifo
+//Bit 6 fifo_enable // De-couple FIFO enable
+//Bit 5 sel_hdmi_clk // select vid_pll_div_clk_out source from cts_hdmi_pll_clk
+//Bit 4 sel_edp_clk // select vid_pll_div_clk_out source from edptx_pixel_clk
+//Bit [3:1] reserved
+//Bit 0 phy_pll_clk_in_en // Enable phy_pll_clk input
+#define COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL1 ((0x000a << 2) + 0xfe018000)
+//Bit 31:8 reserved
+//Bit 7:0 reg_hi_edp_lvds_tx_phy1_cntl1 // unsigned , RW, default = 0
+//Bit 7 wr_enable // start to write de-couple fifo
+//Bit 6 fifo_enable // De-couple FIFO enable
+//Bit 5 sel_hdmi_clk // select vid_pll_div_clk_out source from cts_hdmi_pll_clk
+//Bit 4 sel_edp_clk // select vid_pll_div_clk_out source from edptx_pixel_clk
+//Bit [3:1] reserved
+//Bit 0 phy_pll_clk_in_en // Enable phy_pll_clk input
+#define COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL1 ((0x000b << 2) + 0xfe018000)
+//Bit 31:8 reserved
+//Bit 7:0 reg_hi_edp_lvds_tx_phy2_cntl1 // unsigned , RW, default = 0
+//Bit 7 wr_enable // start to write de-couple fifo
+//Bit 6 fifo_enable // De-couple FIFO enable
+//Bit 5 sel_hdmi_clk // select vid_pll_div_clk_out source from cts_hdmi_pll_clk
+//Bit 4 sel_edp_clk // select vid_pll_div_clk_out source from edptx_pixel_clk
+#define COMBO_DPHY_RO_EDP_LVDS_TX_PHY0_CNTL1 ((0x0010 << 2) + 0xfe018000)
+//Bit 31:16 reserved
+//Bit 15:0 ro_hi_edp_lvds_tx_phy0_cntl1_o // unsigned , RO, default = 0
+#define COMBO_DPHY_RO_EDP_LVDS_TX_PHY1_CNTL1 ((0x0011 << 2) + 0xfe018000)
+//Bit 31:20 reserved
+//Bit 15:0 ro_hi_edp_lvds_tx_phy1_cntl1_o // unsigned , RO, default = 0
+#define COMBO_DPHY_RO_EDP_LVDS_TX_PHY2_CNTL1 ((0x0012 << 2) + 0xfe018000)
+//Bit 31:16 reserved
+//Bit 19:0 ro_hi_edp_lvds_tx_phy2_cntl1_o // unsigned , RO, default = 0
+#define COMBO_DPHY_PROD_TEST0 ((0x0013 << 2) + 0xfe018000)
+//Bit 31:0 reg_int_prod_test0 // unsigned , RW, default = 0
+#define COMBO_DPHY_PROD_TEST1 ((0x0014 << 2) + 0xfe018000)
+//Bit 31:0 reg_int_prod_test1 // unsigned , RW, default = 0
+#define COMBO_DPHY_PROD_TEST2 ((0x0015 << 2) + 0xfe018000)
+//Bit 20:0 reg_int_prod_test2 // unsigned , RW, default = 0
+#define COMBO_DPHY_RO_PROD_TEST ((0x0016 << 2) + 0xfe018000)
+//Bit 31:10 reserved
+//Bit 9:0 ro_prod_sig // unsigned , RO, default = 0
+//
+// Closing file: combo_dphy_regs.h
+//
+//========================================================================
+// PDM
+//========================================================================
+//`include "../audio/rtl/pdm_reg.vh"
+//
+// Reading file: REG_LIST_AUDIO_RTL.h
+//
+//========================================================================
+// AUDIO - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe330000
+// -----------------------------------------------
+#define EE_AUDIO_CLK_GATE_EN0 ((0x0000 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_GATE_EN1 ((0x0001 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_A_CTRL ((0x0002 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_B_CTRL ((0x0003 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_C_CTRL ((0x0004 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_D_CTRL ((0x0005 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_E_CTRL ((0x0006 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_F_CTRL ((0x0007 << 2) + 0xfe330000)
+#define EE_AUDIO_SW_RESET0 ((0x000a << 2) + 0xfe330000)
+#define EE_AUDIO_SW_RESET1 ((0x000b << 2) + 0xfe330000)
+#define EE_AUDIO_CLK81_CTRL ((0x000c << 2) + 0xfe330000)
+#define EE_AUDIO_CLK81_EN ((0x000d << 2) + 0xfe330000)
+#define EE_AUDIO_MST_A_SCLK_CTRL0 ((0x0010 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_A_SCLK_CTRL1 ((0x0011 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_B_SCLK_CTRL0 ((0x0012 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_B_SCLK_CTRL1 ((0x0013 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_C_SCLK_CTRL0 ((0x0014 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_C_SCLK_CTRL1 ((0x0015 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_D_SCLK_CTRL0 ((0x0016 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_D_SCLK_CTRL1 ((0x0017 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_E_SCLK_CTRL0 ((0x0018 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_E_SCLK_CTRL1 ((0x0019 << 2) + 0xfe330000)
+#define EE_AUDIO_MST_F_SCLK_CTRL0 ((0x001a << 2) + 0xfe330000)
+#define EE_AUDIO_MST_F_SCLK_CTRL1 ((0x001b << 2) + 0xfe330000)
+#define EE_AUDIO_MST_DLY_CTRL0 ((0x001c << 2) + 0xfe330000)
+#define EE_AUDIO_MST_DLY_CTRL1 ((0x001d << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMIN_A_CTRL ((0x0020 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMIN_B_CTRL ((0x0021 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMIN_C_CTRL ((0x0022 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMIN_LB_CTRL ((0x0023 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMOUT_A_CTRL ((0x0024 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMOUT_B_CTRL ((0x0025 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_TDMOUT_C_CTRL ((0x0026 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_SPDIFIN_CTRL ((0x0027 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_SPDIFOUT_CTRL ((0x0028 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_RESAMPLEA_CTRL ((0x0029 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_LOCKER_CTRL ((0x002a << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_PDMIN_CTRL0 ((0x002b << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_PDMIN_CTRL1 ((0x002c << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_SPDIFOUT_B_CTRL ((0x002d << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_RESAMPLEB_CTRL ((0x002e << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_SPDIFIN_LB_CTRL ((0x002f << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_EQDRC_CTRL0 ((0x0030 << 2) + 0xfe330000)
+#define EE_AUDIO_VAD_CLK_CTRL ((0x0031 << 2) + 0xfe330000)
+#define EE_AUDIO_EARCTX_CMDC_CLK_CTRL ((0x0032 << 2) + 0xfe330000)
+#define EE_AUDIO_EARCTX_DMAC_CLK_CTRL ((0x0033 << 2) + 0xfe330000)
+#define EE_AUDIO_EARCRX_CMDC_CLK_CTRL ((0x0034 << 2) + 0xfe330000)
+#define EE_AUDIO_EARCRX_DMAC_CLK_CTRL ((0x0035 << 2) + 0xfe330000)
+#define EE_AUDIO_CLK_LOCKERB_CTRL ((0x0036 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CTRL0 ((0x0040 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CTRL1 ((0x0041 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_START_ADDR ((0x0042 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_FINISH_ADDR ((0x0043 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_INT_ADDR ((0x0044 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_STATUS1 ((0x0045 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_STATUS2 ((0x0046 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_START_ADDRB ((0x0047 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_FINISH_ADDRB ((0x0048 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_INIT_ADDR ((0x0049 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CTRL2 ((0x004a << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CTRL0 ((0x0050 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CTRL1 ((0x0051 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_START_ADDR ((0x0052 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_FINISH_ADDR ((0x0053 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_INT_ADDR ((0x0054 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_STATUS1 ((0x0055 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_STATUS2 ((0x0056 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_START_ADDRB ((0x0057 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_FINISH_ADDRB ((0x0058 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_INIT_ADDR ((0x0059 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CTRL2 ((0x005a << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CTRL0 ((0x0060 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CTRL1 ((0x0061 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_START_ADDR ((0x0062 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_FINISH_ADDR ((0x0063 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_INT_ADDR ((0x0064 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_STATUS1 ((0x0065 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_STATUS2 ((0x0066 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_START_ADDRB ((0x0067 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_FINISH_ADDRB ((0x0068 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_INIT_ADDR ((0x0069 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CTRL2 ((0x006a << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_CTRL0 ((0x0070 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_CTRL1 ((0x0071 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_START_ADDR ((0x0072 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_FINISH_ADDR ((0x0073 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_INT_ADDR ((0x0074 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_STATUS1 ((0x0075 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_STATUS2 ((0x0076 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_START_ADDRB ((0x0077 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_FINISH_ADDRB ((0x0078 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_INIT_ADDR ((0x0079 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_A_CTRL2 ((0x007a << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_CTRL0 ((0x0080 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_CTRL1 ((0x0081 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_START_ADDR ((0x0082 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_FINISH_ADDR ((0x0083 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_INT_ADDR ((0x0084 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_STATUS1 ((0x0085 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_STATUS2 ((0x0086 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_START_ADDRB ((0x0087 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_FINISH_ADDRB ((0x0088 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_INIT_ADDR ((0x0089 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_B_CTRL2 ((0x008a << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_CTRL0 ((0x0090 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_CTRL1 ((0x0091 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_START_ADDR ((0x0092 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_FINISH_ADDR ((0x0093 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_INT_ADDR ((0x0094 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_STATUS1 ((0x0095 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_STATUS2 ((0x0096 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_START_ADDRB ((0x0097 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_FINISH_ADDRB ((0x0098 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_INIT_ADDR ((0x0099 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_C_CTRL2 ((0x009a << 2) + 0xfe330000)
+#define EE_AUDIO_ARB_CTRL0 ((0x00a0 << 2) + 0xfe330000)
+#define EE_AUDIO_ARB_CTRL1 ((0x00a1 << 2) + 0xfe330000)
+#define EE_AUDIO_ARB_STS ((0x00a8 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CTRL0 ((0x00b0 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CTRL1 ((0x00b1 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CTRL2 ((0x00b2 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CTRL3 ((0x00b3 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_DAT_CH_ID0 ((0x00b4 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_DAT_CH_ID1 ((0x00b5 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_DAT_CH_ID2 ((0x00b6 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_DAT_CH_ID3 ((0x00b7 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_LB_CH_ID0 ((0x00b8 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_LB_CH_ID1 ((0x00b9 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_LB_CH_ID2 ((0x00ba << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_LB_CH_ID3 ((0x00bb << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_STS ((0x00bc << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CHSYNC_CTRL_INSERT ((0x00bd << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CHSYNC_CTRL_ORIG ((0x00be << 2) + 0xfe330000)
+#define EE_AUDIO_LB_A_CTRL4 ((0x00bf << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_CTRL ((0x00c0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_SWAP0 ((0x00c1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK0 ((0x00c2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK1 ((0x00c3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK2 ((0x00c4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK3 ((0x00c5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_STAT ((0x00c6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE_VAL ((0x00c7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE0 ((0x00c8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE1 ((0x00c9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE2 ((0x00ca << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE3 ((0x00cb << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_CTRL ((0x00d0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_SWAP0 ((0x00d1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK0 ((0x00d2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK1 ((0x00d3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK2 ((0x00d4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK3 ((0x00d5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_STAT ((0x00d6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE_VAL ((0x00d7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE0 ((0x00d8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE1 ((0x00d9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE2 ((0x00da << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE3 ((0x00db << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_CTRL ((0x00e0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_SWAP0 ((0x00e1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK0 ((0x00e2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK1 ((0x00e3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK2 ((0x00e4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK3 ((0x00e5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_STAT ((0x00e6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE_VAL ((0x00e7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE0 ((0x00e8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE1 ((0x00e9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE2 ((0x00ea << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE3 ((0x00eb << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_CTRL ((0x00f0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_SWAP0 ((0x00f1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK0 ((0x00f2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK1 ((0x00f3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK2 ((0x00f4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK3 ((0x00f5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_STAT ((0x00f6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE_VAL ((0x00f7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE0 ((0x00f8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE1 ((0x00f9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE2 ((0x00fa << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE3 ((0x00fb << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL0 ((0x0100 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL1 ((0x0101 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL2 ((0x0102 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL3 ((0x0103 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL4 ((0x0104 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL5 ((0x0105 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL6 ((0x0106 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_STAT0 ((0x0107 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_STAT1 ((0x0108 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_STAT2 ((0x0109 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_MUTE_VAL ((0x010a << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_CTRL7 ((0x010b << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_CTRL0 ((0x0110 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_CTRL1 ((0x0111 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_CTRL2 ((0x0112 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_CTRL3 ((0x0113 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_COEF0 ((0x0114 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_COEF1 ((0x0115 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_COEF2 ((0x0116 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_COEF3 ((0x0117 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_COEF4 ((0x0118 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEA_STATUS1 ((0x0119 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_STAT ((0x0120 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_GAIN0 ((0x0121 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_GAIN1 ((0x0122 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CTRL0 ((0x0123 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CTRL1 ((0x0124 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_PREAMB ((0x0125 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_SWAP ((0x0126 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS0 ((0x0127 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS1 ((0x0128 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS2 ((0x0129 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS3 ((0x012a << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS4 ((0x012b << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS5 ((0x012c << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS6 ((0x012d << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS7 ((0x012e << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS8 ((0x012f << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTS9 ((0x0130 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTSA ((0x0131 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_CHSTSB ((0x0132 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_MUTE_VAL ((0x0133 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_GAIN2 ((0x0134 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_GAIN3 ((0x0135 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_GAIN_EN ((0x0136 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_GAIN_CTRL ((0x0137 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_CTRL0 ((0x0140 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_CTRL1 ((0x0141 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_SWAP0 ((0x0142 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK0 ((0x0143 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK1 ((0x0144 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK2 ((0x0145 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK3 ((0x0146 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_STAT ((0x0147 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_GAIN0 ((0x0148 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_GAIN1 ((0x0149 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE_VAL ((0x014a << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE0 ((0x014b << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE1 ((0x014c << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE2 ((0x014d << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE3 ((0x014e << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK_VAL ((0x014f << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_CTRL0 ((0x0150 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_CTRL1 ((0x0151 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_SWAP0 ((0x0152 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK0 ((0x0153 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK1 ((0x0154 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK2 ((0x0155 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK3 ((0x0156 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_STAT ((0x0157 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_GAIN0 ((0x0158 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_GAIN1 ((0x0159 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE_VAL ((0x015a << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE0 ((0x015b << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE1 ((0x015c << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE2 ((0x015d << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE3 ((0x015e << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK_VAL ((0x015f << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_CTRL0 ((0x0160 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_CTRL1 ((0x0161 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_SWAP0 ((0x0162 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK0 ((0x0163 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK1 ((0x0164 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK2 ((0x0165 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK3 ((0x0166 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_STAT ((0x0167 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_GAIN0 ((0x0168 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_GAIN1 ((0x0169 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE_VAL ((0x016a << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE0 ((0x016b << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE1 ((0x016c << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE2 ((0x016d << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE3 ((0x016e << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK_VAL ((0x016f << 2) + 0xfe330000)
+//`define EE_AUDIO_POW_DET_CTRL0 10'h180
+//`define EE_AUDIO_POW_DET_CTRL1 10'h181
+//`define EE_AUDIO_POW_DET_TH_HI 10'h182
+//`define EE_AUDIO_POW_DET_TH_LO 10'h183
+//`define EE_AUDIO_POW_DET_VALUE 10'h184
+#define EE_AUDIO_SECURITY_CTRL0 ((0x0190 << 2) + 0xfe330000)
+#define EE_AUDIO_SECURITY_CTRL1 ((0x0191 << 2) + 0xfe330000)
+#define EE_AUDIO_SECURITY_CTRL2 ((0x0192 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_STAT ((0x01a0 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN0 ((0x01a1 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN1 ((0x01a2 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CTRL0 ((0x01a3 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CTRL1 ((0x01a4 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_PREAMB ((0x01a5 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_SWAP ((0x01a6 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS0 ((0x01a7 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS1 ((0x01a8 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS2 ((0x01a9 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS3 ((0x01aa << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS4 ((0x01ab << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS5 ((0x01ac << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS6 ((0x01ad << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS7 ((0x01ae << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS8 ((0x01af << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTS9 ((0x01b0 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTSA ((0x01b1 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_CHSTSB ((0x01b2 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_MUTE_VAL ((0x01b3 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN2 ((0x01b4 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN3 ((0x01b5 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN_EN ((0x01b6 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFOUT_B_GAIN_CTRL ((0x01b7 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_CTRL0 ((0x01c0 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_CTRL1 ((0x01c1 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_START_ADDR ((0x01c2 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_FINISH_ADDR ((0x01c3 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_INT_ADDR ((0x01c4 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_STATUS1 ((0x01c5 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_STATUS2 ((0x01c6 << 2) + 0xfe330000)
+#define EE_AUDIO_TORAM_INIT_ADDR ((0x01c7 << 2) + 0xfe330000)
+#define EE_AUDIO_TOACODEC_CTRL0 ((0x01d0 << 2) + 0xfe330000)
+#define EE_AUDIO_TOHDMITX_CTRL0 ((0x01d1 << 2) + 0xfe330000)
+#define EE_AUDIO_TOVAD_CTRL0 ((0x01d2 << 2) + 0xfe330000)
+#define EE_AUDIO_FRATV_CTRL0 ((0x01d3 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_CTRL0 ((0x01e0 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_CTRL1 ((0x01e1 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_CTRL2 ((0x01e2 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_CTRL3 ((0x01e3 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_COEF0 ((0x01e4 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_COEF1 ((0x01e5 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_COEF2 ((0x01e6 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_COEF3 ((0x01e7 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_COEF4 ((0x01e8 << 2) + 0xfe330000)
+#define EE_AUDIO_RESAMPLEB_STATUS1 ((0x01e9 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_LB_CTRL0 ((0x01f0 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_LB_CTRL1 ((0x01f1 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_LB_CTRL6 ((0x01f6 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_LB_STAT0 ((0x01f7 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_LB_STAT1 ((0x01f8 << 2) + 0xfe330000)
+#define EE_AUDIO_SPDIFIN_LB_MUTE_VAL ((0x01fa << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL0 ((0x0200 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL1 ((0x0201 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL2 ((0x0202 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL3 ((0x0203 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL4 ((0x0204 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL5 ((0x0205 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL6 ((0x0206 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_CTRL7 ((0x0207 << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_STAT0 ((0x020a << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_STAT1 ((0x020b << 2) + 0xfe330000)
+#define EE_AUDIO_FRHDMIRX_STAT2 ((0x020c << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CTRL0 ((0x0210 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CTRL1 ((0x0211 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_START_ADDR ((0x0212 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_FINISH_ADDR ((0x0213 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_INT_ADDR ((0x0214 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_STATUS1 ((0x0215 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_STATUS2 ((0x0216 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_START_ADDRB ((0x0217 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_FINISH_ADDRB ((0x0218 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_INIT_ADDR ((0x0219 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CTRL2 ((0x021a << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_CTRL0 ((0x0220 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_CTRL1 ((0x0221 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_START_ADDR ((0x0222 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_FINISH_ADDR ((0x0223 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_INT_ADDR ((0x0224 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_STATUS1 ((0x0225 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_STATUS2 ((0x0226 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_START_ADDRB ((0x0227 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_FINISH_ADDRB ((0x0228 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_INIT_ADDR ((0x0229 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_D_CTRL2 ((0x022a << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CTRL0 ((0x0230 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CTRL1 ((0x0231 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CTRL2 ((0x0232 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CTRL3 ((0x0233 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_DAT_CH_ID0 ((0x0234 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_DAT_CH_ID1 ((0x0235 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_DAT_CH_ID2 ((0x0236 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_DAT_CH_ID3 ((0x0237 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_LB_CH_ID0 ((0x0238 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_LB_CH_ID1 ((0x0239 << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_LB_CH_ID2 ((0x023a << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_LB_CH_ID3 ((0x023b << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_STS ((0x023c << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CHSYNC_CTRL_INSERT ((0x023d << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CHSYNC_CTRL_ORIG ((0x023e << 2) + 0xfe330000)
+#define EE_AUDIO_LB_B_CTRL4 ((0x023f << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CTRL0 ((0x0240 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CTRL1 ((0x0241 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_START_ADDR ((0x0242 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_FINISH_ADDR ((0x0243 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_INT_ADDR ((0x0244 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_STATUS1 ((0x0245 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_STATUS2 ((0x0246 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_START_ADDRB ((0x0247 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_FINISH_ADDRB ((0x0248 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_INIT_ADDR ((0x0249 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CTRL2 ((0x024a << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_CTRL0 ((0x0250 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_CTRL1 ((0x0251 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_START_ADDR ((0x0252 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_FINISH_ADDR ((0x0253 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_INT_ADDR ((0x0254 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_STATUS1 ((0x0255 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_STATUS2 ((0x0256 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_START_ADDRB ((0x0257 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_FINISH_ADDRB ((0x0258 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_INIT_ADDR ((0x0259 << 2) + 0xfe330000)
+#define EE_AUDIO_FRDDR_E_CTRL2 ((0x025a << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_SWAP1 ((0x0260 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK4 ((0x0261 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK5 ((0x0262 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK6 ((0x0263 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MASK7 ((0x0264 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE4 ((0x0265 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE5 ((0x0266 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE6 ((0x0267 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_A_MUTE7 ((0x0268 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_SWAP1 ((0x0270 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK4 ((0x0271 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK5 ((0x0272 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK6 ((0x0273 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MASK7 ((0x0274 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE4 ((0x0275 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE5 ((0x0276 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE6 ((0x0277 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_B_MUTE7 ((0x0278 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_SWAP1 ((0x0280 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK4 ((0x0281 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK5 ((0x0282 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK6 ((0x0283 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MASK7 ((0x0284 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE4 ((0x0285 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE5 ((0x0286 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE6 ((0x0287 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_C_MUTE7 ((0x0288 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_SWAP1 ((0x0290 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK4 ((0x0291 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK5 ((0x0292 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK6 ((0x0293 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MASK7 ((0x0294 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE4 ((0x0295 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE5 ((0x0296 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE6 ((0x0297 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMIN_LB_MUTE7 ((0x0298 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_CTRL2 ((0x02a0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_SWAP1 ((0x02a1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_GAIN2 ((0x02a2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_GAIN3 ((0x02a3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK4 ((0x02a4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK5 ((0x02a5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK6 ((0x02a6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MASK7 ((0x02a7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE4 ((0x02a8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE5 ((0x02a9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE6 ((0x02aa << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_MUTE7 ((0x02ab << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_GAIN_EN ((0x02ac << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_A_GAIN_CTRL ((0x02ad << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_CTRL2 ((0x02b0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_SWAP1 ((0x02b1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_GAIN2 ((0x02b2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_GAIN3 ((0x02b3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK4 ((0x02b4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK5 ((0x02b5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK6 ((0x02b6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MASK7 ((0x02b7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE4 ((0x02b8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE5 ((0x02b9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE6 ((0x02ba << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_MUTE7 ((0x02bb << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_GAIN_EN ((0x02bc << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_B_GAIN_CTRL ((0x02bd << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_CTRL2 ((0x02c0 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_SWAP1 ((0x02c1 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_GAIN2 ((0x02c2 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_GAIN3 ((0x02c3 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK4 ((0x02c4 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK5 ((0x02c5 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK6 ((0x02c6 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MASK7 ((0x02c7 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE4 ((0x02c8 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE5 ((0x02c9 << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE6 ((0x02ca << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_MUTE7 ((0x02cb << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_GAIN_EN ((0x02cc << 2) + 0xfe330000)
+#define EE_AUDIO_TDMOUT_C_GAIN_CTRL ((0x02cd << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID0 ((0x0300 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID1 ((0x0301 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID2 ((0x0302 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID3 ((0x0303 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID4 ((0x0304 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID5 ((0x0305 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID6 ((0x0306 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHNUM_ID7 ((0x0307 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_A_CHSYNC_CTRL ((0x030f << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID0 ((0x0310 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID1 ((0x0311 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID2 ((0x0312 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID3 ((0x0313 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID4 ((0x0314 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID5 ((0x0315 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID6 ((0x0316 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHNUM_ID7 ((0x0317 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_B_CHSYNC_CTRL ((0x031f << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID0 ((0x0320 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID1 ((0x0321 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID2 ((0x0322 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID3 ((0x0323 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID4 ((0x0324 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID5 ((0x0325 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID6 ((0x0326 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHNUM_ID7 ((0x0327 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_C_CHSYNC_CTRL ((0x032f << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID0 ((0x0330 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID1 ((0x0331 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID2 ((0x0332 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID3 ((0x0333 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID4 ((0x0334 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID5 ((0x0335 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID6 ((0x0336 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHNUM_ID7 ((0x0337 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_D_CHSYNC_CTRL ((0x033f << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID0 ((0x0340 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID1 ((0x0341 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID2 ((0x0342 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID3 ((0x0343 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID4 ((0x0344 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID5 ((0x0345 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID6 ((0x0346 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHNUM_ID7 ((0x0347 << 2) + 0xfe330000)
+#define EE_AUDIO_TODDR_E_CHSYNC_CTRL ((0x034f << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID0 ((0x0350 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID1 ((0x0351 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID2 ((0x0352 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID3 ((0x0353 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID4 ((0x0354 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID5 ((0x0355 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID6 ((0x0356 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHNUM_ID7 ((0x0357 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_CHSYNC_MASK ((0x035e << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_A_CHSYNC_CTRL ((0x035f << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID0 ((0x0360 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID1 ((0x0361 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID2 ((0x0362 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID3 ((0x0363 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID4 ((0x0364 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID5 ((0x0365 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID6 ((0x0366 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHNUM_ID7 ((0x0367 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_B_CHSYNC_CTRL ((0x036f << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID0 ((0x0370 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID1 ((0x0371 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID2 ((0x0372 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID3 ((0x0373 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID4 ((0x0374 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID5 ((0x0375 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID6 ((0x0376 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHNUM_ID7 ((0x0377 << 2) + 0xfe330000)
+#define EE_AUDIO_RSAMP_C_CHSYNC_CTRL ((0x037f << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_STS0 ((0x0380 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_STS1 ((0x0381 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_MASK0 ((0x0382 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_MASK1 ((0x0383 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_MODE0 ((0x0384 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_MODE1 ((0x0385 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_CLR0 ((0x0386 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_CLR1 ((0x0387 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_INV0 ((0x0388 << 2) + 0xfe330000)
+#define EE_AUDIO_EXCEPTION_IRQ_INV1 ((0x0389 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL0 ((0x0390 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL1 ((0x0391 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL2 ((0x0392 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL3 ((0x0393 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL4 ((0x0394 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL5 ((0x0395 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL6 ((0x0396 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL7 ((0x0397 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL8 ((0x0398 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRL9 ((0x0399 << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRLA ((0x039a << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRLB ((0x039b << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRLC ((0x039c << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRLD ((0x039d << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRLE ((0x039e << 2) + 0xfe330000)
+#define EE_AUDIO_DAT_PAD_CTRLF ((0x039f << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_PAD_CTRL0 ((0x03a0 << 2) + 0xfe330000)
+#define EE_AUDIO_MCLK_PAD_CTRL1 ((0x03a1 << 2) + 0xfe330000)
+#define EE_AUDIO_SCLK_PAD_CTRL0 ((0x03a2 << 2) + 0xfe330000)
+#define EE_AUDIO_LRCLK_PAD_CTRL0 ((0x03a3 << 2) + 0xfe330000)
+//========================================================================
+// PDM - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe331000
+// -----------------------------------------------
+#define PDM_CTRL ((0x0000 << 2) + 0xfe331000)
+ //bit 31: PDM enable.
+ //bit 30: invert the PDM_DCLK.
+ //bit 29: output mode: 1: 24bits. 0: 32 bits.
+ //bit 28: bypass mode. 1: bypass all filter. directly output the PDM input to DDR. 0: normal mode.
+ //bit 27~9: not used.
+ //bit 16:. PDM Asynchronous FIFO soft reset. write 1 to soft reset AFIFO.
+ //bit 15:8 PDM channel reset. 0: to reset each PDM channel. 1: normal mode.
+ //bit 7:0. PDM channel enable. each bit for one channel.
+#define PDM_HCIC_CTRL1 ((0x0001 << 2) + 0xfe331000)
+ //bit 31 hcic filter enable. 1 use sinc filter. 0 bypass input to output.
+ //bit 29:24. hcic final gain shift parameter.
+ //bit 23:16 hcic final gain multiplier.
+ //bit 8:4 hcic down sample rate.
+ //bit 3:0 hcic stage number. must be between 3 to 9.
+#define PDM_HCIC_CTRL2 ((0x0002 << 2) + 0xfe331000)
+ //Not used.
+#define PDM_F1_CTRL ((0x0003 << 2) + 0xfe331000)
+ //bit 31 . filter 1 enable.
+ //bit 16:15. f1 round mode. 2'b00 : sign bit at bit 49. 28bits output [49:22] round at bit 21. 32bits output [49:18]. 24bits output [49:26]
+ // 2'b01 : sign bit at bit 50. 28bits output [50:23] round at bit 22. 32bits output [49:18]. 24bits output [49:26]
+ // 2'b10 : sign bit at bit 51. 28bits output [51:24] round at bit 23 32bits output [49:18]. 24bits output [49:26].
+ //bit 15:12. filter 1 down sample rate.
+ //bit 8:0. filter 1 stage number.
+#define PDM_F2_CTRL ((0x0004 << 2) + 0xfe331000)
+ //bit 31 . filter 2 enable.
+ //bit 16:15. f2 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23.
+ //bit 15:12. filter 2 down sample rate.
+ //bit 8:0. filter 2 stage number.
+#define PDM_F3_CTRL ((0x0005 << 2) + 0xfe331000)
+ //bit 31 . filter 3 enable.
+ //bit 16:15. f3 round mode. 2'b00 : round at bit 21. 2'b01 : round at bit 22. 2'b10 : round at bit 23.
+ //bit 15:12. filter 3 down sample rate.
+ //bit 8:0. filter 3 stage number.
+#define PDM_HPF_CTRL ((0x0006 << 2) + 0xfe331000)
+ //bit 31 High pass filter enable.
+ //bit 20:16 high pass filter shift steps. 6~19 steps.
+ //bit 15:0 high pass filter output factor.
+#define PDM_CHAN_CTRL ((0x0007 << 2) + 0xfe331000)
+ //bit 31:24. chan3 data sample pointer vs edge of the PDM_DCLK.
+ //bit 23:16 chan2 data sample pointer vs edge of the PDM_DCLK.
+ //bit 15:8. chan1 data sample pointer vs edge of the PDM_DCLK.
+ //bit 7:0 chan0 data sample pointer vs edge of the PDM_DCLK.
+#define PDM_CHAN_CTRL1 ((0x0008 << 2) + 0xfe331000)
+ //bit 31:24. chan7 data sample pointer vs edge of the PDM_DCLK.
+ //bit 23:16 chan6 data sample pointer vs edge of the PDM_DCLK.
+ //bit 15:8. chan5 data sample pointer vs edge of the PDM_DCLK.
+ //bit 7:0 chan4 data sample pointer vs edge of the PDM_DCLK.
+#define PDM_COEFF_ADDR ((0x0009 << 2) + 0xfe331000)
+ // address of the write/read of coeff data.
+#define PDM_COEFF_DATA ((0x000a << 2) + 0xfe331000)
+ //write/read data to coeff memory.
+#define PDM_CLKG_CTRL ((0x000b << 2) + 0xfe331000)
+ // auto clock gating control. 1: disable the clock gating function. the clock will awlays enabled. 0 : use RTL auto clock gating.
+ //31:7 not used.
+ //bit 6 filt_ctrl module auto clock gating control.
+ //bit 5 sinc fifo module auto clock gating control.
+ //bit 4 filter module auto clock gating control.
+ //bit 3 apb module auto clock gating control.
+ //bit 2 coeff memory module auto clock gating control.
+ //bit 1 each channel module auto clock gating control.
+ //bit 0 cts_pdm_clk auto clock gating control.
+#define PDM_STS ((0x000c << 2) + 0xfe331000)
+//bit 1 HPF filter output overflow. means the PCLK is too slow.
+//bit 0 HCIC filter output overflow. means the CTS_PDM_CLK is too slow. can't finished the filter function.
+#define PDM_MUTE_VALUE ((0x000d << 2) + 0xfe331000)
+#define PDM_MASK_NUM ((0x000e << 2) + 0xfe331000)
+#define PDM_CHAN_CTRL2 ((0x000f << 2) + 0xfe331000)
+ //bit 7:0 second sample and start FSM point vs rise edge of PDM_DCLK
+//========================================================================
+// EQ DRC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe332000
+// -----------------------------------------------
+#define AED_COEF_RAM_CNTL ((0x0000 << 2) + 0xfe332000)
+#define AED_COEF_RAM_DATA ((0x0001 << 2) + 0xfe332000)
+#define AED_EQ_EN ((0x0002 << 2) + 0xfe332000)
+#define AED_EQ_TAP_CNTL ((0x0003 << 2) + 0xfe332000)
+#define AED_EQ_VOLUME ((0x0004 << 2) + 0xfe332000)
+#define AED_EQ_VOLUME_SLEW_CNT ((0x0005 << 2) + 0xfe332000)
+#define AED_MUTE ((0x0006 << 2) + 0xfe332000)
+#define AED_DRC_CNTL ((0x0007 << 2) + 0xfe332000)
+#define AED_DRC_RMS_COEF0 ((0x0008 << 2) + 0xfe332000)
+#define AED_DRC_RMS_COEF1 ((0x0009 << 2) + 0xfe332000)
+#define AED_DRC_THD0 ((0x000a << 2) + 0xfe332000)
+#define AED_DRC_THD1 ((0x000b << 2) + 0xfe332000)
+#define AED_DRC_THD2 ((0x000c << 2) + 0xfe332000)
+#define AED_DRC_THD3 ((0x000d << 2) + 0xfe332000)
+#define AED_DRC_THD4 ((0x000e << 2) + 0xfe332000)
+#define AED_DRC_K0 ((0x000f << 2) + 0xfe332000)
+#define AED_DRC_K1 ((0x0010 << 2) + 0xfe332000)
+#define AED_DRC_K2 ((0x0011 << 2) + 0xfe332000)
+#define AED_DRC_K3 ((0x0012 << 2) + 0xfe332000)
+#define AED_DRC_K4 ((0x0013 << 2) + 0xfe332000)
+#define AED_DRC_K5 ((0x0014 << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT0 ((0x0015 << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT1 ((0x0016 << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT2 ((0x0017 << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT3 ((0x0018 << 2) + 0xfe332000)
+#define AED_DRC_OFFSET ((0x0019 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF00 ((0x001a << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF01 ((0x001b << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF10 ((0x001c << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF11 ((0x001d << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF20 ((0x001e << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF21 ((0x001f << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF30 ((0x0020 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF31 ((0x0021 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF40 ((0x0022 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF41 ((0x0023 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF50 ((0x0024 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF51 ((0x0025 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF00 ((0x0026 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF01 ((0x0027 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF10 ((0x0028 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF11 ((0x0029 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF20 ((0x002a << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF21 ((0x002b << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF30 ((0x002c << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF31 ((0x002d << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF40 ((0x002e << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF41 ((0x002f << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF50 ((0x0030 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF51 ((0x0031 << 2) + 0xfe332000)
+#define AED_DRC_LOOPBACK_CNTL ((0x0032 << 2) + 0xfe332000)
+#define AED_MDRC_CNTL ((0x0033 << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF00 ((0x0034 << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF01 ((0x0035 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF00 ((0x0036 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF01 ((0x0037 << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF00 ((0x0038 << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF01 ((0x0039 << 2) + 0xfe332000)
+#define AED_MDRC_THD0 ((0x003a << 2) + 0xfe332000)
+#define AED_MDRC_K0 ((0x003b << 2) + 0xfe332000)
+#define AED_MDRC_LOW_GAIN ((0x003c << 2) + 0xfe332000)
+#define AED_MDRC_OFFSET0 ((0x003d << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF10 ((0x003e << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF11 ((0x003f << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF10 ((0x0040 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF11 ((0x0041 << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF10 ((0x0042 << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF11 ((0x0043 << 2) + 0xfe332000)
+#define AED_MDRC_THD1 ((0x0044 << 2) + 0xfe332000)
+#define AED_MDRC_K1 ((0x0045 << 2) + 0xfe332000)
+#define AED_MDRC_OFFSET1 ((0x0046 << 2) + 0xfe332000)
+#define AED_MDRC_MID_GAIN ((0x0047 << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF20 ((0x0048 << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF21 ((0x0049 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF20 ((0x004a << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF21 ((0x004b << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF20 ((0x004c << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF21 ((0x004d << 2) + 0xfe332000)
+#define AED_MDRC_THD2 ((0x004e << 2) + 0xfe332000)
+#define AED_MDRC_K2 ((0x004f << 2) + 0xfe332000)
+#define AED_MDRC_OFFSET2 ((0x0050 << 2) + 0xfe332000)
+#define AED_MDRC_HIGH_GAIN ((0x0051 << 2) + 0xfe332000)
+#define AED_ED_CNTL ((0x0052 << 2) + 0xfe332000)
+#define AED_DC_EN ((0x0053 << 2) + 0xfe332000)
+#define AED_ND_LOW_THD ((0x0054 << 2) + 0xfe332000)
+#define AED_ND_HIGH_THD ((0x0055 << 2) + 0xfe332000)
+#define AED_ND_CNT_THD ((0x0056 << 2) + 0xfe332000)
+#define AED_ND_SUM_NUM ((0x0057 << 2) + 0xfe332000)
+#define AED_ND_CZ_NUM ((0x0058 << 2) + 0xfe332000)
+#define AED_ND_SUM_THD0 ((0x0059 << 2) + 0xfe332000)
+#define AED_ND_SUM_THD1 ((0x005a << 2) + 0xfe332000)
+#define AED_ND_CZ_THD0 ((0x005b << 2) + 0xfe332000)
+#define AED_ND_CZ_THD1 ((0x005c << 2) + 0xfe332000)
+#define AED_ND_COND_CNTL ((0x005d << 2) + 0xfe332000)
+#define AED_ND_RELEASE_COEF0 ((0x005e << 2) + 0xfe332000)
+#define AED_ND_RELEASE_COEF1 ((0x005f << 2) + 0xfe332000)
+#define AED_ND_ATTACK_COEF0 ((0x0060 << 2) + 0xfe332000)
+#define AED_ND_ATTACK_COEF1 ((0x0061 << 2) + 0xfe332000)
+#define AED_ND_CNTL ((0x0062 << 2) + 0xfe332000)
+#define AED_MIX0_LL ((0x0063 << 2) + 0xfe332000)
+#define AED_MIX0_RL ((0x0064 << 2) + 0xfe332000)
+#define AED_MIX0_LR ((0x0065 << 2) + 0xfe332000)
+#define AED_MIX0_RR ((0x0066 << 2) + 0xfe332000)
+#define AED_CLIP_THD ((0x0067 << 2) + 0xfe332000)
+#define AED_CH1_ND_SUM_OUT ((0x0068 << 2) + 0xfe332000)
+#define AED_CH2_ND_SUM_OUT ((0x0069 << 2) + 0xfe332000)
+#define AED_CH1_ND_CZ_OUT ((0x006a << 2) + 0xfe332000)
+#define AED_CH2_ND_CZ_OUT ((0x006b << 2) + 0xfe332000)
+#define AED_NOISE_STATUS ((0x006c << 2) + 0xfe332000)
+#define AED_POW_CURRENT_S0 ((0x006d << 2) + 0xfe332000)
+#define AED_POW_CURRENT_S1 ((0x006e << 2) + 0xfe332000)
+#define AED_POW_CURRENT_S2 ((0x006f << 2) + 0xfe332000)
+#define AED_POW_OUT0 ((0x0070 << 2) + 0xfe332000)
+#define AED_POW_OUT1 ((0x0071 << 2) + 0xfe332000)
+#define AED_POW_OUT2 ((0x0072 << 2) + 0xfe332000)
+#define AED_POW_ADJ_INDEX0 ((0x0073 << 2) + 0xfe332000)
+#define AED_POW_ADJ_INDEX1 ((0x0074 << 2) + 0xfe332000)
+#define AED_POW_ADJ_INDEX2 ((0x0075 << 2) + 0xfe332000)
+#define AED_DRC_GAIN_INDEX0 ((0x0076 << 2) + 0xfe332000)
+#define AED_DRC_GAIN_INDEX1 ((0x0077 << 2) + 0xfe332000)
+#define AED_DRC_GAIN_INDEX2 ((0x0078 << 2) + 0xfe332000)
+#define AED_CH1_VOLUME_STATE ((0x0079 << 2) + 0xfe332000)
+#define AED_CH2_VOLUME_STATE ((0x007a << 2) + 0xfe332000)
+#define AED_CH1_VOLUME_GAIN ((0x007b << 2) + 0xfe332000)
+#define AED_CH2_VOLUME_GAIN ((0x007c << 2) + 0xfe332000)
+#define AED_FULL_POW_CURRENT ((0x007d << 2) + 0xfe332000)
+#define AED_FULL_POW_OUT ((0x007e << 2) + 0xfe332000)
+#define AED_FULL_POW_ADJ ((0x007f << 2) + 0xfe332000)
+#define AED_FULL_DRC_GAIN ((0x0080 << 2) + 0xfe332000)
+#define AED_MASTER_VOLUME_STATE ((0x0081 << 2) + 0xfe332000)
+#define AED_MASTER_VOLUME_GAIN ((0x0082 << 2) + 0xfe332000)
+#define AED_TOP_CTL0 ((0x0083 << 2) + 0xfe332000)
+#define AED_TOP_CTL1 ((0x0084 << 2) + 0xfe332000)
+#define AED_TOP_CTL2 ((0x0085 << 2) + 0xfe332000)
+#define AED_TOP_ST0 ((0x0086 << 2) + 0xfe332000)
+#define AED_TOP_ST1 ((0x0087 << 2) + 0xfe332000)
+#define AED_EQDRC_DYNAMIC_CNTL ((0x0090 << 2) + 0xfe332000)
+#define AED_COEF_RAM_CNTL_B ((0x0091 << 2) + 0xfe332000)
+#define AED_COEF_RAM_DATA_B ((0x0092 << 2) + 0xfe332000)
+#define AED_DRC_RMS_COEF0_B ((0x0093 << 2) + 0xfe332000)
+#define AED_DRC_RMS_COEF1_B ((0x0094 << 2) + 0xfe332000)
+#define AED_DRC_THD0_B ((0x0095 << 2) + 0xfe332000)
+#define AED_DRC_THD1_B ((0x0096 << 2) + 0xfe332000)
+#define AED_DRC_THD2_B ((0x0097 << 2) + 0xfe332000)
+#define AED_DRC_THD3_B ((0x0098 << 2) + 0xfe332000)
+#define AED_DRC_THD4_B ((0x0099 << 2) + 0xfe332000)
+#define AED_DRC_K0_B ((0x009a << 2) + 0xfe332000)
+#define AED_DRC_K1_B ((0x009b << 2) + 0xfe332000)
+#define AED_DRC_K2_B ((0x009c << 2) + 0xfe332000)
+#define AED_DRC_K3_B ((0x009d << 2) + 0xfe332000)
+#define AED_DRC_K4_B ((0x009e << 2) + 0xfe332000)
+#define AED_DRC_K5_B ((0x009f << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT0_B ((0x00a0 << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT1_B ((0x00a1 << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT2_B ((0x00a2 << 2) + 0xfe332000)
+#define AED_DRC_THD_OUT3_B ((0x00a3 << 2) + 0xfe332000)
+#define AED_DRC_OFFSET_B ((0x00a4 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF00_B ((0x00a5 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF01_B ((0x00a6 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF10_B ((0x00a7 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF11_B ((0x00a8 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF20_B ((0x00a9 << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF21_B ((0x00aa << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF30_B ((0x00ab << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF31_B ((0x00ac << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF40_B ((0x00ad << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF41_B ((0x00ae << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF50_B ((0x00af << 2) + 0xfe332000)
+#define AED_DRC_RELEASE_COEF51_B ((0x00b0 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF00_B ((0x00b1 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF01_B ((0x00b2 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF10_B ((0x00b3 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF11_B ((0x00b4 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF20_B ((0x00b5 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF21_B ((0x00b6 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF30_B ((0x00b7 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF31_B ((0x00b8 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF40_B ((0x00b9 << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF41_B ((0x00ba << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF50_B ((0x00bb << 2) + 0xfe332000)
+#define AED_DRC_ATTACK_COEF51_B ((0x00bc << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF00_B ((0x00bd << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF01_B ((0x00be << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF10_B ((0x00bf << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF11_B ((0x00c0 << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF20_B ((0x00c1 << 2) + 0xfe332000)
+#define AED_MDRC_RMS_COEF21_B ((0x00c2 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF00_B ((0x00c3 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF01_B ((0x00c4 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF10_B ((0x00c5 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF11_B ((0x00c6 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF20_B ((0x00c7 << 2) + 0xfe332000)
+#define AED_MDRC_RELEASE_COEF21_B ((0x00c8 << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF00_B ((0x00c9 << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF01_B ((0x00ca << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF10_B ((0x00cb << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF11_B ((0x00cc << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF20_B ((0x00cd << 2) + 0xfe332000)
+#define AED_MDRC_ATTACK_COEF21_B ((0x00ce << 2) + 0xfe332000)
+#define AED_MDRC_THD0_B ((0x00cf << 2) + 0xfe332000)
+#define AED_MDRC_THD1_B ((0x00d0 << 2) + 0xfe332000)
+#define AED_MDRC_THD2_B ((0x00d1 << 2) + 0xfe332000)
+#define AED_MDRC_K0_B ((0x00d2 << 2) + 0xfe332000)
+#define AED_MDRC_K1_B ((0x00d3 << 2) + 0xfe332000)
+#define AED_MDRC_K2_B ((0x00d4 << 2) + 0xfe332000)
+#define AED_MDRC_OFFSET0_B ((0x00d5 << 2) + 0xfe332000)
+#define AED_MDRC_OFFSET1_B ((0x00d6 << 2) + 0xfe332000)
+#define AED_MDRC_OFFSET2_B ((0x00d7 << 2) + 0xfe332000)
+#define AED_MDRC_LOW_GAIN_B ((0x00d8 << 2) + 0xfe332000)
+#define AED_MDRC_MID_GAIN_B ((0x00d9 << 2) + 0xfe332000)
+#define AED_MDRC_HIGH_GAIN_B ((0x00da << 2) + 0xfe332000)
+#define AED_DRC_CNTL_B ((0x00db << 2) + 0xfe332000)
+#define AED_DRC_LOOPBACK_CNTL_B ((0x00dc << 2) + 0xfe332000)
+#define AED_MDRC_CNTL_B ((0x00dd << 2) + 0xfe332000)
+#define AED_STATUS_REG ((0x00de << 2) + 0xfe332000)
+//========================================================================
+// AUDIO locker - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe331400
+// -----------------------------------------------
+#define AUD_LOCK_EN ((0x0000 << 2) + 0xfe331400)
+#define AUD_LOCK_SW_RESET ((0x0001 << 2) + 0xfe331400)
+#define AUD_LOCK_SW_LATCH ((0x0002 << 2) + 0xfe331400)
+#define AUD_LOCK_HW_LATCH ((0x0003 << 2) + 0xfe331400)
+#define AUD_LOCK_REFCLK_SRC ((0x0004 << 2) + 0xfe331400)
+#define AUD_LOCK_REFCLK_LAT_INT ((0x0005 << 2) + 0xfe331400)
+#define AUD_LOCK_IMCLK_LAT_INT ((0x0006 << 2) + 0xfe331400)
+#define AUD_LOCK_OMCLK_LAT_INT ((0x0007 << 2) + 0xfe331400)
+#define AUD_LOCK_REFCLK_DS_INT ((0x0008 << 2) + 0xfe331400)
+#define AUD_LOCK_IMCLK_DS_INT ((0x0009 << 2) + 0xfe331400)
+#define AUD_LOCK_OMCLK_DS_INT ((0x000a << 2) + 0xfe331400)
+#define AUD_LOCK_INT_CLR ((0x000b << 2) + 0xfe331400)
+#define AUD_LOCK_GCLK_CTRL ((0x000c << 2) + 0xfe331400)
+#define AUD_LOCK_INT_CTRL ((0x000d << 2) + 0xfe331400)
+#define RO_REF2IMCLK_CNT_L ((0x0010 << 2) + 0xfe331400)
+#define RO_REF2IMCLK_CNT_H ((0x0011 << 2) + 0xfe331400)
+#define RO_REF2OMCLK_CNT_L ((0x0012 << 2) + 0xfe331400)
+#define RO_REF2OMCLK_CNT_H ((0x0013 << 2) + 0xfe331400)
+#define RO_IMCLK2REF_CNT_L ((0x0014 << 2) + 0xfe331400)
+#define RO_IMCLK2REF_CNT_H ((0x0015 << 2) + 0xfe331400)
+#define RO_OMCLK2REF_CNT_L ((0x0016 << 2) + 0xfe331400)
+#define RO_OMCLK2REF_CNT_H ((0x0017 << 2) + 0xfe331400)
+#define RO_REFCLK_PKG_CNT ((0x0018 << 2) + 0xfe331400)
+#define RO_IMCLK_PKG_CNT ((0x0019 << 2) + 0xfe331400)
+#define RO_OMCLK_PKG_CNT ((0x001a << 2) + 0xfe331400)
+#define RO_AUD_LOCK_INT_STATUS ((0x001b << 2) + 0xfe331400)
+//========================================================================
+// AUDIO lockerB - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe334400
+// -----------------------------------------------
+#define AUD_LOCKB_EN ((0x0000 << 2) + 0xfe334400)
+#define AUD_LOCKB_SW_RESET ((0x0001 << 2) + 0xfe334400)
+#define AUD_LOCKB_SW_LATCH ((0x0002 << 2) + 0xfe334400)
+#define AUD_LOCKB_HW_LATCH ((0x0003 << 2) + 0xfe334400)
+#define AUD_LOCKB_REFCLK_SRC ((0x0004 << 2) + 0xfe334400)
+#define AUD_LOCKB_REFCLK_LAT_INT ((0x0005 << 2) + 0xfe334400)
+#define AUD_LOCKB_IMCLK_LAT_INT ((0x0006 << 2) + 0xfe334400)
+#define AUD_LOCKB_OMCLK_LAT_INT ((0x0007 << 2) + 0xfe334400)
+#define AUD_LOCKB_REFCLK_DS_INT ((0x0008 << 2) + 0xfe334400)
+#define AUD_LOCKB_IMCLK_DS_INT ((0x0009 << 2) + 0xfe334400)
+#define AUD_LOCKB_OMCLK_DS_INT ((0x000a << 2) + 0xfe334400)
+#define AUD_LOCKB_INT_CLR ((0x000b << 2) + 0xfe334400)
+#define AUD_LOCKB_GCLK_CTRL ((0x000c << 2) + 0xfe334400)
+#define AUD_LOCKB_INT_CTRL ((0x000d << 2) + 0xfe334400)
+#define ROB_REF2IMCLK_CNT_L ((0x0010 << 2) + 0xfe334400)
+#define ROB_REF2IMCLK_CNT_H ((0x0011 << 2) + 0xfe334400)
+#define ROB_REF2OMCLK_CNT_L ((0x0012 << 2) + 0xfe334400)
+#define ROB_REF2OMCLK_CNT_H ((0x0013 << 2) + 0xfe334400)
+#define ROB_IMCLK2REF_CNT_L ((0x0014 << 2) + 0xfe334400)
+#define ROB_IMCLK2REF_CNT_H ((0x0015 << 2) + 0xfe334400)
+#define ROB_OMCLK2REF_CNT_L ((0x0016 << 2) + 0xfe334400)
+#define ROB_OMCLK2REF_CNT_H ((0x0017 << 2) + 0xfe334400)
+#define ROB_REFCLK_PKG_CNT ((0x0018 << 2) + 0xfe334400)
+#define ROB_IMCLK_PKG_CNT ((0x0019 << 2) + 0xfe334400)
+#define ROB_OMCLK_PKG_CNT ((0x001a << 2) + 0xfe334400)
+#define ROB_AUD_LOCK_INT_STATUS ((0x001b << 2) + 0xfe334400)
+//========================================================================
+// AUDIO VAD - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe331800
+// -----------------------------------------------
+//
+// Reading file: VAD_REG.h
+//
+#define VAD_TOP_CTRL0 ((0x0000 << 2) + 0xfe331800)
+#define VAD_TOP_CTRL1 ((0x0001 << 2) + 0xfe331800)
+#define VAD_TOP_CTRL2 ((0x0002 << 2) + 0xfe331800)
+#define VAD_FIR_CTRL ((0x0003 << 2) + 0xfe331800)
+#define VAD_FIR_EMP ((0x0004 << 2) + 0xfe331800)
+#define VAD_FIR_COEF0 ((0x0005 << 2) + 0xfe331800)
+#define VAD_FIR_COEF1 ((0x0006 << 2) + 0xfe331800)
+#define VAD_FIR_COEF2 ((0x0007 << 2) + 0xfe331800)
+#define VAD_FIR_COEF3 ((0x0008 << 2) + 0xfe331800)
+#define VAD_FIR_COEF4 ((0x0009 << 2) + 0xfe331800)
+#define VAD_FIR_COEF5 ((0x000a << 2) + 0xfe331800)
+#define VAD_FIR_COEF6 ((0x000b << 2) + 0xfe331800)
+#define VAD_FIR_COEF7 ((0x000c << 2) + 0xfe331800)
+#define VAD_FIR_COEF8 ((0x000d << 2) + 0xfe331800)
+#define VAD_FIR_COEF9 ((0x000e << 2) + 0xfe331800)
+#define VAD_FIR_COEF10 ((0x000f << 2) + 0xfe331800)
+#define VAD_FIR_COEF11 ((0x0010 << 2) + 0xfe331800)
+#define VAD_FIR_COEF12 ((0x0011 << 2) + 0xfe331800)
+#define VAD_FRAME_CTRL0 ((0x0012 << 2) + 0xfe331800)
+#define VAD_FRAME_CTRL1 ((0x0013 << 2) + 0xfe331800)
+#define VAD_FRAME_CTRL2 ((0x0014 << 2) + 0xfe331800)
+#define VAD_CEP_CTRL0 ((0x0015 << 2) + 0xfe331800)
+#define VAD_CEP_CTRL1 ((0x0016 << 2) + 0xfe331800)
+#define VAD_CEP_CTRL2 ((0x0017 << 2) + 0xfe331800)
+#define VAD_CEP_CTRL3 ((0x0018 << 2) + 0xfe331800)
+#define VAD_CEP_CTRL4 ((0x0019 << 2) + 0xfe331800)
+#define VAD_CEP_CTRL5 ((0x001a << 2) + 0xfe331800)
+#define VAD_DEC_CTRL ((0x001b << 2) + 0xfe331800)
+#define VAD_TOP_STS0 ((0x001c << 2) + 0xfe331800)
+#define VAD_TOP_STS1 ((0x001d << 2) + 0xfe331800)
+#define VAD_TOP_STS2 ((0x001e << 2) + 0xfe331800)
+#define VAD_FIR_STS0 ((0x001f << 2) + 0xfe331800)
+#define VAD_FIR_STS1 ((0x0020 << 2) + 0xfe331800)
+#define VAD_POW_STS0 ((0x0021 << 2) + 0xfe331800)
+#define VAD_POW_STS1 ((0x0022 << 2) + 0xfe331800)
+#define VAD_POW_STS2 ((0x0023 << 2) + 0xfe331800)
+#define VAD_FFT_STS0 ((0x0024 << 2) + 0xfe331800)
+#define VAD_FFT_STS1 ((0x0025 << 2) + 0xfe331800)
+#define VAD_SPE_STS0 ((0x0026 << 2) + 0xfe331800)
+#define VAD_SPE_STS1 ((0x0027 << 2) + 0xfe331800)
+#define VAD_SPE_STS2 ((0x0028 << 2) + 0xfe331800)
+#define VAD_SPE_STS3 ((0x0029 << 2) + 0xfe331800)
+#define VAD_DEC_STS0 ((0x002a << 2) + 0xfe331800)
+#define VAD_DEC_STS1 ((0x002b << 2) + 0xfe331800)
+#define VAD_LUT_CTRL ((0x002c << 2) + 0xfe331800)
+#define VAD_LUT_WR ((0x002d << 2) + 0xfe331800)
+#define VAD_LUT_RD ((0x002e << 2) + 0xfe331800)
+#define VAD_IN_SEL0 ((0x002f << 2) + 0xfe331800)
+#define VAD_IN_SEL1 ((0x0030 << 2) + 0xfe331800)
+#define VAD_TO_DDR ((0x0031 << 2) + 0xfe331800)
+#define VAD_SYNC_CTRL0 ((0x0032 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID0 ((0x0033 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID1 ((0x0034 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID2 ((0x0035 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID3 ((0x0036 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID4 ((0x0037 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID5 ((0x0038 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID6 ((0x0039 << 2) + 0xfe331800)
+#define VAD_SYNC_CHNUM_ID7 ((0x003a << 2) + 0xfe331800)
+//
+// Closing file: VAD_REG.h
+//
+//========================================================================
+// AUDIO RESAMPLEA - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe331c00
+// -----------------------------------------------
+//
+// Reading file: RESAMPLE.h
+//
+#define AUDIO_RSAMP_CTRL0 ((0x0000 << 2) + 0xfe331c00)
+//Bit 31:3 reserved
+//Bit 2 reg_lock_rst //unsigned , default =0;
+//Bit 1 reg_rsamp_rst //unsigned , default =0;
+//Bit 0 reg_sw_rst //unsigned , default =0;
+#define AUDIO_RSAMP_CTRL1 ((0x0001 << 2) + 0xfe331c00)
+//Bit 31:27 reg_in_lsb //unsigned , default =0;
+//Bit 26 reg_watchdog_en //unsigned , default =0;
+//Bit 25 reg_rsamp_rst_sel //unsigned , default =0;
+//Bit 24 reg_module_bypas //unsigned , default =0;
+//Bit 23:18 reg_gclk_ctrl //unsigned , default =0;
+//Bit 17:13 reg_in_msb //unsigned , default =23;
+//Bit 12 reg_output_en //unsigned , default =0;
+//Bit 11 reg_rsamp_en //unsigned , default =0;
+//Bit 10 reg_filt_en //unsigned , default =0;
+//Bit 9 reg_post_en //unsigned , default =0;
+//Bit 8 reg_inp_mux_mode //unsigned , default =0;
+//Bit 7:5 reserved //unsigned , default =2;
+//Bit 4:0 reg_inp_mux //unsigned , default =0;
+#define AUDIO_RSAMP_CTRL2 ((0x0002 << 2) + 0xfe331c00)
+//Bit 31:30 reserved //unsigned , default =0;
+//Bit 29:24 reg_chx_size //unsigned , default =2;
+//Bit 23:18 reserved //unsigned , default =0;
+//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4
+//Bit 15:8 reg_filt_tap //unsigned , default =63;
+//Bit 7:0 reg_intp_tap //unsigned , default =63;
+#define AUDIO_RSAMP_PHSINIT ((0x0003 << 2) + 0xfe331c00)
+//Bit 31:28 reserved //unsigned , default = 0;
+//Bit 27:0 reg_init_phs //unsigned , default = 0;
+#define AUDIO_RSAMP_PHSSTEP ((0x0004 << 2) + 0xfe331c00)
+//Bit 31 reserved //unsigned , default = 0;
+//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000
+#define AUDIO_RSAMP_SHIFT ((0x0005 << 2) + 0xfe331c00)
+//Bit 31:24 reg_rsft_iir //unsigned , default = 23;
+//Bit 23:16 reg_rsft_blnd //unsigned , default = 21;
+//Bit 15:8 reg_rsft_sinc //unsigned , default = 31;
+//Bit 7:0 reg_rsft_aa //unsigned , default = 31;
+#define AUDIO_RSAMP_ADJ_CTRL0 ((0x0006 << 2) + 0xfe331c00)
+//Bit 31:7 reserved //unsigned
+//Bit 6 reg_lock_vld_sel //unsigned , default = 0;
+//Bit 5 reg_loop_dif_clr_en //unsigned , default = 0;
+//Bit 4 reg_aout_force_en //unsigned , default = 0;
+//Bit 3 reserved //unsigned
+//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0;
+//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0;
+//Bit 0 reg_rsamp_adj_en //unsigned , default = 0;
+#define AUDIO_RSAMP_ADJ_CTRL1 ((0x0007 << 2) + 0xfe331c00)
+//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8;
+//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768;
+#define AUDIO_RSAMP_ADJ_SFT ((0x0008 << 2) + 0xfe331c00)
+//Bit 31:30 reserved //unsigned , default = 0;
+//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0;
+//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9;
+//Bit 23:21 reserved //unsigned , default = 0;
+//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1;
+//Bit 15:13 reserved //unsigned , default = 0;
+//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6;
+//Bit 7:6 reserved //unsigned , default = 0;
+//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12;
+#define AUDIO_RSAMP_ADJ_IDET_LEN ((0x0009 << 2) + 0xfe331c00)
+//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000;
+#define AUDIO_RSAMP_ADJ_FORCE ((0x000a << 2) + 0xfe331c00)
+//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8;
+#define AUDIO_RSAMP_ADJ_KI_FORCE ((0x000b << 2) + 0xfe331c00)
+//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0;
+#define AUDIO_RSAMP_WATCHDOG_THRD ((0x000c << 2) + 0xfe331c00)
+//Bit 31:0 reg_watchdog_thrd //signed , default = 32'h1000;
+#define AUDIO_RSAMP_DBG_INFO ((0x000d << 2) + 0xfe331c00)
+//Bit 31:16 reg_aout_force_hi //unsigned , default = 0;
+//Bit 15:7 reserved //unsigned , default = 0;
+//Bit 6 reg_rsamp_dbgcnt_clr //unsigned , default = 0;
+//Bit 5 reg_rsamp_dbgcnt_vldsel //unsigned , default = 0;
+//Bit 4 reg_rsamp_dbgcnt_en //unsigned , default = 0;
+//Bit 3 reserved //unsigned , default = 0;
+//Bit 2:0 reg_watchdog_rstsel //unsigned , default = 4;
+#define AUDIO_RSAMP_AOUT_FORCE ((0x000e << 2) + 0xfe331c00)
+//Bit 31:0 reg_aout_force_lo //unsigned , default = 0;
+#define AUDIO_RSAMP_IRQ_CTRL ((0x000f << 2) + 0xfe331c00)
+//Bit 31:16 reg_irq_thrd //unsigned , default = 0;
+//Bit 15:12 reserved //unsigned , default = 0;
+//Bit 11:8 reg_irq_sel //unsigned , default = 0;
+//Bit 7:4 reg_irq_clr //unsigned , default = 0;
+//Bit 3:0 reg_irq_en //unsigned , default = 0;
+#define AUDIO_RSAMP_RO_STATUS ((0x0010 << 2) + 0xfe331c00)
+//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]}
+#define AUDIO_RSAMP_RO_ADJ_FREQ ((0x0011 << 2) + 0xfe331c00)
+//Bit 31:0 ro_rsamp_adj_freq
+#define AUDIO_RSAMP_RO_ADJ_DIFF_BAK ((0x0012 << 2) + 0xfe331c00)
+//Bit 31:0 ro_det_diff_bak
+#define AUDIO_RSAMP_RO_ADJ_DIFF_DLT ((0x0013 << 2) + 0xfe331c00)
+//Bit 31:0 ro_det_diff_dlt
+#define AUDIO_RSAMP_RO_ADJ_PHS_ERR ((0x0014 << 2) + 0xfe331c00)
+//Bit 31:0 ro_det_phase_err
+#define AUDIO_RSAMP_RO_ADJ_KI_OUT ((0x0015 << 2) + 0xfe331c00)
+//Bit 31:0 ro_rsamp_ki_out
+#define AUDIO_RSAMP_RO_IN_CNT ((0x0016 << 2) + 0xfe331c00)
+//Bit 31:0 ro_rsamp_in_cnt
+#define AUDIO_RSAMP_RO_OUT_CNT ((0x0017 << 2) + 0xfe331c00)
+//Bit 31:0 ro_rsamp_out_cnt
+#define AUDIO_RSAMP_RO_ADJ_PHS_ERR_VAR ((0x0018 << 2) + 0xfe331c00)
+//Bit 31:0 ro_det_phase_err_var
+#define AUDIO_RSAMP_POST_COEF0 ((0x0020 << 2) + 0xfe331c00)
+//Bit 31:0 reg_post_coef0 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF1 ((0x0021 << 2) + 0xfe331c00)
+//Bit 31:0 reg_post_coef1 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF2 ((0x0022 << 2) + 0xfe331c00)
+//Bit 31:0 reg_post_coef2 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF3 ((0x0023 << 2) + 0xfe331c00)
+//Bit 31:0 reg_post_coef3 //signed , default = 0;
+#define AUDIO_RSAMP_POST_COEF4 ((0x0024 << 2) + 0xfe331c00)
+//Bit 31:0 reg_post_coef4 //signed , default = 0;
+#define AUDIO_RSAMP_AA_COEF_ADDR ((0x0030 << 2) + 0xfe331c00)
+//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0;
+#define AUDIO_RSAMP_AA_COEF_DATA ((0x0031 << 2) + 0xfe331c00)
+//Bit 31:0 reg_aa_coef_data //signed , default = 0;
+#define AUDIO_RSAMP_SINC_COEF_ADDR ((0x0040 << 2) + 0xfe331c00)
+//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0;
+#define AUDIO_RSAMP_SINC_COEF_DATA ((0x0041 << 2) + 0xfe331c00)
+//Bit 31:0 reg_sinc_coef_data //signed , default = 0;
+//
+// Closing file: RESAMPLE.h
+//
+//========================================================================
+// AUDIO EARCTX_CMDC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe333000
+// -----------------------------------------------
+//
+// Reading file: earc_tx_cmdc.h
+//
+#define EARC_TX_CMDC_TOP_CTRL0 ((0x0030 << 2) + 0xfe333000)
+//Bit 31 , idle2_int unsigned, default = 0, 1: enable
+//Bit 30 , idle1_int unsigned, default = 0, 1: enable
+//Bit 29 , disc2_int unsigned, default = 0, 1: enable
+//Bit 28 , disc1_int unsigned, default = 0, 1: enable
+//Bit 27 , earc_int unsigned, default = 0, 1: enable
+//Bit 26 , hb_status_int unsigned, default = 0, 1: enable
+//Bit 25 , losthb_int unsigned, default = 0, 1: enable
+//Bit 24 , timeout_int unsigned, default = 0, 1: enable
+//Bit 23 , status_ch_int unsigned, default = 0, 1: enable
+//Bit 22 , int_recv_finished unsigned, default = 0, 1: enable
+//Bit 21 , int_rdata unsigned, default = 0, 1: enable
+//Bit 20 , int_recv_nack unsigned, default = 0, 1: enable
+//Bit 19 , int_recv_norsp unsigned, default = 0, 1: enable
+//Bit 18 , int_recv_unexp unsigned, default = 0, 1: enable
+//Bit 17 , int_recv_data unsigned, default = 0, 1: enable
+//Bit 16 , int_recv_ack unsigned, default = 0, 1: enable
+//Bit 15 , int_recv_ecc_err unsigned, default = 0, 1: enable
+//Bit 14 , int_recv_packet unsigned, default = 0, 1: enable
+//Bit 13:0 , reserved
+#define EARC_TX_CMDC_TOP_CTRL1 ((0x0031 << 2) + 0xfe333000)
+//Bit 31:0, cmdc_top_ctrl1 //unsigned, RW, default = 0,
+#define EARC_TX_CMDC_TOP_CTRL2 ((0x0032 << 2) + 0xfe333000)
+//Bit 31 , reset_idle2_int unsigned, default = 0, 1: enable
+//Bit 30 , reset_idle1_int unsigned, default = 0, 1: enable
+//Bit 29 , reset_disc2_int unsigned, default = 0, 1: enable
+//Bit 28 , reset_disc1_int unsigned, default = 0, 1: enable
+//Bit 27 , reset_earc_int unsigned, default = 0, 1: enable
+//Bit 26 , reset_hb_status_int unsigned, default = 0, 1: enable
+//Bit 25 , reset_losthb_int unsigned, default = 0, 1: enable
+//Bit 24 , reset_timeout_int unsigned, default = 0, 1: enable
+//Bit 23 , reset_status_ch_int unsigned, default = 0, 1: enable
+//Bit 22 , reset_int_recv_finished unsigned, default = 0, 1: enable
+//Bit 21 , reset_int_rdata unsigned, default = 0, 1: enable
+//Bit 20 , reset_int_recv_nack unsigned, default = 0, 1: enable
+//Bit 19 , reset_int_recv_norsp unsigned, default = 0, 1: enable
+//Bit 18 , reset_int_recv_unexp unsigned, default = 0, 1: enable
+//Bit 17 , reset_int_recv_data unsigned, default = 0, 1: enable
+//Bit 16 , reset_int_recv_ack unsigned, default = 0, 1: enable
+//Bit 15 , reset_int_recv_ecc_err unsigned, default = 0, 1: enable
+//Bit 14 , reset_int_recv_packet unsigned, default = 0, 1: enable
+//Bit 13:0 , reserved
+#define EARC_TX_CMDC_TIMER_CTRL0 ((0x0033 << 2) + 0xfe333000)
+//Bit 31:0, cmdc_timer_ctrl0 //unsigned, RW, default = 0,
+#define EARC_TX_CMDC_TIMER_CTRL1 ((0x0034 << 2) + 0xfe333000)
+//Bit 31:0, cmdc_timer_ctrl1 //unsigned, RW, default = 0,
+#define EARC_TX_CMDC_TIMER_CTRL2 ((0x0035 << 2) + 0xfe333000)
+//Bit 31:0, cmdc_timer_ctrl2 //unsigned, RW, default = 0,
+#define EARC_TX_CMDC_TIMER_CTRL3 ((0x0036 << 2) + 0xfe333000)
+//Bit 31:0, cmdc_timer_ctrl3 //unsigned, RW, default = 0,
+#define EARC_TX_CMDC_VSM_CTRL0 ((0x0037 << 2) + 0xfe333000)
+//Bit 31, sw_state_update unsigned, default = 0, XX
+//Bit 30:28, sw_state unsigned, default = 0, XX
+//Bit 27, arc_initiated unsigned, default = 0, XX
+//Bit 26, arc_terminated unsigned, default = 0, XX
+//Bit 25, arc_enable unsigned, default = 1, XX
+//Bit 24, man_hpd unsigned, default = 0, XX
+//Bit 23:22, hpd_sel unsigned, default = 0, XX
+//Bit 21:20, hpd_sel_earc unsigned, default = 0, XX
+//Bit 19, comma_cnt_rst unsigned, default = 0, XX
+//Bit 18, timeout_status_rst unsigned, default = 0, XX
+//Bit 17, losthb_status_rst unsigned, default = 0, XX
+//Bit 16, force_rst unsigned, default = 0, XX
+//Bit 15, auto_state_en unsigned, default = 0, XX
+//Bit 14, cmdc_state_en unsigned, default = 0, XX
+//Bit 13, noack_repeat_en unsigned, default = 0, XX
+//Bit 12:0, reserved
+#define EARC_TX_CMDC_VSM_CTRL1 ((0x0038 << 2) + 0xfe333000)
+//Bit 31:9, reserved
+//Bit 8, cntl_hpd_sel unsigned, default = 0, 0:sel hd_hpd,1:sel hdmirx_hpd
+//Bit 7:0, comma_cnt_th unsigned, default = 0, should bigger than 3 and small than 10
+#define EARC_TX_CMDC_VSM_CTRL2 ((0x0039 << 2) + 0xfe333000)
+//Bit 31:12, max_count_th unsigned, default = 0, disc1 hpd_val timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, disc1 hpd_val timing
+//Bit 6:4, time_sel unsigned, default = 0, disc1 hpd_val timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, disc1 hpd_val timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, disc1 hpd_val timing
+#define EARC_TX_CMDC_VSM_CTRL3 ((0x003a << 2) + 0xfe333000)
+//Bit 31:12, max_count_th unsigned, default = 0, disc2 heartbeat act timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, disc2 heartbeat act timing
+//Bit 6:4, time_sel unsigned, default = 0, disc2 heartbeat act timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, disc2 heartbeat act timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, disc2 heartbeat act timing
+#define EARC_TX_CMDC_VSM_CTRL4 ((0x003b << 2) + 0xfe333000)
+//Bit 31:12, max_count_th unsigned, default = 0, in disc2, no heartbeat ack timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, in disc2, no heartbeat ack timing
+//Bit 6:4, time_sel unsigned, default = 0, in disc2, no heartbeat ack timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, in disc2, no heartbeat ack timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, in disc2, no heartbeat ack timing
+#define EARC_TX_CMDC_VSM_CTRL5 ((0x003c << 2) + 0xfe333000)
+//Bit 31:12, max_count_th unsigned, default = 0, in disc1 and disc2 timing out
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, in disc1 and disc2 timing out
+//Bit 6:4, time_sel unsigned, default = 0, in disc1 and disc2 timing out
+//Bit 3:2, soft_rst_sel unsigned, default = 0, in disc1 and disc2 timing out
+//Bit 1:0, enable_ctrl unsigned, default = 0, in disc1 and disc2 timing out
+#define EARC_TX_CMDC_VSM_CTRL6 ((0x003d << 2) + 0xfe333000)
+//Bit 31:12, max_count_th unsigned, default = 0, in earc heartbeat act timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, in earc heartbeat act timing
+//Bit 6:4, time_sel unsigned, default = 0, in earc heartbeat act timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, in earc heartbeat act timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, in earc heartbeat act timing
+#define EARC_TX_CMDC_VSM_CTRL7 ((0x003e << 2) + 0xfe333000)
+//Bit 31:16, reserved
+//Bit 15:8, status_soft_val unsigned, default = 0, in earc heartbeat det timing
+//Bit 7, reg_soft_rst unsigned, default = 0, in earc heartbeat det timing
+//Bit 6, status_rst unsigned, default = 0, in earc heartbeat det timing
+//Bit 5:4, reserved
+//Bit 3:2, soft_rst_sel unsigned, default = 0, in earc heartbeat det timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, in earc heartbeat det timing
+#define EARC_TX_CMDC_VSM_CTRL8 ((0x003f << 2) + 0xfe333000)
+//Bit 31:0, cmdc_vsm_ctrl8 //unsigned, RW, default = 0,
+#define EARC_TX_CMDC_VSM_CTRL9 ((0x0041 << 2) + 0xfe333000)
+//Bit 31:0, cmdc_vsm_ctrl9 //unsigned, RW, default = 0
+#define EARC_TX_CMDC_SENDER_CTRL0 ((0x0042 << 2) + 0xfe333000)
+//Bit 31:2, sender_ctrl0 unsigned, default = 0,
+//Bit 1, hb_chg_conf_auto unsigned, default = 1,
+//Bit 0, hb_chg_auto unsigned, default = 0,
+#define EARC_TX_CMDC_PACKET_CTRL0 ((0x0043 << 2) + 0xfe333000)
+//Bit 31, packet_mode_enable unsigned, default = 0, packet control
+//Bit 30, free_enable unsigned, default = 0, packet control
+//Bit 29, soft_rst unsigned, default = 0, packet control
+//Bit 28:24, tx_ready_threshold unsigned, default = 0, packet control
+//Bit 23:20, reserved
+//Bit 19:8, send_pre_threshold unsigned, default = 0, packet control
+//Bit 7:6, reserved
+//Bit 5, state_auto_en unsigned, default = 0, packet control
+//Bit 4, sw_state_update_en unsigned, default = 0, packet control
+//Bit 3:0, sw_state_value unsigned, default = 0, packet control
+#define EARC_TX_CMDC_PACKET_CTRL1 ((0x0044 << 2) + 0xfe333000)
+//Bit 31, ecc_endian unsigned, default = 0, send
+//Bit 30, pre_start_value unsigned, default = 0, send
+//Bit 29:21, reserved
+//Bit 20:16, post_threshold unsigned, default = 0, send
+//Bit 15:14, reserved
+//Bit 13:8, pre_threshold unsigned, default = 0, XX
+//Bit 7:0, post_flag unsigned, default = 0, XX
+#define EARC_TX_CMDC_PACKET_CTRL2 ((0x0045 << 2) + 0xfe333000)
+//Bit 31:0, pre_flag unsigned, default = 0, XX
+#define EARC_TX_CMDC_PACKET_CTRL3 ((0x0046 << 2) + 0xfe333000)
+//Bit 31, recv_en unsigned, default = 0, XX
+//Bit 30, recv_parity_mask unsigned, default = 0, XX
+//Bit 29, recv_timeout_en unsigned, default = 0, XX
+//Bit 28, bch_ecc_en unsigned, default = 0, xx
+//Bit 27:16, reserved
+//Bit 15:0, recv_timeout_threshold unsigned, default = 0, XX
+#define EARC_TX_CMDC_PACKET_CTRL4 ((0x0047 << 2) + 0xfe333000)
+//Bit 31:20, reserved
+//Bit 19:0, recv_packet_head unsigned, default = 0, XX
+#define EARC_TX_CMDC_PACKET_CTRL5 ((0x0048 << 2) + 0xfe333000)
+//Bit 31:20, reserved
+//Bit 19:0, recv_packet_head_mask unsigned, default = 0, XX
+#define EARC_TX_CMDC_PACKET_CTRL6 ((0x0049 << 2) + 0xfe333000)
+//Bit 31:20, recv_pre_threshold unsigned, default = 0, packet control
+//Bit 19:7, reserved
+//Bit 6, recv_finished_int unsigned, default = 0, XX
+//Bit 5, recv_ecc_err_int unsigned, default = 0, XX
+//Bit 4, recv_ack_int unsigned, default = 0, XX
+//Bit 3, recv_data_int unsigned, default = 0, XX
+//Bit 2, recv_unexp_int unsigned, default = 0, XX
+//Bit 1, recv_norsp_int unsigned, default = 0, XX
+//Bit 0, recv_nack_int unsigned, default = 0, XX
+#define EARC_TX_CMDC_BIPHASE_CTRL0 ((0x004a << 2) + 0xfe333000)
+//Bit 31:24, reserved
+//Bit 23:16, ack delay threshold unsigned, default = 0, xx
+//Bit 15:10, reserved
+//Bit 9, send_ack_en unsigned, default = 0, xx
+//Bit 8, sq_val_en unsigned, default = 0, XX
+//Bit 7, biphase_send_soft_rst unsigned, default = 0, XX
+//Bit 6, comma_soft_rst unsigned, default = 0, XX
+//Bit 5, fifo_rst unsigned, default = 0, XX
+//Bit 4, receiver_no_sender unsigned, default = 0, XX
+//Bit 3, sender_free unsigned, default = 0, XX
+//Bit 2, receiver_send unsigned, default = 0, XX
+//Bit 1, receiver_earc unsigned, default = 0, XX
+//Bit 0, receiver_free unsigned, default = 0, XX
+#define EARC_TX_CMDC_BIPHASE_CTRL1 ((0x004b << 2) + 0xfe333000)
+//Bit 31:16, reserved
+//Bit 15, ack_enable unsigned, default = 0, send
+//Bit 14:8, reserved
+//Bit 7:0, wait_threshold before ack unsigned, default = 0, send
+#define EARC_TX_CMDC_BIPHASE_CTRL2 ((0x004c << 2) + 0xfe333000)
+//Bit 31, comma_detection_enable unsigned, default = 0, comma detection
+//Bit 30, manual_reset_enable unsigned, default = 0, manual reset select, 1: manual
+//Bit 29, manual_reset_value unsigned, default = 0, manual reset control
+//Bit 28:16, reserved
+//Bit 15:0, comma_detection_threshold unsigned, default = 0,
+#define EARC_TX_CMDC_BIPHASE_CTRL3 ((0x004d << 2) + 0xfe333000)
+//Bit 31:0, cmdc_biphase_ctrl3 unsigned, default = 0,
+#define EARC_TX_CMDC_DEVICE_ID_CTRL ((0x004e << 2) + 0xfe333000)
+//Bit 31, apb_write unsigned, default = 0, apb bus wr/read
+//Bit 30, apb_read unsigned, default = 0, apb bus wr/read
+//Bit 29, apb_rw_done unsigned, default = 0, apb bus wr/read
+//Bit 28, apb_rw_reset unsigned, default = 0, apb bus wr/read
+//Bit 27:17, reserved
+//Bit 16, hpb_rst_enable unsigned, default = 1, hpd rst enable
+//Bit 15:8, apb_rwid unsigned, default = 0, apb bus wr/read
+//Bit 7:0, apbrw_start_addr unsigned, default = 0, apb bus wr/read
+#define EARC_TX_CMDC_DEVICE_WDATA ((0x004f << 2) + 0xfe333000)
+//Bit 31:8, reserved
+//Bit 7:0, apb_write_data unsigned, default = 0, apb bus wr/read
+#define EARC_TX_CMDC_DEVICE_RDATA ((0x0050 << 2) + 0xfe333000)
+//Bit 31:8, reserved
+//Bit 7:0, apb_read_data unsigned, default = 0, apb bus wr/read
+#define EARC_TX_CMDC_MASTER_CTRL ((0x0051 << 2) + 0xfe333000)
+//Bit 31, master_cmd_rw unsigned, default = 0, 1 write 0 read
+//Bit 30, master_hb_ignore unsigned, default =0, 0:wait hb issued before pkt cmd, 1: pkt cmd issued immediately
+//Bit 29, master_idle unsigned, default = 0, master status
+//Bit 28, master_cmd_soft_rst unsigned, default= 0,
+//Bit 27:24, hb_cmd_cal_th unsigned, default= 0,
+//Bit 23:16, master_cmd_count unsigned, default = 0, cmd count -1
+//Bit 15:8, master_cmd_id unsigned, default = 0,
+//Bit 7:0, master_cmd_address unsigned, default = 0,
+#define EARC_TX_ANA_CTRL0 ((0x0052 << 2) + 0xfe333000)
+//Bit 31:0, reg_earctx_ana_ctrl0 //unsigned, RW, default = 0,
+#define EARC_TX_ANA_CTRL1 ((0x0053 << 2) + 0xfe333000)
+//Bit 31:0, reg_earctx_ana_ctrl1 //unsigned, RW, default = 0,
+#define EARC_TX_ANA_CTRL2 ((0x0054 << 2) + 0xfe333000)
+//Bit 31:0, reg_earctx_ana_ctrl2 //unsigned, RW, default = 0,
+#define EARC_TX_ANA_CTRL3 ((0x0055 << 2) + 0xfe333000)
+//Bit 31:0, reg_earctx_ana_ctrl3 //unsigned, RW, default = 0,
+#define EARC_TX_ANA_CTRL4 ((0x0056 << 2) + 0xfe333000)
+//Bit 31:0, reg_earctx_ana_ctrl4 //unsigned, RW, default = 0,
+#define EARC_TX_ANA_CTRL5 ((0x0057 << 2) + 0xfe333000)
+//Bit 31:0, reg_earctx_ana_ctrl5 //unsigned, RW, default = 0,
+#define EARC_TX_ANA_STAT0 ((0x0058 << 2) + 0xfe333000)
+//Bit 31:0, ro_ANA_status0 //unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS0 ((0x0059 << 2) + 0xfe333000)
+//Bit 31:0, ro_cmdc_status0 //unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS1 ((0x005a << 2) + 0xfe333000)
+//Bit 31:0, ro_cmdc_status1 ///unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS2 ((0x005b << 2) + 0xfe333000)
+//Bit 31:0, ro_cmdc_status2 ///unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS3 ((0x005c << 2) + 0xfe333000)
+//Bit 31:0, ro_cmdc_status3 ///unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS4 ((0x005d << 2) + 0xfe333000)
+//Bit 31:0, ro_cmdc_status4 ///unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS5 ((0x005e << 2) + 0xfe333000)
+//Bit 31:0, ro_cmdc_status5 ///unsigned, RO, default = 0,
+#define EARC_TX_CMDC_STATUS6 ((0x005f << 2) + 0xfe333000)
+//Bit 31 , ro_idle2_int unsigned, RO, default = 0
+//Bit 30 , ro_idle1_int unsigned, RO, default = 0
+//Bit 29 , ro_disc2_int unsigned, RO, default = 0
+//Bit 28 , ro_disc1_int unsigned, RO, default = 0
+//Bit 27 , ro_earc_int unsigned, RO, default = 0
+//Bit 26 , ro_hb_status_int unsigned, RO, default = 0
+//Bit 25 , ro_losthb_int unsigned, RO, default = 0
+//Bit 24 , ro_timeout_int unsigned, RO, default = 0
+//Bit 23 , ro_status_ch_int unsigned, RO, default = 0
+//Bit 22 , ro_int_recv_finished unsigned, RO, default = 0
+//Bit 21 , ro_int_rdata unsigned, RO, default = 0
+//Bit 20 , ro_int_recv_nack unsigned, RO, default = 0
+//Bit 19 , ro_int_recv_norsp unsigned, RO, default = 0
+//Bit 18 , ro_int_recv_unexp unsigned, RO, default = 0
+//Bit 17 , ro_int_recv_data unsigned, RO, default = 0
+//Bit 16 , ro_int_recv_ack unsigned, RO, default = 0
+//Bit 15 , ro_int_recv_ecc_err unsigned, RO, default = 0
+//Bit 14 , ro_int_recv_packet unsigned, RO, default = 0
+//Bit 13:0 , reserved
+//
+// Closing file: earc_tx_cmdc.h
+//
+//========================================================================
+// AUDIO EARCTX_DMAC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe333400
+// -----------------------------------------------
+//
+// Reading file: earctx_dmac.h
+//
+#define EARCTX_DMAC_TOP_CTRL0 ((0x0000 << 2) + 0xfe333400)
+//Bit 31, reg_top_reg_sync ,default = 0,Bit 3:0 sync to clk10m,pluse auto clear
+//Bit 30, reg_top_soft_rst ,default = 0
+//Bit 29:26, reserved
+//Bit 25:24, reg_debug_mux ,default = 0
+//Bit 23:21, reserved
+//Bit 20, reg_slow_sync_scan_reg ,default = 0
+//Bit 19, reg_fe_sf_scan_reg ,default = 0
+//Bit 18, reg_fe_slow_sync_scan_reg ,default = 0
+//Bit 17, reg_top_sf_scan_reg ,default = 0
+//Bit 16, reg_top_slow_sync_scan_reg ,default = 0
+//Bit 15:4, reserved
+//Bit 3, reg_spdif_tx_en_force ,default = 0,spdif_tx_en force enable
+//Bit 2, reg_spdif_tx_en_force_value ,default = 0,spdif_tx_en force value
+//Bit 1, reg_dmac_tx_en_force ,default = 0,dmac_tx_en force enable
+//Bit 0, reg_dmac_tx_en_force_value ,default = 0,dmac_tx_en force value
+#define EARCTX_MUTE_VAL ((0x0001 << 2) + 0xfe333400)
+//Bit 31:0, reg_spdif_mute_val ,default = 0,when biahpase encode mute,the channel value,with reg_mute_l/reg_mute_r
+#define EARCTX_SPDIFOUT_GAIN0 ((0x0002 << 2) + 0xfe333400)
+//Bit 31:24, reg_gain_ch3 ,default = 0,channel 3 gain
+//Bit 23:16, reg_gain_ch2 ,default = 0,channel 2 gain
+//Bit 15:8, reg_gain_ch1 ,default = 0,channel 1 gain
+//Bit 7:0, reg_gain_ch0 ,default = 0,channel 0 gain
+#define EARCTX_SPDIFOUT_GAIN1 ((0x0003 << 2) + 0xfe333400)
+//Bit 31:24, reg_gain_ch7 ,default = 0,channel 7 gain
+//Bit 23:16, reg_gain_ch6 ,default = 0,channel 6 gain
+//Bit 15:8, reg_gain_ch5 ,default = 0,channel 5 gain
+//Bit 7:0, reg_gain_ch4 ,default = 0,channel 4 gain
+#define EARCTX_SPDIFOUT_CTRL0 ((0x0004 << 2) + 0xfe333400)
+//Bit 31, reg_work_start ,default = 0,biphase work start,pluse
+//Bit 30, reg_work_clr ,default = 0,biphase work clear,pluse
+//Bit 29, reg_rst_afifo_out_n ,default = 0,afifo out reset
+//Bit 28, reg_rst_afifo_in_n ,default = 0,afifo in reset
+//Bit 27, reg_hold_for_tdm ,default = 0,add delay to mathc TDM out when share buff
+//Bit 26, reg_userdata_sel ,default = 0,user Bit select : 0 from reg_userdata_set 1 from data[29]
+//Bit 25, reg_userdata_set ,default = 0
+//Bit 24, reg_chdata_sel ,default = 0,0 :from reg_chstst 1 from data[30]
+//Bit 23, reserved
+//Bit 22, reg_mute_l ,default = 0,r channel mute ,with reg_mute_val
+//Bit 21, reg_mute_r ,default = 0,l channel mute ,with reg_mute_val
+//Bit 20, reg_data_sel ,default = 0,0 data from 31Bit 1 data from 27bit
+//Bit 19, reg_out_msb_first ,default = 0,0 lsb first 1 msb first
+//Bit 18, reg_valid_sel ,default = 0,biphase encode valid Bit value sel : 0 from data 1 from reg_valid_set
+//Bit 17, reg_valid_set ,default = 0,biphase encode valid Bit value
+//Bit 16, reg_mute_hold_init_en ,default = 0,when c_mute_hold_last_err_corrt valid,clear work enable, initial biphase encode
+//Bit 15:12, reserved
+//Bit 0, reg_parity_mask ,default = 0,Bit 0 is initial parity value
+#define EARCTX_SPDIFOUT_CTRL1 ((0x0005 << 2) + 0xfe333400)
+//Bit 31, reg_eq_drc_sel ,default = 0,set 1 select eq_drc data
+//Bit 30, reg_keep_req_ddr_init ,default = 0,reg_keep_req_ddr_init
+//Bit 29:28, reserved
+//Bit 27, reg_gain_en ,default = 0,gain enable
+//Bit 26:24, reg_frddr_sel ,default = 0,from ddr selet
+//Bit 23:16, reg_wait_cnt ,default = 0,wait some time when enalble set to 1
+//Bit 15:13, reserved
+//Bit 12:8, reg_frddr_msb ,default = 0,msb position of data
+//Bit 7, reg_force_start ,default = 0,set 1 no need ack from frddr to transmit channel status
+//Bit 6:4, reg_frddr_type ,default = 0
+//Bit 3:0, reserved
+#define EARCTX_SPDIFOUT_PREAMB ((0x0006 << 2) + 0xfe333400)
+//Bit 31, reg_premable_Z_set ,default = 0,user 8'b11101000 1 user 7:0
+//Bit 30, reg_premable_Y_set ,default = 0,user 8'b11100100 1 user 15:8
+//Bit 29, reg_premable_X_set ,default = 0,user 8'b11100010 1 user 23:16
+//Bit 28:24, reserved
+//Bit 23:16, reg_premable_X_value ,default = 0
+//Bit 15:8, reg_premable_Y_value ,default = 0
+//Bit 7:0, reg_premable_Z_value ,default = 0
+#define EARCTX_SPDIFOUT_SWAP ((0x0007 << 2) + 0xfe333400)
+//Bit 31:16, reg_hold_cnt ,default = 0,hold start cnt ,valid when reg_hold_for_tdm set 1
+//Bit 15, reg_init_send_en ,default = 0,send 01 squence some times after intial done from frddr set
+//Bit 14:0, reg_init_send_cnt ,default = 0,send 01 squence time ,valid when reg_init_send_en set 1
+#define EARCTX_ERR_CORRT_CTRL0 ((0x0008 << 2) + 0xfe333400)
+//Bit 31:24, reserved
+//Bit 23, reg_bch_in_reverse ,default = 0,bch input data generate in 24it data reverse
+//Bit 22, reg_bch_out_ecc_reverse ,default = 0,bch output ecc reverse
+//Bit 21, reg_bch_out_data_reverse ,default = 0,bch output data reverse
+//Bit 20, reg_bch_out_ecc_msb ,default = 0,bch output ecc position
+//Bit 19:17, reserved
+//Bit 16, reg_ubit_fifo_init_n,default = 0,fifo in initial
+//Bit 15:14, reserved
+//Bit 13:12, reg_gain_shift ,default = 0,gain x 1/2/4/8
+//Bit 11, reg_mix_lr ,default = 0,l/r mix
+//Bit 10:8, reg_spdifout_r_sel ,default = 0,r channel select
+//Bit 7, reserved
+//Bit 6:4, reg_spdifout_l_sel ,default = 0,l channel select
+//Bit 3:0, reg_iu_interval ,default = 0,iu transmit interval
+#define EARCTX_ERR_CORRT_CTRL1 ((0x0009 << 2) + 0xfe333400)
+//Bit 31, reg_ubit_fifo_wr ,default = 0,iu data write enable,pluse,auto clr in reg.v
+//Bit 30:8, reserved
+//Bit 7:0, reg_ubit_fifo_wdata ,default = 0,iu data
+#define EARCTX_ERR_CORRT_CTRL2 ((0x000a << 2) + 0xfe333400)
+//Bit 31, reg_mute_clear ,default = 0,mute clear,pluse,auto clr in reg.v
+//Bit 30, reg_mute_start ,default = 0,mute start,pluse,auto clr in reg.v
+//Bit 29:28, reserved
+//Bit 27:16, reg_mute_block_num ,default = 0,mute block number
+//Bit 15:8, reg_mute_ch_Bit ,default = 0,mute Bit at channel statue which bit
+//Bit 7:3, reserved
+//Bit 2, reg_mute_data_sel ,default = 0,mute data sel: 0 data 1 reg_mute_data_value
+//Bit 1:0, reg_mute_mode ,default = 0,0:always mute 1:mute block number and dis mute 2:mute bolck number and hold bus
+#define EARCTX_ERR_CORRT_CTRL3 ((0x000b << 2) + 0xfe333400)
+//Bit 31:30, reserved
+//Bit 29, reg_bch_en ,default = 0,bch generate enable
+//Bit 28:24, reg_bch_msb ,default = 0,bch data msb position in audio data
+//Bit 23:0, reg_mute_data_value ,default = 0,mute value,only for audio data part
+#define EARCTX_ERR_CORRT_CTRL4 ((0x000c << 2) + 0xfe333400)
+//Bit 31, reg_ubit_fifo_lr_swap ,default = 0,//user Bit lr swap
+//Bit 30, reg_ubit_fifo_lr_same ,default = 0,//l/r channel use same Bit user bit
+//Bit 29:25, reg_data_msb ,default = 0,audio data msb postion in input data
+//Bit 24, reg_data_rsv ,default = 0,audio data msb/lsb
+//Bit 23, reg_ubit_value ,default = 0,user Bit value
+//Bit 22, reg_vbit_value ,default = 0,valid Bit value
+//Bit 21, reg_data_sel ,default = 0,//data sel: 0 data 1 reg_mute_data_value
+//Bit 20:19, reg_ubit_sel ,default = 0,//userBit sel: 0 data 1 reg_value 2 fifo data
+//Bit 18, reg_vbit_sel ,default = 0,//validBit sel: 0 data 1 reg_value
+//Bit 17, reg_chst_sel ,default = 0,//chanel status sel: 0 data 1 reg_value
+//Bit 16, reg_ubit_fifo_less_irq_en ,default = 0,fifo_less_thd irq enable
+//Bit 15:8, reg_ubit_fifo_start_thd ,default = 0,start transmit iu after fifo level greater than this value
+//Bit 7:0, reg_ubit_fifo_less_thd ,default = 0,generate irq,when fifo level less than this value
+#define EARCTX_ERR_CORRT_STAT0 ((0x000d << 2) + 0xfe333400)
+//Bit 31:0, ro_err_corrt_stat0 ,default = 0,
+#define EARCTX_SPDIFOUT_CHSTS0 ((0x000e << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_a_status ,default =0,channel A status[31:0]
+#define EARCTX_SPDIFOUT_CHSTS1 ((0x000f << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_a_status ,default =0,channel A status[63:32]
+#define EARCTX_SPDIFOUT_CHSTS2 ((0x0010 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_a_status ,default =0,channel A status[95:64]
+#define EARCTX_SPDIFOUT_CHSTS3 ((0x0011 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_a_status ,default =0,channel A status[127:96]
+#define EARCTX_SPDIFOUT_CHSTS4 ((0x0012 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_a_status ,default =0,channel A status[159:128]
+#define EARCTX_SPDIFOUT_CHSTS5 ((0x0013 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_a_status ,default =0,channel A status[191:160]
+#define EARCTX_SPDIFOUT_CHSTS6 ((0x0014 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_b_status ,default =0,channel B status[31:0]
+#define EARCTX_SPDIFOUT_CHSTS7 ((0x0015 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_b_status ,default =0,channel B status[63:32]
+#define EARCTX_SPDIFOUT_CHSTS8 ((0x0016 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_b_status ,default =0,channel B status[95:64]
+#define EARCTX_SPDIFOUT_CHSTS9 ((0x0017 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_b_status ,default =0,channel B status[127:96]
+#define EARCTX_SPDIFOUT_CHSTSA ((0x0018 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_b_status ,default =0,channel B status[159:128]
+#define EARCTX_SPDIFOUT_CHSTSB ((0x0019 << 2) + 0xfe333400)
+//Bit 31:0, reg_changel_b_status ,default =0,channel B status[191:160]
+#define EARCTX_FE_CTRL0 ((0x001a << 2) + 0xfe333400)
+//Bit 31, reg_mute_hold_clr ,default = 0,clear mute hold statues,pluse, auto clr
+//Bit 30, reg_work_enable ,default = 0,wore enable
+//Bit 29, reg_dmac_invt ,default = 0,fe out invent
+//Bit 28, reg_hold_time_en ,default = 0,hold min time enable
+//Bit 27, reg_hold_soft_clr_en ,default = 0,0 auto clear hold at next valid 1 clear hold with reg_mute_hold_clr
+//Bit 26:24, reg_hold_time_tick_sel ,default = 0,hold min time tick select
+//Bit 23:0, reg_hold_min_time ,default = 0,hold min time
+#define EARCTX_FE_STAT0 ((0x001b << 2) + 0xfe333400)
+//Bit 31:0, ro_fe_stat0 ,default = 0,
+#define EARCTX_SPDIFOUT_STAT ((0x001c << 2) + 0xfe333400)
+//Bit 31:0, ro_spdifout_stat ,default = 0,
+#define EARCTX_SPDIFOUT_CTRL2 ((0x001d << 2) + 0xfe333400)
+//Bit 31:28, reserved
+//Bit 27:16, reg_clr_by_init ,default = 0,reg_clr_by_init
+//Bit 15:0 , reg_mask ,default = 0,reg_mask
+#define EARCTX_SPDIFOUT_GAIN2 ((0x001e << 2) + 0xfe333400)
+//Bit 31:0, spdifout_gain2 ,default = 0,spdifout gain2
+#define EARCTX_SPDIFOUT_GAIN3 ((0x001f << 2) + 0xfe333400)
+//Bit 31:0, spdifout_gain3 ,default = 0,spdifout gain3
+#define EARCTX_SPDIFOUT_GAIN4 ((0x0020 << 2) + 0xfe333400)
+//Bit 31:0, spdifout_gain4 ,default = 0,spdifout gain4
+#define EARCTX_SPDIFOUT_GAIN5 ((0x0021 << 2) + 0xfe333400)
+//Bit 31:0, spdifout_gain5 ,default = 0,spdifout gain5
+//
+//
+// Closing file: earctx_dmac.h
+//
+//========================================================================
+// AUDIO EARCTX_TOP - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xff603600
+// -----------------------------------------------
+//
+// Reading file: earctx_top.h
+//
+#define EARCTX_TOP_CTRL0 ((0x0000 << 2) + 0xff603600)
+//Bit 31:18, reserved
+//Bit 17:16, reg_earctx_debug_mux unsigned, default = 0, debug mux
+//Bit 15, reg_slow_sync_scan_reg unsigned, default = 0, reg_slow_sync_scan_reg
+//Bit 14:12, reserved
+//Bit 11, reg_hdmi_hpd_invt unsigned, default = 0, hdmi_hpd invent
+//Bit 10, reg_hdmi_hpd_value unsigned, default = 0, hdmi_hpd mux = 3,register value
+//Bit 9:8, reg_hdmi_hpd_mux unsigned, default = 0, hdmi_hpd mux
+//Bit 7, reg_earctx_hd_hpd_invt unsigned, default = 0, earctx_hd_hdp invent
+//Bit 6, reg_earctx_hd_hpd_value unsigned, default = 0, earctx_hd_hdp mux = 3,register value
+//Bit 5:4, reg_earctx_hd_hdp_mux unsigned, default = 0, earctx_hd_hdp mux
+//Bit 3:2, reserved
+//Bit 1, reg_earctx_force_mode_en unsigned, default = 0, force mode enale
+//Bit 0, reg_earctx_force_mode unsigned, default = 0, force mode value
+#define EARCTX_DMAC_INT_MASK ((0x0001 << 2) + 0xff603600)
+//Bit 31:6, reserved
+//Bit 5:0, reg_dmac_int_mask unsigned, default = 0, dmac int mask
+#define EARCTX_DMAC_INT_PENDING ((0x0002 << 2) + 0xff603600)
+//Bit 31:6, reserved
+//Bit 5:0, reg_dmac_int_mask unsigned, default = 0, dmac int pending,read only
+#define EARCTX_CMDC_INT_MASK ((0x0003 << 2) + 0xff603600)
+//Bit 31:18, reserved
+//Bit 17:0, reg_cmdc_int_mask unsigned, default = 0, cmdc int mask
+#define EARCTX_CMDC_INT_PENDING ((0x0004 << 2) + 0xff603600)
+//Bit 31:18, reserved
+//Bit 17:0, reg_cmdc_int_mask unsigned, default = 0, cmdc int pending,read only
+#define EARCTX_ANA_CTRL0 ((0x0005 << 2) + 0xff603600)
+//Bit 31:0, reg_earctx_ana_ctrl0 unsigned, default = 0
+#define EARCTX_ANA_CTRL1 ((0x0006 << 2) + 0xff603600)
+//Bit 31:0, reg_earctx_ana_ctrl0 unsigned, default = 0
+#define EARCTX_ANA_CTRL2 ((0x0007 << 2) + 0xff603600)
+//Bit 31:0, reg_earctx_ana_ctrl0 unsigned, default = 0
+#define EARCTX_ANA_STAT0 ((0x0008 << 2) + 0xff603600)
+//Bit 31:0, reg_earctx_ana_ctrl0 unsigned, default = 0
+//
+// Closing file: earctx_top.h
+//
+//========================================================================
+// AUDIO EARCRX_CMDC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe333800
+// -----------------------------------------------
+//
+// Reading file: earc_rx_cmdc.h
+//
+#define EARC_RX_CMDC_TOP_CTRL0 ((0x0000 << 2) + 0xfe333800)
+//Bit 31 , idle2_int unsigned, default = 0, 1: enable
+//Bit 30 , idle1_int unsigned, default = 0, 1: enable
+//Bit 29 , disc2_int unsigned, default = 0, 1: enable
+//Bit 28 , disc1_int unsigned, default = 0, 1: enable
+//Bit 27 , earc_int unsigned, default = 0, 1: enable
+//Bit 26 , hb_status_int unsigned, default = 0, 1: enable
+//Bit 25 , losthb_int unsigned, default = 0, 1: enable
+//Bit 24 , timeout_int unsigned, default = 0, 1: enable
+//Bit 23 , status_ch_int unsigned, default = 0, 1: enable
+//Bit 22 , int_rec_invalid_id unsigned, default = 0, 1: enable
+//Bit 21 , int_rec_invalid_offset unsigned, default = 0, 1: enable
+//Bit 20 , int_rec_unexp unsigned, default = 0, 1: enable
+//Bit 19 , int_rec_ecc_err unsigned, default = 0, 1: enable
+//Bit 18 , int_rec_parity_err unsigned, default = 0, 1: enable
+//Bit 17 , int_recv_packet unsigned, default = 0, 1: enable
+//Bit 16 , int_rec_time_out unsigned, default = 0, 1: enable
+//Bit 15 , cmdc_debug0 unsigned, default = 0, 1: enable
+//Bit 14 , cmdc_debug1 unsigned, default = 0, 1: enable
+//Bit 13 , cmdc_debug2 unsigned, default = 0, 1: enable
+//Bit 12:7 , reserved
+//Bit 6 , mute_select unsigned, default = 0, 1: use bit5, 0: earc off
+//Bit 5 , mute_contrl unsigned, default = 0, value of mannul mute control
+//Bit 4:0 , reserved
+#define EARC_RX_CMDC_TOP_CTRL1 ((0x0001 << 2) + 0xfe333800)
+//Bit 31:13, reserved
+//Bit 12:8, reg_scan_reg unsigned, RW, default = 0,
+//Bit 7:5, reserved
+//Bit 4:0, reg_top_soft_rst unsigned, RW, default = 0,
+#define EARC_RX_CMDC_TOP_CTRL2 ((0x0002 << 2) + 0xfe333800)
+//Bit 31, reset_idle2_int unsigned, default =0
+//Bit 30, reset_idle1_int unsigned, default =0
+//Bit 29, reset_disc2_int unsigned, default =0
+//Bit 28, reset_disc1_int unsigned, default =0
+//Bit 27, reset_earc_int unsigned, default =0
+//Bit 26, reset_hb_status_int unsigned, default =0
+//Bit 25, reset_losthb_int unsigned, default =0
+//Bit 24, reset_timeout_int unsigned, default =0
+//Bit 23, reset_status_ch_int unsigned, default =0
+//Bit 22, reset_int_rec_invalid_id unsigned, default =0
+//Bit 21, reset_int_rec_invalid_offset unsigned, default =0
+//Bit 20, reset_int_rec_unexp unsigned, default =0
+//Bit 19, reset_int_rec_ecc_err unsigned, default =0
+//Bit 18, reset_int_rec_parity_err unsigned, default =0
+//Bit 17, reset_int_recv_packet unsigned, default =0
+//Bit 16, reset_int_rec_time_out unsigned, default =0
+//Bit 15:0, reserved
+#define EARC_RX_CMDC_TIMER_CTRL0 ((0x0003 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_TIMER_CTRL1 ((0x0004 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_TIMER_CTRL2 ((0x0005 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_TIMER_CTRL3 ((0x0006 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_VSM_CTRL0 ((0x0007 << 2) + 0xfe333800)
+//Bit 31, sw_state_update unsigned, default = 0, XX
+//Bit 30:28, sw_state unsigned, default = 0, XX
+//Bit 27, arc_initiated unsigned, default = 0, XX
+//Bit 26, arc_terminated unsigned, default = 0, XX
+//Bit 25, arc_enable unsigned, default = 0, XX
+//Bit 24, man_hpd unsigned, default = 0, XX
+//Bit 23:22, hpd_sel unsigned, default = 0, XX
+//Bit 21:20, hpd_sel_earc unsigned, default = 0, XX
+//Bit 19, comma_cnt_rst unsigned, default = 0, XX
+//Bit 18, timeout_status_rst unsigned, default = 0, XX
+//Bit 17, losthb_status_rst unsigned, default = 0, XX
+//Bit 16, force_rst unsigned, default = 0, XX
+//Bit 15, auto_state unsigned, default = 0, XX
+//Bit 14, cmdc_state_en unsigned, default = 0, XX
+//Bit 13:0, reserved
+#define EARC_RX_CMDC_VSM_CTRL1 ((0x0008 << 2) + 0xfe333800)
+//Bit 31:12, max_count_th unsigned, default = 0, idle done timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, idle done timing
+//Bit 6:4, time_sel unsigned, default = 0, idle done timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, idle done timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, idle done timing
+#define EARC_RX_CMDC_VSM_CTRL2 ((0x0009 << 2) + 0xfe333800)
+//Bit 31:12, max_count_th unsigned, default = 0, comma off done timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, comma off done timing
+//Bit 6:4, time_sel unsigned, default = 0, comma off done timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, comma off done timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, comma off done timing
+#define EARC_RX_CMDC_VSM_CTRL3 ((0x000a << 2) + 0xfe333800)
+//Bit 31:12, max_count_th unsigned, default = 0, earc_time out timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, earc_time out timing
+//Bit 6:4, time_sel unsigned, default = 0, earc_time out timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, earc_time out timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, earc_time out timing
+#define EARC_RX_CMDC_VSM_CTRL4 ((0x000b << 2) + 0xfe333800)
+//Bit 31:12, max_count_th unsigned, default = 0, heartbeat lost timing
+//Bit 11:8, reserved
+//Bit 7, reg_soft_rst unsigned, default = 0, heartbeat lost timing
+//Bit 6:4, time_sel unsigned, default = 0, heartbeat lost timing
+//Bit 3:2, soft_rst_sel unsigned, default = 0, heartbeat lost timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, heartbeat lost timing
+#define EARC_RX_CMDC_VSM_CTRL5 ((0x000c << 2) + 0xfe333800)
+//Bit 31:16, reserved
+//Bit 15:8, status_soft unsigned, default = 0, in earc heartbeat det timing
+//Bit 7, reg_soft_rst unsigned, default = 0, in earc heartbeat det timing
+//Bit 6, status_rst unsigned, default = 0, in earc heartbeat det timing
+//Bit 5:4, reserved
+//Bit 3:2, soft_rst_sel unsigned, default = 0, in earc heartbeat det timing
+//Bit 1:0, enable_ctrl unsigned, default = 0, in earc heartbeat det timing
+#define EARC_RX_CMDC_VSM_CTRL6 ((0x000d << 2) + 0xfe333800)
+//Bit 31:17, reserved
+//Bit 16, cntl_hpd_sel unsigned, default = 0, in earc heartbeat det timing
+//Bit 15:4, cntl_hpd_valid_width unsigned, default = 0, in earc heartbeat det timing
+//Bit 3:0, cntl_hpd_glitch_width unsigned, default = 0, in earc heartbeat det timing
+#define EARC_RX_CMDC_VSM_CTRL7 ((0x000e << 2) + 0xfe333800)
+//Bit 31:0, vsm_ctrl7 unsigned, default = 0,
+#define EARC_RX_CMDC_VSM_CTRL8 ((0x000f << 2) + 0xfe333800)
+//Bit 31:0, vsm_ctrl8 unsigned, default = 0,
+#define EARC_RX_CMDC_VSM_CTRL9 ((0x0010 << 2) + 0xfe333800)
+//Bit 31:0, vsm_ctrl9 unsigned, default = 0,
+#define EARC_RX_CMDC_SENDER_CTRL0 ((0x0011 << 2) + 0xfe333800)
+//Bit 31:2, reserved
+//Bit 1, hb_chg_conf_auto unsigned, default = 0,
+//Bit 0, hb_chg_auto unsigned, default = 1,
+#define EARC_RX_CMDC_PACKET_CTRL0 ((0x0012 << 2) + 0xfe333800)
+//Bit 31, packet_mode_enable unsigned, default = 0, packet control
+//Bit 30, free_enable unsigned, default = 0, packet control
+//Bit 29, soft_rst_man unsigned, default = 0, packet control
+//Bit 28:24, ready_th unsigned, default = 0, packet control
+//Bit 23:20, reserved
+//Bit 19:8, send_pre_th unsigned, default = 0, packet control
+//Bit 7:5, reserved
+//Bit 4, sw_state_update unsigned, default = 0, packet control
+//Bit 3:0, sw_state unsigned, default = 0, packet control
+#define EARC_RX_CMDC_PACKET_CTRL1 ((0x0013 << 2) + 0xfe333800)
+//Bit 31, ecc_endian unsigned, default = 0, send
+//Bit 30, pre_reg_st unsigned, default = 0, send
+//Bit 29:21, reserved
+//Bit 20:16, post_th unsigned, default = 0, send
+//Bit 15:14, reserved
+//Bit 13:8, pre_th unsigned, default = 0,
+//Bit 7:0, post_flag unsigned, default = 0,
+#define EARC_RX_CMDC_PACKET_CTRL2 ((0x0014 << 2) + 0xfe333800)
+//Bit 31:0, pre_flag unsigned, default = 0, X
+#define EARC_RX_CMDC_PACKET_CTRL3 ((0x0015 << 2) + 0xfe333800)
+//Bit 31, cmdc_en unsigned, default = 0, XX
+//Bit 30, cmdc_parity_mask unsigned, default = 0, XX
+//Bit 29, imeout_en unsigned, default = 0, XX
+//Bit 28, ecc_check_en unsigned, default = 0, XX
+//Bit 27, rev_debug_en unsigned, default = 0, XX
+//Bit 26:16, reserved
+//Bit 15:0, timeout_th unsigned, default = 0, X
+#define EARC_RX_CMDC_PACKET_CTRL4 ((0x0016 << 2) + 0xfe333800)
+//Bit 31, ack_ignore unsigned, default = 0, XX
+//Bit 30, cmdc_tail_check_mask unsigned, default = 0, XX
+//Bit 29:20, reserved
+//Bit 19:0, cmdc_packet_head unsigned, default = 0, XX
+#define EARC_RX_CMDC_PACKET_CTRL5 ((0x0017 << 2) + 0xfe333800)
+//Bit 31:24, rev_debug_mask unsigned, default = 0, XX
+//Bit 23:20, reserved
+//Bit 19:0, cmdc_packet_head_mask unsigned, default = 0, XX
+#define EARC_RX_CMDC_PACKET_CTRL6 ((0x0018 << 2) + 0xfe333800)
+//Bit 31:20, recv_pre_threshold unsigned, default = 0, packet control
+//Bit 19:9, reserved
+//Bit 8, rec_packet_d unsigned, default = 0, XX
+//Bit 7, rec_parity_err_cnt unsigned, default = 0, XX
+//Bit 6, rec_ecc_err_cnt unsigned, default = 0, XX
+//Bit 5, rec_unexp_cnt unsigned, default = 0, XX
+//Bit 4, rec_invalid_offset_cnt unsigned, default = 0, XX
+//Bit 3, rec_invalid_id_cnt unsigned, default = 0, XX
+//Bit 2, rec_timeout_cnt unsigned, default = 0, XX
+//Bit 1, rec_w_cnt unsigned, default = 0, XX
+//Bit 0, rec_r_cnt unsigned, default = 0, X
+#define EARC_RX_CMDC_BIPHASE_CTRL0 ((0x0019 << 2) + 0xfe333800)
+//Bit 31:24, reg_tns unsigned, default = 7, xx
+//Bit 23:16, delay_th unsigned, default = 0, xx
+//Bit 15:10, reserved
+//Bit 9, send_ack_en unsigned, default = 0, xx
+//Bit 8, sq_val_en unsigned, default = 0, XX
+//Bit 7, biphase_send_soft_rst unsigned, default = 0, XX
+//Bit 6, comma_soft_rst unsigned, default = 0, XX
+//Bit 5, fifo_rst unsigned, default = 0, XX
+//Bit 4, receiver_no_sender unsigned, default = 0, XX
+//Bit 3, sender_free unsigned, default = 0, XX
+//Bit 2, receiver_send unsigned, default = 0, XX
+//Bit 1, receiver_earc unsigned, default = 0, XX
+//Bit 0, receiver_free unsigned, default = 0, XX
+#define EARC_RX_CMDC_BIPHASE_CTRL1 ((0x001a << 2) + 0xfe333800)
+//Bit 31:16, reserved
+//Bit 15, ack_val_en unsigned, default = 0, send
+//Bit 14:8, reserved
+//Bit 7:0, width unsigned, default = 0, send
+#define EARC_RX_CMDC_BIPHASE_CTRL2 ((0x001b << 2) + 0xfe333800)
+//Bit 31, ack_val_en unsigned, default = 0, send
+//Bit 30:20, reserved
+//Bit 19:16, ack_rate unsigned, default = 0, comma send
+//Bit 15:0, width unsigned, default = 0, comma sen
+#define EARC_RX_CMDC_BIPHASE_CTRL3 ((0x001c << 2) + 0xfe333800)
+//Bit 31:0, biphase_ctrl3 unsigned, default = 0,
+#define EARC_RX_CMDC_DEVICE_ID_CTRL ((0x001d << 2) + 0xfe333800)
+//Bit 31, apb_write unsigned, default = 0, apb bus wr/read
+//Bit 30, apb_read unsigned, default = 0, apb bus wr/read
+//Bit 29, apb_w_r_done unsigned, default = 0, apb bus wr/read
+//Bit 28, apb_w_r_reset unsigned, default = 0, apb bus wr/read
+//Bit 27:16, reserved
+//Bit 15:8, apb_w_r_id unsigned, default = 0, apb bus wr/read
+//Bit 7:0, apb_w_r_start_addr unsigned, default = 0, apb bus wr/read
+#define EARC_RX_CMDC_DEVICE_WDATA ((0x001e << 2) + 0xfe333800)
+//Bit 31:8, reserved
+//Bit 7:0, apb_write_data unsigned, default = 0, apb bus wr/rea
+#define EARC_RX_CMDC_DEVICE_RDATA ((0x001f << 2) + 0xfe333800)
+//Bit 31:8, reserved
+//Bit 7:0, apb_read_data unsigned, default = 0, apb bus wr/rea
+#define EARC_RX_ANA_CTRL0 ((0x0020 << 2) + 0xfe333800)
+//Bit 31:0, ana_ctrl0 unsigned, default = 0,
+#define EARC_RX_ANA_CTRL1 ((0x0021 << 2) + 0xfe333800)
+//Bit 31:0, ana_ctrl1 unsigned, default = 0,
+#define EARC_RX_ANA_CTRL2 ((0x0022 << 2) + 0xfe333800)
+//Bit 31:0, ana_ctrl2 unsigned, default = 0,
+#define EARC_RX_ANA_CTRL3 ((0x0023 << 2) + 0xfe333800)
+//Bit 31:0, ana_ctrl3 unsigned, default = 0,
+#define EARC_RX_ANA_CTRL4 ((0x0024 << 2) + 0xfe333800)
+//Bit 31:0, ana_ctrl4 unsigned, default = 0,
+#define EARC_RX_ANA_CTRL5 ((0x0025 << 2) + 0xfe333800)
+//Bit 31:0, ana_ctrl5 unsigned, default = 0,
+#define EARC_RX_ANA_STAT0 ((0x0026 << 2) + 0xfe333800)
+//Bit 31:0, ro_ANA_status0 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS0 ((0x0027 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status0 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS1 ((0x0028 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status1 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS2 ((0x0029 << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status2 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS3 ((0x002a << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status3 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS4 ((0x002b << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status4 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS5 ((0x002c << 2) + 0xfe333800)
+//Bit 31:0, ro_cmdc_status5 unsigned, RO, default = 0,
+#define EARC_RX_CMDC_STATUS6 ((0x002d << 2) + 0xfe333800)
+//Bit 31, ro_idle2_int unsigned, RO, dfault =0
+//Bit 30, ro_idle1_int unsigned, RO, dfault =0
+//Bit 29, ro_disc2_int unsigned, RO, dfault =0
+//Bit 28, ro_disc1_int unsigned, RO, dfault =0
+//Bit 27, ro_earc_int unsigned, RO, dfault =0
+//Bit 26, ro_hb_status_int unsigned, RO, dfault =0
+//Bit 25, ro_losthb_int unsigned, RO, dfault =0
+//Bit 24, ro_timeout_int unsigned, RO, dfault =0
+//Bit 23, ro_status_ch_int unsigned, RO, dfault =0
+//Bit 22, ro_int_rec_invalid_id unsigned, RO, dfault =0
+//Bit 21, ro_int_rec_invalid_offset unsigned, RO, dfault =0
+//Bit 20, ro_int_rec_unexp unsigned, RO, dfault =0
+//Bit 19, ro_int_rec_ecc_err unsigned, RO, dfault =0
+//Bit 18, ro_int_rec_parity_err unsigned, RO, dfault =0
+//Bit 17, ro_int_recv_packet unsigned, RO, dfault =0
+//Bit 16, ro_int_rec_time_out unsigned, RO, dfault =0
+//Bit 15:0, reserved
+//
+// Closing file: earc_rx_cmdc.h
+//
+//========================================================================
+// AUDIO EARCRX_DMAC - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe333c00
+// -----------------------------------------------
+//
+// Reading file: earcrx_dmac.h
+//
+#define EARCRX_DMAC_TOP_CTRL0 ((0x0000 << 2) + 0xfe333c00)
+//Bit 31, reg_top_work_en unsigned, default = 0, top work enable
+//Bit 30, reg_top_soft_rst unsigned, default = 0, top soft reset
+//Bit 29:23, reserved
+//Bit 22:20, reg_dmac_debug_sel unsigned, default = 0, dmac debug select
+//Bit 19:18, reserved
+//Bit 17, reg_dmac_valid_sel unsigned, default = 0, dmac sync without clk
+//Bit 16, reg_dmac_without_clk unsigned, default = 0, dmac sync without clk
+//Bit 15, reg_sf_sync_scan_reg unsigned, default = 0, rst_n soft reset scan reg
+//Bit 14, reserved
+//Bit 13, reg_slow_sync_scan_reg unsigned, default = 0, rst_n sync clk_slow scan reg
+//Bit 12, reg_a_sync_scan_reg unsigned, default = 0, rst_n sync clk_analog scan reg
+//Bit 11, reg_slow_auto_gate unsigned, default = 0, clk_slow auto gate
+//Bit 10, reg_a_auto_gate unsigned, default = 0, clk_analog auto gate
+//Bit 9:0, reserved
+#define EARCRX_DMAC_SYNC_CTRL0 ((0x0001 << 2) + 0xfe333c00)
+//Bit 31, reg_work_enable unsigned, default = 0, dmac sync module work enable
+//Bit 30, reg_rst_afifo_out_n unsigned, default = 0, afifo out reset
+//Bit 29, reg_rst_afifo_in_n unsigned, default = 0, afifo in reset
+//Bit 28:17, reserved
+//Bit 16, reg_ana_buf_data_sel_en unsigned, default = 0, data from analog delay enable
+//Bit 15, reserved
+//Bit 14:12, reg_ana_buf_data_sel unsigned, default = 0, delay cycles
+//Bit 11, reserved
+//Bit 10:8, reg_ana_clr_cnt unsigned, default = 0, valid last how many 0 will clear
+//Bit 7, reserved
+//Bit 6:4, reg_ana_set_cnt unsigned, default = 0, valid last how may 1 will set
+//Bit 3:1, reserved
+//Bit 0, reg_dmacin_phase unsigned, default = 0, dmac data invert
+#define EARCRX_DMAC_SYNC_STAT0 ((0x0002 << 2) + 0xfe333c00)
+//Bit 31:0, reg_dmac_sync_stat0 unsigned, default = 0
+#define EARCRX_SPDIFIN_SAMPLE_CTRL0 ((0x0003 << 2) + 0xfe333c00)
+//Bit 31, reg_work_enable unsigned, default = 0, spdif in sample enable
+//Bit 30, reg_spdifin_phase unsigned, default = 0, spdif in invert
+//Bit 29, reg_debug_en unsigned, default = 0, debug single enable
+//Bit 28, reg_width_sel unsigned, default = 0, 0 detect by max_width 1 detect by min_width
+//Bit 27:23, reserved
+//Bit 22:20, reg_sample_mode unsigned, default = 0, value
+//Bit 19:0, reg_base_timer unsigned, default = 0, base timer to detect sample mode change
+#define EARCRX_SPDIFIN_SAMPLE_CTRL1 ((0x0004 << 2) + 0xfe333c00)
+//Bit 31, reg_force_sample_mode unsigned, default = 0, 0 auto detect sample mode 1 force a fixed sample mode with reg_sample_mode
+//Bit 30, reserved
+//Bit 29:20, reg_sample_mode0_timer_th unsigned, default = 0, mode0 threathold time
+//Bit 19:10, reg_sample_mode1_timer_th unsigned, default = 0, mode1 threathold time
+//Bit 9:0, reg_sample_mode2_timer_th unsigned, default = 0, mode2 threathold time
+#define EARCRX_SPDIFIN_SAMPLE_CTRL2 ((0x0005 << 2) + 0xfe333c00)
+//Bit 31:30, reserved
+//Bit 29:20, reg_sample_mode3_timer_th unsigned, default = 0, mode3 threathold time
+//Bit 19:10, reg_sample_mode4_timer_th unsigned, default = 0, mode4 threathold time
+//Bit 9:0, reg_sample_mode5_timer_th unsigned, default = 0, mode5 threathold time
+#define EARCRX_SPDIFIN_SAMPLE_CTRL3 ((0x0006 << 2) + 0xfe333c00)
+//Bit 31:24, reg_sample_mode0_timer unsigned, default = 0, mode0 sample time
+//Bit 23:16, reg_sample_mode1_timer unsigned, default = 0, mode1 sample time
+//Bit 15:8, reg_sample_mode2_timer unsigned, default = 0, mode2 sample time
+//Bit 7:0, reg_sample_mode3_timer unsigned, default = 0, mode3 sample time
+#define EARCRX_SPDIFIN_SAMPLE_CTRL4 ((0x0007 << 2) + 0xfe333c00)
+//Bit 31:24, reg_sample_mode4_timer unsigned, default = 0, mode4 sample time
+//Bit 23:16, reg_sample_mode5_timer unsigned, default = 0, mode5 sample time
+//Bit 15:8, reg_sample_mode6_timer unsigned, default = 0, mode6 sample time
+//Bit 7:0, reserved
+#define EARCRX_SPDIFIN_SAMPLE_CTRL5 ((0x0008 << 2) + 0xfe333c00)
+//Bit 31, reg_sq_filt_en unsigned, default = 0, dmac_sqout filter enable
+//Bit 30, reg_spdif_sqout_phase unsigned, default = 0, dmac_sqout invert
+//Bit 29:27, reg_filter_tick_sel unsigned, default = 0, dmac_sqout filter tick select
+//Bit 26:24, reg_filter_sel unsigned, default = 0, dmac_sqout filter select
+//Bit 23:20, reserved
+//Bit 19:0, reg_sq_filt_timer unsigned, default = 0, dmac_sqout filter tick
+#define EARCRX_SPDIFIN_SAMPLE_STAT0 ((0x0009 << 2) + 0xfe333c00)
+//Bit 31:0, reg_spdifin_sample_stat0 unsigned, default = 0
+#define EARCRX_SPDIFIN_SAMPLE_STAT1 ((0x000a << 2) + 0xfe333c00)
+//Bit 31:0, reg_spdifin_sample_stat1 unsigned, default = 0
+#define EARCRX_SPDIFIN_MUTE_VAL ((0x000b << 2) + 0xfe333c00)
+//Bit 31:0, reg_spdifin_mute_val unsigned, default = 0, spdif in mute value
+#define EARCRX_SPDIFIN_CTRL0 ((0x000c << 2) + 0xfe333c00)
+//Bit 31, reg_work_enable unsigned, default = 0, spdifin wore enable
+//Bit 30, reg_chnum_sel unsigned, default = 0, 0 ch_num = 0~383 1 ch_num = 0~1
+//Bit 29:28, reserved
+//Bit 27, reg_debug_en unsigned, default = 0, debug enable
+//Bit 26, reg_chnum_en unsigned, default = 0, star add ch_cnt to ch_num
+//Bit 25, reg_findpapb_en unsigned, default = 0, papb check enalbe
+//Bit 24, reg_nonpcm2pcm_en unsigned, default = 0, nonpcm2pcm_th enable
+//Bit 23:12, reg_nonpcm2pcm_th unsigned, default = 0, if long time didn't detect PaPb again,will generate irq
+//Bit 11:8, reg_ch_status_sel unsigned, default = 0, for stat1/stat2
+//Bit 7, reg_mute_l unsigned, default = 0, mute channel l
+//Bit 6, reg_mute_r unsigned, default = 0, mute channel r
+//Bit 5:4, reserved
+//Bit 3, reg_check_valid unsigned, default = 0, valid check enable
+//Bit 2, reg_check_parity unsigned, default = 0, parity check enable
+//Bit 1, reg_invert_data unsigned, default = 0, spdif data invert
+//Bit 0, reserved
+#define EARCRX_SPDIFIN_CTRL1 ((0x000d << 2) + 0xfe333c00)
+//Bit 31:24, reserved
+//Bit 31:24, reg_clr_internal_sts unsigned, default = 0, internal irq status clear
+//Bit 23:12, reg_mute_block_check_thd unsigned, default = 0, mute block check time thd
+//Bit 11:9, reg_mute_block_check_tick_sel unsigned, default = 0, mute block check tick sel
+//Bit 8, reg_papb_ext_sync unsigned, default = 0, ext 0 sync check for papb
+//Bit 7:0, reg_papb_ext_mask unsigned, default = 0, sync 0 mask
+#define EARCRX_SPDIFIN_CTRL2 ((0x000e << 2) + 0xfe333c00)
+//Bit 31:24, reg_mute_bit unsigned, default = 0, mute bit in channel st
+//Bit 23:19, reg_mute_block_num unsigned, default = 0, mute min block number to declare
+//Bit 18, reg_mute_lr_ch_sel unsigned, default = 0, mute bit in channel st L or R
+//Bit 17, reg_mute_block_check_en unsigned, default = 0, mute block number check enable
+//Bit 16, reg_earc_cps_chst_clr_en unsigned, default = 0, auto clear compress mode when channel status not compress
+//Bit 15, reg_earc_cps_nonpcm2pcm_clr_en unsigned, default = 0, auto clear compress mode when nonpcm2pcm
+//Bit 14, reg_earc_auto unsigned, default = 0, auto change earc/arc
+//Bit 13, reg_earcin_papb_lr unsigned, default = 0, user l or r channle status to check papb
+//Bit 12, reg_earcin_check_papb unsigned, default = 0, 0:data valid after 1 block;1: in 1st block if exit papb ,data valid after papb
+//Bit 11, reg_earcin_start_papb unsigned, default = 0, start write toddr 1:from papb check,0 from preamble Z,valid when reg_earcin_check_papb set
+//Bit 10, reg_formatchange_auto_rst unsigned, default = 0, auto reset will detect format change
+//Bit 9, reg_earcin_cpsb_pcpd_sel unsigned, default = 0, compress B pcpd select : 1:next 4th subframe data 0:next sub frame data
+//Bit 8:4, reg_earc_papb_msb unsigned, default = 0, papb msb position in data
+//Bit 3, reg_earcin_spdif_force unsigned, default = 0, when in arc mode,spdif on force enable
+//Bit 2, reg_earcin_spdif_force_set unsigned, default = 0, force value
+//Bit 1, reg_earcin_mode_force unsigned, default = 0, earc mode force enable
+//Bit 0, reg_earcin_mode_force_set unsigned, default = 0, force value
+#define EARCRX_SPDIFIN_CTRL3 ((0x000f << 2) + 0xfe333c00)
+//Bit 31:16, reg_earc_pa_value unsigned, default = 0, earc mode pa value
+//Bit 15:0, reg_earc_pb_value unsigned, default = 0, earc mode pb value
+#define EARCRX_SPDIFIN_STAT0 ((0x0010 << 2) + 0xfe333c00)
+//Bit 31:0, reg_spdifin_stat0 unsigned, default = 0
+#define EARCRX_SPDIFIN_STAT1 ((0x0011 << 2) + 0xfe333c00)
+//Bit 31:0, reg_spdifin_stat1 unsigned, default = 0
+#define EARCRX_SPDIFIN_STAT2 ((0x0012 << 2) + 0xfe333c00)
+//Bit 31:0, reg_spdifin_stat2 unsigned, default = 0
+#define EARCRX_DMAC_UBIT_CTRL0 ((0x0013 << 2) + 0xfe333c00)
+//Bit 31, reg_work_enable unsigned, default = 0, dmac user bit decode enable
+//Bit 30:24, reg_iu_sync unsigned, default = 0, iu sync value
+//Bit 23:16, reg_fifo_thd unsigned, default = 0, generate irq when fifo level pass some threthold
+//Bit 15, reg_max_dist_en unsigned, default = 0, max distance bewteen IUs to set lost
+//Bit 14, reg_iu_sync_en unsigned, default = 0, iu sync code enable 0 : all iu to fifo 1 only sync iu packet to fifo
+//Bit 13:12, reg_user_lr unsigned, default = 0, 00 off 01 use l channel userbit 10 use r channel userbit 11 user lr channel userbit
+//Bit 11:8, reg_max_dist unsigned, default = 0, max distance bewteen IUs value
+//Bit 7, reg_fifo_thd_en unsigned, default = 0, fifo_thd irq enable
+//Bit 6, reg_fifo_lost_init_en unsigned, default = 0, when lost,initial fifo
+//Bit 5, reg_fifo_init unsigned, default = 0, fifo initial
+//Bit 4:0, reg_data_bit unsigned, default = 0, user bit position in data
+#define EARCRX_IU_RDATA ((0x0014 << 2) + 0xfe333c00)
+//Bit 31:8, reserved
+//Bit 7:0, i_iu_rdata unsigned, default = 0, iu data,read only
+#define EARCRX_DMAC_UBIT_STAT0 ((0x0015 << 2) + 0xfe333c00)
+//Bit 31:0, reg_dmac_ubit_stat0 unsigned, default = 0
+#define EARCRX_ERR_CORRECT_CTRL0 ((0x0016 << 2) + 0xfe333c00)
+//Bit 31, reg_work_enable unsigned, default = 0, err correct work enable
+//Bit 30, reserved
+//Bit 29, reg_rst_afifo_out_n unsigned, default = 0, reset afifo out side
+//Bit 28, reg_rst_afifo_in_n unsigned, default = 0, reset afifo in side
+//Bit 27, reg_lr_check unsigned, default = 0, enable lr_check
+//Bit 26:7, reserved
+//Bit 6, reg_bchout_data_ml unsigned, default = 0, bch output 16bit data msb is 27 or 19
+//Bit 5, reg_bchout_data_rsv unsigned, default = 0, bch output data revers
+//Bit 4, reg_bchin_ecc_ml unsigned, default = 0, bch input ecc msb/lsb
+//Bit 3, reg_bchin_ecc_rsv unsigned, default = 0, bch input ecc revers
+//Bit 2, reg_bchin_data_rsv unsigned, default = 0, bch input data revers
+//Bit 1, reg_force_set unsigned, default = 0, 0 off 1 compress audio mode
+//Bit 0, reg_force_en unsigned, default = 0, force work mode enable
+#define EARCRX_ERR_CORRECT_STAT0 ((0x0017 << 2) + 0xfe333c00)
+//Bit 31:0, reg_err_correct_stat0 unsigned, default = 0
+#define EARCRX_ANA_RST_CTRL0 ((0x0018 << 2) + 0xfe333c00)
+//Bit 31, reg_work_enable unsigned, default = 0, analog reset check work enable
+//Bit 30, reg_ana_rst_sf_en unsigned, default = 0, analog reset from register enable
+//Bit 29, reg_ana_rst_sf unsigned, default = 0, soft reset value
+//Bit 28, reserved
+//Bit 27:23, reg_new_format_pos_num unsigned, default = 0, when new format data in, hold reset after N posedge
+//Bit 22:20, reg_dmacrx_div2_thd_tick_sel unsigned, default = 0, earcrx_div2 hold thresthold tick select
+//Bit 19:0, reg_earcrx_div2_thd unsigned, default = 0, earcrx_div2 hold thresthold
+#define EARCRX_ANA_RST_CTRL1 ((0x0019 << 2) + 0xfe333c00)
+//Bit 31, reg_dmacrx_data_filt_en unsigned, default = 0, filter enable
+//Bit 30:28, reg_dmacrx_data_filter_sel unsigned, default = 0, filter select
+//Bit 27:25, reg_dmacrx_data_tick_sel unsigned, default = 0, filter tick sel
+//Bit 24:16, reg_dmacrx_data_time unsigned, default = 0, filter tick time
+//Bit 15, reg_dmacrx_sqout_filt_en unsigned, default = 0, filter enable
+//Bit 14:12, reg_dmacrx_sqout_filter_sel unsigned, default = 0, filter select
+//Bit 11:9, reg_dmacrx_sqout_tick_sel unsigned, default = 0, filter tick sel
+//Bit 8:0, reg_dmacrx_sqout_time unsigned, default = 0, filter tick time
+#define EARCRX_SPDIFIN_CTRL4 ((0x0020 << 2) + 0xfe333c00)
+//Bit 31, reserved
+//Bit 30, reg_add_ch_r unsigned, default = 0, reg_add_ch_r
+//Bit 29, reg_bc_val0_en unsigned, default = 0, reg_bc_val0_en
+//Bit 28:20, reg_stable_mask unsigned, default = 0, reg_stable_mask
+//Bit 19:16, reg_stable_zcnt unsigned, default = 0, reg_stable_zcnt
+//Bit 15:0 , reserved
+#define EARCRX_SPDIFIN_CTRL5 ((0x0021 << 2) + 0xfe333c00)
+//Bit 31, reg_st_timeout_sts_clr unsigned, default = 0, reg_st_timeout_sts_clr
+//Bit 30:28, reserved
+//Bit 27:16, reg_st_timeout_check_thd unsigned, default = 0, reg_st_timeout_check_thd
+//Bit 15, reserved
+//Bit 14:12, reg_st_timeout_check_tick_sel unsigned, default = 0, reg_st_timeout_check_tick_sel
+//Bit 11, reg_st_timeout_check_en unsigned, default = 0, reg_st_timeout_check_en
+//Bit 10:9, reserved
+//Bit 8:0, reg_stable_int_mask unsigned, default = 0, reg_stable_int_mask
+#define EARCRX_SPDIFIN_CTRL6 ((0x0022 << 2) + 0xfe333c00)
+//Bit 31:17, reserved
+//Bit 16, reg_check_time_en unsigned, default = 0, reg_check_time_en
+//Bit 15:0, reg_check_time_thd unsigned, default = 0, reg_check_time_thd
+#define EARCRX_DMAC_SYNC_CTRL1 ((0x0023 << 2) + 0xfe333c00)
+//Bit 31:19, reserved
+//Bit 18, reg_auto_neg_int_en unsigned, default = 0, reg_auto_neg_int_en
+//Bit 17, reg_auto_stable_clr unsigned, default = 0, reg_auto_stable_clr
+//Bit 16, reg_auto_stable_en unsigned, default = 0, reg_auto_stable_en
+//Bit 15:0, reg_auto_stable_thd unsigned, default = 0, reg_auto_stable_thd
+#define EARCRX_SPDIFIN_SAMPLE_CTRL6 ((0x0024 << 2) + 0xfe333c00)
+//Bit 31:18, reserved
+//Bit 17, reg_hold_tri_sample unsigned, default = 0, reg_hold_tri_sample
+//Bit 16, reg_sample_mode_filter_en unsigned, default = 0, reg_sample_mode_filter_en
+//Bit 15:8, reg_stable_cyc_min unsigned, default = 0, reg_stable_cyc_min
+//Bit 7:0, reg_stable_cyc_max unsigned, default = 0, reg_stable_cyc_max
+#define EARCRX_DMAC_SYNC_CTRL2 ((0x0025 << 2) + 0xfe333c00)
+//Bit 31, reg_unstable_t0_err_clr unsigned, default = 0, reg_unstable_t0_err_clr
+//Bit 30:20, reserved
+//Bit 19, reg_unstable_t0_check_en unsigned, default = 0, reg_unstable_t0_check_en
+//Bit 18:16, reg_unstable_t0_tick_sel unsigned, default = 0, reg_unstable_t0_tick_sel
+//Bit 15:0, reg_unstable_t0_thd unsigned, default = 0, reg_unstable_t0_thd
+#define EARCRX_DMAC_SYNC_CTRL3 ((0x0026 << 2) + 0xfe333c00)
+//Bit 31, reg_unstable_t1_err_clr unsigned, default = 0, reg_unstable_t1_err_clr
+//Bit 30:20, reserved
+//Bit 19, reg_unstable_t1_check_en unsigned, default = 0, reg_unstable_t1_check_en
+//Bit 18:16, reg_unstable_t1_tick_sel unsigned, default = 0, reg_unstable_t1_tick_sel
+//Bit 15:0, reg_unstable_t1_thd unsigned, default = 0, reg_unstable_t1_thd
+#define EARCRX_DMAC_SYNC_CTRL4 ((0x0027 << 2) + 0xfe333c00)
+//Bit 31, reg_unstable_t2_err_clr unsigned, default = 0, reg_unstable_t2_err_clr
+//Bit 30:20, reserved
+//Bit 19, reg_unstable_t2_check_en unsigned, default = 0, reg_unstable_t2_check_en
+//Bit 18:16, reg_unstable_t2_tick_sel unsigned, default = 0, reg_unstable_t2_tick_sel
+//Bit 15:0, reg_unstable_t2_thd unsigned, default = 0, reg_unstable_t2_thd
+#define EARCRX_DMAC_SYNC_STAT1 ((0x0028 << 2) + 0xfe333c00)
+//Bit 31:0, reg_dmac_sync_stat1 unsigned, default = 0
+#define EARCRX_DMAC_SYNC_STAT2 ((0x0029 << 2) + 0xfe333c00)
+//Bit 31:0, reg_dmac_sync_stat2 unsigned, default = 0
+#define EARCRX_DMAC_SYNC_STAT3 ((0x002a << 2) + 0xfe333c00)
+//Bit 31:0, reg_dmac_sync_stat3 unsigned, default = 0
+//
+// Closing file: earcrx_dmac.h
+//
+//========================================================================
+// AUDIO EARCRX_TOP - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe333e00
+// -----------------------------------------------
+//
+// Reading file: earcrx_top.h
+//
+#define EARCRX_TOP_CTRL0 ((0x0000 << 2) + 0xfe333e00)
+//Bit 31:10, reserved
+//Bit 9:8, reg_top_debug_sel unsigned, default = 0, top debug select
+//Bit 7, reg_spdif_rx_en_force unsigned, default = 0, force spdif_rx_en to reg_spdif_rx_en_force_value
+//Bit 6, reg_spdif_rx_en_force_value unsigned, default = 0, value
+//Bit 5, reg_spdif_rx_sqen_force unsigned, default = 0, force spdif_rx_sqen to reg_spdif_rx_sqe
+//Bit 4, reg_spdif_rx_sqen_force_value unsigned, default = 0, value
+//Bit 3, reg_dmacrx_en_force unsigned, default = 0, force dmacrx_en to reg_dmacrx_en_force_value
+//Bit 2, reg_dmacrx_en_force_value unsigned, default = 0, value
+//Bit 1, reg_dmacrx_sqen_force unsigned, default = 0, force dmacrx_sqen to reg_dmacrx_sqen_force_value
+//Bit 0, reg_dmacrx_sqen_force_value unsigned, default = 0, value
+#define EARCRX_DMAC_INT_MASK ((0x0001 << 2) + 0xfe333e00)
+//Bit 31:30, reserved
+//Bit 29:0, reg_dmac_int_mask unsigned, default = 0, dmac int mask
+#define EARCRX_DMAC_INT_PENDING ((0x0002 << 2) + 0xfe333e00)
+//Bit 31:30, reserved
+//Bit 29:0, reg_dmac_int_mask unsigned, default = 0, dmac int pending,read only
+#define EARCRX_CMDC_INT_MASK ((0x0003 << 2) + 0xfe333e00)
+//Bit 31:16, reserved
+//Bit 15:0, reg_cmdc_int_mask unsigned, default = 0, cmdc int mask
+#define EARCRX_CMDC_INT_PENDING ((0x0004 << 2) + 0xfe333e00)
+//Bit 31:18, reserved
+//Bit 17:0, reg_cmdc_int_mask unsigned, default = 0, cmdc int pending,read only
+#define EARCRX_ANA_CTRL0 ((0x0005 << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_ANA_CTRL1 ((0x0006 << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_ANA_STAT0 ((0x0007 << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_PLL_CTRL0 ((0x0008 << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_PLL_CTRL1 ((0x0009 << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_PLL_CTRL2 ((0x000a << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_PLL_CTRL3 ((0x000b << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+#define EARCRX_PLL_STAT0 ((0x000c << 2) + 0xfe333e00)
+//Bit 31:0, reg_earcrx_ana_ctrl0 unsigned, default = 0
+//
+// Closing file: earcrx_top.h
+//
+//========================================================================
+// AUDIO RESAMPLEB - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe334000
+// -----------------------------------------------
+//
+// Reading file: RESAMPLEB.h
+//
+#define AUDIO_RSAMPB_CTRL0 ((0x0000 << 2) + 0xfe334000)
+//Bit 31:3 reserved
+//Bit 2 reg_lock_rst //unsigned , default =0;
+//Bit 1 reg_rsamp_rst //unsigned , default =0;
+//Bit 0 reg_sw_rst //unsigned , default =0;
+#define AUDIO_RSAMPB_CTRL1 ((0x0001 << 2) + 0xfe334000)
+//Bit 31:27 reg_in_lsb //unsigned , default =0;
+//Bit 26 reg_watchdog_en //unsigned , default =0;
+//Bit 25 reg_rsamp_rst_sel //unsigned , default =0;
+//Bit 24 reg_module_bypas //unsigned , default =0;
+//Bit 23:18 reg_gclk_ctrl //unsigned , default =0;
+//Bit 17:13 reg_in_msb //unsigned , default =23;
+//Bit 12 reg_output_en //unsigned , default =0;
+//Bit 11 reg_rsamp_en //unsigned , default =0;
+//Bit 10 reg_filt_en //unsigned , default =0;
+//Bit 9 reg_post_en //unsigned , default =0;
+//Bit 8 reg_inp_mux_mode //unsigned , default =0;
+//Bit 7:5 reserved //unsigned , default =2;
+//Bit 4:0 reg_inp_mux //unsigned , default =0;
+#define AUDIO_RSAMPB_CTRL2 ((0x0002 << 2) + 0xfe334000)
+//Bit 31:30 reserved //unsigned , default =0;
+//Bit 29:24 reg_chx_size //unsigned , default =2;
+//Bit 23:18 reserved //unsigned , default =0;
+//Bit 17:16 reg_scl_step //unsigned , default =0; 0: 1/1 1: 1/2 2: 1/4
+//Bit 15:8 reg_filt_tap //unsigned , default =63;
+//Bit 7:0 reg_intp_tap //unsigned , default =63;
+#define AUDIO_RSAMPB_PHSINIT ((0x0003 << 2) + 0xfe334000)
+//Bit 31:28 reserved //unsigned , default = 0;
+//Bit 27:0 reg_init_phs //unsigned , default = 0;
+#define AUDIO_RSAMPB_PHSSTEP ((0x0004 << 2) + 0xfe334000)
+//Bit 31 reserved //unsigned , default = 0;
+//Bit 30:0 reg_rsamp_step //unsigned , default = 134217728;//'h800_0000
+#define AUDIO_RSAMPB_SHIFT ((0x0005 << 2) + 0xfe334000)
+//Bit 31:24 reg_rsft_iir //unsigned , default = 23;
+//Bit 23:16 reg_rsft_blnd //unsigned , default = 21;
+//Bit 15:8 reg_rsft_sinc //unsigned , default = 31;
+//Bit 7:0 reg_rsft_aa //unsigned , default = 31;
+#define AUDIO_RSAMPB_ADJ_CTRL0 ((0x0006 << 2) + 0xfe334000)
+//Bit 31:7 reserved //unsigned
+//Bit 6 reg_lock_vld_sel //unsigned , default = 0;
+//Bit 5 reg_loop_dif_clr_en //unsigned , default = 0;
+//Bit 4 reg_aout_force_en //unsigned , default = 0;
+//Bit 3 reserved //unsigned
+//Bit 2 reg_rsamp_adj_out_inv //unsigned , default = 0;
+//Bit 1 reg_rsamp_adj_force_en //unsigned , default = 0;
+//Bit 0 reg_rsamp_adj_en //unsigned , default = 0;
+#define AUDIO_RSAMPB_ADJ_CTRL1 ((0x0007 << 2) + 0xfe334000)
+//Bit 31:16 reg_rsamp_adj_odet_step //unsigned , default = 8;
+//Bit 15:0 reg_rsamp_adj_kmax //unsigned , default = 32768;
+#define AUDIO_RSAMPB_ADJ_SFT ((0x0008 << 2) + 0xfe334000)
+//Bit 31:30 reserved //unsigned , default = 0;
+//Bit 29 reg_rsamp_adj_dif_sel //unsigned , default = 0;
+//Bit 28:24 reg_rsamp_adj_ki //unsigned , default = 9;
+//Bit 23:21 reserved //unsigned , default = 0;
+//Bit 20:16 reg_rsamp_adj_kp //unsigned , default = 1;
+//Bit 15:13 reserved //unsigned , default = 0;
+//Bit 12:8 reg_rsamp_adj_ki_sft //unsigned , default = 6;
+//Bit 7:6 reserved //unsigned , default = 0;
+//Bit 5:0 reg_rsamp_adj_out_sft //unsigned , default = 12;
+#define AUDIO_RSAMPB_ADJ_IDET_LEN ((0x0009 << 2) + 0xfe334000)
+//Bit 31:0 reg_rsamp_adj_idet_len //unsigned , default = 10000;
+#define AUDIO_RSAMPB_ADJ_FORCE ((0x000a << 2) + 0xfe334000)
+//Bit 31:0 reg_rsamp_adj_force_err //signed , default = 8;
+#define AUDIO_RSAMPB_ADJ_KI_FORCE ((0x000b << 2) + 0xfe334000)
+//Bit 31:0 reg_rsamp_adj_ki_force //signed , default = 0;
+#define AUDIO_RSAMPB_WATCHDOG_THRD ((0x000c << 2) + 0xfe334000)
+//Bit 31:0 reg_watchdog_thrd //signed , default = 32'h1000;
+#define AUDIO_RSAMPB_DBG_INFO ((0x000d << 2) + 0xfe334000)
+//Bit 31:16 reg_aout_force_hi //unsigned , default = 0;
+//Bit 15:7 reserved //unsigned , default = 0;
+//Bit 6 reg_rsamp_dbgcnt_clr //unsigned , default = 0;
+//Bit 5 reg_rsamp_dbgcnt_vldsel //unsigned , default = 0;
+//Bit 4 reg_rsamp_dbgcnt_en //unsigned , default = 0;
+//Bit 3 reserved //unsigned , default = 0;
+//Bit 2:0 reg_watchdog_rstsel //unsigned , default = 4;
+#define AUDIO_RSAMPB_AOUT_FORCE ((0x000e << 2) + 0xfe334000)
+//Bit 31:0 reg_aout_force_lo //unsigned , default = 0;
+#define AUDIO_RSAMPB_IRQ_CTRL ((0x000f << 2) + 0xfe334000)
+//Bit 31:16 reg_irq_thrd //unsigned , default = 0;
+//Bit 15:12 reserved //unsigned , default = 0;
+//Bit 11:8 reg_irq_sel //unsigned , default = 0;
+//Bit 7:4 reg_irq_clr //unsigned , default = 0;
+//Bit 3:0 reg_irq_en //unsigned , default = 0;
+#define AUDIO_RSAMPB_RO_STATUS ((0x0010 << 2) + 0xfe334000)
+//Bit 31:0 ro_rsamp_stat //{din_chx_chk_err,is_idle_st,rsamp_fifo_over_cnt[7:0]}
+#define AUDIO_RSAMPB_RO_ADJ_FREQ ((0x0011 << 2) + 0xfe334000)
+//Bit 31:0 ro_rsamp_adj_freq
+#define AUDIO_RSAMPB_RO_ADJ_DIFF_BAK ((0x0012 << 2) + 0xfe334000)
+//Bit 31:0 ro_det_diff_bak
+#define AUDIO_RSAMPB_RO_ADJ_DIFF_DLT ((0x0013 << 2) + 0xfe334000)
+//Bit 31:0 ro_det_diff_dlt
+#define AUDIO_RSAMPB_RO_ADJ_PHS_ERR ((0x0014 << 2) + 0xfe334000)
+//Bit 31:0 ro_det_phase_err
+#define AUDIO_RSAMPB_RO_ADJ_KI_OUT ((0x0015 << 2) + 0xfe334000)
+//Bit 31:0 ro_rsamp_ki_out
+#define AUDIO_RSAMPB_RO_IN_CNT ((0x0016 << 2) + 0xfe334000)
+//Bit 31:0 ro_rsamp_in_cnt
+#define AUDIO_RSAMPB_RO_OUT_CNT ((0x0017 << 2) + 0xfe334000)
+//Bit 31:0 ro_rsamp_out_cnt
+#define AUDIO_RSAMPB_RO_ADJ_PHS_ERR_VAR ((0x0018 << 2) + 0xfe334000)
+//Bit 31:0 ro_det_phase_err_var
+#define AUDIO_RSAMPB_POST_COEF0 ((0x0020 << 2) + 0xfe334000)
+//Bit 31:0 reg_post_coef0 //signed , default = 0;
+#define AUDIO_RSAMPB_POST_COEF1 ((0x0021 << 2) + 0xfe334000)
+//Bit 31:0 reg_post_coef1 //signed , default = 0;
+#define AUDIO_RSAMPB_POST_COEF2 ((0x0022 << 2) + 0xfe334000)
+//Bit 31:0 reg_post_coef2 //signed , default = 0;
+#define AUDIO_RSAMPB_POST_COEF3 ((0x0023 << 2) + 0xfe334000)
+//Bit 31:0 reg_post_coef3 //signed , default = 0;
+#define AUDIO_RSAMPB_POST_COEF4 ((0x0024 << 2) + 0xfe334000)
+//Bit 31:0 reg_post_coef4 //signed , default = 0;
+#define AUDIO_RSAMPB_AA_COEF_ADDR ((0x0030 << 2) + 0xfe334000)
+//Bit 31:0 reg_aa_coef_addr //unsigned, default = 0;
+#define AUDIO_RSAMPB_AA_COEF_DATA ((0x0031 << 2) + 0xfe334000)
+//Bit 31:0 reg_aa_coef_data //signed , default = 0;
+#define AUDIO_RSAMPB_SINC_COEF_ADDR ((0x0040 << 2) + 0xfe334000)
+//Bit 31:0 reg_sinc_coef_addr //unsigned, default = 0;
+#define AUDIO_RSAMPB_SINC_COEF_DATA ((0x0041 << 2) + 0xfe334000)
+//Bit 31:0 reg_sinc_coef_data //signed , default = 0;
+//
+// Closing file: RESAMPLEB.h
+//
+//
+// Closing file: REG_LIST_AUDIO_RTL.h
+//
+//
+// Reading file: REG_LIST_DSP_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//========================================================================
+// DSPA - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe340000
+// -----------------------------------------------
+#define DSP_CFG0 ((0x0000 << 2) + 0xfe340000)
+#define DSP_CFG1 ((0x0001 << 2) + 0xfe340000)
+#define DSP_CFG2 ((0x0002 << 2) + 0xfe340000)
+#define DSP_IMPWIRE ((0x0003 << 2) + 0xfe340000)
+#define DSP_RESET_VEC ((0x0004 << 2) + 0xfe340000)
+#define DSP_SEC_CFG0 ((0x0006 << 2) + 0xfe340000)
+#define DSP_SEC_CFG1 ((0x0007 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL0 ((0x0010 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL1 ((0x0011 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL2 ((0x0012 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL3 ((0x0013 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL4 ((0x0014 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL5 ((0x0015 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL6 ((0x0016 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL7 ((0x0017 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL8 ((0x0018 << 2) + 0xfe340000)
+#define DSP_IRQ_CTRL9 ((0x0019 << 2) + 0xfe340000)
+#define DSP_IRQ_STS ((0x001f << 2) + 0xfe340000)
+#define DSP_REMAP0 ((0x0020 << 2) + 0xfe340000)
+#define DSP_REMAP1 ((0x0021 << 2) + 0xfe340000)
+#define DSP_REMAP2 ((0x0022 << 2) + 0xfe340000)
+#define DSP_STS0 ((0x0040 << 2) + 0xfe340000)
+#define DSP_STS1 ((0x0041 << 2) + 0xfe340000)
+#define DSP_STS2 ((0x0042 << 2) + 0xfe340000)
+#define DSP_STS3 ((0x0043 << 2) + 0xfe340000)
+#define DSP_STS4 ((0x0044 << 2) + 0xfe340000)
+#define DSP_STS5 ((0x0045 << 2) + 0xfe340000)
+#define DSP_QIF_CTRL ((0x0080 << 2) + 0xfe340000)
+#define DSP_QIF_STS ((0x0081 << 2) + 0xfe340000)
+#define DSP_WRFIFO_TOCPUA ((0x0082 << 2) + 0xfe340000)
+#define DSP_WRFIFO_TOCPUB ((0x0083 << 2) + 0xfe340000)
+#define DSP_WRFIFO_TODSP ((0x0084 << 2) + 0xfe340000)
+#define DSP_RDFIFO_FRCPUA ((0x0088 << 2) + 0xfe340000)
+#define DSP_RDFIFO_FRCPUB ((0x0089 << 2) + 0xfe340000)
+#define DSP_RDFIFO_FRDSP ((0x008a << 2) + 0xfe340000)
+#define DSP_PM_CTRL ((0x0090 << 2) + 0xfe340000)
+#define DSP_PDEBUGDATA_STS ((0x0091 << 2) + 0xfe340000)
+#define DSP_PDEBUGINST_STS ((0x0092 << 2) + 0xfe340000)
+#define DSP_PDEBUGLS0STAT_STS ((0x0093 << 2) + 0xfe340000)
+#define DSP_PDEBUGLS1STAT_STS ((0x0094 << 2) + 0xfe340000)
+#define DSP_PDEBUGOUTPIF_STS ((0x0095 << 2) + 0xfe340000)
+#define DSP_PDEBUGPC_STS ((0x0096 << 2) + 0xfe340000)
+#define DSP_PDEBUGPREFETCHL1FILL_STS ((0x0097 << 2) + 0xfe340000)
+#define DSP_PDEBUGPREFETCHLOOKUP_STS ((0x0098 << 2) + 0xfe340000)
+#define DSP_PDEBUGSTATUS_STS ((0x0099 << 2) + 0xfe340000)
+//========================================================================
+// DSPB - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe350000
+// -----------------------------------------------
+#define DSPB_CFG0 ((0x0000 << 2) + 0xfe350000)
+#define DSPB_CFG1 ((0x0001 << 2) + 0xfe350000)
+#define DSPB_CFG2 ((0x0002 << 2) + 0xfe350000)
+#define DSPB_IMPWIRE ((0x0003 << 2) + 0xfe350000)
+#define DSPB_RESET_VEC ((0x0004 << 2) + 0xfe350000)
+#define DSPB_SEC_CFG0 ((0x0006 << 2) + 0xfe350000)
+#define DSPB_SEC_CFG1 ((0x0007 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL0 ((0x0010 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL1 ((0x0011 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL2 ((0x0012 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL3 ((0x0013 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL4 ((0x0014 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL5 ((0x0015 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL6 ((0x0016 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL7 ((0x0017 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL8 ((0x0018 << 2) + 0xfe350000)
+#define DSPB_IRQ_CTRL9 ((0x0019 << 2) + 0xfe350000)
+#define DSPB_IRQ_STS ((0x001f << 2) + 0xfe350000)
+#define DSPB_REMAP0 ((0x0020 << 2) + 0xfe350000)
+#define DSPB_REMAP1 ((0x0021 << 2) + 0xfe350000)
+#define DSPB_REMAP2 ((0x0022 << 2) + 0xfe350000)
+#define DSPB_STS0 ((0x0040 << 2) + 0xfe350000)
+#define DSPB_STS1 ((0x0041 << 2) + 0xfe350000)
+#define DSPB_STS2 ((0x0042 << 2) + 0xfe350000)
+#define DSPB_STS3 ((0x0043 << 2) + 0xfe350000)
+#define DSPB_STS4 ((0x0044 << 2) + 0xfe350000)
+#define DSPB_STS5 ((0x0045 << 2) + 0xfe350000)
+#define DSPB_QIF_CTRL ((0x0080 << 2) + 0xfe350000)
+#define DSPB_QIF_STS ((0x0081 << 2) + 0xfe350000)
+#define DSPB_WRFIFO_TOCPUA ((0x0082 << 2) + 0xfe350000)
+#define DSPB_WRFIFO_TOCPUB ((0x0083 << 2) + 0xfe350000)
+#define DSPB_WRFIFO_TODSP ((0x0084 << 2) + 0xfe350000)
+#define DSPB_RDFIFO_FRCPUA ((0x0088 << 2) + 0xfe350000)
+#define DSPB_RDFIFO_FRCPUB ((0x0089 << 2) + 0xfe350000)
+#define DSPB_RDFIFO_FRDSP ((0x008a << 2) + 0xfe350000)
+#define DSPB_PM_CTRL ((0x0090 << 2) + 0xfe350000)
+#define DSPB_PDEBUGDATA_STS ((0x0091 << 2) + 0xfe350000)
+#define DSPB_PDEBUGINST_STS ((0x0092 << 2) + 0xfe350000)
+#define DSPB_PDEBUGLS0STAT_STS ((0x0093 << 2) + 0xfe350000)
+#define DSPB_PDEBUGLS1STAT_STS ((0x0094 << 2) + 0xfe350000)
+#define DSPB_PDEBUGOUTPIF_STS ((0x0095 << 2) + 0xfe350000)
+#define DSPB_PDEBUGPC_STS ((0x0096 << 2) + 0xfe350000)
+#define DSPB_PDEBUGPREFETCHL1FILL_STS ((0x0097 << 2) + 0xfe350000)
+#define DSPB_PDEBUGPREFETCHLOOKUP_STS ((0x0098 << 2) + 0xfe350000)
+#define DSPB_PDEBUGSTATUS_STS ((0x0099 << 2) + 0xfe350000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: REG_LIST_DSP_RTL.h
+//
+//
+// Reading file: REG_LIST_SECURITY_RTL.h
+//
+//
+//***************************************************************************
+// Title: REG_LIST_SECURITY_RTL.h
+//
+// Author: shan.luan
+//
+// Created: 23:09:44 28/02/2020
+//
+// Description:
+//
+// Note:
+//
+// History:
+//
+//***************************************************************************
+//========================================================================
+// TS_DEMUX_REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe444000
+// -----------------------------------------------
+#define RCH_READY_CHANNEL_0 ((0x0000 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_1 ((0x0008 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_2 ((0x0010 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_3 ((0x0018 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_4 ((0x0020 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_5 ((0x0028 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_6 ((0x0030 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_7 ((0x0038 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_8 ((0x0040 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_9 ((0x0048 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_10 ((0x0050 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_11 ((0x0058 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_12 ((0x0060 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_13 ((0x0068 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_14 ((0x0070 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_15 ((0x0078 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_16 ((0x0080 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_17 ((0x0088 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_18 ((0x0090 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_19 ((0x0098 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_20 ((0x00a0 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_21 ((0x00a8 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_22 ((0x00b0 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_23 ((0x00b8 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_24 ((0x00c0 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_25 ((0x00c8 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_26 ((0x00d0 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_27 ((0x00d8 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_28 ((0x00e0 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_29 ((0x00e8 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_30 ((0x00f0 << 2) + 0xfe444000)
+#define RCH_READY_CHANNEL_31 ((0x00f8 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_0 ((0x0001 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_1 ((0x0009 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_2 ((0x0011 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_3 ((0x0019 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_4 ((0x0021 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_5 ((0x0029 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_6 ((0x0031 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_7 ((0x0039 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_8 ((0x0041 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_9 ((0x0049 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_10 ((0x0051 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_11 ((0x0059 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_12 ((0x0061 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_13 ((0x0069 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_14 ((0x0071 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_15 ((0x0079 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_16 ((0x0081 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_17 ((0x0089 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_18 ((0x0091 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_19 ((0x0099 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_20 ((0x00a1 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_21 ((0x00a9 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_22 ((0x00b1 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_23 ((0x00b9 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_24 ((0x00c1 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_25 ((0x00c9 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_26 ((0x00d1 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_27 ((0x00d9 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_28 ((0x00e1 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_29 ((0x00e9 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_30 ((0x00f1 << 2) + 0xfe444000)
+#define RCH_STATUS_CHANNEL_31 ((0x00f9 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_0 ((0x0002 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_1 ((0x000a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_2 ((0x0012 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_3 ((0x001a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_4 ((0x0022 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_5 ((0x002a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_6 ((0x0032 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_7 ((0x003a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_8 ((0x0042 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_9 ((0x004a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_10 ((0x0052 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_11 ((0x005a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_12 ((0x0062 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_13 ((0x006a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_14 ((0x0072 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_15 ((0x007a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_16 ((0x0082 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_17 ((0x008a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_18 ((0x0092 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_19 ((0x009a << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_20 ((0x00a2 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_21 ((0x00aa << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_22 ((0x00b2 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_23 ((0x00ba << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_24 ((0x00c2 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_25 ((0x00ca << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_26 ((0x00d2 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_27 ((0x00da << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_28 ((0x00e2 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_29 ((0x00ea << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_30 ((0x00f2 << 2) + 0xfe444000)
+#define RCH_CFG_CHANNEL_31 ((0x00fa << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_0 ((0x0003 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_1 ((0x000b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_2 ((0x0013 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_3 ((0x001b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_4 ((0x0023 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_5 ((0x002b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_6 ((0x0033 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_7 ((0x003b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_8 ((0x0043 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_9 ((0x004b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_10 ((0x0053 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_11 ((0x005b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_12 ((0x0063 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_13 ((0x006b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_14 ((0x0073 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_15 ((0x007b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_16 ((0x0083 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_17 ((0x008b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_18 ((0x0093 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_19 ((0x009b << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_20 ((0x00a3 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_21 ((0x00ab << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_22 ((0x00b3 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_23 ((0x00bb << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_24 ((0x00c3 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_25 ((0x00cb << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_26 ((0x00d3 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_27 ((0x00db << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_28 ((0x00e3 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_29 ((0x00eb << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_30 ((0x00f3 << 2) + 0xfe444000)
+#define RCH_ADDR_CHANNEL_31 ((0x00fb << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_0 ((0x0004 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_1 ((0x000c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_2 ((0x0014 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_3 ((0x001c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_4 ((0x0024 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_5 ((0x002c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_6 ((0x0034 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_7 ((0x003c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_8 ((0x0044 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_9 ((0x004c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_10 ((0x0054 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_11 ((0x005c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_12 ((0x0064 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_13 ((0x006c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_14 ((0x0074 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_15 ((0x007c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_16 ((0x0084 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_17 ((0x008c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_18 ((0x0094 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_19 ((0x009c << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_20 ((0x00a4 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_21 ((0x00ac << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_22 ((0x00b4 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_23 ((0x00bc << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_24 ((0x00c4 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_25 ((0x00cc << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_26 ((0x00d4 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_27 ((0x00dc << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_28 ((0x00e4 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_29 ((0x00ec << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_30 ((0x00f4 << 2) + 0xfe444000)
+#define RCH_LEN_CHANNEL_31 ((0x00fc << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_0 ((0x0005 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_1 ((0x000d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_2 ((0x0015 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_3 ((0x001d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_4 ((0x0025 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_5 ((0x002d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_6 ((0x0035 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_7 ((0x003d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_8 ((0x0045 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_9 ((0x004d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_10 ((0x0055 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_11 ((0x005d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_12 ((0x0065 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_13 ((0x006d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_14 ((0x0075 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_15 ((0x007d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_16 ((0x0085 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_17 ((0x008d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_18 ((0x0095 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_19 ((0x009d << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_20 ((0x00a5 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_21 ((0x00ad << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_22 ((0x00b5 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_23 ((0x00bd << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_24 ((0x00c5 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_25 ((0x00cd << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_26 ((0x00d5 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_27 ((0x00dd << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_28 ((0x00e5 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_29 ((0x00ed << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_30 ((0x00f5 << 2) + 0xfe444000)
+#define RCH_RD_LEN_CHANNEL_31 ((0x00fd << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_0 ((0x0006 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_1 ((0x000e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_2 ((0x0016 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_3 ((0x001e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_4 ((0x0026 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_5 ((0x002e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_6 ((0x0036 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_7 ((0x003e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_8 ((0x0046 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_9 ((0x004e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_10 ((0x0056 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_11 ((0x005e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_12 ((0x0066 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_13 ((0x006e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_14 ((0x0076 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_15 ((0x007e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_16 ((0x0086 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_17 ((0x008e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_18 ((0x0096 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_19 ((0x009e << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_20 ((0x00a6 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_21 ((0x00ae << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_22 ((0x00b6 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_23 ((0x00be << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_24 ((0x00c6 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_25 ((0x00ce << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_26 ((0x00d6 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_27 ((0x00de << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_28 ((0x00e6 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_29 ((0x00ee << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_30 ((0x00f6 << 2) + 0xfe444000)
+#define RCH_PTR_CHANNEL_31 ((0x00fe << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_0 ((0x0007 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_1 ((0x000f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_2 ((0x0017 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_3 ((0x001f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_4 ((0x0027 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_5 ((0x002f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_6 ((0x0037 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_7 ((0x003f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_8 ((0x0047 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_9 ((0x004f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_10 ((0x0057 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_11 ((0x005f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_12 ((0x0067 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_13 ((0x006f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_14 ((0x0077 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_15 ((0x007f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_16 ((0x0087 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_17 ((0x008f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_18 ((0x0097 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_19 ((0x009f << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_20 ((0x00a7 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_21 ((0x00af << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_22 ((0x00b7 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_23 ((0x00bf << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_24 ((0x00c7 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_25 ((0x00cf << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_26 ((0x00d7 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_27 ((0x00df << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_28 ((0x00e7 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_29 ((0x00ef << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_30 ((0x00f7 << 2) + 0xfe444000)
+#define RCH_PKT_SYNC_STATUS_CHANNEL_31 ((0x00ff << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_0 ((0x0400 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_1 ((0x0408 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_2 ((0x0410 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_3 ((0x0418 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_4 ((0x0420 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_5 ((0x0428 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_6 ((0x0430 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_7 ((0x0438 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_8 ((0x0440 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_9 ((0x0448 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_10 ((0x0450 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_11 ((0x0458 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_12 ((0x0460 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_13 ((0x0468 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_14 ((0x0470 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_15 ((0x0478 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_16 ((0x0480 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_17 ((0x0488 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_18 ((0x0490 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_19 ((0x0498 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_20 ((0x04a0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_21 ((0x04a8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_22 ((0x04b0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_23 ((0x04b8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_24 ((0x04c0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_25 ((0x04c8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_26 ((0x04d0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_27 ((0x04d8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_28 ((0x04e0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_29 ((0x04e8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_30 ((0x04f0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_31 ((0x04f8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_32 ((0x0500 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_33 ((0x0508 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_34 ((0x0510 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_35 ((0x0518 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_36 ((0x0520 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_37 ((0x0528 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_38 ((0x0530 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_39 ((0x0538 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_40 ((0x0540 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_41 ((0x0548 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_42 ((0x0550 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_43 ((0x0558 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_44 ((0x0560 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_45 ((0x0568 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_46 ((0x0570 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_47 ((0x0578 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_48 ((0x0580 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_49 ((0x0588 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_50 ((0x0590 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_51 ((0x0598 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_52 ((0x05a0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_53 ((0x05a8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_54 ((0x05b0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_55 ((0x05b8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_56 ((0x05c0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_57 ((0x05c8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_58 ((0x05d0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_59 ((0x05d8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_60 ((0x05e0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_61 ((0x05e8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_62 ((0x05f0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_63 ((0x05f8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_64 ((0x0600 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_65 ((0x0608 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_66 ((0x0610 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_67 ((0x0618 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_68 ((0x0620 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_69 ((0x0628 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_70 ((0x0630 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_71 ((0x0638 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_72 ((0x0640 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_73 ((0x0648 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_74 ((0x0650 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_75 ((0x0658 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_76 ((0x0660 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_77 ((0x0668 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_78 ((0x0670 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_79 ((0x0678 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_80 ((0x0680 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_81 ((0x0688 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_82 ((0x0690 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_83 ((0x0698 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_84 ((0x06a0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_85 ((0x06a8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_86 ((0x06b0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_87 ((0x06b8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_88 ((0x06c0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_89 ((0x06c8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_90 ((0x06d0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_91 ((0x06d8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_92 ((0x06e0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_93 ((0x06e8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_94 ((0x06f0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_95 ((0x06f8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_96 ((0x0700 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_97 ((0x0708 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_98 ((0x0710 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_99 ((0x0718 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_100 ((0x0720 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_101 ((0x0728 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_102 ((0x0730 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_103 ((0x0738 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_104 ((0x0740 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_105 ((0x0748 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_106 ((0x0750 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_107 ((0x0758 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_108 ((0x0760 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_109 ((0x0768 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_110 ((0x0770 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_111 ((0x0778 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_112 ((0x0780 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_113 ((0x0788 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_114 ((0x0790 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_115 ((0x0798 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_116 ((0x07a0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_117 ((0x07a8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_118 ((0x07b0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_119 ((0x07b8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_120 ((0x07c0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_121 ((0x07c8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_122 ((0x07d0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_123 ((0x07d8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_124 ((0x07e0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_125 ((0x07e8 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_126 ((0x07f0 << 2) + 0xfe444000)
+#define WCH_READY_CHANNEL_127 ((0x07f8 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_0 ((0x0401 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_1 ((0x0409 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_2 ((0x0411 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_3 ((0x0419 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_4 ((0x0421 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_5 ((0x0429 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_6 ((0x0431 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_7 ((0x0439 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_8 ((0x0441 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_9 ((0x0449 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_10 ((0x0451 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_11 ((0x0459 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_12 ((0x0461 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_13 ((0x0469 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_14 ((0x0471 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_15 ((0x0479 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_16 ((0x0481 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_17 ((0x0489 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_18 ((0x0491 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_19 ((0x0499 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_20 ((0x04a1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_21 ((0x04a9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_22 ((0x04b1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_23 ((0x04b9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_24 ((0x04c1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_25 ((0x04c9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_26 ((0x04d1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_27 ((0x04d9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_28 ((0x04e1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_29 ((0x04e9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_30 ((0x04f1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_31 ((0x04f9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_32 ((0x0501 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_33 ((0x0509 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_34 ((0x0511 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_35 ((0x0519 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_36 ((0x0521 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_37 ((0x0529 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_38 ((0x0531 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_39 ((0x0539 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_40 ((0x0541 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_41 ((0x0549 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_42 ((0x0551 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_43 ((0x0559 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_44 ((0x0561 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_45 ((0x0569 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_46 ((0x0571 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_47 ((0x0579 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_48 ((0x0581 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_49 ((0x0589 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_50 ((0x0591 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_51 ((0x0599 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_52 ((0x05a1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_53 ((0x05a9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_54 ((0x05b1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_55 ((0x05b9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_56 ((0x05c1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_57 ((0x05c9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_58 ((0x05d1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_59 ((0x05d9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_60 ((0x05e1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_61 ((0x05e9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_62 ((0x05f1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_63 ((0x05f9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_64 ((0x0601 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_65 ((0x0609 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_66 ((0x0611 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_67 ((0x0619 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_68 ((0x0621 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_69 ((0x0629 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_70 ((0x0631 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_71 ((0x0639 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_72 ((0x0641 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_73 ((0x0649 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_74 ((0x0651 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_75 ((0x0659 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_76 ((0x0661 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_77 ((0x0669 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_78 ((0x0671 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_79 ((0x0679 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_80 ((0x0681 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_81 ((0x0689 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_82 ((0x0691 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_83 ((0x0699 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_84 ((0x06a1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_85 ((0x06a9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_86 ((0x06b1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_87 ((0x06b9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_88 ((0x06c1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_89 ((0x06c9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_90 ((0x06d1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_91 ((0x06d9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_92 ((0x06e1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_93 ((0x06e9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_94 ((0x06f1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_95 ((0x06f9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_96 ((0x0701 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_97 ((0x0709 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_98 ((0x0711 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_99 ((0x0719 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_100 ((0x0721 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_101 ((0x0729 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_102 ((0x0731 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_103 ((0x0739 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_104 ((0x0741 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_105 ((0x0749 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_106 ((0x0751 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_107 ((0x0759 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_108 ((0x0761 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_109 ((0x0769 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_110 ((0x0771 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_111 ((0x0779 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_112 ((0x0781 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_113 ((0x0789 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_114 ((0x0791 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_115 ((0x0799 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_116 ((0x07a1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_117 ((0x07a9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_118 ((0x07b1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_119 ((0x07b9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_120 ((0x07c1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_121 ((0x07c9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_122 ((0x07d1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_123 ((0x07d9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_124 ((0x07e1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_125 ((0x07e9 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_126 ((0x07f1 << 2) + 0xfe444000)
+#define WCH_DEBUG_CHANNEL_127 ((0x07f9 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_0 ((0x0402 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_1 ((0x040a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_2 ((0x0412 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_3 ((0x041a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_4 ((0x0422 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_5 ((0x042a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_6 ((0x0432 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_7 ((0x043a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_8 ((0x0442 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_9 ((0x044a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_10 ((0x0452 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_11 ((0x045a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_12 ((0x0462 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_13 ((0x046a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_14 ((0x0472 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_15 ((0x047a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_16 ((0x0482 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_17 ((0x048a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_18 ((0x0492 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_19 ((0x049a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_20 ((0x04a2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_21 ((0x04aa << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_22 ((0x04b2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_23 ((0x04ba << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_24 ((0x04c2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_25 ((0x04ca << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_26 ((0x04d2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_27 ((0x04da << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_28 ((0x04e2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_29 ((0x04ea << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_30 ((0x04f2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_31 ((0x04fa << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_32 ((0x0502 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_33 ((0x050a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_34 ((0x0512 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_35 ((0x051a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_36 ((0x0522 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_37 ((0x052a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_38 ((0x0532 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_39 ((0x053a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_40 ((0x0542 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_41 ((0x054a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_42 ((0x0552 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_43 ((0x055a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_44 ((0x0562 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_45 ((0x056a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_46 ((0x0572 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_47 ((0x057a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_48 ((0x0582 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_49 ((0x058a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_50 ((0x0592 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_51 ((0x059a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_52 ((0x05a2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_53 ((0x05aa << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_54 ((0x05b2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_55 ((0x05ba << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_56 ((0x05c2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_57 ((0x05ca << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_58 ((0x05d2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_59 ((0x05da << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_60 ((0x05e2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_61 ((0x05ea << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_62 ((0x05f2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_63 ((0x05fa << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_64 ((0x0602 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_65 ((0x060a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_66 ((0x0612 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_67 ((0x061a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_68 ((0x0622 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_69 ((0x062a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_70 ((0x0632 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_71 ((0x063a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_72 ((0x0642 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_73 ((0x064a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_74 ((0x0652 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_75 ((0x065a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_76 ((0x0662 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_77 ((0x066a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_78 ((0x0672 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_79 ((0x067a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_80 ((0x0682 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_81 ((0x068a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_82 ((0x0692 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_83 ((0x069a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_84 ((0x06a2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_85 ((0x06aa << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_86 ((0x06b2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_87 ((0x06ba << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_88 ((0x06c2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_89 ((0x06ca << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_90 ((0x06d2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_91 ((0x06da << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_92 ((0x06e2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_93 ((0x06ea << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_94 ((0x06f2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_95 ((0x06fa << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_96 ((0x0702 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_97 ((0x070a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_98 ((0x0712 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_99 ((0x071a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_100 ((0x0722 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_101 ((0x072a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_102 ((0x0732 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_103 ((0x073a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_104 ((0x0742 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_105 ((0x074a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_106 ((0x0752 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_107 ((0x075a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_108 ((0x0762 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_109 ((0x076a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_110 ((0x0772 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_111 ((0x077a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_112 ((0x0782 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_113 ((0x078a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_114 ((0x0792 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_115 ((0x079a << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_116 ((0x07a2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_117 ((0x07aa << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_118 ((0x07b2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_119 ((0x07ba << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_120 ((0x07c2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_121 ((0x07ca << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_122 ((0x07d2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_123 ((0x07da << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_124 ((0x07e2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_125 ((0x07ea << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_126 ((0x07f2 << 2) + 0xfe444000)
+#define WCH_CFG_CHANNEL_127 ((0x07fa << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_0 ((0x0403 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_1 ((0x040b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_2 ((0x0413 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_3 ((0x041b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_4 ((0x0423 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_5 ((0x042b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_6 ((0x0433 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_7 ((0x043b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_8 ((0x0443 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_9 ((0x044b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_10 ((0x0453 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_11 ((0x045b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_12 ((0x0463 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_13 ((0x046b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_14 ((0x0473 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_15 ((0x047b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_16 ((0x0483 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_17 ((0x048b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_18 ((0x0493 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_19 ((0x049b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_20 ((0x04a3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_21 ((0x04ab << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_22 ((0x04b3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_23 ((0x04bb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_24 ((0x04c3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_25 ((0x04cb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_26 ((0x04d3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_27 ((0x04db << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_28 ((0x04e3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_29 ((0x04eb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_30 ((0x04f3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_31 ((0x04fb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_32 ((0x0503 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_33 ((0x050b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_34 ((0x0513 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_35 ((0x051b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_36 ((0x0523 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_37 ((0x052b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_38 ((0x0533 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_39 ((0x053b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_40 ((0x0543 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_41 ((0x054b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_42 ((0x0553 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_43 ((0x055b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_44 ((0x0563 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_45 ((0x056b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_46 ((0x0573 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_47 ((0x057b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_48 ((0x0583 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_49 ((0x058b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_50 ((0x0593 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_51 ((0x059b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_52 ((0x05a3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_53 ((0x05ab << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_54 ((0x05b3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_55 ((0x05bb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_56 ((0x05c3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_57 ((0x05cb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_58 ((0x05d3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_59 ((0x05db << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_60 ((0x05e3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_61 ((0x05eb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_62 ((0x05f3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_63 ((0x05fb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_64 ((0x0603 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_65 ((0x060b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_66 ((0x0613 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_67 ((0x061b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_68 ((0x0623 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_69 ((0x062b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_70 ((0x0633 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_71 ((0x063b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_72 ((0x0643 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_73 ((0x064b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_74 ((0x0653 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_75 ((0x065b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_76 ((0x0663 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_77 ((0x066b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_78 ((0x0673 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_79 ((0x067b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_80 ((0x0683 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_81 ((0x068b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_82 ((0x0693 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_83 ((0x069b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_84 ((0x06a3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_85 ((0x06ab << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_86 ((0x06b3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_87 ((0x06bb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_88 ((0x06c3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_89 ((0x06cb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_90 ((0x06d3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_91 ((0x06db << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_92 ((0x06e3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_93 ((0x06eb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_94 ((0x06f3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_95 ((0x06fb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_96 ((0x0703 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_97 ((0x070b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_98 ((0x0713 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_99 ((0x071b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_100 ((0x0723 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_101 ((0x072b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_102 ((0x0733 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_103 ((0x073b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_104 ((0x0743 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_105 ((0x074b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_106 ((0x0753 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_107 ((0x075b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_108 ((0x0763 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_109 ((0x076b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_110 ((0x0773 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_111 ((0x077b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_112 ((0x0783 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_113 ((0x078b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_114 ((0x0793 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_115 ((0x079b << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_116 ((0x07a3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_117 ((0x07ab << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_118 ((0x07b3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_119 ((0x07bb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_120 ((0x07c3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_121 ((0x07cb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_122 ((0x07d3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_123 ((0x07db << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_124 ((0x07e3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_125 ((0x07eb << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_126 ((0x07f3 << 2) + 0xfe444000)
+#define WCH_ADDR_CHANNEL_127 ((0x07fb << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_0 ((0x0404 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_1 ((0x040c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_2 ((0x0414 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_3 ((0x041c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_4 ((0x0424 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_5 ((0x042c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_6 ((0x0434 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_7 ((0x043c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_8 ((0x0444 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_9 ((0x044c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_10 ((0x0454 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_11 ((0x045c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_12 ((0x0464 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_13 ((0x046c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_14 ((0x0474 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_15 ((0x047c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_16 ((0x0484 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_17 ((0x048c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_18 ((0x0494 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_19 ((0x049c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_20 ((0x04a4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_21 ((0x04ac << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_22 ((0x04b4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_23 ((0x04bc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_24 ((0x04c4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_25 ((0x04cc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_26 ((0x04d4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_27 ((0x04dc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_28 ((0x04e4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_29 ((0x04ec << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_30 ((0x04f4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_31 ((0x04fc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_32 ((0x0504 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_33 ((0x050c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_34 ((0x0514 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_35 ((0x051c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_36 ((0x0524 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_37 ((0x052c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_38 ((0x0534 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_39 ((0x053c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_40 ((0x0544 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_41 ((0x054c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_42 ((0x0554 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_43 ((0x055c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_44 ((0x0564 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_45 ((0x056c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_46 ((0x0574 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_47 ((0x057c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_48 ((0x0584 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_49 ((0x058c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_50 ((0x0594 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_51 ((0x059c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_52 ((0x05a4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_53 ((0x05ac << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_54 ((0x05b4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_55 ((0x05bc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_56 ((0x05c4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_57 ((0x05cc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_58 ((0x05d4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_59 ((0x05dc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_60 ((0x05e4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_61 ((0x05ec << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_62 ((0x05f4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_63 ((0x05fc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_64 ((0x0604 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_65 ((0x060c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_66 ((0x0614 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_67 ((0x061c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_68 ((0x0624 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_69 ((0x062c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_70 ((0x0634 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_71 ((0x063c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_72 ((0x0644 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_73 ((0x064c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_74 ((0x0654 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_75 ((0x065c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_76 ((0x0664 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_77 ((0x066c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_78 ((0x0674 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_79 ((0x067c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_80 ((0x0684 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_81 ((0x068c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_82 ((0x0694 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_83 ((0x069c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_84 ((0x06a4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_85 ((0x06ac << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_86 ((0x06b4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_87 ((0x06bc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_88 ((0x06c4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_89 ((0x06cc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_90 ((0x06d4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_91 ((0x06dc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_92 ((0x06e4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_93 ((0x06ec << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_94 ((0x06f4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_95 ((0x06fc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_96 ((0x0704 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_97 ((0x070c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_98 ((0x0714 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_99 ((0x071c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_100 ((0x0724 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_101 ((0x072c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_102 ((0x0734 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_103 ((0x073c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_104 ((0x0744 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_105 ((0x074c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_106 ((0x0754 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_107 ((0x075c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_108 ((0x0764 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_109 ((0x076c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_110 ((0x0774 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_111 ((0x077c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_112 ((0x0784 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_113 ((0x078c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_114 ((0x0794 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_115 ((0x079c << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_116 ((0x07a4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_117 ((0x07ac << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_118 ((0x07b4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_119 ((0x07bc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_120 ((0x07c4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_121 ((0x07cc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_122 ((0x07d4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_123 ((0x07dc << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_124 ((0x07e4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_125 ((0x07ec << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_126 ((0x07f4 << 2) + 0xfe444000)
+#define WCH_LEN_CHANNEL_127 ((0x07fc << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_0 ((0x0405 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_1 ((0x040d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_2 ((0x0415 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_3 ((0x041d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_4 ((0x0425 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_5 ((0x042d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_6 ((0x0435 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_7 ((0x043d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_8 ((0x0445 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_9 ((0x044d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_10 ((0x0455 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_11 ((0x045d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_12 ((0x0465 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_13 ((0x046d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_14 ((0x0475 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_15 ((0x047d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_16 ((0x0485 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_17 ((0x048d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_18 ((0x0495 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_19 ((0x049d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_20 ((0x04a5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_21 ((0x04ad << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_22 ((0x04b5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_23 ((0x04bd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_24 ((0x04c5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_25 ((0x04cd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_26 ((0x04d5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_27 ((0x04dd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_28 ((0x04e5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_29 ((0x04ed << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_30 ((0x04f5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_31 ((0x04fd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_32 ((0x0505 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_33 ((0x050d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_34 ((0x0515 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_35 ((0x051d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_36 ((0x0525 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_37 ((0x052d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_38 ((0x0535 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_39 ((0x053d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_40 ((0x0545 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_41 ((0x054d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_42 ((0x0555 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_43 ((0x055d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_44 ((0x0565 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_45 ((0x056d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_46 ((0x0575 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_47 ((0x057d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_48 ((0x0585 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_49 ((0x058d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_50 ((0x0595 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_51 ((0x059d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_52 ((0x05a5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_53 ((0x05ad << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_54 ((0x05b5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_55 ((0x05bd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_56 ((0x05c5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_57 ((0x05cd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_58 ((0x05d5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_59 ((0x05dd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_60 ((0x05e5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_61 ((0x05ed << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_62 ((0x05f5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_63 ((0x05fd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_64 ((0x0605 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_65 ((0x060d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_66 ((0x0615 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_67 ((0x061d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_68 ((0x0625 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_69 ((0x062d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_70 ((0x0635 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_71 ((0x063d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_72 ((0x0645 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_73 ((0x064d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_74 ((0x0655 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_75 ((0x065d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_76 ((0x0665 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_77 ((0x066d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_78 ((0x0675 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_79 ((0x067d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_80 ((0x0685 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_81 ((0x068d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_82 ((0x0695 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_83 ((0x069d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_84 ((0x06a5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_85 ((0x06ad << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_86 ((0x06b5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_87 ((0x06bd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_88 ((0x06c5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_89 ((0x06cd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_90 ((0x06d5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_91 ((0x06dd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_92 ((0x06e5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_93 ((0x06ed << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_94 ((0x06f5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_95 ((0x06fd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_96 ((0x0705 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_97 ((0x070d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_98 ((0x0715 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_99 ((0x071d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_100 ((0x0725 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_101 ((0x072d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_102 ((0x0735 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_103 ((0x073d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_104 ((0x0745 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_105 ((0x074d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_106 ((0x0755 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_107 ((0x075d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_108 ((0x0765 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_109 ((0x076d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_110 ((0x0775 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_111 ((0x077d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_112 ((0x0785 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_113 ((0x078d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_114 ((0x0795 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_115 ((0x079d << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_116 ((0x07a5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_117 ((0x07ad << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_118 ((0x07b5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_119 ((0x07bd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_120 ((0x07c5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_121 ((0x07cd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_122 ((0x07d5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_123 ((0x07dd << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_124 ((0x07e5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_125 ((0x07ed << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_126 ((0x07f5 << 2) + 0xfe444000)
+#define WCH_WR_LEN_CHANNEL_127 ((0x07fd << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_0 ((0x0406 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_1 ((0x040e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_2 ((0x0416 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_3 ((0x041e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_4 ((0x0426 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_5 ((0x042e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_6 ((0x0436 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_7 ((0x043e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_8 ((0x0446 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_9 ((0x044e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_10 ((0x0456 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_11 ((0x045e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_12 ((0x0466 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_13 ((0x046e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_14 ((0x0476 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_15 ((0x047e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_16 ((0x0486 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_17 ((0x048e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_18 ((0x0496 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_19 ((0x049e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_20 ((0x04a6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_21 ((0x04ae << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_22 ((0x04b6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_23 ((0x04be << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_24 ((0x04c6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_25 ((0x04ce << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_26 ((0x04d6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_27 ((0x04de << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_28 ((0x04e6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_29 ((0x04ee << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_30 ((0x04f6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_31 ((0x04fe << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_32 ((0x0506 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_33 ((0x050e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_34 ((0x0516 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_35 ((0x051e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_36 ((0x0526 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_37 ((0x052e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_38 ((0x0536 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_39 ((0x053e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_40 ((0x0546 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_41 ((0x054e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_42 ((0x0556 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_43 ((0x055e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_44 ((0x0566 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_45 ((0x056e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_46 ((0x0576 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_47 ((0x057e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_48 ((0x0586 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_49 ((0x058e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_50 ((0x0596 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_51 ((0x059e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_52 ((0x05a6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_53 ((0x05ae << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_54 ((0x05b6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_55 ((0x05be << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_56 ((0x05c6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_57 ((0x05ce << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_58 ((0x05d6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_59 ((0x05de << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_60 ((0x05e6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_61 ((0x05ee << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_62 ((0x05f6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_63 ((0x05fe << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_64 ((0x0606 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_65 ((0x060e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_66 ((0x0616 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_67 ((0x061e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_68 ((0x0626 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_69 ((0x062e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_70 ((0x0636 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_71 ((0x063e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_72 ((0x0646 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_73 ((0x064e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_74 ((0x0656 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_75 ((0x065e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_76 ((0x0666 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_77 ((0x066e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_78 ((0x0676 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_79 ((0x067e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_80 ((0x0686 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_81 ((0x068e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_82 ((0x0696 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_83 ((0x069e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_84 ((0x06a6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_85 ((0x06ae << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_86 ((0x06b6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_87 ((0x06be << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_88 ((0x06c6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_89 ((0x06ce << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_90 ((0x06d6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_91 ((0x06de << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_92 ((0x06e6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_93 ((0x06ee << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_94 ((0x06f6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_95 ((0x06fe << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_96 ((0x0706 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_97 ((0x070e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_98 ((0x0716 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_99 ((0x071e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_100 ((0x0726 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_101 ((0x072e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_102 ((0x0736 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_103 ((0x073e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_104 ((0x0746 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_105 ((0x074e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_106 ((0x0756 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_107 ((0x075e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_108 ((0x0766 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_109 ((0x076e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_110 ((0x0776 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_111 ((0x077e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_112 ((0x0786 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_113 ((0x078e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_114 ((0x0796 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_115 ((0x079e << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_116 ((0x07a6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_117 ((0x07ae << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_118 ((0x07b6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_119 ((0x07be << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_120 ((0x07c6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_121 ((0x07ce << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_122 ((0x07d6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_123 ((0x07de << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_124 ((0x07e6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_125 ((0x07ee << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_126 ((0x07f6 << 2) + 0xfe444000)
+#define WCH_PTR_CHANNEL_127 ((0x07fe << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_0 ((0x0407 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_1 ((0x040f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_2 ((0x0417 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_3 ((0x041f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_4 ((0x0427 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_5 ((0x042f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_6 ((0x0437 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_7 ((0x043f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_8 ((0x0447 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_9 ((0x044f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_10 ((0x0457 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_11 ((0x045f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_12 ((0x0467 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_13 ((0x046f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_14 ((0x0477 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_15 ((0x047f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_16 ((0x0487 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_17 ((0x048f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_18 ((0x0497 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_19 ((0x049f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_20 ((0x04a7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_21 ((0x04af << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_22 ((0x04b7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_23 ((0x04bf << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_24 ((0x04c7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_25 ((0x04cf << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_26 ((0x04d7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_27 ((0x04df << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_28 ((0x04e7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_29 ((0x04ef << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_30 ((0x04f7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_31 ((0x04ff << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_32 ((0x0507 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_33 ((0x050f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_34 ((0x0517 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_35 ((0x051f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_36 ((0x0527 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_37 ((0x052f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_38 ((0x0537 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_39 ((0x053f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_40 ((0x0547 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_41 ((0x054f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_42 ((0x0557 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_43 ((0x055f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_44 ((0x0567 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_45 ((0x056f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_46 ((0x0577 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_47 ((0x057f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_48 ((0x0587 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_49 ((0x058f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_50 ((0x0597 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_51 ((0x059f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_52 ((0x05a7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_53 ((0x05af << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_54 ((0x05b7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_55 ((0x05bf << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_56 ((0x05c7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_57 ((0x05cf << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_58 ((0x05d7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_59 ((0x05df << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_60 ((0x05e7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_61 ((0x05ef << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_62 ((0x05f7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_63 ((0x05ff << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_64 ((0x0607 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_65 ((0x060f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_66 ((0x0617 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_67 ((0x061f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_68 ((0x0627 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_69 ((0x062f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_70 ((0x0637 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_71 ((0x063f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_72 ((0x0647 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_73 ((0x064f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_74 ((0x0657 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_75 ((0x065f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_76 ((0x0667 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_77 ((0x066f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_78 ((0x0677 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_79 ((0x067f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_80 ((0x0687 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_81 ((0x068f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_82 ((0x0697 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_83 ((0x069f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_84 ((0x06a7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_85 ((0x06af << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_86 ((0x06b7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_87 ((0x06bf << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_88 ((0x06c7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_89 ((0x06cf << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_90 ((0x06d7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_91 ((0x06df << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_92 ((0x06e7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_93 ((0x06ef << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_94 ((0x06f7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_95 ((0x06ff << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_96 ((0x0707 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_97 ((0x070f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_98 ((0x0717 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_99 ((0x071f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_100 ((0x0727 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_101 ((0x072f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_102 ((0x0737 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_103 ((0x073f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_104 ((0x0747 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_105 ((0x074f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_106 ((0x0757 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_107 ((0x075f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_108 ((0x0767 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_109 ((0x076f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_110 ((0x0777 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_111 ((0x077f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_112 ((0x0787 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_113 ((0x078f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_114 ((0x0797 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_115 ((0x079f << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_116 ((0x07a7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_117 ((0x07af << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_118 ((0x07b7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_119 ((0x07bf << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_120 ((0x07c7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_121 ((0x07cf << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_122 ((0x07d7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_123 ((0x07df << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_124 ((0x07e7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_125 ((0x07ef << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_126 ((0x07f7 << 2) + 0xfe444000)
+#define WCMD_CNT_CHANNEL_127 ((0x07ff << 2) + 0xfe444000)
+#define DMX_RDMA_INT_MASK ((0x0800 << 2) + 0xfe444000)
+#define DMX_WDMA_INT_MASK_0 ((0x0801 << 2) + 0xfe444000)
+#define DMX_WDMA_INT_MASK_1 ((0x0802 << 2) + 0xfe444000)
+#define DMX_WDMA_INT_MASK_2 ((0x0803 << 2) + 0xfe444000)
+#define DMX_WDMA_INT_MASK_3 ((0x0804 << 2) + 0xfe444000)
+#define DMX_CLEAN_W_BATCH_0 ((0x0805 << 2) + 0xfe444000)
+#define DMX_CLEAN_W_BATCH_1 ((0x0806 << 2) + 0xfe444000)
+#define DMX_CLEAN_W_BATCH_2 ((0x0807 << 2) + 0xfe444000)
+#define DMX_CLEAN_W_BATCH_3 ((0x0808 << 2) + 0xfe444000)
+#define DMX_CLEAN_RDMA ((0x0809 << 2) + 0xfe444000)
+#define DMX_CLEAN_WDMA_0 ((0x080a << 2) + 0xfe444000)
+#define DMX_CLEAN_WDMA_1 ((0x080b << 2) + 0xfe444000)
+#define DMX_CLEAN_WDMA_2 ((0x080c << 2) + 0xfe444000)
+#define DMX_CLEAN_WDMA_3 ((0x080d << 2) + 0xfe444000)
+#define DMX_RDMA_ACTIVE ((0x080e << 2) + 0xfe444000)
+#define DMX_WDMA_ACTIVE_0 ((0x080f << 2) + 0xfe444000)
+#define DMX_WDMA_ACTIVE_1 ((0x0810 << 2) + 0xfe444000)
+#define DMX_WDMA_ACTIVE_2 ((0x0811 << 2) + 0xfe444000)
+#define DMX_WDMA_ACTIVE_3 ((0x0812 << 2) + 0xfe444000)
+#define DMX_DMA_RDONE ((0x0813 << 2) + 0xfe444000)
+#define DMX_DMA_WDONE_0 ((0x0814 << 2) + 0xfe444000)
+#define DMX_DMA_WDONE_1 ((0x0815 << 2) + 0xfe444000)
+#define DMX_DMA_WDONE_2 ((0x0816 << 2) + 0xfe444000)
+#define DMX_DMA_WDONE_3 ((0x0817 << 2) + 0xfe444000)
+#define DMX_RDES_ERR ((0x0818 << 2) + 0xfe444000)
+#define DMX_RDES_LEN_ERR ((0x0819 << 2) + 0xfe444000)
+#define DMX_WDES_ERR_0 ((0x081a << 2) + 0xfe444000)
+#define DMX_WDES_ERR_1 ((0x081b << 2) + 0xfe444000)
+#define DMX_WDES_ERR_2 ((0x081c << 2) + 0xfe444000)
+#define DMX_WDES_ERR_3 ((0x081d << 2) + 0xfe444000)
+#define DMX_DMA_BATCH_END_0 ((0x081e << 2) + 0xfe444000)
+#define DMX_DMA_BATCH_END_1 ((0x081f << 2) + 0xfe444000)
+#define DMX_DMA_BATCH_END_2 ((0x0820 << 2) + 0xfe444000)
+#define DMX_DMA_BATCH_END_3 ((0x0821 << 2) + 0xfe444000)
+#define DMX_WDES_EOC_DONE_0 ((0x0822 << 2) + 0xfe444000)
+#define DMX_WDES_EOC_DONE_1 ((0x0823 << 2) + 0xfe444000)
+#define DMX_WDES_EOC_DONE_2 ((0x0824 << 2) + 0xfe444000)
+#define DMX_WDES_EOC_DONE_3 ((0x0825 << 2) + 0xfe444000)
+#define DMX_WCH_RESP_ERR0 ((0x0826 << 2) + 0xfe444000)
+#define DMX_WCH_RESP_ERR1 ((0x0827 << 2) + 0xfe444000)
+#define DMX_WCH_RESP_ERR2 ((0x0828 << 2) + 0xfe444000)
+#define DMX_WCH_RESP_ERR3 ((0x0829 << 2) + 0xfe444000)
+#define DMX_UPDT_PKT_SYNC ((0x0830 << 2) + 0xfe444000)
+#define DMX_RCHN_CFG ((0x0831 << 2) + 0xfe444000)
+#define DMX_WCHN_CFG ((0x0832 << 2) + 0xfe444000)
+#define DMX_MEM_PD_CRTL ((0x0833 << 2) + 0xfe444000)
+#define DMX_DMA_BUS_CFG ((0x0834 << 2) + 0xfe444000)
+#define DMX_DMA_GMW_CFG ((0x0835 << 2) + 0xfe444000)
+#define DMX_DMA_GMR_CFG ((0x0836 << 2) + 0xfe444000)
+//========================================================================
+// TS OUTPUT REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe442c00
+// -----------------------------------------------
+#define TS_OUTPUT_PID_RDY ((0x0000 << 2) + 0xfe442c00)
+#define TS_OUTPUT_TEE_LOCK ((0x0001 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PID_CFG ((0x0002 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PID_DAT ((0x0003 << 2) + 0xfe442c00)
+#define TS_OUTPUT_OUT_CFG ((0x0004 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_0 ((0x0010 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_1 ((0x0011 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_2 ((0x0012 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_3 ((0x0013 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_4 ((0x0014 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_5 ((0x0015 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_6 ((0x0016 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_7 ((0x0017 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_8 ((0x0018 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_9 ((0x0019 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_10 ((0x001a << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_11 ((0x001b << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_12 ((0x001c << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_13 ((0x001d << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_14 ((0x001e << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_TAB_ENTRY_15 ((0x001f << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_0_1 ((0x0020 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_2_3 ((0x0021 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_4_5 ((0x0022 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_6_7 ((0x0023 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_8_9 ((0x0024 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_10_11 ((0x0025 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_12_13 ((0x0026 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_14_15 ((0x0027 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_16_17 ((0x0028 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_18_19 ((0x0029 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_20_21 ((0x002a << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_22_23 ((0x002b << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_24_25 ((0x002c << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_26_27 ((0x002d << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_28_29 ((0x002e << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_30_31 ((0x002f << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_32_33 ((0x0030 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_34_35 ((0x0031 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_36_37 ((0x0032 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_38_39 ((0x0033 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_40_41 ((0x0034 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_42_43 ((0x0035 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_44_45 ((0x0036 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_46_47 ((0x0037 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_48_49 ((0x0038 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_50_51 ((0x0039 << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_52_53 ((0x003a << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_54_55 ((0x003b << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_56_57 ((0x003c << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_58_59 ((0x003d << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_60_61 ((0x003e << 2) + 0xfe442c00)
+#define TS_OUTPUT_SID_TAB_62_63 ((0x003f << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_0 ((0x0040 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_1 ((0x0041 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_2 ((0x0042 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_3 ((0x0043 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_4 ((0x0044 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_5 ((0x0045 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_6 ((0x0046 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_7 ((0x0047 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_8 ((0x0048 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_9 ((0x0049 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_10 ((0x004a << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_11 ((0x004b << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_12 ((0x004c << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_13 ((0x004d << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_14 ((0x004e << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_15 ((0x004f << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_16 ((0x0050 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_17 ((0x0051 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_18 ((0x0052 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_19 ((0x0053 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_20 ((0x0054 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_21 ((0x0055 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_22 ((0x0056 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_23 ((0x0057 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_24 ((0x0058 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_25 ((0x0059 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_26 ((0x005a << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_27 ((0x005b << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_28 ((0x005c << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_29 ((0x005d << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_30 ((0x005e << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_31 ((0x005f << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_32 ((0x0060 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_33 ((0x0061 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_34 ((0x0062 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_35 ((0x0063 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_36 ((0x0064 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_37 ((0x0065 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_38 ((0x0066 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_39 ((0x0067 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_40 ((0x0068 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_41 ((0x0069 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_42 ((0x006a << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_43 ((0x006b << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_44 ((0x006c << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_45 ((0x006d << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_46 ((0x006e << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_47 ((0x006f << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_48 ((0x0070 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_49 ((0x0071 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_50 ((0x0072 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_51 ((0x0073 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_52 ((0x0074 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_53 ((0x0075 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_54 ((0x0076 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_55 ((0x0077 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_56 ((0x0078 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_57 ((0x0079 << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_58 ((0x007a << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_59 ((0x007b << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_60 ((0x007c << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_61 ((0x007d << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_62 ((0x007e << 2) + 0xfe442c00)
+#define TS_OUTPUT_ES_TAB_63 ((0x007f << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_0 ((0x0080 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_0 ((0x0081 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_1 ((0x0082 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_1 ((0x0083 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_2 ((0x0084 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_2 ((0x0085 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_3 ((0x0086 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_3 ((0x0087 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_4 ((0x0088 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_4 ((0x0089 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_5 ((0x008a << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_5 ((0x008b << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_6 ((0x008c << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_6 ((0x008d << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_7 ((0x008e << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_7 ((0x008f << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_8 ((0x0090 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_8 ((0x0091 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_9 ((0x0092 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_9 ((0x0093 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_10 ((0x0094 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_10 ((0x0095 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_11 ((0x0096 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_11 ((0x0097 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_12 ((0x0098 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_12 ((0x0099 << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_13 ((0x009a << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_13 ((0x009b << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_14 ((0x009c << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_14 ((0x009d << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_LSB_15 ((0x009e << 2) + 0xfe442c00)
+#define TS_OUTPUT_PCR_REG_MSB_15 ((0x009f << 2) + 0xfe442c00)
+//========================================================================
+// TSD DESC AES REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe442000
+// -----------------------------------------------
+#define TSD_PID_RDY ((0x0000 << 2) + 0xfe442000)
+#define TSD_TEE_LOCK ((0x0001 << 2) + 0xfe442000)
+#define TSD_PID_STS ((0x0003 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_0 ((0x0004 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_0 ((0x0005 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_1 ((0x0006 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_1 ((0x0007 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_2 ((0x0008 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_2 ((0x0009 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_3 ((0x000a << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_3 ((0x000b << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_4 ((0x000c << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_4 ((0x000d << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_5 ((0x000e << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_5 ((0x000f << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_6 ((0x0010 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_6 ((0x0011 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_7 ((0x0012 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_7 ((0x0013 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_8 ((0x0014 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_8 ((0x0015 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_9 ((0x0016 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_9 ((0x0017 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_10 ((0x0018 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_10 ((0x0019 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_11 ((0x001a << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_11 ((0x001b << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_12 ((0x001c << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_12 ((0x001d << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_13 ((0x001e << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_13 ((0x001f << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_14 ((0x0020 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_14 ((0x0021 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_15 ((0x0022 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_15 ((0x0023 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_16 ((0x0024 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_16 ((0x0025 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_17 ((0x0026 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_17 ((0x0027 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_18 ((0x0028 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_18 ((0x0029 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_19 ((0x002a << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_19 ((0x002b << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_20 ((0x002c << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_20 ((0x002d << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_21 ((0x002e << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_21 ((0x002f << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_22 ((0x0030 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_22 ((0x0031 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_23 ((0x0032 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_23 ((0x0033 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_24 ((0x0034 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_24 ((0x0035 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_25 ((0x0036 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_25 ((0x0037 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_26 ((0x0038 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_26 ((0x0039 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_27 ((0x003a << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_27 ((0x003b << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_28 ((0x003c << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_28 ((0x003d << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_29 ((0x003e << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_29 ((0x003f << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_30 ((0x0040 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_30 ((0x0041 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_31 ((0x0042 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_31 ((0x0043 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_32 ((0x0044 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_32 ((0x0045 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_33 ((0x0046 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_33 ((0x0047 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_34 ((0x0048 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_34 ((0x0049 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_35 ((0x004a << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_35 ((0x004b << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_36 ((0x004c << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_36 ((0x004d << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_37 ((0x004e << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_37 ((0x004f << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_38 ((0x0050 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_38 ((0x0051 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_39 ((0x0052 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_39 ((0x0053 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_40 ((0x0054 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_40 ((0x0055 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_41 ((0x0056 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_41 ((0x0057 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_42 ((0x0058 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_42 ((0x0059 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_43 ((0x005a << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_43 ((0x005b << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_44 ((0x005c << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_44 ((0x005d << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_45 ((0x005e << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_45 ((0x005f << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_46 ((0x0060 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_46 ((0x0061 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_47 ((0x0062 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_47 ((0x0063 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_48 ((0x0064 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_48 ((0x0065 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_49 ((0x0066 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_49 ((0x0067 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_50 ((0x0068 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_50 ((0x0069 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_51 ((0x006a << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_51 ((0x006b << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_52 ((0x006c << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_52 ((0x006d << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_53 ((0x006e << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_53 ((0x006f << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_54 ((0x0070 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_54 ((0x0071 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_55 ((0x0072 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_55 ((0x0073 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_56 ((0x0074 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_56 ((0x0075 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_57 ((0x0076 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_57 ((0x0077 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_58 ((0x0078 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_58 ((0x0079 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_59 ((0x007a << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_59 ((0x007b << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_60 ((0x007c << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_60 ((0x007d << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_61 ((0x007e << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_61 ((0x007f << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_62 ((0x0080 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_62 ((0x0081 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_LSB_63 ((0x0082 << 2) + 0xfe442000)
+#define TSD_PID_TABLE_MSB_63 ((0x0083 << 2) + 0xfe442000)
+//========================================================================
+// SECURE TOP REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe440300
+// -----------------------------------------------
+#define SEC_TOP_CFG_LOCKABLE ((0x0000 << 2) + 0xfe440300)
+#define SEC_TOP_CFG_LOCK ((0x0001 << 2) + 0xfe440300)
+#define SEC_TOP_CFG_WTO ((0x0002 << 2) + 0xfe440300)
+#define SEC_TOP_N2_GENOUT ((0x0003 << 2) + 0xfe440300)
+#define SEC_TOP_CFG_REG ((0x0004 << 2) + 0xfe440300)
+#define SEC_TOP_NSK_CTRL ((0x0005 << 2) + 0xfe440300)
+#define SEC_TOP_AKL_STS ((0x0006 << 2) + 0xfe440300)
+#define SEC_TOP_ND_STATUS ((0x0007 << 2) + 0xfe440300)
+#define SEC_TOP_CFG_DEMUX ((0x0008 << 2) + 0xfe440300)
+#define SEC_TOP_CFG_DIF ((0x000c << 2) + 0xfe440300)
+#define SEC_TOP_NSK_HASH0 ((0x0010 << 2) + 0xfe440300)
+#define SEC_TOP_NSK_HASH1 ((0x0011 << 2) + 0xfe440300)
+#define SEC_TOP_NSK_HASH2 ((0x0012 << 2) + 0xfe440300)
+#define SEC_TOP_NSK_HASH3 ((0x0013 << 2) + 0xfe440300)
+#define SEC_TOP_PATH0_CTRL ((0x0028 << 2) + 0xfe440300)
+#define SEC_TOP_PATH1_CTRL ((0x0029 << 2) + 0xfe440300)
+#define SEC_TOP_PATH2_CTRL ((0x002a << 2) + 0xfe440300)
+#define SEC_TOP_PATH3_CTRL ((0x002b << 2) + 0xfe440300)
+#define SEC_TOP_DEMOD_PKT_CFG0 ((0x002c << 2) + 0xfe440300)
+#define SEC_TOP_DEMOD_PKT_CFG1 ((0x002d << 2) + 0xfe440300)
+#define SEC_TOP_DEMOD_PKT_CFG2 ((0x002e << 2) + 0xfe440300)
+#define SEC_TOP_DEMOD_PKT_CFG3 ((0x002f << 2) + 0xfe440300)
+#define SEC_TOP_DEMOD_FIFO_CFG0 ((0x0030 << 2) + 0xfe440300)
+#define SEC_TOP_DEMOD_FIFO_CFG1 ((0x0031 << 2) + 0xfe440300)
+#define SEC_TOP_TS_O_PATH_CTRL ((0x0032 << 2) + 0xfe440300)
+#define SEC_TOP_CLEAN_DEMOD_INT ((0x0033 << 2) + 0xfe440300)
+#define SEC_TOP_DEMOD_INT_MASK ((0x0034 << 2) + 0xfe440300)
+#define SEC_TOP_DEMOD_INT_STATUS ((0x0035 << 2) + 0xfe440300)
+#define SEC_TOP_TS_CHN0_ERR_STATUS ((0x0036 << 2) + 0xfe440300)
+#define SEC_TOP_TS_CHN1_ERR_STATUS ((0x0037 << 2) + 0xfe440300)
+#define SEC_TOP_TS_CHN2_ERR_STATUS ((0x0038 << 2) + 0xfe440300)
+#define SEC_TOP_TS_CHN3_ERR_STATUS ((0x0039 << 2) + 0xfe440300)
+//========================================================================
+// TSE DESC AES REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe442800
+// -----------------------------------------------
+#define TSE_PID_RDY ((0x0000 << 2) + 0xfe442800)
+#define TSE_TEE_LOCK ((0x0001 << 2) + 0xfe442800)
+#define TSE_PID_STS ((0x0003 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_0 ((0x0004 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_0 ((0x0005 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_1 ((0x0006 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_1 ((0x0007 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_2 ((0x0008 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_2 ((0x0009 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_3 ((0x000a << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_3 ((0x000b << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_4 ((0x000c << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_4 ((0x000d << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_5 ((0x000e << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_5 ((0x000f << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_6 ((0x0010 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_6 ((0x0011 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_7 ((0x0012 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_7 ((0x0013 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_8 ((0x0014 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_8 ((0x0015 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_9 ((0x0016 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_9 ((0x0017 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_10 ((0x0018 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_10 ((0x0019 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_11 ((0x001a << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_11 ((0x001b << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_12 ((0x001c << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_12 ((0x001d << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_13 ((0x001e << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_13 ((0x001f << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_14 ((0x0020 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_14 ((0x0021 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_15 ((0x0022 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_15 ((0x0023 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_16 ((0x0024 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_16 ((0x0025 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_17 ((0x0026 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_17 ((0x0027 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_18 ((0x0028 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_18 ((0x0029 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_19 ((0x002a << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_19 ((0x002b << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_20 ((0x002c << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_20 ((0x002d << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_21 ((0x002e << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_21 ((0x002f << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_22 ((0x0030 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_22 ((0x0031 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_23 ((0x0032 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_23 ((0x0033 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_24 ((0x0034 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_24 ((0x0035 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_25 ((0x0036 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_25 ((0x0037 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_26 ((0x0038 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_26 ((0x0039 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_27 ((0x003a << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_27 ((0x003b << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_28 ((0x003c << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_28 ((0x003d << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_29 ((0x003e << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_29 ((0x003f << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_30 ((0x0040 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_30 ((0x0041 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_31 ((0x0042 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_31 ((0x0043 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_32 ((0x0044 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_32 ((0x0045 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_33 ((0x0046 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_33 ((0x0047 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_34 ((0x0048 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_34 ((0x0049 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_35 ((0x004a << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_35 ((0x004b << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_36 ((0x004c << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_36 ((0x004d << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_37 ((0x004e << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_37 ((0x004f << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_38 ((0x0050 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_38 ((0x0051 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_39 ((0x0052 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_39 ((0x0053 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_40 ((0x0054 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_40 ((0x0055 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_41 ((0x0056 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_41 ((0x0057 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_42 ((0x0058 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_42 ((0x0059 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_43 ((0x005a << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_43 ((0x005b << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_44 ((0x005c << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_44 ((0x005d << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_45 ((0x005e << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_45 ((0x005f << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_46 ((0x0060 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_46 ((0x0061 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_47 ((0x0062 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_47 ((0x0063 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_48 ((0x0064 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_48 ((0x0065 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_49 ((0x0066 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_49 ((0x0067 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_50 ((0x0068 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_50 ((0x0069 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_51 ((0x006a << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_51 ((0x006b << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_52 ((0x006c << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_52 ((0x006d << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_53 ((0x006e << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_53 ((0x006f << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_54 ((0x0070 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_54 ((0x0071 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_55 ((0x0072 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_55 ((0x0073 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_56 ((0x0074 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_56 ((0x0075 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_57 ((0x0076 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_57 ((0x0077 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_58 ((0x0078 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_58 ((0x0079 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_59 ((0x007a << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_59 ((0x007b << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_60 ((0x007c << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_60 ((0x007d << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_61 ((0x007e << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_61 ((0x007f << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_62 ((0x0080 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_62 ((0x0081 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_LSB_63 ((0x0082 << 2) + 0xfe442800)
+#define TSE_PID_TABLE_MSB_63 ((0x0083 << 2) + 0xfe442800)
+//========================================================================
+// TSN DESC REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe442400
+// -----------------------------------------------
+#define TSN_PID_RDY ((0x0000 << 2) + 0xfe442400)
+#define TSN_TEE_LOCK ((0x0001 << 2) + 0xfe442400)
+#define TSN_PID_STS ((0x0003 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_0 ((0x0004 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_1 ((0x0005 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_2 ((0x0006 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_3 ((0x0007 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_4 ((0x0008 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_5 ((0x0009 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_6 ((0x000a << 2) + 0xfe442400)
+#define TSN_PID_TABLE_7 ((0x000b << 2) + 0xfe442400)
+#define TSN_PID_TABLE_8 ((0x000c << 2) + 0xfe442400)
+#define TSN_PID_TABLE_9 ((0x000d << 2) + 0xfe442400)
+#define TSN_PID_TABLE_10 ((0x000e << 2) + 0xfe442400)
+#define TSN_PID_TABLE_11 ((0x000f << 2) + 0xfe442400)
+#define TSN_PID_TABLE_12 ((0x0010 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_13 ((0x0011 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_14 ((0x0012 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_15 ((0x0013 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_16 ((0x0014 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_17 ((0x0015 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_18 ((0x0016 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_19 ((0x0017 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_20 ((0x0018 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_21 ((0x0019 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_22 ((0x001a << 2) + 0xfe442400)
+#define TSN_PID_TABLE_23 ((0x001b << 2) + 0xfe442400)
+#define TSN_PID_TABLE_24 ((0x001c << 2) + 0xfe442400)
+#define TSN_PID_TABLE_25 ((0x001d << 2) + 0xfe442400)
+#define TSN_PID_TABLE_26 ((0x001e << 2) + 0xfe442400)
+#define TSN_PID_TABLE_27 ((0x001f << 2) + 0xfe442400)
+#define TSN_PID_TABLE_28 ((0x0020 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_29 ((0x0021 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_30 ((0x0022 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_31 ((0x0023 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_32 ((0x0024 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_33 ((0x0025 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_34 ((0x0026 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_35 ((0x0027 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_36 ((0x0028 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_37 ((0x0029 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_38 ((0x002a << 2) + 0xfe442400)
+#define TSN_PID_TABLE_39 ((0x002b << 2) + 0xfe442400)
+#define TSN_PID_TABLE_40 ((0x002c << 2) + 0xfe442400)
+#define TSN_PID_TABLE_41 ((0x002d << 2) + 0xfe442400)
+#define TSN_PID_TABLE_42 ((0x002e << 2) + 0xfe442400)
+#define TSN_PID_TABLE_43 ((0x002f << 2) + 0xfe442400)
+#define TSN_PID_TABLE_44 ((0x0030 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_45 ((0x0031 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_46 ((0x0032 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_47 ((0x0033 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_48 ((0x0034 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_49 ((0x0035 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_50 ((0x0036 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_51 ((0x0037 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_52 ((0x0038 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_53 ((0x0039 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_54 ((0x003a << 2) + 0xfe442400)
+#define TSN_PID_TABLE_55 ((0x003b << 2) + 0xfe442400)
+#define TSN_PID_TABLE_56 ((0x003c << 2) + 0xfe442400)
+#define TSN_PID_TABLE_57 ((0x003d << 2) + 0xfe442400)
+#define TSN_PID_TABLE_58 ((0x003e << 2) + 0xfe442400)
+#define TSN_PID_TABLE_59 ((0x003f << 2) + 0xfe442400)
+#define TSN_PID_TABLE_60 ((0x0040 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_61 ((0x0041 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_62 ((0x0042 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_63 ((0x0043 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_64 ((0x0044 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_65 ((0x0045 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_66 ((0x0046 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_67 ((0x0047 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_68 ((0x0048 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_69 ((0x0049 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_70 ((0x004a << 2) + 0xfe442400)
+#define TSN_PID_TABLE_71 ((0x004b << 2) + 0xfe442400)
+#define TSN_PID_TABLE_72 ((0x004c << 2) + 0xfe442400)
+#define TSN_PID_TABLE_73 ((0x004d << 2) + 0xfe442400)
+#define TSN_PID_TABLE_74 ((0x004e << 2) + 0xfe442400)
+#define TSN_PID_TABLE_75 ((0x004f << 2) + 0xfe442400)
+#define TSN_PID_TABLE_76 ((0x0050 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_77 ((0x0051 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_78 ((0x0052 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_79 ((0x0053 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_80 ((0x0054 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_81 ((0x0055 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_82 ((0x0056 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_83 ((0x0057 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_84 ((0x0058 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_85 ((0x0059 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_86 ((0x005a << 2) + 0xfe442400)
+#define TSN_PID_TABLE_87 ((0x005b << 2) + 0xfe442400)
+#define TSN_PID_TABLE_88 ((0x005c << 2) + 0xfe442400)
+#define TSN_PID_TABLE_89 ((0x005d << 2) + 0xfe442400)
+#define TSN_PID_TABLE_90 ((0x005e << 2) + 0xfe442400)
+#define TSN_PID_TABLE_91 ((0x005f << 2) + 0xfe442400)
+#define TSN_PID_TABLE_92 ((0x0060 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_93 ((0x0061 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_94 ((0x0062 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_95 ((0x0063 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_96 ((0x0064 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_97 ((0x0065 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_98 ((0x0066 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_99 ((0x0067 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_100 ((0x0068 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_101 ((0x0069 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_102 ((0x006a << 2) + 0xfe442400)
+#define TSN_PID_TABLE_103 ((0x006b << 2) + 0xfe442400)
+#define TSN_PID_TABLE_104 ((0x006c << 2) + 0xfe442400)
+#define TSN_PID_TABLE_105 ((0x006d << 2) + 0xfe442400)
+#define TSN_PID_TABLE_106 ((0x006e << 2) + 0xfe442400)
+#define TSN_PID_TABLE_107 ((0x006f << 2) + 0xfe442400)
+#define TSN_PID_TABLE_108 ((0x0070 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_109 ((0x0071 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_110 ((0x0072 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_111 ((0x0073 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_112 ((0x0074 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_113 ((0x0075 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_114 ((0x0076 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_115 ((0x0077 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_116 ((0x0078 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_117 ((0x0079 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_118 ((0x007a << 2) + 0xfe442400)
+#define TSN_PID_TABLE_119 ((0x007b << 2) + 0xfe442400)
+#define TSN_PID_TABLE_120 ((0x007c << 2) + 0xfe442400)
+#define TSN_PID_TABLE_121 ((0x007d << 2) + 0xfe442400)
+#define TSN_PID_TABLE_122 ((0x007e << 2) + 0xfe442400)
+#define TSN_PID_TABLE_123 ((0x007f << 2) + 0xfe442400)
+#define TSN_PID_TABLE_124 ((0x0080 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_125 ((0x0081 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_126 ((0x0082 << 2) + 0xfe442400)
+#define TSN_PID_TABLE_127 ((0x0083 << 2) + 0xfe442400)
+//========================================================================
+// RNG REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe440700
+// -----------------------------------------------
+#define RNG_TEE_READY ((0x0000 << 2) + 0xfe440700)
+#define RNG_TEE_LOCK ((0x0001 << 2) + 0xfe440700)
+#define RNG_TEE_CFG ((0x0002 << 2) + 0xfe440700)
+#define RNG_TEE_NIST_OUT ((0x0003 << 2) + 0xfe440700)
+#define RNG_TEE_OUT0 ((0x0004 << 2) + 0xfe440700)
+#define RNG_TEE_OUT1 ((0x0005 << 2) + 0xfe440700)
+#define RNG_TEE_OUT2 ((0x0006 << 2) + 0xfe440700)
+#define RNG_TEE_OUT3 ((0x0007 << 2) + 0xfe440700)
+#define RNG_CFG_RING ((0x0010 << 2) + 0xfe440700)
+#define RNG_CFG_RESEED ((0x0011 << 2) + 0xfe440700)
+#define RNG_CFG_HEALTH ((0x0012 << 2) + 0xfe440700)
+#define RNG_CFG_MISC ((0x0013 << 2) + 0xfe440700)
+#define RNG_REE_READY ((0x0020 << 2) + 0xfe440700)
+#define RNG_REE_DEBUG ((0x0021 << 2) + 0xfe440700)
+#define RNG_REE_CFG ((0x0022 << 2) + 0xfe440700)
+#define RNG_REE_OUT0 ((0x0024 << 2) + 0xfe440700)
+#define RNG_REE_OUT1 ((0x0025 << 2) + 0xfe440700)
+#define RNG_REE_OUT2 ((0x0026 << 2) + 0xfe440700)
+#define RNG_REE_OUT3 ((0x0027 << 2) + 0xfe440700)
+//========================================================================
+// OTP REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe440000
+// -----------------------------------------------
+#define OTP_TEE_RDY ((0x0000 << 2) + 0xfe440000)
+#define OTP_TEE_DEBUG ((0x0001 << 2) + 0xfe440000)
+#define OTP_TEE_CFG ((0x0002 << 2) + 0xfe440000)
+#define OTP_TEE_WR_DAT ((0x0004 << 2) + 0xfe440000)
+#define OTP_TEE_RD_DAT ((0x0008 << 2) + 0xfe440000)
+#define OTP_LIC ((0x0010 << 2) + 0xfe440000)
+#define OTP_AML_ID_L ((0x0020 << 2) + 0xfe440000)
+#define OTP_AML_ID_H ((0x0021 << 2) + 0xfe440000)
+#define OTP_ACGK_ID_L ((0x0022 << 2) + 0xfe440000)
+#define OTP_ACGK_ID_H ((0x0023 << 2) + 0xfe440000)
+#define OTP_DVGK_ID_L ((0x0024 << 2) + 0xfe440000)
+#define OTP_DVGK_ID_H ((0x0025 << 2) + 0xfe440000)
+#define OTP_DVUK_ID_L ((0x0026 << 2) + 0xfe440000)
+#define OTP_DVUK_ID_H ((0x0027 << 2) + 0xfe440000)
+#define OTP_DGPK_ID_L ((0x0028 << 2) + 0xfe440000)
+#define OTP_DGPK_ID_H ((0x0029 << 2) + 0xfe440000)
+#define OTP_SECPU_ID_L ((0x002a << 2) + 0xfe440000)
+#define OTP_SECPU_ID_H ((0x002b << 2) + 0xfe440000)
+#define OTP_ETSI012_ID_L ((0x002c << 2) + 0xfe440000)
+#define OTP_ETSI012_ID_H ((0x002d << 2) + 0xfe440000)
+#define OTP_ETSI3_ID_L ((0x002e << 2) + 0xfe440000)
+#define OTP_ETSI3_ID_H ((0x002f << 2) + 0xfe440000)
+#define OTP_MSR_ID_L ((0x0030 << 2) + 0xfe440000)
+#define OTP_MSR_ID_H ((0x0031 << 2) + 0xfe440000)
+#define OTP_VO_ID_L ((0x0032 << 2) + 0xfe440000)
+#define OTP_VO_ID_H ((0x0033 << 2) + 0xfe440000)
+#define OTP_NUID_ID_L ((0x0034 << 2) + 0xfe440000)
+#define OTP_NUID_ID_H ((0x0035 << 2) + 0xfe440000)
+#define OTP_CONAX_ID_L ((0x0036 << 2) + 0xfe440000)
+#define OTP_CONAX_ID_H ((0x0037 << 2) + 0xfe440000)
+#define OTP_NSK_ID_L ((0x0038 << 2) + 0xfe440000)
+#define OTP_NSK_ID_H ((0x0039 << 2) + 0xfe440000)
+#define OTP_REE_RDY ((0x0040 << 2) + 0xfe440000)
+#define OTP_REE_DEBUG ((0x0041 << 2) + 0xfe440000)
+#define OTP_REE_CFG ((0x0042 << 2) + 0xfe440000)
+#define OTP_MRK_CHKNUM ((0x0043 << 2) + 0xfe440000)
+#define OTP_REE_RD_DAT ((0x0048 << 2) + 0xfe440000)
+
+#define OTP_LIC00 (OTP_LIC + 0x00)
+#define OTP_LIC01 (OTP_LIC + 0x04)
+#define OTP_LIC02 (OTP_LIC + 0x08)
+#define OTP_LIC03 (OTP_LIC + 0x0C)
+
+#define OTP_LIC10 (OTP_LIC + 0x10)
+#define OTP_LIC11 (OTP_LIC + 0x14)
+#define OTP_LIC12 (OTP_LIC + 0x18)
+#define OTP_LIC13 (OTP_LIC + 0x1C)
+
+#define OTP_LIC20 (OTP_LIC + 0x20)
+#define OTP_LIC21 (OTP_LIC + 0x24)
+#define OTP_LIC22 (OTP_LIC + 0x28)
+#define OTP_LIC23 (OTP_LIC + 0x2C)
+
+#define OTP_LIC30 (OTP_LIC + 0x30)
+#define OTP_LIC31 (OTP_LIC + 0x34)
+#define OTP_LIC32 (OTP_LIC + 0x38)
+#define OTP_LIC33 (OTP_LIC + 0x3C)
+
+#define OTP_LIC0 (OTP_LIC00)
+
+//========================================================================
+// KL REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe440200
+// -----------------------------------------------
+#define MKL_TEE_RDY ((0x0000 << 2) + 0xfe440200)
+#define MKL_TEE_DEBUG ((0x0001 << 2) + 0xfe440200)
+#define MKL_TEE_CFG ((0x0002 << 2) + 0xfe440200)
+#define MKL_TEE_CMD ((0x0003 << 2) + 0xfe440200)
+#define MKL_TEE_EK ((0x0004 << 2) + 0xfe440200)
+#define MKL_TEE_CR_0 ((0x001c << 2) + 0xfe440200)
+#define MKL_TEE_CR_1 ((0x001d << 2) + 0xfe440200)
+#define MKL_TEE_CR_2 ((0x001e << 2) + 0xfe440200)
+#define MKL_TEE_CR_3 ((0x001f << 2) + 0xfe440200)
+#define MKL_REE_RDY ((0x0020 << 2) + 0xfe440200)
+#define MKL_REE_DEBUG ((0x0021 << 2) + 0xfe440200)
+#define MKL_REE_CFG ((0x0022 << 2) + 0xfe440200)
+#define MKL_REE_CMD ((0x0023 << 2) + 0xfe440200)
+#define MKL_REE_EK ((0x0024 << 2) + 0xfe440200)
+//========================================================================
+// DMA REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe440400
+// -----------------------------------------------
+#define DMA_CORE_DSC_0 ((0x0000 << 2) + 0xfe440400)
+#define DMA_CORE_DSC_1 ((0x0001 << 2) + 0xfe440400)
+#define DMA_CORE_DSC_2 ((0x0002 << 2) + 0xfe440400)
+#define DMA_CORE_DSC_3 ((0x0003 << 2) + 0xfe440400)
+#define DMA_CORE_DSC_4 ((0x0004 << 2) + 0xfe440400)
+#define DMA_CORE_DSC_5 ((0x0005 << 2) + 0xfe440400)
+#define DMA_CORE_IRQ_STS_0 ((0x0008 << 2) + 0xfe440400)
+#define DMA_CORE_IRQ_STS_1 ((0x0009 << 2) + 0xfe440400)
+#define DMA_CORE_IRQ_STS_2 ((0x000a << 2) + 0xfe440400)
+#define DMA_CORE_IRQ_STS_3 ((0x000b << 2) + 0xfe440400)
+#define DMA_CORE_IRQ_STS_4 ((0x000c << 2) + 0xfe440400)
+#define DMA_CORE_IRQ_STS_5 ((0x000d << 2) + 0xfe440400)
+#define DMA_CORE_CFG_REG ((0x0010 << 2) + 0xfe440400)
+#define DMA_CORE_CFG_SEC_LSB ((0x0011 << 2) + 0xfe440400)
+#define DMA_CORE_CFG_SEC_MSB ((0x0012 << 2) + 0xfe440400)
+//========================================================================
+// KT REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe440500
+// -----------------------------------------------
+#define KT_TEE_RDY ((0x0000 << 2) + 0xfe440500)
+#define KT_TEE_RDY2 ((0x0001 << 2) + 0xfe440500)
+#define KT_TEE_CFG ((0x0002 << 2) + 0xfe440500)
+#define KT_TEE_STS ((0x0003 << 2) + 0xfe440500)
+#define KT_TEE_KEY0 ((0x0004 << 2) + 0xfe440500)
+#define KT_TEE_KEY1 ((0x0005 << 2) + 0xfe440500)
+#define KT_TEE_KEY2 ((0x0006 << 2) + 0xfe440500)
+#define KT_TEE_KEY3 ((0x0007 << 2) + 0xfe440500)
+#define KT_REE_RDY ((0x0020 << 2) + 0xfe440500)
+#define KT_REE_RDY2 ((0x0021 << 2) + 0xfe440500)
+#define KT_REE_CFG ((0x0022 << 2) + 0xfe440500)
+#define KT_REE_STS ((0x0023 << 2) + 0xfe440500)
+#define KT_REE_KEY0 ((0x0024 << 2) + 0xfe440500)
+#define KT_REE_KEY1 ((0x0025 << 2) + 0xfe440500)
+#define KT_REE_KEY2 ((0x0026 << 2) + 0xfe440500)
+#define KT_REE_KEY3 ((0x0027 << 2) + 0xfe440500)
+//========================================================================
+// CERT REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe440600
+// -----------------------------------------------
+//========================================================================
+// SP REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe441000
+// -----------------------------------------------
+//ree domian
+#define REE_SCPU2REE_CSR_ADDR ((0x0300 << 2) + 0xfe441000)
+#define REE_SCPU2REE_DATA_ST_ADDR ((0x0380 << 2) + 0xfe441000)
+#define REE_SCPU2REE_DATA_ED_ADDR ((0x039f << 2) + 0xfe441000)
+#define REE_REE2SCPU_CSR_ADDR ((0x0200 << 2) + 0xfe441000)
+#define REE_REE2SCPU_DATA_ST_ADDR ((0x0280 << 2) + 0xfe441000)
+#define REE_REE2SCPU_DATA_ED_ADDR ((0x029f << 2) + 0xfe441000)
+//tee domian
+#define TEE_SCPU2TEE_CSR_ADDR ((0x0100 << 2) + 0xfe441000)
+#define TEE_SCPU2TEE_DATA_ST_ADDR ((0x0180 << 2) + 0xfe441000)
+#define TEE_SCPU2TEE_DATA_ED_ADDR ((0x019f << 2) + 0xfe441000)
+#define TEE_TEE2SCPU_CSR_ADDR ((0x0000 << 2) + 0xfe441000)
+#define TEE_TEE2SCPU_DATA_ST_ADDR ((0x0080 << 2) + 0xfe441000)
+#define TEE_TEE2SCPU_DATA_ED_ADDR ((0x009f << 2) + 0xfe441000)
+//========================================================================
+// NSK REG - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe450000
+// -----------------------------------------------
+//
+// Closing file: REG_LIST_SECURITY_RTL.h
+//
+//
+// Reading file: REG_LIST_DEMUX_RTL.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe040000
+// -----------------------------------------------
+// There are two instantiations under one CBUS slave. Each CBUS slave can support
+// 256 registers. Each demux is allocated 128 registers so set the offset in
+// the middle
+// Copy this define but don't add a base address
+#define SECOND_DEMUX_OFFSET_0 0x50
+#define THIRD_DEMUX_OFFSET_0 0xa0
+//========================================================================
+// STB TOP Registers (8'hf0 - 8'hf7)
+//========================================================================
+// Bit 5:4 -- fec_sel_demux_2
+// Bit 3:2 -- fec_sel_demux_1
+// Bit 1:0 -- fec_sel_demux_0
+#define TS_TOP_CONFIG1 ((0x004f << 2) + 0xfe040000)
+// Bit 31:24 -- file_m2ts_skip_bytes_hiu1
+// Bit 23:22 -- reserved
+// Bit 21 -- ts_hiu_enable_hiu1
+// Bit 20:16 -- fec_clk_div_hiu1
+// Bit 15:8 -- TS_package_length_sub_1_hiu1 (default : 187)
+// Bit 7:0 -- fec_sync_byte_hiu1 (default : 0x47)
+#define TS_HIU1_CONFIG ((0x004e << 2) + 0xfe040000)
+//bit[1:0]-- stb_recorder2_sel
+#define STB_RECORDER2_CNTL ((0x00ee << 2) + 0xfe040000)
+// bit [11]-- s2p2_disable
+// bit [10:7]-- s2p2_clk_div
+// bit [6:0]-- fec_serial_control_2
+#define STB_S2P2_CONFIG ((0x00ef << 2) + 0xfe040000)
+// bit 30:28 -- ciplus_o_sel
+// bit 27:26 -- ciplus_i_sel
+// bit 25 -- use FAIL fro TS2
+// bit 24 -- use FAIL fro TS1
+// bit 23 -- use FAIL fro TS0
+// bit 22 -- invert fec_error for S2P1
+// bit 21 -- invert fec_data for S2P1
+// bit 20 -- invert fec_sync for S2P1
+// bit 19 -- invert fec_valid for S2P1
+// bit 18 -- invert fec_clk for S2P1
+// bit 17:16 -- fec_s_sel for S2P1 00 - select TS0, 01 -- select TS1, 10 -- select TS2, 11 - reserved
+// Bit 15 -- enable_des_pl_clk
+// Bit 14 -- ts_out_select[3]
+// Bit 13 -- use FAIL for TS3
+// Bit 12:10 -- ts_out_select[2:0], 0-TS0, 1-TS1, 2-TS2, 3-TS3, 4-S2P2, 5-S2P1, 6-S2P0, 7-File, 8-File1
+// bit 9:8 -- des_i_sel 00 -- select_fec_0, 01 -- select_fec_1, 10 -- select_fec_2, 11 - reserved
+// bit 7 -- enable_des_pl
+// bit 6 -- invert fec_error for S2P0
+// bit 5 -- invert fec_data for S2P0
+// bit 4 -- invert fec_sync for S2P0
+// bit 3 -- invert fec_valid for S2P0
+// bit 2 -- invert fec_clk for S2P0
+// bit 1:0 -- fec_s_sel for S2P0 00 - select TS0, 01 -- select TS1, 10 -- select TS2, 11 - reserved
+#define STB_TOP_CONFIG ((0x00f0 << 2) + 0xfe040000)
+// 31:28 - s2p1_clk_div
+// 27:24 - s2p0_clk_div
+// 23 - s2p1_disable
+// 22 - s2p0_disable
+// 21 - Reserved
+// 20 -- TS_OUT_error_INVERT
+// 19 -- TS_OUT_data_INVERT
+// 18 -- TS_OUT_sync_INVERT
+// 17 -- TS_OUT_valid_INVERT
+// 16 -- TS_OUT_clk_INVERT
+// 15:8 -- TS_package_length_sub_1 (default : 187)
+// 7:0 -- fec_sync_byte (default : 0x47)
+#define TS_TOP_CONFIG ((0x00f1 << 2) + 0xfe040000)
+// Bit 25:24 -- transport_scrambling_control_odd_2 // should be 3
+// Bit 23:16 -- file_m2ts_skip_bytes
+// Bit 15:8 -- des_out_dly
+// Bit 7:6 -- transport_scrambling_control_odd // should be 3
+// Bit 5 -- ts_hiu_enable
+// Bit 4:0 -- fec_clk_div
+#define TS_FILE_CONFIG ((0x00f2 << 2) + 0xfe040000)
+// Bit 19:14 -- des_2 ts pl state -- Read Only
+// Bit 13:8 -- des ts pl state -- Read Only
+// Bit 3:0 PID index to 8 PID to get key-set
+// auto increse after TS_PL_PID_DATA read/write
+#define TS_PL_PID_INDEX ((0x00f3 << 2) + 0xfe040000)
+// Bit 13 -- PID match disble
+// Bit 12:0 -- PID
+#define TS_PL_PID_DATA ((0x00f4 << 2) + 0xfe040000)
+#define COMM_DESC_KEY0 ((0x00f5 << 2) + 0xfe040000)
+#define COMM_DESC_KEY1 ((0x00f6 << 2) + 0xfe040000)
+#define COMM_DESC_KEY_RW ((0x00f7 << 2) + 0xfe040000)
+// CI+ Register defines
+// Bits[31:0] of the key
+#define CIPLUS_KEY0 ((0x00f8 << 2) + 0xfe040000)
+// Bits[63:32] of the key
+#define CIPLUS_KEY1 ((0x00f9 << 2) + 0xfe040000)
+// Bits[95:64] of the key
+#define CIPLUS_KEY2 ((0x00fa << 2) + 0xfe040000)
+// Bits[127:96] of the key
+#define CIPLUS_KEY3 ((0x00fb << 2) + 0xfe040000)
+// bit[5] write AES IV B value
+// bit[4] write AES IV A value
+// bit[3] write AES B key
+// bit[2] write AES A key
+// bit[1] write DES B key
+// bit[0] write DES A key
+#define CIPLUS_KEY_WR ((0x00fc << 2) + 0xfe040000)
+// [15:8] TS out delay. This controls the rate at which the CIplus module drives TS out
+// [3] General enable for the ciplus module
+// [2] AES CBC disable (default should be 0 to enable AES CBC)
+// [1] AES Enable
+// [0] DES Eanble
+#define CIPLUS_CONFIG ((0x00fd << 2) + 0xfe040000)
+// bit[31:28] AES IV endian
+// bit[27:24] AES message out endian
+// bit[23:20] AES message in endian
+// bit[19:16] AES key endian
+// bit[15:11] unused
+// bit[10:8] DES message out endian
+// bit[6:4] DES message in endian
+// bit[2:0] DES key endian
+#define CIPLUS_ENDIAN ((0x00fe << 2) + 0xfe040000)
+// bit 15:8 - des_out_dly_2
+// bit 7 - reserved
+// Bit 6-- enable_des_pl_clk_2
+// bit 5 - enable_des_pl_2
+// bit 4:2 -- use_des_2 bit[2] -- demux0, bit[3] -- demux1, bit[4] -- demux2
+// bit 1:0 -- des_i_sel_2 00 -- select_fec_0, 01 -- select_fec_1, 10 -- select_fec_2, 11 - reserved
+#define COMM_DESC_2_CTL ((0x00ff << 2) + 0xfe040000)
+//
+// NOTE: Don't process the demux registers using the standard create_headers.... perl script.
+// Instead, since the demux has multiple instances (and many registers) use a separate
+// script to create a separate stb_define.h for C-code.
+//========================================================================
+// STB Registers (8'h00 - 8'h4f)
+//
+//========================================================================
+// STB registers are 8'h0x
+// Bit 15:0 -- version number : 0x0002 (v0.01)
+// Bit 16 -- fec_select[3]
+// Bit 15 -- fec_core_select 1 - select descramble output
+// Bit 14:12 - fec_select[2:0] 0-TS0, 1-TS1, 2-TS2, 3-TS3, 4-S2P2, 5-S2P1, 6-S2P0, 7-File, 8-File1
+// Bit 11 -- FEC_CLK
+// Bit 10 -- SOP
+// Bit 9 -- D_VALID
+// Bit 8 -- D_FAIL
+// Bit 7:0 -- D_DATA 7:0
+// bit 31 -- enable_free_clk_fec_data_valid
+// bit 30 -- enable_free_clk_stb_reg
+// bit 29 -- always_use_pes_package_length
+// bit 28 -- disable_pre_incomplete_section_fix
+// bit 27 -- pointer_field_multi_pre_en
+// bit 26 -- ignore_pre_incomplete_section
+// bit 25 -- video2_enable
+// bit 24:22 -- video2_type
+// bit 21 -- do_not_trust_pes_package_length
+// bit 20 (bit 4) -- Bypass use recoder path
+// bit 19 (bit 3) -- clear_PID_continuity_counter_valid
+// bit 18 (bit 2) -- Disable Splicing
+// bit 17 (bit 1) -- Insert PES_STRONG_SYNC in Audio PES
+// bit 16 (bit 0) -- Insert PES_STRONG_SYNC in Video PES
+// Bit 15 - do not trust section length
+// Bit 14 - om cmd push even zero
+// Bit 13 - set_buff_ready_even_not_busy
+// Bit 12 - SUB, OTHER PES interrupt at beginning of PES
+// Bit 11 - discard_av_package -- for ts_recorder use only
+// Bit 10 - ts_recorder_select 0:after PID filter 1:before PID filter
+// Bit 9 - ts_recorder_enable
+// Bit 8 - (table_id == 0xff) means section_end
+// Bit 7 - do not send uncomplete section
+// Bit 6 - do not discard duplicate package
+// Bit 5 - search SOP when trasport_error_indicator
+// Bit 4 - stb demux enable
+// Bit 3 - do not reset state machine on SOP
+// Bit 2 - search SOP when error happened ( when ignore_fail_n_sop, will have this case)
+// Bit 1 - do not use SOP input ( check FEC sync byte instead )
+// Bit 0 - ignore fec_error bit when non sop ( check error on SOP only)
+// bit 15:8 demux package length - 1 ( default : 187 )
+// bit 7:0 default is 0x47
+// bit 31:16 -- filter memory write data hi[31:16]
+// bit 15:0 -- filter memory write data low [15:0]
+// bit 31:24 -- advanced setting hi
+// bit 23:16 -- advanced setting low
+// bit 15 -- filter memory write data request
+// bit 7:0 -- filter memory write addr
+// bit 13:8 demux state -- read only
+// bit 7:4 -- maxnum section filter compare address
+// bit 3:0 -- maxnum PID filter compare address
+// bit 15 - transport_error_indicator
+// bit 14 - payload_unit_start_indicator
+// bit 13 - transport_priority
+// bit 12:0 - PID
+// bit 7:6 transport_scrambling_control
+// bit 5:4 adaptation_field_control
+// bit 3:0 continuity_counter
+// bit 15:12 -- om_cmd_count (read only)
+// bit 11:9 -- overflow_count // bit 11:9 -- om_cmd_wr_ptr (read only)
+// bit 8:6 -- om_overwrite_count // bit 8:6 -- om_cmd_rd_ptr (read only)
+// bit 5:3 -- type_stb_om_w_rd (read only)
+// bit 2 -- unit_start_stb_om_w_rd (read only)
+// bit 1 -- om_cmd_overflow (read only)
+// bit 0 -- om_cmd_pending (read)
+// bit 0 -- om_cmd_read_finished (write)
+// bit 15:9 // bit 14:8 -- count_stb_om_w_rd (read only)
+// bit 8:0 // bit 7:0 -- start_stb_om_wa_rd (read only)
+// bit 11:0 -- offset for section data
+// bit 31:16 -- base address for section buffer group 0 (*0x400 to get real address)
+// bit 15:0 -- base address for section buffer group 1 (*0x400 to get real address)
+// bit 31:16 -- ba2e address for section buffer group 2 (*0x400 to get real address)
+// bit 15:0 -- base address for section buffer group 3 (*0x400 to get real address)
+// bit 3:0 -- section buffer size for group 0 (bit used, for example, 10 means 1K)
+// bit 7:4 -- section buffer size for group 1
+// bit 11:8 -- section buffer size for group 2
+// bit 15:12 -- section buffer size for group 3
+// section buffer busy status for buff 31:0 ( Read Only )
+// section buffer write status for buff 31:0 -- Read
+// clear buffer status ( buff READY and BUSY ) -- write
+// bit 4:0 -- SEC_BUFFER_INDEX RW
+// bit 12:8 -- SEC_BUFFER_NUMBER for the INDEX buffer Read_Only
+// bit 14 -- output_section_buffer_valid
+// bit 15 -- section_reset_busy (Read Only)
+// bit 9:5 -- BYPASS PID number
+// bit 4:0 -- PCR PID number
+// bit 15:0 -- stream_id filter bit enable
+// bit 7:0 -- stream_id filter target
+// bit 12 -- PCR_EN
+// bit 11:0 -- PCR90K_DIV
+// bit 31:0 -- PCR[31:0] R/W
+// bit 31:0 -- VPTS[31:0] R/W
+// bit 31:0 -- VDTS[31:0] R/W
+// bit 31:0 -- APTS[31:0] R/W
+// bit 31:0 -- SPTS[31:0] R/W
+// read -- status, write 1 clear status
+// bit 15 -- SUB_PTS[32]
+// bit 14 -- AUDIO_PTS[32]
+// bit 13 -- VIDEO_DTS[32]
+// bit 12 -- VIDEO_PTS[32]
+// bit 3 -- sub_pts_ready
+// bit 2 -- audio_pts_ready
+// bit 1 -- video_dts_ready
+// bit 0 -- video_pts_ready
+// bit 3:0 --
+// 0 -- adaptation_field_length[7:0], adaption_field_byte_1[7:0]
+// 1 -- stream_id[7:0], pes_header_bytes_left[7:0]
+// 2 -- pes_package_bytes_left[15:0]
+// 3 -- pes_ctr_byte[7:0], pes_flag_byte[7:0]
+//
+// read only
+// bit[31] -- no_match_record_en
+// bit[30:16] - reserved
+// default : 0x807f
+// bit 15:9 -- MAX OM DMA COUNT (default: 0x40)
+// bit 8:0 -- LAST ADDR OF OM ADDR (default: 127)
+// 15:0 WRITE 1 CLEAR to clear interrupt source
+//12 -- INPUT_TIME_OUT
+//11 -- PCR_ready
+//10 -- audio_splicing_point
+// 9 -- video_splicing_point
+// 8 -- other_PES_int
+// 7 -- sub_PES_int
+// 6 -- discontinuity
+// 5 -- duplicated_pack_found
+// 4 -- New PDTS ready
+// 3 -- om_cmd_buffer ready for access
+// 2 -- section buffer ready
+// 1 -- transport_error_indicator
+// 0 -- TS ERROR PIN
+// Bit 5:3 - demux om write endian control for bypass
+// Bit 2:0 - demux om write endian control for section
+// When Bit 31 - 1 write will indicate all type use sepertate endian (Write Only)
+// Bit 23:21 - demux om write endian control for OTHER_PES_PACKET
+// Bit 20:18 - demux om write endian control for SCR_ONLY_PACKET
+// Bit 17:15 - demux om write endian control for SUB_PACKET
+// Bit 14:12 - demux om write endian control for AUDIO_PACKET
+// Bit 11:9 - demux om write endian control for VIDEO_PACKET
+//
+// When Bit 31 - 0 write will indicate all type else use Bit 8:6
+// Bit 8:6 - demux om write endian control for else
+// Bit 10:9 -- sel DPTS_wr_ptr: 00 from parserA ; 01 from parserB
+// Bit 8:7 -- use hi_bsf interface: 01 sel hiu0; 10 sel hiu1
+// Bit 6:2 - Reserved
+// Bit 1 - enable_halt_ts_hiu_fix
+// Bit 0 - enable_halt_ts_hiu
+// bit 15:0 -- base address for section buffer start (*0x10000 to get real base)
+// bit 11 -- mask bit for OTHER_PES_AHB_DMA_EN
+// bit 10 -- mask bit for SUB_AHB_DMA_EN
+// bit 9 -- mask bit for BYPASS_AHB_DMA_EN
+// bit 8 -- mask bit for SECTION_AHB_DMA_EN
+// bit 7 -- mask bit for recoder stream
+// bit 6:0 -- mask bit for each type
+// bit 31:0 -- vb_wr_ptr for video PDTS
+// bit 31:0 -- ab_wr_ptr for audio PDTS
+// bit 20:0 -- SB_WRITE_PTR (sb_wr_ptr << 3 == byte write position)
+// bit 19:0 -- SB_START (sb_start << 12 == byte address);
+// bit 20:0 -- SB_SIZE (sb_size << 3 == byte size, 16M maximun)
+// bit 31:0 -- sb_wr_ptr for sub PES
+// bit 31:16 -- ob_wr_ptr for other PES
+// bit 20:0 -- OB_WRITE_PTR (ob_wr_ptr << 3 == byte write position)
+// bit 19:0 -- OB_START (ob_start << 12 == byte address);
+// bit 20:0 -- OB_SIZE (ob_size << 3 == byte size, 16M maximun)
+// bit 31:0 -- ob_wr_ptr for sub PES
+// 15:0 DEMUX interrupt MASK
+// 9 -- splicing_point
+// 8 -- other_PES_int
+// 7 -- sub_PES_int
+// 6 -- discontinuity
+// 5 -- duplicated_pack_found
+// 4 -- New PDTS ready
+// 3 -- om_cmd_buffer ready for access
+// 2 -- section buffer ready
+// 1 -- transport_error_indicator
+// 0 -- TS ERROR PIN
+// 31:16 VIDEO PID filter data
+//15 -- splicing VIDEO PID change enable
+//14:10 -- VIDEO PID FILTER ADDRESS
+// 9 -- PES splicing active (Read Only)
+// 8 -- splicing active (Read Only)
+// 7:0 splicing countdown (Read Only)
+// 31:16 AUDIO PID filter data
+//15 -- splicing AUDIO PID change enable
+//14:10 -- AUDIO PID FILTER ADDRESS
+// 9 -- PES splicing active (Read Only)
+// 8 -- splicing active (Read Only)
+// 7:0 splicing countdown (Read Only)
+// 23:16 M2TS_SKIP_BYTES
+// 15:8 LAST TS PACKAGE BYTE COUNT (Read Only)
+// 7:0 PACKAGE BYTE COUNT (Read Only)
+// 15:0 2 bytes strong sync add to PES
+// bit 15 -- stb_om_ren
+// bit 14:11 -- reserved
+// bit 10:0 -- OM_DATA_RD_ADDR
+// bit 15:0 -- OM_DATA_RD
+// AUTO STOP SETTING for 32 channels
+// 4-nbits per channel
+// when write
+// bit 3 -- set section active
+// bit 2:0 -- auto stop after count (0 means never stop)
+// when read
+// bit 3 -- current active status (1 - active, 0 - stopped )
+// bit 2:0 -- count down to auto stop
+// section 31:24
+// section 23:16
+// section 15:8
+// section 7:0
+// bit 31:0 reset channel status - each bit reset each channel
+// read -- 32 channel status
+// bit 4 -- video_stamp_use_dts
+// bit 3 -- audio_stamp_sync_1_en
+// bit 2 -- audio_stamp_insert_en
+// bit 1 -- video_stamp_sync_1_en
+// bit 0 -- video_stamp_insert_en
+// Write : Bit[4:0] secter filter number for reset
+// Read : select according to output_section_buffer_valid :
+// per bit per section buffer valid status
+// or section_buffer_ignore
+// bit[31:0] - channel_reset_timeout_disable
+// bit[31] - no_match_reset_timeout_disable
+// bit[30:0] input_time_out_int_cnt (0 -- means disable) Wr-setting, Rd-count
+// bit[31:0] - channel_packet_count_disable
+// bit[31] - no_match_packet_count_disable
+// bit[30:0] input_packet_count
+// bit[31:0] channel_record_enable
+// bit[31:0] channel_process_enable
+// bit[31:24] small_sec_size ((n+1) * 256 Bytes)
+// bit[23:16] small_sec_rd_ptr
+// bit[15:8] small_sec_wr_ptr
+// bit[7:2] reserved
+// bit[1] small_sec_wr_ptr_wr_enable
+// bit[0] small_section_enable
+// bit[31:0] small_sec_start_addr
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: REG_LIST_DEMUX_RTL.h
+//
+//
+// Reading file: nna_anakin_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+//========================================================================
+// ANAKIN - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe370000
+// -----------------------------------------------
+#define NNA_ANAKIN_64_0_ST ((0x0000 << 2) + 0xfe370000)
+//Bit 31:0 reserved
+#define NNA_ANAKIN_64_0_ED ((0x03ff << 2) + 0xfe370000)
+//Bit 31:0 reserved
+//========================================================================
+// ANAKIN - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe371000
+// -----------------------------------------------
+#define NNA_ANAKIN_64_1_ST ((0x0000 << 2) + 0xfe371000)
+//Bit 31:0 reserved
+#define NNA_ANAKIN_64_1_ED ((0x03ff << 2) + 0xfe371000)
+//Bit 31:0 reserved
+//
+//========================================================================
+// ANAKIN - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe372000
+// -----------------------------------------------
+#define NNA_ANAKIN_1K_0_ST ((0x0000 << 2) + 0xfe372000)
+//Bit 31:0 reserved
+#define NNA_ANAKIN_1K_0_ED ((0x03ff << 2) + 0xfe372000)
+//Bit 31:0 reserved
+//
+//========================================================================
+// ANAKIN - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe373000
+// -----------------------------------------------
+#define NNA_ANAKIN_1K_1_ST ((0x0000 << 2) + 0xfe373000)
+//Bit 31:0 reserved
+#define NNA_ANAKIN_1K_1_ED ((0x03ff << 2) + 0xfe373000)
+//Bit 31:0 reserved
+//
+//========================================================================
+// ANAKIN - Registers
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe374000
+// -----------------------------------------------
+#define RO_NNA_ANAKIN_0 ((0x0000 << 2) + 0xfe374000)
+//Bit 31: 0 ro_nna0_dbg_bus // unsigned , RO, default = 4
+#define RO_NNA_ANAKIN_1 ((0x0001 << 2) + 0xfe374000)
+//Bit 31: 0 ro_nna1_dbg_bus // unsigned , RO, default = 4
+#define RO_NNA_ANAKIN_2 ((0x0002 << 2) + 0xfe374000)
+//Bit 31: 0 ro_nna2_dbg_bus // unsigned , RO, default = 4
+#define RO_NNA_ANAKIN_3 ((0x0003 << 2) + 0xfe374000)
+//Bit 31: 0 ro_nna3_dbg_bus // unsigned , RO, default = 4 ro_nna_debug
+#define RO_NNA_ANAKIN_EMI ((0x0004 << 2) + 0xfe374000)
+//Bit 31:16 reserved
+//Bit 15: 0 ro_nna_emi // unsigned , RO, default = 0 status
+#define NNA_EMI_CTRL ((0x0005 << 2) + 0xfe374000)
+//Bit 31:28 reg_nna0_emi_fixed // unsigned , RW, default = 0 fixed value nn0
+//Bit 27 reserved
+//Bit 26:25 reg_nna0_emi_lsft // unsigned , RW, default = 2 left shift nna_emi nn0
+//Bit 24 reg_nna0_emi_fix_en // unsigned , RW, default = 0 enable emi_fixed nn0
+//Bit 23:20 reg_nna1_emi_fixed // unsigned , RW, default = 0 fixed value nn1
+//Bit 19 reserved
+//Bit 18:17 reg_nna1_emi_lsft // unsigned , RW, default = 2 left shift nna_emi nn1
+//Bit 16 reg_nna1_emi_fix_en // unsigned , RW, default = 0 enable emi_fixed nn1
+//Bit 15:12 reg_nna2_emi_fixed // unsigned , RW, default = 0 fixed value nn2
+//Bit 11 reserved
+//Bit 10: 9 reg_nna2_emi_lsft // unsigned , RW, default = 2 left shift nna_emi nn2
+//Bit 8 reg_nna2_emi_fix_en // unsigned , RW, default = 0 enable emi_fixed nn2
+//Bit 7: 4 reg_nna3_emi_fixed // unsigned , RW, default = 0 fixed value nn3
+//Bit 3 reserved
+//Bit 2: 1 reg_nna3_emi_lsft // unsigned , RW, default = 2 left shift nna_emi nn3
+//Bit 0 reg_nna3_emi_fix_en // unsigned , RW, default = 0 enable emi_fixed nn3
+#define NNA_ADDR_SEL ((0x0006 << 2) + 0xfe374000)
+//Bit 31:16 reserved
+//Bit 15:14 reg_core0_araddr_sel // unsigned , RW, default = 2
+//Bit 13:12 reg_core1_araddr_sel // unsigned , RW, default = 2
+//Bit 11:10 reg_core2_araddr_sel // unsigned , RW, default = 2
+//Bit 9: 8 reg_core3_araddr_sel // unsigned , RW, default = 2
+//Bit 7: 6 reg_core0_awaddr_sel // unsigned , RW, default = 2
+//Bit 5: 4 reg_core1_awaddr_sel // unsigned , RW, default = 2
+//Bit 3: 2 reg_core2_awaddr_sel // unsigned , RW, default = 2
+//Bit 1: 0 reg_core3_awaddr_sel // unsigned , RW, default = 2
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: nna_anakin_regs.h
+//
+//========================================================================
+// MIPI_DSI_HOST
+//========================================================================
+//
+// Reading file: dsi_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+// MIPI DSI HOST A CONTROLLER Registers 0xfe074000 - 0xfe074fff
+//===========================================================================
+//------------------------------------------------------------------------------
+// DWC IP registers: Synopsys IP, please refer to MIPI DSI HOST Databook
+//------------------------------------------------------------------------------
+//
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe074000
+// -----------------------------------------------
+#define MIPI_DSI_DWC_VERSION_OS ((0x0000 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_PWR_UP_OS ((0x0001 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_CLKMGR_CFG_OS ((0x0002 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_DPI_VCID_OS ((0x0003 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_DPI_COLOR_CODING_OS ((0x0004 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_DPI_CFG_POL_OS ((0x0005 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_DPI_LP_CMD_TIM_OS ((0x0006 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_PCKHDL_CFG_OS ((0x000b << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_GEN_VCID_OS ((0x000c << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_MODE_CFG_OS ((0x000d << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_VID_MODE_CFG_OS ((0x000e << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_VID_PKT_SIZE_OS ((0x000f << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_VID_NUM_CHUNKS_OS ((0x0010 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_VID_NULL_SIZE_OS ((0x0011 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_VID_HSA_TIME_OS ((0x0012 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_VID_HBP_TIME_OS ((0x0013 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_VID_HLINE_TIME_OS ((0x0014 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_VID_VSA_LINES_OS ((0x0015 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_VID_VBP_LINES_OS ((0x0016 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_VID_VFP_LINES_OS ((0x0017 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_VID_VACTIVE_LINES_OS ((0x0018 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_EDPI_CMD_SIZE_OS ((0x0019 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_CMD_MODE_CFG_OS ((0x001a << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_GEN_HDR_OS ((0x001b << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_GEN_PLD_DATA_OS ((0x001c << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_CMD_PKT_STATUS_OS ((0x001d << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_TO_CNT_CFG_OS ((0x001e << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_HS_RD_TO_CNT_OS ((0x001f << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_LP_RD_TO_CNT_OS ((0x0020 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_HS_WR_TO_CNT_OS ((0x0021 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_LP_WR_TO_CNT_OS ((0x0022 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_BTA_TO_CNT_OS ((0x0023 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_SDF_3D_OS ((0x0024 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_LPCLK_CTRL_OS ((0x0025 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_PHY_TMR_LPCLK_CFG_OS ((0x0026 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_PHY_TMR_CFG_OS ((0x0027 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_PHY_RSTZ_OS ((0x0028 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_PHY_IF_CFG_OS ((0x0029 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_PHY_ULPS_CTRL_OS ((0x002a << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_PHY_TX_TRIGGERS_OS ((0x002b << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_PHY_STATUS_OS ((0x002c << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_PHY_TST_CTRL0_OS ((0x002d << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_PHY_TST_CTRL1_OS ((0x002e << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_INT_ST0_OS ((0x002f << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_INT_ST1_OS ((0x0030 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_INT_MSK0_OS ((0x0031 << 2) + 0xfe074000)
+#define MIPI_DSI_DWC_INT_MSK1_OS ((0x0032 << 2) + 0xfe074000)
+//------------------------------------------------------------------------------
+// Top-level registers: AmLogic proprietary
+//------------------------------------------------------------------------------
+#define MIPI_DSI_TOP_SHADOW_HSA_TIME ((0x00e8 << 2) + 0xfe074000)
+#define MIPI_DSI_TOP_SHADOW_HBP_TIME ((0x00e9 << 2) + 0xfe074000)
+#define MIPI_DSI_TOP_SHADOW_HLINE_TIME ((0x00ea << 2) + 0xfe074000)
+#define MIPI_DSI_TOP_SHADOW_VSA_LINES ((0x00eb << 2) + 0xfe074000)
+#define MIPI_DSI_TOP_SHADOW_VBP_LINES ((0x00ec << 2) + 0xfe074000)
+#define MIPI_DSI_TOP_SHADOW_VFP_LINES ((0x00ed << 2) + 0xfe074000)
+#define MIPI_DSI_TOP_SHADOW_VACTIVE_LINES ((0x00ee << 2) + 0xfe074000)
+#define MIPI_DSI_TOP_SHADOW_TIME_CTRL ((0x00ef << 2) + 0xfe074000)
+// 31: 4 Reserved. Default 0.
+// 3 RW ~tim_rst_n: 1=Assert SW reset on mipi_dsi_host_timing block. 0=Release reset. Default 1.
+// 2 RW ~dpi_rst_n: 1=Assert SW reset on mipi_dsi_host_dpi block. 0=Release reset. Default 1.
+// 1 RW ~intr_rst_n: 1=Assert SW reset on mipi_dsi_host_intr block. 0=Release reset. Default 1.
+// 0 RW ~dwc_rst_n: 1=Assert SW reset on IP core. 0=Release reset. Default 1.
+#define MIPI_DSI_TOP_SW_RESET ((0x00f0 << 2) + 0xfe074000)
+// 31: 5 Reserved. Default 0.
+// 4 RW manual_edpihalt: 1=Manual suspend VencL; 0=do not suspend VencL. Default 0.
+// 3 RW auto_edpihalt_en: 1=Enable IP's edpihalt signal to suspend VencL; 0=IP's edpihalt signal does not affect VencL. Default 0.
+// 2 RW clock_freerun: Apply to auto-clock gate only. Default 0.
+// 0=Default, use auto-clock gating to save power;
+// 1=use free-run clock, disable auto-clock gating, for debug mode.
+// 1 RW enable_pixclk: A manual clock gate option, due to DWC IP does not have auto-clock gating. 1=Enable pixclk. Default 0.
+// 0 RW enable_sysclk: A manual clock gate option, due to DWC IP does not have auto-clock gating. 1=Enable sysclk. Default 0.
+#define MIPI_DSI_TOP_CLK_CNTL ((0x00f1 << 2) + 0xfe074000)
+// 31:27 Reserved. Default 0.
+// 26 RW de_dpi_pol: 1= Invert DE polarity from mipi_dsi_host_dpi. Default 0.
+// 25 RW hsync_dpi_pol: 1= Invert HS polarity from mipi_dsi_host_dpi. Default 0.
+// 24 RW vsync_dpi_pol: 1= Invert VS polarity from mipi_dsi_host_dpi. Default 0.
+// 23:20 RW dpi_color_mode: Define DPI pixel format. Default 0.
+// 0=16-bit RGB565 config 1;
+// 1=16-bit RGB565 config 2;
+// 2=16-bit RGB565 config 3;
+// 3=18-bit RGB666 config 1;
+// 4=18-bit RGB666 config 2;
+// 5=24-bit RGB888;
+// 6=20-bit YCbCr 4:2:2;
+// 7=24-bit YCbCr 4:2:2;
+// 8=16-bit YCbCr 4:2:2;
+// 9=30-bit RGB;
+// 10=36-bit RGB;
+// 11=12-bit YCbCr 4:2:0.
+// 19 Reserved. Default 0.
+// 18:16 RW in_color_mode: Define VENC data width. Default 0.
+// 0=30-bit pixel;
+// 1=24-bit pixel;
+// 2=18-bit pixel, RGB666;
+// 3=16-bit pixel, RGB565.
+// 15:14 RW chroma_subsample: Define method of chroma subsampling. Default 0.
+// Applicable to YUV422 or YUV420 only.
+// 0=Use even pixel's chroma;
+// 1=Use odd pixel's chroma;
+// 2=Use averaged value between even and odd pair.
+// 13:12 RW comp2_sel: Select which component to be Cr or B: 0=comp0; 1=comp1; 2=comp2. Default 2.
+// 11:10 RW comp1_sel: Select which component to be Cb or G: 0=comp0; 1=comp1; 2=comp2. Default 1.
+// 9: 8 RW comp0_sel: Select which component to be Y or R: 0=comp0; 1=comp1; 2=comp2. Default 0.
+// 7 Reserved. Default 0.
+// 6 RW de_venc_pol: 1= Invert DE polarity from VENC. Default 0.
+// 5 RW hsync_venc_pol: 1= Invert HS polarity from VENC. Default 0.
+// 4 RW vsync_venc_pol: 1= Invert VS polarity from VENC. Default 0.
+// 3 RW dpicolorm: Signal to IP. Default 0.
+// 2 RW dpishutdn: Signal to IP. Default 0.
+// 1 Reserved. Default 0.
+// 0 Reserved. Default 0.
+#define MIPI_DSI_TOP_CNTL ((0x00f2 << 2) + 0xfe074000)
+// 31:16 Reserved. Default 0.
+// 15: 8 RW suspend_frame_rate: Define rate of timed-suspend. Default 0.
+// 0=Execute suspend every frame; 1=Every other frame; ...; 255=Every 256 frame.
+// 7: 4 Reserved. Default 0.
+// 3 RW disable suspend venc: 1=don`t support suspend VencL. 0=support suspend venc Default 0.
+// 2 RW timed_suspend_en: 1=Enable timed suspend VencL. 0=Disable timed suspend. Default 0.
+// 1 RW manual_suspend_en: 1=Enable manual suspend VencL. 1=Cancel manual suspend VencL. Default 0.
+// 0 RW suspend_on_edpihalt:1=Enable IP's edpihalt signal to suspend VencL; 0=IP's edpihalt signal does not affect VencL. Default 1.
+#define MIPI_DSI_TOP_SUSPEND_CNTL ((0x00f3 << 2) + 0xfe074000)
+// 31:29 Reserved. Default 0.
+// 28:16 RW suspend_line_end: Define timed-suspend region. Suspend from [pix_start,line_start] to [pix_end,line_end]. Default 0.
+// 15:13 Reserved. Default 0.
+// 12: 0 RW suspend_line_start: Define timed-suspend region. Suspend from [pix_start,line_start] to [pix_end,line_end]. Default 0.
+#define MIPI_DSI_TOP_SUSPEND_LINE ((0x00f4 << 2) + 0xfe074000)
+// 31:29 Reserved. Default 0.
+// 28:16 RW suspend_pix_end: Define timed-suspend region. Suspend from [pix_start,line_start] to [pix_end,line_end]. Default 0.
+// 15:13 Reserved. Default 0.
+// 12: 0 RW suspend_pix_start: Define timed-suspend region. Suspend from [pix_start,line_start] to [pix_end,line_end]. Default 0.
+#define MIPI_DSI_TOP_SUSPEND_PIX ((0x00f5 << 2) + 0xfe074000)
+// 31:20 Reserved. Default 0.
+// 19:10 RW meas_vsync: Control on measuring Host Controller's vsync. Default 0.
+// [ 19] meas_en: 1=Enable measurement
+// [ 18] accum_meas_en: 0=meas_count is cleared at the end of each measure;
+// 1=meas_count is accumulated at the end of each measure.
+// [17:10] vsync_span: Define the duration of a measure is to last for how many Vsyncs.
+// 9: 0 RW meas_edpite: Control on measuring Display Slave's edpite. Default 0.
+// [ 9] meas_en: 1=Enable measurement
+// [ 8] accum_meas_en: 0=meas_count is cleared at the end of each measure;
+// 1=meas_count is accumulated at the end of each measure.
+// [ 7: 0] edpite_span: Define the duration of a measure is to last for how many edpite.
+#define MIPI_DSI_TOP_MEAS_CNTL ((0x00f6 << 2) + 0xfe074000)
+// 31 R stat_edpihalt: status of edpihalt signal from IP. Default 0.
+// 30:29 Reserved. Default 0.
+// 28:16 R stat_te_line: Snapshot of Host's line position at edpite. Default 0.
+// 15:13 Reserved. Default 0.
+// 12: 0 R stat_te_pix: Snapshot of Host's pixel position at edpite. Default 0.
+#define MIPI_DSI_TOP_STAT ((0x00f7 << 2) + 0xfe074000)
+// To measure display slave's frame rate, we can use a reference clock to measure the duration of one of more edpite pulse(s).
+// Measurement control is by register MIPI_DSI_TOP_MEAS_CNTL bit[9:0].
+// Reference clock comes from clk_rst_tst.cts_dsi_meas_clk, and is defined by HIU register HHI_VDIN_MEAS_CLK_CNTL bit[23:12].
+// Mesurement result is in MIPI_DSI_TOP_MEAS_STAT_TE0 and MIPI_DSI_TOP_MEAS_STAT_TE1, as below:
+// edpite_meas_count[47:0]: Number of reference clock cycles counted during one measure period (non-incremental measure), or
+// during all measure periods so far (incremental measure).
+// edpite_meas_count_n[3:0]:Number of measure periods has been done. Number can wrap over.
+//
+// 31: 0 R edpite_meas_count[31:0]. Default 0.
+#define MIPI_DSI_TOP_MEAS_STAT_TE0 ((0x00f8 << 2) + 0xfe074000)
+// 19:16 R edpite_meas_count_n. Default 0.
+// 15: 0 R edpite_meas_count[47:32]. Default 0.
+#define MIPI_DSI_TOP_MEAS_STAT_TE1 ((0x00f9 << 2) + 0xfe074000)
+// To measure Host's frame rate, we can use a reference clock to measure the duration of one of more Vsync pulse(s).
+// Measurement control is by register MIPI_DSI_TOP_MEAS_CNTL bit[19:10].
+// Reference clock comes from clk_rst_tst.cts_dsi_meas_clk, and is defined by HIU register HHI_VDIN_MEAS_CLK_CNTL bit[23:12].
+// Mesurement result is in MIPI_DSI_TOP_MEAS_STAT_VS0 and MIPI_DSI_TOP_MEAS_STAT_VS1, as below:
+// vsync_meas_count[47:0]: Number of reference clock cycles counted during one measure period (non-incremental measure), or
+// during all measure periods so far (incremental measure).
+// vsync_meas_count_n[3:0]: Number of measure periods has been done. Number can wrap over.
+//
+// 31: 0 R vsync_meas_count[31:0]. Default 0.
+#define MIPI_DSI_TOP_MEAS_STAT_VS0 ((0x00fa << 2) + 0xfe074000)
+// 19:16 R vsync_meas_count_n. Default 0.
+// 15: 0 R vsync_meas_count[47:32]. Default 0.
+#define MIPI_DSI_TOP_MEAS_STAT_VS1 ((0x00fb << 2) + 0xfe074000)
+// 31:16 RW intr_stat/clr. For each bit, read as this interrupt level status, write 1 to clear. Default 0.
+// Note: To clear the interrupt level, simply write 1 to the specific bit, no need to write 0 afterwards.
+// [31:22] Reserved
+// [ 21] stat/clr of EOF interrupt
+// [ 20] stat/clr of de_fall interrupt
+// [ 19] stat/clr of de_rise interrupt
+// [ 18] stat/clr of vs_fall interrupt
+// [ 17] stat/clr of vs_rise interrupt
+// [ 16] stat/clr of dwc_edpite interrupt
+// 15: 0 RW intr_enable. For each bit, 1=enable this interrupt, 0=disable. Default 0.
+// [15: 6] Reserved
+// [ 5] EOF (End_Of_Field) interrupt
+// [ 4] de_fall interrupt
+// [ 3] de_rise interrupt
+// [ 2] vs_fall interrupt
+// [ 1] vs_rise interrupt
+// [ 0] dwc_edpite interrupt
+#define MIPI_DSI_TOP_INTR_CNTL_STAT ((0x00fc << 2) + 0xfe074000)
+// 31: 2 Reserved. Default 0.
+// 1: 0 RW mem_pd. Default 3.
+#define MIPI_DSI_TOP_MEM_PD ((0x00fd << 2) + 0xfe074000)
+//===========================================================================
+// MIPI DSI HOST B CONTROLLER Registers 0xfe072000 - 0xfe072fff
+//===========================================================================
+//------------------------------------------------------------------------------
+// DWC IP registers: Synopsys IP, please refer to MIPI DSI HOST Databook
+//------------------------------------------------------------------------------
+//
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe072000
+// -----------------------------------------------
+#define MIPI_DSI_B_DWC_VERSION_OS ((0x0000 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_PWR_UP_OS ((0x0001 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_CLKMGR_CFG_OS ((0x0002 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_DPI_VCID_OS ((0x0003 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_DPI_COLOR_CODING_OS ((0x0004 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_DPI_CFG_POL_OS ((0x0005 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_DPI_LP_CMD_TIM_OS ((0x0006 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_PCKHDL_CFG_OS ((0x000b << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_GEN_VCID_OS ((0x000c << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_MODE_CFG_OS ((0x000d << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_VID_MODE_CFG_OS ((0x000e << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_VID_PKT_SIZE_OS ((0x000f << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_VID_NUM_CHUNKS_OS ((0x0010 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_VID_NULL_SIZE_OS ((0x0011 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_VID_HSA_TIME_OS ((0x0012 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_VID_HBP_TIME_OS ((0x0013 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_VID_HLINE_TIME_OS ((0x0014 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_VID_VSA_LINES_OS ((0x0015 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_VID_VBP_LINES_OS ((0x0016 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_VID_VFP_LINES_OS ((0x0017 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_VID_VACTIVE_LINES_OS ((0x0018 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_EDPI_CMD_SIZE_OS ((0x0019 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_CMD_MODE_CFG_OS ((0x001a << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_GEN_HDR_OS ((0x001b << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_GEN_PLD_DATA_OS ((0x001c << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_CMD_PKT_STATUS_OS ((0x001d << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_TO_CNT_CFG_OS ((0x001e << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_HS_RD_TO_CNT_OS ((0x001f << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_LP_RD_TO_CNT_OS ((0x0020 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_HS_WR_TO_CNT_OS ((0x0021 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_LP_WR_TO_CNT_OS ((0x0022 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_BTA_TO_CNT_OS ((0x0023 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_SDF_3D_OS ((0x0024 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_LPCLK_CTRL_OS ((0x0025 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_PHY_TMR_LPCLK_CFG_OS ((0x0026 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_PHY_TMR_CFG_OS ((0x0027 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_PHY_RSTZ_OS ((0x0028 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_PHY_IF_CFG_OS ((0x0029 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_PHY_ULPS_CTRL_OS ((0x002a << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_PHY_TX_TRIGGERS_OS ((0x002b << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_PHY_STATUS_OS ((0x002c << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_PHY_TST_CTRL0_OS ((0x002d << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_PHY_TST_CTRL1_OS ((0x002e << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_INT_ST0_OS ((0x002f << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_INT_ST1_OS ((0x0030 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_INT_MSK0_OS ((0x0031 << 2) + 0xfe072000)
+#define MIPI_DSI_B_DWC_INT_MSK1_OS ((0x0032 << 2) + 0xfe072000)
+//------------------------------------------------------------------------------
+// Top-level registers: AmLogic proprietary
+//------------------------------------------------------------------------------
+#define MIPI_DSI_B_TOP_SHADOW_HSA_TIME ((0x00e8 << 2) + 0xfe072000)
+#define MIPI_DSI_B_TOP_SHADOW_HBP_TIME ((0x00e9 << 2) + 0xfe072000)
+#define MIPI_DSI_B_TOP_SHADOW_HLINE_TIME ((0x00ea << 2) + 0xfe072000)
+#define MIPI_DSI_B_TOP_SHADOW_VSA_LINES ((0x00eb << 2) + 0xfe072000)
+#define MIPI_DSI_B_TOP_SHADOW_VBP_LINES ((0x00ec << 2) + 0xfe072000)
+#define MIPI_DSI_B_TOP_SHADOW_VFP_LINES ((0x00ed << 2) + 0xfe072000)
+#define MIPI_DSI_B_TOP_SHADOW_VACTIVE_LINES ((0x00ee << 2) + 0xfe072000)
+#define MIPI_DSI_B_TOP_SHADOW_TIME_CTRL ((0x00ef << 2) + 0xfe072000)
+// 31: 4 Reserved. Default 0.
+// 3 RW ~tim_rst_n: 1=Assert SW reset on mipi_dsi_host_timing block. 0=Release reset. Default 1.
+// 2 RW ~dpi_rst_n: 1=Assert SW reset on mipi_dsi_host_dpi block. 0=Release reset. Default 1.
+// 1 RW ~intr_rst_n: 1=Assert SW reset on mipi_dsi_host_intr block. 0=Release reset. Default 1.
+// 0 RW ~dwc_rst_n: 1=Assert SW reset on IP core. 0=Release reset. Default 1.
+#define MIPI_DSI_B_TOP_SW_RESET ((0x00f0 << 2) + 0xfe072000)
+// 31: 5 Reserved. Default 0.
+// 4 RW manual_edpihalt: 1=Manual suspend VencL; 0=do not suspend VencL. Default 0.
+// 3 RW auto_edpihalt_en: 1=Enable IP's edpihalt signal to suspend VencL; 0=IP's edpihalt signal does not affect VencL. Default 0.
+// 2 RW clock_freerun: Apply to auto-clock gate only. Default 0.
+// 0=Default, use auto-clock gating to save power;
+// 1=use free-run clock, disable auto-clock gating, for debug mode.
+// 1 RW enable_pixclk: A manual clock gate option, due to DWC IP does not have auto-clock gating. 1=Enable pixclk. Default 0.
+// 0 RW enable_sysclk: A manual clock gate option, due to DWC IP does not have auto-clock gating. 1=Enable sysclk. Default 0.
+#define MIPI_DSI_B_TOP_CLK_CNTL ((0x00f1 << 2) + 0xfe072000)
+// 31:27 Reserved. Default 0.
+// 26 RW de_dpi_pol: 1= Invert DE polarity from mipi_dsi_host_dpi. Default 0.
+// 25 RW hsync_dpi_pol: 1= Invert HS polarity from mipi_dsi_host_dpi. Default 0.
+// 24 RW vsync_dpi_pol: 1= Invert VS polarity from mipi_dsi_host_dpi. Default 0.
+// 23:20 RW dpi_color_mode: Define DPI pixel format. Default 0.
+// 0=16-bit RGB565 config 1;
+// 1=16-bit RGB565 config 2;
+// 2=16-bit RGB565 config 3;
+// 3=18-bit RGB666 config 1;
+// 4=18-bit RGB666 config 2;
+// 5=24-bit RGB888;
+// 6=20-bit YCbCr 4:2:2;
+// 7=24-bit YCbCr 4:2:2;
+// 8=16-bit YCbCr 4:2:2;
+// 9=30-bit RGB;
+// 10=36-bit RGB;
+// 11=12-bit YCbCr 4:2:0.
+// 19 Reserved. Default 0.
+// 18:16 RW in_color_mode: Define VENC data width. Default 0.
+// 0=30-bit pixel;
+// 1=24-bit pixel;
+// 2=18-bit pixel, RGB666;
+// 3=16-bit pixel, RGB565.
+// 15:14 RW chroma_subsample: Define method of chroma subsampling. Default 0.
+// Applicable to YUV422 or YUV420 only.
+// 0=Use even pixel's chroma;
+// 1=Use odd pixel's chroma;
+// 2=Use averaged value between even and odd pair.
+// 13:12 RW comp2_sel: Select which component to be Cr or B: 0=comp0; 1=comp1; 2=comp2. Default 2.
+// 11:10 RW comp1_sel: Select which component to be Cb or G: 0=comp0; 1=comp1; 2=comp2. Default 1.
+// 9: 8 RW comp0_sel: Select which component to be Y or R: 0=comp0; 1=comp1; 2=comp2. Default 0.
+// 7 Reserved. Default 0.
+// 6 RW de_venc_pol: 1= Invert DE polarity from VENC. Default 0.
+// 5 RW hsync_venc_pol: 1= Invert HS polarity from VENC. Default 0.
+// 4 RW vsync_venc_pol: 1= Invert VS polarity from VENC. Default 0.
+// 3 RW dpicolorm: Signal to IP. Default 0.
+// 2 RW dpishutdn: Signal to IP. Default 0.
+// 1 Reserved. Default 0.
+// 0 Reserved. Default 0.
+#define MIPI_DSI_B_TOP_CNTL ((0x00f2 << 2) + 0xfe072000)
+// 31:16 Reserved. Default 0.
+// 15: 8 RW suspend_frame_rate: Define rate of timed-suspend. Default 0.
+// 0=Execute suspend every frame; 1=Every other frame; ...; 255=Every 256 frame.
+// 7: 4 Reserved. Default 0.
+// 3 RW disable suspend venc: 1=don`t support suspend VencL. 0=support suspend venc Default 0.
+// 2 RW timed_suspend_en: 1=Enable timed suspend VencL. 0=Disable timed suspend. Default 0.
+// 1 RW manual_suspend_en: 1=Enable manual suspend VencL. 1=Cancel manual suspend VencL. Default 0.
+// 0 RW suspend_on_edpihalt:1=Enable IP's edpihalt signal to suspend VencL; 0=IP's edpihalt signal does not affect VencL. Default 1.
+#define MIPI_DSI_B_TOP_SUSPEND_CNTL ((0x00f3 << 2) + 0xfe072000)
+// 31:29 Reserved. Default 0.
+// 28:16 RW suspend_line_end: Define timed-suspend region. Suspend from [pix_start,line_start] to [pix_end,line_end]. Default 0.
+// 15:13 Reserved. Default 0.
+// 12: 0 RW suspend_line_start: Define timed-suspend region. Suspend from [pix_start,line_start] to [pix_end,line_end]. Default 0.
+#define MIPI_DSI_B_TOP_SUSPEND_LINE ((0x00f4 << 2) + 0xfe072000)
+// 31:29 Reserved. Default 0.
+// 28:16 RW suspend_pix_end: Define timed-suspend region. Suspend from [pix_start,line_start] to [pix_end,line_end]. Default 0.
+// 15:13 Reserved. Default 0.
+// 12: 0 RW suspend_pix_start: Define timed-suspend region. Suspend from [pix_start,line_start] to [pix_end,line_end]. Default 0.
+#define MIPI_DSI_B_TOP_SUSPEND_PIX ((0x00f5 << 2) + 0xfe072000)
+// 31:20 Reserved. Default 0.
+// 19:10 RW meas_vsync: Control on measuring Host Controller's vsync. Default 0.
+// [ 19] meas_en: 1=Enable measurement
+// [ 18] accum_meas_en: 0=meas_count is cleared at the end of each measure;
+// 1=meas_count is accumulated at the end of each measure.
+// [17:10] vsync_span: Define the duration of a measure is to last for how many Vsyncs.
+// 9: 0 RW meas_edpite: Control on measuring Display Slave's edpite. Default 0.
+// [ 9] meas_en: 1=Enable measurement
+// [ 8] accum_meas_en: 0=meas_count is cleared at the end of each measure;
+// 1=meas_count is accumulated at the end of each measure.
+// [ 7: 0] edpite_span: Define the duration of a measure is to last for how many edpite.
+#define MIPI_DSI_B_TOP_MEAS_CNTL ((0x00f6 << 2) + 0xfe072000)
+// 31 R stat_edpihalt: status of edpihalt signal from IP. Default 0.
+// 30:29 Reserved. Default 0.
+// 28:16 R stat_te_line: Snapshot of Host's line position at edpite. Default 0.
+// 15:13 Reserved. Default 0.
+// 12: 0 R stat_te_pix: Snapshot of Host's pixel position at edpite. Default 0.
+#define MIPI_DSI_B_TOP_STAT ((0x00f7 << 2) + 0xfe072000)
+// To measure display slave's frame rate, we can use a reference clock to measure the duration of one of more edpite pulse(s).
+// Measurement control is by register MIPI_DSI_B_TOP_MEAS_CNTL bit[9:0].
+// Reference clock comes from clk_rst_tst.cts_dsi_meas_clk, and is defined by HIU register HHI_VDIN_MEAS_CLK_CNTL bit[23:12].
+// Mesurement result is in MIPI_DSI_B_TOP_MEAS_STAT_TE0 and MIPI_DSI_B_TOP_MEAS_STAT_TE1, as below:
+// edpite_meas_count[47:0]: Number of reference clock cycles counted during one measure period (non-incremental measure), or
+// during all measure periods so far (incremental measure).
+// edpite_meas_count_n[3:0]:Number of measure periods has been done. Number can wrap over.
+//
+// 31: 0 R edpite_meas_count[31:0]. Default 0.
+#define MIPI_DSI_B_TOP_MEAS_STAT_TE0 ((0x00f8 << 2) + 0xfe072000)
+// 19:16 R edpite_meas_count_n. Default 0.
+// 15: 0 R edpite_meas_count[47:32]. Default 0.
+#define MIPI_DSI_B_TOP_MEAS_STAT_TE1 ((0x00f9 << 2) + 0xfe072000)
+// To measure Host's frame rate, we can use a reference clock to measure the duration of one of more Vsync pulse(s).
+// Measurement control is by register MIPI_DSI_B_TOP_MEAS_CNTL bit[19:10].
+// Reference clock comes from clk_rst_tst.cts_dsi_meas_clk, and is defined by HIU register HHI_VDIN_MEAS_CLK_CNTL bit[23:12].
+// Mesurement result is in MIPI_DSI_B_TOP_MEAS_STAT_VS0 and MIPI_DSI_B_TOP_MEAS_STAT_VS1, as below:
+// vsync_meas_count[47:0]: Number of reference clock cycles counted during one measure period (non-incremental measure), or
+// during all measure periods so far (incremental measure).
+// vsync_meas_count_n[3:0]: Number of measure periods has been done. Number can wrap over.
+//
+// 31: 0 R vsync_meas_count[31:0]. Default 0.
+#define MIPI_DSI_B_TOP_MEAS_STAT_VS0 ((0x00fa << 2) + 0xfe072000)
+// 19:16 R vsync_meas_count_n. Default 0.
+// 15: 0 R vsync_meas_count[47:32]. Default 0.
+#define MIPI_DSI_B_TOP_MEAS_STAT_VS1 ((0x00fb << 2) + 0xfe072000)
+// 31:16 RW intr_stat/clr. For each bit, read as this interrupt level status, write 1 to clear. Default 0.
+// Note: To clear the interrupt level, simply write 1 to the specific bit, no need to write 0 afterwards.
+// [31:22] Reserved
+// [ 21] stat/clr of EOF interrupt
+// [ 20] stat/clr of de_fall interrupt
+// [ 19] stat/clr of de_rise interrupt
+// [ 18] stat/clr of vs_fall interrupt
+// [ 17] stat/clr of vs_rise interrupt
+// [ 16] stat/clr of dwc_edpite interrupt
+// 15: 0 RW intr_enable. For each bit, 1=enable this interrupt, 0=disable. Default 0.
+// [15: 6] Reserved
+// [ 5] EOF (End_Of_Field) interrupt
+// [ 4] de_fall interrupt
+// [ 3] de_rise interrupt
+// [ 2] vs_fall interrupt
+// [ 1] vs_rise interrupt
+// [ 0] dwc_edpite interrupt
+#define MIPI_DSI_B_TOP_INTR_CNTL_STAT ((0x00fc << 2) + 0xfe072000)
+// 31: 2 Reserved. Default 0.
+// 1: 0 RW mem_pd. Default 3.
+#define MIPI_DSI_B_TOP_MEM_PD ((0x00fd << 2) + 0xfe072000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dsi_regs.h
+//
+//========================================================================
+// MIPI_ISP
+//========================================================================
+//
+// Reading file: mipi_isp.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//========================================================================
+// MIPI_ISP adapt fe0
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b0000
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP adapt fe1
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b0400
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP adapt fe2
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b0800
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP adapt fe3
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b0c00
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP adapt cfg
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b1000
+// -----------------------------------------------
+#define MIPI_ADAPT_DDR_RD0_CNTL0 ((0x0000 << 2) + 0xfe3b1000)
+//Bit 31 ,frame_rd_start ,default = 0 ,frame_rd_start ,pluse,one cycle
+//Bit 30 ,reserved
+//Bit 29:28 ,burst_type ,default = 0 ,burst_type
+//Bit 27:26 ,reg_sample_sel ,default = 0 ,reg_sample_sel
+//Bit 25 ,soft_load ,default = 0 ,soft_load
+//Bit 24 ,continue_mode ,default = 0 ,continue_mode
+//Bit 23 ,dol_mode ,default = 0 ,dol_mode
+//Bit 22 ,pingpong_mode ,default = 0 ,pingpong_mode
+//Bit 21 ,dol_time_out_en ,default = 0 ,dol_time_out_en
+//Bit 20 ,frame_wr_done_sel ,default = 0 ,frame_wr_done_sel
+//Bit 19 ,line_wr_done_sel ,default = 0 ,line_wr_done_sel
+//Bit 18 ,dol_frame_end_en ,default = 0 ,dol_frame_end_en
+//Bit 17 ,dol_vblank_clr_sel ,default = 0 ,dol_vblank_clr_sel
+//Bit 16 ,reserved
+//Bit 15:14 ,dol_time_tick_sel ,default = 0 ,dol_time_tick_sel
+//Bit 13:4 ,line_stride ,default = 0 ,line_stride
+//Bit 3:2 ,lbuf_soft_rst_sel ,default = 0 ,lbuf_soft_rst_sel
+//Bit 1 ,frame_loop_enable ,default = 0 ,frame_loop_enable
+//Bit 0 ,enable ,default = 0 ,enable
+#define MIPI_ADAPT_DDR_RD0_CNTL1 ((0x0001 << 2) + 0xfe3b1000)
+//Bit 31:30 ,port_sel ,default = 0 ,port_sel
+//Bit 29 ,frame_vs_rst_en ,default = 0 ,frame_vs_rst_en
+//Bit 28:16 ,line_number ,default = 0 ,line_number
+//Bit 15:12 ,dol_line_threshold ,default = 0 ,dol_line_threshold
+//Bit 11:10 ,frame_vs_rst_sel ,default = 0 ,frame_vs_rst_sel
+//Bit 9:0 ,line_size ,default = 0 ,line_size
+#define MIPI_ADAPT_DDR_RD0_CNTL2 ((0x0002 << 2) + 0xfe3b1000)
+//Bit 31:0 ,frame_base_address_0 ,default = 0 ,frame_base_address_0
+#define MIPI_ADAPT_DDR_RD0_CNTL3 ((0x0003 << 2) + 0xfe3b1000)
+//Bit 31:0 ,frame_base_address_1 ,default = 0 ,frame_base_address_1
+#define MIPI_ADAPT_DDR_RD0_CNTL4 ((0x0004 << 2) + 0xfe3b1000)
+//Bit 31:13 ,dol_time_out ,default = 0 ,dol_time_out
+//Bit 12:0 ,line_threshold ,default = 0 ,line_threshold
+#define MIPI_ADAPT_DDR_RD0_CNTL5 ((0x0005 << 2) + 0xfe3b1000)
+//Bit 31:0 ,frame_end_address_0 ,default = 0 ,frame_end_address_0
+#define MIPI_ADAPT_DDR_RD0_CNTL6 ((0x0006 << 2) + 0xfe3b1000)
+//Bit 31:0 ,frame_end_address_1 ,default = 0 ,frame_end_address_1
+#define MIPI_ADAPT_DDR_RD0_UGT_CNTL0 ((0x0007 << 2) + 0xfe3b1000)
+//Bit 31: 8, reserved
+//Bit 7: 4, reg_rd0_qos_th_val ,default = 0,reg_rd0_qos_th_val
+//Bit 3: 0, reg_rd0_qos_default_val ,default = 0,reg_rd0_qos_default_val
+#define MIPI_ADAPT_DDR_RD0_UGT_CNTL1 ((0x0008 << 2) + 0xfe3b1000)
+//Bit 31 , reg_rd0_qos_auto_en ,default = 0,reg_rd0_qos_auto_en
+//Bit 30:16, reg_rd0_qos_th1 ,default = 0,reg_rd0_qos_th1
+//Bit 15 ,reserved
+//Bit 14: 0, reg_rd0_qos_th0 ,default = 0,reg_rd0_qos_th0
+#define MIPI_ADAPT_DDR_RD0_ST0 ((0x000a << 2) + 0xfe3b1000)
+//Bit 31:0 ,mipi_adapt_ddr_rd0_st0 ,default = 0 ,mipi_adapt_ddr_rd0_st0
+#define MIPI_ADAPT_DDR_RD0_ST1 ((0x000b << 2) + 0xfe3b1000)
+//Bit 31:0 ,mipi_adapt_ddr_rd0_st1 ,default = 0 ,mipi_adapt_ddr_rd0_st1
+#define MIPI_ADAPT_DDR_RD0_ST2 ((0x000c << 2) + 0xfe3b1000)
+//Bit 31:0 ,mipi_adapt_ddr_rd0_st2 ,default = 0 ,mipi_adapt_ddr_rd0_st2
+#define MIPI_ADAPT_DDR_RD0_UGT_ST ((0x000d << 2) + 0xfe3b1000)
+//Bit 31: 0, reg_rd0_qos_st ,default = 0 ,RO
+#define MIPI_ADAPT_DDR_RD1_CNTL0 ((0x0010 << 2) + 0xfe3b1000)
+//Bit 31 ,frame_rd_start ,default = 0 ,frame_rd_start ,pluse,one cycle
+//Bit 30 ,reserved
+//Bit 29:28 ,burst_type ,default = 0 ,burst_type
+//Bit 27:26 ,reg_sample_sel ,default = 0 ,reg_sample_sel
+//Bit 25 ,soft_load ,default = 0 ,soft_load
+//Bit 24 ,continue_mode ,default = 0 ,continue_mode
+//Bit 23 ,dol_mode ,default = 0 ,dol_mode
+//Bit 22 ,pingpong_mode ,default = 0 ,pingpong_mode
+//Bit 21 ,dol_time_out_en ,default = 0 ,dol_time_out_en
+//Bit 20 ,frame_wr_done_sel ,default = 0 ,frame_wr_done_sel
+//Bit 19 ,line_wr_done_sel ,default = 0 ,line_wr_done_sel
+//Bit 18 ,dol_frame_end_en ,default = 0 ,dol_frame_end_en
+//Bit 17 ,dol_vblank_clr_sel ,default = 0 ,dol_vblank_clr_sel
+//Bit 16 ,reserved
+//Bit 15:14 ,dol_time_tick_sel ,default = 0 ,dol_time_tick_sel
+//Bit 13:4 ,line_stride ,default = 0 ,line_stride
+//Bit 3:2 ,lbuf_soft_rst_sel ,default = 0 ,lbuf_soft_rst_sel
+//Bit 1 ,frame_loop_enable ,default = 0 ,frame_loop_enable
+//Bit 0 ,enable ,default = 0 ,enable
+#define MIPI_ADAPT_DDR_RD1_CNTL1 ((0x0011 << 2) + 0xfe3b1000)
+//Bit 31:30 ,port_sel ,default = 0 ,port_sel
+//Bit 29 ,frame_vs_rst_en ,default = 0 ,frame_vs_rst_en
+//Bit 28:16 ,line_number ,default = 0 ,line_number
+//Bit 15:12 ,dol_line_threshold ,default = 0 ,dol_line_threshold
+//Bit 11:10 ,frame_vs_rst_sel ,default = 0 ,frame_vs_rst_sel
+//Bit 9:0 ,line_size ,default = 0 ,line_size
+#define MIPI_ADAPT_DDR_RD1_CNTL2 ((0x0012 << 2) + 0xfe3b1000)
+//Bit 31:0 ,frame_base_address_0 ,default = 0 ,frame_base_address_0
+#define MIPI_ADAPT_DDR_RD1_CNTL3 ((0x0013 << 2) + 0xfe3b1000)
+//Bit 31:0 ,frame_base_address_1 ,default = 0 ,frame_base_address_1
+#define MIPI_ADAPT_DDR_RD1_CNTL4 ((0x0014 << 2) + 0xfe3b1000)
+//Bit 31:13 ,dol_time_out ,default = 0 ,dol_time_out
+//Bit 12:0 ,line_threshold ,default = 0 ,line_threshold
+#define MIPI_ADAPT_DDR_RD1_CNTL5 ((0x0015 << 2) + 0xfe3b1000)
+//Bit 31:0 ,frame_end_address_0 ,default = 0 ,frame_end_address_0
+#define MIPI_ADAPT_DDR_RD1_CNTL6 ((0x0016 << 2) + 0xfe3b1000)
+//Bit 31:0 ,frame_end_address_1 ,default = 0 ,frame_end_address_1
+#define MIPI_ADAPT_DDR_RD1_UGT_CNTL0 ((0x0017 << 2) + 0xfe3b1000)
+//Bit 31: 8, reserved
+//Bit 7: 4, reg_rd1_qos_th_val ,default = 0,reg_rd1_qos_th_val
+//Bit 3: 0, reg_rd1_qos_default_val ,default = 0,reg_rd1_qos_default_val
+#define MIPI_ADAPT_DDR_RD1_UGT_CNTL1 ((0x0018 << 2) + 0xfe3b1000)
+//Bit 31 , reg_rd1_qos_auto_en ,default = 0,reg_rd1_qos_auto_en
+//Bit 30:16, reg_rd1_qos_th1 ,default = 0,reg_rd1_qos_th1
+//Bit 15 ,reserved
+//Bit 14: 0, reg_rd1_qos_th0 ,default = 0,reg_rd1_qos_th0
+#define MIPI_ADAPT_DDR_RD1_ST0 ((0x001a << 2) + 0xfe3b1000)
+//Bit 31:0 ,mipi_adapt_ddr_rd1_st1 ,default = 0 ,mipi_adapt_ddr_rd1_st1
+#define MIPI_ADAPT_DDR_RD1_ST1 ((0x001b << 2) + 0xfe3b1000)
+//Bit 31:0 ,mipi_adapt_ddr_rd1_st2 ,default = 0 ,mipi_adapt_ddr_rd1_st2
+#define MIPI_ADAPT_DDR_RD1_ST2 ((0x001c << 2) + 0xfe3b1000)
+//Bit 31:0 ,mipi_adapt_ddr_rd1_st2 ,default = 0 ,mipi_adapt_ddr_rd1_st2
+#define MIPI_ADAPT_DDR_RD1_UGT_ST ((0x001d << 2) + 0xfe3b1000)
+//Bit 31: 0, reg_rd1_qos_st ,default = 0 ,RO
+#define MIPI_ADAPT_PIXEL0_CNTL0 ((0x0020 << 2) + 0xfe3b1000)
+//Bit 31 ,start_en ,default = 0 ,start_en ,pluse,one cycle
+//Bit 30 ,soft_load ,default = 0 ,soft_load ,pluse,one cycle
+//Bit 29:26 ,reserved
+//Bit 25:20 ,data_type ,default = 0 ,data_type
+//Bit 19:18 ,reserved
+//Bit 17:16 ,data_mode ,default = 0 ,data_mode
+//Bit 15 ,reserved
+//Bit 14 ,color_expand ,default = 0 ,color_expand
+//Bit 13 ,reserved
+//Bit 12:0 ,fifo_threshold ,default = 0 ,fifo_threshold
+#define MIPI_ADAPT_PIXEL0_CNTL1 ((0x0021 << 2) + 0xfe3b1000)
+//Bit 31:16 ,pixel_x_start ,default = 0 ,pixel_x_start
+//Bit 15:0 ,pixel_x_end ,default = 16'hffff ,pixel_x_end
+#define MIPI_ADAPT_PIXEL0_CNTL2 ((0x0022 << 2) + 0xfe3b1000)
+//Bit 31:28 ,reserved
+//Bit 27:15 ,pixel_num ,default = 0 ,pixel_num
+//Bit 14:10 ,reserved
+//Bit 9:0 ,fifo_rd_size ,default = 0 ,fifo_rd_size
+#define MIPI_ADAPT_PIXEL0_CNTL3 ((0x0023 << 2) + 0xfe3b1000)
+//Bit 31 ,frame_sync_dely_en ,default = 0 ,frame_sync_dely_en
+//Bit 30:16 ,frame_sync_dely_time ,default = 0 ,frame_sync_dely_time
+//Bit 15:3 ,reserved
+//Bit 2 ,frame_sync_en ,default = 0 ,frame_sync_en
+//Bit 1 ,frame_sync_rst_en ,default = 0 ,frame_sync_rst_en
+//Bit 0 ,frame_sync_load_en ,default = 0 ,frame_sync_load_en
+#define MIPI_ADAPT_PIXEL0_ST0 ((0x002a << 2) + 0xfe3b1000)
+//Bit 31:0 ,mipi_adapt_pixel0_st0 ,default = 0 ,mipi_adapt_pixel0_st0
+#define MIPI_ADAPT_PIXEL0_ST1 ((0x002b << 2) + 0xfe3b1000)
+//Bit 31:0 ,mipi_adapt_pixel0_st1 ,default = 0 ,mipi_adapt_pixel0_st1
+#define MIPI_ADAPT_PIXEL1_CNTL0 ((0x0030 << 2) + 0xfe3b1000)
+//Bit 31 ,start_en ,default = 0 ,start_en ,pluse,one cycle
+//Bit 30 ,soft_load ,default = 0 ,soft_load ,pluse,one cycle
+//Bit 29:26 ,reserved
+//Bit 25:20 ,data_type ,default = 0 ,data_type
+//Bit 19:18 ,reserved
+//Bit 17:16 ,data_mode ,default = 0 ,data_mode
+//Bit 15 ,mode_422to444 ,default = 0 ,mode_422to444
+//Bit 14 ,color_expand ,default = 0 ,color_expand
+//Bit 13 ,reserved
+//Bit 12:0 ,fifo_threshold ,default = 0 ,fifo_threshold
+#define MIPI_ADAPT_PIXEL1_CNTL1 ((0x0031 << 2) + 0xfe3b1000)
+//Bit 31:16 ,pixel_x_start ,default = 0 ,pixel_x_start
+//Bit 15:0 ,pixel_x_end ,default = 16'hffff ,pixel_x_end
+#define MIPI_ADAPT_PIXEL1_CNTL2 ((0x0032 << 2) + 0xfe3b1000)
+//Bit 31:28 ,reserved
+//Bit 27:15 ,pixel_num ,default = 0 ,pixel_num
+//Bit 14:10 ,reserved
+//Bit 9:0 ,fifo_rd_size ,default = 0 ,fifo_rd_size
+#define MIPI_ADAPT_PIXEL1_CNTL3 ((0x0033 << 2) + 0xfe3b1000)
+//Bit 31 ,frame_sync_dely_en ,default = 0 ,frame_sync_dely_en
+//Bit 30:16 ,frame_sync_dely_time ,default = 0 ,frame_sync_dely_time
+//Bit 15:3 ,reserved
+//Bit 2 ,frame_sync_en ,default = 0 ,frame_sync_en
+//Bit 1 ,frame_sync_rst_en ,default = 0 ,frame_sync_rst_en
+//Bit 0 ,frame_sync_load_en ,default = 0 ,frame_sync_load_en
+#define MIPI_ADAPT_PIXEL1_ST0 ((0x003a << 2) + 0xfe3b1000)
+//Bit 31:0 ,mipi_adapt_pixel1_st0 ,default = 0 ,mipi_adapt_pixel1_st0
+#define MIPI_ADAPT_PIXEL1_ST1 ((0x003b << 2) + 0xfe3b1000)
+//Bit 31:0 ,mipi_adapt_pixel1_st1 ,default = 0 ,mipi_adapt_pixel1_st1
+#define MIPI_ADAPT_ALIG_CNTL0 ((0x0040 << 2) + 0xfe3b1000)
+//Bit 31:16 ,v_num_a ,default = 0 ,v_num_a
+//Bit 15:0 ,h_num_a ,default = 0 ,h_num_a
+#define MIPI_ADAPT_ALIG_CNTL1 ((0x0041 << 2) + 0xfe3b1000)
+//Bit 31:16 ,hpe_num_a ,default = 0 ,hpe_num_a
+//Bit 15:0 ,hps_num_a ,default = 0 ,hps_num_a
+#define MIPI_ADAPT_ALIG_CNTL2 ((0x0042 << 2) + 0xfe3b1000)
+//Bit 31:16 ,vpe_num_a ,default = 0 ,vpe_num_a // line valid end point for camera a
+//Bit 15:0 ,vps_num_a ,default = 0 ,vps_num_a // line valid start point for camera a
+#define MIPI_ADAPT_ALIG_CNTL3 ((0x0043 << 2) + 0xfe3b1000)
+//Bit 31:16 ,frame_start_line ,default = 0 ,frame_start_line // start line after frame_sync when frame_sync_rst_en is 1
+//Bit 15:0 ,frame_start_pixel ,default = 0 ,frame_start_pixel
+#define MIPI_ADAPT_ALIG_CNTL4 ((0x0044 << 2) + 0xfe3b1000)
+//Bit 31:30 ,reserved
+//Bit 29:0 ,fill_data ,default = 0 ,fill_data
+#define MIPI_ADAPT_ALIG_CNTL5 ((0x0045 << 2) + 0xfe3b1000)
+//Bit 31:24 ,flow_done_src_en ,default = 0 ,flow_done_src_en
+//Bit 23:0 ,reserved
+#define MIPI_ADAPT_ALIG_CNTL6 ((0x0046 << 2) + 0xfe3b1000)
+//Bit 31 ,yuvrgb_mode ,default = 0 ,yuvrgb_mode //
+//Bit 30 ,frame_end_load_en ,default = 0 ,frame_end_load_en //
+//Bit 29:16 ,reserved
+//Bit 15 ,vdata3_en ,default = 0 ,vdata3_en //vdata3 enable
+//Bit 14 ,vdata2_en ,default = 0 ,vdata2_en //vdata2 enable
+//Bit 13 ,vdata1_en ,default = 0 ,vdata1_en //vdata1 enable
+//Bit 12 ,vdata0_en ,default = 0 ,vdata0_en //vdata0 enable
+//Bit 11 ,vdata3_sel ,default = 0 ,vdata3_sel //vdata3 select
+//Bit 10 ,vdata2_sel ,default = 0 ,vdata2_sel //vdata2 select
+//Bit 9 ,vdata1_sel ,default = 0 ,vdata1_sel //vdata1 select
+//Bit 8 ,vdata0_sel ,default = 0 ,vdata0_sel //vdata0 select
+//Bit 7:6 ,reserved
+//Bit 5 ,pix_datamode_1 ,default = 0 ,pix_datamode_1 //
+//Bit 4 ,pix_datamode_0 ,default = 0 ,pix_datamode_0 //
+//Bit 3 ,lane1_sel ,default = 0 ,lane1_sel //lane select
+//Bit 2 ,lane1_en ,default = 0 ,lane1_en //lane enable
+//Bit 1 ,lane0_sel ,default = 0 ,lane0_sel //lane select
+//Bit 0 ,lane0_en ,default = 0 ,lane0_en //lane enable
+#define MIPI_ADAPT_ALIG_CNTL7 ((0x0047 << 2) + 0xfe3b1000)
+//Bit 31:16 ,inc_mask_timeout ,default = 0 ,inc_mask_timeout
+//Bit 15 ,inc_mask_timeout_en ,default = 0 ,inc_mask_timeout_en
+//Bit 14 ,frame_sync_rst_en ,default = 0 ,frame_sync_rst_en
+//Bit 13 ,frame_sync_load_en ,default = 0 ,frame_sync_load_en
+//Bit 12:2 ,reserved
+//Bit 1 :0 ,inc_mask_tick_sel ,default = 0 ,inc_mask_tick_sel
+#define MIPI_ADAPT_ALIG_CNTL8 ((0x0048 << 2) + 0xfe3b1000)
+//Bit 31 ,start_en ,default = 0 ,start_en //no shadow
+//Bit 30 ,reserved
+//Bit 29 ,soft_load ,default = 0 ,soft_load //no shadow
+//Bit 28:16 ,reserved
+//Bit 15 ,hsync_irq_num_en ,default = 0 ,hsync_irq_num_en
+//Bit 14 ,reserved
+//Bit 13 ,no_frame_sv_sync_en ,default = 0 ,no_frame_sv_sync_en // reset hcnt to frame_start_pixel
+//Bit 12 ,exc_mask_dis ,default = 0 ,exc_mask_dis //disable inc_mask when exc happen
+//Bit 11 ,mult_camera_req_sf_en ,default = 0 ,mult_camera_req_sf_en //
+//Bit 10 ,mult_camera_req_sf ,default = 0 ,mult_camera_req_sf //
+//Bit 9:7 ,reserved
+//Bit 6 ,isp_mult_frame_req_en ,default = 0 ,isp_mult_frame_req_en
+//Bit 5 ,frame_continue ,default = 0 ,frame_continue
+//Bit 4:0 ,reserved
+#define MIPI_ADAPT_ALIG_CNTL9 ((0x0049 << 2) + 0xfe3b1000)
+//Bit 31 ,frame_sync_dely_en ,default = 0 ,frame_sync_dely_en
+//Bit 30:16 ,frame_sync_dely_time ,default = 0 ,frame_sync_dely_time
+//Bit 15:0 ,hsync_irq_num ,default = 0 ,hsync_irq_num
+#define MIPI_ADAPT_ALIG_CNTL10 ((0x004a << 2) + 0xfe3b1000)
+//Bit 31 ,isp_hold_src7_en ,default = 0 ,isp_hold_src7_en
+//Bit 30 ,isp_hold_src6_en ,default = 0 ,isp_hold_src6_en
+//Bit 29 ,isp_hold_src5_en ,default = 0 ,isp_hold_src5_en
+//Bit 28 ,isp_hold_src4_en ,default = 0 ,isp_hold_src4_en
+//Bit 27 ,isp_hold_src3_en ,default = 0 ,isp_hold_src3_en
+//Bit 26 ,isp_hold_src2_en ,default = 0 ,isp_hold_src2_en
+//Bit 25 ,isp_hold_src1_en ,default = 0 ,isp_hold_src1_en
+//Bit 24 ,isp_hold_src0_en ,default = 0 ,isp_hold_src0_en
+//Bit 23:19 ,reserved
+//Bit 18:16 ,frame_vs_sel ,default = 0 ,frame_vs_sel
+//Bit 15:0 ,frame_vs_cke_delay ,default = 0 ,frame_vs_cke_delay
+#define MIPI_ADAPT_ALIG_CNTL11 ((0x004b << 2) + 0xfe3b1000)
+//Bit 31:19 ,reserved
+//Bit 18:16 ,frame_vs_dst0_sel ,default = 0 ,frame_vs_dst0_sel
+//Bit 15:0 ,frame_vs_dst0_cke_delay ,default = 0 ,frame_vs_dst0_cke_delay
+#define MIPI_ADAPT_ALIG_CNTL12 ((0x004c << 2) + 0xfe3b1000)
+//Bit 31:19 ,reserved
+//Bit 18:16 ,frame_vs_dst1_sel ,default = 0 ,frame_vs_dst1_sel
+//Bit 15:0 ,frame_vs_dst1_cke_delay ,default = 0 ,frame_vs_dst1_cke_delay
+#define MIPI_ADAPT_ALIG_CNTL13 ((0x004d << 2) + 0xfe3b1000)
+//Bit 31:19 ,reserved
+//Bit 18:16 ,frame_vs_dst2_sel ,default = 0 ,frame_vs_dst2_sel
+//Bit 15:0 ,frame_vs_dst2_cke_delay ,default = 0 ,frame_vs_dst2_cke_delay
+#define MIPI_ADAPT_ALIG_CNTL14 ((0x004e << 2) + 0xfe3b1000)
+//Bit 31:19 ,reserved
+//Bit 18:16 ,frame_vs_dst3_sel ,default = 0 ,frame_vs_dst3_sel
+//Bit 15:0 ,frame_vs_dst3_cke_delay ,default = 0 ,frame_vs_dst3_cke_delay
+#define MIPI_ADAPT_ALIG_CNTL15 ((0x004f << 2) + 0xfe3b1000)
+//Bit 31:19 ,reserved
+//Bit 18:16 ,frame_vs_dst4_sel ,default = 0 ,frame_vs_dst4_sel
+//Bit 15:0 ,frame_vs_dst4_cke_delay ,default = 0 ,frame_vs_dst4_cke_delay
+#define MIPI_ADAPT_ALIG_CNTL16 ((0x0050 << 2) + 0xfe3b1000)
+//Bit 31:19 ,reserved
+//Bit 18:16 ,frame_vs_dst5_sel ,default = 0 ,frame_vs_dst5_sel
+//Bit 15:0 ,frame_vs_dst5_cke_delay ,default = 0 ,frame_vs_dst5_cke_delay
+#define MIPI_ADAPT_ALIG_CNTL17 ((0x0051 << 2) + 0xfe3b1000)
+//Bit 31:19 ,reserved
+//Bit 18:16 ,frame_vs_dst6_sel ,default = 0 ,frame_vs_dst6_sel
+//Bit 15:0 ,frame_vs_dst6_cke_delay ,default = 0 ,frame_vs_dst6_cke_delay
+#define MIPI_ADAPT_ALIG_CNTL18 ((0x0052 << 2) + 0xfe3b1000)
+//Bit 31:19 ,reserved
+//Bit 18:16 ,frame_vs_dst7_sel ,default = 0 ,frame_vs_dst7_sel
+//Bit 15:0 ,frame_vs_dst7_cke_delay ,default = 0 ,frame_vs_dst7_cke_delay
+#define MIPI_ADAPT_ALIG_CNTL19 ((0x0053 << 2) + 0xfe3b1000)
+//Bit 31:19 ,reserved
+//Bit 18:16 ,frame_vs_dst8_sel ,default = 0 ,frame_vs_dst8_sel
+//Bit 15:0 ,frame_vs_dst8_cke_delay ,default = 0 ,frame_vs_dst8_cke_delay
+#define MIPI_ADAPT_ALIG_ST0 ((0x005a << 2) + 0xfe3b1000)
+//Bit 31:0 ,mipi_adapt_alig_st0 ,default = 0 ,mipi_adapt_alig_st0
+#define MIPI_ADAPT_ALIG_ST1 ((0x005b << 2) + 0xfe3b1000)
+//Bit 31:0 ,mipi_adapt_alig_st1 ,default = 0 ,mipi_adapt_alig_st1
+#define MIPI_ADAPT_ALIG_ST2 ((0x005c << 2) + 0xfe3b1000)
+//Bit 31:0 ,mipi_adapt_alig_st2 ,default = 0 ,mipi_adapt_alig_st2
+#define MIPI_ADAPT_OTHER_CNTL0 ((0x0060 << 2) + 0xfe3b1000)
+//Bit 31:24 ,reserved
+//Bit 23:20 ,reg_adapt_debug_sel ,default = 0 ,reg_adapt_debug_sel
+//Bit 19:18 ,reserved
+//Bit 17 ,reg_lbuf1_clk_on ,default = 0 ,reg_lbuf1_clk_on
+//Bit 16 ,reg_lbuf0_clk_on ,default = 0 ,reg_lbuf0_clk_on
+//Bit 15:11 ,reserved
+//Bit 10:0 ,reg_soft_rst ,default = 0 ,reg_soft_rst
+#define DDR_RD0_LBUF_STATUS ((0x007a << 2) + 0xfe3b1000)
+//Bit 31:0 ,ddr_rd_0_lbuf_status ,default = 0 ,ddr_rd_0_lbuf_status
+#define DDR_RD1_LBUF_STATUS ((0x007b << 2) + 0xfe3b1000)
+//Bit 31:0 ,ddr_rd_1_lbuf_status ,default = 0 ,ddr_rd_1_lbuf_status
+#define MIPI_ADAPT_FE_MUX_CTL0 ((0x0090 << 2) + 0xfe3b1000)
+//Bit 31:30 ,reserved
+//Bit 29:28 ,reg_alig_frame_valid_en ,default = 0 ,reg_alig_frame_valid_en
+//Bit 27:24 ,reg_alig_vs_sel ,default = 0 ,reg_alig_vs_sel
+//Bit 23:20 ,reg_pixel1_vs_sel ,default = 0 ,reg_pixel1_vs_sel
+//Bit 19:16 ,reg_pixel0_vs_sel ,default = 0 ,reg_pixel0_vs_sel
+//Bit 15 ,reserved
+//Bit 14 ,reg_ddr_rd1_line_wr_vs_sel ,default = 0 ,reg_ddr_rd1_line_wr_vs_sel
+//Bit 13 ,reg_ddr_rd1_frame_wr_done_sel ,default = 0 ,reg_ddr_rd1_frame_wr_done_sel
+//Bit 12 ,reg_ddr_rd1_line_wr_done_sel ,default = 0 ,reg_ddr_rd1_line_wr_done_sel
+//Bit 11:10 ,reserved
+//Bit 9:8 ,reg_ddr_rd1_fe_sel ,default = 0 ,reg_ddr_rd1_fe_sel
+//Bit 7 ,reserved
+//Bit 6 ,reg_ddr_rd0_line_wr_vs_sel ,default = 0 ,reg_ddr_rd0_line_wr_vs_sel
+//Bit 5 ,reg_ddr_rd0_frame_wr_done_sel ,default = 0 ,reg_ddr_rd0_frame_wr_done_sel
+//Bit 4 ,reg_ddr_rd0_line_wr_done_sel ,default = 0 ,reg_ddr_rd0_line_wr_done_sel
+//Bit 3:2 ,reserved
+//Bit 1:0 ,reg_ddr_rd0_fe_sel ,default = 0 ,reg_ddr_rd0_fe_sel
+#define MIPI_ADAPT_FE_MUX_CTL1 ((0x0091 << 2) + 0xfe3b1000)
+//Bit 31:28 ,reserved
+//Bit 27:24 ,reg_lbuf1_vs_sel ,default = 0 ,reg_lbuf1_vs_sel
+//Bit 23:20 ,reg_lbuf0_vs_sel ,default = 0 ,reg_lbuf0_vs_sel
+//Bit 19:17 ,reserved
+//Bit 16 ,reg_de_rd_frame_valid_sel ,default = 0 ,reg_de_rd_frame_valid_sel
+//Bit 15:12 ,reg_de_rd_vs_sel ,default = 0 ,reg_de_rd_vs_sel
+//Bit 11: 8 ,reg_de_wr_vs_sel ,default = 0 ,reg_de_wr_vs_sel
+//Bit 7: 4 ,reg_ds_nb_vs_sel ,default = 0 ,reg_ds_nb_vs_sel
+//Bit 3: 0 ,reg_fr_nb_vs_sel ,default = 0 ,reg_fr_nb_vs_sel
+#define MIPI_ADAPT_FE_MUX0_DLY_CNTL0 ((0x0092 << 2) + 0xfe3b1000)
+//Bit 31 , reg_mux0_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_mux0_mont_clr ,default = 0 ,
+//Bit 28 , reg_mux0_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_mux0_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_mux0_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_mux0_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX0_DLY_STAT0 ((0x0093 << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_mux0_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_mux0_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX1_DLY_CNTL0 ((0x0094 << 2) + 0xfe3b1000)
+//Bit 31 , reg_mux1_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_mux1_mont_clr ,default = 0 ,
+//Bit 28 , reg_mux1_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_mux1_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_mux1_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_mux1_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX1_DLY_STAT0 ((0x0095 << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_mux1_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_mux1_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX2_DLY_CNTL0 ((0x0096 << 2) + 0xfe3b1000)
+//Bit 31 , reg_mux2_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_mux2_mont_clr ,default = 0 ,
+//Bit 28 , reg_mux2_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_mux2_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_mux2_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_mux2_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX2_DLY_STAT0 ((0x0097 << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_mux2_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_mux2_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX3_DLY_CNTL0 ((0x0098 << 2) + 0xfe3b1000)
+//Bit 31 , reg_mux3_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_mux3_mont_clr ,default = 0 ,
+//Bit 28 , reg_mux3_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_mux3_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_mux3_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_mux3_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX3_DLY_STAT0 ((0x0099 << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_mux3_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_mux3_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX4_DLY_CNTL0 ((0x009a << 2) + 0xfe3b1000)
+//Bit 31 , reg_mux4_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_mux4_mont_clr ,default = 0 ,
+//Bit 28 , reg_mux4_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_mux4_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_mux4_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_mux4_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX4_DLY_STAT0 ((0x009b << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_mux4_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_mux4_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX5_DLY_CNTL0 ((0x009c << 2) + 0xfe3b1000)
+//Bit 31 , reg_mux5_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_mux5_mont_clr ,default = 0 ,
+//Bit 28 , reg_mux5_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_mux5_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_mux5_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_mux5_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX5_DLY_STAT0 ((0x009d << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_mux5_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_mux5_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX6_DLY_CNTL0 ((0x009e << 2) + 0xfe3b1000)
+//Bit 31 , reg_mux6_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_mux6_mont_clr ,default = 0 ,
+//Bit 28 , reg_mux6_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_mux6_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_mux6_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_mux6_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX6_DLY_STAT0 ((0x009f << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_mux6_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_mux6_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX7_DLY_CNTL0 ((0x00a0 << 2) + 0xfe3b1000)
+//Bit 31 , reg_mux7_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_mux7_mont_clr ,default = 0 ,
+//Bit 28 , reg_mux7_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_mux7_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_mux7_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_mux7_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX7_DLY_STAT0 ((0x00a1 << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_mux7_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_mux7_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX8_DLY_CNTL0 ((0x00a2 << 2) + 0xfe3b1000)
+//Bit 31 , reg_mux8_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_mux8_mont_clr ,default = 0 ,
+//Bit 28 , reg_mux8_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_mux8_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_mux8_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_mux8_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX8_DLY_STAT0 ((0x00a3 << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_mux8_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_mux8_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX9_DLY_CNTL0 ((0x00a4 << 2) + 0xfe3b1000)
+//Bit 31 , reg_mux9_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_mux9_mont_clr ,default = 0 ,
+//Bit 28 , reg_mux9_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_mux9_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_mux9_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_mux9_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX9_DLY_STAT0 ((0x00a5 << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_mux9_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_mux9_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX10_DLY_CNTL0 ((0x00a6 << 2) + 0xfe3b1000)
+//Bit 31 , reg_mux10_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_mux10_mont_clr ,default = 0 ,
+//Bit 28 , reg_mux10_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_mux10_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_mux10_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_mux10_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX10_DLY_STAT0 ((0x00a7 << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_mux10_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_mux10_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_DST_VS_0_DLY_CNTL0 ((0x00a8 << 2) + 0xfe3b1000)
+//Bit 31 , reg_alig0_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_alig0_mont_clr ,default = 0 ,
+//Bit 28 , reg_alig0_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_alig0_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_alig0_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_alig0_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_DST_VS_0_DLY_STAT0 ((0x00a9 << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_alig0_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_alig0_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_DST_VS_1_DLY_CNTL0 ((0x00aa << 2) + 0xfe3b1000)
+//Bit 31 , reg_alig1_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_alig1_mont_clr ,default = 0 ,
+//Bit 28 , reg_alig1_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_alig1_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_alig1_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_alig1_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_DST_VS_1_DLY_STAT0 ((0x00ab << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_alig1_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_alig1_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_DST_VS_2_DLY_CNTL0 ((0x00ac << 2) + 0xfe3b1000)
+//Bit 31 , reg_alig2_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_alig2_mont_clr ,default = 0 ,
+//Bit 28 , reg_alig2_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_alig2_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_alig2_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_alig2_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_DST_VS_2_DLY_STAT0 ((0x00ad << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_alig2_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_alig2_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_DST_VS_3_DLY_CNTL0 ((0x00ae << 2) + 0xfe3b1000)
+//Bit 31 , reg_alig3_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_alig3_mont_clr ,default = 0 ,
+//Bit 28 , reg_alig3_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_alig3_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_alig3_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_alig3_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_DST_VS_3_DLY_STAT0 ((0x00af << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_alig3_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_alig3_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_DST_VS_4_DLY_CNTL0 ((0x00b0 << 2) + 0xfe3b1000)
+//Bit 31 , reg_alig4_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_alig4_mont_clr ,default = 0 ,
+//Bit 28 , reg_alig4_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_alig4_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_alig4_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_alig4_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_DST_VS_4_DLY_STAT0 ((0x00b1 << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_alig4_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_alig4_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_DST_VS_5_DLY_CNTL0 ((0x00b2 << 2) + 0xfe3b1000)
+//Bit 31 , reg_alig5_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_alig5_mont_clr ,default = 0 ,
+//Bit 28 , reg_alig5_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_alig5_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_alig5_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_alig5_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_DST_VS_5_DLY_STAT0 ((0x00b3 << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_alig5_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_alig5_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_DST_VS_6_DLY_CNTL0 ((0x00b4 << 2) + 0xfe3b1000)
+//Bit 31 , reg_alig6_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_alig6_mont_clr ,default = 0 ,
+//Bit 28 , reg_alig6_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_alig6_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_alig6_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_alig6_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_DST_VS_6_DLY_STAT0 ((0x00b5 << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_alig6_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_alig6_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_DST_VS_7_DLY_CNTL0 ((0x00b6 << 2) + 0xfe3b1000)
+//Bit 31 , reg_alig7_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_alig7_mont_clr ,default = 0 ,
+//Bit 28 , reg_alig7_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_alig7_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_alig7_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_alig7_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_DST_VS_7_DLY_STAT0 ((0x00b7 << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_alig7_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_alig7_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_DST_VS_8_DLY_CNTL0 ((0x00b8 << 2) + 0xfe3b1000)
+//Bit 31 , reg_alig8_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_alig8_mont_clr ,default = 0 ,
+//Bit 28 , reg_alig8_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_alig8_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_alig8_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_alig8_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_DST_VS_8_DLY_STAT0 ((0x00b9 << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_alig8_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_alig8_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX11_DLY_CNTL0 ((0x00ba << 2) + 0xfe3b1000)
+//Bit 31 , reg_mux11_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_mux11_mont_clr ,default = 0 ,
+//Bit 28 , reg_mux11_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_mux11_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_mux11_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_mux11_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX11_DLY_STAT0 ((0x00bb << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_mux11_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_mux11_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX12_DLY_CNTL0 ((0x00bc << 2) + 0xfe3b1000)
+//Bit 31 , reg_mux12_soft_rst ,default = 0 ,
+//Bit 30 , reserved
+//Bit 29 , reg_mux12_mont_clr ,default = 0 ,
+//Bit 28 , reg_mux12_mont_en ,default = 0 ,
+//Bit 27:20 , reserved
+//Bit 19 , reg_mux12_vs_delay_en ,default = 0 ,
+//Bit 18 , reserved
+//Bit 17:16 , reg_mux12_vs_delay_tick_sel ,default = 0 ,
+//Bit 15:0 , reg_mux12_vs_delay_num ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX12_DLY_STAT0 ((0x00bd << 2) + 0xfe3b1000)
+//Bit 31:16 , ro_mux12_vs_mont_max ,default = 0 ,
+//Bit 15:0 , ro_mux12_vs_mon_min ,default = 0 ,
+#define MIPI_ADAPT_FE_MUX_CTL2 ((0x00be << 2) + 0xfe3b1000)
+//Bit 31 ,reg_dst_vs_sel1 ,default = 0 ,reg_dst_vs_sel1
+//Bit 30 ,reserved
+//Bit 29:24 ,reg_core_inf_sel1 ,default = 0 ,reg_core_inf_sel1
+//Bit 23 ,reg_dst_vs_sel0 ,default = 0 ,reg_dst_vs_sel0
+//Bit 22 ,reserved
+//Bit 21:16 ,reg_core_inf_sel0 ,default = 0 ,reg_core_inf_sel0
+//Bit 15: 9 ,reserved
+//Bit 8 ,reg_isp_core_inf_inv ,default = 0 ,reg_isp_core_inf_inv
+//Bit 7: 4 ,reg_mipi_csi_vs1_sel ,default = 0 ,reg_mipi_csi_vs1_sel
+//Bit 3: 0 ,reg_mipi_csi_vs0_sel ,default = 0 ,reg_mipi_csi_vs0_sel
+#define MIPI_ADAPT_FE_MUX_CTL3 ((0x00bf << 2) + 0xfe3b1000)
+//Bit 31 ,reg_dst_vs_sel5 ,default = 0 ,reg_dst_vs_sel5
+//Bit 30 ,reserved
+//Bit 29:24 ,reg_core_inf_sel5 ,default = 0 ,reg_core_inf_sel5
+//Bit 23 ,reg_dst_vs_sel4 ,default = 0 ,reg_dst_vs_sel4
+//Bit 22 ,reserved
+//Bit 21:16 ,reg_core_inf_sel4 ,default = 0 ,reg_core_inf_sel4
+//Bit 15 ,reg_dst_vs_sel3 ,default = 0 ,reg_dst_vs_sel3
+//Bit 14 ,reserved
+//Bit 13: 8 ,reg_core_inf_sel3 ,default = 0 ,reg_core_inf_sel3
+//Bit 7 ,reg_dst_vs_sel2 ,default = 0 ,reg_dst_vs_sel2
+//Bit 6 ,reserved
+//Bit 5: 0 ,reg_core_inf_sel2 ,default = 0 ,reg_core_inf_sel2
+#define MIPI_ADAPT_FE_MUX_CTL4 ((0x00c0 << 2) + 0xfe3b1000)
+//Bit 31:24 ,reserved
+//Bit 23 ,reg_dst_vs_sel8 ,default = 0 ,reg_dst_vs_sel8
+//Bit 22 ,reserved
+//Bit 21:16 ,reg_core_inf_sel8 ,default = 0 ,reg_core_inf_sel8
+//Bit 15 ,reg_dst_vs_sel7 ,default = 0 ,reg_dst_vs_sel7
+//Bit 14 ,reserved
+//Bit 13: 8 ,reg_core_inf_sel7 ,default = 0 ,reg_core_inf_sel7
+//Bit 7 ,reg_dst_vs_sel6 ,default = 0 ,reg_dst_vs_sel6
+//Bit 6 ,reserved
+//Bit 5: 0 ,reg_core_inf_sel6 ,default = 0 ,reg_core_inf_sel6
+#define MIPI_ADAPT_FE_MUX_CTL5 ((0x00c1 << 2) + 0xfe3b1000)
+//Bit 31: 0 ,isp_tnr_wr_fail_mask31_0 ,default = 0 ,isp_tnr_wr_fail_mask31_0
+#define MIPI_ADAPT_FE_MUX_CTL6 ((0x00c2 << 2) + 0xfe3b1000)
+//Bit 31 ,isp_tnr_wr_fail_en ,default = 0 ,isp_tnr_wr_fail_en
+//Bit 30: 9 ,reserved
+//Bit 8: 0 ,isp_tnr_wr_fail_mask40_32 ,default = 0 ,isp_tnr_wr_fail_mask40_32
+#define MIPI_ADAPT_FE_MUX_CTL7 ((0x00c3 << 2) + 0xfe3b1000)
+//Bit 31: 0 ,isp_tnr_rd_fail_mask31_0 ,default = 0 ,isp_tnr_rd_fail_mask31_0
+#define MIPI_ADAPT_FE_MUX_CTL8 ((0x00c4 << 2) + 0xfe3b1000)
+//Bit 31 ,isp_tnr_rd_fail_en ,default = 0 ,isp_tnr_rd_fail_en
+//Bit 30: 9 ,reserved
+//Bit 8: 0 ,isp_tnr_rd_fail_mask40_32 ,default = 0 ,isp_tnr_rd_fail_mask40_32
+//========================================================================
+// MIPI_ISP ds0
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b1400
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP ds1
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b1800
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP ds2
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b1c00
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP crop_mif
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b2000
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP md0
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b2400
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP md1
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b2800
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP fliker
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b2c00
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP top cfg
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b3000
+// -----------------------------------------------
+#define MIPI_BL_ISP_FR_PING_ADDR0_ST ((0x0000 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_PING_ADDR0_ED ((0x0001 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_PING_ADDR1_ST ((0x0002 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_PING_ADDR1_ED ((0x0003 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_PONG_ADDR0_ST ((0x0004 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_PONG_ADDR0_ED ((0x0005 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_PONG_ADDR1_ST ((0x0006 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_PONG_ADDR1_ED ((0x0007 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_FRAME_TH ((0x0008 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_FRAME_BUFFER_START_ADDR0 ((0x0009 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_FRAME_SIZE0 ((0x000a << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_FRAME_BUF_SIZE0 ((0x000b << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_FRAME_BUFFER_START_ADDR1 ((0x000c << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_FRAME_SIZE1 ((0x000d << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_FRAME_BUF_SIZE1 ((0x000e << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_CTRL0 ((0x000f << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_CTRL1 ((0x0010 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_FRAME_COUNT ((0x0011 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_AWADDR_O ((0x0012 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_AWADDR_I ((0x0013 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_STAT0 ((0x0014 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_STAT1 ((0x0015 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_STAT2 ((0x0016 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_STAT3 ((0x0017 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_FR_FRAME_BUFFER_START_ADDR0P ((0x0018 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_PING_ADDR0_ST ((0x0020 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_PING_ADDR0_ED ((0x0021 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_PING_ADDR1_ST ((0x0022 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_PING_ADDR1_ED ((0x0023 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_PONG_ADDR0_ST ((0x0024 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_PONG_ADDR0_ED ((0x0025 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_PONG_ADDR1_ST ((0x0026 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_PONG_ADDR1_ED ((0x0027 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_FRAME_TH ((0x0028 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_FRAME_BUFFER_START_ADDR0 ((0x0029 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_FRAME_SIZE0 ((0x002a << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_FRAME_BUF_SIZE0 ((0x002b << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_FRAME_BUFFER_START_ADDR1 ((0x002c << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_FRAME_SIZE1 ((0x002d << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_FRAME_BUF_SIZE1 ((0x002e << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_CTRL0 ((0x002f << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_CTRL1 ((0x0030 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_FRAME_COUNT ((0x0031 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_AWADDR_O ((0x0032 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_AWADDR_I ((0x0033 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_STAT0 ((0x0034 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_STAT1 ((0x0035 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_STAT2 ((0x0036 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_STAT3 ((0x0037 << 2) + 0xfe3b3000)
+#define MIPI_BL_ISP_DS_FRAME_BUFFER_START_ADDR0P ((0x0038 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_PING_ADDR0_ST ((0x0040 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_PING_ADDR0_ED ((0x0041 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_PING_ADDR1_ST ((0x0042 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_PING_ADDR1_ED ((0x0043 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_PONG_ADDR0_ST ((0x0044 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_PONG_ADDR0_ED ((0x0045 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_PONG_ADDR1_ST ((0x0046 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_PONG_ADDR1_ED ((0x0047 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_FRAME_TH ((0x0048 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_FRAME_BUFFER_START_ADDR0 ((0x0049 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_FRAME_SIZE0 ((0x004a << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_FRAME_BUF_SIZE0 ((0x004b << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_FRAME_BUFFER_START_ADDR1 ((0x004c << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_FRAME_SIZE1 ((0x004d << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_FRAME_BUF_SIZE1 ((0x004e << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_CTRL0 ((0x004f << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_CTRL1 ((0x0050 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_FRAME_COUNT ((0x0051 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_AWADDR_O ((0x0052 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_AWADDR_I ((0x0053 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_STAT0 ((0x0054 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_STAT1 ((0x0055 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_STAT2 ((0x0056 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_STAT3 ((0x0057 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS0_FRAME_BUFFER_START_ADDR0P ((0x0058 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_PING_ADDR0_ST ((0x0060 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_PING_ADDR0_ED ((0x0061 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_PING_ADDR1_ST ((0x0062 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_PING_ADDR1_ED ((0x0063 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_PONG_ADDR0_ST ((0x0064 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_PONG_ADDR0_ED ((0x0065 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_PONG_ADDR1_ST ((0x0066 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_PONG_ADDR1_ED ((0x0067 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_FRAME_TH ((0x0068 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_FRAME_BUFFER_START_ADDR0 ((0x0069 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_FRAME_SIZE0 ((0x006a << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_FRAME_BUF_SIZE0 ((0x006b << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_FRAME_BUFFER_START_ADDR1 ((0x006c << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_FRAME_SIZE1 ((0x006d << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_FRAME_BUF_SIZE1 ((0x006e << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_CTRL0 ((0x006f << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_CTRL1 ((0x0070 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_FRAME_COUNT ((0x0071 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_AWADDR_O ((0x0072 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_AWADDR_I ((0x0073 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_STAT0 ((0x0074 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_STAT1 ((0x0075 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_STAT2 ((0x0076 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_STAT3 ((0x0077 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS1_FRAME_BUFFER_START_ADDR0P ((0x0078 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_PING_ADDR0_ST ((0x0080 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_PING_ADDR0_ED ((0x0081 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_PING_ADDR1_ST ((0x0082 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_PING_ADDR1_ED ((0x0083 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_PONG_ADDR0_ST ((0x0084 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_PONG_ADDR0_ED ((0x0085 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_PONG_ADDR1_ST ((0x0086 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_PONG_ADDR1_ED ((0x0087 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_FRAME_TH ((0x0088 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_FRAME_BUFFER_START_ADDR0 ((0x0089 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_FRAME_SIZE0 ((0x008a << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_FRAME_BUF_SIZE0 ((0x008b << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_FRAME_BUFFER_START_ADDR1 ((0x008c << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_FRAME_SIZE1 ((0x008d << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_FRAME_BUF_SIZE1 ((0x008e << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_CTRL0 ((0x008f << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_CTRL1 ((0x0090 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_FRAME_COUNT ((0x0091 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_AWADDR_O ((0x0092 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_AWADDR_I ((0x0093 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_STAT0 ((0x0094 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_STAT1 ((0x0095 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_STAT2 ((0x0096 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_STAT3 ((0x0097 << 2) + 0xfe3b3000)
+#define MIPI_BL_DS2_FRAME_BUFFER_START_ADDR0P ((0x0098 << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_PING_ADDR0_ST ((0x00a0 << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_PING_ADDR0_ED ((0x00a1 << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_PING_ADDR1_ST ((0x00a2 << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_PING_ADDR1_ED ((0x00a3 << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_PONG_ADDR0_ST ((0x00a4 << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_PONG_ADDR0_ED ((0x00a5 << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_PONG_ADDR1_ST ((0x00a6 << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_PONG_ADDR1_ED ((0x00a7 << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_FRAME_TH ((0x00a8 << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_FRAME_BUFFER_START_ADDR0 ((0x00a9 << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_FRAME_SIZE0 ((0x00aa << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_FRAME_BUF_SIZE0 ((0x00ab << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_FRAME_BUFFER_START_ADDR1 ((0x00ac << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_FRAME_SIZE1 ((0x00ad << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_FRAME_BUF_SIZE1 ((0x00ae << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_CTRL0 ((0x00af << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_CTRL1 ((0x00b0 << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_FRAME_COUNT ((0x00b1 << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_AWADDR_O ((0x00b2 << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_AWADDR_I ((0x00b3 << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_STAT0 ((0x00b4 << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_STAT1 ((0x00b5 << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_STAT2 ((0x00b6 << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_STAT3 ((0x00b7 << 2) + 0xfe3b3000)
+#define MIPI_BL_CROP_MIF_FRAME_BUFFER_START_ADDR0P ((0x00b8 << 2) + 0xfe3b3000)
+#define MIPI_TOP_CSI2_CTRL0 ((0x00c0 << 2) + 0xfe3b3000)
+#define MIPI_TOP_ADAPT_DE_CTRL0 ((0x00c1 << 2) + 0xfe3b3000)
+#define MIPI_TOP_ADAPT_DE_CTRL1 ((0x00c2 << 2) + 0xfe3b3000)
+#define MIPI_TOP_ADAPT_DE_CTRL2 ((0x00c3 << 2) + 0xfe3b3000)
+#define MIPI_TOP_ADAPT_DE_CTRL3 ((0x00c4 << 2) + 0xfe3b3000)
+#define MIPI_TOP_TNR_DE_CTRL0 ((0x00c5 << 2) + 0xfe3b3000)
+#define MIPI_TOP_ARIBIT0_CTRL ((0x00c6 << 2) + 0xfe3b3000)
+#define MIPI_TOP_ARIBIT1_CTRL ((0x00c7 << 2) + 0xfe3b3000)
+#define MIPI_TOP_ARIBIT2_CTRL ((0x00c8 << 2) + 0xfe3b3000)
+#define MIPI_TOP_AXI_CMD_MASK_DDR_RD0_CNTL ((0x00c9 << 2) + 0xfe3b3000)
+#define MIPI_TOP_AXI_CMD_MASK_DDR_RD1_CNTL ((0x00ca << 2) + 0xfe3b3000)
+#define MIPI_TOP_AXI_DS_WBUS_NOBLOCK_CNTL ((0x00cb << 2) + 0xfe3b3000)
+#define MIPI_TOP_AXI_FR_WBUS_NOBLOCK_CNTL ((0x00cc << 2) + 0xfe3b3000)
+#define MIPI_TOP_AXI_DS_WBUF_NOBLOCK_ST0 ((0x00cd << 2) + 0xfe3b3000)
+#define MIPI_TOP_AXI_FR_WBUF_NOBLOCK_ST0 ((0x00ce << 2) + 0xfe3b3000)
+#define MIPI_TOP_ADAPT_DE_STAT0 ((0x00cf << 2) + 0xfe3b3000)
+#define MIPI_TOP_FR_WR_UGT_CNTL0 ((0x00d0 << 2) + 0xfe3b3000)
+#define MIPI_TOP_FR_WR_UGT_CNTL1 ((0x00d1 << 2) + 0xfe3b3000)
+#define MIPI_TOP_FR_WR_UGT_CNTL2 ((0x00d2 << 2) + 0xfe3b3000)
+#define MIPI_TOP_FR_WR_UGT_CNTL3 ((0x00d3 << 2) + 0xfe3b3000)
+#define MIPI_TOP_FR_WR_UGT_ST ((0x00d4 << 2) + 0xfe3b3000)
+#define MIPI_TOP_DS_WR_UGT_CNTL0 ((0x00d5 << 2) + 0xfe3b3000)
+#define MIPI_TOP_DS_WR_UGT_CNTL1 ((0x00d6 << 2) + 0xfe3b3000)
+#define MIPI_TOP_DS_WR_UGT_CNTL2 ((0x00d7 << 2) + 0xfe3b3000)
+#define MIPI_TOP_DS_WR_UGT_CNTL3 ((0x00d8 << 2) + 0xfe3b3000)
+#define MIPI_TOP_DS_WR_UGT_ST ((0x00d9 << 2) + 0xfe3b3000)
+#define MIPI_TOP_TNR_WR_UGT_CNTL0 ((0x00da << 2) + 0xfe3b3000)
+#define MIPI_TOP_TNR_WR_UGT_CNTL1 ((0x00db << 2) + 0xfe3b3000)
+#define MIPI_TOP_TNR_WR_UGT_CNTL2 ((0x00dc << 2) + 0xfe3b3000)
+#define MIPI_TOP_TNR_WR_UGT_CNTL3 ((0x00dd << 2) + 0xfe3b3000)
+#define MIPI_TOP_TNR_WR_UGT_ST ((0x00de << 2) + 0xfe3b3000)
+#define MIPI_TOP_TNR_RD_UGT_CNTL0 ((0x00df << 2) + 0xfe3b3000)
+#define MIPI_TOP_TNR_RD_UGT_CNTL1 ((0x00e0 << 2) + 0xfe3b3000)
+#define MIPI_TOP_TNR_RD_UGT_CNTL2 ((0x00e1 << 2) + 0xfe3b3000)
+#define MIPI_TOP_TNR_RD_UGT_CNTL3 ((0x00e2 << 2) + 0xfe3b3000)
+#define MIPI_TOP_TNR_RD_UGT_ST ((0x00e3 << 2) + 0xfe3b3000)
+#define MIPI_TOP_ISP_FR_AXI_CNTL0 ((0x00e4 << 2) + 0xfe3b3000)
+#define MIPI_TOP_ISP_SIDEBAND_CNTL0 ((0x00e5 << 2) + 0xfe3b3000)
+#define MIPI_TOP_ISP_SIDEBAND_CNTL1 ((0x00e6 << 2) + 0xfe3b3000)
+#define MIPI_TOP_ISP_PENDING_MASK0 ((0x00f0 << 2) + 0xfe3b3000)
+#define MIPI_TOP_ISP_PENDING_MASK1 ((0x00f1 << 2) + 0xfe3b3000)
+#define MIPI_TOP_ISP_PENDING0 ((0x00f2 << 2) + 0xfe3b3000)
+#define MIPI_TOP_ISP_PENDING1 ((0x00f3 << 2) + 0xfe3b3000)
+#define MIPI_TOP_ISP_FR_WBUS_PROT_CNTL ((0x00f4 << 2) + 0xfe3b3000)
+#define MIPI_TOP_ISP_FR_WBUS_PROT_STAT ((0x00f5 << 2) + 0xfe3b3000)
+//========================================================================
+// MIPI_ISP isp ahb dma
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b3400
+// -----------------------------------------------
+#define ISP_DMA_BUS_CNTL ((0x0000 << 2) + 0xfe3b3400)
+#define ISP_DMA_CTL0 ((0x0001 << 2) + 0xfe3b3400)
+#define ISP_DMA_SRC_ADDR0 ((0x0002 << 2) + 0xfe3b3400)
+#define ISP_DMA_DST_ADDR0 ((0x0003 << 2) + 0xfe3b3400)
+#define ISP_DMA_CTL_TASK0 ((0x0004 << 2) + 0xfe3b3400)
+#define ISP_DMA_SRC_ADDR1 ((0x0005 << 2) + 0xfe3b3400)
+#define ISP_DMA_DST_ADDR1 ((0x0006 << 2) + 0xfe3b3400)
+#define ISP_DMA_CTL_TASK1 ((0x0007 << 2) + 0xfe3b3400)
+#define ISP_DMA_SRC_ADDR2 ((0x0008 << 2) + 0xfe3b3400)
+#define ISP_DMA_DST_ADDR2 ((0x0009 << 2) + 0xfe3b3400)
+#define ISP_DMA_CTL_TASK2 ((0x000a << 2) + 0xfe3b3400)
+#define ISP_DMA_SRC_ADDR3 ((0x000b << 2) + 0xfe3b3400)
+#define ISP_DMA_DST_ADDR3 ((0x000c << 2) + 0xfe3b3400)
+#define ISP_DMA_CTL_TASK3 ((0x000d << 2) + 0xfe3b3400)
+#define ISP_DMA_SRC_ADDR4 ((0x000e << 2) + 0xfe3b3400)
+#define ISP_DMA_DST_ADDR4 ((0x000f << 2) + 0xfe3b3400)
+#define ISP_DMA_CTL_TASK4 ((0x0010 << 2) + 0xfe3b3400)
+#define ISP_DMA_SRC_ADDR5 ((0x0011 << 2) + 0xfe3b3400)
+#define ISP_DMA_DST_ADDR5 ((0x0012 << 2) + 0xfe3b3400)
+#define ISP_DMA_CTL_TASK5 ((0x0013 << 2) + 0xfe3b3400)
+#define ISP_DMA_SRC_ADDR6 ((0x0014 << 2) + 0xfe3b3400)
+#define ISP_DMA_DST_ADDR6 ((0x0015 << 2) + 0xfe3b3400)
+#define ISP_DMA_CTL_TASK6 ((0x0016 << 2) + 0xfe3b3400)
+#define ISP_DMA_SRC_ADDR7 ((0x0017 << 2) + 0xfe3b3400)
+#define ISP_DMA_DST_ADDR7 ((0x0018 << 2) + 0xfe3b3400)
+#define ISP_DMA_CTL_TASK7 ((0x0019 << 2) + 0xfe3b3400)
+#define ISP_DMA_ST0 ((0x001a << 2) + 0xfe3b3400)
+#define ISP_DMA_ST1 ((0x001b << 2) + 0xfe3b3400)
+#define ISP_DMA_ST2 ((0x001c << 2) + 0xfe3b3400)
+#define ISP_DMA_ST3 ((0x001d << 2) + 0xfe3b3400)
+#define ISP_DMA_ST4 ((0x001e << 2) + 0xfe3b3400)
+#define ISP_DMA_ST5 ((0x001f << 2) + 0xfe3b3400)
+#define ISP_DMA_ST6 ((0x0020 << 2) + 0xfe3b3400)
+#define ISP_DMA_PENDING ((0x0023 << 2) + 0xfe3b3400)
+#define ISP_DMA_IRQ_MASK ((0x0024 << 2) + 0xfe3b3400)
+//========================================================================
+// MIPI_ISP axi arbit0
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b3800
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP axi arbit1
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b3c00
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP data compress/decompress0_0
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b4000
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP data compress/decompress0_1
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b4400
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP data compress/decompress1_0
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b4800
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP data compress/decompress1_1
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b4c00
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP data compress/decompress1_2
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b5000
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP reveser
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b5400
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP axi arbit2
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3b5800
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP apb dma
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3bbc00
+// -----------------------------------------------
+//
+// Reading file: mipi_apb_dma.h
+//
+#define MIPI_DMA_AXI_CTL ((0x0000 << 2) + 0xfe3bbc00)
+//Bit 31:28, axi_rbus_prot_cntl , default = 0, axi_rbus_prot_cntl
+//Bit 27:24, axi_wbus_prot_cntl , default = 0, axi_wbus_prot_cntl
+//Bit 23:22, reserved
+//Bit 21, reg_axi_arugt , default = 0, axi read urgent
+//Bit 20, reg_axi_awugt , default = 0, axi write urgent
+//Bit 19:11, reserved
+//Bit 12:8, reg_axi_id , default = 0, axi id
+//Bit 7:4, reserved
+//Bit 3:2, reg_axi_wr_burst_type , default = 0, axi wr burst type,00 single 01 incr2 10 incr4 11 incr8
+//Bit 1:0, reg_axi_rd_burst_type , default = 0, axi rd burst type,00 single 01 incr2 10 incr4 11 incr8
+#define MIPI_DMA_CTL0 ((0x0001 << 2) + 0xfe3bbc00)
+//Bit 31, reg_dma_en , default = 0, dma enable
+//Bit 30:28, reserved
+//Bit 27, reg_soft_rst , default = 0, soft reset
+//Bit 26, reg_trig_fifo_rst , default = 0, trigger source fifo reset
+//Bit 25, reg_axi_rfifo_rst , default = 0, axi rfifo reset
+//Bit 24, reg_axi_wfifo_rst , default = 0, axi wfifo reset
+//Bit 17:16, reg_trig_fifo_stat_sel , default = 0, reg_trig_fifo_stat_sel
+//Bit 15:0, reserved
+#define MIPI_DMA_PENDING0 ((0x0002 << 2) + 0xfe3bbc00)
+//Bit 31:16, c_src_trig_err_set , default = 0, when current source task not completed ,next same trigger source in
+//Bit 15:0 , c_src_done_set , default = 0, trigger source all task done
+#define MIPI_DMA_PENDING1 ((0x0003 << 2) + 0xfe3bbc00)
+//Bit 31:2 , reserved
+//Bit 1, bus_mon_fast_irq , default = 0, apb arbit int
+//Bit 0, c_trig_fifo_overflow_set , default = 0, trigger fifo overflow
+#define MIPI_DMA_IRQ_MASK0 ((0x0004 << 2) + 0xfe3bbc00)
+//Bit 31:16, c_src_trig_err_mask , default = 0, when current source task not completed ,next same trigger source in
+//Bit 15:0 , c_src_done_mask , default = 0, trigger source all task done
+#define MIPI_DMA_IRQ_MASK1 ((0x0005 << 2) + 0xfe3bbc00)
+//Bit 31:2 , reserved
+//Bit 1, bus_mon_fast_irq_mask , default = 0, apb arbit int
+//Bit 0, c_trig_fifo_overflow_mask , default = 0, trigger fifo overflow
+#define MIPI_DMA_STAT0 ((0x0010 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_dma_stat0 , default = 0
+#define MIPI_DMA_STAT1 ((0x0011 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_dma_stat1 , default = 0
+#define MIPI_DMA_STAT2 ((0x0012 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_dma_stat2 , default = 0
+#define MIPI_DMA_STAT3 ((0x0013 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_dma_stat3 , default = 0
+#define MIPI_DMA_STAT4 ((0x0014 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_dma_stat4 , default = 0
+#define MIPI_DMA_STAT5 ((0x0015 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_dma_stat5 , default = 0
+#define MIPI_DMA_STAT6 ((0x0016 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_dma_stat5 , default = 0
+#define MIPI_DMA_TRIG_FIFO_STAT0 ((0x0017 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_trig_fifo_stat0 , default = 0
+#define MIPI_DMA_AXI_FIFO_STAT0 ((0x0018 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_axi_fifo_stat0 , default = 0
+#define MIPI_DMA_ARBIT_CNTL0 ((0x0020 << 2) + 0xfe3bbc00)
+//Bit 31:4, reserved
+//Bit 3:0, bus_monitor_cntl , default = 0,apb arbit bus_monitor_cntl
+#define MIPI_DMA_ARBIT_CNTL1 ((0x0021 << 2) + 0xfe3bbc00)
+//Bit 31:0, bus_mon_addr , default = 0,apb arbit bus_mon_addr
+#define MIPI_DMA_ARBIT_CNTL2 ((0x0022 << 2) + 0xfe3bbc00)
+//Bit 31:0, bus_mon_data , default = 0,apb arbit bus_mon_data
+#define MIPI_DMA_ARBIT_CNTL3 ((0x0023 << 2) + 0xfe3bbc00)
+//Bit 31:0, bus_mon_data_msk , default = 0,apb arbit bus_mon_data_msk
+#define MIPI_DMA_SRC0_CTL ((0x0030 << 2) + 0xfe3bbc00)
+//Bit 3, reg_src_pingpong_force_val , default = 0, src0 pingpong force sel
+//Bit 2, reg_src_pingpong_force , default = 0, src0 pingpong force enable
+//Bit 1, reg_src_pingpong_ini , default = 0, src0 pingpong initial sel
+//Bit 0, reg_src0_en , default = 0, src0 enable
+#define MIPI_DMA_SRC0_PING_CMD_ADDR0 ((0x0031 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src0_ping_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC0_PING_DST_ADDR0 ((0x0032 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src0_ping_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC0_PING_TASK0 ((0x0033 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src0_ping_task0_valid , default = 0, task valid
+//Bit 30, reg_src0_ping_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src0_ping_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC0_PING_CMD_ADDR1 ((0x0034 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src0_ping_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC0_PING_DST_ADDR1 ((0x0035 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src0_ping_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC0_PING_TASK1 ((0x0036 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src0_ping_task1_valid , default = 0, task valid
+//Bit 30, reg_src0_ping_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src0_ping_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC0_PONG_CMD_ADDR0 ((0x0037 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src0_pong_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC0_PONG_DST_ADDR0 ((0x0038 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src0_pong_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC0_PONG_TASK0 ((0x0039 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src0_pong_task0_valid , default = 0, task valid
+//Bit 30, reg_src0_pong_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src0_pong_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC0_PONG_CMD_ADDR1 ((0x003a << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src0_pong_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC0_PONG_DST_ADDR1 ((0x003b << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src0_pong_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC0_PONG_TASK1 ((0x003c << 2) + 0xfe3bbc00)
+//Bit 31, reg_src0_pong_task1_valid , default = 0, task valid
+//Bit 30, reg_src0_pong_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src0_pong_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC1_CTL ((0x003d << 2) + 0xfe3bbc00)
+//Bit 3, reg_src_pingpong_force_val , default = 0, src1 pingpong force sel
+//Bit 2, reg_src_pingpong_force , default = 0, src1 pingpong force enable
+//Bit 1, reg_src_pingpong_ini , default = 0, src1 pingpong initial sel
+//Bit 0, reg_src1_en , default = 0, src0 enable
+#define MIPI_DMA_SRC1_PING_CMD_ADDR0 ((0x003e << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src1_ping_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC1_PING_DST_ADDR0 ((0x003f << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src1_ping_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC1_PING_TASK0 ((0x0040 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src1_ping_task0_valid , default = 0, task valid
+//Bit 30, reg_src1_ping_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src1_ping_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC1_PING_CMD_ADDR1 ((0x0041 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src1_ping_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC1_PING_DST_ADDR1 ((0x0042 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src1_ping_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC1_PING_TASK1 ((0x0043 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src1_ping_task1_valid , default = 0, task valid
+//Bit 30, reg_src1_ping_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src1_ping_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC1_PONG_CMD_ADDR0 ((0x0044 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src1_pong_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC1_PONG_DST_ADDR0 ((0x0045 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src1_pong_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC1_PONG_TASK0 ((0x0046 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src1_pong_task0_valid , default = 0, task valid
+//Bit 30, reg_src1_pong_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src1_pong_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC1_PONG_CMD_ADDR1 ((0x0047 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src1_pong_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC1_PONG_DST_ADDR1 ((0x0048 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src1_pong_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC1_PONG_TASK1 ((0x0049 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src1_pong_task1_valid , default = 0, task valid
+//Bit 30, reg_src1_pong_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src1_pong_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC2_CTL ((0x004a << 2) + 0xfe3bbc00)
+//Bit 3, reg_src_pingpong_force_val , default = 0, src2 pingpong force sel
+//Bit 2, reg_src_pingpong_force , default = 0, src2 pingpong force enable
+//Bit 1, reg_src_pingpong_ini , default = 0, src2 pingpong initial sel
+//Bit 0, reg_src2_en , default = 0, src0 enable
+#define MIPI_DMA_SRC2_PING_CMD_ADDR0 ((0x004b << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src2_ping_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC2_PING_DST_ADDR0 ((0x004c << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src2_ping_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC2_PING_TASK0 ((0x004d << 2) + 0xfe3bbc00)
+//Bit 31, reg_src2_ping_task0_valid , default = 0, task valid
+//Bit 30, reg_src2_ping_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src2_ping_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC2_PING_CMD_ADDR1 ((0x004e << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src2_ping_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC2_PING_DST_ADDR1 ((0x004f << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src2_ping_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC2_PING_TASK1 ((0x0050 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src2_ping_task1_valid , default = 0, task valid
+//Bit 30, reg_src2_ping_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src2_ping_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC2_PONG_CMD_ADDR0 ((0x0051 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src2_pong_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC2_PONG_DST_ADDR0 ((0x0052 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src2_pong_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC2_PONG_TASK0 ((0x0053 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src2_pong_task0_valid , default = 0, task valid
+//Bit 30, reg_src2_pong_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src2_pong_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC2_PONG_CMD_ADDR1 ((0x0054 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src2_pong_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC2_PONG_DST_ADDR1 ((0x0055 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src2_pong_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC2_PONG_TASK1 ((0x0056 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src2_pong_task1_valid , default = 0, task valid
+//Bit 30, reg_src2_pong_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src2_pong_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC3_CTL ((0x0057 << 2) + 0xfe3bbc00)
+//Bit 3, reg_src_pingpong_force_val , default = 0, src3 pingpong force sel
+//Bit 2, reg_src_pingpong_force , default = 0, src3 pingpong force enable
+//Bit 1, reg_src_pingpong_ini , default = 0, src3 pingpong initial sel
+//Bit 0, reg_src3_en , default = 0, src0 enable
+#define MIPI_DMA_SRC3_PING_CMD_ADDR0 ((0x0058 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src3_ping_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC3_PING_DST_ADDR0 ((0x0059 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src3_ping_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC3_PING_TASK0 ((0x005a << 2) + 0xfe3bbc00)
+//Bit 31, reg_src3_ping_task0_valid , default = 0, task valid
+//Bit 30, reg_src3_ping_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src3_ping_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC3_PING_CMD_ADDR1 ((0x005b << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src3_ping_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC3_PING_DST_ADDR1 ((0x005c << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src3_ping_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC3_PING_TASK1 ((0x005d << 2) + 0xfe3bbc00)
+//Bit 31, reg_src3_ping_task1_valid , default = 0, task valid
+//Bit 30, reg_src3_ping_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src3_ping_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC3_PONG_CMD_ADDR0 ((0x005e << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src3_pong_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC3_PONG_DST_ADDR0 ((0x005f << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src3_pong_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC3_PONG_TASK0 ((0x0060 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src3_pong_task0_valid , default = 0, task valid
+//Bit 30, reg_src3_pong_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src3_pong_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC3_PONG_CMD_ADDR1 ((0x0061 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src3_pong_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC3_PONG_DST_ADDR1 ((0x0062 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src3_pong_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC3_PONG_TASK1 ((0x0063 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src3_pong_task1_valid , default = 0, task valid
+//Bit 30, reg_src3_pong_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src3_pong_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC4_CTL ((0x0064 << 2) + 0xfe3bbc00)
+//Bit 3, reg_src_pingpong_force_val , default = 0, src4 pingpong force sel
+//Bit 2, reg_src_pingpong_force , default = 0, src4 pingpong force enable
+//Bit 1, reg_src_pingpong_ini , default = 0, src4 pingpong initial sel
+//Bit 0, reg_src4_en , default = 0, src0 enable
+#define MIPI_DMA_SRC4_PING_CMD_ADDR0 ((0x0065 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src4_ping_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC4_PING_DST_ADDR0 ((0x0066 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src4_ping_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC4_PING_TASK0 ((0x0067 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src4_ping_task0_valid , default = 0, task valid
+//Bit 30, reg_src4_ping_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src4_ping_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC4_PING_CMD_ADDR1 ((0x0068 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src4_ping_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC4_PING_DST_ADDR1 ((0x0069 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src4_ping_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC4_PING_TASK1 ((0x006a << 2) + 0xfe3bbc00)
+//Bit 31, reg_src4_ping_task1_valid , default = 0, task valid
+//Bit 30, reg_src4_ping_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src4_ping_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC4_PONG_CMD_ADDR0 ((0x006b << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src4_pong_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC4_PONG_DST_ADDR0 ((0x006c << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src4_pong_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC4_PONG_TASK0 ((0x006d << 2) + 0xfe3bbc00)
+//Bit 31, reg_src4_pong_task0_valid , default = 0, task valid
+//Bit 30, reg_src4_pong_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src4_pong_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC4_PONG_CMD_ADDR1 ((0x006e << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src4_pong_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC4_PONG_DST_ADDR1 ((0x006f << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src4_pong_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC4_PONG_TASK1 ((0x0070 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src4_pong_task1_valid , default = 0, task valid
+//Bit 30, reg_src4_pong_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src4_pong_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC5_CTL ((0x0071 << 2) + 0xfe3bbc00)
+//Bit 3, reg_src_pingpong_force_val , default = 0, src5 pingpong force sel
+//Bit 2, reg_src_pingpong_force , default = 0, src5 pingpong force enable
+//Bit 1, reg_src_pingpong_ini , default = 0, src5 pingpong initial sel
+//Bit 0, reg_src5_en , default = 0, src0 enable
+#define MIPI_DMA_SRC5_PING_CMD_ADDR0 ((0x0072 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src5_ping_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC5_PING_DST_ADDR0 ((0x0073 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src5_ping_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC5_PING_TASK0 ((0x0074 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src5_ping_task0_valid , default = 0, task valid
+//Bit 30, reg_src5_ping_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src5_ping_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC5_PING_CMD_ADDR1 ((0x0075 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src5_ping_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC5_PING_DST_ADDR1 ((0x0076 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src5_ping_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC5_PING_TASK1 ((0x0077 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src5_ping_task1_valid , default = 0, task valid
+//Bit 30, reg_src5_ping_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src5_ping_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC5_PONG_CMD_ADDR0 ((0x0078 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src5_pong_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC5_PONG_DST_ADDR0 ((0x0079 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src5_pong_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC5_PONG_TASK0 ((0x007a << 2) + 0xfe3bbc00)
+//Bit 31, reg_src5_pong_task0_valid , default = 0, task valid
+//Bit 30, reg_src5_pong_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src5_pong_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC5_PONG_CMD_ADDR1 ((0x007b << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src5_pong_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC5_PONG_DST_ADDR1 ((0x007c << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src5_pong_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC5_PONG_TASK1 ((0x007d << 2) + 0xfe3bbc00)
+//Bit 31, reg_src5_pong_task1_valid , default = 0, task valid
+//Bit 30, reg_src5_pong_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src5_pong_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC6_CTL ((0x007e << 2) + 0xfe3bbc00)
+//Bit 3, reg_src_pingpong_force_val , default = 0, src6 pingpong force sel
+//Bit 2, reg_src_pingpong_force , default = 0, src6 pingpong force enable
+//Bit 1, reg_src_pingpong_ini , default = 0, src6 pingpong initial sel
+//Bit 0, reg_src6_en , default = 0, src0 enable
+#define MIPI_DMA_SRC6_PING_CMD_ADDR0 ((0x007f << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src6_ping_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC6_PING_DST_ADDR0 ((0x0080 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src6_ping_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC6_PING_TASK0 ((0x0081 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src6_ping_task0_valid , default = 0, task valid
+//Bit 30, reg_src6_ping_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src6_ping_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC6_PING_CMD_ADDR1 ((0x0082 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src6_ping_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC6_PING_DST_ADDR1 ((0x0083 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src6_ping_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC6_PING_TASK1 ((0x0084 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src6_ping_task1_valid , default = 0, task valid
+//Bit 30, reg_src6_ping_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src6_ping_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC6_PONG_CMD_ADDR0 ((0x0085 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src6_pong_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC6_PONG_DST_ADDR0 ((0x0086 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src6_pong_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC6_PONG_TASK0 ((0x0087 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src6_pong_task0_valid , default = 0, task valid
+//Bit 30, reg_src6_pong_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src6_pong_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC6_PONG_CMD_ADDR1 ((0x0088 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src6_pong_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC6_PONG_DST_ADDR1 ((0x0089 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src6_pong_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC6_PONG_TASK1 ((0x008a << 2) + 0xfe3bbc00)
+//Bit 31, reg_src6_pong_task1_valid , default = 0, task valid
+//Bit 30, reg_src6_pong_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src6_pong_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC7_CTL ((0x008b << 2) + 0xfe3bbc00)
+//Bit 3, reg_src_pingpong_force_val , default = 0, src7 pingpong force sel
+//Bit 2, reg_src_pingpong_force , default = 0, src7 pingpong force enable
+//Bit 1, reg_src_pingpong_ini , default = 0, src7 pingpong initial sel
+//Bit 0, reg_src7_en , default = 0, src0 enable
+#define MIPI_DMA_SRC7_PING_CMD_ADDR0 ((0x008c << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src7_ping_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC7_PING_DST_ADDR0 ((0x008d << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src7_ping_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC7_PING_TASK0 ((0x008e << 2) + 0xfe3bbc00)
+//Bit 31, reg_src7_ping_task0_valid , default = 0, task valid
+//Bit 30, reg_src7_ping_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src7_ping_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC7_PING_CMD_ADDR1 ((0x008f << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src7_ping_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC7_PING_DST_ADDR1 ((0x0090 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src7_ping_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC7_PING_TASK1 ((0x0091 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src7_ping_task1_valid , default = 0, task valid
+//Bit 30, reg_src7_ping_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src7_ping_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC7_PONG_CMD_ADDR0 ((0x0092 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src7_pong_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC7_PONG_DST_ADDR0 ((0x0093 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src7_pong_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC7_PONG_TASK0 ((0x0094 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src7_pong_task0_valid , default = 0, task valid
+//Bit 30, reg_src7_pong_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src7_pong_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC7_PONG_CMD_ADDR1 ((0x0095 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src7_pong_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC7_PONG_DST_ADDR1 ((0x0096 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src7_pong_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC7_PONG_TASK1 ((0x0097 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src7_pong_task1_valid , default = 0, task valid
+//Bit 30, reg_src7_pong_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src7_pong_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC8_CTL ((0x0098 << 2) + 0xfe3bbc00)
+//Bit 3, reg_src_pingpong_force_val , default = 0, src8 pingpong force sel
+//Bit 2, reg_src_pingpong_force , default = 0, src8 pingpong force enable
+//Bit 1, reg_src_pingpong_ini , default = 0, src8 pingpong initial sel
+//Bit 0, reg_src8_en , default = 0, src0 enable
+#define MIPI_DMA_SRC8_PING_CMD_ADDR0 ((0x0099 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src8_ping_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC8_PING_DST_ADDR0 ((0x009a << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src8_ping_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC8_PING_TASK0 ((0x009b << 2) + 0xfe3bbc00)
+//Bit 31, reg_src8_ping_task0_valid , default = 0, task valid
+//Bit 30, reg_src8_ping_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src8_ping_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC8_PING_CMD_ADDR1 ((0x009c << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src8_ping_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC8_PING_DST_ADDR1 ((0x009d << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src8_ping_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC8_PING_TASK1 ((0x009e << 2) + 0xfe3bbc00)
+//Bit 31, reg_src8_ping_task1_valid , default = 0, task valid
+//Bit 30, reg_src8_ping_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src8_ping_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC8_PONG_CMD_ADDR0 ((0x009f << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src8_pong_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC8_PONG_DST_ADDR0 ((0x00a0 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src8_pong_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC8_PONG_TASK0 ((0x00a1 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src8_pong_task0_valid , default = 0, task valid
+//Bit 30, reg_src8_pong_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src8_pong_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC8_PONG_CMD_ADDR1 ((0x00a2 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src8_pong_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC8_PONG_DST_ADDR1 ((0x00a3 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src8_pong_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC8_PONG_TASK1 ((0x00a4 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src8_pong_task1_valid , default = 0, task valid
+//Bit 30, reg_src8_pong_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src8_pong_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC9_CTL ((0x00a5 << 2) + 0xfe3bbc00)
+//Bit 3, reg_src_pingpong_force_val , default = 0, src9 pingpong force sel
+//Bit 2, reg_src_pingpong_force , default = 0, src9 pingpong force enable
+//Bit 1, reg_src_pingpong_ini , default = 0, src9 pingpong initial sel
+//Bit 0, reg_src9_en , default = 0, src0 enable
+#define MIPI_DMA_SRC9_PING_CMD_ADDR0 ((0x00a6 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src9_ping_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC9_PING_DST_ADDR0 ((0x00a7 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src9_ping_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC9_PING_TASK0 ((0x00a8 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src9_ping_task0_valid , default = 0, task valid
+//Bit 30, reg_src9_ping_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src9_ping_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC9_PING_CMD_ADDR1 ((0x00a9 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src9_ping_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC9_PING_DST_ADDR1 ((0x00aa << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src9_ping_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC9_PING_TASK1 ((0x00ab << 2) + 0xfe3bbc00)
+//Bit 31, reg_src9_ping_task1_valid , default = 0, task valid
+//Bit 30, reg_src9_ping_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src9_ping_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC9_PONG_CMD_ADDR0 ((0x00ac << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src9_pong_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC9_PONG_DST_ADDR0 ((0x00ad << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src9_pong_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC9_PONG_TASK0 ((0x00ae << 2) + 0xfe3bbc00)
+//Bit 31, reg_src9_pong_task0_valid , default = 0, task valid
+//Bit 30, reg_src9_pong_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src9_pong_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC9_PONG_CMD_ADDR1 ((0x00af << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src9_pong_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC9_PONG_DST_ADDR1 ((0x00b0 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src9_pong_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC9_PONG_TASK1 ((0x00b1 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src9_pong_task1_valid , default = 0, task valid
+//Bit 30, reg_src9_pong_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src9_pong_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC10_CTL ((0x00b2 << 2) + 0xfe3bbc00)
+//Bit 3, reg_src_pingpong_force_val , default = 0, src10 pingpong force sel
+//Bit 2, reg_src_pingpong_force , default = 0, src10 pingpong force enable
+//Bit 1, reg_src_pingpong_ini , default = 0, src10 pingpong initial sel
+//Bit 0, reg_src10_en , default = 0, src0 enable
+#define MIPI_DMA_SRC10_PING_CMD_ADDR0 ((0x00b3 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src10_ping_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC10_PING_DST_ADDR0 ((0x00b4 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src10_ping_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC10_PING_TASK0 ((0x00b5 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src10_ping_task0_valid , default = 0, task valid
+//Bit 30, reg_src10_ping_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src10_ping_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC10_PING_CMD_ADDR1 ((0x00b6 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src10_ping_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC10_PING_DST_ADDR1 ((0x00b7 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src10_ping_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC10_PING_TASK1 ((0x00b8 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src10_ping_task1_valid , default = 0, task valid
+//Bit 30, reg_src10_ping_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src10_ping_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC10_PONG_CMD_ADDR0 ((0x00b9 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src10_pong_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC10_PONG_DST_ADDR0 ((0x00ba << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src10_pong_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC10_PONG_TASK0 ((0x00bb << 2) + 0xfe3bbc00)
+//Bit 31, reg_src10_pong_task0_valid , default = 0, task valid
+//Bit 30, reg_src10_pong_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src10_pong_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC10_PONG_CMD_ADDR1 ((0x00bc << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src10_pong_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC10_PONG_DST_ADDR1 ((0x00bd << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src10_pong_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC10_PONG_TASK1 ((0x00be << 2) + 0xfe3bbc00)
+//Bit 31, reg_src10_pong_task1_valid , default = 0, task valid
+//Bit 30, reg_src10_pong_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src10_pong_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC11_CTL ((0x00bf << 2) + 0xfe3bbc00)
+//Bit 3, reg_src_pingpong_force_val , default = 0, src11 pingpong force sel
+//Bit 2, reg_src_pingpong_force , default = 0, src11 pingpong force enable
+//Bit 1, reg_src_pingpong_ini , default = 0, src11 pingpong initial sel
+//Bit 0, reg_src11_en , default = 0, src0 enable
+#define MIPI_DMA_SRC11_PING_CMD_ADDR0 ((0x00c0 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src11_ping_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC11_PING_DST_ADDR0 ((0x00c1 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src11_ping_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC11_PING_TASK0 ((0x00c2 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src11_ping_task0_valid , default = 0, task valid
+//Bit 30, reg_src11_ping_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src11_ping_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC11_PING_CMD_ADDR1 ((0x00c3 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src11_ping_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC11_PING_DST_ADDR1 ((0x00c4 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src11_ping_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC11_PING_TASK1 ((0x00c5 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src11_ping_task1_valid , default = 0, task valid
+//Bit 30, reg_src11_ping_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src11_ping_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC11_PONG_CMD_ADDR0 ((0x00c6 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src11_pong_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC11_PONG_DST_ADDR0 ((0x00c7 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src11_pong_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC11_PONG_TASK0 ((0x00c8 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src11_pong_task0_valid , default = 0, task valid
+//Bit 30, reg_src11_pong_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src11_pong_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC11_PONG_CMD_ADDR1 ((0x00c9 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src11_pong_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC11_PONG_DST_ADDR1 ((0x00ca << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src11_pong_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC11_PONG_TASK1 ((0x00cb << 2) + 0xfe3bbc00)
+//Bit 31, reg_src11_pong_task1_valid , default = 0, task valid
+//Bit 30, reg_src11_pong_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src11_pong_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC12_CTL ((0x00cc << 2) + 0xfe3bbc00)
+//Bit 3, reg_src_pingpong_force_val , default = 0, src12 pingpong force sel
+//Bit 2, reg_src_pingpong_force , default = 0, src12 pingpong force enable
+//Bit 1, reg_src_pingpong_ini , default = 0, src12 pingpong initial sel
+//Bit 0, reg_src12_en , default = 0, src0 enable
+#define MIPI_DMA_SRC12_PING_CMD_ADDR0 ((0x00cd << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src12_ping_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC12_PING_DST_ADDR0 ((0x00ce << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src12_ping_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC12_PING_TASK0 ((0x00cf << 2) + 0xfe3bbc00)
+//Bit 31, reg_src12_ping_task0_valid , default = 0, task valid
+//Bit 30, reg_src12_ping_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src12_ping_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC12_PING_CMD_ADDR1 ((0x00d0 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src12_ping_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC12_PING_DST_ADDR1 ((0x00d1 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src12_ping_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC12_PING_TASK1 ((0x00d2 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src12_ping_task1_valid , default = 0, task valid
+//Bit 30, reg_src12_ping_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src12_ping_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC12_PONG_CMD_ADDR0 ((0x00d3 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src12_pong_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC12_PONG_DST_ADDR0 ((0x00d4 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src12_pong_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC12_PONG_TASK0 ((0x00d5 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src12_pong_task0_valid , default = 0, task valid
+//Bit 30, reg_src12_pong_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src12_pong_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC12_PONG_CMD_ADDR1 ((0x00d6 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src12_pong_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC12_PONG_DST_ADDR1 ((0x00d7 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src12_pong_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC12_PONG_TASK1 ((0x00d8 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src12_pong_task1_valid , default = 0, task valid
+//Bit 30, reg_src12_pong_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src12_pong_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC13_CTL ((0x00d9 << 2) + 0xfe3bbc00)
+//Bit 3, reg_src_pingpong_force_val , default = 0, src13 pingpong force sel
+//Bit 2, reg_src_pingpong_force , default = 0, src13 pingpong force enable
+//Bit 1, reg_src_pingpong_ini , default = 0, src13 pingpong initial sel
+//Bit 0, reg_src13_en , default = 0, src0 enable
+#define MIPI_DMA_SRC13_PING_CMD_ADDR0 ((0x00da << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src13_ping_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC13_PING_DST_ADDR0 ((0x00db << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src13_ping_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC13_PING_TASK0 ((0x00dc << 2) + 0xfe3bbc00)
+//Bit 31, reg_src13_ping_task0_valid , default = 0, task valid
+//Bit 30, reg_src13_ping_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src13_ping_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC13_PING_CMD_ADDR1 ((0x00dd << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src13_ping_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC13_PING_DST_ADDR1 ((0x00de << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src13_ping_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC13_PING_TASK1 ((0x00df << 2) + 0xfe3bbc00)
+//Bit 31, reg_src13_ping_task1_valid , default = 0, task valid
+//Bit 30, reg_src13_ping_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src13_ping_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC13_PONG_CMD_ADDR0 ((0x00e0 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src13_pong_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC13_PONG_DST_ADDR0 ((0x00e1 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src13_pong_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC13_PONG_TASK0 ((0x00e2 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src13_pong_task0_valid , default = 0, task valid
+//Bit 30, reg_src13_pong_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src13_pong_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC13_PONG_CMD_ADDR1 ((0x00e3 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src13_pong_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC13_PONG_DST_ADDR1 ((0x00e4 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src13_pong_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC13_PONG_TASK1 ((0x00e5 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src13_pong_task1_valid , default = 0, task valid
+//Bit 30, reg_src13_pong_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src13_pong_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC14_CTL ((0x00e6 << 2) + 0xfe3bbc00)
+//Bit 3, reg_src_pingpong_force_val , default = 0, src14 pingpong force sel
+//Bit 2, reg_src_pingpong_force , default = 0, src14 pingpong force enable
+//Bit 1, reg_src_pingpong_ini , default = 0, src14 pingpong initial sel
+//Bit 0, reg_src14_en , default = 0, src0 enable
+#define MIPI_DMA_SRC14_PING_CMD_ADDR0 ((0x00e7 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src14_ping_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC14_PING_DST_ADDR0 ((0x00e8 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src14_ping_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC14_PING_TASK0 ((0x00e9 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src14_ping_task0_valid , default = 0, task valid
+//Bit 30, reg_src14_ping_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src14_ping_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC14_PING_CMD_ADDR1 ((0x00ea << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src14_ping_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC14_PING_DST_ADDR1 ((0x00eb << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src14_ping_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC14_PING_TASK1 ((0x00ec << 2) + 0xfe3bbc00)
+//Bit 31, reg_src14_ping_task1_valid , default = 0, task valid
+//Bit 30, reg_src14_ping_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src14_ping_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC14_PONG_CMD_ADDR0 ((0x00ed << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src14_pong_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC14_PONG_DST_ADDR0 ((0x00ee << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src14_pong_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC14_PONG_TASK0 ((0x00ef << 2) + 0xfe3bbc00)
+//Bit 31, reg_src14_pong_task0_valid , default = 0, task valid
+//Bit 30, reg_src14_pong_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src14_pong_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC14_PONG_CMD_ADDR1 ((0x00f0 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src14_pong_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC14_PONG_DST_ADDR1 ((0x00f1 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src14_pong_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC14_PONG_TASK1 ((0x00f2 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src14_pong_task1_valid , default = 0, task valid
+//Bit 30, reg_src14_pong_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src14_pong_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC15_CTL ((0x00f3 << 2) + 0xfe3bbc00)
+//Bit 3, reg_src_pingpong_force_val , default = 0, src15 pingpong force sel
+//Bit 2, reg_src_pingpong_force , default = 0, src15 pingpong force enable
+//Bit 1, reg_src_pingpong_ini , default = 0, src15 pingpong initial sel
+//Bit 0, reg_src15_en , default = 0, src0 enable
+#define MIPI_DMA_SRC15_PING_CMD_ADDR0 ((0x00f4 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src15_ping_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC15_PING_DST_ADDR0 ((0x00f5 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src15_ping_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC15_PING_TASK0 ((0x00f6 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src15_ping_task0_valid , default = 0, task valid
+//Bit 30, reg_src15_ping_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src15_ping_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC15_PING_CMD_ADDR1 ((0x00f7 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src15_ping_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC15_PING_DST_ADDR1 ((0x00f8 << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src15_ping_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC15_PING_TASK1 ((0x00f9 << 2) + 0xfe3bbc00)
+//Bit 31, reg_src15_ping_task1_valid , default = 0, task valid
+//Bit 30, reg_src15_ping_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src15_ping_len1 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC15_PONG_CMD_ADDR0 ((0x00fa << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src15_pong_cmd_addr0 , default = 0, source0/task0 cmd address
+#define MIPI_DMA_SRC15_PONG_DST_ADDR0 ((0x00fb << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src15_pong_dst_addr0 , default = 0, source0/task0 dst address,for apb read only
+#define MIPI_DMA_SRC15_PONG_TASK0 ((0x00fc << 2) + 0xfe3bbc00)
+//Bit 31, reg_src15_pong_task0_valid , default = 0, task valid
+//Bit 30, reg_src15_pong_type0 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src15_pong_len0 , default = 0, cmd length,N-1 words
+#define MIPI_DMA_SRC15_PONG_CMD_ADDR1 ((0x00fd << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src15_pong_cmd_addr1 , default = 0, source0/task1 cmd address
+#define MIPI_DMA_SRC15_PONG_DST_ADDR1 ((0x00fe << 2) + 0xfe3bbc00)
+//Bit 31:0, reg_src15_pong_dst_addr1 , default = 0, source0/task1 dst address,for apb read only
+#define MIPI_DMA_SRC15_PONG_TASK1 ((0x00ff << 2) + 0xfe3bbc00)
+//Bit 31, reg_src15_pong_task1_valid , default = 0, task valid
+//Bit 30, reg_src15_pong_type1 , default = 0, task type,1 apb write 0 apb read
+//Bit 29:16, reserved
+//Bit 15:0, reg_src15_pong_len1 , default = 0, cmd length,N-1 words
+//
+// Closing file: mipi_apb_dma.h
+//
+//========================================================================
+// MIPI_ISP top wrapper cfg
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3bdc00
+// -----------------------------------------------
+#define MIPI_CSI_PHY_CNTL0 ((0x0000 << 2) + 0xfe3bdc00)
+#define MIPI_CSI_PHY_CNTL1 ((0x0001 << 2) + 0xfe3bdc00)
+#define MIPI_CSI_PHY_CNTL2 ((0x0002 << 2) + 0xfe3bdc00)
+#define MIPI_CSI_PHY_CNTL3 ((0x0003 << 2) + 0xfe3bdc00)
+#define MIPI_CSI_PHY_CNTL4 ((0x0004 << 2) + 0xfe3bdc00)
+#define MIPI_CSI_PHY_CNTL5 ((0x0005 << 2) + 0xfe3bdc00)
+#define MIPI_CSI_PHY_CNTL6 ((0x0006 << 2) + 0xfe3bdc00)
+#define MIPI_CSI_PHY_CNTL7 ((0x0007 << 2) + 0xfe3bdc00)
+#define MIPI_CSI_PHY_CNTL_I ((0x0010 << 2) + 0xfe3bdc00)
+#define MIPI_ISP_MAX_ADDR_CNTL ((0x0020 << 2) + 0xfe3bdc00)
+#define MIPI_CSI_CFG_CNTL0 ((0x0021 << 2) + 0xfe3bdc00)
+//========================================================================
+// MIPI_ISP HOST3
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3be000
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP HOST2
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3be400
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP HOST1
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3be800
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP HOST0
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3bec00
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP DPHY3
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3bf000
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP DPHY2
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3bf400
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP DPHY1
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3bf800
+// -----------------------------------------------
+//========================================================================
+// MIPI_ISP DPHY0
+//========================================================================
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe3bfc00
+// -----------------------------------------------
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: mipi_isp.h
+//
+//
+// Reading file: mipi_isp_arb_axi_regs.h
+//
+//========================================================================
+// MIPI_ISP axi arbit0
+//========================================================================
+#define MIPI_ISP_RDARB_MODE ((0x0000 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_RDARB_REQEN_SLV ((0x0001 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_RDARB_WEIGH0_SLV ((0x0002 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_RDARB_WEIGH1_SLV ((0x0003 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_RDARB_UGT ((0x0004 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_RDARB_LIMT0 ((0x0005 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_WRARB_MODE ((0x0006 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_WRARB_REQEN_SLV ((0x0007 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_WRARB_WEIGH0_SLV ((0x0008 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_WRARB_WEIGH1_SLV ((0x0009 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_WRARB_UGT ((0x000a << 2) + 0xfe3bfc00)
+#define MIPI_ISP_RDWR_ARB_STATUS ((0x000b << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_DBG_CTRL ((0x000c << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_DBG_STAT ((0x000d << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_WBUS_PROT_CNTL0 ((0x0080 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_RBUS_PROT_CNTL0 ((0x0088 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_WBUS_PROT_STAT0 ((0x0090 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_WBUS_PROT_STAT1 ((0x0091 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_WBUS_PROT_STAT2 ((0x0092 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_WBUS_PROT_STAT3 ((0x0093 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_WBUS_PROT_STAT4 ((0x0094 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_WBUS_PROT_STAT5 ((0x0095 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_WBUS_PROT_STAT6 ((0x0096 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_WBUS_PROT_STAT7 ((0x0097 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_RBUS_PROT_STAT0 ((0x0098 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_RBUS_PROT_STAT1 ((0x0099 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_RBUS_PROT_STAT2 ((0x009a << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_RBUS_PROT_STAT3 ((0x009b << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_RBUS_PROT_STAT4 ((0x009c << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_RBUS_PROT_STAT5 ((0x009d << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_RBUS_PROT_STAT6 ((0x009e << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_RBUS_PROT_STAT7 ((0x009f << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_AXI_BUS_CNTL0 ((0x00b0 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_AXI_BUS_CNTL1 ((0x00b1 << 2) + 0xfe3bfc00)
+#define MIPI_ISP_ARB_AXI_BUS_STAT0 ((0x00b2 << 2) + 0xfe3bfc00)
+//
+// Closing file: mipi_isp_arb_axi_regs.h
+//
+//`include "mipi_adapt_cmpr_regs.h"
+//`include "mipi_tnr_cmpr_regs.h"
+//`include "mipi_tnr_meta_mif_regs.h"
+//========================================================================
+// DEWRAP/AML_GDC
+//========================================================================
+//
+// Reading file: isp_dwap_top_reg.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: REGISTER_BASE_ADDR = 0xfe040000
+// -----------------------------------------------
+#define ISP_DWAP_TOP_SRC_FSIZE ((0x0000 << 2) + 0xfe040000)
+//Bit 31: 16 reg_src_frm_hsize // unsigned , RW, default = 1280
+//Bit 15: 0 reg_src_frm_vsize // unsigned , RW, default = 720
+//
+#define ISP_DWAP_TOP_HDNUM ((0x0001 << 2) + 0xfe040000)
+//Bit 31: 26 reserved
+//Bit 25: 13 reg_hold_hnum // unsigned , RW, default = 2
+//Bit 12: 0 reg_hold_vnum // unsigned , RW, default = 2
+#define ISP_DWAP_TOP_CTRL0 ((0x0002 << 2) + 0xfe040000)
+//Bit 31 pls_frm_rst //unsigned, RW, default=0
+//Bit 30 pls_sw_rst //unsigned, RW, default=0
+//Bit 29 reserved
+//Bit 28:16 reg_stdly_num //unsigned, RW, default=2
+//Bit 15:6 reserved
+//Bit 5 reg_sec_ctrl //unsigned, RW, default=0
+//Bit 4 reg_hs_sel //unsigned, RW, default=0
+//Bit 3:2 reg_din_sel //unsigned, RW, default=1, dos vidin select
+//Bit 1 reserved
+//Bit 0 reg_frm_sel //unsigned, RW, default=0, must be set before pls_frm_rst
+#define ISP_DWAP_TOP_COEF_CTRL0 ((0x0003 << 2) + 0xfe040000)
+//Bit 31:0 reg_coef_baddr //unsigned, RW, default=0
+//
+#define ISP_DWAP_TOP_COEF_CTRL1 ((0x0004 << 2) + 0xfe040000)
+//Bit 31:16 reserved
+//Bit 15:0 reg_coef_size //unsigned, RW, default=0
+#define ISP_DWAP_TOP_CMD_CTRL0 ((0x0005 << 2) + 0xfe040000)
+//Bit 31:0 reg_cmd_baddr //unsigned, RW, default=0
+#define ISP_DWAP_TOP_CMD_CTRL1 ((0x0006 << 2) + 0xfe040000)
+//Bit 31:16 reserved
+//Bit 15:0 reg_cmd_size //unsigned, RW, default=0
+#define ISP_DWAP_TOP_SRC_Y_CTRL0 ((0x0007 << 2) + 0xfe040000)
+//Bit 31:0 reg_src_y_baddr //unsigned, RW, default=0
+//
+#define ISP_DWAP_TOP_SRC_Y_CTRL1 ((0x0008 << 2) + 0xfe040000)
+//Bit 31:16 reserved
+//Bit 15:0 reg_src_y_stride //unsigned, RW, default=0
+#define ISP_DWAP_TOP_SRC_U_CTRL0 ((0x0009 << 2) + 0xfe040000)
+//Bit 31:0 reg_src_u_baddr //unsigned, RW, default=0
+//
+#define ISP_DWAP_TOP_SRC_U_CTRL1 ((0x000a << 2) + 0xfe040000)
+//Bit 31:16 reserved
+//Bit 15:0 reg_src_u_stride //unsigned, RW, default=0
+#define ISP_DWAP_TOP_SRC_V_CTRL0 ((0x000b << 2) + 0xfe040000)
+//Bit 31:0 reg_src_v_baddr //unsigned, RW, default=0
+//
+#define ISP_DWAP_TOP_SRC_V_CTRL1 ((0x000c << 2) + 0xfe040000)
+//Bit 31:16 reserved
+//Bit 15:0 reg_src_v_stride //unsigned, RW, default=0
+#define ISP_DWAP_TOP_MESH_CTRL0 ((0x000d << 2) + 0xfe040000)
+//Bit 31:0 reg_mesh_baddr //unsigned, RW, default=0
+//
+#define ISP_DWAP_TOP_MESH_CTRL1 ((0x000e << 2) + 0xfe040000)
+//Bit 31:16 reserved
+//Bit 15:0 reg_mesh_stride //unsigned, RW, default=0
+//
+#define ISP_DWAP_TOP_GCLK ((0x000f << 2) + 0xfe040000)
+//Bit 31:0 reg_gclk_ctrl //unsigned, RW, default=0
+#define ISP_DWAP_TOP_DST_FSIZE ((0x0010 << 2) + 0xfe040000)
+//Bit 31: 16 reg_dst_frm_hsize // unsigned , RW, default = 1280
+//Bit 15: 0 reg_dst_frm_vsize // unsigned , RW, default = 720
+#define ISP_DWAP_TOP_BLK_NUM ((0x0011 << 2) + 0xfe040000)
+//Bit 31: 16 reg_edge_num // unsigned, RW, default = 0
+//Bit 15: 0 reg_blk_num // unsigned , RW, default = 256
+#define ISP_DWAP_TOP_MESH_SIZE ((0x0012 << 2) + 0xfe040000)
+//Bit 31: 16 reg_mesh_hsize // unsigned, RW, default = 32
+//Bit 15: 0 reg_mesh_vsize // unsigned, RW, default = 32
+#define ISP_DWAP_TOP_DST_Y_CTRL0 ((0x0013 << 2) + 0xfe040000)
+//Bit 31:0 reg_dst_y_baddr //unsigned, RW, default=0
+//
+#define ISP_DWAP_TOP_DST_Y_CTRL1 ((0x0014 << 2) + 0xfe040000)
+//Bit 31:16 reserved
+//Bit 15:0 reg_dst_y_stride //unsigned, RW, default=1024
+#define ISP_DWAP_TOP_DST_U_CTRL0 ((0x0015 << 2) + 0xfe040000)
+//Bit 31:0 reg_dst_u_baddr //unsigned, RW, default=0
+//
+#define ISP_DWAP_TOP_DST_U_CTRL1 ((0x0016 << 2) + 0xfe040000)
+//Bit 31:16 reserved
+//Bit 15:0 reg_dst_u_stride //unsigned, RW, default=1024
+#define ISP_DWAP_TOP_DST_V_CTRL0 ((0x0017 << 2) + 0xfe040000)
+//Bit 31:0 reg_dst_v_baddr //unsigned, RW, default=0
+//
+#define ISP_DWAP_TOP_DST_V_CTRL1 ((0x0018 << 2) + 0xfe040000)
+//Bit 31:16 reserved
+//Bit 15:0 reg_dst_v_stride //unsigned, RW, default=1024
+#define ISP_DWAP_TOP_ERR_CTRL ((0x0019 << 2) + 0xfe040000)
+//Bit 31:1 reserved
+//Bit 0 pls_err_clr // unsigned, RW, default=0
+//
+#define ISP_DWAP_TOP_CMD_ERR ((0x001a << 2) + 0xfe040000)
+//Bit 31:0 ro_cmd_err // unsigned, RO, default=0
+#define ISP_DWAP_TOP_MESH_ERR ((0x001b << 2) + 0xfe040000)
+//Bit 31:0 ro_mesh_num_err // unsigned, RO, default=0
+#define ISP_DWAP_TOP_OFLOW_ERR0 ((0x001c << 2) + 0xfe040000)
+//Bit 31:0 ro_oflow_err0 // unsigned, RO, default=0
+#define ISP_DWAP_TOP_OFLOW_ERR1 ((0x001d << 2) + 0xfe040000)
+//Bit 31:0 ro_oflow_err1 // unsigned, RO, default=0
+#define ISP_DWAP_TOP_OFLOW_ERR2 ((0x001e << 2) + 0xfe040000)
+//Bit 31:0 ro_oflow_err2 // unsigned, RO, default=0
+#define ISP_DWAP_TOP_OFLOW_ERR3 ((0x001f << 2) + 0xfe040000)
+//Bit 31:0 ro_oflow_err3 // unsigned, RO, default=0
+#define ISP_DWAP_TOP_VSPLT_8LN ((0x0020 << 2) + 0xfe040000)
+//Bit 31:0 ro_vsplt_8ln // unsigned, RO, default=0
+#define ISP_DWAP_TOP_VSPLT_4LN ((0x0021 << 2) + 0xfe040000)
+//Bit 31:0 ro_vsplt_4ln // unsigned, RO, default=0
+#define ISP_DWAP_TOP_ERR ((0x0022 << 2) + 0xfe040000)
+//Bit 31:2 reserved
+//Bit 1 ro_frm_sel_err // unsigned, RO, default=0
+//Bit 0 ro_bresp_err // unsigned, RO, default=0
+#define ISP_DWAP_TOP_PERF ((0x0023 << 2) + 0xfe040000)
+//Bit 31:0 ro_proc_time // unsigned, RO, default=0
+#define ISP_DWAP_DDR_VCNT ((0x0024 << 2) + 0xfe040000)
+//Bit 31:17 reserved
+//Bit 16 reg_ddr_vcnt_mode // unsigned, RW, default=0
+//Bit 15:0 reg_ddr_vcnt // unsigned, RW, default=16'hffff
+#define ISP_DWAP_COEF_LD_TIME ((0x0025 << 2) + 0xfe040000)
+//Bit 31:0 ro_coef_ld_time // unsigned, RO, default=0
+#define ISP_DWAP_MESH_LD_TIME ((0x0026 << 2) + 0xfe040000)
+//Bit 31:0 ro_mesh_ld_time // unsigned, RO, default=0
+#define ISP_DWAP_DATA_LD_TIME ((0x0027 << 2) + 0xfe040000)
+//Bit 31:0 ro_data_ld_time // unsigned, RO, default=0
+#define ISP_DWAP_TILE_PROC_TIME ((0x0028 << 2) + 0xfe040000)
+//Bit 31:0 ro_tile_proc_time // unsigned, RO, default=0
+#define ISP_DWAP_EDGE_PROC_TIME ((0x0029 << 2) + 0xfe040000)
+//Bit 31:0 ro_edge_proc_time // unsigned, RO, default=0
+#define ISP_DWAP_WAIT_RST_TIME ((0x002a << 2) + 0xfe040000)
+//Bit 31:0 ro_wait_rst_time // unsigned, RO, default=0
+#define ISP_DWAP_CMD_SWAP ((0x002b << 2) + 0xfe040000)
+//Bit 31:7 reserved
+//Bit 6 reg_data_little_endian // unsigned, RW, default=0
+//Bit 5 reg_data_swap8 // unsigned, RW, default=0
+//Bit 4 reg_coef_swap32 // unsigned, RW, default=0
+//Bit 3 reg_coef_swap16 // unsigned, RW, default=0
+//Bit 2 reg_mesh_swap32 // unsigned, RW, default=0
+//Bit 1 reg_cmd_swap64 // unsigned, RW, default=0
+//Bit 0 reg_cmd_swap32 // unsigned, RW, default=0
+//
+// Reading file: isp_dwap_mif_reg.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define ISP_DWAP_WMIF_CTRL1 ((0x0030 << 2) + 0xfe040000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_sync_sel // unsigned , default = 0, axi canvas id sync with frm rst
+//Bit 23:16 reg_canvas_id // unsigned , default = 0, axi canvas id num
+//Bit 15 reserved
+//Bit 14:12 reg_cmd_intr_len // unsigned , default = 1, interrupt send cmd when how many series axi cmd,
+ // 0=12 1=16 2=24 3=32 4=40 5=48 6=56 7=64
+//Bit 11:10 reg_cmd_req_size // unsigned , default = 1, how many room fifo have, then axi send series req, 0=16 1=32 2=24 3=64
+//Bit 9:8 reg_burst_len // unsigned , default = 2, burst type: 0-single 1-bst2 2-bst4
+//Bit 7 reg_swap_64bit // unsigned , default = 0, 64bits of 128bit swap enable
+//Bit 6 reg_little_endian // unsigned , default = 1, big endian enable
+//Bit 5 reg_y_rev // unsigned , default = 0, vertical reverse enable
+//Bit 4 reg_x_rev // unsigned , default = 0, horizontal reverse enable
+//Bit 3 reserved
+//Bit 2:0 reg_pack_mode // unsigned , default = 3, 0:4bit 1:8bit 2:16bit 3:32bit 4:64bit 5:128bit
+#define ISP_DWAP_WMIF_CTRL2 ((0x0031 << 2) + 0xfe040000)
+//Bit 31:30 reg_sw_rst // unsigned , default = 0,
+//Bit 29:22 reserved
+//Bit 21:20 reg_int_clr // unsigned , default = 0
+//Bit 19:18 reg_gclk_ctrl // unsigned , default = 0,
+//Bit 17 reserved
+//Bit 16:0 reg_urgent_ctrl // unsigned , default = 0, urgent control reg :
+ // 16 reg_ugt_init : urgent initial value
+ // 15 reg_ugt_en : urgent enable
+ // 14 reg_ugt_type : 1= wrmif 0=wrmif
+ // 7:4 reg_ugt_top_th: urgent top threshold
+ // 3:0 reg_ugt_bot_th: urgent bottom threshold
+#define ISP_DWAP_WMIF_CTRL3 ((0x0032 << 2) + 0xfe040000)
+//Bit 31 reserved
+//Bit 30 reg_hold_en // unsigned , default = 0
+//Bit 29:24 reg_pass_num // unsigned , default = 1
+//Bit 23:18 reg_hold_num // unsigned , default = 0
+//Bit 17 reserved
+//Bit 16 reg_acc_mode // unsigned , default = 1,
+//Bit 15:13 reserved
+//Bit 12:0 reg_stride // unsigned , default = 4096,
+#define ISP_DWAP_WMIF_CTRL4 ((0x0033 << 2) + 0xfe040000)
+//Bit 31:0 reg_baddr // unsigned , default = 0,
+#define ISP_DWAP_WMIF_SCOPE_X ((0x0034 << 2) + 0xfe040000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_x_end // unsigned , default = 4095, the canvas hor end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_x_start // unsigned , default = 0, the canvas hor start pixel position
+#define ISP_DWAP_WMIF_SCOPE_Y ((0x0035 << 2) + 0xfe040000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_y_end // unsigned , default = 0, the canvas ver end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_y_start // unsigned , default = 0, the canvas ver start pixel positio
+#define ISP_DWAP_WMIF_RO_STAT ((0x0036 << 2) + 0xfe040000)
+//Bit 31:16 reserved
+//Bit 15:0 reg_status // unsigned ,
+#define ISP_DWAP_RMIF_CTRL1 ((0x0040 << 2) + 0xfe040000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_sync_sel // unsigned , default = 0, axi canvas id sync with frm rst
+//Bit 23:16 reg_canvas_id // unsigned , default = 0, axi canvas id num
+//Bit 15 reserved
+//Bit 14:12 reg_cmd_intr_len // unsigned , default = 1, interrupt send cmd when how many series axi cmd,
+ // 0=12 1=16 2=24 3=32 4=40 5=48 6=56 7=64
+//Bit 11:10 reg_cmd_req_size // unsigned , default = 1, how many room fifo have, then axi send series req, 0=16 1=32 2=24 3=64
+//Bit 9:8 reg_burst_len // unsigned , default = 2, burst type: 0-single 1-bst2 2-bst4
+//Bit 7 reg_swap_64bit // unsigned , default = 0, 64bits of 128bit swap enable
+//Bit 6 reg_little_endian // unsigned , default = 1, big endian enable
+//Bit 5 reg_y_rev // unsigned , default = 0, vertical reverse enable
+//Bit 4 reg_x_rev // unsigned , default = 0, horizontal reverse enable
+//Bit 3 reserved
+//Bit 2:0 reg_pack_mode // unsigned , default = 3, 0:4bit 1:8bit 2:16bit 3:32bit 4:64bit 5:128bit
+#define ISP_DWAP_RMIF_CTRL2 ((0x0041 << 2) + 0xfe040000)
+//Bit 31:30 reg_sw_rst // unsigned , default = 0,
+//Bit 29:26 reserved
+//Bit 25:22 reg_vstep // unsigned , default = 1
+//Bit 21:20 reg_int_clr // unsigned , default = 0
+//Bit 19:18 reg_gclk_ctrl // unsigned , default = 0,
+//Bit 17 reserved
+//Bit 16:0 reg_urgent_ctrl // unsigned , default = 0, urgent control reg :
+ // 16 reg_ugt_init : urgent initial value
+ // 15 reg_ugt_en : urgent enable
+ // 14 reg_ugt_type : 1= wrmif 0=rdmif
+ // 7:4 reg_ugt_top_th: urgent top threshold
+ // 3:0 reg_ugt_bot_th: urgent bottom threshold
+#define ISP_DWAP_RMIF_CTRL3 ((0x0042 << 2) + 0xfe040000)
+//Bit 31 reserved
+//Bit 30 reg_hold_en // unsigned , default = 0
+//Bit 29:24 reg_pass_num // unsigned , default = 1
+//Bit 23:18 reg_hold_num // unsigned , default = 0
+//Bit 17 reserved
+//Bit 16 reg_acc_mode // unsigned , default = 1,
+//Bit 15:13 reserved
+//Bit 12:0 reg_stride // unsigned , default = 4096,
+#define ISP_DWAP_RMIF_CTRL4 ((0x0043 << 2) + 0xfe040000)
+//Bit 31:0 reg_baddr // unsigned , default = 0,
+#define ISP_DWAP_RMIF_SCOPE_X ((0x0044 << 2) + 0xfe040000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_x_end // unsigned , default = 4095, the canvas hor end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_x_start // unsigned , default = 0, the canvas hor start pixel position
+#define ISP_DWAP_RMIF_SCOPE_Y ((0x0045 << 2) + 0xfe040000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_y_end // unsigned , default = 0, the canvas ver end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_y_start // unsigned , default = 0, the canvas ver start pixel positio
+#define ISP_DWAP_RMIF_RO_STAT ((0x0046 << 2) + 0xfe040000)
+//Bit 31:16 reserved
+//Bit 15:0 reg_status // unsigned ,
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: isp_dwap_mif_reg.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: isp_dwap_top_reg.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: ./REG_LIST_RTL.h
+//
+//
+// Reading file: ./vcbus_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+//===========================================================================
+//
+// Reading file: rdma_regs.h
+//
+//===========================================================================
+// RDMA registers 0x00 - 0xff
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: RDMA_VCBUS_BASE = 0x11
+// -----------------------------------------------
+// Bit 31: 0 RW AHB start address for manual start DMA
+#define RDMA_AHB_START_ADDR_MAN ((0x1100 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for manual start DMA
+#define RDMA_AHB_END_ADDR_MAN ((0x1101 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 1
+#define RDMA_AHB_START_ADDR_1 ((0x1102 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 1
+#define RDMA_AHB_END_ADDR_1 ((0x1103 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 2
+#define RDMA_AHB_START_ADDR_2 ((0x1104 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 2
+#define RDMA_AHB_END_ADDR_2 ((0x1105 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 3
+#define RDMA_AHB_START_ADDR_3 ((0x1106 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 3
+#define RDMA_AHB_END_ADDR_3 ((0x1107 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 4
+#define RDMA_AHB_START_ADDR_4 ((0x1108 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 4
+#define RDMA_AHB_END_ADDR_4 ((0x1109 << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 5
+#define RDMA_AHB_START_ADDR_5 ((0x110a << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 5
+#define RDMA_AHB_END_ADDR_5 ((0x110b << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 6
+#define RDMA_AHB_START_ADDR_6 ((0x110c << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 6
+#define RDMA_AHB_END_ADDR_6 ((0x110d << 2) + 0xff000000)
+// Bit 31: 0 RW AHB start address for auto start source 7
+#define RDMA_AHB_START_ADDR_7 ((0x110e << 2) + 0xff000000)
+// Bit 31: 0 RW AHB end address for auto start source 7
+#define RDMA_AHB_END_ADDR_7 ((0x110f << 2) + 0xff000000)
+// Auto start DMA control:
+// Bit 31:24 RW ctrl_enable_int_3. Interrupt inputs enable mask for source 3.
+// Bit 23:16 RW ctrl_enable_int_2. Interrupt inputs enable mask for source 2.
+// Bit 15: 8 RW ctrl_enable_int_1. Interrupt inputs enable mask for source 1.
+// Bit 7 RW ctrl_cbus_write_3. Register read/write mode for auto-start 3. 1=Register write; 0=Register read.
+// Bit 6 RW ctrl_cbus_write_3. Register read/write mode for auto-start 2. 1=Register write; 0=Register read.
+// Bit 5 RW ctrl_cbus_write_3. Register read/write mode for auto-start 1. 1=Register write; 0=Register read.
+// Bit 4 R Rsrv.
+// Bit 3 RW ctrl_cbus_addr_incr_3. 1=Incremental register access for auto-start 3; 0=Non-incremental (individual) register access.
+// Bit 2 RW ctrl_cbus_addr_incr_2. 1=Incremental register access for auto-start 2; 0=Non-incremental (individual) register access.
+// Bit 1 RW ctrl_cbus_addr_incr_1. 1=Incremental register access for auto-start 1; 0=Non-incremental (individual) register access.
+// Bit 0 R Rsrv.
+#define RDMA_ACCESS_AUTO ((0x1110 << 2) + 0xff000000)
+#define RDMA_ACCESS_AUTO2 ((0x1111 << 2) + 0xff000000)
+// Manual start DMA control:
+// Bit 31: 3 R Rsrv.
+// Bit 2 RW ctrl_cbus_write_man. Register read/write mode for manual-start. 1=Register write; 0=Register read.
+// Bit 1 RW ctrl_cbus_addr_incr_man. 1=Incremental register access for manual-start; 0=Non-incremental (individual) register access.
+// Bit 0 W ctrl_start_man. Write 1 to this bit to manual-start DMA. This bit always read back 0.
+#define RDMA_ACCESS_MAN ((0x1113 << 2) + 0xff000000)
+// RDMA general control:
+// Bit 31:25 R Rsrv.
+// Bit 24 W ctrl_clr_rdma_done_int. Write 1 to reset rdma_int level to 0. No need to clear this bit.
+// Bit 23:19 R Rsrv.
+// Bit 18:13 R Rsrv.
+// Bit 12: 7 R Rsrv.
+// Bit 6 RW ctrl_ddr_urgent.
+// Bit 5: 4 RW ctrl_ahb_wr_burst_size. 0=ABH write request burst size 16;
+// 1=ABH write request burst size 24;
+// 2=ABH write request burst size 32;
+// 3=ABH write request burst size 48.
+// Bit 3: 2 RW ctrl_ahb_rd_burst_size. 0=ABH read request burst size 16;
+// 1=ABH read request burst size 24;
+// 2=ABH read request burst size 32;
+// 3=ABH read request burst size 48.
+// Bit 1 RW ctrl_sw_reset. 1=Reset RDMA logics except register.
+// Bit 0 RW ctrl_free_clk_enable. 0=Default, Enable clock gating. 1=No clock gating, enable free clock.
+#define RDMA_CTRL ((0x1114 << 2) + 0xff000000)
+// Read only.
+// Bit 31:29 R Rsrv.
+// Bit 28 R rdma_done_int.
+// Bit 27:25 R Rsrv.
+// Bit 24:18 R ahb_wrfifo_cnt. FIFO for buffering CBus read data to be sent to AHB
+// Bit 17:11 R ahb_rdfifo_cnt. FIFO for buffering data read from AHB.
+// Bit 10: 8 R ddr_req_st. =0 -- Idle; !=0 -- AHB interfacing ongoing.
+// Bit 7: 4 R curr_req. Latest requests that is being/been serviced. E.g. 0000=Idle; 0010=Latest serviced request is Req 1.
+// Bit 3: 0 R req_latch. Requests that are yet to be serviced. E.g. 0000=No request; 0001=Req 0 waiting; 1100=Req 2 and 3 waiting.
+#define RDMA_STATUS ((0x1115 << 2) + 0xff000000)
+#define RDMA_STATUS2 ((0x1116 << 2) + 0xff000000)
+#define RDMA_STATUS3 ((0x1117 << 2) + 0xff000000)
+#define RDMA_ACCESS_AUTO4 ((0x1118 << 2) + 0xff000000)
+#define RDMA_SRAM_CNTL ((0x1120 << 2) + 0xff000000)
+#define RDMA_SRAM_REGADDR ((0x1121 << 2) + 0xff000000)
+#define RDMA_SRAM_REGDATA ((0x1122 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC1_SEL ((0x1123 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC2_SEL ((0x1124 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC3_SEL ((0x1125 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC4_SEL ((0x1126 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC5_SEL ((0x1127 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC6_SEL ((0x1128 << 2) + 0xff000000)
+#define RDMA_AUTO_SRC7_SEL ((0x1129 << 2) + 0xff000000)
+// Bit 1: 0 RW AHB start address[33:32] for manual start DMA
+#define RDMA_AHB_START_ADDR_MAN_MSB ((0x1130 << 2) + 0xff000000)
+// Bit 1: 0 RW AHB end address[33:32] for manual start DMA
+#define RDMA_AHB_END_ADDR_MAN_MSB ((0x1131 << 2) + 0xff000000)
+// Bit 1: 0 RW AHB start address[33:32] for auto start source 1
+#define RDMA_AHB_START_ADDR_1_MSB ((0x1132 << 2) + 0xff000000)
+// Bit 1: 0 RW AHB end address[33:32] for auto start source 1
+#define RDMA_AHB_END_ADDR_1_MSB ((0x1133 << 2) + 0xff000000)
+// Bit 1: 0 RW AHB start address[33:32] for auto start source 2
+#define RDMA_AHB_START_ADDR_2_MSB ((0x1134 << 2) + 0xff000000)
+// Bit 1: 0 RW AHB end address[33:32] for auto start source 2
+#define RDMA_AHB_END_ADDR_2_MSB ((0x1135 << 2) + 0xff000000)
+// Bit 1: 0 RW AHB start address[33:32] for auto start source 3
+#define RDMA_AHB_START_ADDR_3_MSB ((0x1136 << 2) + 0xff000000)
+// Bit 1: 0 RW AHB end address[33:32] for auto start source 3
+#define RDMA_AHB_END_ADDR_3_MSB ((0x1137 << 2) + 0xff000000)
+// Bit 1: 0 RW AHB start address[33:32] for auto start source 4
+#define RDMA_AHB_START_ADDR_4_MSB ((0x1138 << 2) + 0xff000000)
+// Bit 1: 0 RW AHB end address[33:32] for auto start source 4
+#define RDMA_AHB_END_ADDR_4_MSB ((0x1139 << 2) + 0xff000000)
+// Bit 1: 0 RW AHB start address[33:32] for auto start source 5
+#define RDMA_AHB_START_ADDR_5_MSB ((0x113a << 2) + 0xff000000)
+// Bit 1: 0 RW AHB end address[33:32] for auto start source 5
+#define RDMA_AHB_END_ADDR_5_MSB ((0x113b << 2) + 0xff000000)
+// Bit 1: 0 RW AHB start address[33:32] for auto start source 6
+#define RDMA_AHB_START_ADDR_6_MSB ((0x113c << 2) + 0xff000000)
+// Bit 1: 0 RW AHB end address[33:32] for auto start source 6
+#define RDMA_AHB_END_ADDR_6_MSB ((0x113d << 2) + 0xff000000)
+// Bit 1: 0 RW AHB start address[33:32] for auto start source 7
+#define RDMA_AHB_START_ADDR_7_MSB ((0x113e << 2) + 0xff000000)
+// Bit 1: 0 RW AHB end address[33:32] for auto start source 7
+#define RDMA_AHB_END_ADDR_7_MSB ((0x113f << 2) + 0xff000000)
+//
+// Closing file: rdma_regs.h
+//
+//===========================================================================
+//===========================================================================
+//
+// Reading file: vpu_vdin0_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+// VDIN
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VDIN0_VCBUS_BASE = 0x12
+// -----------------------------------------------
+//
+// Reading file: vpu_vdin_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+// VDIN
+//===========================================================================
+#define VDIN_SCALE_COEF_IDX ((0x1200 << 2) + 0xff000000)
+#define VDIN_SCALE_COEF ((0x1201 << 2) + 0xff000000)
+//bit 31, mpeg_to_vdin_sel, 0: mpeg source to NR directly, 1: mpeg source pass through here
+//bit 30, mpeg_field info which can be written by software
+//Bit 29, force go_field, pulse signal
+//Bit 28, force go_line, pulse signal
+//Bit 27, enable mpeg_go_field input signal
+//Bit 26:20, hold lines
+//Bit 19, delay go_field function enable
+//Bit 18:12, delay go_field line number
+//Bit 11:10, component2 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in
+//Bit 9:8, component1 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in
+//Bit 7:6, component0 output switch, 00: select component0 in, 01: select component1 in, 10: select component2 in
+//Bit 5, input window selection function enable
+//Bit 4, enable VDIN common data input, otherwise there will be no video data input
+//Bit 3:0 vdin selection, 1: mpeg_in from dram, 2: bt656 input, 3: component input, 4: tvdecoder input, 5: hdmi rx input, 6: digtial video input, 7: loopback from Viu1, 8: MIPI.
+#define VDIN_COM_CTRL0 ((0x1202 << 2) + 0xff000000)
+//Bit 28:16 active_max_pix_cnt, readonly
+//Bit 12:0 active_max_pix_cnt_shadow, readonly
+#define VDIN_ACTIVE_MAX_PIX_CNT_STATUS ((0x1203 << 2) + 0xff000000)
+//Bit 28:16 go_line_cnt, readonly
+//Bit 12:0 active_line_cnt, readonly
+#define VDIN_LCNT_STATUS ((0x1204 << 2) + 0xff000000)
+//Readonly
+//Bit [14:3] lfifo_buf_cnt
+//Bit 2, vdin_direct_done status
+//Bit 1, vdin_nr_done status
+//Bit 0, field
+#define VDIN_COM_STATUS0 ((0x1205 << 2) + 0xff000000)
+//Readonly
+//Bit 31, vdi4 fifo overflow
+//Bit 29:24, vdi3_asfifo_cnt
+//Bit 23, vdi3 fifo overflow
+//Bit 21:16, vdi3_asfifo_cnt
+//Bit 15, vdi2 fifo overflow
+//Bit 13:8, vdi2_asfifo_cnt
+//Bit 7, vdi1 fifo overflow
+//Bit 5:0, vdi1_asfifo_cnt
+#define VDIN_COM_STATUS1 ((0x1206 << 2) + 0xff000000)
+//Bit 28:16 go_line_cnt_shadow, readonly
+//Bit 12:0 active_line_cnt_shadow, readonly
+#define VDIN_LCNT_SHADOW_STATUS ((0x1207 << 2) + 0xff000000)
+//each 8bit asfifo_ctrl is following:
+//Bit 7, DE enable
+//Bit 6, go field enable
+//Bit 5, go line enable
+//Bit 4, if true, negative active input vsync
+//Bit 3, if true, negative active input hsync
+//Bit 2, vsync soft reset fifo enable
+//Bit 1, overflow status clear
+//Bit 0 asfifo soft reset, level signal
+//Bit 7:0 vdi1 asfifo_ctrl
+//Bit 23:16 vdi2 asfifo_ctrl
+#define VDIN_ASFIFO_CTRL0 ((0x1208 << 2) + 0xff000000)
+//Bit 7:0 vdi3 asfifo_ctrl
+//Bit 23:16 vdi4 asfifo_ctrl
+#define VDIN_ASFIFO_CTRL1 ((0x1209 << 2) + 0xff000000)
+//Bit 28:16 input width minus 1, after the window function
+//Bit 12:0 output width minus 1
+#define VDIN_WIDTHM1I_WIDTHM1O ((0x120a << 2) + 0xff000000)
+//Bit 20:17 prehsc_mode, bit 3:2, prehsc odd line interp mode, bit 1:0, prehsc even line interp mode,
+// each 2bit, 00: pix0+pix1/2, average, 01: pix1, 10: pix0
+//Bit 16:15 sp422_mode, special mode for the component1 and component2, 00: normal case, 01: 32 64 32, 10: 0 64 64 0, 11: 16 96 16
+//Bit 14:8, hsc_ini_pixi_ptr, signed data, only useful when short_lineo_en is true
+//Bit 7, prehsc_en
+//Bit 6, hsc_en,
+//Bit 5, hsc_short_lineo_en, short line output enable
+//Bit 4, hsc_nearest_en
+//Bit 3, hsc_phase0_always_en
+//Bit 2:0, hsc_bank_length
+#define VDIN_SC_MISC_CTRL ((0x120b << 2) + 0xff000000)
+//Bit 28:24, integer portion
+//Bit 23:0, fraction portion
+#define VDIN_HSC_PHASE_STEP ((0x120c << 2) + 0xff000000)
+//Bit 30:29 hscale rpt_p0_num
+//Bit 28:24 hscale ini_rcv_num
+//Bit 23:0 hscale ini_phase
+#define VDIN_HSC_INI_CTRL ((0x120d << 2) + 0xff000000)
+//Read only
+//Bit 23, vdi7 fifo overflow
+//Bit 21:16, vdi7_asfifo_cnt
+//Bit 15, vdi6 fifo overflow
+//Bit 13:8, vdi6_asfifo_cnt
+//Bit 7, vdi5 fifo overflow
+//Bit 5:0, vdi5_asfifo_cnt
+#define VDIN_COM_STATUS2 ((0x120e << 2) + 0xff000000)
+//Bit 25:16 asfifo decimate control
+//Bit 25, if true, decimation counter sync with first valid DE in the field,
+//otherwise the decimation counter is not sync with external signal
+//Bit 24, decimation de enable
+//Bit 23:20, decimation phase, which counter value use to decimate,
+//Bit 19:16, decimation number, 0: not decimation, 1: decimation 2, 2: decimation 3 ....
+//Bit 7:0 vdi5 asfifo_ctrl
+#define VDIN_ASFIFO_CTRL2 ((0x120f << 2) + 0xff000000)
+//Bit 7, highlight_en
+//Bit 6 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix
+//Bit 5:4 probe_sel, 00: select matrix 0, 01: select matrix 1, otherwise select nothing
+//Bit 3:2, matrix coef idx selection, 00: select mat0, 01: select mat1, otherwise slect nothing
+//Bit 1 mat1 conversion matrix enable
+//Bit 0 mat0 conversion matrix enable
+#define VDIN_MATRIX_CTRL ((0x1210 << 2) + 0xff000000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define VDIN_MATRIX_COEF00_01 ((0x1211 << 2) + 0xff000000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define VDIN_MATRIX_COEF02_10 ((0x1212 << 2) + 0xff000000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define VDIN_MATRIX_COEF11_12 ((0x1213 << 2) + 0xff000000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define VDIN_MATRIX_COEF20_21 ((0x1214 << 2) + 0xff000000)
+//BIt 18:16 conv_rs
+//Bit 12:0 coef22
+#define VDIN_MATRIX_COEF22 ((0x1215 << 2) + 0xff000000)
+//Bit 26:16 offset0
+//Bit 10:0 offset1
+#define VDIN_MATRIX_OFFSET0_1 ((0x1216 << 2) + 0xff000000)
+//Bit 10:0 offset2
+#define VDIN_MATRIX_OFFSET2 ((0x1217 << 2) + 0xff000000)
+//Bit 26:16 pre_offset0
+//Bit 10:0 pre_offset1
+#define VDIN_MATRIX_PRE_OFFSET0_1 ((0x1218 << 2) + 0xff000000)
+//Bit 10:0 pre_offset2
+#define VDIN_MATRIX_PRE_OFFSET2 ((0x1219 << 2) + 0xff000000)
+//12:0 lfifo_buf_size
+#define VDIN_LFIFO_CTRL ((0x121a << 2) + 0xff000000)
+#define VDIN_COM_GCLK_CTRL ((0x121b << 2) + 0xff000000)
+//12:0 VDIN input interface width minus 1, before the window function, after the de decimation
+#define VDIN_INTF_WIDTHM1 ((0x121c << 2) + 0xff000000)
+//Bit 15 //default== 0, urgent_ctrl_en
+//Bit 14 //default== 0, urgent_wr, if true for write buffer
+//Bit 13 //default== 0, out_inv_en
+//Bit 12 //default == 0, urgent_ini_value
+//Bit 11:6 //default == 0, up_th up threshold
+//Bit 5:0 //default == 0, dn_th dn threshold
+#define VDIN_LFIFO_URG_CTRL ((0x121e << 2) + 0xff000000)
+//Bit 8, 1: discard data before line fifo, 0: normal mode
+//Bit 7:0 Write chroma canvas address
+#define VDIN_WR_CTRL2 ((0x121f << 2) + 0xff000000)
+//Bit 31:30 hconv_mode, Applicable only to bit[13:12]=0 or 2. 0: Output every even pixels' CbCr;
+// 1: Output every odd pixels' CbCr;
+// 2: Output an average value per even&odd pair of pixels;
+// 3: Output all CbCr. (This does NOT apply to bit[13:12]=0 -- 4:2:2 mode.)
+//Bit 29 no_clk_gate: disable vid_wr_mif clock gating function.
+//Bit 28 clear write response counter in the vdin write memory interface
+//Bit 27 eol_sel, 1: use eol as the line end indication, 0: use width as line end indication in the vdin write memory interface
+//Bit 26 vcp_nr_en. Only used in VDIN0. NOT used in VDIN1.
+//Bit 25 vcp_wr_en. Only used in VDIN0. NOT used in VDIN1.
+//Bit 24 vcp_in_en. Only used in VDIN0. NOT used in VDIN1.
+//Bit 23 vdin frame reset enble, if true, it will provide frame reset during go_field(vsync) to the modules after that
+//Bit 22 vdin line fifo soft reset enable, meaning, if true line fifo will reset during go_field (vsync)
+//Bit 21 vdin direct write done status clear bit
+//Bit 20 vdin NR write done status clear bit
+//Bit 18 swap_cbcr. Applicable only to bit[13:12]=2. 0: Output CbCr (NV12); 1: Output CrCb (NV21).
+//Bit 17:16 vconv_mode, Applicable only to bit[13:12]=2. 0: Output every even lines' CbCr;
+// 1: Output every odd lines' CbCr;
+// 2: Reserved;
+// 3: Output all CbCr.
+//Bit 13:12 vdin write format, 0: 4:2:2 to luma canvas, 1: 4:4:4 to luma canvas,
+// 2: Y to luma canvas, CbCr to chroma canvas. For NV12/21, also define Bit 31:30, 17:16, and bit 18.
+//Bit 11 vdin write canvas double buffer enable, means the canvas address will be latched by vsync before using
+//Bit 10 1: disable ctrl_reg write pulse which will reset internal counter. when bit 11 is 1, this bit should be 1.
+//Bit 9 vdin write request urgent
+//Bit 8 vdin write request enable
+//Bit 7:0 Write luma canvas address
+#define VDIN_WR_CTRL ((0x1220 << 2) + 0xff000000)
+//Bit 29, if true, horizontal reverse
+//Bit 28:16 start
+//Bit 12:0 end
+#define VDIN_WR_H_START_END ((0x1221 << 2) + 0xff000000)
+//Bit 29, if true, vertical reverse
+//Bit 28:16 start
+//Bit 15:13 field mode, 0 frame mode, 4 for field mode botton field, 5 for field mode top field, , 6 for blank line mode
+//Bit 12:0 end
+#define VDIN_WR_V_START_END ((0x1222 << 2) + 0xff000000)
+//Bit 24:20, integer portion
+//Bit 19:0, fraction portion
+#define VDIN_VSC_PHASE_STEP ((0x1223 << 2) + 0xff000000)
+//Bit 23, vsc_en, vertical scaler enable
+//Bit 22 if true, repeat last line while scaling, otherwise use the dummy data to extend the input picture
+//Bit 21 vsc_phase0_always_en, when scale up, you have to set it to 1
+//Bit 20:16 ini skip_line_num
+//Bit 15:0 vscaler ini_phase
+#define VDIN_VSC_INI_CTRL ((0x1224 << 2) + 0xff000000)
+//Bit 28:16, vshrink input height minus 1
+//Bit 12:0, scaler input height minus 1
+#define VDIN_SCIN_HEIGHTM1 ((0x1225 << 2) + 0xff000000)
+//Bit 23:16, dummy component 0
+//Bit 15:8, dummy component 1
+//Bit 7:0, dummy component 2
+#define VDIN_DUMMY_DATA ((0x1226 << 2) + 0xff000000)
+//Read only
+//Bit 29:20 component 0
+//Bit 19:10 component 1
+//Bit 9:0 component 2
+#define VDIN_MATRIX_PROBE_COLOR ((0x1228 << 2) + 0xff000000)
+//Bit 23:16 component 0
+//Bit 15:8 component 1
+//Bit 7:0 component 2
+#define VDIN_MATRIX_HL_COLOR ((0x1229 << 2) + 0xff000000)
+//28:16 probe x, postion
+//12:0 probe y, position
+#define VDIN_MATRIX_PROBE_POS ((0x122a << 2) + 0xff000000)
+#define VDIN_CHROMA_ADDR_PORT ((0x122b << 2) + 0xff000000)
+#define VDIN_CHROMA_DATA_PORT ((0x122c << 2) + 0xff000000)
+//
+#define VDIN_CM_BRI_CON_CTRL ((0x122d << 2) + 0xff000000)
+//Bit 17 clk_cyc_cnt_clr, if true, clear this register
+//Bit 16 if true, use vpu clock to count one line, otherwise use actually hsync to count line_cnt
+//Bit 15:0 line width using vpu clk
+#define VDIN_GO_LINE_CTRL ((0x122f << 2) + 0xff000000)
+//Bit 31:24 hist_pix_white_th, larger than this th is counted as white pixel
+//Bit 23:16 hist_pix_black_th, less than this th is counted as black pixel
+//Bit 11 hist_34bin_only, 34 bin only mode, including white/black
+//Bit 10:9 ldim_stts_din_sel, 00: from matrix0 dout, 01: from vsc_dout, 10: from matrix1 dout, 11: form matrix1 din
+//Bit 8 ldim_stts_en
+//Bit 6:5 hist_dnlp_low the real pixels in each bins got by VDIN_DNLP_HISTXX should multiple with 2^(dnlp_low+3)
+//Bit 3:2 hist_din_sel the source used for hist statistics. 00: from matrix0 dout, 01: from vsc_dout, 10: from matrix1 dout, 11: form matrix1 din
+//Bit 1 hist_win_en 1'b0: hist used for full picture; 1'b1: hist used for pixels within hist window
+//Bit 0 hist_spl_en 1'b0: disable hist readback; 1'b1: enable hist readback
+#define VDIN_HIST_CTRL ((0x1230 << 2) + 0xff000000)
+//Bit 28:16 hist_hstart horizontal start value to define hist window
+//Bit 12:0 hist_hend horizontal end value to define hist window
+#define VDIN_HIST_H_START_END ((0x1231 << 2) + 0xff000000)
+//Bit 28:16 hist_vstart vertical start value to define hist window
+//Bit 12:0 hist_vend vertical end value to define hist window
+#define VDIN_HIST_V_START_END ((0x1232 << 2) + 0xff000000)
+//Bit 15:8 hist_max maximum value
+//Bit 7:0 hist_min minimum value
+//read only
+#define VDIN_HIST_MAX_MIN ((0x1233 << 2) + 0xff000000)
+//Bit 31:0 hist_spl_rd
+//counts for the total luma value
+//read only
+#define VDIN_HIST_SPL_VAL ((0x1234 << 2) + 0xff000000)
+//Bit 21:0 hist_spl_pixel_count
+//counts for the total calculated pixels
+//read only
+#define VDIN_HIST_SPL_PIX_CNT ((0x1235 << 2) + 0xff000000)
+//Bit 31:0 hist_chroma_sum
+//counts for the total chroma value
+//read only
+#define VDIN_HIST_CHROMA_SUM ((0x1236 << 2) + 0xff000000)
+//Bit 31:16 higher hist bin
+//Bit 15:0 lower hist bin
+//0-255 are splited to 64 bins evenly, and VDIN_DNLP_HISTXX
+//are the statistic number of pixels that within each bin.
+//VDIN_DNLP_HIST00[15:0] counts for the first bin
+//VDIN_DNLP_HIST00[31:16] counts for the second bin
+//VDIN_DNLP_HIST01[15:0] counts for the third bin
+//VDIN_DNLP_HIST01[31:16] counts for the fourth bin
+//etc...
+//read only
+#define VDIN_DNLP_HIST00 ((0x1237 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST01 ((0x1238 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST02 ((0x1239 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST03 ((0x123a << 2) + 0xff000000)
+#define VDIN_DNLP_HIST04 ((0x123b << 2) + 0xff000000)
+#define VDIN_DNLP_HIST05 ((0x123c << 2) + 0xff000000)
+#define VDIN_DNLP_HIST06 ((0x123d << 2) + 0xff000000)
+#define VDIN_DNLP_HIST07 ((0x123e << 2) + 0xff000000)
+#define VDIN_DNLP_HIST08 ((0x123f << 2) + 0xff000000)
+#define VDIN_DNLP_HIST09 ((0x1240 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST10 ((0x1241 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST11 ((0x1242 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST12 ((0x1243 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST13 ((0x1244 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST14 ((0x1245 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST15 ((0x1246 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST16 ((0x1247 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST17 ((0x1248 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST18 ((0x1249 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST19 ((0x124a << 2) + 0xff000000)
+#define VDIN_DNLP_HIST20 ((0x124b << 2) + 0xff000000)
+#define VDIN_DNLP_HIST21 ((0x124c << 2) + 0xff000000)
+#define VDIN_DNLP_HIST22 ((0x124d << 2) + 0xff000000)
+#define VDIN_DNLP_HIST23 ((0x124e << 2) + 0xff000000)
+#define VDIN_DNLP_HIST24 ((0x124f << 2) + 0xff000000)
+#define VDIN_DNLP_HIST25 ((0x1250 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST26 ((0x1251 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST27 ((0x1252 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST28 ((0x1253 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST29 ((0x1254 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST30 ((0x1255 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST31 ((0x1256 << 2) + 0xff000000)
+//Bit 31, local dimming statistic enable
+//Bit 28, eol enable
+//Bit 27:25, vertical line overlap number for max finding
+//Bit 24:22, horizontal pixel overlap number, 0: 17 pix, 1: 9 pix, 2: 5 pix, 3: 3 pix, 4: 0 pix
+//Bit 20, 1,2,1 low pass filter enable before max/hist statistic
+//Bit 19:16, region H/V position index, refer to VDIN_LDIM_STTS_HIST_SET_REGION
+//Bit 15, 1: region read index auto increase per read to VDIN_LDIM_STTS_HIST_READ_REGION
+//Bit 6:0, region read index
+//`define VDIN_LDIM_STTS_HIST_REGION_IDX 8'h57
+//Bit 28:0, if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h0: read/write hvstart0
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h1: read/write hend01
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h2: read/write vend01
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h3: read/write hend23
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h4: read/write vend23
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h5: read/write hend45
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h6: read/write vend45
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'd7: read/write hend67
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h8: read/write vend67
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h9: read/write hend89
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'ha: read/write vend89
+//hvstart0, Bit 28:16 row0 vstart, Bit 12:0 col0 hstart
+//hend01, Bit 28:16 col1 hend, Bit 12:0 col0 hend
+//vend01, Bit 28:16 row1 vend, Bit 12:0 row0 vend
+//hend23, Bit 28:16 col3 hend, Bit 12:0 col2 hend
+//vend23, Bit 28:16 row3 vend, Bit 12:0 row2 vend
+//hend45, Bit 28:16 col5 hend, Bit 12:0 col4 hend
+//vend45, Bit 28:16 row5 vend, Bit 12:0 row4 vend
+//hend67, Bit 28:16 col7 hend, Bit 12:0 col6 hend
+//vend67, Bit 28:16 row7 vend, Bit 12:0 row6 vend
+//hend89, Bit 28:16 col9 hend, Bit 12:0 col8 hend
+//vend89, Bit 28:16 row9 vend, Bit 12:0 row8 vend
+//`define VDIN_LDIM_STTS_HIST_SET_REGION 8'h58
+//REGION STATISTIC DATA READ OUT PORT, bit 29:20 max_comp2, bit 19:10 max_comp1, bit 9:0 max_comp0
+//`define VDIN_LDIM_STTS_HIST_READ_REGION 8'h59
+//Bit 18, reset bit, high active
+//Bit 17, if true, widen hs/vs pulse
+//Bit 16 vsync total counter always accumulating enable
+//Bit 14:12, select hs/vs of video input channel to measure, 0: no selection, 1: vdi1, 2: vid2, 3: vid3, 4:vid4, 5:vdi5, 6:vid6, 7:vdi7, 8: vdi8
+//Bit 11:4, vsync_span, define how many vsync span need to measure
+//Bit 2:0 meas_hs_index, index to select which HS counter/range
+#define VDIN_MEAS_CTRL0 ((0x125a << 2) + 0xff000000)
+//Read only
+//19:16 meas_ind_total_count_n, every number of sync_span vsyncs, this count add 1
+//15:0 high bit portion of vsync total counter
+#define VDIN_MEAS_VS_COUNT_HI ((0x125b << 2) + 0xff000000)
+//Read only
+//31:0, low bit portion of vsync total counter
+#define VDIN_MEAS_VS_COUNT_LO ((0x125c << 2) + 0xff000000)
+//according to the meas_hs_index in register VDIN_MEAS_CTRL0
+//meas_hs_index == 0, first hs range
+//meas_hs_index == 1, second hs range
+//meas_hs_index == 2, third hs range
+//meas_hs_index == 3, fourth hs range
+//bit 28:16 count_start
+//bit 12:0 count_end
+#define VDIN_MEAS_HS_RANGE ((0x125d << 2) + 0xff000000)
+//Read only
+//according to the meas_hs_index in register VDIN_MEAS_CTRL0,
+//meas_hs_index == 0, first range hs counter,
+//meas_hs_index == 1, second range hs coutner
+//meas_hs_index == 2, third range hs coutner
+//meas_hs_index == 3, fourth range hs coutner
+//23:0
+#define VDIN_MEAS_HS_COUNT ((0x125e << 2) + 0xff000000)
+//Bit 8 white_enable
+//Bit 7:0 blkbar_white_level
+#define VDIN_BLKBAR_CTRL1 ((0x125f << 2) + 0xff000000)
+// Bit 31:24 blkbar_black_level threshold to judge a black point
+// Bit 23:21 Reserved
+// Bit 20:8 blkbar_hwidth left and right region width
+// Bit 7:5 blkbar_comp_sel select yin or uin or vin to be the valid input
+// Bit 4 blkbar_sw_statistic_en enable software statistic of each block black points number
+// Bit 3 blkbar_det_en
+// Bit 2:1 blkbar_din_sel
+// bit blkbar_det_top_en
+#define VDIN_BLKBAR_CTRL0 ((0x1260 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 blkbar_hstart. Left region start
+// Bit 15:13 Reserved
+// Bit 12:0 blkbar_hend. Right region end
+#define VDIN_BLKBAR_H_START_END ((0x1261 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 blkbar_vstart
+// Bit 15:13 Reserved
+// Bit 12:0 blkbar_vend
+#define VDIN_BLKBAR_V_START_END ((0x1262 << 2) + 0xff000000)
+// Bit 31:20 Reserved
+// Bit 19:0 blkbar_cnt_threshold. threshold to judge whether a block is totally black
+#define VDIN_BLKBAR_CNT_THRESHOLD ((0x1263 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 blkbar_row_th1. //threshold of the top blackbar
+// Bit 15:13 Reserved
+// bit 12:0 blkbar_row_th2 //threshold of the bottom blackbar
+#define VDIN_BLKBAR_ROW_TH1_TH2 ((0x1264 << 2) + 0xff000000)
+//Readonly
+// Bit 31:29 Reserved
+// Bit 28:16 blkbar_ind_left_start. horizontal start of the left region in the current searching
+// Bit 15:13 Reserved
+// Bit 12:0 blkbar_ind_left_end. horizontal end of the left region in the current searching
+#define VDIN_BLKBAR_IND_LEFT_START_END ((0x1265 << 2) + 0xff000000)
+//Readonly
+// Bit 31:29 Reserved
+// Bit 28:16 blkbar_ind_right_start.horizontal start of the right region in the current searching
+// Bit 15:13 Reserved
+// Bit 12:0 blkbar_ind_right_end. horizontal end of the right region in the current searching
+#define VDIN_BLKBAR_IND_RIGHT_START_END ((0x1266 << 2) + 0xff000000)
+//Readonly
+// Bit 31:20 Reserved
+// Bit 19:0 blkbar_ind_left1_cnt. Black pixel counter. left part of the left region
+#define VDIN_BLKBAR_IND_LEFT1_CNT ((0x1267 << 2) + 0xff000000)
+//Readonly
+// Bit 31:20 Reserved
+// Bit 19:0 blkbar_ind_left2_cnt. Black pixel counter. right part of the left region
+#define VDIN_BLKBAR_IND_LEFT2_CNT ((0x1268 << 2) + 0xff000000)
+//Readonly
+// Bit 31:20 Reserved
+// Bit 19:0 blkbar_ind_right1_cnt. Black pixel counter. left part of the right region
+#define VDIN_BLKBAR_IND_RIGHT1_CNT ((0x1269 << 2) + 0xff000000)
+//Readonly
+// Bit 31:20 Reserved
+// Bit 19:0 blkbar_ind_right2_cnt. Black pixel counter. right part of the right region
+#define VDIN_BLKBAR_IND_RIGHT2_CNT ((0x126a << 2) + 0xff000000)
+//Readonly
+// Bit 31:30 Resersed
+// Bit 29 blkbar_ind_black_det_done. LEFT/RIGHT Black detection done
+// Bit 28:16 blkbar_top_pos. Top black bar position
+// Bit 15:13 Reserved.
+// Bit 12:0 blkbar_bot_pos. Bottom black bar position
+#define VDIN_BLKBAR_STATUS0 ((0x126b << 2) + 0xff000000)
+//Readonly
+// Bit 31:29 Reserved
+// Bit 28:16 blkbar_left_pos. Left black bar posiont
+// Bit 15:13 Reserved
+// Bit 12:0 blkbar_right_pos. Right black bar position
+#define VDIN_BLKBAR_STATUS1 ((0x126c << 2) + 0xff000000)
+//Bit 28:16 input window H start
+//Bit 12:0 input window H end
+#define VDIN_WIN_H_START_END ((0x126d << 2) + 0xff000000)
+//Bit 28:16 input window H start
+//Bit 12:0 input window V start
+#define VDIN_WIN_V_START_END ((0x126e << 2) + 0xff000000)
+//Bit 23:16 vdi8 asfifo_ctrl
+//Bit 15:8 vdi7 asfifo_ctrl
+//Bit 7:0 vdi6 asfifo_ctrl
+#define VDIN_ASFIFO_CTRL3 ((0x126f << 2) + 0xff000000)
+//Bit 3:2 vshrk_clk2_ctrl
+//Bit 1:0 vshrk_clk1_ctrl
+#define VDIN_COM_GCLK_CTRL2 ((0x1270 << 2) + 0xff000000)
+//Bit 27 vshrk_en
+//Bit 26:25 vshrk_mode
+//Bit 24 vshrk_lpf_mode
+//Bit 23:0 vshrk_dummy
+#define VDIN_VSHRK_CTRL ((0x1271 << 2) + 0xff000000)
+#define VDIN_DNLP_HIST32 ((0x1272 << 2) + 0xff000000)
+//Read only
+//Bit 7, vdi9 fifo overflow
+//Bit 5:0, vdi9_asfifo_cnt
+#define VDIN_COM_STATUS3 ((0x1273 << 2) + 0xff000000)
+#define VDIN_SYNC_MASK ((0x1274 << 2) + 0xff000000)
+//Bit 7:0, hsync_mask_num
+//Bit 15:8, vsync_mask_num
+//Bit 16, hsync_mask_enable
+//Bit 17, vsync_mask_num
+//dolby vdin
+#define VDIN_DOLBY_DSC_CTRL0 ((0x1275 << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_CTRL1 ((0x1276 << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_CTRL2 ((0x1277 << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_CTRL3 ((0x1278 << 2) + 0xff000000)
+#define VDIN_DOLBY_AXI_CTRL0 ((0x1279 << 2) + 0xff000000)
+#define VDIN_DOLBY_AXI_CTRL1 ((0x127a << 2) + 0xff000000)
+#define VDIN_DOLBY_AXI_CTRL2 ((0x127b << 2) + 0xff000000)
+#define VDIN_DOLBY_AXI_CTRL3 ((0x127c << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_STATUS0 ((0x127d << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_STATUS1 ((0x127e << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_STATUS2 ((0x127f << 2) + 0xff000000)
+#define VDIN_DOLBY_DSC_STATUS3 ((0x121d << 2) + 0xff000000)
+//hdr2 0x80 - -0xc0
+#define VDIN_HDR2_CTRL ((0x1280 << 2) + 0xff000000)
+#define VDIN_HDR2_CLK_GATE ((0x1281 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF00_01 ((0x1282 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF02_10 ((0x1283 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF11_12 ((0x1284 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF20_21 ((0x1285 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF22 ((0x1286 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF30_31 ((0x1287 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF32_40 ((0x1288 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_COEF41_42 ((0x1289 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_OFFSET0_1 ((0x128a << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_OFFSET2 ((0x128b << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x128c << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_PRE_OFFSET2 ((0x128d << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF00_01 ((0x128e << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF02_10 ((0x128f << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF11_12 ((0x1290 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF20_21 ((0x1291 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF22 ((0x1292 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF30_31 ((0x1293 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF32_40 ((0x1294 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_COEF41_42 ((0x1295 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_OFFSET0_1 ((0x1296 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_OFFSET2 ((0x1297 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x1298 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_PRE_OFFSET2 ((0x1299 << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_CLIP ((0x129a << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_CLIP ((0x129b << 2) + 0xff000000)
+#define VDIN_HDR2_CGAIN_OFFT ((0x129c << 2) + 0xff000000)
+#define VDIN_EOTF_LUT_ADDR_PORT ((0x129e << 2) + 0xff000000)
+#define VDIN_EOTF_LUT_DATA_PORT ((0x129f << 2) + 0xff000000)
+#define VDIN_OETF_LUT_ADDR_PORT ((0x12a0 << 2) + 0xff000000)
+#define VDIN_OETF_LUT_DATA_PORT ((0x12a1 << 2) + 0xff000000)
+#define VDIN_CGAIN_LUT_ADDR_PORT ((0x12a2 << 2) + 0xff000000)
+#define VDIN_CGAIN_LUT_DATA_PORT ((0x12a3 << 2) + 0xff000000)
+#define VDIN_HDR2_CGAIN_COEF0 ((0x12a4 << 2) + 0xff000000)
+#define VDIN_HDR2_CGAIN_COEF1 ((0x12a5 << 2) + 0xff000000)
+#define VDIN_OGAIN_LUT_ADDR_PORT ((0x12a6 << 2) + 0xff000000)
+#define VDIN_OGAIN_LUT_DATA_PORT ((0x12a7 << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_CTRL ((0x12a8 << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_ALPHA0 ((0x12a9 << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_ALPHA1 ((0x12aa << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_BETA0 ((0x12ab << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_BETA1 ((0x12ac << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_BETA2 ((0x12ad << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_COEF0 ((0x12ae << 2) + 0xff000000)
+#define VDIN_HDR2_ADPS_COEF1 ((0x12af << 2) + 0xff000000)
+#define VDIN_HDR2_GMUT_CTRL ((0x12b0 << 2) + 0xff000000)
+#define VDIN_HDR2_GMUT_COEF0 ((0x12b1 << 2) + 0xff000000)
+#define VDIN_HDR2_GMUT_COEF1 ((0x12b2 << 2) + 0xff000000)
+#define VDIN_HDR2_GMUT_COEF2 ((0x12b3 << 2) + 0xff000000)
+#define VDIN_HDR2_GMUT_COEF3 ((0x12b4 << 2) + 0xff000000)
+#define VDIN_HDR2_GMUT_COEF4 ((0x12b5 << 2) + 0xff000000)
+#define VDIN_HDR2_PIPE_CTRL1 ((0x12b6 << 2) + 0xff000000)
+#define VDIN_HDR2_PIPE_CTRL2 ((0x12b7 << 2) + 0xff000000)
+#define VDIN_HDR2_PIPE_CTRL3 ((0x12b8 << 2) + 0xff000000)
+#define VDIN_HDR2_PROC_WIN1 ((0x12b9 << 2) + 0xff000000)
+#define VDIN_HDR2_PROC_WIN2 ((0x12ba << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXI_EN_CTRL ((0x12bb << 2) + 0xff000000)
+#define VDIN_HDR2_MATRIXO_EN_CTRL ((0x12bc << 2) + 0xff000000)
+#define VDIN_HDR2_HIST_CTRL ((0x12bd << 2) + 0xff000000)
+#define VDIN_HDR2_HIST_H_START_END ((0x12be << 2) + 0xff000000)
+#define VDIN_HDR2_HIST_V_START_END ((0x12bf << 2) + 0xff000000)
+#define VDIN_HDR2_HIST_RD ((0x129d << 2) + 0xff000000)
+#define VDIN_WRARB_MODE ((0x12c0 << 2) + 0xff000000)
+#define VDIN_WRARB_REQEN_SLV ((0x12c1 << 2) + 0xff000000)
+#define VDIN_WRARB_WEIGH0_SLV ((0x12c2 << 2) + 0xff000000)
+#define VDIN_WRARB_WEIGH1_SLV ((0x12c3 << 2) + 0xff000000)
+#define VDIN_RDWR_ARB_STATUS ((0x12c4 << 2) + 0xff000000)
+#define VDIN_ARB_DBG_CTRL ((0x12c5 << 2) + 0xff000000)
+#define VDIN_ARB_DBG_STAT ((0x12c6 << 2) + 0xff000000)
+#define VDIN_DBG_AXI_CMD_CNT ((0x12c7 << 2) + 0xff000000)
+#define VDIN_DBG_AXI_DAT_CNT ((0x12c8 << 2) + 0xff000000)
+#define VDIN_CRC_CTRL ((0x12c9 << 2) + 0xff000000)
+#define VDIN_RO_CRC ((0x12ca << 2) + 0xff000000)
+#define VDIN_LINE_INT ((0x12cb << 2) + 0xff000000)
+#define VDIN_WR_URGENT_CTRL ((0x1257 << 2) + 0xff000000)
+#define VDIN_RO_WRMIF_STATUS ((0x1258 << 2) + 0xff000000)
+#define VDIN_WR_BADDR_LUMA ((0x12cc << 2) + 0xff000000)
+#define VDIN_WR_BADDR_CHROMA ((0x12cd << 2) + 0xff000000)
+#define VDIN_WR_STRIDE_LUMA ((0x12ce << 2) + 0xff000000)
+#define VDIN_WR_STRIDE_CHROMA ((0x12cf << 2) + 0xff000000)
+//for vdin dolby descramble start
+#define VDIN_DSC_CTRL ((0x12d0 << 2) + 0xff000000)
+//Bit 31:10 reserved
+//Bit 9:4 reg_dithout_switch ,uns, default = 36;//{2'h2,2'h1,2'h0}
+//Bit 3, reg_detunnel_en ,uns, default = 1;
+//Bit 2, reg_detunnel_u_start,uns, default = 0;
+//Bit 1, reg_vdin_dith_en ,uns, default = 1;
+//Bit 0, reg_descramble_en ,uns, default = 1;
+#define VDIN_CFMT_CTRL ((0x12d1 << 2) + 0xff000000)
+//Bit 31:9 reserved
+//Bit 8 reg_chfmt_rpt_pix uns, default = 0 ; // if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
+//Bit 7:4 reg_chfmt_ini_phase uns, default = 0 ; // horizontal formatter initial phase
+//Bit 3 reg_chfmt_rpt_p0_en uns, default = 0 ; // horizontal formatter repeat pixel 0 enable
+//Bit 2:1 reg_chfmt_yc_ratio uns, default = 1 ; // horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
+//Bit 0 reg_chfmt_en uns, default = 1 ; // horizontal formatter enable
+#define VDIN_CFMT_W ((0x12d2 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_chfmt_w uns, default = 1920 ;horizontal formatter width
+//Bit 15:13 reserved
+//Bit 12:0 reg_cvfmt_w uns, default = 960 ;vertical formatter width
+#define VDIN_SCB_CTRL0 ((0x12d3 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 28 reg_scb2_enable uns, default = 0;
+//Bit 27 reg_scb2_444c422_gofield_en uns, default = 1;
+//Bit 26 reg_scb2_tunnel_en uns, default = 1;
+//Bit 25:20 reg_scb2_tunnel_outswitch uns, default = 36;//{2'h2,2'h1,2'h0}
+//Bit 19:18 reg_scb2_444c422_mode uns, default = 0; //0:left 1:right 2,3:avg
+//Bit 17 reg_scb2_444c422_bypass uns, default = 0; 1:bypass
+//Bit 16 reserved //pulse for frm_en
+//
+//Bit 11 reg_444c422_gofield_en uns, default = 1;
+//Bit 10 reg_tunnel_en uns, default = 1;
+//Bit 9:4 reg_tunnel_outswitch uns, default = 36;//{2'h2,2'h1,2'h0}
+//Bit 3:2 reg_444c422_mode uns, default = 0; //0:left 1:right 2,3:avg
+//Bit 1 reg_444c422_bypass uns, default = 0; 1:bypass
+//Bit 0 reserved //pulse for frm_en
+#define VDIN_SCB_CTRL1 ((0x12d4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_444c422_hsize uns, default = 1920 ;horizontal size
+//Bit 15:13 reserved
+//Bit 12:0 reg_444c422_vsize uns, default = 960 ;vertical size
+#define VDIN_DSC_HSIZE ((0x12d5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_detunnel_hsize uns, default = 1920 ;
+//Bit 15:13 reserved
+//Bit 12:0 reg_dither_hsize uns, default = 1920 ;
+#define VDIN_DSC_DETUNNEL_SEL ((0x12d6 << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:0 reg_detunnel_sel uns, default = 34658; //{3'h1,3'h0,3'h3 ,3'h5,3'h4,3'h2}
+#define VDIN_DSC_TUNNEL_SEL ((0x12d7 << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:0 reg_tunnel_sel uns, default = 69868; //= {3'h2,3'h1 ,3'h0,3'h3 ,3'h5,3'h4};
+#define VDIN_SCB_CTRL2 ((0x12da << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scb2_444c422_hsize uns, default = 1920 ;horizontal size
+//Bit 15:13 reserved
+//Bit 12:0 reg_scb2_444c422_vsize uns, default = 960 ;vertical size
+#define VDIN_HDR2_SIZE ((0x12d8 << 2) + 0xff000000)
+#define VDIN_VSHRK_SIZE_M1 ((0x12d9 << 2) + 0xff000000)
+//dither
+#define VDIN_DITH_CTRL ((0x12e0 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_1 ((0x12e1 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_2 ((0x12e2 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_3 ((0x12e3 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_4 ((0x12e4 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_5 ((0x12e5 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_6 ((0x12e6 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_7 ((0x12e7 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_8 ((0x12e8 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_9 ((0x12e9 << 2) + 0xff000000)
+#define VDIN_DITH_LUT_10 ((0x12ea << 2) + 0xff000000)
+#define VDIN_DITH_LUT_11 ((0x12eb << 2) + 0xff000000)
+#define VDIN_DITH_LUT_12 ((0x12ec << 2) + 0xff000000)
+//for vdin dolby descramble end
+#define VDIN_HSK_CTRL ((0x12ef << 2) + 0xff000000)
+//Bit 31:23 reserved
+//Bit 22:16 reg_hsk_size ,uns, default = 4;
+//Bit 15:13 reserved
+//Bit 12:0 reg_frm_hsize ,uns, default = 1920;
+#define VDIN_HSK_COEF_0 ((0x12f0 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef00 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_1 ((0x12f1 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef01 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_2 ((0x12f2 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef02 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_3 ((0x12f3 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef03 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+//
+#define VDIN_HSK_COEF_4 ((0x12f4 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef04 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_5 ((0x12f5 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef05 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_6 ((0x12f6 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef06 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_7 ((0x12f7 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef07 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+//
+#define VDIN_HSK_COEF_8 ((0x12f8 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef08 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_9 ((0x12f9 << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef09 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_A ((0x12fa << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef10 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_B ((0x12fb << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef11 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+//
+#define VDIN_HSK_COEF_C ((0x12fc << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef12 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_D ((0x12fd << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef13 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_E ((0x12fe << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef14 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+#define VDIN_HSK_COEF_F ((0x12ff << 2) + 0xff000000)
+//Bit 31:0 reg_hsk_coef15 ,uns, default = 0;//[29:24] [21:16] [13:8] [5:0] is used
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_vdin_regs.h
+//
+
+//8'h72 occupied by histogram 32
+//VDIN0 8'h00 - 8'h7f
+#define VDIN0_SCALE_COEF_IDX (VDIN_SCALE_COEF_IDX )
+#define VDIN0_SCALE_COEF (VDIN_SCALE_COEF )
+#define VDIN0_COM_CTRL0 (VDIN_COM_CTRL0 )
+#define VDIN0_ACTIVE_MAX_PIX_CNT_STATUS (VDIN_ACTIVE_MAX_PIX_CNT_STATUS )
+#define VDIN0_LCNT_STATUS (VDIN_LCNT_STATUS )
+#define VDIN0_COM_STATUS0 (VDIN_COM_STATUS0 )
+#define VDIN0_COM_STATUS1 (VDIN_COM_STATUS1 )
+#define VDIN0_LCNT_SHADOW_STATUS (VDIN_LCNT_SHADOW_STATUS )
+#define VDIN0_ASFIFO_CTRL0 (VDIN_ASFIFO_CTRL0 )
+#define VDIN0_ASFIFO_CTRL1 (VDIN_ASFIFO_CTRL1 )
+#define VDIN0_WIDTHM1I_WIDTHM1O (VDIN_WIDTHM1I_WIDTHM1O )
+#define VDIN0_SC_MISC_CTRL (VDIN_SC_MISC_CTRL )
+#define VDIN0_HSC_PHASE_STEP (VDIN_HSC_PHASE_STEP )
+#define VDIN0_HSC_INI_CTRL (VDIN_HSC_INI_CTRL )
+#define VDIN0_COM_STATUS2 (VDIN_COM_STATUS2 )
+#define VDIN0_COM_STATUS3 (VDIN_COM_STATUS3 )
+#define VDIN0_ASFIFO_CTRL2 (VDIN_ASFIFO_CTRL2 )
+#define VDIN0_MATRIX_CTRL (VDIN_MATRIX_CTRL )
+#define VDIN0_MATRIX_COEF00_01 (VDIN_MATRIX_COEF00_01 )
+#define VDIN0_MATRIX_COEF02_10 (VDIN_MATRIX_COEF02_10 )
+#define VDIN0_MATRIX_COEF11_12 (VDIN_MATRIX_COEF11_12 )
+#define VDIN0_MATRIX_COEF20_21 (VDIN_MATRIX_COEF20_21 )
+#define VDIN0_MATRIX_COEF22 (VDIN_MATRIX_COEF22 )
+#define VDIN0_MATRIX_OFFSET0_1 (VDIN_MATRIX_OFFSET0_1 )
+#define VDIN0_MATRIX_OFFSET2 (VDIN_MATRIX_OFFSET2 )
+#define VDIN0_MATRIX_PRE_OFFSET0_1 (VDIN_MATRIX_PRE_OFFSET0_1 )
+#define VDIN0_MATRIX_PRE_OFFSET2 (VDIN_MATRIX_PRE_OFFSET2 )
+#define VDIN0_LFIFO_CTRL (VDIN_LFIFO_CTRL )
+#define VDIN0_COM_GCLK_CTRL (VDIN_COM_GCLK_CTRL )
+#define VDIN0_INTF_WIDTHM1 (VDIN_INTF_WIDTHM1 )
+#define VDIN0_WR_CTRL2 (VDIN_WR_CTRL2 )
+#define VDIN0_WR_CTRL (VDIN_WR_CTRL )
+#define VDIN0_WR_H_START_END (VDIN_WR_H_START_END )
+#define VDIN0_WR_V_START_END (VDIN_WR_V_START_END )
+#define VDIN0_VSC_PHASE_STEP (VDIN_VSC_PHASE_STEP )
+#define VDIN0_VSC_INI_CTRL (VDIN_VSC_INI_CTRL )
+#define VDIN0_SCIN_HEIGHTM1 (VDIN_SCIN_HEIGHTM1 )
+#define VDIN0_DUMMY_DATA (VDIN_DUMMY_DATA )
+#define VDIN0_MATRIX_PROBE_COLOR (VDIN_MATRIX_PROBE_COLOR )
+#define VDIN0_MATRIX_HL_COLOR (VDIN_MATRIX_HL_COLOR )
+#define VDIN0_MATRIX_PROBE_POS (VDIN_MATRIX_PROBE_POS )
+#define VDIN0_CHROMA_ADDR_PORT (VDIN_CHROMA_ADDR_PORT )
+#define VDIN0_CHROMA_DATA_PORT (VDIN_CHROMA_DATA_PORT )
+#define VDIN0_CM_BRI_CON_CTRL (VDIN_CM_BRI_CON_CTRL )
+#define VDIN0_GO_LINE_CTRL (VDIN_GO_LINE_CTRL )
+#define VDIN0_HIST_CTRL (VDIN_HIST_CTRL )
+#define VDIN0_HIST_H_START_END (VDIN_HIST_H_START_END )
+#define VDIN0_HIST_V_START_END (VDIN_HIST_V_START_END )
+#define VDIN0_HIST_MAX_MIN (VDIN_HIST_MAX_MIN )
+#define VDIN0_HIST_SPL_VAL (VDIN_HIST_SPL_VAL )
+#define VDIN0_HIST_SPL_PIX_CNT (VDIN_HIST_SPL_PIX_CNT )
+#define VDIN0_HIST_CHROMA_SUM (VDIN_HIST_CHROMA_SUM )
+#define VDIN0_DNLP_HIST00 (VDIN_DNLP_HIST00 )
+#define VDIN0_DNLP_HIST01 (VDIN_DNLP_HIST01 )
+#define VDIN0_DNLP_HIST02 (VDIN_DNLP_HIST02 )
+#define VDIN0_DNLP_HIST03 (VDIN_DNLP_HIST03 )
+#define VDIN0_DNLP_HIST04 (VDIN_DNLP_HIST04 )
+#define VDIN0_DNLP_HIST05 (VDIN_DNLP_HIST05 )
+#define VDIN0_DNLP_HIST06 (VDIN_DNLP_HIST06 )
+#define VDIN0_DNLP_HIST07 (VDIN_DNLP_HIST07 )
+#define VDIN0_DNLP_HIST08 (VDIN_DNLP_HIST08 )
+#define VDIN0_DNLP_HIST09 (VDIN_DNLP_HIST09 )
+#define VDIN0_DNLP_HIST10 (VDIN_DNLP_HIST10 )
+#define VDIN0_DNLP_HIST11 (VDIN_DNLP_HIST11 )
+#define VDIN0_DNLP_HIST12 (VDIN_DNLP_HIST12 )
+#define VDIN0_DNLP_HIST13 (VDIN_DNLP_HIST13 )
+#define VDIN0_DNLP_HIST14 (VDIN_DNLP_HIST14 )
+#define VDIN0_DNLP_HIST15 (VDIN_DNLP_HIST15 )
+#define VDIN0_DNLP_HIST16 (VDIN_DNLP_HIST16 )
+#define VDIN0_DNLP_HIST17 (VDIN_DNLP_HIST17 )
+#define VDIN0_DNLP_HIST18 (VDIN_DNLP_HIST18 )
+#define VDIN0_DNLP_HIST19 (VDIN_DNLP_HIST19 )
+#define VDIN0_DNLP_HIST20 (VDIN_DNLP_HIST20 )
+#define VDIN0_DNLP_HIST21 (VDIN_DNLP_HIST21 )
+#define VDIN0_DNLP_HIST22 (VDIN_DNLP_HIST22 )
+#define VDIN0_DNLP_HIST23 (VDIN_DNLP_HIST23 )
+#define VDIN0_DNLP_HIST24 (VDIN_DNLP_HIST24 )
+#define VDIN0_DNLP_HIST25 (VDIN_DNLP_HIST25 )
+#define VDIN0_DNLP_HIST26 (VDIN_DNLP_HIST26 )
+#define VDIN0_DNLP_HIST27 (VDIN_DNLP_HIST27 )
+#define VDIN0_DNLP_HIST28 (VDIN_DNLP_HIST28 )
+#define VDIN0_DNLP_HIST29 (VDIN_DNLP_HIST29 )
+#define VDIN0_DNLP_HIST30 (VDIN_DNLP_HIST30 )
+#define VDIN0_DNLP_HIST31 (VDIN_DNLP_HIST31 )
+#define VDIN0_DNLP_HIST32 (VDIN_DNLP_HIST32 )
+#define VDIN0_MEAS_CTRL0 (VDIN_MEAS_CTRL0 )
+#define VDIN0_MEAS_VS_COUNT_HI (VDIN_MEAS_VS_COUNT_HI )
+#define VDIN0_MEAS_VS_COUNT_LO (VDIN_MEAS_VS_COUNT_LO )
+#define VDIN0_MEAS_HS_RANGE (VDIN_MEAS_HS_RANGE )
+#define VDIN0_MEAS_HS_COUNT (VDIN_MEAS_HS_COUNT )
+#define VDIN0_BLKBAR_CTRL1 (VDIN_BLKBAR_CTRL1 )
+#define VDIN0_BLKBAR_CTRL0 (VDIN_BLKBAR_CTRL0 )
+#define VDIN0_BLKBAR_H_START_END (VDIN_BLKBAR_H_START_END )
+#define VDIN0_BLKBAR_V_START_END (VDIN_BLKBAR_V_START_END )
+#define VDIN0_BLKBAR_CNT_THRESHOLD (VDIN_BLKBAR_CNT_THRESHOLD )
+#define VDIN0_BLKBAR_ROW_TH1_TH2 (VDIN_BLKBAR_ROW_TH1_TH2 )
+#define VDIN0_BLKBAR_IND_LEFT_START_END (VDIN_BLKBAR_IND_LEFT_START_END )
+#define VDIN0_BLKBAR_IND_RIGHT_START_END (VDIN_BLKBAR_IND_RIGHT_START_END )
+#define VDIN0_BLKBAR_IND_LEFT1_CNT (VDIN_BLKBAR_IND_LEFT1_CNT )
+#define VDIN0_BLKBAR_IND_LEFT2_CNT (VDIN_BLKBAR_IND_LEFT2_CNT )
+#define VDIN0_BLKBAR_IND_RIGHT1_CNT (VDIN_BLKBAR_IND_RIGHT1_CNT )
+#define VDIN0_BLKBAR_IND_RIGHT2_CNT (VDIN_BLKBAR_IND_RIGHT2_CNT )
+#define VDIN0_BLKBAR_STATUS0 (VDIN_BLKBAR_STATUS0 )
+#define VDIN0_BLKBAR_STATUS1 (VDIN_BLKBAR_STATUS1 )
+#define VDIN0_WIN_H_START_END (VDIN_WIN_H_START_END )
+#define VDIN0_WIN_V_START_END (VDIN_WIN_V_START_END )
+#define VDIN0_ASFIFO_CTRL3 (VDIN_ASFIFO_CTRL3 )
+#define VDIN0_LFIFO_URG_CTRL (VDIN_LFIFO_URG_CTRL )
+#define VDIN0_COM_GCLK_CTRL2 (VDIN_COM_GCLK_CTRL2 )
+#define VDIN0_VSHRK_CTRL (VDIN_VSHRK_CTRL )
+#define VDIN0_SYNC_MASK (VDIN_SYNC_MASK )
+#define VDIN0_DOLBY_DSC_CTRL0 (VDIN_DOLBY_DSC_CTRL0 )
+#define VDIN0_DOLBY_DSC_CTRL1 (VDIN_DOLBY_DSC_CTRL1 )
+#define VDIN0_DOLBY_DSC_CTRL2 (VDIN_DOLBY_DSC_CTRL2 )
+#define VDIN0_DOLBY_DSC_CTRL3 (VDIN_DOLBY_DSC_CTRL3 )
+#define VDIN0_DOLBY_AXI_CTRL0 (VDIN_DOLBY_AXI_CTRL0 )
+#define VDIN0_DOLBY_AXI_CTRL1 (VDIN_DOLBY_AXI_CTRL1 )
+#define VDIN0_DOLBY_AXI_CTRL2 (VDIN_DOLBY_AXI_CTRL2 )
+#define VDIN0_DOLBY_AXI_CTRL3 (VDIN_DOLBY_AXI_CTRL3 )
+#define VDIN0_DOLBY_DSC_STATUS0 (VDIN_DOLBY_DSC_STATUS0)
+#define VDIN0_DOLBY_DSC_STATUS1 (VDIN_DOLBY_DSC_STATUS1)
+#define VDIN0_DOLBY_DSC_STATUS2 (VDIN_DOLBY_DSC_STATUS2)
+#define VDIN0_DOLBY_DSC_STATUS3 (VDIN_DOLBY_DSC_STATUS3)
+#define VDIN0_HDR2_CTRL VDIN_HDR2_CTRL
+#define VDIN0_HDR2_CLK_GATE VDIN_HDR2_CLK_GATE
+#define VDIN0_HDR2_MATRIXI_COEF00_01 VDIN_HDR2_MATRIXI_COEF00_01
+#define VDIN0_HDR2_MATRIXI_COEF02_10 VDIN_HDR2_MATRIXI_COEF02_10
+#define VDIN0_HDR2_MATRIXI_COEF11_12 VDIN_HDR2_MATRIXI_COEF11_12
+#define VDIN0_HDR2_MATRIXI_COEF20_21 VDIN_HDR2_MATRIXI_COEF20_21
+#define VDIN0_HDR2_MATRIXI_COEF22 VDIN_HDR2_MATRIXI_COEF22
+#define VDIN0_HDR2_MATRIXI_COEF30_31 VDIN_HDR2_MATRIXI_COEF30_31
+#define VDIN0_HDR2_MATRIXI_COEF32_40 VDIN_HDR2_MATRIXI_COEF32_40
+#define VDIN0_HDR2_MATRIXI_COEF41_42 VDIN_HDR2_MATRIXI_COEF41_42
+#define VDIN0_HDR2_MATRIXI_OFFSET0_1 VDIN_HDR2_MATRIXI_OFFSET0_1
+#define VDIN0_HDR2_MATRIXI_OFFSET2 VDIN_HDR2_MATRIXI_OFFSET2
+#define VDIN0_HDR2_MATRIXI_PRE_OFFSET0_1 VDIN_HDR2_MATRIXI_PRE_OFFSET0_1
+#define VDIN0_HDR2_MATRIXI_PRE_OFFSET2 VDIN_HDR2_MATRIXI_PRE_OFFSET2
+#define VDIN0_HDR2_MATRIXO_COEF00_01 VDIN_HDR2_MATRIXO_COEF00_01
+#define VDIN0_HDR2_MATRIXO_COEF02_10 VDIN_HDR2_MATRIXO_COEF02_10
+#define VDIN0_HDR2_MATRIXO_COEF11_12 VDIN_HDR2_MATRIXO_COEF11_12
+#define VDIN0_HDR2_MATRIXO_COEF20_21 VDIN_HDR2_MATRIXO_COEF20_21
+#define VDIN0_HDR2_MATRIXO_COEF22 VDIN_HDR2_MATRIXO_COEF22
+#define VDIN0_HDR2_MATRIXO_COEF30_31 VDIN_HDR2_MATRIXO_COEF30_31
+#define VDIN0_HDR2_MATRIXO_COEF32_40 VDIN_HDR2_MATRIXO_COEF32_40
+#define VDIN0_HDR2_MATRIXO_COEF41_42 VDIN_HDR2_MATRIXO_COEF41_42
+#define VDIN0_HDR2_MATRIXO_OFFSET0_1 VDIN_HDR2_MATRIXO_OFFSET0_1
+#define VDIN0_HDR2_MATRIXO_OFFSET2 VDIN_HDR2_MATRIXO_OFFSET2
+#define VDIN0_HDR2_MATRIXO_PRE_OFFSET0_1 VDIN_HDR2_MATRIXO_PRE_OFFSET0_1
+#define VDIN0_HDR2_MATRIXO_PRE_OFFSET2 VDIN_HDR2_MATRIXO_PRE_OFFSET2
+#define VDIN0_HDR2_MATRIXI_CLIP VDIN_HDR2_MATRIXI_CLIP
+#define VDIN0_HDR2_MATRIXO_CLIP VDIN_HDR2_MATRIXO_CLIP
+#define VDIN0_HDR2_CGAIN_OFFT VDIN_HDR2_CGAIN_OFFT
+#define VDIN0_EOTF_LUT_ADDR_PORT VDIN_EOTF_LUT_ADDR_PORT
+#define VDIN0_EOTF_LUT_DATA_PORT VDIN_EOTF_LUT_DATA_PORT
+#define VDIN0_OETF_LUT_ADDR_PORT VDIN_OETF_LUT_ADDR_PORT
+#define VDIN0_OETF_LUT_DATA_PORT VDIN_OETF_LUT_DATA_PORT
+#define VDIN0_OGAIN_LUT_ADDR_PORT VDIN_OGAIN_LUT_ADDR_PORT
+#define VDIN0_OGAIN_LUT_DATA_PORT VDIN_OGAIN_LUT_DATA_PORT
+#define VDIN0_CGAIN_LUT_ADDR_PORT VDIN_CGAIN_LUT_ADDR_PORT
+#define VDIN0_CGAIN_LUT_DATA_PORT VDIN_CGAIN_LUT_DATA_PORT
+#define VDIN0_HDR2_CGAIN_COEF0 VDIN_HDR2_CGAIN_COEF0
+#define VDIN0_HDR2_CGAIN_COEF1 VDIN_HDR2_CGAIN_COEF1
+#define VDIN0_HDR2_ADPS_CTRL VDIN_HDR2_ADPS_CTRL
+#define VDIN0_HDR2_ADPS_ALPHA0 VDIN_HDR2_ADPS_ALPHA0
+#define VDIN0_HDR2_ADPS_ALPHA1 VDIN_HDR2_ADPS_ALPHA1
+#define VDIN0_HDR2_ADPS_BETA0 VDIN_HDR2_ADPS_BETA0
+#define VDIN0_HDR2_ADPS_BETA1 VDIN_HDR2_ADPS_BETA1
+#define VDIN0_HDR2_ADPS_BETA2 VDIN_HDR2_ADPS_BETA2
+#define VDIN0_HDR2_ADPS_COEF0 VDIN_HDR2_ADPS_COEF0
+#define VDIN0_HDR2_ADPS_COEF1 VDIN_HDR2_ADPS_COEF1
+#define VDIN0_HDR2_GMUT_CTRL VDIN_HDR2_GMUT_CTRL
+#define VDIN0_HDR2_GMUT_COEF0 VDIN_HDR2_GMUT_COEF0
+#define VDIN0_HDR2_GMUT_COEF1 VDIN_HDR2_GMUT_COEF1
+#define VDIN0_HDR2_GMUT_COEF2 VDIN_HDR2_GMUT_COEF2
+#define VDIN0_HDR2_GMUT_COEF3 VDIN_HDR2_GMUT_COEF3
+#define VDIN0_HDR2_GMUT_COEF4 VDIN_HDR2_GMUT_COEF4
+#define VDIN0_HDR2_PIPE_CTRL1 VDIN_HDR2_PIPE_CTRL1
+#define VDIN0_HDR2_PIPE_CTRL2 VDIN_HDR2_PIPE_CTRL2
+#define VDIN0_HDR2_PIPE_CTRL3 VDIN_HDR2_PIPE_CTRL3
+#define VDIN0_HDR2_PROC_WIN1 VDIN_HDR2_PROC_WIN1
+#define VDIN0_HDR2_PROC_WIN2 VDIN_HDR2_PROC_WIN2
+#define VDIN0_HDR2_MATRIXI_EN_CTRL VDIN_HDR2_MATRIXI_EN_CTRL
+#define VDIN0_HDR2_MATRIXO_EN_CTRL VDIN_HDR2_MATRIXO_EN_CTRL
+#define VDIN0_HDR2_HIST_CTRL VDIN_HDR2_HIST_CTRL
+#define VDIN0_HDR2_HIST_H_START_END VDIN_HDR2_HIST_H_START_END
+#define VDIN0_HDR2_HIST_V_START_END VDIN_HDR2_HIST_V_START_END
+#define VDIN0_HDR2_HIST_RD VDIN_HDR2_HIST_RD
+
+
+#define VDIN0_CRC_CTRL (VDIN_CRC_CTRL)
+#define VDIN0_RO_CRC (VDIN_RO_CRC )
+#define VDIN0_LINE_INT (VDIN_LINE_INT)
+#define VDIN0_WR_URGENT_CTRL (VDIN_WR_URGENT_CTRL)
+#define VDIN0_RO_WRMIF_STATUS (VDIN_RO_WRMIF_STATUS)
+
+#define VDIN0_WR_BADDR_LUMA (VDIN_WR_BADDR_LUMA )
+#define VDIN0_WR_BADDR_CHROMA (VDIN_WR_BADDR_CHROMA )
+#define VDIN0_WR_STRIDE_LUMA (VDIN_WR_STRIDE_LUMA )
+#define VDIN0_WR_STRIDE_CHROMA (VDIN_WR_STRIDE_CHROMA)
+
+#define VDIN0_DSC_CTRL VDIN_DSC_CTRL
+#define VDIN0_CFMT_CTRL VDIN_CFMT_CTRL
+#define VDIN0_CFMT_W VDIN_CFMT_W
+#define VDIN0_SCB_CTRL0 VDIN_SCB_CTRL0
+#define VDIN0_SCB_CTRL1 VDIN_SCB_CTRL1
+#define VDIN0_SCB_CTRL2 VDIN_SCB_CTRL2
+#define VDIN0_DSC_HSIZE VDIN_DSC_HSIZE
+#define VDIN0_DSC_DETUNNEL_SEL VDIN_DSC_DETUNNEL_SEL
+#define VDIN0_DSC_TUNNEL_SEL VDIN_DSC_TUNNEL_SEL
+#define VDIN0_DITH_CTRL VDIN_DITH_CTRL
+#define VDIN0_DITH_LUT_1 VDIN_DITH_LUT_1
+#define VDIN0_DITH_LUT_2 VDIN_DITH_LUT_2
+#define VDIN0_DITH_LUT_3 VDIN_DITH_LUT_3
+#define VDIN0_DITH_LUT_4 VDIN_DITH_LUT_4
+#define VDIN0_DITH_LUT_5 VDIN_DITH_LUT_5
+#define VDIN0_DITH_LUT_6 VDIN_DITH_LUT_6
+#define VDIN0_DITH_LUT_7 VDIN_DITH_LUT_7
+#define VDIN0_DITH_LUT_8 VDIN_DITH_LUT_8
+#define VDIN0_DITH_LUT_9 VDIN_DITH_LUT_9
+#define VDIN0_DITH_LUT_10 VDIN_DITH_LUT_10
+#define VDIN0_DITH_LUT_11 VDIN_DITH_LUT_11
+#define VDIN0_DITH_LUT_12 VDIN_DITH_LUT_12
+
+#define VDIN0_HSK_CTRL VDIN_HSK_CTRL
+#define VDIN0_HSK_COEF_0 VDIN_HSK_COEF_0
+#define VDIN0_HSK_COEF_1 VDIN_HSK_COEF_1
+#define VDIN0_HSK_COEF_2 VDIN_HSK_COEF_2
+#define VDIN0_HSK_COEF_3 VDIN_HSK_COEF_3
+#define VDIN0_HSK_COEF_4 VDIN_HSK_COEF_4
+#define VDIN0_HSK_COEF_5 VDIN_HSK_COEF_5
+#define VDIN0_HSK_COEF_6 VDIN_HSK_COEF_6
+#define VDIN0_HSK_COEF_7 VDIN_HSK_COEF_7
+#define VDIN0_HSK_COEF_8 VDIN_HSK_COEF_8
+#define VDIN0_HSK_COEF_9 VDIN_HSK_COEF_9
+#define VDIN0_HSK_COEF_A VDIN_HSK_COEF_A
+#define VDIN0_HSK_COEF_B VDIN_HSK_COEF_B
+#define VDIN0_HSK_COEF_C VDIN_HSK_COEF_C
+#define VDIN0_HSK_COEF_D VDIN_HSK_COEF_D
+#define VDIN0_HSK_COEF_E VDIN_HSK_COEF_E
+#define VDIN0_HSK_COEF_F VDIN_HSK_COEF_F
+
+#define VDIN0_HDR2_SIZE VDIN_HDR2_SIZE
+#define VDIN0_VSHRK_SIZE_M1 VDIN_VSHRK_SIZE_M1
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_vdin0_regs.h
+//
+//===========================================================================
+//===========================================================================
+//
+// Reading file: vpu_vdin1_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+// VDIN
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VDIN1_VCBUS_BASE = 0x13
+// -----------------------------------------------
+#define VDIN1_OFFSET (0x100)
+// `include "vpu_vdin_regs.h"
+//8'h72 occupied by histogram 32
+//VDIN1 8'h00 - 8'h7f
+#define VDIN1_SCALE_COEF_IDX ((VDIN1_OFFSET << 2) + VDIN_SCALE_COEF_IDX )
+#define VDIN1_SCALE_COEF ((VDIN1_OFFSET << 2) + VDIN_SCALE_COEF )
+#define VDIN1_COM_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_COM_CTRL0 )
+#define VDIN1_ACTIVE_MAX_PIX_CNT_STATUS ((VDIN1_OFFSET << 2) + VDIN_ACTIVE_MAX_PIX_CNT_STATUS )
+#define VDIN1_LCNT_STATUS ((VDIN1_OFFSET << 2) + VDIN_LCNT_STATUS )
+#define VDIN1_COM_STATUS0 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS0 )
+#define VDIN1_COM_STATUS1 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS1 )
+#define VDIN1_LCNT_SHADOW_STATUS ((VDIN1_OFFSET << 2) + VDIN_LCNT_SHADOW_STATUS )
+#define VDIN1_ASFIFO_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL0 )
+#define VDIN1_ASFIFO_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL1 )
+#define VDIN1_WIDTHM1I_WIDTHM1O ((VDIN1_OFFSET << 2) + VDIN_WIDTHM1I_WIDTHM1O )
+#define VDIN1_SC_MISC_CTRL ((VDIN1_OFFSET << 2) + VDIN_SC_MISC_CTRL )
+#define VDIN1_HSC_PHASE_STEP ((VDIN1_OFFSET << 2) + VDIN_HSC_PHASE_STEP )
+#define VDIN1_HSC_INI_CTRL ((VDIN1_OFFSET << 2) + VDIN_HSC_INI_CTRL )
+#define VDIN1_COM_STATUS2 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS2 )
+#define VDIN1_COM_STATUS3 ((VDIN1_OFFSET << 2) + VDIN_COM_STATUS3 )
+#define VDIN1_ASFIFO_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL2 )
+#define VDIN1_MATRIX_CTRL ((VDIN1_OFFSET << 2) + VDIN_MATRIX_CTRL )
+#define VDIN1_MATRIX_COEF00_01 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF00_01 )
+#define VDIN1_MATRIX_COEF02_10 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF02_10 )
+#define VDIN1_MATRIX_COEF11_12 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF11_12 )
+#define VDIN1_MATRIX_COEF20_21 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF20_21 )
+#define VDIN1_MATRIX_COEF22 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_COEF22 )
+#define VDIN1_MATRIX_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_OFFSET0_1 )
+#define VDIN1_MATRIX_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_OFFSET2 )
+#define VDIN1_MATRIX_PRE_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PRE_OFFSET0_1 )
+#define VDIN1_MATRIX_PRE_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PRE_OFFSET2 )
+#define VDIN1_LFIFO_CTRL ((VDIN1_OFFSET << 2) + VDIN_LFIFO_CTRL )
+#define VDIN1_COM_GCLK_CTRL ((VDIN1_OFFSET << 2) + VDIN_COM_GCLK_CTRL )
+#define VDIN1_INTF_WIDTHM1 ((VDIN1_OFFSET << 2) + VDIN_INTF_WIDTHM1 )
+#define VDIN1_WR_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_WR_CTRL2 )
+#define VDIN1_WR_CTRL ((VDIN1_OFFSET << 2) + VDIN_WR_CTRL )
+#define VDIN1_WR_H_START_END ((VDIN1_OFFSET << 2) + VDIN_WR_H_START_END )
+#define VDIN1_WR_V_START_END ((VDIN1_OFFSET << 2) + VDIN_WR_V_START_END )
+#define VDIN1_VSC_PHASE_STEP ((VDIN1_OFFSET << 2) + VDIN_VSC_PHASE_STEP )
+#define VDIN1_VSC_INI_CTRL ((VDIN1_OFFSET << 2) + VDIN_VSC_INI_CTRL )
+#define VDIN1_SCIN_HEIGHTM1 ((VDIN1_OFFSET << 2) + VDIN_SCIN_HEIGHTM1 )
+#define VDIN1_DUMMY_DATA ((VDIN1_OFFSET << 2) + VDIN_DUMMY_DATA )
+#define VDIN1_MATRIX_PROBE_COLOR ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PROBE_COLOR )
+#define VDIN1_MATRIX_HL_COLOR ((VDIN1_OFFSET << 2) + VDIN_MATRIX_HL_COLOR )
+#define VDIN1_MATRIX_PROBE_POS ((VDIN1_OFFSET << 2) + VDIN_MATRIX_PROBE_POS )
+#define VDIN1_CHROMA_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_CHROMA_ADDR_PORT )
+#define VDIN1_CHROMA_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_CHROMA_DATA_PORT )
+#define VDIN1_CM_BRI_CON_CTRL ((VDIN1_OFFSET << 2) + VDIN_CM_BRI_CON_CTRL )
+#define VDIN1_GO_LINE_CTRL ((VDIN1_OFFSET << 2) + VDIN_GO_LINE_CTRL )
+#define VDIN1_HIST_CTRL ((VDIN1_OFFSET << 2) + VDIN_HIST_CTRL )
+#define VDIN1_HIST_H_START_END ((VDIN1_OFFSET << 2) + VDIN_HIST_H_START_END )
+#define VDIN1_HIST_V_START_END ((VDIN1_OFFSET << 2) + VDIN_HIST_V_START_END )
+#define VDIN1_HIST_MAX_MIN ((VDIN1_OFFSET << 2) + VDIN_HIST_MAX_MIN )
+#define VDIN1_HIST_SPL_VAL ((VDIN1_OFFSET << 2) + VDIN_HIST_SPL_VAL )
+#define VDIN1_HIST_SPL_PIX_CNT ((VDIN1_OFFSET << 2) + VDIN_HIST_SPL_PIX_CNT )
+#define VDIN1_HIST_CHROMA_SUM ((VDIN1_OFFSET << 2) + VDIN_HIST_CHROMA_SUM )
+#define VDIN1_DNLP_HIST00 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST00 )
+#define VDIN1_DNLP_HIST01 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST01 )
+#define VDIN1_DNLP_HIST02 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST02 )
+#define VDIN1_DNLP_HIST03 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST03 )
+#define VDIN1_DNLP_HIST04 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST04 )
+#define VDIN1_DNLP_HIST05 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST05 )
+#define VDIN1_DNLP_HIST06 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST06 )
+#define VDIN1_DNLP_HIST07 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST07 )
+#define VDIN1_DNLP_HIST08 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST08 )
+#define VDIN1_DNLP_HIST09 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST09 )
+#define VDIN1_DNLP_HIST10 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST10 )
+#define VDIN1_DNLP_HIST11 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST11 )
+#define VDIN1_DNLP_HIST12 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST12 )
+#define VDIN1_DNLP_HIST13 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST13 )
+#define VDIN1_DNLP_HIST14 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST14 )
+#define VDIN1_DNLP_HIST15 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST15 )
+#define VDIN1_DNLP_HIST16 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST16 )
+#define VDIN1_DNLP_HIST17 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST17 )
+#define VDIN1_DNLP_HIST18 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST18 )
+#define VDIN1_DNLP_HIST19 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST19 )
+#define VDIN1_DNLP_HIST20 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST20 )
+#define VDIN1_DNLP_HIST21 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST21 )
+#define VDIN1_DNLP_HIST22 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST22 )
+#define VDIN1_DNLP_HIST23 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST23 )
+#define VDIN1_DNLP_HIST24 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST24 )
+#define VDIN1_DNLP_HIST25 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST25 )
+#define VDIN1_DNLP_HIST26 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST26 )
+#define VDIN1_DNLP_HIST27 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST27 )
+#define VDIN1_DNLP_HIST28 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST28 )
+#define VDIN1_DNLP_HIST29 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST29 )
+#define VDIN1_DNLP_HIST30 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST30 )
+#define VDIN1_DNLP_HIST31 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST31 )
+#define VDIN1_DNLP_HIST32 ((VDIN1_OFFSET << 2) + VDIN_DNLP_HIST32 )
+#define VDIN1_MEAS_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_MEAS_CTRL0 )
+#define VDIN1_MEAS_VS_COUNT_HI ((VDIN1_OFFSET << 2) + VDIN_MEAS_VS_COUNT_HI )
+#define VDIN1_MEAS_VS_COUNT_LO ((VDIN1_OFFSET << 2) + VDIN_MEAS_VS_COUNT_LO )
+#define VDIN1_MEAS_HS_RANGE ((VDIN1_OFFSET << 2) + VDIN_MEAS_HS_RANGE )
+#define VDIN1_MEAS_HS_COUNT ((VDIN1_OFFSET << 2) + VDIN_MEAS_HS_COUNT )
+#define VDIN1_BLKBAR_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_CTRL1 )
+#define VDIN1_BLKBAR_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_CTRL0 )
+#define VDIN1_BLKBAR_H_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_H_START_END )
+#define VDIN1_BLKBAR_V_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_V_START_END )
+#define VDIN1_BLKBAR_CNT_THRESHOLD ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_CNT_THRESHOLD )
+#define VDIN1_BLKBAR_ROW_TH1_TH2 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_ROW_TH1_TH2 )
+#define VDIN1_BLKBAR_IND_LEFT_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_LEFT_START_END )
+#define VDIN1_BLKBAR_IND_RIGHT_START_END ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_RIGHT_START_END )
+#define VDIN1_BLKBAR_IND_LEFT1_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_LEFT1_CNT )
+#define VDIN1_BLKBAR_IND_LEFT2_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_LEFT2_CNT )
+#define VDIN1_BLKBAR_IND_RIGHT1_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_RIGHT1_CNT )
+#define VDIN1_BLKBAR_IND_RIGHT2_CNT ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_IND_RIGHT2_CNT )
+#define VDIN1_BLKBAR_STATUS0 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_STATUS0 )
+#define VDIN1_BLKBAR_STATUS1 ((VDIN1_OFFSET << 2) + VDIN_BLKBAR_STATUS1 )
+#define VDIN1_WIN_H_START_END ((VDIN1_OFFSET << 2) + VDIN_WIN_H_START_END )
+#define VDIN1_WIN_V_START_END ((VDIN1_OFFSET << 2) + VDIN_WIN_V_START_END )
+#define VDIN1_ASFIFO_CTRL3 ((VDIN1_OFFSET << 2) + VDIN_ASFIFO_CTRL3 )
+#define VDIN1_LFIFO_URG_CTRL ((VDIN1_OFFSET << 2) + VDIN_LFIFO_URG_CTRL )
+#define VDIN1_COM_GCLK_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_COM_GCLK_CTRL2 )
+#define VDIN1_VSHRK_CTRL ((VDIN1_OFFSET << 2) + VDIN_VSHRK_CTRL )
+#define VDIN1_SYNC_MASK ((VDIN1_OFFSET << 2) + VDIN_SYNC_MASK )
+#define VDIN1_DOLBY_DSC_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL0 )
+#define VDIN1_DOLBY_DSC_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL1 )
+#define VDIN1_DOLBY_DSC_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL2 )
+#define VDIN1_DOLBY_DSC_CTRL3 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_CTRL3 )
+#define VDIN1_DOLBY_AXI_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL0 )
+#define VDIN1_DOLBY_AXI_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL1 )
+#define VDIN1_DOLBY_AXI_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL2 )
+#define VDIN1_DOLBY_AXI_CTRL3 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_AXI_CTRL3 )
+#define VDIN1_DOLBY_DSC_STATUS0 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS0)
+#define VDIN1_DOLBY_DSC_STATUS1 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS1)
+#define VDIN1_DOLBY_DSC_STATUS2 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS2)
+#define VDIN1_DOLBY_DSC_STATUS3 ((VDIN1_OFFSET << 2) + VDIN_DOLBY_DSC_STATUS3)
+
+#define VDIN1_HDR2_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_CTRL )
+#define VDIN1_HDR2_CLK_GATE ((VDIN1_OFFSET << 2) + VDIN_HDR2_CLK_GATE )
+#define VDIN1_HDR2_MATRIXI_COEF00_01 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF00_01 )
+#define VDIN1_HDR2_MATRIXI_COEF02_10 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF02_10 )
+#define VDIN1_HDR2_MATRIXI_COEF11_12 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF11_12 )
+#define VDIN1_HDR2_MATRIXI_COEF20_21 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF20_21 )
+#define VDIN1_HDR2_MATRIXI_COEF22 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF22 )
+#define VDIN1_HDR2_MATRIXI_COEF30_31 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF30_31 )
+#define VDIN1_HDR2_MATRIXI_COEF32_40 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF32_40 )
+#define VDIN1_HDR2_MATRIXI_COEF41_42 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_COEF41_42 )
+#define VDIN1_HDR2_MATRIXI_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_OFFSET0_1 )
+#define VDIN1_HDR2_MATRIXI_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_OFFSET2 )
+#define VDIN1_HDR2_MATRIXI_PRE_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_PRE_OFFSET0_1 )
+#define VDIN1_HDR2_MATRIXI_PRE_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_PRE_OFFSET2 )
+#define VDIN1_HDR2_MATRIXO_COEF00_01 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF00_01 )
+#define VDIN1_HDR2_MATRIXO_COEF02_10 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF02_10 )
+#define VDIN1_HDR2_MATRIXO_COEF11_12 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF11_12 )
+#define VDIN1_HDR2_MATRIXO_COEF20_21 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF20_21 )
+#define VDIN1_HDR2_MATRIXO_COEF22 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF22 )
+#define VDIN1_HDR2_MATRIXO_COEF30_31 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF30_31 )
+#define VDIN1_HDR2_MATRIXO_COEF32_40 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF32_40 )
+#define VDIN1_HDR2_MATRIXO_COEF41_42 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_COEF41_42 )
+#define VDIN1_HDR2_MATRIXO_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_OFFSET0_1 )
+#define VDIN1_HDR2_MATRIXO_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_OFFSET2 )
+#define VDIN1_HDR2_MATRIXO_PRE_OFFSET0_1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_PRE_OFFSET0_1 )
+#define VDIN1_HDR2_MATRIXO_PRE_OFFSET2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_PRE_OFFSET2 )
+#define VDIN1_HDR2_MATRIXI_CLIP ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_CLIP )
+#define VDIN1_HDR2_MATRIXO_CLIP ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_CLIP )
+#define VDIN1_HDR2_CGAIN_OFFT ((VDIN1_OFFSET << 2) + VDIN_HDR2_CGAIN_OFFT )
+#define VDIN1_EOTF_LUT_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_EOTF_LUT_ADDR_PORT )
+#define VDIN1_EOTF_LUT_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_EOTF_LUT_DATA_PORT )
+#define VDIN1_OETF_LUT_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_OETF_LUT_ADDR_PORT )
+#define VDIN1_OETF_LUT_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_OETF_LUT_DATA_PORT )
+#define VDIN1_OGAIN_LUT_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_OGAIN_LUT_ADDR_PORT )
+#define VDIN1_OGAIN_LUT_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_OGAIN_LUT_DATA_PORT )
+#define VDIN1_CGAIN_LUT_ADDR_PORT ((VDIN1_OFFSET << 2) + VDIN_CGAIN_LUT_ADDR_PORT )
+#define VDIN1_CGAIN_LUT_DATA_PORT ((VDIN1_OFFSET << 2) + VDIN_CGAIN_LUT_DATA_PORT )
+#define VDIN1_HDR2_CGAIN_COEF0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_CGAIN_COEF0 )
+#define VDIN1_HDR2_CGAIN_COEF1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_CGAIN_COEF1 )
+#define VDIN1_HDR2_ADPS_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_CTRL )
+#define VDIN1_HDR2_ADPS_ALPHA0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_ALPHA0 )
+#define VDIN1_HDR2_ADPS_ALPHA1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_ALPHA1 )
+#define VDIN1_HDR2_ADPS_BETA0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_BETA0 )
+#define VDIN1_HDR2_ADPS_BETA1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_BETA1 )
+#define VDIN1_HDR2_ADPS_BETA2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_BETA2 )
+#define VDIN1_HDR2_ADPS_COEF0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_COEF0 )
+#define VDIN1_HDR2_ADPS_COEF1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_ADPS_COEF1 )
+#define VDIN1_HDR2_GMUT_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_CTRL )
+#define VDIN1_HDR2_GMUT_COEF0 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF0 )
+#define VDIN1_HDR2_GMUT_COEF1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF1 )
+#define VDIN1_HDR2_GMUT_COEF2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF2 )
+#define VDIN1_HDR2_GMUT_COEF3 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF3 )
+#define VDIN1_HDR2_GMUT_COEF4 ((VDIN1_OFFSET << 2) + VDIN_HDR2_GMUT_COEF4 )
+#define VDIN1_HDR2_PIPE_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PIPE_CTRL1 )
+#define VDIN1_HDR2_PIPE_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PIPE_CTRL2 )
+#define VDIN1_HDR2_PIPE_CTRL3 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PIPE_CTRL3 )
+#define VDIN1_HDR2_PROC_WIN1 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PROC_WIN1 )
+#define VDIN1_HDR2_PROC_WIN2 ((VDIN1_OFFSET << 2) + VDIN_HDR2_PROC_WIN2 )
+#define VDIN1_HDR2_MATRIXI_EN_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXI_EN_CTRL )
+#define VDIN1_HDR2_MATRIXO_EN_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_MATRIXO_EN_CTRL )
+#define VDIN1_HDR2_HIST_CTRL ((VDIN1_OFFSET << 2) + VDIN_HDR2_HIST_CTRL )
+#define VDIN1_HDR2_HIST_H_START_END ((VDIN1_OFFSET << 2) + VDIN_HDR2_HIST_H_START_END )
+#define VDIN1_HDR2_HIST_V_START_END ((VDIN1_OFFSET << 2) + VDIN_HDR2_HIST_V_START_END )
+#define VDIN1_HDR2_HIST_RD ((VDIN1_OFFSET << 2) + VDIN_HDR2_HIST_RD )
+
+
+
+#define VDIN1_CRC_CTRL ((VDIN1_OFFSET << 2) + VDIN_CRC_CTRL)
+#define VDIN1_RO_CRC ((VDIN1_OFFSET << 2) + VDIN_RO_CRC )
+#define VDIN1_LINE_INT ((VDIN1_OFFSET << 2) + VDIN_LINE_INT)
+#define VDIN1_WR_URGENT_CTRL ((VDIN1_OFFSET << 2) + VDIN_WR_URGENT_CTRL)
+#define VDIN1_RO_WRMIF_STATUS ((VDIN1_OFFSET << 2) + VDIN_RO_WRMIF_STATUS)
+
+#define VDIN1_WR_BADDR_LUMA ((VDIN1_OFFSET << 2) + VDIN_WR_BADDR_LUMA )
+#define VDIN1_WR_BADDR_CHROMA ((VDIN1_OFFSET << 2) + VDIN_WR_BADDR_CHROMA )
+#define VDIN1_WR_STRIDE_LUMA ((VDIN1_OFFSET << 2) + VDIN_WR_STRIDE_LUMA )
+#define VDIN1_WR_STRIDE_CHROMA ((VDIN1_OFFSET << 2) + VDIN_WR_STRIDE_CHROMA)
+
+#define VDIN1_DSC_CTRL ((VDIN1_OFFSET << 2) + VDIN_DSC_CTRL )
+#define VDIN1_CFMT_CTRL ((VDIN1_OFFSET << 2) + VDIN_CFMT_CTRL )
+#define VDIN1_CFMT_W ((VDIN1_OFFSET << 2) + VDIN_CFMT_W )
+#define VDIN1_SCB_CTRL0 ((VDIN1_OFFSET << 2) + VDIN_SCB_CTRL0 )
+#define VDIN1_SCB_CTRL1 ((VDIN1_OFFSET << 2) + VDIN_SCB_CTRL1 )
+#define VDIN1_SCB_CTRL2 ((VDIN1_OFFSET << 2) + VDIN_SCB_CTRL2 )
+#define VDIN1_DSC_HSIZE ((VDIN1_OFFSET << 2) + VDIN_DSC_HSIZE )
+#define VDIN1_DSC_DETUNNEL_SEL ((VDIN1_OFFSET << 2) + VDIN_DSC_DETUNNEL_SEL)
+#define VDIN1_DSC_TUNNEL_SEL ((VDIN1_OFFSET << 2) + VDIN_DSC_TUNNEL_SEL)
+#define VDIN1_DITH_CTRL ((VDIN1_OFFSET << 2) + VDIN_DITH_CTRL )
+#define VDIN1_DITH_LUT_1 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_1 )
+#define VDIN1_DITH_LUT_2 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_2 )
+#define VDIN1_DITH_LUT_3 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_3 )
+#define VDIN1_DITH_LUT_4 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_4 )
+#define VDIN1_DITH_LUT_5 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_5 )
+#define VDIN1_DITH_LUT_6 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_6 )
+#define VDIN1_DITH_LUT_7 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_7 )
+#define VDIN1_DITH_LUT_8 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_8 )
+#define VDIN1_DITH_LUT_9 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_9 )
+#define VDIN1_DITH_LUT_10 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_10 )
+#define VDIN1_DITH_LUT_11 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_11 )
+#define VDIN1_DITH_LUT_12 ((VDIN1_OFFSET << 2) + VDIN_DITH_LUT_12 )
+
+#define VDIN1_HSK_CTRL ((VDIN1_OFFSET << 2) + VDIN_HSK_CTRL )
+#define VDIN1_HSK_COEF_0 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_0 )
+#define VDIN1_HSK_COEF_1 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_1 )
+#define VDIN1_HSK_COEF_2 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_2 )
+#define VDIN1_HSK_COEF_3 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_3 )
+#define VDIN1_HSK_COEF_4 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_4 )
+#define VDIN1_HSK_COEF_5 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_5 )
+#define VDIN1_HSK_COEF_6 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_6 )
+#define VDIN1_HSK_COEF_7 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_7 )
+#define VDIN1_HSK_COEF_8 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_8 )
+#define VDIN1_HSK_COEF_9 ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_9 )
+#define VDIN1_HSK_COEF_A ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_A )
+#define VDIN1_HSK_COEF_B ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_B )
+#define VDIN1_HSK_COEF_C ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_C )
+#define VDIN1_HSK_COEF_D ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_D )
+#define VDIN1_HSK_COEF_E ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_E )
+#define VDIN1_HSK_COEF_F ((VDIN1_OFFSET << 2) + VDIN_HSK_COEF_F )
+
+#define VDIN1_HDR2_SIZE ((VDIN1_OFFSET << 2) + VDIN_HDR2_SIZE )
+#define VDIN1_VSHRK_SIZE_M1 ((VDIN1_OFFSET << 2) + VDIN_VSHRK_SIZE_M1)
+
+
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_vdin1_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: LCD0_VCBUS_BASE = 0x14
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: lcd_regs.h
+//
+// 0x00 - 0x9f
+//
+// Reading file: ldc_cbus.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define LDC_REG_BLOCK_NUM ((0x1400 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20 reg_ldc_en // unsigned , RW, default = 1 1:enable ldc ,0:disable ldc
+//Bit 19:14 reg_ldc_seg_col // unsigned , RW, default = 16 the number of col segments for calculate backlight
+//Bit 13: 8 reg_ldc_seg_row // unsigned , RW, default = 9 the number of row segments for calculate backlight
+//Bit 7: 4 reg_ldc_blk_xnum // unsigned , RW, default = 7 the number of col blocks for calculate intensity, 1<<blk_xnum
+//Bit 3: 0 reg_ldc_blk_ynum // unsigned , RW, default = 6 the number of row blocks for calculate intensity, 1<<blk_ynum
+#define LDC_REG_SEG_Y_BOUNDARY_0_1 ((0x1401 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:13 reg_ldc_seg_y_boundary_0 // unsigned , RW, default = 0 the segment row boundary
+//Bit 12: 0 reg_ldc_seg_y_boundary_1 // unsigned , RW, default = 0 the segment row boundary
+#define LDC_REG_SEG_Y_BOUNDARY_2_3 ((0x1402 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:13 reg_ldc_seg_y_boundary_2 // unsigned , RW, default = 0 the segment row boundary
+//Bit 12: 0 reg_ldc_seg_y_boundary_3 // unsigned , RW, default = 0 the segment row boundary
+#define LDC_REG_SEG_Y_BOUNDARY_4_5 ((0x1403 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:13 reg_ldc_seg_y_boundary_4 // unsigned , RW, default = 0 the segment row boundary
+//Bit 12: 0 reg_ldc_seg_y_boundary_5 // unsigned , RW, default = 0 the segment row boundary
+#define LDC_REG_SEG_Y_BOUNDARY_6_7 ((0x1404 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:13 reg_ldc_seg_y_boundary_6 // unsigned , RW, default = 0 the segment row boundary
+//Bit 12: 0 reg_ldc_seg_y_boundary_7 // unsigned , RW, default = 0 the segment row boundary
+#define LDC_REG_SEG_Y_BOUNDARY_8_9 ((0x1405 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:13 reg_ldc_seg_y_boundary_8 // unsigned , RW, default = 0 the segment row boundary
+//Bit 12: 0 reg_ldc_seg_y_boundary_9 // unsigned , RW, default = 0 the segment row boundary
+#define LDC_REG_SEG_Y_BOUNDARY_10_11 ((0x1406 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:13 reg_ldc_seg_y_boundary_10 // unsigned , RW, default = 0 the segment row boundary
+//Bit 12: 0 reg_ldc_seg_y_boundary_11 // unsigned , RW, default = 0 the segment row boundary
+#define LDC_REG_SEG_Y_BOUNDARY_12_13 ((0x1407 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:13 reg_ldc_seg_y_boundary_12 // unsigned , RW, default = 0 the segment row boundary
+//Bit 12: 0 reg_ldc_seg_y_boundary_13 // unsigned , RW, default = 0 the segment row boundary
+#define LDC_REG_SEG_Y_BOUNDARY_14_15 ((0x1408 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:13 reg_ldc_seg_y_boundary_14 // unsigned , RW, default = 0 the segment row boundary
+//Bit 12: 0 reg_ldc_seg_y_boundary_15 // unsigned , RW, default = 0 the segment row boundary
+#define LDC_REG_SEG_Y_BOUNDARY_16_17 ((0x1409 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:13 reg_ldc_seg_y_boundary_16 // unsigned , RW, default = 0 the segment row boundary
+//Bit 12: 0 reg_ldc_seg_y_boundary_17 // unsigned , RW, default = 0 the segment row boundary
+#define LDC_REG_SEG_Y_BOUNDARY_18_19 ((0x140a << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:13 reg_ldc_seg_y_boundary_18 // unsigned , RW, default = 0 the segment row boundary
+//Bit 12: 0 reg_ldc_seg_y_boundary_19 // unsigned , RW, default = 0 the segment row boundary
+#define LDC_REG_SEG_Y_BOUNDARY_20_21 ((0x140b << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:13 reg_ldc_seg_y_boundary_20 // unsigned , RW, default = 0 the segment row boundary
+//Bit 12: 0 reg_ldc_seg_y_boundary_21 // unsigned , RW, default = 0 the segment row boundary
+#define LDC_REG_SEG_Y_BOUNDARY_22_23 ((0x140c << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:13 reg_ldc_seg_y_boundary_22 // unsigned , RW, default = 0 the segment row boundary
+//Bit 12: 0 reg_ldc_seg_y_boundary_23 // unsigned , RW, default = 0 the segment row boundary
+#define LDC_REG_SEG_Y_BOUNDARY_24_25 ((0x140d << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:13 reg_ldc_seg_y_boundary_24 // unsigned , RW, default = 0 the segment row boundary
+//Bit 12: 0 reg_ldc_seg_y_boundary_25 // unsigned , RW, default = 0 the segment row boundary
+#define LDC_REG_SEG_Y_BOUNDARY_26_27 ((0x140e << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:13 reg_ldc_seg_y_boundary_26 // unsigned , RW, default = 0 the segment row boundary
+//Bit 12: 0 reg_ldc_seg_y_boundary_27 // unsigned , RW, default = 0 the segment row boundary
+#define LDC_REG_SEG_Y_BOUNDARY_28_29 ((0x140f << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:13 reg_ldc_seg_y_boundary_28 // unsigned , RW, default = 0 the segment row boundary
+//Bit 12: 0 reg_ldc_seg_y_boundary_29 // unsigned , RW, default = 0 the segment row boundary
+#define LDC_REG_SEG_Y_BOUNDARY_30_31 ((0x1410 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:13 reg_ldc_seg_y_boundary_30 // unsigned , RW, default = 0 the segment row boundary
+//Bit 12: 0 reg_ldc_seg_y_boundary_31 // unsigned , RW, default = 0 the segment row boundary
+#define LDC_REG_SEG_X_BOUNDARY_0_1 ((0x1411 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_0 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_1 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_2_3 ((0x1412 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_2 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_3 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_4_5 ((0x1413 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_4 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_5 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_6_7 ((0x1414 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_6 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_7 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_8_9 ((0x1415 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_8 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_9 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_10_11 ((0x1416 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_10 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_11 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_12_13 ((0x1417 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_12 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_13 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_14_15 ((0x1418 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_14 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_15 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_16_17 ((0x1419 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_16 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_17 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_18_19 ((0x141a << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_18 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_19 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_20_21 ((0x141b << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_20 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_21 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_22_23 ((0x141c << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_22 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_23 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_24_25 ((0x141d << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_24 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_25 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_26_27 ((0x141e << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_26 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_27 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_28_29 ((0x141f << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_28 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_29 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_30_31 ((0x1420 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_30 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_31 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_32_33 ((0x1421 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_32 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_33 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_34_35 ((0x1422 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_34 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_35 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_36_37 ((0x1423 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_36 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_37 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_38_39 ((0x1424 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_38 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_39 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_40_41 ((0x1425 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_40 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_41 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_42_43 ((0x1426 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_42 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_43 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_44_45 ((0x1427 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_44 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_45 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_SEG_X_BOUNDARY_46_47 ((0x1428 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:14 reg_ldc_seg_x_boundary_46 // unsigned , RW, default = 0 the segment col boundary
+//Bit 13: 0 reg_ldc_seg_x_boundary_47 // unsigned , RW, default = 0 the segment col boundary
+#define LDC_REG_PANEL_SIZE ((0x1429 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_panel_width // unsigned , RW, default = 0 the panel width
+//Bit 15: 0 reg_ldc_panel_height // unsigned , RW, default = 0 the panel height
+#define LDC_REG_DOWNSAMPLE ((0x142a << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:24 reg_ldc_h_downsample // unsigned , RW, default = 1 horizontal downsample scale, 1:/4, 2:/8, 3:/16, 4:/32
+//Bit 23 reg_ldc_ds_filter_mode // unsigned , RW, default = 1 horizontal downsample filter mode, 0: avg 1: max
+//Bit 22:15 reg_ldc_y_gain // unsigned , RW, default = 8'h40 the gain for input pixel value, 0x40 ==1
+//Bit 14:12 reg_ldc_hist_mode // unsigned , RW, default = 3 the mode for hist statistic value to calculate initial backlight, 0:avg 1: max95, 2, max, 3:blend, 4: adaptive blend coef and blend target(max95 or max)
+//Bit 11 reg_ldc_hist_blend_mode // unsigned , RW, default = 1 the blend mode to calculate initial backlight when hist mode=3, 0: max + avg, 1:max95 + avg
+//Bit 10: 4 reg_ldc_hist_blend_alpha // unsigned , RW, default = 7'h60 the coef for blend when hist mode=3, 128 means "1"
+//Bit 3: 0 reg_ldc_hist_adap_blend_max_gain // unsigned , RW, default = 13 the gain for blend max value when hist mode=4
+#define LDC_REG_HIST_OVERLAP ((0x142b << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:18 reg_ldc_seg_x_overlap // unsigned , RW, default = 0 the overlap pixel num for each segment in col
+//Bit 17: 8 reg_ldc_seg_y_overlap // unsigned , RW, default = 0 the overlap pixel num for each segment in row
+//Bit 7: 0 reg_ldc_max95_ratio // unsigned , RW, default = 10 max95 percentile //10
+#define LDC_REG_BLEND_DIFF_TH ((0x142c << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_ldc_hist_adap_blend_diff_th1 // unsigned , RW, default = 256 the threshold between max95 and average when hist mode=4, default= 4<<6
+//Bit 11: 0 reg_ldc_hist_adap_blend_diff_th2 // unsigned , RW, default = 640 the threshold between max95 and average when hist mode=4, default= 10<<6
+#define LDC_REG_CURVE_COEF ((0x142d << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:18 reg_ldc_hist_adap_blend_gain_0 // unsigned , RW, default = 8'h70 the blend gain0 in curve when hist mode=4
+//Bit 17:10 reg_ldc_hist_adap_blend_gain_1 // unsigned , RW, default = 8'h40 the blend gain1 in curve when hist mode=4
+//Bit 9: 4 reg_ldc_hist_adap_blend_th0 // unsigned , RW, default = 2 the blend threshold base in curve when hist mode=4
+//Bit 3: 0 reg_ldc_hist_adap_blend_thn // unsigned , RW, default = 4 the blend threshold increase step in curve when hist mode=4, th0+1<<thn
+#define LDC_REG_INIT_BL ((0x142e << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_ldc_init_bl_min // unsigned , RW, default = 0 the minimum value of init_bl
+//Bit 11: 0 reg_ldc_init_bl_max // unsigned , RW, default = 12'hfff the maximum value of init_bl
+#define LDC_REG_SF_MODE ((0x142f << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_ldc_sf_mode // unsigned , RW, default = 2 the mode for backlight spatial filter, 0: no filter, 1: TSF filter , 2: new spatial filter
+//Bit 23:12 reg_ldc_sf_tsf_3x3 // unsigned , RW, default = 12'h600 smoothness control of the spatial filter at 3x3
+//Bit 11: 0 reg_ldc_sf_tsf_5x5 // unsigned , RW, default = 12'hC00 smoothness control of the spatial filter at 5x5
+#define LDC_REG_SF_GAIN ((0x1430 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_ldc_sf_gain_up // unsigned , RW, default = 8'h20 the gain for backlight up
+//Bit 7: 0 reg_ldc_sf_gain_dn // unsigned , RW, default = 8'h00 the gain for backlight down,256 as "1"
+#define LDC_REG_BS_MODE ((0x1431 << 2) + 0xff000000)
+//Bit 31:15 reserved
+//Bit 14:12 reg_ldc_bs_bl_mode // unsigned , RW, default = 0 the boost mode, 0:no boost,1:glb boost,2:local boost,3:max,4:min,5:avg
+//Bit 11: 0 reg_ldc_glb_apl // unsigned , RW, default = 4095 global apl for one channel
+#define LDC_REG_APL ((0x1432 << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7: 0 reg_ldc_bs_glb_apl_gain // unsigned , RW, default = 8'h20 0x10 as "1"
+#define LDC_REG_GLB_BOOST ((0x1433 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 reg_ldc_bs_dark_scene_bl_th // unsigned , RW, default = 12'h200 the global threshold for dark scene
+//Bit 15: 8 reg_ldc_bs_gain // unsigned , RW, default = 8'h20 the boost gain, default=0x20, 256 as "1"
+//Bit 7: 0 reg_ldc_bs_limit_gain // unsigned , RW, default = 8'h60 the boost limit gain, 0x40 as "1"
+#define LDC_REG_LOCAL_BOOST ((0x1434 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:20 reg_ldc_bs_loc_apl_gain // unsigned , RW, default = 8'h20 the local apl gain for dark scene, 0x10 as "1"
+//Bit 19:12 reg_ldc_bs_loc_max_min_gain // unsigned , RW, default = 8'h20 the local boost gain,0x10 as "1"
+//Bit 11: 0 reg_ldc_bs_loc_dark_scene_bl_th // unsigned , RW, default = 12'h600 the local threshold for dark scene
+#define LDC_REG_TF ((0x1435 << 2) + 0xff000000)
+//Bit 31:24 reg_ldc_tf_low_alpha // unsigned , RW, default = 8'h20 the low alpha for temporal filter
+//Bit 23:16 reg_ldc_tf_high_alpha // unsigned , RW, default = 8'h20 the high alpha for temporal filter
+//Bit 15: 8 reg_ldc_tf_low_alpha_sc // unsigned , RW, default = 8'h40 the low alpha for temporal filter in scene change
+//Bit 7: 0 reg_ldc_tf_high_alpha_sc // unsigned , RW, default = 8'h40 the high alpha for temporal filter in scene change
+#define LDC_REG_TF_SC ((0x1436 << 2) + 0xff000000)
+//Bit 31: 9 reserved
+//Bit 8 reg_ldc_tf_sc_flag // unsigned , RW, default = 0 the flag for scene change
+//Bit 7: 4 reg_ldc_cmp_mask_x // unsigned , RW, default = 7 the mask width from profile to calculate one block intensity
+//Bit 3: 0 reg_ldc_cmp_mask_y // unsigned , RW, default = 7 the mask height from profile to calculate one block intensity
+#define LDC_REG_PROFILE_MODE ((0x1437 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 8 reg_ldc_profile_k // unsigned , RW, default = 16'h240 the profile numerator coef
+//Bit 7: 0 reg_ldc_profile_bits // unsigned , RW, default = 8'h18 the profile denominator coef
+#define LDC_REG_BLK_FILTER ((0x1438 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_ldc_block_filter_a // unsigned , RW, default = 56 the coef for block intensity filter
+//Bit 7: 0 reg_ldc_block_filter_b // unsigned , RW, default = 37 the coef for block intensity filter
+#define LDC_REG_BLK_FILTER_COEF ((0x1439 << 2) + 0xff000000)
+//Bit 31:24 reg_ldc_block_filter_c // unsigned , RW, default = 20 the coef for block intensity filter
+//Bit 23:16 reg_ldc_block_filter_d // unsigned , RW, default = 10 the coef for block intensity filter
+//Bit 15: 8 reg_ldc_block_filter_e // unsigned , RW, default = 5 the coef for block intensity filter
+//Bit 7: 0 reg_ldc_block_filter_f // unsigned , RW, default = 2 the coef for block intensity filter
+#define LDC_REG_BL_MEMORY ((0x143a << 2) + 0xff000000)
+//Bit 31: 3 reserved
+//Bit 2: 0 reg_ldc_bl_buf_diff // unsigned , RW, default = 0 the memory diff frame
+#define LDC_REG_FACTOR_DIV_0 ((0x143b << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_factor_for_div_00 // unsigned , RW, default = 33893 the factor for divide,33893:2160; 34952:1080
+//Bit 15: 0 reg_ldc_factor_for_div_01 // unsigned , RW, default = 33893 the factor for divide,33893:2160; 34952:1080
+#define LDC_REG_FACTOR_DIV_1 ((0x143c << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_factor_for_div_10 // unsigned , RW, default = 32896 the factor for divide
+//Bit 15: 0 reg_ldc_factor_for_div_11 // unsigned , RW, default = 32896 the factor for divide
+#define LDC_REG_BITS_DIV ((0x143d << 2) + 0xff000000)
+//Bit 31:24 reg_ldc_bits_for_div_00 // unsigned , RW, default = 25 the bits for divide, 25:2160; 23:1080
+//Bit 23:16 reg_ldc_bits_for_div_01 // unsigned , RW, default = 25 the bits for divide, 25:2160; 23:1080
+//Bit 15: 8 reg_ldc_bits_for_div_10 // unsigned , RW, default = 25 the bits for divide, 25:2160; 23:1080
+//Bit 7: 0 reg_ldc_bits_for_div_11 // unsigned , RW, default = 25 the bits for divide, 25:2160; 23:1080
+#define LDC_REG_GLB_GAIN ((0x143e << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11: 0 reg_ldc_glb_gain // unsigned , RW, default = 1024 the global coef for compensation gain
+#define LDC_REG_DITHER ((0x143f << 2) + 0xff000000)
+//Bit 31: 2 reserved
+//Bit 1 reg_ldc_dth_en // unsigned , RW, default = 0 the enable dither
+//Bit 0 reg_ldc_dth_bw // unsigned , RW, default = 0 0: 2bits, 1: 4bits
+#define LDC_REG_MIN_GAIN_LUT_0 ((0x1440 << 2) + 0xff000000)
+//Bit 31:24 reg_ldc_min_gain_lut_3 // unsigned , RW, default = 8'h40
+//Bit 23:16 reg_ldc_min_gain_lut_2 // unsigned , RW, default = 8'h40
+//Bit 15: 8 reg_ldc_min_gain_lut_1 // unsigned , RW, default = 8'h40
+//Bit 7: 0 reg_ldc_min_gain_lut_0 // unsigned , RW, default = 8'h40
+#define LDC_REG_MIN_GAIN_LUT_1 ((0x1441 << 2) + 0xff000000)
+//Bit 31:24 reg_ldc_min_gain_lut_7 // unsigned , RW, default = 8'h40
+//Bit 23:16 reg_ldc_min_gain_lut_6 // unsigned , RW, default = 8'h40
+//Bit 15: 8 reg_ldc_min_gain_lut_5 // unsigned , RW, default = 8'h40
+//Bit 7: 0 reg_ldc_min_gain_lut_4 // unsigned , RW, default = 8'h40
+#define LDC_REG_MIN_GAIN_LUT_2 ((0x1442 << 2) + 0xff000000)
+//Bit 31:24 reg_ldc_min_gain_lut_11 // unsigned , RW, default = 8'h40
+//Bit 23:16 reg_ldc_min_gain_lut_10 // unsigned , RW, default = 8'h40
+//Bit 15: 8 reg_ldc_min_gain_lut_9 // unsigned , RW, default = 8'h40
+//Bit 7: 0 reg_ldc_min_gain_lut_8 // unsigned , RW, default = 8'h40
+#define LDC_REG_MIN_GAIN_LUT_3 ((0x1443 << 2) + 0xff000000)
+//Bit 31:24 reg_ldc_min_gain_lut_15 // unsigned , RW, default = 8'h40
+//Bit 23:16 reg_ldc_min_gain_lut_14 // unsigned , RW, default = 8'h40
+//Bit 15: 8 reg_ldc_min_gain_lut_13 // unsigned , RW, default = 8'h40
+//Bit 7: 0 reg_ldc_min_gain_lut_12 // unsigned , RW, default = 8'h40
+#define LDC_REG_MIN_GAIN_LUT_4 ((0x1444 << 2) + 0xff000000)
+//Bit 31:24 reg_ldc_min_gain_lut_19 // unsigned , RW, default = 8'h40
+//Bit 23:16 reg_ldc_min_gain_lut_18 // unsigned , RW, default = 8'h40
+//Bit 15: 8 reg_ldc_min_gain_lut_17 // unsigned , RW, default = 8'h40
+//Bit 7: 0 reg_ldc_min_gain_lut_16 // unsigned , RW, default = 8'h40
+#define LDC_REG_MIN_GAIN_LUT_5 ((0x1445 << 2) + 0xff000000)
+//Bit 31:24 reg_ldc_min_gain_lut_23 // unsigned , RW, default = 8'h40
+//Bit 23:16 reg_ldc_min_gain_lut_22 // unsigned , RW, default = 8'h40
+//Bit 15: 8 reg_ldc_min_gain_lut_21 // unsigned , RW, default = 8'h40
+//Bit 7: 0 reg_ldc_min_gain_lut_20 // unsigned , RW, default = 8'h40
+#define LDC_REG_MIN_GAIN_LUT_6 ((0x1446 << 2) + 0xff000000)
+//Bit 31:24 reg_ldc_min_gain_lut_27 // unsigned , RW, default = 8'h40
+//Bit 23:16 reg_ldc_min_gain_lut_26 // unsigned , RW, default = 8'h40
+//Bit 15: 8 reg_ldc_min_gain_lut_25 // unsigned , RW, default = 8'h40
+//Bit 7: 0 reg_ldc_min_gain_lut_24 // unsigned , RW, default = 8'h40
+#define LDC_REG_MIN_GAIN_LUT_7 ((0x1447 << 2) + 0xff000000)
+//Bit 31:24 reg_ldc_min_gain_lut_31 // unsigned , RW, default = 8'h40
+//Bit 23:16 reg_ldc_min_gain_lut_30 // unsigned , RW, default = 8'h40
+//Bit 15: 8 reg_ldc_min_gain_lut_29 // unsigned , RW, default = 8'h40
+//Bit 7: 0 reg_ldc_min_gain_lut_28 // unsigned , RW, default = 8'h40
+#define LDC_REG_MIN_GAIN_LUT_8 ((0x1448 << 2) + 0xff000000)
+//Bit 31:24 reg_ldc_min_gain_lut_35 // unsigned , RW, default = 8'h40
+//Bit 23:16 reg_ldc_min_gain_lut_34 // unsigned , RW, default = 8'h40
+//Bit 15: 8 reg_ldc_min_gain_lut_33 // unsigned , RW, default = 8'h40
+//Bit 7: 0 reg_ldc_min_gain_lut_32 // unsigned , RW, default = 8'h40
+#define LDC_REG_MIN_GAIN_LUT_9 ((0x1449 << 2) + 0xff000000)
+//Bit 31:24 reg_ldc_min_gain_lut_39 // unsigned , RW, default = 8'h40
+//Bit 23:16 reg_ldc_min_gain_lut_38 // unsigned , RW, default = 8'h40
+//Bit 15: 8 reg_ldc_min_gain_lut_37 // unsigned , RW, default = 8'h40
+//Bit 7: 0 reg_ldc_min_gain_lut_36 // unsigned , RW, default = 8'h40
+#define LDC_REG_MIN_GAIN_LUT_10 ((0x144a << 2) + 0xff000000)
+//Bit 31:24 reg_ldc_min_gain_lut_43 // unsigned , RW, default = 8'h40
+//Bit 23:16 reg_ldc_min_gain_lut_42 // unsigned , RW, default = 8'h40
+//Bit 15: 8 reg_ldc_min_gain_lut_41 // unsigned , RW, default = 8'h40
+//Bit 7: 0 reg_ldc_min_gain_lut_40 // unsigned , RW, default = 8'h40
+#define LDC_REG_MIN_GAIN_LUT_11 ((0x144b << 2) + 0xff000000)
+//Bit 31:24 reg_ldc_min_gain_lut_47 // unsigned , RW, default = 8'h40
+//Bit 23:16 reg_ldc_min_gain_lut_46 // unsigned , RW, default = 8'h40
+//Bit 15: 8 reg_ldc_min_gain_lut_45 // unsigned , RW, default = 8'h40
+//Bit 7: 0 reg_ldc_min_gain_lut_44 // unsigned , RW, default = 8'h40
+#define LDC_REG_MIN_GAIN_LUT_12 ((0x144c << 2) + 0xff000000)
+//Bit 31:24 reg_ldc_min_gain_lut_51 // unsigned , RW, default = 8'h40
+//Bit 23:16 reg_ldc_min_gain_lut_50 // unsigned , RW, default = 8'h40
+//Bit 15: 8 reg_ldc_min_gain_lut_49 // unsigned , RW, default = 8'h40
+//Bit 7: 0 reg_ldc_min_gain_lut_48 // unsigned , RW, default = 8'h40
+#define LDC_REG_MIN_GAIN_LUT_13 ((0x144d << 2) + 0xff000000)
+//Bit 31:24 reg_ldc_min_gain_lut_55 // unsigned , RW, default = 8'h40
+//Bit 23:16 reg_ldc_min_gain_lut_54 // unsigned , RW, default = 8'h40
+//Bit 15: 8 reg_ldc_min_gain_lut_53 // unsigned , RW, default = 8'h40
+//Bit 7: 0 reg_ldc_min_gain_lut_52 // unsigned , RW, default = 8'h40
+#define LDC_REG_MIN_GAIN_LUT_14 ((0x144e << 2) + 0xff000000)
+//Bit 31:24 reg_ldc_min_gain_lut_59 // unsigned , RW, default = 8'h40
+//Bit 23:16 reg_ldc_min_gain_lut_58 // unsigned , RW, default = 8'h40
+//Bit 15: 8 reg_ldc_min_gain_lut_57 // unsigned , RW, default = 8'h40
+//Bit 7: 0 reg_ldc_min_gain_lut_56 // unsigned , RW, default = 8'h40
+#define LDC_REG_MIN_GAIN_LUT_15 ((0x144f << 2) + 0xff000000)
+//Bit 31:24 reg_ldc_min_gain_lut_63 // unsigned , RW, default = 8'h40
+//Bit 23:16 reg_ldc_min_gain_lut_62 // unsigned , RW, default = 8'h40
+//Bit 15: 8 reg_ldc_min_gain_lut_61 // unsigned , RW, default = 8'h40
+//Bit 7: 0 reg_ldc_min_gain_lut_60 // unsigned , RW, default = 8'h40
+#define LDC_REG_DITHER_LUT_1_0 ((0x1450 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_0 // unsigned , RW, default = 0 the reg dither lut_0
+//Bit 15: 0 reg_ldc_dither_lut2_0 // unsigned , RW, default = 0 the reg dither lut_0
+#define LDC_REG_LDC_DITHER_LUT_1_1 ((0x1451 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_1 // unsigned , RW, default = 0 the reg dither lut_1
+//Bit 15: 0 reg_ldc_dither_lut2_1 // unsigned , RW, default = 0 the reg dither lut_1
+#define LDC_REG_LDC_DITHER_LUT_1_2 ((0x1452 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_2 // unsigned , RW, default = 0 the reg dither lut_2
+//Bit 15: 0 reg_ldc_dither_lut2_2 // unsigned , RW, default = 0 the reg dither lut_2
+#define LDC_REG_LDC_DITHER_LUT_1_3 ((0x1453 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_3 // unsigned , RW, default = 0 the reg dither lut_3
+//Bit 15: 0 reg_ldc_dither_lut2_3 // unsigned , RW, default = 0 the reg dither lut_3
+#define LDC_REG_LDC_DITHER_LUT_1_4 ((0x1454 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_4 // unsigned , RW, default = 0 the reg dither lut_4
+//Bit 15: 0 reg_ldc_dither_lut2_4 // unsigned , RW, default = 0 the reg dither lut_4
+#define LDC_REG_LDC_DITHER_LUT_1_5 ((0x1455 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_5 // unsigned , RW, default = 0 the reg dither lut_5
+//Bit 15: 0 reg_ldc_dither_lut2_5 // unsigned , RW, default = 0 the reg dither lut_5
+#define LDC_REG_LDC_DITHER_LUT_1_6 ((0x1456 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_6 // unsigned , RW, default = 0 the reg dither lut_6
+//Bit 15: 0 reg_ldc_dither_lut2_6 // unsigned , RW, default = 0 the reg dither lut_6
+#define LDC_REG_LDC_DITHER_LUT_1_7 ((0x1457 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_7 // unsigned , RW, default = 0 the reg dither lut_7
+//Bit 15: 0 reg_ldc_dither_lut2_7 // unsigned , RW, default = 0 the reg dither lut_7
+#define LDC_REG_LDC_DITHER_LUT_1_8 ((0x1458 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_8 // unsigned , RW, default = 16'h8241 the reg dither lut_8
+//Bit 15: 0 reg_ldc_dither_lut2_8 // unsigned , RW, default = 16'h8241 the reg dither lut_8
+#define LDC_REG_LDC_DITHER_LUT_1_9 ((0x1459 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_9 // unsigned , RW, default = 16'h4128 thereg dither lut_9
+//Bit 15: 0 reg_ldc_dither_lut2_9 // unsigned , RW, default = 16'h4128 thereg dither lut_9
+#define LDC_REG_LDC_DITHER_LUT_1_10 ((0x145a << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_10 // unsigned , RW, default = 16'h2814 thereg dither lut_10
+//Bit 15: 0 reg_ldc_dither_lut2_10 // unsigned , RW, default = 16'h2814 thereg dither lut_10
+#define LDC_REG_LDC_DITHER_LUT_1_11 ((0x145b << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_11 // unsigned , RW, default = 16'h1482 the reg dither lut_11
+//Bit 15: 0 reg_ldc_dither_lut2_11 // unsigned , RW, default = 16'h1482 the reg dither lut_11
+#define LDC_REG_LDC_DITHER_LUT_1_12 ((0x145c << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_12 // unsigned , RW, default = 16'h1482 the reg dither lut_12
+//Bit 15: 0 reg_ldc_dither_lut2_12 // unsigned , RW, default = 16'h1482 the reg dither lut_12
+#define LDC_REG_LDC_DITHER_LUT_1_13 ((0x145d << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_13 // unsigned , RW, default = 16'h2841 the reg dither lut_13
+//Bit 15: 0 reg_ldc_dither_lut2_13 // unsigned , RW, default = 16'h2841 the reg dither lut_13
+#define LDC_REG_LDC_DITHER_LUT_1_14 ((0x145e << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_14 // unsigned , RW, default = 16'h4128 the reg dither lut_14
+//Bit 15: 0 reg_ldc_dither_lut2_14 // unsigned , RW, default = 16'h4128 the reg dither lut_14
+#define LDC_REG_LDC_DITHER_LUT_1_15 ((0x145f << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_15 // unsigned , RW, default = 16'h8214 the reg dither lut_15
+//Bit 15: 0 reg_ldc_dither_lut2_15 // unsigned , RW, default = 16'h8214 the reg dither lut_15
+#define LDC_REG_LDC_DITHER_LUT_1_16 ((0x1460 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_16 // unsigned , RW, default = 16'h9696 the reg dither lut_16
+//Bit 15: 0 reg_ldc_dither_lut2_16 // unsigned , RW, default = 16'h9696 the reg dither lut_16
+#define LDC_REG_LDC_DITHER_LUT_1_17 ((0x1461 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_17 // unsigned , RW, default = 16'h6969 the reg dither lut_17
+//Bit 15: 0 reg_ldc_dither_lut2_17 // unsigned , RW, default = 16'h6969 the reg dither lut_17
+#define LDC_REG_LDC_DITHER_LUT_1_18 ((0x1462 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_18 // unsigned , RW, default = 16'h9696 the reg dither lut_18
+//Bit 15: 0 reg_ldc_dither_lut2_18 // unsigned , RW, default = 16'h9696 the reg dither lut_18
+#define LDC_REG_LDC_DITHER_LUT_1_19 ((0x1463 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_19 // unsigned , RW, default = 16'h6969 the reg dither lut_19
+//Bit 15: 0 reg_ldc_dither_lut2_19 // unsigned , RW, default = 16'h6969 the reg dither lut_19
+#define LDC_REG_LDC_DITHER_LUT_1_20 ((0x1464 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_20 // unsigned , RW, default = 16'h9669 the reg dither lut_20
+//Bit 15: 0 reg_ldc_dither_lut2_20 // unsigned , RW, default = 16'h9669 the reg dither lut_20
+#define LDC_REG_LDC_DITHER_LUT_1_21 ((0x1465 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_21 // unsigned , RW, default = 16'hc3c3 the reg dither lut_21
+//Bit 15: 0 reg_ldc_dither_lut2_21 // unsigned , RW, default = 16'hc3c3 the reg dither lut_21
+#define LDC_REG_LDC_DITHER_LUT_1_22 ((0x1466 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_22 // unsigned , RW, default = 16'h6996 the reg dither lut_22
+//Bit 15: 0 reg_ldc_dither_lut2_22 // unsigned , RW, default = 16'h6996 the reg dither lut_22
+#define LDC_REG_LDC_DITHER_LUT_1_23 ((0x1467 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_23 // unsigned , RW, default = 16'h3c3c the reg dither lut_23
+//Bit 15: 0 reg_ldc_dither_lut2_23 // unsigned , RW, default = 16'h3c3c the reg dither lut_23
+#define LDC_REG_LDC_DITHER_LUT_1_24 ((0x1468 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_24 // unsigned , RW, default = 16'h7dbe the reg dither lut_24
+//Bit 15: 0 reg_ldc_dither_lut2_24 // unsigned , RW, default = 16'h7dbe the reg dither lut_24
+#define LDC_REG_LDC_DITHER_LUT_1_25 ((0x1469 << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_25 // unsigned , RW, default = 16'hbed7 the reg dither lut_25
+//Bit 15: 0 reg_ldc_dither_lut2_25 // unsigned , RW, default = 16'hbed7 the reg dither lut_25
+#define LDC_REG_LDC_DITHER_LUT_1_26 ((0x146a << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_26 // unsigned , RW, default = 16'hd7eb the reg dither lut_26
+//Bit 15: 0 reg_ldc_dither_lut2_26 // unsigned , RW, default = 16'hd7eb the reg dither lut_26
+#define LDC_REG_LDC_DITHER_LUT_1_27 ((0x146b << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_27 // unsigned , RW, default = 16'heb7d the reg dither lut_27
+//Bit 15: 0 reg_ldc_dither_lut2_27 // unsigned , RW, default = 16'heb7d the reg dither lut_27
+#define LDC_REG_LDC_DITHER_LUT_1_28 ((0x146c << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_28 // unsigned , RW, default = 16'heb7d the reg dither lut_28
+//Bit 15: 0 reg_ldc_dither_lut2_28 // unsigned , RW, default = 16'heb7d the reg dither lut_28
+#define LDC_REG_LDC_DITHER_LUT_1_29 ((0x146d << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_29 // unsigned , RW, default = 16'hd7be the reg dither lut_29
+//Bit 15: 0 reg_ldc_dither_lut2_29 // unsigned , RW, default = 16'hd7be the reg dither lut_29
+#define LDC_REG_LDC_DITHER_LUT_1_30 ((0x146e << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_30 // unsigned , RW, default = 16'hbed7 the reg dither lut_30
+//Bit 15: 0 reg_ldc_dither_lut2_30 // unsigned , RW, default = 16'hbed7 the reg dither lut_30
+#define LDC_REG_LDC_DITHER_LUT_1_31 ((0x146f << 2) + 0xff000000)
+//Bit 31:16 reg_ldc_dither_lut1_31 // unsigned , RW, default = 16'h7deb the reg dither lut_31
+//Bit 15: 0 reg_ldc_dither_lut2_31 // unsigned , RW, default = 16'h7deb the reg dither lut_31
+#define LDC_SEG_INFO_SEL ((0x1470 << 2) + 0xff000000)
+//Bit 31: 1 reserved
+//Bit 0 reg_ldc_bl_duty_info_sft_upd // unsigned , RW, default = 0 0:hardware update duty info; 1:software update duty info
+#define LDC_DDR_ADDR_BASE ((0x1471 << 2) + 0xff000000)
+//Bit 31:0 reg_ldc_ddr_addr_base // unsigned , RW, default = 0 ldc ddr address base
+#define LDC_GAIN_LUT_DATA ((0x1472 << 2) + 0xff000000)
+//Bit 31:0 reg_ldc_gain_lut_data // unsigned , RW, default = 0 gain lut address
+#define LDC_GAIN_LUT_ADDR ((0x1473 << 2) + 0xff000000)
+//Bit 31:0 reg_ldc_gain_lut_addr // unsigned , RW, default = 0 gain lut data
+#define LDC_GAIN_LUT_CTRL0 ((0x1474 << 2) + 0xff000000)
+//Bit 31:2 reserved
+//Bit 1 reg_ldc_gain_lut_smp_data_en_clr // unsigned , RW, default = 0 clear reg_ldc_gain_lut_smp_data_en signal 1: enable 0:disable
+//Bit 0 reg_ldc_gain_lut_wr // unsigned , RW, default = 0 1:software write 0:software read.
+#define LDC_GAIN_LUT_CTRL1 ((0x1475 << 2) + 0xff000000)
+//Bit 31: 1 reserved
+//Bit 0 reg_ldc_gain_lut_str // unsigned , RW, default = 0 0->1:one software write/read start,postive edge valid.
+#define LDC_ADJ_VS_CTRL ((0x1476 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15:0 reg_ldc_blk_intsty_calc_intvl // unsigned , RW, default = 200 delay for one block intensity calculation period
+#define LDC_LOW_POWER_EN ((0x1477 << 2) + 0xff000000)
+//Bit 31: 3 reserved
+//Bit 2 reg_ldc_cbus_clk_gate_free // unsigned , RW, default = 1 1:disable cbus clock gate, 0: enable cbus clock gate
+//Bit 1 reg_ldc_calc_part_clk_gate_free // unsigned , RW, default = 1 1:disable calculation clock gate, 0: enable calculation clock gate
+//Bit 0 reg_ldc_comp_part_clk_gate_free // unsigned , RW, default = 1 1:disable compensation clock gate,0: enable compensation clock gate
+#define LDC_CTRL_MISC0 ((0x1478 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_ldc_frm_end_sel //unsigned , RW, default = 0 1: wait for all axi transfer finish 0:wait for last frame pixel
+//Bit 26 reg_ldc_prt_func_en //unsigned , RW, default = 0 1: enable LDC output protect function 0:disable LDC output protect function
+//Bit 25 reg_ldc_bl_input_sft_ctr_en //unsigned , RW, default = 0 1: software control backlight info write index enable
+//Bit 24:23 reg_ldc_bl_input_sft_wr_idx //unsigned , RW, default = 0 backlight info write index, for debug only
+//Bit 22 reg_ldc_vsync_get_bl_info_en //unsigned , RW, default = 1 0:get backlighth info every block line (no vsync interrupt) 1:get backlighth info accroding to vsync
+//Bit 21:20 reg_ldc_hist_burst_len //unsigned , RW, default = 0 0:2 times 128bit 1:4 times 128bit 2,3:6 times 128bit
+//Bit 19:18 reg_ldc_blk_intsty_burst_len //unsigned , RW, default = 0 0:2 times 128bit 1:4 times 128bit 2:6 times 128bit 3:8 times 128bit
+//Bit 17 reg_ldc_vs_edge_sel //unsigned , RW, default = 1 1:posedge vs sync 0:negedge vs sync
+//Bit 16 reg_ldc_adj_vs_en //unsigned , RW, default = 0 move "vs" to frame end,so use front+back porch time to prefetch profile. 1:enable 0:disable;
+//Bit 15:0 reg_ldc_adj_vs_delay_num //unsigned , RW, default = 500 add a delay num to the frame end
+#define LDC_CTRL_MISC1 ((0x1479 << 2) + 0xff000000)
+//Bit 31:4 reserved
+//Bit 3 reg_ldc_sft_upd_glb_apl_en //unsigned , RW, default = 1 update reg_ldc_glb_apl register every frame by .. 1: by software; 0: by hardware;
+//Bit 2 reg_ldc_scn_chg_en //unsigned , RW, default = 0 positive edge available;
+//Bit 1 reg_ldc_pref_chk_err_clr //unsigned , RW, default = 1 1:clear ldc_pref_chk_err signal; 0: no action;
+//Bit 0 reg_ldc_pref_chk_err_det_mode //unsigned , RW, default = 0 1:auto clear ldc_pref_chk_err signal every frame; 0:no action;
+#define LDC_DGB_CTRL ((0x147a << 2) + 0xff000000)
+//Bit 31:15 reserved
+//Bit 14 reg_ldc_comp_en //unsigned, RW, default = 1 1:enable ldc compensation 0:disable ldc compensation
+//Bit 13 reg_ldc_comp_pxl_cmp_en //unsigned, RW, default = 1 1:enable comp_pxl_cmp_en 0:disable comp_pxl_cmp_en
+//Bit 12 reg_ldc_comp_interp_pxl_en //unsigned, RW, default = 1 1:enable comp_interp_pxl_en 0:disable comp_interp_pxl_en
+//Bit 11 reg_ldc_comp_blk_flt_en //unsigned, RW, default = 1 1:enable comp_blk_flt_en 0:disable comp_blk_flt_en
+//Bit 10 reg_ldc_comp_blk_intsty_en //unsigned, RW, default = 1 1:enable comp_blk_intsty_en 0:disable comp_blk_intsty_en
+//Bit 9 reg_ldc_calc_tmp_flt_en //unsigned, RW, default = 1 1:enable calc_tmp_flt_en 0:disable calc_tmp_flt_en
+//Bit 8:5 reg_ldc_dbg_shft_num //unsigned, RW, default = 0 1:debug
+//Bit 4:1 reg_ldc_dbg_pnt //unsigned, RW, default = 0 detailed info,please refer to application note
+//Bit 0 reg_ldc_dbg_en //unsigned, RW, default = 0 0:normal mode 1: debug mode
+#define LDC_RO_BL_MEMORY_IDX ((0x147b << 2) + 0xff000000)
+//Bit 31: 9 reserved
+//Bit 8 ro_ldc_seg_input_fid // unsigned , RO, default = 0 the memory input segment info index
+//Bit 7: 4 ro_ldc_bl_input_fid // unsigned , RO, default = 0 the memory input frame backlight index
+//Bit 3: 0 ro_ldc_bl_output_fid // unsigned , RO, default = 0 the memory output frame backlight index
+#define LDC_RO_GLB_HIST_SUM ((0x147c << 2) + 0xff000000)
+//Bit 31: 0 ro_ldc_glb_hist_data_sum // unsigned , RO, default = 0 the global hist data sum
+#define LDC_RO_GLB_HIST_CNT ((0x147d << 2) + 0xff000000)
+//Bit 31: 0 ro_ldc_glb_hist_cnt_sum // unsigned , RO, default = 0 the global hist cnt sum
+#define LDC_RO_GAIN_SMP_DATA ((0x147f << 2) + 0xff000000)
+//Bit 31:25 reserved
+//Bit 24 ro_ldc_gain_lut_smp_data_en // unsigned , RO, default = 0 the output frame index
+//Bit 23: 0 ro_ldc_gain_lut_smp_data // unsigned , RO, default = 0 the output frame index
+#define LDC_RO_PREF_CHK_ERROR ((0x1480 << 2) + 0xff000000)
+//Bit 31:1 reserved
+//Bit 0 ro_ldc_pref_chk_err // unsigned , RO, 0:no error found; 1: found error ;
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: ldc_cbus.h
+//
+#define LCD_GAMMA_CNTL_PORT ((0x14a0 << 2) + 0xff000000)
+#define LCD_GAMMA_DATA_PORT ((0x14a1 << 2) + 0xff000000)
+#define LCD_GAMMA_ADDR_PORT ((0x14a2 << 2) + 0xff000000)
+#define LCD_GAMMA_VCOM_HSWITCH_ADDR ((0x14a3 << 2) + 0xff000000)
+#define LCD_RGB_BASE_ADDR ((0x14a5 << 2) + 0xff000000)
+#define LCD_RGB_COEFF_ADDR ((0x14a6 << 2) + 0xff000000)
+#define LCD_POL_CNTL_ADDR ((0x14a7 << 2) + 0xff000000)
+#define LCD_DITH_CNTL_ADDR ((0x14a8 << 2) + 0xff000000)
+#define LCD_GAMMA_PROBE_CTRL ((0x14a9 << 2) + 0xff000000)
+//read only
+#define LCD_GAMMA_PROBE_COLOR_L ((0x14aa << 2) + 0xff000000)
+#define LCD_GAMMA_PROBE_COLOR_H ((0x14ab << 2) + 0xff000000)
+#define LCD_GAMMA_PROBE_HL_COLOR ((0x14ac << 2) + 0xff000000)
+#define LCD_GAMMA_PROBE_POS_X ((0x14ad << 2) + 0xff000000)
+#define LCD_GAMMA_PROBE_POS_Y ((0x14ae << 2) + 0xff000000)
+#define LCD_LCD_MCU_CTL ((0x14b0 << 2) + 0xff000000)
+#define LCD_LCD_MCU_DATA_0 ((0x14b1 << 2) + 0xff000000)
+#define LCD_LCD_MCU_DATA_1 ((0x14b2 << 2) + 0xff000000)
+#define LCD_LCD_PORT_SWAP ((0x14b3 << 2) + 0xff000000)
+#define LCD_GAMMA_CNTL_PORT0 ((0x14b4 << 2) + 0xff000000)
+#define LCD_GAMMA_DATA_PORT0 ((0x14b5 << 2) + 0xff000000)
+#define LCD_GAMMA_ADDR_PORT0 ((0x14b6 << 2) + 0xff000000)
+//
+// Closing file: lcd_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: LCD1_VCBUS_BASE = 0x15
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: lcd1_regs.h
+//
+#define LCD1_GAMMA_CNTL_PORT ((0x15a0 << 2) + 0xff000000)
+#define LCD1_GAMMA_DATA_PORT ((0x15a1 << 2) + 0xff000000)
+#define LCD1_GAMMA_ADDR_PORT ((0x15a2 << 2) + 0xff000000)
+#define LCD1_GAMMA_VCOM_HSWITCH_ADDR ((0x15a3 << 2) + 0xff000000)
+#define LCD1_RGB_BASE_ADDR ((0x15a5 << 2) + 0xff000000)
+#define LCD1_RGB_COEFF_ADDR ((0x15a6 << 2) + 0xff000000)
+#define LCD1_POL_CNTL_ADDR ((0x15a7 << 2) + 0xff000000)
+#define LCD1_DITH_CNTL_ADDR ((0x15a8 << 2) + 0xff000000)
+#define LCD1_GAMMA_PROBE_CTRL ((0x15a9 << 2) + 0xff000000)
+//read only
+#define LCD1_GAMMA_PROBE_COLOR_L ((0x15aa << 2) + 0xff000000)
+#define LCD1_GAMMA_PROBE_COLOR_H ((0x15ab << 2) + 0xff000000)
+#define LCD1_GAMMA_PROBE_HL_COLOR ((0x15ac << 2) + 0xff000000)
+#define LCD1_GAMMA_PROBE_POS_X ((0x15ad << 2) + 0xff000000)
+#define LCD1_GAMMA_PROBE_POS_Y ((0x15ae << 2) + 0xff000000)
+#define LCD1_LCD_MCU_CTL ((0x15b0 << 2) + 0xff000000)
+#define LCD1_LCD_MCU_DATA_0 ((0x15b1 << 2) + 0xff000000)
+#define LCD1_LCD_MCU_DATA_1 ((0x15b2 << 2) + 0xff000000)
+#define LCD1_LCD_PORT_SWAP ((0x15b3 << 2) + 0xff000000)
+#define LCD1_GAMMA_CNTL_PORT0 ((0x15b4 << 2) + 0xff000000)
+#define LCD1_GAMMA_DATA_PORT0 ((0x15b5 << 2) + 0xff000000)
+#define LCD1_GAMMA_ADDR_PORT0 ((0x15b6 << 2) + 0xff000000)
+//
+// Closing file: lcd1_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: LCD2_VCBUS_BASE = 0x16
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: lcd2_regs.h
+//
+#define LCD2_GAMMA_CNTL_PORT ((0x16a0 << 2) + 0xff000000)
+#define LCD2_GAMMA_DATA_PORT ((0x16a1 << 2) + 0xff000000)
+#define LCD2_GAMMA_ADDR_PORT ((0x16a2 << 2) + 0xff000000)
+#define LCD2_GAMMA_VCOM_HSWITCH_ADDR ((0x16a3 << 2) + 0xff000000)
+#define LCD2_RGB_BASE_ADDR ((0x16a5 << 2) + 0xff000000)
+#define LCD2_RGB_COEFF_ADDR ((0x16a6 << 2) + 0xff000000)
+#define LCD2_POL_CNTL_ADDR ((0x16a7 << 2) + 0xff000000)
+#define LCD2_DITH_CNTL_ADDR ((0x16a8 << 2) + 0xff000000)
+#define LCD2_GAMMA_PROBE_CTRL ((0x16a9 << 2) + 0xff000000)
+//read only
+#define LCD2_GAMMA_PROBE_COLOR_L ((0x16aa << 2) + 0xff000000)
+#define LCD2_GAMMA_PROBE_COLOR_H ((0x16ab << 2) + 0xff000000)
+#define LCD2_GAMMA_PROBE_HL_COLOR ((0x16ac << 2) + 0xff000000)
+#define LCD2_GAMMA_PROBE_POS_X ((0x16ad << 2) + 0xff000000)
+#define LCD2_GAMMA_PROBE_POS_Y ((0x16ae << 2) + 0xff000000)
+#define LCD2_LCD_MCU_CTL ((0x16b0 << 2) + 0xff000000)
+#define LCD2_LCD_MCU_DATA_0 ((0x16b1 << 2) + 0xff000000)
+#define LCD2_LCD_MCU_DATA_1 ((0x16b2 << 2) + 0xff000000)
+#define LCD2_LCD_PORT_SWAP ((0x16b3 << 2) + 0xff000000)
+#define LCD2_GAMMA_CNTL_PORT0 ((0x16b4 << 2) + 0xff000000)
+#define LCD2_GAMMA_DATA_PORT0 ((0x16b5 << 2) + 0xff000000)
+#define LCD2_GAMMA_ADDR_PORT0 ((0x16b6 << 2) + 0xff000000)
+//
+// Closing file: lcd2_regs.h
+//
+//===========================================================================
+//===========================================================================
+//
+// Reading file: vpu_mad_regs.h
+//
+//DEINTERLACE module start from 8'h90 end to 8'hff
+// -----------------------------------------------
+// REG_BASE: MAD_VCBUS_BASE = 0x17
+// -----------------------------------------------
+#define DI_PRE_CTRL ((0x1700 << 2) + 0xff000000)
+// bit 31, cbus_pre_frame_rst
+// bit 30, cbus_pre_soft_rst
+// bit 29, pre_field_num
+// bit 27:26, mode_444c422
+// bit 25, di_cont_read_en
+// bit 24:23, mode_422c444
+// bit 22, mtn_after_nr
+// bit 21:16, pre_hold_fifo_lines
+// bit 15, nr_wr_by
+// bit 14, use_vdin_go_line
+// bit 13, di_prevdin_en
+// bit 12, di_pre_viu_link
+// bit 11, di_pre_repeat
+// bit 10, di_pre_drop_1st
+// bit 9, di_buf2_en
+// bit 8, di_chan2_en
+// bit 7, prenr_hist_en
+// bit 6, chan2_hist_en
+// bit 5, hist_check_en
+// bit 4, check_after_nr
+// bit 3, check222p_en
+// bit 2, check322p_en
+// bit 1, mtn_en
+// bit 0, nr_en
+#define DI_POST_CTRL ((0x1701 << 2) + 0xff000000)
+// bit 31, cbus_post_frame_rst
+// bit 30, cbus_post_soft_rst
+// bit 29, post_field_num
+// bit 21:16, post_hold_fifo_lines
+// bit 13, prepost_link
+// bit 12, di_post_viu_link
+// bit 11, di_post_repeat
+// bit 10, di_post_drop_1st
+// bit 9, mif0_to_vpp_en
+// bit 8, di_vpp_out_en
+// bit 7, di_wr_bk_en
+// bit 6, di_mux_en
+// bit 5, di_blend_en
+// bit 4, di_mtnp_read_en
+// bit 3, di_mtn_buf_en
+// bit 2, di_ei_en
+// bit 1, di_buf1_en
+// bit 0, di_buf0_en
+#define DI_POST_SIZE ((0x1702 << 2) + 0xff000000)
+//bit 31:29, diwr_field_mode field mode, 0 frame mode, 4 for field mode botton field, 5 for field mode top field, , 6 for blank line mode
+//bit 28:16, vsize1post
+//bit 12:0, hsize1post
+#define DI_PRE_SIZE ((0x1703 << 2) + 0xff000000)
+//bit 31:29, nrwr_field_mode field mode, 0 frame mode, 4 for field mode botton field, 5 for field mode top field, , 6 for blank line mode
+//bit 28:16, vsize1pre
+//bit 12:0, hsize1pre
+#define DI_EI_CTRL0 ((0x1704 << 2) + 0xff000000)
+//bit 23:16, ei0_filter[2:+] abs_diff_left>filter && ...right>filter && ...top>filter && ...bot>filter -> filter
+//bit 15:8, ei0_threshold[2:+]
+//bit 3, ei0_vertical
+//bit 2, ei0_bpscf2
+//bit 1, ei0_bpsfar1
+#define DI_EI_CTRL1 ((0x1705 << 2) + 0xff000000)
+//bit 31:24, ei0_diff
+//bit 23:16, ei0_angle45
+//bit 15:8, ei0_peak
+//bit 7:0, ei0_cross
+#define DI_EI_CTRL2 ((0x1706 << 2) + 0xff000000)
+//bit 31:24, ei0_close2
+//bit 23:16, ei0_close1
+//bit 15:8, ei0_far2
+//bit 7:0, ei0_far1
+//`define DI_NR_CTRL0 8'h07
+//bit 26, nr_cue_en
+//bit 25, nr2_en
+#define DI_NR_CTRL1 ((0x1708 << 2) + 0xff000000)
+//bit 31:30, mot_p1txtcore_mode
+//bit 29:24, mot_p1txtcore_clmt
+//bit 21:16, mot_p1txtcore_ylmt
+//bit 15:8, mot_p1txtcore_crate
+//bit 7:0, mot_p1txtcore_yrate
+#define DI_NR_CTRL2 ((0x1709 << 2) + 0xff000000)
+//bit 29:24, mot_curtxtcore_clmt
+//bit 21:16, mot_curtxtcore_ylmt
+//bit 15:8, mot_curtxtcore_crate
+//bit 7:0, mot_curtxtcore_yrate
+//`define DI_NR_CTRL3 8'h0a
+//no use
+//`define DI_MTN_CTRL 8'h0b
+//`define DI_CANVAS_URGENT0 8'h0a
+//`define DI_CANVAS_URGENT1 8'h0b
+#define DI_MTN_CTRL1 ((0x170c << 2) + 0xff000000)
+//bit 11:8, mtn_paramtnthd
+//bit 7:0, mtn_parafltthd
+#define DI_BLEND_CTRL ((0x170d << 2) + 0xff000000)
+//bit 31, blend_1_en
+//bit 30, blend_mtn_lpf
+//bit 28, post_mb_en
+//bit 27, blend_mtn3p_max
+//bit 26, blend_mtn3p_min
+//bit 25, blend_mtn3p_ave
+//bit 24, blend_mtn3p_maxtb
+//bit 23, blend_mtn_flt_en
+//bit 22, blend_data_flt_en
+//bit 21:20, blend_top_mode
+//bit 19, blend_reg3_enable
+//bit 18, blend_reg2_enable
+//bit 17, blend_reg1_enable
+//bit 16, blend_reg0_enable
+//bit 15:14, blend_reg3_mode
+//bit 13:12, blend_reg2_mode
+//bit 11:10, blend_reg1_mode
+//bit 9:8, blend_reg0_mode
+//bit 7:0, kdeint
+//`define DI_BLEND_CTRL1 8'h0e
+//no use
+//`define DI_CANVAS_URGENT2 8'h0e
+//`define DI_BLEND_CTRL2 8'h0f
+//no use
+#define DI_ARB_CTRL ((0x170f << 2) + 0xff000000)
+//bit 31:26, di_arb_thd1
+//bit 25:20, di_arb_thd0
+//bit 19, di_arb_tid_mode
+//bit 18, di_arb_arb_mode
+//bit 17, di_arb_acq_en
+//bit 16, di_arb_disable_clk
+//bit 15:0, di_arb_req_en
+#define DI_BLEND_REG0_X ((0x1710 << 2) + 0xff000000)
+//bit 27:16, blend_reg0_startx
+//bit 11:0, blend_reg0_endx
+#define DI_BLEND_REG0_Y ((0x1711 << 2) + 0xff000000)
+#define DI_BLEND_REG1_X ((0x1712 << 2) + 0xff000000)
+#define DI_BLEND_REG1_Y ((0x1713 << 2) + 0xff000000)
+#define DI_BLEND_REG2_X ((0x1714 << 2) + 0xff000000)
+#define DI_BLEND_REG2_Y ((0x1715 << 2) + 0xff000000)
+#define DI_BLEND_REG3_X ((0x1716 << 2) + 0xff000000)
+#define DI_BLEND_REG3_Y ((0x1717 << 2) + 0xff000000)
+#define DI_CLKG_CTRL ((0x1718 << 2) + 0xff000000)
+//bit 31:24, pre_gclk_ctrl no clk gate control. if ==1, module clk is not gated (always on). [3] for pulldown,[2] for mtn_1,[1] for mtn_0,[0] for nr
+//bit 23:16, post_gclk_ctrl no clk gate control. [4] for ei_1, [3] for ei_0,[2] for ei_top, [1] for blend_1, [0] for blend_0
+//bit 1, di_gate_all clk shut down. if ==1 , all di clock shut down
+//bit 0, di_no_clk_gate no clk gate control. if di_gated_all==0 and di_no_clk_gate ==1, all di clock is always working.
+#define DI_EI_CTRL3 ((0x1719 << 2) + 0xff000000)
+//bit 31, reg_ei_1
+//bit 30, reg_demon_en
+//bit 26:24, reg_demon_mux
+//bit 23:20, reg_right_win
+//bit 19:16, reg_left_win
+//bit 7:4, reg_ei_sadm_quatize_margin
+//bit 1:0, reg_ei_sad_relative_mode
+#define DI_EI_CTRL4 ((0x171a << 2) + 0xff000000)
+//bit 29, reg_ei_caldrt_ambliike2_biasvertical
+//bit 28:24, reg_ei_caldrt_addxla2list_drtmax
+//bit 22:20, reg_ei_caldrt_addxla2list_signm0th
+//bit 19, reg_ei_caldrt_addxla2list_mode
+//bit 18:16, reg_ei_signm_sad_cor_rate
+//bit 15:12, reg_ei_signm_sadi_cor_rate
+//bit 11:6, reg_ei_signm_sadi_cor_ofst
+//bit 5:0, reg_ei_signm_sad_ofst
+#define DI_EI_CTRL5 ((0x171b << 2) + 0xff000000)
+//bit 30:28, reg_ei_caldrt_cnflcctchk_frcverthrd
+//bit 26:24, reg_ei_caldrt_cnflctchk_mg
+//bit 23:22, reg_ei_caldrt_cnflctchk_ws
+//bit 21, reg_ei_caldrt_cnflctchk_en
+//bit 20, reg_ei_caldrt_verfrc_final_en
+//bit 19, reg_ei_caldrt_verfrc_retimflt_en
+//bit 18:16, reg_ei_caldrt_verftc_eithratemth
+//bit 15, reg_ei_caldrt_verfrc_retiming_en
+//bit 14:12, reg_ei_caldrt_verfrc_bothratemth
+//bit 11:9, reg_ei_caldrt_ver_thrd
+//bit 8:4, reg_ei_caldrt_addxla2list_drtmin
+//bit 3:0, reg_ei_caldrt_addxla2list_drtlimit
+#define DI_EI_CTRL6 ((0x171c << 2) + 0xff000000)
+//bit 31:24, reg_ei_caldrt_abext_sad12thhig
+//bit 23:16, reg_ei_caldrt_abext_sad00thlow
+//bit 15:8, reg_ei_caldrt_abext_sad12thlow
+//bit 6:4, reg_ei_caldrt_abext_ratemth
+//bit 2:0, reg_ei_caldrt_abext_drtthrd
+#define DI_EI_CTRL7 ((0x171d << 2) + 0xff000000)
+//bit 29, reg_ei_caldrt_xlanopeak_codien
+//bit 28:24, reg_ei_caldrt_xlanopeak_drtmax
+//bit 23, reg_ei_caldrt_xlanopeak_en
+//bit 28:24, reg_ei_caldrt_abext_monotrnd_alpha
+//bit 28:24, reg_ei_caldrt_abext_mononum12_thrd
+//bit 28:24, reg_ei_caldrt_abext_mononum00_thrd
+//bit 28:24, reg_ei_caldrt_abext_sad00rate
+//bit 28:24, reg_ei_caldrt_abext_sad12rate
+//bit 28:24, reg_ei_caldrt_abext_sad00thhig
+#define DI_EI_CTRL8 ((0x171e << 2) + 0xff000000)
+//bit 30:28, reg_ei_assign_headtail_magin
+//bit 26:24, reg_ei_retime_lastcurpncnfltchk_mode
+//bit 22:21, reg_ei_retime_lastcurpncnfltchk_drtth
+//bit 20, reg_ei_caldrt_histchk_cnfid
+//bit 19:16, reg_ei_caldrt_histchk_thrd
+//bit 15, reg_ei_caldrt_histchk_abext
+//bit 14, reg_ei_caldrt_histchk_npen
+//bit 13:11, reg_ei_caldrt_amblike2_drtmg
+//bit 10:8, reg_ei_caldrt_amblike2_valmg
+//bit 7:4, reg_ei_caldrt_amblike2_alpha
+//bit 3:0, reg_ei_caldrt_amblike2_drtth
+#define DI_EI_CTRL9 ((0x171f << 2) + 0xff000000)
+//bit 31:28, reg_ei_caldrt_hcnfcheck_frcvert_xla_th3
+//bit 27, reg_ei_caldrt_hcnfcheck_frcvert_xla_en
+//bit 26:24, reg_ei_caldrt_conf_drtth
+//bit 23:20, reg_ei_caldrt_conf_absdrtth
+//bit 19:18, reg_ei_caldrt_abcheck_mode1
+//bit 17:16, reg_ei_caldrt_abcheck_mode0
+//bit 15:12, reg_ei_caldrt_abcheck_drth1
+//bit 11:8, reg_ei_caldrt_abcheck_drth0
+//bit 6:4, reg_ei_caldrt_abpnchk1_th
+//bit 1, reg_ei_caldrt_abpnchk1_en
+//bit 0, reg_ei_caldrt_abpnchk0_en
+// DEINTERLACE mode check.
+#define DI_MC_REG0_X ((0x1720 << 2) + 0xff000000)
+//bit 27:16, mc_reg0_start_x
+//bit 11:0, mc_reg0_end_x
+#define DI_MC_REG0_Y ((0x1721 << 2) + 0xff000000)
+#define DI_MC_REG1_X ((0x1722 << 2) + 0xff000000)
+#define DI_MC_REG1_Y ((0x1723 << 2) + 0xff000000)
+#define DI_MC_REG2_X ((0x1724 << 2) + 0xff000000)
+#define DI_MC_REG2_Y ((0x1725 << 2) + 0xff000000)
+#define DI_MC_REG3_X ((0x1726 << 2) + 0xff000000)
+#define DI_MC_REG3_Y ((0x1727 << 2) + 0xff000000)
+#define DI_MC_REG4_X ((0x1728 << 2) + 0xff000000)
+#define DI_MC_REG4_Y ((0x1729 << 2) + 0xff000000)
+#define DI_MC_32LVL0 ((0x172a << 2) + 0xff000000)
+//bit 31:24, mc_reg2_32lvl
+//bit 23:16, mc_reg1_32lvl
+//bit 15:8, mc_reg0_32lvl
+//bit 7:0, field_32lvl
+#define DI_MC_32LVL1 ((0x172b << 2) + 0xff000000)
+//bit 15:8, mc_reg3_32lvl
+//bit 7:0, mc_reg4_32lvl
+#define DI_MC_22LVL0 ((0x172c << 2) + 0xff000000)
+//bit 31:16, mc_reg0_22lvl
+//bit 15:0, field_22lvl
+#define DI_MC_22LVL1 ((0x172d << 2) + 0xff000000)
+//bit 31:16, mc_reg2_22lvl
+//bit 15:0, mc_reg1_22lvl
+#define DI_MC_22LVL2 ((0x172e << 2) + 0xff000000)
+//bit 31:16, mc_reg4_22lvl
+//bit 15:0, mc_reg3_22lvl
+#define DI_MC_CTRL ((0x172f << 2) + 0xff000000)
+//bit 4, mc_reg4_en
+//bit 3, mc_reg3_en
+//bit 2, mc_reg2_en
+//bit 1, mc_reg1_en
+//bit 0, mc_reg0_en
+#define DI_INTR_CTRL ((0x1730 << 2) + 0xff000000)
+#define DI_INFO_ADDR ((0x1731 << 2) + 0xff000000)
+#define DI_INFO_DATA ((0x1732 << 2) + 0xff000000)
+#define DI_PRE_HOLD ((0x1733 << 2) + 0xff000000)
+//// DET 3D REG DEFINE BEGIN ////
+//// 8'h34~8'h3f
+// `define DET3D_MOTN_CFG 8'h34
+// //Bit 16, reg_det3d_intr_en Det3d interrupt enable
+// //Bit 9:8, reg_Det3D_Motion_Mode U2 Different mode for Motion Calculation of Luma and Chroma:
+// // 0: MotY, 1: (2*MotY + (MotU + MotV))/4; 2: Max(MotY, MotU,MotV); 3:Max(MotY, (MotU+MotV)/2)
+// //Bit 7:4, reg_Det3D_Motion_Core_Rate U4 K Rate to Edge (HV) details for coring of Motion Calculations, normalized to 32
+// //Bit 3:0, reg_Det3D_Motion_Core_Thrd U4 2X: static coring value for Motion Detection.
+//
+// `define DET3D_CB_CFG 8'h35
+// //Bit 7:4, reg_Det3D_ChessBd_NHV_ofst U4, Noise immune offset for NON-Horizotnal or vertical combing detection.
+// //Bit 3:0, reg_Det3D_ChessBd_HV_ofst U4, Noise immune offset for Horizotnal or vertical combing detection.
+//
+// `define DET3D_SPLT_CFG 8'h36
+// //Bit 7:4, reg_Det3D_SplitValid_ratio U4, Ratio between max_value and the avg_value of the edge mapping for split line valid detection.
+// // The smaller of this value, the easier of the split line detected.
+// //Bit 3:0, reg_Det3D_AvgIdx_ratio U4, Ratio to the avg_value of the edge mapping for split line position estimation.
+// // The smaller of this value, the more samples will be added to the estimation.
+//
+// `define DET3D_HV_MUTE 8'h37
+// //Bit 23:20, reg_Det3D_Edge_Ver_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Top and Bottom border part.
+// //Bit 19:16, reg_Det3D_Edge_Hor_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Left and right border part.
+// //Bit 15:12, reg_Det3D_ChessBd_Ver_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part
+// //Bit 11:8, reg_Det3D_ChessBd_Hor_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part
+// //Bit 7:4, reg_Det3D_STA8X8_Ver_Mute U4 1X: Vertical pixels to be mute from 8x8 statistics calculation in each block.
+// //Bit 3:0, reg_Det3D_STA8X8_Hor_Mute U4 1X: Horizontal pixels to be mute from 8x8 statistics calculation in each block.
+//
+// `define DET3D_MAT_STA_P1M1 8'h38
+// //Bit 31:24, reg_Det3D_STA8X8_P1_K0_R8 U8 SAD to SAI ratio to decide P1, normalized to 256 (0.8)
+// //Bit 23:16, reg_Det3D_STA8X8_P1_K1_R7 U8 SAD to ENG ratio to decide P1, normalized to 128 (0.5)
+// //Bit 15:8, reg_Det3D_STA8X8_M1_K0_R6 U8 SAD to SAI ratio to decide M1, normalized to 64 (1.1)
+// //Bit 7:0, reg_Det3D_STA8X8_M1_K1_R6 U8 SAD to ENG ratio to decide M1, normalized to 64 (0.8)
+//
+// `define DET3D_MAT_STA_P1TH 8'h39
+// //Bit 23:16, reg_Det3D_STAYUV_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (100)
+// //Bit 15:8, reg_Det3D_STAEDG_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (80)
+// //Bit 7:0, reg_Det3D_STAMOT_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (48)
+//
+// `define DET3D_MAT_STA_M1TH 8'h3a
+// //Bit 23:16, reg_Det3D_STAYUV_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (100)
+// //Bit 15:8, reg_Det3D_STAEDG_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (80)
+// //Bit 7:0, reg_Det3D_STAMOT_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (64)
+//
+// `define DET3D_MAT_STA_RSFT 8'h3b
+// //Bit 5:4, reg_Det3D_STAYUV_RSHFT U2 YUV statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
+// // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
+// //Bit 3:2, reg_Det3D_STAEDG_RSHFT U2 Horizontal and Vertical Edge Statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
+// // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
+// //Bit 1:0, reg_Det3D_STAMOT_RSHFT U2 Motion SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
+// // 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
+//
+// `define DET3D_MAT_SYMTC_TH 8'h3c
+// //Bit 31:24, reg_Det3D_STALUM_symtc_Th U8 threshold to decide if the Luma statistics is TB or LR symmetric.
+// //Bit 23:16, reg_Det3D_STACHR_symtc_Th U8 threshold to decide if the Chroma (UV) statistics is TB or LR symmetric.
+// //Bit 15:8, reg_Det3D_STAEDG_symtc_Th U8 threshold to decide if the Horizontal and Vertical Edge statistics is TB or LR symmetric.
+// //Bit 7:0, reg_Det3D_STAMOT_symtc_Th U8 threshold to decide if the Motion statistics is TB or LR symmetric.
+//
+// `define DET3D_RO_DET_CB_HOR 8'h3d
+// //Bit 31:16, RO_Det3D_ChessBd_NHor_value U16 X64: number of Pixels of Horizontally Surely NOT matching Chessboard pattern.
+// //Bit 15:0, RO_Det3D_ChessBd_Hor_value U16 X64: number of Pixels of Horizontally Surely matching Chessboard pattern.
+//
+// `define DET3D_RO_DET_CB_VER 8'h3e
+// //Bit 31:16, RO_Det3D_ChessBd_NVer_value U16 X64: number of Pixels of Vertically Surely NOT matching Chessboard pattern.
+// //Bit 15:0, RO_Det3D_ChessBd_Ver_value U16 X64: number of Pixels of Vertically Surely matching Chessboard pattern.
+//
+// `define DET3D_RO_SPLT_HT 8'h3f
+// //Bit 24, RO_Det3D_Split_HT_valid U1 horizontal LR split border detected valid signal for top half picture
+// //Bit 20:16, RO_Det3D_Split_HT_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+// //Bit 9:0, RO_Det3D_Split_HT_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+//
+// //// DET 3D REG DEFINE END ////
+#define DI_MTN_1_CTRL1 ((0x1740 << 2) + 0xff000000)
+//bit 31, mtn_1_en
+//bit 30, mtn_init
+//bit 29, di2nr_txt_en
+//bit 28, reserved
+//bit 27:24, mtn_def
+//bit 23:16, mtn_adp_yc
+//bit 15:8, mtn_adp_2c
+//bit 7:0, mtn_adp_2y
+#define DI_MTN_1_CTRL2 ((0x1741 << 2) + 0xff000000)
+//bit 31:24, mtn_ykinter
+//bit 23:16, mtn_ckinter
+//bit 15:8, mtn_ykintra
+//bit 7:0, mtn_ckintra
+#define DI_MTN_1_CTRL3 ((0x1742 << 2) + 0xff000000)
+//bit 31:24, mtn_tyrate
+//bit 23:16, mtn_tcrate
+//bit 15: 8, mtn_mxcmby
+//bit 7: 0, mtn_mxcmbc
+#define DI_MTN_1_CTRL4 ((0x1743 << 2) + 0xff000000)
+//bit 31:24, mtn_tcorey
+//bit 23:16, mtn_tcorec
+//bit 15: 8, mtn_minth
+//bit 7: 0, mtn_maxth
+#define DI_MTN_1_CTRL5 ((0x1744 << 2) + 0xff000000)
+//bit 31:28, mtn_m1b_extnd
+//bit 27:24, mtn_m1b_errod
+//bit 21:20, mtn_mot_txt_mode
+//bit 19:18, mtn_replace_cbyy
+//bit 17:16, mtn_replace_ybyc
+//bit 15: 8, mtn_core_ykinter
+//bit 7: 0, mtn_core_ckinter
+//// NR2 REG DEFINE BEGIN////
+#define NR2_MET_NM_CTRL ((0x1745 << 2) + 0xff000000)
+//Bit 28, reg_NM_reset Reset to the status of the Loop filter.
+//Bit 27:24, reg_NM_calc_length Length mode of the Noise measurement sample number for statistics.
+// 0: 256 samples; 1: 512 samples; 2: 1024 samples; ¡X: 2^(8+x) samples
+//Bit 23:20, reg_NM_inc_step Loop filter input gain increase step.
+//Bit 19:16, reg_NM_dec_step Loop filter input gain decrease step.
+//Bit 15:8, reg_NM_YHPmot_thrd Luma channel HP portion motion for condition of pixels included in Luma Noise measurement.
+//Bit 7:0, reg_NM_CHPmot_thrd Chroma channel HP portion motion for condition of pixels included in Chroma Noise measurement.
+#define NR2_MET_NM_YCTRL ((0x1746 << 2) + 0xff000000)
+//Bit 31:28, reg_NM_YPLL_target Target rate of NM_Ynoise_thrd to mean of the Luma Noise
+//Bit 27:24, reg_NM_YLPmot_thrd Luma channel LP portion motion for condition of pixels included in Luma Noise measurement.
+//Bit 23:16, reg_NM_YHPmot_thrd_min Minimum threshold for Luma channel HP portion motion to decide whether the pixel will be included in Luma noise measurement.
+//Bit 15:8, reg_NM_YHPmot_thrd_max Maximum threshold for Luma channel HP portion motion to decide whether the pixel will be included in Luma noise measurement.
+//Bit 7:0, reg_NM_Ylock_rate Rate to decide whether the Luma noise measurement is lock or not.
+#define NR2_MET_NM_CCTRL ((0x1747 << 2) + 0xff000000)
+//Bit 31:28, reg_NM_CPLL_target Target rate of NM_Cnoise_thrd to mean of the Chroma Noise
+//Bit 27:24, reg_NM_CLPmot_thrd Chroma channel LP portion motion for condition of pixels included in Chroma Noise measurement.
+//Bit 23:16, reg_NM_CHPmot_thrd_min Minimum threshold for Chroma channel HP portion motion to decide whether the pixel will be included in Chroma noise measurement.
+//Bit 15:8, reg_NM_CHPmot_thrd_max Maximum threshold for Chroma channel HP portion motion to decide whether the pixel will be included in Chroma noise measurement.
+//Bit 7:0, reg_NM_Clock_rate Rate to decide whether the Chroma noise measurement is lock or not;
+#define NR2_MET_NM_TNR ((0x1748 << 2) + 0xff000000)
+//Bit 25, ro_NM_TNR_Ylock Read-only register to tell ifLuma channel noise measurement is locked or not.
+//Bit 24, ro_NM_TNR_Clock Read-only register to tell if Chroma channel noise measurement is locked or not.
+//Bit 23:12, ro_NM_TNR_Ylevel Read-only register to give Luma channel noise level. It was 16x of pixel difference in 8 bits of YHPmot.
+//Bit 11:0, ro_NM_TNR_Clevel Read-only register to give Chroma channel noise level. It was 16x of pixel difference in 8 bits of CHPmot.
+#define NR2_MET_NMFRM_TNR_YLEV ((0x1749 << 2) + 0xff000000)
+//Bit 28:0, ro_NMFrm_TNR_Ylevel Frame based Read-only register to give Luma channel noise level within one frame/field.
+#define NR2_MET_NMFRM_TNR_YCNT ((0x174a << 2) + 0xff000000)
+//Bit 23:0, ro_NMFrm_TNR_Ycount Number ofLuma channel pixels included in Frame/Field based noise level measurement.
+#define NR2_MET_NMFRM_TNR_CLEV ((0x174b << 2) + 0xff000000)
+//Bit 28:0, ro_NMFrm_TNR_Clevel Frame based Read-only register to give Chroma channel noise level within one frame/field.
+#define NR2_MET_NMFRM_TNR_CCNT ((0x174c << 2) + 0xff000000)
+//Bit 23:0, ro_NMFrm_TNR_Ccount Number of Chroma channel pixels included in Frame/Field based noise level measurement.
+#define NR2_3DEN_MODE ((0x174d << 2) + 0xff000000)
+//Bit 6:4, Blend_3dnr_en_r
+//Bit 2:0, Blend_3dnr_en_l
+// `define NR2_IIR_CTRL 8'h4e
+// //Bit 15:14, reg_LP_IIR_8bit_mode LP IIR membitwidth mode:0: 10bits will be store in memory;1: 9bits will be store in memory;
+// // 2: 8bits will be store in memory;3: 7bits will be store in memory;
+// //Bit 13:12, reg_LP_IIR_mute_mode Mode for the LP IIR mute,
+// //Bit 11:8, reg_LP_IIR_mute_thrd Threshold of LP IIR mute to avoid ghost:
+// //Bit 7:6, reg_HP_IIR_8bit_mode IIR membitwidth mode:0: 10bits will be store in memory;1: 9bits will be store in memory;
+// // 2: 8bits will be store in memory;3: 7bits will be store in memory;
+// //Bit 5:4, reg_HP_IIR_mute_mode Mode for theLP IIR mute
+// //Bit 3:0, reg_HP_IIR_mute_thrd Threshold of HP IIR mute to avoid ghost
+// //
+#define NR2_SW_EN ((0x174f << 2) + 0xff000000)
+//Bit 17:8, Clk_gate_ctrl
+//Bit 7, Cfr_enable
+//Bit 5, Det3d_en
+//Bit 4, Nr2_proc_en
+//Bit 0, Nr2_sw_en
+#define NR2_FRM_SIZE ((0x1750 << 2) + 0xff000000)
+//Bit 27:16, Frm_heigh Frame/field height
+//Bit 11: 0, Frm_width Frame/field width
+// `define NR2_SNR_SAD_CFG 8'h51
+// //Bit 12, reg_MATNR_SNR_SAD_CenRPL U1, Enable signal for Current pixel position SAD to be replaced by SAD_min.0: do not replace Current pixel position SAD by SAD_min;1: do replacements
+// //Bit 11:8, reg_MATNR_SNR_SAD_coring Coring value of the intra-frame SAD. sum = (sum - reg_MATNR_SNR_SAD_coring);sum = (sum<0) ? 0: (sum>255)? 255: sum;
+// //Bit 6:5, reg_MATNR_SNR_SAD_WinMod Unsigned, Intra-frame SAD matching window mode:0: 1x1; 1: [1 1 1] 2: [1 2 1]; 3: [1 2 2 2 1];
+// //Bit 4:0, Sad_coef_num Sad coeffient
+//
+// `define NR2_MATNR_SNR_OS 8'h52
+// //Bit 7:4, reg_MATNR_SNR_COS SNR Filter overshoot control margin for UV channel (X2 to u10 scale)
+// //Bit 3:0, reg_MATNR_SNR_YOS SNR Filter overshoot control margin for luma channel (X2 to u10 scale)
+//
+// `define NR2_MATNR_SNR_NRM_CFG 8'h53
+// //Bit 23:16, reg_MATNR_SNR_NRM_ofst Edge based SNR boosting normalization offset to SAD_max ;
+// //Bit 15:8, reg_MATNR_SNR_NRM_max Edge based SNR boosting normalization Max value
+// //Bit 7:0, reg_MATNR_SNR_NRM_min Edge based SNR boosting normalization Min value
+//
+// `define NR2_MATNR_SNR_NRM_GAIN 8'h54
+// //Bit 15:8, reg_MATNR_SNR_NRM_Cgain Edge based SNR boosting normalization Gain for Chrm channel (norm 32 as 1)
+// //Bit 7:0, reg_MATNR_SNR_NRM_Ygain Edge based SNR boosting normalization Gain for Luma channel (norm 32 as 1)
+//
+// `define NR2_MATNR_SNR_LPF_CFG 8'h55
+// //Bit 23:16,reg_MATNR_SNRLPF_SADmaxTH U8, Threshold to SADmax to use TNRLPF to replace SNRLPF. i.e.if (SAD_max<reg_MATNR_SNRLPF_SADmaxTH) SNRLPF_yuv[k] = TNRLPF_yuv[k];
+// //Bit 13:11,reg_MATNR_SNRLPF_Cmode LPF based SNR filtering mode on CHRM channel:
+// // 0: gradient LPF [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8; 3: gradient LPF [5 4 4 3]/16;
+// // 4: TNRLPF; 5 : CurLPF3x3_yuv[]; 6: CurLPF3o3_yuv[] 7: CurLPF3x5_yuv[]
+// //Bit 10:8, reg_MATNR_SNRLPF_Ymode LPF based SNR filtering mode on LUMA channel:
+// // 0: gradient LPF //Bit [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8;3: gradient LPF [5 4 4 3]/16;
+// // 4: TNRLPF; 5 : CurLPF3x3_yuv[]; 6: CurLPF3o3_yuv[] 7: CurLPF3x5_yuv[]
+// //Bit 7:4, reg_MATNR_SNRLPF_SADmin3TH Offset threshold to SAD_min to Discard SAD_min3 corresponding pixel in LPF SNR filtering. (X8 to u8 scale)
+// //Bit 3:0, reg_MATNR_SNRLPF_SADmin2TH Offset threshold to SAD_min to Discard SAD_min2 corresponding pixel in LPF SNR filtering. (X8 to u8 scale)
+//
+// `define NR2_MATNR_SNR_USF_GAIN 8'h56
+// //Bit 15:8, reg_MATNR_SNR_USF_Cgain Un-sharp (HP) compensate back Chrm portion gain, (norm 64 as 1)
+// //Bit 7:0, reg_MATNR_SNR_USF_Ygain Un-sharp (HP) compensate back Luma portion gain, (norm 64 as 1)
+//
+// `define NR2_MATNR_SNR_EDGE2B 8'h57
+// //Bit 15:8, reg_MATNR_SNR_Edge2Beta_ofst U8, Offset for Beta based on Edge.
+// //Bit 7:0, reg_MATNR_SNR_Edge2Beta_gain U8. Gain to SAD_min for Beta based on Edge. (norm 16 as 1)
+//
+// `define NR2_MATNR_BETA_EGAIN 8'h58
+// //Bit 15:8, reg_MATNR_CBeta_Egain U8, Gain to Edge based Beta for Chrm channel. (normalized to 32 as 1)
+// //Bit 7:0, reg_MATNR_YBeta_Egain U8, Gain to Edge based Beta for Luma channel. (normalized to 32 as 1)
+//
+// `define NR2_MATNR_BETA_BRT 8'h59
+// //Bit 31:28, reg_MATNR_beta_BRT_limt_hi U4, Beta adjustment based on Brightness high side Limit. (X16 to u8 scale)
+// //Bit 27:24, reg_MATNR_beta_BRT_slop_hi U4, Beta adjustment based on Brightness high side slope. Normalized to 16 as 1
+// //Bit 23:16, reg_MATNR_beta_BRT_thrd_hi U8, Beta adjustment based on Brightness high threshold.(u8 scale)
+// //Bit 15:12, reg_MATNR_beta_BRT_limt_lo U4, Beta adjustment based on Brightness low side Limit. (X16 to u8 scale)
+// //Bit 11:8, reg_MATNR_beta_BRT_slop_lo U4, Beta adjustment based on Brightness low side slope. Normalized to 16 as 1
+// //Bit 7:0, reg_MATNR_beta_BRT_thrd_lo U8, Beta adjustment based on Brightness low threshold.(u8 scale)
+// `define NR2_MATNR_XBETA_CFG 8'h5a
+// //Bit 19:18, reg_MATNR_CBeta_use_mode U2, Beta options (mux) from beta_motion and beta_edge for Chrm channel;
+// //Bit 17:16, reg_MATNR_YBeta_use_mode U2, Beta options (mux) from beta_motion and beta_edge for Luma channel;
+// //Bit 15: 8, reg_MATNR_CBeta_Ofst U8, Offset to Beta for Chrm channel.(after beta_edge and beta_motion mux)
+// //Bit 7: 0, reg_MATNR_YBeta_Ofst U8, Offset to Beta for Luma channel.(after beta_edge and beta_motion mux)
+// `define NR2_MATNR_YBETA_SCL 8'h5b
+// //Bit 31:24, reg_MATNR_YBeta_scale_min U8, Final step Beta scale low limit for Luma channel;
+// //Bit 23:16, reg_MATNR_YBeta_scale_max U8, Final step Beta scale high limit for Luma channe;
+// //Bit 15: 8, reg_MATNR_YBeta_scale_gain U8, Final step Beta scale Gain for Luma channel (normalized 32 to 1);
+// //Bit 7 : 0, reg_MATNR_YBeta_scale_ofst S8, Final step Beta scale offset for Luma channel ;
+// `define NR2_MATNR_CBETA_SCL 8'h5c
+// //Bit 31:24, reg_MATNR_CBeta_scale_min Final step Beta scale low limit for Chrm channel.Similar to Y
+// //Bit 23:16, reg_MATNR_CBeta_scale_max U8, Final step Beta scale high limit for Chrm channel.Similar to Y
+// //Bit 15: 8, reg_MATNR_CBeta_scale_gain U8, Final step Beta scale Gain for Chrm channel Similar to Y
+// //Bit 7: 0, reg_MATNR_CBeta_scale_ofst S8, Final step Beta scale offset for Chrm channel Similar to Y
+// `define NR2_SNR_MASK 8'h5d
+// //Bit 20:0, SAD_MSK Valid signal in the 3x7 SAD surface
+// `define NR2_SAD2NORM_LUT0 8'h5e
+// //Bit 31:24, reg_MATNR_SAD2Norm_LUT_3 SAD convert normal LUT node 3
+// //Bit 23:16, reg_MATNR_SAD2Norm_LUT_2 SAD convert normal LUT node 2
+// //Bit 15: 8, reg_MATNR_SAD2Norm_LUT_1 SAD convert normal LUT node 1
+// //Bit 7: 0, reg_MATNR_SAD2Norm_LUT_0 SAD convert normal LUT node 0
+// `define NR2_SAD2NORM_LUT1 8'h5f
+// //Bit 31:24, reg_MATNR_SAD2Norm_LUT_7 SAD convert normal LUT node 7
+// //Bit 23:16, reg_MATNR_SAD2Norm_LUT_6 SAD convert normal LUT node 6
+// //Bit 15: 8, reg_MATNR_SAD2Norm_LUT_5 SAD convert normal LUT node 5
+// //Bit 7: 0, reg_MATNR_SAD2Norm_LUT_4 SAD convert normal LUT node 4
+// `define NR2_SAD2NORM_LUT2 8'h60
+// //Bit 31:24, reg_MATNR_SAD2Norm_LUT_11 SAD convert normal LUT node 11
+// //Bit 23:16, reg_MATNR_SAD2Norm_LUT_10 SAD convert normal LUT node 10
+// //Bit 15: 8, reg_MATNR_SAD2Norm_LUT_9 SAD convert normal LUT node 9
+// //Bit 7: 0, reg_MATNR_SAD2Norm_LUT_8 SAD convert normal LUT node 8
+// `define NR2_SAD2NORM_LUT3 8'h61
+// //Bit 31:24, reg_MATNR_SAD2Norm_LUT_15 SAD convert normal LUT node 15
+// //Bit 23:16, reg_MATNR_SAD2Norm_LUT_14 SAD convert normal LUT node 14
+// //Bit 15:8, reg_MATNR_SAD2Norm_LUT_13 SAD convert normal LUT node 13
+// //Bit 7:0, reg_MATNR_SAD2Norm_LUT_12 SAD convert normal LUT node 12
+// `define NR2_EDGE2BETA_LUT0 8'h62
+// //Bit 31:24, reg_MATNR_Edge2Beta_LUT_3 Edge convert beta LUT node 3
+// //Bit 23:16, reg_MATNR_Edge2Beta_LUT_2 Edge convert beta LUT node 2
+// //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_1 Edge convert beta LUT node 1
+// //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_0 Edge convert beta LUT node 0
+// `define NR2_EDGE2BETA_LUT1 8'h63
+// //Bit 31:24, reg_MATNR_Edge2Beta_LUT_7 Edge convert beta LUT node 7
+// //Bit 23:16, reg_MATNR_Edge2Beta_LUT_6 Edge convert beta LUT node 6
+// //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_5 Edge convert beta LUT node 5
+// //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_4 Edge convert beta LUT node 4
+// `define NR2_EDGE2BETA_LUT2 8'h64
+// //Bit 31:24, reg_MATNR_Edge2Beta_LUT_11 Edge convert beta LUT node 11
+// //Bit 23:16, reg_MATNR_Edge2Beta_LUT_10 Edge convert beta LUT node 10
+// //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_9 Edge convert beta LUT node 9
+// //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_8 Edge convert beta LUT node 8
+// `define NR2_EDGE2BETA_LUT3 8'h65
+// //Bit 31:24, reg_MATNR_Edge2Beta_LUT_15 Edge convert beta LUT node 15
+// //Bit 23:16, reg_MATNR_Edge2Beta_LUT_14 Edge convert beta LUT node 14
+// //Bit 15: 8, reg_MATNR_Edge2Beta_LUT_13 Edge convert beta LUT node 13
+// //Bit 7: 0, reg_MATNR_Edge2Beta_LUT_12 Edge convert beta LUT node 12
+// `define NR2_MOTION2BETA_LUT0 8'h66
+// //Bit 31:24, reg_MATNR_Mot2Beta_LUT_3 Motion convert beta LUT node 3
+// //Bit 23:16, reg_MATNR_Mot2Beta_LUT_2 Motion convert beta LUT node 2
+// //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_1 Motion convert beta LUT node 1
+// //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_0 Motion convert beta LUT node 0
+// `define NR2_MOTION2BETA_LUT1 8'h67
+// //Bit 31:24, reg_MATNR_Mot2Beta_LUT_7 Motion convert beta LUT node 7
+// //Bit 23:16, reg_MATNR_Mot2Beta_LUT_6 Motion convert beta LUT node 6
+// //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_5 Motion convert beta LUT node 5
+// //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_4 Motion convert beta LUT node 4
+// `define NR2_MOTION2BETA_LUT2 8'h68
+// //Bit 31:24, reg_MATNR_Mot2Beta_LUT_11 Motion convert beta LUT node 11
+// //Bit 23:16, reg_MATNR_Mot2Beta_LUT_10 Motion convert beta LUT node 10
+// //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_9 Motion convert beta LUT node 9
+// //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_8 Motion convert beta LUT node 8
+// `define NR2_MOTION2BETA_LUT3 8'h69
+// //Bit 31:24, reg_MATNR_Mot2Beta_LUT_15 Motion convert beta LUT node 15
+// //Bit 23:16, reg_MATNR_Mot2Beta_LUT_14 Motion convert beta LUT node 14
+// //Bit 15: 8, reg_MATNR_Mot2Beta_LUT_13 Motion convert beta LUT node 13
+// //Bit 7: 0, reg_MATNR_Mot2Beta_LUT_12 Motion convert beta LUT node 12
+// `define NR2_MATNR_MTN_CRTL 8'h6a
+// //Bit 25:24, reg_MATNR_Vmtn_use_mode Motion_yuvV channel motion selection mode:0: Vmot;1:Ymot/2 + (Umot+Vmot)/4; 2:Ymot/2 + max(Umot,Vmot)/2; 3: max(Ymot,Umot, Vmot)
+// //Bit 21:20, reg_MATNR_Umtn_use_mode Motion_yuvU channel motion selection mode:0:Umot;1:Ymot/2 + (Umot+Vmot)/4; 2:Ymot/2 + max(Umot,Vmot)/2; 3: max(Ymot,Umot, Vmot)
+// //Bit 17:16, reg_MATNR_Ymtn_use_mode Motion_yuvLuma channel motion selection mode:0: Ymot, 1: Ymot/2 + (Umot+Vmot)/4; 2: Ymot/2 + max(Umot,Vmot)/2; 3: max(Ymot,Umot, Vmot)
+// //Bit 13:12, reg_MATNR_mtn_txt_mode Texture detection mode for adaptive coring of HP motion
+// //Bit 9: 8, reg_MATNR_mtn_cor_mode Coring selection mode based on texture detection;
+// //Bit 6: 4, reg_MATNR_mtn_hpf_mode video mode of current and previous frame/field for MotHPF_yuv[k] calculation:
+// //Bit 2: 0, reg_MATNR_mtn_lpf_mode LPF video mode of current and previous frame/field for MotLPF_yuv[k] calculation:
+// `define NR2_MATNR_MTN_CRTL2 8'h6b
+// //Bit 18:16, reg_MATNR_iir_BS_Ymode IIR TNR filter Band split filter mode for Luma LPF result generation (Cur and Prev);
+// //Bit 15: 8, reg_MATNR_mtnb_alpLP_Cgain Scale of motion_brthp_uv to motion_brtlp_uv, normalized to 32 as 1
+// //Bit 7: 0, reg_MATNR_mtnb_alpLP_Ygain Scale of motion_brthp_y to motion_brtlp_y, normalized to 32 as 1
+// `define NR2_MATNR_MTN_COR 8'h6c
+// //Bit 15:12, reg_MATNR_mtn_cor_Cofst Coring Offset for Chroma Motion.
+// //Bit 11: 8, reg_MATNR_mtn_cor_Cgain Gain to texture based coring for Chroma Motion. Normalized to 16 as 1
+// //Bit 7: 4, reg_MATNR_mtn_cor_Yofst Coring Offset for Luma Motion.
+// //Bit 3: 0, reg_MATNR_mtn_cor_Ygain Gain to texture based coring for Luma Motion. Normalized to 16 as 1
+// `define NR2_MATNR_MTN_GAIN 8'h6d
+// //Bit 31:24, reg_MATNR_mtn_hp_Cgain Gain to MotHPF_yuv[k] Chrm channel for motion calculation, normalized to 64 as 1
+// //Bit 23:16, reg_MATNR_mtn_hp_Ygain Gain to MotHPF_yuv[k] Luma channel for motion calculation, normalized to 64 as 1
+// //Bit 15: 8, reg_MATNR_mtn_lp_Cgain Gain to MotLPF_yuv[k] Chrm channel for motion calculation, normalized to 32 as 1
+// //Bit 7: 0, reg_MATNR_mtn_lp_Ygain Gain to MotLPF_yuv[k] Luma channel for motion calculation, normalized to 32 as 1
+// `define NR2_MATNR_DEGHOST 8'h6e
+// //Bit 8, reg_MATNR_DeGhost_En Enable signal for DeGhost function:0: disable; 1: enable
+// //Bit 7:4, reg_MATNR_DeGhost_COS DeGhost Overshoot margin for UV channel, (X2 to u10 scale)
+// //Bit 3:0, reg_MATNR_DeGhost_YOS DeGhost Overshoot margin for Luma channel, (X2 to u10 scale)
+//
+// `define NR2_MATNR_ALPHALP_LUT0 8'h6f
+// //Bit 31:24, reg_MATNR_AlphaLP_LUT_3 Matnr low-pass filter alpha LUT node 3
+// //Bit 23:16, reg_MATNR_AlphaLP_LUT_2 Matnr low-pass filter alpha LUT node 2
+// //Bit 15: 8, reg_MATNR_AlphaLP_LUT_1 Matnr low-pass filter alpha LUT node 1
+// //Bit 7: 0, reg_MATNR_AlphaLP_LUT_0 Matnr low-pass filter alpha LUT node 0
+// `define NR2_MATNR_ALPHALP_LUT1 8'h70
+// //Bit 31:24, reg_MATNR_AlphaLP_LUT_7 Matnr low-pass filter alpha LUT node 7
+// //Bit 23:16, reg_MATNR_AlphaLP_LUT_6 Matnr low-pass filter alpha LUT node 6
+// //Bit 15: 8, reg_MATNR_AlphaLP_LUT_5 Matnr low-pass filter alpha LUT node 5
+// //Bit 7: 0, reg_MATNR_AlphaLP_LUT_4 Matnr low-pass filter alpha LUT node 4
+// `define NR2_MATNR_ALPHALP_LUT2 8'h71
+// //Bit 31:24, reg_MATNR_AlphaLP_LUT_11 Matnr low-pass filter alpha LUT node 11
+// //Bit 23:16, reg_MATNR_AlphaLP_LUT_10 Matnr low-pass filter alpha LUT node 10
+// //Bit 15: 8, reg_MATNR_AlphaLP_LUT_9 Matnr low-pass filter alpha LUT node 9
+// //Bit 7: 0, reg_MATNR_AlphaLP_LUT_8 Matnr low-pass filter alpha LUT node 8
+// `define NR2_MATNR_ALPHALP_LUT3 8'h72
+// //Bit 31:24, reg_MATNR_AlphaLP_LUT_15 Matnr low-pass filter alpha LUT node 15
+// //Bit 23:16, reg_MATNR_AlphaLP_LUT_14 Matnr low-pass filter alpha LUT node 14
+// //Bit 15: 8, reg_MATNR_AlphaLP_LUT_13 Matnr low-pass filter alpha LUT node 13
+// //Bit 7: 0, reg_MATNR_AlphaLP_LUT_12 Matnr low-pass filter alpha LUT node 12
+// `define NR2_MATNR_ALPHAHP_LUT0 8'h73
+// //Bit 31:24, reg_MATNR_AlphaHP_LUT_3 Matnr high-pass filter alpha LUT node 3
+// //Bit 23:16, reg_MATNR_AlphaHP_LUT_2 Matnr high-pass filter alpha LUT node 2
+// //Bit 15: 8, reg_MATNR_AlphaHP_LUT_1 Matnr high-pass filter alpha LUT node 1
+// //Bit 7: 0, reg_MATNR_AlphaHP_LUT_0 Matnr high-pass filter alpha LUT node 0
+// `define NR2_MATNR_ALPHAHP_LUT1 8'h74
+// //Bit 31:24, reg_MATNR_AlphaHP_LUT_7 Matnr high-pass filter alpha LUT node 7
+// //Bit 23:16, reg_MATNR_AlphaHP_LUT_6 Matnr high-pass filter alpha LUT node 6
+// //Bit 15: 8, reg_MATNR_AlphaHP_LUT_5 Matnr high-pass filter alpha LUT node 5
+// //Bit 7: 0, reg_MATNR_AlphaHP_LUT_4 Matnr high-pass filter alpha LUT node 4
+// `define NR2_MATNR_ALPHAHP_LUT2 8'h75
+// //Bit 31:24, reg_MATNR_AlphaHP_LUT_11 Matnr high-pass filter alpha LUT node 11
+// //Bit 23:16, reg_MATNR_AlphaHP_LUT_10 Matnr high-pass filter alpha LUT node 10
+// //Bit 15: 8, reg_MATNR_AlphaHP_LUT_9 Matnr high-pass filter alpha LUT node 9
+// //Bit 7: 0, reg_MATNR_AlphaHP_LUT_8 Matnr high-pass filter alpha LUT node 8
+// `define NR2_MATNR_ALPHAHP_LUT3 8'h76
+// //Bit 31:24, reg_MATNR_AlphaHP_LUT_15 Matnr high-pass filter alpha LUT node 15
+// //Bit 23:16, reg_MATNR_AlphaHP_LUT_14 Matnr high-pass filter alpha LUT node 14
+// //Bit 15: 8, reg_MATNR_AlphaHP_LUT_13 Matnr high-pass filter alpha LUT node 13
+// //Bit 7: 0, reg_MATNR_AlphaHP_LUT_12 Matnr high-pass filter alpha LUT node 12
+//
+// `define NR2_MATNR_MTNB_BRT 8'h77
+// //Bit 31:28, reg_MATNR_mtnb_BRT_limt_hi Motion adjustment based on Brightness high side Limit. (X16 to u8 scale)
+// //Bit 27:24, reg_MATNR_mtnb_BRT_slop_hi Motion adjustment based on Brightness high side slope. Normalized to 16 as 1
+// //Bit 23:16, reg_MATNR_mtnb_BRT_thrd_hi Motion adjustment based on Brightness high threshold.(u8 scale)
+// //Bit 15:12, reg_MATNR_mtnb_BRT_limt_lo Motion adjustment based on Brightness low side Limit. (X16 to u8 scale)
+// //Bit 11: 8, reg_MATNR_mtnb_BRT_slop_lo Motion adjustment based on Brightness low side slope. Normalized to 16 as 1
+// //Bit 7: 0, reg_MATNR_mtnb_BRT_thrd_lo Motion adjustment based on Brightness low threshold.(u8 scale)
+// 0x51 - 0x69 | 0x4e | 0x6a - 0x77
+//
+// Reading file: vpu_nr2_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//========== nr2_snr_regs register begin ==========//
+#define NR2_SNR_SAD_CFG ((0x1751 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12 reg_matnr_snr_sad_cenrpl // unsigned , default = 1
+//Bit 11: 8 reg_matnr_snr_sad_coring // unsigned , default = 3
+//Bit 7 reserved
+//Bit 6: 5 reg_matnr_snr_sad_winmod // unsigned , default = 1 0: 1x1; 1: [1 1 1] 2: [1 2 1]; 3: [1 2 2 2 1];
+//Bit 4: 0 sad_coef_num // unsigned , default = 1 0: 1x1; 1: [1 1 1] 2: [1 2 1]; 3: [1 2 2 2 1];
+#define NR2_MATNR_SNR_OS ((0x1752 << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7: 4 reg_matnr_snr_cos // unsigned , default = 8
+//Bit 3: 0 reg_matnr_snr_yos // unsigned , default = 13
+#define NR2_MATNR_SNR_NRM_CFG ((0x1753 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_matnr_snr_nrm_ofst // signed , default = 64
+//Bit 15: 8 reg_matnr_snr_nrm_max // unsigned , default = 255
+//Bit 7: 0 reg_matnr_snr_nrm_min // unsigned , default = 0
+#define NR2_MATNR_SNR_NRM_GAIN ((0x1754 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_matnr_snr_nrm_cgain // unsigned , default = 0 norm 32
+//Bit 7: 0 reg_matnr_snr_nrm_ygain // unsigned , default = 32 norm 32
+#define NR2_MATNR_SNR_LPF_CFG ((0x1755 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_matnr_snrlpf_sadmaxth // unsigned , default = 12
+//Bit 15:14 reserved
+//Bit 13:11 reg_matnr_snrlpf_cmode // unsigned , default = 2 0: gradient LPF [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8; 3: gradient LPF [5 5 4 3]/16;
+//Bit 10: 8 reg_matnr_snrlpf_ymode // unsigned , default = 2 0: gradient LPF [1 1]/2, 1: gradient LPF [2 1 1]/4; 2: gradient LPF [3 3 2]/8; 3: gradient LPF [5 5 4 3]/16;
+//Bit 7: 4 reg_matnr_snrlpf_sadmin3th // unsigned , default = 6 X8
+//Bit 3: 0 reg_matnr_snrlpf_sadmin2th // unsigned , default = 4 X8
+#define NR2_MATNR_SNR_USF_GAIN ((0x1756 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_matnr_snr_usf_cgain // unsigned , default = 0 norm 64
+//Bit 7: 0 reg_matnr_snr_usf_ygain // unsigned , default = 0 norm 64
+#define NR2_MATNR_SNR_EDGE2B ((0x1757 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_matnr_snr_edge2beta_ofst // unsigned , default = 128
+//Bit 7: 0 reg_matnr_snr_edge2beta_gain // unsigned , default = 16
+#define NR2_MATNR_BETA_EGAIN ((0x1758 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_matnr_cbeta_egain // unsigned , default = 32 normalized to 32
+//Bit 7: 0 reg_matnr_ybeta_egain // unsigned , default = 32 normalized to 32
+#define NR2_MATNR_BETA_BRT ((0x1759 << 2) + 0xff000000)
+//Bit 31:28 reg_matnr_beta_brt_limt_hi // unsigned , default = 0
+//Bit 27:24 reg_matnr_beta_brt_slop_hi // unsigned , default = 0
+//Bit 23:16 reg_matnr_beta_brt_thrd_hi // unsigned , default = 160
+//Bit 15:12 reg_matnr_beta_brt_limt_lo // unsigned , default = 6
+//Bit 11: 8 reg_matnr_beta_brt_slop_lo // unsigned , default = 6
+//Bit 7: 0 reg_matnr_beta_brt_thrd_lo // unsigned , default = 100
+#define NR2_MATNR_XBETA_CFG ((0x175a << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:18 reg_matnr_cbeta_use_mode // unsigned , default = 0 0: beta_motion; 1: beta_edge; 2: min(beta_mot,beta_edge); 3: (beta_mot + beta_edge)/2
+//Bit 17:16 reg_matnr_ybeta_use_mode // unsigned , default = 0 0: beta_motion; 1: beta_edge; 2: min(beta_mot,beta_edge); 3: (beta_mot + beta_edge)/2;
+//Bit 15: 8 reg_matnr_cbeta_ofst // unsigned , default = 0
+//Bit 7: 0 reg_matnr_ybeta_ofst // unsigned , default = 0
+#define NR2_MATNR_YBETA_SCL ((0x175b << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_ybeta_scale_min // unsigned , default = 60
+//Bit 23:16 reg_matnr_ybeta_scale_max // unsigned , default = 255
+//Bit 15: 8 reg_matnr_ybeta_scale_gain // unsigned , default = 32 normalized 32 to 1.0
+//Bit 7: 0 reg_matnr_ybeta_scale_ofst // signed , default = 0
+#define NR2_MATNR_CBETA_SCL ((0x175c << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_cbeta_scale_min // unsigned , default = 0
+//Bit 23:16 reg_matnr_cbeta_scale_max // unsigned , default = 255
+//Bit 15: 8 reg_matnr_cbeta_scale_gain // unsigned , default = 32 normalized 32 to 1.0
+//Bit 7: 0 reg_matnr_cbeta_scale_ofst // signed , default = 0
+#define NR2_SNR_MASK ((0x175d << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20: 0 sad_msk // unsigned , default = 0x0f9f3e
+#define NR2_SAD2NORM_LUT0 ((0x175e << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_sad2norm_lut3 // unsigned , default = 114
+//Bit 23:16 reg_matnr_sad2norm_lut2 // unsigned , default = 146
+//Bit 15: 8 reg_matnr_sad2norm_lut1 // unsigned , default = 171
+//Bit 7: 0 reg_matnr_sad2norm_lut0 // unsigned , default = 205
+#define NR2_SAD2NORM_LUT1 ((0x175f << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_sad2norm_lut7 // unsigned , default = 28
+//Bit 23:16 reg_matnr_sad2norm_lut6 // unsigned , default = 35
+//Bit 15: 8 reg_matnr_sad2norm_lut5 // unsigned , default = 49
+//Bit 7: 0 reg_matnr_sad2norm_lut4 // unsigned , default = 79
+#define NR2_SAD2NORM_LUT2 ((0x1760 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_sad2norm_lut11 // unsigned , default = 15
+//Bit 23:16 reg_matnr_sad2norm_lut10 // unsigned , default = 17
+//Bit 15: 8 reg_matnr_sad2norm_lut9 // unsigned , default = 19
+//Bit 7: 0 reg_matnr_sad2norm_lut8 // unsigned , default = 23
+#define NR2_SAD2NORM_LUT3 ((0x1761 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_sad2norm_lut15 // unsigned , default = 8
+//Bit 23:16 reg_matnr_sad2norm_lut14 // unsigned , default = 9
+//Bit 15: 8 reg_matnr_sad2norm_lut13 // unsigned , default = 10
+//Bit 7: 0 reg_matnr_sad2norm_lut12 // unsigned , default = 12
+#define NR2_EDGE2BETA_LUT0 ((0x1762 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_edge2beta_lut3 // unsigned , default = 128
+//Bit 23:16 reg_matnr_edge2beta_lut2 // unsigned , default = 160
+//Bit 15: 8 reg_matnr_edge2beta_lut1 // unsigned , default = 224
+//Bit 7: 0 reg_matnr_edge2beta_lut0 // unsigned , default = 255
+#define NR2_EDGE2BETA_LUT1 ((0x1763 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_edge2beta_lut7 // unsigned , default = 4
+//Bit 23:16 reg_matnr_edge2beta_lut6 // unsigned , default = 16
+//Bit 15: 8 reg_matnr_edge2beta_lut5 // unsigned , default = 32
+//Bit 7: 0 reg_matnr_edge2beta_lut4 // unsigned , default = 80
+#define NR2_EDGE2BETA_LUT2 ((0x1764 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_edge2beta_lut11 // unsigned , default = 0
+//Bit 23:16 reg_matnr_edge2beta_lut10 // unsigned , default = 0
+//Bit 15: 8 reg_matnr_edge2beta_lut9 // unsigned , default = 0
+//Bit 7: 0 reg_matnr_edge2beta_lut8 // unsigned , default = 2
+#define NR2_EDGE2BETA_LUT3 ((0x1765 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_edge2beta_lut15 // unsigned , default = 0
+//Bit 23:16 reg_matnr_edge2beta_lut14 // unsigned , default = 0
+//Bit 15: 8 reg_matnr_edge2beta_lut13 // unsigned , default = 0
+//Bit 7: 0 reg_matnr_edge2beta_lut12 // unsigned , default = 0
+#define NR2_MOTION2BETA_LUT0 ((0x1766 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_mot2beta_lut3 // unsigned , default = 32
+//Bit 23:16 reg_matnr_mot2beta_lut2 // unsigned , default = 16
+//Bit 15: 8 reg_matnr_mot2beta_lut1 // unsigned , default = 4
+//Bit 7: 0 reg_matnr_mot2beta_lut0 // unsigned , default = 0
+#define NR2_MOTION2BETA_LUT1 ((0x1767 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_mot2beta_lut7 // unsigned , default = 196
+//Bit 23:16 reg_matnr_mot2beta_lut6 // unsigned , default = 128
+//Bit 15: 8 reg_matnr_mot2beta_lut5 // unsigned , default = 64
+//Bit 7: 0 reg_matnr_mot2beta_lut4 // unsigned , default = 48
+#define NR2_MOTION2BETA_LUT2 ((0x1768 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_mot2beta_lut11 // unsigned , default = 255
+//Bit 23:16 reg_matnr_mot2beta_lut10 // unsigned , default = 255
+//Bit 15: 8 reg_matnr_mot2beta_lut9 // unsigned , default = 240
+//Bit 7: 0 reg_matnr_mot2beta_lut8 // unsigned , default = 224
+#define NR2_MOTION2BETA_LUT3 ((0x1769 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_mot2beta_lut15 // unsigned , default = 255
+//Bit 23:16 reg_matnr_mot2beta_lut14 // unsigned , default = 255
+//Bit 15: 8 reg_matnr_mot2beta_lut13 // unsigned , default = 255
+//Bit 7: 0 reg_matnr_mot2beta_lut12 // unsigned , default = 255
+//========== nr2_snr_regs register end ==========//
+//========== nr2_tnr_regs register begin ==========//
+#define NR2_IIR_CTRL ((0x174e << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15:14 reg_lp_iir_8bit_mode // unsigned , default = 0 10bits; 1: 9bits; 2: 8bits 3: 7bits
+//Bit 13:12 reg_hp_iir_mute_mode // unsigned , default = 0
+//Bit 11: 8 reg_hp_iir_mute_thrd // unsigned , default = 0
+//Bit 7: 6 reg_hp_iir_8bit_mode // unsigned , default = 0
+//Bit 5: 4 reg_lp_iir_mute_mode // unsigned , default = 0
+//Bit 3: 0 reg_lp_iir_mute_thrd // unsigned , default = 0
+#define NR2_MATNR_MTN_CRTL ((0x176a << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:18 reg_matnr_vmtn_use_mode // unsigned , default = 0 0- Vmot, 1- Ymot/2 + (Umot+Vmot)/4; 2- Ymot/2 + max(Umot,Vmot)/2; 3- max(Ymot,Umot, Vmot)
+//Bit 17:16 reg_matnr_umtn_use_mode // unsigned , default = 0 0- Umot, 1- Ymot/2 + (Umot+Vmot)/4; 2- Ymot/2 + max(Umot,Vmot)/2; 3- max(Ymot,Umot, Vmot)
+//Bit 15:14 reg_matnr_ymtn_use_mode // unsigned , default = 0 0- Ymot, 1- Ymot/2 + (Umot+Vmot)/4; 2- Ymot/2 + max(Umot,Vmot)/2; 3- max(Ymot,Umot, Vmot)
+//Bit 13:12 reg_matnr_mtn_txt_mode // unsigned , default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_matnr_mtn_cor_mode // unsigned , default = 1 changes)
+//Bit 7: 4 reg_matnr_mtn_hpf_mode // unsigned , default = 8 extend to u4 for nr4, 0- 1x1; 1: 1x3; 2: 1x5; 3: 3x3; 4: 3o3; 5: 3x5, 6:3x3 SAD, 7: 5x3 SAD, 8-15: drt adaptive
+//Bit 3 reserved
+//Bit 2: 0 reg_matnr_mtn_lpf_mode // unsigned , default = 6 0- 1x1; 1: 1x3; 2: 1x5; 3: 3x3; 4: 3o3; 5: 3x5, 6,7: drt adaptive
+#define NR2_MATNR_MTN_CRTL2 ((0x176b << 2) + 0xff000000)
+//Bit 31:19 reserved
+//Bit 18:16 reg_matnr_iir_bs_ymode // unsigned , default = 6 LPF~~ 0- 1x1; 1: 1x3; 2: 1x5; 3: 3x3; 4: 3o3; 5: 3x5; 6/7: 0
+//Bit 15: 8 reg_matnr_mtnb_alplp_cgain // unsigned , default = 64 to 32
+//Bit 7: 0 reg_matnr_mtnb_alplp_ygain // unsigned , default = 64 to 32
+#define NR2_MATNR_MTN_COR ((0x176c << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15:12 reg_matnr_mtn_cor_cofst // unsigned , default = 3 Offset for Chroma Motion.
+//Bit 11: 8 reg_matnr_mtn_cor_cgain // unsigned , default = 3 to texture based coring for Chroma Motion. Normalized to 16 as 1
+//Bit 7: 4 reg_matnr_mtn_cor_yofst // unsigned , default = 3 Offset for Luma Motion.
+//Bit 3: 0 reg_matnr_mtn_cor_ygain // unsigned , default = 3 to texture based coring for Luma Motion. Normalized to 16 as 1
+#define NR2_MATNR_MTN_GAIN ((0x176d << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_mtn_hp_cgain // unsigned , default = 64 to MotHPF_yuv[k] Chrm channel for motion calculation, normalized to 64 as 1
+//Bit 23:16 reg_matnr_mtn_hp_ygain // unsigned , default = 64 to MotHPF_yuv[k] Luma channel for motion calculation, normalized to 64 as 1
+//Bit 15: 8 reg_matnr_mtn_lp_cgain // unsigned , default = 64 to MotLPF_yuv[k] Chrm channel for motion calculation, normalized to 32 as 1
+//Bit 7: 0 reg_matnr_mtn_lp_ygain // unsigned , default = 64 to MotLPF_yuv[k] Luma channel for motion calculation, normalized to 32 as 1
+#define NR2_MATNR_DEGHOST ((0x176e << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_matnr_deghost_mode // unsigned , default = 0 0:old_deghost; 1:soft_denoise & strong_deghost; 2:strong_denoise & soft_deghost; 3:strong_denoise & strong_deghost
+//Bit 27:25 reserved
+//Bit 24:20 reg_matnr_deghost_ygain // unsigned , default = 4
+//Bit 19:17 reserved
+//Bit 16:12 reg_matnr_deghost_cgain // unsigned , default = 4
+//Bit 11: 9 reserved
+//Bit 8 reg_matnr_deghost_en // unsigned , default = 1 0: disable; 1: enable Enable signal for DeGhost function:0: disable; 1: enable
+//Bit 7: 4 reg_matnr_deghost_cos // unsigned , default = 3 DeGhost Overshoot margin for UV channel, (X2 to u10 scale)
+//Bit 3: 0 reg_matnr_deghost_yos // unsigned , default = 3 DeGhost Overshoot margin for Luma channel, (X2 to u10 scale)
+#define NR2_MATNR_ALPHALP_LUT0 ((0x176f << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphalp_lut3 // unsigned , default = 64 low-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphalp_lut2 // unsigned , default = 128 low-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphalp_lut1 // unsigned , default = 128 low-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphalp_lut0 // unsigned , default = 128 low-pass filter alpha LUT
+#define NR2_MATNR_ALPHALP_LUT1 ((0x1770 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphalp_lut7 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphalp_lut6 // unsigned , default = 128 low-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphalp_lut5 // unsigned , default = 80 low-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphalp_lut4 // unsigned , default = 64 low-pass filter alpha LUT
+#define NR2_MATNR_ALPHALP_LUT2 ((0x1771 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphalp_lut11 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphalp_lut10 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphalp_lut9 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphalp_lut8 // unsigned , default = 255 low-pass filter alpha LUT
+#define NR2_MATNR_ALPHALP_LUT3 ((0x1772 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphalp_lut15 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphalp_lut14 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphalp_lut13 // unsigned , default = 255 low-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphalp_lut12 // unsigned , default = 255 low-pass filter alpha LUT
+#define NR2_MATNR_ALPHAHP_LUT0 ((0x1773 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphahp_lut3 // unsigned , default = 64 high-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphahp_lut2 // unsigned , default = 128 high-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphahp_lut1 // unsigned , default = 128 high-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphahp_lut0 // unsigned , default = 128 high-pass filter alpha LUT
+#define NR2_MATNR_ALPHAHP_LUT1 ((0x1774 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphahp_lut7 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphahp_lut6 // unsigned , default = 128 high-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphahp_lut5 // unsigned , default = 80 high-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphahp_lut4 // unsigned , default = 64 high-pass filter alpha LUT
+#define NR2_MATNR_ALPHAHP_LUT2 ((0x1775 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphahp_lut11 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphahp_lut10 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphahp_lut9 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphahp_lut8 // unsigned , default = 255 high-pass filter alpha LUT
+#define NR2_MATNR_ALPHAHP_LUT3 ((0x1776 << 2) + 0xff000000)
+//Bit 31:24 reg_matnr_alphahp_lut15 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 23:16 reg_matnr_alphahp_lut14 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 15: 8 reg_matnr_alphahp_lut13 // unsigned , default = 255 high-pass filter alpha LUT
+//Bit 7: 0 reg_matnr_alphahp_lut12 // unsigned , default = 255 high-pass filter alpha LUT
+#define NR2_MATNR_MTNB_BRT ((0x1777 << 2) + 0xff000000)
+//Bit 31:28 reg_matnr_mtnb_brt_limt_hi // unsigned , default = 0
+//Bit 27:24 reg_matnr_mtnb_brt_slop_hi // unsigned , default = 0
+//Bit 23:16 reg_matnr_mtnb_brt_thrd_hi // unsigned , default = 160
+//Bit 15:12 reg_matnr_mtnb_brt_limt_lo // unsigned , default = 6
+//Bit 11: 8 reg_matnr_mtnb_brt_slop_lo // unsigned , default = 6
+//Bit 7: 0 reg_matnr_mtnb_brt_thrd_lo // unsigned , default = 100
+//========== nr2_tnr_regs register end ==========//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_nr2_regs.h
+//
+//
+// Reading file: nr2_cue_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define NR2_CUE_MODE ((0x1778 << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19 reg_cue2_isabv_org_invert1 // unsigned , default = 0
+//Bit 18 reg_cue2_valid_condition // unsigned , default = 1
+//Bit 17:16 reg_cue2_orgline_flt_sel // unsigned , default = 1
+//Bit 15:12 reg_cue2_orgline_flt_alph // unsigned , default = 4
+//Bit 11 reg_cue2_isabv_org_invert // unsigned , default = 0
+//Bit 10 reg_cue2_iscur_org_invert // unsigned , default = 0
+//Bit 9 reg_cue_enable_r // unsigned , default = 1 right half frame enable
+//Bit 8 reg_cue_enable_l // unsigned , default = 1 left half frame enable
+//Bit 7 reserved
+//Bit 6: 4 reg_cue_con_rplc_mode // unsigned , default = 7 pixel chroma replace mode;
+//Bit 3: 0 reg_cue_chrm_flt_mode // unsigned , default = 5 improvement filter mode,
+#define NR2_CUE_CON_MOT_TH ((0x1779 << 2) + 0xff000000)
+//Bit 31:24 reg_cue_con_cmot_thrd2 // unsigned , default = 20 Detection threshold of up/down two rows, Chroma channel in Chroma Up-sampling Error (CUE) Detection (tighter).
+//Bit 23:16 reg_cue_con_ymot_thrd2 // unsigned , default = 20 Detection threshold of up/mid/down three rows, Luma channel in Chroma Up-sampling Error (CUE) Detection (tighter).
+//Bit 15: 8 reg_cue_con_cmot_thrd // unsigned , default = 20 Detection threshold of up/down two rows, Chroma channel in Chroma Up-sampling Error (CUE) Detection.
+//Bit 7: 0 reg_cue_con_ymot_thrd // unsigned , default = 20 Detection threshold of up/mid/down three rows, Luma channel in Chroma Up-sampling Error (CUE) Detection.
+#define NR2_CUE_CON_DIF0 ((0x177a << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_cue_con_difp1_thrd // unsigned , default = 20 field Intra-Field top/below line chroma difference threshold,
+//Bit 7: 0 reg_cue_con_difcur_thrd // unsigned , default = 0 Field/Frame Intra-Field up/down line chroma difference threshold,
+#define NR2_CUE_CON_DIF1 ((0x177b << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:16 reg_cue_con_rate0 // unsigned , default = 8 Krate to decide CUE by relationship between CUE_diflG and CUE_difEG
+//Bit 15: 8 reg_cue_con_difeg_thrd // unsigned , default = 0 to the difference between current Field/Frame middle line to down line color channel(CUE_difEG).
+//Bit 7: 0 reg_cue_con_diflg_thrd // unsigned , default = 100 to the difference between P1 field top line to current Field/Frame down line color channel (CUE_diflG).
+#define NR2_CUE_CON_DIF2 ((0x177c << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:16 reg_cue_con_rate1 // unsigned , default = 8 Krate to decide CUE by relationship between CUE_difnC and CUE_difEC
+//Bit 15: 8 reg_cue_con_difec_thrd // unsigned , default = 0 to the difference between current Field/Frame middle line to up line color channel(CUE_difEC).
+//Bit 7: 0 reg_cue_con_difnc_thrd // unsigned , default = 100 to the difference between P1 field bot line to current Field/Frame up line color channel (CUE_difnC).
+#define NR2_CUE_CON_DIF3 ((0x177d << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:16 reg_cue_con_rate2 // unsigned , default = 8 Krate to decide CUE by relationship between CUE_difP1 and CUE_difEP1
+//Bit 15: 8 reg_cue_con_difep1_thrd // unsigned , default = 10 top/below line to current field/frame middle line chroma difference (CUE_difEP1) threshold.
+//Bit 7: 0 reg_cue_con_difp1_thrd2 // unsigned , default = 10 field Intra-Field top/below line chroma difference threshold (tighter),
+#define NR2_CUE_PRG_DIF ((0x177e << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20 reg_cue_prg_enable // unsigned , default = 0 bit for progressive video CUE detection.If interlace input video,
+//Bit 19:16 reg_cue_prg_rate // unsigned , default = 4 Krate to decide CUE by relationship between CUE_difCur and (CUE_difEC+CUE_difEG)
+//Bit 15: 8 reg_cue_prg_difceg_thrd // unsigned , default = 40 Frame Intra-Field up-mid and mid-down line chroma difference threshold for progressive video CUE detection,
+//Bit 7: 0 reg_cue_prg_difcur_thrd // unsigned , default = 30 Frame Intra-Field up/down line chroma difference threshold,
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: nr2_cue_regs.h
+//
+#define NR2_CONV_MODE ((0x177f << 2) + 0xff000000)
+//Bit 3:2, Conv_c444_mode The format convert mode about 422 to 444 when data read out line buffer
+//Bit 1:0, Conv_c422_mode the format convert mode about 444 to 422 when data write to line buffer
+//// NR2 REG DEFINE END ////
+//// DET 3D REG DEFINE BEGIN ////
+//// 8'h34~8'h3f | 8'h80~8'h8f | 0x9a-0x9b
+//
+// Reading file: vpu_det3d_regs.h
+//
+//// DET 3D REG DEFINE BEGIN ////
+//// 8'h34~8'h3f
+//// DET 3D REG DEFINE END ////
+#define DET3D_MOTN_CFG ((0x1734 << 2) + 0xff000000)
+//Bit 16, reg_det3d_intr_en Det3d interrupt enable
+//Bit 9:8, reg_Det3D_Motion_Mode U2 Different mode for Motion Calculation of Luma and Chroma:
+// 0: MotY, 1: (2*MotY + (MotU + MotV))/4; 2: Max(MotY, MotU,MotV); 3:Max(MotY, (MotU+MotV)/2)
+//Bit 7:4, reg_Det3D_Motion_Core_Rate U4 K Rate to Edge (HV) details for coring of Motion Calculations, normalized to 32
+//Bit 3:0, reg_Det3D_Motion_Core_Thrd U4 2X: static coring value for Motion Detection.
+#define DET3D_CB_CFG ((0x1735 << 2) + 0xff000000)
+//Bit 7:4, reg_Det3D_ChessBd_HV_ofst U4, Noise immune offset for Horizotnal or vertical combing detection.
+//Bit 3:0, reg_Det3D_ChessBd_NHV_ofst U4, Noise immune offset for NON-Horizotnal or vertical combing detection.
+#define DET3D_SPLT_CFG ((0x1736 << 2) + 0xff000000)
+//Bit 7:4, reg_Det3D_SplitValid_ratio U4, Ratio between max_value and the avg_value of the edge mapping for split line valid detection.
+// The smaller of this value, the easier of the split line detected.
+//Bit 3:0, reg_Det3D_AvgIdx_ratio U4, Ratio to the avg_value of the edge mapping for split line position estimation.
+// The smaller of this value, the more samples will be added to the estimation.
+#define DET3D_HV_MUTE ((0x1737 << 2) + 0xff000000)
+//Bit 23:20, reg_Det3D_Edge_Ver_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Top and Bottom border part.
+//Bit 19:16, reg_Det3D_Edge_Hor_Mute U4 X2: Horizontal pixels to be mute from H/V Edge calculation Left and right border part.
+//Bit 15:12, reg_Det3D_ChessBd_Ver_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part
+//Bit 11:8, reg_Det3D_ChessBd_Hor_Mute U4 X2: Horizontal pixels to be mute from ChessBoard statistics calculation in middle part
+//Bit 7:4, reg_Det3D_STA8X8_Ver_Mute U4 1X: Vertical pixels to be mute from 8x8 statistics calculation in each block.
+//Bit 3:0, reg_Det3D_STA8X8_Hor_Mute U4 1X: Horizontal pixels to be mute from 8x8 statistics calculation in each block.
+#define DET3D_MAT_STA_P1M1 ((0x1738 << 2) + 0xff000000)
+//Bit 31:24, reg_Det3D_STA8X8_P1_K0_R8 U8 SAD to SAI ratio to decide P1, normalized to 256 (0.8)
+//Bit 23:16, reg_Det3D_STA8X8_P1_K1_R7 U8 SAD to ENG ratio to decide P1, normalized to 128 (0.5)
+//Bit 15:8, reg_Det3D_STA8X8_M1_K0_R6 U8 SAD to SAI ratio to decide M1, normalized to 64 (1.1)
+//Bit 7:0, reg_Det3D_STA8X8_M1_K1_R6 U8 SAD to ENG ratio to decide M1, normalized to 64 (0.8)
+#define DET3D_MAT_STA_P1TH ((0x1739 << 2) + 0xff000000)
+//Bit 23:16, reg_Det3D_STAYUV_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (100)
+//Bit 15:8, reg_Det3D_STAEDG_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (80)
+//Bit 7:0, reg_Det3D_STAMOT_P1_TH_L4 U8 SAD to ENG Thrd offset to decide P1, X16 (48)
+#define DET3D_MAT_STA_M1TH ((0x173a << 2) + 0xff000000)
+//Bit 23:16, reg_Det3D_STAYUV_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (100)
+//Bit 15:8, reg_Det3D_STAEDG_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (80)
+//Bit 7:0, reg_Det3D_STAMOT_M1_TH_L4 U8 SAD to ENG Thrd offset to decide M1, X16 (64)
+#define DET3D_MAT_STA_RSFT ((0x173b << 2) + 0xff000000)
+//Bit 5:4, reg_Det3D_STAYUV_RSHFT U2 YUV statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
+// 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
+//Bit 3:2, reg_Det3D_STAEDG_RSHFT U2 Horizontal and Vertical Edge Statistics SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
+// 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
+//Bit 1:0, reg_Det3D_STAMOT_RSHFT U2 Motion SAD and SAI calculation result right shift bits to accommodate the 12bits clipping:
+// 0: mainly for images <=720x480: 1: mainly for images <=1366x768: 2: mainly for images <=1920X1080: 2; 3: other higher resolutions
+#define DET3D_MAT_SYMTC_TH ((0x173c << 2) + 0xff000000)
+//Bit 31:24, reg_Det3D_STALUM_symtc_Th U8 threshold to decide if the Luma statistics is TB or LR symmetric.
+//Bit 23:16, reg_Det3D_STACHR_symtc_Th U8 threshold to decide if the Chroma (UV) statistics is TB or LR symmetric.
+//Bit 15:8, reg_Det3D_STAEDG_symtc_Th U8 threshold to decide if the Horizontal and Vertical Edge statistics is TB or LR symmetric.
+//Bit 7:0, reg_Det3D_STAMOT_symtc_Th U8 threshold to decide if the Motion statistics is TB or LR symmetric.
+#define DET3D_RO_DET_CB_HOR ((0x173d << 2) + 0xff000000)
+//Bit 31:16, RO_Det3D_ChessBd_NHor_value U16 X64: number of Pixels of Horizontally Surely NOT matching Chessboard pattern.
+//Bit 15:0, RO_Det3D_ChessBd_Hor_value U16 X64: number of Pixels of Horizontally Surely matching Chessboard pattern.
+#define DET3D_RO_DET_CB_VER ((0x173e << 2) + 0xff000000)
+//Bit 31:16, RO_Det3D_ChessBd_NVer_value U16 X64: number of Pixels of Vertically Surely NOT matching Chessboard pattern.
+//Bit 15:0, RO_Det3D_ChessBd_Ver_value U16 X64: number of Pixels of Vertically Surely matching Chessboard pattern.
+#define DET3D_RO_SPLT_HT ((0x173f << 2) + 0xff000000)
+//Bit 24, RO_Det3D_Split_HT_valid U1 horizontal LR split border detected valid signal for top half picture
+//Bit 20:16, RO_Det3D_Split_HT_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+//Bit 9:0, RO_Det3D_Split_HT_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+//// DET 3D REG DEFINE BEGIN ////
+//// 8'h80~8'h8f
+#define DET3D_RO_SPLT_HB ((0x1780 << 2) + 0xff000000)
+//Bit 24, RO_Det3D_Split_HB_valid U1 horizontal LR split border detected valid signal for top half picture
+//Bit 20:16, RO_Det3D_Split_HB_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+//Bit 9: 0, RO_Det3D_Split_HB_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+#define DET3D_RO_SPLT_VL ((0x1781 << 2) + 0xff000000)
+//Bit 24, RO_Det3D_Split_VL_valid U1 horizontal LR split border detected valid signal for top half picture
+//Bit 20:16, RO_Det3D_Split_VL_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+//Bit 9: 0, RO_Det3D_Split_VL_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+#define DET3D_RO_SPLT_VR ((0x1782 << 2) + 0xff000000)
+//Bit 24 , RO_Det3D_Split_VR_valid U1 horizontal LR split border detected valid signal for top half picture
+//Bit 20:16, RO_Det3D_Split_VR_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+//Bit 9: 0, RO_Det3D_Split_VR_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+#define DET3D_RO_MAT_LUMA_LR ((0x1783 << 2) + 0xff000000)
+//Bit 15:0, RO_Luma_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically),
+// it can be -1/0/1:-1: most likely not LR symmetric 0: not sure 1: most likely LR symmetric
+//Bit 7:0, RO_Luma_LR_symtc U1*8 Luma statistics left right pure symmetric for each band (8bands vertically),
+// it can be 0/1: 0: not sure 1: most likely LR is pure symmetric
+//Bit 4:0, RO_Luma_LR_sum S5 Total score of 8x8 Luma statistics for LR like decision,
+// the larger this score, the more confidence that this is a LR 3D video. It is sum of RO_Luma_LR_score[0~7]
+#define DET3D_RO_MAT_LUMA_TB ((0x1784 << 2) + 0xff000000)
+//Bit 15:0, RO_Luma_TB_score S2*8 LUMA statistics Top/Bottom decision score for each band (8bands Horizontally),
+//Bit 7:0, RO_Luma_TB_symtc Luma statistics Top/Bottompure symmetric for each band (8bands Horizontally),
+//Bit 4:0, RO_Luma_TB_sum Total score of 8x8 Luma statistics for TB like decision,
+#define DET3D_RO_MAT_CHRU_LR ((0x1785 << 2) + 0xff000000)
+//Bit 15:0, RO_ChrU_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically),
+//Bit 7:0, RO_ChrU_LR_symtc CHRU statistics left right pure symmetric for each band (8bands vertically),
+//Bit 4:0, RO_ChrU_LR_sum Total score of 8x8 ChrU statistics for LR like decision,
+#define DET3D_RO_MAT_CHRU_TB ((0x1786 << 2) + 0xff000000)
+//Bit 15:0, RO_ChrU_TB_score S2*8 CHRU statistics Top/Bottom decision score for each band (8bands Horizontally)
+//Bit 7:0, RO_ChrU_TB_symtc CHRU statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+//Bit 4:0, RO_ChrU_TB_sum Total score of 8x8 ChrU statistics for TB like decision
+#define DET3D_RO_MAT_CHRV_LR ((0x1787 << 2) + 0xff000000)
+//Bit 15:0, RO_ChrV_LR_score S2*8 CHRUstatistics left right decision score for each band (8bands vertically)
+//Bit 7:0, RO_ChrV_LR_symtc CHRV statistics left right pure symmetric for each band (8bands vertically)
+//Bit 4:0, RO_ChrV_LR_sum Total score of 8x8 ChrV statistics for LR like decision
+#define DET3D_RO_MAT_CHRV_TB ((0x1788 << 2) + 0xff000000)
+//Bit 15:0, RO_ChrV_TB_score CHRV statistics Top/Bottom decision score for each band (8bands Horizontally)
+//Bit 7:0, RO_ChrV_TB_symtc CHRV statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+//Bit 4:0, RO_ChrV_TB_sum Total score of 8x8 ChrV statistics for TB like decision
+#define DET3D_RO_MAT_HEDG_LR ((0x1789 << 2) + 0xff000000)
+//Bit 15:0, RO_Hedg_LR_score Horizontal Edge statistics left right decision score for each band (8bands vertically)
+//Bit 7:0, RO_Hedg_LR_symtc Horizontal Edge statistics left right pure symmetric for each band (8bands vertically)
+//Bit 4:0, RO_Hedg_LR_sum Total score of 8x8 Hedg statistics for LR like decision
+#define DET3D_RO_MAT_HEDG_TB ((0x178a << 2) + 0xff000000)
+//Bit 15:0, RO_Hedg_TB_score Horizontal Edge statistics Top/Bottom decision score for each band (8bands Horizontally)
+//Bit 7:0, RO_Hedg_TB_symtc Horizontal Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+//Bit 4:0, RO_Hedg_TB_sum Total score of 8x8 Hedg statistics for TB like decision
+#define DET3D_RO_MAT_VEDG_LR ((0x178b << 2) + 0xff000000)
+//Bit 15:0, RO_Vedg_LR_score Vertical Edge statistics left right decision score for each band (8bands vertically)
+//Bit 7:0, RO_Vedg_LR_symtc Vertical Edge statistics left right pure symmetric for each band (8bands vertically)
+//Bit 4:0, RO_Vedg_LR_sum Total score of 8x8 Vedg statistics for LR like decision
+#define DET3D_RO_MAT_VEDG_TB ((0x178c << 2) + 0xff000000)
+//Bit 15:0, RO_Vedg_TB_score Vertical Edge statistics Top/Bottom decision score for each band (8bands Horizontally)
+//Bit 7:0, RO_Vedg_TB_symtc Vertical Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+//Bit 4:0, RO_Vedg_TB_sum Total score of 8x8 Vedg statistics for TB like decision
+#define DET3D_RO_MAT_MOTN_LR ((0x178d << 2) + 0xff000000)
+//Bit 15:0, RO_Motn_LR_score Motion statistics left right decision score for each band (8bands vertically)
+//Bit 7:0, RO_Motn_LR_symtc Motion statistics left right pure symmetric for each band (8bands vertically)
+//Bit 4:0, RO_Motn_LR_sum Total score of 8x8 Motion statistics for LR like decision
+#define DET3D_RO_MAT_MOTN_TB ((0x178e << 2) + 0xff000000)
+//Bit 15:0, RO_Motn_TB_score Motion statistics Top/Bottom decision score for each band (8bands Horizontally)
+//Bit 7:0, RO_Motn_TB_symtc Motion statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+//Bit 4:0, RO_Motn_TB_sum Total score of 8x8 Motion statistics for TB like decision
+#define DET3D_RO_FRM_MOTN ((0x178f << 2) + 0xff000000)
+//Bit 15:0, RO_Det3D_Frame_Motion U16 frame based motion value sum for still image decision in FW.
+/// mat ram read enter addr
+#define DET3D_RAMRD_ADDR_PORT ((0x179a << 2) + 0xff000000)
+#define DET3D_RAMRD_DATA_PORT ((0x179b << 2) + 0xff000000)
+//
+// Closing file: vpu_det3d_regs.h
+//
+// `define DET3D_RO_SPLT_HB 8'h80
+// //Bit 24, RO_Det3D_Split_HB_valid U1 horizontal LR split border detected valid signal for top half picture
+// //Bit 20:16, RO_Det3D_Split_HB_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+// //Bit 9: 0, RO_Det3D_Split_HB_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+// `define DET3D_RO_SPLT_VL 8'h81
+// //Bit 24, RO_Det3D_Split_VL_valid U1 horizontal LR split border detected valid signal for top half picture
+// //Bit 20:16, RO_Det3D_Split_VL_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+// //Bit 9: 0, RO_Det3D_Split_VL_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+// `define DET3D_RO_SPLT_VR 8'h82
+// //Bit 24 , RO_Det3D_Split_VR_valid U1 horizontal LR split border detected valid signal for top half picture
+// //Bit 20:16, RO_Det3D_Split_VR_pxnum U5 number of pixels included for the LR split position estimation for top half picture
+// //Bit 9: 0, RO_Det3D_Split_VR_idxX4 S10 X4: horizontal pixel shifts of LR split position to the (ColMax/2) for top half picture
+// `define DET3D_RO_MAT_LUMA_LR 8'h83
+// //Bit 15:0, RO_Luma_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically),
+// // it can be -1/0/1:-1: most likely not LR symmetric 0: not sure 1: most likely LR symmetric
+// //Bit 7:0, RO_Luma_LR_symtc U1*8 Luma statistics left right pure symmetric for each band (8bands vertically),
+// // it can be 0/1: 0: not sure 1: most likely LR is pure symmetric
+// //Bit 4:0, RO_Luma_LR_sum S5 Total score of 8x8 Luma statistics for LR like decision,
+// // the larger this score, the more confidence that this is a LR 3D video. It is sum of RO_Luma_LR_score[0~7]
+// `define DET3D_RO_MAT_LUMA_TB 8'h84
+// //Bit 15:0, RO_Luma_TB_score S2*8 LUMA statistics Top/Bottom decision score for each band (8bands Horizontally),
+// //Bit 7:0, RO_Luma_TB_symtc Luma statistics Top/Bottompure symmetric for each band (8bands Horizontally),
+// //Bit 4:0, RO_Luma_TB_sum Total score of 8x8 Luma statistics for TB like decision,
+// `define DET3D_RO_MAT_CHRU_LR 8'h85
+// //Bit 15:0, RO_ChrU_LR_score S2*8 LUMA statistics left right decision score for each band (8bands vertically),
+// //Bit 7:0, RO_ChrU_LR_symtc CHRU statistics left right pure symmetric for each band (8bands vertically),
+// //Bit 4:0, RO_ChrU_LR_sum Total score of 8x8 ChrU statistics for LR like decision,
+// `define DET3D_RO_MAT_CHRU_TB 8'h86
+// //Bit 15:0, RO_ChrU_TB_score S2*8 CHRU statistics Top/Bottom decision score for each band (8bands Horizontally)
+// //Bit 7:0, RO_ChrU_TB_symtc CHRU statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+// //Bit 4:0, RO_ChrU_TB_sum Total score of 8x8 ChrU statistics for TB like decision
+// `define DET3D_RO_MAT_CHRV_LR 8'h87
+// //Bit 15:0, RO_ChrV_LR_score S2*8 CHRUstatistics left right decision score for each band (8bands vertically)
+// //Bit 7:0, RO_ChrV_LR_symtc CHRV statistics left right pure symmetric for each band (8bands vertically)
+// //Bit 4:0, RO_ChrV_LR_sum Total score of 8x8 ChrV statistics for LR like decision
+// `define DET3D_RO_MAT_CHRV_TB 8'h88
+// //Bit 15:0, RO_ChrV_TB_score CHRV statistics Top/Bottom decision score for each band (8bands Horizontally)
+// //Bit 7:0, RO_ChrV_TB_symtc CHRV statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+// //Bit 4:0, RO_ChrV_TB_sum Total score of 8x8 ChrV statistics for TB like decision
+// `define DET3D_RO_MAT_HEDG_LR 8'h89
+// //Bit 15:0, RO_Hedg_LR_score Horizontal Edge statistics left right decision score for each band (8bands vertically)
+// //Bit 7:0, RO_Hedg_LR_symtc Horizontal Edge statistics left right pure symmetric for each band (8bands vertically)
+// //Bit 4:0, RO_Hedg_LR_sum Total score of 8x8 Hedg statistics for LR like decision
+// `define DET3D_RO_MAT_HEDG_TB 8'h8a
+// //Bit 15:0, RO_Hedg_TB_score Horizontal Edge statistics Top/Bottom decision score for each band (8bands Horizontally)
+// //Bit 7:0, RO_Hedg_TB_symtc Horizontal Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+// //Bit 4:0, RO_Hedg_TB_sum Total score of 8x8 Hedg statistics for TB like decision
+// `define DET3D_RO_MAT_VEDG_LR 8'h8b
+// //Bit 15:0, RO_Vedg_LR_score Vertical Edge statistics left right decision score for each band (8bands vertically)
+// //Bit 7:0, RO_Vedg_LR_symtc Vertical Edge statistics left right pure symmetric for each band (8bands vertically)
+// //Bit 4:0, RO_Vedg_LR_sum Total score of 8x8 Vedg statistics for LR like decision
+// `define DET3D_RO_MAT_VEDG_TB 8'h8c
+// //Bit 15:0, RO_Vedg_TB_score Vertical Edge statistics Top/Bottom decision score for each band (8bands Horizontally)
+// //Bit 7:0, RO_Vedg_TB_symtc Vertical Edge statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+// //Bit 4:0, RO_Vedg_TB_sum Total score of 8x8 Vedg statistics for TB like decision
+// `define DET3D_RO_MAT_MOTN_LR 8'h8d
+// //Bit 15:0, RO_Motn_LR_score Motion statistics left right decision score for each band (8bands vertically)
+// //Bit 7:0, RO_Motn_LR_symtc Motion statistics left right pure symmetric for each band (8bands vertically)
+// //Bit 4:0, RO_Motn_LR_sum Total score of 8x8 Motion statistics for LR like decision
+// `define DET3D_RO_MAT_MOTN_TB 8'h8e
+// //Bit 15:0, RO_Motn_TB_score Motion statistics Top/Bottom decision score for each band (8bands Horizontally)
+// //Bit 7:0, RO_Motn_TB_symtc Motion statistics Top/Bottompure symmetric for each band (8bands Horizontally)
+// //Bit 4:0, RO_Motn_TB_sum Total score of 8x8 Motion statistics for TB like decision
+// `define DET3D_RO_FRM_MOTN 8'h8f
+// //Bit 15:0, RO_Det3D_Frame_Motion U16 frame based motion value sum for still image decision in FW.
+#define DI_EI_CTRL10 ((0x1793 << 2) + 0xff000000)
+//bit 31:28, reg_ei_caldrt_hstrrgchk_drtth
+//bit 27:24, reg_ei_caldrt_hstrrgchk_frcverthrd
+//bit 23:20, reg_ei_caldrt_hstrrgchk_mg
+//bit 19, reg_ei_caldrt_hstrrgchk_1sidnul
+//bit 18, reg_ei_caldrt_hstrrgchk_excpcnf
+//bit 17:16, reg_ei_caldrt_hstrrgchk_ws
+//bit 15, reg_ei_caldrt_hstrrgchk_en
+//bit 14:13, reg_ei_caldrt_hpncheck_mode
+//bit 12, reg_ei_caldrt_hpncheck_mute
+//bit 11:9, reg_ei_caldrt_hcnfcheck_mg2
+//bit 8:6, reg_ei_caldrt_hcnfcheck_mg1
+//bit 5:4, reg_ei_caldrt_hcnfcheck_mode
+//bit 3:0, reg_ei_caldrt_hcnfcheck_mg2
+#define DI_NR_1_CTRL0 ((0x1794 << 2) + 0xff000000)
+#define DI_NR_1_CTRL1 ((0x1795 << 2) + 0xff000000)
+#define DI_NR_1_CTRL2 ((0x1796 << 2) + 0xff000000)
+#define DI_NR_1_CTRL3 ((0x1797 << 2) + 0xff000000)
+#define DI_EI_XWIN0 ((0x1798 << 2) + 0xff000000)
+//bit 27:16, ei_xend0
+//bit 11:0, ei_xstart0
+#define DI_EI_XWIN1 ((0x1799 << 2) + 0xff000000)
+/// mat ram read enter addr
+// `define DET3D_RAMRD_ADDR_PORT 8'h9a
+// `define DET3D_RAMRD_DATA_PORT 8'h9b
+#define NR2_CFR_PARA_CFG0 ((0x179c << 2) + 0xff000000)
+//Bit 8, reg_CFR_CurDif_luma_mode Current Field Top/Bot line Luma difference calculation mode
+//Bit 7:6, reg_MACFR_frm_phase U2 This will be a field based phase register that need to be set by FW phase to phase:
+// this will be calculated based on dbdr_phase of the specific line of this frame.
+// u1: dbdr_phase=1, center line is DB in current line; dbdr_phase=2, center line is Dr in current line;
+//Bit 5:4, reg_CFR_CurDif_tran_mode U2 Current Field Top/Bot line Luma/Chroma transition level calculation mode,
+//Bit 3:2, reg_CFR_alpha_mode U2 Alpha selection mode for CFR block from curAlp and motAlp i.e. 0: motAlp; 1: (motAlp+curAlp)/2; 2: min(motAlp,curAlp); 3: max(motAlp,curAlp);
+//Bit 1:0, reg_CFR_Motion_Luma_mode U2 LumaMotion Calculation mode for MA-CFR. 0: top/bot Lumma motion; 1: middle Luma Motion 2: top/bot + middle motion; 3: max(top/tot motion, middle motion)
+#define NR2_CFR_PARA_CFG1 ((0x179d << 2) + 0xff000000)
+//Bit 23:16, reg_CFR_alpha_gain gain to map muxed curAlp and motAlp to alpha that will be used for final blending.
+//Bit 15: 8, reg_CFR_Motion_ofst Offset to Motion to calculate the motAlp, e,g:motAlp= reg_CFR_Motion_ofst- Motion;This register can be seen as the level of motion that we consider it at moving.
+//Bit 7: 0, reg_CFR_CurDif_gain gain to CurDif to map to alpha, normalized to 32;
+//// DET 3D REG DEFINE END ////
+#define DI_EI_CTRL11 ((0x179e << 2) + 0xff000000)
+//bit 30:29, reg_ei_amb_detect_mode
+//bit 28:24, reg_ei_amb_detect_winth
+//bit 23:21, reg_ei_amb_decide_rppth
+//bit 20:19, reg_ei_retime_lastmappncnfltchk_drtth
+//bit 18:16, reg_ei_retime_lastmappncnfltchk_mode
+//bit 15:14, reg_ei_retime_lastmapvertfrcchk_mode
+//bit 13:12, reg_ei_retime_lastvertfrcchk_mode
+//bit 11:8, reg_ei_retime_lastpnchk_drtth
+//bit 6, reg_ei_retime_lastpnchk_en
+//bit 5:4, reg_ei_retime_mode
+//bit 3, reg_ei_retime_last_en
+//bit 2, reg_ei_retime_ab_en
+//bit 1, reg_ei_caldrt_hstrvertfrcchk_en
+//bit 0, reg_ei_caldrt_hstrrgchk_mode
+#define DI_EI_CTRL12 ((0x179f << 2) + 0xff000000)
+//bit 31:28, reg_ei_drtdelay2_lmt
+//bit 27:26, reg_ei_drtdelay2_notver_lrwin
+//bit 25:24, reg_ei_drtdelay_mode
+//bit 23, reg_ei_drtdelay2_mode
+//bit 22:20, reg_ei_assign_xla_signm0th
+//bit 19, reg_ei_assign_pkbiasvert_en
+//bit 18, reg_ei_assign_xla_en
+//bit 17:16, reg_ei_assign_xla_mode
+//bit 15:12, reg_ei_assign_nlfilter_magin
+//bit 11:8, reg_ei_localsearch_maxrange
+//bit 7:4, reg_ei_xla_drtth
+//bit 3:0, reg_ei_flatmsad_thrd
+//`define DI_DIWR_CANVAS 8'ha0
+//`define DI_DIWR_URGENT 8'ha1
+//`define DI_NRWR_CANVAS 8'ha2
+//`define DI_NRWR_URGENT 8'ha7
+//`define DI_CONTWR_X 8'ha0
+//`define DI_CONTWR_Y 8'ha1
+//`define DI_CONTWR_CTRL 8'ha2
+//`define DI_CONTPRD_X 8'ha3
+//`define DI_CONTPRD_Y 8'ha4
+//`define DI_CONTP2RD_X 8'ha5
+//`define DI_CONTP2RD_Y 8'ha6
+#define DI_RO_PRE_FIELD_CNT0 ((0x17a3 << 2) + 0xff000000)
+#define DI_RO_PRE_FIELD_CNT1 ((0x17a4 << 2) + 0xff000000)
+#define DI_RO_POS_FRAME_CNT0 ((0x17a5 << 2) + 0xff000000)
+#define DI_RO_POS_FRAME_CNT1 ((0x17a6 << 2) + 0xff000000)
+//`define DI_CONTRD_CTRL 8'ha7
+#define DI_EI_CTRL13 ((0x17a8 << 2) + 0xff000000)
+//bit 27:24, reg_ei_int_drt2x_chrdrt_limit
+//bit 23:20, reg_ei_int_drt16x_core
+//bit 19:16, reg_ei_int_drtdelay2_notver_cancv
+//bit 15:8, reg_ei_int_drtdelay2_notver_sadth
+//bit 7:0, reg_ei_int_drtdelay2_vlddrt_sadth
+#define DI_MTN_1_CTRL6 ((0x17a9 << 2) + 0xff000000)
+//bit 31:24, mtn_m1b_extnd
+//bit 23:16, mtn_m1b_errod
+//bit 15: 8, mtn_core_ykinter
+//bit 7: 0, mtn_core_ckinter
+#define DI_MTN_1_CTRL7 ((0x17aa << 2) + 0xff000000)
+//bit 31:24, mtn_core_mxcmby
+//bit 23:16, mtn_core_mxcmbc
+//bit 15: 8, mtn_core_y
+//bit 7: 0, mtn_core_c
+#define DI_MTN_1_CTRL8 ((0x17ab << 2) + 0xff000000)
+//bit 31:24, mtn_fcore_ykinter
+//bit 23:16, mtn_fcore_ckinter
+//bit 15: 8, mtn_fcore_ykintra
+//bit 7: 0, mtn_fcore_ckintra
+#define DI_MTN_1_CTRL9 ((0x17ac << 2) + 0xff000000)
+//bit 31:24, mtn_fcore_2yrate
+//bit 23:16, mtn_fcore_2crate
+//bit 15: 8, mtn_fcore_y
+//bit 7: 0, mtn_fcore_c
+#define DI_MTN_1_CTRL10 ((0x17ad << 2) + 0xff000000)
+//bit 27:24, mtn_motfld0
+//bit 19:16, mtn_stlfld0
+//bit 11: 8, mtn_motfld1
+//bit 3: 0, mtn_stlfld1
+#define DI_MTN_1_CTRL11 ((0x17ae << 2) + 0xff000000)
+//bit 27:24, mtn_smotevn
+//bit 20:16, mtn_smotodd
+//bit 11: 8, mtn_sstlevn
+//bit 4: 0, mtn_sstlodd
+#define DI_MTN_1_CTRL12 ((0x17af << 2) + 0xff000000)
+//bit 31:24, mtn_mgain
+//bit 17:16, mtn_mmode
+//bit 15: 8, mtn_sthrd
+//bit 4: 0, mtn_sgain
+//`define DI_NRWR_X 8'hc0
+//`define DI_NRWR_Y 8'hc1
+//bit 31:30 nrwr_words_lim
+//bit 29 nrwr_rev_y
+//bit 28:16 nrwr_start_y
+//bit 15 nrwr_ext_en
+//bit 12:0 nrwr_end_y
+//`define DI_NRWR_CTRL 8'hc2
+//bit 31 pending_ddr_wrrsp_diwr
+//bit 30 nrwr_reg_swap
+//bit 29:26 nrwr_burst_lim
+//bit 25 nrwr_canvas_syncen
+//bit 24 nrwr_no_clk_gate
+//bit 23:22 nrwr_rgb_mode 0:422 to one canvas;1:4:4:4 to one canvas;
+ //2:Y to luma , CBCR to chroma canvas ,for nv12/21; 3 : reserved
+//bit 21:20 nrwr_hconv_mode
+//bit 19:18 nrwr_vconv_mode
+//bit 17 nrwr_swap_cbcr
+//bit 16 nrwr_urgent
+//bit 15:8 nrwr_canvas_index_chroma
+//bit 7:0 nrwr_canvas_index_luma
+//`define DI_MTNWR_X 8'hc3
+//`define DI_MTNWR_Y 8'hc4
+//`define DI_MTNWR_CTRL 8'hc5
+#define DI_RO_CRC_NRWR ((0x17c0 << 2) + 0xff000000)
+#define DI_RO_CRC_MTNWR ((0x17c1 << 2) + 0xff000000)
+#define DI_RO_CRC_DEINT ((0x17c2 << 2) + 0xff000000)
+#define DI_CRC_CHK0 ((0x17c3 << 2) + 0xff000000)
+#define DI_CRC_CHK1 ((0x17c4 << 2) + 0xff000000)
+//`define DI_DIWR_X 8'hc6
+//`define DI_DIWR_Y 8'hc7
+//bit 31:30 diwr_words_lim
+//bit 29 diwr_rev_y
+//bit 28:16 diwr_start_y
+//bit 15 diwr_ext_en
+//bit 12:0 diwr_end_y
+//`define DI_DIWR_CTRL 8'hc8
+//bit 31 pending_ddr_wrrsp_diwr
+//bit 30 diwr_reg_swap
+//bit 29:26 diwr_burst_lim
+//bit 25 diwr_canvas_syncen
+//bit 24 diwr_no_clk_gate
+//bit 23:22 diwr_rgb_mode 0:422 to one canvas;1:4:4:4 to one canvas;
+ //2:Y to luma , CBCR to chroma canvas ,for nv12/21; 3 : reserved
+//bit 21:20 diwr_hconv_mode
+//bit 19:18 diwr_vconv_mode
+//bit 17 diwr_swap_cbcr
+//bit 16 diwr_urgent
+//bit 15:8 diwr_canvas_index_chroma
+//bit 7:0 diwr_canvas_index_luma
+//`define DI_MTNCRD_X 8'hc9
+//`define DI_MTNCRD_Y 8'hca
+//`define DI_MTNPRD_X 8'hcb
+//`define DI_MTNPRD_Y 8'hcc
+//`define DI_MTNRD_CTRL 8'hcd
+#define DI_TOP_PRE_CTRL ((0x17c5 << 2) + 0xff000000)
+#define DI_TOP_POST_CTRL ((0x17c6 << 2) + 0xff000000)
+#define DI_PRE_GL_CTRL ((0x17c7 << 2) + 0xff000000)
+#define DI_PRE_GL_THD ((0x17c8 << 2) + 0xff000000)
+#define DI_POST_GL_CTRL ((0x17c9 << 2) + 0xff000000)
+#define DI_POST_GL_THD ((0x17ca << 2) + 0xff000000)
+#define DI_RO_PRE_DBG ((0x17cb << 2) + 0xff000000)
+#define DI_RO_POST_DBG ((0x17cc << 2) + 0xff000000)
+#define DI_TOP_CTRL ((0x17cd << 2) + 0xff000000)
+#define DI_AFBCD_GCLK0 ((0x17ce << 2) + 0xff000000)
+#define DI_AFBCD_GCLK1 ((0x17cf << 2) + 0xff000000)
+#define DI_RDMIF_DEPTH0 ((0x17d0 << 2) + 0xff000000)
+#define DI_RDMIF_DEPTH1 ((0x17d1 << 2) + 0xff000000)
+#define DI_RDMIF_DEPTH2 ((0x17d2 << 2) + 0xff000000)
+#define DI_TOP_CTRL1 ((0x17d3 << 2) + 0xff000000)
+#define DI_AFBCE0_HOLD_CTRL ((0x17d4 << 2) + 0xff000000)
+#define DI_AFBCE1_HOLD_CTRL ((0x17d5 << 2) + 0xff000000)
+// 0xe0 - 0xff
+//
+// Reading file: di_pd_grad_reg.h
+//
+#define DI_PD_GRAD_CTRL ((0x17e0 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11:4 reg_fd_min_grad_th // default 255 //u8, for cur/pre1 field. cur_min_grad_err > th, will be excluded of statistic
+//Bit 3 reg_fd_min_grad_th_adjust_en // default 1 //u1, reg_fd_min_grad_err_th adjustment enable/disable
+//Bit 2 reg_fd_err_grad_bf_flt_en // default 1 //u1, 1:comput err_grad_sum before horizontal filtering; 0: ...after...; default=1;
+//Bit 1 reg_fd_comb_field_sel // default 0 //u1, comb consists of 2 field; 0: cur-pre; 1:pre-pre2;
+//Bit 0 reg_fd_iscur_top_inver // default 0 //u1, current field is top flag invert; 0 no invert, 1, invert
+#define DI_PD_GRAD_TH_P ((0x17e1 << 2) + 0xff000000)
+//Bit 31:24 reg_fd_min_grad_th_p0 //default 2 //u8,
+//Bit 23:16 reg_fd_min_grad_th_p1 //default 4 //u8,
+//Bit 15:8 reg_fd_min_grad_th_p2 //default 8 //u8,
+//Bit 7:0 reg_fd_min_grad_th_p3 //default 12 //u8,
+#define DI_PD_GRAD_TH_N ((0x17e2 << 2) + 0xff000000)
+//Bit 31:24 reg_fd_min_grad_th_n0 //default 4 //u8,
+//Bit 23:16 reg_fd_min_grad_th_n1 //default 8 //u8,
+//Bit 15:8 reg_fd_min_grad_th_n2 //default 16 //u8,
+//Bit 7:0 reg_fd_min_grad_th_n3 //default 32 //u8,
+#define DI_PD_GRAD_GAIN_P ((0x17e3 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:24 reg_fd_min_grad_gain_p0 //default 16 //u5,
+//Bit 23:21 reserved
+//Bit 20:16 reg_fd_min_grad_gain_p1 //default 16 //u5,
+//Bit 15:13 reserved
+//Bit 12:8 reg_fd_min_grad_gain_p2 //default 16 //u5,
+//Bit 7:5 reserved
+//Bit 4:0 reg_fd_min_grad_gain_p3 //default 16 //u5,
+#define DI_PD_GRAD_GAIN_N ((0x17e4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:24 reg_fd_min_grad_gain_n0 //default 12 //u5,
+//Bit 23:21 reserved
+//Bit 20:16 reg_fd_min_grad_gain_n1 //default 12 //u5,
+//Bit 15:13 reserved
+//Bit 12:8 reg_fd_min_grad_gain_n2 //default 14 //u5,
+//Bit 7:5 reserved
+//Bit 4:0 reg_fd_min_grad_gain_n3 //default 15 //u5,
+#define DI_PD_RO_SUM_P_WIN0 ((0x17e5 << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_p0
+#define DI_PD_RO_SUM_P_WIN1 ((0x17e6 << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_p1
+#define DI_PD_RO_SUM_P_WIN2 ((0x17e7 << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_p2
+#define DI_PD_RO_SUM_P_WIN3 ((0x17e8 << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_p3
+#define DI_PD_RO_SUM_P_WIN4 ((0x17e9 << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_p4
+#define DI_PD_RO_SUM_N_WIN0 ((0x17ea << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_n0
+#define DI_PD_RO_SUM_N_WIN1 ((0x17eb << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_n1
+#define DI_PD_RO_SUM_N_WIN2 ((0x17ec << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_n2
+#define DI_PD_RO_SUM_N_WIN3 ((0x17ed << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_n3
+#define DI_PD_RO_SUM_N_WIN4 ((0x17ee << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_n4
+#define DI_PD_RO_CNT_P_WIN0 ((0x17ef << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_p0
+#define DI_PD_RO_CNT_P_WIN1 ((0x17f0 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_p1
+#define DI_PD_RO_CNT_P_WIN2 ((0x17f1 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_p2
+#define DI_PD_RO_CNT_P_WIN3 ((0x17f2 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_p3
+#define DI_PD_RO_CNT_P_WIN4 ((0x17f3 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_p4
+#define DI_PD_RO_CNT_N_WIN0 ((0x17f4 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_n0
+#define DI_PD_RO_CNT_N_WIN1 ((0x17f5 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_n1
+#define DI_PD_RO_CNT_N_WIN2 ((0x17f6 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_n2
+#define DI_PD_RO_CNT_N_WIN3 ((0x17f7 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_n3
+#define DI_PD_RO_CNT_N_WIN4 ((0x17f8 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_n4
+#define DI_PD_RO_SUM_P ((0x17f9 << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_p_glb
+#define DI_PD_RO_SUM_N ((0x17fa << 2) + 0xff000000)
+//Bit 31:0 ro_fd_err_grad_sum_n_glb
+#define DI_PD_RO_CNT_P ((0x17fb << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_p_glb
+#define DI_PD_RO_CNT_N ((0x17fc << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20:0 ro_fd_err_grad_cnt_n_glb
+//
+// Closing file: di_pd_grad_reg.h
+//
+//`define DI_INP_GEN_REG 8'hce
+//`define DI_INP_CANVAS0 8'hcf
+//`define DI_INP_LUMA_X0 8'hd0
+//`define DI_INP_LUMA_Y0 8'hd1
+//`define DI_INP_CHROMA_X0 8'hd2
+//`define DI_INP_CHROMA_Y0 8'hd3
+//`define DI_INP_RPT_LOOP 8'hd4
+//`define DI_INP_LUMA0_RPT_PAT 8'hd5
+//`define DI_INP_CHROMA0_RPT_PAT 8'hd6
+//`define DI_INP_DUMMY_PIXEL 8'hd7
+//`define DI_INP_LUMA_FIFO_SIZE 8'hd8
+//`define DI_INP_RANGE_MAP_Y 8'hba
+//`define DI_INP_RANGE_MAP_CB 8'hbb
+//`define DI_INP_RANGE_MAP_CR 8'hbc
+//`define DI_INP_GEN_REG2 8'h91
+//
+//`define DI_INP_FMT_CTRL 8'hd9
+//`define DI_INP_FMT_W 8'hda
+////
+//`define DI_MEM_GEN_REG 8'hdb
+//`define DI_MEM_CANVAS0 8'hdc
+//`define DI_MEM_LUMA_X0 8'hdd
+//`define DI_MEM_LUMA_Y0 8'hde
+//`define DI_MEM_CHROMA_X0 8'hdf
+//`define DI_MEM_CHROMA_Y0 8'he0
+//`define DI_MEM_RPT_LOOP 8'he1
+//`define DI_MEM_LUMA0_RPT_PAT 8'he2
+//`define DI_MEM_CHROMA0_RPT_PAT 8'he3
+//`define DI_MEM_DUMMY_PIXEL 8'he4
+//`define DI_MEM_LUMA_FIFO_SIZE 8'he5
+//`define DI_MEM_RANGE_MAP_Y 8'hbd
+//`define DI_MEM_RANGE_MAP_CB 8'hbe
+//`define DI_MEM_RANGE_MAP_CR 8'hbf
+//`define DI_MEM_GEN_REG2 8'h92
+//
+//`define DI_MEM_FMT_CTRL 8'he6
+//`define DI_MEM_FMT_W 8'he7
+//
+//`define DI_IF1_GEN_REG 8'he8
+//`define DI_IF1_CANVAS0 8'he9
+//`define DI_IF1_LUMA_X0 8'hea
+//`define DI_IF1_LUMA_Y0 8'heb
+//`define DI_IF1_CHROMA_X0 8'hec
+//`define DI_IF1_CHROMA_Y0 8'hed
+//`define DI_IF1_RPT_LOOP 8'hee
+//`define DI_IF1_LUMA0_RPT_PAT 8'hef
+//`define DI_IF1_CHROMA0_RPT_PAT 8'hf0
+//`define DI_IF1_DUMMY_PIXEL 8'hf1
+//`define DI_IF1_LUMA_FIFO_SIZE 8'hf2
+//`define DI_IF1_RANGE_MAP_Y 8'hfc
+//`define DI_IF1_RANGE_MAP_CB 8'hfd
+//`define DI_IF1_RANGE_MAP_CR 8'hfe
+//`define DI_IF1_GEN_REG2 8'h90
+//
+//`define DI_IF1_FMT_CTRL 8'hf3
+//`define DI_IF1_FMT_W 8'hf4
+//
+//
+//`define DI_CHAN2_GEN_REG 8'hf5
+//`define DI_CHAN2_CANVAS0 8'hf6
+//`define DI_CHAN2_LUMA_X0 8'hf7
+//`define DI_CHAN2_LUMA_Y0 8'hf8
+//`define DI_CHAN2_CHROMA_X0 8'hf9
+//`define DI_CHAN2_CHROMA_Y0 8'hfa
+//`define DI_CHAN2_RPT_LOOP 8'hfb
+//`define DI_CHAN2_LUMA0_RPT_PAT 8'hb0
+//`define DI_CHAN2_CHROMA0_RPT_PAT 8'hb1
+//`define DI_CHAN2_DUMMY_PIXEL 8'hb2
+//`define DI_CHAN2_LUMA_FIFO_SIZE 8'hb3
+//`define DI_CHAN2_RANGE_MAP_Y 8'hb4
+//`define DI_CHAN2_RANGE_MAP_CB 8'hb5
+//`define DI_CHAN2_RANGE_MAP_CR 8'hb6
+//`define DI_CHAN2_GEN_REG2 8'hb7
+//`define DI_CHAN2_FMT_CTRL 8'hb8
+//`define DI_CHAN2_FMT_W 8'hb9
+//
+// Closing file: vpu_mad_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: MADD_VCBUS_BASE = 0x18
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: di_dolby_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DI_DOLBY_CORE1C_REG_START ((0x1800 << 2) + 0xff000000)
+#define DI_DOLBY_CORE1C_CLKGATE_CTRL ((0x18f2 << 2) + 0xff000000)
+#define DI_DOLBY_CORE1C_SWAP_CTRL0 ((0x18f3 << 2) + 0xff000000)
+#define DI_DOLBY_CORE1C_SWAP_CTRL1 ((0x18f4 << 2) + 0xff000000)
+#define DI_DOLBY_CORE1C_SWAP_CTRL2 ((0x18f5 << 2) + 0xff000000)
+#define DI_DOLBY_CORE1C_SWAP_CTRL3 ((0x18f6 << 2) + 0xff000000)
+#define DI_DOLBY_CORE1C_SWAP_CTRL4 ((0x18f7 << 2) + 0xff000000)
+#define DI_DOLBY_CORE1C_SWAP_CTRL5 ((0x18f8 << 2) + 0xff000000)
+#define DI_DOLBY_CORE1C_DMA_CTRL ((0x18f9 << 2) + 0xff000000)
+#define DI_DOLBY_CORE1C_DMA_STATUS ((0x18fa << 2) + 0xff000000)
+#define DI_DOLBY_CORE1C_STATUS0 ((0x18fb << 2) + 0xff000000)
+#define DI_DOLBY_CORE1C_STATUS1 ((0x18fc << 2) + 0xff000000)
+#define DI_DOLBY_CORE1C_STATUS2 ((0x18fd << 2) + 0xff000000)
+#define DI_DOLBY_CORE1C_STATUS3 ((0x18fe << 2) + 0xff000000)
+#define DI_DOLBY_CORE1C_DMA_PORT ((0x18ff << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: di_dolby_regs.h
+//
+//`include "di_inp_afbc_dec_regs.h"
+//`include "di_mem_afbc_dec_regs.h"
+//`include "fgrain_di_regs.h"
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: DISP_IF0_VCBUS_BASE = 0x19
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: disp_if_regs.h
+//
+#define L_GAMMA_CNTL_PORT ((0x1900 << 2) + 0xff000000)
+#define L_GAMMA_DATA_PORT ((0x1901 << 2) + 0xff000000)
+#define L_GAMMA_ADDR_PORT ((0x1902 << 2) + 0xff000000)
+#define L_GAMMA_VCOM_HSWITCH_ADDR ((0x1903 << 2) + 0xff000000)
+#define L_RGB_BASE_ADDR ((0x1905 << 2) + 0xff000000)
+#define L_RGB_COEFF_ADDR ((0x1906 << 2) + 0xff000000)
+#define L_POL_CNTL_ADDR ((0x1907 << 2) + 0xff000000)
+#define L_DITH_CNTL_ADDR ((0x1908 << 2) + 0xff000000)
+#define L_GAMMA_PROBE_CTRL ((0x1909 << 2) + 0xff000000)
+//read only
+#define L_GAMMA_PROBE_COLOR_L ((0x190a << 2) + 0xff000000)
+#define L_GAMMA_PROBE_COLOR_H ((0x190b << 2) + 0xff000000)
+#define L_GAMMA_PROBE_HL_COLOR ((0x190c << 2) + 0xff000000)
+#define L_GAMMA_PROBE_POS_X ((0x190d << 2) + 0xff000000)
+#define L_GAMMA_PROBE_POS_Y ((0x190e << 2) + 0xff000000)
+#define L_STH1_HS_ADDR ((0x1910 << 2) + 0xff000000)
+#define L_STH1_HE_ADDR ((0x1911 << 2) + 0xff000000)
+#define L_STH1_VS_ADDR ((0x1912 << 2) + 0xff000000)
+#define L_STH1_VE_ADDR ((0x1913 << 2) + 0xff000000)
+#define L_STH2_HS_ADDR ((0x1914 << 2) + 0xff000000)
+#define L_STH2_HE_ADDR ((0x1915 << 2) + 0xff000000)
+#define L_STH2_VS_ADDR ((0x1916 << 2) + 0xff000000)
+#define L_STH2_VE_ADDR ((0x1917 << 2) + 0xff000000)
+#define L_OEH_HS_ADDR ((0x1918 << 2) + 0xff000000)
+#define L_OEH_HE_ADDR ((0x1919 << 2) + 0xff000000)
+#define L_OEH_VS_ADDR ((0x191a << 2) + 0xff000000)
+#define L_OEH_VE_ADDR ((0x191b << 2) + 0xff000000)
+#define L_VCOM_HSWITCH_ADDR ((0x191c << 2) + 0xff000000)
+#define L_VCOM_VS_ADDR ((0x191d << 2) + 0xff000000)
+#define L_VCOM_VE_ADDR ((0x191e << 2) + 0xff000000)
+#define L_CPV1_HS_ADDR ((0x191f << 2) + 0xff000000)
+#define L_CPV1_HE_ADDR ((0x1920 << 2) + 0xff000000)
+#define L_CPV1_VS_ADDR ((0x1921 << 2) + 0xff000000)
+#define L_CPV1_VE_ADDR ((0x1922 << 2) + 0xff000000)
+#define L_CPV2_HS_ADDR ((0x1923 << 2) + 0xff000000)
+#define L_CPV2_HE_ADDR ((0x1924 << 2) + 0xff000000)
+#define L_CPV2_VS_ADDR ((0x1925 << 2) + 0xff000000)
+#define L_CPV2_VE_ADDR ((0x1926 << 2) + 0xff000000)
+#define L_STV1_HS_ADDR ((0x1927 << 2) + 0xff000000)
+#define L_STV1_HE_ADDR ((0x1928 << 2) + 0xff000000)
+#define L_STV1_VS_ADDR ((0x1929 << 2) + 0xff000000)
+#define L_STV1_VE_ADDR ((0x192a << 2) + 0xff000000)
+#define L_STV2_HS_ADDR ((0x192b << 2) + 0xff000000)
+#define L_STV2_HE_ADDR ((0x192c << 2) + 0xff000000)
+#define L_STV2_VS_ADDR ((0x192d << 2) + 0xff000000)
+#define L_STV2_VE_ADDR ((0x192e << 2) + 0xff000000)
+#define L_OEV1_HS_ADDR ((0x192f << 2) + 0xff000000)
+#define L_OEV1_HE_ADDR ((0x1930 << 2) + 0xff000000)
+#define L_OEV1_VS_ADDR ((0x1931 << 2) + 0xff000000)
+#define L_OEV1_VE_ADDR ((0x1932 << 2) + 0xff000000)
+#define L_OEV2_HS_ADDR ((0x1933 << 2) + 0xff000000)
+#define L_OEV2_HE_ADDR ((0x1934 << 2) + 0xff000000)
+#define L_OEV2_VS_ADDR ((0x1935 << 2) + 0xff000000)
+#define L_OEV2_VE_ADDR ((0x1936 << 2) + 0xff000000)
+#define L_OEV3_HS_ADDR ((0x1937 << 2) + 0xff000000)
+#define L_OEV3_HE_ADDR ((0x1938 << 2) + 0xff000000)
+#define L_OEV3_VS_ADDR ((0x1939 << 2) + 0xff000000)
+#define L_OEV3_VE_ADDR ((0x193a << 2) + 0xff000000)
+#define L_LCD_PWR_ADDR ((0x193b << 2) + 0xff000000)
+#define L_LCD_PWM0_LO_ADDR ((0x193c << 2) + 0xff000000)
+#define L_LCD_PWM0_HI_ADDR ((0x193d << 2) + 0xff000000)
+#define L_LCD_PWM1_LO_ADDR ((0x193e << 2) + 0xff000000)
+#define L_LCD_PWM1_HI_ADDR ((0x193f << 2) + 0xff000000)
+#define L_INV_CNT_ADDR ((0x1940 << 2) + 0xff000000)
+#define L_TCON_MISC_SEL_ADDR ((0x1941 << 2) + 0xff000000)
+#define L_DUAL_PORT_CNTL_ADDR ((0x1942 << 2) + 0xff000000)
+#define MLVDS_CLK_CTL1_HI ((0x1943 << 2) + 0xff000000)
+#define MLVDS_CLK_CTL1_LO ((0x1944 << 2) + 0xff000000)
+// [31:30] enable mlvds clocks
+// [24] mlvds_clk_half_delay 24 // Bit 0
+// [23:0] mlvds_clk_pattern 0 // Bit 23:0
+#define L_TCON_DOUBLE_CTL ((0x1949 << 2) + 0xff000000)
+#define L_TCON_PATTERN_HI ((0x194a << 2) + 0xff000000)
+#define L_TCON_PATTERN_LO ((0x194b << 2) + 0xff000000)
+#define LDIM_BL_ADDR_PORT ((0x194e << 2) + 0xff000000)
+#define LDIM_BL_DATA_PORT ((0x194f << 2) + 0xff000000)
+#define L_DE_HS_ADDR ((0x1951 << 2) + 0xff000000)
+#define L_DE_HE_ADDR ((0x1952 << 2) + 0xff000000)
+#define L_DE_VS_ADDR ((0x1953 << 2) + 0xff000000)
+#define L_DE_VE_ADDR ((0x1954 << 2) + 0xff000000)
+#define L_HSYNC_HS_ADDR ((0x1955 << 2) + 0xff000000)
+#define L_HSYNC_HE_ADDR ((0x1956 << 2) + 0xff000000)
+#define L_HSYNC_VS_ADDR ((0x1957 << 2) + 0xff000000)
+#define L_HSYNC_VE_ADDR ((0x1958 << 2) + 0xff000000)
+#define L_VSYNC_HS_ADDR ((0x1959 << 2) + 0xff000000)
+#define L_VSYNC_HE_ADDR ((0x195a << 2) + 0xff000000)
+#define L_VSYNC_VS_ADDR ((0x195b << 2) + 0xff000000)
+#define L_VSYNC_VE_ADDR ((0x195c << 2) + 0xff000000)
+// bit 8 -- vfifo_mcu_enable
+// bit 7 -- halt_vs_de
+// bit 6 -- R8G8B8_format
+// bit 5 -- R6G6B6_format (round to 6 bits)
+// bit 4 -- R5G6B5_format
+// bit 3 -- dac_dith_sel
+// bit 2 -- lcd_mcu_enable_de -- ReadOnly
+// bit 1 -- lcd_mcu_enable_vsync -- ReadOnly
+// bit 0 -- lcd_mcu_enable
+#define L_LCD_MCU_CTL ((0x195d << 2) + 0xff000000)
+#define P2P_CH_SWAP0 ((0x195e << 2) + 0xff000000)
+#define P2P_CH_SWAP1 ((0x195f << 2) + 0xff000000)
+#define P2P_BIT_REV ((0x1950 << 2) + 0xff000000)
+//**************************************************************************
+//* Dual port mLVDS registers
+//**************************************************************************
+// bit 3 - enable_u_dual_mlvds_dp_clk
+// bit 2 - enable_u_map_mlvds_r_clk
+// bit 1 - enable_u_map_mlvds_l_clk
+// bit 0 - dual_mlvds_en
+//`define DUAL_MLVDS_CTL 8'h60
+// bit[12:0] - dual_mlvds_line_start
+//`define DUAL_MLVDS_LINE_START 8'h61
+// bit[12:0] - dual_mlvds_line_end
+//`define DUAL_MLVDS_LINE_END 8'h62
+// bit[12:0] - dual_mlvds_w_pixel_start_l
+//`define DUAL_MLVDS_PIXEL_W_START_L 8'h63
+// bit[12:0] - dual_mlvds_w_pixel_end_l
+//`define DUAL_MLVDS_PIXEL_W_END_L 8'h64
+// bit[12:0] - dual_mlvds_w_pixel_start_r
+//`define DUAL_MLVDS_PIXEL_W_START_R 8'h65
+// bit[12:0] - dual_mlvds_w_pixel_end_r
+//`define DUAL_MLVDS_PIXEL_W_END_R 8'h66
+// bit[12:0] - dual_mlvds_r_pixel_start_l
+//`define DUAL_MLVDS_PIXEL_R_START_L 8'h67
+// bit[12:0] - dual_mlvds_r_pixel_cnt_l
+//`define DUAL_MLVDS_PIXEL_R_CNT_L 8'h68
+// bit[12:0] - dual_mlvds_r_pixel_start_r
+//`define DUAL_MLVDS_PIXEL_R_START_R 8'h69
+// bit[12:0] - dual_mlvds_r_pixel_cnt_r
+//`define DUAL_MLVDS_PIXEL_R_CNT_R 8'h6a
+// bit[15] - v_inversion_en
+// bit[12:0] - v_inversion_pixel
+//`define V_INVERSION_PIXEL 8'h70
+// bit[15] - v_inversion_sync_en
+// bit[12:0] - v_inversion_line
+//`define V_INVERSION_LINE 8'h71
+// bit[15:12] - v_loop_r
+// bit[11:10] - v_pattern_1_r
+// bit[9:8] - v_pattern_0_r
+// bit[7:4] - v_loop_l
+// bit[3:2] - v_pattern_1_l
+// bit[1:0] - v_pattern_0_l
+//`define V_INVERSION_CONTROL 8'h72
+//`define MLVDS2_CONTROL 8'h74
+ #define mLVDS2_RESERVED 15 // 15
+ #define mLVDS2_double_pattern 14 // 14
+ #define mLVDS2_ins_reset 8 // 13:8 // each channel has one bit
+ #define mLVDS2_dual_gate 7
+ #define mLVDS2_bit_num 6 // 0-6Bits, 1-8Bits
+ #define mLVDS2_pair_num 5 // 0-3Pairs, 1-6Pairs
+ #define mLVDS2_msb_first 4
+ #define mLVDS2_PORT_SWAP 3
+ #define mLVDS2_MLSB_SWAP 2
+ #define mLVDS2_PN_SWAP 1
+ #define mLVDS2_en 0
+//`define MLVDS2_CONFIG_HI 8'h75
+//`define MLVDS2_CONFIG_LO 8'h76
+ #define mLVDS2_reset_offset 29 // Bit 31:29
+ #define mLVDS2_reset_length 23 // Bit 28:23
+ #define mLVDS2_config_reserved 20 // Bit 22:20
+ #define mLVDS2_reset_start_bit12 19 // Bit 19
+ #define mLVDS2_data_write_toggle 18
+ #define mLVDS2_data_write_ini 17
+ #define mLVDS2_data_latch_1_toggle 16
+ #define mLVDS2_data_latch_1_ini 15
+ #define mLVDS2_data_latch_0_toggle 14
+ #define mLVDS2_data_latch_0_ini 13
+ #define mLVDS2_reset_1_select 12 // 0 - same as reset_0, 1 - 1 clock delay of reset_0
+ #define mLVDS2_reset_start 0 // Bit 11:0
+//`define MLVDS2_DUAL_GATE_WR_START 8'h77
+// `define mlvds2_dual_gate_wr_start 0 // Bit 12:0
+//`define MLVDS2_DUAL_GATE_WR_END 8'h78
+// `define mlvds2_dual_gate_wr_end 0 // Bit 12:0
+//
+//`define MLVDS2_DUAL_GATE_RD_START 8'h79
+// `define mlvds2_dual_gate_rd_start 0 // Bit 12:0
+//`define MLVDS2_DUAL_GATE_RD_END 8'h7a
+// `define mlvds2_dual_gate_rd_end 0 // Bit 12:0
+//`define MLVDS2_SECOND_RESET_CTL 8'h7b
+// `define mLVDS2_2nd_reset_start 0 // Bit 12:0
+//
+//`define MLVDS2_DUAL_GATE_CTL_HI 8'h7c
+//`define MLVDS2_DUAL_GATE_CTL_LO 8'h7d
+// `define mlvds2_tcon_field_en 24 // Bit 7:0
+// `define mlvds2_dual_gate_reserved 21 // Bit 2:0
+// `define mlvds2_scan_mode_start_line_bit12 20 // Bit 0
+// `define mlvds2_scan_mode_odd 16 // Bit 3:0
+// `define mlvds2_scan_mode_even 12 // Bit 3:0
+// `define mlvds2_scan_mode_start_line 0 // Bit 11:0
+//
+//`define MLVDS2_RESET_CONFIG_HI 8'h7e
+//`define MLVDS2_RESET_CONFIG_LO 8'h7f
+// `define mLVDS2_reset_range_enable 31 // Bit 0
+// `define mLVDS2_reset_range_inv 30 // Bit 0
+// `define mLVDS2_reset_config_res1 29 // Bit 0
+// `define mLVDS2_reset_range_line_0 16 // Bit 11:0
+// `define mLVDS2_reset_config_res3 13 // Bit 2:0
+// `define mLVDS2_reset_range_line_1 0 // Bit 11:0
+//
+//**************************************************************************
+//* Vbyone registers (Note: no MinLVDS in G9tv, share the register)
+//**************************************************************************
+#define VBO_CTRL_L ((0x1960 << 2) + 0xff000000)
+#define VBO_CTRL_H ((0x1961 << 2) + 0xff000000)
+#define VBO_SOFT_RST ((0x1962 << 2) + 0xff000000)
+#define VBO_LANES ((0x1963 << 2) + 0xff000000)
+#define VBO_VIN_CTRL ((0x1964 << 2) + 0xff000000)
+#define VBO_ACT_VSIZE ((0x1965 << 2) + 0xff000000)
+#define VBO_REGION_00 ((0x1966 << 2) + 0xff000000)
+#define VBO_REGION_01 ((0x1967 << 2) + 0xff000000)
+#define VBO_REGION_02 ((0x1968 << 2) + 0xff000000)
+#define VBO_REGION_03 ((0x1969 << 2) + 0xff000000)
+#define VBO_VBK_CTRL_0 ((0x196a << 2) + 0xff000000)
+#define VBO_VBK_CTRL_1 ((0x196b << 2) + 0xff000000)
+#define VBO_HBK_CTRL ((0x196c << 2) + 0xff000000)
+#define VBO_PXL_CTRL ((0x196d << 2) + 0xff000000)
+#define VBO_LANE_SKEW_L ((0x196e << 2) + 0xff000000)
+#define VBO_LANE_SKEW_H ((0x196f << 2) + 0xff000000)
+#define VBO_GCLK_LANE_L ((0x1970 << 2) + 0xff000000)
+#define VBO_GCLK_LANE_H ((0x1971 << 2) + 0xff000000)
+#define VBO_GCLK_MAIN ((0x1972 << 2) + 0xff000000)
+#define VBO_STATUS_L ((0x1973 << 2) + 0xff000000)
+#define VBO_STATUS_H ((0x1974 << 2) + 0xff000000)
+#define VBO_LANE_OUTPUT ((0x1975 << 2) + 0xff000000)
+#define LCD_PORT_SWAP ((0x1976 << 2) + 0xff000000)
+#define VBO_TMCHK_THRD_L ((0x1978 << 2) + 0xff000000)
+#define VBO_TMCHK_THRD_H ((0x1979 << 2) + 0xff000000)
+#define VBO_FSM_HOLDER_L ((0x197a << 2) + 0xff000000)
+#define VBO_FSM_HOLDER_H ((0x197b << 2) + 0xff000000)
+#define VBO_INTR_STATE_CTRL ((0x197c << 2) + 0xff000000)
+#define VBO_INTR_UNMASK ((0x197d << 2) + 0xff000000)
+#define VBO_TMCHK_HSYNC_STATE_L ((0x197e << 2) + 0xff000000)
+#define VBO_TMCHK_HSYNC_STATE_H ((0x197f << 2) + 0xff000000)
+#define VBO_TMCHK_VSYNC_STATE_L ((0x19f4 << 2) + 0xff000000)
+#define VBO_TMCHK_VSYNC_STATE_H ((0x19f5 << 2) + 0xff000000)
+#define VBO_TMCHK_VDE_STATE_L ((0x19f6 << 2) + 0xff000000)
+#define VBO_TMCHK_VDE_STATE_H ((0x19f7 << 2) + 0xff000000)
+#define VBO_INTR_STATE ((0x19f8 << 2) + 0xff000000)
+#define VBO_INFILTER_CTRL ((0x19f9 << 2) + 0xff000000)
+#define VBO_INSGN_CTRL ((0x19fa << 2) + 0xff000000)
+#define VBO_INFILTER_CTRL_H ((0x1977 << 2) + 0xff000000)
+//**************************************************************************
+//* NOTE:: When Programming the Gamma, please turn off the IRQ service *
+//**************************************************************************
+#define GAMMA_CNTL_PORT ((0x1980 << 2) + 0xff000000)
+ #define GAMMA_VCOM_POL 7 //RW
+ #define GAMMA_RVS_OUT 6 //RW
+ #define ADR_RDY 5 //Read Only
+ #define WR_RDY 4 //Read Only
+ #define RD_RDY 3 //Read Only
+ #define GAMMA_TR 2 //RW
+ #define GAMMA_SET 1 //RW
+ #define GAMMA_EN 0 //RW
+#define GAMMA_DATA_PORT ((0x1981 << 2) + 0xff000000)
+#define GAMMA_ADDR_PORT ((0x1982 << 2) + 0xff000000)
+ #define H_RD 12
+ #define H_AUTO_INC 11
+ #define H_SEL_R 10
+ #define H_SEL_G 9
+ #define H_SEL_B 8
+ #define HADR_MSB 7 //7:0
+ #define HADR 0 //7:0
+#define GAMMA_VCOM_HSWITCH_ADDR ((0x1983 << 2) + 0xff000000)
+#define RGB_BASE_ADDR ((0x1985 << 2) + 0xff000000)
+#define RGB_COEFF_ADDR ((0x1986 << 2) + 0xff000000)
+#define POL_CNTL_ADDR ((0x1987 << 2) + 0xff000000)
+ #define DCLK_SEL 14 //FOR DCLK OUTPUT
+ #define TCON_VSYNC_SEL_DVI 11 //FOR RGB format DVI output
+ #define TCON_HSYNC_SEL_DVI 10 //FOR RGB format DVI output
+ #define TCON_DE_SEL_DVI 9 //FOR RGB format DVI output
+ #define CPH3_POL 8
+ #define CPH2_POL 7
+ #define CPH1_POL 6
+ #define TCON_DE_SEL 5
+ #define TCON_VS_SEL 4
+ #define TCON_HS_SEL 3
+ #define DE_POL 2
+ #define VS_POL 1
+ #define HS_POL 0
+#define DITH_CNTL_ADDR ((0x1988 << 2) + 0xff000000)
+ #define DITH10_EN 10
+ #define DITH8_EN 9
+ #define DITH_MD 8
+ #define DITH10_CNTL_MSB 7 //7:4
+ #define DITH10_CNTL 4 //7:4
+ #define DITH8_CNTL_MSB 3 //3:0
+ #define DITH8_CNTL 0 //3:0
+//Bit 1 highlight_en
+//Bit 0 probe_en
+#define GAMMA_PROBE_CTRL ((0x1989 << 2) + 0xff000000)
+//read only
+//Bit [15:0] probe_color[15:0]
+#define GAMMA_PROBE_COLOR_L ((0x198a << 2) + 0xff000000)
+//Read only
+//Bit 15: if true valid probed color
+//Bit [13:0] probe_color[29:16]
+#define GAMMA_PROBE_COLOR_H ((0x198b << 2) + 0xff000000)
+//bit 15:0, 5:6:5 color
+#define GAMMA_PROBE_HL_COLOR ((0x198c << 2) + 0xff000000)
+//12:0 pos_x
+#define GAMMA_PROBE_POS_X ((0x198d << 2) + 0xff000000)
+//12:0 pos_y
+#define GAMMA_PROBE_POS_Y ((0x198e << 2) + 0xff000000)
+#define STH1_HS_ADDR ((0x1990 << 2) + 0xff000000)
+#define STH1_HE_ADDR ((0x1991 << 2) + 0xff000000)
+#define STH1_VS_ADDR ((0x1992 << 2) + 0xff000000)
+#define STH1_VE_ADDR ((0x1993 << 2) + 0xff000000)
+#define STH2_HS_ADDR ((0x1994 << 2) + 0xff000000)
+#define STH2_HE_ADDR ((0x1995 << 2) + 0xff000000)
+#define STH2_VS_ADDR ((0x1996 << 2) + 0xff000000)
+#define STH2_VE_ADDR ((0x1997 << 2) + 0xff000000)
+#define OEH_HS_ADDR ((0x1998 << 2) + 0xff000000)
+#define OEH_HE_ADDR ((0x1999 << 2) + 0xff000000)
+#define OEH_VS_ADDR ((0x199a << 2) + 0xff000000)
+#define OEH_VE_ADDR ((0x199b << 2) + 0xff000000)
+#define VCOM_HSWITCH_ADDR ((0x199c << 2) + 0xff000000)
+#define VCOM_VS_ADDR ((0x199d << 2) + 0xff000000)
+#define VCOM_VE_ADDR ((0x199e << 2) + 0xff000000)
+#define CPV1_HS_ADDR ((0x199f << 2) + 0xff000000)
+#define CPV1_HE_ADDR ((0x19a0 << 2) + 0xff000000)
+#define CPV1_VS_ADDR ((0x19a1 << 2) + 0xff000000)
+#define CPV1_VE_ADDR ((0x19a2 << 2) + 0xff000000)
+#define CPV2_HS_ADDR ((0x19a3 << 2) + 0xff000000)
+#define CPV2_HE_ADDR ((0x19a4 << 2) + 0xff000000)
+#define CPV2_VS_ADDR ((0x19a5 << 2) + 0xff000000)
+#define CPV2_VE_ADDR ((0x19a6 << 2) + 0xff000000)
+#define STV1_HS_ADDR ((0x19a7 << 2) + 0xff000000)
+#define STV1_HE_ADDR ((0x19a8 << 2) + 0xff000000)
+#define STV1_VS_ADDR ((0x19a9 << 2) + 0xff000000)
+#define STV1_VE_ADDR ((0x19aa << 2) + 0xff000000)
+#define STV2_HS_ADDR ((0x19ab << 2) + 0xff000000)
+#define STV2_HE_ADDR ((0x19ac << 2) + 0xff000000)
+#define STV2_VS_ADDR ((0x19ad << 2) + 0xff000000)
+#define STV2_VE_ADDR ((0x19ae << 2) + 0xff000000)
+#define OEV1_HS_ADDR ((0x19af << 2) + 0xff000000)
+#define OEV1_HE_ADDR ((0x19b0 << 2) + 0xff000000)
+#define OEV1_VS_ADDR ((0x19b1 << 2) + 0xff000000)
+#define OEV1_VE_ADDR ((0x19b2 << 2) + 0xff000000)
+#define OEV2_HS_ADDR ((0x19b3 << 2) + 0xff000000)
+#define OEV2_HE_ADDR ((0x19b4 << 2) + 0xff000000)
+#define OEV2_VS_ADDR ((0x19b5 << 2) + 0xff000000)
+#define OEV2_VE_ADDR ((0x19b6 << 2) + 0xff000000)
+#define OEV3_HS_ADDR ((0x19b7 << 2) + 0xff000000)
+#define OEV3_HE_ADDR ((0x19b8 << 2) + 0xff000000)
+#define OEV3_VS_ADDR ((0x19b9 << 2) + 0xff000000)
+#define OEV3_VE_ADDR ((0x19ba << 2) + 0xff000000)
+#define LCD_PWR_ADDR ((0x19bb << 2) + 0xff000000)
+ #define LCD_VDD 5
+ #define LCD_VBL 4
+ #define LCD_GPI_MSB 3
+ #define LCD_GPIO 0
+#define LCD_PWM0_LO_ADDR ((0x19bc << 2) + 0xff000000)
+#define LCD_PWM0_HI_ADDR ((0x19bd << 2) + 0xff000000)
+#define LCD_PWM1_LO_ADDR ((0x19be << 2) + 0xff000000)
+#define LCD_PWM1_HI_ADDR ((0x19bf << 2) + 0xff000000)
+#define INV_CNT_ADDR ((0x19c0 << 2) + 0xff000000)
+ #define INV_EN 4
+ #define INV_CNT_MSB 3
+ #define INV_CNT 0
+#define TCON_MISC_SEL_ADDR ((0x19c1 << 2) + 0xff000000)
+ #define STH2_SEL 12
+ #define STH1_SEL 11
+ #define OEH_SEL 10
+ #define VCOM_SEL 9
+ #define DB_LINE_SW 8
+ #define CPV2_SEL 7
+ #define CPV1_SEL 6
+ #define STV2_SEL 5
+ #define STV1_SEL 4
+ #define OEV_UNITE 3
+ #define OEV3_SEL 2
+ #define OEV2_SEL 1
+ #define OEV1_SEL 0
+#define DUAL_PORT_CNTL_ADDR ((0x19c2 << 2) + 0xff000000)
+ #define OUTPUT_YUV 15
+ #define DUAL_IDF 12 // 14:12
+ #define DUAL_ISF 9 // 11:9
+ #define LCD_ANALOG_SEL_CPH3 8
+ #define LCD_ANALOG_3PHI_CLK_SEL 7
+ #define LCD_LVDS_SEL54 6
+ #define LCD_LVDS_SEL27 5
+ #define LCD_TTL_SEL 4
+ #define DUAL_LVDC_EN 3
+ #define PORT_SWP 2
+ #define RGB_SWP 1
+ #define BIT_SWP 0
+#define MLVDS_CONTROL ((0x19c3 << 2) + 0xff000000)
+ #define mLVDS_RESERVED 15 // 15
+ #define mLVDS_double_pattern 14 // 14
+ #define mLVDS_ins_reset 8 // 13:8 // each channel has one bit
+ #define mLVDS_dual_gate 7
+ #define mLVDS_bit_num 6 // 0-6Bits, 1-8Bits
+ #define mLVDS_pair_num 5 // 0-3Pairs, 1-6Pairs
+ #define mLVDS_msb_first 4
+ #define mLVDS_PORT_SWAP 3
+ #define mLVDS_MLSB_SWAP 2
+ #define mLVDS_PN_SWAP 1
+ #define mLVDS_en 0
+#define MLVDS_RESET_PATTERN_HI ((0x19c4 << 2) + 0xff000000)
+#define MLVDS_RESET_PATTERN_LO ((0x19c5 << 2) + 0xff000000)
+ #define mLVDS_reset_pattern 0 // Bit 47:16
+#define MLVDS_RESET_PATTERN_EXT ((0x19c6 << 2) + 0xff000000)
+ #define mLVDS_reset_pattern_ext 0 // Bit 15:0
+#define MLVDS_CONFIG_HI ((0x19c7 << 2) + 0xff000000)
+#define MLVDS_CONFIG_LO ((0x19c8 << 2) + 0xff000000)
+ #define mLVDS_reset_offset 29 // Bit 31:29
+ #define mLVDS_reset_length 23 // Bit 28:23
+ #define mLVDS_config_reserved 20 // Bit 22:20
+ #define mLVDS_reset_start_bit12 19 // Bit 19
+ #define mLVDS_data_write_toggle 18
+ #define mLVDS_data_write_ini 17
+ #define mLVDS_data_latch_1_toggle 16
+ #define mLVDS_data_latch_1_ini 15
+ #define mLVDS_data_latch_0_toggle 14
+ #define mLVDS_data_latch_0_ini 13
+ #define mLVDS_reset_1_select 12 // 0 - same as reset_0, 1 - 1 clock delay of reset_0
+ #define mLVDS_reset_start 0 // Bit 11:0
+#define TCON_DOUBLE_CTL ((0x19c9 << 2) + 0xff000000)
+ #define tcon_double_ini 8 // Bit 7:0
+ #define tcon_double_inv 0 // Bit 7:0
+#define TCON_PATTERN_HI ((0x19ca << 2) + 0xff000000)
+#define TCON_PATTERN_LO ((0x19cb << 2) + 0xff000000)
+ #define tcon_pattern_loop_data 16 // Bit 15:0
+ #define tcon_pattern_loop_start 12 // Bit 3:0
+ #define tcon_pattern_loop_end 8 // Bit 3:0
+ #define tcon_pattern_enable 0 // Bit 7:0
+#define TCON_CONTROL_HI ((0x19cc << 2) + 0xff000000)
+#define TCON_CONTROL_LO ((0x19cd << 2) + 0xff000000)
+ #define tcon_pclk_enable 26 // Bit 5:0 (enable pclk on TCON channel 7 to 2)
+ #define tcon_pclk_div 24 // Bit 1:0 (control phy clok divide 2,4,6,8)
+ #define tcon_delay 0 // Bit 23:0 (3 bit for each channel)
+#define LVDS_BLANK_DATA_HI ((0x19ce << 2) + 0xff000000)
+#define LVDS_BLANK_DATA_LO ((0x19cf << 2) + 0xff000000)
+ #define LVDS_blank_data_reserved 30 // 31:30
+ #define LVDS_blank_data_r 20 // 29:20
+ #define LVDS_blank_data_g 10 // 19:10
+ #define LVDS_blank_data_b 0 // 9:0
+#define LVDS_PACK_CNTL_ADDR ((0x19d0 << 2) + 0xff000000)
+ #define LVDS_USE_TCON 7
+ #define LVDS_DUAL 6
+ #define PN_SWP 5
+ #define LSB_FIRST 4
+ #define LVDS_RESV 3
+ #define ODD_EVEN_SWP 2
+ #define LVDS_REPACK 0
+// New from M3 :
+// Bit 15:12 -- Enable OFFSET Double Generate(TOCN7-TCON4)
+// Bit 11:0 -- de_hs(old tcon) second offset_hs (new tcon)
+#define DE_HS_ADDR ((0x19d1 << 2) + 0xff000000)
+// New from M3 :
+// Bit 15:12 -- Enable OFFSET Double Generate(TOCN3-TCON0)
+#define DE_HE_ADDR ((0x19d2 << 2) + 0xff000000)
+#define DE_VS_ADDR ((0x19d3 << 2) + 0xff000000)
+#define DE_VE_ADDR ((0x19d4 << 2) + 0xff000000)
+#define HSYNC_HS_ADDR ((0x19d5 << 2) + 0xff000000)
+#define HSYNC_HE_ADDR ((0x19d6 << 2) + 0xff000000)
+#define HSYNC_VS_ADDR ((0x19d7 << 2) + 0xff000000)
+#define HSYNC_VE_ADDR ((0x19d8 << 2) + 0xff000000)
+#define VSYNC_HS_ADDR ((0x19d9 << 2) + 0xff000000)
+#define VSYNC_HE_ADDR ((0x19da << 2) + 0xff000000)
+#define VSYNC_VS_ADDR ((0x19db << 2) + 0xff000000)
+#define VSYNC_VE_ADDR ((0x19dc << 2) + 0xff000000)
+// bit 8 -- vfifo_mcu_enable
+// bit 7 -- halt_vs_de
+// bit 6 -- R8G8B8_format
+// bit 5 -- R6G6B6_format (round to 6 bits)
+// bit 4 -- R5G6B5_format
+// bit 3 -- dac_dith_sel
+// bit 2 -- lcd_mcu_enable_de -- ReadOnly
+// bit 1 -- lcd_mcu_enable_vsync -- ReadOnly
+// bit 0 -- lcd_mcu_enable
+#define LCD_MCU_CTL ((0x19dd << 2) + 0xff000000)
+// ReadOnly
+// R5G6B5 when R5G6B5_format
+// G8R8 when R8G8B8_format
+// G5R10 Other
+#define LCD_MCU_DATA_0 ((0x19de << 2) + 0xff000000)
+// ReadOnly
+// G8B8 when R8G8B8_format
+// G5B10 Other
+#define LCD_MCU_DATA_1 ((0x19df << 2) + 0xff000000)
+// LVDS
+#define LVDS_GEN_CNTL ((0x19e0 << 2) + 0xff000000)
+//`define LVDS_PHY_CNTL0 8'he1
+//`define LVDS_PHY_CNTL1 8'he2
+//`define LVDS_PHY_CNTL2 8'he3
+//`define LVDS_PHY_CNTL3 8'he4
+//`define LVDS_PHY_CNTL4 8'he5
+//`define LVDS_PHY_CNTL5 8'he6
+#define LVDS_SRG_TEST ((0x19e8 << 2) + 0xff000000)
+#define LVDS_BIST_MUX0 ((0x19e9 << 2) + 0xff000000)
+#define LVDS_BIST_MUX1 ((0x19ea << 2) + 0xff000000)
+#define LVDS_BIST_FIXED0 ((0x19eb << 2) + 0xff000000)
+#define LVDS_BIST_FIXED1 ((0x19ec << 2) + 0xff000000)
+#define LVDS_BIST_CNTL0 ((0x19ed << 2) + 0xff000000)
+#define LVDS_CLKB_CLKA ((0x19ee << 2) + 0xff000000)
+#define LVDS_PHY_CLK_CNTL ((0x19ef << 2) + 0xff000000)
+#define LVDS_SER_EN ((0x19f0 << 2) + 0xff000000)
+//`define LVDS_PHY_CNTL6 8'hf1
+//`define LVDS_PHY_CNTL7 8'hf2
+//`define LVDS_PHY_CNTL8 8'hf3
+#define LVDS_CH_SWAP0 ((0x19e1 << 2) + 0xff000000)
+#define LVDS_CH_SWAP1 ((0x19e2 << 2) + 0xff000000)
+#define LVDS_CH_SWAP2 ((0x19e3 << 2) + 0xff000000)
+//`define MLVDS_CLK_CTL0_HI 8'hf4
+//`define MLVDS_CLK_CTL0_LO 8'hf5
+// `define mlvds_clk_pattern_reserved 31 // Bit 31
+// `define mpclk_dly 28 // Bit 2:0
+// `define mpclk_div 26 // Bit 1:0 (control phy clok divide 2,4,6,8)
+// `define use_mpclk 25 // Bit 0
+// `define mlvds_clk_half_delay 24 // Bit 0
+// `define mlvds_clk_pattern 0 // Bit 23:0
+//`define MLVDS_DUAL_GATE_WR_START 8'hf6
+// `define mlvds_dual_gate_wr_start 0 // Bit 12:0
+//`define MLVDS_DUAL_GATE_WR_END 8'hf7
+// `define mlvds_dual_gate_wr_end 0 // Bit 12:0
+//
+//`define MLVDS_DUAL_GATE_RD_START 8'hf8
+// `define mlvds_dual_gate_rd_start 0 // Bit 12:0
+//`define MLVDS_DUAL_GATE_RD_END 8'hf9
+// `define mlvds_dual_gate_rd_end 0 // Bit 12:0
+//`define MLVDS_SECOND_RESET_CTL 8'hfa
+// `define mLVDS_2nd_reset_start 0 // Bit 12:0
+//
+#define MLVDS_DUAL_GATE_CTL_HI ((0x19fb << 2) + 0xff000000)
+#define MLVDS_DUAL_GATE_CTL_LO ((0x19fc << 2) + 0xff000000)
+// `define mlvds_tcon_field_en 24 // Bit 7:0
+// `define mlvds_dual_gate_reserved 21 // Bit 2:0
+// `define mlvds_scan_mode_start_line_bit12 20 // Bit 0
+// `define mlvds_scan_mode_odd 16 // Bit 3:0
+// `define mlvds_scan_mode_even 12 // Bit 3:0
+// `define mlvds_scan_mode_start_line 0 // Bit 11:0
+//
+//`define MLVDS_RESET_CONFIG_HI 8'hfd
+//`define MLVDS_RESET_CONFIG_LO 8'hfe
+// `define mLVDS_reset_range_enable 31 // Bit 0
+// `define mLVDS_reset_range_inv 30 // Bit 0
+// `define mLVDS_reset_config_res1 29 // Bit 0
+// `define mLVDS_reset_range_line_0 16 // Bit 11:0
+// `define mLVDS_reset_config_res3 13 // Bit 2:0
+// `define mLVDS_reset_range_line_1 0 // Bit 11:0
+//===============================================================
+//LCD DRIVER BASE END
+//===============================================================
+//
+// Closing file: disp_if_regs.h
+//
+//===========================================================================
+//===========================================================================
+//
+// Reading file: vregs_clk2.h
+//
+//===========================================================================
+// Video Interface Registers 0xa00 - 0xaff
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VIU_VCBUS_BASE = 0x1a
+// -----------------------------------------------
+#define VIU_ADDR_START ((0x1a00 << 2) + 0xff000000)
+#define VIU_ADDR_END ((0x1aff << 2) + 0xff000000)
+//`define TRACE_REG 8'ff
+//------------------------------------------------------------------------------
+// VIU top-level registers 0x00-0x0f
+//------------------------------------------------------------------------------
+// Bit 0 RW, osd1_reset
+// Bit 1 RW, osd2_reset
+// Bit 2 RW, vd1_reset
+// Bit 3 RW, vd1_fmt_reset
+// Bit 4 RW, vd2_reset
+// Bit 5 RW, vd2_fmt_reset
+// Bit 6 RW, di_dsr1to2_reset
+// Bit 7 RW, vpp_reset
+// Bit 8 RW, di_if1_reset
+// Bit 9 RW, di_if1_fmt_reset
+// Bit 10 RW, di_inp_reset
+// Bit 11 RW, di_inp_fmt_reset
+// Bit 12 RW, di_mem_reset
+// Bit 13 RW, di_mem_fmt_reset
+// Bit 14 RW, di_nr_wr_mif_reset
+// Bit 15 RW, dein_wr_mif_reset
+// Bit 16 RW, di_chan2_mif_reset
+// Bit 17 RW, di_mtn_wr_mif_reset
+// Bit 18 RW, di_mtn_rd_mif_reset
+// Bit 19 RW, di_mad_reset
+// Bit 20 RW, vdin0_reset
+// Bit 21 RW, vdin1_reset
+// Bit 22 RW, nrin_mux_reset
+// Bit 23 RW, vdin0_wr_reset
+// Bit 24 RW, vdin1_wr_reset
+// Bit 25 RW, reserved
+// Bit 26 RW, d2d3_reset
+// Bit 27 RW, di_cont_wr_mif_reset
+// Bit 28 RW, di_cont_rd_mif_reset
+#define VIU_SW_RESET ((0x1a01 << 2) + 0xff000000)
+#define VIU_SW_RESET0 ((0x1a02 << 2) + 0xff000000)
+// Bit 0 RW, software reset for mcvecrd_mif
+// Bit 1 RW, software reset for mcinfowr_mif
+// Bit 2 RW, software reset for mcinford_mif
+#define VIU_SECURE_REG ((0x1a04 << 2) + 0xff000000)
+// Bit 0 RW, dolby core1_tv secure w and r
+// Bit 1 RW, dolby core2 secure w and r
+// Bit 2 RW, dolby core3 secure w and r
+// Bit 3 RW, for osd1 secure read
+// Bit 4 RW, for osd2 secure read
+#define DOLBY_INT_STAT ((0x1a05 << 2) + 0xff000000)
+// todo
+//bit 15:12 osdbld_gclk_ctrl 3:2 regclk ctrl 1:0 blending clk control
+//bit 8 if true, vsync interrup is generate only field == 0
+//bit 7:0 fix_disable
+#define VIU_MISC_CTRL0 ((0x1a06 << 2) + 0xff000000)
+#define VIU_MISC_CTRL1 ((0x1a07 << 2) + 0xff000000)
+//Bit 31:7 Reserved
+//Bit 6:4 reg_cfg_err_clr
+//Bit 3 Reserved
+//Bit 2:0 reg_cfg_done
+#define VIU_SECURE_DUMMY ((0x1a08 << 2) + 0xff000000)
+#define VIU_SECURE_ST_RO ((0x1a09 << 2) + 0xff000000)
+// Bit 31:30 vdin0 dout splitter, bit 0 turns on vdin0 to old path, bit 1 turns on vdin0 to d2d3_intf vdin0 input path
+// Bit 29:28 vdin1 dout splitter, bit 0 turns on vdin1 to old path, bit 1 turns on vdin1 to d2d3_intf vdin1 input path
+// Bit 27:26 NR write dout splitter, bit 0 turns on NR write to old path, bit 1 turns on NR WR to d2d3_intf NR WR input path
+// Bit 23 if true, turn on clk_d2d3_reg (register clock)
+// Bit 22 if true, turn on clk_d2d3
+// Bit 21 reg_v1_go_line
+// Bit 20 reg_v1_go_field
+// Bit 19 reg_v0_go_field
+// Bit 18:16 v1_gofld_sel, 000: display go_field/go_line, 001: DI pre_frame_rst/go_line, 010: vdin0 go_field/go_line,
+//011: vdin1 go_field/go_line, otherwise: force go_field by reg_v1_go_field(bit20), force go_line by reg_v1_go_line(bit21)
+// Bit 15:13 v0_gofld_sel, 000: display go_field, 001: DI pre_frame_rst, 010: vdin0 go_field, 011: vdin1 go_field, otherwise: force go_field by
+// reg_v0_go_field(bit19)
+// Bit 12:6 hole_lines for d2d3 depth read interface
+// Bit 5:4 d2d3_v1_sel, 2'b01: video display read interface(DI or vd1 fomart output), 2'b10: scale output, otherwise nothing as v1
+// Bit 3 use_vdin_eol, if true, use vdin eol as the v0_eol, otherwise using length to get the v0_eol
+// Bit 2:0 d2d3_v0_sel 001: vdin0, 010: vdin1, 011: NRW, 100: video display read interface(DI or vd1 fomart output), 101: vpp scale output
+//
+// `define D2D3_INTF_CTRL0 8'h09
+#define VD1_AFBCD0_MISC_CTRL ((0x1a0a << 2) + 0xff000000)
+#define VD2_AFBCD1_MISC_CTRL ((0x1a0b << 2) + 0xff000000)
+#define DOLBY_PATH_CTRL ((0x1a0c << 2) + 0xff000000)
+#define WR_BACK_MISC_CTRL ((0x1a0d << 2) + 0xff000000)
+#define OSD_PATH_MISC_CTRL ((0x1a0e << 2) + 0xff000000)
+#define MALI_AFBCD_TOP_CTRL ((0x1a0f << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// OSD1 registers 0x10-0x2f
+//------------------------------------------------------------------------------
+// Bit 31 Reserved
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// 0=use gated clock for low power.
+// Bit 29 R, test_rd_dsr
+// Bit 28 R, osd_done
+// Bit 27:24 R, osd_blk_mode
+// Bit 23:22 R, osd_blk_ptr
+// Bit 21 R, osd_enable
+//
+// Bit 20:12 RW, global_alpha
+// Bit 11 RW, test_rd_en
+// Bit 10: 9 Reserved for control signals
+// Bit 8: 5 RW, ctrl_mtch_y
+// Bit 4 RW, ctrl_422to444
+// Bit 3: 0 RW, osd_blk_enable. Bit 0 to enable block 0: 1=enable, 0=disable;
+// Bit 1 to enable block 1, and so on.
+#define VIU_OSD1_CTRL_STAT ((0x1a10 << 2) + 0xff000000)
+// Bit 31:26 Reserved
+// Bit 25:16 R, fifo_count
+// Bit 15 RW, osd_dpath_sel 0-osd1 mif 1-vpu mali afbcd
+// Bit 14 RW, replaced_alpha_en
+// Bit 13: 6 RW, replaced_alpha
+// Bit 5: 4 RW, hold_fifo_lines[6:5]
+// Bit 3 RW, rgb2yuv_full_range
+// Bit 2 RW, alpha_9b_mode
+// Bit 1 RW, reserved
+// Bit 0 RW, color_expand_mode
+#define VIU_OSD1_CTRL_STAT2 ((0x1a2d << 2) + 0xff000000)
+// Bit 31: 9 Reserved
+// Bit 8 RW, 0 = Write LUT, 1 = Read LUT
+// Bit 7: 0 RW, lut_addr
+#define VIU_OSD1_COLOR_ADDR ((0x1a11 << 2) + 0xff000000)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define VIU_OSD1_COLOR ((0x1a12 << 2) + 0xff000000)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define VIU_OSD1_TCOLOR_AG0 ((0x1a17 << 2) + 0xff000000)
+#define VIU_OSD1_TCOLOR_AG1 ((0x1a18 << 2) + 0xff000000)
+#define VIU_OSD1_TCOLOR_AG2 ((0x1a19 << 2) + 0xff000000)
+#define VIU_OSD1_TCOLOR_AG3 ((0x1a1a << 2) + 0xff000000)
+// Bit 31:30 Reserved
+// Bit 29 RW, y_rev: 0=normal read, 1=reverse read in Y direction
+// Bit 28 RW, x_rev: 0=normal read, 1=reverse read in X direction
+// Bit 27:24 Reserved
+// Bit 23:16 RW, tbl_addr
+// Bit 15 RW, little_endian: 0=big endian, 1=little endian
+// Bit 14 RW, rpt_y
+// Bit 13:12 RW, interp_ctrl. 0x=No interpolation; 10=Interpolate with previous
+// pixel; 11=Interpolate with the average value
+// between previous and next pixel.
+// Bit 11: 8 RW, osd_blk_mode
+// Bit 7 RW, rgb_en
+// Bit 6 RW, tc_alpha_en
+// Bit 5: 2 RW, color_matrix
+// Bit 1 RW, interlace_en
+// Bit 0 RW, interlace_sel_odd
+#define VIU_OSD1_BLK0_CFG_W0 ((0x1a1b << 2) + 0xff000000)
+#define VIU_OSD1_BLK1_CFG_W0 ((0x1a1f << 2) + 0xff000000)
+#define VIU_OSD1_BLK2_CFG_W0 ((0x1a23 << 2) + 0xff000000)
+#define VIU_OSD1_BLK3_CFG_W0 ((0x1a27 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, x_end
+// Bit 15:13 Reserved
+// Bit 12: 0 RW, x_start
+#define VIU_OSD1_BLK0_CFG_W1 ((0x1a1c << 2) + 0xff000000)
+#define VIU_OSD1_BLK1_CFG_W1 ((0x1a20 << 2) + 0xff000000)
+#define VIU_OSD1_BLK2_CFG_W1 ((0x1a24 << 2) + 0xff000000)
+#define VIU_OSD1_BLK3_CFG_W1 ((0x1a28 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, y_end
+// Bit 15:13 Reserved
+// Bit 12: 0 RW, y_start
+#define VIU_OSD1_BLK0_CFG_W2 ((0x1a1d << 2) + 0xff000000)
+#define VIU_OSD1_BLK1_CFG_W2 ((0x1a21 << 2) + 0xff000000)
+#define VIU_OSD1_BLK2_CFG_W2 ((0x1a25 << 2) + 0xff000000)
+#define VIU_OSD1_BLK3_CFG_W2 ((0x1a29 << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, h_end
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, h_start
+#define VIU_OSD1_BLK0_CFG_W3 ((0x1a1e << 2) + 0xff000000)
+#define VIU_OSD1_BLK1_CFG_W3 ((0x1a22 << 2) + 0xff000000)
+#define VIU_OSD1_BLK2_CFG_W3 ((0x1a26 << 2) + 0xff000000)
+#define VIU_OSD1_BLK3_CFG_W3 ((0x1a2a << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, v_end
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, v_start
+#define VIU_OSD1_BLK0_CFG_W4 ((0x1a13 << 2) + 0xff000000)
+#define VIU_OSD1_BLK1_CFG_W4 ((0x1a14 << 2) + 0xff000000)
+#define VIU_OSD1_BLK2_CFG_W4 ((0x1a15 << 2) + 0xff000000)
+#define VIU_OSD1_BLK3_CFG_W4 ((0x1a16 << 2) + 0xff000000)
+// Bit 31 RW, burst_len_sel[2] of [2:0]
+// Bit 30 RW, byte_swap: In addition to endian control, further define
+// whether to swap upper and lower byte within a 16-bit mem word.
+// 0=No swap; 1=Swap data[15:0] to be {data[7:0], data[15:8]}
+// Bit 29 RW, div_swap : swap the 2 64bits words in 128 bit word
+// Bit 28:24 RW, fifo_lim : when osd fifo is small than the fifo_lim*16, closed the rq port of osd_rd_mif
+// Bit 23:22 RW, fifo_ctrl: 00 : for 1 word in 1 burst , 01 : for 2words in 1burst, 10: for 4words in 1burst, 11: reserved
+// Bit 21:20 R, fifo_st. 0=IDLE, 1=FILL, 2=ABORT
+// Bit 19 R, fifo_overflow
+// Bit 18:12 RW, fifo_depth_val, max value=64: set actual fifo depth to fifo_depth_val*8.
+// Bit 11:10 RW, burst_len_sel[1:0] of [2:0]. 0=24(default), 1=32, 2=48, 3=64, 4=96, 5=128.
+// Bit 9: 5 RW, hold_fifo_lines[4:0]
+// Bit 4 RW, clear_err: one pulse to clear fifo_overflow
+// Bit 3 RW, fifo_sync_rst
+// Bit 2: 1 RW, endian
+// Bit 0 RW, urgent
+#define VIU_OSD1_FIFO_CTRL_STAT ((0x1a2b << 2) + 0xff000000)
+// Bit 31:24 R, Y or R
+// Bit 23:16 R, Cb or G
+// Bit 15: 8 R, Cr or B
+// Bit 7: 0 R, Output Alpha[8:1]
+#define VIU_OSD1_TEST_RDDATA ((0x1a2c << 2) + 0xff000000)
+// Bit 15 RW, prot_en: 1=Borrow PROT's FIFO storage, either for rotate or non-rotate.
+// Bit 12: 0 RW, effective FIFO size when prot_en=1.
+#define VIU_OSD1_PROT_CTRL ((0x1a2e << 2) + 0xff000000)
+////add for OSD1/2 mali_unpack
+#define VIU_OSD1_MALI_UNPACK_CTRL ((0x1a2f << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// OSD2 registers 0x30-0x4f 0x64 -0x67
+//------------------------------------------------------------------------------
+// Bit 31 Reserved
+// Bit 30 RW, enable_free_clk: 1=use free-running clock to drive logics;
+// 0=use gated clock for low power.
+// Bit 29 R, test_rd_dsr
+// Bit 28 R, osd_done
+// Bit 27:24 R, osd_blk_mode
+// Bit 23:22 R, osd_blk_ptr
+// Bit 21 R, osd_enable
+//
+// Bit 20:12 RW, global_alpha
+// Bit 11 RW, test_rd_en
+// Bit 10 RW, hl2_en
+// Bit 9 RW, hl1_en
+// Bit 8: 5 RW, ctrl_mtch_y
+// Bit 4 RW, ctrl_422to444
+// Bit 3: 0 RW, osd_blk_enable. Bit 0 to enable block 0: 1=enable, 0=disable;
+// Bit 1 to enable block 1, and so on.
+#define VIU_OSD2_CTRL_STAT ((0x1a30 << 2) + 0xff000000)
+// Bit 31:26 Reserved
+// Bit 25:16 R, fifo_count
+// Bit 15 Reserved
+// Bit 14 RW, replaced_alpha_en
+// Bit 13: 6 RW, replaced_alpha
+// Bit 5: 4 RW, hold_fifo_lines[6:5]
+// Bit 3 RW, rgb2yuv_full_range
+// Bit 2 RW, alpha_9b_mode
+// Bit 1 RW, reserved
+// Bit 0 RW, color_expand_mode
+#define VIU_OSD2_CTRL_STAT2 ((0x1a4d << 2) + 0xff000000)
+// Bit 31: 9 Reserved
+// Bit 8 RW, 0 = Write LUT, 1 = Read LUT
+// Bit 7: 0 RW, lut_addr
+#define VIU_OSD2_COLOR_ADDR ((0x1a31 << 2) + 0xff000000)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define VIU_OSD2_COLOR ((0x1a32 << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, hl[1-2]_h/v_start
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, hl[1-2]_h/v_end
+#define VIU_OSD2_HL1_H_START_END ((0x1a33 << 2) + 0xff000000)
+#define VIU_OSD2_HL1_V_START_END ((0x1a34 << 2) + 0xff000000)
+#define VIU_OSD2_HL2_H_START_END ((0x1a35 << 2) + 0xff000000)
+#define VIU_OSD2_HL2_V_START_END ((0x1a36 << 2) + 0xff000000)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define VIU_OSD2_TCOLOR_AG0 ((0x1a37 << 2) + 0xff000000)
+#define VIU_OSD2_TCOLOR_AG1 ((0x1a38 << 2) + 0xff000000)
+#define VIU_OSD2_TCOLOR_AG2 ((0x1a39 << 2) + 0xff000000)
+#define VIU_OSD2_TCOLOR_AG3 ((0x1a3a << 2) + 0xff000000)
+// Bit 31:24 Reserved
+// Bit 23:16 RW, tbl_addr
+// Bit 15 RW, little_endian: 0=big endian, 1=little endian
+// Bit 14 RW, rpt_y
+// Bit 13:12 RW, interp_ctrl. 0x=No interpolation; 10=Interpolate with previous
+// pixel; 11=Interpolate with the average value
+// between previous and next pixel.
+// Bit 11: 8 RW, osd_blk_mode
+// Bit 7 RW, rgb_en
+// Bit 6 RW, tc_alpha_en
+// Bit 5: 2 RW, color_matrix
+// Bit 1 RW, interlace_en
+// Bit 0 RW, interlace_sel_odd
+#define VIU_OSD2_BLK0_CFG_W0 ((0x1a3b << 2) + 0xff000000)
+#define VIU_OSD2_BLK1_CFG_W0 ((0x1a3f << 2) + 0xff000000)
+#define VIU_OSD2_BLK2_CFG_W0 ((0x1a43 << 2) + 0xff000000)
+#define VIU_OSD2_BLK3_CFG_W0 ((0x1a47 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, x_end
+// Bit 15:13 Reserved
+// Bit 12: 0 RW, x_start
+#define VIU_OSD2_BLK0_CFG_W1 ((0x1a3c << 2) + 0xff000000)
+#define VIU_OSD2_BLK1_CFG_W1 ((0x1a40 << 2) + 0xff000000)
+#define VIU_OSD2_BLK2_CFG_W1 ((0x1a44 << 2) + 0xff000000)
+#define VIU_OSD2_BLK3_CFG_W1 ((0x1a48 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, y_end
+// Bit 15:13 Reserved
+// Bit 12: 0 RW, y_start
+#define VIU_OSD2_BLK0_CFG_W2 ((0x1a3d << 2) + 0xff000000)
+#define VIU_OSD2_BLK1_CFG_W2 ((0x1a41 << 2) + 0xff000000)
+#define VIU_OSD2_BLK2_CFG_W2 ((0x1a45 << 2) + 0xff000000)
+#define VIU_OSD2_BLK3_CFG_W2 ((0x1a49 << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, h_end
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, h_start
+#define VIU_OSD2_BLK0_CFG_W3 ((0x1a3e << 2) + 0xff000000)
+#define VIU_OSD2_BLK1_CFG_W3 ((0x1a42 << 2) + 0xff000000)
+#define VIU_OSD2_BLK2_CFG_W3 ((0x1a46 << 2) + 0xff000000)
+#define VIU_OSD2_BLK3_CFG_W3 ((0x1a4a << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, v_end
+// Bit 15:12 Reserved
+// Bit 11: 0 RW, v_start
+#define VIU_OSD2_BLK0_CFG_W4 ((0x1a64 << 2) + 0xff000000)
+#define VIU_OSD2_BLK1_CFG_W4 ((0x1a65 << 2) + 0xff000000)
+#define VIU_OSD2_BLK2_CFG_W4 ((0x1a66 << 2) + 0xff000000)
+#define VIU_OSD2_BLK3_CFG_W4 ((0x1a67 << 2) + 0xff000000)
+// Bit 31 RW, burst_len_sel[2] of [2:0]
+// Bit 30 RW, byte_swap: In addition to endian control, further define
+// whether to swap upper and lower byte within a 16-bit mem word.
+// 0=No swap; 1=Swap data[15:0] to be {data[7:0], data[15:8]}
+// Bit 29 RW, div_swap : swap the 2 64bits words in 128 bit word
+// Bit 28:24 RW, fifo_lim : when osd fifo is small than the fifo_lim*16, closed the rq port of osd_rd_mif
+// Bit 23:22 RW, fifo_ctrl: 00 : for 1 word in 1 burst , 01 : for 2words in 1burst, 10: for 4words in 1burst, 11: reserved
+// Bit 21:20 R, fifo_st. 0=IDLE, 1=FILL, 2=ABORT
+// Bit 19 R, fifo_overflow
+//
+// Bit 18:12 RW, fifo_depth_val, max value=64: set actual fifo depth to fifo_depth_val*8.
+// Bit 11:10 RW, burst_len_sel[1:0] of [2:0]. 0=24(default), 1=32, 2=48, 3=64, 4=96, 5=128.
+// Bit 9: 5 RW, hold_fifo_lines[4:0]
+// Bit 4 RW, clear_err: one pulse to clear fifo_overflow
+// Bit 3 RW, fifo_sync_rst
+// Bit 2: 1 RW, endian
+// Bit 0 RW, urgent
+#define VIU_OSD2_FIFO_CTRL_STAT ((0x1a4b << 2) + 0xff000000)
+// Bit 31:24 R, Y or R
+// Bit 23:16 R, Cb or G
+// Bit 15: 8 R, Cr or B
+// Bit 7: 0 R, Output Alpha[8:1]
+#define VIU_OSD2_TEST_RDDATA ((0x1a4c << 2) + 0xff000000)
+// Bit 15 RW, prot_en: 1=Borrow PROT's FIFO storage, either for rotate or non-rotate.
+// Bit 12: 0 RW, effective FIFO size when prot_en=1.
+#define VIU_OSD2_PROT_CTRL ((0x1a4e << 2) + 0xff000000)
+#define VIU_GCLK_CTRL ((0x1a4f << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// VIU registers 0x50 -0x5f
+//------------------------------------------------------------------------------
+#define VIU_DATA_SEC ((0x1a50 << 2) + 0xff000000)
+#define VIU_FRM_CTRL ((0x1a51 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29 viu0_frm_start unsigned,default = 0 //pulse
+//Bit 28:20 reserved
+//Bit 19:17 viu0_frm_phs_mode unsigned,default = 0
+//Bit 16 viu0_frm_start_sel unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 viu0_hold_line_num unsigned,default = 4
+#define VIU_RDMIF_DEPTH ((0x1a52 << 2) + 0xff000000)
+#define MALI_AFBCD1_TOP_CTRL ((0x1a55 << 2) + 0xff000000)
+#define MALI_AFBCD2_TOP_CTRL ((0x1a56 << 2) + 0xff000000)
+#define VD1_HDR_IN_SIZE ((0x1a57 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 vd1_hdr_in_vsize unsigned,default = 1920 ,//vsize of hdr
+//Bit 15:13 reserved
+//Bit 12:0 vd1_hdr_in_hsize unsigned,default = 1080 ,//hsize of hdr
+#define VD2_HDR_IN_SIZE ((0x1a58 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 vd2_hdr_in_vsize unsigned,default = 1920 ,//vsize of hdr
+//Bit 15:13 reserved
+//Bit 12:0 vd2_hdr_in_hsize unsigned,default = 1080 ,//hsize of hdr
+#define VD3_HDR_IN_SIZE ((0x1a59 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 vd3_hdr_in_vsize unsigned,default = 1920 ,//vsize of hdr
+//Bit 15:13 reserved
+//Bit 12:0 vd3_hdr_in_hsize unsigned,default = 1080 ,//hsize of hdr
+#define OSD1_HDR_IN_SIZE ((0x1a5a << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 osd1_hdr_in_vsize unsigned,default = 1920 ,//vsize of hdr
+//Bit 15:13 reserved
+//Bit 12:0 osd1_hdr_in_hsize unsigned,default = 1080 ,//hsize of hdr
+#define OSD2_HDR_IN_SIZE ((0x1a5b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 osd2_hdr_in_vsize unsigned,default = 1920 ,//vsize of hdr
+//Bit 15:13 reserved
+//Bit 12:0 osd2_hdr_in_hsize unsigned,default = 1080 ,//hsize of hdr
+#define OSD3_HDR_IN_SIZE ((0x1a5c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 osd3_hdr_in_vsize unsigned,default = 1920 ,//vsize of hdr
+//Bit 15:13 reserved
+//Bit 12:0 osd3_hdr_in_hsize unsigned,default = 1080 ,//hsize of hdr
+#define OSD4_HDR_IN_SIZE ((0x1a5d << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 osd4_hdr_in_vsize unsigned,default = 1920 ,//vsize of hdr
+//Bit 15:13 reserved
+//Bit 12:0 osd4_hdr_in_hsize unsigned,default = 1080 ,//hsize of hdr
+#define OSD_BLEND_DIN_CTRL ((0x1a5e << 2) + 0xff000000)
+//Bit 31:4 reserved
+//Bit 3 :0 osd_bld_din_sel unsigned,default = 0xf
+#define DOLBY_PATH_SWAP_CTRL1 ((0x1a70 << 2) + 0xff000000)
+//Bit 31:0 reserved
+#define DOLBY_PATH_SWAP_CTRL2 ((0x1a71 << 2) + 0xff000000)
+//Bit 31:0 reserved
+#define VD_PATH_MISC_CTRL ((0x1a7a << 2) + 0xff000000)
+//Bit 31:0 reserved
+#define VD1_PPS_DUMMY_DATA ((0x1a80 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:0 vd_pps_dummy_data
+#define VD2_PPS_DUMMY_DATA ((0x1a81 << 2) + 0xff000000)
+//Bit 31:0 reserved
+//Bit 23:0 vd_pps_dummy_data
+#define VD3_PPS_DUMMY_DATA ((0x1a82 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:0 vd_pps_dummy_data
+#define VPP_VD1_DSC_CTRL ((0x1a83 << 2) + 0xff000000)
+//Bit 31:0 vd1_in_dsc_ctrl unsigned,default = 0
+#define VPP_VD2_DSC_CTRL ((0x1a84 << 2) + 0xff000000)
+//Bit 31:0 vd2_in_dsc_ctrl unsigned,default = 0
+#define VPP_VD3_DSC_CTRL ((0x1a85 << 2) + 0xff000000)
+//Bit 31:0 vd3_in_dsc_ctrl unsigned,default = 0
+#define VPP_SC_HOLD_LINES ((0x1a88 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:24 osd4_path_hold_lines unsigned,default = 0 ,//osd4 proc path hold lines
+//Bit 23:20 osd3_path_hold_lines unsigned,default = 0 ,//osd3 proc path hold lines
+//Bit 19:16 osd2_path_hold_lines unsigned,default = 0 ,//osd2 proc path hold lines
+//Bit 15:12 osd1_path_hold_lines unsigned,default = 0 ,//osd1 proc path hold lines
+//Bit 11:8 vd3_path_hold_lines unsigned,default = 0 ,//vd3 proc path hold lines
+//Bit 7 :4 vd2_path_hold_lines unsigned,default = 0 ,//vd2 proc path hold lines
+//Bit 3 :0 vd1_path_hold_lines unsigned,default = 0 ,//vd1 proc path hold lines
+#define PATH_START_SEL ((0x1a8a << 2) + 0xff000000)
+//Bit 31:14 reserved
+//Bit 13:12 osd3_path_start_sel unsigned,default = 2 ,//0:use vpp0_go_field 1:use vpp1_go_field 2:use vpp2_go_field
+//Bit 11:10 reserved
+//Bit 9 :8 osd2_path_start_sel unsigned,default = 1 ,//0:use vpp0_go_field 1:use vpp1_go_field 2:use vpp2_go_field
+//Bit 7 :6 reserved
+//Bit 5 :4 vd3_path_start_sel unsigned,default = 2 ,//0:use vpp0_go_field 1:use vpp1_go_field 2:use vpp2_go_field
+//Bit 3 :2 reserved
+//Bit 1 :0 vd2_path_start_sel unsigned,default = 1 ,//0:use vpp0_go_field 1:use vpp1_go_field 2:use vpp2_go_field
+#define VPP_OSD_SCALE_CTRL ((0x1a8c << 2) + 0xff000000)
+//Bit 31:15 reserved
+//Bit 14 osd4_sc_cmp_byp unsigned,default = 0 ,//0:open data_convert 1:bypass data_convert
+//Bit 13 osd4_sc_cmp_mode unsigned,default = 1 ,//0:{2'd0,data} 1:{data,2'd0}
+//Bit 12 osd4_sc_path_sel unsigned,default = 1 ,//0:after HDR 1:before osd_blend
+//Bit 11 reserved
+//Bit 10 osd3_sc_cmp_byp unsigned,default = 0 ,//0:open data_convert 1:bypass data_convert
+//Bit 9 osd3_sc_cmp_mode unsigned,default = 1 ,//0:{2'd0,data} 1:{data,2'd0}
+//Bit 8 osd3_sc_path_sel unsigned,default = 1 ,//0:after HDR 1:before osd_blend
+//Bit 7 reserved
+//Bit 6 osd2_sc_cmp_byp unsigned,default = 0 ,//0:open data_convert 1:bypass data_convert
+//Bit 5 osd2_sc_cmp_mode unsigned,default = 1 ,//0:{2'd0,data} 1:{data,2'd0}
+//Bit 4 osd2_sc_path_sel unsigned,default = 1 ,//0:after HDR 1:before osd_blend
+//Bit 3 reserved
+//Bit 2 osd1_sc_cmp_byp unsigned,default = 0 ,//0:open data_convert 1:bypass data_convert
+//Bit 1 osd1_sc_cmp_mode unsigned,default = 1 ,//0:{2'd0,data} 1:{data,2'd0}
+//Bit 0 osd1_sc_path_sel unsigned,default = 0 ,//0:after HDR 1:before osd_blend
+#define VIU1_FRM_CTRL ((0x1a8d << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29 viu1_frm_start unsigned,default = 0 //pulse
+//Bit 28:20 reserved
+//Bit 19:17 viu1_frm_phs_mode unsigned,default = 0
+//Bit 16 viu1_frm_start_sel unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 viu1_hold_line_num unsigned,default = 4
+#define VIU2_FRM_CTRL ((0x1a8e << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29 viu2_frm_start unsigned,default = 0 //pulse
+//Bit 28:20 reserved
+//Bit 19:17 viu2_frm_phs_mode unsigned,default = 0
+//Bit 16 viu2_frm_start_sel unsigned,default = 0
+//Bit 15:13 reserved
+//Bit 12:0 viu2_hold_line_num unsigned,default = 4
+#define VPU_SEC_INT_STAT ((0x1a8f << 2) + 0xff000000)
+//Bit 31:3 reserved
+//Bit 2 vpp0_sec_int_stat unsigned,default = 0 ,// vppx in sec error int status
+//Bit 1 vpp1_sec_int_stat unsigned,default = 0 ,// vppx in sec error int status
+//Bit 0 vpp2_sec_int_stat unsigned,default = 0 ,// vppx in sec error int status
+//------------------------------------------------------------------------------
+// OSD1_MATRIX registers 0x90 -0x9f
+//------------------------------------------------------------------------------
+//Bit 7, highlight_en
+//Bit 6 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix
+//Bit 5:4 probe_sel, 00: select matrix 0, 01: select matrix 1, otherwise select nothing
+//Bit 3:2, matrix coef idx selection, 00: select mat0, 01: select mat1, otherwise slect nothing
+//Bit 1 mat1 conversion matrix enable
+//Bit 0 mat0 conversion matrix enable
+#define VIU_OSD1_MATRIX_CTRL ((0x1a90 << 2) + 0xff000000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define VIU_OSD1_MATRIX_COEF00_01 ((0x1a91 << 2) + 0xff000000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define VIU_OSD1_MATRIX_COEF02_10 ((0x1a92 << 2) + 0xff000000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define VIU_OSD1_MATRIX_COEF11_12 ((0x1a93 << 2) + 0xff000000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define VIU_OSD1_MATRIX_COEF20_21 ((0x1a94 << 2) + 0xff000000)
+//Bit 31:30 mat_clmod
+//Bit 18:16 mat_convrs
+//Bit 12:0 mat_coef42
+#define VIU_OSD1_MATRIX_COLMOD_COEF42 ((0x1a95 << 2) + 0xff000000)
+//Bit 26:16 offset0
+//Bit 10:0 offset1
+#define VIU_OSD1_MATRIX_OFFSET0_1 ((0x1a96 << 2) + 0xff000000)
+//Bit 10:0 offset2
+#define VIU_OSD1_MATRIX_OFFSET2 ((0x1a97 << 2) + 0xff000000)
+//Bit 26:16 pre_offset0
+//Bit 10:0 pre_offset1
+#define VIU_OSD1_MATRIX_PRE_OFFSET0_1 ((0x1a98 << 2) + 0xff000000)
+//Bit 10:0 pre_offset2
+#define VIU_OSD1_MATRIX_PRE_OFFSET2 ((0x1a99 << 2) + 0xff000000)
+//Read only
+//Bit 29:20 component 0
+//Bit 19:10 component 1
+//Bit 9:0 component 2
+#define VIU_OSD1_MATRIX_PROBE_COLOR ((0x1a9a << 2) + 0xff000000)
+//Bit 23:16 component 0
+//Bit 15:8 component 1
+//Bit 7:0 component 2
+#define VIU_OSD1_MATRIX_HL_COLOR ((0x1a9b << 2) + 0xff000000)
+//28:16 probe x, postion
+//12:0 probe y, position
+#define VIU_OSD1_MATRIX_PROBE_POS ((0x1a9c << 2) + 0xff000000)
+//Bit 28:16 coef22
+//Bit 12:0 coef30
+#define VIU_OSD1_MATRIX_COEF22_30 ((0x1a9d << 2) + 0xff000000)
+//Bit 28:16 coef31
+//Bit 12:0 coef32
+#define VIU_OSD1_MATRIX_COEF31_32 ((0x1a9e << 2) + 0xff000000)
+//Bit 28:16 coef40
+//Bit 12:0 coef41
+#define VIU_OSD1_MATRIX_COEF40_41 ((0x1a9f << 2) + 0xff000000)
+#define VIU_OSD1_OETF_3X3_OFST_0 ((0x1aa0 << 2) + 0xff000000)
+#define VIU_OSD1_OETF_3X3_OFST_1 ((0x1aa1 << 2) + 0xff000000)
+//`define OSD_BLENDO_H_START_END 8'ha9 //'d1919
+//OSD blending output horizontal start and end
+//Bit 28:16 start
+//Bit 12:0 end
+//`define OSD_BLENDO_V_START_END 8'haa //'d1079
+//OSD blending output vertical start and end
+//Bit 28:16 start
+//Bit 12:0 end
+//`define OSD_BLEND_GEN_CTRL0 8'hab //'h2000
+//Bit 31:23 const_out_alpha
+//Bit 22:14 const_op_alpha
+//Bit 13 if true, OSD2 foreground otherwise OSD1 foreground
+//Bit 12 OSD BLENDing enable
+//Bit 9:8 alpha_op_sel 00: output alpha use osd1_alpha, 01: use osd2_alpha, else use const_out_alpha
+//Bit 5:4 color_op_sel 00: use osd1_alpha, 01: use osd2_alpha, else use const_op_alpha
+//Bit 1 OSD2 enable
+//Bit 0 OSD1 enable
+//`define OSD_BLEND_GEN_CTRL1 8'hac //'h80000
+//Bit 31 osd1_alpha_premult, if true, osd1 alpha is premultipiled
+//Bit 30 osd2_alpha_premult, if true, osd2 alpha is premultipiled
+//Bit 23:16 osd blending hold lines
+//Bit 13:0 osd blending h_size
+//`define OSD_BLEND_DUMMY_DATA 8'had //0
+//Bit 29:20 Y/R
+//Bit 19:10 CB/G
+//Bit 9:0 Cr/B
+//`define OSD_BLEND_CURRENT_XY 8'hae //read only
+//Bit 28:16 current_x
+//Bit 12:0 current_y
+//Bit 7, highlight_en
+//Bit 6 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix
+//Bit 5:4 probe_sel, 00: select matrix 0, 01: select matrix 1, otherwise select nothing
+//Bit 3:2, matrix coef idx selection, 00: select mat0, 01: select mat1, otherwise slect nothing
+//Bit 1 mat1 conversion matrix enable
+//Bit 0 mat0 conversion matrix enable
+//`define VIU_OSD2_MATRIX_CTRL 8'hb0
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define VIU_OSD2_MATRIX_COEF00_01 ((0x1ab1 << 2) + 0xff000000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define VIU_OSD2_MATRIX_COEF02_10 ((0x1ab2 << 2) + 0xff000000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define VIU_OSD2_MATRIX_COEF11_12 ((0x1ab3 << 2) + 0xff000000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define VIU_OSD2_MATRIX_COEF20_21 ((0x1ab4 << 2) + 0xff000000)
+#define VIU_OSD2_MATRIX_COEF22 ((0x1ab5 << 2) + 0xff000000)
+//Bit 26:16 offset0
+//Bit 10:0 offset1
+#define VIU_OSD2_MATRIX_OFFSET0_1 ((0x1ab6 << 2) + 0xff000000)
+//Bit 10:0 offset2
+#define VIU_OSD2_MATRIX_OFFSET2 ((0x1ab7 << 2) + 0xff000000)
+//Bit 26:16 pre_offset0
+//Bit 10:0 pre_offset1
+#define VIU_OSD2_MATRIX_PRE_OFFSET0_1 ((0x1ab8 << 2) + 0xff000000)
+//Bit 10:0 pre_offset2
+#define VIU_OSD2_MATRIX_PRE_OFFSET2 ((0x1ab9 << 2) + 0xff000000)
+//Read only
+//Bit 29:20 component 0
+//Bit 19:10 component 1
+//Bit 9:0 component 2
+#define VIU_OSD2_MATRIX_PROBE_COLOR ((0x1aba << 2) + 0xff000000)
+//Bit 23:16 component 0
+//Bit 15:8 component 1
+//Bit 7:0 component 2
+#define VIU_OSD2_MATRIX_HL_COLOR ((0x1abb << 2) + 0xff000000)
+//28:16 probe x, postion
+//12:0 probe y, position
+#define VIU_OSD2_MATRIX_PROBE_POS ((0x1abc << 2) + 0xff000000)
+#define VIU_OSD2_MALI_UNPACK_CTRL ((0x1abd << 2) + 0xff000000)
+//`define VIU_OSD2_MATRIX_HL_COLOR 8'hbe
+//`define VIU_OSD2_MATRIX_PROBE_POS 8'hbf
+// //todo add comment
+#define LDIM_STTS_GCLK_CTRL0 ((0x1ac0 << 2) + 0xff000000)
+#define LDIM_STTS_CTRL0 ((0x1ac1 << 2) + 0xff000000)
+#define LDIM_STTS_WIDTHM1_HEIGHTM1 ((0x1ac2 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_COEF00_01 ((0x1ac3 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_COEF02_10 ((0x1ac4 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_COEF11_12 ((0x1ac5 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_COEF20_21 ((0x1ac6 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_COEF22 ((0x1ac7 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_OFFSET0_1 ((0x1ac8 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_OFFSET2 ((0x1ac9 << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_PRE_OFFSET0_1 ((0x1aca << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_PRE_OFFSET2 ((0x1acb << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_HL_COLOR ((0x1acc << 2) + 0xff000000)
+#define LDIM_STTS_MATRIX_PROBE_POS ((0x1acd << 2) + 0xff000000)
+//
+// //read only
+#define LDIM_STTS_MATRIX_PROBE_COLOR ((0x1ace << 2) + 0xff000000)
+//
+// //Bit 31, local dimming statistic enable
+// //Bit 29, 1: output region histogram 16bit 0:output region histogram 20bit
+// //Bit 28, eol enable
+// //Bit 27:25, vertical line overlap number for max finding
+// //Bit 24:22, horizontal pixel overlap number, 0: 17 pix, 1: 9 pix, 2: 5 pix, 3: 3 pix, 4: 0 pix
+// //Bit 20, 1,2,1 low pass filter enable before max/hist statistic
+// //Bit 19:16, region H/V position index, refer to VDIN_LDIM_STTS_HIST_SET_REGION
+// //Bit 15:14, 1: region read index auto increase per block read finished to VDIN_LDIM_STTS_HIST_READ_REGION
+// // 2: region read index auto increase per read finished to VDIN_LDIM_STTS_HIST_READ_REGION
+// // 0/3: disable read index self increase
+// //Bit 13:8, region read sub index, which mux the hist & max-finding result to cbus port, refer to LDIM_STTS_HIST_READ_REGION
+// //Bit 6:0, region read index
+#define LDIM_STTS_HIST_REGION_IDX ((0x1ad0 << 2) + 0xff000000)
+//Bit 28:0, if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h0: read/write hvstart0
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h1: read/write hend01
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h2: read/write vend01
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h3: read/write hend23
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h4: read/write vend23
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h5: read/write hend45
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h6: read/write vend45
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'd7: read/write hend67
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h8: read/write vend67
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'h9: read/write hend89
+// if VDIN_LDIM_STTS_HIST_REGION_IDX[19:16] == 5'ha: read/write vend89
+// //hvstart0, Bit 28:16 row0 vstart, Bit 12:0 col0 hstart
+// //hend01, Bit 28:16 col1 hend, Bit 12:0 col0 hend
+// //vend01, Bit 28:16 row1 vend, Bit 12:0 row0 vend
+// //hend23, Bit 28:16 col3 hend, Bit 12:0 col2 hend
+// //vend23, Bit 28:16 row3 vend, Bit 12:0 row2 vend
+// //hend45, Bit 28:16 col5 hend, Bit 12:0 col4 hend
+// //vend45, Bit 28:16 row5 vend, Bit 12:0 row4 vend
+// //hend67, Bit 28:16 col7 hend, Bit 12:0 col6 hend
+// //vend67, Bit 28:16 row7 vend, Bit 12:0 row6 vend
+// //hend89, Bit 28:16 col9 hend, Bit 12:0 col8 hend
+// //vend89, Bit 28:16 row9 vend, Bit 12:0 row8 vend
+#define LDIM_STTS_HIST_SET_REGION ((0x1ad1 << 2) + 0xff000000)
+//
+// //if LDIM_STTS_HIST_REGION_IDX[29] == 0, that is output hist with 20bit data.
+// //if LDIM_STTS_HIST_REGION_IDX[21] == 0, that is output 16hist bins in comp 0.
+// //output sequence as rd_sub_idx from 0~47: {max_comp2, comp0_hist0}, {max_comp1, comp0_hist1}, {max_comp0, comp0_hist2},
+// // comp0_hist3 ... comp2_hist16
+// //if LDIM_STTS_HIST_REGION_IDX[29] == 1, that is output hist with 16bit data.
+// //if LDIM_STTS_HIST_REGION_IDX[21] == 0, that is output 16hist bins in comp 0.
+// //output sequence as rd_sub_idx from 0~47: {max_comp2, max_comp1, max_comp0}, comp0_hist0, comp0_hist1, comp0_hist2
+// // comp0_hist3 ... comp2_hist16
+// //if LDIM_STTS_HIST_REGION_IDX[29] == 0, that is output hist with 20bit data.
+// //if LDIM_STTS_HIST_REGION_IDX[21] == 1, that is output 32hist bins in comp 0.
+// //output sequence as rd_sub_idx from 0~47: {max_comp2, max_comp1, max_comp0}, comp0_hist0, comp0_hist1, comp0_hist2
+// // comp0_hist3 ...comp0_hist31 ... comp1_hist16
+//
+#define LDIM_STTS_HIST_READ_REGION ((0x1ad2 << 2) + 0xff000000)
+#define LDIM_STTS_HIST_START_RD_REGION ((0x1ad3 << 2) + 0xff000000)
+#define LDIM_STTS_PCTL_TH ((0x1aaf << 2) + 0xff000000)
+//Bit 31:27 for all [31] for all eotf enable,[30] for matrix3x3 enable, [29:27] for eotf_ch0~3
+//Bit 17:6 for clock gating
+//Bit 5:4 pscale_mode ch2
+//Bit 3:2 pscale_mode ch1
+//Bit 1:0 pscale_mode ch0
+#define VIU_OSD1_EOTF_CTL ((0x1ad4 << 2) + 0xff000000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define VIU_OSD1_EOTF_COEF00_01 ((0x1ad5 << 2) + 0xff000000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define VIU_OSD1_EOTF_COEF02_10 ((0x1ad6 << 2) + 0xff000000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define VIU_OSD1_EOTF_COEF11_12 ((0x1ad7 << 2) + 0xff000000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define VIU_OSD1_EOTF_COEF20_21 ((0x1ad8 << 2) + 0xff000000)
+//Bit 28:16 coef22
+//Bit 2:0 coef_rs
+#define VIU_OSD1_EOTF_COEF22_RS ((0x1ad9 << 2) + 0xff000000)
+#define VIU_OSD1_EOTF_LUT_ADDR_PORT ((0x1ada << 2) + 0xff000000)
+#define VIU_OSD1_EOTF_LUT_DATA_PORT ((0x1adb << 2) + 0xff000000)
+//Bit 31:29 for OETF ch0~ch2
+//Bit 21:12 for clock gating
+//Bit 11:8 for oetf_scl_ch2
+//Bit 7:4 for oetf_scl_ch1
+//Bit 3:0 for oetf_scl_ch0
+#define VIU_OSD1_OETF_CTL ((0x1adc << 2) + 0xff000000)
+#define VIU_OSD1_OETF_LUT_ADDR_PORT ((0x1add << 2) + 0xff000000)
+#define VIU_OSD1_OETF_LUT_DATA_PORT ((0x1ade << 2) + 0xff000000)
+//can use 8'hdf 8'hcf
+#define VIU_OSD1_DIMM_CTRL ((0x1adf << 2) + 0xff000000)
+#define VIU_OSD2_DIMM_CTRL ((0x1acf << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// OSD1_MATRIX registers 0xe0 -0xfe
+//------------------------------------------------------------------------------
+//the segment of afbc dec is 8'he0-8'hfe
+//`define AFBC_DEC_OFFSET 8'he0
+//
+// Reading file: afbc_dec_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+//// reg
+////===============================////
+#define AFBC_ENABLE ((0x1ae0 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:23, reg_gclk_ctrl_core unsigned, default = 0
+//Bit 22, reg_fmt_size_sw_mode unsigned, default = 0, 0:hw mode 1:sw mode for format size
+//Bit 21, reg_addr_link_en unsigned, default = 1, 1:enable
+//Bit 20, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb
+//Bit 19, reg_dos_uncomp_mode unsigned , default = 0
+//Bit 18:16, soft_rst unsigned , default = 4
+//Bit 15:14, reserved
+//Bit 13:12, ddr_blk_size unsigned , default = 1
+//Bit 11:9, cmd_blk_size unsigend , default = 3
+//Bit 8, dec_enable unsigned , default = 0
+//Bit 7:2, reserved
+//Bit 1, head_len_sel unsigned , default = 1
+//Bit 0, dec_frm_start unsigned , default = 0
+#define AFBC_MODE ((0x1ae1 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29, ddr_sz_mode uns, default = 0 , 0: fixed block ddr size 1 : unfixed block ddr size;
+//Bit 28, blk_mem_mode uns, default = 0 , 0: fixed 16x128 size; 1 : fixed 12x128 size
+//Bit 27:26, rev_mode uns, default = 0 , reverse mode
+//Bit 25:24, mif_urgent uns, default = 3 , info mif and data mif urgent
+//Bit 23, reserved
+//Bit 22:16, hold_line_num uns, default = 4 ,
+//Bit 15:14, burst_len uns, default = 2, 0: burst1 1:burst2 2:burst4
+//Bit 13:8, compbits_yuv uns, default = 0 ,
+// bit 1:0,: y component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+// bit 3:2,: u component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+// bit 5:4,: v component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+//Bit 7:6, vert_skip_y uns, default = 0 , luma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 5:4, horz_skip_y uns, default = 0 , luma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 3:2, vert_skip_uv uns, default = 0 , chroma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 1:0, horz_skip_uv uns, default = 0 , chroma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+#define AFBC_SIZE_IN ((0x1ae2 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hsize_in uns, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_in uns, default = 1080 , pic vert size in unit: pixel
+#define AFBC_DEC_DEF_COLOR ((0x1ae3 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:20, def_color_y uns, default = 255, afbc dec y default setting value
+//Bit 19:10, def_color_u uns, default = 128, afbc dec u default setting value
+//Bit 9: 0, def_color_v uns, default = 128, afbc dec v default setting value
+#define AFBC_CONV_CTRL ((0x1ae4 << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13:12, fmt_mode uns, default = 2, 0:yuv444 1:yuv422 2:yuv420
+//Bit 11: 0, conv_lbuf_len uns, default = 256, unit=16 pixel need to set = 2^n
+#define AFBC_LBUF_DEPTH ((0x1ae5 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, dec_lbuf_depth uns, default = 128; // unit= 8 pixel
+//Bit 15:12, reserved
+//Bit 11:0, mif_lbuf_depth uns, default = 128;
+#define AFBC_HEAD_BADDR ((0x1ae6 << 2) + 0xff000000)
+//Bit 31:0, mif_info_baddr uns, default = 32'h0;
+#define AFBC_BODY_BADDR ((0x1ae7 << 2) + 0xff000000)
+//Bit 31:0, mif_data_baddr uns, default = 32'h00010000;
+#define AFBC_SIZE_OUT ((0x1ae8 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, hsize_out uns, default = 1920 ; // unit: 1 pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_out uns, default = 1080 ; // unit: 1 pixel
+#define AFBC_OUT_YSCOPE ((0x1ae9 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, out_vert_bgn uns, default = 0 ; // unit: 1 pixel
+//Bit 15:13, reserved
+//Bit 12:0, out_vert_end uns, default = 1079 ; // unit: 1 pixel
+#define AFBC_STAT ((0x1aea << 2) + 0xff000000)
+//Bit 31:0, ro_dbg_top_info uns,
+#define AFBC_VD_CFMT_CTRL ((0x1aeb << 2) + 0xff000000)
+//Bit 31 cfmt_gclk_bit_dis uns, default = 0 ; // it true, disable clock, otherwise enable clock
+//Bit 30 cfmt_soft_rst_bit uns, default = 0 ; // soft rst bit
+//Bit 29 reserved
+//Bit 28 chfmt_rpt_pix uns, default = 0 ; // if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
+//Bit 27:24 chfmt_ini_phase uns, default = 0 ; // horizontal formatter initial phase
+//Bit 23 chfmt_rpt_p0_en uns, default = 0 ; // horizontal formatter repeat pixel 0 enable
+//Bit 22:21 chfmt_yc_ratio uns, default = 0 ; // horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
+//Bit 20 chfmt_en uns, default = 0 ; // horizontal formatter enable
+//Bit 19 cvfmt_phase0_always_en uns, default = 0 ; //if true, always use phase0 while vertical formater, meaning always
+// repeat data, no interpolation
+//Bit 18 cvfmt_rpt_last_dis uns, default = 0 ; //if true, disable vertical formatter chroma repeat last line
+//Bit 17 cvfmt_phase0_nrpt_en uns, default = 0 ; //veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable
+//Bit 16 cvfmt_rpt_line0_en uns, default = 0 ; //veritcal formatter repeat line 0 enable
+//Bit 15:12 cvfmt_skip_line_num uns, default = 0 ; //vertical formatter skip line num at the beginning
+//Bit 11:8 cvfmt_ini_phase uns, default = 0 ; //vertical formatter initial phase
+//Bit 7:1 cvfmt_phase_step uns, default = 0 ; //vertical formatter phase step (3.4)
+//Bit 0 cvfmt_en uns, default = 0 ; //vertical formatter enable
+#define AFBC_VD_CFMT_W ((0x1aec << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 chfmt_w uns, default = 0 ;horizontal formatter width
+//Bit 15:13 reserved
+//Bit 12:0 cvfmt_w uns, default = 0 ;vertical formatter width
+#define AFBC_MIF_HOR_SCOPE ((0x1aed << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, mif_blk_bgn_h uns, default = 0 ; // unit: 32 pixel/block hor
+//Bit 15:10, reserved
+//Bit 9: 0, mif_blk_end_h uns, default = 59 ; // unit: 32 pixel/block hor
+#define AFBC_MIF_VER_SCOPE ((0x1aee << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, mif_blk_bgn_v uns, default = 0 ; // unit: 32 pixel/block ver
+//Bit 15:12, reserved
+//Bit 11: 0, mif_blk_end_v uns, default = 269; // unit: 32 pixel/block ver
+#define AFBC_PIXEL_HOR_SCOPE ((0x1aef << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, dec_pixel_bgn_h uns, default = 0 ; // unit: pixel
+//Bit 15:13, reserved
+//Bit 12: 0, dec_pixel_end_h uns, default = 1919 ; // unit: pixel
+#define AFBC_PIXEL_VER_SCOPE ((0x1af0 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, dec_pixel_bgn_v uns, default = 0 ; // unit: pixel
+//Bit 15:13, reserved
+//Bit 12: 0, dec_pixel_end_v uns, default = 1079 ; // unit: pixel
+#define AFBC_VD_CFMT_H ((0x1af1 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12:0 cfmt_h uns, default = 142 ; //vertical formatter height
+#define AFBCDEC_IQUANT_ENABLE ((0x1af2 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_quant_expand_en_1 //unsigned, RW, enable for quantization value expansion
+//Bit 10 reg_quant_expand_en_0 //unsigned, RW, enable for quantization value expansion
+//Bit 9: 8 reg_bcleav_ofst //signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1;
+//Bit 7: 5 reserved
+//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy
+//Bit 3: 1 reserved
+//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy
+#define AFBCDEC_IQUANT_LUT_1 ((0x1af3 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDEC_IQUANT_LUT_2 ((0x1af4 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDEC_IQUANT_LUT_3 ((0x1af5 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDEC_IQUANT_LUT_4 ((0x1af6 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: afbc_dec_regs.h
+//
+//
+// Closing file: vregs_clk2.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VENC0A_VCBUS_BASE = 0x1b
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: venc_regs.h
+//
+//===========================================================================
+// Video Interface Registers 0xa00 - 0xbff
+//===========================================================================
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 0 -- vfifo2vd_en
+#define ENCP_VFIFO2VD_CTL ((0x1b58 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCP_VFIFO2VD_PIXEL_START ((0x1b59 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCP_VFIFO2VD_PIXEL_END ((0x1b5a << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCP_VFIFO2VD_LINE_TOP_START ((0x1b5b << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCP_VFIFO2VD_LINE_TOP_END ((0x1b5c << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCP_VFIFO2VD_LINE_BOT_START ((0x1b5d << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCP_VFIFO2VD_LINE_BOT_END ((0x1b5e << 2) + 0xff000000)
+// Route the hsync and vsync signals round the chip. There are three
+// sources and users of these signals: VIU, internal video encoder, and
+// the pins on the chip. Some muxing is still being done in the VIU. It
+// was not moved to the venc module so that the same exact VIU code could
+// be used both in Twister and Twister2000.
+// Bit 2: venc_sync_source (1=>pins, 0=>viu)
+// Bit 1: viu_sync_source (1=>pins, 0=>venc)
+// Bit 0: vpins_sync_source (1=>venc, 0=>viu)
+#define VENC_SYNC_ROUTE ((0x1b60 << 2) + 0xff000000)
+ // encoder address space is assigned
+ // to the video encoder interface status
+ // register
+#define VENC_VIDEO_EXSRC ((0x1b61 << 2) + 0xff000000)
+#define VENC_DVI_SETTING ((0x1b62 << 2) + 0xff000000)
+#define VENC_C656_CTRL ((0x1b63 << 2) + 0xff000000)
+#define VENC_UPSAMPLE_CTRL0 ((0x1b64 << 2) + 0xff000000)
+#define VENC_UPSAMPLE_CTRL1 ((0x1b65 << 2) + 0xff000000)
+#define VENC_UPSAMPLE_CTRL2 ((0x1b66 << 2) + 0xff000000)
+// Invert control for tcon output
+// bit[15:14] -- vsync, hsync,
+// bit[13:0] -- oev3, oev2, cpv2, cph3, cph2, cph1, oeh, vcom, stv2, stv1, cpv1, oev1, sth1, sth2
+#define TCON_INVERT_CTL ((0x1b67 << 2) + 0xff000000)
+#define VENC_VIDEO_PROG_MODE ((0x1b68 << 2) + 0xff000000)
+//---- Venc pixel/line info
+#define VENC_ENCI_LINE ((0x1b69 << 2) + 0xff000000)
+#define VENC_ENCI_PIXEL ((0x1b6a << 2) + 0xff000000)
+#define VENC_ENCP_LINE ((0x1b6b << 2) + 0xff000000)
+#define VENC_ENCP_PIXEL ((0x1b6c << 2) + 0xff000000)
+//---- Status
+#define VENC_STATA ((0x1b6d << 2) + 0xff000000)
+//---- Interrupt setting
+#define VENC_INTCTRL ((0x1b6e << 2) + 0xff000000)
+#define VENC_INTFLAG ((0x1b6f << 2) + 0xff000000)
+//--------- Video test configuration
+#define VENC_VIDEO_TST_EN ((0x1b70 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_MDSEL ((0x1b71 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_Y ((0x1b72 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_CB ((0x1b73 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_CR ((0x1b74 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_CLRBAR_STRT ((0x1b75 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_CLRBAR_WIDTH ((0x1b76 << 2) + 0xff000000)
+#define VENC_VIDEO_TST_VDCNT_STSET ((0x1b77 << 2) + 0xff000000)
+//----- Video dac setting
+#define VENC_VDAC_DACSEL0 ((0x1b78 << 2) + 0xff000000)
+#define VENC_VDAC_DACSEL1 ((0x1b79 << 2) + 0xff000000)
+#define VENC_VDAC_DACSEL2 ((0x1b7a << 2) + 0xff000000)
+#define VENC_VDAC_DACSEL3 ((0x1b7b << 2) + 0xff000000)
+#define VENC_VDAC_DACSEL4 ((0x1b7c << 2) + 0xff000000)
+#define VENC_VDAC_DACSEL5 ((0x1b7d << 2) + 0xff000000)
+#define VENC_VDAC_SETTING ((0x1b7e << 2) + 0xff000000)
+#define VENC_VDAC_TST_VAL ((0x1b7f << 2) + 0xff000000)
+#define VENC_VDAC_DAC0_GAINCTRL ((0x1bf0 << 2) + 0xff000000)
+#define VENC_VDAC_DAC0_OFFSET ((0x1bf1 << 2) + 0xff000000)
+#define VENC_VDAC_DAC1_GAINCTRL ((0x1bf2 << 2) + 0xff000000)
+#define VENC_VDAC_DAC1_OFFSET ((0x1bf3 << 2) + 0xff000000)
+#define VENC_VDAC_DAC2_GAINCTRL ((0x1bf4 << 2) + 0xff000000)
+#define VENC_VDAC_DAC2_OFFSET ((0x1bf5 << 2) + 0xff000000)
+#define VENC_VDAC_DAC3_GAINCTRL ((0x1bf6 << 2) + 0xff000000)
+#define VENC_VDAC_DAC3_OFFSET ((0x1bf7 << 2) + 0xff000000)
+#define VENC_VDAC_DAC4_GAINCTRL ((0x1bf8 << 2) + 0xff000000)
+#define VENC_VDAC_DAC4_OFFSET ((0x1bf9 << 2) + 0xff000000)
+#define VENC_VDAC_DAC5_GAINCTRL ((0x1bfa << 2) + 0xff000000)
+#define VENC_VDAC_DAC5_OFFSET ((0x1bfb << 2) + 0xff000000)
+#define VENC_VDAC_FIFO_CTRL ((0x1bfc << 2) + 0xff000000)
+#define ENCL_TCON_INVERT_CTL ((0x1bfd << 2) + 0xff000000)
+//
+// Closing file: venc_regs.h
+//
+//
+// Reading file: enc480p_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+// Video Encoder 480p Registers 0xb80 - 0xbef
+//===========================================================================
+//-------- Video basic setting
+#define ENCP_VIDEO_EN ((0x1b80 << 2) + 0xff000000)
+#define ENCP_VIDEO_SYNC_MODE ((0x1b81 << 2) + 0xff000000)
+#define ENCP_MACV_EN ((0x1b82 << 2) + 0xff000000)
+#define ENCP_VIDEO_Y_SCL ((0x1b83 << 2) + 0xff000000)
+#define ENCP_VIDEO_PB_SCL ((0x1b84 << 2) + 0xff000000)
+#define ENCP_VIDEO_PR_SCL ((0x1b85 << 2) + 0xff000000)
+#define ENCP_VIDEO_SYNC_SCL ((0x1b86 << 2) + 0xff000000)
+#define ENCP_VIDEO_MACV_SCL ((0x1b87 << 2) + 0xff000000)
+#define ENCP_VIDEO_Y_OFFST ((0x1b88 << 2) + 0xff000000)
+#define ENCP_VIDEO_PB_OFFST ((0x1b89 << 2) + 0xff000000)
+#define ENCP_VIDEO_PR_OFFST ((0x1b8a << 2) + 0xff000000)
+#define ENCP_VIDEO_SYNC_OFFST ((0x1b8b << 2) + 0xff000000)
+#define ENCP_VIDEO_MACV_OFFST ((0x1b8c << 2) + 0xff000000)
+//----- Video mode
+#define ENCP_VIDEO_MODE ((0x1b8d << 2) + 0xff000000)
+#define ENCP_VIDEO_MODE_ADV ((0x1b8e << 2) + 0xff000000)
+//--------------- Debug pins
+#define ENCP_DBG_PX_RST ((0x1b90 << 2) + 0xff000000)
+#define ENCP_DBG_LN_RST ((0x1b91 << 2) + 0xff000000)
+#define ENCP_DBG_PX_INT ((0x1b92 << 2) + 0xff000000)
+#define ENCP_DBG_LN_INT ((0x1b93 << 2) + 0xff000000)
+//----------- Video Advanced setting
+#define ENCP_VIDEO_YFP1_HTIME ((0x1b94 << 2) + 0xff000000)
+#define ENCP_VIDEO_YFP2_HTIME ((0x1b95 << 2) + 0xff000000)
+#define ENCP_VIDEO_YC_DLY ((0x1b96 << 2) + 0xff000000)
+#define ENCP_VIDEO_MAX_PXCNT ((0x1b97 << 2) + 0xff000000)
+#define ENCP_VIDEO_HSPULS_BEGIN ((0x1b98 << 2) + 0xff000000)
+#define ENCP_VIDEO_HSPULS_END ((0x1b99 << 2) + 0xff000000)
+#define ENCP_VIDEO_HSPULS_SWITCH ((0x1b9a << 2) + 0xff000000)
+#define ENCP_VIDEO_VSPULS_BEGIN ((0x1b9b << 2) + 0xff000000)
+#define ENCP_VIDEO_VSPULS_END ((0x1b9c << 2) + 0xff000000)
+#define ENCP_VIDEO_VSPULS_BLINE ((0x1b9d << 2) + 0xff000000)
+#define ENCP_VIDEO_VSPULS_ELINE ((0x1b9e << 2) + 0xff000000)
+#define ENCP_VIDEO_EQPULS_BEGIN ((0x1b9f << 2) + 0xff000000)
+#define ENCP_VIDEO_EQPULS_END ((0x1ba0 << 2) + 0xff000000)
+#define ENCP_VIDEO_EQPULS_BLINE ((0x1ba1 << 2) + 0xff000000)
+#define ENCP_VIDEO_EQPULS_ELINE ((0x1ba2 << 2) + 0xff000000)
+#define ENCP_VIDEO_HAVON_END ((0x1ba3 << 2) + 0xff000000)
+#define ENCP_VIDEO_HAVON_BEGIN ((0x1ba4 << 2) + 0xff000000)
+#define ENCP_VIDEO_VAVON_ELINE ((0x1baf << 2) + 0xff000000)
+#define ENCP_VIDEO_VAVON_BLINE ((0x1ba6 << 2) + 0xff000000)
+#define ENCP_VIDEO_HSO_BEGIN ((0x1ba7 << 2) + 0xff000000)
+#define ENCP_VIDEO_HSO_END ((0x1ba8 << 2) + 0xff000000)
+#define ENCP_VIDEO_VSO_BEGIN ((0x1ba9 << 2) + 0xff000000)
+#define ENCP_VIDEO_VSO_END ((0x1baa << 2) + 0xff000000)
+#define ENCP_VIDEO_VSO_BLINE ((0x1bab << 2) + 0xff000000)
+#define ENCP_VIDEO_VSO_ELINE ((0x1bac << 2) + 0xff000000)
+#define ENCP_VIDEO_SYNC_WAVE_CURVE ((0x1bad << 2) + 0xff000000)
+#define ENCP_VIDEO_MAX_LNCNT ((0x1bae << 2) + 0xff000000)
+#define ENCP_VIDEO_SY_VAL ((0x1bb0 << 2) + 0xff000000)
+#define ENCP_VIDEO_SY2_VAL ((0x1bb1 << 2) + 0xff000000)
+#define ENCP_VIDEO_BLANKY_VAL ((0x1bb2 << 2) + 0xff000000)
+#define ENCP_VIDEO_BLANKPB_VAL ((0x1bb3 << 2) + 0xff000000)
+#define ENCP_VIDEO_BLANKPR_VAL ((0x1bb4 << 2) + 0xff000000)
+#define ENCP_VIDEO_HOFFST ((0x1bb5 << 2) + 0xff000000)
+#define ENCP_VIDEO_VOFFST ((0x1bb6 << 2) + 0xff000000)
+#define ENCP_VIDEO_RGB_CTRL ((0x1bb7 << 2) + 0xff000000)
+#define ENCP_VIDEO_FILT_CTRL ((0x1bb8 << 2) + 0xff000000)
+#define ENCP_VIDEO_OFLD_VPEQ_OFST ((0x1bb9 << 2) + 0xff000000)
+#define ENCP_VIDEO_OFLD_VOAV_OFST ((0x1bba << 2) + 0xff000000)
+#define ENCP_VIDEO_MATRIX_CB ((0x1bbb << 2) + 0xff000000)
+#define ENCP_VIDEO_MATRIX_CR ((0x1bbc << 2) + 0xff000000)
+#define ENCP_VIDEO_RGBIN_CTRL ((0x1bbd << 2) + 0xff000000)
+//------------------Macrovision advanced setting
+#define ENCP_MACV_BLANKY_VAL ((0x1bc0 << 2) + 0xff000000)
+#define ENCP_MACV_MAXY_VAL ((0x1bc1 << 2) + 0xff000000)
+#define ENCP_MACV_1ST_PSSYNC_STRT ((0x1bc2 << 2) + 0xff000000)
+#define ENCP_MACV_PSSYNC_STRT ((0x1bc3 << 2) + 0xff000000)
+#define ENCP_MACV_AGC_STRT ((0x1bc4 << 2) + 0xff000000)
+#define ENCP_MACV_AGC_END ((0x1bc5 << 2) + 0xff000000)
+#define ENCP_MACV_WAVE_END ((0x1bc6 << 2) + 0xff000000)
+#define ENCP_MACV_STRTLINE ((0x1bc7 << 2) + 0xff000000)
+#define ENCP_MACV_ENDLINE ((0x1bc8 << 2) + 0xff000000)
+#define ENCP_MACV_TS_CNT_MAX_L ((0x1bc9 << 2) + 0xff000000)
+#define ENCP_MACV_TS_CNT_MAX_H ((0x1bca << 2) + 0xff000000)
+#define ENCP_MACV_TIME_DOWN ((0x1bcb << 2) + 0xff000000)
+#define ENCP_MACV_TIME_LO ((0x1bcc << 2) + 0xff000000)
+#define ENCP_MACV_TIME_UP ((0x1bcd << 2) + 0xff000000)
+#define ENCP_MACV_TIME_RST ((0x1bce << 2) + 0xff000000)
+//---------------- VBI control -------------------
+#define ENCP_VBI_CTRL ((0x1bd0 << 2) + 0xff000000)
+#define ENCP_VBI_SETTING ((0x1bd1 << 2) + 0xff000000)
+#define ENCP_VBI_BEGIN ((0x1bd2 << 2) + 0xff000000)
+#define ENCP_VBI_WIDTH ((0x1bd3 << 2) + 0xff000000)
+#define ENCP_VBI_HVAL ((0x1bd4 << 2) + 0xff000000)
+#define ENCP_VBI_DATA0 ((0x1bd5 << 2) + 0xff000000)
+#define ENCP_VBI_DATA1 ((0x1bd6 << 2) + 0xff000000)
+//----------------C656 OUT Control------------- Grant
+#define C656_HS_ST ((0x1be0 << 2) + 0xff000000)
+#define C656_HS_ED ((0x1be1 << 2) + 0xff000000)
+#define C656_VS_LNST_E ((0x1be2 << 2) + 0xff000000)
+#define C656_VS_LNST_O ((0x1be3 << 2) + 0xff000000)
+#define C656_VS_LNED_E ((0x1be4 << 2) + 0xff000000)
+#define C656_VS_LNED_O ((0x1be5 << 2) + 0xff000000)
+#define C656_FS_LNST ((0x1be6 << 2) + 0xff000000)
+#define C656_FS_LNED ((0x1be7 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: enc480p_regs.h
+//
+//
+// Reading file: enci_regs.h
+//
+//===========================================================================
+// Video Interface Registers 0xb00 - 0xb57
+//===========================================================================
+#define ENCI_VIDEO_MODE ((0x1b00 << 2) + 0xff000000)
+#define ENCI_VIDEO_MODE_ADV ((0x1b01 << 2) + 0xff000000)
+#define ENCI_VIDEO_FSC_ADJ ((0x1b02 << 2) + 0xff000000)
+#define ENCI_VIDEO_BRIGHT ((0x1b03 << 2) + 0xff000000)
+#define ENCI_VIDEO_CONT ((0x1b04 << 2) + 0xff000000)
+#define ENCI_VIDEO_SAT ((0x1b05 << 2) + 0xff000000)
+#define ENCI_VIDEO_HUE ((0x1b06 << 2) + 0xff000000)
+#define ENCI_VIDEO_SCH ((0x1b07 << 2) + 0xff000000)
+#define ENCI_SYNC_MODE ((0x1b08 << 2) + 0xff000000)
+#define ENCI_SYNC_CTRL ((0x1b09 << 2) + 0xff000000)
+#define ENCI_SYNC_HSO_BEGIN ((0x1b0a << 2) + 0xff000000)
+#define ENCI_SYNC_HSO_END ((0x1b0b << 2) + 0xff000000)
+#define ENCI_SYNC_VSO_EVN ((0x1b0c << 2) + 0xff000000)
+#define ENCI_SYNC_VSO_ODD ((0x1b0d << 2) + 0xff000000)
+#define ENCI_SYNC_VSO_EVNLN ((0x1b0e << 2) + 0xff000000)
+#define ENCI_SYNC_VSO_ODDLN ((0x1b0f << 2) + 0xff000000)
+#define ENCI_SYNC_HOFFST ((0x1b10 << 2) + 0xff000000)
+#define ENCI_SYNC_VOFFST ((0x1b11 << 2) + 0xff000000)
+#define ENCI_SYNC_ADJ ((0x1b12 << 2) + 0xff000000)
+#define ENCI_RGB_SETTING ((0x1b13 << 2) + 0xff000000)
+//`define ENCI_CMPN_MATRIX_CB 8'h14
+//`define ENCI_CMPN_MATRIX_CR 8'h15
+#define ENCI_DE_H_BEGIN ((0x1b16 << 2) + 0xff000000)
+#define ENCI_DE_H_END ((0x1b17 << 2) + 0xff000000)
+#define ENCI_DE_V_BEGIN_EVEN ((0x1b18 << 2) + 0xff000000)
+#define ENCI_DE_V_END_EVEN ((0x1b19 << 2) + 0xff000000)
+#define ENCI_DE_V_BEGIN_ODD ((0x1b1a << 2) + 0xff000000)
+#define ENCI_DE_V_END_ODD ((0x1b1b << 2) + 0xff000000)
+#define ENCI_VBI_SETTING ((0x1b20 << 2) + 0xff000000)
+#define ENCI_VBI_CCDT_EVN ((0x1b21 << 2) + 0xff000000)
+#define ENCI_VBI_CCDT_ODD ((0x1b22 << 2) + 0xff000000)
+#define ENCI_VBI_CC525_LN ((0x1b23 << 2) + 0xff000000)
+#define ENCI_VBI_CC625_LN ((0x1b24 << 2) + 0xff000000)
+#define ENCI_VBI_WSSDT ((0x1b25 << 2) + 0xff000000)
+#define ENCI_VBI_WSS_LN ((0x1b26 << 2) + 0xff000000)
+#define ENCI_VBI_CGMSDT_L ((0x1b27 << 2) + 0xff000000)
+#define ENCI_VBI_CGMSDT_H ((0x1b28 << 2) + 0xff000000)
+#define ENCI_VBI_CGMS_LN ((0x1b29 << 2) + 0xff000000)
+#define ENCI_VBI_TTX_HTIME ((0x1b2a << 2) + 0xff000000)
+#define ENCI_VBI_TTX_LN ((0x1b2b << 2) + 0xff000000)
+#define ENCI_VBI_TTXDT0 ((0x1b2c << 2) + 0xff000000)
+#define ENCI_VBI_TTXDT1 ((0x1b2d << 2) + 0xff000000)
+#define ENCI_VBI_TTXDT2 ((0x1b2e << 2) + 0xff000000)
+#define ENCI_VBI_TTXDT3 ((0x1b2f << 2) + 0xff000000)
+#define ENCI_MACV_N0 ((0x1b30 << 2) + 0xff000000)
+#define ENCI_MACV_N1 ((0x1b31 << 2) + 0xff000000)
+#define ENCI_MACV_N2 ((0x1b32 << 2) + 0xff000000)
+#define ENCI_MACV_N3 ((0x1b33 << 2) + 0xff000000)
+#define ENCI_MACV_N4 ((0x1b34 << 2) + 0xff000000)
+#define ENCI_MACV_N5 ((0x1b35 << 2) + 0xff000000)
+#define ENCI_MACV_N6 ((0x1b36 << 2) + 0xff000000)
+#define ENCI_MACV_N7 ((0x1b37 << 2) + 0xff000000)
+#define ENCI_MACV_N8 ((0x1b38 << 2) + 0xff000000)
+#define ENCI_MACV_N9 ((0x1b39 << 2) + 0xff000000)
+#define ENCI_MACV_N10 ((0x1b3a << 2) + 0xff000000)
+#define ENCI_MACV_N11 ((0x1b3b << 2) + 0xff000000)
+#define ENCI_MACV_N12 ((0x1b3c << 2) + 0xff000000)
+#define ENCI_MACV_N13 ((0x1b3d << 2) + 0xff000000)
+#define ENCI_MACV_N14 ((0x1b3e << 2) + 0xff000000)
+#define ENCI_MACV_N15 ((0x1b3f << 2) + 0xff000000)
+#define ENCI_MACV_N16 ((0x1b40 << 2) + 0xff000000)
+#define ENCI_MACV_N17 ((0x1b41 << 2) + 0xff000000)
+#define ENCI_MACV_N18 ((0x1b42 << 2) + 0xff000000)
+#define ENCI_MACV_N19 ((0x1b43 << 2) + 0xff000000)
+#define ENCI_MACV_N20 ((0x1b44 << 2) + 0xff000000)
+#define ENCI_MACV_N21 ((0x1b45 << 2) + 0xff000000)
+#define ENCI_MACV_N22 ((0x1b46 << 2) + 0xff000000)
+//`define ENCI_MACV_P_AGC 8'h47
+#define ENCI_DBG_PX_RST ((0x1b48 << 2) + 0xff000000)
+#define ENCI_DBG_FLDLN_RST ((0x1b49 << 2) + 0xff000000)
+#define ENCI_DBG_PX_INT ((0x1b4a << 2) + 0xff000000)
+#define ENCI_DBG_FLDLN_INT ((0x1b4b << 2) + 0xff000000)
+#define ENCI_DBG_MAXPX ((0x1b4c << 2) + 0xff000000)
+#define ENCI_DBG_MAXLN ((0x1b4d << 2) + 0xff000000)
+#define ENCI_MACV_MAX_AMP ((0x1b50 << 2) + 0xff000000)
+#define ENCI_MACV_PULSE_LO ((0x1b51 << 2) + 0xff000000)
+#define ENCI_MACV_PULSE_HI ((0x1b52 << 2) + 0xff000000)
+#define ENCI_MACV_BKP_MAX ((0x1b53 << 2) + 0xff000000)
+#define ENCI_CFILT_CTRL ((0x1b54 << 2) + 0xff000000)
+#define ENCI_CFILT7 ((0x1b55 << 2) + 0xff000000)
+#define ENCI_YC_DELAY ((0x1b56 << 2) + 0xff000000)
+#define ENCI_VIDEO_EN ((0x1b57 << 2) + 0xff000000)
+//
+// Closing file: enci_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VENC0B_VCBUS_BASE = 0x1c
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: venc2_regs.h
+//
+//===========================================================================
+// Venc Registers (Cont.) 0xc00 - 0xcff (VENC registers 0xc00 - 0xcef)
+//===========================================================================
+// Program video control signals from ENCI core to DVI/HDMI interface
+#define ENCI_DVI_HSO_BEGIN ((0x1c00 << 2) + 0xff000000)
+#define ENCI_DVI_HSO_END ((0x1c01 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_BLINE_EVN ((0x1c02 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_BLINE_ODD ((0x1c03 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_ELINE_EVN ((0x1c04 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_ELINE_ODD ((0x1c05 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_BEGIN_EVN ((0x1c06 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_BEGIN_ODD ((0x1c07 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_END_EVN ((0x1c08 << 2) + 0xff000000)
+#define ENCI_DVI_VSO_END_ODD ((0x1c09 << 2) + 0xff000000)
+// Define cmpt and cvbs cb/cr delay after ENCI chroma filters
+// Bit 15:12 RW, enci_cb_cvbs_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+// Bit 11: 8 RW, enci_cr_cvbs_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+// Bit 7: 4 RW, enci_cb_cmpt_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+// Bit 3: 0 RW, enci_cr_cmpt_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+#define ENCI_CFILT_CTRL2 ((0x1c0a << 2) + 0xff000000)
+#define ENCI_DACSEL_0 ((0x1c0b << 2) + 0xff000000)
+#define ENCI_DACSEL_1 ((0x1c0c << 2) + 0xff000000)
+#define ENCP_DACSEL_0 ((0x1c0d << 2) + 0xff000000)
+#define ENCP_DACSEL_1 ((0x1c0e << 2) + 0xff000000)
+#define ENCP_MAX_LINE_SWITCH_POINT ((0x1c0f << 2) + 0xff000000)
+#define ENCI_TST_EN ((0x1c10 << 2) + 0xff000000)
+#define ENCI_TST_MDSEL ((0x1c11 << 2) + 0xff000000)
+#define ENCI_TST_Y ((0x1c12 << 2) + 0xff000000)
+#define ENCI_TST_CB ((0x1c13 << 2) + 0xff000000)
+#define ENCI_TST_CR ((0x1c14 << 2) + 0xff000000)
+#define ENCI_TST_CLRBAR_STRT ((0x1c15 << 2) + 0xff000000)
+#define ENCI_TST_CLRBAR_WIDTH ((0x1c16 << 2) + 0xff000000)
+#define ENCI_TST_VDCNT_STSET ((0x1c17 << 2) + 0xff000000)
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 7 -- vfifo2vd_drop
+// bit 6:1 -- vfifo2vd_delay
+// bit 0 -- vfifo2vd_en
+#define ENCI_VFIFO2VD_CTL ((0x1c18 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCI_VFIFO2VD_PIXEL_START ((0x1c19 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCI_VFIFO2VD_PIXEL_END ((0x1c1a << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCI_VFIFO2VD_LINE_TOP_START ((0x1c1b << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCI_VFIFO2VD_LINE_TOP_END ((0x1c1c << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCI_VFIFO2VD_LINE_BOT_START ((0x1c1d << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCI_VFIFO2VD_LINE_BOT_END ((0x1c1e << 2) + 0xff000000)
+#define ENCI_VFIFO2VD_CTL2 ((0x1c1f << 2) + 0xff000000)
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 7 -- vfifo2vd_drop
+// bit 6:1 -- vfifo2vd_delay
+// bit 0 -- vfifo2vd_en
+#define ENCT_VFIFO2VD_CTL ((0x1c20 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCT_VFIFO2VD_PIXEL_START ((0x1c21 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCT_VFIFO2VD_PIXEL_END ((0x1c22 << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCT_VFIFO2VD_LINE_TOP_START ((0x1c23 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCT_VFIFO2VD_LINE_TOP_END ((0x1c24 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCT_VFIFO2VD_LINE_BOT_START ((0x1c25 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCT_VFIFO2VD_LINE_BOT_END ((0x1c26 << 2) + 0xff000000)
+#define ENCT_VFIFO2VD_CTL2 ((0x1c27 << 2) + 0xff000000)
+#define ENCT_TST_EN ((0x1c28 << 2) + 0xff000000)
+#define ENCT_TST_MDSEL ((0x1c29 << 2) + 0xff000000)
+#define ENCT_TST_Y ((0x1c2a << 2) + 0xff000000)
+#define ENCT_TST_CB ((0x1c2b << 2) + 0xff000000)
+#define ENCT_TST_CR ((0x1c2c << 2) + 0xff000000)
+#define ENCT_TST_CLRBAR_STRT ((0x1c2d << 2) + 0xff000000)
+#define ENCT_TST_CLRBAR_WIDTH ((0x1c2e << 2) + 0xff000000)
+#define ENCT_TST_VDCNT_STSET ((0x1c2f << 2) + 0xff000000)
+// Program video control signals from ENCP core to DVI/HDMI interface
+#define ENCP_DVI_HSO_BEGIN ((0x1c30 << 2) + 0xff000000)
+#define ENCP_DVI_HSO_END ((0x1c31 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_BLINE_EVN ((0x1c32 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_BLINE_ODD ((0x1c33 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_ELINE_EVN ((0x1c34 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_ELINE_ODD ((0x1c35 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_BEGIN_EVN ((0x1c36 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_BEGIN_ODD ((0x1c37 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_END_EVN ((0x1c38 << 2) + 0xff000000)
+#define ENCP_DVI_VSO_END_ODD ((0x1c39 << 2) + 0xff000000)
+#define ENCP_DE_H_BEGIN ((0x1c3a << 2) + 0xff000000)
+#define ENCP_DE_H_END ((0x1c3b << 2) + 0xff000000)
+#define ENCP_DE_V_BEGIN_EVEN ((0x1c3c << 2) + 0xff000000)
+#define ENCP_DE_V_END_EVEN ((0x1c3d << 2) + 0xff000000)
+#define ENCP_DE_V_BEGIN_ODD ((0x1c3e << 2) + 0xff000000)
+#define ENCP_DE_V_END_ODD ((0x1c3f << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCI_SYNC_LINE_LENGTH ((0x1c40 << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCI_SYNC_PIXEL_EN ((0x1c41 << 2) + 0xff000000)
+// Bit 15 - enci_sync_enable
+// Bit 14 - encp_sync_enable
+// Bit 13 - enct_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCI_SYNC_TO_LINE_EN ((0x1c42 << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCI_SYNC_TO_PIXEL ((0x1c43 << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCP_SYNC_LINE_LENGTH ((0x1c44 << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCP_SYNC_PIXEL_EN ((0x1c45 << 2) + 0xff000000)
+// Bit 15 - enci_sync_enable
+// Bit 14 - encp_sync_enable
+// Bit 13 - enct_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCP_SYNC_TO_LINE_EN ((0x1c46 << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCP_SYNC_TO_PIXEL ((0x1c47 << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCT_SYNC_LINE_LENGTH ((0x1c48 << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCT_SYNC_PIXEL_EN ((0x1c49 << 2) + 0xff000000)
+// Bit 15 - enci_sync_enable
+// Bit 14 - encp_sync_enable
+// Bit 13 - enct_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCT_SYNC_TO_LINE_EN ((0x1c4a << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCT_SYNC_TO_PIXEL ((0x1c4b << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCL_SYNC_LINE_LENGTH ((0x1c4c << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCL_SYNC_PIXEL_EN ((0x1c4d << 2) + 0xff000000)
+// Bit 15 - enci_sync_enable
+// Bit 14 - encp_sync_enable
+// Bit 13 - enct_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCL_SYNC_TO_LINE_EN ((0x1c4e << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCL_SYNC_TO_PIXEL ((0x1c4f << 2) + 0xff000000)
+// bit 3 cfg_encp_lcd_scaler_bypass. 1=Do not scale LCD input data;
+// 0=Scale LCD input data to y [16*4,235*4], c [16*4,240*4].
+// bit 2 cfg_encp_vadj_scaler_bypass. 1=Do not scale data to enc480p_vadj;
+// 0=Scale enc480p_vadj input data to y [16*4,235*4], c [16*4,240*4].
+// bit 1 cfg_vfifo2vd_out_scaler_bypass. 1=Do not scale vfifo2vd's output vdata;
+// 0=Scale vfifo2vd's output vdata to y [16,235], c [16,240].
+// bit 0 cfg_vfifo_din_full_range. 1=Data from viu fifo is full range [0,1023];
+// 0=Data from viu fifo is y [16*4,235*4], c [16*4,240*4].
+#define ENCP_VFIFO2VD_CTL2 ((0x1c50 << 2) + 0xff000000)
+// bit 15:1 Reserved.
+// bit 0 cfg_int_dvi_sel_rgb. Applicable for using on-chip hdmi tx module only. This bit controls correct bit-mapping from
+// Venc to hdmi_tx depending on whether YCbCr or RGB mode.
+// 1=Map data bit from Venc to hdmi_tx for RGB mode;
+// 0=Default. Map data bit from Venc to hdmi_tx for YCbCr mode.
+#define VENC_DVI_SETTING_MORE ((0x1c51 << 2) + 0xff000000)
+#define VENC_VDAC_DAC4_FILT_CTRL0 ((0x1c54 << 2) + 0xff000000)
+#define VENC_VDAC_DAC4_FILT_CTRL1 ((0x1c55 << 2) + 0xff000000)
+#define VENC_VDAC_DAC5_FILT_CTRL0 ((0x1c56 << 2) + 0xff000000)
+#define VENC_VDAC_DAC5_FILT_CTRL1 ((0x1c57 << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC_VDAC_DAC0_FILT_CTRL0 ((0x1c58 << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC_VDAC_DAC0_FILT_CTRL1 ((0x1c59 << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC_VDAC_DAC1_FILT_CTRL0 ((0x1c5a << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC_VDAC_DAC1_FILT_CTRL1 ((0x1c5b << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC_VDAC_DAC2_FILT_CTRL0 ((0x1c5c << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC_VDAC_DAC2_FILT_CTRL1 ((0x1c5d << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC_VDAC_DAC3_FILT_CTRL0 ((0x1c5e << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC_VDAC_DAC3_FILT_CTRL1 ((0x1c5f << 2) + 0xff000000)
+//===========================================================================
+// ENCT registers
+#define ENCT_VIDEO_EN ((0x1c60 << 2) + 0xff000000)
+#define ENCT_VIDEO_Y_SCL ((0x1c61 << 2) + 0xff000000)
+#define ENCT_VIDEO_PB_SCL ((0x1c62 << 2) + 0xff000000)
+#define ENCT_VIDEO_PR_SCL ((0x1c63 << 2) + 0xff000000)
+#define ENCT_VIDEO_Y_OFFST ((0x1c64 << 2) + 0xff000000)
+#define ENCT_VIDEO_PB_OFFST ((0x1c65 << 2) + 0xff000000)
+#define ENCT_VIDEO_PR_OFFST ((0x1c66 << 2) + 0xff000000)
+//----- Video mode
+#define ENCT_VIDEO_MODE ((0x1c67 << 2) + 0xff000000)
+#define ENCT_VIDEO_MODE_ADV ((0x1c68 << 2) + 0xff000000)
+//--------------- Debug pins
+#define ENCT_DBG_PX_RST ((0x1c69 << 2) + 0xff000000)
+#define ENCT_DBG_LN_RST ((0x1c6a << 2) + 0xff000000)
+#define ENCT_DBG_PX_INT ((0x1c6b << 2) + 0xff000000)
+#define ENCT_DBG_LN_INT ((0x1c6c << 2) + 0xff000000)
+//----------- Video Advanced setting
+#define ENCT_VIDEO_YFP1_HTIME ((0x1c6d << 2) + 0xff000000)
+#define ENCT_VIDEO_YFP2_HTIME ((0x1c6e << 2) + 0xff000000)
+#define ENCT_VIDEO_YC_DLY ((0x1c6f << 2) + 0xff000000)
+#define ENCT_VIDEO_MAX_PXCNT ((0x1c70 << 2) + 0xff000000)
+#define ENCT_VIDEO_HAVON_END ((0x1c71 << 2) + 0xff000000)
+#define ENCT_VIDEO_HAVON_BEGIN ((0x1c72 << 2) + 0xff000000)
+#define ENCT_VIDEO_VAVON_ELINE ((0x1c73 << 2) + 0xff000000)
+#define ENCT_VIDEO_VAVON_BLINE ((0x1c74 << 2) + 0xff000000)
+#define ENCT_VIDEO_HSO_BEGIN ((0x1c75 << 2) + 0xff000000)
+#define ENCT_VIDEO_HSO_END ((0x1c76 << 2) + 0xff000000)
+#define ENCT_VIDEO_VSO_BEGIN ((0x1c77 << 2) + 0xff000000)
+#define ENCT_VIDEO_VSO_END ((0x1c78 << 2) + 0xff000000)
+#define ENCT_VIDEO_VSO_BLINE ((0x1c79 << 2) + 0xff000000)
+#define ENCT_VIDEO_VSO_ELINE ((0x1c7a << 2) + 0xff000000)
+#define ENCT_VIDEO_MAX_LNCNT ((0x1c7b << 2) + 0xff000000)
+#define ENCT_VIDEO_BLANKY_VAL ((0x1c7c << 2) + 0xff000000)
+#define ENCT_VIDEO_BLANKPB_VAL ((0x1c7d << 2) + 0xff000000)
+#define ENCT_VIDEO_BLANKPR_VAL ((0x1c7e << 2) + 0xff000000)
+#define ENCT_VIDEO_HOFFST ((0x1c7f << 2) + 0xff000000)
+#define ENCT_VIDEO_VOFFST ((0x1c80 << 2) + 0xff000000)
+#define ENCT_VIDEO_RGB_CTRL ((0x1c81 << 2) + 0xff000000)
+#define ENCT_VIDEO_FILT_CTRL ((0x1c82 << 2) + 0xff000000)
+#define ENCT_VIDEO_OFLD_VPEQ_OFST ((0x1c83 << 2) + 0xff000000)
+#define ENCT_VIDEO_OFLD_VOAV_OFST ((0x1c84 << 2) + 0xff000000)
+#define ENCT_VIDEO_MATRIX_CB ((0x1c85 << 2) + 0xff000000)
+#define ENCT_VIDEO_MATRIX_CR ((0x1c86 << 2) + 0xff000000)
+#define ENCT_VIDEO_RGBIN_CTRL ((0x1c87 << 2) + 0xff000000)
+#define ENCT_MAX_LINE_SWITCH_POINT ((0x1c88 << 2) + 0xff000000)
+#define ENCT_DACSEL_0 ((0x1c89 << 2) + 0xff000000)
+#define ENCT_DACSEL_1 ((0x1c8a << 2) + 0xff000000)
+#define ENCT_INBUF_CNTL0 ((0x1c8b << 2) + 0xff000000)
+#define ENCT_INBUF_CNTL1 ((0x1c8c << 2) + 0xff000000)
+#define ENCT_INBUF_CNT ((0x1c8d << 2) + 0xff000000)
+#define ENCT_INBUF_HOLD_CNT ((0x1c8e << 2) + 0xff000000)
+#define ENCT_INBUF_FIX_PIX_NUM ((0x1c8f << 2) + 0xff000000)
+//===========================================================================
+// For ENCL
+//===========================================================================
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 7 -- vfifo2vd_drop
+// bit 6:1 -- vfifo2vd_delay
+// bit 0 -- vfifo2vd_en
+#define ENCL_VFIFO2VD_CTL ((0x1c90 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCL_VFIFO2VD_PIXEL_START ((0x1c91 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCL_VFIFO2VD_PIXEL_END ((0x1c92 << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCL_VFIFO2VD_LINE_TOP_START ((0x1c93 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCL_VFIFO2VD_LINE_TOP_END ((0x1c94 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCL_VFIFO2VD_LINE_BOT_START ((0x1c95 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCL_VFIFO2VD_LINE_BOT_END ((0x1c96 << 2) + 0xff000000)
+#define ENCL_VFIFO2VD_CTL2 ((0x1c97 << 2) + 0xff000000)
+#define ENCL_TST_EN ((0x1c98 << 2) + 0xff000000)
+#define ENCL_TST_MDSEL ((0x1c99 << 2) + 0xff000000)
+#define ENCL_TST_Y ((0x1c9a << 2) + 0xff000000)
+#define ENCL_TST_CB ((0x1c9b << 2) + 0xff000000)
+#define ENCL_TST_CR ((0x1c9c << 2) + 0xff000000)
+#define ENCL_TST_CLRBAR_STRT ((0x1c9d << 2) + 0xff000000)
+#define ENCL_TST_CLRBAR_WIDTH ((0x1c9e << 2) + 0xff000000)
+#define ENCL_TST_VDCNT_STSET ((0x1c9f << 2) + 0xff000000)
+//===========================================================================
+// ENCL registers
+#define ENCL_VIDEO_EN ((0x1ca0 << 2) + 0xff000000)
+#define ENCL_VIDEO_Y_SCL ((0x1ca1 << 2) + 0xff000000)
+#define ENCL_VIDEO_PB_SCL ((0x1ca2 << 2) + 0xff000000)
+#define ENCL_VIDEO_PR_SCL ((0x1ca3 << 2) + 0xff000000)
+#define ENCL_VIDEO_Y_OFFST ((0x1ca4 << 2) + 0xff000000)
+#define ENCL_VIDEO_PB_OFFST ((0x1ca5 << 2) + 0xff000000)
+#define ENCL_VIDEO_PR_OFFST ((0x1ca6 << 2) + 0xff000000)
+//----- Video mode
+#define ENCL_VIDEO_MODE ((0x1ca7 << 2) + 0xff000000)
+#define ENCL_VIDEO_MODE_ADV ((0x1ca8 << 2) + 0xff000000)
+//--------------- Debug pins
+#define ENCL_DBG_PX_RST ((0x1ca9 << 2) + 0xff000000)
+#define ENCL_DBG_LN_RST ((0x1caa << 2) + 0xff000000)
+#define ENCL_DBG_PX_INT ((0x1cab << 2) + 0xff000000)
+#define ENCL_DBG_LN_INT ((0x1cac << 2) + 0xff000000)
+//----------- Video Advanced setting
+#define ENCL_VIDEO_YFP1_HTIME ((0x1cad << 2) + 0xff000000)
+#define ENCL_VIDEO_YFP2_HTIME ((0x1cae << 2) + 0xff000000)
+#define ENCL_VIDEO_YC_DLY ((0x1caf << 2) + 0xff000000)
+#define ENCL_VIDEO_MAX_PXCNT ((0x1cb0 << 2) + 0xff000000)
+#define ENCL_VIDEO_HAVON_END ((0x1cb1 << 2) + 0xff000000)
+#define ENCL_VIDEO_HAVON_BEGIN ((0x1cb2 << 2) + 0xff000000)
+#define ENCL_VIDEO_VAVON_ELINE ((0x1cb3 << 2) + 0xff000000)
+#define ENCL_VIDEO_VAVON_BLINE ((0x1cb4 << 2) + 0xff000000)
+#define ENCL_VIDEO_HSO_BEGIN ((0x1cb5 << 2) + 0xff000000)
+#define ENCL_VIDEO_HSO_END ((0x1cb6 << 2) + 0xff000000)
+#define ENCL_VIDEO_VSO_BEGIN ((0x1cb7 << 2) + 0xff000000)
+#define ENCL_VIDEO_VSO_END ((0x1cb8 << 2) + 0xff000000)
+#define ENCL_VIDEO_VSO_BLINE ((0x1cb9 << 2) + 0xff000000)
+#define ENCL_VIDEO_VSO_ELINE ((0x1cba << 2) + 0xff000000)
+#define ENCL_VIDEO_MAX_LNCNT ((0x1cbb << 2) + 0xff000000)
+#define ENCL_VIDEO_BLANKY_VAL ((0x1cbc << 2) + 0xff000000)
+#define ENCL_VIDEO_BLANKPB_VAL ((0x1cbd << 2) + 0xff000000)
+#define ENCL_VIDEO_BLANKPR_VAL ((0x1cbe << 2) + 0xff000000)
+#define ENCL_VIDEO_HOFFST ((0x1cbf << 2) + 0xff000000)
+#define ENCL_VIDEO_VOFFST ((0x1cc0 << 2) + 0xff000000)
+#define ENCL_VIDEO_RGB_CTRL ((0x1cc1 << 2) + 0xff000000)
+#define ENCL_VIDEO_FILT_CTRL ((0x1cc2 << 2) + 0xff000000)
+#define ENCL_VIDEO_OFLD_VPEQ_OFST ((0x1cc3 << 2) + 0xff000000)
+#define ENCL_VIDEO_OFLD_VOAV_OFST ((0x1cc4 << 2) + 0xff000000)
+#define ENCL_VIDEO_MATRIX_CB ((0x1cc5 << 2) + 0xff000000)
+#define ENCL_VIDEO_MATRIX_CR ((0x1cc6 << 2) + 0xff000000)
+#define ENCL_VIDEO_RGBIN_CTRL ((0x1cc7 << 2) + 0xff000000)
+#define ENCL_MAX_LINE_SWITCH_POINT ((0x1cc8 << 2) + 0xff000000)
+#define ENCL_DACSEL_0 ((0x1cc9 << 2) + 0xff000000)
+#define ENCL_DACSEL_1 ((0x1cca << 2) + 0xff000000)
+#define ENCT_VIDEO_H_PRE_DE_END ((0x1ccb << 2) + 0xff000000)
+#define ENCT_VIDEO_H_PRE_DE_BEGIN ((0x1ccc << 2) + 0xff000000)
+#define ENCT_VIDEO_V_PRE_DE_ELINE ((0x1ccd << 2) + 0xff000000)
+#define ENCT_VIDEO_V_PRE_DE_BLINE ((0x1cce << 2) + 0xff000000)
+#define ENCL_VIDEO_H_PRE_DE_END ((0x1ccf << 2) + 0xff000000)
+#define ENCL_VIDEO_H_PRE_DE_BEGIN ((0x1cd0 << 2) + 0xff000000)
+#define ENCL_VIDEO_V_PRE_DE_ELINE ((0x1cd1 << 2) + 0xff000000)
+#define ENCL_VIDEO_V_PRE_DE_BLINE ((0x1cd2 << 2) + 0xff000000)
+#define ENCL_INBUF_CNTL0 ((0x1cd3 << 2) + 0xff000000)
+#define ENCL_INBUF_CNTL1 ((0x1cd4 << 2) + 0xff000000)
+#define ENCL_INBUF_CNT ((0x1cd5 << 2) + 0xff000000)
+#define ENCL_INBUF_HOLD_CNT ((0x1cd6 << 2) + 0xff000000)
+#define ENCL_INBUF_FIX_PIX_NUM ((0x1cd7 << 2) + 0xff000000)
+#define VENC_VRR_CTRL ((0x1cd8 << 2) + 0xff000000)
+//Bit 31 cfg_vsp_din // W, pulse
+//Bit 30 cfg_vrr_clr // W, pulse
+//Bit 31:28 ro_vrr_vsp_cnt // R,
+//Bit 27:24 ro_vrr_max_err // R,
+//Bit 23:8 cfg_vsp_dly_num // R/W, unsigned, default 0
+//Bit 7:4 cfg_vrr_frm_ths // R/W, unsigned, default 0
+//Bit 3:2 cfg_vrr_vsp_en // R/W, unsigned, default 0
+//Bit 1 cfg_vrr_mode // R/W, unsigned, default 0
+//Bit 0 cfg_vrr_vsp_sel // R/W, unsigned, default 0
+#define VENC_VRR_ADJ_LMT ((0x1cd9 << 2) + 0xff000000)
+//Bit 31:16 cfg_vrr_min_vnum //R/W, unsigned,
+//Bit 15:0 cfg_vrr_max_vnum //R/W, unsigned,
+#define VPU_VPU_PWM_V0 ((0x1ce0 << 2) + 0xff000000)
+#define VPU_VPU_PWM_V1 ((0x1ce1 << 2) + 0xff000000)
+#define VPU_VPU_PWM_V2 ((0x1ce2 << 2) + 0xff000000)
+#define VPU_VPU_PWM_V3 ((0x1ce3 << 2) + 0xff000000)
+#define VPU_VPU_PWM_H0 ((0x1ce4 << 2) + 0xff000000)
+#define VPU_VPU_PWM_H1 ((0x1ce5 << 2) + 0xff000000)
+#define VPU_VPU_PWM_H2 ((0x1ce6 << 2) + 0xff000000)
+#define VPU_VPU_PWM_H3 ((0x1ce7 << 2) + 0xff000000)
+#define VPU_VPU_3D_SYNC1 ((0x1ce8 << 2) + 0xff000000)
+#define VPU_VPU_3D_SYNC2 ((0x1ce9 << 2) + 0xff000000)
+#define VPU_VENC_DUMMY ((0x1cdf << 2) + 0xff000000)
+#define VPU_VENC_ERROR ((0x1cea << 2) + 0xff000000)
+#define VPU_VENCI_STAT ((0x1ceb << 2) + 0xff000000)
+#define VPU_VENCP_STAT ((0x1cec << 2) + 0xff000000)
+#define VPU_VENCL_STAT ((0x1ced << 2) + 0xff000000)
+#define VPU_VENC_DITH ((0x1cee << 2) + 0xff000000)
+#define VPU_VENC_CTRL ((0x1cef << 2) + 0xff000000)
+#define VPU_VENCL_DITH_CTRL ((0x1cf0 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_1 ((0x1cf1 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_2 ((0x1cf2 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_3 ((0x1cf3 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_4 ((0x1cf4 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_5 ((0x1cf5 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_6 ((0x1cf6 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_7 ((0x1cf7 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_8 ((0x1cf8 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_9 ((0x1cf9 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_10 ((0x1cfa << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_11 ((0x1cfb << 2) + 0xff000000)
+#define VPU_VENCL_DITH_LUT_12 ((0x1cfc << 2) + 0xff000000)
+//
+// Closing file: venc2_regs.h
+//
+//===========================================================================
+//===========================================================================
+//
+// Reading file: vpp_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: VPP_VCBUS_BASE = 0x1d
+// -----------------------------------------------
+//===========================================================================
+// Video postprocesing Registers
+//===========================================================================
+// dummy data used in the VPP preblend and scaler
+// Bit 23:16 Y
+// Bit 15:8 CB
+// Bit 7:0 CR
+#define VPP_DUMMY_DATA ((0x1d00 << 2) + 0xff000000)
+//input line length used in VPP
+#define VPP_LINE_IN_LENGTH ((0x1d01 << 2) + 0xff000000)
+//input Picture height used in VPP
+#define VPP_PIC_IN_HEIGHT ((0x1d02 << 2) + 0xff000000)
+//Because there are many coefficients used in the vertical filter and horizontal filters,
+//indirect access the coefficients of vertical filter and horizontal filter is used.
+//For vertical filter, there are 33x4 coefficients
+//For horizontal filter, there are 33x4 coefficients
+//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
+//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
+//Bit 13 if true, vertical separated coef enable
+//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
+//Bit 8:7 type of index, 00: vertical coef, 01: vertical chroma coef: 10: horizontal coef, 11: resevered
+//Bit 6:0 coef index
+#define VPP_SCALE_COEF_IDX ((0x1d03 << 2) + 0xff000000)
+//coefficients for vertical filter and horizontal filter
+#define VPP_SCALE_COEF ((0x1d04 << 2) + 0xff000000)
+//these following registers are the absolute line address pointer for output divided screen
+//The output divided screen is shown in the following:
+//
+// -------------------------- <------ line zero
+// .
+// .
+// . region0 <---------- nonlinear region or nonscaling region
+// .
+// ---------------------------
+// --------------------------- <------ region1_startp
+// .
+// . region1 <---------- nonlinear region
+// .
+// .
+// ---------------------------
+// --------------------------- <------ region2_startp
+// .
+// . region2 <---------- linear region
+// .
+// .
+// ---------------------------
+// --------------------------- <------ region3_startp
+// .
+// . region3 <---------- nonlinear region
+// .
+// .
+// ---------------------------
+// --------------------------- <------ region4_startp
+// .
+// . region4 <---------- nonlinear region or nonoscaling region
+// .
+// .
+// --------------------------- <------ region4_endp
+//Bit 28:16 region1 startp
+//Bit 12:0 region2 startp
+#define VPP_VSC_REGION12_STARTP ((0x1d05 << 2) + 0xff000000)
+//Bit 28:16 region3 startp
+//Bit 12:0 region4 startp
+#define VPP_VSC_REGION34_STARTP ((0x1d06 << 2) + 0xff000000)
+#define VPP_VSC_REGION4_ENDP ((0x1d07 << 2) + 0xff000000)
+//vertical start phase step, (source/dest)*(2^24)
+//Bit 27:24 integer part
+//Bit 23:0 fraction part
+#define VPP_VSC_START_PHASE_STEP ((0x1d08 << 2) + 0xff000000)
+//vertical scaler region0 phase slope, Bit24 signed bit
+#define VPP_VSC_REGION0_PHASE_SLOPE ((0x1d09 << 2) + 0xff000000)
+//vertical scaler region1 phase slope, Bit24 signed bit
+#define VPP_VSC_REGION1_PHASE_SLOPE ((0x1d0a << 2) + 0xff000000)
+//vertical scaler region3 phase slope, Bit24 signed bit
+#define VPP_VSC_REGION3_PHASE_SLOPE ((0x1d0b << 2) + 0xff000000)
+//vertical scaler region4 phase slope, Bit24 signed bit
+#define VPP_VSC_REGION4_PHASE_SLOPE ((0x1d0c << 2) + 0xff000000)
+//Bit 18:17 double line mode, input/output line width of vscaler becomes 2X,
+// so only 2 line buffer in this case, use for 3D line by line interleave scaling
+// bit1 true, double the input width and half input height, bit0 true, change line buffer 2 lines instead of 4 lines
+//Bit 16 0: progressive output, 1: interlace output
+//Bit 15 vertical scaler output line0 in advance or not for bottom field
+//Bit 14:13 vertical scaler initial repeat line0 number for bottom field
+//Bit 11:8 vertical scaler initial receiving number for bottom field
+//Bit 7 vertical scaler output line0 in advance or not for top field
+//Bit 6:5 vertical scaler initial repeat line0 number for top field
+//Bit 3:0 vertical scaler initial receiving number for top field
+#define VPP_VSC_PHASE_CTRL ((0x1d0d << 2) + 0xff000000)
+//Bit 31:16 vertical scaler field initial phase for bottom field
+//Bit 15:0 vertical scaler field initial phase for top field
+#define VPP_VSC_INI_PHASE ((0x1d0e << 2) + 0xff000000)
+//Bit 28:16 region1 startp
+//Bit 12:0 region2 startp
+#define VPP_HSC_REGION12_STARTP ((0x1d10 << 2) + 0xff000000)
+//Bit 28:16 region3 startp
+//Bit 12:0 region4 startp
+#define VPP_HSC_REGION34_STARTP ((0x1d11 << 2) + 0xff000000)
+#define VPP_HSC_REGION4_ENDP ((0x1d12 << 2) + 0xff000000)
+//horizontal start phase step, (source/dest)*(2^24)
+//Bit 27:24 integer part
+//Bit 23:0 fraction part
+#define VPP_HSC_START_PHASE_STEP ((0x1d13 << 2) + 0xff000000)
+//horizontal scaler region0 phase slope, Bit24 signed bit
+#define VPP_HSC_REGION0_PHASE_SLOPE ((0x1d14 << 2) + 0xff000000)
+//horizontal scaler region1 phase slope, Bit24 signed bit
+#define VPP_HSC_REGION1_PHASE_SLOPE ((0x1d15 << 2) + 0xff000000)
+//horizontal scaler region3 phase slope, Bit24 signed bit
+#define VPP_HSC_REGION3_PHASE_SLOPE ((0x1d16 << 2) + 0xff000000)
+//horizontal scaler region4 phase slope, Bit24 signed bit
+#define VPP_HSC_REGION4_PHASE_SLOPE ((0x1d17 << 2) + 0xff000000)
+//Bit 22:21 horizontal scaler initial repeat pixel0 number0
+//Bit 19:16 horizontal scaler initial receiving number0
+//Bit 15:0 horizontal scaler top field initial phase0
+#define VPP_HSC_PHASE_CTRL ((0x1d18 << 2) + 0xff000000)
+// Bit 22 if true, divide VSC line length 2 as the HSC input length, othwise VSC length length is the same as the VSC line length,
+// just for special usage, more flexibility
+// Bit 21 if true, prevsc uses lin buffer, otherwise prevsc does not use line buffer, it should be same as prevsc_en
+// Bit 20 prehsc_en
+// Bit 19 prevsc_en
+// Bit 18 vsc_en
+// Bit 17 hsc_en
+// Bit 16 scale_top_en
+// Bit 15 video1 scale out enable
+// Bit 12 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for horizontal scaler
+// Bit 10:8 horizontal scaler bank length
+// Bit 5, vertical scaler phase field mode, if true, disable the opposite parity line output, more bandwith needed if output 1080i
+// Bit 4 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for vertical scaler
+// Bit 2:0 vertical scaler bank length
+#define VPP_SC_MISC ((0x1d19 << 2) + 0xff000000)
+// preblend video1 horizontal start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_PREBLEND_VD1_H_START_END ((0x1d1a << 2) + 0xff000000)
+// preblend video1 vertical start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_PREBLEND_VD1_V_START_END ((0x1d1b << 2) + 0xff000000)
+// postblend video1 horizontal start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_POSTBLEND_VD1_H_START_END ((0x1d1c << 2) + 0xff000000)
+// postblend video1 vertical start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_POSTBLEND_VD1_V_START_END ((0x1d1d << 2) + 0xff000000)
+// preblend/postblend video2 horizontal start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_BLEND_VD2_H_START_END ((0x1d1e << 2) + 0xff000000)
+// preblend/postblend video2 vertical start and end
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_BLEND_VD2_V_START_END ((0x1d1f << 2) + 0xff000000)
+// preblend horizontal size
+#define VPP_PREBLEND_H_SIZE ((0x1d20 << 2) + 0xff000000)
+// postblend horizontal size
+#define VPP_POSTBLEND_H_SIZE ((0x1d21 << 2) + 0xff000000)
+//VPP hold lines
+//Bit 29:24
+//Bit 21:16
+//Bit 15:8 preblend hold lines
+//Bit 7:0 postblend hold lines
+#define VPP_HOLD_LINES ((0x1d22 << 2) + 0xff000000)
+//Bit 26 if true, automatic change post blend output to one color if field ==1
+//Bit 25 if true, change screen to one color value for preblender
+//Bit 24 if true, change screen to one color value for postblender
+// Bit 23:16 one color Y
+// Bit 15:8 one color Cb
+// Bit 7:0 one color Cr
+#define VPP_BLEND_ONECOLOR_CTRL ((0x1d23 << 2) + 0xff000000)
+//Read Only, VPP preblend current_x, current_y
+//Bit 28:16 current_x
+//Bit 12:0 current_y
+#define VPP_PREBLEND_CURRENT_XY ((0x1d24 << 2) + 0xff000000)
+//Read Only, VPP postblend current_x, current_y
+//Bit 28:16 current_x
+//Bit 12:0 current_y
+#define VPP_POSTBLEND_CURRENT_XY ((0x1d25 << 2) + 0xff000000)
+// Bit 31 vd1_bgosd_exchange_en for preblend
+// Bit 30 vd1_bgosd_exchange_en for postblend
+// Bit 28 color management enable
+// Bit 27, if true, vd2 use viu2 output as the input, otherwise use normal vd2 from memory
+// Bit 26:18, vd2 alpha
+// Bit 17, osd2 enable for preblend
+// Bit 16, osd1 enable for preblend
+// Bit 15, vd2 enable for preblend
+// Bit 14, vd1 enable for preblend
+// Bit 13, osd2 enable for postblend
+// Bit 12, osd1 enable for postblend
+// Bit 11, vd2 enable for postblend
+// Bit 10, vd1 enable for postblend
+// Bit 9, if true, osd1 is alpha premultipiled
+// Bit 8, if true, osd2 is alpha premultipiled
+// Bit 7, postblend module enable
+// Bit 6, preblend module enable
+// Bit 5, if true, osd2 foreground compared with osd1 in preblend
+// Bit 4, if true, osd2 foreground compared with osd1 in postblend
+// Bit 3,
+// Bit 2, if true, disable resetting async fifo every vsync, otherwise every vsync
+// the aync fifo will be reseted.
+// Bit 1,
+// Bit 0 if true, the output result of VPP is saturated
+#define VPP_MISC ((0x1d26 << 2) + 0xff000000)
+//Bit 31:20 ofifo line length minus 1
+//Bit 19 if true invert input vs
+//Bit 18 if true invert input hs
+//Bit 17 force top/bottom field, enable
+//Bit 16 force top/bottom field, 0: top, 1: bottom
+//Bit 15 force one go_field, one pluse, write only
+//Bit 14 force one go_line, one pluse, write only
+//Bit 12:0 ofifo size (actually only bit 10:1 is valid), always even number
+#define VPP_OFIFO_SIZE ((0x1d27 << 2) + 0xff000000)
+//Read only
+//Bit 28:18 current scale out fifo counter
+//Bit 17:13 current afifo counter
+//Bit 12:0 current ofifo counter
+#define VPP_FIFO_STATUS ((0x1d28 << 2) + 0xff000000)
+// Bit 5 SMOKE3 postblend enable only when postblend vd2 is not enable
+// Bit 4 SMOKE3 preblend enable only when preblend vd2 is not enable
+// Bit 3 SMOKE2 postblend enable only when postblend osd2 is not enable
+// Bit 2 SMOKE2 preblend enable only when preblend osd2 is not enable
+// Bit 1 SMOKE1 postblend enable only when postblend osd1 is not enable
+// Bit 0 SMOKE1 preblend enable only when preblend osd1 is not enable
+#define VPP_SMOKE_CTRL ((0x1d29 << 2) + 0xff000000)
+//smoke can be used only when that blending is disable and then be used as smoke function
+//smoke1 for OSD1 chanel
+//smoke2 for OSD2 chanel
+//smoke3 for VD2 chanel
+//31:24 Y
+//23:16 Cb
+//15:8 Cr
+//7:0 Alpha
+#define VPP_SMOKE1_VAL ((0x1d2a << 2) + 0xff000000)
+#define VPP_SMOKE2_VAL ((0x1d2b << 2) + 0xff000000)
+#define VPP_SMOKE3_VAL ((0x1d2c << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_SMOKE1_H_START_END ((0x1d2d << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_SMOKE1_V_START_END ((0x1d2e << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_SMOKE2_H_START_END ((0x1d2f << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_SMOKE2_V_START_END ((0x1d30 << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_SMOKE3_H_START_END ((0x1d31 << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_SMOKE3_V_START_END ((0x1d32 << 2) + 0xff000000)
+//Bit 27:16 scale out fifo line length minus 1
+//Bit 12:0 scale out fifo size (actually only bit 11:1 is valid, 11:1, max 1024), always even number
+#define VPP_SCO_FIFO_CTRL ((0x1d33 << 2) + 0xff000000)
+//for 3D quincunx sub-sampling and horizontal pixel by pixel 3D interleaving
+//Bit 27:24, prehsc_mode, bit 3:2, prehsc odd line interp mode, bit 1:0, prehsc even line interp mode,
+// each 2bit, 00: pix0+pix1/2, average, 01: pix1, 10: pix0
+//Bit 23 horizontal scaler double pixel mode
+//Bit 22:21 horizontal scaler initial repeat pixel0 number1
+//Bit 19:16 horizontal scaler initial receiving number1
+//Bit 15:0 horizontal scaler top field initial phase1
+#define VPP_HSC_PHASE_CTRL1 ((0x1d34 << 2) + 0xff000000)
+//for 3D quincunx sub-sampling
+//31:24 prehsc pattern, each patten 1 bit, from lsb -> msb
+//22:20 prehsc pattern start
+//18:16 prehsc pattern end
+//15:8 hsc pattern, each patten 1 bit, from lsb -> msb
+//6:4 hsc pattern start
+//2:0 hsc pattern end
+#define VPP_HSC_INI_PAT_CTRL ((0x1d35 << 2) + 0xff000000)
+#define VPP_SC_GCLK_CTRL ((0x1d36 << 2) + 0xff000000)
+#define VPP_PREHSC_COEF ((0x1d37 << 2) + 0xff000000)
+#define VPP_PRE_SCALE_CTRL ((0x1d38 << 2) + 0xff000000)
+#define VPP_PREVSC_COEF ((0x1d39 << 2) + 0xff000000)
+#define VPP_PREHSC_COEF1 ((0x1d3a << 2) + 0xff000000)
+// 0x3b-0x3e
+//
+// Reading file: vpp_pst_sta_regs.h
+//
+#define VPP_PST_STA_CTRL ((0x1d3b << 2) + 0xff000000)
+//Bit 31:5 reserved
+//Bit 21:16 reg_pst_hist_rd_idx .unsigned , default = 0, used for histgram read out
+//Bit 15:12 reserved
+//Bit 11:8 reg_gclk_ctrl .unsigned , default = 0,
+//Bit 7:5 reserved
+//Bit 4 reg_pst_hist_win_en .unsigned , default = 0, enable for post histogram sta window mode
+//Bit 3:2 reg_pst_hist_mode_sel .unsigned , default = 0, component selection for hist sta: 0~2 for data[cmp]; 3: max(dat[0],dat[1], dat[2])
+//Bit 1 reg_pst_hist_after_csc .unsigned , default = 0, hist_sta after CSC or NOT. 0: before CSC (YUV); 1: after CSC (R/G/B)
+//Bit 0 reg_pst_hist_sta_en .unsigned , default = 0, enable for post histogram sta
+#define VPP_PST_STA_WIN_X ((0x1d3c << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_pst_hist_win_xed .unsigned , default = 1919
+//Bit 15:14 reserved
+//Bit 13: 0 reg_pst_hist_win_xst .unsigned , default = 0
+#define VPP_PST_STA_WIN_Y ((0x1d3d << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_pst_hist_win_yed .unsigned , default = 1079
+//Bit 15:14 reserved
+//Bit 13: 0 reg_pst_hist_win_yst .unsigned , default = 0
+#define VPP_PST_STA_RO_HIST ((0x1d3e << 2) + 0xff000000)
+//Bit 23:0 ro_pst_hist_out .unsigned ,RO,default = 0 ;
+//
+// Closing file: vpp_pst_sta_regs.h
+//
+//Bit 3 minus black level enable for vadj2
+//Bit 2 Video adjustment enable for vadj2
+//Bit 1 minus black level enable for vadj1
+//Bit 0 Video adjustment enable for vadj1
+#define VPP_VADJ_CTRL ((0x1d40 << 2) + 0xff000000)
+//Bit 16:8 brightness, signed value
+//Bit 7:0 contrast, unsigned value, contrast from 0 <= contrast <2
+//`define VPP_VADJ1_Y 8'h41 //'h00080
+//cb' = cb*ma + cr*mb
+//cr' = cb*mc + cr*md
+//all are bit 9:0, signed value, -2 < ma/mb/mc/md < 2
+//`define VPP_VADJ1_MA_MB 8'h42 //26'h100_0000
+//`define VPP_VADJ1_MC_MD 8'h43 //26'h000_0100
+//Bit 16:8 brightness, signed value
+//Bit 7:0 contrast, unsigned value, contrast from 0 <= contrast <2
+//`define VPP_VADJ2_Y 8'h44 //'h00080
+//cb' = cb*ma + cr*mb
+//cr' = cb*mc + cr*md
+//all are bit 9:0, signed value, -2 < ma/mb/mc/md < 2
+//`define VPP_VADJ2_MA_MB 8'h45 //26'h100_0000
+//`define VPP_VADJ2_MC_MD 8'h46 //26'h000_0100
+//Bit 2 horizontal chroma sharp/blur selection, 0:sharp, 1: blur
+//Bit 1 horizontal luma sharp/blur selection, 0:sharp, 1: blur
+//Bit 0 horizontal sharpness enable
+#define VPP_HSHARP_CTRL ((0x1d50 << 2) + 0xff000000)
+//{1'b0,threhsold} < diff
+//Bit 26:16 luma threshold0
+//Bit 10:0 luma threshold1
+#define VPP_HSHARP_LUMA_THRESH01 ((0x1d51 << 2) + 0xff000000)
+//
+//Bit 26:16 luma threshold2
+//Bit 10:0 luma threshold3
+#define VPP_HSHARP_LUMA_THRESH23 ((0x1d52 << 2) + 0xff000000)
+//Bit 26:16 chroma threshold0
+//Bit 10:0 chroma threshold1
+#define VPP_HSHARP_CHROMA_THRESH01 ((0x1d53 << 2) + 0xff000000)
+//Bit 26:16 chroma threshold2
+//Bit 10:0 chroma threshold3
+#define VPP_HSHARP_CHROMA_THRESH23 ((0x1d54 << 2) + 0xff000000)
+//Bit 23:16 luma gain2
+//Bit 15:8 luma gain1
+//Bit 7:0 luma gain0
+#define VPP_HSHARP_LUMA_GAIN ((0x1d55 << 2) + 0xff000000)
+//
+//Bit 23:16 chroma gain2
+//Bit 15:8 chroma gain1
+//Bit 7:0 chroma gain0
+#define VPP_HSHARP_CHROMA_GAIN ((0x1d56 << 2) + 0xff000000)
+//Read only
+//Bit 31, if it is true, it means this probe is valid in the last field/frame
+//Bit 29:20 component 0
+//Bit 19:10 component 1
+//Bit 9:0 component 2
+#define VPP_MATRIX_PROBE_COLOR ((0x1d5c << 2) + 0xff000000)
+#define VPP_MATRIX_PROBE_COLOR1 ((0x1dd7 << 2) + 0xff000000)
+//Bit 23:16 component 0
+//Bit 15:8 component 1
+//Bit 7:0 component 2
+#define VPP_MATRIX_HL_COLOR ((0x1d5d << 2) + 0xff000000)
+//28:16 probe x, postion
+//12:0 probe y, position
+#define VPP_MATRIX_PROBE_POS ((0x1d5e << 2) + 0xff000000)
+//Bit 16, highlight_en
+//Bit 15 probe_post, if true, probe pixel data after matrix, otherwise probe pixel data before matrix
+//Bit 14:12 probe_sel, 000: select post matrix, 001: select vd1 matrix, 010: select vd2 matrix
+//Bit 9:8 matrix coef idx selection, 00: select post matrix, 01: select vd1 matrix, 10: select vd2 matrix
+//Bit 5 vd1 conversion matrix enable
+//Bit 4 vd2 conversion matrix enable
+//Bit 2 output y/cb/cr saturation enable, only for post matrix (y saturate to 16-235, cb/cr saturate to 16-240)
+//Bit 1 input y/cb/cr saturation enable, only for post matrix (y saturate to 16-235, cb/cr saturate to 16-240)
+//Bit 0 post conversion matrix enable
+#define VPP_MATRIX_CTRL ((0x1d5f << 2) + 0xff000000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define VPP_MATRIX_COEF00_01 ((0x1d60 << 2) + 0xff000000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define VPP_MATRIX_COEF02_10 ((0x1d61 << 2) + 0xff000000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define VPP_MATRIX_COEF11_12 ((0x1d62 << 2) + 0xff000000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define VPP_MATRIX_COEF20_21 ((0x1d63 << 2) + 0xff000000)
+#define VPP_MATRIX_COEF22 ((0x1d64 << 2) + 0xff000000)
+//Bit 26:16 offset0
+//Bit 10:0 offset1
+#define VPP_MATRIX_OFFSET0_1 ((0x1d65 << 2) + 0xff000000)
+//Bit 10:0 offset2
+#define VPP_MATRIX_OFFSET2 ((0x1d66 << 2) + 0xff000000)
+//Bit 26:16 pre_offset0
+//Bit 10:0 pre_offset1
+#define VPP_MATRIX_PRE_OFFSET0_1 ((0x1d67 << 2) + 0xff000000)
+//Bit 10:0 pre_offset2
+#define VPP_MATRIX_PRE_OFFSET2 ((0x1d68 << 2) + 0xff000000)
+// dummy data used in the VPP postblend
+// Bit 23:16 Y
+// Bit 15:8 CB
+// Bit 7:0 CR
+#define VPP_DUMMY_DATA1 ((0x1d69 << 2) + 0xff000000)
+//Bit 31 gainoff module enable
+//Bit 26:16 gain0, 1.10 unsigned data
+//Bit 10:0 gain1, 1.10 unsigned dat
+#define VPP_GAINOFF_CTRL0 ((0x1d6a << 2) + 0xff000000)
+//Bit 26:16 gain2, 1.10 unsigned data
+//Bit 10:0, offset0, signed data
+#define VPP_GAINOFF_CTRL1 ((0x1d6b << 2) + 0xff000000)
+//Bit 26:16, offset1, signed data
+//Bit 10:0, offset2, signed data
+#define VPP_GAINOFF_CTRL2 ((0x1d6c << 2) + 0xff000000)
+//Bit 26:16, pre_offset0, signed data
+//Bit 10:0, pre_offset1, signed data
+#define VPP_GAINOFF_CTRL3 ((0x1d6d << 2) + 0xff000000)
+//Bit 10:0, pre_offset2, signed data
+#define VPP_GAINOFF_CTRL4 ((0x1d6e << 2) + 0xff000000)
+#define VPP_GAINOFF_GCLK_CTRL ((0x1d6f << 2) + 0xff000000)
+//only two registers used in the color management, which are defined in the chroma_reg.h
+//`define VPP_CHROMA_ADDR_PORT 8'h70
+//`define VPP_CHROMA_DATA_PORT 8'h71
+//
+// Reading file: chroma_reg.h
+//
+//**********************************************************************************
+//* Copyright (c) 2008, AMLOGIC Inc.
+//* All rights reserved
+//**********************************************************************************
+//* File : chroma_reg.v
+//* Author : Terrence Wang
+//* Date : Dec 2008
+//* Description :
+//*
+//**********************************************************************************
+//* Modification History:
+//* Date Modified By Reason
+//**********************************************************************************
+// synopsys translate_off
+// synopsys translate_on
+#define VPP_CHROMA_ADDR_PORT ((0x1d70 << 2) + 0xff000000)
+#define VPP_CHROMA_DATA_PORT ((0x1d71 << 2) + 0xff000000)
+//`define CHROMA_ADDR_PORT 8'h67
+//`define CHROMA_DATA_PORT 8'h68
+
+// CHROMA_GAIN_REG_XX(00-07)
+// hue gain, sat gain function control
+// Bit 31 reg_sat_en enable sat adjustment in current region
+// Bit 27 reg_sat_increase sat adjustment increase or decrease
+// 1'b1: increase 1'b0: decrease
+// Bit 26:25 reg_sat_central_en sat adjustment with central biggest or one side biggest
+// 2'b01 central biggest 2'b00 one side biggest
+// Bit 24 reg_sat_shape when sat adjustment one side biggest, define left or right
+// 1'b1: left side biggest 1'b0 right side biggest
+// Bit 23:16 reg_sat_gain define the sat gain when sat adjustment
+// 0x00-0xff
+// Bit 15 reg_hue_en enable hue adjustment in current region
+// Bit 11 reg_hue_clockwise hue adjustment clockwise or anti-clockwise
+// 1'b1: clockwise 1'b0: anti-clockwise
+// Bit 10:9 reg_hue_central_en when hue adjustment, parabola curve or non-symmetry curve
+// 1'b1: parabola curve 1'b0: non-symmetry curve
+// Bit 8 reg_hue_shape when non-symmetry curve, define which side change more
+// 1'b1: right side change more 1'b0: left side change more
+// Bit 7:0 reg_hue_gain define the hue gain when hue adjustment
+// 0x00-0x80, note: should be no bigger than 0x80
+
+ #define CHROMA_GAIN_REG00 0x00
+
+
+// HUE_HUE_RANGE_REG_XX(00-07)
+// hue range select
+// Bit 31:24 no use now
+// Bit 23:16 reg_hue_shift_range define the angle of target region
+// 0x00-0xff,(0x100 means 120 degree though it can not be set)
+// must be greater or equal than 8'd8
+// Bit 15 reg_symmetry_en this is used for create one symmetry region
+// the symmetry region hue_shift_start = reg_hue_hue_shift_start + reg_hue_shift_range<<5
+// the symmetry region hue_shift_range = reg_hue_shift_range
+// in symmetry region, all the sat and hue setting will be same with original region,
+// except reg_hue_shape, reg_sat_shape, reg_hue_clockwise will be reversed
+// Bit 14:0 reg_hue_hue_shift_start define the start angle of target region
+// 0x6000 means 360 degree
+// only region 0 and 1 can exceed 360 degrees.
+
+ #define HUE_HUE_RANGE_REG00 0x01
+
+
+// HUE_RANGE_INV_REG_XX
+// Calculation should be follow
+// HUE_RANGE_INV_REG0X[15:0] = ((1<<20)/HUE_HUE_RANGE_REG0X[23:16]+1)>>1
+// HUE_RANGE_INV_REG_XX is to used to save divider
+
+ #define HUE_RANGE_INV_REG00 0x02
+
+
+
+// for belowing each low, high, low_slope, high_slope group:
+// a_____________b
+// / \ a = low + 2^low_slope
+// / \ b = high - 2^high_slope
+// / \ low_slope <= 7; high_slope <= 7
+// / \ b >= a
+// ______/_____________________\________
+// low high
+//
+//
+// HUE_LUM_RANGE_REG_XX(00-07)
+// luma range selection for hue adjustment
+// Bit 31:24 reg_sat_lum_low define the low level of luma value for sat adjustment
+// 0x00-0xff
+// Bit 23:20 reg_hue_lum_high_slope define the slope area below high level of luma value for hue adjustment
+// 0x00-0x07
+// Bit 19:16 reg_hue_lum_low_slope define the slope area above low level of luma value for hue adjustment
+// 0x00-0x07
+// Bit 15:8 reg_hue_lum_high define the high level of luma value for hue adjustment
+// 0x00-0xff
+// Bit 7:0 reg_hue_lum_low define the low level of luma value for hue adjustment
+// 0x00-0xff
+
+ #define HUE_LUM_RANGE_REG00 0x03
+
+// HUE_SAT_RANGE_REG_XX(00-07)
+// sat range selection for hue adjustment
+// Bit 31:24 reg_sat_lum_high define the high level of luma value for sat adjustment
+// 0x00-0xff
+// Bit 23:20 reg_hue_sat_high_slope define the slope area below high level of sat value for hue adjustment
+// 0x00-0x07
+// Bit 19:16 reg_hue_sat_low_slope define the slope area above low level of sat value for hue adjustment
+// 0x00-0x07
+// Bit 15:8 reg_hue_sat_high define the high level of sat value for hue adjustment
+// 0x00-0xff
+// Bit 7:0 reg_hue_sat_low define the low level of sat value for hue adjustment
+// 0x00-0xff
+
+ #define HUE_SAT_RANGE_REG00 0x04
+
+// SAT_SAT_RANGE_REG_XX(00-07)
+// sat range selection for hue adjustment
+// Bit 31:28 reg_sat_lum_high_slope define the slope area below high level of luma value for sat adjustment
+// 0x00-0x07
+// Bit 27:24 reg_sat_lum_low_slope define the slope area above low level of luma value for sat adjustment
+// 0x00-0x07
+// Bit 23:20 reg_sat_sat_high_slope define the slope area below high level of sat value for sat adjustment
+// 0x00-0x07
+// Bit 19:16 reg_sat_sat_low_slope define the slope area above low level of sat value for sat adjustment
+// 0x00-0x07
+// Bit 15:8 reg_sat_sat_high define the high level of sat value for sat adjustment
+// 0x00-0xff
+// Bit 7:0 reg_sat_sat_low define the low level of sat value for sat adjustment
+// 0x00-0xff
+
+ #define SAT_SAT_RANGE_REG00 0x05
+
+
+ #define CHROMA_GAIN_REG01 0x06
+ #define HUE_HUE_RANGE_REG01 0x07
+ #define HUE_RANGE_INV_REG01 0x08
+ #define HUE_LUM_RANGE_REG01 0x09
+ #define HUE_SAT_RANGE_REG01 0x0a
+ #define SAT_SAT_RANGE_REG01 0x0b
+
+ #define CHROMA_GAIN_REG02 0x0c
+ #define HUE_HUE_RANGE_REG02 0x0d
+ #define HUE_RANGE_INV_REG02 0x0e
+ #define HUE_LUM_RANGE_REG02 0x0f
+ #define HUE_SAT_RANGE_REG02 0x10
+ #define SAT_SAT_RANGE_REG02 0x11
+
+
+ #define CHROMA_GAIN_REG03 0x12
+ #define HUE_HUE_RANGE_REG03 0x13
+ #define HUE_RANGE_INV_REG03 0x14
+ #define HUE_LUM_RANGE_REG03 0x15
+ #define HUE_SAT_RANGE_REG03 0x16
+ #define SAT_SAT_RANGE_REG03 0x17
+
+ #define CHROMA_GAIN_REG04 0x18
+ #define HUE_HUE_RANGE_REG04 0x19
+ #define HUE_RANGE_INV_REG04 0x1a
+ #define HUE_LUM_RANGE_REG04 0x1b
+ #define HUE_SAT_RANGE_REG04 0x1c
+ #define SAT_SAT_RANGE_REG04 0x1d
+
+ #define CHROMA_GAIN_REG05 0x1e
+ #define HUE_HUE_RANGE_REG05 0x1f
+ #define HUE_RANGE_INV_REG05 0x20
+ #define HUE_LUM_RANGE_REG05 0x21
+ #define HUE_SAT_RANGE_REG05 0x22
+ #define SAT_SAT_RANGE_REG05 0x23
+
+ #define CHROMA_GAIN_REG06 0x24
+ #define HUE_HUE_RANGE_REG06 0x25
+ #define HUE_RANGE_INV_REG06 0x26
+ #define HUE_LUM_RANGE_REG06 0x27
+ #define HUE_SAT_RANGE_REG06 0x28
+ #define SAT_SAT_RANGE_REG06 0x29
+
+ #define CHROMA_GAIN_REG07 0x2a
+ #define HUE_HUE_RANGE_REG07 0x2b
+ #define HUE_RANGE_INV_REG07 0x2c
+ #define HUE_LUM_RANGE_REG07 0x2d
+ #define HUE_SAT_RANGE_REG07 0x2e
+ #define SAT_SAT_RANGE_REG07 0x2f
+
+// REG_CHROMA_CONTROL
+// Bit 31 reg_chroma_en enable color manage function
+// 1'b1: enable 1'b0: bypass
+// Bit 6 sat_sel uv_max or u^2+v^2 selected as sat for reference
+// 1'b1: uv_max(default) 1'b0: u^2+v^2
+// Bit 5 uv_adj_en final uv_adjust enable
+// 1'b1: enable 1'b0: bypass
+// Bit 2 hue_en rgb to hue enable
+// 1'b1: enable(default) 1'b0: bypass
+// Bit 1:0 csc_sel define input YUV with different color type
+// 2'b00: 601(16-235) 2'b01: 709(16-235)
+// 2'b10: 601(0-255) 2'b11: 709(0-255)
+ #define REG_CHROMA_CONTROL 0x30 // default 32h'80000024
+ #define REG_DEMO_CENTER_BAR 0x31 // default 32h'0
+ #define REG_DEMO_HLIGHT_MODE 0x32 // default 32h'0
+ #define REG_DEMO_OWR_DATA 0x33 // default 32h'0
+
+
+////===========================================////
+//// CM2 ADDR
+////===========================================////
+
+ #define SAT_BYYB_NODE_REG0 0x200 // default 32'h0
+//Bit 31:24, sat_byyb_node3 the 4th node
+//Bit 23:16, sat_byyb_node2 the 3th node
+//Bit 15: 8, sat_byyb_node1 signed, the 2th node about saturation
+//Bit 7: 0, sat_byyb_node0 signed, the 1th node about saturation
+//gain offset along y coordinate,the gain normalized to 128 as "1"
+
+ #define SAT_BYYB_NODE_REG1 0x201 // default 32'h0
+//Bit 31:24, sat_byyb_node7 the 8th node
+//Bit 23:16, sat_byyb_node6 the 7th node
+//Bit 15: 8, sat_byyb_node5 signed, the 6th node about saturation
+//Bit 7: 0, sat_byyb_node4 signed, the 5th node about saturation
+//gain offset along y coordinate,the gain normalized to 128 as "1"
+
+ #define SAT_BYYB_NODE_REG2 0x202 // default 32'h0
+//Bit 31: 8, reserved
+//Bit 7: 0, sat_byyb_node4 signed, the 5th node about saturation
+
+
+ #define SAT_SRC_NODE_REG 0x203 // default 32'h0
+//Bit 31:28, reserved
+//Bit 27:16, sat_src_node1
+//Bit 15:12, reserved
+//Bit 11: 0, sat_src_node0 usigned, threshold of input saturation for first and second piece
+
+ #define CM_ENH_SFT_MODE_REG 0x204 // default 32'h0
+//Bit 31: 9, reserved
+//Bit 8: 6, hue_lsft_mode hue offset adjustments scale
+//Bit 5: 4, luma_lsft_mode luma offset adjustments scale for reg_cm2_adj_luma_via_hue
+//Bit 3: 2, sat_byy_rsft_mode saturation gain adjustments scale for reg_cm2_adj_sat_via_y
+//Bit 1: 0, sat_byhs_rsft_mode saturation gain adjustments scale for reg_cm2_adj_sat_via_hs[:][:] 0:no scale up/down 1:dnscale by 2(-128,127)/2
+
+ #define FRM_SIZE_REG 0x205 // default 32'h0
+//Bit 31:29, reserved
+//Bit 28:16, reg_frm_height the frame height size
+//Bit 15:13, reserved
+//Bit 12: 0, reg_frm_width the frame width size
+
+ #define FITLER_CFG_REG 0x206 // default 32'h0
+//Bit 31: 5, reserved
+//Bit 4: 4, inteleav_mod horizontal interleave filter(zero-padding) for 3D considerations 0:using non-zero padding lpf 1:using zero-padding lpf
+//Bit 3: 2, lpf_slt_uv apply cm on lp portion or original video pixels options
+//Bit 1: 0, lpf_slt_y apply cm on lp portion or original video pixels options
+
+ #define CM_GLOBAL_GAIN_REG 0x207 // default 32'h0
+//Bit 31:28, reserved
+//Bit 27:16, cm2_global_sat global saturation gain for general color adjustments(0~4095 <=> 0~8),512 normalized to "1"
+//Bit 15:12, reserved
+//Bit 11: 0, cm2_global_hue global hue offsets for general color adjustments(0~4095 <=> 0~360 degree)
+
+ #define CM_ENH_CTL_REG 0x208 // default 32'h0
+//Bit 31:7, reserved
+//Bit 6, hue_adj_en cm2 hue adjustments
+//Bit 5, sat_adj_en cm2 saturation adjustments
+//Bit 4, luma_adj_en enable siganl for cm2 luma adjustments
+//Bit 3, reserved
+//Bit 2, cm2_filt_en apply cm on lp portion enable
+//Bit 1, cm2_en cm2 enable siganl
+//Bit 0, cm1_en
+
+ #define ROI_X_SCOPE_REG 0x209 // default 32'h0
+//Bit 31:29, reserved
+//Bit 28:16, roi_x_end ending col index of the region of interest
+//Bit 15:13, reserved
+//Bit 12: 0, roi_x_beg start col index of the region of interest
+
+ #define ROI_Y_SCOPE_REG 0x20a // default 32'h0
+//Bit 31:29, reserved
+//Bit 28:16, roi_y_end ending row index of the region of interest
+//Bit 15:13, reserved
+//Bit 12: 0, roi_y_beg start row index of the region of interest
+
+ #define POI_XY_DIR_REG 0x20b // default 32'h0
+//Bit 31:29, reserved
+//Bit 28:16, poi_y_dir ending row index of the region of interest
+//Bit 15:13, reserved
+//Bit 12: 0, poi_x_dir start row index of the region of interest
+
+ #define COI_Y_SCOPE_REG 0x20c // default 32'h0
+//Bit 31:16, reserved
+//Bit 15: 8, coi_y_end
+//Bit 7: 0, coi_y_beg
+
+ #define COI_H_SCOPE_REG 0x20d // default 32'h0
+//Bit 31:28, reserved
+//Bit 27:16, coi_h_end
+//Bit 15:12, reserved
+//Bit 11: 0, coi_h_beg lower bound of hue value for color of interest ,12 bits precision
+
+ #define COI_S_SCOPE_REG 0x20e // default 32'h0
+//Bit 31:28, reserved
+//Bit 27:16, coi_s_end
+//Bit 15:12, reserved
+//Bit 11: 0, coi_s_beg lower bound of sat value for color of interest ,12 bits precision
+ #define IFO_MODE_REG 0x20f // default 32'h0
+//Bit 31:8, reserved
+//Bit 7:6, ifo_mode3
+//Bit 5:4, ifo_mode2
+//Bit 3:2, ifo_mode1
+//Bit 1:0, ifo_mode0
+ #define POI_RPL_MODE_REG 0x210 // default 32'h0
+//Bit 31:4, reserved
+//Bit 3:0, poi_rpl_mode enhance mode control of pixels inside and outside region of interest bit[3:2]control roi
+ #define DEMO_OWR_YHS_REG 0x211 // default 32'h0
+//Bit 31: 0, demo_owr_yhs
+
+ #define DEMO_POI_Y_REG 0x212 // default 32'h0
+//Bit 31: 8, reserved
+//Bit 7: 0, luma_data_poi_r only get locked higher 8bits
+ #define DEMO_POI_H_REG 0x213 // default 32'h0
+//Bit 31: 12, reserved
+//Bit 11: 0, hue_data_poi_r only get locked higher 12bits
+ #define DEMO_POI_S_REG 0x214 // default 32'h0
+//Bit 31: 12, reserved
+//Bit 11: 0, sat_data_poi_r only get locked higher 12bits
+ //`define LUMA_BYH_LIMT_REG 10'h215 // default 32'h0
+ #define LUMA_ADJ_LIMT_REG 0x215 // default 32'h0
+//Bit 31:24, reserved
+//Bit 23:16, luma_lmt_satslp slope to do the luma adjustment degrade
+//Bit 15:12, reserved
+//Bit 11:0, luma_lmt_satth threshold to saturation
+ #define SAT_ADJ_LIMT_REG 0x216 // default 32'h0
+//Bit 31:24, reserved
+//Bit 23:16, sat_lmt_satslp slope to do the adjustment degrade
+//Bit 15:12, reserved
+//Bit 11:0, sat_lmt_satth threshold to saturation
+ #define HUE_ADJ_LIMT_REG 0x217 // default 32'h0
+//Bit 31: 24, reserved
+//Bit 23: 16, hue_lmt_satslp slope to do the adjustment degrade
+//Bit 15: 12, reserved
+//Bit 11: 0, hue_lmt_satth threshold to saturation
+ #define UVHS_OFST_REG 0x218 // default 32'h0
+//Bit 31: 24, hs2uv_v_ofst
+//Bit 23: 16, hs2uv_u_ofst
+//Bit 15: 8, uv2hs_v_ofst
+//Bit 7: 0, uv2hs_u_ofst
+ #define HUE_CFG_PARA_REG 0x219 // default 32'h0
+//Bit 31: 17, reserved
+//Bit 16, hue_protect_en
+//Bit 15: 13, cm2_hue_byhs_mode
+//Bit 12, cm2_hue_div_mode
+//Bit 11: 0, cm2_before_hue_ofst
+ #define DEMO_SPLT_CFG_REG 0x21a // default 32'h0
+//Bit 31: 22, reserved
+//Bit 21: 20, demo_split_mode
+//Bit 19: 16, demo_split_width slope to do the adjustment degrade
+//Bit 15: 13, reserved
+//Bit 12: 0, demo_split_post threshold to saturation
+ #define DEMO_SPLT_YHS_REG 0x21b // default 32'h0
+//Bit 31: 0, demo_splt_yhs threshold to saturation
+
+ #define XVYCC_YSCP_REG 0x21c // default 32'h0
+//Bit 31: 28, reserved
+//Bit 27: 16, xvycc_y_max
+//Bit 15: 12, reserved
+//Bit 11: 0, xvycc_y_min
+ #define XVYCC_USCP_REG 0x21d // default 32'h0
+//Bit 31: 28, reserved
+//Bit 27: 16, xvycc_u_max
+//Bit 15: 12, reserved
+//Bit 11: 0, xvycc_u_min
+ #define XVYCC_VSCP_REG 0x21e // default 32'h0
+//Bit 31: 28, reserved
+//Bit 27: 16, xvycc_v_max
+//Bit 15: 12, reserved
+//Bit 11: 0, xvycc_v_min
+ #define LUMA_ADJ0_REG 0x21f // default 32'h0
+//Bit 21: 12, reg_cm_luma_blacklevel
+//Bit 11: 0, reg_cm_luma_contrast
+ #define LUMA_ADJ1_REG 0x220 // default 32'h0
+
+ #define STA_WIN_XYXY0_REG 0x221 // default 32'h0
+ #define STA_WIN_XYXY1_REG 0x222 // default 32'h0
+ #define STA_CFG_REG 0x223 // default 32'h0
+ #define STA_SAT_HIST0_REG 0x224 // default 32'h0
+ #define STA_SAT_HIST1_REG 0x225 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN0 0x226 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN1 0x227 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN2 0x228 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN3 0x229 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN4 0x22a // default 32'h0
+ #define RO_CM_HUE_HIST_BIN5 0x22b // default 32'h0
+ #define RO_CM_HUE_HIST_BIN6 0x22c // default 32'h0
+ #define RO_CM_HUE_HIST_BIN7 0x22d // default 32'h0
+ #define RO_CM_HUE_HIST_BIN8 0x22e // default 32'h0
+ #define RO_CM_HUE_HIST_BIN9 0x22f // default 32'h0
+ #define RO_CM_HUE_HIST_BIN10 0x230 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN11 0x231 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN12 0x232 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN13 0x233 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN14 0x234 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN15 0x235 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN16 0x236 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN17 0x237 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN18 0x238 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN19 0x239 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN20 0x23a // default 32'h0
+ #define RO_CM_HUE_HIST_BIN21 0x23b // default 32'h0
+ #define RO_CM_HUE_HIST_BIN22 0x23c // default 32'h0
+ #define RO_CM_HUE_HIST_BIN23 0x23d // default 32'h0
+ #define RO_CM_HUE_HIST_BIN24 0x23e // default 32'h0
+ #define RO_CM_HUE_HIST_BIN25 0x23f // default 32'h0
+ #define RO_CM_HUE_HIST_BIN26 0x240 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN27 0x241 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN28 0x242 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN29 0x243 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN30 0x244 // default 32'h0
+ #define RO_CM_HUE_HIST_BIN31 0x245 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN0 0x246 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN1 0x247 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN2 0x248 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN3 0x249 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN4 0x24a // default 32'h0
+ #define RO_CM_SAT_HIST_BIN5 0x24b // default 32'h0
+ #define RO_CM_SAT_HIST_BIN6 0x24c // default 32'h0
+ #define RO_CM_SAT_HIST_BIN7 0x24d // default 32'h0
+ #define RO_CM_SAT_HIST_BIN8 0x24e // default 32'h0
+ #define RO_CM_SAT_HIST_BIN9 0x24f // default 32'h0
+ #define RO_CM_SAT_HIST_BIN10 0x250 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN11 0x251 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN12 0x252 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN13 0x253 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN14 0x254 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN15 0x255 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN16 0x256 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN17 0x257 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN18 0x258 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN19 0x259 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN20 0x25a // default 32'h0
+ #define RO_CM_SAT_HIST_BIN21 0x25b // default 32'h0
+ #define RO_CM_SAT_HIST_BIN22 0x25c // default 32'h0
+ #define RO_CM_SAT_HIST_BIN23 0x25d // default 32'h0
+ #define RO_CM_SAT_HIST_BIN24 0x25e // default 32'h0
+ #define RO_CM_SAT_HIST_BIN25 0x25f // default 32'h0
+ #define RO_CM_SAT_HIST_BIN26 0x260 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN27 0x261 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN28 0x262 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN29 0x263 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN30 0x264 // default 32'h0
+ #define RO_CM_SAT_HIST_BIN31 0x265 // default 32'h0
+ #define RO_CM_BLK_BIN 0x266 // default 32'h0
+ #define RO_CM_BRT_BIN 0x267 // default 32'h0
+
+////========= NODE 0 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H00 0x100 // default 32'H0
+//Bit 31: 24, reg_cm2_adj_sat_via_hs_2
+//Bit 23: 16, reg_cm2_adj_sat_via_hs_1
+//Bit 15: 8, reg_cm2_adj_sat_via_hs_0
+//Bit 7: 0, reg_cm2_adj_luma_via_h
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H00 0x101 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H00 0x102 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H00 0x103 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H00 0x104 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 1 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H01 0x108 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H01 0x109 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H01 0x10a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H01 0x10b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H01 0x10c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 2 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H02 0x110 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H02 0x111 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H02 0x112 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H02 0x113 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H02 0x114 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 3 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H03 0x118 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H03 0x119 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H03 0x11a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H03 0x11b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H03 0x11c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 4 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H04 0x120 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H04 0x121 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H04 0x122 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H04 0x123 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H04 0x124 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 5 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H05 0x128 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H05 0x129 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H05 0x12a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H05 0x12b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H05 0x12c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 6 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H06 0x130 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H06 0x131 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H06 0x132 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H06 0x133 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H06 0x134 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 7 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H07 0x138 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H07 0x139 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H07 0x13a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H07 0x13b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H07 0x13c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 8 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H08 0x140 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H08 0x141 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H08 0x142 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H08 0x143 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H08 0x144 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 9 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H09 0x148 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H09 0x149 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H09 0x14a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H09 0x14b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H09 0x14c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 10 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H10 0x150 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H10 0x151 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H10 0x152 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H10 0x153 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H10 0x154 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 11 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H11 0x158 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H11 0x159 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H11 0x15a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H11 0x15b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H11 0x15c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 12 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H12 0x160 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H12 0x161 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H12 0x162 // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H12 0x163 // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H12 0x164 // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+////========= NODE 13 COEFFICIENT ==============////
+
+ #define REG_CM2_ENH_COEFF0_H13 0x168 // default 32'H0
+ // [ 7: 0] : luma_byh_hx / [15: 8] : sat_byhs_s0hx
+ // [23:16] : sat_byhs_s0hx / [31:24] : sat_byhs_s2hx
+ #define REG_CM2_ENH_COEFF1_H13 0x169 // default 32'H0
+ // [ 7: 0] : hue_byh_hx / [15: 8] : hue_byy_y0hx
+ // [23:16] : hue_byy_y1hx / [31:24] : hue_byy_y2hx
+ #define REG_CM2_ENH_COEFF2_H13 0x16a // default 32'H0
+ // [ 7: 0] : hue_byy_y3hx / [15: 8] : hue_byy_y4hx
+ // [23:16] : hue_bys_s0hx / [31:24] : hue_bys_s1hx
+ #define REG_CM2_ENH_COEFF3_H13 0x16b // default 32'H0
+ // [ 7: 0] : hue_bys_s2hx / [15: 8] : hue_bys_s3hx
+ // [23:16] : hue_bys_s4hx / [31:24] : hue_byya_y0hx
+ #define REG_CM2_ENH_COEFF4_H13 0x16c // default 32'H0
+ // [ 7: 0] : hue_byya_y1hx / [15: 8] : hue_byya_y2hx
+ // [23:16] : hue_byya_y3hx / [31:24] : hue_byya_y4hx
+
+
+/* Constraints
+0)
+ there are 16 regions totally. 8 regions are for hue adjustment, 8 regions are for sat adjustment.
+ the hue range of the 16 regions can be set to overlap, but if overlap, the hue range(start and end) must be same.
+ the 8 regions for hue adjustment should not overlap. if corresponding reg_hue_en_00 - 07 == 1
+ the 8 regions for hue adjustment are defined by: (example are for region 0)
+ a) hue:
+ start: reg_hue_hue_shift_start_00[14:0]
+ end:
+ if reg_symmetry_en_00 == 0
+ reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<5)
+ if reg_symmetry_en_00 == 1
+ reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<6)
+ b) sat:
+ start: reg_hue_sat_low_00
+ end: reg_hue_sat_high_00
+
+ the 8 regions for sat adjustment should not overlap. if corresponding reg_sat_en_00 - 07 == 1
+ the 8 regions for sat adjustment are defined by: (example are for region 0)
+ a) hue: same as that for hue adjustment.
+ start: reg_hue_hue_shift_start_00[14:0]
+ end:
+ if reg_symmetry_en_00 == 0
+ reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<5)
+ if reg_symmetry_en_00 == 1
+ reg_hue_hue_shift_start_00[14:0] + (reg_hue_hue_shift_range_00[7:0]<<6)
+ b) sat:
+ start: reg_sat_sat_low_00
+ end: reg_sat_sat_high_00
+
+1)
+ reg_hue_hue_shift_range_00[7:0]:
+ reg_hue_hue_shift_range_01[7:0]:
+ reg_hue_hue_shift_range_02[7:0]:
+ reg_hue_hue_shift_range_03[7:0]:
+ reg_hue_hue_shift_range_04[7:0]:
+ reg_hue_hue_shift_range_05[7:0]:
+ reg_hue_hue_shift_range_06[7:0]:
+ reg_hue_hue_shift_range_07[7:0]:
+ must be greater or equal than 8'd8, so as reg_hue_range_inv_regxx can be represented by 0.0000_0000_xxxx_xxxx_xxxx_xxxx
+
+2)
+ all regions of 0-7 should meet below requirement. below is just an example for region 7.
+ (reg_hue_lum_high_07 - reg_hue_lum_low_07) >=
+ (1<<reg_hue_lum_low_slope_07) + (1<<reg_hue_lum_high_slope_07)
+
+ (reg_hue_sat_high_07 - reg_hue_sat_low_07) >=
+ (1<<reg_hue_sat_low_slope_07) + (1<<reg_hue_sat_high_slope_07)
+
+ (reg_sat_lum_high_07 - reg_sat_lum_low_07) >=
+ (1<<reg_sat_lum_low_slope_07) + (1<<reg_sat_lum_high_slope_07)
+
+ (reg_sat_sat_high_07 - reg_sat_sat_low_07) >=
+ (1<<reg_sat_sat_low_slope_07) + (1<<reg_sat_sat_high_slope_07)
+
+3)
+ all of reg_hue_hue_shift_start_00[14:0] ~ 07[14:0] < 0x6000.
+ only region 0 and 1 can exceed 360 degrees. ie:
+ reg_hue_hue_shift_start_00 + (reg_hue_hue_shift_range_00<<5) can greater than 0x6000.
+ reg_hue_hue_shift_start_01 + (reg_hue_hue_shift_range_01<<5) can greater than 0x6000.
+ but below should be met:
+ reg_hue_hue_shift_start_00 + (reg_hue_hue_shift_range_00<<5) < 0x8000. if reg_symmetry_en_00 == 0
+ reg_hue_hue_shift_start_01 + (reg_hue_hue_shift_range_00<<5) < 0x8000. if reg_symmetry_en_00 == 0
+ reg_hue_hue_shift_start_00 + (reg_hue_hue_shift_range_00<<6) < 0x8000. if reg_symmetry_en_00 == 1
+ reg_hue_hue_shift_start_01 + (reg_hue_hue_shift_range_00<<6) < 0x8000. if reg_symmetry_en_00 == 1
+
+ others could not exceed 360 degrees. ie:
+ reg_hue_hue_shift_start_02(to 7) + (reg_hue_hue_shift_range_02 (to 7) <<5) < 0x6000. if reg_symmetry_en_02 (to 7) == 0.
+ reg_hue_hue_shift_start_02(to 7) + (reg_hue_hue_shift_range_02 (to 7) <<6) < 0x6000. if reg_symmetry_en_02 (to 7) == 1.
+
+4)
+ reg_hue_gain_00[7:0] <= 0x80.
+ reg_hue_gain_01[7:0] <= 0x80.
+ reg_hue_gain_02[7:0] <= 0x80.
+ reg_hue_gain_03[7:0] <= 0x80.
+ reg_hue_gain_04[7:0] <= 0x80.
+ reg_hue_gain_05[7:0] <= 0x80.
+ reg_hue_gain_06[7:0] <= 0x80.
+ reg_hue_gain_07[7:0] <= 0x80.
+
+5)
+ below registers can only have two setting: 00 and 01.
+ reg_hue_central_en_00[1:0] .. _07[1:0]
+ reg_sat_central_en_00[1:0] .. _07[1:0]
+
+6)
+ all reg_..._slope_00-07 should not be greater than 7, ie: maximum value is 7.
+ for example: below is for region 0:
+ reg_hue_lum_low_slope_00[3:0] <= 7
+ reg_hue_lum_high_slope_00[3:0] <= 7
+ reg_hue_sat_low_slope_00[3:0] <= 7
+ reg_hue_sat_high_slope_00[3:0] <= 7
+ reg_sat_lum_low_slope_00[3:0] <= 7
+ reg_sat_lum_high_slope_00[3:0] <= 7
+ reg_sat_sat_low_slope_00[3:0] <= 7
+ reg_sat_sat_high_slope_00[3:0] <= 7
+*/
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: chroma_reg.h
+//
+//(hsvsharp), (blue), gainoff, mat_vd1,mat_vd2, mat_post, prebld, postbld,(hsharp),sco_ff, vadj1, vadj2, ofifo, (chroma1), clk0(free_clk) vpp_reg
+//each item 2bits, for each 2bits, if bit 2*i+1 == 1, free clk, else if bit 2*i == 1 no clk, else auto gated clock
+//bit1 is not used, because I can not turn off vpp_reg clk because I can not turn on again
+//because the register itself canot be set again without clk
+//Bit 31:0
+#define VPP_GCLK_CTRL0 ((0x1d72 << 2) + 0xff000000)
+//(front_lti), (front_cti), Chroma2_filter, Chroma2, (Ccoring), (blackext), dnlp
+//Bit 13:0
+#define VPP_GCLK_CTRL1 ((0x1d73 << 2) + 0xff000000)
+//prehsc_clk, line_buf, prevsc, vsc, hsc_clk, clk0(free_clk)
+//Bit 11:0
+//`define VPP_SC_GCLK_CTRL 8'h74
+//Bit 17:9 VD1 alpha for preblend
+//Bit 8:0 VD1 alpha for postblend
+#define VPP_MISC1 ((0x1d76 << 2) + 0xff000000)
+//Bit 31:0 super scalar clock control
+#define VPP_SRSCL_GCLK_CTRL ((0x1d77 << 2) + 0xff000000)
+//Bit 31:0 OSD super scalar clock control
+#define VPP_OSDSR_GCLK_CTRL ((0x1d78 << 2) + 0xff000000)
+//Bit 31:0 vvycc clock control
+#define VPP_XVYCC_GCLK_CTRL ((0x1d79 << 2) + 0xff000000)
+//Bit 8:0 VD3 alpha for postblend
+#define VPP_MISC2 ((0x1d7a << 2) + 0xff000000)
+//Bit 31:24 blackext_start
+//Bit 23:16 blackext_slope1
+//Bit 15:8 blackext_midpt
+//Bit 7:0 blackext_slope2
+#define VPP_BLACKEXT_CTRL ((0x1d80 << 2) + 0xff000000)
+//Bit 31:24 bottom of region03 output value
+//Bit 23:16 bottom of region02 output value
+//Bit 15:8 bottom of region01 output value
+//Bit 7:0 bottom of region00 output value
+#define VPP_DNLP_CTRL_00 ((0x1d81 << 2) + 0xff000000)
+//Bit 31:24 bottom of region07 output value
+//Bit 23:16 bottom of region06 output value
+//Bit 15:8 bottom of region05 output value
+//Bit 7:0 bottom of region04 output value
+#define VPP_DNLP_CTRL_01 ((0x1d82 << 2) + 0xff000000)
+//Bit 31:24 bottom of region11 output value
+//Bit 23:16 bottom of region10 output value
+//Bit 15:8 bottom of region09 output value
+//Bit 7:0 bottom of region08 output value
+#define VPP_DNLP_CTRL_02 ((0x1d83 << 2) + 0xff000000)
+//Bit 31:24 bottom of region15 output value
+//Bit 23:16 bottom of region14 output value
+//Bit 15:8 bottom of region13 output value
+//Bit 7:0 bottom of region12 output value
+#define VPP_DNLP_CTRL_03 ((0x1d84 << 2) + 0xff000000)
+//Bit 31:24 bottom of region19 output value
+//Bit 23:16 bottom of region18 output value
+//Bit 15:8 bottom of region17 output value
+//Bit 7:0 bottom of region16 output value
+#define VPP_DNLP_CTRL_04 ((0x1d85 << 2) + 0xff000000)
+//Bit 31:24 bottom of region23 output value
+//Bit 23:16 bottom of region22 output value
+//Bit 15:8 bottom of region21 output value
+//Bit 7:0 bottom of region20 output value
+#define VPP_DNLP_CTRL_05 ((0x1d86 << 2) + 0xff000000)
+//Bit 31:24 bottom of region27 output value
+//Bit 23:16 bottom of region26 output value
+//Bit 15:8 bottom of region25 output value
+//Bit 7:0 bottom of region24 output value
+#define VPP_DNLP_CTRL_06 ((0x1d87 << 2) + 0xff000000)
+//Bit 31:24 bottom of region31 output value
+//Bit 23:16 bottom of region30 output value
+//Bit 15:8 bottom of region29 output value
+//Bit 7:0 bottom of region28 output value
+#define VPP_DNLP_CTRL_07 ((0x1d88 << 2) + 0xff000000)
+//Bit 31:24 bottom of region35 output value
+//Bit 23:16 bottom of region34 output value
+//Bit 15:8 bottom of region33 output value
+//Bit 7:0 bottom of region32 output value
+#define VPP_DNLP_CTRL_08 ((0x1d89 << 2) + 0xff000000)
+//Bit 31:24 bottom of region39 output value
+//Bit 23:16 bottom of region38 output value
+//Bit 15:8 bottom of region37 output value
+//Bit 7:0 bottom of region36 output value
+#define VPP_DNLP_CTRL_09 ((0x1d8a << 2) + 0xff000000)
+//Bit 31:24 bottom of region43 output value
+//Bit 23:16 bottom of region42 output value
+//Bit 15:8 bottom of region41 output value
+//Bit 7:0 bottom of region40 output value
+#define VPP_DNLP_CTRL_10 ((0x1d8b << 2) + 0xff000000)
+//Bit 31:24 bottom of region47 output value
+//Bit 23:16 bottom of region46 output value
+//Bit 15:8 bottom of region45 output value
+//Bit 7:0 bottom of region44 output value
+#define VPP_DNLP_CTRL_11 ((0x1d8c << 2) + 0xff000000)
+//Bit 31:24 bottom of region51 output value
+//Bit 23:16 bottom of region50 output value
+//Bit 15:8 bottom of region49 output value
+//Bit 7:0 bottom of region48 output value
+#define VPP_DNLP_CTRL_12 ((0x1d8d << 2) + 0xff000000)
+//Bit 31:24 bottom of region55 output value
+//Bit 23:16 bottom of region54 output value
+//Bit 15:8 bottom of region53 output value
+//Bit 7:0 bottom of region52 output value
+#define VPP_DNLP_CTRL_13 ((0x1d8e << 2) + 0xff000000)
+//Bit 31:24 bottom of region59 output value
+//Bit 23:16 bottom of region58 output value
+//Bit 15:8 bottom of region57 output value
+//Bit 7:0 bottom of region56 output value
+#define VPP_DNLP_CTRL_14 ((0x1d8f << 2) + 0xff000000)
+//Bit 31:24 bottom of region63 output value
+//Bit 23:16 bottom of region62 output value
+//Bit 15:8 bottom of region61 output value
+//Bit 7:0 bottom of region60 output value
+#define VPP_DNLP_CTRL_15 ((0x1d90 << 2) + 0xff000000)
+// `define VPP_PEAKING_HGAIN 8'h91 //32'h0
+// `define VPP_PEAKING_VGAIN 8'h92 //32'h0
+// `define VPP_PEAKING_NLP_1 8'h93 //32'h0
+// `define VPP_PEAKING_NLP_2 8'h94 //32'h0
+// `define VPP_PEAKING_NLP_3 8'h95 //32'h0
+// `define VPP_PEAKING_NLP_4 8'h96 //32'h0
+// `define VPP_PEAKING_NLP_5 8'h97 //32'h0
+// `define VPP_SHARP_LIMIT 8'h98 //32'h0
+// `define VPP_VLTI_CTRL 8'h99 //32'h0
+// `define VPP_HLTI_CTRL 8'h9a //32'h0
+// `define VPP_CTI_CTRL 8'h9b //32'h0
+#define VPP_SRSHARP0_CTRL ((0x1d91 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 srsharp_demo_split_sz srsharp demo top/bot left/right width
+//Bit 15:6 reserved
+//Bit 5:4 srsharp_demo_disp_post srsharp demo display postion
+//Bit 3 srsharp_demo_en srsharp demo enable
+//Bit 2 srsharp_c444to422_en srsharp format444 convert 422 enable
+//Bit 1, srsharp_buf_en srsharp buffer enable
+//Bit 0, srsharp_en srsharp enable
+#define VPP_SRSHARP1_CTRL ((0x1d92 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 srsharp_demo_split_sz srsharp demo top/bot left/right width
+//Bit 15:6 reserved
+//Bit 5:4 srsharp_demo_disp_post srsharp demo display postion
+//Bit 3 srsharp_demo_en srsharp demo enable
+//Bit 2 srsharp_c444to422_en srsharp format444 convert 422 enable
+//Bit 1, srsharp_buf_en srsharp buffer enable
+//Bit 0, srsharp_en srsharp enable
+#define VPP_DOLBY_CTRL ((0x1d93 << 2) + 0xff000000)
+//todo
+#define VPP_DAT_CONV_PARA0 ((0x1d94 << 2) + 0xff000000)
+#define VPP_DAT_CONV_PARA1 ((0x1d95 << 2) + 0xff000000)
+//todo
+#define VPP_SYNC_SEL0 ((0x1d96 << 2) + 0xff000000)
+//`define VPP_VADJ1_BLACK_VAL 8'h97 //32'h0
+//`define VPP_VADJ2_BLACK_VAL 8'h98 //32'h0
+//Bit 29 blue_stretch_cb_inc
+//Bit 28 blue_stretch_cr_inc
+//Bit 27 the MSB of blue_stretch_error_crp_inv[11:0]
+//Bit 26 the MSB of blue_stretch_error_crn_inv[11:0]
+//Bit 25 the MSB of blue_stretch_error_cbp_inv[11:0]
+//Bit 24 the MSB of blue_stretch_error_cbn_inv[11:0]
+//Bit 23:16 blue_stretch_gain
+//Bit 15:8 blue_stretch_gain_cb4cr
+//Bit 7:0 blue_stretch_luma_high
+#define VPP_BLUE_STRETCH_1 ((0x1d9c << 2) + 0xff000000)
+//Bit 31:27 blue_stretch_error_crp
+//Bit 26:16 the 11 LSB of blue_stretch_error_crp_inv[11:0]
+//Bit 15:11 blue_stretch_error_crn
+//Bit 10:0 the 11 LSB of blue_stretch_error_crn_inv[11:0]
+#define VPP_BLUE_STRETCH_2 ((0x1d9d << 2) + 0xff000000)
+//Bit 31:27 blue_stretch_error_cbp
+//Bit 26:16 the 11 LSB of blue_stretch_error_cbp_inv[11:0]
+//Bit 15:11 blue_stretch_error_cbn
+//Bit 10:0 the 11 LSB of blue_stretch_error_cbn_inv[11:0]
+#define VPP_BLUE_STRETCH_3 ((0x1d9e << 2) + 0xff000000)
+#define VPP_CCORING_CTRL ((0x1da0 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_bypass_ccoring_ythd // unsigned , default = 0 bypass_ccoring_ythd
+//Bit 15:8 ccoring_th // unsigned , default = 0 Chroma coring threshold
+//Bit 7:0 reserved
+//Bit 3:0 ccoring_slope // unsigned , default = 0 Chroma coring slope
+#define VPP_VE_ENABLE_CTRL ((0x1da1 << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20 demo_ccoring_enable // unsigned , default = 0 demo chroma coring enable
+//Bit 19 demo_blackext_enable // unsigned , default = 0 demo black enxtension enable
+//Bit 18 demo_dnlp_enable // unsigned , default = 0 demo dynamic nonlinear luma processing enable
+//Bit 17 demo_hsvsharp_enable // unsigned , default = 0 demo hsvsharp enable
+//Bit 16 demo_bluestretch_enable // unsigned , default = 0 demo bluestretch enable
+//Bit 15:14 demo_disp_position // unsigned , default = 0 2'b00: demo adjust on top, 2'b01: demo adjust on bottom, 2'b10: demo adjust on left, 2'b11: demo adjust on right
+//Bit 13:7 reserved
+//Bit 6 sr4c0_path_sel // unsigned , default = 0
+//Bit 5 srscl_path_sel // unsigned , default = 0
+//Bit 4 ccoring_en // unsigned , default = 0 chroma coring enable
+//Bit 3 blackext_en // unsigned , default = 0 black enxtension enable
+//Bit 2 dnlp_en // unsigned , default = 0 dynamic nonlinear luma processing enable
+//Bit 1 hsvsharp_en // unsigned , default = 0 hsvsharp enable
+//Bit 0 blue_stretch_en // unsigned , default = 0 bluestretch enable
+#define VPP_VE_DEMO_LEFT_TOP_SCREEN_WIDTH ((0x1da2 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 ve_demo_left_top_screen_width // unsigned , default = 0 demo left or top screen width
+#define VPP_VE_DEMO_CENTER_BAR ((0x1da3 << 2) + 0xff000000)
+ //Bit 31 ve_demo_center_bar // unsigned , default = 0 center bar enable
+ //Bit 27:24 ve_demo_center_bar // unsigned , default = 0 center bar width (*2)
+ //Bit 23:16 ve_demo_center_bar // unsigned , default = 0 center bar Cr (*4)
+ //Bit 15:8 ve_demo_center_bar // unsigned , default = 0 center bar Cb (*4)
+ //Bit 7:0 ve_demo_center_bar // unsigned , default = 0 center bar y (*4)
+#define VPP_VE_H_V_SIZE ((0x1da4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 ve_line_length // unsigned , default = 780 ve_line_length
+//Bit 15:13 reserved
+//Bit 12:0 ve_pic_height // unsigned , default = 438 ve_pic_height
+#define VPP_OUT_H_V_SIZE ((0x1da5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 vppout_line_length / unsigned , default = 780 vppout_line_length
+//Bit 15:13 reserved
+//Bit 12:0 vppout_pic_height // unsigned , default = 438 vppout_pic_height
+#define VPP_IN_H_V_SIZE ((0x1da6 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 vppin_line_length / unsigned , default = 780 vppout_line_length
+//Bit 15:13 reserved
+//Bit 12:0 vppin_pic_height // unsigned , default = 438 vppout_pic_height
+#define VPP_VDO_MEAS_CTRL ((0x1da8 << 2) + 0xff000000)
+//Bit 31:11 reserved
+//Bit 10:0 vdo_meas_ctrl // unsigned , default = 0 vdo_meas_ctrl
+//Read only
+//19:16 ind_meas_count_n, every number of sync_span vsyncs, this counter add 1
+//15:0, high bit portion of counter
+#define VPP_VDO_MEAS_VS_COUNT_HI ((0x1da9 << 2) + 0xff000000)
+//Read only
+//31:0, low bit portion of counter
+#define VPP_VDO_MEAS_VS_COUNT_LO ((0x1daa << 2) + 0xff000000)
+//bit 11:9 vd2_sel, 001: select vd1_din, 010: select vd2_din, 011: select d2d3_l_din, 100: d2d3_r_din, otherwise no selection
+//bit 8:6 vd1_l_sel, 001: select vd1_din, 010: select vd2_din, 011: select d2d3_l_din, 100: d2d3_r_din, otherwise no selection
+//bit 5:3 vd1_r_sel, 001: select vd1_din, 010: select vd2_din, 011: select d2d3_l_din, 100: d2d3_r_din, otherwise no selection
+//note: the source vd1_l_sel selected cannot be used as the source of vd1_r_sel or vd2_sel
+// vd1_r_sel is useful only vd1_interleave_mode is not 00. And the source vd1_r_sel used can not used for the vd2_sel any more.
+//bit 2:0 vd1_interleave_mode, 000: no interleave, 001: pixel interleaving, 010: line interleaving, 011: 2 pixel interleaving,
+// 100: 2 line interleaving
+#define VPP_INPUT_CTRL ((0x1dab << 2) + 0xff000000)
+//bit 25:24 cti_bpf_sel
+//bit 20:16 cti_blend_factor_gama
+//bit 12:8 cti_blend_factor_beta
+//bit 4:0 cti_blend_factor_alpha
+#define VPP_CTI_CTRL2 ((0x1dac << 2) + 0xff000000)
+// `define VPP_PEAKING_SAT_THD1 8'had
+// `define VPP_PEAKING_SAT_THD2 8'hae
+// `define VPP_PEAKING_SAT_THD3 8'haf
+// `define VPP_PEAKING_SAT_THD4 8'hb0
+// `define VPP_PEAKING_SAT_THD5 8'hb1
+// `define VPP_PEAKING_SAT_THD6 8'hb2
+// `define VPP_PEAKING_SAT_THD7 8'hb3
+// `define VPP_PEAKING_SAT_THD8 8'hb4
+// `define VPP_PEAKING_SAT_THD9 8'hb5
+// `define VPP_PEAKING_GAIN_ADD1 8'hb6
+// `define VPP_PEAKING_GAIN_ADD2 8'hb7
+#define VPP_WRBAK_CTRL_SEC ((0x1dad << 2) + 0xff000000)
+#define VD1_BLEND_SRC_CTRL_SEC ((0x1dae << 2) + 0xff000000)
+#define VD2_BLEND_SRC_CTRL_SEC ((0x1daf << 2) + 0xff000000)
+#define OSD1_BLEND_SRC_CTRL_SEC ((0x1db0 << 2) + 0xff000000)
+#define OSD2_BLEND_SRC_CTRL_SEC ((0x1db1 << 2) + 0xff000000)
+//crc check , new add
+#define VPP_RO_CRCSUM ((0x1db2 << 2) + 0xff000000)
+#define VPP_CRC_CHK ((0x1db3 << 2) + 0xff000000)
+//bit 23:16 peaking_dnlp_gain, u5.3, DNLP effect
+//bit 15:8 peaking_factor
+//bit 5 peaking_dnlp_demo_en
+//bit 4 peaking_dnlp_en
+//bit 3:0 peaking_filter_sel
+#define VPP_PEAKING_DNLP ((0x1db8 << 2) + 0xff000000)
+//bit 24 sharp_demo_win_en
+//bit 23:12 sharp_demo_win_vend
+//bit 11:0 sharp_demo_win_vstart
+#define VPP_SHARP_DEMO_WIN_CTRL1 ((0x1db9 << 2) + 0xff000000)
+//bit 23:12 sharp_demo_win_hend
+//bit 11:0 sharp_demo_win_hstart
+#define VPP_SHARP_DEMO_WIN_CTRL2 ((0x1dba << 2) + 0xff000000)
+//Bit 31:24 front_hlti_neg_gain
+//Bit 23:16 front_hlti_pos_gain
+//Bit 15:8 front_hlti_threshold
+//Bit 7:0 front_hlti_blend_factor
+#define VPP_FRONT_HLTI_CTRL ((0x1dbb << 2) + 0xff000000)
+//Bit 31 front_enable, enable the front LTI&CTI before scaler
+//Bit 26:24 front_cti_step2
+//Bit 23:21 front_cti_step
+//Bit 20:16 front_cti_blend_factor
+//Bit 15 front_cti_median_mode
+//Bit 14:8 front_cti_threshold
+//Bit 7:0 front_cti_gain
+#define VPP_FRONT_CTI_CTRL ((0x1dbc << 2) + 0xff000000)
+//bit 29:28 front_hlti_step
+//bit 25:24 front_cti_bpf_sel
+//bit 20:16 front_cti_blend_factor_gama
+//bit 12:8 front_cti_blend_factor_beta
+//bit 4:0 front_cti_blend_factor_alpha
+#define VPP_FRONT_CTI_CTRL2 ((0x1dbd << 2) + 0xff000000)
+//Bit 12:0 line number use to generate interrupt when line == this number
+#define VPP_INT_LINE_NUM ((0x1dce << 2) + 0xff000000)
+#define VPP_XVYCC_MISC ((0x1dcf << 2) + 0xff000000)
+// new add lti/cti in 120924
+//Bit 3: 0 //default== 0 reg_hlti_dn_flt_coe[0]
+//Bit 7: 4 //default== 0 reg_hlti_dn_flt_coe[1]
+//Bit 11: 8 //default== 0 reg_hlti_dn_flt_coe[2]
+//Bit 15:12 //default== 2 reg_hlti_dn_flt_coe[3]
+//Bit 19:16 //default== 4 reg_hlti_dn_flt_coe[4]
+//Bit 22:20 //default== 3 reg_hlti_dn_flt_nrm u3: 3~7
+#define VPP_HLTI_DN_FLT ((0x1dd0 << 2) + 0xff000000)
+//Bit 7: 0 //default== 8 reg_hlti_bst_gain u8, norm 16 as "1"
+//Bit 15: 8 //default== 20 reg_hlti_bst_core u8, norm 32 as "1"
+//Bit 23:16 //default== 32 reg_hlti_oob_gain u8, norm 32 as "1"
+//Bit 28:24 //default== 0 reg_hlti_oob_core u5
+#define VPP_HLTI_GAIN ((0x1dd1 << 2) + 0xff000000)
+//Bit 7: 0 //default== 2 reg_hlti_clp_ofst u8,
+//Bit 8 //default== 0 reg_hlti_clp_mode u1,
+//Bit 11: 9 //default== 1 reg_hlti_clp_wind u3,
+//Bit 14:12 //default== 1 reg_hlti_bst_fltr u3,
+//Bit 15 //default== 1 reg_hlti_enable u1,
+#define VPP_HLTI_PARA ((0x1dd2 << 2) + 0xff000000)
+//Bit 3: 0 //default== 0 reg_hcti_dn_flt_coe[0]
+//Bit 7: 4 //default== 0 reg_hcti_dn_flt_coe[1]
+//Bit 11: 8 //default== 1 reg_hcti_dn_flt_coe[2]
+//Bit 15:12 //default== 2 reg_hcti_dn_flt_coe[3]
+//Bit 19:16 //default== 2 reg_hcti_dn_flt_coe[4]
+//Bit 22:20 //default== 3 reg_hcti_dn_flt_nrm u3: 3~7
+#define VPP_HCTI_DN_FLT ((0x1dd3 << 2) + 0xff000000)
+//Bit 7: 0 //default== 48 reg_hcti_bst_gain u8, norm 16 as "1"
+//Bit15: 8 //default== 17 reg_hcti_bst_core u8, norm 32 as "1"
+//Bit23:16 //default== 16 reg_hcti_oob_gain u8, norm 32 as "1"
+//Bit28:24 //default== 0 reg_hcti_oob_core u5
+#define VPP_HCTI_GAIN ((0x1dd4 << 2) + 0xff000000)
+//Bit 7: 0 //default== 0 reg_hcti_clp_ofst u8,
+//Bit 8 //default== 1 reg_hcti_clp_mode u1,
+//Bit 11: 9 //default== 3 reg_hcti_clp_wind u3,
+//Bit 14:12 //default== 6 reg_hcti_bst_fltr u3,
+//Bit 15 //default== 1 reg_hcti_enable u1,
+#define VPP_HCTI_PARA ((0x1dd5 << 2) + 0xff000000)
+//Bit 7: 0 //default== 48 reg_vcti_bst_gain u8, normalize 16 as "1"
+//Bit 15: 8 //default== 10 reg_vcti_bst_core u8
+//Bit 19:16 //default== 10 reg_vcti_clp_ofst u4
+//Bit 20 //default== 1 reg_vcti_clp_wind u1, 0: wind 3, 1: wind5
+#define VPP_VCTI_PARA ((0x1dd6 << 2) + 0xff000000)
+//`define VPP_MATRIX_PROBE_COLOR1 8'hd7 //defined before
+//Bit 31 //default== 0, urgent fifo hold enable
+//Bit 28:12 //default== 0, urgent fifo hold line threshold
+//Bit 15 //default== 0, urgent_ctrl_en
+//Bit 14 //default== 0, urgent_wr, if true for write buffer
+//Bit 13 //default== 0, out_inv_en
+//Bit 12 //default == 0, urgent_ini_value
+//Bit 11:6 //default == 0, up_th up threshold
+//Bit 5:0 //default == 0, dn_th dn threshold
+#define VPP_OFIFO_URG_CTRL ((0x1dd8 << 2) + 0xff000000)
+#define VPP_CLIP_MISC0 ((0x1dd9 << 2) + 0xff000000)
+//Bit 29:20 // default == 1023, final clip r channel top
+//Bit 19:10 // default == 1023, final clip g channel top
+//Bit 9: 0 // default == 1023, final clip b channel top
+#define VPP_CLIP_MISC1 ((0x1dda << 2) + 0xff000000)
+//Bit 29:20 // default == 0, final clip r channel bottom
+//Bit 19:10 // default == 0, final clip g channel bottom
+//Bit 9: 0 // default == 0, final clip b channel bottom
+#define VPP_MATRIX_COEF13_14 ((0x1ddb << 2) + 0xff000000)
+//Bit 28:16 // default == 0, matrix coef13
+//Bit 12:0 // default == 0, matrix coef14
+#define VPP_MATRIX_COEF23_24 ((0x1ddc << 2) + 0xff000000)
+//Bit 28:16 // default == 0, matrix coef23
+//Bit 12:0 // default == 0, matrix coef24
+#define VPP_MATRIX_COEF15_25 ((0x1ddd << 2) + 0xff000000)
+//Bit 28:16 // default == 0, matrix coef15
+//Bit 12:0 // default == 0, matrix coef25
+#define VPP_MATRIX_CLIP ((0x1dde << 2) + 0xff000000)
+//Bit 7:5 // default == 0, mat rs
+//Bit 4:3 // default == 0, mat clmod
+//Bit 2:0 // default == 0, mat clip enable
+#define VPP_XVYCC_MISC0 ((0x1ddf << 2) + 0xff000000)
+//Bit 29:20 // default == 1023, xvycc clip r channel top
+//Bit 19:10 // default == 1023, xvycc clip g channel top
+//Bit 9: 0 // default == 1023, xvycc clip b channel top
+#define VPP_XVYCC_MISC1 ((0x1de0 << 2) + 0xff000000)
+//Bit 29:20 // default == 0, xvycc clip r channel bottom
+//Bit 19:10 // default == 0, xvycc clip g channel bottom
+//Bit 9: 0 // default == 0, xvycc clip b channel bottom
+#define VPP_VD1_CLIP_MISC0 ((0x1de1 << 2) + 0xff000000)
+//Bit 29:20 // default == 1023, vd1 clip r channel top
+//Bit 19:10 // default == 1023, vd1 clip g channel top
+//Bit 9: 0 // default == 1023, vd1 clip b channel top
+#define VPP_VD1_CLIP_MISC1 ((0x1de2 << 2) + 0xff000000)
+//Bit 29:20 // default == 0, vd1 clip r channel bottom
+//Bit 19:10 // default == 0, vd1 clip g channel bottom
+//Bit 9: 0 // default == 0, vd1 clip b channel bottom
+#define VPP_VD2_CLIP_MISC0 ((0x1de3 << 2) + 0xff000000)
+//Bit 29:20 // default == 1023, vd2 clip r channel top
+//Bit 19:10 // default == 1023, vd2 clip g channel top
+//Bit 9: 0 // default == 1023, vd2 clip b channel top
+#define VPP_VD2_CLIP_MISC1 ((0x1de4 << 2) + 0xff000000)
+//Bit 29:20 // default == 0, vd2 clip r channel bottom
+//Bit 19:10 // default == 0, vd2 clip g channel bottom
+//Bit 9: 0 // default == 0, vd2 clip b channel bottom
+#define VPP_VD3_CLIP_MISC0 ((0x1de5 << 2) + 0xff000000)
+//Bit 29:20 // default == 1023, vd2 clip r channel top
+//Bit 19:10 // default == 1023, vd2 clip g channel top
+//Bit 9: 0 // default == 1023, vd2 clip b channel top
+#define VPP_VD3_CLIP_MISC1 ((0x1de6 << 2) + 0xff000000)
+//Bit 29:20 // default == 0, vd2 clip r channel bottom
+//Bit 19:10 // default == 0, vd2 clip g channel bottom
+//Bit 9: 0 // default == 0, vd2 clip b channel bottom
+#define VPP_BLEND_VD3_H_START_END ((0x1deb << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VPP_BLEND_VD3_V_START_END ((0x1dec << 2) + 0xff000000)
+//Bit 28:16 start
+//Bit 12:0 end
+#define VD3_BLEND_SRC_CTRL ((0x1def << 2) + 0xff000000)
+#define VPP_VD2_HDR_IN_SIZE ((0x1df0 << 2) + 0xff000000)
+//Bit 31:16 // default == 0
+//Bit 15:0 // default == 0
+#define VPP_OSD1_IN_SIZE ((0x1df1 << 2) + 0xff000000)
+//Bit 31:16 // default == 0
+//Bit 15:0 // default == 0
+#define VPP_GCLK_CTRL2 ((0x1df2 << 2) + 0xff000000)
+//`define VPP_BLEND_SRC_SEL 8'hf3
+//`define VD2_PPS_DUMMY_DATA 8'hf4
+#define VPP_OSD1_BLD_H_SCOPE ((0x1df5 << 2) + 0xff000000)
+#define VPP_OSD1_BLD_V_SCOPE ((0x1df6 << 2) + 0xff000000)
+#define VPP_OSD2_BLD_H_SCOPE ((0x1df7 << 2) + 0xff000000)
+#define VPP_OSD2_BLD_V_SCOPE ((0x1df8 << 2) + 0xff000000)
+#define VPP_WRBAK_CTRL ((0x1df9 << 2) + 0xff000000)
+#define VPP_SLEEP_CTRL ((0x1dfa << 2) + 0xff000000)
+#define VD1_BLEND_SRC_CTRL ((0x1dfb << 2) + 0xff000000)
+#define VD2_BLEND_SRC_CTRL ((0x1dfc << 2) + 0xff000000)
+#define OSD1_BLEND_SRC_CTRL ((0x1dfd << 2) + 0xff000000)
+#define OSD2_BLEND_SRC_CTRL ((0x1dfe << 2) + 0xff000000)
+//`define VPP_OSD_SCALE_CTRL 8'hff
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: DISP_IF1_VCBUS_BASE = 0x1e
+// -----------------------------------------------
+//===========================================================================
+//`include "disp_if_regs.h"
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: DISP_IF2_VCBUS_BASE = 0x1f
+// -----------------------------------------------
+//===========================================================================
+//`include "disp_if_regs.h"
+//===========================================================================
+//===========================================================================
+//
+// Reading file: vregs_clk1.h
+//
+//===========================================================================
+// Video Interface Registers 0xa00 - 0xaff
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VIUB_VCBUS_BASE = 0x20
+// -----------------------------------------------
+#define VIUB_ADDR_START ((0x2000 << 2) + 0xff000000)
+#define VIUB_ADDR_END ((0x20ff << 2) + 0xff000000)
+//`define TRACE_REG 8'ff
+//------------------------------------------------------------------------------
+// VIU top-level registers
+//------------------------------------------------------------------------------
+// Bit 0 RW, osd1_reset
+// Bit 1 RW, osd2_reset
+// Bit 2 RW, vd1_reset
+// Bit 3 RW, vd1_fmt_reset
+// Bit 4 RW, vd2_reset
+// Bit 5 RW, vd2_fmt_reset
+// Bit 6 RW, di_dsr1to2_reset
+// Bit 7 RW, vpp_reset
+// Bit 8 RW, di_if1_reset
+// Bit 9 RW, di_if1_fmt_reset
+// Bit 10 RW, di_inp_reset
+// Bit 11 RW, di_inp_fmt_reset
+// Bit 12 RW, di_mem_reset
+// Bit 13 RW, di_mem_fmt_reset
+// Bit 14 RW, di_nr_wr_mif_reset
+// Bit 15 RW, dein_wr_mif_reset
+// Bit 16 RW, di_chan2_mif_reset
+// Bit 17 RW, di_mtn_wr_mif_reset
+// Bit 18 RW, di_mtn_rd_mif_reset
+// Bit 19 RW, di_mad_reset
+// Bit 20 RW, vdin0_reset
+// Bit 21 RW, vdin1_reset
+// Bit 22 RW, nrin_mux_reset
+// Bit 23 RW, vdin0_wr_reset
+// Bit 24 RW, vdin1_wr_reset
+// Bit 25 RW, reserved
+// Bit 26 RW, d2d3_reset
+// Bit 27 RW, di_cont_wr_mif_reset
+// Bit 28 RW, di_cont_rd_mif_reset
+#define VIUB_SW_RESET ((0x2001 << 2) + 0xff000000)
+#define VIUB_SW_RESET0 ((0x2002 << 2) + 0xff000000)
+// Bit 0 RW, software reset for mcvecrd_mif
+// Bit 1 RW, software reset for mcinfowr_mif
+// Bit 2 RW, software reset for mcinford_mif
+#define DI_AFBCE_CTRL ((0x2003 << 2) + 0xff000000)
+#define VIUB_SECURE_ST_RO ((0x2004 << 2) + 0xff000000)
+//bit 8 if true, vsync interrup is generate only field == 0
+//bit 7:0 fix_disable
+#define VIUB_MISC_CTRL0 ((0x2006 << 2) + 0xff000000)
+#define VIUB_GCLK_CTRL0 ((0x2007 << 2) + 0xff000000)
+//// gclk_ctrl0_gl[ 0] : def=1 di_top_wrap clk enable
+////
+//// gclk_ctrl0_gl[ 8] : def=0 mad pre clock enable, from mad clock
+//// gclk_ctrl0_gl[ 9] : def=0 mad post clock enable, from mad clock
+//// gclk_ctrl0_gl[10] : def=0 div clock enable, di slow clock including di&mcdi
+//// gclk_ctrl0_gl[11] : def=0 mcdi clock enable, from div clock
+//// gclk_ctrl0_gl[12] : def=0 di post clock enable, from div clock
+//// gclk_ctrl0_gl[13] : def=0 reserved
+//// gclk_ctrl0_gl[14] : def=1 di_no_clk_gate, for old di
+//// gclk_ctrl0_gl[15] : def=0 di_gate_all, for old di
+#define VIUB_GCLK_CTRL1 ((0x2008 << 2) + 0xff000000)
+//// gclk_ctrl1_gl[ 1: 0] : def=2'b00 mif-sub-arb clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[ 3: 2] : def=2'b00 if1 rdmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[ 5: 4] : def=2'b00 if2 rdmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[ 7: 6] : def=2'b00 de wrmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[ 9: 8] : def=2'b00 mtnrd post mif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[11:10] : def=2'b00 mcdi post mif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[17:16] : def=2'b00 inp rdmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[19:18] : def=2'b00 mem rdmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[21:20] : def=2'b00 chan rdmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[23:22] : def=2'b00 nr wrmif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[25:24] : def=2'b00 mtn mif clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl1_gl[27:26] : def=2'b00 mcdi pre mif clock gate ctrl [1]: clock valid, [0]: clock close
+////
+#define VIUB_GCLK_CTRL2 ((0x2009 << 2) + 0xff000000)
+//// gclk_ctrl_pre[ 1: 0] : def=2'b00 nr clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_pre[ 3: 2] : def=2'b00 pd clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_pre[ 5: 4] : def=2'b00 mtn det clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_pre[ 7: 6] : def=2'b00 debanding clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_pre[ 9: 8] : def=2'b00 dnr clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_pre[11:10] : def=2'b00 nr&dnr blend clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_pre[13:12] : def=2'b00 mcdi clock gate ctrl [1]: clock valid, [0]: clock close
+#define VIUB_GCLK_CTRL3 ((0x200a << 2) + 0xff000000)
+//// gclk_ctrl_post[ 1: 0] : def=2'b00 di blend clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_post[ 3: 2] : def=2'b00 ei clock gate ctrl [1]: clock valid, [0]: clock close
+//// gclk_ctrl_post[ 5: 4] : def=2'b00 ei_0 clock gate ctrl [1]: clock valid, [0]: clock close
+#define DI_DBG_CTRL ((0x200b << 2) + 0xff000000)
+#define DI_DBG_CTRL1 ((0x200c << 2) + 0xff000000)
+#define DI_DBG_SRDY_INF ((0x200d << 2) + 0xff000000)
+#define DI_DBG_RRDY_INF ((0x200e << 2) + 0xff000000)
+#define VIUB_SECURE_REG ((0x200f << 2) + 0xff000000)
+#define DI_PRE_SEC_IN ((0x2010 << 2) + 0xff000000)
+#define DI_POST_SEC_IN ((0x2011 << 2) + 0xff000000)
+//`define DI_IF2_GEN_REG 8'h10
+//`define DI_IF2_CANVAS0 8'h11
+//`define DI_IF2_LUMA_X0 8'h12
+//`define DI_IF2_LUMA_Y0 8'h13
+//`define DI_IF2_CHROMA_X0 8'h14
+//`define DI_IF2_CHROMA_Y0 8'h15
+//`define DI_IF2_RPT_LOOP 8'h16
+//`define DI_IF2_LUMA0_RPT_PAT 8'h17
+//`define DI_IF2_CHROMA0_RPT_PAT 8'h18
+//`define DI_IF2_DUMMY_PIXEL 8'h19
+//`define DI_IF2_LUMA_FIFO_SIZE 8'h1a
+//`define DI_IF2_RANGE_MAP_Y 8'h1b
+//`define DI_IF2_RANGE_MAP_CB 8'h1c
+//`define DI_IF2_RANGE_MAP_CR 8'h1d
+//`define DI_IF2_GEN_REG2 8'h1e
+//`define DI_IF2_FMT_CTRL 8'h1f
+//`define DI_IF2_FMT_W 8'h20
+//
+//`define DI_IF2_URGENT_CTRL 8'h21
+//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path
+//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path
+//`define DI_IF2_GEN_REG3 8'h22
+//bit 31:1, reversed
+//bit 0, cntl_64bit_rev
+//==================================
+#define DI_EI_DRT_CTRL ((0x2028 << 2) + 0xff000000)
+//Bit 31, reg_rectg_en ;u1
+//Bit 30, reg_recbld_en ;u1
+//Bit 29:28, reg_rectg_ws ;u2
+//Bit 27, reserved
+//Bit 26:24, reg_abq_margin ;u3
+//Bit 23, reserved
+//Bit 22:20, reg_trend_mg ;u3
+//Bit 19:16, reg_int_d16xc1 ;u4
+//Bit 15:14, reserved
+//Bit 13: 8, reg_int_chlmt1 ;u6
+//Bit 7, reserved
+//Bit 6: 4, reg_nscheck_thrd ;u3
+//Bit 3, reserved
+//Bit 2: 0, reg_horsl_ws ;u3
+#define DI_EI_DRT_PIXTH ((0x2029 << 2) + 0xff000000)
+//Bit 31:24, reg_min_pix ;u8
+//Bit 23:16, reg_max_pix ;u8
+//Bit 15: 8, reg_dmaxmin_thrdma ;u8
+//Bit 7: 0, reg_dmaxmin_thrdmi ;u8
+#define DI_EI_DRT_CORRPIXTH ((0x202a << 2) + 0xff000000)
+//Bit 31:24, reg_newcorrpix_maxthrd ;u8
+//Bit 23:16, reg_corrpix_diffthrd ;u8
+//Bit 15: 8, reg_corrpix_minthrd ;u8
+//Bit 7: 0, reg_corrpix_maxthrd ;u8
+#define DI_EI_DRT_RECTG_WAVE ((0x202b << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_max_pixwave ;u5
+//Bit 23:21, reserved
+//Bit 20:16, reg_pix_wave ;u5
+//Bit 15:14, reserved
+//Bit 13: 8, reg_maxdrt_thrd ;u6
+//Bit 7: 0, reg_wave_thrd ;u8
+#define DI_EI_DRT_PIX_DIFFTH ((0x202c << 2) + 0xff000000)
+//Bit 31:24, reg_newraw_thrd ;u8
+//Bit 23:16, reg_tb_max_thrd ;u8
+//Bit 15: 8, reg_diffpix_thrd ;u8
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_bilt_trendnumt ;u8
+#define DI_EI_DRT_UNBITREND_TH ((0x202d << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_trend_numb ;u5
+//Bit 23:21, reserved
+//Bit 20:16, reg_bilt_trendnum ;u5
+//Bit 15:13, reserved
+//Bit 12: 8, reg_unil_trendnumt ;u5
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_trend_num ;u5
+//`define DI_IF0_GEN_REG 8'h30
+//`define DI_IF0_CANVAS0 8'h31
+//`define DI_IF0_LUMA_X0 8'h32
+//`define DI_IF0_LUMA_Y0 8'h33
+//`define DI_IF0_CHROMA_X0 8'h34
+//`define DI_IF0_CHROMA_Y0 8'h35
+//`define DI_IF0_RPT_LOOP 8'h36
+//`define DI_IF0_LUMA0_RPT_PAT 8'h37
+//`define DI_IF0_CHROMA0_RPT_PAT 8'h38
+//`define DI_IF0_DUMMY_PIXEL 8'h39
+//`define DI_IF0_LUMA_FIFO_SIZE 8'h3a
+//`define DI_IF0_RANGE_MAP_Y 8'h3b
+//`define DI_IF0_RANGE_MAP_CB 8'h3c
+//`define DI_IF0_RANGE_MAP_CR 8'h3d
+//`define DI_IF0_GEN_REG2 8'h3e
+//`define DI_IF0_FMT_CTRL 8'h3f
+//`define DI_IF0_FMT_W 8'h40
+//
+//`define DI_IF0_URGENT_CTRL 8'h41
+//bit15, auto enable; bit14, canvas write mode ;7:4, high threshold ;3:0 , low threshold for di inp chroma path
+//bit31, auto enable; bit30, canvas write mode ;23:20, high threshold ;19:16 , low threshold for di inp luma path
+//`define DI_IF0_GEN_REG3 8'h42
+//bit 31:1, reversed
+//bit 0, cntl_64bit_rev
+// di arbtration :
+// the segment is 8'h50-8'h5f
+//
+// Reading file: di_arb_axi_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+//// reg
+////===============================////
+#define DI_RDARB_MODE_L1C1 ((0x2050 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, rdarb_sel uns, default = 0 ,
+// rdarb_sel[0]==0 slave dc0 connect master port0 rdarb_sel[0]==1 slave dc0 connect master port1
+// rdarb_sel[1]==0 slave dc1 connect master port0 rdarb_sel[1]==1 slave dc1 connect master port1
+// rdarb_sel[2]==0 slave dc2 connect master port0 rdarb_sel[2]==1 slave dc2 connect master port1
+// rdarb_sel[3]==0 slave dc3 connect master port0 rdarb_sel[3]==1 slave dc3 connect master port1
+// rdarb_sel[4]==0 slave dc4 connect master port0 rdarb_sel[4]==1 slave dc4 connect master port1
+// rdarb_sel[5]==0 slave dc5 connect master port0 rdarb_sel[5]==1 slave dc5 connect master port1
+//Bit 15:10, reserved
+//Bit 9:8, rdarb_arb_mode uns, default = 0 ,
+// rdarb_arb_mode[0] master port0 arb way,
+// rdarb_arb_mode[1] master port1 arb way,
+//Bit 7:4, reserved
+//Bit 3:0, rdarb_gate_clk_ctrl uns, default = 0 ,
+// rdarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// rdarb_gate_clk_ctrl[3:2] master port1 clk gate control
+#define DI_RDARB_REQEN_SLV_L1C1 ((0x2051 << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, rdarb_dc_req_en unsigned , default = 12'hfff
+// rdarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// rdarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// rdarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// rdarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// rdarb_dc_req_en[4]: the slv4 req to mst port0 enable,
+// rdarb_dc_req_en[5]: the slv5 req to mst port0 enable,
+// rdarb_dc_req_en[6]: the slv0 req to mst port1 enable,
+// rdarb_dc_req_en[7]: the slv1 req to mst port1 enable,
+// rdarb_dc_req_en[8]: the slv2 req to mst port1 enable,
+// rdarb_dc_req_en[9]: the slv3 req to mst port1 enable,
+// rdarb_dc_req_en[10]: the slv4 req to mst port1 enable,
+// rdarb_dc_req_en[11]: the slv5 req to mst port1 enable,
+#define DI_RDARB_WEIGH0_SLV_L1C1 ((0x2052 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// rddc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// rddc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// rddc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+// rddc_weigh_sxn[4*6+:6]: the slv4 req weigh number
+#define DI_RDARB_WEIGH1_SLV_L1C1 ((0x2053 << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[5*6+:6]: the slv5 req weigh number
+#define DI_WRARB_MODE_L1C1 ((0x2054 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, wrarb_sel uns, default = 0 ,
+// wrarb_sel[0]==0 slave dc0 connect master port0 wrarb_sel[0]==1 slave dc0 connect master port1
+// wrarb_sel[1]==0 slave dc1 connect master port0 wrarb_sel[1]==1 slave dc1 connect master port1
+// wrarb_sel[2]==0 slave dc2 connect master port0 wrarb_sel[2]==1 slave dc2 connect master port1
+// wrarb_sel[3]==0 slave dc3 connect master port0 wrarb_sel[3]==1 slave dc3 connect master port1
+// wrarb_sel[4]==0 slave dc4 connect master port0 wrarb_sel[4]==1 slave dc4 connect master port1
+// wrarb_sel[5]==0 slave dc5 connect master port0 wrarb_sel[5]==1 slave dc5 connect master port1
+//Bit 15:10, reserved
+//Bit 9:8, wrarb_arb_mode uns, default = 0 ,
+// wrarb_arb_mode[0] master port0 arb way,
+// wrarb_arb_mode[1] master port1 arb way,
+//Bit 7:4, reserved
+//Bit 3:0, wrarb_gate_clk_ctrl uns, default = 0 ,
+// wrarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// wrarb_gate_clk_ctrl[3:2] master port1 clk gate control
+#define DI_WRARB_REQEN_SLV_L1C1 ((0x2055 << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, wrarb_dc_req_en unsigned , default = 0
+// wrarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// wrarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// wrarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// wrarb_dc_req_en[4]: the slv4 req to mst port0 enable,
+// wrarb_dc_req_en[5]: the slv5 req to mst port0 enable,
+// wrarb_dc_req_en[0]: the slv0 req to mst port1 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port1 enable,
+// wrarb_dc_req_en[2]: the slv2 req to mst port1 enable,
+// wrarb_dc_req_en[3]: the slv3 req to mst port1 enable,
+// wrarb_dc_req_en[4]: the slv4 req to mst port1 enable,
+// wrarb_dc_req_en[5]: the slv5 req to mst port1 enable,
+#define DI_WRARB_WEIGH0_SLV_L1C1 ((0x2056 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// wrdc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// wrdc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+// wrdc_weigh_sxn[4*6+:6]: the slv4 req weigh number
+#define DI_WRARB_WEIGH1_SLV_L1C1 ((0x2057 << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[5*6+:6]: the slv5 req weigh number
+#define DI_RDWR_ARB_STATUS_L1C1 ((0x2058 << 2) + 0xff000000)
+//Bit 31:4, reserved
+//Bit 3:2, wrarb_arb_busy unsigned , default = 0
+//Bit 1:0, rdarb_arb_busy unsigned , default = 0
+#define DI_ARB_DBG_CTRL_L1C1 ((0x2059 << 2) + 0xff000000)
+#define DI_ARB_DBG_STAT_L1C1 ((0x205a << 2) + 0xff000000)
+#define DI_RDARB_UGT_L1C1 ((0x205b << 2) + 0xff000000)
+#define DI_RDARB_LIMT0_L1C1 ((0x205c << 2) + 0xff000000)
+#define DI_WRARB_UGT_L1C1 ((0x205d << 2) + 0xff000000)
+#define DI_ARB_AXIWR_PROT ((0x205e << 2) + 0xff000000)
+#define DI_ARB_AXIRD0_PROT ((0x205f << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: di_arb_axi_regs.h
+//
+// di afbc_enc
+// the segment is 8'h60-8'h8f
+//
+// Reading file: di_afbc_enc0_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DI_AFBCE_ENABLE ((0x2060 << 2) + 0xff000000)
+//Bit 31:20, gclk_ctrl unsigned , default = 0,
+//Bit 19:16, di_afbce_sync_sel unsigned , default = 0,
+//Bit 15:14, reserved
+//Bit 13, enc_rst_mode unsigned , default = 0,
+//Bit 12, enc_en_mode unsigned , default = 0,
+//Bit 11:9, reserved
+//Bit 8, enc_enable unsigned , default = 0,
+//Bit 7:1, reserved
+//Bit 0, reserved enc_frm_start pulse use this bit don't use
+#define DI_AFBCE_MODE ((0x2061 << 2) + 0xff000000)
+//Bit 31:29, soft_rst unsigned, default = 0 ,the use as go_field
+//Bit 28, reserved
+//Bit 27:26, rev_mode unsigned, default = 0 , reverse mode
+//Bit 25:24, mif_urgent unsigned, default = 3 , info mif and data mif urgent
+//Bit 23, reserved
+//Bit 22:16, hold_line_num unsigned, default = 4, 0: burst1 1:burst2 2:burst4
+//Bit 15:14, burst_mode unsigned, default = 1, 0: burst1 1:burst2 2:burst4
+//Bit 13:1, reserved
+//Bit 0, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb
+#define DI_AFBCE_SIZE_IN ((0x2062 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hsize_in unsigned, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_in unsigned, default = 1080 , pic vert size in unit: pixel
+#define DI_AFBCE_BLK_SIZE_IN ((0x2063 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hblk_size unsigned, default = 60 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vblk_size unsigned, default = 270, pic vert size in unit: pixel
+#define DI_AFBCE_HEAD_BADDR ((0x2064 << 2) + 0xff000000)
+//Bit 31:0, head_baddr unsigned, default = 32'h00;
+#define DI_AFBCE_MIF_SIZE ((0x2065 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:28, ddr_blk_size unsigned, default = 1;
+//Bit 27, reserved
+//Bit 26:24, cmd_blk_size unsigned, default = 3;
+//Bit 23:21, reserved
+//Bit 20:16, uncmp_size unsigned, default = 20;
+//Bit 15:0, mmu_page_size unsigned, default = 4096;
+#define DI_AFBCE_PIXEL_IN_HOR_SCOPE ((0x2066 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, enc_win_end_h unsigned, default = 1919 ; //
+//Bit 15:13, reserved
+//Bit 12:0, enc_win_bgn_h unsigned, default = 0 ; //
+#define DI_AFBCE_PIXEL_IN_VER_SCOPE ((0x2067 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, enc_win_end_v unsigned, default = 1079 ; //
+//Bit 15:13, reserved
+//Bit 12:0, enc_win_bgn_v unsigned, default = 0 ; //
+#define DI_AFBCE_CONV_CTRL ((0x2068 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, fmt_ybuf_depth unsigned, default = 2048
+//Bit 15:12, reserved
+//Bit 11: 0, lbuf_depth unsigned, default = 256, unit=16 pixel need to set = 2^n
+#define DI_AFBCE_MIF_HOR_SCOPE ((0x2069 << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, blk_end_h unsigned, default = 0 ; //
+//Bit 15:10, reserved
+//Bit 9:0, blk_bgn_h unsigned, default = 59 ; //
+#define DI_AFBCE_MIF_VER_SCOPE ((0x206a << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, blk_end_v unsigned, default = 0 ; //
+//Bit 15:12, reserved
+//Bit 11:0, blk_bgn_v unsigned, default = 269 ; //
+#define DI_AFBCE_STAT1 ((0x206b << 2) + 0xff000000)
+//Bit 31, ro_frm_end_pulse1 unsigned, RO,default = 0 ;frame end status
+//Bit 30:0, ro_dbg_top_info1 unsigned, RO,default = 0 ;
+#define DI_AFBCE_STAT2 ((0x206c << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30:0, ro_dbg_top_info2 unsigned, RO,default = 0 ;
+#define DI_AFBCE_FORMAT ((0x206d << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11:10 reserved
+//Bit 9: 8 reg_format_mode // unsigned , RW, default = 2 data format;0 : YUV444, 1:YUV422, 2:YUV420, 3:RGB
+//Bit 7: 4 reg_compbits_c // unsigned , RW, default = 10 chroma bitwidth
+//Bit 3: 0 reg_compbits_y // unsigned , RW, default = 10 luma bitwidth
+#define DI_AFBCE_MODE_EN ((0x206e << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 reserved
+//Bit 25 reg_adpt_interleave_ymode // unsigned , RW, default = 0 force 0 to disable it: no HW implementation
+//Bit 24 reg_adpt_interleave_cmode // unsigned , RW, default = 0 force 0 to disable it: not HW implementation
+//Bit 23 reg_adpt_yinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
+//Bit 22 reg_adpt_yinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
+//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
+//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
+//Bit 19 reserved
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 11 reserved
+//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
+//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
+//Bit 8 reg_uncompress_split_mode // unsigned , RW, default = 0 0: no split; 1: split
+//Bit 7: 6 reserved
+//Bit 5 reg_input_padding_uv128 // unsigned , RW, default = 0 input picture 32x4 block gap mode: 0: pad uv=0; 1: pad uv=128
+//Bit 4 reg_dwds_padding_uv128 // unsigned , RW, default = 0 downsampled image for double write 32x gap mode: 0: pad uv=0; 1: pad uv=128
+//Bit 3: 1 reg_force_order_mode_value // unsigned , RW, default = 0 force order mode 0~7
+//Bit 0 reg_force_order_mode_en // unsigned , RW, default = 0 force order mode enable: 0: no force; 1: forced to force_value
+#define DI_AFBCE_DWSCALAR ((0x206f << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7: 6 reg_dwscalar_w0 // unsigned , RW, default = 3 horizontal 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 5: 4 reg_dwscalar_w1 // unsigned , RW, default = 0 horizontal 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 3: 2 reg_dwscalar_h0 // unsigned , RW, default = 2 vertical 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 1: 0 reg_dwscalar_h1 // unsigned , RW, default = 3 vertical 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+#define DI_AFBCE_DEFCOLOR_1 ((0x2070 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_enc_defalutcolor_3 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr]
+//Bit 11: 0 reg_enc_defalutcolor_0 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr]
+#define DI_AFBCE_DEFCOLOR_2 ((0x2071 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_enc_defalutcolor_2 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr]
+//Bit 11: 0 reg_enc_defalutcolor_1 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr]
+#define DI_AFBCE_QUANT_ENABLE ((0x2072 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_quant_expand_en_1 // unsigned , RW, default = 0 enable for quantization value expansion
+//Bit 10 reg_quant_expand_en_0 // unsigned , RW, default = 0 enable for quantization value expansion
+//Bit 9: 8 reg_bcleav_ofst // signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1;
+//Bit 7: 5 reserved
+//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy
+//Bit 3: 1 reserved
+//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy
+#define DI_AFBCE_IQUANT_LUT_1 ((0x2073 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE_IQUANT_LUT_2 ((0x2074 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE_IQUANT_LUT_3 ((0x2075 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE_IQUANT_LUT_4 ((0x2076 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE_RQUANT_LUT_1 ((0x2077 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_rquant_yclut_0_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting)
+//Bit 27 reserved
+//Bit 26:24 reg_rquant_yclut_0_10 // unsigned , RW, default = 5
+//Bit 23 reserved
+//Bit 22:20 reg_rquant_yclut_0_9 // unsigned , RW, default = 4
+//Bit 19 reserved
+//Bit 18:16 reg_rquant_yclut_0_8 // unsigned , RW, default = 4
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_0_7 // unsigned , RW, default = 3
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_0_6 // unsigned , RW, default = 3
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_0_5 // unsigned , RW, default = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_0_4 // unsigned , RW, default = 2
+#define DI_AFBCE_RQUANT_LUT_2 ((0x2078 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_0_3 // unsigned , RW, default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_0_2 // unsigned , RW, default = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_0_1 // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_0_0 // unsigned , RW, default = 0
+#define DI_AFBCE_RQUANT_LUT_3 ((0x2079 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_rquant_yclut_1_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting)
+//Bit 27 reserved
+//Bit 26:24 reg_rquant_yclut_1_10 // unsigned , RW, default = 5
+//Bit 23 reserved
+//Bit 22:20 reg_rquant_yclut_1_9 // unsigned , RW, default = 4
+//Bit 19 reserved
+//Bit 18:16 reg_rquant_yclut_1_8 // unsigned , RW, default = 4
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_1_7 // unsigned , RW, default = 3
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_1_6 // unsigned , RW, default = 3
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_1_5 // unsigned , RW, default = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_1_4 // unsigned , RW, default = 2
+#define DI_AFBCE_RQUANT_LUT_4 ((0x207a << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_1_3 // unsigned , RW, default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_1_2 // unsigned , RW, default = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_1_1 // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_1_0 // unsigned , RW, default = 0
+#define DI_AFBCE_YUV_FORMAT_CONV_MODE ((0x207b << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7 reserved
+//Bit 6: 4 reg_444to422_mode // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_422to420_mode // unsigned , RW, default = 0
+#define DI_AFBCE_DUMMY_DATA ((0x207c << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29: 0 reg_dummy_data // unsigned , default = 0 ;
+#define DI_AFBCE_CLR_FLAG ((0x207d << 2) + 0xff000000)
+//Bit 31:0 reg_di_afbce_clr_flag // unsigned, default = 0 ;
+#define DI_AFBCE_STA_FLAGT ((0x207e << 2) + 0xff000000)
+//Bit 31:0 ro_di_afbce__sta_flag // unsigned, RO,default = 0 ;
+#define DI_AFBCE_MMU_NUM ((0x207f << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 0 ro_frm_mmu_num // unsigned, RO,default = 0 ;
+#define DI_AFBCE_MMU_RMIF_CTRL1 ((0x2080 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_sync_sel // unsigned , default = 0, axi canvas id sync with frm rst
+//Bit 23:16 reg_canvas_id // unsigned , default = 0, axi canvas id num
+//Bit 15 reserved
+//Bit 14:12 reg_cmd_intr_len // unsigned , default = 1, interrupt send cmd when how many series axi cmd,
+ // 0=12 1=16 2=24 3=32 4=40 5=48 6=56 7=64
+//Bit 11:10 reg_cmd_req_size // unsigned , default = 1, how many room fifo have, then axi send series req, 0=16 1=32 2=24 3=64
+//Bit 9:8 reg_burst_len // unsigned , default = 2, burst type: 0-single 1-bst2 2-bst4
+//Bit 7 reg_swap_64bit // unsigned , default = 0, 64bits of 128bit swap enable
+//Bit 6 reg_little_endian // unsigned , default = 0, big endian enable
+//Bit 5 reg_y_rev // unsigned , default = 0, vertical reverse enable
+//Bit 4 reg_x_rev // unsigned , default = 0, horizontal reverse enable
+//Bit 3 reserved
+//Bit 2:0 reg_pack_mode // unsigned , default = 3, 0:4bit 1:8bit 2:16bit 3:32bit 4:64bit 5:128bit
+#define DI_AFBCE_MMU_RMIF_CTRL2 ((0x2081 << 2) + 0xff000000)
+//Bit 31:30 reg_sw_rst // unsigned , default = 0,
+//Bit 29:24 reserved
+//Bit 23:18 reg_gclk_ctrl
+//Bit 17 reserved
+//Bit 16:0 reg_urgent_ctrl // unsigned , default = 0, urgent control reg :
+ // 16 reg_ugt_init : urgent initial value
+ // 15 reg_ugt_en : urgent enable
+ // 14 reg_ugt_type : 1= wrmif 0=rdmif
+ // 7:4 reg_ugt_top_th: urgent top threshold
+ // 3:0 reg_ugt_bot_th: urgent bottom threshold
+#define DI_AFBCE_MMU_RMIF_CTRL3 ((0x2082 << 2) + 0xff000000)
+//Bit 31:17 reserved
+//Bit 16 reg_acc_mode // unsigned , default = 1,
+//Bit 15:13 reserved
+//Bit 12:0 reg_stride // unsigned , default = 4096,
+#define DI_AFBCE_MMU_RMIF_CTRL4 ((0x2083 << 2) + 0xff000000)
+//Bit 31:0 reg_baddr // unsigned , default = 0,
+#define DI_AFBCE_MMU_RMIF_SCOPE_X ((0x2084 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_x_end // unsigned , default = 4095, the canvas hor end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_x_start // unsigned , default = 0, the canvas hor start pixel position
+#define DI_AFBCE_MMU_RMIF_SCOPE_Y ((0x2085 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_y_end // unsigned , default = 0, the canvas ver end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_y_start // unsigned , default = 0, the canvas ver start pixel positio
+#define DI_AFBCE_MMU_RMIF_RO_STAT ((0x2086 << 2) + 0xff000000)
+//Bit 15:0 reg_status // unsigned ,
+#define DI_AFBCE_PIP_CTRL ((0x208a << 2) + 0xff000000)
+//Bit 31:3 reserved
+//Bit 2 reg_enc_align_en //unsigned , RW,default = 1,
+//Bit 1 reg_pip_ini_ctrl //unsigned , RW,default = 0,
+//Bit 0 reg_pip_mode //unsigned , RW,default = 0,
+#define DI_AFBCE_ROT_CTRL ((0x208b << 2) + 0xff000000)
+//Bit 31:5 reserved
+//Bit 4 reg_rot_en //unsigned , RW,default = 0, rotation enable
+//Bit 3:0 reg_vstep //unsigned , RW,default = 8, rotation vstep ,setting acorrding rotation shrink mode
+#define DI_AFBCE_DIMM_CTRL ((0x208c << 2) + 0xff000000)
+//Bit 31 reg_dimm_layer_en //unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30 reserved
+//Bit 29:0 reg_dimm_data //unsigned , RW,default = 29'h00080200,dimm_layer data
+#define DI_AFBCE_BND_DEC_MISC ((0x208d << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 bnd_dec_rev_mode //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 25:24 bnd_dec_mif_urgent //unsigned , RW,default = 3 only pip mode use those bits,ususaly don't need configure
+//Bit 23:22 bnd_dec_burst_len //unsigned , RW,default = 2 only pip mode use those bits,ususaly don't need configure
+//Bit 21:20 bnd_dec_ddr_blk_size //unsigned , RW,default = 1 only pip mode use those bits,ususaly don't need configure
+//Bit 19 reserved
+//Bit 18:16 bnd_dec_cmd_blk_size //unsigned , RW,default = 3 only pip mode use those bits,ususaly don't need configure
+//Bit 15 reserved
+//Bit 14 bnd_dec_blk_mem_mode //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 13 bnd_dec_addr_link_en //unsigned , RW,default = 1 only pip mode use those bits,ususaly don't need configure
+//Bit 12 bnd_dec_always_body_rden //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 11:0 bnd_dec_mif_lbuf_depth //unsigned , RW,default = 128 only pip mode use those bits,ususaly don't need configure
+#define DI_AFBCE_RD_ARB_MISC ((0x208e << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12 reg_arb_sw_rst //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 11:10 reserved
+//Bit 9 reg_arb_arblk_last1 //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 8 reg_arb_arblk_last0 //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 7:4 reg_arb_weight_ch1 //unsigned , RW,default = 4 only pip mode use those bits,ususaly don't need configure
+//Bit 3:0 reg_arb_weight_ch0 //unsigned , RW,default = 10 only pip mode use those bits,ususaly don't need configure
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: di_afbc_enc0_regs.h
+//
+// the segment is 8'h90-8'ha3
+//
+// Reading file: di_wrmif0_regs.h
+//
+#define NRWR_DBG_AXI_CMD_CNT ((0x2090 << 2) + 0xff000000)
+#define NRWR_DBG_AXI_DAT_CNT ((0x2091 << 2) + 0xff000000)
+#define DI_NRWR_CANVAS ((0x2092 << 2) + 0xff000000)
+#define DI_NRWR_URGENT ((0x2093 << 2) + 0xff000000)
+#define DI_NRWR_X ((0x2094 << 2) + 0xff000000)
+#define DI_NRWR_Y ((0x2095 << 2) + 0xff000000)
+//bit 31:30 NRWR_words_lim
+//bit 29 NRWR_rev_y
+//bit 28:16 NRWR_start_y
+//bit 15 NRWR_ext_en
+//bit 12:0 NRWR_end_y
+#define DI_NRWR_CTRL ((0x2096 << 2) + 0xff000000)
+//bit 31 pending_ddr_wrrsp_NRWR
+//bit 30 NRWR_reg_swap
+//bit 29:26 NRWR_burst_lim
+//bit 25 NRWR_canvas_syncen
+//bit 24 NRWR_no_clk_gate
+//bit 23:22 NRWR_rgb_mode 0:422 to one canvas;1:4:4:4 to one canvas 2:Y to luma , CBCR to chroma canvas ,for nv12/21; 3 : reserved
+//bit 21:20 NRWR_hconv_mode
+//bit 19:18 NRWR_vconv_mode
+//bit 17 NRWR_swap_cbcr
+//bit 16 NRWR_urgent
+//bit 15:8 NRWR_canvas_index_chroma
+//bit 7:0 NRWR_canvas_index_luma
+#define DI_NRWR_SHRK_CTRL ((0x2097 << 2) + 0xff000000)
+//bit 31:10 reserved
+//bit 9:8 reg_vshrk_mode unsigned, default = 0, 0:1/2 horizonal shrink 1:1/4 horizonal shrink 2:1/8 horizonal shrink
+//bit 7:6 reg_hshrk_mode unsigned, default = 0, 0:1/2 vertical shrink 1:1/4 vertical shrink 2:1/8 vertical shrink
+//bit 5:2 reg_gclk_ctrl unsigned, default = 0
+//bit 1 reg_frm_rst unsigned, default = 0
+//bit 0 reg_shrk_en unsigned, default = 0
+#define DI_NRWR_SHRK_SIZE ((0x2098 << 2) + 0xff000000)
+//bit 31:26 reserved
+//bit 25:13 reg_frm_hsize unsigned, default = 1920, hsize in
+//bit 12:0 reg_frm_vsize unsigned, default = 1080, vsize in
+#define DI_NRWR_CROP_CTRL ((0x209a << 2) + 0xff000000)
+//Bit 31 reg_crop_en unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30:4 reserved
+//Bit 3:0 reg_hold_line unsigned , RW,default = 4,dimm_layer data
+#define DI_NRWR_CROP_DIMM_CTRL ((0x209b << 2) + 0xff000000)
+//Bit 31 reg_dimm_layer_en unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30 reserved
+//Bit 29:0 reg_dimm_data unsigned , RW,default = 29'h00080200,dimm_layer data
+#define DI_NRWR_CROP_SIZE_IN ((0x209c << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 reg_crop_hsize unsigned, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, reg_crop_vsize unsigned, default = 1080 , pic vert size in unit: pixel
+#define DI_NRWR_CROP_HSCOPE ((0x209d << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_cropwin_end_h unsigned, default = 1919 ;
+//Bit 15:13, reserved
+//Bit 12:0, reg_cropwin_bgn_h unsigned, default = 0 ;
+#define DI_NRWR_CROP_VSCOPE ((0x209e << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_cropwin_end_v unsigned, default = 1079 ;
+//Bit 15:13, reserved
+//Bit 12:0, reg_cropwin_bgn_v unsigned, default = 0 ;
+#define DI_NRWR_BADDR0 ((0x20a0 << 2) + 0xff000000)
+//Bit 31:0 wmif_baddr_luma unsigned, default = 0x20000
+#define DI_NRWR_STRIDE0 ((0x20a1 << 2) + 0xff000000)
+//Bit 31 canvas_mode_en unsigned, default = 0 ;
+//Bit 30:14 reserved
+//Bit 13:0 wmif_stride_luma unsigned, default = 0x1000;
+#define DI_NRWR_BADDR1 ((0x20a2 << 2) + 0xff000000)
+//Bit 31:0 wmif_baddr_chroma unsigned, default = 0x20000
+#define DI_NRWR_STRIDE1 ((0x20a3 << 2) + 0xff000000)
+//Bit 31 canvas_mode_en unsigned, default = 0 ;
+//Bit 30:14 reserved
+//Bit 13:0 wmif_stride_chroma unsigned, default = 0x1000;
+//
+// Closing file: di_wrmif0_regs.h
+//
+// di afbc_enc
+// the segment is 8'hc0-8'hef
+//
+// Reading file: di_afbc_enc1_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DI_AFBCE1_ENABLE ((0x20c0 << 2) + 0xff000000)
+//Bit 31:20, gclk_ctrl unsigned , default = 0,
+//Bit 19:16, di_AFBCE1_sync_sel unsigned , default = 0,
+//Bit 15:14, reserved
+//Bit 13, enc_rst_mode unsigned , default = 0,
+//Bit 12, enc_en_mode unsigned , default = 0,
+//Bit 11:9, reserved
+//Bit 8, enc_enable unsigned , default = 0,
+//Bit 7:1, reserved
+//Bit 0, reserved enc_frm_start pulse use this bit don't use
+#define DI_AFBCE1_MODE ((0x20c1 << 2) + 0xff000000)
+//Bit 31:29, soft_rst unsigned, default = 0 ,the use as go_field
+//Bit 28, reserved unsigned, default = 0 , enable singal of crop
+//Bit 27:26, rev_mode unsigned, default = 0 , reverse mode
+//Bit 25:24, mif_urgent unsigned, default = 3 , info mif and data mif urgent
+//Bit 23, reserved
+//Bit 22:16, hold_line_num unsigned, default = 4, 0: burst1 1:burst2 2:burst4
+//Bit 15:14, burst_mode unsigned, default = 1, 0: burst1 1:burst2 2:burst4
+//Bit 13:1, reserved
+//Bit 0, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb
+#define DI_AFBCE1_SIZE_IN ((0x20c2 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hsize_in unsigned, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_in unsigned, default = 1080 , pic vert size in unit: pixel
+#define DI_AFBCE1_BLK_SIZE_IN ((0x20c3 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hblk_size unsigned, default = 60 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vblk_size unsigned, default = 270, pic vert size in unit: pixel
+#define DI_AFBCE1_HEAD_BADDR ((0x20c4 << 2) + 0xff000000)
+//Bit 31:0, head_baddr unsigned, default = 32'h00;
+#define DI_AFBCE1_MIF_SIZE ((0x20c5 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:28, ddr_blk_size unsigned, default = 1;
+//Bit 27, reserved
+//Bit 26:24, cmd_blk_size unsigned, default = 3;
+//Bit 23:21, reserved
+//Bit 20:16, uncmp_size unsigned, default = 20;
+//Bit 15:0, mmu_page_size unsigned, default = 4096;
+#define DI_AFBCE1_PIXEL_IN_HOR_SCOPE ((0x20c6 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, enc_win_end_h unsigned, default = 1919 ; //
+//Bit 15:13, reserved
+//Bit 12:0, enc_win_bgn_h unsigned, default = 0 ; //
+#define DI_AFBCE1_PIXEL_IN_VER_SCOPE ((0x20c7 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, enc_win_end_v unsigned, default = 1079 ; //
+//Bit 15:13, reserved
+//Bit 12:0, enc_win_bgn_v unsigned, default = 0 ; //
+#define DI_AFBCE1_CONV_CTRL ((0x20c8 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, fmt_ybuf_depth unsigned, default = 2048
+//Bit 15:12, reserved
+//Bit 11: 0, lbuf_depth unsigned, default = 256, unit=16 pixel need to set = 2^n
+#define DI_AFBCE1_MIF_HOR_SCOPE ((0x20c9 << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, blk_end_h unsigned, default = 0 ; //
+//Bit 15:10, reserved
+//Bit 9:0, blk_bgn_h unsigned, default = 59 ; //
+#define DI_AFBCE1_MIF_VER_SCOPE ((0x20ca << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, blk_end_v unsigned, default = 0 ; //
+//Bit 15:12, reserved
+//Bit 11:0, blk_bgn_v unsigned, default = 269 ; //
+#define DI_AFBCE1_STAT1 ((0x20cb << 2) + 0xff000000)
+//Bit 31, ro_frm_end_pulse1 unsigned, RO,default = 0 ;frame end status
+//Bit 30:0, ro_dbg_top_info1 unsigned, RO,default = 0 ;
+#define DI_AFBCE1_STAT2 ((0x20cc << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30:0, ro_dbg_top_info2 unsigned, RO,default = 0 ;
+#define DI_AFBCE1_FORMAT ((0x20cd << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11:10 reserved
+//Bit 9: 8 reg_format_mode // unsigned , RW, default = 2 data format;0 : YUV444, 1:YUV422, 2:YUV420, 3:RGB
+//Bit 7: 4 reg_compbits_c // unsigned , RW, default = 10 chroma bitwidth
+//Bit 3: 0 reg_compbits_y // unsigned , RW, default = 10 luma bitwidth
+#define DI_AFBCE1_MODE_EN ((0x20ce << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 reserved
+//Bit 25 reg_adpt_interleave_ymode // unsigned , RW, default = 0 force 0 to disable it: no HW implementation
+//Bit 24 reg_adpt_interleave_cmode // unsigned , RW, default = 0 force 0 to disable it: not HW implementation
+//Bit 23 reg_adpt_yinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
+//Bit 22 reg_adpt_yinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
+//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
+//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
+//Bit 19 reserved
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 11 reserved
+//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
+//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
+//Bit 8 reg_uncompress_split_mode // unsigned , RW, default = 0 0: no split; 1: split
+//Bit 7: 6 reserved
+//Bit 5 reg_input_padding_uv128 // unsigned , RW, default = 0 input picture 32x4 block gap mode: 0: pad uv=0; 1: pad uv=128
+//Bit 4 reg_dwds_padding_uv128 // unsigned , RW, default = 0 downsampled image for double write 32x gap mode: 0: pad uv=0; 1: pad uv=128
+//Bit 3: 1 reg_force_order_mode_value // unsigned , RW, default = 0 force order mode 0~7
+//Bit 0 reg_force_order_mode_en // unsigned , RW, default = 0 force order mode enable: 0: no force; 1: forced to force_value
+#define DI_AFBCE1_DWSCALAR ((0x20cf << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7: 6 reg_dwscalar_w0 // unsigned , RW, default = 3 horizontal 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 5: 4 reg_dwscalar_w1 // unsigned , RW, default = 0 horizontal 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 3: 2 reg_dwscalar_h0 // unsigned , RW, default = 2 vertical 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 1: 0 reg_dwscalar_h1 // unsigned , RW, default = 3 vertical 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+#define DI_AFBCE1_DEFCOLOR_1 ((0x20d0 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_enc_defalutcolor_3 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr]
+//Bit 11: 0 reg_enc_defalutcolor_0 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr]
+#define DI_AFBCE1_DEFCOLOR_2 ((0x20d1 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_enc_defalutcolor_2 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr]
+//Bit 11: 0 reg_enc_defalutcolor_1 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr]
+#define DI_AFBCE1_QUANT_ENABLE ((0x20d2 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_quant_expand_en_1 // unsigned , RW, default = 0 enable for quantization value expansion
+//Bit 10 reg_quant_expand_en_0 // unsigned , RW, default = 0 enable for quantization value expansion
+//Bit 9: 8 reg_bcleav_ofst // signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1;
+//Bit 7: 5 reserved
+//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy
+//Bit 3: 1 reserved
+//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy
+#define DI_AFBCE1_IQUANT_LUT_1 ((0x20d3 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE1_IQUANT_LUT_2 ((0x20d4 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE1_IQUANT_LUT_3 ((0x20d5 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE1_IQUANT_LUT_4 ((0x20d6 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define DI_AFBCE1_RQUANT_LUT_1 ((0x20d7 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_rquant_yclut_0_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting)
+//Bit 27 reserved
+//Bit 26:24 reg_rquant_yclut_0_10 // unsigned , RW, default = 5
+//Bit 23 reserved
+//Bit 22:20 reg_rquant_yclut_0_9 // unsigned , RW, default = 4
+//Bit 19 reserved
+//Bit 18:16 reg_rquant_yclut_0_8 // unsigned , RW, default = 4
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_0_7 // unsigned , RW, default = 3
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_0_6 // unsigned , RW, default = 3
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_0_5 // unsigned , RW, default = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_0_4 // unsigned , RW, default = 2
+#define DI_AFBCE1_RQUANT_LUT_2 ((0x20d8 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_0_3 // unsigned , RW, default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_0_2 // unsigned , RW, default = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_0_1 // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_0_0 // unsigned , RW, default = 0
+#define DI_AFBCE1_RQUANT_LUT_3 ((0x20d9 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_rquant_yclut_1_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting)
+//Bit 27 reserved
+//Bit 26:24 reg_rquant_yclut_1_10 // unsigned , RW, default = 5
+//Bit 23 reserved
+//Bit 22:20 reg_rquant_yclut_1_9 // unsigned , RW, default = 4
+//Bit 19 reserved
+//Bit 18:16 reg_rquant_yclut_1_8 // unsigned , RW, default = 4
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_1_7 // unsigned , RW, default = 3
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_1_6 // unsigned , RW, default = 3
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_1_5 // unsigned , RW, default = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_1_4 // unsigned , RW, default = 2
+#define DI_AFBCE1_RQUANT_LUT_4 ((0x20da << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_1_3 // unsigned , RW, default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_1_2 // unsigned , RW, default = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_1_1 // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_1_0 // unsigned , RW, default = 0
+#define DI_AFBCE1_YUV_FORMAT_CONV_MODE ((0x20db << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7 reserved
+//Bit 6: 4 reg_444to422_mode // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_422to420_mode // unsigned , RW, default = 0
+#define DI_AFBCE1_DUMMY_DATA ((0x20dc << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29: 0 reg_dummy_data // unsigned , default = 0 ;
+#define DI_AFBCE1_CLR_FLAG ((0x20dd << 2) + 0xff000000)
+//Bit 31:0 reg_di_AFBCE1_clr_flag // unsigned, default = 0 ;
+#define DI_AFBCE1_STA_FLAGT ((0x20de << 2) + 0xff000000)
+//Bit 31:0 ro_di_AFBCE1__sta_flag // unsigned, RO,default = 0 ;
+#define DI_AFBCE1_MMU_NUM ((0x20df << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 0 ro_frm_mmu_num // unsigned, RO,default = 0 ;
+#define DI_AFBCE1_MMU_RMIF_CTRL1 ((0x20e0 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_sync_sel // unsigned , default = 0, axi canvas id sync with frm rst
+//Bit 23:16 reg_canvas_id // unsigned , default = 0, axi canvas id num
+//Bit 15 reserved
+//Bit 14:12 reg_cmd_intr_len // unsigned , default = 1, interrupt send cmd when how many series axi cmd,
+ // 0=12 1=16 2=24 3=32 4=40 5=48 6=56 7=64
+//Bit 11:10 reg_cmd_req_size // unsigned , default = 1, how many room fifo have, then axi send series req, 0=16 1=32 2=24 3=64
+//Bit 9:8 reg_burst_len // unsigned , default = 2, burst type: 0-single 1-bst2 2-bst4
+//Bit 7 reg_swap_64bit // unsigned , default = 0, 64bits of 128bit swap enable
+//Bit 6 reg_little_endian // unsigned , default = 0, big endian enable
+//Bit 5 reg_y_rev // unsigned , default = 0, vertical reverse enable
+//Bit 4 reg_x_rev // unsigned , default = 0, horizontal reverse enable
+//Bit 3 reserved
+//Bit 2:0 reg_pack_mode // unsigned , default = 3, 0:4bit 1:8bit 2:16bit 3:32bit 4:64bit 5:128bit
+#define DI_AFBCE1_MMU_RMIF_CTRL2 ((0x20e1 << 2) + 0xff000000)
+//Bit 31:30 reg_sw_rst // unsigned , default = 0,
+//Bit 29:24 reserved
+//Bit 23:18 reg_gclk_ctrl
+//Bit 17 reserved
+//Bit 16:0 reg_urgent_ctrl // unsigned , default = 0, urgent control reg :
+ // 16 reg_ugt_init : urgent initial value
+ // 15 reg_ugt_en : urgent enable
+ // 14 reg_ugt_type : 1= wrmif 0=rdmif
+ // 7:4 reg_ugt_top_th: urgent top threshold
+ // 3:0 reg_ugt_bot_th: urgent bottom threshold
+#define DI_AFBCE1_MMU_RMIF_CTRL3 ((0x20e2 << 2) + 0xff000000)
+//Bit 31:17 reserved
+//Bit 16 reg_acc_mode // unsigned , default = 1,
+//Bit 15:13 reserved
+//Bit 12:0 reg_stride // unsigned , default = 4096,
+#define DI_AFBCE1_MMU_RMIF_CTRL4 ((0x20e3 << 2) + 0xff000000)
+//Bit 31:0 reg_baddr // unsigned , default = 0,
+#define DI_AFBCE1_MMU_RMIF_SCOPE_X ((0x20e4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_x_end // unsigned , default = 4095, the canvas hor end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_x_start // unsigned , default = 0, the canvas hor start pixel position
+#define DI_AFBCE1_MMU_RMIF_SCOPE_Y ((0x20e5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_y_end // unsigned , default = 0, the canvas ver end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_y_start // unsigned , default = 0, the canvas ver start pixel positio
+#define DI_AFBCE1_MMU_RMIF_RO_STAT ((0x20e6 << 2) + 0xff000000)
+//Bit 15:0 reg_status // unsigned ,
+#define DI_AFBCE1_PIP_CTRL ((0x20ea << 2) + 0xff000000)
+//Bit 31:3 reserved
+//Bit 2 reg_enc_align_en //unsigned , RW,default = 1,
+//Bit 1 reg_pip_ini_ctrl //unsigned , RW,default = 0,
+//Bit 0 reg_pip_mode //unsigned , RW,default = 0,
+#define DI_AFBCE1_ROT_CTRL ((0x20eb << 2) + 0xff000000)
+//Bit 31:5 reserved
+//Bit 4 reg_rot_en //unsigned , RW,default = 0, rotation enable
+//Bit 3:0 reg_vstep //unsigned , RW,default = 8, rotation vstep ,setting acorrding rotation shrink mode
+#define DI_AFBCE1_DIMM_CTRL ((0x20ec << 2) + 0xff000000)
+//Bit 31 reg_dimm_layer_en //unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30 reserved
+//Bit 29:0 reg_dimm_data //unsigned , RW,default = 29'h00080200,dimm_layer data
+#define DI_AFBCE1_BND_DEC_MISC ((0x20ed << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 bnd_dec_rev_mode //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 25:24 bnd_dec_mif_urgent //unsigned , RW,default = 3 only pip mode use those bits,ususaly don't need configure
+//Bit 23:22 bnd_dec_burst_len //unsigned , RW,default = 2 only pip mode use those bits,ususaly don't need configure
+//Bit 21:20 bnd_dec_ddr_blk_size //unsigned , RW,default = 1 only pip mode use those bits,ususaly don't need configure
+//Bit 19 reserved
+//Bit 18:16 bnd_dec_cmd_blk_size //unsigned , RW,default = 3 only pip mode use those bits,ususaly don't need configure
+//Bit 15 reserved
+//Bit 14 bnd_dec_blk_mem_mode //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 13 bnd_dec_addr_link_en //unsigned , RW,default = 1 only pip mode use those bits,ususaly don't need configure
+//Bit 12 bnd_dec_always_body_rden //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 11:0 bnd_dec_mif_lbuf_depth //unsigned , RW,default = 128 only pip mode use those bits,ususaly don't need configure
+#define DI_AFBCE1_RD_ARB_MISC ((0x20ee << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12 reg_arb_sw_rst //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 11:10 reserved
+//Bit 9 reg_arb_arblk_last1 //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 8 reg_arb_arblk_last0 //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 7:4 reg_arb_weight_ch1 //unsigned , RW,default = 4 only pip mode use those bits,ususaly don't need configure
+//Bit 3:0 reg_arb_weight_ch0 //unsigned , RW,default = 10 only pip mode use those bits,ususaly don't need configure
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: di_afbc_enc1_regs.h
+//
+// the segment is 8'hf0-8'hff, 8'ha8-8'hab
+//
+// Reading file: di_wrmif1_regs.h
+//
+#define DIWR_DBG_AXI_CMD_CNT ((0x20f0 << 2) + 0xff000000)
+#define DIWR_DBG_AXI_DAT_CNT ((0x20f1 << 2) + 0xff000000)
+#define DI_DIWR_CANVAS ((0x20f2 << 2) + 0xff000000)
+#define DI_DIWR_URGENT ((0x20f3 << 2) + 0xff000000)
+#define DI_DIWR_X ((0x20f4 << 2) + 0xff000000)
+#define DI_DIWR_Y ((0x20f5 << 2) + 0xff000000)
+//bit 31:30 diwr_words_lim
+//bit 29 diwr_rev_y
+//bit 28:16 diwr_start_y
+//bit 15 diwr_ext_en
+//bit 12:0 diwr_end_y
+#define DI_DIWR_CTRL ((0x20f6 << 2) + 0xff000000)
+//bit 31 pending_ddr_wrrsp_diwr
+//bit 30 diwr_reg_swap
+//bit 29:26 diwr_burst_lim
+//bit 25 diwr_canvas_syncen
+//bit 24 diwr_no_clk_gate
+//bit 23:22 diwr_rgb_mode 0:422 to one canvas;1:4:4:4 to one canvas 2:Y to luma , CBCR to chroma canvas ,for nv12/21; 3 : reserved
+//bit 21:20 diwr_hconv_mode
+//bit 19:18 diwr_vconv_mode
+//bit 17 diwr_swap_cbcr
+//bit 16 diwr_urgent
+//bit 15:8 diwr_canvas_index_chroma
+//bit 7:0 diwr_canvas_index_luma
+#define DI_DIWR_SHRK_CTRL ((0x20f7 << 2) + 0xff000000)
+//bit 31:10 reserved
+//bit 9:8 reg_vshrk_mode unsigned, default = 0, 0:1/2 horizonal shrink 1:1/4 horizonal shrink 2:1/8 horizonal shrink
+//bit 7:6 reg_hshrk_mode unsigned, default = 0, 0:1/2 vertical shrink 1:1/4 vertical shrink 2:1/8 vertical shrink
+//bit 5:2 reg_gclk_ctrl unsigned, default = 0
+//bit 1 reg_frm_rst unsigned, default = 0
+//bit 0 reg_shrk_en unsigned, default = 0
+#define DI_DIWR_SHRK_SIZE ((0x20f8 << 2) + 0xff000000)
+//bit 31:26 reserved
+//bit 25:13 reg_frm_hsize unsigned, default = 1920, hsize in
+//bit 12:0 reg_frm_vsize unsigned, default = 1080, vsize in
+#define DI_DIWR_CROP_CTRL ((0x20fa << 2) + 0xff000000)
+//Bit 31 reg_crop_en unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30:4 reserved
+//Bit 3:0 reg_hold_line unsigned , RW,default = 4,dimm_layer data
+#define DI_DIWR_CROP_DIMM_CTRL ((0x20fb << 2) + 0xff000000)
+//Bit 31 reg_dimm_layer_en unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30 reserved
+//Bit 29:0 reg_dimm_data unsigned , RW,default = 29'h00080200,dimm_layer data
+#define DI_DIWR_CROP_SIZE_IN ((0x20fc << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 reg_crop_hsize unsigned, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, reg_crop_vsize unsigned, default = 1080 , pic vert size in unit: pixel
+#define DI_DIWR_CROP_HSCOPE ((0x20fd << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_cropwin_end_h unsigned, default = 1919 ;
+//Bit 15:13, reserved
+//Bit 12:0, reg_cropwin_bgn_h unsigned, default = 0 ;
+#define DI_DIWR_CROP_VSCOPE ((0x20fe << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_cropwin_end_v unsigned, default = 1079 ;
+//Bit 15:13, reserved
+//Bit 12:0, reg_cropwin_bgn_v unsigned, default = 0 ;
+#define DI_DIWR_BADDR0 ((0x20a8 << 2) + 0xff000000)
+//Bit 31:0 wmif_baddr_luma unsigned, default = 0x20000
+#define DI_DIWR_STRIDE0 ((0x20a9 << 2) + 0xff000000)
+//Bit 31 canvas_mode_en unsigned, default = 0 ;
+//Bit 30:14 reserved
+//Bit 13:0 wmif_stride_luma unsigned, default = 0x1000;
+#define DI_DIWR_BADDR1 ((0x20aa << 2) + 0xff000000)
+//Bit 31:0 wmif_baddr_chroma unsigned, default = 0x20000
+#define DI_DIWR_STRIDE1 ((0x20ab << 2) + 0xff000000)
+//Bit 31 canvas_mode_en unsigned, default = 0 ;
+//Bit 30:14 reserved
+//Bit 13:0 wmif_stride_chroma unsigned, default = 0x1000;
+//
+// Closing file: di_wrmif1_regs.h
+//
+//
+// Closing file: vregs_clk1.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VENC1A_VCBUS_BASE = 0x21
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: venc_1_regs.h
+//
+//===========================================================================
+// Video Interface Registers 0xa00 - 0xbff
+//===========================================================================
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 0 -- vfifo2vd_en
+#define ENCP1_VFIFO2VD_CTL ((0x2158 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCP1_VFIFO2VD_PIXEL_START ((0x2159 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCP1_VFIFO2VD_PIXEL_END ((0x215a << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCP1_VFIFO2VD_LINE_TOP_START ((0x215b << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCP1_VFIFO2VD_LINE_TOP_END ((0x215c << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCP1_VFIFO2VD_LINE_BOT_START ((0x215d << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCP1_VFIFO2VD_LINE_BOT_END ((0x215e << 2) + 0xff000000)
+// Route the hsync and vsync signals round the chip. There are three
+// sources and users of these signals: VIU, internal video encoder, and
+// the pins on the chip. Some muxing is still being done in the VIU. It
+// was not moved to the venc module so that the same exact VIU code could
+// be used both in Twister and Twister2000.
+// Bit 2: venc_sync_source (1=>pins, 0=>viu)
+// Bit 1: viu_sync_source (1=>pins, 0=>venc)
+// Bit 0: vpins_sync_source (1=>venc, 0=>viu)
+#define VENC1_SYNC_ROUTE ((0x2160 << 2) + 0xff000000)
+ // encoder address space is assigned
+ // to the video encoder interface status
+ // register
+#define VENC1_VIDEO_EXSRC ((0x2161 << 2) + 0xff000000)
+#define VENC1_DVI_SETTING ((0x2162 << 2) + 0xff000000)
+#define VENC1_C656_CTRL ((0x2163 << 2) + 0xff000000)
+#define VENC1_UPSAMPLE_CTRL0 ((0x2164 << 2) + 0xff000000)
+#define VENC1_UPSAMPLE_CTRL1 ((0x2165 << 2) + 0xff000000)
+#define VENC1_UPSAMPLE_CTRL2 ((0x2166 << 2) + 0xff000000)
+// Invert control for tcon output
+// bit[15:14] -- vsync, hsync,
+// bit[13:0] -- oev3, oev2, cpv2, cph3, cph2, cph1, oeh, vcom, stv2, stv1, cpv1, oev1, sth1, sth2
+#define TCON1_INVERT_CTL ((0x2167 << 2) + 0xff000000)
+#define VENC1_VIDEO_PROG_MODE ((0x2168 << 2) + 0xff000000)
+//---- Venc pixel/line info
+#define VENC1_ENCI_LINE ((0x2169 << 2) + 0xff000000)
+#define VENC1_ENCI_PIXEL ((0x216a << 2) + 0xff000000)
+#define VENC1_ENCP_LINE ((0x216b << 2) + 0xff000000)
+#define VENC1_ENCP_PIXEL ((0x216c << 2) + 0xff000000)
+//---- Status
+#define VENC1_STATA ((0x216d << 2) + 0xff000000)
+//---- Interrupt setting
+#define VENC1_INTCTRL ((0x216e << 2) + 0xff000000)
+#define VENC1_INTFLAG ((0x216f << 2) + 0xff000000)
+//--------- Video test configuration
+#define VENC1_VIDEO_TST_EN ((0x2170 << 2) + 0xff000000)
+#define VENC1_VIDEO_TST_MDSEL ((0x2171 << 2) + 0xff000000)
+#define VENC1_VIDEO_TST_Y ((0x2172 << 2) + 0xff000000)
+#define VENC1_VIDEO_TST_CB ((0x2173 << 2) + 0xff000000)
+#define VENC1_VIDEO_TST_CR ((0x2174 << 2) + 0xff000000)
+#define VENC1_VIDEO_TST_CLRBAR_STRT ((0x2175 << 2) + 0xff000000)
+#define VENC1_VIDEO_TST_CLRBAR_WIDTH ((0x2176 << 2) + 0xff000000)
+#define VENC1_VIDEO_TST_VDCNT_STSET ((0x2177 << 2) + 0xff000000)
+//----- Video dac setting
+#define VENC1_VDAC_DACSEL0 ((0x2178 << 2) + 0xff000000)
+#define VENC1_VDAC_DACSEL1 ((0x2179 << 2) + 0xff000000)
+#define VENC1_VDAC_DACSEL2 ((0x217a << 2) + 0xff000000)
+#define VENC1_VDAC_DACSEL3 ((0x217b << 2) + 0xff000000)
+#define VENC1_VDAC_DACSEL4 ((0x217c << 2) + 0xff000000)
+#define VENC1_VDAC_DACSEL5 ((0x217d << 2) + 0xff000000)
+#define VENC1_VDAC_SETTING ((0x217e << 2) + 0xff000000)
+#define VENC1_VDAC_TST_VAL ((0x217f << 2) + 0xff000000)
+#define VENC1_VDAC_DAC0_GAINCTRL ((0x21f0 << 2) + 0xff000000)
+#define VENC1_VDAC_DAC0_OFFSET ((0x21f1 << 2) + 0xff000000)
+#define VENC1_VDAC_DAC1_GAINCTRL ((0x21f2 << 2) + 0xff000000)
+#define VENC1_VDAC_DAC1_OFFSET ((0x21f3 << 2) + 0xff000000)
+#define VENC1_VDAC_DAC2_GAINCTRL ((0x21f4 << 2) + 0xff000000)
+#define VENC1_VDAC_DAC2_OFFSET ((0x21f5 << 2) + 0xff000000)
+#define VENC1_VDAC_DAC3_GAINCTRL ((0x21f6 << 2) + 0xff000000)
+#define VENC1_VDAC_DAC3_OFFSET ((0x21f7 << 2) + 0xff000000)
+#define VENC1_VDAC_DAC4_GAINCTRL ((0x21f8 << 2) + 0xff000000)
+#define VENC1_VDAC_DAC4_OFFSET ((0x21f9 << 2) + 0xff000000)
+#define VENC1_VDAC_DAC5_GAINCTRL ((0x21fa << 2) + 0xff000000)
+#define VENC1_VDAC_DAC5_OFFSET ((0x21fb << 2) + 0xff000000)
+#define VENC1_VDAC_FIFO_CTRL ((0x21fc << 2) + 0xff000000)
+#define ENCL1_TCON_INVERT_CTL ((0x21fd << 2) + 0xff000000)
+//
+// Closing file: venc_1_regs.h
+//
+//
+// Reading file: enc480p_1_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+// Video Encoder 480p Registers 0xb80 - 0xbef
+//===========================================================================
+//-------- Video basic setting
+#define ENCP1_VIDEO_EN ((0x2180 << 2) + 0xff000000)
+#define ENCP1_VIDEO_SYNC_MODE ((0x2181 << 2) + 0xff000000)
+#define ENCP1_MACV_EN ((0x2182 << 2) + 0xff000000)
+#define ENCP1_VIDEO_Y_SCL ((0x2183 << 2) + 0xff000000)
+#define ENCP1_VIDEO_PB_SCL ((0x2184 << 2) + 0xff000000)
+#define ENCP1_VIDEO_PR_SCL ((0x2185 << 2) + 0xff000000)
+#define ENCP1_VIDEO_SYNC_SCL ((0x2186 << 2) + 0xff000000)
+#define ENCP1_VIDEO_MACV_SCL ((0x2187 << 2) + 0xff000000)
+#define ENCP1_VIDEO_Y_OFFST ((0x2188 << 2) + 0xff000000)
+#define ENCP1_VIDEO_PB_OFFST ((0x2189 << 2) + 0xff000000)
+#define ENCP1_VIDEO_PR_OFFST ((0x218a << 2) + 0xff000000)
+#define ENCP1_VIDEO_SYNC_OFFST ((0x218b << 2) + 0xff000000)
+#define ENCP1_VIDEO_MACV_OFFST ((0x218c << 2) + 0xff000000)
+//----- Video mode
+#define ENCP1_VIDEO_MODE ((0x218d << 2) + 0xff000000)
+#define ENCP1_VIDEO_MODE_ADV ((0x218e << 2) + 0xff000000)
+//--------------- Debug pins
+#define ENCP1_DBG_PX_RST ((0x2190 << 2) + 0xff000000)
+#define ENCP1_DBG_LN_RST ((0x2191 << 2) + 0xff000000)
+#define ENCP1_DBG_PX_INT ((0x2192 << 2) + 0xff000000)
+#define ENCP1_DBG_LN_INT ((0x2193 << 2) + 0xff000000)
+//----------- Video Advanced setting
+#define ENCP1_VIDEO_YFP1_HTIME ((0x2194 << 2) + 0xff000000)
+#define ENCP1_VIDEO_YFP2_HTIME ((0x2195 << 2) + 0xff000000)
+#define ENCP1_VIDEO_YC_DLY ((0x2196 << 2) + 0xff000000)
+#define ENCP1_VIDEO_MAX_PXCNT ((0x2197 << 2) + 0xff000000)
+#define ENCP1_VIDEO_HSPULS_BEGIN ((0x2198 << 2) + 0xff000000)
+#define ENCP1_VIDEO_HSPULS_END ((0x2199 << 2) + 0xff000000)
+#define ENCP1_VIDEO_HSPULS_SWITCH ((0x219a << 2) + 0xff000000)
+#define ENCP1_VIDEO_VSPULS_BEGIN ((0x219b << 2) + 0xff000000)
+#define ENCP1_VIDEO_VSPULS_END ((0x219c << 2) + 0xff000000)
+#define ENCP1_VIDEO_VSPULS_BLINE ((0x219d << 2) + 0xff000000)
+#define ENCP1_VIDEO_VSPULS_ELINE ((0x219e << 2) + 0xff000000)
+#define ENCP1_VIDEO_EQPULS_BEGIN ((0x219f << 2) + 0xff000000)
+#define ENCP1_VIDEO_EQPULS_END ((0x21a0 << 2) + 0xff000000)
+#define ENCP1_VIDEO_EQPULS_BLINE ((0x21a1 << 2) + 0xff000000)
+#define ENCP1_VIDEO_EQPULS_ELINE ((0x21a2 << 2) + 0xff000000)
+#define ENCP1_VIDEO_HAVON_END ((0x21a3 << 2) + 0xff000000)
+#define ENCP1_VIDEO_HAVON_BEGIN ((0x21a4 << 2) + 0xff000000)
+#define ENCP1_VIDEO_VAVON_ELINE ((0x21af << 2) + 0xff000000)
+#define ENCP1_VIDEO_VAVON_BLINE ((0x21a6 << 2) + 0xff000000)
+#define ENCP1_VIDEO_HSO_BEGIN ((0x21a7 << 2) + 0xff000000)
+#define ENCP1_VIDEO_HSO_END ((0x21a8 << 2) + 0xff000000)
+#define ENCP1_VIDEO_VSO_BEGIN ((0x21a9 << 2) + 0xff000000)
+#define ENCP1_VIDEO_VSO_END ((0x21aa << 2) + 0xff000000)
+#define ENCP1_VIDEO_VSO_BLINE ((0x21ab << 2) + 0xff000000)
+#define ENCP1_VIDEO_VSO_ELINE ((0x21ac << 2) + 0xff000000)
+#define ENCP1_VIDEO_SYNC_WAVE_CURVE ((0x21ad << 2) + 0xff000000)
+#define ENCP1_VIDEO_MAX_LNCNT ((0x21ae << 2) + 0xff000000)
+#define ENCP1_VIDEO_SY_VAL ((0x21b0 << 2) + 0xff000000)
+#define ENCP1_VIDEO_SY2_VAL ((0x21b1 << 2) + 0xff000000)
+#define ENCP1_VIDEO_BLANKY_VAL ((0x21b2 << 2) + 0xff000000)
+#define ENCP1_VIDEO_BLANKPB_VAL ((0x21b3 << 2) + 0xff000000)
+#define ENCP1_VIDEO_BLANKPR_VAL ((0x21b4 << 2) + 0xff000000)
+#define ENCP1_VIDEO_HOFFST ((0x21b5 << 2) + 0xff000000)
+#define ENCP1_VIDEO_VOFFST ((0x21b6 << 2) + 0xff000000)
+#define ENCP1_VIDEO_RGB_CTRL ((0x21b7 << 2) + 0xff000000)
+#define ENCP1_VIDEO_FILT_CTRL ((0x21b8 << 2) + 0xff000000)
+#define ENCP1_VIDEO_OFLD_VPEQ_OFST ((0x21b9 << 2) + 0xff000000)
+#define ENCP1_VIDEO_OFLD_VOAV_OFST ((0x21ba << 2) + 0xff000000)
+#define ENCP1_VIDEO_MATRIX_CB ((0x21bb << 2) + 0xff000000)
+#define ENCP1_VIDEO_MATRIX_CR ((0x21bc << 2) + 0xff000000)
+#define ENCP1_VIDEO_RGBIN_CTRL ((0x21bd << 2) + 0xff000000)
+//------------------Macrovision advanced setting
+#define ENCP1_MACV_BLANKY_VAL ((0x21c0 << 2) + 0xff000000)
+#define ENCP1_MACV_MAXY_VAL ((0x21c1 << 2) + 0xff000000)
+#define ENCP1_MACV_1ST_PSSYNC_STRT ((0x21c2 << 2) + 0xff000000)
+#define ENCP1_MACV_PSSYNC_STRT ((0x21c3 << 2) + 0xff000000)
+#define ENCP1_MACV_AGC_STRT ((0x21c4 << 2) + 0xff000000)
+#define ENCP1_MACV_AGC_END ((0x21c5 << 2) + 0xff000000)
+#define ENCP1_MACV_WAVE_END ((0x21c6 << 2) + 0xff000000)
+#define ENCP1_MACV_STRTLINE ((0x21c7 << 2) + 0xff000000)
+#define ENCP1_MACV_ENDLINE ((0x21c8 << 2) + 0xff000000)
+#define ENCP1_MACV_TS_CNT_MAX_L ((0x21c9 << 2) + 0xff000000)
+#define ENCP1_MACV_TS_CNT_MAX_H ((0x21ca << 2) + 0xff000000)
+#define ENCP1_MACV_TIME_DOWN ((0x21cb << 2) + 0xff000000)
+#define ENCP1_MACV_TIME_LO ((0x21cc << 2) + 0xff000000)
+#define ENCP1_MACV_TIME_UP ((0x21cd << 2) + 0xff000000)
+#define ENCP1_MACV_TIME_RST ((0x21ce << 2) + 0xff000000)
+//---------------- VBI control -------------------
+#define ENCP1_VBI_CTRL ((0x21d0 << 2) + 0xff000000)
+#define ENCP1_VBI_SETTING ((0x21d1 << 2) + 0xff000000)
+#define ENCP1_VBI_BEGIN ((0x21d2 << 2) + 0xff000000)
+#define ENCP1_VBI_WIDTH ((0x21d3 << 2) + 0xff000000)
+#define ENCP1_VBI_HVAL ((0x21d4 << 2) + 0xff000000)
+#define ENCP1_VBI_DATA0 ((0x21d5 << 2) + 0xff000000)
+#define ENCP1_VBI_DATA1 ((0x21d6 << 2) + 0xff000000)
+//----------------C656 OUT Control------------- Grant
+#define C656_HS_ST_1 ((0x21e0 << 2) + 0xff000000)
+#define C656_HS_ED_1 ((0x21e1 << 2) + 0xff000000)
+#define C656_VS_LNST_E_1 ((0x21e2 << 2) + 0xff000000)
+#define C656_VS_LNST_O_1 ((0x21e3 << 2) + 0xff000000)
+#define C656_VS_LNED_E_1 ((0x21e4 << 2) + 0xff000000)
+#define C656_VS_LNED_O_1 ((0x21e5 << 2) + 0xff000000)
+#define C656_FS_LNST_1 ((0x21e6 << 2) + 0xff000000)
+#define C656_FS_LNED_1 ((0x21e7 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: enc480p_1_regs.h
+//
+//
+// Reading file: enci_1_regs.h
+//
+//===========================================================================
+// Video Interface Registers 0xb00 - 0xb57
+//===========================================================================
+#define ENCI1_VIDEO_MODE ((0x2100 << 2) + 0xff000000)
+#define ENCI1_VIDEO_MODE_ADV ((0x2101 << 2) + 0xff000000)
+#define ENCI1_VIDEO_FSC_ADJ ((0x2102 << 2) + 0xff000000)
+#define ENCI1_VIDEO_BRIGHT ((0x2103 << 2) + 0xff000000)
+#define ENCI1_VIDEO_CONT ((0x2104 << 2) + 0xff000000)
+#define ENCI1_VIDEO_SAT ((0x2105 << 2) + 0xff000000)
+#define ENCI1_VIDEO_HUE ((0x2106 << 2) + 0xff000000)
+#define ENCI1_VIDEO_SCH ((0x2107 << 2) + 0xff000000)
+#define ENCI1_SYNC_MODE ((0x2108 << 2) + 0xff000000)
+#define ENCI1_SYNC_CTRL ((0x2109 << 2) + 0xff000000)
+#define ENCI1_SYNC_HSO_BEGIN ((0x210a << 2) + 0xff000000)
+#define ENCI1_SYNC_HSO_END ((0x210b << 2) + 0xff000000)
+#define ENCI1_SYNC_VSO_EVN ((0x210c << 2) + 0xff000000)
+#define ENCI1_SYNC_VSO_ODD ((0x210d << 2) + 0xff000000)
+#define ENCI1_SYNC_VSO_EVNLN ((0x210e << 2) + 0xff000000)
+#define ENCI1_SYNC_VSO_ODDLN ((0x210f << 2) + 0xff000000)
+#define ENCI1_SYNC_HOFFST ((0x2110 << 2) + 0xff000000)
+#define ENCI1_SYNC_VOFFST ((0x2111 << 2) + 0xff000000)
+#define ENCI1_SYNC_ADJ ((0x2112 << 2) + 0xff000000)
+#define ENCI1_RGB_SETTING ((0x2113 << 2) + 0xff000000)
+//`define ENCI1_CMPN_MATRIX_CB 8'h14
+//`define ENCI1_CMPN_MATRIX_CR 8'h15
+#define ENCI1_DE_H_BEGIN ((0x2116 << 2) + 0xff000000)
+#define ENCI1_DE_H_END ((0x2117 << 2) + 0xff000000)
+#define ENCI1_DE_V_BEGIN_EVEN ((0x2118 << 2) + 0xff000000)
+#define ENCI1_DE_V_END_EVEN ((0x2119 << 2) + 0xff000000)
+#define ENCI1_DE_V_BEGIN_ODD ((0x211a << 2) + 0xff000000)
+#define ENCI1_DE_V_END_ODD ((0x211b << 2) + 0xff000000)
+#define ENCI1_VBI_SETTING ((0x2120 << 2) + 0xff000000)
+#define ENCI1_VBI_CCDT_EVN ((0x2121 << 2) + 0xff000000)
+#define ENCI1_VBI_CCDT_ODD ((0x2122 << 2) + 0xff000000)
+#define ENCI1_VBI_CC525_LN ((0x2123 << 2) + 0xff000000)
+#define ENCI1_VBI_CC625_LN ((0x2124 << 2) + 0xff000000)
+#define ENCI1_VBI_WSSDT ((0x2125 << 2) + 0xff000000)
+#define ENCI1_VBI_WSS_LN ((0x2126 << 2) + 0xff000000)
+#define ENCI1_VBI_CGMSDT_L ((0x2127 << 2) + 0xff000000)
+#define ENCI1_VBI_CGMSDT_H ((0x2128 << 2) + 0xff000000)
+#define ENCI1_VBI_CGMS_LN ((0x2129 << 2) + 0xff000000)
+#define ENCI1_VBI_TTX_HTIME ((0x212a << 2) + 0xff000000)
+#define ENCI1_VBI_TTX_LN ((0x212b << 2) + 0xff000000)
+#define ENCI1_VBI_TTXDT0 ((0x212c << 2) + 0xff000000)
+#define ENCI1_VBI_TTXDT1 ((0x212d << 2) + 0xff000000)
+#define ENCI1_VBI_TTXDT2 ((0x212e << 2) + 0xff000000)
+#define ENCI1_VBI_TTXDT3 ((0x212f << 2) + 0xff000000)
+#define ENCI1_MACV_N0 ((0x2130 << 2) + 0xff000000)
+#define ENCI1_MACV_N1 ((0x2131 << 2) + 0xff000000)
+#define ENCI1_MACV_N2 ((0x2132 << 2) + 0xff000000)
+#define ENCI1_MACV_N3 ((0x2133 << 2) + 0xff000000)
+#define ENCI1_MACV_N4 ((0x2134 << 2) + 0xff000000)
+#define ENCI1_MACV_N5 ((0x2135 << 2) + 0xff000000)
+#define ENCI1_MACV_N6 ((0x2136 << 2) + 0xff000000)
+#define ENCI1_MACV_N7 ((0x2137 << 2) + 0xff000000)
+#define ENCI1_MACV_N8 ((0x2138 << 2) + 0xff000000)
+#define ENCI1_MACV_N9 ((0x2139 << 2) + 0xff000000)
+#define ENCI1_MACV_N10 ((0x213a << 2) + 0xff000000)
+#define ENCI1_MACV_N11 ((0x213b << 2) + 0xff000000)
+#define ENCI1_MACV_N12 ((0x213c << 2) + 0xff000000)
+#define ENCI1_MACV_N13 ((0x213d << 2) + 0xff000000)
+#define ENCI1_MACV_N14 ((0x213e << 2) + 0xff000000)
+#define ENCI1_MACV_N15 ((0x213f << 2) + 0xff000000)
+#define ENCI1_MACV_N16 ((0x2140 << 2) + 0xff000000)
+#define ENCI1_MACV_N17 ((0x2141 << 2) + 0xff000000)
+#define ENCI1_MACV_N18 ((0x2142 << 2) + 0xff000000)
+#define ENCI1_MACV_N19 ((0x2143 << 2) + 0xff000000)
+#define ENCI1_MACV_N20 ((0x2144 << 2) + 0xff000000)
+#define ENCI1_MACV_N21 ((0x2145 << 2) + 0xff000000)
+#define ENCI1_MACV_N22 ((0x2146 << 2) + 0xff000000)
+//`define ENCI1_MACV_P_AGC 8'h47
+#define ENCI1_DBG_PX_RST ((0x2148 << 2) + 0xff000000)
+#define ENCI1_DBG_FLDLN_RST ((0x2149 << 2) + 0xff000000)
+#define ENCI1_DBG_PX_INT ((0x214a << 2) + 0xff000000)
+#define ENCI1_DBG_FLDLN_INT ((0x214b << 2) + 0xff000000)
+#define ENCI1_DBG_MAXPX ((0x214c << 2) + 0xff000000)
+#define ENCI1_DBG_MAXLN ((0x214d << 2) + 0xff000000)
+#define ENCI1_MACV_MAX_AMP ((0x2150 << 2) + 0xff000000)
+#define ENCI1_MACV_PULSE_LO ((0x2151 << 2) + 0xff000000)
+#define ENCI1_MACV_PULSE_HI ((0x2152 << 2) + 0xff000000)
+#define ENCI1_MACV_BKP_MAX ((0x2153 << 2) + 0xff000000)
+#define ENCI1_CFILT_CTRL ((0x2154 << 2) + 0xff000000)
+#define ENCI1_CFILT7 ((0x2155 << 2) + 0xff000000)
+#define ENCI1_YC_DELAY ((0x2156 << 2) + 0xff000000)
+#define ENCI1_VIDEO_EN ((0x2157 << 2) + 0xff000000)
+//
+// Closing file: enci_1_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VENC1B_VCBUS_BASE = 0x22
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: venc2_1_regs.h
+//
+//===========================================================================
+// Venc Registers (Cont.) 0xc00 - 0xcff (VENC registers 0xc00 - 0xcef)
+//===========================================================================
+// Program video control signals from ENCI core to DVI/HDMI interface
+#define ENCI1_DVI_HSO_BEGIN ((0x2200 << 2) + 0xff000000)
+#define ENCI1_DVI_HSO_END ((0x2201 << 2) + 0xff000000)
+#define ENCI1_DVI_VSO_BLINE_EVN ((0x2202 << 2) + 0xff000000)
+#define ENCI1_DVI_VSO_BLINE_ODD ((0x2203 << 2) + 0xff000000)
+#define ENCI1_DVI_VSO_ELINE_EVN ((0x2204 << 2) + 0xff000000)
+#define ENCI1_DVI_VSO_ELINE_ODD ((0x2205 << 2) + 0xff000000)
+#define ENCI1_DVI_VSO_BEGIN_EVN ((0x2206 << 2) + 0xff000000)
+#define ENCI1_DVI_VSO_BEGIN_ODD ((0x2207 << 2) + 0xff000000)
+#define ENCI1_DVI_VSO_END_EVN ((0x2208 << 2) + 0xff000000)
+#define ENCI1_DVI_VSO_END_ODD ((0x2209 << 2) + 0xff000000)
+// Define cmpt and cvbs cb/cr delay after ENCI chroma filters
+// Bit 15:12 RW, enci_cb_cvbs_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+// Bit 11: 8 RW, enci_cr_cvbs_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+// Bit 7: 4 RW, enci_cb_cmpt_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+// Bit 3: 0 RW, enci_cr_cmpt_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+#define ENCI1_CFILT_CTRL2 ((0x220a << 2) + 0xff000000)
+#define ENCI1_DACSEL_0 ((0x220b << 2) + 0xff000000)
+#define ENCI1_DACSEL_1 ((0x220c << 2) + 0xff000000)
+#define ENCP1_DACSEL_0 ((0x220d << 2) + 0xff000000)
+#define ENCP1_DACSEL_1 ((0x220e << 2) + 0xff000000)
+#define ENCP1_MAX_LINE_SWITCH_POINT ((0x220f << 2) + 0xff000000)
+#define ENCI1_TST_EN ((0x2210 << 2) + 0xff000000)
+#define ENCI1_TST_MDSEL ((0x2211 << 2) + 0xff000000)
+#define ENCI1_TST_Y ((0x2212 << 2) + 0xff000000)
+#define ENCI1_TST_CB ((0x2213 << 2) + 0xff000000)
+#define ENCI1_TST_CR ((0x2214 << 2) + 0xff000000)
+#define ENCI1_TST_CLRBAR_STRT ((0x2215 << 2) + 0xff000000)
+#define ENCI1_TST_CLRBAR_WIDTH ((0x2216 << 2) + 0xff000000)
+#define ENCI1_TST_VDCNT_STSET ((0x2217 << 2) + 0xff000000)
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 7 -- vfifo2vd_drop
+// bit 6:1 -- vfifo2vd_delay
+// bit 0 -- vfifo2vd_en
+#define ENCI1_VFIFO2VD_CTL ((0x2218 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCI1_VFIFO2VD_PIXEL_START ((0x2219 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCI1_VFIFO2VD_PIXEL_END ((0x221a << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCI1_VFIFO2VD_LINE_TOP_START ((0x221b << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCI1_VFIFO2VD_LINE_TOP_END ((0x221c << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCI1_VFIFO2VD_LINE_BOT_START ((0x221d << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCI1_VFIFO2VD_LINE_BOT_END ((0x221e << 2) + 0xff000000)
+#define ENCI1_VFIFO2VD_CTL2 ((0x221f << 2) + 0xff000000)
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 7 -- vfifo2vd_drop
+// bit 6:1 -- vfifo2vd_delay
+// bit 0 -- vfifo2vd_en
+#define ENCT1_VFIFO2VD_CTL ((0x2220 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCT1_VFIFO2VD_PIXEL_START ((0x2221 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCT1_VFIFO2VD_PIXEL_END ((0x2222 << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCT1_VFIFO2VD_LINE_TOP_START ((0x2223 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCT1_VFIFO2VD_LINE_TOP_END ((0x2224 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCT1_VFIFO2VD_LINE_BOT_START ((0x2225 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCT1_VFIFO2VD_LINE_BOT_END ((0x2226 << 2) + 0xff000000)
+#define ENCT1_VFIFO2VD_CTL2 ((0x2227 << 2) + 0xff000000)
+#define ENCT1_TST_EN ((0x2228 << 2) + 0xff000000)
+#define ENCT1_TST_MDSEL ((0x2229 << 2) + 0xff000000)
+#define ENCT1_TST_Y ((0x222a << 2) + 0xff000000)
+#define ENCT1_TST_CB ((0x222b << 2) + 0xff000000)
+#define ENCT1_TST_CR ((0x222c << 2) + 0xff000000)
+#define ENCT1_TST_CLRBAR_STRT ((0x222d << 2) + 0xff000000)
+#define ENCT1_TST_CLRBAR_WIDTH ((0x222e << 2) + 0xff000000)
+#define ENCT1_TST_VDCNT_STSET ((0x222f << 2) + 0xff000000)
+// Program video control signals from ENCP core to DVI/HDMI interface
+#define ENCP1_DVI_HSO_BEGIN ((0x2230 << 2) + 0xff000000)
+#define ENCP1_DVI_HSO_END ((0x2231 << 2) + 0xff000000)
+#define ENCP1_DVI_VSO_BLINE_EVN ((0x2232 << 2) + 0xff000000)
+#define ENCP1_DVI_VSO_BLINE_ODD ((0x2233 << 2) + 0xff000000)
+#define ENCP1_DVI_VSO_ELINE_EVN ((0x2234 << 2) + 0xff000000)
+#define ENCP1_DVI_VSO_ELINE_ODD ((0x2235 << 2) + 0xff000000)
+#define ENCP1_DVI_VSO_BEGIN_EVN ((0x2236 << 2) + 0xff000000)
+#define ENCP1_DVI_VSO_BEGIN_ODD ((0x2237 << 2) + 0xff000000)
+#define ENCP1_DVI_VSO_END_EVN ((0x2238 << 2) + 0xff000000)
+#define ENCP1_DVI_VSO_END_ODD ((0x2239 << 2) + 0xff000000)
+#define ENCP1_DE_H_BEGIN ((0x223a << 2) + 0xff000000)
+#define ENCP1_DE_H_END ((0x223b << 2) + 0xff000000)
+#define ENCP1_DE_V_BEGIN_EVEN ((0x223c << 2) + 0xff000000)
+#define ENCP1_DE_V_END_EVEN ((0x223d << 2) + 0xff000000)
+#define ENCP1_DE_V_BEGIN_ODD ((0x223e << 2) + 0xff000000)
+#define ENCP1_DE_V_END_ODD ((0x223f << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCI1_SYNC_LINE_LENGTH ((0x2240 << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCI1_SYNC_PIXEL_EN ((0x2241 << 2) + 0xff000000)
+// Bit 15 - ENCI1_sync_enable
+// Bit 14 - ENCP1_sync_enable
+// Bit 13 - ENCT1_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCI1_SYNC_TO_LINE_EN ((0x2242 << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCI1_SYNC_TO_PIXEL ((0x2243 << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCP1_SYNC_LINE_LENGTH ((0x2244 << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCP1_SYNC_PIXEL_EN ((0x2245 << 2) + 0xff000000)
+// Bit 15 - ENCI1_sync_enable
+// Bit 14 - ENCP1_sync_enable
+// Bit 13 - ENCT1_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCP1_SYNC_TO_LINE_EN ((0x2246 << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCP1_SYNC_TO_PIXEL ((0x2247 << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCT1_SYNC_LINE_LENGTH ((0x2248 << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCT1_SYNC_PIXEL_EN ((0x2249 << 2) + 0xff000000)
+// Bit 15 - ENCI1_sync_enable
+// Bit 14 - ENCP1_sync_enable
+// Bit 13 - ENCT1_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCT1_SYNC_TO_LINE_EN ((0x224a << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCT1_SYNC_TO_PIXEL ((0x224b << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCL1_SYNC_LINE_LENGTH ((0x224c << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCL1_SYNC_PIXEL_EN ((0x224d << 2) + 0xff000000)
+// Bit 15 - ENCI1_sync_enable
+// Bit 14 - ENCP1_sync_enable
+// Bit 13 - ENCT1_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCL1_SYNC_TO_LINE_EN ((0x224e << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCL1_SYNC_TO_PIXEL ((0x224f << 2) + 0xff000000)
+// bit 3 cfg_encp_lcd_scaler_bypass. 1=Do not scale LCD input data;
+// 0=Scale LCD input data to y [16*4,235*4], c [16*4,240*4].
+// bit 2 cfg_encp_vadj_scaler_bypass. 1=Do not scale data to enc480p_vadj;
+// 0=Scale enc480p_vadj input data to y [16*4,235*4], c [16*4,240*4].
+// bit 1 cfg_vfifo2vd_out_scaler_bypass. 1=Do not scale vfifo2vd's output vdata;
+// 0=Scale vfifo2vd's output vdata to y [16,235], c [16,240].
+// bit 0 cfg_vfifo_din_full_range. 1=Data from viu fifo is full range [0,1023];
+// 0=Data from viu fifo is y [16*4,235*4], c [16*4,240*4].
+#define ENCP1_VFIFO2VD_CTL2 ((0x2250 << 2) + 0xff000000)
+// bit 15:1 Reserved.
+// bit 0 cfg_int_dvi_sel_rgb. Applicable for using on-chip hdmi tx module only. This bit controls correct bit-mapping from
+// Venc to hdmi_tx depending on whether YCbCr or RGB mode.
+// 1=Map data bit from Venc to hdmi_tx for RGB mode;
+// 0=Default. Map data bit from Venc to hdmi_tx for YCbCr mode.
+#define VENC1_DVI_SETTING_MORE ((0x2251 << 2) + 0xff000000)
+#define VENC1_VDAC_DAC4_FILT_CTRL0 ((0x2254 << 2) + 0xff000000)
+#define VENC1_VDAC_DAC4_FILT_CTRL1 ((0x2255 << 2) + 0xff000000)
+#define VENC1_VDAC_DAC5_FILT_CTRL0 ((0x2256 << 2) + 0xff000000)
+#define VENC1_VDAC_DAC5_FILT_CTRL1 ((0x2257 << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC1_VDAC_DAC0_FILT_CTRL0 ((0x2258 << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC1_VDAC_DAC0_FILT_CTRL1 ((0x2259 << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC1_VDAC_DAC1_FILT_CTRL0 ((0x225a << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC1_VDAC_DAC1_FILT_CTRL1 ((0x225b << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC1_VDAC_DAC2_FILT_CTRL0 ((0x225c << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC1_VDAC_DAC2_FILT_CTRL1 ((0x225d << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC1_VDAC_DAC3_FILT_CTRL0 ((0x225e << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC1_VDAC_DAC3_FILT_CTRL1 ((0x225f << 2) + 0xff000000)
+//===========================================================================
+// ENCT registers
+#define ENCT1_VIDEO_EN ((0x2260 << 2) + 0xff000000)
+#define ENCT1_VIDEO_Y_SCL ((0x2261 << 2) + 0xff000000)
+#define ENCT1_VIDEO_PB_SCL ((0x2262 << 2) + 0xff000000)
+#define ENCT1_VIDEO_PR_SCL ((0x2263 << 2) + 0xff000000)
+#define ENCT1_VIDEO_Y_OFFST ((0x2264 << 2) + 0xff000000)
+#define ENCT1_VIDEO_PB_OFFST ((0x2265 << 2) + 0xff000000)
+#define ENCT1_VIDEO_PR_OFFST ((0x2266 << 2) + 0xff000000)
+//----- Video mode
+#define ENCT1_VIDEO_MODE ((0x2267 << 2) + 0xff000000)
+#define ENCT1_VIDEO_MODE_ADV ((0x2268 << 2) + 0xff000000)
+//--------------- Debug pins
+#define ENCT1_DBG_PX_RST ((0x2269 << 2) + 0xff000000)
+#define ENCT1_DBG_LN_RST ((0x226a << 2) + 0xff000000)
+#define ENCT1_DBG_PX_INT ((0x226b << 2) + 0xff000000)
+#define ENCT1_DBG_LN_INT ((0x226c << 2) + 0xff000000)
+//----------- Video Advanced setting
+#define ENCT1_VIDEO_YFP1_HTIME ((0x226d << 2) + 0xff000000)
+#define ENCT1_VIDEO_YFP2_HTIME ((0x226e << 2) + 0xff000000)
+#define ENCT1_VIDEO_YC_DLY ((0x226f << 2) + 0xff000000)
+#define ENCT1_VIDEO_MAX_PXCNT ((0x2270 << 2) + 0xff000000)
+#define ENCT1_VIDEO_HAVON_END ((0x2271 << 2) + 0xff000000)
+#define ENCT1_VIDEO_HAVON_BEGIN ((0x2272 << 2) + 0xff000000)
+#define ENCT1_VIDEO_VAVON_ELINE ((0x2273 << 2) + 0xff000000)
+#define ENCT1_VIDEO_VAVON_BLINE ((0x2274 << 2) + 0xff000000)
+#define ENCT1_VIDEO_HSO_BEGIN ((0x2275 << 2) + 0xff000000)
+#define ENCT1_VIDEO_HSO_END ((0x2276 << 2) + 0xff000000)
+#define ENCT1_VIDEO_VSO_BEGIN ((0x2277 << 2) + 0xff000000)
+#define ENCT1_VIDEO_VSO_END ((0x2278 << 2) + 0xff000000)
+#define ENCT1_VIDEO_VSO_BLINE ((0x2279 << 2) + 0xff000000)
+#define ENCT1_VIDEO_VSO_ELINE ((0x227a << 2) + 0xff000000)
+#define ENCT1_VIDEO_MAX_LNCNT ((0x227b << 2) + 0xff000000)
+#define ENCT1_VIDEO_BLANKY_VAL ((0x227c << 2) + 0xff000000)
+#define ENCT1_VIDEO_BLANKPB_VAL ((0x227d << 2) + 0xff000000)
+#define ENCT1_VIDEO_BLANKPR_VAL ((0x227e << 2) + 0xff000000)
+#define ENCT1_VIDEO_HOFFST ((0x227f << 2) + 0xff000000)
+#define ENCT1_VIDEO_VOFFST ((0x2280 << 2) + 0xff000000)
+#define ENCT1_VIDEO_RGB_CTRL ((0x2281 << 2) + 0xff000000)
+#define ENCT1_VIDEO_FILT_CTRL ((0x2282 << 2) + 0xff000000)
+#define ENCT1_VIDEO_OFLD_VPEQ_OFST ((0x2283 << 2) + 0xff000000)
+#define ENCT1_VIDEO_OFLD_VOAV_OFST ((0x2284 << 2) + 0xff000000)
+#define ENCT1_VIDEO_MATRIX_CB ((0x2285 << 2) + 0xff000000)
+#define ENCT1_VIDEO_MATRIX_CR ((0x2286 << 2) + 0xff000000)
+#define ENCT1_VIDEO_RGBIN_CTRL ((0x2287 << 2) + 0xff000000)
+#define ENCT1_MAX_LINE_SWITCH_POINT ((0x2288 << 2) + 0xff000000)
+#define ENCT1_DACSEL_0 ((0x2289 << 2) + 0xff000000)
+#define ENCT1_DACSEL_1 ((0x228a << 2) + 0xff000000)
+#define ENCT1_INBUF_CNTL0 ((0x228b << 2) + 0xff000000)
+#define ENCT1_INBUF_CNTL1 ((0x228c << 2) + 0xff000000)
+#define ENCT1_INBUF_CNT ((0x228d << 2) + 0xff000000)
+#define ENCT1_INBUF_HOLD_CNT ((0x228e << 2) + 0xff000000)
+#define ENCT1_INBUF_FIX_PIX_NUM ((0x228f << 2) + 0xff000000)
+//===========================================================================
+// For ENCL
+//===========================================================================
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 7 -- vfifo2vd_drop
+// bit 6:1 -- vfifo2vd_delay
+// bit 0 -- vfifo2vd_en
+#define ENCL1_VFIFO2VD_CTL ((0x2290 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCL1_VFIFO2VD_PIXEL_START ((0x2291 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCL1_VFIFO2VD_PIXEL_END ((0x2292 << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCL1_VFIFO2VD_LINE_TOP_START ((0x2293 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCL1_VFIFO2VD_LINE_TOP_END ((0x2294 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCL1_VFIFO2VD_LINE_BOT_START ((0x2295 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCL1_VFIFO2VD_LINE_BOT_END ((0x2296 << 2) + 0xff000000)
+#define ENCL1_VFIFO2VD_CTL2 ((0x2297 << 2) + 0xff000000)
+#define ENCL1_TST_EN ((0x2298 << 2) + 0xff000000)
+#define ENCL1_TST_MDSEL ((0x2299 << 2) + 0xff000000)
+#define ENCL1_TST_Y ((0x229a << 2) + 0xff000000)
+#define ENCL1_TST_CB ((0x229b << 2) + 0xff000000)
+#define ENCL1_TST_CR ((0x229c << 2) + 0xff000000)
+#define ENCL1_TST_CLRBAR_STRT ((0x229d << 2) + 0xff000000)
+#define ENCL1_TST_CLRBAR_WIDTH ((0x229e << 2) + 0xff000000)
+#define ENCL1_TST_VDCNT_STSET ((0x229f << 2) + 0xff000000)
+//===========================================================================
+// ENCL1 registers
+#define ENCL1_VIDEO_EN ((0x22a0 << 2) + 0xff000000)
+#define ENCL1_VIDEO_Y_SCL ((0x22a1 << 2) + 0xff000000)
+#define ENCL1_VIDEO_PB_SCL ((0x22a2 << 2) + 0xff000000)
+#define ENCL1_VIDEO_PR_SCL ((0x22a3 << 2) + 0xff000000)
+#define ENCL1_VIDEO_Y_OFFST ((0x22a4 << 2) + 0xff000000)
+#define ENCL1_VIDEO_PB_OFFST ((0x22a5 << 2) + 0xff000000)
+#define ENCL1_VIDEO_PR_OFFST ((0x22a6 << 2) + 0xff000000)
+//----- Video mode
+#define ENCL1_VIDEO_MODE ((0x22a7 << 2) + 0xff000000)
+#define ENCL1_VIDEO_MODE_ADV ((0x22a8 << 2) + 0xff000000)
+//--------------- Debug pins
+#define ENCL1_DBG_PX_RST ((0x22a9 << 2) + 0xff000000)
+#define ENCL1_DBG_LN_RST ((0x22aa << 2) + 0xff000000)
+#define ENCL1_DBG_PX_INT ((0x22ab << 2) + 0xff000000)
+#define ENCL1_DBG_LN_INT ((0x22ac << 2) + 0xff000000)
+//----------- Video Advanced setting
+#define ENCL1_VIDEO_YFP1_HTIME ((0x22ad << 2) + 0xff000000)
+#define ENCL1_VIDEO_YFP2_HTIME ((0x22ae << 2) + 0xff000000)
+#define ENCL1_VIDEO_YC_DLY ((0x22af << 2) + 0xff000000)
+#define ENCL1_VIDEO_MAX_PXCNT ((0x22b0 << 2) + 0xff000000)
+#define ENCL1_VIDEO_HAVON_END ((0x22b1 << 2) + 0xff000000)
+#define ENCL1_VIDEO_HAVON_BEGIN ((0x22b2 << 2) + 0xff000000)
+#define ENCL1_VIDEO_VAVON_ELINE ((0x22b3 << 2) + 0xff000000)
+#define ENCL1_VIDEO_VAVON_BLINE ((0x22b4 << 2) + 0xff000000)
+#define ENCL1_VIDEO_HSO_BEGIN ((0x22b5 << 2) + 0xff000000)
+#define ENCL1_VIDEO_HSO_END ((0x22b6 << 2) + 0xff000000)
+#define ENCL1_VIDEO_VSO_BEGIN ((0x22b7 << 2) + 0xff000000)
+#define ENCL1_VIDEO_VSO_END ((0x22b8 << 2) + 0xff000000)
+#define ENCL1_VIDEO_VSO_BLINE ((0x22b9 << 2) + 0xff000000)
+#define ENCL1_VIDEO_VSO_ELINE ((0x22ba << 2) + 0xff000000)
+#define ENCL1_VIDEO_MAX_LNCNT ((0x22bb << 2) + 0xff000000)
+#define ENCL1_VIDEO_BLANKY_VAL ((0x22bc << 2) + 0xff000000)
+#define ENCL1_VIDEO_BLANKPB_VAL ((0x22bd << 2) + 0xff000000)
+#define ENCL1_VIDEO_BLANKPR_VAL ((0x22be << 2) + 0xff000000)
+#define ENCL1_VIDEO_HOFFST ((0x22bf << 2) + 0xff000000)
+#define ENCL1_VIDEO_VOFFST ((0x22c0 << 2) + 0xff000000)
+#define ENCL1_VIDEO_RGB_CTRL ((0x22c1 << 2) + 0xff000000)
+#define ENCL1_VIDEO_FILT_CTRL ((0x22c2 << 2) + 0xff000000)
+#define ENCL1_VIDEO_OFLD_VPEQ_OFST ((0x22c3 << 2) + 0xff000000)
+#define ENCL1_VIDEO_OFLD_VOAV_OFST ((0x22c4 << 2) + 0xff000000)
+#define ENCL1_VIDEO_MATRIX_CB ((0x22c5 << 2) + 0xff000000)
+#define ENCL1_VIDEO_MATRIX_CR ((0x22c6 << 2) + 0xff000000)
+#define ENCL1_VIDEO_RGBIN_CTRL ((0x22c7 << 2) + 0xff000000)
+#define ENCL1_MAX_LINE_SWITCH_POINT ((0x22c8 << 2) + 0xff000000)
+#define ENCL1_DACSEL_0 ((0x22c9 << 2) + 0xff000000)
+#define ENCL1_DACSEL_1 ((0x22ca << 2) + 0xff000000)
+#define ENCT1_VIDEO_H_PRE_DE_END ((0x22cb << 2) + 0xff000000)
+#define ENCT1_VIDEO_H_PRE_DE_BEGIN ((0x22cc << 2) + 0xff000000)
+#define ENCT1_VIDEO_V_PRE_DE_ELINE ((0x22cd << 2) + 0xff000000)
+#define ENCT1_VIDEO_V_PRE_DE_BLINE ((0x22ce << 2) + 0xff000000)
+#define ENCL1_VIDEO_H_PRE_DE_END ((0x22cf << 2) + 0xff000000)
+#define ENCL1_VIDEO_H_PRE_DE_BEGIN ((0x22d0 << 2) + 0xff000000)
+#define ENCL1_VIDEO_V_PRE_DE_ELINE ((0x22d1 << 2) + 0xff000000)
+#define ENCL1_VIDEO_V_PRE_DE_BLINE ((0x22d2 << 2) + 0xff000000)
+#define ENCL1_INBUF_CNTL0 ((0x22d3 << 2) + 0xff000000)
+#define ENCL1_INBUF_CNTL1 ((0x22d4 << 2) + 0xff000000)
+#define ENCL1_INBUF_CNT ((0x22d5 << 2) + 0xff000000)
+#define ENCL1_INBUF_HOLD_CNT ((0x22d6 << 2) + 0xff000000)
+#define ENCL1_INBUF_FIX_PIX_NUM ((0x22d7 << 2) + 0xff000000)
+#define VPU1_VPU_PWM_V0 ((0x22e0 << 2) + 0xff000000)
+#define VPU1_VPU_PWM_V1 ((0x22e1 << 2) + 0xff000000)
+#define VPU1_VPU_PWM_V2 ((0x22e2 << 2) + 0xff000000)
+#define VPU1_VPU_PWM_V3 ((0x22e3 << 2) + 0xff000000)
+#define VPU1_VPU_PWM_H0 ((0x22e4 << 2) + 0xff000000)
+#define VPU1_VPU_PWM_H1 ((0x22e5 << 2) + 0xff000000)
+#define VPU1_VPU_PWM_H2 ((0x22e6 << 2) + 0xff000000)
+#define VPU1_VPU_PWM_H3 ((0x22e7 << 2) + 0xff000000)
+#define VPU1_VPU_3D_SYNC1 ((0x22e8 << 2) + 0xff000000)
+#define VPU1_VPU_3D_SYNC2 ((0x22e9 << 2) + 0xff000000)
+#define VPU1_VENC_DUMMY ((0x22df << 2) + 0xff000000)
+#define VPU1_VENC_ERROR ((0x22ea << 2) + 0xff000000)
+#define VPU1_VENCI_STAT ((0x22eb << 2) + 0xff000000)
+#define VPU1_VENCP_STAT ((0x22ec << 2) + 0xff000000)
+#define VPU1_VENCL_STAT ((0x22ed << 2) + 0xff000000)
+#define VPU1_VENC_DITH ((0x22ee << 2) + 0xff000000)
+#define VPU1_VENC_CTRL ((0x22ef << 2) + 0xff000000)
+#define VPU1_VENCL_DITH_CTRL ((0x22f0 << 2) + 0xff000000)
+#define VPU1_VENCL_DITH_LUT_1 ((0x22f1 << 2) + 0xff000000)
+#define VPU1_VENCL_DITH_LUT_2 ((0x22f2 << 2) + 0xff000000)
+#define VPU1_VENCL_DITH_LUT_3 ((0x22f3 << 2) + 0xff000000)
+#define VPU1_VENCL_DITH_LUT_4 ((0x22f4 << 2) + 0xff000000)
+#define VPU1_VENCL_DITH_LUT_5 ((0x22f5 << 2) + 0xff000000)
+#define VPU1_VENCL_DITH_LUT_6 ((0x22f6 << 2) + 0xff000000)
+#define VPU1_VENCL_DITH_LUT_7 ((0x22f7 << 2) + 0xff000000)
+#define VPU1_VENCL_DITH_LUT_8 ((0x22f8 << 2) + 0xff000000)
+#define VPU1_VENCL_DITH_LUT_9 ((0x22f9 << 2) + 0xff000000)
+#define VPU1_VENCL_DITH_LUT_10 ((0x22fa << 2) + 0xff000000)
+#define VPU1_VENCL_DITH_LUT_11 ((0x22fb << 2) + 0xff000000)
+#define VPU1_VENCL_DITH_LUT_12 ((0x22fc << 2) + 0xff000000)
+//
+// Closing file: venc2_1_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VENC2A_VCBUS_BASE = 0x23
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: venc_2_regs.h
+//
+//===========================================================================
+// Video Interface Registers 0xa00 - 0xbff
+//===========================================================================
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 0 -- vfifo2vd_en
+#define ENCP2_VFIFO2VD_CTL ((0x2358 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCP2_VFIFO2VD_PIXEL_START ((0x2359 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCP2_VFIFO2VD_PIXEL_END ((0x235a << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCP2_VFIFO2VD_LINE_TOP_START ((0x235b << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCP2_VFIFO2VD_LINE_TOP_END ((0x235c << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCP2_VFIFO2VD_LINE_BOT_START ((0x235d << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCP2_VFIFO2VD_LINE_BOT_END ((0x235e << 2) + 0xff000000)
+// Route the hsync and vsync signals round the chip. There are three
+// sources and users of these signals: VIU, internal video encoder, and
+// the pins on the chip. Some muxing is still being done in the VIU. It
+// was not moved to the venc module so that the same exact VIU code could
+// be used both in Twister and Twister2000.
+// Bit 2: venc_sync_source (1=>pins, 0=>viu)
+// Bit 1: viu_sync_source (1=>pins, 0=>venc)
+// Bit 0: vpins_sync_source (1=>venc, 0=>viu)
+#define VENC2_SYNC_ROUTE ((0x2360 << 2) + 0xff000000)
+ // encoder address space is assigned
+ // to the video encoder interface status
+ // register
+#define VENC2_VIDEO_EXSRC ((0x2361 << 2) + 0xff000000)
+#define VENC2_DVI_SETTING ((0x2362 << 2) + 0xff000000)
+#define VENC2_C656_CTRL ((0x2363 << 2) + 0xff000000)
+#define VENC2_UPSAMPLE_CTRL0 ((0x2364 << 2) + 0xff000000)
+#define VENC2_UPSAMPLE_CTRL1 ((0x2365 << 2) + 0xff000000)
+#define VENC2_UPSAMPLE_CTRL2 ((0x2366 << 2) + 0xff000000)
+// Invert control for tcon output
+// bit[15:14] -- vsync, hsync,
+// bit[13:0] -- oev3, oev2, cpv2, cph3, cph2, cph1, oeh, vcom, stv2, stv1, cpv1, oev1, sth1, sth2
+#define TCON2_INVERT_CTL ((0x2367 << 2) + 0xff000000)
+#define VENC2_VIDEO_PROG_MODE ((0x2368 << 2) + 0xff000000)
+//---- Venc pixel/line info
+#define VENC2_ENCI_LINE ((0x2369 << 2) + 0xff000000)
+#define VENC2_ENCI_PIXEL ((0x236a << 2) + 0xff000000)
+#define VENC2_ENCP_LINE ((0x236b << 2) + 0xff000000)
+#define VENC2_ENCP_PIXEL ((0x236c << 2) + 0xff000000)
+//---- Status
+#define VENC2_STATA ((0x236d << 2) + 0xff000000)
+//---- Interrupt setting
+#define VENC2_INTCTRL ((0x236e << 2) + 0xff000000)
+#define VENC2_INTFLAG ((0x236f << 2) + 0xff000000)
+//--------- Video test configuration
+#define VENC2_VIDEO_TST_EN ((0x2370 << 2) + 0xff000000)
+#define VENC2_VIDEO_TST_MDSEL ((0x2371 << 2) + 0xff000000)
+#define VENC2_VIDEO_TST_Y ((0x2372 << 2) + 0xff000000)
+#define VENC2_VIDEO_TST_CB ((0x2373 << 2) + 0xff000000)
+#define VENC2_VIDEO_TST_CR ((0x2374 << 2) + 0xff000000)
+#define VENC2_VIDEO_TST_CLRBAR_STRT ((0x2375 << 2) + 0xff000000)
+#define VENC2_VIDEO_TST_CLRBAR_WIDTH ((0x2376 << 2) + 0xff000000)
+#define VENC2_VIDEO_TST_VDCNT_STSET ((0x2377 << 2) + 0xff000000)
+//----- Video dac setting
+#define VENC2_VDAC_DACSEL0 ((0x2378 << 2) + 0xff000000)
+#define VENC2_VDAC_DACSEL1 ((0x2379 << 2) + 0xff000000)
+#define VENC2_VDAC_DACSEL2 ((0x237a << 2) + 0xff000000)
+#define VENC2_VDAC_DACSEL3 ((0x237b << 2) + 0xff000000)
+#define VENC2_VDAC_DACSEL4 ((0x237c << 2) + 0xff000000)
+#define VENC2_VDAC_DACSEL5 ((0x237d << 2) + 0xff000000)
+#define VENC2_VDAC_SETTING ((0x237e << 2) + 0xff000000)
+#define VENC2_VDAC_TST_VAL ((0x237f << 2) + 0xff000000)
+#define VENC2_VDAC_DAC0_GAINCTRL ((0x23f0 << 2) + 0xff000000)
+#define VENC2_VDAC_DAC0_OFFSET ((0x23f1 << 2) + 0xff000000)
+#define VENC2_VDAC_DAC1_GAINCTRL ((0x23f2 << 2) + 0xff000000)
+#define VENC2_VDAC_DAC1_OFFSET ((0x23f3 << 2) + 0xff000000)
+#define VENC2_VDAC_DAC2_GAINCTRL ((0x23f4 << 2) + 0xff000000)
+#define VENC2_VDAC_DAC2_OFFSET ((0x23f5 << 2) + 0xff000000)
+#define VENC2_VDAC_DAC3_GAINCTRL ((0x23f6 << 2) + 0xff000000)
+#define VENC2_VDAC_DAC3_OFFSET ((0x23f7 << 2) + 0xff000000)
+#define VENC2_VDAC_DAC4_GAINCTRL ((0x23f8 << 2) + 0xff000000)
+#define VENC2_VDAC_DAC4_OFFSET ((0x23f9 << 2) + 0xff000000)
+#define VENC2_VDAC_DAC5_GAINCTRL ((0x23fa << 2) + 0xff000000)
+#define VENC2_VDAC_DAC5_OFFSET ((0x23fb << 2) + 0xff000000)
+#define VENC2_VDAC_FIFO_CTRL ((0x23fc << 2) + 0xff000000)
+#define ENCL2_TCON_INVERT_CTL ((0x23fd << 2) + 0xff000000)
+//
+// Closing file: venc_2_regs.h
+//
+//
+// Reading file: enc480p_2_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+// Video Encoder 480p Registers 0xb80 - 0xbef
+//===========================================================================
+//-------- Video basic setting
+#define ENCP2_VIDEO_EN ((0x2380 << 2) + 0xff000000)
+#define ENCP2_VIDEO_SYNC_MODE ((0x2381 << 2) + 0xff000000)
+#define ENCP2_MACV_EN ((0x2382 << 2) + 0xff000000)
+#define ENCP2_VIDEO_Y_SCL ((0x2383 << 2) + 0xff000000)
+#define ENCP2_VIDEO_PB_SCL ((0x2384 << 2) + 0xff000000)
+#define ENCP2_VIDEO_PR_SCL ((0x2385 << 2) + 0xff000000)
+#define ENCP2_VIDEO_SYNC_SCL ((0x2386 << 2) + 0xff000000)
+#define ENCP2_VIDEO_MACV_SCL ((0x2387 << 2) + 0xff000000)
+#define ENCP2_VIDEO_Y_OFFST ((0x2388 << 2) + 0xff000000)
+#define ENCP2_VIDEO_PB_OFFST ((0x2389 << 2) + 0xff000000)
+#define ENCP2_VIDEO_PR_OFFST ((0x238a << 2) + 0xff000000)
+#define ENCP2_VIDEO_SYNC_OFFST ((0x238b << 2) + 0xff000000)
+#define ENCP2_VIDEO_MACV_OFFST ((0x238c << 2) + 0xff000000)
+//----- Video mode
+#define ENCP2_VIDEO_MODE ((0x238d << 2) + 0xff000000)
+#define ENCP2_VIDEO_MODE_ADV ((0x238e << 2) + 0xff000000)
+//--------------- Debug pins
+#define ENCP2_DBG_PX_RST ((0x2390 << 2) + 0xff000000)
+#define ENCP2_DBG_LN_RST ((0x2391 << 2) + 0xff000000)
+#define ENCP2_DBG_PX_INT ((0x2392 << 2) + 0xff000000)
+#define ENCP2_DBG_LN_INT ((0x2393 << 2) + 0xff000000)
+//----------- Video Advanced setting
+#define ENCP2_VIDEO_YFP1_HTIME ((0x2394 << 2) + 0xff000000)
+#define ENCP2_VIDEO_YFP2_HTIME ((0x2395 << 2) + 0xff000000)
+#define ENCP2_VIDEO_YC_DLY ((0x2396 << 2) + 0xff000000)
+#define ENCP2_VIDEO_MAX_PXCNT ((0x2397 << 2) + 0xff000000)
+#define ENCP2_VIDEO_HSPULS_BEGIN ((0x2398 << 2) + 0xff000000)
+#define ENCP2_VIDEO_HSPULS_END ((0x2399 << 2) + 0xff000000)
+#define ENCP2_VIDEO_HSPULS_SWITCH ((0x239a << 2) + 0xff000000)
+#define ENCP2_VIDEO_VSPULS_BEGIN ((0x239b << 2) + 0xff000000)
+#define ENCP2_VIDEO_VSPULS_END ((0x239c << 2) + 0xff000000)
+#define ENCP2_VIDEO_VSPULS_BLINE ((0x239d << 2) + 0xff000000)
+#define ENCP2_VIDEO_VSPULS_ELINE ((0x239e << 2) + 0xff000000)
+#define ENCP2_VIDEO_EQPULS_BEGIN ((0x239f << 2) + 0xff000000)
+#define ENCP2_VIDEO_EQPULS_END ((0x23a0 << 2) + 0xff000000)
+#define ENCP2_VIDEO_EQPULS_BLINE ((0x23a1 << 2) + 0xff000000)
+#define ENCP2_VIDEO_EQPULS_ELINE ((0x23a2 << 2) + 0xff000000)
+#define ENCP2_VIDEO_HAVON_END ((0x23a3 << 2) + 0xff000000)
+#define ENCP2_VIDEO_HAVON_BEGIN ((0x23a4 << 2) + 0xff000000)
+#define ENCP2_VIDEO_VAVON_ELINE ((0x23af << 2) + 0xff000000)
+#define ENCP2_VIDEO_VAVON_BLINE ((0x23a6 << 2) + 0xff000000)
+#define ENCP2_VIDEO_HSO_BEGIN ((0x23a7 << 2) + 0xff000000)
+#define ENCP2_VIDEO_HSO_END ((0x23a8 << 2) + 0xff000000)
+#define ENCP2_VIDEO_VSO_BEGIN ((0x23a9 << 2) + 0xff000000)
+#define ENCP2_VIDEO_VSO_END ((0x23aa << 2) + 0xff000000)
+#define ENCP2_VIDEO_VSO_BLINE ((0x23ab << 2) + 0xff000000)
+#define ENCP2_VIDEO_VSO_ELINE ((0x23ac << 2) + 0xff000000)
+#define ENCP2_VIDEO_SYNC_WAVE_CURVE ((0x23ad << 2) + 0xff000000)
+#define ENCP2_VIDEO_MAX_LNCNT ((0x23ae << 2) + 0xff000000)
+#define ENCP2_VIDEO_SY_VAL ((0x23b0 << 2) + 0xff000000)
+#define ENCP2_VIDEO_SY2_VAL ((0x23b1 << 2) + 0xff000000)
+#define ENCP2_VIDEO_BLANKY_VAL ((0x23b2 << 2) + 0xff000000)
+#define ENCP2_VIDEO_BLANKPB_VAL ((0x23b3 << 2) + 0xff000000)
+#define ENCP2_VIDEO_BLANKPR_VAL ((0x23b4 << 2) + 0xff000000)
+#define ENCP2_VIDEO_HOFFST ((0x23b5 << 2) + 0xff000000)
+#define ENCP2_VIDEO_VOFFST ((0x23b6 << 2) + 0xff000000)
+#define ENCP2_VIDEO_RGB_CTRL ((0x23b7 << 2) + 0xff000000)
+#define ENCP2_VIDEO_FILT_CTRL ((0x23b8 << 2) + 0xff000000)
+#define ENCP2_VIDEO_OFLD_VPEQ_OFST ((0x23b9 << 2) + 0xff000000)
+#define ENCP2_VIDEO_OFLD_VOAV_OFST ((0x23ba << 2) + 0xff000000)
+#define ENCP2_VIDEO_MATRIX_CB ((0x23bb << 2) + 0xff000000)
+#define ENCP2_VIDEO_MATRIX_CR ((0x23bc << 2) + 0xff000000)
+#define ENCP2_VIDEO_RGBIN_CTRL ((0x23bd << 2) + 0xff000000)
+//------------------Macrovision advanced setting
+#define ENCP2_MACV_BLANKY_VAL ((0x23c0 << 2) + 0xff000000)
+#define ENCP2_MACV_MAXY_VAL ((0x23c1 << 2) + 0xff000000)
+#define ENCP2_MACV_1ST_PSSYNC_STRT ((0x23c2 << 2) + 0xff000000)
+#define ENCP2_MACV_PSSYNC_STRT ((0x23c3 << 2) + 0xff000000)
+#define ENCP2_MACV_AGC_STRT ((0x23c4 << 2) + 0xff000000)
+#define ENCP2_MACV_AGC_END ((0x23c5 << 2) + 0xff000000)
+#define ENCP2_MACV_WAVE_END ((0x23c6 << 2) + 0xff000000)
+#define ENCP2_MACV_STRTLINE ((0x23c7 << 2) + 0xff000000)
+#define ENCP2_MACV_ENDLINE ((0x23c8 << 2) + 0xff000000)
+#define ENCP2_MACV_TS_CNT_MAX_L ((0x23c9 << 2) + 0xff000000)
+#define ENCP2_MACV_TS_CNT_MAX_H ((0x23ca << 2) + 0xff000000)
+#define ENCP2_MACV_TIME_DOWN ((0x23cb << 2) + 0xff000000)
+#define ENCP2_MACV_TIME_LO ((0x23cc << 2) + 0xff000000)
+#define ENCP2_MACV_TIME_UP ((0x23cd << 2) + 0xff000000)
+#define ENCP2_MACV_TIME_RST ((0x23ce << 2) + 0xff000000)
+//---------------- VBI control -------------------
+#define ENCP2_VBI_CTRL ((0x23d0 << 2) + 0xff000000)
+#define ENCP2_VBI_SETTING ((0x23d1 << 2) + 0xff000000)
+#define ENCP2_VBI_BEGIN ((0x23d2 << 2) + 0xff000000)
+#define ENCP2_VBI_WIDTH ((0x23d3 << 2) + 0xff000000)
+#define ENCP2_VBI_HVAL ((0x23d4 << 2) + 0xff000000)
+#define ENCP2_VBI_DATA0 ((0x23d5 << 2) + 0xff000000)
+#define ENCP2_VBI_DATA1 ((0x23d6 << 2) + 0xff000000)
+//----------------C656 OUT Control------------- Grant
+#define C656_HS_ST_2 ((0x23e0 << 2) + 0xff000000)
+#define C656_HS_ED_2 ((0x23e1 << 2) + 0xff000000)
+#define C656_VS_LNST_E_2 ((0x23e2 << 2) + 0xff000000)
+#define C656_VS_LNST_O_2 ((0x23e3 << 2) + 0xff000000)
+#define C656_VS_LNED_E_2 ((0x23e4 << 2) + 0xff000000)
+#define C656_VS_LNED_O_2 ((0x23e5 << 2) + 0xff000000)
+#define C656_FS_LNST_2 ((0x23e6 << 2) + 0xff000000)
+#define C656_FS_LNED_2 ((0x23e7 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: enc480p_2_regs.h
+//
+//
+// Reading file: enci_2_regs.h
+//
+//===========================================================================
+// Video Interface Registers 0xb00 - 0xb57
+//===========================================================================
+#define ENCI2_VIDEO_MODE ((0x2300 << 2) + 0xff000000)
+#define ENCI2_VIDEO_MODE_ADV ((0x2301 << 2) + 0xff000000)
+#define ENCI2_VIDEO_FSC_ADJ ((0x2302 << 2) + 0xff000000)
+#define ENCI2_VIDEO_BRIGHT ((0x2303 << 2) + 0xff000000)
+#define ENCI2_VIDEO_CONT ((0x2304 << 2) + 0xff000000)
+#define ENCI2_VIDEO_SAT ((0x2305 << 2) + 0xff000000)
+#define ENCI2_VIDEO_HUE ((0x2306 << 2) + 0xff000000)
+#define ENCI2_VIDEO_SCH ((0x2307 << 2) + 0xff000000)
+#define ENCI2_SYNC_MODE ((0x2308 << 2) + 0xff000000)
+#define ENCI2_SYNC_CTRL ((0x2309 << 2) + 0xff000000)
+#define ENCI2_SYNC_HSO_BEGIN ((0x230a << 2) + 0xff000000)
+#define ENCI2_SYNC_HSO_END ((0x230b << 2) + 0xff000000)
+#define ENCI2_SYNC_VSO_EVN ((0x230c << 2) + 0xff000000)
+#define ENCI2_SYNC_VSO_ODD ((0x230d << 2) + 0xff000000)
+#define ENCI2_SYNC_VSO_EVNLN ((0x230e << 2) + 0xff000000)
+#define ENCI2_SYNC_VSO_ODDLN ((0x230f << 2) + 0xff000000)
+#define ENCI2_SYNC_HOFFST ((0x2310 << 2) + 0xff000000)
+#define ENCI2_SYNC_VOFFST ((0x2311 << 2) + 0xff000000)
+#define ENCI2_SYNC_ADJ ((0x2312 << 2) + 0xff000000)
+#define ENCI2_RGB_SETTING ((0x2313 << 2) + 0xff000000)
+//`define ENCI2_CMPN_MATRIX_CB 8'h14
+//`define ENCI2_CMPN_MATRIX_CR 8'h15
+#define ENCI2_DE_H_BEGIN ((0x2316 << 2) + 0xff000000)
+#define ENCI2_DE_H_END ((0x2317 << 2) + 0xff000000)
+#define ENCI2_DE_V_BEGIN_EVEN ((0x2318 << 2) + 0xff000000)
+#define ENCI2_DE_V_END_EVEN ((0x2319 << 2) + 0xff000000)
+#define ENCI2_DE_V_BEGIN_ODD ((0x231a << 2) + 0xff000000)
+#define ENCI2_DE_V_END_ODD ((0x231b << 2) + 0xff000000)
+#define ENCI2_VBI_SETTING ((0x2320 << 2) + 0xff000000)
+#define ENCI2_VBI_CCDT_EVN ((0x2321 << 2) + 0xff000000)
+#define ENCI2_VBI_CCDT_ODD ((0x2322 << 2) + 0xff000000)
+#define ENCI2_VBI_CC525_LN ((0x2323 << 2) + 0xff000000)
+#define ENCI2_VBI_CC625_LN ((0x2324 << 2) + 0xff000000)
+#define ENCI2_VBI_WSSDT ((0x2325 << 2) + 0xff000000)
+#define ENCI2_VBI_WSS_LN ((0x2326 << 2) + 0xff000000)
+#define ENCI2_VBI_CGMSDT_L ((0x2327 << 2) + 0xff000000)
+#define ENCI2_VBI_CGMSDT_H ((0x2328 << 2) + 0xff000000)
+#define ENCI2_VBI_CGMS_LN ((0x2329 << 2) + 0xff000000)
+#define ENCI2_VBI_TTX_HTIME ((0x232a << 2) + 0xff000000)
+#define ENCI2_VBI_TTX_LN ((0x232b << 2) + 0xff000000)
+#define ENCI2_VBI_TTXDT0 ((0x232c << 2) + 0xff000000)
+#define ENCI2_VBI_TTXDT1 ((0x232d << 2) + 0xff000000)
+#define ENCI2_VBI_TTXDT2 ((0x232e << 2) + 0xff000000)
+#define ENCI2_VBI_TTXDT3 ((0x232f << 2) + 0xff000000)
+#define ENCI2_MACV_N0 ((0x2330 << 2) + 0xff000000)
+#define ENCI2_MACV_N1 ((0x2331 << 2) + 0xff000000)
+#define ENCI2_MACV_N2 ((0x2332 << 2) + 0xff000000)
+#define ENCI2_MACV_N3 ((0x2333 << 2) + 0xff000000)
+#define ENCI2_MACV_N4 ((0x2334 << 2) + 0xff000000)
+#define ENCI2_MACV_N5 ((0x2335 << 2) + 0xff000000)
+#define ENCI2_MACV_N6 ((0x2336 << 2) + 0xff000000)
+#define ENCI2_MACV_N7 ((0x2337 << 2) + 0xff000000)
+#define ENCI2_MACV_N8 ((0x2338 << 2) + 0xff000000)
+#define ENCI2_MACV_N9 ((0x2339 << 2) + 0xff000000)
+#define ENCI2_MACV_N10 ((0x233a << 2) + 0xff000000)
+#define ENCI2_MACV_N11 ((0x233b << 2) + 0xff000000)
+#define ENCI2_MACV_N12 ((0x233c << 2) + 0xff000000)
+#define ENCI2_MACV_N13 ((0x233d << 2) + 0xff000000)
+#define ENCI2_MACV_N14 ((0x233e << 2) + 0xff000000)
+#define ENCI2_MACV_N15 ((0x233f << 2) + 0xff000000)
+#define ENCI2_MACV_N16 ((0x2340 << 2) + 0xff000000)
+#define ENCI2_MACV_N17 ((0x2341 << 2) + 0xff000000)
+#define ENCI2_MACV_N18 ((0x2342 << 2) + 0xff000000)
+#define ENCI2_MACV_N19 ((0x2343 << 2) + 0xff000000)
+#define ENCI2_MACV_N20 ((0x2344 << 2) + 0xff000000)
+#define ENCI2_MACV_N21 ((0x2345 << 2) + 0xff000000)
+#define ENCI2_MACV_N22 ((0x2346 << 2) + 0xff000000)
+//`define ENCI2_MACV_P_AGC 8'h47
+#define ENCI2_DBG_PX_RST ((0x2348 << 2) + 0xff000000)
+#define ENCI2_DBG_FLDLN_RST ((0x2349 << 2) + 0xff000000)
+#define ENCI2_DBG_PX_INT ((0x234a << 2) + 0xff000000)
+#define ENCI2_DBG_FLDLN_INT ((0x234b << 2) + 0xff000000)
+#define ENCI2_DBG_MAXPX ((0x234c << 2) + 0xff000000)
+#define ENCI2_DBG_MAXLN ((0x234d << 2) + 0xff000000)
+#define ENCI2_MACV_MAX_AMP ((0x2350 << 2) + 0xff000000)
+#define ENCI2_MACV_PULSE_LO ((0x2351 << 2) + 0xff000000)
+#define ENCI2_MACV_PULSE_HI ((0x2352 << 2) + 0xff000000)
+#define ENCI2_MACV_BKP_MAX ((0x2353 << 2) + 0xff000000)
+#define ENCI2_CFILT_CTRL ((0x2354 << 2) + 0xff000000)
+#define ENCI2_CFILT7 ((0x2355 << 2) + 0xff000000)
+#define ENCI2_YC_DELAY ((0x2356 << 2) + 0xff000000)
+#define ENCI2_VIDEO_EN ((0x2357 << 2) + 0xff000000)
+//
+// Closing file: enci_2_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VENC2B_VCBUS_BASE = 0x24
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: venc2_2_regs.h
+//
+//===========================================================================
+// Venc Registers (Cont.) 0xc00 - 0xcff (VENC registers 0xc00 - 0xcef)
+//===========================================================================
+// Program video control signals from ENCI core to DVI/HDMI interface
+#define ENCI2_DVI_HSO_BEGIN ((0x2400 << 2) + 0xff000000)
+#define ENCI2_DVI_HSO_END ((0x2401 << 2) + 0xff000000)
+#define ENCI2_DVI_VSO_BLINE_EVN ((0x2402 << 2) + 0xff000000)
+#define ENCI2_DVI_VSO_BLINE_ODD ((0x2403 << 2) + 0xff000000)
+#define ENCI2_DVI_VSO_ELINE_EVN ((0x2404 << 2) + 0xff000000)
+#define ENCI2_DVI_VSO_ELINE_ODD ((0x2405 << 2) + 0xff000000)
+#define ENCI2_DVI_VSO_BEGIN_EVN ((0x2406 << 2) + 0xff000000)
+#define ENCI2_DVI_VSO_BEGIN_ODD ((0x2407 << 2) + 0xff000000)
+#define ENCI2_DVI_VSO_END_EVN ((0x2408 << 2) + 0xff000000)
+#define ENCI2_DVI_VSO_END_ODD ((0x2409 << 2) + 0xff000000)
+// Define cmpt and cvbs cb/cr delay after ENCI chroma filters
+// Bit 15:12 RW, enci_cb_cvbs_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+// Bit 11: 8 RW, enci_cr_cvbs_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+// Bit 7: 4 RW, enci_cb_cmpt_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+// Bit 3: 0 RW, enci_cr_cmpt_dly_sel. 0=no delay; 1~6=delay by 1~6 clk; 7~15 reserved.
+#define ENCI2_CFILT_CTRL2 ((0x240a << 2) + 0xff000000)
+#define ENCI2_DACSEL_0 ((0x240b << 2) + 0xff000000)
+#define ENCI2_DACSEL_1 ((0x240c << 2) + 0xff000000)
+#define ENCP2_DACSEL_0 ((0x240d << 2) + 0xff000000)
+#define ENCP2_DACSEL_1 ((0x240e << 2) + 0xff000000)
+#define ENCP2_MAX_LINE_SWITCH_POINT ((0x240f << 2) + 0xff000000)
+#define ENCI2_TST_EN ((0x2410 << 2) + 0xff000000)
+#define ENCI2_TST_MDSEL ((0x2411 << 2) + 0xff000000)
+#define ENCI2_TST_Y ((0x2412 << 2) + 0xff000000)
+#define ENCI2_TST_CB ((0x2413 << 2) + 0xff000000)
+#define ENCI2_TST_CR ((0x2414 << 2) + 0xff000000)
+#define ENCI2_TST_CLRBAR_STRT ((0x2415 << 2) + 0xff000000)
+#define ENCI2_TST_CLRBAR_WIDTH ((0x2416 << 2) + 0xff000000)
+#define ENCI2_TST_VDCNT_STSET ((0x2417 << 2) + 0xff000000)
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 7 -- vfifo2vd_drop
+// bit 6:1 -- vfifo2vd_delay
+// bit 0 -- vfifo2vd_en
+#define ENCI2_VFIFO2VD_CTL ((0x2418 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCI2_VFIFO2VD_PIXEL_START ((0x2419 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCI2_VFIFO2VD_PIXEL_END ((0x241a << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCI2_VFIFO2VD_LINE_TOP_START ((0x241b << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCI2_VFIFO2VD_LINE_TOP_END ((0x241c << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCI2_VFIFO2VD_LINE_BOT_START ((0x241d << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCI2_VFIFO2VD_LINE_BOT_END ((0x241e << 2) + 0xff000000)
+#define ENCI2_VFIFO2VD_CTL2 ((0x241f << 2) + 0xff000000)
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 7 -- vfifo2vd_drop
+// bit 6:1 -- vfifo2vd_delay
+// bit 0 -- vfifo2vd_en
+#define ENCT2_VFIFO2VD_CTL ((0x2420 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCT2_VFIFO2VD_PIXEL_START ((0x2421 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCT2_VFIFO2VD_PIXEL_END ((0x2422 << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCT2_VFIFO2VD_LINE_TOP_START ((0x2423 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCT2_VFIFO2VD_LINE_TOP_END ((0x2424 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCT2_VFIFO2VD_LINE_BOT_START ((0x2425 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCT2_VFIFO2VD_LINE_BOT_END ((0x2426 << 2) + 0xff000000)
+#define ENCT2_VFIFO2VD_CTL2 ((0x2427 << 2) + 0xff000000)
+#define ENCT2_TST_EN ((0x2428 << 2) + 0xff000000)
+#define ENCT2_TST_MDSEL ((0x2429 << 2) + 0xff000000)
+#define ENCT2_TST_Y ((0x242a << 2) + 0xff000000)
+#define ENCT2_TST_CB ((0x242b << 2) + 0xff000000)
+#define ENCT2_TST_CR ((0x242c << 2) + 0xff000000)
+#define ENCT2_TST_CLRBAR_STRT ((0x242d << 2) + 0xff000000)
+#define ENCT2_TST_CLRBAR_WIDTH ((0x242e << 2) + 0xff000000)
+#define ENCT2_TST_VDCNT_STSET ((0x242f << 2) + 0xff000000)
+// Program video control signals from ENCP core to DVI/HDMI interface
+#define ENCP2_DVI_HSO_BEGIN ((0x2430 << 2) + 0xff000000)
+#define ENCP2_DVI_HSO_END ((0x2431 << 2) + 0xff000000)
+#define ENCP2_DVI_VSO_BLINE_EVN ((0x2432 << 2) + 0xff000000)
+#define ENCP2_DVI_VSO_BLINE_ODD ((0x2433 << 2) + 0xff000000)
+#define ENCP2_DVI_VSO_ELINE_EVN ((0x2434 << 2) + 0xff000000)
+#define ENCP2_DVI_VSO_ELINE_ODD ((0x2435 << 2) + 0xff000000)
+#define ENCP2_DVI_VSO_BEGIN_EVN ((0x2436 << 2) + 0xff000000)
+#define ENCP2_DVI_VSO_BEGIN_ODD ((0x2437 << 2) + 0xff000000)
+#define ENCP2_DVI_VSO_END_EVN ((0x2438 << 2) + 0xff000000)
+#define ENCP2_DVI_VSO_END_ODD ((0x2439 << 2) + 0xff000000)
+#define ENCP2_DE_H_BEGIN ((0x243a << 2) + 0xff000000)
+#define ENCP2_DE_H_END ((0x243b << 2) + 0xff000000)
+#define ENCP2_DE_V_BEGIN_EVEN ((0x243c << 2) + 0xff000000)
+#define ENCP2_DE_V_END_EVEN ((0x243d << 2) + 0xff000000)
+#define ENCP2_DE_V_BEGIN_ODD ((0x243e << 2) + 0xff000000)
+#define ENCP2_DE_V_END_ODD ((0x243f << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCI2_SYNC_LINE_LENGTH ((0x2440 << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCI2_SYNC_PIXEL_EN ((0x2441 << 2) + 0xff000000)
+// Bit 15 - ENCI2_sync_enable
+// Bit 14 - ENCP2_sync_enable
+// Bit 13 - ENCT2_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCI2_SYNC_TO_LINE_EN ((0x2442 << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCI2_SYNC_TO_PIXEL ((0x2443 << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCP2_SYNC_LINE_LENGTH ((0x2444 << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCP2_SYNC_PIXEL_EN ((0x2445 << 2) + 0xff000000)
+// Bit 15 - ENCI2_sync_enable
+// Bit 14 - ENCP2_sync_enable
+// Bit 13 - ENCT2_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCP2_SYNC_TO_LINE_EN ((0x2446 << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCP2_SYNC_TO_PIXEL ((0x2447 << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCT2_SYNC_LINE_LENGTH ((0x2448 << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCT2_SYNC_PIXEL_EN ((0x2449 << 2) + 0xff000000)
+// Bit 15 - ENCI2_sync_enable
+// Bit 14 - ENCP2_sync_enable
+// Bit 13 - ENCT2_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCT2_SYNC_TO_LINE_EN ((0x244a << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCT2_SYNC_TO_PIXEL ((0x244b << 2) + 0xff000000)
+// Bit 15:11 - sync length
+// Bit 10:0 - sync start line
+#define ENCL2_SYNC_LINE_LENGTH ((0x244c << 2) + 0xff000000)
+// Bit 15 - sync_pulse_enable
+// Bit 12:0 - sync start pixel
+#define ENCL2_SYNC_PIXEL_EN ((0x244d << 2) + 0xff000000)
+// Bit 15 - ENCI2_sync_enable
+// Bit 14 - ENCP2_sync_enable
+// Bit 13 - ENCT2_sync_enable
+// Bit 12 - short_fussy_sync
+// Bit 11 - fussy_sync_enable
+// Bit 10:0 - sync target line
+#define ENCL2_SYNC_TO_LINE_EN ((0x244e << 2) + 0xff000000)
+// Bit 12:0 - sync target pixel
+#define ENCL2_SYNC_TO_PIXEL ((0x244f << 2) + 0xff000000)
+// bit 3 cfg_encp_lcd_scaler_bypass. 1=Do not scale LCD input data;
+// 0=Scale LCD input data to y [16*4,235*4], c [16*4,240*4].
+// bit 2 cfg_encp_vadj_scaler_bypass. 1=Do not scale data to enc480p_vadj;
+// 0=Scale enc480p_vadj input data to y [16*4,235*4], c [16*4,240*4].
+// bit 1 cfg_vfifo2vd_out_scaler_bypass. 1=Do not scale vfifo2vd's output vdata;
+// 0=Scale vfifo2vd's output vdata to y [16,235], c [16,240].
+// bit 0 cfg_vfifo_din_full_range. 1=Data from viu fifo is full range [0,1023];
+// 0=Data from viu fifo is y [16*4,235*4], c [16*4,240*4].
+#define ENCP2_VFIFO2VD_CTL2 ((0x2450 << 2) + 0xff000000)
+// bit 15:1 Reserved.
+// bit 0 cfg_int_dvi_sel_rgb. Applicable for using on-chip hdmi tx module only. This bit controls correct bit-mapping from
+// Venc to hdmi_tx depending on whether YCbCr or RGB mode.
+// 1=Map data bit from Venc to hdmi_tx for RGB mode;
+// 0=Default. Map data bit from Venc to hdmi_tx for YCbCr mode.
+#define VENC2_DVI_SETTING_MORE ((0x2451 << 2) + 0xff000000)
+#define VENC2_VDAC_DAC4_FILT_CTRL0 ((0x2454 << 2) + 0xff000000)
+#define VENC2_VDAC_DAC4_FILT_CTRL1 ((0x2455 << 2) + 0xff000000)
+#define VENC2_VDAC_DAC5_FILT_CTRL0 ((0x2456 << 2) + 0xff000000)
+#define VENC2_VDAC_DAC5_FILT_CTRL1 ((0x2457 << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC2_VDAC_DAC0_FILT_CTRL0 ((0x2458 << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC2_VDAC_DAC0_FILT_CTRL1 ((0x2459 << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC2_VDAC_DAC1_FILT_CTRL0 ((0x245a << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC2_VDAC_DAC1_FILT_CTRL1 ((0x245b << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC2_VDAC_DAC2_FILT_CTRL0 ((0x245c << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC2_VDAC_DAC2_FILT_CTRL1 ((0x245d << 2) + 0xff000000)
+//Bit 0 filter_en
+#define VENC2_VDAC_DAC3_FILT_CTRL0 ((0x245e << 2) + 0xff000000)
+//dout = ((din + din_d2) * coef1 + (din_d1 * coef0) + 32) >> 6
+//Bit 15:8, coef1,
+//Bit 7:0, coef0,
+#define VENC2_VDAC_DAC3_FILT_CTRL1 ((0x245f << 2) + 0xff000000)
+//===========================================================================
+// ENCT registers
+#define ENCT2_VIDEO_EN ((0x2460 << 2) + 0xff000000)
+#define ENCT2_VIDEO_Y_SCL ((0x2461 << 2) + 0xff000000)
+#define ENCT2_VIDEO_PB_SCL ((0x2462 << 2) + 0xff000000)
+#define ENCT2_VIDEO_PR_SCL ((0x2463 << 2) + 0xff000000)
+#define ENCT2_VIDEO_Y_OFFST ((0x2464 << 2) + 0xff000000)
+#define ENCT2_VIDEO_PB_OFFST ((0x2465 << 2) + 0xff000000)
+#define ENCT2_VIDEO_PR_OFFST ((0x2466 << 2) + 0xff000000)
+//----- Video mode
+#define ENCT2_VIDEO_MODE ((0x2467 << 2) + 0xff000000)
+#define ENCT2_VIDEO_MODE_ADV ((0x2468 << 2) + 0xff000000)
+//--------------- Debug pins
+#define ENCT2_DBG_PX_RST ((0x2469 << 2) + 0xff000000)
+#define ENCT2_DBG_LN_RST ((0x246a << 2) + 0xff000000)
+#define ENCT2_DBG_PX_INT ((0x246b << 2) + 0xff000000)
+#define ENCT2_DBG_LN_INT ((0x246c << 2) + 0xff000000)
+//----------- Video Advanced setting
+#define ENCT2_VIDEO_YFP1_HTIME ((0x246d << 2) + 0xff000000)
+#define ENCT2_VIDEO_YFP2_HTIME ((0x246e << 2) + 0xff000000)
+#define ENCT2_VIDEO_YC_DLY ((0x246f << 2) + 0xff000000)
+#define ENCT2_VIDEO_MAX_PXCNT ((0x2470 << 2) + 0xff000000)
+#define ENCT2_VIDEO_HAVON_END ((0x2471 << 2) + 0xff000000)
+#define ENCT2_VIDEO_HAVON_BEGIN ((0x2472 << 2) + 0xff000000)
+#define ENCT2_VIDEO_VAVON_ELINE ((0x2473 << 2) + 0xff000000)
+#define ENCT2_VIDEO_VAVON_BLINE ((0x2474 << 2) + 0xff000000)
+#define ENCT2_VIDEO_HSO_BEGIN ((0x2475 << 2) + 0xff000000)
+#define ENCT2_VIDEO_HSO_END ((0x2476 << 2) + 0xff000000)
+#define ENCT2_VIDEO_VSO_BEGIN ((0x2477 << 2) + 0xff000000)
+#define ENCT2_VIDEO_VSO_END ((0x2478 << 2) + 0xff000000)
+#define ENCT2_VIDEO_VSO_BLINE ((0x2479 << 2) + 0xff000000)
+#define ENCT2_VIDEO_VSO_ELINE ((0x247a << 2) + 0xff000000)
+#define ENCT2_VIDEO_MAX_LNCNT ((0x247b << 2) + 0xff000000)
+#define ENCT2_VIDEO_BLANKY_VAL ((0x247c << 2) + 0xff000000)
+#define ENCT2_VIDEO_BLANKPB_VAL ((0x247d << 2) + 0xff000000)
+#define ENCT2_VIDEO_BLANKPR_VAL ((0x247e << 2) + 0xff000000)
+#define ENCT2_VIDEO_HOFFST ((0x247f << 2) + 0xff000000)
+#define ENCT2_VIDEO_VOFFST ((0x2480 << 2) + 0xff000000)
+#define ENCT2_VIDEO_RGB_CTRL ((0x2481 << 2) + 0xff000000)
+#define ENCT2_VIDEO_FILT_CTRL ((0x2482 << 2) + 0xff000000)
+#define ENCT2_VIDEO_OFLD_VPEQ_OFST ((0x2483 << 2) + 0xff000000)
+#define ENCT2_VIDEO_OFLD_VOAV_OFST ((0x2484 << 2) + 0xff000000)
+#define ENCT2_VIDEO_MATRIX_CB ((0x2485 << 2) + 0xff000000)
+#define ENCT2_VIDEO_MATRIX_CR ((0x2486 << 2) + 0xff000000)
+#define ENCT2_VIDEO_RGBIN_CTRL ((0x2487 << 2) + 0xff000000)
+#define ENCT2_MAX_LINE_SWITCH_POINT ((0x2488 << 2) + 0xff000000)
+#define ENCT2_DACSEL_0 ((0x2489 << 2) + 0xff000000)
+#define ENCT2_DACSEL_1 ((0x248a << 2) + 0xff000000)
+#define ENCT2_INBUF_CNTL0 ((0x248b << 2) + 0xff000000)
+#define ENCT2_INBUF_CNTL1 ((0x248c << 2) + 0xff000000)
+#define ENCT2_INBUF_CNT ((0x248d << 2) + 0xff000000)
+#define ENCT2_INBUF_HOLD_CNT ((0x248e << 2) + 0xff000000)
+#define ENCT2_INBUF_FIX_PIX_NUM ((0x248f << 2) + 0xff000000)
+//===========================================================================
+// For ENCL
+//===========================================================================
+// bit 15:8 -- vfifo2vd_vd_sel
+// bit 7 -- vfifo2vd_drop
+// bit 6:1 -- vfifo2vd_delay
+// bit 0 -- vfifo2vd_en
+#define ENCL2_VFIFO2VD_CTL ((0x2490 << 2) + 0xff000000)
+// bit 12:0 -- vfifo2vd_pixel_start
+#define ENCL2_VFIFO2VD_PIXEL_START ((0x2491 << 2) + 0xff000000)
+// bit 12:00 -- vfifo2vd_pixel_end
+#define ENCL2_VFIFO2VD_PIXEL_END ((0x2492 << 2) + 0xff000000)
+// bit 10:0 -- vfifo2vd_line_top_start
+#define ENCL2_VFIFO2VD_LINE_TOP_START ((0x2493 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_top_end
+#define ENCL2_VFIFO2VD_LINE_TOP_END ((0x2494 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_start
+#define ENCL2_VFIFO2VD_LINE_BOT_START ((0x2495 << 2) + 0xff000000)
+// bit 10:00 -- vfifo2vd_line_bot_end
+#define ENCL2_VFIFO2VD_LINE_BOT_END ((0x2496 << 2) + 0xff000000)
+#define ENCL2_VFIFO2VD_CTL2 ((0x2497 << 2) + 0xff000000)
+#define ENCL2_TST_EN ((0x2498 << 2) + 0xff000000)
+#define ENCL2_TST_MDSEL ((0x2499 << 2) + 0xff000000)
+#define ENCL2_TST_Y ((0x249a << 2) + 0xff000000)
+#define ENCL2_TST_CB ((0x249b << 2) + 0xff000000)
+#define ENCL2_TST_CR ((0x249c << 2) + 0xff000000)
+#define ENCL2_TST_CLRBAR_STRT ((0x249d << 2) + 0xff000000)
+#define ENCL2_TST_CLRBAR_WIDTH ((0x249e << 2) + 0xff000000)
+#define ENCL2_TST_VDCNT_STSET ((0x249f << 2) + 0xff000000)
+//===========================================================================
+// ENCL2 registers
+#define ENCL2_VIDEO_EN ((0x24a0 << 2) + 0xff000000)
+#define ENCL2_VIDEO_Y_SCL ((0x24a1 << 2) + 0xff000000)
+#define ENCL2_VIDEO_PB_SCL ((0x24a2 << 2) + 0xff000000)
+#define ENCL2_VIDEO_PR_SCL ((0x24a3 << 2) + 0xff000000)
+#define ENCL2_VIDEO_Y_OFFST ((0x24a4 << 2) + 0xff000000)
+#define ENCL2_VIDEO_PB_OFFST ((0x24a5 << 2) + 0xff000000)
+#define ENCL2_VIDEO_PR_OFFST ((0x24a6 << 2) + 0xff000000)
+//----- Video mode
+#define ENCL2_VIDEO_MODE ((0x24a7 << 2) + 0xff000000)
+#define ENCL2_VIDEO_MODE_ADV ((0x24a8 << 2) + 0xff000000)
+//--------------- Debug pins
+#define ENCL2_DBG_PX_RST ((0x24a9 << 2) + 0xff000000)
+#define ENCL2_DBG_LN_RST ((0x24aa << 2) + 0xff000000)
+#define ENCL2_DBG_PX_INT ((0x24ab << 2) + 0xff000000)
+#define ENCL2_DBG_LN_INT ((0x24ac << 2) + 0xff000000)
+//----------- Video Advanced setting
+#define ENCL2_VIDEO_YFP1_HTIME ((0x24ad << 2) + 0xff000000)
+#define ENCL2_VIDEO_YFP2_HTIME ((0x24ae << 2) + 0xff000000)
+#define ENCL2_VIDEO_YC_DLY ((0x24af << 2) + 0xff000000)
+#define ENCL2_VIDEO_MAX_PXCNT ((0x24b0 << 2) + 0xff000000)
+#define ENCL2_VIDEO_HAVON_END ((0x24b1 << 2) + 0xff000000)
+#define ENCL2_VIDEO_HAVON_BEGIN ((0x24b2 << 2) + 0xff000000)
+#define ENCL2_VIDEO_VAVON_ELINE ((0x24b3 << 2) + 0xff000000)
+#define ENCL2_VIDEO_VAVON_BLINE ((0x24b4 << 2) + 0xff000000)
+#define ENCL2_VIDEO_HSO_BEGIN ((0x24b5 << 2) + 0xff000000)
+#define ENCL2_VIDEO_HSO_END ((0x24b6 << 2) + 0xff000000)
+#define ENCL2_VIDEO_VSO_BEGIN ((0x24b7 << 2) + 0xff000000)
+#define ENCL2_VIDEO_VSO_END ((0x24b8 << 2) + 0xff000000)
+#define ENCL2_VIDEO_VSO_BLINE ((0x24b9 << 2) + 0xff000000)
+#define ENCL2_VIDEO_VSO_ELINE ((0x24ba << 2) + 0xff000000)
+#define ENCL2_VIDEO_MAX_LNCNT ((0x24bb << 2) + 0xff000000)
+#define ENCL2_VIDEO_BLANKY_VAL ((0x24bc << 2) + 0xff000000)
+#define ENCL2_VIDEO_BLANKPB_VAL ((0x24bd << 2) + 0xff000000)
+#define ENCL2_VIDEO_BLANKPR_VAL ((0x24be << 2) + 0xff000000)
+#define ENCL2_VIDEO_HOFFST ((0x24bf << 2) + 0xff000000)
+#define ENCL2_VIDEO_VOFFST ((0x24c0 << 2) + 0xff000000)
+#define ENCL2_VIDEO_RGB_CTRL ((0x24c1 << 2) + 0xff000000)
+#define ENCL2_VIDEO_FILT_CTRL ((0x24c2 << 2) + 0xff000000)
+#define ENCL2_VIDEO_OFLD_VPEQ_OFST ((0x24c3 << 2) + 0xff000000)
+#define ENCL2_VIDEO_OFLD_VOAV_OFST ((0x24c4 << 2) + 0xff000000)
+#define ENCL2_VIDEO_MATRIX_CB ((0x24c5 << 2) + 0xff000000)
+#define ENCL2_VIDEO_MATRIX_CR ((0x24c6 << 2) + 0xff000000)
+#define ENCL2_VIDEO_RGBIN_CTRL ((0x24c7 << 2) + 0xff000000)
+#define ENCL2_MAX_LINE_SWITCH_POINT ((0x24c8 << 2) + 0xff000000)
+#define ENCL2_DACSEL_0 ((0x24c9 << 2) + 0xff000000)
+#define ENCL2_DACSEL_1 ((0x24ca << 2) + 0xff000000)
+#define ENCT2_VIDEO_H_PRE_DE_END ((0x24cb << 2) + 0xff000000)
+#define ENCT2_VIDEO_H_PRE_DE_BEGIN ((0x24cc << 2) + 0xff000000)
+#define ENCT2_VIDEO_V_PRE_DE_ELINE ((0x24cd << 2) + 0xff000000)
+#define ENCT2_VIDEO_V_PRE_DE_BLINE ((0x24ce << 2) + 0xff000000)
+#define ENCL2_VIDEO_H_PRE_DE_END ((0x24cf << 2) + 0xff000000)
+#define ENCL2_VIDEO_H_PRE_DE_BEGIN ((0x24d0 << 2) + 0xff000000)
+#define ENCL2_VIDEO_V_PRE_DE_ELINE ((0x24d1 << 2) + 0xff000000)
+#define ENCL2_VIDEO_V_PRE_DE_BLINE ((0x24d2 << 2) + 0xff000000)
+#define ENCL2_INBUF_CNTL0 ((0x24d3 << 2) + 0xff000000)
+#define ENCL2_INBUF_CNTL1 ((0x24d4 << 2) + 0xff000000)
+#define ENCL2_INBUF_CNT ((0x24d5 << 2) + 0xff000000)
+#define ENCL2_INBUF_HOLD_CNT ((0x24d6 << 2) + 0xff000000)
+#define ENCL2_INBUF_FIX_PIX_NUM ((0x24d7 << 2) + 0xff000000)
+#define VPU2_VPU_PWM_V0 ((0x24e0 << 2) + 0xff000000)
+#define VPU2_VPU_PWM_V1 ((0x24e1 << 2) + 0xff000000)
+#define VPU2_VPU_PWM_V2 ((0x24e2 << 2) + 0xff000000)
+#define VPU2_VPU_PWM_V3 ((0x24e3 << 2) + 0xff000000)
+#define VPU2_VPU_PWM_H0 ((0x24e4 << 2) + 0xff000000)
+#define VPU2_VPU_PWM_H1 ((0x24e5 << 2) + 0xff000000)
+#define VPU2_VPU_PWM_H2 ((0x24e6 << 2) + 0xff000000)
+#define VPU2_VPU_PWM_H3 ((0x24e7 << 2) + 0xff000000)
+#define VPU2_VPU_3D_SYNC1 ((0x24e8 << 2) + 0xff000000)
+#define VPU2_VPU_3D_SYNC2 ((0x24e9 << 2) + 0xff000000)
+#define VPU2_VENC_DUMMY ((0x24df << 2) + 0xff000000)
+#define VPU2_VENC_ERROR ((0x24ea << 2) + 0xff000000)
+#define VPU2_VENCI_STAT ((0x24eb << 2) + 0xff000000)
+#define VPU2_VENCP_STAT ((0x24ec << 2) + 0xff000000)
+#define VPU2_VENCL_STAT ((0x24ed << 2) + 0xff000000)
+#define VPU2_VENC_DITH ((0x24ee << 2) + 0xff000000)
+#define VPU2_VENC_CTRL ((0x24ef << 2) + 0xff000000)
+#define VPU2_VENCL_DITH_CTRL ((0x24f0 << 2) + 0xff000000)
+#define VPU2_VENCL_DITH_LUT_1 ((0x24f1 << 2) + 0xff000000)
+#define VPU2_VENCL_DITH_LUT_2 ((0x24f2 << 2) + 0xff000000)
+#define VPU2_VENCL_DITH_LUT_3 ((0x24f3 << 2) + 0xff000000)
+#define VPU2_VENCL_DITH_LUT_4 ((0x24f4 << 2) + 0xff000000)
+#define VPU2_VENCL_DITH_LUT_5 ((0x24f5 << 2) + 0xff000000)
+#define VPU2_VENCL_DITH_LUT_6 ((0x24f6 << 2) + 0xff000000)
+#define VPU2_VENCL_DITH_LUT_7 ((0x24f7 << 2) + 0xff000000)
+#define VPU2_VENCL_DITH_LUT_8 ((0x24f8 << 2) + 0xff000000)
+#define VPU2_VENCL_DITH_LUT_9 ((0x24f9 << 2) + 0xff000000)
+#define VPU2_VENCL_DITH_LUT_10 ((0x24fa << 2) + 0xff000000)
+#define VPU2_VENCL_DITH_LUT_11 ((0x24fb << 2) + 0xff000000)
+#define VPU2_VENCL_DITH_LUT_12 ((0x24fc << 2) + 0xff000000)
+//
+// Closing file: venc2_2_regs.h
+//
+//===========================================================================
+//===========================================================================
+//
+// Reading file: vpu_top_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//======================================================================
+// vpu register.
+//======================================================================
+// -----------------------------------------------
+// REG_BASE: VPU_VCBUS_BASE = 0x27
+// -----------------------------------------------
+#define VPU_CRC_CTRL ((0x2701 << 2) + 0xff000000)
+#define VPU_RO_CRC0 ((0x2702 << 2) + 0xff000000)
+#define VPU_RO_CRC1 ((0x2703 << 2) + 0xff000000)
+#define VPU_RO_CRC2 ((0x2704 << 2) + 0xff000000)
+#define VPU_RO_CRC3 ((0x2705 << 2) + 0xff000000)
+#define VPU_RO_CRC4 ((0x2706 << 2) + 0xff000000)
+#define VPU_RO_CRC5 ((0x2707 << 2) + 0xff000000)
+#define VPU_RO_CRC6 ((0x2708 << 2) + 0xff000000)
+#define VPU_INTF_CTRL ((0x270a << 2) + 0xff000000)
+#define VPU_APB_PROT_CTRL ((0x270b << 2) + 0xff000000)
+#define VPU_ENC_ERROR ((0x270c << 2) + 0xff000000)
+#define VPU_SECURE_REG ((0x270d << 2) + 0xff000000)
+#define VPU_SECURE_ST_RO ((0x270e << 2) + 0xff000000)
+#define VPU_VDIN_SEC_IN ((0x270f << 2) + 0xff000000)
+//Read only
+//`define VPU_TVDVBI_VSLATCH_ADDR 8'h12
+//Read only
+//`define VPU_TVDVBI_WRRSP_ADDR 8'h13
+#define VPU_VDIN_PRE_ARB_CTRL ((0x2714 << 2) + 0xff000000)
+#define VPU_VDISP_PRE_ARB_CTRL ((0x2715 << 2) + 0xff000000)
+#define VPU_VPUARB2_PRE_ARB_CTRL ((0x2716 << 2) + 0xff000000)
+// [31:21] Reserved.
+// [20:18] cntl_encx_clk_sel
+// [17:16] cntl_vencl_dpi_sel_clk
+// [15: 8] Reserved
+// [ 6: 4] Reserved
+// [ 3: 2] cntl_viu2_sel_venc. Select which one of the encI/P/T that VIU2 connects to:
+// 0=No connection, 1=ENCI, 2=ENCP, 3=ENCT.
+// [ 1: 0] cntl_viu1_sel_venc. Select which one of the encI/P/T that VIU1 connects to:
+// 0=No connection, 1=ENCI, 2=ENCP, 3=ENCT.
+#define VPU_VIU_VENC_MUX_CTRL ((0x271a << 2) + 0xff000000)
+// [15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.
+// [11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.
+// [ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:
+// 0=output CrYCb(BRG);
+// 1=output YCbCr(RGB);
+// 2=output YCrCb(RBG);
+// 3=output CbCrY(GBR);
+// 4=output CbYCr(GRB);
+// 5=output CrCbY(BGR);
+// 6,7=Rsrv.
+// [ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).
+// [ 3] inv_vsync. 1=Invert Vsync polarity.
+// [ 2] inv_hsync. 1=Invert Hsync polarity.
+// [ 1: 0] src_sel. 0=Disable output to HDMI; 1=Select VENC_I output to HDMI; 2=Select VENC_P output.
+#define VPU_HDMI_SETTING ((0x271b << 2) + 0xff000000)
+#define ENCI_INFO_READ ((0x271c << 2) + 0xff000000)
+#define ENCP_INFO_READ ((0x271d << 2) + 0xff000000)
+#define ENCT_INFO_READ ((0x271e << 2) + 0xff000000)
+#define ENCL_INFO_READ ((0x271f << 2) + 0xff000000)
+// Bit 0 RW, viu_rst_n
+// Bit 1 RW, vdin_mmc_arb_rst_n
+// Bit 2 RW, vdisp_mmc_arb_rst_n
+// Bit 3 RW, vpuarb2_mmc_arb_rst_n
+#define VPU_SW_RESET ((0x2720 << 2) + 0xff000000)
+// Bit 6 RW, gclk_mpeg_vpu_misc
+// Bit 5 RW, gclk_mpeg_venc_l_top
+// Bit 4 RW, gclk_mpeg_vencl_int
+// Bit 3 RW, gclk_mpeg_vencp_int
+// Bit 2 RW, gclk_mpeg_vi2_top
+// Bit 1 RW, gclk_mpeg_vi_top
+// Bit 0 RW, gclk_mpeg_venc_p_top
+#define VPU_CLK_GATE ((0x2723 << 2) + 0xff000000)
+#define VPU_MEM_PD_REG0 ((0x2725 << 2) + 0xff000000)
+#define VPU_MEM_PD_REG1 ((0x2726 << 2) + 0xff000000)
+// [ 31] hdmi_data_ovr_en: 1=Enable overriding data input to HDMI TX with hdmi_data_ovr[29:0]. 0=No override. Default 0.
+// [ 30] Reserved. Default 0
+// [29: 0] hdmi_data_ovr. Default 0.
+#define VPU_HDMI_DATA_OVR ((0x2727 << 2) + 0xff000000)
+#define VPU_AXI_QOS_RD0 ((0x2730 << 2) + 0xff000000)
+#define VPU_AXI_QOS_RD1 ((0x2731 << 2) + 0xff000000)
+#define VPU_AXI_QOS_WR0 ((0x2732 << 2) + 0xff000000)
+//Bit 0, if true, force vencl clk enable, otherwise, it might auto turn off by mipi DSI
+#define VPU_MISC_CTRL ((0x2740 << 2) + 0xff000000)
+#define VPU_ISP_GCLK_CTRL0 ((0x2741 << 2) + 0xff000000)
+#define VPU_ISP_GCLK_CTRL1 ((0x2742 << 2) + 0xff000000)
+#define VPU_HDMI_FMT_CTRL ((0x2743 << 2) + 0xff000000)
+#define VPU_VDIN_ASYNC_HOLD_CTRL ((0x2744 << 2) + 0xff000000)
+#define VPU_VDISP_ASYNC_HOLD_CTRL ((0x2745 << 2) + 0xff000000)
+#define VPU_VPUARB2_ASYNC_HOLD_CTRL ((0x2746 << 2) + 0xff000000)
+#define VPU_ARB_URG_CTRL ((0x2747 << 2) + 0xff000000)
+#define VPU_SECURE_DUMMY ((0x2748 << 2) + 0xff000000)
+#define VPU_VENCL_DITH_EN ((0x2749 << 2) + 0xff000000)
+// todo :
+#define VPU_422TO444_RST ((0x274a << 2) + 0xff000000)
+// todo :
+#define VPU_422TO444_CTRL0 ((0x274b << 2) + 0xff000000)
+// todo :
+#define VPU_422TO444_CTRL1 ((0x274c << 2) + 0xff000000)
+// todo :
+#define VPU_422TO444_CTRL2 ((0x274d << 2) + 0xff000000)
+// todo :
+#define VPU_422TO444_CTRL3 ((0x274e << 2) + 0xff000000)
+// todo :
+#define VPU_422TO444_CTRL4 ((0x274f << 2) + 0xff000000)
+//Bit 20 reg_viu2vdin0_sw_reset: software reset
+//Bit 19:18 reg_viu2vdin0_dn_ratio: down-scale ratio; 0: no scale; 1: 1/2; 2:1/4; 3: reserved
+//Bit 17:16 reg_viu2vdin0_flt_mode: filter mode; 0: no filter; 1:[0 2 2 0]/4; 2:[1 1 1 1]/4; 3:[1 3 3 1]/8
+//Bit 15:14 reversed
+//Bit 13:0 reg_viu2vdin0_hsize: source horizontal size
+#define VPU_VIU2VDIN0_HDN_CTRL ((0x2780 << 2) + 0xff000000)
+#define VPU_VIU_ASYNC_MASK ((0x2781 << 2) + 0xff000000)
+#define VPU_VDIN_MISC_CTRL ((0x2782 << 2) + 0xff000000)
+// [31:29] Reserved.
+// [28:24] cntl_viu2vdin1_sel_data. Select VIU to VDIN data path, must clear it first before changing the path selection:
+// 5'b00000=Disable VIU to VDIN path;
+// 5'b00001=Enable VIU of ENC_I domain to VDIN;
+// 5'b00010=Enable VIU of ENC_P domain to VDIN;
+// 5'b00100=Enable VIU of ENC_T domain to VDIN;
+// 5'b01000=Enable VIU WriteBack 1 domain to VDIN;
+// 5'b10000=Enable VIU WriteBack 2 domain to VDIN;
+// [23:21] Reserved.
+// [20:16] cntl_viu2vdin1_sel_clk. Select which clock to VDIN path, must clear it first before changing the clock:
+// 5'b00000=Disable VIU to VDIN clock;
+// 5'b00001=Select encI clock to VDIN;
+// 5'b00010=Select encP clock to VDIN;
+// 5'b00100=Select encT clock to VDIN;
+// 5'b01000=Select VIU WriteBack 1 clock to VDIN;
+// 5'b10000=Select VIU WriteBack 2 clock to VDIN;
+// [15:13] Reserved.
+// [12: 8] cntl_viu2vdin0_sel_data. Select VIU to VDIN data path, must clear it first before changing the path selection:
+// 5'b00000=Disable VIU to VDIN path;
+// 5'b00001=Enable VIU of ENC_I domain to VDIN;
+// 5'b00010=Enable VIU of ENC_P domain to VDIN;
+// 5'b00100=Enable VIU of ENC_T domain to VDIN;
+// 5'b01000=Enable VIU WriteBack 1 domain to VDIN;
+// 5'b10000=Enable VIU WriteBack 2 domain to VDIN;
+// [ 7:5] Reserved.
+// [ 4: 0] cntl_viu2vdin0_sel_clk. Select which clock to VDIN path, must clear it first before changing the clock:
+// 5'b00000=Disable VIU to VDIN clock;
+// 5'b00001=Select encI clock to VDIN;
+// 5'b00010=Select encP clock to VDIN;
+// 5'b00100=Select encT clock to VDIN;
+// 5'b01000=Select VIU WriteBack 1 clock to VDIN;
+// 5'b10000=Select VIU WriteBack 2 clock to VDIN;
+#define VPU_VIU_VDIN_IF_MUX_CTRL ((0x2783 << 2) + 0xff000000)
+//Bit 20 reg_viu2vdin1_sw_reset: software reset
+//Bit 19:18 reg_viu2vdin1_dn_ratio: down-scale ratio; 0: no scale; 1: 1/2; 2:1/4; 3: reserved
+//Bit 17:16 reg_viu2vdin1_flt_mode: filter mode; 0: no filter; 1:[0 2 2 0]/4; 2:[1 1 1 1]/4; 3:[1 3 3 1]/8
+//Bit 15:14 reversed
+//Bit 13:0 reg_viu2vdin1_hsize: source horizontal size
+#define VPU_VIU2VDIN1_HDN_CTRL ((0x2784 << 2) + 0xff000000)
+#define VPU_VENCX_CLK_CTRL ((0x2785 << 2) + 0xff000000)
+//Bit 0 encp_afifo_clk
+//Bit 1 encl_afifo_clk
+//Bit 2 enci_afifo_clk
+#define VPU_DISP_VIU0_CTRL ((0x2786 << 2) + 0xff000000)
+//Bit 31 lvds_out_enable[0]
+//Bit 30 vbo_out_enable[0]
+//Bit 29 hdmi_tx_enable[0]
+//Bit 28 dsi_edp_enable[0]
+//Bit 27:7 reversed
+//Bit 6 viu0_disable_rst_afifo
+//Bit 5:4 viu0_vs_hs_ctrl
+//Bit 3:2 viu0_force_field_ctrl
+//Bit 1 viu0_force_go_line
+//Bit 0 viu0_force_go_field
+#define VPU_DISP_VIU1_CTRL ((0x2787 << 2) + 0xff000000)
+//Bit 31 lvds_out_enable[1]
+//Bit 30 vbo_out_enable[1]
+//Bit 29 hdmi_tx_enable[1]
+//Bit 28 dsi_edp_enable[1]
+//Bit 27:7 reversed
+//Bit 6 viu1_disable_rst_afifo
+//Bit 5:4 viu1_vs_hs_ctrl
+//Bit 3:2 viu1_force_field_ctrl
+//Bit 1 viu1_force_go_line
+//Bit 0 viu1_force_go_field
+#define VPU_DISP_VIU2_CTRL ((0x2788 << 2) + 0xff000000)
+//Bit 31 lvds_out_enable[2]
+//Bit 30 vbo_out_enable[2]
+//Bit 29 hdmi_tx_enable[2]
+//Bit 28 dsi_edp_enable[2]
+//Bit 27:7 reversed
+//Bit 6 viu2_disable_rst_afifo
+//Bit 5:4 viu2_vs_hs_ctrl
+//Bit 3:2 viu2_force_field_ctrl
+//Bit 1 viu2_force_go_line
+//Bit 0 viu2_force_go_field
+#define VPU_VENC_RGN_CTRL ((0x2789 << 2) + 0xff000000)
+#define VPU_VENC_RGN_RSIZE ((0x278a << 2) + 0xff000000)
+#define VPU_DISP_WRAP_CTRL ((0x278b << 2) + 0xff000000)
+// vpu arbtration :
+// the segment is 8'h90-8'hc8
+//
+// Reading file: vpu_arb_axi_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+//// reg
+////===============================////
+#define VPU_RDARB_MODE_L1C1 ((0x2790 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, rdarb_sel uns, default = 0 ,
+// rdarb_sel[0]==0 slave dc0 connect master port0 rdarb_sel[0]==1 slave dc0 connect master port1
+// rdarb_sel[1]==0 slave dc1 connect master port0 rdarb_sel[1]==1 slave dc1 connect master port1
+// rdarb_sel[2]==0 slave dc2 connect master port0 rdarb_sel[2]==1 slave dc2 connect master port1
+// rdarb_sel[3]==0 slave dc3 connect master port0 rdarb_sel[3]==1 slave dc3 connect master port1
+// rdarb_sel[4]==0 slave dc4 connect master port0 rdarb_sel[4]==1 slave dc4 connect master port1
+// rdarb_sel[5]==0 slave dc5 connect master port0 rdarb_sel[5]==1 slave dc5 connect master port1
+//Bit 15:10, reserved
+//Bit 9:8, rdarb_arb_mode uns, default = 0 ,
+// rdarb_arb_mode[0] master port0 arb way,
+// rdarb_arb_mode[1] master port1 arb way,
+//Bit 7:4, reserved
+//Bit 3:0, rdarb_gate_clk_ctrl uns, default = 0 ,
+// rdarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// rdarb_gate_clk_ctrl[3:2] master port1 clk gate control
+#define VPU_RDARB_REQEN_SLV_L1C1 ((0x2791 << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, rdarb_dc_req_en unsigned , default = 12'hfff
+// rdarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// rdarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// rdarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// rdarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// rdarb_dc_req_en[4]: the slv4 req to mst port0 enable,
+// rdarb_dc_req_en[5]: the slv5 req to mst port0 enable,
+// rdarb_dc_req_en[6]: the slv0 req to mst port1 enable,
+// rdarb_dc_req_en[7]: the slv1 req to mst port1 enable,
+// rdarb_dc_req_en[8]: the slv2 req to mst port1 enable,
+// rdarb_dc_req_en[9]: the slv3 req to mst port1 enable,
+// rdarb_dc_req_en[10]: the slv4 req to mst port1 enable,
+// rdarb_dc_req_en[11]: the slv5 req to mst port1 enable,
+#define VPU_RDARB_WEIGH0_SLV_L1C1 ((0x2792 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// rddc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// rddc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// rddc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+// rddc_weigh_sxn[4*6+:6]: the slv4 req weigh number
+#define VPU_RDARB_WEIGH1_SLV_L1C1 ((0x2793 << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[5*6+:6]: the slv5 req weigh number
+#define VPU_WRARB_MODE_L1C1 ((0x2794 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, wrarb_sel uns, default = 0 ,
+// wrarb_sel[0]==0 slave dc0 connect master port0 wrarb_sel[0]==1 slave dc0 connect master port1
+// wrarb_sel[1]==0 slave dc1 connect master port0 wrarb_sel[1]==1 slave dc1 connect master port1
+// wrarb_sel[2]==0 slave dc2 connect master port0 wrarb_sel[2]==1 slave dc2 connect master port1
+// wrarb_sel[3]==0 slave dc3 connect master port0 wrarb_sel[3]==1 slave dc3 connect master port1
+// wrarb_sel[4]==0 slave dc4 connect master port0 wrarb_sel[4]==1 slave dc4 connect master port1
+// wrarb_sel[5]==0 slave dc5 connect master port0 wrarb_sel[5]==1 slave dc5 connect master port1
+//Bit 15:10, reserved
+//Bit 9:8, wrarb_arb_mode uns, default = 0 ,
+// wrarb_arb_mode[0] master port0 arb way,
+// wrarb_arb_mode[1] master port1 arb way,
+//Bit 7:4, reserved
+//Bit 3:0, wrarb_gate_clk_ctrl uns, default = 0 ,
+// wrarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// wrarb_gate_clk_ctrl[3:2] master port1 clk gate control
+#define VPU_WRARB_REQEN_SLV_L1C1 ((0x2795 << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, wrarb_dc_req_en unsigned , default = 0
+// wrarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// wrarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// wrarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// wrarb_dc_req_en[4]: the slv4 req to mst port0 enable,
+// wrarb_dc_req_en[5]: the slv5 req to mst port0 enable,
+// wrarb_dc_req_en[0]: the slv0 req to mst port1 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port1 enable,
+// wrarb_dc_req_en[2]: the slv2 req to mst port1 enable,
+// wrarb_dc_req_en[3]: the slv3 req to mst port1 enable,
+// wrarb_dc_req_en[4]: the slv4 req to mst port1 enable,
+// wrarb_dc_req_en[5]: the slv5 req to mst port1 enable,
+#define VPU_WRARB_WEIGH0_SLV_L1C1 ((0x2796 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// wrdc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// wrdc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+// wrdc_weigh_sxn[4*6+:6]: the slv4 req weigh number
+#define VPU_WRARB_WEIGH1_SLV_L1C1 ((0x2797 << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[5*6+:6]: the slv5 req weigh number
+#define VPU_RDWR_ARB_STATUS_L1C1 ((0x2798 << 2) + 0xff000000)
+//Bit 31:4, reserved
+//Bit 3:2, wrarb_arb_busy unsigned , default = 0
+//Bit 1:0, rdarb_arb_busy unsigned , default = 0
+#define VPU_RDARB_MODE_L1C2 ((0x2799 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, rdarb_sel uns, default = 0 ,
+// rdarb_sel[0]==0 slave dc0 connect master port0 rdarb_sel[0]==1 slave dc0 connect master port1
+// rdarb_sel[1]==0 slave dc1 connect master port0 rdarb_sel[1]==1 slave dc1 connect master port1
+// rdarb_sel[2]==0 slave dc2 connect master port0 rdarb_sel[2]==1 slave dc2 connect master port1
+// rdarb_sel[3]==0 slave dc3 connect master port0 rdarb_sel[3]==1 slave dc3 connect master port1
+// rdarb_sel[4]==0 slave dc4 connect master port0 rdarb_sel[4]==1 slave dc4 connect master port1
+//Bit 15:10, reserved
+//Bit 9:8, rdarb_arb_mode uns, default = 0 ,
+// rdarb_arb_mode[0] master port0 arb way,
+// rdarb_arb_mode[1] master port1 arb way,
+//Bit 7:4, reserved
+//Bit 3:0, rdarb_gate_clk_ctrl uns, default = 0 ,
+// rdarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// rdarb_gate_clk_ctrl[3:2] master port0 clk gate control
+#define VPU_RDARB_REQEN_SLV_L1C2 ((0x279a << 2) + 0xff000000)
+//Bit 31:10, reserved
+//Bit 9:0, rdarb_dc_req_en unsigned , default = 0
+// rdarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// rdarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// rdarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// rdarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// rdarb_dc_req_en[4]: the slv4 req to mst port0 enable,
+// rdarb_dc_req_en[5]: the slv0 req to mst port1 enable,
+// rdarb_dc_req_en[6]: the slv1 req to mst port1 enable,
+// rdarb_dc_req_en[7]: the slv2 req to mst port1 enable,
+// rdarb_dc_req_en[8]: the slv3 req to mst port1 enable,
+// rdarb_dc_req_en[9]: the slv4 req to mst port1 enable,
+#define VPU_RDARB_WEIGH0_SLV_L1C2 ((0x279b << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// rddc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// rddc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// rddc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+// rddc_weigh_sxn[4*6+:6]: the slv4 req weigh number
+#define VPU_RDWR_ARB_STATUS_L1C2 ((0x279c << 2) + 0xff000000)
+//Bit 31:3, reserved
+//Bit 2, wrarb_arb_busy unsigned , default = 0
+//Bit 1:0, rdarb_arb_busy unsigned , default = 0
+#define VPU_RDARB_MODE_L2C1 ((0x279d << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, rdarb_sel uns, default = 0 ,
+// rdarb_sel[0]==0 slave dc0 connect master port0 rdarb_sel[0]==1 slave dc0 connect master port1
+// rdarb_sel[1]==0 slave dc1 connect master port0 rdarb_sel[1]==1 slave dc1 connect master port1
+// rdarb_sel[2]==0 slave dc2 connect master port0 rdarb_sel[2]==1 slave dc2 connect master port1
+// rdarb_sel[3]==0 slave dc3 connect master port0 rdarb_sel[3]==1 slave dc3 connect master port1
+// rdarb_sel[4]==0 slave dc4 connect master port0 rdarb_sel[4]==1 slave dc4 connect master port1
+// rdarb_sel[5]==0 slave dc5 connect master port0 rdarb_sel[5]==1 slave dc5 connect master port1
+//Bit 15:11, reserved
+//Bit 10:8, rdarb_arb_mode uns, default = 0 ,
+// rdarb_arb_mode[0] master port0 arb way,
+// rdarb_arb_mode[1] master port1 arb way,
+//Bit 7:6, reserved
+//Bit 5:0, rdarb_gate_clk_ctrl uns, default = 0 ,
+// rdarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// rdarb_gate_clk_ctrl[3:2] master port1 clk gate control
+// rdarb_gate_clk_ctrl[5:4] master port2 clk gate control
+#define VPU_RDARB_REQEN_SLV_L2C1 ((0x279e << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:0, rdarb_dc_req_en unsigned , default = 0
+// rdarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// rdarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// rdarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// rdarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// rdarb_dc_req_en[4]: the slv4 req to mst port0 enable,
+// rdarb_dc_req_en[5]: the slv5 req to mst port0 enable,
+// rdarb_dc_req_en[0]: the slv0 req to mst port1 enable,
+// rdarb_dc_req_en[1]: the slv1 req to mst port1 enable,
+// rdarb_dc_req_en[2]: the slv2 req to mst port1 enable,
+// rdarb_dc_req_en[3]: the slv3 req to mst port1 enable,
+// rdarb_dc_req_en[4]: the slv4 req to mst port1 enable,
+// rdarb_dc_req_en[5]: the slv5 req to mst port1 enable,
+#define VPU_RDARB_WEIGH0_SLV_L2C1 ((0x279f << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// rddc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// rddc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// rddc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+// rddc_weigh_sxn[4*6+:6]: the slv4 req weigh number
+#define VPU_RDARB_WEIGH1_SLV_L2C1 ((0x27a0 << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[5*6+:6]: the slv5 req weigh number
+#define VPU_RDWR_ARB_STATUS_L2C1 ((0x27a1 << 2) + 0xff000000)
+//Bit 31:4, reserved
+//Bit 3:2, wrarb_arb_busy unsigned , default = 0
+//Bit 1:0, rdarb_arb_busy unsigned , default = 0
+#define VPU_WRARB_MODE_L2C1 ((0x27a2 << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:16, wrarb_sel uns, default = 0 ,
+// wrarb_sel[0]==0 slave dc0 connect master port0 wrarb_sel[0]==1 slave dc0 connect master port1
+// wrarb_sel[1]==0 slave dc1 connect master port0 wrarb_sel[1]==1 slave dc1 connect master port1
+// wrarb_sel[2]==0 slave dc2 connect master port0 wrarb_sel[2]==1 slave dc2 connect master port1
+// wrarb_sel[3]==0 slave dc3 connect master port0 wrarb_sel[3]==1 slave dc3 connect master port1
+//Bit 15:10, reserved
+//Bit 9:8, wrarb_arb_mode uns, default = 0 ,
+// wrarb_arb_mode[0] master port0 arb way,
+// wrarb_arb_mode[1] master port1 arb way,
+//Bit 7:4, reserved
+//Bit 3:0, wrarb_gate_clk_ctrl uns, default = 0 ,
+// wrarb_gate_clk_ctrl[1:0] master port0 clk gate control
+// wrarb_gate_clk_ctrl[3:2] master port0 clk gate control
+#define VPU_WRARB_REQEN_SLV_L2C1 ((0x27a3 << 2) + 0xff000000)
+//Bit 31:8, reserved
+//Bit 7:0, wrarb_dc_req_en unsigned , default = 0
+// wrarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+// wrarb_dc_req_en[2]: the slv2 req to mst port0 enable,
+// wrarb_dc_req_en[3]: the slv3 req to mst port0 enable,
+// wrarb_dc_req_en[0]: the slv0 req to mst port1 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port1 enable,
+// wrarb_dc_req_en[2]: the slv2 req to mst port1 enable,
+// wrarb_dc_req_en[3]: the slv3 req to mst port1 enable,
+#define VPU_WRARB_WEIGH0_SLV_L2C1 ((0x27a4 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// wrdc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[2*6+:6]: the slv2 req weigh number
+// wrdc_weigh_sxn[3*6+:6]: the slv3 req weigh number
+#define VPU_ASYNC_RD_MODE0 ((0x27a5 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
+#define VPU_ASYNC_RD_MODE1 ((0x27a6 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
+#define VPU_ASYNC_RD_MODE2 ((0x27a7 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
+#define VPU_ASYNC_RD_MODE3 ((0x27a8 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
+#define VPU_ASYNC_RD_MODE4 ((0x27a9 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, rd_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, rd_rel_num unsigned , default = 0 release the read command threshold
+#define VPU_ASYNC_WR_MODE0 ((0x27aa << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
+#define VPU_ASYNC_WR_MODE1 ((0x27ab << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
+#define VPU_ASYNC_WR_MODE2 ((0x27ac << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, req_en unsigned , default = 0 async enable
+//Bit 17:16, clk_gate_ctrl unsigned , default = 0 async clock gate control
+//Bit 15:12, auto_arugt_weight unsigned , default = 4
+//Bit 11, reserved
+//Bit 10:9, arugt_sel unsigned , default = 0
+// 00 : use auto fifo arugt generate the output arugt.
+// 01 : use the register bit control
+// 00 : use the input arguent
+//Bit 8, arguent_cfg unsigned , default = 0 register arguent control bit
+//Bit 7:4, wr_hold_num unsigned , default = 4 hold the read command threshold
+//Bit 3:0, wr_rel_num unsigned , default = 0 release the write command threshold
+#define VPU_ASYNC_STAT ((0x27ad << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18, axiwr2_chan_idle unsigned , RO, axi write channel2 idle state
+//Bit 17, axiwr1_chan_idle unsigned , RO, axi write channel1 idle state
+//Bit 16, axiwr0_chan_idle unsigned , RO, axi write channel0 idle state
+//Bit 15:5, reserved
+//Bit 4, axird4_chan_idle unsigned , RO, axi read channel4 idle state
+//Bit 3, axird3_chan_idle unsigned , RO, axi read channel3 idle state
+//Bit 2, axird2_chan_idle unsigned , RO, axi read channel2 idle state
+//Bit 1, axird1_chan_idle unsigned , RO, axi read channel1 idle state
+//Bit 0, axird0_chan_idle unsigned , RO, axi read channel0 idle state
+#define VPU_WRARB_MODE_L1C2 ((0x27ae << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:16, wrarb_sel uns, default = 0 ,
+// wrarb_sel[0]==0 slave dc0 connect master port0 wrarb_sel[0]==1 slave dc0 connect master port1
+// wrarb_sel[1]==0 slave dc1 connect master port0 wrarb_sel[1]==1 slave dc1 connect master port1
+//Bit 15:9, reserved
+//Bit 8, wrarb_arb_mode uns, default = 0 ,
+// wrarb_arb_mode[0] master port0 arb way,
+//Bit 7:2, reserved
+//Bit 1:0, wrarb_gate_clk_ctrl uns, default = 0 ,
+// wrarb_gate_clk_ctrl[1:0] master port0 clk gate control
+#define VPU_WRARB_REQEN_SLV_L1C2 ((0x27af << 2) + 0xff000000)
+//Bit 31:2, reserved
+//Bit 1:0, wrarb_dc_req_en unsigned , default = 0
+// wrarb_dc_req_en[0]: the slv0 req to mst port0 enable,
+// wrarb_dc_req_en[1]: the slv1 req to mst port0 enable,
+#define VPU_WRARB_WEIGH0_SLV_L1C2 ((0x27b0 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[0*6+:6]: the slv0 req weigh number
+// wrdc_weigh_sxn[1*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[2*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[3*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[4*6+:6]: the slv1 req weigh number
+#define VPU_WRARB_WEIGH1_SLV_L1C2 ((0x27b1 << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:0, wrdc_weigh_sxn unsigned , default = 0
+// wrdc_weigh_sxn[5*6+:6]: the slv0 req weigh number
+// wrdc_weigh_sxn[6*6+:6]: the slv1 req weigh number
+// wrdc_weigh_sxn[7*6+:6]: the slv1 req weigh number
+#define VPU_RDARB_WEIGH1_SLV_L1C2 ((0x27b2 << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:0, rddc_weigh_sxn unsigned , default = 0
+// rddc_weigh_sxn[5*6+:6]: the slv0 req weigh number
+// rddc_weigh_sxn[6*6+:6]: the slv1 req weigh number
+// rddc_weigh_sxn[7*6+:6]: the slv2 req weigh number
+#define VPU_ARB_DBG_CTRL_L1C1 ((0x27b3 << 2) + 0xff000000)
+#define VPU_ARB_DBG_STAT_L1C1 ((0x27b4 << 2) + 0xff000000)
+#define VPU_ARB_DBG_CTRL_L1C2 ((0x27b5 << 2) + 0xff000000)
+#define VPU_ARB_DBG_STAT_L1C2 ((0x27b6 << 2) + 0xff000000)
+#define VPU_ARB_DBG_CTRL_L2C1 ((0x27b7 << 2) + 0xff000000)
+#define VPU_ARB_DBG_STAT_L2C1 ((0x27b8 << 2) + 0xff000000)
+#define VPU_ARB_PATH_CTRL ((0x27b9 << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP00 ((0x27ba << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP01 ((0x27bb << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP02 ((0x27bc << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP03 ((0x27bd << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP10 ((0x27be << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP11 ((0x27bf << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP12 ((0x27c0 << 2) + 0xff000000)
+#define VPU_ARB_PATH_MAP13 ((0x27c1 << 2) + 0xff000000)
+#define VPU_RDARB_UGT_L2C1 ((0x27c2 << 2) + 0xff000000)
+#define VPU_WRARB_UGT_L2C1 ((0x27c3 << 2) + 0xff000000)
+#define VPU_RDARB_LIMT0_L2C1 ((0x27c4 << 2) + 0xff000000)
+#define VPU_RDARB_LIMT1_L2C1 ((0x27c5 << 2) + 0xff000000)
+#define VPU_ARB_AXIWR_PROT ((0x27c6 << 2) + 0xff000000)
+#define VPU_ARB_AXIRD0_PROT ((0x27c7 << 2) + 0xff000000)
+#define VPU_ARB_AXIRD1_PROT ((0x27c8 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_arb_axi_regs.h
+//
+// vpu lut dma
+// the segment is 8'h50~8'h7f & 8'hca-8'hdf
+//
+// Reading file: vpu_lut_dma_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// 0x50~0x7f
+//
+// Reading file: viu_dma_top.h
+//
+#define VPU_DMA_RDMIF0_CTRL ((0x2750 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd0_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd0_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd0_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd0_enable_int // unsigned , RW , default = 0 channel0 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd0_stride // unsigned , RW , default = 512 channel0 send number
+#define VPU_DMA_RDMIF1_CTRL ((0x2751 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd1_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd1_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd1_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd1_enable_int // unsigned , RW , default = 0 channel1 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd1_stride // unsigned , RW , default = 512 channel1 send number
+#define VPU_DMA_RDMIF2_CTRL ((0x2752 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd2_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd2_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd2_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd2_enable_int // unsigned , RW , default = 0 channel2 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd2_stride // unsigned , RW , default = 512 channel2 send number
+#define VPU_DMA_RDMIF3_CTRL ((0x2753 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd3_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd3_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd3_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd3_enable_int // unsigned , RW , default = 0 channel3 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd3_stride // unsigned , RW , default = 512 channel3 send number
+#define VPU_DMA_RDMIF4_CTRL ((0x2754 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd4_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd4_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd4_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd4_enable_int // unsigned , RW , default = 0 channel4 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd4_stride // unsigned , RW , default = 512 channel4 send number
+#define VPU_DMA_RDMIF5_CTRL ((0x2755 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd5_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd5_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd5_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd5_enable_int // unsigned , RW , default = 0 channel5 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd5_stride // unsigned , RW , default = 512 channel5 send number
+#define VPU_DMA_RDMIF6_CTRL ((0x2756 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd6_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd6_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd6_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd6_enable_int // unsigned , RW , default = 0 channel6 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd6_stride // unsigned , RW , default = 512 channel6 send number
+#define VPU_DMA_RDMIF7_CTRL ((0x2757 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27 reg_rd7_frm_ctrl // unsigned , RW , default = 0
+//Bit 26 reg_rd7_frm_froce // unsigned , RW , default = 0
+//Bit 25:24 reg_rd7_frm_ini // unsigned , RW , default = 0
+//Bit 23:16 reg_rd7_enable_int // unsigned , RW , default = 0 channel7 select interrupt source
+//Bit 15:13 reserved
+//Bit 12:0 reg_rd7_stride // unsigned , RW , default = 512 channel7 send number
+#define VPU_DMA_RDMIF0_BADR0 ((0x2758 << 2) + 0xff000000)
+//Bit 31:0 lut0_reg_baddr0
+#define VPU_DMA_RDMIF0_BADR1 ((0x2759 << 2) + 0xff000000)
+//Bit 31:0 lut0_reg_baddr1
+#define VPU_DMA_RDMIF0_BADR2 ((0x275a << 2) + 0xff000000)
+//Bit 31:0 lut0_reg_baddr2
+#define VPU_DMA_RDMIF0_BADR3 ((0x275b << 2) + 0xff000000)
+//Bit 31:0 lut0_reg_baddr3
+#define VPU_DMA_RDMIF1_BADR0 ((0x275c << 2) + 0xff000000)
+//Bit 31:0 lut1_reg_baddr0
+#define VPU_DMA_RDMIF1_BADR1 ((0x275d << 2) + 0xff000000)
+//Bit 31:0 lut1_reg_baddr1
+#define VPU_DMA_RDMIF1_BADR2 ((0x275e << 2) + 0xff000000)
+//Bit 31:0 lut1_reg_baddr2
+#define VPU_DMA_RDMIF1_BADR3 ((0x275f << 2) + 0xff000000)
+//Bit 31:0 lut1_reg_baddr3
+#define VPU_DMA_RDMIF2_BADR0 ((0x2760 << 2) + 0xff000000)
+//Bit 31:0 lut2_reg_baddr0
+#define VPU_DMA_RDMIF2_BADR1 ((0x2761 << 2) + 0xff000000)
+//Bit 31:0 lut2_reg_baddr1
+#define VPU_DMA_RDMIF2_BADR2 ((0x2762 << 2) + 0xff000000)
+//Bit 31:0 lut2_reg_baddr2
+#define VPU_DMA_RDMIF2_BADR3 ((0x2763 << 2) + 0xff000000)
+//Bit 31:0 lut2_reg_baddr3
+#define VPU_DMA_RDMIF3_BADR0 ((0x2764 << 2) + 0xff000000)
+//Bit 31:0 lut3_reg_baddr0
+#define VPU_DMA_RDMIF3_BADR1 ((0x2765 << 2) + 0xff000000)
+//Bit 31:0 lut3_reg_baddr1
+#define VPU_DMA_RDMIF3_BADR2 ((0x2766 << 2) + 0xff000000)
+//Bit 31:0 lut3_reg_baddr2
+#define VPU_DMA_RDMIF3_BADR3 ((0x2767 << 2) + 0xff000000)
+//Bit 31:0 lut3_reg_baddr3
+#define VPU_DMA_RDMIF4_BADR0 ((0x2768 << 2) + 0xff000000)
+//Bit 31:0 lut4_reg_baddr0
+#define VPU_DMA_RDMIF4_BADR1 ((0x2769 << 2) + 0xff000000)
+//Bit 31:0 lut4_reg_baddr1
+#define VPU_DMA_RDMIF4_BADR2 ((0x276a << 2) + 0xff000000)
+//Bit 31:0 lut4_reg_baddr2
+#define VPU_DMA_RDMIF4_BADR3 ((0x276b << 2) + 0xff000000)
+//Bit 31:0 lut4_reg_baddr3
+#define VPU_DMA_RDMIF5_BADR0 ((0x276c << 2) + 0xff000000)
+//Bit 31:0 lut5_reg_baddr0
+#define VPU_DMA_RDMIF5_BADR1 ((0x276d << 2) + 0xff000000)
+//Bit 31:0 lut5_reg_baddr1
+#define VPU_DMA_RDMIF5_BADR2 ((0x276e << 2) + 0xff000000)
+//Bit 31:0 lut5_reg_baddr2
+#define VPU_DMA_RDMIF5_BADR3 ((0x276f << 2) + 0xff000000)
+//Bit 31:0 lut5_reg_baddr3
+#define VPU_DMA_RDMIF6_BADR0 ((0x2770 << 2) + 0xff000000)
+//Bit 31:0 lut6_reg_baddr0
+#define VPU_DMA_RDMIF6_BADR1 ((0x2771 << 2) + 0xff000000)
+//Bit 31:0 lut6_reg_baddr1
+#define VPU_DMA_RDMIF6_BADR2 ((0x2772 << 2) + 0xff000000)
+//Bit 31:0 lut6_reg_baddr2
+#define VPU_DMA_RDMIF6_BADR3 ((0x2773 << 2) + 0xff000000)
+//Bit 31:0 lut6_reg_baddr3
+#define VPU_DMA_RDMIF7_BADR0 ((0x2774 << 2) + 0xff000000)
+//Bit 31:0 lut7_reg_baddr0
+#define VPU_DMA_RDMIF7_BADR1 ((0x2775 << 2) + 0xff000000)
+//Bit 31:0 lut7_reg_baddr1
+#define VPU_DMA_RDMIF7_BADR2 ((0x2776 << 2) + 0xff000000)
+//Bit 31:0 lut7_reg_baddr2
+#define VPU_DMA_RDMIF7_BADR3 ((0x2777 << 2) + 0xff000000)
+//Bit 31:0 lut7_reg_baddr3
+//
+// Closing file: viu_dma_top.h
+//
+// 0x00~0x06
+//`include"viu_com_rdmif_regs.h"
+#define VPU_DMA_RDMIF_CTRL1 ((0x27ca << 2) + 0xff000000)
+#define VPU_DMA_RDMIF_CTRL2 ((0x27cb << 2) + 0xff000000)
+#define VPU_DMA_RDMIF_RO_STAT ((0x27d0 << 2) + 0xff000000)
+//0x07~0x0d
+//`include"viu_com_wrmif_regs.h"
+#define VPU_DMA_WRMIF_CTRL1 ((0x27d1 << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_CTRL2 ((0x27d2 << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_CTRL3 ((0x27d3 << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_BADDR0 ((0x27d4 << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_RO_STAT ((0x27d7 << 2) + 0xff000000)
+#define VPU_DMA_RDMIF_CTRL ((0x27d8 << 2) + 0xff000000)
+#define VPU_DMA_RDMIF_BADDR1 ((0x27d9 << 2) + 0xff000000)
+#define VPU_DMA_RDMIF_BADDR2 ((0x27da << 2) + 0xff000000)
+#define VPU_DMA_RDMIF_BADDR3 ((0x27db << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_CTRL ((0x27dc << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_BADDR1 ((0x27dd << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_BADDR2 ((0x27de << 2) + 0xff000000)
+#define VPU_DMA_WRMIF_BADDR3 ((0x27df << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_lut_dma_regs.h
+//
+//new added 4x4 dither
+// the segment is 8'hf0
+#define VPU_HDMI_DITH_01_04 ((0x27f0 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_01_15 ((0x27f1 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_01_26 ((0x27f2 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_01_37 ((0x27f3 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_10_04 ((0x27f4 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_10_15 ((0x27f5 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_10_26 ((0x27f6 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_10_37 ((0x27f7 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_11_04 ((0x27f8 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_11_15 ((0x27f9 << 2) + 0xff000000)
+#define VPU_HDMI_DITH_11_26 ((0x27fa << 2) + 0xff000000)
+#define VPU_HDMI_DITH_11_37 ((0x27fb << 2) + 0xff000000)
+#define VPU_HDMI_DITH_CNTL ((0x27fc << 2) + 0xff000000)
+#define VPU_HDMI_TIMING_STAT ((0x27fd << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_top_regs.h
+//
+//===========================================================================
+// MIPI CSI2 Controller Adaptor (16'h2a00 - 16'h2aff)
+//===========================================================================
+//`include "csi2_regs.h"
+//===========================================================================
+// D2D3 registers
+//===========================================================================
+//
+// Reading file: d2d3_regs.h
+//
+//===========================================================================
+// D2D3 Registers 0x - 0x
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: D2D3_VCBUS_BASE = 0x2b
+// -----------------------------------------------
+//------------------------------------------------------------------------------
+// D2D3 top-level registers
+//------------------------------------------------------------------------------
+// Bit 31 RW, rd_lock_en, 1 to allow update some read-only registers based on filed
+// Bit 30 RW, sw_rst_nobuf, 1 to reset the whole d2d3 unit
+// Bit 29:28 RW, clk_auto_dis, [29] DBR clock disable
+// [28] DPG clock disable
+// Bit 27:16 RW, clk_ctrl, [27:26] gated clock control for register unit
+// [25:24] gated clock control for DBR unit
+// [23:22] gated clock control for LBDG unit
+// [21:20] gated clock control for MBDG unit
+// [19:18] gated clock control for CBDG unit
+// [17:16] gated clock control for DBLD unit and SCD81 unit
+// Bit 15:12 Reserved
+// Bit 11 RW, lo_chroma_sign, 0: negate the u/v component of DBR left channel video output, 1: bypass
+// Bit 10 RW, ro_chroma_sign, 0: negate the u/v component of DBR right channel video output, 1: bypass
+// Bit 9 RW, vi0_chroma_sign, 0: negate the u/v component of DPG video input, 1: bypass
+// Bit 8 RW, vi1_chroma_sign, 0: negate the u/v component of DBR video input, 1: bypass
+// Bit 7:5 Reserved
+// Bit 4 RW, lg_en, Enable the LBDG unit and LBDG clock
+// Bit 3 RW, mg_en, Enable the MBDG unit and MBDG clock
+// Bit 2 RW, cg_en, Enable the CBDG unit and CBDG clock
+// Bit 1 RW, dbr_en, Enable the DBR unit and DBR clock
+// Bit 0 RW, dpg_en, Enable the DPG unit and clock except sub-unit CBDG, MBDG and LBDG
+#define D2D3_GLB_CTRL ((0x2b00 << 2) + 0xff000000)
+// Indicate the input picture size in DPG unit
+// Bit 31:16 RW, szx_vi_m1, The horizontal size minus 1
+// Bit 15:0 RW, szy_vi_m1, The vertical size minus 1
+#define D2D3_DPG_INPIC_SIZE ((0x2b01 << 2) + 0xff000000)
+// Indicate the output picture size in DBR unit
+// Bit 31:16 RW, szx_vo_m1, The horizontal size minus 1
+// Bit 15:0 RW, szy_vo_m1, The vertical size minus 1
+#define D2D3_DBR_OUTPIC_SIZE ((0x2b02 << 2) + 0xff000000)
+// Indicate the rectangular window to generate the "depth" in DPG unit
+// Bit 31:16 RW, dg_win_x_start, Horizontal start position, count from 0
+// Bit 15:0 RW, dg_win_x_end, Horizontal end position, count from 0
+#define D2D3_DGEN_WIN_HOR ((0x2b03 << 2) + 0xff000000)
+// Indicate the rectangular window to generate the "depth" in DPG unit
+// Bit 31:16 RW, dg_win_y_start, Vertical start position, count from 0
+// Bit 15:0 RW, dg_win_y_end, Vertical end position, count from 0
+#define D2D3_DGEN_WIN_VER ((0x2b04 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// CBDG SCU18 SCD81 SCD81_PRE registers
+// cg: color based depth generate module
+// scu18: scale up module
+// scd81: scale down module
+// scd81_pre: scd81 pre-scale-down module
+//------------------------------------------------------------------------------
+// Indicate parameters of pre-scale-down unit
+// Bit 31:16 RW, scd81_hphs_step, horizontal step
+// Bit 15:0 RW, scd81_hphs_ini, horizontal initial phase
+#define D2D3_PRE_SCD_H ((0x2b05 << 2) + 0xff000000)
+// Bit 31:16 RW, scu18_iniph, initial phase in SCU18,
+// [23:16] indicate the horizontal phase offset from the first data of every line
+// [31:24] indicate the vertical phase offset from the first line of every frame
+// Bit 15:12 Reserved
+// Bit 11 RW, scd81_predrop_en, 1 to enable scd81 pre-scale-down function
+// Bit 10:9 RW, cg_csc_sel, Color Space Conversion(CSC) matrix mode selector in CBDG
+// 0: BT.601 (16-235/240)
+// 1: BT.709 (16-235/240)
+// 2: BT.601 (0-255)
+// 3: BT.709 (0-255)
+// Bit 8 RW, scu18_rep_en, 1 to double each line of the SCU18 output
+// Bit 7:4 RW, scu18_factor, up-scale factor in SCU18 on DBR input depth data
+// [7:6] for vertical, 0->1:1, 1->1:2, 2->1:4, 3->1:8
+// [5:4] for horizontal, 0->1:1, 1->1:2, 2->1:4, 3->1:8
+// Bit 3:0 RW, scd81_factor, down-scale factor in SCD81 on DPG source video
+// [3:2] for vertical, 0->1:1, 1->2:1, 2->4:1, 3->8:1
+// [1:0] for horizontal, 0->1:1, 1->2:1, 2->4:1, 3->8:1
+#define D2D3_SCALER_CTRL ((0x2b06 << 2) + 0xff000000)
+// Bit 31:24 RW, cg_rpg_dth, the down |r-g| threshold for sky detect
+// Bit 23:16 RW, cg_rpg_uth, the up |r-g| threshold for sky detect
+// Bit 15:8 RW, cg_lum_dth, the down Y threshold for sky detect
+// Bit 7:0 RW, cg_lum_uth, the up Y threshold for sky detect
+#define D2D3_CG_THRESHOLD_1 ((0x2b07 << 2) + 0xff000000)
+// Bit 31:24 RW, cg_rpb_dth, the down |r-b| threshold for sky detect
+// Bit 23:16 RW, cg_rpb_uth, the up |r-b| threshold for sky detect
+// Bit 15:8 RW, cg_bpg_dth, the down |b-g| threshold for sky detect
+// Bit 7:0 RW, cg_bpg_uth, the up |b-g| threshold for sky detect
+#define D2D3_CG_THRESHOLD_2 ((0x2b08 << 2) + 0xff000000)
+// Bit 31:24 RW, cg_vp_rel_k, parameter to calculate vanish point reliability
+// Bit 23:16 RW, cg_vp_y_thr, the max limitation to calculate the vanish-point's vertical position
+// Bit 15:8 RW, cg_meet_dval, signed depth value in the sky-bitmap
+// Bit 7:0 RW, cg_unmt_dval, signed depth value not in the sky-bitmap
+#define D2D3_CG_PARAM_1 ((0x2b09 << 2) + 0xff000000)
+// Bit 31:16 RW, cg_vpos_thr, Maximal vertical limitation for sky-bit map when cg_vpos_en=1 and cg_vpos_adpt_en=0
+// Bit 15:8 Reserved
+// Bit 7 RW, cg_vpos_en, 1 to enable the max vertical limitation for sky-bitmap
+// Bit 6 RW, cg_vpos_adpt_en, 1 to enable the adaptive max vertical limitation for sky-bitmap.
+// It is only valid when cg_vpos_en=1.
+// The max vertical limitation is the previous field's vanish-point (vertical position) if cg_vpos_adpt_en=1.
+// Bit 5:4 RW, cg_lpf_bypass, bypass of low pass filter
+// [5]:Vertical bypass, 1: bypass the vertical LPF on the CBDG depth
+// [4]:Horizontal bypass, 1: bypass the horizontal LPF on the CBDG depth
+// Bit 3:0 RW, cg_vp_rel_s, parameter to calculate vanish point reliability
+#define D2D3_CG_PARAM_2 ((0x2b0a << 2) + 0xff000000)
+// Indicate parameters of pre-scale-down unit
+// Bit 31:16 RW, scd81_vphs_step, vertical step
+// Bit 15:0 RW, scd81_vphs_ini, vertical initial phase
+#define D2D3_PRE_SCD_V ((0x2b0b << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// D2P registers
+// d2p: depth to parallax transform module
+//------------------------------------------------------------------------------
+// Bit 31:24 RW, d2p_brdwid, Horizontal boundary width for parallax, the parallax value would be forced to 0 in boundary,
+// the d2p_brdwid should not 0 when D2P_WRAP is enabled
+// Bit 23:22 Reserved
+// Bit 21:20 RW, d2p_lomode, line output mode,
+// 0:whole line is left or right; 1:whole line is left or right;
+// 2:left/right pixel interleaved; 3:left/right half-line interleaved
+// Bit 19 RW, d2p_neg, 1 to exchange the left and right parallax value
+// Bit 18 Reserved
+// Bit 17 RW, d2p_wrap_en, 1 to enable D2P_WRAP unit
+// Bit 16 RW, d2p_lar, Indicate the first output for left or right, 0: left; 1: right
+// Bit 15 RW, d2p_lr_switch, enable left/right flag filed switch automatically, only valid when parallax output mode is field interleaved
+// Bit 14 RW, d2p_1dtolr, enable to generate 2 parallax data (left and right) from one depth
+// Bit 13:12 RW, d2p_out_mode, Parallax output mode
+// 0:left/right pixel interleaved; 1:line or half line interleaved; 2:field interleaved
+// Bit 11:8 RW, d2p_smode, Shift mode,
+// 0: no shift; 1: enable left shift;
+// 2: enable right shift; 3: both left and right shift are enabled
+// Bit 7:0 RW, d2p_offset, depth offset, signed,
+#define D2D3_D2P_PARAM_1 ((0x2b0c << 2) + 0xff000000)
+// Bit 31:24 RW, d2p_pg0, positive parallax gain when Parallax value < pt
+// Bit 23:16 RW, d2p_pg1, positive parallax gain when Parallax value >= pt
+// Bit 15:8 RW, d2p_pt, unsigned value used to separate the positive parallax range
+// Bit 7:0 RW, d2p_plimit, The limitation for positive parallax
+#define D2D3_D2P_PARAM_2 ((0x2b0d << 2) + 0xff000000)
+// Bit 31:24 RW, d2p_ng0, negative parallax gain when Parallax value > -nt
+// Bit 23:16 RW, d2p_ng1, negative parallax gain when Parallax value <= -nt
+// Bit 15:8 RW, d2p_nt, unsigned value used to separate the negative parallax range
+// Bit 7:0 RW, d2p_nlimit, The limitation for negative parallax
+#define D2D3_D2P_PARAM_3 ((0x2b0e << 2) + 0xff000000)
+// Indicate step parameters of SCU18 unit
+// Bit 31:17 Reserved
+// Bit 16 RW, scu18_step_en, step set enable in SCU18
+// Bit 15:8 RW, scu18_hphs_step, horizontal step in SCU18
+// Bit 7:0 RW, scu18_vphs_step, vertical step in SCU18
+#define D2D3_SCU18_STEP ((0x2b0f << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// LBDG and DBLD registers
+// lg: luma based depth generate module
+// db: depth blending module
+//------------------------------------------------------------------------------
+// Bit 31:22 Reserved
+// Bit 21:20 RW, db_lpf_bpcoeff, [21]:Vertical factor of low pass filter,
+// 1: Vfactor = 0/0/64/0/0, 0: Vfactor = {db_vf_a,db_vf_b,db_vf_c,db_vf_b,db_vf_a}, see D2D3_CTRL_15
+// [20]:Horizontal factor of low pass filter,
+// 1: Hfactor = 0/0/64/0/0, 0: Hfactor = {db_hf_a,db_hf_b,db_hf_c,db_hf_b,db_hf_a}, see D2D3_CTRL_14
+// Bit 19:18 RW, lg_lpf_bpcoeff, [19]:Vertical factor of low pass filter, 1: Vfactor = 0/64/0, 0: Vfactor = 20/24/20
+// [18]:Horizontal factor of low pass filter, 1: Hfactor = 0/64/0, 0: Hfactor = 16/32/16
+// Bit 17:16 RW, cg_lpf_bpcoeff, [17]:Vertical factor of low pass filter, 1: Vfactor = 0/64/0, 0: Vfactor = 20/24/20
+// [16]:Horizontal factor of low pass filter, 1: Hfactor = 0/64/0, 0: Hfactor = 16/32/16
+// Bit 15:10 Reserved
+// Bit 9:8 RW, db_lpf_bypass, [9] 1 to bypass the vertical LPF on the DBLD depth
+// [8] 1 to bypass the horizontal LPF on the DBLD depth
+// Bit 7:6 RW, lg_lpf_bypass, [7] 1 to bypass the vertical LPF on the LBDG depth
+// [6] 1 to bypass the horizontal LPF on the LBDG depth
+// Bit 5:0 RW, lg_kc, gain of CPL(v-u+256-y) to calculate the depth in LBDG
+#define D2D3_DPF_LPF_CTRL ((0x2b10 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// DBLD registers
+// db: depth blending module
+//------------------------------------------------------------------------------
+// Bit 31:24 RW, db_g2_cg, gain of CBDG depth in DBLD
+// Bit 23:16 RW, db_o2_cg, offset of CBDG depth in DBLD
+// Bit 15:8 RW, db_g1_cg, gain of CBDG depth using for summary in DBLD
+// Bit 7:0 RW, db_o1_cg, offset of CBDG depth using for summary in DBLD
+#define D2D3_DBLD_CG_PARAM ((0x2b11 << 2) + 0xff000000)
+// Bit 31:24 RW, db_g2_mg, gain of MBDG depth in DBLD
+// Bit 23:16 RW, db_o2_mg, offset of MBDG depth in DBLD
+// Bit 15:8 RW, db_g1_mg, gain of MBDG depth using for summary in DBLD
+// Bit 7:0 RW, db_o1_mg, offset of MBDG depth using for summary in DBLD
+#define D2D3_DBLD_MG_PARAM ((0x2b12 << 2) + 0xff000000)
+// Bit 31:24 RW, db_g2_lg, gain of LBDG depth in DBLD
+// Bit 23:16 RW, db_o2_lg, offset of LBDG depth in DBLD
+// Bit 15:8 RW, db_g1_lg, gain of LBDG depth using for summary in DBLD
+// Bit 7:0 RW, db_o1_lg, offset of LBDG depth using for summary in DBLD
+#define D2D3_DBLD_LG_PARAM ((0x2b13 << 2) + 0xff000000)
+// Bit 31:24 RW, db_factor, unsigned gain of difference in DBLD
+// Bit 23:16 RW, db_hf_a, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign
+// Bit 15:8 RW, db_hf_b, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign
+// Bit 7:0 RW, db_hf_c, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign
+#define D2D3_DBLD_LPF_HCOEFF ((0x2b14 << 2) + 0xff000000)
+// Bit 31:24 RW, db_owin_fill, signed depth value outside the rectangular window defined in register DGEN_WIN_HOR and DGEN_WIN_VER
+// Bit 23:16 RW, db_vf_a, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign
+// Bit 15:8 RW, db_vf_b, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign
+// Bit 7:0 RW, db_vf_c, see register DPF_LPF_CTRL:db_lpf_bpcoeff, sign
+#define D2D3_DBLD_LPF_VCOEFF ((0x2b15 << 2) + 0xff000000)
+// Bit 31:28 RW, hist_depth_idx,
+// Bit 27:26 Reserved
+// Bit 25 RW, mbdg_dep_neg, 1 to negate the output data of MBDG
+// Bit 24 RW, lbdg_dep_neg, 1 to negate the output data of LBDG
+// Bit 23:16 RW, db_f1_ctrl, MUX1 selector
+// [1:0] MUX1 path1 selector, 0:summary, 1:CBDG, 2:MBDG, 3:LBDG
+// [3:2] MUX1 path2 selector, 0:summary, 1:CBDG, 2:MBDG, 3:LBDG
+// [6:4] MUX1 out1 selector, 1:CBDG, 2:MBDG, 3:LBDG, 4:summary, 5:MUX1out0, others:summary
+// [7] MUX1OUT0 selector, 0:MIN (MUX1PATH1,MUX1Path2), 1:MAX (MUX1Path1,MUX1Path2)
+// Bit 15:8 RW, db_f2_ctrl, MUX2 selector
+// [1:0] MUX2 path1 selector, 0:MUX1OUT1, 1:CBDG, 2:MBDG, 3:LBDG
+// [3:2] MUX2 path2 selector, 0:MUX1OUT1, 1:CBDG, 2:MBDG, 3:LBDG
+// [6:4] MUX2 out1 selector, 1:CBDG, 2:MBDG, 3:LBDG, 4:summary, 5:MUX2out0, others:MUX2out0
+// [7] MUX2OUT0 selector, 0:MIN (MUX2PATH1,MUX2Path2), 1:MAX (MUX2Path1,MUX2Path2)
+// Bit 7:4 RW, db_fifo0_sel, the source input of FIFO0
+// 0: no use; 1:from CBDG; 2:from MBDG; 3:from LBDG others:reserved
+// Bit 3:0 RW, db_fifo1_sel, the source input of FIFO1
+// 0: no use; 1:from CBDG; 2:from MBDG; 3:from LBDG 4: from FIFO0; others:reserved
+#define D2D3_DBLD_PATH_CTRL ((0x2b16 << 2) + 0xff000000)
+// Indicate the input picture size in SCU18 unit
+// Bit 31:16 RW, szy_scui, The vertical size
+// Bit 15:0 RW, szx_scui, The horizontal size
+#define D2D3_SCU18_INPIC_SIZE ((0x2b17 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// MBDG registers
+// mg: model based depth generate module
+//------------------------------------------------------------------------------
+// Bit 31:18 Reserved
+// Bit 17 RW, mg_vp_en, mdg vanish point enable, not used
+// Bit 16 RW, mg_sw_en, 1 to use the software forced parameter for the point D, U and C in MBDG
+// Bit 15:8 RW, mg_owin_fill, Signed depth value outside the rectangular window defined in register DGEN_WIN_HOR and DGEN_WIN_VER
+// Bit 7 RW, mg_iir_en, 1 to enable the 2-taps IIR filter in MBDG
+// Bit 6:0 RW, mg_iir, [6]: 1 to bypass the 2-taps IIR filter in MBDG
+// [5:0]:Unsigned coefficient of the 2-taps IIR filter in MBDG
+// [6]:bypass, 1:bypass, 0:not bypass
+#define D2D3_MBDG_CTRL ((0x2b18 << 2) + 0xff000000)
+// Bit 31:28 RW, mg_dtl_pxl_left, Max pixel number (1<< mg_dtl_pxl_left) using in the left window for activities in MBDG
+// Bit 27:24 RW, mg_dtl_pxl_right, Max pixel number (1<< mg_dtl_pxl_right) using in the right window for activities in MBDG
+// Bit 23:16 RW, mg_cx_sw, Depth of point C in horizontal curve in MBDG for software forced
+// Bit 15:8 RW, mg_ux_sw, Depth of point U in horizontal curve in MBDG for software forced
+// Bit 7:0 RW, mg_dx_sw, Depth of point D in horizontal curve in MBDG for software forced
+#define D2D3_MBDG_PARAM_0 ((0x2b19 << 2) + 0xff000000)
+// Bit 31:28 RW, mg_dtl_pxl_up, Max pixel number (1<< mg_dtl_pxl_up) using in the top window for activities in MBDG
+// Bit 27:24 RW, mg_dtl_pxl_dn, Max pixel number (1<< mg_dtl_pxl_dn) using in the bottom window for activities in MBDG
+// Bit 23:16 RW, mg_cy_sw, Depth of point C in vertical curve in MBDG for software forced
+// Bit 15:8 RW, mg_uy_sw, Depth of point U in vertical curve in MBDG for software forced
+// Bit 7:0 RW, mg_dy_sw, Depth of point D in vertical curve in MBDG for software forced
+#define D2D3_MBDG_PARAM_1 ((0x2b1a << 2) + 0xff000000)
+// Bit 31:24 RW, mg_dtl_ln_up, Line number in the top window for activities in MBDG
+// Bit 23:16 RW, mg_dtl_ln_dn, Line number in the bottom window for activities in MBDG
+// Bit 15:8 RW, mg_dtl_ln_left, Column number in the left window for activities in MBDG
+// Bit 7:0 RW, mg_dtl_ln_right,Column number in the right window for activities in MBDG
+#define D2D3_MBDG_PARAM_2 ((0x2b1b << 2) + 0xff000000)
+// Bit 31:24 RW, mg_y_max, Software initial depth of point D and U in vertical curve
+// Bit 23:16 RW, mg_y_min, Software initial depth of point C in vertical curve
+// Bit 15:8 RW, mg_x_max, Software initial depth of point D and U in horizontal curve
+// Bit 7:0 RW, mg_x_min, Software initial depth of point C in horizontal curve
+#define D2D3_MBDG_PARAM_3 ((0x2b1c << 2) + 0xff000000)
+// Bit 31:27 Reserved
+// Bit 26 RW, mg_y_adapt_en, 1 to enable the adaptive mode for point U/D in vertical curve calculation
+// Bit 25 RW, mg_xmm_adapt_en, 1 to enable the XMM adaptive mode for point U/D in horizontal curve calculation
+// Bit 24 RW, mg_x_adapt_en, 1 to enable the adaptive mode for point U/D in horizontal curve calculation
+// Bit 23:20 RW, mg_ytrans_1, Shifter controller in vertical curve calculation, if mg_xtrans_1<0, right shift abs(mg_xtrans_1) bits, others left shift abs(mg_xtrans_1) bits
+// Bit 19:16 RW, mg_xtrans_1, Shifter controller in horizontal curve calculation, if mg_xtrans_1<0, right shift abs(mg_xtrans_1) bits, others left shift abs(mg_xtrans_1) bits
+// Bit 15:8 RW, mg_yk_0, The based activities value of the ACT for vertical curve
+// Bit 7:0 RW, mg_xk_0, The based activities value of the ACT for horizontal curve
+#define D2D3_MBDG_PARAM_4 ((0x2b1d << 2) + 0xff000000)
+// Bit 31:24 RW, mg_ysu3, Quantized value 3 in vertical curve adaptive calculation
+// Bit 23:16 RW, mg_ysu2, Quantized value 2 in vertical curve adaptive calculation
+// Bit 15:8 RW, mg_ysu1, Quantized value 1 in vertical curve adaptive calculation
+// Bit 7:0 RW, mg_ysu0, Quantized value 0 in vertical curve adaptive calculation
+#define D2D3_MBDG_PARAM_5 ((0x2b1e << 2) + 0xff000000)
+// Bit 31:24 RW, mg_xsu3, Quantized value 3 in horizontal curve adaptive calculation
+// Bit 23:16 RW, mg_xsu2, Quantized value 2 in horizontal curve adaptive calculation
+// Bit 15:8 RW, mg_xsu1, Quantized value 1 in horizontal curve adaptive calculation
+// Bit 7:0 RW, mg_xsu0, Quantized value 0 in horizontal curve adaptive calculation
+#define D2D3_MBDG_PARAM_6 ((0x2b1f << 2) + 0xff000000)
+// Bit 31:16 Reserved
+// Bit 15:8 RW, mg_xsu4, Quantized value 4 in horizontal curve adaptive calculation
+// Bit 7:0 RW, mg_ysu4, Quantized value 4 in vertical curve adaptive calculation
+#define D2D3_MBDG_PARAM_7 ((0x2b20 << 2) + 0xff000000)
+// Bit 31:28 RW, dbg_hscnt_sel see DBG_STATUS_2
+// Bit 27:25 Reserved
+// Bit 24 RW, dbg_dbr_en, 1 to enable debug mode in DBR
+// Bit 23:16 RW, dbg_force_data, Forced data in debug mode
+// Bit 15:12 RW, dbg_bld_ctrl, debug controller for DBLD
+// [12]:enable; [13]: 0 for passive mode, 0 for handshake mode
+// [15:14]: 0 for constant mode, 1 for step1 mode
+// Bit 11:8 RW, dbg_mg_ctrl, debug controller for MBDG
+// [8]:enable; [9]: 0 for passive mode, 0 for handshake mode
+// [11:10]: 0 for constant mode, 1 for step1 mode
+// Bit 7:4 RW, dbg_cg_ctrl, debug controller for CBDG
+// [4]:enable; [5]: 0 for passive mode, 0 for handshake mode
+// [7:6]: 0 for constant mode, 1 for step1 mode
+// Bit 3:0 RW, dbg_lg_ctrl, debug controller for LBDG
+// [0]:enable; [1]: 0 for passive mode, 0 for handshake mode
+// [3:2]: 0 for constant mode, 1 for step1 mode
+#define D2D3_DBG_CTRL ((0x2b23 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// DWMIF registers
+//------------------------------------------------------------------------------
+// Bit 31:18 Reserved
+// Bit 17 RW, dw_x_rev 0: Normal write data from left to right in horizontal
+// 1: Reversed write data from left to right in horizontal
+// Bit 16 RW, dw_y_rev 0: Normal write data from top to bottom in horizontal
+// 1: Reversed write data from bottom to top in horizontal
+// Bit 15 RW, dw_done_clr 1 to clear register depw_done (DWMIF_STATUS)
+// Bit 14 RW, dw_little_endian, 0: data is ordered in big-endian, 1: little endian
+// Bit 13:12 RW, dw_pic_struct, 0:read every line, 1:reserved, 2:read even line, 3:read odd line
+// Bit 11 RW, dw_urgent, urgent index
+// Bit 10 RW, dw_clr_wrrsp, 1:clear the write fifo counter
+// Bit 9 RW, dw_canvas_wr, canvas write initialization again
+// Bit 8 RW, dw_req_en, 1 to enable write request
+// Bit 7:0 RW, dw_canvas_index,Canvas index for the MSB of memory address for memory write
+#define D2D3_DWMIF_CTRL ((0x2b24 << 2) + 0xff000000)
+// Bit 31 Reserved
+// Bit 30:16 RW, dw_end_x, Horizontal end position for memory write, count by BYTE
+// Bit 15 Reserved
+// Bit 14:0 RW, dw_start_x, Horizontal start position for memory write, count by BYTE
+#define D2D3_DWMIF_HPOS ((0x2b25 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, dw_end_y, Vertical end position for memory write, count by BYTE
+// Bit 15:13 Reserved
+// Bit 12:0 RW, dw_start_y, Vertical start position for memory write, count by BYTE
+#define D2D3_DWMIF_VPOS ((0x2b26 << 2) + 0xff000000)
+// Bit 31:28 Reserved
+// Bit 27:16 RW, dw_vsizem1, Vertical size for memory write, equal the size minus 1
+// Bit 15:12 Reserved
+// Bit 11:0 RW, dw_hsizem1, Horizontal size for memory write, equal the size minus 1
+#define D2D3_DWMIF_SIZE ((0x2b27 << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// DRMIF registers
+//------------------------------------------------------------------------------
+// Bit 31:18 Reserved
+// Bit 17 RW, dr_y_rev, 0: Normal Read data from top to bottom in horizontal
+// 1: Reversed read data from bottom to top in horizontal
+// Bit 16 RW, dr_x_rev, 0: Normal Read data from left to right in horizontal
+// 1: Reversed read data from right to left in horizontal
+// Bit 15 RW, dr_clr_fifo_error, 1 to clear the overflow flag of the sticky FIFO
+// Bit 14 RW, dr_little_endian, 0: data is ordered in big-endian; 1: little-endian
+// Bit 13:12 RW, dr_pic_struct, 0: progressive; 1: Reserved;
+// 2: interlaced, even line; 3: interlaced, odd line
+// Bit 11 RW, dr_urgent, urgent index, no use in this system
+// Bit 10:9 RW, dr_burst_size, Burst read length for each request; 0=24,1=32,2=48,3=64
+// Bit 8 RW, dr_req_en, 1 to enable read request
+// Bit 7:0 RW, dr_canvas_index, Canvas index for the MSB of memory address for memory read
+#define D2D3_DRMIF_CTRL ((0x2b28 << 2) + 0xff000000)
+// Bit 31 Reserved
+// Bit 30:16 RW, dr_end_x, Horizontal end position for memory read, count by BYTE
+// Bit 15 Reserved
+// Bit 14:0 RW, dr_start_x, Horizontal start position for memory read, count by BYTE
+#define D2D3_DRMIF_HPOS ((0x2b29 << 2) + 0xff000000)
+// Bit 31:29 Reserved
+// Bit 28:16 RW, dr_end_y, Vertical end position for memory read, count by BYTE
+// Bit 15:13 Reserved
+// Bit 12:0 RW, dr_start_y, Vertical start position for memory read, count by BYTE
+#define D2D3_DRMIF_VPOS ((0x2b2a << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// PDR registers
+// ddd: parallax based render
+//------------------------------------------------------------------------------
+// Bit 31:8 Reserved
+// Bit 7 RW, ddd_brdlpf_en, 1 to enable the smooth filter on the depth around the boundary
+// Bit 6 RW, ddd_extn_black, 1 to enable the function to fill black colour when interpolated pixels is outside the picture in DBR
+// Bit 5 RW, ddd_wrap_en, Reserved
+// Bit 4 RW, ddd_hhalf, 1 to indicate the left/right line length is a half of original line.
+// Bit 3:2 RW, ddd_out_mode, Reserved
+// Bit 1:0 RW, ddd_lomode, wrap & pbr interleave mode:
+// 2'b0x: whole line is left or right;
+// 2'b10: d2p_lar=1(D2P_PARAM_1), rlrlrlrl inteleave in one line,
+// d2p_lar=0(D2P_PARAM_1), lrlrlrlr inteleave in one line,
+// 2'b11: d2p_lar=1(D2P_PARAM_1), rrrrr-lllll, half line is right, another half is left,
+// d2p_lar=0(D2P_PARAM_1), lllll-rrrrr, half line is left, another half is right,
+#define D2D3_DBR_DDD_CTRL ((0x2b2c << 2) + 0xff000000)
+// Bit 31:0 RW, ddd_dbg_ctrl, no use
+#define D2D3_DBR_DDD_DBG ((0x2b2d << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// LRDMX registers
+//------------------------------------------------------------------------------
+// Bit 31:9 Reserved
+// Bit 8 RW, lr_merge, 1: all the left/right input go to the left channel output
+// Bit 7:6 RW, lrd_ff0_sel, FF0 source selector
+// 0:from left input; 1:from right input; 2:from FF0; 3:no used
+// Bit 5:4 RW, lrd_ff1_sel, FF1 source selector
+// 0:from left input; 1:from right input; 2:from FF0; 3:no used
+// Bit 3:2 RW, lrd_lout_sel, left channel DEMUX
+// 00: ff0 01:ff1 10: left input 11:right input
+// Bit 1:0 RW, lrd_rout_sel, right channel DEMUX
+// 00: ff1 01:ff0 10: left input 11:right input
+#define D2D3_DBR_LRDMX_CTRL ((0x2b2f << 2) + 0xff000000)
+//------------------------------------------------------------------------------
+// Read Only registers
+//------------------------------------------------------------------------------
+// Bit 31:24 RO, ro_cg_vprel, vanish point's reliability in CBDG
+// Bit 23:12 RO, ro_cg_vpx, vanish point's X-Axis in CBDG
+// Bit 11:0 RO, ro_cg_vpy, vanish point's Y-Axis in CBDG
+#define D2D3_CBDG_STATUS_1 ((0x2b30 << 2) + 0xff000000)
+// Bit 31:24 RO, ro_mg_cx[7:0], X-Axis of point C in horizontal curve in MBDG
+// Bit 23:16 RO, ro_mg_ux, Depth value of point U in horizontal curve in MBDG
+// Bit 15:8 RO, ro_mg_dx, Depth value of point D in horizontal curve in MBDG
+// Bit 7:0 RO, ro_mg_minx, Depth value of point C in horizontal curve in MBDG
+#define D2D3_MBDG_STATUS_1 ((0x2b31 << 2) + 0xff000000)
+// Bit 31:24 RO, ro_mg_cy[7:0], X-Axis of point C in vertical curve in MBDG
+// Bit 23:16 RO, ro_mg_uy, Depth value of point U in vertical curve in MBDG
+// Bit 15:8 RO, ro_mg_dy, Depth value of point D in vertical curve in MBDG
+// Bit 7:0 RO, ro_mg_miny, Depth value of point C in vertical curve in MBDG
+#define D2D3_MBDG_STATUS_2 ((0x2b32 << 2) + 0xff000000)
+// Bit 31 RO, ro_wrap_status, 1 indicate the D2P_WRAP is busy to perform the initialization
+// Bit 30:8 Reserved
+// Bit 7:4 RO, ro_mg_cy[11:8], X-Axis of point C in vertical curve in MBDG
+// Bit 3:0 RO, ro_mg_cx[11:8], X-Axis of point C in horizontal curve in MBDG
+#define D2D3_MBDG_STATUS_3 ((0x2b33 << 2) + 0xff000000)
+// Bit 31:21 Reserved
+// Bit 20:0 RO, ro_mg_sum_u, ACT(top): activities of the top part
+#define D2D3_MBDG_STATUS_4 ((0x2b34 << 2) + 0xff000000)
+// Bit 31:21 Reserved
+// Bit 20:0 RO, ro_mg_sum_d, ACT(bottom): activities of the bottom part
+#define D2D3_MBDG_STATUS_5 ((0x2b35 << 2) + 0xff000000)
+// Bit 31:21 Reserved
+// Bit 20:0 RO, ro_mg_sum_l, ACT(left): activities of the left part
+#define D2D3_MBDG_STATUS_6 ((0x2b36 << 2) + 0xff000000)
+// Bit 31:21 Reserved
+// Bit 20:0 RO, ro_mg_sum_r, ACT(right): activities of the right part
+#define D2D3_MBDG_STATUS_7 ((0x2b37 << 2) + 0xff000000)
+// Bit 31:0 dbg_handshake_ro0, handshake signal for debug, internal srdy and rrdy
+#define D2D3_DBG_STATUS_1 ((0x2b38 << 2) + 0xff000000)
+// Bit 31:0 dbg_hscnt, dbg_hscnt_sel == 4'h0, output lg hscnt
+// dbg_hscnt_sel == 4'h1, output cg hscnt
+// dbg_hscnt_sel == 4'h2, output mg hscnt
+// dbg_hscnt_sel == 4'h3, output bld hscnt
+// dbg_hscnt_sel == other value, output 32'h0
+#define D2D3_DBG_STATUS_2 ((0x2b39 << 2) + 0xff000000)
+// Bit 31:0 RO, drmif_status, drmif module internal status
+#define D2D3_DRMIF_STATUS ((0x2b3a << 2) + 0xff000000)
+// Bit 31:2 RO, Reserved
+// Bit 1:0 RO, d2d3_status0, [1]: depw_done, one field depth write to ddr has done
+// [0]: dwmif_pending_ddr_wrrsp, 1 to indicate write response from ddr
+#define D2D3_DWMIF_STATUS ((0x2b3b << 2) + 0xff000000)
+// Bit 31:24 Reserved
+// Bit 23:0 RO, ro_meet_sum, register sumxy_sum_dbg in CBDG
+#define D2D3_CBDG_STATUS_2 ((0x2b3c << 2) + 0xff000000)
+// Bit 31:20 Reserved
+// Bit 19:0 RO, ro_hist_depth,
+#define D2D3_DBLD_STATUS ((0x2b3d << 2) + 0xff000000)
+// Bit 31:0 Reserved
+#define D2D3_RESEV_STATUS1 ((0x2b3e << 2) + 0xff000000)
+// Bit 31:0 Reserved
+#define D2D3_RESEV_STATUS2 ((0x2b3f << 2) + 0xff000000)
+//
+// Closing file: d2d3_regs.h
+//
+//===========================================================================
+// MIPI DSI Host Controller (16'h2c00 - 16'h2cff)
+//===========================================================================
+//`include "dsi_regs.h"
+//===========================================================================
+// ISP register (16'h2d00 - 16'h2dff)
+//===========================================================================
+//`include "isp_reg.h"
+//===========================================================================
+//===========================================================================
+//
+// Reading file: vpu_dnr_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: MADB_VCBUS_BASE = 0x2d
+// -----------------------------------------------
+#define DNR_CTRL ((0x2d00 << 2) + 0xff000000)
+//Bit 31:17, reserved
+//Bit 16, reg_dnr_en , dnr enable . unsigned , default = 1
+//Bit 15, reg_dnr_db_vdbstep , vdb step, 0: 4, 1: 8 . unsigned , default = 1
+//Bit 14, reg_dnr_db_vdbprten , vdb protectoin enable . unsigned , default = 1
+//Bit 13, reg_dnr_gbs_difen , enable dif (between LR and LL/RR) condition for gbs stat.. unsigned , default = 0
+//Bit 12, reg_dnr_luma_en , enable ycbcr2luma module . unsigned , default = 1
+//Bit 11:10, reg_dnr_db_mod , deblocking mode, 0: disable, 1: horizontal deblocking, 2: vertical deblocking, 3: horizontal & vertical deblocking. unsigned , default = 3
+//Bit 9, reg_dnr_db_chrmen , enable chroma deblocking . unsigned , default = 1
+//Bit 8, reg_dnr_hvdif_mod , 0: calc. difs by original Y, 1: by new luma. unsigned , default = 1
+//Bit 7, reserved
+//Bit 6: 4, reg_dnr_demo_lften , b0: Y b1:U b2:V . unsigned , default = 7
+//Bit 3, reserved
+//Bit 2: 0, reg_dnr_demo_rgten , b0: Y b1:U b2:V . unsigned , default = 7
+#define DNR_HVSIZE ((0x2d01 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_dnr_hsize , hsize . unsigned , default = 0
+//Bit 15:13, reserved
+//Bit 12: 0, reg_dnr_vsize , vsize . unsigned , default = 0
+#define DNR_DBLK_BLANK_NUM ((0x2d02 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_dblk_hblank_num , deblock hor blank num . unsigned , default = 16
+//Bit 7: 0, reg_dblk_vblank_num , deblock ver blank num . unsigned , default = 45
+#define DNR_BLK_OFFST ((0x2d03 << 2) + 0xff000000)
+//Bit 31: 7, reserved
+//Bit 6: 4, reg_dnr_hbofst , horizontal block offset may provide by software calc.. unsigned , default = 0
+//Bit 3, reserved
+//Bit 2: 0, reg_dnr_vbofst , vertical block offset may provide by software calc.. unsigned , default = 0
+#define DNR_GBS ((0x2d04 << 2) + 0xff000000)
+//Bit 31: 2, reserved
+//Bit 1: 0, reg_dnr_gbs , global block strength may update by software calc.. unsigned , default = 0
+#define DNR_HBOFFST_STAT ((0x2d05 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_hbof_difthd , dif threshold (>=) between LR and LL/RR. unsigned , default = 2
+//Bit 23:16, reg_dnr_hbof_edgethd , edge threshold (<=) for LR . unsigned , default = 32
+//Bit 15: 8, reg_dnr_hbof_flatthd , flat threshold (>=) for LR . unsigned , default = 0
+//Bit 7, reserved
+//Bit 6: 4, reg_dnr_hbof_delta , delta for weighted bin accumulator. unsigned , default = 1
+//Bit 3, reserved
+//Bit 2: 0, reg_dnr_hbof_statmod , statistic mode for horizontal block offset, 0: count flags for 8-bin, 1: count LRs for 8-bin, 2: count difs for 8-bin, 3: count weighted flags for 8-bin, 4: count flags for first 32-bin, 5: count LRs for first 32-bin, 6 or 7: count difs for first 32-bin. unsigned , default = 2
+#define DNR_VBOFFST_STAT ((0x2d06 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_vbof_difthd , dif threshold (>=) between Up and Dw. unsigned , default = 1
+//Bit 23:16, reg_dnr_vbof_edgethd , edge threshold (<=) for Up/Dw. unsigned , default = 16
+//Bit 15: 8, reg_dnr_vbof_flatthd , flat threshold (>=) for Up/Dw. unsigned , default = 0
+//Bit 7, reserved
+//Bit 6: 4, reg_dnr_vbof_delta , delta for weighted bin accumulator. unsigned , default = 1
+//Bit 3, reserved
+//Bit 2: 0, reg_dnr_vbof_statmod , statistic mode for vertical block offset, 0: count flags for 8-bin, 1: count Ups for 8-bin, 2: count difs for 8-bin, 3: count weighted flags for 8-bin, 4: count flags for first 32-bin, 5: count Ups for first 32-bin, 6 or 7: count difs for first 32-bin. unsigned , default = 2
+#define DNR_GBS_STAT ((0x2d07 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_gbs_edgethd , edge threshold (<=) for LR . unsigned , default = 32
+//Bit 23:16, reg_dnr_gbs_flatthd , flat threshold (>=) for LR . unsigned , default = 0
+//Bit 15: 8, reg_dnr_gbs_varthd , variation threshold (<=) for Lvar/Rvar. unsigned , default = 16
+//Bit 7: 0, reg_dnr_gbs_difthd , dif threshold (>=) between LR and LL/RR. unsigned , default = 2
+#define DNR_STAT_X_START_END ((0x2d08 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:16, reg_dnr_stat_xst . unsigned , default = 24
+//Bit 15:14, reserved
+//Bit 13: 0, reg_dnr_stat_xed . unsigned , default = HSIZE - 25
+#define DNR_STAT_Y_START_END ((0x2d09 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:16, reg_dnr_stat_yst . unsigned , default = 24
+//Bit 15:14, reserved
+//Bit 13: 0, reg_dnr_stat_yed . unsigned , default = VSIZE - 25
+#define DNR_LUMA ((0x2d0a << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:24, reg_dnr_luma_sqrtshft , left shift for fast squart of chroma, [0, 4]. unsigned , default = 2
+//Bit 23:21, reserved
+//Bit 20:16, reg_dnr_luma_sqrtoffst , offset for fast squart of chroma. signed , default = 0
+//Bit 15, reserved
+//Bit 14:12, reg_dnr_luma_wcmod , theta related to warm/cool segment line, 0: 0, 1: 45, 2: 90, 3: 135, 4: 180, 5: 225, 6: 270, 7: 315. . unsigned , default = 3
+//Bit 11: 8, reg_dnr_luma_cshft , shift for calc. delta part, 0~8, . unsigned , default = 8
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_dnr_luma_cgain , final gain for delta part, 32 normalized to "1". unsigned , default = 4
+#define DNR_DB_YEDGE_THD ((0x2d0b << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_db_yedgethd0 , edge threshold0 for luma . unsigned , default = 12
+//Bit 23:16, reg_dnr_db_yedgethd1 , edge threshold1 for luma . unsigned , default = 15
+//Bit 15: 8, reg_dnr_db_yedgethd2 , edge threshold2 for luma . unsigned , default = 18
+//Bit 7: 0, reg_dnr_db_yedgethd3 , edge threshold3 for luma . unsigned , default = 25
+#define DNR_DB_CEDGE_THD ((0x2d0c << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_db_cedgethd0 , edge threshold0 for chroma . unsigned , default = 12
+//Bit 23:16, reg_dnr_db_cedgethd1 , edge threshold1 for chroma . unsigned , default = 15
+//Bit 15: 8, reg_dnr_db_cedgethd2 , edge threshold2 for chroma . unsigned , default = 18
+//Bit 7: 0, reg_dnr_db_cedgethd3 , edge threshold3 for chroma . unsigned , default = 25
+#define DNR_DB_HGAP ((0x2d0d << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_dnr_db_hgapthd , horizontal gap thd (<=) for very sure blockiness . unsigned , default = 8
+//Bit 15: 8, reg_dnr_db_hgapdifthd , dif thd between hgap and lft/rgt hdifs. unsigned , default = 1
+//Bit 7: 1, reserved
+//Bit 0, reg_dnr_db_hgapmod , horizontal gap calc. mode, 0: just use current col x, 1: find max between (x-1, x, x+1) . unsigned , default = 0
+#define DNR_DB_HBS ((0x2d0e << 2) + 0xff000000)
+//Bit 31: 6, reserved
+//Bit 5: 4, reg_dnr_db_hbsup , horizontal bs up value . unsigned , default = 1
+//Bit 3: 2, reg_dnr_db_hbsmax , max value of hbs for global control. unsigned , default = 3
+//Bit 1: 0, reg_dnr_db_hgbsthd , gbs thd (>=) for hbs calc. . unsigned , default = 1
+#define DNR_DB_HACT ((0x2d0f << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_dnr_db_hactthd0 , thd0 of hact, for block classification. unsigned , default = 10
+//Bit 7: 0, reg_dnr_db_hactthd1 , thd1 of hact, for block classification. unsigned , default = 32
+#define DNR_DB_YHDELTA_GAIN ((0x2d10 << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:24, reg_dnr_db_yhdeltagain1 , (p1-q1) gain for Y's delta calc. when bs=1, normalized 8 as "1" . unsigned , default = 2
+//Bit 23, reserved
+//Bit 22:20, reg_dnr_db_yhdeltagain2 , (p1-q1) gain for Y's delta calc. when bs=2, normalized 8 as "1" . unsigned , default = 0
+//Bit 19, reserved
+//Bit 18:16, reg_dnr_db_yhdeltagain3 , (p1-q1) gain for Y's delta calc. when bs=3, normalized 8 as "1" . unsigned , default = 0
+//Bit 15, reserved
+//Bit 14: 8, reg_dnr_db_yhdeltaadjoffst , offset for adjust Y's hdelta (-64, 63). signed , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_dnr_db_yhdeltaadjgain , gain for adjust Y's hdelta, normalized 32 as "1" . unsigned , default = 32
+#define DNR_DB_YHDELTA2_GAIN ((0x2d11 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_dnr_db_yhdelta2gain2 , gain for bs=2's adjust Y's hdelta2, normalized 64 as "1" . unsigned , default = 8
+//Bit 23:21, reserved
+//Bit 20:16, reg_dnr_db_yhdelta2offst2 , offset for bs=2's adjust Y's hdelta2 (-16, 15). signed , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_dnr_db_yhdelta2gain3 , gain for bs=3's adjust Y's hdelta2, normalized 64 as "1" . unsigned , default = 4
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_db_yhdelta2offst3 , offset for bs=3's adjust Y's hdelta2 (-16, 15). signed , default = 0
+#define DNR_DB_CHDELTA_GAIN ((0x2d12 << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:24, reg_dnr_db_chdeltagain1 , (p1-q1) gain for UV's delta calc. when bs=1, normalized 8 as "1". unsigned , default = 2
+//Bit 23, reserved
+//Bit 22:20, reg_dnr_db_chdeltagain2 , (p1-q1) gain for UV's delta calc. when bs=2, normalized 8 as "1". unsigned , default = 0
+//Bit 19, reserved
+//Bit 18:16, reg_dnr_db_chdeltagain3 , (p1-q1) gain for UV's delta calc. when bs=3, normalized 8 as "1". unsigned , default = 0
+//Bit 15, reserved
+//Bit 14: 8, reg_dnr_db_chdeltaadjoffst , offset for adjust UV's hdelta (-64, 63). signed , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_dnr_db_chdeltaadjgain , gain for adjust UV's hdelta, normalized 32 as "1". unsigned , default = 32
+#define DNR_DB_CHDELTA2_GAIN ((0x2d13 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_dnr_db_chdelta2gain2 , gain for bs=2's adjust UV's hdelta2, normalized 64 as "1" . unsigned , default = 8
+//Bit 23:21, reserved
+//Bit 20:16, reg_dnr_db_chdelta2offst2 , offset for bs=2's adjust UV's hdelta2 (-16, 15). signed , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_dnr_db_chdelta2gain3 , gain for bs=2's adjust UV's hdelta2, normalized 64 as "1" . unsigned , default = 4
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_db_chdelta2offst3 , offset for bs=2's adjust UV's hdelta2 (-16, 15). signed , default = 0
+#define DNR_DB_YC_VEDGE_THD ((0x2d14 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_dnr_db_yvedgethd , special Y's edge thd for vdb. unsigned , default = 12
+//Bit 7: 0, reg_dnr_db_cvedgethd , special UV's edge thd for vdb. unsigned , default = 12
+#define DNR_DB_VBS_MISC ((0x2d15 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_db_vgapthd , vertical gap thd (<=) for very sure blockiness . unsigned , default = 8
+//Bit 23:16, reg_dnr_db_vactthd , thd of vact, for block classification . unsigned , default = 10
+//Bit 15: 8, reg_dnr_db_vgapdifthd , dif thd between vgap and vact. unsigned , default = 4
+//Bit 7: 4, reserved
+//Bit 3: 2, reg_dnr_db_vbsmax , max value of vbs for global control. unsigned , default = 2
+//Bit 1: 0, reg_dnr_db_vgbsthd , gbs thd (>=) for vbs calc. . unsigned , default = 1
+#define DNR_DB_YVDELTA_GAIN ((0x2d16 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_dnr_db_yvdeltaadjgain , gain for adjust Y's vdelta, normalized 32 as "1". unsigned , default = 32
+//Bit 23, reserved
+//Bit 22:16, reg_dnr_db_yvdeltaadjoffst , offset for adjust Y's vdelta (-64, 63). signed , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_dnr_db_yvdelta2gain , gain for adjust Y's vdelta2, normalized 64 as "1". unsigned , default = 8
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_db_yvdelta2offst , offset for adjust Y's vdelta2 (-16, 15). signed , default = 0
+#define DNR_DB_CVDELTA_GAIN ((0x2d17 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_dnr_db_cvdeltaadjgain , gain for adjust UV's vdelta, normalized 32 as "1". unsigned , default = 32
+//Bit 23, reserved
+//Bit 22:16, reg_dnr_db_cvdeltaadjoffst , offset for adjust UV's vdelta (-64, 63). signed , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_dnr_db_cvdelta2gain , gain for adjust UV's vdelta2, normalized 64 as "1". unsigned , default = 8
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_db_cvdelta2offst , offset for adjust UV's vdelta2 (-16, 15). signed , default = 0
+#define DNR_RO_GBS_STAT_LR ((0x2d18 << 2) + 0xff000000)
+//Bit 31: 0, ro_gbs_stat_lr . unsigned , default = 0
+#define DNR_RO_GBS_STAT_LL ((0x2d19 << 2) + 0xff000000)
+//Bit 31: 0, ro_gbs_stat_ll . unsigned , default = 0
+#define DNR_RO_GBS_STAT_RR ((0x2d1a << 2) + 0xff000000)
+//Bit 31: 0, ro_gbs_stat_rr . unsigned , default = 0
+#define DNR_RO_GBS_STAT_DIF ((0x2d1b << 2) + 0xff000000)
+//Bit 31: 0, ro_gbs_stat_dif . unsigned , default = 0
+#define DNR_RO_GBS_STAT_CNT ((0x2d1c << 2) + 0xff000000)
+//Bit 31: 0, ro_gbs_stat_cnt . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_0 ((0x2d1d << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt0 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_1 ((0x2d1e << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt1 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_2 ((0x2d1f << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt2 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_3 ((0x2d20 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt3 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_4 ((0x2d21 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt4 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_5 ((0x2d22 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt5 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_6 ((0x2d23 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt6 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_7 ((0x2d24 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt7 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_8 ((0x2d25 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt8 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_9 ((0x2d26 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt9 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_10 ((0x2d27 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt10 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_11 ((0x2d28 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt11 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_12 ((0x2d29 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt12 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_13 ((0x2d2a << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt13 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_14 ((0x2d2b << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt14 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_15 ((0x2d2c << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt15 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_16 ((0x2d2d << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt16 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_17 ((0x2d2e << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt17 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_18 ((0x2d2f << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt18 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_19 ((0x2d30 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt19 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_20 ((0x2d31 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt20 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_21 ((0x2d32 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt21 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_22 ((0x2d33 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt22 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_23 ((0x2d34 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt23 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_24 ((0x2d35 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt24 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_25 ((0x2d36 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt25 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_26 ((0x2d37 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt26 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_27 ((0x2d38 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt27 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_28 ((0x2d39 << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt28 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_29 ((0x2d3a << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt29 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_30 ((0x2d3b << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt30 . unsigned , default = 0
+#define DNR_RO_HBOF_STAT_CNT_31 ((0x2d3c << 2) + 0xff000000)
+//Bit 31: 0, ro_hbof_stat_cnt31 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_0 ((0x2d3d << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt0 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_1 ((0x2d3e << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt1 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_2 ((0x2d3f << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt2 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_3 ((0x2d40 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt3 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_4 ((0x2d41 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt4 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_5 ((0x2d42 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt5 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_6 ((0x2d43 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt6 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_7 ((0x2d44 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt7 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_8 ((0x2d45 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt8 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_9 ((0x2d46 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt9 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_10 ((0x2d47 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt10 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_11 ((0x2d48 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt11 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_12 ((0x2d49 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt12 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_13 ((0x2d4a << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt13 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_14 ((0x2d4b << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt14 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_15 ((0x2d4c << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt15 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_16 ((0x2d4d << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt16 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_17 ((0x2d4e << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt17 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_18 ((0x2d4f << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt18 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_19 ((0x2d50 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt19 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_20 ((0x2d51 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt20 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_21 ((0x2d52 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt21 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_22 ((0x2d53 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt22 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_23 ((0x2d54 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt23 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_24 ((0x2d55 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt24 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_25 ((0x2d56 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt25 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_26 ((0x2d57 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt26 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_27 ((0x2d58 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt27 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_28 ((0x2d59 << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt28 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_29 ((0x2d5a << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt29 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_30 ((0x2d5b << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt30 . unsigned , default = 0
+#define DNR_RO_VBOF_STAT_CNT_31 ((0x2d5c << 2) + 0xff000000)
+//Bit 31: 0, ro_vbof_stat_cnt31 . unsigned , default = 0
+#define DNR_DM_ADP_EN ((0x2d5d << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7 reg_dnr_scene_change_flg // unsigned , default = 1 , scence change flag for dnr(dm);
+//Bit 6 reg_dnr_dm_lpf_en // unsigned , default = 1 , enable lpf for demosquito filter
+//Bit 5 reg_dnr_dm_adp_level_en // unsigned , default = 1 , enable adptive demosquito level
+//Bit 4 reg_dnr_dm_flg2bdif_en // unsigned , default = 1 , enable edge flg to blkdif calc.
+//Bit 3: 2 reg_dnr_dm_edgeiir // unsigned , default = 1 , edge flag iir mode, 0: cur, 1: max(pre, cur), 2: choice 0/1 by org mtn, 3: choice 0/1 by ref mtn
+//Bit 1 reg_dnr_dm_dirdifmod // unsigned , default = 1 , dif mode for direction calc, 0: abs(dif02), 1: (abs(dif01)+abs(dif21))/2
+//Bit 0 reg_dnr_dm_sur_dir_mod // unsigned , default = 0 , sure direction mode for cordif calc.
+#define DNR_DM_EDGE_DIR ((0x2d5e << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_dnr_dm_dirdifcor // unsigned , default = 2 , dif coring threshold for direction calc
+//Bit 15: 8 reg_dnr_dm_edgecordifthd // unsigned , default = 160 , edge flg down when cordif is large than threshold
+//Bit 7: 0 reg_dnr_dm_mtnrt // unsigned , default = 60 , motion ratio for mtn decision
+#define DNR_DM_CTRL ((0x2d60 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12, reg_dnr_dm_fedgeflg_en , enable edge flag calc. of each frame. unsigned , default = 1
+//Bit 11, reg_dnr_dm_fedgeflg_cl , clear frame edge flag if needed. unsigned , default = 1
+//Bit 10, reg_dnr_dm_fedgeflg_df , user defined edge when reg_dnr_dm_fedgeflg_en=0, default = 1
+//Bit 9, reg_dnr_dm_en , enable demosquito function . unsigned , default = 1
+//Bit 8, reg_dnr_dm_chrmen , enable chrome processing for demosquito. unsigned , default = 1
+//Bit 7: 6, reg_dnr_dm_level , demosquito level . unsigned , default = 3
+//Bit 5: 4, reg_dnr_dm_leveldw0 , level down when gbs is small. unsigned , default = 1
+//Bit 3: 2, reg_dnr_dm_leveldw1 , level down for no edge/flat blocks. unsigned , default = 1
+//Bit 1: 0, reg_dnr_dm_gbsthd , small/large threshold for gbs (<=). unsigned , default = 0
+#define DNR_DM_NR_BLND ((0x2d61 << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24, reg_dnr_dm_defalpen , enable user define alpha for dm & nr blend. unsigned , default = 0
+//Bit 23:16, reg_dnr_dm_defalp , user define alpha for dm & nr blend if enable. unsigned , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_dnr_dm_alpgain , gain for nr/dm alpha, normalized 32 as "1". unsigned , default = 32
+//Bit 7: 0, reg_dnr_dm_alpoffst , (-128, 127), offset for nr/dm alpha. signed , default = 0
+#define DNR_DM_RNG_THD ((0x2d62 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_dnr_dm_rngminthd . unsigned , default = 2
+//Bit 15: 8, reg_dnr_dm_rngmaxthd . unsigned , default = 64
+//Bit 7: 0, reg_dnr_dm_rngdifthd . unsigned , default = 4
+#define DNR_DM_RNG_GAIN_OFST ((0x2d63 << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13: 8, reg_dnr_dm_rnggain , normalized 16 as "1" . unsigned , default = 16
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_dnr_dm_rngofst . unsigned , default = 0
+#define DNR_DM_DIR_MISC ((0x2d64 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29, reg_dnr_dm_diralpen . unsigned , default = 1
+//Bit 28:24, reg_dnr_dm_diralpgain . unsigned , default = 0
+//Bit 23:22, reserved
+//Bit 21:16, reg_dnr_dm_diralpofst . unsigned , default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_diralpmin . unsigned , default = 0
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_diralpmax . unsigned , default = 31
+#define DNR_DM_COR_DIF ((0x2d65 << 2) + 0xff000000)
+//Bit 31: 4, reserved
+//Bit 3: 1, reg_dnr_dm_cordifshft . unsigned , default = 3
+//Bit 0, reg_dnr_dm_cordifmod , 0:use max dir dif as cordif, 1: use max3x3 - min3x3 as cordif. unsigned , default = 1
+#define DNR_DM_FLT_THD ((0x2d66 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_dm_fltthd00 , block flat threshold0 for block average difference when gbs is small, for flat block detection. unsigned , default = 4
+//Bit 23:16, reg_dnr_dm_fltthd01 , block flat threshold1 for block average difference when gbs is small, for flat block detection. unsigned , default = 6
+//Bit 15: 8, reg_dnr_dm_fltthd10 , block flat threshold0 for block average difference when gbs is large, for flat block detection. unsigned , default = 9
+//Bit 7: 0, reg_dnr_dm_fltthd11 , block flat threshold1 for block average difference when gbs is large, for flat block detection. unsigned , default = 12
+#define DNR_DM_VAR_THD ((0x2d67 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_dm_varthd00 , block variance threshold0 (>=) when gbs is small, for flat block detection. unsigned , default = 2
+//Bit 23:16, reg_dnr_dm_varthd01 , block variance threshold1 (<=) when gbs is small, for flat block detection. unsigned , default = 15
+//Bit 15: 8, reg_dnr_dm_varthd10 , block variance threshold0 (>=) when gbs is large, for flat block detection. unsigned , default = 3
+//Bit 7: 0, reg_dnr_dm_varthd11 , block variance threshold1 (<=) when gbs is large, for flat block detection. unsigned , default = 24
+#define DNR_DM_EDGE_DIF_THD ((0x2d68 << 2) + 0xff000000)
+//Bit 31:24, reg_dnr_dm_edgethd0 , block edge threshold (<=) when gbs is small, for flat block detection. unsigned , default = 32
+//Bit 23:16, reg_dnr_dm_edgethd1 , block edge threshold (<=) when gbs is large, for flat block detection. unsigned , default = 48
+//Bit 15: 8, reg_dnr_dm_difthd0 , block dif threshold (<=) when gbs is small, for flat block detection. unsigned , default = 48
+//Bit 7: 0, reg_dnr_dm_difthd1 , block dif threshold (<=) when gbs is large, for flat block detection. unsigned , default = 64
+#define DNR_DM_AVG_THD ((0x2d69 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_dnr_dm_avgthd0 , block average threshold (>=), for flat block detection. unsigned , default = 160
+//Bit 7: 0, reg_dnr_dm_avgthd1 , block average threshold (<=), for flat block detection. unsigned , default = 128
+#define DNR_DM_AVG_VAR_DIF_THD ((0x2d6a << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_dnr_dm_avgdifthd , block average dif threshold (<) between cur and up block, for flat block detection. unsigned , default = 12
+//Bit 7: 0, reg_dnr_dm_vardifthd , block variance dif threshold (>=) between cur and up block, for flat block detection. unsigned , default = 1
+#define DNR_DM_VAR_EDGE_DIF_THD2 ((0x2d6b << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_dnr_dm_varthd2 , block variance threshold (>=), for edge block detection. unsigned , default = 24
+//Bit 15: 8, reg_dnr_dm_edgethd2 , block edge threshold (>=), for edge block detection. unsigned , default = 40
+//Bit 7: 0, reg_dnr_dm_difthd2 , block dif threshold (>=), for edge block detection. unsigned , default = 80
+#define DNR_DM_DIF_FLT_MISC ((0x2d6c << 2) + 0xff000000)
+//Bit 31:28, reg_dnr_dm_ldifoob , pre-defined large dif when pixel out of blocks. unsigned , default = 0
+//Bit 27:24, reg_dnr_dm_bdifoob , pre-defined block dif when pixel out of blocks;. unsigned , default = 0
+//Bit 23:16, reg_dnr_dm_fltalp , pre-defined alpha for dm and nr blending, when block is flat with mos.. unsigned , default = 200
+//Bit 15:12, reserved
+//Bit 11: 8, reg_dnr_dm_fltminbdif , pre-defined min block dif for dm filter, when block is flat with mos.. unsigned , default = 12
+//Bit 7, reserved
+//Bit 6: 2, reg_dnr_dm_difnormgain , gain for pixel dif normalization for dm filter, normalized 16 as "1". unsigned , default = 16
+//Bit 1, reg_dnr_dm_difnormen , enable pixel dif normalization for dm filter. unsigned , default = 1
+//Bit 0, reg_dnr_dm_difupden , enable block dif update using max of left, cur, right difs. unsigned , default = 0
+#define DNR_DM_SDIF_LUT0_2 ((0x2d6d << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_sdiflut0 , normally 0-16 . unsigned , default = 16
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_sdiflut1 , normally 0-16 . unsigned , default = 14
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_sdiflut2 , normally 0-16 . unsigned , default = 13
+#define DNR_DM_SDIF_LUT3_5 ((0x2d6e << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_sdiflut3 , normally 0-16 . unsigned , default = 10
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_sdiflut4 , normally 0-16 . unsigned , default = 7
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_sdiflut5 , normally 0-16 . unsigned , default = 5
+#define DNR_DM_SDIF_LUT6_8 ((0x2d6f << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_sdiflut6 , normally 0-16 . unsigned , default = 3
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_sdiflut7 , normally 0-16 . unsigned , default = 1
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_sdiflut8 , normally 0-16 . unsigned , default = 0
+#define DNR_DM_LDIF_LUT0_2 ((0x2d70 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_ldiflut0 , normally 0-16 . unsigned , default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_ldiflut1 , normally 0-16 . unsigned , default = 4
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_ldiflut2 , normally 0-16 . unsigned , default = 12
+#define DNR_DM_LDIF_LUT3_5 ((0x2d71 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_ldiflut3 , normally 0-16 . unsigned , default = 14
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_ldiflut4 , normally 0-16 . unsigned , default = 15
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_ldiflut5 , normally 0-16 . unsigned , default = 16
+#define DNR_DM_LDIF_LUT6_8 ((0x2d72 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_ldiflut6 , normally 0-16 . unsigned , default = 16
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_ldiflut7 , normally 0-16 . unsigned , default = 16
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_ldiflut8 , normally 0-16 . unsigned , default = 16
+#define DNR_DM_DIF2NORM_LUT0_2 ((0x2d73 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_dif2normlut0 , normally 0-16 . unsigned , default = 16
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_dif2normlut1 , normally 0-16 . unsigned , default = 5
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_dif2normlut2 , normally 0-16 . unsigned , default = 3
+#define DNR_DM_DIF2NORM_LUT3_5 ((0x2d74 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_dif2normlut3 , normally 0-16 . unsigned , default = 2
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_dif2normlut4 , normally 0-16 . unsigned , default = 2
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_dif2normlut5 , normally 0-16 . unsigned , default = 1
+#define DNR_DM_DIF2NORM_LUT6_8 ((0x2d75 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_dnr_dm_dif2normlut6 , normally 0-16 . unsigned , default = 1
+//Bit 15:13, reserved
+//Bit 12: 8, reg_dnr_dm_dif2normlut7 , normally 0-16 . unsigned , default = 1
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_dnr_dm_dif2normlut8 , normally 0-16 . unsigned , default = 1
+#define DNR_DM_GMS_THD ((0x2d76 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_gms_stat_thd0 . unsigned , default = 0
+//Bit 7: 0, reg_gms_stat_thd1 . unsigned , default = 128
+#define DNR_RO_DM_GMS_STAT_CNT ((0x2d77 << 2) + 0xff000000)
+//Bit 31: 0, ro_dm_gms_stat_cnt . unsigned , default = 0
+#define DNR_RO_DM_GMS_STAT_MS ((0x2d78 << 2) + 0xff000000)
+//Bit 31: 0, ro_dm_gms_stat_ms . unsigned , default = 0
+#define DNR_DM_EDGE_GAIN ((0x2d79 << 2) + 0xff000000)
+//Bit 31:24 reg_dnr_dm_alpedgegain0 // unsigned , default = 8 , edge based gain for alpha, normalized 16 as "1"
+//Bit 23:16 reg_dnr_dm_alpedgegain1 // unsigned , default = 16 , edge based gain for alpha, normalized 16 as "1"
+//Bit 15: 8 reg_dnr_dm_alpedgegain2 // unsigned , default = 24 , edge based gain for alpha, normalized 16 as "1"
+//Bit 7: 0 reg_dnr_dm_alpedgegain3 // unsigned , default = 32 , edge based gain for alpha, normalized 16 as "1"
+#define DNR_DM_FLG_BDIF ((0x2d7a << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:24 reg_dnr_dm_flg2bdif0 // unsigned , default = 0 , (0-16), edge flg to blkdif calc.
+//Bit 23:21 reserved
+//Bit 20:16 reg_dnr_dm_flg2bdif1 // unsigned , default = 6 , (0-16), edge flg to blkdif calc.
+//Bit 15:13 reserved
+//Bit 12: 8 reg_dnr_dm_flg2bdif2 // unsigned , default = 10 , (0-16), edge flg to blkdif calc.
+//Bit 7: 5 reserved
+//Bit 4: 0 reg_dnr_dm_flg2bdif3 // unsigned , default = 12 , (0-16), edge flg to blkdif calc.
+#define DNR_DM_GBS_RORM ((0x2d7b << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15:12 reg_dnr_dm_gbs4difnorm0 // unsigned , default = 0 , gbs=0 for dif norm calc.
+//Bit 11: 8 reg_dnr_dm_gbs4difnorm1 // unsigned , default = 1 , gbs=1 for dif norm calc.
+//Bit 7: 4 reg_dnr_dm_gbs4difnorm2 // unsigned , default = 4 , gbs=2 for dif norm calc.
+//Bit 3: 0 reg_dnr_dm_gbs4difnorm3 // unsigned , default = 6 , gbs=3 for dif norm calc.
+#define DNR_DM_FLG_LEV ((0x2d7c << 2) + 0xff000000)
+//Bit 31:14 reserved
+//Bit 13:12 reg_dnr_dm_flg2lev0 // unsigned , default = 1 , edge flg to filter level calc.
+//Bit 11:10 reserved
+//Bit 9: 8 reg_dnr_dm_flg2lev1 // unsigned , default = 3 , edge flg to filter level calc.
+//Bit 7: 6 reserved
+//Bit 5: 4 reg_dnr_dm_flg2lev2 // unsigned , default = 3 , edge flg to filter level calc.
+//Bit 3: 2 reserved
+//Bit 1: 0 reg_dnr_dm_flg2lev3 // unsigned , default = 3 , edge flg to filter level calc.
+#define DNR_DM_DIF_FLG_TH ((0x2d7d << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_dnr_dm_dif2flgthd1 // unsigned , default = 128 , dif to edge flg threshold 1
+//Bit 7: 0 reg_dnr_dm_dif2flgthd2 // unsigned , default = 192 , dif to edge flg threshold 2
+#define DNR_DM_CALP_GAIN_OFST ((0x2d7e << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:16 reg_dnr_dm_calpgain // unsigned , default = 16 , chroma gain for nr/dm alpha, normalized 32 as "1"
+//Bit 15: 9 reserved
+//Bit 8: 0 reg_dnr_dm_calpoffst // signed , default = -64 , (-255, 255), chroma offset for nr/dm alpha
+// 0x80-0x90
+//
+// Reading file: vpu_decomb_regs.h
+//
+ // defined registers
+#define DECOMB_DET_VERT_CON0 ((0x2d80 << 2) + 0xff000000)
+//Bit 31:24 reg_di_dcmb_det_vcon_thd0 default = 60 // u8
+//Bit 23:16 reg_di_dcmb_det_vcon_thd1 default = 80 // u8
+//Bit 15: 8 reg_di_dcmb_det_valp_lmt0 default = 63 // u8
+//Bit 7: 0 reg_di_dcmb_det_valp_lmt1 default = 4 // u8
+#define DECOMB_DET_VERT_CON1 ((0x2d81 << 2) + 0xff000000)
+//Bit 23:16 reg_di_dcmb_det_valp_lmt2 default = 0 // u8
+//Bit 15: 8 reg_di_dcmb_det_vrate0 default = 32 // u8
+//Bit 7: 0 reg_di_dcmb_det_vrate1 default = 4 // u8
+#define DECOMB_DET_EDGE_CON0 ((0x2d82 << 2) + 0xff000000)
+//Bit 31:24 reg_di_dcmb_det_econ_thd0 default = 60 // u8
+//Bit 23:16 reg_di_dcmb_det_econ_thd1 default = 80 // u8
+//Bit 15: 8 reg_di_dcmb_det_ealp_lmt0 default = 63 // u8
+//Bit 7: 0 reg_di_dcmb_det_ealp_lmt1 default = 4 // u8
+#define DECOMB_DET_EDGE_CON1 ((0x2d83 << 2) + 0xff000000)
+//Bit 23:16 reg_di_dcmb_det_ealp_lmt2 default = 0 // u8
+//Bit 15: 8 reg_di_dcmb_det_erate0 default = 32 // u8
+//Bit 7: 0 reg_di_dcmb_det_erate1 default = 4 // u8
+#define DECOMB_PARA ((0x2d84 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:28 reg_di_dcmb_cmb_lpf default = 1 // u2, 0:no lpf, 1:[1 2 1], 2,3: [1 2 2 2 1]
+//Bit 27:26 reg_di_dcmb_vedge_chk default = 0 // u2, vertical edge check, 0: no check, 1: vrt!=0, 2: vrt==3
+//Bit 25:24 reg_di_dcmb_nedge_chk default = 0 // u2, no idea edge check, 0, no check, 1, check
+//Bit 23:20 reg_di_dcmb_edge_min default = 0 // u4, min edge for edge cmb
+//Bit 19:16 reg_di_dcmb_edge_max default = 15 // u4, min edge for edge cmb
+//Bit 15:8 reg_di_dcmb_bld_alp default = 255 // u8, user defined alpha for di & decmb blend
+//Bit 7:0 reg_di_dcmb_bld_alp_beta default = 40 // u8, beta for mtn & cmb blend, for bld alpha calc.
+#define DECOMB_BLND_CON0 ((0x2d85 << 2) + 0xff000000)
+//Bit 31:24 reg_di_dcmb_bld_con_thd0 default = 100 // u8
+//Bit 23:16 reg_di_dcmb_bld_con_thd1 default = 120 // u8
+//Bit 15: 8 reg_di_dcmb_bld_alp_lmt0 default = 0 // u8
+//Bit 7: 0 reg_di_dcmb_bld_alp_lmt1 default = 128 // u8
+#define DECOMB_BLND_CON1 ((0x2d86 << 2) + 0xff000000)
+//Bit 23:16 reg_di_dcmb_bld_alp_lmt2 default = 255 // u8
+//Bit 15: 8 reg_di_dcmb_bld_rate0 default = 32 // u8
+//Bit 7: 0 reg_di_dcmb_bld_rate1 default = 32 // u8
+#define DECOMB_YC_THRD ((0x2d87 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_di_dcmb_ythd default = 2 // u8, default = 2
+//Bit 7: 0 reg_di_dcmb_cthd default = 2 // u8, default = 2
+#define DECOMB_MTN_GAIN_OFST ((0x2d88 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:16 reg_di_dcmb_mtn_alp_gain default = 16 // u6, 16 is normalized to '1'
+//Bit 15:9 reserved
+//Bit 8:0 reg_di_dcmb_mtn_alp_ofst default = 0 // s9, [-256, 255]
+#define DECOMB_CMB_SEL_GAIN_OFST ((0x2d89 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:16 reg_di_dcmb_cmb_sel_gain default = 48 // u6, 16 is normalized to '1'
+//Bit 15:9 reserved
+//Bit 8:0 reg_di_dcmb_cmb_sel_ofst default = 0 // s9, [-256, 255]
+#define DECOMB_WIND00 ((0x2d8a << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_di_dcmb_wnd00 default = 0 // u13, x0 for window 0, software control
+//Bit 15:13 reserved
+//Bit 12:0 reg_di_dcmb_wnd01 default = 719 // u13, x1 for window 0, HSIZE-1, software control
+#define DECOMB_WIND01 ((0x2d8b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_di_dcmb_wnd02 default = 0 // u13, y0 for window 0, software control
+//Bit 15:13 reserved
+//Bit 12:0 reg_di_dcmb_wnd03 default = 39 // u13, y1 for window 0, software control
+#define DECOMB_WIND10 ((0x2d8c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_di_dcmb_wnd10 default = 0 // u13, x0 for window 1, software control
+//Bit 15:13 reserved
+//Bit 12:0 reg_di_dcmb_wnd11 default = 719 // u13, x1 for window 1, HSIZE-1, software control
+#define DECOMB_WIND11 ((0x2d8d << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_di_dcmb_wnd12 default = 40 // u13, y0 for window 1, software control
+//Bit 15:13 reserved
+//Bit 12:0 reg_di_dcmb_wnd13 default = 239 // u13, y1 for window 1, VSIZE-1-40, software control
+#define DECOMB_MODE ((0x2d8e << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reg_di_dcmb_is_cmb_bef default = 1 // u1, 1: decide is_cmb before cmbing refine, 0: decide is_cmb after cmbing refine
+//Bit 14 reg_di_dcmb_en0 default = 1 // u1, enable decmobing for wind0
+//Bit 13 reg_di_dcmb_en1 default = 1 // u1, enable decmobing for wind1
+//Bit 12 reg_di_dcmb_en2 default = 1 // u1, enable decmobing for wind2
+//Bit 11:10 reg_di_dcmb_lpf_mod0 default = 2 // u2, get combing free pixels of wind0 by: 0, vertical lpf, 1, edge lpf, 2,3, ei data
+//Bit 9:8 reg_di_dcmb_lpf_mod1 default = 2 // u2, get combing free pixels of wind1 by: 0, vertical lpf, 1, edge lpf, 2,3, ei data
+//Bit 7:6 reg_di_dcmb_lpf_mod2 default = 0 // u2, get combing free pixels of wind2 by: 0, vertical lpf, 1, edge lpf, 2,3, ei data
+//Bit 5 reg_di_dcmb_cmb_sel0 default = 1 // u1, wind0 decmb based on: 0, vert cmb, 1, edge cmb
+//Bit 4 reg_di_dcmb_cmb_sel1 default = 1 // u1, wind1 decmb based on: 0, vert cmb, 1, edge cmb
+//Bit 3 reg_di_dcmb_cmb_sel2 default = 0 // u1, wind2 decmb based on: 0, vert cmb, 1, edge cmb
+//Bit 2 reg_di_dcmb_alp_mod0 default = 1 // u1, wind0 decmb alpha based on: 0, user-defined, 1, motion adaptive
+//Bit 1 reg_di_dcmb_alp_mod1 default = 1 // u1, wind1 decmb alpha based on: 0, user-defined, 1, motion adaptive
+//Bit 0 reg_di_dcmb_alp_mod2 default = 1 // u1, wind2 decmb alpha based on: 0, user-defined, 1, motion adaptive
+#define DECOMB_FRM_SIZE ((0x2d8f << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 hsize_in default = 1920 // u13, pic horz size in unit: pixel
+//Bit 15:13 reserved
+//Bit 12:0 vsize_in default = 1080 // u13, pic vert size in unit: pixel
+#define DECOMB_HV_BLANK ((0x2d90 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15:8 hblank_num default = 20 // u8, hor blank time
+//Bit 7:0 vblank_num default = 50 // u8, ver blank time
+//
+// Closing file: vpu_decomb_regs.h
+//
+// 0x98-0xa3
+//
+// Reading file: vpu_nr2_dpolar_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define NR2_POLAR3_MODE ((0x2d98 << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:18 reg_polar3_f02lpf_mod0 // unsigned , default = 3 low pass filter mode for field 0 and field2 before polar3 detection; 0 for no lpf, 1: [1 2 1]/4 vert lpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 no hlpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 [1 2 1]/4 hlpf
+//Bit 17:16 reg_polar3_f02lpf_mod1 // unsigned , default = 3 low pass filter mode for field 0 and field2 before polar3 detection; 0 for no lpf, 1: [1 2 1]/4 vert lpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 no hlpf; 2: [1 2 1; 2 4 2; 1 2 1]/16 2d lpf, p1 [1 2 1]/4 hlpf
+//Bit 15: 8 reg_polar3_dif02_thrd0 // unsigned , default = 5 threshold of dif for polar3 detection except for 32 detection, only do polar3 detection on obvious motion, [0] for luma, 1[1] for chroma
+//Bit 7: 0 reg_polar3_dif02_thrd1 // unsigned , default = 5 threshold of dif for polar3 detection except for 32 detection, only do polar3 detection on obvious motion, [0] for luma, 1[1] for chroma
+#define NR2_POLAR3_THRD ((0x2d99 << 2) + 0xff000000)
+//Bit 31:24 reg_polar3_txtf02_thrd0 // unsigned , default = 30 threshold to vertical f0f2 texture, if texture larger than this threshold, will not do the polar3 decision.
+//Bit 23:16 reg_polar3_txtf02_thrd1 // unsigned , default = 30 threshold to vertical f0f2 texture, if texture larger than this threshold, will not do the polar3 decision.
+//Bit 15: 8 reg_polar3_txtf1_thrd0 // unsigned , default = 20 threshold to vertical f1 texture, if texture larger than this threshold, will not do the polar3 decision.
+//Bit 7: 0 reg_polar3_txtf1_thrd1 // unsigned , default = 20 threshold to vertical f1 texture, if texture larger than this threshold, will not do the polar3 decision.
+#define NR2_POLAR3_PARA0 ((0x2d9a << 2) + 0xff000000)
+//Bit 31:28 reg_polar3_rate00 // unsigned , default = 6 delt = rate*dif02/32, e.g. f2<f0, if f1 within((f0+f2)/2 - delt), ((f0+f2)/2 + delt), then polar3_smoothmv++;
+//Bit 27:24 reg_polar3_rate01 // unsigned , default = 6 delt = rate*dif02/32, e.g. f2<f0, if f1 within((f0+f2)/2 - delt), ((f0+f2)/2 + delt), then polar3_smoothmv++;
+//Bit 23:20 reg_polar3_rate10 // unsigned , default = 8 delt = rate*dif02/32, e.g. f2-ofst1<f0, if f1<((f0+f2)/2 - delt), then polar3_m1++; if f1>((f0+f2)/2 + delt), then polar3_p1++;
+//Bit 19:16 reg_polar3_rate11 // unsigned , default = 8 delt = rate*dif02/32, e.g. f2-ofst1<f0, if f1<((f0+f2)/2 - delt), then polar3_m1++; if f1>((f0+f2)/2 + delt), then polar3_p1++;
+//Bit 15:12 reg_polar3_rate20 // unsigned , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset2), then polar3_m2++; if f1>((f0 + delt+ ofset2), then polar3_p2++;
+//Bit 11: 8 reg_polar3_rate21 // unsigned , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset2), then polar3_m2++; if f1>((f0 + delt+ ofset2), then polar3_p2++;
+//Bit 7: 1 reserved
+//Bit 0 reg_polar3_ro_reset // unsigned , default = 0 reset signal of the polar3 read only registers
+#define NR2_POLAR3_PARA1 ((0x2d9b << 2) + 0xff000000)
+//Bit 31:24 reg_polar3_rate30 // unsigned , default = 48 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset3) or f1>((f0 + delt+ofst3), then polar3_32++;
+//Bit 23:16 reg_polar3_rate31 // unsigned , default = 48 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset3) or f1>((f0 + delt+ofst3), then polar3_32++;
+//Bit 15:12 reg_polar3_ofst30 // signed , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt-ofst3) or f1>((f0 + delt+ofst3), then polar3_32++;
+//Bit 11: 8 reg_polar3_ofst31 // signed , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt-ofst3) or f1>((f0 + delt+ofst3), then polar3_32++;
+//Bit 7: 4 reg_polar3_ofst20 // signed , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset2), then polar3_m2++; if f1>((f0 + delt+ ofset2), then polar3_p2++;
+//Bit 3: 0 reg_polar3_ofst21 // signed , default = 2 delt = rate*dif02/32, e.g. f2<f0, if f1<(f2 - delt- ofset2), then polar3_m2++; if f1>((f0 + delt+ ofset2), then polar3_p2++;
+#define NR2_POLAR3_CTRL ((0x2d9c << 2) + 0xff000000)
+//Bit 31:24 reg_polar3_ofst10 // signed , default = 1
+//Bit 23:16 reg_polar3_ofst11 // signed , default = 1
+//Bit 15: 8 reg_polar3_h_mute // unsigned , default = 10 horizontal pixels to mute for left right sides for polar3 detection;
+//Bit 7: 0 reg_polar3_v_mute // unsigned , default = 10 vertical pixels to mute for top and bottom sides for polar3 detection;
+#define NR2_RO_POLAR3_NUMOFPIX ((0x2d9d << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_numofpix // unsigned , default = 0 number of pixels detected as polar3
+#define NR2_RO_POLAR3_SMOOTHMV ((0x2d9e << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_smoothmv // unsigned , default = 0 number of pixels with smooth mv, F(t) is close between avg of f(t-1) and f(t+1);
+#define NR2_RO_POLAR3_M1 ((0x2d9f << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_m1 // unsigned , default = 0 number of pixels with F(t) is close to f(t-1) instead of f(t+1), but in between [f(t-1), f(t+1)];
+#define NR2_RO_POLAR3_P1 ((0x2da0 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_p1 // unsigned , default = 0 number of pixels with F(t) is close to f(t+1) instead of f(t-1), but in between [f(t-1), f(t+1)];
+#define NR2_RO_POLAR3_M2 ((0x2da1 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_m2 // unsigned , default = 0 number of pixels with F(t) is close to f(t-1) instead of f(t+1), but out side of (f(t-1), f(t+1));
+#define NR2_RO_POLAR3_P2 ((0x2da2 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_p2 // unsigned , default = 0 number of pixels with F(t) is close to f(t+1) instead of f(t-1), but out side of (f(t-1), f(t+1));
+#define NR2_RO_POLAR3_32 ((0x2da3 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23: 0 ro_polar3_32 // unsigned , default = 0 number of pixels with F(t) far from [f(t-1),f(t+1)] and f(t-1) is close to f(t+1);
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_nr2_dpolar_regs.h
+//
+// 0xa4-0xf7 / 0xff
+//
+// Reading file: vpu_nr4_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//========== nr4_drt_regs register begin ==========//
+#define NR4_DRT_CTRL ((0x2da4 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_ydrt_3line_ssd_gain // unsigned , default = 16 gain to max ssd normalized 16 as '1'
+//Bit 23:16 reg_nr4_ydrt_5line_ssd_gain // unsigned , default = 16 gain to max ssd normalized 16 as '1'
+//Bit 15 reserved
+//Bit 14:13 reg_nr4_drt_yhsad_mode // unsigned , default = 1 mode for luma horiztonal sad calc., 0: no vertical lpf, 1: vertical [1 2 1], 2 or 3: vertical [ 1 2 2 2 1] if 5 lines
+//Bit 12:11 reg_nr4_drt_chsad_mode // unsigned , default = 1 mode for chroma horiztonal sad calc., 0: no vertical lpf, 1: vertical [1 2 1], 2 or 3: vertical [ 1 2 2 2 1] if 5 lines
+//Bit 10 reg_nr4_drt_yhsad_hlpf // unsigned , default = 1 hlpf for luma hsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf
+//Bit 9 reg_nr4_drt_yvsad_hlpf // unsigned , default = 1 hlpf for luma vsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf
+//Bit 8 reg_nr4_drt_ydsad_hlpf // unsigned , default = 1 hlpf for luma dsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf
+//Bit 7 reg_nr4_drt_chsad_hlpf // unsigned , default = 1 hlpf for chrome hsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf
+//Bit 6 reg_nr4_drt_cvsad_hlpf // unsigned , default = 1 hlpf for chroma vsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf
+//Bit 5 reg_nr4_drt_cdsad_hlpf // unsigned , default = 1 hlpf for chroma dsad of drt calculation, 0: no lpf, 1: with [1 2 1] hlpf
+//Bit 4 reg_nr4_ydrt_dif_mode // unsigned , default = 1 0:y_dif, 1: y_dif + (u_dif + v_dif)/2
+//Bit 3: 2 reg_nr4_cdrt_dif_mode // unsigned , default = 2 0:(u_dif + v_dif), 1: y_dif/4 + (u_dif + v_dif)*3/4, 2:y_dif/2 + (u_dif + v_dif)/2, 3: y_dif (not recommended)
+//Bit 1: 0 reserved
+#define NR4_DRT_YSAD_GAIN ((0x2da5 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_ysad_hrz_gain // unsigned , default = 16 gain for horizontal sad, 16 normalized to "1"
+//Bit 23:16 reg_nr4_ysad_diag_gain // unsigned , default = 20 gain for diagonal sad, 16 normalized to "1"
+//Bit 15: 8 reg_nr4_ysad_vrt_gain // unsigned , default = 16 gain for vertical sad, 16 normalized to "1"
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_drt_ysad_core_rate // unsigned , default = 6 rate of coring for sad(theta) - sad(theta+pi/2)*rate/64
+#define NR4_DRT_CSAD_GAIN ((0x2da6 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_csad_hrz_gain // unsigned , default = 16 gain for horizontal sad, 16 normalized to "1"
+//Bit 23:16 reg_nr4_csad_diag_gain // unsigned , default = 20 gain for diagonal sad, 16 normalized to "1"
+//Bit 15: 8 reg_nr4_csad_vrt_gain // unsigned , default = 16 gain for vertical sad, 16 normalized to "1"
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_drt_csad_core_rate // unsigned , default = 6 rate of coring for sad(theta) - sad(theta+pi/2)*rate/64
+#define NR4_DRT_SAD_ALP_CORE ((0x2da7 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:20 reg_nr4_ydrt_alp_core_rate // unsigned , default = 0 luma ratio to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 0/32
+//Bit 19:16 reg_nr4_cdrt_alp_core_rate // unsigned , default = 0 chroma ratio to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 0/32
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_ydrt_alp_core_ofst // unsigned , default = 10 luma offset to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 10
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_cdrt_alp_core_ofst // unsigned , default = 10 chroma offset to min_err, alpha = (min_err - (max_err - min_err)*rate + ofst)/max_err * 64; dft = 10
+#define NR4_DRT_ALP_MINMAX ((0x2da8 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_ydrt_alp_min // unsigned , default = 0 luma min value of alpha, dft = 0
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_ydrt_alp_max // unsigned , default = 63 luma max value of alpha, dft = 63
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_cdrt_alp_min // unsigned , default = 0 chroma min value of alpha, dft = 0
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_cdrt_alp_max // unsigned , default = 63 chroma max value of alpha, dft = 63
+//========== nr4_drt_regs register end ==========//
+//========== nr4_snr_regs register begin ==========//
+#define NR4_SNR_CTRL_REG ((0x2da9 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12 reg_nr4_bet2_sel // unsigned , default = 1
+//Bit 11: 9 reg_nr4_snr2_sel_mode // unsigned , default = 0 0: no filter, 1: adpgau, adp_drt_lpf blend; 2: adpgau, drt4_lpf blend; 3: adp_drt_lpf method, 4: drt4_lpf method, 5: adp_drt_ //original image blend, 6: drt4_lpf, original image blend, 7: adpgau method; dft=1
+//Bit 8 reg_nr4_snr2_gaulpf_mode // unsigned , default = 1 0: 3*5 or 5*5 gaussian lpf; 1: 3*3 (window size) gaussian lpf; dft=1
+//Bit 7: 6 reg_nr4_snr2_alpha0_sad_mode // unsigned , default = 3 0: max_sad*max_ssd; 1: max_sad*max_sad; 2: adp_max_sad*max_ssd; 3: adp_max_sad*adp_max_sad dft=3
+//Bit 5: 4 reg_nr4_snr2_alpha1_sad_mode // unsigned , default = 2 0: max_sad; 1: cross_max_sad; 2 or 3: adp_sad dft=2
+//Bit 3: 2 reserved
+//Bit 1: 0 reg_nr4_snr2_adp_drtlpf_mode // unsigned , default = 3 0: adp_drtlpf [2 1 1]/4, 1: adp_drtlpf [4 2 1 1]/8; 2: adp_drtlpf [2 2 2 1 1]/8; 3: adp_drtlpf [7 7 7 6 5]/32; dft=3;
+#define NR4_SNR_ALPHA0_MAX_MIN ((0x2daa << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:23 reg_nr4_snr2_alp0_ymin // unsigned , default = 127 normalized to 128 as '1'
+//Bit 22:16 reg_nr4_snr2_alp0_ymax // unsigned , default = 127 normalized to 128 as '1'
+//Bit 15:14 reserved
+//Bit 13: 7 reg_nr4_snr2_alp0_cmin // unsigned , default = 127 normalized to 128 as '1'
+//Bit 6: 0 reg_nr4_snr2_alp0_cmax // unsigned , default = 127 normalized to 128 as '1'
+#define NR4_ALP0C_ERR2CURV_LIMIT0 ((0x2dab << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_snr2_alp0_minerr_cpar0 // unsigned , default = 0 threshold0 of curve to map mierr to alp0 for chroma channel, this will be set value of flat region mierr that no need blur.
+//Bit 23:16 reg_nr4_snr2_alp0_minerr_cpar1 // unsigned , default = 25 threshold1 of curve to map mierr to alp0 for chroma channel,this will be set value of texture region mierr that can not blur.
+//Bit 15: 8 reg_nr4_snr2_alp0_minerr_cpar5 // unsigned , default = 40 rate0 (for mierr<th0) of curve to map mierr to alp0 for chroma channel. the larger of the value, the deep of the slope. 0~255.
+//Bit 7: 0 reg_nr4_snr2_alp0_minerr_cpar6 // unsigned , default = 40 rate1 (for mierr>th1) of curve to map mierr to alp0 for chroma channel. the larger of the value, the deep of the slope. 0~255.
+#define NR4_ALP0C_ERR2CURV_LIMIT1 ((0x2dac << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_snr2_alp0_minerr_cpar2 // unsigned , default = 127 level limit(for mierr<th0) of curve to map mierr to alp0 for chroma channel, that we can do for flat region. 0~255.
+//Bit 15: 8 reg_nr4_snr2_alp0_minerr_cpar3 // unsigned , default = 0 level limit(for th0<mierr<th1) of curve to map mierr to alp0 for chroma channel, that we can do for misc region. 0~255.
+//Bit 7: 0 reg_nr4_snr2_alp0_minerr_cpar4 // unsigned , default = 127 level limit(for mierr>th1) of curve to map mierr to alp0 for chroma channel, that we can do for texture region. 0~255.
+#define NR4_ALP0Y_ERR2CURV_LIMIT0 ((0x2dad << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_snr2_alp0_minerr_ypar0 // unsigned , default = 0 threshold0 of curve to map mierr to alp0 for luma channel, this will be set value of flat region mierr that no need blur. 0~255.
+//Bit 23:16 reg_nr4_snr2_alp0_minerr_ypar1 // unsigned , default = 25 threshold1 of curve to map mierr to alp0 for luma channel,this will be set value of texture region mierr that can not blur.
+//Bit 15: 8 reg_nr4_snr2_alp0_minerr_ypar5 // unsigned , default = 40 rate0 (for mierr<th0) of curve to map mierr to alp0 for luma channel. the larger of the value, the deep of the slope. 0~255.
+//Bit 7: 0 reg_nr4_snr2_alp0_minerr_ypar6 // unsigned , default = 40 rate1 (for mierr>th1) of curve to map mierr to alp0 for luma channel. the larger of the value, the deep of the slope. 0~255.
+#define NR4_ALP0Y_ERR2CURV_LIMIT1 ((0x2dae << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_snr2_alp0_minerr_ypar2 // unsigned , default = 127 level limit(for mierr<th0) of curve to map mierr to alp0 for luma channel, set to alp0 that we can do for flat region. 0~255.
+//Bit 15: 8 reg_nr4_snr2_alp0_minerr_ypar3 // unsigned , default = 0 level limit(for th0<mierr<th1) of curve to map mierr to alp0 for luma channel, alp0 that we can do for misc region. 0~255.
+//Bit 7: 0 reg_nr4_snr2_alp0_minerr_ypar4 // unsigned , default = 127 level limit(for mierr>th1) of curve to map mierr to alp0 for luma channel, alp0 that we can do for texture region. 0~255.
+#define NR4_SNR_ALPA1_RATE_AND_OFST ((0x2daf << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:18 reg_nr4_snr2_alp1_ycore_rate // unsigned , default = 0 normalized 64 as "1"
+//Bit 17:12 reg_nr4_snr2_alp1_ccore_rate // unsigned , default = 0 normalized 64 as "1"
+//Bit 11: 6 reg_nr4_snr2_alp1_ycore_ofst // signed , default = 3 normalized 64 as "1"
+//Bit 5: 0 reg_nr4_snr2_alp1_ccore_ofst // signed , default = 3 normalized 64 as "1"
+#define NR4_SNR_ALPHA1_MAX_MIN ((0x2db0 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:18 reg_nr4_snr2_alp1_ymin // unsigned , default = 0 normalized to 64 as '1'
+//Bit 17:12 reg_nr4_snr2_alp1_ymax // unsigned , default = 63 normalized to 64 as '1'
+//Bit 11: 6 reg_nr4_snr2_alp1_cmin // unsigned , default = 0 normalized to 64 as '1'
+//Bit 5: 0 reg_nr4_snr2_alp1_cmax // unsigned , default = 63 normalized to 64 as '1'
+#define NR4_ALP1C_ERR2CURV_LIMIT0 ((0x2db1 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_snr2_alp1_minerr_cpar0 // unsigned , default = 0 annel, this will be set value of flat region mierr that no need directional NR. 0~255.
+//Bit 23:16 reg_nr4_snr2_alp1_minerr_cpar1 // unsigned , default = 24 hannel,this will be set value of texture region mierr that can not do directional NR. 0~255.
+//Bit 15: 8 reg_nr4_snr2_alp1_minerr_cpar5 // unsigned , default = 0 a/chroma channel. the larger of the value, the deep of the slope.
+//Bit 7: 0 reg_nr4_snr2_alp1_minerr_cpar6 // unsigned , default = 20 a/chroma channel. the larger of the value, the deep of the slope. 0~255
+#define NR4_ALP1C_ERR2CURV_LIMIT1 ((0x2db2 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_snr2_alp1_minerr_cpar2 // unsigned , default = 0 will be set to alp1 that we can do for flat region. 0~255.
+//Bit 15: 8 reg_nr4_snr2_alp1_minerr_cpar3 // unsigned , default = 16 this will be set to alp1 that we can do for misc region. 0~255.
+//Bit 7: 0 reg_nr4_snr2_alp1_minerr_cpar4 // unsigned , default = 63 will be set to alp1 that we can do for texture region. 0~255.255 before
+#define NR4_ALP1Y_ERR2CURV_LIMIT0 ((0x2db3 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_snr2_alp1_minerr_ypar0 // unsigned , default = 0 thra/chroma channel, this will be set value of flat region mierr that no need directional NR. 0~255.
+//Bit 23:16 reg_nr4_snr2_alp1_minerr_ypar1 // unsigned , default = 24 thra/chroma channel,this will be set value of texture region mierr that can not do directional NR. 0~255.
+//Bit 15: 8 reg_nr4_snr2_alp1_minerr_ypar5 // unsigned , default = 0 ratlp1 for luma/chroma channel. the larger of the value, the deep of the slope.
+//Bit 7: 0 reg_nr4_snr2_alp1_minerr_ypar6 // unsigned , default = 20 ratlp1 for luma/chroma channel. the larger of the value, the deep of the slope. 0~255
+#define NR4_ALP1Y_ERR2CURV_LIMIT1 ((0x2db4 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_snr2_alp1_minerr_ypar2 // unsigned , default = 0 lev to alp1 for luma/chroma channel, this will be set to alp1 that we can do for flat region. 0~255.
+//Bit 15: 8 reg_nr4_snr2_alp1_minerr_ypar3 // unsigned , default = 16 levierr to alp1 for luma/chroma channel, this will be set to alp1 that we can do for misc region. 0~255.
+//Bit 7: 0 reg_nr4_snr2_alp1_minerr_ypar4 // unsigned , default = 63 lev to alp1 for luma/chroma channel, this will be set to alp1 that we can do for texture region. 0~255.255 before
+//========== nr4_snr_regs register end ==========//
+//========== nr4_tnr_regs register begin ==========//
+#define NR4_MTN_CTRL ((0x2db5 << 2) + 0xff000000)
+//Bit 31: 2 reserved
+//Bit 1 reg_nr4_mtn_ref_en // unsigned , default = 1 enable motion refinement, dft = 1
+//Bit 0 reg_nr4_mtn_ref_bet_sel // unsigned , default = 0 beta selection mode for motion refinement, 0: beta1, 1: beta2, dft = 0
+#define NR4_MTN_REF_PAR0 ((0x2db6 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_mtn_ref_par0 // unsigned , default = 24 par0 for beta to gain, dft =
+//Bit 23:16 reg_nr4_mtn_ref_par1 // unsigned , default = 60 par1 for beta to gain, dft =
+//Bit 15: 8 reg_nr4_mtn_ref_par2 // unsigned , default = 4 par2 for beta to gain, dft =
+//Bit 7: 0 reg_nr4_mtn_ref_par3 // unsigned , default = 32 par3 for beta to gain, dft =
+#define NR4_MTN_REF_PAR1 ((0x2db7 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_mtn_ref_par4 // unsigned , default = 128 par4 for beta to gain, dft =
+//Bit 15: 8 reg_nr4_mtn_ref_par5 // unsigned , default = 40 par5 for beta to gain, dft =
+//Bit 7: 0 reg_nr4_mtn_ref_par6 // unsigned , default = 20 par6 for beta to gain, dft =
+//========== nr4_tnr_regs register end ==========//
+//========== nr4_mcnr_regs register begin ==========//
+#define NR4_MCNR_LUMA_ENH_CTRL ((0x2db8 << 2) + 0xff000000)
+//Bit 31: 4 reserved
+//Bit 3 reg_nr4_luma_plus_en // unsigned , default = 1 enable luma enhancement, dft = 1
+//Bit 2 reg_nr4_luma_plus_wt_mode // unsigned , default = 1 luma weight calc mode, 0:sqrt(1+x^2), 1: 1+abs(x), dft = 0
+//Bit 1: 0 reg_nr4_luma_plus_orient_mode // unsigned , default = 1 0: only use previous orient for pre and cur luma plus, 1: 0: only use current orient for pre and cur luma plus
+#define NR4_MCNR_LUMA_STAT_LIMTX ((0x2db9 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_nr4_luma_plus_xst // unsigned , default = 8 start for luma plus statistic, dft = 8
+//Bit 15:14 reserved
+//Bit 13: 0 reg_nr4_luma_plus_xed // unsigned , default = 711 end for luma plus statistic, dft = HSIZE-8-1;
+#define NR4_MCNR_LUMA_STAT_LIMTY ((0x2dba << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_nr4_luma_plus_yst // unsigned , default = 8 start for luma plus statistic, dft = 8
+//Bit 15:14 reserved
+//Bit 13: 0 reg_nr4_luma_plus_yed // unsigned , default = 231 end for luma plus statistic, dft = VSIZE-8-1
+#define NR4_MCNR_LUMA_DIF_CALC ((0x2dbb << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_luma_plus_ugain // unsigned , default = 8 U's gain for luma enhancement, 16 normalized as '1'
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_luma_plus_vgain // unsigned , default = 8 V's gain for luma enhancement, 16 normalized as '1'
+//Bit 15: 8 reg_nr4_luma_plus_ycor_thd // unsigned , default = 2 Y coring threshold for difference calc., dft = 0
+//Bit 7: 0 reg_nr4_luma_plus_ccor_thd // unsigned , default = 0 C coring threshold for difference calc., dft = 0
+#define NR4_MCNR_LUMAPRE_CAL_PRAM ((0x2dbc << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_nr4_pre_u_orient // signed , default = 0 orientation of previous U, initial to 0, and will be updated by software
+//Bit 23:18 reserved
+//Bit 17:16 reg_nr4_pre_v_orient // signed , default = 0 orientation of previous V, initial to 0, and will be updated by software
+//Bit 15: 8 reg_nr4_pre_u_mean // unsigned , default = 0 mean of previous U, initial to 0, and will be updated by software
+//Bit 7: 0 reg_nr4_pre_v_mean // unsigned , default = 0 mean of previousV, initial to 0, and will be updated by software
+#define NR4_MCNR_LUMACUR_CAL_PRAM ((0x2dbd << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_nr4_cur_u_orient // signed , default = 0 orientation of current U, initial to 0, and will be updated by software
+//Bit 23:18 reserved
+//Bit 17:16 reg_nr4_cur_v_orient // signed , default = 0 orientation of current V, initial to 0, and will be updated by software
+//Bit 15: 8 reg_nr4_cur_u_mean // unsigned , default = 0 mean of current U, initial to 0, and will be updated by software
+//Bit 7: 0 reg_nr4_cur_v_mean // unsigned , default = 0 mean of current, initial to 0, and will be updated by software
+#define NR4_MCNR_MV_CTRL_REG ((0x2dbe << 2) + 0xff000000)
+//Bit 31:14 reserved
+//Bit 13:12 reg_nr4_sad_bitw // unsigned , default = 2 sad bit width (8 + x) before clip to u8, dft = 1
+//Bit 11: 4 reg_nr4_glb_gain // unsigned , default = 64 global gain calc. by software, 64 is normalized as '1'
+//Bit 3: 0 reg_nr4_mv_err_rsft // unsigned , default = 8 right shift for mv err calc., dft = 9
+#define NR4_MCNR_MV_GAIN0 ((0x2dbf << 2) + 0xff000000)
+//Bit 31:28 reg_nr4_lftmvx_gain // unsigned , default = 1 left mvx gain for err calc., dft = 1
+//Bit 27:24 reg_nr4_lftmvy_gain // unsigned , default = 1 left mvy gain for err calc., dft = 1
+//Bit 23:20 reg_nr4_zmvx_gain // unsigned , default = 5 zero mvx gain for err calc., dft = 2
+//Bit 19:16 reg_nr4_zmvy_gain // unsigned , default = 5 zero mvy gain for err calc., dft = 4
+//Bit 15:12 reg_nr4_lmvx0_gain // unsigned , default = 2 line mvx0 gain for err calc., dft = 1
+//Bit 11: 8 reg_nr4_lmvx1_gain // unsigned , default = 2 line mvx1 gain for err calc., dft = 1
+//Bit 7: 4 reg_nr4_lmvy0_gain // unsigned , default = 2 line mvy0 gain for err calc., dft = 1
+//Bit 3: 0 reg_nr4_lmvy1_gain // unsigned , default = 2 line mvy1 gain for err calc., dft = 1
+#define NR4_MCNR_LMV_PARM ((0x2dc0 << 2) + 0xff000000)
+//Bit 31:28 reg_nr4_lmv_rt0 // unsigned , default = 3 ratio of max lmv
+//Bit 27:24 reg_nr4_lmv_rt1 // unsigned , default = 3 ratio of second max lmv
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_lmv_num_lmt0 // unsigned , default = 16 lmv0 least/limit number of (total number - zero_bin)
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_lmv_num_lmt1 // unsigned , default = 8 lmv1 least/limit number of (total number - zero_bin - max0)
+//Bit 7: 2 reserved
+//Bit 1: 0 reg_nr4_max_sad_rng // unsigned , default = 1 search range of max2 sad in small region, dft = 1
+#define NR4_MCNR_ALP0_REG ((0x2dc1 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25 reg_nr4_alp0_fail_chk // unsigned , default = 1 enable check for alp0 fail status
+//Bit 24 reg_nr4_bet0_coef_ref_en // unsigned , default = 1 bet1 refinement by coef_blt
+//Bit 23:16 reg_nr4_alp0_posad_gain // unsigned , default = 255 the sad (norm) gain for pixel pointed by MV;
+//Bit 15:10 reserved
+//Bit 9: 8 reg_nr4_alp0_norm_mode // unsigned , default = 0 alp0 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_alp0_norm_gain // unsigned , default = 16 alp0 gain for sad norm, '32' as '1', dft = 1
+#define NR4_MCNR_ALP1_AND_BET0_REG ((0x2dc2 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_nr4_alp1_norm_mode // unsigned , default = 3 alp1 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_alp1_norm_gain // unsigned , default = 3 alp1 gain for sad norm, '32' as '1', dft = 1
+//Bit 15:10 reserved
+//Bit 9: 8 reg_nr4_bet0_norm_mode // unsigned , default = 3 bet0 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bet0_norm_gain // unsigned , default = 8 bet0 gain for sad norm, '32' as '1', dft = 1
+#define NR4_MCNR_BET1_AND_BET2_REG ((0x2dc3 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_nr4_bet1_norm_mode // unsigned , default = 3 bet1 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_bet1_norm_gain // unsigned , default = 8 bet1 gain for sad norm, '32' as '1', dft = 1
+//Bit 15:10 reserved
+//Bit 9: 8 reg_nr4_bet2_norm_mode // unsigned , default = 0 bet2 select sad norm mode, 0: disable, 1: enable dc norm, 2: enable ac norm, 3: enable both (dc/ac) norm, dft = 3
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bet2_norm_gain // unsigned , default = 16 bet2 gain for sad norm, '32' as '1', dft = 1
+#define NR4_MCNR_AC_DC_CRTL ((0x2dc4 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15:12 reserved
+//Bit 11 reg_nr4_dc_mode // unsigned , default = 1 mode for dc selection,0: Y_lpf, 1: Y_lpf + (U_Lpf+V_lpf)/2,
+//Bit 10 reg_nr4_ac_mode // unsigned , default = 1 mode for ac selection, 0: Y_abs_dif, 1: Y_abs_dif + (U_abs_dif + V_abs_dif)/2
+//Bit 9 reg_nr4_dc_sel // unsigned , default = 0 selection mode for dc value, 0: 3x5, 1: 5x5, dft = 1
+//Bit 8 reg_nr4_ac_sel // unsigned , default = 0 selection mode for ac value, 0: 3x5, 1: 5x5, dft = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_nr4_dc_shft // unsigned , default = 2 right shift for dc value, dft = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_nr4_ac_shft // unsigned , default = 0 right shift for ac value, dft = 2
+#define NR4_MCNR_CM_CTRL0 ((0x2dc5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28 reg_nr4_cm_skin_prc_bet0 // unsigned , default = 0 enable skin tone processing for mcnr bet0 calc., dft = 1
+//Bit 27:26 reg_nr4_cm_chrm_sel // unsigned , default = 1 chrome selection for color match, 0: 1x1, 1: 3X3LPF, 2: 3x5LPF, 3: 5x5LPF for 5lines, 3x5LPF for 3lines, dft = 3
+//Bit 25:24 reg_nr4_cm_luma_sel // unsigned , default = 1 luma selection for color match, 0: 1x1, 1: 3X3LPF, 2: 3x5LPF, 3: 5x5LPF for 5lines, 3x5LPF for 3lines, dft = 3
+//Bit 23:21 reg_nr4_cm_skin_rshft_bet0 // unsigned , default = 3 right shift for bet0's skin color gains, dft = 3
+//Bit 20 reg_nr4_cm_var_sel // unsigned , default = 1 variation selection for color match, 0: 3x5, 1: 5x5 for 5lines, 3x5 for 3lines, dft = 1
+//Bit 19 reg_nr4_cm_green_prc_bet0 // unsigned , default = 1 enable green processing for mcnr bet0 calc., dft = 1
+//Bit 18:16 reg_nr4_cm_green_rshft_bet0 // unsigned , default = 4 right shift for bet0's green color gains, dft = 4
+//Bit 15:14 reg_nr4_preflt_mod // unsigned , default = 2 pre filter mode in mcnr, 0: mv pointed pixel, 1: bilater filter
+//Bit 13:12 reg_nr4_alp1_mode // unsigned , default = 1 mode for alpha1's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad
+//Bit 11:10 reserved
+//Bit 9: 8 reg_nr4_bet0_mode // unsigned , default = 0 mode for bet0's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad, else: (co sad) - (min sad)
+//Bit 7: 6 reserved
+//Bit 5: 4 reg_nr4_bet1_mode // unsigned , default = 2 mode for bet1's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad, else: (co sad) - (min sad)
+//Bit 3: 2 reserved
+//Bit 1: 0 reg_nr4_bet2_mode // unsigned , default = 1 mode for bet2's sad selection, 0: max sad, 1: three min sads, 2: min sad, 3: co sad, else: (co sad) - (min sad)
+#define NR4_MCNR_CM_PRAM ((0x2dc6 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29 reg_nr4_cm_blue_prc_alp0 // unsigned , default = 1 enable blue processing for mcnr alpha0 calc., dft = 1
+//Bit 28 reg_nr4_cm_blue_prc_alp1 // unsigned , default = 1 enable blue processing for mcnr alpha1 calc., dft = 1
+//Bit 27 reg_nr4_cm_skin_prc_alp0 // unsigned , default = 1 enable skin tone processing for mcnr alpha0 calc., dft = 1
+//Bit 26 reg_nr4_cm_green_prc_alp0 // unsigned , default = 1 enable green processing for mcnr alpha0 clac., dft = 1
+//Bit 25 reg_nr4_cm_skin_prc_alp1 // unsigned , default = 1 enable skin tone processing for mcnr alpha0 calc., dft = 1
+//Bit 24 reg_nr4_cm_green_prc_alp1 // unsigned , default = 1 enable green processing for mcnr alpha1 clac., dft = 1
+//Bit 23:20 reg_nr4_cm_blue_hue_st // unsigned , default = 13 hue start of blue, dft =
+//Bit 19:16 reg_nr4_cm_blue_hue_ed // unsigned , default = 15 hue end of blue, dft =
+//Bit 15:12 reg_nr4_cm_green_hue_st // unsigned , default = 7 hue start of green, dft =
+//Bit 11: 8 reg_nr4_cm_green_hue_ed // unsigned , default = 10 hue end of green, dft =
+//Bit 7: 4 reg_nr4_cm_skin_hue_st // unsigned , default = 5 hue start of skin, dft =
+//Bit 3: 0 reg_nr4_cm_skin_hue_ed // unsigned , default = 6 hue end of skin, dft =
+#define NR4_MCNR_CM_RSHFT_ALP0 ((0x2dc7 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:25 reg_nr4_cm_blue_rshft_bet0 // unsigned , default = 5 right shift for bet0's blue color gains, dft = 5
+//Bit 24 reg_nr4_cm_blue_prc_bet0 // unsigned , default = 1 enable blue processing for mcnr bet0 calc., dft = 1
+//Bit 23 reserved
+//Bit 22:20 reg_nr4_cm_blue_rshft_alp0 // unsigned , default = 5 right shift for alpha0/1's blue color gains, dft = 5
+//Bit 19 reserved
+//Bit 18:16 reg_nr4_cm_blue_rshft_alp1 // unsigned , default = 5 right shift for alpha0/1's blue color gains, dft = 5
+//Bit 15 reserved
+//Bit 14:12 reg_nr4_cm_green_rshft_alp0 // unsigned , default = 4 right shift for alpha0/1's green color gains, dft = 4
+//Bit 11 reserved
+//Bit 10: 8 reg_nr4_cm_green_rshft_alp1 // unsigned , default = 4 right shift for alpha0/1's green color gains, dft = 4
+//Bit 7 reserved
+//Bit 6: 4 reg_nr4_cm_skin_rshft_alp0 // unsigned , default = 3 right shift for alpha0/1's skin color gains, dft = 3
+//Bit 3 reserved
+//Bit 2: 0 reg_nr4_cm_skin_rshft_alp1 // unsigned , default = 3 right shift for alpha0/1's skin color gains, dft = 3
+#define NR4_MCNR_BLUE_CENT ((0x2dc8 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_blue_centx // unsigned , default = 157 x coordinate of center of blue, dft =
+//Bit 15: 8 reserved
+//Bit 7: 0 reg_nr4_cm_blue_centy // unsigned , default = 110 y coordinate of center of blue, dft =
+#define NR4_MCNR_BLUE_GAIN_PAR0 ((0x2dc9 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_cm_blue_gain_par0 // unsigned , default = 32 par0 for blue gain, dft =
+//Bit 23:16 reg_nr4_cm_blue_gain_par1 // unsigned , default = 255 par1 for blue gain, dft =
+//Bit 15: 8 reg_nr4_cm_blue_gain_par2 // unsigned , default = 4 par2 for blue gain, dft =
+//Bit 7: 0 reg_nr4_cm_blue_gain_par3 // unsigned , default = 32 par3 for blue gain, dft =
+#define NR4_MCNR_BLUE_GAIN_PAR1 ((0x2dca << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_blue_gain_par4 // unsigned , default = 32 par4 for blue gain, dft =
+//Bit 15: 8 reg_nr4_cm_blue_gain_par5 // unsigned , default = 32 par5 for blue gain, dft =
+//Bit 7: 0 reg_nr4_cm_blue_gain_par6 // unsigned , default = 0 par6 for blue gain, dft =
+#define NR4_MCNR_CM_BLUE_CLIP0 ((0x2dcb << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_blue_luma_min // unsigned , default = 40 luma min for blue color matching, dft =
+//Bit 15: 8 reserved
+//Bit 7: 0 reg_nr4_cm_blue_luma_max // unsigned , default = 180 luma max for blue color matching, dft =
+#define NR4_MCNR_CM_BLUE_CLIP1 ((0x2dcc << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_cm_blue_sat_min // unsigned , default = 5 saturation min for blue color matching, dft =
+//Bit 23:16 reg_nr4_cm_blue_sat_max // unsigned , default = 255 saturation max for blue color matching, dft =
+//Bit 15: 8 reg_nr4_cm_blue_var_min // unsigned , default = 0 variation min for blue color matching, dft =
+//Bit 7: 0 reg_nr4_cm_blue_var_max // unsigned , default = 12 variation max for blue color matching, dft =
+#define NR4_MCNR_GREEN_CENT ((0x2dcd << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_green_centx // unsigned , default = 114 x coordinate of center of green, dft =
+//Bit 15: 8 reserved
+//Bit 7: 0 reg_nr4_cm_green_centy // unsigned , default = 126 y coordinate of center of green, dft =
+#define NR4_MCNR_GREEN_GAIN_PAR0 ((0x2dce << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_cm_green_gain_par0 // unsigned , default = 16 par0 for green gain, dft =
+//Bit 23:16 reg_nr4_cm_green_gain_par1 // unsigned , default = 255 par1 for green gain, dft =
+//Bit 15: 8 reg_nr4_cm_green_gain_par2 // unsigned , default = 255 par2 for green gain, dft =
+//Bit 7: 0 reg_nr4_cm_green_gain_par3 // unsigned , default = 16 par3 for green gain, dft =
+#define NR4_MCNR_GREEN_GAIN_PAR1 ((0x2dcf << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_green_gain_par4 // unsigned , default = 16 par4 for green gain, dft =
+//Bit 15: 8 reg_nr4_cm_green_gain_par5 // unsigned , default = 128 par5 for green gain, dft =
+//Bit 7: 0 reg_nr4_cm_green_gain_par6 // unsigned , default = 0 par6 for green gain, dft =
+#define NR4_MCNR_GREEN_CLIP0 ((0x2dd0 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_green_luma_min // unsigned , default = 40 luma min for green color matching, dft =
+//Bit 15: 8 reserved
+//Bit 7: 0 reg_nr4_cm_green_luma_max // unsigned , default = 160 luma max for green color matching, dft =
+#define NR4_MCNR_GREEN_CLIP2 ((0x2dd1 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_cm_green_sat_min // unsigned , default = 4 saturation min for green color matching, dft =
+//Bit 23:16 reg_nr4_cm_green_sat_max // unsigned , default = 255 saturation max for green color matching, dft =
+//Bit 15: 8 reg_nr4_cm_green_var_min // unsigned , default = 0 variation min for green color matching, dft =
+//Bit 7: 0 reg_nr4_cm_green_var_max // unsigned , default = 12 variation max for green color matching, dft =
+#define NR4_MCNR_SKIN_CENT ((0x2dd2 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_skin_centx // unsigned , default = 112 x coordinate of center of skin tone, dft =
+//Bit 15: 8 reserved
+//Bit 7: 0 reg_nr4_cm_skin_centy // unsigned , default = 149 y coordinate of center of skin tone, dft =
+#define NR4_MCNR_SKIN_GAIN_PAR0 ((0x2dd3 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_cm_skin_gain_par0 // unsigned , default = 20 par0 for skin gain, dft =
+//Bit 23:16 reg_nr4_cm_skin_gain_par1 // unsigned , default = 255 par1 for skin gain, dft =
+//Bit 15: 8 reg_nr4_cm_skin_gain_par2 // unsigned , default = 255 par2 for skin gain, dft =
+//Bit 7: 0 reg_nr4_cm_skin_gain_par3 // unsigned , default = 8 par3 for skin gain, dft =
+#define NR4_MCNR_SKIN_GAIN_PAR1 ((0x2dd4 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_skin_gain_par4 // unsigned , default = 8 par4 for skin gain, dft =
+//Bit 15: 8 reg_nr4_cm_skin_gain_par5 // unsigned , default = 128 par5 for skin gain, dft =
+//Bit 7: 0 reg_nr4_cm_skin_gain_par6 // unsigned , default = 0 par6 for skin gain, dft =
+#define NR4_MCNR_SKIN_CLIP0 ((0x2dd5 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_cm_skin_luma_min // unsigned , default = 40 luma min for skin color matching, dft =
+//Bit 15: 8 reserved
+//Bit 7: 0 reg_nr4_cm_skin_luma_max // unsigned , default = 180 luma max for skin color matching, dft =
+#define NR4_MCNR_SKIN_CLIP1 ((0x2dd6 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_cm_skin_sat_min // unsigned , default = 5 saturation min for skin color matching, dft =
+//Bit 23:16 reg_nr4_cm_skin_sat_max // unsigned , default = 255 saturation max for skin color matching, dft =
+//Bit 15: 8 reg_nr4_cm_skin_var_min // unsigned , default = 0 variation min for skin color matching, dft =
+//Bit 7: 0 reg_nr4_cm_skin_var_max // unsigned , default = 12 variation max for skin color matching, dft =
+#define NR4_MCNR_ALP1_GLB_CTRL ((0x2dd7 << 2) + 0xff000000)
+//Bit 31 reg_nr4_alp1_glb_gain_en // unsigned , default = 0 alp1 adjust by global gain, dft = 1
+//Bit 30:28 reg_nr4_alp1_glb_gain_lsft // unsigned , default = 6 alp1 left shift before combine with global gain
+//Bit 27 reg_nr4_bet0_glb_gain_en // unsigned , default = 1 bet0 adjust by global gain, dft = 1
+//Bit 26:24 reg_nr4_bet0_glb_gain_lsft // unsigned , default = 6 bet1 left shift before combine with global gain
+//Bit 23 reg_nr4_bet1_glb_gain_en // unsigned , default = 0 bet1 adjust by global gain, dft = 0
+//Bit 22:20 reg_nr4_bet1_glb_gain_lsft // unsigned , default = 6 bet1 left shift before combine with global gain
+//Bit 19 reg_nr4_bet2_glb_gain_en // unsigned , default = 1 bet2 adjust by global gain, dft = 1
+//Bit 18:16 reg_nr4_bet2_glb_gain_lsft // unsigned , default = 6 bet2 left shift before combine with global gain
+//Bit 15 reg_nr4_alp1_ac_en // unsigned , default = 1 alp1 adjust by ac, dft = 1
+//Bit 14:12 reg_nr4_alp1_ac_lsft // unsigned , default = 5 alp1 left shift before combine with ac
+//Bit 11 reg_nr4_bet0_ac_en // unsigned , default = 0 bet0 adjust by ac, dft = 1
+//Bit 10: 8 reg_nr4_bet0_ac_lsft // unsigned , default = 5 bet0 left shift before combine with ac
+//Bit 7 reg_nr4_bet1_ac_en // unsigned , default = 0 bet1 adjust by ac, dft = 1
+//Bit 6: 4 reg_nr4_bet1_ac_lsft // unsigned , default = 5 bet1 left shift before combine with ac
+//Bit 3 reg_nr4_bet2_ac_en // unsigned , default = 0 bet2 adjust by ac, dft = 1
+//Bit 2: 0 reg_nr4_bet2_ac_lsft // unsigned , default = 5 bet2 left shift before combine with ac
+#define NR4_MCNR_DC2NORM_LUT0 ((0x2dd8 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:24 reg_nr4_dc2norm_lut0 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+//Bit 23:21 reserved
+//Bit 20:16 reg_nr4_dc2norm_lut1 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+//Bit 15:13 reserved
+//Bit 12: 8 reg_nr4_dc2norm_lut2 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+//Bit 7: 5 reserved
+//Bit 4: 0 reg_nr4_dc2norm_lut3 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+#define NR4_MCNR_DC2NORM_LUT1 ((0x2dd9 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:24 reg_nr4_dc2norm_lut4 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+//Bit 23:21 reserved
+//Bit 20:16 reg_nr4_dc2norm_lut5 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+//Bit 15:13 reserved
+//Bit 12: 8 reg_nr4_dc2norm_lut6 // unsigned , default = 16 normal 0~16, dc to norm for alpha adjust, dft =
+//Bit 7: 5 reserved
+//Bit 4: 0 reg_nr4_dc2norm_lut7 // unsigned , default = 12 normal 0~16, dc to norm for alpha adjust, dft =
+#define NR4_MCNR_DC2NORM_LUT2 ((0x2dda << 2) + 0xff000000)
+//Bit 31: 5 reserved
+//Bit 4: 0 reg_nr4_dc2norm_lut8 // unsigned , default = 8 normal 0~16, dc to norm for alpha adjust, dft =
+#define NR4_MCNR_AC2NORM_LUT0 ((0x2ddb << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:24 reg_nr4_ac2norm_lut0 // unsigned , default = 2 normal 0~16, ac to norm for alpha adjust, dft =
+//Bit 23:21 reserved
+//Bit 20:16 reg_nr4_ac2norm_lut1 // unsigned , default = 16 normal 0~16, ac to norm for alpha adjust, dft =
+//Bit 15:13 reserved
+//Bit 12: 8 reg_nr4_ac2norm_lut2 // unsigned , default = 16 normal 0~16, ac to norm for alpha adjust, dft =
+//Bit 7: 5 reserved
+//Bit 4: 0 reg_nr4_ac2norm_lut3 // unsigned , default = 12 normal 0~16, ac to norm for alpha adjust, dft =
+#define NR4_MCNR_AC2NORM_LUT1 ((0x2ddc << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:24 reg_nr4_ac2norm_lut4 // unsigned , default = 4 normal 0~16, ac to norm for alpha adjust, dft =
+//Bit 23:21 reserved
+//Bit 20:16 reg_nr4_ac2norm_lut5 // unsigned , default = 2 normal 0~16, ac to norm for alpha adjust, dft =
+//Bit 15:13 reserved
+//Bit 12: 8 reg_nr4_ac2norm_lut6 // unsigned , default = 1 normal 0~16, ac to norm for alpha adjust, dft =
+//Bit 7: 5 reserved
+//Bit 4: 0 reg_nr4_ac2norm_lut7 // unsigned , default = 1 normal 0~16, ac to norm for alpha adjust, dft =
+#define NR4_MCNR_AC2NORM_LUT2 ((0x2ddd << 2) + 0xff000000)
+//Bit 31: 5 reserved
+//Bit 4: 0 reg_nr4_ac2norm_lut8 // unsigned , default = 1 normal 0~16, ac to norm for alpha adjust, dft =
+#define NR4_MCNR_SAD2ALP0_LUT0 ((0x2dde << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp0_lut0 // unsigned , default = 255 sad to alpha0 for temporal pixel value, dft = 255
+//Bit 23:16 reg_nr4_sad2alp0_lut1 // unsigned , default = 252 sad to alpha0 for temporal pixel value, dft = 252
+//Bit 15: 8 reg_nr4_sad2alp0_lut2 // unsigned , default = 249 sad to alpha0 for temporal pixel value, dft = 249
+//Bit 7: 0 reg_nr4_sad2alp0_lut3 // unsigned , default = 235 sad to alpha0 for temporal pixel value, dft = 70
+#define NR4_MCNR_SAD2ALP0_LUT1 ((0x2ddf << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp0_lut4 // unsigned , default = 185 sad to alpha0 for temporal pixel value, dft = 12
+//Bit 23:16 reg_nr4_sad2alp0_lut5 // unsigned , default = 70 sad to alpha0 for temporal pixel value, dft = 1
+//Bit 15: 8 reg_nr4_sad2alp0_lut6 // unsigned , default = 14 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 7: 0 reg_nr4_sad2alp0_lut7 // unsigned , default = 1 sad to alpha0 for temporal pixel value, dft = 0
+#define NR4_MCNR_SAD2ALP0_LUT2 ((0x2de0 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp0_lut8 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 23:16 reg_nr4_sad2alp0_lut9 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 15: 8 reg_nr4_sad2alp0_lut10 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 7: 0 reg_nr4_sad2alp0_lut11 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+#define NR4_MCNR_SAD2ALP0_LUT3 ((0x2de1 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp0_lut12 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 23:16 reg_nr4_sad2alp0_lut13 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 15: 8 reg_nr4_sad2alp0_lut14 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+//Bit 7: 0 reg_nr4_sad2alp0_lut15 // unsigned , default = 0 sad to alpha0 for temporal pixel value, dft = 0
+#define NR4_MCNR_SAD2ALP1_LUT0 ((0x2de2 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp1_lut0 // unsigned , default = 192 sad to alpha1 for temporal blending, dft = 128
+//Bit 23:16 reg_nr4_sad2alp1_lut1 // unsigned , default = 160 sad to alpha1 for temporal blending, dft = 128
+//Bit 15: 8 reg_nr4_sad2alp1_lut2 // unsigned , default = 128 sad to alpha1 for temporal blending, dft = 128
+//Bit 7: 0 reg_nr4_sad2alp1_lut3 // unsigned , default = 96 sad to alpha1 for temporal blending, dft = 64
+#define NR4_MCNR_SAD2ALP1_LUT1 ((0x2de3 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp1_lut4 // unsigned , default = 64 sad to alpha1 for temporal blending, dft = 64
+//Bit 23:16 reg_nr4_sad2alp1_lut5 // unsigned , default = 32 sad to alpha1 for temporal blending, dft = 128
+//Bit 15: 8 reg_nr4_sad2alp1_lut6 // unsigned , default = 16 sad to alpha1 for temporal blending, dft = 255
+//Bit 7: 0 reg_nr4_sad2alp1_lut7 // unsigned , default = 8 sad to alpha1 for temporal blending, dft = 255
+#define NR4_MCNR_SAD2ALP1_LUT2 ((0x2de4 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp1_lut8 // unsigned , default = 4 sad to alpha1 for temporal blending, dft = 255
+//Bit 23:16 reg_nr4_sad2alp1_lut9 // unsigned , default = 0 sad to alpha1 for temporal blending, dft = 255
+//Bit 15: 8 reg_nr4_sad2alp1_lut10 // unsigned , default = 16 sad to alpha1 for temporal blending, dft = 255
+//Bit 7: 0 reg_nr4_sad2alp1_lut11 // unsigned , default = 64 sad to alpha1 for temporal blending, dft = 255
+#define NR4_MCNR_SAD2ALP1_LUT3 ((0x2de5 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2alp1_lut12 // unsigned , default = 96 sad to alpha1 for temporal blending, dft = 255
+//Bit 23:16 reg_nr4_sad2alp1_lut13 // unsigned , default = 224 sad to alpha1 for temporal blending, dft = 255
+//Bit 15: 8 reg_nr4_sad2alp1_lut14 // unsigned , default = 255 sad to alpha1 for temporal blending, dft = 255
+//Bit 7: 0 reg_nr4_sad2alp1_lut15 // unsigned , default = 255 sad to alpha1 for temporal blending, dft = 255
+#define NR4_MCNR_SAD2BET0_LUT0 ((0x2de6 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet0_lut0 // unsigned , default = 0 sad to beta0 for tnr and mcnr blending, dft = 0
+//Bit 23:16 reg_nr4_sad2bet0_lut1 // unsigned , default = 2 sad to beta0 for tnr and mcnr blending, dft = 2
+//Bit 15: 8 reg_nr4_sad2bet0_lut2 // unsigned , default = 4 sad to beta0 for tnr and mcnr blending, dft = 4
+//Bit 7: 0 reg_nr4_sad2bet0_lut3 // unsigned , default = 8 sad to beta0 for tnr and mcnr blending, dft = 8
+#define NR4_MCNR_SAD2BET0_LUT1 ((0x2de7 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet0_lut4 // unsigned , default = 16 sad to beta0 for tnr and mcnr blending, dft = 16
+//Bit 23:16 reg_nr4_sad2bet0_lut5 // unsigned , default = 32 sad to beta0 for tnr and mcnr blending, dft = 32
+//Bit 15: 8 reg_nr4_sad2bet0_lut6 // unsigned , default = 48 sad to beta0 for tnr and mcnr blending, dft = 48
+//Bit 7: 0 reg_nr4_sad2bet0_lut7 // unsigned , default = 64 sad to beta0 for tnr and mcnr blending, dft = 64
+#define NR4_MCNR_SAD2BET0_LUT2 ((0x2de8 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet0_lut8 // unsigned , default = 80 sad to beta0 for tnr and mcnr blending, dft = 80
+//Bit 23:16 reg_nr4_sad2bet0_lut9 // unsigned , default = 96 sad to beta0 for tnr and mcnr blending, dft = 96
+//Bit 15: 8 reg_nr4_sad2bet0_lut10 // unsigned , default = 112 sad to beta0 for tnr and mcnr blending, dft = 112
+//Bit 7: 0 reg_nr4_sad2bet0_lut11 // unsigned , default = 128 sad to beta0 for tnr and mcnr blending, dft = 128
+#define NR4_MCNR_SAD2BET0_LUT3 ((0x2de9 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet0_lut12 // unsigned , default = 196 sad to beta0 for tnr and mcnr blending, dft = 160
+//Bit 23:16 reg_nr4_sad2bet0_lut13 // unsigned , default = 224 sad to beta0 for tnr and mcnr blending, dft = 192
+//Bit 15: 8 reg_nr4_sad2bet0_lut14 // unsigned , default = 255 sad to beta0 for tnr and mcnr blending, dft = 224
+//Bit 7: 0 reg_nr4_sad2bet0_lut15 // unsigned , default = 255 sad to beta0 for tnr and mcnr blending, dft = 255
+#define NR4_MCNR_SAD2BET1_LUT0 ((0x2dea << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet1_lut0 // unsigned , default = 0 sad to beta1 for deghost blending, dft = 0
+//Bit 23:16 reg_nr4_sad2bet1_lut1 // unsigned , default = 2 sad to beta1 for deghost blending, dft = 2
+//Bit 15: 8 reg_nr4_sad2bet1_lut2 // unsigned , default = 4 sad to beta1 for deghost blending, dft = 4
+//Bit 7: 0 reg_nr4_sad2bet1_lut3 // unsigned , default = 8 sad to beta1 for deghost blending, dft = 8
+#define NR4_MCNR_SAD2BET1_LUT1 ((0x2deb << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet1_lut4 // unsigned , default = 16 sad to beta1 for deghost blending, dft = 16
+//Bit 23:16 reg_nr4_sad2bet1_lut5 // unsigned , default = 32 sad to beta1 for deghost blending, dft = 32
+//Bit 15: 8 reg_nr4_sad2bet1_lut6 // unsigned , default = 48 sad to beta1 for deghost blending, dft = 48
+//Bit 7: 0 reg_nr4_sad2bet1_lut7 // unsigned , default = 64 sad to beta1 for deghost blending, dft = 64
+#define NR4_MCNR_SAD2BET1_LUT2 ((0x2dec << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet1_lut8 // unsigned , default = 80 sad to beta1 for deghost blending, dft = 80
+//Bit 23:16 reg_nr4_sad2bet1_lut9 // unsigned , default = 96 sad to beta1 for deghost blending, dft = 96
+//Bit 15: 8 reg_nr4_sad2bet1_lut10 // unsigned , default = 112 sad to beta1 for deghost blending, dft = 112
+//Bit 7: 0 reg_nr4_sad2bet1_lut11 // unsigned , default = 128 sad to beta1 for deghost blending, dft = 128
+#define NR4_MCNR_SAD2BET1_LUT3 ((0x2ded << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet1_lut12 // unsigned , default = 160 sad to beta1 for deghost blending, dft = 160
+//Bit 23:16 reg_nr4_sad2bet1_lut13 // unsigned , default = 192 sad to beta1 for deghost blending, dft = 192
+//Bit 15: 8 reg_nr4_sad2bet1_lut14 // unsigned , default = 224 sad to beta1 for deghost blending, dft = 224
+//Bit 7: 0 reg_nr4_sad2bet1_lut15 // unsigned , default = 255 sad to beta1 for deghost blending, dft = 255
+#define NR4_MCNR_SAD2BET2_LUT0 ((0x2dee << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet2_lut0 // unsigned , default = 0 sad to beta2 for snr and mcnr blending, dft = 0
+//Bit 23:16 reg_nr4_sad2bet2_lut1 // unsigned , default = 1 sad to beta2 for snr and mcnr blending, dft = 2
+//Bit 15: 8 reg_nr4_sad2bet2_lut2 // unsigned , default = 2 sad to beta2 for snr and mcnr blending, dft = 4
+//Bit 7: 0 reg_nr4_sad2bet2_lut3 // unsigned , default = 4 sad to beta2 for snr and mcnr blending, dft = 8
+#define NR4_MCNR_SAD2BET2_LUT1 ((0x2def << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet2_lut4 // unsigned , default = 8 sad to beta2 for snr and mcnr blending, dft = 16
+//Bit 23:16 reg_nr4_sad2bet2_lut5 // unsigned , default = 16 sad to beta2 for snr and mcnr blending, dft = 32
+//Bit 15: 8 reg_nr4_sad2bet2_lut6 // unsigned , default = 32 sad to beta2 for snr and mcnr blending, dft = 48
+//Bit 7: 0 reg_nr4_sad2bet2_lut7 // unsigned , default = 48 sad to beta2 for snr and mcnr blending, dft = 64
+#define NR4_MCNR_SAD2BET2_LUT2 ((0x2df0 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet2_lut8 // unsigned , default = 64 sad to beta2 for snr and mcnr blending, dft = 80
+//Bit 23:16 reg_nr4_sad2bet2_lut9 // unsigned , default = 80 sad to beta2 for snr and mcnr blending, dft = 96
+//Bit 15: 8 reg_nr4_sad2bet2_lut10 // unsigned , default = 96 sad to beta2 for snr and mcnr blending, dft = 112
+//Bit 7: 0 reg_nr4_sad2bet2_lut11 // unsigned , default = 112 sad to beta2 for snr and mcnr blending, dft = 128
+#define NR4_MCNR_SAD2BET2_LUT3 ((0x2df1 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_sad2bet2_lut12 // unsigned , default = 128 sad to beta2 for snr and mcnr blending, dft = 160
+//Bit 23:16 reg_nr4_sad2bet2_lut13 // unsigned , default = 160 sad to beta2 for snr and mcnr blending, dft = 192
+//Bit 15: 8 reg_nr4_sad2bet2_lut14 // unsigned , default = 224 sad to beta2 for snr and mcnr blending, dft = 224
+//Bit 7: 0 reg_nr4_sad2bet2_lut15 // unsigned , default = 255 sad to beta2 for snr and mcnr blending, dft = 255
+#define NR4_MCNR_RO_U_SUM ((0x2df2 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_u_sum // unsigned , default = 0 sum of U of current field/frame
+#define NR4_MCNR_RO_V_SUM ((0x2df3 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_v_sum // unsigned , default = 0 sum of V of current field/frame
+#define NR4_MCNR_RO_GRDU_SUM ((0x2df4 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_grdu_sum // unsigned , default = 0 sum of gradient U of current field/frame
+#define NR4_MCNR_RO_GRDV_SUM ((0x2df5 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_grdv_sum // unsigned , default = 0 sum of gradient V of current field/frame
+#define NR4_TOP_CTRL ((0x2dff << 2) + 0xff000000)
+//Bit 31:20 reg_gclk_ctrl // unsigned , default = 0
+//Bit 19 reserved
+//Bit 18 reg_nr4_mcnr_en // unsigned , default = 1 ncnr enable or bypass, dft = 1
+//Bit 17 reg_nr2_en // unsigned , default = 1 nr2 enable, dft = 1
+//Bit 16 reg_nr4_en // unsigned , default = 1 nr4 enable, dft = 1
+//Bit 15 reg_nr2_proc_en // unsigned , default = 1
+//Bit 14 reg_det3d_en // unsigned , default = 1
+//Bit 13 di_polar_en // unsigned , default = 1 do does not have in C
+//Bit 12 reg_cfr_enable // unsigned , default = 0 0-disable; 1:enable
+//Bit 11: 9 reg_3dnr_enable_l // unsigned , default = 7 b0: Y b1:U b2:V
+//Bit 8: 6 reg_3dnr_enable_r // unsigned , default = 7 b0: Y b1:U b2:V
+//Bit 5 reg_nr4_lnbuf_ctrl // unsigned , default = 1 line buf ctrl for nr4: 0, 3lines, 1, 5lines, dft = 1
+//Bit 4 reg_nr4_snr2_en // unsigned , default = 0 snr2 enable, 0: use old snr, 1: use new snr2, dft = 1
+//Bit 3 reg_nr4_scene_change_en // unsigned , default = 1 enable scene change proc. dft = 1
+//Bit 2 nr2_sw_en // unsigned , default = 1 do does not have in C
+//Bit 1 reserved
+//Bit 0 reg_nr4_scene_change_flg // unsigned , default = 0 flags for scene change, dft = 0
+//========== nr4_mcnr_regs register end ==========//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_nr4_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_dnr_regs.h
+//
+//===========================================================================
+// VI_HIST_SPL register (16'h2e00 - 16'h2eff)
+//===========================================================================
+//
+// Reading file: vi_hist_spl_reg.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// ----------------------------
+// VI_HIST_SPL 0x2e
+// ----------------------------
+// -----------------------------------------------
+// REG_BASE: VI_HIST_SPL_VCBUS_BASE = 0x2e
+// -----------------------------------------------
+//BIT 14: 34bin only, 0&255 and other 32bins
+//Bit 13:11 hist_din_sel, 00: from vdin0 dout, 1: from vdin1, 2: from nr dout, 3: di output, 4: vpp output, 5: vd1_din, 6: vd2_din, 7:osd1_dout
+//Bit 10:8 hist_din_comp_mux, mux of [29:22], [19:12], [9:2] for hist detect
+//Bit 7:5 hist_dnlp_low the real pixels in each bins got by VI_DNLP_HISTXX should multiple with 2^(dnlp_low+3)
+//Bit 3:2 hist_din_sel the source used for hist statistics. 00: from matrix0 dout, 01: from vsc_dout, 10: from matrix1 dout, 11: form matrix1 din
+//Bit 1 hist_win_en 1'b0: hist used for full picture; 1'b1: hist used for pixels within hist window
+//Bit 0 hist_spl_en 1'b0: disable hist readback; 1'b1: enable hist readback
+#define VI_HIST_CTRL ((0x2e00 << 2) + 0xff000000)
+//Bit 28:16 hist_hstart horizontal start value to define hist window
+//Bit 12:0 hist_hend horizontal end value to define hist window
+#define VI_HIST_H_START_END ((0x2e01 << 2) + 0xff000000)
+//Bit 28:16 hist_vstart vertical start value to define hist window
+//Bit 12:0 hist_vend vertical end value to define hist window
+#define VI_HIST_V_START_END ((0x2e02 << 2) + 0xff000000)
+//Bit 15:8 hist_max maximum value
+//Bit 7:0 hist_min minimum value
+//read only
+#define VI_HIST_MAX_MIN ((0x2e03 << 2) + 0xff000000)
+//Bit 31:0 hist_spl_rd
+//counts for the total luma value
+//read only
+#define VI_HIST_SPL_VAL ((0x2e04 << 2) + 0xff000000)
+//Bit 21:0 hist_spl_pixel_count
+//counts for the total calculated pixels
+//read only
+#define VI_HIST_SPL_PIX_CNT ((0x2e05 << 2) + 0xff000000)
+//Bit 31:0 hist_chroma_sum
+//counts for the total chroma value
+//read only
+#define VI_HIST_CHROMA_SUM ((0x2e06 << 2) + 0xff000000)
+//Bit 31:16 higher hist bin
+//Bit 15:0 lower hist bin
+//0-255 are splited to 64 bins evenly, and VI_DNLP_HISTXX
+//are the statistic number of pixels that within each bin.
+//VI_DNLP_HIST00[15:0] counts for the first bin
+//VI_DNLP_HIST00[31:16] counts for the second bin
+//VI_DNLP_HIST01[15:0] counts for the third bin
+//VI_DNLP_HIST01[31:16] counts for the fourth bin
+//etc...
+//read only
+#define VI_DNLP_HIST00 ((0x2e07 << 2) + 0xff000000)
+#define VI_DNLP_HIST01 ((0x2e08 << 2) + 0xff000000)
+#define VI_DNLP_HIST02 ((0x2e09 << 2) + 0xff000000)
+#define VI_DNLP_HIST03 ((0x2e0a << 2) + 0xff000000)
+#define VI_DNLP_HIST04 ((0x2e0b << 2) + 0xff000000)
+#define VI_DNLP_HIST05 ((0x2e0c << 2) + 0xff000000)
+#define VI_DNLP_HIST06 ((0x2e0d << 2) + 0xff000000)
+#define VI_DNLP_HIST07 ((0x2e0e << 2) + 0xff000000)
+#define VI_DNLP_HIST08 ((0x2e0f << 2) + 0xff000000)
+#define VI_DNLP_HIST09 ((0x2e10 << 2) + 0xff000000)
+#define VI_DNLP_HIST10 ((0x2e11 << 2) + 0xff000000)
+#define VI_DNLP_HIST11 ((0x2e12 << 2) + 0xff000000)
+#define VI_DNLP_HIST12 ((0x2e13 << 2) + 0xff000000)
+#define VI_DNLP_HIST13 ((0x2e14 << 2) + 0xff000000)
+#define VI_DNLP_HIST14 ((0x2e15 << 2) + 0xff000000)
+#define VI_DNLP_HIST15 ((0x2e16 << 2) + 0xff000000)
+#define VI_DNLP_HIST16 ((0x2e17 << 2) + 0xff000000)
+#define VI_DNLP_HIST17 ((0x2e18 << 2) + 0xff000000)
+#define VI_DNLP_HIST18 ((0x2e19 << 2) + 0xff000000)
+#define VI_DNLP_HIST19 ((0x2e1a << 2) + 0xff000000)
+#define VI_DNLP_HIST20 ((0x2e1b << 2) + 0xff000000)
+#define VI_DNLP_HIST21 ((0x2e1c << 2) + 0xff000000)
+#define VI_DNLP_HIST22 ((0x2e1d << 2) + 0xff000000)
+#define VI_DNLP_HIST23 ((0x2e1e << 2) + 0xff000000)
+#define VI_DNLP_HIST24 ((0x2e1f << 2) + 0xff000000)
+#define VI_DNLP_HIST25 ((0x2e20 << 2) + 0xff000000)
+#define VI_DNLP_HIST26 ((0x2e21 << 2) + 0xff000000)
+#define VI_DNLP_HIST27 ((0x2e22 << 2) + 0xff000000)
+#define VI_DNLP_HIST28 ((0x2e23 << 2) + 0xff000000)
+#define VI_DNLP_HIST29 ((0x2e24 << 2) + 0xff000000)
+#define VI_DNLP_HIST30 ((0x2e25 << 2) + 0xff000000)
+#define VI_DNLP_HIST31 ((0x2e26 << 2) + 0xff000000)
+#define VI_DNLP_HIST32 ((0x2e27 << 2) + 0xff000000)
+//Bit 28:16 hist_pic_height active input data window height
+//Bit 12:0 hist_pic_width active input data window width
+#define VI_HIST_PIC_SIZE ((0x2e28 << 2) + 0xff000000)
+//Bit 15:8 hist_pix_white_value: >= this value will be white pixel
+//Bit 7:0 hist_pix_black_value: <= this value will be black pixel
+#define VI_HIST_BLACK_WHITE_VALUE ((0x2e29 << 2) + 0xff000000)
+#define VI_HIST_GCLK_CTRL ((0x2e2a << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vi_hist_spl_reg.h
+//
+//===========================================================================
+//===========================================================================
+//
+// Reading file: mcdi_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: MCDI_VCBUS_BASE = 0x2f
+// -----------------------------------------------
+////=================================================================////
+//// memc di core 0
+////=================================================================////
+#define MCDI_HV_SIZEIN ((0x2f00 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_mcdi_hsize image horizontal size (number of cols) default=1024
+//Bit 15:13, reserved
+//Bit 12: 0, reg_mcdi_vsize image vertical size (number of rows) default=1024
+#define MCDI_HV_BLKSIZEIN ((0x2f01 << 2) + 0xff000000)
+//Bit 31, reg_mcdi_vrev default = 0
+//Bit 30, reg_mcdi_hrev default = 0
+//Bit 29:28, reserved
+//Bit 27:16, reg_mcdi_blkhsize image horizontal blk size (number of cols) default=1024
+//Bit 15:13, reserved
+//Bit 11: 0, reg_mcdi_blkvsize image vertical blk size (number of rows) default=1024
+#define MCDI_BLKTOTAL ((0x2f02 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23: 0, reg_mcdi_blktotal
+#define MCDI_MOTINEN ((0x2f03 << 2) + 0xff000000)
+//Bit 31: 2, reserved
+//Bit 1, reg_mcdi_motionrefen. enable motion refinement of MA, default = 1
+//Bit 0, reg_mcdi_motionparadoxen. enable motion paradox detection, default = 1
+#define MCDI_CTRL_MODE ((0x2f04 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:26, reg_mcdi_lmvlocken 0:disable, 1: use max Lmv, 2: use no-zero Lmv, lmv lock enable mode, default = 2
+//Bit 25, reg_mcdi_reldetrptchken
+// 0: unable; 1: enable, enable repeat pattern check (not repeat mv detection) in rel det part, default = 1
+//Bit 24, reg_mcdi_reldetgmvpd22chken
+// 0: unable; 1: enable, enable pull-down 22 mode check in gmv lock mode for rel det, default = 1
+//Bit 23, reg_mcdi_pd22chken
+// 0: unable; 1: enable, enable pull-down 22 mode check (lock) function, default = 1
+//Bit 22, reg_mcdi_reldetlpfen
+// 0: unable; 1: enable, enable det value lpf, default = 1
+//Bit 21, reg_mcdi_reldetlmvpd22chken
+// 0: unable; 1: enable, enable pull-down 22 mode check in lmv lock mode for rel det, default = 1
+//Bit 20, reg_mcdi_reldetlmvdifchken
+// 0: unable; 1: enable, enable lmv dif check in lmv lock mode for rel det, default = 1
+//Bit 19, reg_mcdi_reldetgmvdifchken
+// 0: unable; 1: enable, enable lmv dif check in lmv lock mode for rel det, default = 1
+//Bit 18, reg_mcdi_reldetpd22chken
+// 0: unable; 1: enable, enable pull-down 22 mode check for rel det refinement, default = 1
+//Bit 17, reg_mcdi_reldetfrqchken
+// 0: unable; 1: enable, enable mv frequency check in rel det, default = 1
+//Bit 16, reg_mcdi_qmeen
+// 0: unable; 1: enable, enable quarter motion estimation, defautl = 1
+//Bit 15, reg_mcdi_refrptmven
+// 0: unable; 1: enable, use repeat mv in refinement, default = 1
+//Bit 14, reg_mcdi_refgmven
+// 0: unable; 1: enable, use gmv in refinement, default = 1
+//Bit 13, reg_mcdi_reflmven
+// 0: unable; 1: enable, use lmvs in refinement, default = 1
+//Bit 12, reg_mcdi_refnmven
+// 0: unable; 1: enable, use neighoring mvs in refinement, default = 1
+//Bit 11, reserved
+//Bit 10, reg_mcdi_referrfrqchken
+// 0: unable; 1: enable, enable mv frquency check while finding min err in ref, default = 1
+//Bit 9, reg_mcdi_refen
+// 0: unable; 1: enable, enable mv refinement, default = 1
+//Bit 8, reg_mcdi_horlineen
+// 0: unable; 1: enable,enable horizontal lines detection by sad map, default = 1
+//Bit 7, reg_mcdi_highvertfrqdeten
+// 0: unable; 1: enable, enable high vertical frequency pattern detection, default = 1
+//Bit 6, reg_mcdi_gmvlocken
+// 0: unable; 1: enable, enable gmv lock mode, default = 1
+//Bit 5, reg_mcdi_rptmven
+// 0: unable; 1: enable, enable repeat pattern detection, default = 1
+//Bit 4, reg_mcdi_gmven
+// 0: unable; 1: enable, enable global motion estimation, default = 1
+//Bit 3, reg_mcdi_lmven
+// 0: unable; 1: enable, enable line mv estimation for hme, default = 1
+//Bit 2, reg_mcdi_chkedgeen
+// 0: unable; 1: enable, enable check edge function, default = 1
+//Bit 1, reg_mcdi_txtdeten
+// 0: unable; 1: enable, enable texture detection, default = 1
+//Bit 0, reg_mcdi_memcen
+// 0: unable; 1: enable, enable of memc di, default = 1
+#define MCDI_UNI_MVDST ((0x2f05 << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:17, reg_mcdi_unimvdstabsseg0 segment0 for uni-mv abs, default = 1
+//Bit 16:12, reg_mcdi_unimvdstabsseg1 segment1 for uni-mv abs, default = 15
+//Bit 11: 8, reg_mcdi_unimvdstabsdifgain0 2/2, gain0 of uni-mv abs dif for segment0, normalized 2 to '1', default = 2
+//Bit 7: 5, reg_mcdi_unimvdstabsdifgain1 2/2, gain1 of uni-mv abs dif for segment1, normalized 2 to '1', default = 2
+//Bit 4: 2, reg_mcdi_unimvdstabsdifgain2 2/2, gain2 of uni-mv abs dif beyond segment1, normalized 2 to '1', default = 2
+//Bit 1: 0, reg_mcdi_unimvdstsgnshft shift for neighboring distance of uni-mv, default = 0
+#define MCDI_BI_MVDST ((0x2f06 << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:17, reg_mcdi_bimvdstabsseg0 segment0 for bi-mv abs, default = 1
+//Bit 16:12, reg_mcdi_bimvdstabsseg1 segment1 for bi-mv abs, default = 9
+//Bit 11: 8, reg_mcdi_bimvdstabsdifgain0 6/2, gain0 of bi-mv abs dif for segment0, normalized 2 to '1', default = 6
+//Bit 7: 5, reg_mcdi_bimvdstabsdifgain1 3/2, gain1 of bi-mvabs dif for segment1, normalized 2 to '1', default = 3
+//Bit 4: 2, reg_mcdi_bimvdstabsdifgain2 2/2, gain2 of bi-mvabs dif beyond segment1, normalized 2 to '1', default = 2
+//Bit 1: 0, reg_mcdi_bimvdstsgnshft shift for neighboring distance of bi-mv, default = 0
+#define MCDI_SAD_GAIN ((0x2f07 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18:17, reg_mcdi_unisadcorepxlgain uni-sad core pixels gain, default = 3
+//Bit 16, reg_mcdi_unisadcorepxlnormen enable uni-sad core pixels normalization, default = 0
+//Bit 15:11, reserved
+//Bit 10: 9, reg_mcdi_bisadcorepxlgain bi-sad core pixels gain, default = 3
+//Bit 8, reg_mcdi_bisadcorepxlnormen enable bi-sad core pixels normalization, default = 1
+//Bit 7: 3, reserved
+//Bit 2: 1, reg_mcdi_biqsadcorepxlgain bi-qsad core pixels gain, default = 3
+//Bit 0, reg_mcdi_biqsadcorepxlnormen enable bi-qsad core pixels normalization, default = 1
+#define MCDI_TXT_THD ((0x2f08 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_mcdi_txtminmaxdifthd, min max dif threshold (>=) for texture detection, default = 24
+//Bit 15: 8, reg_mcdi_txtmeandifthd, mean dif threshold (<) for texture detection, default = 9
+//Bit 7: 3, reserved
+//Bit 2: 0, reg_mcdi_txtdetthd, texture detecting threshold, 0~4, default = 2
+#define MCDI_FLT_MODESEL ((0x2f09 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28, reg_mcdi_flthorlineselmode mode for horizontal line detecting flat calculation, default = 1, same as below
+//Bit 27 reserved
+//Bit 26:24, reg_mcdi_fltgmvselmode mode for gmv flat calculation, default = 4, same as below
+//Bit 23, reserved
+//Bit 22:20, reg_mcdi_fltsadselmode mode for sad flat calculation, default = 2, same as below
+//Bit 19, reserved
+//Bit 18:16, reg_mcdi_fltbadwselmode mode for badw flat calculation, default = 3, same as below
+//Bit 15, reserved
+//Bit 14:12, reg_mcdi_fltrptmvselmode mode for repeat mv flat calculation, default = 4, same as below
+//Bit 11, reserved
+//Bit 10: 8, reg_mcdi_fltbadrelselmode mode for bad rel flat calculation, default = 4, same as below
+//Bit 7, reserved
+//Bit 6: 4, reg_mcdi_fltcolcfdselmode mode for col cfd flat calculation, default = 2, same as below
+//Bit 3, reserved
+//Bit 2: 0, reg_mcdi_fltpd22chkselmode mode for pd22 check flat calculation, default = 2, # 0:cur dif h, 1: cur dif v, 2: pre dif h, 3: pre dif v, 4: cur flt, 5: pre flt, 6: cur+pre, 7: max all(cur,pre)
+#define MCDI_CHK_EDGE_THD ((0x2f0a << 2) + 0xff000000)
+//Bit 23:28, reserved.
+//Bit 27:24, reg_mcdi_chkedgedifsadthd. thd (<=) for sad dif check, 0~8, default = 1
+//Bit 23:16, reserved.
+//Bit 15:12, reg_mcdi_chkedgemaxedgethd. max drt of edge, default = 15
+//Bit 11: 8, reg_mcdi_chkedgeminedgethd. min drt of edge, default = 2
+//Bit 7, reserved.
+//Bit 6: 0, reg_mcdi_chkedgevdifthd. thd for vertical dif in check edge, default = 14
+#define MCDI_CHK_EDGE_GAIN_OFFST ((0x2f0b << 2) + 0xff000000)
+//Bit 31:24, reserved.
+//Bit 23:20, reg_mcdi_chkedgedifthd1. thd1 for edge dif check (<=), default = 4
+//Bit 19:16, reg_mcdi_chkedgedifthd0. thd0 for edge dif check (>=), default = 15
+//Bit :15, reserved.
+//Bit 14:10, reg_mcdi_chkedgechklen. total check length for edge check, 1~24 (>0), default = 24
+//Bit 9: 8, reg_mcdi_chkedgeedgesel. final edge select mode, 0: original start edge, 1: lpf start edge, 2: orignal start+end edge, 3: lpf start+end edge, default = 1
+//Bit 7: 3, reg_mcdi_chkedgesaddstgain. distance gain for sad calc while getting edges, default = 4
+//Bit 2, reg_mcdi_chkedgechkmode. edge used in check mode, 0: original edge, 1: lpf edge, defautl = 1
+//Bit 1, reg_mcdi_chkedgestartedge. edge mode for start edge, 0: original edge, 1: lpf edge, defautl = 0
+//Bit 0, reg_mcdi_chkedgeedgelpf. edge lpf mode, 0:[0,2,4,2,0], 1:[1,2,2,2,1], default = 0
+#define MCDI_LMV_RT ((0x2f0c << 2) + 0xff000000)
+//BIt 31:15, reserved
+//Bit 14:12, reg_mcdi_lmvvalidmode valid mode for lmv calc., 100b: use char det, 010b: use flt, 001b: use hori flg
+//Bit 11:10, reg_mcdi_lmvgainmvmode four modes of mv selection for lmv weight calucluation, default = 1
+// 0: cur(x-3), lst(x-1,x,x+1); 1: cur(x-4,x-3), lst(x,x+1); 2: cur(x-5,x-4,x-3), lst(x-1,x,x+1,x+2,x+3); 3: cur(x-6,x-5,x-4,x-3), lst(x-1,x,x+1,x+2);
+//Bit 9, reg_mcdi_lmvinitmode initial lmvs at first row of input field, 0: intial value = 0; 1: inital = 32 (invalid), default = 0
+//Bit 8, reserved
+//Bit 7: 4, reg_mcdi_lmvrt0 ratio of max mv, default = 5
+//Bit 3: 0, reg_mcdi_lmvrt1 ratio of second max mv, default = 5
+#define MCDI_LMV_GAINTHD ((0x2f0d << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_lmvvxmaxgain max gain of lmv weight, default = 96
+//Bit 23, reserved
+//Bit 22:20, reg_mcdi_lmvdifthd0 dif threshold 0 (<) for small lmv, default = 1
+//Bit 19:17, reg_mcdi_lmvdifthd1 dif threshold 1 (<) for median lmv, default = 2
+//Bit 16:14, reg_mcdi_lmvdifthd2 dif threshold 2 (<) for large lmv, default = 3
+//Bit 13: 8, reg_mcdi_lmvnumlmt least/limit number of (total number - max0), default = 20
+//Bit 7: 0, reg_mcdi_lmvfltthd flt cnt thd (<) for lmv, default = 9
+#define MCDI_RPTMV_THD0 ((0x2f0e << 2) + 0xff000000)
+//Bit 31:25, reg_mcdi_rptmvslpthd2 slope thd (>=) between i and i+3/i-3 (i+4/i-4), default = 64
+//Bit 24:20, reg_mcdi_rptmvslpthd1 slope thd (>=) between i and i+2/i-2, default = 4
+//Bit 19:10, reg_mcdi_rptmvampthd2 amplitude thd (>=) between max and min, when count cycles, default = 300
+//Bit 9: 0, reg_mcdi_rptmvampthd1 amplitude thd (>=) between average of max and min, default = 400
+#define MCDI_RPTMV_THD1 ((0x2f0f << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:25, reg_mcdi_rptmvcyccntthd thd (>=) of total cycles count, default = 2
+//Bit 24:21, reg_mcdi_rptmvcycdifthd dif thd (<) of cycles length, default = 3
+//Bit 20:18, reg_mcdi_rptmvcycvldthd thd (>) of valid cycles number, default = 1
+//Bit 17:15, reg_mcdi_rptmvhalfcycminthd min length thd (>=) of half cycle, default = 2
+//Bit 14:11, reg_mcdi_rptmvhalfcycdifthd neighboring half cycle length dif thd (<), default = 5
+//Bit 10: 8, reg_mcdi_rptmvminmaxcntthd least number of valid max and min, default = 2
+//Bit 7: 5, reg_mcdi_rptmvcycminthd min length thd (>=) of cycles, default = 2
+//Bit 4: 0, reg_mcdi_rptmvcycmaxthd max length thd (<) of cycles, default = 17
+#define MCDI_RPTMV_THD2 ((0x2f10 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_mcdi_rptmvhdifthd0 higher hdif thd (>=) (vertical edge) for rpt detection, default = 8
+//Bit 15: 8, reg_mcdi_rptmvhdifthd1 hdif thd (>=) (slope edge) for rpt detection, default = 4
+//Bit 7: 0, reg_mcdi_rptmvvdifthd vdif thd (>=) (slope edge) for rpt detection, default = 1
+#define MCDI_RPTMV_SAD ((0x2f11 << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, reg_mcdi_rptmvsaddifthdgain 7x3x(16/16), gain for sad dif thd in rpt mv detection, 0~672, normalized 16 as '1', default = 336
+//Bit 15:10, reserved
+//Bit 9: 0, reg_mcdi_rptmvsaddifthdoffst offset for sad dif thd in rpt mv detection, -512~511, default = 16
+#define MCDI_RPTMV_FLG ((0x2f12 << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:16, reg_mcdi_rptmvmode select mode of mvs for repeat motion estimation, 0: hmv, 1: qmv/2, 2 or 3: qmv/4, default = 2
+//Bit 15: 8, reg_mcdi_rptmvflgcntthd thd (>=) of min count number for rptmv of whole field, for rptmv estimation, default = 64
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_rptmvflgcntrt 4/32, ratio for repeat mv flag count, normalized 32 as '1', set 31 to 32,
+#define MCDI_RPTMV_GAIN ((0x2f13 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_rptmvlftgain up repeat mv gain for hme, default = 96
+//Bit 23:16, reg_mcdi_rptmvuplftgain up left repeat mv gain for hme, default = 32
+//Bit 15: 8, reg_mcdi_rptmvupgain up repeat mv gain for hme, default = 64
+//Bit 7: 0, reg_mcdi_rptmvuprightgain up right repeat mv gain for hme, default = 32
+#define MCDI_GMV_RT ((0x2f14 << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30:24, reg_mcdi_gmvmtnrt0 ratio 0 for motion senario, set 127 to 128, normalized 128 as '1', default =32
+//Bit 23, reserved
+//Bit 22:16, reg_mcdi_gmvmtnrt1 ratio 1 for motion senario, set 127 to 128, normalized 128 as '1', default = 56
+//Bit 15, reserved
+//Bit 14: 8, reg_mcdi_gmvstlrt0 ratio 0 for still senario, set 127 to 128, normalized 128 as '1', default = 56
+//Bit 7, reserved
+//Bit 6: 0, reg_mcdi_gmvstlrt1 ratio 1 for still senario, set 127 to 128, normalized 128 as '1', default = 80
+#define MCDI_GMV_GAIN ((0x2f15 << 2) + 0xff000000)
+//Bit 31:25, reg_mcdi_gmvzeromvlockrt0 ratio 0 for locking zero mv, set 127 to 128, normalized 128 as '1', default = 100
+//Bit 24:18, reg_mcdi_gmvzeromvlockrt1 ratio 1 for locking zero mv, set 127 to 128, normalized 128 as '1', default = 112
+//Bit 17:16, reg_mcdi_gmvvalidmode valid mode for gmv calc., 10b: use flt, 01b: use hori flg, default = 3
+//Bit 15: 8, reg_mcdi_gmvvxgain gmv's vx gain when gmv locked for hme, default = 0
+//Bit 7: 0, reg_mcdi_gmvfltthd flat thd (<) for gmv calc. default = 3
+#define MCDI_HOR_SADOFST ((0x2f16 << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24:16, reg_mcdi_horsaddifthdgain 21*1/8, gain/divisor for sad dif threshold in hor line detection, normalized 8 as '1', default = 21
+//Bit 15: 8, reg_mcdi_horsaddifthdoffst offset for sad dif threshold in hor line detection, -128~127, default = 0
+//Bit 7: 0, reg_mcdi_horvdifthd threshold (>=) of vertical dif of next block for horizontal line detection, default = 24
+#define MCDI_REF_MV_NUM ((0x2f17 << 2) + 0xff000000)
+//Bit 31: 2, reserved
+//Bit 1: 0, reg_mcdi_refmcmode. motion compensated mode used in refinement, 0: pre, 1: next, 2: (pre+next)/2, default = 0
+#define MCDI_REF_BADW_THD_GAIN ((0x2f18 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:24, reg_mcdi_refbadwcnt2gain. gain for badwv count num==3, default = 6
+//Bit 23:20, reg_mcdi_refbadwcnt1gain. gain for badwv count num==2, default = 3
+//Bit 19:16, reg_mcdi_refbadwcnt0gain. gain for badwv count num==1, default = 1
+//Bit 15:12, reg_mcdi_refbadwthd3. threshold 3 for detect badweave with largest average luma, default = 4
+//Bit 11: 8, reg_mcdi_refbadwthd2. threshold 2 for detect badweave with third smallest average luma, default = 3
+//Bit 7: 4, reg_mcdi_refbadwthd1. threshold 1 for detect badweave with second smallest average luma, default = 2
+//Bit 3: 0, reg_mcdi_refbadwthd0. threshold 0 for detect badweave with smallest average luma, default = 1
+#define MCDI_REF_BADW_SUM_GAIN ((0x2f19 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12: 8, reg_mcdi_refbadwsumgain0. sum gain for r channel, 0~16, default = 8
+//Bit 7: 5, reserved
+//Bit 4, reg_mcdi_refbadwcalcmode. mode for badw calculation, 0:sum, 1:max, default = 0
+//Bit 3: 0, reserved
+#define MCDI_REF_BS_THD_GAIN ((0x2f1a << 2) + 0xff000000)
+//Bit 31:28, reg_mcdi_refbsudgain1. up & down block stregth gain1, normalized to 8 as '1', default = 2
+//Bit 27:24, reg_mcdi_refbsudgain0. up & down block stregth gain0, normalized to 8 as '1', default = 4
+//Bit 23:19, reserved
+//Bit 18:16, reg_mcdi_refbslftgain. left block strength gain, default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_refbsthd1. threshold 1 for detect block stregth in refinment, default = 16
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_refbsthd0. threshold 0 for detect block stregth in refinment, default = 8
+#define MCDI_REF_ERR_GAIN0 ((0x2f1b << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30:24, reg_mcdi_referrnbrdstgain. neighoring mv distances gain for err calc. in ref, normalized to 8 as '1', default = 48
+//Bit 23:20, reserved
+//Bit 19:16, reg_mcdi_referrbsgain. bs gain for err calc. in ref, normalized to 8 as '1', default = 4
+//Bit 15, reserved
+//Bit 14: 8, reg_mcdi_referrbadwgain. badw gain for err calc. in ref, normalized to 8 as '1', default = 64
+//Bit 7: 4, reserved
+//Bit 3: 0, reg_mcdi_referrsadgain. sad gain for err calc. in ref, normalized to 8 as '1', default = 4
+#define MCDI_REF_ERR_GAIN1 ((0x2f1c << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:16, reg_mcdi_referrchkedgegain. check edge gain for err calc. in ref, normalized to 8 as '1', default = 4
+//Bit 15:12, reserved
+//Bit 11: 8, reg_mcdi_referrlmvgain. (locked) lmv gain for err calc. in ref, normalized to 8 as '1', default = 0
+//Bit 7: 4, reserved
+//Bit 3: 0, reg_mcdi_referrgmvgain. (locked) gmv gain for err calc. in ref, normalized to 8 as '1', default = 0
+#define MCDI_REF_ERR_FRQ_CHK ((0x2f1d << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:24, reg_mcdi_referrfrqgain. gain for mv frquency, normalized to 4 as '1', default = 10
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_referrfrqmax. max gain for mv frquency check, default = 31
+//Bit 15, reserved
+//Bit 14:12, reg_mcdi_ref_errfrqmvdifthd2. mv dif threshold 2 (<) for mv frquency check, default = 3
+//Bit 11, reserved
+//Bit 10: 8, reg_mcdi_ref_errfrqmvdifthd1. mv dif threshold 1 (<) for mv frquency check, default = 2
+//Bit 7, reserved
+//Bit 6: 4, reg_mcdi_ref_errfrqmvdifthd0. mv dif threshold 0 (<) for mv frquency check, default = 1
+//Bit 3: 0, reserved
+#define MCDI_QME_LPF_MSK ((0x2f1e << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:24, reg_mcdi_qmechkedgelpfmsk0. lpf mask0 for chk edge in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7
+//Bit 23:20, reserved
+//Bit 19:16, reg_mcdi_qmebslpfmsk0. lpf mask0 for bs in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7
+//Bit 15:12, reserved
+//Bit 11: 8, reg_mcdi_qmebadwlpfmsk0. lpf mask0 for badw in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7
+//Bit 7: 4, reserved
+//Bit 3: 0, reg_mcdi_qmesadlpfmsk0. lpf mask0 for sad in qme, 0~8, msk1 = (8-msk0), normalized to 8 as '1', default = 7
+#define MCDI_REL_DIF_THD_02 ((0x2f1f << 2) + 0xff000000)
+//Bit 31:24, reserved.
+//Bit 23:16, reg_mcdi_reldifthd2. thd (<) for (hdif+vdif), default = 9
+//Bit 15: 8, reg_mcdi_reldifthd1. thd (<) for (vdif), default = 5
+//Bit 7: 0, reg_mcdi_reldifthd0. thd (>=) for (hdif-vdif), default = 48
+#define MCDI_REL_DIF_THD_34 ((0x2f20 << 2) + 0xff000000)
+//Bit 31:16, reserved.
+//Bit 15: 8, reg_mcdi_reldifthd4. thd (<) for (hdif), default = 255
+//Bit 7: 0, reg_mcdi_reldifthd3. thd (>=) for (vdif-hdif), default = 48
+#define MCDI_REL_BADW_GAIN_OFFST_01 ((0x2f21 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_relbadwoffst1. offset for badw adj, for flat block, -128~127, default = 0
+//Bit 23:16, reg_mcdi_relbadwgain1. gain for badw adj, for flat block, default = 128
+//Bit 15: 8, reg_mcdi_relbadwoffst0. offset for badw adj, for vertical block, -128~127, default = 0
+//Bit 7: 0, reg_mcdi_relbadwgain0. gain for badw adj, for vertical block, default = 160
+#define MCDI_REL_BADW_GAIN_OFFST_23 ((0x2f22 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_relbadwoffst3. offset for badw adj, for other block, -128~127, default = 0
+//Bit 23:16, reg_mcdi_relbadwgain3. gain for badw adj, for other block, default = 48
+//Bit 15: 8, reg_mcdi_relbadwoffst2. offset for badw adj, for horizontal block, -128~127, default = 0
+//Bit 7: 0, reg_mcdi_relbadwgain2. gain for badw adj, for horizontal block, default = 48
+#define MCDI_REL_BADW_THD_GAIN_OFFST ((0x2f23 << 2) + 0xff000000)
+//Bit 31:23, reserved.
+//Bit 22:16, reg_mcdi_relbadwoffst. offset for badw thd adj, -64~63, default = 0
+//Bit 15: 8, reserved.
+//Bit 7: 0, reg_mcdi_relbadwthdgain. gain0 for badw thd adj, normalized to 16 as '1', default = 16
+#define MCDI_REL_BADW_THD_MIN_MAX ((0x2f24 << 2) + 0xff000000)
+//Bit 31:18, reserved.
+//Bit 17: 8, reg_mcdi_relbadwthdmax. max for badw thd adj, default = 256
+//Bit 7: 0, reg_mcdi_relbadwthdmin. min for badw thd adj, default = 16
+#define MCDI_REL_SAD_GAIN_OFFST_01 ((0x2f25 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_relsadoffst1. offset for sad adj, for flat block, -128~127, default = 0
+//Bit 23:20, reserved.
+//Bit 19:16, reg_mcdi_relsadgain1. gain for sad adj, for flat block, normalized to 8 as '1', default = 8
+//Bit 15: 8, reg_mcdi_relsadoffst0. offset for sad adj, for vertical block, -128~127, default = 0
+//Bit 7: 4, reserved.
+//Bit 3: 0, reg_mcdi_relsadgain0. gain for sad adj, for vertical block, normalized to 8 as '1', default = 6
+#define MCDI_REL_SAD_GAIN_OFFST_23 ((0x2f26 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_relsadoffst3. offset for sad adj, for other block, -128~127, default = 0
+//Bit 23:20, reserved.
+//Bit 19:16, reg_mcdi_relsadgain3. gain for sad adj, for other block, normalized to 8 as '1', default = 8
+//Bit 15: 8, reg_mcdi_relsadoffst2. offset for sad adj, for horizontal block, -128~127, default = 0
+//Bit 7: 4, reserved.
+//Bit 3: 0, reg_mcdi_relsadgain2. gain for sad adj, for horizontal block, normalized to 8 as '1', default = 12
+#define MCDI_REL_SAD_THD_GAIN_OFFST ((0x2f27 << 2) + 0xff000000)
+//Bit 31:24, reserved.
+//Bit 23:16, reg_mcdi_relsadoffst. offset for sad thd adj, -128~127, default = 0
+//Bit 15:10, reserved.
+//Bit 9: 0, reg_mcdi_relsadthdgain. gain for sad thd adj, 21*2/16, normalized to 16 as '1', default = 42
+#define MCDI_REL_SAD_THD_MIN_MAX ((0x2f28 << 2) + 0xff000000)
+//Bit 31:27, reserved.
+//Bit 26:16, reg_mcdi_relsadthdmax. max for sad thd adj, 21*32, default = 672
+//Bit 15: 9, reserved.
+//Bit 8: 0, reg_mcdi_relsadthdmin. min for sad thd adj, 21*2, default = 42
+#define MCDI_REL_DET_GAIN_00 ((0x2f29 << 2) + 0xff000000)
+//Bit 31:21, reserved.
+//Bit 20:16, reg_mcdi_reldetbsgain0. gain0 (gmv locked) for bs, for det. calc. normalized to 16 as '1', default = 8
+//Bit 15:14, reserved.
+//Bit 13: 8, reg_mcdi_reldetbadwgain0. gain0 (gmv locked) for badw, for det. calc. normalized to 16 as '1', default = 12
+//Bit 7: 5, reserved.
+//Bit 4: 0, reg_mcdi_reldetsadgain0. gain0 (gmv locked) for qsad, for det. calc. normalized to 16 as '1', default = 8
+#define MCDI_REL_DET_GAIN_01 ((0x2f2a << 2) + 0xff000000)
+//Bit 31:14, reserved.
+//Bit 12: 8, reg_mcdi_reldetchkedgegain0. gain0 (gmv locked) for chk_edge, for det. calc. normalized to 16 as '1', default = 2
+//Bit 7, reserved.
+//Bit 6: 0, reg_mcdi_reldetnbrdstgain0. gain0 (gmv locked) for neighoring dist, for det. calc. normalized to 16 as '1', default = 24
+#define MCDI_REL_DET_GAIN_10 ((0x2f2b << 2) + 0xff000000)
+//Bit 31:21, reserved.
+//Bit 20:16, reg_mcdi_reldetbsgain1. gain1 (lmv locked) for bs, for det. calc. normalized to 16 as '1', default = 0
+//Bit 15:14, reserved.
+//Bit 13: 8, reg_mcdi_reldetbadwgain1. gain1 (lmv locked) for badw, for det. calc. normalized to 16 as '1', default = 8
+//Bit 7: 5, reserved.
+//Bit 4: 0, reg_mcdi_reldetsadgain1. gain1 (lmv locked) for qsad, for det. calc. normalized to 16 as '1', default = 8
+#define MCDI_REL_DET_GAIN_11 ((0x2f2c << 2) + 0xff000000)
+//Bit 31:14, reserved.
+//Bit 12: 8, reg_mcdi_reldetchkedgegain1. gain1 (lmv locked) for chk_edge, for det. calc. normalized to 16 as '1', default = 0
+//Bit 7, reserved.
+//Bit 6: 0, reg_mcdi_reldetnbrdstgain1. gain1 (lmv locked) for neighoring dist, for det. calc. normalized to 16 as '1', default = 24
+#define MCDI_REL_DET_GAIN_20 ((0x2f2d << 2) + 0xff000000)
+//Bit 31:21, reserved.
+//Bit 20:16, reg_mcdi_reldetbsgain2. gain2 (no locked) for bs, for det. calc. normalized to 16 as '1', default = 12
+//Bit 15:14, reserved.
+//Bit 13: 8, reg_mcdi_reldetbadwgain2. gain2 (no locked) for badw, for det. calc. normalized to 16 as '1', default = 32
+//Bit 7: 5, reserved.
+//Bit 4: 0, reg_mcdi_reldetsadgain2. gain2 (no locked) for qsad, for det. calc. normalized to 16 as '1', default = 16
+#define MCDI_REL_DET_GAIN_21 ((0x2f2e << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, reg_mcdi_reldetoffst. offset for rel calculation, for det. calc. -512~511, default = 0
+//Bit 15:14, reserved.
+//Bit 12: 8, reg_mcdi_reldetchkedgegain2. gain2 (no locked) for chk_edge, for det. calc. normalized to 16 as '1', default = 10
+//Bit 7, reserved.
+//Bit 6: 0, reg_mcdi_reldetnbrdstgain2. gain2 (no locked) for neighoring dist, for det. calc. normalized to 16 as '1', default = 32
+#define MCDI_REL_DET_GMV_DIF_CHK ((0x2f2f << 2) + 0xff000000)
+//Bit 31:24, reserved.
+//Bit 23:16, reg_mcdi_reldetgmvfltthd. flat thd (>=) for gmv lock decision, default = 0
+//Bit 15, reserved.
+//Bit 14:12, reg_mcdi_reldetgmvdifthd. dif thd (>=) for current mv different from gmv for gmv dif check, actually used in Lmv lock check, default = 3
+//Bit 11, reserved.
+//Bit 10: 8, reg_mcdi_reldetgmvdifmin. min mv dif for gmv dif check, default = 1, note: dif between reg_mcdi_rel_det_gmv_dif_max and reg_mcdi_rel_det_gmv_dif_min should be; 0,1,3,7, not work for others
+//Bit 7: 4, reg_mcdi_reldetgmvdifmax. max mv dif for gmv dif check, default = 4
+//Bit 3: 1, reserved
+//Bit 0, reg_mcdi_reldetgmvdifmvmode. mv mode used for gmv dif check, 0: use refmv, 1: use qmv, default = 0
+#define MCDI_REL_DET_LMV_DIF_CHK ((0x2f30 << 2) + 0xff000000)
+//Bit 31:24, reserved.
+//Bit 23:16, reg_mcdi_reldetlmvfltthd. flat thd (>=) for lmv lock decision, default = 12
+//Bit 15:14, reserved.
+//Bit 13:12, reg_mcdi_reldetlmvlockchkmode. lmv lock check mode, 0:cur Lmv, 1: cur & (last | next), 2: last & cur & next Lmv, default = 1
+//Bit 11, reserved.
+//Bit 10: 8, reg_mcdi_reldetlmvdifmin. min mv dif for lmv dif check, default = 1, note: dif between reg_mcdi_rel_det_lmv_dif_max and reg_mcdi_rel_det_lmv_dif_min should be; 0,1,3,7, not work for others
+//Bit 7: 4, reg_mcdi_reldetlmvdifmax. max mv dif for lmv dif check, default = 4
+//Bit 3: 1, reserved
+//Bit 0, reg_mcdi_reldetlmvdifmvmode. mv mode used for lmv dif check, 0: use refmv, 1: use qmv, default = 0
+#define MCDI_REL_DET_FRQ_CHK ((0x2f31 << 2) + 0xff000000)
+//Bit 31:12, reserved.
+//Bit 11: 8, reg_mcdi_reldetfrqgain. gain for frequency check, normalized to 4 as '1', default = 10
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetfrqmax. max value for frequency check, default = 31
+#define MCDI_REL_DET_PD22_CHK ((0x2f32 << 2) + 0xff000000)
+//Bit 31:18, reserved.
+//Bit 17: 8, reg_mcdi_reldetpd22chkoffst. offset for pd22 check happened, default = 512
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetpd22chkgain. gain for pd22 check happened, normalized to 8 as '1', default = 12
+#define MCDI_REL_DET_RPT_CHK_ROW ((0x2f33 << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:16, reg_mcdi_reldetrptchkendrow. end row (<) number for repeat check, default = 2047
+//Bit 15:11, reserved
+//Bit 10: 0, reg_mcdi_reldetrptchkstartrow. start row (>=) number for repeat check, default = 0
+#define MCDI_REL_DET_RPT_CHK_GAIN_QMV ((0x2f34 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_mcdi_reldetrptchkqmvmax. max thd (<) of abs qmv for repeat check, default = 15, note that quarter mv's range is -63~63
+//Bit 23:22, reserved
+//Bit 21:16, reg_mcdi_reldetrptchkqmvmin. min thd (>=) of abs qmv for repeat check, default = 10, note that quarter mv's range is -63~63
+//Bit 15, reserved/
+//Bit 14: 4, reg_mcdi_reldetrptchkoffst. offset for repeat check, default = 512
+//Bit 3: 0, reg_mcdi_reldetrptchkgain. gain for repeat check, normalized to 8 as '1', default = 4
+#define MCDI_REL_DET_RPT_CHK_THD_0 ((0x2f35 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_mcdi_reldetrptchkzerosadthd. zero sad thd (<) for repeat check, default = 255
+//Bit 15:14, reserved.
+//Bit 13: 8, reg_mcdi_reldetrptchkzerobadwthd. zero badw thd (>=) for repeat check, default = 16
+//Bit 7: 4, reserved
+//Bit 3: 0, reg_mcdi_reldetrptchkfrqdifthd. frequency dif thd (<) for repeat check, 0~10, default = 5
+#define MCDI_REL_DET_RPT_CHK_THD_1 ((0x2f36 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_mcdi_reldetrptchkvdifthd. vertical dif thd (<) for repeat check, default = 16
+//Bit 7: 0, reg_mcdi_reldetrptchkhdifthd. horizontal dif thd (>=) for repeat check, default = 16
+#define MCDI_REL_DET_LPF_DIF_THD ((0x2f37 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetlpfdifthd3. hdif thd (<) for lpf selection of horizontal block, default = 9
+//Bit 23:16, reg_mcdi_reldetlpfdifthd2. vdif-hdif thd (>=) for lpf selection of horizontal block, default = 48
+//Bit 15: 8, reg_mcdi_reldetlpfdifthd1. vdif thd (<) for lpf selection of vertical block, default = 9
+//Bit 7: 0, reg_mcdi_reldetlpfdifthd0. hdif-vdif thd (>=) for lpf selection of vertical block, default = 48
+#define MCDI_REL_DET_LPF_MSK_00_03 ((0x2f38 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_mcdi_reldetlpfmsk03. det lpf mask03 for gmv/lmv locked mode, 0~16, default = 1
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_reldetlpfmsk02. det lpf mask02 for gmv/lmv locked mode, 0~16, default = 1
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_reldetlpfmsk01. det lpf mask01 for gmv/lmv locked mode, 0~16, default = 5
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetlpfmsk00. det lpf mask00 for gmv/lmv locked mode, 0~16, default = 8
+#define MCDI_REL_DET_LPF_MSK_04_12 ((0x2f39 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_mcdi_reldetlpfmsk12. det lpf mask12 for vertical blocks, 0~16, default = 0
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_reldetlpfmsk11. det lpf mask11 for vertical blocks, 0~16, default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_reldetlpfmsk10. det lpf mask10 for vertical blocks, 0~16, default = 16
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetlpfmsk04. det lpf mask04 for gmv/lmv locked mode, 0~16, default = 1
+#define MCDI_REL_DET_LPF_MSK_13_21 ((0x2f3a << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_mcdi_reldetlpfmsk21. det lpf mask21 for horizontal blocks, 0~16, default = 6
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_reldetlpfmsk20. det lpf mask20 for horizontal blocks, 0~16, default = 8
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_reldetlpfmsk14. det lpf mask14 for vertical blocks, 0~16, default = 0
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetlpfmsk13. det lpf mask13 for vertical blocks, 0~16, default = 0
+#define MCDI_REL_DET_LPF_MSK_22_30 ((0x2f3b << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_mcdi_reldetlpfmsk30. det lpf mask30 for other blocks, 0~16, default = 16
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_reldetlpfmsk24. det lpf mask24 for horizontal blocks, 0~16, default = 1
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_reldetlpfmsk23. det lpf mask23 for horizontal blocks, 0~16, default = 0
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetlpfmsk22. det lpf mask22 for horizontal blocks, 0~16, default = 1
+#define MCDI_REL_DET_LPF_MSK_31_34 ((0x2f3c << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_mcdi_reldetlpfmsk34. det lpf mask34 for other blocks, 0~16, default = 0
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_reldetlpfmsk33. det lpf mask33 for other blocks, 0~16, default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_reldetlpfmsk32. det lpf mask32 for other blocks, 0~16, default = 0
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_reldetlpfmsk31. det lpf mask31 for other blocks, 0~16, default = 0
+//Note: there are four group lpf masks from addr 37~3b, each group sum equal to 16.
+#define MCDI_REL_DET_MIN ((0x2f3d << 2) + 0xff000000)
+//Bit 31: 7, reserved
+//Bit 6: 0, reg_mcdi_reldetmin. min of detected value, default = 16
+#define MCDI_REL_DET_LUT_0_3 ((0x2f3e << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetmaplut3. default = 8
+//Bit 23:16, reg_mcdi_reldetmaplut2. default = 4
+//Bit 15: 8, reg_mcdi_reldetmaplut1. default = 2
+//Bit 7: 0, reg_mcdi_reldetmaplut0. default = 0
+#define MCDI_REL_DET_LUT_4_7 ((0x2f3f << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetmaplut7. default = 64
+//Bit 23:16, reg_mcdi_reldetmaplut6. default = 48
+//Bit 15: 8, reg_mcdi_reldetmaplut5. default = 32
+//Bit 7: 0, reg_mcdi_reldetmaplut4. default = 16
+#define MCDI_REL_DET_LUT_8_11 ((0x2f40 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetmaplut11. default = 160
+//Bit 23:16, reg_mcdi_reldetmaplut10. default = 128
+//Bit 15: 8, reg_mcdi_reldetmaplut9. default = 96
+//Bit 7: 0, reg_mcdi_reldetmaplut8. default = 80
+#define MCDI_REL_DET_LUT_12_15 ((0x2f41 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetmaplut15. default = 255
+//Bit 23:16, reg_mcdi_reldetmaplut14. default = 240
+//Bit 15: 8, reg_mcdi_reldetmaplut13. default = 224
+//Bit 7: 0, reg_mcdi_reldetmaplut12. default = 192
+#define MCDI_REL_DET_COL_CFD_THD ((0x2f42 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetcolcfdfltthd. thd for flat smaller than (<) of column cofidence, default = 5
+//Bit 23:16, reg_mcdi_reldetcolcfdthd1. thd for rel larger than (>=) in rel calc. mode col confidence without gmv locking, default = 160
+//Bit 15: 8, reg_mcdi_reldetcolcfdthd0. thd for rel larger than (>=) in rel calc. mode col confidence when gmv locked, default = 100
+//Bit 7: 2, reg_mcdi_reldetcolcfdbadwthd. thd for badw larger than (>=) in qbadw calc. mode of column cofidence, default = 16
+//Bit 1, reserved
+//Bit 0, reg_mcdi_reldetcolcfdcalcmode. calc. mode for column cofidence, 0: use rel, 1: use qbadw, default = 0
+#define MCDI_REL_DET_COL_CFD_AVG_LUMA ((0x2f43 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_reldetcolcfdavgmin1. avg luma min1 (>=) for column cofidence, valid between 16~235, default = 235
+//Bit 23:16, reg_mcdi_reldetcolcfdavgmax1. avg luma max1 (<) for column cofidence, valid between 16~235, default = 235
+//Bit 15: 8, reg_mcdi_reldetcolcfdavgmin0. avg luma min0 (>=) for column cofidence, valid between 16~235, default = 16
+//Bit 7: 0, reg_mcdi_reldetcolcfdavgmax0. avg luma max0 (<) for column cofidence, valid between 16~235, default = 21
+#define MCDI_REL_DET_BAD_THD_0 ((0x2f44 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_mcdi_reldetbadsadthd. thd (>=) for bad sad, default = 120 (480/4)
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_mcdi_reldetbadbadwthd. thd (>=) for bad badw, 0~42, default = 12
+#define MCDI_REL_DET_BAD_THD_1 ((0x2f45 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_mcdi_reldetbadrelfltthd. thd (>=) of flat for bad rel detection, default = 4
+//Bit 15: 8, reg_mcdi_reldetbadrelthd1. thd (>=) for bad rel without gmv/lmv locked, default = 160
+//Bit 7: 0, reg_mcdi_reldetbadrelthd0. thd (>=) for bad rel with gmv/lmv locked, default = 120
+#define MCDI_PD22_CHK_THD ((0x2f46 << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24:16, reg_mcdi_pd22chksaddifthd. sad dif thd (>=) for (pd22chksad - qsad) for pd22 check, default = 64
+//Bit 15:14, reserved
+//Bit 13: 8, reg_mcdi_pd22chkqmvthd. thd (>=) of abs qmv for pd22 check, default = 2
+//Bit 7: 0, reg_mcdi_pd22chkfltthd. thd (>=) of flat for pd22 check, default = 4
+#define MCDI_PD22_CHK_GAIN_OFFST_0 ((0x2f47 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_pd22chkedgeoffst0. offset0 of pd22chkedge from right film22 phase, -128~127, default = 0
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_pd22chkedgegain0. gain0 of pd22chkedge from right film22 phase, normalized to 16 as '1', default = 16
+//Bit 15:12, reserved
+//Bit 11: 8, reg_mcdi_pd22chkbadwoffst0. offset0 of pd22chkbadw from right film22 phase, -8~7, default = 0
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_pd22chkbadwgain0. gain0 of pd22chkbadw from right film22 phase, normalized to 16 as '1', default = 8
+#define MCDI_PD22_CHK_GAIN_OFFST_1 ((0x2f48 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_pd22chkedgeoffst1. offset1 of pd22chkedge from right film22 phase, -128~127, default = 0
+//Bit 23:21, reserved
+//Bit 20:16, reg_mcdi_pd22chkedgegain1. gain1 of pd22chkedge from right film22 phase, normalized to 16 as '1', default = 16
+//Bit 15:12, reserved
+//Bit 11: 8, reg_mcdi_pd22chkbadwoffst1. offset1 of pd22chkbadw from right film22 phase, -8~7, default = 0
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_pd22chkbadwgain1. gain1 of pd22chkbadw from right film22 phase, normalized to 16 as '1', default = 12
+#define MCDI_LMV_LOCK_CNT_THD_GAIN ((0x2f49 << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:16, reg_mcdi_lmvlockcntmax. max lmv lock count number, default = 6
+//Bit 15:12, reg_mcdi_lmvlockcntoffst. offset for lmv lock count, -8~7, default = 0
+//Bit 11: 8, reg_mcdi_lmvlockcntgain. gain for lmv lock count, normalized 8 as '1', 15 is set to 16, default = 8
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_lmvlockcntthd. lmv count thd (>=) before be locked, 1~31, default = 4
+#define MCDI_LMV_LOCK_ABS_DIF_THD ((0x2f4a << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:24, reg_mcdi_lmvlockdifthd2. lmv dif thd for third part, before locked, default = 1
+//Bit 23, reserved
+//Bit 22:20, reg_mcdi_lmvlockdifthd1. lmv dif thd for second part, before locked, default = 1
+//Bit 19, reserved
+//Bit 18:16, reg_mcdi_lmvlockdifthd0. lmv dif thd for first part, before locked, default = 1
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_lmvlockabsmax. max abs (<) of lmv to be locked, default = 24
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_lmvlockabsmin. min abs (>=) of lmv to be locked, default = 1
+#define MCDI_LMV_LOCK_ROW ((0x2f4b << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:16, reg_mcdi_lmvlockendrow. end row (<) for lmv lock, default = 2047
+//Bit 15:11, reserved
+//Bit 10: 0, reg_mcdi_lmvlockstartrow. start row (>=) for lmv lock, default = 0
+#define MCDI_LMV_LOCK_RT_MODE ((0x2f4c << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:24, reg_mcdi_lmvlockextmode. extend lines for lmv lock check, check how many lines for lmv locking, default = 2
+//Bit 23:16, reg_mcdi_lmvlockfltcntrt. ratio of flt cnt for lock check, normalized 256 as '1', 255 is set to 256, default = 32
+//Bit 15: 8, reg_mcdi_lmvlocklmvcntrt1. ratio when use non-zero lmv for lock check, normalized 256 as '1', 255 is set to 256, default = 48
+//Bit 7: 0, reg_mcdi_lmvlocklmvcntrt0. ratio when use max lmv for lock check, normalized 256 as '1', 255 is set to 256, default = 106
+#define MCDI_GMV_LOCK_CNT_THD_GAIN ((0x2f4d << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:16, reg_mcdi_gmvlockcntmax. max gmv lock count number, default = 6
+//Bit 15:12, reg_mcdi_gmvlockcntoffst. offset for gmv lock count, -8~7, default = 0
+//Bit 11: 8, reg_mcdi_gmvlockcntgain. gain for gmv lock count, normalized 8 as '1', 15 is set to 16, default = 8
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_gmvlockcntthd. gmv count thd (>=) before be locked, 1~31, default = 4
+#define MCDI_GMV_LOCK_ABS_DIF_THD ((0x2f4e << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:24, reg_mcdi_gmvlockdifthd2. gmv dif thd for third part, before locked, default = 3
+//Bit 23, reserved
+//Bit 22:20, reg_mcdi_gmvlockdifthd1. gmv dif thd for second part, before locked, default = 2
+//Bit 19, reserved
+//Bit 18:16, reg_mcdi_gmvlockdifthd0. gmv dif thd for first part, before locked, default = 1
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_gmvlockabsmax. max abs of gmv to be locked, default = 15
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_gmvlockabsmin. min abs of gmv to be locked, default = 1
+#define MCDI_HIGH_VERT_FRQ_DIF_THD ((0x2f4f << 2) + 0xff000000)
+//Bit 31: 0, reg_mcdi_highvertfrqfldavgdifthd. high_vert_frq field average luma dif thd (>=), 3*Blk_Width*Blk_Height, set by software, default = 103680
+#define MCDI_HIGH_VERT_FRQ_DIF_DIF_THD ((0x2f50 << 2) + 0xff000000)
+//Bit 31: 0, reg_mcdi_highvertfrqfldavgdifdifthd. high_vert_frq field average luma dif's dif thd (<), 3*Blk_Width*Blk_Height, set by software, default = 103680
+#define MCDI_HIGH_VERT_FRQ_RT_GAIN ((0x2f51 << 2) + 0xff000000)
+//Bit 31:20, reserved
+//Bit 19:16, reg_mcdi_highvertfrqcntthd. high_vert_frq count thd (>=) before locked, 1~31, default = 4
+//Bit 15: 8, reg_mcdi_highvertfrqbadsadrt. ratio for high_vert_frq bad sad count, normalized 256 as '1', 255 is set to 256, default = 24
+//Bit 7: 0, reg_mcdi_highvertfrqbadbadwrt. ratio for high_vert_frq badw count, normalized 256 as '1', 255 is set to 256, default = 130
+#define MCDI_MOTION_PARADOX_THD ((0x2f52 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:24, reg_mcdi_motionparadoxcntthd. motion paradox count thd (>=) before locked, 1~31, default = 4
+//Bit 23:22, reserved
+//Bit 21:16, reg_mcdi_motionparadoxgmvthd. abs gmv thd (<) of motion paradox, 0~32, note that 32 means invalid gmv, be careful, default = 32
+//Bit 15: 0, reserved
+#define MCDI_MOTION_PARADOX_RT ((0x2f53 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_mcdi_motionparadoxbadsadrt. ratio for field bad sad count of motion paradox, normalized 256 as '1', 255 is set to 256, default = 24
+//Bit 15: 8, reg_mcdi_motionparadoxbadrelrt. ratio for field bad reliabilty count of motion paradox, normalized 256 as '1', 255 is set to 256, default = 120
+//Bit 7: 0, reg_mcdi_motionparadoxmtnrt. ratio for field motion count of motion paradox, normalized 256 as '1', 255 is set to 256, default = 218
+#define MCDI_MOTION_REF_THD ((0x2f54 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:20, reg_mcdi_motionrefoffst. motion ref additive offset, default = 15
+//Bit 19:16, reg_mcdi_motionrefgain. motion ref gain, normalized 8 as '1', default = 8
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_motionrefrptmvthd. abs thd (>=) of rpt mv (0~31, 32 means invalid) for motion ref, default = 1
+//Bit 7: 2, reg_mcdi_motionrefqmvthd. min thd (>=) of abs qmv for motion ref, note that quarter mv's range is -63~63, default = 2
+//Bit 1: 0, reg_mcdi_motionreflpfmode. Mv and (8 x repeat flg) 's lpf mode of motion refinement, 0: no lpf, 1: [1 2 1], 2: [1 2 2 2 1], default = 1
+#define MCDI_REL_COL_REF_RT ((0x2f55 << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_mcdi_relcolrefrt. ratio for column cofidence level against column number, for refinement, default = 135
+#define MCDI_PD22_CHK_THD_RT ((0x2f56 << 2) + 0xff000000)
+//Bit 31:27, reserved
+//Bit 26:16, reg_mcdi_pd22chkfltcntrt. ratio for flat count of field pulldown 22 check, normalized 2048 as '1', 2047 is set to 2048, default = 1
+//Bit 15: 8, reg_mcdi_pd22chkcntrt. ratio of pulldown 22 check count, normalized 256 as '1', 255 is set to 256, default = 100
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_pd22chkcntthd. thd (>=) for pd22 count before locked, 1~31, default = 4
+#define MCDI_CHAR_DET_DIF_THD ((0x2f57 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_mcdi_chardetminmaxdifthd. thd (>=) for dif between min and max value, default = 64
+//Bit 15: 8, reg_mcdi_chardetmaxdifthd. thd (<) for dif between max value, default = 17
+//Bit 7: 0, reg_mcdi_chardetmindifthd. thd (<) for dif between min value, default = 17
+#define MCDI_CHAR_DET_CNT_THD ((0x2f58 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_mcdi_chardettotcntthd. thd (>=) for total count, 0~21, default = 18
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_chardetmaxcntthd. thd (>=) for max count, 0~21, default = 1
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_chardetmincntthd. thd (>=) for min count, 0~21, default = 1
+//new add
+#define MCDI_PD_22_CHK_WND0_X ((0x2f59 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_mcdi_pd22chkwnd0_x1 u13, x1 for window 0, HSIZE-1, software control, default = 719
+//Bit 15:13, reserved
+//Bit 12: 0, reg_mcdi_pd22chkwnd0_x0 u13, x0 for window 0, software control, default = 0
+#define MCDI_PD_22_CHK_WND0_Y ((0x2f5a << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_mcdi_pd22chkwnd0_y1 u13, y1 for window 0 software control, default = 39
+//Bit 15:13, reserved
+//Bit 12: 0, reg_mcdi_pd22chkwnd0_y0 u13, y0 for window 0, software control, default = 0
+#define MCDI_PD_22_CHK_WND1_X ((0x2f5b << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_mcdi_pd22chkwnd1_x1 u13, x1 for window 1, HSIZE-1, software control, default = 719
+//Bit 15:13, reserved
+//Bit 12: 0, reg_mcdi_pd22chkwnd1_x0 u13, x0 for window 1, software control, default = 0
+#define MCDI_PD_22_CHK_WND1_Y ((0x2f5c << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_mcdi_pd22chkwnd1_y1 u13, y1 for window 1 software control, default = 199
+//Bit 15:13, reserved
+//Bit 12: 0, reg_mcdi_pd22chkwnd1_y0 u13, y0 for window 1, software control, default = 40
+#define MCDI_PD_22_CHK_FRC_LMV ((0x2f5d << 2) + 0xff000000)
+//Bit 31:11, reserved
+//Bit 10, reg_mcdi_pd22chklmvchk2 u1, lmv lock check while force vof for each windows, default = 1
+//Bit 9, reg_mcdi_pd22chklmvchk1 u1, lmv lock check while force vof for each windows, default = 0
+//Bit 8, reg_mcdi_pd22chklmvchk0 u1, lmv lock check while force vof for each windows, default = 0
+//Bit 7, reserved
+//Bit 6, reg_mcdi_pd22chkfrcpd2 u1, force pd flags for each windows, default = 0
+//Bit 5, reg_mcdi_pd22chkfrcpd1 u1, force pd flags for each windows, default = 0
+//Bit 4, reg_mcdi_pd22chkfrcpd0 u1, force pd flags for each windows, default = 0
+//Bit 3, reserved
+//Bit 2, reg_mcdi_pd22chkfrcvof2 u1, force vof flags for each windows, default = 1
+//Bit 1, reg_mcdi_pd22chkfrcvof1 u1, force vof flags for each windows, default = 0
+//Bit 0, reg_mcdi_pd22chkfrcvof0 u1, force vof flags for each windows, default = 0
+#define MCDI_PD_22_CHK_FLG_CNT ((0x2f5e << 2) + 0xff000000)
+//Bit 31:27, reserved.
+//Bit 26, reg_mcdi_pd22chkflg2. pull down 22 flag of prevoius one field. initial = 0
+//Bit 25, reg_mcdi_pd22chkflg1. pull down 22 flag of prevoius one field. initial = 0
+//Bit 24, reg_mcdi_pd22chkflg. pull down 22 flag of prevoius one field. initial = 0
+//Bit 23:16, reg_mcdi_pd22chkcnt2. pull down 22 count till prevoius one field. initial = 0
+//Bit 15: 8, reg_mcdi_pd22chkcnt1. pull down 22 count till prevoius one field. initial = 0
+//Bit 7: 0, reg_mcdi_pd22chkcnt. pull down 22 count till prevoius one field. initial = 0
+#define MCDI_RO_FLD_PD_22_PRE_CNT1 ((0x2fca << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22precnt1. prevoius pd22 check count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_FOR_CNT1 ((0x2fcb << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22forcnt1. forward pd22 check count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_FLT_CNT1 ((0x2fcc << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22fltcnt1. flat count (for pd22 check) of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_PRE_CNT2 ((0x2fcd << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22precnt2. prevoius pd22 check count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_FOR_CNT2 ((0x2fce << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22forcnt2. forward pd22 check count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_FLT_CNT2 ((0x2fcf << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22fltcnt2. flat count (for pd22 check) of whole pre one field (block based). initial = 0
+#define MCDI_FIELD_MV ((0x2f60 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_pd22chkcnt
+//Bit 23:16, reg_mcdi_fieldgmvcnt
+//Bit 15, reg_mcdi_pd22chkflg
+//Bit 14, reg_mcdi_fieldgmvlock
+//Bit 13: 8, reg_mcdi_fieldrptmv. last field rpt mv
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_mcdi_fieldgmv. last field gmv
+#define MCDI_FIELD_HVF_PRDX_CNT ((0x2f61 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_motionparadoxcnt.
+//Bit 23:17, reserved
+//Bit 16, reg_mcdi_motionparadoxflg.
+//Bit 15: 8, reg_mcdi_highvertfrqcnt.
+//Bit 7: 4, reserved
+//Bit 3: 2, reg_mcdi_highvertfrqphase.
+//Bit 1, reserved
+//Bit 0, reg_mcdi_highvertfrqflg.
+#define MCDI_FIELD_LUMA_AVG_SUM_0 ((0x2f62 << 2) + 0xff000000)
+//Bit 31: 0, reg_mcdi_fld_luma_avg_sum0.
+#define MCDI_FIELD_LUMA_AVG_SUM_1 ((0x2f63 << 2) + 0xff000000)
+//Bit 31: 0, reg_mcdi_fld_luma_avg_sum1.
+#define MCDI_YCBCR_BLEND_CRTL ((0x2f64 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_mcdi_ycbcrblendgain. ycbcr blending gain for cbcr in ycbcr. default = 0
+//Bit 7: 2, reserved.
+//Bit 1: 0, reg_mcdi_ycbcrblendmode. 0:y+cmb(cb,cr), 1:med(r,g,b), 2:max(r,g,b), default = 2
+#define MCDI_MCVECWR_CANVAS_SIZE ((0x2f65 << 2) + 0xff000000)
+#define MCDI_MCVECRD_CANVAS_SIZE ((0x2f66 << 2) + 0xff000000)
+#define MCDI_MCINFOWR_CANVAS_SIZE ((0x2f67 << 2) + 0xff000000)
+#define MCDI_MCINFORD_CANVAS_SIZE ((0x2f68 << 2) + 0xff000000)
+#define MCDI_MCVECWR_X ((0x2f92 << 2) + 0xff000000)
+#define MCDI_MCVECWR_Y ((0x2f93 << 2) + 0xff000000)
+#define MCDI_MCVECWR_CTRL ((0x2f94 << 2) + 0xff000000)
+#define MCDI_MCVECRD_X ((0x2f95 << 2) + 0xff000000)
+#define MCDI_MCVECRD_Y ((0x2f96 << 2) + 0xff000000)
+#define MCDI_MCVECRD_CTRL ((0x2f97 << 2) + 0xff000000)
+#define MCDI_MCINFOWR_X ((0x2f98 << 2) + 0xff000000)
+#define MCDI_MCINFOWR_Y ((0x2f99 << 2) + 0xff000000)
+#define MCDI_MCINFOWR_CTRL ((0x2f9a << 2) + 0xff000000)
+#define MCDI_MCINFORD_X ((0x2f9b << 2) + 0xff000000)
+#define MCDI_MCINFORD_Y ((0x2f9c << 2) + 0xff000000)
+#define MCDI_MCINFORD_CTRL ((0x2f9d << 2) + 0xff000000)
+#define MCDI_LMVLCKSTEXT_0 ((0x2f69 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, mcdi_lmvlckstext_1 lmv lck blog 1 line start
+//Bit 15:12, reserved
+//Bit 11: 0, mcdi_lmvlckstext_0 lmv lck blog 0 line start
+#define MCDI_LMVLCKSTEXT_1 ((0x2f6a << 2) + 0xff000000)
+//Bit 31 , mcdi_refnewmode new ref me mv array order
+//Bit 30 , mcdi_ref_lmv_lck_en use locked line mvs for ref
+//Bit 29:28, mcdi_lmvlckupdw_ext up/down extend lines for locked lmv line's
+//Bit 27:12, mcdi_lmvlckmin lmv lck blog height limit
+//Bit 15:12, reserved
+//Bit 11: 0, mcdi_lmvlckstext_2 lmv lck blog 2 line start
+#define MCDI_LMVLCKEDEXT_0 ((0x2f6b << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, mcdi_lmvlckedext_1 lmv lck blog 1 line end
+//Bit 15:12, reserved
+//Bit 11: 0, mcdi_lmvlckedext_0 lmv lck blog 0 line end
+#define MCDI_LMVLCKEDEXT_1 ((0x2f6c << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11: 0, mcdi_lmvlckedext_2 lmv lck blog 2 line end
+// ================================================================== MC registers ========================================================================================================
+#define MCDI_MC_CRTL ((0x2f70 << 2) + 0xff000000)
+//Bit 31: 9, reserved
+//Bit 8, reg_mcdi_mcpreflg. flag to use previous field for MC, 0:forward field, 1: previous field, default = 1
+//Bit 7, reg_mcdi_mcrelrefbycolcfden. enable rel refinement by column cofidence in mc blending, default = 1
+//Bit 6: 5, reg_mcdi_mclpfen. enable mc pixles/rel lpf, 0:disable, 1: lpf rel, 2: lpf mc pxls, 3: lpf both rel and mc pxls, default = 0
+//Bit 4: 2, reg_mcdi_mcdebugmode. enable mc debug mode, 0:disable, 1: split left/right, 2: split top/bottom, 3: debug mv, 4: debug rel, default = 0
+//Bit 1: 0, reg_mcdi_mcen. mcdi enable mode, 0:disable, 1: blend with ma, 2: full mc, default = 1
+#define MCDI_MC_LPF_MSK_0 ((0x2f71 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_mcdi_mclpfmsk02. mc lpf coef. 2 for pixel 0 of current block, normalized 16 as '1', default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_mclpfmsk01. mc lpf coef. 1 for pixel 0 of current block, normalized 16 as '1', default = 9
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_mclpfmsk00. mc lpf coef. 0 for pixel 0 of current block, normalized 16 as '1', default = 7
+#define MCDI_MC_LPF_MSK_1 ((0x2f72 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_mcdi_mclpfmsk12. mc lpf coef. 2 for pixel 1 of current block, 0~16, normalized 16 as '1', default = 0
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_mclpfmsk11. mc lpf coef. 1 for pixel 1 of current block, 0~16, normalized 16 as '1', default = 11
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_mclpfmsk10. mc lpf coef. 0 for pixel 1 of current block, 0~16, normalized 16 as '1', default = 5
+#define MCDI_MC_LPF_MSK_2 ((0x2f73 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_mcdi_mclpfmsk22. mc lpf coef. 2 for pixel 2 of current block, 0~16, normalized 16 as '1', default = 1
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_mclpfmsk21. mc lpf coef. 1 for pixel 2 of current block, 0~16, normalized 16 as '1', default = 14
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_mclpfmsk20. mc lpf coef. 0 for pixel 2 of current block, 0~16, normalized 16 as '1', default = 1
+#define MCDI_MC_LPF_MSK_3 ((0x2f74 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_mcdi_mclpfmsk32. mc lpf coef. 2 for pixel 3 of current block, 0~16, normalized 16 as '1', default = 5
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_mclpfmsk31. mc lpf coef. 1 for pixel 3 of current block, 0~16, normalized 16 as '1', default = 11
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_mclpfmsk30. mc lpf coef. 0 for pixel 3 of current block, 0~16, normalized 16 as '1', default = 0
+#define MCDI_MC_LPF_MSK_4 ((0x2f75 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:16, reg_mcdi_mclpfmsk42. mc lpf coef. 2 for pixel 4 of current block, 0~16, normalized 16 as '1', default = 7
+//Bit 15:13, reserved
+//Bit 12: 8, reg_mcdi_mclpfmsk41. mc lpf coef. 1 for pixel 4 of current block, 0~16, normalized 16 as '1', default = 9
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_mcdi_mclpfmsk40. mc lpf coef. 0 for pixel 4 of current block, 0~16, normalized 16 as '1', default = 0
+#define MCDI_MC_REL_GAIN_OFFST_0 ((0x2f76 << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25, reg_mcdi_mcmotionparadoxflg. flag of motion paradox, initial with 0 and read from software, default = 0
+//Bit 24, reg_mcdi_mchighvertfrqflg. flag of high vert frq, initial with 0 and read from software, default = 0
+//Bit 23:16, reg_mcdi_mcmotionparadoxoffst. offset (rel + offset) for rel (MC blending coef.) refinement if motion paradox detected before MC blending before MC blending, default = 128
+//Bit 15:12, reserved
+//Bit 11: 8, reg_mcdi_mcmotionparadoxgain. gain for rel (MC blending coef.) refinement if motion paradox detected before MC blending, normalized 8 as '1', set 15 to 16, default = 8
+//Bit 7: 4, reg_mcdi_mchighvertfrqoffst. minus offset (alpha - offset) for motion (MA blending coef.) refinement if high vertical frequency detected before MA blending, default = 15
+//Bit 3: 0, reg_mcdi_mchighvertfrqgain. gain for motion (MA blending coef.) refinement if high vertical frequency detected before MA blending, normalized 8 as '1', set 15 to 16, default = 8
+#define MCDI_MC_REL_GAIN_OFFST_1 ((0x2f77 << 2) + 0xff000000)
+//Bit 31:24, reg_mcdi_mcoutofboundrayoffst. offset (rel + offset) for rel (MC blending coef.) refinement if MC pointed out of boundray before MC blending before MC blending, default = 255
+//Bit 23:20, reserved
+//Bit 19:16, reg_mcdi_mcoutofboundraygain. gain for rel (MC blending coef.) refinement if MC pointed out of boundray before MC blending, normalized 8 as '1', set 15 to 16, default = 8
+//Bit 15: 8, reg_mcdi_mcrelrefbycolcfdoffst. offset (rel + offset) for rel (MC blending coef.) refinement if motion paradox detected before MC blending before MC blending, default = 255
+//Bit 7: 4, reserved.
+//Bit 3: 0, reg_mcdi_mcrelrefbycolcfdgain. gain for rel (MC blending coef.) refinement if column cofidence failed before MC blending, normalized 8 as '1', set 15 to 16, default = 8
+#define MCDI_MC_COL_CFD_0 ((0x2f78 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_0. column cofidence value 0 read from software. initial = 0
+#define MCDI_MC_COL_CFD_1 ((0x2f79 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_1. column cofidence value 1 read from software. initial = 0
+#define MCDI_MC_COL_CFD_2 ((0x2f7a << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_2. column cofidence value 2 read from software. initial = 0
+#define MCDI_MC_COL_CFD_3 ((0x2f7b << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_3. column cofidence value 3 read from software. initial = 0
+#define MCDI_MC_COL_CFD_4 ((0x2f7c << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_4. column cofidence value 4 read from software. initial = 0
+#define MCDI_MC_COL_CFD_5 ((0x2f7d << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_5. column cofidence value 5 read from software. initial = 0
+#define MCDI_MC_COL_CFD_6 ((0x2f7e << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_6. column cofidence value 6 read from software. initial = 0
+#define MCDI_MC_COL_CFD_7 ((0x2f7f << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_7. column cofidence value 7 read from software. initial = 0
+#define MCDI_MC_COL_CFD_8 ((0x2f80 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_8. column cofidence value 8 read from software. initial = 0
+#define MCDI_MC_COL_CFD_9 ((0x2f81 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_9. column cofidence value 9 read from software. initial = 0
+#define MCDI_MC_COL_CFD_10 ((0x2f82 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_10. column cofidence value 10 read from software. initial = 0
+#define MCDI_MC_COL_CFD_11 ((0x2f83 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_11. column cofidence value 11 read from software. initial = 0
+#define MCDI_MC_COL_CFD_12 ((0x2f84 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_12. column cofidence value 12 read from software. initial = 0
+#define MCDI_MC_COL_CFD_13 ((0x2f85 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_13. column cofidence value 13 read from software. initial = 0
+#define MCDI_MC_COL_CFD_14 ((0x2f86 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_14. column cofidence value 14 read from software. initial = 0
+#define MCDI_MC_COL_CFD_15 ((0x2f87 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_15. column cofidence value 15 read from software. initial = 0
+#define MCDI_MC_COL_CFD_16 ((0x2f88 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_16. column cofidence value 16 read from software. initial = 0
+#define MCDI_MC_COL_CFD_17 ((0x2f89 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_17. column cofidence value 17 read from software. initial = 0
+#define MCDI_MC_COL_CFD_18 ((0x2f8a << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_18. column cofidence value 18 read from software. initial = 0
+#define MCDI_MC_COL_CFD_19 ((0x2f8b << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_19. column cofidence value 19 read from software. initial = 0
+#define MCDI_MC_COL_CFD_20 ((0x2f8c << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_20. column cofidence value 20 read from software. initial = 0
+#define MCDI_MC_COL_CFD_21 ((0x2f8d << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_21. column cofidence value 21 read from software. initial = 0
+#define MCDI_MC_COL_CFD_22 ((0x2f8e << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_22. column cofidence value 22 read from software. initial = 0
+#define MCDI_MC_COL_CFD_23 ((0x2f8f << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_23. column cofidence value 23 read from software. initial = 0
+#define MCDI_MC_COL_CFD_24 ((0x2f90 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_24. column cofidence value 24 read from software. initial = 0
+#define MCDI_MC_COL_CFD_25 ((0x2f91 << 2) + 0xff000000)
+//Bit 31: 0, mcdi_mc_col_cfd_25. column cofidence value 25 read from software. initial = 0
+// ===================================================================================== PRE RO Registers ==========================================================================================
+#define MCDI_RO_FLD_LUMA_AVG_SUM ((0x2fa0 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldlumaavgsum. block's luma avg sum of current filed (block based). initial = 0
+#define MCDI_RO_GMV_VLD_CNT ((0x2fa1 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_gmvvldcnt. valid gmv's count of pre one filed (block based). initial = 0
+#define MCDI_RO_RPT_FLG_CNT ((0x2fa2 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_rptflgcnt. repeat mv's count of pre one filed (block based). initial = 0
+#define MCDI_RO_FLD_BAD_SAD_CNT ((0x2fa3 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldbadsadcnt. bad sad count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_BAD_BADW_CNT ((0x2fa4 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldbadbadwcnt. bad badw count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_BAD_REL_CNT ((0x2fa5 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldbadrelcnt. bad rel count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_MTN_CNT ((0x2fa6 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldmtncnt. motion count of whole pre one field (pixel based). initial = 0
+#define MCDI_RO_FLD_VLD_CNT ((0x2fa7 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldvldcnt. valid motion count of whole pre one field (pixel based). initial = 0
+#define MCDI_RO_FLD_PD_22_PRE_CNT ((0x2fa8 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22precnt. prevoius pd22 check count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_FOR_CNT ((0x2fa9 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22forcnt. forward pd22 check count of whole pre one field (block based). initial = 0
+#define MCDI_RO_FLD_PD_22_FLT_CNT ((0x2faa << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_fldpd22fltcnt. flat count (for pd22 check) of whole pre one field (block based). initial = 0
+#define MCDI_RO_HIGH_VERT_FRQ_FLG ((0x2fab << 2) + 0xff000000)
+//Bit 31:16, reserved.
+//Bit 15: 8, ro_mcdi_highvertfrqcnt. high vertical frequency count till prevoius one field. initial = 0
+//Bit 7: 3, reserved.
+//Bit 2: 1, ro_mcdi_highvertfrqphase. high vertical frequency phase of prevoius one field. initial = 2
+//Bit 0, ro_mcdi_highvertfrqflg. high vertical frequency flag of prevoius one field. initial = 0
+#define MCDI_RO_GMV_LOCK_FLG ((0x2fac << 2) + 0xff000000)
+//Bit 31:16, reserved.
+//Bit 15: 8, ro_mcdi_gmvlckcnt. global mv lock count till prevoius one field. initial = 0
+//Bit 7: 2, ro_mcdi_gmv. global mv of prevoius one field. -31~31, initial = 32 (invalid value)
+//Bit 1, ro_mcdi_zerogmvlckflg. zero global mv lock flag of prevoius one field. initial = 0
+//Bit 0, ro_mcdi_gmvlckflg. global mv lock flag of prevoius one field. initial = 0
+#define MCDI_RO_RPT_MV ((0x2fad << 2) + 0xff000000)
+//Bit 5: 0, ro_mcdi_rptmv. repeate mv of prevoius one field. -31~31, initial = 32 (invalid value)
+#define MCDI_RO_MOTION_PARADOX_FLG ((0x2fae << 2) + 0xff000000)
+//Bit 31:16, reserved.
+//Bit 15: 8, ro_mcdi_motionparadoxcnt. motion paradox count till prevoius one field. initial = 0
+//Bit 7: 1, reserved.
+//Bit 0, ro_mcdi_motionparadoxflg. motion paradox flag of prevoius one field. initial = 0
+#define MCDI_RO_PD_22_FLG ((0x2faf << 2) + 0xff000000)
+//Bit 31:27, reserved.
+//Bit 26, ro_mcdi_pd22flg2. pull down 22 flag of prevoius one field. initial = 0
+//Bit 25, ro_mcdi_pd22flg1. pull down 22 flag of prevoius one field. initial = 0
+//Bit 24, ro_mcdi_pd22flg. pull down 22 flag of prevoius one field. initial = 0
+//Bit 23:16, ro_mcdi_pd22cnt2. pull down 22 count till prevoius one field. initial = 0
+//Bit 15: 8, ro_mcdi_pd22cnt1. pull down 22 count till prevoius one field. initial = 0
+//Bit 7: 0, ro_mcdi_pd22cnt. pull down 22 count till prevoius one field. initial = 0
+#define MCDI_RO_COL_CFD_0 ((0x2fb0 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_0. column cofidence value 0. initial = 0
+#define MCDI_RO_COL_CFD_1 ((0x2fb1 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_1. column cofidence value 1. initial = 0
+#define MCDI_RO_COL_CFD_2 ((0x2fb2 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_2. column cofidence value 2. initial = 0
+#define MCDI_RO_COL_CFD_3 ((0x2fb3 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_3. column cofidence value 3. initial = 0
+#define MCDI_RO_COL_CFD_4 ((0x2fb4 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_4. column cofidence value 4. initial = 0
+#define MCDI_RO_COL_CFD_5 ((0x2fb5 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_5. column cofidence value 5. initial = 0
+#define MCDI_RO_COL_CFD_6 ((0x2fb6 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_6. column cofidence value 6. initial = 0
+#define MCDI_RO_COL_CFD_7 ((0x2fb7 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_7. column cofidence value 7. initial = 0
+#define MCDI_RO_COL_CFD_8 ((0x2fb8 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_8. column cofidence value 8. initial = 0
+#define MCDI_RO_COL_CFD_9 ((0x2fb9 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_9. column cofidence value 9. initial = 0
+#define MCDI_RO_COL_CFD_10 ((0x2fba << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_10. column cofidence value 10. initial = 0
+#define MCDI_RO_COL_CFD_11 ((0x2fbb << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_11. column cofidence value 11. initial = 0
+#define MCDI_RO_COL_CFD_12 ((0x2fbc << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_12. column cofidence value 12. initial = 0
+#define MCDI_RO_COL_CFD_13 ((0x2fbd << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_13. column cofidence value 13. initial = 0
+#define MCDI_RO_COL_CFD_14 ((0x2fbe << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_14. column cofidence value 14. initial = 0
+#define MCDI_RO_COL_CFD_15 ((0x2fbf << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_15. column cofidence value 15. initial = 0
+#define MCDI_RO_COL_CFD_16 ((0x2fc0 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_16. column cofidence value 16. initial = 0
+#define MCDI_RO_COL_CFD_17 ((0x2fc1 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_17. column cofidence value 17. initial = 0
+#define MCDI_RO_COL_CFD_18 ((0x2fc2 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_18. column cofidence value 18. initial = 0
+#define MCDI_RO_COL_CFD_19 ((0x2fc3 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_19. column cofidence value 19. initial = 0
+#define MCDI_RO_COL_CFD_20 ((0x2fc4 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_20. column cofidence value 20. initial = 0
+#define MCDI_RO_COL_CFD_21 ((0x2fc5 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_21. column cofidence value 21. initial = 0
+#define MCDI_RO_COL_CFD_22 ((0x2fc6 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_22. column cofidence value 22. initial = 0
+#define MCDI_RO_COL_CFD_23 ((0x2fc7 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_23. column cofidence value 23. initial = 0
+#define MCDI_RO_COL_CFD_24 ((0x2fc8 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_24. column cofidence value 24. initial = 0
+#define MCDI_RO_COL_CFD_25 ((0x2fc9 << 2) + 0xff000000)
+//Bit 31: 0, ro_mcdi_col_cfd_25. column cofidence value 25. initial = 0
+// add space 8'hd0-8'hef
+//
+// Reading file: dipd_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// using 8'he0-8'hef
+#define DIPD_COMB_CTRL0 ((0x2fd0 << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl0
+#define DIPD_COMB_CTRL1 ((0x2fd1 << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl1
+#define DIPD_COMB_CTRL2 ((0x2fd2 << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl2
+#define DIPD_COMB_CTRL3 ((0x2fd3 << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl3
+#define DIPD_COMB_CTRL4 ((0x2fd4 << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl4
+#define DIPD_COMB_CTRL5 ((0x2fd5 << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl5
+#define DIPD_RO_COMB_0 ((0x2fd6 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_0
+#define DIPD_RO_COMB_1 ((0x2fd7 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_1
+#define DIPD_RO_COMB_2 ((0x2fd8 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_2
+#define DIPD_RO_COMB_3 ((0x2fd9 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_3
+#define DIPD_RO_COMB_4 ((0x2fda << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_4
+#define DIPD_RO_COMB_5 ((0x2fdb << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_5
+#define DIPD_RO_COMB_6 ((0x2fdc << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_6
+#define DIPD_RO_COMB_7 ((0x2fdd << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_7
+#define DIPD_RO_COMB_8 ((0x2fde << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_8
+#define DIPD_RO_COMB_9 ((0x2fdf << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_9
+#define DIPD_RO_COMB_10 ((0x2fe0 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_10
+#define DIPD_RO_COMB_11 ((0x2fe1 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_11
+#define DIPD_RO_COMB_12 ((0x2fe2 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_12
+#define DIPD_RO_COMB_13 ((0x2fe3 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_13
+#define DIPD_RO_COMB_14 ((0x2fe4 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_14
+#define DIPD_RO_COMB_15 ((0x2fe5 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_15
+#define DIPD_RO_COMB_16 ((0x2fe6 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_16
+#define DIPD_RO_COMB_17 ((0x2fe7 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_17
+#define DIPD_RO_COMB_18 ((0x2fe8 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_18
+#define DIPD_RO_COMB_19 ((0x2fe9 << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_19
+#define DIPD_RO_COMB_20 ((0x2fea << 2) + 0xff000000)
+//Bit 31:0, ro_pd_comb_20
+#define DIPD_COMB_CTRL6 ((0x2feb << 2) + 0xff000000)
+//Bit 31:0, reg_pd_comb_ctrl6
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dipd_regs.h
+//
+// addr space 8'hf0-8'hff
+//
+// Reading file: nr3_tnr_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define NR3_MODE ((0x2ff0 << 2) + 0xff000000)
+//Bit 31: 6 reserved
+//Bit 5 reg_nr3_vtxt_mode // unsigned , default = 0 0: avg; 1:MAX
+//Bit 4 reg_3dnr_nr3_cbyy_ignor_coop // unsigned , default = 0 ignore coop condition for cbyy motion decision
+//Bit 3 reg_3dnr_nr3_ybyc_ignor_cnoop // unsigned , default = 0 ignore cnoop condition for ybyc motion decision
+//Bit 2: 0 reg_3dnr_nr3_suremot_txt_mode // unsigned , default = 3 0: cur, 1:p2; 2: (cur+p2)/2; 3/up: min(cur,p2)
+#define NR3_COOP_PARA ((0x2ff1 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:20 reg_3dnr_nr3_coop_mode // unsigned , default = 2 0 original pixel 1: [1 2 1]/4 lpf; 2: [1 2 2 2 1]/8; 3: 3x3 lpf
+//Bit 19:16 reg_3dnr_nr3_coop_ratio // unsigned , default = 8 cur and p2 color oop decision ratio: (avg1<(dif1*ratio/8 + ofst));
+//Bit 15: 8 reg_3dnr_nr3_coop_ofset // signed , default = -1 cur and p2 color oop decision ofst: (avg1<(dif1*ratio/8 + ofst));
+//Bit 7: 0 reg_3dnr_nr3_coop_sat_thrd // unsigned , default = 0 cur and p2 color oop decision min(sat0,sat1) threshold;
+#define NR3_CNOOP_GAIN ((0x2ff2 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:20 reg_3dnr_nr3_cnoop_ratio0 // unsigned , default = 8 cur and p2 color noop decision ratio0: (avg1<(MAX(sat0,sat2)*ratio0/8 + ofst0));
+//Bit 19:16 reg_3dnr_nr3_cnoop_ratio1 // unsigned , default = 8 cur and p2 color noop decision ratio1: (dif1<(MIN(sat0,sat2)*ratio1/8 + ofst1));
+//Bit 15: 8 reg_3dnr_nr3_cnoop_ofset0 // signed , default = 25 cur and p2 color noop decision ofset0: (avg1<(MAX(sat0,sat2)*ratio0/8 + ofst0));
+//Bit 7: 0 reg_3dnr_nr3_cnoop_ofset1 // signed , default = 0 cur and p2 color noop decision ofset1: (dif1<(MIN(sat0,sat2)*ratio1/8 + ofst1));
+#define NR3_YMOT_PARA ((0x2ff3 << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19 reg_3dnr_nr3_ymot_only_en // unsigned , default = 1 enable signal for ignor chroma motion: (ytxt &coop)
+//Bit 18 reg_3dnr_nr3_ymot_only_cmtmode // unsigned , default = 1 0: cmot=ymot; 1: cmot = MIN(ymot, cmot)
+//Bit 17:16 reg_3dnr_nr3_ymot_only_txtmode // unsigned , default = 0 0, min(txt0,txt2); 1, max(txt0,txt2);2, (txt0+txt2)/2; 3: sat(txt0, txt2)
+//Bit 15: 8 reg_3dnr_nr3_ymot_only_txtthrd // unsigned , default = 10 threshold to luma texture to decide use ymot only
+//Bit 7: 0 reg_3dnr_nr3_ymot_only_motthrd // unsigned , default = 30 threshold to luma motion to decide use ymot only
+#define NR3_CMOT_PARA ((0x2ff4 << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19 reg_3dnr_nr3_cmot_only_en // unsigned , default = 1 enable signal for ignor luma motion: (ctxt &cnoop)
+//Bit 18 reg_3dnr_nr3_cmot_only_ymtmode // unsigned , default = 0 0: ymot=cmot+ymot/4; 1: ymot = MIN(ymot, cmot)
+//Bit 17:16 reg_3dnr_nr3_cmot_only_txtmode // unsigned , default = 0 0, min(txt0,txt2); 1, max(txt0,txt2);2, (txt0+txt2)/2; 3: sat(txt0, txt2)
+//Bit 15: 8 reg_3dnr_nr3_cmot_only_txtthrd // unsigned , default = 20 threshold to chroma texture to decide use cmot only
+//Bit 7: 0 reg_3dnr_nr3_cmot_only_motthrd // unsigned , default = 15 threshold to chroma motion to decide use cmot only
+#define NR3_SUREMOT_YGAIN ((0x2ff5 << 2) + 0xff000000)
+//Bit 31:24 reg_3dnr_nr3_suremot_dec_yrate // unsigned , default = 16 (norm 16)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+//Bit 23:16 reg_3dnr_nr3_suremot_dec_yofst // unsigned , default = 12 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+//Bit 15: 8 reg_3dnr_nr3_suremot_frc_ygain // unsigned , default = 64 (norm 8)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+//Bit 7: 0 reg_3dnr_nr3_suremot_frc_yofst // unsigned , default = 20 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+#define NR3_SUREMOT_CGAIN ((0x2ff6 << 2) + 0xff000000)
+//Bit 31:24 reg_3dnr_nr3_suremot_dec_crate // unsigned , default = 34 (norm 16)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+//Bit 23:16 reg_3dnr_nr3_suremot_dec_cofst // unsigned , default = 38 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+//Bit 15: 8 reg_3dnr_nr3_suremot_frc_cgain // unsigned , default = 64 (norm 8)lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+//Bit 7: 0 reg_3dnr_nr3_suremot_frc_cofst // unsigned , default = 20 lpfMot>(dec_rate*txt +ofst) then force lpfMot*frc_gain+frc_ofset
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: nr3_tnr_regs.h
+//
+#define LBUF_TOP_CTRL ((0x2fff << 2) + 0xff000000)
+//bit 23:22 mode_444c422
+//bit 21:20 mode_422c444
+//bit 17 lbuf_fmt444_mode
+//bit 16 lbuf_line5_mode
+//bit 12:0 pre_lbuf_size
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: mcdi_regs.h
+//
+//===========================================================================
+// VPU_VLOCK register (16'h3000 - 16'h30ff)
+//===========================================================================
+//
+// Reading file: vpu_vlock_reg.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// ----------------------------
+// VPU_VLOCK 0x30
+// ----------------------------
+// -----------------------------------------------
+// REG_BASE: VPU_VLOCK_VCBUS_BASE = 0x30
+// -----------------------------------------------
+#define VPU_VLOCK_CTRL ((0x3000 << 2) + 0xff000000)
+#define VPU_VLOCK_MISC_CTRL ((0x3001 << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP0_ACCUM_LMT ((0x3002 << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP0_CTRL0 ((0x3003 << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP1_CTRL0 ((0x3004 << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP1_IMISSYNC_MAX ((0x3005 << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP1_IMISSYNC_MIN ((0x3006 << 2) + 0xff000000)
+#define VPU_VLOCK_OVWRITE_ACCUM0 ((0x3007 << 2) + 0xff000000)
+#define VPU_VLOCK_OVWRITE_ACCUM1 ((0x3008 << 2) + 0xff000000)
+#define VPU_VLOCK_OUTPUT0_CAPT_LMT ((0x3009 << 2) + 0xff000000)
+#define VPU_VLOCK_OUTPUT0_PLL_LMT ((0x300a << 2) + 0xff000000)
+#define VPU_VLOCK_OUTPUT1_CAPT_LMT ((0x300b << 2) + 0xff000000)
+#define VPU_VLOCK_OUTPUT1_PLL_LMT ((0x300c << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP1_PHSDIF_TGT ((0x300d << 2) + 0xff000000)
+#define VPU_VLOCK_RO_LOOP0_ACCUM ((0x300e << 2) + 0xff000000)
+#define VPU_VLOCK_RO_LOOP1_ACCUM ((0x300f << 2) + 0xff000000)
+#define VPU_VLOCK_OROW_OCOL_MAX ((0x3010 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_VS_I_DIST ((0x3011 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_VS_O_DIST ((0x3012 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_LINE_PIX_ADJ ((0x3013 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_OUTPUT_00_01 ((0x3014 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_OUTPUT_10_11 ((0x3015 << 2) + 0xff000000)
+#define VPU_VLOCK_MX4096 ((0x3016 << 2) + 0xff000000)
+#define VPU_VLOCK_STBDET_WIN0_WIN1 ((0x3017 << 2) + 0xff000000)
+#define VPU_VLOCK_STBDET_CLP ((0x3018 << 2) + 0xff000000)
+#define VPU_VLOCK_STBDET_ABS_WIN0 ((0x3019 << 2) + 0xff000000)
+#define VPU_VLOCK_STBDET_ABS_WIN1 ((0x301a << 2) + 0xff000000)
+#define VPU_VLOCK_STBDET_SGN_WIN0 ((0x301b << 2) + 0xff000000)
+#define VPU_VLOCK_STBDET_SGN_WIN1 ((0x301c << 2) + 0xff000000)
+#define VPU_VLOCK_ADJ_EN_SYNC_CTRL ((0x301d << 2) + 0xff000000)
+#define VPU_VLOCK_GCLK_EN ((0x301e << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP1_ACCUM_LMT ((0x301f << 2) + 0xff000000)
+#define VPU_VLOCK_RO_M_INT_FRAC ((0x3020 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_PH_DIS ((0x3021 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_PH_ERR ((0x3022 << 2) + 0xff000000)
+#define VPU_VLOCK_LOCK_TH ((0x3023 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_LCK_FRM ((0x3024 << 2) + 0xff000000)
+#define VPU_VLOCK_WIN0_TH ((0x3025 << 2) + 0xff000000)
+#define VPU_VLOCK_WIN0_RATIO ((0x3026 << 2) + 0xff000000)
+#define VPU_VLOCK_WIN0_FILTER_CNTL ((0x3027 << 2) + 0xff000000)
+#define VPU_VLOCK_WIN1_TH ((0x3028 << 2) + 0xff000000)
+#define VPU_VLOCK_WIN1_RATIO ((0x3029 << 2) + 0xff000000)
+#define VPU_VLOCK_WIN1_FILTER_CNTL ((0x302a << 2) + 0xff000000)
+#define VPU_VLOCK_LOCK_TH1 ((0x302b << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP0_ERR_LMT ((0x302c << 2) + 0xff000000)
+#define VPU_VLOCK_LOOP1_ERR_LMT ((0x302d << 2) + 0xff000000)
+#define VPU_VLOCK_ERR_CTRL0 ((0x302e << 2) + 0xff000000)
+#define VPU_VLOCK_RO_VS_O_ABS_CNT_LSB ((0x302f << 2) + 0xff000000)
+#define VPU_VLOCK_RO_VS_I_ABS_CNT_LSB ((0x3030 << 2) + 0xff000000)
+#define VPU_VLOCK_RO_VS_ABS_CNT_MSB ((0x3031 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_vlock_reg.h
+//
+//===========================================================================
+//===========================================================================
+//
+// Reading file: vpp_partb_reg.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: VPPB_VCBUS_BASE = 0x31
+// -----------------------------------------------
+////=================================================================////
+//// vkeystone
+////=================================================================////
+// 8'h00-8'h17
+//
+// Reading file: vkstone_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VKS_CTRL ((0x3100 << 2) + 0xff000000)
+//Bit 31 reg_vks_en // unsigned , default = 1 enable signal of the vks function
+//Bit 30 reg_vks_scl_mode0 // unsigned , default = 1 : b0 mode of vks ofset mode, 0: offset= offset; 1: offset= offset*step= ofset/scale;
+//Bit 29 reg_vks_scl_mode1 // unsigned , default = 1 : b0 mode of vks ofset mode, 0: offset= offset; 1: offset= offset*step= ofset/scale;
+//Bit 28 reg_vks_fill_mode // unsigned , default = 1 mode of out-of-boundary fill, 0 extension, 1: fill with the fill_value
+//Bit 27:26 reg_vks_row_inp_mode // unsigned , default = 1 , interpolation mode from 16pieces ofset/step to each line ofset and step; 0: linear interpolation; 1: cubic interpolation (using ccoef)
+//Bit 25 reg_vks_border_ext_mode0 // unsigned , default = 0 , extend mode of the border data of luma and chroma, 0: copy the most border one; 1: extropolate the border one
+//Bit 24 reg_vks_border_ext_mode1 // unsigned , default = 0 , extend mode of the border data of luma and chroma, 0: copy the most border one; 1: extropolate the border one
+//Bit 23 reg_vks_obuf_mode0 // unsigned , default = 1 , mode of output buffer left/right side. 0: no precalculate active pixels during output fill region; 1: precaclc active pixels during output fill regions
+//Bit 22 reg_vks_obuf_mode1 // unsigned , default = 1 , mode of output buffer left/right side. 0: no precalculate active pixels during output fill region; 1: precaclc active pixels during output fill regions
+//Bit 21:20 reg_vks_obuf_mrgn0 // unsigned , default = 3 , margin pixels for left right most active pixel to the fill pixels to avoid jump
+//Bit 19:18 reg_vks_obuf_mrgn1 // unsigned , default = 3 , margin pixels for left right most active pixel to the fill pixels to avoid jump
+//Bit 17:16 reg_vks_phs_qmode // unsigned , default = 2 , interpolation mode of the phase, 0: floor to 1/64 phase; 1: round to 1/64 phase; 2/3 linear intp
+//Bit 15: 0 reg_vks_row_scl // unsigned , default = 11651 , scale of row to make it fit to the 16 pieces, scl = (2^23)/RowMax
+#define VKS_OUT_WIN_SIZE ((0x3101 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_vks_ocolmax // unsigned , default = 1280 output outer window col number, decided by the projector
+//Bit 15:14 reserved
+//Bit 13: 0 reg_vks_orowmax // unsigned , default = 720 output outer window row number, decided by the projector
+#define VKS_PRELPF_YCOEF0 ((0x3102 << 2) + 0xff000000)
+//Bit 31:24 reg_vks_prelpf_ycoef0 // signed , default = -128 coef of horizontal luma prelpf for Keystone, normalized 128 as '1'
+//Bit 23:16 reg_vks_prelpf_ycoef1 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1'
+//Bit 15: 8 reg_vks_prelpf_ycoef2 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1'
+//Bit 7: 0 reg_vks_prelpf_ycoef3 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1'
+#define VKS_PRELPF_YCOEF1 ((0x3103 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_vks_prelpf_ycoef4 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1'
+//Bit 7: 0 reg_vks_prelpf_ycoef5 // signed , default = 0 coef of horizontal luma prelpf for Keystone, normalized 128 as '1'
+#define VKS_PRELPF_CCOEF0 ((0x3104 << 2) + 0xff000000)
+//Bit 31:24 reg_vks_prelpf_ccoef0 // signed , default = -128 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1'
+//Bit 23:16 reg_vks_prelpf_ccoef1 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1'
+//Bit 15: 8 reg_vks_prelpf_ccoef2 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1'
+//Bit 7: 0 reg_vks_prelpf_ccoef3 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1'
+#define VKS_PRELPF_CCOEF1 ((0x3105 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 8 reg_vks_prelpf_ccoef4 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1'
+//Bit 7: 0 reg_vks_prelpf_ccoef5 // signed , default = 0 mode of horizontal chroma prelpf for Keystone, normalized 128 as '1'
+#define VKS_FILL_VAL ((0x3106 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_vks_fill_value0 // unsigned , default = 0 , border fill color define. yuv: [0 128 128]; rgb:[0 0 0]
+//Bit 15: 8 reg_vks_fill_value1 // unsigned , default = 128 , border fill color define. yuv: [0 128 128]; rgb:[0 0 0]
+//Bit 7: 0 reg_vks_fill_value2 // unsigned , default = 128 , border fill color define. yuv: [0 128 128]; rgb:[0 0 0]
+#define VKS_IWIN_HSIZE ((0x3107 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_vks_iwinx0 // unsigned , default = 160 , input start-col and end-col;
+//Bit 15:14 reserved
+//Bit 13: 0 reg_vks_iwinx1 // unsigned , default = 1279 , input start-col and end-col;
+#define VKS_IWIN_VSIZE ((0x3108 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_vks_iwiny0 // unsigned , default = 0 , input start-row and end-row;
+//Bit 15:14 reserved
+//Bit 13: 0 reg_vks_iwiny1 // unsigned , default = 719 , input start-row and end-row;
+#define VKS_TOP_MISC ((0x3109 << 2) + 0xff000000)
+//Bit 31:19 reserved
+//Bit 18 reg_flt_en // unsigned , default = 1
+//Bit 17 reg_frm_rst // unsigned , default = 0
+//Bit 16 reg_ctrl_sync // unsigned , default = 0
+//Bit 15: 8 blank_num // unsigned , default = 4
+//Bit 7: 0 flt_blank_num // unsigned , default = 9
+#define VKS_START_CTRL ((0x310a << 2) + 0xff000000)
+//Bit 31:17 reserved
+//Bit 16 reg_vks_en_mode // unsigned , default = 0
+//Bit 15: 0 reg_hold_phnum // unsigned , default = 5
+#define VKS_LBUF_SIZE ((0x310b << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11: 0 reg_lbuf_depth // unsigned , default = 1024
+#define VKS_PARA_ADDR_PORT ((0x310e << 2) + 0xff000000)
+#define VKS_PARA_DATA_PORT ((0x310f << 2) + 0xff000000)
+
+ #define VKS_SCL_OFSET00 0x9 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset0 // unsigned , default = 118534 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET01 0xa //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset1 // unsigned , default = 111450 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET02 0xb //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset2 // unsigned , default = 104366 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET03 0xc //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset3 // unsigned , default = 97283 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET04 0xd //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset4 // unsigned , default = 90199 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET05 0xe //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset5 // unsigned , default = 83115 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET06 0xf //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset6 // unsigned , default = 76031 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET07 0x10 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset7 // unsigned , default = 68947 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET08 0x11 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset8 // unsigned , default = 61864 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET09 0x12 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset9 // unsigned , default = 54780 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET10 0x13 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset10 // unsigned , default = 47696 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET11 0x14 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset11 // unsigned , default = 40612 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET12 0x15 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset12 // unsigned , default = 33528 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET13 0x16 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset13 // unsigned , default = 26444 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET14 0x17 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset14 // unsigned , default = 19361 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET15 0x18 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset15 // unsigned , default = 12277 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_OFSET16 0x19 //
+//Bit 31:20 reserved
+//Bit 19: 0 reg_vks_scl_ofset16 // unsigned , default = 5193 , left offset of the input pixel offset from left, 12.8 12bits pixel + 8bits float phase
+ #define VKS_SCL_STEP00 0x1a //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step0 // unsigned , default = 331378 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP01 0x1b //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step1 // unsigned , default = 383191 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP02 0x1c //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step2 // unsigned , default = 435004 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP03 0x1d //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step3 // unsigned , default = 486818 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP04 0x1e //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step4 // unsigned , default = 538631 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP05 0x1f //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step5 // unsigned , default = 590444 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP06 0x20 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step6 // unsigned , default = 642257 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP07 0x21 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step7 // unsigned , default = 694070 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP08 0x22 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step8 // unsigned , default = 745884 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP09 0x23 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step9 // unsigned , default = 797697 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP10 0x24 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step10 // unsigned , default = 849510 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP11 0x25 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step11 // unsigned , default = 901323 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP12 0x26 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step12 // unsigned , default = 953136 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP13 0x27 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step13 // unsigned , default = 1004949 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP14 0x28 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step14 // unsigned , default = 1056763 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP15 0x29 //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step15 // unsigned , default = 1108576 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_SCL_STEP16 0x2a //
+//Bit 31:24 reserved
+//Bit 23: 0 reg_vks_scl_step16 // unsigned , default = 1160389 , for ratio of each line (defined piece),step: 4.20 opixnum = (ipixnum<<20)/step; scale:4.20 = 1/step
+ #define VKS_PPS_YCOEF00 0x2b //
+//Bit 31:24 reg_vks_ycoef0 // signed , default = 0 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef1 // signed , default = 128 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef2 // signed , default = 0 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef3 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF01 0x2c //
+//Bit 31:24 reg_vks_ycoef4 // signed , default = 0 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef5 // signed , default = 127 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef6 // signed , default = 1 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef7 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF02 0x2d //
+//Bit 31:24 reg_vks_ycoef8 // signed , default = -1 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef9 // signed , default = 127 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef10 // signed , default = 2 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef11 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF03 0x2e //
+//Bit 31:24 reg_vks_ycoef12 // signed , default = -2 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef13 // signed , default = 127 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef14 // signed , default = 3 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef15 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF04 0x2f //
+//Bit 31:24 reg_vks_ycoef16 // signed , default = -3 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef17 // signed , default = 126 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef18 // signed , default = 5 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef19 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF05 0x30 //
+//Bit 31:24 reg_vks_ycoef20 // signed , default = -4 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef21 // signed , default = 126 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef22 // signed , default = 6 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef23 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF06 0x31 //
+//Bit 31:24 reg_vks_ycoef24 // signed , default = -5 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef25 // signed , default = 125 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef26 // signed , default = 8 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef27 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF07 0x32 //
+//Bit 31:24 reg_vks_ycoef28 // signed , default = -5 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef29 // signed , default = 124 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef30 // signed , default = 9 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef31 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF08 0x33 //
+//Bit 31:24 reg_vks_ycoef32 // signed , default = -6 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef33 // signed , default = 123 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef34 // signed , default = 11 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef35 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF09 0x34 //
+//Bit 31:24 reg_vks_ycoef36 // signed , default = -6 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef37 // signed , default = 122 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef38 // signed , default = 13 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef39 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF10 0x35 //
+//Bit 31:24 reg_vks_ycoef40 // signed , default = -7 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef41 // signed , default = 121 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef42 // signed , default = 15 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef43 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF11 0x36 //
+//Bit 31:24 reg_vks_ycoef44 // signed , default = -7 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef45 // signed , default = 119 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef46 // signed , default = 17 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef47 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF12 0x37 //
+//Bit 31:24 reg_vks_ycoef48 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef49 // signed , default = 118 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef50 // signed , default = 19 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef51 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF13 0x38 //
+//Bit 31:24 reg_vks_ycoef52 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef53 // signed , default = 116 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef54 // signed , default = 22 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef55 // signed , default = -2 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF14 0x39 //
+//Bit 31:24 reg_vks_ycoef56 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef57 // signed , default = 114 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef58 // signed , default = 24 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef59 // signed , default = -2 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF15 0x3a //
+//Bit 31:24 reg_vks_ycoef60 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef61 // signed , default = 112 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef62 // signed , default = 26 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef63 // signed , default = -2 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF16 0x3b //
+//Bit 31:24 reg_vks_ycoef64 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef65 // signed , default = 111 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef66 // signed , default = 29 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef67 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF17 0x3c //
+//Bit 31:24 reg_vks_ycoef68 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef69 // signed , default = 109 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef70 // signed , default = 31 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef71 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF18 0x3d //
+//Bit 31:24 reg_vks_ycoef72 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef73 // signed , default = 107 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef74 // signed , default = 33 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef75 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF19 0x3e //
+//Bit 31:24 reg_vks_ycoef76 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef77 // signed , default = 104 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef78 // signed , default = 36 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef79 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF20 0x3f //
+//Bit 31:24 reg_vks_ycoef80 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef81 // signed , default = 102 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef82 // signed , default = 39 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef83 // signed , default = -4 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF21 0x40 //
+//Bit 31:24 reg_vks_ycoef84 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef85 // signed , default = 100 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef86 // signed , default = 41 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef87 // signed , default = -4 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF22 0x41 //
+//Bit 31:24 reg_vks_ycoef88 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef89 // signed , default = 97 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef90 // signed , default = 44 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef91 // signed , default = -4 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF23 0x42 //
+//Bit 31:24 reg_vks_ycoef92 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef93 // signed , default = 95 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef94 // signed , default = 47 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef95 // signed , default = -5 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF24 0x43 //
+//Bit 31:24 reg_vks_ycoef96 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef97 // signed , default = 93 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef98 // signed , default = 49 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef99 // signed , default = -5 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF25 0x44 //
+//Bit 31:24 reg_vks_ycoef100 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef101 // signed , default = 90 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef102 // signed , default = 52 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef103 // signed , default = -5 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF26 0x45 //
+//Bit 31:24 reg_vks_ycoef104 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef105 // signed , default = 88 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef106 // signed , default = 55 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef107 // signed , default = -6 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF27 0x46 //
+//Bit 31:24 reg_vks_ycoef108 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef109 // signed , default = 85 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef110 // signed , default = 58 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef111 // signed , default = -6 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF28 0x47 //
+//Bit 31:24 reg_vks_ycoef112 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef113 // signed , default = 82 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef114 // signed , default = 60 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef115 // signed , default = -6 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF29 0x48 //
+//Bit 31:24 reg_vks_ycoef116 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef117 // signed , default = 80 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef118 // signed , default = 63 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef119 // signed , default = -7 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF30 0x49 //
+//Bit 31:24 reg_vks_ycoef120 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef121 // signed , default = 77 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef122 // signed , default = 66 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef123 // signed , default = -7 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF31 0x4a //
+//Bit 31:24 reg_vks_ycoef124 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef125 // signed , default = 74 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef126 // signed , default = 69 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef127 // signed , default = -7 poly-phase scalar coefs
+ #define VKS_PPS_YCOEF32 0x4b //
+//Bit 31:24 reg_vks_ycoef128 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ycoef129 // signed , default = 72 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ycoef130 // signed , default = 72 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ycoef131 // signed , default = -8 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF00 0x4c //
+//Bit 31:24 reg_vks_ccoef0 // signed , default = 0 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef1 // signed , default = 128 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef2 // signed , default = 0 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef3 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF01 0x4d //
+//Bit 31:24 reg_vks_ccoef4 // signed , default = 0 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef5 // signed , default = 127 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef6 // signed , default = 1 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef7 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF02 0x4e //
+//Bit 31:24 reg_vks_ccoef8 // signed , default = -1 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef9 // signed , default = 127 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef10 // signed , default = 2 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef11 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF03 0x4f //
+//Bit 31:24 reg_vks_ccoef12 // signed , default = -2 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef13 // signed , default = 127 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef14 // signed , default = 3 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef15 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF04 0x50 //
+//Bit 31:24 reg_vks_ccoef16 // signed , default = -3 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef17 // signed , default = 126 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef18 // signed , default = 5 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef19 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF05 0x51 //
+//Bit 31:24 reg_vks_ccoef20 // signed , default = -4 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef21 // signed , default = 126 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef22 // signed , default = 6 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef23 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF06 0x52 //
+//Bit 31:24 reg_vks_ccoef24 // signed , default = -5 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef25 // signed , default = 125 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef26 // signed , default = 8 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef27 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF07 0x53 //
+//Bit 31:24 reg_vks_ccoef28 // signed , default = -5 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef29 // signed , default = 124 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef30 // signed , default = 9 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef31 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF08 0x54 //
+//Bit 31:24 reg_vks_ccoef32 // signed , default = -6 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef33 // signed , default = 123 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef34 // signed , default = 11 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef35 // signed , default = 0 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF09 0x55 //
+//Bit 31:24 reg_vks_ccoef36 // signed , default = -6 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef37 // signed , default = 122 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef38 // signed , default = 13 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef39 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF10 0x56 //
+//Bit 31:24 reg_vks_ccoef40 // signed , default = -7 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef41 // signed , default = 121 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef42 // signed , default = 15 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef43 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF11 0x57 //
+//Bit 31:24 reg_vks_ccoef44 // signed , default = -7 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef45 // signed , default = 119 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef46 // signed , default = 17 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef47 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF12 0x58 //
+//Bit 31:24 reg_vks_ccoef48 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef49 // signed , default = 118 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef50 // signed , default = 19 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef51 // signed , default = -1 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF13 0x59 //
+//Bit 31:24 reg_vks_ccoef52 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef53 // signed , default = 116 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef54 // signed , default = 22 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef55 // signed , default = -2 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF14 0x5a //
+//Bit 31:24 reg_vks_ccoef56 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef57 // signed , default = 114 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef58 // signed , default = 24 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef59 // signed , default = -2 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF15 0x5b //
+//Bit 31:24 reg_vks_ccoef60 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef61 // signed , default = 112 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef62 // signed , default = 26 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef63 // signed , default = -2 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF16 0x5c //
+//Bit 31:24 reg_vks_ccoef64 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef65 // signed , default = 111 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef66 // signed , default = 29 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef67 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF17 0x5d //
+//Bit 31:24 reg_vks_ccoef68 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef69 // signed , default = 109 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef70 // signed , default = 31 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef71 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF18 0x5e //
+//Bit 31:24 reg_vks_ccoef72 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef73 // signed , default = 107 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef74 // signed , default = 33 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef75 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF19 0x5f //
+//Bit 31:24 reg_vks_ccoef76 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef77 // signed , default = 104 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef78 // signed , default = 36 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef79 // signed , default = -3 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF20 0x60 //
+//Bit 31:24 reg_vks_ccoef80 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef81 // signed , default = 102 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef82 // signed , default = 39 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef83 // signed , default = -4 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF21 0x61 //
+//Bit 31:24 reg_vks_ccoef84 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef85 // signed , default = 100 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef86 // signed , default = 41 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef87 // signed , default = -4 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF22 0x62 //
+//Bit 31:24 reg_vks_ccoef88 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef89 // signed , default = 97 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef90 // signed , default = 44 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef91 // signed , default = -4 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF23 0x63 //
+//Bit 31:24 reg_vks_ccoef92 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef93 // signed , default = 95 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef94 // signed , default = 47 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef95 // signed , default = -5 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF24 0x64 //
+//Bit 31:24 reg_vks_ccoef96 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef97 // signed , default = 93 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef98 // signed , default = 49 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef99 // signed , default = -5 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF25 0x65 //
+//Bit 31:24 reg_vks_ccoef100 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef101 // signed , default = 90 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef102 // signed , default = 52 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef103 // signed , default = -5 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF26 0x66 //
+//Bit 31:24 reg_vks_ccoef104 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef105 // signed , default = 88 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef106 // signed , default = 55 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef107 // signed , default = -6 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF27 0x67 //
+//Bit 31:24 reg_vks_ccoef108 // signed , default = -9 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef109 // signed , default = 85 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef110 // signed , default = 58 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef111 // signed , default = -6 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF28 0x68 //
+//Bit 31:24 reg_vks_ccoef112 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef113 // signed , default = 82 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef114 // signed , default = 60 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef115 // signed , default = -6 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF29 0x69 //
+//Bit 31:24 reg_vks_ccoef116 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef117 // signed , default = 80 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef118 // signed , default = 63 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef119 // signed , default = -7 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF30 0x6a //
+//Bit 31:24 reg_vks_ccoef120 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef121 // signed , default = 77 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef122 // signed , default = 66 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef123 // signed , default = -7 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF31 0x6b //
+//Bit 31:24 reg_vks_ccoef124 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef125 // signed , default = 74 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef126 // signed , default = 69 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef127 // signed , default = -7 poly-phase scalar coefs
+ #define VKS_PPS_CCOEF32 0x6c //
+//Bit 31:24 reg_vks_ccoef128 // signed , default = -8 poly-phase scalar coefs
+//Bit 23:16 reg_vks_ccoef129 // signed , default = 72 poly-phase scalar coefs
+//Bit 15: 8 reg_vks_ccoef130 // signed , default = 72 poly-phase scalar coefs
+//Bit 7: 0 reg_vks_ccoef131 // signed , default = -8 poly-phase scalar coefs
+
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vkstone_regs.h
+//
+////=================================================================////
+//// vpp dither
+////=================================================================////
+// 8'h20-8'h3f
+//
+// Reading file: vpp_dither_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VPP_VE_DITHER_CTRL ((0x3120 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_1 ((0x3121 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_2 ((0x3122 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_3 ((0x3123 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_4 ((0x3124 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_5 ((0x3125 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_6 ((0x3126 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_7 ((0x3127 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_8 ((0x3128 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_9 ((0x3129 << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_10 ((0x312a << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_11 ((0x312b << 2) + 0xff000000)
+#define VPP_VE_DITHER_LUT_12 ((0x312c << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_CTRL ((0x3130 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_1 ((0x3131 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_2 ((0x3132 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_3 ((0x3133 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_4 ((0x3134 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_5 ((0x3135 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_6 ((0x3136 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_7 ((0x3137 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_8 ((0x3138 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_9 ((0x3139 << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_10 ((0x313a << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_11 ((0x313b << 2) + 0xff000000)
+#define VPP_OSDSC_DITHER_LUT_12 ((0x313c << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_dither_regs.h
+//
+//register definition for xvycc
+// 8'h50-8'h7f
+//
+// Reading file: xvycc_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define XVYCC_INV_LUT_Y_ADDR_PORT ((0x3158 << 2) + 0xff000000)
+//Bit 31:7, reserved
+//Bit 6:0, xvycc_inv_lut_y_addr;
+#define XVYCC_INV_LUT_Y_DATA_PORT ((0x3159 << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, xvycc_inv_lut_y_data;
+#define XVYCC_INV_LUT_U_ADDR_PORT ((0x315a << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, xvycc_inv_lut_u_addr;
+#define XVYCC_INV_LUT_U_DATA_PORT ((0x315b << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, xvycc_inv_lut_u_data;
+#define XVYCC_INV_LUT_V_ADDR_PORT ((0x315c << 2) + 0xff000000)
+//Bit 31:6, reserved
+//Bit 5:0, xvycc_inv_lut_v_addr;
+#define XVYCC_INV_LUT_V_DATA_PORT ((0x315d << 2) + 0xff000000)
+//Bit 31:12, reserved
+//Bit 11:0, xvycc_inv_lut_v_data;
+#define XVYCC_LUT_R_ADDR_PORT ((0x315e << 2) + 0xff000000)
+//Bit 31:7, reserved
+//Bit 6:0, xvycc_lut_r_addr;
+#define XVYCC_LUT_R_DATA_PORT ((0x315f << 2) + 0xff000000)
+//Bit 31:10, reserved
+//Bit 9:0, xvycc_lut_r_data;
+#define XVYCC_LUT_G_ADDR_PORT ((0x3160 << 2) + 0xff000000)
+//Bit 31:7, reserved
+//Bit 6:0, xvycc_lut_g_addr;
+#define XVYCC_LUT_G_DATA_PORT ((0x3161 << 2) + 0xff000000)
+//Bit 31:10, reserved
+//Bit 9:0, xvycc_lut_g_data;
+#define XVYCC_LUT_B_ADDR_PORT ((0x3162 << 2) + 0xff000000)
+//Bit 31:7, reserved
+//Bit 6:0, xvycc_lut_b_addr;
+#define XVYCC_LUT_B_DATA_PORT ((0x3163 << 2) + 0xff000000)
+//Bit 31:10, reserved
+//Bit 9:0, xvycc_lut_b_data;
+#define XVYCC_INV_LUT_CTL ((0x3164 << 2) + 0xff000000)
+//Bit 31:15, reserved
+//Bit 14:12, reg_xvycc_cmpr_invlut_enable enable for xvycc compression inverse-lut [2] for Y, [1] for U, [0] for V default=0
+//Bit 11:10, reg_xvycc_cmpr_invlut_vscl_1 v LUT input scale for positive portion default=0
+//Bit 9: 8, reg_xvycc_cmpr_invlut_vscl_0 v LUT input scale for negative portion default=0
+//Bit 7: 6, reg_xvycc_cmpr_invlut_uscl_1 u LUT input scale for positive portion default=0
+//Bit 5: 4, reg_xvycc_cmpr_invlut_uscl_0 u LUT input scale for negative portion default=0
+//Bit 3: 2, reg_xvycc_cmpr_invlut_yscl_1 y LUT input scale for positive portion default=0
+//Bit 1: 0, reg_xvycc_cmpr_invlut_yscl_0 y LUT input scale for negative portion default=0
+#define XVYCC_LUT_CTL ((0x3165 << 2) + 0xff000000)
+//Bit 31: 7, reserved
+//Bit 6: 4, reg_xvycc_lut_enable LUT enable [6] for R, [5] for G, [4] for B default=0
+//Bit 3: 2, reg_xvycc_lut_scl_1 LUT input scale for positive portion default=0
+//Bit 1: 0, reg_xvycc_lut_scl_0 LUT input scale for negative portion default=0
+#define XVYCC_VADJ1_CURV_0 ((0x3166 << 2) + 0xff000000)
+//Bit 31:24, vadj1_softcon_curv0_ci default=0
+//Bit 23:12, vadj1_softcon_curv0_b default=0
+//Bit 11: 0, vadj1_softcon_curv0_a default=0
+#define XVYCC_VADJ1_CURV_1 ((0x3167 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12: 4, vadj1_softcon_curv0_g default=0
+//Bit 3, reserved
+//Bit 2: 0, vadj1_softcon_curv0_cs default=0
+#define XVYCC_VADJ1_CURV_2 ((0x3168 << 2) + 0xff000000)
+//Bit 31:24, vadj1_softcon_curv1_ci default=0
+//Bit 23:12, vadj1_softcon_curv1_b default=0
+//Bit 11: 0, vadj1_softcon_curv1_a default=0
+#define XVYCC_VADJ1_CURV_3 ((0x3169 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12: 4, vadj1_softcon_curv1_g default=0
+//Bit 3, reserved
+//Bit 2: 0, vadj1_softcon_curv1_cs default=0
+#define XVYCC_VADJ2_CURV_0 ((0x316a << 2) + 0xff000000)
+//Bit 31:24, vadj2_softcon_curv0_ci default=0
+//Bit 23:12, vadj2_softcon_curv0_b default=0
+//Bit 11: 0, vadj2_softcon_curv0_a default=0
+#define XVYCC_VADJ2_CURV_1 ((0x316b << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12: 4, vadj2_softcon_curv0_g default=0
+//Bit 3, reserved
+//Bit 2: 0, vadj2_softcon_curv0_cs default=0
+#define XVYCC_VADJ2_CURV_2 ((0x316c << 2) + 0xff000000)
+//Bit 31:24, vadj2_softcon_curv1_ci default=0
+//Bit 23:12, vadj2_softcon_curv1_b default=0
+//Bit 11: 0, vadj2_softcon_curv1_a default=0
+#define XVYCC_VADJ2_CURV_3 ((0x316d << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12: 4, vadj2_softcon_curv1_g default=0
+//Bit 3, reserved
+//Bit 2: 0, vadj2_softcon_curv1_cs default=0
+#define XVYCC_VD1_RGB_CTRST ((0x3170 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, reg_vd1_rgb_ctrst u12, contrast in rgb. default=1024
+//Bit 15:14, reserved
+//Bit 13: 4, reg_vd1_rgb_ctrst_blklvl u10, contrast blacklevel default=64
+//Bit 3: 2, reserved
+//Bit 1, reg_vd1_rgbbst_en u1, enable rgbbst default=0
+//Bit 0, reg_vd1_rgb_ctrst_prt u1, enable signal to protect saturation in rgb. default=1
+#define XVYCC_VD1_RGB_BRGHT ((0x3171 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 4, reg_vd1_rgb_brght s12, brightness level in rgb domain default=0
+//Bit 3: 2, reserved
+//Bit 1, reg_vd1_rgb_brght_prt u1, enalbe signal to protect saturation in rgb default=1
+//Bit 0, reg_vd1_rgbbst_dlut_x2 u1, enable signal to do x2 to the dlut cells before subtracting default=0
+#define XVYCC_VD1_RGB_DLUT_0_3 ((0x3172 << 2) + 0xff000000)
+//Bit 31:24, reg_vd1_rgbbst_dlut0 u8, default = 255
+//Bit 23:16, reg_vd1_rgbbst_dlut1 u8, default = 205
+//Bit 15: 8, reg_vd1_rgbbst_dlut2 u8, default = 171
+//Bit 7: 0, reg_vd1_rgbbst_dlut3 u8, default = 147
+#define XVYCC_VD1_RGB_DLUT_4_7 ((0x3173 << 2) + 0xff000000)
+//Bit 31:24, reg_vd1_rgbbst_dlut4 u8, default = 128
+//Bit 23:16, reg_vd1_rgbbst_dlut5 u8, default = 113
+//Bit 15: 8, reg_vd1_rgbbst_dlut6 u8, default = 102
+//Bit 7: 0, reg_vd1_rgbbst_dlut7 u8, default = 93
+#define XVYCC_VD1_RGB_DLUT_8_11 ((0x3174 << 2) + 0xff000000)
+//Bit 31:24, reg_vd1_rgbbst_dlut8 u8, default = 85
+//Bit 23:16, reg_vd1_rgbbst_dlut9 u8, default = 78
+//Bit 15: 8, reg_vd1_rgbbst_dlut10 u8, default = 73
+//Bit 7: 0, reg_vd1_rgbbst_dlut11 u8, default = 68
+#define XVYCC_POST_RGB_CTRST ((0x3175 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, reg_post_rgb_ctrst u12, contrast in rgb. default=1024
+//Bit 15:14, reserved
+//Bit 13: 4, reg_post_rgb_ctrst_blklvl u10, contrast blacklevel default=64
+//Bit 3: 2, reserved
+//Bit 1, reg_post_rgbbst_en u1, enable rgbbst default=0
+//Bit 0, reg_post_rgb_ctrst_prt u1, enable signal to protect saturation in rgb. default=1
+#define XVYCC_POST_RGB_BRGHT ((0x3176 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 4, reg_post_rgb_brght s12, brightness level in rgb domain default=0
+//Bit 3: 2, reserved
+//Bit 1, reg_post_rgb_brght_prt u1, enalbe signal to protect saturation in rgb default=1
+//Bit 0, reg_post_rgbbst_dlut_x2 u1, enable signal to do x2 to the dlut cells before subtracting default=0
+#define XVYCC_POST_RGB_DLUT_0_3 ((0x3177 << 2) + 0xff000000)
+//Bit 31:24, reg_post_rgbbst_dlut0 u8, default = 255
+//Bit 23:16, reg_post_rgbbst_dlut1 u8, default = 205
+//Bit 15: 8, reg_post_rgbbst_dlut2 u8, default = 171
+//Bit 7: 0, reg_post_rgbbst_dlut3 u8, default = 147
+#define XVYCC_POST_RGB_DLUT_4_7 ((0x3178 << 2) + 0xff000000)
+//Bit 31:24, reg_post_rgbbst_dlut4 u8, default = 128
+//Bit 23:16, reg_post_rgbbst_dlut5 u8, default = 113
+//Bit 15: 8, reg_post_rgbbst_dlut6 u8, default = 102
+//Bit 7: 0, reg_post_rgbbst_dlut7 u8, default = 93
+#define XVYCC_POST_RGB_DLUT_8_11 ((0x3179 << 2) + 0xff000000)
+//Bit 31:24, reg_post_rgbbst_dlut8 u8, default = 85
+//Bit 23:16, reg_post_rgbbst_dlut9 u8, default = 78
+//Bit 15: 8, reg_post_rgbbst_dlut10 u8, default = 73
+//Bit 7: 0, reg_post_rgbbst_dlut11 u8, default = 68
+#define ADAPTIVE_SCALE_REG0 ((0x3150 << 2) + 0xff000000)
+//Bit 31, reg_adaptive_scale_enable u1, default = 1
+//Bit 27:16, reg_adpscl_ys_coef_0 u12, default = 538
+//Bit 11: 0, reg_adpscl_ys_coef_1 u12, default = 1389
+#define ADAPTIVE_SCALE_REG1 ((0x3151 << 2) + 0xff000000)
+//Bit 27:16, reg_adpscl_ys_coef_2 u12, default = 121
+//Bit 11: 0, reg_adpscl_alpha_0 u12, default = 1024
+#define ADAPTIVE_SCALE_REG2 ((0x3152 << 2) + 0xff000000)
+//Bit 27:16, reg_adpscl_alpha_1 u12, default = 1024
+//Bit 11: 0, reg_adpscl_alpha_2 u12, default = 1024
+#define ADAPTIVE_SCALE_REG3 ((0x3153 << 2) + 0xff000000)
+//Bit 31:16, reg_adpscl_beta_0 u16, default = 0
+//Bit 15: 0, reg_adpscl_beta_1 u16, default = 0
+#define ADAPTIVE_SCALE_REG4 ((0x3154 << 2) + 0xff000000)
+//Bit 31:16, reg_adpscl_beta_2 u16, default = 0
+#define ADAPTIVE_SCALE_ADDR ((0x3155 << 2) + 0xff000000)
+//Bit 6:0, reg_lut_addr u7, default = 0
+#define ADAPTIVE_SCALE_DATA ((0x3156 << 2) + 0xff000000)
+//Bit 11:0, reg_lut_data u12, default = 0
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: xvycc_regs.h
+//
+//register definition for vd2 afbc dec
+// 8'h80-8'h9f
+//
+// Reading file: vd2_afbc_dec_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+//// reg
+////===============================////
+#define VD2_AFBC_ENABLE ((0x3180 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:23, reg_gclk_ctrl_core unsigned, default = 0
+//Bit 22, reg_fmt_size_sw_mode unsigned, default = 0, 0:hw mode 1:sw mode for format size
+//Bit 21, reg_addr_link_en unsigned, default = 1, 1:enable
+//Bit 20, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb
+//Bit 19, reg_dos_uncomp_mode unsigned , default = 0
+//Bit 18:16, soft_rst unsigned , default = 4
+//Bit 15:14, reserved
+//Bit 13:12, ddr_blk_size unsigned , default = 1
+//Bit 11:9, cmd_blk_size unsigend , default = 3
+//Bit 8, dec_enable unsigned , default = 0
+//Bit 7:2, reserved
+//Bit 1, head_len_sel unsigned , default = 1
+//Bit 0, dec_frm_start unsigned , default = 0
+#define VD2_AFBC_MODE ((0x3181 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29, ddr_sz_mode uns, default = 0 , 0: fixed block ddr size 1 : unfixed block ddr size;
+//Bit 28, blk_mem_mode uns, default = 0 , 0: fixed 16x128 size; 1 : fixed 12x128 size
+//Bit 27:26, rev_mode uns, default = 0 , reverse mode
+//Bit 25:24, mif_urgent uns, default = 3 , info mif and data mif urgent
+//Bit 23, reserved
+//Bit 22:16, hold_line_num uns, default = 4 ,
+//Bit 15:14, burst_len uns, default = 2, 0: burst1 1:burst2 2:burst4
+//Bit 13:8, compbits_yuv uns, default = 0 ,
+// bit 1:0,: y component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+// bit 3:2,: u component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+// bit 5:4,: v component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+//Bit 7:6, vert_skip_y uns, default = 0 , luma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 5:4, horz_skip_y uns, default = 0 , luma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 3:2, vert_skip_uv uns, default = 0 , chroma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 1:0, horz_skip_uv uns, default = 0 , chroma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+#define VD2_AFBC_SIZE_IN ((0x3182 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hsize_in uns, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_in uns, default = 1080 , pic vert size in unit: pixel
+#define VD2_AFBC_DEC_DEF_COLOR ((0x3183 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:20, def_color_y uns, default = 255, afbc dec y default setting value
+//Bit 19:10, def_color_u uns, default = 128, afbc dec u default setting value
+//Bit 9: 0, def_color_v uns, default = 128, afbc dec v default setting value
+#define VD2_AFBC_CONV_CTRL ((0x3184 << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13:12, fmt_mode uns, default = 2, 0:yuv444 1:yuv422 2:yuv420
+//Bit 11: 0, conv_lbuf_len uns, default = 256, unit=16 pixel need to set = 2^n
+#define VD2_AFBC_LBUF_DEPTH ((0x3185 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, dec_lbuf_depth uns, default = 128; // unit= 8 pixel
+//Bit 15:12, reserved
+//Bit 11:0, mif_lbuf_depth uns, default = 128;
+#define VD2_AFBC_HEAD_BADDR ((0x3186 << 2) + 0xff000000)
+//Bit 31:0, mif_info_baddr uns, default = 32'h0;
+#define VD2_AFBC_BODY_BADDR ((0x3187 << 2) + 0xff000000)
+//Bit 31:0, mif_data_baddr uns, default = 32'h00010000;
+#define VD2_AFBC_SIZE_OUT ((0x3188 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, hsize_out uns, default = 1920 ; // unit: 1 pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_out uns, default = 1080 ; // unit: 1 pixel
+#define VD2_AFBC_OUT_YSCOPE ((0x3189 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, out_vert_bgn uns, default = 0 ; // unit: 1 pixel
+//Bit 15:13, reserved
+//Bit 12:0, out_vert_end uns, default = 1079 ; // unit: 1 pixel
+#define VD2_AFBC_STAT ((0x318a << 2) + 0xff000000)
+//Bit 31:0, ro_dbg_top_info uns
+#define VD2_AFBC_VD_CFMT_CTRL ((0x318b << 2) + 0xff000000)
+//Bit 31 cfmt_gclk_bit_dis uns, default = 0 ; // it true, disable clock, otherwise enable clock
+//Bit 30 cfmt_soft_rst_bit uns, default = 0 ; // soft rst bit
+//Bit 29 reserved
+//Bit 28 chfmt_rpt_pix uns, default = 0 ; // if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
+//Bit 27:24 chfmt_ini_phase uns, default = 0 ; // horizontal formatter initial phase
+//Bit 23 chfmt_rpt_p0_en uns, default = 0 ; // horizontal formatter repeat pixel 0 enable
+//Bit 22:21 chfmt_yc_ratio uns, default = 0 ; // horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
+//Bit 20 chfmt_en uns, default = 0 ; // horizontal formatter enable
+//Bit 19 cvfmt_phase0_always_en uns, default = 0 ; //if true, always use phase0 while vertical formater, meaning always
+// repeat data, no interpolation
+//Bit 18 cvfmt_rpt_last_dis uns, default = 0 ; //if true, disable vertical formatter chroma repeat last line
+//Bit 17 cvfmt_phase0_nrpt_en uns, default = 0 ; //veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable
+//Bit 16 cvfmt_rpt_line0_en uns, default = 0 ; //veritcal formatter repeat line 0 enable
+//Bit 15:12 cvfmt_skip_line_num uns, default = 0 ; //vertical formatter skip line num at the beginning
+//Bit 11:8 cvfmt_ini_phase uns, default = 0 ; //vertical formatter initial phase
+//Bit 7:1 cvfmt_phase_step uns, default = 0 ; //vertical formatter phase step (3.4)
+//Bit 0 cvfmt_en uns, default = 0 ; //vertical formatter enable
+#define VD2_AFBC_VD_CFMT_W ((0x318c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 chfmt_w uns, default = 0 ;horizontal formatter width
+//Bit 15:13 reserved
+//Bit 12:0 cvfmt_w uns, default = 0 ;vertical formatter width
+#define VD2_AFBC_MIF_HOR_SCOPE ((0x318d << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, mif_blk_bgn_h uns, default = 0 ; // unit: 32 pixel/block hor
+//Bit 15:10, reserved
+//Bit 9: 0, mif_blk_end_h uns, default = 59 ; // unit: 32 pixel/block hor
+#define VD2_AFBC_MIF_VER_SCOPE ((0x318e << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, mif_blk_bgn_v uns, default = 0 ; // unit: 32 pixel/block ver
+//Bit 15:12, reserved
+//Bit 11: 0, mif_blk_end_v uns, default = 269; // unit: 32 pixel/block ver
+#define VD2_AFBC_PIXEL_HOR_SCOPE ((0x318f << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, dec_pixel_bgn_h uns, default = 0 ; // unit: pixel
+//Bit 15:13, reserved
+//Bit 12: 0, dec_pixel_end_h uns, default = 1919 ; // unit: pixel
+#define VD2_AFBC_PIXEL_VER_SCOPE ((0x3190 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, dec_pixel_bgn_v uns, default = 0 ; // unit: pixel
+//Bit 15:13, reserved
+//Bit 12: 0, dec_pixel_end_v uns, default = 1079 ; // unit: pixel
+#define VD2_AFBC_VD_CFMT_H ((0x3191 << 2) + 0xff000000)
+//Bit 31:13, reserved
+//Bit 12:0 cfmt_h uns, default = 142 ; //vertical formatter height
+#define VD2_AFBCDEC_IQUANT_ENABLE ((0x3192 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_quant_expand_en_1 //unsigned, RW, enable for quantization value expansion
+//Bit 10 reg_quant_expand_en_0 //unsigned, RW, enable for quantization value expansion
+//Bit 9: 8 reg_bcleav_ofst // signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1;
+//Bit 7: 5 reserved
+//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy
+//Bit 3: 1 reserved
+//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy
+#define VD2_AFBCDEC_IQUANT_LUT_1 ((0x3193 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define VD2_AFBCDEC_IQUANT_LUT_2 ((0x3194 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define VD2_AFBCDEC_IQUANT_LUT_3 ((0x3195 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define VD2_AFBCDEC_IQUANT_LUT_4 ((0x3196 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vd2_afbc_dec_regs.h
+//
+//register definition for osd1 afbcd dec
+// 8'ha0-8'haf
+//
+// Reading file: osd1_afbcd_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+//// reg
+////===============================////
+#define OSD1_AFBCD_ENABLE ((0x31a0 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:9, id_fifo_thrd unsigned , default = 64, axi id fifo threshold
+//Bit 8, dec_enable unsigned , default = 0
+//Bit 7:1, reserved
+//Bit 0, frm_start unsigned , default = 0
+#define OSD1_AFBCD_MODE ((0x31a1 << 2) + 0xff000000)
+//Bit 31, soft_reset the use as go_field
+//Bit 30:29, reserved
+//Bit 28, axi_reorder_mode default=0, the axi reorder mode, note : don't seting
+//Bit 27:26, reserved
+//Bit 25:24, mif_urgent uns, default = 3 , info mif and data mif urgent
+//Bit 22:16, hold_line_num
+//Bit 15:8, rgba_exchan_ctrl
+//Bit 7, reserved
+//Bit 6, hreg_block_split uns, default = 1 , Enable/disable block split mode in sparse allocation
+//Bit 5, hreg_half_block uns, default = 1 , Enable/disable half block decoding. 1=half block, 0=full block
+//Bit 4:0, hreg_pixel_packing_fmt uns, default = 5 , Pixel format
+#define OSD1_AFBCD_SIZE_IN ((0x31a2 << 2) + 0xff000000)
+//Bit 31:16 hreg_hsize_in uns, default = 1920 , pic horz size in unit: pixel
+//Bit 15:0, hreg_vsize_in uns, default = 1080 , pic vert size in unit: pixel
+#define OSD1_AFBCD_HDR_PTR ((0x31a3 << 2) + 0xff000000)
+//Bit 31:0 hreg_hdr_ptr uns, default = 0 ,
+#define OSD1_AFBCD_FRAME_PTR ((0x31a4 << 2) + 0xff000000)
+//Bit 31:0 hreg_frame_ptr uns, default = 0 , The start address of the target frame buffer.
+// For YUV format, this pointer specifies the luma buffer.
+#define OSD1_AFBCD_CHROMA_PTR ((0x31a5 << 2) + 0xff000000)
+//Bit 31:0 hreg_chroma_ptr uns, default = 0 , Only valid in YUV format, to specify the target chroma buffer.
+#define OSD1_AFBCD_CONV_CTRL ((0x31a6 << 2) + 0xff000000)
+//Bit 31:15, reserved
+//Bit 15: 0, conv_lbuf_len uns, default = 1024, unit=16 pixel need to set = 2^n
+#define OSD1_AFBCD_STATUS ((0x31a8 << 2) + 0xff000000)
+//Bit 30:4, reserved
+//Bit 3, hreg_dec_resp uns, default = 0 , Decoder error flage from the dec4x4 core
+//Bit 2, hreg_axi_bresp uns, default = 0 , Bus error flag for AXI write error
+//Bit 1, hreg_axi_rresp uns, default = 0 , Bus error flag for AXI read error
+//Bit 0, hreg_idle_n uns, default = 0 , Idle output, value 0 indicates the standalone decoder is free now and can start the next frame.
+#define OSD1_AFBCD_PIXEL_HSCOPE ((0x31a9 << 2) + 0xff000000)
+//Bit 31:16, dec_pixel_bgn_h uns, default = 0 ; // unit: pixel
+//Bit 15: 0, dec_pixel_end_h uns, default = 1919 ; // unit: pixel
+#define OSD1_AFBCD_PIXEL_VSCOPE ((0x31aa << 2) + 0xff000000)
+//Bit 31:16, dec_pixel_bgn_v uns, default = 0 ; // unit: pixel
+//Bit 15: 0, dec_pixel_end_v uns, default = 1079 ; // unit: pixel
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: osd1_afbcd_regs.h
+//
+//register definition for osd1 afbcd dec
+// 8'hb0-8'hca
+//
+// Reading file: vpp_vmx_wm_regs.h
+//
+//// synopsys translate_off
+//`ifdef VPP_WM_REGS_H
+//`else
+// `define VPP_WM_REGS_H
+//// synopsys translate_on
+#define WM_CTRL ((0x31b0 << 2) + 0xff000000)
+//Bit 31, int_mask default = 0
+//Bit 30:16, reserved
+//Bit 15:8, strength_multiply default =1
+//Bit 7:6, reserved
+//Bit 5, shift_en default = 0
+//Bit 4, background_embedding_on default =0
+//Bit 3, mark_en default =0
+//Bit 2, noise_en default =0
+//Bit 1, blend_en default =0
+//Bit 0, wm_en default =0
+#define WM_SPACE_RESOLUTION ((0x31b1 << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24:16, spacing_horz default =10
+//Bit 15:9, reserved
+//Bit 8:0, spacing_vert default =12
+#define WM_SYMBOLS_NUM ((0x31b2 << 2) + 0xff000000)
+//Bit 31:8, reserved
+//Bit 7:4, symbols_cols 1~10; default =5
+//Bit 3:0, symbols_rows 1~10; default =2
+#define WM_MARK_RESOLUTION ((0x31b3 << 2) + 0xff000000)
+//Bit 31:20, mark_hsize mark_buffer_width; default =1820
+//Bit 19:8, mark_vsize mark_buffer_height; default =1820 t =780
+//Bit 7:6, reserved
+//Bit 5:0, scale default =13 // scale up
+#define WM_FREQ_DIST_LEFT ((0x31b4 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:0, freq_dist_left default =21092 // frequency_distance [n][0] each is 7bits, there is 3 dist
+#define WM_FREQ_DIST_RIGHT ((0x31b5 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:0, freq_dist_right default =21092 // frequency_distance [n][0] each is 7bits, there is 3 dist
+#define WM_FREQ_DIST_TOP ((0x31b6 << 2) + 0xff000000)
+//Bit 31:21, reserved
+//Bit 20:0, freq_dist_top default =21092 // frequency_distance [n][0] each is 7bits, there is 3 dist
+#define WM_SYMBOLS_XPOS ((0x31b7 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, symbols_xpos_start default =1536 // SYMBOLS_XPOS * h_res
+//Bit 15:13, reserved
+//Bit 12:0, symbols_xpos_end default =3356 // SYMBOLS_XPOS * h_res + mark_hsize
+#define WM_SYMBOLS_YPOS ((0x31b8 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, symbols_ypos_start default =756 // SYMBOLS_yPOS * y_res
+//Bit 15:13, reserved
+//Bit 12:0, symbols_ypos_end default =1536 // SYMBOLS_yPOS * y_res + mark_vsize
+#define WM_STORAGE_SETTING ((0x31b9 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, direction_max default = 80
+//Bit 15, reserved
+//Bit 14:8, storage_s default =18 // biggest is 72 S
+//Bit 7, reserved
+//Bit 6:0, storage_max_distance default =36 // biggest is 72 max_distance
+#define WM_VIDEO_RESOLUTION ((0x31ba << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, h_res default =3840 // video hsize
+//Bit 15:13, reserved
+//Bit 12:0, v_res default =2160 // video vsize
+#define WM_EMBEDDING_STRENGTH_THRESHOLD0 ((0x31bb << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_0 default =48
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_1 default =60
+#define WM_EMBEDDING_STRENGTH_THRESHOLD1 ((0x31bc << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_2 default = 68
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_3 default = 80
+#define WM_EMBEDDING_STRENGTH_THRESHOLD2 ((0x31bd << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_4 default = 88
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_5 default = 96
+#define WM_EMBEDDING_STRENGTH_THRESHOLD3 ((0x31be << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_6 default = 100
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_7 default = 108
+#define WM_EMBEDDING_STRENGTH_THRESHOLD4 ((0x31bf << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_8 default = 112
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_9 default = 116
+#define WM_EMBEDDING_STRENGTH_THRESHOLD5 ((0x31c0 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_10 default = 120
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_11 default = 124
+#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG0 ((0x31c1 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_bg_0 default =320
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_bg_1 default = 328
+#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG1 ((0x31c2 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_bg_2 default = 332
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_bg_3 default = 340
+#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG2 ((0x31c3 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_bg_4 default = 344
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_bg_5 default = 348
+#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG3 ((0x31c4 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_bg_6 default = 352
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_bg_7 default = 356
+#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG4 ((0x31c5 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_bg_8 default = 360
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_bg_9 default = 368
+#define WM_EMBEDDING_STRENGTH_THRESHOLD_BG5 ((0x31c6 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, embedding_strength_threshold_bg_10 default = 372
+//Bit 15:12, reserved
+//Bit 11:0, embedding_strength_threshold_bg_11 default = 380
+#define WM_AM_LUT_DATA_PORT ((0x31c7 << 2) + 0xff000000)
+#define WM_AM_LUT_ADDR_PORT ((0x31c8 << 2) + 0xff000000)
+#define WM_STATUS_RO ((0x31c9 << 2) + 0xff000000)
+//Bit 31, ro_resolution_changed
+//Bit 30:29, reserved
+//Bit 30:16, ro_hsize_in
+//Bit 15:13, reserved
+//Bit 8:0, ro_vsize_in
+#define WM_STATUS_RAM_RO ((0x31ca << 2) + 0xff000000)
+//Bit 31:9, reserved
+//Bit 8:0, ro_ram_addr
+#define WM_THRES_ADDR_PORT ((0x31cb << 2) + 0xff000000)
+#define WM_THRES_DATA_PORT ((0x31cd << 2) + 0xff000000)
+//
+// Closing file: vpp_vmx_wm_regs.h
+//
+//
+// Reading file: ngptv_reg.h
+//
+//// synopsys translate_off
+//`ifdef VPP_WM_REGS_H
+//`else
+// `define VPP_WM_REGS_H
+//// synopsys translate_on
+#define REG_NGPTV_CTRL0 ((0x31ab << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24, bypass_latch
+//Bit 23, count_enable deafult=1
+//Bit 22, soft_rst
+//Bit 21, count_rst
+//Bit 20, bypass run
+//Bit 19:14, ochannel_sel deafult=0x24
+//Bit 13:8, ichannel_sel deafult=0x24
+//Bit 3, 8bit mode
+//Bit 2, 10bit mode
+//Bit 1, reg_sync enable
+//Bit 0, bypass
+#define REG_NGPTV_CTRL1 ((0x31ac << 2) + 0xff000000)
+//Bit 31:7 reserved
+//Bit 6 reset sw default=0
+//Bit 5:0 gclk_ctrl
+#define REG_NGPTV_CTRL2 ((0x31ad << 2) + 0xff000000)
+//Bit 31:8 reserved
+//Bit 7 SpareIn
+//Bit 6 NG_EnableServiceIn
+//Bit 5:4 reserved
+//Bit 3 NG_DebugEnableIn
+//Bit 2 reserved
+//Bit 1 NG_Payload24_56n
+//Bit 0 NG_YUVnRGBIn
+#define REG_NGPTV_CTRL3 ((0x31ce << 2) + 0xff000000)
+//Bit 31:0 NG_KeyIn default=0x01ac7f33
+#define REG_NGPTV_CTRL4 ((0x31cf << 2) + 0xff000000)
+//Bit 31:0 NG_PayloadDataIn[31:0] default=0x6789abcd
+#define REG_NGPTV_CTRL5 ((0x31f0 << 2) + 0xff000000)
+//Bit 31:26 Reserved
+//Bit 25:24 NG_FrameTypeIn default=3
+//Bit 23:0 NG_PayloadDataIn default=0x012345
+#define REG_NGPTV_CTRL6 ((0x31f1 << 2) + 0xff000000)
+//Bit 31:0 NG_SettingIn[31:0] default=0x18c6318c
+#define REG_NGPTV_CTRL7 ((0x31f2 << 2) + 0xff000000)
+//Bit 31:0 NG_SettingIn[63:32] default=0x84210842
+#define REG_NGPTV_CTRL8 ((0x31f3 << 2) + 0xff000000)
+//Bit 31:0 NG_SettingIn[95:64] default=0x21084210
+#define REG_NGPTV_CTRL9 ((0x31f4 << 2) + 0xff000000)
+//Bit 31:0 NG_SettingIn[127:96] default=0x8c631084
+#define REG_NGPTV_CTRL10 ((0x31f5 << 2) + 0xff000000)
+//Bit 31:0 NG_SettingIn[159:128] default=0x84210631
+#define REG_NGPTV_CTRL11 ((0x31f6 << 2) + 0xff000000)
+//Bit 31:16 Reserved
+//Bit 15:8 NG_FrameRateIn default=0x18
+//Bit 7 Reserved
+//Bit 6:5 NG_CoreIDIn default=0
+//Bit 4:0 NG_SettingIn[165:160] default=0x10
+#define REG_NGPTV_CTRL12 ((0x31f7 << 2) + 0xff000000)
+//Bit 31:29 Reserved
+//Bit 28:16 vsize default=0x438
+//Bit 16:13 Reserved
+//Bit 12:0 hsize default=0x780
+#define REG_NGPTV_CTRL13 ((0x31f8 << 2) + 0xff000000)
+//Bit 31:29 Reserved
+//Bit 28:16 reg_vphstart default=0x0
+//Bit 16:13 Reserved
+//Bit 12:0 reg_vphend default=0x437
+#define REG_NGPTV_CTRL14 ((0x31f9 << 2) + 0xff000000)
+//Bit 31:13 Reserved
+//Bit 12:0 reg_3d_right_st default=0x3c0
+#define REG_NGPTV_CTRL15 ((0x31fa << 2) + 0xff000000)
+//Bit 31:29 Reserved
+//Bit 28:16 reg_vpvstart0 default=0x0
+//Bit 16:13 Reserved
+//Bit 12:0 reg_vpvend0 default=0x437
+#define REG_NGPTV_CTRL16 ((0x31fb << 2) + 0xff000000)
+//Bit 31:29 Reserved
+//Bit 28:16 reg_vpvstart1 default=0
+//Bit 16:13 Reserved
+//Bit 12:0 reg_vpvend1 default=0
+#define REG_NGPTV_CTRL17 ((0x31fc << 2) + 0xff000000)
+//Bit 31:29 Reserved
+//Bit 28:16 reg_vpvstart2 default=0
+//Bit 16:13 Reserved
+//Bit 12:0 reg_vpvend2 default=0
+#define REG_NGPTV_CTRL18 ((0x31fd << 2) + 0xff000000)
+//Bit 31:29 Reserved
+//Bit 28:16 reg_vpvstart3 default=0
+//Bit 16:13 Reserved
+//Bit 12:0 reg_vpvend3 default=0
+#define RO_NGPTV_CTRL19 ((0x31fe << 2) + 0xff000000)
+//Bit 31 dat_val_in
+//Bit 30 in_hold
+//Bit 29 out_hold
+//Bit 28:16 vcnt
+//Bit 15:12 NG_ErrorOut
+//Bit 11:0 NG_VersionOut
+//
+// Closing file: ngptv_reg.h
+//
+// 8'hd0-8hef
+//
+// Reading file: bt2020_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//Bit 31:27 for all [31] for all eotf enable,[30] for matrix3x3 enable, [29:27] for eotf_ch0~3
+//Bit 17:6 for clock gating
+//Bit 5:4 pscale_mode ch2
+//Bit 3:2 pscale_mode ch1
+//Bit 1:0 pscale_mode ch0
+#define VPP_EOTF_CTL ((0x31d0 << 2) + 0xff000000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define VPP_EOTF_COEF00_01 ((0x31d1 << 2) + 0xff000000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define VPP_EOTF_COEF02_10 ((0x31d2 << 2) + 0xff000000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define VPP_EOTF_COEF11_12 ((0x31d3 << 2) + 0xff000000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define VPP_EOTF_COEF20_21 ((0x31d4 << 2) + 0xff000000)
+//Bit 28:16 coef22
+//Bit 2:0 coef_rs
+#define VPP_EOTF_COEF22_RS ((0x31d5 << 2) + 0xff000000)
+#define VPP_EOTF_LUT_ADDR_PORT ((0x31d6 << 2) + 0xff000000)
+#define VPP_EOTF_LUT_DATA_PORT ((0x31d7 << 2) + 0xff000000)
+#define VPP_EOTF_3X3_OFST_0 ((0x31d8 << 2) + 0xff000000)
+#define VPP_EOTF_3X3_OFST_1 ((0x31d9 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: bt2020_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_partb_reg.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VPPD_VCBUS_BASE = 0x32
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: vpp_vadj_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//------------------------------------------------------------------------------
+// VD1 path
+//------------------------------------------------------------------------------
+//`define VD1_IF0_GEN_REG 8'h0
+//`define VD1_IF0_CANVAS0 8'h1
+//`define VD1_IF0_CANVAS1 8'h2
+//`define VD1_IF0_LUMA_X0 8'h3
+//`define VD1_IF0_LUMA_Y0 8'h4
+//`define VD1_IF0_CHROMA_X0 8'h5
+//`define VD1_IF0_CHROMA_Y0 8'h6
+//`define VD1_IF0_LUMA_X1 8'h7
+//`define VD1_IF0_LUMA_Y1 8'h8
+//`define VD1_IF0_CHROMA_X1 8'h9
+//`define VD1_IF0_CHROMA_Y1 8'ha
+//`define VD1_IF0_RPT_LOOP 8'hb
+//`define VD1_IF0_LUMA0_RPT_PAT 8'hc
+//`define VD1_IF0_CHROMA0_RPT_PAT 8'hd
+//`define VD1_IF0_LUMA1_RPT_PAT 8'he
+//`define VD1_IF0_CHROMA1_RPT_PAT 8'hf
+//`define VD1_IF0_LUMA_PSEL 8'h10
+//`define VD1_IF0_CHROMA_PSEL 8'h11
+//`define VD1_IF0_DUMMY_PIXEL 8'h12
+//`define VD1_IF0_LUMA_FIFO_SIZE 8'h13
+//`define VD1_IF0_AXI_CMD_CNT 8'h14
+//`define VD1_IF0_AXI_RDAT_CNT 8'h15
+//`define VD1_IF0_GEN_REG3 8'h16
+//Bit 31 it true, disable clock, otherwise enable clock
+//Bit 30 soft rst bit
+//Bit 28 if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
+//Bit 27:24 horizontal formatter initial phase
+//Bit 23 horizontal formatter repeat pixel 0 enable
+//Bit 22:21 horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
+//Bit 20 horizontal formatter enable
+//Bit 19 if true, always use phase0 while vertical formater, meaning always
+// repeat data, no interpolation
+//Bit 18 if true, disable vertical formatter chroma repeat last line
+//Bit 17 veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable
+//Bit 16 veritcal formatter repeat line 0 enable
+//Bit 15:12 vertical formatter skip line num at the beginning
+//Bit 11:8 vertical formatter initial phase
+//Bit 7:1 vertical formatter phase step (3.4)
+//Bit 0 vertical formatter enable
+//`define VIU_VD1_FMT_CTRL 8'h18 //29'h0
+//Bit 27:16 horizontal formatter width
+//Bit 11:0 vertical formatter width
+//`define VIU_VD1_FMT_W 8'h19 //28'h0
+//`define VD1_IF0_RANGE_MAP_Y 8'h1a
+//`define VD1_IF0_RANGE_MAP_CB 8'h1b
+//`define VD1_IF0_RANGE_MAP_CR 8'h1c
+//`define VD1_IF0_GEN_REG2 8'h1d
+//`define VD1_IF0_PROT_CNTL 8'h1e
+//`define VD1_IF0_URGENT_CTRL 8'h1f
+//------------------------------------------------------------------------------
+// VD2 path
+//------------------------------------------------------------------------------
+//`define VD2_IF0_GEN_REG 8'h20
+//`define VD2_IF0_CANVAS0 8'h21
+//`define VD2_IF0_CANVAS1 8'h22
+//`define VD2_IF0_LUMA_X0 8'h23
+//`define VD2_IF0_LUMA_Y0 8'h24
+//`define VD2_IF0_CHROMA_X0 8'h25
+//`define VD2_IF0_CHROMA_Y0 8'h26
+//`define VD2_IF0_LUMA_X1 8'h27
+//`define VD2_IF0_LUMA_Y1 8'h28
+//`define VD2_IF0_CHROMA_X1 8'h29
+//`define VD2_IF0_CHROMA_Y1 8'h2a
+//`define VD2_IF0_RPT_LOOP 8'h2b
+//`define VD2_IF0_LUMA0_RPT_PAT 8'h2c
+//`define VD2_IF0_CHROMA0_RPT_PAT 8'h2d
+//`define VD2_IF0_LUMA1_RPT_PAT 8'h2e
+//`define VD2_IF0_CHROMA1_RPT_PAT 8'h2f
+//`define VD2_IF0_LUMA_PSEL 8'h30
+//`define VD2_IF0_CHROMA_PSEL 8'h31
+//`define VD2_IF0_DUMMY_PIXEL 8'h32
+//`define VD2_IF0_LUMA_FIFO_SIZE 8'h33
+//`define VD2_IF0_AXI_CMD_CNT 8'h34
+//`define VD2_IF0_AXI_RDAT_CNT 8'h35
+//`define VD2_IF0_GEN_REG3 8'h36
+//Bit 31 it true, disable clock, otherwise enable clock
+//Bit 30 soft rst bit
+//Bit 28 if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
+//Bit 27:24 horizontal formatter initial phase
+//Bit 23 horizontal formatter repeat pixel 0 enable
+//Bit 22:21 horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
+//Bit 20 horizontal formatter enable
+//Bit 17 veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable
+//Bit 16 veritcal formatter repeat line 0 enable
+//Bit 15:12 vertical formatter skip line num at the beginning
+//Bit 11:8 vertical formatter initial phase
+//Bit 7:1 vertical formatter phase step (3.4)
+//Bit 0 vertical formatter enable
+//`define VIU_VD2_FMT_CTRL 8'h38 //29'h0
+//Bit 27:16 horizontal formatter width
+//Bit 11:0 vertical formatter width
+//`define VIU_VD2_FMT_W 8'h39 //28'h0
+//`define VD2_IF0_RANGE_MAP_Y 8'h3a
+//`define VD2_IF0_RANGE_MAP_CB 8'h3b
+//`define VD2_IF0_RANGE_MAP_CR 8'h3c
+//`define VD2_IF0_GEN_REG2 8'h3d
+//`define VD2_IF0_PROT_CNTL 8'h3e
+//`define VD2_IF0_URGENT_CTRL 8'h3f
+#define VPP_VADJ1_MISC ((0x3280 << 2) + 0xff000000)
+#define VPP_VADJ1_BLACK_VAL ((0x3281 << 2) + 0xff000000)
+#define VPP_VADJ1_Y ((0x3282 << 2) + 0xff000000)
+#define VPP_VADJ1_MA_MB ((0x3283 << 2) + 0xff000000)
+#define VPP_VADJ1_MC_MD ((0x3284 << 2) + 0xff000000)
+#define VPP_VADJ1_CURV_0 ((0x3285 << 2) + 0xff000000)
+#define VPP_VADJ1_CURV_1 ((0x3286 << 2) + 0xff000000)
+#define VPP_VADJ1_CURV_2 ((0x3287 << 2) + 0xff000000)
+#define VPP_VADJ1_CURV_3 ((0x3288 << 2) + 0xff000000)
+#define VPP_VD1_RGB_CTRST ((0x3289 << 2) + 0xff000000)
+#define VPP_VD1_RGB_BRGHT ((0x328a << 2) + 0xff000000)
+#define VPP_VD1_RGB_DLUT_0_3 ((0x328b << 2) + 0xff000000)
+#define VPP_VD1_RGB_DLUT_4_7 ((0x328c << 2) + 0xff000000)
+#define VPP_VD1_RGB_DLUT_8_11 ((0x328d << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF00_01 ((0x3290 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF02_10 ((0x3291 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF11_12 ((0x3292 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF20_21 ((0x3293 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF22 ((0x3294 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF13_14 ((0x3295 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF23_24 ((0x3296 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_COEF15_25 ((0x3297 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_CLIP ((0x3298 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_OFFSET0_1 ((0x3299 << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_OFFSET2 ((0x329a << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_PRE_OFFSET0_1 ((0x329b << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_PRE_OFFSET2 ((0x329c << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_EN_CTRL ((0x329d << 2) + 0xff000000)
+#define VPP_VADJ2_MISC ((0x32a0 << 2) + 0xff000000)
+#define VPP_VADJ2_BLACK_VAL ((0x32a1 << 2) + 0xff000000)
+#define VPP_VADJ2_Y ((0x32a2 << 2) + 0xff000000)
+#define VPP_VADJ2_MA_MB ((0x32a3 << 2) + 0xff000000)
+#define VPP_VADJ2_MC_MD ((0x32a4 << 2) + 0xff000000)
+#define VPP_VADJ2_CURV_0 ((0x32a5 << 2) + 0xff000000)
+#define VPP_VADJ2_CURV_1 ((0x32a6 << 2) + 0xff000000)
+#define VPP_VADJ2_CURV_2 ((0x32a7 << 2) + 0xff000000)
+#define VPP_VADJ2_CURV_3 ((0x32a8 << 2) + 0xff000000)
+#define VPP_POST_RGB_CTRST ((0x32a9 << 2) + 0xff000000)
+#define VPP_POST_RGB_BRGHT ((0x32aa << 2) + 0xff000000)
+#define VPP_POST_RGB_DLUT_0_3 ((0x32ab << 2) + 0xff000000)
+#define VPP_POST_RGB_DLUT_4_7 ((0x32ac << 2) + 0xff000000)
+#define VPP_POST_RGB_DLUT_8_11 ((0x32ad << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF00_01 ((0x32b0 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF02_10 ((0x32b1 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF11_12 ((0x32b2 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF20_21 ((0x32b3 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF22 ((0x32b4 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF13_14 ((0x32b5 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF23_24 ((0x32b6 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_COEF15_25 ((0x32b7 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_CLIP ((0x32b8 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_OFFSET0_1 ((0x32b9 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_OFFSET2 ((0x32ba << 2) + 0xff000000)
+#define VPP_POST_MATRIX_PRE_OFFSET0_1 ((0x32bb << 2) + 0xff000000)
+#define VPP_POST_MATRIX_PRE_OFFSET2 ((0x32bc << 2) + 0xff000000)
+#define VPP_POST_MATRIX_EN_CTRL ((0x32bd << 2) + 0xff000000)
+#define VPP_VD1_MATRIX_SAT ((0x32c0 << 2) + 0xff000000)
+#define VPP_POST_MATRIX_SAT ((0x32c1 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_vadj_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: DOLBY1A_VCBUS_BASE = 0x33
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: dolby1a_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DOLBY_CORE1A_REG_START ((0x3300 << 2) + 0xff000000)
+#define DOLBY_CORE1A_CLKGATE_CTRL ((0x33f2 << 2) + 0xff000000)
+#define DOLBY_CORE1A_SWAP_CTRL0 ((0x33f3 << 2) + 0xff000000)
+#define DOLBY_CORE1A_SWAP_CTRL1 ((0x33f4 << 2) + 0xff000000)
+#define DOLBY_CORE1A_SWAP_CTRL2 ((0x33f5 << 2) + 0xff000000)
+#define DOLBY_CORE1A_SWAP_CTRL3 ((0x33f6 << 2) + 0xff000000)
+#define DOLBY_CORE1A_SWAP_CTRL4 ((0x33f7 << 2) + 0xff000000)
+#define DOLBY_CORE1A_SWAP_CTRL5 ((0x33f8 << 2) + 0xff000000)
+#define DOLBY_CORE1A_DMA_CTRL ((0x33f9 << 2) + 0xff000000)
+#define DOLBY_CORE1A_DMA_STATUS ((0x33fa << 2) + 0xff000000)
+#define DOLBY_CORE1A_STATUS0 ((0x33fb << 2) + 0xff000000)
+#define DOLBY_CORE1A_STATUS1 ((0x33fc << 2) + 0xff000000)
+#define DOLBY_CORE1A_STATUS2 ((0x33fd << 2) + 0xff000000)
+#define DOLBY_CORE1A_STATUS3 ((0x33fe << 2) + 0xff000000)
+#define DOLBY_CORE1A_DMA_PORT ((0x33ff << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dolby1a_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: DOLBY2A_VCBUS_BASE = 0x34
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: dolby2a_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DOLBY_CORE2A_REG_START ((0x3400 << 2) + 0xff000000)
+#define DOLBY_CORE2A_CLKGATE_CTRL ((0x3432 << 2) + 0xff000000)
+#define DOLBY_CORE2A_SWAP_CTRL0 ((0x3433 << 2) + 0xff000000)
+#define DOLBY_CORE2A_SWAP_CTRL1 ((0x3434 << 2) + 0xff000000)
+#define DOLBY_CORE2A_SWAP_CTRL2 ((0x3435 << 2) + 0xff000000)
+#define DOLBY_CORE2A_SWAP_CTRL3 ((0x3436 << 2) + 0xff000000)
+#define DOLBY_CORE2A_SWAP_CTRL4 ((0x3437 << 2) + 0xff000000)
+#define DOLBY_CORE2A_SWAP_CTRL5 ((0x3438 << 2) + 0xff000000)
+#define DOLBY_CORE2A_DMA_CTRL ((0x3439 << 2) + 0xff000000)
+#define DOLBY_CORE2A_DMA_STATUS ((0x343a << 2) + 0xff000000)
+#define DOLBY_CORE2A_STATUS0 ((0x343b << 2) + 0xff000000)
+#define DOLBY_CORE2A_STATUS1 ((0x343c << 2) + 0xff000000)
+#define DOLBY_CORE2A_STATUS2 ((0x343d << 2) + 0xff000000)
+#define DOLBY_CORE2A_STATUS3 ((0x343e << 2) + 0xff000000)
+#define DOLBY_CORE2A_DMA_PORT ((0x343f << 2) + 0xff000000)
+#define DOLBY_CORE2A_AXI2DMA_CTRL0 ((0x3440 << 2) + 0xff000000)
+#define DOLBY_CORE2A_AXI2DMA_CTRL1 ((0x3441 << 2) + 0xff000000)
+#define DOLBY_CORE2A_AXI2DMA_CTRL2 ((0x3442 << 2) + 0xff000000)
+#define DOLBY_CORE2A_AXI2DMA_CTRL3 ((0x3443 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dolby2a_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: DOLBY2B_VCBUS_BASE = 0x35
+// -----------------------------------------------
+//===========================================================================
+//`include "dolby2b_regs.h"
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: DOLBY3_VCBUS_BASE = 0x36
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: dolby3_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DOLBY_CORE3_REG_START ((0x3600 << 2) + 0xff000000)
+#define DOLBY_CORE3_CLKGATE_CTRL ((0x36f0 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL0 ((0x36f1 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL1 ((0x36f2 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL2 ((0x36f3 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL3 ((0x36f4 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL4 ((0x36f5 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL5 ((0x36f6 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL6 ((0x36f7 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL7 ((0x36f8 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL8 ((0x36f9 << 2) + 0xff000000)
+#define DOLBY_CORE3_SWAP_CTRL9 ((0x36fa << 2) + 0xff000000)
+#define DOLBY_CORE3_STATUS0 ((0x36fb << 2) + 0xff000000)
+#define DOLBY_CORE3_STATUS1 ((0x36fc << 2) + 0xff000000)
+#define DOLBY_CORE3_STATUS2 ((0x36fd << 2) + 0xff000000)
+#define DOLBY_CORE3_STATUS3 ((0x36fe << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dolby3_regs.h
+//
+//===========================================================================
+//===========================================================================
+//
+// Reading file: vpu_madc_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: MADC_VCBUS_BASE = 0x37
+// -----------------------------------------------
+// 0x00-0x28
+//
+// Reading file: nr4_nm_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define NR4_MCNR_SAD_GAIN ((0x3700 << 2) + 0xff000000)
+//Bit 31:25 reserved
+//Bit 24 reg_nr4_bld12vs3_usemaxsad // unsigned , default = 0 use minsad/maxsad instead of minsad/avgsad to decision if it was texture or flat region, 1: use minsad/maxsad
+//Bit 23:16 reg_nr4_bld12vs3_rate_gain // unsigned , default = 64 gain to minsad/maxsad or minsad/avgsad before LUT, 64 normalized as "1"
+//Bit 15: 8 reg_nr4_bld1vs2_rate_gain // unsigned , default = 32 gain to minsad/maxsad or minsad/avgsad before the LUT, 64 normalized as"1"
+//Bit 7: 0 reg_nr4_coefblt_gain // unsigned , default = 64 gain to final coefblt, normalized 64 as "1"
+#define NR4_MCNR_LPF_CTRL ((0x3701 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:22 reg_nr4_preflt_alpofst // signed , default = 0 pre filter alpha ofst
+//Bit 21:16 reg_nr4_preflt_alpgain // unsigned , default = 16 pre filter alpha gain
+//Bit 15:14 reg_nr4_preflt_alpsel // unsigned , default = 3 pre filter alpha selection for adaptive blending, 0: mv pointed sad, 1: weighted mv pointed sad, 2or3: coefblt
+//Bit 13: 8 reg_nr4_avgsad_gain // unsigned , default = 8 gain for avg sad before luts
+//Bit 7 reserved
+//Bit 6 reg_nr4_maxsad_mod // unsigned , default = 1 max sad select mode, 0: mx2_sad, 1: max sad
+//Bit 5 reg_nr4_minsad_mod // unsigned , default = 1 min sad select mode, 0: sad with min err, 1: min sad
+//Bit 4 reg_nr4_minmaxsad_lpf // unsigned , default = 1 mode of lpf for minmaxsad, 0: no LPF, 1: [1 2 1]/4
+//Bit 3 reg_nr4_avgsad_lpf // unsigned , default = 1 mode of lpf for avgsad, 0: no LPF, 1: [1 2 1]/4
+//Bit 2 reg_nr4_minavgsad_ratio_lpf // unsigned , default = 1 mode of lpf for minsad/avgsad and zmvsad/avgsad, 0: no LPF, 1: [1 2 1]/4
+//Bit 1 reg_nr4_bldvs_lut_lpf // unsigned , default = 1 mode of lpf for bld12vs3 and bld1vs2 LUT results, 0: no LPF, 1: [1 2 1]/4
+//Bit 0 reg_nr4_final_coef_lpf // unsigned , default = 1 mode of lpf for final coef_blt_blend123, 0: no LPF, 1: [1 2 1]/4
+#define NR4_MCNR_BLD_VS3LUT0 ((0x3702 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_bld12vs3_lut0 // unsigned , default = 0
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_bld12vs3_lut1 // unsigned , default = 8
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_bld12vs3_lut2 // unsigned , default = 10
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bld12vs3_lut3 // unsigned , default = 11
+#define NR4_MCNR_BLD_VS3LUT1 ((0x3703 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_bld12vs3_lut4 // unsigned , default = 12
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_bld12vs3_lut5 // unsigned , default = 14
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_bld12vs3_lut6 // unsigned , default = 16
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bld12vs3_lut7 // unsigned , default = 24
+#define NR4_MCNR_BLD_VS3LUT2 ((0x3704 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_bld12vs3_lut8 // unsigned , default = 50
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_bld12vs3_lut9 // unsigned , default = 58
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_bld12vs3_lut10 // unsigned , default = 63
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bld12vs3_lut11 // unsigned , default = 63
+#define NR4_MCNR_BLD_VS2LUT0 ((0x3705 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_bld1vs2_lut0 // unsigned , default = 63
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_bld1vs2_lut1 // unsigned , default = 32
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_bld1vs2_lut2 // unsigned , default = 16
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bld1vs2_lut3 // unsigned , default = 8
+#define NR4_MCNR_BLD_VS2LUT1 ((0x3706 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nr4_bld1vs2_lut4 // unsigned , default = 4
+//Bit 23:22 reserved
+//Bit 21:16 reg_nr4_bld1vs2_lut5 // unsigned , default = 2
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nr4_bld1vs2_lut6 // unsigned , default = 1
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nr4_bld1vs2_lut7 // unsigned , default = 0
+#define NR4_COEFBLT_LUT10 ((0x3707 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut10 // signed , default = -128
+//Bit 23:16 reg_nr4_coefblt_lut11 // signed , default = -128
+//Bit 15: 8 reg_nr4_coefblt_lut12 // signed , default = -126
+//Bit 7: 0 reg_nr4_coefblt_lut13 // signed , default = -124
+#define NR4_COEFBLT_LUT11 ((0x3708 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut14 // signed , default = -120
+//Bit 23:16 reg_nr4_coefblt_lut15 // signed , default = -110
+//Bit 15: 8 reg_nr4_coefblt_lut16 // signed , default = -100
+//Bit 7: 0 reg_nr4_coefblt_lut17 // signed , default = -90
+#define NR4_COEFBLT_LUT12 ((0x3709 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut18 // signed , default = -56
+//Bit 23:16 reg_nr4_coefblt_lut19 // signed , default = -32
+//Bit 15: 8 reg_nr4_coefblt_lut110 // signed , default = -64
+//Bit 7: 0 reg_nr4_coefblt_lut111 // signed , default = -128
+#define NR4_COEFBLT_LUT20 ((0x370a << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut20 // signed , default = -128
+//Bit 23:16 reg_nr4_coefblt_lut21 // signed , default = -120
+//Bit 15: 8 reg_nr4_coefblt_lut22 // signed , default = -112
+//Bit 7: 0 reg_nr4_coefblt_lut23 // signed , default = -104
+#define NR4_COEFBLT_LUT21 ((0x370b << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut24 // signed , default = -96
+//Bit 23:16 reg_nr4_coefblt_lut25 // signed , default = -88
+//Bit 15: 8 reg_nr4_coefblt_lut26 // signed , default = -76
+//Bit 7: 0 reg_nr4_coefblt_lut27 // signed , default = -64
+#define NR4_COEFBLT_LUT22 ((0x370c << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut28 // signed , default = -48
+//Bit 23:16 reg_nr4_coefblt_lut29 // signed , default = -32
+//Bit 15: 8 reg_nr4_coefblt_lut210 // signed , default = -64
+//Bit 7: 0 reg_nr4_coefblt_lut211 // signed , default = -108
+#define NR4_COEFBLT_LUT30 ((0x370d << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut30 // signed , default = 8
+//Bit 23:16 reg_nr4_coefblt_lut31 // signed , default = 16
+//Bit 15: 8 reg_nr4_coefblt_lut32 // signed , default = 24
+//Bit 7: 0 reg_nr4_coefblt_lut33 // signed , default = 30
+#define NR4_COEFBLT_LUT31 ((0x370e << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut34 // signed , default = 36
+//Bit 23:16 reg_nr4_coefblt_lut35 // signed , default = 48
+//Bit 15: 8 reg_nr4_coefblt_lut36 // signed , default = 70
+//Bit 7: 0 reg_nr4_coefblt_lut37 // signed , default = 96
+#define NR4_COEFBLT_LUT32 ((0x370f << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_coefblt_lut38 // signed , default = 120
+//Bit 23:16 reg_nr4_coefblt_lut39 // signed , default = 64
+//Bit 15: 8 reg_nr4_coefblt_lut310 // signed , default = 16
+//Bit 7: 0 reg_nr4_coefblt_lut311 // signed , default = -8
+#define NR4_COEFBLT_CONV ((0x3710 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_nr4_coefblt_convmin // unsigned , default = 0 minimum of coef. bilateral conversion
+//Bit 15: 8 reg_nr4_coefblt_convmax // unsigned , default = 255 maximum of coef. bilateral conversion
+//Bit 7: 0 reg_nr4_coefblt_convmid // unsigned , default = 128 value at midpoint of coef. bilateral conversion
+#define NR4_DBGWIN_YX0 ((0x3711 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_nr4_dgbwin_yx0 // unsigned , default = 100 ystart for debug window
+//Bit 15:14 reserved
+//Bit 13: 0 reg_nr4_dgbwin_yx1 // unsigned , default = 160 yend for debug window
+#define NR4_DBGWIN_YX1 ((0x3712 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_nr4_dgbwin_yx2 // unsigned , default = 200 xstart for debug window
+//Bit 15:14 reserved
+//Bit 13: 0 reg_nr4_dgbwin_yx3 // unsigned , default = 300 xend for debug window
+#define NR4_NM_X_CFG ((0x3713 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_nr4_nm_xst // unsigned , default = 8 start for noise meter statistic, dft = 8
+//Bit 15:14 reserved
+//Bit 13: 0 reg_nr4_nm_xed // unsigned , default = 711 end for noise meter statistic, dft = HSIZE-8-1;
+#define NR4_NM_Y_CFG ((0x3714 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:16 reg_nr4_nm_yst // unsigned , default = 8 start for noise meter statistic, dft = 8;
+//Bit 15:14 reserved
+//Bit 13: 0 reg_nr4_nm_yed // unsigned , default = 231 end for noise meter statistic, dft = VSIZE-8-1;
+#define NR4_NM_SAD_THD ((0x3715 << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7: 0 reg_nr4_nm_sad_thd // unsigned , default = 255 threshold for (flat region) sad count, dft = 4
+#define NR4_MCNR_BANDSPLIT_PRAM ((0x3716 << 2) + 0xff000000)
+//Bit 31: 5 reserved
+//Bit 4 reg_nr4_mc_use_bandsplit // unsigned , default = 1 separate lp and us for mc IIR filter, 0: no BS used; 1: use BS
+//Bit 3 reg_nr4_mc_apply_on_lp // unsigned , default = 1 use mcnr only on lowpass portion;
+//Bit 2 reg_nr4_mc_apply_on_us // unsigned , default = 1 use mcnr only on lp complimentary portion;
+//Bit 1: 0 reg_nr4_mc_zmvbs_use_adplpf // unsigned , default = 1 use adapptive LPF for the zmv pointing data for MCNR, for abs(mvx)<th
+#define NR4_MCNR_ALP1_SGN_COR ((0x3717 << 2) + 0xff000000)
+//Bit 31:24 reg_nr4_mc_aph1_sgn_coring0 // unsigned , default = 10 coring to cur-pre before do sgn decision
+//Bit 23:16 reg_nr4_mc_aph1_sgn_coring1 // unsigned , default = 7 coring to cur-pre before do sgn decision
+//Bit 15: 8 reg_nr4_mc_aph1_sgn_core_max0 // unsigned , default = 90 maximum of coring, default = 30/15
+//Bit 7: 0 reg_nr4_mc_aph1_sgn_core_max1 // unsigned , default = 15 maximum of coring, default = 30/15
+#define NR4_MCNR_ALP1_SGN_PRAM ((0x3718 << 2) + 0xff000000)
+//Bit 31:11 reserved
+//Bit 10 reg_nr4_mc_alp1_sgn_half // unsigned , default = 1 half block sgn sum mode enable, 0: only use 3x5 whole block sum of sgns; 1: use max(sgn_3x5, sqrt(sgn_left+sgn_righ))
+//Bit 9 reg_nr4_mc_alp1_sgn_frczmv // unsigned , default = 1 force zmv to calculate the sign_sum;
+//Bit 8 reg_nr4_mc_alp1_sgnmvx_mode // unsigned , default = 1 blend mode of sgnlut and mvxlut blend mode: 0: sgnlut+ mvxlut; 1: max(sgnlut, mvxlut), default =1
+//Bit 7: 4 reg_nr4_mc_aph1_sgn_crate0 // unsigned , default = 4 rate to var, norm to 16 as 1, default = 2
+//Bit 3: 0 reg_nr4_mc_aph1_sgn_crate1 // unsigned , default = 2 rate to var, norm to 16 as 1, default = 2
+#define NR4_MCNR_ALP1_MVX_LUT1 ((0x3719 << 2) + 0xff000000)
+//Bit 31:28 reg_nr4_mc_alp1_mvx_luty3 // unsigned , default = 14 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 27:24 reg_nr4_mc_alp1_mvx_lutc3 // unsigned , default = 14 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 23:20 reg_nr4_mc_alp1_mvx_luty2 // unsigned , default = 12 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 19:16 reg_nr4_mc_alp1_mvx_lutc2 // unsigned , default = 12 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 15:12 reg_nr4_mc_alp1_mvx_luty1 // unsigned , default = 5 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 11: 8 reg_nr4_mc_alp1_mvx_lutc1 // unsigned , default = 5 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 7: 4 reg_nr4_mc_alp1_mvx_luty0 // unsigned , default = 3 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 3: 0 reg_nr4_mc_alp1_mvx_lutc0 // unsigned , default = 3 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+#define NR4_MCNR_ALP1_MVX_LUT2 ((0x371a << 2) + 0xff000000)
+//Bit 31:28 reg_nr4_mc_alp1_mvx_luty7 // unsigned , default = 15 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 27:24 reg_nr4_mc_alp1_mvx_lutc7 // unsigned , default = 15 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 23:20 reg_nr4_mc_alp1_mvx_luty6 // unsigned , default = 15 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 19:16 reg_nr4_mc_alp1_mvx_lutc6 // unsigned , default = 15 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 15:12 reg_nr4_mc_alp1_mvx_luty5 // unsigned , default = 15 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 11: 8 reg_nr4_mc_alp1_mvx_lutc5 // unsigned , default = 15 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 7: 4 reg_nr4_mc_alp1_mvx_luty4 // unsigned , default = 15 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 3: 0 reg_nr4_mc_alp1_mvx_lutc4 // unsigned , default = 15 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+#define NR4_MCNR_ALP1_MVX_LUT3 ((0x371b << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7: 4 reg_nr4_mc_alp1_mvx_luty8 // unsigned , default = 6 alp1 of luma vas mvx(0~7), and alp1 vs mvy(0,1)
+//Bit 3: 0 reg_nr4_mc_alp1_mvx_lutc8 // unsigned , default = 6 alp1 of chrm vas mvx(0~7), and alp1 vs mvy(0,1)
+#define NR4_MCNR_ALP1_LP_PRAM ((0x371c << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:16 reg_nr4_mc_alp1_lp_sel // unsigned , default = 1 mode for alp1_lp for lp portion IIR, 0: apha1, 1:dc_dif vs ac analysis; 2: gain/ofst of alp1; 3: max of #1/#2 results
+//Bit 15: 8 reg_nr4_mc_alp1_lp_gain // unsigned , default = 64 gain to alp1 to get the alp1_lp = alp1*gain/32 + ofset, default =64;
+//Bit 7: 0 reg_nr4_mc_alp1_lp_ofst // signed , default = 0 offset to alp1 to get the alp1_lp = alp1*gain/32 + ofset, default =10;
+#define NR4_MCNR_ALP1_SGN_LUT1 ((0x371d << 2) + 0xff000000)
+//Bit 31:28 reg_nr4_mc_alp1_sgn_lut0 // unsigned , default = 3 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 27:24 reg_nr4_mc_alp1_sgn_lut1 // unsigned , default = 3 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 23:20 reg_nr4_mc_alp1_sgn_lut2 // unsigned , default = 3 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 19:16 reg_nr4_mc_alp1_sgn_lut3 // unsigned , default = 4 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 15:12 reg_nr4_mc_alp1_sgn_lut4 // unsigned , default = 5 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 11: 8 reg_nr4_mc_alp1_sgn_lut5 // unsigned , default = 6 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 7: 4 reg_nr4_mc_alp1_sgn_lut6 // unsigned , default = 7 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 3: 0 reg_nr4_mc_alp1_sgn_lut7 // unsigned , default = 8 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+#define NR4_MCNR_ALP1_SGN_LUT2 ((0x371e << 2) + 0xff000000)
+//Bit 31:28 reg_nr4_mc_alp1_sgn_lut8 // unsigned , default = 9 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 27:24 reg_nr4_mc_alp1_sgn_lut9 // unsigned , default = 10 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 23:20 reg_nr4_mc_alp1_sgn_lut10 // unsigned , default = 11 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 19:16 reg_nr4_mc_alp1_sgn_lut11 // unsigned , default = 12 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 15:12 reg_nr4_mc_alp1_sgn_lut12 // unsigned , default = 13 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 11: 8 reg_nr4_mc_alp1_sgn_lut13 // unsigned , default = 14 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 7: 4 reg_nr4_mc_alp1_sgn_lut14 // unsigned , default = 15 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+//Bit 3: 0 reg_nr4_mc_alp1_sgn_lut15 // unsigned , default = 15 alp1 vs x=abs|sgn(cur-pre)|, if x is small, less possibility of flat region move
+#define NR4_RO_NM_SAD_SUM ((0x371f << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_nm_sad_sum // unsigned , default = 0 sum of sad, for scene change detectcion, in noise meter
+#define NR4_RO_NM_SAD_CNT ((0x3720 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_nm_sad_cnt // unsigned , default = 0 cnt of sad, for scene change detectcion, in noise meter
+#define NR4_RO_NM_VAR_SUM ((0x3721 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_nm_var_sum // unsigned , default = 0 sum of var, for noise level detection, in noise meter
+#define NR4_RO_NM_VAR_SCNT ((0x3722 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_nm_var_cnt // unsigned , default = 0 cnt of var, for noise level detection, in noise meter
+#define NR4_RO_NM_VAR_MIN_MAX ((0x3723 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:12 ro_nr4_nm_min_var // unsigned , default = 1023 min of var, for noise level detection, in noise meter
+//Bit 11:10 reserved
+//Bit 9: 0 ro_nr4_nm_max_var // unsigned , default = 0 max of var, for noise level detection, in noise meter
+#define NR4_RO_NR4_DBGPIX_NUM ((0x3724 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27: 0 ro_nr4_dbgpix_num // unsigned , default = 0 number of pixels statistic invoved (removed?)
+#define NR4_RO_NR4_BLDVS2_SUM ((0x3725 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_bld1vs2_sum // unsigned , default = 0 sum of blend_1vs2 with the debug window
+#define NR4_BLDVS3_SUM ((0x3726 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_bld12vs3_sum // unsigned , default = 0 sum of blend_12vs3 with the debug window
+#define NR4_COEF12_SUM ((0x3727 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_coef12_sum // signed , default = 0 sum of coef_blt_blend12 with the debug window, under 8 bits precision
+#define NR4_COEF123_SUM ((0x3728 << 2) + 0xff000000)
+//Bit 31: 0 ro_nr4_coef123_sum // signed , default = 0 sum of coef_final with the debug window, under 8 bits precision
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: nr4_nm_regs.h
+//
+// 0x30-0x33
+//
+// Reading file: vpu_xlr_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define XLR_CTRL ((0x3730 << 2) + 0xff000000)
+//Bit 31:23 reserved
+//Bit 22 reg_xlr_en // unsigned , default = 1 enable bits for xlr function, 1: enable, 0: disable default = 1
+//Bit 21 reg_xlr_side_en // unsigned , default = 1 enable to filter the above and below lines with xlr filter, default = 1
+//Bit 20 reg_xlr_3lines // unsigned , default = 1 3 lines version enable default= 0
+//Bit 19:16 reg_xlr_simlp_gain // unsigned , default = 12 gain to simlp to decide if need the XLR, default= 12
+//Bit 15:14 reserved
+//Bit 13: 8 reg_xlr_ooplp_gain // unsigned , default = 6 gain to out-of-phase lp error to decide if need the XLR, birn to 16 as 1, default= 3
+//Bit 7: 0 reg_xlr_dislp_thrd // unsigned , default = 64 threshold to lp error to discard XLR. default= 80
+#define XLR_THRD ((0x3731 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:24 reg_xlr_txt_core // unsigned , default = 3 coring to texture default = 3, (3/32)
+//Bit 23:16 reg_xlr_err_thrd2 // unsigned , default = 5 threshold to error to decide blending coef, 0, 1/4, 1/2, 1.0, defaut= {20, 10, 5}
+//Bit 15: 8 reg_xlr_err_thrd1 // unsigned , default = 10 threshold to error to decide blending coef, 0, 1/4, 1/2, 1.0, defaut= {20, 10, 5}
+//Bit 7: 0 reg_xlr_err_thrd0 // unsigned , default = 20 threshold to error to decide blending coef, 0, 1/4, 1/2, 1.0, defaut= {20, 10, 5}
+#define XLR_HCT_THRD ((0x3732 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 reg_xlr_hct_step // unsigned , default = 1 horizontal chroma diff steps, 0: abs[-1 (2) -1]; 1: abs[-1 0 (2) 0 -1], 2: abs[-1 0 0 (2) 0 0 -1]; 3:abs[-1 0 0 0 (2) 0 0 0 -1]
+//Bit 25:24 reg_xlr_hct_lpf // unsigned , default = 1 horizontal chroma diff low-pass filter enable, 0: no HLPF; 1: [1 2 1]; 2: max[-1:1]; 3: max[-2:2]
+//Bit 23:16 reg_xlr_hct_thr // unsigned , default = 20 horizontal chroma diff threshold for xlr enable, to save the horozontal no color tran mode
+//Bit 15: 8 reg_xlr_sat_thr // unsigned , default = 8 saturation threshold for xlr enable, the smaller of the threshold , the more will do xlr;
+//Bit 7: 2 reg_xlr_hmargin // unsigned , default = 3 left/right number of pixels without xlr;
+//Bit 1 reserved
+//Bit 0 reg_xlr_hpf_only // unsigned , default = 0 enable for only do xlr filter on high pass portion of the data, instead full data
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_xlr_regs.h
+//
+// 0x38-0x3f
+//
+// Reading file: nr_deband_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define NR_DB_FLT_CTRL ((0x3738 << 2) + 0xff000000)
+//Bit 31:27 reserved
+//Bit 26 reg_nrdeband_reset1 // unsigned , default = 0 0 : no reset seed 1: reload chroma seed
+//Bit 25 reg_nrdeband_reset0 // unsigned , default = 0 0 : no reset seed 1: reload luma seed
+//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 0 : yuv 1: RGB
+//Bit 23 reg_nrdeband_en11 // unsigned , default = 1 debanding registers of side lines, [0] for luma, same for below
+//Bit 22 reg_nrdeband_en10 // unsigned , default = 1 debanding registers of side lines, [1] for chroma, same for below
+//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
+//Bit 16 reserved
+//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
+//Bit 12 reserved
+//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6
+//Bit 8 reserved
+//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 debanding random hp portion xor, [0] for luma
+//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 debanding random hp portion xor, [1] for chroma
+//Bit 5 reg_nrdeband_en1 // unsigned , default = 1 debanding registers, for luma
+//Bit 4 reg_nrdeband_en0 // unsigned , default = 1 debanding registers, for chroma
+//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+#define NR_DB_FLT_YC_THRD ((0x3739 << 2) + 0xff000000)
+//Bit 31:28 reg_nrdeband_luma_th3 // unsigned , default = 9 threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 27:24 reg_nrdeband_luma_th2 // unsigned , default = 7 elseif <th[1] use (lpf*3 + y)/4
+//Bit 23:20 reg_nrdeband_luma_th1 // unsigned , default = 6 elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 19:16 reg_nrdeband_luma_th0 // unsigned , default = 5 elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else
+//Bit 15:12 reg_nrdeband_chrm_th3 // unsigned , default = 9 threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 11: 8 reg_nrdeband_chrm_th2 // unsigned , default = 7 elseif <th[1] use (lpf*3 + y)/4
+//Bit 7: 4 reg_nrdeband_chrm_th1 // unsigned , default = 6 elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 3: 0 reg_nrdeband_chrm_th0 // unsigned , default = 5 elseif <th[1] use (lpf*3 + y)/4elseif elseif
+#define NR_DB_FLT_RANDLUT ((0x373a << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:21 reg_nrdeband_randslut7 // unsigned , default = 1 lut0
+//Bit 20:18 reg_nrdeband_randslut6 // unsigned , default = 1 lut0
+//Bit 17:15 reg_nrdeband_randslut5 // unsigned , default = 1 lut0
+//Bit 14:12 reg_nrdeband_randslut4 // unsigned , default = 1 lut0
+//Bit 11: 9 reg_nrdeband_randslut3 // unsigned , default = 1 lut0
+//Bit 8: 6 reg_nrdeband_randslut2 // unsigned , default = 1 lut0
+//Bit 5: 3 reg_nrdeband_randslut1 // unsigned , default = 1 lut0
+//Bit 2: 0 reg_nrdeband_randslut0 // unsigned , default = 1 lut0
+#define NR_DB_FLT_PXI_THRD ((0x373b << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 to luma/|u/v| for using the denoise
+//Bit 15:10 reserved
+//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 to luma/|u/v| for using the denoise
+#define NR_DB_FLT_SEED_Y ((0x373c << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 noise adding seed for Y. seed[0]= 0x60a52f20; as default
+#define NR_DB_FLT_SEED_U ((0x373d << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 noise adding seed for U. seed[0]= 0x60a52f27; as default
+#define NR_DB_FLT_SEED_V ((0x373e << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define NR_DB_FLT_SEED3 ((0x373f << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed3 // unsigned , default = 1621438242 noise adding seed for V. seed[0]= 0x60a52f22; as default
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: nr_deband_regs.h
+//
+// 0x40-0x43
+//
+// Reading file: nr_downscale_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define NR_DS_BUF_SIZE ((0x3740 << 2) + 0xff000000)
+//Bit 31:24 dsbuf_rowmax // unsigned , default = 96
+//Bit 23:16 dsbuf_colmax // unsigned , default = 128
+//Bit 15: 8 dsbuf_orow // unsigned , default = 128
+//Bit 7: 0 dsbuf_ocol // unsigned , default = 128
+#define NR_DS_CTRL ((0x3741 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_h_step // unsigned , default = 8 rand lut0
+//Bit 23:22 reserved
+//Bit 21:16 reg_v_step // unsigned , default = 8 rand lut0
+//Bit 15 reserved
+//Bit 14:12 reg_haa_sel // unsigned , default = 4
+//Bit 11 reserved
+//Bit 10: 8 reg_vaa_sel // unsigned , default = 4
+//Bit 7 reserved
+//Bit 6: 4 reg_use_hphase // unsigned , default = 1
+//Bit 3: 1 reserved
+//Bit 0 reg_yuv_bldmode // unsigned , default = 0
+#define NR_DS_OFFSET ((0x3742 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_h_ofst // signed , default = 0
+//Bit 15:10 reserved
+//Bit 9: 0 reg_v_ofst // signed , default = 0
+#define NR_DS_BLD_COEF ((0x3743 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_yuv_bldcoef2 // unsigned , default = 128
+//Bit 15: 8 reg_yuv_bldcoef1 // unsigned , default = 64
+//Bit 7: 0 reg_yuv_bldcoef0 // unsigned , default = 64
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: nr_downscale_regs.h
+//
+// 0x44-0xbf
+//
+// Reading file: di_scale_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DI_SCO_FIFO_CTRL ((0x374e << 2) + 0xff000000)
+#define DI_SC_TOP_CTRL ((0x374f << 2) + 0xff000000)
+// dummy data used in the DI preblend and scaler
+// Bit 23:16 Y
+// Bit 15:8 CB
+// Bit 7:0 CR
+#define DI_SC_DUMMY_DATA ((0x3750 << 2) + 0xff000000)
+//input line length used in DI
+#define DI_SC_LINE_IN_LENGTH ((0x3751 << 2) + 0xff000000)
+//input Picture height used in DI
+#define DI_SC_PIC_IN_HEIGHT ((0x3752 << 2) + 0xff000000)
+//Because there are many coefficients used in the vertical filter and horizontal filters,
+//indirect access the coefficients of vertical filter and horizontal filter is used.
+//For vertical filter, there are 33x4 coefficients
+//For horizontal filter, there are 33x4 coefficients
+//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
+//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
+//Bit 13 if true, vertical separated coef enable
+//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
+//Bit 8:7 type of index, 00: vertical coef, 01: vertical chroma coef: 10: horizontal coef, 11: resevered
+//Bit 6:0 coef index
+#define DI_SC_COEF_IDX ((0x3753 << 2) + 0xff000000)
+//coefficients for vertical filter and horizontal filter
+#define DI_SC_COEF ((0x3754 << 2) + 0xff000000)
+//these following registers are the absolute line address pointer for output divided screen
+//The output divided screen is shown in the following:
+//
+// -------------------------- <------ line zero
+// .
+// .
+// . region0 <---------- nonlinear region or nonscaling region
+// .
+// ---------------------------
+// --------------------------- <------ region1_startp
+// .
+// . region1 <---------- nonlinear region
+// .
+// .
+// ---------------------------
+// --------------------------- <------ region2_startp
+// .
+// . region2 <---------- linear region
+// .
+// .
+// ---------------------------
+// --------------------------- <------ region3_startp
+// .
+// . region3 <---------- nonlinear region
+// .
+// .
+// ---------------------------
+// --------------------------- <------ region4_startp
+// .
+// . region4 <---------- nonlinear region or nonoscaling region
+// .
+// .
+// --------------------------- <------ region4_endp
+//Bit 28:16 region1 startp
+//Bit 12:0 region2 startp
+#define DI_VSC_REGION12_STARTP ((0x3755 << 2) + 0xff000000)
+//Bit 28:16 region3 startp
+//Bit 12:0 region4 startp
+#define DI_VSC_REGION34_STARTP ((0x3756 << 2) + 0xff000000)
+#define DI_VSC_REGION4_ENDP ((0x3757 << 2) + 0xff000000)
+//vertical start phase step, (source/dest)*(2^24)
+//Bit 27:24 integer part
+//Bit 23:0 fraction part
+#define DI_VSC_START_PHASE_STEP ((0x3758 << 2) + 0xff000000)
+//vertical scaler region0 phase slope, Bit24 signed bit
+#define DI_VSC_REGION0_PHASE_SLOPE ((0x3759 << 2) + 0xff000000)
+//vertical scaler region1 phase slope, Bit24 signed bit
+#define DI_VSC_REGION1_PHASE_SLOPE ((0x375a << 2) + 0xff000000)
+//vertical scaler region3 phase slope, Bit24 signed bit
+#define DI_VSC_REGION3_PHASE_SLOPE ((0x375b << 2) + 0xff000000)
+//vertical scaler region4 phase slope, Bit24 signed bit
+#define DI_VSC_REGION4_PHASE_SLOPE ((0x375c << 2) + 0xff000000)
+//Bit 18:17 double line mode, input/output line width of vscaler becomes 2X,
+// so only 2 line buffer in this case, use for 3D line by line interleave scaling
+// bit1 true, double the input width and half input height, bit0 true, change line buffer 2 lines instead of 4 lines
+//Bit 16 0: progressive output, 1: interlace output
+//Bit 15 vertical scaler output line0 in advance or not for bottom field
+//Bit 14:13 vertical scaler initial repeat line0 number for bottom field
+//Bit 11:8 vertical scaler initial receiving number for bottom field
+//Bit 7 vertical scaler output line0 in advance or not for top field
+//Bit 6:5 vertical scaler initial repeat line0 number for top field
+//Bit 3:0 vertical scaler initial receiving number for top field
+#define DI_VSC_PHASE_CTRL ((0x375d << 2) + 0xff000000)
+//Bit 31:16 vertical scaler field initial phase for bottom field
+//Bit 15:0 vertical scaler field initial phase for top field
+#define DI_VSC_INI_PHASE ((0x375e << 2) + 0xff000000)
+//Bit 28:16 region1 startp
+//Bit 12:0 region2 startp
+#define DI_HSC_REGION12_STARTP ((0x3760 << 2) + 0xff000000)
+//Bit 28:16 region3 startp
+//Bit 12:0 region4 startp
+#define DI_HSC_REGION34_STARTP ((0x3761 << 2) + 0xff000000)
+#define DI_HSC_REGION4_ENDP ((0x3762 << 2) + 0xff000000)
+//horizontal start phase step, (source/dest)*(2^24)
+//Bit 27:24 integer part
+//Bit 23:0 fraction part
+#define DI_HSC_START_PHASE_STEP ((0x3763 << 2) + 0xff000000)
+//horizontal scaler region0 phase slope, Bit24 signed bit
+#define DI_HSC_REGION0_PHASE_SLOPE ((0x3764 << 2) + 0xff000000)
+//horizontal scaler region1 phase slope, Bit24 signed bit
+#define DI_HSC_REGION1_PHASE_SLOPE ((0x3765 << 2) + 0xff000000)
+//horizontal scaler region3 phase slope, Bit24 signed bit
+#define DI_HSC_REGION3_PHASE_SLOPE ((0x3766 << 2) + 0xff000000)
+//horizontal scaler region4 phase slope, Bit24 signed bit
+#define DI_HSC_REGION4_PHASE_SLOPE ((0x3767 << 2) + 0xff000000)
+//Bit 22:21 horizontal scaler initial repeat pixel0 number0
+//Bit 19:16 horizontal scaler initial receiving number0
+//Bit 15:0 horizontal scaler top field initial phase0
+#define DI_HSC_PHASE_CTRL ((0x3768 << 2) + 0xff000000)
+// Bit 31 if false, di_scale swap layer bypass
+// bit 30 if true, scale before diwr, else scaler before nrwr
+// Bit 22 if true, divide VSC line length 2 as the HSC input length, othwise VSC length length is the same as the VSC line length,
+// just for special usage, more flexibility
+// Bit 21 if true, prevsc uses lin buffer, otherwise prevsc does not use line buffer, it should be same as prevsc_en
+// Bit 20 prehsc_en
+// Bit 19 prevsc_en
+// Bit 18 vsc_en
+// Bit 17 hsc_en
+// Bit 16 scale_top_en
+// Bit 15 video1 scale out enable
+// Bit 12 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for horizontal scaler
+// Bit 10:8 horizontal scaler bank length
+// Bit 5, vertical scaler phase field mode, if true, disable the opposite parity line output, more bandwith needed if output 1080i
+// Bit 4 if true, region0,region4 are nonlinear regions, otherwise they are not scaling regions, for vertical scaler
+// Bit 2:0 vertical scaler bank length
+#define DI_SC_MISC ((0x3769 << 2) + 0xff000000)
+#define DI_HSC_PHASE_CTRL1 ((0x376a << 2) + 0xff000000)
+#define DI_HSC_INI_PAT_CTRL ((0x376b << 2) + 0xff000000)
+#define DI_SC_GCLK_CTRL ((0x376c << 2) + 0xff000000)
+#define DI_SC_HOLD_LINE ((0x376d << 2) + 0xff000000)
+#define DI_HDR_IN_HSIZE ((0x376e << 2) + 0xff000000)
+#define DI_HDR_IN_VSIZE ((0x376f << 2) + 0xff000000)
+#define DI_HDR_OFFSET 0x70
+#define DI_HDR2_CTRL ((0x3770 << 2) + 0xff000000)
+#define DI_HDR2_CLK_GATE ((0x3771 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF00_01 ((0x3772 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF02_10 ((0x3773 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF11_12 ((0x3774 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF20_21 ((0x3775 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF22 ((0x3776 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF30_31 ((0x3777 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF32_40 ((0x3778 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_COEF41_42 ((0x3779 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_OFFSET0_1 ((0x377a << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_OFFSET2 ((0x377b << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x377c << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_PRE_OFFSET2 ((0x377d << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF00_01 ((0x377e << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF02_10 ((0x377f << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF11_12 ((0x3780 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF20_21 ((0x3781 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF22 ((0x3782 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF30_31 ((0x3783 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF32_40 ((0x3784 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_COEF41_42 ((0x3785 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_OFFSET0_1 ((0x3786 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_OFFSET2 ((0x3787 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x3788 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_PRE_OFFSET2 ((0x3789 << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_CLIP ((0x378a << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_CLIP ((0x378b << 2) + 0xff000000)
+#define DI_HDR2_CGAIN_OFFT ((0x378c << 2) + 0xff000000)
+#define DI_EOTF_LUT_ADDR_PORT ((0x378e << 2) + 0xff000000)
+#define DI_EOTF_LUT_DATA_PORT ((0x378f << 2) + 0xff000000)
+#define DI_OETF_LUT_ADDR_PORT ((0x3790 << 2) + 0xff000000)
+#define DI_OETF_LUT_DATA_PORT ((0x3791 << 2) + 0xff000000)
+#define DI_CGAIN_LUT_ADDR_PORT ((0x3792 << 2) + 0xff000000)
+#define DI_CGAIN_LUT_DATA_PORT ((0x3793 << 2) + 0xff000000)
+#define DI_HDR2_CGAIN_COEF0 ((0x3794 << 2) + 0xff000000)
+#define DI_HDR2_CGAIN_COEF1 ((0x3795 << 2) + 0xff000000)
+#define DI_OGAIN_LUT_ADDR_PORT ((0x3796 << 2) + 0xff000000)
+#define DI_OGAIN_LUT_DATA_PORT ((0x3797 << 2) + 0xff000000)
+#define DI_HDR2_ADPS_CTRL ((0x3798 << 2) + 0xff000000)
+#define DI_HDR2_ADPS_ALPHA0 ((0x3799 << 2) + 0xff000000)
+#define DI_HDR2_ADPS_ALPHA1 ((0x379a << 2) + 0xff000000)
+#define DI_HDR2_ADPS_BETA0 ((0x379b << 2) + 0xff000000)
+#define DI_HDR2_ADPS_BETA1 ((0x379c << 2) + 0xff000000)
+#define DI_HDR2_ADPS_BETA2 ((0x379d << 2) + 0xff000000)
+#define DI_HDR2_ADPS_COEF0 ((0x379e << 2) + 0xff000000)
+#define DI_HDR2_ADPS_COEF1 ((0x379f << 2) + 0xff000000)
+#define DI_HDR2_GMUT_CTRL ((0x37a0 << 2) + 0xff000000)
+#define DI_HDR2_GMUT_COEF0 ((0x37a1 << 2) + 0xff000000)
+#define DI_HDR2_GMUT_COEF1 ((0x37a2 << 2) + 0xff000000)
+#define DI_HDR2_GMUT_COEF2 ((0x37a3 << 2) + 0xff000000)
+#define DI_HDR2_GMUT_COEF3 ((0x37a4 << 2) + 0xff000000)
+#define DI_HDR2_GMUT_COEF4 ((0x37a5 << 2) + 0xff000000)
+#define DI_HDR2_PIPE_CTRL1 ((0x37a6 << 2) + 0xff000000)
+#define DI_HDR2_PIPE_CTRL2 ((0x37a7 << 2) + 0xff000000)
+#define DI_HDR2_PIPE_CTRL3 ((0x37a8 << 2) + 0xff000000)
+#define DI_HDR2_PROC_WIN1 ((0x37a9 << 2) + 0xff000000)
+#define DI_HDR2_PROC_WIN2 ((0x37aa << 2) + 0xff000000)
+#define DI_HDR2_MATRIXI_EN_CTRL ((0x37ab << 2) + 0xff000000)
+#define DI_HDR2_MATRIXO_EN_CTRL ((0x37ac << 2) + 0xff000000)
+#define DI_HDR2_HIST_CTRL ((0x37ad << 2) + 0xff000000)
+#define DI_HDR2_HIST_H_START_END ((0x37ae << 2) + 0xff000000)
+#define DI_HDR2_HIST_V_START_END ((0x37af << 2) + 0xff000000)
+#define DI_HDR2_HIST_RD ((0x378d << 2) + 0xff000000)
+#define DI_VIU_HSC_WIDTHM1 ((0x37b0 << 2) + 0xff000000)
+#define DI_VIU_HSC_PHASE_STEP ((0x37b1 << 2) + 0xff000000)
+#define DI_VIU_HSC_CTRL ((0x37b2 << 2) + 0xff000000)
+#define DI_VIU_HSC_PHASE_CTRL ((0x37b3 << 2) + 0xff000000)
+#define DI_VIU_HSC_COEF ((0x37b4 << 2) + 0xff000000)
+#define DI_VIU_HSC_COEF_IDX ((0x37b5 << 2) + 0xff000000)
+#define DI_SC_PREHSC_COEF ((0x37b9 << 2) + 0xff000000)
+#define DI_SC_PRE_SCALE_CTRL ((0x37ba << 2) + 0xff000000)
+#define DI_SC_PREVSC_COEF ((0x37bb << 2) + 0xff000000)
+#define DI_SC_PREHSC_COEF1 ((0x37bc << 2) + 0xff000000)
+#define DI_DITH_CTRL ((0x3744 << 2) + 0xff000000)
+#define DI_DITH_LUT_1 ((0x3745 << 2) + 0xff000000)
+#define DI_DITH_LUT_2 ((0x3746 << 2) + 0xff000000)
+#define DI_DITH_LUT_3 ((0x3747 << 2) + 0xff000000)
+#define DI_DITH_LUT_4 ((0x3748 << 2) + 0xff000000)
+#define DI_DITH_LUT_5 ((0x3749 << 2) + 0xff000000)
+#define DI_DITH_LUT_6 ((0x374a << 2) + 0xff000000)
+#define DI_DITH_LUT_7 ((0x374b << 2) + 0xff000000)
+#define DI_DITH_LUT_8 ((0x374c << 2) + 0xff000000)
+#define DI_DITH_LUT_9 ((0x374d << 2) + 0xff000000)
+#define DI_DITH_LUT_10 ((0x37b6 << 2) + 0xff000000)
+#define DI_DITH_LUT_11 ((0x37b7 << 2) + 0xff000000)
+#define DI_DITH_LUT_12 ((0x37b8 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: di_scale_regs.h
+//
+//0x29-0x2f 0x34-0x37 0xc0~0xff
+//
+// Reading file: di_arb_sub_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DI_SUB_RDARB_MODE ((0x37c0 << 2) + 0xff000000)
+#define DI_SUB_RDARB_REQEN_SLV ((0x37c1 << 2) + 0xff000000)
+#define DI_SUB_RDARB_WEIGH0_SLV ((0x37c2 << 2) + 0xff000000)
+#define DI_SUB_RDARB_WEIGH1_SLV ((0x37c3 << 2) + 0xff000000)
+#define DI_SUB_RDARB_UGT ((0x37c4 << 2) + 0xff000000)
+#define DI_SUB_RDARB_LIMT0 ((0x37c5 << 2) + 0xff000000)
+#define DI_SUB_WRARB_MODE ((0x37c6 << 2) + 0xff000000)
+#define DI_SUB_WRARB_REQEN_SLV ((0x37c7 << 2) + 0xff000000)
+#define DI_SUB_WRARB_WEIGH0_SLV ((0x37c8 << 2) + 0xff000000)
+#define DI_SUB_WRARB_WEIGH1_SLV ((0x37c9 << 2) + 0xff000000)
+#define DI_SUB_WRARB_UGT ((0x37ca << 2) + 0xff000000)
+#define DI_SUB_RDWR_ARB_STATUS ((0x37cb << 2) + 0xff000000)
+#define DI_SUB_ARB_DBG_CTRL ((0x37cc << 2) + 0xff000000)
+#define DI_SUB_ARB_DBG_STAT ((0x37cd << 2) + 0xff000000)
+#define CONTRD_CTRL1 ((0x37d0 << 2) + 0xff000000)
+#define CONTRD_CTRL2 ((0x37d1 << 2) + 0xff000000)
+#define CONTRD_SCOPE_X ((0x37d2 << 2) + 0xff000000)
+#define CONTRD_SCOPE_Y ((0x37d3 << 2) + 0xff000000)
+#define CONTRD_RO_STAT ((0x37d4 << 2) + 0xff000000)
+#define CONT2RD_CTRL1 ((0x37d5 << 2) + 0xff000000)
+#define CONT2RD_CTRL2 ((0x37d6 << 2) + 0xff000000)
+#define CONT2RD_SCOPE_X ((0x37d7 << 2) + 0xff000000)
+#define CONT2RD_SCOPE_Y ((0x37d8 << 2) + 0xff000000)
+#define CONT2RD_RO_STAT ((0x37d9 << 2) + 0xff000000)
+#define MTNRD_CTRL1 ((0x37da << 2) + 0xff000000)
+#define MTNRD_CTRL2 ((0x37db << 2) + 0xff000000)
+#define MTNRD_SCOPE_X ((0x37dc << 2) + 0xff000000)
+#define MTNRD_SCOPE_Y ((0x37dd << 2) + 0xff000000)
+#define MTNRD_RO_STAT ((0x37de << 2) + 0xff000000)
+#define MCVECRD_CTRL1 ((0x37df << 2) + 0xff000000)
+#define MCVECRD_CTRL2 ((0x37e0 << 2) + 0xff000000)
+#define MCVECRD_SCOPE_X ((0x37e1 << 2) + 0xff000000)
+#define MCVECRD_SCOPE_Y ((0x37e2 << 2) + 0xff000000)
+#define MCVECRD_RO_STAT ((0x37e3 << 2) + 0xff000000)
+#define MCINFRD_CTRL1 ((0x37e4 << 2) + 0xff000000)
+#define MCINFRD_CTRL2 ((0x37e5 << 2) + 0xff000000)
+#define MCINFRD_SCOPE_X ((0x37e6 << 2) + 0xff000000)
+#define MCINFRD_SCOPE_Y ((0x37e7 << 2) + 0xff000000)
+#define MCINFRD_RO_STAT ((0x37e8 << 2) + 0xff000000)
+#define CONTWR_X ((0x37e9 << 2) + 0xff000000)
+#define CONTWR_Y ((0x37ea << 2) + 0xff000000)
+#define CONTWR_CTRL ((0x37eb << 2) + 0xff000000)
+#define CONTWR_CAN_SIZE ((0x37ec << 2) + 0xff000000)
+#define MTNWR_X ((0x37ed << 2) + 0xff000000)
+#define MTNWR_Y ((0x37ee << 2) + 0xff000000)
+#define MTNWR_CTRL ((0x37ef << 2) + 0xff000000)
+#define MTNWR_CAN_SIZE ((0x37f0 << 2) + 0xff000000)
+#define MCVECWR_X ((0x37f1 << 2) + 0xff000000)
+#define MCVECWR_Y ((0x37f2 << 2) + 0xff000000)
+#define MCVECWR_CTRL ((0x37f3 << 2) + 0xff000000)
+#define MCVECWR_CAN_SIZE ((0x37f4 << 2) + 0xff000000)
+#define MCINFWR_X ((0x37f5 << 2) + 0xff000000)
+#define MCINFWR_Y ((0x37f6 << 2) + 0xff000000)
+#define MCINFWR_CTRL ((0x37f7 << 2) + 0xff000000)
+#define MCINFWR_CAN_SIZE ((0x37f8 << 2) + 0xff000000)
+#define NRDSWR_X ((0x37f9 << 2) + 0xff000000)
+#define NRDSWR_Y ((0x37fa << 2) + 0xff000000)
+#define NRDSWR_CTRL ((0x37fb << 2) + 0xff000000)
+#define NRDSWR_CAN_SIZE ((0x37fc << 2) + 0xff000000)
+#define CONTRD_BADDR ((0x3729 << 2) + 0xff000000)
+#define CONT2RD_BADDR ((0x372a << 2) + 0xff000000)
+#define MTNRD_BADDR ((0x372b << 2) + 0xff000000)
+#define MCVECRD_BADDR ((0x372c << 2) + 0xff000000)
+#define MCINFRD_BADDR ((0x372d << 2) + 0xff000000)
+#define CONTWR_BADDR ((0x3734 << 2) + 0xff000000)
+#define CONTWR_STRIDE ((0x3735 << 2) + 0xff000000)
+#define MTNWR_BADDR ((0x3736 << 2) + 0xff000000)
+#define MTNWR_STRIDE ((0x3737 << 2) + 0xff000000)
+#define MCVECWR_BADDR ((0x372e << 2) + 0xff000000)
+#define MCVECWR_STRIDE ((0x372f << 2) + 0xff000000)
+#define MCINFWR_BADDR ((0x37ce << 2) + 0xff000000)
+#define MCINFWR_STRIDE ((0x37cf << 2) + 0xff000000)
+#define NRDSWR_BADDR ((0x37fd << 2) + 0xff000000)
+#define NRDSWR_STRIDE ((0x37fe << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: di_arb_sub_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_madc_regs.h
+//
+//===========================================================================
+//===========================================================================
+//
+// Reading file: vpp_hdr2_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: VPP_HDR2_VCBUS_BASE = 0x38
+// -----------------------------------------------
+#define VD1_HDR2_OFFSET 0x00
+#define VD2_HDR2_OFFSET 0x50
+#define OSD1_HDR2_OFFSET 0xa0
+//`include "hdr2_top_reg.h"
+//vd1 0x00 - -x35
+#define VD1_HDR2_CTRL ((0x3800 << 2) + 0xff000000)
+#define VD1_HDR2_CLK_GATE ((0x3801 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF00_01 ((0x3802 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF02_10 ((0x3803 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF11_12 ((0x3804 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF20_21 ((0x3805 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF22 ((0x3806 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF30_31 ((0x3807 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF32_40 ((0x3808 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_COEF41_42 ((0x3809 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_OFFSET0_1 ((0x380a << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_OFFSET2 ((0x380b << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x380c << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_PRE_OFFSET2 ((0x380d << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF00_01 ((0x380e << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF02_10 ((0x380f << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF11_12 ((0x3810 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF20_21 ((0x3811 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF22 ((0x3812 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF30_31 ((0x3813 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF32_40 ((0x3814 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_COEF41_42 ((0x3815 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_OFFSET0_1 ((0x3816 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_OFFSET2 ((0x3817 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x3818 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_PRE_OFFSET2 ((0x3819 << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_CLIP ((0x381a << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_CLIP ((0x381b << 2) + 0xff000000)
+#define VD1_HDR2_CGAIN_OFFT ((0x381c << 2) + 0xff000000)
+#define VD1_EOTF_LUT_ADDR_PORT ((0x381e << 2) + 0xff000000)
+#define VD1_EOTF_LUT_DATA_PORT ((0x381f << 2) + 0xff000000)
+#define VD1_OETF_LUT_ADDR_PORT ((0x3820 << 2) + 0xff000000)
+#define VD1_OETF_LUT_DATA_PORT ((0x3821 << 2) + 0xff000000)
+#define VD1_CGAIN_LUT_ADDR_PORT ((0x3822 << 2) + 0xff000000)
+#define VD1_CGAIN_LUT_DATA_PORT ((0x3823 << 2) + 0xff000000)
+#define VD1_HDR2_CGAIN_COEF0 ((0x3824 << 2) + 0xff000000)
+#define VD1_HDR2_CGAIN_COEF1 ((0x3825 << 2) + 0xff000000)
+#define VD1_OGAIN_LUT_ADDR_PORT ((0x3826 << 2) + 0xff000000)
+#define VD1_OGAIN_LUT_DATA_PORT ((0x3827 << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_CTRL ((0x3828 << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_ALPHA0 ((0x3829 << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_ALPHA1 ((0x382a << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_BETA0 ((0x382b << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_BETA1 ((0x382c << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_BETA2 ((0x382d << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_COEF0 ((0x382e << 2) + 0xff000000)
+#define VD1_HDR2_ADPS_COEF1 ((0x382f << 2) + 0xff000000)
+#define VD1_HDR2_GMUT_CTRL ((0x3830 << 2) + 0xff000000)
+#define VD1_HDR2_GMUT_COEF0 ((0x3831 << 2) + 0xff000000)
+#define VD1_HDR2_GMUT_COEF1 ((0x3832 << 2) + 0xff000000)
+#define VD1_HDR2_GMUT_COEF2 ((0x3833 << 2) + 0xff000000)
+#define VD1_HDR2_GMUT_COEF3 ((0x3834 << 2) + 0xff000000)
+#define VD1_HDR2_GMUT_COEF4 ((0x3835 << 2) + 0xff000000)
+#define VD1_HDR2_PIPE_CTRL1 ((0x3836 << 2) + 0xff000000)
+#define VD1_HDR2_PIPE_CTRL2 ((0x3837 << 2) + 0xff000000)
+#define VD1_HDR2_PIPE_CTRL3 ((0x3838 << 2) + 0xff000000)
+#define VD1_HDR2_PROC_WIN1 ((0x3839 << 2) + 0xff000000)
+#define VD1_HDR2_PROC_WIN2 ((0x383a << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXI_EN_CTRL ((0x383b << 2) + 0xff000000)
+#define VD1_HDR2_MATRIXO_EN_CTRL ((0x383c << 2) + 0xff000000)
+#define VD1_HDR2_HIST_CTRL ((0x383d << 2) + 0xff000000)
+#define VD1_HDR2_HIST_H_START_END ((0x383e << 2) + 0xff000000)
+#define VD1_HDR2_HIST_V_START_END ((0x383f << 2) + 0xff000000)
+#define VD1_HDR2_HIST_RD ((0x381d << 2) + 0xff000000)
+//vd2 0x50 - 0x85
+#define VD2_HDR2_CTRL ((0x3850 << 2) + 0xff000000)
+#define VD2_HDR2_CLK_GATE ((0x3851 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF00_01 ((0x3852 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF02_10 ((0x3853 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF11_12 ((0x3854 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF20_21 ((0x3855 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF22 ((0x3856 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF30_31 ((0x3857 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF32_40 ((0x3858 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_COEF41_42 ((0x3859 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_OFFSET0_1 ((0x385a << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_OFFSET2 ((0x385b << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x385c << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_PRE_OFFSET2 ((0x385d << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF00_01 ((0x385e << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF02_10 ((0x385f << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF11_12 ((0x3860 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF20_21 ((0x3861 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF22 ((0x3862 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF30_31 ((0x3863 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF32_40 ((0x3864 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_COEF41_42 ((0x3865 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_OFFSET0_1 ((0x3866 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_OFFSET2 ((0x3867 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x3868 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_PRE_OFFSET2 ((0x3869 << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_CLIP ((0x386a << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_CLIP ((0x386b << 2) + 0xff000000)
+#define VD2_HDR2_CGAIN_OFFT ((0x386c << 2) + 0xff000000)
+#define VD2_EOTF_LUT_ADDR_PORT ((0x386e << 2) + 0xff000000)
+#define VD2_EOTF_LUT_DATA_PORT ((0x386f << 2) + 0xff000000)
+#define VD2_OETF_LUT_ADDR_PORT ((0x3870 << 2) + 0xff000000)
+#define VD2_OETF_LUT_DATA_PORT ((0x3871 << 2) + 0xff000000)
+#define VD2_CGAIN_LUT_ADDR_PORT ((0x3872 << 2) + 0xff000000)
+#define VD2_CGAIN_LUT_DATA_PORT ((0x3873 << 2) + 0xff000000)
+#define VD2_HDR2_CGAIN_COEF0 ((0x3874 << 2) + 0xff000000)
+#define VD2_HDR2_CGAIN_COEF1 ((0x3875 << 2) + 0xff000000)
+#define VD2_OGAIN_LUT_ADDR_PORT ((0x3876 << 2) + 0xff000000)
+#define VD2_OGAIN_LUT_DATA_PORT ((0x3877 << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_CTRL ((0x3878 << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_ALPHA0 ((0x3879 << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_ALPHA1 ((0x387a << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_BETA0 ((0x387b << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_BETA1 ((0x387c << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_BETA2 ((0x387d << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_COEF0 ((0x387e << 2) + 0xff000000)
+#define VD2_HDR2_ADPS_COEF1 ((0x387f << 2) + 0xff000000)
+#define VD2_HDR2_GMUT_CTRL ((0x3880 << 2) + 0xff000000)
+#define VD2_HDR2_GMUT_COEF0 ((0x3881 << 2) + 0xff000000)
+#define VD2_HDR2_GMUT_COEF1 ((0x3882 << 2) + 0xff000000)
+#define VD2_HDR2_GMUT_COEF2 ((0x3883 << 2) + 0xff000000)
+#define VD2_HDR2_GMUT_COEF3 ((0x3884 << 2) + 0xff000000)
+#define VD2_HDR2_GMUT_COEF4 ((0x3885 << 2) + 0xff000000)
+#define VD2_HDR2_PIPE_CTRL1 ((0x3886 << 2) + 0xff000000)
+#define VD2_HDR2_PIPE_CTRL2 ((0x3887 << 2) + 0xff000000)
+#define VD2_HDR2_PIPE_CTRL3 ((0x3888 << 2) + 0xff000000)
+#define VD2_HDR2_PROC_WIN1 ((0x3889 << 2) + 0xff000000)
+#define VD2_HDR2_PROC_WIN2 ((0x388a << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXI_EN_CTRL ((0x388b << 2) + 0xff000000)
+#define VD2_HDR2_MATRIXO_EN_CTRL ((0x388c << 2) + 0xff000000)
+#define VD2_HDR2_HIST_CTRL ((0x388d << 2) + 0xff000000)
+#define VD2_HDR2_HIST_H_START_END ((0x388e << 2) + 0xff000000)
+#define VD2_HDR2_HIST_V_START_END ((0x388f << 2) + 0xff000000)
+#define VD2_HDR2_HIST_RD ((0x386d << 2) + 0xff000000)
+// vd3 to do, use correct register addrss
+#define VD3_HDR2_CTRL ((0x5930 << 2) + 0xff000000)
+#define VD3_HDR2_CLK_GATE ((0x5931 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_COEF00_01 ((0x5932 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_COEF02_10 ((0x5933 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_COEF11_12 ((0x5934 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_COEF20_21 ((0x5935 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_COEF22 ((0x5936 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_COEF30_31 ((0x5937 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_COEF32_40 ((0x5938 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_COEF41_42 ((0x5939 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_OFFSET0_1 ((0x593a << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_OFFSET2 ((0x593b << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x593c << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_PRE_OFFSET2 ((0x593d << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_COEF00_01 ((0x593e << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_COEF02_10 ((0x593f << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_COEF11_12 ((0x5940 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_COEF20_21 ((0x5941 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_COEF22 ((0x5942 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_COEF30_31 ((0x5943 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_COEF32_40 ((0x5944 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_COEF41_42 ((0x5945 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_OFFSET0_1 ((0x5946 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_OFFSET2 ((0x5947 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x5948 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_PRE_OFFSET2 ((0x5949 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_CLIP ((0x594a << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_CLIP ((0x594b << 2) + 0xff000000)
+#define VD3_HDR2_CGAIN_OFFT ((0x594c << 2) + 0xff000000)
+#define VD3_HDR2_HIST_RD_2 ((0x594d << 2) + 0xff000000)
+#define VD3_EOTF_LUT_ADDR_PORT ((0x594e << 2) + 0xff000000)
+#define VD3_EOTF_LUT_DATA_PORT ((0x594f << 2) + 0xff000000)
+#define VD3_OETF_LUT_ADDR_PORT ((0x5950 << 2) + 0xff000000)
+#define VD3_OETF_LUT_DATA_PORT ((0x5951 << 2) + 0xff000000)
+#define VD3_CGAIN_LUT_ADDR_PORT ((0x5952 << 2) + 0xff000000)
+#define VD3_CGAIN_LUT_DATA_PORT ((0x5953 << 2) + 0xff000000)
+#define VD3_HDR2_CGAIN_COEF0 ((0x5954 << 2) + 0xff000000)
+#define VD3_HDR2_CGAIN_COEF1 ((0x5955 << 2) + 0xff000000)
+#define VD3_OGAIN_LUT_ADDR_PORT ((0x5956 << 2) + 0xff000000)
+#define VD3_OGAIN_LUT_DATA_PORT ((0x5957 << 2) + 0xff000000)
+#define VD3_HDR2_ADPS_CTRL ((0x5958 << 2) + 0xff000000)
+#define VD3_HDR2_ADPS_ALPHA0 ((0x5959 << 2) + 0xff000000)
+#define VD3_HDR2_ADPS_ALPHA1 ((0x595a << 2) + 0xff000000)
+#define VD3_HDR2_ADPS_BETA0 ((0x595b << 2) + 0xff000000)
+#define VD3_HDR2_ADPS_BETA1 ((0x595c << 2) + 0xff000000)
+#define VD3_HDR2_ADPS_BETA2 ((0x595d << 2) + 0xff000000)
+#define VD3_HDR2_ADPS_COEF0 ((0x595e << 2) + 0xff000000)
+#define VD3_HDR2_ADPS_COEF1 ((0x595f << 2) + 0xff000000)
+#define VD3_HDR2_GMUT_CTRL ((0x5960 << 2) + 0xff000000)
+#define VD3_HDR2_GMUT_COEF0 ((0x5961 << 2) + 0xff000000)
+#define VD3_HDR2_GMUT_COEF1 ((0x5962 << 2) + 0xff000000)
+#define VD3_HDR2_GMUT_COEF2 ((0x5963 << 2) + 0xff000000)
+#define VD3_HDR2_GMUT_COEF3 ((0x5964 << 2) + 0xff000000)
+#define VD3_HDR2_GMUT_COEF4 ((0x5965 << 2) + 0xff000000)
+#define VD3_HDR2_PIPE_CTRL1 ((0x5966 << 2) + 0xff000000)
+#define VD3_HDR2_PIPE_CTRL2 ((0x5967 << 2) + 0xff000000)
+#define VD3_HDR2_PIPE_CTRL3 ((0x5968 << 2) + 0xff000000)
+#define VD3_HDR2_PROC_WIN1 ((0x5969 << 2) + 0xff000000)
+#define VD3_HDR2_PROC_WIN2 ((0x596a << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_EN_CTRL ((0x596b << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_EN_CTRL ((0x596c << 2) + 0xff000000)
+#define VD3_HDR2_HIST_CTRL ((0x596d << 2) + 0xff000000)
+#define VD3_HDR2_HIST_H_START_END ((0x596e << 2) + 0xff000000)
+#define VD3_HDR2_HIST_V_START_END ((0x596f << 2) + 0xff000000)
+
+// end of vd3 part for t7
+
+//osd1 0xa0 - 0xd5
+#define OSD1_HDR2_CTRL ((0x38a0 << 2) + 0xff000000)
+#define OSD1_HDR2_CLK_GATE ((0x38a1 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF00_01 ((0x38a2 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF02_10 ((0x38a3 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF11_12 ((0x38a4 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF20_21 ((0x38a5 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF22 ((0x38a6 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF30_31 ((0x38a7 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF32_40 ((0x38a8 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_COEF41_42 ((0x38a9 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_OFFSET0_1 ((0x38aa << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_OFFSET2 ((0x38ab << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x38ac << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_PRE_OFFSET2 ((0x38ad << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF00_01 ((0x38ae << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF02_10 ((0x38af << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF11_12 ((0x38b0 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF20_21 ((0x38b1 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF22 ((0x38b2 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF30_31 ((0x38b3 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF32_40 ((0x38b4 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_COEF41_42 ((0x38b5 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_OFFSET0_1 ((0x38b6 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_OFFSET2 ((0x38b7 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x38b8 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_PRE_OFFSET2 ((0x38b9 << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_CLIP ((0x38ba << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_CLIP ((0x38bb << 2) + 0xff000000)
+#define OSD1_HDR2_CGAIN_OFFT ((0x38bc << 2) + 0xff000000)
+#define OSD1_EOTF_LUT_ADDR_PORT ((0x38be << 2) + 0xff000000)
+#define OSD1_EOTF_LUT_DATA_PORT ((0x38bf << 2) + 0xff000000)
+#define OSD1_OETF_LUT_ADDR_PORT ((0x38c0 << 2) + 0xff000000)
+#define OSD1_OETF_LUT_DATA_PORT ((0x38c1 << 2) + 0xff000000)
+#define OSD1_CGAIN_LUT_ADDR_PORT ((0x38c2 << 2) + 0xff000000)
+#define OSD1_CGAIN_LUT_DATA_PORT ((0x38c3 << 2) + 0xff000000)
+#define OSD1_HDR2_CGAIN_COEF0 ((0x38c4 << 2) + 0xff000000)
+#define OSD1_HDR2_CGAIN_COEF1 ((0x38c5 << 2) + 0xff000000)
+#define OSD1_OGAIN_LUT_ADDR_PORT ((0x38c6 << 2) + 0xff000000)
+#define OSD1_OGAIN_LUT_DATA_PORT ((0x38c7 << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_CTRL ((0x38c8 << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_ALPHA0 ((0x38c9 << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_ALPHA1 ((0x38ca << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_BETA0 ((0x38cb << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_BETA1 ((0x38cc << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_BETA2 ((0x38cd << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_COEF0 ((0x38ce << 2) + 0xff000000)
+#define OSD1_HDR2_ADPS_COEF1 ((0x38cf << 2) + 0xff000000)
+#define OSD1_HDR2_GMUT_CTRL ((0x38d0 << 2) + 0xff000000)
+#define OSD1_HDR2_GMUT_COEF0 ((0x38d1 << 2) + 0xff000000)
+#define OSD1_HDR2_GMUT_COEF1 ((0x38d2 << 2) + 0xff000000)
+#define OSD1_HDR2_GMUT_COEF2 ((0x38d3 << 2) + 0xff000000)
+#define OSD1_HDR2_GMUT_COEF3 ((0x38d4 << 2) + 0xff000000)
+#define OSD1_HDR2_GMUT_COEF4 ((0x38d5 << 2) + 0xff000000)
+#define OSD1_HDR2_PIPE_CTRL1 ((0x38d6 << 2) + 0xff000000)
+#define OSD1_HDR2_PIPE_CTRL2 ((0x38d7 << 2) + 0xff000000)
+#define OSD1_HDR2_PIPE_CTRL3 ((0x38d8 << 2) + 0xff000000)
+#define OSD1_HDR2_PROC_WIN1 ((0x38d9 << 2) + 0xff000000)
+#define OSD1_HDR2_PROC_WIN2 ((0x38da << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXI_EN_CTRL ((0x38db << 2) + 0xff000000)
+#define OSD1_HDR2_MATRIXO_EN_CTRL ((0x38dc << 2) + 0xff000000)
+#define OSD1_HDR2_HIST_CTRL ((0x38dd << 2) + 0xff000000)
+#define OSD1_HDR2_HIST_H_START_END ((0x38de << 2) + 0xff000000)
+#define OSD1_HDR2_HIST_V_START_END ((0x38df << 2) + 0xff000000)
+#define OSD1_HDR2_HIST_RD ((0x38bd << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_hdr2_regs.h
+//
+//===========================================================================
+//===========================================================================
+//
+// Reading file: vpp_misc_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// -----------------------------------------------
+// REG_BASE: VPP_MISC_VCBUS_BASE = 0x39
+// -----------------------------------------------
+//0x01-0a
+//
+// Reading file: vpp_vd2_mat_3x3_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VPP_VD2_MATRIX_COEF00_01 ((0x3901 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_COEF02_10 ((0x3902 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_COEF11_12 ((0x3903 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_COEF20_21 ((0x3904 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_COEF22 ((0x3905 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_OFFSET0_1 ((0x3906 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_OFFSET2 ((0x3907 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_CLIP ((0x3908 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_PRE_OFFSET0_1 ((0x3909 << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_PRE_OFFSET2 ((0x390a << 2) + 0xff000000)
+#define VPP_VD2_MATRIX_EN_CTRL ((0x390b << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_vd2_mat_3x3_regs.h
+//
+//0x10-1c
+//
+// Reading file: vpp_osd1_mat_3x5_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VPP_OSD1_MATRIX_COEF00_01 ((0x3910 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef00 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef01 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF02_10 ((0x3911 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef02 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef10 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF11_12 ((0x3912 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef11 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef12 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF20_21 ((0x3913 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef20 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef21 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF22 ((0x3914 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 coef22 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF13_14 ((0x3915 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef13 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef14 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF23_24 ((0x3916 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef23 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef24 //signed , default = 0
+#define VPP_OSD1_MATRIX_COEF15_25 ((0x3917 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef15 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef25 //signed , default = 0
+#define VPP_OSD1_MATRIX_CLIP ((0x3918 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:8 comp_thrd0 // signed ,default == 0, mat clip enable
+//Bit 7:5 conv_rs // unsigned ,default == 0, mat rs
+//Bit 4:3 clmod // unsigned ,default == 0, mat clmod
+#define VPP_OSD1_MATRIX_OFFSET0_1 ((0x3919 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 offset0 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 offset1 //signed , default = 0
+#define VPP_OSD1_MATRIX_OFFSET2 ((0x391a << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 offset2 //signed , default = 0
+#define VPP_OSD1_MATRIX_PRE_OFFSET0_1 ((0x391b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 pre_offset0 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 pre_offset1 //signed , default = 0
+#define VPP_OSD1_MATRIX_PRE_OFFSET2 ((0x391c << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 pre_offset2 //signed , default = 0
+#define VPP_OSD1_MATRIX_EN_CTRL ((0x391d << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_osd1_mat_3x5_regs.h
+//
+//0x20-2c
+//
+// Reading file: vpp_osd2_mat_3x5_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VPP_OSD2_MATRIX_COEF00_01 ((0x3920 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef00 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef01 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF02_10 ((0x3921 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef02 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef10 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF11_12 ((0x3922 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef11 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef12 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF20_21 ((0x3923 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef20 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef21 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF22 ((0x3924 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 coef22 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF13_14 ((0x3925 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef13 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef14 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF23_24 ((0x3926 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef23 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef24 //signed , default = 0
+#define VPP_OSD2_MATRIX_COEF15_25 ((0x3927 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef15 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef25 //signed , default = 0
+#define VPP_OSD2_MATRIX_CLIP ((0x3928 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:8 comp_thrd0 // signed ,default == 0, mat clip enable
+//Bit 7:5 conv_rs // unsigned ,default == 0, mat rs
+//Bit 4:3 clmod // unsigned ,default == 0, mat clmod
+#define VPP_OSD2_MATRIX_OFFSET0_1 ((0x3929 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 offset0 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 offset1 //signed , default = 0
+#define VPP_OSD2_MATRIX_OFFSET2 ((0x392a << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 offset2 //signed , default = 0
+#define VPP_OSD2_MATRIX_PRE_OFFSET0_1 ((0x392b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 pre_offset0 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 pre_offset1 //signed , default = 0
+#define VPP_OSD2_MATRIX_PRE_OFFSET2 ((0x392c << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 pre_offset2 //signed , default = 0
+#define VPP_OSD2_MATRIX_EN_CTRL ((0x392d << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_osd2_mat_3x5_regs.h
+//
+//0x33-0x4f
+//
+// Reading file: vpp_vd2_scale_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VD2_SCALE_COEF_IDX ((0x3933 << 2) + 0xff000000)
+#define VD2_SCALE_COEF ((0x3934 << 2) + 0xff000000)
+#define VD2_VSC_REGION12_STARTP ((0x3935 << 2) + 0xff000000)
+#define VD2_VSC_REGION34_STARTP ((0x3936 << 2) + 0xff000000)
+#define VD2_VSC_REGION4_ENDP ((0x3937 << 2) + 0xff000000)
+#define VD2_VSC_START_PHASE_STEP ((0x3938 << 2) + 0xff000000)
+#define VD2_VSC_REGION0_PHASE_SLOPE ((0x3939 << 2) + 0xff000000)
+#define VD2_VSC_REGION1_PHASE_SLOPE ((0x393a << 2) + 0xff000000)
+#define VD2_VSC_REGION3_PHASE_SLOPE ((0x393b << 2) + 0xff000000)
+#define VD2_VSC_REGION4_PHASE_SLOPE ((0x393c << 2) + 0xff000000)
+#define VD2_VSC_PHASE_CTRL ((0x393d << 2) + 0xff000000)
+#define VD2_VSC_INI_PHASE ((0x393e << 2) + 0xff000000)
+#define VD2_HSC_REGION12_STARTP ((0x393f << 2) + 0xff000000)
+#define VD2_HSC_REGION34_STARTP ((0x3940 << 2) + 0xff000000)
+#define VD2_HSC_REGION4_ENDP ((0x3941 << 2) + 0xff000000)
+#define VD2_HSC_START_PHASE_STEP ((0x3942 << 2) + 0xff000000)
+#define VD2_HSC_REGION0_PHASE_SLOPE ((0x3943 << 2) + 0xff000000)
+#define VD2_HSC_REGION1_PHASE_SLOPE ((0x3944 << 2) + 0xff000000)
+#define VD2_HSC_REGION3_PHASE_SLOPE ((0x3945 << 2) + 0xff000000)
+#define VD2_HSC_REGION4_PHASE_SLOPE ((0x3946 << 2) + 0xff000000)
+#define VD2_HSC_PHASE_CTRL ((0x3947 << 2) + 0xff000000)
+#define VD2_SC_MISC ((0x3948 << 2) + 0xff000000)
+#define VD2_SCO_FIFO_CTRL ((0x3949 << 2) + 0xff000000)
+#define VD2_HSC_PHASE_CTRL1 ((0x394a << 2) + 0xff000000)
+#define VD2_HSC_INI_PAT_CTRL ((0x394b << 2) + 0xff000000)
+#define VD2_SC_GCLK_CTRL ((0x394c << 2) + 0xff000000)
+#define VD2_PREHSC_COEF ((0x394d << 2) + 0xff000000)
+#define VD2_PRE_SCALE_CTRL ((0x394e << 2) + 0xff000000)
+#define VD2_PREVSC_COEF ((0x394f << 2) + 0xff000000)
+#define VD2_PREHSC_COEF1 ((0x3950 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_vd2_scale_regs.h
+//
+#define VPP_PRE_BLEND_CTRL ((0x3960 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:20 hold_lines //unsigned , default = 8'h4
+//Bit 19:2 reserved
+//Bit 1 :0 gclk_ctrl //unsigned , default = 2'd0
+#define VPP_PRE_BLEND_BLEND_DUMMY_DATA ((0x3961 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 blend0_dummy_data_y //unsigned , default = 8'h10
+//Bit 15:8 blend0_dummy_data_cb //unsigned , default = 8'h80
+//Bit 7:0 blend0_dummy_data_cr //unsigned , default = 8'h0
+#define VPP_PRE_BLEND_DUMMY_ALPHA ((0x3962 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 blend1_dummy_alpha //unsigned , default = 9'h0
+//Bit 15:9 reserved
+//Bit 8 :0 blend0_dummy_alpha //unsigned , default = 9'h0
+#define VPP_PRE_BLEND_RO_CURRENT_XY ((0x3963 << 2) + 0xff000000)
+//Bit 31:0 ro_blend_current_xy //unsigned , default = 32'h0
+#define VPP_PRE_BLEND_DUMMY_ALPHA1 ((0x3964 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 blend1_dummy_alpha //unsigned , default = 9'h0
+//Bit 15:9 reserved
+//Bit 8 :0 blend0_dummy_alpha //unsigned , default = 9'h0
+#define VPP_POST_BLEND_CTRL ((0x3967 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:20 hold_lines //unsigned , default = 8'h4
+//Bit 19:2 reserved
+//Bit 1 :0 gclk_ctrl //unsigned , default = 2'd0
+#define VPP_POST_BLEND_BLEND_DUMMY_DATA ((0x3968 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 blend0_dummy_data_y //unsigned , default = 8'h10
+//Bit 15:8 blend0_dummy_data_cb //unsigned , default = 8'h80
+//Bit 7:0 blend0_dummy_data_cr //unsigned , default = 8'h0
+#define VPP_POST_BLEND_DUMMY_ALPHA ((0x3969 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 blend1_dummy_alpha //unsigned , default = 9'h0
+//Bit 15:9 reserved
+//Bit 8 :0 blend0_dummy_alpha //unsigned , default = 9'h0
+#define VPP_POST_BLEND_RO_CURRENT_XY ((0x396a << 2) + 0xff000000)
+//Bit 31:0 ro_blend_current_xy //unsigned , default = 32'h0
+#define VPP_POST_BLEND_DUMMY_ALPHA1 ((0x396b << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 blend1_dummy_alpha //unsigned , default = 9'h0
+//Bit 15:9 reserved
+//Bit 8 :0 blend0_dummy_alpha //unsigned , default = 9'h0
+#define VPP_AFBC_RDARB_MODE ((0x3970 << 2) + 0xff000000)
+#define VPP_AFBC_RDARB_REQEN_SLV ((0x3971 << 2) + 0xff000000)
+#define VPP_AFBC_RDARB_WEIGH0_SLV ((0x3972 << 2) + 0xff000000)
+#define VPP_AFBC_RDWR_ARB_STATUS ((0x3973 << 2) + 0xff000000)
+#define VPP_AFBC_ARB_DBG_CTRL ((0x3974 << 2) + 0xff000000)
+#define VPP_AFBC_ARB_DBG_STAT ((0x3975 << 2) + 0xff000000)
+#define VPP_RDARB_MODE ((0x3978 << 2) + 0xff000000)
+#define VPP_RDARB_REQEN_SLV ((0x3979 << 2) + 0xff000000)
+#define VPP_RDARB_WEIGH0_SLV ((0x397a << 2) + 0xff000000)
+#define VPP_RDARB_WEIGH1_SLV ((0x397b << 2) + 0xff000000)
+#define VPP_RDWR_ARB_STATUS ((0x397c << 2) + 0xff000000)
+#define VPP_ARB_DBG_CTRL ((0x397e << 2) + 0xff000000)
+#define VPP_ARB_DBG_STAT ((0x397f << 2) + 0xff000000)
+//ox80-0x9f & 0xe0-0xef
+//
+// Reading file: vpu_primesl_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define PRIMESL_LUTC_ADDR_PORT ((0x3980 << 2) + 0xff000000)
+#define PRIMESL_LUTC_DATA_PORT ((0x3981 << 2) + 0xff000000)
+#define PRIMESL_LUTP_ADDR_PORT ((0x3982 << 2) + 0xff000000)
+#define PRIMESL_LUTP_DATA_PORT ((0x3983 << 2) + 0xff000000)
+#define PRIMESL_LUTD_ADDR_PORT ((0x3984 << 2) + 0xff000000)
+#define PRIMESL_LUTD_DATA_PORT ((0x3985 << 2) + 0xff000000)
+#define PRIMESL_CTRL0 ((0x3990 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29 legacy_mode_en // unsigned , default = 0 = 'h0
+//Bit 28 clip_en // unsigned , default = 1 = 'h0
+//Bit 27 reserved
+//Bit 26:16 inv_chroma_ratio // unsigned , default = 0 = 'h0,
+//Bit 15 reserved
+//Bit 14: 4 inv_y_ratio // unsigned , default = 0 = 'h0,
+//Bit 3 reg_gclk_ctrl // unsigned , default = 0 = 'h0,
+//Bit 2: 1 gclk_ctrl // unsigned , default = 0 = 'h0,
+//Bit 0 primesl_en // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL1 ((0x3991 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 l_headroom // unsigned , default = 0 = 'h0,
+//Bit 15:10 reserved
+//Bit 9: 0 footroom // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL2 ((0x3992 << 2) + 0xff000000)
+//Bit 31:10 reserved
+//Bit 9: 0 c_headroom // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL3 ((0x3993 << 2) + 0xff000000)
+//Bit 31:16 mub // unsigned , default = 0 = 'h0,
+//Bit 15: 0 mua // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL4 ((0x3994 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 oct_7_1 // signed , default = 0 = 'h0,
+//Bit 15:10 reserved
+//Bit 9: 0 oct_7_0 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL5 ((0x3995 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 oct_7_3 // signed , default = 0 = 'h0,
+//Bit 15:10 reserved
+//Bit 9: 0 oct_7_2 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL6 ((0x3996 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 oct_7_5 // signed , default = 0 = 'h0,
+//Bit 15:10 reserved
+//Bit 9: 0 oct_7_4 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL7 ((0x3997 << 2) + 0xff000000)
+//Bit 31:10 reserved
+//Bit 9: 0 oct_7_6 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL8 ((0x3998 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 d_lut_threshold_3_1 // unsigned , default = 0 = 'h0,
+//Bit 15:13 reserved
+//Bit 12: 0 d_lut_threshold_3_0 // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL9 ((0x3999 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12: 0 d_lut_threshold_3_2 // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL10 ((0x399a << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15:12 d_lut_step_4_3 // unsigned , default = 0 = 'h0,
+//Bit 11: 8 d_lut_step_4_2 // unsigned , default = 0 = 'h0,
+//Bit 7: 4 d_lut_step_4_1 // unsigned , default = 0 = 'h0,
+//Bit 3: 0 d_lut_step_4_0 // unsigned , default = 0 = 'h0,
+#define PRIMESL_CTRL11 ((0x399b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 rgb2yuv_9_0 // signed , default = 0 = 'h0,
+//Bit 15:13 reserved
+//Bit 12: 0 rgb2yuv_9_1 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL12 ((0x399c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 rgb2yuv_9_2 // signed , default = 0 = 'h0,
+//Bit 15:13 reserved
+//Bit 12: 0 rgb2yuv_9_3 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL13 ((0x399d << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 rgb2yuv_9_4 // signed , default = 0 = 'h0,
+//Bit 15:13 reserved
+//Bit 12: 0 rgb2yuv_9_5 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL14 ((0x399e << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 rgb2yuv_9_6 // signed , default = 0 = 'h0,
+//Bit 15:13 reserved
+//Bit 12: 0 rgb2yuv_9_7 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL15 ((0x399f << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12: 0 rgb2yuv_9_8 // signed , default = 0 = 'h0,
+#define PRIMESL_CTRL16 ((0x39e0 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30 byp_s_lut // unsigned , default = 0 = 'h0,
+//Bit 29 byp_d_lut // unsigned , default = 0 = 'h0,
+//Bit 28 byp_mat // unsigned , default = 0 = 'h0,
+//Bit 27 rgb_swap // unsigned , default = 0 = 'h0,
+//Bit 26:24 uv_shift // unsigned , default = 0 = 'h0,
+//Bit 23:22 rgb_shift // unsigned , default = 0 = 'h0,
+//Bit 21:20 rgb_clip // unsigned , default = 3 = 'h3,
+//Bit 19:18 reserved
+//Bit 17:16 rgb_rs // unsigned , default = 0 = 'h0,
+//Bit 15:14 reserved
+//Bit 13: 0 reg_s // signed , default = 1024 = 'h1024,
+#define PRIMESL_OMAT_OFFSET0 ((0x39e1 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 pre_offset0 // unsigned , default = 512 = 'h512
+//Bit 15:12 reserved
+//Bit 11: 0 pre_offset1 // unsigned , default = 512 = 'h512
+#define PRIMESL_OMAT_OFFSET1 ((0x39e2 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 pre_offset2 // unsigned , default = 512 = 'h512
+//Bit 15:12 reserved
+//Bit 11: 0 offset0 // unsigned , default = 256 = 'h256
+#define PRIMESL_OMAT_OFFSET2 ((0x39e3 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 offset1 // unsigned , default = 2048 = 'h2048
+//Bit 15:12 reserved
+//Bit 11: 0 offset2 // unsigned , default = 2048 = 'h2048
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_primesl_regs.h
+//
+//oxa0-0xaf
+//
+// Reading file: vpp_post2_mat_3x5_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VPP_POST2_MATRIX_COEF00_01 ((0x39a0 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef00 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef01 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF02_10 ((0x39a1 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef02 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef10 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF11_12 ((0x39a2 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef11 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef12 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF20_21 ((0x39a3 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef20 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef21 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF22 ((0x39a4 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 coef22 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF13_14 ((0x39a5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef13 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef14 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF23_24 ((0x39a6 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef23 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef24 //signed , default = 0
+#define VPP_POST2_MATRIX_COEF15_25 ((0x39a7 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 coef15 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 coef25 //signed , default = 0
+#define VPP_POST2_MATRIX_CLIP ((0x39a8 << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:8 comp_thrd0 // signed ,default == 0, mat clip enable
+//Bit 7:5 conv_rs // unsigned ,default == 0, mat rs
+//Bit 4:3 clmod // unsigned ,default == 0, mat clmod
+#define VPP_POST2_MATRIX_OFFSET0_1 ((0x39a9 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 offset0 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 offset1 //signed , default = 0
+#define VPP_POST2_MATRIX_OFFSET2 ((0x39aa << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 offset2 //signed , default = 0
+#define VPP_POST2_MATRIX_PRE_OFFSET0_1 ((0x39ab << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 pre_offset0 //signed , default = 0
+//Bit 15:13 reserved
+//Bit 12:0 pre_offset1 //signed , default = 0
+#define VPP_POST2_MATRIX_PRE_OFFSET2 ((0x39ac << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 pre_offset2 //signed , default = 0
+#define VPP_POST2_MATRIX_EN_CTRL ((0x39ad << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_post2_mat_3x5_regs.h
+//
+//0xb0-0xcf
+//
+// Reading file: osd_blend_reg.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VIU_OSD_BLEND_CTRL ((0x39b0 << 2) + 0xff000000)
+//Bit 31:29 hold_lines //unsigned , default = 3'h0
+//Bit 28:27 blend2_premult_en //unsigned , default = 2'h3
+//Bit 26 din0_byp_blend //unsigned , default = 1'h1
+//Bit 25 din2_osd_sel //unsigned , default = 1'h1
+//Bit 24 din3_osd_sel //unsigned , default = 1'h1
+//Bit 23:20 blend_din_en //unsigned , default = 4'h5
+//Bit 19:16 din_premult_en //unsigned , default = 4'h0
+//Bit 15:0 din_reoder_sel //unsigned , default = 16'h2341
+#define VIU_OSD_BLEND_CTRL1 ((0x39c0 << 2) + 0xff000000)
+//Bit 31:6 reserved
+//Bit 5:4 reg_alp_mapping_mode
+//Bit 2:1 reg_div_gclk_en
+//Bit 0 reg_div_alpha_en
+#define VIU_OSD_BLEND_DIN0_SCOPE_H ((0x39b1 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din0_h_end ///unsigned , default = 13'h2d0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din0_h_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN0_SCOPE_V ((0x39b2 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din0_v_end ///unsigned , default = 13'h1e0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din0_v_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN1_SCOPE_H ((0x39b3 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din1_h_end ///unsigned , default = 13'h2d0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din1_h_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN1_SCOPE_V ((0x39b4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din1_v_end ///unsigned , default = 13'h1e0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din1_v_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN2_SCOPE_H ((0x39b5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din2_h_end ///unsigned , default = 13'h2d0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din2_h_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN2_SCOPE_V ((0x39b6 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din2_v_end ///unsigned , default = 13'h1e0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din2_v_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN3_SCOPE_H ((0x39b7 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din3_h_end ///unsigned , default = 13'h2d0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din3_h_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DIN3_SCOPE_V ((0x39b8 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 bld_din3_v_end ///unsigned , default = 13'h1e0
+//Bit 15:13 reserved
+//Bit 12:0 bld_din3_v_start ///unsigned , default = 13'h0
+#define VIU_OSD_BLEND_DUMMY_DATA0 ((0x39b9 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 23:16 blend0_dummy_data_y //unsigned , default = 8'h00
+//Bit 15:8 blend0_dummy_data_cb //unsigned , default = 8'h80
+//Bit 7:0 blend0_dummy_data_cr //unsigned , default = 8'h80
+#define VIU_OSD_BLEND_DUMMY_ALPHA ((0x39ba << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:20 blend0_dummy_alpha //unsigned , default = 9'h0
+//Bit 19:11 blend1_dummy_alpha //unsigned , default = 9'h0
+//Bit 8:0 blend2_dummy_alpha //unsigned , default = 9'h0
+#define VIU_OSD_BLEND_BLEND0_SIZE ((0x39bb << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 blend0_vsize //unsigned , default = 13'h1e0
+//Bit 15:13 reserved
+//Bit 12:0 blend0_hsize //unsigned , default = 13'h2d0
+#define VIU_OSD_BLEND_BLEND1_SIZE ((0x39bc << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 blend1_vsize //unsigned , default = 13'h1e0
+//Bit 15:13 reserved
+//Bit 12:0 blend1_hsize ///unsigned , default = 13'h2d0
+//`define VIU_OSD_BLEND_DOUT0_HV_START 8'hbd
+//Bit 31:29 reserved
+//Bit 28:0 osd_blend_dout0_hv_start //unsigned , default = 29'h0
+//`define VIU_OSD_BLEND_DOUT1_HV_START 8'hbe
+//Bit 31:29 reserved
+//Bit 28:0 osd_blend_dout1_hv_start //unsigned , default = 29'h0
+#define VIU_OSD_HOLD_LINE_HIGH_BITS ((0x39c1 << 2) + 0xff000000)
+//Bit 31:8 reserved
+//Bit 7:0 hold_line_high_bits //unsigned , default = 32'h0
+#define VIU_OSD_BLEND_RO_CURRENT_XY ((0x39bf << 2) + 0xff000000)
+//Bit 31:0 ro_blend2_current_xy //unsigned , default = 32'h0
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: osd_blend_reg.h
+//
+#define VPP_LUT3D_CTRL ((0x39d0 << 2) + 0xff000000)
+#define VPP_LUT3D_CBUS2RAM_CTRL ((0x39d1 << 2) + 0xff000000)
+#define VPP_LUT3D_RAM_ADDR ((0x39d2 << 2) + 0xff000000)
+#define VPP_LUT3D_RAM_DATA ((0x39d3 << 2) + 0xff000000)
+#define VPP_GAMMA_CTRL ((0x39d4 << 2) + 0xff000000)
+#define VPP_GAMMA_BIN_ADDR ((0x39d5 << 2) + 0xff000000)
+#define VPP_GAMMA_BIN_DATA ((0x39d6 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_misc_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VPP_AFBCD0_VCBUS_BASE = 0x3a
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: vpp_mali_tx300_afbc_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+ //0x00 - 0x80
+#define VPU_MAFBC_BLOCK_ID ((0x3a00 << 2) + 0xff000000)
+#define VPU_MAFBC_IRQ_RAW_STATUS ((0x3a01 << 2) + 0xff000000)
+#define VPU_MAFBC_IRQ_CLEAR ((0x3a02 << 2) + 0xff000000)
+#define VPU_MAFBC_IRQ_MASK ((0x3a03 << 2) + 0xff000000)
+#define VPU_MAFBC_IRQ_STATUS ((0x3a04 << 2) + 0xff000000)
+#define VPU_MAFBC_COMMAND ((0x3a05 << 2) + 0xff000000)
+#define VPU_MAFBC_STATUS ((0x3a06 << 2) + 0xff000000)
+#define VPU_MAFBC_SURFACE_CFG ((0x3a07 << 2) + 0xff000000)
+#define VPU_MAFBC_AXI_CFG ((0x3a08 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S0 ((0x3a10 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S0 ((0x3a11 << 2) + 0xff000000)
+#define VPU_MAFBC_FORMAT_SPECIFIER_S0 ((0x3a12 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_WIDTH_S0 ((0x3a13 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_HEIGHT_S0 ((0x3a14 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_START_S0 ((0x3a15 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_END_S0 ((0x3a16 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_START_S0 ((0x3a17 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_END_S0 ((0x3a18 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S0 ((0x3a19 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S0 ((0x3a1a << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S0 ((0x3a1b << 2) + 0xff000000)
+#define VPU_MAFBC_PREFETCH_CFG_S0 ((0x3a1c << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_LOW_S0 ((0x3a1d << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_HIGH_S0 ((0x3a1e << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_LOW_S0 ((0x3a1f << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_HIGH_S0 ((0x3a20 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S1 ((0x3a30 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S1 ((0x3a31 << 2) + 0xff000000)
+#define VPU_MAFBC_FORMAT_SPECIFIER_S1 ((0x3a32 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_WIDTH_S1 ((0x3a33 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_HEIGHT_S1 ((0x3a34 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_START_S1 ((0x3a35 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_END_S1 ((0x3a36 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_START_S1 ((0x3a37 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_END_S1 ((0x3a38 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S1 ((0x3a39 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S1 ((0x3a3a << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S1 ((0x3a3b << 2) + 0xff000000)
+#define VPU_MAFBC_PREFETCH_CFG_S1 ((0x3a3c << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_LOW_S1 ((0x3a3d << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_HIGH_S1 ((0x3a3e << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_LOW_S1 ((0x3a3f << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_HIGH_S1 ((0x3a40 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S2 ((0x3a50 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S2 ((0x3a51 << 2) + 0xff000000)
+#define VPU_MAFBC_FORMAT_SPECIFIER_S2 ((0x3a52 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_WIDTH_S2 ((0x3a53 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_HEIGHT_S2 ((0x3a54 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_START_S2 ((0x3a55 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_END_S2 ((0x3a56 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_START_S2 ((0x3a57 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_END_S2 ((0x3a58 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S2 ((0x3a59 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S2 ((0x3a5a << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S2 ((0x3a5b << 2) + 0xff000000)
+#define VPU_MAFBC_PREFETCH_CFG_S2 ((0x3a5c << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_LOW_S2 ((0x3a5d << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_HIGH_S2 ((0x3a5e << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_LOW_S2 ((0x3a5f << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_HIGH_S2 ((0x3a60 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_LOW_S3 ((0x3a70 << 2) + 0xff000000)
+#define VPU_MAFBC_HEADER_BUF_ADDR_HIGH_S3 ((0x3a71 << 2) + 0xff000000)
+#define VPU_MAFBC_FORMAT_SPECIFIER_S3 ((0x3a72 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_WIDTH_S3 ((0x3a73 << 2) + 0xff000000)
+#define VPU_MAFBC_BUFFER_HEIGHT_S3 ((0x3a74 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_START_S3 ((0x3a75 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_X_END_S3 ((0x3a76 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_START_S3 ((0x3a77 << 2) + 0xff000000)
+#define VPU_MAFBC_BOUNDING_BOX_Y_END_S3 ((0x3a78 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_LOW_S3 ((0x3a79 << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_ADDR_HIGH_S3 ((0x3a7a << 2) + 0xff000000)
+#define VPU_MAFBC_OUTPUT_BUF_STRIDE_S3 ((0x3a7b << 2) + 0xff000000)
+#define VPU_MAFBC_PREFETCH_CFG_S3 ((0x3a7c << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_LOW_S3 ((0x3a7d << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MIN_HIGH_S3 ((0x3a7e << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_LOW_S3 ((0x3a7f << 2) + 0xff000000)
+#define VPU_MAFBC_PAYLOAD_MAX_HIGH_S3 ((0x3a80 << 2) + 0xff000000)
+ // synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_mali_tx300_afbc_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: VPP_AFBCD1_VCBUS_BASE = 0x3b
+// -----------------------------------------------
+//
+// Reading file: vpp_mali_tx300_afbc1_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+ //0x00 - 0x80
+#define VPU_MAFBC1_BLOCK_ID ((0x3b00 << 2) + 0xff000000)
+#define VPU_MAFBC1_IRQ_RAW_STATUS ((0x3b01 << 2) + 0xff000000)
+#define VPU_MAFBC1_IRQ_CLEAR ((0x3b02 << 2) + 0xff000000)
+#define VPU_MAFBC1_IRQ_MASK ((0x3b03 << 2) + 0xff000000)
+#define VPU_MAFBC1_IRQ_STATUS ((0x3b04 << 2) + 0xff000000)
+#define VPU_MAFBC1_COMMAND ((0x3b05 << 2) + 0xff000000)
+#define VPU_MAFBC1_STATUS ((0x3b06 << 2) + 0xff000000)
+#define VPU_MAFBC1_SURFACE_CFG ((0x3b07 << 2) + 0xff000000)
+#define VPU_MAFBC1_AXI_CFG ((0x3b08 << 2) + 0xff000000)
+#define VPU_MAFBC1_HEADER_BUF_ADDR_LOW_S0 ((0x3b10 << 2) + 0xff000000)
+#define VPU_MAFBC1_HEADER_BUF_ADDR_HIGH_S0 ((0x3b11 << 2) + 0xff000000)
+#define VPU_MAFBC1_FORMAT_SPECIFIER_S0 ((0x3b12 << 2) + 0xff000000)
+#define VPU_MAFBC1_BUFFER_WIDTH_S0 ((0x3b13 << 2) + 0xff000000)
+#define VPU_MAFBC1_BUFFER_HEIGHT_S0 ((0x3b14 << 2) + 0xff000000)
+#define VPU_MAFBC1_BOUNDING_BOX_X_START_S0 ((0x3b15 << 2) + 0xff000000)
+#define VPU_MAFBC1_BOUNDING_BOX_X_END_S0 ((0x3b16 << 2) + 0xff000000)
+#define VPU_MAFBC1_BOUNDING_BOX_Y_START_S0 ((0x3b17 << 2) + 0xff000000)
+#define VPU_MAFBC1_BOUNDING_BOX_Y_END_S0 ((0x3b18 << 2) + 0xff000000)
+#define VPU_MAFBC1_OUTPUT_BUF_ADDR_LOW_S0 ((0x3b19 << 2) + 0xff000000)
+#define VPU_MAFBC1_OUTPUT_BUF_ADDR_HIGH_S0 ((0x3b1a << 2) + 0xff000000)
+#define VPU_MAFBC1_OUTPUT_BUF_STRIDE_S0 ((0x3b1b << 2) + 0xff000000)
+#define VPU_MAFBC1_PREFETCH_CFG_S0 ((0x3b1c << 2) + 0xff000000)
+#define VPU_MAFBC1_PAYLOAD_MIN_LOW_S0 ((0x3b1d << 2) + 0xff000000)
+#define VPU_MAFBC1_PAYLOAD_MIN_HIGH_S0 ((0x3b1e << 2) + 0xff000000)
+#define VPU_MAFBC1_PAYLOAD_MAX_LOW_S0 ((0x3b1f << 2) + 0xff000000)
+#define VPU_MAFBC1_PAYLOAD_MAX_HIGH_S0 ((0x3b20 << 2) + 0xff000000)
+#define VPU_MAFBC1_HEADER_BUF_ADDR_LOW_S1 ((0x3b30 << 2) + 0xff000000)
+#define VPU_MAFBC1_HEADER_BUF_ADDR_HIGH_S1 ((0x3b31 << 2) + 0xff000000)
+#define VPU_MAFBC1_FORMAT_SPECIFIER_S1 ((0x3b32 << 2) + 0xff000000)
+#define VPU_MAFBC1_BUFFER_WIDTH_S1 ((0x3b33 << 2) + 0xff000000)
+#define VPU_MAFBC1_BUFFER_HEIGHT_S1 ((0x3b34 << 2) + 0xff000000)
+#define VPU_MAFBC1_BOUNDING_BOX_X_START_S1 ((0x3b35 << 2) + 0xff000000)
+#define VPU_MAFBC1_BOUNDING_BOX_X_END_S1 ((0x3b36 << 2) + 0xff000000)
+#define VPU_MAFBC1_BOUNDING_BOX_Y_START_S1 ((0x3b37 << 2) + 0xff000000)
+#define VPU_MAFBC1_BOUNDING_BOX_Y_END_S1 ((0x3b38 << 2) + 0xff000000)
+#define VPU_MAFBC1_OUTPUT_BUF_ADDR_LOW_S1 ((0x3b39 << 2) + 0xff000000)
+#define VPU_MAFBC1_OUTPUT_BUF_ADDR_HIGH_S1 ((0x3b3a << 2) + 0xff000000)
+#define VPU_MAFBC1_OUTPUT_BUF_STRIDE_S1 ((0x3b3b << 2) + 0xff000000)
+#define VPU_MAFBC1_PREFETCH_CFG_S1 ((0x3b3c << 2) + 0xff000000)
+#define VPU_MAFBC1_PAYLOAD_MIN_LOW_S1 ((0x3b3d << 2) + 0xff000000)
+#define VPU_MAFBC1_PAYLOAD_MIN_HIGH_S1 ((0x3b3e << 2) + 0xff000000)
+#define VPU_MAFBC1_PAYLOAD_MAX_LOW_S1 ((0x3b3f << 2) + 0xff000000)
+#define VPU_MAFBC1_PAYLOAD_MAX_HIGH_S1 ((0x3b40 << 2) + 0xff000000)
+#define VPU_MAFBC1_HEADER_BUF_ADDR_LOW_S2 ((0x3b50 << 2) + 0xff000000)
+#define VPU_MAFBC1_HEADER_BUF_ADDR_HIGH_S2 ((0x3b51 << 2) + 0xff000000)
+#define VPU_MAFBC1_FORMAT_SPECIFIER_S2 ((0x3b52 << 2) + 0xff000000)
+#define VPU_MAFBC1_BUFFER_WIDTH_S2 ((0x3b53 << 2) + 0xff000000)
+#define VPU_MAFBC1_BUFFER_HEIGHT_S2 ((0x3b54 << 2) + 0xff000000)
+#define VPU_MAFBC1_BOUNDING_BOX_X_START_S2 ((0x3b55 << 2) + 0xff000000)
+#define VPU_MAFBC1_BOUNDING_BOX_X_END_S2 ((0x3b56 << 2) + 0xff000000)
+#define VPU_MAFBC1_BOUNDING_BOX_Y_START_S2 ((0x3b57 << 2) + 0xff000000)
+#define VPU_MAFBC1_BOUNDING_BOX_Y_END_S2 ((0x3b58 << 2) + 0xff000000)
+#define VPU_MAFBC1_OUTPUT_BUF_ADDR_LOW_S2 ((0x3b59 << 2) + 0xff000000)
+#define VPU_MAFBC1_OUTPUT_BUF_ADDR_HIGH_S2 ((0x3b5a << 2) + 0xff000000)
+#define VPU_MAFBC1_OUTPUT_BUF_STRIDE_S2 ((0x3b5b << 2) + 0xff000000)
+#define VPU_MAFBC1_PREFETCH_CFG_S2 ((0x3b5c << 2) + 0xff000000)
+#define VPU_MAFBC1_PAYLOAD_MIN_LOW_S2 ((0x3b5d << 2) + 0xff000000)
+#define VPU_MAFBC1_PAYLOAD_MIN_HIGH_S2 ((0x3b5e << 2) + 0xff000000)
+#define VPU_MAFBC1_PAYLOAD_MAX_LOW_S2 ((0x3b5f << 2) + 0xff000000)
+#define VPU_MAFBC1_PAYLOAD_MAX_HIGH_S2 ((0x3b60 << 2) + 0xff000000)
+#define VPU_MAFBC1_HEADER_BUF_ADDR_LOW_S3 ((0x3b70 << 2) + 0xff000000)
+#define VPU_MAFBC1_HEADER_BUF_ADDR_HIGH_S3 ((0x3b71 << 2) + 0xff000000)
+#define VPU_MAFBC1_FORMAT_SPECIFIER_S3 ((0x3b72 << 2) + 0xff000000)
+#define VPU_MAFBC1_BUFFER_WIDTH_S3 ((0x3b73 << 2) + 0xff000000)
+#define VPU_MAFBC1_BUFFER_HEIGHT_S3 ((0x3b74 << 2) + 0xff000000)
+#define VPU_MAFBC1_BOUNDING_BOX_X_START_S3 ((0x3b75 << 2) + 0xff000000)
+#define VPU_MAFBC1_BOUNDING_BOX_X_END_S3 ((0x3b76 << 2) + 0xff000000)
+#define VPU_MAFBC1_BOUNDING_BOX_Y_START_S3 ((0x3b77 << 2) + 0xff000000)
+#define VPU_MAFBC1_BOUNDING_BOX_Y_END_S3 ((0x3b78 << 2) + 0xff000000)
+#define VPU_MAFBC1_OUTPUT_BUF_ADDR_LOW_S3 ((0x3b79 << 2) + 0xff000000)
+#define VPU_MAFBC1_OUTPUT_BUF_ADDR_HIGH_S3 ((0x3b7a << 2) + 0xff000000)
+#define VPU_MAFBC1_OUTPUT_BUF_STRIDE_S3 ((0x3b7b << 2) + 0xff000000)
+#define VPU_MAFBC1_PREFETCH_CFG_S3 ((0x3b7c << 2) + 0xff000000)
+#define VPU_MAFBC1_PAYLOAD_MIN_LOW_S3 ((0x3b7d << 2) + 0xff000000)
+#define VPU_MAFBC1_PAYLOAD_MIN_HIGH_S3 ((0x3b7e << 2) + 0xff000000)
+#define VPU_MAFBC1_PAYLOAD_MAX_LOW_S3 ((0x3b7f << 2) + 0xff000000)
+#define VPU_MAFBC1_PAYLOAD_MAX_HIGH_S3 ((0x3b80 << 2) + 0xff000000)
+ // synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_mali_tx300_afbc1_regs.h
+//
+// -----------------------------------------------
+// REG_BASE: VPP_AFBCD2_VCBUS_BASE = 0x3c
+// -----------------------------------------------
+//
+// Reading file: vpp_mali_tx300_afbc2_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+ //0x00 - 0x80
+#define VPU_MAFBC2_BLOCK_ID ((0x3c00 << 2) + 0xff000000)
+#define VPU_MAFBC2_IRQ_RAW_STATUS ((0x3c01 << 2) + 0xff000000)
+#define VPU_MAFBC2_IRQ_CLEAR ((0x3c02 << 2) + 0xff000000)
+#define VPU_MAFBC2_IRQ_MASK ((0x3c03 << 2) + 0xff000000)
+#define VPU_MAFBC2_IRQ_STATUS ((0x3c04 << 2) + 0xff000000)
+#define VPU_MAFBC2_COMMAND ((0x3c05 << 2) + 0xff000000)
+#define VPU_MAFBC2_STATUS ((0x3c06 << 2) + 0xff000000)
+#define VPU_MAFBC2_SURFACE_CFG ((0x3c07 << 2) + 0xff000000)
+#define VPU_MAFBC2_AXI_CFG ((0x3c08 << 2) + 0xff000000)
+#define VPU_MAFBC2_HEADER_BUF_ADDR_LOW_S0 ((0x3c10 << 2) + 0xff000000)
+#define VPU_MAFBC2_HEADER_BUF_ADDR_HIGH_S0 ((0x3c11 << 2) + 0xff000000)
+#define VPU_MAFBC2_FORMAT_SPECIFIER_S0 ((0x3c12 << 2) + 0xff000000)
+#define VPU_MAFBC2_BUFFER_WIDTH_S0 ((0x3c13 << 2) + 0xff000000)
+#define VPU_MAFBC2_BUFFER_HEIGHT_S0 ((0x3c14 << 2) + 0xff000000)
+#define VPU_MAFBC2_BOUNDING_BOX_X_START_S0 ((0x3c15 << 2) + 0xff000000)
+#define VPU_MAFBC2_BOUNDING_BOX_X_END_S0 ((0x3c16 << 2) + 0xff000000)
+#define VPU_MAFBC2_BOUNDING_BOX_Y_START_S0 ((0x3c17 << 2) + 0xff000000)
+#define VPU_MAFBC2_BOUNDING_BOX_Y_END_S0 ((0x3c18 << 2) + 0xff000000)
+#define VPU_MAFBC2_OUTPUT_BUF_ADDR_LOW_S0 ((0x3c19 << 2) + 0xff000000)
+#define VPU_MAFBC2_OUTPUT_BUF_ADDR_HIGH_S0 ((0x3c1a << 2) + 0xff000000)
+#define VPU_MAFBC2_OUTPUT_BUF_STRIDE_S0 ((0x3c1b << 2) + 0xff000000)
+#define VPU_MAFBC2_PREFETCH_CFG_S0 ((0x3c1c << 2) + 0xff000000)
+#define VPU_MAFBC2_PAYLOAD_MIN_LOW_S0 ((0x3c1d << 2) + 0xff000000)
+#define VPU_MAFBC2_PAYLOAD_MIN_HIGH_S0 ((0x3c1e << 2) + 0xff000000)
+#define VPU_MAFBC2_PAYLOAD_MAX_LOW_S0 ((0x3c1f << 2) + 0xff000000)
+#define VPU_MAFBC2_PAYLOAD_MAX_HIGH_S0 ((0x3c20 << 2) + 0xff000000)
+#define VPU_MAFBC2_HEADER_BUF_ADDR_LOW_S1 ((0x3c30 << 2) + 0xff000000)
+#define VPU_MAFBC2_HEADER_BUF_ADDR_HIGH_S1 ((0x3c31 << 2) + 0xff000000)
+#define VPU_MAFBC2_FORMAT_SPECIFIER_S1 ((0x3c32 << 2) + 0xff000000)
+#define VPU_MAFBC2_BUFFER_WIDTH_S1 ((0x3c33 << 2) + 0xff000000)
+#define VPU_MAFBC2_BUFFER_HEIGHT_S1 ((0x3c34 << 2) + 0xff000000)
+#define VPU_MAFBC2_BOUNDING_BOX_X_START_S1 ((0x3c35 << 2) + 0xff000000)
+#define VPU_MAFBC2_BOUNDING_BOX_X_END_S1 ((0x3c36 << 2) + 0xff000000)
+#define VPU_MAFBC2_BOUNDING_BOX_Y_START_S1 ((0x3c37 << 2) + 0xff000000)
+#define VPU_MAFBC2_BOUNDING_BOX_Y_END_S1 ((0x3c38 << 2) + 0xff000000)
+#define VPU_MAFBC2_OUTPUT_BUF_ADDR_LOW_S1 ((0x3c39 << 2) + 0xff000000)
+#define VPU_MAFBC2_OUTPUT_BUF_ADDR_HIGH_S1 ((0x3c3a << 2) + 0xff000000)
+#define VPU_MAFBC2_OUTPUT_BUF_STRIDE_S1 ((0x3c3b << 2) + 0xff000000)
+#define VPU_MAFBC2_PREFETCH_CFG_S1 ((0x3c3c << 2) + 0xff000000)
+#define VPU_MAFBC2_PAYLOAD_MIN_LOW_S1 ((0x3c3d << 2) + 0xff000000)
+#define VPU_MAFBC2_PAYLOAD_MIN_HIGH_S1 ((0x3c3e << 2) + 0xff000000)
+#define VPU_MAFBC2_PAYLOAD_MAX_LOW_S1 ((0x3c3f << 2) + 0xff000000)
+#define VPU_MAFBC2_PAYLOAD_MAX_HIGH_S1 ((0x3c40 << 2) + 0xff000000)
+#define VPU_MAFBC2_HEADER_BUF_ADDR_LOW_S2 ((0x3c50 << 2) + 0xff000000)
+#define VPU_MAFBC2_HEADER_BUF_ADDR_HIGH_S2 ((0x3c51 << 2) + 0xff000000)
+#define VPU_MAFBC2_FORMAT_SPECIFIER_S2 ((0x3c52 << 2) + 0xff000000)
+#define VPU_MAFBC2_BUFFER_WIDTH_S2 ((0x3c53 << 2) + 0xff000000)
+#define VPU_MAFBC2_BUFFER_HEIGHT_S2 ((0x3c54 << 2) + 0xff000000)
+#define VPU_MAFBC2_BOUNDING_BOX_X_START_S2 ((0x3c55 << 2) + 0xff000000)
+#define VPU_MAFBC2_BOUNDING_BOX_X_END_S2 ((0x3c56 << 2) + 0xff000000)
+#define VPU_MAFBC2_BOUNDING_BOX_Y_START_S2 ((0x3c57 << 2) + 0xff000000)
+#define VPU_MAFBC2_BOUNDING_BOX_Y_END_S2 ((0x3c58 << 2) + 0xff000000)
+#define VPU_MAFBC2_OUTPUT_BUF_ADDR_LOW_S2 ((0x3c59 << 2) + 0xff000000)
+#define VPU_MAFBC2_OUTPUT_BUF_ADDR_HIGH_S2 ((0x3c5a << 2) + 0xff000000)
+#define VPU_MAFBC2_OUTPUT_BUF_STRIDE_S2 ((0x3c5b << 2) + 0xff000000)
+#define VPU_MAFBC2_PREFETCH_CFG_S2 ((0x3c5c << 2) + 0xff000000)
+#define VPU_MAFBC2_PAYLOAD_MIN_LOW_S2 ((0x3c5d << 2) + 0xff000000)
+#define VPU_MAFBC2_PAYLOAD_MIN_HIGH_S2 ((0x3c5e << 2) + 0xff000000)
+#define VPU_MAFBC2_PAYLOAD_MAX_LOW_S2 ((0x3c5f << 2) + 0xff000000)
+#define VPU_MAFBC2_PAYLOAD_MAX_HIGH_S2 ((0x3c60 << 2) + 0xff000000)
+#define VPU_MAFBC2_HEADER_BUF_ADDR_LOW_S3 ((0x3c70 << 2) + 0xff000000)
+#define VPU_MAFBC2_HEADER_BUF_ADDR_HIGH_S3 ((0x3c71 << 2) + 0xff000000)
+#define VPU_MAFBC2_FORMAT_SPECIFIER_S3 ((0x3c72 << 2) + 0xff000000)
+#define VPU_MAFBC2_BUFFER_WIDTH_S3 ((0x3c73 << 2) + 0xff000000)
+#define VPU_MAFBC2_BUFFER_HEIGHT_S3 ((0x3c74 << 2) + 0xff000000)
+#define VPU_MAFBC2_BOUNDING_BOX_X_START_S3 ((0x3c75 << 2) + 0xff000000)
+#define VPU_MAFBC2_BOUNDING_BOX_X_END_S3 ((0x3c76 << 2) + 0xff000000)
+#define VPU_MAFBC2_BOUNDING_BOX_Y_START_S3 ((0x3c77 << 2) + 0xff000000)
+#define VPU_MAFBC2_BOUNDING_BOX_Y_END_S3 ((0x3c78 << 2) + 0xff000000)
+#define VPU_MAFBC2_OUTPUT_BUF_ADDR_LOW_S3 ((0x3c79 << 2) + 0xff000000)
+#define VPU_MAFBC2_OUTPUT_BUF_ADDR_HIGH_S3 ((0x3c7a << 2) + 0xff000000)
+#define VPU_MAFBC2_OUTPUT_BUF_STRIDE_S3 ((0x3c7b << 2) + 0xff000000)
+#define VPU_MAFBC2_PREFETCH_CFG_S3 ((0x3c7c << 2) + 0xff000000)
+#define VPU_MAFBC2_PAYLOAD_MIN_LOW_S3 ((0x3c7d << 2) + 0xff000000)
+#define VPU_MAFBC2_PAYLOAD_MIN_HIGH_S3 ((0x3c7e << 2) + 0xff000000)
+#define VPU_MAFBC2_PAYLOAD_MAX_LOW_S3 ((0x3c7f << 2) + 0xff000000)
+#define VPU_MAFBC2_PAYLOAD_MAX_HIGH_S3 ((0x3c80 << 2) + 0xff000000)
+ // synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_mali_tx300_afbc2_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VPU_OSDSC_BLD_VCBUS_BASE = 0x3d
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: vpu_osdsc_bld_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+// for osd3 & osd4 blend
+#define OSD34_OUT_HSCOPE ((0x3d40 << 2) + 0xff000000)
+#define OSD34_OUT_VSCOPE ((0x3d41 << 2) + 0xff000000)
+#define OSD34_DUMMY_DATA ((0x3d42 << 2) + 0xff000000)
+#define OSD34_BLEND_CTRL0 ((0x3d43 << 2) + 0xff000000)
+#define OSD34_BLEND_CTRL1 ((0x3d44 << 2) + 0xff000000)
+#define OSD34_RO_HV_CNT ((0x3d45 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF00_01 ((0x3d60 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF02_10 ((0x3d61 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF11_12 ((0x3d62 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF20_21 ((0x3d63 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF22 ((0x3d64 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF13_14 ((0x3d65 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF23_24 ((0x3d66 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_COEF15_25 ((0x3d67 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_CLIP ((0x3d68 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_OFFSET0_1 ((0x3d69 << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_OFFSET2 ((0x3d6a << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET0_1 ((0x3d6b << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_PRE_OFFSET2 ((0x3d6c << 2) + 0xff000000)
+#define VPP_WRAP_OSD1_MATRIX_EN_CTRL ((0x3d6d << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF00_01 ((0x3d70 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF02_10 ((0x3d71 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF11_12 ((0x3d72 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF20_21 ((0x3d73 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF22 ((0x3d74 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF13_14 ((0x3d75 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF23_24 ((0x3d76 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_COEF15_25 ((0x3d77 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_CLIP ((0x3d78 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_OFFSET0_1 ((0x3d79 << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_OFFSET2 ((0x3d7a << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET0_1 ((0x3d7b << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_PRE_OFFSET2 ((0x3d7c << 2) + 0xff000000)
+#define VPP_WRAP_OSD2_MATRIX_EN_CTRL ((0x3d7d << 2) + 0xff000000)
+#define VIU_OSD3_CTRL_STAT ((0x3d80 << 2) + 0xff000000)
+#define VIU_OSD3_CTRL_STAT2 ((0x3d81 << 2) + 0xff000000)
+#define VIU_OSD3_COLOR_ADDR ((0x3d82 << 2) + 0xff000000)
+#define VIU_OSD3_COLOR ((0x3d83 << 2) + 0xff000000)
+#define VIU_OSD3_TCOLOR_AG0 ((0x3d84 << 2) + 0xff000000)
+#define VIU_OSD3_TCOLOR_AG1 ((0x3d85 << 2) + 0xff000000)
+#define VIU_OSD3_TCOLOR_AG2 ((0x3d86 << 2) + 0xff000000)
+#define VIU_OSD3_TCOLOR_AG3 ((0x3d87 << 2) + 0xff000000)
+#define VIU_OSD3_BLK0_CFG_W0 ((0x3d88 << 2) + 0xff000000)
+#define VIU_OSD3_BLK1_CFG_W0 ((0x3d89 << 2) + 0xff000000)
+#define VIU_OSD3_BLK2_CFG_W0 ((0x3d8a << 2) + 0xff000000)
+#define VIU_OSD3_BLK3_CFG_W0 ((0x3d8b << 2) + 0xff000000)
+#define VIU_OSD3_BLK0_CFG_W1 ((0x3d8c << 2) + 0xff000000)
+#define VIU_OSD3_BLK1_CFG_W1 ((0x3d8d << 2) + 0xff000000)
+#define VIU_OSD3_BLK2_CFG_W1 ((0x3d8e << 2) + 0xff000000)
+#define VIU_OSD3_BLK3_CFG_W1 ((0x3d8f << 2) + 0xff000000)
+#define VIU_OSD3_BLK0_CFG_W2 ((0x3d90 << 2) + 0xff000000)
+#define VIU_OSD3_BLK1_CFG_W2 ((0x3d91 << 2) + 0xff000000)
+#define VIU_OSD3_BLK2_CFG_W2 ((0x3d92 << 2) + 0xff000000)
+#define VIU_OSD3_BLK3_CFG_W2 ((0x3d93 << 2) + 0xff000000)
+#define VIU_OSD3_BLK0_CFG_W3 ((0x3d94 << 2) + 0xff000000)
+#define VIU_OSD3_BLK1_CFG_W3 ((0x3d95 << 2) + 0xff000000)
+#define VIU_OSD3_BLK2_CFG_W3 ((0x3d96 << 2) + 0xff000000)
+#define VIU_OSD3_BLK3_CFG_W3 ((0x3d97 << 2) + 0xff000000)
+#define VIU_OSD3_BLK0_CFG_W4 ((0x3d98 << 2) + 0xff000000)
+#define VIU_OSD3_BLK1_CFG_W4 ((0x3d99 << 2) + 0xff000000)
+#define VIU_OSD3_BLK2_CFG_W4 ((0x3d9a << 2) + 0xff000000)
+#define VIU_OSD3_BLK3_CFG_W4 ((0x3d9b << 2) + 0xff000000)
+#define VIU_OSD3_FIFO_CTRL_STAT ((0x3d9c << 2) + 0xff000000)
+#define VIU_OSD3_TEST_RDDATA ((0x3d9d << 2) + 0xff000000)
+#define VIU_OSD3_PROT_CTRL ((0x3d9e << 2) + 0xff000000)
+#define VIU_OSD3_MALI_UNPACK_CTRL ((0x3d9f << 2) + 0xff000000)
+#define VIU_OSD3_DIMM_CTRL ((0x3da0 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF00_01 ((0x3db0 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF02_10 ((0x3db1 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF11_12 ((0x3db2 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF20_21 ((0x3db3 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF22 ((0x3db4 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF13_14 ((0x3db5 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF23_24 ((0x3db6 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_COEF15_25 ((0x3db7 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_CLIP ((0x3db8 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_OFFSET0_1 ((0x3db9 << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_OFFSET2 ((0x3dba << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_PRE_OFFSET0_1 ((0x3dbb << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_PRE_OFFSET2 ((0x3dbc << 2) + 0xff000000)
+#define VIU_OSD3_MATRIX_EN_CTRL ((0x3dbd << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_COEF00_01 ((0x3db0 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_COEF02_10 ((0x3db1 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_COEF11_12 ((0x3db2 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_COEF20_21 ((0x3db3 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_COEF22 ((0x3db4 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_COEF13_14 ((0x3db5 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_COEF23_24 ((0x3db6 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_COEF15_25 ((0x3db7 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_CLIP ((0x3db8 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_OFFSET0_1 ((0x3db9 << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_OFFSET2 ((0x3dba << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET0_1 ((0x3dbb << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_PRE_OFFSET2 ((0x3dbc << 2) + 0xff000000)
+#define VPP_WRAP_OSD3_MATRIX_EN_CTRL ((0x3dbd << 2) + 0xff000000)
+#define VIU_OSD4_CTRL_STAT ((0x3dc0 << 2) + 0xff000000)
+#define VIU_OSD4_CTRL_STAT2 ((0x3dc1 << 2) + 0xff000000)
+#define VIU_OSD4_COLOR_ADDR ((0x3dc2 << 2) + 0xff000000)
+#define VIU_OSD4_COLOR ((0x3dc3 << 2) + 0xff000000)
+#define VIU_OSD4_TCOLOR_AG0 ((0x3dc4 << 2) + 0xff000000)
+#define VIU_OSD4_TCOLOR_AG1 ((0x3dc5 << 2) + 0xff000000)
+#define VIU_OSD4_TCOLOR_AG2 ((0x3dc6 << 2) + 0xff000000)
+#define VIU_OSD4_TCOLOR_AG3 ((0x3dc7 << 2) + 0xff000000)
+#define VIU_OSD4_BLK0_CFG_W0 ((0x3dc8 << 2) + 0xff000000)
+#define VIU_OSD4_BLK1_CFG_W0 ((0x3dc9 << 2) + 0xff000000)
+#define VIU_OSD4_BLK2_CFG_W0 ((0x3dca << 2) + 0xff000000)
+#define VIU_OSD4_BLK3_CFG_W0 ((0x3dcb << 2) + 0xff000000)
+#define VIU_OSD4_BLK0_CFG_W1 ((0x3dcc << 2) + 0xff000000)
+#define VIU_OSD4_BLK1_CFG_W1 ((0x3dcd << 2) + 0xff000000)
+#define VIU_OSD4_BLK2_CFG_W1 ((0x3dce << 2) + 0xff000000)
+#define VIU_OSD4_BLK3_CFG_W1 ((0x3dcf << 2) + 0xff000000)
+#define VIU_OSD4_BLK0_CFG_W2 ((0x3dd0 << 2) + 0xff000000)
+#define VIU_OSD4_BLK1_CFG_W2 ((0x3dd1 << 2) + 0xff000000)
+#define VIU_OSD4_BLK2_CFG_W2 ((0x3dd2 << 2) + 0xff000000)
+#define VIU_OSD4_BLK3_CFG_W2 ((0x3dd3 << 2) + 0xff000000)
+#define VIU_OSD4_BLK0_CFG_W3 ((0x3dd4 << 2) + 0xff000000)
+#define VIU_OSD4_BLK1_CFG_W3 ((0x3dd5 << 2) + 0xff000000)
+#define VIU_OSD4_BLK2_CFG_W3 ((0x3dd6 << 2) + 0xff000000)
+#define VIU_OSD4_BLK3_CFG_W3 ((0x3dd7 << 2) + 0xff000000)
+#define VIU_OSD4_BLK0_CFG_W4 ((0x3dd8 << 2) + 0xff000000)
+#define VIU_OSD4_BLK1_CFG_W4 ((0x3dd9 << 2) + 0xff000000)
+#define VIU_OSD4_BLK2_CFG_W4 ((0x3dda << 2) + 0xff000000)
+#define VIU_OSD4_BLK3_CFG_W4 ((0x3ddb << 2) + 0xff000000)
+#define VIU_OSD4_FIFO_CTRL_STAT ((0x3ddc << 2) + 0xff000000)
+#define VIU_OSD4_TEST_RDDATA ((0x3ddd << 2) + 0xff000000)
+#define VIU_OSD4_PROT_CTRL ((0x3dde << 2) + 0xff000000)
+#define VIU_OSD4_MALI_UNPACK_CTRL ((0x3ddf << 2) + 0xff000000)
+#define VIU_OSD4_DIMM_CTRL ((0x3de0 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF00_01 ((0x3df0 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF02_10 ((0x3df1 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF11_12 ((0x3df2 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF20_21 ((0x3df3 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF22 ((0x3df4 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF13_14 ((0x3df5 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF23_24 ((0x3df6 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_COEF15_25 ((0x3df7 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_CLIP ((0x3df8 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_OFFSET0_1 ((0x3df9 << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_OFFSET2 ((0x3dfa << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_PRE_OFFSET0_1 ((0x3dfb << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_PRE_OFFSET2 ((0x3dfc << 2) + 0xff000000)
+#define VIU_OSD4_MATRIX_EN_CTRL ((0x3dfd << 2) + 0xff000000)
+ // synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_osdsc_bld_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VPPF_VCBUS_BASE = 0x40
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: lc_stts_curve.h
+//
+#define LC_CURVE_CTRL ((0x4000 << 2) + 0xff000000)
+ //Bit 31 :12 reg_lc_misc U RW default = 'h0 None
+ //Bit 11 :10 reserved U RW default = 'h0 None
+ //Bit 9 :8 reg_lc_hist_curve_nodes_hlpf U RW default = 'h1 horizontal lpf of the ram_curve_nodes, 0: no LPF, 1= [1 2 1]; 2: [1 2 2 2 1]/8
+ //Bit 7 :6 reserved U RW default = 'h0 None
+ //Bit 5 :4 reg_lc_hist_curve_nodes_vlpf U RW default = 'h1 vertical lpf of the ram_curve_nodes, 0: no LPF, 1= [1 2 1]; 2: [1 2 2 2 1]/8
+ //Bit 3 :2 reserved U RW default = 'h0 None
+ //Bit 1 reg_lc_blackbar_mute_en U RW default = 'h1 mute the black bar corresponding bin, 0: no mute, 1: mute enable; default=1
+ //Bit 0 reg_lc_curve_en U RW default = 'h1 default=0
+#define LC_CURVE_HV_NUM ((0x4001 << 2) + 0xff000000)
+ //Bit 31 :13 reserved U RW default = 'h0 None
+ //Bit 12 :8 reg_lc_cur_blk_hnum U RW default = 'hc lc processing region number of V, maximum to (STA_LEN_V-1) (0~8), should be same as reg_lc_blk_hnum
+ //Bit 7 :5 reserved U RW default = 'h0 None
+ //Bit 4 :0 reg_lc_cur_blk_vnum U RW default = 'h8 lc processing region number of H, maximum to (STA_LEN_H-1) (0~12), should be same as reg_lc_blk_vnum
+#define LC_CURVE_LMT_RAT ((0x4002 << 2) + 0xff000000)
+ //Bit 31 :16 reserved U RW default = 'h0 None
+ //Bit 15 :8 reg_lmtrat_minmax U RW default = 'h6 x/1024 of amount
+ //Bit 7 :0 reg_lmtrat_valid U RW default = 'h14 x/1024 of amount
+#define LC_CURVE_CONTRAST_LH ((0x4003 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_contrast_low U RW default = 'h10 contrast gain to the lc for dark side, normalized 256 as "1", set adaptive TODO
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_contrast_hig U RW default = 'h18 contrast gain to the lc for bright side, normalized 256 as "1"
+#define LC_CURVE_CONTRAST__LMT_LH ((0x4004 << 2) + 0xff000000)
+ //Bit 31 :24 reg_lc_cntstlmt_low_0 U RW default = 'ha limit for the contrast low, delta_low = MIN(delta_low, MIN( MAX((minBV-min_val)*scl_low/8, lmt_low[0]),lmt_low[1]))
+ //Bit 23 :16 reg_lc_cntstlmt_hig_0 U RW default = 'h14 limit for the contrast high,delta_hig = MIN(delta_hig, MIN( MAX((max_val-maxBV)*scl_hig/8, lmt_hig[0]),lmt_hig[1]))
+ //Bit 15 :8 reg_lc_cntstlmt_low_1 U RW default = 'hff limit for the contrast low, delta_low = MIN(delta_low, MIN( MAX((minBV-min_val)*scl_low/8, lmt_low[0]),lmt_low[1]))
+ //Bit 7 :0 reg_lc_cntstlmt_hig_1 U RW default = 'hff limit for the contrast high,delta_hig = MIN(delta_hig, MIN( MAX((max_val-maxBV)*scl_hig/8, lmt_hig[0]),lmt_hig[1]))
+#define LC_CURVE_CONTRAST_SCL_LH ((0x4005 << 2) + 0xff000000)
+ //Bit 31 :16 reserved U RW default = 'h0 None
+ //Bit 15 :8 reg_lc_cntstscl_low U RW default = 'h40 scale for the contrast low, norm 8 as 1; delta_low = MIN(delta_low, MIN(MAX((minBV-min_val)*scl_low/8, lmt_low[0]),lmt_low[1]))
+ //Bit 7 :0 reg_lc_cntstscl_hig U RW default = 'h20 scale for the contrast high,norm 8 as 1; delta_hig = MIN(delta_hig, MIN(MAX((max_val-maxBV)*scl_hig/8, lmt_hig[0]),lmt_hig[1]))
+#define LC_CURVE_CONTRAST_BVN_LH ((0x4006 << 2) + 0xff000000)
+ //Bit 31 :16 reserved U RW default = 'h0 None
+ //Bit 15 :8 reg_lc_cntstbvn_low U RW default = 'h20 scale to num_m as limit of min_val to minBV distance, to protect mono-color, default = 32; min_val= MAX(min_val, minBV- MAX(num_m-1,0)*bvn_low)
+ //Bit 7 :0 reg_lc_cntstbvn_hig U RW default = 'h20 scale to num_m as limit of max_val to maxBV distance, to protect mono-color, default = 32; min_val= MIN(max_val, maxBV+ MAX(num_m-1,0)*bvn_lo
+#define LC_CURVE_MISC0 ((0x4007 << 2) + 0xff000000)
+ //Bit 31 :20 reserved U RW default = 'h0 None
+ //Bit 19 :16 reg_lc_num_m_coring U RW default = 'h1 coring to num_m, soft coring,default = 2;
+ //Bit 15 :8 reg_lc_vbin_min U RW default = 'h30 4x is min width of valid histogram bin num,
+ //Bit 7 :0 reg_lc_slope_max_face U RW default = 'h38 maximum slope for the pkBin-maxBV range curve to do face protection, normalized to 32 as 1, default= 48
+#define LC_CURVE_YPKBV_RAT ((0x4008 << 2) + 0xff000000)
+ //Bit 31 :24 reg_lc_ypkbv_ratio_0 U RW default = 'h8c x= ratio*(maxBv-minBv)+min_val as low bound of the ypkBV; normalized to 256 as 1
+ //Bit 23 :16 reg_lc_ypkbv_ratio_1 U RW default = 'ha0 x= ratio*(maxBv-minBv)+min_val as low bound of the ypkBV; normalized to 256 as 1
+ //Bit 15 :8 reg_lc_ypkbv_ratio_2 U RW default = 'h78 x= ratio*(maxBv-minBv)+min_val as low bound of the ypkBV; normalized to 256 as 1
+ //Bit 7 :0 reg_lc_ypkbv_ratio_3 U RW default = 'h60 x= ratio*(maxBv-minBv)+min_val as low bound of the ypkBV; normalized to 256 as 1
+#define LC_CURVE_YPKBV_SLP_LMT ((0x4009 << 2) + 0xff000000)
+ //Bit 31 :16 reserved U RW default = 'h0 None
+ //Bit 15 :8 reg_lc_ypkbv_slope_lmt_0 U RW default = 'hc min max slop for the curves to avoid artifacts, [0] for min_slope, [1] for max_slop, e.g.max_slope= limit*(pkBv-minBv)+min_val as high bound of the ypkBV; normalized to 32 as 1
+ //Bit 7 :0 reg_lc_ypkbv_slope_lmt_1 U RW default = 'h60 None
+#define LC_CURVE_YMINVAL_LMT_0_1 ((0x400a << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_0 U RW default = 'h30 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_1 U RW default = 'h50 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMINVAL_LMT_2_3 ((0x400b << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_2 U RW default = 'h78 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_3 U RW default = 'h80 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMINVAL_LMT_4_5 ((0x400c << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_4 U RW default = 'ha0 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_5 U RW default = 'hc4 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMINVAL_LMT_6_7 ((0x400d << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_6 U RW default = 'he0 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_7 U RW default = 'h100 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMINVAL_LMT_8_9 ((0x400e << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_8 U RW default = 'h120 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_9 U RW default = 'h140 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMINVAL_LMT_10_11 ((0x400f << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_10 U RW default = 'h160 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_11 U RW default = 'h190 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMAXVAL_LMT_0_1 ((0x4010 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_0 U RW default = 'h78 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_1 U RW default = 'h96 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_YMAXVAL_LMT_2_3 ((0x4011 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_2 U RW default = 'he6 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_3 U RW default = 'h112 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_YMAXVAL_LMT_4_5 ((0x4012 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_4 U RW default = 'h14a lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_5 U RW default = 'h180 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_YMAXVAL_LMT_6_7 ((0x4013 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_6 U RW default = 'h1d4 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_7 U RW default = 'h200 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_YMAXVAL_LMT_8_9 ((0x4014 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_8 U RW default = 'h240 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_9 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_YMAXVAL_LMT_10_11 ((0x4015 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_10 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_11 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_HISTVLD_THRD ((0x4016 << 2) + 0xff000000)
+ //Bit 31 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_histvld_thrd U RW default = 'h1fa threshold to compare to bin to get number of valid bins
+#define LC_CURVE_BB_MUTE_THRD ((0x4017 << 2) + 0xff000000)
+ //Bit 31 :24 reserved U RW default = 'h0 None
+ //Bit 23 :0 reg_lc_blackbar_mute_thrd U RW default = 'h2a30 1/8 of the region
+#define LC_CURVE_INT_STATUS ((0x4018 << 2) + 0xff000000)
+#define LC_CURVE_RAM_CTRL ((0x4020 << 2) + 0xff000000)
+#define LC_CURVE_RAM_ADDR ((0x4021 << 2) + 0xff000000)
+#define LC_CURVE_RAM_DATA ((0x4022 << 2) + 0xff000000)
+#define LC_CURVE_YMINVAL_LMT_12_13 ((0x4040 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_12 U RW default = 'h160 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_13 U RW default = 'h190 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMINVAL_LMT_14_15 ((0x4041 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_yminval_lmt_14 U RW default = 'h160 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_yminval_lmt_15 U RW default = 'h190 lmt_val = lmt[minBV(64:64:768)], and yminV = MAX(yminV,lmt_val), for very dark region boost, default= [48, 80, 120, 60]
+#define LC_CURVE_YMAXVAL_LMT_12_13 ((0x4042 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_12 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_13 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+#define LC_CURVE_YMAXVAL_LMT_14_15 ((0x4043 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ymaxval_lmt_14 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ymaxval_lmt_15 U RW default = 'h280 lmt_val = 4*lmt[maxBV(64:64:1023)], and ymaxV = MAX(ymaxV,lmt[maxBV]), default= ...
+//u10, lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV])
+#define LC_CURVE_YPKBV_LMT_0_1 ((0x4044 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_0 U RW default = 'h78 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_1 U RW default = 'h96 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_2_3 ((0x4045 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_2 U RW default = 'he6 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_3 U RW default = 'h112 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_4_5 ((0x4046 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_4 U RW default = 'h14a lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_5 U RW default = 'h180 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_6_7 ((0x4047 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_6 U RW default = 'h1d4 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_7 U RW default = 'h200 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_8_9 ((0x4048 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_8 U RW default = 'h240 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_9 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_10_11 ((0x4049 << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_10 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_11 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_12_13 ((0x404a << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_12 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_13 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+#define LC_CURVE_YPKBV_LMT_14_15 ((0x404b << 2) + 0xff000000)
+ //Bit 31 :26 reserved U RW default = 'h0 None
+ //Bit 25 :16 reg_lc_ypkbv_lmt_14 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+ //Bit 15 :10 reserved U RW default = 'h0 None
+ //Bit 9 :0 reg_lc_ypkbv_lmt_15 U RW default = 'h280 lmt_val = 4*lmt[pkBV(64:64:1023)] , and ypkBV = MAX(ypkBV,lmt[pkBV]), default= ...
+//-------------------------------------------------------------
+#define LC_STTS_GCLK_CTRL0 ((0x4028 << 2) + 0xff000000)
+#define LC_STTS_CTRL0 ((0x4029 << 2) + 0xff000000)
+#define LC_STTS_WIDTHM1_HEIGHTM1 ((0x402a << 2) + 0xff000000)
+#define LC_STTS_MATRIX_COEF00_01 ((0x402b << 2) + 0xff000000)
+#define LC_STTS_MATRIX_COEF02_10 ((0x402c << 2) + 0xff000000)
+#define LC_STTS_MATRIX_COEF11_12 ((0x402d << 2) + 0xff000000)
+#define LC_STTS_MATRIX_COEF20_21 ((0x402e << 2) + 0xff000000)
+#define LC_STTS_MATRIX_COEF22 ((0x402f << 2) + 0xff000000)
+#define LC_STTS_MATRIX_OFFSET0_1 ((0x4030 << 2) + 0xff000000)
+#define LC_STTS_MATRIX_OFFSET2 ((0x4031 << 2) + 0xff000000)
+#define LC_STTS_MATRIX_PRE_OFFSET0_1 ((0x4032 << 2) + 0xff000000)
+#define LC_STTS_MATRIX_PRE_OFFSET2 ((0x4033 << 2) + 0xff000000)
+#define LC_STTS_MATRIX_HL_COLOR ((0x4034 << 2) + 0xff000000)
+#define LC_STTS_MATRIX_PROBE_POS ((0x4035 << 2) + 0xff000000)
+#define LC_STTS_MATRIX_PROBE_COLOR ((0x4036 << 2) + 0xff000000)
+#define LC_STTS_HIST_REGION_IDX ((0x4037 << 2) + 0xff000000)
+#define LC_STTS_HIST_SET_REGION ((0x4038 << 2) + 0xff000000)
+#define LC_STTS_HIST_READ_REGION ((0x4039 << 2) + 0xff000000)
+#define LC_STTS_HIST_START_RD_REGION ((0x403a << 2) + 0xff000000)
+#define LC_STTS_WHITE_INFO ((0x403b << 2) + 0xff000000)
+#define LC_STTS_BLACK_INFO ((0x403c << 2) + 0xff000000)
+//
+// Closing file: lc_stts_curve.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VDIN_AFBCE_VCBUS_BASE = 0x41
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: vdin_afbce_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+// VDIN
+//===========================================================================
+#define VDIN2_WR_CTRL ((0x4101 << 2) + 0xff000000)
+#define VDIN2_WR_CTRL2 ((0x4102 << 2) + 0xff000000)
+#define VDIN2_WR_H_START_END ((0x4103 << 2) + 0xff000000)
+#define VDIN2_WR_V_START_END ((0x4104 << 2) + 0xff000000)
+#define VDIN2_DBG_AXI_CMD_CNT ((0x4105 << 2) + 0xff000000)
+#define VDIN2_DBG_AXI_DAT_CNT ((0x4106 << 2) + 0xff000000)
+#define VDIN2_WR_URGENT_CTRL ((0x4107 << 2) + 0xff000000)
+#define VDIN2_RO_WRMIF_STATUS ((0x4108 << 2) + 0xff000000)
+#define VDIN2_WR_BADDR_LUMA ((0x4110 << 2) + 0xff000000)
+#define VDIN2_WR_BADDR_CHROMA ((0x4111 << 2) + 0xff000000)
+#define VDIN2_WR_STRIDE_LUMA ((0x4112 << 2) + 0xff000000)
+#define VDIN2_WR_STRIDE_CHROMA ((0x4113 << 2) + 0xff000000)
+#define VDIN_TOP_SECURE0_ST_RO ((0x4109 << 2) + 0xff000000)
+#define VDIN_TOP_SECURE_DUMMY ((0x410a << 2) + 0xff000000)
+#define VDIN_TOP_DOUBLE_CTRL ((0x410b << 2) + 0xff000000)
+#define VDIN_TOP_SECURE1_ST_RO ((0x410c << 2) + 0xff000000)
+#define VDIN_TOP_MISC ((0x410d << 2) + 0xff000000)
+#define VDIN_TOP_SECURE_REG0 ((0x410e << 2) + 0xff000000)
+#define VDIN_TOP_SECURE_REG1 ((0x410f << 2) + 0xff000000)
+#define VDIN_SECURE_RXIN_DW ((0x4116 << 2) + 0xff000000)
+// 8'ha0 ~ 8'hc6
+//
+// Reading file: vdin_afbc_enc_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define AFBCE_ENABLE ((0x41a0 << 2) + 0xff000000)
+//Bit 31:20, gclk_ctrl unsigned , default = 0,
+//Bit 19:16, afbce_sync_sel unsigned , default = 0,
+//Bit 15:14, reserved
+//Bit 13, enc_rst_mode unsigned , default = 0,
+//Bit 12, enc_en_mode unsigned , default = 0,
+//Bit 11:9, reserved
+//Bit 8, enc_enable unsigned , default = 0,
+//Bit 7:1, reserved
+//Bit 0, reserved enc_frm_start pulse use this bit don't use
+#define AFBCE_MODE ((0x41a1 << 2) + 0xff000000)
+//Bit 31:29, soft_rst unsigned, default = 0 ,the use as go_field
+//Bit 28, reserved unsigned, default = 0 , enable singal of crop
+//Bit 27:26, rev_mode unsigned, default = 0 , reverse mode
+//Bit 25:24, mif_urgent unsigned, default = 3 , info mif and data mif urgent
+//Bit 23, reserved
+//Bit 22:16, hold_line_num unsigned, default = 4, 0: burst1 1:burst2 2:burst4
+//Bit 15:14, burst_mode unsigned, default = 1, 0: burst1 1:burst2 2:burst4
+//Bit 13:1, reserved
+//Bit 0, reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb
+#define AFBCE_SIZE_IN ((0x41a2 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hsize_in unsigned, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vsize_in unsigned, default = 1080 , pic vert size in unit: pixel
+#define AFBCE_BLK_SIZE_IN ((0x41a3 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16 hblk_size unsigned, default = 60 , pic horz size in unit: pixel
+//Bit 15:13, reserved
+//Bit 12:0, vblk_size unsigned, default = 270, pic vert size in unit: pixel
+#define AFBCE_HEAD_BADDR ((0x41a4 << 2) + 0xff000000)
+//Bit 31:0, head_baddr unsigned, default = 32'h00;
+#define AFBCE_MIF_SIZE ((0x41a5 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:28, ddr_blk_size unsigned, default = 1;
+//Bit 27, reserved
+//Bit 26:24, cmd_blk_size unsigned, default = 3;
+//Bit 23:21, reserved
+//Bit 20:16, uncmp_size unsigned, default = 20;
+//Bit 15:0, mmu_page_size unsigned, default = 4096;
+#define AFBCE_PIXEL_IN_HOR_SCOPE ((0x41a6 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, enc_win_end_h unsigned, default = 1919 ; //
+//Bit 15:13, reserved
+//Bit 12:0, enc_win_bgn_h unsigned, default = 0 ; //
+#define AFBCE_PIXEL_IN_VER_SCOPE ((0x41a7 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, enc_win_end_v unsigned, default = 1079 ; //
+//Bit 15:13, reserved
+//Bit 12:0, enc_win_bgn_v unsigned, default = 0 ; //
+#define AFBCE_CONV_CTRL ((0x41a8 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, fmt_ybuf_depth unsigned, default = 2048
+//Bit 15:12, reserved
+//Bit 11: 0, lbuf_depth unsigned, default = 256, unit=16 pixel need to set = 2^n
+#define AFBCE_MIF_HOR_SCOPE ((0x41a9 << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25:16, blk_end_h unsigned, default = 0 ; //
+//Bit 15:10, reserved
+//Bit 9:0, blk_bgn_h unsigned, default = 59 ; //
+#define AFBCE_MIF_VER_SCOPE ((0x41aa << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, blk_end_v unsigned, default = 0 ; //
+//Bit 15:12, reserved
+//Bit 11:0, blk_bgn_v unsigned, default = 269 ; //
+#define AFBCE_STAT1 ((0x41ab << 2) + 0xff000000)
+//Bit 31, ro_frm_end_pulse1 unsigned, RO,default = 0 ;frame end status
+//Bit 30:0, ro_dbg_top_info1 unsigned, RO,default = 0 ;
+#define AFBCE_STAT2 ((0x41ac << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30:0, ro_dbg_top_info2 unsigned, RO,default = 0 ;
+#define AFBCE_FORMAT ((0x41ad << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11:10 reserved
+//Bit 9: 8 reg_format_mode // unsigned , RW, default = 2 data format;0 : YUV444, 1:YUV422, 2:YUV420, 3:RGB
+//Bit 7: 4 reg_compbits_c // unsigned , RW, default = 10 chroma bitwidth
+//Bit 3: 0 reg_compbits_y // unsigned , RW, default = 10 luma bitwidth
+#define AFBCE_MODE_EN ((0x41ae << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 reserved
+//Bit 25 reg_adpt_interleave_ymode // unsigned , RW, default = 0 force 0 to disable it: no HW implementation
+//Bit 24 reg_adpt_interleave_cmode // unsigned , RW, default = 0 force 0 to disable it: not HW implementation
+//Bit 23 reg_adpt_yinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
+//Bit 22 reg_adpt_yinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
+//Bit 21 reg_adpt_xinterleave_luma_ride // unsigned , RW, default = 1 vertical interleave piece luma reorder ride; 0: no reorder ride; 1: w/4 as ride
+//Bit 20 reg_adpt_xinterleave_chrm_ride // unsigned , RW, default = 1 vertical interleave piece chroma reorder ride; 0: no reorder ride; 1: w/2 as ride
+//Bit 19 reserved
+//Bit 18 reg_disable_order_mode_i_6 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 17 reg_disable_order_mode_i_5 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 16 reg_disable_order_mode_i_4 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 15 reg_disable_order_mode_i_3 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 14 reg_disable_order_mode_i_2 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 13 reg_disable_order_mode_i_1 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 12 reg_disable_order_mode_i_0 // unsigned , RW, default = 0 disable order mode0~6: each mode with one disable bit: 0: no disable, 1: diable
+//Bit 11 reserved
+//Bit 10 reg_minval_yenc_en // unsigned , RW, default = 0 force disable, final decision to remove this ws 1% performance loss
+//Bit 9 reg_16x4block_enable // unsigned , RW, default = 0 block as mission, but permit 16x4 block
+//Bit 8 reg_uncompress_split_mode // unsigned , RW, default = 0 0: no split; 1: split
+//Bit 7: 6 reserved
+//Bit 5 reg_input_padding_uv128 // unsigned , RW, default = 0 input picture 32x4 block gap mode: 0: pad uv=0; 1: pad uv=128
+//Bit 4 reg_dwds_padding_uv128 // unsigned , RW, default = 0 downsampled image for double write 32x gap mode: 0: pad uv=0; 1: pad uv=128
+//Bit 3: 1 reg_force_order_mode_value // unsigned , RW, default = 0 force order mode 0~7
+//Bit 0 reg_force_order_mode_en // unsigned , RW, default = 0 force order mode enable: 0: no force; 1: forced to force_value
+#define AFBCE_DWSCALAR ((0x41af << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7: 6 reg_dwscalar_w0 // unsigned , RW, default = 3 horizontal 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 5: 4 reg_dwscalar_w1 // unsigned , RW, default = 0 horizontal 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 3: 2 reg_dwscalar_h0 // unsigned , RW, default = 2 vertical 1st step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+//Bit 1: 0 reg_dwscalar_h1 // unsigned , RW, default = 3 vertical 2nd step scalar mode: 0: 1:1 no scalar; 1: 2:1 data drop (0,2,4, 6) pixel kept; 2: 2:1 data drop (1, 3, 5,7..) pixels kept; 3: avg
+#define AFBCE_DEFCOLOR_1 ((0x41b0 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_enc_defalutcolor_3 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr]
+//Bit 11: 0 reg_enc_defalutcolor_0 // unsigned , RW, default = 4095 Picture wise default color value in [Y Cb Cr]
+#define AFBCE_DEFCOLOR_2 ((0x41b1 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_enc_defalutcolor_2 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr]
+//Bit 11: 0 reg_enc_defalutcolor_1 // unsigned , RW, default = 2048 wise default color value in [Y Cb Cr]
+#define AFBCE_QUANT_ENABLE ((0x41b2 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_quant_expand_en_1 // unsigned , RW, default = 0 enable for quantization value expansion
+//Bit 10 reg_quant_expand_en_0 // unsigned , RW, default = 0 enable for quantization value expansion
+//Bit 9: 8 reg_bcleav_ofst // signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1;
+//Bit 7: 5 reserved
+//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy
+//Bit 3: 1 reserved
+//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy
+#define AFBCE_IQUANT_LUT_1 ((0x41b3 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCE_IQUANT_LUT_2 ((0x41b4 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCE_IQUANT_LUT_3 ((0x41b5 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCE_IQUANT_LUT_4 ((0x41b6 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCE_RQUANT_LUT_1 ((0x41b7 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_rquant_yclut_0_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting)
+//Bit 27 reserved
+//Bit 26:24 reg_rquant_yclut_0_10 // unsigned , RW, default = 5
+//Bit 23 reserved
+//Bit 22:20 reg_rquant_yclut_0_9 // unsigned , RW, default = 4
+//Bit 19 reserved
+//Bit 18:16 reg_rquant_yclut_0_8 // unsigned , RW, default = 4
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_0_7 // unsigned , RW, default = 3
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_0_6 // unsigned , RW, default = 3
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_0_5 // unsigned , RW, default = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_0_4 // unsigned , RW, default = 2
+#define AFBCE_RQUANT_LUT_2 ((0x41b8 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_0_3 // unsigned , RW, default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_0_2 // unsigned , RW, default = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_0_1 // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_0_0 // unsigned , RW, default = 0
+#define AFBCE_RQUANT_LUT_3 ((0x41b9 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_rquant_yclut_1_11 // unsigned , RW, default = 5 quantization lut for bctree leavs, quant=2^lut(bc_leav_r+1), can be calculated from iquant_yclut(fw_setting)
+//Bit 27 reserved
+//Bit 26:24 reg_rquant_yclut_1_10 // unsigned , RW, default = 5
+//Bit 23 reserved
+//Bit 22:20 reg_rquant_yclut_1_9 // unsigned , RW, default = 4
+//Bit 19 reserved
+//Bit 18:16 reg_rquant_yclut_1_8 // unsigned , RW, default = 4
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_1_7 // unsigned , RW, default = 3
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_1_6 // unsigned , RW, default = 3
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_1_5 // unsigned , RW, default = 2
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_1_4 // unsigned , RW, default = 2
+#define AFBCE_RQUANT_LUT_4 ((0x41ba << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_rquant_yclut_1_3 // unsigned , RW, default = 1
+//Bit 11 reserved
+//Bit 10: 8 reg_rquant_yclut_1_2 // unsigned , RW, default = 1
+//Bit 7 reserved
+//Bit 6: 4 reg_rquant_yclut_1_1 // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_rquant_yclut_1_0 // unsigned , RW, default = 0
+#define AFBCE_YUV_FORMAT_CONV_MODE ((0x41bb << 2) + 0xff000000)
+//Bit 31: 8 reserved
+//Bit 7 reserved
+//Bit 6: 4 reg_444to422_mode // unsigned , RW, default = 0
+//Bit 3 reserved
+//Bit 2: 0 reg_422to420_mode // unsigned , RW, default = 0
+#define AFBCE_DUMMY_DATA ((0x41bc << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29: 0 reg_dummy_data // unsigned , default = 0 ;
+#define AFBCE_CLR_FLAG ((0x41bd << 2) + 0xff000000)
+//Bit 31:0 reg_afbce_clr_flag // unsigned, default = 0 ;
+#define AFBCE_STA_FLAGT ((0x41be << 2) + 0xff000000)
+//Bit 31:0 ro_afbce_sta_flag // unsigned, RO,default = 0 ;
+#define AFBCE_MMU_NUM ((0x41bf << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15: 0 ro_frm_mmu_num // unsigned, RO,default = 0 ;
+#define AFBCE_MMU_RMIF_CTRL1 ((0x41c0 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_sync_sel // unsigned , default = 0, axi canvas id sync with frm rst
+//Bit 23:16 reg_canvas_id // unsigned , default = 0, axi canvas id num
+//Bit 15 reserved
+//Bit 14:12 reg_cmd_intr_len // unsigned , default = 1, interrupt send cmd when how many series axi cmd,
+ // 0=12 1=16 2=24 3=32 4=40 5=48 6=56 7=64
+//Bit 11:10 reg_cmd_req_size // unsigned , default = 1, how many room fifo have, then axi send series req, 0=16 1=32 2=24 3=64
+//Bit 9:8 reg_burst_len // unsigned , default = 2, burst type: 0-single 1-bst2 2-bst4
+//Bit 7 reg_swap_64bit // unsigned , default = 0, 64bits of 128bit swap enable
+//Bit 6 reg_little_endian // unsigned , default = 0, big endian enable
+//Bit 5 reg_y_rev // unsigned , default = 0, vertical reverse enable
+//Bit 4 reg_x_rev // unsigned , default = 0, horizontal reverse enable
+//Bit 3 reserved
+//Bit 2:0 reg_pack_mode // unsigned , default = 3, 0:4bit 1:8bit 2:16bit 3:32bit 4:64bit 5:128bit
+#define AFBCE_MMU_RMIF_CTRL2 ((0x41c1 << 2) + 0xff000000)
+//Bit 31:30 reg_sw_rst // unsigned , default = 0,
+//Bit 29:24 reserved
+//Bit 23:18 reg_gclk_ctrl
+//Bit 17 reserved
+//Bit 16:0 reg_urgent_ctrl // unsigned , default = 0, urgent control reg :
+ // 16 reg_ugt_init : urgent initial value
+ // 15 reg_ugt_en : urgent enable
+ // 14 reg_ugt_type : 1= wrmif 0=rdmif
+ // 7:4 reg_ugt_top_th: urgent top threshold
+ // 3:0 reg_ugt_bot_th: urgent bottom threshold
+#define AFBCE_MMU_RMIF_CTRL3 ((0x41c2 << 2) + 0xff000000)
+//Bit 31:17 reserved
+//Bit 16 reg_acc_mode // unsigned , default = 1,
+//Bit 15:13 reserved
+//Bit 12:0 reg_stride // unsigned , default = 4096,
+#define AFBCE_MMU_RMIF_CTRL4 ((0x41c3 << 2) + 0xff000000)
+//Bit 31:0 reg_baddr // unsigned , default = 0,
+#define AFBCE_MMU_RMIF_SCOPE_X ((0x41c4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_x_end // unsigned , default = 4095, the canvas hor end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_x_start // unsigned , default = 0, the canvas hor start pixel position
+#define AFBCE_MMU_RMIF_SCOPE_Y ((0x41c5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_y_end // unsigned , default = 0, the canvas ver end pixel position
+//Bit 15:13 reserved
+//Bit 12: 0 reg_y_start // unsigned , default = 0, the canvas ver start pixel positio
+#define AFBCE_MMU_RMIF_RO_STAT ((0x41c6 << 2) + 0xff000000)
+//Bit 15:0 reg_status // unsigned ,
+#define AFBCE_PIP_CTRL ((0x41ca << 2) + 0xff000000)
+//Bit 31:3 reserved
+//Bit 2 reg_enc_align_en //unsigned , RW,default = 1,
+//Bit 1 reg_pip_ini_ctrl //unsigned , RW,default = 0,
+//Bit 0 reg_pip_mode //unsigned , RW,default = 0,
+#define AFBCE_ROT_CTRL ((0x41cb << 2) + 0xff000000)
+//Bit 31:5 reserved
+//Bit 4 reg_rot_en //unsigned , RW,default = 0, rotation enable
+//Bit 3:0 reg_vstep //unsigned , RW,default = 8, rotation vstep ,setting acorrding rotation shrink mode
+#define AFBCE_DIMM_CTRL ((0x41cc << 2) + 0xff000000)
+//Bit 31 reg_dimm_layer_en //unsigned , RW,default = 0,dimm_layer enable singal
+//Bit 30 reserved
+//Bit 29:0 reg_dimm_data //unsigned , RW,default = 29'h00080200,dimm_layer data
+#define AFBCE_BND_DEC_MISC ((0x41cd << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 bnd_dec_rev_mode //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 25:24 bnd_dec_mif_urgent //unsigned , RW,default = 3 only pip mode use those bits,ususaly don't need configure
+//Bit 23:22 bnd_dec_burst_len //unsigned , RW,default = 2 only pip mode use those bits,ususaly don't need configure
+//Bit 21:20 bnd_dec_ddr_blk_size //unsigned , RW,default = 1 only pip mode use those bits,ususaly don't need configure
+//Bit 19 reserved
+//Bit 18:16 bnd_dec_cmd_blk_size //unsigned , RW,default = 3 only pip mode use those bits,ususaly don't need configure
+//Bit 15 reserved
+//Bit 14 bnd_dec_blk_mem_mode //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 13 bnd_dec_addr_link_en //unsigned , RW,default = 1 only pip mode use those bits,ususaly don't need configure
+//Bit 12 bnd_dec_always_body_rden //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 11:0 bnd_dec_mif_lbuf_depth //unsigned , RW,default = 128 only pip mode use those bits,ususaly don't need configure
+#define AFBCE_RD_ARB_MISC ((0x41ce << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12 reg_arb_sw_rst //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 11:10 reserved
+//Bit 9 reg_arb_arblk_last1 //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 8 reg_arb_arblk_last0 //unsigned , RW,default = 0 only pip mode use those bits,ususaly don't need configure
+//Bit 7:4 reg_arb_weight_ch1 //unsigned , RW,default = 4 only pip mode use those bits,ususaly don't need configure
+//Bit 3:0 reg_arb_weight_ch0 //unsigned , RW,default = 10 only pip mode use those bits,ususaly don't need configure
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vdin_afbc_enc_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vdin_afbce_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: DOLBYTV_VCBUS_BASE = 0x43
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: dolby_tv_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DOLBY_TV_REG_START ((0x4300 << 2) + 0xff000000)
+// dolby register address 0~0xDA
+#define DOLBY_TV_CLKGATE_CTRL ((0x43f1 << 2) + 0xff000000)
+//bit[9:8] R-RW 0~3 0 dma2axi_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock"
+//bit[7:6] R-RW 0~3 0 bl_dolby_swaps_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock"
+//bit[5:4] R-RW 0~3 0 el_swaps_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock"
+//bit[3:2] R-RW 0~3 0 el_buf_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock"
+//bit[1:0] R-RW 0~3 0 top_level_reg_clkgate_ctrl : 0 "auto gated clock", 1 "closed clock", 2&3 "free run clock"
+#define DOLBY_TV_SWAP_CTRL0 ((0x43f2 << 2) + 0xff000000)
+//bit[2] R-RW 0~1 0 el_41mode : 1 "bl resolution : el resolution = 4:1", 0 "bl_res : el_res = 1:1"
+//bit[1] R-RW 0~1 0 el_enable : 1 "enhancement layer is supported", 0 "el is not supported"
+//bit[0] R-RW 0~1 0 source_enable : 1 "base layer is supported", 0 "bl is not supported"
+#define DOLBY_TV_SWAP_CTRL1 ((0x43f3 << 2) + 0xff000000)
+//bit[28:16] R-RW 0~8191 0 htotal : total pixels number in each line
+//bit[21:0] R-RW 0~8191 0 vtotal : total line number in each frame (only support progress frame)
+#define DOLBY_TV_SWAP_CTRL2 ((0x43f4 << 2) + 0xff000000)
+//bit[28:16] R-RW 0~4096 0 hsize : active pixels number in each line
+//bit[21:0] R-RW 0~3840 0 vsize : active lines number in each frame
+#define DOLBY_TV_SWAP_CTRL3 ((0x43f5 << 2) + 0xff000000)
+//bit[28:16] R-RW 0~8191 0 hsync_width : hsync signal width (high effective)
+//bit[21:0] R-RW 0~8191 0 vsync_width : vysnc singal width (high effective)
+#define DOLBY_TV_SWAP_CTRL4 ((0x43f6 << 2) + 0xff000000)
+//bit[28:16] R-RW 0~8191 0 hsync_backporch : pixels number between hsync and h_active_duration
+//bit[21:0] R-RW 0~8191 0 vsync_backporch : lines number between vsync and v_active_duration
+#define DOLBY_TV_SWAP_CTRL5 ((0x43f7 << 2) + 0xff000000)
+//[25:8] R-RW : reg_tunnel_sel for tunnel bit match swap
+//bit[4] R-RW 0~1 0 bl_tunnel_mode : 1 "hdmi input, source is 12bit422 tunnel in 8bit444", 0 "opt mode, 10 bit 444"
+//bit[3:2] R-RW 0~3 0 bl_uv_mode : 3 "uv=in_u", 2 "uv[0]=u[0],uv[1]=v[0]", 1 "uv[0]=v[0],uv[1]=u[0]", 0 "uv=in_v"
+//bit[1:0] R-RW 0~3 0 el_uv_mode : 3 "uv=in_u", 2 "uv[0]=u[0],uv[1]=v[0]", 1 "uv[0]=v[0],uv[1]=u[0]", 0 "uv=in_v"
+#define DOLBY_TV_SWAP_CTRL6 ((0x43f8 << 2) + 0xff000000)
+//bit[31] R-RW 0~1 dm_uv_input : uv select
+//bit[23:16] R-RW 0~1 0 dump_ctrl : 1 "fixed output bitdepth as 12bit", 0 "output bitdepth based on vdr_bit_depth"
+//bit[15] R-RW 0~1 datapath_reset_n_enable : manual reset control
+//bit[14] R-RW 0~1 handshake_reset_n_enable : manual reset control
+//bit[13] R-RW 0~1 axi_reset_n_enable : manual reset control
+//bit[5:2] R-RW 0~15 vdr_bit_depth
+//bit[1:0] R-RW 0~3 reg_hdmi_mode
+#define DOLBY_TV_SWAP_CTRL7 ((0x43f9 << 2) + 0xff000000)
+//reserved
+#define DOLBY_TV_AXI2DMA_CTRL0 ((0x43fa << 2) + 0xff000000)
+//bit[31] R-RW 0~1 0 reg_req_en : enable req after line count
+//bit[30] R-RW 0~1 0 reg_id_check : check the id of data path and req path
+//bit[29] R-RW 0~1 0 reg_clear_fifo : manually reset bit
+//bit[28] R-RW 0~1 0 reg_vsync_rst : soft_rst auto reset enable
+//bit[27] R-RW 0~1 0 reg_update_addr : manually udpate start addr
+//bit[26] R-RW 0~1 0 reg_addr_auto : auto update start addr enable
+//bit[25] R-RW 0~1 0 reg_keep_receive : data path keep receive
+//bit[24:19] R-RW 0~63 0 reg_req_th : fifo_room > req_th, then send the request
+//bit[18:16] R-RW 0~7 0 reg_arsize : axi arsize
+//bit[14:12] R-RW 0~7 0 reg_arprot : axi arprot
+//bit[11:8] R-RW 0~15 0 reg_aruser : axi aruser
+//bit[5:4] R-RW 0~3 0 reg_arid : axi arid
+//bit[3:0] R-RW 0~2 0 reg_lens : default request lens, each burst has "reg_lens+1" data
+#define DOLBY_TV_AXI2DMA_CTRL1 ((0x43fb << 2) + 0xff000000)
+//bit[31] R-RW 0~1 0 axi_addr_mode : 1 "canvas mode", 0 "normal mode"
+//bit[27:16] R-RW 0~4095 0 dma_size0 : total data number in dma0
+//bit[11:0] R-RW 0~4095 0 dma_size1 : total data number in dma1
+#define DOLBY_TV_AXI2DMA_CTRL2 ((0x43fc << 2) + 0xff000000)
+//bit[31:0] R-RW 0~4294967295 0 axi_start_addr : axi start address
+#define DOLBY_TV_AXI2DMA_CTRL3 ((0x43fd << 2) + 0xff000000)
+//bit[11:0] R-RW 0~4095 0 hold_line : after hold_line the axi slave start requesting
+#define DOLBY_TV_STATUS0 ((0x43fe << 2) + 0xff000000)
+#define DOLBY_TV_STATUS1 ((0x43ff << 2) + 0xff000000)
+#define DOLBY_TV_ADAPTIVE_SCALE_REGADDR ((0x43e0 << 2) + 0xff000000)
+#define DOLBY_TV_ADAPTIVE_SCALE_REGDATA ((0x43e1 << 2) + 0xff000000)
+#define DOLBY_TV_ADAPTIVE_SCALE_LUTADDR ((0x43e2 << 2) + 0xff000000)
+#define DOLBY_TV_ADAPTIVE_SCALE_LUTDATA ((0x43e3 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dolby_tv_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: DOLBY1B_VCBUS_BASE = 0x44
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: dolby1b_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DOLBY_CORE1B_REG_START ((0x4400 << 2) + 0xff000000)
+#define DOLBY_CORE1B_CLKGATE_CTRL ((0x44f2 << 2) + 0xff000000)
+#define DOLBY_CORE1B_SWAP_CTRL0 ((0x44f3 << 2) + 0xff000000)
+#define DOLBY_CORE1B_SWAP_CTRL1 ((0x44f4 << 2) + 0xff000000)
+#define DOLBY_CORE1B_SWAP_CTRL2 ((0x44f5 << 2) + 0xff000000)
+#define DOLBY_CORE1B_SWAP_CTRL3 ((0x44f6 << 2) + 0xff000000)
+#define DOLBY_CORE1B_SWAP_CTRL4 ((0x44f7 << 2) + 0xff000000)
+#define DOLBY_CORE1B_SWAP_CTRL5 ((0x44f8 << 2) + 0xff000000)
+#define DOLBY_CORE1B_DMA_CTRL ((0x44f9 << 2) + 0xff000000)
+#define DOLBY_CORE1B_DMA_STATUS ((0x44fa << 2) + 0xff000000)
+#define DOLBY_CORE1B_STATUS0 ((0x44fb << 2) + 0xff000000)
+#define DOLBY_CORE1B_STATUS1 ((0x44fc << 2) + 0xff000000)
+#define DOLBY_CORE1B_STATUS2 ((0x44fd << 2) + 0xff000000)
+#define DOLBY_CORE1B_STATUS3 ((0x44fe << 2) + 0xff000000)
+#define DOLBY_CORE1B_DMA_PORT ((0x44ff << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dolby1b_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VPP_VD12_VCBUS_BASE = 0x48
+// -----------------------------------------------
+//===========================================================================
+//`include "afbcd_mult_regs.h"
+//
+// Reading file: afbcd_vd12_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+// reg addr map
+// 0 -3f : rdmif
+// 40-6f : afbcd
+// 70-7f : fgrain
+////===============================////
+#define VD1_IF0_GEN_REG ((0x4800 << 2) + 0xff000000)
+#define VD1_IF0_CANVAS0 ((0x4801 << 2) + 0xff000000)
+#define VD1_IF0_CANVAS1 ((0x4802 << 2) + 0xff000000)
+#define VD1_IF0_LUMA_X0 ((0x4803 << 2) + 0xff000000)
+#define VD1_IF0_LUMA_Y0 ((0x4804 << 2) + 0xff000000)
+#define VD1_IF0_CHROMA_X0 ((0x4805 << 2) + 0xff000000)
+#define VD1_IF0_CHROMA_Y0 ((0x4806 << 2) + 0xff000000)
+#define VD1_IF0_LUMA_X1 ((0x4807 << 2) + 0xff000000)
+#define VD1_IF0_LUMA_Y1 ((0x4808 << 2) + 0xff000000)
+#define VD1_IF0_CHROMA_X1 ((0x4809 << 2) + 0xff000000)
+#define VD1_IF0_CHROMA_Y1 ((0x480a << 2) + 0xff000000)
+#define VD1_IF0_RPT_LOOP ((0x480b << 2) + 0xff000000)
+#define VD1_IF0_LUMA0_RPT_PAT ((0x480c << 2) + 0xff000000)
+#define VD1_IF0_CHROMA0_RPT_PAT ((0x480d << 2) + 0xff000000)
+#define VD1_IF0_LUMA1_RPT_PAT ((0x480e << 2) + 0xff000000)
+#define VD1_IF0_CHROMA1_RPT_PAT ((0x480f << 2) + 0xff000000)
+#define VD1_IF0_LUMA_PSEL ((0x4810 << 2) + 0xff000000)
+#define VD1_IF0_CHROMA_PSEL ((0x4811 << 2) + 0xff000000)
+#define VD1_IF0_DUMMY_PIXEL ((0x4812 << 2) + 0xff000000)
+#define VD1_IF0_LUMA_FIFO_SIZE ((0x4813 << 2) + 0xff000000)
+#define VD1_IF0_AXI_CMD_CNT ((0x4814 << 2) + 0xff000000)
+#define VD1_IF0_AXI_RDAT_CNT ((0x4815 << 2) + 0xff000000)
+#define VD1_IF0_RANGE_MAP_Y ((0x4816 << 2) + 0xff000000)
+#define VD1_IF0_RANGE_MAP_CB ((0x4817 << 2) + 0xff000000)
+#define VD1_IF0_RANGE_MAP_CR ((0x4818 << 2) + 0xff000000)
+#define VD1_IF0_GEN_REG2 ((0x4819 << 2) + 0xff000000)
+#define VD1_IF0_PROT ((0x481a << 2) + 0xff000000)
+#define VD1_IF0_URGENT_CTRL ((0x481b << 2) + 0xff000000)
+#define VD1_IF0_GEN_REG3 ((0x481c << 2) + 0xff000000)
+#define VIU_VD1_FMT_CTRL ((0x481d << 2) + 0xff000000)
+#define VIU_VD1_FMT_W ((0x481e << 2) + 0xff000000)
+#define VD1_IF0_BADDR_Y ((0x4820 << 2) + 0xff000000)
+#define VD1_IF0_BADDR_CB ((0x4821 << 2) + 0xff000000)
+#define VD1_IF0_BADDR_CR ((0x4822 << 2) + 0xff000000)
+#define VD1_IF0_STRIDE_0 ((0x4823 << 2) + 0xff000000)
+#define VD1_IF0_STRIDE_1 ((0x4824 << 2) + 0xff000000)
+#define VD1_IF0_BADDR_Y_F1 ((0x4825 << 2) + 0xff000000)
+#define VD1_IF0_BADDR_CB_F1 ((0x4826 << 2) + 0xff000000)
+#define VD1_IF0_BADDR_CR_F1 ((0x4827 << 2) + 0xff000000)
+#define VD1_IF0_STRIDE_0_F1 ((0x4828 << 2) + 0xff000000)
+#define VD1_IF0_STRIDE_1_F1 ((0x4829 << 2) + 0xff000000)
+//8'h28-8'h6f for vd1_afbcd
+//8'h70-8'h7f for vd1_fgrain
+#define VD2_IF0_GEN_REG ((0x4880 << 2) + 0xff000000)
+#define VD2_IF0_CANVAS0 ((0x4881 << 2) + 0xff000000)
+#define VD2_IF0_CANVAS1 ((0x4882 << 2) + 0xff000000)
+#define VD2_IF0_LUMA_X0 ((0x4883 << 2) + 0xff000000)
+#define VD2_IF0_LUMA_Y0 ((0x4884 << 2) + 0xff000000)
+#define VD2_IF0_CHROMA_X0 ((0x4885 << 2) + 0xff000000)
+#define VD2_IF0_CHROMA_Y0 ((0x4886 << 2) + 0xff000000)
+#define VD2_IF0_LUMA_X1 ((0x4887 << 2) + 0xff000000)
+#define VD2_IF0_LUMA_Y1 ((0x4888 << 2) + 0xff000000)
+#define VD2_IF0_CHROMA_X1 ((0x4889 << 2) + 0xff000000)
+#define VD2_IF0_CHROMA_Y1 ((0x488a << 2) + 0xff000000)
+#define VD2_IF0_RPT_LOOP ((0x488b << 2) + 0xff000000)
+#define VD2_IF0_LUMA0_RPT_PAT ((0x488c << 2) + 0xff000000)
+#define VD2_IF0_CHROMA0_RPT_PAT ((0x488d << 2) + 0xff000000)
+#define VD2_IF0_LUMA1_RPT_PAT ((0x488e << 2) + 0xff000000)
+#define VD2_IF0_CHROMA1_RPT_PAT ((0x488f << 2) + 0xff000000)
+#define VD2_IF0_LUMA_PSEL ((0x4890 << 2) + 0xff000000)
+#define VD2_IF0_CHROMA_PSEL ((0x4891 << 2) + 0xff000000)
+#define VD2_IF0_DUMMY_PIXEL ((0x4892 << 2) + 0xff000000)
+#define VD2_IF0_LUMA_FIFO_SIZE ((0x4893 << 2) + 0xff000000)
+#define VD2_IF0_AXI_CMD_CNT ((0x4894 << 2) + 0xff000000)
+#define VD2_IF0_AXI_RDAT_CNT ((0x4895 << 2) + 0xff000000)
+#define VD2_IF0_RANGE_MAP_Y ((0x4896 << 2) + 0xff000000)
+#define VD2_IF0_RANGE_MAP_CB ((0x4897 << 2) + 0xff000000)
+#define VD2_IF0_RANGE_MAP_CR ((0x4898 << 2) + 0xff000000)
+#define VD2_IF0_GEN_REG2 ((0x4899 << 2) + 0xff000000)
+#define VD2_IF0_PROT ((0x489a << 2) + 0xff000000)
+#define VD2_IF0_URGENT_CTRL ((0x489b << 2) + 0xff000000)
+#define VD2_IF0_GEN_REG3 ((0x489c << 2) + 0xff000000)
+#define VIU_VD2_FMT_CTRL ((0x489d << 2) + 0xff000000)
+#define VIU_VD2_FMT_W ((0x489e << 2) + 0xff000000)
+#define VD2_IF0_BADDR_Y ((0x48a0 << 2) + 0xff000000)
+#define VD2_IF0_BADDR_CB ((0x48a1 << 2) + 0xff000000)
+#define VD2_IF0_BADDR_CR ((0x48a2 << 2) + 0xff000000)
+#define VD2_IF0_STRIDE_0 ((0x48a3 << 2) + 0xff000000)
+#define VD2_IF0_STRIDE_1 ((0x48a4 << 2) + 0xff000000)
+#define VD2_IF0_BADDR_Y_F1 ((0x48a5 << 2) + 0xff000000)
+#define VD2_IF0_BADDR_CB_F1 ((0x48a6 << 2) + 0xff000000)
+#define VD2_IF0_BADDR_CR_F1 ((0x48a7 << 2) + 0xff000000)
+#define VD2_IF0_STRIDE_0_F1 ((0x48a8 << 2) + 0xff000000)
+#define VD2_IF0_STRIDE_1_F1 ((0x48a9 << 2) + 0xff000000)
+//8'hb8-8'hef for vd2_afbcd
+//8'hf0-8'hff for vd2_fgrain
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: afbcd_vd12_regs.h
+//
+//`include "fgrain_regs.h" //nouse
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VPP_VD34_VCBUS_BASE = 0x49
+// -----------------------------------------------
+//===========================================================================
+//`include "afbcd_mult_regs.h"
+//
+// Reading file: afbcd_vd34_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+// reg addr map
+// 0 -3f : rdmif
+// 40-6f : afbcd
+// 70-7f : fgrain
+////===============================////
+#define VD3_IF0_GEN_REG ((0x4900 << 2) + 0xff000000)
+#define VD3_IF0_CANVAS0 ((0x4901 << 2) + 0xff000000)
+#define VD3_IF0_CANVAS1 ((0x4902 << 2) + 0xff000000)
+#define VD3_IF0_LUMA_X0 ((0x4903 << 2) + 0xff000000)
+#define VD3_IF0_LUMA_Y0 ((0x4904 << 2) + 0xff000000)
+#define VD3_IF0_CHROMA_X0 ((0x4905 << 2) + 0xff000000)
+#define VD3_IF0_CHROMA_Y0 ((0x4906 << 2) + 0xff000000)
+#define VD3_IF0_LUMA_X1 ((0x4907 << 2) + 0xff000000)
+#define VD3_IF0_LUMA_Y1 ((0x4908 << 2) + 0xff000000)
+#define VD3_IF0_CHROMA_X1 ((0x4909 << 2) + 0xff000000)
+#define VD3_IF0_CHROMA_Y1 ((0x490a << 2) + 0xff000000)
+#define VD3_IF0_RPT_LOOP ((0x490b << 2) + 0xff000000)
+#define VD3_IF0_LUMA0_RPT_PAT ((0x490c << 2) + 0xff000000)
+#define VD3_IF0_CHROMA0_RPT_PAT ((0x490d << 2) + 0xff000000)
+#define VD3_IF0_LUMA1_RPT_PAT ((0x490e << 2) + 0xff000000)
+#define VD3_IF0_CHROMA1_RPT_PAT ((0x490f << 2) + 0xff000000)
+#define VD3_IF0_LUMA_PSEL ((0x4910 << 2) + 0xff000000)
+#define VD3_IF0_CHROMA_PSEL ((0x4911 << 2) + 0xff000000)
+#define VD3_IF0_DUMMY_PIXEL ((0x4912 << 2) + 0xff000000)
+#define VD3_IF0_LUMA_FIFO_SIZE ((0x4913 << 2) + 0xff000000)
+#define VD3_IF0_AXI_CMD_CNT ((0x4914 << 2) + 0xff000000)
+#define VD3_IF0_AXI_RDAT_CNT ((0x4915 << 2) + 0xff000000)
+#define VD3_IF0_RANGE_MAP_Y ((0x4916 << 2) + 0xff000000)
+#define VD3_IF0_RANGE_MAP_CB ((0x4917 << 2) + 0xff000000)
+#define VD3_IF0_RANGE_MAP_CR ((0x4918 << 2) + 0xff000000)
+#define VD3_IF0_GEN_REG2 ((0x4919 << 2) + 0xff000000)
+#define VD3_IF0_PROT ((0x491a << 2) + 0xff000000)
+#define VD3_IF0_URGENT_CTRL ((0x491b << 2) + 0xff000000)
+#define VD3_IF0_GEN_REG3 ((0x491c << 2) + 0xff000000)
+#define VIU_VD3_FMT_CTRL ((0x491d << 2) + 0xff000000)
+#define VIU_VD3_FMT_W ((0x491e << 2) + 0xff000000)
+#define VD3_IF0_BADDR_Y ((0x4920 << 2) + 0xff000000)
+#define VD3_IF0_BADDR_CB ((0x4921 << 2) + 0xff000000)
+#define VD3_IF0_BADDR_CR ((0x4922 << 2) + 0xff000000)
+#define VD3_IF0_STRIDE_0 ((0x4923 << 2) + 0xff000000)
+#define VD3_IF0_STRIDE_1 ((0x4924 << 2) + 0xff000000)
+#define VD3_IF0_BADDR_Y_F1 ((0x4925 << 2) + 0xff000000)
+#define VD3_IF0_BADDR_CB_F1 ((0x4926 << 2) + 0xff000000)
+#define VD3_IF0_BADDR_CR_F1 ((0x4927 << 2) + 0xff000000)
+#define VD3_IF0_STRIDE_0_F1 ((0x4928 << 2) + 0xff000000)
+#define VD3_IF0_STRIDE_1_F1 ((0x4929 << 2) + 0xff000000)
+//8'h28-8'h6f for vd3_afbcd
+//8'h70-8'h7f for vd3_fgrain
+//8'h80-8'hff reserved
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: afbcd_vd34_regs.h
+//
+//`include "fgrain_regs.h" //nouse
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VPPC_VCBUS_BASE = 0x50
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: srsharp_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//SRSHARP0 8'h00 - 8'hff
+//SRSHARP1 8'h100 - 8'1ff
+#define SRSHARP0_OFFSET (0x000<<2)
+#define SRSHARP1_OFFSET (0x200<<2)
+
+//
+// Reading file: sharp_regs.h
+//
+#define SHARP_HVSIZE ((0x5000 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_pknr_hsize . unsigned , default = 1920
+//Bit 15:13, reserved
+//Bit 12: 0, reg_pknr_vsize . unsigned , default = 1080
+#define SHARP_HVBLANK_NUM ((0x5001 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_deband_hblank
+//Bit 15: 8, reg_pknr_hblank_num . unsigned , default = 20
+//Bit 7: 0, reg_pknr_vblank_num . unsigned , default = 73
+#define NR_GAUSSIAN_MODE ((0x5002 << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13:12, reg_nr_gau_ynorm : C adpative coef norm, 0: 128, 1: 256, 2: 512, 3: 1024 . unsigned , default = 0
+//Bit 11:10, reserved
+//Bit 9: 8, reg_nr_gau_cnorm : C adpative coef norm, 0: 128, 1: 256, 2: 512, 3: 1024 . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 4, reg_nr_gau_ymode : 0 3x3 filter; 1: 5x5 filter; 2/3:adpative coef . unsigned , default = 1
+//Bit 3: 2, reserved
+//Bit 1: 0, reg_nr_gau_cmode : 0 3x3 filter; 1: 5x5 filter; 2/3:adpative coef . unsigned , default = 1
+#define PK_CON_2CIRHPGAIN_TH_RATE ((0x5005 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_cirhpcon2gain0 : threshold0 of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 25
+//Bit 23:16, reg_pk_cirhpcon2gain1 : threshold1 of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 60
+//Bit 15: 8, reg_pk_cirhpcon2gain5 : rate0 (for hpcon<th0) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 80
+//Bit 7: 0, reg_pk_cirhpcon2gain6 : rate1 (for hpcon>th1) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 20
+#define PK_CON_2CIRHPGAIN_LIMIT ((0x5006 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_cirhpcon2gain2 : level limit(for hpcon<th0) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 155
+//Bit 23:16, reg_pk_cirhpcon2gain3 : level limit(for th0<hpcon<th1) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 150
+//Bit 15: 8, reg_pk_cirhpcon2gain4 : level limit(for hpcon>th1) of curve to map hpcon to hpgain for circle hp filter (all 8 direction same). 0~255.. unsigned , default = 5
+//Bit 7: 0, reserved
+#define PK_CON_2CIRBPGAIN_TH_RATE ((0x5007 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_cirbpcon2gain0 : threshold0 of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 20
+//Bit 23:16, reg_pk_cirbpcon2gain1 : threshold1 of curve to map bpcon to bpgain for circle bp filter (all 8 direction same).. unsigned , default = 50
+//Bit 15: 8, reg_pk_cirbpcon2gain5 : rate0 (for bpcon<th0) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 50
+//Bit 7: 0, reg_pk_cirbpcon2gain6 : rate1 (for bpcon>th1) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 25
+#define PK_CON_2CIRBPGAIN_LIMIT ((0x5008 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_cirbpcon2gain2 : level limit(for bpcon<th0) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 155
+//Bit 23:16, reg_pk_cirbpcon2gain3 : level limit(for th0<bpcon<th1) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 150
+//Bit 15: 8, reg_pk_cirbpcon2gain4 : level limit(for bpcon>th1) of curve to map bpcon to bpgain for circle bp filter (all 8 direction same). 0~255.. unsigned , default = 5
+//Bit 7: 0, reserved
+#define PK_CON_2DRTHPGAIN_TH_RATE ((0x5009 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_drthpcon2gain0 : threshold0 of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 25
+//Bit 23:16, reg_pk_drthpcon2gain1 : threshold1 of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 60
+//Bit 15: 8, reg_pk_drthpcon2gain5 : rate0 (for hpcon<th0) of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 80
+//Bit 7: 0, reg_pk_drthpcon2gain6 : rate1 (for hpcon>th1) of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 20
+#define PK_CON_2DRTHPGAIN_LIMIT ((0x500a << 2) + 0xff000000)
+//Bit 31:24, reg_pk_drthpcon2gain2 : level limit(for hpcon<th0) of curve to map hpcon to hpgain for directional hp filter (best direction).. unsigned , default = 105
+//Bit 23:16, reg_pk_drthpcon2gain3 : level limit(for th0<hpcon<th1) of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 96
+//Bit 15: 8, reg_pk_drthpcon2gain4 : level limit(for hpcon>th1) of curve to map hpcon to hpgain for directional hp filter (best direction). 0~255.. unsigned , default = 5
+//Bit 7: 0, reserved
+#define PK_CON_2DRTBPGAIN_TH_RATE ((0x500b << 2) + 0xff000000)
+//Bit 31:24, reg_pk_drtbpcon2gain0 : threshold0 of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 20
+//Bit 23:16, reg_pk_drtbpcon2gain1 : threshold1 of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 50
+//Bit 15: 8, reg_pk_drtbpcon2gain5 : rate0 (for bpcon<th0) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 50
+//Bit 7: 0, reg_pk_drtbpcon2gain6 : rate1 (for bpcon>th1) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 25
+#define PK_CON_2DRTBPGAIN_LIMIT ((0x500c << 2) + 0xff000000)
+//Bit 31:24, reg_pk_drtbpcon2gain2 : level limit(for bpcon<th0) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 55
+//Bit 23:16, reg_pk_drtbpcon2gain3 : level limit(for th0<bpcon<th1) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 40
+//Bit 15: 8, reg_pk_drtbpcon2gain4 : level limit(for bpcon>th1) of curve to map bpcon to bpgain for directional bp filter (best direction). 0~255.. unsigned , default = 5
+//Bit 7: 0, reserved
+#define PK_CIRFB_LPF_MODE ((0x500d << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:28, reg_cirhp_horz_mode : no horz filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1
+//Bit 27:26, reserved
+//Bit 25:24, reg_cirhp_vert_mode : no vert filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1
+//Bit 23:22, reserved
+//Bit 21:20, reg_cirhp_diag_mode : filter on HP; 1: [1 2 1]/4; . unsigned , default = 1
+//Bit 19:14, reserved
+//Bit 13:12, reg_cirbp_horz_mode : no horz filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1
+//Bit 11:10, reserved
+//Bit 9: 8, reg_cirbp_vert_mode : no vert filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 . unsigned , default = 1
+//Bit 7: 6, reserved
+//Bit 5: 4, reg_cirbp_diag_mode : filter on BP; 1: [1 2 1]/4; . unsigned , default = 1
+//Bit 3: 0, reserved
+#define PK_DRTFB_LPF_MODE ((0x500e << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:28, reg_drthp_horz_mode : no horz filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1
+//Bit 27:26, reserved
+//Bit 25:24, reg_drthp_vert_mode : no vert filter on HP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1
+//Bit 23:22, reserved
+//Bit 21:20, reg_drthp_diag_mode : filter on HP; 1: [1 2 1]/4; 1 . unsigned , default = 1
+//Bit 19:14, reserved
+//Bit 13:12, reg_drtbp_horz_mode : no horz filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1
+//Bit 11:10, reserved
+//Bit 9: 8, reg_drtbp_vert_mode : no vert filter on BP; 1: [1 2 1]/4; 2/3: [1 2 2 2 1]/8 2 . unsigned , default = 1
+//Bit 7: 6, reserved
+//Bit 5: 4, reg_drtbp_diag_mode : filter on BP; 1: [1 2 1]/4; 1 . unsigned , default = 1
+//Bit 3: 0, reserved
+#define PK_CIRFB_HP_CORING ((0x500f << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, reg_cirhp_horz_core : coring of HP for Horz . unsigned , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_cirhp_vert_core : coring of HP for Vert . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_cirhp_diag_core : coring of HP for Diag . unsigned , default = 0
+#define PK_CIRFB_BP_CORING ((0x5010 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, reg_cirbp_horz_core : coring of HP for Horz . unsigned , default = 1
+//Bit 15:14, reserved
+//Bit 13: 8, reg_cirbp_vert_core : coring of HP for Vert . unsigned , default = 1
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_cirbp_diag_core : coring of HP for Diag . unsigned , default = 1
+#define PK_DRTFB_HP_CORING ((0x5011 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, reg_drthp_horz_core : coring of HP for Horz . unsigned , default = 1
+//Bit 15:14, reserved
+//Bit 13: 8, reg_drthp_vert_core : coring of HP for Vert . unsigned , default = 1
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_drthp_diag_core : coring of HP for Diag . unsigned , default = 1
+#define PK_DRTFB_BP_CORING ((0x5012 << 2) + 0xff000000)
+//Bit 31:22, reserved
+//Bit 21:16, reg_drtbp_horz_core : coring of HP for Horz . unsigned , default = 1
+//Bit 15:14, reserved
+//Bit 13: 8, reg_drtbp_vert_core : coring of HP for Vert . unsigned , default = 1
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_drtbp_diag_core : coring of HP for Diag . unsigned , default = 1
+#define PK_CIRFB_BLEND_GAIN ((0x5013 << 2) + 0xff000000)
+//Bit 31:28, reg_hp_cir_hgain : normalized 8 as '1' . unsigned , default = 8
+//Bit 27:24, reg_hp_cir_vgain : normalized 8 as '1' . unsigned , default = 8
+//Bit 23:20, reg_hp_cir_dgain : normalized 8 as '1' . unsigned , default = 8
+//Bit 19:16, reserved
+//Bit 15:12, reg_bp_cir_hgain : normalized 8 as '1' . unsigned , default = 8
+//Bit 11: 8, reg_bp_cir_vgain : normalized 8 as '1' . unsigned , default = 8
+//Bit 7: 4, reg_bp_cir_dgain : normalized 8 as '1' . unsigned , default = 8
+//Bit 3: 0, reserved
+#define NR_ALPY_SSD_GAIN_OFST ((0x5014 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_nr_alp0_ssd_gain : gain to max ssd normalized 16 as '1' . unsigned , default = 16
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_nr_alp0_ssd_ofst : offset to ssd before dividing to min_err . signed , default = -2
+#define NR_ALP0Y_ERR2CURV_TH_RATE ((0x5015 << 2) + 0xff000000)
+//Bit 31:24, reg_nr_alp0_minerr_ypar0 : threshold0 of curve to map mierr to alp0 for luma channel, this will be set value of flat region mierr that no need blur. 0~255.. unsigned , default = 10
+//Bit 23:16, reg_nr_alp0_minerr_ypar1 : threshold1 of curve to map mierr to alp0 for luma channel,this will be set value of texture region mierr that can not blur.. unsigned , default = 25
+//Bit 15: 8, reg_nr_alp0_minerr_ypar5 : rate0 (for mierr<th0) of curve to map mierr to alp0 for luma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 80
+//Bit 7: 0, reg_nr_alp0_minerr_ypar6 : rate1 (for mierr>th1) of curve to map mierr to alp0 for luma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 64
+#define NR_ALP0Y_ERR2CURV_LIMIT ((0x5016 << 2) + 0xff000000)
+//Bit 31:24, reg_nr_alp0_minerr_ypar2 : level limit(for mierr<th0) of curve to map mierr to alp0 for luma channel, this will be set to alp0 that we can do for flat region. 0~255.. unsigned , default = 63
+//Bit 23:16, reg_nr_alp0_minerr_ypar3 : level limit(for th0<mierr<th1) of curve to map mierr to alp0 for luma channel, this will be set to alp0 that we can do for misc region. 0~255.. unsigned , default = 0
+//Bit 15: 8, reg_nr_alp0_minerr_ypar4 : level limit(for mierr>th1) of curve to map mierr to alp0 for luma channel, this will be set to alp0 that we can do for texture region. 0~255.. unsigned , default = 63
+//Bit 7: 0, reserved
+#define NR_ALP0C_ERR2CURV_TH_RATE ((0x5017 << 2) + 0xff000000)
+//Bit 31:24, reg_nr_alp0_minerr_cpar0 : threshold0 of curve to map mierr to alp0 for chroma channel, this will be set value of flat region mierr that no need blur.. unsigned , default = 10
+//Bit 23:16, reg_nr_alp0_minerr_cpar1 : threshold1 of curve to map mierr to alp0 for chroma channel,this will be set value of texture region mierr that can not blur.. unsigned , default = 25
+//Bit 15: 8, reg_nr_alp0_minerr_cpar5 : rate0 (for mierr<th0) of curve to map mierr to alp0 for chroma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 80
+//Bit 7: 0, reg_nr_alp0_minerr_cpar6 : rate1 (for mierr>th1) of curve to map mierr to alp0 for chroma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 64
+#define NR_ALP0C_ERR2CURV_LIMIT ((0x5018 << 2) + 0xff000000)
+//Bit 31:24, reg_nr_alp0_minerr_cpar2 : level limit(for mierr<th0) of curve to map mierr to alp0 for chroma channel, this will be set to alp0 that we can do for flat region. 0~255.. unsigned , default = 63
+//Bit 23:16, reg_nr_alp0_minerr_cpar3 : level limit(for th0<mierr<th1) of curve to map mierr to alp0 for chroma channel, this will be set to alp0 that we can do for misc region. 0~255.. unsigned , default = 0
+//Bit 15: 8, reg_nr_alp0_minerr_cpar4 : level limit(for mierr>th1) of curve to map mierr to alp0 for chroma channel, this will be set to alp0 that we can do for texture region. 0~255.. unsigned , default = 63
+//Bit 7: 0, reserved
+#define NR_ALP0_MIN_MAX ((0x5019 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_nr_alp0_ymin : normalized to 64 as '1' . unsigned , default = 0
+//Bit 23:22, reserved
+//Bit 21:16, reg_nr_alp0_ymax : normalized to 64 as '1' . unsigned , default = 63
+//Bit 15:14, reserved
+//Bit 13: 8, reg_nr_alp0_cmin : normalized to 64 as '1' . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_nr_alp0_cmax : normalized to 64 as '1' . unsigned , default = 63
+#define NR_ALP1_MIERR_CORING ((0x501a << 2) + 0xff000000)
+//Bit 31:17, reserved
+//Bit 16, reg_nr_alp1_maxerr_mode : 0 max err; 1: xerr . unsigned , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_nr_alp1_core_rate : normalized 64 as "1" . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_nr_alp1_core_ofst : normalized 64 as "1" . signed , default = 3
+#define NR_ALP1_ERR2CURV_TH_RATE ((0x501b << 2) + 0xff000000)
+//Bit 31:24, reg_nr_alp1_minerr_par0 : threshold0 of curve to map mierr to alp1 for luma/chroma channel, this will be set value of flat region mierr that no need directional NR. 0~255.. unsigned , default = 0
+//Bit 23:16, reg_nr_alp1_minerr_par1 : threshold1 of curve to map mierr to alp1 for luma/chroma channel,this will be set value of texture region mierr that can not do directional NR. 0~255.. unsigned , default = 24
+//Bit 15: 8, reg_nr_alp1_minerr_par5 : rate0 (for mierr<th0) of curve to map mierr to alp1 for luma/chroma channel. the larger of the value, the deep of the slope.. unsigned , default = 0
+//Bit 7: 0, reg_nr_alp1_minerr_par6 : rate1 (for mierr>th1) of curve to map mierr to alp1 for luma/chroma channel. the larger of the value, the deep of the slope. 0~255. unsigned , default = 20
+#define NR_ALP1_ERR2CURV_LIMIT ((0x501c << 2) + 0xff000000)
+//Bit 31:24, reg_nr_alp1_minerr_par2 : level limit(for mierr<th0) of curve to map mierr to alp1 for luma/chroma channel, this will be set to alp1 that we can do for flat region. 0~255.. unsigned , default = 0
+//Bit 23:16, reg_nr_alp1_minerr_par3 : level limit(for th0<mierr<th1) of curve to map mierr to alp1 for luma/chroma channel, this will be set to alp1 that we can do for misc region. 0~255.. unsigned , default = 16
+//Bit 15: 8, reg_nr_alp1_minerr_par4 : level limit(for mierr>th1) of curve to map mierr to alp1 for luma/chroma channel, this will be set to alp1 that we can do for texture region. 0~255.255 before. unsigned , default = 63
+//Bit 7: 0, reserved
+#define NR_ALP1_MIN_MAX ((0x501d << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_nr_alp1_ymin : normalized to 64 as '1' . unsigned , default = 0
+//Bit 23:22, reserved
+//Bit 21:16, reg_nr_alp1_ymax : normalized to 64 as '1' . unsigned , default = 63
+//Bit 15:14, reserved
+//Bit 13: 8, reg_nr_alp1_cmin : normalized to 64 as '1' . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_nr_alp1_cmax : normalized to 64 as '1' . unsigned , default = 63
+#define PK_ALP2_MIERR_CORING ((0x501e << 2) + 0xff000000)
+//Bit 31:17, reserved
+//Bit 16, reg_pk_alp2_maxerr_mode : 0 max err; 1: xerr . unsigned , default = 1
+//Bit 15:14, reserved
+//Bit 13: 8, reg_pk_alp2_core_rate : normalized 64 as "1" . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_pk_alp2_core_ofst : normalized 64 as "1" . signed , default = 1
+#define PK_ALP2_ERR2CURV_TH_RATE ((0x501f << 2) + 0xff000000)
+//Bit 31:24, reg_pk_alp2_minerr_par0 : threshold0 of curve to map mierr to alp2 for luma channel, this will be set value of flat region mierr that no need peaking.. unsigned , default = 0
+//Bit 23:16, reg_pk_alp2_minerr_par1 : threshold1 of curve to map mierr to alp2 for luma channel,this will be set value of texture region mierr that can not do peaking. 0~255.. unsigned , default = 24
+//Bit 15: 8, reg_pk_alp2_minerr_par5 : rate0 (for mierr<th0) of curve to map mierr to alp2 for luma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 0
+//Bit 7: 0, reg_pk_alp2_minerr_par6 : rate1 (for mierr>th1) of curve to map mierr to alp2 for luma channel. the larger of the value, the deep of the slope. 0~255.. unsigned , default = 20
+#define PK_ALP2_ERR2CURV_LIMIT ((0x5020 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_alp2_minerr_par2 : level limit(for mierr<th0) of curve to map mierr to alp2 for luma channel, this will be set to alp2 that we can do for flat region. 0~255.. unsigned , default = 0
+//Bit 23:16, reg_pk_alp2_minerr_par3 : level limit(for th0<mierr<th1) of curve to map mierr to alp2 for luma channel, this will be set to alp2 that we can do for misc region. 0~255.. unsigned , default = 16
+//Bit 15: 8, reg_pk_alp2_minerr_par4 : level limit(for mierr>th1) of curve to map mierr to alp2 for luma channel, this will be set to alp2 that we can do for texture region. 0~255. default = 32;. unsigned , default = 32
+//Bit 7: 0, reserved
+#define PK_ALP2_MIN_MAX ((0x5021 << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13: 8, reg_pk_alp2_min : normalized to 64 as '1' . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_pk_alp2_max : normalized to 64 as '1' . unsigned , default = 63
+#define PK_FINALGAIN_HP_BP ((0x5022 << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:16, reg_final_gain_rs : s2: right shift bits for the gain normalization, 0 normal to 32 as 1; 1 normalize to 64 as 1; -2 normalized to 8 as 1; -1 normalize 16 as 1. default = 0
+//Bit 15: 8, reg_hp_final_gain : gain to highpass boost result (including directional/circle blending), normalized 32 as '1', 0~255. 1.25 * 32. unsigned , default = 40
+//Bit 7: 0, reg_bp_final_gain : gain to bandpass boost result (including directional/circle blending), normalized 32 as '1', 0~255. 1.25 * 32. unsigned , default = 30
+#define PK_OS_HORZ_CORE_GAIN ((0x5023 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_os_hsidecore : side coring (not to current pixel) to adaptive overshoot margin in horizontal direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 8
+//Bit 23:16, reg_pk_os_hsidegain : side gain (not to current pixel) to adaptive overshoot margin in horizontal direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20
+//Bit 15: 8, reg_pk_os_hmidcore : midd coring (to current pixel) to adaptive overshoot margin in horizontal direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 2
+//Bit 7: 0, reg_pk_os_hmidgain : midd gain (to current pixel) to adaptive overshoot margin in horizontal direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20
+#define PK_OS_VERT_CORE_GAIN ((0x5024 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_os_vsidecore : side coring (not to current pixel) to adaptive overshoot margin in vertical direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 8
+//Bit 23:16, reg_pk_os_vsidegain : side gain (not to current pixel) to adaptive overshoot margin in vertical direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20
+//Bit 15: 8, reg_pk_os_vmidcore : midd coring (to current pixel) to adaptive overshoot margin in vertical direction. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 2
+//Bit 7: 0, reg_pk_os_vmidgain : midd gain (to current pixel) to adaptive overshoot margin in vertical direction. normalized to 32 as '1'. 0~255;. unsigned , default = 20
+#define PK_OS_ADPT_MISC ((0x5025 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_os_minerr_core : coring to minerr for adaptive overshoot margin. the larger of this value, the less overshoot admitted 0~255;. unsigned , default = 40
+//Bit 23:16, reg_pk_os_minerr_gain : gain to minerr based adaptive overshoot margin. normalized to 64 as '1'. 0~255;. unsigned , default = 6
+//Bit 15: 8, reg_pk_os_adpt_max : maximum limit adaptive overshoot margin (4x). 0~255; . unsigned , default = 200
+//Bit 7: 0, reg_pk_os_adpt_min : minimun limit adaptive overshoot margin (1x). 0~255; . unsigned , default = 20
+#define PK_OS_STATIC ((0x5026 << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:28, reg_pk_osh_mode : 0~3: (2x+1) window in H direction . unsigned , default = 2
+//Bit 27:26, reserved
+//Bit 25:24, reg_pk_osv_mode : 0~3: (2x+1) window in V direction . unsigned , default = 2
+//Bit 23:22, reserved
+//Bit 21:12, reg_pk_os_down : static negative overshoot margin. 0~1023; . unsigned , default = 200
+//Bit 11:10, reserved
+//Bit 9: 0, reg_pk_os_up : static positive overshoot margin. 0~1023; . unsigned , default = 200
+#define PK_NR_ENABLE ((0x5027 << 2) + 0xff000000)
+//Bit 31: 4, reserved
+//Bit 3: 2, reg_3d_mode , 0: no 3D; 1: L/R; 2: T/B; 3: horizontal interleaved, dft = 0 //. unsigned , default = 0
+//Bit 1, reg_pk_en . unsigned , default = 1
+//Bit 0, reg_nr_en . unsigned , default = 1
+#define PK_DRT_SAD_MISC ((0x5028 << 2) + 0xff000000)
+//Bit 31:24, reg_pk_sad_ver_gain : gain to sad[4], 16 normalized to "1"; . unsigned , default = 32
+//Bit 23:16, reg_pk_sad_hor_gain : gain to sad[0], 16 normalized to "1"; . unsigned , default = 24
+//Bit 15:12, reserved
+//Bit 11 reserved
+//Bit 10: 9, reg_pk_bias_diag : bias towards diag . unsigned , default = 0
+//Bit 8, reserved
+//Bit 7: 5, reserved
+//Bit 4: 0, reg_pk_drt_force : force direction of drt peaking filter, h2b: 0:hp drt force, 1: bp drt force; 2: bp+hp drt force, 3: no force;. unsigned , default = 24
+#define NR_TI_DNLP_BLEND ((0x5029 << 2) + 0xff000000)
+//Bit 31:11, reserved
+//Bit 10: 8, reg_dnlp_input_mode : dnlp input options. 0: org_y; 1: gau_y; 2: gauadp_y; 3: edgadplpf_y; 4: nr_y;5: lti_y; 6: pk_y (before os);7: pk_y (after os). unsigned , default = 4
+//Bit 7: 4, reserved
+//Bit 3: 2, reg_nr_cti_blend_mode : blend mode of nr and lti result: 0: nr; 1:cti; 2: (nr+cti)/2; 3:cti + dlt_nr . unsigned , default = 1
+//Bit 1: 0, reg_nr_lti_blend_mode : blend mode of nr and lti result: 0: nr; 1:lti; 2: (nr+lti)/2; 3:lti + dlt_nr . unsigned , default = 2
+////////////////////////////////////////////////////////////////////////////////
+// new ti regsters from here
+////////////////////////////////////////////////////////////////////////////////
+#define LTI_DIR_CORE_ALPHA ((0x502a << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_adp_lti_dir_alp_core_ofst : ofst to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=10. unsigned , default = 10
+//Bit 23:20, reserved
+//Bit 19:16, reg_adp_lti_dir_alp_core_rate : ofset to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=0/32. unsigned , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_adp_lti_dir_alpmin : min value of alpha, alpha = (min_err+x +ofst)/max_err*64; dft=10 . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_adp_lti_dir_alpmax : max value of alpha, alpha = (min_err+x +ofst)/max_err*64; dft=63 . unsigned , default = 63
+#define CTI_DIR_ALPHA ((0x502b << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_adp_cti_dir_alp_core_ofst : ofst to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=10. unsigned , default = 5
+//Bit 23:20, reserved
+//Bit 19:16, reg_adp_cti_dir_alp_core_rate : ofset to min_err, alpha = (min_err - (max_err-min_err)*rate + ofst)/max_err*64; dft=0/32. unsigned , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_adp_cti_dir_alpmin : min value of alpha, alpha = (min_err +x+ofst)/max_err*64; dft=10 . unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_adp_cti_dir_alpmax : max value of alpha, alpha = (min_err +x+ofst)/max_err*64; dft=63 . unsigned , default = 63
+#define LTI_CTI_DF_GAIN ((0x502c << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_adp_lti_hdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12
+//Bit 23:22, reserved
+//Bit 21:16, reg_adp_lti_vdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12
+//Bit 15:14, reserved
+//Bit 13: 8, reg_adp_cti_hdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_adp_cti_vdf_gain : 8 normalized to "1"; default = 12 . unsigned , default = 12
+#define LTI_CTI_DIR_AC_DBG ((0x502d << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30, reg_adp_lti_dir_lpf : 0: no lpf; 1: [1 2 2 2 1]/8 lpf . unsigned , default = 1
+//Bit 29, reserved
+//Bit 28, reg_adp_lti_dir_difmode : 0: y_dif; 1: y_dif + (u_dif+v_dif)/2; . unsigned , default = 1
+//Bit 27, reserved
+//Bit 26, reg_adp_cti_dir_lpf : 0: no lpf; 1: [1 2 2 2 1]/8 lpf dft=1 . unsigned , default = 1
+//Bit 25:24, reg_adp_cti_dir_difmode : 0: (u_dif+v_dif); 1: y_dif/2 + (u_dif+v_dif)*3/4; 2: y_dif + (u_dif+v_dif)/2; 3: y_dif*2 (not recomended). unsigned , default = 2
+//Bit 23:22, reg_adp_hvlti_dcblend_mode : 0: hlti_dc; 1:vlti_dc; 2: avg 3; blend on alpha . unsigned , default = 3
+//Bit 21:20, reg_adp_hvcti_dcblend_mode : 0: hcti_dc; 1:vcti_dc; 2: avg 3; blend on alpha . unsigned , default = 2
+//Bit 19:18, reg_adp_hvlti_acblend_mode : hlti_ac; 1:vlti_ac; 2: add 3;:adaptive to alpha . unsigned , default = 3
+//Bit 17:16, reg_adp_hvcti_acblend_mode : hcti_ac; 1:vcti_ac; 2: add 3;: adaptive to alpha . unsigned , default = 2
+//Bit 15, reserved
+//Bit 14:12, reg_adp_hlti_debug , for hlti debug, default = 0 . unsigned , default = 0
+//Bit 11, reserved
+//Bit 10: 8, reg_adp_vlti_debug , for vlti debug, default = 0 . unsigned , default = 0
+//Bit 7, reserved
+//Bit 6: 4, reg_adp_hcti_debug , for hcti debug, default = 0 . unsigned , default = 0
+//Bit 3, reserved
+//Bit 2: 0, reg_adp_vcti_debug , for vcti debug, default = 0 . unsigned , default = 0
+#define HCTI_FLT_CLP_DC ((0x502e << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28, reg_adp_hcti_en , 0: no cti, 1: new cti, default = 1 . unsigned , default = 1
+//Bit 27:26, reg_adp_hcti_vdn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 25:24, reg_adp_hcti_hdn_flt , 0: no lpf; 1:[0, 0, 0, 4, 8, 4, 0, 0, 0], 2:[0, 0, 2, 4, 4, 4, 2, 0, 0], 3: [1, 2, 2, 2, 2, 2, 2, 2, 1], default = 2. unsigned , default = 2
+//Bit 23:22, reg_adp_hcti_ddn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 21:20, reg_adp_hcti_lpf0_flt , 0:no filter; 1:sigma=0.75, 2: sigma = 1.0, 3: sigma = 1.5, default = 1 . unsigned , default = 1
+//Bit 19:18, reg_adp_hcti_lpf1_flt , 0:no filter; 1:sigma= 2.0, 2: sigma = 3.0, 3: sigma = 4.0, default = 1 . unsigned , default = 1
+//Bit 17:16, reg_adp_hcti_lpf2_flt , 0:no filter; 1:sigma=5.0, 2: sigma = 9.0, 3: sigma = 13.0, default = 1 . unsigned , default = 1
+//Bit 15:12, reg_adp_hcti_hard_clp_win , window size, 0~8, default = 5 . unsigned , default = 5
+//Bit 11: 8, reg_adp_hcti_hard_win_min , window size, 0~8, default = 3 . unsigned , default = 3
+//Bit 7: 5, reserved
+//Bit 4, reg_adp_hcti_clp_mode , 0: hard clip, 1: adaptive clip, default = 1 . unsigned , default = 1
+//Bit 3, reserved
+//Bit 2: 0, reg_adp_hcti_dc_mode , 0:dn, 1:lpf0, 2:lpf1, 3:lpf2, 4: lpf3: 5: vdn result; 6/7:org, default = 0 . unsigned , default = 0
+#define HCTI_BST_GAIN ((0x502f << 2) + 0xff000000)
+//Bit 31:24, reg_adp_hcti_bst_gain0 : gain of the bandpass 0 (lpf1-lpf2)- LBP, default = 80 . unsigned , default = 80
+//Bit 23:16, reg_adp_hcti_bst_gain1 : gain of the bandpass 1 (lpf0-lpf1)- BP, default = 96 . unsigned , default = 96
+//Bit 15: 8, reg_adp_hcti_bst_gain2 : gain of the bandpass 2 (hdn-lpf0)- HP, default = 64 . unsigned , default = 64
+//Bit 7: 0, reg_adp_hcti_bst_gain3 : gain of the unsharp band (yuvin-hdn) - US, default = 16 . unsigned , default = 16
+#define HCTI_BST_CORE ((0x5030 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_hcti_bst_core0 : core of the bandpass 0 (lpf1-lpf2)- LBP, default = 5 . unsigned , default = 5
+//Bit 23:16, reg_adp_hcti_bst_core1 : core of the bandpass 1 (lpf0-lpf1)- BP, default = 5 . unsigned , default = 5
+//Bit 15: 8, reg_adp_hcti_bst_core2 : core of the bandpass 2 (hdn-lpf0)- HP, default = 5 . unsigned , default = 5
+//Bit 7: 0, reg_adp_hcti_bst_core3 : core of the unsharp band (yuvin-hdn) - US, default = 3 . unsigned , default = 5
+#define HCTI_CON_2_GAIN_0 ((0x5031 << 2) + 0xff000000)
+//Bit 31:29, reg_adp_hcti_con_mode : con mode 0:[0, 0,-1, 1, 0, 0, 0]+[0, 0, 0, 1,-1, 0, 0], 1: [0, 0,-1, 0, 1, 0, 0], 2: [0,-1, 0, 0, 0, 1, 0], 3:[-1, 0, 0, 0, 0, 0, 1], 4: .... default = 1. unsigned , default = 1
+//Bit 28:26, reg_adp_hcti_dx_mode : dx mode 0: [-1 1 0]; 1~7: [-1 (2x+1)"0" 1], default = 2 . unsigned , default = 2
+//Bit 25:24, reg_adp_hcti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0
+//Bit 23:16, reg_adp_hcti_con_2_gain0 , default = 25 . unsigned , default = 25
+//Bit 15: 8, reg_adp_hcti_con_2_gain1 , default = 60 . unsigned , default = 60
+//Bit 7: 0, reg_adp_hcti_con_2_gain2 0;, default = 5 . unsigned , default = 5
+#define HCTI_CON_2_GAIN_1 ((0x5032 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_hcti_con_2_gain3 96;, default = 96 . unsigned , default = 96
+//Bit 23:16, reg_adp_hcti_con_2_gain4 5;, default = 5 . unsigned , default = 5
+//Bit 15: 8, reg_adp_hcti_con_2_gain5 80;, default = 80 . unsigned , default = 80
+//Bit 7: 0, reg_adp_hcti_con_2_gain6 20;, default = 20 . unsigned , default = 20
+#define HCTI_OS_MARGIN ((0x5033 << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_adp_hcti_os_margin : margin for hcti overshoot, default = 0 . unsigned , default = 0
+#define HLTI_FLT_CLP_DC ((0x5034 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28, reg_adp_hlti_en , 0: no cti, 1: new cti, default = 1 . unsigned , default = 1
+//Bit 27:26, reg_adp_hlti_vdn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 25:24, reg_adp_hlti_hdn_flt , 0: no lpf; 1:[0, 0, 0, 4, 8, 4, 0, 0, 0], 2:[0, 0, 2, 4, 4, 4, 2, 0, 0], 3: [1, 2, 2, 2, 2, 2, 2, 2, 1], default = 1. unsigned , default = 1
+//Bit 23:22, reg_adp_hlti_ddn_flt , 0: no lpf; 1:[0,2,4,2,0], 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 1 . unsigned , default = 1
+//Bit 21:20, reg_adp_hlti_lpf0_flt , 0:no filter; 1:sigma=0.75, 2: sigma = 1.0, 3: sigma = 1.5, default = 1 . unsigned , default = 1
+//Bit 19:18, reg_adp_hlti_lpf1_flt , 0:no filter; 1:sigma= 2.0, 2: sigma = 3.0, 3: sigma = 4.0, default = 1 . unsigned , default = 1
+//Bit 17:16, reg_adp_hlti_lpf2_flt , 0:no filter; 1:sigma=5.0, 2: sigma = 9.0, 3: sigma = 13.0, default = 1 . unsigned , default = 1
+//Bit 15:12, reg_adp_hlti_hard_clp_win , window size, 0~8, default = 2 . unsigned , default = 2
+//Bit 11: 8, reg_adp_hlti_hard_win_min , window size, 0~8, default = 1 . unsigned , default = 1
+//Bit 7: 5, reserved
+//Bit 4, reg_adp_hlti_clp_mode , 0: hard clip, 1: adaptive clip, default = 0 . unsigned , default = 0
+//Bit 3, reserved
+//Bit 2: 0, reg_adp_hlti_dc_mode , 0:dn, 1:lpf0, 2:lpf1, 3:lpf2, 4: lpf3: 5: vdn result; 6/7:org, default = 4 . unsigned , default = 4
+#define HLTI_BST_GAIN ((0x5035 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_hlti_bst_gain0 : gain of the bandpass 0 (lpf1-lpf2)- LBP, default = 32 . unsigned , default = 32
+//Bit 23:16, reg_adp_hlti_bst_gain1 : gain of the bandpass 1 (lpf0-lpf1)- BP, default = 32 . unsigned , default = 32
+//Bit 15: 8, reg_adp_hlti_bst_gain2 : gain of the bandpass 2 (hdn-lpf0)- HP, default = 28 . unsigned , default = 28
+//Bit 7: 0, reg_adp_hlti_bst_gain3 : gain of the unsharp band (yuvin-hdn) - US, default = 12 . unsigned , default = 12
+#define HLTI_BST_CORE ((0x5036 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_hlti_bst_core0 : core of the bandpass 0 (lpf1-lpf2)- LBP, default = 5 . unsigned , default = 5
+//Bit 23:16, reg_adp_hlti_bst_core1 : core of the bandpass 1 (lpf0-lpf1)- BP, default = 5 . unsigned , default = 5
+//Bit 15: 8, reg_adp_hlti_bst_core2 : core of the bandpass 2 (hdn-lpf0)- HP, default = 5 . unsigned , default = 5
+//Bit 7: 0, reg_adp_hlti_bst_core3 : core of the unsharp band (yuvin-hdn) - US, default = 3 . unsigned , default = 3
+#define HLTI_CON_2_GAIN_0 ((0x5037 << 2) + 0xff000000)
+//Bit 31:29, reg_adp_hlti_con_mode : con mode 0:[0, 0,-1, 1, 0, 0, 0]+[0, 0, 0, 1,-1, 0, 0], 1: [0, 0,-1, 0, 1, 0, 0], 2: [0,-1, 0, 0, 0, 1, 0], 3:[-1, 0, 0, 0, 0, 0, 1], 4: ....., default = 1. unsigned , default = 1
+//Bit 28:26, reg_adp_hlti_dx_mode : dx mode 0: [-1 1 0]; 1~7: [-1 (2x+1)"0" 1], default = 1 . unsigned , default = 1
+//Bit 25:24, reg_adp_hlti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0
+//Bit 23:16, reg_adp_hlti_con_2_gain0 25;, default = 25 . unsigned , default = 25
+//Bit 15: 8, reg_adp_hlti_con_2_gain1 60;, default = 60 . unsigned , default = 60
+//Bit 7: 0, reg_adp_hlti_con_2_gain2 0;, default = 5 . unsigned , default = 5
+#define HLTI_CON_2_GAIN_1 ((0x5038 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_hlti_con_2_gain3 96;, default = 96 . unsigned , default = 96
+//Bit 23:16, reg_adp_hlti_con_2_gain4 5;, default = 95 . unsigned , default = 95
+//Bit 15: 8, reg_adp_hlti_con_2_gain5 80;, default = 80 . unsigned , default = 80
+//Bit 7: 0, reg_adp_hlti_con_2_gain6 20;, default = 20 . unsigned , default = 20
+#define HLTI_OS_MARGIN ((0x5039 << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_adp_hlti_os_margin : margin for hlti overshoot, default = 0 . unsigned , default = 0
+#define VLTI_FLT_CON_CLP ((0x503a << 2) + 0xff000000)
+//Bit 31:15, reserved
+//Bit 14, reg_adp_vlti_en : enable bit of vlti, default = 1 . unsigned , default = 1
+//Bit 13:12, reg_adp_vlti_hxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 11:10, reg_adp_vlti_dxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 9: 8, reg_adp_vlti_han_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 7: 6, reg_adp_vlti_dan_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 5: 4, reg_adp_vlti_dx_mode : 0:[-1 1] 1:[-1 0 -1]; 2/3: [-1 0 0 0 -1], default = 1 . unsigned , default = 1
+//Bit 3, reserved
+//Bit 2, reg_adp_vlti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0
+//Bit 1, reserved
+//Bit 0, reg_adp_vlti_hard_clp_win : window size; 0: 1x3 window; 1: 1x5 window, default = 0 . unsigned , default = 0
+#define VLTI_BST_GAIN ((0x503b << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_adp_vlti_bst_gain0 : gain to boost filter [-1 2 -1];, default = 32 . unsigned , default = 32
+//Bit 15: 8, reg_adp_vlti_bst_gain1 : gain to boost filter [-1 0 2 0 -1];, default = 32 . unsigned , default = 32
+//Bit 7: 0, reg_adp_vlti_bst_gain2 : gain to boost filter usf, default = 32 . unsigned , default = 32
+#define VLTI_BST_CORE ((0x503c << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_adp_vlti_bst_core0 : coring to boost filter [-1 2 -1];, default = 5 . unsigned , default = 5
+//Bit 15: 8, reg_adp_vlti_bst_core1 : coring to boost filter [-1 0 2 0 -1];, default = 5 . unsigned , default = 5
+//Bit 7: 0, reg_adp_vlti_bst_core2 : coring to boost filter usf, default = 3 . unsigned , default = 3
+#define VLTI_CON_2_GAIN_0 ((0x503d << 2) + 0xff000000)
+//Bit 31:24, reg_adp_vlti_con_2_gain0 25;, default = 25 . unsigned , default = 25
+//Bit 23:16, reg_adp_vlti_con_2_gain1 60;, default = 60 . unsigned , default = 60
+//Bit 15: 8, reg_adp_vlti_con_2_gain2 0;, default = 5 . unsigned , default = 5
+//Bit 7: 0, reg_adp_vlti_con_2_gain3 96;, default = 96 . unsigned , default = 96
+#define VLTI_CON_2_GAIN_1 ((0x503e << 2) + 0xff000000)
+//Bit 31:24, reg_adp_vlti_con_2_gain4 5;, default = 95 . unsigned , default = 95
+//Bit 23:16, reg_adp_vlti_con_2_gain5 80;, default = 80 . unsigned , default = 80
+//Bit 15: 8, reg_adp_vlti_con_2_gain6 20;, default = 20 . unsigned , default = 20
+//Bit 7: 0, reg_adp_vlti_os_margin : margin for vlti overshoot, default = 0 . unsigned , default = 0
+#define VCTI_FLT_CON_CLP ((0x503f << 2) + 0xff000000)
+//Bit 31:15, reserved
+//Bit 14, reg_adp_vcti_en : enable bit of vlti, default = 1 . unsigned , default = 1
+//Bit 13:12, reg_adp_vcti_hxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 11:10, reg_adp_vcti_dxn_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 9: 8, reg_adp_vcti_han_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 7: 6, reg_adp_vcti_dan_flt : 0: no dn; 1: [1 2 1]/4; 2 : [1 2 2 2 1]/8 3:[1 0 2 0 1]/4, default = 2 . unsigned , default = 2
+//Bit 5: 4, reg_adp_vcti_dx_mode : 0:[-1 1] 1:[-1 0 -1]; 2/3: [-1 0 0 0 -1], default = 1 . unsigned , default = 1
+//Bit 3, reserved
+//Bit 2, reg_adp_vcti_con_lpf : lpf mode of the con: 0: [1 2 1]/4; 1:[1 2 2 2 1]/8, default = 0 . unsigned , default = 0
+//Bit 1, reserved
+//Bit 0, reg_adp_vcti_hard_clp_win : window size; 0: 1x3 window; 1: 1x5 window, default = 0 . unsigned , default = 0
+#define VCTI_BST_GAIN ((0x5040 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_adp_vcti_bst_gain0 : gain to boost filter [-1 2 -1];, default = 16 . unsigned , default = 16
+//Bit 15: 8, reg_adp_vcti_bst_gain1 : gain to boost filter [-1 0 2 0 -1];, default = 16 . unsigned , default = 16
+//Bit 7: 0, reg_adp_vcti_bst_gain2 : gain to boost filter usf, default = 16 . unsigned , default = 16
+#define VCTI_BST_CORE ((0x5041 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_adp_vcti_bst_core0 : coring to boost filter [-1 2 -1];, default = 5 . unsigned , default = 5
+//Bit 15: 8, reg_adp_vcti_bst_core1 : coring to boost filter [-1 0 2 0 -1];, default = 5 . unsigned , default = 5
+//Bit 7: 0, reg_adp_vcti_bst_core2 : coring to boost filter usf, default = 3 . unsigned , default = 3
+#define VCTI_CON_2_GAIN_0 ((0x5042 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_vcti_con_2_gain0 25;, default = 25 . unsigned , default = 25
+//Bit 23:16, reg_adp_vcti_con_2_gain1 60;, default = 60 . unsigned , default = 60
+//Bit 15: 8, reg_adp_vcti_con_2_gain2 0;, default = 5 . unsigned , default = 5
+//Bit 7: 0, reg_adp_vcti_con_2_gain3 96;, default = 96 . unsigned , default = 96
+#define VCTI_CON_2_GAIN_1 ((0x5043 << 2) + 0xff000000)
+//Bit 31:24, reg_adp_vcti_con_2_gain4 5;, default = 95 . unsigned , default = 95
+//Bit 23:16, reg_adp_vcti_con_2_gain5 80;, default = 80 . unsigned , default = 80
+//Bit 15: 8, reg_adp_vcti_con_2_gain6 20;, default = 20 . unsigned , default = 20
+//Bit 7: 0, reg_adp_vcti_os_margin : margin for vcti overshoot, default = 0 . unsigned , default = 0
+#define SHARP_3DLIMIT ((0x5044 << 2) + 0xff000000)
+//Bit 31:29, reserved
+//Bit 28:16, reg_3d_mid_width ,width of left part of 3d input, dft = half size of input width default = 0 . unsigned , default = 960
+//Bit 15:13, reserved
+//Bit 12: 0, reg_3d_mid_height ,height of left part of 3d input, dft = half size of input height default = 0 . unsigned , default = 540
+#define DNLP_EN ((0x5045 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_dnlp_hblank
+//Bit 7: 1, reserved
+//Bit 0, reg_dnlp_en . unsigned , default = 1
+#define DEMO_CRTL ((0x5056 << 2) + 0xff000000)
+//Bit 31:19, reserved
+//Bit 18:17, demo_disp_position . unsigned , default = 2
+//Bit 16, demo_hsvsharp_enable . unsigned , default = 0
+//Bit 15:13, reserved
+//Bit 12: 0, demo_left_top_screen_width : . unsigned , default = 360
+#define SHARP_SR2_CTRL ((0x5057 << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24 reg_sr2_bic_pknr_bypass :
+//Bit 23:22 reserved
+//Bit 21:16, reg_sr2_pk_la_err_dis_rate : . unsigned , low angle and high angle error should not be no less than nearby_error*rate/64; default = 24
+//Bit 15:8, reg_sr2_pk_sad_diag_gain : . unsigned , gain to sad[2] and sad[6], 16 normalized to "1"; default = 16
+//Bit 7, reg_sr2_vert_outphs : . unsigned , default = 0
+//Bit 6, reg_sr2_horz_outphs : . unsigned , default = 0
+//Bit 5, reg_sr2_vert_ratio : . unsigned , default = 0
+//Bit 4, reg_sr2_hori_ratio : . unsigned , default = 0
+//Bit 3, reg_sr2_bic_norm : . unsigned , default = 1
+//Bit 2, reg_sr2_enable : . unsigned , default = 0
+//Bit 1, reg_sr2_sharp_prc_lr_hbic : . unsigned , default = 0
+//Bit 0, reg_sr2_sharp_prc_lr : lti/cti/nr/peaking processing using LR grid, 0: on HR grid; 1:on LR grid, horizontally no upscale, but using simple bic . unsigned , default = 0
+#define SHARP_SR2_YBIC_HCOEF0 ((0x5058 << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_y_bic_hcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel Filter will be normalized to 128 as ‘1’; default=0
+//Bit 23:16, reg_sr2_y_bic_hcoef02 the same as above; default=0
+//Bit 15: 8, reg_sr2_y_bic_hcoef01 the same as above; default=64
+//Bit 7: 0, reg_sr2_y_bic_hcoef00 the same as above; default=0
+#define SHARP_SR2_YBIC_HCOEF1 ((0x5059 << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_y_bic_hcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channel,Filter will be normalized to 128 as ‘1’; default=-4
+//Bit 23:16, reg_sr2_y_bic_hcoef12 the same as above; default=36
+//Bit 15: 8, reg_sr2_y_bic_hcoef11 the same as above; default=36
+//Bit 7: 0, reg_sr2_y_bic_hcoef10 the same as above; default=-4
+#define SHARP_SR2_CBIC_HCOEF0 ((0x505a << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_c_bic_hcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel ,Filter will be normalized to 128 as ‘1’; default=0
+//Bit 23:16, reg_sr2_c_bic_hcoef02 the same as above; default=21
+//Bit 15: 8, reg_sr2_c_bic_hcoef01 the same as above; default=22
+//Bit 7: 0, reg_sr2_c_bic_hcoef00 the same as above; default=21
+#define SHARP_SR2_CBIC_HCOEF1 ((0x505b << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_c_bic_hcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channel,Filter will be normalized to 128 as ‘1’; default=-4
+//Bit 23:16, reg_sr2_c_bic_hcoef12 the same as above; default=36
+//Bit 15: 8, reg_sr2_c_bic_hcoef11 the same as above; default=36
+//Bit 7: 0, reg_sr2_c_bic_hcoef10 the same as above; default=-4
+#define SHARP_SR2_YBIC_VCOEF0 ((0x505c << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_y_bic_vcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel, Filter will be normalized to 128 as ‘1’; default=0
+//Bit 23:16, reg_sr2_y_bic_vcoef02 the same as above; default=0
+//Bit 15: 8, reg_sr2_y_bic_vcoef01 the same as above; default=64
+//Bit 7: 0, reg_sr2_y_bic_vcoef00 the same as above; default=0
+#define SHARP_SR2_YBIC_VCOEF1 ((0x505d << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_y_bic_vcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channe, lFilter will be normalized to 128 as ‘1’; default=-4
+//Bit 23:16, reg_sr2_y_bic_vcoef12 the same as above; default=36
+//Bit 15: 8, reg_sr2_y_bic_vcoef11 the same as above; default=36
+//Bit 7: 0, reg_sr2_y_bic_vcoef10 the same as above; default=-4
+#define SHARP_SR2_CBIC_VCOEF0 ((0x505e << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_c_bic_vcoef03 Horizontal bi-cubic filter of 1.0 phase of luma channel, Filter will be normalized to 128 as ‘1’; default=0
+//Bit 23:16, reg_sr2_c_bic_vcoef02 the same as above; default=21
+//Bit 15: 8, reg_sr2_c_bic_vcoef01 the same as above; default=22
+//Bit 7: 0, reg_sr2_c_bic_vcoef00 the same as above; default=21
+#define SHARP_SR2_CBIC_VCOEF1 ((0x505f << 2) + 0xff000000)
+//Bit 31:24, reg_sr2_c_bic_vcoef13 Horizontal bi-cubic filter of 0.5 phase of luma channel,Filter will be normalized to 128 as ‘1’; default=-4
+//Bit 23:16, reg_sr2_c_bic_vcoef12 the same as above; default=36
+//Bit 15: 8, reg_sr2_c_bic_vcoef11 the same as above; default=36
+//Bit 7: 0, reg_sr2_c_bic_vcoef10 the same as above; default=-4
+#define SHARP_SR2_MISC ((0x5060 << 2) + 0xff000000)
+//Bit 31:2, reserved
+//Bit 1, reg_sr2_cmpmux_bef : . unsigned , default = 0,0 no swap anf for YUV->YUV; 1, swapped and for RGB->GBR;
+//Bit 0, reg_sr2_cmpmux_aft : . unsigned , default = 0,0 no swap anf for YUV->YUV; 1, swapped and for GBR-RGB;
+#define SHARP_SR3_SAD_CTRL ((0x5061 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_sr3_pk_sad_core_rate // u6: rate of coring for sad(theta) - sad(theta+pi/2)*rate/64
+//Bit 23:22 reserved
+//Bit 21:16 reg_sr3_lti_sad_core_rate // u6: rate of coring for sad(theta) - sad(theta+pi/2)*rate/64 , default= 6
+//Bit 15:14 reserved
+//Bit 13:8 reg_sr3_cti_sad_core_rate // u6: rate of coring for sad(theta) - sad(theta+pi/2)*rate/64 , default= 6
+//Bit 7, reg_sr3_lti_hsad_mode // u1: mode for hsad of lti caluclation; 0: block based; 1:othor shape; default= 1
+//Bit 6, reg_sr3_cti_hsad_mode // u1: mode for hsad of cti caluclation; 0: block based; 1:othor shape; default= 1
+//Bit 5, reg_sr3_lti_dsad_mode // u1: mode for dsad of lti caluclation, 0: block based; 1:othor shape; default= 1
+//Bit 4, reg_sr3_cti_dsad_mode // u1: mode for dsad of cti caluclation, 0: block based; 1:othor shape; default= 1
+//Bit 3, reg_sr3_lti_vsad_mode // u1: mode for vsad of lti caluclation, 0: block based; 1:othor shape; default= 1
+//Bit 2, reg_sr3_cti_vsad_mode // u1: mode for vsad of cti caluclation, 0: block based; 1:othor shape; default= 1
+//Bit 1, reg_sr3_lti_hsad_hlpf // u1: hlpf for hsad of lti caluclation, 0: no hlpf; 1: with [1 2 1] hlpf; default= 1
+//Bit 0, reg_sr3_cti_hsad_hlpf // u1: hlpf for hsad of cti caluclation, 0: no hlpf; 1: with [1 2 1] hlpf; default= 1
+#define SHARP_SR3_PK_CTRL0 ((0x5062 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11, reg_sr3_pk_sad_mode // u1: mode for sad of peaking and noise reduction, 0: block based; 1:othor shape; default= 1
+//Bit 10, reg_sr3_pk_hsad_hlpf // u1: hlpf for hsad for peaking caluclation, 0: no hlpf; 1: with [1 2 2 2 1] hlpf; default= 1
+//Bit 9, reg_sr3_pk_vsad_hlpf // u1: hlpf for vsad for peaking caluclation, 0: no hlpf; 1: with [1 2 2 2 1] hlpf; default= 1
+//Bit 8, reg_sr3_pk_dsad_hlpf // u1: hlpf for dsad for peaking caluclation, 0: no hlpf; 1: with [1 2 2 2 1] hlpf; default= 1
+//Bit 7:6, reg_sr3_pk_hpdrt_mode // u2: mode for HPdrt filter: default= 3
+//Bit 5:4, reg_sr3_pk_bpdrt_mode // u2: mode for BPdrt filter: default= 3
+//Bit 3:2, reg_sr3_pk_drtbld_range // u2: range of the min2 and min direction distance; default =1
+//Bit 1, reserved
+//Bit 0, reg_sr3_pk_ti_blend_mode // u1: blend mode of the TI and PK results: default = 0;
+#define SHARP_SR3_PK_CTRL1 ((0x5063 << 2) + 0xff000000)
+//Bit 31, reserved
+//Bit 30:28, reg_sr3_pk_hp_hvcon_replace8_maxsad //u3: replace HP hvcon by maxsad, default =1
+//Bit 27, reserved
+//Bit 26:24, reg_sr3_pk_bp_hvcon_replace8_maxsad //u3: replace HP hvcon by maxsad, default =1
+//Bit 23:16, reg_sr3_pk_hp_hvcon_replace8lv_gain //u8: gain to local variant before calculating the hv gain for peaking, normalized to 32 as "1" default = 32;
+//Bit 15:8, reg_sr3_pk_bp_hvcon_replace8lv_gain //u8: gain to local variant before calculating the hv gain for peaking, normalized to 32 as "1" default = 32;
+//Bit 7, reg_sr3_sad_intlev_mode //u1: interleave detection xerr mode: 0 max; 1:sum default=1
+//Bit 6, reg_sr3_sad_intlev_mode1 //u1: mode 1 of using diagonal protection: 0: no digonal protection; 1: with diagonal protection default=1
+//Bit 5:0, reg_sr3_sad_intlev_gain //u6: interleave detection for sad gain applied, normalized to 8 as 1 default=12
+#define SHARP_DEJ_CTRL ((0x5064 << 2) + 0xff000000)
+//Bit 31:4 reserved
+//Bit 15:8, reg_sr3_dejaggy_hblank // u8
+//Bit 7:4 reserved
+//Bit 3:2, reg_sr3_dejaggy_sameside_prtct // u2: enable of sr3 dejaggy same side curve protect from filter, [0] for proc, [1] for ctrl path, default=3
+//Bit 1, reg_sr3_dejaggy_sameside_mode // u1: mode of the sameside flag decision: default =1
+//Bit 0, reg_sr3_dejaggy_enable // u1: enable of sr3 dejaggy: default =0
+#define SHARP_DEJ_ALPHA ((0x5065 << 2) + 0xff000000)
+//Bit 31:28, reg_sr3_dejaggy_ctrlchrm_alpha_1 //u4: alpha for LR video LPF, default = 0
+//Bit 27:24, reg_sr3_dejaggy_ctrlchrm_alpha_0 //u4: alpha for LR video LPF, default = 15
+//Bit 23:20, reg_sr3_dejaggy_ctrlluma_alpha_1 //u4: alpha for LR video LPF, default = 0
+//Bit 19:16, reg_sr3_dejaggy_ctrlluma_alpha_0 //u4: alpha for LR video LPF, default = 15
+//Bit 15:12, reg_sr3_dejaggy_procchrm_alpha_1 //u4: alpha for LR video LPF, default = 4
+//Bit 11:8, reg_sr3_dejaggy_procchrm_alpha_0 //u4: alpha for LR video LPF, default = 6
+//Bit 7:4, reg_sr3_dejaggy_procluma_alpha_1 //u4: alpha for LR video LPF, default = 4
+//Bit 3:0, reg_sr3_dejaggy_procluma_alpha_0 //u4: alpha for LR video LPF, default = 6
+#define SHARP_SR3_DRTLPF_EN ((0x5066 << 2) + 0xff000000)
+//Bit 31:15 reserved
+//Bit 14:8, reg_pk_debug_edge . unsigned , default = 0
+//Bit 7, reserved
+//Bit 6:4, reg_sr3_drtlpf_theta_en //u1x3 theta (pure vertical and horizontal HF burst protection) enable. 0: not enable, 1:enable protection
+//Bit 3, reserved
+//Bit 2:0 reg_sr3_drtlpf_enable //u1x3 directional lpf on luma U and V channels, default = 7
+#define SHARP_SR3_DRTLPF_ALPHA_0 ((0x5067 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_sr3_drtlpf_alpha3 //u6: directional lpf alpha coef for min_sad/max_sad comparied, default = 9
+//Bit 23:22 reserved
+//Bit 21:16 reg_sr3_drtlpf_alpha2 //u6: default =10
+//Bit 15:14 reserved
+//Bit 13:8 reg_sr3_drtlpf_alpha1 //u6: default = 11
+//Bit 7:6 reserved
+//Bit 5:0 reg_sr3_drtlpf_alpha0 //u6: default = 12
+#define SHARP_SR3_DRTLPF_ALPHA_1 ((0x5068 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_sr3_drtlpf_alpha7 //u6: directional lpf alpha coef for min_sad/max_sad comparied, default = 1
+//Bit 23:22 reserved
+//Bit 21:16 reg_sr3_drtlpf_alpha6 //u6: default = 4
+//Bit 15:14 reserved
+//Bit 13:8 reg_sr3_drtlpf_alpha5 //u6: default = 7
+//Bit 7:6 reserved
+//Bit 5:0 reg_sr3_drtlpf_alpha4 //u6: default = 8
+#define SHARP_SR3_DRTLPF_ALPHA_2 ((0x5069 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_sr3_drtlpf_alpha11 //u6: directional lpf alpha coef for min_sad/max_sad comparied, default = 0
+//Bit 23:22 reserved
+//Bit 21:16 reg_sr3_drtlpf_alpha10 //u6: default = 0
+//Bit 15:14 reserved
+//Bit 13:8 reg_sr3_drtlpf_alpha9 //u6: default = 0
+//Bit 7:6 reserved
+//Bit 5:0 reg_sr3_drtlpf_alpha8 //u6: default = 0
+#define SHARP_SR3_DRTLPF_ALPHA_OFST ((0x506a << 2) + 0xff000000)
+//Bit 31:28 reg_sr3_drtlpf_alpha_ofst7 //s4: directional lpf alpha coef ofset of each directions, default = -8
+//Bit 27:24 reg_sr3_drtlpf_alpha_ofst6 //s4: default = -8
+//Bit 23:20 reg_sr3_drtlpf_alpha_ofst5 //s4: default = -8
+//Bit 19:16 reg_sr3_drtlpf_alpha_ofst4 //s4: default = -8
+//Bit 15:12 reg_sr3_drtlpf_alpha_ofst3 //s4: default = -8
+//Bit 11:8 reg_sr3_drtlpf_alpha_ofst2 //s4: default = -8
+//Bit 7:4 reg_sr3_drtlpf_alpha_ofst1 //s4: default = -8
+//Bit 3:0 reg_sr3_drtlpf_alpha_ofst0 //s4: default = -8
+#define SHARP_SR3_DERING_CTRL ((0x506b << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_sr3_dering_enable // u3: dering enable bits; default = 1
+//Bit 27 reserved
+//Bit 26:24 reg_sr3_dering_varlpf_mode // u3: local variant LPF mode: 0 no filter, 1, errosion 3x3; 2: 3x3 lpf; 3 and up: 3x3 errosion + lpf default = 3
+//Bit 23:20 reg_sr3_dering_maxrange // u4: maximum:range of dering in LR resolution, max to 12; default = 9
+//Bit 19:18 reserved
+//Bit 17:16 reg_sr3_dering_lcvar_blend_mode // u2: mode for lcvar calculation: 0: HVblend; 1: diagblend; 2: HVblend+V (for hring); 3: HVblend+ DiagBlend default = 2
+//Bit 15:8 reg_sr3_dering_lcvar_gain // u8: gain to local variant and normalized to 32 as "1" default = 64
+//Bit 7:0 reg_sr3_dering_lcvar_nearby_maxsad_th // u8: threshold to use nearer side maxsad if that side sad is larger than this threshold, ortherwise, use the max one default = 28
+#define SHARP_SR3_DERING_LUMA2PKGAIN_0TO3 ((0x506c << 2) + 0xff000000)
+//Bit 31:24 reg_sr3_dering_luma2pkgain3 // u8: level limit(for th0<bpcon<th1) of curve for dering pkgain based on LPF luma level. default=255
+//Bit 23:16 reg_sr3_dering_luma2pkgain2 // u8: level limit(for bpcon<th0) of curve for dering pkgain based on LPF luma level. default=255
+//Bit 15:8 reg_sr3_dering_luma2pkgain1 // u8: threshold1 of curve for dering pkgain based on LPF luma level default =200
+//Bit 7:0 reg_sr3_dering_luma2pkgain0 // u8: threshold0 of curve for dering pkgain based on LPF luma level. default =30
+#define SHARP_SR3_DERING_LUMA2PKGAIN_4TO6 ((0x506d << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_sr3_dering_luma2pkgain6 // u8: rate1 (for bpcon>th1) of curve for dering pkgain based on LPF luma level. default =24
+//Bit 15:8 reg_sr3_dering_luma2pkgain5 // u8: rate0 (for bpcon<th0) of curve for dering pkgain based on LPF luma level. dfault =50
+//Bit 7:0 reg_sr3_dering_luma2pkgain4 // u8: level limit(for bpcon>th1) of curve for dering pkgain based on LPF luma level. default =255
+#define SHARP_SR3_DERING_LUMA2PKOS_0TO3 ((0x506e << 2) + 0xff000000)
+//Bit 31:24 reg_sr3_dering_luma2pkos3 // u8: level limit(for th0<bpcon<th1) of curve for dering pkOS based on LPF luma level. default=255
+//Bit 23:16 reg_sr3_dering_luma2pkos2 // u8: level limit(for bpcon<th0) of curve for dering pkOS based on LPF luma level. default=255
+//Bit 15:8 reg_sr3_dering_luma2pkos1 // u8: threshold1 of curve for dering pkOS based on LPF luma level default =200
+//Bit 7:0 reg_sr3_dering_luma2pkos0 // u8: threshold0 of curve for dering pkOS based on LPF luma leve. default =30
+#define SHARP_SR3_DERING_LUMA2PKOS_4TO6 ((0x506f << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_sr3_dering_luma2pkos6 // u8: rate1 (for bpcon>th1) of curve for dering pkOS based on LPF luma level. default =24
+//Bit 15:8 reg_sr3_dering_luma2pkos5 // u8: rate0 (for bpcon<th0) of curve for dering pkOS based on LPF luma level. dfault =50
+//Bit 7:0 reg_sr3_dering_luma2pkos4 // u8: level limit(for bpcon>th1) of curve for dering pkOS based on LPF luma level. default =255
+#define SHARP_SR3_DERING_GAINVS_MADSAD ((0x5070 << 2) + 0xff000000)
+//Bit 31:28 reg_sr3_dering_gainvs_maxsad7 //u4: pkgain vs maxsad value, 8 node interpolations, default = 0
+//Bit 27:24 reg_sr3_dering_gainvs_maxsad6 //u4: default = 0
+//Bit 23:20 reg_sr3_dering_gainvs_maxsad5 //u4: default = 0
+//Bit 19:16 reg_sr3_dering_gainvs_maxsad4 //u4: default = 0
+//Bit 15:12 reg_sr3_dering_gainvs_maxsad3 //u4: default = 0
+//Bit 11:8 reg_sr3_dering_gainvs_maxsad2 //u4: default = 0
+//Bit 7:4 reg_sr3_dering_gainvs_maxsad1 //u4: default = 4
+//Bit 3:0 reg_sr3_dering_gainvs_maxsad0 //u4: default = 8
+#define SHARP_SR3_DERING_GAINVS_VR2MAX ((0x5071 << 2) + 0xff000000)
+//Bit 31:28 reg_sr3_dering_gainvs_vr2max7 //u4: pkgain vs ratio = max(local_var, floor)/maxsad nearby, default = 15
+//Bit 27:24 reg_sr3_dering_gainvs_vr2max6 //u4: default = 15
+//Bit 23:20 reg_sr3_dering_gainvs_vr2max5 //u4: default = 15
+//Bit 19:16 reg_sr3_dering_gainvs_vr2max4 //u4: default = 15
+//Bit 15:12 reg_sr3_dering_gainvs_vr2max3 //u4: default = 14
+//Bit 11:8 reg_sr3_dering_gainvs_vr2max2 //u4: default = 12
+//Bit 7:4 reg_sr3_dering_gainvs_vr2max1 //u4: default = 2
+//Bit 3:0 reg_sr3_dering_gainvs_vr2max0 //u4: default = 0
+#define SHARP_SR3_DERING_PARAM0 ((0x5072 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:16 reg_sr3_dering_lcvar_floor //u8: local varianet no smaller than this value to calculate dgain max(localvar,x)/maxsad. default = 10
+//Bit 15:8 reg_sr3_dering_vr2max_gain //u8: gain to max(local_var, floor)/maxsad before feeding to LUT. default = 32
+//Bit 7:6 reserved
+//Bit 5:0 reg_sr3_dering_vr2max_limt //u6: limit of maxsad to max(local_var, floor)*(max(maxsad, lmit))/maxsad. default = 16
+#define SHARP_SR3_DRTLPF_THETA ((0x5073 << 2) + 0xff000000)
+//Bit 31:0 reg_sr3_drtlpf_theta //u4x8: directional lpf beta coef for min_sad/min2_sad compared to x=0:7 correspond to[1:8]/16; 0 means no drtLPF, 15: 100% alpha dependant drtLPF
+#define SHARP_SATPRT_CTRL ((0x5074 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 reg_satprt_sat_core //u8: 4x will be coring to cor(irgb_max-irgb_min) to calculate the oy_delt, the smaller the more protection to color, the larger only the rich color will be protected;
+//Bit 15:8 reg_satprt_sat_rate //u8: rate to cor(irgb_max-irgb_min) to calculate the oy_delt, the larger the more protection to rich color; norm 16 as 1
+//Bit 7:4 reserved
+//Bit 3:2 reg_satprt_csc_mode //u2: csc mode of current yuv input: 0:601, 1:709, 2:BT2020 NCL, 3:reserved
+//Bit 1 reg_satprt_is_lmt //u1: flag telling the YUV is limited range data or full range data, 0 full range, 1: limited range
+//Bit 0 reg_satprt_enable //u1: enable of saturation protection for dnlp adjustments
+#define SHARP_SATPRT_DIVM ((0x5075 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:0 reg_satprt_div_m //u8x3, 1/m, normalized to 128 as 1, default=1
+#define SHARP_DB_FLT_CTRL ((0x5077 << 2) + 0xff000000)
+//Bit 31:27 reserved
+//Bit 26 reg_nrdeband_reset1
+//Bit 25 reg_nrdeband_reset0
+//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 0:yuv 1:RGB
+//Bit 23 reg_nrdeband_en11 // unsigned , default = 1 debanding registers of side lines, [0] for luma, same for below
+//Bit 22 reg_nrdeband_en10 // unsigned , default = 1 debanding registers of side lines, [1] for chroma, same for below
+//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
+//Bit 16 reserved
+//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
+//Bit 12 reserved
+//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6
+//Bit 8 reserved
+//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 debanding random hp portion xor, [0] for luma
+//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 debanding random hp portion xor, [1] for chroma
+//Bit 5 reg_nrdeband_en1 // unsigned , default = 1 debanding registers, for luma
+//Bit 4 reg_nrdeband_en0 // unsigned , default = 1 debanding registers, for chroma
+//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+#define SHARP_DB_FLT_RANDLUT ((0x5079 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:21 reg_nrdebandslut7 // unsigned , default = 1 lut0
+//Bit 20:18 reg_nrdebandslut6 // unsigned , default = 1 lut0
+//Bit 17:15 reg_nrdebandslut5 // unsigned , default = 1 lut0
+//Bit 14:12 reg_nrdebandslut4 // unsigned , default = 1 lut0
+//Bit 11: 9 reg_nrdebandslut3 // unsigned , default = 1 lut0
+//Bit 8: 6 reg_nrdebandslut2 // unsigned , default = 1 lut0
+//Bit 5: 3 reg_nrdebandslut1 // unsigned , default = 1 lut0
+//Bit 2: 0 reg_nrdebandslut0 // unsigned , default = 1 lut0
+#define SHARP_DB_FLT_PXI_THRD ((0x507a << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 to luma/|u/v| for using the denoise
+//Bit 15:10 reserved
+//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 to luma/|u/v| for using the denoise
+#define SHARP_DB_FLT_SEED_Y ((0x507b << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 noise adding seed for Y. seed[0]= 0x60a52f20; as default
+#define SHARP_DB_FLT_SEED_U ((0x507c << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 noise adding seed for U. seed[0]= 0x60a52f27; as default
+#define SHARP_DB_FLT_SEED_V ((0x507d << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define SHARP_PKGAIN_VSLUMA_LUT_L ((0x507e << 2) + 0xff000000)
+//Bit 31:28 reg_pkgain_vsluma_lut7;
+//Bit 27:24 reg_pkgain_vsluma_lut6;
+//Bit 23:20 reg_pkgain_vsluma_lut5;
+//Bit 19:16 reg_pkgain_vsluma_lut4;
+//Bit 15:12 reg_pkgain_vsluma_lut3;
+//Bit 11: 8 reg_pkgain_vsluma_lut2;
+//Bit 7: 4 reg_pkgain_vsluma_lut1;
+//Bit 3: 0 reg_pkgain_vsluma_lut0;
+#define SHARP_PKGAIN_VSLUMA_LUT_H ((0x507f << 2) + 0xff000000)
+//Bit 31: 4 reserved;
+//Bit 3: 0 reg_pkgain_vsluma_lut8;
+#define SHARP_PKOSHT_VSLUMA_LUT_L ((0x5080 << 2) + 0xff000000)
+//Bit 31:28 reg_pkosht_vsluma_lut7;
+//Bit 27:24 reg_pkosht_vsluma_lut6;
+//Bit 23:20 reg_pkosht_vsluma_lut5;
+//Bit 19:16 reg_pkosht_vsluma_lut4;
+//Bit 15:12 reg_pkosht_vsluma_lut3;
+//Bit 11: 8 reg_pkosht_vsluma_lut2;
+//Bit 7: 4 reg_pkosht_vsluma_lut1;
+//Bit 3: 0 reg_pkosht_vsluma_lut0;
+#define SHARP_PKOSHT_VSLUMA_LUT_H ((0x5081 << 2) + 0xff000000)
+//Bit 31: 4 reserved;
+//Bit 3: 0 reg_pkosht_vsluma_lut8;
+#define SHARP_SATPRT_LMT_RGB1 ((0x5082 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 reg_satprt_lmt_g //u12x3, limit of the rgb channel, for limited range RGB, set to 960, otherwise set to 1023
+//Bit 15:12 reserved
+//Bit 11:0 reg_satprt_lmt_r //u12x3, limit of the rgb channel, for limited range RGB, set to 960, otherwise set to 1023
+#define SHARP_SATPRT_LMT_RGB2 ((0x5083 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11:0 reg_satprt_lmt_b //u12x3, limit of the rgb channel, for limited range RGB, set to 960, otherwise set to 1023
+#define SHARP_GATE_CLK_CTRL_0 ((0x5084 << 2) + 0xff000000)
+//Bit 31: 0 reg_gate_clk_ctrl_0
+#define SHARP_GATE_CLK_CTRL_1 ((0x5085 << 2) + 0xff000000)
+//Bit 31: 0 reg_gate_clk_ctrl_1
+#define SHARP_GATE_CLK_CTRL_2 ((0x5086 << 2) + 0xff000000)
+//Bit 31: 0 reg_gate_clk_ctrl_2
+#define SHARP_GATE_CLK_CTRL_3 ((0x5087 << 2) + 0xff000000)
+//Bit 31: 0 reg_gate_clk_ctrl_3
+#define SHARP_DPS_CTRL ((0x5088 << 2) + 0xff000000)
+//Bit 31: 0 reg_sharp_dps_ctrl
+#define DNLP_00 ((0x5090 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid0 : dnlp00 . unsigned , default = 32'h00008060
+#define DNLP_01 ((0x5091 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid1 : dnlp01 . unsigned , default = 32'h100e0c0a
+#define DNLP_02 ((0x5092 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid2 : dnlp02 . unsigned , default = 32'h1a171412
+#define DNLP_03 ((0x5093 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid3 : dnlp03 . unsigned , default = 32'h2824201d
+#define DNLP_04 ((0x5094 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid4 : dnlp04 . unsigned , default = 32'h3834302c
+#define DNLP_05 ((0x5095 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid5 : dnlp05 . unsigned , default = 32'h4b45403c
+#define DNLP_06 ((0x5096 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid6 : dnlp06 . unsigned , default = 32'h605b5550
+#define DNLP_07 ((0x5097 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid7 : dnlp07 . unsigned , default = 32'h80787068
+#define DNLP_08 ((0x5098 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid8 : dnlp08 . unsigned , default = 32'ha0989088
+#define DNLP_09 ((0x5099 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid9 : dnlp09 . unsigned , default = 32'hb8b2aca6
+#define DNLP_10 ((0x509a << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid10 : dnlp10 . unsigned , default = 32'hc8c4c0bc
+#define DNLP_11 ((0x509b << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid11 : dnlp11 . unsigned , default = 32'hd4d2cecb
+#define DNLP_12 ((0x509c << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid12 : dnlp12 . unsigned , default = 32'hdad8d7d6
+#define DNLP_13 ((0x509d << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid13 : dnlp13 . unsigned , default = 32'he2e0dedc
+#define DNLP_14 ((0x509e << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid14 : dnlp14 . unsigned , default = 32'hf0ece8e4
+#define DNLP_15 ((0x509f << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid15 : dnlp15 . unsigned , default = 32'hfffcf8f4
+#define DNLP_16 ((0x50a0 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid16 : dnlp16 . unsigned , default = 32'h08060402
+#define DNLP_17 ((0x50a1 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid17 : dnlp17 . unsigned , default = 32'h100e0c0a
+#define DNLP_18 ((0x50a2 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid18 : dnlp18 . unsigned , default = 32'h1a171412
+#define DNLP_19 ((0x50a3 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid19 : dnlp19 . unsigned , default = 32'h2824201d
+#define DNLP_20 ((0x50a4 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid20 : dnlp20 . unsigned , default = 32'h3834302c
+#define DNLP_21 ((0x50a5 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid21 : dnlp21 . unsigned , default = 32'h4b45403c
+#define DNLP_22 ((0x50a6 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid22 : dnlp22 . unsigned , default = 32'h605b5550
+#define DNLP_23 ((0x50a7 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid23 : dnlp23 . unsigned , default = 32'h80787068
+#define DNLP_24 ((0x50a8 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid24 : dnlp24 . unsigned , default = 32'ha0989088
+#define DNLP_25 ((0x50a9 << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid25 : dnlp25 . unsigned , default = 32'hb8b2aca6
+#define DNLP_26 ((0x50aa << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid26 : dnlp26 . unsigned , default = 32'hc8c4c0bc
+#define DNLP_27 ((0x50ab << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid27 : dnlp27 . unsigned , default = 32'hd4d2cecb
+#define DNLP_28 ((0x50ac << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid28 : dnlp28 . unsigned , default = 32'hdad8d7d6
+#define DNLP_29 ((0x50ad << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid29 : dnlp29 . unsigned , default = 32'he2e0dedc
+#define DNLP_30 ((0x50ae << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid30 : dnlp30 . unsigned , default = 32'hf0ece8e4
+#define DNLP_31 ((0x50af << 2) + 0xff000000)
+//Bit 31: 0, reg_dnlp_ygrid31 : dnlp31 . unsigned , default = 32'hfffcf8f4
+#define SHARP_SYNC_CTRL ((0x50b0 << 2) + 0xff000000)
+//Bit 15: 0, reg_sync_ctrl //reg_sync_ctrl: shaddow register control . unsigned , default = 0
+#define LC_INPUT_MUX ((0x50b1 << 2) + 0xff000000)
+//Bit 31:7 reserved
+//Bit 6:4 reg_lcinput_ysel //u3, local contrast luma input options 0: org_y; 1: gau_y; 2: gauadp_y; 3: edgadplpf_y; 4: nr_y;5: lti_y; 6: pk_y (before os);7: pk_y (after os) . unsigned , default = 5
+//Bit 3 reserved
+//Bit 2:0 reg_lcinput_csel //u3, local contrast chroma input options 0: org_c; 1: gau_c; 2: gauadp_c; 3: edgadplpf_c; 4: nr_c;5: cti_c; 6: pk_c . unsigned , default = 5
+#define NR_GAU_YH_COEF02 ((0x50b2 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:20 reg_nr_gau_yhcoef_0 //s10, luma's horizontal adaptive coef0 . signed , default = 32
+//Bit 19:10 reg_nr_gau_yhcoef_1 //s10, luma's horizontal adaptive coef1 . signed , default = 32
+//Bit 9: 0 reg_nr_gau_yhcoef_2 //s10, luma's horizontal adaptive coef2 . signed , default = 16
+#define NR_GAU_YH_COEF34 ((0x50b3 << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:10 reg_nr_gau_yhcoef_3 //s10, luma's horizontal adaptive coef3 . signed , default = 0
+//Bit 9: 0 reg_nr_gau_yhcoef_4 //s10, luma's horizontal adaptive coef4 . signed , default = 0
+#define NR_GAU_YV_COEF1 ((0x50b4 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:20 reg_nr_gau_yvcoef_0 //s10, luma's vertical adaptive coef0 . signed , default = 32
+//Bit 19:10 reg_nr_gau_yvcoef_1 //s10, luma's vertical adaptive coef1 . signed , default = 32
+//Bit 9: 0 reg_nr_gau_yvcoef_2 //s10, luma's vertical adaptive coef2 . signed , default = 16
+#define NR_GAU_CH_COEF02 ((0x50b5 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:20 reg_nr_gau_chcoef_0 //s10, chroma's horizontal adaptive coef0 . signed , default = 32
+//Bit 19:10 reg_nr_gau_chcoef_1 //s10, chroma's horizontal adaptive coef1 . signed , default = 32
+//Bit 9: 0 reg_nr_gau_chcoef_2 //s10, chroma's horizontal adaptive coef2 . signed , default = 16
+#define NR_GAU_CH_COEF34 ((0x50b6 << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19:10 reg_nr_gau_chcoef_3 //s10, chroma's horizontal adaptive coef3 . signed , default = 0
+//Bit 9: 0 reg_nr_gau_chcoef_4 //s10, chroma's horizontal adaptive coef4 . signed , default = 0
+#define NR_GAU_CV_COEF1 ((0x50b7 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:20 reg_nr_gau_cvcoef_0 //s10, chroma's vertical adaptive coef0 . signed , default = 32
+//Bit 19:10 reg_nr_gau_cvcoef_1 //s10, chroma's vertical adaptive coef1 . signed , default = 32
+//Bit 9: 0 reg_nr_gau_cvcoef_2 //s10, chroma's vertical adaptive coef2 . signed , default = 16
+#define SHARP_DB_FLT_CTRL1 ((0x50b8 << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:16 reg_nrdeband_noise_rs // unsigned , default = 2
+//Bit 15:12 reg_nrdeband_randgain // unsigned , default = 8
+//Bit 11 reserved
+//Bit 10: 8 reserved
+//Bit 7 reserved
+//Bit 6: 4 reserved
+//Bit 3 reserved
+//Bit 2: 0 reserved
+#define SHARP_DB_FLT_LUMA_THRD ((0x50b9 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_luma_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_luma_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_luma_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_luma_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else
+#define SHARP_DB_FLT_CHRM_THRD ((0x50ba << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_chrm_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_chrm_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_chrm_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_chrm_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif
+#define LC_TOP_CTRL ((0x50c0 << 2) + 0xff000000)
+ //Bit 31 :8 reg_lc_misc U RW default = 'h0
+ //Bit 7 :5 reserved U RW default = 'h0 None
+ //Bit 4 reg_lc_enable U RW default = 'h1 enable signal for local contrast enhancement, 1-enable; 0 disable
+ //Bit 3 :1 reserved U RW default = 'h0 None
+ //Bit 0 reg_lc_blkblend_mode U RW default = 'h1 use bilinear interpolation between blocks, 0: no interpolation 1: blender enabled
+#define LC_HV_NUM ((0x50c1 << 2) + 0xff000000)
+ //Bit 31 :13 reserved U RW default = 'h0 None
+ //Bit 12 :8 reg_lc_blk_hnum U RW default = 'hc lc processing region number of V, maximum to (STA_LEN_V-1) (0~8)
+ //Bit 7 :5 reserved U RW default = 'h0 None
+ //Bit 4 :0 reg_lc_blk_vnum U RW default = 'h8 lc processing region number of H, maximum to (STA_LEN_H-1) (0~12)
+#define LC_SAT_LUT_0_1 ((0x50c2 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_0 U RW default = 'hc saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_1 U RW default = 'h20 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_2_3 ((0x50c3 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_2 U RW default = 'h38 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_3 U RW default = 'h54 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_4_5 ((0x50c4 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_4 U RW default = 'h73 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_5 U RW default = 'h95 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_6_7 ((0x50c5 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_6 U RW default = 'hb9 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_7 U RW default = 'hdf saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_8_9 ((0x50c6 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_8 U RW default = 'h107 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_9 U RW default = 'h131 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_10_11 ((0x50c7 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_10 U RW default = 'h15c saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_11 U RW default = 'h189 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_12_13 ((0x50c8 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_12 U RW default = 'h1b8 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_13 U RW default = 'h1e8 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_14_15 ((0x50c9 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_14 U RW default = 'h219 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_15 U RW default = 'h24c saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_16_17 ((0x50ca << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_16 U RW default = 'h280 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_17 U RW default = 'h2b6 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_18_19 ((0x50cb << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_18 U RW default = 'h2ec saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_19 U RW default = 'h324 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_20_21 ((0x50cc << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_20 U RW default = 'h35d saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_21 U RW default = 'h397 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_22_23 ((0x50cd << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_22 U RW default = 'h3d2 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_23 U RW default = 'h40e saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_24_25 ((0x50ce << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_24 U RW default = 'h44b saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_25 U RW default = 'h489 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_26_27 ((0x50cf << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_26 U RW default = 'h4c8 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_27 U RW default = 'h507 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_28_29 ((0x50d0 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_28 U RW default = 'h548 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_29 U RW default = 'h58a saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_30_31 ((0x50d1 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_30 U RW default = 'h5cd saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_31 U RW default = 'h610 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_32_33 ((0x50d2 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_32 U RW default = 'h654 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_33 U RW default = 'h69a saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_34_35 ((0x50d3 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_34 U RW default = 'h6e0 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_35 U RW default = 'h726 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_36_37 ((0x50d4 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_36 U RW default = 'h76e saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_37 U RW default = 'h7b6 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_38_39 ((0x50d5 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_38 U RW default = 'h7ff saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_39 U RW default = 'h849 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_40_41 ((0x50d6 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_40 U RW default = 'h894 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_41 U RW default = 'h8df saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_42_43 ((0x50d7 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_42 U RW default = 'h92b saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_43 U RW default = 'h978 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_44_45 ((0x50d8 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_44 U RW default = 'h9c6 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_45 U RW default = 'ha14 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_46_47 ((0x50d9 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_46 U RW default = 'ha63 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_47 U RW default = 'hab2 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_48_49 ((0x50da << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_48 U RW default = 'hb02 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_49 U RW default = 'hb53 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_50_51 ((0x50db << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_50 U RW default = 'hba5 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_51 U RW default = 'hbf7 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_52_53 ((0x50dc << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_52 U RW default = 'hc4a saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_53 U RW default = 'hc9d saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_54_55 ((0x50dd << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_54 U RW default = 'hcf1 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_55 U RW default = 'hd46 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_56_57 ((0x50de << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_56 U RW default = 'hd9b saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_57 U RW default = 'hdf1 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_58_59 ((0x50df << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_58 U RW default = 'he47 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_59 U RW default = 'he9e saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_60_61 ((0x50e0 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_satur_lut_60 U RW default = 'hef6 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_61 U RW default = 'hf4e saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_SAT_LUT_62 ((0x50e1 << 2) + 0xff000000)
+ //Bit 31 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_satur_lut_62 U RW default = 'hfa7 saturation protection curve, normalized to 4096 as 1, default = y=x^1.2
+#define LC_CURVE_BLK_HIDX_0_1 ((0x50e2 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_hidx_0 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_1 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_HIDX_2_3 ((0x50e3 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_hidx_2 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_3 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_HIDX_4_5 ((0x50e4 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_hidx_4 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_5 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_HIDX_6_7 ((0x50e5 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_hidx_6 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_7 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_HIDX_8_9 ((0x50e6 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_hidx_8 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_9 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_HIDX_10_11 ((0x50e7 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_hidx_10 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_11 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_HIDX_12 ((0x50e8 << 2) + 0xff000000)
+ //Bit 31 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_hidx_12 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_VIDX_0_1 ((0x50e9 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_vidx_0 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_vidx_1 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_VIDX_2_3 ((0x50ea << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_vidx_2 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_vidx_3 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_VIDX_4_5 ((0x50eb << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_vidx_4 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_vidx_5 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_VIDX_6_7 ((0x50ec << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :16 reg_lc_blk_vidx_6 U RW default = 'h0 block boundary x-index
+ //Bit 15 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_vidx_7 U RW default = 'h0 block boundary x-index
+#define LC_CURVE_BLK_VIDX_8 ((0x50ed << 2) + 0xff000000)
+ //Bit 31 :14 reserved U RW default = 'h0 None
+ //Bit 13 :0 reg_lc_blk_vidx_8 U RW default = 'h0 block boundary x-index
+#define LC_YUV2RGB_MAT_0_1 ((0x50ee << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_yuv2rgb_mat3x3_0 S RW default = 1192 yuv2rgb 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_1 S RW default = 'h0 yuv2rgb 3x3 matrix
+#define LC_YUV2RGB_MAT_2_3 ((0x50ef << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_yuv2rgb_mat3x3_2 S RW default = 1836 yuv2rgb 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_3 S RW default = 1192 yuv2rgb 3x3 matrix
+#define LC_YUV2RGB_MAT_4_5 ((0x50f0 << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_yuv2rgb_mat3x3_4 S RW default = -218 yuv2rgb 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_5 S RW default = -547 yuv2rgb 3x3 matrix
+#define LC_YUV2RGB_MAT_6_7 ((0x50f1 << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_yuv2rgb_mat3x3_6 S RW default = 1192 yuv2rgb 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_7 S RW default = '2166 yuv2rgb 3x3 matrix
+#define LC_YUV2RGB_MAT_8 ((0x50f2 << 2) + 0xff000000)
+ //Bit 31 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_yuv2rgb_mat3x3_8 S RW default = 'h0 yuv2rgb 3x3 matrix
+#define LC_RGB2YUV_MAT_0_1 ((0x50f3 << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_rgb2yuv_mat3x3_0 S RW default = 187 rgb2yuv 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_1 S RW default = 629 rgb2yuv 3x3 matrix
+#define LC_RGB2YUV_MAT_2_3 ((0x50f4 << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_rgb2yuv_mat3x3_2 S RW default = 63 rgb2yuv 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_3 S RW default = -103 rgb2yuv 3x3 matrix
+#define LC_RGB2YUV_MAT_4_5 ((0x50f5 << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_rgb2yuv_mat3x3_4 S RW default = -346 rgb2yuv 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_5 S RW default = 450 rgb2yuv 3x3 matrix
+#define LC_RGB2YUV_MAT_6_7 ((0x50f6 << 2) + 0xff000000)
+ //Bit 31 :29 reserved U RW default = 'h0 None
+ //Bit 28 :16 reg_lc_rgb2yuv_mat3x3_6 S RW default = 450 rgb2yuv 3x3 matrix
+ //Bit 15 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_7 S RW default = -409 rgb2yuv 3x3 matrix
+#define LC_RGB2YUV_MAT_8 ((0x50f7 << 2) + 0xff000000)
+ //Bit 31 :13 reserved U RW default = 'h0 None
+ //Bit 12 :0 reg_lc_rgb2yuv_mat3x3_8 S RW default = 41 rgb2yuv 3x3 matrix
+#define LC_YUV2RGB_OFST ((0x50f8 << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_yuv2rgb_ofset_0 U RW default = 'h40 yuv2rgb pre-offset to yuv,
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_yuv2rgb_ofset_1 U RW default = 'h200 yuv2rgb pre-offset to yuv,
+#define LC_YUV2RGB_CLIP ((0x50f9 << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :28 reg_lc_yuv2rgb_rs U RW default = 'h0 matrix normalization right shift extra bits, norm= (1<<(8+rs))
+ //Bit 27 :16 reg_lc_yuv2rgb_clip_0 U RW default = 'h0 yuv2rgb converted RGB clipping range
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_yuv2rgb_clip_1 U RW default = 'h3ff yuv2rgb converted RGB clipping range
+#define LC_RGB2YUV_OFST ((0x50fa << 2) + 0xff000000)
+ //Bit 31 :28 reserved U RW default = 'h0 None
+ //Bit 27 :16 reg_lc_rgb2yuv_ofset_0 U RW default = 'h40 rgb2yuv post-offset to yuv,
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_rgb2yuv_ofset_1 U RW default = 'h200 rgb2yuv post-offset to yuv,
+#define LC_RGB2YUV_CLIP ((0x50fb << 2) + 0xff000000)
+ //Bit 31 :30 reserved U RW default = 'h0 None
+ //Bit 29 :28 reg_lc_rgb2yuv_rs U RW default = 'h0 matrix normalization right shift extra bits, norm= (1<<(10+rs))
+ //Bit 27 :16 reg_lc_rgb2yuv_clip_0 U RW default = 'h0 rgb2yuv converted YUV clipping range
+ //Bit 15 :12 reserved U RW default = 'h0 None
+ //Bit 11 :0 reg_lc_rgb2yuv_clip_1 U RW default = 'h3ff rgb2yuv converted YUV clipping range
+#define LC_MAP_RAM_CTRL ((0x50fc << 2) + 0xff000000)
+#define LC_MAP_RAM_ADDR ((0x50fd << 2) + 0xff000000)
+#define LC_MAP_RAM_DATA ((0x50fe << 2) + 0xff000000)
+#define SHARP_FMETER_CTRL ((0x5089 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11:10 reg_fmeter_vwin_mm //u2, vertical window size, 0:1 cloumn, 1:3cloumn, 2or3: 5cloumn .unsigned , default = 0
+//Bit 9 : 8 reg_fmeter_hwin_mm //u2, horizontal window size, 0:1x7, 1:1x9, 2or3: 1x11 .unsigned , default = 0
+//Bit 7 reg_fmeter_d2_mode //u1, selectino filter D2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 6 reg_fmeter_v2_mode //u1, selectino filter V2, 0: [0 -2 0 0 2], 1: [-2 0 0 0 2] .unsigned , default = 0
+//Bit 5: 4 reg_fmeter_h2_mode //u2, selection filter H2, 0: [0 0 0 -2 0 0 2 0 0], 1: [-2 0 0 0 2], 2or3: [0-2 0 0 0 0 0 2 0] .unsigned , default = 0
+//Bit 3: 1 reserved
+//Bit 0 reg_freq_meter_en //u1, freq meter enable .unsigned , default = 0
+#define SHARP_FMETER_WIN_HOR ((0x508a << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_fmeter_xwin_ed //u13, window location: hend .unsigned , default = 1920
+//Bit 15:13 reserved
+//Bit 12: 0 reg_fmeter_xwin_st //u13, window location: hstart .unsigned , default = 0
+#define SHARP_FMETER_WIN_VER ((0x508b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_fmeter_ywin_ed //u14, window location: vend .unsigned , default = 1080
+//Bit 15:13 reserved
+//Bit 12: 0 reg_fmeter_ywin_st //u14, window location: vstart .unsigned , default = 0
+#define SHARP_FMETER_CORING ((0x508c << 2) + 0xff000000)
+//Bit 31:24 reg_fmeter_low_bound //u8, low bound for threshold .unsigned , default = 4
+//Bit 23:16 reg_fmeter_coring_d //u8, coring of diff before compare with threhold for diagonal frequency .unsigned , default = 4
+//Bit 15:8 reg_fmeter_coring_v //u8, coring of diff before compare with threhold for vertical frequency .unsigned , default = 4
+//Bit 7: 0 reg_fmeter_coring_h //u8, coring of diff before compare with threhold for horizontal frequency .unsigned , default = 4
+#define SHARP_FMETER_RATIO_H ((0x508d << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:16 reg_fmeter_ratio_h2 //u6, ratio for threshold calc. for horizontal frequency, 16 is normalized as "1" .unsigned , default = 16
+//Bit 15:14 reserved
+//Bit 13: 8 reg_fmeter_ratio_h1 //u6, ratio for threshold calc. for horizontal frequency, 16 is normalized as "1" .unsigned , default = 16
+//Bit 7 : 6 reserved
+//Bit 5 : 0 reg_fmeter_ratio_h0 //u6, ratio for threshold calc. for horizontal frequency, 16 is normalized as "1" .unsigned , default = 16
+#define SHARP_FMETER_RATIO_V ((0x508e << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:16 reg_fmeter_ratio_v2 //u6, ratio for threshold calc. for vertical frequency, 16 is normalized as "1" .unsigned , default = 16
+//Bit 15:14 reserved
+//Bit 13: 8 reg_fmeter_ratio_v1 //u6, ratio for threshold calc. for vertical frequency, 16 is normalized as "1" .unsigned , default = 16
+//Bit 7 : 6 reserved
+//Bit 5 : 0 reg_fmeter_ratio_v0 //u6, ratio for threshold calc. for vertical frequency, 16 is normalized as "1" .unsigned , default = 16
+#define SHARP_FMETER_RATIO_D ((0x508f << 2) + 0xff000000)
+//Bit 31:22 reserved
+//Bit 21:16 reg_fmeter_ratio_d2 //u6, ratio for threshold calc. for diagonal frequency, 16 is normalized as "1" .unsigned , default = 16
+//Bit 15:14 reserved
+//Bit 13: 8 reg_fmeter_ratio_d1 //u6, ratio for threshold calc. for diagonal frequency, 16 is normalized as "1" .unsigned , default = 16
+//Bit 7 : 6 reserved
+//Bit 5 : 0 reg_fmeter_ratio_d0 //u6, ratio for threshold calc. for diagonal frequency, 16 is normalized as "1" .unsigned , default = 16
+#define SHARP_RO_FMETER_HCNT_TYPE0 ((0x5046 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_hcnt_type0 //u32, count for horizontal frequency
+#define SHARP_RO_FMETER_HCNT_TYPE1 ((0x5047 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_hcnt_type1 //u32, count for horizontal frequency
+#define SHARP_RO_FMETER_HCNT_TYPE2 ((0x5048 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_hcnt_type2 //u32, count for horizontal frequency
+#define SHARP_RO_FMETER_HCNT_TYPE3 ((0x5049 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_hcnt_type3 //u32, count for horizontal frequency
+#define SHARP_RO_FMETER_VCNT_TYPE0 ((0x504a << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_vcnt_type0 //u32, count for vertical frequency
+#define SHARP_RO_FMETER_VCNT_TYPE1 ((0x504b << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_vcnt_type1 //u32, count for vertical frequency
+#define SHARP_RO_FMETER_VCNT_TYPE2 ((0x504c << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_vcnt_type2 //u32, count for vertical frequency
+#define SHARP_RO_FMETER_VCNT_TYPE3 ((0x504d << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_vcnt_type3 //u32, count for vertical frequency
+#define SHARP_RO_FMETER_PDCNT_TYPE0 ((0x504e << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_pdcnt_type0 //u32, count for positive diagonal frequency
+#define SHARP_RO_FMETER_PDCNT_TYPE1 ((0x504f << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_pdcnt_type1 //u32, count for positive diagonal frequency
+#define SHARP_RO_FMETER_PDCNT_TYPE2 ((0x5050 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_pdcnt_type2 //u32, count for positive diagonal frequency
+#define SHARP_RO_FMETER_PDCNT_TYPE3 ((0x5051 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_pdcnt_type3 //u32, count for positive diagonal frequency
+#define SHARP_RO_FMETER_NDCNT_TYPE0 ((0x5052 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_ndcnt_type0 //u32, count for negitive diagonal frequency
+#define SHARP_RO_FMETER_NDCNT_TYPE1 ((0x5053 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_ndcnt_type1 //u32, count for negitive diagonal frequency
+#define SHARP_RO_FMETER_NDCNT_TYPE2 ((0x5054 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_ndcnt_type2 //u32, count for negitive diagonal frequency
+#define SHARP_RO_FMETER_NDCNT_TYPE3 ((0x5055 << 2) + 0xff000000)
+//Bit 31:0 ro_fmeter_ndcnt_type3 //u32, count for negitive diagonal frequency
+//
+// Closing file: sharp_regs.h
+//
+
+#define SRSHARP0_SHARP_HVSIZE (SRSHARP0_OFFSET + SHARP_HVSIZE ) //0x00 //
+#define SRSHARP0_SHARP_HVBLANK_NUM (SRSHARP0_OFFSET + SHARP_HVBLANK_NUM ) //0x01 //
+#define SRSHARP0_NR_GAUSSIAN_MODE (SRSHARP0_OFFSET + NR_GAUSSIAN_MODE ) //0x02 //
+//`define SRSHARP0_PK_HVCON_LPF_MODE (`SRSHARP0_OFFSET + `PK_HVCON_LPF_MODE ) //8'h03 //
+//`define SRSHARP0_PK_CON_BLEND_GAIN (`SRSHARP0_OFFSET + `PK_CON_BLEND_GAIN ) //8'h04 //
+#define SRSHARP0_PK_CON_2CIRHPGAIN_TH_RATE (SRSHARP0_OFFSET + PK_CON_2CIRHPGAIN_TH_RATE ) //0x05 //
+#define SRSHARP0_PK_CON_2CIRHPGAIN_LIMIT (SRSHARP0_OFFSET + PK_CON_2CIRHPGAIN_LIMIT ) //0x06 //
+#define SRSHARP0_PK_CON_2CIRBPGAIN_TH_RATE (SRSHARP0_OFFSET + PK_CON_2CIRBPGAIN_TH_RATE ) //0x07 //
+#define SRSHARP0_PK_CON_2CIRBPGAIN_LIMIT (SRSHARP0_OFFSET + PK_CON_2CIRBPGAIN_LIMIT ) //0x08 //
+#define SRSHARP0_PK_CON_2DRTHPGAIN_TH_RATE (SRSHARP0_OFFSET + PK_CON_2DRTHPGAIN_TH_RATE ) //0x09 //
+#define SRSHARP0_PK_CON_2DRTHPGAIN_LIMIT (SRSHARP0_OFFSET + PK_CON_2DRTHPGAIN_LIMIT ) //0x0a //
+#define SRSHARP0_PK_CON_2DRTBPGAIN_TH_RATE (SRSHARP0_OFFSET + PK_CON_2DRTBPGAIN_TH_RATE ) //0x0b //
+#define SRSHARP0_PK_CON_2DRTBPGAIN_LIMIT (SRSHARP0_OFFSET + PK_CON_2DRTBPGAIN_LIMIT ) //0x0c //
+#define SRSHARP0_PK_CIRFB_LPF_MODE (SRSHARP0_OFFSET + PK_CIRFB_LPF_MODE ) //0x0d //
+#define SRSHARP0_PK_DRTFB_LPF_MODE (SRSHARP0_OFFSET + PK_DRTFB_LPF_MODE ) //0x0e //
+#define SRSHARP0_PK_CIRFB_HP_CORING (SRSHARP0_OFFSET + PK_CIRFB_HP_CORING ) //0x0f //
+#define SRSHARP0_PK_CIRFB_BP_CORING (SRSHARP0_OFFSET + PK_CIRFB_BP_CORING ) //0x10 //
+#define SRSHARP0_PK_DRTFB_HP_CORING (SRSHARP0_OFFSET + PK_DRTFB_HP_CORING ) //0x11 //
+#define SRSHARP0_PK_DRTFB_BP_CORING (SRSHARP0_OFFSET + PK_DRTFB_BP_CORING ) //0x12 //
+#define SRSHARP0_PK_CIRFB_BLEND_GAIN (SRSHARP0_OFFSET + PK_CIRFB_BLEND_GAIN ) //0x13 //
+#define SRSHARP0_NR_ALPY_SSD_GAIN_OFST (SRSHARP0_OFFSET + NR_ALPY_SSD_GAIN_OFST ) //0x14 //
+#define SRSHARP0_NR_ALP0Y_ERR2CURV_TH_RATE (SRSHARP0_OFFSET + NR_ALP0Y_ERR2CURV_TH_RATE ) //0x15 //
+#define SRSHARP0_NR_ALP0Y_ERR2CURV_LIMIT (SRSHARP0_OFFSET + NR_ALP0Y_ERR2CURV_LIMIT ) //0x16 //
+#define SRSHARP0_NR_ALP0C_ERR2CURV_TH_RATE (SRSHARP0_OFFSET + NR_ALP0C_ERR2CURV_TH_RATE ) //0x17 //
+#define SRSHARP0_NR_ALP0C_ERR2CURV_LIMIT (SRSHARP0_OFFSET + NR_ALP0C_ERR2CURV_LIMIT ) //0x18 //
+#define SRSHARP0_NR_ALP0_MIN_MAX (SRSHARP0_OFFSET + NR_ALP0_MIN_MAX ) //0x19 //
+#define SRSHARP0_NR_ALP1_MIERR_CORING (SRSHARP0_OFFSET + NR_ALP1_MIERR_CORING ) //0x1a //
+#define SRSHARP0_NR_ALP1_ERR2CURV_TH_RATE (SRSHARP0_OFFSET + NR_ALP1_ERR2CURV_TH_RATE ) //0x1b //
+#define SRSHARP0_NR_ALP1_ERR2CURV_LIMIT (SRSHARP0_OFFSET + NR_ALP1_ERR2CURV_LIMIT ) //0x1c //
+#define SRSHARP0_NR_ALP1_MIN_MAX (SRSHARP0_OFFSET + NR_ALP1_MIN_MAX ) //0x1d //
+#define SRSHARP0_PK_ALP2_MIERR_CORING (SRSHARP0_OFFSET + PK_ALP2_MIERR_CORING ) //0x1e //
+#define SRSHARP0_PK_ALP2_ERR2CURV_TH_RATE (SRSHARP0_OFFSET + PK_ALP2_ERR2CURV_TH_RATE ) //0x1f //
+#define SRSHARP0_PK_ALP2_ERR2CURV_LIMIT (SRSHARP0_OFFSET + PK_ALP2_ERR2CURV_LIMIT ) //0x20 //
+#define SRSHARP0_PK_ALP2_MIN_MAX (SRSHARP0_OFFSET + PK_ALP2_MIN_MAX ) //0x21 //
+#define SRSHARP0_PK_FINALGAIN_HP_BP (SRSHARP0_OFFSET + PK_FINALGAIN_HP_BP ) //0x22 //
+#define SRSHARP0_PK_OS_HORZ_CORE_GAIN (SRSHARP0_OFFSET + PK_OS_HORZ_CORE_GAIN ) //0x23 //
+#define SRSHARP0_PK_OS_VERT_CORE_GAIN (SRSHARP0_OFFSET + PK_OS_VERT_CORE_GAIN ) //0x24 //
+#define SRSHARP0_PK_OS_ADPT_MISC (SRSHARP0_OFFSET + PK_OS_ADPT_MISC ) //0x25 //
+#define SRSHARP0_PK_OS_STATIC (SRSHARP0_OFFSET + PK_OS_STATIC ) //0x26 //
+#define SRSHARP0_PK_NR_ENABLE (SRSHARP0_OFFSET + PK_NR_ENABLE ) //0x27 //
+#define SRSHARP0_PK_DRT_SAD_MISC (SRSHARP0_OFFSET + PK_DRT_SAD_MISC ) //0x28 //
+#define SRSHARP0_NR_TI_DNLP_BLEND (SRSHARP0_OFFSET + NR_TI_DNLP_BLEND ) //0x29 //
+#define SRSHARP0_LTI_DIR_CORE_ALPHA (SRSHARP0_OFFSET + LTI_DIR_CORE_ALPHA ) //0x2a //
+#define SRSHARP0_CTI_DIR_ALPHA (SRSHARP0_OFFSET + CTI_DIR_ALPHA ) //0x2b //
+#define SRSHARP0_LTI_CTI_DF_GAIN (SRSHARP0_OFFSET + LTI_CTI_DF_GAIN ) //0x2c //
+#define SRSHARP0_LTI_CTI_DIR_AC_DBG (SRSHARP0_OFFSET + LTI_CTI_DIR_AC_DBG ) //0x2d //
+#define SRSHARP0_HCTI_FLT_CLP_DC (SRSHARP0_OFFSET + HCTI_FLT_CLP_DC ) //0x2e //
+#define SRSHARP0_HCTI_BST_GAIN (SRSHARP0_OFFSET + HCTI_BST_GAIN ) //0x2f //
+#define SRSHARP0_HCTI_BST_CORE (SRSHARP0_OFFSET + HCTI_BST_CORE ) //0x30 //
+#define SRSHARP0_HCTI_CON_2_GAIN_0 (SRSHARP0_OFFSET + HCTI_CON_2_GAIN_0 ) //0x31 //
+#define SRSHARP0_HCTI_CON_2_GAIN_1 (SRSHARP0_OFFSET + HCTI_CON_2_GAIN_1 ) //0x32 //
+#define SRSHARP0_HCTI_OS_MARGIN (SRSHARP0_OFFSET + HCTI_OS_MARGIN ) //0x33 //
+#define SRSHARP0_HLTI_FLT_CLP_DC (SRSHARP0_OFFSET + HLTI_FLT_CLP_DC ) //0x34 //
+#define SRSHARP0_HLTI_BST_GAIN (SRSHARP0_OFFSET + HLTI_BST_GAIN ) //0x35 //
+#define SRSHARP0_HLTI_BST_CORE (SRSHARP0_OFFSET + HLTI_BST_CORE ) //0x36 //
+#define SRSHARP0_HLTI_CON_2_GAIN_0 (SRSHARP0_OFFSET + HLTI_CON_2_GAIN_0 ) //0x37 //
+#define SRSHARP0_HLTI_CON_2_GAIN_1 (SRSHARP0_OFFSET + HLTI_CON_2_GAIN_1 ) //0x38 //
+#define SRSHARP0_HLTI_OS_MARGIN (SRSHARP0_OFFSET + HLTI_OS_MARGIN ) //0x39 //
+#define SRSHARP0_VLTI_FLT_CON_CLP (SRSHARP0_OFFSET + VLTI_FLT_CON_CLP ) //0x3a //
+#define SRSHARP0_VLTI_BST_GAIN (SRSHARP0_OFFSET + VLTI_BST_GAIN ) //0x3b //
+#define SRSHARP0_VLTI_BST_CORE (SRSHARP0_OFFSET + VLTI_BST_CORE ) //0x3c //
+#define SRSHARP0_VLTI_CON_2_GAIN_0 (SRSHARP0_OFFSET + VLTI_CON_2_GAIN_0 ) //0x3d //
+#define SRSHARP0_VLTI_CON_2_GAIN_1 (SRSHARP0_OFFSET + VLTI_CON_2_GAIN_1 ) //0x3e //
+#define SRSHARP0_VCTI_FLT_CON_CLP (SRSHARP0_OFFSET + VCTI_FLT_CON_CLP ) //0x3f //
+#define SRSHARP0_VCTI_BST_GAIN (SRSHARP0_OFFSET + VCTI_BST_GAIN ) //0x40 //
+#define SRSHARP0_VCTI_BST_CORE (SRSHARP0_OFFSET + VCTI_BST_CORE ) //0x41 //
+#define SRSHARP0_VCTI_CON_2_GAIN_0 (SRSHARP0_OFFSET + VCTI_CON_2_GAIN_0 ) //0x42 //
+#define SRSHARP0_VCTI_CON_2_GAIN_1 (SRSHARP0_OFFSET + VCTI_CON_2_GAIN_1 ) //0x43 //
+#define SRSHARP0_SHARP_3DLIMIT (SRSHARP0_OFFSET + SHARP_3DLIMIT ) //0x44 //
+#define SRSHARP0_DNLP_EN (SRSHARP0_OFFSET + DNLP_EN ) //0x45 //
+//`define SRSHARP0_DNLP_00 (`SRSHARP0_OFFSET + `DNLP_00 ) //8'h46 //
+//`define SRSHARP0_DNLP_01 (`SRSHARP0_OFFSET + `DNLP_01 ) //8'h47 //
+//`define SRSHARP0_DNLP_02 (`SRSHARP0_OFFSET + `DNLP_02 ) //8'h48 //
+//`define SRSHARP0_DNLP_03 (`SRSHARP0_OFFSET + `DNLP_03 ) //8'h49 //
+//`define SRSHARP0_DNLP_04 (`SRSHARP0_OFFSET + `DNLP_04 ) //8'h4a //
+//`define SRSHARP0_DNLP_05 (`SRSHARP0_OFFSET + `DNLP_05 ) //8'h4b //
+//`define SRSHARP0_DNLP_06 (`SRSHARP0_OFFSET + `DNLP_06 ) //8'h4c //
+//`define SRSHARP0_DNLP_07 (`SRSHARP0_OFFSET + `DNLP_07 ) //8'h4d //
+//`define SRSHARP0_DNLP_08 (`SRSHARP0_OFFSET + `DNLP_08 ) //8'h4e //
+//`define SRSHARP0_DNLP_09 (`SRSHARP0_OFFSET + `DNLP_09 ) //8'h4f //
+//`define SRSHARP0_DNLP_10 (`SRSHARP0_OFFSET + `DNLP_10 ) //8'h50 //
+//`define SRSHARP0_DNLP_11 (`SRSHARP0_OFFSET + `DNLP_11 ) //8'h51 //
+//`define SRSHARP0_DNLP_12 (`SRSHARP0_OFFSET + `DNLP_12 ) //8'h52 //
+//`define SRSHARP0_DNLP_13 (`SRSHARP0_OFFSET + `DNLP_13 ) //8'h53 //
+//`define SRSHARP0_DNLP_14 (`SRSHARP0_OFFSET + `DNLP_14 ) //8'h54 //
+//`define SRSHARP0_DNLP_15 (`SRSHARP0_OFFSET + `DNLP_15 ) //8'h55 //
+#define SRSHARP0_DEMO_CRTL (SRSHARP0_OFFSET + DEMO_CRTL ) //0x56 //
+#define SRSHARP0_SHARP_SR2_CTRL (SRSHARP0_OFFSET + SHARP_SR2_CTRL ) //0x57 //
+#define SRSHARP0_SHARP_SR2_YBIC_HCOEF0 (SRSHARP0_OFFSET + SHARP_SR2_YBIC_HCOEF0 ) //0x58
+#define SRSHARP0_SHARP_SR2_YBIC_HCOEF1 (SRSHARP0_OFFSET + SHARP_SR2_YBIC_HCOEF1 ) //0x59 //
+#define SRSHARP0_SHARP_SR2_CBIC_HCOEF0 (SRSHARP0_OFFSET + SHARP_SR2_CBIC_HCOEF0 ) //0x5a //
+#define SRSHARP0_SHARP_SR2_CBIC_HCOEF1 (SRSHARP0_OFFSET + SHARP_SR2_CBIC_HCOEF1 ) //0x5b //
+#define SRSHARP0_SHARP_SR2_YBIC_VCOEF0 (SRSHARP0_OFFSET + SHARP_SR2_YBIC_VCOEF0 ) //0x5c //
+#define SRSHARP0_SHARP_SR2_YBIC_VCOEF1 (SRSHARP0_OFFSET + SHARP_SR2_YBIC_VCOEF1 ) //0x5d //
+#define SRSHARP0_SHARP_SR2_CBIC_VCOEF0 (SRSHARP0_OFFSET + SHARP_SR2_CBIC_VCOEF0 ) //0x5e //
+#define SRSHARP0_SHARP_SR2_CBIC_VCOEF1 (SRSHARP0_OFFSET + SHARP_SR2_CBIC_VCOEF1 ) //0x5f //
+#define SRSHARP0_SHARP_SR2_MISC (SRSHARP0_OFFSET + SHARP_SR2_MISC ) //0x60 //
+#define SRSHARP0_SR3_SAD_CTRL (SRSHARP0_OFFSET + SHARP_SR3_SAD_CTRL ) // 0x61 //
+#define SRSHARP0_SR3_PK_CTRL0 (SRSHARP0_OFFSET + SHARP_SR3_PK_CTRL0 ) // 0x62
+#define SRSHARP0_SR3_PK_CTRL1 (SRSHARP0_OFFSET + SHARP_SR3_PK_CTRL1 ) // 0x63
+#define SRSHARP0_DEJ_CTRL (SRSHARP0_OFFSET + SHARP_DEJ_CTRL ) // 0x64
+#define SRSHARP0_DEJ_ALPHA (SRSHARP0_OFFSET + SHARP_DEJ_ALPHA ) // 0x65
+#define SRSHARP0_SR3_DRTLPF_EN (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_EN ) // 0x66
+#define SRSHARP0_SR3_DRTLPF_ALPHA_0 (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_ALPHA_0 ) // 0x67
+#define SRSHARP0_SR3_DRTLPF_ALPHA_1 (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_ALPHA_1 ) // 0x68
+#define SRSHARP0_SR3_DRTLPF_ALPHA_2 (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_ALPHA_2 ) // 0x69
+#define SRSHARP0_SR3_DRTLPF_ALPHA_OFST (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_ALPHA_OFST ) // 0x6a
+#define SRSHARP0_SR3_DERING_CTRL (SRSHARP0_OFFSET + SHARP_SR3_DERING_CTRL ) // 0x6b
+#define SRSHARP0_SR3_DERING_LUMA2PKGAIN_0TO3 (SRSHARP0_OFFSET + SHARP_SR3_DERING_LUMA2PKGAIN_0TO3 ) // 0x6c
+#define SRSHARP0_SR3_DERING_LUMA2PKGAIN_4TO6 (SRSHARP0_OFFSET + SHARP_SR3_DERING_LUMA2PKGAIN_4TO6 ) // 0x6d
+#define SRSHARP0_SR3_DERING_LUMA2PKOS_0TO3 (SRSHARP0_OFFSET + SHARP_SR3_DERING_LUMA2PKOS_0TO3 ) // 0x6e
+#define SRSHARP0_SR3_DERING_LUMA2PKOS_4TO6 (SRSHARP0_OFFSET + SHARP_SR3_DERING_LUMA2PKOS_4TO6 ) // 0x6f
+#define SRSHARP0_SR3_DERING_GAINVS_MADSAD (SRSHARP0_OFFSET + SHARP_SR3_DERING_GAINVS_MADSAD ) // 0x70
+#define SRSHARP0_SR3_DERING_GAINVS_VR2MAX (SRSHARP0_OFFSET + SHARP_SR3_DERING_GAINVS_VR2MAX ) // 0x71
+#define SRSHARP0_SR3_DERING_PARAM0 (SRSHARP0_OFFSET + SHARP_SR3_DERING_PARAM0 ) // 0x72
+#define SRSHARP0_SR3_DRTLPF_THETA (SRSHARP0_OFFSET + SHARP_SR3_DRTLPF_THETA ) // 0x73
+#define SRSHARP0_SATPRT_CTRL (SRSHARP0_OFFSET + SHARP_SATPRT_CTRL ) // 0x74
+#define SRSHARP0_SATPRT_DIVM (SRSHARP0_OFFSET + SHARP_SATPRT_DIVM ) // 0x75
+#define SRSHARP0_DB_FLT_CTRL (SRSHARP0_OFFSET + SHARP_DB_FLT_CTRL ) // 0x77
+//`define SRSHARP0_DB_FLT_YC_THRD (`SRSHARP0_OFFSET + `SHARP_DB_FLT_YC_THRD ) // 8'h78
+#define SRSHARP0_DB_FLT_CTRL1 (SRSHARP0_OFFSET + SHARP_DB_FLT_CTRL1 ) // 0xb8
+#define SRSHARP0_DB_FLT_LUMA_THRD (SRSHARP0_OFFSET + SHARP_DB_FLT_LUMA_THRD ) // 0xb9
+#define SRSHARP0_DB_FLT_CHRM_THRD (SRSHARP0_OFFSET + SHARP_DB_FLT_CHRM_THRD ) // 0xba
+#define SRSHARP0_DB_FLT_RANDLUT (SRSHARP0_OFFSET + SHARP_DB_FLT_RANDLUT ) // 0x79
+#define SRSHARP0_DB_FLT_PXI_THRD (SRSHARP0_OFFSET + SHARP_DB_FLT_PXI_THRD ) // 0x7a
+#define SRSHARP0_DB_FLT_SEED_Y (SRSHARP0_OFFSET + SHARP_DB_FLT_SEED_Y ) // 0x7b
+#define SRSHARP0_DB_FLT_SEED_U (SRSHARP0_OFFSET + SHARP_DB_FLT_SEED_U ) // 0x7c
+#define SRSHARP0_DB_FLT_SEED_V (SRSHARP0_OFFSET + SHARP_DB_FLT_SEED_V ) // 0x7d
+#define SRSHARP0_PKGAIN_VSLUMA_LUT_L (SRSHARP0_OFFSET + SHARP_PKGAIN_VSLUMA_LUT_L ) // 0x7e
+#define SRSHARP0_PKGAIN_VSLUMA_LUT_H (SRSHARP0_OFFSET + SHARP_PKGAIN_VSLUMA_LUT_H ) // 0x7f
+#define SRSHARP0_PKOSHT_VSLUMA_LUT_L (SRSHARP0_OFFSET + SHARP_PKOSHT_VSLUMA_LUT_L ) // 0x80
+#define SRSHARP0_PKOSHT_VSLUMA_LUT_H (SRSHARP0_OFFSET + SHARP_PKOSHT_VSLUMA_LUT_H ) // 0x81
+#define SRSHARP0_SATPRT_LMT_RGB1 (SRSHARP0_OFFSET + SHARP_SATPRT_LMT_RGB1 ) // 0x82
+#define SRSHARP0_SATPRT_LMT_RGB2 (SRSHARP0_OFFSET + SHARP_SATPRT_LMT_RGB2 ) // 0x83
+#define SRSHARP0_SHARP_GATE_CLK_CTRL_0 (SRSHARP0_OFFSET + SHARP_GATE_CLK_CTRL_0 ) // 0x84
+#define SRSHARP0_SHARP_GATE_CLK_CTRL_1 (SRSHARP0_OFFSET + SHARP_GATE_CLK_CTRL_1 ) // 0x85
+#define SRSHARP0_SHARP_GATE_CLK_CTRL_2 (SRSHARP0_OFFSET + SHARP_GATE_CLK_CTRL_2 ) // 0x86
+#define SRSHARP0_SHARP_GATE_CLK_CTRL_3 (SRSHARP0_OFFSET + SHARP_GATE_CLK_CTRL_3 ) // 0x87
+#define SRSHARP0_SHARP_DPS_CTRL (SRSHARP0_OFFSET + SHARP_DPS_CTRL ) // 0x88
+#define SRSHARP0_DNLP_00 (SRSHARP0_OFFSET + DNLP_00 ) // 0x90 //
+#define SRSHARP0_DNLP_01 (SRSHARP0_OFFSET + DNLP_01 ) // 0x91 //
+#define SRSHARP0_DNLP_02 (SRSHARP0_OFFSET + DNLP_02 ) // 0x92 //
+#define SRSHARP0_DNLP_03 (SRSHARP0_OFFSET + DNLP_03 ) // 0x93 //
+#define SRSHARP0_DNLP_04 (SRSHARP0_OFFSET + DNLP_04 ) // 0x94 //
+#define SRSHARP0_DNLP_05 (SRSHARP0_OFFSET + DNLP_05 ) // 0x95 //
+#define SRSHARP0_DNLP_06 (SRSHARP0_OFFSET + DNLP_06 ) // 0x96 //
+#define SRSHARP0_DNLP_07 (SRSHARP0_OFFSET + DNLP_07 ) // 0x97 //
+#define SRSHARP0_DNLP_08 (SRSHARP0_OFFSET + DNLP_08 ) // 0x98 //
+#define SRSHARP0_DNLP_09 (SRSHARP0_OFFSET + DNLP_09 ) // 0x99 //
+#define SRSHARP0_DNLP_10 (SRSHARP0_OFFSET + DNLP_10 ) // 0x9a //
+#define SRSHARP0_DNLP_11 (SRSHARP0_OFFSET + DNLP_11 ) // 0x9b //
+#define SRSHARP0_DNLP_12 (SRSHARP0_OFFSET + DNLP_12 ) // 0x9c //
+#define SRSHARP0_DNLP_13 (SRSHARP0_OFFSET + DNLP_13 ) // 0x9d //
+#define SRSHARP0_DNLP_14 (SRSHARP0_OFFSET + DNLP_14 ) // 0x9e //
+#define SRSHARP0_DNLP_15 (SRSHARP0_OFFSET + DNLP_15 ) // 0x9f //
+#define SRSHARP0_DNLP_16 (SRSHARP0_OFFSET + DNLP_16 ) // 0xa0 //
+#define SRSHARP0_DNLP_17 (SRSHARP0_OFFSET + DNLP_17 ) // 0xa1 //
+#define SRSHARP0_DNLP_18 (SRSHARP0_OFFSET + DNLP_18 ) // 0xa2 //
+#define SRSHARP0_DNLP_19 (SRSHARP0_OFFSET + DNLP_19 ) // 0xa3 //
+#define SRSHARP0_DNLP_20 (SRSHARP0_OFFSET + DNLP_20 ) // 0xa4 //
+#define SRSHARP0_DNLP_21 (SRSHARP0_OFFSET + DNLP_21 ) // 0xa5 //
+#define SRSHARP0_DNLP_22 (SRSHARP0_OFFSET + DNLP_22 ) // 0xa6 //
+#define SRSHARP0_DNLP_23 (SRSHARP0_OFFSET + DNLP_23 ) // 0xa7 //
+#define SRSHARP0_DNLP_24 (SRSHARP0_OFFSET + DNLP_24 ) // 0xa8 //
+#define SRSHARP0_DNLP_25 (SRSHARP0_OFFSET + DNLP_25 ) // 0xa9 //
+#define SRSHARP0_DNLP_26 (SRSHARP0_OFFSET + DNLP_26 ) // 0xaa //
+#define SRSHARP0_DNLP_27 (SRSHARP0_OFFSET + DNLP_27 ) // 0xab //
+#define SRSHARP0_DNLP_28 (SRSHARP0_OFFSET + DNLP_28 ) // 0xac //
+#define SRSHARP0_DNLP_29 (SRSHARP0_OFFSET + DNLP_29 ) // 0xad //
+#define SRSHARP0_DNLP_30 (SRSHARP0_OFFSET + DNLP_30 ) // 0xae //
+#define SRSHARP0_DNLP_31 (SRSHARP0_OFFSET + DNLP_31 ) // 0xaf //
+#define SRSHARP0_SHARP_SYNC_CTRL (SRSHARP0_OFFSET + SHARP_SYNC_CTRL ) // 0xb0 //
+#define SRSHARP0_LC_INPUT_MUX (SRSHARP0_OFFSET + LC_INPUT_MUX ) // 0xb1 //
+#define SRSHARP0_NR_GAU_YH_COEF02 (SRSHARP0_OFFSET + NR_GAU_YH_COEF02 ) // 0xb2 //
+#define SRSHARP0_NR_GAU_YH_COEF34 (SRSHARP0_OFFSET + NR_GAU_YH_COEF34 ) // 0xb3 //
+#define SRSHARP0_NR_GAU_YV_COEF1 (SRSHARP0_OFFSET + NR_GAU_YV_COEF1 ) // 0xb4 //
+#define SRSHARP0_NR_GAU_CH_COEF02 (SRSHARP0_OFFSET + NR_GAU_CH_COEF02 ) // 0xb5 //
+#define SRSHARP0_NR_GAU_CH_COEF34 (SRSHARP0_OFFSET + NR_GAU_CH_COEF34 ) // 0xb6 //
+#define SRSHARP0_NR_GAU_CV_COEF1 (SRSHARP0_OFFSET + NR_GAU_CV_COEF1 ) // 0xb7 //
+#define SRSHARP0_LC_TOP_CTRL (SRSHARP0_OFFSET + LC_TOP_CTRL ) // 0xc0 //
+#define SRSHARP0_LC_HV_NUM (SRSHARP0_OFFSET + LC_HV_NUM ) // 0xc1
+#define SRSHARP0_LC_SAT_LUT_0_1 (SRSHARP0_OFFSET + LC_SAT_LUT_0_1 ) // 0xc2
+#define SRSHARP0_LC_SAT_LUT_2_3 (SRSHARP0_OFFSET + LC_SAT_LUT_2_3 ) // 0xc3
+#define SRSHARP0_LC_SAT_LUT_4_5 (SRSHARP0_OFFSET + LC_SAT_LUT_4_5 ) // 0xc4
+#define SRSHARP0_LC_SAT_LUT_6_7 (SRSHARP0_OFFSET + LC_SAT_LUT_6_7 ) // 0xc5
+#define SRSHARP0_LC_SAT_LUT_8_9 (SRSHARP0_OFFSET + LC_SAT_LUT_8_9 ) // 0xc6
+#define SRSHARP0_LC_SAT_LUT_10_11 (SRSHARP0_OFFSET + LC_SAT_LUT_10_11 ) // 0xc7
+#define SRSHARP0_LC_SAT_LUT_12_13 (SRSHARP0_OFFSET + LC_SAT_LUT_12_13 ) // 0xc8
+#define SRSHARP0_LC_SAT_LUT_14_15 (SRSHARP0_OFFSET + LC_SAT_LUT_14_15 ) // 0xc9
+#define SRSHARP0_LC_SAT_LUT_16_17 (SRSHARP0_OFFSET + LC_SAT_LUT_16_17 ) // 0xca
+#define SRSHARP0_LC_SAT_LUT_18_19 (SRSHARP0_OFFSET + LC_SAT_LUT_18_19 ) // 0xcb
+#define SRSHARP0_LC_SAT_LUT_20_21 (SRSHARP0_OFFSET + LC_SAT_LUT_20_21 ) // 0xcc
+#define SRSHARP0_LC_SAT_LUT_22_23 (SRSHARP0_OFFSET + LC_SAT_LUT_22_23 ) // 0xcd
+#define SRSHARP0_LC_SAT_LUT_24_25 (SRSHARP0_OFFSET + LC_SAT_LUT_24_25 ) // 0xce
+#define SRSHARP0_LC_SAT_LUT_26_27 (SRSHARP0_OFFSET + LC_SAT_LUT_26_27 ) // 0xcf
+#define SRSHARP0_LC_SAT_LUT_28_29 (SRSHARP0_OFFSET + LC_SAT_LUT_28_29 ) // 0xd0
+#define SRSHARP0_LC_SAT_LUT_30_31 (SRSHARP0_OFFSET + LC_SAT_LUT_30_31 ) // 0xd1
+#define SRSHARP0_LC_SAT_LUT_32_33 (SRSHARP0_OFFSET + LC_SAT_LUT_32_33 ) // 0xd2
+#define SRSHARP0_LC_SAT_LUT_34_35 (SRSHARP0_OFFSET + LC_SAT_LUT_34_35 ) // 0xd3
+#define SRSHARP0_LC_SAT_LUT_36_37 (SRSHARP0_OFFSET + LC_SAT_LUT_36_37 ) // 0xd4
+#define SRSHARP0_LC_SAT_LUT_38_39 (SRSHARP0_OFFSET + LC_SAT_LUT_38_39 ) // 0xd5
+#define SRSHARP0_LC_SAT_LUT_40_41 (SRSHARP0_OFFSET + LC_SAT_LUT_40_41 ) // 0xd6
+#define SRSHARP0_LC_SAT_LUT_42_43 (SRSHARP0_OFFSET + LC_SAT_LUT_42_43 ) // 0xd7
+#define SRSHARP0_LC_SAT_LUT_44_45 (SRSHARP0_OFFSET + LC_SAT_LUT_44_45 ) // 0xd8
+#define SRSHARP0_LC_SAT_LUT_46_47 (SRSHARP0_OFFSET + LC_SAT_LUT_46_47 ) // 0xd9
+#define SRSHARP0_LC_SAT_LUT_48_49 (SRSHARP0_OFFSET + LC_SAT_LUT_48_49 ) // 0xda
+#define SRSHARP0_LC_SAT_LUT_50_51 (SRSHARP0_OFFSET + LC_SAT_LUT_50_51 ) // 0xdb
+#define SRSHARP0_LC_SAT_LUT_52_53 (SRSHARP0_OFFSET + LC_SAT_LUT_52_53 ) // 0xdc
+#define SRSHARP0_LC_SAT_LUT_54_55 (SRSHARP0_OFFSET + LC_SAT_LUT_54_55 ) // 0xdd
+#define SRSHARP0_LC_SAT_LUT_56_57 (SRSHARP0_OFFSET + LC_SAT_LUT_56_57 ) // 0xde
+#define SRSHARP0_LC_SAT_LUT_58_59 (SRSHARP0_OFFSET + LC_SAT_LUT_58_59 ) // 0xdf
+#define SRSHARP0_LC_SAT_LUT_60_61 (SRSHARP0_OFFSET + LC_SAT_LUT_60_61 ) // 0xe0
+#define SRSHARP0_LC_SAT_LUT_62 (SRSHARP0_OFFSET + LC_SAT_LUT_62 ) // 0xe1
+#define SRSHARP0_LC_CURVE_BLK_HIDX_0_1 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_0_1 ) // 0xe2
+#define SRSHARP0_LC_CURVE_BLK_HIDX_2_3 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_2_3 ) // 0xe3
+#define SRSHARP0_LC_CURVE_BLK_HIDX_4_5 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_4_5 ) // 0xe4
+#define SRSHARP0_LC_CURVE_BLK_HIDX_6_7 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_6_7 ) // 0xe5
+#define SRSHARP0_LC_CURVE_BLK_HIDX_8_9 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_8_9 ) // 0xe6
+#define SRSHARP0_LC_CURVE_BLK_HIDX_10_11 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_10_11 ) // 0xe7
+#define SRSHARP0_LC_CURVE_BLK_HIDX_12 (SRSHARP0_OFFSET + LC_CURVE_BLK_HIDX_12 ) // 0xe8
+#define SRSHARP0_LC_CURVE_BLK_VIDX_0_1 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_0_1 ) // 0xe9
+#define SRSHARP0_LC_CURVE_BLK_VIDX_2_3 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_2_3 ) // 0xea
+#define SRSHARP0_LC_CURVE_BLK_VIDX_4_5 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_4_5 ) // 0xeb
+#define SRSHARP0_LC_CURVE_BLK_VIDX_6_7 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_6_7 ) // 0xec
+#define SRSHARP0_LC_CURVE_BLK_VIDX_8 (SRSHARP0_OFFSET + LC_CURVE_BLK_VIDX_8 ) // 0xed
+#define SRSHARP0_LC_YUV2RGB_MAT_0_1 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_0_1 ) // 0xee
+#define SRSHARP0_LC_YUV2RGB_MAT_2_3 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_2_3 ) // 0xef
+#define SRSHARP0_LC_YUV2RGB_MAT_4_5 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_4_5 ) // 0xf0
+#define SRSHARP0_LC_YUV2RGB_MAT_6_7 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_6_7 ) // 0xf1
+#define SRSHARP0_LC_YUV2RGB_MAT_8 (SRSHARP0_OFFSET + LC_YUV2RGB_MAT_8 ) // 0xf2
+#define SRSHARP0_LC_RGB2YUV_MAT_0_1 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_0_1 ) // 0xf3
+#define SRSHARP0_LC_RGB2YUV_MAT_2_3 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_2_3 ) // 0xf4
+#define SRSHARP0_LC_RGB2YUV_MAT_4_5 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_4_5 ) // 0xf5
+#define SRSHARP0_LC_RGB2YUV_MAT_6_7 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_6_7 ) // 0xf6
+#define SRSHARP0_LC_RGB2YUV_MAT_8 (SRSHARP0_OFFSET + LC_RGB2YUV_MAT_8 ) // 0xf7
+#define SRSHARP0_LC_YUV2RGB_OFST (SRSHARP0_OFFSET + LC_YUV2RGB_OFST ) // 0xf8
+#define SRSHARP0_LC_YUV2RGB_CLIP (SRSHARP0_OFFSET + LC_YUV2RGB_CLIP ) // 0xf9
+#define SRSHARP0_LC_RGB2YUV_OFST (SRSHARP0_OFFSET + LC_RGB2YUV_OFST ) // 0xfa
+#define SRSHARP0_LC_RGB2YUV_CLIP (SRSHARP0_OFFSET + LC_RGB2YUV_CLIP ) // 0xfb
+#define SRSHARP0_LC_MAP_RAM_CTRL (SRSHARP0_OFFSET + LC_MAP_RAM_CTRL ) // 0xfc
+#define SRSHARP0_LC_MAP_RAM_ADDR (SRSHARP0_OFFSET + LC_MAP_RAM_ADDR ) // 0xfd
+#define SRSHARP0_LC_MAP_RAM_DATA (SRSHARP0_OFFSET + LC_MAP_RAM_DATA ) // 0xfe
+
+#define SRSHARP0_FMETER_CTRL (SRSHARP0_OFFSET + SHARP_FMETER_CTRL ) // 0x89
+#define SRSHARP0_FMETER_WIN_HOR (SRSHARP0_OFFSET + SHARP_FMETER_WIN_HOR ) // 0x8a
+#define SRSHARP0_FMETER_WIN_VER (SRSHARP0_OFFSET + SHARP_FMETER_WIN_VER ) // 0x8b
+#define SRSHARP0_FMETER_CORING (SRSHARP0_OFFSET + SHARP_FMETER_CORING ) // 0x8c
+#define SRSHARP0_FMETER_RATIO_H (SRSHARP0_OFFSET + SHARP_FMETER_RATIO_H ) // 0x8d
+#define SRSHARP0_FMETER_RATIO_V (SRSHARP0_OFFSET + SHARP_FMETER_RATIO_V ) // 0x8e
+#define SRSHARP0_FMETER_RATIO_D (SRSHARP0_OFFSET + SHARP_FMETER_RATIO_D ) // 0x8f
+#define SRSHARP0_RO_FMETER_HCNT_TYPE0 (SRSHARP0_OFFSET + SHARP_RO_FMETER_HCNT_TYPE0 ) // 0x46
+#define SRSHARP0_RO_FMETER_HCNT_TYPE1 (SRSHARP0_OFFSET + SHARP_RO_FMETER_HCNT_TYPE1 ) // 0x47
+#define SRSHARP0_RO_FMETER_HCNT_TYPE2 (SRSHARP0_OFFSET + SHARP_RO_FMETER_HCNT_TYPE2 ) // 0x48
+#define SRSHARP0_RO_FMETER_HCNT_TYPE3 (SRSHARP0_OFFSET + SHARP_RO_FMETER_HCNT_TYPE3 ) // 0x49
+#define SRSHARP0_RO_FMETER_VCNT_TYPE0 (SRSHARP0_OFFSET + SHARP_RO_FMETER_VCNT_TYPE0 ) // 0x4a
+#define SRSHARP0_RO_FMETER_VCNT_TYPE1 (SRSHARP0_OFFSET + SHARP_RO_FMETER_VCNT_TYPE1 ) // 0x4b
+#define SRSHARP0_RO_FMETER_VCNT_TYPE2 (SRSHARP0_OFFSET + SHARP_RO_FMETER_VCNT_TYPE2 ) // 0x4c
+#define SRSHARP0_RO_FMETER_VCNT_TYPE3 (SRSHARP0_OFFSET + SHARP_RO_FMETER_VCNT_TYPE3 ) // 0x4d
+#define SRSHARP0_RO_FMETER_PDCNT_TYPE0 (SRSHARP0_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE0 ) // 0x4e
+#define SRSHARP0_RO_FMETER_PDCNT_TYPE1 (SRSHARP0_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE1 ) // 0x4f
+#define SRSHARP0_RO_FMETER_PDCNT_TYPE2 (SRSHARP0_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE2 ) // 0x50
+#define SRSHARP0_RO_FMETER_PDCNT_TYPE3 (SRSHARP0_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE3 ) // 0x51
+#define SRSHARP0_RO_FMETER_NDCNT_TYPE0 (SRSHARP0_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE0 ) // 0x52
+#define SRSHARP0_RO_FMETER_NDCNT_TYPE1 (SRSHARP0_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE1 ) // 0x53
+#define SRSHARP0_RO_FMETER_NDCNT_TYPE2 (SRSHARP0_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE2 ) // 0x54
+#define SRSHARP0_RO_FMETER_NDCNT_TYPE3 (SRSHARP0_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE3 ) // 0x55
+
+
+
+
+
+//// srsharp1 reg define
+
+#define SRSHARP1_SHARP_HVSIZE (SRSHARP1_OFFSET + SHARP_HVSIZE ) //0x00 //
+#define SRSHARP1_SHARP_HVBLANK_NUM (SRSHARP1_OFFSET + SHARP_HVBLANK_NUM ) //0x01 //
+#define SRSHARP1_NR_GAUSSIAN_MODE (SRSHARP1_OFFSET + NR_GAUSSIAN_MODE ) //0x02 //
+#define SRSHARP1_PK_CON_2CIRHPGAIN_TH_RATE (SRSHARP1_OFFSET + PK_CON_2CIRHPGAIN_TH_RATE ) //0x05 //
+#define SRSHARP1_PK_CON_2CIRHPGAIN_LIMIT (SRSHARP1_OFFSET + PK_CON_2CIRHPGAIN_LIMIT ) //0x06 //
+#define SRSHARP1_PK_CON_2CIRBPGAIN_TH_RATE (SRSHARP1_OFFSET + PK_CON_2CIRBPGAIN_TH_RATE ) //0x07 //
+#define SRSHARP1_PK_CON_2CIRBPGAIN_LIMIT (SRSHARP1_OFFSET + PK_CON_2CIRBPGAIN_LIMIT ) //0x08 //
+#define SRSHARP1_PK_CON_2DRTHPGAIN_TH_RATE (SRSHARP1_OFFSET + PK_CON_2DRTHPGAIN_TH_RATE ) //0x09 //
+#define SRSHARP1_PK_CON_2DRTHPGAIN_LIMIT (SRSHARP1_OFFSET + PK_CON_2DRTHPGAIN_LIMIT ) //0x0a //
+#define SRSHARP1_PK_CON_2DRTBPGAIN_TH_RATE (SRSHARP1_OFFSET + PK_CON_2DRTBPGAIN_TH_RATE ) //0x0b //
+#define SRSHARP1_PK_CON_2DRTBPGAIN_LIMIT (SRSHARP1_OFFSET + PK_CON_2DRTBPGAIN_LIMIT ) //0x0c //
+#define SRSHARP1_PK_CIRFB_LPF_MODE (SRSHARP1_OFFSET + PK_CIRFB_LPF_MODE ) //0x0d //
+#define SRSHARP1_PK_DRTFB_LPF_MODE (SRSHARP1_OFFSET + PK_DRTFB_LPF_MODE ) //0x0e //
+#define SRSHARP1_PK_CIRFB_HP_CORING (SRSHARP1_OFFSET + PK_CIRFB_HP_CORING ) //0x0f //
+#define SRSHARP1_PK_CIRFB_BP_CORING (SRSHARP1_OFFSET + PK_CIRFB_BP_CORING ) //0x10 //
+#define SRSHARP1_PK_DRTFB_HP_CORING (SRSHARP1_OFFSET + PK_DRTFB_HP_CORING ) //0x11 //
+#define SRSHARP1_PK_DRTFB_BP_CORING (SRSHARP1_OFFSET + PK_DRTFB_BP_CORING ) //0x12 //
+#define SRSHARP1_PK_CIRFB_BLEND_GAIN (SRSHARP1_OFFSET + PK_CIRFB_BLEND_GAIN ) //0x13 //
+#define SRSHARP1_NR_ALPY_SSD_GAIN_OFST (SRSHARP1_OFFSET + NR_ALPY_SSD_GAIN_OFST ) //0x14 //
+#define SRSHARP1_NR_ALP0Y_ERR2CURV_TH_RATE (SRSHARP1_OFFSET + NR_ALP0Y_ERR2CURV_TH_RATE ) //0x15 //
+#define SRSHARP1_NR_ALP0Y_ERR2CURV_LIMIT (SRSHARP1_OFFSET + NR_ALP0Y_ERR2CURV_LIMIT ) //0x16 //
+#define SRSHARP1_NR_ALP0C_ERR2CURV_TH_RATE (SRSHARP1_OFFSET + NR_ALP0C_ERR2CURV_TH_RATE ) //0x17 //
+#define SRSHARP1_NR_ALP0C_ERR2CURV_LIMIT (SRSHARP1_OFFSET + NR_ALP0C_ERR2CURV_LIMIT ) //0x18 //
+#define SRSHARP1_NR_ALP0_MIN_MAX (SRSHARP1_OFFSET + NR_ALP0_MIN_MAX ) //0x19 //
+#define SRSHARP1_NR_ALP1_MIERR_CORING (SRSHARP1_OFFSET + NR_ALP1_MIERR_CORING ) //0x1a //
+#define SRSHARP1_NR_ALP1_ERR2CURV_TH_RATE (SRSHARP1_OFFSET + NR_ALP1_ERR2CURV_TH_RATE ) //0x1b //
+#define SRSHARP1_NR_ALP1_ERR2CURV_LIMIT (SRSHARP1_OFFSET + NR_ALP1_ERR2CURV_LIMIT ) //0x1c //
+#define SRSHARP1_NR_ALP1_MIN_MAX (SRSHARP1_OFFSET + NR_ALP1_MIN_MAX ) //0x1d //
+#define SRSHARP1_PK_ALP2_MIERR_CORING (SRSHARP1_OFFSET + PK_ALP2_MIERR_CORING ) //0x1e //
+#define SRSHARP1_PK_ALP2_ERR2CURV_TH_RATE (SRSHARP1_OFFSET + PK_ALP2_ERR2CURV_TH_RATE ) //0x1f //
+#define SRSHARP1_PK_ALP2_ERR2CURV_LIMIT (SRSHARP1_OFFSET + PK_ALP2_ERR2CURV_LIMIT ) //0x20 //
+#define SRSHARP1_PK_ALP2_MIN_MAX (SRSHARP1_OFFSET + PK_ALP2_MIN_MAX ) //0x21 //
+#define SRSHARP1_PK_FINALGAIN_HP_BP (SRSHARP1_OFFSET + PK_FINALGAIN_HP_BP ) //0x22 //
+#define SRSHARP1_PK_OS_HORZ_CORE_GAIN (SRSHARP1_OFFSET + PK_OS_HORZ_CORE_GAIN ) //0x23 //
+#define SRSHARP1_PK_OS_VERT_CORE_GAIN (SRSHARP1_OFFSET + PK_OS_VERT_CORE_GAIN ) //0x24 //
+#define SRSHARP1_PK_OS_ADPT_MISC (SRSHARP1_OFFSET + PK_OS_ADPT_MISC ) //0x25 //
+#define SRSHARP1_PK_OS_STATIC (SRSHARP1_OFFSET + PK_OS_STATIC ) //0x26 //
+#define SRSHARP1_PK_NR_ENABLE (SRSHARP1_OFFSET + PK_NR_ENABLE ) //0x27 //
+#define SRSHARP1_PK_DRT_SAD_MISC (SRSHARP1_OFFSET + PK_DRT_SAD_MISC ) //0x28 //
+#define SRSHARP1_NR_TI_DNLP_BLEND (SRSHARP1_OFFSET + NR_TI_DNLP_BLEND ) //0x29 //
+#define SRSHARP1_LTI_DIR_CORE_ALPHA (SRSHARP1_OFFSET + LTI_DIR_CORE_ALPHA ) //0x2a //
+#define SRSHARP1_CTI_DIR_ALPHA (SRSHARP1_OFFSET + CTI_DIR_ALPHA ) //0x2b //
+#define SRSHARP1_LTI_CTI_DF_GAIN (SRSHARP1_OFFSET + LTI_CTI_DF_GAIN ) //0x2c //
+#define SRSHARP1_LTI_CTI_DIR_AC_DBG (SRSHARP1_OFFSET + LTI_CTI_DIR_AC_DBG ) //0x2d //
+#define SRSHARP1_HCTI_FLT_CLP_DC (SRSHARP1_OFFSET + HCTI_FLT_CLP_DC ) //0x2e //
+#define SRSHARP1_HCTI_BST_GAIN (SRSHARP1_OFFSET + HCTI_BST_GAIN ) //0x2f //
+#define SRSHARP1_HCTI_BST_CORE (SRSHARP1_OFFSET + HCTI_BST_CORE ) //0x30 //
+#define SRSHARP1_HCTI_CON_2_GAIN_0 (SRSHARP1_OFFSET + HCTI_CON_2_GAIN_0 ) //0x31 //
+#define SRSHARP1_HCTI_CON_2_GAIN_1 (SRSHARP1_OFFSET + HCTI_CON_2_GAIN_1 ) //0x32 //
+#define SRSHARP1_HCTI_OS_MARGIN (SRSHARP1_OFFSET + HCTI_OS_MARGIN ) //0x33 //
+#define SRSHARP1_HLTI_FLT_CLP_DC (SRSHARP1_OFFSET + HLTI_FLT_CLP_DC ) //0x34 //
+#define SRSHARP1_HLTI_BST_GAIN (SRSHARP1_OFFSET + HLTI_BST_GAIN ) //0x35 //
+#define SRSHARP1_HLTI_BST_CORE (SRSHARP1_OFFSET + HLTI_BST_CORE ) //0x36 //
+#define SRSHARP1_HLTI_CON_2_GAIN_0 (SRSHARP1_OFFSET + HLTI_CON_2_GAIN_0 ) //0x37 //
+#define SRSHARP1_HLTI_CON_2_GAIN_1 (SRSHARP1_OFFSET + HLTI_CON_2_GAIN_1 ) //0x38 //
+#define SRSHARP1_HLTI_OS_MARGIN (SRSHARP1_OFFSET + HLTI_OS_MARGIN ) //0x39 //
+#define SRSHARP1_VLTI_FLT_CON_CLP (SRSHARP1_OFFSET + VLTI_FLT_CON_CLP ) //0x3a //
+#define SRSHARP1_VLTI_BST_GAIN (SRSHARP1_OFFSET + VLTI_BST_GAIN ) //0x3b //
+#define SRSHARP1_VLTI_BST_CORE (SRSHARP1_OFFSET + VLTI_BST_CORE ) //0x3c //
+#define SRSHARP1_VLTI_CON_2_GAIN_0 (SRSHARP1_OFFSET + VLTI_CON_2_GAIN_0 ) //0x3d //
+#define SRSHARP1_VLTI_CON_2_GAIN_1 (SRSHARP1_OFFSET + VLTI_CON_2_GAIN_1 ) //0x3e //
+#define SRSHARP1_VCTI_FLT_CON_CLP (SRSHARP1_OFFSET + VCTI_FLT_CON_CLP ) //0x3f //
+#define SRSHARP1_VCTI_BST_GAIN (SRSHARP1_OFFSET + VCTI_BST_GAIN ) //0x40 //
+#define SRSHARP1_VCTI_BST_CORE (SRSHARP1_OFFSET + VCTI_BST_CORE ) //0x41 //
+#define SRSHARP1_VCTI_CON_2_GAIN_0 (SRSHARP1_OFFSET + VCTI_CON_2_GAIN_0 ) //0x42 //
+#define SRSHARP1_VCTI_CON_2_GAIN_1 (SRSHARP1_OFFSET + VCTI_CON_2_GAIN_1 ) //0x43 //
+#define SRSHARP1_SHARP_3DLIMIT (SRSHARP1_OFFSET + SHARP_3DLIMIT ) //0x44 //
+#define SRSHARP1_DNLP_EN (SRSHARP1_OFFSET + DNLP_EN ) //0x45 //
+//`define SRSHARP1_DNLP_00 (`SRSHARP1_OFFSET + `DNLP_00 ) //8'h46 //
+//`define SRSHARP1_DNLP_01 (`SRSHARP1_OFFSET + `DNLP_01 ) //8'h47 //
+//`define SRSHARP1_DNLP_02 (`SRSHARP1_OFFSET + `DNLP_02 ) //8'h48 //
+//`define SRSHARP1_DNLP_03 (`SRSHARP1_OFFSET + `DNLP_03 ) //8'h49 //
+//`define SRSHARP1_DNLP_04 (`SRSHARP1_OFFSET + `DNLP_04 ) //8'h4a //
+//`define SRSHARP1_DNLP_05 (`SRSHARP1_OFFSET + `DNLP_05 ) //8'h4b //
+//`define SRSHARP1_DNLP_06 (`SRSHARP1_OFFSET + `DNLP_06 ) //8'h4c //
+//`define SRSHARP1_DNLP_07 (`SRSHARP1_OFFSET + `DNLP_07 ) //8'h4d //
+//`define SRSHARP1_DNLP_08 (`SRSHARP1_OFFSET + `DNLP_08 ) //8'h4e //
+//`define SRSHARP1_DNLP_09 (`SRSHARP1_OFFSET + `DNLP_09 ) //8'h4f //
+//`define SRSHARP1_DNLP_10 (`SRSHARP1_OFFSET + `DNLP_10 ) //8'h50 //
+//`define SRSHARP1_DNLP_11 (`SRSHARP1_OFFSET + `DNLP_11 ) //8'h51 //
+//`define SRSHARP1_DNLP_12 (`SRSHARP1_OFFSET + `DNLP_12 ) //8'h52 //
+//`define SRSHARP1_DNLP_13 (`SRSHARP1_OFFSET + `DNLP_13 ) //8'h53 //
+//`define SRSHARP1_DNLP_14 (`SRSHARP1_OFFSET + `DNLP_14 ) //8'h54 //
+//`define SRSHARP1_DNLP_15 (`SRSHARP1_OFFSET + `DNLP_15 ) //8'h55 //
+#define SRSHARP1_DEMO_CRTL (SRSHARP1_OFFSET + DEMO_CRTL ) //0x56 //
+#define SRSHARP1_SHARP_SR2_CTRL (SRSHARP1_OFFSET + SHARP_SR2_CTRL ) //0x57 //
+#define SRSHARP1_SHARP_SR2_YBIC_HCOEF0 (SRSHARP1_OFFSET + SHARP_SR2_YBIC_HCOEF0 ) //0x58
+#define SRSHARP1_SHARP_SR2_YBIC_HCOEF1 (SRSHARP1_OFFSET + SHARP_SR2_YBIC_HCOEF1 ) //0x59 //
+#define SRSHARP1_SHARP_SR2_CBIC_HCOEF0 (SRSHARP1_OFFSET + SHARP_SR2_CBIC_HCOEF0 ) //0x5a //
+#define SRSHARP1_SHARP_SR2_CBIC_HCOEF1 (SRSHARP1_OFFSET + SHARP_SR2_CBIC_HCOEF1 ) //0x5b //
+#define SRSHARP1_SHARP_SR2_YBIC_VCOEF0 (SRSHARP1_OFFSET + SHARP_SR2_YBIC_VCOEF0 ) //0x5c //
+#define SRSHARP1_SHARP_SR2_YBIC_VCOEF1 (SRSHARP1_OFFSET + SHARP_SR2_YBIC_VCOEF1 ) //0x5d //
+#define SRSHARP1_SHARP_SR2_CBIC_VCOEF0 (SRSHARP1_OFFSET + SHARP_SR2_CBIC_VCOEF0 ) //0x5e //
+#define SRSHARP1_SHARP_SR2_CBIC_VCOEF1 (SRSHARP1_OFFSET + SHARP_SR2_CBIC_VCOEF1 ) //0x5f //
+#define SRSHARP1_SHARP_SR2_MISC (SRSHARP1_OFFSET + SHARP_SR2_MISC ) //0x60 //
+#define SRSHARP1_SR3_SAD_CTRL (SRSHARP1_OFFSET + SHARP_SR3_SAD_CTRL ) // 0x61 //
+#define SRSHARP1_SR3_PK_CTRL0 (SRSHARP1_OFFSET + SHARP_SR3_PK_CTRL0 ) // 0x62
+#define SRSHARP1_SR3_PK_CTRL1 (SRSHARP1_OFFSET + SHARP_SR3_PK_CTRL1 ) // 0x63
+#define SRSHARP1_DEJ_CTRL (SRSHARP1_OFFSET + SHARP_DEJ_CTRL ) // 0x64
+#define SRSHARP1_DEJ_ALPHA (SRSHARP1_OFFSET + SHARP_DEJ_ALPHA ) // 0x65
+#define SRSHARP1_SR3_DRTLPF_EN (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_EN ) // 0x66
+#define SRSHARP1_SR3_DRTLPF_ALPHA_0 (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_ALPHA_0 ) // 0x67
+#define SRSHARP1_SR3_DRTLPF_ALPHA_1 (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_ALPHA_1 ) // 0x68
+#define SRSHARP1_SR3_DRTLPF_ALPHA_2 (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_ALPHA_2 ) // 0x69
+#define SRSHARP1_SR3_DRTLPF_ALPHA_OFST (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_ALPHA_OFST ) // 0x6a
+#define SRSHARP1_SR3_DERING_CTRL (SRSHARP1_OFFSET + SHARP_SR3_DERING_CTRL ) // 0x6b
+#define SRSHARP1_SR3_DERING_LUMA2PKGAIN_0TO3 (SRSHARP1_OFFSET + SHARP_SR3_DERING_LUMA2PKGAIN_0TO3 ) // 0x6c
+#define SRSHARP1_SR3_DERING_LUMA2PKGAIN_4TO6 (SRSHARP1_OFFSET + SHARP_SR3_DERING_LUMA2PKGAIN_4TO6 ) // 0x6d
+#define SRSHARP1_SR3_DERING_LUMA2PKOS_0TO3 (SRSHARP1_OFFSET + SHARP_SR3_DERING_LUMA2PKOS_0TO3 ) // 0x6e
+#define SRSHARP1_SR3_DERING_LUMA2PKOS_4TO6 (SRSHARP1_OFFSET + SHARP_SR3_DERING_LUMA2PKOS_4TO6 ) // 0x6f
+#define SRSHARP1_SR3_DERING_GAINVS_MADSAD (SRSHARP1_OFFSET + SHARP_SR3_DERING_GAINVS_MADSAD ) // 0x70
+#define SRSHARP1_SR3_DERING_GAINVS_VR2MAX (SRSHARP1_OFFSET + SHARP_SR3_DERING_GAINVS_VR2MAX ) // 0x71
+#define SRSHARP1_SR3_DERING_PARAM0 (SRSHARP1_OFFSET + SHARP_SR3_DERING_PARAM0 ) // 0x72
+#define SRSHARP1_SR3_DRTLPF_THETA (SRSHARP1_OFFSET + SHARP_SR3_DRTLPF_THETA ) // 0x73
+#define SRSHARP1_SATPRT_CTRL (SRSHARP1_OFFSET + SHARP_SATPRT_CTRL ) // 0x74
+#define SRSHARP1_SATPRT_DIVM (SRSHARP1_OFFSET + SHARP_SATPRT_DIVM ) // 0x75
+#define SRSHARP1_DB_FLT_CTRL (SRSHARP1_OFFSET + SHARP_DB_FLT_CTRL ) // 0x77
+//`define SRSHARP1_DB_FLT_YC_THRD (`SRSHARP1_OFFSET + `SHARP_DB_FLT_YC_THRD ) // 8'h78
+#define SRSHARP1_DB_FLT_CTRL1 (SRSHARP1_OFFSET + SHARP_DB_FLT_CTRL1 ) // 0xb8
+#define SRSHARP1_DB_FLT_LUMA_THRD (SRSHARP1_OFFSET + SHARP_DB_FLT_LUMA_THRD ) // 0xb9
+#define SRSHARP1_DB_FLT_CHRM_THRD (SRSHARP1_OFFSET + SHARP_DB_FLT_CHRM_THRD ) // 0xba
+#define SRSHARP1_DB_FLT_RANDLUT (SRSHARP1_OFFSET + SHARP_DB_FLT_RANDLUT ) // 0x79
+#define SRSHARP1_DB_FLT_PXI_THRD (SRSHARP1_OFFSET + SHARP_DB_FLT_PXI_THRD ) // 0x7a
+#define SRSHARP1_DB_FLT_SEED_Y (SRSHARP1_OFFSET + SHARP_DB_FLT_SEED_Y ) // 0x7b
+#define SRSHARP1_DB_FLT_SEED_U (SRSHARP1_OFFSET + SHARP_DB_FLT_SEED_U ) // 0x7c
+#define SRSHARP1_DB_FLT_SEED_V (SRSHARP1_OFFSET + SHARP_DB_FLT_SEED_V ) // 0x7d
+#define SRSHARP1_PKGAIN_VSLUMA_LUT_L (SRSHARP1_OFFSET + SHARP_PKGAIN_VSLUMA_LUT_L ) // 0x7e
+#define SRSHARP1_PKGAIN_VSLUMA_LUT_H (SRSHARP1_OFFSET + SHARP_PKGAIN_VSLUMA_LUT_H ) // 0x7f
+#define SRSHARP1_PKOSHT_VSLUMA_LUT_L (SRSHARP1_OFFSET + SHARP_PKOSHT_VSLUMA_LUT_L ) // 0x80
+#define SRSHARP1_PKOSHT_VSLUMA_LUT_H (SRSHARP1_OFFSET + SHARP_PKOSHT_VSLUMA_LUT_H ) // 0x81
+#define SRSHARP1_SATPRT_LMT_RGB1 (SRSHARP1_OFFSET + SHARP_SATPRT_LMT_RGB1 ) // 0x82
+#define SRSHARP1_SATPRT_LMT_RGB2 (SRSHARP1_OFFSET + SHARP_SATPRT_LMT_RGB2 ) // 0x83
+#define SRSHARP1_SHARP_GATE_CLK_CTRL_0 (SRSHARP1_OFFSET + SHARP_GATE_CLK_CTRL_0 ) // 0x84
+#define SRSHARP1_SHARP_GATE_CLK_CTRL_1 (SRSHARP1_OFFSET + SHARP_GATE_CLK_CTRL_1 ) // 0x85
+#define SRSHARP1_SHARP_GATE_CLK_CTRL_2 (SRSHARP1_OFFSET + SHARP_GATE_CLK_CTRL_2 ) // 0x86
+#define SRSHARP1_SHARP_GATE_CLK_CTRL_3 (SRSHARP1_OFFSET + SHARP_GATE_CLK_CTRL_3 ) // 0x87
+#define SRSHARP1_SHARP_DPS_CTRL (SRSHARP1_OFFSET + SHARP_DPS_CTRL ) // 0x88
+#define SRSHARP1_DNLP_00 (SRSHARP1_OFFSET + DNLP_00 ) // 0x90 //
+#define SRSHARP1_DNLP_01 (SRSHARP1_OFFSET + DNLP_01 ) // 0x91 //
+#define SRSHARP1_DNLP_02 (SRSHARP1_OFFSET + DNLP_02 ) // 0x92 //
+#define SRSHARP1_DNLP_03 (SRSHARP1_OFFSET + DNLP_03 ) // 0x93 //
+#define SRSHARP1_DNLP_04 (SRSHARP1_OFFSET + DNLP_04 ) // 0x94 //
+#define SRSHARP1_DNLP_05 (SRSHARP1_OFFSET + DNLP_05 ) // 0x95 //
+#define SRSHARP1_DNLP_06 (SRSHARP1_OFFSET + DNLP_06 ) // 0x96 //
+#define SRSHARP1_DNLP_07 (SRSHARP1_OFFSET + DNLP_07 ) // 0x97 //
+#define SRSHARP1_DNLP_08 (SRSHARP1_OFFSET + DNLP_08 ) // 0x98 //
+#define SRSHARP1_DNLP_09 (SRSHARP1_OFFSET + DNLP_09 ) // 0x99 //
+#define SRSHARP1_DNLP_10 (SRSHARP1_OFFSET + DNLP_10 ) // 0x9a //
+#define SRSHARP1_DNLP_11 (SRSHARP1_OFFSET + DNLP_11 ) // 0x9b //
+#define SRSHARP1_DNLP_12 (SRSHARP1_OFFSET + DNLP_12 ) // 0x9c //
+#define SRSHARP1_DNLP_13 (SRSHARP1_OFFSET + DNLP_13 ) // 0x9d //
+#define SRSHARP1_DNLP_14 (SRSHARP1_OFFSET + DNLP_14 ) // 0x9e //
+#define SRSHARP1_DNLP_15 (SRSHARP1_OFFSET + DNLP_15 ) // 0x9f //
+#define SRSHARP1_DNLP_16 (SRSHARP1_OFFSET + DNLP_16 ) // 0xa0 //
+#define SRSHARP1_DNLP_17 (SRSHARP1_OFFSET + DNLP_17 ) // 0xa1 //
+#define SRSHARP1_DNLP_18 (SRSHARP1_OFFSET + DNLP_18 ) // 0xa2 //
+#define SRSHARP1_DNLP_19 (SRSHARP1_OFFSET + DNLP_19 ) // 0xa3 //
+#define SRSHARP1_DNLP_20 (SRSHARP1_OFFSET + DNLP_20 ) // 0xa4 //
+#define SRSHARP1_DNLP_21 (SRSHARP1_OFFSET + DNLP_21 ) // 0xa5 //
+#define SRSHARP1_DNLP_22 (SRSHARP1_OFFSET + DNLP_22 ) // 0xa6 //
+#define SRSHARP1_DNLP_23 (SRSHARP1_OFFSET + DNLP_23 ) // 0xa7 //
+#define SRSHARP1_DNLP_24 (SRSHARP1_OFFSET + DNLP_24 ) // 0xa8 //
+#define SRSHARP1_DNLP_25 (SRSHARP1_OFFSET + DNLP_25 ) // 0xa9 //
+#define SRSHARP1_DNLP_26 (SRSHARP1_OFFSET + DNLP_26 ) // 0xaa //
+#define SRSHARP1_DNLP_27 (SRSHARP1_OFFSET + DNLP_27 ) // 0xab //
+#define SRSHARP1_DNLP_28 (SRSHARP1_OFFSET + DNLP_28 ) // 0xac //
+#define SRSHARP1_DNLP_29 (SRSHARP1_OFFSET + DNLP_29 ) // 0xad //
+#define SRSHARP1_DNLP_30 (SRSHARP1_OFFSET + DNLP_30 ) // 0xae //
+#define SRSHARP1_DNLP_31 (SRSHARP1_OFFSET + DNLP_31 ) // 0xaf //
+#define SRSHARP1_SHARP_SYNC_CTRL (SRSHARP1_OFFSET + SHARP_SYNC_CTRL ) // 0xb0 //
+#define SRSHARP1_LC_INPUT_MUX (SRSHARP1_OFFSET + LC_INPUT_MUX ) // 0xb1 //
+#define SRSHARP1_NR_GAU_YH_COEF02 (SRSHARP1_OFFSET + NR_GAU_YH_COEF02 ) // 0xb2 //
+#define SRSHARP1_NR_GAU_YH_COEF34 (SRSHARP1_OFFSET + NR_GAU_YH_COEF34 ) // 0xb3 //
+#define SRSHARP1_NR_GAU_YV_COEF1 (SRSHARP1_OFFSET + NR_GAU_YV_COEF1 ) // 0xb4 //
+#define SRSHARP1_NR_GAU_CH_COEF02 (SRSHARP1_OFFSET + NR_GAU_CH_COEF02 ) // 0xb5 //
+#define SRSHARP1_NR_GAU_CH_COEF34 (SRSHARP1_OFFSET + NR_GAU_CH_COEF34 ) // 0xb6 //
+#define SRSHARP1_NR_GAU_CV_COEF1 (SRSHARP1_OFFSET + NR_GAU_CV_COEF1 ) // 0xb7 //
+#define SRSHARP1_LC_TOP_CTRL (SRSHARP1_OFFSET + LC_TOP_CTRL ) // 0xc0 //
+#define SRSHARP1_LC_HV_NUM (SRSHARP1_OFFSET + LC_HV_NUM ) // 0xc1
+#define SRSHARP1_LC_SAT_LUT_0_1 (SRSHARP1_OFFSET + LC_SAT_LUT_0_1 ) // 0xc2
+#define SRSHARP1_LC_SAT_LUT_2_3 (SRSHARP1_OFFSET + LC_SAT_LUT_2_3 ) // 0xc3
+#define SRSHARP1_LC_SAT_LUT_4_5 (SRSHARP1_OFFSET + LC_SAT_LUT_4_5 ) // 0xc4
+#define SRSHARP1_LC_SAT_LUT_6_7 (SRSHARP1_OFFSET + LC_SAT_LUT_6_7 ) // 0xc5
+#define SRSHARP1_LC_SAT_LUT_8_9 (SRSHARP1_OFFSET + LC_SAT_LUT_8_9 ) // 0xc6
+#define SRSHARP1_LC_SAT_LUT_10_11 (SRSHARP1_OFFSET + LC_SAT_LUT_10_11 ) // 0xc7
+#define SRSHARP1_LC_SAT_LUT_12_13 (SRSHARP1_OFFSET + LC_SAT_LUT_12_13 ) // 0xc8
+#define SRSHARP1_LC_SAT_LUT_14_15 (SRSHARP1_OFFSET + LC_SAT_LUT_14_15 ) // 0xc9
+#define SRSHARP1_LC_SAT_LUT_16_17 (SRSHARP1_OFFSET + LC_SAT_LUT_16_17 ) // 0xca
+#define SRSHARP1_LC_SAT_LUT_18_19 (SRSHARP1_OFFSET + LC_SAT_LUT_18_19 ) // 0xcb
+#define SRSHARP1_LC_SAT_LUT_20_21 (SRSHARP1_OFFSET + LC_SAT_LUT_20_21 ) // 0xcc
+#define SRSHARP1_LC_SAT_LUT_22_23 (SRSHARP1_OFFSET + LC_SAT_LUT_22_23 ) // 0xcd
+#define SRSHARP1_LC_SAT_LUT_24_25 (SRSHARP1_OFFSET + LC_SAT_LUT_24_25 ) // 0xce
+#define SRSHARP1_LC_SAT_LUT_26_27 (SRSHARP1_OFFSET + LC_SAT_LUT_26_27 ) // 0xcf
+#define SRSHARP1_LC_SAT_LUT_28_29 (SRSHARP1_OFFSET + LC_SAT_LUT_28_29 ) // 0xd0
+#define SRSHARP1_LC_SAT_LUT_30_31 (SRSHARP1_OFFSET + LC_SAT_LUT_30_31 ) // 0xd1
+#define SRSHARP1_LC_SAT_LUT_32_33 (SRSHARP1_OFFSET + LC_SAT_LUT_32_33 ) // 0xd2
+#define SRSHARP1_LC_SAT_LUT_34_35 (SRSHARP1_OFFSET + LC_SAT_LUT_34_35 ) // 0xd3
+#define SRSHARP1_LC_SAT_LUT_36_37 (SRSHARP1_OFFSET + LC_SAT_LUT_36_37 ) // 0xd4
+#define SRSHARP1_LC_SAT_LUT_38_39 (SRSHARP1_OFFSET + LC_SAT_LUT_38_39 ) // 0xd5
+#define SRSHARP1_LC_SAT_LUT_40_41 (SRSHARP1_OFFSET + LC_SAT_LUT_40_41 ) // 0xd6
+#define SRSHARP1_LC_SAT_LUT_42_43 (SRSHARP1_OFFSET + LC_SAT_LUT_42_43 ) // 0xd7
+#define SRSHARP1_LC_SAT_LUT_44_45 (SRSHARP1_OFFSET + LC_SAT_LUT_44_45 ) // 0xd8
+#define SRSHARP1_LC_SAT_LUT_46_47 (SRSHARP1_OFFSET + LC_SAT_LUT_46_47 ) // 0xd9
+#define SRSHARP1_LC_SAT_LUT_48_49 (SRSHARP1_OFFSET + LC_SAT_LUT_48_49 ) // 0xda
+#define SRSHARP1_LC_SAT_LUT_50_51 (SRSHARP1_OFFSET + LC_SAT_LUT_50_51 ) // 0xdb
+#define SRSHARP1_LC_SAT_LUT_52_53 (SRSHARP1_OFFSET + LC_SAT_LUT_52_53 ) // 0xdc
+#define SRSHARP1_LC_SAT_LUT_54_55 (SRSHARP1_OFFSET + LC_SAT_LUT_54_55 ) // 0xdd
+#define SRSHARP1_LC_SAT_LUT_56_57 (SRSHARP1_OFFSET + LC_SAT_LUT_56_57 ) // 0xde
+#define SRSHARP1_LC_SAT_LUT_58_59 (SRSHARP1_OFFSET + LC_SAT_LUT_58_59 ) // 0xdf
+#define SRSHARP1_LC_SAT_LUT_60_61 (SRSHARP1_OFFSET + LC_SAT_LUT_60_61 ) // 0xe0
+#define SRSHARP1_LC_SAT_LUT_62 (SRSHARP1_OFFSET + LC_SAT_LUT_62 ) // 0xe1
+#define SRSHARP1_LC_CURVE_BLK_HIDX_0_1 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_0_1 ) // 0xe2
+#define SRSHARP1_LC_CURVE_BLK_HIDX_2_3 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_2_3 ) // 0xe3
+#define SRSHARP1_LC_CURVE_BLK_HIDX_4_5 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_4_5 ) // 0xe4
+#define SRSHARP1_LC_CURVE_BLK_HIDX_6_7 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_6_7 ) // 0xe5
+#define SRSHARP1_LC_CURVE_BLK_HIDX_8_9 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_8_9 ) // 0xe6
+#define SRSHARP1_LC_CURVE_BLK_HIDX_10_11 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_10_11 ) // 0xe7
+#define SRSHARP1_LC_CURVE_BLK_HIDX_12 (SRSHARP1_OFFSET + LC_CURVE_BLK_HIDX_12 ) // 0xe8
+#define SRSHARP1_LC_CURVE_BLK_VIDX_0_1 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_0_1 ) // 0xe9
+#define SRSHARP1_LC_CURVE_BLK_VIDX_2_3 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_2_3 ) // 0xea
+#define SRSHARP1_LC_CURVE_BLK_VIDX_4_5 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_4_5 ) // 0xeb
+#define SRSHARP1_LC_CURVE_BLK_VIDX_6_7 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_6_7 ) // 0xec
+#define SRSHARP1_LC_CURVE_BLK_VIDX_8 (SRSHARP1_OFFSET + LC_CURVE_BLK_VIDX_8 ) // 0xed
+#define SRSHARP1_LC_YUV2RGB_MAT_0_1 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_0_1 ) // 0xee
+#define SRSHARP1_LC_YUV2RGB_MAT_2_3 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_2_3 ) // 0xef
+#define SRSHARP1_LC_YUV2RGB_MAT_4_5 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_4_5 ) // 0xf0
+#define SRSHARP1_LC_YUV2RGB_MAT_6_7 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_6_7 ) // 0xf1
+#define SRSHARP1_LC_YUV2RGB_MAT_8 (SRSHARP1_OFFSET + LC_YUV2RGB_MAT_8 ) // 0xf2
+#define SRSHARP1_LC_RGB2YUV_MAT_0_1 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_0_1 ) // 0xf3
+#define SRSHARP1_LC_RGB2YUV_MAT_2_3 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_2_3 ) // 0xf4
+#define SRSHARP1_LC_RGB2YUV_MAT_4_5 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_4_5 ) // 0xf5
+#define SRSHARP1_LC_RGB2YUV_MAT_6_7 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_6_7 ) // 0xf6
+#define SRSHARP1_LC_RGB2YUV_MAT_8 (SRSHARP1_OFFSET + LC_RGB2YUV_MAT_8 ) // 0xf7
+#define SRSHARP1_LC_YUV2RGB_OFST (SRSHARP1_OFFSET + LC_YUV2RGB_OFST ) // 0xf8
+#define SRSHARP1_LC_YUV2RGB_CLIP (SRSHARP1_OFFSET + LC_YUV2RGB_CLIP ) // 0xf9
+#define SRSHARP1_LC_RGB2YUV_OFST (SRSHARP1_OFFSET + LC_RGB2YUV_OFST ) // 0xfa
+#define SRSHARP1_LC_RGB2YUV_CLIP (SRSHARP1_OFFSET + LC_RGB2YUV_CLIP ) // 0xfb
+#define SRSHARP1_LC_MAP_RAM_CTRL (SRSHARP1_OFFSET + LC_MAP_RAM_CTRL ) // 0xfc
+#define SRSHARP1_LC_MAP_RAM_ADDR (SRSHARP1_OFFSET + LC_MAP_RAM_ADDR ) // 0xfd
+#define SRSHARP1_LC_MAP_RAM_DATA (SRSHARP1_OFFSET + LC_MAP_RAM_DATA ) // 0xfe
+
+#define SRSHARP1_FMETER_CTRL (SRSHARP1_OFFSET + SHARP_FMETER_CTRL ) // 0x89
+#define SRSHARP1_FMETER_WIN_HOR (SRSHARP1_OFFSET + SHARP_FMETER_WIN_HOR ) // 0x8a
+#define SRSHARP1_FMETER_WIN_VER (SRSHARP1_OFFSET + SHARP_FMETER_WIN_VER ) // 0x8b
+#define SRSHARP1_FMETER_CORING (SRSHARP1_OFFSET + SHARP_FMETER_CORING ) // 0x8c
+#define SRSHARP1_FMETER_RATIO_H (SRSHARP1_OFFSET + SHARP_FMETER_RATIO_H ) // 0x8d
+#define SRSHARP1_FMETER_RATIO_V (SRSHARP1_OFFSET + SHARP_FMETER_RATIO_V ) // 0x8e
+#define SRSHARP1_FMETER_RATIO_D (SRSHARP1_OFFSET + SHARP_FMETER_RATIO_D ) // 0x8f
+#define SRSHARP1_RO_FMETER_HCNT_TYPE0 (SRSHARP1_OFFSET + SHARP_RO_FMETER_HCNT_TYPE0 ) // 0x46
+#define SRSHARP1_RO_FMETER_HCNT_TYPE1 (SRSHARP1_OFFSET + SHARP_RO_FMETER_HCNT_TYPE1 ) // 0x47
+#define SRSHARP1_RO_FMETER_HCNT_TYPE2 (SRSHARP1_OFFSET + SHARP_RO_FMETER_HCNT_TYPE2 ) // 0x48
+#define SRSHARP1_RO_FMETER_HCNT_TYPE3 (SRSHARP1_OFFSET + SHARP_RO_FMETER_HCNT_TYPE3 ) // 0x49
+#define SRSHARP1_RO_FMETER_VCNT_TYPE0 (SRSHARP1_OFFSET + SHARP_RO_FMETER_VCNT_TYPE0 ) // 0x4a
+#define SRSHARP1_RO_FMETER_VCNT_TYPE1 (SRSHARP1_OFFSET + SHARP_RO_FMETER_VCNT_TYPE1 ) // 0x4b
+#define SRSHARP1_RO_FMETER_VCNT_TYPE2 (SRSHARP1_OFFSET + SHARP_RO_FMETER_VCNT_TYPE2 ) // 0x4c
+#define SRSHARP1_RO_FMETER_VCNT_TYPE3 (SRSHARP1_OFFSET + SHARP_RO_FMETER_VCNT_TYPE3 ) // 0x4d
+#define SRSHARP1_RO_FMETER_PDCNT_TYPE0 (SRSHARP1_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE0 ) // 0x4e
+#define SRSHARP1_RO_FMETER_PDCNT_TYPE1 (SRSHARP1_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE1 ) // 0x4f
+#define SRSHARP1_RO_FMETER_PDCNT_TYPE2 (SRSHARP1_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE2 ) // 0x50
+#define SRSHARP1_RO_FMETER_PDCNT_TYPE3 (SRSHARP1_OFFSET + SHARP_RO_FMETER_PDCNT_TYPE3 ) // 0x51
+#define SRSHARP1_RO_FMETER_NDCNT_TYPE0 (SRSHARP1_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE0 ) // 0x52
+#define SRSHARP1_RO_FMETER_NDCNT_TYPE1 (SRSHARP1_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE1 ) // 0x53
+#define SRSHARP1_RO_FMETER_NDCNT_TYPE2 (SRSHARP1_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE2 ) // 0x54
+#define SRSHARP1_RO_FMETER_NDCNT_TYPE3 (SRSHARP1_OFFSET + SHARP_RO_FMETER_NDCNT_TYPE3 ) // 0x55
+
+
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: srsharp_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VPPE_VCBUS_BASE = 0x51
+// -----------------------------------------------
+// 8'h50/51/52/53 have used for srsharp_regs
+//===========================================================================
+//
+// Reading file: srsharp_regs2.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//SRSHARP0 8'h00 - 8'hff
+//SRSHARP1 8'h100 - 8'1ff
+#define SRSHARP0_OFFSET (0x000<<2)
+#define SRSHARP1_OFFSET (0x200<<2)
+
+//
+// Reading file: sharp_regs2.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define SR7_DRTLPF_EN ((0x5100 << 2) + 0xff000000)
+//Bit 31:11, reserved
+//Bit 10, reg_sr7_drtlpf_beta_en2 : enable of direction ambiguity protection for drt_lpf, beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), 0, equivalent beta[i]=15, 1, enable. unsigned , default = 0
+//Bit 9, reg_sr7_drtlpf_beta_en1 : enable of direction ambiguity protection for drt_lpf, beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), 0, equivalent beta[i]=15, 1, enable. unsigned , default = 0
+//Bit 8, reg_sr7_drtlpf_beta_en0 : enable of direction ambiguity protection for drt_lpf, beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), 0, equivalent beta[i]=15, 1, enable. unsigned , default = 0
+//Bit 7: 6, reserved
+//Bit 5, reg_sr7_drtlpf_edge_en2 : enable of direction lpf based on edge strength. unsigned , default = 0
+//Bit 4, reg_sr7_drtlpf_edge_en1 : enable of direction lpf based on edge strength. unsigned , default = 0
+//Bit 3, reg_sr7_drtlpf_edge_en0 : enable of direction lpf based on edge strength. unsigned , default = 0
+//Bit 2, reg_sr7_drtlpf_sdfd_en2 : sdfd gamma (HF burst compare to real edge protection) enable. 0: not enable, 1:enable protection. unsigned , default = 1
+//Bit 1, reg_sr7_drtlpf_sdfd_en1 : sdfd gamma (HF burst compare to real edge protection) enable. 0: not enable, 1:enable protection. unsigned , default = 1
+//Bit 0, reg_sr7_drtlpf_sdfd_en0 : sdfd gamma (HF burst compare to real edge protection) enable. 0: not enable, 1:enable protection. unsigned , default = 1
+#define SR7_DRTLPF_BETA ((0x5101 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_drtlpf_beta3 : beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo lpf. unsigned , default = 0
+//Bit 11: 8, reg_sr7_drtlpf_beta2 : beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo lpf. unsigned , default = 4
+//Bit 7: 4, reg_sr7_drtlpf_beta1 : beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo lpf. unsigned , default = 8
+//Bit 3: 0, reg_sr7_drtlpf_beta0 : beta for drt filter coef base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo lpf. unsigned , default = 15
+#define SR7_PKBLD_BETA ((0x5102 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_pkdrtbld_beta3 : beta for drt and cir blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use cir wo drt. unsigned , default = 0
+//Bit 11: 8, reg_sr7_pkdrtbld_beta2 : beta for drt and cir blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use cir wo drt. unsigned , default = 4
+//Bit 7: 4, reg_sr7_pkdrtbld_beta1 : beta for drt and cir blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use cir wo drt. unsigned , default = 8
+//Bit 3: 0, reg_sr7_pkdrtbld_beta0 : beta for drt and cir blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use cir wo drt. unsigned , default = 15
+#define SR7_XLTIBLD_BETA ((0x5103 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_xlti_dcbld_beta3 : beta for denoise and org dc blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 0
+//Bit 11: 8, reg_sr7_xlti_dcbld_beta2 : beta for denoise and org dc blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 4
+//Bit 7: 4, reg_sr7_xlti_dcbld_beta1 : beta for denoise and org dc blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 8
+//Bit 3: 0, reg_sr7_xlti_dcbld_beta0 : beta for denoise and org dc blend base on the x=cal_drt_dif8(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 15
+#define SR7_DRTLPF_EDGE0 ((0x5104 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_drtlpf_edge7 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_drtlpf_edge6 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_drtlpf_edge5 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_drtlpf_edge4 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_drtlpf_edge3 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_drtlpf_edge2 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_drtlpf_edge1 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_drtlpf_edge0 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+#define SR7_DRTLPF_EDGE1 ((0x5105 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_drtlpf_edge15 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_drtlpf_edge14 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_drtlpf_edge13 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_drtlpf_edge12 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_drtlpf_edge11 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_drtlpf_edge10 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_drtlpf_edge9 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_drtlpf_edge8 : edge lamda for drt lpf base on max_sad [0:16:128~255];. unsigned , default = 15
+#define SR7_DRTLPF_SDCOR0 ((0x5106 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_drtlpf_sdcor7 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_drtlpf_sdcor6 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_drtlpf_sdcor5 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_drtlpf_sdcor4 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_drtlpf_sdcor3 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_drtlpf_sdcor2 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_drtlpf_sdcor1 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_drtlpf_sdcor0 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+#define SR7_DRTLPF_SDCOR1 ((0x5107 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_drtlpf_sdcor15 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_drtlpf_sdcor14 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_drtlpf_sdcor13 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_drtlpf_sdcor12 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_drtlpf_sdcor11 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_drtlpf_sdcor10 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_drtlpf_sdcor9 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_drtlpf_sdcor8 : gamma for drt lpf base on SD'[0:16:128~255];. unsigned , default = 15
+#define SR7_CTIGAIN_SDCOR0 ((0x5108 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_ctigain_sdcor7 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_ctigain_sdcor6 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_ctigain_sdcor5 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_ctigain_sdcor4 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_ctigain_sdcor3 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_ctigain_sdcor2 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_ctigain_sdcor1 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_ctigain_sdcor0 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+#define SR7_CTIGAIN_SDCOR1 ((0x5109 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_ctigain_sdcor15 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_ctigain_sdcor14 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_ctigain_sdcor13 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_ctigain_sdcor12 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_ctigain_sdcor11 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_ctigain_sdcor10 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_ctigain_sdcor9 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_ctigain_sdcor8 : adaptive gamma for cti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+#define SR7_LTIGAIN_SDCOR0 ((0x510a << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_ltigain_sdcor7 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_ltigain_sdcor6 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_ltigain_sdcor5 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_ltigain_sdcor4 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_ltigain_sdcor3 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_ltigain_sdcor2 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_ltigain_sdcor1 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_ltigain_sdcor0 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+#define SR7_LTIGAIN_SDCOR1 ((0x510b << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_ltigain_sdcor15 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 27:24, reg_sr7_ltigain_sdcor14 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 23:20, reg_sr7_ltigain_sdcor13 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 19:16, reg_sr7_ltigain_sdcor12 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 15:12, reg_sr7_ltigain_sdcor11 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 11: 8, reg_sr7_ltigain_sdcor10 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 7: 4, reg_sr7_ltigain_sdcor9 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+//Bit 3: 0, reg_sr7_ltigain_sdcor8 : adaptive gamma for lti boost gain base on SD'[0:16:128~255];. unsigned , default = 15
+#define SR7_HLTIBPF_TAP0 ((0x510c << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_hlti_bpf_tap153 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0
+//Bit 23:16, reg_sr7_hlti_bpf_tap152 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -34
+//Bit 15: 8, reg_sr7_hlti_bpf_tap151 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -1
+//Bit 7: 0, reg_sr7_hlti_bpf_tap150 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 120
+#define SR7_HLTIBPF_TAP1 ((0x510d << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_hlti_bpf_tap157 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 2
+//Bit 23:16, reg_sr7_hlti_bpf_tap156 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -7
+//Bit 15: 8, reg_sr7_hlti_bpf_tap155 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 1
+//Bit 7: 0, reg_sr7_hlti_bpf_tap154 : tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -21
+#define SR7_HCTIBPF_TAP0 ((0x510e << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_hcti_bpf_tap153 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0
+//Bit 23:16, reg_sr7_hcti_bpf_tap152 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -34
+//Bit 15: 8, reg_sr7_hcti_bpf_tap151 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -1
+//Bit 7: 0, reg_sr7_hcti_bpf_tap150 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 120
+#define SR7_HCTIBPF_TAP1 ((0x510f << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_hcti_bpf_tap157 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 2
+//Bit 23:16, reg_sr7_hcti_bpf_tap156 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -7
+//Bit 15: 8, reg_sr7_hcti_bpf_tap155 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 1
+//Bit 7: 0, reg_sr7_hcti_bpf_tap154 : tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -21
+#define SR7_PKLONGBPF_HTAP0 ((0x5110 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_bpf_hztap153 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -24
+//Bit 23:16, reg_sr7_pk_long_bpf_hztap152 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -19
+//Bit 15: 8, reg_sr7_pk_long_bpf_hztap151 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 31
+//Bit 7: 0, reg_sr7_pk_long_bpf_hztap150 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 66
+#define SR7_PKLONGBPF_HTAP1 ((0x5111 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_bpf_hztap157 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -6
+//Bit 23:16, reg_sr7_pk_long_bpf_hztap156 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -10
+//Bit 15: 8, reg_sr7_pk_long_bpf_hztap155 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -1
+//Bit 7: 0, reg_sr7_pk_long_bpf_hztap154 : tap15 BPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -4
+#define SR7_PKLONGHPF_HTAP0 ((0x5112 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_hpf_hztap153 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 27
+//Bit 23:16, reg_sr7_pk_long_hpf_hztap152 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -15
+//Bit 15: 8, reg_sr7_pk_long_hpf_hztap151 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -32
+//Bit 7: 0, reg_sr7_pk_long_hpf_hztap150 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 58
+#define SR7_PKLONGHPF_HTAP1 ((0x5113 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_hpf_hztap157 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 8
+//Bit 23:16, reg_sr7_pk_long_hpf_hztap156 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -6
+//Bit 15: 8, reg_sr7_pk_long_hpf_hztap155 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -1
+//Bit 7: 0, reg_sr7_pk_long_hpf_hztap154 : tap15 HPF for horizontal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -10
+#define SR7_VLTIBPF_TAP0 ((0x5114 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_vlti_bpf_tap093 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0
+//Bit 23:16, reg_sr7_vlti_bpf_tap092 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -41
+//Bit 15: 8, reg_sr7_vlti_bpf_tap091 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0
+//Bit 7: 0, reg_sr7_vlti_bpf_tap090 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 126
+#define SR7_VLTIBPF_TAP1 ((0x5115 << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_sr7_vlti_bpf_tap094 : tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -22
+#define SR7_VCTIBPF_TAP0 ((0x5116 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_vcti_bpf_tap093 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0
+//Bit 23:16, reg_sr7_vcti_bpf_tap092 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -41
+//Bit 15: 8, reg_sr7_vcti_bpf_tap091 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 0
+//Bit 7: 0, reg_sr7_vcti_bpf_tap090 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = 126
+#define SR7_VCTIBPF_TAP1 ((0x5117 << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_sr7_vcti_bpf_tap094 : tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0. signed , default = -22
+#define SR7_PKLONGBPF_VTAP0 ((0x5118 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_bpf_vdtap093 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -32
+//Bit 23:16, reg_sr7_pk_long_bpf_vdtap092 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -28
+//Bit 15: 8, reg_sr7_pk_long_bpf_vdtap091 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 30
+//Bit 7: 0, reg_sr7_pk_long_bpf_vdtap090 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 68
+#define SR7_PKLONGBPF_VTAP1 ((0x5119 << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_sr7_pk_long_bpf_vdtap094 : tap09 BPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -4
+#define SR7_PKLONGHPF_VTAP0 ((0x511a << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_hpf_vdtap093 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 30
+//Bit 23:16, reg_sr7_pk_long_hpf_vdtap092 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -28
+//Bit 15: 8, reg_sr7_pk_long_hpf_vdtap091 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -31
+//Bit 7: 0, reg_sr7_pk_long_hpf_vdtap090 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = 68
+#define SR7_PKLONGHPF_VTAP1 ((0x511b << 2) + 0xff000000)
+//Bit 31: 8, reserved
+//Bit 7: 0, reg_sr7_pk_long_hpf_vdtap094 : tap09 HPF for vertical and diagonal peaking filter, only store half of the filter normalized to 258 as 1.0. signed , default = -5
+#define SR7_CIRBPLONG_ALP ((0x511c << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_cirbp_long_alpha3 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+//Bit 11: 8, reg_sr7_cirbp_long_alpha2 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+//Bit 7: 4, reg_sr7_cirbp_long_alpha1 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+//Bit 3: 0, reg_sr7_cirbp_long_alpha0 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+#define SR7_CIRHPLONG_ALP ((0x511d << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_cirhp_long_alpha3 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+//Bit 11: 8, reg_sr7_cirhp_long_alpha2 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+//Bit 7: 4, reg_sr7_cirhp_long_alpha1 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+//Bit 3: 0, reg_sr7_cirhp_long_alpha0 : alpha to blend bp_long to the cirpk filter corresponding angle (0/45/90/135), norm to 16 as 1.0; default = 15, ==0 means same as s6-;. unsigned , default = 15
+#define SR7_DRTBPLONG_ALP ((0x511e << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_drtbp_long_alpha7 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 27:24, reg_sr7_drtbp_long_alpha6 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 23:20, reg_sr7_drtbp_long_alpha5 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 19:16, reg_sr7_drtbp_long_alpha4 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 15:12, reg_sr7_drtbp_long_alpha3 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 11: 8, reg_sr7_drtbp_long_alpha2 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 7: 4, reg_sr7_drtbp_long_alpha1 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 3: 0, reg_sr7_drtbp_long_alpha0 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+#define SR7_DRTHPLONG_ALP ((0x511f << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_drthp_long_alpha7 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 27:24, reg_sr7_drthp_long_alpha6 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 23:20, reg_sr7_drthp_long_alpha5 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 19:16, reg_sr7_drthp_long_alpha4 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 15:12, reg_sr7_drthp_long_alpha3 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 11: 8, reg_sr7_drthp_long_alpha2 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 7: 4, reg_sr7_drthp_long_alpha1 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+//Bit 3: 0, reg_sr7_drthp_long_alpha0 : alpha to blend bp_long to the drtpk filter corresponding angle (8 angles), norm to 16 as 1.0; default = 0, ==0 means same as s6-;. unsigned , default = 15
+#define SR7_PKMINMAXCIR_BLD_LUT2D0 ((0x5120 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_cirbld_lut2d7 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0
+//Bit 27:24, reg_sr7_pk_mimaxerr2_cirbld_lut2d6 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0
+//Bit 23:20, reg_sr7_pk_mimaxerr2_cirbld_lut2d5 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 19:16, reg_sr7_pk_mimaxerr2_cirbld_lut2d4 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d3 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d2 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d1 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d0 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+#define SR7_PKMINMAXCIR_BLD_LUT2D1 ((0x5121 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_cirbld_lut2d15 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 27:24, reg_sr7_pk_mimaxerr2_cirbld_lut2d14 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0
+//Bit 23:20, reg_sr7_pk_mimaxerr2_cirbld_lut2d13 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 19:16, reg_sr7_pk_mimaxerr2_cirbld_lut2d12 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d11 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d10 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d9 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d8 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+#define SR7_PKMINMAXCIR_BLD_LUT2D2 ((0x5122 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_cirbld_lut2d23 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 27:24, reg_sr7_pk_mimaxerr2_cirbld_lut2d22 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 10
+//Bit 23:20, reg_sr7_pk_mimaxerr2_cirbld_lut2d21 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 19:16, reg_sr7_pk_mimaxerr2_cirbld_lut2d20 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d19 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d18 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d17 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d16 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12
+#define SR7_PKMINMAXCIR_BLD_LUT2D3 ((0x5123 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_cirbld_lut2d31 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 14
+//Bit 27:24, reg_sr7_pk_mimaxerr2_cirbld_lut2d30 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 23:20, reg_sr7_pk_mimaxerr2_cirbld_lut2d29 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 19:16, reg_sr7_pk_mimaxerr2_cirbld_lut2d28 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 8
+//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d27 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 10
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d26 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d25 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d24 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+#define SR7_PKMINMAXCIR_BLD_LUT2D4 ((0x5124 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_pk_mimaxerr2_cirbld_lut2d35 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_cirbld_lut2d34 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_cirbld_lut2d33 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_cirbld_lut2d32 : 2D-LUT for alpha2 for cir-PK blender,larger coef means less drt-pk, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12
+#define SR7_PKMINMAXLPF_BLD_LUT2D0 ((0x5125 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_lpfbld_lut2d7 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0
+//Bit 27:24, reg_sr7_pk_mimaxerr2_lpfbld_lut2d6 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0
+//Bit 23:20, reg_sr7_pk_mimaxerr2_lpfbld_lut2d5 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 19:16, reg_sr7_pk_mimaxerr2_lpfbld_lut2d4 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d3 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d2 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d1 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d0 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+#define SR7_PKMINMAXLPF_BLD_LUT2D1 ((0x5126 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_lpfbld_lut2d15 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 27:24, reg_sr7_pk_mimaxerr2_lpfbld_lut2d14 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 0
+//Bit 23:20, reg_sr7_pk_mimaxerr2_lpfbld_lut2d13 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 19:16, reg_sr7_pk_mimaxerr2_lpfbld_lut2d12 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d11 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d10 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d9 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d8 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+#define SR7_PKMINMAXLPF_BLD_LUT2D2 ((0x5127 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_lpfbld_lut2d23 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 27:24, reg_sr7_pk_mimaxerr2_lpfbld_lut2d22 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 10
+//Bit 23:20, reg_sr7_pk_mimaxerr2_lpfbld_lut2d21 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 19:16, reg_sr7_pk_mimaxerr2_lpfbld_lut2d20 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d19 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d18 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d17 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 6
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d16 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12
+#define SR7_PKMINMAXLPF_BLD_LUT2D3 ((0x5128 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_pk_mimaxerr2_lpfbld_lut2d31 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 14
+//Bit 27:24, reg_sr7_pk_mimaxerr2_lpfbld_lut2d30 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 23:20, reg_sr7_pk_mimaxerr2_lpfbld_lut2d29 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+//Bit 19:16, reg_sr7_pk_mimaxerr2_lpfbld_lut2d28 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 8
+//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d27 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 10
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d26 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d25 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 2
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d24 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 4
+#define SR7_PKMINMAXLPF_BLD_LUT2D4 ((0x5129 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_pk_mimaxerr2_lpfbld_lut2d35 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 11: 8, reg_sr7_pk_mimaxerr2_lpfbld_lut2d34 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 7: 4, reg_sr7_pk_mimaxerr2_lpfbld_lut2d33 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 15
+//Bit 3: 0, reg_sr7_pk_mimaxerr2_lpfbld_lut2d32 : 2D-LUT for alpha2 for PK lpf along edge blender, lareger coef means less lpf along edge, x-min_err, y-max_err, nodes as 0,8,16,32,64,128,192,256, use bilinear interpolation, mi=0,ma=0.8..256; mi=8, ma=8..256, .... unsigned , default = 12
+#define SR7_PKDRT_BLD_EN ((0x512a << 2) + 0xff000000)
+//Bit 31: 1, reserved
+//Bit 0, reg_sr7_pkdrtbld_beta_en : enable of direction ambiguity protection for drt and cir blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 0
+#define SR7_DRTDIF_TH ((0x512b << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15: 8, reg_sr7_drtdif_min2sad_th1 : for min2_sad threshold for ambiguilty ignoring, if (min_sad<min2_sad/2 && min2_sad>thrd) drt_dif=1;. unsigned , default = 128
+//Bit 7: 0, reg_sr7_drtdif_min2sad_th0 : for min2_sad threshold for ambiguilty ignoring, if (min_sad<min2_sad/2 && min2_sad>thrd) drt_dif=1;. unsigned , default = 128
+#define SR7_TIBLD_PRT ((0x512c << 2) + 0xff000000)
+//Bit 31:14, reserved
+//Bit 13, reg_sr7_hlti_dcbld_beta_en : enable of denoise protection for dc org and denoise blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 1
+//Bit 12, reg_sr7_vlti_dcbld_beta_en : enable of denoise protection for dc org and denoise blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 1
+//Bit 11: 8, reg_sr7_xcti_dcbld_beta1 : beta for denoise and org dc blend base on the x=cal_drt_dif4(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 0
+//Bit 7: 4, reg_sr7_xcti_dcbld_beta0 : beta for denoise and org dc blend base on the x=cal_drt_dif4(min_idx,min2_idx), beta = lut[x-1], the larger of x, means the higher possibility for ambiguilty, beta=0 use org wo denoise. unsigned , default = 15
+//Bit 3, reg_sr7_hcti_dcbld_beta_en : enable of denoise protection for dc org and denoise blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 1
+//Bit 2, reg_sr7_vcti_dcbld_beta_en : enable of denoise protection for dc org and denoise blend, beta for , 0, equivalent beta[i]=15, 1, enable. unsigned , default = 1
+//Bit 1, reg_sr7_hcti_dcbld_use_ybeta : enable to use beta from hlti, 0, use c-beta, 1, use y-beta. unsigned , default = 0
+//Bit 0, reg_sr7_vcti_dcbld_use_ybeta : enable to use beta from vlti, 0, use c-beta, 1, use y-beta. unsigned , default = 0
+#define SR7_HTI_OPT_FORCE ((0x512d << 2) + 0xff000000)
+//Bit 31: 6, reserved
+//Bit 5, reg_sr7_diag_force_hti1 : force hti for diagonal edges luma/chroma, 0: diagonal use vti, 1: diagonal use hti, default=1. unsigned , default = 1
+//Bit 4, reg_sr7_diag_force_hti0 : force hti for diagonal edges luma/chroma, 0: diagonal use vti, 1: diagonal use hti, default=1. unsigned , default = 1
+//Bit 3, reg_sr7_horz_force_vti1 : force vti for horizontal edges luma/chroma, 0: bias hti, 1: horizontal edge force 100% vti, default=1. unsigned , default = 1
+//Bit 2, reg_sr7_horz_force_vti0 : force vti for horizontal edges luma/chroma, 0: bias hti, 1: horizontal edge force 100% vti, default=1. unsigned , default = 1
+//Bit 1, reg_sr7_alph_force_hvsad1 : alpha = minsad*64/maxsad, force minsad=sad_h, maxsad=sad_v for alpha calculation, [0]for luma, [1] for chroma. if sad_h>sad_v alpha will be large, default=1. unsigned , default = 1
+//Bit 0, reg_sr7_alph_force_hvsad0 : alpha = minsad*64/maxsad, force minsad=sad_h, maxsad=sad_v for alpha calculation, [0]for luma, [1] for chroma. if sad_h>sad_v alpha will be large, default=1. unsigned , default = 1
+#define SR7_HVTI_FINALGAIN ((0x512e << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:16, reg_sr7_hvti_finalgain1 : final gain for HVTI boost, for easier level tunning for application, normalized to 256 as 1.0 default = 256. unsigned , default = 256
+//Bit 15:12, reserved
+//Bit 11: 0, reg_sr7_hvti_finalgain0 : final gain for HVTI boost, for easier level tunning for application, normalized to 256 as 1.0 default = 256. unsigned , default = 256
+#define SR7_TIOS_SDRATIO ((0x512f << 2) + 0xff000000)
+//Bit 31:30, reserved
+//Bit 29:24, reg_sr7_hti_osmargin_sdratio1 : ratio for HTI OS margin adaptive to sd. osmargin= (sd*ratio)>>6; default=3. unsigned , default = 3
+//Bit 23:22, reserved
+//Bit 21:16, reg_sr7_hti_osmargin_sdratio0 : ratio for HTI OS margin adaptive to sd. osmargin= (sd*ratio)>>6; default=3. unsigned , default = 3
+//Bit 15:14, reserved
+//Bit 13: 8, reg_sr7_vti_osmargin_sdratio1 : ratio for VTI OS margin adaptive to sd. osmargin= (sd*ratio)>>6; default=3. unsigned , default = 3
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_sr7_vti_osmargin_sdratio0 : ratio for VTI OS margin adaptive to sd. osmargin= (sd*ratio)>>6; default=3. unsigned , default = 3
+#define SR7_XTI_SDFDEN ((0x5130 << 2) + 0xff000000)
+//Bit 31: 2, reserved
+//Bit 1, reg_sr7_xtigain_sdfd_en1 : adaptive gamma for cti boost gain enable.[0]for luma, [1] for chroma. 0: not enable, 1:enable, default = 1. unsigned , default = 1
+//Bit 0, reg_sr7_xtigain_sdfd_en0 : adaptive gamma for cti boost gain enable.[0]for luma, [1] for chroma. 0: not enable, 1:enable, default = 1. unsigned , default = 1
+#define SR7_FDSD_PARAM ((0x5131 << 2) + 0xff000000)
+//Bit 31:26, reserved
+//Bit 25, reg_fdsd_vlpf_en : use vertical [1 2 1] lpf filter for the fd and sd derivativecalculations. unsigned , default = 1
+//Bit 24, reg_fdsd_hlpf_en : use horizontal [1 2 1] lpf filter for the fd and sd derivativecalculations. unsigned , default = 1
+//Bit 23:20, reg_sd_coring_th1 : coring to SD'= MAX(SD - FD*ratio - coring,0); default = 0. unsigned , default = 0
+//Bit 19:16, reg_sd_coring_th0 : coring to SD'= MAX(SD - FD*ratio - coring,0); default = 0. unsigned , default = 0
+//Bit 15:14, reserved
+//Bit 13: 8, reg_sd_coring_ratio2fd1 : ratio to FD for adaptive coring to SD'= MAX(SD - FD*ratio - coring,0); normalized 64 as 1.0 default = 4. unsigned , default = 4
+//Bit 7: 6, reserved
+//Bit 5: 0, reg_sd_coring_ratio2fd0 : ratio to FD for adaptive coring to SD'= MAX(SD - FD*ratio - coring,0); normalized 64 as 1.0 default = 4. unsigned , default = 4
+#define SR7_TI_BPF_EN ((0x5132 << 2) + 0xff000000)
+//Bit 31: 4, reserved
+//Bit 3, reg_sr7_hlti_bpf_en : enable of tap15 BPF for hlti (gain3), only store half of the filter normalized to 258 as 1.0. unsigned , default = 1
+//Bit 2, reg_sr7_hcti_bpf_en : enable of tap15 BPF for hcti (gain3), only store half of the filter normalized to 258 as 1.0. unsigned , default = 1
+//Bit 1, reg_sr7_vlti_bpf_en : enable of tap09 BPF for vlti (gain3), only store half of the filter normalized to 258 as 1.0, mainly for 2x2 UP case. unsigned , default = 1
+//Bit 0, reg_sr7_vcti_bpf_en : enable of tap09 BPF for vcti (gain3), only store half of the filter normalized to 258 as 1.0, mainly for 2x2 UP case. unsigned , default = 1
+#define SR7_PKLONG_PF_EN ((0x5133 << 2) + 0xff000000)
+//Bit 31: 2, reserved
+//Bit 1, reg_sr7_pk_long_bpf_en : enable of long BPF for peaking only store half of the filter normalized to 258 as 1.0. unsigned , default = 1
+//Bit 0, reg_sr7_pk_long_hpf_en : enable of long HPF for peaking only store half of the filter normalized to 258 as 1.0. unsigned , default = 1
+#define SR7_PKLONG_PF_GAIN ((0x5134 << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_pk_long_bpf_hzgain : gain to long horizontal BPF for peaking, normalized to 64 as 1.0. unsigned , default = 64
+//Bit 23:16, reg_sr7_pk_long_bpf_vdgain : gain to long vertical and diagonal BPF for peaking, normalized to 64 as 1.0. unsigned , default = 64
+//Bit 15: 8, reg_sr7_pk_long_hpf_hzgain : gain to long horizontal HPF for peaking, normalized to 64 as 1.0. unsigned , default = 64
+//Bit 7: 0, reg_sr7_pk_long_hpf_vdgain : gain to long vertical and diagonal HPF for peaking, normalized to 64 as 1.0. unsigned , default = 64
+#define SR7_PKMINMAX_BLD ((0x5135 << 2) + 0xff000000)
+//Bit 31: 4, reserved
+//Bit 3, reg_sr7_pk_mimaxerr2_cirbld_on_bp : enable to use adaptive blender of drtBP vs cirBP alpha2, the larger of cell, the more cirPK results, 0: alp2=lut2d(minerr, maxerr),1:alp2=min_err/maxerr,default = 1. unsigned , default = 1
+//Bit 2, reg_sr7_pk_mimaxerr2_cirbld_on_hp : enable to use adaptive blender of drtHP vs cirHP alpha2, the larger of cell, the more cirPK results, 0: alp2=lut2d(minerr, maxerr),1:alp2=min_err/maxerr,default = 1. unsigned , default = 1
+//Bit 1, reg_sr7_pk_mimaxerr2_lpfbld_on_bp : enable to use adaptive blender of BP result lpf along edge based on the mimaxsad relationship, default = 1. unsigned , default = 1
+//Bit 0, reg_sr7_pk_mimaxerr2_lpfbld_on_hp : enable to use adaptive blender of HP result lpf along edge based on the mimaxsad relationship, default = 1. unsigned , default = 1
+#define SR7_TI_CONMAXERR_GAIN ((0x5136 << 2) + 0xff000000)
+//Bit 31:16, reserved
+//Bit 15:12, reg_sr7_hti_conmaxerr_gain1 : con=max(con, maxerr) for the horizontal transition calculation, gain=0, same as s6 and prev, [0] for y and [1] for uv. unsigned , default = 8
+//Bit 11: 8, reg_sr7_hti_conmaxerr_gain0 : con=max(con, maxerr) for the horizontal transition calculation, gain=0, same as s6 and prev, [0] for y and [1] for uv. unsigned , default = 8
+//Bit 7: 4, reg_sr7_vti_conmaxerr_gain1 : con=max(con, maxerr) for the vertical transition calculation, gain=0, same as s6 and prev, [0] for y and [1] for uv. unsigned , default = 8
+//Bit 3: 0, reg_sr7_vti_conmaxerr_gain0 : con=max(con, maxerr) for the vertical transition calculation, gain=0, same as s6 and prev, [0] for y and [1] for uv. unsigned , default = 8
+#define SR7_CC_PK_ADJ ((0x5137 << 2) + 0xff000000)
+//Bit 31:25, reserved
+//Bit 24, reg_sr7_cc_enable : color compensation enable, 0: no CC, 1: with CC, default = 1. unsigned , default = 1
+//Bit 23:22, reserved
+//Bit 21:20, reg_sr7_cc_yinp_sel : color compensation input luma selection, 0: org_y; 1: gau_y ; 2:gauadp_y; 3:edgeadp_y (same as dnlp input sel), default= 0. unsigned , default = 0
+//Bit 19:18, reg_sr7_cc_ydlt_sel : color compensation output luma selection, 0: peaking+lti output; 1: dnlp output; 2/3: peaking+lti+dnlp, default = 2. unsigned , default = 2
+//Bit 17:16, reg_sr7_cc_sat_norm : normalization of lut cell to saturation. 0: norm to 8 as 1.0, sat[0:23/8]; 1: norm to 16 as 1.0, sat[1/16:31/16]; 2: norm to 32 as 1.0, sat[17/32:47/32]; 3:norm to 64 as 1.0, sat[49/64:79/64]. unsigned , default = 1
+//Bit 15: 8, reg_sr7_cc_ydlt_pscl : prescale to the y-delta (if >0) before feeding to y-lumadlt, normalized 64 as 1.0. default = 64.. unsigned , default = 64
+//Bit 7: 0, reg_sr7_cc_ydlt_nscl : prescale to the y-delta (if <0) before feeding to y-lumadlt, normalized 64 as 1.0. default = 64.. unsigned , default = 64
+#define SR7_CC_LUT0 ((0x5138 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_cc_lut003 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=0, dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 27:24, reg_sr7_cc_lut002 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=0, dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 23:20, reg_sr7_cc_lut001 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=0, dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 19:16, reg_sr7_cc_lut000 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=0, dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 15:12, reg_sr7_cc_lut103 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=1/8 dft={1, 2, 4, 8}. unsigned , default = 8
+//Bit 11: 8, reg_sr7_cc_lut102 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=1/8 dft={1, 2, 4, 8}. unsigned , default = 4
+//Bit 7: 4, reg_sr7_cc_lut101 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=1/8 dft={1, 2, 4, 8}. unsigned , default = 2
+//Bit 3: 0, reg_sr7_cc_lut100 : valid for y-lumadlt= 1/4, 1/2, 3/4, 1.0; of x-lumainput=1/8 dft={1, 2, 4, 8}. unsigned , default = 1
+#define SR7_CC_LUT1 ((0x5139 << 2) + 0xff000000)
+//Bit 31:28, reserved
+//Bit 27:24, reg_sr7_cc_lut202 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=2/8 dft={4, 8,12}. unsigned , default = 12
+//Bit 23:20, reg_sr7_cc_lut201 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=2/8 dft={4, 8,12}. unsigned , default = 8
+//Bit 19:16, reg_sr7_cc_lut200 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=2/8 dft={4, 8,12}. unsigned , default = 4
+//Bit 15:12, reserved
+//Bit 11: 8, reg_sr7_cc_lut302 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=3/8 dft={5,10,15}. unsigned , default = 15
+//Bit 7: 4, reg_sr7_cc_lut301 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=3/8 dft={5,10,15}. unsigned , default = 10
+//Bit 3: 0, reg_sr7_cc_lut300 : valid for y-lumadlt= 1/4, 1/2, 3/4 ; of x-lumainput=3/8 dft={5,10,15}. unsigned , default = 5
+#define SR7_CC_LUT2 ((0x513a << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:20, reg_sr7_cc_lut401 : valid for y-lumadlt= 1/4, 1/2, ; of x-lumainput=4/8 dft={8,15}. unsigned , default = 15
+//Bit 19:16, reg_sr7_cc_lut400 : valid for y-lumadlt= 1/4, 1/2, ; of x-lumainput=4/8 dft={8,15}. unsigned , default = 8
+//Bit 15:12, reg_sr7_cc_lut501 : valid for y-lumadlt= 1/4, 1/2, ; of x-lumainput=5/8 dft={6,13}. unsigned , default = 13
+//Bit 11: 8, reg_sr7_cc_lut500 : valid for y-lumadlt= 1/4, 1/2, ; of x-lumainput=5/8 dft={6,13}. unsigned , default = 6
+//Bit 7: 4, reg_sr7_cc_lut600 : valid for y-lumadlt= 1/4, ; of x-lumainput=6/8 dft={5}. unsigned , default = 5
+//Bit 3: 0, reg_sr7_cc_lut700 : valid for y-lumadlt= 1/4, ; of x-lumainput=7/8 dft={4}. unsigned , default = 4
+#define SR7_CC_LUT3 ((0x513b << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:20, reg_sr7_cc_lut710 : valid for y-lumadlt= -1/4, ; of x-lumainput=1/8 dft={4}. unsigned , default = 4
+//Bit 19:16, reg_sr7_cc_lut610 : valid for y-lumadlt= -1/4, ; of x-lumainput=2/8 dft={5}. unsigned , default = 5
+//Bit 15:12, reg_sr7_cc_lut511 : valid for y-lumadlt= -1/4, -1/2, ; of x-lumainput=3/8 dft={6,13}. unsigned , default = 13
+//Bit 11: 8, reg_sr7_cc_lut510 : valid for y-lumadlt= -1/4, -1/2, ; of x-lumainput=3/8 dft={6,13}. unsigned , default = 6
+//Bit 7: 4, reg_sr7_cc_lut411 : valid for y-lumadlt= -1/4, -1/2, ; of x-lumainput=4/8 dft={8,15}. unsigned , default = 15
+//Bit 3: 0, reg_sr7_cc_lut410 : valid for y-lumadlt= -1/4, -1/2, ; of x-lumainput=4/8 dft={8,15}. unsigned , default = 8
+#define SR7_CC_LUT4 ((0x513c << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:20, reg_sr7_cc_lut312 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=5/8 dft={5,10,15}. unsigned , default = 15
+//Bit 19:16, reg_sr7_cc_lut311 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=5/8 dft={5,10,15}. unsigned , default = 10
+//Bit 15:12, reg_sr7_cc_lut310 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=5/8 dft={5,10,15}. unsigned , default = 5
+//Bit 11: 8, reg_sr7_cc_lut212 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=6/8 dft={4, 8,12}. unsigned , default = 12
+//Bit 7: 4, reg_sr7_cc_lut211 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=6/8 dft={4, 8,12}. unsigned , default = 8
+//Bit 3: 0, reg_sr7_cc_lut210 : valid for y-lumadlt= -1/4, -1/2,-3/4, ; of x-lumainput=6/8 dft={4, 8,12}. unsigned , default = 4
+#define SR7_CC_LUT5 ((0x513d << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_cc_lut113 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=7/8 dft={1, 2, 4, 8}. unsigned , default = 8
+//Bit 27:24, reg_sr7_cc_lut112 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=7/8 dft={1, 2, 4, 8}. unsigned , default = 4
+//Bit 23:20, reg_sr7_cc_lut111 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=7/8 dft={1, 2, 4, 8}. unsigned , default = 2
+//Bit 19:16, reg_sr7_cc_lut110 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=7/8 dft={1, 2, 4, 8}. unsigned , default = 1
+//Bit 15:12, reg_sr7_cc_lut013 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=8/8 dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 11: 8, reg_sr7_cc_lut012 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=8/8 dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 7: 4, reg_sr7_cc_lut011 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=8/8 dft={0, 0, 0, 0}. unsigned , default = 0
+//Bit 3: 0, reg_sr7_cc_lut010 : valid for y-lumadlt= -1/4, -1/2,-3/4,-1.0; of x-lumainput=8/8 dft={0, 0, 0, 0}. unsigned , default = 0
+#define SR7_GRAPHIC_CTRL ((0x513e << 2) + 0xff000000)
+//Bit 31:11, reserved
+//Bit 10, reg_sr7_grph_en : enable graphic statistic . unsigned , default = 1
+//Bit 9, reg_sr7_grph_hflt : horizontal filter, 0: [0 1 -1], 1: [-1 2 -1]. unsigned , default = 1
+//Bit 8, reg_sr7_grph_vflt : vertical filter, 0: [0 1 -1], 1: [-1 2 -1]. unsigned , default = 1
+//Bit 7: 0, reg_sr7_grph_dif_cor : coring for dif while count for graphic. unsigned , default = 0
+#define SR7_GRAPHIC_THD_GAIN ((0x513f << 2) + 0xff000000)
+//Bit 31:24, reg_sr7_grph_flt_thd : flat threshold for dif while count for graphic. unsigned , default = 2
+//Bit 23:16, reg_sr7_grph_dtl_thd : detail threshold for dif while count for graphic. unsigned , default = 40
+//Bit 15: 8, reg_sr7_grph_hgain : horizontal gain for fast squart of hp. unsigned , default = 32
+//Bit 7: 0, reg_sr7_grph_vgain : vertical gain for fast squart of hp. unsigned , default = 32
+#define SR7_RO_GRAPHIC_FLT_CNT ((0x5140 << 2) + 0xff000000)
+//Bit 31: 0, ro_sr7_grph_flt_cnt : flat count numbers for graphic. unsigned , default = 0
+#define SR7_RO_GRAPHIC_DTL_CNT ((0x5141 << 2) + 0xff000000)
+//Bit 31: 0, ro_sr7_grph_dtl_cnt : detail count numbers for graphic. unsigned , default = 0
+#define SR7_CLR_PRT_PARAM ((0x5142 << 2) + 0xff000000)
+//Bit 31:18, reserved
+//Bit 17:16, reg_sr7_clr_prct_inpsel : input UV selection for color protection, 0: org; 1: NRout; 2: CTIout; 3: (NR+TIout)/2. unsigned , default = 3
+//Bit 15: 8, reg_sr7_clr_prct_dnlp_gain : gain to de-boost of dnlp_dlt base on color region, norm to 64 as 1.0. set to 0 as disable. unsigned , default = 64
+//Bit 7: 0, reg_sr7_clr_prct_peak_gain : gain to de-boost of peak_dlt base on color region, norm to 64 as 1.0, set to 0 as disable. unsigned , default = 64
+#define SR7_CLR_PRT_LC_GAIN ((0x5143 << 2) + 0xff000000)
+//Bit 31:24, reserved
+//Bit 23:16, reg_sr7_clr_prct_lc_gain2 : gain to de-boost of lc_dlt (y/u/v) base on color region, norm to 64 as 1.0, set to 0 as disable. unsigned , default = 64
+//Bit 15: 8, reg_sr7_clr_prct_lc_gain1 : gain to de-boost of lc_dlt (y/u/v) base on color region, norm to 64 as 1.0, set to 0 as disable. unsigned , default = 64
+//Bit 7: 0, reg_sr7_clr_prct_lc_gain0 : gain to de-boost of lc_dlt (y/u/v) base on color region, norm to 64 as 1.0, set to 0 as disable. unsigned , default = 64
+#define SR7_CLR_PRT_LUT0 ((0x5144 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut7 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut6 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut5 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut4 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut3 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut2 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut1 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut0 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT1 ((0x5145 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut15 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut14 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut13 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut12 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut11 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut10 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut9 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut8 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT2 ((0x5146 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut23 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut22 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut21 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut20 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut19 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut18 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut17 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut16 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT3 ((0x5147 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut31 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut30 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut29 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut28 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut27 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut26 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut25 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut24 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT4 ((0x5148 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut39 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut38 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut37 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut36 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut35 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut34 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut33 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut32 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT5 ((0x5149 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut47 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut46 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut45 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut44 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut43 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut42 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut41 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut40 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT6 ((0x514a << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut55 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut54 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut53 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut52 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut51 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut50 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut49 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut48 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT7 ((0x514b << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut63 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut62 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut61 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut60 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut59 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut58 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut57 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut56 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT8 ((0x514c << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut71 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut70 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut69 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut68 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut67 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut66 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut65 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut64 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT9 ((0x514d << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut79 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut78 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut77 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut76 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut75 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut74 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut73 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut72 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT10 ((0x514e << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut87 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut86 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut85 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut84 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut83 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut82 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut81 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut80 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT11 ((0x514f << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut95 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut94 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut93 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut92 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut91 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut90 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut89 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut88 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT12 ((0x5150 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut103 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut102 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut101 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut100 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut99 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut98 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut97 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut96 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT13 ((0x5151 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut111 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut110 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut109 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut108 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut107 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut106 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut105 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut104 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT14 ((0x5152 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut119 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut118 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut117 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut116 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut115 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut114 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut113 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut112 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT15 ((0x5153 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut127 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut126 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut125 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut124 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut123 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut122 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut121 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut120 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT16 ((0x5154 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut135 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut134 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut133 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut132 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut131 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut130 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut129 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut128 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT17 ((0x5155 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut143 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut142 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut141 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut140 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut139 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut138 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut137 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut136 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT18 ((0x5156 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut151 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 27:24, reg_sr7_clr_prct_lut150 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 23:20, reg_sr7_clr_prct_lut149 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 19:16, reg_sr7_clr_prct_lut148 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut147 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut146 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut145 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut144 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT19 ((0x5157 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut159 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut158 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut157 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut156 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut155 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut154 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut153 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 3: 0, reg_sr7_clr_prct_lut152 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+#define SR7_CLR_PRT_LUT20 ((0x5158 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut167 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 27:24, reg_sr7_clr_prct_lut166 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 23:20, reg_sr7_clr_prct_lut165 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 19:16, reg_sr7_clr_prct_lut164 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut163 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut162 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut161 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut160 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT21 ((0x5159 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut175 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut174 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut173 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut172 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut171 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut170 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut169 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 3: 0, reg_sr7_clr_prct_lut168 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+#define SR7_CLR_PRT_LUT22 ((0x515a << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut183 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 27:24, reg_sr7_clr_prct_lut182 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 23:20, reg_sr7_clr_prct_lut181 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 19:16, reg_sr7_clr_prct_lut180 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut179 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut178 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut177 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut176 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT23 ((0x515b << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut191 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut190 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut189 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut188 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut187 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut186 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut185 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 3: 0, reg_sr7_clr_prct_lut184 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+#define SR7_CLR_PRT_LUT24 ((0x515c << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut199 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 27:24, reg_sr7_clr_prct_lut198 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 23:20, reg_sr7_clr_prct_lut197 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 19:16, reg_sr7_clr_prct_lut196 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut195 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut194 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut193 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut192 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT25 ((0x515d << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut207 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut206 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut205 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut204 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut203 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut202 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut201 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 3: 0, reg_sr7_clr_prct_lut200 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+#define SR7_CLR_PRT_LUT26 ((0x515e << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut215 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 27:24, reg_sr7_clr_prct_lut214 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 23:20, reg_sr7_clr_prct_lut213 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 19:16, reg_sr7_clr_prct_lut212 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut211 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut210 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut209 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut208 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT27 ((0x515f << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut223 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut222 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut221 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut220 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut219 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut218 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut217 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 3: 0, reg_sr7_clr_prct_lut216 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+#define SR7_CLR_PRT_LUT28 ((0x5160 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut231 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 27:24, reg_sr7_clr_prct_lut230 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 23:20, reg_sr7_clr_prct_lut229 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 19:16, reg_sr7_clr_prct_lut228 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut227 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut226 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut225 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut224 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT29 ((0x5161 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut239 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut238 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut237 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut236 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut235 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut234 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut233 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+//Bit 3: 0, reg_sr7_clr_prct_lut232 : color protection lut, 16 is normalized to 1. unsigned , default = 15
+#define SR7_CLR_PRT_LUT30 ((0x5162 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut247 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut246 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut245 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut244 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut243 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut242 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut241 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut240 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+#define SR7_CLR_PRT_LUT31 ((0x5163 << 2) + 0xff000000)
+//Bit 31:28, reg_sr7_clr_prct_lut255 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 27:24, reg_sr7_clr_prct_lut254 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 23:20, reg_sr7_clr_prct_lut253 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 19:16, reg_sr7_clr_prct_lut252 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 15:12, reg_sr7_clr_prct_lut251 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 11: 8, reg_sr7_clr_prct_lut250 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 7: 4, reg_sr7_clr_prct_lut249 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+//Bit 3: 0, reg_sr7_clr_prct_lut248 : color protection lut, 16 is normalized to 1. unsigned , default = 0
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: sharp_regs2.h
+//
+
+#define SRSHARP0_SR7_DRTLPF_EN (SRSHARP0_OFFSET + SR7_DRTLPF_EN )//
+#define SRSHARP0_SR7_DRTLPF_BETA (SRSHARP0_OFFSET + SR7_DRTLPF_BETA )//
+#define SRSHARP0_SR7_PKBLD_BETA (SRSHARP0_OFFSET + SR7_PKBLD_BETA )//
+#define SRSHARP0_SR7_XLTIBLD_BETA (SRSHARP0_OFFSET + SR7_XLTIBLD_BETA )//
+#define SRSHARP0_SR7_DRTLPF_EDGE0 (SRSHARP0_OFFSET + SR7_DRTLPF_EDGE0 )//
+#define SRSHARP0_SR7_DRTLPF_EDGE1 (SRSHARP0_OFFSET + SR7_DRTLPF_EDGE1 )//
+#define SRSHARP0_SR7_DRTLPF_SDCOR0 (SRSHARP0_OFFSET + SR7_DRTLPF_SDCOR0 )//
+#define SRSHARP0_SR7_DRTLPF_SDCOR1 (SRSHARP0_OFFSET + SR7_DRTLPF_SDCOR1 )//
+#define SRSHARP0_SR7_CTIGAIN_SDCOR0 (SRSHARP0_OFFSET + SR7_CTIGAIN_SDCOR0 )//
+#define SRSHARP0_SR7_CTIGAIN_SDCOR1 (SRSHARP0_OFFSET + SR7_CTIGAIN_SDCOR1 )//
+#define SRSHARP0_SR7_LTIGAIN_SDCOR0 (SRSHARP0_OFFSET + SR7_LTIGAIN_SDCOR0 )//
+#define SRSHARP0_SR7_LTIGAIN_SDCOR1 (SRSHARP0_OFFSET + SR7_LTIGAIN_SDCOR1 )//
+#define SRSHARP0_SR7_HLTIBPF_TAP0 (SRSHARP0_OFFSET + SR7_HLTIBPF_TAP0 )//
+#define SRSHARP0_SR7_HLTIBPF_TAP1 (SRSHARP0_OFFSET + SR7_HLTIBPF_TAP1 )//
+#define SRSHARP0_SR7_HCTIBPF_TAP0 (SRSHARP0_OFFSET + SR7_HCTIBPF_TAP0 )//
+#define SRSHARP0_SR7_HCTIBPF_TAP1 (SRSHARP0_OFFSET + SR7_HCTIBPF_TAP1 )//
+#define SRSHARP0_SR7_PKLONGBPF_HTAP0 (SRSHARP0_OFFSET + SR7_PKLONGBPF_HTAP0 ) //
+#define SRSHARP0_SR7_PKLONGBPF_HTAP1 (SRSHARP0_OFFSET + SR7_PKLONGBPF_HTAP1 ) //
+#define SRSHARP0_SR7_PKLONGHPF_HTAP0 (SRSHARP0_OFFSET + SR7_PKLONGHPF_HTAP0 ) //
+#define SRSHARP0_SR7_PKLONGHPF_HTAP1 (SRSHARP0_OFFSET + SR7_PKLONGHPF_HTAP1 ) //
+#define SRSHARP0_SR7_VLTIBPF_TAP0 (SRSHARP0_OFFSET + SR7_VLTIBPF_TAP0 ) //
+#define SRSHARP0_SR7_VLTIBPF_TAP1 (SRSHARP0_OFFSET + SR7_VLTIBPF_TAP1 ) //
+#define SRSHARP0_SR7_VCTIBPF_TAP0 (SRSHARP0_OFFSET + SR7_VCTIBPF_TAP0 ) //
+#define SRSHARP0_SR7_VCTIBPF_TAP1 (SRSHARP0_OFFSET + SR7_VCTIBPF_TAP1 ) //
+#define SRSHARP0_SR7_PKLONGBPF_VTAP0 (SRSHARP0_OFFSET + SR7_PKLONGBPF_VTAP0 ) //
+#define SRSHARP0_SR7_PKLONGBPF_VTAP1 (SRSHARP0_OFFSET + SR7_PKLONGBPF_VTAP1 ) //
+#define SRSHARP0_SR7_PKLONGHPF_VTAP0 (SRSHARP0_OFFSET + SR7_PKLONGHPF_VTAP0 ) //
+#define SRSHARP0_SR7_PKLONGHPF_VTAP1 (SRSHARP0_OFFSET + SR7_PKLONGHPF_VTAP1 ) //
+#define SRSHARP0_SR7_CIRBPLONG_ALP (SRSHARP0_OFFSET + SR7_CIRBPLONG_ALP ) //
+#define SRSHARP0_SR7_CIRHPLONG_ALP (SRSHARP0_OFFSET + SR7_CIRHPLONG_ALP ) //
+#define SRSHARP0_SR7_DRTBPLONG_ALP (SRSHARP0_OFFSET + SR7_DRTBPLONG_ALP ) //
+#define SRSHARP0_SR7_DRTHPLONG_ALP (SRSHARP0_OFFSET + SR7_DRTHPLONG_ALP ) //
+#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D0 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D0) //
+#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D1 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D1) //
+#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D2 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D2) //
+#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D3 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D3) //
+#define SRSHARP0_SR7_PKMINMAXCIR_BLD_LUT2D4 (SRSHARP0_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D4) //
+#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D0 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D0) //
+#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D1 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D1) //
+#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D2 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D2) //
+#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D3 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D3) //
+#define SRSHARP0_SR7_PKMINMAXLPF_BLD_LUT2D4 (SRSHARP0_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D4) //
+#define SRSHARP0_SR7_PKDRT_BLD_EN (SRSHARP0_OFFSET + SR7_PKDRT_BLD_EN ) //
+#define SRSHARP0_SR7_DRTDIF_TH (SRSHARP0_OFFSET + SR7_DRTDIF_TH ) //
+#define SRSHARP0_SR7_TIBLD_PRT (SRSHARP0_OFFSET + SR7_TIBLD_PRT ) //
+#define SRSHARP0_SR7_HTI_OPT_FORCE (SRSHARP0_OFFSET + SR7_HTI_OPT_FORCE ) //
+#define SRSHARP0_SR7_HVTI_FINALGAIN (SRSHARP0_OFFSET + SR7_HVTI_FINALGAIN ) //
+#define SRSHARP0_SR7_TIOS_SDRATIO (SRSHARP0_OFFSET + SR7_TIOS_SDRATIO ) //
+#define SRSHARP0_SR7_XTI_SDFDEN (SRSHARP0_OFFSET + SR7_XTI_SDFDEN ) //
+#define SRSHARP0_SR7_FDSD_PARAM (SRSHARP0_OFFSET + SR7_FDSD_PARAM ) //
+#define SRSHARP0_SR7_TI_BPF_EN (SRSHARP0_OFFSET + SR7_TI_BPF_EN ) //
+#define SRSHARP0_SR7_PKLONG_PF_EN (SRSHARP0_OFFSET + SR7_PKLONG_PF_EN ) //
+#define SRSHARP0_SR7_PKLONG_PF_GAIN (SRSHARP0_OFFSET + SR7_PKLONG_PF_GAIN ) //
+#define SRSHARP0_SR7_PKMINMAX_BLD (SRSHARP0_OFFSET + SR7_PKMINMAX_BLD ) //
+#define SRSHARP0_SR7_TI_CONMAXERR_GAIN (SRSHARP0_OFFSET + SR7_TI_CONMAXERR_GAIN ) //
+#define SRSHARP0_SR7_CC_PK_ADJ (SRSHARP0_OFFSET + SR7_CC_PK_ADJ ) //
+#define SRSHARP0_SR7_CC_LUT0 (SRSHARP0_OFFSET + SR7_CC_LUT0 ) //
+#define SRSHARP0_SR7_CC_LUT1 (SRSHARP0_OFFSET + SR7_CC_LUT1 ) //
+#define SRSHARP0_SR7_CC_LUT2 (SRSHARP0_OFFSET + SR7_CC_LUT2 ) //
+#define SRSHARP0_SR7_CC_LUT3 (SRSHARP0_OFFSET + SR7_CC_LUT3 ) //
+#define SRSHARP0_SR7_CC_LUT4 (SRSHARP0_OFFSET + SR7_CC_LUT4 ) //
+#define SRSHARP0_SR7_CC_LUT5 (SRSHARP0_OFFSET + SR7_CC_LUT5 ) //
+#define SRSHARP0_SR7_GRAPHIC_CTRL (SRSHARP0_OFFSET + SR7_GRAPHIC_CTRL ) //
+#define SRSHARP0_SR7_GRAPHIC_THD_GAIN (SRSHARP0_OFFSET + SR7_GRAPHIC_THD_GAIN ) //
+#define SRSHARP0_SR7_RO_GRAPHIC_FLT_CNT (SRSHARP0_OFFSET + SR7_RO_GRAPHIC_FLT_CNT ) //
+#define SRSHARP0_SR7_RO_GRAPHIC_DTL_CNT (SRSHARP0_OFFSET + SR7_RO_GRAPHIC_DTL_CNT ) //
+#define SRSHARP0_SR7_CLR_PRT_PARAM (SRSHARP0_OFFSET + SR7_CLR_PRT_PARAM ) //
+#define SRSHARP0_SR7_CLR_PRT_LC_GAIN (SRSHARP0_OFFSET + SR7_CLR_PRT_LC_GAIN ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT0 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT0 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT1 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT1 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT2 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT2 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT3 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT3 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT4 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT4 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT5 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT5 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT6 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT6 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT7 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT7 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT8 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT8 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT9 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT9 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT10 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT10 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT11 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT11 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT12 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT12 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT13 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT13 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT14 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT14 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT15 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT15 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT16 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT16 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT17 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT17 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT18 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT18 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT19 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT19 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT20 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT20 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT21 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT21 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT22 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT22 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT23 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT23 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT24 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT24 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT25 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT25 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT26 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT26 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT27 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT27 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT28 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT28 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT29 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT29 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT30 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT30 ) //
+#define SRSHARP0_SR7_CLR_PRT_LUT31 (SRSHARP0_OFFSET + SR7_CLR_PRT_LUT31 ) //
+
+
+//// srsharp1 reg define
+#define SRSHARP1_SR7_DRTLPF_EN (SRSHARP1_OFFSET + SR7_DRTLPF_EN )//
+#define SRSHARP1_SR7_DRTLPF_BETA (SRSHARP1_OFFSET + SR7_DRTLPF_BETA )//
+#define SRSHARP1_SR7_PKBLD_BETA (SRSHARP1_OFFSET + SR7_PKBLD_BETA )//
+#define SRSHARP1_SR7_XLTIBLD_BETA (SRSHARP1_OFFSET + SR7_XLTIBLD_BETA )//
+#define SRSHARP1_SR7_DRTLPF_EDGE0 (SRSHARP1_OFFSET + SR7_DRTLPF_EDGE0 )//
+#define SRSHARP1_SR7_DRTLPF_EDGE1 (SRSHARP1_OFFSET + SR7_DRTLPF_EDGE1 )//
+#define SRSHARP1_SR7_DRTLPF_SDCOR0 (SRSHARP1_OFFSET + SR7_DRTLPF_SDCOR0 )//
+#define SRSHARP1_SR7_DRTLPF_SDCOR1 (SRSHARP1_OFFSET + SR7_DRTLPF_SDCOR1 )//
+#define SRSHARP1_SR7_CTIGAIN_SDCOR0 (SRSHARP1_OFFSET + SR7_CTIGAIN_SDCOR0 )//
+#define SRSHARP1_SR7_CTIGAIN_SDCOR1 (SRSHARP1_OFFSET + SR7_CTIGAIN_SDCOR1 )//
+#define SRSHARP1_SR7_LTIGAIN_SDCOR0 (SRSHARP1_OFFSET + SR7_LTIGAIN_SDCOR0 )//
+#define SRSHARP1_SR7_LTIGAIN_SDCOR1 (SRSHARP1_OFFSET + SR7_LTIGAIN_SDCOR1 )//
+#define SRSHARP1_SR7_HLTIBPF_TAP0 (SRSHARP1_OFFSET + SR7_HLTIBPF_TAP0 )//
+#define SRSHARP1_SR7_HLTIBPF_TAP1 (SRSHARP1_OFFSET + SR7_HLTIBPF_TAP1 )//
+#define SRSHARP1_SR7_HCTIBPF_TAP0 (SRSHARP1_OFFSET + SR7_HCTIBPF_TAP0 )//
+#define SRSHARP1_SR7_HCTIBPF_TAP1 (SRSHARP1_OFFSET + SR7_HCTIBPF_TAP1 )//
+#define SRSHARP1_SR7_PKLONGBPF_HTAP0 (SRSHARP1_OFFSET + SR7_PKLONGBPF_HTAP0 ) //
+#define SRSHARP1_SR7_PKLONGBPF_HTAP1 (SRSHARP1_OFFSET + SR7_PKLONGBPF_HTAP1 ) //
+#define SRSHARP1_SR7_PKLONGHPF_HTAP0 (SRSHARP1_OFFSET + SR7_PKLONGHPF_HTAP0 ) //
+#define SRSHARP1_SR7_PKLONGHPF_HTAP1 (SRSHARP1_OFFSET + SR7_PKLONGHPF_HTAP1 ) //
+#define SRSHARP1_SR7_VLTIBPF_TAP0 (SRSHARP1_OFFSET + SR7_VLTIBPF_TAP0 ) //
+#define SRSHARP1_SR7_VLTIBPF_TAP1 (SRSHARP1_OFFSET + SR7_VLTIBPF_TAP1 ) //
+#define SRSHARP1_SR7_VCTIBPF_TAP0 (SRSHARP1_OFFSET + SR7_VCTIBPF_TAP0 ) //
+#define SRSHARP1_SR7_VCTIBPF_TAP1 (SRSHARP1_OFFSET + SR7_VCTIBPF_TAP1 ) //
+#define SRSHARP1_SR7_PKLONGBPF_VTAP0 (SRSHARP1_OFFSET + SR7_PKLONGBPF_VTAP0 ) //
+#define SRSHARP1_SR7_PKLONGBPF_VTAP1 (SRSHARP1_OFFSET + SR7_PKLONGBPF_VTAP1 ) //
+#define SRSHARP1_SR7_PKLONGHPF_VTAP0 (SRSHARP1_OFFSET + SR7_PKLONGHPF_VTAP0 ) //
+#define SRSHARP1_SR7_PKLONGHPF_VTAP1 (SRSHARP1_OFFSET + SR7_PKLONGHPF_VTAP1 ) //
+#define SRSHARP1_SR7_CIRBPLONG_ALP (SRSHARP1_OFFSET + SR7_CIRBPLONG_ALP ) //
+#define SRSHARP1_SR7_CIRHPLONG_ALP (SRSHARP1_OFFSET + SR7_CIRHPLONG_ALP ) //
+#define SRSHARP1_SR7_DRTBPLONG_ALP (SRSHARP1_OFFSET + SR7_DRTBPLONG_ALP ) //
+#define SRSHARP1_SR7_DRTHPLONG_ALP (SRSHARP1_OFFSET + SR7_DRTHPLONG_ALP ) //
+#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D0 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D0) //
+#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D1 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D1) //
+#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D2 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D2) //
+#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D3 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D3) //
+#define SRSHARP1_SR7_PKMINMAXCIR_BLD_LUT2D4 (SRSHARP1_OFFSET + SR7_PKMINMAXCIR_BLD_LUT2D4) //
+#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D0 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D0) //
+#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D1 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D1) //
+#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D2 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D2) //
+#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D3 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D3) //
+#define SRSHARP1_SR7_PKMINMAXLPF_BLD_LUT2D4 (SRSHARP1_OFFSET + SR7_PKMINMAXLPF_BLD_LUT2D4) //
+#define SRSHARP1_SR7_PKDRT_BLD_EN (SRSHARP1_OFFSET + SR7_PKDRT_BLD_EN ) //
+#define SRSHARP1_SR7_DRTDIF_TH (SRSHARP1_OFFSET + SR7_DRTDIF_TH ) //
+#define SRSHARP1_SR7_TIBLD_PRT (SRSHARP1_OFFSET + SR7_TIBLD_PRT ) //
+#define SRSHARP1_SR7_HTI_OPT_FORCE (SRSHARP1_OFFSET + SR7_HTI_OPT_FORCE ) //
+#define SRSHARP1_SR7_HVTI_FINALGAIN (SRSHARP1_OFFSET + SR7_HVTI_FINALGAIN ) //
+#define SRSHARP1_SR7_TIOS_SDRATIO (SRSHARP1_OFFSET + SR7_TIOS_SDRATIO ) //
+#define SRSHARP1_SR7_XTI_SDFDEN (SRSHARP1_OFFSET + SR7_XTI_SDFDEN ) //
+#define SRSHARP1_SR7_FDSD_PARAM (SRSHARP1_OFFSET + SR7_FDSD_PARAM ) //
+#define SRSHARP1_SR7_TI_BPF_EN (SRSHARP1_OFFSET + SR7_TI_BPF_EN ) //
+#define SRSHARP1_SR7_PKLONG_PF_EN (SRSHARP1_OFFSET + SR7_PKLONG_PF_EN ) //
+#define SRSHARP1_SR7_PKLONG_PF_GAIN (SRSHARP1_OFFSET + SR7_PKLONG_PF_GAIN ) //
+#define SRSHARP1_SR7_PKMINMAX_BLD (SRSHARP1_OFFSET + SR7_PKMINMAX_BLD ) //
+#define SRSHARP1_SR7_TI_CONMAXERR_GAIN (SRSHARP1_OFFSET + SR7_TI_CONMAXERR_GAIN ) //
+#define SRSHARP1_SR7_CC_PK_ADJ (SRSHARP1_OFFSET + SR7_CC_PK_ADJ ) //
+#define SRSHARP1_SR7_CC_LUT0 (SRSHARP1_OFFSET + SR7_CC_LUT0 ) //
+#define SRSHARP1_SR7_CC_LUT1 (SRSHARP1_OFFSET + SR7_CC_LUT1 ) //
+#define SRSHARP1_SR7_CC_LUT2 (SRSHARP1_OFFSET + SR7_CC_LUT2 ) //
+#define SRSHARP1_SR7_CC_LUT3 (SRSHARP1_OFFSET + SR7_CC_LUT3 ) //
+#define SRSHARP1_SR7_CC_LUT4 (SRSHARP1_OFFSET + SR7_CC_LUT4 ) //
+#define SRSHARP1_SR7_CC_LUT5 (SRSHARP1_OFFSET + SR7_CC_LUT5 ) //
+#define SRSHARP1_SR7_GRAPHIC_CTRL (SRSHARP1_OFFSET + SR7_GRAPHIC_CTRL ) //
+#define SRSHARP1_SR7_GRAPHIC_THD_GAIN (SRSHARP1_OFFSET + SR7_GRAPHIC_THD_GAIN ) //
+#define SRSHARP1_SR7_RO_GRAPHIC_FLT_CNT (SRSHARP1_OFFSET + SR7_RO_GRAPHIC_FLT_CNT ) //
+#define SRSHARP1_SR7_RO_GRAPHIC_DTL_CNT (SRSHARP1_OFFSET + SR7_RO_GRAPHIC_DTL_CNT ) //
+#define SRSHARP1_SR7_CLR_PRT_PARAM (SRSHARP1_OFFSET + SR7_CLR_PRT_PARAM ) //
+#define SRSHARP1_SR7_CLR_PRT_LC_GAIN (SRSHARP1_OFFSET + SR7_CLR_PRT_LC_GAIN ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT0 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT0 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT1 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT1 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT2 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT2 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT3 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT3 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT4 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT4 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT5 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT5 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT6 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT6 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT7 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT7 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT8 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT8 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT9 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT9 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT10 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT10 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT11 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT11 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT12 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT12 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT13 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT13 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT14 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT14 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT15 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT15 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT16 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT16 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT17 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT17 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT18 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT18 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT19 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT19 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT20 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT20 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT21 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT21 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT22 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT22 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT23 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT23 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT24 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT24 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT25 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT25 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT26 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT26 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT27 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT27 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT28 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT28 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT29 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT29 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT30 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT30 ) //
+#define SRSHARP1_SR7_CLR_PRT_LUT31 (SRSHARP1_OFFSET + SR7_CLR_PRT_LUT31 ) //
+
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: srsharp_regs2.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VPPG_VCBUS_BASE = 0x52
+// -----------------------------------------------
+//===========================================================================
+// 8'h50/51/52/53 have used for srsharp_regs
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VPPH_VCBUS_BASE = 0x53
+// -----------------------------------------------
+//===========================================================================
+// 8'h50/51/52/53 have used for srsharp_regs
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: MADE_VCBUS_BASE = 0x54
+// -----------------------------------------------
+//afbcd_multx6 use 3 reg_pages
+//===========================================================================
+//
+// Reading file: afbcd_mult_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+////===============================////
+// reg addr map
+// 8'h0 - 8'h37 : rdmif
+// 8'h38 - 8'h3f : vd_top
+// 8'h40 - 8'h6f : afbcd
+// 8'h70 - 8'h7f : fgrain
+////===============================////
+//==========================================================================
+// NOR_RD_MIF
+//==========================================================================
+#define RDMIFXN_GEN_REG ((0x5400 << 2) + 0xff000000)
+//Bit 31 cntl_enable_free_clk //unsigned, RW, default = 0
+//Bit 30 reserved //unsigned, pulse cntl_sw_reset
+//Bit 29 cntl_reset_on_go_field //unsigned, RW, default = 0
+//Bit 28 cntl_urgent_chroma //unsigned, RW, default = 0
+//Bit 27 cntl_urgent_luma //unsigned, RW, default = 0
+//Bit 26 cntl_chroma_end_at_last_line //unsigned, RW, default = 0
+//Bit 25 cntl_luma_end_at_last_line //unsigned, RW, default = 0
+//Bit 24:19 cntl_hold_lines[5:0] //unsigned, RW, default = 0
+//Bit 18 cntl_last_line_mode //unsigned, RW, default = 1
+//Bit 17 ro_busy //unsigned, RO, default = 0//used as busy readback, ro ?
+//Bit 16 cntl_demux_mode //unsigned, RW, default = 0
+//Bit 15:14 cntl_bytes_per_pixel //unsigned, RW, default = 0
+//Bit 13:12 cntl_ddr_burst_size_cr //unsigned, RW, default = 0
+//Bit 11:10 cntl_ddr_burst_size_cb //unsigned, RW, default = 0
+//Bit 9:8 cntl_ddr_burst_size_y //unsigned, RW, default = 0
+//Bit 7 reserved //unsigned, pulse cntl_start_frame_man
+//Bit 6 cntl_chro_rpt_lastl //unsigned, RW, default = 0
+//Bit 5 reserved //unsigned,
+//Bit 4 cntl_little_endian //unsigned, RW, default = 0
+//Bit 3 cntl_chroma_hz_avg //unsigned, RW, default = 0
+//Bit 2 cntl_luma_hz_avg //unsigned, RW, default = 0
+//Bit 1 cntl_st_separate_en //unsigned, RW, default = 0
+//Bit 0 cntl_enable //unsigned, RW, default = 0
+#define RDMIFXN_CANVAS0 ((0x5401 << 2) + 0xff000000)
+//Bit 31 cntl_canvas0_addr_syncen //unsigned, RW, default = 0
+//Bit 30:24 reserved
+//Bit 23:16 cntl_canvas0_addr2 //unsigned, RW, default = 0
+//Bit 15:8 cntl_canvas0_addr1 //unsigned, RW, default = 0
+//Bit 7:0 cntl_canvas0_addr0 //unsigned, RW, default = 0
+#define RDMIFXN_CANVAS1 ((0x5402 << 2) + 0xff000000)
+//Bit 31 cntl_canvas1_addr_syncen //unsigned, RW, default = 0
+//Bit 30:24 reserved
+//Bit 23:16 cntl_canvas1_addr2 //unsigned, RW, default = 0
+//Bit 15:8 cntl_canvas1_addr1 //unsigned, RW, default = 0
+//Bit 7:0 cntl_canvas1_addr0 //unsigned, RW, default = 0
+#define RDMIFXN_LUMA_X0 ((0x5403 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:16 cntl_luma_x_end0 //unsigned, RW, default = 0
+//Bit 15 reserved
+//Bit 14:0 cntl_luma_x_start0 //unsigned, RW, default = 0
+#define RDMIFXN_LUMA_Y0 ((0x5404 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 cntl_luma_y_end0 //unsigned, RW, default = 0
+//Bit 15:13 reserved
+//Bit 12:0 cntl_luma_y_start0 //unsigned, RW, default = 0
+#define RDMIFXN_CHROMA_X0 ((0x5405 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:16 cntl_chroma_x_end0 //unsigned, RW, default = 0
+//Bit 15 reserved
+//Bit 14:0 cntl_chroma_x_start0 //unsigned, RW, default = 0
+#define RDMIFXN_CHROMA_Y0 ((0x5406 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 cntl_chroma_y_end0 //unsigned, RW, default = 0
+//Bit 15:13 reserved
+//Bit 12:0 cntl_chroma_y_start0 //unsigned, RW, default = 0
+#define RDMIFXN_LUMA_X1 ((0x5407 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:16 cntl_luma_x_end1 //unsigned, RW, default = 0
+//Bit 15 reserved
+//Bit 14:0 cntl_luma_x_start1 //unsigned, RW, default = 0
+#define RDMIFXN_LUMA_Y1 ((0x5408 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 cntl_luma_y_end1 //unsigned, RW, default = 0
+//Bit 15:13 reserved
+//Bit 12:0 cntl_luma_y_start1 //unsigned, RW, default = 0
+#define RDMIFXN_CHROMA_X1 ((0x5409 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:16 cntl_chroma_x_end1 //unsigned, RW, default = 0
+//Bit 15 reserved
+//Bit 14:0 cntl_chroma_x_start1 //unsigned, RW, default = 0
+#define RDMIFXN_CHROMA_Y1 ((0x540a << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 cntl_chroma_y_end1 //unsigned, RW, default = 0
+//Bit 15:13 reserved
+//Bit 12:0 cntl_chroma_y_start1 //unsigned, RW, default = 0
+#define RDMIFXN_RPT_LOOP ((0x540b << 2) + 0xff000000)
+//Bit 31:24 cntl_chroma_rpt_loop1 //unsigned, RW, default = 0
+//Bit 23:16 cntl_luma_rpt_loop1 //unsigned, RW, default = 0
+//Bit 15:8 cntl_chroma_rpt_loop0 //unsigned, RW, default = 0
+//Bit 7:0 cntl_luma_rpt_loop0 //unsigned, RW, default = 0
+#define RDMIFXN_LUMA0_RPT_PAT ((0x540c << 2) + 0xff000000)
+//Bit 31:0 cntl_luma_rpt_pat0 //unsigned, RW, default = 0
+#define RDMIFXN_CHROMA0_RPT_PAT ((0x540d << 2) + 0xff000000)
+//Bit 31:0 cntl_chroma_rpt_pat0 //unsigned, RW, default = 0
+#define RDMIFXN_LUMA1_RPT_PAT ((0x540e << 2) + 0xff000000)
+//Bit 31:0 cntl_luma_rpt_pat1 //unsigned, RW, default = 0
+#define RDMIFXN_CHROMA1_RPT_PAT ((0x540f << 2) + 0xff000000)
+//Bit 31:0 cntl_chroma_rpt_pat1 //unsigned, RW, default = 0
+#define RDMIFXN_LUMA_PSEL ((0x5410 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 cntl_luma_psel_mode //unsigned, RW, default = 0
+//Bit 25:24 cntl_luma_psel_last_line //unsigned, RW, default = 0
+//Bit 23:8 cntl_luma_psel_pat //unsigned, RW, default = 0
+//Bit 7:0 cntl_luma_psel_loop //unsigned, RW, default = 0
+#define RDMIFXN_CHROMA_PSEL ((0x5411 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:26 cntl_chroma_psel_mode //unsigned, RW, default = 0
+//Bit 25:24 cntl_chroma_psel_last_line //unsigned, RW, default = 0
+//Bit 23:8 cntl_chroma_psel_pat //unsigned, RW, default = 0
+//Bit 7:0 cntl_chroma_psel_loop //unsigned, RW, default = 0
+#define RDMIFXN_DUMMY_PIXEL ((0x5412 << 2) + 0xff000000)
+//Bit 31:0 cntl_dummy_pixel_val //unsigned, RW, default = 32'h00808000
+#define RDMIFXN_LUMA_FIFO_SIZE ((0x5413 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 cntl_luma_fifo_size //unsigned, RW, default = 128
+#define RDMIFXN_AXI_CMD_CNT ((0x5414 << 2) + 0xff000000)
+//Bit 31:0 ro_axi_cmd_cnt_sel //unsigned, RO, default = 0
+#define RDMIFXN_AXI_RDAT_CNT ((0x5415 << 2) + 0xff000000)
+//Bit 31:0 ro_axi_rdat_cnt_sel //unsigned, RO, default = 0
+#define RDMIFXN_RANGE_MAP_Y ((0x5416 << 2) + 0xff000000)
+//Bit 31:23 cntl_din_offset_y //unsigned, RW, default = 0
+//Bit 22:15 cntl_range_map_coef_y //unsigned, RW, default = 0
+//Bit 14 reserved
+//Bit 13:10 cntl_range_map_sr_y //unsigned, RW, default = 0
+//Bit 9:1 cntl_dout_offset_y //unsigned, RW, default = 0
+//Bit 0 cntl_range_map_en_y //unsigned, RW, default = 0
+#define RDMIFXN_RANGE_MAP_CB ((0x5417 << 2) + 0xff000000)
+//Bit 31:23 cntl_din_offset_cb //unsigned, RW, default = 0
+//Bit 22:15 cntl_range_map_coef_cb //unsigned, RW, default = 0
+//Bit 14 reserved
+//Bit 13:10 cntl_range_map_sr_cb //unsigned, RW, default = 0
+//Bit 9:1 cntl_dout_offset_cb //unsigned, RW, default = 0
+//Bit 0 cntl_range_map_en_cb //unsigned, RW, default = 0
+#define RDMIFXN_RANGE_MAP_CR ((0x5418 << 2) + 0xff000000)
+//Bit 31:23 cntl_din_offset_cr //unsigned, RW, default = 0
+//Bit 22:15 cntl_range_map_coef_cr //unsigned, RW, default = 0
+//Bit 14 reserved
+//Bit 13:10 cntl_range_map_sr_cr //unsigned, RW, default = 0
+//Bit 9:1 cntl_dout_offset_cr //unsigned, RW, default = 0
+//Bit 0 cntl_range_map_en_cr //unsigned, RW, default = 0
+#define RDMIFXN_GEN_REG2 ((0x5419 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29 cntl_chroma_line_read_sel //unsigned, RW, default = 0
+//Bit 28 cntl_luma_line_read_sel //unsigned, RW, default = 0
+//Bit 27:24 cntl_shift_pat_cr //unsigned, RW, default = 0
+//Bit 23:20 reserved
+//Bit 19:16 cntl_shift_pat_cb //unsigned, RW, default = 0
+//Bit 15:12 reserved
+//Bit 11:8 cntl_shift_pat_y //unsigned, RW, default = 0
+//Bit 7 reserved
+//Bit 6 cntl_hold_lines[6] //unsigned, RW, default = 0
+//Bit 5 cntl_y_rev1 //unsigned, RW, default = 0
+//Bit 4 cntl_x_rev1 //unsigned, RW, default = 0
+//Bit 3 cntl_y_rev0 //unsigned, RW, default = 0
+//Bit 2 cntl_x_rev0 //unsigned, RW, default = 0
+//Bit 1:0 cntl_color_map //unsigned, RW, default = 0
+#define RDMIFXN_PROT ((0x541a << 2) + 0xff000000)
+//Bit 31 cntl_prot_en //unsigned, RW, default = 0
+//Bit 30:29 reserved
+//Bit 28:16 cntl_prot_chroma_fifo_size //unsigned, RW, default = 0
+//Bit 15:13 reserved
+//Bit 12:0 cntl_prot_luma_fifo_size //unsigned, RW, default = 0
+#define RDMIFXN_URGENT_CTRL ((0x541b << 2) + 0xff000000)
+//Bit 31:16 cntl_urgent_ctrl_luma //unsigned, RW, default = 0
+//Bit 15:0 cntl_urgent_ctrl_chroma //unsigned, RW, default = 0
+#define RDMIFXN_GEN_REG3 ((0x541c << 2) + 0xff000000)
+//Bit 31:21 reserved
+//Bit 20 cntl_f0_stride32aligned //unsigned, RW, default = 0
+//Bit 19:18 cntl_f0_cav_blk_mode //unsigned, RW, default = 0
+//Bit 17:16 cntl_abort_mode //unsigned, RW, default = 0
+//Bit 15:12 reserved
+//Bit 11:10 cntl_dbg_mode //unsigned, RW, default = 0
+//Bit 9:8 cntl_bits_mode //unsigned, RW, default = 0
+//Bit 7 reserved
+//Bit 6:4 cntl_blk_len //unsigned, RW, default = 0
+//Bit 3 reserved
+//Bit 2:1 cntl_burst_len //unsigned, RW, default = 0
+//Bit 0 cntl_64bit_rev //unsigned, RW, default = 0
+#define RDMIFXN_CFMT_CTRL ((0x541d << 2) + 0xff000000)
+//Bit 31 cntl_cfmt_gclk_bit_dis //unsigned, RW, default = 0;
+//Bit 30 cntl_cfmt_soft_rst_bit //unsigned, RW, default = 0;
+//Bit 29 reserved
+//Bit 28 cntl_chfmt_rpt_pix //unsigned, RW, default = 0;
+//Bit 27:24 cntl_chfmt_ini_phase //unsigned, RW, default = 0;
+//Bit 23 cntl_chfmt_rpt_p0_en //unsigned, RW, default = 0;
+//Bit 22:21 cntl_chfmt_yc_ratio //unsigned, RW, default = 0;
+//Bit 20 cntl_chfmt_en //unsigned, RW, default = 0;
+//Bit 19 cntl_cvfmt_phase0_always_en //unsigned, RW, default = 0;
+//Bit 18 cntl_cvfmt_rpt_last_dis //unsigned, RW, default = 0;
+//Bit 17 cntl_cvfmt_phase0_nrpt_en //unsigned, RW, default = 0;
+//Bit 16 cntl_cvfmt_rpt_line0_en //unsigned, RW, default = 0;
+//Bit 15:12 cntl_cvfmt_skip_line_num //unsigned, RW, default = 0;
+//Bit 11:8 cntl_cvfmt_ini_phase //unsigned, RW, default = 0;
+//Bit 7:1 cntl_cvfmt_phase_step //unsigned, RW, default = 0;
+//Bit 0 cntl_cvfmt_en //unsigned, RW, default = 0;
+#define RDMIFXN_CFMT_W ((0x541e << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 cntl_chfmt_w //unsigned, RW, default = 0;
+//Bit 15:13 reserved
+//Bit 12:0 cntl_cvfmt_w //unsigned, RW, default = 0;
+#define RDMIFXN_BADDR_Y ((0x5420 << 2) + 0xff000000)
+//Bit 31:0 cntl_f0_baddr_y //unsigned, RW, default = 0
+#define RDMIFXN_BADDR_CB ((0x5421 << 2) + 0xff000000)
+//Bit 31:0 cntl_f0_baddr_cb //unsigned, RW, default = 0
+#define RDMIFXN_BADDR_CR ((0x5422 << 2) + 0xff000000)
+//Bit 31:0 cntl_f0_baddr_cr //unsigned, RW, default = 0
+#define RDMIFXN_STRIDE_0 ((0x5423 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 cntl_f0_stride_cb //unsigned, RW, default = 256
+//Bit 15:13 reserved
+//Bit 12:0 cntl_f0_stride_y //unsigned, RW, default = 256
+#define RDMIFXN_STRIDE_1 ((0x5424 << 2) + 0xff000000)
+//Bit 31:17 reserved
+//Bit 16 cntl_f0_acc_mode //unsigned, RW, default = 0
+//Bit 15:13 reserved
+//Bit 12:0 cntl_f0_stride_cr //unsigned, RW, default = 256
+#define RDMIFXN_BADDR_Y_F1 ((0x5425 << 2) + 0xff000000)
+//Bit 31:0 cntl_f1_baddr_y //unsigned, RW, default = 0
+#define RDMIFXN_BADDR_CB_F1 ((0x5426 << 2) + 0xff000000)
+//Bit 31:0 cntl_f1_baddr_cb //unsigned, RW, default = 0
+#define RDMIFXN_BADDR_CR_F1 ((0x5427 << 2) + 0xff000000)
+//Bit 31:0 cntl_f1_baddr_cr //unsigned, RW, default = 0
+#define RDMIFXN_STRIDE_0_F1 ((0x5428 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 cntl_f1_stride_cb //unsigned, RW, default = 256
+//Bit 15:13 reserved
+//Bit 12:0 cntl_f1_stride_y //unsigned, RW, default = 256
+#define RDMIFXN_STRIDE_1_F1 ((0x5429 << 2) + 0xff000000)
+//Bit 31:20 reserved
+//Bit 19 cntl_f1_stride32aligned //unsigned, RW, default = 0
+//Bit 18:17 cntl_f1_cav_blk_mode //unsigned, RW, default = 0
+//Bit 16 cntl_f1_acc_mode //unsigned, RW, default = 0
+//Bit 15:13 reserved
+//Bit 12:0 cntl_f1_stride_cr //unsigned, RW, default = 256
+//==========================================================================
+// VD_TOP
+//==========================================================================
+#define AFBCDM_VDTOP_CTRL0 ((0x5438 << 2) + 0xff000000)
+//Bit 31:22 reserved //
+//Bit 21:16 reg_afbc_gclk_ctrl // unsigned, RW, default = 0
+//Bit 15 reg_frm_start_sel // unsigned, RW, default = 0
+//Bit 14 reg_use_4kram // unsigned, RW, default = 0
+//Bit 13 reg_afbc_vd_sel // unsigned, RW, default = 0, 0:nor_rdmif 1:afbc_dec
+//Bit 12 reg_rdmif_lbuf_bypas // unsigned, RW, default = 1, 1:rdmif lbuf bypass
+//Bit 11:0 reg_rdmif_lbuf_depth // unsigned, RW, default = 512
+//==========================================================================
+// AFBC_DEC
+//==========================================================================
+#define AFBCDM_ENABLE ((0x5440 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:23 reg_gclk_ctrl_core unsigned, default = 0
+//Bit 22 reg_fmt_size_sw_mode unsigned, default = 0, 0:hw mode 1:sw mode for format size
+//Bit 21 reg_addr_link_en unsigned, default = 1, 1:enable
+//Bit 20 reg_fmt444_comb unsigned, default = 0, 0: 444 8bit uncomb
+//Bit 19 reg_dos_uncomp_mode unsigned , default = 0
+//Bit 18:16 soft_rst unsigned , default = 4
+//Bit 15:14 reserved
+//Bit 13:12 ddr_blk_size unsigned , default = 1
+//Bit 11:9 cmd_blk_size unsigend , default = 3
+//Bit 8 dec_enable unsigned , default = 0
+//Bit 7:2 reserved
+//Bit 1 head_len_sel unsigned , default = 1
+//Bit 0 reserved unsigned , pulse dec_frm_start
+#define AFBCDM_MODE ((0x5441 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29 ddr_sz_mode unsigned, default = 0 , 0: fixed block ddr size 1 : unfixed block ddr size;
+//Bit 28 blk_mem_mode unsigned, default = 0 , 0: fixed 16x128 size; 1 : fixed 12x128 size
+//Bit 27:26 rev_mode unsigned, default = 0 , reverse mode
+//Bit 25:24 mif_urgent unsigned, default = 3 , info mif and data mif urgent
+//Bit 23 reserved
+//Bit 22:16 hold_line_num unsigned, default = 0 ,
+//Bit 15:14 burst_len unsigned, default = 2, 0: burst1 1:burst2 2:burst4
+//Bit 13:8 compbits_yuv unsigned, default = 0 ,
+// bit 1:0,: y component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+// bit 3:2,: u component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+// bit 5:4,: v component bitwidth : 00-8bit 01-9bit 10-10bit 11-12bit
+//Bit 7:6 vert_skip_y unsigned, default = 0 , luma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 5:4 horz_skip_y unsigned, default = 0 , luma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 3:2 vert_skip_uv unsigned, default = 0 , chroma vert skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+//Bit 1:0 horz_skip_uv unsigned, default = 0 , chroma horz skip mode : 00-y0y1, 01-y0, 10-y1, 11-(y0+y1)/2
+#define AFBCDM_SIZE_IN ((0x5442 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 hsize_in unsigned, default = 1920 , pic horz size in unit: pixel
+//Bit 15:13 reserved
+//Bit 12:0 vsize_in unsigned, default = 1080 , pic vert size in unit: pixel
+#define AFBCDM_DEC_DEF_COLOR ((0x5443 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:20 def_color_y unsigned, default = 255, afbc dec y default setting value
+//Bit 19:10 def_color_u unsigned, default = 128, afbc dec u default setting value
+//Bit 9: 0 def_color_v unsigned, default = 128, afbc dec v default setting value
+#define AFBCDM_CONV_CTRL ((0x5444 << 2) + 0xff000000)
+//Bit 31:14 reserved
+//Bit 13:12 fmt_mode unsigned, default = 2, 0:yuv444 1:yuv422 2:yuv420
+//Bit 11: 0 conv_lbuf_len unsigned, default = 256, unit=16 pixel need to set = 2^n
+#define AFBCDM_LBUF_DEPTH ((0x5445 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 dec_lbuf_depth unsigned, default = 128; // unit= 8 pixel
+//Bit 15:12 reserved
+//Bit 11:0 mif_lbuf_depth unsigned, default = 128;
+#define AFBCDM_HEAD_BADDR ((0x5446 << 2) + 0xff000000)
+//Bit 31:0 mif_info_baddr unsigned, default = 32'h0;
+#define AFBCDM_BODY_BADDR ((0x5447 << 2) + 0xff000000)
+//Bit 31:0 mif_data_baddr unsigned, default = 32'h00010000;
+#define AFBCDM_SIZE_OUT ((0x5448 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 hsize_out unsigned, default = 1920 ; // unit: 1 pixel
+//Bit 15:13 reserved
+//Bit 12:0 vsize_out unsigned, default = 1080 ; // unit: 1 pixel
+#define AFBCDM_OUT_YSCOPE ((0x5449 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 out_vert_bgn unsigned, default = 0 ; // unit: 1 pixel
+//Bit 15:13 reserved
+//Bit 12:0 out_vert_end unsigned, default = 1079 ; // unit: 1 pixel
+#define AFBCDM_STAT ((0x544a << 2) + 0xff000000)
+//Bit 31:18 ro_dbg_axi_cnt_d8 unsigned,RO, default = 0
+//Bit 17:16 ro_dbg_axi_idel unsigned,RO, default = 0
+//Bit 15:14 reserved
+//Bit 13:8 ro_dbg_frm_cnt unsigned,RO, default = 0
+//Bit 7 :1 ro_dbg_go_line_cnt unsigned,RO, default = 0
+//Bit 0 frm_end_stat unsigned, default = 0 frame end status
+#define AFBCDM_VD_CFMT_CTRL ((0x544b << 2) + 0xff000000)
+//Bit 31 cfmt_gclk_bit_dis unsigned, default = 0 ; // it true, disable clock, otherwise enable clock
+//Bit 30 cfmt_soft_rst_bit unsigned, default = 0 ; // soft rst bit
+//Bit 29 reserved
+//Bit 28 chfmt_rpt_pix unsigned, default = 0 ; // if true, horizontal formatter use repeating to generete pixel, otherwise use bilinear interpolation
+//Bit 27:24 chfmt_ini_phase unsigned, default = 0 ; // horizontal formatter initial phase
+//Bit 23 chfmt_rpt_p0_en unsigned, default = 0 ; // horizontal formatter repeat pixel 0 enable
+//Bit 22:21 chfmt_yc_ratio unsigned, default = 0 ; // horizontal Y/C ratio, 00: 1:1, 01: 2:1, 10: 4:1
+//Bit 20 chfmt_en unsigned, default = 0 ; // horizontal formatter enable
+//Bit 19 cvfmt_phase0_always_en unsigned, default = 0 ; //if true, always use phase0 while vertical formater, meaning always //repeat data, no interpolation
+//Bit 18 cvfmt_rpt_last_dis unsigned, default = 0 ; //if true, disable vertical formatter chroma repeat last line
+//Bit 17 cvfmt_phase0_nrpt_en unsigned, default = 0 ; //veritcal formatter dont need repeat line on phase0, 1: enable, 0: disable
+//Bit 16 cvfmt_rpt_line0_en unsigned, default = 0 ; //veritcal formatter repeat line 0 enable
+//Bit 15:12 cvfmt_skip_line_num unsigned, default = 0 ; //vertical formatter skip line num at the beginning
+//Bit 11:8 cvfmt_ini_phase unsigned, default = 0 ; //vertical formatter initial phase
+//Bit 7:1 cvfmt_phase_step unsigned, default = 0 ; //vertical formatter phase step (3.4)
+//Bit 0 cvfmt_en unsigned, default = 0 ; //vertical formatter enable
+#define AFBCDM_VD_CFMT_W ((0x544c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 chfmt_w unsigned, default = 0 ;horizontal formatter width
+//Bit 15:13 reserved
+//Bit 12:0 cvfmt_w unsigned, default = 0 ;vertical formatter width
+#define AFBCDM_MIF_HOR_SCOPE ((0x544d << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 mif_blk_bgn_h unsigned, default = 0 ; // unit: 32 pixel/block hor
+//Bit 15:10 reserved
+//Bit 9: 0 mif_blk_end_h unsigned, default = 59 ; // unit: 32 pixel/block hor
+#define AFBCDM_MIF_VER_SCOPE ((0x544e << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 mif_blk_bgn_v unsigned, default = 0 ; // unit: 32 pixel/block ver
+//Bit 15:12 reserved
+//Bit 11: 0 mif_blk_end_v unsigned, default = 269; // unit: 32 pixel/block ver
+#define AFBCDM_PIXEL_HOR_SCOPE ((0x544f << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 dec_pixel_bgn_h unsigned, default = 0 ; // unit: pixel
+//Bit 15:13 reserved
+//Bit 12: 0 dec_pixel_end_h unsigned, default = 1919 ; // unit: pixel
+#define AFBCDM_PIXEL_VER_SCOPE ((0x5450 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 dec_pixel_bgn_v unsigned, default = 0 ; // unit: pixel
+//Bit 15:13 reserved
+//Bit 12: 0 dec_pixel_end_v unsigned, default = 1079 ; // unit: pixel
+#define AFBCDM_VD_CFMT_H ((0x5451 << 2) + 0xff000000)
+//Bit 31:13 reserved
+//Bit 12:0 cfmt_h unsigned, default = 142 ; //vertical formatter height
+#define AFBCDM_IQUANT_ENABLE ((0x5452 << 2) + 0xff000000)
+//Bit 31:12 reserved
+//Bit 11 reg_quant_expand_en_1 //unsigned, RW, default = 0 enable for quantization value expansion
+//Bit 10 reg_quant_expand_en_0 //unsigned, RW, default = 0 enable for quantization value expansion
+//Bit 9: 8 reg_bcleav_ofst //signed , RW, default = 0 bcleave ofset to get lower range, especially under lossy, for v1/v2, x=0 is equivalent, default = -1;
+//Bit 7: 5 reserved
+//Bit 4 reg_quant_enable_1 // unsigned , RW, default = 0 enable for quant to get some lossy
+//Bit 3: 1 reserved
+//Bit 0 reg_quant_enable_0 // unsigned , RW, default = 0 enable for quant to get some lossy
+#define AFBCDM_IQUANT_LUT_1 ((0x5453 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_0_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_0_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_0_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_0_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDM_IQUANT_LUT_2 ((0x5454 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_0_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_0_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_0_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_0_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDM_IQUANT_LUT_3 ((0x5455 << 2) + 0xff000000)
+//Bit 31 reserved
+//Bit 30:28 reg_iquant_yclut_1_11 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 27 reserved
+//Bit 26:24 reg_iquant_yclut_1_10 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 23 reserved
+//Bit 22:20 reg_iquant_yclut_1_9 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 19 reserved
+//Bit 18:16 reg_iquant_yclut_1_8 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_7 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_6 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_5 // unsigned , RW, default = 5 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_4 // unsigned , RW, default = 4 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDM_IQUANT_LUT_4 ((0x5456 << 2) + 0xff000000)
+//Bit 31:16 reserved
+//Bit 15 reserved
+//Bit 14:12 reg_iquant_yclut_1_3 // unsigned , RW, default = 3 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 11 reserved
+//Bit 10: 8 reg_iquant_yclut_1_2 // unsigned , RW, default = 2 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 7 reserved
+//Bit 6: 4 reg_iquant_yclut_1_1 // unsigned , RW, default = 1 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+//Bit 3 reserved
+//Bit 2: 0 reg_iquant_yclut_1_0 // unsigned , RW, default = 0 quantization lut for mintree leavs, iquant=2^lut(bc_leav_q+1)
+#define AFBCDM_ROT_CTRL ((0x5460 << 2) + 0xff000000)
+//Bit 31:30 reg_rot_ohds2_mode //unsigned, RW, default = 0 , rot output format down hor drop mode,0:average 1:use 0 2:use 1
+//Bit 29:28 reg_rot_ovds2_mode //unsigned, RW, default = 0 , rot output format down ver drop mode,0:average 1:use 0 2:use 1
+//Bit 27 reg_pip_mode //unsigned, RW, default = 0 , 0:dec_src from vdin/dos 1:dec_src from pip
+//Bit 26:24 reg_rot_uv_vshrk_drop_mode //unsigned, RW, default = 0 , 0:average (1/2: 1:left 2:right) (1/4: 1:[0] 2:[1] 3:[2] 4:[3], 5:left_121 6:right_121)
+//Bit 23 reserved
+//Bit 22:20 reg_rot_uv_hshrk_drop_mode //unsigned, RW, default = 0 , 0:average (1/2: 1:left 2:right) (1/4: 1:[0] 2:[1] 3:[2] 4:[3], 5:left_121 6:right_121)
+//Bit 19:18 reg_rot_uv_vshrk_ratio //unsigned, RW, default = 0 , 0:no shrink 1:1/2 shrink 2:1/4 shrink
+//Bit 17:16 reg_rot_uv_hshrk_ratio //unsigned, RW, default = 0 , 0:no shrink 1:1/2 shrink 2:1/4 shrink
+//Bit 15 reserved
+//Bit 14:12 reg_rot_y_vshrk_drop_mode //unsigned, RW, default = 0 , 0:average (1/2: 1:left 2:right) (1/4: 1:[0] 2:[1] 3:[2] 4:[3], 5:left_121 6:right_121)
+//Bit 11 reserved
+//Bit 10:8 reg_rot_y_hshrk_drop_mode //unsigned, RW, default = 0 , 0:average (1/2: 1:left 2:right) (1/4: 1:[0] 2:[1] 3:[2] 4:[3], 5:left_121 6:right_121)
+//Bit 7:6 reg_rot_y_vshrk_ratio //unsigned, RW, default = 0 , 0:no shrink 1:1/2 shrink 2:1/4 shrink
+//Bit 5:4 reg_rot_y_hshrk_ratio //unsigned, RW, default = 0 , 0:no shrink 1:1/2 shrink 2:1/4 shrink
+//Bit 3:2 reg_rot_uv422_drop_mode //unsigned, RW, default = 0 , 0:average 1:left 2:right
+//Bit 1 reg_rot_uv422_omode //unsigned, RW, default = 0 , when rot input fmt422, 0:output_uv422 1:output_uv420
+//Bit 0 reg_rot_enable //unsigned, RW, default = 0 , rotation enable
+#define AFBCDM_ROT_SCOPE ((0x5461 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:20 reg_rot_debug_probe //unsigned, RW , default = 0, y:[2:0] uv:[5:3]; 0:iblk_size 1:oblk_size 2:iblk_cnt 3:oblk_cnt 4:hsize_in 5:vsize_in 6:vstep
+//Bit 19 reg_rot_dout_ds_mode_sw //unsigned, RW , default = 0, 0:use hardware mode 1:use software mode
+//Bit 18:17 reg_rot_dout_ds_mode //unsigned, RW , default = 0, rot output fmt_down mode: [0]:h_downscale [1]:v_downscale
+//Bit 16 reg_rot_ifmt_force444 //unsigned, RW , default = 1, 1: rot input fmt force as 444
+//Bit 15:14 reg_rot_ofmt_mode //unsigned, RW , default = 0, rot output fmt mode
+//Bit 13:12 reg_rot_compbits_out_y //unsigned, RW , default = 0, rot output compbit y
+//Bit 11:10 reg_rot_compbits_out_uv //unsigned, RW , default = 0, rot output compbit uv
+//Bit 9:8 reg_rot_wrbgn_v //unsigned, RW , default = 0, rot pic vert size window begin pixel
+//Bit 7:5 reserved
+//Bit 4:0 reg_rot_wrbgn_h //unsigned, RW , default = 0, rot pic hori size window begin pixel
+#define AFBCDM_RPLC_CTRL ((0x5462 << 2) + 0xff000000)
+//Bit 31 reg_rplc_inter_corr_en //unsigned, RW , default = 0 , //pip replace inte-frame edge correct enable
+//Bit 30 reg_rplc_dummy_corr_en //unsigned, RW , default = 0 , //pip replace outsize of real-pipframe edge correct enable
+//Bit 29 reg_rplc_byps //unsigned, RW , default = 1 , //pip replace module bypass
+//Bit 28:16 reg_rplc_vsize_in //unsigned, RW , default = 1080, //
+//Bit 15:13 reserved
+//Bit 12:0 reg_rplc_hsize_in //unsigned, RW , default = 1920,
+#define AFBCDM_RPLC_PICEN ((0x5463 << 2) + 0xff000000)
+//Bit 31:28 reserved
+//Bit 27:16 reg_rplc_def_color_y //unsigned, RW , default =0 , //pip replace def_color_y
+//Bit 15:0 reg_rplc_pic_enable //unsigned, RW , default =16'hffff , //pip replace pip_picure enbale
+#define AFBCDM_RPLC_DEFCOL ((0x5464 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:12 reg_rplc_def_color_v //unsigned, RW , default =0 , //pip replace def_color_v
+//Bit 11:0 reg_rplc_def_color_u //unsigned, RW , default =0 , //pip replace def_color_u
+#define AFBCDM_RPLC_SCPXN_ADDR ((0x5465 << 2) + 0xff000000)
+//Bit 31:5 reserved
+//Bit 4:0 reg_rplc_scpxn_addr //unsigned, RW , default =0 , //pip replace scopx16 addr
+#define AFBCDM_RPLC_SCPXN_DATA ((0x5466 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:0 reg_rplc_scpxn_data //unsigned, RW , default =0 , //pip replace scopx16 data
+#define AFBCDM_ROT_RO_STAT ((0x5467 << 2) + 0xff000000)
+//Bit 31:0 ro_rot_debug //unsigned, RO , default = 0, rot some status
+//==========================================================================
+// FGRAIN
+//==========================================================================
+#define AFBCDM_FGRAIN_CTRL ((0x5470 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:24 reg_sync_ctrl // unsigned , RW, default = 0
+//Bit 23 reserved
+//Bit 22 reg_dma_st_clr // unsigned , RW, default = 0 clear DMA error status
+//Bit 21 reg_hold4dma_scale // unsigned , RW, default = 0 1 to wait DMA scale data ready before accept input data default = 0
+//Bit 20 reg_hold4dma_tbl // unsigned , RW, default = 0 1 to wait DMA grain table data ready before accept input data default = 0
+//Bit 19 reg_cin_uv_swap // unsigned , RW, default = 0 1 to swap U/V input
+//Bit 18 reg_cin_rev // unsigned , RW, default = 0 1 to reverse the U/V input order
+//Bit 17 reg_yin_rev // unsigned , RW, default = 0 1 to reverse the Y input order
+//Bit 16 reg_fgrain_ext_imode // unsigned , RW, default = 1 0 to indicate the input data is *4 in 8bit mode
+//Bit 15 reg_use_par_apply_fgrain // unsigned , RW, default = 0 1 to use apply_fgrain from DMA table
+//Bit 14 reg_fgrain_last_ln_mode // unsigned , RW, default = 0 1 to keep fgrain noise generator though the input is finished for rdmif.
+//Bit 13 reg_fgrain_use_sat4bp // unsigned , RW, default = 0 1 to use fgain_max/min for sat not {DW{1'b1}}/0
+//Bit 12 reg_apply_c_mode // unsigned , RW, default = 1 0 to following C
+//Bit 11 reg_fgrain_tbl_sign_mode // unsigned , RW, default = 1 0 to indicate signed bit is not extended in 8bit mode
+//Bit 10 reg_fgrain_tbl_ext_mode // unsigned , RW, default = 1 0 to indicate the grain table is *4 in 8bit mode
+//Bit 9: 8 reg_fmt_mode // unsigned , RW, default = 2 0:444; 1:422; 2:420; 3:reserved
+//Bit 7: 6 reg_comp_bits // unsigned , RW, default = 1 0:8bits; 1:10bits, else 12 bits
+//Bit 5: 4 reg_rev_mode // unsigned . RW, default = 0 0:h_rev; 1:v_rev;
+//Bit 3 reserved
+//Bit 2 reg_block_mode // unsigned , RW, default = 1
+//Bit 1 reg_fgrain_loc_en // unsigned , RW, default = 0 frame-based fgrain enable
+//Bit 0 reg_fgrain_glb_en // unsigned , RW, default = 0 global-based fgrain enable
+#define AFBCDM_FGRAIN_WIN_H ((0x5471 << 2) + 0xff000000)
+//Bit 31:16 reg_win_end_h .unsigned , default = 3812
+//Bit 15: 0 reg_win_bgn_h .unsigned , default = 0
+#define AFBCDM_FGRAIN_WIN_V ((0x5472 << 2) + 0xff000000)
+//Bit 31:16 reg_win_end_v .unsigned , default = 2156
+//Bit 15: 0 reg_win_bgn_v .unsigned , default = 0
+#define AFBCDM_FGRAIN_SW_Y_RANNGE ((0x5473 << 2) + 0xff000000)
+//Bit 31 reg_fgrain_sw_yrange .unsigned , default = 0
+//Bit 30:26 reserved
+//Bit 25:16 reg_fgrain_ymax .unsigned , default = 1023
+//Bit 15:10 reserved
+//Bit 9: 0 reg_fgrain_ymin .unsigned , default = 0
+#define AFBCDM_FGRAIN_SW_C_RANNGE ((0x5474 << 2) + 0xff000000)
+//Bit 31 reg_fgrain_sw_crange .unsigned , default = 0
+//Bit 30:26 reserved
+//Bit 25:16 reg_fgrain_cmax .unsigned , default = 1023
+//Bit 15:10 reserved
+//Bit 9: 0 reg_fgrain_cmin .unsigned , default = 0
+#define AFBCDM_FGRAIN_GCLK_CTRL_0 ((0x5475 << 2) + 0xff000000)
+//Bit 31:0 reg_fgrain_gclk_ctrl0 .unsigned , default = 0
+#define AFBCDM_FGRAIN_GCLK_CTRL_1 ((0x5476 << 2) + 0xff000000)
+//Bit 31:0 reg_fgrain_gclk_ctrl1 .unsigned , default = 0
+#define AFBCDM_FGRAIN_GCLK_CTRL_2 ((0x5477 << 2) + 0xff000000)
+//Bit 31:0 reg_fgrain_gclk_ctrl2 .unsigned , default = 0
+#define AFBCDM_FGRAIN_PARAM_ADDR ((0x5478 << 2) + 0xff000000)
+#define AFBCDM_FGRAIN_PARAM_DATA ((0x5479 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: afbcd_mult_regs.h
+//
+//afbcd_multx6 use 3 reg_pages
+// -----------------------------------------------
+// REG_BASE: MADF_VCBUS_BASE = 0x55
+// -----------------------------------------------
+//`include "afbcd_mult_regs.h"
+//afbcd_multx6 use 3 reg_pages
+// -----------------------------------------------
+// REG_BASE: MADG_VCBUS_BASE = 0x56
+// -----------------------------------------------
+//`include "afbcd_mult_regs.h"
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: MADH_VCBUS_BASE = 0x57
+// -----------------------------------------------
+//===========================================================================
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VPPI_VCBUS_BASE = 0x58
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: pip_alph_gen_regs.h
+//
+//
+// Reading file: vd3_pip_alph_gen_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+////===================================////
+////reg
+////===================================////
+#define VD3_PIP_ALPH_CTRL ((0x5850 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28 reg_alph_gen_dbg unsigned,default = 0 1 bit dbg_mode: output pic with alph_256 to check function
+//Bit 27:12 reg_pic_en unsigned,default = 16'h0 16bits decide which pics are enable
+//Bit 11:3 reg_alph0 unsigned,default = 0 9 bits alph0: alph value of those points which are out of the windows range
+//Bit 2:1 reg_alph_gen_mode unsigned, default = 0 2 bits out of window/border/inside of window: 0:original, 1: 0/0.5/1 alpha 2: 0/0.25/0.5/0.75/1 alph
+//Bit 0 reg_alph_gen_byps unsigned, default = 1 1 bit bypass mode
+#define VD3_PIP_ALPH_SCP_H_0 ((0x5851 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h0 unsigned,default = 0 13bits pic_0 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h0 unsigned,default = 0 13bits pic_0 window horizontal begin
+#define VD3_PIP_ALPH_SCP_H_1 ((0x5852 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h1 unsigned,default = 0 13bits pic_1 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h1 unsigned,default = 0 13bits pic_1 window horizontal begin
+#define VD3_PIP_ALPH_SCP_H_2 ((0x5853 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h2 unsigned,default = 0 13bits pic_2 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h2 unsigned,default = 0 13bits pic_2 window horizontal begin
+#define VD3_PIP_ALPH_SCP_H_3 ((0x5854 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h3 unsigned,default = 0 13bits pic_3 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h3 unsigned,default = 0 13bits pic_3 window horizontal begin
+#define VD3_PIP_ALPH_SCP_H_4 ((0x5855 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h4 unsigned,default = 0 13bits pic_4 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h4 unsigned,default = 0 13bits pic_4 window horizontal begin
+#define VD3_PIP_ALPH_SCP_H_5 ((0x5856 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h5 unsigned,default = 0 13bits pic_5 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h5 unsigned,default = 0 13bits pic_5 window horizontal begin
+#define VD3_PIP_ALPH_SCP_H_6 ((0x5857 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h6 unsigned,default = 0 13bits pic_6 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h6 unsigned,default = 0 13bits pic_6 window horizontal begin
+#define VD3_PIP_ALPH_SCP_H_7 ((0x5858 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h7 unsigned,default = 0 13bits pic_7 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h7 unsigned,default = 0 13bits pic_7 window horizontal begin
+#define VD3_PIP_ALPH_SCP_H_8 ((0x5859 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h8 unsigned,default = 0 13bits pic_8 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h8 unsigned,default = 0 13bits pic_8 window horizontal begin
+#define VD3_PIP_ALPH_SCP_H_9 ((0x585a << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h9 unsigned,default = 0 13bits pic_9 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h9 unsigned,default = 0 13bits pic_9 window horizontal begin
+#define VD3_PIP_ALPH_SCP_H_10 ((0x585b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h10 unsigned,default = 0 13bits pic_10 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h10 unsigned,default = 0 13bits pic_10 window horizontal begi
+#define VD3_PIP_ALPH_SCP_H_11 ((0x585c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h11 unsigned,default = 0 13bits pic_11 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h11 unsigned,default = 0 13bits pic_11 window horizontal begi
+#define VD3_PIP_ALPH_SCP_H_12 ((0x585d << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h12 unsigned,default = 0 13bits pic_12 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h12 unsigned,default = 0 13bits pic_12 window horizontal begi
+#define VD3_PIP_ALPH_SCP_H_13 ((0x585e << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h13 unsigned,default = 0 13bits pic_13 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h13 unsigned,default = 0 13bits pic_13 window horizontal begi
+#define VD3_PIP_ALPH_SCP_H_14 ((0x585f << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h14 unsigned,default = 0 13bits pic_14 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h14 unsigned,default = 0 13bits pic_14 window horizontal begi
+#define VD3_PIP_ALPH_SCP_H_15 ((0x5860 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h15 unsigned,default = 0 13bits pic_15 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h15 unsigned,default = 0 13bits pic_15 window horizontal begi
+#define VD3_PIP_ALPH_SCP_V_0 ((0x5861 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v0 unsigned,default = 0 13bits pic_0 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v0 unsigned,default = 0 13bits pic_0 window vertical begin
+#define VD3_PIP_ALPH_SCP_V_1 ((0x5862 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v1 unsigned,default = 0 13bits pic_1 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v1 unsigned,default = 0 13bits pic_1 window vertical begin
+#define VD3_PIP_ALPH_SCP_V_2 ((0x5863 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v2 unsigned,default = 0 13bits pic_2 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v2 unsigned,default = 0 13bits pic_2 window vertical begin
+#define VD3_PIP_ALPH_SCP_V_3 ((0x5864 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v3 unsigned,default = 0 13bits pic_3 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v3 unsigned,default = 0 13bits pic_3 window vertical begin
+#define VD3_PIP_ALPH_SCP_V_4 ((0x5865 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v4 unsigned,default = 0 13bits pic_4 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v4 unsigned,default = 0 13bits pic_4 window vertical begin
+#define VD3_PIP_ALPH_SCP_V_5 ((0x5866 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v5 unsigned,default = 0 13bits pic_5 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v5 unsigned,default = 0 13bits pic_5 window vertical begin
+#define VD3_PIP_ALPH_SCP_V_6 ((0x5867 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v6 unsigned,default = 0 13bits pic_6 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v6 unsigned,default = 0 13bits pic_6 window vertical begin
+#define VD3_PIP_ALPH_SCP_V_7 ((0x5868 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v7 unsigned,default = 0 13bits pic_7 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v7 unsigned,default = 0 13bits pic_7 window vertical begin
+#define VD3_PIP_ALPH_SCP_V_8 ((0x5869 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v8 unsigned,default = 0 13bits pic_8 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v8 unsigned,default = 0 13bits pic_8 window vertical begin
+#define VD3_PIP_ALPH_SCP_V_9 ((0x586a << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v9 unsigned,default = 0 13bits pic_9 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v9 unsigned,default = 0 13bits pic_9 window vertical begin
+#define VD3_PIP_ALPH_SCP_V_10 ((0x586b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v10 unsigned,default = 0 13bits pic_10 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v10 unsigned,default = 0 13bits pic_10 window vertical begin
+#define VD3_PIP_ALPH_SCP_V_11 ((0x586c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v11 unsigned,default = 0 13bits pic_11 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v11 unsigned,default = 0 13bits pic_11 window vertical begin
+#define VD3_PIP_ALPH_SCP_V_12 ((0x586d << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v12 unsigned,default = 0 13bits pic_12 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v12 unsigned,default = 0 13bits pic_12 window vertical begin
+#define VD3_PIP_ALPH_SCP_V_13 ((0x586e << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v13 unsigned,default = 0 13bits pic_13 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v13 unsigned,default = 0 13bits pic_13 window vertical begin
+#define VD3_PIP_ALPH_SCP_V_14 ((0x586f << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v14 unsigned,default = 0 13bits pic_14 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v14 unsigned,default = 0 13bits pic_14 window vertical begin
+#define VD3_PIP_ALPH_SCP_V_15 ((0x5870 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v15 unsigned,default = 0 13bits pic_15 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v15 unsigned,default = 0 13bits pic_15 window vertical begin
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vd3_pip_alph_gen_regs.h
+//
+//
+// Reading file: vd1_pip_alph_gen_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+////===================================////
+////reg
+////===================================////
+#define VD1_PIP_ALPH_CTRL ((0x5880 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28 reg_alph_gen_dbg unsigned,default = 0 1 bit dbg_mode: output pic with alph_256 to check function
+//Bit 27:12 reg_pic_en unsigned,default = 16'h0 16bits decide which pics are enable
+//Bit 11:3 reg_alph0 unsigned,default = 0 9 bits alph0: alph value of those points which are out of the windows range
+//Bit 2:1 reg_alph_gen_mode unsigned, default = 0 2 bits out of window/border/inside of window: 0:original, 1: 0/0.5/1 alpha 2: 0/0.25/0.5/0.75/1 alph
+//Bit 0 reg_alph_gen_byps unsigned, default = 1 1 bit bypass mode
+#define VD1_PIP_ALPH_SCP_H_0 ((0x5881 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h0 unsigned,default = 0 13bits pic_0 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h0 unsigned,default = 0 13bits pic_0 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_1 ((0x5882 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h1 unsigned,default = 0 13bits pic_1 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h1 unsigned,default = 0 13bits pic_1 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_2 ((0x5883 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h2 unsigned,default = 0 13bits pic_2 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h2 unsigned,default = 0 13bits pic_2 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_3 ((0x5884 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h3 unsigned,default = 0 13bits pic_3 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h3 unsigned,default = 0 13bits pic_3 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_4 ((0x5885 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h4 unsigned,default = 0 13bits pic_4 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h4 unsigned,default = 0 13bits pic_4 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_5 ((0x5886 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h5 unsigned,default = 0 13bits pic_5 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h5 unsigned,default = 0 13bits pic_5 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_6 ((0x5887 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h6 unsigned,default = 0 13bits pic_6 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h6 unsigned,default = 0 13bits pic_6 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_7 ((0x5888 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h7 unsigned,default = 0 13bits pic_7 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h7 unsigned,default = 0 13bits pic_7 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_8 ((0x5889 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h8 unsigned,default = 0 13bits pic_8 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h8 unsigned,default = 0 13bits pic_8 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_9 ((0x588a << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h9 unsigned,default = 0 13bits pic_9 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h9 unsigned,default = 0 13bits pic_9 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_10 ((0x588b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h10 unsigned,default = 0 13bits pic_10 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h10 unsigned,default = 0 13bits pic_10 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_11 ((0x588c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h11 unsigned,default = 0 13bits pic_11 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h11 unsigned,default = 0 13bits pic_11 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_12 ((0x588d << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h12 unsigned,default = 0 13bits pic_12 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h12 unsigned,default = 0 13bits pic_12 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_13 ((0x588e << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h13 unsigned,default = 0 13bits pic_13 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h13 unsigned,default = 0 13bits pic_13 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_14 ((0x588f << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h14 unsigned,default = 0 13bits pic_14 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h14 unsigned,default = 0 13bits pic_14 window horizontal begin
+#define VD1_PIP_ALPH_SCP_H_15 ((0x5890 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h15 unsigned,default = 0 13bits pic_15 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h15 unsigned,default = 0 13bits pic_15 window horizontal begin
+#define VD1_PIP_ALPH_SCP_V_0 ((0x5891 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v0 unsigned,default = 0 13bits pic_0 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v0 unsigned,default = 0 13bits pic_0 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_1 ((0x5892 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v1 unsigned,default = 0 13bits pic_1 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v1 unsigned,default = 0 13bits pic_1 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_2 ((0x5893 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v2 unsigned,default = 0 13bits pic_2 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v2 unsigned,default = 0 13bits pic_2 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_3 ((0x5894 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v3 unsigned,default = 0 13bits pic_3 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v3 unsigned,default = 0 13bits pic_3 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_4 ((0x5895 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v4 unsigned,default = 0 13bits pic_4 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v4 unsigned,default = 0 13bits pic_4 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_5 ((0x5896 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v5 unsigned,default = 0 13bits pic_5 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v5 unsigned,default = 0 13bits pic_5 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_6 ((0x5897 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v6 unsigned,default = 0 13bits pic_6 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v6 unsigned,default = 0 13bits pic_6 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_7 ((0x5898 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v7 unsigned,default = 0 13bits pic_7 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v7 unsigned,default = 0 13bits pic_7 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_8 ((0x5899 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v8 unsigned,default = 0 13bits pic_8 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v8 unsigned,default = 0 13bits pic_8 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_9 ((0x589a << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v9 unsigned,default = 0 13bits pic_9 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v9 unsigned,default = 0 13bits pic_9 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_10 ((0x589b << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v10 unsigned,default = 0 13bits pic_10 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v10 unsigned,default = 0 13bits pic_10 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_11 ((0x589c << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v11 unsigned,default = 0 13bits pic_11 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v11 unsigned,default = 0 13bits pic_11 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_12 ((0x589d << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v12 unsigned,default = 0 13bits pic_12 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v12 unsigned,default = 0 13bits pic_12 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_13 ((0x589e << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v13 unsigned,default = 0 13bits pic_13 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v13 unsigned,default = 0 13bits pic_13 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_14 ((0x589f << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v14 unsigned,default = 0 13bits pic_14 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v14 unsigned,default = 0 13bits pic_14 window vertical begin
+#define VD1_PIP_ALPH_SCP_V_15 ((0x58a0 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v15 unsigned,default = 0 13bits pic_15 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v15 unsigned,default = 0 13bits pic_15 window vertical begin
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vd1_pip_alph_gen_regs.h
+//
+//
+// Reading file: vd2_pip_alph_gen_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//
+////===================================////
+////reg
+////===================================////
+#define VD2_PIP_ALPH_CTRL ((0x58b0 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28 reg_alph_gen_dbg unsigned,default = 0 1 bit dbg_mode: output pic with alph_256 to check function
+//Bit 27:12 reg_pic_en unsigned,default = 16'h0 16bits decide which pics are enable
+//Bit 11:3 reg_alph0 unsigned,default = 0 9 bits alph0: alph value of those points which are out of the windows range
+//Bit 2:1 reg_alph_gen_mode unsigned, default = 0 2 bits out of window/border/inside of window: 0:original, 1: 0/0.5/1 alpha 2: 0/0.25/0.5/0.75/1 alph
+//Bit 0 reg_alph_gen_byps unsigned, default = 1 1 bit bypass mode
+#define VD2_PIP_ALPH_SCP_H_0 ((0x58b1 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h0 unsigned,default = 0 13bits pic_0 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h0 unsigned,default = 0 13bits pic_0 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_1 ((0x58b2 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h1 unsigned,default = 0 13bits pic_1 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h1 unsigned,default = 0 13bits pic_1 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_2 ((0x58b3 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h2 unsigned,default = 0 13bits pic_2 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h2 unsigned,default = 0 13bits pic_2 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_3 ((0x58b4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h3 unsigned,default = 0 13bits pic_3 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h3 unsigned,default = 0 13bits pic_3 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_4 ((0x58b5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h4 unsigned,default = 0 13bits pic_4 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h4 unsigned,default = 0 13bits pic_4 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_5 ((0x58b6 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h5 unsigned,default = 0 13bits pic_5 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h5 unsigned,default = 0 13bits pic_5 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_6 ((0x58b7 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h6 unsigned,default = 0 13bits pic_6 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h6 unsigned,default = 0 13bits pic_6 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_7 ((0x58b8 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h7 unsigned,default = 0 13bits pic_7 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h7 unsigned,default = 0 13bits pic_7 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_8 ((0x58b9 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h8 unsigned,default = 0 13bits pic_8 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h8 unsigned,default = 0 13bits pic_8 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_9 ((0x58ba << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h9 unsigned,default = 0 13bits pic_9 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h9 unsigned,default = 0 13bits pic_9 window horizontal begin
+#define VD2_PIP_ALPH_SCP_H_10 ((0x58bb << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h10 unsigned,default = 0 13bits pic_10 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h10 unsigned,default = 0 13bits pic_10 window horizontal begi
+#define VD2_PIP_ALPH_SCP_H_11 ((0x58bc << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h11 unsigned,default = 0 13bits pic_11 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h11 unsigned,default = 0 13bits pic_11 window horizontal begi
+#define VD2_PIP_ALPH_SCP_H_12 ((0x58bd << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h12 unsigned,default = 0 13bits pic_12 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h12 unsigned,default = 0 13bits pic_12 window horizontal begi
+#define VD2_PIP_ALPH_SCP_H_13 ((0x58be << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h13 unsigned,default = 0 13bits pic_13 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h13 unsigned,default = 0 13bits pic_13 window horizontal begi
+#define VD2_PIP_ALPH_SCP_H_14 ((0x58bf << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h14 unsigned,default = 0 13bits pic_14 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h14 unsigned,default = 0 13bits pic_14 window horizontal begi
+#define VD2_PIP_ALPH_SCP_H_15 ((0x58c0 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_h15 unsigned,default = 0 13bits pic_15 window horizontal end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_h15 unsigned,default = 0 13bits pic_15 window horizontal begi
+#define VD2_PIP_ALPH_SCP_V_0 ((0x58c1 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v0 unsigned,default = 0 13bits pic_0 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v0 unsigned,default = 0 13bits pic_0 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_1 ((0x58c2 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v1 unsigned,default = 0 13bits pic_1 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v1 unsigned,default = 0 13bits pic_1 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_2 ((0x58c3 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v2 unsigned,default = 0 13bits pic_2 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v2 unsigned,default = 0 13bits pic_2 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_3 ((0x58c4 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v3 unsigned,default = 0 13bits pic_3 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v3 unsigned,default = 0 13bits pic_3 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_4 ((0x58c5 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v4 unsigned,default = 0 13bits pic_4 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v4 unsigned,default = 0 13bits pic_4 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_5 ((0x58c6 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v5 unsigned,default = 0 13bits pic_5 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v5 unsigned,default = 0 13bits pic_5 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_6 ((0x58c7 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v6 unsigned,default = 0 13bits pic_6 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v6 unsigned,default = 0 13bits pic_6 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_7 ((0x58c8 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v7 unsigned,default = 0 13bits pic_7 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v7 unsigned,default = 0 13bits pic_7 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_8 ((0x58c9 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v8 unsigned,default = 0 13bits pic_8 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v8 unsigned,default = 0 13bits pic_8 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_9 ((0x58ca << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v9 unsigned,default = 0 13bits pic_9 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v9 unsigned,default = 0 13bits pic_9 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_10 ((0x58cb << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v10 unsigned,default = 0 13bits pic_10 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v10 unsigned,default = 0 13bits pic_10 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_11 ((0x58cc << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v11 unsigned,default = 0 13bits pic_11 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v11 unsigned,default = 0 13bits pic_11 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_12 ((0x58cd << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v12 unsigned,default = 0 13bits pic_12 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v12 unsigned,default = 0 13bits pic_12 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_13 ((0x58ce << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v13 unsigned,default = 0 13bits pic_13 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v13 unsigned,default = 0 13bits pic_13 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_14 ((0x58cf << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v14 unsigned,default = 0 13bits pic_14 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v14 unsigned,default = 0 13bits pic_14 window vertical begin
+#define VD2_PIP_ALPH_SCP_V_15 ((0x58d0 << 2) + 0xff000000)
+//Bit 31:29 reserved
+//Bit 28:16 reg_scpxn_end_v15 unsigned,default = 0 13bits pic_15 window vertical end
+//Bit 15:13 reserved
+//Bit 12:0 reg_scpxn_bgn_v15 unsigned,default = 0 13bits pic_15 window vertical begin
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vd2_pip_alph_gen_regs.h
+//
+//
+// Closing file: pip_alph_gen_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VPPJ_VCBUS_BASE = 0x59
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: vppj_regs.h
+//
+//0x00-0x2f
+//
+// Reading file: vpp_vd3_scale_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VD3_SCALE_COEF_IDX ((0x5903 << 2) + 0xff000000)
+#define VD3_SCALE_COEF ((0x5904 << 2) + 0xff000000)
+#define VD3_VSC_REGION12_STARTP ((0x5905 << 2) + 0xff000000)
+#define VD3_VSC_REGION34_STARTP ((0x5906 << 2) + 0xff000000)
+#define VD3_VSC_REGION4_ENDP ((0x5907 << 2) + 0xff000000)
+#define VD3_VSC_START_PHASE_STEP ((0x5908 << 2) + 0xff000000)
+#define VD3_VSC_REGION0_PHASE_SLOPE ((0x5909 << 2) + 0xff000000)
+#define VD3_VSC_REGION1_PHASE_SLOPE ((0x590a << 2) + 0xff000000)
+#define VD3_VSC_REGION3_PHASE_SLOPE ((0x590b << 2) + 0xff000000)
+#define VD3_VSC_REGION4_PHASE_SLOPE ((0x590c << 2) + 0xff000000)
+#define VD3_VSC_PHASE_CTRL ((0x590d << 2) + 0xff000000)
+#define VD3_VSC_INI_PHASE ((0x590e << 2) + 0xff000000)
+#define VD3_HSC_REGION12_STARTP ((0x590f << 2) + 0xff000000)
+#define VD3_HSC_REGION34_STARTP ((0x5910 << 2) + 0xff000000)
+#define VD3_HSC_REGION4_ENDP ((0x5911 << 2) + 0xff000000)
+#define VD3_HSC_START_PHASE_STEP ((0x5912 << 2) + 0xff000000)
+#define VD3_HSC_REGION0_PHASE_SLOPE ((0x5913 << 2) + 0xff000000)
+#define VD3_HSC_REGION1_PHASE_SLOPE ((0x5914 << 2) + 0xff000000)
+#define VD3_HSC_REGION3_PHASE_SLOPE ((0x5915 << 2) + 0xff000000)
+#define VD3_HSC_REGION4_PHASE_SLOPE ((0x5916 << 2) + 0xff000000)
+#define VD3_HSC_PHASE_CTRL ((0x5917 << 2) + 0xff000000)
+#define VD3_SC_MISC ((0x5918 << 2) + 0xff000000)
+#define VD3_SCO_FIFO_CTRL ((0x5919 << 2) + 0xff000000)
+#define VD3_HSC_PHASE_CTRL1 ((0x591a << 2) + 0xff000000)
+#define VD3_HSC_INI_PAT_CTRL ((0x591b << 2) + 0xff000000)
+#define VD3_SC_GCLK_CTRL ((0x591c << 2) + 0xff000000)
+#define VD3_PREHSC_COEF ((0x591d << 2) + 0xff000000)
+#define VD3_PRE_SCALE_CTRL ((0x591e << 2) + 0xff000000)
+#define VD3_PREVSC_COEF ((0x591f << 2) + 0xff000000)
+#define VD3_PREHSC_COEF1 ((0x5920 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp_vd3_scale_regs.h
+//
+//0x30-0x7f
+//
+// Reading file: vd3_hdr2_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//`include "hdr2_top_reg.h"
+//VD3 0x00 - -x35
+#define VD3_HDR2_CTRL ((0x5930 << 2) + 0xff000000)
+#define VD3_HDR2_CLK_GATE ((0x5931 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_COEF00_01 ((0x5932 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_COEF02_10 ((0x5933 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_COEF11_12 ((0x5934 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_COEF20_21 ((0x5935 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_COEF22 ((0x5936 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_COEF30_31 ((0x5937 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_COEF32_40 ((0x5938 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_COEF41_42 ((0x5939 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_OFFSET0_1 ((0x593a << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_OFFSET2 ((0x593b << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x593c << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_PRE_OFFSET2 ((0x593d << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_COEF00_01 ((0x593e << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_COEF02_10 ((0x593f << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_COEF11_12 ((0x5940 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_COEF20_21 ((0x5941 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_COEF22 ((0x5942 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_COEF30_31 ((0x5943 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_COEF32_40 ((0x5944 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_COEF41_42 ((0x5945 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_OFFSET0_1 ((0x5946 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_OFFSET2 ((0x5947 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x5948 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_PRE_OFFSET2 ((0x5949 << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_CLIP ((0x594a << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_CLIP ((0x594b << 2) + 0xff000000)
+#define VD3_HDR2_CGAIN_OFFT ((0x594c << 2) + 0xff000000)
+#define VD3_HDR2_HIST_RD ((0x594d << 2) + 0xff000000)
+#define VD3_EOTF_LUT_ADDR_PORT ((0x594e << 2) + 0xff000000)
+#define VD3_EOTF_LUT_DATA_PORT ((0x594f << 2) + 0xff000000)
+#define VD3_OETF_LUT_ADDR_PORT ((0x5950 << 2) + 0xff000000)
+#define VD3_OETF_LUT_DATA_PORT ((0x5951 << 2) + 0xff000000)
+#define VD3_CGAIN_LUT_ADDR_PORT ((0x5952 << 2) + 0xff000000)
+#define VD3_CGAIN_LUT_DATA_PORT ((0x5953 << 2) + 0xff000000)
+#define VD3_HDR2_CGAIN_COEF0 ((0x5954 << 2) + 0xff000000)
+#define VD3_HDR2_CGAIN_COEF1 ((0x5955 << 2) + 0xff000000)
+#define VD3_OGAIN_LUT_ADDR_PORT ((0x5956 << 2) + 0xff000000)
+#define VD3_OGAIN_LUT_DATA_PORT ((0x5957 << 2) + 0xff000000)
+#define VD3_HDR2_ADPS_CTRL ((0x5958 << 2) + 0xff000000)
+#define VD3_HDR2_ADPS_ALPHA0 ((0x5959 << 2) + 0xff000000)
+#define VD3_HDR2_ADPS_ALPHA1 ((0x595a << 2) + 0xff000000)
+#define VD3_HDR2_ADPS_BETA0 ((0x595b << 2) + 0xff000000)
+#define VD3_HDR2_ADPS_BETA1 ((0x595c << 2) + 0xff000000)
+#define VD3_HDR2_ADPS_BETA2 ((0x595d << 2) + 0xff000000)
+#define VD3_HDR2_ADPS_COEF0 ((0x595e << 2) + 0xff000000)
+#define VD3_HDR2_ADPS_COEF1 ((0x595f << 2) + 0xff000000)
+#define VD3_HDR2_GMUT_CTRL ((0x5960 << 2) + 0xff000000)
+#define VD3_HDR2_GMUT_COEF0 ((0x5961 << 2) + 0xff000000)
+#define VD3_HDR2_GMUT_COEF1 ((0x5962 << 2) + 0xff000000)
+#define VD3_HDR2_GMUT_COEF2 ((0x5963 << 2) + 0xff000000)
+#define VD3_HDR2_GMUT_COEF3 ((0x5964 << 2) + 0xff000000)
+#define VD3_HDR2_GMUT_COEF4 ((0x5965 << 2) + 0xff000000)
+#define VD3_HDR2_PIPE_CTRL1 ((0x5966 << 2) + 0xff000000)
+#define VD3_HDR2_PIPE_CTRL2 ((0x5967 << 2) + 0xff000000)
+#define VD3_HDR2_PIPE_CTRL3 ((0x5968 << 2) + 0xff000000)
+#define VD3_HDR2_PROC_WIN1 ((0x5969 << 2) + 0xff000000)
+#define VD3_HDR2_PROC_WIN2 ((0x596a << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXI_EN_CTRL ((0x596b << 2) + 0xff000000)
+#define VD3_HDR2_MATRIXO_EN_CTRL ((0x596c << 2) + 0xff000000)
+#define VD3_HDR2_HIST_CTRL ((0x596d << 2) + 0xff000000)
+#define VD3_HDR2_HIST_H_START_END ((0x596e << 2) + 0xff000000)
+#define VD3_HDR2_HIST_V_START_END ((0x596f << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vd3_hdr2_regs.h
+//
+//0x80-0xff
+//
+// Reading file: vpp1_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//ox80-0xbf
+#define VPP1_TOP_CTRL ((0x5980 << 2) + 0xff000000)
+#define VPP1_WRBAK_CTRL ((0x5981 << 2) + 0xff000000)
+#define VPP1_LFIFO_CTRL ((0x5982 << 2) + 0xff000000)
+#define VPP1_CRC_RO ((0x5983 << 2) + 0xff000000)
+#define VPP1_RO_STATUS ((0x5984 << 2) + 0xff000000)
+#define VPP1_BLD_CTRL ((0x5985 << 2) + 0xff000000)
+#define VPP1_BLD_OUT_SIZE ((0x5986 << 2) + 0xff000000)
+#define VPP1_BLD_DIN0_HSCOPE ((0x5987 << 2) + 0xff000000)
+#define VPP1_BLD_DIN0_VSCOPE ((0x5988 << 2) + 0xff000000)
+#define VPP1_BLD_DIN1_HSCOPE ((0x5989 << 2) + 0xff000000)
+#define VPP1_BLD_DIN1_VSCOPE ((0x598a << 2) + 0xff000000)
+#define VPP1_BLD_DIN2_HSCOPE ((0x598b << 2) + 0xff000000)
+#define VPP1_BLD_DIN2_VSCOPE ((0x598c << 2) + 0xff000000)
+#define VPP1_MISC ((0x598d << 2) + 0xff000000)
+#define VPP1_URGENT_CTRL ((0x598e << 2) + 0xff000000)
+#define VPP1_MATRIX_COEF00_01 ((0x5990 << 2) + 0xff000000)
+#define VPP1_MATRIX_COEF02_10 ((0x5991 << 2) + 0xff000000)
+#define VPP1_MATRIX_COEF11_12 ((0x5992 << 2) + 0xff000000)
+#define VPP1_MATRIX_COEF20_21 ((0x5993 << 2) + 0xff000000)
+#define VPP1_MATRIX_COEF22 ((0x5994 << 2) + 0xff000000)
+#define VPP1_MATRIX_COEF13_14 ((0x5995 << 2) + 0xff000000)
+#define VPP1_MATRIX_COEF23_24 ((0x5996 << 2) + 0xff000000)
+#define VPP1_MATRIX_COEF15_25 ((0x5997 << 2) + 0xff000000)
+#define VPP1_MATRIX_CLIP ((0x5998 << 2) + 0xff000000)
+#define VPP1_MATRIX_OFFSET0_1 ((0x5999 << 2) + 0xff000000)
+#define VPP1_MATRIX_OFFSET2 ((0x599a << 2) + 0xff000000)
+#define VPP1_MATRIX_PRE_OFFSET0_1 ((0x599b << 2) + 0xff000000)
+#define VPP1_MATRIX_PRE_OFFSET2 ((0x599c << 2) + 0xff000000)
+#define VPP1_MATRIX_EN_CTRL ((0x599d << 2) + 0xff000000)
+#define VPP1_GAINOFF_GCLK_CTRL ((0x59a0 << 2) + 0xff000000)
+#define VPP1_GAINOFF_CTRL0 ((0x59a1 << 2) + 0xff000000)
+#define VPP1_GAINOFF_CTRL1 ((0x59a2 << 2) + 0xff000000)
+#define VPP1_GAINOFF_CTRL2 ((0x59a3 << 2) + 0xff000000)
+#define VPP1_GAINOFF_CTRL3 ((0x59a4 << 2) + 0xff000000)
+#define VPP1_GAINOFF_CTRL4 ((0x59a5 << 2) + 0xff000000)
+#define VPP1_BLEND_CTRL ((0x59a8 << 2) + 0xff000000)
+#define VPP1_BLEND_BLEND_DUMMY_DATA ((0x59a9 << 2) + 0xff000000)
+#define VPP1_BLEND_DUMMY_ALPHA ((0x59aa << 2) + 0xff000000)
+#define VPP1_BLEND2_RO_CURRENT_XY ((0x59ab << 2) + 0xff000000)
+//oxc0-0xff
+#define VPP2_TOP_CTRL ((0x59c0 << 2) + 0xff000000)
+#define VPP2_WRBAK_CTRL ((0x59c1 << 2) + 0xff000000)
+#define VPP2_LFIFO_CTRL ((0x59c2 << 2) + 0xff000000)
+#define VPP2_CRC_RO ((0x59c3 << 2) + 0xff000000)
+#define VPP2_RO_STATUS ((0x59c4 << 2) + 0xff000000)
+#define VPP2_BLD_CTRL ((0x59c5 << 2) + 0xff000000)
+#define VPP2_BLD_OUT_SIZE ((0x59c6 << 2) + 0xff000000)
+#define VPP2_BLD_DIN0_HSCOPE ((0x59c7 << 2) + 0xff000000)
+#define VPP2_BLD_DIN0_VSCOPE ((0x59c8 << 2) + 0xff000000)
+#define VPP2_BLD_DIN1_HSCOPE ((0x59c9 << 2) + 0xff000000)
+#define VPP2_BLD_DIN1_VSCOPE ((0x59ca << 2) + 0xff000000)
+#define VPP2_BLD_DIN2_HSCOPE ((0x59cb << 2) + 0xff000000)
+#define VPP2_BLD_DIN2_VSCOPE ((0x59cc << 2) + 0xff000000)
+#define VPP2_MISC ((0x59cd << 2) + 0xff000000)
+#define VPP2_URGENT_CTRL ((0x59ce << 2) + 0xff000000)
+#define VPP2_MATRIX_COEF00_01 ((0x59d0 << 2) + 0xff000000)
+#define VPP2_MATRIX_COEF02_10 ((0x59d1 << 2) + 0xff000000)
+#define VPP2_MATRIX_COEF11_12 ((0x59d2 << 2) + 0xff000000)
+#define VPP2_MATRIX_COEF20_21 ((0x59d3 << 2) + 0xff000000)
+#define VPP2_MATRIX_COEF22 ((0x59d4 << 2) + 0xff000000)
+#define VPP2_MATRIX_COEF13_14 ((0x59d5 << 2) + 0xff000000)
+#define VPP2_MATRIX_COEF23_24 ((0x59d6 << 2) + 0xff000000)
+#define VPP2_MATRIX_COEF15_25 ((0x59d7 << 2) + 0xff000000)
+#define VPP2_MATRIX_CLIP ((0x59d8 << 2) + 0xff000000)
+#define VPP2_MATRIX_OFFSET0_1 ((0x59d9 << 2) + 0xff000000)
+#define VPP2_MATRIX_OFFSET2 ((0x59da << 2) + 0xff000000)
+#define VPP2_MATRIX_PRE_OFFSET0_1 ((0x59db << 2) + 0xff000000)
+#define VPP2_MATRIX_PRE_OFFSET2 ((0x59dc << 2) + 0xff000000)
+#define VPP2_MATRIX_EN_CTRL ((0x59dd << 2) + 0xff000000)
+#define VPP2_GAINOFF_GCLK_CTRL ((0x59e0 << 2) + 0xff000000)
+#define VPP2_GAINOFF_CTRL0 ((0x59e1 << 2) + 0xff000000)
+#define VPP2_GAINOFF_CTRL1 ((0x59e2 << 2) + 0xff000000)
+#define VPP2_GAINOFF_CTRL2 ((0x59e3 << 2) + 0xff000000)
+#define VPP2_GAINOFF_CTRL3 ((0x59e4 << 2) + 0xff000000)
+#define VPP2_GAINOFF_CTRL4 ((0x59e5 << 2) + 0xff000000)
+#define VPP2_BLEND_CTRL ((0x59e8 << 2) + 0xff000000)
+#define VPP2_BLEND_BLEND_DUMMY_DATA ((0x59e9 << 2) + 0xff000000)
+#define VPP2_BLEND_DUMMY_ALPHA ((0x59ea << 2) + 0xff000000)
+#define VPP2_BLEND2_RO_CURRENT_XY ((0x59eb << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpp1_regs.h
+//
+//
+// Closing file: vppj_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VPPK_VCBUS_BASE = 0x5a
+// -----------------------------------------------
+//osd_scale
+//===========================================================================
+//
+// Reading file: vppk_regs.h
+//
+//0x00-0x3f
+//
+// Reading file: vpu_osd1_scale.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define VPP_OSD_VSC_PHASE_STEP ((0x5a00 << 2) + 0xff000000)
+//vertical scaler phase step
+//Bit 27:0, 4.24 format
+#define VPP_OSD_VSC_INI_PHASE ((0x5a01 << 2) + 0xff000000)
+//Bit 31:16, botttom vertical scaler initial phase
+//Bit 15:0, top vertical scaler initial phase
+#define VPP_OSD_VSC_CTRL0 ((0x5a02 << 2) + 0xff000000)
+//Bit 24 osd vertical Scaler enable
+//Bit 23 osd_prog_interlace 0: current field is progressive, 1: current field is interlace
+//Bit 22:21 osd_vsc_double_line_mode, bit1, double input width and half input height, bit0, change line buffer becomes 2 lines
+//Bit 20 osd_vsc_phase0_always_en
+//Bit 19 osd_vsc_nearest_en
+//Bit 17:16 osd_vsc_bot_rpt_l0_num
+//Bit 14:11 osd_vsc_bot_ini_rcv_num
+//Bit 9:8 osd_vsc_top_rpt_l0_num
+//Bit 6:3 osd_vsc_top_ini_rcv_num
+//Bit 2:0 osd_vsc_bank_length
+#define VPP_OSD_HSC_PHASE_STEP ((0x5a03 << 2) + 0xff000000)
+//horizontal scaler phase step
+//Bit 27:0, 4.24 format
+#define VPP_OSD_HSC_INI_PHASE ((0x5a04 << 2) + 0xff000000)
+//Bit 31:16, horizontal scaler initial phase1
+//Bit 15:0, horizontal scaler initial phase0
+#define VPP_OSD_HSC_CTRL0 ((0x5a05 << 2) + 0xff000000)
+//Bit 22 osd horizontal scaler enable
+//Bit 21 osd_hsc_double_pix_mode
+//Bit 20 osd_hsc_phase0_always_en
+//Bit 19 osd_hsc_nearest_en
+//Bit 17:16 osd_hsc_rpt_p0_num1
+//Bit 14:11 osd_hsc_ini_rcv_num1
+//Bit 9:8 osd_hsc_rpt_p0_num0
+//Bit 6:3 osd_hsc_ini_rcv_num0
+//Bit 2:0 osd_hsc_bank_length
+#define VPP_OSD_HSC_INI_PAT_CTRL ((0x5a06 << 2) + 0xff000000)
+//for 3D quincunx sub-sampling
+//bit 15:8 pattern, each patten 1 bit, from lsb -> msb
+//bit 6:4 pattern start
+//bit 2:0 pattern end
+#define VPP_OSD_SC_DUMMY_DATA ((0x5a07 << 2) + 0xff000000)
+//bit 31:24, componet 0
+//bit 23:16, component 1
+//bit 15:8, component 2
+//bit 7:0 component 3, alpha
+#define VPP_OSD_SC_CTRL0 ((0x5a08 << 2) + 0xff000000)
+//Bit 14 osc_sc_din_osd1_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 13 osc_sc_din_osd2_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 12 osc_sc_dout_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 12 osc_sc_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 11:4 default alpha for vd1 or vd2 if they are selected as the source
+//Bit 3 osd scaler path enable
+//Bit 1:0 osd_sc_sel, 00: select osd1 input, 01: select osd2 input, 10: select vd1 input, 11: select vd2 input after matrix
+#define VPP_OSD_SCI_WH_M1 ((0x5a09 << 2) + 0xff000000)
+//Bit 28:16 OSD scaler input width minus 1
+//Bit 12:0 OSD scaler input height minus 1
+#define VPP_OSD_SCO_H_START_END ((0x5a0a << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output horizontal start
+//Bit 12:0 OSD scaler output horizontal end
+#define VPP_OSD_SCO_V_START_END ((0x5a0b << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output vertical start
+//Bit 12:0 OSD scaler output vertical end
+#define VPP_OSD_SCALE_COEF_IDX ((0x5a0c << 2) + 0xff000000)
+//Because there are many coefficients used in the vertical filter and horizontal filters,
+//indirect access the coefficients of vertical filter and horizontal filter is used.
+//For vertical filter, there are 33x4 coefficients
+//For horizontal filter, there are 33x4 coefficients
+//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
+//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
+//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
+//Bit 8 type of index, 0: vertical coef, 1: horizontal coef
+//Bit 6:0 coef index
+#define VPP_OSD_SCALE_COEF ((0x5a0d << 2) + 0xff000000)
+//coefficients for vertical filter and horizontal filter
+ // synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_osd1_scale.h
+//
+//
+// Reading file: osdsc_deband_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define OSD_DB_FLT_CTRL ((0x5a20 << 2) + 0xff000000)
+//Bit 31:27 reserved
+//Bit 26 reg_nrdeband_reset1 // unsigned , default = 1 , 0 : no reload chrm seed 1: reload chrm seed
+//Bit 25 reg_nrdeband_reset0 // unsigned , default = 1 , 0 : no reload luma seed 1: reload luma seed
+//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 , 0 : yuv 1: RGB
+//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
+//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
+//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
+//Bit 16 reserved
+//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
+//Bit 12 reserved
+//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6
+//Bit 8 reserved
+//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 , debanding random hp portion xor, [0] for luma
+//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 , debanding random hp portion xor, [1] for chroma
+//Bit 5 reg_nrdeband_en1 // unsigned , default = 0 , debanding registers, for luma
+//Bit 4 reg_nrdeband_en0 // unsigned , default = 0 , debanding registers, for chroma
+//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+#define OSD_DB_FLT_CTRL1 ((0x5a21 << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:16 reg_nrdeband_noise_rs // unsigned , default = 2
+//Bit 15:12 reg_nrdeband_randgain // unsigned , default = 8
+//Bit 11 reserved
+//Bit 10: 8 reg_nrdeband_bandrand5 // unsigned , default = 6
+//Bit 7 reserved
+//Bit 6: 4 reg_nrdeband_bandrand4 // unsigned , default = 6
+//Bit 3 reserved
+//Bit 2: 0 reg_nrdeband_bandrand3 // unsigned , default = 6
+#define OSD_DB_FLT_LUMA_THRD ((0x5a22 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_luma_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_luma_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_luma_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_luma_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else
+#define OSD_DB_FLT_CHRM_THRD ((0x5a23 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_chrm_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_chrm_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_chrm_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_chrm_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif
+#define OSD_DB_FLT_RANDLUT ((0x5a24 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:21 reg_nrdeband_randslut7 // unsigned , default = 1 rand lut7
+//Bit 20:18 reg_nrdeband_randslut6 // unsigned , default = 1 rand lut6
+//Bit 17:15 reg_nrdeband_randslut5 // unsigned , default = 1 rand lut5
+//Bit 14:12 reg_nrdeband_randslut4 // unsigned , default = 1 rand lut4
+//Bit 11: 9 reg_nrdeband_randslut3 // unsigned , default = 1 rand lut3
+//Bit 8: 6 reg_nrdeband_randslut2 // unsigned , default = 1 rand lut2
+//Bit 5: 3 reg_nrdeband_randslut1 // unsigned , default = 1 rand lut1
+//Bit 2: 0 reg_nrdeband_randslut0 // unsigned , default = 1 rand lut0
+#define OSD_DB_FLT_PXI_THRD ((0x5a25 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+//Bit 15:10 reserved
+//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+#define OSD_DB_FLT_SEED_Y ((0x5a26 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 ,debanding noise adding seed for Y. seed[0]= 0x60a52f20; as default
+#define OSD_DB_FLT_SEED_U ((0x5a27 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 ,debanding noise adding seed for U. seed[0]= 0x60a52f27; as default
+#define OSD_DB_FLT_SEED_V ((0x5a28 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD_DB_FLT_SEED3 ((0x5a29 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed3 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD_DB_FLT_SEED4 ((0x5a2a << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed4 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD_DB_FLT_SEED5 ((0x5a2b << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed5 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: osdsc_deband_regs.h
+//
+//0x40-0x7f
+//
+// Reading file: vpu_osd2_scale.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define OSD2_VSC_PHASE_STEP ((0x5a40 << 2) + 0xff000000)
+//vertical scaler phase step
+//Bit 27:0, 4.24 format
+#define OSD2_VSC_INI_PHASE ((0x5a41 << 2) + 0xff000000)
+//Bit 31:16, botttom vertical scaler initial phase
+//Bit 15:0, top vertical scaler initial phase
+#define OSD2_VSC_CTRL0 ((0x5a42 << 2) + 0xff000000)
+//Bit 24 osd vertical Scaler enable
+//Bit 23 osd_prog_interlace 0: current field is progressive, 1: current field is interlace
+//Bit 22:21 osd_vsc_double_line_mode, bit1, double input width and half input height, bit0, change line buffer becomes 2 lines
+//Bit 20 osd_vsc_phase0_always_en
+//Bit 19 osd_vsc_nearest_en
+//Bit 17:16 osd_vsc_bot_rpt_l0_num
+//Bit 14:11 osd_vsc_bot_ini_rcv_num
+//Bit 9:8 osd_vsc_top_rpt_l0_num
+//Bit 6:3 osd_vsc_top_ini_rcv_num
+//Bit 2:0 osd_vsc_bank_length
+#define OSD2_HSC_PHASE_STEP ((0x5a43 << 2) + 0xff000000)
+//horizontal scaler phase step
+//Bit 27:0, 4.24 format
+#define OSD2_HSC_INI_PHASE ((0x5a44 << 2) + 0xff000000)
+//Bit 31:16, horizontal scaler initial phase1
+//Bit 15:0, horizontal scaler initial phase0
+#define OSD2_HSC_CTRL0 ((0x5a45 << 2) + 0xff000000)
+//Bit 22 osd horizontal scaler enable
+//Bit 21 osd_hsc_double_pix_mode
+//Bit 20 osd_hsc_phase0_always_en
+//Bit 19 osd_hsc_nearest_en
+//Bit 17:16 osd_hsc_rpt_p0_num1
+//Bit 14:11 osd_hsc_ini_rcv_num1
+//Bit 9:8 osd_hsc_rpt_p0_num0
+//Bit 6:3 osd_hsc_ini_rcv_num0
+//Bit 2:0 osd_hsc_bank_length
+#define OSD2_HSC_INI_PAT_CTRL ((0x5a46 << 2) + 0xff000000)
+//for 3D quincunx sub-sampling
+//bit 15:8 pattern, each patten 1 bit, from lsb -> msb
+//bit 6:4 pattern start
+//bit 2:0 pattern end
+#define OSD2_SC_DUMMY_DATA ((0x5a47 << 2) + 0xff000000)
+//bit 31:24, componet 0
+//bit 23:16, component 1
+//bit 15:8, component 2
+//bit 7:0 component 3, alpha
+#define OSD2_SC_CTRL0 ((0x5a48 << 2) + 0xff000000)
+//Bit 14 osc_sc_din_osd1_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 13 osc_sc_din_osd2_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 12 osc_sc_dout_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 12 osc_sc_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 11:4 default alpha for vd1 or vd2 if they are selected as the source
+//Bit 3 osd scaler path enable
+//Bit 1:0 osd_sc_sel, 00: select osd1 input, 01: select osd2 input, 10: select vd1 input, 11: select vd2 input after matrix
+#define OSD2_SCI_WH_M1 ((0x5a49 << 2) + 0xff000000)
+//Bit 28:16 OSD scaler input width minus 1
+//Bit 12:0 OSD scaler input height minus 1
+#define OSD2_SCO_H_START_END ((0x5a4a << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output horizontal start
+//Bit 12:0 OSD scaler output horizontal end
+#define OSD2_SCO_V_START_END ((0x5a4b << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output vertical start
+//Bit 12:0 OSD scaler output vertical end
+#define OSD2_SCALE_COEF_IDX ((0x5a4c << 2) + 0xff000000)
+//Because there are many coefficients used in the vertical filter and horizontal filters,
+//indirect access the coefficients of vertical filter and horizontal filter is used.
+//For vertical filter, there are 33x4 coefficients
+//For horizontal filter, there are 33x4 coefficients
+//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
+//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
+//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
+//Bit 8 type of index, 0: vertical coef, 1: horizontal coef
+//Bit 6:0 coef index
+#define OSD2_SCALE_COEF ((0x5a4d << 2) + 0xff000000)
+//coefficients for vertical filter and horizontal filter
+ // synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_osd2_scale.h
+//
+//
+// Reading file: vpu_osd2_deband_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define OSD2_DB_FLT_CTRL ((0x5a60 << 2) + 0xff000000)
+//Bit 31:27 reserved
+//Bit 26 reg_nrdeband_reset1 // unsigned , default = 1 , 0 : no reload chrm seed 1: reload chrm seed
+//Bit 25 reg_nrdeband_reset0 // unsigned , default = 1 , 0 : no reload luma seed 1: reload luma seed
+//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 , 0 : yuv 1: RGB
+//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
+//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
+//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
+//Bit 16 reserved
+//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
+//Bit 12 reserved
+//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6
+//Bit 8 reserved
+//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 , debanding random hp portion xor, [0] for luma
+//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 , debanding random hp portion xor, [1] for chroma
+//Bit 5 reg_nrdeband_en1 // unsigned , default = 0 , debanding registers, for luma
+//Bit 4 reg_nrdeband_en0 // unsigned , default = 0 , debanding registers, for chroma
+//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+#define OSD2_DB_FLT_CTRL1 ((0x5a61 << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:16 reg_nrdeband_noise_rs // unsigned , default = 2
+//Bit 15:12 reg_nrdeband_randgain // unsigned , default = 8
+//Bit 11 reserved
+//Bit 10: 8 reg_nrdeband_bandrand5 // unsigned , default = 6
+//Bit 7 reserved
+//Bit 6: 4 reg_nrdeband_bandrand4 // unsigned , default = 6
+//Bit 3 reserved
+//Bit 2: 0 reg_nrdeband_bandrand3 // unsigned , default = 6
+#define OSD2_DB_FLT_LUMA_THRD ((0x5a62 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_luma_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_luma_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_luma_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_luma_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else
+#define OSD2_DB_FLT_CHRM_THRD ((0x5a63 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_chrm_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_chrm_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_chrm_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_chrm_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif
+#define OSD2_DB_FLT_RANDLUT ((0x5a64 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:21 reg_nrdeband_randslut7 // unsigned , default = 1 rand lut7
+//Bit 20:18 reg_nrdeband_randslut6 // unsigned , default = 1 rand lut6
+//Bit 17:15 reg_nrdeband_randslut5 // unsigned , default = 1 rand lut5
+//Bit 14:12 reg_nrdeband_randslut4 // unsigned , default = 1 rand lut4
+//Bit 11: 9 reg_nrdeband_randslut3 // unsigned , default = 1 rand lut3
+//Bit 8: 6 reg_nrdeband_randslut2 // unsigned , default = 1 rand lut2
+//Bit 5: 3 reg_nrdeband_randslut1 // unsigned , default = 1 rand lut1
+//Bit 2: 0 reg_nrdeband_randslut0 // unsigned , default = 1 rand lut0
+#define OSD2_DB_FLT_PXI_THRD ((0x5a65 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+//Bit 15:10 reserved
+//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+#define OSD2_DB_FLT_SEED_Y ((0x5a66 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 ,debanding noise adding seed for Y. seed[0]= 0x60a52f20; as default
+#define OSD2_DB_FLT_SEED_U ((0x5a67 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 ,debanding noise adding seed for U. seed[0]= 0x60a52f27; as default
+#define OSD2_DB_FLT_SEED_V ((0x5a68 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD2_DB_FLT_SEED3 ((0x5a69 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed3 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD2_DB_FLT_SEED4 ((0x5a6a << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed4 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD2_DB_FLT_SEED5 ((0x5a6b << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed5 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_osd2_deband_regs.h
+//
+//0x80-0xbf
+//
+// Reading file: vpu_osd3_scale.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define OSD34_VSC_PHASE_STEP ((0x5a80 << 2) + 0xff000000)
+//vertical scaler phase step
+//Bit 27:0, 4.24 format
+#define OSD34_VSC_INI_PHASE ((0x5a81 << 2) + 0xff000000)
+//Bit 31:16, botttom vertical scaler initial phase
+//Bit 15:0, top vertical scaler initial phase
+#define OSD34_VSC_CTRL0 ((0x5a82 << 2) + 0xff000000)
+//Bit 24 osd vertical Scaler enable
+//Bit 23 osd_prog_interlace 0: current field is progressive, 1: current field is interlace
+//Bit 22:21 osd_vsc_double_line_mode, bit1, double input width and half input height, bit0, change line buffer becomes 2 lines
+//Bit 20 osd_vsc_phase0_always_en
+//Bit 19 osd_vsc_nearest_en
+//Bit 17:16 osd_vsc_bot_rpt_l0_num
+//Bit 14:11 osd_vsc_bot_ini_rcv_num
+//Bit 9:8 osd_vsc_top_rpt_l0_num
+//Bit 6:3 osd_vsc_top_ini_rcv_num
+//Bit 2:0 osd_vsc_bank_length
+#define OSD34_HSC_PHASE_STEP ((0x5a83 << 2) + 0xff000000)
+//horizontal scaler phase step
+//Bit 27:0, 4.24 format
+#define OSD34_HSC_INI_PHASE ((0x5a84 << 2) + 0xff000000)
+//Bit 31:16, horizontal scaler initial phase1
+//Bit 15:0, horizontal scaler initial phase0
+#define OSD34_HSC_CTRL0 ((0x5a85 << 2) + 0xff000000)
+//Bit 22 osd horizontal scaler enable
+//Bit 21 osd_hsc_double_pix_mode
+//Bit 20 osd_hsc_phase0_always_en
+//Bit 19 osd_hsc_nearest_en
+//Bit 17:16 osd_hsc_rpt_p0_num1
+//Bit 14:11 osd_hsc_ini_rcv_num1
+//Bit 9:8 osd_hsc_rpt_p0_num0
+//Bit 6:3 osd_hsc_ini_rcv_num0
+//Bit 2:0 osd_hsc_bank_length
+#define OSD34_HSC_INI_PAT_CTRL ((0x5a86 << 2) + 0xff000000)
+//for 3D quincunx sub-sampling
+//bit 15:8 pattern, each patten 1 bit, from lsb -> msb
+//bit 6:4 pattern start
+//bit 2:0 pattern end
+#define OSD34_SC_DUMMY_DATA ((0x5a87 << 2) + 0xff000000)
+//bit 31:24, componet 0
+//bit 23:16, component 1
+//bit 15:8, component 2
+//bit 7:0 component 3, alpha
+#define OSD34_SC_CTRL0 ((0x5a88 << 2) + 0xff000000)
+//Bit 14 osc_sc_din_osd1_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 13 osc_sc_din_osd2_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 12 osc_sc_dout_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 12 osc_sc_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 11:4 default alpha for vd1 or vd2 if they are selected as the source
+//Bit 3 osd scaler path enable
+//Bit 1:0 osd_sc_sel, 00: select osd1 input, 01: select osd2 input, 10: select vd1 input, 11: select vd2 input after matrix
+#define OSD34_SCI_WH_M1 ((0x5a89 << 2) + 0xff000000)
+//Bit 28:16 OSD scaler input width minus 1
+//Bit 12:0 OSD scaler input height minus 1
+#define OSD34_SCO_H_START_END ((0x5a8a << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output horizontal start
+//Bit 12:0 OSD scaler output horizontal end
+#define OSD34_SCO_V_START_END ((0x5a8b << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output vertical start
+//Bit 12:0 OSD scaler output vertical end
+#define OSD34_SCALE_COEF_IDX ((0x5a8c << 2) + 0xff000000)
+//Because there are many coefficients used in the vertical filter and horizontal filters,
+//indirect access the coefficients of vertical filter and horizontal filter is used.
+//For vertical filter, there are 33x4 coefficients
+//For horizontal filter, there are 33x4 coefficients
+//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
+//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
+//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
+//Bit 8 type of index, 0: vertical coef, 1: horizontal coef
+//Bit 6:0 coef index
+#define OSD34_SCALE_COEF ((0x5a8d << 2) + 0xff000000)
+//coefficients for vertical filter and horizontal filter
+ // synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_osd3_scale.h
+//
+//
+// Reading file: vpu_osd3_deband_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define OSD34_DB_FLT_CTRL ((0x5aa0 << 2) + 0xff000000)
+//Bit 31:27 reserved
+//Bit 26 reg_nrdeband_reset1 // unsigned , default = 1 , 0 : no reload chrm seed 1: reload chrm seed
+//Bit 25 reg_nrdeband_reset0 // unsigned , default = 1 , 0 : no reload luma seed 1: reload luma seed
+//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 , 0 : yuv 1: RGB
+//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
+//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
+//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
+//Bit 16 reserved
+//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
+//Bit 12 reserved
+//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6
+//Bit 8 reserved
+//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 , debanding random hp portion xor, [0] for luma
+//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 , debanding random hp portion xor, [1] for chroma
+//Bit 5 reg_nrdeband_en1 // unsigned , default = 0 , debanding registers, for luma
+//Bit 4 reg_nrdeband_en0 // unsigned , default = 0 , debanding registers, for chroma
+//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+#define OSD34_DB_FLT_CTRL1 ((0x5aa1 << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:16 reg_nrdeband_noise_rs // unsigned , default = 2
+//Bit 15:12 reg_nrdeband_randgain // unsigned , default = 8
+//Bit 11 reserved
+//Bit 10: 8 reg_nrdeband_bandrand5 // unsigned , default = 6
+//Bit 7 reserved
+//Bit 6: 4 reg_nrdeband_bandrand4 // unsigned , default = 6
+//Bit 3 reserved
+//Bit 2: 0 reg_nrdeband_bandrand3 // unsigned , default = 6
+#define OSD34_DB_FLT_LUMA_THRD ((0x5aa2 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_luma_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_luma_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_luma_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_luma_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else
+#define OSD34_DB_FLT_CHRM_THRD ((0x5aa3 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_chrm_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_chrm_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_chrm_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_chrm_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif
+#define OSD34_DB_FLT_RANDLUT ((0x5aa4 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:21 reg_nrdeband_randslut7 // unsigned , default = 1 rand lut7
+//Bit 20:18 reg_nrdeband_randslut6 // unsigned , default = 1 rand lut6
+//Bit 17:15 reg_nrdeband_randslut5 // unsigned , default = 1 rand lut5
+//Bit 14:12 reg_nrdeband_randslut4 // unsigned , default = 1 rand lut4
+//Bit 11: 9 reg_nrdeband_randslut3 // unsigned , default = 1 rand lut3
+//Bit 8: 6 reg_nrdeband_randslut2 // unsigned , default = 1 rand lut2
+//Bit 5: 3 reg_nrdeband_randslut1 // unsigned , default = 1 rand lut1
+//Bit 2: 0 reg_nrdeband_randslut0 // unsigned , default = 1 rand lut0
+#define OSD34_DB_FLT_PXI_THRD ((0x5aa5 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+//Bit 15:10 reserved
+//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+#define OSD34_DB_FLT_SEED_Y ((0x5aa6 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 ,debanding noise adding seed for Y. seed[0]= 0x60a52f20; as default
+#define OSD34_DB_FLT_SEED_U ((0x5aa7 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 ,debanding noise adding seed for U. seed[0]= 0x60a52f27; as default
+#define OSD34_DB_FLT_SEED_V ((0x5aa8 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD34_DB_FLT_SEED3 ((0x5aa9 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed3 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD34_DB_FLT_SEED4 ((0x5aaa << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed4 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD34_DB_FLT_SEED5 ((0x5aab << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed5 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_osd3_deband_regs.h
+//
+//0xc0-0xff
+//
+// Reading file: vpu_osd4_scale.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define OSD4_VSC_PHASE_STEP ((0x5ac0 << 2) + 0xff000000)
+//vertical scaler phase step
+//Bit 27:0, 4.24 format
+#define OSD4_VSC_INI_PHASE ((0x5ac1 << 2) + 0xff000000)
+//Bit 31:16, botttom vertical scaler initial phase
+//Bit 15:0, top vertical scaler initial phase
+#define OSD4_VSC_CTRL0 ((0x5ac2 << 2) + 0xff000000)
+//Bit 24 osd vertical Scaler enable
+//Bit 23 osd_prog_interlace 0: current field is progressive, 1: current field is interlace
+//Bit 22:21 osd_vsc_double_line_mode, bit1, double input width and half input height, bit0, change line buffer becomes 2 lines
+//Bit 20 osd_vsc_phase0_always_en
+//Bit 19 osd_vsc_nearest_en
+//Bit 17:16 osd_vsc_bot_rpt_l0_num
+//Bit 14:11 osd_vsc_bot_ini_rcv_num
+//Bit 9:8 osd_vsc_top_rpt_l0_num
+//Bit 6:3 osd_vsc_top_ini_rcv_num
+//Bit 2:0 osd_vsc_bank_length
+#define OSD4_HSC_PHASE_STEP ((0x5ac3 << 2) + 0xff000000)
+//horizontal scaler phase step
+//Bit 27:0, 4.24 format
+#define OSD4_HSC_INI_PHASE ((0x5ac4 << 2) + 0xff000000)
+//Bit 31:16, horizontal scaler initial phase1
+//Bit 15:0, horizontal scaler initial phase0
+#define OSD4_HSC_CTRL0 ((0x5ac5 << 2) + 0xff000000)
+//Bit 22 osd horizontal scaler enable
+//Bit 21 osd_hsc_double_pix_mode
+//Bit 20 osd_hsc_phase0_always_en
+//Bit 19 osd_hsc_nearest_en
+//Bit 17:16 osd_hsc_rpt_p0_num1
+//Bit 14:11 osd_hsc_ini_rcv_num1
+//Bit 9:8 osd_hsc_rpt_p0_num0
+//Bit 6:3 osd_hsc_ini_rcv_num0
+//Bit 2:0 osd_hsc_bank_length
+#define OSD4_HSC_INI_PAT_CTRL ((0x5ac6 << 2) + 0xff000000)
+//for 3D quincunx sub-sampling
+//bit 15:8 pattern, each patten 1 bit, from lsb -> msb
+//bit 6:4 pattern start
+//bit 2:0 pattern end
+#define OSD4_SC_DUMMY_DATA ((0x5ac7 << 2) + 0xff000000)
+//bit 31:24, componet 0
+//bit 23:16, component 1
+//bit 15:8, component 2
+//bit 7:0 component 3, alpha
+#define OSD4_SC_CTRL0 ((0x5ac8 << 2) + 0xff000000)
+//Bit 14 osc_sc_din_osd1_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 13 osc_sc_din_osd2_alpha_mode, 1: (alpha >= 128) ? alpha -1: alpha, 0: (alpha >=1) ? alpha - 1: alpha.
+//Bit 12 osc_sc_dout_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 12 osc_sc_alpha_mode, 1: (alpha >= 128) ? alpha + 1: alpha, 0: (alpha >=1) ? alpha + 1: alpha.
+//Bit 11:4 default alpha for vd1 or vd2 if they are selected as the source
+//Bit 3 osd scaler path enable
+//Bit 1:0 osd_sc_sel, 00: select osd1 input, 01: select osd2 input, 10: select vd1 input, 11: select vd2 input after matrix
+#define OSD4_SCI_WH_M1 ((0x5ac9 << 2) + 0xff000000)
+//Bit 28:16 OSD scaler input width minus 1
+//Bit 12:0 OSD scaler input height minus 1
+#define OSD4_SCO_H_START_END ((0x5aca << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output horizontal start
+//Bit 12:0 OSD scaler output horizontal end
+#define OSD4_SCO_V_START_END ((0x5acb << 2) + 0xff000000)
+//Bit 28:16 OSD scaler output vertical start
+//Bit 12:0 OSD scaler output vertical end
+#define OSD4_SCALE_COEF_IDX ((0x5acc << 2) + 0xff000000)
+//Because there are many coefficients used in the vertical filter and horizontal filters,
+//indirect access the coefficients of vertical filter and horizontal filter is used.
+//For vertical filter, there are 33x4 coefficients
+//For horizontal filter, there are 33x4 coefficients
+//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
+//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
+//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
+//Bit 8 type of index, 0: vertical coef, 1: horizontal coef
+//Bit 6:0 coef index
+#define OSD4_SCALE_COEF ((0x5acd << 2) + 0xff000000)
+//coefficients for vertical filter and horizontal filter
+ // synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_osd4_scale.h
+//
+//
+// Reading file: vpu_osd4_deband_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define OSD4_DB_FLT_CTRL ((0x5ae0 << 2) + 0xff000000)
+//Bit 31:27 reserved
+//Bit 26 reg_nrdeband_reset1 // unsigned , default = 1 , 0 : no reload chrm seed 1: reload chrm seed
+//Bit 25 reg_nrdeband_reset0 // unsigned , default = 1 , 0 : no reload luma seed 1: reload luma seed
+//Bit 24 reg_nrdeband_rgb // unsigned , default = 0 , 0 : yuv 1: RGB
+//Bit 23 reg_nrdeband_en11 // unsigned , default = 0 , debanding registers of side lines, [0] for luma, same for below
+//Bit 22 reg_nrdeband_en10 // unsigned , default = 0 , debanding registers of side lines, [1] for chroma, same for below
+//Bit 21 reg_nrdeband_siderand // unsigned , default = 1 , options to use side two lines use the rand, instead of use for the YUV three component of middle line, 0: seed[3]/bandrand[3] for middle line yuv; 1: seed[3]/bandrand[3] for nearby three lines Y;
+//Bit 20 reg_nrdeband_randmode // unsigned , default = 0 , mode of rand noise adding, 0: same noise strength for all difs; else: strenght of noise will not exceed the difs, MIN((pPKReg->reg_nrdeband_bandrand[m]), noise[m])
+//Bit 19:17 reg_nrdeband_bandrand2 // unsigned , default = 6
+//Bit 16 reserved
+//Bit 15:13 reg_nrdeband_bandrand1 // unsigned , default = 6
+//Bit 12 reserved
+//Bit 11: 9 reg_nrdeband_bandrand0 // unsigned , default = 6
+//Bit 8 reserved
+//Bit 7 reg_nrdeband_hpxor1 // unsigned , default = 1 , debanding random hp portion xor, [0] for luma
+//Bit 6 reg_nrdeband_hpxor0 // unsigned , default = 1 , debanding random hp portion xor, [1] for chroma
+//Bit 5 reg_nrdeband_en1 // unsigned , default = 0 , debanding registers, for luma
+//Bit 4 reg_nrdeband_en0 // unsigned , default = 0 , debanding registers, for chroma
+//Bit 3: 2 reg_nrdeband_lpf_mode1 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+//Bit 1: 0 reg_nrdeband_lpf_mode0 // unsigned , default = 2 , lpf mode, 0: 3x3, 1:3x5; 2: 5x5; 3:5x7
+#define OSD4_DB_FLT_CTRL1 ((0x5ae1 << 2) + 0xff000000)
+//Bit 31:18 reserved
+//Bit 17:16 reg_nrdeband_noise_rs // unsigned , default = 2
+//Bit 15:12 reg_nrdeband_randgain // unsigned , default = 8
+//Bit 11 reserved
+//Bit 10: 8 reg_nrdeband_bandrand5 // unsigned , default = 6
+//Bit 7 reserved
+//Bit 6: 4 reg_nrdeband_bandrand4 // unsigned , default = 6
+//Bit 3 reserved
+//Bit 2: 0 reg_nrdeband_bandrand3 // unsigned , default = 6
+#define OSD4_DB_FLT_LUMA_THRD ((0x5ae2 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_luma_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_luma_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_luma_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_luma_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif <th[3] (lpf*1 + 3*y)/4; else
+#define OSD4_DB_FLT_CHRM_THRD ((0x5ae3 << 2) + 0xff000000)
+//Bit 31:30 reserved
+//Bit 29:24 reg_nrdeband_chrm_th3 // unsigned , default = 36 , threshold to |Y-Ylpf|, if < th[0] use lpf
+//Bit 23:22 reserved
+//Bit 21:16 reg_nrdeband_chrm_th2 // unsigned , default = 28 , elseif <th[1] use (lpf*3 + y)/4
+//Bit 15:14 reserved
+//Bit 13: 8 reg_nrdeband_chrm_th1 // unsigned , default = 24 , elseif <th[1] use (lpf*3 + y)/4elseif <th[2] (lpf*1 + y)/2
+//Bit 7: 6 reserved
+//Bit 5: 0 reg_nrdeband_chrm_th0 // unsigned , default = 20 , elseif <th[1] use (lpf*3 + y)/4elseif elseif
+#define OSD4_DB_FLT_RANDLUT ((0x5ae4 << 2) + 0xff000000)
+//Bit 31:24 reserved
+//Bit 23:21 reg_nrdeband_randslut7 // unsigned , default = 1 rand lut7
+//Bit 20:18 reg_nrdeband_randslut6 // unsigned , default = 1 rand lut6
+//Bit 17:15 reg_nrdeband_randslut5 // unsigned , default = 1 rand lut5
+//Bit 14:12 reg_nrdeband_randslut4 // unsigned , default = 1 rand lut4
+//Bit 11: 9 reg_nrdeband_randslut3 // unsigned , default = 1 rand lut3
+//Bit 8: 6 reg_nrdeband_randslut2 // unsigned , default = 1 rand lut2
+//Bit 5: 3 reg_nrdeband_randslut1 // unsigned , default = 1 rand lut1
+//Bit 2: 0 reg_nrdeband_randslut0 // unsigned , default = 1 rand lut0
+#define OSD4_DB_FLT_PXI_THRD ((0x5ae5 << 2) + 0xff000000)
+//Bit 31:26 reserved
+//Bit 25:16 reg_nrdeband_yc_th1 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+//Bit 15:10 reserved
+//Bit 9: 0 reg_nrdeband_yc_th0 // unsigned , default = 0 ,threshold to luma/|u/v| for using the denoise
+#define OSD4_DB_FLT_SEED_Y ((0x5ae6 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed0 // unsigned , default = 1621438240 ,debanding noise adding seed for Y. seed[0]= 0x60a52f20; as default
+#define OSD4_DB_FLT_SEED_U ((0x5ae7 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed1 // unsigned , default = 1621438247 ,debanding noise adding seed for U. seed[0]= 0x60a52f27; as default
+#define OSD4_DB_FLT_SEED_V ((0x5ae8 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed2 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD4_DB_FLT_SEED3 ((0x5ae9 << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed3 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD4_DB_FLT_SEED4 ((0x5aea << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed4 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+#define OSD4_DB_FLT_SEED5 ((0x5aeb << 2) + 0xff000000)
+//Bit 31: 0 reg_nrdeband_seed5 // unsigned , default = 1621438242 ,debanding noise adding seed for V. seed[0]= 0x60a52f22; as default
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: vpu_osd4_deband_regs.h
+//
+//
+// Closing file: vppk_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VPPL_VCBUS_BASE = 0x5b
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: vppl_regs.h
+//
+//0x00-0x4f
+//
+// Reading file: osd2_hdr2_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//osd1 0x40 - 0x7f
+#define OSD2_HDR2_CTRL ((0x5b00 << 2) + 0xff000000)
+#define OSD2_HDR2_CLK_GATE ((0x5b01 << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXI_COEF00_01 ((0x5b02 << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXI_COEF02_10 ((0x5b03 << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXI_COEF11_12 ((0x5b04 << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXI_COEF20_21 ((0x5b05 << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXI_COEF22 ((0x5b06 << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXI_COEF30_31 ((0x5b07 << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXI_COEF32_40 ((0x5b08 << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXI_COEF41_42 ((0x5b09 << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXI_OFFSET0_1 ((0x5b0a << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXI_OFFSET2 ((0x5b0b << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x5b0c << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXI_PRE_OFFSET2 ((0x5b0d << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXO_COEF00_01 ((0x5b0e << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXO_COEF02_10 ((0x5b0f << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXO_COEF11_12 ((0x5b10 << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXO_COEF20_21 ((0x5b11 << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXO_COEF22 ((0x5b12 << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXO_COEF30_31 ((0x5b13 << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXO_COEF32_40 ((0x5b14 << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXO_COEF41_42 ((0x5b15 << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXO_OFFSET0_1 ((0x5b16 << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXO_OFFSET2 ((0x5b17 << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x5b18 << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXO_PRE_OFFSET2 ((0x5b19 << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXI_CLIP ((0x5b1a << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXO_CLIP ((0x5b1b << 2) + 0xff000000)
+#define OSD2_HDR2_CGAIN_OFFT ((0x5b1c << 2) + 0xff000000)
+#define OSD2_HDR2_HIST_RD ((0x5b1d << 2) + 0xff000000)
+#define OSD2_EOTF_LUT_ADDR_PORT ((0x5b1e << 2) + 0xff000000)
+#define OSD2_EOTF_LUT_DATA_PORT ((0x5b1f << 2) + 0xff000000)
+#define OSD2_OETF_LUT_ADDR_PORT ((0x5b20 << 2) + 0xff000000)
+#define OSD2_OETF_LUT_DATA_PORT ((0x5b21 << 2) + 0xff000000)
+#define OSD2_CGAIN_LUT_ADDR_PORT ((0x5b22 << 2) + 0xff000000)
+#define OSD2_CGAIN_LUT_DATA_PORT ((0x5b23 << 2) + 0xff000000)
+#define OSD2_HDR2_CGAIN_COEF0 ((0x5b24 << 2) + 0xff000000)
+#define OSD2_HDR2_CGAIN_COEF1 ((0x5b25 << 2) + 0xff000000)
+#define OSD2_OGAIN_LUT_ADDR_PORT ((0x5b26 << 2) + 0xff000000)
+#define OSD2_OGAIN_LUT_DATA_PORT ((0x5b27 << 2) + 0xff000000)
+#define OSD2_HDR2_ADPS_CTRL ((0x5b28 << 2) + 0xff000000)
+#define OSD2_HDR2_ADPS_ALPHA0 ((0x5b29 << 2) + 0xff000000)
+#define OSD2_HDR2_ADPS_ALPHA1 ((0x5b2a << 2) + 0xff000000)
+#define OSD2_HDR2_ADPS_BETA0 ((0x5b2b << 2) + 0xff000000)
+#define OSD2_HDR2_ADPS_BETA1 ((0x5b2c << 2) + 0xff000000)
+#define OSD2_HDR2_ADPS_BETA2 ((0x5b2d << 2) + 0xff000000)
+#define OSD2_HDR2_ADPS_COEF0 ((0x5b2e << 2) + 0xff000000)
+#define OSD2_HDR2_ADPS_COEF1 ((0x5b2f << 2) + 0xff000000)
+#define OSD2_HDR2_GMUT_CTRL ((0x5b30 << 2) + 0xff000000)
+#define OSD2_HDR2_GMUT_COEF0 ((0x5b31 << 2) + 0xff000000)
+#define OSD2_HDR2_GMUT_COEF1 ((0x5b32 << 2) + 0xff000000)
+#define OSD2_HDR2_GMUT_COEF2 ((0x5b33 << 2) + 0xff000000)
+#define OSD2_HDR2_GMUT_COEF3 ((0x5b34 << 2) + 0xff000000)
+#define OSD2_HDR2_GMUT_COEF4 ((0x5b35 << 2) + 0xff000000)
+#define OSD2_HDR2_PIPE_CTRL1 ((0x5b36 << 2) + 0xff000000)
+#define OSD2_HDR2_PIPE_CTRL2 ((0x5b37 << 2) + 0xff000000)
+#define OSD2_HDR2_PIPE_CTRL3 ((0x5b38 << 2) + 0xff000000)
+#define OSD2_HDR2_PROC_WIN1 ((0x5b39 << 2) + 0xff000000)
+#define OSD2_HDR2_PROC_WIN2 ((0x5b3a << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXI_EN_CTRL ((0x5b3b << 2) + 0xff000000)
+#define OSD2_HDR2_MATRIXO_EN_CTRL ((0x5b3c << 2) + 0xff000000)
+#define OSD2_HDR2_HIST_CTRL ((0x5b3d << 2) + 0xff000000)
+#define OSD2_HDR2_HIST_H_START_END ((0x5b3e << 2) + 0xff000000)
+#define OSD2_HDR2_HIST_V_START_END ((0x5b3f << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: osd2_hdr2_regs.h
+//
+//0x50-0x9f
+//
+// Reading file: osd3_hdr2_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//osd1 0x40 - 0x7f
+#define OSD3_HDR2_CTRL ((0x5b50 << 2) + 0xff000000)
+#define OSD3_HDR2_CLK_GATE ((0x5b51 << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXI_COEF00_01 ((0x5b52 << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXI_COEF02_10 ((0x5b53 << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXI_COEF11_12 ((0x5b54 << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXI_COEF20_21 ((0x5b55 << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXI_COEF22 ((0x5b56 << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXI_COEF30_31 ((0x5b57 << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXI_COEF32_40 ((0x5b58 << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXI_COEF41_42 ((0x5b59 << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXI_OFFSET0_1 ((0x5b5a << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXI_OFFSET2 ((0x5b5b << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x5b5c << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXI_PRE_OFFSET2 ((0x5b5d << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXO_COEF00_01 ((0x5b5e << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXO_COEF02_10 ((0x5b5f << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXO_COEF11_12 ((0x5b60 << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXO_COEF20_21 ((0x5b61 << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXO_COEF22 ((0x5b62 << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXO_COEF30_31 ((0x5b63 << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXO_COEF32_40 ((0x5b64 << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXO_COEF41_42 ((0x5b65 << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXO_OFFSET0_1 ((0x5b66 << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXO_OFFSET2 ((0x5b67 << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x5b68 << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXO_PRE_OFFSET2 ((0x5b69 << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXI_CLIP ((0x5b6a << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXO_CLIP ((0x5b6b << 2) + 0xff000000)
+#define OSD3_HDR2_CGAIN_OFFT ((0x5b6c << 2) + 0xff000000)
+#define OSD3_HDR2_HIST_RD ((0x5b6d << 2) + 0xff000000)
+#define OSD3_EOTF_LUT_ADDR_PORT ((0x5b6e << 2) + 0xff000000)
+#define OSD3_EOTF_LUT_DATA_PORT ((0x5b6f << 2) + 0xff000000)
+#define OSD3_OETF_LUT_ADDR_PORT ((0x5b70 << 2) + 0xff000000)
+#define OSD3_OETF_LUT_DATA_PORT ((0x5b71 << 2) + 0xff000000)
+#define OSD3_CGAIN_LUT_ADDR_PORT ((0x5b72 << 2) + 0xff000000)
+#define OSD3_CGAIN_LUT_DATA_PORT ((0x5b73 << 2) + 0xff000000)
+#define OSD3_HDR2_CGAIN_COEF0 ((0x5b74 << 2) + 0xff000000)
+#define OSD3_HDR2_CGAIN_COEF1 ((0x5b75 << 2) + 0xff000000)
+#define OSD3_OGAIN_LUT_ADDR_PORT ((0x5b76 << 2) + 0xff000000)
+#define OSD3_OGAIN_LUT_DATA_PORT ((0x5b77 << 2) + 0xff000000)
+#define OSD3_HDR2_ADPS_CTRL ((0x5b78 << 2) + 0xff000000)
+#define OSD3_HDR2_ADPS_ALPHA0 ((0x5b79 << 2) + 0xff000000)
+#define OSD3_HDR2_ADPS_ALPHA1 ((0x5b7a << 2) + 0xff000000)
+#define OSD3_HDR2_ADPS_BETA0 ((0x5b7b << 2) + 0xff000000)
+#define OSD3_HDR2_ADPS_BETA1 ((0x5b7c << 2) + 0xff000000)
+#define OSD3_HDR2_ADPS_BETA2 ((0x5b7d << 2) + 0xff000000)
+#define OSD3_HDR2_ADPS_COEF0 ((0x5b7e << 2) + 0xff000000)
+#define OSD3_HDR2_ADPS_COEF1 ((0x5b7f << 2) + 0xff000000)
+#define OSD3_HDR2_GMUT_CTRL ((0x5b80 << 2) + 0xff000000)
+#define OSD3_HDR2_GMUT_COEF0 ((0x5b81 << 2) + 0xff000000)
+#define OSD3_HDR2_GMUT_COEF1 ((0x5b82 << 2) + 0xff000000)
+#define OSD3_HDR2_GMUT_COEF2 ((0x5b83 << 2) + 0xff000000)
+#define OSD3_HDR2_GMUT_COEF3 ((0x5b84 << 2) + 0xff000000)
+#define OSD3_HDR2_GMUT_COEF4 ((0x5b85 << 2) + 0xff000000)
+#define OSD3_HDR2_PIPE_CTRL1 ((0x5b86 << 2) + 0xff000000)
+#define OSD3_HDR2_PIPE_CTRL2 ((0x5b87 << 2) + 0xff000000)
+#define OSD3_HDR2_PIPE_CTRL3 ((0x5b88 << 2) + 0xff000000)
+#define OSD3_HDR2_PROC_WIN1 ((0x5b89 << 2) + 0xff000000)
+#define OSD3_HDR2_PROC_WIN2 ((0x5b8a << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXI_EN_CTRL ((0x5b8b << 2) + 0xff000000)
+#define OSD3_HDR2_MATRIXO_EN_CTRL ((0x5b8c << 2) + 0xff000000)
+#define OSD3_HDR2_HIST_CTRL ((0x5b8d << 2) + 0xff000000)
+#define OSD3_HDR2_HIST_H_START_END ((0x5b8e << 2) + 0xff000000)
+#define OSD3_HDR2_HIST_V_START_END ((0x5b8f << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: osd3_hdr2_regs.h
+//
+//0xa0-0xef
+//
+// Reading file: osd4_hdr2_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//osd1 0x40 - 0x7f
+#define OSD4_HDR2_CTRL ((0x5ba0 << 2) + 0xff000000)
+#define OSD4_HDR2_CLK_GATE ((0x5ba1 << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXI_COEF00_01 ((0x5ba2 << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXI_COEF02_10 ((0x5ba3 << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXI_COEF11_12 ((0x5ba4 << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXI_COEF20_21 ((0x5ba5 << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXI_COEF22 ((0x5ba6 << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXI_COEF30_31 ((0x5ba7 << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXI_COEF32_40 ((0x5ba8 << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXI_COEF41_42 ((0x5ba9 << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXI_OFFSET0_1 ((0x5baa << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXI_OFFSET2 ((0x5bab << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXI_PRE_OFFSET0_1 ((0x5bac << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXI_PRE_OFFSET2 ((0x5bad << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXO_COEF00_01 ((0x5bae << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXO_COEF02_10 ((0x5baf << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXO_COEF11_12 ((0x5bb0 << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXO_COEF20_21 ((0x5bb1 << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXO_COEF22 ((0x5bb2 << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXO_COEF30_31 ((0x5bb3 << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXO_COEF32_40 ((0x5bb4 << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXO_COEF41_42 ((0x5bb5 << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXO_OFFSET0_1 ((0x5bb6 << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXO_OFFSET2 ((0x5bb7 << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXO_PRE_OFFSET0_1 ((0x5bb8 << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXO_PRE_OFFSET2 ((0x5bb9 << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXI_CLIP ((0x5bba << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXO_CLIP ((0x5bbb << 2) + 0xff000000)
+#define OSD4_HDR2_CGAIN_OFFT ((0x5bbc << 2) + 0xff000000)
+#define OSD4_HDR2_HIST_RD ((0x5bbd << 2) + 0xff000000)
+#define OSD4_EOTF_LUT_ADDR_PORT ((0x5bbe << 2) + 0xff000000)
+#define OSD4_EOTF_LUT_DATA_PORT ((0x5bbf << 2) + 0xff000000)
+#define OSD4_OETF_LUT_ADDR_PORT ((0x5bc0 << 2) + 0xff000000)
+#define OSD4_OETF_LUT_DATA_PORT ((0x5bc1 << 2) + 0xff000000)
+#define OSD4_CGAIN_LUT_ADDR_PORT ((0x5bc2 << 2) + 0xff000000)
+#define OSD4_CGAIN_LUT_DATA_PORT ((0x5bc3 << 2) + 0xff000000)
+#define OSD4_HDR2_CGAIN_COEF0 ((0x5bc4 << 2) + 0xff000000)
+#define OSD4_HDR2_CGAIN_COEF1 ((0x5bc5 << 2) + 0xff000000)
+#define OSD4_OGAIN_LUT_ADDR_PORT ((0x5bc6 << 2) + 0xff000000)
+#define OSD4_OGAIN_LUT_DATA_PORT ((0x5bc7 << 2) + 0xff000000)
+#define OSD4_HDR2_ADPS_CTRL ((0x5bc8 << 2) + 0xff000000)
+#define OSD4_HDR2_ADPS_ALPHA0 ((0x5bc9 << 2) + 0xff000000)
+#define OSD4_HDR2_ADPS_ALPHA1 ((0x5bca << 2) + 0xff000000)
+#define OSD4_HDR2_ADPS_BETA0 ((0x5bcb << 2) + 0xff000000)
+#define OSD4_HDR2_ADPS_BETA1 ((0x5bcc << 2) + 0xff000000)
+#define OSD4_HDR2_ADPS_BETA2 ((0x5bcd << 2) + 0xff000000)
+#define OSD4_HDR2_ADPS_COEF0 ((0x5bce << 2) + 0xff000000)
+#define OSD4_HDR2_ADPS_COEF1 ((0x5bcf << 2) + 0xff000000)
+#define OSD4_HDR2_GMUT_CTRL ((0x5bd0 << 2) + 0xff000000)
+#define OSD4_HDR2_GMUT_COEF0 ((0x5bd1 << 2) + 0xff000000)
+#define OSD4_HDR2_GMUT_COEF1 ((0x5bd2 << 2) + 0xff000000)
+#define OSD4_HDR2_GMUT_COEF2 ((0x5bd3 << 2) + 0xff000000)
+#define OSD4_HDR2_GMUT_COEF3 ((0x5bd4 << 2) + 0xff000000)
+#define OSD4_HDR2_GMUT_COEF4 ((0x5bd5 << 2) + 0xff000000)
+#define OSD4_HDR2_PIPE_CTRL1 ((0x5bd6 << 2) + 0xff000000)
+#define OSD4_HDR2_PIPE_CTRL2 ((0x5bd7 << 2) + 0xff000000)
+#define OSD4_HDR2_PIPE_CTRL3 ((0x5bd8 << 2) + 0xff000000)
+#define OSD4_HDR2_PROC_WIN1 ((0x5bd9 << 2) + 0xff000000)
+#define OSD4_HDR2_PROC_WIN2 ((0x5bda << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXI_EN_CTRL ((0x5bdb << 2) + 0xff000000)
+#define OSD4_HDR2_MATRIXO_EN_CTRL ((0x5bdc << 2) + 0xff000000)
+#define OSD4_HDR2_HIST_CTRL ((0x5bdd << 2) + 0xff000000)
+#define OSD4_HDR2_HIST_H_START_END ((0x5bde << 2) + 0xff000000)
+#define OSD4_HDR2_HIST_V_START_END ((0x5bdf << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: osd4_hdr2_regs.h
+//
+//
+// Closing file: vppl_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: DOLBY1C_VCBUS_BASE = 0x60
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: dolby1c_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DOLBY_CORE1C_REG_START ((0x6000 << 2) + 0xff000000)
+#define DOLBY_CORE1C_CLKGATE_CTRL ((0x60f2 << 2) + 0xff000000)
+#define DOLBY_CORE1C_SWAP_CTRL0 ((0x60f3 << 2) + 0xff000000)
+#define DOLBY_CORE1C_SWAP_CTRL1 ((0x60f4 << 2) + 0xff000000)
+#define DOLBY_CORE1C_SWAP_CTRL2 ((0x60f5 << 2) + 0xff000000)
+#define DOLBY_CORE1C_SWAP_CTRL3 ((0x60f6 << 2) + 0xff000000)
+#define DOLBY_CORE1C_SWAP_CTRL4 ((0x60f7 << 2) + 0xff000000)
+#define DOLBY_CORE1C_SWAP_CTRL5 ((0x60f8 << 2) + 0xff000000)
+#define DOLBY_CORE1C_DMA_CTRL ((0x60f9 << 2) + 0xff000000)
+#define DOLBY_CORE1C_DMA_STATUS ((0x60fa << 2) + 0xff000000)
+#define DOLBY_CORE1C_STATUS0 ((0x60fb << 2) + 0xff000000)
+#define DOLBY_CORE1C_STATUS1 ((0x60fc << 2) + 0xff000000)
+#define DOLBY_CORE1C_STATUS2 ((0x60fd << 2) + 0xff000000)
+#define DOLBY_CORE1C_STATUS3 ((0x60fe << 2) + 0xff000000)
+#define DOLBY_CORE1C_DMA_PORT ((0x60ff << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dolby1c_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: DOLBY2C_VCBUS_BASE = 0x61
+// -----------------------------------------------
+//===========================================================================
+//
+// Reading file: dolby2c_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+#define DOLBY_CORE2C_REG_START ((0x6100 << 2) + 0xff000000)
+#define DOLBY_CORE2C_CLKGATE_CTRL ((0x6132 << 2) + 0xff000000)
+#define DOLBY_CORE2C_SWAP_CTRL0 ((0x6133 << 2) + 0xff000000)
+#define DOLBY_CORE2C_SWAP_CTRL1 ((0x6134 << 2) + 0xff000000)
+#define DOLBY_CORE2C_SWAP_CTRL2 ((0x6135 << 2) + 0xff000000)
+#define DOLBY_CORE2C_SWAP_CTRL3 ((0x6136 << 2) + 0xff000000)
+#define DOLBY_CORE2C_SWAP_CTRL4 ((0x6137 << 2) + 0xff000000)
+#define DOLBY_CORE2C_SWAP_CTRL5 ((0x6138 << 2) + 0xff000000)
+#define DOLBY_CORE2C_DMA_CTRL ((0x6139 << 2) + 0xff000000)
+#define DOLBY_CORE2C_DMA_STATUS ((0x613a << 2) + 0xff000000)
+#define DOLBY_CORE2C_STATUS0 ((0x613b << 2) + 0xff000000)
+#define DOLBY_CORE2C_STATUS1 ((0x613c << 2) + 0xff000000)
+#define DOLBY_CORE2C_STATUS2 ((0x613d << 2) + 0xff000000)
+#define DOLBY_CORE2C_STATUS3 ((0x613e << 2) + 0xff000000)
+#define DOLBY_CORE2C_DMA_PORT ((0x613f << 2) + 0xff000000)
+#define DOLBY_CORE2C_AXI2DMA_CTRL0 ((0x6140 << 2) + 0xff000000)
+#define DOLBY_CORE2C_AXI2DMA_CTRL1 ((0x6141 << 2) + 0xff000000)
+#define DOLBY_CORE2C_AXI2DMA_CTRL2 ((0x6142 << 2) + 0xff000000)
+#define DOLBY_CORE2C_AXI2DMA_CTRL3 ((0x6143 << 2) + 0xff000000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: dolby2c_regs.h
+//
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: VPP2_VCBUS_BASE = 0x70
+// -----------------------------------------------
+// -----------------------------------------------
+// REG_BASE: VIU2_VCBUS_BASE = 0x71
+// -----------------------------------------------
+//===========================================================================
+//`include "v2regs.h"
+//`include "viu2_regs.h"
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: ./vcbus_regs.h
+//
+//
+// Reading file: ./ge2d_regs.h
+//
+// synopsys translate_off
+// synopsys translate_on
+//===========================================================================
+////// GE2D Registers 0x8a0 - 0x8ff
+//address is 0xd016_0000 - 0xd0160000 - 0xd01603ff
+//===========================================================================
+// -----------------------------------------------
+// REG_BASE: GE2D_GCBUS_BASE = 0x00
+// -----------------------------------------------
+//Bit 31, destination bytemask only if destination bitmask is enable
+//Bit 30, destination bitmask enable
+//Bit 29, source2 key enable
+//Bit 28, source2 key mode, 0: mask data when match, 1: mask data when unmatch
+//Bit 27, source1 key enable
+//Bit 26, source1 key mode, 0: mask data when match, 1: mask data when unmatch
+//Bit 25:24, dst1 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 23 dst clip mode, 0: write inside clip window, 1: write outside clip window
+//Bit 22:17, reserved
+//Bit 16:15, src2 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 14 src2 fill mode, 0: repeat data, 1: fill default color
+//Bit 13:12 src2 picture struct, 00: frame, 10: even, 11: odd
+//Bit 11 src1 x direction yc ration, 0: 1:1, 1: 2:1
+//Bit 10 src1 y direction yc ration, 0: 1:1, 1: 2:1
+//Bit 9:7 reserved
+//Bit 6:5, src1 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 4 src1 fill mode, 0: repeat data, 1: fill default color
+//Bit 3 src1 lookup table enable
+//Bit 2:1 src1 picture struct, 00: frame, 10: even, 11: odd
+//Bit 0 src1 separate buffer enable
+#define GE2D_GEN_CTRL0 ((0x00a0 << 2) + 0xff040000)
+//Bit 31, soft rst
+//Bit 30, dst write response counter reset
+//Bit 29, disable adding dst write response count to busy bit
+//Bit 28:26, reserved
+//bit 25:24, interrupt control, if bit[0] true, generate interrupt when one command done,
+// if bit[1] true, generate interrupt when ge2d change from busy to not busy
+//Bit 23:22 src2 burst size control
+//Bit 21:16 src1 burst size control, 5:4, yfifo, 3:2, cbfifo, 1:0, crfifo
+// each 2bit, 00: 24 64bitword, 01: 32 64bitword, 10: 48 64bitwords, 11: 64 64bitwords
+//Bit 15:14, dst1 picture struct, 00: frame, 10:top, 11: bottom
+//Bit 13:12, bit 13 if true, force read src1, bit 12 if true, force read src2
+//Bit 11, dst2 request urgent enable
+//Bit 10, src1 request urgent enable
+//Bit 9, src2 request urgent enable
+//Bit 8, dst1 request urgent enable
+//Bit 7:0 src1 global alpha
+#define GE2D_GEN_CTRL1 ((0x00a1 << 2) + 0xff040000)
+//Bit31 alpha conversion mode in alu, 0: alpha_out = (alpha !=0) ? alpha +1 : 0;
+// otherwise, alpha_out = (alpha < 128) ? alpha: alpha + 1;
+//Bit30 color conversion mode in alu, 0: color_out = (color != 0) ? color +1: 0;
+// otherwise, color_out = (color < 128) ? color: color + 1;
+//Bit29 src1_gb_alpha_en, As = src1_gb_alpha_en ? Asr * Ag: Asr
+//Bit28 dst1_color_round_mode, 0: truncate, 1: + 0.5 rounding
+//Bit27 src2_color_expand_mode, 0: add 0, 1: add MSBs
+//Bit26 src2_alpha_expand_mode, 0: add 0, 1: add MSBs
+//Bit25 src1_color_expand_mode, 0: add 0, 1: add MSBs
+//Bit24 src1_alpha_expand_mode, 0: add 0, 1: add MSBs
+//Bit 23 if true, dst little endian, otherwise big endian
+//Bit 22:19 dst1 color_map
+// dst1_format=0 : output 8-bit;
+// dst1_format=1, dst1_color_map=1: output 16-bit YCbCr 655;
+// dst1_format=1, dst1_color_map=2: output 16-bit YCbCr 844;
+// dst1_format=1, dst1_color_map=3: output 16-bit YCbCrA 6442;
+// dst1_format=1, dst1_color_map=4: output 16-bit YCbCrA 4444;
+// dst1_format=1, dst1_color_map=5: output 16-bit YCbCr 565;
+// dst1_format=1, dst1_color_map=6: output 16-bit AYCbCr 4444;
+// dst1_format=1, dst1_color_map=7: output 16-bit AYCbCr 1555;
+// dst1_format=1, dst1_color_map=8: output 16-bit YCbCrA 4642;
+// dst1_format=1, dst1_color_map=9: output 16-bit CbCr 88;
+// dst1_format=1, dst1_color_map=10:output 16-bit CrCb 88;
+// dst1_format=2, dst1_color_map=0: output 24-bit YCbCr 888;
+// dst1_format=2, dst1_color_map=1: output 24-bit YCbCrA 5658;
+// dst1_format=2, dst1_color_map=2: output 24-bit AYCbCr 8565;
+// dst1_format=2, dst1_color_map=3: output 24-bit YCbCrA 6666;
+// dst1_format=2, dst1_color_map=4: output 24-bit AYCbCr 6666;
+// dst1_format=2, dst1_color_map=5: output 24-bit CrCbY 888;
+// dst1_format=3, dst1_color_map=0: output 32-bit YCbCrA 8888;
+// dst1_format=3, dst1_color_map=1: output 32-bit AYCbCr 8888;
+// dst1_format=3, dst1_color_map=2: output 32-bit ACrCbY 8888;
+// dst1_format=3, dst1_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 17:16 dst1_format, 00: 8bit, 01:16bit, 10:24bit, 11: 32bit
+//Bit 15 if true, src2 little endian, otherwise big endian
+//Bit 14:11 src2 color_map
+// src2_format=0 : output 8-bit;
+// src2_format=1, src2_color_map=1: output 16-bit YCbCr 655;
+// src2_format=1, src2_color_map=2: output 16-bit YCbCr 844;
+// src2_format=1, src2_color_map=3: output 16-bit YCbCrA 6442;
+// src2_format=1, src2_color_map=4: output 16-bit YCbCrA 4444;
+// src2_format=1, src2_color_map=5: output 16-bit YCbCr 565;
+// src2_format=1, src2_color_map=6: output 16-bit AYCbCr 4444;
+// src2_format=1, src2_color_map=7: output 16-bit AYCbCr 1555;
+// src2_format=1, src2_color_map=8: output 16-bit YCbCrA 4642;
+// src2_format=2, src2_color_map=0: output 24-bit YCbCr 888;
+// src2_format=2, src2_color_map=1: output 24-bit YCbCrA 5658;
+// src2_format=2, src2_color_map=2: output 24-bit AYCbCr 8565;
+// src2_format=2, src2_color_map=3: output 24-bit YCbCrA 6666;
+// src2_format=2, src2_color_map=4: output 24-bit AYCbCr 6666;
+// src2_format=2, src2_color_map=5: output 24-bit CrCbY 888;
+// src2_format=3, src2_color_map=0: output 32-bit YCbCrA 8888;
+// src2_format=3, src2_color_map=1: output 32-bit AYCbCr 8888;
+// src2_format=3, src2_color_map=2: output 32-bit ACrCbY 8888;
+// src2_format=3, src2_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 9:8 src2 format, 00: 8bit, 01:16bit, 10:24bit 11: 32bit
+//Bit 7 if true, src1 little endian, otherwise big endian
+//Bit 6:3 src1 color_map
+// src1_format=0 : output 8-bit;
+// src1_format=1, src1_color_map=0: output 4:2:2 (Y0Cb0Y1Cr0);
+// src1_format=1, src1_color_map=1: output 16-bit YCbCr 655;
+// src1_format=1, src1_color_map=2: output 16-bit YCbCr 844;
+// src1_format=1, src1_color_map=3: output 16-bit YCbCrA 6442;
+// src1_format=1, src1_color_map=4: output 16-bit YCbCrA 4444;
+// src1_format=1, src1_color_map=5: output 16-bit YCbCr 565;
+// src1_format=1, src1_color_map=6: output 16-bit AYCbCr 4444;
+// src1_format=1, src1_color_map=7: output 16-bit AYCbCr 1555;
+// src1_format=1, src2_color_map=8: output 16-bit YCbCrA 4642;
+// src1_format=2, src1_color_map=0: output 24-bit YCbCr 888;
+// src1_format=2, src1_color_map=1: output 24-bit YCbCrA 5658;
+// src1_format=2, src1_color_map=2: output 24-bit AYCbCr 8565;
+// src1_format=2, src1_color_map=3: output 24-bit YCbCrA 6666;
+// src1_format=2, src1_color_map=4: output 24-bit AYCbCr 6666;
+// src1_format=2, src1_color_map=5: output 24-bit CrCbY 888;
+// src1_format=2, src1_color_map=14:output 8-bit Y and 16-bit CbCr;
+// src1_format=2, src1_color_map=15:output 8-bit Y and 16-bit CrCb;
+// src1_format=3, src1_color_map=0: output 32-bit YCbCrA 8888;
+// src1_format=3, src1_color_map=1: output 32-bit AYCbCr 8888;
+// src1_format=3, src1_color_map=2: output 32-bit ACrCbY 8888;
+// src1_format=3, src1_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 1:0 src1 format, 00: 8bit, 01:16bit/4:2:2, 10:24bit 11: 32bit
+#define GE2D_GEN_CTRL2 ((0x00a2 << 2) + 0xff040000)
+//Bit 9 if true, all src2 data use default color
+//Bit 8 if true, all src1 data use default color
+//Bit 7 if true, dst x/y swap
+//Bit 6 if true, dst x direction reversely read
+//Bit 5 if true, dst y direction reversely read
+//Bit 4 if true, src2 x direction reversely read
+//Bit 3 if true, src2 y direction reversely read
+//Bit 2 if true, src1 x direction reversely read
+//Bit 1 if true, src1 y direction reversely read
+//Bit 0 cmd write
+#define GE2D_CMD_CTRL ((0x00a3 << 2) + 0xff040000)
+//Read only
+//Bit 28:17 dst write response counter, for debug only
+//Bit 16:7 ge2d_dp status, for debug only
+//Bit 6 read src1 cmd ready
+//Bit 5 read src2 cmd ready
+//Bit 4 pre dpcmd ready
+//Bit 3 ge2d dpcmd ready
+//Bit 2 ge2d buffer command valid
+//Bit 1 ge2d current command valid
+//Bit 0 ge2d busy
+#define GE2D_STATUS0 ((0x00a4 << 2) + 0xff040000)
+//
+//Read only
+// Bit 29:16 ge2d_dst1_status, for debug only
+// Bit 15 ge2d_rd_src2 core.fifo_empty
+// Bit 14 ge2d_rd_src2 core.fifo_overflow
+// Bit 13:12 ge2d_rd_src2 core.req_st
+// Bit 11 ge2d_rd_src2 cmd_if.cmd_err, true if cmd_format=1
+// Bit 10 ge2d_rd_src2 cmd_if.cmd_st, 0=IDLE state, 1=BUSY state
+// Bit 9 ge2d_rd_src1 luma_core(chroma_core).fifo_empty
+// Bit 8 ge2d_rd_src1 luma_core(chroma_core).fifo_overflow
+// Bit 7: 6 ge2d_rd_src1 chroma_core.req_st_cr
+// Bit 5: 4 ge2d_rd_src1 chroma_core.req_st_cb
+// Bit 3: 2 ge2d_rd_src1 luma_core.req_st_y
+// Bit 1 ge2d_rd_src1 cmd_if.stat_read_window_err, 1=reading/clipping window setting exceed limit
+// Bit 0 ge2d_rd_src1 cmd_if.cmd_st, 0=IDLE state, 1=BUSY state
+#define GE2D_STATUS1 ((0x00a5 << 2) + 0xff040000)
+//SRC1 default clolor
+//{Y,Cb,Cr,A}/{R,G,B,A}
+#define GE2D_SRC1_DEF_COLOR ((0x00a6 << 2) + 0xff040000)
+//Bit 31, SRC1 clip x start extra, if true, one more data is read for chroma
+//Bit 28:16, SRC1 clip x start
+//Bit 15, SRC1 clip x end extra, if true, one more data is read for chroma
+//Bit 12:0, SRC1 clip x end
+#define GE2D_SRC1_CLIPX_START_END ((0x00a7 << 2) + 0xff040000)
+//Bit 31, SRC1 clip y start extra, if true, one more data is read for chroma
+//Bit 28:16, SRC1 clip y start
+//Bit 15, SRC1 clip y end extra, if true, one more data is read for chroma
+//Bit 12:0, SRC1 clip y end
+#define GE2D_SRC1_CLIPY_START_END ((0x00a8 << 2) + 0xff040000)
+//Bit 31:24, SRC1 canvas address0
+//Bit 23:16, SRC1 canvas address1
+//Bit 15:8, SRC1 canvas address2
+#define GE2D_SRC1_CANVAS ((0x00a9 << 2) + 0xff040000)
+//Bit 31, SRC1 x start extra bit1, if true, one more chroma data is read for x even start chroma data when y/c ratio = 2
+// or x even/odd start chroma extra data when y/c ratio = 1
+//Bit 30, SRC1 x start extra bit0, if true, one more chroma data is read for x odd start chroma data when y/c ratio = 2
+//Bit 29:16, SRC1 x start, signed data
+//Bit 15, SRC1 x end extra bit1, if true, one more chroma data is read for x odd end chroma data when y/c ratio = 2
+// or x even/odd end chroma extra data when y/c ratio = 1
+//Bit 14, SRC1 x end extra bit0, if true, one more chroma data is read for x even end chroma data when y/c ratio = 2
+//Bit 13:0, SRC1 x end, signed data
+#define GE2D_SRC1_X_START_END ((0x00aa << 2) + 0xff040000)
+//Bit 31, SRC1 y start extra, if true, one more chroma data is read for y even start chroma data when y/c ratio = 2
+// or y even/odd start chroma extra data when y/c ratio = 1
+//Bit 30, SRC1 y start extra, if true, one more chroma data is read for x odd start chroma data when y/c ratio = 2
+//Bit 28:16, SRC1 y start
+//Bit 15, SRC1 y end extra bit1, if true, one more chroma data is read for y odd end chroma data when y/c ratio = 2
+// or y even/odd end chroma extra data when y/c ratio = 1
+//Bit 14, SRC1 y end extra bit0, if true, one more chroma data is read for y even end chroma data when y/c ratio = 2
+//Bit 12:0, SRC1 y end
+#define GE2D_SRC1_Y_START_END ((0x00ab << 2) + 0xff040000)
+// Bit 31: 9 Reserved
+// Bit 8 RW, 0 = Write LUT, 1 = Read LUT
+// Bit 7: 0 RW, lut_addr
+#define GE2D_SRC1_LUT_ADDR ((0x00ac << 2) + 0xff040000)
+// Bit 31:24 RW, Y or R
+// Bit 23:16 RW, Cb or G
+// Bit 15: 8 RW, Cr or B
+// Bit 7: 0 RW, Alpha
+#define GE2D_SRC1_LUT_DAT ((0x00ad << 2) + 0xff040000)
+//Bit 19, if true, horizontal formatter using repeat to get the pixel, otherwise using interpolation
+//Bit 18, horizontal formatter en
+//Bit 17, if true, vertical formatter using repeat to get the pixel, otherwise using interpolation
+//Bit 16, vertical formatter en
+//Bit 15:8 X direction chroma phase,
+// [7:4] for x direction even start/end chroma phase when y/c ratio = 2
+// or start/end even/odd chroma phase when y/c ratio = 1
+// [3:0] for x direction odd start/end chroma phase only when y/c ration = 2
+//Bit 7:0 Y direction chroma phase,
+// [7:4] for y direction even start/end chroma phase when y/c ratio = 2
+// or start/end even/odd chroma phase when y/c ratio = 1
+// [3:0] for y direction odd start/end chroma phase only when y/c ration = 2
+#define GE2D_SRC1_FMT_CTRL ((0x00ae << 2) + 0xff040000)
+//SRC2 default clolor
+//{Y,Cb,Cr,A}/{R,G,B,A}
+#define GE2D_SRC2_DEF_COLOR ((0x00af << 2) + 0xff040000)
+//Bit 28:16, SRC2 clip x start
+//Bit 12:0, SRC2 clip x end
+#define GE2D_SRC2_CLIPX_START_END ((0x00b0 << 2) + 0xff040000)
+//Bit 28:16, SRC2 clip y start
+//Bit 12:0, SRC2 clip y end
+#define GE2D_SRC2_CLIPY_START_END ((0x00b1 << 2) + 0xff040000)
+//Bit 28:16, SRC2 x start
+//Bit 12:0, SRC2 x end
+#define GE2D_SRC2_X_START_END ((0x00b2 << 2) + 0xff040000)
+//Bit 28:16, SRC2 y start
+//Bit 12:0, SRC2 y end
+#define GE2D_SRC2_Y_START_END ((0x00b3 << 2) + 0xff040000)
+//Bit 28:16, DST clip x start
+//Bit 12:0, DST clip x end
+#define GE2D_DST_CLIPX_START_END ((0x00b4 << 2) + 0xff040000)
+//
+//Bit 28:16, DST clip y start
+//Bit 12:0, DST clip y end
+#define GE2D_DST_CLIPY_START_END ((0x00b5 << 2) + 0xff040000)
+//Bit 28:16, DST x start
+//Bit 12:0, DST x end
+#define GE2D_DST_X_START_END ((0x00b6 << 2) + 0xff040000)
+//
+//Bit 28:16, DST x start
+//Bit 12:0, DST x end
+#define GE2D_DST_Y_START_END ((0x00b7 << 2) + 0xff040000)
+//Bit 23:16 DST2 canvas address
+//Bit 15:8 SRC2 canvas address
+//Bit 7:0 DST1 canvas address
+#define GE2D_SRC2_DST_CANVAS ((0x00b8 << 2) + 0xff040000)
+//vertical scaler phase step
+//Bit 28:0, 5.24 format
+#define GE2D_VSC_START_PHASE_STEP ((0x00b9 << 2) + 0xff040000)
+//phase slope
+//Bit 24:0, bit 24 signed bit
+#define GE2D_VSC_PHASE_SLOPE ((0x00ba << 2) + 0xff040000)
+//Bit 30:29, vertical repeat line0 number
+//Bit 23:0, vertical scaler initial phase
+#define GE2D_VSC_INI_CTRL ((0x00bb << 2) + 0xff040000)
+//horizontal scaler phase step
+//Bit 28:0, 5.24 format
+#define GE2D_HSC_START_PHASE_STEP ((0x00bc << 2) + 0xff040000)
+//phase slope
+//Bit 24:0, bit 24 signed bit
+#define GE2D_HSC_PHASE_SLOPE ((0x00bd << 2) + 0xff040000)
+//Bit 30:29, horizontal repeat line0 number
+//Bit 23:0, horizontal scaler initial phase
+#define GE2D_HSC_INI_CTRL ((0x00be << 2) + 0xff040000)
+//Bit 31:24, advance number in this round, if horizontal scaler is working on dividing mode
+//Bit 23:0, horizontal scaler advance phase in this round, if horizontal scaler is working on dividing mode
+#define GE2D_HSC_ADV_CTRL ((0x00bf << 2) + 0xff040000)
+//Bit 30, vertical nearest mode enable, must set vt_bank_length = 4
+//Bit 29, horizontal nearest mode enable, must set hz_bank_length = 4
+//Bit 28, horizontal scaler dividing mode enable
+//Bit 27:15, horizontal dividing length, if bit 28 is enable
+//Bit 14, pre horizontal scaler enable
+//Bit 13, pre vertical scale enable
+//Bit 12, vertical scale enable
+//Bit 11, horizontal scaler enable
+//Bit 9, if true, treat horizontal repeat line number(GE2D_HSC_INI_CTRL bit 30:29) as repeating line,
+// otherwise using treat horizontal repeat line number as minus line number.
+//Bit 8, if true, treat vertical repeat line number(GE2D_VSC_INI_CTRL bit 30:29) as repeating line,
+// otherwise using treat vertical repeat line number as minus line number.
+//Bit 7, if true, always use phase0 in vertical scaler
+//Bit 6:4, vertical scaler bank length
+//Bit 3, if true, always use phase0 in horizontal scaler
+//Bit 2:0, horizontal scaler bank length
+#define GE2D_SC_MISC_CTRL ((0x00c0 << 2) + 0xff040000)
+//Read only
+//vertical scaler next round integer pixel pointer, signed data
+//Bit 13:0
+#define GE2D_VSC_NRND_POINT ((0x00c1 << 2) + 0xff040000)
+//Read only
+//vertical scaler next round phase
+//bit 23:0
+#define GE2D_VSC_NRND_PHASE ((0x00c2 << 2) + 0xff040000)
+//Read only
+//horizontal scaler next round integer pixel pointer, signed data
+//Bit 13:0
+#define GE2D_HSC_NRND_POINT ((0x00c3 << 2) + 0xff040000)
+//Read only
+//horizontal scaler next round phase
+//bit 23:0
+#define GE2D_HSC_NRND_PHASE ((0x00c4 << 2) + 0xff040000)
+//
+//Bit 28:20, pre_offset0
+//Bit 18:10, pre_offset1
+//Bit 8:0, pre_offset2
+#define GE2D_MATRIX_PRE_OFFSET ((0x00c5 << 2) + 0xff040000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define GE2D_MATRIX_COEF00_01 ((0x00c6 << 2) + 0xff040000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define GE2D_MATRIX_COEF02_10 ((0x00c7 << 2) + 0xff040000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define GE2D_MATRIX_COEF11_12 ((0x00c8 << 2) + 0xff040000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define GE2D_MATRIX_COEF20_21 ((0x00c9 << 2) + 0xff040000)
+//Bit 28:16 coef22
+//Bit 7 input y/cb/cr saturation enable
+//Bit 0 conversion matrix enable
+#define GE2D_MATRIX_COEF22_CTRL ((0x00ca << 2) + 0xff040000)
+//Bit 28:20, offset0
+//Bit 18:10, offset1
+//Bit 8:0, offset2
+#define GE2D_MATRIX_OFFSET ((0x00cb << 2) + 0xff040000)
+//Bit 26:25, SRC1 color multiplier alpha selection
+// if 00, Cs = Csr
+// if 01, Cs = Csr * Asr * Ag (if source is not premultiplied)
+// if 10, Cs = Csr * Ag (if source is premultipied)
+//Bit 24 SRC2 color multiplier alpha selection
+// if 0, no multiplier, Cd = Cdr, otherwise, Cd = Cdr * Ad.
+//Bit 22:12 ALU color operation
+// bit10:8 Blending Mode Parameter
+// 3'b000: ADD Cs*Fs + Cd*Fd
+// 3'b001: SUBTRACT Cs*Fs - Cd*Fd
+// 3'b010: REVERSE SUBTRACT Cd*Fd - Cs*Fs
+// 3'b011: MIN min(Cs*Fs, Cd*Fd)
+// 3'b100: MAX max(Cs*Fs, Cd*Fd)
+// 3'b101: LOGIC OP Cs op Cd
+// bit7:4 Source Color Blending Factor CFs
+// 4'b0000: ZERO 0
+// 4'b0001: ONE 1
+// 4'b0010: SRC_COLOR Cs(RGBs)
+// 4'b0011: ONE_MINUS_SRC_COLOR 1 - Cs(RGBs)
+// 4'b0100: DST_COLOR Cd(RGBd)
+// 4'b0101: ONE_MINUS_DST_COLOR 1 - Cd(RGBd)
+// 4'b0110: SRC_ALPHA As
+// 4'b0111: ONE_MINUS_SRC_ALPHA 1 - As
+// 4'b1000: DST_ALPHA Ad
+// 4'b1001: ONE_MINUS_DST_ALPHA 1 - Ad
+// 4'b1010: CONST_COLOR Cc(RGBc)
+// 4'b1011: ONE_MINUS_CONST_COLOR 1 - Cc(RGBc)
+// 4'b1100: CONST_ALPHA Ac
+// 4'b1101: ONE_MINUS_CONST_ALPHA 1 - Ac
+// 4'b1110: SRC_ALPHA_SATURATE min(As,1-Ad)
+// bit3:0 dest Color Blending Factor CFd, when bit10:8 != LOGIC OP
+// 4'b0000: ZERO 0
+// 4'b0001: ONE 1
+// 4'b0010: SRC_COLOR Cs(RGBs)
+// 4'b0011: ONE_MINUS_SRC_COLOR 1 - Cs(RGBs)
+// 4'b0100: DST_COLOR Cd(RGBd)
+// 4'b0101: ONE_MINUS_DST_COLOR 1 - Cd(RGBd)
+// 4'b0110: SRC_ALPHA As
+// 4'b0111: ONE_MINUS_SRC_ALPHA 1 - As
+// 4'b1000: DST_ALPHA Ad
+// 4'b1001: ONE_MINUS_DST_ALPHA 1 - Ad
+// 4'b1010: CONST_COLOR Cc(RGBc)
+// 4'b1011: ONE_MINUS_CONST_COLOR 1 - Cc(RGBc)
+// 4'b1100: CONST_ALPHA Ac
+// 4'b1101: ONE_MINUS_CONST_ALPHA 1 - Ac
+// 4'b1110: SRC_ALPHA_SATURATE min(As,1-Ad)
+// bit3:0 logic operations, when bit10:8 == LOGIC OP
+// 4'b0000: CLEAR 0
+// 4'b0001: COPY s
+// 4'b0010: NOOP d
+// 4'b0011: SET 1
+// 4'b0100: COPY_INVERT ~s
+// 4'b0101: INVERT ~d
+// 4'b0110: AND_REVERSE s & ~d
+// 4'b0111: OR_REVERSE s | ~d
+// 4'b1000: AND s & d
+// 4'b1001: OR s | d
+// 4'b1010: NAND ~(s & d)
+// 4'b1011: NOR ~(s | d)
+// 4'b1100: XOR s ^ d
+// 4'b1101: EQUIV ~(s ^ d)
+// 4'b1110: AND_INVERTED ~s & d
+// 4'b1111: OR_INVERTED ~s | d
+//Bit 10:0 ALU alpha operation
+// bit10:8 Blending Equation Math Operation
+// 3'b000: ADD As*Fs + Ad*Fd
+// 3'b001: SUBTRACT As*Fs - Ad*Fd
+// 3'b010: REVERSE SUBTRACT Ad*Fd - As*Fs
+// 3'b011: MIN min(As*Fs, Ad*Fd)
+// 3'b100: MAX max(As*Fs, Ad*Fd)
+// 3'b101: LOGIC OP As op Ad
+// bit7:4 Source alpha Blending Factor AFs
+// 4'b0000 0
+// 4'b0001 1
+// 4'b0010 As
+// 4'b0011 1 - As
+// 4'b0100 Ad
+// 4'b0101 1 - Ad
+// 4'b0110 Ac
+// 4'b0111 1 - Ac
+// .... reserved
+// bit3:0 Destination alpha Blending Factor AFd, when bit10:8 != LOGIC OP
+// 4'b0000 0
+// 4'b0001 1
+// 4'b0010 As
+// 4'b0011 1 - As
+// 4'b0100 Ad
+// 4'b0101 1 - Ad
+// 4'b0110 Ac
+// 4'b0111 1 - Ac
+// .... reserved
+// bit3:0 logic operations, when bit10:8 == LOGIC OP
+// 4'b0000: CLEAR 0
+// 4'b0001: COPY s
+// 4'b0010: NOOP d
+// 4'b0011: SET 1
+// 4'b0100: COPY_INVERT ~s
+// 4'b0101: INVERT ~d
+// 4'b0110: AND_REVERSE s & ~d
+// 4'b0111: OR_REVERSE s | ~d
+// 4'b1000: AND s & d
+// 4'b1001: OR s | d
+// 4'b1010: NAND ~(s & d)
+// 4'b1011: NOR ~(s | d)
+// 4'b1100: XOR s ^ d
+// 4'b1101: EQUIV ~(s ^ d)
+// 4'b1110: AND_INVERTED ~s & d
+// 4'b1111: OR_INVERTED ~s | d
+#define GE2D_ALU_OP_CTRL ((0x00cc << 2) + 0xff040000)
+//bit 31:0 (RGBA,YCBCRA)
+#define GE2D_ALU_CONST_COLOR ((0x00cd << 2) + 0xff040000)
+//SRC1 Key
+//31:0
+#define GE2D_SRC1_KEY ((0x00ce << 2) + 0xff040000)
+//SRC1 Key Mask
+//31:0
+#define GE2D_SRC1_KEY_MASK ((0x00cf << 2) + 0xff040000)
+//SRC2 Key
+//31:0
+#define GE2D_SRC2_KEY ((0x00d0 << 2) + 0xff040000)
+//SRC2 Key Mask
+//31:0
+#define GE2D_SRC2_KEY_MASK ((0x00d1 << 2) + 0xff040000)
+//Destination Bit Mask
+//31:0
+#define GE2D_DST_BITMASK ((0x00d2 << 2) + 0xff040000)
+//Bit 31 DP onoff mode, 0: on_counter means how many pixels will output before ge2d turns off
+// 1: on_counter means how many clocks will ge2d turn on before ge2d turns off
+//Bit 30:16 DP on counter
+//Bit 15 0: vd_format doesnt have onoff mode, 1: vd format has onoff mode
+//Bit 14:0 DP off counter
+#define GE2D_DP_ONOFF_CTRL ((0x00d3 << 2) + 0xff040000)
+//Because there are many coefficients used in the vertical filter and horizontal filters,
+//indirect access the coefficients of vertical filter and horizontal filter is used.
+//For vertical filter, there are 33x4 coefficients
+//For horizontal filter, there are 33x4 coefficients
+//Bit 15 index increment, if bit9 == 1 then (0: index increase 1, 1: index increase 2) else (index increase 2)
+//Bit 14 1: read coef through cbus enable, just for debug purpose in case when we wanna check the coef in ram in correct or not
+//Bit 9 if true, use 9bit resolution coef, other use 8bit resolution coef
+//Bit 8 type of index, 0: vertical coef
+// 1: horizontal coef
+//Bit 6:0 coef index
+#define GE2D_SCALE_COEF_IDX ((0x00d4 << 2) + 0xff040000)
+//coefficients for vertical filter and horizontal filter
+#define GE2D_SCALE_COEF ((0x00d5 << 2) + 0xff040000)
+//Bit 24 src2 alpha fill mode: together with GE2D_GEN_CTRL0[4](fill_mode), define what alpha values are used
+// for the area outside the clipping window. As below:
+// fill_mode=0, alpha_fill_mode=0 : use inner alpha, (or default_alpha if src data have no alpha values);
+// fill_mode=0, alpha_fill_mode=1 : use outside_alpha;
+// fill_mode=1, alpha_fill_mode=0 : use default_alpha;
+// fill_mode=1, alpha_fill_mode=1 : use outside_alpha.
+//Bit 23:16 src2 outside alpha
+//Bit 8 src1 alpha fill mode, refer to src2 alpha fill mode above.
+//Bit 7:0 src1 outside alpha
+#define GE2D_SRC_OUTSIDE_ALPHA ((0x00d6 << 2) + 0xff040000)
+//Bit 31 antiflick enable
+//Bit 24 1: alpha value for the first line use repeated alpha, 0: use bit 23:16 as the first line alpha
+//Bit 23:16 register value for the first line alpha when bit 24 is 1
+//Bit 8 1: alpha value for the last line use repeated alpha, 0: use bit 7:0 as the last line alpha
+//Bit 7:0 register value for the last line alpha when bit 8 is 1
+#define GE2D_ANTIFLICK_CTRL0 ((0x00d8 << 2) + 0xff040000)
+//Bit 25, rgb_sel, 1: antiflick RGBA, 0: antiflick YCbCrA
+//Bit 24, cbcr_en, 1: also filter cbcr in case of antiflicking YCbCrA, 0: no filter on cbcr in case of antiflicking YCbCrA
+//Bit 23:16, R mult coef for converting RGB to Y
+//Bit 15:8, G mult coef for converting RGB to Y
+//Bit 7:0, B mult coef for converting RGB to Y
+//Y = (R * y_r + G * y_g + B * y_b) / 256
+#define GE2D_ANTIFLICK_CTRL1 ((0x00d9 << 2) + 0xff040000)
+//Bit 31:24, Y threhold1, when 0<Y<=th1, use filter0;
+//Bit 23:16, color antiflick filter0 n3
+//Bit 15:8, color antiflick filter0 n2
+//Bit 7:0, color antiflick filter0 n1
+//Y = (line_up * n1 + line_center * n2 + line_dn * n3) / 128
+#define GE2D_ANTIFLICK_COLOR_FILT0 ((0x00da << 2) + 0xff040000)
+//Bit 31:24, Y threhold2, when th1<Y<=th2, use filter1;
+//Bit 23:16, color antiflick filter1 n3
+//Bit 15:8, color antiflick filter1 n2
+//Bit 7:0, color antiflick filter1 n1
+#define GE2D_ANTIFLICK_COLOR_FILT1 ((0x00db << 2) + 0xff040000)
+//Bit 31:24, Y threhold3, when th2<Y<=th3, use filter2; Y>th3, use filter3
+//Bit 23:16, color antiflick filter2 n3
+//Bit 15:8, color antiflick filter2 n2
+//Bit 7:0, color antiflick filter2 n1
+#define GE2D_ANTIFLICK_COLOR_FILT2 ((0x00dc << 2) + 0xff040000)
+//Bit 23:16, color antiflick filter3 n3
+//Bit 15:8, color antiflick filter3 n2
+//Bit 7:0, color antiflick filter3 n1
+#define GE2D_ANTIFLICK_COLOR_FILT3 ((0x00dd << 2) + 0xff040000)
+//Bit 31:24, Alpha threhold1, when 0<Alpha<=th1, use filter0;
+//Bit 23:16, Alpha antiflick filter0 n3
+//Bit 15:8, Alpha antiflick filter0 n2
+//Bit 7:0, Alpha antiflick filter0 n1
+//Alpha = (line_up * n1 + line_center * n2 + line_dn * n3) / 128
+#define GE2D_ANTIFLICK_ALPHA_FILT0 ((0x00de << 2) + 0xff040000)
+//Bit 31:24, Alpha threhold2, when th1<Alpha<=th2, use filter1;
+//Bit 23:16, Alpha antiflick filter1 n3
+//Bit 15:8, Alpha antiflick filter1 n2
+//Bit 7:0, Alpha antiflick filter1 n1
+#define GE2D_ANTIFLICK_ALPHA_FILT1 ((0x00df << 2) + 0xff040000)
+//Bit 31:24, Alpha threhold3, when th2<Alpha<=th3, use filter2; Alpha>th3, use filter3
+//Bit 23:16, Alpha antiflick filter2 n3
+//Bit 15:8, Alpha antiflick filter2 n2
+//Bit 7:0, Alpha antiflick filter2 n1
+#define GE2D_ANTIFLICK_ALPHA_FILT2 ((0x00e0 << 2) + 0xff040000)
+//Bit 23:16, Alpha antiflick filter3 n3
+//Bit 15:8, Alpha antiflick filter3 n2
+//Bit 7:0, Alpha antiflick filter3 n1
+#define GE2D_ANTIFLICK_ALPHA_FILT3 ((0x00e1 << 2) + 0xff040000)
+//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset)
+//Bit 30:22 din_offset (signed data)
+//Bit 21:14 map_coef (unsigned data)
+//Bit 13:10 map_sr (unsigned data)
+//Bit 9:1 dout_offset (signed data)
+//Bit 0 enable
+#define GE2D_SRC1_RANGE_MAP_Y_CTRL ((0x00e3 << 2) + 0xff040000)
+//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset)
+//Bit 30:22 din_offset (signed data)
+//Bit 21:14 map_coef (unsigned data)
+//Bit 13:10 map_sr (unsigned data)
+//Bit 9:1 dout_offset (signed data)
+//Bit 0 enable
+#define GE2D_SRC1_RANGE_MAP_CB_CTRL ((0x00e4 << 2) + 0xff040000)
+//dout = clipto_0_255(((din + din_offset) * map_coef + ((1 << (map_sr - 1))) >> map_sr + dout_offset)
+//Bit 30:22 din_offset (signed data)
+//Bit 21:14 map_coef (unsigned data)
+//Bit 13:10 map_sr (unsigned data)
+//Bit 9:1 dout_offset (signed data)
+//Bit 0 enable
+#define GE2D_SRC1_RANGE_MAP_CR_CTRL ((0x00e5 << 2) + 0xff040000)
+//Bit 21:16 src1 prearbitor burst number
+//Bit 13:8 src2 prearbitor burst number
+//Bit 5:0 dst prearbitor burst number
+#define GE2D_ARB_BURST_NUM ((0x00e6 << 2) + 0xff040000)
+//each 6bit ID, high 4bit are thread ID, low 2bits are the token
+//Bit 21:16 src1 ID
+//Bit 13:8 src2 ID
+//Bit 5:0 dst ID
+#define GE2D_TID_TOKEN ((0x00e7 << 2) + 0xff040000)
+//Bit 31:28 dst2_bytemask_val. 1-bit mask for each byte (8-bit). Applicable only if both dst_bitmask_en=1 and dst_bytemask_only=1.
+//Bit 27:26, dst2 picture struct, 00: frame, 10:top, 11: bottom
+//Bit 25:24, dst2 8bit mode component selection,
+// 00: select Y(R), 01: Cb(G), 10: Cr(B), 11: Alpha
+//Bit 22:19 dst2 color_map
+// dst2_format=0 : output 8-bit;
+// dst2_format=1, dst2_color_map=1: output 16-bit YCbCr 655;
+// dst2_format=1, dst2_color_map=2: output 16-bit YCbCr 844;
+// dst2_format=1, dst2_color_map=3: output 16-bit YCbCrA 6442;
+// dst2_format=1, dst2_color_map=4: output 16-bit YCbCrA 4444;
+// dst2_format=1, dst2_color_map=5: output 16-bit YCbCr 565;
+// dst2_format=1, dst2_color_map=6: output 16-bit AYCbCr 4444;
+// dst2_format=1, dst2_color_map=7: output 16-bit AYCbCr 1555;
+// dst2_format=1, dst2_color_map=8: output 16-bit YCbCrA 4642;
+// dst2_format=1, dst2_color_map=9: output 16-bit CbCr 88;
+// dst2_format=1, dst2_color_map=10:output 16-bit CrCb 88;
+// dst2_format=2, dst2_color_map=0: output 24-bit YCbCr 888;
+// dst2_format=2, dst2_color_map=1: output 24-bit YCbCrA 5658;
+// dst2_format=2, dst2_color_map=2: output 24-bit AYCbCr 8565;
+// dst2_format=2, dst2_color_map=3: output 24-bit YCbCrA 6666;
+// dst2_format=2, dst2_color_map=4: output 24-bit AYCbCr 6666;
+// dst2_format=2, dst2_color_map=5: output 24-bit CrCbY 888;
+// dst2_format=3, dst2_color_map=0: output 32-bit YCbCrA 8888;
+// dst2_format=3, dst2_color_map=1: output 32-bit AYCbCr 8888;
+// dst2_format=3, dst2_color_map=2: output 32-bit ACrCbY 8888;
+// dst2_format=3, dst2_color_map=3: output 32-bit CrCbYA 8888.
+//Bit 17:16 dst2_format, 00: 8bit, 01:16bit, 10:24bit, 11: 32bit
+//Bit 15 reserved
+//Bit 14 dst2_color_round_mode, 0: truncate, 1: + 0.5 rounding
+//Bit 13:12, dst2_x_discard_mode. 00: no discard; 10=discard even x; 11=discard odd x. Note: x is post reverse/rotation.
+//Bit 11:10, dst2_y_discard_mode. 00: no discard; 10=discard even y; 11=discard odd y. Note: y is post reverse/rotation.
+//Bit 9 reserved
+//Bit 8, dst2_enable. 0: disable dst2 (default); 1=enable dst2.
+//Bit 7: 6 reserved
+//Bit 5: 4, dst1_x_discard_mode. 00: no discard; 10=discard even x; 11=discard odd x. Note: x is post reverse/rotation.
+//Bit 3: 2, dst1_y_discard_mode. 00: no discard; 10=discard even y; 11=discard odd y. Note: y is post reverse/rotation.
+//Bit 1 reserved
+//Bit 0, dst1_enable. 0: disable dst1; 1=enable dst1 (default).
+#define GE2D_GEN_CTRL3 ((0x00e8 << 2) + 0xff040000)
+//Read only
+// Bit 13:0 ge2d_dst2_status, for debug only
+#define GE2D_STATUS2 ((0x00e9 << 2) + 0xff040000)
+//Bit 27:26 src1 Y fifo size control, 00: 512, 01: 256, 10: 128 11: 96
+//Bit 25:24 src2 fifo size control, 00: 512, 01: 256, 10: 128 11: 96
+//Bit 23:22 dst1 fifo size control, 00: 512, 01: 256, 10: 128 11: 64
+//Bit 21:20 dst2 fifo size control, 00: 512, 01: 256, 10: 128 11: 64
+//Bit 19:18, dst1 fifo burst control, 00: 24x64, 01: 32x64, 10: 48x64, 11:64x64
+//Bit 17:16, dst2 fifo burst control, 00: 24x64, 01: 32x64, 10: 48x64, 11:64x64
+//Bit 15:1, top_wrap_ctrl
+//bit 0, if true, disable bug fix about the dp_out_done/scale_out_done(test1823) hang issue when scaling down ratio is high.
+#define GE2D_GEN_CTRL4 ((0x00ea << 2) + 0xff040000)
+#define GE2D_GCLK_CTRL0 ((0x00ef << 2) + 0xff040000)
+#define GE2D_GCLK_CTRL1 ((0x00f0 << 2) + 0xff040000)
+#define GE2D_GEN_CTRL5 ((0x00f1 << 2) + 0xff040000)
+#define GE2D_DST1_BADDR_CTRL ((0x00f2 << 2) + 0xff040000)
+//Bit 31:0, dst1 base address in 64bits
+#define GE2D_DST1_STRIDE_CTRL ((0x00f3 << 2) + 0xff040000)
+//Bit 19:0, dst1 stride size in 64bits
+#define GE2D_DST2_BADDR_CTRL ((0x00f4 << 2) + 0xff040000)
+//Bit 31:0, dst1 base address in 64bits
+#define GE2D_DST2_STRIDE_CTRL ((0x00f5 << 2) + 0xff040000)
+//Bit 19:0, dst1 stride size in 64bits
+#define GE2D_SRC1_BADDR_CTRL_Y ((0x00f6 << 2) + 0xff040000)
+//Bit 31:0, src1 base address in 64bits
+#define GE2D_SRC1_STRIDE_CTRL_Y ((0x00f7 << 2) + 0xff040000)
+//Bit 19:0, src1 stride size in 64bits
+#define GE2D_SRC1_BADDR_CTRL_CB ((0x00f8 << 2) + 0xff040000)
+//Bit 31:0, src1 base address in 64bits
+#define GE2D_SRC1_STRIDE_CTRL_CB ((0x00f9 << 2) + 0xff040000)
+//Bit 19:0, src1 stride size in 64bits
+#define GE2D_SRC1_BADDR_CTRL_CR ((0x00fa << 2) + 0xff040000)
+//Bit 31:0, src1 base address in 64bits
+#define GE2D_SRC1_STRIDE_CTRL_CR ((0x00fb << 2) + 0xff040000)
+//Bit 19:0, src1 stride size in 64bits
+#define GE2D_SRC2_BADDR_CTRL ((0x00fc << 2) + 0xff040000)
+//Bit 31:0, src2 base address in 64bits
+#define GE2D_SRC2_STRIDE_CTRL ((0x00fd << 2) + 0xff040000)
+//Bit 19:0, src2 stride size in 64bits
+//
+//
+//Bit 28:20, pre_offset0
+//Bit 18:10, pre_offset1
+//Bit 8:0, pre_offset2
+#define GE2D_MATRIX2_PRE_OFFSET ((0x0090 << 2) + 0xff040000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define GE2D_MATRIX2_COEF00_01 ((0x0091 << 2) + 0xff040000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define GE2D_MATRIX2_COEF02_10 ((0x0092 << 2) + 0xff040000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define GE2D_MATRIX2_COEF11_12 ((0x0093 << 2) + 0xff040000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define GE2D_MATRIX2_COEF20_21 ((0x0094 << 2) + 0xff040000)
+//Bit 28:16 coef22
+//Bit 7 input y/cb/cr saturation enable
+//Bit 0 conversion matrix enable
+#define GE2D_MATRIX2_COEF22_CTRL ((0x0095 << 2) + 0xff040000)
+//Bit 28:20, offset0
+//Bit 18:10, offset1
+//Bit 8:0, offset2
+#define GE2D_MATRIX2_OFFSET ((0x0096 << 2) + 0xff040000)
+//Bit 19:0, src2 stride size in 64bits
+//
+//
+//Bit 28:20, pre_offset0
+//Bit 18:10, pre_offset1
+//Bit 8:0, pre_offset2
+#define GE2D_MATRIX3_PRE_OFFSET ((0x0097 << 2) + 0xff040000)
+//Bit 28:16 coef00
+//Bit 12:0 coef01
+#define GE2D_MATRIX3_COEF00_01 ((0x0098 << 2) + 0xff040000)
+//Bit 28:16 coef02
+//Bit 12:0 coef10
+#define GE2D_MATRIX3_COEF02_10 ((0x0099 << 2) + 0xff040000)
+//Bit 28:16 coef11
+//Bit 12:0 coef12
+#define GE2D_MATRIX3_COEF11_12 ((0x009a << 2) + 0xff040000)
+//Bit 28:16 coef20
+//Bit 12:0 coef21
+#define GE2D_MATRIX3_COEF20_21 ((0x009b << 2) + 0xff040000)
+//Bit 28:16 coef22
+//Bit 7 input y/cb/cr saturation enable
+//Bit 0 conversion matrix enable
+#define GE2D_MATRIX3_COEF22_CTRL ((0x009c << 2) + 0xff040000)
+//Bit 28:20, offset0
+//Bit 18:10, offset1
+//Bit 8:0, offset2
+#define GE2D_MATRIX3_OFFSET ((0x009d << 2) + 0xff040000)
+// synopsys translate_off
+// synopsys translate_on
+//
+// Closing file: ./ge2d_regs.h
+//
+//
+// Reading file: ./parser_regs.h
+//
+//
+//***************************************************************************
+// Title: parser.h
+//
+// Author: chong.gu
+//
+// Created: 17:15:11 06/08/2019
+//
+// Description:
+//
+// Note:
+//
+// History:
+//
+//***************************************************************************
+//-----------------------------------------------------------
+// PARSER
+//-----------------------------------------------------------
+// -----------------------------------------------
+// REG_BASE: PARSER_PCBUS_BASE = 0x38
+// -----------------------------------------------
+// bit 31:8 -- es_pack_size
+// bit 7:6 -- es_type 00-Video, 01-Audio, 10-Subtitle
+// bit 5 -- es_write
+// bit 4 -- es_passthrough
+// bit 3 -- insert_before_es_write
+// bit 2 -- discard_cmd
+// bit 1 -- search_cmd
+// bit 0 -- Parser Busy
+#define PARSER_CONTROL ((0x3860 << 2) + 0xfdf00000)
+// Write
+// bit 31:0 begin address for parser fetch
+// Read
+// 32 bit current fetch address
+#define PARSER_FETCH_ADDR ((0x3861 << 2) + 0xfdf00000)
+// Write
+// bit 31 circle buffer indicator
+// bit 30 check_buffer_stop_addr
+// bit 29:27 fetch endian
+// bit 26:0 buffer size ( Bytes )
+// Special command:
+// when bit 26:0 == 27'h0
+// then bit 29 -- stream_passthrough_enable
+// bit 28:27 -- stream_passthrough_type
+// Read
+// 6:5 cmd_rd_ptr
+// 4:3 cmd_wr_ptr
+// 2:0 cmd_number
+#define PARSER_FETCH_CMD ((0x3862 << 2) + 0xfdf00000)
+// 31:0 stop_fetch_addr
+#define PARSER_FETCH_STOP_ADDR ((0x3863 << 2) + 0xfdf00000)
+// 31:0 stop_fetch_addr - current_write_addr // read only
+#define PARSER_FETCH_LEVEL ((0x3864 << 2) + 0xfdf00000)
+// bit 31 - fetch_dma_urgent
+// bit 30 - stream_dma_urgent
+// bit 29 - force_pfifo_ren
+// bit 28 - pfifo_peak_enable
+// bit 27 - enable_free_clk_parser_reg
+// bit 26 -
+// bit 25:24 - parser_src_sel (00 - fetch, 01 - aux1, 10 - aux2 11 - aux3)
+// bit 23:16 - pfifo_empty_count
+// bit 15:12 - max_es_write_cycle (x16x64bits)
+// 11:10 - start code width ( 00-8bits, 01-16bits, 10-24bits, 11-32bits )
+// 9:8 - pfifo data access width ( 00-8bits, 01-16bits, 10-24bits, 11-32bits )
+// 7:0 - empty room for fetch data ( max_fetch_cycle ) x64 bits
+#define PARSER_CONFIG ((0x3865 << 2) + 0xfdf00000)
+// bit 24:16 -- pfifo_level
+// bit 9:0 -- point to byte address
+#define PFIFO_WR_PTR ((0x3866 << 2) + 0xfdf00000)
+// bit 9:0 -- point to byte address
+#define PFIFO_RD_PTR ((0x3867 << 2) + 0xfdf00000)
+// bit 31:0 -- 8/16/24/32 bits data acording to pfifo_data_width
+#define PFIFO_DATA ((0x3868 << 2) + 0xfdf00000)
+// bit 31:0 -- parser search pattern
+#define PARSER_SEARCH_PATTERN ((0x3869 << 2) + 0xfdf00000)
+// bit 31:0 -- parser search mask ( 0 - disable bit match test )
+#define PARSER_SEARCH_MASK ((0x386a << 2) + 0xfdf00000)
+// bit 31:16 -- parser_int_disable_count
+// bit 15:8 -- Parser interrupt enable for host cpu
+// bit 7:0 -- Parser interrupt enable for Amrisc
+#define PARSER_INT_ENABLE ((0x386b << 2) + 0xfdf00000)
+// Bit 7 -- fetch_cmd_finished
+// Bit 6:5 -- reserved
+// Bit 4 -- parse finished
+// Bit 3 -- discard finished
+// Bit 2 -- insert zero finished
+// Bit 1 -- Action Finished Except Search Start Code
+// Bit 0 -- Search match interrupt (StartCode found)
+// Read 7:0 int status
+// Write will clear (bit based)
+#define PARSER_INT_STATUS ((0x386c << 2) + 0xfdf00000)
+// 15 - SCR_32_READ_OUT (Read Only)
+// 14 - SCR_32_data_valid
+// 13 - SCR_32_data
+// 12 - SCR_count_en
+// 11:0 - SCR90K_DIV
+#define PARSER_SCR_CTL ((0x386d << 2) + 0xfdf00000)
+// bit 31:0 SCR value
+#define PARSER_SCR ((0x386e << 2) + 0xfdf00000)
+// bit 31:24 -- insert_loop_number
+// bit 23:21 --
+// bit 20:16 -- insert_byte_number
+// bit 15:0 -- discard number
+#define PARSER_PARAMETER ((0x386f << 2) + 0xfdf00000)
+// bit 31:0 -- insert data // write only
+// write to PARSER_CONTROL will reset the write position
+// continous write to this address can write upto 16 bytes
+#define PARSER_INSERT_DATA ((0x3870 << 2) + 0xfdf00000)
+// Bit 31:24 -- Reserved Stream_ID
+// Bit 23:16 -- Sub Stream_ID
+// Bit 15:8 -- Audio Stream_ID
+// Bit 7:0 -- Video Stream_ID
+#define VAS_STREAM_ID ((0x3871 << 2) + 0xfdf00000)
+// Bit 31:0 -- VIDEO_DTS
+#define VIDEO_DTS ((0x3872 << 2) + 0xfdf00000)
+// Bit 31:0 -- VIDEO_PTS
+#define VIDEO_PTS ((0x3873 << 2) + 0xfdf00000)
+// Bit 31:0 -- VIDEO_PTS_DTS_WR_PTR
+#define VIDEO_PTS_DTS_WR_PTR ((0x3874 << 2) + 0xfdf00000)
+// Bit 31:0 -- AUDIO_PTS
+#define AUDIO_PTS ((0x3875 << 2) + 0xfdf00000)
+// Bit 31:0 -- AUDIO_PTS_WR_PTR
+#define AUDIO_PTS_WR_PTR ((0x3876 << 2) + 0xfdf00000)
+// bit 31:20 -- stream_es_count ( Read Only)
+// bit 19 -- req_pending ( parser ddr_A_fifo ) (Read Only)
+// bit 18 -- stream_es_passthrough_enable
+// bit 17:16 -- stream_es_passthrough_type
+// bit 15:13 -- VIDEO2 Ees_write Endian
+// bit 12 -- VIDEO2 using manual read point
+// bit 11:9 -- SUB Ees_write Endian
+// bit 8 -- SUB using manual read point
+// bit 7:5 -- AUDIO Ees_write Endian
+// bit 4 -- AUDIO using manual read point
+// bit 3:1 -- VIDEO Ees_write Endian
+// bit 0 -- VIDEO using manual read point
+#define PARSER_ES_CONTROL ((0x3877 << 2) + 0xfdf00000)
+// Bit 31:0 PFIFO_MONITOR
+#define PFIFO_MONITOR ((0x3878 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_VIDEO DDR Interface
+// --------------------------------------------
+// The PARSER_VIDEO start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_VIDEO_START_PTR ((0x3880 << 2) + 0xfdf00000)
+#define PARSER_VIDEO_END_PTR ((0x3881 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_VIDEO Buffer Level Manager
+// --------------------------------------------
+#define PARSER_VIDEO_WP ((0x3882 << 2) + 0xfdf00000)
+#define PARSER_VIDEO_RP ((0x3883 << 2) + 0xfdf00000)
+#define PARSER_VIDEO_HOLE ((0x3884 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_AUDIO DDR Interface
+// --------------------------------------------
+// The PARSER_AUDIO start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_AUDIO_START_PTR ((0x3885 << 2) + 0xfdf00000)
+#define PARSER_AUDIO_END_PTR ((0x3886 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_AUDIO Buffer Level Manager
+// --------------------------------------------
+#define PARSER_AUDIO_WP ((0x3887 << 2) + 0xfdf00000)
+#define PARSER_AUDIO_RP ((0x3888 << 2) + 0xfdf00000)
+#define PARSER_AUDIO_HOLE ((0x3889 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_SUB DDR Interface
+// --------------------------------------------
+// The PARSER_SUB start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_SUB_START_PTR ((0x388a << 2) + 0xfdf00000)
+#define PARSER_SUB_END_PTR ((0x388b << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_SUB Buffer Level Manager
+// --------------------------------------------
+#define PARSER_SUB_WP ((0x388c << 2) + 0xfdf00000)
+#define PARSER_SUB_RP ((0x388d << 2) + 0xfdf00000)
+#define PARSER_SUB_HOLE ((0x388e << 2) + 0xfdf00000)
+// Bit[31] dma_busy
+// Bit[30] cur_fetch_or_es_write
+// Bit[29:28] reserved
+// Bit[27:24] fetch_status
+// Bit[23:0] buffer_cycles_left
+#define PARSER_FETCH_INFO ((0x388f << 2) + 0xfdf00000)
+// Bit[31:28] ctl_status
+// Bit[27:24] insert_byte_offset
+// Bit[23:0] es_pack_left_cycle
+#define PARSER_STATUS ((0x3890 << 2) + 0xfdf00000)
+// Bit [31:16] AUDIO_wrap_count
+// Bit [15:0] VIDEO_wrap_count
+#define PARSER_AV_WRAP_COUNT ((0x3891 << 2) + 0xfdf00000)
+// bit[29:24] A_brst_num_parser
+// bit[21:16] A_id_parser
+// bit[11:0] wrrsp_count_parser
+#define WRRSP_PARSER ((0x3892 << 2) + 0xfdf00000)
+// `define CSS_cmd 12'h200 // address of css command and indirect register
+// `define CSS_cntl 12'h201 // css control register
+// `define CSS_data 12'h202 // indirect register
+// `define CSS_id1_data 12'h203 // ID data for the first and second bytes
+// `define CSS_id2_data 12'h204 // ID data for the third and fourth bytes
+//CPPM registers
+// `define CPPM_IFIFO_CTRL 12'h210 //CPPM input FIFO control
+// `define CPPM_C2BC_KEY 12'h211 //CPPM C2 Block Cipher Key register
+// `define CPPM_C2BC_DIN 12'h212 //CPPM C2 Block Cipher data input register
+// `define CPPM_C2BC_DOUT 12'h213 //CPPM C2 Block Cipher data result register
+// `define CPPM_CMD 12'h214 //CPPM command and control register
+// `define CPPM_CTRL_STATUS 12'h215 //CPPM control status, mainly for debug
+// `define CPPM_IFIFO_DATA 12'h216 //CPPM input FIFO data pop port, just for debug
+// --------------------------------------------
+// PARSER_VIDEO2 DDR Interface
+// --------------------------------------------
+// The PARSER_VIDEO2 start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_VIDEO2_START_PTR ((0x3893 << 2) + 0xfdf00000)
+#define PARSER_VIDEO2_END_PTR ((0x3894 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_VIDEO2 Buffer Level Manager
+// --------------------------------------------
+#define PARSER_VIDEO2_WP ((0x3895 << 2) + 0xfdf00000)
+#define PARSER_VIDEO2_RP ((0x3896 << 2) + 0xfdf00000)
+#define PARSER_VIDEO2_HOLE ((0x3897 << 2) + 0xfdf00000)
+// Bit [31:16] AUDIO_wrap_count
+// Bit [15:0] VIDEO2_wrap_count
+#define PARSER_AV2_WRAP_COUNT ((0x3898 << 2) + 0xfdf00000)
+//-----------------------------------------------------------
+// PARSER_B
+//-----------------------------------------------------------
+// -----------------------------------------------
+// REG_BASE: PARSER_B_PCBUS_BASE = 0x11
+// -----------------------------------------------
+#define PARSER_B_PARSER_CONTROL ((0x1160 << 2) + 0xfdf00000)
+// Write
+// bit 31:0 begin address for parser fetch
+// Read
+// 32 bit current fetch address
+#define PARSER_B_PARSER_FETCH_ADDR ((0x1161 << 2) + 0xfdf00000)
+// Write
+// bit 31 circle buffer indicator
+// bit 30 check_buffer_stop_addr
+// bit 29:27 fetch endian
+// bit 26:0 buffer size ( Bytes )
+// Special command:
+// when bit 26:0 == 27'h0
+// then bit 29 -- stream_passthrough_enable
+// bit 28:27 -- stream_passthrough_type
+// Read
+// 6:5 cmd_rd_ptr
+// 4:3 cmd_wr_ptr
+// 2:0 cmd_number
+#define PARSER_B_PARSER_FETCH_CMD ((0x1162 << 2) + 0xfdf00000)
+// 31:0 stop_fetch_addr
+#define PARSER_B_PARSER_FETCH_STOP_ADDR ((0x1163 << 2) + 0xfdf00000)
+// 31:0 stop_fetch_addr - current_write_addr // read only
+#define PARSER_B_PARSER_FETCH_LEVEL ((0x1164 << 2) + 0xfdf00000)
+// bit 31 - fetch_dma_urgent
+// bit 30 - stream_dma_urgent
+// bit 29 - force_pfifo_ren
+// bit 28 - pfifo_peak_enable
+// bit 27 - enable_free_clk_parser_reg
+// bit 26 -
+// bit 25:24 - parser_src_sel (00 - fetch, 01 - aux1, 10 - aux2 11 - aux3)
+// bit 23:16 - pfifo_empty_count
+// bit 15:12 - max_es_write_cycle (x16x64bits)
+// 11:10 - start code width ( 00-8bits, 01-16bits, 10-24bits, 11-32bits )
+// 9:8 - pfifo data access width ( 00-8bits, 01-16bits, 10-24bits, 11-32bits )
+// 7:0 - empty room for fetch data ( max_fetch_cycle ) x64 bits
+#define PARSER_B_PARSER_CONFIG ((0x1165 << 2) + 0xfdf00000)
+// bit 24:16 -- pfifo_level
+// bit 9:0 -- point to byte address
+#define PARSER_B_PFIFO_WR_PTR ((0x1166 << 2) + 0xfdf00000)
+// bit 9:0 -- point to byte address
+#define PARSER_B_PFIFO_RD_PTR ((0x1167 << 2) + 0xfdf00000)
+// bit 31:0 -- 8/16/24/32 bits data acording to pfifo_data_width
+#define PARSER_B_PFIFO_DATA ((0x1168 << 2) + 0xfdf00000)
+// bit 31:0 -- parser search pattern
+#define PARSER_B_PARSER_SEARCH_PATTERN ((0x1169 << 2) + 0xfdf00000)
+// bit 31:0 -- parser search mask ( 0 - disable bit match test )
+#define PARSER_B_PARSER_SEARCH_MASK ((0x116a << 2) + 0xfdf00000)
+// bit 31:16 -- parser_int_disable_count
+// bit 15:8 -- Parser interrupt enable for host cpu
+// bit 7:0 -- Parser interrupt enable for Amrisc
+#define PARSER_B_PARSER_INT_ENABLE ((0x116b << 2) + 0xfdf00000)
+// Bit 7 -- fetch_cmd_finished
+// Bit 6:5 -- reserved
+// Bit 4 -- parse finished
+// Bit 3 -- discard finished
+// Bit 2 -- insert zero finished
+// Bit 1 -- Action Finished Except Search Start Code
+// Bit 0 -- Search match interrupt (StartCode found)
+// Read 7:0 int status
+// Write will clear (bit based)
+#define PARSER_B_PARSER_INT_STATUS ((0x116c << 2) + 0xfdf00000)
+// 15 - SCR_32_READ_OUT (Read Only)
+// 14 - SCR_32_data_valid
+// 13 - SCR_32_data
+// 12 - SCR_count_en
+// 11:0 - SCR90K_DIV
+#define PARSER_B_PARSER_SCR_CTL ((0x116d << 2) + 0xfdf00000)
+// bit 31:0 SCR value
+#define PARSER_B_PARSER_SCR ((0x116e << 2) + 0xfdf00000)
+// bit 31:24 -- insert_loop_number
+// bit 23:21 --
+// bit 20:16 -- insert_byte_number
+// bit 15:0 -- discard number
+#define PARSER_B_PARSER_PARAMETER ((0x116f << 2) + 0xfdf00000)
+// bit 31:0 -- insert data // write only
+// write to PARSER_CONTROL will reset the write position
+// continous write to this address can write upto 16 bytes
+#define PARSER_B_PARSER_INSERT_DATA ((0x1170 << 2) + 0xfdf00000)
+// Bit 31:24 -- Reserved Stream_ID
+// Bit 23:16 -- Sub Stream_ID
+// Bit 15:8 -- Audio Stream_ID
+// Bit 7:0 -- Video Stream_ID
+#define PARSER_B_VAS_STREAM_ID ((0x1171 << 2) + 0xfdf00000)
+// Bit 31:0 -- VIDEO_DTS
+#define PARSER_B_VIDEO_DTS ((0x1172 << 2) + 0xfdf00000)
+// Bit 31:0 -- VIDEO_PTS
+#define PARSER_B_VIDEO_PTS ((0x1173 << 2) + 0xfdf00000)
+// Bit 31:0 -- VIDEO_PTS_DTS_WR_PTR
+#define PARSER_B_VIDEO_PTS_DTS_WR_PTR ((0x1174 << 2) + 0xfdf00000)
+// Bit 31:0 -- AUDIO_PTS
+#define PARSER_B_AUDIO_PTS ((0x1175 << 2) + 0xfdf00000)
+// Bit 31:0 -- AUDIO_PTS_WR_PTR
+#define PARSER_B_AUDIO_PTS_WR_PTR ((0x1176 << 2) + 0xfdf00000)
+// bit 31:20 -- stream_es_count ( Read Only)
+// bit 19 -- req_pending ( parser ddr_A_fifo ) (Read Only)
+// bit 18 -- stream_es_passthrough_enable
+// bit 17:16 -- stream_es_passthrough_type
+// bit 15:13 -- VIDEO2 Ees_write Endian
+// bit 12 -- VIDEO2 using manual read point
+// bit 11:9 -- SUB Ees_write Endian
+// bit 8 -- SUB using manual read point
+// bit 7:5 -- AUDIO Ees_write Endian
+// bit 4 -- AUDIO using manual read point
+// bit 3:1 -- VIDEO Ees_write Endian
+// bit 0 -- VIDEO using manual read point
+#define PARSER_B_PARSER_ES_CONTROL ((0x1177 << 2) + 0xfdf00000)
+// Bit 31:0 PFIFO_MONITOR
+#define PARSER_B_PFIFO_MONITOR ((0x1178 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_VIDEO DDR Interface
+// --------------------------------------------
+// The PARSER_VIDEO start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_B_PARSER_VIDEO_START_PTR ((0x1180 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_VIDEO_END_PTR ((0x1181 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_VIDEO Buffer Level Manager
+// --------------------------------------------
+#define PARSER_B_PARSER_VIDEO_WP ((0x1182 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_VIDEO_RP ((0x1183 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_VIDEO_HOLE ((0x1184 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_AUDIO DDR Interface
+// --------------------------------------------
+// The PARSER_AUDIO start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_B_PARSER_AUDIO_START_PTR ((0x1185 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_AUDIO_END_PTR ((0x1186 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_AUDIO Buffer Level Manager
+// --------------------------------------------
+#define PARSER_B_PARSER_AUDIO_WP ((0x1187 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_AUDIO_RP ((0x1188 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_AUDIO_HOLE ((0x1189 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_SUB DDR Interface
+// --------------------------------------------
+// The PARSER_SUB start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_B_PARSER_SUB_START_PTR ((0x118a << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_SUB_END_PTR ((0x118b << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_SUB Buffer Level Manager
+// --------------------------------------------
+#define PARSER_B_PARSER_SUB_WP ((0x118c << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_SUB_RP ((0x118d << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_SUB_HOLE ((0x118e << 2) + 0xfdf00000)
+// Bit[31] dma_busy
+// Bit[30] cur_fetch_or_es_write
+// Bit[29:28] reserved
+// Bit[27:24] fetch_status
+// Bit[23:0] buffer_cycles_left
+#define PARSER_B_PARSER_FETCH_INFO ((0x118f << 2) + 0xfdf00000)
+// Bit[31:28] ctl_status
+// Bit[27:24] insert_byte_offset
+// Bit[23:0] es_pack_left_cycle
+#define PARSER_B_PARSER_STATUS ((0x1190 << 2) + 0xfdf00000)
+// Bit [31:16] AUDIO_wrap_count
+// Bit [15:0] VIDEO_wrap_count
+#define PARSER_B_PARSER_AV_WRAP_COUNT ((0x1191 << 2) + 0xfdf00000)
+// bit[29:24] A_brst_num_parser
+// bit[21:16] A_id_parser
+// bit[11:0] wrrsp_count_parser
+#define PARSER_B_WRRSP_PARSER ((0x1192 << 2) + 0xfdf00000)
+// `define CSS_cmd 12'h200 // address of css command and indirect register
+// `define CSS_cntl 12'h201 // css control register
+// `define CSS_data 12'h202 // indirect register
+// `define CSS_id1_data 12'h203 // ID data for the first and second bytes
+// `define CSS_id2_data 12'h204 // ID data for the third and fourth bytes
+//CPPM registers
+// `define CPPM_IFIFO_CTRL 12'h210 //CPPM input FIFO control
+// `define CPPM_C2BC_KEY 12'h211 //CPPM C2 Block Cipher Key register
+// `define CPPM_C2BC_DIN 12'h212 //CPPM C2 Block Cipher data input register
+// `define CPPM_C2BC_DOUT 12'h213 //CPPM C2 Block Cipher data result register
+// `define CPPM_CMD 12'h214 //CPPM command and control register
+// `define CPPM_CTRL_STATUS 12'h215 //CPPM control status, mainly for debug
+// `define CPPM_IFIFO_DATA 12'h216 //CPPM input FIFO data pop port, just for debug
+// --------------------------------------------
+// PARSER_VIDEO2 DDR Interface
+// --------------------------------------------
+// The PARSER_VIDEO2 start pointer into DDR memory is a 32-bit number
+// The Start pointer will automatically be truncated to land on
+// an 8-byte boundary. That is, bits [2:0] = 0;
+#define PARSER_B_PARSER_VIDEO2_START_PTR ((0x1193 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_VIDEO2_END_PTR ((0x1194 << 2) + 0xfdf00000)
+// --------------------------------------------
+// PARSER_VIDEO2 Buffer Level Manager
+// --------------------------------------------
+#define PARSER_B_PARSER_VIDEO2_WP ((0x1195 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_VIDEO2_RP ((0x1196 << 2) + 0xfdf00000)
+#define PARSER_B_PARSER_VIDEO2_HOLE ((0x1197 << 2) + 0xfdf00000)
+// Bit [31:16] AUDIO_wrap_count
+// Bit [15:0] VIDEO2_wrap_count
+#define PARSER_B_PARSER_AV2_WRAP_COUNT ((0x1198 << 2) + 0xfdf00000)
+//
+// Closing file: ./parser_regs.h
+//
+
+#define REG_BASE_VCBUS (0xff000000)
+
+#include "soc_def.h"
+#endif // REGISTER_H
+
diff --git a/arch/arm/include/asm/arch-t7/regs.h b/arch/arm/include/asm/arch-t7/regs.h
new file mode 100644
index 0000000..cfc25ed
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/regs.h
@@ -0,0 +1,58 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AML_REG_H__
+#define __AML_REG_H__
+/*
+ * all used regs
+ */
+/*
+ * ISA_TIMERE use SYSCTRL_TIMERE
+ * WATCHDOG_CNTL use RESETCTRL_WATCHDOG_CTRL0
+ * WATCHDOG_TCNT use RESETCTRL_WATCHDOG_CNT
+ * WATCHDOG_RESET use RESETCTRL_WATCHDOG_CLR
+ */
+#define ISA_TIMERE ((0x0041 << 2) + 0xfe005800)
+#define WATCHDOG_CNTL ((0x0040 << 2) + 0xfe000000)
+#define WATCHDOG_TCNT ((0x0042 << 2) + 0xfe000000)
+#define WATCHDOG_RESET ((0x0043 << 2) + 0xfe000000)
+
+/*
+ * SEC_AO_SEC_GP_CFG0 use SYSCTRL_SEC_STATUS_REG4
+ * AO_SEC_GP_CFG0 use SYSCTRL_SEC_STATUS_REG4
+ * AO_RTI_STATUS_REG3 use SYSCTRL_SEC_STICKY_REG1
+ * AO_SEC_SD_CFG15 use SYSCTRL_SEC_STATUS_REG2
+ */
+//#define SEC_AO_SEC_GP_CFG0 ((0x00c4 << 2) + 0xfe005800)
+#define AO_SEC_GP_CFG0 ((0x00c4 << 2) + 0xfe005800)
+#define AO_RTI_STATUS_REG3 ((0x00e1 << 2) + 0xfe005800)
+//#define AO_SEC_SD_CFG15 ((0x00c2 << 2) + 0xfe005800)
+
+/* PREG_STICKY_REG8 use SYSCTRL_STICKY_REG7
+ * P_AO_SEC_GP_CFG12 use SYSCTRL_DEBUG_REG6
+ * P_AO_SEC_GP_CFG13 use SYSCTRL_DEBUG_REG7
+ */
+#define PREG_STICKY_REG8 ((0x00b7 << 2) + 0xfe005800)
+#define P_AO_SEC_GP_CFG12 (volatile uint32_t *)((0x0096 << 2) + 0xfe005800)
+#define P_AO_SEC_GP_CFG13 (volatile uint32_t *)((0x0097 << 2) + 0xfe005800)
+
+/*
+ * P_AO_RTI_PINMUX_REG0 use PADCTRL_PIN_MUX_REG0
+ * P_AO_TIMEBASE_CNTL1 use CLKTREE_TIMEBASE_CTRL1
+ * AO_UART_WFIFO use UART_B_WFIFO
+ */
+#define P_AO_RTI_PINMUX_REG0 ((0x0000 << 2) + 0xfe000400)
+#define P_AO_TIMEBASE_CNTL1 ((0x0016 << 2) + 0xfe000800)
+#define AO_UART_WFIFO ((0x0000 << 2) + 0xfe002000)
+
+/*
+ * Not AO watch dog
+ */
+#define P_WATCHDOG_CNTL (volatile uint32_t *)(WATCHDOG_CNTL)
+#define P_WATCHDOG_TCNT (volatile uint32_t *)(WATCHDOG_TCNT)
+#define P_WATCHDOG_RESET (volatile uint32_t *)(WATCHDOG_RESET)
+#define P_ISA_TIMERE (volatile uint32_t *)(ISA_TIMERE)
+
+#endif /* __AML_REG_H__ */
diff --git a/arch/arm/include/asm/arch-t7/romboot.h b/arch/arm/include/asm/arch-t7/romboot.h
new file mode 100644
index 0000000..2967fbb
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/romboot.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOOT_ROM_H_
+#define __BOOT_ROM_H_
+#ifndef __ASSEMBLY__
+//#include <stdint.h>
+//uint8_t simple_i2c(uint8_t adr);
+//void spi_pin_mux(void);
+//void spi_init(void);
+//uint32_t spi_read(uint32_t src, uint32_t mem, uint32_t size);
+//void udelay(uint32_t usec);
+//void boot_des_decrypt(uint8_t *ct, uint8_t *pt, uint32_t size);
+
+#endif /* ! __ASSEMBLY__ */
+#include "config.h"
+
+/* Magic number to "boot" up A53 */
+#define AO_SEC_SD_CFG10_CB 0x80000000
+
+/*BOOT device and ddr size*/
+/*31-28: boot device id, 27-24: boot device para, 23-20: reserved*/
+/*19-8: ddr size, 7-0: board revision*/
+//#define P_AO_SEC_GP_CFG0 0xDA100240 //defined in secure_apb.h
+#define AO_SEC_GP_CFG7_W0_BIT 8
+#define AO_SEC_GP_CFG7_W0 0x100
+
+#define BOOT_ID_RESERVED 0
+#define BOOT_ID_EMMC 1
+#define BOOT_ID_NAND 2
+#define BOOT_ID_SPI 3
+#define BOOT_ID_SDCARD 4
+#define BOOT_ID_USB 5
+
+#endif /* __BOOT_ROM_H_ */
diff --git a/arch/arm/include/asm/arch-t7/sd_emmc.h b/arch/arm/include/asm/arch-t7/sd_emmc.h
new file mode 100644
index 0000000..dfa74f7
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/sd_emmc.h
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __SD_EMMC_H__
+#define __SD_EMMC_H__
+
+#include <mmc.h>
+
+#define SDIO_PORT_A 0
+#define SDIO_PORT_B 1
+#define SDIO_PORT_C 2
+
+#define SD_EMMC_CLKSRC_24M 24000000 /* 24 MHz */
+#define SD_EMMC_CLKSRC_DIV2 1000000000 /* 1 GHz */
+
+#define MESON_SD_EMMC_CLOCK 0x00
+#define CLK_MAX_DIV GENMASK(5, 0)
+#define CLK_MAX_SRC GENMASK(7, 6)
+#define Cfg_div 0
+#define Cfg_src 6
+#define Cfg_co_phase 8
+#define Cfg_tx_phase 10
+#define Cfg_rx_phase 12
+#define Cfg_sram_pd 14
+#define Cfg_tx_delay 16
+#define Cfg_rx_delay 22
+#define Cfg_always_on 28
+#define Cfg_irq_sdio_sleep 29
+#define Cfg_irq_sdio_sleep_ds 30
+
+#define MESON_SD_EMMC_DELAY1 0x4
+#define DLY_D0_MASK GENMASK(5, 0)
+#define DLY_D1_MASK GENMASK(11, 6)
+#define DLY_D2_MASK GENMASK(17, 12)
+#define DLY_D3_MASK GENMASK(23, 18)
+#define DLY_D4_MASK GENMASK(31, 24)
+#define Dly_d0 0
+#define Dly_d1 6
+#define Dly_d2 12
+#define Dly_d3 18
+#define Dly_d4 24
+
+#define MESON_SD_EMMC_DELAY2 0x8
+#define DLY_D5_MASK GENMASK(5, 0)
+#define DLY_D6_MASK GENMASK(11, 6)
+#define DLY_D7_MASK GENMASK(17, 12)
+#define DLY_D8_MASK GENMASK(23, 18)
+#define DLY_D9_MASK GENMASK(31, 24)
+#define Dly_d5 0
+#define Dly_d6 6
+#define Dly_d7 12
+#define Dly_d8 18
+#define Dly_d9 24
+
+#define MESON_SD_EMMC_ADJUST 0xC
+#define CALI_SEL_MASK GENMASK(11, 8)
+#define ADJ_DLY_MASK GENMASK(21, 16)
+#define Cfg_cali_sel 8
+#define Cfg_cali_en 12
+#define Cfg_adj_en 13
+#define Cfg_cali_rise 14
+#define Cfg_ds_en 15
+#define Cfg_adj_dly 16
+#define Cfg_adj_auto 22
+#define Cfg_adj_init 23
+
+#define MESON_SD_EMMC_START 0x40
+#define CFG_DESC_INIT BIT(0)
+#define CFG_DESC_BUSY BIT(1)
+#define CFG_DESC_ADDR 2
+
+#define MESON_SD_EMMC_CFG 0x44
+#define CFG_BUS_WIDTH_MASK GENMASK(1, 0)
+#define CFG_BUS_WIDTH_1 0
+#define CFG_BUS_WIDTH_4 1
+#define CFG_BUS_WIDTH_8 2
+#define CFG_DDR BIT(2)
+#define CFG_BL_LEN_MASK GENMASK(7, 4)
+#define CFG_BL_LEN_SHIFT 4
+#define CFG_BL_LEN_512 (9 << 4)
+#define CFG_RESP_TIMEOUT_MASK GENMASK(11, 8)
+#define CFG_RESP_TIMEOUT_256 (8 << 8)
+#define CFG_RC_CC_MASK GENMASK(15, 12)
+#define CFG_RC_CC_16 (4 << 12)
+#define CFG_SDCLK_ALWAYS_ON BIT(18)
+#define CFG_AUTO_CLK BIT(23)
+
+#define MESON_SD_EMMC_STATUS 0x48
+#define STATUS_MASK GENMASK(15, 0)
+#define STATUS_ERR_MASK GENMASK(12, 0)
+#define STATUS_RXD_ERR_MASK GENMASK(7, 0)
+#define STATUS_TXD_ERR BIT(8)
+#define STATUS_DESC_ERR BIT(9)
+#define STATUS_RESP_ERR BIT(10)
+#define STATUS_RESP_TIMEOUT BIT(11)
+#define STATUS_DESC_TIMEOUT BIT(12)
+#define STATUS_END_OF_CHAIN BIT(13)
+
+#define MESON_SD_EMMC_IRQ_EN 0x4c
+
+#define MESON_SD_EMMC_CMD_CFG 0x50
+#define CMD_CFG_LENGTH_MASK GENMASK(8, 0)
+#define CMD_CFG_BLOCK_MODE BIT(9)
+#define CMD_CFG_R1B BIT(10)
+#define CMD_CFG_END_OF_CHAIN BIT(11)
+#define CMD_CFG_TIMEOUT_4S (12 << 12)
+#define CMD_CFG_NO_RESP BIT(16)
+#define CMD_CFG_NO_CMD BIT(17)
+#define CMD_CFG_DATA_IO BIT(18)
+#define CMD_CFG_DATA_WR BIT(19)
+#define CMD_CFG_RESP_NOCRC BIT(20)
+#define CMD_CFG_RESP_128 BIT(21)
+#define CMD_CFG_RESP_NUM BIT(22)
+#define CMD_CFG_DATA_NUM BIT(23)
+#define CMD_CFG_CMD_INDEX_MASK GENMASK(29, 24)
+#define CMD_CFG_CMD_INDEX_SHIFT 24
+#define CMD_CFG_ERR BIT(30)
+#define CMD_CFG_OWNER BIT(31)
+
+#define MESON_SD_EMMC_CMD_ARG 0x54
+#define MESON_SD_EMMC_CMD_DAT 0x58
+#define MESON_SD_EMMC_CMD_RSP 0x5c
+#define MESON_SD_EMMC_CMD_RSP1 0x60
+#define MESON_SD_EMMC_CMD_RSP2 0x64
+#define MESON_SD_EMMC_CMD_RSP3 0x68
+
+#define SD_EMMC_RXD_ERROR (1 << 0)
+#define SD_EMMC_TXD_ERROR (1 << 1)
+#define SD_EMMC_DESC_ERROR (1 << 2)
+#define SD_EMMC_RESP_CRC_ERROR (1 << 3)
+#define SD_EMMC_RESP_TIMEOUT_ERROR (1 << 4)
+#define SD_EMMC_DESC_TIMEOUT_ERROR (1 << 5)
+
+//boot from sd or emmc
+/*this macro of SEC_AO_SEC_GP_CFG0 was defined in ./arch/arm/include/asm/arch-t7/soc_def.h */
+//#define SEC_AO_SEC_GP_CFG0 (SYSCTRL_SEC_STATUS_REG4)
+#endif
diff --git a/arch/arm/include/asm/arch-t7/secure_apb.h b/arch/arm/include/asm/arch-t7/secure_apb.h
new file mode 100644
index 0000000..ff4a0e8
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/secure_apb.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/register.h>
+
+#define DMA_BASE (uint32_t)(0xfe440400)
+
+#define DMA_T0 (uint32_t)(DMA_BASE + 0x00)
+#define DMA_T1 (uint32_t)(DMA_BASE + 0x04)
+#define DMA_T2 (uint32_t)(DMA_BASE + 0x08)
+#define DMA_T3 (uint32_t)(DMA_BASE + 0x0c)
+#define DMA_T4 (uint32_t)(DMA_BASE + 0x10)
+#define DMA_T5 (uint32_t)(DMA_BASE + 0x14)
+#define DMA_STS0 (uint32_t)(DMA_BASE + 0x20)
+#define DMA_STS1 (uint32_t)(DMA_BASE + 0x24)
+#define DMA_STS2 (uint32_t)(DMA_BASE + 0x28)
+#define DMA_STS3 (uint32_t)(DMA_BASE + 0x2c)
+#define DMA_STS4 (uint32_t)(DMA_BASE + 0x30)
+#define DMA_STS5 (uint32_t)(DMA_BASE + 0x34)
+#define DMA_CFG (uint32_t)(DMA_BASE + 0x40)
+#define DMA_SEC (uint32_t)(DMA_BASE + 0x44)
+#define DMA_END (uint32_t)(DMA_BASE + 0x3ff)
+
+#define P_DMA_T0 (volatile uint32_t *)(DMA_BASE + 0x00)
+#define P_DMA_T1 (volatile uint32_t *)(DMA_BASE + 0x04)
+#define P_DMA_T2 (volatile uint32_t *)(DMA_BASE + 0x08)
+#define P_DMA_T3 (volatile uint32_t *)(DMA_BASE + 0x0c)
+#define P_DMA_T4 (volatile uint32_t *)(DMA_BASE + 0x10)
+#define P_DMA_T5 (volatile uint32_t *)(DMA_BASE + 0x14)
+#define P_DMA_STS0 (volatile uint32_t *)(DMA_BASE + 0x20)
+#define P_DMA_STS1 (volatile uint32_t *)(DMA_BASE + 0x24)
+#define P_DMA_STS2 (volatile uint32_t *)(DMA_BASE + 0x28)
+#define P_DMA_STS3 (volatile uint32_t *)(DMA_BASE + 0x2c)
+#define P_DMA_STS4 (volatile uint32_t *)(DMA_BASE + 0x30)
+#define P_DMA_STS5 (volatile uint32_t *)(DMA_BASE + 0x34)
+#define P_DMA_CFG (volatile uint32_t *)(DMA_BASE + 0x40)
+#define P_DMA_SEC (volatile uint32_t *)(DMA_BASE + 0x44)
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-t7/soc_def.h b/arch/arm/include/asm/arch-t7/soc_def.h
new file mode 100644
index 0000000..7eaa5e6
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/soc_def.h
@@ -0,0 +1,33 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __SC2_DEF_H__
+#define __SC2_DEF_H__
+
+#include "secure_apb.h"
+
+
+#define SEC_SYS_CPU_CFG2 CPUCTRL_SYS_CPU_CFG2
+
+#define SEC_AO_SEC_GP_CFG0 SYSCTRL_SEC_STATUS_REG4
+#define SEC_AO_SEC_GP_CFG2 SYSCTRL_SEC_STATUS_REG6
+#define SEC_AO_SEC_GP_CFG3 SYSCTRL_SEC_STATUS_REG15
+#define SEC_AO_SEC_GP_CFG4 SYSCTRL_SEC_STATUS_REG16
+#define SEC_AO_SEC_GP_CFG5 SYSCTRL_SEC_STATUS_REG17
+#define SEC_AO_SEC_GP_CFG7 SYSCTRL_SEC_STATUS_REG2
+#define SEC_AO_SEC_GP_CFG8 SYSCTRL_SEC_STATUS_REG10
+#define SEC_AO_SEC_GP_CFG9 SYSCTRL_SEC_STATUS_REG11
+
+
+#define AO_SEC_GP_CFG8 SYSCTRL_SEC_STATUS_REG10
+#define AO_SEC_GP_CFG9 SYSCTRL_SEC_STATUS_REG11
+#define SEC_AO_SEC_SD_CFG15 SYSCTRL_SEC_STATUS_REG2
+
+#define SEC_AO_RTI_STATUS_REG3 SYSCTRL_SEC_STICKY_REG1
+
+
+#define AO_SEC_SD_CFG15 SEC_AO_SEC_SD_CFG15
+
+#endif /* __SC2_DEF_H__ */
diff --git a/arch/arm/include/asm/arch-t7/timer.h b/arch/arm/include/asm/arch-t7/timer.h
new file mode 100644
index 0000000..492cc8d
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/timer.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __TIMER_H
+#define __TIMER_H
+
+#include <asm/arch/romboot.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/io.h>
+
+/**
+ * Get the current timestamp from the system timer.
+ */
+uint32_t get_time(void);
+
+/**
+ * Busy-wait.
+ *
+ * @param us Number of microseconds to delay.
+ */
+void _udelay(unsigned int us);
+
+#endif /* __TIMER_H */
diff --git a/arch/arm/include/asm/arch-t7/timing.h b/arch/arm/include/asm/arch-t7/timing.h
new file mode 100644
index 0000000..4bcc0f1
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/timing.h
@@ -0,0 +1,439 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AML_TIMING_H_
+#define __AML_TIMING_H_
+
+#include <asm/arch/ddr_define.h>
+#include <asm/arch/types.h>
+#include <asm/arch/mnPmuSramMsgBlock_ddr3.h>
+#include <asm/arch/mnPmuSramMsgBlock_ddr4.h>
+#include <asm/arch/mnPmuSramMsgBlock_ddr4_2d.h>
+#include <asm/arch/mnPmuSramMsgBlock_lpddr3.h>
+#include <asm/arch/mnPmuSramMsgBlock_lpddr4.h>
+#include <asm/arch/mnPmuSramMsgBlock_lpddr4_2d.h>
+#include <asm/arch/dev_parameter.h>
+
+#define BL2_INIT_STAGE_0 0
+#define BL2_INIT_STAGE_1 1
+#define BL2_INIT_STAGE_2 2
+#define BL2_INIT_STAGE_3 3
+#define BL2_INIT_STAGE_4 4
+#define BL2_INIT_STAGE_5 5
+#define BL2_INIT_STAGE_6 6
+#define BL2_INIT_STAGE_7 7
+#define BL2_INIT_STAGE_8 8
+#define BL2_INIT_STAGE_9 9
+
+typedef struct bl2_reg {
+ unsigned int reg;
+ unsigned int value;
+ unsigned int mask;
+ unsigned int flag;
+ unsigned short udelay;
+ unsigned short rsv_0;
+}__attribute__ ((packed)) bl2_reg_t;
+
+typedef struct training_delay_set_ps{
+ unsigned char ac_trace_delay[10];
+ unsigned char ac_trace_delay_rev[2];
+ unsigned char read_dqs_delay[16];
+ unsigned char read_dq_bit_delay[72];
+ unsigned short write_dqs_delay[16];
+// */
+ unsigned short write_dq_bit_delay[72];
+ unsigned short read_dqs_gate_delay[16];
+ unsigned char soc_bit_vref[36];
+ unsigned char dram_bit_vref[32];
+ ///*
+ unsigned char rever1;//read_dqs read_dq,write_dqs, write_dq
+ unsigned char dfi_mrl;
+ unsigned char dfi_hwtmrl;
+ unsigned char ARdPtrInitVal;
+ unsigned short csr_vrefinglobal;
+ unsigned short csr_dqsrcvcntrl[4];
+ unsigned short csr_pptdqscntinvtrntg0[4];
+ unsigned short csr_pptdqscntinvtrntg1[4];
+ unsigned short csr_seq0bgpr[9];
+ unsigned short csr_dllgainctl;
+ unsigned short csr_dlllockpara;
+// unsigned short rever2;
+}__attribute__ ((packed)) training_delay_set_ps_t;
+
+typedef struct ddr_mrs_reg {
+ unsigned int cfg_ddr_mr[8];
+ unsigned int cfg_ddr_mr11;
+ unsigned int cfg_ddr_mr12;
+ unsigned int cfg_ddr_mr13;
+ unsigned int cfg_ddr_mr14;
+ unsigned int cfg_ddr_mr16;
+ unsigned int cfg_ddr_mr17;
+ unsigned int cfg_ddr_mr22;
+ unsigned int cfg_ddr_mr24;
+}__attribute__ ((packed)) ddr_mrs_reg_t;
+
+typedef struct ddr_timing{
+ unsigned int identifier;
+ unsigned int cfg_ddr_mrd;
+ unsigned int cfg_ddr_rfcab;
+ unsigned int cfg_ddr_rfcpb;
+ unsigned int cfg_ddr_rpab;
+ unsigned int cfg_ddr_rppb;
+ unsigned int cfg_ddr_rtw;
+ unsigned int cfg_ddr_rl;
+ unsigned int cfg_ddr_wl;
+ unsigned int cfg_ddr_ras;
+ unsigned int cfg_ddr_rc;
+ unsigned int cfg_ddr_rcd;
+ unsigned int cfg_ddr_rrds;
+ unsigned int cfg_ddr_rrdl;
+ unsigned int cfg_ddr_faw;
+ unsigned int cfg_ddr_rtp;
+ unsigned int cfg_ddr_wr;
+ unsigned int cfg_ddr_wtrs;
+ unsigned int cfg_ddr_wtrl;
+ unsigned int cfg_ddr_ccds;
+ unsigned int cfg_ddr_ccdl;
+ unsigned int cfg_ddr_exsr;
+ unsigned int cfg_ddr_xs;
+ unsigned int cfg_ddr_xp;
+ unsigned int cfg_ddr_xpdll;
+ unsigned int cfg_ddr_zqcs;
+ unsigned int cfg_ddr_cksre;
+ unsigned int cfg_ddr_cksrx;
+ unsigned int cfg_ddr_cke;
+ unsigned int cfg_ddr_mod;
+ unsigned int cfg_ddr_dqs;
+ unsigned int cfg_ddr_rstl;
+ unsigned int cfg_ddr_zqlat;
+ unsigned int cfg_ddr_mrr;
+ unsigned int cfg_ddr_ckesr;
+ unsigned int cfg_ddr_dpd;
+ unsigned int cfg_ddr_ckeck;
+ unsigned int cfg_ddr_refi;
+ unsigned int cfg_ddr_sr;
+ unsigned int cfg_ddr_ccdmw;
+ unsigned int cfg_ddr_escke;
+ unsigned int cfg_ddr_refi_ddr3;
+ unsigned int cfg_ddr_dfictrldelay;
+ unsigned int cfg_ddr_dfiphywrdata;
+ unsigned int cfg_ddr_dfiphywrlat;
+ unsigned int cfg_ddr_dfiphyrddataen;
+ unsigned int cfg_ddr_dfiphyrdlat;
+ unsigned int cfg_ddr_dfictrlupdmin;
+ unsigned int cfg_ddr_dfictrlupdmax;
+ unsigned int cfg_ddr_dfimstrresp;
+ unsigned int cfg_ddr_dfirefmski;
+ unsigned int cfg_ddr_dfictrlupdi;
+ unsigned int cfg_ddr_dfidramclk;
+ unsigned int cfg_ddr_dfilpresp;
+ unsigned int cfg_ddr_dfiphymstr;
+ unsigned int cfg_ddr_rtodt;
+ unsigned int cfg_ddr_wlmrd;
+ unsigned int cfg_ddr_wlo;
+ unsigned int cfg_ddr_al;
+ unsigned int cfg_ddr_zqcl;
+ unsigned int cfg_ddr_zqcsi;
+ unsigned int cfg_ddr_zqreset;
+ unsigned int cfg_ddr_tdqsck_min;
+ unsigned int cfg_ddr_tdqsck_max;
+ //training_delay_set_ps_t cfg_ddr_training_delay_ps;
+ ddr_mrs_reg_t cfg_ddr_mrs_reg_ps[2];
+ unsigned int dfi_odt1_config_ps[2];
+ //ddr_mrs_reg_t cfg_ddr_mrs_reg_ps1;
+ #if 0
+ unsigned int cfg_ddr_mr[8];
+ unsigned int cfg_ddr_mr11;
+ unsigned int cfg_ddr_mr12;
+ unsigned int cfg_ddr_mr13;
+ unsigned int cfg_ddr_mr14;
+ unsigned int cfg_ddr_mr16;
+ unsigned int cfg_ddr_mr17;
+ unsigned int cfg_ddr_mr22;
+ unsigned int cfg_ddr_mr24;
+ unsigned int cfg_ddr_reserve[5];
+ #endif
+}__attribute__ ((packed)) ddr_timing_t;
+
+typedef struct ddr_phy_common_extra_set{
+ unsigned short csr_pllctrl3;
+ unsigned short csr_pptctlstatic[4];
+ unsigned short csr_trainingincdecdtsmen[4];
+ unsigned short csr_tsmbyte0[4];
+ unsigned short csr_hwtcamode;
+ unsigned short csr_hwtlpcsena;
+ unsigned short csr_hwtlpcsenb;
+ unsigned short csr_acsmctrl13;
+ unsigned short csr_acsmctrl23;
+ unsigned char csr_soc_vref_dac1_dfe[36];
+}__attribute__ ((packed)) ddr_phy_common_extra_set_t;
+
+typedef struct retraining_set{
+ ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t;
+ training_delay_set_ps_t cfg_ddr_training_delay_ps;
+}__attribute__ ((packed)) retraining_set_t;
+
+typedef struct ddr_set{
+ unsigned int magic;
+ unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test
+ //unsigned int rsv_int0;
+ unsigned int ddr_func;
+ unsigned char board_id;
+ //board id reserve,,do not modify
+ unsigned char version;
+ // firmware reserve version,,do not modify
+ unsigned char DramType;
+ //support DramType should confirm with amlogic
+ //#define CONFIG_DDR_TYPE_DDR3 0
+ //#define CONFIG_DDR_TYPE_DDR4 1
+ //#define CONFIG_DDR_TYPE_LPDDR4 2
+ //#define CONFIG_DDR_TYPE_LPDDR3 3
+ //#define CONFIG_DDR_TYPE_LPDDR2 4
+ //#define CONFIG_DDR_TYPE_LPDDR4x 5
+ unsigned char DisabledDbyte[2]; //ch0 and ch1
+ //use for dram bus 16bit or 32bit,if use 16bit mode ,should disable bit 2,3
+ //bit 0 ---cs0 use byte 0 ,1 disable byte 0,
+ //bit 1 ---cs0 use byte 1 ,1 disable byte 1,
+ //bit 2 ---cs0 use byte 2 ,1 disable byte 2,
+ //bit 3 ---cs0 use byte 3 ,1 disable byte 3,
+ //bit 4 ---cs1 use byte 0 ,1 disable byte 0,
+ //bit 5 ---cs1 use byte 1 ,1 disable byte 1,
+ //bit 6 ---cs1 use byte 2 ,1 disable byte 2,
+ //bit 7 ---cs1 use byte 3 ,1 disable byte 3,
+ unsigned char Is2Ttiming;
+ //ddr3/ddr3 use 2t timing,now only support 2t timming
+ unsigned char HdtCtrl;
+ //training information control,do not modify
+ unsigned char dram_rank_config;
+ //support Dram connection type should confirm with amlogic
+ //#define CONFIG_DDR0_16BIT_CH0 0x1 //dram total bus width 16bit only use cs0
+ //#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 //dram total bus width 16bit use cs0 cs1
+ //#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 //dram total bus width 32bit use cs0
+ //#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 //only for lpddr4,dram total bus width 32bit use chanel a cs0 cs1 chanel b cs0 cs1
+ //#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 //dram total bus width 32bit only use cs0,but high address use 16bit mode
+ //#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 //dram total bus width 32bit use cs0 cs1,but cs1 use 16bit mode ,current phy not support reserve
+ //#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7 //dram total bus width 32bit use cs0 cs1
+ //#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8 //only for lpddr4,dram total bus width 32bit use chanel a cs0 chanel b cs0
+
+ /* rsv_char0. update for diagnose type define */
+ //unsigned char diagnose;
+
+ unsigned short soc_data_drv_ohm_ps1;
+ unsigned short dram_data_drv_ohm_ps1;
+ unsigned short soc_data_odt_ohm_ps1;
+ unsigned short dram_data_odt_ohm_ps1;
+ unsigned short dram_data_wr_odt_ohm_ps1;
+#if 0
+ /* imem/dmem define */
+ unsigned int imem_load_addr;
+ //system reserve,do not modify
+ unsigned int dmem_load_addr;
+ //system reserve,do not modify
+ unsigned short imem_load_size;
+#endif
+ //system reserve,do not modify
+ unsigned short soc_data_drv_ohm_ffe; //dmem_load_size;
+ //system reserve,do not modify
+ unsigned int ddr_base_addr;
+ //system reserve,do not modify
+ unsigned int ddr_start_offset;
+ //system reserve,do not modify
+
+ unsigned short dram_ch0_size_MB;
+ //config cs0 dram size ,like 1G DRAM ,setting 1024
+ unsigned short dram_ch1_size_MB;
+ //config cs1 dram size,like 512M DRAM ,setting 512
+ /* align8 */
+
+ unsigned short training_SequenceCtrl[2];
+ //system reserve,do not modify
+ unsigned char phy_odt_config_rank[2];
+ //unsigned char rever1;
+ //unsigned char rever2;
+ unsigned short rank1_ca_vref_permil;
+ //training odt config ,only use for training
+ // [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ // [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ unsigned int dfi_odt_config;
+ //normal go status od config,use for normal status
+ //bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity.
+ //bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1.
+ //bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0.
+ //bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1.
+ //bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0.
+ //bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity.
+ //bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0.
+ //bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1.
+ //bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0.
+ //bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1.
+ unsigned short DRAMFreq[4];
+ //config dram frequency,use DRAMFreq[0],ohter reserve
+ unsigned char PllBypassEn;
+ //system reserve,do not modify
+ unsigned char ddr_rdbi_wr_enable;
+ //system reserve,do not modify
+ unsigned char ddr_rfc_type;
+ //config dram rfc type,according dram type,also can use same dram type max config
+ //#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+ //#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+ //#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+ //#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+ //#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+ //#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+ //#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+ //#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+ //#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+ //#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+ //#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+ //#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+ unsigned char enable_lpddr4x_mode;
+ //system reserve,do not modify
+ /* align8 */
+
+ unsigned int pll_ssc_mode;
+ //
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ unsigned short clk_drv_ohm;
+ //config soc clk pin signal driver stength ,select 20,30,40,60ohm
+ unsigned short cs_drv_ohm;
+ //config soc cs0 cs1 pin signal driver stength ,select 20,30,40,60ohm
+ unsigned short ac_drv_ohm;
+ //config soc normal address command pin driver stength ,select 20,30,40,60ohm
+ unsigned short soc_data_drv_ohm_p;
+ //config soc data pin pull up driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short soc_data_drv_ohm_n;
+ //config soc data pin pull down driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short soc_data_odt_ohm_p;
+ //config soc data pin odt pull up stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short soc_data_odt_ohm_n;
+ //config soc data pin odt pull down stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short dram_data_drv_ohm;
+ //config dram data pin pull up pull down driver stength,ddr3 select 34,40ohm,ddr4 select 34,48ohm,lpddr4 select 40,48,60,80,120,240ohm
+ unsigned short dram_data_odt_ohm;
+ //config dram data pin odt pull up down stength,ddr3 select 40,60,120ohm,ddr4 select 34,40,48,60,120,240ohm,lpddr4 select 40,48,60,80,120,240ohm
+ unsigned short dram_ac_odt_ohm;
+ //config dram ac pin odt pull up down stength,use for lpddr4, select 40,48,60,80,120,240ohm
+ unsigned short soc_clk_slew_rate;
+ //system reserve,do not modify
+ unsigned short soc_cs_slew_rate;
+ //system reserve,do not modify
+ unsigned short soc_ac_slew_rate;
+ //system reserve,do not modify
+ unsigned short soc_data_slew_rate;
+ //system reserve,do not modify
+ unsigned short vref_output_permil; //phy
+ //setting same with vref_dram_permil
+ unsigned short vref_receiver_permil; //soc
+ //soc init SOC receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
+ unsigned short vref_dram_permil;
+ //soc init DRAM receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
+ unsigned short max_core_timmming_frequency;
+ //use for limited ddr speed core timmming parameter,for some old dram maybe have no over speed register
+ /* align8 */
+
+ unsigned char ac_trace_delay[10];
+ unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting;
+ //use for lpddr4 read vout voltage setting 0 --->2/5VDDQ ,1--->1/3VDDQ
+ unsigned char lpddr4_x8_mode;
+ unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function
+ //[1],slt test parameter ,use for force delay line offset
+ //system reserve,do not modify
+ unsigned short tdqs2dq;
+ unsigned char dram_data_wr_odt_ohm;
+ unsigned char bitTimeControl_2d;
+ //system reserve,do not modify
+ /* align8 */
+ unsigned char char_rev1;
+ unsigned char training_offset;//char_rev2;
+ unsigned int ddr_dmc_remap[5];
+ unsigned int dram_rtt_nom_wr_park[2];
+ //system reserve,do not modify
+ /* align8 */
+ unsigned char ddr_lpddr34_ca_remap[4];
+ ////use for lpddr3 /lpddr4 ca training data byte lane remap
+ unsigned char ddr_lpddr34_dq_remap[32];
+ ////use for lpddr3 /lpddr4 ca pinmux remap
+ unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL];
+ //use for lpddr3 /lpddr4 ca pinmux remap
+ unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL];
+ unsigned char char_rev3;
+ unsigned char char_rev4;
+ ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t;
+ training_delay_set_ps_t cfg_ddr_training_delay_ps[2];
+
+ //override read bit delay
+}__attribute__ ((packed)) ddr_set_t;
+
+typedef struct board_clk_set{
+ unsigned short cpu_clk;
+ unsigned short dsu_clk;
+ unsigned short vddee;
+ unsigned short vcck;
+ unsigned short pxp;
+ unsigned char low_console_baud;
+ unsigned char szPad[1];
+}__attribute__ ((packed)) board_clk_set_t;
+
+typedef struct pll_ctrl{
+ /*Enable flag: 0xa1:need set pll in bl2
+ 0xa2:need set pll in bl2x
+ other: no need
+ */
+ unsigned char flag;
+ /* Delay time for timing sequence in 10us, range [0 .. 255]*/
+ unsigned char delay_10u;
+ /* PLL clock
+ * syspll [93 .. 6000]
+ * fixpll [93 .. 6000]
+ * gp0pll [93 .. 6000]
+ * gp1pll [93 .. 6000]
+ * hifipll [375 .. 6000]
+ */
+ unsigned short clkset;
+ unsigned int pll_para[8];
+ unsigned int reserve;
+} __attribute__ ((packed)) pll_ctrl_t;
+
+typedef struct pll_set{
+ /*new struct for sc2*/
+ pll_ctrl_t sys_pll_ctrl;
+ pll_ctrl_t fix_pll_ctrl;
+ pll_ctrl_t gp0_pll_ctrl;
+ pll_ctrl_t gp1_pll_ctrl;
+ pll_ctrl_t hifi_pll_ctrl;
+}__attribute__ ((packed)) pll_set_t;
+
+typedef struct bl2_sec_parameter{
+ /*new struct for sc2*/
+ uint32_t version;
+ uint32_t bl31_region_start;
+ uint32_t bl31_region_size;
+ uint32_t bl32_region_start;
+ uint32_t bl32_region_size;
+
+ uint32_t RFU[27];
+}__attribute__ ((packed)) sec_parameter_t;
+
+typedef struct dmem_cfg {
+ PMU_SMB_DDR3U_1D_t ddr3u;
+ PMU_SMB_DDR4U_1D_t ddr4u;
+ PMU_SMB_DDR4U_2D_t ddr4u_2d;
+ PMU_SMB_LPDDR3_1D_t lpddr3u;
+ PMU_SMB_LPDDR4_1D_t lpddr4u;
+ PMU_SMB_LPDDR4_2D_t lpddr4u_2d;
+} dmem_cfg_t;
+
+#endif //__AML_TIMING_H_
diff --git a/arch/arm/include/asm/arch-t7/tsensor.h b/arch/arm/include/asm/arch-t7/tsensor.h
new file mode 100644
index 0000000..8b365a4
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/tsensor.h
@@ -0,0 +1,53 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __TSENSOR_H__
+#define __TSENSOR_H__
+
+
+struct tsensor_cali_data {
+ unsigned int cmd; /* R/W */
+ unsigned int offset;
+ unsigned int size;
+ unsigned long buffer_phy;
+ unsigned long retcnt_phy;
+};
+
+
+#define CONFIG_HIGH_TEMP_COOL 90
+
+#define T_AVG_NUM 16 /*read temp cnt*/
+#define T_VER_MASK 0x80
+#define T_VALUE_MIN 0x1500
+#define T_VALUE_MAX 0x3500
+#define T_DLY_TIME 4500 /*update sensor register need 4.2ms*/
+
+#define T_CONTROL_DATA 0x62b
+#define T_TSCLK_DATA 0x130
+
+#define ts_b 3159
+#define ts_a 9411
+#define ts_m 424
+#define ts_n 324
+
+#ifdef CONFIG_AML_TSENSOR
+int temp_read_entry(void);
+int temp_trim_entry(int tempbase, int tempver);
+int temp_cooling_entry(void);
+#else
+int temp_read_entry(void)
+{
+ return -1;
+}
+int temp_trim_entry(int tempbase, int tempver)
+{
+ return -1;
+}
+int temp_cooling_entry(void)
+{
+ return 0;
+}
+#endif
+#endif
diff --git a/arch/arm/include/asm/arch-t7/types.h b/arch/arm/include/asm/arch-t7/types.h
new file mode 100644
index 0000000..2d362b1
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/types.h
@@ -0,0 +1,89 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __TYPES_H
+#define __TYPES_H
+
+#ifndef _INT8_T_DECLARED
+typedef char int8_t;
+#define _INT8_T_DECLARED
+#endif
+
+#ifndef _INT16_T_DECLARED
+typedef short int16_t;
+#define _INT16_T_DECLARED
+#endif
+
+#ifndef _INT32_T_DECLARED
+typedef int int32_t;
+#define _INT32_T_DECLARED
+#endif
+
+#ifndef _INT64_T_DECLARED
+typedef long int64_t;
+#define _INT64_T_DECLARED
+#endif
+
+#ifndef _UINT8_T_DECLARED
+typedef unsigned char uint8_t;
+#define _UINT8_T_DECLARED
+#endif
+
+#ifndef _UINT16_T_DECLARED
+typedef unsigned short uint16_t;
+#define _UINT16_T_DECLARED
+#endif
+
+#ifndef _UINT32_T_DECLARED
+typedef unsigned int uint32_t;
+#define _UINT32_T_DECLARED
+#endif
+
+#ifndef _UINT64_T_DECLARED
+typedef unsigned long uint64_t;
+#define _UINT64_T_DECLARED
+#endif
+
+#ifndef _INT8PTR_T_DECLARED
+typedef char * int8ptr_t;
+#define _INT8PTR_T_DECLARED
+#endif
+
+#ifndef _INT16PTR_T_DECLARED
+typedef short * int16ptr_t;
+#define _INT16PTR_T_DECLARED
+#endif
+
+#ifndef _INT32PTR_T_DECLARED
+typedef int * int32ptr_t;
+#define _INT32PTR_T_DECLARED
+#endif
+
+#ifndef _INT64PTR_T_DECLARED
+typedef long * int64ptr_t;
+#define _INT64PTR_T_DECLARED
+#endif
+
+#ifndef _UINT8PTR_T_DECLARED
+typedef unsigned char * uint8ptr_t;
+#define _UINT8PTR_T_DECLARED
+#endif
+
+#ifndef _UINT16PTR_T_DECLARED
+typedef unsigned short * uint16ptr_t;
+#define _UINT16PTR_T_DECLARED
+#endif
+
+#ifndef _UINT32PTR_T_DECLARED
+typedef unsigned int * uint32ptr_t;
+#define _UINT32PTR_T_DECLARED
+#endif
+
+#ifndef _UINT64PTR_T_DECLARED
+typedef unsigned long * uint64ptr_t;
+#define _UINT64PTR_T_DECLARED
+#endif
+
+#endif
\ No newline at end of file
diff --git a/arch/arm/include/asm/arch-t7/uart.h b/arch/arm/include/asm/arch-t7/uart.h
new file mode 100644
index 0000000..757dc91
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/uart.h
@@ -0,0 +1,152 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __MESON_FIRM_UART_H_
+#define __MESON_FIRM_UART_H_
+#include <config.h>
+#include <common.h>
+#include "register.h"
+//#include "io.h"
+#include <asm/arch/secure_apb.h>
+
+#ifndef CONFIG_CONS_INDEX
+#error Please define CONFIG_CONS_INDEX==[0|1]
+#endif
+
+#if CONFIG_CONS_INDEX==0
+#define UART_PORT_CONS UART_PORT_0
+#elif CONFIG_CONS_INDEX==1
+#define UART_PORT_CONS UART_PORT_1
+#elif CONFIG_CONS_INDEX==2
+#define UART_PORT_CONS UART_PORT_AO
+#define USE_AO_UART 1
+#else
+#error Please define CONFIG_CONS_INDEX==[0|1]
+#endif
+/*
+#define UART_PORT_0 CBUS_REG_ADDR(UART0_WFIFO)
+#define UART_PORT_1 CBUS_REG_ADDR(UART1_WFIFO)
+#define UART_PORT_2 CBUS_REG_ADDR(UART2_WFIFO)
+#define UART_PORT_AO P_AO_UART_WFIFO
+
+#define UART_WFIFO (0<<2)
+#define UART_RFIFO (1<<2)
+#define UART_CONTROL (2<<2)
+#define UART_STATUS (3<<2)
+#define UART_MISC (4<<2)
+*/
+
+#include "clock.h"
+
+#define UART_CLK_SRC CLK81
+#define UART_PORT_0 0xfe001c00
+#define UART_PORT_1 0xfe001c00
+#define UART_PORT_AO 0xfe001c00
+#define UART_WFIFO 0
+#define UART_RFIFO 1
+#define UART_CONTROL 2
+#define UART_STATUS 3
+#define UART_MISC 4
+
+#if USE_AO_UART == 1
+#define P_UART(uart_base,reg) (uart_base + (reg<<2))
+#else
+#define P_UART(uart_base,reg) CBUS_REG_ADDR(uart_base+reg)
+#endif
+#define P_UART_WFIFO(uart_base) P_UART(uart_base,UART_WFIFO)
+#define P_UART_RFIFO(uart_base) P_UART(uart_base,UART_RFIFO)
+
+#define P_UART_CONTROL(uart_base) P_UART(uart_base,UART_CONTROL)
+ #define UART_CNTL_MASK_BAUD_RATE (0xfff)
+ #define UART_CNTL_MASK_TX_EN (1<<12)
+ #define UART_CNTL_MASK_RX_EN (1<<13)
+ #define UART_CNTL_MASK_2WIRE (1<<15)
+ #define UART_CNTL_MASK_STP_BITS (3<<16)
+ #define UART_CNTL_MASK_STP_1BIT (0<<16)
+ #define UART_CNTL_MASK_STP_2BIT (1<<16)
+ #define UART_CNTL_MASK_PRTY_EVEN (0<<18)
+ #define UART_CNTL_MASK_PRTY_ODD (1<<18)
+ #define UART_CNTL_MASK_PRTY_TYPE (1<<18)
+ #define UART_CNTL_MASK_PRTY_EN (1<<19)
+ #define UART_CNTL_MASK_CHAR_LEN (3<<20)
+ #define UART_CNTL_MASK_CHAR_8BIT (0<<20)
+ #define UART_CNTL_MASK_CHAR_7BIT (1<<20)
+ #define UART_CNTL_MASK_CHAR_6BIT (2<<20)
+ #define UART_CNTL_MASK_CHAR_5BIT (3<<20)
+ #define UART_CNTL_MASK_RST_TX (1<<22)
+ #define UART_CNTL_MASK_RST_RX (1<<23)
+ #define UART_CNTL_MASK_CLR_ERR (1<<24)
+ #define UART_CNTL_MASK_INV_RX (1<<25)
+ #define UART_CNTL_MASK_INV_TX (1<<26)
+ #define UART_CNTL_MASK_RINT_EN (1<<27)
+ #define UART_CNTL_MASK_TINT_EN (1<<28)
+ #define UART_CNTL_MASK_INV_CTS (1<<29)
+ #define UART_CNTL_MASK_MASK_ERR (1<<30)
+ #define UART_CNTL_MASK_INV_RTS (1<<31)
+#define P_UART_STATUS(uart_base) P_UART(uart_base,UART_STATUS )
+ #define UART_STAT_MASK_RFIFO_CNT (0x7f<<0)
+ #define UART_STAT_MASK_TFIFO_CNT (0x7f<<8)
+ #define UART_STAT_MASK_PRTY_ERR (1<<16)
+ #define UART_STAT_MASK_FRAM_ERR (1<<17)
+ #define UART_STAT_MASK_WFULL_ERR (1<<18)
+ #define UART_STAT_MASK_RFIFO_FULL (1<<19)
+ #define UART_STAT_MASK_RFIFO_EMPTY (1<<20)
+ #define UART_STAT_MASK_TFIFO_FULL (1<<21)
+ #define UART_STAT_MASK_TFIFO_EMPTY (1<<22)
+ #define UART_STAT_MASK_XMIT_BUSY (1<<25)
+ #define UART_STAT_MASK_RECV_BUSY (1<<26)
+#define P_UART_MISC(uart_base) P_UART(uart_base,UART_MISC )
+
+
+#ifndef CONFIG_SERIAL_STP_BITS
+#define CONFIG_SERIAL_STP_BITS 1 // 1 , 2
+#endif
+#if CONFIG_SERIAL_STP_BITS==1
+#define UART_STP_BIT UART_CNTL_MASK_STP_1BIT
+#elif CONFIG_SERIAL_STP_BITS==2
+#define UART_STP_BIT UART_CNTL_MASK_STP_2BIT
+#else
+#error CONFIG_SERIAL_STP_BITS wrong
+#endif
+
+
+#ifndef CONFIG_SERIAL_PRTY_TYPE
+#define CONFIG_SERIAL_PRTY_TYPE 0 //0 ,2 ,3
+#endif
+#if CONFIG_SERIAL_PRTY_TYPE==0
+#define UART_PRTY_BIT 0
+#elif CONFIG_SERIAL_PRTY_TYPE==2
+#define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_EVEN)
+#elif CONFIG_SERIAL_PRTY_TYPE==3
+#define UART_PRTY_BIT (UART_CNTL_MASK_PRTY_EN|UART_CNTL_MASK_PRTY_ODD)
+#else
+#error CONFIG_SERIAL_PRTY_TYPE wrong
+#endif
+
+#ifndef CONFIG_SERIAL_CHAR_LEN
+#define CONFIG_SERIAL_CHAR_LEN 8 //5,6,7,8
+#endif
+#if CONFIG_SERIAL_CHAR_LEN==5
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_5BIT
+#elif CONFIG_SERIAL_CHAR_LEN==6
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_6BIT
+#elif CONFIG_SERIAL_CHAR_LEN==7
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_7BIT
+#elif CONFIG_SERIAL_CHAR_LEN==8
+#define UART_CHAR_LEN UART_CNTL_MASK_CHAR_8BIT
+#else
+#error CONFIG_SERIAL_CHAR_LEN wrong
+#endif
+#define UART_CONTROL_SET(baud,clk81) \
+ (((clk81)/(baud*4) -1) \
+ | UART_STP_BIT \
+ | UART_PRTY_BIT \
+ | UART_CHAR_LEN \
+ | UART_CNTL_MASK_TX_EN \
+ | UART_CNTL_MASK_RX_EN \
+ | UART_CNTL_MASK_RST_TX \
+ | UART_CNTL_MASK_RST_RX \
+ | UART_CNTL_MASK_CLR_ERR )
+#endif
diff --git a/arch/arm/include/asm/arch-t7/usb.h b/arch/arm/include/asm/arch-t7/usb.h
new file mode 100644
index 0000000..365048b
--- /dev/null
+++ b/arch/arm/include/asm/arch-t7/usb.h
@@ -0,0 +1,242 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __ARCH_ARM_MESON_USB_H_U_BOOT__
+#define __ARCH_ARM_MESON_USB_H_U_BOOT__
+
+#include <common.h>
+#include <asm/types.h>
+#include <asm/arch/io.h>
+#include <asm/arch/secure_apb.h>
+#include <generic-phy.h>
+#include <asm-generic/gpio.h>
+
+#define USB_PHY_PORT_MAX 1
+/* Phy register MACRO definitions */
+
+#define LINKSYSTEM_FLADJ_MASK (0x3f << 1)
+#define LINKSYSTEM_FLADJ(_x) ((_x) << 1)
+#define LINKSYSTEM_XHCI_VERSION_CONTROL (0x1 << 27)
+
+#define PHYUTMI_OTGDISABLE (1 << 6)
+#define PHYUTMI_FORCESUSPEND (1 << 1)
+#define PHYUTMI_FORCESLEEP (1 << 0)
+
+#define PHYCLKRST_SSC_REFCLKSEL_MASK (0xff << 23)
+#define PHYCLKRST_SSC_REFCLKSEL(_x) ((_x) << 23)
+
+#define PHYCLKRST_SSC_RANGE_MASK (0x03 << 21)
+#define PHYCLKRST_SSC_RANGE(_x) ((_x) << 21)
+
+#define PHYCLKRST_SSC_EN (0x1 << 20)
+#define PHYCLKRST_REF_SSP_EN (0x1 << 19)
+#define PHYCLKRST_REF_CLKDIV2 (0x1 << 18)
+
+#define PHYCLKRST_MPLL_MULTIPLIER_MASK (0x7f << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_100MHZ_REF (0x19 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_50M_REF (0x02 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_24MHZ_REF (0x68 << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_20MHZ_REF (0x7d << 11)
+#define PHYCLKRST_MPLL_MULTIPLIER_19200KHZ_REF (0x02 << 11)
+
+#define PHYCLKRST_FSEL_MASK (0x3f << 5)
+#define PHYCLKRST_FSEL(_x) ((_x) << 5)
+#define PHYCLKRST_FSEL_PAD_100MHZ (0x27 << 5)
+#define PHYCLKRST_FSEL_PAD_24MHZ (0x2a << 5)
+#define PHYCLKRST_FSEL_PAD_20MHZ (0x31 << 5)
+#define PHYCLKRST_FSEL_PAD_19_2MHZ (0x38 << 5)
+
+#define PHYCLKRST_RETENABLEN (0x1 << 4)
+
+#define PHYCLKRST_REFCLKSEL_MASK (0x03 << 2)
+#define PHYCLKRST_REFCLKSEL_PAD_REFCLK (0x2 << 2)
+#define PHYCLKRST_REFCLKSEL_EXT_REFCLK (0x3 << 2)
+
+#define PHYCLKRST_PORTRESET (0x1 << 1)
+#define PHYCLKRST_COMMONONN (0x1 << 0)
+
+#define PHYPARAM0_REF_USE_PAD (0x1 << 31)
+#define PHYPARAM0_REF_LOSLEVEL_MASK (0x1f << 26)
+#define PHYPARAM0_REF_LOSLEVEL (0x9 << 26)
+
+#define PHYPARAM1_PCS_TXDEEMPH_MASK (0x1f << 0)
+#define PHYPARAM1_PCS_TXDEEMPH (0x1c)
+
+#define PHYTEST_POWERDOWN_SSP (0x1 << 3)
+#define PHYTEST_POWERDOWN_HSP (0x1 << 2)
+
+#define PHYBATCHG_UTMI_CLKSEL (0x1 << 2)
+
+#define FSEL_CLKSEL_24M (0x5)
+
+#define USB_PHY2_ENABLE 0x10000000
+#define USB_PHY2_RESET 0x20000000
+
+/* XHCI PHY register structure */
+#define PHY_REGISTER_SIZE 0x20
+
+struct phy_aml_usb2_priv {
+ unsigned int base_addr;
+ unsigned int reset_addr;
+ unsigned int dwc2_a_addr;
+ unsigned int u2_port_num;
+ unsigned int usbphy_reset_bit[8];
+ unsigned int usb_phy2_pll_base_addr[4];
+};
+
+struct phy_aml_usb3_priv {
+ unsigned int base_addr;
+ unsigned int usb3_port_num;
+ struct gpio_desc desc;
+};
+
+/* Register definitions */
+typedef struct u2p_aml_regs {
+ volatile uint32_t u2p_r0;
+ volatile uint32_t u2p_r1;
+} u2p_aml_regs_t;
+
+typedef union u2p_r0 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned host_device:1;
+ unsigned power_ok:1;
+ unsigned hast_mode:1;
+ unsigned POR:1;
+ unsigned IDPULLUP0:1;
+ unsigned DRVVBUS0:1;
+ unsigned reserved:26;
+ } b;
+} u2p_r0_t;
+
+typedef union u2p_r1 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned phy_rdy:1;
+ unsigned IDDIG0:1;
+ unsigned OTGSESSVLD0:1;
+ unsigned VBUSVALID0:1;
+ unsigned reserved:28;
+ } b;
+} u2p_r1_t;
+
+
+typedef struct usb_aml_regs {
+ volatile uint32_t usb_r0;
+ volatile uint32_t usb_r1;
+ volatile uint32_t usb_r2;
+ volatile uint32_t usb_r3;
+ volatile uint32_t usb_r4;
+ volatile uint32_t usb_r5;
+} usb_aml_regs_t;
+
+typedef union usb_r0 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned reserved:17;
+ unsigned p30_lane0_tx2rx_loopback:1;
+ unsigned p30_lane0_ext_pclk_reg:1;
+ unsigned p30_pcs_rx_los_mask_val:10;
+ unsigned u2d_ss_scaledown_mode:2;
+ unsigned u2d_act:1;
+ } b;
+} usb_r0_t;
+
+typedef union usb_r1 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned u3h_bigendian_gs:1;
+ unsigned u3h_pme_en:1;
+ unsigned u3h_hub_port_overcurrent:3;
+ unsigned reserved_1:2;
+ unsigned u3h_hub_port_perm_attach:3;
+ unsigned reserved_2:2;
+ unsigned u3h_host_u2_port_disable:2;
+ unsigned reserved_3:2;
+ unsigned u3h_host_u3_port_disable:1;
+ unsigned u3h_host_port_power_control_present:1;
+ unsigned u3h_host_msi_enable:1;
+ unsigned u3h_fladj_30mhz_reg:6;
+ unsigned p30_pcs_tx_swing_full:7;
+ } b;
+} usb_r1_t;
+
+typedef union usb_r2 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned reserved:20;
+ unsigned p30_pcs_tx_deemph_3p5db:6;
+ unsigned p30_pcs_tx_deemph_6db:6;
+ } b;
+} usb_r2_t;
+
+typedef union usb_r3 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned p30_ssc_en:1;
+ unsigned p30_ssc_range:3;
+ unsigned p30_ssc_ref_clk_sel:9;
+ unsigned p30_ref_ssp_en:1;
+ unsigned reserved:18;
+ } b;
+} usb_r3_t;
+
+typedef union usb_r4 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned p21_PORTRESET0:1;
+ unsigned p21_SLEEPM0:1;
+ unsigned mem_pd:2;
+ unsigned p21_only:1;
+ unsigned reserved:27;
+ } b;
+} usb_r4_t;
+
+typedef union usb_r5 {
+ /** raw register data */
+ uint32_t d32;
+ /** register bits */
+ struct {
+ unsigned iddig_sync:1;
+ unsigned iddig_reg:1;
+ unsigned iddig_cfg:2;
+ unsigned iddig_en0:1;
+ unsigned iddig_en1:1;
+ unsigned iddig_curr:1;
+ unsigned usb_iddig_irq:1;
+ unsigned iddig_th:8;
+ unsigned iddig_cnt:8;
+ unsigned reserved:8;
+ } b;
+} usb_r5_t;
+
+/* usb id mode, only after M2
+ mode = 0 : HARDWARE
+ mode = 1 : SW_HOST
+ mode = 2 : SW_DEVICE
+ */
+#define USB_ID_MODE_HARDWARE (1)
+#define USB_ID_MODE_SW_HOST (2)
+#define USB_ID_MODE_SW_DEVICE (3)
+int usb2_phy_tuning(uint32_t phy2_pll_base, int port);
+void set_usb_pll(uint32_t phy2_pll_base);
+int usb_save_phy_dev (unsigned int number, struct phy *phy);
+int usb2_phy_init (struct phy *phy);
+void usb_device_mode_init(int phy_num);
+#endif
diff --git a/arch/arm/include/asm/io.h b/arch/arm/include/asm/io.h
index 12bc7fb..8d14199 100644
--- a/arch/arm/include/asm/io.h
+++ b/arch/arm/include/asm/io.h
@@ -41,12 +41,12 @@
*/
#define __arch_getb(a) (*(volatile unsigned char *)(a))
#define __arch_getw(a) (*(volatile unsigned short *)(a))
-#define __arch_getl(a) (*(volatile unsigned int *)(a))
+#define __arch_getl(a) (*(volatile unsigned int *)(uintptr_t)(a))
#define __arch_getq(a) (*(volatile unsigned long long *)(a))
#define __arch_putb(v,a) (*(volatile unsigned char *)(a) = (v))
#define __arch_putw(v,a) (*(volatile unsigned short *)(a) = (v))
-#define __arch_putl(v,a) (*(volatile unsigned int *)(a) = (v))
+#define __arch_putl(v,a) (*(volatile unsigned int *)(uintptr_t)(a) = (v))
#define __arch_putq(v,a) (*(volatile unsigned long long *)(a) = (v))
static inline void __raw_writesb(unsigned long addr, const void *data,
diff --git a/arch/arm/lib/bootm.c b/arch/arm/lib/bootm.c
index d3cb5a5..d1972da 100644
--- a/arch/arm/lib/bootm.c
+++ b/arch/arm/lib/bootm.c
@@ -32,10 +32,6 @@
#endif
#include <asm/setup.h>
-#if defined(CONFIG_ZIRCON_BOOT_IMAGE)
-#include <zircon/zircon.h>
-#endif
-
DECLARE_GLOBAL_DATA_PTR;
static struct tag *params;
@@ -336,6 +332,7 @@
debug("## Transferring control to Linux (at address %lx)...\n",
(ulong) kernel_entry);
bootstage_mark(BOOTSTAGE_ID_RUN_OS);
+
announce_and_cleanup(fake);
if (!fake) {
@@ -369,6 +366,8 @@
}
#endif
#endif
+ extern uint32_t get_time(void);
+ printf("uboot time: %u us\n", get_time());
if (images->os.arch == IH_ARCH_ARM) {
printf("boot 32bit kernel\n");
jump_to_a32_kernel(images->ep, machid, (unsigned long)images->ft_addr);
@@ -477,47 +476,3 @@
((void (*)(void *))images->ep)(images->ft_addr);
}
#endif
-
-#if defined(CONFIG_ZIRCON_BOOT_IMAGE)
-
-#define ZIRCON_KERNEL_ALIGN 65536
-
-int do_bootm_zircon(int flag, int argc, char * const argv[],
- bootm_headers_t *images)
-{
- zbi_header_t *zbi = (zbi_header_t *)images->ep;
- const zbi_header_t *kernel_hdr = &zbi[1];
- const zbi_kernel_t *kernel = (zbi_kernel_t *)&zbi[2];
- int ret = zircon_preboot(zbi);
-
- if (ret < 0) {
- printf("zircon_preboot failed\n");
- return ret;
- }
-
- u32 zbi_len = zbi->length + sizeof(zbi_header_t);
- u32 kernel_len = kernel_hdr->length + 2 * sizeof(zbi_header_t);
-
- /*
- * If zbi_len is greater than kernel_len,
- * then we have boot items after the kernel.
- * In that case we must relocate the kernel after the zbi
- */
- if (zbi_len > kernel_len) {
- uintptr_t dest = (ulong)zbi + zbi_len;
- // align to 64K boundary
- dest = (dest + ZIRCON_KERNEL_ALIGN - 1) &
- ~(ZIRCON_KERNEL_ALIGN - 1);
- memcpy((void *)dest, zbi, kernel_len);
- images->ep = dest + kernel->entry;
- } else {
- images->ep = (ulong)zbi + kernel->entry;
- }
-
- /* this will pass the zbi pointer to the kernel via x0 */
- images->ft_addr = (char *)zbi;
-
- boot_jump_linux(images, flag);
- return 0;
-}
-#endif
diff --git a/arch/arm/lib/reset.c b/arch/arm/lib/reset.c
index f3ea116..4b6a125 100644
--- a/arch/arm/lib/reset.c
+++ b/arch/arm/lib/reset.c
@@ -34,7 +34,9 @@
disable_interrupts();
- reset_misc();
+ dcache_disable();
+
+ //reset_misc(); /* a1 call this function here crash ? */
reset_cpu(0);
/*NOTREACHED*/
diff --git a/arch/arm/mach-aspeed/Kconfig b/arch/arm/mach-aspeed/Kconfig
index e20df0f..4f021ba 100644
--- a/arch/arm/mach-aspeed/Kconfig
+++ b/arch/arm/mach-aspeed/Kconfig
@@ -21,4 +21,3 @@
source "arch/arm/mach-aspeed/ast2500/Kconfig"
endif
-
diff --git a/arch/arm/mach-aspeed/ast2500/Kconfig b/arch/arm/mach-aspeed/ast2500/Kconfig
index 54f635f..b815153 100644
--- a/arch/arm/mach-aspeed/ast2500/Kconfig
+++ b/arch/arm/mach-aspeed/ast2500/Kconfig
@@ -14,4 +14,3 @@
source "board/aspeed/evb_ast2500/Kconfig"
endif
-
diff --git a/arch/arm/mach-at91/Kconfig b/arch/arm/mach-at91/Kconfig
index 1bbc8ec..a6329dc 100644
--- a/arch/arm/mach-at91/Kconfig
+++ b/arch/arm/mach-at91/Kconfig
@@ -299,4 +299,3 @@
default "arch/arm/mach-at91/armv7/u-boot-spl.lds" if CPU_V7A
endif
-
diff --git a/arch/arm/mach-bcm283x/Kconfig b/arch/arm/mach-bcm283x/Kconfig
index 93d67db..821caed 100644
--- a/arch/arm/mach-bcm283x/Kconfig
+++ b/arch/arm/mach-bcm283x/Kconfig
@@ -142,4 +142,3 @@
default "rpi"
endmenu
-
diff --git a/arch/arm/mach-bcmstb/Kconfig b/arch/arm/mach-bcmstb/Kconfig
index dbc2535..0a56c3c 100644
--- a/arch/arm/mach-bcmstb/Kconfig
+++ b/arch/arm/mach-bcmstb/Kconfig
@@ -41,4 +41,3 @@
default 1
endif
-
diff --git a/arch/arm/mach-davinci/Kconfig b/arch/arm/mach-davinci/Kconfig
index d09732f..12b1e68 100644
--- a/arch/arm/mach-davinci/Kconfig
+++ b/arch/arm/mach-davinci/Kconfig
@@ -157,4 +157,3 @@
default "board/$(BOARDDIR)/u-boot-spl-da850evm.lds"
endif
-
diff --git a/arch/arm/mach-exynos/Kconfig b/arch/arm/mach-exynos/Kconfig
index 963a6f1..ed04369 100644
--- a/arch/arm/mach-exynos/Kconfig
+++ b/arch/arm/mach-exynos/Kconfig
@@ -167,4 +167,3 @@
default "board/samsung/common/exynos-uboot-spl.lds" if ARCH_EXYNOS5 || ARCH_EXYNOS4
endif
-
diff --git a/arch/arm/mach-highbank/Kconfig b/arch/arm/mach-highbank/Kconfig
index 516f2e4..0e73c04 100644
--- a/arch/arm/mach-highbank/Kconfig
+++ b/arch/arm/mach-highbank/Kconfig
@@ -10,4 +10,3 @@
default "highbank"
endif
-
diff --git a/arch/arm/mach-imx/Kconfig b/arch/arm/mach-imx/Kconfig
index a1ea3a2..a1566cc 100644
--- a/arch/arm/mach-imx/Kconfig
+++ b/arch/arm/mach-imx/Kconfig
@@ -78,4 +78,3 @@
NXP boards based on i.MX6/7 contain the board revision information
stored in the fuses. Select this option if you want to be able to
retrieve the board revision information.
-
diff --git a/arch/arm/mach-imx/imx8/Kconfig b/arch/arm/mach-imx/imx8/Kconfig
index d07d84d..0d3a87c 100644
--- a/arch/arm/mach-imx/imx8/Kconfig
+++ b/arch/arm/mach-imx/imx8/Kconfig
@@ -24,4 +24,3 @@
source "board/freescale/imx8qxp_mek/Kconfig"
endif
-
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 5239191..317dee9 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/mach-imx/imx8m/Kconfig
@@ -21,4 +21,3 @@
source "board/freescale/imx8mq_evk/Kconfig"
endif
-
diff --git a/arch/arm/mach-imx/mx2/Kconfig b/arch/arm/mach-imx/mx2/Kconfig
index f2762ae..ea308fc 100644
--- a/arch/arm/mach-imx/mx2/Kconfig
+++ b/arch/arm/mach-imx/mx2/Kconfig
@@ -28,4 +28,3 @@
source "board/syteco/zmx25/Kconfig"
endif
-
diff --git a/arch/arm/mach-imx/mx3/Kconfig b/arch/arm/mach-imx/mx3/Kconfig
index c5e848b..5028d5e 100644
--- a/arch/arm/mach-imx/mx3/Kconfig
+++ b/arch/arm/mach-imx/mx3/Kconfig
@@ -32,4 +32,3 @@
source "board/freescale/mx31pdk/Kconfig"
endif
-
diff --git a/arch/arm/mach-imx/mx5/Kconfig b/arch/arm/mach-imx/mx5/Kconfig
index 378b809..29051c4 100644
--- a/arch/arm/mach-imx/mx5/Kconfig
+++ b/arch/arm/mach-imx/mx5/Kconfig
@@ -98,4 +98,3 @@
source "board/technologic/ts4800/Kconfig"
endif
-
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig
index 1960e3e..3d56346 100644
--- a/arch/arm/mach-imx/mx6/Kconfig
+++ b/arch/arm/mach-imx/mx6/Kconfig
@@ -573,4 +573,3 @@
source "board/warp/Kconfig"
endif
-
diff --git a/arch/arm/mach-imx/mx7/Kconfig b/arch/arm/mach-imx/mx7/Kconfig
index 75ffff9..232f332 100644
--- a/arch/arm/mach-imx/mx7/Kconfig
+++ b/arch/arm/mach-imx/mx7/Kconfig
@@ -72,4 +72,3 @@
source "board/warp7/Kconfig"
endif
-
diff --git a/arch/arm/mach-imx/mx7ulp/Kconfig b/arch/arm/mach-imx/mx7ulp/Kconfig
index a157071..d4b0299 100644
--- a/arch/arm/mach-imx/mx7ulp/Kconfig
+++ b/arch/arm/mach-imx/mx7ulp/Kconfig
@@ -16,4 +16,3 @@
source "board/freescale/mx7ulp_evk/Kconfig"
endif
-
diff --git a/arch/arm/mach-imx/mxs/Kconfig b/arch/arm/mach-imx/mxs/Kconfig
index 69b7386..68072d5 100644
--- a/arch/arm/mach-imx/mxs/Kconfig
+++ b/arch/arm/mach-imx/mxs/Kconfig
@@ -72,4 +72,3 @@
source "board/technologic/ts4600/Kconfig"
endif
-
diff --git a/arch/arm/mach-integrator/Kconfig b/arch/arm/mach-integrator/Kconfig
index bcc8dd4..d506ee5 100644
--- a/arch/arm/mach-integrator/Kconfig
+++ b/arch/arm/mach-integrator/Kconfig
@@ -57,4 +57,3 @@
default 0x2000
endmenu
-
diff --git a/arch/arm/mach-k3/Kconfig b/arch/arm/mach-k3/Kconfig
index 45b06cc..e677a2e 100644
--- a/arch/arm/mach-k3/Kconfig
+++ b/arch/arm/mach-k3/Kconfig
@@ -67,4 +67,3 @@
source "board/ti/am65x/Kconfig"
endif
-
diff --git a/arch/arm/mach-keystone/Kconfig b/arch/arm/mach-keystone/Kconfig
index 327f7a6..d24596e 100644
--- a/arch/arm/mach-keystone/Kconfig
+++ b/arch/arm/mach-keystone/Kconfig
@@ -38,4 +38,3 @@
source "board/ti/ks2_evm/Kconfig"
endif
-
diff --git a/arch/arm/mach-kirkwood/Kconfig b/arch/arm/mach-kirkwood/Kconfig
index daa237b..3b860c4 100644
--- a/arch/arm/mach-kirkwood/Kconfig
+++ b/arch/arm/mach-kirkwood/Kconfig
@@ -91,4 +91,3 @@
source "board/alliedtelesis/SBx81LIFXCAT/Kconfig"
endif
-
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig
index ba7e0c6..7a733e9 100644
--- a/arch/arm/mach-mediatek/Kconfig
+++ b/arch/arm/mach-mediatek/Kconfig
@@ -37,4 +37,3 @@
source "board/mediatek/mt7629/Kconfig"
endif
-
diff --git a/arch/arm/mach-meson/Kconfig b/arch/arm/mach-meson/Kconfig
index 4435f18..8fd69c3 100644
--- a/arch/arm/mach-meson/Kconfig
+++ b/arch/arm/mach-meson/Kconfig
@@ -43,6 +43,54 @@
help
Select this if your SoC is an A113X/D
+config MESON_A1
+ bool "A1"
+ select ARM64
+ select DM
+ select DM_SERIAL
+ help
+ Support Amlogic Meson A1 (A1 etc..)
+
+config MESON_C1
+ bool "C1"
+ select ARM64
+ select DM
+ select DM_SERIAL
+ help
+ Support Amlogic Meson C1
+
+config MESON_S4
+ bool "S4"
+ select ARM64
+ select DM
+ select DM_SERIAL
+ help
+ Support Amlogic Meson S4
+
+config MESON_SC2
+ bool "SC2"
+ select ARM64
+ select DM
+ select DM_SERIAL
+ help
+ Support Amlogic Meson SC2
+
+config MESON_T7
+ bool "T7"
+ select ARM64
+ select DM
+ select DM_SERIAL
+ help
+ Support Amlogic Meson T7
+
+config MESON_C2
+ bool "C2"
+ select ARM64
+ select DM
+ select DM_SERIAL
+ help
+ Support Amlogic Meson C2
+
config MESON_G12A
bool "G12A"
select ARM64
@@ -61,137 +109,9 @@
endchoice
-config AML_BL33_COMPRESS_ENABLE
- bool "Amlogic U-boot compress"
- help
- Support U-boot compress function
-
-config AML_SECURE_BOOT_V3
- bool "Amlogic SecureBoot V3"
- help
- "Support Amlogic SecureBoot V3 version"
-
-config FIP_IMG_SUPPORT
- bool "Amlogic FIP IMG format file"
- help
- "Support Amlogic FIP IMG format"
-
-config AML_SECURE_UBOOT
- bool "Amlogic SecureBoot function"
- help
- "Support Amlogic SecureBoot function"
-
-config AML_CRYPTO_UBOOT
- bool "Encrypt Amlogic U-boot"
- help
- "Support U-boot encrypt function"
-
-config AML_TSENSOR
- bool "Amlogic Temp Sensor"
- help
- "Support Amlogic Thermal Sensor"
-
-config AML_TSENSOR_COOL
- bool "Amlogic HIGH TEMP COOL"
- depends on AML_TSENSOR
- help
- "Support Amlogic High Temperature Cool"
-
-config AML_OSCRING
- bool "Amlogic OSCRING MSR"
- help
- "Support Amlogic chip oscring msr"
-
-if MESON_GXBB
-
-config TARGET_ODROID_C2
- bool "ODROID-C2"
- help
- ODROID-C2 is a single board computer based on Meson GXBaby
- with 2 GiB of RAM, Gigabit Ethernet, HDMI, 4 USB, micro-SD
- slot, eMMC, IR receiver and a 40-pin GPIO header.
-
-endif
-
-if MESON_GXL
-
-config SYS_SOC
- default "gxl"
-
-config TARGET_P212
- bool "P212"
- help
- P212 is a reference dessign board based on Meson GXL S905X SoC
- with 2 GiB of RAM, Ethernet, HDMI, 2 USB, micro-SD slot,
- eMMC, IR receiver, CVBS+Audio jack and a SDIO WiFi module.
-
-config TARGET_LIBRETECH_CC
- bool "LIBRETECH-CC"
- help
- LibreTech CC is a single board computer based on Meson GXL
- with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
- eMMC, IR receiver and a 40-pin GPIO header.
-
-config TARGET_KHADAS_VIM
- bool "KHADAS-VIM"
- help
- Khadas VIM is a single board computer based on Meson GXL
- with 2 GiB of RAM, Ethernet, HDMI, 4 USB, micro-SD slot,
- eMMC, IR receiver and a 40-pin GPIO header.
-
-endif
-
-# G12A series boards
-
-if MESON_G12A
-
-config SYS_SOC
- default "g12a"
-
-config TARGET_G12A_U200_V1
- bool "G12A_U200_V1"
-
-config TARGET_G12A_U211_V1
- bool "G12A_U211_V1"
-
-config TARGET_SM1_ELAINE_P1
- bool "SM1_ELAINE_P1"
-
-config TARGET_SM1_ELAINE_P2
- bool "SM1_ELAINE_P2"
-
-config TARGET_SM1_ELAINE_B1
- bool "SM1_ELAINE_B1"
-
-config TARGET_SM1_ELAINE_BX
- bool "SM1_ELAINE_BX"
-
-endif
-
-if MESON_G12B
-
-config SYS_SOC
- default "g12b"
-
-config TARGET_G12B_W400_V1
- bool "G12B_W400_V1"
-
-config TARGET_G12B_NEWMAN_PX
- bool "G12B_NEWMAN_PX"
-
-config TARGET_G12B_NEWMAN_BX
- bool "G12B_NEWMAN_BX"
-
-config TARGET_G12B_PUDDY_PX
- bool "G12B_PUDDY_PX"
-
-endif
-
-
config SYS_MALLOC_F_LEN
default 0x1000
source "board/amlogic/Kconfig"
endif
-
diff --git a/arch/arm/mach-meson/Makefile b/arch/arm/mach-meson/Makefile
index ee492cd..6ed4a1f 100644
--- a/arch/arm/mach-meson/Makefile
+++ b/arch/arm/mach-meson/Makefile
@@ -3,7 +3,12 @@
# Copyright (c) 2016 Beniamino Galvani <b.galvani@gmail.com>
#obj-y += board-common.o sm.o
+obj-y += cpu_id.o
obj-$(CONFIG_MESON_GX) += board-gx.o
obj-$(CONFIG_MESON_AXG) += board-axg.o
obj-$(CONFIG_ARCH_MESON) += $(SOC)/
+
+obj-$(CONFIG_AML_HW_SHA2) += hard_sha2.o
+obj-$(CONFIG_CMD_PLLTEST) += clk-pll.o clk-mpll.o
+obj-$(CONFIG_AML_ANTIROLLBACK) += anti-rollback.o
diff --git a/arch/arm/mach-meson/a1/Makefile b/arch/arm/mach-meson/a1/Makefile
new file mode 100644
index 0000000..a7b0aae
--- /dev/null
+++ b/arch/arm/mach-meson/a1/Makefile
@@ -0,0 +1,14 @@
+
+obj-y := sdio.o pinctrl_init.o
+obj-y += bl31_apis.o
+obj-y += cpu_reset.o
+obj-y += timer.o
+#obj-y += mailbox.o
+#obj-y += gate_init.o
+#obj-y += power_cal.o
+obj-$(CONFIG_CMD_PLLTEST) += pll.o
+obj-$(CONFIG_CMD_AML_MTEST) += core.o
+obj-$(CONFIG_AML_HDMITX) += hdmitx.o
+obj-y += usb.o
+obj-$(CONFIG_AML_TSENSOR) += tsensor.o
+obj-$(CONFIG_AML_OSCRING) += oscring.o
diff --git a/arch/arm/mach-meson/a1/bl31_apis.c b/arch/arm/mach-meson/a1/bl31_apis.c
new file mode 100644
index 0000000..4aadd1a
--- /dev/null
+++ b/arch/arm/mach-meson/a1/bl31_apis.c
@@ -0,0 +1,502 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ * Trustzone API
+ */
+
+#include <asm/arch/io.h>
+#include <asm/arch/efuse.h>
+#include <asm/cache.h>
+#include <asm/arch/bl31_apis.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+
+static long sharemem_input_base;
+static long sharemem_output_base;
+
+long get_sharemem_info(unsigned long function_id)
+{
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ : "+r" (function_id));
+
+ return function_id;
+}
+
+int32_t set_boot_params(const keymaster_boot_params *boot_params)
+{
+ /* Fake function for the reason that set_boot_params is not
+ * supported for this platform */
+ return -1;
+}
+
+#ifdef CONFIG_EFUSE
+int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg)
+{
+ int ret;
+ unsigned cmd, offset, size;
+ unsigned long *retcnt = (unsigned long *)(arg->retcnt_phy);
+
+ if (!sharemem_input_base)
+ sharemem_input_base =
+ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE);
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ if (arg->cmd == EFUSE_HAL_API_READ)
+ cmd = EFUSE_READ;
+ else if (arg->cmd == EFUSE_HAL_API_WRITE)
+ cmd = EFUSE_WRITE;
+ else
+ cmd = EFUSE_WRITE_PATTERN;
+ offset = arg->offset;
+ size = arg->size;
+
+ if (arg->cmd == EFUSE_HAL_API_WRITE) {
+ memcpy((void *)sharemem_input_base,
+ (const void *)arg->buffer_phy, size);
+ flush_cache(sharemem_input_base, size);
+ }
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = cmd;
+ register uint64_t x1 asm("x1") = offset;
+ register uint64_t x2 asm("x2") = size;
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2));
+ } while (0);
+ ret = x0;
+ *retcnt = x0;
+
+ if ((arg->cmd == EFUSE_HAL_API_READ) && (ret != 0)) {
+ flush_cache(sharemem_output_base, ret);
+ memcpy((void *)arg->buffer_phy,
+ (const void *)sharemem_output_base, ret);
+ }
+
+ if (!ret)
+ return -1;
+ else
+ return 0;
+}
+
+int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg)
+{
+ int32_t ret;
+ unsigned cmd = 0;
+
+ if (arg->cmd == EFUSE_HAL_API_USER_MAX)
+ cmd = EFUSE_USER_MAX;
+
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = cmd;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0));
+ } while (0);
+ ret = x0;
+
+ if (!ret)
+ return -1;
+ else
+ return ret;
+}
+
+ssize_t meson_trustzone_efuse_writepattern(const char *buf, size_t count)
+{
+ struct efuse_hal_api_arg arg;
+ unsigned long retcnt;
+
+ if (count != EFUSE_BYTES)
+ return 0; /* Past EOF */
+
+ arg.cmd = EFUSE_HAL_API_WRITE_PATTERN;
+ arg.offset = 0;
+ arg.size = count;
+ arg.buffer_phy = (unsigned long)buf;
+ arg.retcnt_phy = (unsigned long)&retcnt;
+ int ret;
+ ret = meson_trustzone_efuse(&arg);
+ return ret;
+}
+#endif
+
+uint64_t meson_trustzone_efuse_check(unsigned char *addr)
+{
+ uint64_t ret = 0;
+ struct sram_hal_api_arg arg = {};
+
+ arg.cmd = SRAM_HAL_API_CHECK_EFUSE;
+ arg.req_len = 0x1000000;
+ arg.res_len = 0;
+ arg.req_phy_addr = (unsigned long)addr;
+ arg.res_phy_addr = (unsigned long)NULL;
+
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = CALL_TRUSTZONE_HAL_API;
+ register uint64_t x1 asm("x1") = TRUSTZONE_HAL_API_SRAM;
+ register uint64_t x2 asm("x2") = (unsigned long)(&arg);
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2));
+ } while (0);
+
+ ret = x0;
+
+ return ret;
+}
+
+void debug_efuse_cmd(unsigned long cmd)
+{
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ : : "r" (cmd));
+}
+
+void bl31_debug_efuse_write_pattern(const char *buf)
+{
+ if (!sharemem_input_base)
+ sharemem_input_base =
+ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE);
+ memcpy((void *)sharemem_input_base, (const void *)buf, 512);
+
+ debug_efuse_cmd(DEBUG_EFUSE_WRITE_PATTERN);
+}
+
+void bl31_debug_efuse_read_pattern(char *buf)
+{
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+ debug_efuse_cmd(DEBUG_EFUSE_READ_PATTERN);
+
+ memcpy((void *)buf, (const void *)sharemem_output_base, 512);
+}
+
+void aml_set_jtag_state(unsigned state, unsigned select)
+{
+ uint64_t command;
+ if (state == JTAG_STATE_ON)
+ command = JTAG_ON;
+ else
+ command = JTAG_OFF;
+ asm __volatile__("" : : : "memory");
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : : "r" (command), "r"(select));
+}
+
+void wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value)
+{
+ register long x0 asm("x0") = 0x82000086;
+ register long x1 asm("x1") = cmd;
+ register long x2 asm("x2") = value;
+ register long x3 asm("x3") = 0;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+}
+
+unsigned aml_get_reboot_reason(void)
+{
+ unsigned reason;
+ uint64_t ret;
+
+ register uint64_t x0 asm("x0") = GET_REBOOT_REASON;
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ :"+r"(x0));
+ ret = x0;
+ reason = (unsigned)(ret&0xffffffff);
+ return reason;
+}
+
+void set_viu_probe_enable(void)
+{
+ register uint64_t x0 asm("x0") = VIU_PREOBE_EN;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ :"+r"(x0));
+}
+
+void power_set_dsp(unsigned int id, unsigned int powerflag)
+{
+ register long x0 asm("x0") = DSP_SEC_POWERSET;
+ register long x1 asm("x1") = id;
+ register long x2 asm("x2") = powerflag;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2));
+}
+
+void init_dsp(unsigned int id,unsigned int addr,unsigned int cfg0)
+{
+ register long x0 asm("x0") = START_HIFI4;
+ register long x1 asm("x1") = id;
+ register long x2 asm("x2") = addr;
+ register long x3 asm("x3") = cfg0;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+}
+
+
+unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2)
+{
+ register long x0 asm("x0") = function_id;
+ register long x1 asm("x1") = arg0;
+ register long x2 asm("x2") = arg1;
+ register long x3 asm("x3") = arg2;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+
+ return function_id;
+}
+
+void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2)
+{
+ register long x0 asm("x0") = function_id;
+ register long x1 asm("x1") = arg0;
+ register long x2 asm("x2") = arg1;
+ register long x3 asm("x3") = arg2;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+
+ return ;
+}
+
+unsigned long aml_sec_boot_check(unsigned long nType,
+ unsigned long pBuffer,
+ unsigned long nLength,
+ unsigned long nOption)
+{
+ uint64_t ret = 1;
+
+//#define AML_SECURE_LOG_TE
+
+#if defined(AML_SECURE_LOG_TE)
+ #define AML_GET_TE(a) do{a = *((volatile unsigned int*)0xc1109988);}while(0);
+ unsigned nT1,nT2,nT3;
+#else
+ #define AML_GET_TE(...)
+#endif
+
+ AML_GET_TE(nT1);
+
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = AML_DATA_PROCESS;
+ register uint64_t x1 asm("x1") = nType;
+ register uint64_t x2 asm("x2") = pBuffer;
+ register uint64_t x3 asm("x3") = nLength;
+ register uint64_t x4 asm("x4") = nOption;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ __asmeq("%4", "x3")
+ __asmeq("%5", "x4")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2),"r"(x3),"r"(x4));
+ } while (0);
+
+ ret = x0;
+
+ AML_GET_TE(nT2);;
+
+ flush_dcache_range((unsigned long )pBuffer, (unsigned long )pBuffer+nLength);
+
+ AML_GET_TE(nT3);
+
+#if defined(AML_SECURE_LOG_TE)
+ printf("aml log : dec use %d(us) , flush cache used %d(us)\n",
+ nT2 - nT1, nT3 - nT2);
+#endif
+
+ return ret;
+}
+
+void set_usb_boot_function(unsigned long command)
+{
+ register long x0 asm("x0") = SET_USB_BOOT_FUNC;
+ register long x1 asm("x1") = command;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+}
+
+void set_boot_first_timeout(uint64_t arg0)
+{
+ register long x0 asm("x0") = SET_BOOT_FIRST;
+ register long x1 asm("x1") = arg0;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+}
+void aml_system_off(void)
+{
+ /* TODO: Add poweroff capability */
+ aml_reboot(0x82000042, 1, 0, 0);
+ aml_reboot(0x84000008, 0, 0, 0);
+}
+
+int __get_chip_id(unsigned char *buff, unsigned int size)
+{
+ if (buff == NULL || size < 16)
+ return -1;
+
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ if (sharemem_output_base) {
+ register long x0 asm("x0") = GET_CHIP_ID;
+ register long x1 asm("x1") = 2;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+
+ if (x0 == 0) {
+ int version = *((unsigned int *)sharemem_output_base);
+
+ if (version == 2) {
+ memcpy(buff, (void *)sharemem_output_base + 4, 16);
+ }
+ else {
+ /**
+ * Legacy 12-byte chip ID read out, transform data
+ * to expected order format.
+ */
+ uint32_t chip_info = 0;//readl(P_AO_SEC_SD_CFG8);
+ uint8_t *ch;
+ int i;
+
+ ((uint32_t *)buff)[0] =
+ ((chip_info & 0xff000000) | // Family ID
+ ((chip_info << 8) & 0xff0000) | // Chip Revision
+ ((chip_info >> 8) & 0xff00)); // Package ID
+
+ ((uint32_t *)buff)[0] = htonl(((uint32_t *)buff)[0]);
+
+ /* Transform into expected order for display */
+ ch = (uint8_t *)(sharemem_output_base + 4);
+ for (i = 0; i < 12; i++)
+ buff[i + 4] = ch[11 - i];
+ }
+
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
+int bl31_get_cornerinfo(uint8_t *outbuf, int size)
+{
+ int buff_len = 0;
+
+ if (outbuf == NULL) {
+ printf("BL33: corner efuse info storebuf is NULL\n");
+ return -1;
+ }
+
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ if (sharemem_output_base) {
+ register long x0 asm("x0") = OSCRING_EFUSE_GET;
+ register long x1 asm("x1") = size;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+ } while(0);
+ buff_len = x0;
+ if (buff_len <= size) {
+ memcpy(outbuf, (void *)sharemem_output_base, buff_len);
+ return 0;
+ } else {
+ printf("BL33: corner efuse info buf len %d over storebuf size %d\n", buff_len, size);
+ return -1;
+ }
+ }
+ return -1;
+}
diff --git a/arch/arm/mach-meson/a1/core.c b/arch/arm/mach-meson/a1/core.c
new file mode 100644
index 0000000..8640828
--- /dev/null
+++ b/arch/arm/mach-meson/a1/core.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/types.h>
+#include <asm/arch/cpu.h>
+#include <common.h>
+
+const unsigned int core_map[] = {
+ 0x0,
+ 0x1,
+ 0x2,
+ 0x3,
+};
+
+int get_core_mpidr(unsigned int cpuid)
+{
+ unsigned int coremax = (unsigned int)(sizeof(core_map)/sizeof(unsigned int));
+
+ if (cpuid >= coremax)
+ return -1;
+ return core_map[cpuid];
+}
+
+int get_core_idx(unsigned int mpidr)
+{
+ unsigned int clusterid, cpuid;
+
+ cpuid = mpidr & 0xff;
+ clusterid = mpidr & 0xff00;
+
+ cpuid += (clusterid >> 6);
+
+ if (cpuid >= NR_CPUS)
+ return -1;
+
+ return cpuid;
+}
+
+int get_core_max(void)
+{
+ return (sizeof(core_map)/sizeof(unsigned int));
+}
diff --git a/arch/arm/mach-meson/a1/cpu_reset.c b/arch/arm/mach-meson/a1/cpu_reset.c
new file mode 100644
index 0000000..ca0a42d
--- /dev/null
+++ b/arch/arm/mach-meson/a1/cpu_reset.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/types.h>
+#include <asm/arch/romboot.h>
+#include <asm/arch/cpu_reset.h>
+#include <asm/arch/io.h>
+#include <asm/arch/timer.h>
+#include <dm.h>
+#include <wdt.h>
+
+/*
+ *GPIOE_0 VDDEE_PWM
+ *GPIOE_1 VDDCPU_PWM
+ * */
+void set_pwm_to_input(void)
+{
+ //hxbao, need fine tune
+ #if 0
+ unsigned int val;
+
+ val = readl(AO_RTI_PINMUX_REG1);
+ val &= ~(0xff << 16);
+ writel(val, AO_RTI_PINMUX_REG1);/* clear pinmux */
+ val = readl(AO_GPIO_O_EN_N);
+ val &= ~(0x3 << 16);
+ val |= 0x3 << 16;
+ writel(val, AO_GPIO_O_EN_N);/* set input mode */
+ val = readl(AO_RTI_PULL_UP_EN_REG);
+ val &= ~(0x3 << 16);
+ writel(val, AO_RTI_PULL_UP_EN_REG);/* disable pull up/down */
+ #endif
+}
+
+void reset_system(void)
+{
+ struct udevice *watchdog_devp;
+ int ret;
+
+ set_pwm_to_input();
+
+ _udelay(10000); //wait print
+
+ ret = uclass_get_device_by_name(UCLASS_WDT, "watchdog", &watchdog_devp);
+ if (ret < 0) {
+ printf("failed to reset system because can't get wdt device\n");
+ return;
+ }
+ wdt_start(watchdog_devp, 0, 0);
+ while (1);
+}
+
+/* uboot reset interface */
+void reset_cpu(unsigned long flag){
+ reset_system();
+}
diff --git a/arch/arm/mach-meson/a1/firmware/acs/Makefile b/arch/arm/mach-meson/a1/firmware/acs/Makefile
new file mode 100644
index 0000000..70d2d83
--- /dev/null
+++ b/arch/arm/mach-meson/a1/firmware/acs/Makefile
@@ -0,0 +1,431 @@
+#
+# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of ARM nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+#
+# Default values for build configurations
+#
+
+export CROSS_COMPILE=/opt/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-
+
+include $(buildsrc)/config.mk
+include $(buildtree)/include/autoconf.mk
+include $(buildtree)/.config
+
+# Build verbosity
+V := 0
+# Debug build
+BUILD_TYPE := ${BL2_BUILD_TYPE}
+# Build architecture
+ARCH := aarch64
+# Build platform
+#DEFAULT_PLAT := gx
+PLAT := ${SOC}
+export PLAT
+# SPD choice
+SPD := none
+# Base commit to perform code check on
+BASE_COMMIT := origin/master
+# NS timer register save and restore
+NS_TIMER_SWITCH := 0
+# By default, Bl1 acts as the reset handler, not BL31
+RESET_TO_BL31 := 0
+
+# Checkpatch ignores
+CHECK_IGNORE = --ignore COMPLEX_MACRO
+
+CHECKPATCH_ARGS = --no-tree --no-signoff ${CHECK_IGNORE}
+CHECKCODE_ARGS = --no-patch --no-tree --no-signoff ${CHECK_IGNORE}
+
+ifeq (${V},0)
+ Q=@
+ CHECKCODE_ARGS += --no-summary --terse
+else
+ Q=
+endif
+export Q
+
+ifeq (${GIT_VERSION},)
+ GIT_VERSION := $(shell git describe --abbrev=7 --dirty --always --tags)
+endif
+ifeq (${BUILDER},)
+ BUILDER := ${USER}@$(shell hostname)
+endif
+
+BL_COMMON_SOURCES := common/bl_common.c \
+ common/debug.c \
+ lib/aarch64/cache_helpers.S \
+ lib/aarch64/misc_helpers.S \
+ lib/aarch64/tlb_helpers.S \
+ lib/aarch64/xlat_helpers.c \
+ lib/stdlib/std.c \
+ lib/io_storage.c \
+ plat/common/aarch64/platform_helpers.S
+
+BUILD_BASE := $(buildtree)/firmware
+#BUILD_PLAT := ${BUILD_BASE}/${PLAT}
+BUILD_PLAT := $(buildtree)/board/${BOARDDIR}/firmware
+#BUILD_PLAT := $(buildtree)/${BOARDDIR}/firmware
+
+# Convenience function for adding build definitions
+# $(eval $(call add_define,FOO)) will have:
+# -DFOO if $(FOO) is empty; -DFOO=$(FOO) otherwise
+define add_define
+DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
+endef
+
+# Convenience function for verifying option has a boolean value
+# $(eval $(call assert_boolean,FOO)) will assert FOO is 0 or 1
+define assert_boolean
+$(and $(patsubst 0,,$(value $(1))),$(patsubst 1,,$(value $(1))),$(error $(1) must be boolean))
+endef
+
+ifeq (${PLAT},)
+ $(error "Error: Unknown platform. Please use PLAT=<platform name> to specify the platform.")
+endif
+
+all: msg_start
+
+msg_start:
+ @echo "Building ${BOARDDIR}/acs.bin"
+
+#include plat/${PLAT}/platform.mk
+#ifdef BL2_SOURCES
+NEED_BL2 := yes
+include acs.mk
+#endif
+
+# Include SPD Makefile if one has been specified
+ifneq (${SPD},none)
+ # We expect to locate an spd.mk under the specified SPD directory
+ SPD_MAKE := $(shell m="services/spd/${SPD}/${SPD}.mk"; [ -f "$$m" ] && echo "$$m")
+
+ ifeq (${SPD_MAKE},)
+ $(error Error: No services/spd/${SPD}/${SPD}.mk located)
+ endif
+ $(info Including ${SPD_MAKE})
+ include ${SPD_MAKE}
+
+ # If there's BL32 companion for the chosen SPD, and the SPD wants to build the
+ # BL2 from source, we expect that the SPD's Makefile would set NEED_BL32
+ # variable to "yes"
+endif
+
+.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool fip
+.SUFFIXES:
+
+INCLUDES += -Iinclude/bl2 \
+ -Iinclude/bl31 \
+ -Iinclude/common \
+ -Iinclude/drivers \
+ -Iinclude/drivers/arm \
+ -Iinclude/drivers/serial \
+ -Iinclude/lib \
+ -Iinclude/lib/aarch64 \
+ -Iinclude/plat/common \
+ -Iinclude/stdlib \
+ -Iinclude/stdlib/sys \
+ ${PLAT_INCLUDES} \
+ ${SPD_INCLUDES}
+
+# Process DEBUG flag
+$(eval $(call assert_boolean,DEBUG))
+$(eval $(call add_define,DEBUG))
+ifeq (${DEBUG},0)
+ $(eval $(call add_define,NDEBUG))
+else
+CFLAGS += -g
+ASFLAGS += -g -Wa,--gdwarf-2
+endif
+
+# Process NS_TIMER_SWITCH flag
+$(eval $(call assert_boolean,NS_TIMER_SWITCH))
+$(eval $(call add_define,NS_TIMER_SWITCH))
+
+# Process RESET_TO_BL31 flag
+$(eval $(call assert_boolean,RESET_TO_BL31))
+$(eval $(call add_define,RESET_TO_BL31))
+
+VPATH_LIST = $(buildsrc)/board/$(BOARDDIR)
+#VPATH_LIST = $(buildsrc)/$(BOARDDIR)
+VPATH_LIST:=$(VPATH_LIST:%=%/firmware/)
+
+vpath %.c $(VPATH_LIST)
+
+ASFLAGS += -nostdinc -ffreestanding -Wa,--fatal-warnings \
+ -mgeneral-regs-only -D__ASSEMBLY__ \
+ ${DEFINES} ${INCLUDES}
+CFLAGS += -nostdinc -pedantic -ffreestanding -Wall \
+ -Werror -mgeneral-regs-only -std=c99 -c -Os \
+ ${DEFINES} ${INCLUDES} $(VPATH_LIST:%=-I%)
+CFLAGS += -ffunction-sections -fdata-sections
+ASFLAGS += ${FIRMWARE_CPPFLAGS}
+CFLAGS += ${FIRMWARE_CPPFLAGS}
+CFLAGS += -Wno-unused
+
+LDFLAGS += --fatal-warnings -O1
+LDFLAGS += --gc-sections
+
+CC := ${CROSS_COMPILE}gcc
+CPP := ${CROSS_COMPILE}cpp
+AS := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OC := ${CROSS_COMPILE}objcopy
+OD := ${CROSS_COMPILE}objdump
+NM := ${CROSS_COMPILE}nm
+PP := ${CROSS_COMPILE}gcc -E ${CFLAGS}
+
+# Variables for use with Firmware Image Package
+FIPTOOLPATH ?= tools/fip_create
+FIPTOOL ?= ${FIPTOOLPATH}/fip_create
+fiptool: ${FIPTOOL}
+fip: ${BUILD_PLAT}/fip.bin
+
+locate-checkpatch:
+ifndef CHECKPATCH
+ $(error "Please set CHECKPATCH to point to the Linux checkpatch.pl file, eg: CHECKPATCH=../linux/script/checkpatch.pl")
+else
+ifeq (,$(wildcard ${CHECKPATCH}))
+ $(error "The file CHECKPATCH points to cannot be found, use eg: CHECKPATCH=../linux/script/checkpatch.pl")
+endif
+endif
+
+clean:
+ @echo " CLEAN"
+ ${Q}rm -rf ${BUILD_PLAT}
+ ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
+
+realclean distclean:
+ @echo " REALCLEAN"
+ ${Q}rm -rf ${BUILD_BASE}
+ ${Q}rm -f ${CURDIR}/cscope.*
+ ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
+
+checkcodebase: locate-checkpatch
+ @echo " CHECKING STYLE"
+ @if test -d .git ; then \
+ git ls-files | while read GIT_FILE ; do ${CHECKPATCH} ${CHECKCODE_ARGS} -f $$GIT_FILE ; done ; \
+ else \
+ find . -type f -not -iwholename "*.git*" -not -iwholename "*build*" -exec ${CHECKPATCH} ${CHECKCODE_ARGS} -f {} \; ; \
+ fi
+
+checkpatch: locate-checkpatch
+ @echo " CHECKING STYLE"
+ @git format-patch --stdout ${BASE_COMMIT} | ${CHECKPATCH} ${CHECKPATCH_ARGS} - || true
+
+${FIPTOOL}:
+ ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH}
+ @echo
+ @echo "Built $@ successfully"
+ @echo
+
+define match_goals
+$(strip $(foreach goal,$(1),$(filter $(goal),$(MAKECMDGOALS))))
+endef
+
+# List of rules that involve building things
+BUILD_TARGETS := all bl1 bl2 bl31 bl32 fip
+
+# Does the list of goals specified on the command line include a build target?
+ifneq ($(call match_goals,${BUILD_TARGETS}),)
+IS_ANYTHING_TO_BUILD := 1
+endif
+
+define MAKE_C
+
+$(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2))))
+$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ)))
+
+$(OBJ) : $(2)
+ @echo " CC $$<"
+ $$(Q)$$(CC) $$(CFLAGS) -c $$< -o $$@
+
+
+$(PREREQUISITES) : $(2)
+ @echo " DEPS $$@"
+ @mkdir -p $(1)
+ $$(Q)$$(CC) $$(CFLAGS) -M -MT $(OBJ) -MF $$@ $$<
+
+ifdef IS_ANYTHING_TO_BUILD
+-include $(PREREQUISITES)
+endif
+
+endef
+
+
+define MAKE_S
+
+$(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2))))
+$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ)))
+
+$(OBJ) : $(2)
+ @echo " AS $$<"
+ $$(Q)$$(AS) $$(ASFLAGS) -c $$< -o $$@
+
+$(PREREQUISITES) : $(2)
+ @echo " DEPS $$@"
+ @mkdir -p $(1)
+ $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(OBJ) -MF $$@ $$<
+
+ifdef IS_ANYTHING_TO_BUILD
+-include $(PREREQUISITES)
+endif
+
+endef
+
+
+define MAKE_LD
+
+$(eval PREREQUISITES := $(1).d)
+
+$(1) : $(2)
+ @echo " PP $$<"
+ $$(Q)$$(AS) $$(ASFLAGS) -P -E -o $$@ $$<
+
+$(PREREQUISITES) : $(2)
+ @echo " DEPS $$@"
+ @mkdir -p $$(dir $$@)
+ $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(1) -MF $$@ $$<
+
+ifdef IS_ANYTHING_TO_BUILD
+-include $(PREREQUISITES)
+endif
+
+endef
+
+
+define MAKE_OBJS
+ $(eval C_OBJS := $(filter %.c,$(2)))
+ $(eval REMAIN := $(filter-out %.c,$(2)))
+ $(eval $(foreach obj,$(C_OBJS),$(call MAKE_C,$(1),$(obj))))
+
+ $(eval S_OBJS := $(filter %.S,$(REMAIN)))
+ $(eval REMAIN := $(filter-out %.S,$(REMAIN)))
+ $(eval $(foreach obj,$(S_OBJS),$(call MAKE_S,$(1),$(obj))))
+
+ $(and $(REMAIN),$(error Unexpected source files present: $(REMAIN)))
+endef
+
+
+# NOTE: The line continuation '\' is required in the next define otherwise we
+# end up with a line-feed characer at the end of the last c filename.
+# Also bare this issue in mind if extending the list of supported filetypes.
+define SOURCES_TO_OBJS
+ $(notdir $(patsubst %.c,%.o,$(filter %.c,$(1)))) \
+ $(notdir $(patsubst %.S,%.o,$(filter %.S,$(1))))
+endef
+
+define MAKE_BL
+ $(eval BUILD_DIR := ${BUILD_PLAT})
+ $(eval SOURCES := $(SOURCES))
+ $(eval OBJS := $(addprefix $(BUILD_DIR)/,$(call SOURCES_TO_OBJS,$(SOURCES))))
+ $(eval LINKERFILE := $(BUILD_DIR)/acs.ld)
+ $(eval MAPFILE := $(BUILD_DIR)/acs.map)
+ $(eval ELF := $(BUILD_DIR)/acs.elf)
+ $(eval DUMP := $(BUILD_DIR)/acs.dump)
+ $(eval BIN := $(BUILD_DIR)/acs.bin)
+
+ $(eval $(call MAKE_OBJS,$(BUILD_DIR),$(SOURCES)))
+ $(eval $(call MAKE_LD,$(LINKERFILE),$(LINKERFILE_T)))
+
+$(BUILD_DIR) :
+ $$(Q)mkdir -p "$$@"
+
+$(ELF) : $(OBJS) $(LINKERFILE)
+ @echo " LD $$@"
+ @echo 'const char build_message[] = "Built : "__TIME__", "__DATE__". \\nver:${GIT_VERSION} - ${BUILDER}";' | \
+ $$(CC) $$(CFLAGS) -xc - -o $(BUILD_DIR)/build_message.o
+ $$(Q)$$(LD) -o $$@ $$(LDFLAGS) -Map=$(MAPFILE) --script $(LINKERFILE) \
+ $(BUILD_DIR)/build_message.o $(OBJS)
+
+$(DUMP) : $(ELF)
+ @echo " OD $$@"
+ $${Q}$${OD} -dxS $$< > $$@
+
+$(BIN) : $(ELF)
+ @echo " BIN $$@"
+ $$(Q)$$(OC) -O binary $$< $$@
+ @echo
+ @echo "Built $$@ successfully"
+ @echo
+
+.PHONY : bl$(1)
+bl$(1) : $(BUILD_DIR) $(DUMP) $(BIN)
+
+all : bl$(1)
+
+$(eval FIP_DEPS += $(if $2,$(BIN),))
+$(eval FIP_ARGS += $(if $2,--bl$(1) $(BIN),))
+
+endef
+
+ifeq (${NEED_BL2},yes)
+$(eval $(call MAKE_BL,2,in_fip))
+endif
+
+${BUILD_PLAT}/fip.bin: ${FIP_DEPS} ${BL33} ${FIPTOOL}
+ $(if ${BL33},,$(error "To build a FIP, please set BL33 to point to the Normal World binary, eg: BL33=../uefi/FVP_AARCH64_EFI.fd"))
+ ${Q}${FIPTOOL} --dump \
+ ${FIP_ARGS} \
+ --bl33 ${BL33} \
+ $@
+ @echo
+ @echo "Built $@ successfully"
+ @echo
+
+
+cscope:
+ @echo " CSCOPE"
+ ${Q}find ${CURDIR} -name "*.[chsS]" > cscope.files
+ ${Q}cscope -b -q -k
+
+help:
+ @echo "usage: ${MAKE} PLAT=<${HELP_PLATFORMS}> <all|bl1|bl2|bl31|distclean|clean|checkcodebase|checkpatch>"
+ @echo ""
+ @echo "PLAT is used to specify which platform you wish to build."
+ @echo "If no platform is specified, PLAT defaults to: ${DEFAULT_PLAT}"
+ @echo ""
+ @echo "Supported Targets:"
+ @echo " all Build the BL1, BL2 and BL31 binaries"
+ @echo " bl1 Build the BL1 binary"
+ @echo " bl2 Build the BL2 binary"
+ @echo " bl31 Build the BL31 binary"
+ @echo " checkcodebase Check the coding style of the entire source tree"
+ @echo " checkpatch Check the coding style on changes in the current"
+ @echo " branch against BASE_COMMIT (default origin/master)"
+ @echo " clean Clean the build for the selected platform"
+ @echo " cscope Generate cscope index"
+ @echo " distclean Remove all build artifacts for all platforms"
+ @echo " fiptool Build the Firmware Image Package(FIP) creation tool"
+ @echo ""
+ @echo "note: most build targets require PLAT to be set to a specific platform."
+ @echo ""
+ @echo "example: build all targets for the FVP platform:"
+ @echo " CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp all"
diff --git a/arch/arm/mach-meson/a1/firmware/acs/acs.c b/arch/arm/mach-meson/a1/firmware/acs/acs.c
new file mode 100644
index 0000000..b10cd66
--- /dev/null
+++ b/arch/arm/mach-meson/a1/firmware/acs/acs.c
@@ -0,0 +1,63 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/acs.h>
+#include <asm/arch/timing.h>
+#include "timing.c"
+
+//main acs struct
+acs_set_t __acs_set={
+ .acs_magic = "acs__",
+ .chip_type = 0x0,
+ .version = 1,
+ .acs_set_length = sizeof(__acs_set),
+
+ .ddr_magic = "ddrs_",
+ .ddr_set_version= 1,
+ .ddr_set_length = sizeof(__ddr_setting),
+ .ddr_set_addr = (unsigned long)(&__ddr_setting),
+
+#if 0
+ .psram_magic = "psram",
+ .psram_set_version = 1,
+ .psram_set_length = sizeof(__psram_setting),
+ .psram_set_addr = (unsigned long)(&__psram_setting),
+#endif
+ .ddr_reg_magic = "ddrr_",
+ .ddr_reg_version= 1,
+ .ddr_reg_length = sizeof(__ddr_reg),
+ .ddr_reg_addr = (unsigned long)(&__ddr_reg),
+
+ .pll_magic = "pll__",
+ .pll_set_version= 1,
+ .pll_set_length = sizeof(__pll_setting),
+ .pll_set_addr = (unsigned long)(&__pll_setting),
+
+ .sto_magic = "store",
+ .sto_set_version= 1,
+ .sto_set_length = 0,
+ .sto_set_addr = 0,
+
+ .bl2_regs_magic = "bl2r_",
+ .bl2_regs_version = 1,
+ .bl2_regs_length = sizeof(__bl2_reg),
+ .bl2_regs_addr = (unsigned long)(&__bl2_reg),
+
+#if 1
+ .psram_magic = "psram",
+ .psram_set_version = 1,
+ .psram_set_length = sizeof(__psram_setting),
+ .psram_set_addr = (unsigned long)(&__psram_setting),
+#endif
+#if 0
+ .rsv_magic = "rsv0_",
+ .rsv_set_version= 1,
+ .rsv_set_length = 0,
+ .rsv_set_addr = 0,
+#endif
+ .board_id = {0,},
+ .ddr_struct_size = {0,},
+ .ddr_struct_org_size = sizeof(ddr_set_t),
+};
diff --git a/arch/arm/mach-meson/a1/firmware/acs/acs.ld.S b/arch/arm/mach-meson/a1/firmware/acs/acs.ld.S
new file mode 100644
index 0000000..3e5bf1d
--- /dev/null
+++ b/arch/arm/mach-meson/a1/firmware/acs/acs.ld.S
@@ -0,0 +1,19 @@
+
+OUTPUT_FORMAT("elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(acs_entry)
+
+SECTIONS
+{
+ . = 0xFFFF6000;
+
+ . : {
+ __RO_START__ = .;
+ *acs_entry.o(.text*)
+ *(.text*)
+ *(.data*)
+ *(.ddr_settings*)
+ }
+
+ //ASSERT(. <= 0xFFFF7000, "timing image has exceeded its limit.")
+}
diff --git a/arch/arm/mach-meson/a1/firmware/acs/acs.mk b/arch/arm/mach-meson/a1/firmware/acs/acs.mk
new file mode 100644
index 0000000..883a9df
--- /dev/null
+++ b/arch/arm/mach-meson/a1/firmware/acs/acs.mk
@@ -0,0 +1,9 @@
+SOURCES += acs_entry.S
+
+ifdef CONFIG_MDUMP_COMPRESS
+SOURCES += ramdump.c
+endif
+
+SOURCES += acs.c
+
+LINKERFILE_T := acs.ld.S
diff --git a/arch/arm/mach-meson/a1/firmware/acs/acs_entry.S b/arch/arm/mach-meson/a1/firmware/acs/acs_entry.S
new file mode 100644
index 0000000..feca813
--- /dev/null
+++ b/arch/arm/mach-meson/a1/firmware/acs/acs_entry.S
@@ -0,0 +1,14 @@
+
+ .globl acs_entry
+
+acs_entry:
+ .word 0
+ .word __acs_set
+#ifdef CONFIG_MDUMP_COMPRESS
+ .word __ramdump_data
+ .word __ddr_setting
+#else
+ .word 0x0
+ .word __ddr_setting
+#endif
+
diff --git a/arch/arm/mach-meson/a1/firmware/bl21/Makefile b/arch/arm/mach-meson/a1/firmware/bl21/Makefile
new file mode 100644
index 0000000..b6d7d1a
--- /dev/null
+++ b/arch/arm/mach-meson/a1/firmware/bl21/Makefile
@@ -0,0 +1,3 @@
+all:
+ @echo "BL21 no action for A1 "
+
diff --git a/arch/arm/mach-meson/a1/firmware/scp_task/Makefile b/arch/arm/mach-meson/a1/firmware/scp_task/Makefile
new file mode 100644
index 0000000..925690d
--- /dev/null
+++ b/arch/arm/mach-meson/a1/firmware/scp_task/Makefile
@@ -0,0 +1,3 @@
+all:
+ echo "BL301 no action for A1"
+
diff --git a/arch/arm/mach-meson/a1/gate_init.c b/arch/arm/mach-meson/a1/gate_init.c
new file mode 100644
index 0000000..31629f6
--- /dev/null
+++ b/arch/arm/mach-meson/a1/gate_init.c
@@ -0,0 +1,366 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "power_gate.h"
+
+#define SECUREBOOT_FLAG_ADDR 0xc8100228
+
+#ifdef CONFIG_AML_CVBS
+extern unsigned int cvbs_mode;
+#endif
+void ee_gate_off(void)
+{
+ printf("ee_gate_off ...\n");
+ return;
+/* int secureboot = readl(SECUREBOOT_FLAG_ADDR)&(1<<5);*/
+
+#ifdef CONFIG_AML_CVBS
+ unsigned int cvbs_opened = 0;
+#endif
+
+#ifdef CONFIG_AML_CVBS
+ if ((cvbs_mode == 0) || (cvbs_mode == 1))
+ cvbs_opened = 1;
+#endif
+
+ /*
+ //if close , audio maybe have noise
+ CLK_GATE_OFF(AUD);
+ CLK_GATE_OFF(AUD2);
+ CLK_GATE_OFF(AUD_CLK_2);
+ CLK_GATE_OFF(AUD_CLK_3);
+ */
+ CLK_GATE_OFF(AUD_IN);
+ CLK_GATE_OFF(AIU_AUD_MIXER);
+ CLK_GATE_OFF(SANA);
+
+ /*kernel will reopen */
+ CLK_GATE_OFF(CTS_ENCL);
+ /* CLK_GATE_OFF(CTS_ENCT); */
+#if 0 /* HDMITX 480i60hz/576i50hz need this gate */
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0)
+ CLK_GATE_OFF(CTS_ENCI);
+#else
+ CLK_GATE_OFF(CTS_ENCI);
+#endif
+#endif
+ /* CLK_GATE_OFF(CTS_ENCP); */
+
+ /*close cvbs clock*/
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0) {
+ CLK_GATE_OFF(DAC_CLK);
+ CLK_GATE_OFF(CTS_VDAC);
+ }
+#else
+ CLK_GATE_OFF(DAC_CLK);
+ CLK_GATE_OFF(CTS_VDAC);
+#endif
+
+ /* usb clock close */
+ CLK_GATE_OFF(USB0);
+ CLK_GATE_OFF(USB1);
+ //CLK_GATE_OFF(USB_CLK); //g12a no reg
+ CLK_GATE_OFF(MISC_USB0_TO_DDR);
+ CLK_GATE_OFF(MISC_USB1_TO_DDR);
+
+ /* uarts close */
+ CLK_GATE_OFF(UART0);
+ CLK_GATE_OFF(UART1);
+ CLK_GATE_OFF(UART2);
+ CLK_GATE_OFF(UART3);
+
+ CLK_GATE_OFF(VCLK2_VENCP);
+ CLK_GATE_OFF(VCLK2_VENCT);
+ CLK_GATE_OFF(VCLK2_VENCT1);
+ CLK_GATE_OFF(VCLK2_OTHER);
+#if 0 /* HDMITX 480i60hz/576i50hz need HHI_GCLK_OTHER[8][2] */
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0) {
+ CLK_GATE_OFF(VCLK2_VENCI);
+ CLK_GATE_OFF(VCLK2_VENCI1);
+ }
+#else
+ CLK_GATE_OFF(VCLK2_VENCI);
+ CLK_GATE_OFF(VCLK2_VENCI1);
+#endif
+#endif
+ CLK_GATE_OFF(VCLK2_VENCL);
+ CLK_GATE_OFF(VCLK2_OTHER1);
+#if 0 /* HDMITX 480i60hz/576i50hz need HHI_GCLK_OTHER[8][2] */
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0)
+ CLK_GATE_OFF(VCLK2_ENCI);
+#else
+ CLK_GATE_OFF(VCLK2_ENCI);
+#endif
+#endif
+ CLK_GATE_OFF(VCLK2_ENCL);
+ CLK_GATE_OFF(VCLK2_ENCT);
+
+ CLK_GATE_OFF(VDEC_CLK_1);
+ CLK_GATE_OFF(VDEC_CLK_2);
+ CLK_GATE_OFF(VDEC2_CLK_1);
+ CLK_GATE_OFF(VDEC2_CLK_2);
+ CLK_GATE_OFF(HCODEC_CLK_1);
+ CLK_GATE_OFF(HCODEC_CLK_2);
+ /* CLK_GATE_OFF(HEVC_CLK_1 ); */
+ /* CLK_GATE_OFF(HEVC_CLK_2 ); */
+
+ //CLK_GATE_OFF(MMC_A_PCLK); //g12a no reg
+ //CLK_GATE_OFF(MMC_B_PCLK); //g12a no reg
+ //CLK_GATE_OFF(MMC_C_PCLK); //g12a no reg
+
+ CLK_GATE_OFF(LCD_AN_PHY2);
+ CLK_GATE_OFF(LCD_AN_PHY3);
+
+ CLK_GATE_OFF(ETHERNET);
+ //CLK_GATE_OFF(ETH_CLK); //g12a no reg
+
+ CLK_GATE_OFF(GE2D);
+ CLK_GATE_OFF(GEN_CLK);
+ //CLK_GATE_OFF(PCM_MCLK); //g12a no reg
+ //CLK_GATE_OFF(PCM_SCLK); //g12a no reg
+
+
+ CLK_GATE_OFF(HIU_PARSER_TOP);
+
+
+ /* can not off nand_clk */
+ /* CLK_GATE_OFF(NAND_CLK); */
+ /*
+ //HDMI no output
+ CLK_GATE_OFF(VCLK2_VENCP1);
+ CLK_GATE_OFF(VCLK2_ENCP);
+ */
+
+ /*
+ //if OFF, HDMI will report error!
+ CLK_GATE_OFF(HDMI_PCLK);
+ CLK_GATE_OFF(HDMI_PLL_CNTL);
+ CLK_GATE_OFF(HDMITX_CLK);
+ */
+
+ /*
+ //PWM B used for VCCK,PWM D used for VDDEE,ignoring
+ CLK_GATE_OFF(PWM_A_CLK);
+ CLK_GATE_OFF(PWM_B_CLK);
+ CLK_GATE_OFF(PWM_C_CLK);
+ CLK_GATE_OFF(PWM_D_CLK);
+ CLK_GATE_OFF(PWM_E_CLK);
+ CLK_GATE_OFF(PWM_F_CLK);
+ */
+
+
+ /* can not close
+ CLK_GATE_OFF(VPU_CLK_1);
+ CLK_GATE_OFF(VPU_CLK_2);
+ CLK_GATE_OFF(VPU_CLKB);
+ CLK_GATE_OFF(MALI_CLK_1);
+ CLK_GATE_OFF(MALI_CLK_2);
+ CLK_GATE_OFF(ATV_DEMO_VDAC);
+ CLK_GATE_OFF(EMMC_A);
+ CLK_GATE_OFF(EMMC_B);
+ CLK_GATE_OFF(EMMC_C);
+ CLK_GATE_OFF(EMMC_A_CLK);
+ CLK_GATE_OFF(EMMC_B_CLK);
+
+ CLK_GATE_OFF(MSR_CLK);
+ CLK_GATE_OFF(MSR_HS_CLK);
+ CLK_GATE_OFF(32K_CLK);
+ CLK_GATE_OFF(VAPB_CLK_1);
+ CLK_GATE_OFF(VAPB_CLK_2);
+ CLK_GATE_OFF(GIC);
+ CLK_GATE_OFF(I2C_AO); //no close for to use
+ CLK_GATE_OFF(AO_CPU);
+ CLK_GATE_OFF(ASSIST_MISC);
+ CLK_GATE_OFF(HIU_PARSER);
+ CLK_GATE_OFF(PERIPHS_TOP);
+ CLK_GATE_OFF(PL310_CBUS);
+ CLK_GATE_OFF(ISA);
+ CLK_GATE_OFF(SECURE_AHP_APB3);
+ CLK_GATE_OFF(VPU_INTR);
+ CLK_GATE_OFF(MMC_PCLK); //can not close
+ CLK_GATE_OFF(AIU_PCLK);
+ //can not connect pc
+ CLK_GATE_OFF(USB_GENERAL);
+ CLK_GATE_OFF(AHB_DATA_BUS);
+ CLK_GATE_OFF(AHB_CONTROL_BUS);
+ CLK_GATE_OFF(HDMI_INTR_SYNC); //should open
+ //can't suspend @ 2nd time
+ //CLK_GATE_OFF(RESET);
+
+ // close rom
+ //disable this bit will make other cpu can not be booted.
+ //CLK_GATE_OFF(ROM_CLK);
+
+*/
+ /*************************/
+ CLK_GATE_OFF(AHB_ARB0);
+ CLK_GATE_OFF(ASYNC_FIFO);
+ CLK_GATE_OFF(STREAM);
+ CLK_GATE_OFF(RANDOM_NUM_GEN);
+ CLK_GATE_OFF(RANDOM_NUM_GEN1);
+ CLK_GATE_OFF(SMART_CARD_MPEG_DOMAIN);
+ CLK_GATE_OFF(I2C);
+ CLK_GATE_OFF(SPI);
+ CLK_GATE_OFF(SPICC);
+ CLK_GATE_OFF(DOS);
+ CLK_GATE_OFF(SAR_ADC);
+ CLK_GATE_OFF(MISC_DVIN);
+ CLK_GATE_OFF(BT656);
+ CLK_GATE_OFF(BT656_2);
+ CLK_GATE_OFF(PDM);
+
+ /* close AIU */
+ CLK_GATE_OFF(AIU_IEC958);
+ CLK_GATE_OFF(AIU_ICE958_AMCLK);
+
+ CLK_GATE_OFF(AIU_AMCLK_MEASURE);
+ CLK_GATE_OFF(AIU_AIFIFO2);
+ CLK_GATE_OFF(AIU_MIXER_REG);
+ CLK_GATE_OFF(AIU_ADC);
+ CLK_GATE_OFF(AIU_TOP_LEVEL);
+ CLK_GATE_OFF(AIU_AOCLK);
+ CLK_GATE_OFF(AIU_AI_TOP_GLUE);
+ CLK_GATE_OFF(AIU_I2S_OUT);
+
+ CLK_GATE_OFF(ENC480P);
+
+ CLK_GATE_OFF(DEMUX);
+/*
+* EFUSE/BLK_MOV clock gate must be on,
+ kernel storage ops depend on them.
+ it can be reference PD#112732
+*/
+/*
+ if (secureboot) {
+ printf("secure boot ignore [ BLK_MOV, efuse ] clk gate\n");
+ } else {
+ CLK_GATE_OFF(EFUSE);
+ CLK_GATE_OFF(BLK_MOV);
+ }
+*/
+}
+
+void ee_gate_on(void)
+{
+
+ printf("ee_gate_on ...\n");
+
+ /*
+ //if close , audio maybe have noise
+ CLK_GATE_ON(AUD);
+ CLK_GATE_ON(AUD2);
+ CLK_GATE_ON(AUD_CLK_2);
+ CLK_GATE_ON(AUD_CLK_3);
+ */
+ CLK_GATE_ON(AUD_IN);
+ CLK_GATE_ON(AIU_AUD_MIXER);
+ CLK_GATE_ON(SANA);
+
+ /*kernel will reopen */
+ CLK_GATE_ON(CTS_ENCL);
+ /* CLK_GATE_ON(CTS_ENCT); */
+ CLK_GATE_ON(CTS_ENCI);
+ /* CLK_GATE_ON(CTS_ENCP); */
+
+ /*close cvbs clock*/
+ CLK_GATE_ON(DAC_CLK);
+ CLK_GATE_ON(CTS_VDAC);
+
+ /* usb clock close */
+ CLK_GATE_ON(USB0);
+ CLK_GATE_ON(USB1);
+ //CLK_GATE_ON(USB_CLK); //g12a no reg
+ CLK_GATE_ON(MISC_USB0_TO_DDR);
+ CLK_GATE_ON(MISC_USB1_TO_DDR);
+
+ /* uarts close */
+ CLK_GATE_ON(UART0);
+ CLK_GATE_ON(UART1);
+ CLK_GATE_ON(UART2);
+ CLK_GATE_ON(UART3);
+
+ CLK_GATE_ON(VCLK2_VENCP);
+ CLK_GATE_ON(VCLK2_VENCT);
+ CLK_GATE_ON(VCLK2_VENCT1);
+ CLK_GATE_ON(VCLK2_OTHER);
+ CLK_GATE_ON(VCLK2_VENCI);
+ CLK_GATE_ON(VCLK2_VENCI1);
+ CLK_GATE_ON(VCLK2_VENCL);
+ CLK_GATE_ON(VCLK2_OTHER1);
+
+
+ CLK_GATE_ON(VCLK2_ENCI);
+ CLK_GATE_ON(VCLK2_ENCL);
+ CLK_GATE_ON(VCLK2_ENCT);
+
+ CLK_GATE_ON(VDEC_CLK_1);
+ CLK_GATE_ON(VDEC_CLK_2);
+ CLK_GATE_ON(VDEC2_CLK_1);
+ CLK_GATE_ON(VDEC2_CLK_2);
+ CLK_GATE_ON(HCODEC_CLK_1);
+ CLK_GATE_ON(HCODEC_CLK_2);
+ /* CLK_GATE_ON(HEVC_CLK_1 ); */
+ /* CLK_GATE_ON(HEVC_CLK_2 ); */
+
+ //CLK_GATE_ON(MMC_A_PCLK); //g12a no reg
+ //CLK_GATE_ON(MMC_B_PCLK); //g12a no reg
+ //CLK_GATE_ON(MMC_C_PCLK); //g12a no reg
+
+ CLK_GATE_ON(LCD_AN_PHY2);
+ CLK_GATE_ON(LCD_AN_PHY3);
+
+ CLK_GATE_ON(ETHERNET);
+ //CLK_GATE_ON(ETH_CLK); //g12a no reg
+
+ CLK_GATE_ON(GE2D);
+ CLK_GATE_ON(GEN_CLK);
+ //CLK_GATE_ON(PCM_MCLK); //g12a no reg
+ //CLK_GATE_ON(PCM_SCLK); //g12a no reg
+
+
+ CLK_GATE_ON(HIU_PARSER_TOP);
+
+ /*************************/
+ CLK_GATE_ON(AHB_ARB0);
+ CLK_GATE_ON(ASYNC_FIFO);
+ CLK_GATE_ON(STREAM);
+ CLK_GATE_ON(RANDOM_NUM_GEN);
+ CLK_GATE_ON(RANDOM_NUM_GEN1);
+ CLK_GATE_ON(SMART_CARD_MPEG_DOMAIN);
+ CLK_GATE_ON(I2C);
+ CLK_GATE_ON(SPI);
+ CLK_GATE_ON(SPICC);
+ CLK_GATE_ON(DOS);
+ CLK_GATE_ON(SAR_ADC);
+ CLK_GATE_ON(MISC_DVIN);
+ CLK_GATE_ON(BT656);
+ CLK_GATE_ON(BT656_2);
+ CLK_GATE_ON(PDM);
+
+ /* close AIU */
+ CLK_GATE_ON(AIU_IEC958);
+ CLK_GATE_ON(AIU_ICE958_AMCLK);
+
+ CLK_GATE_ON(AIU_AMCLK_MEASURE);
+ CLK_GATE_ON(AIU_AIFIFO2);
+ CLK_GATE_ON(AIU_MIXER_REG);
+ CLK_GATE_ON(AIU_ADC);
+ CLK_GATE_ON(AIU_TOP_LEVEL);
+ CLK_GATE_ON(AIU_AOCLK);
+ CLK_GATE_ON(AIU_AI_TOP_GLUE);
+ CLK_GATE_ON(AIU_I2S_OUT);
+
+ CLK_GATE_ON(ENC480P);
+
+ CLK_GATE_ON(DEMUX);
+
+ CLK_GATE_ON(EFUSE);
+ CLK_GATE_ON(BLK_MOV);
+}
+
diff --git a/arch/arm/mach-meson/a1/gpio.c b/arch/arm/mach-meson/a1/gpio.c
new file mode 100644
index 0000000..7332773
--- /dev/null
+++ b/arch/arm/mach-meson/a1/gpio.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <linux/compiler.h>
+#include <amlogic/aml_gpio.h>
+#include <asm/arch/gpio.h>
+
+struct pin_mux_desc {
+ unsigned char domain;
+ unsigned char reg;
+ unsigned char bit;
+};
+
+#define MUX_AO_DOMAIN 0
+#define MUX_EE_DOMAIN 1
+
+#define PIN_MUX(d, r, b) \
+{ \
+ .domain = d, \
+ .reg = r, \
+ .bit = b, \
+}
+
+#define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
+{ \
+ .name = n, \
+ .first = f, \
+ .last = l, \
+ .regs = { \
+ [REG_PULLEN] = { (0xff634520 + (per<<2)), peb }, \
+ [REG_PULL] = { (0xff6344e8 + (pr<<2)), pb }, \
+ [REG_DIR] = { (0xff634440 + (dr<<2)), db }, \
+ [REG_OUT] = { (0xff634440 + (or<<2)), ob }, \
+ [REG_IN] = { (0xff634440 + (ir<<2)), ib }, \
+ }, \
+ }
+#define AOBANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
+{ \
+ .name = n, \
+ .first = f, \
+ .last = l, \
+ .regs = { \
+ [REG_PULLEN] = { (0xff800024 + (per<<2)), peb }, \
+ [REG_PULL] = { (0xff800024 + (pr<<2)), pb }, \
+ [REG_DIR] = { (0xff800024 + (dr<<2)), db }, \
+ [REG_OUT] = { (0xff800024 + (or<<2)), ob }, \
+ [REG_IN] = { (0xff800024 + (ir<<2)), ib }, \
+ }, \
+ }
+
+static struct pin_mux_desc pin_to_gpio[] = {
+ [GPIOAO(GPIOAO_0)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 0),
+ [GPIOAO(GPIOAO_1)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 4),
+ [GPIOAO(GPIOAO_2)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 8),
+ [GPIOAO(GPIOAO_3)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 12),
+ [GPIOAO(GPIOAO_4)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 16),
+ [GPIOAO(GPIOAO_5)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 20),
+ [GPIOAO(GPIOAO_6)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 24),
+ [GPIOAO(GPIOAO_7)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 28),
+ [GPIOAO(GPIOAO_8)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 0),
+ [GPIOAO(GPIOAO_9)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 4),
+ [GPIOAO(GPIOAO_10)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 8),
+ [GPIOAO(GPIOAO_11)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 12),
+ [GPIOAO(GPIOE_0)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 16),
+ [GPIOAO(GPIOE_1)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 20),
+ [GPIOAO(GPIOE_2)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 24),
+ [GPIOEE(GPIOZ_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 0),
+ [GPIOEE(GPIOZ_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 4),
+ [GPIOEE(GPIOZ_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 8),
+ [GPIOEE(GPIOZ_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 12),
+ [GPIOEE(GPIOZ_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 16),
+ [GPIOEE(GPIOZ_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 20),
+ [GPIOEE(GPIOZ_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 24),
+ [GPIOEE(GPIOZ_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 28),
+ [GPIOEE(GPIOZ_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 0),
+ [GPIOEE(GPIOZ_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 4),
+ [GPIOEE(GPIOZ_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 8),
+ [GPIOEE(GPIOZ_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 12),
+ [GPIOEE(GPIOZ_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 16),
+ [GPIOEE(GPIOZ_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 20),
+ [GPIOEE(GPIOZ_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 24),
+ [GPIOEE(GPIOZ_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 28),
+ [GPIOEE(GPIOH_0)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 0),
+ [GPIOEE(GPIOH_1)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 4),
+ [GPIOEE(GPIOH_2)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 8),
+ [GPIOEE(GPIOH_3)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 12),
+ [GPIOEE(GPIOH_4)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 16),
+ [GPIOEE(GPIOH_5)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 20),
+ [GPIOEE(GPIOH_6)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 24),
+ [GPIOEE(GPIOH_7)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 28),
+ [GPIOEE(GPIOH_8)] = PIN_MUX(MUX_EE_DOMAIN, 0xc, 0),
+ [GPIOEE(BOOT_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 0),
+ [GPIOEE(BOOT_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 4),
+ [GPIOEE(BOOT_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 8),
+ [GPIOEE(BOOT_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 12),
+ [GPIOEE(BOOT_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 16),
+ [GPIOEE(BOOT_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 20),
+ [GPIOEE(BOOT_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 24),
+ [GPIOEE(BOOT_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 28),
+ [GPIOEE(BOOT_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 0),
+ [GPIOEE(BOOT_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 4),
+ [GPIOEE(BOOT_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 8),
+ [GPIOEE(BOOT_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 12),
+ [GPIOEE(BOOT_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 16),
+ [GPIOEE(BOOT_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 20),
+ [GPIOEE(BOOT_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 24),
+ [GPIOEE(BOOT_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 28),
+ [GPIOEE(GPIOC_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 0),
+ [GPIOEE(GPIOC_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 4),
+ [GPIOEE(GPIOC_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 8),
+ [GPIOEE(GPIOC_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 12),
+ [GPIOEE(GPIOC_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 16),
+ [GPIOEE(GPIOC_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 20),
+ [GPIOEE(GPIOC_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 24),
+ [GPIOEE(GPIOC_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 28),
+ [GPIOEE(GPIOA_0)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 0),
+ [GPIOEE(GPIOA_1)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 4),
+ [GPIOEE(GPIOA_2)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 8),
+ [GPIOEE(GPIOA_3)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 12),
+ [GPIOEE(GPIOA_4)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 16),
+ [GPIOEE(GPIOA_5)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 20),
+ [GPIOEE(GPIOA_6)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 24),
+ [GPIOEE(GPIOA_7)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 28),
+ [GPIOEE(GPIOA_8)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 0),
+ [GPIOEE(GPIOA_9)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 4),
+ [GPIOEE(GPIOA_10)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 8),
+ [GPIOEE(GPIOA_11)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 12),
+ [GPIOEE(GPIOA_12)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 16),
+ [GPIOEE(GPIOA_13)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 20),
+ [GPIOEE(GPIOA_14)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 24),
+ [GPIOEE(GPIOA_15)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 28),
+ [GPIOEE(GPIOX_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 0),
+ [GPIOEE(GPIOX_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 4),
+ [GPIOEE(GPIOX_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 8),
+ [GPIOEE(GPIOX_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 12),
+ [GPIOEE(GPIOX_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 16),
+ [GPIOEE(GPIOX_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 20),
+ [GPIOEE(GPIOX_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 24),
+ [GPIOEE(GPIOX_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 28),
+ [GPIOEE(GPIOX_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 0),
+ [GPIOEE(GPIOX_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 4),
+ [GPIOEE(GPIOX_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 8),
+ [GPIOEE(GPIOX_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 12),
+ [GPIOEE(GPIOX_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 16),
+ [GPIOEE(GPIOX_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 20),
+ [GPIOEE(GPIOX_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 24),
+ [GPIOEE(GPIOX_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 28),
+ [GPIOEE(GPIOX_16)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 0),
+ [GPIOEE(GPIOX_17)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 4),
+ [GPIOEE(GPIOX_18)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 8),
+ [GPIOEE(GPIOX_19)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 12),
+};
+/*sequence of banks keep same as arch-g12a/gpio.h*/
+static struct meson_bank mesontxhd_banks[] = {
+ /*name first last pullen pull dir out in*/
+ AOBANK("GPIOAO_", GPIOAO(GPIOAO_0), GPIOAO(GPIOAO_11),
+ 3, 0, 2, 0, 0, 0, 4, 0, 1, 0),
+ AOBANK("GPIOE_", GPIOAO(GPIOE_0), GPIOAO(GPIOE_2),
+ 3, 16, 2, 16, 0, 16, 4, 16, 1, 16),
+ BANK("GPIOZ_", GPIOEE(GPIOZ_0), GPIOEE(GPIOZ_15),
+ 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
+ BANK("GPIOH_", GPIOEE(GPIOH_0), GPIOEE(GPIOH_8),
+ 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
+ BANK("BOOT_", GPIOEE(BOOT_0), GPIOEE(BOOT_15),
+ 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
+ BANK("GPIOC_", GPIOEE(GPIOC_0), GPIOEE(GPIOC_7),
+ 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
+ BANK("GPIOA_", GPIOEE(GPIOA_0), GPIOEE(GPIOA_15),
+ 5, 0, 5, 0, 16, 0, 17, 0, 18, 0),
+ BANK("GPIOX_", GPIOEE(GPIOX_0), GPIOEE(GPIOX_19),
+ 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
+};
+
+U_BOOT_DEVICES(txhd_gpios) = {
+ { "gpio_aml", &mesontxhd_banks[0] },
+ { "gpio_aml", &mesontxhd_banks[1] },
+ { "gpio_aml", &mesontxhd_banks[2] },
+ { "gpio_aml", &mesontxhd_banks[3] },
+ { "gpio_aml", &mesontxhd_banks[4] },
+ { "gpio_aml", &mesontxhd_banks[5] },
+ { "gpio_aml", &mesontxhd_banks[6] },
+ { "gpio_aml", &mesontxhd_banks[7] },
+};
+
+static unsigned long domain[]={
+ [MUX_AO_DOMAIN] = 0xff800014,
+ [MUX_EE_DOMAIN] = 0xff6346c0,
+};
+
+int clear_pinmux(unsigned int pin)
+{
+ struct pin_mux_desc *pmux_desc = &pin_to_gpio[pin];
+
+ regmap_update_bits(domain[pmux_desc->domain] + (pmux_desc->reg << 2),
+ 0xf << (pmux_desc->bit), 0 << (pmux_desc->bit));
+
+ return 0;
+}
+
+#ifdef CONFIG_AML_SPICC
+#include <asm/arch/secure_apb.h>
+/* generic pins control for spicc1.
+ * if deleted, you have to add it into all g12a board files as necessary.
+ * GPIOH_4: MOSI:regB[19:16]=3
+ * GPIOH_5: MISO:regB[23:20]=3
+ * GPIOH_7: CLK:regB[31:28]=3
+ */
+int spicc1_pinctrl_enable(bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_B);
+ val &= ~(0xf0ff << 16);
+ if (enable)
+ val |= 0x3033 << 16;
+ writel(val, P_PERIPHS_PIN_MUX_B);
+ return 0;
+}
+#endif /* CONFIG_AML_SPICC */
diff --git a/arch/arm/mach-meson/a1/hdmitx.c b/arch/arm/mach-meson/a1/hdmitx.c
new file mode 100644
index 0000000..5292c87
--- /dev/null
+++ b/arch/arm/mach-meson/a1/hdmitx.c
@@ -0,0 +1,594 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/io.h>
+#include <asm/io.h>
+#include <amlogic/media/vout/hdmitx.h>
+#include <asm/arch/regs.h>
+#include <asm/arch/secure_apb.h>
+
+#define HDMITX_DWC_BASE_OFFSET 0xFF600000
+#define HDMITX_TOP_BASE_OFFSET 0xFF608000
+
+static int dbg_en =0;
+
+unsigned long hd_read_reg(volatile unsigned int* addr)
+{
+ unsigned long val = 0;
+
+ val = *addr;
+ if (dbg_en)
+ printk("R: 0x%8p 0x%08lx\n", addr, val);
+ return val;
+}
+
+void hd_write_reg(volatile unsigned int* addr, unsigned long val)
+{
+ *addr = val;
+ if (dbg_en)
+ printk("W: 0x%8p 0x%08lx %s 0x%08lx\n", addr,
+ val, (val == hd_read_reg(addr)) ? "==" : "!=", hd_read_reg(addr));
+}
+
+void hd_set_reg_bits(volatile unsigned int* addr, unsigned long value,
+ unsigned long offset, unsigned long len)
+{
+ unsigned long data = 0;
+
+ data = hd_read_reg(addr);
+ data &= ~(((1L << len) - 1) << offset);
+ data |= (value & ((1L << len) - 1)) << offset;
+ hd_write_reg(addr, data);
+}
+
+#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
+unsigned int hdmitx_rd_reg(unsigned int addr)
+{
+ unsigned int large_offset = addr >> 24;
+ unsigned int small_offset = addr & ((1 << 24) - 1);
+ unsigned int data = 0;
+ register long x0 asm("x0") = 0x82000018;
+ register long x1 asm("x1") = (unsigned long)addr;
+
+ if (large_offset == 0x10) {
+ large_offset = HDMITX_DWC_BASE_OFFSET;
+ data = readb((unsigned long)(large_offset + small_offset));
+ } else if (large_offset == 0x0){
+ large_offset = HDMITX_TOP_BASE_OFFSET;
+ if ((small_offset >= 0x2000) && (small_offset <= 0x365E)) {
+ data = readb((unsigned long)(large_offset + small_offset));
+ } else {
+ small_offset = small_offset << 2;
+ data = readl((unsigned long)(large_offset + small_offset));
+ }
+ } else {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r"(x0) : "r"(x1)
+ );
+ data = (unsigned)(x0&0xffffffff);
+ }
+ if (dbg_en)
+ printk("%s wr[0x%x] 0x%x\n", large_offset ? "DWC" : "TOP",
+ addr, data);
+
+ return data;
+}
+
+void hdmitx_wr_reg(unsigned int addr, unsigned int data)
+{
+ unsigned int large_offset = addr >> 24;
+ unsigned int small_offset = addr & ((1 << 24) - 1);
+ register long x0 asm("x0") = 0x82000019;
+ register long x1 asm("x1") = (unsigned long)addr;
+ register long x2 asm("x2") = data;
+
+ if (large_offset == 0x10) {
+ large_offset = HDMITX_DWC_BASE_OFFSET;
+ writeb(data & 0xff, (unsigned long)(large_offset + small_offset));
+ } else if (large_offset == 0x0){
+ large_offset = HDMITX_TOP_BASE_OFFSET;
+ if ((small_offset >= 0x2000) && (small_offset <= 0x365E)) {
+ writeb(data & 0xff,(unsigned long)(large_offset + small_offset));
+ } else {
+ small_offset = small_offset << 2;
+ writel(data,(unsigned long)(large_offset + small_offset));
+ }
+ } else {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ "smc #0\n"
+ : : "r"(x0), "r"(x1), "r"(x2)
+ );
+ }
+ if (dbg_en)
+ printk("%s wr[0x%x] 0x%x\n", large_offset ? "DWC" : "TOP",
+ addr, data);
+}
+
+void hdmitx_set_reg_bits(unsigned int addr, unsigned int value,
+ unsigned int offset, unsigned int len)
+{
+ unsigned int data32 = 0;
+
+ data32 = hdmitx_rd_reg(addr);
+ data32 &= ~(((1 << len) - 1) << offset);
+ data32 |= (value & ((1 << len) - 1)) << offset;
+ hdmitx_wr_reg(addr, data32);
+}
+
+void hdmitx_poll_reg(unsigned int addr, unsigned int val,
+ unsigned long timeout)
+{
+ udelay(2000);
+ if (!(hdmitx_rd_reg(addr) & val))
+ printk("hdmitx poll:0x%x val:0x%x t=%dms timeout\n",
+ addr, val, 2000);
+}
+
+void hdmitx_rd_check_reg (unsigned long addr,
+ unsigned long exp_data, unsigned long mask)
+{
+ unsigned long rd_data;
+ rd_data = hdmitx_rd_reg(addr);
+ if ((rd_data | mask) != (exp_data | mask)) {
+ printk("HDMITX-DWC addr=0x%04x rd_data=0x%02x\n",
+ (unsigned int)addr, (unsigned int)rd_data);
+ printk("Error: HDMITX-DWC exp_data=0x%02x mask=0x%02x\n",
+ (unsigned int)exp_data, (unsigned int)mask);
+ }
+}
+
+static void set_phy_by_mode(unsigned int mode)
+{
+ switch (mode) {
+ case 1: /* 5.94/4.5/3.7Gbps */
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb5584);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b);
+ break;
+ case 2: /* 2.97Gbps */
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4262);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
+ break;
+ case 3: /* 1.485Gbps, and below */
+ default:
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4242);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
+ break;
+ }
+}
+void hdmitx_set_phy(struct hdmitx_dev *hdev)
+{
+ if (!hdev)
+ return;
+
+ switch (hdev->vic) {
+ case HDMI_3840x2160p50_16x9:
+ case HDMI_3840x2160p60_16x9:
+ case HDMI_4096x2160p50_256x135:
+ case HDMI_4096x2160p60_256x135:
+ if ((hdev->para->cs == HDMI_COLOR_FORMAT_420)
+ && (hdev->para->cd == HDMI_COLOR_DEPTH_24B))
+ set_phy_by_mode(2);
+ else
+ set_phy_by_mode(1);
+ break;
+ case HDMI_3840x2160p50_16x9_Y420:
+ case HDMI_3840x2160p60_16x9_Y420:
+ case HDMI_4096x2160p50_256x135_Y420:
+ case HDMI_4096x2160p60_256x135_Y420:
+ if (hdev->para->cd == HDMI_COLOR_DEPTH_24B)
+ set_phy_by_mode(2);
+ else
+ set_phy_by_mode(1);
+ break;
+ case HDMI_3840x2160p24_16x9:
+ case HDMI_3840x2160p24_64x27:
+ case HDMI_3840x2160p25_16x9:
+ case HDMI_3840x2160p25_64x27:
+ case HDMI_3840x2160p30_16x9:
+ case HDMI_3840x2160p30_64x27:
+ case HDMI_4096x2160p24_256x135:
+ case HDMI_4096x2160p25_256x135:
+ case HDMI_4096x2160p30_256x135:
+ if ((hdev->para->cs == HDMI_COLOR_FORMAT_422)
+ || (hdev->para->cd == HDMI_COLOR_DEPTH_24B))
+ set_phy_by_mode(2);
+ else
+ set_phy_by_mode(1);
+ break;
+ case HDMI_1920x1080p60_16x9:
+ case HDMI_1920x1080p50_16x9:
+ case HDMI_1920x1080i100_16x9:
+ case HDMI_1920x1080i120_16x9:
+ case HDMI_1280x720p100_16x9:
+ case HDMI_1280x720p120_16x9:
+ default:
+ set_phy_by_mode(3);
+ break;
+ }
+/* P_HHI_HDMI_PHY_CNTL1 bit[1]: enable clock bit[0]: soft reset */
+#define RESET_HDMI_PHY() \
+do { \
+ hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0xf, 0, 4); \
+ mdelay(2); \
+ hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0xe, 0, 4); \
+ mdelay(2); \
+} while (0)
+
+ hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0x0390, 16, 16);
+ hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0x0, 0, 4);
+ RESET_HDMI_PHY();
+ RESET_HDMI_PHY();
+ RESET_HDMI_PHY();
+#undef RESET_HDMI_PHY
+
+ printk("hdmitx phy setting done\n");
+}
+
+void hdmitx_turnoff(void)
+{
+ /* Close HDMITX PHY */
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0);
+ /* Disable HPLL */
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0);
+}
+
+#define WAIT_FOR_PLL_LOCKED(reg) \
+ do { \
+ unsigned int st = 0; \
+ int cnt = 10; \
+ while (cnt--) { \
+ udelay(50); \
+ st = (((hd_read_reg(reg) >> 30) & 0x3) == 3); \
+ if (st) \
+ break; \
+ else { \
+ /* reset hpll */ \
+ hd_set_reg_bits(reg, 1, 29, 1); \
+ hd_set_reg_bits(reg, 0, 29, 1); \
+ } \
+ } \
+ if (cnt < 9) \
+ printk("pll[0x%8p] reset %d times\n", reg, 9 - cnt);\
+ } while (0)
+
+static bool set_hpll_hclk_v1(unsigned int m, unsigned int frac_val,
+ struct hdmitx_dev *hdev)
+{
+ int ret = 0;
+
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x0b3a0400 | (m & 0xff));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x3, 28, 2);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, frac_val);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ if (frac_val == 0x8148) {
+ if (((hdev->para->vic == HDMI_3840x2160p50_16x9) ||
+ (hdev->para->vic == HDMI_3840x2160p60_16x9) ||
+ (hdev->para->vic == HDMI_3840x2160p50_64x27) ||
+ (hdev->para->vic == HDMI_3840x2160p60_64x27)) &&
+ (hdev->para->cs != HDMI_COLOR_FORMAT_420)) {
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x11551293);
+ } else {
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x44331290);
+ }
+ } else {
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a68dc00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290);
+ }
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39272000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540000);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLLv1: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+
+ ret = (((hd_read_reg(P_HHI_HDMI_PLL_CNTL0) >> 30) & 0x3) == 0x3);
+ return ret;
+}
+
+static bool set_hpll_hclk_v2(unsigned int m, unsigned int frac_val)
+{
+ int ret = 0;
+
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x0b3a0400 | (m & 0xff));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x3, 28, 2);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, frac_val);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0xea68dc00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39272000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540000);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLLv2: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+
+ ret = (((hd_read_reg(P_HHI_HDMI_PLL_CNTL0) >> 30) & 0x3) == 0x3);
+ return ret;
+}
+
+static bool set_hpll_hclk_v3(unsigned int m, unsigned int frac_val)
+{
+ int ret = 0;
+
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x0b3a0400 | (m & 0xff));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x3, 28, 2);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, frac_val);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0xea68dc00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39272000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x55540000);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLLv3: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+
+ ret = (((hd_read_reg(P_HHI_HDMI_PLL_CNTL0) >> 30) & 0x3) == 0x3);
+ return ret;
+}
+
+void set_hpll_clk_out(unsigned clk, struct hdmitx_dev *hdev)
+{
+ unsigned int frac_rate ;
+
+ frac_rate = hdev->frac_rate_policy;
+ if (clk == -1)
+ return;
+ printk("config HPLL = %d frac_rate = %d\n", clk, frac_rate);
+
+ switch (clk) {
+ case 5940000:
+ if (set_hpll_hclk_v1(0xf7, frac_rate ? 0x8148 : 0x10000, hdev))
+ break;
+ else if (set_hpll_hclk_v2(0x7b,0x18000))
+ break;
+ else if (set_hpll_hclk_v3(0xf7,0x10000))
+ break;
+ else
+ break;
+ break;
+ case 5405400:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004e1);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00007333);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 4455000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b9);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00014000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 3712500:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00049a);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00016000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 3450000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00048f);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 3243240:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000487);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0000451f);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 2970000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00047b);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 4324320:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b4);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ default:
+ printk("error hpll clk: %d\n", clk);
+ break;
+ }
+ printk("config HPLL done\n");
+}
+
+void set_hpll_od1(unsigned div)
+{
+ switch (div) {
+ case 1:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0, 16, 2);
+ break;
+ case 2:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 1, 16, 2);
+ break;
+ case 4:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 2, 16, 2);
+ break;
+ default:
+ printk("Err %s[%d]\n", __func__, __LINE__);
+ break;
+ }
+}
+
+void set_hpll_od2(unsigned div)
+{
+ switch (div) {
+ case 1:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0, 18, 2);
+ break;
+ case 2:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 1, 18, 2);
+ break;
+ case 4:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 2, 18, 2);
+ break;
+ default:
+ printk("Err %s[%d]\n", __func__, __LINE__);
+ break;
+ }
+}
+
+void set_hpll_od3(unsigned div)
+{
+ switch (div) {
+ case 1:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0, 20, 2);
+ break;
+ case 2:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 1, 20, 2);
+ break;
+ case 4:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 2, 20, 2);
+ break;
+ default:
+ printk("Err %s[%d]\n", __func__, __LINE__);
+ break;
+ }
+}
+
+/* HERE MUST BE BIT OPERATION!!! */
+void set_hpll_sspll(struct hdmitx_dev *hdev)
+{
+ enum hdmi_vic vic = hdev->vic;
+
+ switch (vic) {
+ case HDMI_1920x1080p60_16x9:
+ case HDMI_1920x1080p50_16x9:
+ case HDMI_1280x720p60_16x9:
+ case HDMI_1280x720p50_16x9:
+ case HDMI_1920x1080i60_16x9:
+ case HDMI_1920x1080i50_16x9:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 1, 29, 1);
+ /* bit[22:20] hdmi_dpll_fref_sel
+ * bit[8] hdmi_dpll_ssc_en
+ * bit[7:4] hdmi_dpll_ssc_dep_sel
+ */
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 1, 20, 3);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 1, 8, 1);
+ /* 2: 1000ppm 1: 500ppm */
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 2, 4, 4);
+ /* bit[15] hdmi_dpll_sdmnc_en */
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL3, 0, 15, 1);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0, 29, 1);
+ break;
+ default:
+ break;
+ }
+}
+
+void ddc_pinmux_init(void)
+{
+ hd_set_reg_bits(P_PAD_PULL_UP_EN_REG3, 0, 0, 2); /*Disable GPIOH_1/2 pull-up/down*/
+ hd_set_reg_bits(P_PAD_PULL_UP_REG3, 0, 0, 2);
+ hd_set_reg_bits(P_PREG_PAD_GPIO3_EN_N, 3, 0, 2); /*GPIOH_1/2 input*/
+ hd_set_reg_bits(P_PERIPHS_PIN_MUX_B, 0x11, 0, 8); /*Mux DDC SDA/SCL*/
+}
+
+int hdmitx_get_hpd_state(void)
+{
+ int st = 0;
+
+ st = !!(hd_read_reg(P_PREG_PAD_GPIO3_I) & (1 << 2));
+ return st;
+}
+
+void hdmitx_prbs(void)
+{
+ unsigned int i;
+
+ for (i = 0; i < 4; i ++) {
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0x0390000f);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0x0390000e);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0x03904002);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL4, 0x0001efff | (i << 20));
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0xef904002);
+ mdelay(10);
+ if (i > 0)
+ pr_info("prbs D[%d]:%lx\n", i -1, hd_read_reg(P_HHI_HDMI_PHY_STATUS));
+ else
+ pr_info("prbs clk :%lx\n",hd_read_reg(P_HHI_HDMI_PHY_STATUS));
+ }
+}
+
+void hdmitx_enable_apb3(void)
+{
+ /*g12a doesn't need enable apb3*/
+ return;
+ /*hd_set_reg_bits(P_HDMITX_CTRL_PORT, 1, 15, 1);*/
+ /*hd_set_reg_bits((P_HDMITX_CTRL_PORT + 0x10), 1, 15, 1);*/
+}
diff --git a/arch/arm/mach-meson/a1/mailbox.c b/arch/arm/mach-meson/a1/mailbox.c
new file mode 100644
index 0000000..7105170
--- /dev/null
+++ b/arch/arm/mach-meson/a1/mailbox.c
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/arch/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/arch/mailbox.h>
+#include <asm/arch/secure_apb.h>
+
+/* Bit position for size value in MHU header */
+#define SIZE_SHIFT 20
+/* Mask to extract size value in MHU header*/
+#define SIZE_MASK 0x1ff
+
+static unsigned int *ap_mb_stat[] = {
+ (unsigned int *)HIU_MAILBOX_STAT_4,
+ (unsigned int *)HIU_MAILBOX_STAT_5,
+};
+static unsigned int *ap_mb_set[] = {
+ (unsigned int *)HIU_MAILBOX_SET_4,
+ (unsigned int *)HIU_MAILBOX_SET_5,
+};
+static unsigned int *ap_mb_clear[] = {
+ (unsigned int *)HIU_MAILBOX_CLR_4,
+ (unsigned int *)HIU_MAILBOX_CLR_5,
+};
+static unsigned int *ap_mb_payload[] = {
+ (unsigned int *)(P_SHARE_SRAM_BASE + MHU_LOW_AP_TO_SCP_PAYLOAD),
+ (unsigned int *)(P_SHARE_SRAM_BASE + MHU_HIGH_AP_TO_SCP_PAYLOAD),
+};
+static unsigned int *scp_mb_stat[] = {
+ (unsigned int *)HIU_MAILBOX_STAT_1,
+ (unsigned int *)HIU_MAILBOX_STAT_2,
+};
+/*
+static unsigned int *scp_mb_set[] = {
+ (unsigned int *)HIU_MAILBOX_SET_1,
+ (unsigned int *)HIU_MAILBOX_SET_2,
+};
+*/
+static unsigned int *scp_mb_clear[] = {
+ (unsigned int *)HIU_MAILBOX_CLR_1,
+ (unsigned int *)HIU_MAILBOX_CLR_2,
+};
+static unsigned int *scp_mb_payload[] = {
+ (unsigned int *)(P_SHARE_SRAM_BASE + MHU_LOW_SCP_TO_AP_PAYLOAD),
+ (unsigned int *)(P_SHARE_SRAM_BASE + MHU_HIGH_SCP_TO_AP_PAYLOAD),
+};
+
+static void mb_message_start(unsigned int priority)
+{
+ while (readl(ap_mb_stat[priority]) != 0)
+ ;
+}
+static void mb_message_send(unsigned int command, unsigned int priority)
+{
+ writel(command, ap_mb_set[priority]);
+ while (readl(ap_mb_stat[priority]) != 0)
+ ;
+}
+static unsigned int mb_message_wait(unsigned int priority)
+{
+ unsigned int response;
+ while (!(response = readl(scp_mb_stat[priority])))
+ ;
+ return response;
+}
+static void mb_message_end(unsigned int priority)
+{
+ writel(0xffffffff, scp_mb_clear[priority]);
+}
+static unsigned int mb_message_receive(
+ void **message_out,
+ unsigned int *size_out,
+ unsigned int priority)
+{
+ unsigned int response = mb_message_wait(priority);
+ unsigned int size = (response >> SIZE_SHIFT) & SIZE_MASK;
+
+ response &= ~(SIZE_MASK << SIZE_SHIFT);
+
+ if (size_out)
+ *size_out = size;
+ if (message_out)
+ *message_out = (void *)(scp_mb_payload[priority]);
+
+ return response;
+}
+static void mb_init(unsigned int priority)
+{
+ writel(0xffffffff, ap_mb_clear[priority]);
+}
+
+static void scpi_send32(unsigned int command,
+ unsigned int message, unsigned int priority)
+{
+ mb_init(priority);
+ mb_message_start(priority);
+ writel(message, ap_mb_payload[priority]);
+ mb_message_send(command, priority);
+ mb_message_wait(priority);
+ mb_message_end(priority);
+}
+
+static void scpi_send_block(unsigned int command,
+ unsigned int *message, unsigned int message_size, unsigned int priority)
+{
+ mb_init(priority);
+ mb_message_start(priority);
+ memcpy(ap_mb_payload[priority], message, message_size);
+ mb_message_send(command, priority);
+ mb_message_wait(priority);
+ mb_message_end(priority);
+}
+
+void open_scp_log(unsigned int channel)
+{
+ scpi_send32(SCPI_CMD_OPEN_SCP_LOG, channel, LOW_PRIORITY);
+}
+
+int send_usr_data(unsigned int clinet_id, unsigned int *val, unsigned int size)
+{
+ unsigned long command;
+
+ if (size > 0x1fd)
+ return -1;
+
+ command = ((unsigned int)SCPI_CMD_SET_USR_DATA & 0xff) | ((clinet_id & 0xff) << 8) | ((size & 0x1ff) << 20);
+ scpi_send_block(command,val,size,0);
+
+ return 0;
+}
+
+/*
+* type:
+* 0: data; 1: version
+*/
+int thermal_calibration(unsigned int type, unsigned int data)
+{
+ unsigned int *appayload = ap_mb_payload[LOW_PRIORITY];
+ unsigned int *response;
+ unsigned int size;
+
+ mb_message_start(LOW_PRIORITY);
+ writel(type, appayload);
+ writel(data, appayload+1);
+ mb_message_send(
+ ((0x8 << SIZE_SHIFT) | SCPI_CMD_THERMAL_CALIB),
+ LOW_PRIORITY);
+ mb_message_receive((void *)&response, &size, LOW_PRIORITY);
+ mb_message_end(LOW_PRIORITY);
+
+ if (*response != SCPI_SUCCESS)
+ return -1;
+ else
+ return 0;
+}
+
+int thermal_get_value(unsigned int sensor_id, unsigned int *value)
+{
+ unsigned int *response;
+ unsigned int size;
+
+ mb_message_start(LOW_PRIORITY);
+ writel(sensor_id, ap_mb_payload[LOW_PRIORITY]);
+ mb_message_send(
+ ((0x4 << SIZE_SHIFT) | SCPI_CMD_SENSOR_VALUE),
+ LOW_PRIORITY);
+ mb_message_receive((void *)&response, &size, LOW_PRIORITY);
+ mb_message_end(LOW_PRIORITY);
+
+ *value = *(response+1);
+ if (*response != SCPI_SUCCESS)
+ return -1;
+ else
+ return 0;
+}
+
+
+void send_pwm_delt(int32_t vcck_delt, int32_t ee_delt)
+{
+ unsigned int *appayload = ap_mb_payload[LOW_PRIORITY];
+ mb_message_start(LOW_PRIORITY);
+ writel(vcck_delt, appayload);
+ writel(ee_delt, appayload+1);
+ mb_message_send(SCPI_CMD_REV_PWM_DELT, LOW_PRIORITY);
+ mb_message_wait(LOW_PRIORITY);
+ mb_message_end(LOW_PRIORITY);
+}
+
diff --git a/arch/arm/mach-meson/a1/oscring.c b/arch/arm/mach-meson/a1/oscring.c
new file mode 100644
index 0000000..837394d
--- /dev/null
+++ b/arch/arm/mach-meson/a1/oscring.c
@@ -0,0 +1,99 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/arch/io.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/oscring.h>
+
+void ring_powerinit(void)
+{
+ writel(0x0017000b, RING_PWM_VCCK);/*set vcck 0.8v*/
+ //writel(0x10000c, RING_PWM_EE);/*set ee 0.8v*/
+}
+
+unsigned long clk_util_ring_msr(unsigned long clk_mux)
+{
+ unsigned int regval = 0;
+
+ writel(0, MSR_CLK_REG0);
+ /* Set the measurement gate to 64uS */
+ /* 64uS is enough for measure the frequence? */
+ setbits_le32(MSR_CLK_REG0, (10000 - 1));
+ /* Disable continuous measurement */
+ /* Disable interrupts */
+ clrbits_le32(MSR_CLK_REG0, (1 << 17) | (1 << 18));
+ clrbits_le32(MSR_CLK_REG0, 0x7f << 20);
+ setbits_le32(MSR_CLK_REG0, (clk_mux) << 20 | (1 << 19) | (1 << 16));
+ /* Wait for the measurement to be done */
+ regval = readl(MSR_CLK_REG0);
+ do {
+ regval = readl(MSR_CLK_REG0);
+ } while (regval & (1 << 31));
+
+ /* Disable measuring */
+ clrbits_le32(MSR_CLK_REG0, 1 << 16);
+ regval = (readl(MSR_CLK_REG2) + 31) & 0x000fffff;
+
+ return (regval / 10);
+}
+
+int ring_msr(int index)
+{
+ const char* clk_table[] = {
+ [9] = "osc_ring_ramb(16svt) " ,
+ [8] = "osc_ring_rama(16svt) " ,
+ [7] = "osc_ring_dspb(16svt) " ,
+ [6] = "osc_ring_dspa(16svt) " ,
+ [5] = "osc_ring_dmc(16svt) " ,
+ [4] = "osc_ring_ddr(24svt) " ,
+ [3] = "osc_ring_top1(16svt) " ,
+ [2] = "osc_ring_top0(20lvt) " ,
+ [1] = "osc_ring_cpu1(20lvt) " ,
+ [0] = "osc_ring_cpu0(20lvt) " ,
+ };
+ const int tb[] = {50, 51, 54, 55, 56, 57, 58, 59, 60, 61};
+ unsigned long i;
+ uint8_t efuseinfo[4] = {0, 0, 0, 0};
+
+ if ((index != 0xff) && (index != 0)) {
+ if (bl31_get_cornerinfo(efuseinfo, sizeof(efuseinfo) / sizeof(uint8_t)) != 0) {
+ printf("fail get efuse info\n");
+ return 0;
+ }
+ if ((index >= 1) && (index <= 3))
+ printf("%d\n", efuseinfo[index]);
+ else
+ printf("input data not support!\n");
+
+ return 0;
+ }
+ if (0xff != index) {
+ ring_powerinit();
+ printf("set vcck vddee to 800mv\n");
+ }
+ /*RING_OSCILLATOR 0x7f: set slow ring*/
+ writel(OSCRING_CTL_DATA, OSCRING_CTL_REG);
+
+ for (i = 0; i < 10; i++) {
+ printf("%s :",clk_table[i]);
+ printf("%ld KHz",clk_util_ring_msr(tb[i]));
+ printf("\n");
+ }
+
+ if (bl31_get_cornerinfo(efuseinfo, sizeof(efuseinfo) / sizeof(uint8_t)) != 0) {
+ printf("fail get efuse info\n");
+ return 0;
+ }
+
+ printf("osc efuse info:\n");
+ for (i = 0; i < sizeof(efuseinfo) / sizeof(uint8_t); i++)
+ printf("0x%x, ", efuseinfo[i]);
+ printf("\n");
+
+ return 0;
+}
diff --git a/arch/arm/mach-meson/a1/pinctrl_init.c b/arch/arm/mach-meson/a1/pinctrl_init.c
new file mode 100644
index 0000000..829ce28
--- /dev/null
+++ b/arch/arm/mach-meson/a1/pinctrl_init.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm/uclass.h>
+#include <linux/err.h>
+#include <asm/arch/pinctrl_init.h>
+
+int pinctrl_devices_active(int pinctrl_num)
+{
+ int ret;
+ int idx;
+ struct udevice *pinctrl;
+
+ for (idx = 0; idx < pinctrl_num; idx++) {
+ ret = uclass_get_device(UCLASS_PINCTRL, idx, &pinctrl);
+ if (ret) {
+ debug("%s: failed to active pinctrl device [%d]",
+ __func__, idx);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-meson/a1/pll.c b/arch/arm/mach-meson/a1/pll.c
new file mode 100644
index 0000000..501a6ea
--- /dev/null
+++ b/arch/arm/mach-meson/a1/pll.c
@@ -0,0 +1,1047 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <amlogic/cpu_id.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/pll.h>
+
+#define STR_PLL_TEST_ALL "all"
+#define STR_PLL_TEST_SYS "sys"
+#define STR_PLL_TEST_FIX "fix"
+#define STR_PLL_TEST_DDR "ddr"
+#define STR_PLL_TEST_HIFI "hifi"
+#define STR_PLL_TEST_USBPHY "usbphy"
+
+#define PLL_LOCK_CHECK_MAX 20
+
+#define RET_PLL_LOCK_FAIL 0x1000
+#define RET_CLK_NOT_MATCH 0x1
+#define SYS_PLL_DIV16_CNTL (1<<24)
+#define SYS_CLK_DIV16_CNTL (1)
+#define SYS_PLL_TEST_DIV 4 /* div16 */
+#define HDMI_PLL_DIV_CNTL (1<<18)
+#define HDMI_PLL_DIV_GATE (1<<19)
+
+#define PLL_DIV16_OFFSET 4 /* div2/2/4 */
+#define GP0_PLL_TEST_DIV 0 /* div1 */
+#define PLL_DIV8_OFFSET 3
+
+#define Wr(addr, data) writel(data, addr)
+#define Rd(addr) readl(addr)
+
+static int sys_pll_init(sys_pll_set_t * sys_pll_set);
+static int sys_pll_test(sys_pll_set_t * sys_pll_set);
+static int sys_pll_test_all(sys_pll_cfg_t * sys_pll_cfg);
+static int fix_pll_test(void);
+static int ddr_pll_test(void);
+extern unsigned long clk_util_clk_msr(unsigned long clk_mux);
+
+#if 0
+static int hdmi_pll_init(hdmi_pll_set_t * hdmi_pll_set);
+static int hdmi_pll_test(hdmi_pll_set_t * hdmi_pll_set);
+static int hdmi_pll_test_all(hdmi_pll_cfg_t * hdmi_pll_cfg);
+static int gp0_pll_test(gp0_pll_set_t * gp0_pll);
+static int gp0_pll_test_all(void);
+#endif
+
+#if 0
+static unsigned int pll_range[PLL_ENUM][2] = {
+ {101, 202}, //sys pll range
+ {303, 404}, //fix pll range
+ {505, 606}, //ddr pll range
+ {707, 808}, //hdmi pll range
+ {909, 999}, // pll range
+};
+
+static char pll_range_ind[PLL_ENUM][10] = {
+ "sys",
+ "fix",
+ "ddr",
+ "hdmi",
+ "gp0",
+};
+#endif
+
+static void update_bits(size_t reg, size_t mask, unsigned int val)
+{
+ unsigned int tmp, orig;
+ orig = readl(reg);
+ tmp = orig & ~mask;
+ tmp |= val & mask;
+ writel(tmp, reg);
+}
+
+uint32_t sys_pll_clk[PLL_TEST_SYS_TOTAL] = {768, 888, 960, 1008, 1152, 1248, 1392, 1536};
+sys_pll_cfg_t sys_pll_cfg = {
+ .sys_pll[0] = {
+ .cpu_clk = 768,
+ .pll_cntl0 = 0x01f18420,
+ .pll_cntl1 = 0x01800000,
+ .pll_cntl2 = 0x00001100,
+ .pll_cntl3 = 0x10022300,
+ .pll_cntl4 = 0x00300000
+ },
+ .sys_pll[1] = {
+ .cpu_clk = 888,
+ .pll_cntl0 = 0x01f18425,
+ .pll_cntl1 = 0x01800000,
+ .pll_cntl2 = 0x00001100,
+ .pll_cntl3 = 0x10022300,
+ .pll_cntl4 = 0x00300000
+ },
+ .sys_pll[2] = {
+ .cpu_clk = 960,
+ .pll_cntl0 = 0x01f18428,
+ .pll_cntl1 = 0x01800000,
+ .pll_cntl2 = 0x00001100,
+ .pll_cntl3 = 0x10022300,
+ .pll_cntl4 = 0x00300000
+ },
+ .sys_pll[3] = {
+ .cpu_clk = 1008,
+ .pll_cntl0 = 0x01f1842A,
+ .pll_cntl1 = 0x01800000,
+ .pll_cntl2 = 0x00001100,
+ .pll_cntl3 = 0x10022300,
+ .pll_cntl4 = 0x00300000
+ },
+ .sys_pll[4] = {
+ .cpu_clk = 1152,
+ .pll_cntl0 = 0x01f18430,
+ .pll_cntl1 = 0x01800000,
+ .pll_cntl2 = 0x00001100,
+ .pll_cntl3 = 0x10022300,
+ .pll_cntl4 = 0x00300000
+ },
+ .sys_pll[5] = {
+ .cpu_clk = 1248,
+ .pll_cntl0 = 0x01f18434,
+ .pll_cntl1 = 0x01800000,
+ .pll_cntl2 = 0x00001100,
+ .pll_cntl3 = 0x10022300,
+ .pll_cntl4 = 0x00300000
+ },
+ .sys_pll[6] = {
+ .cpu_clk = 1392,
+ .pll_cntl0 = 0x01f1843A,
+ .pll_cntl1 = 0x01800000,
+ .pll_cntl2 = 0x00001100,
+ .pll_cntl3 = 0x10022300,
+ .pll_cntl4 = 0x00300000
+ },
+ .sys_pll[7] = {
+ .cpu_clk = 1536,
+ .pll_cntl0 = 0x01f18440,
+ .pll_cntl1 = 0x01800000,
+ .pll_cntl2 = 0x00001100,
+ .pll_cntl3 = 0x10022300,
+ .pll_cntl4 = 0x00300000
+ },
+};
+
+#define GPLL0_RATE(_rate, _m, _n, _od) \
+{ \
+ .rate = (_rate), \
+ .m = (_m), \
+ .n = (_n), \
+ .od = (_od), \
+}
+
+#if 0
+static gpll_rate_table_t gpll0_tbl[] = {
+ GPLL0_RATE(408, 136, 1, 3), /*DCO=3264M*/
+ GPLL0_RATE(600, 200, 1, 3), /*DCO=4800M*/
+ GPLL0_RATE(696, 232, 1, 3), /*DCO=5568M*/
+ GPLL0_RATE(792, 132, 1, 2), /*DCO=3168M*/
+ GPLL0_RATE(846, 141, 1, 2), /*DCO=3384M*/
+ GPLL0_RATE(912, 152, 1, 2), /*DCO=3648M*/
+};
+#endif
+
+static hifipll_rate_table_t hifipll_tbl[] = {
+ GPLL0_RATE(864, 36, 1, 0), /*DCO=864M*/
+ GPLL0_RATE(960, 40, 1, 0), /*DCO=960M*/
+ GPLL0_RATE(1056, 44, 1, 0), /*DCO=1056M*/
+ GPLL0_RATE(1200, 50, 1, 0), /*DCO=1200M*/
+ GPLL0_RATE(1320, 55, 1, 0), /*DCO=1320M*/
+ GPLL0_RATE(1536, 64, 1, 0), /*DCO=1536M*/
+};
+
+static void pll_report(unsigned int flag, char * name) {
+ if (flag)
+ printf("%s pll test failed!\n", name);
+ else
+ printf("%s pll test pass!\n", name);
+ return;
+}
+
+static int clk_around(unsigned int clk, unsigned int cmp) {
+ if (((cmp-2) <= clk) && (clk <= (cmp+2)))
+ return 1;
+ else
+ return 0;
+}
+
+#if 0
+static void clocks_set_sys_cpu_clk(uint32_t freq, uint32_t pclk_ratio, uint32_t aclkm_ratio, uint32_t atclk_ratio )
+{
+ uint32_t control;
+ uint32_t dyn_pre_mux;
+ uint32_t dyn_post_mux;
+ uint32_t dyn_div;
+
+ // Make sure not busy from last setting and we currently match the last setting
+ do {
+ control = Rd(CPUCTRL_CLK_CTRL0);
+ } while( (control & (1 << 28)) );
+
+ control = control | (1 << 26); // Enable
+
+ // Switching to System PLL...just change the final mux
+ if ( freq == 1 ) {
+ // wire cntl_final_mux_sel = control[11];
+ control = control | (1 << 11);
+ } else {
+ switch ( freq ) {
+ case 0: // If Crystal
+ dyn_pre_mux = 0;
+ dyn_post_mux = 0;
+ dyn_div = 0; // divide by 1
+ break;
+ case 1000: // fclk_div2
+ dyn_pre_mux = 1;
+ dyn_post_mux = 0;
+ dyn_div = 0; // divide by 1
+ break;
+ case 667: // fclk_div3
+ dyn_pre_mux = 2;
+ dyn_post_mux = 0;
+ dyn_div = 0; // divide by 1
+ break;
+ case 500: // fclk_div2/2
+ dyn_pre_mux = 1;
+ dyn_post_mux = 1;
+ dyn_div = 1; // Divide by 2
+ break;
+ case 333: // fclk_div3/2
+ dyn_pre_mux = 2;
+ dyn_post_mux = 1;
+ dyn_div = 1; // divide by 2
+ break;
+ case 250: // fclk_div2/4
+ dyn_pre_mux = 1;
+ dyn_post_mux = 1;
+ dyn_div = 3; // divide by 4
+ break;
+ default:
+ dyn_pre_mux = 0;
+ dyn_post_mux = 0;
+ dyn_div = 0; // divide by 1
+ break;
+ }
+ if ( control & (1 << 10) ) { // if using Dyn mux1, set dyn mux 0
+ // Toggle bit[10] indicating a dynamic mux change
+ control = (control & ~((1 << 10) | (0x3f << 4) | (1 << 2) | (0x3 << 0)))
+ | ((0 << 10)
+ | (dyn_div << 4)
+ | (dyn_post_mux << 2)
+ | (dyn_pre_mux << 0));
+ } else {
+ // Toggle bit[10] indicating a dynamic mux change
+ control = (control & ~((1 << 10) | (0x3f << 20) | (1 << 18) | (0x3 << 16)))
+ | ((1 << 10)
+ | (dyn_div << 20)
+ | (dyn_post_mux << 18)
+ | (dyn_pre_mux << 16));
+ }
+ // Select Dynamic mux
+ control = control & ~(1 << 11);
+ }
+ Wr(HHI_SYS_CPU_CLK_CNTL,control);
+ //
+ // Now set the divided clocks related to the System CPU
+ //
+ // This function changes the clock ratios for the
+ // PCLK, ACLKM (AXI) and ATCLK
+ // .clk_clken0_i ( {clk_div2_en,clk_div2} ),
+ // .clk_clken1_i ( {clk_div3_en,clk_div3} ),
+ // .clk_clken2_i ( {clk_div4_en,clk_div4} ),
+ // .clk_clken3_i ( {clk_div5_en,clk_div5} ),
+ // .clk_clken4_i ( {clk_div6_en,clk_div6} ),
+ // .clk_clken5_i ( {clk_div7_en,clk_div7} ),
+ // .clk_clken6_i ( {clk_div8_en,clk_div8} ),
+
+ uint32_t control1 = Rd(HHI_SYS_CPU_CLK_CNTL1);
+
+ // .cntl_PCLK_mux ( hi_sys_cpu_clk_cntl1[5:3] ),
+ if ( (pclk_ratio >= 2) && (pclk_ratio <= 8) ) {
+ control1 = (control1 & ~(0x7 << 3)) | ((pclk_ratio-2) << 3);
+ }
+ // .cntl_ACLKM_clk_mux ( hi_sys_cpu_clk_cntl1[11:9] ), // AXI matrix
+ if ( (aclkm_ratio >= 2) && (aclkm_ratio <= 8) ) {
+ control1 = (control1 & ~(0x7 << 9)) | ((aclkm_ratio-2) << 9);
+ }
+ // .cntl_ATCLK_clk_mux ( hi_sys_cpu_clk_cntl1[8:6] ),
+ if ( (atclk_ratio >= 2) && (atclk_ratio <= 8) ) {
+ control1 = (control1 & ~(0x7 << 6)) | ((atclk_ratio-2) << 6);
+ }
+ Wr( HHI_SYS_CPU_CLK_CNTL1, control1 );
+}
+#endif
+
+void clocks_set_sys_cpu_clk(uint32_t src) {
+ /*
+ * src
+ * 0: use 24M, 1: use SYS PLL
+ */
+ uint32_t control;
+ uint32_t dyn_pre_mux;
+ uint32_t dyn_post_mux;
+ uint32_t dyn_div;
+ //runtime_info_t info;
+
+ // Make sure not busy from last setting and we currently match the last setting
+ do {
+ control = readl(CPUCTRL_CLK_CTRL0);
+ } while( (control & (1 << 28)) );
+
+ control = control | (1 << 26);// Enable
+
+ dyn_pre_mux = 0; //use oscin
+ dyn_post_mux = 0;
+ dyn_div = 0;/* divide by 1 */
+
+ // Select Dynamic mux
+ if (src == 1) {
+ control = control | (1 << 11);
+ }
+ else {
+ control = control & ~(1 << 11);
+ if (control & (1 << 10)) {// if using Dyn mux1, set dyn mux 0
+ // Toggle bit[10] indicating a dynamic mux change
+ control = (control & ~((1 << 10) | (0x3f << 4) | (1 << 2) | (0x3 << 0)))
+ | ((0 << 10)
+ | (dyn_div << 4)
+ | (dyn_post_mux << 2)
+ | (dyn_pre_mux << 0));
+ } else {
+ // Toggle bit[10] indicating a dynamic mux change
+ control = (control & ~((1 << 10) | (0x3f << 20) | (1 << 18) | (0x3 << 16)))
+ | ((1 << 10)
+ | (dyn_div << 20)
+ | (dyn_post_mux << 18)
+ | (dyn_pre_mux << 16));
+ }
+ }
+
+ writel(control, CPUCTRL_CLK_CTRL0);
+
+ return;
+}
+
+static int sys_pll_init(sys_pll_set_t * sys_pll_set) {
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ do {
+ writel(sys_pll_set->pll_cntl1, ANACTRL_SYSPLL_CTRL1);
+ writel(sys_pll_set->pll_cntl2, ANACTRL_SYSPLL_CTRL2);
+ writel(sys_pll_set->pll_cntl3, ANACTRL_SYSPLL_CTRL3);
+ writel(sys_pll_set->pll_cntl4, ANACTRL_SYSPLL_CTRL4);
+ writel(sys_pll_set->pll_cntl0, ANACTRL_SYSPLL_CTRL0);
+ writel(sys_pll_set->pll_cntl0 | (1<<28) , ANACTRL_SYSPLL_CTRL0);
+ _udelay(10);
+ writel(sys_pll_set->pll_cntl0 | (1<<28) | (1<<26), ANACTRL_SYSPLL_CTRL0);
+ _udelay(40);
+ writel(sys_pll_set->pll_cntl2 | (1<<6), ANACTRL_SYSPLL_CTRL2);
+ writel(sys_pll_set->pll_cntl2, ANACTRL_SYSPLL_CTRL2);
+ _udelay(20);
+ } while((0 == ((Rd(ANACTRL_SYSPLL_STS) >> 31) & 0x1)) && (--lock_check));
+ if (lock_check != 0)
+ return 0;
+ else
+ return RET_PLL_LOCK_FAIL;
+}
+
+static int sys_pll_test_all(sys_pll_cfg_t * sys_pll_cfg) {
+ unsigned int i=0;
+ int ret=0;
+/*
+ for (i=0; i<(sizeof(sys_pll_cfg_t)/sizeof(sys_pll_set_t)); i++) {
+ ret += sys_pll_test(&(sys_pll_cfg->sys_pll[i]));
+ }
+*/
+
+ for (i=0; i<(sizeof(sys_pll_clk)/sizeof(uint32_t)); i++) {
+ sys_pll_cfg->sys_pll[0].cpu_clk = sys_pll_clk[i];
+ ret += sys_pll_test(&(sys_pll_cfg->sys_pll[i]));
+ }
+ return ret;
+}
+
+static int sys_pll_test(sys_pll_set_t * sys_pll_set) {
+ //unsigned int clk_msr_reg = 0;
+ unsigned int clk_msr_val = 0;
+ unsigned int sys_clk = 0;
+ //unsigned int sys_pll_cntl = 0;
+ int ret=0;
+
+ /* switch sys clk to oscillator */
+ clocks_set_sys_cpu_clk(0);
+
+ /* store current sys pll cntl */
+ sys_pll_set_t sys_pll;
+ sys_pll.pll_cntl0 = readl(ANACTRL_SYSPLL_CTRL0);
+ sys_pll.pll_cntl1 = readl(ANACTRL_SYSPLL_CTRL1);
+ sys_pll.pll_cntl2 = readl(ANACTRL_SYSPLL_CTRL2);
+ sys_pll.pll_cntl3 = readl(ANACTRL_SYSPLL_CTRL3);
+ sys_pll.pll_cntl4 = readl(ANACTRL_SYSPLL_CTRL4);
+
+ if (sys_pll_set->cpu_clk == 0) {
+ sys_clk = (24 * (sys_pll_set->pll_cntl0&0xFF)) / ((sys_pll_set->pll_cntl0>>10)&0x1F);
+ }
+
+ /* store CPU clk msr reg, restore it when test done */
+ //clk_msr_reg = readl(HHI_SYS_CPU_CLK_CNTL1);
+
+ /* enable CPU clk msr cntl bit */
+ //writel(clk_msr_reg | SYS_PLL_DIV16_CNTL | SYS_CLK_DIV16_CNTL, HHI_SYS_CPU_CLK_CNTL1);
+
+ //printf("HHI_SYS_CPU_CLK_CNTL: 0x%x\n", readl(HHI_SYS_CPU_CLK_CNTL));
+ //printf("HHI_SYS_CPU_CLK_CNTL1: 0x%x\n", readl(HHI_SYS_CPU_CLK_CNTL1));
+
+ if (0 == sys_pll_set->pll_cntl0) {
+ printf("sys pll cntl equal NULL, skip\n");
+ return -1;
+ }
+
+ /* test sys pll */
+ if (sys_pll_set->cpu_clk)
+ sys_clk = sys_pll_set->cpu_clk;
+
+ ret = sys_pll_init(sys_pll_set);
+ if (ret) {
+ printf("SYS pll lock Failed! - %4d MHz\n", sys_clk);
+ }
+ else {
+ printf("SYS pll lock OK! - %4d MHz. Div16 - %4d MHz. ", sys_clk, sys_clk>>PLL_DIV16_OFFSET);
+ clocks_set_sys_cpu_clk(1);
+ //open div16
+ writel(0x005012A2, CPUCTRL_CLK_CTRL1);
+ clk_msr_val = clk_util_clk_msr(45);
+ printf("CLKMSR(45) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, sys_clk>>SYS_PLL_TEST_DIV)) {
+ /* sys clk/pll div16 */
+ printf(": Match\n");
+ }
+ else {
+ ret = RET_CLK_NOT_MATCH;
+ printf(": MisMatch\n");
+ }
+ }
+
+ /* restore sys pll */
+ sys_pll_init(&sys_pll);
+ //clocks_set_sys_cpu_clk( 1, 0, 0, 0);
+ clocks_set_sys_cpu_clk(1);
+
+ /* restore clk msr reg */
+ //writel(clk_msr_reg, HHI_SYS_CPU_CLK_CNTL1);
+ return ret;
+}
+
+static int fix_pll_test(void) {
+ return 0;
+}
+
+static int ddr_pll_test(void) {
+ return 0;
+}
+
+static int hifi_pll_test_all(void){
+ unsigned int i=0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+ int ret=0;
+ unsigned int ctrl0 = 0;
+ for (i=0; i<(sizeof(hifipll_tbl)/sizeof(hifipll_tbl[0])); i++) {
+ ctrl0 = 0;
+ ctrl0 = ctrl0 | ((hifipll_tbl[i].m)<<0) | ((hifipll_tbl[i].n)<<10);
+ writel(0x01800000, ANACTRL_HIFIPLL_CTRL1);
+ writel(0x00001100, ANACTRL_HIFIPLL_CTRL2);
+ writel(0x10022300, ANACTRL_HIFIPLL_CTRL3);
+ writel(0x00300000, ANACTRL_HIFIPLL_CTRL4);
+ writel(0x01f18400 | ctrl0, ANACTRL_HIFIPLL_CTRL0);
+ writel(0x11f18400 | ctrl0, ANACTRL_HIFIPLL_CTRL0);
+ _udelay(10);
+ writel(0x15f18400 | ctrl0, ANACTRL_HIFIPLL_CTRL0);
+ _udelay(40);
+ writel(0x00001140, ANACTRL_HIFIPLL_CTRL2);
+ writel(0x00001100, ANACTRL_HIFIPLL_CTRL2);
+ _udelay(20);
+/* dump paras */
+#if 0
+ printf("hifi %d:\n", hifipll_tbl[i].rate);
+ printf("HHI_HIFI_PLL_CNTL0: 0x%8x\n", readl(HHI_HIFI_PLL_CNTL0));
+ //printf("HHI_HIFI_PLL_CNTL2: 0x%8x\n", readl(HHI_HIFI_PLL_CNTL2));
+ //printf("HHI_HIFI_PLL_CNTL3: 0x%8x\n", readl(HHI_HIFI_PLL_CNTL3));
+ //printf("HHI_HIFI_PLL_CNTL4: 0x%8x\n", readl(HHI_HIFI_PLL_CNTL4));
+ //printf("HHI_HIFI_PLL_CNTL5: 0x%8x\n", readl(HHI_HIFI_PLL_CNTL5));
+#endif
+
+ lock_check = PLL_LOCK_CHECK_MAX;
+ do {
+ update_bits(ANACTRL_HIFIPLL_CTRL0, 1<<26, 1 << 26);
+ _udelay(10);
+ update_bits(ANACTRL_HIFIPLL_CTRL0, 1<<26, 0);
+ _udelay(100);
+ //printf("hifi lock_check: %4d\n", lock_check);
+ } while((0 == ((Rd(ANACTRL_HIFIPLL_STS) >> 31) & 0x1)) && (--lock_check));
+
+ if (0 == lock_check) {
+ printf("HIFI pll lock Failed! - %4d MHz\n", hifipll_tbl[i].rate);
+ ret += RET_PLL_LOCK_FAIL;
+ }
+ else {
+ printf("HIFI pll lock OK! - %4d MHz. Div8 - %4d MHz. ", hifipll_tbl[i].rate, hifipll_tbl[i].rate>>PLL_DIV8_OFFSET);
+ Wr(CLKTREE_SPICC_CLK_CTRL, ((3<<9) | (1<<8) | (7<<0)));
+ //printf("CLKTREE_SPICC_CLK_CTRL: 0x%8x\n", readl(CLKTREE_SPICC_CLK_CTRL));
+ clk_msr_val = clk_util_clk_msr(16);
+ printf("CLKMSR(16) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, hifipll_tbl[i].rate>>PLL_DIV8_OFFSET)) {
+ printf(": Match\n");
+ }
+ else {
+ printf(": MisMatch\n");
+ ret += RET_CLK_NOT_MATCH;
+ }
+ }
+ }
+
+ return ret;
+
+}
+
+static int hifi_pll_test(hifi_pll_set_t * hifi_pll) {
+ int ret=0;
+ unsigned int i=0, pll_clk=0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+
+ for (i=0; i<(sizeof(hifipll_tbl)/sizeof(hifipll_tbl[0])); i++) {
+ if ((hifi_pll->pll_cntl0 & 0xFF) == hifipll_tbl[i].m) {
+ pll_clk = hifipll_tbl[i].rate;
+ }
+ }
+
+ writel(hifi_pll->pll_cntl1, ANACTRL_HIFIPLL_CTRL1);
+ writel(hifi_pll->pll_cntl2, ANACTRL_HIFIPLL_CTRL2);
+ writel(hifi_pll->pll_cntl3, ANACTRL_HIFIPLL_CTRL3);
+ writel(hifi_pll->pll_cntl4, ANACTRL_HIFIPLL_CTRL4);
+ writel(hifi_pll->pll_cntl0, ANACTRL_HIFIPLL_CTRL0);
+ writel(hifi_pll->pll_cntl0 | (1<<28), ANACTRL_HIFIPLL_CTRL0);
+ _udelay(10);
+ writel(hifi_pll->pll_cntl0 | (1<<28) | (1<<26), ANACTRL_HIFIPLL_CTRL0);
+ _udelay(40);
+ writel(hifi_pll->pll_cntl2 | (1<<6), ANACTRL_HIFIPLL_CTRL2);
+ writel(hifi_pll->pll_cntl2, ANACTRL_HIFIPLL_CTRL2);
+ _udelay(20);
+
+ lock_check = PLL_LOCK_CHECK_MAX;
+ do {
+ update_bits(ANACTRL_HIFIPLL_CTRL0, 1<<26, 1 << 26);
+ _udelay(10);
+ update_bits(ANACTRL_HIFIPLL_CTRL0, 1<<26, 0);
+ _udelay(100);
+ //printf("hifi lock_check: %4d\n", lock_check);
+ } while((0 == ((Rd(ANACTRL_HIFIPLL_STS) >> 31) & 0x1)) && (--lock_check));
+ if (0 == lock_check) {
+ printf("HIFI pll lock Failed! - %4d MHz\n", pll_clk);
+ ret += RET_PLL_LOCK_FAIL;
+ }
+ else {
+ printf("HIFI pll lock OK! - %4d MHz. Div8 - %4d MHz. ", pll_clk, pll_clk>>PLL_DIV8_OFFSET);
+ Wr(CLKTREE_SPICC_CLK_CTRL, ((3<<9) | (1<<8) | (7<<0)));
+ //printf("CLKTREE_SPICC_CLK_CTRL: 0x%8x\n", readl(CLKTREE_SPICC_CLK_CTRL));
+ clk_msr_val = clk_util_clk_msr(16);
+ printf("CLKMSR(16) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk>>PLL_DIV8_OFFSET)) {
+ printf(": Match\n");
+ }
+ else {
+ printf(": MisMatch\n");
+ ret += RET_CLK_NOT_MATCH;
+ }
+ }
+
+ return ret;
+}
+
+
+static int usbphy_pll_test_all(void) {
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ int ret=0;
+ unsigned long usbphy_base_cfg = 0xFE004000;
+
+ writel(0x09400414, (usbphy_base_cfg + 0x40));
+ writel(0x927e0000, (usbphy_base_cfg + 0x44));
+ writel(0xac5f69e5, (usbphy_base_cfg + 0x48));
+ writel(0x29400414, (usbphy_base_cfg + 0x40));
+ writel(0x09400414, (usbphy_base_cfg + 0x40));
+
+ do {
+ update_bits((usbphy_base_cfg + 0x40), 1<<29, 1 << 29);
+ _udelay(10);
+ update_bits((usbphy_base_cfg + 0x40), 1<<29, 0);
+ _udelay(100);
+ //printf("ethphy lock_check: %4d\n", lock_check);
+ } while ((!((readl(usbphy_base_cfg + 0x40)>>31)&0x1)) && --lock_check);
+
+ if (0 == lock_check) {
+ printf("usbphy pll lock Failed! - 480MHz\n");
+ ret += RET_PLL_LOCK_FAIL;
+ }
+ else {
+ printf("usbphy pll lock OK! - 480MHz.\n");
+ }
+
+ return ret;
+}
+
+static int usbphy_pll_test(usbphy_pll_set_t * usbphy_pll) {
+ int ret = 0;
+ unsigned int pll_clk = 0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned long usbphy_base_cfg = 0xFE004000;
+
+ if ((usbphy_pll->pll_cntl0 & 0x1FF) == 0x14) {
+ pll_clk = 480;
+ }
+ else
+ {
+ printf("input frequency point is not support\n");
+ return -1;
+ }
+ writel(usbphy_pll->pll_cntl0, (usbphy_base_cfg + 0x40));
+ writel(usbphy_pll->pll_cntl1, (usbphy_base_cfg + 0x44));
+ writel(usbphy_pll->pll_cntl2, (usbphy_base_cfg + 0x48));
+
+ lock_check = PLL_LOCK_CHECK_MAX;
+ do {
+ update_bits((usbphy_base_cfg + 0x40), 1<<29, 1 << 29);
+ _udelay(10);
+ update_bits((usbphy_base_cfg + 0x40), 1<<29, 0);
+ _udelay(100);
+ //printf("ethphy lock_check: %4d\n", lock_check);
+ } while ((!((readl(usbphy_base_cfg + 0x40)>>31)&0x1)) && --lock_check);
+ if (0 == lock_check) {
+ printf("usbphy pll lock Failed! - %4d MHz\n", pll_clk);
+ ret = RET_PLL_LOCK_FAIL;
+ }
+ else{
+ printf("usbphy pll lock OK! - %4d MHz.\n", pll_clk);
+ }
+
+ return ret;
+}
+
+
+#if 0
+static int hdmi_pll_init(hdmi_pll_set_t * hdmi_pll_set) {
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ do {
+ Wr(P_HHI_HDMI_PLL_CNTL0, hdmi_pll_set->pll_cntl0);
+ Wr(P_HHI_HDMI_PLL_CNTL1, hdmi_pll_set->pll_cntl1);
+ Wr(P_HHI_HDMI_PLL_CNTL2, hdmi_pll_set->pll_cntl2);
+ Wr(P_HHI_HDMI_PLL_CNTL3, hdmi_pll_set->pll_cntl3);
+ Wr(P_HHI_HDMI_PLL_CNTL4, hdmi_pll_set->pll_cntl4);
+ Wr(P_HHI_HDMI_PLL_CNTL5, hdmi_pll_set->pll_cntl5);
+ Wr(P_HHI_HDMI_PLL_CNTL6, hdmi_pll_set->pll_cntl6);
+ Wr(P_HHI_HDMI_PLL_CNTL0, Rd(P_HHI_HDMI_PLL_CNTL0) | (1<<29));
+ Wr(P_HHI_HDMI_PLL_CNTL0, Rd(P_HHI_HDMI_PLL_CNTL0) & (~(1<<29)));
+ //printf("lock_check: %d\n", lock_check);
+ _udelay(20);
+ } while ((!(0x3==((readl(P_HHI_HDMI_PLL_CNTL0)>>30)&0x3))) && --lock_check);
+ if (lock_check != 0)
+ return 0;
+ else
+ return RET_PLL_LOCK_FAIL;
+}
+
+static int hdmi_pll_test_all(hdmi_pll_cfg_t * hdmi_pll_cfg) {
+ unsigned int i=0;
+ int ret=0;
+ for (i=0; i<(sizeof(hdmi_pll_cfg_t)/sizeof(hdmi_pll_set_t)); i++) {
+ ret += hdmi_pll_test(&(hdmi_pll_cfg->hdmi_pll[i]));
+ }
+ return ret;
+}
+
+static int hdmi_pll_test(hdmi_pll_set_t * hdmi_pll_set) {
+ unsigned int i=0;
+ unsigned int pll_clk = 0;
+ unsigned int pll_clk_div = 0;
+ unsigned int clk_msr_val = 0;
+ unsigned int clk_msr_reg = 0;
+ int ret = 0;
+
+#if 0
+ /* store current pll cntl */
+ hdmi_pll_set_t hdmi_pll;
+ hdmi_pll.pll_cntl = readl(P_HHI_HDMI_PLL_CNTL0);
+ hdmi_pll.pll_cntl1 = readl(P_HHI_HDMI_PLL_CNTL1);
+ hdmi_pll.pll_cntl2 = readl(P_HHI_HDMI_PLL_CNTL2);
+ hdmi_pll.pll_cntl3 = readl(P_HHI_HDMI_PLL_CNTL3);
+ hdmi_pll.pll_cntl4 = readl(P_HHI_HDMI_PLL_CNTL4);
+ hdmi_pll.pll_cntl5 = readl(P_HHI_HDMI_PLL_CNTL5);
+#endif
+
+ /* store pll div setting */
+ clk_msr_reg = readl(HHI_VID_PLL_CLK_DIV);
+ /* connect vid_pll_div to HDMIPLL directly */
+ //writel(clk_msr_reg | HDMI_PLL_DIV_CNTL | HDMI_PLL_DIV_GATE, HHI_VID_PLL_CLK_DIV);
+ clrbits_le32(HHI_VID_PLL_CLK_DIV, 1<<19);
+ clrbits_le32(HHI_VID_PLL_CLK_DIV, 1<<15);
+
+#if 0
+ /* div1 */
+ setbits_le32(HHI_VID_PLL_CLK_DIV, 1<<18);
+#else
+ /* div14 */
+ clrbits_le32(HHI_VID_PLL_CLK_DIV, 1<<18);
+ clrbits_le32(HHI_VID_PLL_CLK_DIV, 0x3<<16);
+ clrbits_le32(HHI_VID_PLL_CLK_DIV, 1<<15);
+ clrbits_le32(HHI_VID_PLL_CLK_DIV, 0x7fff);
+ setbits_le32(HHI_VID_PLL_CLK_DIV, 1<<16);
+ setbits_le32(HHI_VID_PLL_CLK_DIV, 1<<15);
+ setbits_le32(HHI_VID_PLL_CLK_DIV, 0x3f80);
+ clrbits_le32(HHI_VID_PLL_CLK_DIV, 1<<15);
+#endif
+ setbits_le32(HHI_VID_PLL_CLK_DIV, 1<<19);
+
+ /* test pll */
+ for (i=0; i<(sizeof(hdmi_pll_cfg_t)/sizeof(hdmi_pll_set_t)); i++) {
+ if (hdmi_pll_set->pll_cntl0 == hdmi_pll_cfg.hdmi_pll[i].pll_cntl0) {
+ pll_clk = hdmi_pll_cfg.hdmi_pll[i].pll_clk;
+ }
+ }
+ _udelay(100);
+ ret = hdmi_pll_init(hdmi_pll_set);
+ _udelay(2000);
+ if (ret) {
+ printf("HDMI pll lock Failed! - %4d MHz\n", pll_clk);
+ }
+ else {
+ pll_clk_div = pll_clk/14;
+ printf("HDMI pll lock OK! - %4d MHz. Div14 - %4d MHz. ", pll_clk, pll_clk_div);
+ /* get [ 55][1485 MHz] vid_pll_div_clk_out */
+ clk_msr_val = clk_util_clk_msr(55);
+ printf("CLKMSR(55) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk_div)) {
+ printf(": Match\n");
+ }
+ else {
+ ret = RET_CLK_NOT_MATCH;
+ printf(": MisMatch\n");
+ }
+ }
+
+ /* restore pll */
+ //hdmi_pll_init(hdmi_pll);
+ //hdmi_pll_init(hdmi_pll_cfg->hdmi_pll[0]);
+
+ /* restore div cntl bit */
+ writel(clk_msr_reg, HHI_VID_PLL_CLK_DIV);
+
+ return ret;
+}
+
+static int gp0_pll_test(gp0_pll_set_t * gp0_pll) {
+ int ret=0;
+ unsigned int i=0, pll_clk=0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0, od=0;
+
+ for (i=0; i<(sizeof(gpll0_tbl)/sizeof(gpll0_tbl[0])); i++) {
+ if ((gp0_pll->pll_cntl0 & 0xFF) == gpll0_tbl[i].m) {
+ pll_clk = gpll0_tbl[i].rate;
+ od = gpll0_tbl[i].od;
+ }
+ }
+
+ writel(gp0_pll->pll_cntl0, HHI_GP0_PLL_CNTL0);
+ writel(gp0_pll->pll_cntl1, HHI_GP0_PLL_CNTL1);
+ writel(gp0_pll->pll_cntl2, HHI_GP0_PLL_CNTL2);
+ writel(gp0_pll->pll_cntl3, HHI_GP0_PLL_CNTL3);
+ writel(gp0_pll->pll_cntl4, HHI_GP0_PLL_CNTL4);
+ writel(gp0_pll->pll_cntl5, HHI_GP0_PLL_CNTL5);
+ writel(gp0_pll->pll_cntl6, HHI_GP0_PLL_CNTL6);
+ lock_check = PLL_LOCK_CHECK_MAX;
+ do {
+ update_bits(HHI_GP0_PLL_CNTL0, 1<<29, 1 << 29);
+ _udelay(10);
+ update_bits(HHI_GP0_PLL_CNTL0, 1<<29, 0);
+ _udelay(100);
+ //printf("gp0 lock_check: %4d\n", lock_check);
+ } while ((!((readl(HHI_GP0_PLL_CNTL0)>>31)&0x1)) && --lock_check);
+ if (0 == lock_check) {
+ printf("GP0 pll lock Failed! - %4d MHz\n", pll_clk);
+ ret = RET_PLL_LOCK_FAIL;
+ }
+ else {
+ printf("GP0 pll lock OK! - %4d MHz. ", pll_clk);
+ /* get gp0_pll_clk */
+ clk_msr_val = clk_util_clk_msr(4) << (5-od);
+ printf("CLKMSR(4) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk)) {
+ printf(": Match\n");
+ }
+ else {
+ printf(": MisMatch\n");
+ ret = RET_CLK_NOT_MATCH;
+ }
+ }
+ return ret;
+}
+
+static int gp0_pll_test_all(void) {
+ unsigned int i=0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+ int ret=0;
+
+ for (i=0; i<(sizeof(gpll0_tbl)/sizeof(gpll0_tbl[0])); i++) {
+ writel(0x380404e9, HHI_GP0_PLL_CNTL0);
+ writel(0x00000000, HHI_GP0_PLL_CNTL1);
+ writel(0x00000000, HHI_GP0_PLL_CNTL2);
+ writel(0x48681c00, HHI_GP0_PLL_CNTL3);
+ writel(0x33771290, HHI_GP0_PLL_CNTL4);
+ writel(0x39272000, HHI_GP0_PLL_CNTL5);
+ writel(0x56540000, HHI_GP0_PLL_CNTL6);
+ update_bits(HHI_GP0_PLL_CNTL0, (0x1ff << 0), (gpll0_tbl[i].m)<<0);
+ update_bits(HHI_GP0_PLL_CNTL0, (0x1f << 10), (gpll0_tbl[i].n)<<10);
+ update_bits(HHI_GP0_PLL_CNTL0, (0x3 << 16), (gpll0_tbl[i].od)<<16);
+/* dump paras */
+#if 0
+ printf("gp0 %d:\n", gpll0_tbl[i].rate);
+ printf("HHI_GP0_PLL_CNTL0: 0x%8x\n", readl(HHI_GP0_PLL_CNTL0));
+ //printf("HHI_GP0_PLL_CNTL2: 0x%8x\n", readl(HHI_GP0_PLL_CNTL2));
+ //printf("HHI_GP0_PLL_CNTL3: 0x%8x\n", readl(HHI_GP0_PLL_CNTL3));
+ //printf("HHI_GP0_PLL_CNTL4: 0x%8x\n", readl(HHI_GP0_PLL_CNTL4));
+ //printf("HHI_GP0_PLL_CNTL5: 0x%8x\n", readl(HHI_GP0_PLL_CNTL5));
+#endif
+ lock_check = PLL_LOCK_CHECK_MAX;
+ do {
+ update_bits(HHI_GP0_PLL_CNTL0, 1<<29, 1 << 29);
+ _udelay(10);
+ update_bits(HHI_GP0_PLL_CNTL0, 1<<29, 0);
+ _udelay(100);
+ //printf("gp0 lock_check: %4d\n", lock_check);
+ } while ((!((readl(HHI_GP0_PLL_CNTL0)>>31)&0x1)) && --lock_check);
+ if (0 == lock_check) {
+ printf("GP0 pll lock Failed! - %4d MHz\n", gpll0_tbl[i].rate);
+ ret += RET_PLL_LOCK_FAIL;
+ }
+ else {
+ printf("GP0 pll lock OK! - %4d MHz. ", gpll0_tbl[i].rate);
+ /* get gp0_pll_clk */
+ clk_msr_val = clk_util_clk_msr(4) << (5-gpll0_tbl[i].od);
+ printf("CLKMSR(4) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, gpll0_tbl[i].rate)) {
+ printf(": Match\n");
+ }
+ else {
+ printf(": MisMatch\n");
+ ret += RET_CLK_NOT_MATCH;
+ }
+ }
+ }
+
+ return ret;
+}
+#endif
+static int pll_test_all(unsigned char * pll_list) {
+ int ret = 0;
+ unsigned char i=0;
+ for (i=0; i<PLL_ENUM; i++) {
+ switch (pll_list[i]) {
+ case PLL_SYS:
+ ret = sys_pll_test_all(&sys_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_SYS);
+ break;
+ case PLL_FIX:
+ ret = fix_pll_test();
+ pll_report(ret, STR_PLL_TEST_FIX);
+ break;
+ case PLL_DDR:
+ ret = ddr_pll_test();
+ pll_report(ret, STR_PLL_TEST_DDR);
+ break;
+ case PLL_HIFI:
+ ret = hifi_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_HIFI);
+ break;
+ case PLL_USBPHY:
+ ret = usbphy_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_USBPHY);
+ break;
+ default:
+ break;
+ }
+ }
+ return ret;
+}
+
+int pll_test(int argc, char * const argv[])
+{
+ int ret = 0;
+
+ sys_pll_set_t sys_pll_set = {0};
+ hifi_pll_set_t hifi_pll_set = {0};
+ usbphy_pll_set_t usbphy_pll_set = {0};
+
+ unsigned char plls[PLL_ENUM] = {
+ PLL_SYS,
+ 0xff,// PLL_FIX, //0xff will skip this pll
+ 0xff,// PLL_DDR,
+ PLL_HIFI,
+ PLL_USBPHY,
+ };
+
+ if (0 == strcmp(STR_PLL_TEST_ALL, argv[1])) {
+ printf("Test all plls\n");
+ pll_test_all(plls);
+ }
+ else if(0 == strcmp(STR_PLL_TEST_SYS, argv[1])) {
+ if (argc == 2) {
+ ret = sys_pll_test_all(&sys_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_SYS);
+ }
+ else if (argc != 7){
+ printf("%s pll test: args error\n", STR_PLL_TEST_SYS);
+ return -1;
+ }
+ else {
+ sys_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL, 16);
+ sys_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, 16);
+ sys_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, 16);
+ sys_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL, 16);
+ sys_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL, 16);
+ ret = sys_pll_test(&sys_pll_set);
+ pll_report(ret, STR_PLL_TEST_SYS);
+ }
+ }
+ else if (0 == strcmp(STR_PLL_TEST_HIFI, argv[1])) {
+ if (argc == 2) {
+ ret = hifi_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_HIFI);
+ }
+ else if (argc != 7){
+ printf("%s pll test: args error\n", STR_PLL_TEST_HIFI);
+ return -1;
+ }
+ else {
+ hifi_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL, 16);
+ hifi_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, 16);
+ hifi_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, 16);
+ hifi_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL, 16);
+ hifi_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL, 16);
+ ret = hifi_pll_test(&hifi_pll_set);
+ pll_report(ret, STR_PLL_TEST_HIFI);
+ }
+ }
+ else if (0 == strcmp(STR_PLL_TEST_USBPHY, argv[1])) {
+ if (argc == 2) {
+ ret = usbphy_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_USBPHY);
+ }
+ else if (argc != 5){
+ printf("%s pll test: args error\n", STR_PLL_TEST_USBPHY);
+ return -1;
+ }
+ else {
+ usbphy_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL, 16);
+ usbphy_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, 16);
+ usbphy_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, 16);
+ ret = usbphy_pll_test(&usbphy_pll_set);
+ pll_report(ret, STR_PLL_TEST_USBPHY);
+ }
+ }
+ #if 0
+ else if (0 == strcmp(STR_PLL_TEST_HDMI, argv[1])) {
+ if (argc == 2) {
+ ret = hdmi_pll_test_all(&hdmi_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_HDMI);
+ }
+ else if (argc != 9){
+ printf("%s pll test: args error\n", STR_PLL_TEST_HDMI);
+ return -1;
+ }
+ else {
+ hdmi_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL, 16);
+ hdmi_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, 16);
+ hdmi_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, 16);
+ hdmi_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL, 16);
+ hdmi_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL, 16);
+ hdmi_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL, 16);
+ hdmi_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL, 16);
+ ret = hdmi_pll_test(&hdmi_pll_set);
+ pll_report(ret, STR_PLL_TEST_HDMI);
+ }
+ }
+ else if (0 == strcmp(STR_PLL_TEST_GP0, argv[1])) {
+ if (argc == 2) {
+ ret = gp0_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_GP0);
+ }
+ else if (argc != 9){
+ printf("%s pll test: args error\n", STR_PLL_TEST_GP0);
+ return -1;
+ }
+ else {
+ gp0_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL, 16);
+ gp0_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, 16);
+ gp0_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, 16);
+ gp0_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL, 16);
+ gp0_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL, 16);
+ gp0_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL, 16);
+ gp0_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL, 16);
+ ret = gp0_pll_test(&gp0_pll_set);
+ pll_report(ret, STR_PLL_TEST_GP0);
+ }
+ }
+ #endif
+ else if (0 == strcmp(STR_PLL_TEST_DDR, argv[1])) {
+ printf("%s pll not support now\n", STR_PLL_TEST_DDR);
+ return -1;
+ }
+ else if (0 == strcmp(STR_PLL_TEST_FIX, argv[1])) {
+ printf("%s pll not support now\n", STR_PLL_TEST_FIX);
+ return -1;
+ }
+
+#if 0
+ unsigned char * pll_list = NULL;
+ switch (get_cpu_id().family_id) {
+ case MESON_CPU_MAJOR_ID_GXTVBB:
+ pll_list = gxtvbb_plls;
+ break;
+ case MESON_CPU_MAJOR_ID_GXL:
+ pll_list = gxl_plls;
+ break;
+ default:
+ printf("un-support chip\n");
+ break;
+ }
+ if (pll_list) {
+ return plltest(pll_list);
+ }
+#endif
+
+ return 0;
+}
diff --git a/arch/arm/mach-meson/a1/power_cal.c b/arch/arm/mach-meson/a1/power_cal.c
new file mode 100644
index 0000000..e4f9c53
--- /dev/null
+++ b/arch/arm/mach-meson/a1/power_cal.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/io.h>
+#include <amlogic/saradc.h>
+#include <asm/arch/mailbox.h>
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2))))
+#define vcck_adc_channel 0x4
+#define ee_adc_channel 0x5
+#define default_ref_val 1800
+
+extern const int pwm_cal_voltage_table[][2];
+extern const int pwm_cal_voltage_table_ee[][2];
+extern int pwm_cal_voltage_table_size;
+extern int pwm_cal_voltage_table_ee_size;
+
+
+enum pwm_id {
+ pwm_vcck = 0,
+ pwm_ee,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+int32_t aml_delt_get(int adc_val, unsigned int voltage)
+{
+ unsigned int adc_volt;
+ int32_t delt;
+ int32_t div = 10; /*10mv is min step*/
+
+ if (adc_val != -1) {
+ adc_volt = default_ref_val*adc_val/1024;
+ printf("aml pwm cal adc_val = %x, adc_voltage = %d, def_voltage = %d\n",
+ adc_val, adc_volt, voltage);
+ } else {
+ adc_volt = voltage;
+ printf("warning:aml pwm cal adc get voltage error\n");
+ return 0;
+ }
+ delt = voltage - adc_volt;
+ delt = delt / div;
+ return delt;
+}
+
+void aml_set_voltage(unsigned int id, unsigned int voltage, int delt)
+{
+ int to;
+
+ switch (id) {
+ case pwm_vcck:
+ for (to = 0; to < pwm_cal_voltage_table_size; to++) {
+ if (pwm_cal_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ to +=delt;
+ if (to >= pwm_cal_voltage_table_size) {
+ to = pwm_cal_voltage_table_size - 1;
+ }
+ /*vcck volt set by dvfs and avs*/
+ //writel(pwm_voltage_table[to][0], PWM_PWM_A_ADRESS);
+ _udelay_(200);
+ break;
+
+ case pwm_ee:
+ for (to = 0; to < pwm_cal_voltage_table_ee_size; to++) {
+ if (pwm_cal_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ to +=delt;
+ if (to >= pwm_cal_voltage_table_ee_size) {
+ to = pwm_cal_voltage_table_ee_size - 1;
+ }
+ printf("aml pwm cal before ee_address: %x, ee_voltage: %x\n",
+ AO_PWM_PWM_B, readl(AO_PWM_PWM_B));
+ writel(pwm_cal_voltage_table_ee[to][0],AO_PWM_PWM_B);
+ _udelay_(1000);
+ printf("aml pwm cal after ee_address: %x, ee_voltage: %x\n",
+ AO_PWM_PWM_B, readl(AO_PWM_PWM_B));
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+int aml_cal_pwm(unsigned int ee_voltage, unsigned int vcck_voltage)
+{
+ int32_t ee_delt, vcck_delt;
+ unsigned int ee_val, vcck_val;
+ int ret;
+
+ /*txlx vcck ch4,vddee ch5*/
+ ret = adc_channel_single_shot_mode("adc", ADC_MODE_HIGH_PRECISION,
+ vcck_adc_channel, &vcck_val);
+ if (ret)
+ return ret;
+
+ ret = adc_channel_single_shot_mode("adc", ADC_MODE_HIGH_PRECISION,
+ ee_adc_channel, &ee_val);
+ if (ret)
+ return ret;
+
+ vcck_delt = aml_delt_get(vcck_val, vcck_voltage);
+ ee_delt = aml_delt_get(ee_val, ee_voltage);
+ send_pwm_delt(vcck_delt, ee_delt);
+ aml_set_voltage(pwm_ee, AML_VDDEE_INIT_VOLTAGE, ee_delt);
+ //aml_set_voltage(pwm_vcck, CONFIG_VCCK_INIT_VOLTAGE, vcck_delt);
+ printf("aml board pwm vcck: %x, ee: %x\n", vcck_delt, ee_delt);
+
+ return 0;
+}
+
+void aml_pwm_cal_init(int mode)
+{
+ printf("aml pwm cal init\n");
+ aml_cal_pwm(AML_VDDEE_INIT_VOLTAGE, AML_VCCK_INIT_VOLTAGE);
+}
diff --git a/arch/arm/mach-meson/a1/power_gate.h b/arch/arm/mach-meson/a1/power_gate.h
new file mode 100644
index 0000000..9ca1a9d
--- /dev/null
+++ b/arch/arm/mach-meson/a1/power_gate.h
@@ -0,0 +1,1161 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __POWER_MGR_HEADER_
+#define __POWER_MGR_HEADER_
+
+#include <asm/arch/io.h>
+#include <common.h>
+//#include <asm/arch-gxb/io.h>
+/* #include <asm/arch-gxb/register.h> */
+#include <asm/arch/secure_apb.h>
+/* clock gate control */
+
+#define DEBUG_MASK 0
+
+#define SET_CLK_GATE_MASK(reg, mask) __raw_writel((__raw_readl(reg)|mask), reg)
+#define CLEAR_CLK_GATE_MASK(reg, mask) \
+ __raw_writel((__raw_readl(reg)&(~mask)), reg)
+#define CLK_GATE_ON(_MOD) do { \
+ if (DEBUG_MASK) \
+ printf("on reg %24s before read :0x%x : 0x%x\n",\
+ GCLK_NAME_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ SET_CLK_GATE_MASK(GCLK_REG_##_MOD, \
+ (unsigned int)GCLK_MASK_##_MOD); \
+ if (DEBUG_MASK) \
+ printf("on reg %24s after read :0x%x : 0x%x\n",\
+ GCLK_NAME_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ } while (0)
+
+#define CLK_GATE_OFF(_MOD) do { \
+ if (DEBUG_MASK) \
+ printf("off reg[ %24s ][0x%08x]before read:0x%08x:0x%08x\n",\
+ GCLK_NAME_##_MOD, (int)GCLK_MASK_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ CLEAR_CLK_GATE_MASK(GCLK_REG_##_MOD, (unsigned int)GCLK_MASK_##_MOD);\
+ if (DEBUG_MASK)\
+ printf("off reg[ %24s ][0x%08x] read after:0x%08x:0x%08x\n",\
+ GCLK_NAME_##_MOD, \
+ (int)GCLK_MASK_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ } while (0)
+
+#define IS_CLK_GATE_ON(_MOD) (__raw_readl(GCLK_REG_##_MOD) & (GCLK_MASK_##_MOD))
+#define GATE_INIT(_MOD) GCLK_ref[GCLK_IDX_##_MOD] = IS_CLK_GATE_ON(_MOD) ? 1 : 0
+
+#define GCLK_IDX_DDR 0
+#define GCLK_NAME_DDR "DDR"
+#define GCLK_DEV_DDR "CLKGATE_DDR"
+#define GCLK_REG_DDR (HHI_GCLK_MPEG0)
+#define GCLK_MASK_DDR (1<<0)
+
+#define GCLK_IDX_DOS 1
+#define GCLK_NAME_DOS "DOS"
+#define GCLK_DEV_DOS "CLKGATE_DOS"
+#define GCLK_REG_DOS (HHI_GCLK_MPEG0)
+#define GCLK_MASK_DOS (1<<1)
+
+#define GCLK_IDX_RESERVED0_0 2
+#define GCLK_NAME_RESERVED0_0 "RESERVED0_0"
+#define GCLK_DEV_RESERVED0_0 "CLKGATE_RESERVED0_0"
+#define GCLK_REG_RESERVED0_0 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_0 (1<<2)
+
+#define GCLK_IDX_RESERVED0_1 3
+#define GCLK_NAME_RESERVED0_1 "RESERVED0_1"
+#define GCLK_DEV_RESERVED0_1 "CLKGATE_RESERVED0_1"
+#define GCLK_REG_RESERVED0_1 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_1 (1<<3)
+
+/* #define GCLK_IDX_AHB_BRIDGE 4 */
+/* #define GCLK_NAME_AHB_BRIDGE "AHB_BRIDGE" */
+/* #define GCLK_DEV_AHB_BRIDGE "CLKGATE_AHB_BRIDGE" */
+/* #define GCLK_REG_AHB_BRIDGE (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_AHB_BRIDGE (1<<4) */
+
+#define GCLK_IDX_ISA 5
+#define GCLK_NAME_ISA "ISA"
+#define GCLK_DEV_ISA "CLKGATE_ISA"
+#define GCLK_REG_ISA (HHI_GCLK_MPEG0)
+#define GCLK_MASK_ISA (1<<5)
+
+/* NEW ADD */
+#define GCLK_IDX_PL310_CBUS 6
+#define GCLK_NAME_PL310_CBUS "PL310_CBUS"
+#define GCLK_DEV_PL310_CBUS "CLKGATE_PL310_CBUS"
+#define GCLK_REG_PL310_CBUS (HHI_GCLK_MPEG0)
+#define GCLK_MASK_PL310_CBUS (1<<6)
+
+#define GCLK_IDX_PERIPHS_TOP 7
+#define GCLK_NAME_PERIPHS_TOP "PERIPHS_TOP"
+#define GCLK_DEV_PERIPHS_TOP "CLKGATE_PERIPHS_TOP"
+#define GCLK_REG_PERIPHS_TOP (HHI_GCLK_MPEG0)
+#define GCLK_MASK_PERIPHS_TOP (1<<7)
+
+#define GCLK_IDX_SPICC 8
+#define GCLK_NAME_SPICC "SPICC"
+#define GCLK_DEV_SPICC "CLKGATE_SPICC"
+#define GCLK_REG_SPICC (HHI_GCLK_MPEG0)
+#define GCLK_MASK_SPICC (1<<8)
+
+#define GCLK_IDX_I2C 9
+#define GCLK_NAME_I2C "I2C"
+#define GCLK_DEV_I2C "CLKGATE_I2C"
+#define GCLK_REG_I2C (HHI_GCLK_MPEG0)
+#define GCLK_MASK_I2C (1<<9)
+
+#define GCLK_IDX_SAR_ADC 10
+#define GCLK_NAME_SAR_ADC "SAR_ADC"
+#define GCLK_DEV_SAR_ADC "CLKGATE_SAR_ADC"
+//#define GCLK_REG_SAR_ADC (HHI_SAR_CLK_CNTL) //no HHI_SAR_CLK_CNTL on TXL
+#define GCLK_REG_SAR_ADC (AO_SAR_CLK)
+#define GCLK_MASK_SAR_ADC (1<<8)
+
+#define GCLK_IDX_SMART_CARD_MPEG_DOMAIN 11
+#define GCLK_NAME_SMART_CARD_MPEG_DOMAIN "SMART_CARD_MPEG_DOMAIN"
+#define GCLK_DEV_SMART_CARD_MPEG_DOMAIN "CLKGATE_SMART_CARD_MPEG_DOMAIN"
+#define GCLK_REG_SMART_CARD_MPEG_DOMAIN (HHI_GCLK_MPEG0)
+#define GCLK_MASK_SMART_CARD_MPEG_DOMAIN (1<<11)
+
+#define GCLK_IDX_RANDOM_NUM_GEN 12
+#define GCLK_NAME_RANDOM_NUM_GEN "RANDOM_NUM_GEN"
+#define GCLK_DEV_RANDOM_NUM_GEN "CLKGATE_RANDOM_NUM_GEN"
+#define GCLK_REG_RANDOM_NUM_GEN (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RANDOM_NUM_GEN (1<<12)
+
+#define GCLK_IDX_UART0 13
+#define GCLK_NAME_UART0 "UART0"
+#define GCLK_DEV_UART0 "CLKGATE_UART0"
+#define GCLK_REG_UART0 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_UART0 (1<<13)
+
+/* gxb no this clock gate */
+/* #define GCLK_IDX_SDHC 14 */
+/* #define GCLK_NAME_SDHC "SDHC" */
+/* #define GCLK_DEV_SDHC "CLKGATE_SDHC" */
+/* #define GCLK_REG_SDHC (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_SDHC (1<<14) */
+
+#define GCLK_IDX_STREAM 15
+#define GCLK_NAME_STREAM "STREAM"
+#define GCLK_DEV_STREAM "CLKGATE_STREAM"
+#define GCLK_REG_STREAM (HHI_GCLK_MPEG0)
+#define GCLK_MASK_STREAM (1<<15)
+
+#define GCLK_IDX_ASYNC_FIFO 16
+#define GCLK_NAME_ASYNC_FIFO "ASYNC_FIFO"
+#define GCLK_DEV_ASYNC_FIFO "CLKGATE_ASYNC_FIFO"
+#define GCLK_REG_ASYNC_FIFO (HHI_GCLK_MPEG0)
+#define GCLK_MASK_ASYNC_FIFO (1<<16)
+
+/* gxb no this clock gate */
+/* #define GCLK_IDX_SDIO 17 */
+/* #define GCLK_NAME_SDIO "SDIO" */
+/* #define GCLK_DEV_SDIO "CLKGATE_SDIO" */
+/* #define GCLK_REG_SDIO (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_SDIO (1<<17) */
+
+/* gxb no this clock gate */
+/* #define GCLK_IDX_AUD_BUF 18 */
+/* #define GCLK_NAME_AUD_BUF "AUD_BUF" */
+/* #define GCLK_DEV_AUD_BUF "CLKGATE_AUD_BUF" */
+/* #define GCLK_REG_AUD_BUF (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_AUD_BUF (1<<18) */
+
+#define GCLK_IDX_HIU_PARSER 19
+#define GCLK_NAME_HIU_PARSER "HIU_PARSER"
+#define GCLK_DEV_HIU_PARSER "CLKGATE_HIU_PARSER"
+#define GCLK_REG_HIU_PARSER (HHI_GCLK_MPEG0)
+#define GCLK_MASK_HIU_PARSER (1<<19)
+
+#define GCLK_IDX_RESERVED0_2 20
+#define GCLK_NAME_RESERVED0_2 "RESERVED0_2"
+#define GCLK_DEV_RESERVED0_2 "CLKGATE_RESERVED0_2"
+#define GCLK_REG_RESERVED0_2 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_2 (1<<20)
+
+/* NEW ADD */
+#define GCLK_IDX_RESERVED0_3 21
+#define GCLK_NAME_RESERVED0_3 "RESERVED0_3 "
+#define GCLK_DEV_RESERVED0_3 "CLKGATE_RESERVED0_3 "
+#define GCLK_REG_RESERVED0_3 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_3 (1<<21)
+
+#define GCLK_IDX_RESERVED0_4 22
+#define GCLK_NAME_RESERVED0_4 "RESERVED0_4"
+#define GCLK_DEV_RESERVED0_4 "CLKGATE_RESERVED0_4"
+#define GCLK_REG_RESERVED0_4 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_4 (1<<22)
+
+#define GCLK_IDX_ASSIST_MISC 23
+#define GCLK_NAME_ASSIST_MISC "ASSIST_MISC"
+#define GCLK_DEV_ASSIST_MISC "CLKGATE_ASSIST_MISC"
+#define GCLK_REG_ASSIST_MISC (HHI_GCLK_MPEG0)
+#define GCLK_MASK_ASSIST_MISC (1<<23)
+
+
+#define GCLK_IDX_EMMC_A 24
+#define GCLK_NAME_EMMC_A "EMMC_A"
+#define GCLK_DEV_EMMC_A "CLKGATE_EMMC_A"
+#define GCLK_REG_EMMC_A (HHI_GCLK_MPEG0)
+#define GCLK_MASK_EMMC_A (1<<24)
+
+#define GCLK_IDX_EMMC_B 25
+#define GCLK_NAME_EMMC_B "EMMC_B"
+#define GCLK_DEV_EMMC_B "CLKGATE_EMMC_B"
+#define GCLK_REG_EMMC_B (HHI_GCLK_MPEG0)
+#define GCLK_MASK_EMMC_B (1<<25)
+
+#define GCLK_IDX_EMMC_C 26
+#define GCLK_NAME_EMMC_C "EMMC_C"
+#define GCLK_DEV_EMMC_C "CLKGATE_EMMC_C"
+#define GCLK_REG_EMMC_C (HHI_GCLK_MPEG0)
+#define GCLK_MASK_EMMC_C (1<<26)
+
+#define GCLK_IDX_RESERVED0_8 27
+#define GCLK_NAME_RESERVED0_8 "RESERVED0_8"
+#define GCLK_DEV_RESERVED0_8 "CLKGATE_RESERVED0_8"
+#define GCLK_REG_RESERVED0_8 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_8 (1<<27)
+
+#define GCLK_IDX_RESERVED0_9 28
+#define GCLK_NAME_RESERVED0_9 "RESERVED0_9"
+#define GCLK_DEV_RESERVED0_9 "CLKGATE_RESERVED0_9"
+#define GCLK_REG_RESERVED0_9 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_9 (1<<28)
+
+#define GCLK_IDX_RESERVED0_A 29
+#define GCLK_NAME_RESERVED0_A "RESERVED0_A"
+#define GCLK_DEV_RESERVED0_A "CLKGATE_RESERVED0_A"
+#define GCLK_REG_RESERVED0_A (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_A (1<<29)
+
+#define GCLK_IDX_SPI 30
+#define GCLK_NAME_SPI "SPI"
+#define GCLK_DEV_SPI "CLKGATE_SPI"
+#define GCLK_REG_SPI (HHI_GCLK_MPEG0)
+#define GCLK_MASK_SPI (1<<30)
+
+#define GCLK_IDX_RESERVED0_B 31
+#define GCLK_NAME_RESERVED0_B "RESERVED0_B"
+#define GCLK_DEV_RESERVED0_B "CLKGATE_RESERVED0_B"
+#define GCLK_REG_RESERVED0_B (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_B (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_RESERVED1_1 32
+#define GCLK_NAME_RESERVED1_1 "RESERVED1_1"
+#define GCLK_DEV_RESERVED1_1 "CLKGATE_RESERVED1_1"
+#define GCLK_REG_RESERVED1_1 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_1 (1<<0)
+
+
+#define GCLK_IDX_RESERVED1_2 33
+#define GCLK_NAME_RESERVED1_2 "RESERVED1_2"
+#define GCLK_DEV_RESERVED1_2 "CLKGATE_RESERVED1_2"
+#define GCLK_REG_RESERVED1_2 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_2 (1<<1)
+
+
+#define GCLK_IDX_AUD_IN 34
+#define GCLK_NAME_AUD_IN "AUD_IN"
+#define GCLK_DEV_AUD_IN "CLKGATE_AUD_IN"
+#define GCLK_REG_AUD_IN (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AUD_IN (1<<2)
+
+#define GCLK_IDX_ETHERNET 35
+#define GCLK_NAME_ETHERNET "ETHERNET"
+#define GCLK_DEV_ETHERNET "CLKGATE_ETHERNET"
+#define GCLK_REG_ETHERNET (HHI_GCLK_MPEG1)
+#define GCLK_MASK_ETHERNET (1<<3)
+
+/* g12a no reg */
+#if 0
+#define GCLK_IDX_ETH_CLK 145
+#define GCLK_NAME_ETH_CLK "ETH_CLK"
+#define GCLK_REG_ETH_CLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_ETH_CLK (1<<3)
+#endif
+
+#define GCLK_IDX_DEMUX 36
+#define GCLK_NAME_DEMUX "DEMUX"
+#define GCLK_DEV_DEMUX "CLKGATE_DEMUX"
+#define GCLK_REG_DEMUX (HHI_GCLK_MPEG1)
+#define GCLK_MASK_DEMUX (1<<4)
+
+#define GCLK_IDX_RESERVED1_3 37
+#define GCLK_NAME_RESERVED1_3 "RESERVED1_3"
+#define GCLK_DEV_RESERVED1_3 "CLKGATE_RESERVED1_3"
+#define GCLK_REG_RESERVED1_3 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_3 (1<<5)
+
+#define GCLK_IDX_AIU_AI_TOP_GLUE 38
+#define GCLK_NAME_AIU_AI_TOP_GLUE "AIU_AI_TOP_GLUE"
+#define GCLK_DEV_AIU_AI_TOP_GLUE "CLKGATE_AIU_AI_TOP_GLUE"
+#define GCLK_REG_AIU_AI_TOP_GLUE (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AI_TOP_GLUE (1<<6)
+
+#define GCLK_IDX_AIU_IEC958 39
+#define GCLK_NAME_AIU_IEC958 "AIU_IEC958"
+#define GCLK_DEV_AIU_IEC958 "CLKGATE_AIU_IEC958"
+#define GCLK_REG_AIU_IEC958 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_IEC958 (1<<7)
+
+#define GCLK_IDX_AIU_I2S_OUT 40
+#define GCLK_NAME_AIU_I2S_OUT "AIU_I2S_OUT"
+#define GCLK_DEV_AIU_I2S_OUT "CLKGATE_AIU_I2S_OUT"
+#define GCLK_REG_AIU_I2S_OUT (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_I2S_OUT (1<<8)
+
+#define GCLK_IDX_AIU_AMCLK_MEASURE 41
+#define GCLK_NAME_AIU_AMCLK_MEASURE "AIU_AMCLK_MEASURE"
+#define GCLK_DEV_AIU_AMCLK_MEASURE "CLKGATE_AIU_AMCLK_MEASURE"
+#define GCLK_REG_AIU_AMCLK_MEASURE (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AMCLK_MEASURE (1<<9)
+
+#define GCLK_IDX_AIU_AIFIFO2 42
+#define GCLK_NAME_AIU_AIFIFO2 "AIU_AIFIFO2"
+#define GCLK_DEV_AIU_AIFIFO2 "CLKGATE_AIU_AIFIFO2"
+#define GCLK_REG_AIU_AIFIFO2 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AIFIFO2 (1<<10)
+
+#define GCLK_IDX_AIU_AUD_MIXER 43
+#define GCLK_NAME_AIU_AUD_MIXER "AIU_AUD_MIXER"
+#define GCLK_DEV_AIU_AUD_MIXER "CLKGATE_AIU_AUD_MIXER"
+#define GCLK_REG_AIU_AUD_MIXER (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AUD_MIXER (1<<11)
+
+#define GCLK_IDX_AIU_MIXER_REG 44
+#define GCLK_NAME_AIU_MIXER_REG "AIU_MIXER_REG"
+#define GCLK_DEV_AIU_MIXER_REG "CLKGATE_AIU_MIXER_REG"
+#define GCLK_REG_AIU_MIXER_REG (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_MIXER_REG (1<<12)
+
+#define GCLK_IDX_AIU_ADC 45
+#define GCLK_NAME_AIU_ADC "AIU_ADC"
+#define GCLK_DEV_AIU_ADC "CLKGATE_AIU_ADC"
+#define GCLK_REG_AIU_ADC (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_ADC (1<<13)
+
+#define GCLK_IDX_BLK_MOV 46
+#define GCLK_NAME_BLK_MOV "BLK_MOV"
+#define GCLK_DEV_BLK_MOV "CLKGATE_BLK_MOV"
+#define GCLK_REG_BLK_MOV (HHI_GCLK_MPEG1)
+#define GCLK_MASK_BLK_MOV (1<<14)
+
+/* NEW ADD */
+#define GCLK_IDX_AIU_TOP_LEVEL 47
+#define GCLK_NAME_AIU_TOP_LEVEL "AIU_TOP_LEVEL"
+#define GCLK_DEV_AIU_TOP_LEVEL "CLKGATE_AIU_TOP_LEVEL"
+#define GCLK_REG_AIU_TOP_LEVEL (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_TOP_LEVEL (1<<15)
+
+//g12a no reg
+#if 0
+#define GCLK_NAME_PCM_MCLK "PCM_MCLK"
+#define GCLK_REG_PCM_MCLK (HHI_PCM_CLK_CNTL)
+#define GCLK_MASK_PCM_MCLK (1<<9)
+
+#define GCLK_NAME_PCM_SCLK "PCM_SCLK"
+#define GCLK_REG_PCM_SCLK (HHI_PCM_CLK_CNTL)
+#define GCLK_MASK_PCM_SCLK (1<<22)
+#endif
+
+#define GCLK_IDX_UART1 48
+#define GCLK_NAME_UART1 "UART1"
+#define GCLK_DEV_UART1 "CLKGATE_UART1"
+#define GCLK_REG_UART1 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_UART1 (1<<16)
+
+#define GCLK_IDX_RESERVED1_4 49
+#define GCLK_NAME_RESERVED1_4 "RESERVED1_4"
+#define GCLK_DEV_RESERVED1_4 "CLKGATE_RESERVED1_4"
+#define GCLK_REG_RESERVED1_4 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_4 (1<<17)
+
+/* NEW ADD */
+#define GCLK_IDX_RESERVED1_5 50
+#define GCLK_NAME_RESERVED1_5 "RESERVED1_5"
+#define GCLK_DEV_RESERVED1_5 "CLKGATE_RESERVED1_5"
+#define GCLK_REG_RESERVED1_5 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_5 (1<<18)
+
+#define GCLK_IDX_RESERVED1_6 51
+#define GCLK_NAME_RESERVED1_6 "RESERVED1_6"
+#define GCLK_DEV_RESERVED1_6 "CLKGATE_RESERVED1_6"
+#define GCLK_REG_RESERVED1_6 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_6 (1<<19)
+
+#define GCLK_IDX_GE2D 52
+#define GCLK_NAME_GE2D "GE2D"
+#define GCLK_DEV_GE2D "CLKGATE_GE2D"
+#define GCLK_REG_GE2D (HHI_GCLK_MPEG1)
+#define GCLK_MASK_GE2D (1<<20)
+
+#define GCLK_IDX_USB0 53
+#define GCLK_NAME_USB0 "USB0"
+#define GCLK_DEV_USB0 "CLKGATE_USB0"
+#define GCLK_REG_USB0 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_USB0 (1<<21)
+
+#define GCLK_IDX_USB1 54
+#define GCLK_NAME_USB1 "USB1"
+#define GCLK_DEV_USB1 "CLKGATE_USB1"
+#define GCLK_REG_USB1 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_USB1 (1<<22)
+
+#define GCLK_IDX_RESET 55
+#define GCLK_NAME_RESET "RESET"
+#define GCLK_DEV_RESET "CLKGATE_RESET"
+#define GCLK_REG_RESET (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESET (1<<23)
+
+#define GCLK_IDX_NAND_CLK 56
+#define GCLK_NAME_NAND_CLK "NAND CLK"
+#define GCLK_DEV_NAND_CLK "HHI_NAND_CLK"
+#define GCLK_REG_NAND_CLK (HHI_NAND_CLK_CNTL)
+#define GCLK_MASK_NAND_CLK (1<<7)
+
+#define GCLK_IDX_HIU_PARSER_TOP 57
+#define GCLK_NAME_HIU_PARSER_TOP "HIU_PARSER_TOP"
+#define GCLK_DEV_HIU_PARSER_TOP "CLKGATE_HIU_PARSER_TOP"
+#define GCLK_REG_HIU_PARSER_TOP (HHI_GCLK_MPEG1)
+#define GCLK_MASK_HIU_PARSER_TOP (1<<25)
+
+/* NEW ADD */
+
+/* g12a no reg */
+#if 0
+#define GCLK_NAME_USB_CLK "USB_CLK"
+#define GCLK_REG_USB_CLK (HHI_USB_CLK_CNTL)
+#define GCLK_MASK_USB_CLK (1<<9)
+#endif
+
+#define GCLK_IDX_USB_GENERAL 58
+#define GCLK_NAME_USB_GENERAL "USB_GENERAL"
+#define GCLK_DEV_USB_GENERAL "CLKGATE_USB_GENERAL"
+#define GCLK_REG_USB_GENERAL (HHI_GCLK_MPEG1)
+#define GCLK_MASK_USB_GENERAL (1<<26)
+
+#define GCLK_IDX_RESERVED1_7 59
+#define GCLK_NAME_RESERVED1_7 "RESERVED1_7"
+#define GCLK_DEV_RESERVED1_7 "CLKGATE_RESERVED1_7"
+#define GCLK_REG_RESERVED1_7 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_7 (1<<27)
+
+/* #define GCLK_IDX_VDIN1 60 */
+/* #define GCLK_NAME_VDIN1 "VDIN1" */
+/* #define GCLK_DEV_VDIN1 "CLKGATE_VDIN1" */
+/* #define GCLK_REG_VDIN1 (HHI_GCLK_MPEG1) */
+/* #define GCLK_MASK_VDIN1 (1<<28) */
+
+#define GCLK_IDX_AHB_ARB0 61
+#define GCLK_NAME_AHB_ARB0 "AHB_ARB0"
+#define GCLK_DEV_AHB_ARB0 "CLKGATE_AHB_ARB0"
+#define GCLK_REG_AHB_ARB0 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AHB_ARB0 (1<<29)
+
+#define GCLK_IDX_EFUSE 62
+#define GCLK_NAME_EFUSE "EFUSE"
+#define GCLK_DEV_EFUSE "CLKGATE_EFUSE"
+#define GCLK_REG_EFUSE (HHI_GCLK_MPEG1)
+#define GCLK_MASK_EFUSE (1<<30)
+
+#define GCLK_IDX_ROM_CLK 63
+#define GCLK_NAME_ROM_CLK "ROM_CLK"
+#define GCLK_DEV_ROM_CLK "CLKGATE_ROM_CLK"
+#define GCLK_REG_ROM_CLK (HHI_GCLK_MPEG1)
+#define GCLK_MASK_ROM_CLK (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_RESERVED2_0 64
+#define GCLK_NAME_RESERVED2_0 "RESERVED2_0"
+#define GCLK_DEV_RESERVED2_0 "CLKGATE_RESERVED2_0"
+#define GCLK_REG_RESERVED2_0 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_0 (1<<0)
+
+#define GCLK_IDX_AHB_DATA_BUS 65
+#define GCLK_NAME_AHB_DATA_BUS "AHB_DATA_BUS"
+#define GCLK_DEV_AHB_DATA_BUS "CLKGATE_AHB_DATA_BUS"
+#define GCLK_REG_AHB_DATA_BUS (HHI_GCLK_MPEG2)
+#define GCLK_MASK_AHB_DATA_BUS (1<<1)
+
+#define GCLK_IDX_AHB_CONTROL_BUS 66
+#define GCLK_NAME_AHB_CONTROL_BUS "AHB_CONTROL_BUS"
+#define GCLK_DEV_AHB_CONTROL_BUS "CLKGATE_AHB_CONTROL_BUS"
+#define GCLK_REG_AHB_CONTROL_BUS (HHI_GCLK_MPEG2)
+#define GCLK_MASK_AHB_CONTROL_BUS (1<<2)
+
+#define GCLK_IDX_HDMI_INTR_SYNC 67
+#define GCLK_NAME_HDMI_INTR_SYNC "HDMI_INTR_SYNC"
+#define GCLK_DEV_HDMI_INTR_SYNC "CLKGATE_HDMI_INTR_SYNC"
+#define GCLK_REG_HDMI_INTR_SYNC (HHI_GCLK_MPEG2)
+#define GCLK_MASK_HDMI_INTR_SYNC (1<<3)
+
+#define GCLK_IDX_HDMI_PCLK 68
+#define GCLK_NAME_HDMI_PCLK "HDMI_PCLK"
+#define GCLK_DEV_HDMI_PCLK "CLKGATE_HDMI_PCLK"
+#define GCLK_REG_HDMI_PCLK (HHI_GCLK_MPEG2)
+#define GCLK_MASK_HDMI_PCLK (1<<4)
+
+#define GCLK_IDX_PDM 69
+#define GCLK_NAME_PDM "PDM"
+#define GCLK_DEV_PDM "CLKGATE_PDM"
+#define GCLK_REG_PDM (HHI_GCLK_MPEG2)
+#define GCLK_MASK_PDM (1<<5)
+
+#define GCLK_IDX_BT656 70
+#define GCLK_NAME_BT656 "BT656"
+#define GCLK_DEV_BT656 "CLKGATE_BT656"
+#define GCLK_REG_BT656 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_BT656 (1<<6)
+
+#define GCLK_IDX_BT656_2 71
+#define GCLK_NAME_BT656_2 "BT656_2"
+#define GCLK_DEV_BT656_2 "CLKGATE_BT656_2"
+#define GCLK_REG_BT656_2 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_BT656_2 (1<<7)
+
+#define GCLK_IDX_MISC_USB1_TO_DDR 72
+#define GCLK_NAME_MISC_USB1_TO_DDR "MISC_USB1_TO_DDR"
+#define GCLK_DEV_MISC_USB1_TO_DDR "CLKGATE_MISC_USB1_TO_DDR"
+#define GCLK_REG_MISC_USB1_TO_DDR (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MISC_USB1_TO_DDR (1<<8)
+
+#define GCLK_IDX_MISC_USB0_TO_DDR 73
+#define GCLK_NAME_MISC_USB0_TO_DDR "MISC_USB0_TO_DDR"
+#define GCLK_DEV_MISC_USB0_TO_DDR "CLKGATE_MISC_USB0_TO_DDR"
+#define GCLK_REG_MISC_USB0_TO_DDR (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MISC_USB0_TO_DDR (1<<9)
+
+#define GCLK_IDX_RESERVED2_4 74
+#define GCLK_NAME_RESERVED2_4 "RESERVED2_4"
+#define GCLK_DEV_RESERVED2_4 "CLKGATE_RESERVED2_4"
+#define GCLK_REG_RESERVED2_4 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_4 (1<<10)
+
+#define GCLK_IDX_MMC_PCLK 75
+#define GCLK_NAME_MMC_PCLK "MMC_PCLK"
+#define GCLK_DEV_MMC_PCLK "CLKGATE_MMC_PCLK"
+#define GCLK_REG_MMC_PCLK (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MMC_PCLK (1<<11)
+
+//g12a no reg
+#if 0
+#define GCLK_NAME_MMC_A_PCLK "MMC_A_PCLK"
+#define GCLK_REG_MMC_A_PCLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_MMC_A_PCLK (1<<2)
+
+#define GCLK_NAME_MMC_B_PCLK "MMC_B_PCLK"
+#define GCLK_REG_MMC_B_PCLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_MMC_B_PCLK (1<<1)
+
+#define GCLK_NAME_MMC_C_PCLK "MMC_C_PCLK"
+#define GCLK_REG_MMC_C_PCLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_MMC_C_PCLK (1<<0)
+#endif
+
+#define GCLK_NAME_EMMC_A_CLK "EMMC_A_CLK"
+#define GCLK_REG_EMMC_A_CLK (HHI_SD_EMMC_CLK_CNTL)
+#define GCLK_MASK_EMMC_A_CLK (1<<7)
+
+#define GCLK_NAME_EMMC_B_CLK "EMMC_B_CLK"
+#define GCLK_REG_EMMC_B_CLK (HHI_SD_EMMC_CLK_CNTL)
+#define GCLK_MASK_EMMC_B_CLK (1<<23)
+
+#define GCLK_IDX_MISC_DVIN 76
+#define GCLK_NAME_MISC_DVIN "MISC_DVIN"
+#define GCLK_DEV_MISC_DVIN "CLKGATE_MISC_DVIN"
+#define GCLK_REG_MISC_DVIN (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MISC_DVIN (1<<12)
+
+#define GCLK_IDX_RESERVED2_5 77
+#define GCLK_NAME_RESERVED2_5 "RESERVED2_5"
+#define GCLK_DEV_RESERVED2_5 "CLKGATE_RESERVED2_5"
+#define GCLK_REG_RESERVED2_5 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_5 (1<<13)
+
+#define GCLK_IDX_RESERVED2_6 78
+#define GCLK_NAME_RESERVED2_6 "RESERVED2_6"
+#define GCLK_DEV_RESERVED2_6 "CLKGATE_RESERVED2_6"
+#define GCLK_REG_RESERVED2_6 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_6 (1<<14)
+
+#define GCLK_IDX_UART2 79
+#define GCLK_NAME_UART2 "UART2"
+#define GCLK_DEV_UART2 "CLKGATE_UART2"
+#define GCLK_REG_UART2 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_UART2 (1<<15)
+
+#define GCLK_IDX_RESERVED2_7 80
+#define GCLK_NAME_RESERVED2_7 "RESERVED2_7"
+#define GCLK_DEV_RESERVED2_7 "CLKGATE_RESERVED2_7"
+#define GCLK_REG_RESERVED2_7 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_7 (1<<16)
+
+#define GCLK_IDX_RESERVED2_8 81
+#define GCLK_NAME_RESERVED2_8 "RESERVED2_8"
+#define GCLK_DEV_RESERVED2_8 "CLKGATE_RESERVED2_8"
+#define GCLK_REG_RESERVED2_8 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_8 (1<<17)
+
+#define GCLK_IDX_RESERVED2_9 82
+#define GCLK_NAME_RESERVED2_9 "RESERVED2_9"
+#define GCLK_DEV_RESERVED2_9 "CLKGATE_RESERVED2_9"
+#define GCLK_REG_RESERVED2_9 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_9 (1<<18)
+
+#define GCLK_IDX_RESERVED2_A 83
+#define GCLK_NAME_RESERVED2_A "RESERVED2_A"
+#define GCLK_DEV_RESERVED2_A "CLKGATE_RESERVED2_A"
+#define GCLK_REG_RESERVED2_A (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_A (1<<19)
+
+#define GCLK_IDX_RESERVED2_B 84
+#define GCLK_NAME_RESERVED2_B "RESERVED2_B"
+#define GCLK_DEV_RESERVED2_B "CLKGATE_RESERVED2_B"
+#define GCLK_REG_RESERVED2_B (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_B (1<<20)
+
+#define GCLK_IDX_UART3 85
+#define GCLK_NAME_UART3 "UART3"
+#define GCLK_DEV_UART3 "CLKGATE_UART3"
+#define GCLK_REG_UART3 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_UART3 (1<<21)
+
+#define GCLK_IDX_SANA 86
+#define GCLK_NAME_SANA "SANA"
+#define GCLK_DEV_SANA "CLKGATE_SANA"
+#define GCLK_REG_SANA (HHI_GCLK_MPEG2)
+#define GCLK_MASK_SANA (1<<22)
+
+#define GCLK_IDX_RESERVED2_D 87
+#define GCLK_NAME_RESERVED2_D "RESERVED2_D"
+#define GCLK_DEV_RESERVED2_D "CLKGATE_RESERVED2_D"
+#define GCLK_REG_RESERVED2_D (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_D (1<<23)
+
+#define GCLK_IDX_RESERVED2_E 88
+#define GCLK_NAME_RESERVED2_E "RESERVED2_E"
+#define GCLK_DEV_RESERVED2_E "CLKGATE_RESERVED2_E"
+#define GCLK_REG_RESERVED2_E (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_E (1<<24)
+
+#define GCLK_IDX_VPU_INTR 89
+#define GCLK_NAME_VPU_INTR "VPU_INTR"
+#define GCLK_DEV_VPU_INTR "CLKGATE_VPU_INTR"
+#define GCLK_REG_VPU_INTR (HHI_GCLK_MPEG2)
+#define GCLK_MASK_VPU_INTR (1<<25)
+
+#define GCLK_IDX_SECURE_AHP_APB3 90
+#define GCLK_NAME_SECURE_AHP_APB3 "SECURE_AHP_APB3"
+#define GCLK_DEV_SECURE_AHP_APB3 "CLKGATE_SECURE_AHP_APB3"
+#define GCLK_REG_SECURE_AHP_APB3 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_SECURE_AHP_APB3 (1<<26)
+
+#define GCLK_IDX_RESERVED2_F 91
+#define GCLK_NAME_RESERVED2_F "RESERVED2_F"
+#define GCLK_DEV_RESERVED2_F "CLKGATE_RESERVED2_F"
+#define GCLK_REG_RESERVED2_F (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_F (1<<27)
+
+#define GCLK_IDX_RESERVED2_10 92
+#define GCLK_NAME_RESERVED2_10 "RESERVED2_10"
+#define GCLK_DEV_RESERVED2_10 "CLKGATE_RESERVED2_10"
+#define GCLK_REG_RESERVED2_10 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_10 (1<<28)
+
+#define GCLK_IDX_CLK81_TO_A9 93
+#define GCLK_NAME_CLK81_TO_A9 "CLK81_TO_A9"
+#define GCLK_DEV_CLK81_TO_A9 "CLKGATE_CLK81_TO_A9"
+#define GCLK_REG_CLK81_TO_A9 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_CLK81_TO_A9 (1<<29)
+
+#define GCLK_IDX_GIC 94
+#define GCLK_NAME_GIC "GIC"
+#define GCLK_DEV_GIC "CLKGATE_GIC"
+#define GCLK_REG_GIC (HHI_GCLK_MPEG2)
+#define GCLK_MASK_GIC (1<<30)
+
+#define GCLK_IDX_RESERVED2_12 95
+#define GCLK_NAME_RESERVED2_12 "RESERVED2_12"
+#define GCLK_DEV_RESERVED2_12 "CLKGATE_RESERVED2_12"
+#define GCLK_REG_RESERVED2_12 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_12 (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_RESERVED3_0 96
+#define GCLK_NAME_RESERVED3_0 "RESERVED3_0"
+#define GCLK_DEV_RESERVED3_0 "CLKGATE_RESERVED3_0"
+#define GCLK_REG_RESERVED3_0 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_0 (1<<0)
+
+#define GCLK_IDX_VCLK2_VENCI 97
+#define GCLK_NAME_VCLK2_VENCI "VCLK2_VENCI"
+#define GCLK_DEV_VCLK2_VENCI "CLKGATE_VCLK2_VENCI"
+#define GCLK_REG_VCLK2_VENCI (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCI (1<<1)
+
+#define GCLK_IDX_VCLK2_VENCI1 98
+#define GCLK_NAME_VCLK2_VENCI1 "VCLK2_VENCI1"
+#define GCLK_DEV_VCLK2_VENCI1 "CLKGATE_VCLK2_VENCI1"
+#define GCLK_REG_VCLK2_VENCI1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCI1 (1<<2)
+
+#define GCLK_IDX_VCLK2_VENCP 99
+#define GCLK_NAME_VCLK2_VENCP "VCLK2_VENCP"
+#define GCLK_DEV_VCLK2_VENCP "CLKGATE_VCLK2_VENCP"
+#define GCLK_REG_VCLK2_VENCP (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCP (1<<3)
+
+#define GCLK_IDX_VCLK2_VENCP1 100
+#define GCLK_NAME_VCLK2_VENCP1 "VCLK2_VENCP1"
+#define GCLK_DEV_VCLK2_VENCP1 "CLKGATE_VCLK2_VENCP1"
+#define GCLK_REG_VCLK2_VENCP1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCP1 (1<<4)
+
+#define GCLK_IDX_VCLK2_VENCT 101
+#define GCLK_NAME_VCLK2_VENCT "VCLK2_VENCT"
+#define GCLK_DEV_VCLK2_VENCT "CLKGATE_VCLK2_VENCT"
+#define GCLK_REG_VCLK2_VENCT (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCT (1<<5)
+
+#define GCLK_IDX_VCLK2_VENCT1 102
+#define GCLK_NAME_VCLK2_VENCT1 "VCLK2_VENCT1"
+#define GCLK_DEV_VCLK2_VENCT1 "CLKGATE_VCLK2_VENCT1"
+#define GCLK_REG_VCLK2_VENCT1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCT1 (1<<6)
+
+#define GCLK_IDX_VCLK2_OTHER 103
+#define GCLK_NAME_VCLK2_OTHER "VCLK2_OTHER"
+#define GCLK_DEV_VCLK2_OTHER "CLKGATE_VCLK2_OTHER"
+#define GCLK_REG_VCLK2_OTHER (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_OTHER (1<<7)
+
+#define GCLK_IDX_VCLK2_ENCI 104
+#define GCLK_NAME_VCLK2_ENCI "VCLK2_ENCI"
+#define GCLK_DEV_VCLK2_ENCI "CLKGATE_VCLK2_ENCI"
+#define GCLK_REG_VCLK2_ENCI (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCI (1<<8)
+
+#define GCLK_IDX_VCLK2_ENCP 105
+#define GCLK_NAME_VCLK2_ENCP "VCLK2_ENCP"
+#define GCLK_DEV_VCLK2_ENCP "CLKGATE_VCLK2_ENCP"
+#define GCLK_REG_VCLK2_ENCP (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCP (1<<9)
+
+#define GCLK_IDX_DAC_CLK 106
+#define GCLK_NAME_DAC_CLK "DAC_CLK"
+#define GCLK_DEV_DAC_CLK "CLKGATE_DAC_CLK"
+#define GCLK_REG_DAC_CLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_DAC_CLK (1<<10)
+
+#define GCLK_IDX_RESERVED3_1 107
+#define GCLK_NAME_RESERVED3_1 "RESERVED3_1"
+#define GCLK_DEV_RESERVED3_1 "CLKGATE_RESERVED3_1"
+#define GCLK_REG_RESERVED3_1 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_1 (1<<11)
+
+#define GCLK_IDX_RESERVED3_2 108
+#define GCLK_NAME_RESERVED3_2 "RESERVED3_2"
+#define GCLK_DEV_RESERVED3_2 "CLKGATE_RESERVED3_2"
+#define GCLK_REG_RESERVED3_2 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_2 (1<<12)
+
+#define GCLK_IDX_RESERVED3_3 109
+#define GCLK_NAME_RESERVED3_3 "RESERVED3_3"
+#define GCLK_DEV_RESERVED3_3 "CLKGATE_RESERVED3_3"
+#define GCLK_REG_RESERVED3_3 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_3 (1<<13)
+
+#define GCLK_IDX_AIU_AOCLK 110
+#define GCLK_NAME_AIU_AOCLK "AIU_AOCLK"
+#define GCLK_DEV_AIU_AOCLK "CLKGATE_AIU_AOCLK"
+#define GCLK_REG_AIU_AOCLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_AIU_AOCLK (1<<14)
+
+#define GCLK_IDX_RESERVED3_4 111
+#define GCLK_NAME_RESERVED3_4 "RESERVED3_4"
+#define GCLK_DEV_RESERVED3_4 "CLKGATE_RESERVED3_4"
+#define GCLK_REG_RESERVED3_4 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_4 (1<<15)
+
+#define GCLK_IDX_AIU_ICE958_AMCLK 112
+#define GCLK_NAME_AIU_ICE958_AMCLK "AIU_ICE958_AMCLK"
+#define GCLK_DEV_AIU_ICE958_AMCLK "CLKGATE_AIU_ICE958_AMCLK"
+#define GCLK_REG_AIU_ICE958_AMCLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_AIU_ICE958_AMCLK (1<<16)
+
+#define GCLK_IDX_RESERVED3_5 113
+#define GCLK_NAME_RESERVED3_5 "RESERVED3_5"
+#define GCLK_DEV_RESERVED3_5 "CLKGATE_RESERVED3_5"
+#define GCLK_REG_RESERVED3_5 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_5 (1<<17)
+
+#define GCLK_IDX_RESERVED3_6 114
+#define GCLK_NAME_RESERVED3_6 "RESERVED3_6"
+#define GCLK_DEV_RESERVED3_6 "CLKGATE_RESERVED3_6"
+#define GCLK_REG_RESERVED3_6 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_6 (1<<18)
+
+#define GCLK_IDX_RESERVED3_7 115
+#define GCLK_NAME_RESERVED3_7 "RESERVED3_7"
+#define GCLK_DEV_RESERVED3_7 "CLKGATE_RESERVED3_7"
+#define GCLK_REG_RESERVED3_7 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_7 (1<<19)
+
+#define GCLK_IDX_ENC480P 116
+#define GCLK_NAME_ENC480P "ENC480P"
+#define GCLK_DEV_ENC480P "CLKGATE_ENC480P"
+#define GCLK_REG_ENC480P (HHI_GCLK_OTHER)
+#define GCLK_MASK_ENC480P (1<<20)
+
+#define GCLK_IDX_RANDOM_NUM_GEN1 117
+#define GCLK_NAME_RANDOM_NUM_GEN1 "RANDOM_NUM_GEN1"
+#define GCLK_DEV_RANDOM_NUM_GEN1 "CLKGATE_RANDOM_NUM_GEN1"
+#define GCLK_REG_RANDOM_NUM_GEN1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RANDOM_NUM_GEN1 (1<<21)
+
+#define GCLK_IDX_VCLK2_ENCT 118
+#define GCLK_NAME_VCLK2_ENCT "GCLK_VENCL_INT"
+#define GCLK_DEV_VCLK2_ENCT "CLKGATE_GCLK_VENCL_INT"
+#define GCLK_REG_VCLK2_ENCT (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCT (1<<22)
+
+#define GCLK_IDX_VCLK2_ENCL 119
+#define GCLK_NAME_VCLK2_ENCL "VLKC2_ENCL"
+#define GCLK_DEV_VCLK2_ENCL "CLKGATE_VCLK2_ENCL"
+#define GCLK_REG_VCLK2_ENCL (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCL (1<<23)
+
+#define GCLK_IDX_MMC_CLK 120
+#define GCLK_NAME_MMC_CLK "MMC_CLK"
+#define GCLK_DEV_MMC_CLK "CLKGATE_MMC_CLK"
+#define GCLK_REG_MMC_CLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_MMC_CLK (1<<24)
+
+#define GCLK_IDX_VCLK2_VENCL 121
+#define GCLK_NAME_VCLK2_VENCL "VCLK2_VENCL"
+#define GCLK_DEV_VCLK2_VENCL "CLKGATE_VCLK2_VENCL"
+#define GCLK_REG_VCLK2_VENCL (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCL (1<<25)
+
+#define GCLK_IDX_VCLK2_OTHER1 122
+#define GCLK_NAME_VCLK2_OTHER1 "VCLK2_OTHER1"
+#define GCLK_DEV_VCLK2_OTHER1 "CLKGATE_VCLK2_OTHER1"
+#define GCLK_REG_VCLK2_OTHER1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_OTHER1 (1<<26)
+
+#define GCLK_IDX_RESERVED3_9 123
+#define GCLK_NAME_RESERVED3_9 "RESERVED3_9"
+#define GCLK_DEV_RESERVED3_9 "CLKGATE_RESERVED3_9"
+#define GCLK_REG_RESERVED3_9 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_9 (1<<27)
+
+#define GCLK_IDX_RESERVED3_A 124
+#define GCLK_NAME_RESERVED3_A "RESERVED3_A"
+#define GCLK_DEV_RESERVED3_A "CLKGATE_RESERVED3_A"
+#define GCLK_REG_RESERVED3_A (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_A (1<<28)
+
+#define GCLK_IDX_RESERVED3_B 125
+#define GCLK_NAME_RESERVED3_B "RESERVED3_B"
+#define GCLK_DEV_RESERVED3_B "CLKGATE_RESERVED3_B"
+#define GCLK_REG_RESERVED3_B (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_B (1<<29)
+
+#define GCLK_IDX_RESERVED3_C 126
+#define GCLK_NAME_RESERVED3_C "RESERVED3_C"
+#define GCLK_DEV_RESERVED3_C "CLKGATE_RESERVED3_C"
+#define GCLK_REG_RESERVED3_C (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_C (1<<30)
+
+#define GCLK_IDX_EDP_CLK 127
+#define GCLK_NAME_EDP_CLK "EDP_CLK"
+#define GCLK_DEV_EDP_CLK "CLKGATE_EDP_CLK"
+#define GCLK_REG_EDP_CLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_EDP_CLK (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_MEDIA_CPU 128
+#define GCLK_NAME_MEDIA_CPU "MEDIA_CPU"
+#define GCLK_DEV_MEDIA_CPU "CLKGATE_MEDIA_CPU"
+#define GCLK_REG_MEDIA_CPU (HHI_GCLK_AO)
+#define GCLK_MASK_MEDIA_CPU (1<<0)
+
+#define GCLK_IDX_AHB_SRAM 129
+#define GCLK_NAME_AHB_SRAM "AHB_SRAM"
+#define GCLK_DEV_AHB_SRAM "CLKGATE_AHB_SRAM"
+#define GCLK_REG_AHB_SRAM (HHI_GCLK_AO)
+#define GCLK_MASK_AHB_SRAM (1<<1)
+
+#define GCLK_IDX_AHB_BUS 130
+#define GCLK_NAME_AHB_BUS "AHB_BUS"
+#define GCLK_DEV_AHB_BUS "CLKGATE_AHB_BUS"
+#define GCLK_REG_AHB_BUS (HHI_GCLK_AO)
+#define GCLK_MASK_AHB_BUS (1<<2)
+
+#define GCLK_IDX_AO_REGS 131
+#define GCLK_NAME_AO_REGS "AO_REGS"
+#define GCLK_DEV_AO_REGS "CLKGATE_AO_REGS"
+#define GCLK_REG_AO_REGS (HHI_GCLK_AO)
+#define GCLK_MASK_AO_REGS (1<<3)
+
+#define GCLK_NAME_I2C_AO "I2C_AO"
+#define GCLK_REG_I2C_AO (HHI_GCLK_AO)
+#define GCLK_MASK_I2C_AO (1<<4)
+
+
+#define GCLK_IDX_CTS_ENCI 132
+#define GCLK_NAME_CTS_ENCI "CTS_ENCI"
+#define GCLK_DEV_CTS_ENCI "CLKGATE_CTS_ENCI"
+#define GCLK_REG_CTS_ENCI (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCI (1<<0)
+
+#define GCLK_IDX_CTS_ENCT 133
+#define GCLK_NAME_CTS_ENCT "CTS_ENCT"
+#define GCLK_DEV_CTS_ENCT "CLKGATE_CTS_ENCT"
+#define GCLK_REG_CTS_ENCT (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCT (1<<1)
+
+#define GCLK_IDX_CTS_ENCP 134
+#define GCLK_NAME_CTS_ENCP "CTS_ENCP"
+#define GCLK_DEV_CTS_ENCP "CLKGATE_CTS_ENCP"
+#define GCLK_REG_CTS_ENCP (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCP (1<<2)
+
+#define GCLK_IDX_CTS_ENCL 135
+#define GCLK_NAME_CTS_ENCL "CTS_ENCL"
+#define GCLK_DEV_CTS_ENCL "CLKGATE_CTS_ENCL"
+#define GCLK_REG_CTS_ENCL (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCL (1<<3)
+
+#define GCLK_IDX_CTS_VDAC 136
+#define GCLK_NAME_CTS_VDAC "CTS_VDAC"
+#define GCLK_DEV_CTS_VDAC "CLKGATE_CTS_VDAC"
+#define GCLK_REG_CTS_VDAC (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_VDAC (1<<4)
+
+#define GCLK_IDX_CTS_HDMI_TX_PIXEL 137
+#define GCLK_NAME_CTS_HDMI_TX_PIXEL "CTS_HDMI_TX_PIXEL"
+#define GCLK_DEV_CTS_HDMI_TX_PIXEL "CLKGATE_CTS_HDMI_TX_PIXEL"
+#define GCLK_REG_CTS_HDMI_TX_PIXEL (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_HDMI_TX_PIXEL (1<<5)
+
+#define GCLK_IDX_AUD 138
+#define GCLK_NAME_AUD "AUD"
+#define GCLK_DEV_AUD "CLKGATE_AUD"
+#define GCLK_REG_AUD (HHI_AUD_CLK_CNTL)
+#define GCLK_MASK_AUD (1<<23)
+
+
+#define GCLK_IDX_AUD2 138
+#define GCLK_NAME_AUD2 "AUD2"
+#define GCLK_DEV_AUD2 "CLKGATE_AUD2"
+#define GCLK_REG_AUD2 (HHI_AUD_CLK_CNTL)
+#define GCLK_MASK_AUD2 (1<<8)
+
+
+#define GCLK_NAME_AUD_CLK_2 "AUD_CLK_2"
+#define GCLK_REG_AUD_CLK_2 (HHI_AUD_CLK_CNTL2)
+#define GCLK_MASK_AUD_CLK_2 (1<<8)
+
+#define GCLK_IDX_AUD_CLK_3 138
+#define GCLK_NAME_AUD_CLK_3 "AUD_CLK"
+#define GCLK_DEV_AUD_CLK_3 "CLKGATE_AUD_CLK"
+#define GCLK_REG_AUD_CLK_3 (HHI_AUD_CLK_CNTL3)
+#define GCLK_MASK_AUD_CLK_3 (1<<16)
+
+#define GCLK_IDX_LCD_AN_PHY2 139
+#define GCLK_NAME_LCD_AN_PHY2 "LCD_AN_PHY2"
+#define GCLK_DEV_LCD_AN_PHY2 "CLKGATE_LCD_AN_PHY2"
+#define GCLK_REG_LCD_AN_PHY2 (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_LCD_AN_PHY2 (1<<7)
+
+#define GCLK_IDX_LCD_AN_PHY3 140
+#define GCLK_NAME_LCD_AN_PHY3 "LCD_AN_PHY3"
+#define GCLK_DEV_LCD_AN_PHY3 "CLKGATE_LCD_AN_PHY3"
+#define GCLK_REG_LCD_AN_PHY3 (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_LCD_AN_PHY3 (1<<6)
+
+#define GCLK_NAME_ATV_DEMO_VDAC "ATV_DEMO_VDAC"
+#define GCLK_REG_ATV_DEMO_VDAC (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_ATV_DEMO_VDAC (1<<8)
+
+#define GCLK_IDX_HDMI_PLL_CNTL 142
+#define GCLK_NAME_HDMI_PLL_CNTL "HDMI_PLL_CNTL"
+#define GCLK_DEV_HDMI_PLL_CNTL "GATE_HDMI_PLL_CNTL"
+#define GCLK_REG_HDMI_PLL_CNTL (HHI_HDMI_PLL_CNTL)
+#define GCLK_MASK_HDMI_PLL_CNTL (1<<30)
+
+#define GCLK_NAME_HDMITX_CLK "HDMITX_CLK"
+#define GCLK_REG_HDMITX_CLK (HHI_HDMI_CLK_CNTL)
+#define GCLK_MASK_HDMITX_CLK (1<<8)
+
+
+#define GCLK_NAME_HDMITX_CLK "HDMITX_CLK"
+#define GCLK_REG_HDMITX_CLK (HHI_HDMI_CLK_CNTL)
+#define GCLK_MASK_HDMITX_CLK (1<<8)
+
+#define GCLK_IDX_VDEC_CLK_1 144
+#define GCLK_NAME_VDEC_CLK_1 "VDEC_CLK_1"
+#define GCLK_DEV_VDEC_CLK_1 "CLKGATE_VDEC_CLK_1"
+#define GCLK_REG_VDEC_CLK_1 (HHI_VDEC_CLK_CNTL)
+#define GCLK_MASK_VDEC_CLK_1 (1<<8)
+
+#define GCLK_NAME_VDEC_CLK_2 "VDEC_CLK_2"
+#define GCLK_REG_VDEC_CLK_2 (HHI_VDEC3_CLK_CNTL)
+#define GCLK_MASK_VDEC_CLK_2 (1<<8)
+
+#define GCLK_NAME_VDEC2_CLK_1 "VDEC2_CLK_1"
+#define GCLK_REG_VDEC2_CLK_1 (HHI_VDEC2_CLK_CNTL)
+#define GCLK_MASK_VDEC2_CLK_1 (1<<8)
+
+#define GCLK_NAME_VDEC2_CLK_2 "VDEC2_CLK_2"
+#define GCLK_REG_VDEC2_CLK_2 (HHI_VDEC4_CLK_CNTL)
+#define GCLK_MASK_VDEC2_CLK_2 (1<<8)
+
+#define GCLK_IDX_HCODEC_CLK_1 145
+#define GCLK_NAME_HCODEC_CLK_1 "HCODEC_CLK"
+#define GCLK_DEV_HCODEC_CLK_1 "CLKGATE_HCODEC_CLK"
+#define GCLK_REG_HCODEC_CLK_1 (HHI_VDEC_CLK_CNTL)
+#define GCLK_MASK_HCODEC_CLK_1 (1<<24)
+
+#define GCLK_NAME_HCODEC_CLK_2 "HCODEC_CLK_2"
+#define GCLK_REG_HCODEC_CLK_2 (HHI_VDEC3_CLK_CNTL)
+#define GCLK_MASK_HCODEC_CLK_2 (1<<24)
+
+#define GCLK_NAME_HEVC_CLK_1 "HCODEC_CLK_1"
+#define GCLK_REG_HEVC_CLK_1 (HHI_VDEC2_CLK_CNTL)
+#define GCLK_MASK_HEVC_CLK_1 (1<<24)
+
+#define GCLK_NAME_HEVC_CLK_2 "HEVC_CLK_2"
+#define GCLK_REG_HEVC_CLK_2 (HHI_VDEC4_CLK_CNTL)
+#define GCLK_MASK_HEVC_CLK_2 (1<<24)
+
+#define GCLK_IDX_GEN_CLK 146
+#define GCLK_NAME_GEN_CLK "GEN_CLK"
+#define GCLK_DEV_GEN_CLK "CLKGATE_HCODEC_CLK"
+#define GCLK_REG_GEN_CLK (HHI_GEN_CLK_CNTL)
+#define GCLK_MASK_GEN_CLK (1<<11)
+
+#define GCLK_NAME_VPU_CLK_1 "VPU_CLK_1"
+#define GCLK_REG_VPU_CLK_1 (HHI_VPU_CLK_CNTL)
+#define GCLK_MASK_VPU_CLK_1 (1<<8)
+
+#define GCLK_NAME_VPU_CLK_2 "VPU_CLK_2"
+#define GCLK_REG_VPU_CLK_2 (HHI_VPU_CLK_CNTL)
+#define GCLK_MASK_VPU_CLK_2 (1<<24)
+
+
+#define GCLK_NAME_VPU_CLKB "VPU_CLKB"
+#define GCLK_REG_VPU_CLKB (HHI_VPU_CLKB_CNTL)
+#define GCLK_MASK_VPU_CLKB (1<<8)
+
+#define GCLK_NAME_VAPB_CLK_1 "VAPB_CLK_1"
+#define GCLK_REG_VAPB_CLK_1 (HHI_VAPBCLK_CNTL)
+#define GCLK_MASK_VAPB_CLK_1 (1<<8)
+
+#define GCLK_NAME_VAPB_CLK_2 "VAPB_CLK_2"
+#define GCLK_REG_VAPB_CLK_2 (HHI_VAPBCLK_CNTL)
+#define GCLK_MASK_VAPB_CLK_2 (1<<24)
+
+#define GCLK_NAME_MALI_CLK_1 "MALI_CLK_1"
+#define GCLK_REG_MALI_CLK_1 (HHI_MALI_CLK_CNTL)
+#define GCLK_MASK_MALI_CLK_1 (1<<8)
+
+#define GCLK_NAME_MALI_CLK_2 "MALI_CLK_2"
+#define GCLK_REG_MALI_CLK_2 (HHI_MALI_CLK_CNTL)
+#define GCLK_MASK_MALI_CLK_2 (1<<24)
+
+#define GCLK_NAME_PWM_A_CLK "PWM_A_CLK"
+#define GCLK_REG_PWM_A_CLK (CBUS_REG_ADDR(0x2156))
+#define GCLK_MASK_PWM_A_CLK (1<<15)
+
+#define GCLK_NAME_PWM_B_CLK "PWM_B_CLK"
+#define GCLK_REG_PWM_B_CLK (CBUS_REG_ADDR(0x2156))
+#define GCLK_MASK_PWM_B_CLK (1<<23)
+
+#define GCLK_NAME_PWM_C_CLK "PWM_C_CLK"
+#define GCLK_REG_PWM_C_CLK (CBUS_REG_ADDR(0x2196))
+#define GCLK_MASK_PWM_C_CLK (1<<15)
+
+#define GCLK_NAME_PWM_D_CLK "PWM_D_CLK"
+#define GCLK_REG_PWM_D_CLK (CBUS_REG_ADDR(0x2196))
+#define GCLK_MASK_PWM_D_CLK (1<<23)
+
+#define GCLK_NAME_PWM_E_CLK "PWM_E_CLK"
+#define GCLK_REG_PWM_E_CLK (CBUS_REG_ADDR(0x21b2))
+#define GCLK_MASK_PWM_E_CLK (1<<15)
+
+#define GCLK_NAME_PWM_F_CLK "PWM_D_CLK"
+#define GCLK_REG_PWM_F_CLK (CBUS_REG_ADDR(0x21b2))
+#define GCLK_MASK_PWM_F_CLK (1<<23)
+
+#define GCLK_NAME_VDIN_MEAS_CLK "VDIN_MEAS_CLK"
+#define GCLK_REG_VDIN_MEAS_CLK (HHI_VDIN_MEAS_CLK_CNTL)
+#define GCLK_MASK_VDIN_MEAS_CLK (1<<8)
+
+#define GCLK_NAME_MSR_CLK "MSR_CLK"
+#define GCLK_REG_MSR_CLK (CBUS_REG_ADDR(0x21d7))
+#define GCLK_MASK_MSR_CLK (1<<19)
+
+#define GCLK_NAME_MSR_HS_CLK "MSR_HS_CLK"
+#define GCLK_REG_MSR_HS_CLK (CBUS_REG_ADDR(0x21d9))
+#define GCLK_MASK_MSR_HS_CLK (1<<28)
+
+#define GCLK_NAME_32K_CLK "32K_CLK"
+#define GCLK_REG_32K_CLK (HHI_32K_CLK_CNTL)
+#define GCLK_MASK_32K_CLK (1<<15)
+
+
+
+#define GCLK_IDX_MAX 200
+
+extern short GCLK_ref[GCLK_IDX_MAX];
+
+#define REGISTER_CLK(_MOD) \
+static struct clk CLK_##_MOD = { \
+ .name = GCLK_NAME_##_MOD, \
+ .clock_index = GCLK_IDX_##_MOD, \
+ .clock_gate_reg_adr = GCLK_REG_##_MOD, \
+ .clock_gate_reg_mask = GCLK_MASK_##_MOD, \
+}
+
+#define CLK_LOOKUP_ITEM(_MOD) \
+ { \
+ .dev_id = GCLK_DEV_##_MOD, \
+ .con_id = GCLK_NAME_##_MOD, \
+ .clk = &CLK_##_MOD, \
+ }
+
+
+
+/**********************/
+/* internal audio dac control */
+#define ADAC_RESET (0x5000+0x00*4)
+#define ADAC_LATCH (0x5000+0x01*4)
+#define ADAC_POWER_CTRL_REG1 (0x5000+0x10*4)
+#define ADAC_POWER_CTRL_REG2 (0x5000+0x11*4)
+
+int audio_internal_dac_disable(void);
+
+/* video dac control */
+int video_dac_enable(unsigned char enable_mask);
+
+int video_dac_disable(void);
+
+
+#endif
diff --git a/arch/arm/mach-meson/a1/sdio.c b/arch/arm/mach-meson/a1/sdio.c
new file mode 100644
index 0000000..14ec635
--- /dev/null
+++ b/arch/arm/mach-meson/a1/sdio.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <asm/arch/io.h>
+#include <asm/arch/cpu_sdio.h>
+#include <asm/arch/secure_apb.h>
+#include <amlogic/cpu_id.h>
+#include <common.h>
+
+void cpu_sd_emmc_pwr_prepare(unsigned port)
+{
+}
+int cpu_sd_emmc_init(unsigned port)
+{
+ return 0;
+}
+
+/* return:
+ 0: insert
+ 1: not insert
+ */
+__weak int sd_emmc_detect(unsigned port)
+{
+ int ret = 0;
+
+ return ret;
+}
+
+
diff --git a/arch/arm/mach-meson/a1/timer.c b/arch/arm/mach-meson/a1/timer.c
new file mode 100644
index 0000000..8c16210
--- /dev/null
+++ b/arch/arm/mach-meson/a1/timer.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timer.h>
+#include <asm/types.h>
+
+uint32_t get_time(void)
+{
+ return readl(SYSCTRL_TIMERE);
+}
+
+void _udelay(unsigned int us)
+{
+#ifndef CONFIG_PXP_EMULATOR
+ unsigned int t0 = get_time();
+
+ while (get_time() - t0 <= us)
+ ;
+#endif
+}
diff --git a/arch/arm/mach-meson/a1/tsensor.c b/arch/arm/mach-meson/a1/tsensor.c
new file mode 100644
index 0000000..d707a78
--- /dev/null
+++ b/arch/arm/mach-meson/a1/tsensor.c
@@ -0,0 +1,268 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <command.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/mailbox.h>
+#include <asm/arch/tsensor.h>
+#include <asm/arch/bl31_apis.h>
+
+int tsensor_tz_calibration(unsigned int type, unsigned int data)
+{
+ int ret;
+
+ register long x0 asm("x0") = TSENSOR_CALI_SET;
+ register long x1 asm("x1") = type;
+ register long x2 asm("x2") = data;
+ register long x3 asm("x3") = 0;
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+ } while (0);
+ ret = x0;
+
+ if (!ret)
+ return -1;
+ else
+ return 0;
+}
+
+int r1p1_codetotemp(unsigned long value, unsigned int u_efuse)
+{
+ int64_t temp;
+
+ temp = (value * ts_m) * (1 << 16) / (100 * (1 << 16) + ts_n * value);
+ if (u_efuse & 0x8000) {
+ temp = ((temp - (u_efuse & 0x7fff)) * ts_a / (1 << 16) - ts_b) / 10;
+ } else {
+ temp = ((temp + (u_efuse & 0x7fff)) * ts_a / (1 << 16) - ts_b) / 10;
+ }
+ return temp;
+}
+
+int r1p1_temp_read(int type)
+{
+ unsigned int ret, u_efuse;
+ unsigned int value_ts, value_all_ts;
+ int tmp = -1;
+ int i, cnt;
+ char buf[2];
+
+ switch (type) {
+ case 1:
+ /*enable thermal1*/
+ writel(T_CONTROL_DATA, TS_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKTREE_TS_CLK_CTRL);
+ ret = readl(SYSCTRL_SEC_STATUS_REG13);/*thermal1 cali data in reg CFG10*/
+ mdelay(5);
+ buf[0] = (ret) & 0xff;
+ buf[1] = (ret >> 8) & 0xff;
+ u_efuse = buf[1];
+ u_efuse = (u_efuse << 8) | buf[0];
+ value_ts = 0;
+ value_all_ts = 0;
+ cnt = 0;
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_STAT0) & 0xffff;
+ }
+ for (i = 0; i < T_READ_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_STAT0) & 0xffff;
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ if (cnt) {
+ value_ts = value_all_ts / cnt;
+ } else {
+ value_ts = 0;
+ printf("tsensor read temp cnt is zero");
+ }
+ printf("tsensor avg: 0x%x, u_efuse: 0x%x\n", value_ts, u_efuse);
+ if (value_ts == 0) {
+ printf("tsensor read temp is zero\n");
+ return -1;
+ }
+ tmp = r1p1_codetotemp(value_ts, u_efuse);
+ printf("temp1: %d\n", tmp);
+ break;
+ default:
+ printf("r1p1 tsensor trim type not support\n");
+ return -1;
+ }
+ return tmp;
+}
+
+unsigned int r1p1_temptocode(unsigned long value, int tempbase)
+{
+ unsigned long tmp1, tmp2, u_efuse, signbit;
+
+ printf("a b m n: %d, %d, %d, %d\n", ts_a, ts_b, ts_m, ts_n);
+ tmp1 = ((tempbase * 10 + ts_b) * (1 << 16)) / ts_a; /*ideal u*/
+ printf("%s : tmp1: 0x%lx\n", __func__, tmp1);
+ tmp2 = (ts_m * value * (1 << 16)) / ((1 << 16) * 100 + ts_n * value);
+ printf("%s : tmp2: 0x%lx\n", __func__, tmp2);
+ signbit = ((tmp1 > tmp2) ? 0 : 1);
+ u_efuse = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
+ u_efuse = (signbit << 15) | u_efuse;
+ return u_efuse;
+}
+
+int r1p1_temp_trim(int tempbase, int tempver, int type)
+{
+ unsigned int u_efuse, index_ts, index_ver;
+ unsigned int value_ts, value_all_ts;
+ int i, cnt;
+
+ printf("r1p1 temp trim type: 0x%x\n", type);
+ switch (type) {
+ case 0:
+ index_ver = 5;
+ if (tsensor_tz_calibration(index_ver, tempver) < 0)
+ printf("version tsensor thermal_calibration send error\n");
+ break;
+ case 1:
+ value_ts = 0;
+ value_all_ts = 0;
+ index_ts = 6;
+ cnt = 0;
+ /*enable thermal1*/
+ writel(T_CONTROL_DATA, TS_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKTREE_TS_CLK_CTRL);
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_STAT0) & 0xffff;
+ printf("tsensor read: 0x%x\n", value_ts);
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ value_ts = value_all_ts / cnt;
+ printf("tsensor avg: 0x%x\n", value_ts);
+ if (value_ts == 0) {
+ printf("tsensor read temp is zero\n");
+ return -1;
+ }
+ u_efuse = r1p1_temptocode(value_ts, tempbase);
+ printf("ts efuse:%d\n", u_efuse);
+ printf("ts efuse:0x%x, index: %d\n", u_efuse, index_ts);
+ if (tsensor_tz_calibration(index_ts, u_efuse) < 0) {
+ printf("tsensor thermal_calibration send error\n");
+ return -1;
+ }
+ break;
+ default:
+ printf("r1p1 tsensor trim type not support\n");
+ return -1;
+ break;
+ }
+ return 0;
+}
+
+int temp_read_entry(void)
+{
+ unsigned int ret, ver;
+
+ ret = readl(SYSCTRL_SEC_STATUS_REG13);
+ ver = (ret >> 24) & 0xff;
+ if (0 == (ver & T_VER_MASK)) {
+ printf("tsensor no trimmed: calidata:0x%x\n",
+ readl(SYSCTRL_SEC_STATUS_REG13));
+ return -1;
+ }
+ ret = (ver & 0xf) >> 2;
+ switch (ret) {
+ case 0x2:
+ printf("temp type no support\n");
+ break;
+ case 0x0:
+ printf("temp type no support\n");
+ break;
+ case 0x1:
+ r1p1_temp_read(1);
+ printf("read the thermal\n");
+ break;
+ case 0x3:
+ printf("temp type no support\n");
+ return -1;
+ break;
+ default:
+ printf("thermal version not support!!!Please check!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int temp_trim_entry(int tempbase, int tempver)
+{
+ unsigned int ret, ver;
+
+ ret = readl(SYSCTRL_SEC_STATUS_REG13);
+ ver = (ret >> 24) & 0xff;
+ if (ver & T_VER_MASK) {
+ printf("tsensor trimmed: cali data: 0x%x\n",
+ readl(SYSCTRL_SEC_STATUS_REG13));
+ return -1;
+ }
+
+ printf("tsensor input trim tempver, tempver:0x%x\n", tempver);
+ switch (tempver) {
+ case 0x84:
+ r1p1_temp_trim(tempbase, tempver, 1);
+ r1p1_temp_trim(tempbase, tempver, 0);
+ printf("triming the thermal by bbt-sw\n");
+ break;
+ case 0x85:
+ r1p1_temp_trim(tempbase, tempver, 1);
+ r1p1_temp_trim(tempbase, tempver, 0);
+ printf("triming the thermal by bbt-ops\n");
+ break;
+ case 0x87:
+ r1p1_temp_trim(tempbase, tempver, 1);
+ r1p1_temp_trim(tempbase, tempver, 0);
+ printf("triming the thermal by slt\n");
+ break;
+ default:
+ printf("thermal version not support!!!Please check!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int temp_cooling_entry(void)
+{
+#ifdef CONFIG_AML_TSENSOR_COOL
+ int temp;
+
+ while (1) {
+ temp = r1p1_temp_read(1);
+ if (temp <= CONFIG_HIGH_TEMP_COOL) {
+ printf("device cool done\n");
+ break;
+ }
+ mdelay(2000);
+ printf("warning: temp %d over %d, cooling\n", temp,
+ CONFIG_HIGH_TEMP_COOL);
+ }
+#endif
+ return 0;
+}
diff --git a/arch/arm/mach-meson/a1/usb.c b/arch/arm/mach-meson/a1/usb.c
new file mode 100644
index 0000000..c2ba3d7
--- /dev/null
+++ b/arch/arm/mach-meson/a1/usb.c
@@ -0,0 +1,403 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <power/regulator.h>
+#include <clk.h>
+#include <asm/arch/usb.h>
+#include <amlogic/cpu_id.h>
+
+#include <linux/compat.h>
+#include <linux/ioport.h>
+#include <asm-generic/gpio.h>
+
+#define U2_CTRL_SLEEP_SHIFT 24
+#define U2_HHI_MEM_PD_MASK 0x3
+#define U2_HHI_MEM_PD_SHIFT 0x0
+#define U2_CTRL_ISO_SHIFT 24
+#define PHY20_RESET_LEVEL_BIT 6
+#define USB_RESET_BIT 4
+
+#define USB2_PHY_PLL_OFFSET_40 (0x09400414)
+#define USB2_PHY_PLL_OFFSET_44 (0x927E0000)
+#define USB2_PHY_PLL_OFFSET_48 (0xac5f69e5)
+
+#define USB2_PHY_PLL_OFFSET_34 (0x78000)
+
+#define USB2_PHY_PLL_OFFSET_50 (0xfe18)
+#define USB2_PHY_PLL_OFFSET_54 (0x2a)
+
+#define TUNING_DISCONNECT_THRESHOLD 0x34
+
+#define P_AO_RTI_GEN_PWR_SLEEP0 0xfe007808
+#define P_AO_RTI_GEN_PWR_ISO0 0xfe007804
+#define P_HHI_MEM_PD_REG0 0xfe007850
+
+static struct phy usb_phys[2];
+
+int get_usbphy_baseinfo(struct phy *usb_phys)
+{
+ struct udevice *bus;
+ struct uclass *uc;
+ int ret, i;
+ int count;
+
+ if (usb_phys[0].dev && usb_phys[1].dev)
+ return 0;
+
+ ret = uclass_get(UCLASS_USB, &uc);
+ if (ret)
+ return ret;
+ uclass_foreach_dev(bus, uc) {
+ debug("bus->name=%s, bus->driver->name =%s\n",
+ bus->name, bus->driver->name);
+ count = dev_count_phandle_with_args(bus, "phys", "#phy-cells");
+ debug("usb phy count=%u\n", count);
+ if (count <= 0)
+ return count;
+ for (i = 0; i < count; i++) {
+ ret = generic_phy_get_by_index(bus, i, &usb_phys[i]);
+ if (ret && ret != -ENOENT) {
+ pr_err("Failed to get USB PHY%d for %s\n",
+ i, bus->name);
+ return ret;
+ }
+ ret = generic_phy_getinfo(&usb_phys[i]);
+ if (ret)
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static void usb_set_power_domain (void)
+{
+ writel((readl(P_AO_RTI_GEN_PWR_SLEEP0) & (~(0x1 << U2_CTRL_SLEEP_SHIFT))),
+ P_AO_RTI_GEN_PWR_SLEEP0);
+ writel((readl(P_AO_RTI_GEN_PWR_ISO0) & (~(0x1 << U2_CTRL_ISO_SHIFT))),
+ P_AO_RTI_GEN_PWR_ISO0);
+ writel((readl(P_HHI_MEM_PD_REG0)
+ & (~(U2_HHI_MEM_PD_MASK << U2_HHI_MEM_PD_SHIFT))), P_HHI_MEM_PD_REG0);
+
+ return;
+}
+
+static void usb_set_clock_freq(unsigned int clock_addr)
+{
+ unsigned int val = (1 << 8) | (1 << 9) | (0 << 0);
+ writel(val, (unsigned long)clock_addr);
+ return;
+}
+
+static void set_pll_Calibration_default(uint32_t phy2_pll_base)
+{
+ u32 tmp;
+
+ tmp = (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x8));
+ tmp &= 0xfff;
+ tmp |= (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10));
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10))
+ = tmp;
+}
+
+void usb_reset(unsigned int reset_addr, int bit){
+ *(volatile unsigned int *)(unsigned long)reset_addr = (1 << bit);
+}
+
+static void usb_enable_phy_pll (void)
+{
+ *(volatile uint32_t *)RESETCTRL_RESET1_LEVEL |= (1 << PHY20_RESET_LEVEL_BIT);
+}
+
+static void usb_disable_phy_pll (void)
+{
+ *(volatile uint32_t *)RESETCTRL_RESET1_LEVEL &= ~(1 << PHY20_RESET_LEVEL_BIT);
+}
+
+void set_usb_pll(uint32_t phy2_pll_base)
+{
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))
+ = (USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET | USB_PHY2_ENABLE);
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44)) =
+ USB2_PHY_PLL_OFFSET_44;
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x48)) =
+ USB2_PHY_PLL_OFFSET_48;
+ udelay(100);
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x40))
+ = (((USB2_PHY_PLL_OFFSET_40) | (USB_PHY2_ENABLE))
+ & (~(USB_PHY2_RESET)));
+
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50))
+ = USB2_PHY_PLL_OFFSET_50;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x54))
+ = USB2_PHY_PLL_OFFSET_54;
+
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0xc)) =
+ TUNING_DISCONNECT_THRESHOLD;
+
+ set_pll_Calibration_default(phy2_pll_base);
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x34))
+ = USB2_PHY_PLL_OFFSET_34;
+
+ debug("tuning_disconnect_threshold=0x%x\n", TUNING_DISCONNECT_THRESHOLD);
+}
+
+int usb_save_phy_dev (unsigned int number, struct phy *phy)
+{
+ usb_phys[number].dev = phy->dev;
+ usb_phys[number].id = phy->id;
+ return 0;
+}
+
+int usb2_phy_init (struct phy *phy) {
+ struct phy_aml_usb2_priv *priv = dev_get_priv(phy->dev);
+ struct u2p_aml_regs *u2p_aml_reg;
+ u2p_r0_t dev_u2p_r0;
+ u2p_r1_t dev_u2p_r1;
+ int i,cnt;
+
+ usb_save_phy_dev(0, phy);
+ usb_enable_phy_pll();
+ usb_set_power_domain();
+
+ priv->clktree_usb_bus_ctrl_addr = dev_read_addr_index(phy->dev, 2 + priv->u2_port_num);
+ if (priv->clktree_usb_bus_ctrl_addr == FDT_ADDR_T_NONE) {
+ pr_err("Coun't get clktree_usb_bus_ctrl addr index %d\n", 2 + priv->u2_port_num);
+ } else {
+ usb_set_clock_freq(priv->clktree_usb_bus_ctrl_addr);
+ }
+
+ usb_reset(priv->reset_addr, USB_RESET_BIT);
+
+ udelay(500);
+ priv->usbphy_reset_bit[0] = PHY20_RESET_LEVEL_BIT;
+
+ for (i = 0; i < priv->u2_port_num; i++) {
+ u2p_aml_reg = (struct u2p_aml_regs *)((ulong)(priv->base_addr + i * PHY_REGISTER_SIZE));
+ dev_u2p_r0.d32 = u2p_aml_reg->u2p_r0;
+ dev_u2p_r0.b.host_device= 1;
+ dev_u2p_r0.b.POR= 0;
+ u2p_aml_reg->u2p_r0 = dev_u2p_r0.d32;
+ udelay(10);
+ /***USB PHY RESET : reset1 and reset1_level both need set ***/
+ /***reset1: usb_reset ***/
+ /***reset1_level: usb_enable_phy_pll ***/
+ usb_reset(priv->reset_addr, priv->usbphy_reset_bit[i]);
+ udelay(50);
+
+ /* wait for phy ready */
+ dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
+ cnt = 0;
+ while (dev_u2p_r1.b.phy_rdy != 1) {
+ dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
+ /*we wait phy ready max 1ms, common is 100us*/
+ if (cnt > 200)
+ break;
+ else {
+ cnt++;
+ udelay(5);
+ }
+ }
+ }
+
+ for (i = 0; i < priv->u2_port_num; i++) {
+ debug("------set usb pll\n");
+ set_usb_pll(priv->usb_phy2_pll_base_addr[i]);
+ }
+ return 0;
+
+}
+
+int usb2_phy_tuning(uint32_t phy2_pll_base, int port)
+{
+ return 0;
+}
+
+/**************************************************************/
+/* device mode config */
+/**************************************************************/
+unsigned int usb_get_dwc_a_base_addr(void)
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ int ret;
+
+ if (!usb_phys[0].dev) {
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ return usb2_priv->dwc2_a_addr;
+}
+unsigned int usb_get_device_mode_phy_base(void)
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ int ret;
+
+ if (!usb_phys[0].dev) {
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ return usb2_priv->usb_phy2_pll_base_addr[0];
+}
+
+void usb_phy_tuning_reset(void)
+{
+ return;
+}
+
+void usb_device_mode_init(void){
+ u2p_r0_t dev_u2p_r0;
+ u2p_r1_t dev_u2p_r1;
+
+ usb_r0_t dev_usb_r0;
+ usb_r4_t dev_usb_r4;
+ int cnt, ret;
+ u2p_aml_regs_t * u2p_aml_regs;
+ usb_aml_regs_t *usb_aml_regs;
+ struct phy_aml_usb2_priv *usb2_priv;
+ struct phy_aml_usb3_priv *usb3_priv;
+ unsigned int phy_base_addr, reset_addr;
+
+ usb_enable_phy_pll();
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return;
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ usb3_priv = dev_get_priv(usb_phys[1].dev);
+ if (!usb2_priv || !usb3_priv) {
+ printf("get usb phy address from dts failed\n");
+ return;
+ }
+
+ u2p_aml_regs = (u2p_aml_regs_t * )(ulong)usb2_priv->base_addr;
+ usb_aml_regs = (usb_aml_regs_t * )(ulong)usb3_priv->base_addr;
+ phy_base_addr = usb2_priv->usb_phy2_pll_base_addr[0];
+ reset_addr = usb2_priv->reset_addr;
+
+ usb_set_power_domain();
+ usb_set_clock_freq(CLKTREE_USB_BUSCLK_CTRL);
+
+ printf("PHY2=0x%08x\n", usb2_priv->base_addr);
+ if ((*(volatile uint32_t *)((ulong)(phy_base_addr + 0x38))) != 0) {
+ usb_phy_tuning_reset();
+ mdelay(150);
+ }
+
+ //step 1: usb controller reset
+ usb_reset(reset_addr, USB_RESET_BIT);
+
+ // step 3: enable usb INT internal USB
+ dev_usb_r0.d32 = usb_aml_regs->usb_r0;
+ dev_usb_r0.b.u2d_ss_scaledown_mode = 0;
+ dev_usb_r0.b.u2d_act = 1;
+ usb_aml_regs->usb_r0 = dev_usb_r0.d32;
+
+ // step 4: disable usb phy sleep
+ dev_usb_r4.d32 = usb_aml_regs->usb_r4;
+ dev_usb_r4.b.p21_SLEEPM0 = 1;
+ usb_aml_regs->usb_r4 = dev_usb_r4.d32;
+
+ // step 5: config phy21 device mode
+ dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0;
+ dev_u2p_r0.b.host_device= 0;
+ dev_u2p_r0.b.POR= 0;
+ u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32;
+
+ udelay(10);
+ //step 6: phy21 reset
+ usb_reset(reset_addr, PHY20_RESET_LEVEL_BIT);
+ udelay(50);
+
+ // step 6: wait for phy ready
+ dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
+ cnt = 0;
+ while ((dev_u2p_r1.d32 & 0x00000001) != 1) {
+ dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
+ if (cnt > 200)
+ break;
+ else {
+ cnt++;
+ udelay(5);
+ }
+ }
+
+ set_usb_pll(phy_base_addr);
+ //--------------------------------------------------
+
+ // ------------- usb phy21 initinal end ----------
+
+ //--------------------------------------------------
+
+}
+
+static void usb_disable_phy(uint32_t phy2_pll_base)
+{
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))=
+ ((USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET) & (~USB_PHY2_ENABLE));
+ udelay(5);
+}
+
+static void usb_print_usb_baseinfo
+ (struct phy_aml_usb2_priv *usb2_priv, struct phy_aml_usb3_priv *usb3_priv)
+{
+ if (usb3_priv) {
+ printf("priv->usb3 port num = %d, config addr=0x%08x\n",
+ usb3_priv->usb3_port_num, usb3_priv->base_addr);
+ }
+ if (usb2_priv) {
+ printf("usb2 phy: config addr = 0x%08x, reset addr=0x%08x\n",
+ usb2_priv->base_addr, usb2_priv->reset_addr);
+
+ printf("usb2 phy: portnum=%d, phy-addr1= 0x%08x, phy-addr2= 0x%08x\n",
+ usb2_priv->u2_port_num, usb2_priv->usb_phy2_pll_base_addr[0],
+ usb2_priv->usb_phy2_pll_base_addr[1]);
+ printf("dwc2_a base addr: 0x%08x\n", usb2_priv->dwc2_a_addr);
+ }
+}
+
+int usb_aml_detect_operation(int argc, char * const argv[])
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ struct phy_aml_usb3_priv *usb3_priv;
+ int ret;
+
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ usb3_priv = dev_get_priv(usb_phys[1].dev);
+
+ if (argc >= 2) {
+ if (strncmp(argv[1], "disable", 7) == 0) {
+ usb_disable_phy_pll();
+ usb_disable_phy(usb2_priv->usb_phy2_pll_base_addr[0]);
+ printf("disable USB phy\n");
+ return 0;
+ }
+
+ if (strncmp(argv[1], "info", 4) == 0) {
+ usb_print_usb_baseinfo(usb2_priv, usb3_priv);
+ return 0;
+ }
+ }
+ return CMD_RET_USAGE;
+}
diff --git a/arch/arm/mach-meson/anti-rollback.c b/arch/arm/mach-meson/anti-rollback.c
new file mode 100644
index 0000000..7a84d52
--- /dev/null
+++ b/arch/arm/mach-meson/anti-rollback.c
@@ -0,0 +1,171 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/bl31_apis.h>
+#include "anti-rollback.h"
+
+#define FUNCID_ANTIROLLBACK_VERSION_CHECK 0xb2000010
+
+#define FUNCID_AVB_VERSION_SET 0xb2000011
+#define FUNCID_AVB_VERSION_GET 0xb2000012
+#define FUNCID_AVB_LOCK_STATE_GET 0xb2000013
+#define FUNCID_AVB_LOCK 0xb2000014
+#define FUNCID_AVB_UNLOCK 0xb2000015
+
+#define IMAGE_VERSION_TYPE_BOOTLOADER 0x001
+#define IMAGE_VERSION_TYPE_RECOVERY 0x002
+#define IMAGE_VERSION_TYPE_BOOT 0x003
+
+#define KERNEL_TYPE_UNKNOWN 0x00
+#define KERNEL_TYPE_BOOT 0x01
+#define KERNEL_TYPE_RECOVERY 0x02
+
+static uint32_t antirollback_image_version_check(uint32_t type,
+ uint32_t version)
+{
+ register uint32_t x0 asm("x0") = FUNCID_ANTIROLLBACK_VERSION_CHECK;
+ register uint32_t x1 asm("x1") = type;
+ register uint32_t x2 asm("x2") = version;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2));
+ } while (0);
+
+ return x0;
+}
+
+bool check_antirollback(uint32_t kernel_version)
+{
+ bool ret = true;
+ uint32_t type = (kernel_version >> 24);
+ uint32_t version = ((kernel_version << 8) >> 8);
+ if (KERNEL_TYPE_BOOT == type) {
+ if (antirollback_image_version_check(IMAGE_VERSION_TYPE_BOOT,
+ version) != 0) {
+ printf("checking boot.img version failed\n");
+ ret = false;
+ }
+ }
+ else if (KERNEL_TYPE_RECOVERY == type) {
+ if (antirollback_image_version_check(
+ IMAGE_VERSION_TYPE_RECOVERY,
+ version) != 0) {
+ printf("checking recovery.img version failed\n");
+ ret = false;
+ }
+ }
+ else {
+ printf("the kernel type is unknown\n");
+ ret = false;
+ }
+
+ if (ret)
+ printf("checking version success\n");
+
+ return ret;
+}
+
+bool set_avb_antirollback(uint32_t index, uint32_t version)
+{
+ register uint32_t x0 asm("x0") = FUNCID_AVB_VERSION_SET;
+ register uint32_t x1 asm("x1") = index;
+ register uint32_t x2 asm("x2") = version;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2));
+ } while (0);
+
+ return 0 == x0;
+}
+
+bool get_avb_antirollback(uint32_t index, uint32_t* version)
+{
+ register uint32_t x0 asm("x0") = FUNCID_AVB_VERSION_GET;
+ register uint32_t x1 asm("x1") = index;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x0")
+ __asmeq("%3", "x1")
+ "smc #0\n"
+ : "=r"(x0), "=r"(x1)
+ : "r"(x0), "r"(x1));
+ } while (0);
+
+ if (0 == x0)
+ *version = x1;
+
+ return 0 == x0;
+}
+
+bool get_avb_lock_state(uint32_t* lock_state)
+{
+ register uint32_t x0 asm("x0") = FUNCID_AVB_LOCK_STATE_GET;
+ register uint32_t x1 asm("x1") = 0;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x0")
+ "smc #0\n"
+ : "=r"(x0), "=r"(x1)
+ : "r"(x0));
+ } while (0);
+
+ if (0 == x0)
+ *lock_state = x1;
+
+ return 0 == x0;
+}
+
+bool avb_lock(void)
+{
+ register uint32_t x0 asm("x0") = FUNCID_AVB_LOCK;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0));
+ } while (0);
+
+ return 0 == x0;
+}
+
+bool avb_unlock(void)
+{
+ register uint32_t x0 asm("x0") = FUNCID_AVB_UNLOCK;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0));
+ } while (0);
+
+ return 0 == x0;
+}
diff --git a/arch/arm/mach-meson/c1/Makefile b/arch/arm/mach-meson/c1/Makefile
new file mode 100644
index 0000000..a7b0aae
--- /dev/null
+++ b/arch/arm/mach-meson/c1/Makefile
@@ -0,0 +1,14 @@
+
+obj-y := sdio.o pinctrl_init.o
+obj-y += bl31_apis.o
+obj-y += cpu_reset.o
+obj-y += timer.o
+#obj-y += mailbox.o
+#obj-y += gate_init.o
+#obj-y += power_cal.o
+obj-$(CONFIG_CMD_PLLTEST) += pll.o
+obj-$(CONFIG_CMD_AML_MTEST) += core.o
+obj-$(CONFIG_AML_HDMITX) += hdmitx.o
+obj-y += usb.o
+obj-$(CONFIG_AML_TSENSOR) += tsensor.o
+obj-$(CONFIG_AML_OSCRING) += oscring.o
diff --git a/arch/arm/mach-meson/c1/bl31_apis.c b/arch/arm/mach-meson/c1/bl31_apis.c
new file mode 100644
index 0000000..9cc103a
--- /dev/null
+++ b/arch/arm/mach-meson/c1/bl31_apis.c
@@ -0,0 +1,498 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ * Trustzone API
+ */
+
+#include <asm/arch/io.h>
+#include <asm/arch/efuse.h>
+#include <asm/cache.h>
+#include <asm/arch/bl31_apis.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+
+static long sharemem_input_base;
+static long sharemem_output_base;
+
+long get_sharemem_info(unsigned long function_id)
+{
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ : "+r" (function_id));
+
+ return function_id;
+}
+
+int32_t set_boot_params(const keymaster_boot_params *boot_params)
+{
+ /* Fake function for the reason that set_boot_params is not
+ * supported for this platform */
+ return -1;
+}
+
+#ifdef CONFIG_EFUSE
+int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg)
+{
+ int ret;
+ unsigned cmd, offset, size;
+ unsigned long *retcnt = (unsigned long *)(arg->retcnt_phy);
+
+ if (!sharemem_input_base)
+ sharemem_input_base =
+ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE);
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ if (arg->cmd == EFUSE_HAL_API_READ)
+ cmd = EFUSE_READ;
+ else if (arg->cmd == EFUSE_HAL_API_WRITE)
+ cmd = EFUSE_WRITE;
+ else
+ cmd = EFUSE_WRITE_PATTERN;
+ offset = arg->offset;
+ size = arg->size;
+
+ if (arg->cmd == EFUSE_HAL_API_WRITE)
+ memcpy((void *)sharemem_input_base,
+ (const void *)arg->buffer_phy, size);
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = cmd;
+ register uint64_t x1 asm("x1") = offset;
+ register uint64_t x2 asm("x2") = size;
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2));
+ } while (0);
+ ret = x0;
+ *retcnt = x0;
+
+ if ((arg->cmd == EFUSE_HAL_API_READ) && (ret != 0))
+ memcpy((void *)arg->buffer_phy,
+ (const void *)sharemem_output_base, ret);
+
+ if (!ret)
+ return -1;
+ else
+ return 0;
+}
+
+int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg)
+{
+ int32_t ret;
+ unsigned cmd = 0;
+
+ if (arg->cmd == EFUSE_HAL_API_USER_MAX)
+ cmd = EFUSE_USER_MAX;
+
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = cmd;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0));
+ } while (0);
+ ret = x0;
+
+ if (!ret)
+ return -1;
+ else
+ return ret;
+}
+
+ssize_t meson_trustzone_efuse_writepattern(const char *buf, size_t count)
+{
+ struct efuse_hal_api_arg arg;
+ unsigned long retcnt;
+
+ if (count != EFUSE_BYTES)
+ return 0; /* Past EOF */
+
+ arg.cmd = EFUSE_HAL_API_WRITE_PATTERN;
+ arg.offset = 0;
+ arg.size = count;
+ arg.buffer_phy = (unsigned long)buf;
+ arg.retcnt_phy = (unsigned long)&retcnt;
+ int ret;
+ ret = meson_trustzone_efuse(&arg);
+ return ret;
+}
+#endif
+
+uint64_t meson_trustzone_efuse_check(unsigned char *addr)
+{
+ uint64_t ret = 0;
+ struct sram_hal_api_arg arg = {};
+
+ arg.cmd = SRAM_HAL_API_CHECK_EFUSE;
+ arg.req_len = 0x1000000;
+ arg.res_len = 0;
+ arg.req_phy_addr = (unsigned long)addr;
+ arg.res_phy_addr = (unsigned long)NULL;
+
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = CALL_TRUSTZONE_HAL_API;
+ register uint64_t x1 asm("x1") = TRUSTZONE_HAL_API_SRAM;
+ register uint64_t x2 asm("x2") = (unsigned long)(&arg);
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2));
+ } while (0);
+
+ ret = x0;
+
+ return ret;
+}
+
+void debug_efuse_cmd(unsigned long cmd)
+{
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ : : "r" (cmd));
+}
+
+void bl31_debug_efuse_write_pattern(const char *buf)
+{
+ if (!sharemem_input_base)
+ sharemem_input_base =
+ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE);
+ memcpy((void *)sharemem_input_base, (const void *)buf, 512);
+
+ debug_efuse_cmd(DEBUG_EFUSE_WRITE_PATTERN);
+}
+
+void bl31_debug_efuse_read_pattern(char *buf)
+{
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+ debug_efuse_cmd(DEBUG_EFUSE_READ_PATTERN);
+
+ memcpy((void *)buf, (const void *)sharemem_output_base, 512);
+}
+
+void aml_set_jtag_state(unsigned state, unsigned select)
+{
+ uint64_t command;
+ if (state == JTAG_STATE_ON)
+ command = JTAG_ON;
+ else
+ command = JTAG_OFF;
+ asm __volatile__("" : : : "memory");
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : : "r" (command), "r"(select));
+}
+
+void wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value)
+{
+ register long x0 asm("x0") = 0x82000086;
+ register long x1 asm("x1") = cmd;
+ register long x2 asm("x2") = value;
+ register long x3 asm("x3") = 0;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+}
+
+unsigned aml_get_reboot_reason(void)
+{
+ unsigned reason;
+ uint64_t ret;
+
+ register uint64_t x0 asm("x0") = GET_REBOOT_REASON;
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ :"+r"(x0));
+ ret = x0;
+ reason = (unsigned)(ret&0xffffffff);
+ return reason;
+}
+
+void set_viu_probe_enable(void)
+{
+ register uint64_t x0 asm("x0") = VIU_PREOBE_EN;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ :"+r"(x0));
+}
+
+void power_set_dsp(unsigned int id, unsigned int powerflag)
+{
+ register long x0 asm("x0") = DSP_SEC_POWERSET;
+ register long x1 asm("x1") = id;
+ register long x2 asm("x2") = powerflag;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2));
+}
+
+void init_dsp(unsigned int id,unsigned int addr,unsigned int cfg0)
+{
+ register long x0 asm("x0") = START_HIFI4;
+ register long x1 asm("x1") = id;
+ register long x2 asm("x2") = addr;
+ register long x3 asm("x3") = cfg0;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+}
+
+
+unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2)
+{
+ register long x0 asm("x0") = function_id;
+ register long x1 asm("x1") = arg0;
+ register long x2 asm("x2") = arg1;
+ register long x3 asm("x3") = arg2;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+
+ return function_id;
+}
+
+void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2)
+{
+ register long x0 asm("x0") = function_id;
+ register long x1 asm("x1") = arg0;
+ register long x2 asm("x2") = arg1;
+ register long x3 asm("x3") = arg2;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+
+ return ;
+}
+
+unsigned long aml_sec_boot_check(unsigned long nType,
+ unsigned long pBuffer,
+ unsigned long nLength,
+ unsigned long nOption)
+{
+ uint64_t ret = 1;
+
+//#define AML_SECURE_LOG_TE
+
+#if defined(AML_SECURE_LOG_TE)
+ #define AML_GET_TE(a) do{a = *((volatile unsigned int*)0xc1109988);}while(0);
+ unsigned nT1,nT2,nT3;
+#else
+ #define AML_GET_TE(...)
+#endif
+
+ AML_GET_TE(nT1);
+
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = AML_DATA_PROCESS;
+ register uint64_t x1 asm("x1") = nType;
+ register uint64_t x2 asm("x2") = pBuffer;
+ register uint64_t x3 asm("x3") = nLength;
+ register uint64_t x4 asm("x4") = nOption;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ __asmeq("%4", "x3")
+ __asmeq("%5", "x4")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2),"r"(x3),"r"(x4));
+ } while (0);
+
+ ret = x0;
+
+ AML_GET_TE(nT2);;
+
+ flush_dcache_range((unsigned long )pBuffer, (unsigned long )pBuffer+nLength);
+
+ AML_GET_TE(nT3);
+
+#if defined(AML_SECURE_LOG_TE)
+ printf("aml log : dec use %d(us) , flush cache used %d(us)\n",
+ nT2 - nT1, nT3 - nT2);
+#endif
+
+ return ret;
+}
+
+void set_usb_boot_function(unsigned long command)
+{
+ register long x0 asm("x0") = SET_USB_BOOT_FUNC;
+ register long x1 asm("x1") = command;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+}
+
+void set_boot_first_timeout(uint64_t arg0)
+{
+ register long x0 asm("x0") = SET_BOOT_FIRST;
+ register long x1 asm("x1") = arg0;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+}
+void aml_system_off(void)
+{
+ /* TODO: Add poweroff capability */
+ aml_reboot(0x82000042, 1, 0, 0);
+ aml_reboot(0x84000008, 0, 0, 0);
+}
+
+int __get_chip_id(unsigned char *buff, unsigned int size)
+{
+ if (buff == NULL || size < 16)
+ return -1;
+
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ if (sharemem_output_base) {
+ register long x0 asm("x0") = GET_CHIP_ID;
+ register long x1 asm("x1") = 2;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+
+ if (x0 == 0) {
+ int version = *((unsigned int *)sharemem_output_base);
+
+ if (version == 2) {
+ memcpy(buff, (void *)sharemem_output_base + 4, 16);
+ }
+ else {
+ /**
+ * Legacy 12-byte chip ID read out, transform data
+ * to expected order format.
+ */
+ uint32_t chip_info = 0;//readl(P_AO_SEC_SD_CFG8);
+ uint8_t *ch;
+ int i;
+
+ ((uint32_t *)buff)[0] =
+ ((chip_info & 0xff000000) | // Family ID
+ ((chip_info << 8) & 0xff0000) | // Chip Revision
+ ((chip_info >> 8) & 0xff00)); // Package ID
+
+ ((uint32_t *)buff)[0] = htonl(((uint32_t *)buff)[0]);
+
+ /* Transform into expected order for display */
+ ch = (uint8_t *)(sharemem_output_base + 4);
+ for (i = 0; i < 12; i++)
+ buff[i + 4] = ch[11 - i];
+ }
+
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
+int bl31_get_cornerinfo(uint8_t *outbuf, int size)
+{
+ int buff_len = 0;
+
+ if (outbuf == NULL) {
+ printf("BL33: corner efuse info storebuf is NULL\n");
+ return -1;
+ }
+
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ if (sharemem_output_base) {
+ register long x0 asm("x0") = OSCRING_EFUSE_GET;
+ register long x1 asm("x1") = size;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+ } while(0);
+ buff_len = x0;
+ if (buff_len <= size) {
+ memcpy(outbuf, (void *)sharemem_output_base, buff_len);
+ return 0;
+ } else {
+ printf("BL33: corner efuse info buf len %d over storebuf size %d\n", buff_len, size);
+ return -1;
+ }
+ }
+ return -1;
+}
diff --git a/arch/arm/mach-meson/c1/core.c b/arch/arm/mach-meson/c1/core.c
new file mode 100644
index 0000000..8640828
--- /dev/null
+++ b/arch/arm/mach-meson/c1/core.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/types.h>
+#include <asm/arch/cpu.h>
+#include <common.h>
+
+const unsigned int core_map[] = {
+ 0x0,
+ 0x1,
+ 0x2,
+ 0x3,
+};
+
+int get_core_mpidr(unsigned int cpuid)
+{
+ unsigned int coremax = (unsigned int)(sizeof(core_map)/sizeof(unsigned int));
+
+ if (cpuid >= coremax)
+ return -1;
+ return core_map[cpuid];
+}
+
+int get_core_idx(unsigned int mpidr)
+{
+ unsigned int clusterid, cpuid;
+
+ cpuid = mpidr & 0xff;
+ clusterid = mpidr & 0xff00;
+
+ cpuid += (clusterid >> 6);
+
+ if (cpuid >= NR_CPUS)
+ return -1;
+
+ return cpuid;
+}
+
+int get_core_max(void)
+{
+ return (sizeof(core_map)/sizeof(unsigned int));
+}
diff --git a/arch/arm/mach-meson/c1/cpu_reset.c b/arch/arm/mach-meson/c1/cpu_reset.c
new file mode 100644
index 0000000..ca0a42d
--- /dev/null
+++ b/arch/arm/mach-meson/c1/cpu_reset.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/types.h>
+#include <asm/arch/romboot.h>
+#include <asm/arch/cpu_reset.h>
+#include <asm/arch/io.h>
+#include <asm/arch/timer.h>
+#include <dm.h>
+#include <wdt.h>
+
+/*
+ *GPIOE_0 VDDEE_PWM
+ *GPIOE_1 VDDCPU_PWM
+ * */
+void set_pwm_to_input(void)
+{
+ //hxbao, need fine tune
+ #if 0
+ unsigned int val;
+
+ val = readl(AO_RTI_PINMUX_REG1);
+ val &= ~(0xff << 16);
+ writel(val, AO_RTI_PINMUX_REG1);/* clear pinmux */
+ val = readl(AO_GPIO_O_EN_N);
+ val &= ~(0x3 << 16);
+ val |= 0x3 << 16;
+ writel(val, AO_GPIO_O_EN_N);/* set input mode */
+ val = readl(AO_RTI_PULL_UP_EN_REG);
+ val &= ~(0x3 << 16);
+ writel(val, AO_RTI_PULL_UP_EN_REG);/* disable pull up/down */
+ #endif
+}
+
+void reset_system(void)
+{
+ struct udevice *watchdog_devp;
+ int ret;
+
+ set_pwm_to_input();
+
+ _udelay(10000); //wait print
+
+ ret = uclass_get_device_by_name(UCLASS_WDT, "watchdog", &watchdog_devp);
+ if (ret < 0) {
+ printf("failed to reset system because can't get wdt device\n");
+ return;
+ }
+ wdt_start(watchdog_devp, 0, 0);
+ while (1);
+}
+
+/* uboot reset interface */
+void reset_cpu(unsigned long flag){
+ reset_system();
+}
diff --git a/arch/arm/mach-meson/c1/firmware/acs/Makefile b/arch/arm/mach-meson/c1/firmware/acs/Makefile
new file mode 100644
index 0000000..70d2d83
--- /dev/null
+++ b/arch/arm/mach-meson/c1/firmware/acs/Makefile
@@ -0,0 +1,431 @@
+#
+# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of ARM nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+#
+# Default values for build configurations
+#
+
+export CROSS_COMPILE=/opt/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-
+
+include $(buildsrc)/config.mk
+include $(buildtree)/include/autoconf.mk
+include $(buildtree)/.config
+
+# Build verbosity
+V := 0
+# Debug build
+BUILD_TYPE := ${BL2_BUILD_TYPE}
+# Build architecture
+ARCH := aarch64
+# Build platform
+#DEFAULT_PLAT := gx
+PLAT := ${SOC}
+export PLAT
+# SPD choice
+SPD := none
+# Base commit to perform code check on
+BASE_COMMIT := origin/master
+# NS timer register save and restore
+NS_TIMER_SWITCH := 0
+# By default, Bl1 acts as the reset handler, not BL31
+RESET_TO_BL31 := 0
+
+# Checkpatch ignores
+CHECK_IGNORE = --ignore COMPLEX_MACRO
+
+CHECKPATCH_ARGS = --no-tree --no-signoff ${CHECK_IGNORE}
+CHECKCODE_ARGS = --no-patch --no-tree --no-signoff ${CHECK_IGNORE}
+
+ifeq (${V},0)
+ Q=@
+ CHECKCODE_ARGS += --no-summary --terse
+else
+ Q=
+endif
+export Q
+
+ifeq (${GIT_VERSION},)
+ GIT_VERSION := $(shell git describe --abbrev=7 --dirty --always --tags)
+endif
+ifeq (${BUILDER},)
+ BUILDER := ${USER}@$(shell hostname)
+endif
+
+BL_COMMON_SOURCES := common/bl_common.c \
+ common/debug.c \
+ lib/aarch64/cache_helpers.S \
+ lib/aarch64/misc_helpers.S \
+ lib/aarch64/tlb_helpers.S \
+ lib/aarch64/xlat_helpers.c \
+ lib/stdlib/std.c \
+ lib/io_storage.c \
+ plat/common/aarch64/platform_helpers.S
+
+BUILD_BASE := $(buildtree)/firmware
+#BUILD_PLAT := ${BUILD_BASE}/${PLAT}
+BUILD_PLAT := $(buildtree)/board/${BOARDDIR}/firmware
+#BUILD_PLAT := $(buildtree)/${BOARDDIR}/firmware
+
+# Convenience function for adding build definitions
+# $(eval $(call add_define,FOO)) will have:
+# -DFOO if $(FOO) is empty; -DFOO=$(FOO) otherwise
+define add_define
+DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
+endef
+
+# Convenience function for verifying option has a boolean value
+# $(eval $(call assert_boolean,FOO)) will assert FOO is 0 or 1
+define assert_boolean
+$(and $(patsubst 0,,$(value $(1))),$(patsubst 1,,$(value $(1))),$(error $(1) must be boolean))
+endef
+
+ifeq (${PLAT},)
+ $(error "Error: Unknown platform. Please use PLAT=<platform name> to specify the platform.")
+endif
+
+all: msg_start
+
+msg_start:
+ @echo "Building ${BOARDDIR}/acs.bin"
+
+#include plat/${PLAT}/platform.mk
+#ifdef BL2_SOURCES
+NEED_BL2 := yes
+include acs.mk
+#endif
+
+# Include SPD Makefile if one has been specified
+ifneq (${SPD},none)
+ # We expect to locate an spd.mk under the specified SPD directory
+ SPD_MAKE := $(shell m="services/spd/${SPD}/${SPD}.mk"; [ -f "$$m" ] && echo "$$m")
+
+ ifeq (${SPD_MAKE},)
+ $(error Error: No services/spd/${SPD}/${SPD}.mk located)
+ endif
+ $(info Including ${SPD_MAKE})
+ include ${SPD_MAKE}
+
+ # If there's BL32 companion for the chosen SPD, and the SPD wants to build the
+ # BL2 from source, we expect that the SPD's Makefile would set NEED_BL32
+ # variable to "yes"
+endif
+
+.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool fip
+.SUFFIXES:
+
+INCLUDES += -Iinclude/bl2 \
+ -Iinclude/bl31 \
+ -Iinclude/common \
+ -Iinclude/drivers \
+ -Iinclude/drivers/arm \
+ -Iinclude/drivers/serial \
+ -Iinclude/lib \
+ -Iinclude/lib/aarch64 \
+ -Iinclude/plat/common \
+ -Iinclude/stdlib \
+ -Iinclude/stdlib/sys \
+ ${PLAT_INCLUDES} \
+ ${SPD_INCLUDES}
+
+# Process DEBUG flag
+$(eval $(call assert_boolean,DEBUG))
+$(eval $(call add_define,DEBUG))
+ifeq (${DEBUG},0)
+ $(eval $(call add_define,NDEBUG))
+else
+CFLAGS += -g
+ASFLAGS += -g -Wa,--gdwarf-2
+endif
+
+# Process NS_TIMER_SWITCH flag
+$(eval $(call assert_boolean,NS_TIMER_SWITCH))
+$(eval $(call add_define,NS_TIMER_SWITCH))
+
+# Process RESET_TO_BL31 flag
+$(eval $(call assert_boolean,RESET_TO_BL31))
+$(eval $(call add_define,RESET_TO_BL31))
+
+VPATH_LIST = $(buildsrc)/board/$(BOARDDIR)
+#VPATH_LIST = $(buildsrc)/$(BOARDDIR)
+VPATH_LIST:=$(VPATH_LIST:%=%/firmware/)
+
+vpath %.c $(VPATH_LIST)
+
+ASFLAGS += -nostdinc -ffreestanding -Wa,--fatal-warnings \
+ -mgeneral-regs-only -D__ASSEMBLY__ \
+ ${DEFINES} ${INCLUDES}
+CFLAGS += -nostdinc -pedantic -ffreestanding -Wall \
+ -Werror -mgeneral-regs-only -std=c99 -c -Os \
+ ${DEFINES} ${INCLUDES} $(VPATH_LIST:%=-I%)
+CFLAGS += -ffunction-sections -fdata-sections
+ASFLAGS += ${FIRMWARE_CPPFLAGS}
+CFLAGS += ${FIRMWARE_CPPFLAGS}
+CFLAGS += -Wno-unused
+
+LDFLAGS += --fatal-warnings -O1
+LDFLAGS += --gc-sections
+
+CC := ${CROSS_COMPILE}gcc
+CPP := ${CROSS_COMPILE}cpp
+AS := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OC := ${CROSS_COMPILE}objcopy
+OD := ${CROSS_COMPILE}objdump
+NM := ${CROSS_COMPILE}nm
+PP := ${CROSS_COMPILE}gcc -E ${CFLAGS}
+
+# Variables for use with Firmware Image Package
+FIPTOOLPATH ?= tools/fip_create
+FIPTOOL ?= ${FIPTOOLPATH}/fip_create
+fiptool: ${FIPTOOL}
+fip: ${BUILD_PLAT}/fip.bin
+
+locate-checkpatch:
+ifndef CHECKPATCH
+ $(error "Please set CHECKPATCH to point to the Linux checkpatch.pl file, eg: CHECKPATCH=../linux/script/checkpatch.pl")
+else
+ifeq (,$(wildcard ${CHECKPATCH}))
+ $(error "The file CHECKPATCH points to cannot be found, use eg: CHECKPATCH=../linux/script/checkpatch.pl")
+endif
+endif
+
+clean:
+ @echo " CLEAN"
+ ${Q}rm -rf ${BUILD_PLAT}
+ ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
+
+realclean distclean:
+ @echo " REALCLEAN"
+ ${Q}rm -rf ${BUILD_BASE}
+ ${Q}rm -f ${CURDIR}/cscope.*
+ ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
+
+checkcodebase: locate-checkpatch
+ @echo " CHECKING STYLE"
+ @if test -d .git ; then \
+ git ls-files | while read GIT_FILE ; do ${CHECKPATCH} ${CHECKCODE_ARGS} -f $$GIT_FILE ; done ; \
+ else \
+ find . -type f -not -iwholename "*.git*" -not -iwholename "*build*" -exec ${CHECKPATCH} ${CHECKCODE_ARGS} -f {} \; ; \
+ fi
+
+checkpatch: locate-checkpatch
+ @echo " CHECKING STYLE"
+ @git format-patch --stdout ${BASE_COMMIT} | ${CHECKPATCH} ${CHECKPATCH_ARGS} - || true
+
+${FIPTOOL}:
+ ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH}
+ @echo
+ @echo "Built $@ successfully"
+ @echo
+
+define match_goals
+$(strip $(foreach goal,$(1),$(filter $(goal),$(MAKECMDGOALS))))
+endef
+
+# List of rules that involve building things
+BUILD_TARGETS := all bl1 bl2 bl31 bl32 fip
+
+# Does the list of goals specified on the command line include a build target?
+ifneq ($(call match_goals,${BUILD_TARGETS}),)
+IS_ANYTHING_TO_BUILD := 1
+endif
+
+define MAKE_C
+
+$(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2))))
+$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ)))
+
+$(OBJ) : $(2)
+ @echo " CC $$<"
+ $$(Q)$$(CC) $$(CFLAGS) -c $$< -o $$@
+
+
+$(PREREQUISITES) : $(2)
+ @echo " DEPS $$@"
+ @mkdir -p $(1)
+ $$(Q)$$(CC) $$(CFLAGS) -M -MT $(OBJ) -MF $$@ $$<
+
+ifdef IS_ANYTHING_TO_BUILD
+-include $(PREREQUISITES)
+endif
+
+endef
+
+
+define MAKE_S
+
+$(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2))))
+$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ)))
+
+$(OBJ) : $(2)
+ @echo " AS $$<"
+ $$(Q)$$(AS) $$(ASFLAGS) -c $$< -o $$@
+
+$(PREREQUISITES) : $(2)
+ @echo " DEPS $$@"
+ @mkdir -p $(1)
+ $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(OBJ) -MF $$@ $$<
+
+ifdef IS_ANYTHING_TO_BUILD
+-include $(PREREQUISITES)
+endif
+
+endef
+
+
+define MAKE_LD
+
+$(eval PREREQUISITES := $(1).d)
+
+$(1) : $(2)
+ @echo " PP $$<"
+ $$(Q)$$(AS) $$(ASFLAGS) -P -E -o $$@ $$<
+
+$(PREREQUISITES) : $(2)
+ @echo " DEPS $$@"
+ @mkdir -p $$(dir $$@)
+ $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(1) -MF $$@ $$<
+
+ifdef IS_ANYTHING_TO_BUILD
+-include $(PREREQUISITES)
+endif
+
+endef
+
+
+define MAKE_OBJS
+ $(eval C_OBJS := $(filter %.c,$(2)))
+ $(eval REMAIN := $(filter-out %.c,$(2)))
+ $(eval $(foreach obj,$(C_OBJS),$(call MAKE_C,$(1),$(obj))))
+
+ $(eval S_OBJS := $(filter %.S,$(REMAIN)))
+ $(eval REMAIN := $(filter-out %.S,$(REMAIN)))
+ $(eval $(foreach obj,$(S_OBJS),$(call MAKE_S,$(1),$(obj))))
+
+ $(and $(REMAIN),$(error Unexpected source files present: $(REMAIN)))
+endef
+
+
+# NOTE: The line continuation '\' is required in the next define otherwise we
+# end up with a line-feed characer at the end of the last c filename.
+# Also bare this issue in mind if extending the list of supported filetypes.
+define SOURCES_TO_OBJS
+ $(notdir $(patsubst %.c,%.o,$(filter %.c,$(1)))) \
+ $(notdir $(patsubst %.S,%.o,$(filter %.S,$(1))))
+endef
+
+define MAKE_BL
+ $(eval BUILD_DIR := ${BUILD_PLAT})
+ $(eval SOURCES := $(SOURCES))
+ $(eval OBJS := $(addprefix $(BUILD_DIR)/,$(call SOURCES_TO_OBJS,$(SOURCES))))
+ $(eval LINKERFILE := $(BUILD_DIR)/acs.ld)
+ $(eval MAPFILE := $(BUILD_DIR)/acs.map)
+ $(eval ELF := $(BUILD_DIR)/acs.elf)
+ $(eval DUMP := $(BUILD_DIR)/acs.dump)
+ $(eval BIN := $(BUILD_DIR)/acs.bin)
+
+ $(eval $(call MAKE_OBJS,$(BUILD_DIR),$(SOURCES)))
+ $(eval $(call MAKE_LD,$(LINKERFILE),$(LINKERFILE_T)))
+
+$(BUILD_DIR) :
+ $$(Q)mkdir -p "$$@"
+
+$(ELF) : $(OBJS) $(LINKERFILE)
+ @echo " LD $$@"
+ @echo 'const char build_message[] = "Built : "__TIME__", "__DATE__". \\nver:${GIT_VERSION} - ${BUILDER}";' | \
+ $$(CC) $$(CFLAGS) -xc - -o $(BUILD_DIR)/build_message.o
+ $$(Q)$$(LD) -o $$@ $$(LDFLAGS) -Map=$(MAPFILE) --script $(LINKERFILE) \
+ $(BUILD_DIR)/build_message.o $(OBJS)
+
+$(DUMP) : $(ELF)
+ @echo " OD $$@"
+ $${Q}$${OD} -dxS $$< > $$@
+
+$(BIN) : $(ELF)
+ @echo " BIN $$@"
+ $$(Q)$$(OC) -O binary $$< $$@
+ @echo
+ @echo "Built $$@ successfully"
+ @echo
+
+.PHONY : bl$(1)
+bl$(1) : $(BUILD_DIR) $(DUMP) $(BIN)
+
+all : bl$(1)
+
+$(eval FIP_DEPS += $(if $2,$(BIN),))
+$(eval FIP_ARGS += $(if $2,--bl$(1) $(BIN),))
+
+endef
+
+ifeq (${NEED_BL2},yes)
+$(eval $(call MAKE_BL,2,in_fip))
+endif
+
+${BUILD_PLAT}/fip.bin: ${FIP_DEPS} ${BL33} ${FIPTOOL}
+ $(if ${BL33},,$(error "To build a FIP, please set BL33 to point to the Normal World binary, eg: BL33=../uefi/FVP_AARCH64_EFI.fd"))
+ ${Q}${FIPTOOL} --dump \
+ ${FIP_ARGS} \
+ --bl33 ${BL33} \
+ $@
+ @echo
+ @echo "Built $@ successfully"
+ @echo
+
+
+cscope:
+ @echo " CSCOPE"
+ ${Q}find ${CURDIR} -name "*.[chsS]" > cscope.files
+ ${Q}cscope -b -q -k
+
+help:
+ @echo "usage: ${MAKE} PLAT=<${HELP_PLATFORMS}> <all|bl1|bl2|bl31|distclean|clean|checkcodebase|checkpatch>"
+ @echo ""
+ @echo "PLAT is used to specify which platform you wish to build."
+ @echo "If no platform is specified, PLAT defaults to: ${DEFAULT_PLAT}"
+ @echo ""
+ @echo "Supported Targets:"
+ @echo " all Build the BL1, BL2 and BL31 binaries"
+ @echo " bl1 Build the BL1 binary"
+ @echo " bl2 Build the BL2 binary"
+ @echo " bl31 Build the BL31 binary"
+ @echo " checkcodebase Check the coding style of the entire source tree"
+ @echo " checkpatch Check the coding style on changes in the current"
+ @echo " branch against BASE_COMMIT (default origin/master)"
+ @echo " clean Clean the build for the selected platform"
+ @echo " cscope Generate cscope index"
+ @echo " distclean Remove all build artifacts for all platforms"
+ @echo " fiptool Build the Firmware Image Package(FIP) creation tool"
+ @echo ""
+ @echo "note: most build targets require PLAT to be set to a specific platform."
+ @echo ""
+ @echo "example: build all targets for the FVP platform:"
+ @echo " CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp all"
diff --git a/arch/arm/mach-meson/c1/firmware/acs/acs.c b/arch/arm/mach-meson/c1/firmware/acs/acs.c
new file mode 100644
index 0000000..76869b3
--- /dev/null
+++ b/arch/arm/mach-meson/c1/firmware/acs/acs.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <version.h>
+#include <asm/arch/acs.h>
+#include <asm/arch/timing.h>
+#include "timing.c"
+
+//main acs struct
+acs_set_t __acs_set={
+ .acs_magic = "acs__",
+ .chip_type = 0x0,
+ .version = 1,
+ .acs_set_length = sizeof(__acs_set),
+
+ .ddr_magic = "ddrs_",
+ .ddr_set_version= 1,
+ .ddr_set_length = sizeof(__ddr_setting),
+ .ddr_set_addr = (unsigned long)(&__ddr_setting),
+
+ .ddr_reg_magic = "ddrr_",
+ .ddr_reg_version= 1,
+ .ddr_reg_length = sizeof(__ddr_reg),
+ .ddr_reg_addr = (unsigned long)(&__ddr_reg),
+
+ .pll_magic = "pll__",
+ .pll_set_version= 1,
+ .pll_set_length = sizeof(__pll_setting),
+ .pll_set_addr = (unsigned long)(&__pll_setting),
+
+ .sto_magic = "store",
+ .sto_set_version= 1,
+ .sto_set_length = 0,
+ .sto_set_addr = 0,
+
+ .bl2_regs_magic = "bl2r_",
+ .bl2_regs_version = 1,
+ .bl2_regs_length = sizeof(__bl2_reg),
+ .bl2_regs_addr = (unsigned long)(&__bl2_reg),
+
+ .rsv_magic = "rsv0_",
+ .rsv_set_version= 1,
+ .rsv_set_length = 0,
+ .rsv_set_addr = 0,
+ .board_id = {0,},
+ .ddr_struct_size = {0,},
+ .ddr_struct_org_size = sizeof(ddr_set_t),
+ .revision = ACS_VERSION,
+};
diff --git a/arch/arm/mach-meson/c1/firmware/acs/acs.ld.S b/arch/arm/mach-meson/c1/firmware/acs/acs.ld.S
new file mode 100644
index 0000000..3e5bf1d
--- /dev/null
+++ b/arch/arm/mach-meson/c1/firmware/acs/acs.ld.S
@@ -0,0 +1,19 @@
+
+OUTPUT_FORMAT("elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(acs_entry)
+
+SECTIONS
+{
+ . = 0xFFFF6000;
+
+ . : {
+ __RO_START__ = .;
+ *acs_entry.o(.text*)
+ *(.text*)
+ *(.data*)
+ *(.ddr_settings*)
+ }
+
+ //ASSERT(. <= 0xFFFF7000, "timing image has exceeded its limit.")
+}
diff --git a/arch/arm/mach-meson/c1/firmware/acs/acs.mk b/arch/arm/mach-meson/c1/firmware/acs/acs.mk
new file mode 100644
index 0000000..0c63194
--- /dev/null
+++ b/arch/arm/mach-meson/c1/firmware/acs/acs.mk
@@ -0,0 +1,9 @@
+SOURCES += acs_entry.S
+
+ifdef CONFIG_MDUMP_COMPRESS
+SOURCES += ramdump.c
+endif
+
+SOURCES += acs.c
+
+LINKERFILE_T := acs.ld.S
diff --git a/arch/arm/mach-meson/c1/firmware/acs/acs_entry.S b/arch/arm/mach-meson/c1/firmware/acs/acs_entry.S
new file mode 100644
index 0000000..feca813
--- /dev/null
+++ b/arch/arm/mach-meson/c1/firmware/acs/acs_entry.S
@@ -0,0 +1,14 @@
+
+ .globl acs_entry
+
+acs_entry:
+ .word 0
+ .word __acs_set
+#ifdef CONFIG_MDUMP_COMPRESS
+ .word __ramdump_data
+ .word __ddr_setting
+#else
+ .word 0x0
+ .word __ddr_setting
+#endif
+
diff --git a/arch/arm/mach-meson/c1/firmware/bl21/Makefile b/arch/arm/mach-meson/c1/firmware/bl21/Makefile
new file mode 100644
index 0000000..b6d7d1a
--- /dev/null
+++ b/arch/arm/mach-meson/c1/firmware/bl21/Makefile
@@ -0,0 +1,3 @@
+all:
+ @echo "BL21 no action for A1 "
+
diff --git a/arch/arm/mach-meson/c1/firmware/scp_task/Makefile b/arch/arm/mach-meson/c1/firmware/scp_task/Makefile
new file mode 100644
index 0000000..925690d
--- /dev/null
+++ b/arch/arm/mach-meson/c1/firmware/scp_task/Makefile
@@ -0,0 +1,3 @@
+all:
+ echo "BL301 no action for A1"
+
diff --git a/arch/arm/mach-meson/c1/gate_init.c b/arch/arm/mach-meson/c1/gate_init.c
new file mode 100644
index 0000000..31629f6
--- /dev/null
+++ b/arch/arm/mach-meson/c1/gate_init.c
@@ -0,0 +1,366 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "power_gate.h"
+
+#define SECUREBOOT_FLAG_ADDR 0xc8100228
+
+#ifdef CONFIG_AML_CVBS
+extern unsigned int cvbs_mode;
+#endif
+void ee_gate_off(void)
+{
+ printf("ee_gate_off ...\n");
+ return;
+/* int secureboot = readl(SECUREBOOT_FLAG_ADDR)&(1<<5);*/
+
+#ifdef CONFIG_AML_CVBS
+ unsigned int cvbs_opened = 0;
+#endif
+
+#ifdef CONFIG_AML_CVBS
+ if ((cvbs_mode == 0) || (cvbs_mode == 1))
+ cvbs_opened = 1;
+#endif
+
+ /*
+ //if close , audio maybe have noise
+ CLK_GATE_OFF(AUD);
+ CLK_GATE_OFF(AUD2);
+ CLK_GATE_OFF(AUD_CLK_2);
+ CLK_GATE_OFF(AUD_CLK_3);
+ */
+ CLK_GATE_OFF(AUD_IN);
+ CLK_GATE_OFF(AIU_AUD_MIXER);
+ CLK_GATE_OFF(SANA);
+
+ /*kernel will reopen */
+ CLK_GATE_OFF(CTS_ENCL);
+ /* CLK_GATE_OFF(CTS_ENCT); */
+#if 0 /* HDMITX 480i60hz/576i50hz need this gate */
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0)
+ CLK_GATE_OFF(CTS_ENCI);
+#else
+ CLK_GATE_OFF(CTS_ENCI);
+#endif
+#endif
+ /* CLK_GATE_OFF(CTS_ENCP); */
+
+ /*close cvbs clock*/
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0) {
+ CLK_GATE_OFF(DAC_CLK);
+ CLK_GATE_OFF(CTS_VDAC);
+ }
+#else
+ CLK_GATE_OFF(DAC_CLK);
+ CLK_GATE_OFF(CTS_VDAC);
+#endif
+
+ /* usb clock close */
+ CLK_GATE_OFF(USB0);
+ CLK_GATE_OFF(USB1);
+ //CLK_GATE_OFF(USB_CLK); //g12a no reg
+ CLK_GATE_OFF(MISC_USB0_TO_DDR);
+ CLK_GATE_OFF(MISC_USB1_TO_DDR);
+
+ /* uarts close */
+ CLK_GATE_OFF(UART0);
+ CLK_GATE_OFF(UART1);
+ CLK_GATE_OFF(UART2);
+ CLK_GATE_OFF(UART3);
+
+ CLK_GATE_OFF(VCLK2_VENCP);
+ CLK_GATE_OFF(VCLK2_VENCT);
+ CLK_GATE_OFF(VCLK2_VENCT1);
+ CLK_GATE_OFF(VCLK2_OTHER);
+#if 0 /* HDMITX 480i60hz/576i50hz need HHI_GCLK_OTHER[8][2] */
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0) {
+ CLK_GATE_OFF(VCLK2_VENCI);
+ CLK_GATE_OFF(VCLK2_VENCI1);
+ }
+#else
+ CLK_GATE_OFF(VCLK2_VENCI);
+ CLK_GATE_OFF(VCLK2_VENCI1);
+#endif
+#endif
+ CLK_GATE_OFF(VCLK2_VENCL);
+ CLK_GATE_OFF(VCLK2_OTHER1);
+#if 0 /* HDMITX 480i60hz/576i50hz need HHI_GCLK_OTHER[8][2] */
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0)
+ CLK_GATE_OFF(VCLK2_ENCI);
+#else
+ CLK_GATE_OFF(VCLK2_ENCI);
+#endif
+#endif
+ CLK_GATE_OFF(VCLK2_ENCL);
+ CLK_GATE_OFF(VCLK2_ENCT);
+
+ CLK_GATE_OFF(VDEC_CLK_1);
+ CLK_GATE_OFF(VDEC_CLK_2);
+ CLK_GATE_OFF(VDEC2_CLK_1);
+ CLK_GATE_OFF(VDEC2_CLK_2);
+ CLK_GATE_OFF(HCODEC_CLK_1);
+ CLK_GATE_OFF(HCODEC_CLK_2);
+ /* CLK_GATE_OFF(HEVC_CLK_1 ); */
+ /* CLK_GATE_OFF(HEVC_CLK_2 ); */
+
+ //CLK_GATE_OFF(MMC_A_PCLK); //g12a no reg
+ //CLK_GATE_OFF(MMC_B_PCLK); //g12a no reg
+ //CLK_GATE_OFF(MMC_C_PCLK); //g12a no reg
+
+ CLK_GATE_OFF(LCD_AN_PHY2);
+ CLK_GATE_OFF(LCD_AN_PHY3);
+
+ CLK_GATE_OFF(ETHERNET);
+ //CLK_GATE_OFF(ETH_CLK); //g12a no reg
+
+ CLK_GATE_OFF(GE2D);
+ CLK_GATE_OFF(GEN_CLK);
+ //CLK_GATE_OFF(PCM_MCLK); //g12a no reg
+ //CLK_GATE_OFF(PCM_SCLK); //g12a no reg
+
+
+ CLK_GATE_OFF(HIU_PARSER_TOP);
+
+
+ /* can not off nand_clk */
+ /* CLK_GATE_OFF(NAND_CLK); */
+ /*
+ //HDMI no output
+ CLK_GATE_OFF(VCLK2_VENCP1);
+ CLK_GATE_OFF(VCLK2_ENCP);
+ */
+
+ /*
+ //if OFF, HDMI will report error!
+ CLK_GATE_OFF(HDMI_PCLK);
+ CLK_GATE_OFF(HDMI_PLL_CNTL);
+ CLK_GATE_OFF(HDMITX_CLK);
+ */
+
+ /*
+ //PWM B used for VCCK,PWM D used for VDDEE,ignoring
+ CLK_GATE_OFF(PWM_A_CLK);
+ CLK_GATE_OFF(PWM_B_CLK);
+ CLK_GATE_OFF(PWM_C_CLK);
+ CLK_GATE_OFF(PWM_D_CLK);
+ CLK_GATE_OFF(PWM_E_CLK);
+ CLK_GATE_OFF(PWM_F_CLK);
+ */
+
+
+ /* can not close
+ CLK_GATE_OFF(VPU_CLK_1);
+ CLK_GATE_OFF(VPU_CLK_2);
+ CLK_GATE_OFF(VPU_CLKB);
+ CLK_GATE_OFF(MALI_CLK_1);
+ CLK_GATE_OFF(MALI_CLK_2);
+ CLK_GATE_OFF(ATV_DEMO_VDAC);
+ CLK_GATE_OFF(EMMC_A);
+ CLK_GATE_OFF(EMMC_B);
+ CLK_GATE_OFF(EMMC_C);
+ CLK_GATE_OFF(EMMC_A_CLK);
+ CLK_GATE_OFF(EMMC_B_CLK);
+
+ CLK_GATE_OFF(MSR_CLK);
+ CLK_GATE_OFF(MSR_HS_CLK);
+ CLK_GATE_OFF(32K_CLK);
+ CLK_GATE_OFF(VAPB_CLK_1);
+ CLK_GATE_OFF(VAPB_CLK_2);
+ CLK_GATE_OFF(GIC);
+ CLK_GATE_OFF(I2C_AO); //no close for to use
+ CLK_GATE_OFF(AO_CPU);
+ CLK_GATE_OFF(ASSIST_MISC);
+ CLK_GATE_OFF(HIU_PARSER);
+ CLK_GATE_OFF(PERIPHS_TOP);
+ CLK_GATE_OFF(PL310_CBUS);
+ CLK_GATE_OFF(ISA);
+ CLK_GATE_OFF(SECURE_AHP_APB3);
+ CLK_GATE_OFF(VPU_INTR);
+ CLK_GATE_OFF(MMC_PCLK); //can not close
+ CLK_GATE_OFF(AIU_PCLK);
+ //can not connect pc
+ CLK_GATE_OFF(USB_GENERAL);
+ CLK_GATE_OFF(AHB_DATA_BUS);
+ CLK_GATE_OFF(AHB_CONTROL_BUS);
+ CLK_GATE_OFF(HDMI_INTR_SYNC); //should open
+ //can't suspend @ 2nd time
+ //CLK_GATE_OFF(RESET);
+
+ // close rom
+ //disable this bit will make other cpu can not be booted.
+ //CLK_GATE_OFF(ROM_CLK);
+
+*/
+ /*************************/
+ CLK_GATE_OFF(AHB_ARB0);
+ CLK_GATE_OFF(ASYNC_FIFO);
+ CLK_GATE_OFF(STREAM);
+ CLK_GATE_OFF(RANDOM_NUM_GEN);
+ CLK_GATE_OFF(RANDOM_NUM_GEN1);
+ CLK_GATE_OFF(SMART_CARD_MPEG_DOMAIN);
+ CLK_GATE_OFF(I2C);
+ CLK_GATE_OFF(SPI);
+ CLK_GATE_OFF(SPICC);
+ CLK_GATE_OFF(DOS);
+ CLK_GATE_OFF(SAR_ADC);
+ CLK_GATE_OFF(MISC_DVIN);
+ CLK_GATE_OFF(BT656);
+ CLK_GATE_OFF(BT656_2);
+ CLK_GATE_OFF(PDM);
+
+ /* close AIU */
+ CLK_GATE_OFF(AIU_IEC958);
+ CLK_GATE_OFF(AIU_ICE958_AMCLK);
+
+ CLK_GATE_OFF(AIU_AMCLK_MEASURE);
+ CLK_GATE_OFF(AIU_AIFIFO2);
+ CLK_GATE_OFF(AIU_MIXER_REG);
+ CLK_GATE_OFF(AIU_ADC);
+ CLK_GATE_OFF(AIU_TOP_LEVEL);
+ CLK_GATE_OFF(AIU_AOCLK);
+ CLK_GATE_OFF(AIU_AI_TOP_GLUE);
+ CLK_GATE_OFF(AIU_I2S_OUT);
+
+ CLK_GATE_OFF(ENC480P);
+
+ CLK_GATE_OFF(DEMUX);
+/*
+* EFUSE/BLK_MOV clock gate must be on,
+ kernel storage ops depend on them.
+ it can be reference PD#112732
+*/
+/*
+ if (secureboot) {
+ printf("secure boot ignore [ BLK_MOV, efuse ] clk gate\n");
+ } else {
+ CLK_GATE_OFF(EFUSE);
+ CLK_GATE_OFF(BLK_MOV);
+ }
+*/
+}
+
+void ee_gate_on(void)
+{
+
+ printf("ee_gate_on ...\n");
+
+ /*
+ //if close , audio maybe have noise
+ CLK_GATE_ON(AUD);
+ CLK_GATE_ON(AUD2);
+ CLK_GATE_ON(AUD_CLK_2);
+ CLK_GATE_ON(AUD_CLK_3);
+ */
+ CLK_GATE_ON(AUD_IN);
+ CLK_GATE_ON(AIU_AUD_MIXER);
+ CLK_GATE_ON(SANA);
+
+ /*kernel will reopen */
+ CLK_GATE_ON(CTS_ENCL);
+ /* CLK_GATE_ON(CTS_ENCT); */
+ CLK_GATE_ON(CTS_ENCI);
+ /* CLK_GATE_ON(CTS_ENCP); */
+
+ /*close cvbs clock*/
+ CLK_GATE_ON(DAC_CLK);
+ CLK_GATE_ON(CTS_VDAC);
+
+ /* usb clock close */
+ CLK_GATE_ON(USB0);
+ CLK_GATE_ON(USB1);
+ //CLK_GATE_ON(USB_CLK); //g12a no reg
+ CLK_GATE_ON(MISC_USB0_TO_DDR);
+ CLK_GATE_ON(MISC_USB1_TO_DDR);
+
+ /* uarts close */
+ CLK_GATE_ON(UART0);
+ CLK_GATE_ON(UART1);
+ CLK_GATE_ON(UART2);
+ CLK_GATE_ON(UART3);
+
+ CLK_GATE_ON(VCLK2_VENCP);
+ CLK_GATE_ON(VCLK2_VENCT);
+ CLK_GATE_ON(VCLK2_VENCT1);
+ CLK_GATE_ON(VCLK2_OTHER);
+ CLK_GATE_ON(VCLK2_VENCI);
+ CLK_GATE_ON(VCLK2_VENCI1);
+ CLK_GATE_ON(VCLK2_VENCL);
+ CLK_GATE_ON(VCLK2_OTHER1);
+
+
+ CLK_GATE_ON(VCLK2_ENCI);
+ CLK_GATE_ON(VCLK2_ENCL);
+ CLK_GATE_ON(VCLK2_ENCT);
+
+ CLK_GATE_ON(VDEC_CLK_1);
+ CLK_GATE_ON(VDEC_CLK_2);
+ CLK_GATE_ON(VDEC2_CLK_1);
+ CLK_GATE_ON(VDEC2_CLK_2);
+ CLK_GATE_ON(HCODEC_CLK_1);
+ CLK_GATE_ON(HCODEC_CLK_2);
+ /* CLK_GATE_ON(HEVC_CLK_1 ); */
+ /* CLK_GATE_ON(HEVC_CLK_2 ); */
+
+ //CLK_GATE_ON(MMC_A_PCLK); //g12a no reg
+ //CLK_GATE_ON(MMC_B_PCLK); //g12a no reg
+ //CLK_GATE_ON(MMC_C_PCLK); //g12a no reg
+
+ CLK_GATE_ON(LCD_AN_PHY2);
+ CLK_GATE_ON(LCD_AN_PHY3);
+
+ CLK_GATE_ON(ETHERNET);
+ //CLK_GATE_ON(ETH_CLK); //g12a no reg
+
+ CLK_GATE_ON(GE2D);
+ CLK_GATE_ON(GEN_CLK);
+ //CLK_GATE_ON(PCM_MCLK); //g12a no reg
+ //CLK_GATE_ON(PCM_SCLK); //g12a no reg
+
+
+ CLK_GATE_ON(HIU_PARSER_TOP);
+
+ /*************************/
+ CLK_GATE_ON(AHB_ARB0);
+ CLK_GATE_ON(ASYNC_FIFO);
+ CLK_GATE_ON(STREAM);
+ CLK_GATE_ON(RANDOM_NUM_GEN);
+ CLK_GATE_ON(RANDOM_NUM_GEN1);
+ CLK_GATE_ON(SMART_CARD_MPEG_DOMAIN);
+ CLK_GATE_ON(I2C);
+ CLK_GATE_ON(SPI);
+ CLK_GATE_ON(SPICC);
+ CLK_GATE_ON(DOS);
+ CLK_GATE_ON(SAR_ADC);
+ CLK_GATE_ON(MISC_DVIN);
+ CLK_GATE_ON(BT656);
+ CLK_GATE_ON(BT656_2);
+ CLK_GATE_ON(PDM);
+
+ /* close AIU */
+ CLK_GATE_ON(AIU_IEC958);
+ CLK_GATE_ON(AIU_ICE958_AMCLK);
+
+ CLK_GATE_ON(AIU_AMCLK_MEASURE);
+ CLK_GATE_ON(AIU_AIFIFO2);
+ CLK_GATE_ON(AIU_MIXER_REG);
+ CLK_GATE_ON(AIU_ADC);
+ CLK_GATE_ON(AIU_TOP_LEVEL);
+ CLK_GATE_ON(AIU_AOCLK);
+ CLK_GATE_ON(AIU_AI_TOP_GLUE);
+ CLK_GATE_ON(AIU_I2S_OUT);
+
+ CLK_GATE_ON(ENC480P);
+
+ CLK_GATE_ON(DEMUX);
+
+ CLK_GATE_ON(EFUSE);
+ CLK_GATE_ON(BLK_MOV);
+}
+
diff --git a/arch/arm/mach-meson/c1/gpio.c b/arch/arm/mach-meson/c1/gpio.c
new file mode 100644
index 0000000..7332773
--- /dev/null
+++ b/arch/arm/mach-meson/c1/gpio.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <linux/compiler.h>
+#include <amlogic/aml_gpio.h>
+#include <asm/arch/gpio.h>
+
+struct pin_mux_desc {
+ unsigned char domain;
+ unsigned char reg;
+ unsigned char bit;
+};
+
+#define MUX_AO_DOMAIN 0
+#define MUX_EE_DOMAIN 1
+
+#define PIN_MUX(d, r, b) \
+{ \
+ .domain = d, \
+ .reg = r, \
+ .bit = b, \
+}
+
+#define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
+{ \
+ .name = n, \
+ .first = f, \
+ .last = l, \
+ .regs = { \
+ [REG_PULLEN] = { (0xff634520 + (per<<2)), peb }, \
+ [REG_PULL] = { (0xff6344e8 + (pr<<2)), pb }, \
+ [REG_DIR] = { (0xff634440 + (dr<<2)), db }, \
+ [REG_OUT] = { (0xff634440 + (or<<2)), ob }, \
+ [REG_IN] = { (0xff634440 + (ir<<2)), ib }, \
+ }, \
+ }
+#define AOBANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
+{ \
+ .name = n, \
+ .first = f, \
+ .last = l, \
+ .regs = { \
+ [REG_PULLEN] = { (0xff800024 + (per<<2)), peb }, \
+ [REG_PULL] = { (0xff800024 + (pr<<2)), pb }, \
+ [REG_DIR] = { (0xff800024 + (dr<<2)), db }, \
+ [REG_OUT] = { (0xff800024 + (or<<2)), ob }, \
+ [REG_IN] = { (0xff800024 + (ir<<2)), ib }, \
+ }, \
+ }
+
+static struct pin_mux_desc pin_to_gpio[] = {
+ [GPIOAO(GPIOAO_0)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 0),
+ [GPIOAO(GPIOAO_1)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 4),
+ [GPIOAO(GPIOAO_2)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 8),
+ [GPIOAO(GPIOAO_3)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 12),
+ [GPIOAO(GPIOAO_4)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 16),
+ [GPIOAO(GPIOAO_5)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 20),
+ [GPIOAO(GPIOAO_6)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 24),
+ [GPIOAO(GPIOAO_7)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 28),
+ [GPIOAO(GPIOAO_8)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 0),
+ [GPIOAO(GPIOAO_9)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 4),
+ [GPIOAO(GPIOAO_10)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 8),
+ [GPIOAO(GPIOAO_11)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 12),
+ [GPIOAO(GPIOE_0)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 16),
+ [GPIOAO(GPIOE_1)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 20),
+ [GPIOAO(GPIOE_2)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 24),
+ [GPIOEE(GPIOZ_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 0),
+ [GPIOEE(GPIOZ_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 4),
+ [GPIOEE(GPIOZ_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 8),
+ [GPIOEE(GPIOZ_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 12),
+ [GPIOEE(GPIOZ_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 16),
+ [GPIOEE(GPIOZ_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 20),
+ [GPIOEE(GPIOZ_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 24),
+ [GPIOEE(GPIOZ_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 28),
+ [GPIOEE(GPIOZ_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 0),
+ [GPIOEE(GPIOZ_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 4),
+ [GPIOEE(GPIOZ_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 8),
+ [GPIOEE(GPIOZ_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 12),
+ [GPIOEE(GPIOZ_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 16),
+ [GPIOEE(GPIOZ_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 20),
+ [GPIOEE(GPIOZ_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 24),
+ [GPIOEE(GPIOZ_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 28),
+ [GPIOEE(GPIOH_0)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 0),
+ [GPIOEE(GPIOH_1)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 4),
+ [GPIOEE(GPIOH_2)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 8),
+ [GPIOEE(GPIOH_3)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 12),
+ [GPIOEE(GPIOH_4)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 16),
+ [GPIOEE(GPIOH_5)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 20),
+ [GPIOEE(GPIOH_6)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 24),
+ [GPIOEE(GPIOH_7)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 28),
+ [GPIOEE(GPIOH_8)] = PIN_MUX(MUX_EE_DOMAIN, 0xc, 0),
+ [GPIOEE(BOOT_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 0),
+ [GPIOEE(BOOT_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 4),
+ [GPIOEE(BOOT_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 8),
+ [GPIOEE(BOOT_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 12),
+ [GPIOEE(BOOT_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 16),
+ [GPIOEE(BOOT_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 20),
+ [GPIOEE(BOOT_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 24),
+ [GPIOEE(BOOT_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 28),
+ [GPIOEE(BOOT_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 0),
+ [GPIOEE(BOOT_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 4),
+ [GPIOEE(BOOT_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 8),
+ [GPIOEE(BOOT_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 12),
+ [GPIOEE(BOOT_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 16),
+ [GPIOEE(BOOT_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 20),
+ [GPIOEE(BOOT_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 24),
+ [GPIOEE(BOOT_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 28),
+ [GPIOEE(GPIOC_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 0),
+ [GPIOEE(GPIOC_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 4),
+ [GPIOEE(GPIOC_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 8),
+ [GPIOEE(GPIOC_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 12),
+ [GPIOEE(GPIOC_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 16),
+ [GPIOEE(GPIOC_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 20),
+ [GPIOEE(GPIOC_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 24),
+ [GPIOEE(GPIOC_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 28),
+ [GPIOEE(GPIOA_0)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 0),
+ [GPIOEE(GPIOA_1)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 4),
+ [GPIOEE(GPIOA_2)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 8),
+ [GPIOEE(GPIOA_3)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 12),
+ [GPIOEE(GPIOA_4)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 16),
+ [GPIOEE(GPIOA_5)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 20),
+ [GPIOEE(GPIOA_6)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 24),
+ [GPIOEE(GPIOA_7)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 28),
+ [GPIOEE(GPIOA_8)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 0),
+ [GPIOEE(GPIOA_9)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 4),
+ [GPIOEE(GPIOA_10)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 8),
+ [GPIOEE(GPIOA_11)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 12),
+ [GPIOEE(GPIOA_12)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 16),
+ [GPIOEE(GPIOA_13)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 20),
+ [GPIOEE(GPIOA_14)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 24),
+ [GPIOEE(GPIOA_15)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 28),
+ [GPIOEE(GPIOX_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 0),
+ [GPIOEE(GPIOX_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 4),
+ [GPIOEE(GPIOX_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 8),
+ [GPIOEE(GPIOX_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 12),
+ [GPIOEE(GPIOX_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 16),
+ [GPIOEE(GPIOX_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 20),
+ [GPIOEE(GPIOX_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 24),
+ [GPIOEE(GPIOX_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 28),
+ [GPIOEE(GPIOX_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 0),
+ [GPIOEE(GPIOX_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 4),
+ [GPIOEE(GPIOX_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 8),
+ [GPIOEE(GPIOX_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 12),
+ [GPIOEE(GPIOX_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 16),
+ [GPIOEE(GPIOX_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 20),
+ [GPIOEE(GPIOX_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 24),
+ [GPIOEE(GPIOX_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 28),
+ [GPIOEE(GPIOX_16)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 0),
+ [GPIOEE(GPIOX_17)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 4),
+ [GPIOEE(GPIOX_18)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 8),
+ [GPIOEE(GPIOX_19)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 12),
+};
+/*sequence of banks keep same as arch-g12a/gpio.h*/
+static struct meson_bank mesontxhd_banks[] = {
+ /*name first last pullen pull dir out in*/
+ AOBANK("GPIOAO_", GPIOAO(GPIOAO_0), GPIOAO(GPIOAO_11),
+ 3, 0, 2, 0, 0, 0, 4, 0, 1, 0),
+ AOBANK("GPIOE_", GPIOAO(GPIOE_0), GPIOAO(GPIOE_2),
+ 3, 16, 2, 16, 0, 16, 4, 16, 1, 16),
+ BANK("GPIOZ_", GPIOEE(GPIOZ_0), GPIOEE(GPIOZ_15),
+ 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
+ BANK("GPIOH_", GPIOEE(GPIOH_0), GPIOEE(GPIOH_8),
+ 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
+ BANK("BOOT_", GPIOEE(BOOT_0), GPIOEE(BOOT_15),
+ 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
+ BANK("GPIOC_", GPIOEE(GPIOC_0), GPIOEE(GPIOC_7),
+ 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
+ BANK("GPIOA_", GPIOEE(GPIOA_0), GPIOEE(GPIOA_15),
+ 5, 0, 5, 0, 16, 0, 17, 0, 18, 0),
+ BANK("GPIOX_", GPIOEE(GPIOX_0), GPIOEE(GPIOX_19),
+ 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
+};
+
+U_BOOT_DEVICES(txhd_gpios) = {
+ { "gpio_aml", &mesontxhd_banks[0] },
+ { "gpio_aml", &mesontxhd_banks[1] },
+ { "gpio_aml", &mesontxhd_banks[2] },
+ { "gpio_aml", &mesontxhd_banks[3] },
+ { "gpio_aml", &mesontxhd_banks[4] },
+ { "gpio_aml", &mesontxhd_banks[5] },
+ { "gpio_aml", &mesontxhd_banks[6] },
+ { "gpio_aml", &mesontxhd_banks[7] },
+};
+
+static unsigned long domain[]={
+ [MUX_AO_DOMAIN] = 0xff800014,
+ [MUX_EE_DOMAIN] = 0xff6346c0,
+};
+
+int clear_pinmux(unsigned int pin)
+{
+ struct pin_mux_desc *pmux_desc = &pin_to_gpio[pin];
+
+ regmap_update_bits(domain[pmux_desc->domain] + (pmux_desc->reg << 2),
+ 0xf << (pmux_desc->bit), 0 << (pmux_desc->bit));
+
+ return 0;
+}
+
+#ifdef CONFIG_AML_SPICC
+#include <asm/arch/secure_apb.h>
+/* generic pins control for spicc1.
+ * if deleted, you have to add it into all g12a board files as necessary.
+ * GPIOH_4: MOSI:regB[19:16]=3
+ * GPIOH_5: MISO:regB[23:20]=3
+ * GPIOH_7: CLK:regB[31:28]=3
+ */
+int spicc1_pinctrl_enable(bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_B);
+ val &= ~(0xf0ff << 16);
+ if (enable)
+ val |= 0x3033 << 16;
+ writel(val, P_PERIPHS_PIN_MUX_B);
+ return 0;
+}
+#endif /* CONFIG_AML_SPICC */
diff --git a/arch/arm/mach-meson/c1/hdmitx.c b/arch/arm/mach-meson/c1/hdmitx.c
new file mode 100644
index 0000000..5292c87
--- /dev/null
+++ b/arch/arm/mach-meson/c1/hdmitx.c
@@ -0,0 +1,594 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/io.h>
+#include <asm/io.h>
+#include <amlogic/media/vout/hdmitx.h>
+#include <asm/arch/regs.h>
+#include <asm/arch/secure_apb.h>
+
+#define HDMITX_DWC_BASE_OFFSET 0xFF600000
+#define HDMITX_TOP_BASE_OFFSET 0xFF608000
+
+static int dbg_en =0;
+
+unsigned long hd_read_reg(volatile unsigned int* addr)
+{
+ unsigned long val = 0;
+
+ val = *addr;
+ if (dbg_en)
+ printk("R: 0x%8p 0x%08lx\n", addr, val);
+ return val;
+}
+
+void hd_write_reg(volatile unsigned int* addr, unsigned long val)
+{
+ *addr = val;
+ if (dbg_en)
+ printk("W: 0x%8p 0x%08lx %s 0x%08lx\n", addr,
+ val, (val == hd_read_reg(addr)) ? "==" : "!=", hd_read_reg(addr));
+}
+
+void hd_set_reg_bits(volatile unsigned int* addr, unsigned long value,
+ unsigned long offset, unsigned long len)
+{
+ unsigned long data = 0;
+
+ data = hd_read_reg(addr);
+ data &= ~(((1L << len) - 1) << offset);
+ data |= (value & ((1L << len) - 1)) << offset;
+ hd_write_reg(addr, data);
+}
+
+#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
+unsigned int hdmitx_rd_reg(unsigned int addr)
+{
+ unsigned int large_offset = addr >> 24;
+ unsigned int small_offset = addr & ((1 << 24) - 1);
+ unsigned int data = 0;
+ register long x0 asm("x0") = 0x82000018;
+ register long x1 asm("x1") = (unsigned long)addr;
+
+ if (large_offset == 0x10) {
+ large_offset = HDMITX_DWC_BASE_OFFSET;
+ data = readb((unsigned long)(large_offset + small_offset));
+ } else if (large_offset == 0x0){
+ large_offset = HDMITX_TOP_BASE_OFFSET;
+ if ((small_offset >= 0x2000) && (small_offset <= 0x365E)) {
+ data = readb((unsigned long)(large_offset + small_offset));
+ } else {
+ small_offset = small_offset << 2;
+ data = readl((unsigned long)(large_offset + small_offset));
+ }
+ } else {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r"(x0) : "r"(x1)
+ );
+ data = (unsigned)(x0&0xffffffff);
+ }
+ if (dbg_en)
+ printk("%s wr[0x%x] 0x%x\n", large_offset ? "DWC" : "TOP",
+ addr, data);
+
+ return data;
+}
+
+void hdmitx_wr_reg(unsigned int addr, unsigned int data)
+{
+ unsigned int large_offset = addr >> 24;
+ unsigned int small_offset = addr & ((1 << 24) - 1);
+ register long x0 asm("x0") = 0x82000019;
+ register long x1 asm("x1") = (unsigned long)addr;
+ register long x2 asm("x2") = data;
+
+ if (large_offset == 0x10) {
+ large_offset = HDMITX_DWC_BASE_OFFSET;
+ writeb(data & 0xff, (unsigned long)(large_offset + small_offset));
+ } else if (large_offset == 0x0){
+ large_offset = HDMITX_TOP_BASE_OFFSET;
+ if ((small_offset >= 0x2000) && (small_offset <= 0x365E)) {
+ writeb(data & 0xff,(unsigned long)(large_offset + small_offset));
+ } else {
+ small_offset = small_offset << 2;
+ writel(data,(unsigned long)(large_offset + small_offset));
+ }
+ } else {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ "smc #0\n"
+ : : "r"(x0), "r"(x1), "r"(x2)
+ );
+ }
+ if (dbg_en)
+ printk("%s wr[0x%x] 0x%x\n", large_offset ? "DWC" : "TOP",
+ addr, data);
+}
+
+void hdmitx_set_reg_bits(unsigned int addr, unsigned int value,
+ unsigned int offset, unsigned int len)
+{
+ unsigned int data32 = 0;
+
+ data32 = hdmitx_rd_reg(addr);
+ data32 &= ~(((1 << len) - 1) << offset);
+ data32 |= (value & ((1 << len) - 1)) << offset;
+ hdmitx_wr_reg(addr, data32);
+}
+
+void hdmitx_poll_reg(unsigned int addr, unsigned int val,
+ unsigned long timeout)
+{
+ udelay(2000);
+ if (!(hdmitx_rd_reg(addr) & val))
+ printk("hdmitx poll:0x%x val:0x%x t=%dms timeout\n",
+ addr, val, 2000);
+}
+
+void hdmitx_rd_check_reg (unsigned long addr,
+ unsigned long exp_data, unsigned long mask)
+{
+ unsigned long rd_data;
+ rd_data = hdmitx_rd_reg(addr);
+ if ((rd_data | mask) != (exp_data | mask)) {
+ printk("HDMITX-DWC addr=0x%04x rd_data=0x%02x\n",
+ (unsigned int)addr, (unsigned int)rd_data);
+ printk("Error: HDMITX-DWC exp_data=0x%02x mask=0x%02x\n",
+ (unsigned int)exp_data, (unsigned int)mask);
+ }
+}
+
+static void set_phy_by_mode(unsigned int mode)
+{
+ switch (mode) {
+ case 1: /* 5.94/4.5/3.7Gbps */
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb5584);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b);
+ break;
+ case 2: /* 2.97Gbps */
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4262);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
+ break;
+ case 3: /* 1.485Gbps, and below */
+ default:
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4242);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
+ break;
+ }
+}
+void hdmitx_set_phy(struct hdmitx_dev *hdev)
+{
+ if (!hdev)
+ return;
+
+ switch (hdev->vic) {
+ case HDMI_3840x2160p50_16x9:
+ case HDMI_3840x2160p60_16x9:
+ case HDMI_4096x2160p50_256x135:
+ case HDMI_4096x2160p60_256x135:
+ if ((hdev->para->cs == HDMI_COLOR_FORMAT_420)
+ && (hdev->para->cd == HDMI_COLOR_DEPTH_24B))
+ set_phy_by_mode(2);
+ else
+ set_phy_by_mode(1);
+ break;
+ case HDMI_3840x2160p50_16x9_Y420:
+ case HDMI_3840x2160p60_16x9_Y420:
+ case HDMI_4096x2160p50_256x135_Y420:
+ case HDMI_4096x2160p60_256x135_Y420:
+ if (hdev->para->cd == HDMI_COLOR_DEPTH_24B)
+ set_phy_by_mode(2);
+ else
+ set_phy_by_mode(1);
+ break;
+ case HDMI_3840x2160p24_16x9:
+ case HDMI_3840x2160p24_64x27:
+ case HDMI_3840x2160p25_16x9:
+ case HDMI_3840x2160p25_64x27:
+ case HDMI_3840x2160p30_16x9:
+ case HDMI_3840x2160p30_64x27:
+ case HDMI_4096x2160p24_256x135:
+ case HDMI_4096x2160p25_256x135:
+ case HDMI_4096x2160p30_256x135:
+ if ((hdev->para->cs == HDMI_COLOR_FORMAT_422)
+ || (hdev->para->cd == HDMI_COLOR_DEPTH_24B))
+ set_phy_by_mode(2);
+ else
+ set_phy_by_mode(1);
+ break;
+ case HDMI_1920x1080p60_16x9:
+ case HDMI_1920x1080p50_16x9:
+ case HDMI_1920x1080i100_16x9:
+ case HDMI_1920x1080i120_16x9:
+ case HDMI_1280x720p100_16x9:
+ case HDMI_1280x720p120_16x9:
+ default:
+ set_phy_by_mode(3);
+ break;
+ }
+/* P_HHI_HDMI_PHY_CNTL1 bit[1]: enable clock bit[0]: soft reset */
+#define RESET_HDMI_PHY() \
+do { \
+ hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0xf, 0, 4); \
+ mdelay(2); \
+ hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0xe, 0, 4); \
+ mdelay(2); \
+} while (0)
+
+ hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0x0390, 16, 16);
+ hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0x0, 0, 4);
+ RESET_HDMI_PHY();
+ RESET_HDMI_PHY();
+ RESET_HDMI_PHY();
+#undef RESET_HDMI_PHY
+
+ printk("hdmitx phy setting done\n");
+}
+
+void hdmitx_turnoff(void)
+{
+ /* Close HDMITX PHY */
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0);
+ /* Disable HPLL */
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0);
+}
+
+#define WAIT_FOR_PLL_LOCKED(reg) \
+ do { \
+ unsigned int st = 0; \
+ int cnt = 10; \
+ while (cnt--) { \
+ udelay(50); \
+ st = (((hd_read_reg(reg) >> 30) & 0x3) == 3); \
+ if (st) \
+ break; \
+ else { \
+ /* reset hpll */ \
+ hd_set_reg_bits(reg, 1, 29, 1); \
+ hd_set_reg_bits(reg, 0, 29, 1); \
+ } \
+ } \
+ if (cnt < 9) \
+ printk("pll[0x%8p] reset %d times\n", reg, 9 - cnt);\
+ } while (0)
+
+static bool set_hpll_hclk_v1(unsigned int m, unsigned int frac_val,
+ struct hdmitx_dev *hdev)
+{
+ int ret = 0;
+
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x0b3a0400 | (m & 0xff));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x3, 28, 2);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, frac_val);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ if (frac_val == 0x8148) {
+ if (((hdev->para->vic == HDMI_3840x2160p50_16x9) ||
+ (hdev->para->vic == HDMI_3840x2160p60_16x9) ||
+ (hdev->para->vic == HDMI_3840x2160p50_64x27) ||
+ (hdev->para->vic == HDMI_3840x2160p60_64x27)) &&
+ (hdev->para->cs != HDMI_COLOR_FORMAT_420)) {
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x11551293);
+ } else {
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x44331290);
+ }
+ } else {
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a68dc00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290);
+ }
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39272000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540000);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLLv1: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+
+ ret = (((hd_read_reg(P_HHI_HDMI_PLL_CNTL0) >> 30) & 0x3) == 0x3);
+ return ret;
+}
+
+static bool set_hpll_hclk_v2(unsigned int m, unsigned int frac_val)
+{
+ int ret = 0;
+
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x0b3a0400 | (m & 0xff));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x3, 28, 2);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, frac_val);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0xea68dc00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39272000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540000);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLLv2: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+
+ ret = (((hd_read_reg(P_HHI_HDMI_PLL_CNTL0) >> 30) & 0x3) == 0x3);
+ return ret;
+}
+
+static bool set_hpll_hclk_v3(unsigned int m, unsigned int frac_val)
+{
+ int ret = 0;
+
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x0b3a0400 | (m & 0xff));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x3, 28, 2);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, frac_val);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0xea68dc00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39272000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x55540000);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLLv3: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+
+ ret = (((hd_read_reg(P_HHI_HDMI_PLL_CNTL0) >> 30) & 0x3) == 0x3);
+ return ret;
+}
+
+void set_hpll_clk_out(unsigned clk, struct hdmitx_dev *hdev)
+{
+ unsigned int frac_rate ;
+
+ frac_rate = hdev->frac_rate_policy;
+ if (clk == -1)
+ return;
+ printk("config HPLL = %d frac_rate = %d\n", clk, frac_rate);
+
+ switch (clk) {
+ case 5940000:
+ if (set_hpll_hclk_v1(0xf7, frac_rate ? 0x8148 : 0x10000, hdev))
+ break;
+ else if (set_hpll_hclk_v2(0x7b,0x18000))
+ break;
+ else if (set_hpll_hclk_v3(0xf7,0x10000))
+ break;
+ else
+ break;
+ break;
+ case 5405400:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004e1);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00007333);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 4455000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b9);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00014000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 3712500:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00049a);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00016000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 3450000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00048f);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 3243240:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000487);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0000451f);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 2970000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00047b);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 4324320:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b4);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ default:
+ printk("error hpll clk: %d\n", clk);
+ break;
+ }
+ printk("config HPLL done\n");
+}
+
+void set_hpll_od1(unsigned div)
+{
+ switch (div) {
+ case 1:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0, 16, 2);
+ break;
+ case 2:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 1, 16, 2);
+ break;
+ case 4:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 2, 16, 2);
+ break;
+ default:
+ printk("Err %s[%d]\n", __func__, __LINE__);
+ break;
+ }
+}
+
+void set_hpll_od2(unsigned div)
+{
+ switch (div) {
+ case 1:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0, 18, 2);
+ break;
+ case 2:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 1, 18, 2);
+ break;
+ case 4:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 2, 18, 2);
+ break;
+ default:
+ printk("Err %s[%d]\n", __func__, __LINE__);
+ break;
+ }
+}
+
+void set_hpll_od3(unsigned div)
+{
+ switch (div) {
+ case 1:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0, 20, 2);
+ break;
+ case 2:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 1, 20, 2);
+ break;
+ case 4:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 2, 20, 2);
+ break;
+ default:
+ printk("Err %s[%d]\n", __func__, __LINE__);
+ break;
+ }
+}
+
+/* HERE MUST BE BIT OPERATION!!! */
+void set_hpll_sspll(struct hdmitx_dev *hdev)
+{
+ enum hdmi_vic vic = hdev->vic;
+
+ switch (vic) {
+ case HDMI_1920x1080p60_16x9:
+ case HDMI_1920x1080p50_16x9:
+ case HDMI_1280x720p60_16x9:
+ case HDMI_1280x720p50_16x9:
+ case HDMI_1920x1080i60_16x9:
+ case HDMI_1920x1080i50_16x9:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 1, 29, 1);
+ /* bit[22:20] hdmi_dpll_fref_sel
+ * bit[8] hdmi_dpll_ssc_en
+ * bit[7:4] hdmi_dpll_ssc_dep_sel
+ */
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 1, 20, 3);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 1, 8, 1);
+ /* 2: 1000ppm 1: 500ppm */
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 2, 4, 4);
+ /* bit[15] hdmi_dpll_sdmnc_en */
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL3, 0, 15, 1);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0, 29, 1);
+ break;
+ default:
+ break;
+ }
+}
+
+void ddc_pinmux_init(void)
+{
+ hd_set_reg_bits(P_PAD_PULL_UP_EN_REG3, 0, 0, 2); /*Disable GPIOH_1/2 pull-up/down*/
+ hd_set_reg_bits(P_PAD_PULL_UP_REG3, 0, 0, 2);
+ hd_set_reg_bits(P_PREG_PAD_GPIO3_EN_N, 3, 0, 2); /*GPIOH_1/2 input*/
+ hd_set_reg_bits(P_PERIPHS_PIN_MUX_B, 0x11, 0, 8); /*Mux DDC SDA/SCL*/
+}
+
+int hdmitx_get_hpd_state(void)
+{
+ int st = 0;
+
+ st = !!(hd_read_reg(P_PREG_PAD_GPIO3_I) & (1 << 2));
+ return st;
+}
+
+void hdmitx_prbs(void)
+{
+ unsigned int i;
+
+ for (i = 0; i < 4; i ++) {
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0x0390000f);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0x0390000e);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0x03904002);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL4, 0x0001efff | (i << 20));
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0xef904002);
+ mdelay(10);
+ if (i > 0)
+ pr_info("prbs D[%d]:%lx\n", i -1, hd_read_reg(P_HHI_HDMI_PHY_STATUS));
+ else
+ pr_info("prbs clk :%lx\n",hd_read_reg(P_HHI_HDMI_PHY_STATUS));
+ }
+}
+
+void hdmitx_enable_apb3(void)
+{
+ /*g12a doesn't need enable apb3*/
+ return;
+ /*hd_set_reg_bits(P_HDMITX_CTRL_PORT, 1, 15, 1);*/
+ /*hd_set_reg_bits((P_HDMITX_CTRL_PORT + 0x10), 1, 15, 1);*/
+}
diff --git a/arch/arm/mach-meson/c1/mailbox.c b/arch/arm/mach-meson/c1/mailbox.c
new file mode 100644
index 0000000..7105170
--- /dev/null
+++ b/arch/arm/mach-meson/c1/mailbox.c
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/arch/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/arch/mailbox.h>
+#include <asm/arch/secure_apb.h>
+
+/* Bit position for size value in MHU header */
+#define SIZE_SHIFT 20
+/* Mask to extract size value in MHU header*/
+#define SIZE_MASK 0x1ff
+
+static unsigned int *ap_mb_stat[] = {
+ (unsigned int *)HIU_MAILBOX_STAT_4,
+ (unsigned int *)HIU_MAILBOX_STAT_5,
+};
+static unsigned int *ap_mb_set[] = {
+ (unsigned int *)HIU_MAILBOX_SET_4,
+ (unsigned int *)HIU_MAILBOX_SET_5,
+};
+static unsigned int *ap_mb_clear[] = {
+ (unsigned int *)HIU_MAILBOX_CLR_4,
+ (unsigned int *)HIU_MAILBOX_CLR_5,
+};
+static unsigned int *ap_mb_payload[] = {
+ (unsigned int *)(P_SHARE_SRAM_BASE + MHU_LOW_AP_TO_SCP_PAYLOAD),
+ (unsigned int *)(P_SHARE_SRAM_BASE + MHU_HIGH_AP_TO_SCP_PAYLOAD),
+};
+static unsigned int *scp_mb_stat[] = {
+ (unsigned int *)HIU_MAILBOX_STAT_1,
+ (unsigned int *)HIU_MAILBOX_STAT_2,
+};
+/*
+static unsigned int *scp_mb_set[] = {
+ (unsigned int *)HIU_MAILBOX_SET_1,
+ (unsigned int *)HIU_MAILBOX_SET_2,
+};
+*/
+static unsigned int *scp_mb_clear[] = {
+ (unsigned int *)HIU_MAILBOX_CLR_1,
+ (unsigned int *)HIU_MAILBOX_CLR_2,
+};
+static unsigned int *scp_mb_payload[] = {
+ (unsigned int *)(P_SHARE_SRAM_BASE + MHU_LOW_SCP_TO_AP_PAYLOAD),
+ (unsigned int *)(P_SHARE_SRAM_BASE + MHU_HIGH_SCP_TO_AP_PAYLOAD),
+};
+
+static void mb_message_start(unsigned int priority)
+{
+ while (readl(ap_mb_stat[priority]) != 0)
+ ;
+}
+static void mb_message_send(unsigned int command, unsigned int priority)
+{
+ writel(command, ap_mb_set[priority]);
+ while (readl(ap_mb_stat[priority]) != 0)
+ ;
+}
+static unsigned int mb_message_wait(unsigned int priority)
+{
+ unsigned int response;
+ while (!(response = readl(scp_mb_stat[priority])))
+ ;
+ return response;
+}
+static void mb_message_end(unsigned int priority)
+{
+ writel(0xffffffff, scp_mb_clear[priority]);
+}
+static unsigned int mb_message_receive(
+ void **message_out,
+ unsigned int *size_out,
+ unsigned int priority)
+{
+ unsigned int response = mb_message_wait(priority);
+ unsigned int size = (response >> SIZE_SHIFT) & SIZE_MASK;
+
+ response &= ~(SIZE_MASK << SIZE_SHIFT);
+
+ if (size_out)
+ *size_out = size;
+ if (message_out)
+ *message_out = (void *)(scp_mb_payload[priority]);
+
+ return response;
+}
+static void mb_init(unsigned int priority)
+{
+ writel(0xffffffff, ap_mb_clear[priority]);
+}
+
+static void scpi_send32(unsigned int command,
+ unsigned int message, unsigned int priority)
+{
+ mb_init(priority);
+ mb_message_start(priority);
+ writel(message, ap_mb_payload[priority]);
+ mb_message_send(command, priority);
+ mb_message_wait(priority);
+ mb_message_end(priority);
+}
+
+static void scpi_send_block(unsigned int command,
+ unsigned int *message, unsigned int message_size, unsigned int priority)
+{
+ mb_init(priority);
+ mb_message_start(priority);
+ memcpy(ap_mb_payload[priority], message, message_size);
+ mb_message_send(command, priority);
+ mb_message_wait(priority);
+ mb_message_end(priority);
+}
+
+void open_scp_log(unsigned int channel)
+{
+ scpi_send32(SCPI_CMD_OPEN_SCP_LOG, channel, LOW_PRIORITY);
+}
+
+int send_usr_data(unsigned int clinet_id, unsigned int *val, unsigned int size)
+{
+ unsigned long command;
+
+ if (size > 0x1fd)
+ return -1;
+
+ command = ((unsigned int)SCPI_CMD_SET_USR_DATA & 0xff) | ((clinet_id & 0xff) << 8) | ((size & 0x1ff) << 20);
+ scpi_send_block(command,val,size,0);
+
+ return 0;
+}
+
+/*
+* type:
+* 0: data; 1: version
+*/
+int thermal_calibration(unsigned int type, unsigned int data)
+{
+ unsigned int *appayload = ap_mb_payload[LOW_PRIORITY];
+ unsigned int *response;
+ unsigned int size;
+
+ mb_message_start(LOW_PRIORITY);
+ writel(type, appayload);
+ writel(data, appayload+1);
+ mb_message_send(
+ ((0x8 << SIZE_SHIFT) | SCPI_CMD_THERMAL_CALIB),
+ LOW_PRIORITY);
+ mb_message_receive((void *)&response, &size, LOW_PRIORITY);
+ mb_message_end(LOW_PRIORITY);
+
+ if (*response != SCPI_SUCCESS)
+ return -1;
+ else
+ return 0;
+}
+
+int thermal_get_value(unsigned int sensor_id, unsigned int *value)
+{
+ unsigned int *response;
+ unsigned int size;
+
+ mb_message_start(LOW_PRIORITY);
+ writel(sensor_id, ap_mb_payload[LOW_PRIORITY]);
+ mb_message_send(
+ ((0x4 << SIZE_SHIFT) | SCPI_CMD_SENSOR_VALUE),
+ LOW_PRIORITY);
+ mb_message_receive((void *)&response, &size, LOW_PRIORITY);
+ mb_message_end(LOW_PRIORITY);
+
+ *value = *(response+1);
+ if (*response != SCPI_SUCCESS)
+ return -1;
+ else
+ return 0;
+}
+
+
+void send_pwm_delt(int32_t vcck_delt, int32_t ee_delt)
+{
+ unsigned int *appayload = ap_mb_payload[LOW_PRIORITY];
+ mb_message_start(LOW_PRIORITY);
+ writel(vcck_delt, appayload);
+ writel(ee_delt, appayload+1);
+ mb_message_send(SCPI_CMD_REV_PWM_DELT, LOW_PRIORITY);
+ mb_message_wait(LOW_PRIORITY);
+ mb_message_end(LOW_PRIORITY);
+}
+
diff --git a/arch/arm/mach-meson/c1/oscring.c b/arch/arm/mach-meson/c1/oscring.c
new file mode 100644
index 0000000..fcf6872
--- /dev/null
+++ b/arch/arm/mach-meson/c1/oscring.c
@@ -0,0 +1,105 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/arch/io.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/oscring.h>
+
+void ring_powerinit(void)
+{
+ writel(0x18000a, RING_PWM_VCCK);/*set vcck 0.8v*/
+ writel(0xc0006, RING_PWM_EE);/*set ee 0.8v*/
+}
+
+unsigned long clk_util_ring_msr(unsigned long clk_mux)
+{
+ unsigned int regval = 0;
+
+ writel(0, MSR_CLK_REG0);
+ /* Set the measurement gate to 64uS */
+ /* 64uS is enough for measure the frequence? */
+ setbits_le32(MSR_CLK_REG0, (10000 - 1));
+ /* Disable continuous measurement */
+ /* Disable interrupts */
+ clrbits_le32(MSR_CLK_REG0, (1 << 17) | (1 << 18));
+ clrbits_le32(MSR_CLK_REG0, 0x7f << 20);
+ setbits_le32(MSR_CLK_REG0, (clk_mux) << 20 | (1 << 19) | (1 << 16));
+ /* Wait for the measurement to be done */
+ regval = readl(MSR_CLK_REG0);
+ do {
+ regval = readl(MSR_CLK_REG0);
+ } while (regval & (1 << 31));
+
+ /* Disable measuring */
+ clrbits_le32(MSR_CLK_REG0, 1 << 16);
+ regval = (readl(MSR_CLK_REG2) + 31) & 0x000fffff;
+
+ return (regval / 10);
+}
+
+int ring_msr(int index)
+{
+ const char* clk_table[] = {
+ [14] = "osc_ring_clk_dos3 " ,
+ [13] = "osc_ring_clk_dos2 " ,
+ [12] = "osc_ring_clk_dos1 " ,
+ [11] = "osc_ring_clk_dos0 " ,
+ [10] = "osc_ring_clk_ramc " ,
+ [9] = "osc_ring_clk_ramb " ,
+ [8] = "osc_ring_clk_rama " ,
+ [7] = "osc_ring_clk_dspb " ,
+ [6] = "osc_ring_clk_dspa " ,
+ [5] = "osc_ring_clk_dmc " ,
+ [4] = "osc_ring_clk_ddr " ,
+ [3] = "osc_ring_clk_cpu3 " ,
+ [2] = "osc_ring_clk_cpu2 " ,
+ [1] = "osc_ring_clk_cpu1 " ,
+ [0] = "osc_ring_clk_cpu0" ,
+ };
+ const int tb[] = {46,47,48,49,50, 51, 54, 55, 56, 57, 58, 59, 60};
+ unsigned long i;
+ uint8_t efuseinfo[4] = {0, 0, 0, 0};
+
+ if ((index != 0xff) && (index != 0)) {
+ if (bl31_get_cornerinfo(efuseinfo, sizeof(efuseinfo) / sizeof(uint8_t)) != 0) {
+ printf("fail get efuse info\n");
+ return 0;
+ }
+ if ((index >= 1) && (index <= 3))
+ printf("%d\n", efuseinfo[index]);
+ else
+ printf("input data not support!\n");
+
+ return 0;
+ }
+ if (0xff != index) {
+ ring_powerinit();
+ printf("set vcck vddee to 800mv\n");
+ }
+ /*RING_OSCILLATOR 0x7f: set slow ring*/
+ writel(OSCRING_CTL_DATA0, OSCRING_CTL_REG0);
+ writel(OSCRING_CTL_DATA1, OSCRING_CTL_REG1);
+
+ for (i = 0; i < 15; i++) {
+ printf("%s :",clk_table[i]);
+ printf("%ld KHz",clk_util_ring_msr(tb[i]));
+ printf("\n");
+ }
+
+ if (bl31_get_cornerinfo(efuseinfo, sizeof(efuseinfo) / sizeof(uint8_t)) != 0) {
+ printf("fail get efuse info\n");
+ return 0;
+ }
+
+ printf("osc efuse info:\n");
+ for (i = 0; i < sizeof(efuseinfo) / sizeof(uint8_t); i++)
+ printf("0x%x, ", efuseinfo[i]);
+ printf("\n");
+
+ return 0;
+}
diff --git a/arch/arm/mach-meson/c1/pinctrl_init.c b/arch/arm/mach-meson/c1/pinctrl_init.c
new file mode 100644
index 0000000..829ce28
--- /dev/null
+++ b/arch/arm/mach-meson/c1/pinctrl_init.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm/uclass.h>
+#include <linux/err.h>
+#include <asm/arch/pinctrl_init.h>
+
+int pinctrl_devices_active(int pinctrl_num)
+{
+ int ret;
+ int idx;
+ struct udevice *pinctrl;
+
+ for (idx = 0; idx < pinctrl_num; idx++) {
+ ret = uclass_get_device(UCLASS_PINCTRL, idx, &pinctrl);
+ if (ret) {
+ debug("%s: failed to active pinctrl device [%d]",
+ __func__, idx);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-meson/c1/pll.c b/arch/arm/mach-meson/c1/pll.c
new file mode 100644
index 0000000..b53979f
--- /dev/null
+++ b/arch/arm/mach-meson/c1/pll.c
@@ -0,0 +1,1062 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <amlogic/cpu_id.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/pll.h>
+
+#define STR_PLL_TEST_ALL "all"
+#define STR_PLL_TEST_SYS "sys"
+#define STR_PLL_TEST_FIX "fix"
+#define STR_PLL_TEST_DDR "ddr"
+#define STR_PLL_TEST_HIFI "hifi"
+#define STR_PLL_TEST_GP "gp"
+#define STR_PLL_TEST_DDS "dds"
+#define STR_PLL_TEST_USBPHY "usbphy"
+#define STR_PLL_TEST_ETHPHY "ethphy"
+
+
+#define PLL_LOCK_CHECK_MAX 20
+
+#define RET_PLL_LOCK_FAIL 0x1000
+#define RET_CLK_NOT_MATCH 0x1
+#define SYS_PLL_DIV16_CNTL (1<<24)
+#define SYS_CLK_DIV16_CNTL (1)
+#define SYS_PLL_TEST_DIV 4 /* div16 */
+#define HDMI_PLL_DIV_CNTL (1<<18)
+#define HDMI_PLL_DIV_GATE (1<<19)
+
+#define PLL_DIV16_OFFSET 4 /* div2/2/4 */
+#define gp_PLL_TEST_DIV 0 /* div1 */
+#define PLL_DIV8_OFFSET 3
+
+#define Wr(addr, data) writel(data, addr)
+#define Rd(addr) readl(addr)
+
+static int sys_pll_init(sys_pll_set_t * sys_pll_set);
+static int sys_pll_test(sys_pll_set_t * sys_pll_set);
+static int sys_pll_test_all(sys_pll_cfg_t * sys_pll_cfg);
+static int fix_pll_test(void);
+static int ddr_pll_test(void);
+static int gp_pll_test(gp_pll_set_t * gp_pll);
+static int gp_pll_test_all(void);
+extern unsigned long clk_util_clk_msr(unsigned long clk_mux);
+
+#if 0
+static unsigned int pll_range[PLL_ENUM][2] = {
+ {101, 202}, //sys pll range
+ {303, 404}, //fix pll range
+ {505, 606}, //ddr pll range
+ {707, 808}, //hdmi pll range
+ {909, 999}, // pll range
+};
+
+static char pll_range_ind[PLL_ENUM][10] = {
+ "sys",
+ "fix",
+ "ddr",
+ "hdmi",
+ "gp",
+};
+#endif
+
+static void update_bits(size_t reg, size_t mask, unsigned int val)
+{
+ unsigned int tmp, orig;
+ orig = readl(reg);
+ tmp = orig & ~mask;
+ tmp |= val & mask;
+ writel(tmp, reg);
+}
+
+uint32_t sys_pll_clk[PLL_TEST_SYS_TOTAL] = {768, 888, 960, 1008, 1152, 1248, 1392, 1536};
+sys_pll_cfg_t sys_pll_cfg = {
+ .sys_pll[0] = {
+ .cpu_clk = 768,
+ .pll_cntl0 = 0x01f18420,
+ .pll_cntl1 = 0x01800000,
+ .pll_cntl2 = 0x00001100,
+ .pll_cntl3 = 0x10022300,
+ .pll_cntl4 = 0x00300000
+ },
+ .sys_pll[1] = {
+ .cpu_clk = 888,
+ .pll_cntl0 = 0x01f18425,
+ .pll_cntl1 = 0x01800000,
+ .pll_cntl2 = 0x00001100,
+ .pll_cntl3 = 0x10022300,
+ .pll_cntl4 = 0x00300000
+ },
+ .sys_pll[2] = {
+ .cpu_clk = 960,
+ .pll_cntl0 = 0x01f18428,
+ .pll_cntl1 = 0x01800000,
+ .pll_cntl2 = 0x00001100,
+ .pll_cntl3 = 0x10022300,
+ .pll_cntl4 = 0x00300000
+ },
+ .sys_pll[3] = {
+ .cpu_clk = 1008,
+ .pll_cntl0 = 0x01f1842A,
+ .pll_cntl1 = 0x01800000,
+ .pll_cntl2 = 0x00001100,
+ .pll_cntl3 = 0x10022300,
+ .pll_cntl4 = 0x00300000
+ },
+ .sys_pll[4] = {
+ .cpu_clk = 1152,
+ .pll_cntl0 = 0x01f18430,
+ .pll_cntl1 = 0x01800000,
+ .pll_cntl2 = 0x00001100,
+ .pll_cntl3 = 0x10022300,
+ .pll_cntl4 = 0x00300000
+ },
+ .sys_pll[5] = {
+ .cpu_clk = 1248,
+ .pll_cntl0 = 0x01f18434,
+ .pll_cntl1 = 0x01800000,
+ .pll_cntl2 = 0x00001100,
+ .pll_cntl3 = 0x10022300,
+ .pll_cntl4 = 0x00300000
+ },
+ .sys_pll[6] = {
+ .cpu_clk = 1392,
+ .pll_cntl0 = 0x01f1843A,
+ .pll_cntl1 = 0x01800000,
+ .pll_cntl2 = 0x00001100,
+ .pll_cntl3 = 0x10022300,
+ .pll_cntl4 = 0x00300000
+ },
+ .sys_pll[7] = {
+ .cpu_clk = 1536,
+ .pll_cntl0 = 0x01f18440,
+ .pll_cntl1 = 0x01800000,
+ .pll_cntl2 = 0x00001100,
+ .pll_cntl3 = 0x10022300,
+ .pll_cntl4 = 0x00300000
+ },
+};
+
+
+#define PLL_RATE(_rate, _m, _n, _od) \
+{ \
+ .rate = (_rate), \
+ .m = (_m), \
+ .n = (_n), \
+ .od = (_od), \
+}
+
+#define DDSPLL_RATE(_RATE, _CTS, _N) \
+{ \
+ .RATE = (_RATE), \
+ .CTS= (_CTS), \
+ .N = (_N), \
+}
+
+static gpll_rate_table_t gpll_tbl[] = {
+ PLL_RATE(864, 36, 1, 0), /*DCO=864M*/
+ PLL_RATE(960, 40, 1, 0), /*DCO=960M*/
+ PLL_RATE(1056, 44, 1, 0), /*DCO=1056M*/
+ PLL_RATE(1200, 50, 1, 0), /*DCO=1200M*/
+ PLL_RATE(1320, 55, 1, 0), /*DCO=1320M*/
+ PLL_RATE(1536, 64, 1, 0), /*DCO=1536M*/
+
+};
+
+static hifipll_rate_table_t hifipll_tbl[] = {
+ PLL_RATE(864, 36, 1, 0), /*DCO=864M*/
+ PLL_RATE(960, 40, 1, 0), /*DCO=960M*/
+ PLL_RATE(1056, 44, 1, 0), /*DCO=1056M*/
+ PLL_RATE(1200, 50, 1, 0), /*DCO=1200M*/
+ PLL_RATE(1320, 55, 1, 0), /*DCO=1320M*/
+ PLL_RATE(1536, 64, 1, 0), /*DCO=1536M*/
+};
+
+
+static ddspll_rate_table_t ddspll_tbl[] = {
+ DDSPLL_RATE(32, 1000, 64),
+ DDSPLL_RATE(50, 1000, 100),
+ DDSPLL_RATE(60, 82, 10),
+ DDSPLL_RATE(80, 625, 100),
+ DDSPLL_RATE(100, 5, 1),
+};
+
+
+
+static void pll_report(unsigned int flag, char * name) {
+ if (flag)
+ printf("%s pll test failed!\n", name);
+ else
+ printf("%s pll test pass!\n", name);
+ return;
+}
+
+static int clk_around(unsigned int clk, unsigned int cmp) {
+ if (((cmp-2) <= clk) && (clk <= (cmp+2)))
+ return 1;
+ else
+ return 0;
+}
+
+void clocks_set_sys_cpu_clk(uint32_t src) {
+ /*
+ * src
+ * 0: use 24M, 1: use SYS PLL
+ */
+ uint32_t control;
+ uint32_t dyn_pre_mux;
+ uint32_t dyn_post_mux;
+ uint32_t dyn_div;
+ //runtime_info_t info;
+
+ // Make sure not busy from last setting and we currently match the last setting
+ do {
+ control = readl(CPUCTRL_CLK_CTRL0);
+ } while( (control & (1 << 28)) );
+
+ control = control | (1 << 26);// Enable
+
+ dyn_pre_mux = 0; //use oscin
+ dyn_post_mux = 0;
+ dyn_div = 0;/* divide by 1 */
+
+ // Select Dynamic mux
+ if (src == 1) {
+ control = control | (1 << 11);
+ }
+ else {
+ control = control & ~(1 << 11);
+ if (control & (1 << 10)) {// if using Dyn mux1, set dyn mux 0
+ // Toggle bit[10] indicating a dynamic mux change
+ control = (control & ~((1 << 10) | (0x3f << 4) | (1 << 2) | (0x3 << 0)))
+ | ((0 << 10)
+ | (dyn_div << 4)
+ | (dyn_post_mux << 2)
+ | (dyn_pre_mux << 0));
+ } else {
+ // Toggle bit[10] indicating a dynamic mux change
+ control = (control & ~((1 << 10) | (0x3f << 20) | (1 << 18) | (0x3 << 16)))
+ | ((1 << 10)
+ | (dyn_div << 20)
+ | (dyn_post_mux << 18)
+ | (dyn_pre_mux << 16));
+ }
+ }
+
+ writel(control, CPUCTRL_CLK_CTRL0);
+
+ return;
+}
+
+static int sys_pll_init(sys_pll_set_t * sys_pll_set) {
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ do {
+ writel(sys_pll_set->pll_cntl1, ANACTRL_SYSPLL_CTRL1);
+ writel(sys_pll_set->pll_cntl2, ANACTRL_SYSPLL_CTRL2);
+ writel(sys_pll_set->pll_cntl3, ANACTRL_SYSPLL_CTRL3);
+ writel(sys_pll_set->pll_cntl4, ANACTRL_SYSPLL_CTRL4);
+ writel(sys_pll_set->pll_cntl0, ANACTRL_SYSPLL_CTRL0);
+ writel(sys_pll_set->pll_cntl0 | (1<<28) , ANACTRL_SYSPLL_CTRL0);
+ _udelay(10);
+ writel(sys_pll_set->pll_cntl0 | (1<<28) | (1<<26), ANACTRL_SYSPLL_CTRL0);
+ _udelay(40);
+ writel(sys_pll_set->pll_cntl2 | (1<<5), ANACTRL_SYSPLL_CTRL2);
+ _udelay(20);
+ } while((0 == ((Rd(ANACTRL_SYSPLL_STS) >> 31) & 0x1)) && (--lock_check));
+ if (lock_check != 0)
+ return 0;
+ else
+ return RET_PLL_LOCK_FAIL;
+}
+
+
+static int sys_pll_test_all(sys_pll_cfg_t * sys_pll_cfg) {
+ unsigned int i=0;
+ int ret=0;
+/*
+ for (i=0; i<(sizeof(sys_pll_cfg_t)/sizeof(sys_pll_set_t)); i++) {
+ ret += sys_pll_test(&(sys_pll_cfg->sys_pll[i]));
+ }
+*/
+ for (i=0; i<(sizeof(sys_pll_clk)/sizeof(uint32_t)); i++) {
+ sys_pll_cfg->sys_pll[0].cpu_clk = sys_pll_clk[i];
+ ret += sys_pll_test(&(sys_pll_cfg->sys_pll[i]));
+ }
+ return ret;
+}
+
+
+static int sys_pll_test(sys_pll_set_t * sys_pll_set) {
+ //unsigned int clk_msr_reg = 0;
+ unsigned int clk_msr_val = 0;
+ unsigned int sys_clk = 0;
+ //unsigned int sys_pll_cntl = 0;
+ int ret=0;
+
+ /* switch sys clk to oscillator */
+ clocks_set_sys_cpu_clk(0);
+
+ /* store current sys pll cntl */
+ sys_pll_set_t sys_pll;
+ sys_pll.pll_cntl0 = readl(ANACTRL_SYSPLL_CTRL0);
+ sys_pll.pll_cntl1 = readl(ANACTRL_SYSPLL_CTRL1);
+ sys_pll.pll_cntl2 = readl(ANACTRL_SYSPLL_CTRL2);
+ sys_pll.pll_cntl3 = readl(ANACTRL_SYSPLL_CTRL3);
+ sys_pll.pll_cntl4 = readl(ANACTRL_SYSPLL_CTRL4);
+
+ if (sys_pll_set->cpu_clk == 0) {
+ sys_clk = (24 * (sys_pll_set->pll_cntl0&0xFF)) / ((sys_pll_set->pll_cntl0>>10)&0x1F);
+ }
+
+ /* store CPU clk msr reg, restore it when test done */
+ //clk_msr_reg = readl(HHI_SYS_CPU_CLK_CNTL1);
+
+ /* enable CPU clk msr cntl bit */
+ //writel(clk_msr_reg | SYS_PLL_DIV16_CNTL | SYS_CLK_DIV16_CNTL, HHI_SYS_CPU_CLK_CNTL1);
+
+ //printf("HHI_SYS_CPU_CLK_CNTL: 0x%x\n", readl(HHI_SYS_CPU_CLK_CNTL));
+ //printf("HHI_SYS_CPU_CLK_CNTL1: 0x%x\n", readl(HHI_SYS_CPU_CLK_CNTL1));
+
+ if (0 == sys_pll_set->pll_cntl0) {
+ printf("sys pll cntl equal NULL, skip\n");
+ return -1;
+ }
+
+ /* test sys pll */
+ if (sys_pll_set->cpu_clk)
+ sys_clk = sys_pll_set->cpu_clk;
+
+ ret = sys_pll_init(sys_pll_set);
+ if (ret) {
+ printf("SYS pll lock Failed! - %4d MHz\n", sys_clk);
+ }
+ else {
+ printf("SYS pll lock OK! - %4d MHz. Div16 - %4d MHz. ", sys_clk, sys_clk>>PLL_DIV16_OFFSET);
+ clocks_set_sys_cpu_clk(1);
+ //open div16
+ writel(0x005012A2, CPUCTRL_CLK_CTRL1);
+ clk_msr_val = clk_util_clk_msr(45);
+ printf("CLKMSR(45) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, sys_clk>>SYS_PLL_TEST_DIV)) {
+ /* sys clk/pll div16 */
+ printf(": Match\n");
+ }
+ else {
+ ret = RET_CLK_NOT_MATCH;
+ printf(": MisMatch\n");
+ }
+ }
+
+ /* restore sys pll */
+ sys_pll_init(&sys_pll);
+ //clocks_set_sys_cpu_clk( 1, 0, 0, 0);
+ clocks_set_sys_cpu_clk(1);
+
+ /* restore clk msr reg */
+ //writel(clk_msr_reg, HHI_SYS_CPU_CLK_CNTL1);
+ return ret;
+}
+
+
+static int fix_pll_test(void) {
+ return 0;
+}
+
+static int ddr_pll_test(void) {
+ return 0;
+}
+
+static int hifi_pll_test(hifi_pll_set_t * hifi_pll) {
+ int ret=0;
+ unsigned int i=0, pll_clk=0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+
+ for (i=0; i<(sizeof(hifipll_tbl)/sizeof(hifipll_tbl[0])); i++) {
+ if ((hifi_pll->pll_cntl0 & 0xFF) == hifipll_tbl[i].m) {
+ pll_clk = hifipll_tbl[i].rate;
+ }
+ }
+
+ writel(hifi_pll->pll_cntl1, ANACTRL_HIFIPLL_CTRL1);
+ writel(hifi_pll->pll_cntl2, ANACTRL_HIFIPLL_CTRL2);
+ writel(hifi_pll->pll_cntl3, ANACTRL_HIFIPLL_CTRL3);
+ writel(hifi_pll->pll_cntl4, ANACTRL_HIFIPLL_CTRL4);
+ writel(hifi_pll->pll_cntl0, ANACTRL_HIFIPLL_CTRL0);
+ writel(hifi_pll->pll_cntl0 | (1<<28), ANACTRL_HIFIPLL_CTRL0);
+ _udelay(10);
+ writel(hifi_pll->pll_cntl0 | (1<<28) | (1<<26), ANACTRL_HIFIPLL_CTRL0);
+ _udelay(40);
+ writel(hifi_pll->pll_cntl2 | (1<<5), ANACTRL_HIFIPLL_CTRL2);
+ _udelay(20);
+
+ lock_check = PLL_LOCK_CHECK_MAX;
+ do {
+ update_bits(ANACTRL_HIFIPLL_CTRL0, 1<<26, 1 << 26);
+ _udelay(10);
+ update_bits(ANACTRL_HIFIPLL_CTRL0, 1<<26, 0);
+ _udelay(100);
+ //printf("hifi lock_check: %4d\n", lock_check);
+ } while((0 == ((Rd(ANACTRL_HIFIPLL_STS) >> 31) & 0x1)) && (--lock_check));
+ if (0 == lock_check) {
+ printf("HIFI pll lock Failed! - %4d MHz\n", pll_clk);
+ ret += RET_PLL_LOCK_FAIL;
+ }
+ else {
+ printf("HIFI pll lock OK! - %4d MHz. Div8 - %4d MHz. ", pll_clk, pll_clk>>PLL_DIV8_OFFSET);
+ Wr(CLKTREE_SPICC_CLK_CTRL, ((3<<9) | (1<<8) | (7<<0)));
+ //printf("CLKTREE_SPICC_CLK_CTRL: 0x%8x\n", readl(CLKTREE_SPICC_CLK_CTRL));
+ clk_msr_val = clk_util_clk_msr(16);
+ printf("CLKMSR(16) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk>>PLL_DIV8_OFFSET)) {
+ printf(": Match\n");
+ }
+ else {
+ printf(": MisMatch\n");
+ ret += RET_CLK_NOT_MATCH;
+ }
+ }
+
+ return ret;
+}
+
+static int hifi_pll_test_all(void){
+ unsigned int i=0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+ int ret=0;
+ unsigned int ctrl0 = 0;
+ for (i=0; i<(sizeof(hifipll_tbl)/sizeof(hifipll_tbl[0])); i++) {
+ ctrl0 = 0;
+ ctrl0 = ctrl0 | ((hifipll_tbl[i].m)<<0) | ((hifipll_tbl[i].n)<<10);
+ writel(0x01800000, ANACTRL_HIFIPLL_CTRL1);
+ writel(0x00001100, ANACTRL_HIFIPLL_CTRL2);
+ writel(0x10022300, ANACTRL_HIFIPLL_CTRL3);
+ writel(0x00300000, ANACTRL_HIFIPLL_CTRL4);
+ writel(0x01f18400 | ctrl0, ANACTRL_HIFIPLL_CTRL0);
+ writel(0x11f18400 | ctrl0, ANACTRL_HIFIPLL_CTRL0);
+ _udelay(10);
+ writel(0x15f18400 | ctrl0, ANACTRL_HIFIPLL_CTRL0);
+ _udelay(40);
+ //writel(0x00001140, ANACTRL_HIFIPLL_CTRL2);
+ writel(0x00001120, ANACTRL_HIFIPLL_CTRL2);
+ _udelay(20);
+/* dump paras */
+#if 0
+ printf("hifi %d:\n", hifipll_tbl[i].rate);
+ printf("HHI_HIFI_PLL_CNTL0: 0x%8x\n", readl(HHI_HIFI_PLL_CNTL0));
+ //printf("HHI_HIFI_PLL_CNTL2: 0x%8x\n", readl(HHI_HIFI_PLL_CNTL2));
+ //printf("HHI_HIFI_PLL_CNTL3: 0x%8x\n", readl(HHI_HIFI_PLL_CNTL3));
+ //printf("HHI_HIFI_PLL_CNTL4: 0x%8x\n", readl(HHI_HIFI_PLL_CNTL4));
+ //printf("HHI_HIFI_PLL_CNTL5: 0x%8x\n", readl(HHI_HIFI_PLL_CNTL5));
+#endif
+
+ lock_check = PLL_LOCK_CHECK_MAX;
+ do {
+ update_bits(ANACTRL_HIFIPLL_CTRL0, 1<<26, 1 << 26);
+ _udelay(10);
+ update_bits(ANACTRL_HIFIPLL_CTRL0, 1<<26, 0);
+ _udelay(100);
+ //printf("hifi lock_check: %4d\n", lock_check);
+ } while((0 == ((Rd(ANACTRL_HIFIPLL_STS) >> 31) & 0x1)) && (--lock_check));
+
+ if (0 == lock_check) {
+ printf("HIFI pll lock Failed! - %4d MHz\n", hifipll_tbl[i].rate);
+ ret += RET_PLL_LOCK_FAIL;
+ }
+ else {
+ printf("HIFI pll lock OK! - %4d MHz. Div8 - %4d MHz. ", hifipll_tbl[i].rate, hifipll_tbl[i].rate>>PLL_DIV8_OFFSET);
+ Wr(CLKTREE_SPICC_CLK_CTRL, ((3<<9) | (1<<8) | (7<<0)));
+ //printf("CLKTREE_SPICC_CLK_CTRL: 0x%8x\n", readl(CLKTREE_SPICC_CLK_CTRL));
+ clk_msr_val = clk_util_clk_msr(16);
+ printf("CLKMSR(16) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, hifipll_tbl[i].rate>>PLL_DIV8_OFFSET)) {
+ printf(": Match\n");
+ }
+ else {
+ printf(": MisMatch\n");
+ ret += RET_CLK_NOT_MATCH;
+ }
+ }
+ }
+
+ return ret;
+
+}
+
+static int gp_pll_test(gp_pll_set_t * gp_pll) {
+ int ret = 0;
+ unsigned int i = 0, pll_clk = 0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+
+ for (i=0; i<(sizeof(gpll_tbl)/sizeof(gpll_tbl[0])); i++) {
+ if ((gp_pll->pll_cntl0 & 0xFF) == gpll_tbl[i].m) {
+ pll_clk = gpll_tbl[i].rate;
+ }
+ }
+
+ writel(gp_pll->pll_cntl1, ANACTRL_GPPLL_CTRL1);
+ writel(gp_pll->pll_cntl2, ANACTRL_GPPLL_CTRL2);
+ writel(gp_pll->pll_cntl3, ANACTRL_GPPLL_CTRL3);
+ writel(gp_pll->pll_cntl4, ANACTRL_GPPLL_CTRL4);
+ writel(gp_pll->pll_cntl5, ANACTRL_GPPLL_CTRL5);
+ writel(gp_pll->pll_cntl0, ANACTRL_GPPLL_CTRL0);
+ writel(gp_pll->pll_cntl0 | (1<<28), ANACTRL_GPPLL_CTRL0);
+
+ _udelay(10);
+ writel(gp_pll->pll_cntl0 | (1<<28) | (1<<26), ANACTRL_GPPLL_CTRL0);
+ _udelay(40);
+ writel(gp_pll->pll_cntl2 | (1<<5), ANACTRL_GPPLL_CTRL2);
+ _udelay(20);
+
+ lock_check = PLL_LOCK_CHECK_MAX;
+ do {
+ update_bits(ANACTRL_GPPLL_CTRL0, 1<<26, 1 << 26);
+ _udelay(10);
+ update_bits(ANACTRL_GPPLL_CTRL0, 1<<26, 0);
+ _udelay(100);
+ //printf("gp lock_check: %4d\n", lock_check);
+ } while ((!((readl(ANACTRL_GPPLL_STS)>>31)&0x1)) && --lock_check);
+ if (0 == lock_check) {
+ printf("GP pll lock Failed! - %4d MHz\n", pll_clk);
+ ret = RET_PLL_LOCK_FAIL;
+ }
+ else {
+ printf("GP pll lock OK! - %4d MHz. Div8 - %4d MHz. ", pll_clk, pll_clk>>PLL_DIV8_OFFSET);
+ Wr(CLKTREE_SPICC_CLK_CTRL, ((4<<9) | (1<<8) | (7<<0)));
+ /* get gp_pll_clk */
+ clk_msr_val = clk_util_clk_msr(16);
+ printf("CLKMSR(16) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk>>PLL_DIV8_OFFSET)) {
+ printf(": Match\n");
+ }
+ else {
+ printf(": MisMatch\n");
+ ret += RET_CLK_NOT_MATCH;
+ }
+ }
+ return ret;
+}
+
+static int gp_pll_test_all(void) {
+ unsigned int i=0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+ int ret=0;
+ unsigned int ctrl0 = 0;
+
+ for (i=0; i<(sizeof(gpll_tbl)/sizeof(gpll_tbl[0])); i++) {
+ ctrl0 = 0;
+ ctrl0 = ctrl0 | ((gpll_tbl[i].m)<<0) | ((gpll_tbl[i].n)<<10);
+ writel(0x01800000, ANACTRL_GPPLL_CTRL1);
+ writel(0x00001100, ANACTRL_GPPLL_CTRL2);
+ writel(0x10022300, ANACTRL_GPPLL_CTRL3);
+ writel(0x00300000, ANACTRL_GPPLL_CTRL4);
+ writel(0x00088888, ANACTRL_GPPLL_CTRL5);
+ writel(0x01f18400 | ctrl0, ANACTRL_GPPLL_CTRL0);
+ writel(0x11f18400 | ctrl0, ANACTRL_GPPLL_CTRL0);
+ _udelay(10);
+ writel(0x15f18400 | ctrl0, ANACTRL_GPPLL_CTRL0);
+ _udelay(40);
+ writel(0x00001120, ANACTRL_GPPLL_CTRL2);
+ _udelay(20);
+
+/* dump paras */
+#if 0
+ printf("gp %d:\n", gpll0_tbl[i].rate);
+ printf("HHI_gp_PLL_CNTL0: 0x%8x\n", readl(HHI_gp_PLL_CNTL0));
+ //printf("HHI_gp_PLL_CNTL2: 0x%8x\n", readl(HHI_gp_PLL_CNTL2));
+ //printf("HHI_gp_PLL_CNTL3: 0x%8x\n", readl(HHI_gp_PLL_CNTL3));
+ //printf("HHI_gp_PLL_CNTL4: 0x%8x\n", readl(HHI_gp_PLL_CNTL4));
+ //printf("HHI_gp_PLL_CNTL5: 0x%8x\n", readl(HHI_gp_PLL_CNTL5));
+#endif
+
+ lock_check = PLL_LOCK_CHECK_MAX;
+ do {
+ update_bits(ANACTRL_GPPLL_CTRL0, 1<<26, 1 << 26);
+ _udelay(10);
+ update_bits(ANACTRL_GPPLL_CTRL0, 1<<26, 0);
+ _udelay(100);
+ //printf("gp lock_check: %4d\n", lock_check);
+ } while((0 == ((Rd(ANACTRL_GPPLL_STS) >> 31) & 0x1)) && (--lock_check));
+
+ if (0 == lock_check) {
+ printf("gp pll lock Failed! - %4d MHz\n", gpll_tbl[i].rate);
+ ret += RET_PLL_LOCK_FAIL;
+ }
+ else {
+ printf("gp pll lock OK! - %4d MHz. Div8 - %4d MHz. ", gpll_tbl[i].rate, gpll_tbl[i].rate>>PLL_DIV8_OFFSET);
+ Wr(CLKTREE_SPICC_CLK_CTRL, ((4<<9) | (1<<8) | (7<<0)));
+ //printf("CLKTREE_SPICC_CLK_CTRL: 0x%8x\n", readl(CLKTREE_SPICC_CLK_CTRL));
+ clk_msr_val = clk_util_clk_msr(16);
+ printf("CLKMSR(16) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, gpll_tbl[i].rate>>PLL_DIV8_OFFSET)) {
+ printf(": Match\n");
+ }
+ else {
+ printf(": MisMatch\n");
+ ret += RET_CLK_NOT_MATCH;
+ }
+ }
+ }
+
+ return ret;
+}
+
+static int dds_pll_test(dds_pll_set_t * dds_pll) {
+ int ret=0;
+ unsigned int i=0, pll_clk=0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+
+ for (i=0; i<(sizeof(ddspll_tbl)/sizeof(ddspll_tbl[0])); i++) {
+ if (((dds_pll->pll_cntl3)/(dds_pll->pll_cntl4)) == ((ddspll_tbl[i].CTS)/(ddspll_tbl[i].N))) {
+ pll_clk = ddspll_tbl[i].RATE;
+ }
+ }
+ do {
+ writel(dds_pll->misctop_cntl0, ANACTRL_MISCTOP_CTRL0);
+ writel(dds_pll->pll_cntl0, ANACTRL_AUDDDS_CTRL0);
+ writel(dds_pll->pll_cntl1, ANACTRL_AUDDDS_CTRL1);
+ writel(dds_pll->pll_cntl2, ANACTRL_AUDDDS_CTRL2);
+ writel(dds_pll->pll_cntl3, ANACTRL_AUDDDS_CTRL3);
+ writel(dds_pll->pll_cntl4, ANACTRL_AUDDDS_CTRL4);
+ writel((dds_pll->pll_cntl0 | (1<<29) | (1<<10) | (1<<11)) & ~(1<<28), ANACTRL_AUDDDS_CTRL0);
+
+ writel(dds_pll->pll_cntl1 | (1<<31), ANACTRL_AUDDDS_CTRL1);
+
+ //printf("gp lock_check: %4d\n", lock_check);
+ } while ((!((readl(ANACTRL_AUDDDS_STS)>>31)&0x1)) && --lock_check);
+ if (0 == lock_check) {
+ printf("dds pll lock Failed! - %4d MHz\n", pll_clk);
+ ret = RET_PLL_LOCK_FAIL;
+ }
+ else {
+ printf("dds pll lock OK! - %4d MHz.", pll_clk);
+ clk_msr_val = clk_util_clk_msr(44);
+ printf("CLKMSR(44) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk)) {
+ printf(": Match\n");
+ }
+ else {
+ printf(": MisMatch\n");
+ ret += RET_CLK_NOT_MATCH;
+ }
+ }
+ return ret;
+}
+
+static int dds_pll_test_all(void) {
+ unsigned int i=0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+ int ret=0;
+ //unsigned int ctrl0 = 0;
+
+ for (i=0; i<(sizeof(ddspll_tbl)/sizeof(ddspll_tbl[0])); i++) {
+ //ctrl0 = 0;
+ //ctrl0 = ctrl0 | ((gpll0_tbl[i].m)<<0) | ((gpll0_tbl[i].n)<<10);
+ do {
+ writel(0x4, ANACTRL_MISCTOP_CTRL0);
+ writel(0x50041340, ANACTRL_AUDDDS_CTRL0);
+ writel(0x0, ANACTRL_AUDDDS_CTRL1);
+ writel(0x0, ANACTRL_AUDDDS_CTRL2);
+ writel(ddspll_tbl[i].CTS, ANACTRL_AUDDDS_CTRL3);
+ writel(ddspll_tbl[i].N, ANACTRL_AUDDDS_CTRL4);
+ writel(0x60041f40, ANACTRL_AUDDDS_CTRL0);
+ writel(0x80000000, ANACTRL_AUDDDS_CTRL1);
+ } while((0 == ((Rd(ANACTRL_AUDDDS_STS) >> 31) & 0x1)) && (--lock_check));
+
+ if (0 == lock_check) {
+ printf("dds pll lock Failed! - %4d MHz\n", ddspll_tbl[i].RATE);
+ ret += RET_PLL_LOCK_FAIL;
+ }
+ else {
+ printf("dds pll lock OK! - %4d MHz.", ddspll_tbl[i].RATE);
+ //Wr(CLKTREE_SPICC_CLK_CTRL, ((4<<9) | (1<<8) | (7<<0)));
+ //printf("CLKTREE_SPICC_CLK_CTRL: 0x%8x\n", readl(CLKTREE_SPICC_CLK_CTRL));
+ clk_msr_val = clk_util_clk_msr(44);
+ printf("CLKMSR(44) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, ddspll_tbl[i].RATE)) {
+ printf(": Match\n");
+ }
+ else {
+ printf(": MisMatch\n");
+ ret += RET_CLK_NOT_MATCH;
+ }
+ }
+ }
+
+ return ret;
+
+}
+
+static int usbphy_pll_test(usbphy_pll_set_t * usbphy_pll) {
+ int ret = 0;
+ unsigned int pll_clk = 0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned long usbphy_base_cfg = 0xFE004000;
+
+ if ((usbphy_pll->pll_cntl0 & 0x1FF) == 0x14) {
+ pll_clk = 480;
+ }
+ else
+ {
+ printf("input frequency point is not support\n");
+ return -1;
+ }
+ writel(usbphy_pll->pll_cntl0, (usbphy_base_cfg + 0x40));
+ writel(usbphy_pll->pll_cntl1, (usbphy_base_cfg + 0x44));
+ writel(usbphy_pll->pll_cntl2, (usbphy_base_cfg + 0x48));
+
+ lock_check = PLL_LOCK_CHECK_MAX;
+ do {
+ update_bits((usbphy_base_cfg + 0x40), 1<<29, 1 << 29);
+ _udelay(10);
+ update_bits((usbphy_base_cfg + 0x40), 1<<29, 0);
+ _udelay(100);
+ //printf("ethphy lock_check: %4d\n", lock_check);
+ } while ((!((readl(usbphy_base_cfg + 0x40)>>31)&0x1)) && --lock_check);
+ if (0 == lock_check) {
+ printf("usbphy pll lock Failed! - %4d MHz\n", pll_clk);
+ ret = RET_PLL_LOCK_FAIL;
+ }
+ else{
+ printf("usbphy pll lock OK! - %4d MHz.\n", pll_clk);
+ }
+
+ return ret;
+}
+
+static int usbphy_pll_test_all(void) {
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ int ret=0;
+ unsigned long usbphy_base_cfg = 0xFE004000;
+
+ writel(0x09400414, (usbphy_base_cfg + 0x40));
+ writel(0x927e0000, (usbphy_base_cfg + 0x44));
+ writel(0xac5f69e5, (usbphy_base_cfg + 0x48));
+ writel(0x29400414, (usbphy_base_cfg + 0x40));
+ writel(0x09400414, (usbphy_base_cfg + 0x40));
+
+ do {
+ update_bits((usbphy_base_cfg + 0x40), 1<<29, 1 << 29);
+ _udelay(10);
+ update_bits((usbphy_base_cfg + 0x40), 1<<29, 0);
+ _udelay(100);
+ //printf("usbphy lock_check: %4d\n", lock_check);
+ } while ((!((readl(usbphy_base_cfg + 0x40)>>31)&0x1)) && --lock_check);
+
+ if (0 == lock_check) {
+ printf("usbphy pll lock Failed! - 480MHz\n");
+ ret += RET_PLL_LOCK_FAIL;
+ }
+ else {
+ printf("usbphy pll lock OK! - 480MHz.\n");
+ }
+
+ return ret;
+}
+
+
+static int ethphy_pll_test(ethphy_pll_set_t * ethphy_pll) {
+ int ret=0;
+ unsigned int pll_clk=0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+
+ if ((ethphy_pll->pll_cntl0 & 0x1FF) == 0xA) {
+ pll_clk = 500;
+ }
+ else
+ {
+ printf("input frequency point is not support\n");
+ return -1;
+ }
+
+ do {
+ writel(ethphy_pll->pll_cntl0 | 0x30000000, ETH_PLL_CTL0);
+ writel(ethphy_pll->pll_cntl1, ETH_PLL_CTL1);
+ writel(ethphy_pll->pll_cntl2, ETH_PLL_CTL2);
+ _udelay(150);
+ writel(ethphy_pll->pll_cntl0 | 0x10000000, ETH_PLL_CTL0);
+ _udelay(150);
+ } while ((!((readl(ETH_PLL_CTL0)>>30)&0x1))&& --lock_check);
+
+ if (0 == lock_check) {
+ printf("ETHPHY pll lock Failed! - %4d MHz\n", pll_clk);
+ ret = RET_PLL_LOCK_FAIL;
+ }
+ else {
+ printf("ETHPHY pll lock OK! - %4d MHz. ", pll_clk);
+ /* get ethphy_pll_clk */
+ clk_msr_val = clk_util_clk_msr(64)<<2;
+ printf("CLKMSR(64) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk)) {
+ printf(": Match\n");
+ }
+ else {
+ printf(": MisMatch\n");
+ ret = RET_CLK_NOT_MATCH;
+ }
+ }
+ return ret;
+}
+
+static int ethphy_pll_test_all(void) {
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+ int ret=0;
+
+ do {
+ writel(0x9c0040a | 0x30000000, ETH_PLL_CTL0);
+ writel(0x927e0000, ETH_PLL_CTL1);
+ writel(0xac5f49e5, ETH_PLL_CTL2);
+ writel(0x00000000, ETH_PLL_CTL3);
+ _udelay(150);
+ writel(0x9c0040a | 0x10000000, ETH_PLL_CTL0);
+ _udelay(150);
+ } while ((!((readl(ETH_PLL_CTL0)>>30)&0x1))&& --lock_check);
+
+ if (0 == lock_check) {
+ printf("ethphy pll lock Failed! - 500MHz\n");
+ ret += RET_PLL_LOCK_FAIL;
+ }
+ else {
+ printf("ethphy pll lock OK! - 500MHz. ");
+ /* get ethphy_pll_clk */
+ clk_msr_val = clk_util_clk_msr(64)<<2;
+ printf("CLKMSR(64) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, 500)) {
+ printf(": Match\n");
+ }
+ else {
+ printf(": MisMatch\n");
+ ret += RET_CLK_NOT_MATCH;
+ }
+ }
+
+ return ret;
+}
+
+
+static int pll_test_all(unsigned char * pll_list) {
+ int ret = 0;
+ unsigned char i=0;
+ for (i=0; i<PLL_ENUM; i++) {
+ switch (pll_list[i]) {
+ case PLL_SYS:
+ ret = sys_pll_test_all(&sys_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_SYS);
+ break;
+ case PLL_FIX:
+ ret = fix_pll_test();
+ pll_report(ret, STR_PLL_TEST_FIX);
+ break;
+ case PLL_DDR:
+ ret = ddr_pll_test();
+ pll_report(ret, STR_PLL_TEST_DDR);
+ break;
+ case PLL_HIFI:
+ ret = hifi_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_HIFI);
+ break;
+ case PLL_GP:
+ ret = gp_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_GP);
+ break;
+ case PLL_DDS:
+ ret = dds_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_DDS);
+ break;
+ case PLL_USBPHY:
+ ret = usbphy_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_USBPHY);
+ break;
+ case PLL_ETHPHY:
+ ret = ethphy_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_ETHPHY);
+ break;
+ default:
+ break;
+ }
+ }
+ return ret;
+}
+
+int pll_test(int argc, char * const argv[])
+{
+ int ret = 0;
+
+ sys_pll_set_t sys_pll_set = {0};
+ hifi_pll_set_t hifi_pll_set = {0};
+ gp_pll_set_t gp_pll_set = {0};
+ dds_pll_set_t dds_pll_set = {0};
+ usbphy_pll_set_t usbphy_pll_set = {0};
+ ethphy_pll_set_t ethphy_pll_set = {0};
+
+ unsigned char plls[PLL_ENUM] = {
+ PLL_SYS,
+ 0xff,// PLL_FIX, //0xff will skip this pll
+ 0xff,// PLL_DDR,
+ PLL_HIFI,
+ PLL_GP,
+ PLL_DDS,
+ PLL_USBPHY,
+ PLL_ETHPHY,
+ };
+
+ if (0 == strcmp(STR_PLL_TEST_ALL, argv[1])) {
+ printf("Test all plls\n");
+ pll_test_all(plls);
+ }
+ else if(0 == strcmp(STR_PLL_TEST_SYS, argv[1])) {
+ if (argc == 2) {
+ ret = sys_pll_test_all(&sys_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_SYS);
+ }
+ else if (argc != 7){
+ printf("%s pll test: args error\n", STR_PLL_TEST_SYS);
+ return -1;
+ }
+ else {
+ sys_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL, 16);
+ sys_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, 16);
+ sys_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, 16);
+ sys_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL, 16);
+ sys_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL, 16);
+ ret = sys_pll_test(&sys_pll_set);
+ pll_report(ret, STR_PLL_TEST_SYS);
+ }
+ }
+ else if (0 == strcmp(STR_PLL_TEST_HIFI, argv[1])) {
+ if (argc == 2) {
+ ret = hifi_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_HIFI);
+ }
+ else if (argc != 7){
+ printf("%s pll test: args error\n", STR_PLL_TEST_HIFI);
+ return -1;
+ }
+ else {
+ hifi_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL, 16);
+ hifi_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, 16);
+ hifi_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, 16);
+ hifi_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL, 16);
+ hifi_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL, 16);
+ ret = hifi_pll_test(&hifi_pll_set);
+ pll_report(ret, STR_PLL_TEST_HIFI);
+ }
+ }
+ else if (0 == strcmp(STR_PLL_TEST_GP, argv[1])) {
+ if (argc == 2) {
+ ret = gp_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_GP);
+ }
+ else if (argc != 8){
+ printf("%s pll test: args error\n", STR_PLL_TEST_GP);
+ return -1;
+ }
+ else {
+ gp_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL, 16);
+ gp_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, 16);
+ gp_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, 16);
+ gp_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL, 16);
+ gp_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL, 16);
+ gp_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL, 16);
+ ret = gp_pll_test(&gp_pll_set);
+ pll_report(ret, STR_PLL_TEST_GP);
+ }
+ }
+ else if (0 == strcmp(STR_PLL_TEST_DDR, argv[1])) {
+ printf("%s pll not support now\n", STR_PLL_TEST_DDR);
+ return -1;
+ }
+ else if (0 == strcmp(STR_PLL_TEST_FIX, argv[1])) {
+ printf("%s pll not support now\n", STR_PLL_TEST_FIX);
+ return -1;
+ }
+ else if (0 == strcmp(STR_PLL_TEST_DDS, argv[1])) {
+ if (argc == 2) {
+ ret = gp_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_DDS);
+ }
+ else if (argc != 8){
+ printf("%s pll test: args error\n", STR_PLL_TEST_DDS);
+ return -1;
+ }
+ else {
+ dds_pll_set.misctop_cntl0 = simple_strtoul(argv[2], NULL, 16);
+ dds_pll_set.pll_cntl0 = simple_strtoul(argv[3], NULL, 16);
+ dds_pll_set.pll_cntl1 = simple_strtoul(argv[4], NULL, 16);
+ dds_pll_set.pll_cntl2 = simple_strtoul(argv[5], NULL, 16);
+ dds_pll_set.pll_cntl3 = simple_strtoul(argv[6], NULL, 16);
+ dds_pll_set.pll_cntl4 = simple_strtoul(argv[7], NULL, 16);
+ ret = dds_pll_test(&dds_pll_set);
+ pll_report(ret, STR_PLL_TEST_DDS);
+ }
+ }
+ else if (0 == strcmp(STR_PLL_TEST_USBPHY, argv[1])) {
+ if (argc == 2) {
+ ret = usbphy_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_USBPHY);
+ }
+ else if (argc != 5){
+ printf("%s pll test: args error\n", STR_PLL_TEST_USBPHY);
+ return -1;
+ }
+ else {
+ usbphy_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL, 16);
+ usbphy_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, 16);
+ usbphy_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, 16);
+ ret = usbphy_pll_test(&usbphy_pll_set);
+ pll_report(ret, STR_PLL_TEST_USBPHY);
+ }
+ }
+ else if (0 == strcmp(STR_PLL_TEST_ETHPHY, argv[1])) {
+ if (argc == 2) {
+ ret = ethphy_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_ETHPHY);
+ }
+ else if (argc != 5){
+ printf("%s pll test: args error\n", STR_PLL_TEST_ETHPHY);
+ return -1;
+ }
+ else {
+ ethphy_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL, 16);
+ ethphy_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL, 16);
+ ethphy_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL, 16);
+ ret = ethphy_pll_test(ðphy_pll_set);
+ pll_report(ret, STR_PLL_TEST_ETHPHY);
+ }
+ }
+
+#if 0
+ unsigned char * pll_list = NULL;
+ switch (get_cpu_id().family_id) {
+ case MESON_CPU_MAJOR_ID_GXTVBB:
+ pll_list = gxtvbb_plls;
+ break;
+ case MESON_CPU_MAJOR_ID_GXL:
+ pll_list = gxl_plls;
+ break;
+ default:
+ printf("un-support chip\n");
+ break;
+ }
+ if (pll_list) {
+ return plltest(pll_list);
+ }
+#endif
+
+ return 0;
+}
diff --git a/arch/arm/mach-meson/c1/power_cal.c b/arch/arm/mach-meson/c1/power_cal.c
new file mode 100644
index 0000000..e4f9c53
--- /dev/null
+++ b/arch/arm/mach-meson/c1/power_cal.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/io.h>
+#include <amlogic/saradc.h>
+#include <asm/arch/mailbox.h>
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2))))
+#define vcck_adc_channel 0x4
+#define ee_adc_channel 0x5
+#define default_ref_val 1800
+
+extern const int pwm_cal_voltage_table[][2];
+extern const int pwm_cal_voltage_table_ee[][2];
+extern int pwm_cal_voltage_table_size;
+extern int pwm_cal_voltage_table_ee_size;
+
+
+enum pwm_id {
+ pwm_vcck = 0,
+ pwm_ee,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+int32_t aml_delt_get(int adc_val, unsigned int voltage)
+{
+ unsigned int adc_volt;
+ int32_t delt;
+ int32_t div = 10; /*10mv is min step*/
+
+ if (adc_val != -1) {
+ adc_volt = default_ref_val*adc_val/1024;
+ printf("aml pwm cal adc_val = %x, adc_voltage = %d, def_voltage = %d\n",
+ adc_val, adc_volt, voltage);
+ } else {
+ adc_volt = voltage;
+ printf("warning:aml pwm cal adc get voltage error\n");
+ return 0;
+ }
+ delt = voltage - adc_volt;
+ delt = delt / div;
+ return delt;
+}
+
+void aml_set_voltage(unsigned int id, unsigned int voltage, int delt)
+{
+ int to;
+
+ switch (id) {
+ case pwm_vcck:
+ for (to = 0; to < pwm_cal_voltage_table_size; to++) {
+ if (pwm_cal_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ to +=delt;
+ if (to >= pwm_cal_voltage_table_size) {
+ to = pwm_cal_voltage_table_size - 1;
+ }
+ /*vcck volt set by dvfs and avs*/
+ //writel(pwm_voltage_table[to][0], PWM_PWM_A_ADRESS);
+ _udelay_(200);
+ break;
+
+ case pwm_ee:
+ for (to = 0; to < pwm_cal_voltage_table_ee_size; to++) {
+ if (pwm_cal_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ to +=delt;
+ if (to >= pwm_cal_voltage_table_ee_size) {
+ to = pwm_cal_voltage_table_ee_size - 1;
+ }
+ printf("aml pwm cal before ee_address: %x, ee_voltage: %x\n",
+ AO_PWM_PWM_B, readl(AO_PWM_PWM_B));
+ writel(pwm_cal_voltage_table_ee[to][0],AO_PWM_PWM_B);
+ _udelay_(1000);
+ printf("aml pwm cal after ee_address: %x, ee_voltage: %x\n",
+ AO_PWM_PWM_B, readl(AO_PWM_PWM_B));
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+int aml_cal_pwm(unsigned int ee_voltage, unsigned int vcck_voltage)
+{
+ int32_t ee_delt, vcck_delt;
+ unsigned int ee_val, vcck_val;
+ int ret;
+
+ /*txlx vcck ch4,vddee ch5*/
+ ret = adc_channel_single_shot_mode("adc", ADC_MODE_HIGH_PRECISION,
+ vcck_adc_channel, &vcck_val);
+ if (ret)
+ return ret;
+
+ ret = adc_channel_single_shot_mode("adc", ADC_MODE_HIGH_PRECISION,
+ ee_adc_channel, &ee_val);
+ if (ret)
+ return ret;
+
+ vcck_delt = aml_delt_get(vcck_val, vcck_voltage);
+ ee_delt = aml_delt_get(ee_val, ee_voltage);
+ send_pwm_delt(vcck_delt, ee_delt);
+ aml_set_voltage(pwm_ee, AML_VDDEE_INIT_VOLTAGE, ee_delt);
+ //aml_set_voltage(pwm_vcck, CONFIG_VCCK_INIT_VOLTAGE, vcck_delt);
+ printf("aml board pwm vcck: %x, ee: %x\n", vcck_delt, ee_delt);
+
+ return 0;
+}
+
+void aml_pwm_cal_init(int mode)
+{
+ printf("aml pwm cal init\n");
+ aml_cal_pwm(AML_VDDEE_INIT_VOLTAGE, AML_VCCK_INIT_VOLTAGE);
+}
diff --git a/arch/arm/mach-meson/c1/power_gate.h b/arch/arm/mach-meson/c1/power_gate.h
new file mode 100644
index 0000000..9ca1a9d
--- /dev/null
+++ b/arch/arm/mach-meson/c1/power_gate.h
@@ -0,0 +1,1161 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __POWER_MGR_HEADER_
+#define __POWER_MGR_HEADER_
+
+#include <asm/arch/io.h>
+#include <common.h>
+//#include <asm/arch-gxb/io.h>
+/* #include <asm/arch-gxb/register.h> */
+#include <asm/arch/secure_apb.h>
+/* clock gate control */
+
+#define DEBUG_MASK 0
+
+#define SET_CLK_GATE_MASK(reg, mask) __raw_writel((__raw_readl(reg)|mask), reg)
+#define CLEAR_CLK_GATE_MASK(reg, mask) \
+ __raw_writel((__raw_readl(reg)&(~mask)), reg)
+#define CLK_GATE_ON(_MOD) do { \
+ if (DEBUG_MASK) \
+ printf("on reg %24s before read :0x%x : 0x%x\n",\
+ GCLK_NAME_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ SET_CLK_GATE_MASK(GCLK_REG_##_MOD, \
+ (unsigned int)GCLK_MASK_##_MOD); \
+ if (DEBUG_MASK) \
+ printf("on reg %24s after read :0x%x : 0x%x\n",\
+ GCLK_NAME_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ } while (0)
+
+#define CLK_GATE_OFF(_MOD) do { \
+ if (DEBUG_MASK) \
+ printf("off reg[ %24s ][0x%08x]before read:0x%08x:0x%08x\n",\
+ GCLK_NAME_##_MOD, (int)GCLK_MASK_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ CLEAR_CLK_GATE_MASK(GCLK_REG_##_MOD, (unsigned int)GCLK_MASK_##_MOD);\
+ if (DEBUG_MASK)\
+ printf("off reg[ %24s ][0x%08x] read after:0x%08x:0x%08x\n",\
+ GCLK_NAME_##_MOD, \
+ (int)GCLK_MASK_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ } while (0)
+
+#define IS_CLK_GATE_ON(_MOD) (__raw_readl(GCLK_REG_##_MOD) & (GCLK_MASK_##_MOD))
+#define GATE_INIT(_MOD) GCLK_ref[GCLK_IDX_##_MOD] = IS_CLK_GATE_ON(_MOD) ? 1 : 0
+
+#define GCLK_IDX_DDR 0
+#define GCLK_NAME_DDR "DDR"
+#define GCLK_DEV_DDR "CLKGATE_DDR"
+#define GCLK_REG_DDR (HHI_GCLK_MPEG0)
+#define GCLK_MASK_DDR (1<<0)
+
+#define GCLK_IDX_DOS 1
+#define GCLK_NAME_DOS "DOS"
+#define GCLK_DEV_DOS "CLKGATE_DOS"
+#define GCLK_REG_DOS (HHI_GCLK_MPEG0)
+#define GCLK_MASK_DOS (1<<1)
+
+#define GCLK_IDX_RESERVED0_0 2
+#define GCLK_NAME_RESERVED0_0 "RESERVED0_0"
+#define GCLK_DEV_RESERVED0_0 "CLKGATE_RESERVED0_0"
+#define GCLK_REG_RESERVED0_0 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_0 (1<<2)
+
+#define GCLK_IDX_RESERVED0_1 3
+#define GCLK_NAME_RESERVED0_1 "RESERVED0_1"
+#define GCLK_DEV_RESERVED0_1 "CLKGATE_RESERVED0_1"
+#define GCLK_REG_RESERVED0_1 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_1 (1<<3)
+
+/* #define GCLK_IDX_AHB_BRIDGE 4 */
+/* #define GCLK_NAME_AHB_BRIDGE "AHB_BRIDGE" */
+/* #define GCLK_DEV_AHB_BRIDGE "CLKGATE_AHB_BRIDGE" */
+/* #define GCLK_REG_AHB_BRIDGE (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_AHB_BRIDGE (1<<4) */
+
+#define GCLK_IDX_ISA 5
+#define GCLK_NAME_ISA "ISA"
+#define GCLK_DEV_ISA "CLKGATE_ISA"
+#define GCLK_REG_ISA (HHI_GCLK_MPEG0)
+#define GCLK_MASK_ISA (1<<5)
+
+/* NEW ADD */
+#define GCLK_IDX_PL310_CBUS 6
+#define GCLK_NAME_PL310_CBUS "PL310_CBUS"
+#define GCLK_DEV_PL310_CBUS "CLKGATE_PL310_CBUS"
+#define GCLK_REG_PL310_CBUS (HHI_GCLK_MPEG0)
+#define GCLK_MASK_PL310_CBUS (1<<6)
+
+#define GCLK_IDX_PERIPHS_TOP 7
+#define GCLK_NAME_PERIPHS_TOP "PERIPHS_TOP"
+#define GCLK_DEV_PERIPHS_TOP "CLKGATE_PERIPHS_TOP"
+#define GCLK_REG_PERIPHS_TOP (HHI_GCLK_MPEG0)
+#define GCLK_MASK_PERIPHS_TOP (1<<7)
+
+#define GCLK_IDX_SPICC 8
+#define GCLK_NAME_SPICC "SPICC"
+#define GCLK_DEV_SPICC "CLKGATE_SPICC"
+#define GCLK_REG_SPICC (HHI_GCLK_MPEG0)
+#define GCLK_MASK_SPICC (1<<8)
+
+#define GCLK_IDX_I2C 9
+#define GCLK_NAME_I2C "I2C"
+#define GCLK_DEV_I2C "CLKGATE_I2C"
+#define GCLK_REG_I2C (HHI_GCLK_MPEG0)
+#define GCLK_MASK_I2C (1<<9)
+
+#define GCLK_IDX_SAR_ADC 10
+#define GCLK_NAME_SAR_ADC "SAR_ADC"
+#define GCLK_DEV_SAR_ADC "CLKGATE_SAR_ADC"
+//#define GCLK_REG_SAR_ADC (HHI_SAR_CLK_CNTL) //no HHI_SAR_CLK_CNTL on TXL
+#define GCLK_REG_SAR_ADC (AO_SAR_CLK)
+#define GCLK_MASK_SAR_ADC (1<<8)
+
+#define GCLK_IDX_SMART_CARD_MPEG_DOMAIN 11
+#define GCLK_NAME_SMART_CARD_MPEG_DOMAIN "SMART_CARD_MPEG_DOMAIN"
+#define GCLK_DEV_SMART_CARD_MPEG_DOMAIN "CLKGATE_SMART_CARD_MPEG_DOMAIN"
+#define GCLK_REG_SMART_CARD_MPEG_DOMAIN (HHI_GCLK_MPEG0)
+#define GCLK_MASK_SMART_CARD_MPEG_DOMAIN (1<<11)
+
+#define GCLK_IDX_RANDOM_NUM_GEN 12
+#define GCLK_NAME_RANDOM_NUM_GEN "RANDOM_NUM_GEN"
+#define GCLK_DEV_RANDOM_NUM_GEN "CLKGATE_RANDOM_NUM_GEN"
+#define GCLK_REG_RANDOM_NUM_GEN (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RANDOM_NUM_GEN (1<<12)
+
+#define GCLK_IDX_UART0 13
+#define GCLK_NAME_UART0 "UART0"
+#define GCLK_DEV_UART0 "CLKGATE_UART0"
+#define GCLK_REG_UART0 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_UART0 (1<<13)
+
+/* gxb no this clock gate */
+/* #define GCLK_IDX_SDHC 14 */
+/* #define GCLK_NAME_SDHC "SDHC" */
+/* #define GCLK_DEV_SDHC "CLKGATE_SDHC" */
+/* #define GCLK_REG_SDHC (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_SDHC (1<<14) */
+
+#define GCLK_IDX_STREAM 15
+#define GCLK_NAME_STREAM "STREAM"
+#define GCLK_DEV_STREAM "CLKGATE_STREAM"
+#define GCLK_REG_STREAM (HHI_GCLK_MPEG0)
+#define GCLK_MASK_STREAM (1<<15)
+
+#define GCLK_IDX_ASYNC_FIFO 16
+#define GCLK_NAME_ASYNC_FIFO "ASYNC_FIFO"
+#define GCLK_DEV_ASYNC_FIFO "CLKGATE_ASYNC_FIFO"
+#define GCLK_REG_ASYNC_FIFO (HHI_GCLK_MPEG0)
+#define GCLK_MASK_ASYNC_FIFO (1<<16)
+
+/* gxb no this clock gate */
+/* #define GCLK_IDX_SDIO 17 */
+/* #define GCLK_NAME_SDIO "SDIO" */
+/* #define GCLK_DEV_SDIO "CLKGATE_SDIO" */
+/* #define GCLK_REG_SDIO (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_SDIO (1<<17) */
+
+/* gxb no this clock gate */
+/* #define GCLK_IDX_AUD_BUF 18 */
+/* #define GCLK_NAME_AUD_BUF "AUD_BUF" */
+/* #define GCLK_DEV_AUD_BUF "CLKGATE_AUD_BUF" */
+/* #define GCLK_REG_AUD_BUF (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_AUD_BUF (1<<18) */
+
+#define GCLK_IDX_HIU_PARSER 19
+#define GCLK_NAME_HIU_PARSER "HIU_PARSER"
+#define GCLK_DEV_HIU_PARSER "CLKGATE_HIU_PARSER"
+#define GCLK_REG_HIU_PARSER (HHI_GCLK_MPEG0)
+#define GCLK_MASK_HIU_PARSER (1<<19)
+
+#define GCLK_IDX_RESERVED0_2 20
+#define GCLK_NAME_RESERVED0_2 "RESERVED0_2"
+#define GCLK_DEV_RESERVED0_2 "CLKGATE_RESERVED0_2"
+#define GCLK_REG_RESERVED0_2 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_2 (1<<20)
+
+/* NEW ADD */
+#define GCLK_IDX_RESERVED0_3 21
+#define GCLK_NAME_RESERVED0_3 "RESERVED0_3 "
+#define GCLK_DEV_RESERVED0_3 "CLKGATE_RESERVED0_3 "
+#define GCLK_REG_RESERVED0_3 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_3 (1<<21)
+
+#define GCLK_IDX_RESERVED0_4 22
+#define GCLK_NAME_RESERVED0_4 "RESERVED0_4"
+#define GCLK_DEV_RESERVED0_4 "CLKGATE_RESERVED0_4"
+#define GCLK_REG_RESERVED0_4 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_4 (1<<22)
+
+#define GCLK_IDX_ASSIST_MISC 23
+#define GCLK_NAME_ASSIST_MISC "ASSIST_MISC"
+#define GCLK_DEV_ASSIST_MISC "CLKGATE_ASSIST_MISC"
+#define GCLK_REG_ASSIST_MISC (HHI_GCLK_MPEG0)
+#define GCLK_MASK_ASSIST_MISC (1<<23)
+
+
+#define GCLK_IDX_EMMC_A 24
+#define GCLK_NAME_EMMC_A "EMMC_A"
+#define GCLK_DEV_EMMC_A "CLKGATE_EMMC_A"
+#define GCLK_REG_EMMC_A (HHI_GCLK_MPEG0)
+#define GCLK_MASK_EMMC_A (1<<24)
+
+#define GCLK_IDX_EMMC_B 25
+#define GCLK_NAME_EMMC_B "EMMC_B"
+#define GCLK_DEV_EMMC_B "CLKGATE_EMMC_B"
+#define GCLK_REG_EMMC_B (HHI_GCLK_MPEG0)
+#define GCLK_MASK_EMMC_B (1<<25)
+
+#define GCLK_IDX_EMMC_C 26
+#define GCLK_NAME_EMMC_C "EMMC_C"
+#define GCLK_DEV_EMMC_C "CLKGATE_EMMC_C"
+#define GCLK_REG_EMMC_C (HHI_GCLK_MPEG0)
+#define GCLK_MASK_EMMC_C (1<<26)
+
+#define GCLK_IDX_RESERVED0_8 27
+#define GCLK_NAME_RESERVED0_8 "RESERVED0_8"
+#define GCLK_DEV_RESERVED0_8 "CLKGATE_RESERVED0_8"
+#define GCLK_REG_RESERVED0_8 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_8 (1<<27)
+
+#define GCLK_IDX_RESERVED0_9 28
+#define GCLK_NAME_RESERVED0_9 "RESERVED0_9"
+#define GCLK_DEV_RESERVED0_9 "CLKGATE_RESERVED0_9"
+#define GCLK_REG_RESERVED0_9 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_9 (1<<28)
+
+#define GCLK_IDX_RESERVED0_A 29
+#define GCLK_NAME_RESERVED0_A "RESERVED0_A"
+#define GCLK_DEV_RESERVED0_A "CLKGATE_RESERVED0_A"
+#define GCLK_REG_RESERVED0_A (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_A (1<<29)
+
+#define GCLK_IDX_SPI 30
+#define GCLK_NAME_SPI "SPI"
+#define GCLK_DEV_SPI "CLKGATE_SPI"
+#define GCLK_REG_SPI (HHI_GCLK_MPEG0)
+#define GCLK_MASK_SPI (1<<30)
+
+#define GCLK_IDX_RESERVED0_B 31
+#define GCLK_NAME_RESERVED0_B "RESERVED0_B"
+#define GCLK_DEV_RESERVED0_B "CLKGATE_RESERVED0_B"
+#define GCLK_REG_RESERVED0_B (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_B (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_RESERVED1_1 32
+#define GCLK_NAME_RESERVED1_1 "RESERVED1_1"
+#define GCLK_DEV_RESERVED1_1 "CLKGATE_RESERVED1_1"
+#define GCLK_REG_RESERVED1_1 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_1 (1<<0)
+
+
+#define GCLK_IDX_RESERVED1_2 33
+#define GCLK_NAME_RESERVED1_2 "RESERVED1_2"
+#define GCLK_DEV_RESERVED1_2 "CLKGATE_RESERVED1_2"
+#define GCLK_REG_RESERVED1_2 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_2 (1<<1)
+
+
+#define GCLK_IDX_AUD_IN 34
+#define GCLK_NAME_AUD_IN "AUD_IN"
+#define GCLK_DEV_AUD_IN "CLKGATE_AUD_IN"
+#define GCLK_REG_AUD_IN (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AUD_IN (1<<2)
+
+#define GCLK_IDX_ETHERNET 35
+#define GCLK_NAME_ETHERNET "ETHERNET"
+#define GCLK_DEV_ETHERNET "CLKGATE_ETHERNET"
+#define GCLK_REG_ETHERNET (HHI_GCLK_MPEG1)
+#define GCLK_MASK_ETHERNET (1<<3)
+
+/* g12a no reg */
+#if 0
+#define GCLK_IDX_ETH_CLK 145
+#define GCLK_NAME_ETH_CLK "ETH_CLK"
+#define GCLK_REG_ETH_CLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_ETH_CLK (1<<3)
+#endif
+
+#define GCLK_IDX_DEMUX 36
+#define GCLK_NAME_DEMUX "DEMUX"
+#define GCLK_DEV_DEMUX "CLKGATE_DEMUX"
+#define GCLK_REG_DEMUX (HHI_GCLK_MPEG1)
+#define GCLK_MASK_DEMUX (1<<4)
+
+#define GCLK_IDX_RESERVED1_3 37
+#define GCLK_NAME_RESERVED1_3 "RESERVED1_3"
+#define GCLK_DEV_RESERVED1_3 "CLKGATE_RESERVED1_3"
+#define GCLK_REG_RESERVED1_3 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_3 (1<<5)
+
+#define GCLK_IDX_AIU_AI_TOP_GLUE 38
+#define GCLK_NAME_AIU_AI_TOP_GLUE "AIU_AI_TOP_GLUE"
+#define GCLK_DEV_AIU_AI_TOP_GLUE "CLKGATE_AIU_AI_TOP_GLUE"
+#define GCLK_REG_AIU_AI_TOP_GLUE (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AI_TOP_GLUE (1<<6)
+
+#define GCLK_IDX_AIU_IEC958 39
+#define GCLK_NAME_AIU_IEC958 "AIU_IEC958"
+#define GCLK_DEV_AIU_IEC958 "CLKGATE_AIU_IEC958"
+#define GCLK_REG_AIU_IEC958 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_IEC958 (1<<7)
+
+#define GCLK_IDX_AIU_I2S_OUT 40
+#define GCLK_NAME_AIU_I2S_OUT "AIU_I2S_OUT"
+#define GCLK_DEV_AIU_I2S_OUT "CLKGATE_AIU_I2S_OUT"
+#define GCLK_REG_AIU_I2S_OUT (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_I2S_OUT (1<<8)
+
+#define GCLK_IDX_AIU_AMCLK_MEASURE 41
+#define GCLK_NAME_AIU_AMCLK_MEASURE "AIU_AMCLK_MEASURE"
+#define GCLK_DEV_AIU_AMCLK_MEASURE "CLKGATE_AIU_AMCLK_MEASURE"
+#define GCLK_REG_AIU_AMCLK_MEASURE (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AMCLK_MEASURE (1<<9)
+
+#define GCLK_IDX_AIU_AIFIFO2 42
+#define GCLK_NAME_AIU_AIFIFO2 "AIU_AIFIFO2"
+#define GCLK_DEV_AIU_AIFIFO2 "CLKGATE_AIU_AIFIFO2"
+#define GCLK_REG_AIU_AIFIFO2 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AIFIFO2 (1<<10)
+
+#define GCLK_IDX_AIU_AUD_MIXER 43
+#define GCLK_NAME_AIU_AUD_MIXER "AIU_AUD_MIXER"
+#define GCLK_DEV_AIU_AUD_MIXER "CLKGATE_AIU_AUD_MIXER"
+#define GCLK_REG_AIU_AUD_MIXER (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AUD_MIXER (1<<11)
+
+#define GCLK_IDX_AIU_MIXER_REG 44
+#define GCLK_NAME_AIU_MIXER_REG "AIU_MIXER_REG"
+#define GCLK_DEV_AIU_MIXER_REG "CLKGATE_AIU_MIXER_REG"
+#define GCLK_REG_AIU_MIXER_REG (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_MIXER_REG (1<<12)
+
+#define GCLK_IDX_AIU_ADC 45
+#define GCLK_NAME_AIU_ADC "AIU_ADC"
+#define GCLK_DEV_AIU_ADC "CLKGATE_AIU_ADC"
+#define GCLK_REG_AIU_ADC (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_ADC (1<<13)
+
+#define GCLK_IDX_BLK_MOV 46
+#define GCLK_NAME_BLK_MOV "BLK_MOV"
+#define GCLK_DEV_BLK_MOV "CLKGATE_BLK_MOV"
+#define GCLK_REG_BLK_MOV (HHI_GCLK_MPEG1)
+#define GCLK_MASK_BLK_MOV (1<<14)
+
+/* NEW ADD */
+#define GCLK_IDX_AIU_TOP_LEVEL 47
+#define GCLK_NAME_AIU_TOP_LEVEL "AIU_TOP_LEVEL"
+#define GCLK_DEV_AIU_TOP_LEVEL "CLKGATE_AIU_TOP_LEVEL"
+#define GCLK_REG_AIU_TOP_LEVEL (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_TOP_LEVEL (1<<15)
+
+//g12a no reg
+#if 0
+#define GCLK_NAME_PCM_MCLK "PCM_MCLK"
+#define GCLK_REG_PCM_MCLK (HHI_PCM_CLK_CNTL)
+#define GCLK_MASK_PCM_MCLK (1<<9)
+
+#define GCLK_NAME_PCM_SCLK "PCM_SCLK"
+#define GCLK_REG_PCM_SCLK (HHI_PCM_CLK_CNTL)
+#define GCLK_MASK_PCM_SCLK (1<<22)
+#endif
+
+#define GCLK_IDX_UART1 48
+#define GCLK_NAME_UART1 "UART1"
+#define GCLK_DEV_UART1 "CLKGATE_UART1"
+#define GCLK_REG_UART1 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_UART1 (1<<16)
+
+#define GCLK_IDX_RESERVED1_4 49
+#define GCLK_NAME_RESERVED1_4 "RESERVED1_4"
+#define GCLK_DEV_RESERVED1_4 "CLKGATE_RESERVED1_4"
+#define GCLK_REG_RESERVED1_4 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_4 (1<<17)
+
+/* NEW ADD */
+#define GCLK_IDX_RESERVED1_5 50
+#define GCLK_NAME_RESERVED1_5 "RESERVED1_5"
+#define GCLK_DEV_RESERVED1_5 "CLKGATE_RESERVED1_5"
+#define GCLK_REG_RESERVED1_5 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_5 (1<<18)
+
+#define GCLK_IDX_RESERVED1_6 51
+#define GCLK_NAME_RESERVED1_6 "RESERVED1_6"
+#define GCLK_DEV_RESERVED1_6 "CLKGATE_RESERVED1_6"
+#define GCLK_REG_RESERVED1_6 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_6 (1<<19)
+
+#define GCLK_IDX_GE2D 52
+#define GCLK_NAME_GE2D "GE2D"
+#define GCLK_DEV_GE2D "CLKGATE_GE2D"
+#define GCLK_REG_GE2D (HHI_GCLK_MPEG1)
+#define GCLK_MASK_GE2D (1<<20)
+
+#define GCLK_IDX_USB0 53
+#define GCLK_NAME_USB0 "USB0"
+#define GCLK_DEV_USB0 "CLKGATE_USB0"
+#define GCLK_REG_USB0 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_USB0 (1<<21)
+
+#define GCLK_IDX_USB1 54
+#define GCLK_NAME_USB1 "USB1"
+#define GCLK_DEV_USB1 "CLKGATE_USB1"
+#define GCLK_REG_USB1 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_USB1 (1<<22)
+
+#define GCLK_IDX_RESET 55
+#define GCLK_NAME_RESET "RESET"
+#define GCLK_DEV_RESET "CLKGATE_RESET"
+#define GCLK_REG_RESET (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESET (1<<23)
+
+#define GCLK_IDX_NAND_CLK 56
+#define GCLK_NAME_NAND_CLK "NAND CLK"
+#define GCLK_DEV_NAND_CLK "HHI_NAND_CLK"
+#define GCLK_REG_NAND_CLK (HHI_NAND_CLK_CNTL)
+#define GCLK_MASK_NAND_CLK (1<<7)
+
+#define GCLK_IDX_HIU_PARSER_TOP 57
+#define GCLK_NAME_HIU_PARSER_TOP "HIU_PARSER_TOP"
+#define GCLK_DEV_HIU_PARSER_TOP "CLKGATE_HIU_PARSER_TOP"
+#define GCLK_REG_HIU_PARSER_TOP (HHI_GCLK_MPEG1)
+#define GCLK_MASK_HIU_PARSER_TOP (1<<25)
+
+/* NEW ADD */
+
+/* g12a no reg */
+#if 0
+#define GCLK_NAME_USB_CLK "USB_CLK"
+#define GCLK_REG_USB_CLK (HHI_USB_CLK_CNTL)
+#define GCLK_MASK_USB_CLK (1<<9)
+#endif
+
+#define GCLK_IDX_USB_GENERAL 58
+#define GCLK_NAME_USB_GENERAL "USB_GENERAL"
+#define GCLK_DEV_USB_GENERAL "CLKGATE_USB_GENERAL"
+#define GCLK_REG_USB_GENERAL (HHI_GCLK_MPEG1)
+#define GCLK_MASK_USB_GENERAL (1<<26)
+
+#define GCLK_IDX_RESERVED1_7 59
+#define GCLK_NAME_RESERVED1_7 "RESERVED1_7"
+#define GCLK_DEV_RESERVED1_7 "CLKGATE_RESERVED1_7"
+#define GCLK_REG_RESERVED1_7 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_7 (1<<27)
+
+/* #define GCLK_IDX_VDIN1 60 */
+/* #define GCLK_NAME_VDIN1 "VDIN1" */
+/* #define GCLK_DEV_VDIN1 "CLKGATE_VDIN1" */
+/* #define GCLK_REG_VDIN1 (HHI_GCLK_MPEG1) */
+/* #define GCLK_MASK_VDIN1 (1<<28) */
+
+#define GCLK_IDX_AHB_ARB0 61
+#define GCLK_NAME_AHB_ARB0 "AHB_ARB0"
+#define GCLK_DEV_AHB_ARB0 "CLKGATE_AHB_ARB0"
+#define GCLK_REG_AHB_ARB0 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AHB_ARB0 (1<<29)
+
+#define GCLK_IDX_EFUSE 62
+#define GCLK_NAME_EFUSE "EFUSE"
+#define GCLK_DEV_EFUSE "CLKGATE_EFUSE"
+#define GCLK_REG_EFUSE (HHI_GCLK_MPEG1)
+#define GCLK_MASK_EFUSE (1<<30)
+
+#define GCLK_IDX_ROM_CLK 63
+#define GCLK_NAME_ROM_CLK "ROM_CLK"
+#define GCLK_DEV_ROM_CLK "CLKGATE_ROM_CLK"
+#define GCLK_REG_ROM_CLK (HHI_GCLK_MPEG1)
+#define GCLK_MASK_ROM_CLK (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_RESERVED2_0 64
+#define GCLK_NAME_RESERVED2_0 "RESERVED2_0"
+#define GCLK_DEV_RESERVED2_0 "CLKGATE_RESERVED2_0"
+#define GCLK_REG_RESERVED2_0 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_0 (1<<0)
+
+#define GCLK_IDX_AHB_DATA_BUS 65
+#define GCLK_NAME_AHB_DATA_BUS "AHB_DATA_BUS"
+#define GCLK_DEV_AHB_DATA_BUS "CLKGATE_AHB_DATA_BUS"
+#define GCLK_REG_AHB_DATA_BUS (HHI_GCLK_MPEG2)
+#define GCLK_MASK_AHB_DATA_BUS (1<<1)
+
+#define GCLK_IDX_AHB_CONTROL_BUS 66
+#define GCLK_NAME_AHB_CONTROL_BUS "AHB_CONTROL_BUS"
+#define GCLK_DEV_AHB_CONTROL_BUS "CLKGATE_AHB_CONTROL_BUS"
+#define GCLK_REG_AHB_CONTROL_BUS (HHI_GCLK_MPEG2)
+#define GCLK_MASK_AHB_CONTROL_BUS (1<<2)
+
+#define GCLK_IDX_HDMI_INTR_SYNC 67
+#define GCLK_NAME_HDMI_INTR_SYNC "HDMI_INTR_SYNC"
+#define GCLK_DEV_HDMI_INTR_SYNC "CLKGATE_HDMI_INTR_SYNC"
+#define GCLK_REG_HDMI_INTR_SYNC (HHI_GCLK_MPEG2)
+#define GCLK_MASK_HDMI_INTR_SYNC (1<<3)
+
+#define GCLK_IDX_HDMI_PCLK 68
+#define GCLK_NAME_HDMI_PCLK "HDMI_PCLK"
+#define GCLK_DEV_HDMI_PCLK "CLKGATE_HDMI_PCLK"
+#define GCLK_REG_HDMI_PCLK (HHI_GCLK_MPEG2)
+#define GCLK_MASK_HDMI_PCLK (1<<4)
+
+#define GCLK_IDX_PDM 69
+#define GCLK_NAME_PDM "PDM"
+#define GCLK_DEV_PDM "CLKGATE_PDM"
+#define GCLK_REG_PDM (HHI_GCLK_MPEG2)
+#define GCLK_MASK_PDM (1<<5)
+
+#define GCLK_IDX_BT656 70
+#define GCLK_NAME_BT656 "BT656"
+#define GCLK_DEV_BT656 "CLKGATE_BT656"
+#define GCLK_REG_BT656 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_BT656 (1<<6)
+
+#define GCLK_IDX_BT656_2 71
+#define GCLK_NAME_BT656_2 "BT656_2"
+#define GCLK_DEV_BT656_2 "CLKGATE_BT656_2"
+#define GCLK_REG_BT656_2 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_BT656_2 (1<<7)
+
+#define GCLK_IDX_MISC_USB1_TO_DDR 72
+#define GCLK_NAME_MISC_USB1_TO_DDR "MISC_USB1_TO_DDR"
+#define GCLK_DEV_MISC_USB1_TO_DDR "CLKGATE_MISC_USB1_TO_DDR"
+#define GCLK_REG_MISC_USB1_TO_DDR (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MISC_USB1_TO_DDR (1<<8)
+
+#define GCLK_IDX_MISC_USB0_TO_DDR 73
+#define GCLK_NAME_MISC_USB0_TO_DDR "MISC_USB0_TO_DDR"
+#define GCLK_DEV_MISC_USB0_TO_DDR "CLKGATE_MISC_USB0_TO_DDR"
+#define GCLK_REG_MISC_USB0_TO_DDR (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MISC_USB0_TO_DDR (1<<9)
+
+#define GCLK_IDX_RESERVED2_4 74
+#define GCLK_NAME_RESERVED2_4 "RESERVED2_4"
+#define GCLK_DEV_RESERVED2_4 "CLKGATE_RESERVED2_4"
+#define GCLK_REG_RESERVED2_4 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_4 (1<<10)
+
+#define GCLK_IDX_MMC_PCLK 75
+#define GCLK_NAME_MMC_PCLK "MMC_PCLK"
+#define GCLK_DEV_MMC_PCLK "CLKGATE_MMC_PCLK"
+#define GCLK_REG_MMC_PCLK (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MMC_PCLK (1<<11)
+
+//g12a no reg
+#if 0
+#define GCLK_NAME_MMC_A_PCLK "MMC_A_PCLK"
+#define GCLK_REG_MMC_A_PCLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_MMC_A_PCLK (1<<2)
+
+#define GCLK_NAME_MMC_B_PCLK "MMC_B_PCLK"
+#define GCLK_REG_MMC_B_PCLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_MMC_B_PCLK (1<<1)
+
+#define GCLK_NAME_MMC_C_PCLK "MMC_C_PCLK"
+#define GCLK_REG_MMC_C_PCLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_MMC_C_PCLK (1<<0)
+#endif
+
+#define GCLK_NAME_EMMC_A_CLK "EMMC_A_CLK"
+#define GCLK_REG_EMMC_A_CLK (HHI_SD_EMMC_CLK_CNTL)
+#define GCLK_MASK_EMMC_A_CLK (1<<7)
+
+#define GCLK_NAME_EMMC_B_CLK "EMMC_B_CLK"
+#define GCLK_REG_EMMC_B_CLK (HHI_SD_EMMC_CLK_CNTL)
+#define GCLK_MASK_EMMC_B_CLK (1<<23)
+
+#define GCLK_IDX_MISC_DVIN 76
+#define GCLK_NAME_MISC_DVIN "MISC_DVIN"
+#define GCLK_DEV_MISC_DVIN "CLKGATE_MISC_DVIN"
+#define GCLK_REG_MISC_DVIN (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MISC_DVIN (1<<12)
+
+#define GCLK_IDX_RESERVED2_5 77
+#define GCLK_NAME_RESERVED2_5 "RESERVED2_5"
+#define GCLK_DEV_RESERVED2_5 "CLKGATE_RESERVED2_5"
+#define GCLK_REG_RESERVED2_5 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_5 (1<<13)
+
+#define GCLK_IDX_RESERVED2_6 78
+#define GCLK_NAME_RESERVED2_6 "RESERVED2_6"
+#define GCLK_DEV_RESERVED2_6 "CLKGATE_RESERVED2_6"
+#define GCLK_REG_RESERVED2_6 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_6 (1<<14)
+
+#define GCLK_IDX_UART2 79
+#define GCLK_NAME_UART2 "UART2"
+#define GCLK_DEV_UART2 "CLKGATE_UART2"
+#define GCLK_REG_UART2 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_UART2 (1<<15)
+
+#define GCLK_IDX_RESERVED2_7 80
+#define GCLK_NAME_RESERVED2_7 "RESERVED2_7"
+#define GCLK_DEV_RESERVED2_7 "CLKGATE_RESERVED2_7"
+#define GCLK_REG_RESERVED2_7 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_7 (1<<16)
+
+#define GCLK_IDX_RESERVED2_8 81
+#define GCLK_NAME_RESERVED2_8 "RESERVED2_8"
+#define GCLK_DEV_RESERVED2_8 "CLKGATE_RESERVED2_8"
+#define GCLK_REG_RESERVED2_8 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_8 (1<<17)
+
+#define GCLK_IDX_RESERVED2_9 82
+#define GCLK_NAME_RESERVED2_9 "RESERVED2_9"
+#define GCLK_DEV_RESERVED2_9 "CLKGATE_RESERVED2_9"
+#define GCLK_REG_RESERVED2_9 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_9 (1<<18)
+
+#define GCLK_IDX_RESERVED2_A 83
+#define GCLK_NAME_RESERVED2_A "RESERVED2_A"
+#define GCLK_DEV_RESERVED2_A "CLKGATE_RESERVED2_A"
+#define GCLK_REG_RESERVED2_A (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_A (1<<19)
+
+#define GCLK_IDX_RESERVED2_B 84
+#define GCLK_NAME_RESERVED2_B "RESERVED2_B"
+#define GCLK_DEV_RESERVED2_B "CLKGATE_RESERVED2_B"
+#define GCLK_REG_RESERVED2_B (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_B (1<<20)
+
+#define GCLK_IDX_UART3 85
+#define GCLK_NAME_UART3 "UART3"
+#define GCLK_DEV_UART3 "CLKGATE_UART3"
+#define GCLK_REG_UART3 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_UART3 (1<<21)
+
+#define GCLK_IDX_SANA 86
+#define GCLK_NAME_SANA "SANA"
+#define GCLK_DEV_SANA "CLKGATE_SANA"
+#define GCLK_REG_SANA (HHI_GCLK_MPEG2)
+#define GCLK_MASK_SANA (1<<22)
+
+#define GCLK_IDX_RESERVED2_D 87
+#define GCLK_NAME_RESERVED2_D "RESERVED2_D"
+#define GCLK_DEV_RESERVED2_D "CLKGATE_RESERVED2_D"
+#define GCLK_REG_RESERVED2_D (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_D (1<<23)
+
+#define GCLK_IDX_RESERVED2_E 88
+#define GCLK_NAME_RESERVED2_E "RESERVED2_E"
+#define GCLK_DEV_RESERVED2_E "CLKGATE_RESERVED2_E"
+#define GCLK_REG_RESERVED2_E (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_E (1<<24)
+
+#define GCLK_IDX_VPU_INTR 89
+#define GCLK_NAME_VPU_INTR "VPU_INTR"
+#define GCLK_DEV_VPU_INTR "CLKGATE_VPU_INTR"
+#define GCLK_REG_VPU_INTR (HHI_GCLK_MPEG2)
+#define GCLK_MASK_VPU_INTR (1<<25)
+
+#define GCLK_IDX_SECURE_AHP_APB3 90
+#define GCLK_NAME_SECURE_AHP_APB3 "SECURE_AHP_APB3"
+#define GCLK_DEV_SECURE_AHP_APB3 "CLKGATE_SECURE_AHP_APB3"
+#define GCLK_REG_SECURE_AHP_APB3 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_SECURE_AHP_APB3 (1<<26)
+
+#define GCLK_IDX_RESERVED2_F 91
+#define GCLK_NAME_RESERVED2_F "RESERVED2_F"
+#define GCLK_DEV_RESERVED2_F "CLKGATE_RESERVED2_F"
+#define GCLK_REG_RESERVED2_F (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_F (1<<27)
+
+#define GCLK_IDX_RESERVED2_10 92
+#define GCLK_NAME_RESERVED2_10 "RESERVED2_10"
+#define GCLK_DEV_RESERVED2_10 "CLKGATE_RESERVED2_10"
+#define GCLK_REG_RESERVED2_10 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_10 (1<<28)
+
+#define GCLK_IDX_CLK81_TO_A9 93
+#define GCLK_NAME_CLK81_TO_A9 "CLK81_TO_A9"
+#define GCLK_DEV_CLK81_TO_A9 "CLKGATE_CLK81_TO_A9"
+#define GCLK_REG_CLK81_TO_A9 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_CLK81_TO_A9 (1<<29)
+
+#define GCLK_IDX_GIC 94
+#define GCLK_NAME_GIC "GIC"
+#define GCLK_DEV_GIC "CLKGATE_GIC"
+#define GCLK_REG_GIC (HHI_GCLK_MPEG2)
+#define GCLK_MASK_GIC (1<<30)
+
+#define GCLK_IDX_RESERVED2_12 95
+#define GCLK_NAME_RESERVED2_12 "RESERVED2_12"
+#define GCLK_DEV_RESERVED2_12 "CLKGATE_RESERVED2_12"
+#define GCLK_REG_RESERVED2_12 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_12 (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_RESERVED3_0 96
+#define GCLK_NAME_RESERVED3_0 "RESERVED3_0"
+#define GCLK_DEV_RESERVED3_0 "CLKGATE_RESERVED3_0"
+#define GCLK_REG_RESERVED3_0 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_0 (1<<0)
+
+#define GCLK_IDX_VCLK2_VENCI 97
+#define GCLK_NAME_VCLK2_VENCI "VCLK2_VENCI"
+#define GCLK_DEV_VCLK2_VENCI "CLKGATE_VCLK2_VENCI"
+#define GCLK_REG_VCLK2_VENCI (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCI (1<<1)
+
+#define GCLK_IDX_VCLK2_VENCI1 98
+#define GCLK_NAME_VCLK2_VENCI1 "VCLK2_VENCI1"
+#define GCLK_DEV_VCLK2_VENCI1 "CLKGATE_VCLK2_VENCI1"
+#define GCLK_REG_VCLK2_VENCI1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCI1 (1<<2)
+
+#define GCLK_IDX_VCLK2_VENCP 99
+#define GCLK_NAME_VCLK2_VENCP "VCLK2_VENCP"
+#define GCLK_DEV_VCLK2_VENCP "CLKGATE_VCLK2_VENCP"
+#define GCLK_REG_VCLK2_VENCP (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCP (1<<3)
+
+#define GCLK_IDX_VCLK2_VENCP1 100
+#define GCLK_NAME_VCLK2_VENCP1 "VCLK2_VENCP1"
+#define GCLK_DEV_VCLK2_VENCP1 "CLKGATE_VCLK2_VENCP1"
+#define GCLK_REG_VCLK2_VENCP1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCP1 (1<<4)
+
+#define GCLK_IDX_VCLK2_VENCT 101
+#define GCLK_NAME_VCLK2_VENCT "VCLK2_VENCT"
+#define GCLK_DEV_VCLK2_VENCT "CLKGATE_VCLK2_VENCT"
+#define GCLK_REG_VCLK2_VENCT (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCT (1<<5)
+
+#define GCLK_IDX_VCLK2_VENCT1 102
+#define GCLK_NAME_VCLK2_VENCT1 "VCLK2_VENCT1"
+#define GCLK_DEV_VCLK2_VENCT1 "CLKGATE_VCLK2_VENCT1"
+#define GCLK_REG_VCLK2_VENCT1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCT1 (1<<6)
+
+#define GCLK_IDX_VCLK2_OTHER 103
+#define GCLK_NAME_VCLK2_OTHER "VCLK2_OTHER"
+#define GCLK_DEV_VCLK2_OTHER "CLKGATE_VCLK2_OTHER"
+#define GCLK_REG_VCLK2_OTHER (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_OTHER (1<<7)
+
+#define GCLK_IDX_VCLK2_ENCI 104
+#define GCLK_NAME_VCLK2_ENCI "VCLK2_ENCI"
+#define GCLK_DEV_VCLK2_ENCI "CLKGATE_VCLK2_ENCI"
+#define GCLK_REG_VCLK2_ENCI (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCI (1<<8)
+
+#define GCLK_IDX_VCLK2_ENCP 105
+#define GCLK_NAME_VCLK2_ENCP "VCLK2_ENCP"
+#define GCLK_DEV_VCLK2_ENCP "CLKGATE_VCLK2_ENCP"
+#define GCLK_REG_VCLK2_ENCP (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCP (1<<9)
+
+#define GCLK_IDX_DAC_CLK 106
+#define GCLK_NAME_DAC_CLK "DAC_CLK"
+#define GCLK_DEV_DAC_CLK "CLKGATE_DAC_CLK"
+#define GCLK_REG_DAC_CLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_DAC_CLK (1<<10)
+
+#define GCLK_IDX_RESERVED3_1 107
+#define GCLK_NAME_RESERVED3_1 "RESERVED3_1"
+#define GCLK_DEV_RESERVED3_1 "CLKGATE_RESERVED3_1"
+#define GCLK_REG_RESERVED3_1 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_1 (1<<11)
+
+#define GCLK_IDX_RESERVED3_2 108
+#define GCLK_NAME_RESERVED3_2 "RESERVED3_2"
+#define GCLK_DEV_RESERVED3_2 "CLKGATE_RESERVED3_2"
+#define GCLK_REG_RESERVED3_2 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_2 (1<<12)
+
+#define GCLK_IDX_RESERVED3_3 109
+#define GCLK_NAME_RESERVED3_3 "RESERVED3_3"
+#define GCLK_DEV_RESERVED3_3 "CLKGATE_RESERVED3_3"
+#define GCLK_REG_RESERVED3_3 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_3 (1<<13)
+
+#define GCLK_IDX_AIU_AOCLK 110
+#define GCLK_NAME_AIU_AOCLK "AIU_AOCLK"
+#define GCLK_DEV_AIU_AOCLK "CLKGATE_AIU_AOCLK"
+#define GCLK_REG_AIU_AOCLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_AIU_AOCLK (1<<14)
+
+#define GCLK_IDX_RESERVED3_4 111
+#define GCLK_NAME_RESERVED3_4 "RESERVED3_4"
+#define GCLK_DEV_RESERVED3_4 "CLKGATE_RESERVED3_4"
+#define GCLK_REG_RESERVED3_4 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_4 (1<<15)
+
+#define GCLK_IDX_AIU_ICE958_AMCLK 112
+#define GCLK_NAME_AIU_ICE958_AMCLK "AIU_ICE958_AMCLK"
+#define GCLK_DEV_AIU_ICE958_AMCLK "CLKGATE_AIU_ICE958_AMCLK"
+#define GCLK_REG_AIU_ICE958_AMCLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_AIU_ICE958_AMCLK (1<<16)
+
+#define GCLK_IDX_RESERVED3_5 113
+#define GCLK_NAME_RESERVED3_5 "RESERVED3_5"
+#define GCLK_DEV_RESERVED3_5 "CLKGATE_RESERVED3_5"
+#define GCLK_REG_RESERVED3_5 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_5 (1<<17)
+
+#define GCLK_IDX_RESERVED3_6 114
+#define GCLK_NAME_RESERVED3_6 "RESERVED3_6"
+#define GCLK_DEV_RESERVED3_6 "CLKGATE_RESERVED3_6"
+#define GCLK_REG_RESERVED3_6 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_6 (1<<18)
+
+#define GCLK_IDX_RESERVED3_7 115
+#define GCLK_NAME_RESERVED3_7 "RESERVED3_7"
+#define GCLK_DEV_RESERVED3_7 "CLKGATE_RESERVED3_7"
+#define GCLK_REG_RESERVED3_7 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_7 (1<<19)
+
+#define GCLK_IDX_ENC480P 116
+#define GCLK_NAME_ENC480P "ENC480P"
+#define GCLK_DEV_ENC480P "CLKGATE_ENC480P"
+#define GCLK_REG_ENC480P (HHI_GCLK_OTHER)
+#define GCLK_MASK_ENC480P (1<<20)
+
+#define GCLK_IDX_RANDOM_NUM_GEN1 117
+#define GCLK_NAME_RANDOM_NUM_GEN1 "RANDOM_NUM_GEN1"
+#define GCLK_DEV_RANDOM_NUM_GEN1 "CLKGATE_RANDOM_NUM_GEN1"
+#define GCLK_REG_RANDOM_NUM_GEN1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RANDOM_NUM_GEN1 (1<<21)
+
+#define GCLK_IDX_VCLK2_ENCT 118
+#define GCLK_NAME_VCLK2_ENCT "GCLK_VENCL_INT"
+#define GCLK_DEV_VCLK2_ENCT "CLKGATE_GCLK_VENCL_INT"
+#define GCLK_REG_VCLK2_ENCT (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCT (1<<22)
+
+#define GCLK_IDX_VCLK2_ENCL 119
+#define GCLK_NAME_VCLK2_ENCL "VLKC2_ENCL"
+#define GCLK_DEV_VCLK2_ENCL "CLKGATE_VCLK2_ENCL"
+#define GCLK_REG_VCLK2_ENCL (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCL (1<<23)
+
+#define GCLK_IDX_MMC_CLK 120
+#define GCLK_NAME_MMC_CLK "MMC_CLK"
+#define GCLK_DEV_MMC_CLK "CLKGATE_MMC_CLK"
+#define GCLK_REG_MMC_CLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_MMC_CLK (1<<24)
+
+#define GCLK_IDX_VCLK2_VENCL 121
+#define GCLK_NAME_VCLK2_VENCL "VCLK2_VENCL"
+#define GCLK_DEV_VCLK2_VENCL "CLKGATE_VCLK2_VENCL"
+#define GCLK_REG_VCLK2_VENCL (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCL (1<<25)
+
+#define GCLK_IDX_VCLK2_OTHER1 122
+#define GCLK_NAME_VCLK2_OTHER1 "VCLK2_OTHER1"
+#define GCLK_DEV_VCLK2_OTHER1 "CLKGATE_VCLK2_OTHER1"
+#define GCLK_REG_VCLK2_OTHER1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_OTHER1 (1<<26)
+
+#define GCLK_IDX_RESERVED3_9 123
+#define GCLK_NAME_RESERVED3_9 "RESERVED3_9"
+#define GCLK_DEV_RESERVED3_9 "CLKGATE_RESERVED3_9"
+#define GCLK_REG_RESERVED3_9 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_9 (1<<27)
+
+#define GCLK_IDX_RESERVED3_A 124
+#define GCLK_NAME_RESERVED3_A "RESERVED3_A"
+#define GCLK_DEV_RESERVED3_A "CLKGATE_RESERVED3_A"
+#define GCLK_REG_RESERVED3_A (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_A (1<<28)
+
+#define GCLK_IDX_RESERVED3_B 125
+#define GCLK_NAME_RESERVED3_B "RESERVED3_B"
+#define GCLK_DEV_RESERVED3_B "CLKGATE_RESERVED3_B"
+#define GCLK_REG_RESERVED3_B (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_B (1<<29)
+
+#define GCLK_IDX_RESERVED3_C 126
+#define GCLK_NAME_RESERVED3_C "RESERVED3_C"
+#define GCLK_DEV_RESERVED3_C "CLKGATE_RESERVED3_C"
+#define GCLK_REG_RESERVED3_C (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_C (1<<30)
+
+#define GCLK_IDX_EDP_CLK 127
+#define GCLK_NAME_EDP_CLK "EDP_CLK"
+#define GCLK_DEV_EDP_CLK "CLKGATE_EDP_CLK"
+#define GCLK_REG_EDP_CLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_EDP_CLK (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_MEDIA_CPU 128
+#define GCLK_NAME_MEDIA_CPU "MEDIA_CPU"
+#define GCLK_DEV_MEDIA_CPU "CLKGATE_MEDIA_CPU"
+#define GCLK_REG_MEDIA_CPU (HHI_GCLK_AO)
+#define GCLK_MASK_MEDIA_CPU (1<<0)
+
+#define GCLK_IDX_AHB_SRAM 129
+#define GCLK_NAME_AHB_SRAM "AHB_SRAM"
+#define GCLK_DEV_AHB_SRAM "CLKGATE_AHB_SRAM"
+#define GCLK_REG_AHB_SRAM (HHI_GCLK_AO)
+#define GCLK_MASK_AHB_SRAM (1<<1)
+
+#define GCLK_IDX_AHB_BUS 130
+#define GCLK_NAME_AHB_BUS "AHB_BUS"
+#define GCLK_DEV_AHB_BUS "CLKGATE_AHB_BUS"
+#define GCLK_REG_AHB_BUS (HHI_GCLK_AO)
+#define GCLK_MASK_AHB_BUS (1<<2)
+
+#define GCLK_IDX_AO_REGS 131
+#define GCLK_NAME_AO_REGS "AO_REGS"
+#define GCLK_DEV_AO_REGS "CLKGATE_AO_REGS"
+#define GCLK_REG_AO_REGS (HHI_GCLK_AO)
+#define GCLK_MASK_AO_REGS (1<<3)
+
+#define GCLK_NAME_I2C_AO "I2C_AO"
+#define GCLK_REG_I2C_AO (HHI_GCLK_AO)
+#define GCLK_MASK_I2C_AO (1<<4)
+
+
+#define GCLK_IDX_CTS_ENCI 132
+#define GCLK_NAME_CTS_ENCI "CTS_ENCI"
+#define GCLK_DEV_CTS_ENCI "CLKGATE_CTS_ENCI"
+#define GCLK_REG_CTS_ENCI (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCI (1<<0)
+
+#define GCLK_IDX_CTS_ENCT 133
+#define GCLK_NAME_CTS_ENCT "CTS_ENCT"
+#define GCLK_DEV_CTS_ENCT "CLKGATE_CTS_ENCT"
+#define GCLK_REG_CTS_ENCT (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCT (1<<1)
+
+#define GCLK_IDX_CTS_ENCP 134
+#define GCLK_NAME_CTS_ENCP "CTS_ENCP"
+#define GCLK_DEV_CTS_ENCP "CLKGATE_CTS_ENCP"
+#define GCLK_REG_CTS_ENCP (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCP (1<<2)
+
+#define GCLK_IDX_CTS_ENCL 135
+#define GCLK_NAME_CTS_ENCL "CTS_ENCL"
+#define GCLK_DEV_CTS_ENCL "CLKGATE_CTS_ENCL"
+#define GCLK_REG_CTS_ENCL (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCL (1<<3)
+
+#define GCLK_IDX_CTS_VDAC 136
+#define GCLK_NAME_CTS_VDAC "CTS_VDAC"
+#define GCLK_DEV_CTS_VDAC "CLKGATE_CTS_VDAC"
+#define GCLK_REG_CTS_VDAC (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_VDAC (1<<4)
+
+#define GCLK_IDX_CTS_HDMI_TX_PIXEL 137
+#define GCLK_NAME_CTS_HDMI_TX_PIXEL "CTS_HDMI_TX_PIXEL"
+#define GCLK_DEV_CTS_HDMI_TX_PIXEL "CLKGATE_CTS_HDMI_TX_PIXEL"
+#define GCLK_REG_CTS_HDMI_TX_PIXEL (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_HDMI_TX_PIXEL (1<<5)
+
+#define GCLK_IDX_AUD 138
+#define GCLK_NAME_AUD "AUD"
+#define GCLK_DEV_AUD "CLKGATE_AUD"
+#define GCLK_REG_AUD (HHI_AUD_CLK_CNTL)
+#define GCLK_MASK_AUD (1<<23)
+
+
+#define GCLK_IDX_AUD2 138
+#define GCLK_NAME_AUD2 "AUD2"
+#define GCLK_DEV_AUD2 "CLKGATE_AUD2"
+#define GCLK_REG_AUD2 (HHI_AUD_CLK_CNTL)
+#define GCLK_MASK_AUD2 (1<<8)
+
+
+#define GCLK_NAME_AUD_CLK_2 "AUD_CLK_2"
+#define GCLK_REG_AUD_CLK_2 (HHI_AUD_CLK_CNTL2)
+#define GCLK_MASK_AUD_CLK_2 (1<<8)
+
+#define GCLK_IDX_AUD_CLK_3 138
+#define GCLK_NAME_AUD_CLK_3 "AUD_CLK"
+#define GCLK_DEV_AUD_CLK_3 "CLKGATE_AUD_CLK"
+#define GCLK_REG_AUD_CLK_3 (HHI_AUD_CLK_CNTL3)
+#define GCLK_MASK_AUD_CLK_3 (1<<16)
+
+#define GCLK_IDX_LCD_AN_PHY2 139
+#define GCLK_NAME_LCD_AN_PHY2 "LCD_AN_PHY2"
+#define GCLK_DEV_LCD_AN_PHY2 "CLKGATE_LCD_AN_PHY2"
+#define GCLK_REG_LCD_AN_PHY2 (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_LCD_AN_PHY2 (1<<7)
+
+#define GCLK_IDX_LCD_AN_PHY3 140
+#define GCLK_NAME_LCD_AN_PHY3 "LCD_AN_PHY3"
+#define GCLK_DEV_LCD_AN_PHY3 "CLKGATE_LCD_AN_PHY3"
+#define GCLK_REG_LCD_AN_PHY3 (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_LCD_AN_PHY3 (1<<6)
+
+#define GCLK_NAME_ATV_DEMO_VDAC "ATV_DEMO_VDAC"
+#define GCLK_REG_ATV_DEMO_VDAC (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_ATV_DEMO_VDAC (1<<8)
+
+#define GCLK_IDX_HDMI_PLL_CNTL 142
+#define GCLK_NAME_HDMI_PLL_CNTL "HDMI_PLL_CNTL"
+#define GCLK_DEV_HDMI_PLL_CNTL "GATE_HDMI_PLL_CNTL"
+#define GCLK_REG_HDMI_PLL_CNTL (HHI_HDMI_PLL_CNTL)
+#define GCLK_MASK_HDMI_PLL_CNTL (1<<30)
+
+#define GCLK_NAME_HDMITX_CLK "HDMITX_CLK"
+#define GCLK_REG_HDMITX_CLK (HHI_HDMI_CLK_CNTL)
+#define GCLK_MASK_HDMITX_CLK (1<<8)
+
+
+#define GCLK_NAME_HDMITX_CLK "HDMITX_CLK"
+#define GCLK_REG_HDMITX_CLK (HHI_HDMI_CLK_CNTL)
+#define GCLK_MASK_HDMITX_CLK (1<<8)
+
+#define GCLK_IDX_VDEC_CLK_1 144
+#define GCLK_NAME_VDEC_CLK_1 "VDEC_CLK_1"
+#define GCLK_DEV_VDEC_CLK_1 "CLKGATE_VDEC_CLK_1"
+#define GCLK_REG_VDEC_CLK_1 (HHI_VDEC_CLK_CNTL)
+#define GCLK_MASK_VDEC_CLK_1 (1<<8)
+
+#define GCLK_NAME_VDEC_CLK_2 "VDEC_CLK_2"
+#define GCLK_REG_VDEC_CLK_2 (HHI_VDEC3_CLK_CNTL)
+#define GCLK_MASK_VDEC_CLK_2 (1<<8)
+
+#define GCLK_NAME_VDEC2_CLK_1 "VDEC2_CLK_1"
+#define GCLK_REG_VDEC2_CLK_1 (HHI_VDEC2_CLK_CNTL)
+#define GCLK_MASK_VDEC2_CLK_1 (1<<8)
+
+#define GCLK_NAME_VDEC2_CLK_2 "VDEC2_CLK_2"
+#define GCLK_REG_VDEC2_CLK_2 (HHI_VDEC4_CLK_CNTL)
+#define GCLK_MASK_VDEC2_CLK_2 (1<<8)
+
+#define GCLK_IDX_HCODEC_CLK_1 145
+#define GCLK_NAME_HCODEC_CLK_1 "HCODEC_CLK"
+#define GCLK_DEV_HCODEC_CLK_1 "CLKGATE_HCODEC_CLK"
+#define GCLK_REG_HCODEC_CLK_1 (HHI_VDEC_CLK_CNTL)
+#define GCLK_MASK_HCODEC_CLK_1 (1<<24)
+
+#define GCLK_NAME_HCODEC_CLK_2 "HCODEC_CLK_2"
+#define GCLK_REG_HCODEC_CLK_2 (HHI_VDEC3_CLK_CNTL)
+#define GCLK_MASK_HCODEC_CLK_2 (1<<24)
+
+#define GCLK_NAME_HEVC_CLK_1 "HCODEC_CLK_1"
+#define GCLK_REG_HEVC_CLK_1 (HHI_VDEC2_CLK_CNTL)
+#define GCLK_MASK_HEVC_CLK_1 (1<<24)
+
+#define GCLK_NAME_HEVC_CLK_2 "HEVC_CLK_2"
+#define GCLK_REG_HEVC_CLK_2 (HHI_VDEC4_CLK_CNTL)
+#define GCLK_MASK_HEVC_CLK_2 (1<<24)
+
+#define GCLK_IDX_GEN_CLK 146
+#define GCLK_NAME_GEN_CLK "GEN_CLK"
+#define GCLK_DEV_GEN_CLK "CLKGATE_HCODEC_CLK"
+#define GCLK_REG_GEN_CLK (HHI_GEN_CLK_CNTL)
+#define GCLK_MASK_GEN_CLK (1<<11)
+
+#define GCLK_NAME_VPU_CLK_1 "VPU_CLK_1"
+#define GCLK_REG_VPU_CLK_1 (HHI_VPU_CLK_CNTL)
+#define GCLK_MASK_VPU_CLK_1 (1<<8)
+
+#define GCLK_NAME_VPU_CLK_2 "VPU_CLK_2"
+#define GCLK_REG_VPU_CLK_2 (HHI_VPU_CLK_CNTL)
+#define GCLK_MASK_VPU_CLK_2 (1<<24)
+
+
+#define GCLK_NAME_VPU_CLKB "VPU_CLKB"
+#define GCLK_REG_VPU_CLKB (HHI_VPU_CLKB_CNTL)
+#define GCLK_MASK_VPU_CLKB (1<<8)
+
+#define GCLK_NAME_VAPB_CLK_1 "VAPB_CLK_1"
+#define GCLK_REG_VAPB_CLK_1 (HHI_VAPBCLK_CNTL)
+#define GCLK_MASK_VAPB_CLK_1 (1<<8)
+
+#define GCLK_NAME_VAPB_CLK_2 "VAPB_CLK_2"
+#define GCLK_REG_VAPB_CLK_2 (HHI_VAPBCLK_CNTL)
+#define GCLK_MASK_VAPB_CLK_2 (1<<24)
+
+#define GCLK_NAME_MALI_CLK_1 "MALI_CLK_1"
+#define GCLK_REG_MALI_CLK_1 (HHI_MALI_CLK_CNTL)
+#define GCLK_MASK_MALI_CLK_1 (1<<8)
+
+#define GCLK_NAME_MALI_CLK_2 "MALI_CLK_2"
+#define GCLK_REG_MALI_CLK_2 (HHI_MALI_CLK_CNTL)
+#define GCLK_MASK_MALI_CLK_2 (1<<24)
+
+#define GCLK_NAME_PWM_A_CLK "PWM_A_CLK"
+#define GCLK_REG_PWM_A_CLK (CBUS_REG_ADDR(0x2156))
+#define GCLK_MASK_PWM_A_CLK (1<<15)
+
+#define GCLK_NAME_PWM_B_CLK "PWM_B_CLK"
+#define GCLK_REG_PWM_B_CLK (CBUS_REG_ADDR(0x2156))
+#define GCLK_MASK_PWM_B_CLK (1<<23)
+
+#define GCLK_NAME_PWM_C_CLK "PWM_C_CLK"
+#define GCLK_REG_PWM_C_CLK (CBUS_REG_ADDR(0x2196))
+#define GCLK_MASK_PWM_C_CLK (1<<15)
+
+#define GCLK_NAME_PWM_D_CLK "PWM_D_CLK"
+#define GCLK_REG_PWM_D_CLK (CBUS_REG_ADDR(0x2196))
+#define GCLK_MASK_PWM_D_CLK (1<<23)
+
+#define GCLK_NAME_PWM_E_CLK "PWM_E_CLK"
+#define GCLK_REG_PWM_E_CLK (CBUS_REG_ADDR(0x21b2))
+#define GCLK_MASK_PWM_E_CLK (1<<15)
+
+#define GCLK_NAME_PWM_F_CLK "PWM_D_CLK"
+#define GCLK_REG_PWM_F_CLK (CBUS_REG_ADDR(0x21b2))
+#define GCLK_MASK_PWM_F_CLK (1<<23)
+
+#define GCLK_NAME_VDIN_MEAS_CLK "VDIN_MEAS_CLK"
+#define GCLK_REG_VDIN_MEAS_CLK (HHI_VDIN_MEAS_CLK_CNTL)
+#define GCLK_MASK_VDIN_MEAS_CLK (1<<8)
+
+#define GCLK_NAME_MSR_CLK "MSR_CLK"
+#define GCLK_REG_MSR_CLK (CBUS_REG_ADDR(0x21d7))
+#define GCLK_MASK_MSR_CLK (1<<19)
+
+#define GCLK_NAME_MSR_HS_CLK "MSR_HS_CLK"
+#define GCLK_REG_MSR_HS_CLK (CBUS_REG_ADDR(0x21d9))
+#define GCLK_MASK_MSR_HS_CLK (1<<28)
+
+#define GCLK_NAME_32K_CLK "32K_CLK"
+#define GCLK_REG_32K_CLK (HHI_32K_CLK_CNTL)
+#define GCLK_MASK_32K_CLK (1<<15)
+
+
+
+#define GCLK_IDX_MAX 200
+
+extern short GCLK_ref[GCLK_IDX_MAX];
+
+#define REGISTER_CLK(_MOD) \
+static struct clk CLK_##_MOD = { \
+ .name = GCLK_NAME_##_MOD, \
+ .clock_index = GCLK_IDX_##_MOD, \
+ .clock_gate_reg_adr = GCLK_REG_##_MOD, \
+ .clock_gate_reg_mask = GCLK_MASK_##_MOD, \
+}
+
+#define CLK_LOOKUP_ITEM(_MOD) \
+ { \
+ .dev_id = GCLK_DEV_##_MOD, \
+ .con_id = GCLK_NAME_##_MOD, \
+ .clk = &CLK_##_MOD, \
+ }
+
+
+
+/**********************/
+/* internal audio dac control */
+#define ADAC_RESET (0x5000+0x00*4)
+#define ADAC_LATCH (0x5000+0x01*4)
+#define ADAC_POWER_CTRL_REG1 (0x5000+0x10*4)
+#define ADAC_POWER_CTRL_REG2 (0x5000+0x11*4)
+
+int audio_internal_dac_disable(void);
+
+/* video dac control */
+int video_dac_enable(unsigned char enable_mask);
+
+int video_dac_disable(void);
+
+
+#endif
diff --git a/arch/arm/mach-meson/c1/sdio.c b/arch/arm/mach-meson/c1/sdio.c
new file mode 100644
index 0000000..14ec635
--- /dev/null
+++ b/arch/arm/mach-meson/c1/sdio.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <asm/arch/io.h>
+#include <asm/arch/cpu_sdio.h>
+#include <asm/arch/secure_apb.h>
+#include <amlogic/cpu_id.h>
+#include <common.h>
+
+void cpu_sd_emmc_pwr_prepare(unsigned port)
+{
+}
+int cpu_sd_emmc_init(unsigned port)
+{
+ return 0;
+}
+
+/* return:
+ 0: insert
+ 1: not insert
+ */
+__weak int sd_emmc_detect(unsigned port)
+{
+ int ret = 0;
+
+ return ret;
+}
+
+
diff --git a/arch/arm/mach-meson/c1/timer.c b/arch/arm/mach-meson/c1/timer.c
new file mode 100644
index 0000000..8c16210
--- /dev/null
+++ b/arch/arm/mach-meson/c1/timer.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timer.h>
+#include <asm/types.h>
+
+uint32_t get_time(void)
+{
+ return readl(SYSCTRL_TIMERE);
+}
+
+void _udelay(unsigned int us)
+{
+#ifndef CONFIG_PXP_EMULATOR
+ unsigned int t0 = get_time();
+
+ while (get_time() - t0 <= us)
+ ;
+#endif
+}
diff --git a/arch/arm/mach-meson/c1/tsensor.c b/arch/arm/mach-meson/c1/tsensor.c
new file mode 100644
index 0000000..36b5d52
--- /dev/null
+++ b/arch/arm/mach-meson/c1/tsensor.c
@@ -0,0 +1,263 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <command.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/mailbox.h>
+#include <asm/arch/tsensor.h>
+#include <asm/arch/bl31_apis.h>
+
+int tsensor_tz_calibration(unsigned int type, unsigned int data)
+{
+ int ret;
+
+ register long x0 asm("x0") = TSENSOR_CALI_SET;
+ register long x1 asm("x1") = type;
+ register long x2 asm("x2") = data;
+ register long x3 asm("x3") = 0;
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+ } while (0);
+ ret = x0;
+
+ if (!ret)
+ return -1;
+ else
+ return 0;
+}
+
+int r1p1_codetotemp(unsigned long value, unsigned int u_efuse)
+{
+ int64_t temp;
+
+ temp = (value * ts_m) * (1 << 16) / (100 * (1 << 16) + ts_n * value);
+ if (u_efuse & 0x8000) {
+ temp = ((temp - (u_efuse & 0x7fff)) * ts_a / (1 << 16) - ts_b) / 10;
+ } else {
+ temp = ((temp + (u_efuse & 0x7fff)) * ts_a / (1 << 16) - ts_b) / 10;
+ }
+ return temp;
+}
+
+int r1p1_temp_read(int type)
+{
+ unsigned int ret, u_efuse;
+ unsigned int value_ts, value_all_ts;
+ int tmp = -1;
+ int i, cnt;
+ char buf[2];
+
+ switch (type) {
+ case 1:
+ /*enable thermal1*/
+ writel(T_CONTROL_DATA, TS_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKTREE_TS_CLK_CTRL);
+ ret = readl(SYSCTRL_SEC_STATUS_REG13);/*thermal1 cali data in reg CFG10*/
+ mdelay(5);
+ buf[0] = (ret) & 0xff;
+ buf[1] = (ret >> 8) & 0xff;
+ u_efuse = buf[1];
+ u_efuse = (u_efuse << 8) | buf[0];
+ value_ts = 0;
+ value_all_ts = 0;
+ cnt = 0;
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_STAT0) & 0xffff;
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ value_ts = value_all_ts / cnt;
+ printf("tsensor avg: 0x%x, u_efuse: 0x%x\n", value_ts, u_efuse);
+ if (value_ts == 0) {
+ printf("tsensor read temp is zero\n");
+ return -1;
+ }
+ tmp = r1p1_codetotemp(value_ts, u_efuse);
+ printf("temp1: %d\n", tmp);
+ break;
+ default:
+ printf("r1p1 tsensor trim type not support\n");
+ return -1;
+ }
+ return tmp;
+}
+
+unsigned int r1p1_temptocode(unsigned long value, int tempbase)
+{
+ unsigned long tmp1, tmp2, u_efuse, signbit;
+
+ printf("a b m n: %d, %d, %d, %d\n", ts_a, ts_b, ts_m, ts_n);
+ tmp1 = ((tempbase * 10 + ts_b) * (1 << 16)) / ts_a; /*ideal u*/
+ printf("%s : tmp1: 0x%lx\n", __func__, tmp1);
+ tmp2 = (ts_m * value * (1 << 16)) / ((1 << 16) * 100 + ts_n * value);
+ printf("%s : tmp2: 0x%lx\n", __func__, tmp2);
+ signbit = ((tmp1 > tmp2) ? 0 : 1);
+ u_efuse = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
+ u_efuse = (signbit << 15) | u_efuse;
+ return u_efuse;
+}
+
+int r1p1_temp_trim(int tempbase, int tempver, int type)
+{
+ unsigned int u_efuse, index_ts, index_ver;
+ unsigned int value_ts, value_all_ts;
+ int i, cnt;
+
+ printf("r1p1 temp trim type: 0x%x\n", type);
+ switch (type) {
+ case 0:
+ index_ver = 5;
+ if (tsensor_tz_calibration(index_ver, tempver) < 0)
+ printf("version tsensor thermal_calibration send error\n");
+ break;
+ case 1:
+ value_ts = 0;
+ value_all_ts = 0;
+ index_ts = 6;
+ cnt = 0;
+ /*enable thermal1*/
+ writel(T_CONTROL_DATA, TS_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKTREE_TS_CLK_CTRL);
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_STAT0) & 0xffff;
+ printf("tsensor read: 0x%x\n", value_ts);
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ value_ts = value_all_ts / cnt;
+ printf("tsensor avg: 0x%x\n", value_ts);
+ if (value_ts == 0) {
+ printf("tsensor read temp is zero\n");
+ return -1;
+ }
+ u_efuse = r1p1_temptocode(value_ts, tempbase);
+ printf("ts efuse:%d\n", u_efuse);
+ printf("ts efuse:0x%x, index: %d\n", u_efuse, index_ts);
+ if (tsensor_tz_calibration(index_ts, u_efuse) < 0) {
+ printf("tsensor thermal_calibration send error\n");
+ return -1;
+ }
+ break;
+ default:
+ printf("r1p1 tsensor trim type not support\n");
+ return -1;
+ break;
+ }
+ return 0;
+}
+
+int temp_read_entry(void)
+{
+ unsigned int ret, ver;
+
+ ret = readl(SYSCTRL_SEC_STATUS_REG13);
+ ver = (ret >> 24) & 0xff;
+ if (0 == (ver & T_VER_MASK)) {
+ printf("tsensor no trimmed: calidata:0x%x\n",
+ readl(SYSCTRL_SEC_STATUS_REG13));
+ return -1;
+ }
+ ret = (ver & 0xf) >> 2;
+ switch (ret) {
+ case 0x2:
+ printf("temp type no support\n");
+ break;
+ case 0x0:
+ printf("temp type no support\n");
+ break;
+ case 0x1:
+ r1p1_temp_read(1);
+ printf("read the thermal\n");
+ break;
+ case 0x3:
+ printf("temp type no support\n");
+ return -1;
+ break;
+ default:
+ printf("thermal version not support!!!Please check!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int temp_trim_entry(int tempbase, int tempver)
+{
+ unsigned int ret, ver;
+
+ ret = readl(SYSCTRL_SEC_STATUS_REG13);
+ ver = (ret >> 24) & 0xff;
+ if (ver & T_VER_MASK) {
+ printf("tsensor trimmed: cali data: 0x%x\n",
+ readl(SYSCTRL_SEC_STATUS_REG13));
+ return -1;
+ }
+
+ printf("tsensor input trim tempver, tempver:0x%x\n", tempver);
+ switch (tempver) {
+ case 0x84:
+ r1p1_temp_trim(tempbase, tempver, 1);
+ r1p1_temp_trim(tempbase, tempver, 0);
+ printf("triming the thermal by bbt-sw\n");
+ break;
+ case 0x85:
+ r1p1_temp_trim(tempbase, tempver, 1);
+ r1p1_temp_trim(tempbase, tempver, 0);
+ printf("triming the thermal by bbt-ops\n");
+ break;
+ case 0x87:
+ r1p1_temp_trim(tempbase, tempver, 1);
+ r1p1_temp_trim(tempbase, tempver, 0);
+ printf("triming the thermal by slt\n");
+ break;
+ default:
+ printf("thermal version not support!!!Please check!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int temp_cooling_entry(void)
+{
+#ifdef CONFIG_AML_TSENSOR_COOL
+ int temp;
+
+ while (1) {
+ temp = r1p1_temp_read(1);
+ if (temp <= CONFIG_HIGH_TEMP_COOL) {
+ printf("device cool done\n");
+ break;
+ }
+ mdelay(2000);
+ printf("warning: temp %d over %d, cooling\n", temp,
+ CONFIG_HIGH_TEMP_COOL);
+ }
+#endif
+ return 0;
+}
diff --git a/arch/arm/mach-meson/c1/usb.c b/arch/arm/mach-meson/c1/usb.c
new file mode 100644
index 0000000..3bb082a
--- /dev/null
+++ b/arch/arm/mach-meson/c1/usb.c
@@ -0,0 +1,404 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <power/regulator.h>
+#include <clk.h>
+#include <asm/arch/usb.h>
+#include <amlogic/cpu_id.h>
+
+#include <linux/compat.h>
+#include <linux/ioport.h>
+#include <asm-generic/gpio.h>
+
+#define U2_CTRL_SLEEP_SHIFT 24
+#define U2_HHI_MEM_PD_MASK 0x3
+#define U2_HHI_MEM_PD_SHIFT 0x0
+#define U2_CTRL_ISO_SHIFT 24
+#define PHY20_RESET_LEVEL_BIT 4
+#define USB_RESET_BIT 3
+
+#define USB2_PHY_PLL_OFFSET_40 (0x09400414)
+#define USB2_PHY_PLL_OFFSET_44 (0x927E0000)
+#define USB2_PHY_PLL_OFFSET_48 (0xac5f69e5)
+
+#define USB2_PHY_PLL_OFFSET_34 (0x78000)
+
+
+#define USB2_PHY_PLL_OFFSET_50 (0xfe18)
+#define USB2_PHY_PLL_OFFSET_54 (0x2a)
+
+#define TUNING_DISCONNECT_THRESHOLD 0x34
+
+#define P_AO_RTI_GEN_PWR_SLEEP0 0xfe007808
+#define P_AO_RTI_GEN_PWR_ISO0 0xfe007804
+#define P_HHI_MEM_PD_REG0 0xfe007850
+
+static struct phy usb_phys[2];
+
+int get_usbphy_baseinfo(struct phy *usb_phys)
+{
+ struct udevice *bus;
+ struct uclass *uc;
+ int ret, i;
+ int count;
+
+ if (usb_phys[0].dev && usb_phys[1].dev)
+ return 0;
+
+ ret = uclass_get(UCLASS_USB, &uc);
+ if (ret)
+ return ret;
+ uclass_foreach_dev(bus, uc) {
+ debug("bus->name=%s, bus->driver->name =%s\n",
+ bus->name, bus->driver->name);
+ count = dev_count_phandle_with_args(bus, "phys", "#phy-cells");
+ debug("usb phy count=%u\n", count);
+ if (count <= 0)
+ return count;
+ for (i = 0; i < count; i++) {
+ ret = generic_phy_get_by_index(bus, i, &usb_phys[i]);
+ if (ret && ret != -ENOENT) {
+ pr_err("Failed to get USB PHY%d for %s\n",
+ i, bus->name);
+ return ret;
+ }
+ ret = generic_phy_getinfo(&usb_phys[i]);
+ if (ret)
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static void usb_set_power_domain (void)
+{
+ writel((readl(P_AO_RTI_GEN_PWR_SLEEP0) & (~(0x1 << U2_CTRL_SLEEP_SHIFT))),
+ P_AO_RTI_GEN_PWR_SLEEP0);
+ writel((readl(P_AO_RTI_GEN_PWR_ISO0) & (~(0x1 << U2_CTRL_ISO_SHIFT))),
+ P_AO_RTI_GEN_PWR_ISO0);
+ writel((readl(P_HHI_MEM_PD_REG0)
+ & (~(U2_HHI_MEM_PD_MASK << U2_HHI_MEM_PD_SHIFT))), P_HHI_MEM_PD_REG0);
+
+ return;
+}
+
+static void usb_set_clock_freq(unsigned int clock_addr)
+{
+ unsigned int val = (1 << 8) | (2 << 9) | (9 << 0);
+ writel(val, (unsigned long)clock_addr);
+ return;
+}
+
+static void set_pll_Calibration_default(uint32_t phy2_pll_base)
+{
+ u32 tmp;
+
+ tmp = (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x8));
+ tmp &= 0xfff;
+ tmp |= (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10));
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10))
+ = tmp;
+}
+
+void usb_reset(unsigned int reset_addr, int bit)
+{
+ *(volatile unsigned int *)(unsigned long)reset_addr = (1 << bit);
+}
+
+static void usb_enable_phy_pll (void)
+{
+ *(volatile uint32_t *)RESETCTRL_RESET1_LEVEL |= (1 << PHY20_RESET_LEVEL_BIT);
+}
+
+static void usb_disable_phy_pll (void)
+{
+ *(volatile uint32_t *)RESETCTRL_RESET1_LEVEL &= ~(1 << PHY20_RESET_LEVEL_BIT);
+}
+
+void set_usb_pll(uint32_t phy2_pll_base)
+{
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))
+ = (USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET | USB_PHY2_ENABLE);
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44)) =
+ USB2_PHY_PLL_OFFSET_44;
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x48)) =
+ USB2_PHY_PLL_OFFSET_48;
+ udelay(100);
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x40))
+ = (((USB2_PHY_PLL_OFFSET_40) | (USB_PHY2_ENABLE))
+ & (~(USB_PHY2_RESET)));
+
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50))
+ = USB2_PHY_PLL_OFFSET_50;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x54))
+ = USB2_PHY_PLL_OFFSET_54;
+ set_pll_Calibration_default(phy2_pll_base);
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0xc)) =
+ TUNING_DISCONNECT_THRESHOLD;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x34))
+ = USB2_PHY_PLL_OFFSET_34;
+
+ debug("tuning_disconnect_threshold=0x%x\n", TUNING_DISCONNECT_THRESHOLD);
+}
+
+int usb_save_phy_dev (unsigned int number, struct phy *phy)
+{
+ usb_phys[number].dev = phy->dev;
+ usb_phys[number].id = phy->id;
+ return 0;
+}
+
+int usb2_phy_init (struct phy *phy) {
+ struct phy_aml_usb2_priv *priv = dev_get_priv(phy->dev);
+ struct u2p_aml_regs *u2p_aml_reg;
+ u2p_r0_t dev_u2p_r0;
+ u2p_r1_t dev_u2p_r1;
+ int i,cnt;
+
+ usb_save_phy_dev(0, phy);
+ usb_enable_phy_pll();
+ usb_set_power_domain();
+
+ priv->clktree_usb_bus_ctrl_addr = dev_read_addr_index(phy->dev, 2 + priv->u2_port_num);
+ if (priv->clktree_usb_bus_ctrl_addr == FDT_ADDR_T_NONE) {
+ pr_err("Coun't get clktree_usb_bus_ctrl addr index %d\n", 2 + priv->u2_port_num);
+ } else {
+ usb_set_clock_freq(priv->clktree_usb_bus_ctrl_addr);
+ }
+
+ usb_reset(priv->reset_addr, USB_RESET_BIT);
+
+ udelay(500);
+ priv->usbphy_reset_bit[0] = PHY20_RESET_LEVEL_BIT;
+
+ for (i = 0; i < priv->u2_port_num; i++) {
+ u2p_aml_reg = (struct u2p_aml_regs *)((ulong)(priv->base_addr + i * PHY_REGISTER_SIZE));
+ dev_u2p_r0.d32 = u2p_aml_reg->u2p_r0;
+ dev_u2p_r0.b.host_device= 1;
+ dev_u2p_r0.b.POR= 0;
+ u2p_aml_reg->u2p_r0 = dev_u2p_r0.d32;
+ udelay(10);
+ /***USB PHY RESET : reset1 and reset1_level both need set ***/
+ /***reset1: usb_reset ***/
+ /***reset1_level: usb_enable_phy_pll ***/
+ usb_reset(priv->reset_addr, priv->usbphy_reset_bit[i]);
+ udelay(50);
+
+ /* wait for phy ready */
+ dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
+ cnt = 0;
+ while (dev_u2p_r1.b.phy_rdy != 1) {
+ dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
+ /*we wait phy ready max 1ms, common is 100us*/
+ if (cnt > 200)
+ break;
+ else {
+ cnt++;
+ udelay(5);
+ }
+ }
+ }
+
+ for (i = 0; i < priv->u2_port_num; i++) {
+ debug("------set usb pll\n");
+ set_usb_pll(priv->usb_phy2_pll_base_addr[i]);
+ }
+ return 0;
+
+}
+
+int usb2_phy_tuning(uint32_t phy2_pll_base, int port)
+{
+ return 0;
+}
+
+/**************************************************************/
+/* device mode config */
+/**************************************************************/
+unsigned int usb_get_dwc_a_base_addr(void)
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ int ret;
+
+ if (!usb_phys[0].dev) {
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ return usb2_priv->dwc2_a_addr;
+}
+
+unsigned int usb_get_device_mode_phy_base(void)
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ int ret;
+
+ if (!usb_phys[0].dev) {
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ return usb2_priv->usb_phy2_pll_base_addr[0];
+}
+
+void usb_phy_tuning_reset(void)
+{
+ return;
+}
+
+void usb_device_mode_init(void){
+ u2p_r0_t dev_u2p_r0;
+ u2p_r1_t dev_u2p_r1;
+
+ usb_r0_t dev_usb_r0;
+ usb_r4_t dev_usb_r4;
+ int cnt, ret;
+ u2p_aml_regs_t * u2p_aml_regs;
+ usb_aml_regs_t *usb_aml_regs;
+ struct phy_aml_usb2_priv *usb2_priv;
+ struct phy_aml_usb3_priv *usb3_priv;
+ unsigned int phy_base_addr, reset_addr;
+
+ usb_enable_phy_pll();
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return;
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ usb3_priv = dev_get_priv(usb_phys[1].dev);
+ if (!usb2_priv || !usb3_priv) {
+ printf("get usb phy address from dts failed\n");
+ return;
+ }
+
+ u2p_aml_regs = (u2p_aml_regs_t * )((ulong)usb2_priv->base_addr);
+ usb_aml_regs = (usb_aml_regs_t * )((ulong)usb3_priv->base_addr);
+ phy_base_addr = usb2_priv->usb_phy2_pll_base_addr[0];
+ reset_addr = usb2_priv->reset_addr;
+
+ usb_set_power_domain();
+ usb_set_clock_freq(CLKTREE_USB_BUSCLK_CTRL);
+
+ printf("PHY2=0x%08x\n", usb2_priv->base_addr);
+ if ((*(volatile uint32_t *)((ulong)(phy_base_addr + 0x38))) != 0) {
+ usb_phy_tuning_reset();
+ mdelay(150);
+ }
+
+ //step 1: usb controller reset
+ usb_reset(reset_addr, USB_RESET_BIT);
+
+ // step 3: enable usb INT internal USB
+ dev_usb_r0.d32 = usb_aml_regs->usb_r0;
+ dev_usb_r0.b.u2d_ss_scaledown_mode = 0;
+ dev_usb_r0.b.u2d_act = 1;
+ usb_aml_regs->usb_r0 = dev_usb_r0.d32;
+
+ // step 4: disable usb phy sleep
+ dev_usb_r4.d32 = usb_aml_regs->usb_r4;
+ dev_usb_r4.b.p21_SLEEPM0 = 1;
+ usb_aml_regs->usb_r4 = dev_usb_r4.d32;
+
+ // step 5: config phy21 device mode
+ dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0;
+ dev_u2p_r0.b.host_device= 0;
+ dev_u2p_r0.b.POR= 0;
+ u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32;
+
+ udelay(10);
+ //step 6: phy21 reset
+ usb_reset(reset_addr, PHY20_RESET_LEVEL_BIT);
+ udelay(50);
+
+ // step 6: wait for phy ready
+ dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
+ cnt = 0;
+ while ((dev_u2p_r1.d32 & 0x00000001) != 1) {
+ dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
+ if (cnt > 200)
+ break;
+ else {
+ cnt++;
+ udelay(5);
+ }
+ }
+
+ set_usb_pll(phy_base_addr);
+ //--------------------------------------------------
+
+ // ------------- usb phy21 initinal end ----------
+
+ //--------------------------------------------------
+
+}
+
+static void usb_disable_phy(uint32_t phy2_pll_base)
+{
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))=
+ ((USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET) & (~USB_PHY2_ENABLE));
+ udelay(5);
+}
+
+static void usb_print_usb_baseinfo
+ (struct phy_aml_usb2_priv *usb2_priv, struct phy_aml_usb3_priv *usb3_priv)
+{
+ if (usb3_priv) {
+ printf("priv->usb3 port num = %d, config addr=0x%08x\n",
+ usb3_priv->usb3_port_num, usb3_priv->base_addr);
+ }
+ if (usb2_priv) {
+ printf("usb2 phy: config addr = 0x%08x, reset addr=0x%08x\n",
+ usb2_priv->base_addr, usb2_priv->reset_addr);
+
+ printf("usb2 phy: portnum=%d, phy-addr1= 0x%08x, phy-addr2= 0x%08x\n",
+ usb2_priv->u2_port_num, usb2_priv->usb_phy2_pll_base_addr[0],
+ usb2_priv->usb_phy2_pll_base_addr[1]);
+ printf("dwc2_a base addr: 0x%08x\n", usb2_priv->dwc2_a_addr);
+ }
+}
+
+int usb_aml_detect_operation(int argc, char * const argv[])
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ struct phy_aml_usb3_priv *usb3_priv;
+ int ret;
+
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ usb3_priv = dev_get_priv(usb_phys[1].dev);
+
+ if (argc >= 2) {
+ if (strncmp(argv[1], "disable", 7) == 0) {
+ usb_disable_phy_pll();
+ usb_disable_phy(usb2_priv->usb_phy2_pll_base_addr[0]);
+ printf("disable USB phy\n");
+ return 0;
+ }
+
+ if (strncmp(argv[1], "info", 4) == 0) {
+ usb_print_usb_baseinfo(usb2_priv, usb3_priv);
+ return 0;
+ }
+ }
+ return CMD_RET_USAGE;
+}
diff --git a/arch/arm/mach-meson/c2/Makefile b/arch/arm/mach-meson/c2/Makefile
new file mode 100644
index 0000000..a7b0aae
--- /dev/null
+++ b/arch/arm/mach-meson/c2/Makefile
@@ -0,0 +1,14 @@
+
+obj-y := sdio.o pinctrl_init.o
+obj-y += bl31_apis.o
+obj-y += cpu_reset.o
+obj-y += timer.o
+#obj-y += mailbox.o
+#obj-y += gate_init.o
+#obj-y += power_cal.o
+obj-$(CONFIG_CMD_PLLTEST) += pll.o
+obj-$(CONFIG_CMD_AML_MTEST) += core.o
+obj-$(CONFIG_AML_HDMITX) += hdmitx.o
+obj-y += usb.o
+obj-$(CONFIG_AML_TSENSOR) += tsensor.o
+obj-$(CONFIG_AML_OSCRING) += oscring.o
diff --git a/arch/arm/mach-meson/c2/bl31_apis.c b/arch/arm/mach-meson/c2/bl31_apis.c
new file mode 100644
index 0000000..2d74c24
--- /dev/null
+++ b/arch/arm/mach-meson/c2/bl31_apis.c
@@ -0,0 +1,491 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ * Trustzone API
+ */
+
+#include <asm/arch/io.h>
+#include <asm/arch/efuse.h>
+#include <asm/cache.h>
+#include <asm/arch/bl31_apis.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+
+static long sharemem_input_base;
+static long sharemem_output_base;
+
+long get_sharemem_info(unsigned long function_id)
+{
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ : "+r" (function_id));
+
+ return function_id;
+}
+
+#ifdef CONFIG_EFUSE
+int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg)
+{
+ int ret;
+ unsigned cmd, offset, size;
+ unsigned long *retcnt = (unsigned long *)(arg->retcnt_phy);
+
+ if (!sharemem_input_base)
+ sharemem_input_base =
+ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE);
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ if (arg->cmd == EFUSE_HAL_API_READ)
+ cmd = EFUSE_READ;
+ else if (arg->cmd == EFUSE_HAL_API_WRITE)
+ cmd = EFUSE_WRITE;
+ else
+ cmd = EFUSE_WRITE_PATTERN;
+ offset = arg->offset;
+ size = arg->size;
+
+ if (arg->cmd == EFUSE_HAL_API_WRITE)
+ memcpy((void *)sharemem_input_base,
+ (const void *)arg->buffer_phy, size);
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = cmd;
+ register uint64_t x1 asm("x1") = offset;
+ register uint64_t x2 asm("x2") = size;
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2));
+ } while (0);
+ ret = x0;
+ *retcnt = x0;
+
+ if ((arg->cmd == EFUSE_HAL_API_READ) && (ret != 0))
+ memcpy((void *)arg->buffer_phy,
+ (const void *)sharemem_output_base, ret);
+
+ if (!ret)
+ return -1;
+ else
+ return 0;
+}
+
+int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg)
+{
+ int32_t ret;
+ unsigned cmd = 0;
+
+ if (arg->cmd == EFUSE_HAL_API_USER_MAX)
+ cmd = EFUSE_USER_MAX;
+
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = cmd;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0));
+ } while (0);
+ ret = x0;
+
+ if (!ret)
+ return -1;
+ else
+ return ret;
+}
+
+ssize_t meson_trustzone_efuse_writepattern(const char *buf, size_t count)
+{
+ struct efuse_hal_api_arg arg;
+ unsigned long retcnt;
+
+ if (count != EFUSE_BYTES)
+ return 0; /* Past EOF */
+
+ arg.cmd = EFUSE_HAL_API_WRITE_PATTERN;
+ arg.offset = 0;
+ arg.size = count;
+ arg.buffer_phy = (unsigned long)buf;
+ arg.retcnt_phy = (unsigned long)&retcnt;
+ int ret;
+ ret = meson_trustzone_efuse(&arg);
+ return ret;
+}
+#endif
+
+uint64_t meson_trustzone_efuse_check(unsigned char *addr)
+{
+ uint64_t ret = 0;
+ struct sram_hal_api_arg arg = {};
+
+ arg.cmd = SRAM_HAL_API_CHECK_EFUSE;
+ arg.req_len = 0x1000000;
+ arg.res_len = 0;
+ arg.req_phy_addr = (unsigned long)addr;
+ arg.res_phy_addr = (unsigned long)NULL;
+
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = CALL_TRUSTZONE_HAL_API;
+ register uint64_t x1 asm("x1") = TRUSTZONE_HAL_API_SRAM;
+ register uint64_t x2 asm("x2") = (unsigned long)(&arg);
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2));
+ } while (0);
+
+ ret = x0;
+
+ return ret;
+}
+
+void debug_efuse_cmd(unsigned long cmd)
+{
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ : : "r" (cmd));
+}
+
+void bl31_debug_efuse_write_pattern(const char *buf)
+{
+ if (!sharemem_input_base)
+ sharemem_input_base =
+ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE);
+ memcpy((void *)sharemem_input_base, (const void *)buf, 512);
+
+ debug_efuse_cmd(DEBUG_EFUSE_WRITE_PATTERN);
+}
+
+void bl31_debug_efuse_read_pattern(char *buf)
+{
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+ debug_efuse_cmd(DEBUG_EFUSE_READ_PATTERN);
+
+ memcpy((void *)buf, (const void *)sharemem_output_base, 512);
+}
+
+void aml_set_jtag_state(unsigned state, unsigned select)
+{
+ uint64_t command;
+ if (state == JTAG_STATE_ON)
+ command = JTAG_ON;
+ else
+ command = JTAG_OFF;
+ asm __volatile__("" : : : "memory");
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : : "r" (command), "r"(select));
+}
+
+void wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value)
+{
+ register long x0 asm("x0") = 0x82000086;
+ register long x1 asm("x1") = cmd;
+ register long x2 asm("x2") = value;
+ register long x3 asm("x3") = 0;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+}
+
+unsigned aml_get_reboot_reason(void)
+{
+ unsigned reason;
+ uint64_t ret;
+
+ register uint64_t x0 asm("x0") = GET_REBOOT_REASON;
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ :"+r"(x0));
+ ret = x0;
+ reason = (unsigned)(ret&0xffffffff);
+ return reason;
+}
+
+void set_viu_probe_enable(void)
+{
+ register uint64_t x0 asm("x0") = VIU_PREOBE_EN;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ :"+r"(x0));
+}
+
+void power_set_dsp(unsigned int id, unsigned int powerflag)
+{
+ register long x0 asm("x0") = DSP_SEC_POWERSET;
+ register long x1 asm("x1") = id;
+ register long x2 asm("x2") = powerflag;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2));
+}
+
+void init_dsp(unsigned int id,unsigned int addr,unsigned int cfg0)
+{
+ register long x0 asm("x0") = START_HIFI4;
+ register long x1 asm("x1") = id;
+ register long x2 asm("x2") = addr;
+ register long x3 asm("x3") = cfg0;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+}
+
+
+unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2)
+{
+ register long x0 asm("x0") = function_id;
+ register long x1 asm("x1") = arg0;
+ register long x2 asm("x2") = arg1;
+ register long x3 asm("x3") = arg2;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+
+ return function_id;
+}
+
+void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2)
+{
+ register long x0 asm("x0") = function_id;
+ register long x1 asm("x1") = arg0;
+ register long x2 asm("x2") = arg1;
+ register long x3 asm("x3") = arg2;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+
+ return ;
+}
+
+unsigned long aml_sec_boot_check(unsigned long nType,
+ unsigned long pBuffer,
+ unsigned long nLength,
+ unsigned long nOption)
+{
+ uint64_t ret = 1;
+
+//#define AML_SECURE_LOG_TE
+
+#if defined(AML_SECURE_LOG_TE)
+ #define AML_GET_TE(a) do{a = *((volatile unsigned int*)0xc1109988);}while(0);
+ unsigned nT1,nT2,nT3;
+#else
+ #define AML_GET_TE(...)
+#endif
+
+ AML_GET_TE(nT1);
+
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = AML_DATA_PROCESS;
+ register uint64_t x1 asm("x1") = nType;
+ register uint64_t x2 asm("x2") = pBuffer;
+ register uint64_t x3 asm("x3") = nLength;
+ register uint64_t x4 asm("x4") = nOption;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ __asmeq("%4", "x3")
+ __asmeq("%5", "x4")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2),"r"(x3),"r"(x4));
+ } while (0);
+
+ ret = x0;
+
+ AML_GET_TE(nT2);;
+
+ flush_dcache_range((unsigned long )pBuffer, (unsigned long )pBuffer+nLength);
+
+ AML_GET_TE(nT3);
+
+#if defined(AML_SECURE_LOG_TE)
+ printf("aml log : dec use %d(us) , flush cache used %d(us)\n",
+ nT2 - nT1, nT3 - nT2);
+#endif
+
+ return ret;
+}
+
+void set_usb_boot_function(unsigned long command)
+{
+ register long x0 asm("x0") = SET_USB_BOOT_FUNC;
+ register long x1 asm("x1") = command;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+}
+
+void set_boot_first_timeout(uint64_t arg0)
+{
+ register long x0 asm("x0") = SET_BOOT_FIRST;
+ register long x1 asm("x1") = arg0;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+}
+void aml_system_off(void)
+{
+ /* TODO: Add poweroff capability */
+ aml_reboot(0x82000042, 1, 0, 0);
+ aml_reboot(0x84000008, 0, 0, 0);
+}
+
+int __get_chip_id(unsigned char *buff, unsigned int size)
+{
+ if (buff == NULL || size < 16)
+ return -1;
+
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ if (sharemem_output_base) {
+ register long x0 asm("x0") = GET_CHIP_ID;
+ register long x1 asm("x1") = 2;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+
+ if (x0 == 0) {
+ int version = *((unsigned int *)sharemem_output_base);
+
+ if (version == 2) {
+ memcpy(buff, (void *)sharemem_output_base + 4, 16);
+ }
+ else {
+ /**
+ * Legacy 12-byte chip ID read out, transform data
+ * to expected order format.
+ */
+ uint32_t chip_info = 0;//readl(P_AO_SEC_SD_CFG8);
+ uint8_t *ch;
+ int i;
+
+ ((uint32_t *)buff)[0] =
+ ((chip_info & 0xff000000) | // Family ID
+ ((chip_info << 8) & 0xff0000) | // Chip Revision
+ ((chip_info >> 8) & 0xff00)); // Package ID
+
+ ((uint32_t *)buff)[0] = htonl(((uint32_t *)buff)[0]);
+
+ /* Transform into expected order for display */
+ ch = (uint8_t *)(sharemem_output_base + 4);
+ for (i = 0; i < 12; i++)
+ buff[i + 4] = ch[11 - i];
+ }
+
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
+int bl31_get_cornerinfo(uint8_t *outbuf, int size)
+{
+ int buff_len = 0;
+
+ if (outbuf == NULL) {
+ printf("BL33: corner efuse info storebuf is NULL\n");
+ return -1;
+ }
+
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ if (sharemem_output_base) {
+ register long x0 asm("x0") = OSCRING_EFUSE_GET;
+ register long x1 asm("x1") = size;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+ } while(0);
+ buff_len = x0;
+ if (buff_len <= size) {
+ memcpy(outbuf, (void *)sharemem_output_base, buff_len);
+ return 0;
+ } else {
+ printf("BL33: corner efuse info buf len %d over storebuf size %d\n", buff_len, size);
+ return -1;
+ }
+ }
+ return -1;
+}
diff --git a/arch/arm/mach-meson/c2/core.c b/arch/arm/mach-meson/c2/core.c
new file mode 100644
index 0000000..8640828
--- /dev/null
+++ b/arch/arm/mach-meson/c2/core.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/types.h>
+#include <asm/arch/cpu.h>
+#include <common.h>
+
+const unsigned int core_map[] = {
+ 0x0,
+ 0x1,
+ 0x2,
+ 0x3,
+};
+
+int get_core_mpidr(unsigned int cpuid)
+{
+ unsigned int coremax = (unsigned int)(sizeof(core_map)/sizeof(unsigned int));
+
+ if (cpuid >= coremax)
+ return -1;
+ return core_map[cpuid];
+}
+
+int get_core_idx(unsigned int mpidr)
+{
+ unsigned int clusterid, cpuid;
+
+ cpuid = mpidr & 0xff;
+ clusterid = mpidr & 0xff00;
+
+ cpuid += (clusterid >> 6);
+
+ if (cpuid >= NR_CPUS)
+ return -1;
+
+ return cpuid;
+}
+
+int get_core_max(void)
+{
+ return (sizeof(core_map)/sizeof(unsigned int));
+}
diff --git a/arch/arm/mach-meson/c2/cpu_reset.c b/arch/arm/mach-meson/c2/cpu_reset.c
new file mode 100644
index 0000000..ca0a42d
--- /dev/null
+++ b/arch/arm/mach-meson/c2/cpu_reset.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/types.h>
+#include <asm/arch/romboot.h>
+#include <asm/arch/cpu_reset.h>
+#include <asm/arch/io.h>
+#include <asm/arch/timer.h>
+#include <dm.h>
+#include <wdt.h>
+
+/*
+ *GPIOE_0 VDDEE_PWM
+ *GPIOE_1 VDDCPU_PWM
+ * */
+void set_pwm_to_input(void)
+{
+ //hxbao, need fine tune
+ #if 0
+ unsigned int val;
+
+ val = readl(AO_RTI_PINMUX_REG1);
+ val &= ~(0xff << 16);
+ writel(val, AO_RTI_PINMUX_REG1);/* clear pinmux */
+ val = readl(AO_GPIO_O_EN_N);
+ val &= ~(0x3 << 16);
+ val |= 0x3 << 16;
+ writel(val, AO_GPIO_O_EN_N);/* set input mode */
+ val = readl(AO_RTI_PULL_UP_EN_REG);
+ val &= ~(0x3 << 16);
+ writel(val, AO_RTI_PULL_UP_EN_REG);/* disable pull up/down */
+ #endif
+}
+
+void reset_system(void)
+{
+ struct udevice *watchdog_devp;
+ int ret;
+
+ set_pwm_to_input();
+
+ _udelay(10000); //wait print
+
+ ret = uclass_get_device_by_name(UCLASS_WDT, "watchdog", &watchdog_devp);
+ if (ret < 0) {
+ printf("failed to reset system because can't get wdt device\n");
+ return;
+ }
+ wdt_start(watchdog_devp, 0, 0);
+ while (1);
+}
+
+/* uboot reset interface */
+void reset_cpu(unsigned long flag){
+ reset_system();
+}
diff --git a/arch/arm/mach-meson/c2/firmware/acs/Makefile b/arch/arm/mach-meson/c2/firmware/acs/Makefile
new file mode 100644
index 0000000..70d2d83
--- /dev/null
+++ b/arch/arm/mach-meson/c2/firmware/acs/Makefile
@@ -0,0 +1,431 @@
+#
+# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of ARM nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+#
+# Default values for build configurations
+#
+
+export CROSS_COMPILE=/opt/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-
+
+include $(buildsrc)/config.mk
+include $(buildtree)/include/autoconf.mk
+include $(buildtree)/.config
+
+# Build verbosity
+V := 0
+# Debug build
+BUILD_TYPE := ${BL2_BUILD_TYPE}
+# Build architecture
+ARCH := aarch64
+# Build platform
+#DEFAULT_PLAT := gx
+PLAT := ${SOC}
+export PLAT
+# SPD choice
+SPD := none
+# Base commit to perform code check on
+BASE_COMMIT := origin/master
+# NS timer register save and restore
+NS_TIMER_SWITCH := 0
+# By default, Bl1 acts as the reset handler, not BL31
+RESET_TO_BL31 := 0
+
+# Checkpatch ignores
+CHECK_IGNORE = --ignore COMPLEX_MACRO
+
+CHECKPATCH_ARGS = --no-tree --no-signoff ${CHECK_IGNORE}
+CHECKCODE_ARGS = --no-patch --no-tree --no-signoff ${CHECK_IGNORE}
+
+ifeq (${V},0)
+ Q=@
+ CHECKCODE_ARGS += --no-summary --terse
+else
+ Q=
+endif
+export Q
+
+ifeq (${GIT_VERSION},)
+ GIT_VERSION := $(shell git describe --abbrev=7 --dirty --always --tags)
+endif
+ifeq (${BUILDER},)
+ BUILDER := ${USER}@$(shell hostname)
+endif
+
+BL_COMMON_SOURCES := common/bl_common.c \
+ common/debug.c \
+ lib/aarch64/cache_helpers.S \
+ lib/aarch64/misc_helpers.S \
+ lib/aarch64/tlb_helpers.S \
+ lib/aarch64/xlat_helpers.c \
+ lib/stdlib/std.c \
+ lib/io_storage.c \
+ plat/common/aarch64/platform_helpers.S
+
+BUILD_BASE := $(buildtree)/firmware
+#BUILD_PLAT := ${BUILD_BASE}/${PLAT}
+BUILD_PLAT := $(buildtree)/board/${BOARDDIR}/firmware
+#BUILD_PLAT := $(buildtree)/${BOARDDIR}/firmware
+
+# Convenience function for adding build definitions
+# $(eval $(call add_define,FOO)) will have:
+# -DFOO if $(FOO) is empty; -DFOO=$(FOO) otherwise
+define add_define
+DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
+endef
+
+# Convenience function for verifying option has a boolean value
+# $(eval $(call assert_boolean,FOO)) will assert FOO is 0 or 1
+define assert_boolean
+$(and $(patsubst 0,,$(value $(1))),$(patsubst 1,,$(value $(1))),$(error $(1) must be boolean))
+endef
+
+ifeq (${PLAT},)
+ $(error "Error: Unknown platform. Please use PLAT=<platform name> to specify the platform.")
+endif
+
+all: msg_start
+
+msg_start:
+ @echo "Building ${BOARDDIR}/acs.bin"
+
+#include plat/${PLAT}/platform.mk
+#ifdef BL2_SOURCES
+NEED_BL2 := yes
+include acs.mk
+#endif
+
+# Include SPD Makefile if one has been specified
+ifneq (${SPD},none)
+ # We expect to locate an spd.mk under the specified SPD directory
+ SPD_MAKE := $(shell m="services/spd/${SPD}/${SPD}.mk"; [ -f "$$m" ] && echo "$$m")
+
+ ifeq (${SPD_MAKE},)
+ $(error Error: No services/spd/${SPD}/${SPD}.mk located)
+ endif
+ $(info Including ${SPD_MAKE})
+ include ${SPD_MAKE}
+
+ # If there's BL32 companion for the chosen SPD, and the SPD wants to build the
+ # BL2 from source, we expect that the SPD's Makefile would set NEED_BL32
+ # variable to "yes"
+endif
+
+.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool fip
+.SUFFIXES:
+
+INCLUDES += -Iinclude/bl2 \
+ -Iinclude/bl31 \
+ -Iinclude/common \
+ -Iinclude/drivers \
+ -Iinclude/drivers/arm \
+ -Iinclude/drivers/serial \
+ -Iinclude/lib \
+ -Iinclude/lib/aarch64 \
+ -Iinclude/plat/common \
+ -Iinclude/stdlib \
+ -Iinclude/stdlib/sys \
+ ${PLAT_INCLUDES} \
+ ${SPD_INCLUDES}
+
+# Process DEBUG flag
+$(eval $(call assert_boolean,DEBUG))
+$(eval $(call add_define,DEBUG))
+ifeq (${DEBUG},0)
+ $(eval $(call add_define,NDEBUG))
+else
+CFLAGS += -g
+ASFLAGS += -g -Wa,--gdwarf-2
+endif
+
+# Process NS_TIMER_SWITCH flag
+$(eval $(call assert_boolean,NS_TIMER_SWITCH))
+$(eval $(call add_define,NS_TIMER_SWITCH))
+
+# Process RESET_TO_BL31 flag
+$(eval $(call assert_boolean,RESET_TO_BL31))
+$(eval $(call add_define,RESET_TO_BL31))
+
+VPATH_LIST = $(buildsrc)/board/$(BOARDDIR)
+#VPATH_LIST = $(buildsrc)/$(BOARDDIR)
+VPATH_LIST:=$(VPATH_LIST:%=%/firmware/)
+
+vpath %.c $(VPATH_LIST)
+
+ASFLAGS += -nostdinc -ffreestanding -Wa,--fatal-warnings \
+ -mgeneral-regs-only -D__ASSEMBLY__ \
+ ${DEFINES} ${INCLUDES}
+CFLAGS += -nostdinc -pedantic -ffreestanding -Wall \
+ -Werror -mgeneral-regs-only -std=c99 -c -Os \
+ ${DEFINES} ${INCLUDES} $(VPATH_LIST:%=-I%)
+CFLAGS += -ffunction-sections -fdata-sections
+ASFLAGS += ${FIRMWARE_CPPFLAGS}
+CFLAGS += ${FIRMWARE_CPPFLAGS}
+CFLAGS += -Wno-unused
+
+LDFLAGS += --fatal-warnings -O1
+LDFLAGS += --gc-sections
+
+CC := ${CROSS_COMPILE}gcc
+CPP := ${CROSS_COMPILE}cpp
+AS := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OC := ${CROSS_COMPILE}objcopy
+OD := ${CROSS_COMPILE}objdump
+NM := ${CROSS_COMPILE}nm
+PP := ${CROSS_COMPILE}gcc -E ${CFLAGS}
+
+# Variables for use with Firmware Image Package
+FIPTOOLPATH ?= tools/fip_create
+FIPTOOL ?= ${FIPTOOLPATH}/fip_create
+fiptool: ${FIPTOOL}
+fip: ${BUILD_PLAT}/fip.bin
+
+locate-checkpatch:
+ifndef CHECKPATCH
+ $(error "Please set CHECKPATCH to point to the Linux checkpatch.pl file, eg: CHECKPATCH=../linux/script/checkpatch.pl")
+else
+ifeq (,$(wildcard ${CHECKPATCH}))
+ $(error "The file CHECKPATCH points to cannot be found, use eg: CHECKPATCH=../linux/script/checkpatch.pl")
+endif
+endif
+
+clean:
+ @echo " CLEAN"
+ ${Q}rm -rf ${BUILD_PLAT}
+ ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
+
+realclean distclean:
+ @echo " REALCLEAN"
+ ${Q}rm -rf ${BUILD_BASE}
+ ${Q}rm -f ${CURDIR}/cscope.*
+ ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
+
+checkcodebase: locate-checkpatch
+ @echo " CHECKING STYLE"
+ @if test -d .git ; then \
+ git ls-files | while read GIT_FILE ; do ${CHECKPATCH} ${CHECKCODE_ARGS} -f $$GIT_FILE ; done ; \
+ else \
+ find . -type f -not -iwholename "*.git*" -not -iwholename "*build*" -exec ${CHECKPATCH} ${CHECKCODE_ARGS} -f {} \; ; \
+ fi
+
+checkpatch: locate-checkpatch
+ @echo " CHECKING STYLE"
+ @git format-patch --stdout ${BASE_COMMIT} | ${CHECKPATCH} ${CHECKPATCH_ARGS} - || true
+
+${FIPTOOL}:
+ ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH}
+ @echo
+ @echo "Built $@ successfully"
+ @echo
+
+define match_goals
+$(strip $(foreach goal,$(1),$(filter $(goal),$(MAKECMDGOALS))))
+endef
+
+# List of rules that involve building things
+BUILD_TARGETS := all bl1 bl2 bl31 bl32 fip
+
+# Does the list of goals specified on the command line include a build target?
+ifneq ($(call match_goals,${BUILD_TARGETS}),)
+IS_ANYTHING_TO_BUILD := 1
+endif
+
+define MAKE_C
+
+$(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2))))
+$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ)))
+
+$(OBJ) : $(2)
+ @echo " CC $$<"
+ $$(Q)$$(CC) $$(CFLAGS) -c $$< -o $$@
+
+
+$(PREREQUISITES) : $(2)
+ @echo " DEPS $$@"
+ @mkdir -p $(1)
+ $$(Q)$$(CC) $$(CFLAGS) -M -MT $(OBJ) -MF $$@ $$<
+
+ifdef IS_ANYTHING_TO_BUILD
+-include $(PREREQUISITES)
+endif
+
+endef
+
+
+define MAKE_S
+
+$(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2))))
+$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ)))
+
+$(OBJ) : $(2)
+ @echo " AS $$<"
+ $$(Q)$$(AS) $$(ASFLAGS) -c $$< -o $$@
+
+$(PREREQUISITES) : $(2)
+ @echo " DEPS $$@"
+ @mkdir -p $(1)
+ $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(OBJ) -MF $$@ $$<
+
+ifdef IS_ANYTHING_TO_BUILD
+-include $(PREREQUISITES)
+endif
+
+endef
+
+
+define MAKE_LD
+
+$(eval PREREQUISITES := $(1).d)
+
+$(1) : $(2)
+ @echo " PP $$<"
+ $$(Q)$$(AS) $$(ASFLAGS) -P -E -o $$@ $$<
+
+$(PREREQUISITES) : $(2)
+ @echo " DEPS $$@"
+ @mkdir -p $$(dir $$@)
+ $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(1) -MF $$@ $$<
+
+ifdef IS_ANYTHING_TO_BUILD
+-include $(PREREQUISITES)
+endif
+
+endef
+
+
+define MAKE_OBJS
+ $(eval C_OBJS := $(filter %.c,$(2)))
+ $(eval REMAIN := $(filter-out %.c,$(2)))
+ $(eval $(foreach obj,$(C_OBJS),$(call MAKE_C,$(1),$(obj))))
+
+ $(eval S_OBJS := $(filter %.S,$(REMAIN)))
+ $(eval REMAIN := $(filter-out %.S,$(REMAIN)))
+ $(eval $(foreach obj,$(S_OBJS),$(call MAKE_S,$(1),$(obj))))
+
+ $(and $(REMAIN),$(error Unexpected source files present: $(REMAIN)))
+endef
+
+
+# NOTE: The line continuation '\' is required in the next define otherwise we
+# end up with a line-feed characer at the end of the last c filename.
+# Also bare this issue in mind if extending the list of supported filetypes.
+define SOURCES_TO_OBJS
+ $(notdir $(patsubst %.c,%.o,$(filter %.c,$(1)))) \
+ $(notdir $(patsubst %.S,%.o,$(filter %.S,$(1))))
+endef
+
+define MAKE_BL
+ $(eval BUILD_DIR := ${BUILD_PLAT})
+ $(eval SOURCES := $(SOURCES))
+ $(eval OBJS := $(addprefix $(BUILD_DIR)/,$(call SOURCES_TO_OBJS,$(SOURCES))))
+ $(eval LINKERFILE := $(BUILD_DIR)/acs.ld)
+ $(eval MAPFILE := $(BUILD_DIR)/acs.map)
+ $(eval ELF := $(BUILD_DIR)/acs.elf)
+ $(eval DUMP := $(BUILD_DIR)/acs.dump)
+ $(eval BIN := $(BUILD_DIR)/acs.bin)
+
+ $(eval $(call MAKE_OBJS,$(BUILD_DIR),$(SOURCES)))
+ $(eval $(call MAKE_LD,$(LINKERFILE),$(LINKERFILE_T)))
+
+$(BUILD_DIR) :
+ $$(Q)mkdir -p "$$@"
+
+$(ELF) : $(OBJS) $(LINKERFILE)
+ @echo " LD $$@"
+ @echo 'const char build_message[] = "Built : "__TIME__", "__DATE__". \\nver:${GIT_VERSION} - ${BUILDER}";' | \
+ $$(CC) $$(CFLAGS) -xc - -o $(BUILD_DIR)/build_message.o
+ $$(Q)$$(LD) -o $$@ $$(LDFLAGS) -Map=$(MAPFILE) --script $(LINKERFILE) \
+ $(BUILD_DIR)/build_message.o $(OBJS)
+
+$(DUMP) : $(ELF)
+ @echo " OD $$@"
+ $${Q}$${OD} -dxS $$< > $$@
+
+$(BIN) : $(ELF)
+ @echo " BIN $$@"
+ $$(Q)$$(OC) -O binary $$< $$@
+ @echo
+ @echo "Built $$@ successfully"
+ @echo
+
+.PHONY : bl$(1)
+bl$(1) : $(BUILD_DIR) $(DUMP) $(BIN)
+
+all : bl$(1)
+
+$(eval FIP_DEPS += $(if $2,$(BIN),))
+$(eval FIP_ARGS += $(if $2,--bl$(1) $(BIN),))
+
+endef
+
+ifeq (${NEED_BL2},yes)
+$(eval $(call MAKE_BL,2,in_fip))
+endif
+
+${BUILD_PLAT}/fip.bin: ${FIP_DEPS} ${BL33} ${FIPTOOL}
+ $(if ${BL33},,$(error "To build a FIP, please set BL33 to point to the Normal World binary, eg: BL33=../uefi/FVP_AARCH64_EFI.fd"))
+ ${Q}${FIPTOOL} --dump \
+ ${FIP_ARGS} \
+ --bl33 ${BL33} \
+ $@
+ @echo
+ @echo "Built $@ successfully"
+ @echo
+
+
+cscope:
+ @echo " CSCOPE"
+ ${Q}find ${CURDIR} -name "*.[chsS]" > cscope.files
+ ${Q}cscope -b -q -k
+
+help:
+ @echo "usage: ${MAKE} PLAT=<${HELP_PLATFORMS}> <all|bl1|bl2|bl31|distclean|clean|checkcodebase|checkpatch>"
+ @echo ""
+ @echo "PLAT is used to specify which platform you wish to build."
+ @echo "If no platform is specified, PLAT defaults to: ${DEFAULT_PLAT}"
+ @echo ""
+ @echo "Supported Targets:"
+ @echo " all Build the BL1, BL2 and BL31 binaries"
+ @echo " bl1 Build the BL1 binary"
+ @echo " bl2 Build the BL2 binary"
+ @echo " bl31 Build the BL31 binary"
+ @echo " checkcodebase Check the coding style of the entire source tree"
+ @echo " checkpatch Check the coding style on changes in the current"
+ @echo " branch against BASE_COMMIT (default origin/master)"
+ @echo " clean Clean the build for the selected platform"
+ @echo " cscope Generate cscope index"
+ @echo " distclean Remove all build artifacts for all platforms"
+ @echo " fiptool Build the Firmware Image Package(FIP) creation tool"
+ @echo ""
+ @echo "note: most build targets require PLAT to be set to a specific platform."
+ @echo ""
+ @echo "example: build all targets for the FVP platform:"
+ @echo " CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp all"
diff --git a/arch/arm/mach-meson/c2/firmware/acs/acs.c b/arch/arm/mach-meson/c2/firmware/acs/acs.c
new file mode 100644
index 0000000..76869b3
--- /dev/null
+++ b/arch/arm/mach-meson/c2/firmware/acs/acs.c
@@ -0,0 +1,51 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <version.h>
+#include <asm/arch/acs.h>
+#include <asm/arch/timing.h>
+#include "timing.c"
+
+//main acs struct
+acs_set_t __acs_set={
+ .acs_magic = "acs__",
+ .chip_type = 0x0,
+ .version = 1,
+ .acs_set_length = sizeof(__acs_set),
+
+ .ddr_magic = "ddrs_",
+ .ddr_set_version= 1,
+ .ddr_set_length = sizeof(__ddr_setting),
+ .ddr_set_addr = (unsigned long)(&__ddr_setting),
+
+ .ddr_reg_magic = "ddrr_",
+ .ddr_reg_version= 1,
+ .ddr_reg_length = sizeof(__ddr_reg),
+ .ddr_reg_addr = (unsigned long)(&__ddr_reg),
+
+ .pll_magic = "pll__",
+ .pll_set_version= 1,
+ .pll_set_length = sizeof(__pll_setting),
+ .pll_set_addr = (unsigned long)(&__pll_setting),
+
+ .sto_magic = "store",
+ .sto_set_version= 1,
+ .sto_set_length = 0,
+ .sto_set_addr = 0,
+
+ .bl2_regs_magic = "bl2r_",
+ .bl2_regs_version = 1,
+ .bl2_regs_length = sizeof(__bl2_reg),
+ .bl2_regs_addr = (unsigned long)(&__bl2_reg),
+
+ .rsv_magic = "rsv0_",
+ .rsv_set_version= 1,
+ .rsv_set_length = 0,
+ .rsv_set_addr = 0,
+ .board_id = {0,},
+ .ddr_struct_size = {0,},
+ .ddr_struct_org_size = sizeof(ddr_set_t),
+ .revision = ACS_VERSION,
+};
diff --git a/arch/arm/mach-meson/c2/firmware/acs/acs.ld.S b/arch/arm/mach-meson/c2/firmware/acs/acs.ld.S
new file mode 100644
index 0000000..3e5bf1d
--- /dev/null
+++ b/arch/arm/mach-meson/c2/firmware/acs/acs.ld.S
@@ -0,0 +1,19 @@
+
+OUTPUT_FORMAT("elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(acs_entry)
+
+SECTIONS
+{
+ . = 0xFFFF6000;
+
+ . : {
+ __RO_START__ = .;
+ *acs_entry.o(.text*)
+ *(.text*)
+ *(.data*)
+ *(.ddr_settings*)
+ }
+
+ //ASSERT(. <= 0xFFFF7000, "timing image has exceeded its limit.")
+}
diff --git a/arch/arm/mach-meson/c2/firmware/acs/acs.mk b/arch/arm/mach-meson/c2/firmware/acs/acs.mk
new file mode 100644
index 0000000..0c63194
--- /dev/null
+++ b/arch/arm/mach-meson/c2/firmware/acs/acs.mk
@@ -0,0 +1,9 @@
+SOURCES += acs_entry.S
+
+ifdef CONFIG_MDUMP_COMPRESS
+SOURCES += ramdump.c
+endif
+
+SOURCES += acs.c
+
+LINKERFILE_T := acs.ld.S
diff --git a/arch/arm/mach-meson/c2/firmware/acs/acs_entry.S b/arch/arm/mach-meson/c2/firmware/acs/acs_entry.S
new file mode 100644
index 0000000..feca813
--- /dev/null
+++ b/arch/arm/mach-meson/c2/firmware/acs/acs_entry.S
@@ -0,0 +1,14 @@
+
+ .globl acs_entry
+
+acs_entry:
+ .word 0
+ .word __acs_set
+#ifdef CONFIG_MDUMP_COMPRESS
+ .word __ramdump_data
+ .word __ddr_setting
+#else
+ .word 0x0
+ .word __ddr_setting
+#endif
+
diff --git a/arch/arm/mach-meson/c2/firmware/bl21/Makefile b/arch/arm/mach-meson/c2/firmware/bl21/Makefile
new file mode 100644
index 0000000..3c121d8
--- /dev/null
+++ b/arch/arm/mach-meson/c2/firmware/bl21/Makefile
@@ -0,0 +1,3 @@
+all:
+ @echo "BL21 no action for C2 "
+
diff --git a/arch/arm/mach-meson/c2/firmware/scp_task/Makefile b/arch/arm/mach-meson/c2/firmware/scp_task/Makefile
new file mode 100644
index 0000000..efa820c
--- /dev/null
+++ b/arch/arm/mach-meson/c2/firmware/scp_task/Makefile
@@ -0,0 +1,3 @@
+all:
+ @echo "BL301 no action for C2"
+
diff --git a/arch/arm/mach-meson/c2/gate_init.c b/arch/arm/mach-meson/c2/gate_init.c
new file mode 100644
index 0000000..31629f6
--- /dev/null
+++ b/arch/arm/mach-meson/c2/gate_init.c
@@ -0,0 +1,366 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "power_gate.h"
+
+#define SECUREBOOT_FLAG_ADDR 0xc8100228
+
+#ifdef CONFIG_AML_CVBS
+extern unsigned int cvbs_mode;
+#endif
+void ee_gate_off(void)
+{
+ printf("ee_gate_off ...\n");
+ return;
+/* int secureboot = readl(SECUREBOOT_FLAG_ADDR)&(1<<5);*/
+
+#ifdef CONFIG_AML_CVBS
+ unsigned int cvbs_opened = 0;
+#endif
+
+#ifdef CONFIG_AML_CVBS
+ if ((cvbs_mode == 0) || (cvbs_mode == 1))
+ cvbs_opened = 1;
+#endif
+
+ /*
+ //if close , audio maybe have noise
+ CLK_GATE_OFF(AUD);
+ CLK_GATE_OFF(AUD2);
+ CLK_GATE_OFF(AUD_CLK_2);
+ CLK_GATE_OFF(AUD_CLK_3);
+ */
+ CLK_GATE_OFF(AUD_IN);
+ CLK_GATE_OFF(AIU_AUD_MIXER);
+ CLK_GATE_OFF(SANA);
+
+ /*kernel will reopen */
+ CLK_GATE_OFF(CTS_ENCL);
+ /* CLK_GATE_OFF(CTS_ENCT); */
+#if 0 /* HDMITX 480i60hz/576i50hz need this gate */
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0)
+ CLK_GATE_OFF(CTS_ENCI);
+#else
+ CLK_GATE_OFF(CTS_ENCI);
+#endif
+#endif
+ /* CLK_GATE_OFF(CTS_ENCP); */
+
+ /*close cvbs clock*/
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0) {
+ CLK_GATE_OFF(DAC_CLK);
+ CLK_GATE_OFF(CTS_VDAC);
+ }
+#else
+ CLK_GATE_OFF(DAC_CLK);
+ CLK_GATE_OFF(CTS_VDAC);
+#endif
+
+ /* usb clock close */
+ CLK_GATE_OFF(USB0);
+ CLK_GATE_OFF(USB1);
+ //CLK_GATE_OFF(USB_CLK); //g12a no reg
+ CLK_GATE_OFF(MISC_USB0_TO_DDR);
+ CLK_GATE_OFF(MISC_USB1_TO_DDR);
+
+ /* uarts close */
+ CLK_GATE_OFF(UART0);
+ CLK_GATE_OFF(UART1);
+ CLK_GATE_OFF(UART2);
+ CLK_GATE_OFF(UART3);
+
+ CLK_GATE_OFF(VCLK2_VENCP);
+ CLK_GATE_OFF(VCLK2_VENCT);
+ CLK_GATE_OFF(VCLK2_VENCT1);
+ CLK_GATE_OFF(VCLK2_OTHER);
+#if 0 /* HDMITX 480i60hz/576i50hz need HHI_GCLK_OTHER[8][2] */
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0) {
+ CLK_GATE_OFF(VCLK2_VENCI);
+ CLK_GATE_OFF(VCLK2_VENCI1);
+ }
+#else
+ CLK_GATE_OFF(VCLK2_VENCI);
+ CLK_GATE_OFF(VCLK2_VENCI1);
+#endif
+#endif
+ CLK_GATE_OFF(VCLK2_VENCL);
+ CLK_GATE_OFF(VCLK2_OTHER1);
+#if 0 /* HDMITX 480i60hz/576i50hz need HHI_GCLK_OTHER[8][2] */
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0)
+ CLK_GATE_OFF(VCLK2_ENCI);
+#else
+ CLK_GATE_OFF(VCLK2_ENCI);
+#endif
+#endif
+ CLK_GATE_OFF(VCLK2_ENCL);
+ CLK_GATE_OFF(VCLK2_ENCT);
+
+ CLK_GATE_OFF(VDEC_CLK_1);
+ CLK_GATE_OFF(VDEC_CLK_2);
+ CLK_GATE_OFF(VDEC2_CLK_1);
+ CLK_GATE_OFF(VDEC2_CLK_2);
+ CLK_GATE_OFF(HCODEC_CLK_1);
+ CLK_GATE_OFF(HCODEC_CLK_2);
+ /* CLK_GATE_OFF(HEVC_CLK_1 ); */
+ /* CLK_GATE_OFF(HEVC_CLK_2 ); */
+
+ //CLK_GATE_OFF(MMC_A_PCLK); //g12a no reg
+ //CLK_GATE_OFF(MMC_B_PCLK); //g12a no reg
+ //CLK_GATE_OFF(MMC_C_PCLK); //g12a no reg
+
+ CLK_GATE_OFF(LCD_AN_PHY2);
+ CLK_GATE_OFF(LCD_AN_PHY3);
+
+ CLK_GATE_OFF(ETHERNET);
+ //CLK_GATE_OFF(ETH_CLK); //g12a no reg
+
+ CLK_GATE_OFF(GE2D);
+ CLK_GATE_OFF(GEN_CLK);
+ //CLK_GATE_OFF(PCM_MCLK); //g12a no reg
+ //CLK_GATE_OFF(PCM_SCLK); //g12a no reg
+
+
+ CLK_GATE_OFF(HIU_PARSER_TOP);
+
+
+ /* can not off nand_clk */
+ /* CLK_GATE_OFF(NAND_CLK); */
+ /*
+ //HDMI no output
+ CLK_GATE_OFF(VCLK2_VENCP1);
+ CLK_GATE_OFF(VCLK2_ENCP);
+ */
+
+ /*
+ //if OFF, HDMI will report error!
+ CLK_GATE_OFF(HDMI_PCLK);
+ CLK_GATE_OFF(HDMI_PLL_CNTL);
+ CLK_GATE_OFF(HDMITX_CLK);
+ */
+
+ /*
+ //PWM B used for VCCK,PWM D used for VDDEE,ignoring
+ CLK_GATE_OFF(PWM_A_CLK);
+ CLK_GATE_OFF(PWM_B_CLK);
+ CLK_GATE_OFF(PWM_C_CLK);
+ CLK_GATE_OFF(PWM_D_CLK);
+ CLK_GATE_OFF(PWM_E_CLK);
+ CLK_GATE_OFF(PWM_F_CLK);
+ */
+
+
+ /* can not close
+ CLK_GATE_OFF(VPU_CLK_1);
+ CLK_GATE_OFF(VPU_CLK_2);
+ CLK_GATE_OFF(VPU_CLKB);
+ CLK_GATE_OFF(MALI_CLK_1);
+ CLK_GATE_OFF(MALI_CLK_2);
+ CLK_GATE_OFF(ATV_DEMO_VDAC);
+ CLK_GATE_OFF(EMMC_A);
+ CLK_GATE_OFF(EMMC_B);
+ CLK_GATE_OFF(EMMC_C);
+ CLK_GATE_OFF(EMMC_A_CLK);
+ CLK_GATE_OFF(EMMC_B_CLK);
+
+ CLK_GATE_OFF(MSR_CLK);
+ CLK_GATE_OFF(MSR_HS_CLK);
+ CLK_GATE_OFF(32K_CLK);
+ CLK_GATE_OFF(VAPB_CLK_1);
+ CLK_GATE_OFF(VAPB_CLK_2);
+ CLK_GATE_OFF(GIC);
+ CLK_GATE_OFF(I2C_AO); //no close for to use
+ CLK_GATE_OFF(AO_CPU);
+ CLK_GATE_OFF(ASSIST_MISC);
+ CLK_GATE_OFF(HIU_PARSER);
+ CLK_GATE_OFF(PERIPHS_TOP);
+ CLK_GATE_OFF(PL310_CBUS);
+ CLK_GATE_OFF(ISA);
+ CLK_GATE_OFF(SECURE_AHP_APB3);
+ CLK_GATE_OFF(VPU_INTR);
+ CLK_GATE_OFF(MMC_PCLK); //can not close
+ CLK_GATE_OFF(AIU_PCLK);
+ //can not connect pc
+ CLK_GATE_OFF(USB_GENERAL);
+ CLK_GATE_OFF(AHB_DATA_BUS);
+ CLK_GATE_OFF(AHB_CONTROL_BUS);
+ CLK_GATE_OFF(HDMI_INTR_SYNC); //should open
+ //can't suspend @ 2nd time
+ //CLK_GATE_OFF(RESET);
+
+ // close rom
+ //disable this bit will make other cpu can not be booted.
+ //CLK_GATE_OFF(ROM_CLK);
+
+*/
+ /*************************/
+ CLK_GATE_OFF(AHB_ARB0);
+ CLK_GATE_OFF(ASYNC_FIFO);
+ CLK_GATE_OFF(STREAM);
+ CLK_GATE_OFF(RANDOM_NUM_GEN);
+ CLK_GATE_OFF(RANDOM_NUM_GEN1);
+ CLK_GATE_OFF(SMART_CARD_MPEG_DOMAIN);
+ CLK_GATE_OFF(I2C);
+ CLK_GATE_OFF(SPI);
+ CLK_GATE_OFF(SPICC);
+ CLK_GATE_OFF(DOS);
+ CLK_GATE_OFF(SAR_ADC);
+ CLK_GATE_OFF(MISC_DVIN);
+ CLK_GATE_OFF(BT656);
+ CLK_GATE_OFF(BT656_2);
+ CLK_GATE_OFF(PDM);
+
+ /* close AIU */
+ CLK_GATE_OFF(AIU_IEC958);
+ CLK_GATE_OFF(AIU_ICE958_AMCLK);
+
+ CLK_GATE_OFF(AIU_AMCLK_MEASURE);
+ CLK_GATE_OFF(AIU_AIFIFO2);
+ CLK_GATE_OFF(AIU_MIXER_REG);
+ CLK_GATE_OFF(AIU_ADC);
+ CLK_GATE_OFF(AIU_TOP_LEVEL);
+ CLK_GATE_OFF(AIU_AOCLK);
+ CLK_GATE_OFF(AIU_AI_TOP_GLUE);
+ CLK_GATE_OFF(AIU_I2S_OUT);
+
+ CLK_GATE_OFF(ENC480P);
+
+ CLK_GATE_OFF(DEMUX);
+/*
+* EFUSE/BLK_MOV clock gate must be on,
+ kernel storage ops depend on them.
+ it can be reference PD#112732
+*/
+/*
+ if (secureboot) {
+ printf("secure boot ignore [ BLK_MOV, efuse ] clk gate\n");
+ } else {
+ CLK_GATE_OFF(EFUSE);
+ CLK_GATE_OFF(BLK_MOV);
+ }
+*/
+}
+
+void ee_gate_on(void)
+{
+
+ printf("ee_gate_on ...\n");
+
+ /*
+ //if close , audio maybe have noise
+ CLK_GATE_ON(AUD);
+ CLK_GATE_ON(AUD2);
+ CLK_GATE_ON(AUD_CLK_2);
+ CLK_GATE_ON(AUD_CLK_3);
+ */
+ CLK_GATE_ON(AUD_IN);
+ CLK_GATE_ON(AIU_AUD_MIXER);
+ CLK_GATE_ON(SANA);
+
+ /*kernel will reopen */
+ CLK_GATE_ON(CTS_ENCL);
+ /* CLK_GATE_ON(CTS_ENCT); */
+ CLK_GATE_ON(CTS_ENCI);
+ /* CLK_GATE_ON(CTS_ENCP); */
+
+ /*close cvbs clock*/
+ CLK_GATE_ON(DAC_CLK);
+ CLK_GATE_ON(CTS_VDAC);
+
+ /* usb clock close */
+ CLK_GATE_ON(USB0);
+ CLK_GATE_ON(USB1);
+ //CLK_GATE_ON(USB_CLK); //g12a no reg
+ CLK_GATE_ON(MISC_USB0_TO_DDR);
+ CLK_GATE_ON(MISC_USB1_TO_DDR);
+
+ /* uarts close */
+ CLK_GATE_ON(UART0);
+ CLK_GATE_ON(UART1);
+ CLK_GATE_ON(UART2);
+ CLK_GATE_ON(UART3);
+
+ CLK_GATE_ON(VCLK2_VENCP);
+ CLK_GATE_ON(VCLK2_VENCT);
+ CLK_GATE_ON(VCLK2_VENCT1);
+ CLK_GATE_ON(VCLK2_OTHER);
+ CLK_GATE_ON(VCLK2_VENCI);
+ CLK_GATE_ON(VCLK2_VENCI1);
+ CLK_GATE_ON(VCLK2_VENCL);
+ CLK_GATE_ON(VCLK2_OTHER1);
+
+
+ CLK_GATE_ON(VCLK2_ENCI);
+ CLK_GATE_ON(VCLK2_ENCL);
+ CLK_GATE_ON(VCLK2_ENCT);
+
+ CLK_GATE_ON(VDEC_CLK_1);
+ CLK_GATE_ON(VDEC_CLK_2);
+ CLK_GATE_ON(VDEC2_CLK_1);
+ CLK_GATE_ON(VDEC2_CLK_2);
+ CLK_GATE_ON(HCODEC_CLK_1);
+ CLK_GATE_ON(HCODEC_CLK_2);
+ /* CLK_GATE_ON(HEVC_CLK_1 ); */
+ /* CLK_GATE_ON(HEVC_CLK_2 ); */
+
+ //CLK_GATE_ON(MMC_A_PCLK); //g12a no reg
+ //CLK_GATE_ON(MMC_B_PCLK); //g12a no reg
+ //CLK_GATE_ON(MMC_C_PCLK); //g12a no reg
+
+ CLK_GATE_ON(LCD_AN_PHY2);
+ CLK_GATE_ON(LCD_AN_PHY3);
+
+ CLK_GATE_ON(ETHERNET);
+ //CLK_GATE_ON(ETH_CLK); //g12a no reg
+
+ CLK_GATE_ON(GE2D);
+ CLK_GATE_ON(GEN_CLK);
+ //CLK_GATE_ON(PCM_MCLK); //g12a no reg
+ //CLK_GATE_ON(PCM_SCLK); //g12a no reg
+
+
+ CLK_GATE_ON(HIU_PARSER_TOP);
+
+ /*************************/
+ CLK_GATE_ON(AHB_ARB0);
+ CLK_GATE_ON(ASYNC_FIFO);
+ CLK_GATE_ON(STREAM);
+ CLK_GATE_ON(RANDOM_NUM_GEN);
+ CLK_GATE_ON(RANDOM_NUM_GEN1);
+ CLK_GATE_ON(SMART_CARD_MPEG_DOMAIN);
+ CLK_GATE_ON(I2C);
+ CLK_GATE_ON(SPI);
+ CLK_GATE_ON(SPICC);
+ CLK_GATE_ON(DOS);
+ CLK_GATE_ON(SAR_ADC);
+ CLK_GATE_ON(MISC_DVIN);
+ CLK_GATE_ON(BT656);
+ CLK_GATE_ON(BT656_2);
+ CLK_GATE_ON(PDM);
+
+ /* close AIU */
+ CLK_GATE_ON(AIU_IEC958);
+ CLK_GATE_ON(AIU_ICE958_AMCLK);
+
+ CLK_GATE_ON(AIU_AMCLK_MEASURE);
+ CLK_GATE_ON(AIU_AIFIFO2);
+ CLK_GATE_ON(AIU_MIXER_REG);
+ CLK_GATE_ON(AIU_ADC);
+ CLK_GATE_ON(AIU_TOP_LEVEL);
+ CLK_GATE_ON(AIU_AOCLK);
+ CLK_GATE_ON(AIU_AI_TOP_GLUE);
+ CLK_GATE_ON(AIU_I2S_OUT);
+
+ CLK_GATE_ON(ENC480P);
+
+ CLK_GATE_ON(DEMUX);
+
+ CLK_GATE_ON(EFUSE);
+ CLK_GATE_ON(BLK_MOV);
+}
+
diff --git a/arch/arm/mach-meson/c2/gpio.c b/arch/arm/mach-meson/c2/gpio.c
new file mode 100644
index 0000000..7332773
--- /dev/null
+++ b/arch/arm/mach-meson/c2/gpio.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <linux/compiler.h>
+#include <amlogic/aml_gpio.h>
+#include <asm/arch/gpio.h>
+
+struct pin_mux_desc {
+ unsigned char domain;
+ unsigned char reg;
+ unsigned char bit;
+};
+
+#define MUX_AO_DOMAIN 0
+#define MUX_EE_DOMAIN 1
+
+#define PIN_MUX(d, r, b) \
+{ \
+ .domain = d, \
+ .reg = r, \
+ .bit = b, \
+}
+
+#define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
+{ \
+ .name = n, \
+ .first = f, \
+ .last = l, \
+ .regs = { \
+ [REG_PULLEN] = { (0xff634520 + (per<<2)), peb }, \
+ [REG_PULL] = { (0xff6344e8 + (pr<<2)), pb }, \
+ [REG_DIR] = { (0xff634440 + (dr<<2)), db }, \
+ [REG_OUT] = { (0xff634440 + (or<<2)), ob }, \
+ [REG_IN] = { (0xff634440 + (ir<<2)), ib }, \
+ }, \
+ }
+#define AOBANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
+{ \
+ .name = n, \
+ .first = f, \
+ .last = l, \
+ .regs = { \
+ [REG_PULLEN] = { (0xff800024 + (per<<2)), peb }, \
+ [REG_PULL] = { (0xff800024 + (pr<<2)), pb }, \
+ [REG_DIR] = { (0xff800024 + (dr<<2)), db }, \
+ [REG_OUT] = { (0xff800024 + (or<<2)), ob }, \
+ [REG_IN] = { (0xff800024 + (ir<<2)), ib }, \
+ }, \
+ }
+
+static struct pin_mux_desc pin_to_gpio[] = {
+ [GPIOAO(GPIOAO_0)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 0),
+ [GPIOAO(GPIOAO_1)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 4),
+ [GPIOAO(GPIOAO_2)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 8),
+ [GPIOAO(GPIOAO_3)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 12),
+ [GPIOAO(GPIOAO_4)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 16),
+ [GPIOAO(GPIOAO_5)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 20),
+ [GPIOAO(GPIOAO_6)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 24),
+ [GPIOAO(GPIOAO_7)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 28),
+ [GPIOAO(GPIOAO_8)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 0),
+ [GPIOAO(GPIOAO_9)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 4),
+ [GPIOAO(GPIOAO_10)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 8),
+ [GPIOAO(GPIOAO_11)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 12),
+ [GPIOAO(GPIOE_0)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 16),
+ [GPIOAO(GPIOE_1)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 20),
+ [GPIOAO(GPIOE_2)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 24),
+ [GPIOEE(GPIOZ_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 0),
+ [GPIOEE(GPIOZ_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 4),
+ [GPIOEE(GPIOZ_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 8),
+ [GPIOEE(GPIOZ_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 12),
+ [GPIOEE(GPIOZ_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 16),
+ [GPIOEE(GPIOZ_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 20),
+ [GPIOEE(GPIOZ_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 24),
+ [GPIOEE(GPIOZ_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 28),
+ [GPIOEE(GPIOZ_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 0),
+ [GPIOEE(GPIOZ_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 4),
+ [GPIOEE(GPIOZ_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 8),
+ [GPIOEE(GPIOZ_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 12),
+ [GPIOEE(GPIOZ_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 16),
+ [GPIOEE(GPIOZ_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 20),
+ [GPIOEE(GPIOZ_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 24),
+ [GPIOEE(GPIOZ_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 28),
+ [GPIOEE(GPIOH_0)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 0),
+ [GPIOEE(GPIOH_1)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 4),
+ [GPIOEE(GPIOH_2)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 8),
+ [GPIOEE(GPIOH_3)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 12),
+ [GPIOEE(GPIOH_4)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 16),
+ [GPIOEE(GPIOH_5)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 20),
+ [GPIOEE(GPIOH_6)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 24),
+ [GPIOEE(GPIOH_7)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 28),
+ [GPIOEE(GPIOH_8)] = PIN_MUX(MUX_EE_DOMAIN, 0xc, 0),
+ [GPIOEE(BOOT_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 0),
+ [GPIOEE(BOOT_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 4),
+ [GPIOEE(BOOT_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 8),
+ [GPIOEE(BOOT_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 12),
+ [GPIOEE(BOOT_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 16),
+ [GPIOEE(BOOT_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 20),
+ [GPIOEE(BOOT_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 24),
+ [GPIOEE(BOOT_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 28),
+ [GPIOEE(BOOT_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 0),
+ [GPIOEE(BOOT_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 4),
+ [GPIOEE(BOOT_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 8),
+ [GPIOEE(BOOT_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 12),
+ [GPIOEE(BOOT_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 16),
+ [GPIOEE(BOOT_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 20),
+ [GPIOEE(BOOT_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 24),
+ [GPIOEE(BOOT_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 28),
+ [GPIOEE(GPIOC_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 0),
+ [GPIOEE(GPIOC_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 4),
+ [GPIOEE(GPIOC_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 8),
+ [GPIOEE(GPIOC_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 12),
+ [GPIOEE(GPIOC_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 16),
+ [GPIOEE(GPIOC_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 20),
+ [GPIOEE(GPIOC_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 24),
+ [GPIOEE(GPIOC_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 28),
+ [GPIOEE(GPIOA_0)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 0),
+ [GPIOEE(GPIOA_1)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 4),
+ [GPIOEE(GPIOA_2)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 8),
+ [GPIOEE(GPIOA_3)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 12),
+ [GPIOEE(GPIOA_4)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 16),
+ [GPIOEE(GPIOA_5)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 20),
+ [GPIOEE(GPIOA_6)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 24),
+ [GPIOEE(GPIOA_7)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 28),
+ [GPIOEE(GPIOA_8)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 0),
+ [GPIOEE(GPIOA_9)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 4),
+ [GPIOEE(GPIOA_10)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 8),
+ [GPIOEE(GPIOA_11)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 12),
+ [GPIOEE(GPIOA_12)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 16),
+ [GPIOEE(GPIOA_13)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 20),
+ [GPIOEE(GPIOA_14)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 24),
+ [GPIOEE(GPIOA_15)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 28),
+ [GPIOEE(GPIOX_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 0),
+ [GPIOEE(GPIOX_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 4),
+ [GPIOEE(GPIOX_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 8),
+ [GPIOEE(GPIOX_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 12),
+ [GPIOEE(GPIOX_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 16),
+ [GPIOEE(GPIOX_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 20),
+ [GPIOEE(GPIOX_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 24),
+ [GPIOEE(GPIOX_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 28),
+ [GPIOEE(GPIOX_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 0),
+ [GPIOEE(GPIOX_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 4),
+ [GPIOEE(GPIOX_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 8),
+ [GPIOEE(GPIOX_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 12),
+ [GPIOEE(GPIOX_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 16),
+ [GPIOEE(GPIOX_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 20),
+ [GPIOEE(GPIOX_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 24),
+ [GPIOEE(GPIOX_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 28),
+ [GPIOEE(GPIOX_16)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 0),
+ [GPIOEE(GPIOX_17)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 4),
+ [GPIOEE(GPIOX_18)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 8),
+ [GPIOEE(GPIOX_19)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 12),
+};
+/*sequence of banks keep same as arch-g12a/gpio.h*/
+static struct meson_bank mesontxhd_banks[] = {
+ /*name first last pullen pull dir out in*/
+ AOBANK("GPIOAO_", GPIOAO(GPIOAO_0), GPIOAO(GPIOAO_11),
+ 3, 0, 2, 0, 0, 0, 4, 0, 1, 0),
+ AOBANK("GPIOE_", GPIOAO(GPIOE_0), GPIOAO(GPIOE_2),
+ 3, 16, 2, 16, 0, 16, 4, 16, 1, 16),
+ BANK("GPIOZ_", GPIOEE(GPIOZ_0), GPIOEE(GPIOZ_15),
+ 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
+ BANK("GPIOH_", GPIOEE(GPIOH_0), GPIOEE(GPIOH_8),
+ 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
+ BANK("BOOT_", GPIOEE(BOOT_0), GPIOEE(BOOT_15),
+ 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
+ BANK("GPIOC_", GPIOEE(GPIOC_0), GPIOEE(GPIOC_7),
+ 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
+ BANK("GPIOA_", GPIOEE(GPIOA_0), GPIOEE(GPIOA_15),
+ 5, 0, 5, 0, 16, 0, 17, 0, 18, 0),
+ BANK("GPIOX_", GPIOEE(GPIOX_0), GPIOEE(GPIOX_19),
+ 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
+};
+
+U_BOOT_DEVICES(txhd_gpios) = {
+ { "gpio_aml", &mesontxhd_banks[0] },
+ { "gpio_aml", &mesontxhd_banks[1] },
+ { "gpio_aml", &mesontxhd_banks[2] },
+ { "gpio_aml", &mesontxhd_banks[3] },
+ { "gpio_aml", &mesontxhd_banks[4] },
+ { "gpio_aml", &mesontxhd_banks[5] },
+ { "gpio_aml", &mesontxhd_banks[6] },
+ { "gpio_aml", &mesontxhd_banks[7] },
+};
+
+static unsigned long domain[]={
+ [MUX_AO_DOMAIN] = 0xff800014,
+ [MUX_EE_DOMAIN] = 0xff6346c0,
+};
+
+int clear_pinmux(unsigned int pin)
+{
+ struct pin_mux_desc *pmux_desc = &pin_to_gpio[pin];
+
+ regmap_update_bits(domain[pmux_desc->domain] + (pmux_desc->reg << 2),
+ 0xf << (pmux_desc->bit), 0 << (pmux_desc->bit));
+
+ return 0;
+}
+
+#ifdef CONFIG_AML_SPICC
+#include <asm/arch/secure_apb.h>
+/* generic pins control for spicc1.
+ * if deleted, you have to add it into all g12a board files as necessary.
+ * GPIOH_4: MOSI:regB[19:16]=3
+ * GPIOH_5: MISO:regB[23:20]=3
+ * GPIOH_7: CLK:regB[31:28]=3
+ */
+int spicc1_pinctrl_enable(bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_B);
+ val &= ~(0xf0ff << 16);
+ if (enable)
+ val |= 0x3033 << 16;
+ writel(val, P_PERIPHS_PIN_MUX_B);
+ return 0;
+}
+#endif /* CONFIG_AML_SPICC */
diff --git a/arch/arm/mach-meson/c2/hdmitx.c b/arch/arm/mach-meson/c2/hdmitx.c
new file mode 100644
index 0000000..5292c87
--- /dev/null
+++ b/arch/arm/mach-meson/c2/hdmitx.c
@@ -0,0 +1,594 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/io.h>
+#include <asm/io.h>
+#include <amlogic/media/vout/hdmitx.h>
+#include <asm/arch/regs.h>
+#include <asm/arch/secure_apb.h>
+
+#define HDMITX_DWC_BASE_OFFSET 0xFF600000
+#define HDMITX_TOP_BASE_OFFSET 0xFF608000
+
+static int dbg_en =0;
+
+unsigned long hd_read_reg(volatile unsigned int* addr)
+{
+ unsigned long val = 0;
+
+ val = *addr;
+ if (dbg_en)
+ printk("R: 0x%8p 0x%08lx\n", addr, val);
+ return val;
+}
+
+void hd_write_reg(volatile unsigned int* addr, unsigned long val)
+{
+ *addr = val;
+ if (dbg_en)
+ printk("W: 0x%8p 0x%08lx %s 0x%08lx\n", addr,
+ val, (val == hd_read_reg(addr)) ? "==" : "!=", hd_read_reg(addr));
+}
+
+void hd_set_reg_bits(volatile unsigned int* addr, unsigned long value,
+ unsigned long offset, unsigned long len)
+{
+ unsigned long data = 0;
+
+ data = hd_read_reg(addr);
+ data &= ~(((1L << len) - 1) << offset);
+ data |= (value & ((1L << len) - 1)) << offset;
+ hd_write_reg(addr, data);
+}
+
+#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
+unsigned int hdmitx_rd_reg(unsigned int addr)
+{
+ unsigned int large_offset = addr >> 24;
+ unsigned int small_offset = addr & ((1 << 24) - 1);
+ unsigned int data = 0;
+ register long x0 asm("x0") = 0x82000018;
+ register long x1 asm("x1") = (unsigned long)addr;
+
+ if (large_offset == 0x10) {
+ large_offset = HDMITX_DWC_BASE_OFFSET;
+ data = readb((unsigned long)(large_offset + small_offset));
+ } else if (large_offset == 0x0){
+ large_offset = HDMITX_TOP_BASE_OFFSET;
+ if ((small_offset >= 0x2000) && (small_offset <= 0x365E)) {
+ data = readb((unsigned long)(large_offset + small_offset));
+ } else {
+ small_offset = small_offset << 2;
+ data = readl((unsigned long)(large_offset + small_offset));
+ }
+ } else {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r"(x0) : "r"(x1)
+ );
+ data = (unsigned)(x0&0xffffffff);
+ }
+ if (dbg_en)
+ printk("%s wr[0x%x] 0x%x\n", large_offset ? "DWC" : "TOP",
+ addr, data);
+
+ return data;
+}
+
+void hdmitx_wr_reg(unsigned int addr, unsigned int data)
+{
+ unsigned int large_offset = addr >> 24;
+ unsigned int small_offset = addr & ((1 << 24) - 1);
+ register long x0 asm("x0") = 0x82000019;
+ register long x1 asm("x1") = (unsigned long)addr;
+ register long x2 asm("x2") = data;
+
+ if (large_offset == 0x10) {
+ large_offset = HDMITX_DWC_BASE_OFFSET;
+ writeb(data & 0xff, (unsigned long)(large_offset + small_offset));
+ } else if (large_offset == 0x0){
+ large_offset = HDMITX_TOP_BASE_OFFSET;
+ if ((small_offset >= 0x2000) && (small_offset <= 0x365E)) {
+ writeb(data & 0xff,(unsigned long)(large_offset + small_offset));
+ } else {
+ small_offset = small_offset << 2;
+ writel(data,(unsigned long)(large_offset + small_offset));
+ }
+ } else {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ "smc #0\n"
+ : : "r"(x0), "r"(x1), "r"(x2)
+ );
+ }
+ if (dbg_en)
+ printk("%s wr[0x%x] 0x%x\n", large_offset ? "DWC" : "TOP",
+ addr, data);
+}
+
+void hdmitx_set_reg_bits(unsigned int addr, unsigned int value,
+ unsigned int offset, unsigned int len)
+{
+ unsigned int data32 = 0;
+
+ data32 = hdmitx_rd_reg(addr);
+ data32 &= ~(((1 << len) - 1) << offset);
+ data32 |= (value & ((1 << len) - 1)) << offset;
+ hdmitx_wr_reg(addr, data32);
+}
+
+void hdmitx_poll_reg(unsigned int addr, unsigned int val,
+ unsigned long timeout)
+{
+ udelay(2000);
+ if (!(hdmitx_rd_reg(addr) & val))
+ printk("hdmitx poll:0x%x val:0x%x t=%dms timeout\n",
+ addr, val, 2000);
+}
+
+void hdmitx_rd_check_reg (unsigned long addr,
+ unsigned long exp_data, unsigned long mask)
+{
+ unsigned long rd_data;
+ rd_data = hdmitx_rd_reg(addr);
+ if ((rd_data | mask) != (exp_data | mask)) {
+ printk("HDMITX-DWC addr=0x%04x rd_data=0x%02x\n",
+ (unsigned int)addr, (unsigned int)rd_data);
+ printk("Error: HDMITX-DWC exp_data=0x%02x mask=0x%02x\n",
+ (unsigned int)exp_data, (unsigned int)mask);
+ }
+}
+
+static void set_phy_by_mode(unsigned int mode)
+{
+ switch (mode) {
+ case 1: /* 5.94/4.5/3.7Gbps */
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x37eb5584);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x0000080b);
+ break;
+ case 2: /* 2.97Gbps */
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4262);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
+ break;
+ case 3: /* 1.485Gbps, and below */
+ default:
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0x33eb4242);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0x2ab0ff3b);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0x00000003);
+ break;
+ }
+}
+void hdmitx_set_phy(struct hdmitx_dev *hdev)
+{
+ if (!hdev)
+ return;
+
+ switch (hdev->vic) {
+ case HDMI_3840x2160p50_16x9:
+ case HDMI_3840x2160p60_16x9:
+ case HDMI_4096x2160p50_256x135:
+ case HDMI_4096x2160p60_256x135:
+ if ((hdev->para->cs == HDMI_COLOR_FORMAT_420)
+ && (hdev->para->cd == HDMI_COLOR_DEPTH_24B))
+ set_phy_by_mode(2);
+ else
+ set_phy_by_mode(1);
+ break;
+ case HDMI_3840x2160p50_16x9_Y420:
+ case HDMI_3840x2160p60_16x9_Y420:
+ case HDMI_4096x2160p50_256x135_Y420:
+ case HDMI_4096x2160p60_256x135_Y420:
+ if (hdev->para->cd == HDMI_COLOR_DEPTH_24B)
+ set_phy_by_mode(2);
+ else
+ set_phy_by_mode(1);
+ break;
+ case HDMI_3840x2160p24_16x9:
+ case HDMI_3840x2160p24_64x27:
+ case HDMI_3840x2160p25_16x9:
+ case HDMI_3840x2160p25_64x27:
+ case HDMI_3840x2160p30_16x9:
+ case HDMI_3840x2160p30_64x27:
+ case HDMI_4096x2160p24_256x135:
+ case HDMI_4096x2160p25_256x135:
+ case HDMI_4096x2160p30_256x135:
+ if ((hdev->para->cs == HDMI_COLOR_FORMAT_422)
+ || (hdev->para->cd == HDMI_COLOR_DEPTH_24B))
+ set_phy_by_mode(2);
+ else
+ set_phy_by_mode(1);
+ break;
+ case HDMI_1920x1080p60_16x9:
+ case HDMI_1920x1080p50_16x9:
+ case HDMI_1920x1080i100_16x9:
+ case HDMI_1920x1080i120_16x9:
+ case HDMI_1280x720p100_16x9:
+ case HDMI_1280x720p120_16x9:
+ default:
+ set_phy_by_mode(3);
+ break;
+ }
+/* P_HHI_HDMI_PHY_CNTL1 bit[1]: enable clock bit[0]: soft reset */
+#define RESET_HDMI_PHY() \
+do { \
+ hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0xf, 0, 4); \
+ mdelay(2); \
+ hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0xe, 0, 4); \
+ mdelay(2); \
+} while (0)
+
+ hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0x0390, 16, 16);
+ hd_set_reg_bits(P_HHI_HDMI_PHY_CNTL1, 0x0, 0, 4);
+ RESET_HDMI_PHY();
+ RESET_HDMI_PHY();
+ RESET_HDMI_PHY();
+#undef RESET_HDMI_PHY
+
+ printk("hdmitx phy setting done\n");
+}
+
+void hdmitx_turnoff(void)
+{
+ /* Close HDMITX PHY */
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL0, 0);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL3, 0);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL5, 0);
+ /* Disable HPLL */
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0);
+}
+
+#define WAIT_FOR_PLL_LOCKED(reg) \
+ do { \
+ unsigned int st = 0; \
+ int cnt = 10; \
+ while (cnt--) { \
+ udelay(50); \
+ st = (((hd_read_reg(reg) >> 30) & 0x3) == 3); \
+ if (st) \
+ break; \
+ else { \
+ /* reset hpll */ \
+ hd_set_reg_bits(reg, 1, 29, 1); \
+ hd_set_reg_bits(reg, 0, 29, 1); \
+ } \
+ } \
+ if (cnt < 9) \
+ printk("pll[0x%8p] reset %d times\n", reg, 9 - cnt);\
+ } while (0)
+
+static bool set_hpll_hclk_v1(unsigned int m, unsigned int frac_val,
+ struct hdmitx_dev *hdev)
+{
+ int ret = 0;
+
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x0b3a0400 | (m & 0xff));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x3, 28, 2);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, frac_val);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ if (frac_val == 0x8148) {
+ if (((hdev->para->vic == HDMI_3840x2160p50_16x9) ||
+ (hdev->para->vic == HDMI_3840x2160p60_16x9) ||
+ (hdev->para->vic == HDMI_3840x2160p50_64x27) ||
+ (hdev->para->vic == HDMI_3840x2160p60_64x27)) &&
+ (hdev->para->cs != HDMI_COLOR_FORMAT_420)) {
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x11551293);
+ } else {
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x44331290);
+ }
+ } else {
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a68dc00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290);
+ }
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39272000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540000);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLLv1: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+
+ ret = (((hd_read_reg(P_HHI_HDMI_PLL_CNTL0) >> 30) & 0x3) == 0x3);
+ return ret;
+}
+
+static bool set_hpll_hclk_v2(unsigned int m, unsigned int frac_val)
+{
+ int ret = 0;
+
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x0b3a0400 | (m & 0xff));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x3, 28, 2);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, frac_val);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0xea68dc00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39272000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540000);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLLv2: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+
+ ret = (((hd_read_reg(P_HHI_HDMI_PLL_CNTL0) >> 30) & 0x3) == 0x3);
+ return ret;
+}
+
+static bool set_hpll_hclk_v3(unsigned int m, unsigned int frac_val)
+{
+ int ret = 0;
+
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x0b3a0400 | (m & 0xff));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x3, 28, 2);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, frac_val);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0xea68dc00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x65771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39272000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x55540000);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLLv3: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+
+ ret = (((hd_read_reg(P_HHI_HDMI_PLL_CNTL0) >> 30) & 0x3) == 0x3);
+ return ret;
+}
+
+void set_hpll_clk_out(unsigned clk, struct hdmitx_dev *hdev)
+{
+ unsigned int frac_rate ;
+
+ frac_rate = hdev->frac_rate_policy;
+ if (clk == -1)
+ return;
+ printk("config HPLL = %d frac_rate = %d\n", clk, frac_rate);
+
+ switch (clk) {
+ case 5940000:
+ if (set_hpll_hclk_v1(0xf7, frac_rate ? 0x8148 : 0x10000, hdev))
+ break;
+ else if (set_hpll_hclk_v2(0x7b,0x18000))
+ break;
+ else if (set_hpll_hclk_v3(0xf7,0x10000))
+ break;
+ else
+ break;
+ break;
+ case 5405400:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004e1);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00007333);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 4455000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b9);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00014000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 3712500:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00049a);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00016000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x6a685c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x43231290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x29272000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x56540028);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 3450000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00048f);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 3243240:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b000487);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x0000451f);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 2970000:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b00047b);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00018000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ case 4324320:
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL0, 0x3b0004b4);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL1, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL2, 0x00000000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL3, 0x0a691c00);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL4, 0x33771290);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL5, 0x39270000);
+ hd_write_reg(P_HHI_HDMI_PLL_CNTL6, 0x50540000);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0x0, 29, 1);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ WAIT_FOR_PLL_LOCKED(P_HHI_HDMI_PLL_CNTL0);
+ printk("HPLL: 0x%lx\n", hd_read_reg(P_HHI_HDMI_PLL_CNTL0));
+ break;
+ default:
+ printk("error hpll clk: %d\n", clk);
+ break;
+ }
+ printk("config HPLL done\n");
+}
+
+void set_hpll_od1(unsigned div)
+{
+ switch (div) {
+ case 1:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0, 16, 2);
+ break;
+ case 2:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 1, 16, 2);
+ break;
+ case 4:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 2, 16, 2);
+ break;
+ default:
+ printk("Err %s[%d]\n", __func__, __LINE__);
+ break;
+ }
+}
+
+void set_hpll_od2(unsigned div)
+{
+ switch (div) {
+ case 1:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0, 18, 2);
+ break;
+ case 2:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 1, 18, 2);
+ break;
+ case 4:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 2, 18, 2);
+ break;
+ default:
+ printk("Err %s[%d]\n", __func__, __LINE__);
+ break;
+ }
+}
+
+void set_hpll_od3(unsigned div)
+{
+ switch (div) {
+ case 1:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0, 20, 2);
+ break;
+ case 2:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 1, 20, 2);
+ break;
+ case 4:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 2, 20, 2);
+ break;
+ default:
+ printk("Err %s[%d]\n", __func__, __LINE__);
+ break;
+ }
+}
+
+/* HERE MUST BE BIT OPERATION!!! */
+void set_hpll_sspll(struct hdmitx_dev *hdev)
+{
+ enum hdmi_vic vic = hdev->vic;
+
+ switch (vic) {
+ case HDMI_1920x1080p60_16x9:
+ case HDMI_1920x1080p50_16x9:
+ case HDMI_1280x720p60_16x9:
+ case HDMI_1280x720p50_16x9:
+ case HDMI_1920x1080i60_16x9:
+ case HDMI_1920x1080i50_16x9:
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 1, 29, 1);
+ /* bit[22:20] hdmi_dpll_fref_sel
+ * bit[8] hdmi_dpll_ssc_en
+ * bit[7:4] hdmi_dpll_ssc_dep_sel
+ */
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 1, 20, 3);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 1, 8, 1);
+ /* 2: 1000ppm 1: 500ppm */
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL2, 2, 4, 4);
+ /* bit[15] hdmi_dpll_sdmnc_en */
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL3, 0, 15, 1);
+ hd_set_reg_bits(P_HHI_HDMI_PLL_CNTL0, 0, 29, 1);
+ break;
+ default:
+ break;
+ }
+}
+
+void ddc_pinmux_init(void)
+{
+ hd_set_reg_bits(P_PAD_PULL_UP_EN_REG3, 0, 0, 2); /*Disable GPIOH_1/2 pull-up/down*/
+ hd_set_reg_bits(P_PAD_PULL_UP_REG3, 0, 0, 2);
+ hd_set_reg_bits(P_PREG_PAD_GPIO3_EN_N, 3, 0, 2); /*GPIOH_1/2 input*/
+ hd_set_reg_bits(P_PERIPHS_PIN_MUX_B, 0x11, 0, 8); /*Mux DDC SDA/SCL*/
+}
+
+int hdmitx_get_hpd_state(void)
+{
+ int st = 0;
+
+ st = !!(hd_read_reg(P_PREG_PAD_GPIO3_I) & (1 << 2));
+ return st;
+}
+
+void hdmitx_prbs(void)
+{
+ unsigned int i;
+
+ for (i = 0; i < 4; i ++) {
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0x0390000f);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0x0390000e);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0x03904002);
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL4, 0x0001efff | (i << 20));
+ hd_write_reg(P_HHI_HDMI_PHY_CNTL1, 0xef904002);
+ mdelay(10);
+ if (i > 0)
+ pr_info("prbs D[%d]:%lx\n", i -1, hd_read_reg(P_HHI_HDMI_PHY_STATUS));
+ else
+ pr_info("prbs clk :%lx\n",hd_read_reg(P_HHI_HDMI_PHY_STATUS));
+ }
+}
+
+void hdmitx_enable_apb3(void)
+{
+ /*g12a doesn't need enable apb3*/
+ return;
+ /*hd_set_reg_bits(P_HDMITX_CTRL_PORT, 1, 15, 1);*/
+ /*hd_set_reg_bits((P_HDMITX_CTRL_PORT + 0x10), 1, 15, 1);*/
+}
diff --git a/arch/arm/mach-meson/c2/mailbox.c b/arch/arm/mach-meson/c2/mailbox.c
new file mode 100644
index 0000000..7105170
--- /dev/null
+++ b/arch/arm/mach-meson/c2/mailbox.c
@@ -0,0 +1,194 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/arch/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/arch/mailbox.h>
+#include <asm/arch/secure_apb.h>
+
+/* Bit position for size value in MHU header */
+#define SIZE_SHIFT 20
+/* Mask to extract size value in MHU header*/
+#define SIZE_MASK 0x1ff
+
+static unsigned int *ap_mb_stat[] = {
+ (unsigned int *)HIU_MAILBOX_STAT_4,
+ (unsigned int *)HIU_MAILBOX_STAT_5,
+};
+static unsigned int *ap_mb_set[] = {
+ (unsigned int *)HIU_MAILBOX_SET_4,
+ (unsigned int *)HIU_MAILBOX_SET_5,
+};
+static unsigned int *ap_mb_clear[] = {
+ (unsigned int *)HIU_MAILBOX_CLR_4,
+ (unsigned int *)HIU_MAILBOX_CLR_5,
+};
+static unsigned int *ap_mb_payload[] = {
+ (unsigned int *)(P_SHARE_SRAM_BASE + MHU_LOW_AP_TO_SCP_PAYLOAD),
+ (unsigned int *)(P_SHARE_SRAM_BASE + MHU_HIGH_AP_TO_SCP_PAYLOAD),
+};
+static unsigned int *scp_mb_stat[] = {
+ (unsigned int *)HIU_MAILBOX_STAT_1,
+ (unsigned int *)HIU_MAILBOX_STAT_2,
+};
+/*
+static unsigned int *scp_mb_set[] = {
+ (unsigned int *)HIU_MAILBOX_SET_1,
+ (unsigned int *)HIU_MAILBOX_SET_2,
+};
+*/
+static unsigned int *scp_mb_clear[] = {
+ (unsigned int *)HIU_MAILBOX_CLR_1,
+ (unsigned int *)HIU_MAILBOX_CLR_2,
+};
+static unsigned int *scp_mb_payload[] = {
+ (unsigned int *)(P_SHARE_SRAM_BASE + MHU_LOW_SCP_TO_AP_PAYLOAD),
+ (unsigned int *)(P_SHARE_SRAM_BASE + MHU_HIGH_SCP_TO_AP_PAYLOAD),
+};
+
+static void mb_message_start(unsigned int priority)
+{
+ while (readl(ap_mb_stat[priority]) != 0)
+ ;
+}
+static void mb_message_send(unsigned int command, unsigned int priority)
+{
+ writel(command, ap_mb_set[priority]);
+ while (readl(ap_mb_stat[priority]) != 0)
+ ;
+}
+static unsigned int mb_message_wait(unsigned int priority)
+{
+ unsigned int response;
+ while (!(response = readl(scp_mb_stat[priority])))
+ ;
+ return response;
+}
+static void mb_message_end(unsigned int priority)
+{
+ writel(0xffffffff, scp_mb_clear[priority]);
+}
+static unsigned int mb_message_receive(
+ void **message_out,
+ unsigned int *size_out,
+ unsigned int priority)
+{
+ unsigned int response = mb_message_wait(priority);
+ unsigned int size = (response >> SIZE_SHIFT) & SIZE_MASK;
+
+ response &= ~(SIZE_MASK << SIZE_SHIFT);
+
+ if (size_out)
+ *size_out = size;
+ if (message_out)
+ *message_out = (void *)(scp_mb_payload[priority]);
+
+ return response;
+}
+static void mb_init(unsigned int priority)
+{
+ writel(0xffffffff, ap_mb_clear[priority]);
+}
+
+static void scpi_send32(unsigned int command,
+ unsigned int message, unsigned int priority)
+{
+ mb_init(priority);
+ mb_message_start(priority);
+ writel(message, ap_mb_payload[priority]);
+ mb_message_send(command, priority);
+ mb_message_wait(priority);
+ mb_message_end(priority);
+}
+
+static void scpi_send_block(unsigned int command,
+ unsigned int *message, unsigned int message_size, unsigned int priority)
+{
+ mb_init(priority);
+ mb_message_start(priority);
+ memcpy(ap_mb_payload[priority], message, message_size);
+ mb_message_send(command, priority);
+ mb_message_wait(priority);
+ mb_message_end(priority);
+}
+
+void open_scp_log(unsigned int channel)
+{
+ scpi_send32(SCPI_CMD_OPEN_SCP_LOG, channel, LOW_PRIORITY);
+}
+
+int send_usr_data(unsigned int clinet_id, unsigned int *val, unsigned int size)
+{
+ unsigned long command;
+
+ if (size > 0x1fd)
+ return -1;
+
+ command = ((unsigned int)SCPI_CMD_SET_USR_DATA & 0xff) | ((clinet_id & 0xff) << 8) | ((size & 0x1ff) << 20);
+ scpi_send_block(command,val,size,0);
+
+ return 0;
+}
+
+/*
+* type:
+* 0: data; 1: version
+*/
+int thermal_calibration(unsigned int type, unsigned int data)
+{
+ unsigned int *appayload = ap_mb_payload[LOW_PRIORITY];
+ unsigned int *response;
+ unsigned int size;
+
+ mb_message_start(LOW_PRIORITY);
+ writel(type, appayload);
+ writel(data, appayload+1);
+ mb_message_send(
+ ((0x8 << SIZE_SHIFT) | SCPI_CMD_THERMAL_CALIB),
+ LOW_PRIORITY);
+ mb_message_receive((void *)&response, &size, LOW_PRIORITY);
+ mb_message_end(LOW_PRIORITY);
+
+ if (*response != SCPI_SUCCESS)
+ return -1;
+ else
+ return 0;
+}
+
+int thermal_get_value(unsigned int sensor_id, unsigned int *value)
+{
+ unsigned int *response;
+ unsigned int size;
+
+ mb_message_start(LOW_PRIORITY);
+ writel(sensor_id, ap_mb_payload[LOW_PRIORITY]);
+ mb_message_send(
+ ((0x4 << SIZE_SHIFT) | SCPI_CMD_SENSOR_VALUE),
+ LOW_PRIORITY);
+ mb_message_receive((void *)&response, &size, LOW_PRIORITY);
+ mb_message_end(LOW_PRIORITY);
+
+ *value = *(response+1);
+ if (*response != SCPI_SUCCESS)
+ return -1;
+ else
+ return 0;
+}
+
+
+void send_pwm_delt(int32_t vcck_delt, int32_t ee_delt)
+{
+ unsigned int *appayload = ap_mb_payload[LOW_PRIORITY];
+ mb_message_start(LOW_PRIORITY);
+ writel(vcck_delt, appayload);
+ writel(ee_delt, appayload+1);
+ mb_message_send(SCPI_CMD_REV_PWM_DELT, LOW_PRIORITY);
+ mb_message_wait(LOW_PRIORITY);
+ mb_message_end(LOW_PRIORITY);
+}
+
diff --git a/arch/arm/mach-meson/c2/oscring.c b/arch/arm/mach-meson/c2/oscring.c
new file mode 100644
index 0000000..8a588cb
--- /dev/null
+++ b/arch/arm/mach-meson/c2/oscring.c
@@ -0,0 +1,129 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/arch/io.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/oscring.h>
+
+void ring_powerinit(void)
+{
+ writel(0x18000a, RING_PWM_VCCK);/*set vcck 0.8v*/
+ writel(0x090009, RING_PWM_EE);/*set ee 0.8v*/
+}
+
+unsigned long clk_util_ring_msr(unsigned long clk_mux)
+{
+ unsigned int regval = 0;
+
+ writel(0, MSR_CLK_REG0);
+ /* Set the measurement gate to 64uS */
+ /* 64uS is enough for measure the frequence? */
+ setbits_le32(MSR_CLK_REG0, (10000 - 1));
+ /* Disable continuous measurement */
+ /* Disable interrupts */
+ clrbits_le32(MSR_CLK_REG0, (1 << 17) | (1 << 18));
+ clrbits_le32(MSR_CLK_REG0, 0x7f << 20);
+ setbits_le32(MSR_CLK_REG0, (clk_mux) << 20 | (1 << 19) | (1 << 16));
+ /* Wait for the measurement to be done */
+ regval = readl(MSR_CLK_REG0);
+ do {
+ regval = readl(MSR_CLK_REG0);
+ } while (regval & (1 << 31));
+
+ /* Disable measuring */
+ clrbits_le32(MSR_CLK_REG0, 1 << 16);
+ regval = (readl(MSR_CLK_REG2) + 31) & 0x000fffff;
+
+ return (regval / 10);
+}
+
+int ring_msr(int index)
+{
+ const char* clk_table[] = {
+ [26] = "osc_ring_clk_top(14_rvt) " ,
+ [25] = "osc_ring_clk_top(16_lvt) " ,
+ [24] = "osc_ring_clk_top(16_rvt) " ,
+ [23] = "osc_ring_clk_isp(14_rvt) " ,
+ [22] = "osc_ring_clk_isp(16_lvt) " ,
+ [21] = "osc_ring_clk_isp(16_rvt) " ,
+ [20] = "osc_ring_clk_ddr(14_slvt) " ,
+ [19] = "osc_ring_clk_ddr(14_rvt) " ,
+ [18] = "osc_ring_clk_ddr(16_lvt) " ,
+ [17] = "osc_ring_clk_sram(14_lvt) " ,
+ [16] = "osc_ring_clk_sram(16_slvt) " ,
+ [15] = "osc_ring_clk_sram(16_lvt) " ,
+ [14] = "osc_ring_clk_dsp(14lvt) " ,
+ [13] = "osc_ring_clk_dsp(14rvt) " ,
+ [12] = "osc_ring_clk_dsp(16_rvt) " ,
+ [11] = "osc_ring_clk_dos(14_lvt) " ,
+ [10] = "osc_ring_clk_dos(14_rvt) " ,
+ [9] = "osc_ring_clk_dos(16_rvt) " ,
+ [8] = "osc_ring_clk_nna(14_lvt) " ,
+ [7] = "osc_ring_clk_nna(16_slvt) " ,
+ [6] = "osc_ring_clk_nna(16_lvt) " ,
+ [5] = "osc_ring_clk_cpu1(9T_14_slvt) " ,
+ [4] = "osc_ring_clk_cpu1(9T_14_lvt) " ,
+ [3] = "osc_ring_clk_cpu1(9T_16_slvt) " ,
+ [2] = "osc_ring_clk_cpu0(9T_14_slvt) " ,
+ [1] = "osc_ring_clk_cpu0(9T_14_lvt) " ,
+ [0] = "osc_ring_clk_cpu0(9T_16_slvt) " ,
+ };
+ const int tb[] = {93, 94, 95, 96, 97, 98, 99, 100, 101, 102, 103, 104, 105, 106, 107,
+ 108, 109, 110, 111, 112, 113, 114, 115, 116, 117, 118, 119};
+ unsigned long i;
+ uint8_t efuseinfo[8] = {0, 0, 0, 0, 0, 0, 0, 0};
+
+ if ((index != 0xff) && (index != 0)) {
+ if (bl31_get_cornerinfo(efuseinfo, sizeof(efuseinfo) / sizeof(uint8_t)) != 0) {
+ printf("fail get efuse info\n");
+ return 0;
+ }
+ if ((index >= 1) && (index <= 3))
+ printf("%d\n", efuseinfo[index]);
+ else
+ printf("input data not support!\n");
+
+ return 0;
+ }
+ if (0xff != index) {
+ ring_powerinit();
+ printf("set vcck vddee to 800mv\n");
+ }
+ /*RING_OSCILLATOR 0x7f: set slow ring*/
+ writel(OSCRING_CTL_DATA0, OSCRING_CTL_REG0);
+ writel(OSCRING_CTL_DATA1, OSCRING_CTL_REG1);
+ writel(OSCRING_CTL_DATA2, OSCRING_CTL_REG2);
+
+ for (i = 0; i < 27; i++) {
+ printf("%s :",clk_table[i]);
+ printf("%ld KHz",clk_util_ring_msr(tb[i]));
+ printf("\n");
+ }
+
+ if (bl31_get_cornerinfo(efuseinfo, sizeof(efuseinfo) / sizeof(uint8_t)) != 0) {
+ printf("fail get efuse info\n");
+ return 0;
+ }
+
+ printf("osc efuse info:\n");
+ for (i = 0; i < sizeof(efuseinfo) / sizeof(uint8_t); i++)
+ printf("0x%x, ", efuseinfo[i]);
+ printf("\n");
+
+ /*efuse to test value*/
+ printf("A35_core0(2) (14SLVT), idd_ee, idd_cpu\n");
+
+ printf("%d KHz ", (efuseinfo[1] * 50));
+
+ for (i = 2; i <=3; i++) {
+ printf("%d uA ", (efuseinfo[i] * 400));
+ }
+ printf("\n");
+
+ return 0;
+}
diff --git a/arch/arm/mach-meson/c2/pinctrl_init.c b/arch/arm/mach-meson/c2/pinctrl_init.c
new file mode 100644
index 0000000..829ce28
--- /dev/null
+++ b/arch/arm/mach-meson/c2/pinctrl_init.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm/uclass.h>
+#include <linux/err.h>
+#include <asm/arch/pinctrl_init.h>
+
+int pinctrl_devices_active(int pinctrl_num)
+{
+ int ret;
+ int idx;
+ struct udevice *pinctrl;
+
+ for (idx = 0; idx < pinctrl_num; idx++) {
+ ret = uclass_get_device(UCLASS_PINCTRL, idx, &pinctrl);
+ if (ret) {
+ debug("%s: failed to active pinctrl device [%d]",
+ __func__, idx);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-meson/c2/pll.c b/arch/arm/mach-meson/c2/pll.c
new file mode 100644
index 0000000..2c01070
--- /dev/null
+++ b/arch/arm/mach-meson/c2/pll.c
@@ -0,0 +1,890 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <amlogic/cpu_id.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/pll.h>
+
+#define STR_PLL_TEST_ALL "all"
+#define STR_PLL_TEST_SYS "sys"
+#define STR_PLL_TEST_FIX "fix"
+#define STR_PLL_TEST_DDR "ddr"
+#define STR_PLL_TEST_HIFI "hifi"
+#define STR_PLL_TEST_GP "gp0"
+#define STR_PLL_TEST_DDS "dds"
+#define STR_PLL_TEST_USBPHY "usbphy"
+#define STR_PLL_TEST_ETHPHY "ethphy"
+
+#define PLL_LOCK_CHECK_MAX 10
+
+#define RET_PLL_LOCK_FAIL 0x1000
+#define RET_CLK_NOT_MATCH 0x1
+#define SYS_PLL_DIV16_CNTL (1<<24)
+#define SYS_CLK_DIV16_CNTL (1)
+#define SYS_PLL_TEST_DIV 4 /* div16 */
+#define HDMI_PLL_DIV_CNTL (1<<18)
+#define HDMI_PLL_DIV_GATE (1<<19)
+
+#define PLL_DIV16_OFFSET 4 /* div2/2/4 */
+#define gp_PLL_TEST_DIV 0 /* div1 */
+#define PLL_DIV8_OFFSET 3
+
+#define Wr(addr, data) writel(data, addr)
+#define Rd(addr) readl(addr)
+
+static int sys_pll_init(sys_pll_set_t * sys_pll_set);
+static int sys_pll_test(sys_pll_set_t * sys_pll_set);
+static int sys_pll_test_all(sys_pll_cfg_t * sys_pll_cfg);
+static int fix_pll_test(void);
+static int ddr_pll_test(void);
+static int gp_pll_test(gp_pll_set_t * gp_pll);
+static int gp_pll_test_all(gp0_pll_cfg_t * gp0_pll_cfg);
+extern unsigned long clk_util_clk_msr(unsigned long clk_mux);
+
+static void update_bits(size_t reg, size_t mask, unsigned int val)
+{
+ unsigned int tmp, orig;
+ orig = readl(reg);
+ tmp = orig & ~mask;
+ tmp |= val & mask;
+ writel(tmp, reg);
+}
+
+uint32_t sys_pll_clk[PLL_TEST_SYS_TOTAL] = {3216, 1584};
+sys_pll_cfg_t sys_pll_cfg = {
+ .sys_pll[0] = {
+ .cpu_clk = 3216,
+ .pll_cntl0 = 0x00300486,
+ .pll_cntl1 = 0x00021092,
+ .pll_cntl2 = 0x09023302,
+ .pll_cntl3 = 0x02008000,
+ },
+ .sys_pll[1] = {
+ .cpu_clk = 1584,
+ .pll_cntl0 = 0x00000442,
+ .pll_cntl1 = 0x00021092,
+ .pll_cntl2 = 0x09023302,
+ .pll_cntl3 = 0x02008000,
+ },
+};
+
+uint32_t hifi_pll_clk[] = {1560, 744};
+hifi_pll_cfg_t hifi_pll_cfg = {
+ .hifi_pll[0] = {
+ .pll_clk = 1560,
+ .pll_cntl0 = 0x00030441,
+ .pll_cntl1 = 0x802000b1,
+ .pll_cntl2 = 0x15002320,
+ .pll_cntl3 = 0xf0005555,
+ .pll_cntl4 = 0x45004000,
+ },
+
+ .hifi_pll[1] = {
+ .pll_clk = 744,
+ .pll_cntl0 = 0x0003041f,
+ .pll_cntl1 = 0x802000b1,
+ .pll_cntl2 = 0x12002320,
+ .pll_cntl3 = 0xf0005555,
+ .pll_cntl4 = 0x45004000,
+ },
+};
+
+gp0_pll_cfg_t gp0_pll_cfg = {
+ .gp0_pll[0] = {
+ .pll_clk = 1560, /* MHz */
+ .pll_cntl0 = 0x00030441,
+ .pll_cntl1 = 0x802000b1,
+ .pll_cntl2 = 0x11002320,
+ .pll_cntl3 = 0xd0010000,
+ .pll_cntl4 = 0x45004000,
+ .pll_cntl5 = 0x51a051a,
+ .pll_cntl6 = 0x01888585
+ },
+ .gp0_pll[1] = {
+ .pll_clk = 744, /* MHz */
+ .pll_cntl0 = 0x0003041f,
+ .pll_cntl1 = 0x802000b1,
+ .pll_cntl2 = 0x11002320,
+ .pll_cntl3 = 0xd0010000,
+ .pll_cntl4 = 0x45004000,
+ .pll_cntl5 = 0x51a051a,
+ .pll_cntl6 = 0x01888585
+ },
+};
+
+#define PLL_RATE(_rate, _m, _n, _od) \
+{ \
+ .rate = (_rate), \
+ .m = (_m), \
+ .n = (_n), \
+ .od = (_od), \
+}
+
+#define DDSPLL_RATE(_RATE, _CTS, _N) \
+{ \
+ .RATE = (_RATE), \
+ .CTS= (_CTS), \
+ .N = (_N), \
+}
+
+static void pll_report(unsigned int flag, char * name)
+{
+ if (flag)
+ printf("%s pll test failed!\n", name);
+ else
+ printf("%s pll test pass!\n", name);
+ return;
+}
+
+static int clk_around(unsigned int clk, unsigned int cmp)
+{
+ if (((cmp - 2) <= clk) && (clk <= (cmp + 2)))
+ return 1;
+ else
+ return 0;
+}
+
+void clocks_set_sys_cpu_clk(uint32_t src)
+{
+ /*
+ * src
+ * 0: use 24M, 1: use SYS PLL
+ */
+ uint32_t control;
+ uint32_t dyn_pre_mux;
+ uint32_t dyn_post_mux;
+ uint32_t dyn_div;
+ //runtime_info_t info;
+
+ // Make sure not busy from last setting and we currently match the last setting
+ do {
+ control = readl(CPUCTRL_CLK_CTRL0);
+ } while( (control & (1 << 28)) );
+
+ control = control | (1 << 26);// Enable
+
+ dyn_pre_mux = 0; //use oscin
+ dyn_post_mux = 0;
+ dyn_div = 0;/* divide by 1 */
+
+ // Select Dynamic mux
+ if (src == 1) {
+ control = control | (1 << 11);
+ }
+ else {
+ control = control & ~(1 << 11);
+ if (control & (1 << 10)) {// if using Dyn mux1, set dyn mux 0
+ // Toggle bit[10] indicating a dynamic mux change
+ control = (control & ~((1 << 10) | (0x3f << 4) | (1 << 2) | (0x3 << 0)))
+ | ((0 << 10)
+ | (dyn_div << 4)
+ | (dyn_post_mux << 2)
+ | (dyn_pre_mux << 0));
+ } else {
+ // Toggle bit[10] indicating a dynamic mux change
+ control = (control & ~((1 << 10) | (0x3f << 20) | (1 << 18) | (0x3 << 16)))
+ | ((1 << 10)
+ | (dyn_div << 20)
+ | (dyn_post_mux << 18)
+ | (dyn_pre_mux << 16));
+ }
+ }
+
+ writel(control, CPUCTRL_CLK_CTRL0);
+
+ return;
+}
+
+static int sys_pll_init(sys_pll_set_t * sys_pll_set)
+{
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int lock_timeout = 0;
+
+ do {
+ _udelay(5);
+ writel(sys_pll_set->pll_cntl0 | (1 << 29),
+ ANACTRL_SYSPLL_CTRL0);
+ writel(sys_pll_set->pll_cntl1, ANACTRL_SYSPLL_CTRL1);
+ writel(sys_pll_set->pll_cntl2, ANACTRL_SYSPLL_CTRL2);
+ writel(sys_pll_set->pll_cntl3, ANACTRL_SYSPLL_CTRL3);
+ writel(sys_pll_set->pll_cntl0 | (1 << 28) | (1 << 29),
+ ANACTRL_SYSPLL_CTRL0);
+ _udelay(5);
+ writel(sys_pll_set->pll_cntl0 | (1 << 28),
+ ANACTRL_SYSPLL_CTRL0);
+ _udelay(10);
+ writel(sys_pll_set->pll_cntl0 | (1 << 28) | (1 << 27),
+ ANACTRL_SYSPLL_CTRL0);
+ lock_timeout = 80;
+ do {
+ _udelay(5);
+ } while ((0 == ((Rd(ANACTRL_SYSPLL_STS) >> 31) & 0x1)) &&
+ (--lock_timeout));
+ } while((0 == ((Rd(ANACTRL_SYSPLL_STS) >> 31) & 0x1)) &&
+ (--lock_check));
+ if (lock_check != 0)
+ return 0;
+ else
+ return RET_PLL_LOCK_FAIL;
+}
+
+
+static int sys_pll_test_all(sys_pll_cfg_t * sys_pll_cfg)
+{
+ unsigned int i = 0;
+ int ret = 0;
+
+ for (i = 0; i < (sizeof(sys_pll_clk) / sizeof(uint32_t)); i++) {
+ sys_pll_cfg->sys_pll[0].cpu_clk = sys_pll_clk[i];
+ ret += sys_pll_test(&(sys_pll_cfg->sys_pll[i]));
+ }
+ return ret;
+}
+
+
+static int sys_pll_test(sys_pll_set_t * sys_pll_set)
+{
+ unsigned int clk_msr_val = 0;
+ unsigned int sys_clk = 0, od = 0;
+ int ret = 0;
+
+ /* switch sys clk to oscillator */
+ clocks_set_sys_cpu_clk(0);
+
+ /* store current sys pll cntl */
+ sys_pll_set_t sys_pll;
+ sys_pll.pll_cntl0 = readl(ANACTRL_SYSPLL_CTRL0) & (~(0x7 << 27));
+ sys_pll.pll_cntl1 = readl(ANACTRL_SYSPLL_CTRL1);
+ sys_pll.pll_cntl2 = readl(ANACTRL_SYSPLL_CTRL2);
+ sys_pll.pll_cntl3 = readl(ANACTRL_SYSPLL_CTRL3);
+
+ if (sys_pll_set->cpu_clk == 0) {
+ sys_clk = (24 * (sys_pll_set->pll_cntl0 & 0xFF)) /
+ ((sys_pll_set->pll_cntl0 >> 10) & 0x1F);
+ }
+
+ if (0 == sys_pll_set->pll_cntl0) {
+ printf("sys pll cntl equal NULL, skip\n");
+ return -1;
+ }
+
+ od = (sys_pll_set->pll_cntl0 >> 20) & 0x3;
+ /* test sys pll */
+ if (sys_pll_set->cpu_clk)
+ sys_clk = sys_pll_set->cpu_clk;
+
+ ret = sys_pll_init(sys_pll_set);
+ if (ret) {
+ printf("SYS pll lock Failed! - %4d MHz\n", sys_clk);
+ } else {
+ printf("SYS pll lock OK! - %4d MHz >> %d/Div16 - %4d MHz.",
+ sys_clk, od, (sys_clk >> od) >> PLL_DIV16_OFFSET);
+ clocks_set_sys_cpu_clk(1);
+ /*open div16*/
+ writel(readl(CPUCTRL_CLK_CTRL1) | (1 << 24) | (1 << 1),
+ CPUCTRL_CLK_CTRL1);
+ clk_msr_val = clk_util_clk_msr(45);
+ printf("CLKMSR(45) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, (sys_clk >> od) >>
+ SYS_PLL_TEST_DIV)) {
+ /* sys clk/pll div16 */
+ printf(": Match\n");
+ } else {
+ ret = RET_CLK_NOT_MATCH;
+ printf(": MisMatch\n");
+ }
+ }
+
+ /* restore sys pll */
+ clocks_set_sys_cpu_clk(0);
+ //printf("cpu = 0x%x\n", readl(CPUCTRL_CLK_CTRL0));
+ ret = sys_pll_init(&sys_pll);
+ if (ret)
+ printf("restore sys pll lock Failed!\n");
+ clocks_set_sys_cpu_clk(1);
+
+ return ret;
+}
+
+
+static int fix_pll_test(void)
+{
+ return 0;
+}
+
+static int ddr_pll_test(void)
+{
+ return 0;
+}
+
+static int hifi_pll_test(hifi_pll_set_t * hifi_pll)
+{
+ int ret = 0;
+ unsigned int pll_clk = 0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+
+ if (hifi_pll->pll_clk == 0)
+ pll_clk = (24 / ((hifi_pll->pll_cntl0 >> 10) & 0x1F) *
+ (hifi_pll->pll_cntl0 & 0x1FF));
+ else
+ pll_clk = hifi_pll->pll_clk;
+
+ do {
+ writel(hifi_pll->pll_cntl0 | (1 << 29),
+ ANACTRL_HIFIPLL_CTRL0);
+ writel(hifi_pll->pll_cntl1, ANACTRL_HIFIPLL_CTRL1);
+ writel(hifi_pll->pll_cntl2, ANACTRL_HIFIPLL_CTRL2);
+ writel(hifi_pll->pll_cntl3, ANACTRL_HIFIPLL_CTRL3);
+ writel(hifi_pll->pll_cntl4, ANACTRL_HIFIPLL_CTRL4);
+ _udelay(5);
+ writel(hifi_pll->pll_cntl0 | (1 << 28) | (1 << 29),
+ ANACTRL_HIFIPLL_CTRL0);
+ _udelay(5);
+ writel(hifi_pll->pll_cntl0 | (1 << 28),
+ ANACTRL_HIFIPLL_CTRL0);
+ _udelay(10);
+ writel(hifi_pll->pll_cntl4 | (1 << 0), ANACTRL_HIFIPLL_CTRL4);
+ _udelay(100);
+ } while((0 == ((Rd(ANACTRL_HIFIPLL_STS) >> 31) & 0x1)) &&
+ (--lock_check));
+
+ if (0 == lock_check) {
+ printf("HIFI pll lock Failed! - %4d MHz\n", pll_clk);
+ ret += RET_PLL_LOCK_FAIL;
+ } else {
+ printf("HIFI pll lock OK! - %4d MHz. Div8 - %4d MHz. ",
+ pll_clk, pll_clk >> PLL_DIV8_OFFSET);
+
+ Wr(CLKTREE_SPICC_CLK_CTRL, ((3 << 9) | (1 << 8) | (0 << 0)));
+ clk_msr_val = clk_util_clk_msr(16);
+ printf("CLKMSR(16) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk >> PLL_DIV8_OFFSET)) {
+ printf(": Match\n");
+ } else {
+ printf(": MisMatch\n");
+ ret += RET_CLK_NOT_MATCH;
+ }
+ }
+
+ return ret;
+}
+
+static int hifi_pll_test_all(hifi_pll_cfg_t * hifi_pll_cfg)
+{
+ unsigned int i = 0;
+ int ret = 0;
+
+ for (i = 0; i < (sizeof(hifi_pll_clk) / sizeof(uint32_t)); i++)
+ ret += hifi_pll_test(&(hifi_pll_cfg->hifi_pll[i]));
+ return ret;
+}
+
+static int gp_pll_test(gp_pll_set_t * gp_pll)
+{
+ int ret = 0;
+ unsigned int pll_clk = 0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+
+ if (gp_pll->pll_clk == 0)
+ pll_clk = (24 / ((gp_pll->pll_cntl0 >> 10) & 0x1F) *
+ (gp_pll->pll_cntl0 & 0xFF));
+ else
+ pll_clk = gp_pll->pll_clk;
+
+ lock_check = PLL_LOCK_CHECK_MAX;
+ do {
+ writel(gp_pll->pll_cntl0 | (1 << 29), ANACTRL_GPPLL_CTRL0);
+ writel(gp_pll->pll_cntl1, ANACTRL_GPPLL_CTRL1);
+ writel(gp_pll->pll_cntl2, ANACTRL_GPPLL_CTRL2);
+ writel(gp_pll->pll_cntl3, ANACTRL_GPPLL_CTRL3);
+ writel(gp_pll->pll_cntl4, ANACTRL_GPPLL_CTRL4);
+ writel(gp_pll->pll_cntl5, ANACTRL_GPPLL_CTRL5);
+ writel(gp_pll->pll_cntl6, ANACTRL_GPPLL_CTRL6);
+ _udelay(5);
+ writel(gp_pll->pll_cntl0 | (1 << 28) | (1 << 29),
+ ANACTRL_GPPLL_CTRL0);
+ _udelay(5);
+ writel(gp_pll->pll_cntl0 | (1 << 28),
+ ANACTRL_GPPLL_CTRL0);
+ _udelay(10);
+ writel(gp_pll->pll_cntl4 | (1 << 0), ANACTRL_GPPLL_CTRL4);
+ _udelay(100);
+ } while ((!((readl(ANACTRL_GPPLL_STS) >> 31) & 0x1)) && --lock_check);
+
+ if (0 == lock_check) {
+ printf("GP pll lock Failed! - %4d MHz\n", pll_clk);
+ ret = RET_PLL_LOCK_FAIL;
+ } else {
+ printf("GP pll lock OK! - %4d MHz. Div8 - %4d MHz. ",
+ pll_clk, pll_clk >> PLL_DIV8_OFFSET);
+ Wr(CLKTREE_SPICC_CLK_CTRL, ((4 << 9) | (1 << 8) | (0 << 0)));
+ /* get gp_pll_clk */
+ clk_msr_val = clk_util_clk_msr(16);
+ printf("CLKMSR(16) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk >> PLL_DIV8_OFFSET)) {
+ printf(": Match\n");
+ } else {
+ printf(": MisMatch\n");
+ ret += RET_CLK_NOT_MATCH;
+ }
+ }
+ return ret;
+}
+
+static int gp_pll_test_all(gp0_pll_cfg_t * gp0_pll_cfg)
+{
+ unsigned int i = 0;
+ int ret = 0;
+ for (i = 0; i < (sizeof(gp0_pll_cfg_t) / sizeof(gp_pll_set_t)); i++)
+ ret += gp_pll_test(&(gp0_pll_cfg->gp0_pll[i]));
+ return ret;
+}
+
+static int dds_pll_test(dds_pll_set_t * dds_pll)
+{
+ int ret=0;
+ #if 0 //2020.02.20
+ unsigned int i=0, pll_clk=0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+
+ for (i=0; i<(sizeof(ddspll_tbl)/sizeof(ddspll_tbl[0])); i++) {
+ if (((dds_pll->pll_cntl3)/(dds_pll->pll_cntl4)) == ((ddspll_tbl[i].CTS)/(ddspll_tbl[i].N))) {
+ pll_clk = ddspll_tbl[i].RATE;
+ }
+ }
+ do {
+ writel(dds_pll->misctop_cntl0, ANACTRL_MISCTOP_CTRL0);
+ writel(dds_pll->pll_cntl0, ANACTRL_AUDDDS_CTRL0);
+ writel(dds_pll->pll_cntl1, ANACTRL_AUDDDS_CTRL1);
+ writel(dds_pll->pll_cntl2, ANACTRL_AUDDDS_CTRL2);
+ writel(dds_pll->pll_cntl3, ANACTRL_AUDDDS_CTRL3);
+ writel(dds_pll->pll_cntl4, ANACTRL_AUDDDS_CTRL4);
+ writel((dds_pll->pll_cntl0 | (1<<29) | (1<<10) | (1<<11)) & ~(1<<28), ANACTRL_AUDDDS_CTRL0);
+
+ writel(dds_pll->pll_cntl1 | (1<<31), ANACTRL_AUDDDS_CTRL1);
+
+ //printf("gp lock_check: %4d\n", lock_check);
+ } while ((!((readl(ANACTRL_AUDDDS_STS)>>31)&0x1)) && --lock_check);
+ if (0 == lock_check) {
+ printf("dds pll lock Failed! - %4d MHz\n", pll_clk);
+ ret = RET_PLL_LOCK_FAIL;
+ }
+ else {
+ printf("dds pll lock OK! - %4d MHz.", pll_clk);
+ clk_msr_val = clk_util_clk_msr(44);
+ printf("CLKMSR(44) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk)) {
+ printf(": Match\n");
+ }
+ else {
+ printf(": MisMatch\n");
+ ret += RET_CLK_NOT_MATCH;
+ }
+ }
+ #endif
+ return ret;
+}
+
+static int dds_pll_test_all(void)
+{
+ #if 0 //2020.02.20
+ unsigned int i=0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+ int ret=0;
+ //unsigned int ctrl0 = 0;
+
+ for (i=0; i<(sizeof(ddspll_tbl)/sizeof(ddspll_tbl[0])); i++) {
+ //ctrl0 = 0;
+ //ctrl0 = ctrl0 | ((gpll0_tbl[i].m)<<0) | ((gpll0_tbl[i].n)<<10);
+ do {
+ writel(0x4, ANACTRL_MISCTOP_CTRL0);
+ writel(0x50041340, ANACTRL_AUDDDS_CTRL0);
+ writel(0x0, ANACTRL_AUDDDS_CTRL1);
+ writel(0x0, ANACTRL_AUDDDS_CTRL2);
+ writel(ddspll_tbl[i].CTS, ANACTRL_AUDDDS_CTRL3);
+ writel(ddspll_tbl[i].N, ANACTRL_AUDDDS_CTRL4);
+ writel(0x60041f40, ANACTRL_AUDDDS_CTRL0);
+ writel(0x80000000, ANACTRL_AUDDDS_CTRL1);
+ } while((0 == ((Rd(ANACTRL_AUDDDS_STS) >> 31) & 0x1)) && (--lock_check));
+
+ if (0 == lock_check) {
+ printf("dds pll lock Failed! - %4d MHz\n", ddspll_tbl[i].RATE);
+ ret += RET_PLL_LOCK_FAIL;
+ }
+ else {
+ printf("dds pll lock OK! - %4d MHz.", ddspll_tbl[i].RATE);
+ //Wr(CLKTREE_SPICC_CLK_CTRL, ((4<<9) | (1<<8) | (7<<0)));
+ //printf("CLKTREE_SPICC_CLK_CTRL: 0x%8x\n", readl(CLKTREE_SPICC_CLK_CTRL));
+ clk_msr_val = clk_util_clk_msr(44);
+ printf("CLKMSR(44) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, ddspll_tbl[i].RATE)) {
+ printf(": Match\n");
+ }
+ else {
+ printf(": MisMatch\n");
+ ret += RET_CLK_NOT_MATCH;
+ }
+ }
+ }
+ return ret;
+ #endif
+
+ return 0;
+}
+
+static int usbphy_pll_test(usbphy_pll_set_t * usbphy_pll)
+{
+ int ret = 0;
+ unsigned int pll_clk = 0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned long usbphy_base_cfg = 0xFE004000;
+
+ if ((usbphy_pll->pll_cntl0 & 0x1FF) == 0x14) {
+ pll_clk = 480;
+ } else {
+ printf("input frequency point is not support\n");
+ return -1;
+ }
+ writel(usbphy_pll->pll_cntl0, (usbphy_base_cfg + 0x40));
+ writel(usbphy_pll->pll_cntl1, (usbphy_base_cfg + 0x44));
+ writel(usbphy_pll->pll_cntl2, (usbphy_base_cfg + 0x48));
+
+ lock_check = PLL_LOCK_CHECK_MAX;
+ do {
+ update_bits((usbphy_base_cfg + 0x40), 1<<29, 1 << 29);
+ _udelay(10);
+ update_bits((usbphy_base_cfg + 0x40), 1<<29, 0);
+ _udelay(100);
+ //printf("ethphy lock_check: %4d\n", lock_check);
+ } while ((!((readl(usbphy_base_cfg + 0x40)>>31)&0x1)) && --lock_check);
+ if (0 == lock_check) {
+ printf("usbphy pll lock Failed! - %4d MHz\n", pll_clk);
+ ret = RET_PLL_LOCK_FAIL;
+ } else {
+ printf("usbphy pll lock OK! - %4d MHz.\n", pll_clk);
+ }
+
+ return ret;
+}
+
+static int usbphy_pll_test_all(void)
+{
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ int ret=0;
+ unsigned long usbphy_base_cfg = 0xFE004000;
+
+ writel(0x09400414, (usbphy_base_cfg + 0x40));
+ writel(0x927e0000, (usbphy_base_cfg + 0x44));
+ writel(0xac5f69e5, (usbphy_base_cfg + 0x48));
+ writel(0x29400414, (usbphy_base_cfg + 0x40));
+ writel(0x09400414, (usbphy_base_cfg + 0x40));
+
+ do {
+ update_bits((usbphy_base_cfg + 0x40), 1<<29, 1 << 29);
+ _udelay(10);
+ update_bits((usbphy_base_cfg + 0x40), 1<<29, 0);
+ _udelay(100);
+ //printf("usbphy lock_check: %4d\n", lock_check);
+ } while ((!((readl(usbphy_base_cfg + 0x40)>>31)&0x1)) && --lock_check);
+
+ if (0 == lock_check) {
+ printf("usbphy pll lock Failed! - 480MHz\n");
+ ret += RET_PLL_LOCK_FAIL;
+ } else {
+ printf("usbphy pll lock OK! - 480MHz.\n");
+ }
+
+ return ret;
+}
+
+static int ethphy_pll_test(ethphy_pll_set_t * ethphy_pll)
+{
+ int ret = 0;
+ unsigned int pll_clk=0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+
+ if ((ethphy_pll->pll_cntl0 & 0x1FF) == 0xA) {
+ pll_clk = 500;
+ } else {
+ printf("input frequency point is not support\n");
+ return -1;
+ }
+
+ do {
+ writel(ethphy_pll->pll_cntl0 | 0x30000000, ETH_PLL_CTL0);
+ writel(ethphy_pll->pll_cntl1, ETH_PLL_CTL1);
+ writel(ethphy_pll->pll_cntl2, ETH_PLL_CTL2);
+ _udelay(150);
+ writel(ethphy_pll->pll_cntl0 | 0x10000000, ETH_PLL_CTL0);
+ _udelay(150);
+ } while ((!((readl(ETH_PLL_CTL0)>>30)&0x1))&& --lock_check);
+
+ if (0 == lock_check) {
+ printf("ETHPHY pll lock Failed! - %4d MHz\n", pll_clk);
+ ret = RET_PLL_LOCK_FAIL;
+ } else {
+ printf("ETHPHY pll lock OK! - %4d MHz. ", pll_clk);
+ /* get ethphy_pll_clk */
+ clk_msr_val = clk_util_clk_msr(64)<<2;
+ printf("CLKMSR(64) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk)) {
+ printf(": Match\n");
+ } else {
+ printf(": MisMatch\n");
+ ret = RET_CLK_NOT_MATCH;
+ }
+ }
+ return ret;
+}
+
+static int ethphy_pll_test_all(void)
+{
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+ int ret = 0;
+
+ do {
+ writel(0x9c0040a | 0x30000000, ETH_PLL_CTL0);
+ writel(0x927e0000, ETH_PLL_CTL1);
+ writel(0xac5f49e5, ETH_PLL_CTL2);
+ writel(0x00000000, ETH_PLL_CTL3);
+ _udelay(150);
+ writel(0x9c0040a | 0x10000000, ETH_PLL_CTL0);
+ _udelay(150);
+ } while ((!((readl(ETH_PLL_CTL0)>>30)&0x1))&& --lock_check);
+
+ if (0 == lock_check) {
+ printf("ethphy pll lock Failed! - 500MHz\n");
+ ret += RET_PLL_LOCK_FAIL;
+ } else {
+ printf("ethphy pll lock OK! - 500MHz. ");
+ /* get ethphy_pll_clk */
+ clk_msr_val = clk_util_clk_msr(64)<<2;
+ printf("CLKMSR(64) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, 500)) {
+ printf(": Match\n");
+ } else {
+ printf(": MisMatch\n");
+ ret += RET_CLK_NOT_MATCH;
+ }
+ }
+
+ return ret;
+}
+
+static int pll_test_all(unsigned char * pll_list)
+{
+ int ret = 0;
+ unsigned char i = 0;
+ for (i = 0; i < PLL_ENUM; i++) {
+ switch (pll_list[i]) {
+ case PLL_SYS:
+ ret = sys_pll_test_all(&sys_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_SYS);
+ break;
+ case PLL_FIX:
+ ret = fix_pll_test();
+ pll_report(ret, STR_PLL_TEST_FIX);
+ break;
+ case PLL_DDR:
+ ret = ddr_pll_test();
+ pll_report(ret, STR_PLL_TEST_DDR);
+ break;
+ case PLL_HIFI:
+ ret = hifi_pll_test_all(&hifi_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_HIFI);
+ break;
+ case PLL_GP:
+ ret = gp_pll_test_all(&gp0_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_GP);
+ break;
+ case PLL_DDS:
+ ret = dds_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_DDS);
+ break;
+ case PLL_USBPHY:
+ ret = usbphy_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_USBPHY);
+ break;
+ case PLL_ETHPHY:
+ ret = ethphy_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_ETHPHY);
+ break;
+ default:
+ break;
+ }
+ }
+ return ret;
+}
+
+int pll_test(int argc, char * const argv[])
+{
+ int ret = 0;
+ sys_pll_set_t sys_pll_set = {0};
+ hifi_pll_set_t hifi_pll_set = {0};
+ gp_pll_set_t gp_pll_set = {0};
+ dds_pll_set_t dds_pll_set = {0};
+ usbphy_pll_set_t usbphy_pll_set = {0};
+ ethphy_pll_set_t ethphy_pll_set = {0};
+
+ unsigned char plls[PLL_ENUM] = {
+ PLL_SYS,
+ 0xff,// PLL_FIX, //0xff will skip this pll
+ 0xff,// PLL_DDR,
+ PLL_HIFI,
+ PLL_GP,
+ 0xff,//PLL_DDS
+ 0xff,//PLL_USBPHY
+ 0xff,//PLL_ETHPHY
+ };
+
+ if (0 == strcmp(STR_PLL_TEST_ALL, argv[1])) {
+ printf("Test all plls\n");
+ pll_test_all(plls);
+ } else if(0 == strcmp(STR_PLL_TEST_SYS, argv[1])) {
+ if (argc == 2) {
+ ret = sys_pll_test_all(&sys_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_SYS);
+ } else if (argc != 6) {
+ printf("%s pll test: args error\n", STR_PLL_TEST_SYS);
+ return -1;
+ } else {
+ sys_pll_set.pll_cntl0 = simple_strtoul(argv[2],
+ NULL, 16);
+ sys_pll_set.pll_cntl1 = simple_strtoul(argv[3],
+ NULL, 16);
+ sys_pll_set.pll_cntl2 = simple_strtoul(argv[4],
+ NULL, 16);
+ sys_pll_set.pll_cntl3 = simple_strtoul(argv[5],
+ NULL, 16);
+ ret = sys_pll_test(&sys_pll_set);
+ pll_report(ret, STR_PLL_TEST_SYS);
+ }
+ } else if (0 == strcmp(STR_PLL_TEST_HIFI, argv[1])) {
+ if (argc == 2) {
+ ret = hifi_pll_test_all(&hifi_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_HIFI);
+ } else if (argc != 7){
+ printf("%s pll test: args error\n", STR_PLL_TEST_HIFI);
+ return -1;
+ } else {
+ hifi_pll_set.pll_cntl0 = simple_strtoul(argv[2],
+ NULL, 16);
+ hifi_pll_set.pll_cntl1 = simple_strtoul(argv[3],
+ NULL, 16);
+ hifi_pll_set.pll_cntl2 = simple_strtoul(argv[4],
+ NULL, 16);
+ hifi_pll_set.pll_cntl3 = simple_strtoul(argv[5],
+ NULL, 16);
+ hifi_pll_set.pll_cntl4 = simple_strtoul(argv[6],
+ NULL, 16);
+ ret = hifi_pll_test(&hifi_pll_set);
+ pll_report(ret, STR_PLL_TEST_HIFI);
+ }
+ } else if (0 == strcmp(STR_PLL_TEST_GP, argv[1])) {
+ if (argc == 2) {
+ ret = gp_pll_test_all(&gp0_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_GP);
+ } else if (argc != 9) {
+ printf("%s pll test: args error\n", STR_PLL_TEST_GP);
+ return -1;
+ } else {
+ gp_pll_set.pll_cntl0 = simple_strtoul(argv[2],
+ NULL, 16);
+ gp_pll_set.pll_cntl1 = simple_strtoul(argv[3],
+ NULL, 16);
+ gp_pll_set.pll_cntl2 = simple_strtoul(argv[4],
+ NULL, 16);
+ gp_pll_set.pll_cntl3 = simple_strtoul(argv[5],
+ NULL, 16);
+ gp_pll_set.pll_cntl4 = simple_strtoul(argv[6],
+ NULL, 16);
+ gp_pll_set.pll_cntl5 = simple_strtoul(argv[7],
+ NULL, 16);
+ gp_pll_set.pll_cntl6 = simple_strtoul(argv[8],
+ NULL, 16);
+ ret = gp_pll_test(&gp_pll_set);
+ pll_report(ret, STR_PLL_TEST_GP);
+ }
+ } else if (0 == strcmp(STR_PLL_TEST_DDR, argv[1])) {
+ printf("%s pll not support now\n", STR_PLL_TEST_DDR);
+ return -1;
+ } else if (0 == strcmp(STR_PLL_TEST_FIX, argv[1])) {
+ printf("%s pll not support now\n", STR_PLL_TEST_FIX);
+ return -1;
+ } else if (0 == strcmp(STR_PLL_TEST_DDS, argv[1])) {
+ if (argc == 2) {
+ ret = dds_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_DDS);
+ } else if (argc != 8) {
+ printf("%s pll test: args error\n", STR_PLL_TEST_DDS);
+ return -1;
+ } else {
+ dds_pll_set.misctop_cntl0 = simple_strtoul(argv[2],
+ NULL, 16);
+ dds_pll_set.pll_cntl0 = simple_strtoul(argv[3],
+ NULL, 16);
+ dds_pll_set.pll_cntl1 = simple_strtoul(argv[4],
+ NULL, 16);
+ dds_pll_set.pll_cntl2 = simple_strtoul(argv[5],
+ NULL, 16);
+ dds_pll_set.pll_cntl3 = simple_strtoul(argv[6],
+ NULL, 16);
+ dds_pll_set.pll_cntl4 = simple_strtoul(argv[7],
+ NULL, 16);
+ ret = dds_pll_test(&dds_pll_set);
+ pll_report(ret, STR_PLL_TEST_DDS);
+ }
+ } else if (0 == strcmp(STR_PLL_TEST_USBPHY, argv[1])) {
+ if (argc == 2) {
+ ret = usbphy_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_USBPHY);
+ } else if (argc != 5) {
+ printf("%s pll test: args error\n",
+ STR_PLL_TEST_USBPHY);
+ return -1;
+ } else {
+ usbphy_pll_set.pll_cntl0 = simple_strtoul(argv[2],
+ NULL, 16);
+ usbphy_pll_set.pll_cntl1 = simple_strtoul(argv[3],
+ NULL, 16);
+ usbphy_pll_set.pll_cntl2 = simple_strtoul(argv[4],
+ NULL, 16);
+ ret = usbphy_pll_test(&usbphy_pll_set);
+ pll_report(ret, STR_PLL_TEST_USBPHY);
+ }
+ } else if (0 == strcmp(STR_PLL_TEST_ETHPHY, argv[1])) {
+ if (argc == 2) {
+ ret = ethphy_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_ETHPHY);
+ } else if (argc != 5) {
+ printf("%s pll test: args error\n",
+ STR_PLL_TEST_ETHPHY);
+ return -1;
+ } else {
+ ethphy_pll_set.pll_cntl0 = simple_strtoul(argv[2],
+ NULL, 16);
+ ethphy_pll_set.pll_cntl1 = simple_strtoul(argv[3],
+ NULL, 16);
+ ethphy_pll_set.pll_cntl2 = simple_strtoul(argv[4],
+ NULL, 16);
+ ret = ethphy_pll_test(ðphy_pll_set);
+ pll_report(ret, STR_PLL_TEST_ETHPHY);
+ }
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-meson/c2/power_cal.c b/arch/arm/mach-meson/c2/power_cal.c
new file mode 100644
index 0000000..e4f9c53
--- /dev/null
+++ b/arch/arm/mach-meson/c2/power_cal.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/io.h>
+#include <amlogic/saradc.h>
+#include <asm/arch/mailbox.h>
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2))))
+#define vcck_adc_channel 0x4
+#define ee_adc_channel 0x5
+#define default_ref_val 1800
+
+extern const int pwm_cal_voltage_table[][2];
+extern const int pwm_cal_voltage_table_ee[][2];
+extern int pwm_cal_voltage_table_size;
+extern int pwm_cal_voltage_table_ee_size;
+
+
+enum pwm_id {
+ pwm_vcck = 0,
+ pwm_ee,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+int32_t aml_delt_get(int adc_val, unsigned int voltage)
+{
+ unsigned int adc_volt;
+ int32_t delt;
+ int32_t div = 10; /*10mv is min step*/
+
+ if (adc_val != -1) {
+ adc_volt = default_ref_val*adc_val/1024;
+ printf("aml pwm cal adc_val = %x, adc_voltage = %d, def_voltage = %d\n",
+ adc_val, adc_volt, voltage);
+ } else {
+ adc_volt = voltage;
+ printf("warning:aml pwm cal adc get voltage error\n");
+ return 0;
+ }
+ delt = voltage - adc_volt;
+ delt = delt / div;
+ return delt;
+}
+
+void aml_set_voltage(unsigned int id, unsigned int voltage, int delt)
+{
+ int to;
+
+ switch (id) {
+ case pwm_vcck:
+ for (to = 0; to < pwm_cal_voltage_table_size; to++) {
+ if (pwm_cal_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ to +=delt;
+ if (to >= pwm_cal_voltage_table_size) {
+ to = pwm_cal_voltage_table_size - 1;
+ }
+ /*vcck volt set by dvfs and avs*/
+ //writel(pwm_voltage_table[to][0], PWM_PWM_A_ADRESS);
+ _udelay_(200);
+ break;
+
+ case pwm_ee:
+ for (to = 0; to < pwm_cal_voltage_table_ee_size; to++) {
+ if (pwm_cal_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ to +=delt;
+ if (to >= pwm_cal_voltage_table_ee_size) {
+ to = pwm_cal_voltage_table_ee_size - 1;
+ }
+ printf("aml pwm cal before ee_address: %x, ee_voltage: %x\n",
+ AO_PWM_PWM_B, readl(AO_PWM_PWM_B));
+ writel(pwm_cal_voltage_table_ee[to][0],AO_PWM_PWM_B);
+ _udelay_(1000);
+ printf("aml pwm cal after ee_address: %x, ee_voltage: %x\n",
+ AO_PWM_PWM_B, readl(AO_PWM_PWM_B));
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+int aml_cal_pwm(unsigned int ee_voltage, unsigned int vcck_voltage)
+{
+ int32_t ee_delt, vcck_delt;
+ unsigned int ee_val, vcck_val;
+ int ret;
+
+ /*txlx vcck ch4,vddee ch5*/
+ ret = adc_channel_single_shot_mode("adc", ADC_MODE_HIGH_PRECISION,
+ vcck_adc_channel, &vcck_val);
+ if (ret)
+ return ret;
+
+ ret = adc_channel_single_shot_mode("adc", ADC_MODE_HIGH_PRECISION,
+ ee_adc_channel, &ee_val);
+ if (ret)
+ return ret;
+
+ vcck_delt = aml_delt_get(vcck_val, vcck_voltage);
+ ee_delt = aml_delt_get(ee_val, ee_voltage);
+ send_pwm_delt(vcck_delt, ee_delt);
+ aml_set_voltage(pwm_ee, AML_VDDEE_INIT_VOLTAGE, ee_delt);
+ //aml_set_voltage(pwm_vcck, CONFIG_VCCK_INIT_VOLTAGE, vcck_delt);
+ printf("aml board pwm vcck: %x, ee: %x\n", vcck_delt, ee_delt);
+
+ return 0;
+}
+
+void aml_pwm_cal_init(int mode)
+{
+ printf("aml pwm cal init\n");
+ aml_cal_pwm(AML_VDDEE_INIT_VOLTAGE, AML_VCCK_INIT_VOLTAGE);
+}
diff --git a/arch/arm/mach-meson/c2/power_gate.h b/arch/arm/mach-meson/c2/power_gate.h
new file mode 100644
index 0000000..9ca1a9d
--- /dev/null
+++ b/arch/arm/mach-meson/c2/power_gate.h
@@ -0,0 +1,1161 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __POWER_MGR_HEADER_
+#define __POWER_MGR_HEADER_
+
+#include <asm/arch/io.h>
+#include <common.h>
+//#include <asm/arch-gxb/io.h>
+/* #include <asm/arch-gxb/register.h> */
+#include <asm/arch/secure_apb.h>
+/* clock gate control */
+
+#define DEBUG_MASK 0
+
+#define SET_CLK_GATE_MASK(reg, mask) __raw_writel((__raw_readl(reg)|mask), reg)
+#define CLEAR_CLK_GATE_MASK(reg, mask) \
+ __raw_writel((__raw_readl(reg)&(~mask)), reg)
+#define CLK_GATE_ON(_MOD) do { \
+ if (DEBUG_MASK) \
+ printf("on reg %24s before read :0x%x : 0x%x\n",\
+ GCLK_NAME_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ SET_CLK_GATE_MASK(GCLK_REG_##_MOD, \
+ (unsigned int)GCLK_MASK_##_MOD); \
+ if (DEBUG_MASK) \
+ printf("on reg %24s after read :0x%x : 0x%x\n",\
+ GCLK_NAME_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ } while (0)
+
+#define CLK_GATE_OFF(_MOD) do { \
+ if (DEBUG_MASK) \
+ printf("off reg[ %24s ][0x%08x]before read:0x%08x:0x%08x\n",\
+ GCLK_NAME_##_MOD, (int)GCLK_MASK_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ CLEAR_CLK_GATE_MASK(GCLK_REG_##_MOD, (unsigned int)GCLK_MASK_##_MOD);\
+ if (DEBUG_MASK)\
+ printf("off reg[ %24s ][0x%08x] read after:0x%08x:0x%08x\n",\
+ GCLK_NAME_##_MOD, \
+ (int)GCLK_MASK_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ } while (0)
+
+#define IS_CLK_GATE_ON(_MOD) (__raw_readl(GCLK_REG_##_MOD) & (GCLK_MASK_##_MOD))
+#define GATE_INIT(_MOD) GCLK_ref[GCLK_IDX_##_MOD] = IS_CLK_GATE_ON(_MOD) ? 1 : 0
+
+#define GCLK_IDX_DDR 0
+#define GCLK_NAME_DDR "DDR"
+#define GCLK_DEV_DDR "CLKGATE_DDR"
+#define GCLK_REG_DDR (HHI_GCLK_MPEG0)
+#define GCLK_MASK_DDR (1<<0)
+
+#define GCLK_IDX_DOS 1
+#define GCLK_NAME_DOS "DOS"
+#define GCLK_DEV_DOS "CLKGATE_DOS"
+#define GCLK_REG_DOS (HHI_GCLK_MPEG0)
+#define GCLK_MASK_DOS (1<<1)
+
+#define GCLK_IDX_RESERVED0_0 2
+#define GCLK_NAME_RESERVED0_0 "RESERVED0_0"
+#define GCLK_DEV_RESERVED0_0 "CLKGATE_RESERVED0_0"
+#define GCLK_REG_RESERVED0_0 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_0 (1<<2)
+
+#define GCLK_IDX_RESERVED0_1 3
+#define GCLK_NAME_RESERVED0_1 "RESERVED0_1"
+#define GCLK_DEV_RESERVED0_1 "CLKGATE_RESERVED0_1"
+#define GCLK_REG_RESERVED0_1 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_1 (1<<3)
+
+/* #define GCLK_IDX_AHB_BRIDGE 4 */
+/* #define GCLK_NAME_AHB_BRIDGE "AHB_BRIDGE" */
+/* #define GCLK_DEV_AHB_BRIDGE "CLKGATE_AHB_BRIDGE" */
+/* #define GCLK_REG_AHB_BRIDGE (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_AHB_BRIDGE (1<<4) */
+
+#define GCLK_IDX_ISA 5
+#define GCLK_NAME_ISA "ISA"
+#define GCLK_DEV_ISA "CLKGATE_ISA"
+#define GCLK_REG_ISA (HHI_GCLK_MPEG0)
+#define GCLK_MASK_ISA (1<<5)
+
+/* NEW ADD */
+#define GCLK_IDX_PL310_CBUS 6
+#define GCLK_NAME_PL310_CBUS "PL310_CBUS"
+#define GCLK_DEV_PL310_CBUS "CLKGATE_PL310_CBUS"
+#define GCLK_REG_PL310_CBUS (HHI_GCLK_MPEG0)
+#define GCLK_MASK_PL310_CBUS (1<<6)
+
+#define GCLK_IDX_PERIPHS_TOP 7
+#define GCLK_NAME_PERIPHS_TOP "PERIPHS_TOP"
+#define GCLK_DEV_PERIPHS_TOP "CLKGATE_PERIPHS_TOP"
+#define GCLK_REG_PERIPHS_TOP (HHI_GCLK_MPEG0)
+#define GCLK_MASK_PERIPHS_TOP (1<<7)
+
+#define GCLK_IDX_SPICC 8
+#define GCLK_NAME_SPICC "SPICC"
+#define GCLK_DEV_SPICC "CLKGATE_SPICC"
+#define GCLK_REG_SPICC (HHI_GCLK_MPEG0)
+#define GCLK_MASK_SPICC (1<<8)
+
+#define GCLK_IDX_I2C 9
+#define GCLK_NAME_I2C "I2C"
+#define GCLK_DEV_I2C "CLKGATE_I2C"
+#define GCLK_REG_I2C (HHI_GCLK_MPEG0)
+#define GCLK_MASK_I2C (1<<9)
+
+#define GCLK_IDX_SAR_ADC 10
+#define GCLK_NAME_SAR_ADC "SAR_ADC"
+#define GCLK_DEV_SAR_ADC "CLKGATE_SAR_ADC"
+//#define GCLK_REG_SAR_ADC (HHI_SAR_CLK_CNTL) //no HHI_SAR_CLK_CNTL on TXL
+#define GCLK_REG_SAR_ADC (AO_SAR_CLK)
+#define GCLK_MASK_SAR_ADC (1<<8)
+
+#define GCLK_IDX_SMART_CARD_MPEG_DOMAIN 11
+#define GCLK_NAME_SMART_CARD_MPEG_DOMAIN "SMART_CARD_MPEG_DOMAIN"
+#define GCLK_DEV_SMART_CARD_MPEG_DOMAIN "CLKGATE_SMART_CARD_MPEG_DOMAIN"
+#define GCLK_REG_SMART_CARD_MPEG_DOMAIN (HHI_GCLK_MPEG0)
+#define GCLK_MASK_SMART_CARD_MPEG_DOMAIN (1<<11)
+
+#define GCLK_IDX_RANDOM_NUM_GEN 12
+#define GCLK_NAME_RANDOM_NUM_GEN "RANDOM_NUM_GEN"
+#define GCLK_DEV_RANDOM_NUM_GEN "CLKGATE_RANDOM_NUM_GEN"
+#define GCLK_REG_RANDOM_NUM_GEN (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RANDOM_NUM_GEN (1<<12)
+
+#define GCLK_IDX_UART0 13
+#define GCLK_NAME_UART0 "UART0"
+#define GCLK_DEV_UART0 "CLKGATE_UART0"
+#define GCLK_REG_UART0 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_UART0 (1<<13)
+
+/* gxb no this clock gate */
+/* #define GCLK_IDX_SDHC 14 */
+/* #define GCLK_NAME_SDHC "SDHC" */
+/* #define GCLK_DEV_SDHC "CLKGATE_SDHC" */
+/* #define GCLK_REG_SDHC (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_SDHC (1<<14) */
+
+#define GCLK_IDX_STREAM 15
+#define GCLK_NAME_STREAM "STREAM"
+#define GCLK_DEV_STREAM "CLKGATE_STREAM"
+#define GCLK_REG_STREAM (HHI_GCLK_MPEG0)
+#define GCLK_MASK_STREAM (1<<15)
+
+#define GCLK_IDX_ASYNC_FIFO 16
+#define GCLK_NAME_ASYNC_FIFO "ASYNC_FIFO"
+#define GCLK_DEV_ASYNC_FIFO "CLKGATE_ASYNC_FIFO"
+#define GCLK_REG_ASYNC_FIFO (HHI_GCLK_MPEG0)
+#define GCLK_MASK_ASYNC_FIFO (1<<16)
+
+/* gxb no this clock gate */
+/* #define GCLK_IDX_SDIO 17 */
+/* #define GCLK_NAME_SDIO "SDIO" */
+/* #define GCLK_DEV_SDIO "CLKGATE_SDIO" */
+/* #define GCLK_REG_SDIO (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_SDIO (1<<17) */
+
+/* gxb no this clock gate */
+/* #define GCLK_IDX_AUD_BUF 18 */
+/* #define GCLK_NAME_AUD_BUF "AUD_BUF" */
+/* #define GCLK_DEV_AUD_BUF "CLKGATE_AUD_BUF" */
+/* #define GCLK_REG_AUD_BUF (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_AUD_BUF (1<<18) */
+
+#define GCLK_IDX_HIU_PARSER 19
+#define GCLK_NAME_HIU_PARSER "HIU_PARSER"
+#define GCLK_DEV_HIU_PARSER "CLKGATE_HIU_PARSER"
+#define GCLK_REG_HIU_PARSER (HHI_GCLK_MPEG0)
+#define GCLK_MASK_HIU_PARSER (1<<19)
+
+#define GCLK_IDX_RESERVED0_2 20
+#define GCLK_NAME_RESERVED0_2 "RESERVED0_2"
+#define GCLK_DEV_RESERVED0_2 "CLKGATE_RESERVED0_2"
+#define GCLK_REG_RESERVED0_2 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_2 (1<<20)
+
+/* NEW ADD */
+#define GCLK_IDX_RESERVED0_3 21
+#define GCLK_NAME_RESERVED0_3 "RESERVED0_3 "
+#define GCLK_DEV_RESERVED0_3 "CLKGATE_RESERVED0_3 "
+#define GCLK_REG_RESERVED0_3 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_3 (1<<21)
+
+#define GCLK_IDX_RESERVED0_4 22
+#define GCLK_NAME_RESERVED0_4 "RESERVED0_4"
+#define GCLK_DEV_RESERVED0_4 "CLKGATE_RESERVED0_4"
+#define GCLK_REG_RESERVED0_4 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_4 (1<<22)
+
+#define GCLK_IDX_ASSIST_MISC 23
+#define GCLK_NAME_ASSIST_MISC "ASSIST_MISC"
+#define GCLK_DEV_ASSIST_MISC "CLKGATE_ASSIST_MISC"
+#define GCLK_REG_ASSIST_MISC (HHI_GCLK_MPEG0)
+#define GCLK_MASK_ASSIST_MISC (1<<23)
+
+
+#define GCLK_IDX_EMMC_A 24
+#define GCLK_NAME_EMMC_A "EMMC_A"
+#define GCLK_DEV_EMMC_A "CLKGATE_EMMC_A"
+#define GCLK_REG_EMMC_A (HHI_GCLK_MPEG0)
+#define GCLK_MASK_EMMC_A (1<<24)
+
+#define GCLK_IDX_EMMC_B 25
+#define GCLK_NAME_EMMC_B "EMMC_B"
+#define GCLK_DEV_EMMC_B "CLKGATE_EMMC_B"
+#define GCLK_REG_EMMC_B (HHI_GCLK_MPEG0)
+#define GCLK_MASK_EMMC_B (1<<25)
+
+#define GCLK_IDX_EMMC_C 26
+#define GCLK_NAME_EMMC_C "EMMC_C"
+#define GCLK_DEV_EMMC_C "CLKGATE_EMMC_C"
+#define GCLK_REG_EMMC_C (HHI_GCLK_MPEG0)
+#define GCLK_MASK_EMMC_C (1<<26)
+
+#define GCLK_IDX_RESERVED0_8 27
+#define GCLK_NAME_RESERVED0_8 "RESERVED0_8"
+#define GCLK_DEV_RESERVED0_8 "CLKGATE_RESERVED0_8"
+#define GCLK_REG_RESERVED0_8 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_8 (1<<27)
+
+#define GCLK_IDX_RESERVED0_9 28
+#define GCLK_NAME_RESERVED0_9 "RESERVED0_9"
+#define GCLK_DEV_RESERVED0_9 "CLKGATE_RESERVED0_9"
+#define GCLK_REG_RESERVED0_9 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_9 (1<<28)
+
+#define GCLK_IDX_RESERVED0_A 29
+#define GCLK_NAME_RESERVED0_A "RESERVED0_A"
+#define GCLK_DEV_RESERVED0_A "CLKGATE_RESERVED0_A"
+#define GCLK_REG_RESERVED0_A (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_A (1<<29)
+
+#define GCLK_IDX_SPI 30
+#define GCLK_NAME_SPI "SPI"
+#define GCLK_DEV_SPI "CLKGATE_SPI"
+#define GCLK_REG_SPI (HHI_GCLK_MPEG0)
+#define GCLK_MASK_SPI (1<<30)
+
+#define GCLK_IDX_RESERVED0_B 31
+#define GCLK_NAME_RESERVED0_B "RESERVED0_B"
+#define GCLK_DEV_RESERVED0_B "CLKGATE_RESERVED0_B"
+#define GCLK_REG_RESERVED0_B (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_B (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_RESERVED1_1 32
+#define GCLK_NAME_RESERVED1_1 "RESERVED1_1"
+#define GCLK_DEV_RESERVED1_1 "CLKGATE_RESERVED1_1"
+#define GCLK_REG_RESERVED1_1 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_1 (1<<0)
+
+
+#define GCLK_IDX_RESERVED1_2 33
+#define GCLK_NAME_RESERVED1_2 "RESERVED1_2"
+#define GCLK_DEV_RESERVED1_2 "CLKGATE_RESERVED1_2"
+#define GCLK_REG_RESERVED1_2 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_2 (1<<1)
+
+
+#define GCLK_IDX_AUD_IN 34
+#define GCLK_NAME_AUD_IN "AUD_IN"
+#define GCLK_DEV_AUD_IN "CLKGATE_AUD_IN"
+#define GCLK_REG_AUD_IN (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AUD_IN (1<<2)
+
+#define GCLK_IDX_ETHERNET 35
+#define GCLK_NAME_ETHERNET "ETHERNET"
+#define GCLK_DEV_ETHERNET "CLKGATE_ETHERNET"
+#define GCLK_REG_ETHERNET (HHI_GCLK_MPEG1)
+#define GCLK_MASK_ETHERNET (1<<3)
+
+/* g12a no reg */
+#if 0
+#define GCLK_IDX_ETH_CLK 145
+#define GCLK_NAME_ETH_CLK "ETH_CLK"
+#define GCLK_REG_ETH_CLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_ETH_CLK (1<<3)
+#endif
+
+#define GCLK_IDX_DEMUX 36
+#define GCLK_NAME_DEMUX "DEMUX"
+#define GCLK_DEV_DEMUX "CLKGATE_DEMUX"
+#define GCLK_REG_DEMUX (HHI_GCLK_MPEG1)
+#define GCLK_MASK_DEMUX (1<<4)
+
+#define GCLK_IDX_RESERVED1_3 37
+#define GCLK_NAME_RESERVED1_3 "RESERVED1_3"
+#define GCLK_DEV_RESERVED1_3 "CLKGATE_RESERVED1_3"
+#define GCLK_REG_RESERVED1_3 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_3 (1<<5)
+
+#define GCLK_IDX_AIU_AI_TOP_GLUE 38
+#define GCLK_NAME_AIU_AI_TOP_GLUE "AIU_AI_TOP_GLUE"
+#define GCLK_DEV_AIU_AI_TOP_GLUE "CLKGATE_AIU_AI_TOP_GLUE"
+#define GCLK_REG_AIU_AI_TOP_GLUE (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AI_TOP_GLUE (1<<6)
+
+#define GCLK_IDX_AIU_IEC958 39
+#define GCLK_NAME_AIU_IEC958 "AIU_IEC958"
+#define GCLK_DEV_AIU_IEC958 "CLKGATE_AIU_IEC958"
+#define GCLK_REG_AIU_IEC958 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_IEC958 (1<<7)
+
+#define GCLK_IDX_AIU_I2S_OUT 40
+#define GCLK_NAME_AIU_I2S_OUT "AIU_I2S_OUT"
+#define GCLK_DEV_AIU_I2S_OUT "CLKGATE_AIU_I2S_OUT"
+#define GCLK_REG_AIU_I2S_OUT (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_I2S_OUT (1<<8)
+
+#define GCLK_IDX_AIU_AMCLK_MEASURE 41
+#define GCLK_NAME_AIU_AMCLK_MEASURE "AIU_AMCLK_MEASURE"
+#define GCLK_DEV_AIU_AMCLK_MEASURE "CLKGATE_AIU_AMCLK_MEASURE"
+#define GCLK_REG_AIU_AMCLK_MEASURE (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AMCLK_MEASURE (1<<9)
+
+#define GCLK_IDX_AIU_AIFIFO2 42
+#define GCLK_NAME_AIU_AIFIFO2 "AIU_AIFIFO2"
+#define GCLK_DEV_AIU_AIFIFO2 "CLKGATE_AIU_AIFIFO2"
+#define GCLK_REG_AIU_AIFIFO2 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AIFIFO2 (1<<10)
+
+#define GCLK_IDX_AIU_AUD_MIXER 43
+#define GCLK_NAME_AIU_AUD_MIXER "AIU_AUD_MIXER"
+#define GCLK_DEV_AIU_AUD_MIXER "CLKGATE_AIU_AUD_MIXER"
+#define GCLK_REG_AIU_AUD_MIXER (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AUD_MIXER (1<<11)
+
+#define GCLK_IDX_AIU_MIXER_REG 44
+#define GCLK_NAME_AIU_MIXER_REG "AIU_MIXER_REG"
+#define GCLK_DEV_AIU_MIXER_REG "CLKGATE_AIU_MIXER_REG"
+#define GCLK_REG_AIU_MIXER_REG (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_MIXER_REG (1<<12)
+
+#define GCLK_IDX_AIU_ADC 45
+#define GCLK_NAME_AIU_ADC "AIU_ADC"
+#define GCLK_DEV_AIU_ADC "CLKGATE_AIU_ADC"
+#define GCLK_REG_AIU_ADC (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_ADC (1<<13)
+
+#define GCLK_IDX_BLK_MOV 46
+#define GCLK_NAME_BLK_MOV "BLK_MOV"
+#define GCLK_DEV_BLK_MOV "CLKGATE_BLK_MOV"
+#define GCLK_REG_BLK_MOV (HHI_GCLK_MPEG1)
+#define GCLK_MASK_BLK_MOV (1<<14)
+
+/* NEW ADD */
+#define GCLK_IDX_AIU_TOP_LEVEL 47
+#define GCLK_NAME_AIU_TOP_LEVEL "AIU_TOP_LEVEL"
+#define GCLK_DEV_AIU_TOP_LEVEL "CLKGATE_AIU_TOP_LEVEL"
+#define GCLK_REG_AIU_TOP_LEVEL (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_TOP_LEVEL (1<<15)
+
+//g12a no reg
+#if 0
+#define GCLK_NAME_PCM_MCLK "PCM_MCLK"
+#define GCLK_REG_PCM_MCLK (HHI_PCM_CLK_CNTL)
+#define GCLK_MASK_PCM_MCLK (1<<9)
+
+#define GCLK_NAME_PCM_SCLK "PCM_SCLK"
+#define GCLK_REG_PCM_SCLK (HHI_PCM_CLK_CNTL)
+#define GCLK_MASK_PCM_SCLK (1<<22)
+#endif
+
+#define GCLK_IDX_UART1 48
+#define GCLK_NAME_UART1 "UART1"
+#define GCLK_DEV_UART1 "CLKGATE_UART1"
+#define GCLK_REG_UART1 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_UART1 (1<<16)
+
+#define GCLK_IDX_RESERVED1_4 49
+#define GCLK_NAME_RESERVED1_4 "RESERVED1_4"
+#define GCLK_DEV_RESERVED1_4 "CLKGATE_RESERVED1_4"
+#define GCLK_REG_RESERVED1_4 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_4 (1<<17)
+
+/* NEW ADD */
+#define GCLK_IDX_RESERVED1_5 50
+#define GCLK_NAME_RESERVED1_5 "RESERVED1_5"
+#define GCLK_DEV_RESERVED1_5 "CLKGATE_RESERVED1_5"
+#define GCLK_REG_RESERVED1_5 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_5 (1<<18)
+
+#define GCLK_IDX_RESERVED1_6 51
+#define GCLK_NAME_RESERVED1_6 "RESERVED1_6"
+#define GCLK_DEV_RESERVED1_6 "CLKGATE_RESERVED1_6"
+#define GCLK_REG_RESERVED1_6 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_6 (1<<19)
+
+#define GCLK_IDX_GE2D 52
+#define GCLK_NAME_GE2D "GE2D"
+#define GCLK_DEV_GE2D "CLKGATE_GE2D"
+#define GCLK_REG_GE2D (HHI_GCLK_MPEG1)
+#define GCLK_MASK_GE2D (1<<20)
+
+#define GCLK_IDX_USB0 53
+#define GCLK_NAME_USB0 "USB0"
+#define GCLK_DEV_USB0 "CLKGATE_USB0"
+#define GCLK_REG_USB0 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_USB0 (1<<21)
+
+#define GCLK_IDX_USB1 54
+#define GCLK_NAME_USB1 "USB1"
+#define GCLK_DEV_USB1 "CLKGATE_USB1"
+#define GCLK_REG_USB1 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_USB1 (1<<22)
+
+#define GCLK_IDX_RESET 55
+#define GCLK_NAME_RESET "RESET"
+#define GCLK_DEV_RESET "CLKGATE_RESET"
+#define GCLK_REG_RESET (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESET (1<<23)
+
+#define GCLK_IDX_NAND_CLK 56
+#define GCLK_NAME_NAND_CLK "NAND CLK"
+#define GCLK_DEV_NAND_CLK "HHI_NAND_CLK"
+#define GCLK_REG_NAND_CLK (HHI_NAND_CLK_CNTL)
+#define GCLK_MASK_NAND_CLK (1<<7)
+
+#define GCLK_IDX_HIU_PARSER_TOP 57
+#define GCLK_NAME_HIU_PARSER_TOP "HIU_PARSER_TOP"
+#define GCLK_DEV_HIU_PARSER_TOP "CLKGATE_HIU_PARSER_TOP"
+#define GCLK_REG_HIU_PARSER_TOP (HHI_GCLK_MPEG1)
+#define GCLK_MASK_HIU_PARSER_TOP (1<<25)
+
+/* NEW ADD */
+
+/* g12a no reg */
+#if 0
+#define GCLK_NAME_USB_CLK "USB_CLK"
+#define GCLK_REG_USB_CLK (HHI_USB_CLK_CNTL)
+#define GCLK_MASK_USB_CLK (1<<9)
+#endif
+
+#define GCLK_IDX_USB_GENERAL 58
+#define GCLK_NAME_USB_GENERAL "USB_GENERAL"
+#define GCLK_DEV_USB_GENERAL "CLKGATE_USB_GENERAL"
+#define GCLK_REG_USB_GENERAL (HHI_GCLK_MPEG1)
+#define GCLK_MASK_USB_GENERAL (1<<26)
+
+#define GCLK_IDX_RESERVED1_7 59
+#define GCLK_NAME_RESERVED1_7 "RESERVED1_7"
+#define GCLK_DEV_RESERVED1_7 "CLKGATE_RESERVED1_7"
+#define GCLK_REG_RESERVED1_7 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_7 (1<<27)
+
+/* #define GCLK_IDX_VDIN1 60 */
+/* #define GCLK_NAME_VDIN1 "VDIN1" */
+/* #define GCLK_DEV_VDIN1 "CLKGATE_VDIN1" */
+/* #define GCLK_REG_VDIN1 (HHI_GCLK_MPEG1) */
+/* #define GCLK_MASK_VDIN1 (1<<28) */
+
+#define GCLK_IDX_AHB_ARB0 61
+#define GCLK_NAME_AHB_ARB0 "AHB_ARB0"
+#define GCLK_DEV_AHB_ARB0 "CLKGATE_AHB_ARB0"
+#define GCLK_REG_AHB_ARB0 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AHB_ARB0 (1<<29)
+
+#define GCLK_IDX_EFUSE 62
+#define GCLK_NAME_EFUSE "EFUSE"
+#define GCLK_DEV_EFUSE "CLKGATE_EFUSE"
+#define GCLK_REG_EFUSE (HHI_GCLK_MPEG1)
+#define GCLK_MASK_EFUSE (1<<30)
+
+#define GCLK_IDX_ROM_CLK 63
+#define GCLK_NAME_ROM_CLK "ROM_CLK"
+#define GCLK_DEV_ROM_CLK "CLKGATE_ROM_CLK"
+#define GCLK_REG_ROM_CLK (HHI_GCLK_MPEG1)
+#define GCLK_MASK_ROM_CLK (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_RESERVED2_0 64
+#define GCLK_NAME_RESERVED2_0 "RESERVED2_0"
+#define GCLK_DEV_RESERVED2_0 "CLKGATE_RESERVED2_0"
+#define GCLK_REG_RESERVED2_0 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_0 (1<<0)
+
+#define GCLK_IDX_AHB_DATA_BUS 65
+#define GCLK_NAME_AHB_DATA_BUS "AHB_DATA_BUS"
+#define GCLK_DEV_AHB_DATA_BUS "CLKGATE_AHB_DATA_BUS"
+#define GCLK_REG_AHB_DATA_BUS (HHI_GCLK_MPEG2)
+#define GCLK_MASK_AHB_DATA_BUS (1<<1)
+
+#define GCLK_IDX_AHB_CONTROL_BUS 66
+#define GCLK_NAME_AHB_CONTROL_BUS "AHB_CONTROL_BUS"
+#define GCLK_DEV_AHB_CONTROL_BUS "CLKGATE_AHB_CONTROL_BUS"
+#define GCLK_REG_AHB_CONTROL_BUS (HHI_GCLK_MPEG2)
+#define GCLK_MASK_AHB_CONTROL_BUS (1<<2)
+
+#define GCLK_IDX_HDMI_INTR_SYNC 67
+#define GCLK_NAME_HDMI_INTR_SYNC "HDMI_INTR_SYNC"
+#define GCLK_DEV_HDMI_INTR_SYNC "CLKGATE_HDMI_INTR_SYNC"
+#define GCLK_REG_HDMI_INTR_SYNC (HHI_GCLK_MPEG2)
+#define GCLK_MASK_HDMI_INTR_SYNC (1<<3)
+
+#define GCLK_IDX_HDMI_PCLK 68
+#define GCLK_NAME_HDMI_PCLK "HDMI_PCLK"
+#define GCLK_DEV_HDMI_PCLK "CLKGATE_HDMI_PCLK"
+#define GCLK_REG_HDMI_PCLK (HHI_GCLK_MPEG2)
+#define GCLK_MASK_HDMI_PCLK (1<<4)
+
+#define GCLK_IDX_PDM 69
+#define GCLK_NAME_PDM "PDM"
+#define GCLK_DEV_PDM "CLKGATE_PDM"
+#define GCLK_REG_PDM (HHI_GCLK_MPEG2)
+#define GCLK_MASK_PDM (1<<5)
+
+#define GCLK_IDX_BT656 70
+#define GCLK_NAME_BT656 "BT656"
+#define GCLK_DEV_BT656 "CLKGATE_BT656"
+#define GCLK_REG_BT656 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_BT656 (1<<6)
+
+#define GCLK_IDX_BT656_2 71
+#define GCLK_NAME_BT656_2 "BT656_2"
+#define GCLK_DEV_BT656_2 "CLKGATE_BT656_2"
+#define GCLK_REG_BT656_2 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_BT656_2 (1<<7)
+
+#define GCLK_IDX_MISC_USB1_TO_DDR 72
+#define GCLK_NAME_MISC_USB1_TO_DDR "MISC_USB1_TO_DDR"
+#define GCLK_DEV_MISC_USB1_TO_DDR "CLKGATE_MISC_USB1_TO_DDR"
+#define GCLK_REG_MISC_USB1_TO_DDR (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MISC_USB1_TO_DDR (1<<8)
+
+#define GCLK_IDX_MISC_USB0_TO_DDR 73
+#define GCLK_NAME_MISC_USB0_TO_DDR "MISC_USB0_TO_DDR"
+#define GCLK_DEV_MISC_USB0_TO_DDR "CLKGATE_MISC_USB0_TO_DDR"
+#define GCLK_REG_MISC_USB0_TO_DDR (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MISC_USB0_TO_DDR (1<<9)
+
+#define GCLK_IDX_RESERVED2_4 74
+#define GCLK_NAME_RESERVED2_4 "RESERVED2_4"
+#define GCLK_DEV_RESERVED2_4 "CLKGATE_RESERVED2_4"
+#define GCLK_REG_RESERVED2_4 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_4 (1<<10)
+
+#define GCLK_IDX_MMC_PCLK 75
+#define GCLK_NAME_MMC_PCLK "MMC_PCLK"
+#define GCLK_DEV_MMC_PCLK "CLKGATE_MMC_PCLK"
+#define GCLK_REG_MMC_PCLK (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MMC_PCLK (1<<11)
+
+//g12a no reg
+#if 0
+#define GCLK_NAME_MMC_A_PCLK "MMC_A_PCLK"
+#define GCLK_REG_MMC_A_PCLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_MMC_A_PCLK (1<<2)
+
+#define GCLK_NAME_MMC_B_PCLK "MMC_B_PCLK"
+#define GCLK_REG_MMC_B_PCLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_MMC_B_PCLK (1<<1)
+
+#define GCLK_NAME_MMC_C_PCLK "MMC_C_PCLK"
+#define GCLK_REG_MMC_C_PCLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_MMC_C_PCLK (1<<0)
+#endif
+
+#define GCLK_NAME_EMMC_A_CLK "EMMC_A_CLK"
+#define GCLK_REG_EMMC_A_CLK (HHI_SD_EMMC_CLK_CNTL)
+#define GCLK_MASK_EMMC_A_CLK (1<<7)
+
+#define GCLK_NAME_EMMC_B_CLK "EMMC_B_CLK"
+#define GCLK_REG_EMMC_B_CLK (HHI_SD_EMMC_CLK_CNTL)
+#define GCLK_MASK_EMMC_B_CLK (1<<23)
+
+#define GCLK_IDX_MISC_DVIN 76
+#define GCLK_NAME_MISC_DVIN "MISC_DVIN"
+#define GCLK_DEV_MISC_DVIN "CLKGATE_MISC_DVIN"
+#define GCLK_REG_MISC_DVIN (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MISC_DVIN (1<<12)
+
+#define GCLK_IDX_RESERVED2_5 77
+#define GCLK_NAME_RESERVED2_5 "RESERVED2_5"
+#define GCLK_DEV_RESERVED2_5 "CLKGATE_RESERVED2_5"
+#define GCLK_REG_RESERVED2_5 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_5 (1<<13)
+
+#define GCLK_IDX_RESERVED2_6 78
+#define GCLK_NAME_RESERVED2_6 "RESERVED2_6"
+#define GCLK_DEV_RESERVED2_6 "CLKGATE_RESERVED2_6"
+#define GCLK_REG_RESERVED2_6 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_6 (1<<14)
+
+#define GCLK_IDX_UART2 79
+#define GCLK_NAME_UART2 "UART2"
+#define GCLK_DEV_UART2 "CLKGATE_UART2"
+#define GCLK_REG_UART2 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_UART2 (1<<15)
+
+#define GCLK_IDX_RESERVED2_7 80
+#define GCLK_NAME_RESERVED2_7 "RESERVED2_7"
+#define GCLK_DEV_RESERVED2_7 "CLKGATE_RESERVED2_7"
+#define GCLK_REG_RESERVED2_7 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_7 (1<<16)
+
+#define GCLK_IDX_RESERVED2_8 81
+#define GCLK_NAME_RESERVED2_8 "RESERVED2_8"
+#define GCLK_DEV_RESERVED2_8 "CLKGATE_RESERVED2_8"
+#define GCLK_REG_RESERVED2_8 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_8 (1<<17)
+
+#define GCLK_IDX_RESERVED2_9 82
+#define GCLK_NAME_RESERVED2_9 "RESERVED2_9"
+#define GCLK_DEV_RESERVED2_9 "CLKGATE_RESERVED2_9"
+#define GCLK_REG_RESERVED2_9 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_9 (1<<18)
+
+#define GCLK_IDX_RESERVED2_A 83
+#define GCLK_NAME_RESERVED2_A "RESERVED2_A"
+#define GCLK_DEV_RESERVED2_A "CLKGATE_RESERVED2_A"
+#define GCLK_REG_RESERVED2_A (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_A (1<<19)
+
+#define GCLK_IDX_RESERVED2_B 84
+#define GCLK_NAME_RESERVED2_B "RESERVED2_B"
+#define GCLK_DEV_RESERVED2_B "CLKGATE_RESERVED2_B"
+#define GCLK_REG_RESERVED2_B (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_B (1<<20)
+
+#define GCLK_IDX_UART3 85
+#define GCLK_NAME_UART3 "UART3"
+#define GCLK_DEV_UART3 "CLKGATE_UART3"
+#define GCLK_REG_UART3 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_UART3 (1<<21)
+
+#define GCLK_IDX_SANA 86
+#define GCLK_NAME_SANA "SANA"
+#define GCLK_DEV_SANA "CLKGATE_SANA"
+#define GCLK_REG_SANA (HHI_GCLK_MPEG2)
+#define GCLK_MASK_SANA (1<<22)
+
+#define GCLK_IDX_RESERVED2_D 87
+#define GCLK_NAME_RESERVED2_D "RESERVED2_D"
+#define GCLK_DEV_RESERVED2_D "CLKGATE_RESERVED2_D"
+#define GCLK_REG_RESERVED2_D (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_D (1<<23)
+
+#define GCLK_IDX_RESERVED2_E 88
+#define GCLK_NAME_RESERVED2_E "RESERVED2_E"
+#define GCLK_DEV_RESERVED2_E "CLKGATE_RESERVED2_E"
+#define GCLK_REG_RESERVED2_E (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_E (1<<24)
+
+#define GCLK_IDX_VPU_INTR 89
+#define GCLK_NAME_VPU_INTR "VPU_INTR"
+#define GCLK_DEV_VPU_INTR "CLKGATE_VPU_INTR"
+#define GCLK_REG_VPU_INTR (HHI_GCLK_MPEG2)
+#define GCLK_MASK_VPU_INTR (1<<25)
+
+#define GCLK_IDX_SECURE_AHP_APB3 90
+#define GCLK_NAME_SECURE_AHP_APB3 "SECURE_AHP_APB3"
+#define GCLK_DEV_SECURE_AHP_APB3 "CLKGATE_SECURE_AHP_APB3"
+#define GCLK_REG_SECURE_AHP_APB3 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_SECURE_AHP_APB3 (1<<26)
+
+#define GCLK_IDX_RESERVED2_F 91
+#define GCLK_NAME_RESERVED2_F "RESERVED2_F"
+#define GCLK_DEV_RESERVED2_F "CLKGATE_RESERVED2_F"
+#define GCLK_REG_RESERVED2_F (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_F (1<<27)
+
+#define GCLK_IDX_RESERVED2_10 92
+#define GCLK_NAME_RESERVED2_10 "RESERVED2_10"
+#define GCLK_DEV_RESERVED2_10 "CLKGATE_RESERVED2_10"
+#define GCLK_REG_RESERVED2_10 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_10 (1<<28)
+
+#define GCLK_IDX_CLK81_TO_A9 93
+#define GCLK_NAME_CLK81_TO_A9 "CLK81_TO_A9"
+#define GCLK_DEV_CLK81_TO_A9 "CLKGATE_CLK81_TO_A9"
+#define GCLK_REG_CLK81_TO_A9 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_CLK81_TO_A9 (1<<29)
+
+#define GCLK_IDX_GIC 94
+#define GCLK_NAME_GIC "GIC"
+#define GCLK_DEV_GIC "CLKGATE_GIC"
+#define GCLK_REG_GIC (HHI_GCLK_MPEG2)
+#define GCLK_MASK_GIC (1<<30)
+
+#define GCLK_IDX_RESERVED2_12 95
+#define GCLK_NAME_RESERVED2_12 "RESERVED2_12"
+#define GCLK_DEV_RESERVED2_12 "CLKGATE_RESERVED2_12"
+#define GCLK_REG_RESERVED2_12 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_12 (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_RESERVED3_0 96
+#define GCLK_NAME_RESERVED3_0 "RESERVED3_0"
+#define GCLK_DEV_RESERVED3_0 "CLKGATE_RESERVED3_0"
+#define GCLK_REG_RESERVED3_0 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_0 (1<<0)
+
+#define GCLK_IDX_VCLK2_VENCI 97
+#define GCLK_NAME_VCLK2_VENCI "VCLK2_VENCI"
+#define GCLK_DEV_VCLK2_VENCI "CLKGATE_VCLK2_VENCI"
+#define GCLK_REG_VCLK2_VENCI (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCI (1<<1)
+
+#define GCLK_IDX_VCLK2_VENCI1 98
+#define GCLK_NAME_VCLK2_VENCI1 "VCLK2_VENCI1"
+#define GCLK_DEV_VCLK2_VENCI1 "CLKGATE_VCLK2_VENCI1"
+#define GCLK_REG_VCLK2_VENCI1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCI1 (1<<2)
+
+#define GCLK_IDX_VCLK2_VENCP 99
+#define GCLK_NAME_VCLK2_VENCP "VCLK2_VENCP"
+#define GCLK_DEV_VCLK2_VENCP "CLKGATE_VCLK2_VENCP"
+#define GCLK_REG_VCLK2_VENCP (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCP (1<<3)
+
+#define GCLK_IDX_VCLK2_VENCP1 100
+#define GCLK_NAME_VCLK2_VENCP1 "VCLK2_VENCP1"
+#define GCLK_DEV_VCLK2_VENCP1 "CLKGATE_VCLK2_VENCP1"
+#define GCLK_REG_VCLK2_VENCP1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCP1 (1<<4)
+
+#define GCLK_IDX_VCLK2_VENCT 101
+#define GCLK_NAME_VCLK2_VENCT "VCLK2_VENCT"
+#define GCLK_DEV_VCLK2_VENCT "CLKGATE_VCLK2_VENCT"
+#define GCLK_REG_VCLK2_VENCT (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCT (1<<5)
+
+#define GCLK_IDX_VCLK2_VENCT1 102
+#define GCLK_NAME_VCLK2_VENCT1 "VCLK2_VENCT1"
+#define GCLK_DEV_VCLK2_VENCT1 "CLKGATE_VCLK2_VENCT1"
+#define GCLK_REG_VCLK2_VENCT1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCT1 (1<<6)
+
+#define GCLK_IDX_VCLK2_OTHER 103
+#define GCLK_NAME_VCLK2_OTHER "VCLK2_OTHER"
+#define GCLK_DEV_VCLK2_OTHER "CLKGATE_VCLK2_OTHER"
+#define GCLK_REG_VCLK2_OTHER (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_OTHER (1<<7)
+
+#define GCLK_IDX_VCLK2_ENCI 104
+#define GCLK_NAME_VCLK2_ENCI "VCLK2_ENCI"
+#define GCLK_DEV_VCLK2_ENCI "CLKGATE_VCLK2_ENCI"
+#define GCLK_REG_VCLK2_ENCI (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCI (1<<8)
+
+#define GCLK_IDX_VCLK2_ENCP 105
+#define GCLK_NAME_VCLK2_ENCP "VCLK2_ENCP"
+#define GCLK_DEV_VCLK2_ENCP "CLKGATE_VCLK2_ENCP"
+#define GCLK_REG_VCLK2_ENCP (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCP (1<<9)
+
+#define GCLK_IDX_DAC_CLK 106
+#define GCLK_NAME_DAC_CLK "DAC_CLK"
+#define GCLK_DEV_DAC_CLK "CLKGATE_DAC_CLK"
+#define GCLK_REG_DAC_CLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_DAC_CLK (1<<10)
+
+#define GCLK_IDX_RESERVED3_1 107
+#define GCLK_NAME_RESERVED3_1 "RESERVED3_1"
+#define GCLK_DEV_RESERVED3_1 "CLKGATE_RESERVED3_1"
+#define GCLK_REG_RESERVED3_1 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_1 (1<<11)
+
+#define GCLK_IDX_RESERVED3_2 108
+#define GCLK_NAME_RESERVED3_2 "RESERVED3_2"
+#define GCLK_DEV_RESERVED3_2 "CLKGATE_RESERVED3_2"
+#define GCLK_REG_RESERVED3_2 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_2 (1<<12)
+
+#define GCLK_IDX_RESERVED3_3 109
+#define GCLK_NAME_RESERVED3_3 "RESERVED3_3"
+#define GCLK_DEV_RESERVED3_3 "CLKGATE_RESERVED3_3"
+#define GCLK_REG_RESERVED3_3 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_3 (1<<13)
+
+#define GCLK_IDX_AIU_AOCLK 110
+#define GCLK_NAME_AIU_AOCLK "AIU_AOCLK"
+#define GCLK_DEV_AIU_AOCLK "CLKGATE_AIU_AOCLK"
+#define GCLK_REG_AIU_AOCLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_AIU_AOCLK (1<<14)
+
+#define GCLK_IDX_RESERVED3_4 111
+#define GCLK_NAME_RESERVED3_4 "RESERVED3_4"
+#define GCLK_DEV_RESERVED3_4 "CLKGATE_RESERVED3_4"
+#define GCLK_REG_RESERVED3_4 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_4 (1<<15)
+
+#define GCLK_IDX_AIU_ICE958_AMCLK 112
+#define GCLK_NAME_AIU_ICE958_AMCLK "AIU_ICE958_AMCLK"
+#define GCLK_DEV_AIU_ICE958_AMCLK "CLKGATE_AIU_ICE958_AMCLK"
+#define GCLK_REG_AIU_ICE958_AMCLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_AIU_ICE958_AMCLK (1<<16)
+
+#define GCLK_IDX_RESERVED3_5 113
+#define GCLK_NAME_RESERVED3_5 "RESERVED3_5"
+#define GCLK_DEV_RESERVED3_5 "CLKGATE_RESERVED3_5"
+#define GCLK_REG_RESERVED3_5 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_5 (1<<17)
+
+#define GCLK_IDX_RESERVED3_6 114
+#define GCLK_NAME_RESERVED3_6 "RESERVED3_6"
+#define GCLK_DEV_RESERVED3_6 "CLKGATE_RESERVED3_6"
+#define GCLK_REG_RESERVED3_6 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_6 (1<<18)
+
+#define GCLK_IDX_RESERVED3_7 115
+#define GCLK_NAME_RESERVED3_7 "RESERVED3_7"
+#define GCLK_DEV_RESERVED3_7 "CLKGATE_RESERVED3_7"
+#define GCLK_REG_RESERVED3_7 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_7 (1<<19)
+
+#define GCLK_IDX_ENC480P 116
+#define GCLK_NAME_ENC480P "ENC480P"
+#define GCLK_DEV_ENC480P "CLKGATE_ENC480P"
+#define GCLK_REG_ENC480P (HHI_GCLK_OTHER)
+#define GCLK_MASK_ENC480P (1<<20)
+
+#define GCLK_IDX_RANDOM_NUM_GEN1 117
+#define GCLK_NAME_RANDOM_NUM_GEN1 "RANDOM_NUM_GEN1"
+#define GCLK_DEV_RANDOM_NUM_GEN1 "CLKGATE_RANDOM_NUM_GEN1"
+#define GCLK_REG_RANDOM_NUM_GEN1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RANDOM_NUM_GEN1 (1<<21)
+
+#define GCLK_IDX_VCLK2_ENCT 118
+#define GCLK_NAME_VCLK2_ENCT "GCLK_VENCL_INT"
+#define GCLK_DEV_VCLK2_ENCT "CLKGATE_GCLK_VENCL_INT"
+#define GCLK_REG_VCLK2_ENCT (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCT (1<<22)
+
+#define GCLK_IDX_VCLK2_ENCL 119
+#define GCLK_NAME_VCLK2_ENCL "VLKC2_ENCL"
+#define GCLK_DEV_VCLK2_ENCL "CLKGATE_VCLK2_ENCL"
+#define GCLK_REG_VCLK2_ENCL (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCL (1<<23)
+
+#define GCLK_IDX_MMC_CLK 120
+#define GCLK_NAME_MMC_CLK "MMC_CLK"
+#define GCLK_DEV_MMC_CLK "CLKGATE_MMC_CLK"
+#define GCLK_REG_MMC_CLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_MMC_CLK (1<<24)
+
+#define GCLK_IDX_VCLK2_VENCL 121
+#define GCLK_NAME_VCLK2_VENCL "VCLK2_VENCL"
+#define GCLK_DEV_VCLK2_VENCL "CLKGATE_VCLK2_VENCL"
+#define GCLK_REG_VCLK2_VENCL (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCL (1<<25)
+
+#define GCLK_IDX_VCLK2_OTHER1 122
+#define GCLK_NAME_VCLK2_OTHER1 "VCLK2_OTHER1"
+#define GCLK_DEV_VCLK2_OTHER1 "CLKGATE_VCLK2_OTHER1"
+#define GCLK_REG_VCLK2_OTHER1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_OTHER1 (1<<26)
+
+#define GCLK_IDX_RESERVED3_9 123
+#define GCLK_NAME_RESERVED3_9 "RESERVED3_9"
+#define GCLK_DEV_RESERVED3_9 "CLKGATE_RESERVED3_9"
+#define GCLK_REG_RESERVED3_9 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_9 (1<<27)
+
+#define GCLK_IDX_RESERVED3_A 124
+#define GCLK_NAME_RESERVED3_A "RESERVED3_A"
+#define GCLK_DEV_RESERVED3_A "CLKGATE_RESERVED3_A"
+#define GCLK_REG_RESERVED3_A (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_A (1<<28)
+
+#define GCLK_IDX_RESERVED3_B 125
+#define GCLK_NAME_RESERVED3_B "RESERVED3_B"
+#define GCLK_DEV_RESERVED3_B "CLKGATE_RESERVED3_B"
+#define GCLK_REG_RESERVED3_B (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_B (1<<29)
+
+#define GCLK_IDX_RESERVED3_C 126
+#define GCLK_NAME_RESERVED3_C "RESERVED3_C"
+#define GCLK_DEV_RESERVED3_C "CLKGATE_RESERVED3_C"
+#define GCLK_REG_RESERVED3_C (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_C (1<<30)
+
+#define GCLK_IDX_EDP_CLK 127
+#define GCLK_NAME_EDP_CLK "EDP_CLK"
+#define GCLK_DEV_EDP_CLK "CLKGATE_EDP_CLK"
+#define GCLK_REG_EDP_CLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_EDP_CLK (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_MEDIA_CPU 128
+#define GCLK_NAME_MEDIA_CPU "MEDIA_CPU"
+#define GCLK_DEV_MEDIA_CPU "CLKGATE_MEDIA_CPU"
+#define GCLK_REG_MEDIA_CPU (HHI_GCLK_AO)
+#define GCLK_MASK_MEDIA_CPU (1<<0)
+
+#define GCLK_IDX_AHB_SRAM 129
+#define GCLK_NAME_AHB_SRAM "AHB_SRAM"
+#define GCLK_DEV_AHB_SRAM "CLKGATE_AHB_SRAM"
+#define GCLK_REG_AHB_SRAM (HHI_GCLK_AO)
+#define GCLK_MASK_AHB_SRAM (1<<1)
+
+#define GCLK_IDX_AHB_BUS 130
+#define GCLK_NAME_AHB_BUS "AHB_BUS"
+#define GCLK_DEV_AHB_BUS "CLKGATE_AHB_BUS"
+#define GCLK_REG_AHB_BUS (HHI_GCLK_AO)
+#define GCLK_MASK_AHB_BUS (1<<2)
+
+#define GCLK_IDX_AO_REGS 131
+#define GCLK_NAME_AO_REGS "AO_REGS"
+#define GCLK_DEV_AO_REGS "CLKGATE_AO_REGS"
+#define GCLK_REG_AO_REGS (HHI_GCLK_AO)
+#define GCLK_MASK_AO_REGS (1<<3)
+
+#define GCLK_NAME_I2C_AO "I2C_AO"
+#define GCLK_REG_I2C_AO (HHI_GCLK_AO)
+#define GCLK_MASK_I2C_AO (1<<4)
+
+
+#define GCLK_IDX_CTS_ENCI 132
+#define GCLK_NAME_CTS_ENCI "CTS_ENCI"
+#define GCLK_DEV_CTS_ENCI "CLKGATE_CTS_ENCI"
+#define GCLK_REG_CTS_ENCI (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCI (1<<0)
+
+#define GCLK_IDX_CTS_ENCT 133
+#define GCLK_NAME_CTS_ENCT "CTS_ENCT"
+#define GCLK_DEV_CTS_ENCT "CLKGATE_CTS_ENCT"
+#define GCLK_REG_CTS_ENCT (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCT (1<<1)
+
+#define GCLK_IDX_CTS_ENCP 134
+#define GCLK_NAME_CTS_ENCP "CTS_ENCP"
+#define GCLK_DEV_CTS_ENCP "CLKGATE_CTS_ENCP"
+#define GCLK_REG_CTS_ENCP (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCP (1<<2)
+
+#define GCLK_IDX_CTS_ENCL 135
+#define GCLK_NAME_CTS_ENCL "CTS_ENCL"
+#define GCLK_DEV_CTS_ENCL "CLKGATE_CTS_ENCL"
+#define GCLK_REG_CTS_ENCL (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCL (1<<3)
+
+#define GCLK_IDX_CTS_VDAC 136
+#define GCLK_NAME_CTS_VDAC "CTS_VDAC"
+#define GCLK_DEV_CTS_VDAC "CLKGATE_CTS_VDAC"
+#define GCLK_REG_CTS_VDAC (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_VDAC (1<<4)
+
+#define GCLK_IDX_CTS_HDMI_TX_PIXEL 137
+#define GCLK_NAME_CTS_HDMI_TX_PIXEL "CTS_HDMI_TX_PIXEL"
+#define GCLK_DEV_CTS_HDMI_TX_PIXEL "CLKGATE_CTS_HDMI_TX_PIXEL"
+#define GCLK_REG_CTS_HDMI_TX_PIXEL (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_HDMI_TX_PIXEL (1<<5)
+
+#define GCLK_IDX_AUD 138
+#define GCLK_NAME_AUD "AUD"
+#define GCLK_DEV_AUD "CLKGATE_AUD"
+#define GCLK_REG_AUD (HHI_AUD_CLK_CNTL)
+#define GCLK_MASK_AUD (1<<23)
+
+
+#define GCLK_IDX_AUD2 138
+#define GCLK_NAME_AUD2 "AUD2"
+#define GCLK_DEV_AUD2 "CLKGATE_AUD2"
+#define GCLK_REG_AUD2 (HHI_AUD_CLK_CNTL)
+#define GCLK_MASK_AUD2 (1<<8)
+
+
+#define GCLK_NAME_AUD_CLK_2 "AUD_CLK_2"
+#define GCLK_REG_AUD_CLK_2 (HHI_AUD_CLK_CNTL2)
+#define GCLK_MASK_AUD_CLK_2 (1<<8)
+
+#define GCLK_IDX_AUD_CLK_3 138
+#define GCLK_NAME_AUD_CLK_3 "AUD_CLK"
+#define GCLK_DEV_AUD_CLK_3 "CLKGATE_AUD_CLK"
+#define GCLK_REG_AUD_CLK_3 (HHI_AUD_CLK_CNTL3)
+#define GCLK_MASK_AUD_CLK_3 (1<<16)
+
+#define GCLK_IDX_LCD_AN_PHY2 139
+#define GCLK_NAME_LCD_AN_PHY2 "LCD_AN_PHY2"
+#define GCLK_DEV_LCD_AN_PHY2 "CLKGATE_LCD_AN_PHY2"
+#define GCLK_REG_LCD_AN_PHY2 (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_LCD_AN_PHY2 (1<<7)
+
+#define GCLK_IDX_LCD_AN_PHY3 140
+#define GCLK_NAME_LCD_AN_PHY3 "LCD_AN_PHY3"
+#define GCLK_DEV_LCD_AN_PHY3 "CLKGATE_LCD_AN_PHY3"
+#define GCLK_REG_LCD_AN_PHY3 (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_LCD_AN_PHY3 (1<<6)
+
+#define GCLK_NAME_ATV_DEMO_VDAC "ATV_DEMO_VDAC"
+#define GCLK_REG_ATV_DEMO_VDAC (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_ATV_DEMO_VDAC (1<<8)
+
+#define GCLK_IDX_HDMI_PLL_CNTL 142
+#define GCLK_NAME_HDMI_PLL_CNTL "HDMI_PLL_CNTL"
+#define GCLK_DEV_HDMI_PLL_CNTL "GATE_HDMI_PLL_CNTL"
+#define GCLK_REG_HDMI_PLL_CNTL (HHI_HDMI_PLL_CNTL)
+#define GCLK_MASK_HDMI_PLL_CNTL (1<<30)
+
+#define GCLK_NAME_HDMITX_CLK "HDMITX_CLK"
+#define GCLK_REG_HDMITX_CLK (HHI_HDMI_CLK_CNTL)
+#define GCLK_MASK_HDMITX_CLK (1<<8)
+
+
+#define GCLK_NAME_HDMITX_CLK "HDMITX_CLK"
+#define GCLK_REG_HDMITX_CLK (HHI_HDMI_CLK_CNTL)
+#define GCLK_MASK_HDMITX_CLK (1<<8)
+
+#define GCLK_IDX_VDEC_CLK_1 144
+#define GCLK_NAME_VDEC_CLK_1 "VDEC_CLK_1"
+#define GCLK_DEV_VDEC_CLK_1 "CLKGATE_VDEC_CLK_1"
+#define GCLK_REG_VDEC_CLK_1 (HHI_VDEC_CLK_CNTL)
+#define GCLK_MASK_VDEC_CLK_1 (1<<8)
+
+#define GCLK_NAME_VDEC_CLK_2 "VDEC_CLK_2"
+#define GCLK_REG_VDEC_CLK_2 (HHI_VDEC3_CLK_CNTL)
+#define GCLK_MASK_VDEC_CLK_2 (1<<8)
+
+#define GCLK_NAME_VDEC2_CLK_1 "VDEC2_CLK_1"
+#define GCLK_REG_VDEC2_CLK_1 (HHI_VDEC2_CLK_CNTL)
+#define GCLK_MASK_VDEC2_CLK_1 (1<<8)
+
+#define GCLK_NAME_VDEC2_CLK_2 "VDEC2_CLK_2"
+#define GCLK_REG_VDEC2_CLK_2 (HHI_VDEC4_CLK_CNTL)
+#define GCLK_MASK_VDEC2_CLK_2 (1<<8)
+
+#define GCLK_IDX_HCODEC_CLK_1 145
+#define GCLK_NAME_HCODEC_CLK_1 "HCODEC_CLK"
+#define GCLK_DEV_HCODEC_CLK_1 "CLKGATE_HCODEC_CLK"
+#define GCLK_REG_HCODEC_CLK_1 (HHI_VDEC_CLK_CNTL)
+#define GCLK_MASK_HCODEC_CLK_1 (1<<24)
+
+#define GCLK_NAME_HCODEC_CLK_2 "HCODEC_CLK_2"
+#define GCLK_REG_HCODEC_CLK_2 (HHI_VDEC3_CLK_CNTL)
+#define GCLK_MASK_HCODEC_CLK_2 (1<<24)
+
+#define GCLK_NAME_HEVC_CLK_1 "HCODEC_CLK_1"
+#define GCLK_REG_HEVC_CLK_1 (HHI_VDEC2_CLK_CNTL)
+#define GCLK_MASK_HEVC_CLK_1 (1<<24)
+
+#define GCLK_NAME_HEVC_CLK_2 "HEVC_CLK_2"
+#define GCLK_REG_HEVC_CLK_2 (HHI_VDEC4_CLK_CNTL)
+#define GCLK_MASK_HEVC_CLK_2 (1<<24)
+
+#define GCLK_IDX_GEN_CLK 146
+#define GCLK_NAME_GEN_CLK "GEN_CLK"
+#define GCLK_DEV_GEN_CLK "CLKGATE_HCODEC_CLK"
+#define GCLK_REG_GEN_CLK (HHI_GEN_CLK_CNTL)
+#define GCLK_MASK_GEN_CLK (1<<11)
+
+#define GCLK_NAME_VPU_CLK_1 "VPU_CLK_1"
+#define GCLK_REG_VPU_CLK_1 (HHI_VPU_CLK_CNTL)
+#define GCLK_MASK_VPU_CLK_1 (1<<8)
+
+#define GCLK_NAME_VPU_CLK_2 "VPU_CLK_2"
+#define GCLK_REG_VPU_CLK_2 (HHI_VPU_CLK_CNTL)
+#define GCLK_MASK_VPU_CLK_2 (1<<24)
+
+
+#define GCLK_NAME_VPU_CLKB "VPU_CLKB"
+#define GCLK_REG_VPU_CLKB (HHI_VPU_CLKB_CNTL)
+#define GCLK_MASK_VPU_CLKB (1<<8)
+
+#define GCLK_NAME_VAPB_CLK_1 "VAPB_CLK_1"
+#define GCLK_REG_VAPB_CLK_1 (HHI_VAPBCLK_CNTL)
+#define GCLK_MASK_VAPB_CLK_1 (1<<8)
+
+#define GCLK_NAME_VAPB_CLK_2 "VAPB_CLK_2"
+#define GCLK_REG_VAPB_CLK_2 (HHI_VAPBCLK_CNTL)
+#define GCLK_MASK_VAPB_CLK_2 (1<<24)
+
+#define GCLK_NAME_MALI_CLK_1 "MALI_CLK_1"
+#define GCLK_REG_MALI_CLK_1 (HHI_MALI_CLK_CNTL)
+#define GCLK_MASK_MALI_CLK_1 (1<<8)
+
+#define GCLK_NAME_MALI_CLK_2 "MALI_CLK_2"
+#define GCLK_REG_MALI_CLK_2 (HHI_MALI_CLK_CNTL)
+#define GCLK_MASK_MALI_CLK_2 (1<<24)
+
+#define GCLK_NAME_PWM_A_CLK "PWM_A_CLK"
+#define GCLK_REG_PWM_A_CLK (CBUS_REG_ADDR(0x2156))
+#define GCLK_MASK_PWM_A_CLK (1<<15)
+
+#define GCLK_NAME_PWM_B_CLK "PWM_B_CLK"
+#define GCLK_REG_PWM_B_CLK (CBUS_REG_ADDR(0x2156))
+#define GCLK_MASK_PWM_B_CLK (1<<23)
+
+#define GCLK_NAME_PWM_C_CLK "PWM_C_CLK"
+#define GCLK_REG_PWM_C_CLK (CBUS_REG_ADDR(0x2196))
+#define GCLK_MASK_PWM_C_CLK (1<<15)
+
+#define GCLK_NAME_PWM_D_CLK "PWM_D_CLK"
+#define GCLK_REG_PWM_D_CLK (CBUS_REG_ADDR(0x2196))
+#define GCLK_MASK_PWM_D_CLK (1<<23)
+
+#define GCLK_NAME_PWM_E_CLK "PWM_E_CLK"
+#define GCLK_REG_PWM_E_CLK (CBUS_REG_ADDR(0x21b2))
+#define GCLK_MASK_PWM_E_CLK (1<<15)
+
+#define GCLK_NAME_PWM_F_CLK "PWM_D_CLK"
+#define GCLK_REG_PWM_F_CLK (CBUS_REG_ADDR(0x21b2))
+#define GCLK_MASK_PWM_F_CLK (1<<23)
+
+#define GCLK_NAME_VDIN_MEAS_CLK "VDIN_MEAS_CLK"
+#define GCLK_REG_VDIN_MEAS_CLK (HHI_VDIN_MEAS_CLK_CNTL)
+#define GCLK_MASK_VDIN_MEAS_CLK (1<<8)
+
+#define GCLK_NAME_MSR_CLK "MSR_CLK"
+#define GCLK_REG_MSR_CLK (CBUS_REG_ADDR(0x21d7))
+#define GCLK_MASK_MSR_CLK (1<<19)
+
+#define GCLK_NAME_MSR_HS_CLK "MSR_HS_CLK"
+#define GCLK_REG_MSR_HS_CLK (CBUS_REG_ADDR(0x21d9))
+#define GCLK_MASK_MSR_HS_CLK (1<<28)
+
+#define GCLK_NAME_32K_CLK "32K_CLK"
+#define GCLK_REG_32K_CLK (HHI_32K_CLK_CNTL)
+#define GCLK_MASK_32K_CLK (1<<15)
+
+
+
+#define GCLK_IDX_MAX 200
+
+extern short GCLK_ref[GCLK_IDX_MAX];
+
+#define REGISTER_CLK(_MOD) \
+static struct clk CLK_##_MOD = { \
+ .name = GCLK_NAME_##_MOD, \
+ .clock_index = GCLK_IDX_##_MOD, \
+ .clock_gate_reg_adr = GCLK_REG_##_MOD, \
+ .clock_gate_reg_mask = GCLK_MASK_##_MOD, \
+}
+
+#define CLK_LOOKUP_ITEM(_MOD) \
+ { \
+ .dev_id = GCLK_DEV_##_MOD, \
+ .con_id = GCLK_NAME_##_MOD, \
+ .clk = &CLK_##_MOD, \
+ }
+
+
+
+/**********************/
+/* internal audio dac control */
+#define ADAC_RESET (0x5000+0x00*4)
+#define ADAC_LATCH (0x5000+0x01*4)
+#define ADAC_POWER_CTRL_REG1 (0x5000+0x10*4)
+#define ADAC_POWER_CTRL_REG2 (0x5000+0x11*4)
+
+int audio_internal_dac_disable(void);
+
+/* video dac control */
+int video_dac_enable(unsigned char enable_mask);
+
+int video_dac_disable(void);
+
+
+#endif
diff --git a/arch/arm/mach-meson/c2/sdio.c b/arch/arm/mach-meson/c2/sdio.c
new file mode 100644
index 0000000..14ec635
--- /dev/null
+++ b/arch/arm/mach-meson/c2/sdio.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <asm/arch/io.h>
+#include <asm/arch/cpu_sdio.h>
+#include <asm/arch/secure_apb.h>
+#include <amlogic/cpu_id.h>
+#include <common.h>
+
+void cpu_sd_emmc_pwr_prepare(unsigned port)
+{
+}
+int cpu_sd_emmc_init(unsigned port)
+{
+ return 0;
+}
+
+/* return:
+ 0: insert
+ 1: not insert
+ */
+__weak int sd_emmc_detect(unsigned port)
+{
+ int ret = 0;
+
+ return ret;
+}
+
+
diff --git a/arch/arm/mach-meson/c2/timer.c b/arch/arm/mach-meson/c2/timer.c
new file mode 100644
index 0000000..8c16210
--- /dev/null
+++ b/arch/arm/mach-meson/c2/timer.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timer.h>
+#include <asm/types.h>
+
+uint32_t get_time(void)
+{
+ return readl(SYSCTRL_TIMERE);
+}
+
+void _udelay(unsigned int us)
+{
+#ifndef CONFIG_PXP_EMULATOR
+ unsigned int t0 = get_time();
+
+ while (get_time() - t0 <= us)
+ ;
+#endif
+}
diff --git a/arch/arm/mach-meson/c2/tsensor.c b/arch/arm/mach-meson/c2/tsensor.c
new file mode 100644
index 0000000..18c4e79
--- /dev/null
+++ b/arch/arm/mach-meson/c2/tsensor.c
@@ -0,0 +1,276 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <command.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/mailbox.h>
+#include <asm/arch/tsensor.h>
+#include <asm/arch/bl31_apis.h>
+
+int tsensor_tz_calibration(unsigned int type, unsigned int data)
+{
+ int ret;
+
+ register long x0 asm("x0") = TSENSOR_CALI_SET;
+ register long x1 asm("x1") = type;
+ register long x2 asm("x2") = data;
+ register long x3 asm("x3") = 0;
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+ } while (0);
+ ret = x0;
+
+ if (!ret)
+ return -1;
+ else
+ return 0;
+}
+
+int r1p1_codetotemp(unsigned long value, unsigned int u_efuse)
+{
+ int64_t temp;
+
+ temp = (value * ts_m) * (1 << 16) / (100 * (1 << 16) + ts_n * value);
+ if (u_efuse & 0x8000) {
+ temp = ((temp - (u_efuse & 0x7fff)) * ts_a / (1 << 16) - ts_b) / 10;
+ } else {
+ temp = ((temp + (u_efuse & 0x7fff)) * ts_a / (1 << 16) - ts_b) / 10;
+ }
+ return temp;
+}
+
+int r1p1_temp_read(int type)
+{
+ unsigned int ret, u_efuse;
+ unsigned int value_ts, value_all_ts;
+ int tmp = -1;
+ int i, cnt;
+ char buf[2];
+
+ switch (type) {
+ case 1:
+ /*enable thermal1*/
+ writel(T_CONTROL_DATA, TS_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKTREE_TS_CLK_CTRL);
+ ret = readl(SYSCTRL_SEC_STATUS_REG13);/*thermal1 cali data in reg CFG10*/
+ mdelay(5);
+ buf[0] = (ret) & 0xff;
+ buf[1] = (ret >> 8) & 0xff;
+ u_efuse = buf[1];
+ u_efuse = (u_efuse << 8) | buf[0];
+ value_ts = 0;
+ value_all_ts = 0;
+ cnt = 0;
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_STAT0) & 0xffff;
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ value_ts = value_all_ts / cnt;
+ printf("tsensor avg: 0x%x, u_efuse: 0x%x\n", value_ts, u_efuse);
+ if (value_ts == 0) {
+ printf("tsensor read temp is zero\n");
+ return -1;
+ }
+ tmp = r1p1_codetotemp(value_ts, u_efuse);
+ printf("temp1: %d\n", tmp);
+ break;
+ default:
+ printf("r1p1 tsensor trim type not support\n");
+ return -1;
+ }
+ return tmp;
+}
+
+unsigned int r1p1_temptocode(unsigned long value, int tempbase)
+{
+ unsigned long tmp1, tmp2, u_efuse, signbit;
+
+ printf("a b m n: %d, %d, %d, %d\n", ts_a, ts_b, ts_m, ts_n);
+ tmp1 = ((tempbase * 10 + ts_b) * (1 << 16)) / ts_a; /*ideal u*/
+ printf("%s : tmp1: 0x%lx\n", __func__, tmp1);
+ tmp2 = (ts_m * value * (1 << 16)) / ((1 << 16) * 100 + ts_n * value);
+ printf("%s : tmp2: 0x%lx\n", __func__, tmp2);
+ signbit = ((tmp1 > tmp2) ? 0 : 1);
+ u_efuse = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
+ if (u_efuse > 0x3ff)
+ return 0;
+ u_efuse = (1 << 11) | (signbit << 10) | u_efuse;
+ return u_efuse;
+}
+
+int r1p1_temp_trim(int tempbase, int tempver, int type)
+{
+ unsigned int u_efuse, index_ts, index_ver;
+ unsigned int value_ts, value_all_ts;
+ int i, cnt;
+
+ printf("r1p1 temp trim type: 0x%x\n", type);
+ switch (type) {
+ case 0:
+ index_ver = 5;
+ tempver = tempver & 0xf;
+ if (tsensor_tz_calibration(index_ver, tempver) < 0)
+ printf("version tsensor thermal_calibration send error\n");
+ break;
+ case 1:
+ value_ts = 0;
+ value_all_ts = 0;
+ index_ts = 6;
+ cnt = 0;
+ /*enable thermal1*/
+ writel(T_CONTROL_DATA, TS_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKTREE_TS_CLK_CTRL);
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_STAT0) & 0xffff;
+ printf("tsensor read: 0x%x\n", value_ts);
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ value_ts = value_all_ts / cnt;
+ printf("tsensor avg: 0x%x\n", value_ts);
+ if (value_ts == 0) {
+ printf("tsensor read temp is zero\n");
+ return -1;
+ }
+ u_efuse = r1p1_temptocode(value_ts, tempbase);
+ if (!u_efuse) {
+ printf("ts efuse is greater than 0x3ff, not trim!\n");
+ return -1;
+ }
+ printf("ts efuse:%d\n", u_efuse);
+ printf("ts efuse:0x%x, index: %d\n", u_efuse, index_ts);
+ if (tsensor_tz_calibration(index_ts, u_efuse) < 0) {
+ printf("tsensor thermal_calibration send error\n");
+ return -1;
+ }
+ break;
+ default:
+ printf("r1p1 tsensor trim type not support\n");
+ return -1;
+ break;
+ }
+ return 0;
+}
+
+int temp_read_entry(void)
+{
+ unsigned int ret, ver;
+
+ ret = readl(SYSCTRL_SEC_STATUS_REG13);
+ ver = (ret >> 24) & 0xff;
+ if (0 == (ver & T_VER_MASK)) {
+ printf("tsensor no trimmed: calidata:0x%x\n",
+ readl(SYSCTRL_SEC_STATUS_REG13));
+ return -1;
+ }
+ ret = (ver & 0xf) >> 2;
+ switch (ret) {
+ case 0x2:
+ printf("temp type no support\n");
+ break;
+ case 0x0:
+ printf("temp type no support\n");
+ break;
+ case 0x1:
+ r1p1_temp_read(1);
+ printf("read the thermal\n");
+ break;
+ case 0x3:
+ printf("temp type no support\n");
+ return -1;
+ break;
+ default:
+ printf("thermal version not support!!!Please check!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int temp_trim_entry(int tempbase, int tempver)
+{
+ unsigned int ret, ver;
+
+ ret = readl(SYSCTRL_SEC_STATUS_REG13);
+ ver = (ret >> 24) & 0xff;
+ if (ver & T_VER_MASK) {
+ printf("tsensor trimmed: cali data: 0x%x\n",
+ readl(SYSCTRL_SEC_STATUS_REG13));
+ return -1;
+ }
+
+ printf("tsensor input trim tempver, tempver:0x%x\n", tempver);
+ switch (tempver) {
+ case 0x84:
+ ret = r1p1_temp_trim(tempbase, tempver, 1);
+ if (!ret) {
+ r1p1_temp_trim(tempbase, tempver, 0);
+ printf("triming the thermal by bbt-sw\n");
+ }
+ break;
+ case 0x85:
+ ret = r1p1_temp_trim(tempbase, tempver, 1);
+ if (!ret) {
+ r1p1_temp_trim(tempbase, tempver, 0);
+ printf("triming the thermal by bbt-ops\n");
+ }
+ break;
+ case 0x87:
+ ret = r1p1_temp_trim(tempbase, tempver, 1);
+ if (!ret) {
+ r1p1_temp_trim(tempbase, tempver, 0);
+ printf("triming the thermal by slt\n");
+ }
+ break;
+ default:
+ printf("thermal version not support!!!Please check!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int temp_cooling_entry(void)
+{
+#ifdef CONFIG_AML_TSENSOR_COOL
+ int temp;
+
+ while (1) {
+ temp = r1p1_temp_read(1);
+ if (temp <= CONFIG_HIGH_TEMP_COOL) {
+ printf("device cool done\n");
+ break;
+ }
+ mdelay(2000);
+ printf("warning: temp %d over %d, cooling\n", temp,
+ CONFIG_HIGH_TEMP_COOL);
+ }
+#endif
+ return 0;
+}
diff --git a/arch/arm/mach-meson/c2/usb.c b/arch/arm/mach-meson/c2/usb.c
new file mode 100644
index 0000000..e817e02
--- /dev/null
+++ b/arch/arm/mach-meson/c2/usb.c
@@ -0,0 +1,451 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <power/regulator.h>
+#include <clk.h>
+#include <asm/arch/usb.h>
+#include <amlogic/cpu_id.h>
+
+#include <linux/compat.h>
+#include <linux/ioport.h>
+#include <asm-generic/gpio.h>
+
+#define U2_CTRL_SLEEP_SHIFT 24
+#define U2_HHI_MEM_PD_MASK 0x3
+#define U2_HHI_MEM_PD_SHIFT 0x0
+#define U2_CTRL_ISO_SHIFT 24
+#define PHY20_RESET_LEVEL_BIT 4
+#define USB_RESET_BIT 3
+
+#define USB2_PHY_PLL_OFFSET_40 (0x0816a010)
+#define USB2_PHY_PLL_OFFSET_44 (0x000a72f2)
+
+#define USB2_PHY_PLL_OFFSET_34 (0x70000)
+
+#define USB2_PHY_PLL_OFFSET_50 (0xfe18)
+#define USB2_PHY_PLL_OFFSET_54 (0x2a)
+
+#define TUNING_DISCONNECT_THRESHOLD 0x34
+
+#define P_AO_RTI_GEN_PWR_SLEEP0 0xfe013008
+#define P_AO_RTI_GEN_PWR_ISO0 0xfe013004
+#define P_HHI_MEM_PD_REG0 0xfe013050
+
+struct phy usb_phys[2];
+
+int get_usbphy_baseinfo(struct phy *usb_phys)
+{
+ struct udevice *bus;
+ struct uclass *uc;
+ int ret, i;
+ int count;
+
+ if (usb_phys[0].dev && usb_phys[1].dev)
+ return 0;
+
+ ret = uclass_get(UCLASS_USB, &uc);
+ if (ret)
+ return ret;
+ uclass_foreach_dev(bus, uc) {
+ debug("bus->name=%s, bus->driver->name =%s\n",
+ bus->name, bus->driver->name);
+ count = dev_count_phandle_with_args(bus, "phys", "#phy-cells");
+ debug("usb phy count=%u\n", count);
+ if (count <= 0)
+ return count;
+ for (i = 0; i < count; i++) {
+ ret = generic_phy_get_by_index(bus, i, &usb_phys[i]);
+ if (ret && ret != -ENOENT) {
+ pr_err("Failed to get USB PHY%d for %s\n",
+ i, bus->name);
+ return ret;
+ }
+ ret = generic_phy_getinfo(&usb_phys[i]);
+ if (ret)
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static void usb_set_power_domain (void)
+{
+ writel((readl(P_AO_RTI_GEN_PWR_SLEEP0) & (~(0x1 << U2_CTRL_SLEEP_SHIFT))),
+ P_AO_RTI_GEN_PWR_SLEEP0);
+ writel((readl(P_AO_RTI_GEN_PWR_ISO0) & (~(0x1 << U2_CTRL_ISO_SHIFT))),
+ P_AO_RTI_GEN_PWR_ISO0);
+ writel((readl(P_HHI_MEM_PD_REG0)
+ & (~(U2_HHI_MEM_PD_MASK << U2_HHI_MEM_PD_SHIFT))), P_HHI_MEM_PD_REG0);
+
+ return;
+}
+
+static void usb_set_calibration_trim(uint32_t phy2_pll_base, uint8_t mode)
+{
+ uint32_t cali, value,i, tmp;
+ uint8_t cali_en;
+
+ if (mode == DEVICE_MODE) {
+ value = readl((unsigned long)(phy2_pll_base + 0x10));
+ value |= 0xfff;
+ writel(value, (unsigned long)(phy2_pll_base + 0x10));
+ return;
+ }
+
+ cali = readl((unsigned long)SYSCTRL_SEC_STATUS_REG12);
+ cali_en = (cali >> 30) & 0x1;
+ tmp = cali >> 26;
+
+ if (cali_en) {
+ tmp =tmp & 0xf;
+ cali = tmp;
+ if (cali > 12)
+ cali = 12;
+
+ value = readl((unsigned long)(phy2_pll_base + 0x10));
+ value &= (~0xfff);
+ for (i = 0; i < cali; i++)
+ value |= (1 << i);
+
+ writel(value, (unsigned long)(phy2_pll_base + 0x10));
+ }
+
+}
+
+static void usb_set_clock_freq(unsigned int clock_addr)
+{
+ unsigned int val = (1 << 8) | (2 << 9) | (9 << 0);
+ writel(val, (unsigned long)clock_addr);
+ return;
+}
+
+void usb_reset(unsigned int reset_addr, int bit){
+ *(volatile unsigned int *)(unsigned long)reset_addr = (1 << bit);
+}
+
+static void usb_enable_phy_pll (void)
+{
+ *(volatile uint32_t *)RESETCTRL_RESET1_LEVEL |= (1 << PHY20_RESET_LEVEL_BIT);
+}
+
+static void usb_disable_phy_pll (void)
+{
+ *(volatile uint32_t *)RESETCTRL_RESET1_LEVEL &= ~(1 << PHY20_RESET_LEVEL_BIT);
+}
+
+void set_usb_pll(uint32_t phy2_pll_base)
+{
+ uint32_t tmp, retry = 5;
+
+__retry:
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))=
+ (USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET);
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44)) =
+ USB2_PHY_PLL_OFFSET_44;
+ udelay(5);
+
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))=
+ (USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET | USB_PHY2_ENABLE);
+ udelay(5);
+
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))=
+ (USB2_PHY_PLL_OFFSET_40 | USB_PHY2_ENABLE);
+ udelay(10);
+
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44))=
+ (USB2_PHY_PLL_OFFSET_44 | USBPLL_LK_OD_EN);
+
+ udelay(200);
+
+ tmp = *(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40);
+
+ if (tmp >> USBPLL_LOCKFLAG_BIT) {
+ goto __setphyparameter;
+ } else {
+ retry --;
+ if (!retry)
+ goto __setphyparameter;
+ goto __retry;
+ }
+
+__setphyparameter:
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50))
+ = USB2_PHY_PLL_OFFSET_50;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x54))
+ = USB2_PHY_PLL_OFFSET_54;
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0xc)) =
+ TUNING_DISCONNECT_THRESHOLD;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x34))
+ = USB2_PHY_PLL_OFFSET_34;
+
+ debug("tuning_disconnect_threshold=0x%x\n", TUNING_DISCONNECT_THRESHOLD);
+}
+
+int usb_save_phy_dev (unsigned int number, struct phy *phy)
+{
+ usb_phys[number].dev = phy->dev;
+ usb_phys[number].id = phy->id;
+ return 0;
+}
+
+int usb2_phy_init (struct phy *phy) {
+ struct phy_aml_usb2_priv *priv = dev_get_priv(phy->dev);
+ struct u2p_aml_regs *u2p_aml_reg;
+ u2p_r0_t dev_u2p_r0;
+ u2p_r1_t dev_u2p_r1;
+ int i,cnt;
+
+ usb_save_phy_dev(0, phy);
+ usb_enable_phy_pll();
+ usb_set_power_domain();
+
+ priv->clktree_usb_bus_ctrl_addr = dev_read_addr_index(phy->dev, 2 + priv->u2_port_num);
+ if (priv->clktree_usb_bus_ctrl_addr == FDT_ADDR_T_NONE) {
+ pr_err("Coun't get clktree_usb_bus_ctrl addr index %d\n", 2 + priv->u2_port_num);
+ } else {
+ usb_set_clock_freq(priv->clktree_usb_bus_ctrl_addr);
+ }
+
+ usb_reset(priv->reset_addr, USB_RESET_BIT);
+
+ udelay(500);
+ priv->usbphy_reset_bit[0] = PHY20_RESET_LEVEL_BIT;
+
+ for (i = 0; i < priv->u2_port_num; i++) {
+ u2p_aml_reg = (struct u2p_aml_regs *)((ulong)(priv->base_addr + i * PHY_REGISTER_SIZE));
+ dev_u2p_r0.d32 = u2p_aml_reg->u2p_r0;
+ dev_u2p_r0.b.host_device= 1;
+ dev_u2p_r0.b.POR= 0;
+ u2p_aml_reg->u2p_r0 = dev_u2p_r0.d32;
+ udelay(10);
+ /***USB PHY RESET : reset1 and reset1_level both need set ***/
+ /***reset1: usb_reset ***/
+ /***reset1_level: usb_enable_phy_pll ***/
+ usb_reset(priv->reset_addr, priv->usbphy_reset_bit[i]);
+
+ usb_set_calibration_trim(priv->usb_phy2_pll_base_addr[i], HOST_MODE);
+
+ udelay(50);
+
+ /* wait for phy ready */
+ dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
+ cnt = 0;
+ while (dev_u2p_r1.b.phy_rdy != 1) {
+ dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
+ /*we wait phy ready max 1ms, common is 100us*/
+ if (cnt > 200)
+ break;
+ else {
+ cnt++;
+ udelay(5);
+ }
+ }
+ }
+
+ for (i = 0; i < priv->u2_port_num; i++) {
+ debug("------set usb pll\n");
+ set_usb_pll(priv->usb_phy2_pll_base_addr[i]);
+ writel(0xfe18, (unsigned long)(priv->usb_phy2_pll_base_addr[i] + 0x50));
+ }
+ return 0;
+
+}
+
+int usb2_phy_tuning(uint32_t phy2_pll_base, int port)
+{
+ return 0;
+}
+
+/**************************************************************/
+/* device mode config */
+/**************************************************************/
+unsigned int usb_get_dwc_a_base_addr(void)
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ int ret;
+
+ if (!usb_phys[0].dev) {
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ return usb2_priv->dwc2_a_addr;
+}
+
+unsigned int usb_get_device_mode_phy_base(void)
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ int ret;
+
+ if (!usb_phys[0].dev) {
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ return usb2_priv->usb_phy2_pll_base_addr[0];
+}
+
+void usb_phy_tuning_reset(void)
+{
+ return;
+}
+
+void usb_device_mode_init(void){
+ u2p_r0_t dev_u2p_r0;
+ u2p_r1_t dev_u2p_r1;
+
+ usb_r0_t dev_usb_r0;
+ usb_r4_t dev_usb_r4;
+ int cnt, ret;
+ u2p_aml_regs_t * u2p_aml_regs;
+ usb_aml_regs_t *usb_aml_regs;
+ struct phy_aml_usb2_priv *usb2_priv;
+ struct phy_aml_usb3_priv *usb3_priv;
+ unsigned int phy_base_addr, reset_addr;
+
+ usb_enable_phy_pll();
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return;
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ usb3_priv = dev_get_priv(usb_phys[1].dev);
+ if (!usb2_priv || !usb3_priv) {
+ printf("get usb phy address from dts failed\n");
+ return;
+ }
+
+ u2p_aml_regs = (u2p_aml_regs_t * )((ulong)usb2_priv->base_addr);
+ usb_aml_regs = (usb_aml_regs_t * )((ulong)usb3_priv->base_addr);
+ phy_base_addr = usb2_priv->usb_phy2_pll_base_addr[0];
+ reset_addr = usb2_priv->reset_addr;
+
+ usb_set_power_domain();
+ usb_set_clock_freq(CLKTREE_USB_BUSCLK_CTRL);
+
+ printf("PHY2=0x%08x\n", usb2_priv->base_addr);
+ if ((*(volatile uint32_t *)((ulong)(phy_base_addr + 0x38))) != 0) {
+ usb_phy_tuning_reset();
+ mdelay(150);
+ }
+
+ //step 1: usb controller reset
+ usb_reset(reset_addr, USB_RESET_BIT);
+
+ // step 3: enable usb INT internal USB
+ dev_usb_r0.d32 = usb_aml_regs->usb_r0;
+ dev_usb_r0.b.u2d_ss_scaledown_mode = 0;
+ dev_usb_r0.b.u2d_act = 1;
+ usb_aml_regs->usb_r0 = dev_usb_r0.d32;
+
+ // step 4: disable usb phy sleep
+ dev_usb_r4.d32 = usb_aml_regs->usb_r4;
+ dev_usb_r4.b.p21_SLEEPM0 = 1;
+ usb_aml_regs->usb_r4 = dev_usb_r4.d32;
+
+ // step 5: config phy21 device mode
+ dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0;
+ dev_u2p_r0.b.host_device= 0;
+ dev_u2p_r0.b.POR= 0;
+ u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32;
+
+ udelay(10);
+ //step 6: phy21 reset
+ usb_reset(reset_addr, PHY20_RESET_LEVEL_BIT);
+ udelay(50);
+ usb_set_calibration_trim(phy_base_addr, DEVICE_MODE);
+ udelay(50);
+
+ // step 6: wait for phy ready
+ dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
+ cnt = 0;
+ while ((dev_u2p_r1.d32 & 0x00000001) != 1) {
+ dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
+ if (cnt > 200)
+ break;
+ else {
+ cnt++;
+ udelay(5);
+ }
+ }
+
+ set_usb_pll(phy_base_addr);
+ writel(0xbe18, (unsigned long)(phy_base_addr + 0x50));
+ //--------------------------------------------------
+
+ // ------------- usb phy21 initinal end ----------
+
+ //--------------------------------------------------
+
+}
+
+static void usb_disable_phy(uint32_t phy2_pll_base)
+{
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))=
+ ((USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET) & (~USB_PHY2_ENABLE));
+ udelay(5);
+}
+
+static void usb_print_usb_baseinfo
+ (struct phy_aml_usb2_priv *usb2_priv, struct phy_aml_usb3_priv *usb3_priv)
+{
+ if (usb3_priv) {
+ printf("priv->usb3 port num = %d, config addr=0x%08x\n",
+ usb3_priv->usb3_port_num, usb3_priv->base_addr);
+ }
+ if (usb2_priv) {
+ printf("usb2 phy: config addr = 0x%08x, reset addr=0x%08x\n",
+ usb2_priv->base_addr, usb2_priv->reset_addr);
+
+ printf("usb2 phy: portnum=%d, phy-addr1= 0x%08x, phy-addr2= 0x%08x\n",
+ usb2_priv->u2_port_num, usb2_priv->usb_phy2_pll_base_addr[0],
+ usb2_priv->usb_phy2_pll_base_addr[1]);
+ printf("dwc2_a base addr: 0x%08x\n", usb2_priv->dwc2_a_addr);
+ }
+}
+
+int usb_aml_detect_operation(int argc, char * const argv[])
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ struct phy_aml_usb3_priv *usb3_priv;
+ int ret;
+
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ usb3_priv = dev_get_priv(usb_phys[1].dev);
+
+ if (argc >= 2) {
+ if (strncmp(argv[1], "disable", 7) == 0) {
+ usb_disable_phy_pll();
+ usb_disable_phy(usb2_priv->usb_phy2_pll_base_addr[0]);
+ printf("disable USB phy\n");
+ return 0;
+ }
+
+ if (strncmp(argv[1], "info", 4) == 0) {
+ usb_print_usb_baseinfo(usb2_priv, usb3_priv);
+ return 0;
+ }
+ }
+ return CMD_RET_USAGE;
+}
diff --git a/arch/arm/mach-meson/clk-mpll.c b/arch/arm/mach-meson/clk-mpll.c
new file mode 100644
index 0000000..e9886cf
--- /dev/null
+++ b/arch/arm/mach-meson/clk-mpll.c
@@ -0,0 +1,124 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ * MultiPhase Locked Loops are outputs from a PLL with additional frequency
+ * scaling capabilities. MPLL rates are calculated as:
+ *
+ * f(N2_integer, SDM_IN ) = 2.0G/(N2_integer + SDM_IN/16384)
+ */
+
+#include "clk-pll.h"
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/math64.h>
+#include <amlogic/clk_measure.h>
+#include <div64.h>
+
+#define SDM_DEN 16384
+#define N2_MIN 4
+#define N2_MAX 511
+#define MPLL_PARENT_RATE 2000*1000*1000
+
+static void params_from_rate(unsigned long requested_rate,
+ unsigned int *sdm,
+ unsigned int *n2,
+ u8 flags)
+{
+ uint64_t div = MPLL_PARENT_RATE;
+ uint64_t frac = do_div(div, requested_rate);
+
+ frac *= SDM_DEN;
+
+ if (flags & CLK_MESON_MPLL_ROUND_CLOSEST)
+ *sdm = DIV_ROUND_CLOSEST_ULL(frac, requested_rate);
+ else
+ *sdm = DIV_ROUND_UP_ULL(frac, requested_rate);
+
+ if (*sdm == SDM_DEN) {
+ *sdm = 0;
+ div += 1;
+ }
+
+ if (div < N2_MIN) {
+ *n2 = N2_MIN;
+ *sdm = 0;
+ } else if (div > N2_MAX) {
+ *n2 = N2_MAX;
+ *sdm = SDM_DEN - 1;
+ } else {
+ *n2 = div;
+ }
+}
+
+static void mpll_init(struct meson_clk_mpll_data *mpll)
+{
+ const struct reg_sequence *init_regs = mpll->init_regs;
+ unsigned int i, val;
+
+ for (i = 0; i < mpll->init_count; i++) {
+ val = init_regs[i].def;
+ writel(val, init_regs[i].reg);
+ if (init_regs[i].delay_us)
+ _udelay(init_regs[i].delay_us);
+ }
+
+ /* Enable the fractional part */
+ meson_parm_write(&mpll->sdm_en, 1);
+
+ /* Set spread spectrum if possible */
+ if (MESON_PARM_APPLICABLE(&mpll->ssen)) {
+ unsigned int ss =
+ mpll->flags & CLK_MESON_MPLL_SPREAD_SPECTRUM ? 1 : 0;
+ meson_parm_write(&mpll->ssen, ss);
+ }
+
+ /* Set the magic misc bit if required */
+ if (MESON_PARM_APPLICABLE(&mpll->misc))
+ meson_parm_write(&mpll->misc, 1);
+}
+
+int meson_mpll_set_rate(struct meson_clk_mpll_data *mpll,
+ unsigned long rate)
+{
+ unsigned int sdm, n2;
+
+ mpll_init(mpll);
+
+ params_from_rate(rate, &sdm, &n2, mpll->flags);
+
+ /* Set the fractional part */
+ meson_parm_write(&mpll->sdm, sdm);
+
+ /* Set the integer divider part */
+ meson_parm_write(&mpll->n2, n2);
+
+ /* Enable */
+ meson_parm_write(&mpll->en, 1);
+
+ return 0;
+}
+
+void meson_mpll_report(struct meson_clk_mpll_data *pll, unsigned int target, unsigned long res)
+{
+ if (((target-2*5) <= res) && (res <= (target+2*5)))
+ printf("%s target rate = %uM, clkmsr rate = %luM : Match\n", pll->name , target, res);
+ else
+ printf("%s target rate = %uM, clkmsr rate = %luM: Not Match\n", pll->name, target, res);
+}
+
+void meson_mpll_test(struct meson_clk_mpll_data *pll)
+{
+ int i;
+ unsigned long result;
+
+ for (i = 0; i < pll->def_cnt;i++) {
+ meson_mpll_set_rate(pll, (unsigned long)pll->def_rate[i] * (unsigned long)1000000);
+
+ result = clk_util_clk_msr(pll->clkmsr_id);
+
+ meson_mpll_report(pll, pll->def_rate[i], result);
+ }
+}
diff --git a/arch/arm/mach-meson/clk-pll.c b/arch/arm/mach-meson/clk-pll.c
new file mode 100644
index 0000000..eaf3c92
--- /dev/null
+++ b/arch/arm/mach-meson/clk-pll.c
@@ -0,0 +1,432 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ * In the most basic form, a Meson PLL is composed as follows:
+ *
+ * PLL
+ * +--------------------------------+
+ * | |
+ * | +--+ |
+ * in >>-----[ /N ]--->| | +-----+ |
+ * | | |------| DCO |---->> out
+ * | +--------->| | +--v--+ |
+ * | | +--+ | |
+ * | | | |
+ * | +--[ *(M + (F/Fmax) ]<--+ |
+ * | |
+ * +--------------------------------+
+ *
+ * out = in * (m + frac / frac_max) / n
+ */
+
+#include <linux/kernel.h>
+#include <linux/errno.h>
+#include <linux/math64.h>
+#include <div64.h>
+#include "clk-pll.h"
+#include <amlogic/clk_measure.h>
+#include <asm/arch/timer.h>
+
+#define PARENT_RATE 24000000
+//#define MESON_PLL_DEBUG /* pll debug macro */
+
+static int __pll_round_closest_mult(struct meson_clk_pll_data *pll)
+{
+ if ((pll->flags & CLK_MESON_PLL_ROUND_CLOSEST) &&
+ !MESON_PARM_APPLICABLE(&pll->frac))
+ return 1;
+
+ return 0;
+}
+
+static unsigned long __pll_params_to_rate(unsigned int m, unsigned int n,
+ unsigned int frac,
+ struct meson_clk_pll_data *pll,
+ unsigned int od)
+{
+ u64 rate = (u64)PARENT_RATE * m;
+ u64 frac_rate;
+
+ if (frac && MESON_PARM_APPLICABLE(&pll->frac)) {
+ frac_rate = (u64)PARENT_RATE * frac;
+ if (frac & (1 << (pll->frac.width - 1)))
+ rate -= DIV_ROUND_UP_ULL(frac_rate,
+ (1 << (pll->frac.width - 2)));
+ else
+ rate += DIV_ROUND_UP_ULL(frac_rate,
+ (1 << (pll->frac.width - 2)));
+ }
+
+ if (n == 0)
+ return 0;
+
+ return DIV_ROUND_UP_ULL(rate, n) >> od;
+}
+
+static unsigned int __pll_params_with_frac(unsigned long rate,
+ unsigned int m,
+ unsigned int n,
+ struct meson_clk_pll_data *pll)
+{
+ unsigned int frac_max = (1 << pll->frac.width);
+ u64 val = (u64)rate * n;
+
+ /* Bail out if we are already over the requested rate */
+ if (rate < PARENT_RATE * m / n)
+ return 0;
+
+ if (pll->flags & CLK_MESON_PLL_ROUND_CLOSEST)
+ val = DIV_ROUND_CLOSEST_ULL(val * frac_max, PARENT_RATE);
+ else
+ val = div_u64(val * frac_max, PARENT_RATE);
+
+ val -= m * frac_max;
+
+ return min((unsigned int)val, (frac_max - 1));
+}
+
+static bool meson_clk_pll_is_better(unsigned long rate,
+ unsigned long best,
+ unsigned long now,
+ struct meson_clk_pll_data *pll)
+{
+ if (__pll_round_closest_mult(pll)) {
+ /* Round Closest */
+ if (abs(now - rate) < abs(best - rate))
+ return true;
+ } else {
+ /* Round down */
+ if (now <= rate && best < now)
+ return true;
+ }
+
+ return false;
+}
+
+static int meson_clk_get_pll_table_index(unsigned int index,
+ unsigned int *m,
+ unsigned int *n,
+ struct meson_clk_pll_data *pll,
+ unsigned int *od)
+{
+ if (!pll->table[index].n)
+ return -EINVAL;
+
+ *m = pll->table[index].m;
+ *n = pll->table[index].n;
+ *od = pll->table[index].od;
+
+ return 0;
+}
+
+static int meson_clk_get_pll_get_index(unsigned long rate,
+ unsigned int index,
+ unsigned int *m,
+ unsigned int *n,
+ struct meson_clk_pll_data *pll,
+ unsigned int *od)
+{
+ /* only support table in arm32 */
+ if (pll->table)
+ return meson_clk_get_pll_table_index(index, m, n, pll, od);
+
+ return -EINVAL;
+}
+
+static int meson_clk_get_pll_settings(unsigned long rate,
+ unsigned int *best_m,
+ unsigned int *best_n,
+ struct meson_clk_pll_data *pll,
+ unsigned int *best_od)
+{
+ unsigned long best = 0, now = 0;
+ unsigned int i, m, n, od;
+ int ret;
+
+ for (i = 0, ret = 0; !ret; i++) {
+ ret = meson_clk_get_pll_get_index(rate,
+ i, &m, &n, pll, &od);
+ if (ret == -EINVAL)
+ break;
+
+ now = __pll_params_to_rate(m, n, 0, pll, od);
+ if (meson_clk_pll_is_better(rate, best, now, pll)) {
+ best = now;
+ *best_m = m;
+ *best_n = n;
+ *best_od = od;
+
+ if (now == rate)
+ break;
+ }
+ }
+
+ return best ? 0 : -EINVAL;
+}
+
+#if 0
+static long meson_clk_pll_round_rate(struct meson_clk_pll_data *pll, unsigned long rate)
+{
+ unsigned int m, n, frac, od;
+ unsigned long round;
+ int ret;
+
+ ret = meson_clk_get_pll_settings(rate, &m, &n, pll, &od);
+ if (ret)
+ return meson_clk_pll_recalc_rate(pll);
+
+ round = __pll_params_to_rate(m, n, 0, pll, od);
+
+ if (!MESON_PARM_APPLICABLE(&pll->frac) || rate == round)
+ return round;
+
+ /*
+ * The rate provided by the setting is not an exact match, let's
+ * try to improve the result using the fractional parameter
+ */
+ frac = __pll_params_with_frac(rate, m, n, pll);
+
+ return __pll_params_to_rate(m, n, frac, pll, od);
+}
+#endif
+
+static int meson_clk_pll_wait_lock(struct meson_clk_pll_data *pll)
+{
+ int delay = 1000;
+
+ do {
+ /* Is the clock locked now ? */
+ if (meson_parm_read(&pll->l))
+ return 0;
+ _udelay(1);
+ } while (delay--);
+
+ return -ETIMEDOUT;
+}
+
+void meson_clk_pll_disable(struct meson_clk_pll_data *pll)
+{
+ /* Put the pll is in reset */
+ setbits_le32(pll->rst.reg, 1 << pll->rst.shift);
+
+ /* Disable the pll */
+ setbits_le32(pll->en.reg, 0 << pll->en.shift);
+}
+
+int meson_pll_set_rate(struct meson_clk_pll_data *pll, unsigned long rate)
+{
+ unsigned int enabled, m, n, frac = 0, od, i, ret, val;
+ struct parm *pm = &pll->m;
+ struct parm *pn = &pll->n;
+ struct parm *pod = &pll->od;
+ struct parm *pfrac = &pll->frac;
+ const struct reg_sequence *init_regs = pll->init_regs;
+
+ if (PARENT_RATE == 0 || rate == 0) {
+ printf("%s, target rate is invalid\n", __func__);
+ return -EINVAL;
+ }
+
+ ret = meson_clk_get_pll_settings(rate, &m, &n, pll, &od);
+ if (ret)
+ return ret;
+
+ if (MESON_PARM_APPLICABLE(&pll->frac))
+ frac = __pll_params_with_frac(rate, m, n, pll);
+
+#ifdef MESON_PLL_DEBUG
+ printf("meson_pll_set_rate: %s trate = %lu, m = %d, n = %d, od = %d\n",
+ pll->name, rate, m, n, od);
+#endif
+ enabled = meson_parm_read(&pll->en);
+ if (enabled)
+ meson_clk_pll_disable(pll);
+
+ /* run the same sequence provided by vlsi */
+ for (i = 0; i < pll->init_count; i++) {
+ if (pn->reg == init_regs[i].reg) {
+ /* Clear M N Vbits and Update M N value */
+ val = init_regs[i].def;
+ val &= CLRPMASK(pn->width, pn->shift);
+ val &= CLRPMASK(pm->width, pm->shift);
+ val &= CLRPMASK(pod->width, pod->shift);
+ val |= n << pn->shift;
+ val |= m << pm->shift;
+ val |= od << pod->shift;
+ writel(val, pn->reg);
+ } else if (pfrac->reg == init_regs[i].reg &&
+ (MESON_PARM_APPLICABLE(&pll->frac))) {
+ /* Clear Frac bits and Update Frac value */
+ val = init_regs[i].def;
+ val &= CLRPMASK(pfrac->width, pfrac->shift);
+ val |= frac << pfrac->shift;
+ writel(val, pfrac->reg);
+ } else {
+ val = init_regs[i].def;
+ writel(val, init_regs[i].reg);
+ }
+ if (init_regs[i].delay_us)
+ _udelay(init_regs[i].delay_us);
+ }
+
+ if (meson_clk_pll_wait_lock(pll))
+ printf("%s pll did not lock, retrying?\n", pll->name);
+
+ return 0;
+}
+
+int meson_pll_set_one_rate(struct meson_clk_pll_data *pll, unsigned long rate)
+{
+ unsigned int enabled, i, val, j = 10;
+ const struct reg_sequence *init_regs = pll->init_regs;
+
+ if (PARENT_RATE == 0 || rate == 0)
+ return -EINVAL;
+
+ enabled = meson_parm_read(&pll->en);
+ if (enabled)
+ meson_clk_pll_disable(pll);
+
+ do {
+ /* run the same sequence provided by vlsi */
+ for (i = 0; i < pll->init_count; i++) {
+ val = init_regs[i].def;
+ writel(val, init_regs[i].reg);
+ if (init_regs[i].delay_us)
+ _udelay(init_regs[i].delay_us);
+ }
+
+ if (meson_clk_pll_wait_lock(pll))
+ printf("pcie pll did not lock, retrying %d\n", 10 - j);
+ else
+ break;
+ j--;
+ } while (j);
+
+ return 0;
+}
+
+void meson_secure_pll_disable(struct meson_clk_pll_data *pll)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(pll->smc_id, pll->secid_disable,
+ 0, 0, 0, 0, 0, 0, &res);
+}
+
+int meson_secure_pll_set_rate(struct meson_clk_pll_data *pll, unsigned long rate)
+{
+ struct arm_smccc_res res;
+ unsigned int enabled, m, n, ret = 0;
+ unsigned int od;
+
+ if (PARENT_RATE == 0 || rate == 0)
+ return -EINVAL;
+
+ ret = meson_clk_get_pll_settings(rate, &m, &n, pll, &od);
+ if (ret)
+ return ret;
+
+ enabled = meson_parm_read(&pll->en);
+ if (enabled)
+ meson_secure_pll_disable(pll);
+ /*Send m,n for arm64 */
+ arm_smccc_smc(pll->smc_id, pll->secid,
+ m, n, od, 0, 0, 0, &res);
+
+ return 0;
+}
+
+void meson_pll_report(struct meson_clk_pll_data *pll, unsigned int target, unsigned long res)
+{
+ if (((target-2) <= res) && (res <= (target+2)))
+ printf("%s PLL lock ok, target rate = %uM, clkmsr rate = %luM : Match\n", pll->name, target, res);
+ else
+ printf("%s PLL lock failed, target rate = %uM, clkmsr rate = %luM: Not Match\n", pll->name, target, res);
+}
+
+void meson_pll_test(struct meson_clk_pll_data *pll)
+{
+ int i;
+ unsigned long result;
+
+ for (i = 0; i < pll->def_cnt;i++) {
+ meson_pll_set_rate(pll, (unsigned long)pll->def_rate[i] * (unsigned long)1000000);
+
+ result = clk_util_clk_msr(pll->clkmsr_id);
+
+ meson_pll_report(pll, pll->def_rate[i], result);
+ }
+}
+
+void meson_secure_pll_test(struct meson_clk_pll_data *pll)
+{
+ int i;
+ unsigned long result;
+
+ for (i = 0; i < pll->def_cnt;i++) {
+ meson_secure_pll_set_rate(pll, (unsigned long)pll->def_rate[i] * (unsigned long)1000000);
+
+ result = clk_util_clk_msr(pll->clkmsr_id);
+ /* for sys_pll, clkmsr result is actual value/16 */
+ if (pll->clkmsr_div16_en)
+ result *= 16;
+
+ if (((pll->def_rate[i]-2*5) <= result) && (result <= (pll->def_rate[i]+2*5)))
+ printf("%s PLL lock ok, target rate = %u M, clkmsr rate = %lu: Match\n", pll->name, pll->def_rate[i], result);
+ else
+ printf("%s PLL lock failed, target rate = %u M, clkmsr rate = %lu: Not Match\n", pll->name, pll->def_rate[i], result);
+ }
+}
+
+void meson_pll_test_one(struct meson_clk_pll_data *pll)
+{
+ int i;
+ unsigned long result;
+
+ for (i = 0; i < pll->def_cnt;i++) {
+ meson_pll_set_one_rate(pll, (unsigned long)pll->def_rate[i] * (unsigned long)1000000);
+
+ result = clk_util_clk_msr(pll->clkmsr_id);
+
+ meson_pll_report(pll, pll->def_rate[i], result);
+ }
+}
+
+void meson_switch_cpu_clk(unsigned int smc_id, unsigned int secid, unsigned int flag)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(smc_id, secid,
+ 0x1 << 11, flag << 11,
+ 0, 0, 0, 0, &res);
+}
+
+void one_pll_test(struct meson_clk_pll_data **pll_list, int pll_cnt,
+ struct meson_clk_mpll_data **mpll_list, int mpll_cnt,
+ char *arg)
+{
+ struct meson_clk_pll_data *pll;
+ struct meson_clk_mpll_data *mpll;
+ unsigned int i, j;
+
+ for (i = 0; i < pll_cnt;i++) {
+ pll = pll_list[i];
+ if (0 == strcmp(pll->name, arg)) {
+ meson_pll_test(pll);
+ return;
+ }
+ }
+ for (j = 0; j < mpll_cnt;j++) {
+ mpll = mpll_list[j];
+ if (0 == strcmp(mpll->name, arg)) {
+ meson_mpll_test(mpll);
+ return;
+ }
+ }
+ if (i == pll_cnt && (j == mpll_cnt))
+ printf("The pll is not supported Or wrong pll name\n");
+}
diff --git a/arch/arm/mach-meson/clk-pll.h b/arch/arm/mach-meson/clk-pll.h
new file mode 100644
index 0000000..4cb6817
--- /dev/null
+++ b/arch/arm/mach-meson/clk-pll.h
@@ -0,0 +1,137 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __MESON_CLK_PLL_H
+#define __MESON_CLK_PLL_H
+
+#include <asm/io.h>
+#include <linux/bitops.h>
+#include <common.h>
+#include <linux/arm-smccc.h>
+//#include <linux/delay.h>
+#include <asm/arch/timer.h>
+
+#define PLL_ENABLE BIT(28)
+#define PLL_RESET BIT(29)
+#define PLL_LOCK BIT(31)
+#define SETPMASK(width, shift) GENMASK(shift + width - 1, shift)
+#define CLRPMASK(width, shift) (~SETPMASK(width, shift))
+
+#define PARM_GET(width, shift, reg) \
+ (((reg) & SETPMASK(width, shift)) >> (shift))
+#define PARM_SET(width, shift, reg, val) \
+ (((reg) & CLRPMASK(width, shift)) | (val << (shift)))
+#define MESON_PARM_APPLICABLE(p) (!!((p)->width))
+
+struct pll_params_table {
+ u16 m;
+ u16 n;
+ u16 od;
+};
+
+#define PLL_PARAMS(_m, _n, _od) \
+ { \
+ .m = (_m), \
+ .n = (_n), \
+ .od = (_od), \
+ }
+
+#define CLK_MESON_PLL_ROUND_CLOSEST BIT(0)
+
+struct parm {
+ uint32_t reg;
+ uint8_t shift;
+ uint8_t width;
+};
+
+struct reg_sequence {
+ unsigned int reg;
+ unsigned int def;
+ unsigned int mask;
+ unsigned int delay_us;
+};
+
+struct meson_clk_pll_data {
+ char name[16];
+ struct parm m;
+ struct parm n;
+ struct parm rst;
+ struct parm l;
+ struct parm frac;
+ struct parm od;
+ struct parm en;
+ const struct reg_sequence *init_regs;
+ unsigned int init_count;
+ unsigned int *def_rate;
+ unsigned int def_cnt;
+ const struct pll_params_table *table;
+ unsigned int smc_id;
+ u8 flags;
+ u8 secid_disable;
+ u8 secid;
+ u8 clkmsr_id;
+ u8 clkmsr_div16_en;
+};
+
+static inline unsigned int meson_parm_read(struct parm *p)
+{
+ unsigned int val;
+
+ val = readl(p->reg);
+
+ return PARM_GET(p->width, p->shift, val);
+}
+
+static inline void meson_parm_write(struct parm *p,
+ unsigned int val)
+{
+ unsigned int tmp;
+
+ tmp = readl(p->reg);
+ tmp &= CLRPMASK(p->width, p->shift);
+ tmp |= val << p->shift;
+ writel(tmp, p->reg);
+}
+
+/* mpll data structure */
+struct meson_clk_mpll_data {
+ char name[8];
+ struct parm sdm;
+ struct parm sdm_en;
+ struct parm n2;
+ struct parm ssen;
+ struct parm misc;
+ struct parm en;
+ unsigned int *def_rate;
+ unsigned int def_cnt;
+ const struct reg_sequence *init_regs;
+ unsigned int init_count;
+ u8 flags;
+ u8 clkmsr_id;
+};
+
+#define CLK_MESON_MPLL_ROUND_CLOSEST BIT(0)
+#define CLK_MESON_MPLL_SPREAD_SPECTRUM BIT(1)
+
+int meson_pll_set_rate(struct meson_clk_pll_data *pll, unsigned long rate);
+int meson_pll_set_one_rate(struct meson_clk_pll_data *pll, unsigned long rate);
+void meson_pll_test(struct meson_clk_pll_data *pll);
+void meson_pll_test_one(struct meson_clk_pll_data *pll);
+
+int meson_secure_pll_set_rate(struct meson_clk_pll_data *pll, unsigned long rate);
+void meson_secure_pll_test(struct meson_clk_pll_data *pll);
+void meson_secure_pll_disable(struct meson_clk_pll_data *pll);
+void meson_clk_pll_disable(struct meson_clk_pll_data *pll);
+
+void meson_switch_cpu_clk(unsigned int smc_id, unsigned int secid, unsigned int flag);
+
+int meson_mpll_set_rate(struct meson_clk_mpll_data *mpll,
+ unsigned long rate);
+void meson_mpll_test(struct meson_clk_mpll_data *pll);
+
+void one_pll_test(struct meson_clk_pll_data **pll, int pll_cnt,
+ struct meson_clk_mpll_data **mpll, int mpll_cnt, char *arg);
+
+#endif /* __MESON_CLK_PLL_H */
diff --git a/arch/arm/mach-meson/cpu_id.c b/arch/arm/mach-meson/cpu_id.c
new file mode 100644
index 0000000..74a0e6f
--- /dev/null
+++ b/arch/arm/mach-meson/cpu_id.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/io.h>
+
+/**
+ * TODO: This should be moved to a RO region of registers or SRAM that
+ * provides static system information that's needed across all software
+ *
+ * Chip ID copy to avoid unnecessary message exchange.
+ */
+chip_id_t aml_chip_id = { 0, { 0 } };
+
+cpu_id_t __attribute__((weak)) get_cpu_id(void)
+{
+ cpu_id_t cpu_id;
+ unsigned int cpu_id_reg = readl(CPU_ID_REG);
+
+ cpu_id.family_id = (cpu_id_reg >> 24) & (0xFF);
+ cpu_id.package_id = (cpu_id_reg >> 16) & (PACKAGE_ID_MASK);
+ cpu_id.chip_rev = (cpu_id_reg >> 8) & (0xFF);
+ cpu_id.layout_ver = (cpu_id_reg) & (0xF);
+ return cpu_id;
+}
+
+int get_chip_id(unsigned char *buff, unsigned int size)
+{
+ int rc = 0;
+
+ if (buff == NULL || size < 16)
+ return -1;
+
+ if (aml_chip_id.version == 0) {
+ /* Chip ID has not been fetched yet */
+ rc = __get_chip_id(&aml_chip_id.chipid[0], 16);
+
+ /* Mark version if chip ID is fetched successfully */
+ if (rc == 0)
+ aml_chip_id.version = 2;
+ }
+
+ memcpy(buff, &aml_chip_id.chipid[0], 16);
+ return rc;
+}
diff --git a/arch/arm/mach-meson/g12a/Makefile b/arch/arm/mach-meson/g12a/Makefile
index 2010fe3..0bd1de9 100644
--- a/arch/arm/mach-meson/g12a/Makefile
+++ b/arch/arm/mach-meson/g12a/Makefile
@@ -1,7 +1,7 @@
obj-y := sdio.o pinctrl_init.o
obj-y += bl31_apis.o
-obj-y += watchdog.o
+obj-y += cpu_reset.o
obj-y += timer.o
obj-y += mailbox.o
obj-y += gate_init.o
@@ -9,7 +9,6 @@
obj-$(CONFIG_CMD_PLLTEST) += pll.o
obj-$(CONFIG_CMD_AML_MTEST) += core.o
obj-$(CONFIG_AML_HDMITX) += hdmitx.o
-obj-y += cpu_id.o
-#obj-y += usb.o
+obj-y += usb.o
obj-$(CONFIG_AML_TSENSOR) += tsensor.o
obj-$(CONFIG_AML_OSCRING) += oscring.o
diff --git a/arch/arm/mach-meson/g12a/bl31_apis.c b/arch/arm/mach-meson/g12a/bl31_apis.c
index c8805d4..11ca2f0 100644
--- a/arch/arm/mach-meson/g12a/bl31_apis.c
+++ b/arch/arm/mach-meson/g12a/bl31_apis.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txlx/bl31_apis.c
- *
- * Copyright (C) 2014-2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
/*
@@ -26,7 +11,7 @@
#include <asm/arch/efuse.h>
#include <asm/cache.h>
#include <asm/arch/bl31_apis.h>
-#include <asm/arch/cpu_id.h>
+#include <amlogic/cpu_id.h>
#include <asm/arch/secure_apb.h>
static long sharemem_input_base;
@@ -42,6 +27,36 @@
return function_id;
}
+int32_t set_boot_params(const keymaster_boot_params *boot_params)
+{
+ const unsigned cmd = SET_BOOT_PARAMS;
+
+ if (!boot_params)
+ return -1;
+
+ if (!sharemem_input_base)
+ sharemem_input_base =
+ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE);
+
+ memcpy((void *)sharemem_input_base,
+ (const void *)boot_params, sizeof(keymaster_boot_params));
+
+ asm __volatile__("" : : : "memory");
+ register uint64_t x0 asm("x0") = cmd;
+ register uint64_t x1 asm("x1") = sizeof(keymaster_boot_params);
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1));
+ } while (0);
+
+ return (!x0)? -1: 0;
+}
+
#ifdef CONFIG_EFUSE
int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg)
{
@@ -68,7 +83,7 @@
if (arg->cmd == EFUSE_HAL_API_WRITE)
memcpy((void *)sharemem_input_base,
(const void *)arg->buffer_phy, size);
- asm __volatile__("" : : : "memory");
+ asm __volatile__("" : : : "memory");
register uint64_t x0 asm("x0") = cmd;
register uint64_t x1 asm("x1") = offset;
@@ -98,7 +113,7 @@
int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg)
{
- int32_t ret = 0;
+ int32_t ret;
unsigned cmd = 0;
if (arg->cmd == EFUSE_HAL_API_USER_MAX)
@@ -234,21 +249,6 @@
return reason;
}
-unsigned aml_get_dvfs_id(void)
-{
- unsigned dvfs_id;
- uint64_t ret;
-
- register uint64_t x0 asm("x0") = GET_DVFS_TABLE_INDEX;
- asm volatile(
- __asmeq("%0", "x0")
- "smc #0\n"
- :"+r"(x0));
- ret = x0;
- dvfs_id = (unsigned)(ret&0xffffffff);
- return dvfs_id;
-}
-
void set_viu_probe_enable(void)
{
register uint64_t x0 asm("x0") = VIU_PREOBE_EN;
@@ -423,3 +423,37 @@
return -1;
}
+
+int32_t get_avbkey_from_fip(uint8_t *buf, uint32_t buflen)
+{
+ const unsigned cmd = GET_AVBKEY_FROM_FIP;
+ uint32_t retlen = 0;
+ uint32_t ret = 0;
+
+ if (!buf)
+ return -1;
+
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ asm __volatile__("" : : : "memory");
+ register uint64_t x0 asm("x0") = cmd;
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0));
+ } while (0);
+
+ if (!x0)
+ ret = -1;
+ retlen = x0;
+
+ if (ret != -1 && buflen >= retlen)
+ memcpy(buf, (const void *)sharemem_output_base, retlen);
+
+ return ret;
+}
diff --git a/arch/arm/mach-meson/g12a/core.c b/arch/arm/mach-meson/g12a/core.c
index 73519bb..8640828 100644
--- a/arch/arm/mach-meson/g12a/core.c
+++ b/arch/arm/mach-meson/g12a/core.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/g12a/core.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <asm/arch/secure_apb.h>
#include <asm/types.h>
diff --git a/arch/arm/mach-meson/g12a/cpu_id.c b/arch/arm/mach-meson/g12a/cpu_id.c
deleted file mode 100644
index 8457866..0000000
--- a/arch/arm/mach-meson/g12a/cpu_id.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * arch/arm/cpu/armv8/cpu_id.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <asm/arch/cpu_id.h>
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/io.h>
-
-/**
- * TODO: This should be moved to a RO region of registers or SRAM that
- * provides static system information that's needed across all software
- *
- * Chip ID copy to avoid unnecessary message exchange.
- */
-chip_id_t aml_chip_id = { 0, { 0 } };
-
-cpu_id_t get_cpu_id(void)
-{
- cpu_id_t cpu_id;
- unsigned int cpu_id_reg = readl(P_AO_SEC_SD_CFG8);
-
- memset(&cpu_id, 0, sizeof(cpu_id_t));
- cpu_id.family_id = (cpu_id_reg >> 24) & (0XFF);
- cpu_id.package_id = (cpu_id_reg >> 16) & (0XF0);
- cpu_id.chip_rev = (cpu_id_reg >> 8) & (0XFF);
- cpu_id.layout_ver = (cpu_id_reg) & (0XF);
- return cpu_id;
-}
-
-int get_chip_id(unsigned char *buff, unsigned int size)
-{
- int rc = 0;
-
- if (buff == NULL || size < 16)
- return -1;
-
- if (aml_chip_id.version == 0) {
- /* Chip ID has not been fetched yet */
- rc = __get_chip_id(&aml_chip_id.chipid[0], 16);
-
- /* Mark version if chip ID is fetched successfully */
- if (rc == 0)
- aml_chip_id.version = 2;
- }
-
- memcpy(buff, &aml_chip_id.chipid[0], 16);
- return rc;
-}
diff --git a/arch/arm/mach-meson/g12a/cpu_reset.c b/arch/arm/mach-meson/g12a/cpu_reset.c
new file mode 100644
index 0000000..08852ec
--- /dev/null
+++ b/arch/arm/mach-meson/g12a/cpu_reset.c
@@ -0,0 +1,39 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/types.h>
+#include <asm/arch/romboot.h>
+#include <asm/arch/cpu_reset.h>
+#include <asm/arch/io.h>
+#include <asm/arch/timer.h>
+#include <wdt.h>
+#include <dm.h>
+
+void reset_system(void)
+{
+ struct udevice *wdt;
+ int ret;
+
+#ifdef CONFIG_USB_DEVICE_V2
+ *P_RESET1_REGISTER |= (1<<17);
+ mdelay(200);
+#endif
+ _udelay(10000); //wait print
+
+ ret = uclass_get_device_by_name(UCLASS_WDT, "watchdog", &wdt);
+ if (ret) {
+ printf("failed to reset system because can't get wdt device\n");
+ return;
+ }
+
+ wdt_start(wdt, 0, 0);
+ while (1);
+}
+
+/* uboot reset interface */
+void reset_cpu(unsigned long flag){
+ reset_system();
+}
diff --git a/arch/arm/mach-meson/g12a/firmware/acs/Makefile b/arch/arm/mach-meson/g12a/firmware/acs/Makefile
old mode 100755
new mode 100644
index 4a2fb2c..47daf72
--- a/arch/arm/mach-meson/g12a/firmware/acs/Makefile
+++ b/arch/arm/mach-meson/g12a/firmware/acs/Makefile
@@ -32,6 +32,8 @@
# Default values for build configurations
#
+export CROSS_COMPILE=/opt/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-
+
include $(buildsrc)/config.mk
include $(buildtree)/include/autoconf.mk
include $(buildtree)/.config
@@ -118,22 +120,6 @@
@echo "KBUILD_OUTPUT: ${KBUILD_OUTPUT}"
@echo "Building ${BOARDDIR}/acs.bin"
-# ENABLE_DDR_LOGGING is defined in fip/mk_script.sh:
-# 1: enable DDR tuning log; 0: disable DDR tuning log
-ifeq (${ENABLE_DDR_LOGGING},1)
-CFLAGS += -DCONFIG_DDR_LOGS_ENABLED=1
-else
-CFLAGS += -DCONFIG_DDR_LOGS_ENABLED=0
-endif
-
-# ENABLE_BFT_TIME_SAVING is defined in fip/mk_script.sh:
-# 1: enable BFT time saving; 0: disable BFT time saving
-ifeq (${ENABLE_BFT_TIME_SAVING},1)
-CFLAGS += -DCONFIG_BFT_TIME_SAVING_ENABLED=1
-else
-CFLAGS += -DCONFIG_BFT_TIME_SAVING_ENABLED=0
-endif
-
#include plat/${PLAT}/platform.mk
#ifdef BL2_SOURCES
NEED_BL2 := yes
diff --git a/arch/arm/mach-meson/g12a/firmware/acs/acs.c b/arch/arm/mach-meson/g12a/firmware/acs/acs.c
index 66bd216..9d1ab36 100644
--- a/arch/arm/mach-meson/g12a/firmware/acs/acs.c
+++ b/arch/arm/mach-meson/g12a/firmware/acs/acs.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/firmware/acs/acs.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <asm/arch/acs.h>
#include <asm/arch/timing.h>
@@ -59,4 +43,7 @@
.rsv_set_version= 1,
.rsv_set_length = 0,
.rsv_set_addr = 0,
+ .board_id = {0,},
+ .ddr_struct_size = {0,},
+ .ddr_struct_org_size = sizeof(ddr_set_t),
};
diff --git a/arch/arm/mach-meson/g12a/firmware/acs/acs.ld.S b/arch/arm/mach-meson/g12a/firmware/acs/acs.ld.S
index c818b1a..4a952c7 100644
--- a/arch/arm/mach-meson/g12a/firmware/acs/acs.ld.S
+++ b/arch/arm/mach-meson/g12a/firmware/acs/acs.ld.S
@@ -12,7 +12,8 @@
*acs_entry.o(.text*)
*(.text*)
*(.data*)
+ *(.ddr_settings*)
}
- ASSERT(. <= 0xFFFB0000, "timing image has exceeded its limit.")
+ //ASSERT(. <= 0xFFFB0000, "timing image has exceeded its limit.")
}
diff --git a/arch/arm/mach-meson/g12a/firmware/acs/acs.mk b/arch/arm/mach-meson/g12a/firmware/acs/acs.mk
index 996209b..883a9df 100644
--- a/arch/arm/mach-meson/g12a/firmware/acs/acs.mk
+++ b/arch/arm/mach-meson/g12a/firmware/acs/acs.mk
@@ -1,3 +1,9 @@
-SOURCES += acs.c \
- acs_entry.S
+SOURCES += acs_entry.S
+
+ifdef CONFIG_MDUMP_COMPRESS
+SOURCES += ramdump.c
+endif
+
+SOURCES += acs.c
+
LINKERFILE_T := acs.ld.S
diff --git a/arch/arm/mach-meson/g12a/firmware/acs/acs_entry.S b/arch/arm/mach-meson/g12a/firmware/acs/acs_entry.S
index 2d69287..feca813 100644
--- a/arch/arm/mach-meson/g12a/firmware/acs/acs_entry.S
+++ b/arch/arm/mach-meson/g12a/firmware/acs/acs_entry.S
@@ -4,4 +4,11 @@
acs_entry:
.word 0
.word __acs_set
+#ifdef CONFIG_MDUMP_COMPRESS
+ .word __ramdump_data
+ .word __ddr_setting
+#else
+ .word 0x0
+ .word __ddr_setting
+#endif
diff --git a/arch/arm/mach-meson/g12a/firmware/scp_task/Makefile b/arch/arm/mach-meson/g12a/firmware/scp_task/Makefile
index d71bad8..ecc4671 100644
--- a/arch/arm/mach-meson/g12a/firmware/scp_task/Makefile
+++ b/arch/arm/mach-meson/g12a/firmware/scp_task/Makefile
@@ -7,12 +7,12 @@
# Select ARMv7-m bare-metal toolchain
CROSS_COMPILE=arm-none-eabi-
-ASM=$(CROSS_COMPILE_T32)as
-CC=$(CROSS_COMPILE_T32)gcc
-CPP=$(CROSS_COMPILE_T32)cpp
-LD=$(CROSS_COMPILE_T32)ld
-OBJCOPY=$(CROSS_COMPILE_T32)objcopy
-OBJDUMP=$(CROSS_COMPILE_T32)objdump
+ASM=$(CROSS_COMPILE)as
+CC=$(CROSS_COMPILE)gcc
+CPP=$(CROSS_COMPILE)cpp
+LD=$(CROSS_COMPILE)ld
+OBJCOPY=$(CROSS_COMPILE)objcopy
+OBJDUMP=$(CROSS_COMPILE)objdump
ARM_ARCH=armv7-m
ARM_CPU=cortex-m3
diff --git a/arch/arm/mach-meson/g12a/firmware/scp_task/aml_led.c b/arch/arm/mach-meson/g12a/firmware/scp_task/aml_led.c
index e899729..5570001 100644
--- a/arch/arm/mach-meson/g12a/firmware/scp_task/aml_led.c
+++ b/arch/arm/mach-meson/g12a/firmware/scp_task/aml_led.c
@@ -1,9 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * uboot/aml_led.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <amlogic/aml_led.h>
diff --git a/arch/arm/mach-meson/g12a/firmware/scp_task/cec_tx_reg.h b/arch/arm/mach-meson/g12a/firmware/scp_task/cec_tx_reg.h
index 9360d47..2382604 100644
--- a/arch/arm/mach-meson/g12a/firmware/scp_task/cec_tx_reg.h
+++ b/arch/arm/mach-meson/g12a/firmware/scp_task/cec_tx_reg.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/cec_tx_reg.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _CEC_TX_REG_H
#define _CEC_TX_REG_H
diff --git a/arch/arm/mach-meson/g12a/firmware/scp_task/config.h b/arch/arm/mach-meson/g12a/firmware/scp_task/config.h
index de0eae6..2d13a9a 100644
--- a/arch/arm/mach-meson/g12a/firmware/scp_task/config.h
+++ b/arch/arm/mach-meson/g12a/firmware/scp_task/config.h
@@ -1,29 +1,13 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/config.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _CONFIG_H_
#define _CONFIG_H_
-#define CONFIG_RAM_BASE (0x10000000 + 40 * 1024)
-#define CONFIG_RAM_SIZE (13 * 1024)
+#define CONFIG_RAM_BASE (0x10000000 + 46 * 1024)
+#define CONFIG_RAM_SIZE (15 * 1024)
#define CONFIG_RAM_END (CONFIG_RAM_BASE+CONFIG_RAM_SIZE)
#define CONFIG_TASK_STACK_SIZE 512
@@ -36,13 +20,13 @@
* after BL301 enable wakeup, bl30 store irq no. in share memory
*/
#define WAKEUP_SRC_IRQ_ADDR_BASE (CONFIG_RAM_END - 128)
-#define SECURE_TASK_SHARE_MEM_BASE 0x1000D400
-#define SECURE_TASK_RESPONSE_MEM_BASE 0x1000D600
-#define SECURE_TASK_RESPONSE_WAKEUP_EN 0x1000D7FC
-#define HIGH_TASK_SHARE_MEM_BASE 0x1000D800
-#define HIGH_TASK_RESPONSE_MEM_BASE 0x1000DA00
-#define LOW_TASK_SHARE_MEM_BASE 0x1000DC00
-#define LOW_TASK_RESPONSE_MEM_BASE 0x1000DE00
+#define SECURE_TASK_SHARE_MEM_BASE CONFIG_RAM_END
+#define SECURE_TASK_RESPONSE_MEM_BASE (CONFIG_RAM_END + 0x200)
+#define SECURE_TASK_RESPONSE_WAKEUP_EN (CONFIG_RAM_END + 0x400 - 4)
+#define HIGH_TASK_SHARE_MEM_BASE (CONFIG_RAM_END + 0x400)
+#define HIGH_TASK_RESPONSE_MEM_BASE (CONFIG_RAM_END + 0x600)
+#define LOW_TASK_SHARE_MEM_BASE (CONFIG_RAM_END + 0x800)
+#define LOW_TASK_RESPONSE_MEM_BASE (CONFIG_RAM_END + 0xA00)
/*
* BL30/BL301 share memory command list
*/
diff --git a/arch/arm/mach-meson/g12a/firmware/scp_task/data.h b/arch/arm/mach-meson/g12a/firmware/scp_task/data.h
index 5c67a97..f8cb67f 100644
--- a/arch/arm/mach-meson/g12a/firmware/scp_task/data.h
+++ b/arch/arm/mach-meson/g12a/firmware/scp_task/data.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/data.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include "config.h"
diff --git a/arch/arm/mach-meson/g12a/firmware/scp_task/gpio.h b/arch/arm/mach-meson/g12a/firmware/scp_task/gpio.h
index 082f0ad..865d67f 100644
--- a/arch/arm/mach-meson/g12a/firmware/scp_task/gpio.h
+++ b/arch/arm/mach-meson/g12a/firmware/scp_task/gpio.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/gpio-gxbb.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __ARCH_GXBB_GPIO_H__
#define __ARCH_GXBB_GPIO_H__
diff --git a/arch/arm/mach-meson/g12a/firmware/scp_task/hdmi_cec_arc.c b/arch/arm/mach-meson/g12a/firmware/scp_task/hdmi_cec_arc.c
index ba7f42f..88f7559 100644
--- a/arch/arm/mach-meson/g12a/firmware/scp_task/hdmi_cec_arc.c
+++ b/arch/arm/mach-meson/g12a/firmware/scp_task/hdmi_cec_arc.c
@@ -1,7 +1,8 @@
-/**************************************************
- * HDMI CEC uboot code *
- * *
- **************************************************/
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifdef CONFIG_CEC_WAKEUP
#include "secure_apb.h"
#include "cec_tx_reg.h"
diff --git a/arch/arm/mach-meson/g12a/firmware/scp_task/lib/delay.c b/arch/arm/mach-meson/g12a/firmware/scp_task/lib/delay.c
index cd15225..3fb9915 100644
--- a/arch/arm/mach-meson/g12a/firmware/scp_task/lib/delay.c
+++ b/arch/arm/mach-meson/g12a/firmware/scp_task/lib/delay.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/lib/delay.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#define P_AO_TIMER_E (*((volatile unsigned *)(0xff800000 + (0xf9 << 2))))
unsigned int get_time(void)
diff --git a/arch/arm/mach-meson/g12a/firmware/scp_task/lib/string.c b/arch/arm/mach-meson/g12a/firmware/scp_task/lib/string.c
index 2e551f4..fa270c0 100644
--- a/arch/arm/mach-meson/g12a/firmware/scp_task/lib/string.c
+++ b/arch/arm/mach-meson/g12a/firmware/scp_task/lib/string.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/lib/string.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
void *memcpy(void *dest, const void *src, unsigned int count)
{
diff --git a/arch/arm/mach-meson/g12a/firmware/scp_task/registers.h b/arch/arm/mach-meson/g12a/firmware/scp_task/registers.h
index 0ad0fc7..ba8d224 100644
--- a/arch/arm/mach-meson/g12a/firmware/scp_task/registers.h
+++ b/arch/arm/mach-meson/g12a/firmware/scp_task/registers.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/registers.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _SCP_REGISTER_DEFINES_
#define _SCP_REGISTER_DEFINES_
diff --git a/arch/arm/mach-meson/g12a/firmware/scp_task/scp_adc.c b/arch/arm/mach-meson/g12a/firmware/scp_task/scp_adc.c
index d5f44bd..fadb302 100644
--- a/arch/arm/mach-meson/g12a/firmware/scp_task/scp_adc.c
+++ b/arch/arm/mach-meson/g12a/firmware/scp_task/scp_adc.c
@@ -1,3 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#define MESON_CPU_MAJOR_ID_GXBB 0x1F
#define MESON_CPU_MAJOR_ID_GXTVBB 0x20
#define MESON_CPU_MAJOR_ID_GXL 0x21
diff --git a/arch/arm/mach-meson/g12a/firmware/scp_task/scp_remote.c b/arch/arm/mach-meson/g12a/firmware/scp_task/scp_remote.c
index c52eb5a..aafaa69 100644
--- a/arch/arm/mach-meson/g12a/firmware/scp_task/scp_remote.c
+++ b/arch/arm/mach-meson/g12a/firmware/scp_task/scp_remote.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/scp_remote.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <config.h>
#include "config.h"
@@ -284,6 +268,10 @@
static int init_remote(void)
{
return 0;
+ uart_put_hex(readl(AO_IR_DEC_STATUS), 32);
+ uart_put_hex(readl(AO_IR_DEC_FRAME), 32);
+ init_custom_trigger();
+ //return 0;
}
/*can be called in pwr_ctrl.c*/
diff --git a/arch/arm/mach-meson/g12a/firmware/scp_task/secure_apb.h b/arch/arm/mach-meson/g12a/firmware/scp_task/secure_apb.h
index 67f88be..a5fbfbc 100644
--- a/arch/arm/mach-meson/g12a/firmware/scp_task/secure_apb.h
+++ b/arch/arm/mach-meson/g12a/firmware/scp_task/secure_apb.h
@@ -1,15 +1,8 @@
-// ----------------------------------------------------------------------
-// This file is automatically generated from the script:
-//
-// ./create_headers_from_secure_apb4_h.pl
-//
-// and was applied to the file
-//
-// ./secure_apb4_ee.h ./ao_rti_reg.h
-//
-// DO NOT EDIT!!!!!
-// ----------------------------------------------------------------------
-//
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifdef SECURE_APB_H
#else
#define SECURE_APB_H
diff --git a/arch/arm/mach-meson/g12a/firmware/scp_task/suspend.c b/arch/arm/mach-meson/g12a/firmware/scp_task/suspend.c
index 7274ada..d9962dd 100644
--- a/arch/arm/mach-meson/g12a/firmware/scp_task/suspend.c
+++ b/arch/arm/mach-meson/g12a/firmware/scp_task/suspend.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/suspend.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include "config.h"
#include "registers.h"
diff --git a/arch/arm/mach-meson/g12a/firmware/scp_task/suspend.h b/arch/arm/mach-meson/g12a/firmware/scp_task/suspend.h
index f207f22..dc3506c 100644
--- a/arch/arm/mach-meson/g12a/firmware/scp_task/suspend.h
+++ b/arch/arm/mach-meson/g12a/firmware/scp_task/suspend.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/suspend.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __SCP_SUSPEND_H_
#define __SCP_SUSPEND_H_
diff --git a/arch/arm/mach-meson/g12a/firmware/scp_task/task_apis.h b/arch/arm/mach-meson/g12a/firmware/scp_task/task_apis.h
index 31ab63f..4bb9274 100644
--- a/arch/arm/mach-meson/g12a/firmware/scp_task/task_apis.h
+++ b/arch/arm/mach-meson/g12a/firmware/scp_task/task_apis.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/task_apis.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __TASK_APIS_H_
#define __TASK_APIS_H_
diff --git a/arch/arm/mach-meson/g12a/firmware/scp_task/uart.c b/arch/arm/mach-meson/g12a/firmware/scp_task/uart.c
index a3dc56f..0ac32c8 100644
--- a/arch/arm/mach-meson/g12a/firmware/scp_task/uart.c
+++ b/arch/arm/mach-meson/g12a/firmware/scp_task/uart.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/uart.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include "registers.h"
#include <stdint.h>
diff --git a/arch/arm/mach-meson/g12a/firmware/scp_task/user_task.c b/arch/arm/mach-meson/g12a/firmware/scp_task/user_task.c
index 088a083..6984a92 100644
--- a/arch/arm/mach-meson/g12a/firmware/scp_task/user_task.c
+++ b/arch/arm/mach-meson/g12a/firmware/scp_task/user_task.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/user_task.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include "config.h"
#include "data.h"
diff --git a/arch/arm/mach-meson/g12a/gate_init.c b/arch/arm/mach-meson/g12a/gate_init.c
index 7390665..31629f6 100644
--- a/arch/arm/mach-meson/g12a/gate_init.c
+++ b/arch/arm/mach-meson/g12a/gate_init.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/gate_init.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include "power_gate.h"
diff --git a/arch/arm/mach-meson/g12a/gpio.c b/arch/arm/mach-meson/g12a/gpio.c
index 130f37f..7332773 100644
--- a/arch/arm/mach-meson/g12a/gpio.c
+++ b/arch/arm/mach-meson/g12a/gpio.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/g12a/gpio.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <common.h>
#include <dm.h>
diff --git a/arch/arm/mach-meson/g12a/hdmitx.c b/arch/arm/mach-meson/g12a/hdmitx.c
index b9ca3d9..5292c87 100644
--- a/arch/arm/mach-meson/g12a/hdmitx.c
+++ b/arch/arm/mach-meson/g12a/hdmitx.c
@@ -1,22 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/mach-meson/g12a/hdmitx.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <common.h>
#include <asm/arch/io.h>
diff --git a/arch/arm/mach-meson/g12a/mailbox.c b/arch/arm/mach-meson/g12a/mailbox.c
index b1e860f..2c99d81 100644
--- a/arch/arm/mach-meson/g12a/mailbox.c
+++ b/arch/arm/mach-meson/g12a/mailbox.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/mailbox.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <config.h>
#include <common.h>
diff --git a/arch/arm/mach-meson/g12a/oscring.c b/arch/arm/mach-meson/g12a/oscring.c
index 51aaeca..5a18f31 100644
--- a/arch/arm/mach-meson/g12a/oscring.c
+++ b/arch/arm/mach-meson/g12a/oscring.c
@@ -1,3 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include <config.h>
#include <common.h>
#include <asm/arch/io.h>
@@ -5,7 +10,7 @@
#include <asm/arch/clock.h>
#include <asm/arch/mailbox.h>
#include <asm/arch/oscring.h>
-#include <asm/arch/cpu_id.h>
+#include <amlogic/cpu_id.h>
void ring_powerinit(void)
{
@@ -95,7 +100,7 @@
}
printf("osc efuse info:\n");
- for (i = 0; i <= 11; i++)
+ for (i = 0; i < sizeof(efuseinfo) / sizeof(uint8_t); i++)
printf("0x%x, ", efuseinfo[i]);
printf("\n");
diff --git a/arch/arm/mach-meson/g12a/pinctrl_init.c b/arch/arm/mach-meson/g12a/pinctrl_init.c
index 5c40be1..829ce28 100644
--- a/arch/arm/mach-meson/g12a/pinctrl_init.c
+++ b/arch/arm/mach-meson/g12a/pinctrl_init.c
@@ -1,8 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
- * Author: Xingyu Chen <xingyu.chen@amlogic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
diff --git a/arch/arm/mach-meson/g12a/pll.c b/arch/arm/mach-meson/g12a/pll.c
index f256a90..68a1941 100644
--- a/arch/arm/mach-meson/g12a/pll.c
+++ b/arch/arm/mach-meson/g12a/pll.c
@@ -1,15 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * rev history:
- * 2017.04.06 structure done
- *
- *
- *
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
#include <command.h>
-#include <asm/cpu_id.h>
+#include <amlogic/cpu_id.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
diff --git a/arch/arm/mach-meson/g12a/power_cal.c b/arch/arm/mach-meson/g12a/power_cal.c
index d4accfc..e4f9c53 100644
--- a/arch/arm/mach-meson/g12a/power_cal.c
+++ b/arch/arm/mach-meson/g12a/power_cal.c
@@ -1,28 +1,12 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/xx/power_cal.c
- *
- * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <common.h>
#include <asm/arch/secure_apb.h>
#include <asm/arch/io.h>
-#include <asm/arch/saradc.h>
+#include <amlogic/saradc.h>
#include <asm/arch/mailbox.h>
#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2))))
diff --git a/arch/arm/mach-meson/g12a/power_gate.h b/arch/arm/mach-meson/g12a/power_gate.h
index 33f42bf..9ca1a9d 100644
--- a/arch/arm/mach-meson/g12a/power_gate.h
+++ b/arch/arm/mach-meson/g12a/power_gate.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/cpu/armv8/txl/power_gate.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __POWER_MGR_HEADER_
#define __POWER_MGR_HEADER_
diff --git a/arch/arm/mach-meson/g12a/sdio.c b/arch/arm/mach-meson/g12a/sdio.c
index 000d641..93dcc8f 100644
--- a/arch/arm/mach-meson/g12a/sdio.c
+++ b/arch/arm/mach-meson/g12a/sdio.c
@@ -1,29 +1,13 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/sdio.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <config.h>
#include <asm/arch/io.h>
#include <asm/arch/cpu_sdio.h>
#include <asm/arch/secure_apb.h>
-#include <asm/arch/cpu_id.h>
+#include <amlogic/cpu_id.h>
#include <common.h>
void cpu_sd_emmc_pwr_prepare(unsigned port)
diff --git a/arch/arm/mach-meson/g12a/timer.c b/arch/arm/mach-meson/g12a/timer.c
index 1687bb9..80c17bb 100644
--- a/arch/arm/mach-meson/g12a/timer.c
+++ b/arch/arm/mach-meson/g12a/timer.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/timer.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <asm/arch/secure_apb.h>
#include <asm/arch/timer.h>
diff --git a/arch/arm/mach-meson/g12a/tsensor.c b/arch/arm/mach-meson/g12a/tsensor.c
index c43db95..42bf639 100644
--- a/arch/arm/mach-meson/g12a/tsensor.c
+++ b/arch/arm/mach-meson/g12a/tsensor.c
@@ -1,3 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include <common.h>
#include <asm/io.h>
#include <command.h>
@@ -46,7 +51,7 @@
udelay(50);
value_ts = readl(TS_PLL_STAT0) & 0xffff;
}
- for (i = 0; i <= T_AVG_NUM; i ++) {
+ for (i = 0; i < T_READ_NUM; i ++) {
udelay(T_DLY_TIME);
value_ts = readl(TS_PLL_STAT0) & 0xffff;
if ((value_ts >= T_VALUE_MIN) &&
@@ -55,7 +60,12 @@
cnt ++;
}
}
- value_ts = value_all_ts / cnt;
+ if (cnt) {
+ value_ts = value_all_ts / cnt;
+ } else {
+ value_ts = 0;
+ printf("tsensor read temp cnt is zero");
+ }
printf("pll tsensor avg: 0x%x, u_efuse: 0x%x\n", value_ts, u_efuse);
if (value_ts == 0) {
printf("tsensor read temp is zero\n");
@@ -81,7 +91,7 @@
udelay(50);
value_ts = readl(TS_DDR_STAT0) & 0xffff;
}
- for (i = 0; i <= T_AVG_NUM; i ++) {
+ for (i = 0; i < T_READ_NUM; i ++) {
udelay(T_DLY_TIME);
value_ts = readl(TS_DDR_STAT0) & 0xffff;
if ((value_ts >= T_VALUE_MIN) &&
@@ -90,7 +100,12 @@
cnt ++;
}
}
- value_ts = value_all_ts / cnt;
+ if (cnt) {
+ value_ts = value_all_ts / cnt;
+ } else {
+ value_ts = 0;
+ printf("tsensor read temp cnt is zero");
+ }
printf("ddr tsensor avg: 0x%x, u_efuse: 0x%x\n", value_ts, u_efuse);
if (value_ts == 0) {
printf("tsensor read temp is zero\n");
diff --git a/arch/arm/mach-meson/g12a/usb.c b/arch/arm/mach-meson/g12a/usb.c
new file mode 100644
index 0000000..7832de4
--- /dev/null
+++ b/arch/arm/mach-meson/g12a/usb.c
@@ -0,0 +1,454 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <power/regulator.h>
+#include <clk.h>
+#include <asm/arch/usb.h>
+#include <amlogic/cpu_id.h>
+
+#include <linux/compat.h>
+#include <linux/ioport.h>
+#include <asm-generic/gpio.h>
+
+#define U2_CTRL_SLEEP_SHIFT 17
+#define U2_HHI_MEM_PD_MASK 0x3
+#define U2_HHI_MEM_PD_SHIFT 30
+#define U2_CTRL_ISO_SHIFT 17
+#define PHY20_RESET_LEVEL_BIT 16
+#define PHY21_RESET_LEVEL_BIT 17
+#define USB_RESET_BIT 2
+
+#define USB2_PHY_PLL_OFFSET_40 (0x09400414)
+#define USB2_PHY_PLL_OFFSET_44 (0x927E0000)
+#define USB2_PHY_PLL_OFFSET_48 (0xac5f49e5)
+#define USB2_SM1_PHY_PLL_OFFSET_48 (0xac5f69e5)
+
+#define USB2_PHY_PLL_OFFSET_10 (0x80000fff)
+#define USB2_PHY_PLL_OFFSET_34 (0x78000)
+
+#define USB2_PHY_PLL_OFFSET_38_CLEAR (0)
+#define USB2_PHY_PLL_OFFSET_38_SET (0xe0004)
+#define USB2_PHY_PLL_OFFSET_50 (0xfe18)
+#define USB2_PHY_PLL_OFFSET_54 (0x2a)
+
+#define TUNING_DISCONNECT_THRESHOLD 0x34
+
+static int Rev_flag = 0;
+
+static struct phy usb_phys[2];
+
+/*Rev_flag == 0XB, g12b and revB, tl1 */
+/*Rev_flag == 1, sm1 */
+static void phy_aml_usb2_check_rev (void)
+{
+ cpu_id_t cpu_id = get_cpu_id();
+
+ if (cpu_id.family_id == MESON_CPU_MAJOR_ID_G12B) {
+ if (cpu_id.chip_rev == 0xb)
+ Rev_flag = 0xb;
+ else
+ Rev_flag = 0;
+ } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SM1) {
+ Rev_flag = MESON_CPU_MAJOR_ID_SM1;
+ } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_A1) {
+ Rev_flag = MESON_CPU_MAJOR_ID_A1;
+ } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_C1) {
+ Rev_flag = MESON_CPU_MAJOR_ID_C1;
+ }
+ return;
+}
+
+static int phy_aml_usb2_get_rev_type (void)
+{
+ int val = 0;
+
+ switch (Rev_flag) {
+ case MESON_CPU_MAJOR_ID_SM1:
+ case MESON_CPU_MAJOR_ID_A1:
+ case MESON_CPU_MAJOR_ID_C1:
+ case 0xb:
+ val = 1;
+ break;
+ default:
+ printk("amlogic usb phy need tuning\n");
+ val = 0;
+ break;
+ }
+
+ return val;
+}
+
+int get_usbphy_baseinfo(struct phy *usb_phys)
+{
+ struct udevice *bus;
+ struct uclass *uc;
+ int ret, i;
+ int count;
+
+ if (usb_phys[0].dev && usb_phys[1].dev)
+ return 0;
+
+ ret = uclass_get(UCLASS_USB, &uc);
+ if (ret)
+ return ret;
+ uclass_foreach_dev(bus, uc) {
+ debug("bus->name=%s, bus->driver->name =%s\n",
+ bus->name, bus->driver->name);
+ count = dev_count_phandle_with_args(bus, "phys", "#phy-cells");
+ debug("usb phy count=%u\n", count);
+ if (count <= 0)
+ return count;
+ for (i = 0; i < count; i++) {
+ ret = generic_phy_get_by_index(bus, i, &usb_phys[i]);
+ if (ret && ret != -ENOENT) {
+ pr_err("Failed to get USB PHY%d for %s\n",
+ i, bus->name);
+ return ret;
+ }
+ ret = generic_phy_getinfo(&usb_phys[i]);
+ if (ret)
+ return ret;
+ }
+ }
+ return 0;
+}
+
+int usb_aml_detect_operation(int argc, char * const argv[])
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ struct phy_aml_usb3_priv *usb3_priv;
+ int ret;
+
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ usb3_priv = dev_get_priv(usb_phys[1].dev);
+
+ if (usb3_priv) {
+ printf("priv->usb3 port num = %d, config addr=0x%08x\n",
+ usb3_priv->usb3_port_num, usb3_priv->base_addr);
+ }
+ if (usb2_priv) {
+ printf("usb2 phy: config addr = 0x%08x, reset addr=0x%08x\n",
+ usb2_priv->base_addr, usb2_priv->reset_addr);
+
+ printf("usb2 phy: portnum=%d, phy-addr1= 0x%08x, phy-addr2= 0x%08x\n",
+ usb2_priv->u2_port_num, usb2_priv->usb_phy2_pll_base_addr[0],
+ usb2_priv->usb_phy2_pll_base_addr[1]);
+ printf("dwc2_a base addr: 0x%08x\n", usb2_priv->dwc2_a_addr);
+ }
+ phy_aml_usb2_check_rev();
+ printf("PHY version is 0x%02x\n", Rev_flag);
+ return 0;
+}
+
+static void usb_set_power_domain (void)
+{
+ int rev_type;
+
+ rev_type = phy_aml_usb2_get_rev_type();
+ if (rev_type ) {
+ writel((readl(P_AO_RTI_GEN_PWR_SLEEP0) & (~(0x1 << U2_CTRL_SLEEP_SHIFT))),
+ P_AO_RTI_GEN_PWR_SLEEP0);
+ writel((readl(P_AO_RTI_GEN_PWR_ISO0) & (~(0x1 << U2_CTRL_ISO_SHIFT))),
+ P_AO_RTI_GEN_PWR_ISO0);
+ writel((readl(P_HHI_MEM_PD_REG0)
+ & (~(U2_HHI_MEM_PD_MASK << U2_HHI_MEM_PD_SHIFT))), P_HHI_MEM_PD_REG0);
+ }
+
+ return;
+}
+
+static void set_pll_Calibration_default(uint32_t phy2_pll_base)
+{
+ u32 tmp;
+
+ tmp = (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x8));
+ tmp &= 0xfff;
+ tmp |= (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10));
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10))
+ = tmp;
+}
+
+void usb_reset(unsigned int reset_addr, int bit){
+ *(volatile unsigned int *)(unsigned long)reset_addr = (1 << bit);
+}
+
+void set_usb_pll(uint32_t phy2_pll_base)
+{
+ unsigned int pll_offset_48;
+ int hardware_rev;
+
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))
+ = (USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET | USB_PHY2_ENABLE);
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44)) =
+ USB2_PHY_PLL_OFFSET_44;
+ hardware_rev = phy_aml_usb2_get_rev_type();
+ if (hardware_rev)
+ pll_offset_48 = USB2_SM1_PHY_PLL_OFFSET_48;
+ else
+ pll_offset_48 = USB2_PHY_PLL_OFFSET_48;
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x48)) =
+ pll_offset_48;
+ udelay(100);
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x40))
+ = (((USB2_PHY_PLL_OFFSET_40) | (USB_PHY2_ENABLE))
+ & (~(USB_PHY2_RESET)));
+ if (hardware_rev) {
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50))
+ = USB2_PHY_PLL_OFFSET_50;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x54))
+ = USB2_PHY_PLL_OFFSET_54;
+ set_pll_Calibration_default(phy2_pll_base);
+ } else {
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50))
+ = USB2_PHY_PLL_OFFSET_50;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10))
+ = USB2_PHY_PLL_OFFSET_10;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x38))
+ = USB2_PHY_PLL_OFFSET_38_CLEAR;
+ }
+
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0xc)) =
+ TUNING_DISCONNECT_THRESHOLD;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x34))
+ = USB2_PHY_PLL_OFFSET_34;
+ debug("tuning_disconnect_threshold=0x%x\n", TUNING_DISCONNECT_THRESHOLD);
+}
+
+int usb_save_phy_dev (unsigned int number, struct phy *phy)
+{
+ usb_phys[number].dev = phy->dev;
+ usb_phys[number].id = phy->id;
+ return 0;
+}
+
+int usb2_phy_init (struct phy *phy) {
+ struct phy_aml_usb2_priv *priv = dev_get_priv(phy->dev);
+ struct u2p_aml_regs *u2p_aml_reg;
+ u2p_r0_t dev_u2p_r0;
+ u2p_r1_t dev_u2p_r1;
+ int i,cnt;
+
+ usb_save_phy_dev(0, phy);
+ phy_aml_usb2_check_rev();
+ usb_set_power_domain();
+
+ usb_reset(priv->reset_addr, USB_RESET_BIT);
+
+ udelay(500);
+ priv->usbphy_reset_bit[0] = PHY20_RESET_LEVEL_BIT;
+ priv->usbphy_reset_bit[1] = PHY21_RESET_LEVEL_BIT;
+
+ for (i = 0; i < priv->u2_port_num; i++) {
+ u2p_aml_reg = (struct u2p_aml_regs *)((ulong)(priv->base_addr + i * PHY_REGISTER_SIZE));
+ dev_u2p_r0.d32 = u2p_aml_reg->u2p_r0;
+ dev_u2p_r0.b.host_device= 1;
+ dev_u2p_r0.b.POR= 0;
+ u2p_aml_reg->u2p_r0 = dev_u2p_r0.d32;
+ udelay(10);
+ /***USB PHY RESET : reset1 and reset1_level both need set ***/
+ /***reset1: usb_reset ***/
+ /***reset1_level: usb_enable_phy_pll ***/
+ usb_reset(priv->reset_addr, priv->usbphy_reset_bit[i]);
+ udelay(50);
+
+ /* wait for phy ready */
+ dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
+ cnt = 0;
+ while (dev_u2p_r1.b.phy_rdy != 1) {
+ dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
+ /*we wait phy ready max 1ms, common is 100us*/
+ if (cnt > 200)
+ break;
+ else {
+ cnt++;
+ udelay(5);
+ }
+ }
+ }
+
+ for (i = 0; i < priv->u2_port_num; i++) {
+ debug("------set usb pll\n");
+ set_usb_pll(priv->usb_phy2_pll_base_addr[i]);
+ }
+ return 0;
+
+}
+
+int usb2_phy_tuning(uint32_t phy2_pll_base, int port)
+{
+ unsigned long phy_reg_base;
+ unsigned int pll_set38, pll_set34;
+ unsigned int rev_type = 0;
+
+ if (port > 2)
+ return 0;
+
+ pll_set38 = USB2_PHY_PLL_OFFSET_38_SET;
+ pll_set34 = USB2_PHY_PLL_OFFSET_34;
+
+ debug("pll38=0x%08x, pll34=0x%08x,\n",
+ pll_set38, pll_set34);
+
+
+ phy_reg_base = phy2_pll_base;
+
+ rev_type = phy_aml_usb2_get_rev_type();
+ if (rev_type) {
+ return 0;
+ }
+
+ (*(volatile uint32_t *)(phy_reg_base + 0x38)) = pll_set38;
+ (*(volatile uint32_t *)(phy_reg_base + 0x34)) = pll_set34;
+ return 0;
+}
+/**************************************************************/
+/* device mode config */
+/**************************************************************/
+unsigned int usb_get_dwc_a_base_addr(void)
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ int ret;
+
+ if (!usb_phys[0].dev) {
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ return usb2_priv->dwc2_a_addr;
+}
+
+unsigned int usb_get_device_mode_phy_base(void)
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ int ret;
+
+ if (!usb_phys[0].dev) {
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ return usb2_priv->usb_phy2_pll_base_addr[1];
+}
+
+void usb_phy_tuning_reset(void)
+{
+ unsigned long phy_reg_base = usb_get_device_mode_phy_base();
+ int rev_type;
+
+ rev_type = phy_aml_usb2_get_rev_type();
+
+ if (rev_type)
+ return;
+ if (phy_reg_base == 0)
+ return;
+
+ (*(volatile uint32_t *)(phy_reg_base + 0x38)) = USB2_PHY_PLL_OFFSET_38_CLEAR;
+ (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB2_PHY_PLL_OFFSET_34;
+}
+
+void usb_device_mode_init(void){
+ u2p_r0_t dev_u2p_r0;
+ u2p_r1_t dev_u2p_r1;
+
+ usb_r0_t dev_usb_r0;
+ usb_r4_t dev_usb_r4;
+ int cnt, ret;
+ u2p_aml_regs_t * u2p_aml_regs;
+ usb_aml_regs_t *usb_aml_regs;
+ struct phy_aml_usb2_priv *usb2_priv;
+ struct phy_aml_usb3_priv *usb3_priv;
+ unsigned int phy_base_addr, reset_addr;
+
+ phy_aml_usb2_check_rev();
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return;
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ usb3_priv = dev_get_priv(usb_phys[1].dev);
+ if (!usb2_priv || !usb3_priv) {
+ printf("get usb phy address from dts failed\n");
+ return;
+ }
+
+ u2p_aml_regs = (u2p_aml_regs_t * )((ulong)(usb2_priv->base_addr + PHY_REGISTER_SIZE));
+ usb_aml_regs = (usb_aml_regs_t * )((ulong)usb3_priv->base_addr);
+ phy_base_addr = usb2_priv->usb_phy2_pll_base_addr[1];
+ reset_addr = usb2_priv->reset_addr;
+
+ usb_set_power_domain();
+
+ printf("PHY2=0x%08lx,PHY3=0x%08lx\n", (uintptr_t)u2p_aml_regs, (uintptr_t)usb_aml_regs);
+ if ((*(volatile uint32_t *)((ulong)(phy_base_addr + 0x38))) != 0) {
+ usb_phy_tuning_reset();
+ mdelay(150);
+ }
+
+ //step 1: usb controller reset
+ usb_reset(reset_addr, USB_RESET_BIT);
+
+ // step 3: enable usb INT internal USB
+ dev_usb_r0.d32 = usb_aml_regs->usb_r0;
+ dev_usb_r0.b.u2d_ss_scaledown_mode = 0;
+ dev_usb_r0.b.u2d_act = 1;
+ usb_aml_regs->usb_r0 = dev_usb_r0.d32;
+
+ // step 4: disable usb phy sleep
+ dev_usb_r4.d32 = usb_aml_regs->usb_r4;
+ dev_usb_r4.b.p21_SLEEPM0 = 1;
+ usb_aml_regs->usb_r4 = dev_usb_r4.d32;
+
+ // step 5: config phy21 device mode
+ dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0;
+ dev_u2p_r0.b.host_device= 0;
+ dev_u2p_r0.b.POR= 0;
+ u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32;
+
+ udelay(10);
+ //step 6: phy21 reset
+ usb_reset(reset_addr, PHY21_RESET_LEVEL_BIT);
+ udelay(50);
+
+ // step 6: wait for phy ready
+ dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
+ cnt = 0;
+ while ((dev_u2p_r1.d32 & 0x00000001) != 1) {
+ dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
+ if (cnt > 200)
+ break;
+ else {
+ cnt++;
+ udelay(5);
+ }
+ }
+
+ set_usb_pll(phy_base_addr);
+ //--------------------------------------------------
+
+ // ------------- usb phy21 initinal end ----------
+
+ //--------------------------------------------------
+
+}
+
diff --git a/arch/arm/mach-meson/g12a/watchdog.c b/arch/arm/mach-meson/g12a/watchdog.c
deleted file mode 100644
index 2acbcbd..0000000
--- a/arch/arm/mach-meson/g12a/watchdog.c
+++ /dev/null
@@ -1,81 +0,0 @@
-
-/*
- * arch/arm/cpu/armv8/txl/watchdog.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <asm/types.h>
-#include <asm/arch/romboot.h>
-#include <asm/arch/watchdog.h>
-#include <asm/arch/io.h>
-#include <asm/arch/timer.h>
-
-void watchdog_init(uint32_t msec)
-{
- // src: 24MHz
- // div: 24000 for 1ms
- // reset ao-22 and ee-21
- *P_WATCHDOG_CNTL = (1<<24)|(1<<25)|(1<<22)|(1<<21)|(24000-1);
-
- // set timeout
- *P_WATCHDOG_TCNT = msec;
- *P_WATCHDOG_RESET = 0;
-
- // enable
- *P_WATCHDOG_CNTL |= (1<<18);
-}
-
-void watchdog_reset(void)
-{
- *P_WATCHDOG_RESET = 0;
-}
-
-void watchdog_disable(void)
-{
- // turn off internal counter and disable
- *P_WATCHDOG_CNTL &= ~((1<<18)|(1<<25));
-}
-void reset_system(void)
-{
- int i;
-#ifdef CONFIG_USB_DEVICE_V2
- *P_RESET1_REGISTER |= (1<<17);
- mdelay(200);
-#endif
- _udelay(10000); //wait print
- while (1) {
- writel( 0x3 | (1 << 21) // sys reset en
- | (1 << 23) // interrupt en
- | (1 << 24) // clk en
- | (1 << 25) // clk div en
- | (1 << 26) // sys reset now
- , P_WATCHDOG_CNTL);
- writel(0, P_WATCHDOG_RESET);
-
- writel(readl(P_WATCHDOG_CNTL) | (1<<18), // watchdog en
- P_WATCHDOG_CNTL);
- for (i=0; i<100; i++)
- readl(P_WATCHDOG_CNTL);/*Deceive gcc for waiting some cycles */
- }
-}
-
-/* uboot reset interface */
-void reset_cpu(unsigned long flag){
- reset_system();
-}
\ No newline at end of file
diff --git a/arch/arm/mach-meson/g12b/Makefile b/arch/arm/mach-meson/g12b/Makefile
index f83dd16..dbdb708 100644
--- a/arch/arm/mach-meson/g12b/Makefile
+++ b/arch/arm/mach-meson/g12b/Makefile
@@ -1,14 +1,14 @@
obj-y := sdio.o pinctrl_init.o
obj-y += bl31_apis.o
-obj-y += watchdog.o
+obj-y += cpu_reset.o
obj-y += timer.o
obj-y += mailbox.o
obj-y += gate_init.o
obj-y += power_cal.o
+obj-y += usb.o
obj-$(CONFIG_CMD_PLLTEST) += pll.o
obj-$(CONFIG_CMD_AML_MTEST) += core.o
obj-$(CONFIG_AML_HDMITX) += hdmitx.o
-obj-y += cpu_id.o
obj-$(CONFIG_AML_TSENSOR) += tsensor.o
obj-$(CONFIG_AML_OSCRING) += oscring.o
diff --git a/arch/arm/mach-meson/g12b/bl31_apis.c b/arch/arm/mach-meson/g12b/bl31_apis.c
index b71055f..11ca2f0 100644
--- a/arch/arm/mach-meson/g12b/bl31_apis.c
+++ b/arch/arm/mach-meson/g12b/bl31_apis.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txlx/bl31_apis.c
- *
- * Copyright (C) 2014-2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
/*
@@ -26,7 +11,7 @@
#include <asm/arch/efuse.h>
#include <asm/cache.h>
#include <asm/arch/bl31_apis.h>
-#include <asm/arch/cpu_id.h>
+#include <amlogic/cpu_id.h>
#include <asm/arch/secure_apb.h>
static long sharemem_input_base;
@@ -42,6 +27,36 @@
return function_id;
}
+int32_t set_boot_params(const keymaster_boot_params *boot_params)
+{
+ const unsigned cmd = SET_BOOT_PARAMS;
+
+ if (!boot_params)
+ return -1;
+
+ if (!sharemem_input_base)
+ sharemem_input_base =
+ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE);
+
+ memcpy((void *)sharemem_input_base,
+ (const void *)boot_params, sizeof(keymaster_boot_params));
+
+ asm __volatile__("" : : : "memory");
+ register uint64_t x0 asm("x0") = cmd;
+ register uint64_t x1 asm("x1") = sizeof(keymaster_boot_params);
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1));
+ } while (0);
+
+ return (!x0)? -1: 0;
+}
+
#ifdef CONFIG_EFUSE
int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg)
{
@@ -68,7 +83,7 @@
if (arg->cmd == EFUSE_HAL_API_WRITE)
memcpy((void *)sharemem_input_base,
(const void *)arg->buffer_phy, size);
- asm __volatile__("" : : : "memory");
+ asm __volatile__("" : : : "memory");
register uint64_t x0 asm("x0") = cmd;
register uint64_t x1 asm("x1") = offset;
@@ -98,7 +113,7 @@
int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg)
{
- int32_t ret = 0;
+ int32_t ret;
unsigned cmd = 0;
if (arg->cmd == EFUSE_HAL_API_USER_MAX)
@@ -408,3 +423,37 @@
return -1;
}
+
+int32_t get_avbkey_from_fip(uint8_t *buf, uint32_t buflen)
+{
+ const unsigned cmd = GET_AVBKEY_FROM_FIP;
+ uint32_t retlen = 0;
+ uint32_t ret = 0;
+
+ if (!buf)
+ return -1;
+
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ asm __volatile__("" : : : "memory");
+ register uint64_t x0 asm("x0") = cmd;
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0));
+ } while (0);
+
+ if (!x0)
+ ret = -1;
+ retlen = x0;
+
+ if (ret != -1 && buflen >= retlen)
+ memcpy(buf, (const void *)sharemem_output_base, retlen);
+
+ return ret;
+}
diff --git a/arch/arm/mach-meson/g12b/core.c b/arch/arm/mach-meson/g12b/core.c
index 73519bb..8640828 100644
--- a/arch/arm/mach-meson/g12b/core.c
+++ b/arch/arm/mach-meson/g12b/core.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/g12a/core.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <asm/arch/secure_apb.h>
#include <asm/types.h>
diff --git a/arch/arm/mach-meson/g12b/cpu_id.c b/arch/arm/mach-meson/g12b/cpu_id.c
deleted file mode 100644
index 8457866..0000000
--- a/arch/arm/mach-meson/g12b/cpu_id.c
+++ /dev/null
@@ -1,65 +0,0 @@
-/*
- * arch/arm/cpu/armv8/cpu_id.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <asm/arch/cpu_id.h>
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/io.h>
-
-/**
- * TODO: This should be moved to a RO region of registers or SRAM that
- * provides static system information that's needed across all software
- *
- * Chip ID copy to avoid unnecessary message exchange.
- */
-chip_id_t aml_chip_id = { 0, { 0 } };
-
-cpu_id_t get_cpu_id(void)
-{
- cpu_id_t cpu_id;
- unsigned int cpu_id_reg = readl(P_AO_SEC_SD_CFG8);
-
- memset(&cpu_id, 0, sizeof(cpu_id_t));
- cpu_id.family_id = (cpu_id_reg >> 24) & (0XFF);
- cpu_id.package_id = (cpu_id_reg >> 16) & (0XF0);
- cpu_id.chip_rev = (cpu_id_reg >> 8) & (0XFF);
- cpu_id.layout_ver = (cpu_id_reg) & (0XF);
- return cpu_id;
-}
-
-int get_chip_id(unsigned char *buff, unsigned int size)
-{
- int rc = 0;
-
- if (buff == NULL || size < 16)
- return -1;
-
- if (aml_chip_id.version == 0) {
- /* Chip ID has not been fetched yet */
- rc = __get_chip_id(&aml_chip_id.chipid[0], 16);
-
- /* Mark version if chip ID is fetched successfully */
- if (rc == 0)
- aml_chip_id.version = 2;
- }
-
- memcpy(buff, &aml_chip_id.chipid[0], 16);
- return rc;
-}
diff --git a/arch/arm/mach-meson/g12b/cpu_reset.c b/arch/arm/mach-meson/g12b/cpu_reset.c
new file mode 100644
index 0000000..070fd62
--- /dev/null
+++ b/arch/arm/mach-meson/g12b/cpu_reset.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/types.h>
+#include <asm/arch/romboot.h>
+#include <asm/arch/cpu_reset.h>
+#include <asm/arch/io.h>
+#include <asm/arch/timer.h>
+#include <wdt.h>
+#include <dm.h>
+
+/*
+ *GPIOE_0 VDDEE_PWM
+ *GPIOE_1 VDDCPU_PWM_B
+ *GPIOE_2 VDDCPU_PWM_A
+ * */
+void set_pwm_to_input(void)
+{
+ unsigned int val;
+
+ val = readl(AO_RTI_PINMUX_REG1);
+ val &= ~(0xfff << 16);
+ writel(val, AO_RTI_PINMUX_REG1);/* clear pinmux */
+ val = readl(AO_GPIO_O_EN_N);
+ val &= ~(0x7 << 16);
+ val |= 0x7 << 16;
+ writel(val, AO_GPIO_O_EN_N);/* set input mode */
+ val = readl(AO_RTI_PULL_UP_EN_REG);
+ val &= ~(0x7 << 16);
+ writel(val, AO_RTI_PULL_UP_EN_REG);/* disable pull up/down */
+}
+
+void reset_system(void)
+{
+ struct udevice *wdt;
+ int ret;
+
+#ifdef CONFIG_USB_DEVICE_V2
+ *P_RESET1_REGISTER |= (1<<17);
+ mdelay(200);
+#endif
+
+ set_pwm_to_input();
+ _udelay(10000); //wait print
+
+ ret = uclass_get_device_by_name(UCLASS_WDT, "watchdog", &wdt);
+ if (ret) {
+ printf("failed to reset system because can't get wdt device\n");
+ return;
+ }
+
+ wdt_start(wdt, 0, 0);
+ while (1);
+}
+
+/* uboot reset interface */
+void reset_cpu(unsigned long flag){
+ reset_system();
+}
diff --git a/arch/arm/mach-meson/g12b/firmware/acs/Makefile b/arch/arm/mach-meson/g12b/firmware/acs/Makefile
index 54b2e48..38d0dbd 100644
--- a/arch/arm/mach-meson/g12b/firmware/acs/Makefile
+++ b/arch/arm/mach-meson/g12b/firmware/acs/Makefile
@@ -200,10 +200,6 @@
NM := ${CROSS_COMPILE}nm
PP := ${CROSS_COMPILE}gcc -E ${CFLAGS}
-ifeq ($(BL33_DEBUG), 1)
- CFLAGS += -DBL33_DEBUG_PRINT
-endif
-
# Variables for use with Firmware Image Package
FIPTOOLPATH ?= tools/fip_create
FIPTOOL ?= ${FIPTOOLPATH}/fip_create
diff --git a/arch/arm/mach-meson/g12b/firmware/acs/acs.c b/arch/arm/mach-meson/g12b/firmware/acs/acs.c
index 66bd216..9d1ab36 100644
--- a/arch/arm/mach-meson/g12b/firmware/acs/acs.c
+++ b/arch/arm/mach-meson/g12b/firmware/acs/acs.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/firmware/acs/acs.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <asm/arch/acs.h>
#include <asm/arch/timing.h>
@@ -59,4 +43,7 @@
.rsv_set_version= 1,
.rsv_set_length = 0,
.rsv_set_addr = 0,
+ .board_id = {0,},
+ .ddr_struct_size = {0,},
+ .ddr_struct_org_size = sizeof(ddr_set_t),
};
diff --git a/arch/arm/mach-meson/g12b/firmware/acs/acs.ld.S b/arch/arm/mach-meson/g12b/firmware/acs/acs.ld.S
index c818b1a..4a952c7 100644
--- a/arch/arm/mach-meson/g12b/firmware/acs/acs.ld.S
+++ b/arch/arm/mach-meson/g12b/firmware/acs/acs.ld.S
@@ -12,7 +12,8 @@
*acs_entry.o(.text*)
*(.text*)
*(.data*)
+ *(.ddr_settings*)
}
- ASSERT(. <= 0xFFFB0000, "timing image has exceeded its limit.")
+ //ASSERT(. <= 0xFFFB0000, "timing image has exceeded its limit.")
}
diff --git a/arch/arm/mach-meson/g12b/firmware/acs/acs_entry.S b/arch/arm/mach-meson/g12b/firmware/acs/acs_entry.S
index 52d56f2..d983cda 100644
--- a/arch/arm/mach-meson/g12b/firmware/acs/acs_entry.S
+++ b/arch/arm/mach-meson/g12b/firmware/acs/acs_entry.S
@@ -3,4 +3,11 @@
acs_entry:
.word 0
- .word __acs_set
\ No newline at end of file
+ .word __acs_set
+#ifdef CONFIG_MDUMP_COMPRESS
+ .word __ramdump_data
+ .word __ddr_setting
+#else
+ .word 0x0
+ .word __ddr_setting
+#endif
diff --git a/arch/arm/mach-meson/g12b/firmware/scp_task/Makefile b/arch/arm/mach-meson/g12b/firmware/scp_task/Makefile
index 46c8877..ecc4671 100644
--- a/arch/arm/mach-meson/g12b/firmware/scp_task/Makefile
+++ b/arch/arm/mach-meson/g12b/firmware/scp_task/Makefile
@@ -6,13 +6,13 @@
include $(buildtree)/.config
# Select ARMv7-m bare-metal toolchain
-#CROSS_COMPILE=arm-none-eabi-
-ASM=$(CROSS_COMPILE_T32)as
-CC=$(CROSS_COMPILE_T32)gcc
-CPP=$(CROSS_COMPILE_T32)cpp
-LD=$(CROSS_COMPILE_T32)ld
-OBJCOPY=$(CROSS_COMPILE_T32)objcopy
-OBJDUMP=$(CROSS_COMPILE_T32)objdump
+CROSS_COMPILE=arm-none-eabi-
+ASM=$(CROSS_COMPILE)as
+CC=$(CROSS_COMPILE)gcc
+CPP=$(CROSS_COMPILE)cpp
+LD=$(CROSS_COMPILE)ld
+OBJCOPY=$(CROSS_COMPILE)objcopy
+OBJDUMP=$(CROSS_COMPILE)objdump
ARM_ARCH=armv7-m
ARM_CPU=cortex-m3
@@ -48,10 +48,6 @@
LDFLAGS=-Bstatic
#LDFLAGS+=$(LD_LIB_PATH_ARM:%=-L%) -lm -lc -lgcc
-ifeq ($(BL33_DEBUG), 1)
- CFLAGS += -DBL33_DEBUG_PRINT
-endif
-
# Output directory for build objects
obj=$(buildtree)/scp_task
diff --git a/arch/arm/mach-meson/g12b/firmware/scp_task/aml_led.c b/arch/arm/mach-meson/g12b/firmware/scp_task/aml_led.c
index e899729..5570001 100644
--- a/arch/arm/mach-meson/g12b/firmware/scp_task/aml_led.c
+++ b/arch/arm/mach-meson/g12b/firmware/scp_task/aml_led.c
@@ -1,9 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * uboot/aml_led.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <amlogic/aml_led.h>
diff --git a/arch/arm/mach-meson/g12b/firmware/scp_task/cec_tx_reg.h b/arch/arm/mach-meson/g12b/firmware/scp_task/cec_tx_reg.h
index 4b9df96..a124316 100644
--- a/arch/arm/mach-meson/g12b/firmware/scp_task/cec_tx_reg.h
+++ b/arch/arm/mach-meson/g12b/firmware/scp_task/cec_tx_reg.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/cec_tx_reg.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _CEC_TX_REG_H
#define _CEC_TX_REG_H
diff --git a/arch/arm/mach-meson/g12b/firmware/scp_task/config.h b/arch/arm/mach-meson/g12b/firmware/scp_task/config.h
index de0eae6..9c11419 100644
--- a/arch/arm/mach-meson/g12b/firmware/scp_task/config.h
+++ b/arch/arm/mach-meson/g12b/firmware/scp_task/config.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/config.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _CONFIG_H_
#define _CONFIG_H_
diff --git a/arch/arm/mach-meson/g12b/firmware/scp_task/data.h b/arch/arm/mach-meson/g12b/firmware/scp_task/data.h
index 5c67a97..f8cb67f 100644
--- a/arch/arm/mach-meson/g12b/firmware/scp_task/data.h
+++ b/arch/arm/mach-meson/g12b/firmware/scp_task/data.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/data.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include "config.h"
diff --git a/arch/arm/mach-meson/g12b/firmware/scp_task/gpio.h b/arch/arm/mach-meson/g12b/firmware/scp_task/gpio.h
index 082f0ad..865d67f 100644
--- a/arch/arm/mach-meson/g12b/firmware/scp_task/gpio.h
+++ b/arch/arm/mach-meson/g12b/firmware/scp_task/gpio.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/gpio-gxbb.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __ARCH_GXBB_GPIO_H__
#define __ARCH_GXBB_GPIO_H__
diff --git a/arch/arm/mach-meson/g12b/firmware/scp_task/hdmi_cec_arc.c b/arch/arm/mach-meson/g12b/firmware/scp_task/hdmi_cec_arc.c
index 0e2906a..ebec465 100644
--- a/arch/arm/mach-meson/g12b/firmware/scp_task/hdmi_cec_arc.c
+++ b/arch/arm/mach-meson/g12b/firmware/scp_task/hdmi_cec_arc.c
@@ -1,7 +1,8 @@
-/**************************************************
- * HDMI CEC uboot code *
- * *
- **************************************************/
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifdef CONFIG_CEC_WAKEUP
#include "secure_apb.h"
#include "cec_tx_reg.h"
diff --git a/arch/arm/mach-meson/g12b/firmware/scp_task/lib/delay.c b/arch/arm/mach-meson/g12b/firmware/scp_task/lib/delay.c
index cd15225..3fb9915 100644
--- a/arch/arm/mach-meson/g12b/firmware/scp_task/lib/delay.c
+++ b/arch/arm/mach-meson/g12b/firmware/scp_task/lib/delay.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/lib/delay.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#define P_AO_TIMER_E (*((volatile unsigned *)(0xff800000 + (0xf9 << 2))))
unsigned int get_time(void)
diff --git a/arch/arm/mach-meson/g12b/firmware/scp_task/lib/string.c b/arch/arm/mach-meson/g12b/firmware/scp_task/lib/string.c
index 2e551f4..fa270c0 100644
--- a/arch/arm/mach-meson/g12b/firmware/scp_task/lib/string.c
+++ b/arch/arm/mach-meson/g12b/firmware/scp_task/lib/string.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/lib/string.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
void *memcpy(void *dest, const void *src, unsigned int count)
{
diff --git a/arch/arm/mach-meson/g12b/firmware/scp_task/registers.h b/arch/arm/mach-meson/g12b/firmware/scp_task/registers.h
index 0ad0fc7..ba8d224 100644
--- a/arch/arm/mach-meson/g12b/firmware/scp_task/registers.h
+++ b/arch/arm/mach-meson/g12b/firmware/scp_task/registers.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/registers.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _SCP_REGISTER_DEFINES_
#define _SCP_REGISTER_DEFINES_
diff --git a/arch/arm/mach-meson/g12b/firmware/scp_task/scp_adc.c b/arch/arm/mach-meson/g12b/firmware/scp_task/scp_adc.c
index d5f44bd..fadb302 100644
--- a/arch/arm/mach-meson/g12b/firmware/scp_task/scp_adc.c
+++ b/arch/arm/mach-meson/g12b/firmware/scp_task/scp_adc.c
@@ -1,3 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#define MESON_CPU_MAJOR_ID_GXBB 0x1F
#define MESON_CPU_MAJOR_ID_GXTVBB 0x20
#define MESON_CPU_MAJOR_ID_GXL 0x21
diff --git a/arch/arm/mach-meson/g12b/firmware/scp_task/scp_remote.c b/arch/arm/mach-meson/g12b/firmware/scp_task/scp_remote.c
index c52eb5a..aafaa69 100644
--- a/arch/arm/mach-meson/g12b/firmware/scp_task/scp_remote.c
+++ b/arch/arm/mach-meson/g12b/firmware/scp_task/scp_remote.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/scp_remote.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <config.h>
#include "config.h"
@@ -284,6 +268,10 @@
static int init_remote(void)
{
return 0;
+ uart_put_hex(readl(AO_IR_DEC_STATUS), 32);
+ uart_put_hex(readl(AO_IR_DEC_FRAME), 32);
+ init_custom_trigger();
+ //return 0;
}
/*can be called in pwr_ctrl.c*/
diff --git a/arch/arm/mach-meson/g12b/firmware/scp_task/secure_apb.h b/arch/arm/mach-meson/g12b/firmware/scp_task/secure_apb.h
index 67f88be..a5fbfbc 100644
--- a/arch/arm/mach-meson/g12b/firmware/scp_task/secure_apb.h
+++ b/arch/arm/mach-meson/g12b/firmware/scp_task/secure_apb.h
@@ -1,15 +1,8 @@
-// ----------------------------------------------------------------------
-// This file is automatically generated from the script:
-//
-// ./create_headers_from_secure_apb4_h.pl
-//
-// and was applied to the file
-//
-// ./secure_apb4_ee.h ./ao_rti_reg.h
-//
-// DO NOT EDIT!!!!!
-// ----------------------------------------------------------------------
-//
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifdef SECURE_APB_H
#else
#define SECURE_APB_H
diff --git a/arch/arm/mach-meson/g12b/firmware/scp_task/suspend.c b/arch/arm/mach-meson/g12b/firmware/scp_task/suspend.c
index 7274ada..d9962dd 100644
--- a/arch/arm/mach-meson/g12b/firmware/scp_task/suspend.c
+++ b/arch/arm/mach-meson/g12b/firmware/scp_task/suspend.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/suspend.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include "config.h"
#include "registers.h"
diff --git a/arch/arm/mach-meson/g12b/firmware/scp_task/suspend.h b/arch/arm/mach-meson/g12b/firmware/scp_task/suspend.h
index e957a02..34bfca7 100644
--- a/arch/arm/mach-meson/g12b/firmware/scp_task/suspend.h
+++ b/arch/arm/mach-meson/g12b/firmware/scp_task/suspend.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/suspend.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __SCP_SUSPEND_H_
#define __SCP_SUSPEND_H_
diff --git a/arch/arm/mach-meson/g12b/firmware/scp_task/task_apis.h b/arch/arm/mach-meson/g12b/firmware/scp_task/task_apis.h
index 31ab63f..4bb9274 100644
--- a/arch/arm/mach-meson/g12b/firmware/scp_task/task_apis.h
+++ b/arch/arm/mach-meson/g12b/firmware/scp_task/task_apis.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/task_apis.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __TASK_APIS_H_
#define __TASK_APIS_H_
diff --git a/arch/arm/mach-meson/g12b/firmware/scp_task/uart.c b/arch/arm/mach-meson/g12b/firmware/scp_task/uart.c
index a3dc56f..0ac32c8 100644
--- a/arch/arm/mach-meson/g12b/firmware/scp_task/uart.c
+++ b/arch/arm/mach-meson/g12b/firmware/scp_task/uart.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/uart.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include "registers.h"
#include <stdint.h>
diff --git a/arch/arm/mach-meson/g12b/firmware/scp_task/user_task.c b/arch/arm/mach-meson/g12b/firmware/scp_task/user_task.c
index ebad8c8..6984a92 100644
--- a/arch/arm/mach-meson/g12b/firmware/scp_task/user_task.c
+++ b/arch/arm/mach-meson/g12b/firmware/scp_task/user_task.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/firmware/scp_task/user_task.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include "config.h"
#include "data.h"
@@ -81,7 +65,7 @@
/*init bss */
bss_init();
- pr_info("secure task start!\n");
+ dbg_prints("secure task start!\n");
/* suspend pwr ops init*/
suspend_pwr_ops_init();
@@ -129,7 +113,7 @@
(unsigned *)(&(high_task_share_mem[TASK_RESPONSE_OFFSET]));
unsigned command;
- pr_info("high task start!\n");
+ dbg_prints("high task start!\n");
*pcommand = 0;
while (1) {
@@ -170,7 +154,7 @@
unsigned command;
*pcommand = 0;
- pr_info("low task start!\n");
+ dbg_prints("low task start!\n");
while (1) {
/* do low task process */
diff --git a/arch/arm/mach-meson/g12b/gate_init.c b/arch/arm/mach-meson/g12b/gate_init.c
index 7390665..31629f6 100644
--- a/arch/arm/mach-meson/g12b/gate_init.c
+++ b/arch/arm/mach-meson/g12b/gate_init.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/gate_init.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include "power_gate.h"
diff --git a/arch/arm/mach-meson/g12b/hdmitx.c b/arch/arm/mach-meson/g12b/hdmitx.c
index b9ca3d9..5292c87 100644
--- a/arch/arm/mach-meson/g12b/hdmitx.c
+++ b/arch/arm/mach-meson/g12b/hdmitx.c
@@ -1,22 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/mach-meson/g12a/hdmitx.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <common.h>
#include <asm/arch/io.h>
diff --git a/arch/arm/mach-meson/g12b/mailbox.c b/arch/arm/mach-meson/g12b/mailbox.c
index b1e860f..2c99d81 100644
--- a/arch/arm/mach-meson/g12b/mailbox.c
+++ b/arch/arm/mach-meson/g12b/mailbox.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/mailbox.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <config.h>
#include <common.h>
diff --git a/arch/arm/mach-meson/g12b/oscring.c b/arch/arm/mach-meson/g12b/oscring.c
index 3bdbe4a..a9cdab9 100644
--- a/arch/arm/mach-meson/g12b/oscring.c
+++ b/arch/arm/mach-meson/g12b/oscring.c
@@ -1,3 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include <config.h>
#include <common.h>
#include <asm/arch/io.h>
@@ -58,7 +63,7 @@
[0] = "am_ring_osc_clk_out_ee[0] " ,
};
const int tb[] = {0, 1, 2, 99, 100, 101, 102, 103, 104, 105, 3, 33};
- unsigned long i;
+ unsigned long i = 0;
unsigned char efuseinfo[12] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
if ((index != 0xff) && (index != 0)) {
@@ -100,7 +105,7 @@
}
printf("osc efuse info:\n");
- for (i = 0; i <= 11; i++)
+ for (i = 0; i < sizeof(efuseinfo) / sizeof(uint8_t); i++)
printf("0x%x, ", efuseinfo[i]);
printf("\n");
diff --git a/arch/arm/mach-meson/g12b/pinctrl_init.c b/arch/arm/mach-meson/g12b/pinctrl_init.c
index 5c40be1..829ce28 100644
--- a/arch/arm/mach-meson/g12b/pinctrl_init.c
+++ b/arch/arm/mach-meson/g12b/pinctrl_init.c
@@ -1,8 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
- * Author: Xingyu Chen <xingyu.chen@amlogic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
diff --git a/arch/arm/mach-meson/g12b/pll.c b/arch/arm/mach-meson/g12b/pll.c
index e4b716f..e42de30 100644
--- a/arch/arm/mach-meson/g12b/pll.c
+++ b/arch/arm/mach-meson/g12b/pll.c
@@ -1,15 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * rev history:
- * 2017.04.06 structure done
- *
- *
- *
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
#include <command.h>
-#include <asm/cpu_id.h>
+#include <amlogic/cpu_id.h>
#include <malloc.h>
#include <asm/io.h>
#include <asm/arch/clock.h>
diff --git a/arch/arm/mach-meson/g12b/power_cal.c b/arch/arm/mach-meson/g12b/power_cal.c
index d4accfc..e4f9c53 100644
--- a/arch/arm/mach-meson/g12b/power_cal.c
+++ b/arch/arm/mach-meson/g12b/power_cal.c
@@ -1,28 +1,12 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/xx/power_cal.c
- *
- * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <common.h>
#include <asm/arch/secure_apb.h>
#include <asm/arch/io.h>
-#include <asm/arch/saradc.h>
+#include <amlogic/saradc.h>
#include <asm/arch/mailbox.h>
#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2))))
diff --git a/arch/arm/mach-meson/g12b/power_gate.h b/arch/arm/mach-meson/g12b/power_gate.h
index 33f42bf..9ca1a9d 100644
--- a/arch/arm/mach-meson/g12b/power_gate.h
+++ b/arch/arm/mach-meson/g12b/power_gate.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * arch/arm/cpu/armv8/txl/power_gate.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __POWER_MGR_HEADER_
#define __POWER_MGR_HEADER_
diff --git a/arch/arm/mach-meson/g12b/sdio.c b/arch/arm/mach-meson/g12b/sdio.c
index 000d641..93dcc8f 100644
--- a/arch/arm/mach-meson/g12b/sdio.c
+++ b/arch/arm/mach-meson/g12b/sdio.c
@@ -1,29 +1,13 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/sdio.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <config.h>
#include <asm/arch/io.h>
#include <asm/arch/cpu_sdio.h>
#include <asm/arch/secure_apb.h>
-#include <asm/arch/cpu_id.h>
+#include <amlogic/cpu_id.h>
#include <common.h>
void cpu_sd_emmc_pwr_prepare(unsigned port)
diff --git a/arch/arm/mach-meson/g12b/timer.c b/arch/arm/mach-meson/g12b/timer.c
index 1687bb9..80c17bb 100644
--- a/arch/arm/mach-meson/g12b/timer.c
+++ b/arch/arm/mach-meson/g12b/timer.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * arch/arm/cpu/armv8/txl/timer.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <asm/arch/secure_apb.h>
#include <asm/arch/timer.h>
diff --git a/arch/arm/mach-meson/g12b/tsensor.c b/arch/arm/mach-meson/g12b/tsensor.c
index c43db95..6d8adf9 100644
--- a/arch/arm/mach-meson/g12b/tsensor.c
+++ b/arch/arm/mach-meson/g12b/tsensor.c
@@ -1,3 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include <common.h>
#include <asm/io.h>
#include <command.h>
@@ -46,7 +51,7 @@
udelay(50);
value_ts = readl(TS_PLL_STAT0) & 0xffff;
}
- for (i = 0; i <= T_AVG_NUM; i ++) {
+ for (i = 0; i < T_READ_NUM; i ++) {
udelay(T_DLY_TIME);
value_ts = readl(TS_PLL_STAT0) & 0xffff;
if ((value_ts >= T_VALUE_MIN) &&
@@ -55,7 +60,12 @@
cnt ++;
}
}
- value_ts = value_all_ts / cnt;
+ if (cnt) {
+ value_ts = value_all_ts / cnt;
+ } else {
+ value_ts = 0;
+ printf("tsensor read temp cnt is zero");
+ }
printf("pll tsensor avg: 0x%x, u_efuse: 0x%x\n", value_ts, u_efuse);
if (value_ts == 0) {
printf("tsensor read temp is zero\n");
@@ -81,7 +91,7 @@
udelay(50);
value_ts = readl(TS_DDR_STAT0) & 0xffff;
}
- for (i = 0; i <= T_AVG_NUM; i ++) {
+ for (i = 0; i <= T_READ_NUM; i ++) {
udelay(T_DLY_TIME);
value_ts = readl(TS_DDR_STAT0) & 0xffff;
if ((value_ts >= T_VALUE_MIN) &&
@@ -90,7 +100,12 @@
cnt ++;
}
}
- value_ts = value_all_ts / cnt;
+ if (cnt) {
+ value_ts = value_all_ts / cnt;
+ } else {
+ value_ts = 0;
+ printf("tsensor read temp cnt is zero");
+ }
printf("ddr tsensor avg: 0x%x, u_efuse: 0x%x\n", value_ts, u_efuse);
if (value_ts == 0) {
printf("tsensor read temp is zero\n");
diff --git a/arch/arm/mach-meson/g12b/usb.c b/arch/arm/mach-meson/g12b/usb.c
new file mode 100644
index 0000000..14ffdb4
--- /dev/null
+++ b/arch/arm/mach-meson/g12b/usb.c
@@ -0,0 +1,425 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <power/regulator.h>
+#include <clk.h>
+#include <asm/arch/usb.h>
+#include <amlogic/cpu_id.h>
+
+#include <linux/compat.h>
+#include <linux/ioport.h>
+#include <asm-generic/gpio.h>
+
+#define PHY20_RESET_LEVEL_BIT 16
+#define PHY21_RESET_LEVEL_BIT 17
+#define USB_RESET_BIT 2
+
+#define USB2_PHY_PLL_OFFSET_40 (0x09400414)
+#define USB2_PHY_PLL_OFFSET_44 (0x927E0000)
+#define USB2_PHY_PLL_OFFSET_48 (0xac5f69e5)
+
+#define USB2_PHY_PLL_OFFSET_10 (0x80000fff)
+#define USB2_PHY_PLL_OFFSET_34 (0x78000)
+#define USB2_REVB_PHY_PLL_OFFSET_34 (0x70000)
+
+#define USB2_PHY_PLL_OFFSET_38_CLEAR (0)
+#define USB2_PHY_PLL_OFFSET_38_SET (0xe0004)
+#define USB2_PHY_PLL_OFFSET_50 (0xfe18)
+#define USB2_PHY_PLL_OFFSET_54 (0x2a)
+
+#define TUNING_DISCONNECT_THRESHOLD 0x3C
+
+static int Rev_flag = 0;
+
+static struct phy usb_phys[2];
+
+/*Rev_flag == 0XB, g12b and revB, tl1 */
+/*Rev_flag == 1, sm1 */
+static void phy_aml_usb2_check_rev (void)
+{
+ cpu_id_t cpu_id = get_cpu_id();
+
+ if (cpu_id.family_id == MESON_CPU_MAJOR_ID_G12B) {
+ if (cpu_id.chip_rev == 0xb)
+ Rev_flag = 0xb;
+ else
+ Rev_flag = 0;
+ } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SM1) {
+ Rev_flag = MESON_CPU_MAJOR_ID_SM1;
+ } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_A1) {
+ Rev_flag = MESON_CPU_MAJOR_ID_A1;
+ } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_C1) {
+ Rev_flag = MESON_CPU_MAJOR_ID_C1;
+ }
+ return;
+}
+
+static int phy_aml_usb2_get_rev_type (void)
+{
+ int val = 0;
+
+ switch (Rev_flag) {
+ case MESON_CPU_MAJOR_ID_SM1:
+ case MESON_CPU_MAJOR_ID_A1:
+ case MESON_CPU_MAJOR_ID_C1:
+ case 0xb:
+ val = 1;
+ break;
+ default:
+ printk("amlogic usb phy need tuning\n");
+ val = 0;
+ break;
+ }
+
+ return val;
+}
+
+int get_usbphy_baseinfo(struct phy *usb_phys)
+{
+ struct udevice *bus;
+ struct uclass *uc;
+ int ret, i;
+ int count;
+
+ if (usb_phys[0].dev && usb_phys[1].dev)
+ return 0;
+
+ ret = uclass_get(UCLASS_USB, &uc);
+ if (ret)
+ return ret;
+ uclass_foreach_dev(bus, uc) {
+ debug("bus->name=%s, bus->driver->name =%s\n",
+ bus->name, bus->driver->name);
+ count = dev_count_phandle_with_args(bus, "phys", "#phy-cells");
+ debug("usb phy count=%u\n", count);
+ if (count <= 0)
+ return count;
+ for (i = 0; i < count; i++) {
+ ret = generic_phy_get_by_index(bus, i, &usb_phys[i]);
+ if (ret && ret != -ENOENT) {
+ pr_err("Failed to get USB PHY%d for %s\n",
+ i, bus->name);
+ return ret;
+ }
+ ret = generic_phy_getinfo(&usb_phys[i]);
+ if (ret)
+ return ret;
+ }
+ }
+ return 0;
+}
+
+int usb_aml_detect_operation(int argc, char * const argv[])
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ struct phy_aml_usb3_priv *usb3_priv;
+ int ret;
+
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ usb3_priv = dev_get_priv(usb_phys[1].dev);
+
+ if (usb3_priv) {
+ printf("priv->usb3 port num = %d, config addr=0x%08x\n",
+ usb3_priv->usb3_port_num, usb3_priv->base_addr);
+ }
+ if (usb2_priv) {
+ printf("usb2 phy: config addr = 0x%08x, reset addr=0x%08x\n",
+ usb2_priv->base_addr, usb2_priv->reset_addr);
+
+ printf("usb2 phy: portnum=%d, phy-addr1= 0x%08x, phy-addr2= 0x%08x\n",
+ usb2_priv->u2_port_num, usb2_priv->usb_phy2_pll_base_addr[0],
+ usb2_priv->usb_phy2_pll_base_addr[1]);
+ printf("dwc2_a base addr: 0x%08x\n", usb2_priv->dwc2_a_addr);
+ }
+ phy_aml_usb2_check_rev();
+ printf("PHY version is 0x%02x\n", Rev_flag);
+ return 0;
+}
+
+static void set_pll_Calibration_default(uint32_t phy2_pll_base)
+{
+ u32 tmp;
+
+ tmp = (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x8));
+ tmp &= 0xfff;
+ tmp |= (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10));
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10))
+ = tmp;
+}
+
+void usb_reset(unsigned int reset_addr, int bit){
+ *(volatile unsigned int *)(unsigned long)reset_addr = (1 << bit);
+}
+
+void set_usb_pll(uint32_t phy2_pll_base)
+{
+ int hardware_rev;
+
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))
+ = (USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET | USB_PHY2_ENABLE);
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44)) =
+ USB2_PHY_PLL_OFFSET_44;
+ hardware_rev = phy_aml_usb2_get_rev_type();
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x48)) =
+ USB2_PHY_PLL_OFFSET_48;
+ udelay(100);
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x40))
+ = (((USB2_PHY_PLL_OFFSET_40) | (USB_PHY2_ENABLE))
+ & (~(USB_PHY2_RESET)));
+
+ if (hardware_rev) {
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50))
+ = USB2_PHY_PLL_OFFSET_50;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x54))
+ = USB2_PHY_PLL_OFFSET_54;
+ set_pll_Calibration_default(phy2_pll_base);
+ } else {
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50))
+ = USB2_PHY_PLL_OFFSET_50;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10))
+ = USB2_PHY_PLL_OFFSET_10;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x38))
+ = USB2_PHY_PLL_OFFSET_38_CLEAR;
+ }
+
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0xc)) =
+ TUNING_DISCONNECT_THRESHOLD;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x34))
+ = USB2_PHY_PLL_OFFSET_34;
+ debug("tuning_disconnect_threshold=0x%x\n", TUNING_DISCONNECT_THRESHOLD);
+}
+
+int usb_save_phy_dev (unsigned int number, struct phy *phy)
+{
+ usb_phys[number].dev = phy->dev;
+ usb_phys[number].id = phy->id;
+ return 0;
+}
+
+int usb2_phy_init (struct phy *phy) {
+ struct phy_aml_usb2_priv *priv = dev_get_priv(phy->dev);
+ struct u2p_aml_regs *u2p_aml_reg;
+ u2p_r0_t dev_u2p_r0;
+ u2p_r1_t dev_u2p_r1;
+ int i,cnt;
+
+ usb_save_phy_dev(0, phy);
+ phy_aml_usb2_check_rev();
+
+ *(volatile unsigned int *)(unsigned long)priv->reset_addr = (1 << USB_RESET_BIT);
+
+ udelay(500);
+ priv->usbphy_reset_bit[0] = PHY20_RESET_LEVEL_BIT;
+ priv->usbphy_reset_bit[1] = PHY21_RESET_LEVEL_BIT;
+
+ for (i = 0; i < priv->u2_port_num; i++) {
+ u2p_aml_reg = (struct u2p_aml_regs *)((ulong)(priv->base_addr + i * PHY_REGISTER_SIZE));
+ dev_u2p_r0.d32 = u2p_aml_reg->u2p_r0;
+ dev_u2p_r0.b.host_device= 1;
+ dev_u2p_r0.b.POR= 0;
+ u2p_aml_reg->u2p_r0 = dev_u2p_r0.d32;
+ udelay(10);
+ *(volatile unsigned int *)(unsigned long)priv->reset_addr = (1 << priv->usbphy_reset_bit[i]);
+ udelay(50);
+
+ /* wait for phy ready */
+ dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
+ cnt = 0;
+ while (dev_u2p_r1.b.phy_rdy != 1) {
+ dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
+ /*we wait phy ready max 1ms, common is 100us*/
+ if (cnt > 200)
+ break;
+ else {
+ cnt++;
+ udelay(5);
+ }
+ }
+ }
+
+ for (i = 0; i < priv->u2_port_num; i++) {
+ debug("------set usb pll\n");
+ set_usb_pll(priv->usb_phy2_pll_base_addr[i]);
+ }
+ return 0;
+
+}
+
+int usb2_phy_tuning(uint32_t phy2_pll_base, int port)
+{
+ unsigned long phy_reg_base;
+ unsigned int pll_set38, pll_set34;
+ unsigned int rev_type = 0;
+
+ if (port > 2)
+ return 0;
+
+ pll_set38 = USB2_PHY_PLL_OFFSET_38_SET;
+ pll_set34 = USB2_PHY_PLL_OFFSET_34;
+
+ debug("pll38=0x%08x, pll34=0x%08x,\n",
+ pll_set38, pll_set34);
+
+
+ phy_reg_base = phy2_pll_base;
+
+ rev_type = phy_aml_usb2_get_rev_type();
+ if (rev_type) {
+ return 0;
+ }
+
+ (*(volatile uint32_t *)(phy_reg_base + 0x38)) = pll_set38;
+ (*(volatile uint32_t *)(phy_reg_base + 0x34)) = pll_set34;
+ return 0;
+}
+
+/**************************************************************/
+/* device mode config */
+/**************************************************************/
+unsigned int usb_get_dwc_a_base_addr(void)
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ int ret;
+
+ if (!usb_phys[0].dev) {
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ return usb2_priv->dwc2_a_addr;
+}
+
+unsigned int usb_get_device_mode_phy_base(void)
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ int ret;
+
+ if (!usb_phys[0].dev) {
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ return usb2_priv->usb_phy2_pll_base_addr[1];
+}
+
+void usb_phy_tuning_reset(void)
+{
+ unsigned long phy_reg_base = usb_get_device_mode_phy_base();
+ int rev_type;
+
+ if (phy_reg_base == 0)
+ return;
+ rev_type = phy_aml_usb2_get_rev_type();
+
+ if (rev_type)
+ return;
+
+ (*(volatile uint32_t *)(phy_reg_base + 0x38)) = USB2_PHY_PLL_OFFSET_38_CLEAR;
+ (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB2_PHY_PLL_OFFSET_34;
+}
+
+void usb_device_mode_init(void){
+ int ret;
+ u2p_aml_regs_t * u2p_aml_regs;
+ usb_aml_regs_t *usb_aml_regs;
+ struct phy_aml_usb2_priv *usb2_priv;
+ struct phy_aml_usb3_priv *usb3_priv;
+ unsigned int phy_base_addr;
+
+ phy_aml_usb2_check_rev();
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return;
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ usb3_priv = dev_get_priv(usb_phys[1].dev);
+ if (!usb2_priv || !usb3_priv) {
+ printf("get usb phy address from dts failed\n");
+ return;
+ }
+
+ u2p_aml_regs = (u2p_aml_regs_t * )((unsigned long)(usb2_priv->base_addr + PHY_REGISTER_SIZE));
+ usb_aml_regs = (usb_aml_regs_t * )((ulong)usb3_priv->base_addr);
+ phy_base_addr = usb2_priv->usb_phy2_pll_base_addr[1];
+ unsigned int reset_addr;
+ reset_addr = usb2_priv->reset_addr;
+
+ printf("PHY2=0x%p,PHY3=0x%p\n", u2p_aml_regs, usb_aml_regs);
+ if ((*(volatile uint32_t *)(unsigned long)(phy_base_addr + 0x38)) != 0) {
+ usb_phy_tuning_reset();
+ mdelay(150);
+ }
+
+ //step 1: usb controller reset
+ usb_reset(reset_addr, USB_RESET_BIT);
+ u2p_r0_t dev_u2p_r0;
+ u2p_r1_t dev_u2p_r1;
+
+ usb_r0_t dev_usb_r0;
+ usb_r4_t dev_usb_r4;
+ // step 3: enable usb INT internal USB
+ dev_usb_r0.d32 = usb_aml_regs->usb_r0;
+ dev_usb_r0.b.u2d_ss_scaledown_mode = 0;
+ dev_usb_r0.b.u2d_act = 1;
+ usb_aml_regs->usb_r0 = dev_usb_r0.d32;
+
+ // step 4: disable usb phy sleep
+ dev_usb_r4.d32 = usb_aml_regs->usb_r4;
+ dev_usb_r4.b.p21_SLEEPM0 = 1;
+ usb_aml_regs->usb_r4 = dev_usb_r4.d32;
+
+ // step 5: config phy21 device mode
+ dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0;
+ dev_u2p_r0.b.host_device= 0;
+ dev_u2p_r0.b.POR= 0;
+ u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32;
+
+ udelay(10);
+ //step 6: phy21 reset
+ usb_reset(reset_addr, PHY21_RESET_LEVEL_BIT);
+ udelay(50);
+
+ // step 6: wait for phy ready
+ dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
+ int cnt = 0;
+ while ((dev_u2p_r1.d32 & 0x00000001) != 1) {
+ dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
+ if (cnt > 200)
+ break;
+ else {
+ cnt++;
+ udelay(5);
+ }
+ }
+
+ //set_usb_phy21_pll();
+ set_usb_pll(phy_base_addr);
+ //--------------------------------------------------
+
+ // ------------- usb phy21 initinal end ----------
+
+ //--------------------------------------------------
+
+}
+
diff --git a/arch/arm/mach-meson/g12b/watchdog.c b/arch/arm/mach-meson/g12b/watchdog.c
deleted file mode 100644
index fcbb8bc..0000000
--- a/arch/arm/mach-meson/g12b/watchdog.c
+++ /dev/null
@@ -1,106 +0,0 @@
-
-/*
- * arch/arm/cpu/armv8/txl/watchdog.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <asm/types.h>
-#include <asm/arch/romboot.h>
-#include <asm/arch/watchdog.h>
-#include <asm/arch/io.h>
-#include <asm/arch/timer.h>
-
-void watchdog_init(uint32_t msec)
-{
- // src: 24MHz
- // div: 24000 for 1ms
- // reset ao-22 and ee-21
- *P_WATCHDOG_CNTL = (1<<24)|(1<<25)|(1<<22)|(1<<21)|(24000-1);
-
- // set timeout
- *P_WATCHDOG_TCNT = msec;
- *P_WATCHDOG_RESET = 0;
-
- // enable
- *P_WATCHDOG_CNTL |= (1<<18);
-}
-
-void watchdog_reset(void)
-{
- *P_WATCHDOG_RESET = 0;
-}
-
-void watchdog_disable(void)
-{
- // turn off internal counter and disable
- *P_WATCHDOG_CNTL &= ~((1<<18)|(1<<25));
-}
-
-/*
- *GPIOE_0 VDDEE_PWM
- *GPIOE_1 VDDCPU_PWM_B
- *GPIOE_2 VDDCPU_PWM_A
- * */
-void set_pwm_to_input(void)
-{
- unsigned int val;
-
- val = readl(AO_RTI_PINMUX_REG1);
- val &= ~(0xfff << 16);
- writel(val, AO_RTI_PINMUX_REG1);/* clear pinmux */
- val = readl(AO_GPIO_O_EN_N);
- val &= ~(0x7 << 16);
- val |= 0x7 << 16;
- writel(val, AO_GPIO_O_EN_N);/* set input mode */
- val = readl(AO_RTI_PULL_UP_EN_REG);
- val &= ~(0x7 << 16);
- writel(val, AO_RTI_PULL_UP_EN_REG);/* disable pull up/down */
-}
-
-void reset_system(void)
-{
- int i;
-
-#ifdef CONFIG_USB_DEVICE_V2
- *P_RESET1_REGISTER |= (1<<17);
- mdelay(200);
-#endif
-
- set_pwm_to_input();
- _udelay(10000); //wait print
- while (1) {
- writel( 0x3 | (1 << 21) // sys reset en
- | (1 << 23) // interrupt en
- | (1 << 24) // clk en
- | (1 << 25) // clk div en
- | (1 << 26) // sys reset now
- , P_WATCHDOG_CNTL);
- writel(0, P_WATCHDOG_RESET);
-
- writel(readl(P_WATCHDOG_CNTL) | (1<<18), // watchdog en
- P_WATCHDOG_CNTL);
- for (i=0; i<100; i++)
- readl(P_WATCHDOG_CNTL);/*Deceive gcc for waiting some cycles */
- }
-}
-
-/* uboot reset interface */
-void reset_cpu(unsigned long flag){
- reset_system();
-}
diff --git a/arch/arm/mach-meson/hard_sha2.c b/arch/arm/mach-meson/hard_sha2.c
new file mode 100644
index 0000000..782cc8b
--- /dev/null
+++ b/arch/arm/mach-meson/hard_sha2.c
@@ -0,0 +1,261 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <stdio.h>
+#include <string.h>
+#include <dma.h>
+#include <asm/arch/regs.h>
+#include <asm/arch/secure_apb.h>
+#include <u-boot/sha256.h>
+
+#ifndef __AP_DMA_H__
+#define __AP_DMA_H__
+
+typedef struct dma_dsc {
+ union {
+ uint32_t d32;
+ struct {
+ unsigned length:17;
+ unsigned irq:1;
+ unsigned eoc:1;
+ unsigned loop:1;
+ unsigned mode:4;
+ unsigned begin:1;
+ unsigned end:1;
+ unsigned op_mode:2;
+ unsigned enc_sha_only:1;
+ unsigned block:1;
+ unsigned error:1;
+ unsigned owner:1;
+ } b;
+ } dsc_cfg;
+ uint32_t src_addr;
+ uint32_t tgt_addr;
+} dma_dsc_t;
+
+#endif /* __AP_DMA_H__ */
+
+static sha2_ctx *cur_ctx;
+
+static void hw_init(uint32_t is224)
+{
+ cur_ctx->digest_len = is224 ? 224 : 256;
+ cur_ctx->tot_len = 0;
+}
+
+static void hw_update(const uint8_t *input, uint32_t ilen,
+ uint8_t *hash, uint8_t last_update)
+{
+ dma_dsc_t dsc;
+ unsigned char szTempSHA2[64];
+
+ if (!last_update && (ilen % 64))
+ {
+ serial_puts("Err:sha5\n");
+ // sha2 usage problem
+ return;
+ }
+
+ struct {
+ unsigned long lSource;
+ unsigned long lTarget;
+ unsigned int nLength;
+ unsigned int nBlkFlag;
+ }arrSteps[2];
+
+ unsigned int index = 0;
+ memset((void *)arrSteps, 0, sizeof(arrSteps));
+
+ arrSteps[0].lSource = (unsigned long)input;
+ arrSteps[0].lTarget = (unsigned long)hash;
+ arrSteps[1].lTarget = (unsigned long)szTempSHA2;
+
+ int nStep_len = (128<<10) - 64; //17bit length
+ /*If input length bigger than (128KB - 64bytes),default use block mode is 1. */
+
+ if (ilen > nStep_len)
+ {
+ arrSteps[0].nLength = ilen >> 9;
+ arrSteps[0].nBlkFlag = 1;
+ arrSteps[1].lSource = arrSteps[0].lSource + (arrSteps[0].nLength << 9);
+ arrSteps[1].nLength = ilen % 512;
+ arrSteps[1].nBlkFlag = 0;
+ }
+ else
+ {
+ arrSteps[0].nLength = ilen;
+ arrSteps[0].nBlkFlag = 0;
+ }
+
+ for (index = 0; index < sizeof(arrSteps) / sizeof(arrSteps[0]); index++)
+ {
+ dsc.src_addr = arrSteps[index].lSource;
+ dsc.tgt_addr = arrSteps[index].lTarget;
+ dsc.dsc_cfg.d32 = 0;
+ dsc.dsc_cfg.b.length = arrSteps[index].nLength;
+ dsc.dsc_cfg.b.enc_sha_only = 1;
+ dsc.dsc_cfg.b.mode = cur_ctx->digest_len == 224 ? 7 : 6;
+ dsc.dsc_cfg.b.begin = cur_ctx->tot_len == 0; // first
+ dsc.dsc_cfg.b.end = last_update;
+ dsc.dsc_cfg.b.eoc = 1;
+ dsc.dsc_cfg.b.owner = 1;
+ dsc.dsc_cfg.b.block = arrSteps[index].nBlkFlag;
+
+ flush_dcache_range((unsigned long)&dsc,(unsigned long)&dsc+sizeof(dsc));
+ invalidate_dcache_range((unsigned long)dsc.tgt_addr,(unsigned long)dsc.tgt_addr + 32);
+
+ *P_DMA_STS0 = 0xf;
+ *P_DMA_T0 = (uint64_t)&dsc | 2;
+
+ if (arrSteps[index].nBlkFlag)
+ {
+ cur_ctx->tot_len += arrSteps[index].nLength << 9;
+ }
+ else
+ cur_ctx->tot_len += arrSteps[index].nLength;
+
+ while (*P_DMA_STS0 == 0);
+
+ if (!dsc.dsc_cfg.b.block)
+ return;
+ }
+}
+
+static void SHA2_HW_init(sha2_ctx *ctx, uint32_t digest_len)
+{
+ if (cur_ctx != NULL) {
+ serial_puts("Err:sha4\n");
+ // sha2 usage problem
+ return;
+ }
+ cur_ctx = ctx;
+
+ hw_init(digest_len == 224);
+
+ ctx->len = 0;
+}
+
+static void SHA2_HW_update(sha2_ctx *ctx, const uint8_t *data, uint32_t len)
+{
+
+ unsigned int fill_len, data_len, rem_len,offset;
+
+ if (cur_ctx != ctx) {
+ serial_puts("Err:sha3\n");
+ // sha2 usage problem
+ return;
+ }
+ /* This method updates the hash for the input data in blocks, except the last
+ * partial|full block, which is saved in ctx->block. The last partial|full
+ * block will be added to the hash in SHA2_final.
+ */
+ data_len = len;
+ offset = 0;
+ /* fill saved block from beginning of input data */
+ if (ctx->len) {
+ fill_len = SHA256_BLOCK_SIZE - ctx->len;
+ memcpy(&ctx->block[ctx->len], data, fill_len);
+ flush_dcache_range((unsigned long)ctx->block,(unsigned long)ctx->block+128);
+ data_len -= fill_len;
+ offset = fill_len;
+ ctx->len += fill_len;
+ }
+ if (ctx->len == SHA256_BLOCK_SIZE && data_len > 0) {
+ /* saved block is full and is not last block, hash it */
+ hw_update(ctx->block, SHA256_BLOCK_SIZE,ctx->buf, 0);
+ ctx->len = 0;
+ }
+ if (data_len > SHA256_BLOCK_SIZE) {
+ /* still have more than 1 block. hash up until last [partial|full] block */
+ rem_len = data_len % SHA256_BLOCK_SIZE;
+
+ if (rem_len == 0) {
+ rem_len = SHA256_BLOCK_SIZE;
+ }
+
+ data_len -= rem_len;
+ hw_update(&data[offset], data_len,ctx->buf, 0);
+ offset += data_len;
+ } else {
+ rem_len = data_len;
+ }
+ if (rem_len) {
+ /* save the remaining data */
+ memcpy(ctx->block, &data[offset], rem_len);
+ flush_dcache_range((unsigned long)ctx->block,(unsigned long)ctx->block+128);
+ ctx->len = rem_len;
+ }
+}
+
+static uint8_t *SHA2_HW_final(sha2_ctx *ctx)
+{
+ if (cur_ctx != ctx) {
+ serial_puts("Err:sha1\n");
+ // sha2 usage problem
+ return ctx->buf;
+ }
+ if (ctx->len == 0 || ctx->len > SHA256_BLOCK_SIZE) {
+ serial_puts("Err:sha2\n");
+ // internal sha2 problem
+ return ctx->buf;
+ }
+
+ hw_update(ctx->block, ctx->len,ctx->buf, 1);
+ cur_ctx = NULL;
+ return ctx->buf;
+}
+
+ void sha256_starts(sha256_context * ctx)
+{
+ if (ctx)
+ memset(ctx,0,sizeof(sha256_context));
+ SHA2_HW_init(ctx, 256);
+}
+
+ void sha256_update(sha256_context *ctx, const uint8_t *input, uint32_t length)
+{
+ int nOffset = 0;
+ int nStep = (128<<19); //64MB
+
+ if (length > nStep)
+ {
+ for (;nOffset < length;)
+ {
+ SHA2_HW_update(ctx, input+nOffset, nStep);
+ nOffset+=nStep;
+ if ((length - nOffset ) < nStep)
+ nStep = length - nOffset;
+ }
+ }
+ else
+ {
+ SHA2_HW_update(ctx, input, length);
+ }
+}
+
+ void sha256_finish(sha256_context * ctx, uint8_t digest[SHA256_SUM_LEN])
+{
+ SHA2_HW_final(ctx);
+ /*before memcpy,must invalidate dcache.so memcpy data from ddr*/
+ invalidate_dcache_range((unsigned long)digest,(unsigned long)(digest+32));
+ invalidate_dcache_range((unsigned long)ctx->buf,(unsigned long)(ctx->buf+32));
+
+ memcpy(digest,ctx->buf,32);
+}
+
+ void sha256_csum_wd(const unsigned char *input, unsigned int ilen,
+ unsigned char *output, unsigned int chunk_sz)
+{
+ flush_dcache_range((unsigned long)input,(unsigned long)input+ilen);
+
+ sha2_ctx sha_ctx;
+
+ sha256_starts(&sha_ctx);
+
+ sha256_update(&sha_ctx, input, ilen);
+
+ sha256_finish(&sha_ctx, output);
+}
diff --git a/arch/arm/mach-meson/s4/Makefile b/arch/arm/mach-meson/s4/Makefile
new file mode 100644
index 0000000..cc7aa5d
--- /dev/null
+++ b/arch/arm/mach-meson/s4/Makefile
@@ -0,0 +1,16 @@
+
+obj-y := sdio.o pinctrl_init.o
+obj-y += bl31_apis.o
+obj-y += cpu_reset.o
+obj-y += timer.o
+obj-y += mailbox.o
+#obj-y += gate_init.o
+#obj-y += power_cal.o
+obj-$(CONFIG_CMD_PLLTEST) += pll.o
+obj-$(CONFIG_CMD_AML_MTEST) += core.o
+obj-y += usb.o
+obj-$(CONFIG_AML_TSENSOR) += tsensor.o
+obj-$(CONFIG_AML_OSCRING) += oscring.o
+obj-$(CONFIG_AML_HDMITX20) += hdmitx_hw.o hdmitx_clk.o
+obj-y += aml_efuse.o
+obj-$(CONFIG_SECURE_POWER_CONTROL) += pwrc.o
diff --git a/arch/arm/mach-meson/s4/aml_efuse.c b/arch/arm/mach-meson/s4/aml_efuse.c
new file mode 100644
index 0000000..f108dc9
--- /dev/null
+++ b/arch/arm/mach-meson/s4/aml_efuse.c
@@ -0,0 +1,122 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ *
+ * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
+*/
+
+#include <common.h>
+#include <asm/arch/io.h>
+#include <amlogic/aml_efuse.h>
+#include <asm/arch/secure_apb.h>
+
+/*load license bit [0...127...255...511]*/
+#define OTP_BIT_LOAD(feat) (readl(OTP_LIC00 + (((feat)/32)<<2)) & (1<<((feat)%32)))
+
+#define FEAT_ENABLE_DEVICE_SCS_SIG_0 (10)
+#define FEAT_ENABLE_DEVICE_SCS_SIG_1 (11)
+#define IS_FEAT_EN_DEVICE_SCS_SIG() \
+ ((OTP_BIT_LOAD(FEAT_ENABLE_DEVICE_SCS_SIG_0) || \
+ OTP_BIT_LOAD(FEAT_ENABLE_DEVICE_SCS_SIG_1)) ? 1 : 0)
+/*check license bit*/
+#define OTP_BIT_CHECK(feat) (OTP_BIT_LOAD((feat)) ? 1 : 0)
+
+/* OTP_LIC block#0 ...*/
+#define FEAT_DISABLE_CHIPSET_ROOTCERT_0 (4)
+#define FEAT_DISABLE_NORMAL_DEVICE_ROOTCERT_0 (12)
+#define FEAT_DISABLE_DFU_DEVICE_ROOTCERT_0 (28)
+
+/* OTP_LIC block#3 ...*/
+#define FEAT_DISABLE_NBL2_SNOR (384+44)
+#define FEAT_DISABLE_NBL2_SNAND (384+45)
+#define FEAT_ENABLE_4BL2_SNOR (384+46)
+#define FEAT_ENABLE_8BL2_SNAND (384+47)
+#define FEAT_DISABLE_EMMC_USER (384+53)
+#define FEAT_DISABLE_EMMC_BOOT_0 (384+54)
+#define FEAT_DISABLE_EMMC_BOOT_1 (384+55)
+#define FEAT_DISABLE_NBL2_NAND (384+57)
+#define FEAT_DISABLE_8BL2_NAND (384+58)
+
+//function for EFUSE license query
+int IS_FEAT_BOOT_VERIFY(void)
+{
+ return IS_FEAT_EN_DEVICE_SCS_SIG();
+}
+
+int IS_FEAT_DIS_EMMC_USER(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_EMMC_USER);
+}
+
+int IS_FEAT_DIS_EMMC_BOOT_0(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_EMMC_BOOT_0);
+}
+
+int IS_FEAT_DIS_EMMC_BOOT_1(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_EMMC_BOOT_1);
+}
+
+int IS_FEAT_EN_4BL2_SNOR(void)
+{
+ return OTP_BIT_CHECK(FEAT_ENABLE_4BL2_SNOR);
+}
+
+int IS_FEAT_DIS_NBL2_SNOR(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_NBL2_SNOR);
+}
+
+int IS_FEAT_EN_8BL2_SNAND(void)
+{
+ return OTP_BIT_CHECK(FEAT_ENABLE_8BL2_SNAND);
+}
+
+int IS_FEAT_DIS_NBL2_SNAND(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_NBL2_SNAND);
+}
+
+int IS_FEAT_DIS_8BL2_NAND(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_8BL2_NAND);
+}
+
+int IS_FEAT_DIS_NBL2_NAND(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_NBL2_NAND);
+}
+
+int IS_FEAT_DIS_CHIPSET_ROOTCERT_0(void)
+{
+ // Do double-read to prevent hardware glitch attack
+ if (OTP_BIT_CHECK(FEAT_DISABLE_CHIPSET_ROOTCERT_0))
+ return 1;
+ if (OTP_BIT_CHECK(FEAT_DISABLE_CHIPSET_ROOTCERT_0) == 0)
+ return 0;
+ return 1;
+}
+
+int IS_FEAT_DIS_NORMAL_DEVICE_ROOTCERT_0(void)
+{
+ // Do double-read to prevent hardware glitch attack
+ if (OTP_BIT_CHECK(FEAT_DISABLE_NORMAL_DEVICE_ROOTCERT_0))
+ return 1;
+ if (OTP_BIT_CHECK(FEAT_DISABLE_NORMAL_DEVICE_ROOTCERT_0) == 0)
+ return 0;
+ return 1;
+}
+
+int IS_FEAT_DIS_DFU_DEVICE_ROOTCERT_0(void)
+{
+ // Do double-read to prevent hardware glitch attack
+ if (OTP_BIT_CHECK(FEAT_DISABLE_DFU_DEVICE_ROOTCERT_0))
+ return 1;
+ if (OTP_BIT_CHECK(FEAT_DISABLE_DFU_DEVICE_ROOTCERT_0) == 0)
+ return 0;
+ return 1;
+}
diff --git a/arch/arm/mach-meson/s4/bl31_apis.c b/arch/arm/mach-meson/s4/bl31_apis.c
new file mode 100644
index 0000000..9bbc004
--- /dev/null
+++ b/arch/arm/mach-meson/s4/bl31_apis.c
@@ -0,0 +1,578 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ * Trustzone API
+ */
+
+#include <asm/arch/io.h>
+#include <asm/arch/efuse.h>
+#include <asm/cache.h>
+#include <asm/arch/bl31_apis.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+
+static long sharemem_input_base;
+static long sharemem_output_base;
+
+long get_sharemem_info(unsigned long function_id)
+{
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ : "+r" (function_id));
+
+ return function_id;
+}
+
+int32_t set_boot_params(const keymaster_boot_params *boot_params)
+{
+ const unsigned cmd = SET_BOOT_PARAMS;
+
+ if (!boot_params)
+ return -1;
+
+ if (!sharemem_input_base)
+ sharemem_input_base =
+ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE);
+
+ memcpy((void *)sharemem_input_base,
+ (const void *)boot_params, sizeof(keymaster_boot_params));
+
+ asm __volatile__("" : : : "memory");
+ register uint64_t x0 asm("x0") = cmd;
+ register uint64_t x1 asm("x1") = sizeof(keymaster_boot_params);
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1));
+ } while (0);
+
+ return (!x0)? -1: 0;
+}
+
+#ifdef CONFIG_EFUSE
+int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg)
+{
+ int ret;
+ unsigned cmd, offset, size;
+ unsigned long *retcnt = (unsigned long *)(arg->retcnt_phy);
+
+ if (!sharemem_input_base)
+ sharemem_input_base =
+ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE);
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ if (arg->cmd == EFUSE_HAL_API_READ)
+ cmd = EFUSE_READ;
+ else if (arg->cmd == EFUSE_HAL_API_WRITE)
+ cmd = EFUSE_WRITE;
+ else
+ cmd = EFUSE_WRITE_PATTERN;
+ offset = arg->offset;
+ size = arg->size;
+
+ if (arg->cmd == EFUSE_HAL_API_WRITE)
+ memcpy((void *)sharemem_input_base,
+ (const void *)arg->buffer_phy, size);
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = cmd;
+ register uint64_t x1 asm("x1") = offset;
+ register uint64_t x2 asm("x2") = size;
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2));
+ } while (0);
+ ret = x0;
+ *retcnt = x0;
+
+ if ((arg->cmd == EFUSE_HAL_API_READ) && (ret != 0))
+ memcpy((void *)arg->buffer_phy,
+ (const void *)sharemem_output_base, ret);
+
+ if (!ret)
+ return -1;
+ else
+ return 0;
+}
+
+int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg)
+{
+ int32_t ret;
+ unsigned cmd = 0;
+
+ if (arg->cmd == EFUSE_HAL_API_USER_MAX)
+ cmd = EFUSE_USER_MAX;
+
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = cmd;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0));
+ } while (0);
+ ret = x0;
+
+ if (!ret)
+ return -1;
+ else
+ return ret;
+}
+
+ssize_t meson_trustzone_efuse_writepattern(const char *buf, size_t count)
+{
+ struct efuse_hal_api_arg arg;
+ unsigned long retcnt;
+
+ if (count != EFUSE_BYTES)
+ return 0; /* Past EOF */
+
+ arg.cmd = EFUSE_HAL_API_WRITE_PATTERN;
+ arg.offset = 0;
+ arg.size = count;
+ arg.buffer_phy = (unsigned long)buf;
+ arg.retcnt_phy = (unsigned long)&retcnt;
+ int ret;
+ ret = meson_trustzone_efuse(&arg);
+ return ret;
+}
+#endif
+
+uint64_t meson_trustzone_efuse_check(unsigned char *addr)
+{
+ uint64_t ret = 0;
+ struct sram_hal_api_arg arg = {};
+
+ arg.cmd = SRAM_HAL_API_CHECK_EFUSE;
+ arg.req_len = 0x1000000;
+ arg.res_len = 0;
+ arg.req_phy_addr = (unsigned long)addr;
+ arg.res_phy_addr = (unsigned long)NULL;
+
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = CALL_TRUSTZONE_HAL_API;
+ register uint64_t x1 asm("x1") = TRUSTZONE_HAL_API_SRAM;
+ register uint64_t x2 asm("x2") = (unsigned long)(&arg);
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2));
+ } while (0);
+
+ ret = x0;
+
+ return ret;
+}
+
+void debug_efuse_cmd(unsigned long cmd)
+{
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ : : "r" (cmd));
+}
+
+void bl31_debug_efuse_write_pattern(const char *buf)
+{
+ if (!sharemem_input_base)
+ sharemem_input_base =
+ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE);
+ memcpy((void *)sharemem_input_base, (const void *)buf, 512);
+
+ debug_efuse_cmd(DEBUG_EFUSE_WRITE_PATTERN);
+}
+
+void bl31_debug_efuse_read_pattern(char *buf)
+{
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+ debug_efuse_cmd(DEBUG_EFUSE_READ_PATTERN);
+
+ memcpy((void *)buf, (const void *)sharemem_output_base, 512);
+}
+
+void aml_set_jtag_state(unsigned state, unsigned select)
+{
+ uint64_t command;
+ if (state == JTAG_STATE_ON)
+ command = JTAG_ON;
+ else
+ command = JTAG_OFF;
+ asm __volatile__("" : : : "memory");
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : : "r" (command), "r"(select));
+}
+
+void wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value)
+{
+ register long x0 asm("x0") = 0x82000086;
+ register long x1 asm("x1") = cmd;
+ register long x2 asm("x2") = value;
+ register long x3 asm("x3") = 0;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+}
+
+unsigned aml_get_reboot_reason(void)
+{
+ unsigned reason;
+ uint64_t ret;
+
+ register uint64_t x0 asm("x0") = GET_REBOOT_REASON;
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ :"+r"(x0));
+ ret = x0;
+ reason = (unsigned)(ret&0xffffffff);
+ return reason;
+}
+
+void set_viu_probe_enable(void)
+{
+ register uint64_t x0 asm("x0") = VIU_PREOBE_EN;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ :"+r"(x0));
+}
+
+void power_set_dsp(unsigned int id, unsigned int powerflag)
+{
+ register long x0 asm("x0") = DSP_SEC_POWERSET;
+ register long x1 asm("x1") = id;
+ register long x2 asm("x2") = powerflag;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2));
+}
+
+void init_dsp(unsigned int id,unsigned int addr,unsigned int cfg0)
+{
+ register long x0 asm("x0") = START_HIFI4;
+ register long x1 asm("x1") = id;
+ register long x2 asm("x2") = addr;
+ register long x3 asm("x3") = cfg0;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+}
+
+
+unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2)
+{
+ register long x0 asm("x0") = function_id;
+ register long x1 asm("x1") = arg0;
+ register long x2 asm("x2") = arg1;
+ register long x3 asm("x3") = arg2;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+
+ return function_id;
+}
+
+/* clear boot sequence related registers */
+void aml_set_bootsequence(uint32_t val)
+{
+ register long x0 asm("x0") = SET_STORAGE_BOOTSEQUENCE;
+ register long x1 asm("x1") = val;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ :"+r"(x0)
+ : "r" (x1));
+
+ return;
+}
+
+void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2)
+{
+ register long x0 asm("x0") = function_id;
+ register long x1 asm("x1") = arg0;
+ register long x2 asm("x2") = arg1;
+ register long x3 asm("x3") = arg2;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+
+ return ;
+}
+
+unsigned long aml_sec_boot_check(unsigned long nType,
+ unsigned long pBuffer,
+ unsigned long nLength,
+ unsigned long nOption)
+{
+ uint64_t ret = 1;
+
+//#define AML_SECURE_LOG_TE
+
+#if defined(AML_SECURE_LOG_TE)
+ #define AML_GET_TE(a) do{a = *((volatile unsigned int*)0xc1109988);}while(0);
+ unsigned nT1,nT2,nT3;
+#else
+ #define AML_GET_TE(...)
+#endif
+
+ AML_GET_TE(nT1);
+
+ switch (nType) {
+ case AML_D_P_W_EFUSE_AMLOGIC:
+ case AML_D_P_W_EFUSE_SECURE_BOOT:
+ break;
+ default:
+ return 0;
+ }
+
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = AML_DATA_PROCESS;
+ register uint64_t x1 asm("x1") = nType;
+ register uint64_t x2 asm("x2") = pBuffer;
+ register uint64_t x3 asm("x3") = nLength;
+ register uint64_t x4 asm("x4") = nOption;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ __asmeq("%4", "x3")
+ __asmeq("%5", "x4")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2),"r"(x3),"r"(x4));
+ } while (0);
+
+ ret = x0;
+
+ AML_GET_TE(nT2);;
+
+ flush_dcache_range((unsigned long )pBuffer, (unsigned long )pBuffer+nLength);
+
+ AML_GET_TE(nT3);
+
+#if defined(AML_SECURE_LOG_TE)
+ printf("aml log : dec use %d(us) , flush cache used %d(us)\n",
+ nT2 - nT1, nT3 - nT2);
+#endif
+
+ return ret;
+}
+
+void set_usb_boot_function(unsigned long command)
+{
+ register long x0 asm("x0") = SET_USB_BOOT_FUNC;
+ register long x1 asm("x1") = command;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+}
+
+void set_boot_first_timeout(uint64_t arg0)
+{
+ register long x0 asm("x0") = SET_BOOT_FIRST;
+ register long x1 asm("x1") = arg0;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+}
+void aml_system_off(void)
+{
+ /* TODO: Add poweroff capability */
+ aml_reboot(0x82000042, 1, 0, 0);
+ aml_reboot(0x84000008, 0, 0, 0);
+}
+
+int __get_chip_id(unsigned char *buff, unsigned int size)
+{
+ if (buff == NULL || size < 16)
+ return -1;
+
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ if (sharemem_output_base) {
+ register long x0 asm("x0") = GET_CHIP_ID;
+ register long x1 asm("x1") = 2;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+
+ if (x0 == 0) {
+ int version = *((unsigned int *)sharemem_output_base);
+
+ if (version == 2) {
+ memcpy(buff, (void *)sharemem_output_base + 4, 16);
+ }
+ else {
+ /**
+ * Legacy 12-byte chip ID read out, transform data
+ * to expected order format.
+ */
+ uint32_t chip_info = 0;//readl(P_AO_SEC_SD_CFG8);
+ uint8_t *ch;
+ int i;
+
+ ((uint32_t *)buff)[0] =
+ ((chip_info & 0xff000000) | // Family ID
+ ((chip_info << 8) & 0xff0000) | // Chip Revision
+ ((chip_info >> 8) & 0xff00)); // Package ID
+
+ ((uint32_t *)buff)[0] = htonl(((uint32_t *)buff)[0]);
+
+ /* Transform into expected order for display */
+ ch = (uint8_t *)(sharemem_output_base + 4);
+ for (i = 0; i < 12; i++)
+ buff[i + 4] = ch[11 - i];
+ }
+
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
+int bl31_get_cornerinfo(uint8_t *outbuf, int size)
+{
+ int buff_len = 0;
+
+ if (outbuf == NULL) {
+ printf("BL33: corner efuse info storebuf is NULL\n");
+ return -1;
+ }
+
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ if (sharemem_output_base) {
+ register long x0 asm("x0") = OSCRING_EFUSE_GET;
+ register long x1 asm("x1") = size;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+ } while(0);
+ buff_len = x0;
+ if (buff_len <= size) {
+ memcpy(outbuf, (void *)sharemem_output_base, buff_len);
+ return 0;
+ } else {
+ printf("BL33: corner efuse info buf len %d over storebuf size %d\n", buff_len, size);
+ return -1;
+ }
+ }
+ return -1;
+}
+
+int32_t get_avbkey_from_fip(uint8_t *buf, uint32_t buflen)
+{
+ const unsigned cmd = GET_AVBKEY_FROM_FIP;
+ uint32_t retlen = 0;
+ uint32_t ret = 0;
+
+ if (!buf)
+ return -1;
+
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ asm __volatile__("" : : : "memory");
+ register uint64_t x0 asm("x0") = cmd;
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0));
+ } while (0);
+
+ if (!x0)
+ ret = -1;
+ retlen = x0;
+
+ if (ret != -1 && buflen >= retlen)
+ memcpy(buf, (const void *)sharemem_output_base, retlen);
+
+ return ret;
+}
diff --git a/arch/arm/mach-meson/s4/core.c b/arch/arm/mach-meson/s4/core.c
new file mode 100644
index 0000000..8640828
--- /dev/null
+++ b/arch/arm/mach-meson/s4/core.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/types.h>
+#include <asm/arch/cpu.h>
+#include <common.h>
+
+const unsigned int core_map[] = {
+ 0x0,
+ 0x1,
+ 0x2,
+ 0x3,
+};
+
+int get_core_mpidr(unsigned int cpuid)
+{
+ unsigned int coremax = (unsigned int)(sizeof(core_map)/sizeof(unsigned int));
+
+ if (cpuid >= coremax)
+ return -1;
+ return core_map[cpuid];
+}
+
+int get_core_idx(unsigned int mpidr)
+{
+ unsigned int clusterid, cpuid;
+
+ cpuid = mpidr & 0xff;
+ clusterid = mpidr & 0xff00;
+
+ cpuid += (clusterid >> 6);
+
+ if (cpuid >= NR_CPUS)
+ return -1;
+
+ return cpuid;
+}
+
+int get_core_max(void)
+{
+ return (sizeof(core_map)/sizeof(unsigned int));
+}
diff --git a/arch/arm/mach-meson/s4/cpu_reset.c b/arch/arm/mach-meson/s4/cpu_reset.c
new file mode 100644
index 0000000..ca0a42d
--- /dev/null
+++ b/arch/arm/mach-meson/s4/cpu_reset.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/types.h>
+#include <asm/arch/romboot.h>
+#include <asm/arch/cpu_reset.h>
+#include <asm/arch/io.h>
+#include <asm/arch/timer.h>
+#include <dm.h>
+#include <wdt.h>
+
+/*
+ *GPIOE_0 VDDEE_PWM
+ *GPIOE_1 VDDCPU_PWM
+ * */
+void set_pwm_to_input(void)
+{
+ //hxbao, need fine tune
+ #if 0
+ unsigned int val;
+
+ val = readl(AO_RTI_PINMUX_REG1);
+ val &= ~(0xff << 16);
+ writel(val, AO_RTI_PINMUX_REG1);/* clear pinmux */
+ val = readl(AO_GPIO_O_EN_N);
+ val &= ~(0x3 << 16);
+ val |= 0x3 << 16;
+ writel(val, AO_GPIO_O_EN_N);/* set input mode */
+ val = readl(AO_RTI_PULL_UP_EN_REG);
+ val &= ~(0x3 << 16);
+ writel(val, AO_RTI_PULL_UP_EN_REG);/* disable pull up/down */
+ #endif
+}
+
+void reset_system(void)
+{
+ struct udevice *watchdog_devp;
+ int ret;
+
+ set_pwm_to_input();
+
+ _udelay(10000); //wait print
+
+ ret = uclass_get_device_by_name(UCLASS_WDT, "watchdog", &watchdog_devp);
+ if (ret < 0) {
+ printf("failed to reset system because can't get wdt device\n");
+ return;
+ }
+ wdt_start(watchdog_devp, 0, 0);
+ while (1);
+}
+
+/* uboot reset interface */
+void reset_cpu(unsigned long flag){
+ reset_system();
+}
diff --git a/arch/arm/mach-meson/s4/firmware/acs/Makefile b/arch/arm/mach-meson/s4/firmware/acs/Makefile
new file mode 100644
index 0000000..c87e341
--- /dev/null
+++ b/arch/arm/mach-meson/s4/firmware/acs/Makefile
@@ -0,0 +1,439 @@
+#
+# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of ARM nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+#
+# Default values for build configurations
+#
+
+CROSS_COMPILE ?= /opt/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-
+export CROSS_COMPILE
+
+include $(buildsrc)/config.mk
+include $(buildtree)/include/autoconf.mk
+include $(buildtree)/.config
+
+# Build verbosity
+V := 0
+# Debug build
+BUILD_TYPE := ${BL2_BUILD_TYPE}
+# Build architecture
+ARCH := aarch64
+# Build platform
+#DEFAULT_PLAT := gx
+PLAT := ${SOC}
+export PLAT
+# SPD choice
+SPD := none
+# Base commit to perform code check on
+BASE_COMMIT := origin/master
+# NS timer register save and restore
+NS_TIMER_SWITCH := 0
+# By default, Bl1 acts as the reset handler, not BL31
+RESET_TO_BL31 := 0
+
+# Checkpatch ignores
+CHECK_IGNORE = --ignore COMPLEX_MACRO
+
+CHECKPATCH_ARGS = --no-tree --no-signoff ${CHECK_IGNORE}
+CHECKCODE_ARGS = --no-patch --no-tree --no-signoff ${CHECK_IGNORE}
+
+ifeq (${V},0)
+ Q=@
+ CHECKCODE_ARGS += --no-summary --terse
+else
+ Q=
+endif
+export Q
+
+ifeq (${GIT_VERSION},)
+ GIT_VERSION := $(shell git describe --abbrev=7 --dirty --always --tags)
+endif
+ifeq (${BUILDER},)
+ BUILDER := ${USER}@$(shell hostname)
+endif
+
+BL_COMMON_SOURCES := common/bl_common.c \
+ common/debug.c \
+ lib/aarch64/cache_helpers.S \
+ lib/aarch64/misc_helpers.S \
+ lib/aarch64/tlb_helpers.S \
+ lib/aarch64/xlat_helpers.c \
+ lib/stdlib/std.c \
+ lib/io_storage.c \
+ plat/common/aarch64/platform_helpers.S
+
+BUILD_BASE := $(buildtree)/firmware
+#BUILD_PLAT := ${BUILD_BASE}/${PLAT}
+BUILD_PLAT := $(buildtree)/board/${BOARDDIR}/firmware
+#BUILD_PLAT := $(buildtree)/${BOARDDIR}/firmware
+
+# Convenience function for adding build definitions
+# $(eval $(call add_define,FOO)) will have:
+# -DFOO if $(FOO) is empty; -DFOO=$(FOO) otherwise
+define add_define
+DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
+endef
+
+# Convenience function for verifying option has a boolean value
+# $(eval $(call assert_boolean,FOO)) will assert FOO is 0 or 1
+define assert_boolean
+$(and $(patsubst 0,,$(value $(1))),$(patsubst 1,,$(value $(1))),$(error $(1) must be boolean))
+endef
+
+ifeq (${PLAT},)
+ $(error "Error: Unknown platform. Please use PLAT=<platform name> to specify the platform.")
+endif
+
+all: msg_start
+
+msg_start:
+ @echo "Building ${BOARDDIR}/acs.bin"
+
+#include plat/${PLAT}/platform.mk
+#ifdef BL2_SOURCES
+NEED_BL2 := yes
+include acs.mk
+#endif
+
+# Include SPD Makefile if one has been specified
+ifneq (${SPD},none)
+ # We expect to locate an spd.mk under the specified SPD directory
+ SPD_MAKE := $(shell m="services/spd/${SPD}/${SPD}.mk"; [ -f "$$m" ] && echo "$$m")
+
+ ifeq (${SPD_MAKE},)
+ $(error Error: No services/spd/${SPD}/${SPD}.mk located)
+ endif
+ $(info Including ${SPD_MAKE})
+ include ${SPD_MAKE}
+
+ # If there's BL32 companion for the chosen SPD, and the SPD wants to build the
+ # BL2 from source, we expect that the SPD's Makefile would set NEED_BL32
+ # variable to "yes"
+endif
+
+.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool fip
+.SUFFIXES:
+
+INCLUDES += -Iinclude/bl2 \
+ -Iinclude/bl31 \
+ -Iinclude/common \
+ -Iinclude/drivers \
+ -Iinclude/drivers/arm \
+ -Iinclude/drivers/serial \
+ -Iinclude/lib \
+ -Iinclude/lib/aarch64 \
+ -Iinclude/plat/common \
+ -Iinclude/stdlib \
+ -Iinclude/stdlib/sys \
+ ${PLAT_INCLUDES} \
+ ${SPD_INCLUDES}
+
+# Process DEBUG flag
+$(eval $(call assert_boolean,DEBUG))
+$(eval $(call add_define,DEBUG))
+ifeq (${DEBUG},0)
+ $(eval $(call add_define,NDEBUG))
+else
+CFLAGS += -g
+ASFLAGS += -g -Wa,--gdwarf-2
+endif
+
+# Process NS_TIMER_SWITCH flag
+$(eval $(call assert_boolean,NS_TIMER_SWITCH))
+$(eval $(call add_define,NS_TIMER_SWITCH))
+
+# Process RESET_TO_BL31 flag
+$(eval $(call assert_boolean,RESET_TO_BL31))
+$(eval $(call add_define,RESET_TO_BL31))
+
+VPATH_LIST = $(buildsrc)/board/$(BOARDDIR)
+#VPATH_LIST = $(buildsrc)/$(BOARDDIR)
+VPATH_LIST:=$(VPATH_LIST:%=%/firmware/)
+
+vpath %.c $(VPATH_LIST)
+
+ASFLAGS += -nostdinc -ffreestanding -Wa,--fatal-warnings \
+ -mgeneral-regs-only -D__ASSEMBLY__ \
+ ${DEFINES} ${INCLUDES}
+CFLAGS += -nostdinc -pedantic -ffreestanding -Wall \
+ -Werror -mgeneral-regs-only -std=c99 -c -Os \
+ ${DEFINES} ${INCLUDES} $(VPATH_LIST:%=-I%)
+CFLAGS += -ffunction-sections -fdata-sections
+ASFLAGS += ${FIRMWARE_CPPFLAGS}
+CFLAGS += ${FIRMWARE_CPPFLAGS}
+CFLAGS += -Wno-unused
+
+LDFLAGS += --fatal-warnings -O1
+LDFLAGS += --gc-sections
+
+OCFLAGS += -j .dev_header -j .generic_param -j .clk_param \
+ -j .misc_param -j .store_param -j .ddr_param \
+ -j .ddr_2acs_index -j .ddr_2acs_data \
+ --gap-fill 0x0
+
+CC := ${CROSS_COMPILE}gcc
+CPP := ${CROSS_COMPILE}cpp
+AS := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OC := ${CROSS_COMPILE}objcopy
+OD := ${CROSS_COMPILE}objdump
+NM := ${CROSS_COMPILE}nm
+PP := ${CROSS_COMPILE}gcc -E ${CFLAGS}
+
+# Variables for use with Firmware Image Package
+FIPTOOLPATH ?= tools/fip_create
+FIPTOOL ?= ${FIPTOOLPATH}/fip_create
+fiptool: ${FIPTOOL}
+fip: ${BUILD_PLAT}/fip.bin
+
+locate-checkpatch:
+ifndef CHECKPATCH
+ $(error "Please set CHECKPATCH to point to the Linux checkpatch.pl file, eg: CHECKPATCH=../linux/script/checkpatch.pl")
+else
+ifeq (,$(wildcard ${CHECKPATCH}))
+ $(error "The file CHECKPATCH points to cannot be found, use eg: CHECKPATCH=../linux/script/checkpatch.pl")
+endif
+endif
+
+clean:
+ @echo " CLEAN"
+ ${Q}rm -rf ${BUILD_PLAT}
+ ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
+
+realclean distclean:
+ @echo " REALCLEAN"
+ ${Q}rm -rf ${BUILD_BASE}
+ ${Q}rm -f ${CURDIR}/cscope.*
+ ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
+
+checkcodebase: locate-checkpatch
+ @echo " CHECKING STYLE"
+ @if test -d .git ; then \
+ git ls-files | while read GIT_FILE ; do ${CHECKPATCH} ${CHECKCODE_ARGS} -f $$GIT_FILE ; done ; \
+ else \
+ find . -type f -not -iwholename "*.git*" -not -iwholename "*build*" -exec ${CHECKPATCH} ${CHECKCODE_ARGS} -f {} \; ; \
+ fi
+
+checkpatch: locate-checkpatch
+ @echo " CHECKING STYLE"
+ @git format-patch --stdout ${BASE_COMMIT} | ${CHECKPATCH} ${CHECKPATCH_ARGS} - || true
+
+${FIPTOOL}:
+ ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH}
+ @echo
+ @echo "Built $@ successfully"
+ @echo
+
+define match_goals
+$(strip $(foreach goal,$(1),$(filter $(goal),$(MAKECMDGOALS))))
+endef
+
+# List of rules that involve building things
+BUILD_TARGETS := all bl1 bl2 bl31 bl32 fip
+
+# Does the list of goals specified on the command line include a build target?
+ifneq ($(call match_goals,${BUILD_TARGETS}),)
+IS_ANYTHING_TO_BUILD := 1
+endif
+
+define MAKE_C
+
+$(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2))))
+$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ)))
+
+$(OBJ) : $(2)
+ @echo " CC $$<"
+ $$(Q)$$(CC) $$(CFLAGS) -c $$< -o $$@
+
+
+$(PREREQUISITES) : $(2)
+ @echo " DEPS $$@"
+ @mkdir -p $(1)
+ $$(Q)$$(CC) $$(CFLAGS) -M -MT $(OBJ) -MF $$@ $$<
+
+ifdef IS_ANYTHING_TO_BUILD
+-include $(PREREQUISITES)
+endif
+
+endef
+
+
+define MAKE_S
+
+$(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2))))
+$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ)))
+
+$(OBJ) : $(2)
+ @echo " AS $$<"
+ $$(Q)$$(AS) $$(ASFLAGS) -c $$< -o $$@
+
+$(PREREQUISITES) : $(2)
+ @echo " DEPS $$@"
+ @mkdir -p $(1)
+ $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(OBJ) -MF $$@ $$<
+
+ifdef IS_ANYTHING_TO_BUILD
+-include $(PREREQUISITES)
+endif
+
+endef
+
+
+define MAKE_LD
+
+$(eval PREREQUISITES := $(1).d)
+
+$(1) : $(2)
+ @echo " PP $$<"
+ $$(Q)$$(AS) $$(ASFLAGS) -P -E -o $$@ $$<
+
+$(PREREQUISITES) : $(2)
+ @echo " DEPS $$@"
+ @mkdir -p $$(dir $$@)
+ $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(1) -MF $$@ $$<
+
+ifdef IS_ANYTHING_TO_BUILD
+-include $(PREREQUISITES)
+endif
+
+endef
+
+
+define MAKE_OBJS
+ $(eval C_OBJS := $(filter %.c,$(2)))
+ $(eval REMAIN := $(filter-out %.c,$(2)))
+ $(eval $(foreach obj,$(C_OBJS),$(call MAKE_C,$(1),$(obj))))
+
+ $(eval S_OBJS := $(filter %.S,$(REMAIN)))
+ $(eval REMAIN := $(filter-out %.S,$(REMAIN)))
+ $(eval $(foreach obj,$(S_OBJS),$(call MAKE_S,$(1),$(obj))))
+
+ $(and $(REMAIN),$(error Unexpected source files present: $(REMAIN)))
+endef
+
+
+# NOTE: The line continuation '\' is required in the next define otherwise we
+# end up with a line-feed characer at the end of the last c filename.
+# Also bare this issue in mind if extending the list of supported filetypes.
+define SOURCES_TO_OBJS
+ $(notdir $(patsubst %.c,%.o,$(filter %.c,$(1)))) \
+ $(notdir $(patsubst %.S,%.o,$(filter %.S,$(1))))
+endef
+
+define MAKE_BL
+ $(eval BUILD_DIR := ${BUILD_PLAT})
+ $(eval SOURCES := $(SOURCES))
+ $(eval OBJS := $(addprefix $(BUILD_DIR)/,$(call SOURCES_TO_OBJS,$(SOURCES))))
+ $(eval LINKERFILE := $(BUILD_DIR)/acs.ld)
+ $(eval MAPFILE := $(BUILD_DIR)/acs.map)
+ $(eval ELF := $(BUILD_DIR)/acs.elf)
+ $(eval DUMP := $(BUILD_DIR)/acs.dump)
+ $(eval BIN := $(BUILD_DIR)/acs.bin)
+
+ $(eval $(call MAKE_OBJS,$(BUILD_DIR),$(SOURCES)))
+ $(eval $(call MAKE_LD,$(LINKERFILE),$(LINKERFILE_T)))
+
+$(BUILD_DIR) :
+ $$(Q)mkdir -p "$$@"
+
+$(ELF) : $(OBJS) $(LINKERFILE)
+ @echo " LD $$@"
+ @echo 'const char build_message[] = "Built : "__TIME__", "__DATE__". \\nver:${GIT_VERSION} - ${BUILDER}";' | \
+ $$(CC) $$(CFLAGS) -xc - -o $(BUILD_DIR)/build_message.o
+ $$(Q)$$(LD) -o $$@ $$(LDFLAGS) -Map=$(MAPFILE) --script $(LINKERFILE) \
+ $(BUILD_DIR)/build_message.o $(OBJS)
+
+$(DUMP) : $(ELF)
+ @echo " OD $$@"
+ $${Q}$${OD} -D -x $$< > $$@
+
+$(BIN) : $(ELF)
+ @echo " BIN $$@"
+ $$(Q)$$(OC) $$(OCFLAGS) -O binary $$< $$@.tmp
+ @dd if=/dev/zero of=$$@ bs=4096 count=1
+ @dd if=$$@.tmp of=$$@ conv=notrunc && rm -f $$@.tmp
+ @echo
+ @echo "Built $$@ successfully"
+ @echo
+
+.PHONY : bl$(1)
+bl$(1) : $(BUILD_DIR) $(DUMP) $(BIN)
+
+all : bl$(1)
+
+$(eval FIP_DEPS += $(if $2,$(BIN),))
+$(eval FIP_ARGS += $(if $2,--bl$(1) $(BIN),))
+
+endef
+
+ifeq (${NEED_BL2},yes)
+$(eval $(call MAKE_BL,2,in_fip))
+endif
+
+${BUILD_PLAT}/fip.bin: ${FIP_DEPS} ${BL33} ${FIPTOOL}
+ $(if ${BL33},,$(error "To build a FIP, please set BL33 to point to the Normal World binary, eg: BL33=../uefi/FVP_AARCH64_EFI.fd"))
+ ${Q}${FIPTOOL} --dump \
+ ${FIP_ARGS} \
+ --bl33 ${BL33} \
+ $@
+ @echo
+ @echo "Built $@ successfully"
+ @echo
+
+
+cscope:
+ @echo " CSCOPE"
+ ${Q}find ${CURDIR} -name "*.[chsS]" > cscope.files
+ ${Q}cscope -b -q -k
+
+help:
+ @echo "usage: ${MAKE} PLAT=<${HELP_PLATFORMS}> <all|bl1|bl2|bl31|distclean|clean|checkcodebase|checkpatch>"
+ @echo ""
+ @echo "PLAT is used to specify which platform you wish to build."
+ @echo "If no platform is specified, PLAT defaults to: ${DEFAULT_PLAT}"
+ @echo ""
+ @echo "Supported Targets:"
+ @echo " all Build the BL1, BL2 and BL31 binaries"
+ @echo " bl1 Build the BL1 binary"
+ @echo " bl2 Build the BL2 binary"
+ @echo " bl31 Build the BL31 binary"
+ @echo " checkcodebase Check the coding style of the entire source tree"
+ @echo " checkpatch Check the coding style on changes in the current"
+ @echo " branch against BASE_COMMIT (default origin/master)"
+ @echo " clean Clean the build for the selected platform"
+ @echo " cscope Generate cscope index"
+ @echo " distclean Remove all build artifacts for all platforms"
+ @echo " fiptool Build the Firmware Image Package(FIP) creation tool"
+ @echo ""
+ @echo "note: most build targets require PLAT to be set to a specific platform."
+ @echo ""
+ @echo "example: build all targets for the FVP platform:"
+ @echo " CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp all"
diff --git a/arch/arm/mach-meson/s4/firmware/acs/acs.c b/arch/arm/mach-meson/s4/firmware/acs/acs.c
new file mode 100644
index 0000000..f6f58e1
--- /dev/null
+++ b/arch/arm/mach-meson/s4/firmware/acs/acs.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <version.h>
+#include <asm/arch/acs.h>
+#include <asm/arch/timing.h>
+#include "timing.c"
+
+dev_param_hdr_t __param_hdr __attribute__ ((section(".dev_header"))) = {
+ .magic = DEV_PARAM_MAGIC,
+ .version = DEV_PARAM_VERSION,
+
+ .bl2_regs_magic = "bl2r_",
+ .bl2_regs_length = sizeof(__bl2_reg),
+
+ .board_clk_magic = "bclk_",
+ .board_clk_length = sizeof(__board_clk_setting),
+
+ .opt_reg_magic = "ops__",
+ .opt_reg_length = sizeof(__bl2_ops_reg),
+
+ .sto_set_magic = "store",
+ .sto_set_length = sizeof(__store_para),
+
+ .ddr_set_magic = "ddrs_",
+ .ddr_set_length = sizeof(__ddr_setting),
+};
+
diff --git a/arch/arm/mach-meson/s4/firmware/acs/acs.ld.S b/arch/arm/mach-meson/s4/firmware/acs/acs.ld.S
new file mode 100644
index 0000000..5075761
--- /dev/null
+++ b/arch/arm/mach-meson/s4/firmware/acs/acs.ld.S
@@ -0,0 +1,62 @@
+
+OUTPUT_FORMAT("elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(acs_entry)
+
+SECTIONS
+{
+ . = 0x00001000;
+ . = ALIGN(4);
+ .entry : {
+ __RO_START__ = .;
+ *acs_entry.o(.text*)
+ *(.text*)
+ *(.data*)
+ *(.bss*)
+ }
+
+ . = 0x00000000;
+ .dev_header :
+ {
+ *(.dev_header*)
+ }
+
+ . = 0x00000100;
+ .generic_param :
+ {
+ *(.generic_param*)
+ }
+
+ . = 0x0000200;
+ .clk_param :
+ {
+ *(.clk_param*)
+ }
+
+ . = 0x00000300;
+ .misc_param :
+ {
+ *(.misc_param*)
+ }
+
+ . = 0x00000500;
+ .store_param :
+ {
+ *(.store_param*)
+ }
+
+ . = 0x00000600 - 0x40;
+ .ddr_param :
+ {
+ *(.ddr_param*)
+ }
+ .ddr_2acs_index :
+ {
+ *(.ddr_2acs_index*)
+ }
+ .ddr_2acs_data :
+ {
+ *(.ddr_2acs_data*)
+ }
+ ASSERT(. <= 0x00001000, "params image has exceeded its limit.")
+}
diff --git a/arch/arm/mach-meson/s4/firmware/acs/acs.mk b/arch/arm/mach-meson/s4/firmware/acs/acs.mk
new file mode 100644
index 0000000..0c63194
--- /dev/null
+++ b/arch/arm/mach-meson/s4/firmware/acs/acs.mk
@@ -0,0 +1,9 @@
+SOURCES += acs_entry.S
+
+ifdef CONFIG_MDUMP_COMPRESS
+SOURCES += ramdump.c
+endif
+
+SOURCES += acs.c
+
+LINKERFILE_T := acs.ld.S
diff --git a/arch/arm/mach-meson/s4/firmware/acs/acs_entry.S b/arch/arm/mach-meson/s4/firmware/acs/acs_entry.S
new file mode 100644
index 0000000..d15e190
--- /dev/null
+++ b/arch/arm/mach-meson/s4/firmware/acs/acs_entry.S
@@ -0,0 +1,16 @@
+
+ .globl acs_entry
+
+acs_entry:
+ .word __param_hdr
+ .word __bl2_reg
+ .word __board_clk_setting
+ .word __bl2_ops_reg
+ .word __store_para
+ .word __ddr_setting
+ .word __ddr_parameter_reg_index
+ .word __bl2_ddr_reg_data
+ .rept 10
+ .word 0x0
+ .endr
+
diff --git a/arch/arm/mach-meson/s4/firmware/bl21/Makefile b/arch/arm/mach-meson/s4/firmware/bl21/Makefile
new file mode 100644
index 0000000..b6d7d1a
--- /dev/null
+++ b/arch/arm/mach-meson/s4/firmware/bl21/Makefile
@@ -0,0 +1,3 @@
+all:
+ @echo "BL21 no action for A1 "
+
diff --git a/arch/arm/mach-meson/s4/firmware/scp_task/Makefile b/arch/arm/mach-meson/s4/firmware/scp_task/Makefile
new file mode 100644
index 0000000..925690d
--- /dev/null
+++ b/arch/arm/mach-meson/s4/firmware/scp_task/Makefile
@@ -0,0 +1,3 @@
+all:
+ echo "BL301 no action for A1"
+
diff --git a/arch/arm/mach-meson/s4/gate_init.c b/arch/arm/mach-meson/s4/gate_init.c
new file mode 100644
index 0000000..31629f6
--- /dev/null
+++ b/arch/arm/mach-meson/s4/gate_init.c
@@ -0,0 +1,366 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "power_gate.h"
+
+#define SECUREBOOT_FLAG_ADDR 0xc8100228
+
+#ifdef CONFIG_AML_CVBS
+extern unsigned int cvbs_mode;
+#endif
+void ee_gate_off(void)
+{
+ printf("ee_gate_off ...\n");
+ return;
+/* int secureboot = readl(SECUREBOOT_FLAG_ADDR)&(1<<5);*/
+
+#ifdef CONFIG_AML_CVBS
+ unsigned int cvbs_opened = 0;
+#endif
+
+#ifdef CONFIG_AML_CVBS
+ if ((cvbs_mode == 0) || (cvbs_mode == 1))
+ cvbs_opened = 1;
+#endif
+
+ /*
+ //if close , audio maybe have noise
+ CLK_GATE_OFF(AUD);
+ CLK_GATE_OFF(AUD2);
+ CLK_GATE_OFF(AUD_CLK_2);
+ CLK_GATE_OFF(AUD_CLK_3);
+ */
+ CLK_GATE_OFF(AUD_IN);
+ CLK_GATE_OFF(AIU_AUD_MIXER);
+ CLK_GATE_OFF(SANA);
+
+ /*kernel will reopen */
+ CLK_GATE_OFF(CTS_ENCL);
+ /* CLK_GATE_OFF(CTS_ENCT); */
+#if 0 /* HDMITX 480i60hz/576i50hz need this gate */
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0)
+ CLK_GATE_OFF(CTS_ENCI);
+#else
+ CLK_GATE_OFF(CTS_ENCI);
+#endif
+#endif
+ /* CLK_GATE_OFF(CTS_ENCP); */
+
+ /*close cvbs clock*/
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0) {
+ CLK_GATE_OFF(DAC_CLK);
+ CLK_GATE_OFF(CTS_VDAC);
+ }
+#else
+ CLK_GATE_OFF(DAC_CLK);
+ CLK_GATE_OFF(CTS_VDAC);
+#endif
+
+ /* usb clock close */
+ CLK_GATE_OFF(USB0);
+ CLK_GATE_OFF(USB1);
+ //CLK_GATE_OFF(USB_CLK); //g12a no reg
+ CLK_GATE_OFF(MISC_USB0_TO_DDR);
+ CLK_GATE_OFF(MISC_USB1_TO_DDR);
+
+ /* uarts close */
+ CLK_GATE_OFF(UART0);
+ CLK_GATE_OFF(UART1);
+ CLK_GATE_OFF(UART2);
+ CLK_GATE_OFF(UART3);
+
+ CLK_GATE_OFF(VCLK2_VENCP);
+ CLK_GATE_OFF(VCLK2_VENCT);
+ CLK_GATE_OFF(VCLK2_VENCT1);
+ CLK_GATE_OFF(VCLK2_OTHER);
+#if 0 /* HDMITX 480i60hz/576i50hz need HHI_GCLK_OTHER[8][2] */
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0) {
+ CLK_GATE_OFF(VCLK2_VENCI);
+ CLK_GATE_OFF(VCLK2_VENCI1);
+ }
+#else
+ CLK_GATE_OFF(VCLK2_VENCI);
+ CLK_GATE_OFF(VCLK2_VENCI1);
+#endif
+#endif
+ CLK_GATE_OFF(VCLK2_VENCL);
+ CLK_GATE_OFF(VCLK2_OTHER1);
+#if 0 /* HDMITX 480i60hz/576i50hz need HHI_GCLK_OTHER[8][2] */
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0)
+ CLK_GATE_OFF(VCLK2_ENCI);
+#else
+ CLK_GATE_OFF(VCLK2_ENCI);
+#endif
+#endif
+ CLK_GATE_OFF(VCLK2_ENCL);
+ CLK_GATE_OFF(VCLK2_ENCT);
+
+ CLK_GATE_OFF(VDEC_CLK_1);
+ CLK_GATE_OFF(VDEC_CLK_2);
+ CLK_GATE_OFF(VDEC2_CLK_1);
+ CLK_GATE_OFF(VDEC2_CLK_2);
+ CLK_GATE_OFF(HCODEC_CLK_1);
+ CLK_GATE_OFF(HCODEC_CLK_2);
+ /* CLK_GATE_OFF(HEVC_CLK_1 ); */
+ /* CLK_GATE_OFF(HEVC_CLK_2 ); */
+
+ //CLK_GATE_OFF(MMC_A_PCLK); //g12a no reg
+ //CLK_GATE_OFF(MMC_B_PCLK); //g12a no reg
+ //CLK_GATE_OFF(MMC_C_PCLK); //g12a no reg
+
+ CLK_GATE_OFF(LCD_AN_PHY2);
+ CLK_GATE_OFF(LCD_AN_PHY3);
+
+ CLK_GATE_OFF(ETHERNET);
+ //CLK_GATE_OFF(ETH_CLK); //g12a no reg
+
+ CLK_GATE_OFF(GE2D);
+ CLK_GATE_OFF(GEN_CLK);
+ //CLK_GATE_OFF(PCM_MCLK); //g12a no reg
+ //CLK_GATE_OFF(PCM_SCLK); //g12a no reg
+
+
+ CLK_GATE_OFF(HIU_PARSER_TOP);
+
+
+ /* can not off nand_clk */
+ /* CLK_GATE_OFF(NAND_CLK); */
+ /*
+ //HDMI no output
+ CLK_GATE_OFF(VCLK2_VENCP1);
+ CLK_GATE_OFF(VCLK2_ENCP);
+ */
+
+ /*
+ //if OFF, HDMI will report error!
+ CLK_GATE_OFF(HDMI_PCLK);
+ CLK_GATE_OFF(HDMI_PLL_CNTL);
+ CLK_GATE_OFF(HDMITX_CLK);
+ */
+
+ /*
+ //PWM B used for VCCK,PWM D used for VDDEE,ignoring
+ CLK_GATE_OFF(PWM_A_CLK);
+ CLK_GATE_OFF(PWM_B_CLK);
+ CLK_GATE_OFF(PWM_C_CLK);
+ CLK_GATE_OFF(PWM_D_CLK);
+ CLK_GATE_OFF(PWM_E_CLK);
+ CLK_GATE_OFF(PWM_F_CLK);
+ */
+
+
+ /* can not close
+ CLK_GATE_OFF(VPU_CLK_1);
+ CLK_GATE_OFF(VPU_CLK_2);
+ CLK_GATE_OFF(VPU_CLKB);
+ CLK_GATE_OFF(MALI_CLK_1);
+ CLK_GATE_OFF(MALI_CLK_2);
+ CLK_GATE_OFF(ATV_DEMO_VDAC);
+ CLK_GATE_OFF(EMMC_A);
+ CLK_GATE_OFF(EMMC_B);
+ CLK_GATE_OFF(EMMC_C);
+ CLK_GATE_OFF(EMMC_A_CLK);
+ CLK_GATE_OFF(EMMC_B_CLK);
+
+ CLK_GATE_OFF(MSR_CLK);
+ CLK_GATE_OFF(MSR_HS_CLK);
+ CLK_GATE_OFF(32K_CLK);
+ CLK_GATE_OFF(VAPB_CLK_1);
+ CLK_GATE_OFF(VAPB_CLK_2);
+ CLK_GATE_OFF(GIC);
+ CLK_GATE_OFF(I2C_AO); //no close for to use
+ CLK_GATE_OFF(AO_CPU);
+ CLK_GATE_OFF(ASSIST_MISC);
+ CLK_GATE_OFF(HIU_PARSER);
+ CLK_GATE_OFF(PERIPHS_TOP);
+ CLK_GATE_OFF(PL310_CBUS);
+ CLK_GATE_OFF(ISA);
+ CLK_GATE_OFF(SECURE_AHP_APB3);
+ CLK_GATE_OFF(VPU_INTR);
+ CLK_GATE_OFF(MMC_PCLK); //can not close
+ CLK_GATE_OFF(AIU_PCLK);
+ //can not connect pc
+ CLK_GATE_OFF(USB_GENERAL);
+ CLK_GATE_OFF(AHB_DATA_BUS);
+ CLK_GATE_OFF(AHB_CONTROL_BUS);
+ CLK_GATE_OFF(HDMI_INTR_SYNC); //should open
+ //can't suspend @ 2nd time
+ //CLK_GATE_OFF(RESET);
+
+ // close rom
+ //disable this bit will make other cpu can not be booted.
+ //CLK_GATE_OFF(ROM_CLK);
+
+*/
+ /*************************/
+ CLK_GATE_OFF(AHB_ARB0);
+ CLK_GATE_OFF(ASYNC_FIFO);
+ CLK_GATE_OFF(STREAM);
+ CLK_GATE_OFF(RANDOM_NUM_GEN);
+ CLK_GATE_OFF(RANDOM_NUM_GEN1);
+ CLK_GATE_OFF(SMART_CARD_MPEG_DOMAIN);
+ CLK_GATE_OFF(I2C);
+ CLK_GATE_OFF(SPI);
+ CLK_GATE_OFF(SPICC);
+ CLK_GATE_OFF(DOS);
+ CLK_GATE_OFF(SAR_ADC);
+ CLK_GATE_OFF(MISC_DVIN);
+ CLK_GATE_OFF(BT656);
+ CLK_GATE_OFF(BT656_2);
+ CLK_GATE_OFF(PDM);
+
+ /* close AIU */
+ CLK_GATE_OFF(AIU_IEC958);
+ CLK_GATE_OFF(AIU_ICE958_AMCLK);
+
+ CLK_GATE_OFF(AIU_AMCLK_MEASURE);
+ CLK_GATE_OFF(AIU_AIFIFO2);
+ CLK_GATE_OFF(AIU_MIXER_REG);
+ CLK_GATE_OFF(AIU_ADC);
+ CLK_GATE_OFF(AIU_TOP_LEVEL);
+ CLK_GATE_OFF(AIU_AOCLK);
+ CLK_GATE_OFF(AIU_AI_TOP_GLUE);
+ CLK_GATE_OFF(AIU_I2S_OUT);
+
+ CLK_GATE_OFF(ENC480P);
+
+ CLK_GATE_OFF(DEMUX);
+/*
+* EFUSE/BLK_MOV clock gate must be on,
+ kernel storage ops depend on them.
+ it can be reference PD#112732
+*/
+/*
+ if (secureboot) {
+ printf("secure boot ignore [ BLK_MOV, efuse ] clk gate\n");
+ } else {
+ CLK_GATE_OFF(EFUSE);
+ CLK_GATE_OFF(BLK_MOV);
+ }
+*/
+}
+
+void ee_gate_on(void)
+{
+
+ printf("ee_gate_on ...\n");
+
+ /*
+ //if close , audio maybe have noise
+ CLK_GATE_ON(AUD);
+ CLK_GATE_ON(AUD2);
+ CLK_GATE_ON(AUD_CLK_2);
+ CLK_GATE_ON(AUD_CLK_3);
+ */
+ CLK_GATE_ON(AUD_IN);
+ CLK_GATE_ON(AIU_AUD_MIXER);
+ CLK_GATE_ON(SANA);
+
+ /*kernel will reopen */
+ CLK_GATE_ON(CTS_ENCL);
+ /* CLK_GATE_ON(CTS_ENCT); */
+ CLK_GATE_ON(CTS_ENCI);
+ /* CLK_GATE_ON(CTS_ENCP); */
+
+ /*close cvbs clock*/
+ CLK_GATE_ON(DAC_CLK);
+ CLK_GATE_ON(CTS_VDAC);
+
+ /* usb clock close */
+ CLK_GATE_ON(USB0);
+ CLK_GATE_ON(USB1);
+ //CLK_GATE_ON(USB_CLK); //g12a no reg
+ CLK_GATE_ON(MISC_USB0_TO_DDR);
+ CLK_GATE_ON(MISC_USB1_TO_DDR);
+
+ /* uarts close */
+ CLK_GATE_ON(UART0);
+ CLK_GATE_ON(UART1);
+ CLK_GATE_ON(UART2);
+ CLK_GATE_ON(UART3);
+
+ CLK_GATE_ON(VCLK2_VENCP);
+ CLK_GATE_ON(VCLK2_VENCT);
+ CLK_GATE_ON(VCLK2_VENCT1);
+ CLK_GATE_ON(VCLK2_OTHER);
+ CLK_GATE_ON(VCLK2_VENCI);
+ CLK_GATE_ON(VCLK2_VENCI1);
+ CLK_GATE_ON(VCLK2_VENCL);
+ CLK_GATE_ON(VCLK2_OTHER1);
+
+
+ CLK_GATE_ON(VCLK2_ENCI);
+ CLK_GATE_ON(VCLK2_ENCL);
+ CLK_GATE_ON(VCLK2_ENCT);
+
+ CLK_GATE_ON(VDEC_CLK_1);
+ CLK_GATE_ON(VDEC_CLK_2);
+ CLK_GATE_ON(VDEC2_CLK_1);
+ CLK_GATE_ON(VDEC2_CLK_2);
+ CLK_GATE_ON(HCODEC_CLK_1);
+ CLK_GATE_ON(HCODEC_CLK_2);
+ /* CLK_GATE_ON(HEVC_CLK_1 ); */
+ /* CLK_GATE_ON(HEVC_CLK_2 ); */
+
+ //CLK_GATE_ON(MMC_A_PCLK); //g12a no reg
+ //CLK_GATE_ON(MMC_B_PCLK); //g12a no reg
+ //CLK_GATE_ON(MMC_C_PCLK); //g12a no reg
+
+ CLK_GATE_ON(LCD_AN_PHY2);
+ CLK_GATE_ON(LCD_AN_PHY3);
+
+ CLK_GATE_ON(ETHERNET);
+ //CLK_GATE_ON(ETH_CLK); //g12a no reg
+
+ CLK_GATE_ON(GE2D);
+ CLK_GATE_ON(GEN_CLK);
+ //CLK_GATE_ON(PCM_MCLK); //g12a no reg
+ //CLK_GATE_ON(PCM_SCLK); //g12a no reg
+
+
+ CLK_GATE_ON(HIU_PARSER_TOP);
+
+ /*************************/
+ CLK_GATE_ON(AHB_ARB0);
+ CLK_GATE_ON(ASYNC_FIFO);
+ CLK_GATE_ON(STREAM);
+ CLK_GATE_ON(RANDOM_NUM_GEN);
+ CLK_GATE_ON(RANDOM_NUM_GEN1);
+ CLK_GATE_ON(SMART_CARD_MPEG_DOMAIN);
+ CLK_GATE_ON(I2C);
+ CLK_GATE_ON(SPI);
+ CLK_GATE_ON(SPICC);
+ CLK_GATE_ON(DOS);
+ CLK_GATE_ON(SAR_ADC);
+ CLK_GATE_ON(MISC_DVIN);
+ CLK_GATE_ON(BT656);
+ CLK_GATE_ON(BT656_2);
+ CLK_GATE_ON(PDM);
+
+ /* close AIU */
+ CLK_GATE_ON(AIU_IEC958);
+ CLK_GATE_ON(AIU_ICE958_AMCLK);
+
+ CLK_GATE_ON(AIU_AMCLK_MEASURE);
+ CLK_GATE_ON(AIU_AIFIFO2);
+ CLK_GATE_ON(AIU_MIXER_REG);
+ CLK_GATE_ON(AIU_ADC);
+ CLK_GATE_ON(AIU_TOP_LEVEL);
+ CLK_GATE_ON(AIU_AOCLK);
+ CLK_GATE_ON(AIU_AI_TOP_GLUE);
+ CLK_GATE_ON(AIU_I2S_OUT);
+
+ CLK_GATE_ON(ENC480P);
+
+ CLK_GATE_ON(DEMUX);
+
+ CLK_GATE_ON(EFUSE);
+ CLK_GATE_ON(BLK_MOV);
+}
+
diff --git a/arch/arm/mach-meson/s4/gpio.c b/arch/arm/mach-meson/s4/gpio.c
new file mode 100644
index 0000000..7332773
--- /dev/null
+++ b/arch/arm/mach-meson/s4/gpio.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <linux/compiler.h>
+#include <amlogic/aml_gpio.h>
+#include <asm/arch/gpio.h>
+
+struct pin_mux_desc {
+ unsigned char domain;
+ unsigned char reg;
+ unsigned char bit;
+};
+
+#define MUX_AO_DOMAIN 0
+#define MUX_EE_DOMAIN 1
+
+#define PIN_MUX(d, r, b) \
+{ \
+ .domain = d, \
+ .reg = r, \
+ .bit = b, \
+}
+
+#define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
+{ \
+ .name = n, \
+ .first = f, \
+ .last = l, \
+ .regs = { \
+ [REG_PULLEN] = { (0xff634520 + (per<<2)), peb }, \
+ [REG_PULL] = { (0xff6344e8 + (pr<<2)), pb }, \
+ [REG_DIR] = { (0xff634440 + (dr<<2)), db }, \
+ [REG_OUT] = { (0xff634440 + (or<<2)), ob }, \
+ [REG_IN] = { (0xff634440 + (ir<<2)), ib }, \
+ }, \
+ }
+#define AOBANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
+{ \
+ .name = n, \
+ .first = f, \
+ .last = l, \
+ .regs = { \
+ [REG_PULLEN] = { (0xff800024 + (per<<2)), peb }, \
+ [REG_PULL] = { (0xff800024 + (pr<<2)), pb }, \
+ [REG_DIR] = { (0xff800024 + (dr<<2)), db }, \
+ [REG_OUT] = { (0xff800024 + (or<<2)), ob }, \
+ [REG_IN] = { (0xff800024 + (ir<<2)), ib }, \
+ }, \
+ }
+
+static struct pin_mux_desc pin_to_gpio[] = {
+ [GPIOAO(GPIOAO_0)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 0),
+ [GPIOAO(GPIOAO_1)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 4),
+ [GPIOAO(GPIOAO_2)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 8),
+ [GPIOAO(GPIOAO_3)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 12),
+ [GPIOAO(GPIOAO_4)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 16),
+ [GPIOAO(GPIOAO_5)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 20),
+ [GPIOAO(GPIOAO_6)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 24),
+ [GPIOAO(GPIOAO_7)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 28),
+ [GPIOAO(GPIOAO_8)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 0),
+ [GPIOAO(GPIOAO_9)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 4),
+ [GPIOAO(GPIOAO_10)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 8),
+ [GPIOAO(GPIOAO_11)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 12),
+ [GPIOAO(GPIOE_0)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 16),
+ [GPIOAO(GPIOE_1)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 20),
+ [GPIOAO(GPIOE_2)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 24),
+ [GPIOEE(GPIOZ_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 0),
+ [GPIOEE(GPIOZ_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 4),
+ [GPIOEE(GPIOZ_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 8),
+ [GPIOEE(GPIOZ_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 12),
+ [GPIOEE(GPIOZ_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 16),
+ [GPIOEE(GPIOZ_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 20),
+ [GPIOEE(GPIOZ_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 24),
+ [GPIOEE(GPIOZ_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 28),
+ [GPIOEE(GPIOZ_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 0),
+ [GPIOEE(GPIOZ_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 4),
+ [GPIOEE(GPIOZ_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 8),
+ [GPIOEE(GPIOZ_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 12),
+ [GPIOEE(GPIOZ_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 16),
+ [GPIOEE(GPIOZ_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 20),
+ [GPIOEE(GPIOZ_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 24),
+ [GPIOEE(GPIOZ_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 28),
+ [GPIOEE(GPIOH_0)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 0),
+ [GPIOEE(GPIOH_1)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 4),
+ [GPIOEE(GPIOH_2)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 8),
+ [GPIOEE(GPIOH_3)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 12),
+ [GPIOEE(GPIOH_4)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 16),
+ [GPIOEE(GPIOH_5)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 20),
+ [GPIOEE(GPIOH_6)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 24),
+ [GPIOEE(GPIOH_7)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 28),
+ [GPIOEE(GPIOH_8)] = PIN_MUX(MUX_EE_DOMAIN, 0xc, 0),
+ [GPIOEE(BOOT_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 0),
+ [GPIOEE(BOOT_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 4),
+ [GPIOEE(BOOT_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 8),
+ [GPIOEE(BOOT_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 12),
+ [GPIOEE(BOOT_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 16),
+ [GPIOEE(BOOT_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 20),
+ [GPIOEE(BOOT_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 24),
+ [GPIOEE(BOOT_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 28),
+ [GPIOEE(BOOT_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 0),
+ [GPIOEE(BOOT_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 4),
+ [GPIOEE(BOOT_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 8),
+ [GPIOEE(BOOT_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 12),
+ [GPIOEE(BOOT_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 16),
+ [GPIOEE(BOOT_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 20),
+ [GPIOEE(BOOT_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 24),
+ [GPIOEE(BOOT_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 28),
+ [GPIOEE(GPIOC_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 0),
+ [GPIOEE(GPIOC_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 4),
+ [GPIOEE(GPIOC_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 8),
+ [GPIOEE(GPIOC_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 12),
+ [GPIOEE(GPIOC_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 16),
+ [GPIOEE(GPIOC_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 20),
+ [GPIOEE(GPIOC_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 24),
+ [GPIOEE(GPIOC_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 28),
+ [GPIOEE(GPIOA_0)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 0),
+ [GPIOEE(GPIOA_1)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 4),
+ [GPIOEE(GPIOA_2)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 8),
+ [GPIOEE(GPIOA_3)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 12),
+ [GPIOEE(GPIOA_4)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 16),
+ [GPIOEE(GPIOA_5)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 20),
+ [GPIOEE(GPIOA_6)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 24),
+ [GPIOEE(GPIOA_7)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 28),
+ [GPIOEE(GPIOA_8)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 0),
+ [GPIOEE(GPIOA_9)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 4),
+ [GPIOEE(GPIOA_10)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 8),
+ [GPIOEE(GPIOA_11)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 12),
+ [GPIOEE(GPIOA_12)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 16),
+ [GPIOEE(GPIOA_13)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 20),
+ [GPIOEE(GPIOA_14)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 24),
+ [GPIOEE(GPIOA_15)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 28),
+ [GPIOEE(GPIOX_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 0),
+ [GPIOEE(GPIOX_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 4),
+ [GPIOEE(GPIOX_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 8),
+ [GPIOEE(GPIOX_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 12),
+ [GPIOEE(GPIOX_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 16),
+ [GPIOEE(GPIOX_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 20),
+ [GPIOEE(GPIOX_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 24),
+ [GPIOEE(GPIOX_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 28),
+ [GPIOEE(GPIOX_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 0),
+ [GPIOEE(GPIOX_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 4),
+ [GPIOEE(GPIOX_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 8),
+ [GPIOEE(GPIOX_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 12),
+ [GPIOEE(GPIOX_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 16),
+ [GPIOEE(GPIOX_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 20),
+ [GPIOEE(GPIOX_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 24),
+ [GPIOEE(GPIOX_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 28),
+ [GPIOEE(GPIOX_16)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 0),
+ [GPIOEE(GPIOX_17)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 4),
+ [GPIOEE(GPIOX_18)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 8),
+ [GPIOEE(GPIOX_19)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 12),
+};
+/*sequence of banks keep same as arch-g12a/gpio.h*/
+static struct meson_bank mesontxhd_banks[] = {
+ /*name first last pullen pull dir out in*/
+ AOBANK("GPIOAO_", GPIOAO(GPIOAO_0), GPIOAO(GPIOAO_11),
+ 3, 0, 2, 0, 0, 0, 4, 0, 1, 0),
+ AOBANK("GPIOE_", GPIOAO(GPIOE_0), GPIOAO(GPIOE_2),
+ 3, 16, 2, 16, 0, 16, 4, 16, 1, 16),
+ BANK("GPIOZ_", GPIOEE(GPIOZ_0), GPIOEE(GPIOZ_15),
+ 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
+ BANK("GPIOH_", GPIOEE(GPIOH_0), GPIOEE(GPIOH_8),
+ 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
+ BANK("BOOT_", GPIOEE(BOOT_0), GPIOEE(BOOT_15),
+ 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
+ BANK("GPIOC_", GPIOEE(GPIOC_0), GPIOEE(GPIOC_7),
+ 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
+ BANK("GPIOA_", GPIOEE(GPIOA_0), GPIOEE(GPIOA_15),
+ 5, 0, 5, 0, 16, 0, 17, 0, 18, 0),
+ BANK("GPIOX_", GPIOEE(GPIOX_0), GPIOEE(GPIOX_19),
+ 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
+};
+
+U_BOOT_DEVICES(txhd_gpios) = {
+ { "gpio_aml", &mesontxhd_banks[0] },
+ { "gpio_aml", &mesontxhd_banks[1] },
+ { "gpio_aml", &mesontxhd_banks[2] },
+ { "gpio_aml", &mesontxhd_banks[3] },
+ { "gpio_aml", &mesontxhd_banks[4] },
+ { "gpio_aml", &mesontxhd_banks[5] },
+ { "gpio_aml", &mesontxhd_banks[6] },
+ { "gpio_aml", &mesontxhd_banks[7] },
+};
+
+static unsigned long domain[]={
+ [MUX_AO_DOMAIN] = 0xff800014,
+ [MUX_EE_DOMAIN] = 0xff6346c0,
+};
+
+int clear_pinmux(unsigned int pin)
+{
+ struct pin_mux_desc *pmux_desc = &pin_to_gpio[pin];
+
+ regmap_update_bits(domain[pmux_desc->domain] + (pmux_desc->reg << 2),
+ 0xf << (pmux_desc->bit), 0 << (pmux_desc->bit));
+
+ return 0;
+}
+
+#ifdef CONFIG_AML_SPICC
+#include <asm/arch/secure_apb.h>
+/* generic pins control for spicc1.
+ * if deleted, you have to add it into all g12a board files as necessary.
+ * GPIOH_4: MOSI:regB[19:16]=3
+ * GPIOH_5: MISO:regB[23:20]=3
+ * GPIOH_7: CLK:regB[31:28]=3
+ */
+int spicc1_pinctrl_enable(bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_B);
+ val &= ~(0xf0ff << 16);
+ if (enable)
+ val |= 0x3033 << 16;
+ writel(val, P_PERIPHS_PIN_MUX_B);
+ return 0;
+}
+#endif /* CONFIG_AML_SPICC */
diff --git a/arch/arm/mach-meson/s4/hdmitx_clk.c b/arch/arm/mach-meson/s4/hdmitx_clk.c
new file mode 100644
index 0000000..0dcab99
--- /dev/null
+++ b/arch/arm/mach-meson/s4/hdmitx_clk.c
@@ -0,0 +1,862 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <amlogic/media/vout/hdmitx/hdmitx.h>
+#include "hdmitx_clk.h"
+
+static uint32_t frac_rate;
+
+#define msleep(i) udelay(i*1000)
+
+#define check_clk_config(para)\
+ if (para == -1)\
+ return;
+
+#define check_div() \
+ if (div == -1)\
+ return ;\
+ switch (div) {\
+ case 1:\
+ div = 0; break;\
+ case 2:\
+ div = 1; break;\
+ case 4:\
+ div = 2; break;\
+ case 6:\
+ div = 3; break;\
+ case 12:\
+ div = 4; break;\
+ default:\
+ break;\
+ }
+
+#define WAIT_FOR_PLL_LOCKED(_reg) \
+ do { \
+ unsigned int st = 0; \
+ int cnt = 10; \
+ unsigned int reg = _reg; \
+ while (cnt--) { \
+ msleep(5); \
+ st = (((hd_read_reg(reg) >> 30) & 0x3) == 3); \
+ if (st) \
+ break; \
+ else { \
+ /* reset hpll */ \
+ hd_set_reg_bits(reg, 1, 29, 1); \
+ hd_set_reg_bits(reg, 0, 29, 1); \
+ } \
+ } \
+ if (cnt < 9) \
+ printf("pll[0x%x] reset %d times\n", reg, 9 - cnt);\
+ } while (0)
+
+static void set_hdmitx_sys_clk(void)
+{
+ hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, 0, 9, 3);
+ hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, 0, 0, 7);
+ hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, 1, 8, 1);
+}
+
+/*
+ * When VCO outputs 6.0 GHz, if VCO unlock with default v1
+ * steps, then need reset with v2 or v3
+ */
+static bool set_hpll_hclk_v1(unsigned int m, unsigned int frac_val)
+{
+ int ret = 0;
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
+
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x0b3a0400 | (m & 0xff));
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x3, 28, 2);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, frac_val);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+
+ if (frac_val == 0x8148) {
+ if (((hdev->para->vic == HDMI_3840x2160p50_16x9) ||
+ (hdev->para->vic == HDMI_3840x2160p60_16x9) ||
+ (hdev->para->vic == HDMI_3840x2160p50_64x27) ||
+ (hdev->para->vic == HDMI_3840x2160p60_64x27)) &&
+ (hdev->para->cs != HDMI_COLOR_FORMAT_420)) {
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x11551293);
+ } else {
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x44331290);
+ }
+ } else {
+ if (hdmitx_find_vendor(hdev) &&
+ ((hdev->para->vic == HDMI_3840x2160p50_16x9) ||
+ (hdev->para->vic == HDMI_3840x2160p60_16x9) ||
+ (hdev->para->vic == HDMI_3840x2160p50_64x27) ||
+ (hdev->para->vic == HDMI_3840x2160p60_64x27) ||
+ (hdev->para->vic == HDMI_4096x2160p50_256x135) ||
+ (hdev->para->vic == HDMI_4096x2160p60_256x135)) &&
+ (hdev->para->cs != HDMI_COLOR_FORMAT_420)) {
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x11551293);
+ } else {
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a68dc00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x65771290);
+ }
+ }
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39272000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+
+ ret = (((hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0) >> 30) & 0x3) == 0x3);
+ return ret; /* return hpll locked status */
+}
+
+static bool set_hpll_hclk_v2(unsigned int m, unsigned int frac_val)
+{
+ int ret = 0;
+
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x0b3a0400 | (m & 0xff));
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x3, 28, 2);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, frac_val);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0xea68dc00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x65771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39272000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+
+ ret = (((hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0) >> 30) & 0x3) == 0x3);
+ return ret; /* return hpll locked status */
+}
+
+static bool set_hpll_hclk_v3(unsigned int m, unsigned int frac_val)
+{
+ int ret = 0;
+
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x0b3a0400 | (m & 0xff));
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x3, 28, 2);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, frac_val);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0xea68dc00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x65771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39272000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x55540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+
+ ret = (((hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0) >> 30) & 0x3) == 0x3);
+ return ret; /* return hpll locked status */
+}
+
+void set_hpll_clk_out(unsigned int clk)
+{
+ pr_info("config HPLL = %d frac_rate = %d\n", clk, frac_rate);
+ switch (clk) {
+ case 5940000:
+ if (set_hpll_hclk_v1(0xf7, frac_rate ? 0x8148 : 0x10000))
+ break;
+ if (set_hpll_hclk_v2(0x7b, 0x18000))
+ break;
+ if (set_hpll_hclk_v3(0xf7, 0x10000))
+ break;
+ break;
+ case 5850000:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004f3);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00018000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 5600000:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004e9);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x0000aaab);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);/*test*/
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 5405400:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004e1);
+ if (frac_rate)
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00000000);
+ else
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00007333);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 4897000:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004cc);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x0000d560);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x43231290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x29272000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540028);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 4455000:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004b9);
+ if (frac_rate)
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x0000e10e);
+ else
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00014000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x43231290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x29272000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540028);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 4324320:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004b4);
+ if (frac_rate)
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00000000);
+ else
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00005c29);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 3712500:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b00049a);
+ if (frac_rate)
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x000110e1);
+ else
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00016000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x43231290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x29272000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540028);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 3450000:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b00048f);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00018000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 3243240:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b000487);
+ if (frac_rate)
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00000000);
+ else
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x0000451f);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 3197500:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b000485);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00007555);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 2970000:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b00047b);
+ if (frac_rate)
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x000140b4);
+ else
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00018000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ default:
+ printf("error hpll clk: %d\n", clk);
+ break;
+ }
+}
+
+static void set_hpll_sspll(struct hdmitx_dev *hdev)
+{
+ enum hdmi_vic vic = hdev->vic;
+
+ switch (vic) {
+ case HDMI_1920x1080p60_16x9:
+ case HDMI_1920x1080p50_16x9:
+ case HDMI_1280x720p60_16x9:
+ case HDMI_1280x720p50_16x9:
+ case HDMI_1920x1080i60_16x9:
+ case HDMI_1920x1080i50_16x9:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 1, 29, 1);
+ /* bit[22:20] hdmi_dpll_fref_sel
+ * bit[8] hdmi_dpll_ssc_en
+ * bit[7:4] hdmi_dpll_ssc_dep_sel
+ */
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL2, 1, 20, 3);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL2, 1, 8, 1);
+ /* 2: 1000ppm 1: 500ppm */
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL2, 2, 4, 4);
+ if (hdev->dongle_mode)
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL2, 4, 4, 4);
+ /* bit[15] hdmi_dpll_sdmnc_en */
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL3, 0, 15, 1);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0, 29, 1);
+ break;
+ default:
+ break;
+ }
+}
+
+static void set_hpll_od1(unsigned div)
+{
+ switch (div) {
+ case 1:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0, 16, 2);
+ break;
+ case 2:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 1, 16, 2);
+ break;
+ case 4:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 2, 16, 2);
+ break;
+ default:
+ break;
+ }
+}
+
+static void set_hpll_od2(unsigned div)
+{
+ switch (div) {
+ case 1:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0, 18, 2);
+ break;
+ case 2:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 1, 18, 2);
+ break;
+ case 4:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 2, 18, 2);
+ break;
+ default:
+ break;
+ }
+}
+
+static void set_hpll_od3(unsigned div)
+{
+ switch (div) {
+ case 1:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0, 20, 2);
+ break;
+ case 2:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 1, 20, 2);
+ break;
+ case 4:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 2, 20, 2);
+ break;
+ default:
+ printf("Err %s[%d]\n", __func__, __LINE__);
+ break;
+ }
+}
+
+// --------------------------------------------------
+// clocks_set_vid_clk_div
+// --------------------------------------------------
+// wire clk_final_en = control[19];
+// wire clk_div1 = control[18];
+// wire [1:0] clk_sel = control[17:16];
+// wire set_preset = control[15];
+// wire [14:0] shift_preset = control[14:0];
+static void set_hpll_od3_clk_div(int div_sel)
+{
+ int shift_val = 0;
+ int shift_sel = 0;
+
+ /* When div 6.25, need to reset vid_pll_div */
+ if (div_sel == VID_PLL_DIV_6p25) {
+ msleep(1);
+ hd_write_reg(P_RESETCTRL_RESET0, 1 << 19);
+ }
+ // Disable the output clock
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 18, 2);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 15, 1);
+
+ switch (div_sel) {
+ case VID_PLL_DIV_1: shift_val = 0xFFFF; shift_sel = 0; break;
+ case VID_PLL_DIV_2: shift_val = 0x0aaa; shift_sel = 0; break;
+ case VID_PLL_DIV_3: shift_val = 0x0db6; shift_sel = 0; break;
+ case VID_PLL_DIV_3p5: shift_val = 0x36cc; shift_sel = 1; break;
+ case VID_PLL_DIV_3p75: shift_val = 0x6666; shift_sel = 2; break;
+ case VID_PLL_DIV_4: shift_val = 0x0ccc; shift_sel = 0; break;
+ case VID_PLL_DIV_5: shift_val = 0x739c; shift_sel = 2; break;
+ case VID_PLL_DIV_6: shift_val = 0x0e38; shift_sel = 0; break;
+ case VID_PLL_DIV_6p25: shift_val = 0x0000; shift_sel = 3; break;
+ case VID_PLL_DIV_7: shift_val = 0x3c78; shift_sel = 1; break;
+ case VID_PLL_DIV_7p5: shift_val = 0x78f0; shift_sel = 2; break;
+ case VID_PLL_DIV_12: shift_val = 0x0fc0; shift_sel = 0; break;
+ case VID_PLL_DIV_14: shift_val = 0x3f80; shift_sel = 1; break;
+ case VID_PLL_DIV_15: shift_val = 0x7f80; shift_sel = 2; break;
+ case VID_PLL_DIV_2p5: shift_val = 0x5294; shift_sel = 2; break;
+ case VID_PLL_DIV_3p25: shift_val = 0x66cc; shift_sel = 2; break;
+ default:
+ debug("Error: clocks_set_vid_clk_div: Invalid parameter\n");
+ break;
+ }
+
+ if (shift_val == 0xffff ) { // if divide by 1
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 1, 18, 1);
+ } else {
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 18, 1);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 16, 2);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 15, 1);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 0, 15);
+
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, shift_sel, 16, 2);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 1, 15, 1);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, shift_val, 0, 15);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 15, 1);
+ }
+ // Enable the final output clock
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 1, 19, 1);
+}
+
+static void set_vid_clk_div(unsigned div)
+{
+ check_clk_config(div);
+ if (div == 0)
+ div = 1;
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL, 0, 16, 3); // select vid_pll_clk
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_DIV, div-1, 0, 8);
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL, 7, 0, 3);
+}
+
+static void set_hdmi_tx_pixel_div(unsigned div)
+{
+ check_div();
+ hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, div, 16, 4);
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL2, 1, 5, 1); //enable gate
+}
+
+static void set_encp_div(unsigned div)
+{
+ check_div();
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_DIV, div, 24, 4);
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL2, 1, 2, 1); //enable gate
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL, 1, 19, 1);
+}
+
+static void set_enci_div(unsigned div)
+{
+ check_div();
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_DIV, div, 28, 4);
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL2, 1, 0, 1); //enable gate
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL, 1, 19, 1);
+}
+
+/* mode hpll_clk_out od1 od2(PHY) od3
+ * vid_pll_div vid_clk_div hdmi_tx_pixel_div encp_div enci_div
+ */
+/* For colordepth 8bits */
+static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
+ {{HDMI_720x480i60_16x9,
+ HDMI_720x576i50_16x9,
+ GROUP_END},
+ 1, VIU_ENCI, 4324320, 4, 4, 1, VID_PLL_DIV_5, 1, 2, -1, 2},
+ {{HDMI_720x576p50_16x9,
+ HDMI_720x480p60_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4324320, 4, 4, 1, VID_PLL_DIV_5, 1, 2, 2, -1},
+ {{HDMI_720x576p100_16x9,
+ HDMI_720x480p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4324320, 4, 2, 1, VID_PLL_DIV_5, 1, 2, 2, -1},
+ {{HDMI_1280x720p50_16x9,
+ HDMI_1280x720p60_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 4, 2, 1, VID_PLL_DIV_5, 1, 2, 2, -1},
+ {{HDMI_1920x1080i60_16x9,
+ HDMI_1920x1080i50_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 4, 2, 1, VID_PLL_DIV_5, 1, 2, 2, -1},
+ {{HDMI_1920x1080i100_16x9,
+ HDMI_1920x1080i120_16x9,
+ HDMI_1280x720p100_16x9,
+ HDMI_1280x720p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 4, 1, 1, VID_PLL_DIV_5, 1, 2, 2, -1},
+ {{HDMI_1920x1080p60_16x9,
+ HDMI_1920x1080p50_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 4, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ {{HDMI_1920x1080p30_16x9,
+ HDMI_1920x1080p24_16x9,
+ HDMI_1920x1080p25_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ {{HDMI_3840x2160p30_16x9,
+ HDMI_3840x2160p25_16x9,
+ HDMI_3840x2160p24_16x9,
+ HDMI_4096x2160p24_256x135,
+ HDMI_4096x2160p25_256x135,
+ HDMI_4096x2160p30_256x135,
+ HDMI_1920x1080p100_16x9,
+ HDMI_1920x1080p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_2160x1200p90hz,
+ GROUP_END},
+ 1, VIU_ENCP, 5371100, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ {{HDMI_3840x2160p60_16x9,
+ HDMI_3840x2160p50_16x9,
+ HDMI_4096x2160p60_256x135,
+ HDMI_4096x2160p50_256x135,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 1, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ {{HDMI_4096x2160p60_256x135_Y420,
+ HDMI_4096x2160p50_256x135_Y420,
+ HDMI_3840x2160p60_16x9_Y420,
+ HDMI_3840x2160p50_16x9_Y420,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 2, 1, 1, VID_PLL_DIV_5, 1, 2, 1, -1},
+ /* pll setting for VESA modes */
+ {{HDMIV_640x480p60hz, /* 4.028G / 16 = 251.75M */
+ GROUP_END},
+ 1, VIU_ENCP, 4028000, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_800x480p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4761600, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_800x600p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 3200000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_852x480p60hz,
+ HDMIV_854x480p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4838400, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1024x600p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4115866, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1024x768p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 5200000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1280x768p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 3180000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1280x800p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 5680000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1152x864p75hz,
+ HDMIV_1280x960p60hz,
+ HDMIV_1280x1024p60hz,
+ HDMIV_1600x900p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4320000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1600x1200p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 3240000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1360x768p60hz,
+ HDMIV_1366x768p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 3420000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1400x1050p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4870000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1440x900p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4260000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1440x2560p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4897000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1440x2560p70hz,
+ GROUP_END},
+ 1, VIU_ENCP, 5600000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1680x1050p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 5850000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1920x1200p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 3865000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_2560x1600p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 3485000, 1, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {
+ {
+ HDMIV_3440x1440p60hz, GROUP_END
+ },
+ 1, VIU_ENCP, 3197500, 1, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1
+ },
+ {
+ {
+ HDMIV_2400x1200p90hz, GROUP_END
+ },
+ 1, VIU_ENCP, 5600000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1
+ },
+};
+
+/* For colordepth 10bits */
+static struct hw_enc_clk_val_group setting_enc_clk_val_30[] = {
+ {{HDMI_720x480i60_16x9,
+ HDMI_720x576i50_16x9,
+ GROUP_END},
+ 1, VIU_ENCI, 5405400, 4, 4, 1, VID_PLL_DIV_6p25, 1, 2, -1, 2},
+ {{HDMI_720x576p50_16x9,
+ HDMI_720x480p60_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5405400, 4, 4, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+ {{HDMI_720x576p100_16x9,
+ HDMI_720x480p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5405400, 4, 2, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+ {{HDMI_1280x720p50_16x9,
+ HDMI_1280x720p60_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 4, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+ {{HDMI_1920x1080i60_16x9,
+ HDMI_1920x1080i50_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 4, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+ {{HDMI_1920x1080i120_16x9,
+ HDMI_1920x1080i100_16x9,
+ HDMI_1280x720p100_16x9,
+ HDMI_1280x720p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 2, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+ {{HDMI_1920x1080p60_16x9,
+ HDMI_1920x1080p50_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 1, 2, 2, VID_PLL_DIV_6p25, 1, 1, 1, -1},
+ {{HDMI_1920x1080p120_16x9,
+ HDMI_1920x1080p100_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 1, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+ {{HDMI_1920x1080p30_16x9,
+ HDMI_1920x1080p24_16x9,
+ HDMI_1920x1080p25_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 2, 2, 2, VID_PLL_DIV_6p25, 1, 1, 1, -1},
+ {{HDMI_4096x2160p60_256x135_Y420,
+ HDMI_4096x2160p50_256x135_Y420,
+ HDMI_3840x2160p60_16x9_Y420,
+ HDMI_3840x2160p50_16x9_Y420,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 1, 1, 1, VID_PLL_DIV_6p25, 1, 2, 1, -1},
+ {{HDMI_3840x2160p24_16x9,
+ HDMI_3840x2160p25_16x9,
+ HDMI_3840x2160p30_16x9,
+ HDMI_4096x2160p24_256x135,
+ HDMI_4096x2160p25_256x135,
+ HDMI_4096x2160p30_256x135,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 1, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+};
+
+/* For colordepth 12bits */
+static struct hw_enc_clk_val_group setting_enc_clk_val_36[] = {
+ {{HDMI_720x480i60_16x9,
+ HDMI_720x576i50_16x9,
+ GROUP_END},
+ 1, VIU_ENCI, 3243240, 2, 4, 1, VID_PLL_DIV_7p5, 1, 2, -1, 2},
+ {{HDMI_720x576p50_16x9,
+ HDMI_720x480p60_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3243240, 2, 4, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+ {{HDMI_720x576p100_16x9,
+ HDMI_720x480p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3243240, 2, 2, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+ {{HDMI_1280x720p50_16x9,
+ HDMI_1280x720p60_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 4, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+ {{HDMI_1920x1080i60_16x9,
+ HDMI_1920x1080i50_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 4, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+ {{HDMI_1920x1080i120_16x9,
+ HDMI_1920x1080i100_16x9,
+ HDMI_1280x720p100_16x9,
+ HDMI_1280x720p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 2, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+ {{HDMI_1920x1080p60_16x9,
+ HDMI_1920x1080p50_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 1, 2, 2, VID_PLL_DIV_7p5, 1, 1, 1, -1},
+ {{HDMI_1920x1080p120_16x9,
+ HDMI_1920x1080p100_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 1, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+ {{HDMI_1920x1080p30_16x9,
+ HDMI_1920x1080p24_16x9,
+ HDMI_1920x1080p25_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 2, 2, 2, VID_PLL_DIV_7p5, 1, 1, 1, -1},
+ {{HDMI_4096x2160p60_256x135_Y420,
+ HDMI_4096x2160p50_256x135_Y420,
+ HDMI_3840x2160p60_16x9_Y420,
+ HDMI_3840x2160p50_16x9_Y420,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 1, 1, 2, VID_PLL_DIV_3p25, 1, 2, 1, -1},
+ {{HDMI_3840x2160p24_16x9,
+ HDMI_3840x2160p25_16x9,
+ HDMI_3840x2160p30_16x9,
+ HDMI_4096x2160p24_256x135,
+ HDMI_4096x2160p25_256x135,
+ HDMI_4096x2160p30_256x135,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 1, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+};
+
+static void set_hdmitx_fe_clk(struct hdmitx_dev *hdev)
+{
+ unsigned int tmp = 0;
+ enum hdmi_vic vic = hdev->vic;
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL2, 1, 9, 1);
+
+ switch (vic) {
+ case HDMI_720x480i60_16x9:
+ case HDMI_720x576i50_16x9:
+ tmp = (hd_read_reg(P_CLKCTRL_VID_CLK_DIV) >> 28) & 0xf;
+ break;
+ default:
+ tmp = (hd_read_reg(P_CLKCTRL_VID_CLK_DIV) >> 24) & 0xf;
+ break;
+ }
+
+ hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, tmp, 20, 4);
+}
+
+static void set_hdmitx_clk_(struct hdmitx_dev *hdev, enum hdmi_color_depth cd)
+{
+ int i = 0;
+ int j = 0;
+ struct hw_enc_clk_val_group *p_enc = NULL;
+ enum hdmi_vic vic = hdev->vic;
+ char *sspll_dis = NULL;
+
+ if (cd == HDMI_COLOR_DEPTH_24B) {
+ p_enc = &setting_enc_clk_val_24[0];
+ for (j = 0; j < ARRAY_SIZE(setting_enc_clk_val_24); j++) {
+ for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i] != GROUP_END)); i ++) {
+ if (vic == p_enc[j].group[i])
+ goto next;
+ }
+ }
+ if (j == ARRAY_SIZE(setting_enc_clk_val_24)) {
+ debug("Not find VIC = %d for hpll setting\n", vic);
+ return;
+ }
+ } else if (cd == HDMI_COLOR_DEPTH_30B) {
+ p_enc = &setting_enc_clk_val_30[0];
+ for (j = 0; j < ARRAY_SIZE(setting_enc_clk_val_30); j++) {
+ for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i] != GROUP_END)); i ++) {
+ if (vic == p_enc[j].group[i])
+ goto next;
+ }
+ }
+ if (j == ARRAY_SIZE(setting_enc_clk_val_30)) {
+ debug("Not find VIC = %d for hpll setting\n", vic);
+ return;
+ }
+ } else if (cd == HDMI_COLOR_DEPTH_36B) {
+ p_enc = &setting_enc_clk_val_36[0];
+ for (j = 0; j < ARRAY_SIZE(setting_enc_clk_val_36); j++) {
+ for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i]
+ != GROUP_END)); i++) {
+ if (vic == p_enc[j].group[i])
+ goto next;
+ }
+ }
+ if (j == ARRAY_SIZE(setting_enc_clk_val_36)) {
+ printf("Not find VIC = %d for hpll setting\n", vic);
+ return;
+ }
+ } else {
+ printf("not support colordepth 48bits\n");
+ return;
+ }
+next:
+ set_hdmitx_sys_clk();
+ set_hpll_clk_out(p_enc[j].hpll_clk_out);
+ sspll_dis = env_get("sspll_dis");
+ if ((!sspll_dis || !strcmp(sspll_dis, "0")) &&
+ (cd == HDMI_COLOR_DEPTH_24B))
+ set_hpll_sspll(hdev);
+ set_hpll_od1(p_enc[j].od1);
+ set_hpll_od2(p_enc[j].od2);
+ set_hpll_od3(p_enc[j].od3);
+ set_hpll_od3_clk_div(p_enc[j].vid_pll_div);
+ debug("j = %d vid_clk_div = %d\n", j, p_enc[j].vid_clk_div);
+ set_vid_clk_div(p_enc[j].vid_clk_div);
+ set_hdmi_tx_pixel_div(p_enc[j].hdmi_tx_pixel_div);
+ set_encp_div(p_enc[j].encp_div);
+ set_enci_div(p_enc[j].enci_div);
+ set_hdmitx_fe_clk(hdev);
+}
+
+int hdmitx_likely_frac_rate_mode(char *m)
+{
+ if (strstr(m, "24hz") || strstr(m, "30hz") || strstr(m, "60hz")
+ || strstr(m, "120hz") || strstr(m, "240hz"))
+ return 1;
+ else
+ return 0;
+}
+
+void hdmitx_set_clk(struct hdmitx_dev *hdev)
+{
+ char *frac_rate_str = NULL;
+
+ frac_rate_str = env_get("frac_rate_policy");
+ if (frac_rate_str && (frac_rate_str[0] == '0'))
+ frac_rate = 0;
+ else if (hdmitx_likely_frac_rate_mode(hdev->para->ext_name))
+ frac_rate = 1;
+ hdev->frac_rate_policy = frac_rate;
+
+ if (hdev->para->cs != HDMI_COLOR_FORMAT_422)
+ set_hdmitx_clk_(hdev, hdev->para->cd);
+ else
+ set_hdmitx_clk_(hdev, HDMI_COLOR_DEPTH_24B);
+}
+
diff --git a/arch/arm/mach-meson/s4/hdmitx_clk.h b/arch/arm/mach-meson/s4/hdmitx_clk.h
new file mode 100644
index 0000000..d8fda6f
--- /dev/null
+++ b/arch/arm/mach-meson/s4/hdmitx_clk.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __HDMITX_COMMON_H__
+#define __HDMITX_COMMON_H__
+
+#include <common.h>
+#include <amlogic/media/vout/hdmitx/hdmitx.h>
+
+#define VID_PLL_DIV_1 0
+#define VID_PLL_DIV_2 1
+#define VID_PLL_DIV_3 2
+#define VID_PLL_DIV_3p5 3
+#define VID_PLL_DIV_3p75 4
+#define VID_PLL_DIV_4 5
+#define VID_PLL_DIV_5 6
+#define VID_PLL_DIV_6 7
+#define VID_PLL_DIV_6p25 8
+#define VID_PLL_DIV_7 9
+#define VID_PLL_DIV_7p5 10
+#define VID_PLL_DIV_12 11
+#define VID_PLL_DIV_14 12
+#define VID_PLL_DIV_15 13
+#define VID_PLL_DIV_2p5 14
+#define VID_PLL_DIV_3p25 15
+
+enum viu_type {
+ VIU_ENCL = 0,
+ VIU_ENCI,
+ VIU_ENCP,
+ VIU_ENCT,
+};
+
+typedef struct{
+ enum hdmi_vic vic;
+ unsigned viu_path;
+ enum viu_type viu_type;
+ unsigned hpll_clk_out;
+ unsigned od1;
+ unsigned od2;
+ unsigned od3;
+ unsigned vid_pll_div;
+ unsigned vid_clk_div;
+ unsigned hdmi_tx_pixel_div;
+ unsigned encp_div;
+ unsigned enci_div;
+}hw_enc_clk_val_t;
+
+#define GROUP_MAX 10
+#define GROUP_END -1
+struct hw_enc_clk_val_group {
+ enum hdmi_vic group[GROUP_MAX];
+ unsigned viu_path;
+ enum viu_type viu_type;
+ unsigned hpll_clk_out;
+ unsigned od1;
+ unsigned od2;
+ unsigned od3;
+ unsigned vid_pll_div;
+ unsigned vid_clk_div;
+ unsigned hdmi_tx_pixel_div;
+ unsigned encp_div;
+ unsigned enci_div;
+};
+
+#endif
diff --git a/arch/arm/mach-meson/s4/hdmitx_hw.c b/arch/arm/mach-meson/s4/hdmitx_hw.c
new file mode 100644
index 0000000..b598cb5
--- /dev/null
+++ b/arch/arm/mach-meson/s4/hdmitx_hw.c
@@ -0,0 +1,318 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
+#include <amlogic/media/vout/hdmitx/hdmitx_reg.h>
+#include <amlogic/media/vout/hdmitx/mach_reg.h>
+#include <asm/arch/bl31_apis.h>
+#include "hdmitx_misc.h"
+
+static struct reg_map reg_maps[] = {
+ [CBUS_REG_IDX] = { /* CBUS */
+ .base_addr = 0xfe001000,
+ },
+ [PERIPHS_REG_IDX] = { /* PERIPHS */
+ .base_addr = 0xfe004000,
+ },
+ [VCBUS_REG_IDX] = { /* VPU */
+ .base_addr = 0xff000000,
+ },
+ [HHI_REG_IDX] = { /* HIU */
+ .base_addr = 0xfe000000,
+ },
+ [SYSCTRL_REG_IDX] = {
+ .base_addr = 0xfe010000,
+ },
+ [RESETCTRL_REG_IDX] = {
+ .base_addr = 0xfe002000,
+ },
+ [ANACTRL_REG_IDX] = {
+ .base_addr = 0xfe008000,
+ },
+ [PWRCTRL_REG_IDX] = {
+ .base_addr = 0xfe00c000,
+ },
+ [HDMITX_SEC_REG_IDX] = { /* HDMITX DWC LEVEL*/
+ .base_addr = 0xfe300000,
+ },
+ [HDMITX_REG_IDX] = { /* HDMITX TOP LEVEL*/
+ .base_addr = 0xfe308000,
+ },
+ [REG_IDX_END] = {
+ },
+};
+
+#define HDMITX_DWC_BASE_OFFSET (reg_maps[HDMITX_SEC_REG_IDX].base_addr)
+#define HDMITX_TOP_BASE_OFFSET (reg_maps[HDMITX_REG_IDX].base_addr)
+
+int hdmitx_get_hpd_state(void)
+{
+ int st = 0;
+
+ st = !!(hd_read_reg(P_PADCTRL_GPIOH_I) & (1 << 2));
+ return st;
+}
+
+void hdmitx_ddc_init(void)
+{
+ /*Mux DDC SDA/SCL*/
+ hd_set_reg_bits(P_PADCTRL_PIN_MUX_REGB, 1, 0, 4);
+ hd_set_reg_bits(P_PADCTRL_PIN_MUX_REGB, 1, 4, 4);
+}
+
+static uint32_t get_base_addr(uint32_t idx)
+{
+ if (idx >= REG_IDX_END)
+ return 0;
+ if (!reg_maps[idx].base_addr)
+ printf("%s[%d] idx = %d\n", __func__, __LINE__, idx);
+
+ return reg_maps[idx].base_addr;
+}
+
+uint32_t hd_get_paddr(uint32_t addr)
+{
+ uint32_t idx = (addr) >> BASE_REG_OFFSET;
+ uint32_t offset_addr = ((1 << BASE_REG_OFFSET) - 1) & (addr);
+ uint32_t paddr;
+
+ paddr = get_base_addr(idx) + offset_addr;
+ return paddr;
+}
+
+uint32_t hd_read_reg(uint32_t addr)
+{
+ uint32_t val;
+ uint32_t idx = (addr) >> BASE_REG_OFFSET;
+ uint32_t offset_addr = ((1 << BASE_REG_OFFSET) - 1) & (addr);
+ void *paddr;
+
+ paddr = (void *)((unsigned long)(get_base_addr(idx) + offset_addr));
+ val = readl(paddr);
+
+ return val;
+}
+
+void hd_write_reg(unsigned int addr, unsigned int val)
+{
+ uint32_t idx = (addr) >> BASE_REG_OFFSET;
+ uint32_t offset_addr = ((1 << BASE_REG_OFFSET) - 1) & (addr);
+ void *paddr;
+
+ paddr = (void *)((unsigned long)(get_base_addr(idx) + offset_addr));
+ writel(val, paddr);
+}
+
+void hd_set_reg_bits(unsigned int addr, unsigned int value,
+ unsigned int offset, unsigned int len)
+{
+ unsigned int data32 = 0;
+
+ data32 = hd_read_reg(addr);
+ data32 &= ~(((1 << len) - 1) << offset);
+ data32 |= (value & ((1 << len) - 1)) << offset;
+ hd_write_reg(addr, data32);
+}
+
+static unsigned int hdmitx_rd_reg_normal(unsigned int addr)
+{
+ unsigned int data;
+ register long x0 asm("x0") = 0x82000018;
+ register long x1 asm("x1") = (unsigned long)addr;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r"(x0) : "r"(x1)
+ );
+ data = (unsigned int)(x0&0xffffffff);
+
+ return data;
+}
+
+static void hdmitx_wr_reg_normal(unsigned int addr, unsigned int data)
+{
+ register long x0 asm("x0") = 0x82000019;
+ register long x1 asm("x1") = (unsigned long)addr;
+ register long x2 asm("x2") = data;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ "smc #0\n"
+ : : "r"(x0), "r"(x1), "r"(x2)
+ );
+}
+
+unsigned int hdmitx_rd_reg(unsigned int addr)
+{
+ unsigned int large_offset = addr >> 24;
+ unsigned int small_offset = addr & ((1 << 24) - 1);
+ unsigned long hdmitx_addr = 0;
+ unsigned int data;
+
+ switch (large_offset) {
+ case 0x10:
+ /*DWC*/
+ hdmitx_addr = HDMITX_DWC_BASE_OFFSET + small_offset;
+ data = readb(hdmitx_addr);
+ break;
+ case 0x11:
+ case 0x01:
+ data = hdmitx_rd_reg_normal(addr);
+ break;
+ case 0x00:
+ default:
+ /* TOP */
+ if ((small_offset >= 0x2000) && (small_offset <= 0x365E)) {
+ hdmitx_addr = HDMITX_TOP_BASE_OFFSET + small_offset;
+ data = readb(hdmitx_addr);
+ } else {
+ hdmitx_addr = HDMITX_TOP_BASE_OFFSET + (small_offset << 2);
+ data = readl(hdmitx_addr);
+ }
+ break;
+ }
+
+ return data;
+}
+
+void hdmitx_wr_reg(unsigned int addr, unsigned int data)
+{
+ unsigned int large_offset = addr >> 24;
+ unsigned int small_offset = addr & ((1 << 24) - 1);
+ unsigned long hdmitx_addr = 0;
+
+ switch (large_offset) {
+ case 0x10:
+ /*DWC*/
+ hdmitx_addr = HDMITX_DWC_BASE_OFFSET + small_offset;
+ writeb(data & 0xff, hdmitx_addr);
+ break;
+ case 0x11:
+ case 0x01:
+ /*SECURITY DWC/TOP*/
+ hdmitx_wr_reg_normal(addr, data);
+ break;
+ case 00:
+ default:
+ /*TOP*/
+ if ((small_offset >= 0x2000) && (small_offset <= 0x365E)) {
+ hdmitx_addr = HDMITX_TOP_BASE_OFFSET + small_offset;
+ writeb(data & 0xff, hdmitx_addr);
+ } else {
+ hdmitx_addr = HDMITX_TOP_BASE_OFFSET + (small_offset << 2);
+ writel(data, hdmitx_addr);
+ }
+ }
+}
+
+void hdmitx_set_reg_bits(unsigned int addr, unsigned int value,
+ unsigned int offset, unsigned int len)
+{
+ unsigned int data32 = 0;
+
+ data32 = hdmitx_rd_reg(addr);
+ data32 &= ~(((1 << len) - 1) << offset);
+ data32 |= (value & ((1 << len) - 1)) << offset;
+ hdmitx_wr_reg(addr, data32);
+}
+
+void hdmitx_poll_reg(unsigned int addr, unsigned int val, unsigned long timeout)
+{
+}
+
+unsigned int hdmitx_rd_check_reg(unsigned int addr, unsigned int exp_data,
+ unsigned int mask)
+{
+ return 0;
+}
+
+void hdmitx_hdcp_init(void)
+{
+ register long x0 asm("x0") = 0x82000012;
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ : : "r"(x0)
+ );
+}
+
+void hdmitx_set_phypara(enum hdmi_phy_para mode)
+{
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x0);
+/* P_ANACTRL_HDMIPHY_CTRL1 bit[1]: enable clock bit[0]: soft reset */
+#define RESET_HDMI_PHY() \
+do { \
+ hd_set_reg_bits(P_ANACTRL_HDMIPHY_CTRL1, 0xf, 0, 4); \
+ mdelay(2); \
+ hd_set_reg_bits(P_ANACTRL_HDMIPHY_CTRL1, 0xe, 0, 4); \
+ mdelay(2); \
+} while (0)
+
+ hd_set_reg_bits(P_ANACTRL_HDMIPHY_CTRL1, 0x0390, 16, 16);
+ hd_set_reg_bits(P_ANACTRL_HDMIPHY_CTRL1, 0x0, 0, 4);
+ RESET_HDMI_PHY();
+ RESET_HDMI_PHY();
+#undef RESET_HDMI_PHY
+
+ switch (mode) {
+ case HDMI_PHYPARA_6G: /* 5.94/4.5/3.7Gbps */
+ case HDMI_PHYPARA_4p5G:
+ case HDMI_PHYPARA_3p7G:
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0x0000080b);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x37eb65c4);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b);
+ break;
+ case HDMI_PHYPARA_3G: /* 2.97Gbps */
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0x00000003);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x33eb42a2);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b);
+ break;
+ case HDMI_PHYPARA_270M: /* SD format, 480p/576p, 270Mbps */
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0x00000003);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x33eb4242);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b);
+ break;
+ case HDMI_PHYPARA_DEF:
+ default:
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0x00000003);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x33eb4252);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b);
+ break;
+ }
+}
+
+void hdmitx_turnoff(void)
+{
+ /* Close HDMITX PHY */
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0);
+ /* Disable HPLL */
+ hd_write_reg(ANACTRL_HDMIPLL_CTRL0, 0);
+}
+
+void hdmitx_test_prbs(void)
+{
+ unsigned int i;
+
+ for (i = 0; i < 4; i ++) {
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL1, 0x0390000f);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL1, 0x0390000e);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL1, 0x03904002);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL4, 0x0001efff | (i << 20));
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL1, 0xef904002);
+ mdelay(1);
+ if (i == 0)
+ printf("prbs clk: %08x\n",hd_read_reg(P_ANACTRL_HDMIPLL_CTRL6));
+ else
+ printf("prbs D[%d]: %08x\n", i -1, hd_read_reg(P_ANACTRL_HDMIPLL_CTRL6));
+ }
+}
diff --git a/arch/arm/mach-meson/s4/hdmitx_misc.h b/arch/arm/mach-meson/s4/hdmitx_misc.h
new file mode 100644
index 0000000..5e32df8
--- /dev/null
+++ b/arch/arm/mach-meson/s4/hdmitx_misc.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __HDMITX_MISC_H__
+#define __HDMITX_MISC_H__
+
+/* miscellaneous definition */
+
+/* REG_BASE: REGISTER_BASE_ADDR = 0xfe000000 */
+#define CLKCTRL_SYS_CLK_EN0_REG2 0x0013
+#define P_CLKCTRL_SYS_CLK_EN0_REG2 HHI_REG_ADDR(CLKCTRL_SYS_CLK_EN0_REG2)
+#define CLKCTRL_VID_CLK_CTRL 0x0030
+#define P_CLKCTRL_VID_CLK_CTRL HHI_REG_ADDR(CLKCTRL_VID_CLK_CTRL)
+#define CLKCTRL_VID_CLK_CTRL2 0x0031
+#define P_CLKCTRL_VID_CLK_CTRL2 HHI_REG_ADDR(CLKCTRL_VID_CLK_CTRL2)
+#define CLKCTRL_VID_CLK_DIV 0x0032
+#define P_CLKCTRL_VID_CLK_DIV HHI_REG_ADDR(CLKCTRL_VID_CLK_DIV)
+#define CLKCTRL_HDMI_CLK_CTRL 0x0038
+#define P_CLKCTRL_HDMI_CLK_CTRL HHI_REG_ADDR(CLKCTRL_HDMI_CLK_CTRL)
+#define CLKCTRL_VID_PLL_CLK_DIV 0x0039
+#define P_CLKCTRL_VID_PLL_CLK_DIV HHI_REG_ADDR(CLKCTRL_VID_PLL_CLK_DIV)
+#define CLKCTRL_HDCP22_CLK_CTRL 0x0040
+#define P_CLKCTRL_HDCP22_CLK_CTRL HHI_REG_ADDR(CLKCTRL_HDCP22_CLK_CTRL)
+
+/* REG_BASE: REGISTER_BASE_ADDR = 0xfe002000 */
+#define RESETCTRL_RESET0 0x0000
+#define P_RESETCTRL_RESET0 RESETCTRL_REG_ADDR(RESETCTRL_RESET0)
+#define RESETCTRL_RESET2 0x0002
+#define P_RESETCTRL_RESET2 RESETCTRL_REG_ADDR(RESETCTRL_RESET2)
+
+/* REG_BASE: REGISTER_BASE_ADDR = 0xfe008000 */
+#define ANACTRL_HDMIPLL_CTRL0 0x0070
+#define P_ANACTRL_HDMIPLL_CTRL0 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL0)
+#define ANACTRL_HDMIPLL_CTRL1 0x0071
+#define P_ANACTRL_HDMIPLL_CTRL1 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL1)
+#define ANACTRL_HDMIPLL_CTRL2 0x0072
+#define P_ANACTRL_HDMIPLL_CTRL2 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL2)
+#define ANACTRL_HDMIPLL_CTRL3 0x0073
+#define P_ANACTRL_HDMIPLL_CTRL3 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL3)
+#define ANACTRL_HDMIPLL_CTRL4 0x0074
+#define P_ANACTRL_HDMIPLL_CTRL4 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL4)
+#define ANACTRL_HDMIPLL_CTRL5 0x0075
+#define P_ANACTRL_HDMIPLL_CTRL5 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL5)
+#define ANACTRL_HDMIPLL_CTRL6 0x0076
+#define P_ANACTRL_HDMIPLL_CTRL6 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL6)
+#define ANACTRL_HDMIPLL_STS 0x0077
+#define P_ANACTRL_HDMIPLL_STS ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_STS)
+#define ANACTRL_HDMIPLL_VLOCK 0x0079
+#define P_ANACTRL_HDMIPLL_VLOCK ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_VLOCK)
+#define ANACTRL_HDMIPHY_CTRL0 0x0080
+#define P_ANACTRL_HDMIPHY_CTRL0 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL0)
+#define ANACTRL_HDMIPHY_CTRL1 0x0081
+#define P_ANACTRL_HDMIPHY_CTRL1 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL1)
+#define ANACTRL_HDMIPHY_CTRL2 0x0082
+#define P_ANACTRL_HDMIPHY_CTRL2 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL2)
+#define ANACTRL_HDMIPHY_CTRL3 0x0083
+#define P_ANACTRL_HDMIPHY_CTRL3 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL3)
+#define ANACTRL_HDMIPHY_CTRL4 0x0084
+#define P_ANACTRL_HDMIPHY_CTRL4 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL4)
+#define ANACTRL_HDMIPHY_CTRL5 0x0085
+#define P_ANACTRL_HDMIPHY_CTRL5 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL5)
+#define ANACTRL_HDMIPHY_STS 0x0086
+#define P_ANACTRL_HDMIPHY_STS ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_STS)
+
+/* REG_BASE: REGISTER_BASE_ADDR = 0xfe00c000 */
+#define PWRCTRL_MEM_PD11 0x001b
+#define P_PWRCTRL_MEM_PD11 PWRCTRL_REG_ADDR(PWRCTRL_MEM_PD11)
+
+#endif
diff --git a/arch/arm/mach-meson/s4/mailbox.c b/arch/arm/mach-meson/s4/mailbox.c
new file mode 100644
index 0000000..93cef28
--- /dev/null
+++ b/arch/arm/mach-meson/s4/mailbox.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/arch/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/arch/mailbox.h>
+#include <asm/arch/secure_apb.h>
+
+#define aml_writel32(value, reg) writel(value, reg)
+#define aml_readl32(reg) readl(reg)
+
+
+static inline void mbwrite(uint32_t to, void *from, long count)
+{
+ int i = 0;
+ int len = count / 4 + (count % 4);
+ uint32_t *p = from;
+
+ while (len > 0) {
+ aml_writel32(p[i], to + (4 * i));
+ len--;
+ i++;
+ }
+}
+
+static inline void mbclean(uint32_t to, long count)
+{
+ int i = 0;
+ int len = count / 4 + (count % 4);
+
+ while (len > 0) {
+ aml_writel32(0, to + (4 * i));
+ len--;
+ i++;
+ }
+}
+
+int mhu_get_addr(uint32_t chan, uint32_t *mboxset, uint32_t *mboxsts,
+ uintptr_t *mboxpl, uint32_t *mboxwr, uint32_t *mboxrd,
+ uint32_t *mboxirqclr, uint32_t *mboxid)
+{
+ int ret = 0;
+
+ switch (chan) {
+ case AOCPU_REE_CHANNEL:
+ *mboxset = REE2AO_SET_ADDR;
+ *mboxsts = REE2AO_STS_ADDR;
+ *mboxwr = REE2AO_WR_ADDR;
+ *mboxrd = REE2AO_RD_ADDR;
+ *mboxirqclr = REE2AO_IRQCLR_ADDR;
+ *mboxid = REE2AO_MBOX_ID;
+ break;
+ default:
+ printf("[BL33]: no support chan 0x%x\n", chan);
+ ret = -1;
+ break;
+ };
+ return ret;
+}
+
+void mhu_message_start(uint32_t mboxsts)
+{
+ /* Make sure any previous command has finished */
+ while (aml_readl32(mboxsts) != 0);
+}
+
+void mhu_build_payload(uintptr_t mboxpl, uint32_t mboxwr, void *message, uint32_t size)
+{
+ if (size > (MHU_PAYLOAD_SIZE - MHU_DATA_OFFSET)) {
+ printf("bl33: scpi send input size error\n");
+ return;
+ }
+ if (size == 0)
+ return;
+ mbwrite(mboxwr + MHU_DATA_OFFSET, message, size);
+}
+
+void mhu_get_payload(uintptr_t mboxpl, uint32_t mboxwr, void *message, uint32_t size)
+{
+ if (size > (MHU_PAYLOAD_SIZE - MHU_DATA_OFFSET)) {
+ printf("bl33: scpi send input size error\n");
+ return;
+ }
+ if (size == 0)
+ return;
+ printf("bl33: scpi no support get revmessage\n");
+}
+
+void mhu_message_send(uint32_t mboxset, uint32_t command, uint32_t size)
+{
+ uint32_t mbox_cmd;
+ mbox_cmd = MHU_CMD_BUILD(command, size + MHU_DATA_OFFSET);
+ aml_writel32(mbox_cmd, mboxset);
+}
+
+uint32_t mhu_message_wait(uint32_t mboxsts)
+{
+ /* Wait for response from HIFI */
+ uint32_t response;
+
+ while ((response = aml_readl32(mboxsts)));
+
+ return response;
+}
+
+void mhu_message_end(uintptr_t mboxpl, uint32_t mboxwr, uint32_t mboxirqclr, uint32_t mboxid)
+{
+ mbclean(mboxwr, MHU_PAYLOAD_SIZE);
+ /* Clear any response we got by writing all ones to the CLEAR register */
+ aml_writel32(MHU_ACK_MASK(mboxid), mboxirqclr);
+}
+
+void mhu_init(void)
+{
+ aml_writel32(0xffffffffu, REE2AO_CLR_ADDR);
+ printf("[BL33] mhu init done -v2\n");
+}
+int scpi_send_data(uint32_t chan, uint32_t command,
+ void *sendmessage, uint32_t sendsize,
+ void *revmessage, uint32_t revsize)
+{
+ uint32_t mboxset = 0;
+ uint32_t mboxsts = 0;
+ uintptr_t mboxpl = 0;
+ uint32_t mboxwr = 0;
+ uint32_t mboxrd = 0;
+ uint32_t mboxirq = 0;
+ uint32_t mboxid = 0;
+ int ret = 0;
+
+ ret = mhu_get_addr(chan, &mboxset, &mboxsts,
+ &mboxpl, &mboxwr, &mboxrd,
+ &mboxirq, &mboxid);
+ if (ret) {
+ printf("bl33: mhu get addr fail\n");
+ return ret;
+ }
+ mhu_message_start(mboxsts);
+ if (sendmessage != NULL && sendsize != 0)
+ mhu_build_payload(mboxpl, mboxwr, sendmessage, sendsize);
+ mhu_message_send(mboxset, command, sendsize);
+ mhu_message_wait(mboxsts);
+ if (revmessage != NULL && revsize != 0)
+ mhu_get_payload(mboxpl, mboxrd, revmessage, revsize);
+ mhu_message_end(mboxpl, mboxwr, mboxirq, mboxid);
+ return ret;
+}
+
diff --git a/arch/arm/mach-meson/s4/oscring.c b/arch/arm/mach-meson/s4/oscring.c
new file mode 100644
index 0000000..eb736c7
--- /dev/null
+++ b/arch/arm/mach-meson/s4/oscring.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/arch/io.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/oscring.h>
+
+void ring_powerinit(void)
+{
+ writel(0x18000a, RING_PWM_VCCK);/*set vcck 0.8v*/
+ writel(0x90009, RING_PWM_EE);/*set ee 0.8v*/
+}
+
+unsigned long clk_util_ring_msr(unsigned long clk_mux)
+{
+ unsigned int regval = 0;
+
+ writel(0, MSR_CLK_REG0);
+ /* Set the measurement gate to 64uS */
+ /* 64uS is enough for measure the frequence? */
+ setbits_le32(MSR_CLK_REG0, (10000 - 1));
+ /* Disable continuous measurement */
+ /* Disable interrupts */
+ clrbits_le32(MSR_CLK_REG0, (1 << 17) | (1 << 18));
+ clrbits_le32(MSR_CLK_REG0, 0x7f << 20);
+ setbits_le32(MSR_CLK_REG0, (clk_mux) << 20 | (1 << 19) | (1 << 16));
+ mdelay(10);
+ /* Wait for the measurement to be done */
+ regval = readl(MSR_CLK_REG0);
+ do {
+ regval = readl(MSR_CLK_REG0);
+ } while (regval & (1 << 31));
+
+ /* Disable measuring */
+ clrbits_le32(MSR_CLK_REG0, 1 << 16);
+ regval = (readl(MSR_CLK_REG2) + 31) & 0x000fffff;
+
+ return (regval / 10);
+}
+
+int ring_msr(int index)
+{
+ const char* clk_table[] = {
+ [41] = "top[3] (LVT16) " ,
+ [40] = "top[2] (LVT16) " ,
+ [39] = "top[1] (ULVT16) " ,
+ [38] = "top[0] (ULVT16) " ,
+ [37] = "core3[5] (LVT16) " ,
+ [36] = "core3[4] (LVT16) " ,
+ [35] = "core3[3] (LVT16)" ,
+ [34] = "core3[2] (ULVT16) " ,
+ [33] = "core3[1] (ULVT16) " ,
+ [32] = "core3[0] (ULVT16) " ,
+ [31] = "core2[5] (LVT16) " ,
+ [30] = "core2[4] (LVT16) " ,
+ [29] = "core2[3] (LVT16)" ,
+ [28] = "core2[2] (ULVT16) " ,
+ [27] = "core2[1] (ULVT16) " ,
+ [26] = "core2[0] (ULVT16) " ,
+ [25] = "core1[5] (LVT16) " ,
+ [24] = "core1[4] (LVT16) " ,
+ [23] = "core1[3] (LVT16)" ,
+ [22] = "core1[2] (ULVT16) " ,
+ [21] = "core1[1] (ULVT16) " ,
+ [20] = "core1[0] (ULVT16) " ,
+ [19] = "core0[5] (LVT16) " ,
+ [18] = "core0[4] (LVT16) " ,
+ [17] = "core0[3] (LVT16)" ,
+ [16] = "core0[2] (ULVT16) " ,
+ [15] = "core0[1] (ULVT16) " ,
+ [14] = "core0[0] (ULVT16) " ,
+ [13] = "demod[1] (LVT16) " ,
+ [12] = "demod[0] (SVT24) " ,
+ [11] = "ram (SVT16) " ,
+ [10] = "dos (ULVT20) " ,
+ [9] = "dos (LVT16) " ,
+ [8] = "dos (SVT16) " ,
+ [7] = "dos (SVT24) " ,
+ [6] = "vpu (LVT16) " ,
+ [5] = "vpu (LVT20) " ,
+ [4] = "vpu (SVT24) " ,
+ [3] = "mali (SVT16) " ,
+ [2] = "mali (ULVT16) " ,
+ [1] = "mali (LVT16) " ,
+ [0] = "dmc_top (LVT16) " ,
+ };
+ const int tb[] = {180, 181, 182, 183, 184, 185, 186, 187, 188, 189,
+ 190, 192, 193, 194, 196, 197, 198, 199, 200, 201,
+ 202, 203, 204, 205, 206, 207, 208, 209, 210, 211,
+ 212, 213, 214, 215, 216, 217, 218, 219, 220, 221,
+ 222, 223, 224, 225, 226, 227, 228, 229, 230, 231,
+ 232};
+ unsigned long i;
+ uint8_t efuseinfo[4] = {0, 0, 0, 0};
+
+ if ((index != 0xff) && (index != 0)) {
+ if (bl31_get_cornerinfo(efuseinfo, sizeof(efuseinfo) / sizeof(uint8_t)) != 0) {
+ printf("fail get efuse info\n");
+ return 0;
+ }
+ if ((index >= 1) && (index <= 3))
+ printf("%d\n", efuseinfo[index]);
+ else
+ printf("input data not support!\n");
+
+ return 0;
+ }
+ if (0xff != index) {
+ ring_powerinit();
+ printf("set vcck vddee to 800mv\n");
+ }
+ /*RING_OSCILLATOR 0x7f: set slow ring*/
+ writel(OSCRING_CTL_DATA0, OSCRING_CTL_REG0);
+ writel(OSCRING_CTL_DATA1, OSCRING_CTL_REG1);
+
+ for (i = 0; i < 42; i++) {
+ printf("%s :",clk_table[i]);
+ printf("%ld KHz",clk_util_ring_msr(tb[i]));
+ printf("\n");
+ }
+
+ if (bl31_get_cornerinfo(efuseinfo, sizeof(efuseinfo) / sizeof(uint8_t)) != 0) {
+ printf("fail get efuse info\n");
+ return 0;
+ }
+
+ printf("osc efuse info:\n");
+ for (i = 0; i < 4; i++)
+ printf("0x%x, ", efuseinfo[i]);
+ printf("\n");
+
+ /*efuse to test value*/
+ printf("sys_cpu_osc_ring0(ulvt16), idd_cpu, idd_ee\n");
+
+ printf("%d KHz ", (efuseinfo[1] * 20));
+
+ for (i = 2; i <=3; i++) {
+ printf("%d uA ", (efuseinfo[i] * 400));
+ }
+ printf("\n");
+
+ return 0;
+}
diff --git a/arch/arm/mach-meson/s4/pinctrl_init.c b/arch/arm/mach-meson/s4/pinctrl_init.c
new file mode 100644
index 0000000..829ce28
--- /dev/null
+++ b/arch/arm/mach-meson/s4/pinctrl_init.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm/uclass.h>
+#include <linux/err.h>
+#include <asm/arch/pinctrl_init.h>
+
+int pinctrl_devices_active(int pinctrl_num)
+{
+ int ret;
+ int idx;
+ struct udevice *pinctrl;
+
+ for (idx = 0; idx < pinctrl_num; idx++) {
+ ret = uclass_get_device(UCLASS_PINCTRL, idx, &pinctrl);
+ if (ret) {
+ debug("%s: failed to active pinctrl device [%d]",
+ __func__, idx);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-meson/s4/pll.c b/arch/arm/mach-meson/s4/pll.c
new file mode 100644
index 0000000..bfd6008
--- /dev/null
+++ b/arch/arm/mach-meson/s4/pll.c
@@ -0,0 +1,1094 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/pll.h>
+#include <linux/arm-smccc.h>
+
+#define STR_PLL_TEST_ALL "all"
+#define STR_PLL_TEST_SYS "sys"
+#define STR_PLL_TEST_FIX "fix"
+#define STR_PLL_TEST_DDR "ddr"
+#define STR_PLL_TEST_HDMI "hdmi"
+#define STR_PLL_TEST_GP0 "gp0"
+#define STR_PLL_TEST_GP1 "gp1"
+#define STR_PLL_TEST_HIFI "hifi"
+#define STR_PLL_TEST_PCIE "pcie"
+#define STR_PLL_TEST_ETHPHY "ethphy"
+#define STR_PLL_TEST_USBPHY "usbphy"
+#define STR_PLL_TEST_MPLL "mpll"
+
+
+#define PLL_LOCK_CHECK_MAX 3
+
+#define RET_PLL_LOCK_FAIL 0x1000
+#define RET_CLK_NOT_MATCH 0x1
+#define SYS_PLL_DIV16_CNTL (1 << 24)
+#define SYS_CLK_DIV16_CNTL (1 << 1)
+#define SYS_PLL_TEST_DIV 4 /* div16 */
+#define HDMI_PLL_DIV_CNTL (1 << 18)
+#define HDMI_PLL_DIV_GATE (1 << 19)
+
+#define PLL_DIV16_OFFSET 4 /* div2/2/4 */
+
+#define RW_CPUCTRL_SYS_CPU_CLK 0
+#define SYS_PLL 1
+#define RW_CPUCTRL_SYS_CPU_CLK5 2
+#define GP1_PLL 3
+
+enum sec_pll {
+ SECID_SYS0_DCO_PLL = 0,
+ SECID_SYS0_DCO_PLL_DIS,
+ SECID_SYS0_PLL_OD,
+ SECID_SYS1_DCO_PLL,
+ SECID_SYS1_DCO_PLL_DIS,
+ SECID_SYS1_PLL_OD,
+ SECID_CPU_CLK_SEL,
+ SECID_CPU_CLK_RD,
+ SECID_CPU_CLK_DYN,
+};
+
+extern unsigned long clk_util_clk_msr(unsigned long clk_mux);
+
+gp0_pll_cfg_t gp0_pll_cfg = {
+ .gp0_pll[0] = {
+ .pll_clk = 6000, /* MHz */
+ .pll_cntl0 = 0x080304fa,
+ .pll_cntl1 = 0x00000000,
+ .pll_cntl2 = 0x00000000,
+ .pll_cntl3 = 0x48681c00,
+ .pll_cntl4 = 0x88770290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x56540000
+ },
+ .gp0_pll[1] = {
+ .pll_clk = 3000, /* MHz */
+ .pll_cntl0 = 0X0803047d,
+ .pll_cntl1 = 0x00006aab,
+ .pll_cntl2 = 0x00000000,
+ .pll_cntl3 = 0x6a295c00,
+ .pll_cntl4 = 0x65771290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x54540000
+ },
+};
+
+gp1_pll_cfg_t gp1_pll_cfg = {
+ .gp1_pll[0] = {
+ .pll_clk = 6000, /* MHz */
+ .pll_cntl0 = 0x080304fa,
+ .pll_cntl1 = 0x00000000,
+ .pll_cntl2 = 0x00000000,
+ .pll_cntl3 = 0x48681c00,
+ .pll_cntl4 = 0x88770290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x56540000
+ },
+ .gp1_pll[1] = {
+ .pll_clk = 3000, /* MHz */
+ .pll_cntl0 = 0X0803047d,
+ .pll_cntl1 = 0x00006aab,
+ .pll_cntl2 = 0x00000000,
+ .pll_cntl3 = 0x6a295c00,
+ .pll_cntl4 = 0x65771290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x54540000
+ },
+};
+
+hdmi_pll_cfg_t hdmi_pll_cfg = {
+ .hdmi_pll[0] = {
+ .pll_clk = 5940, /* MHz */
+ .pll_cntl0 = 0x0b3004f7,
+ .pll_cntl1 = 0x00010000,
+ .pll_cntl2 = 0x00000000,
+ .pll_cntl3 = 0x6a28dc00,
+ .pll_cntl4 = 0x65771290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x56540000
+ },
+ .hdmi_pll[1] = {
+ .pll_clk = 2970,
+ .pll_cntl0 = 0x0b00047b,
+ .pll_cntl1 = 0x00018000,
+ .pll_cntl2 = 0x00000000,
+ .pll_cntl3 = 0x6a29dc00,
+ .pll_cntl4 = 0x65771290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x54540000
+ },
+};
+
+uint32_t sys_pll_clk[] = {6000, 3000};
+sys_pll_cfg_t sys_pll_cfg = {
+ .sys_pll[0] = {
+ .cpu_clk = 6000,
+ .pll_cntl = 0X080304fa,
+ .pll_cntl1 = 0x0,
+ .pll_cntl2 = 0x0,
+ .pll_cntl3 = 0x48681c00,
+ .pll_cntl4 = 0x88770290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x56540000
+ },
+
+ .sys_pll[1] = {
+ .cpu_clk = 3000,
+ .pll_cntl = 0X0803047d,
+ .pll_cntl1 = 0x0,
+ .pll_cntl2 = 0x0,
+ .pll_cntl3 = 0x48681c00,
+ .pll_cntl4 = 0x88770290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x56540000
+ },
+};
+
+hifi_pll_cfg_t hifi_pll_cfg = {
+ .hifi_pll[0] = {
+ .pll_clk = 6005,
+ .pll_cntl0 = 0X080304fa,
+ .pll_cntl1 = 0X00006aab,
+ .pll_cntl2 = 0x0,
+ .pll_cntl3 = 0x6a285c00,
+ .pll_cntl4 = 0x65771290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x56540000
+ },
+
+ .hifi_pll[1] = {
+ .pll_clk = 3000,
+ .pll_cntl0 = 0X0803047d,
+ .pll_cntl1 = 0X00006aab,
+ .pll_cntl2 = 0x0,
+ .pll_cntl3 = 0x68295c00,
+ .pll_cntl4 = 0x65771290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x54540000
+ },
+};
+
+mpll_pll_set_t mpll = {
+ .pll_clk = 100,
+ .pll_cntl0 = 0x00000543,
+ .pll_cntl1 = 0xc14003e7,
+ .pll_cntl2 = 0x60000033,
+ .pll_cntl3 = 0xc14003e7,
+ .pll_cntl4 = 0x60000033,
+ .pll_cntl5 = 0xc14003e7,
+ .pll_cntl6 = 0x60000033,
+ .pll_cntl7 = 0xc14003e7,
+ .pll_cntl8 = 0x60000033
+
+};
+
+/*PCIE clk_out = 24M*m/2^(n+1)/OD*/
+static const struct pciepll_rate_table pcie_pll_rate_table[] = {
+ PLL_RATE(4800, 200, 1, 12),
+};
+
+static void pll_report(unsigned int flag, char * name)
+{
+ if (flag)
+ printf("%s pll test failed!\n", name);
+ else
+ printf("%s pll test pass!\n", name);
+ return;
+}
+
+static int clk_around(unsigned int clk, unsigned int cmp)
+{
+ if (cmp == 1)
+ cmp += 1;
+ if (((cmp-2) <= clk) && (clk <= (cmp+2)))
+ return 1;
+ else
+ return 0;
+}
+
+static void clocks_set_sys_cpu_clk(uint32_t freq)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(0x82000099, SECID_CPU_CLK_SEL, (1 << 11), freq? 1 : 0,
+ 0, 0, 0, 0, &res);
+ arm_smccc_smc(0x82000099, SECID_CPU_CLK_DYN, freq, 0, 0, 0,
+ 0, 0, &res);
+}
+
+static int sys_pll_init(sys_pll_set_t * sys_pll_set)
+{
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int lock_timeout = 0;
+ struct arm_smccc_res res;
+
+ do {
+ arm_smccc_smc(0x82000098, SECID_SYS0_DCO_PLL,
+ (sys_pll_set->pll_cntl & 0x1FF),
+ ((sys_pll_set->pll_cntl >> 10) & 0x1F),
+ ((sys_pll_set->pll_cntl >> 16) & 0x3),
+ 0, 0, 0, &res);
+ //Wr(ANACTRL_SYSPLL_CTRL0, sys_pll_set->pll_cntl);
+ //Wr(ANACTRL_SYSPLL_CTRL0, sys_pll_set->pll_cntl | (3 << 28));
+ //Wr(ANACTRL_SYSPLL_CTRL1, sys_pll_set->pll_cntl1);
+ //Wr(ANACTRL_SYSPLL_CTRL2, sys_pll_set->pll_cntl2);
+ //Wr(ANACTRL_SYSPLL_CTRL3, sys_pll_set->pll_cntl3);
+ //Wr(ANACTRL_SYSPLL_CTRL4, sys_pll_set->pll_cntl4);
+ //Wr(ANACTRL_SYSPLL_CTRL5, sys_pll_set->pll_cntl5);
+ //Wr(ANACTRL_SYSPLL_CTRL6, sys_pll_set->pll_cntl6);
+ //Wr(ANACTRL_SYSPLL_CTRL0, ((1<<29) | Rd(HHI_SYS_PLL_CNTL0)));
+ //Wr(ANACTRL_SYSPLL_CTRL0, Rd(HHI_SYS_PLL_CNTL0)&(~(1<<29)));
+ lock_timeout = 200;
+ do {
+ _udelay(2);
+ } while ((!((readl(ANACTRL_SYSPLL_STS) >> 31) & 0x1)) &&
+ --lock_timeout);
+ } while((!((readl(ANACTRL_SYSPLL_STS) >> 31) & 0x1)) && --lock_check);
+
+ if (lock_check != 0)
+ return 0;
+ else
+ return RET_PLL_LOCK_FAIL;
+}
+
+static int sys_pll_test(sys_pll_set_t * sys_pll_set)
+{
+ unsigned int clk_msr_val = 0;
+ unsigned int sys_clk = 0;
+ sys_pll_set_t sys_pll;
+ int ret = 0, od = 0;
+
+ od = ((sys_pll_set->pll_cntl >> 16) & 0x3);
+ /* switch sys clk to oscillator */
+ clocks_set_sys_cpu_clk(0);
+
+ /* store current sys pll cntl */
+ sys_pll.pll_cntl = readl(ANACTRL_SYSPLL_CTRL0);
+ sys_pll.pll_cntl1 = readl(ANACTRL_SYSPLL_CTRL1);
+ sys_pll.pll_cntl2 = readl(ANACTRL_SYSPLL_CTRL2);
+ sys_pll.pll_cntl3 = readl(ANACTRL_SYSPLL_CTRL3);
+ sys_pll.pll_cntl4 = readl(ANACTRL_SYSPLL_CTRL4);
+ sys_pll.pll_cntl5 = readl(ANACTRL_SYSPLL_CTRL5);
+ sys_pll.pll_cntl6 = readl(ANACTRL_SYSPLL_CTRL6);
+
+ if (sys_pll_set->cpu_clk == 0) {
+ sys_clk = (24 / ((sys_pll_set->pll_cntl >> 10) & 0x1F) *
+ (sys_pll_set->pll_cntl & 0x1FF)) >>
+ ((sys_pll_set->pll_cntl >> 16) & 0x3);
+ } else {
+ sys_clk = sys_pll_set->cpu_clk;
+ }
+
+ if (0 == sys_pll_set->pll_cntl) {
+ printf("sys pll cntl equal NULL, skip\n");
+ return -1;
+ }
+
+ /* test sys pll */
+ ret = sys_pll_init(sys_pll_set);
+ _udelay(5);
+ if (ret) {
+ printf("SYS pll lock Failed! - %4d MHz\n", sys_clk);
+ } else {
+ printf("SYS pll lock OK! - %4d MHz. Div16 >>%d - %4d MHz. ",
+ sys_clk, od, (sys_clk >> SYS_PLL_TEST_DIV) >> od);
+ clk_msr_val = clk_util_clk_msr(23);
+ printf("CLKMSR(23) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, (sys_clk >> SYS_PLL_TEST_DIV) >> od)) {
+ /* sys clk/pll div16 */
+ printf(": Match\n");
+ } else {
+ ret = RET_CLK_NOT_MATCH;
+ printf(": MisMatch\n");
+ }
+ }
+
+ /* restore sys pll */
+ sys_pll_init(&sys_pll);
+ clocks_set_sys_cpu_clk(2);
+
+ return ret;
+}
+
+static int sys_pll_test_all(sys_pll_cfg_t * sys_pll_cfg)
+{
+ unsigned int i = 0;
+ int ret = 0;
+
+ for (i = 0; i < (sizeof(sys_pll_cfg_t) / sizeof(sys_pll_set_t)); i++)
+ ret += sys_pll_test(&(sys_pll_cfg->sys_pll[i]));
+ return ret;
+}
+
+static void set_dsu_clk(uint32_t flag)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(0x8200009C, RW_CPUCTRL_SYS_CPU_CLK5, flag, 0, 0, 0,
+ 0, 0, &res);
+}
+
+static int gp1_pll_init(gp1_pll_set_t * gp1_pll_set)
+{
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int lock_timeout = 0;
+ struct arm_smccc_res res;
+
+ do {
+ arm_smccc_smc(0x8200009C, GP1_PLL, gp1_pll_set->pll_cntl0,
+ gp1_pll_set->pll_cntl3, gp1_pll_set->pll_cntl4,
+ 0, 0, 0, &res);
+ lock_timeout = 200;
+ do {
+ _udelay(2);
+ } while ((!((readl(ANACTRL_GP1PLL_STS) >> 31) & 0x1)) &&
+ --lock_timeout);
+ } while((!((readl(ANACTRL_GP1PLL_STS) >> 31) & 0x1)) && --lock_check);
+
+ if (lock_check != 0)
+ return 0;
+ else
+ return RET_PLL_LOCK_FAIL;
+}
+
+static int gp1_pll_test(gp1_pll_set_t * gp1_pll_set)
+{
+ unsigned int clk_msr_val = 0, od = 0;
+ unsigned int pll_clk = 0;
+ gp1_pll_set_t gp1_pll;
+ int ret = 0;
+
+ od = (gp1_pll_set->pll_cntl0 >> 16) & 0x7;
+ /* switch dsu clk to oscillator */
+ set_dsu_clk(0);
+
+ /* store current gp1 pll cntl */
+ gp1_pll.pll_cntl0 = readl(ANACTRL_GP1PLL_CTRL0);
+ gp1_pll.pll_cntl1 = readl(ANACTRL_GP1PLL_CTRL1);
+ gp1_pll.pll_cntl2 = readl(ANACTRL_GP1PLL_CTRL2);
+ gp1_pll.pll_cntl3 = readl(ANACTRL_GP1PLL_CTRL3);
+ gp1_pll.pll_cntl4 = readl(ANACTRL_GP1PLL_CTRL4);
+ gp1_pll.pll_cntl5 = readl(ANACTRL_GP1PLL_CTRL5);
+ gp1_pll.pll_cntl6 = readl(ANACTRL_GP1PLL_CTRL6);
+
+ if (gp1_pll_set->pll_clk == 0) {
+ pll_clk = (24 / ((gp1_pll_set->pll_cntl0 >> 10) & 0x1F) *
+ (gp1_pll_set->pll_cntl0 & 0x1FF));
+ } else {
+ pll_clk = gp1_pll_set->pll_clk;
+ }
+
+ if (0 == gp1_pll_set->pll_cntl0) {
+ printf("gp1 pll cntl equal NULL, skip\n");
+ return -1;
+ }
+
+ /* test gp1 pll */
+ ret = gp1_pll_init(gp1_pll_set);
+ _udelay(5);
+ if (ret) {
+ printf("GP1 pll lock Failed! - %4d MHz\n", pll_clk);
+ } else {
+ printf("GP1 pll lock OK! - %4d MHz>>%d - %4d MHz. ",
+ pll_clk, od, pll_clk >> od);
+ clk_msr_val = clk_util_clk_msr(21);
+ printf("CLKMSR(21) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk >> od)) {
+ printf(": Match\n");
+ } else {
+ ret = RET_CLK_NOT_MATCH;
+ printf(": MisMatch\n");
+ }
+ }
+
+ /* restore gp1 pll */
+ gp1_pll_init(&gp1_pll);
+ set_dsu_clk(1);
+
+ return ret;
+}
+
+static int gp1_pll_test_all(gp1_pll_cfg_t * gp1_pll_cfg)
+{
+ unsigned int i = 0;
+ int ret = 0;
+
+ for (i = 0; i < (sizeof(gp1_pll_cfg_t) / sizeof(gp1_pll_set_t)); i++)
+ ret += gp1_pll_test(&(gp1_pll_cfg->gp1_pll[i]));
+ return ret;
+}
+
+static int fix_pll_test(void)
+{
+ return 0;
+}
+
+static int ddr_pll_test(void)
+{
+ return 0;
+}
+
+static int hdmi_pll_init(hdmi_pll_set_t * hdmi_pll)
+{
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+
+ do {
+ writel(hdmi_pll->pll_cntl0, ANACTRL_HDMIPLL_CTRL0);
+ writel(hdmi_pll->pll_cntl0 | (3 << 28), ANACTRL_HDMIPLL_CTRL0);
+ writel(hdmi_pll->pll_cntl1, ANACTRL_HDMIPLL_CTRL1);
+ writel(hdmi_pll->pll_cntl2, ANACTRL_HDMIPLL_CTRL2);
+ writel(hdmi_pll->pll_cntl3, ANACTRL_HDMIPLL_CTRL3);
+ writel(hdmi_pll->pll_cntl4, ANACTRL_HDMIPLL_CTRL4);
+ writel(hdmi_pll->pll_cntl5, ANACTRL_HDMIPLL_CTRL5);
+ writel(hdmi_pll->pll_cntl6, ANACTRL_HDMIPLL_CTRL6);
+
+ writel(readl(ANACTRL_HDMIPLL_CTRL0) | (1 << 29),
+ ANACTRL_HDMIPLL_CTRL0);
+ _udelay(10);
+ writel(readl(ANACTRL_HDMIPLL_CTRL0) & (~(1 << 29)),
+ ANACTRL_HDMIPLL_CTRL0);
+ _udelay(100);
+ } while ((!(0x3==((readl(ANACTRL_HDMIPLL_STS) >> 30) & 0x3))) &&
+ --lock_check);
+ if (lock_check != 0)
+ return 0;
+ else
+ return RET_PLL_LOCK_FAIL;
+}
+
+static int hdmi_pll_test(hdmi_pll_set_t * hdmi_pll_set)
+{
+ unsigned int pll_clk = 0 , od = 0;
+ unsigned int pll_clk_div = 0;
+ unsigned int clk_msr_val = 0;
+ unsigned int clk_msr_reg = 0;
+ int ret = 0;
+
+ /* store pll div setting */
+ clk_msr_reg = readl(CLKCTRL_VID_PLL_CLK_DIV);
+ /* connect vid_pll_div to HDMIPLL directly */
+ clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 19);
+ clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 15);
+
+ /* div14 */
+ clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 18);
+ clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 0x3 << 16);
+ clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 15);
+ clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 0x7fff);
+ setbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 16);
+ setbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 15);
+ setbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 0x3f80);
+ clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 15);
+
+ setbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 19);
+
+ /* test pll */
+ if (hdmi_pll_set->pll_clk == 0)
+ pll_clk = ((24 * (hdmi_pll_set->pll_cntl0 & 0xff)) /
+ ((hdmi_pll_set->pll_cntl0 >> 10) & 0x1f));
+ else
+ pll_clk = hdmi_pll_set->pll_clk;
+
+ _udelay(10);
+ ret = hdmi_pll_init(hdmi_pll_set);
+ if (ret) {
+ printf("HDMI pll lock Failed! - %4d MHz\n", pll_clk);
+ } else {
+ od = (hdmi_pll_set->pll_cntl0 >> 20) & 0x3;
+ pll_clk_div = (pll_clk >>od) / 14;
+ printf("HDMI pll lock OK! - %4d MHz>>%d and Div14 - %4d MHz. ",
+ pll_clk, od, pll_clk_div);
+ /* get [ 55][1485 MHz] vid_pll_div_clk_out */
+ clk_msr_val = clk_util_clk_msr(50);
+ printf("CLKMSR(50) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk_div)) {
+ printf(": Match\n");
+ } else {
+ ret = RET_CLK_NOT_MATCH;
+ printf(": MisMatch\n");
+ }
+ }
+
+ /* restore pll */
+ /* restore div cntl bit */
+ writel(clk_msr_reg, CLKCTRL_VID_PLL_CLK_DIV);
+
+ return ret;
+}
+
+static int hdmi_pll_test_all(hdmi_pll_cfg_t * hdmi_pll_cfg)
+{
+ unsigned int i = 0;
+ int ret = 0;
+
+ for (i = 0; i < (sizeof(hdmi_pll_cfg_t) / sizeof(hdmi_pll_set_t)); i++)
+ ret += hdmi_pll_test(&(hdmi_pll_cfg->hdmi_pll[i]));
+ return ret;
+}
+
+static int gp0_pll_test(gp0_pll_set_t * gp0_pll)
+{
+ unsigned int pll_clk = 0;
+ int ret = 0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0, od = 0;
+
+ od = (gp0_pll->pll_cntl0 >> 16) & 0x7;
+
+ if (gp0_pll->pll_clk == 0)
+ pll_clk = (24 / ((gp0_pll->pll_cntl0 >> 10) & 0x1F) *
+ (gp0_pll->pll_cntl0 & 0x1FF));
+ else
+ pll_clk = gp0_pll->pll_clk;
+
+ do {
+ writel(gp0_pll->pll_cntl0, ANACTRL_GP0PLL_CTRL0);
+ writel(gp0_pll->pll_cntl0 | (3 << 28), ANACTRL_GP0PLL_CTRL0);
+ writel(gp0_pll->pll_cntl1, ANACTRL_GP0PLL_CTRL1);
+ writel(gp0_pll->pll_cntl2, ANACTRL_GP0PLL_CTRL2);
+ writel(gp0_pll->pll_cntl3, ANACTRL_GP0PLL_CTRL3);
+ writel(gp0_pll->pll_cntl4, ANACTRL_GP0PLL_CTRL4);
+ writel(gp0_pll->pll_cntl5, ANACTRL_GP0PLL_CTRL5);
+ writel(gp0_pll->pll_cntl6, ANACTRL_GP0PLL_CTRL6);
+
+ writel(readl(ANACTRL_GP0PLL_CTRL0) | (1 << 29),
+ ANACTRL_GP0PLL_CTRL0);
+ _udelay(10);
+ writel(readl(ANACTRL_GP0PLL_CTRL0) & (~(1 << 29)),
+ ANACTRL_GP0PLL_CTRL0);
+ _udelay(100);
+ } while ((!((readl(ANACTRL_GP0PLL_STS) >> 31) & 0x1)) && --lock_check);
+
+ if (0 == lock_check) {
+ printf("GP0 pll lock Failed! - %4d MHz\n", pll_clk);
+ ret = RET_PLL_LOCK_FAIL;
+ } else {
+ printf("GP0 pll lock OK! - %4d MHz >>%d - %4d MHz. ",
+ pll_clk, od, pll_clk >> od);
+ /* get gp0_pll_clk */
+ clk_msr_val = clk_util_clk_msr(20);
+ printf("CLKMSR(20) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk >> od)) {
+ printf(": Match\n");
+ } else {
+ printf(": MisMatch\n");
+ ret = RET_CLK_NOT_MATCH;
+ }
+ }
+ return ret;
+}
+
+static int gp0_pll_test_all(gp0_pll_cfg_t * gp0_pll_cfg)
+{
+ unsigned int i = 0;
+ int ret = 0;
+ for (i = 0; i < (sizeof(gp0_pll_cfg_t) / sizeof(gp0_pll_set_t)); i++)
+ ret += gp0_pll_test(&(gp0_pll_cfg->gp0_pll[i]));
+ return ret;
+}
+
+static int hifi_pll_test(hifi_pll_set_t * hifi_pll)
+{
+ unsigned int pll_clk = 0;
+ int ret = 0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0, od = 0;
+
+ od = (hifi_pll->pll_cntl0 >> 16) & 0x3;
+
+ if (hifi_pll->pll_clk == 0)
+ pll_clk = (24 / ((hifi_pll->pll_cntl0 >> 10) & 0x1F) *
+ (hifi_pll->pll_cntl0 & 0x1FF));
+ else
+ pll_clk = hifi_pll->pll_clk;
+
+ do {
+ writel(hifi_pll->pll_cntl0, ANACTRL_HIFIPLL_CTRL0);
+ writel(hifi_pll->pll_cntl0 | (3 << 28), ANACTRL_HIFIPLL_CTRL0);
+ writel(hifi_pll->pll_cntl1, ANACTRL_HIFIPLL_CTRL1);
+ writel(hifi_pll->pll_cntl2, ANACTRL_HIFIPLL_CTRL2);
+ writel(hifi_pll->pll_cntl3, ANACTRL_HIFIPLL_CTRL3);
+ writel(hifi_pll->pll_cntl4, ANACTRL_HIFIPLL_CTRL4);
+ writel(hifi_pll->pll_cntl5, ANACTRL_HIFIPLL_CTRL5);
+ writel(hifi_pll->pll_cntl6, ANACTRL_HIFIPLL_CTRL6);
+ writel(readl(ANACTRL_HIFIPLL_CTRL0) | (1 << 29),
+ ANACTRL_HIFIPLL_CTRL0);
+ _udelay(10);
+ writel(readl(ANACTRL_HIFIPLL_CTRL0)&(~(1 << 29)),
+ ANACTRL_HIFIPLL_CTRL0);
+ _udelay(100);
+ } while ((!((readl(ANACTRL_HIFIPLL_STS) >> 31) & 0x1)) &&
+ --lock_check);
+ if (0 == lock_check) {
+ printf("HIFI pll lock Failed! - %4d MHz\n", pll_clk);
+ ret = RET_PLL_LOCK_FAIL;
+ } else {
+ printf("HIFI pll lock OK! - %4d MHz.Div8 - %4d MHz.",
+ pll_clk, pll_clk >> od);
+ /* get hifi_pll_clk */
+ clk_msr_val = clk_util_clk_msr(19);
+ printf("CLKMSR(19) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk >> od)) {
+ printf(": Match\n");
+ } else {
+ printf(": MisMatch\n");
+ ret = RET_CLK_NOT_MATCH;
+ }
+ }
+ return ret;
+}
+
+static int hifi_pll_test_all(hifi_pll_cfg_t * hifi_pll_cfg)
+{
+ unsigned int i = 0;
+ int ret = 0;
+
+ for (i = 0; i < (sizeof(hifi_pll_cfg_t) / sizeof(hifi_pll_set_t)); i++)
+ ret += hifi_pll_test(&(hifi_pll_cfg->hifi_pll[i]));
+ return ret;
+}
+
+static int pcie_pll_test(pcie_pll_set_t * pcie_pll)
+{
+ int ret = 0;
+ unsigned int i = 0, pll_clk = 0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+
+ for (i = 0; i < (sizeof(pcie_pll_rate_table) /
+ sizeof(pcie_pll_rate_table[0])); i++) {
+ if ((pcie_pll->pll_cntl0 & 0xFF) ==
+ pcie_pll_rate_table[i].m)
+ pll_clk = pcie_pll_rate_table[i].rate;
+ }
+
+ do {
+ writel(pcie_pll->pll_cntl0, ANACTRL_PCIEPLL_CTRL0);
+ writel(pcie_pll->pll_cntl0 | 0x30000000,
+ ANACTRL_PCIEPLL_CTRL0);
+ writel(pcie_pll->pll_cntl1, ANACTRL_PCIEPLL_CTRL1);
+ writel(pcie_pll->pll_cntl2, ANACTRL_PCIEPLL_CTRL2);
+ writel(pcie_pll->pll_cntl3, ANACTRL_PCIEPLL_CTRL3);
+ writel(pcie_pll->pll_cntl4, ANACTRL_PCIEPLL_CTRL4);
+ writel(pcie_pll->pll_cntl5, ANACTRL_PCIEPLL_CTRL5);
+ writel(pcie_pll->pll_cntl5 | 0x68, ANACTRL_PCIEPLL_CTRL5);
+ _udelay(20);
+ writel(pcie_pll->pll_cntl4 | 0x00800000,
+ ANACTRL_PCIEPLL_CTRL4);
+ _udelay(10);
+ writel(pcie_pll->pll_cntl0 | 0x34000000,
+ ANACTRL_PCIEPLL_CTRL0);
+ writel(((pcie_pll->pll_cntl0 & (~(1 << 29))) | (1 << 26)) |
+ (1 << 28), ANACTRL_PCIEPLL_CTRL0);
+ _udelay(10);
+ writel(pcie_pll->pll_cntl2 & (~(1 << 8)),
+ ANACTRL_PCIEPLL_CTRL2);
+ _udelay(10);
+ } while ((!((readl(ANACTRL_PCIEPLL_STS) >> 31) & 0x1)) &&
+ --lock_check);
+ if (0 == lock_check) {
+ printf("PCIE pll lock Failed! - %4d MHz\n", pll_clk);
+ ret = RET_PLL_LOCK_FAIL;
+ } else {
+ printf("PCIE pll lock OK! - %4d MHz.Div48 - %4d MHz. ",
+ pll_clk, pll_clk / 48);
+ /* get pcie_pll_clk */
+ clk_msr_val = clk_util_clk_msr(16);
+ printf("CLKMSR(16) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk / 48)) {
+ printf(": Match\n");
+ } else {
+ printf(": MisMatch\n");
+ ret = RET_CLK_NOT_MATCH;
+ }
+ }
+
+ return ret;
+}
+
+static int pcie_pll_test_all(void)
+{
+ unsigned int i = 0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+ int ret = 0;
+
+ do {
+ writel(0x200c04c8, ANACTRL_PCIEPLL_CTRL0);
+ writel(0x300c04c8, ANACTRL_PCIEPLL_CTRL0);
+ writel(0x30000000, ANACTRL_PCIEPLL_CTRL1);
+ writel(0x00001100, ANACTRL_PCIEPLL_CTRL2);
+ writel(0x10058e00, ANACTRL_PCIEPLL_CTRL3);
+ writel(0x000100c0, ANACTRL_PCIEPLL_CTRL4);
+ writel(0x68000048, ANACTRL_PCIEPLL_CTRL5);
+ writel(0x68000068, ANACTRL_PCIEPLL_CTRL5);
+ _udelay(20);
+ writel(0x008100c0, ANACTRL_PCIEPLL_CTRL4);
+ _udelay(10);
+ writel(0x340c04c8, ANACTRL_PCIEPLL_CTRL0);
+ writel(0x140c04c8, ANACTRL_PCIEPLL_CTRL0);
+ _udelay(10);
+ writel(0x00001000, ANACTRL_PCIEPLL_CTRL2);
+ _udelay(10);
+ } while ((!((readl(ANACTRL_PCIEPLL_STS) >> 31) & 0x1)) &&
+ --lock_check);
+
+ if (0 == lock_check) {
+ printf("pcie pll lock Failed! - %4d MHz\n",
+ pcie_pll_rate_table[i].rate);
+ ret += RET_PLL_LOCK_FAIL;
+ } else {
+ printf("pcie pll lock OK! - %4d MHz.Div48 - %4d MHz.",
+ pcie_pll_rate_table[i].rate,
+ pcie_pll_rate_table[i].rate / 48);
+ /* get pcie_pll_clk */
+ clk_msr_val = clk_util_clk_msr(16);
+ printf("CLKMSR(16) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val,
+ pcie_pll_rate_table[i].rate / 48)) {
+ printf(": Match\n");
+ } else {
+ printf(": MisMatch\n");
+ ret += RET_CLK_NOT_MATCH;
+ }
+ }
+
+ return ret;
+}
+
+static void set_mpll(mpll_pll_set_t *mpll)
+{
+ writel(mpll->pll_cntl0, ANACTRL_MPLL_CTRL0);
+ writel(mpll->pll_cntl1, ANACTRL_MPLL_CTRL1);
+ writel(mpll->pll_cntl2, ANACTRL_MPLL_CTRL2);
+ writel(mpll->pll_cntl3, ANACTRL_MPLL_CTRL3);
+ writel(mpll->pll_cntl4, ANACTRL_MPLL_CTRL4);
+ writel(mpll->pll_cntl5, ANACTRL_MPLL_CTRL5);
+ writel(mpll->pll_cntl6, ANACTRL_MPLL_CTRL6);
+ writel(mpll->pll_cntl7, ANACTRL_MPLL_CTRL7);
+ writel(mpll->pll_cntl8, ANACTRL_MPLL_CTRL8);
+}
+
+static int mpll_pll_test(mpll_pll_set_t *mpll)
+{
+ unsigned int i, ret = 0, clk_msr_val = 0;
+ mpll_pll_set_t old_mpll;
+ u64 clk_rate[4] = {0};
+
+ old_mpll.pll_cntl0 = readl(ANACTRL_MPLL_CTRL0);
+ old_mpll.pll_cntl1 = readl(ANACTRL_MPLL_CTRL1);
+ old_mpll.pll_cntl2 = readl(ANACTRL_MPLL_CTRL2);
+ old_mpll.pll_cntl3 = readl(ANACTRL_MPLL_CTRL3);
+ old_mpll.pll_cntl4 = readl(ANACTRL_MPLL_CTRL4);
+ old_mpll.pll_cntl5 = readl(ANACTRL_MPLL_CTRL5);
+ old_mpll.pll_cntl6 = readl(ANACTRL_MPLL_CTRL6);
+ old_mpll.pll_cntl7 = readl(ANACTRL_MPLL_CTRL7);
+ old_mpll.pll_cntl8 = readl(ANACTRL_MPLL_CTRL8);
+
+ if (!mpll->pll_clk) {
+ clk_rate[0] = (2000 * 16384)/
+ ((16384 * ((mpll->pll_cntl1 >> 20) & 0x1ff)) +
+ (mpll->pll_cntl1 & 0x7fff));
+ clk_rate[1] = (2000 * 16384)/
+ ((16384 * ((mpll->pll_cntl3 >> 20) & 0x1ff)) +
+ (mpll->pll_cntl3 & 0x7fff));
+ clk_rate[2] = (2000 * 16384)/
+ ((16384 * ((mpll->pll_cntl5 >> 20) & 0x1ff)) +
+ (mpll->pll_cntl5 & 0x7fff));
+ clk_rate[3] = (2000 * 16384)/
+ ((16384 * ((mpll->pll_cntl7 >> 20) & 0x1ff)) +
+ (mpll->pll_cntl7 & 0x7fff));
+ }
+
+ set_mpll(mpll);
+ for (i = 0; i < 4; i++) {
+ if (mpll->pll_clk) {
+ clk_rate[i] = mpll->pll_clk;
+ }
+ printf("mpll%d - %4lld MHz-", i, clk_rate[i]);
+ clk_msr_val = clk_util_clk_msr(11 + i);
+ printf("CLKMSR(16) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, clk_rate[i])) {
+ printf(": Match\n");
+ } else {
+ printf(": MisMatch\n");
+ ret += RET_CLK_NOT_MATCH;
+ }
+ }
+
+ set_mpll(&old_mpll);
+ return ret;
+}
+
+static int pll_test_all(unsigned char * pll_list)
+{
+ int ret = 0;
+ unsigned char i = 0;
+
+ for (i = 0; i < PLL_ENUM; i++) {
+ switch (pll_list[i]) {
+ case PLL_SYS:
+ ret = sys_pll_test_all(&sys_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_SYS);
+ break;
+ case PLL_FIX:
+ ret = fix_pll_test();
+ pll_report(ret, STR_PLL_TEST_FIX);
+ break;
+ case PLL_DDR:
+ ret = ddr_pll_test();
+ pll_report(ret, STR_PLL_TEST_DDR);
+ break;
+ case PLL_HDMI:
+ ret = hdmi_pll_test_all(&hdmi_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_HDMI);
+ break;
+ case PLL_GP0:
+ ret = gp0_pll_test_all(&gp0_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_GP0);
+ break;
+ case PLL_HIFI:
+ ret = hifi_pll_test_all(&hifi_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_HIFI);
+ break;
+ case PLL_PCIE:
+ ret = pcie_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_PCIE);
+ break;
+ case PLL_GP1:
+ ret = gp1_pll_test_all(&gp1_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_GP1);
+ break;
+ case PLL_MPLL:
+ ret = mpll_pll_test(&mpll);
+ pll_report(ret, STR_PLL_TEST_MPLL);
+ break;
+ default:
+ break;
+ }
+ }
+ return ret;
+}
+
+int pll_test(int argc, char * const argv[])
+{
+ int ret = 0;
+ sys_pll_set_t sys_pll_set = {0};
+ hdmi_pll_set_t hdmi_pll_set = {0};
+ gp0_pll_set_t gp0_pll_set = {0};
+ gp1_pll_set_t gp1_pll_set = {0};
+ hifi_pll_set_t hifi_pll_set = {0};
+ pcie_pll_set_t pcie_pll_set = {0};
+ mpll_pll_set_t mpll_pll_set = {0};
+
+ unsigned char plls[PLL_ENUM] = {
+ PLL_SYS,
+ 0xff,// PLL_FIX, //0xff will skip this pll
+ 0xff,// PLL_DDR,
+ 0xff,// PLL_HDMI
+ PLL_GP0,
+ PLL_HIFI,
+ 0xff, //PLL_PCIE
+ 0xff, //PLL_GP1
+ 0xff,//PLL_USBPHY
+ PLL_MPLL,
+ };
+
+ if (0 == strcmp(STR_PLL_TEST_ALL, argv[1])) {
+ printf("Test all plls\n");
+ pll_test_all(plls);
+ } else if(0 == strcmp(STR_PLL_TEST_SYS, argv[1])) {
+ if (argc == 2) {
+ ret = sys_pll_test_all(&sys_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_SYS);
+ } else if (argc != 9) {
+ printf("%s pll test: args error\n", STR_PLL_TEST_SYS);
+ return -1;
+ } else {
+ sys_pll_set.pll_cntl = simple_strtoul(argv[2], NULL,
+ 16);
+ sys_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL,
+ 16);
+ sys_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL,
+ 16);
+ sys_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL,
+ 16);
+ sys_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL,
+ 16);
+ sys_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL,
+ 16);
+ sys_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL,
+ 16);
+ ret = sys_pll_test(&sys_pll_set);
+ pll_report(ret, STR_PLL_TEST_SYS);
+ }
+ } else if (0 == strcmp(STR_PLL_TEST_HDMI, argv[1])) {
+ if (argc == 2) {
+ ret = hdmi_pll_test_all(&hdmi_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_HDMI);
+ } else if (argc != 9) {
+ printf("%s pll test: args error\n", STR_PLL_TEST_HDMI);
+ return -1;
+ } else {
+ hdmi_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL,
+ 16);
+ hdmi_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL,
+ 16);
+ hdmi_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL,
+ 16);
+ hdmi_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL,
+ 16);
+ hdmi_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL,
+ 16);
+ hdmi_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL,
+ 16);
+ hdmi_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL,
+ 16);
+ ret = hdmi_pll_test(&hdmi_pll_set);
+ pll_report(ret, STR_PLL_TEST_HDMI);
+ }
+ } else if (0 == strcmp(STR_PLL_TEST_GP0, argv[1])) {
+ if (argc == 2) {
+ ret = gp0_pll_test_all(&gp0_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_GP0);
+ } else if (argc != 9) {
+ printf("%s pll test: args error\n", STR_PLL_TEST_GP0);
+ return -1;
+ } else {
+ gp0_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL,
+ 16);
+ gp0_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL,
+ 16);
+ gp0_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL,
+ 16);
+ gp0_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL,
+ 16);
+ gp0_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL,
+ 16);
+ gp0_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL,
+ 16);
+ gp0_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL,
+ 16);
+ ret = gp0_pll_test(&gp0_pll_set);
+ pll_report(ret, STR_PLL_TEST_GP0);
+ }
+ } else if (0 == strcmp(STR_PLL_TEST_HIFI, argv[1])) {
+ if (argc == 2) {
+ ret = hifi_pll_test_all(&hifi_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_HIFI);
+ } else if (argc != 9) {
+ printf("%s pll test:args error\n", STR_PLL_TEST_HIFI);
+ return -1;
+ } else {
+ hifi_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL,
+ 16);
+ hifi_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL,
+ 16);
+ hifi_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL,
+ 16);
+ hifi_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL,
+ 16);
+ hifi_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL,
+ 16);
+ hifi_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL,
+ 16);
+ hifi_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL,
+ 16);
+ ret = hifi_pll_test(&hifi_pll_set);
+ pll_report(ret, STR_PLL_TEST_HIFI);
+ }
+ } else if (0 == strcmp(STR_PLL_TEST_PCIE, argv[1])) {
+ if (argc == 2) {
+ ret = pcie_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_PCIE);
+ } else if (argc != 8) {
+ printf("%s pll test: args error\n", STR_PLL_TEST_PCIE);
+ return -1;
+ } else {
+ pcie_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL,
+ 16);
+ pcie_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL,
+ 16);
+ pcie_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL,
+ 16);
+ pcie_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL,
+ 16);
+ pcie_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL,
+ 16);
+ pcie_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL,
+ 16);
+ ret = pcie_pll_test(&pcie_pll_set);
+ pll_report(ret, STR_PLL_TEST_PCIE);
+ }
+ } else if (0 == strcmp(STR_PLL_TEST_MPLL, argv[1])) {
+ if (argc == 2) {
+ ret = mpll_pll_test(&mpll);
+ pll_report(ret, STR_PLL_TEST_MPLL);
+ } else if (argc != 11) {
+ printf("%s pll test: args error\n", STR_PLL_TEST_MPLL);
+ return -1;
+ } else {
+ mpll_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL,
+ 16);
+ mpll_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL,
+ 16);
+ mpll_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL,
+ 16);
+ mpll_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL,
+ 16);
+ mpll_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL,
+ 16);
+ mpll_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL,
+ 16);
+ mpll_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL,
+ 16);
+ mpll_pll_set.pll_cntl7 = simple_strtoul(argv[9], NULL,
+ 16);
+ mpll_pll_set.pll_cntl8 = simple_strtoul(argv[10], NULL,
+ 16);
+ ret = mpll_pll_test(&mpll_pll_set);
+ pll_report(ret, STR_PLL_TEST_MPLL);
+ }
+ } else if (0 == strcmp(STR_PLL_TEST_GP1, argv[1])) {
+ if (argc == 2) {
+ ret = gp1_pll_test_all(&gp1_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_GP1);
+ } else if (argc != 9) {
+ printf("%s pll test: args error\n", STR_PLL_TEST_GP1);
+ return -1;
+ } else {
+ gp1_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL,
+ 16);
+ gp1_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL,
+ 16);
+ gp1_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL,
+ 16);
+ gp1_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL,
+ 16);
+ gp1_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL,
+ 16);
+ gp1_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL,
+ 16);
+ gp1_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL,
+ 16);
+ ret = gp1_pll_test(&gp1_pll_set);
+ pll_report(ret, STR_PLL_TEST_GP1);
+ }
+ } else if (0 == strcmp(STR_PLL_TEST_DDR, argv[1])) {
+ printf("%s pll not support now\n", STR_PLL_TEST_DDR);
+ return -1;
+ } else if (0 == strcmp(STR_PLL_TEST_FIX, argv[1])) {
+ printf("%s pll not support now\n", STR_PLL_TEST_FIX);
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-meson/s4/power_cal.c b/arch/arm/mach-meson/s4/power_cal.c
new file mode 100644
index 0000000..e4f9c53
--- /dev/null
+++ b/arch/arm/mach-meson/s4/power_cal.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/io.h>
+#include <amlogic/saradc.h>
+#include <asm/arch/mailbox.h>
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2))))
+#define vcck_adc_channel 0x4
+#define ee_adc_channel 0x5
+#define default_ref_val 1800
+
+extern const int pwm_cal_voltage_table[][2];
+extern const int pwm_cal_voltage_table_ee[][2];
+extern int pwm_cal_voltage_table_size;
+extern int pwm_cal_voltage_table_ee_size;
+
+
+enum pwm_id {
+ pwm_vcck = 0,
+ pwm_ee,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+int32_t aml_delt_get(int adc_val, unsigned int voltage)
+{
+ unsigned int adc_volt;
+ int32_t delt;
+ int32_t div = 10; /*10mv is min step*/
+
+ if (adc_val != -1) {
+ adc_volt = default_ref_val*adc_val/1024;
+ printf("aml pwm cal adc_val = %x, adc_voltage = %d, def_voltage = %d\n",
+ adc_val, adc_volt, voltage);
+ } else {
+ adc_volt = voltage;
+ printf("warning:aml pwm cal adc get voltage error\n");
+ return 0;
+ }
+ delt = voltage - adc_volt;
+ delt = delt / div;
+ return delt;
+}
+
+void aml_set_voltage(unsigned int id, unsigned int voltage, int delt)
+{
+ int to;
+
+ switch (id) {
+ case pwm_vcck:
+ for (to = 0; to < pwm_cal_voltage_table_size; to++) {
+ if (pwm_cal_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ to +=delt;
+ if (to >= pwm_cal_voltage_table_size) {
+ to = pwm_cal_voltage_table_size - 1;
+ }
+ /*vcck volt set by dvfs and avs*/
+ //writel(pwm_voltage_table[to][0], PWM_PWM_A_ADRESS);
+ _udelay_(200);
+ break;
+
+ case pwm_ee:
+ for (to = 0; to < pwm_cal_voltage_table_ee_size; to++) {
+ if (pwm_cal_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ to +=delt;
+ if (to >= pwm_cal_voltage_table_ee_size) {
+ to = pwm_cal_voltage_table_ee_size - 1;
+ }
+ printf("aml pwm cal before ee_address: %x, ee_voltage: %x\n",
+ AO_PWM_PWM_B, readl(AO_PWM_PWM_B));
+ writel(pwm_cal_voltage_table_ee[to][0],AO_PWM_PWM_B);
+ _udelay_(1000);
+ printf("aml pwm cal after ee_address: %x, ee_voltage: %x\n",
+ AO_PWM_PWM_B, readl(AO_PWM_PWM_B));
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+int aml_cal_pwm(unsigned int ee_voltage, unsigned int vcck_voltage)
+{
+ int32_t ee_delt, vcck_delt;
+ unsigned int ee_val, vcck_val;
+ int ret;
+
+ /*txlx vcck ch4,vddee ch5*/
+ ret = adc_channel_single_shot_mode("adc", ADC_MODE_HIGH_PRECISION,
+ vcck_adc_channel, &vcck_val);
+ if (ret)
+ return ret;
+
+ ret = adc_channel_single_shot_mode("adc", ADC_MODE_HIGH_PRECISION,
+ ee_adc_channel, &ee_val);
+ if (ret)
+ return ret;
+
+ vcck_delt = aml_delt_get(vcck_val, vcck_voltage);
+ ee_delt = aml_delt_get(ee_val, ee_voltage);
+ send_pwm_delt(vcck_delt, ee_delt);
+ aml_set_voltage(pwm_ee, AML_VDDEE_INIT_VOLTAGE, ee_delt);
+ //aml_set_voltage(pwm_vcck, CONFIG_VCCK_INIT_VOLTAGE, vcck_delt);
+ printf("aml board pwm vcck: %x, ee: %x\n", vcck_delt, ee_delt);
+
+ return 0;
+}
+
+void aml_pwm_cal_init(int mode)
+{
+ printf("aml pwm cal init\n");
+ aml_cal_pwm(AML_VDDEE_INIT_VOLTAGE, AML_VCCK_INIT_VOLTAGE);
+}
diff --git a/arch/arm/mach-meson/s4/power_gate.h b/arch/arm/mach-meson/s4/power_gate.h
new file mode 100644
index 0000000..9ca1a9d
--- /dev/null
+++ b/arch/arm/mach-meson/s4/power_gate.h
@@ -0,0 +1,1161 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __POWER_MGR_HEADER_
+#define __POWER_MGR_HEADER_
+
+#include <asm/arch/io.h>
+#include <common.h>
+//#include <asm/arch-gxb/io.h>
+/* #include <asm/arch-gxb/register.h> */
+#include <asm/arch/secure_apb.h>
+/* clock gate control */
+
+#define DEBUG_MASK 0
+
+#define SET_CLK_GATE_MASK(reg, mask) __raw_writel((__raw_readl(reg)|mask), reg)
+#define CLEAR_CLK_GATE_MASK(reg, mask) \
+ __raw_writel((__raw_readl(reg)&(~mask)), reg)
+#define CLK_GATE_ON(_MOD) do { \
+ if (DEBUG_MASK) \
+ printf("on reg %24s before read :0x%x : 0x%x\n",\
+ GCLK_NAME_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ SET_CLK_GATE_MASK(GCLK_REG_##_MOD, \
+ (unsigned int)GCLK_MASK_##_MOD); \
+ if (DEBUG_MASK) \
+ printf("on reg %24s after read :0x%x : 0x%x\n",\
+ GCLK_NAME_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ } while (0)
+
+#define CLK_GATE_OFF(_MOD) do { \
+ if (DEBUG_MASK) \
+ printf("off reg[ %24s ][0x%08x]before read:0x%08x:0x%08x\n",\
+ GCLK_NAME_##_MOD, (int)GCLK_MASK_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ CLEAR_CLK_GATE_MASK(GCLK_REG_##_MOD, (unsigned int)GCLK_MASK_##_MOD);\
+ if (DEBUG_MASK)\
+ printf("off reg[ %24s ][0x%08x] read after:0x%08x:0x%08x\n",\
+ GCLK_NAME_##_MOD, \
+ (int)GCLK_MASK_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ } while (0)
+
+#define IS_CLK_GATE_ON(_MOD) (__raw_readl(GCLK_REG_##_MOD) & (GCLK_MASK_##_MOD))
+#define GATE_INIT(_MOD) GCLK_ref[GCLK_IDX_##_MOD] = IS_CLK_GATE_ON(_MOD) ? 1 : 0
+
+#define GCLK_IDX_DDR 0
+#define GCLK_NAME_DDR "DDR"
+#define GCLK_DEV_DDR "CLKGATE_DDR"
+#define GCLK_REG_DDR (HHI_GCLK_MPEG0)
+#define GCLK_MASK_DDR (1<<0)
+
+#define GCLK_IDX_DOS 1
+#define GCLK_NAME_DOS "DOS"
+#define GCLK_DEV_DOS "CLKGATE_DOS"
+#define GCLK_REG_DOS (HHI_GCLK_MPEG0)
+#define GCLK_MASK_DOS (1<<1)
+
+#define GCLK_IDX_RESERVED0_0 2
+#define GCLK_NAME_RESERVED0_0 "RESERVED0_0"
+#define GCLK_DEV_RESERVED0_0 "CLKGATE_RESERVED0_0"
+#define GCLK_REG_RESERVED0_0 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_0 (1<<2)
+
+#define GCLK_IDX_RESERVED0_1 3
+#define GCLK_NAME_RESERVED0_1 "RESERVED0_1"
+#define GCLK_DEV_RESERVED0_1 "CLKGATE_RESERVED0_1"
+#define GCLK_REG_RESERVED0_1 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_1 (1<<3)
+
+/* #define GCLK_IDX_AHB_BRIDGE 4 */
+/* #define GCLK_NAME_AHB_BRIDGE "AHB_BRIDGE" */
+/* #define GCLK_DEV_AHB_BRIDGE "CLKGATE_AHB_BRIDGE" */
+/* #define GCLK_REG_AHB_BRIDGE (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_AHB_BRIDGE (1<<4) */
+
+#define GCLK_IDX_ISA 5
+#define GCLK_NAME_ISA "ISA"
+#define GCLK_DEV_ISA "CLKGATE_ISA"
+#define GCLK_REG_ISA (HHI_GCLK_MPEG0)
+#define GCLK_MASK_ISA (1<<5)
+
+/* NEW ADD */
+#define GCLK_IDX_PL310_CBUS 6
+#define GCLK_NAME_PL310_CBUS "PL310_CBUS"
+#define GCLK_DEV_PL310_CBUS "CLKGATE_PL310_CBUS"
+#define GCLK_REG_PL310_CBUS (HHI_GCLK_MPEG0)
+#define GCLK_MASK_PL310_CBUS (1<<6)
+
+#define GCLK_IDX_PERIPHS_TOP 7
+#define GCLK_NAME_PERIPHS_TOP "PERIPHS_TOP"
+#define GCLK_DEV_PERIPHS_TOP "CLKGATE_PERIPHS_TOP"
+#define GCLK_REG_PERIPHS_TOP (HHI_GCLK_MPEG0)
+#define GCLK_MASK_PERIPHS_TOP (1<<7)
+
+#define GCLK_IDX_SPICC 8
+#define GCLK_NAME_SPICC "SPICC"
+#define GCLK_DEV_SPICC "CLKGATE_SPICC"
+#define GCLK_REG_SPICC (HHI_GCLK_MPEG0)
+#define GCLK_MASK_SPICC (1<<8)
+
+#define GCLK_IDX_I2C 9
+#define GCLK_NAME_I2C "I2C"
+#define GCLK_DEV_I2C "CLKGATE_I2C"
+#define GCLK_REG_I2C (HHI_GCLK_MPEG0)
+#define GCLK_MASK_I2C (1<<9)
+
+#define GCLK_IDX_SAR_ADC 10
+#define GCLK_NAME_SAR_ADC "SAR_ADC"
+#define GCLK_DEV_SAR_ADC "CLKGATE_SAR_ADC"
+//#define GCLK_REG_SAR_ADC (HHI_SAR_CLK_CNTL) //no HHI_SAR_CLK_CNTL on TXL
+#define GCLK_REG_SAR_ADC (AO_SAR_CLK)
+#define GCLK_MASK_SAR_ADC (1<<8)
+
+#define GCLK_IDX_SMART_CARD_MPEG_DOMAIN 11
+#define GCLK_NAME_SMART_CARD_MPEG_DOMAIN "SMART_CARD_MPEG_DOMAIN"
+#define GCLK_DEV_SMART_CARD_MPEG_DOMAIN "CLKGATE_SMART_CARD_MPEG_DOMAIN"
+#define GCLK_REG_SMART_CARD_MPEG_DOMAIN (HHI_GCLK_MPEG0)
+#define GCLK_MASK_SMART_CARD_MPEG_DOMAIN (1<<11)
+
+#define GCLK_IDX_RANDOM_NUM_GEN 12
+#define GCLK_NAME_RANDOM_NUM_GEN "RANDOM_NUM_GEN"
+#define GCLK_DEV_RANDOM_NUM_GEN "CLKGATE_RANDOM_NUM_GEN"
+#define GCLK_REG_RANDOM_NUM_GEN (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RANDOM_NUM_GEN (1<<12)
+
+#define GCLK_IDX_UART0 13
+#define GCLK_NAME_UART0 "UART0"
+#define GCLK_DEV_UART0 "CLKGATE_UART0"
+#define GCLK_REG_UART0 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_UART0 (1<<13)
+
+/* gxb no this clock gate */
+/* #define GCLK_IDX_SDHC 14 */
+/* #define GCLK_NAME_SDHC "SDHC" */
+/* #define GCLK_DEV_SDHC "CLKGATE_SDHC" */
+/* #define GCLK_REG_SDHC (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_SDHC (1<<14) */
+
+#define GCLK_IDX_STREAM 15
+#define GCLK_NAME_STREAM "STREAM"
+#define GCLK_DEV_STREAM "CLKGATE_STREAM"
+#define GCLK_REG_STREAM (HHI_GCLK_MPEG0)
+#define GCLK_MASK_STREAM (1<<15)
+
+#define GCLK_IDX_ASYNC_FIFO 16
+#define GCLK_NAME_ASYNC_FIFO "ASYNC_FIFO"
+#define GCLK_DEV_ASYNC_FIFO "CLKGATE_ASYNC_FIFO"
+#define GCLK_REG_ASYNC_FIFO (HHI_GCLK_MPEG0)
+#define GCLK_MASK_ASYNC_FIFO (1<<16)
+
+/* gxb no this clock gate */
+/* #define GCLK_IDX_SDIO 17 */
+/* #define GCLK_NAME_SDIO "SDIO" */
+/* #define GCLK_DEV_SDIO "CLKGATE_SDIO" */
+/* #define GCLK_REG_SDIO (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_SDIO (1<<17) */
+
+/* gxb no this clock gate */
+/* #define GCLK_IDX_AUD_BUF 18 */
+/* #define GCLK_NAME_AUD_BUF "AUD_BUF" */
+/* #define GCLK_DEV_AUD_BUF "CLKGATE_AUD_BUF" */
+/* #define GCLK_REG_AUD_BUF (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_AUD_BUF (1<<18) */
+
+#define GCLK_IDX_HIU_PARSER 19
+#define GCLK_NAME_HIU_PARSER "HIU_PARSER"
+#define GCLK_DEV_HIU_PARSER "CLKGATE_HIU_PARSER"
+#define GCLK_REG_HIU_PARSER (HHI_GCLK_MPEG0)
+#define GCLK_MASK_HIU_PARSER (1<<19)
+
+#define GCLK_IDX_RESERVED0_2 20
+#define GCLK_NAME_RESERVED0_2 "RESERVED0_2"
+#define GCLK_DEV_RESERVED0_2 "CLKGATE_RESERVED0_2"
+#define GCLK_REG_RESERVED0_2 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_2 (1<<20)
+
+/* NEW ADD */
+#define GCLK_IDX_RESERVED0_3 21
+#define GCLK_NAME_RESERVED0_3 "RESERVED0_3 "
+#define GCLK_DEV_RESERVED0_3 "CLKGATE_RESERVED0_3 "
+#define GCLK_REG_RESERVED0_3 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_3 (1<<21)
+
+#define GCLK_IDX_RESERVED0_4 22
+#define GCLK_NAME_RESERVED0_4 "RESERVED0_4"
+#define GCLK_DEV_RESERVED0_4 "CLKGATE_RESERVED0_4"
+#define GCLK_REG_RESERVED0_4 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_4 (1<<22)
+
+#define GCLK_IDX_ASSIST_MISC 23
+#define GCLK_NAME_ASSIST_MISC "ASSIST_MISC"
+#define GCLK_DEV_ASSIST_MISC "CLKGATE_ASSIST_MISC"
+#define GCLK_REG_ASSIST_MISC (HHI_GCLK_MPEG0)
+#define GCLK_MASK_ASSIST_MISC (1<<23)
+
+
+#define GCLK_IDX_EMMC_A 24
+#define GCLK_NAME_EMMC_A "EMMC_A"
+#define GCLK_DEV_EMMC_A "CLKGATE_EMMC_A"
+#define GCLK_REG_EMMC_A (HHI_GCLK_MPEG0)
+#define GCLK_MASK_EMMC_A (1<<24)
+
+#define GCLK_IDX_EMMC_B 25
+#define GCLK_NAME_EMMC_B "EMMC_B"
+#define GCLK_DEV_EMMC_B "CLKGATE_EMMC_B"
+#define GCLK_REG_EMMC_B (HHI_GCLK_MPEG0)
+#define GCLK_MASK_EMMC_B (1<<25)
+
+#define GCLK_IDX_EMMC_C 26
+#define GCLK_NAME_EMMC_C "EMMC_C"
+#define GCLK_DEV_EMMC_C "CLKGATE_EMMC_C"
+#define GCLK_REG_EMMC_C (HHI_GCLK_MPEG0)
+#define GCLK_MASK_EMMC_C (1<<26)
+
+#define GCLK_IDX_RESERVED0_8 27
+#define GCLK_NAME_RESERVED0_8 "RESERVED0_8"
+#define GCLK_DEV_RESERVED0_8 "CLKGATE_RESERVED0_8"
+#define GCLK_REG_RESERVED0_8 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_8 (1<<27)
+
+#define GCLK_IDX_RESERVED0_9 28
+#define GCLK_NAME_RESERVED0_9 "RESERVED0_9"
+#define GCLK_DEV_RESERVED0_9 "CLKGATE_RESERVED0_9"
+#define GCLK_REG_RESERVED0_9 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_9 (1<<28)
+
+#define GCLK_IDX_RESERVED0_A 29
+#define GCLK_NAME_RESERVED0_A "RESERVED0_A"
+#define GCLK_DEV_RESERVED0_A "CLKGATE_RESERVED0_A"
+#define GCLK_REG_RESERVED0_A (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_A (1<<29)
+
+#define GCLK_IDX_SPI 30
+#define GCLK_NAME_SPI "SPI"
+#define GCLK_DEV_SPI "CLKGATE_SPI"
+#define GCLK_REG_SPI (HHI_GCLK_MPEG0)
+#define GCLK_MASK_SPI (1<<30)
+
+#define GCLK_IDX_RESERVED0_B 31
+#define GCLK_NAME_RESERVED0_B "RESERVED0_B"
+#define GCLK_DEV_RESERVED0_B "CLKGATE_RESERVED0_B"
+#define GCLK_REG_RESERVED0_B (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_B (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_RESERVED1_1 32
+#define GCLK_NAME_RESERVED1_1 "RESERVED1_1"
+#define GCLK_DEV_RESERVED1_1 "CLKGATE_RESERVED1_1"
+#define GCLK_REG_RESERVED1_1 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_1 (1<<0)
+
+
+#define GCLK_IDX_RESERVED1_2 33
+#define GCLK_NAME_RESERVED1_2 "RESERVED1_2"
+#define GCLK_DEV_RESERVED1_2 "CLKGATE_RESERVED1_2"
+#define GCLK_REG_RESERVED1_2 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_2 (1<<1)
+
+
+#define GCLK_IDX_AUD_IN 34
+#define GCLK_NAME_AUD_IN "AUD_IN"
+#define GCLK_DEV_AUD_IN "CLKGATE_AUD_IN"
+#define GCLK_REG_AUD_IN (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AUD_IN (1<<2)
+
+#define GCLK_IDX_ETHERNET 35
+#define GCLK_NAME_ETHERNET "ETHERNET"
+#define GCLK_DEV_ETHERNET "CLKGATE_ETHERNET"
+#define GCLK_REG_ETHERNET (HHI_GCLK_MPEG1)
+#define GCLK_MASK_ETHERNET (1<<3)
+
+/* g12a no reg */
+#if 0
+#define GCLK_IDX_ETH_CLK 145
+#define GCLK_NAME_ETH_CLK "ETH_CLK"
+#define GCLK_REG_ETH_CLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_ETH_CLK (1<<3)
+#endif
+
+#define GCLK_IDX_DEMUX 36
+#define GCLK_NAME_DEMUX "DEMUX"
+#define GCLK_DEV_DEMUX "CLKGATE_DEMUX"
+#define GCLK_REG_DEMUX (HHI_GCLK_MPEG1)
+#define GCLK_MASK_DEMUX (1<<4)
+
+#define GCLK_IDX_RESERVED1_3 37
+#define GCLK_NAME_RESERVED1_3 "RESERVED1_3"
+#define GCLK_DEV_RESERVED1_3 "CLKGATE_RESERVED1_3"
+#define GCLK_REG_RESERVED1_3 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_3 (1<<5)
+
+#define GCLK_IDX_AIU_AI_TOP_GLUE 38
+#define GCLK_NAME_AIU_AI_TOP_GLUE "AIU_AI_TOP_GLUE"
+#define GCLK_DEV_AIU_AI_TOP_GLUE "CLKGATE_AIU_AI_TOP_GLUE"
+#define GCLK_REG_AIU_AI_TOP_GLUE (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AI_TOP_GLUE (1<<6)
+
+#define GCLK_IDX_AIU_IEC958 39
+#define GCLK_NAME_AIU_IEC958 "AIU_IEC958"
+#define GCLK_DEV_AIU_IEC958 "CLKGATE_AIU_IEC958"
+#define GCLK_REG_AIU_IEC958 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_IEC958 (1<<7)
+
+#define GCLK_IDX_AIU_I2S_OUT 40
+#define GCLK_NAME_AIU_I2S_OUT "AIU_I2S_OUT"
+#define GCLK_DEV_AIU_I2S_OUT "CLKGATE_AIU_I2S_OUT"
+#define GCLK_REG_AIU_I2S_OUT (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_I2S_OUT (1<<8)
+
+#define GCLK_IDX_AIU_AMCLK_MEASURE 41
+#define GCLK_NAME_AIU_AMCLK_MEASURE "AIU_AMCLK_MEASURE"
+#define GCLK_DEV_AIU_AMCLK_MEASURE "CLKGATE_AIU_AMCLK_MEASURE"
+#define GCLK_REG_AIU_AMCLK_MEASURE (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AMCLK_MEASURE (1<<9)
+
+#define GCLK_IDX_AIU_AIFIFO2 42
+#define GCLK_NAME_AIU_AIFIFO2 "AIU_AIFIFO2"
+#define GCLK_DEV_AIU_AIFIFO2 "CLKGATE_AIU_AIFIFO2"
+#define GCLK_REG_AIU_AIFIFO2 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AIFIFO2 (1<<10)
+
+#define GCLK_IDX_AIU_AUD_MIXER 43
+#define GCLK_NAME_AIU_AUD_MIXER "AIU_AUD_MIXER"
+#define GCLK_DEV_AIU_AUD_MIXER "CLKGATE_AIU_AUD_MIXER"
+#define GCLK_REG_AIU_AUD_MIXER (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AUD_MIXER (1<<11)
+
+#define GCLK_IDX_AIU_MIXER_REG 44
+#define GCLK_NAME_AIU_MIXER_REG "AIU_MIXER_REG"
+#define GCLK_DEV_AIU_MIXER_REG "CLKGATE_AIU_MIXER_REG"
+#define GCLK_REG_AIU_MIXER_REG (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_MIXER_REG (1<<12)
+
+#define GCLK_IDX_AIU_ADC 45
+#define GCLK_NAME_AIU_ADC "AIU_ADC"
+#define GCLK_DEV_AIU_ADC "CLKGATE_AIU_ADC"
+#define GCLK_REG_AIU_ADC (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_ADC (1<<13)
+
+#define GCLK_IDX_BLK_MOV 46
+#define GCLK_NAME_BLK_MOV "BLK_MOV"
+#define GCLK_DEV_BLK_MOV "CLKGATE_BLK_MOV"
+#define GCLK_REG_BLK_MOV (HHI_GCLK_MPEG1)
+#define GCLK_MASK_BLK_MOV (1<<14)
+
+/* NEW ADD */
+#define GCLK_IDX_AIU_TOP_LEVEL 47
+#define GCLK_NAME_AIU_TOP_LEVEL "AIU_TOP_LEVEL"
+#define GCLK_DEV_AIU_TOP_LEVEL "CLKGATE_AIU_TOP_LEVEL"
+#define GCLK_REG_AIU_TOP_LEVEL (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_TOP_LEVEL (1<<15)
+
+//g12a no reg
+#if 0
+#define GCLK_NAME_PCM_MCLK "PCM_MCLK"
+#define GCLK_REG_PCM_MCLK (HHI_PCM_CLK_CNTL)
+#define GCLK_MASK_PCM_MCLK (1<<9)
+
+#define GCLK_NAME_PCM_SCLK "PCM_SCLK"
+#define GCLK_REG_PCM_SCLK (HHI_PCM_CLK_CNTL)
+#define GCLK_MASK_PCM_SCLK (1<<22)
+#endif
+
+#define GCLK_IDX_UART1 48
+#define GCLK_NAME_UART1 "UART1"
+#define GCLK_DEV_UART1 "CLKGATE_UART1"
+#define GCLK_REG_UART1 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_UART1 (1<<16)
+
+#define GCLK_IDX_RESERVED1_4 49
+#define GCLK_NAME_RESERVED1_4 "RESERVED1_4"
+#define GCLK_DEV_RESERVED1_4 "CLKGATE_RESERVED1_4"
+#define GCLK_REG_RESERVED1_4 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_4 (1<<17)
+
+/* NEW ADD */
+#define GCLK_IDX_RESERVED1_5 50
+#define GCLK_NAME_RESERVED1_5 "RESERVED1_5"
+#define GCLK_DEV_RESERVED1_5 "CLKGATE_RESERVED1_5"
+#define GCLK_REG_RESERVED1_5 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_5 (1<<18)
+
+#define GCLK_IDX_RESERVED1_6 51
+#define GCLK_NAME_RESERVED1_6 "RESERVED1_6"
+#define GCLK_DEV_RESERVED1_6 "CLKGATE_RESERVED1_6"
+#define GCLK_REG_RESERVED1_6 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_6 (1<<19)
+
+#define GCLK_IDX_GE2D 52
+#define GCLK_NAME_GE2D "GE2D"
+#define GCLK_DEV_GE2D "CLKGATE_GE2D"
+#define GCLK_REG_GE2D (HHI_GCLK_MPEG1)
+#define GCLK_MASK_GE2D (1<<20)
+
+#define GCLK_IDX_USB0 53
+#define GCLK_NAME_USB0 "USB0"
+#define GCLK_DEV_USB0 "CLKGATE_USB0"
+#define GCLK_REG_USB0 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_USB0 (1<<21)
+
+#define GCLK_IDX_USB1 54
+#define GCLK_NAME_USB1 "USB1"
+#define GCLK_DEV_USB1 "CLKGATE_USB1"
+#define GCLK_REG_USB1 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_USB1 (1<<22)
+
+#define GCLK_IDX_RESET 55
+#define GCLK_NAME_RESET "RESET"
+#define GCLK_DEV_RESET "CLKGATE_RESET"
+#define GCLK_REG_RESET (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESET (1<<23)
+
+#define GCLK_IDX_NAND_CLK 56
+#define GCLK_NAME_NAND_CLK "NAND CLK"
+#define GCLK_DEV_NAND_CLK "HHI_NAND_CLK"
+#define GCLK_REG_NAND_CLK (HHI_NAND_CLK_CNTL)
+#define GCLK_MASK_NAND_CLK (1<<7)
+
+#define GCLK_IDX_HIU_PARSER_TOP 57
+#define GCLK_NAME_HIU_PARSER_TOP "HIU_PARSER_TOP"
+#define GCLK_DEV_HIU_PARSER_TOP "CLKGATE_HIU_PARSER_TOP"
+#define GCLK_REG_HIU_PARSER_TOP (HHI_GCLK_MPEG1)
+#define GCLK_MASK_HIU_PARSER_TOP (1<<25)
+
+/* NEW ADD */
+
+/* g12a no reg */
+#if 0
+#define GCLK_NAME_USB_CLK "USB_CLK"
+#define GCLK_REG_USB_CLK (HHI_USB_CLK_CNTL)
+#define GCLK_MASK_USB_CLK (1<<9)
+#endif
+
+#define GCLK_IDX_USB_GENERAL 58
+#define GCLK_NAME_USB_GENERAL "USB_GENERAL"
+#define GCLK_DEV_USB_GENERAL "CLKGATE_USB_GENERAL"
+#define GCLK_REG_USB_GENERAL (HHI_GCLK_MPEG1)
+#define GCLK_MASK_USB_GENERAL (1<<26)
+
+#define GCLK_IDX_RESERVED1_7 59
+#define GCLK_NAME_RESERVED1_7 "RESERVED1_7"
+#define GCLK_DEV_RESERVED1_7 "CLKGATE_RESERVED1_7"
+#define GCLK_REG_RESERVED1_7 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_7 (1<<27)
+
+/* #define GCLK_IDX_VDIN1 60 */
+/* #define GCLK_NAME_VDIN1 "VDIN1" */
+/* #define GCLK_DEV_VDIN1 "CLKGATE_VDIN1" */
+/* #define GCLK_REG_VDIN1 (HHI_GCLK_MPEG1) */
+/* #define GCLK_MASK_VDIN1 (1<<28) */
+
+#define GCLK_IDX_AHB_ARB0 61
+#define GCLK_NAME_AHB_ARB0 "AHB_ARB0"
+#define GCLK_DEV_AHB_ARB0 "CLKGATE_AHB_ARB0"
+#define GCLK_REG_AHB_ARB0 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AHB_ARB0 (1<<29)
+
+#define GCLK_IDX_EFUSE 62
+#define GCLK_NAME_EFUSE "EFUSE"
+#define GCLK_DEV_EFUSE "CLKGATE_EFUSE"
+#define GCLK_REG_EFUSE (HHI_GCLK_MPEG1)
+#define GCLK_MASK_EFUSE (1<<30)
+
+#define GCLK_IDX_ROM_CLK 63
+#define GCLK_NAME_ROM_CLK "ROM_CLK"
+#define GCLK_DEV_ROM_CLK "CLKGATE_ROM_CLK"
+#define GCLK_REG_ROM_CLK (HHI_GCLK_MPEG1)
+#define GCLK_MASK_ROM_CLK (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_RESERVED2_0 64
+#define GCLK_NAME_RESERVED2_0 "RESERVED2_0"
+#define GCLK_DEV_RESERVED2_0 "CLKGATE_RESERVED2_0"
+#define GCLK_REG_RESERVED2_0 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_0 (1<<0)
+
+#define GCLK_IDX_AHB_DATA_BUS 65
+#define GCLK_NAME_AHB_DATA_BUS "AHB_DATA_BUS"
+#define GCLK_DEV_AHB_DATA_BUS "CLKGATE_AHB_DATA_BUS"
+#define GCLK_REG_AHB_DATA_BUS (HHI_GCLK_MPEG2)
+#define GCLK_MASK_AHB_DATA_BUS (1<<1)
+
+#define GCLK_IDX_AHB_CONTROL_BUS 66
+#define GCLK_NAME_AHB_CONTROL_BUS "AHB_CONTROL_BUS"
+#define GCLK_DEV_AHB_CONTROL_BUS "CLKGATE_AHB_CONTROL_BUS"
+#define GCLK_REG_AHB_CONTROL_BUS (HHI_GCLK_MPEG2)
+#define GCLK_MASK_AHB_CONTROL_BUS (1<<2)
+
+#define GCLK_IDX_HDMI_INTR_SYNC 67
+#define GCLK_NAME_HDMI_INTR_SYNC "HDMI_INTR_SYNC"
+#define GCLK_DEV_HDMI_INTR_SYNC "CLKGATE_HDMI_INTR_SYNC"
+#define GCLK_REG_HDMI_INTR_SYNC (HHI_GCLK_MPEG2)
+#define GCLK_MASK_HDMI_INTR_SYNC (1<<3)
+
+#define GCLK_IDX_HDMI_PCLK 68
+#define GCLK_NAME_HDMI_PCLK "HDMI_PCLK"
+#define GCLK_DEV_HDMI_PCLK "CLKGATE_HDMI_PCLK"
+#define GCLK_REG_HDMI_PCLK (HHI_GCLK_MPEG2)
+#define GCLK_MASK_HDMI_PCLK (1<<4)
+
+#define GCLK_IDX_PDM 69
+#define GCLK_NAME_PDM "PDM"
+#define GCLK_DEV_PDM "CLKGATE_PDM"
+#define GCLK_REG_PDM (HHI_GCLK_MPEG2)
+#define GCLK_MASK_PDM (1<<5)
+
+#define GCLK_IDX_BT656 70
+#define GCLK_NAME_BT656 "BT656"
+#define GCLK_DEV_BT656 "CLKGATE_BT656"
+#define GCLK_REG_BT656 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_BT656 (1<<6)
+
+#define GCLK_IDX_BT656_2 71
+#define GCLK_NAME_BT656_2 "BT656_2"
+#define GCLK_DEV_BT656_2 "CLKGATE_BT656_2"
+#define GCLK_REG_BT656_2 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_BT656_2 (1<<7)
+
+#define GCLK_IDX_MISC_USB1_TO_DDR 72
+#define GCLK_NAME_MISC_USB1_TO_DDR "MISC_USB1_TO_DDR"
+#define GCLK_DEV_MISC_USB1_TO_DDR "CLKGATE_MISC_USB1_TO_DDR"
+#define GCLK_REG_MISC_USB1_TO_DDR (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MISC_USB1_TO_DDR (1<<8)
+
+#define GCLK_IDX_MISC_USB0_TO_DDR 73
+#define GCLK_NAME_MISC_USB0_TO_DDR "MISC_USB0_TO_DDR"
+#define GCLK_DEV_MISC_USB0_TO_DDR "CLKGATE_MISC_USB0_TO_DDR"
+#define GCLK_REG_MISC_USB0_TO_DDR (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MISC_USB0_TO_DDR (1<<9)
+
+#define GCLK_IDX_RESERVED2_4 74
+#define GCLK_NAME_RESERVED2_4 "RESERVED2_4"
+#define GCLK_DEV_RESERVED2_4 "CLKGATE_RESERVED2_4"
+#define GCLK_REG_RESERVED2_4 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_4 (1<<10)
+
+#define GCLK_IDX_MMC_PCLK 75
+#define GCLK_NAME_MMC_PCLK "MMC_PCLK"
+#define GCLK_DEV_MMC_PCLK "CLKGATE_MMC_PCLK"
+#define GCLK_REG_MMC_PCLK (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MMC_PCLK (1<<11)
+
+//g12a no reg
+#if 0
+#define GCLK_NAME_MMC_A_PCLK "MMC_A_PCLK"
+#define GCLK_REG_MMC_A_PCLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_MMC_A_PCLK (1<<2)
+
+#define GCLK_NAME_MMC_B_PCLK "MMC_B_PCLK"
+#define GCLK_REG_MMC_B_PCLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_MMC_B_PCLK (1<<1)
+
+#define GCLK_NAME_MMC_C_PCLK "MMC_C_PCLK"
+#define GCLK_REG_MMC_C_PCLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_MMC_C_PCLK (1<<0)
+#endif
+
+#define GCLK_NAME_EMMC_A_CLK "EMMC_A_CLK"
+#define GCLK_REG_EMMC_A_CLK (HHI_SD_EMMC_CLK_CNTL)
+#define GCLK_MASK_EMMC_A_CLK (1<<7)
+
+#define GCLK_NAME_EMMC_B_CLK "EMMC_B_CLK"
+#define GCLK_REG_EMMC_B_CLK (HHI_SD_EMMC_CLK_CNTL)
+#define GCLK_MASK_EMMC_B_CLK (1<<23)
+
+#define GCLK_IDX_MISC_DVIN 76
+#define GCLK_NAME_MISC_DVIN "MISC_DVIN"
+#define GCLK_DEV_MISC_DVIN "CLKGATE_MISC_DVIN"
+#define GCLK_REG_MISC_DVIN (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MISC_DVIN (1<<12)
+
+#define GCLK_IDX_RESERVED2_5 77
+#define GCLK_NAME_RESERVED2_5 "RESERVED2_5"
+#define GCLK_DEV_RESERVED2_5 "CLKGATE_RESERVED2_5"
+#define GCLK_REG_RESERVED2_5 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_5 (1<<13)
+
+#define GCLK_IDX_RESERVED2_6 78
+#define GCLK_NAME_RESERVED2_6 "RESERVED2_6"
+#define GCLK_DEV_RESERVED2_6 "CLKGATE_RESERVED2_6"
+#define GCLK_REG_RESERVED2_6 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_6 (1<<14)
+
+#define GCLK_IDX_UART2 79
+#define GCLK_NAME_UART2 "UART2"
+#define GCLK_DEV_UART2 "CLKGATE_UART2"
+#define GCLK_REG_UART2 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_UART2 (1<<15)
+
+#define GCLK_IDX_RESERVED2_7 80
+#define GCLK_NAME_RESERVED2_7 "RESERVED2_7"
+#define GCLK_DEV_RESERVED2_7 "CLKGATE_RESERVED2_7"
+#define GCLK_REG_RESERVED2_7 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_7 (1<<16)
+
+#define GCLK_IDX_RESERVED2_8 81
+#define GCLK_NAME_RESERVED2_8 "RESERVED2_8"
+#define GCLK_DEV_RESERVED2_8 "CLKGATE_RESERVED2_8"
+#define GCLK_REG_RESERVED2_8 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_8 (1<<17)
+
+#define GCLK_IDX_RESERVED2_9 82
+#define GCLK_NAME_RESERVED2_9 "RESERVED2_9"
+#define GCLK_DEV_RESERVED2_9 "CLKGATE_RESERVED2_9"
+#define GCLK_REG_RESERVED2_9 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_9 (1<<18)
+
+#define GCLK_IDX_RESERVED2_A 83
+#define GCLK_NAME_RESERVED2_A "RESERVED2_A"
+#define GCLK_DEV_RESERVED2_A "CLKGATE_RESERVED2_A"
+#define GCLK_REG_RESERVED2_A (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_A (1<<19)
+
+#define GCLK_IDX_RESERVED2_B 84
+#define GCLK_NAME_RESERVED2_B "RESERVED2_B"
+#define GCLK_DEV_RESERVED2_B "CLKGATE_RESERVED2_B"
+#define GCLK_REG_RESERVED2_B (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_B (1<<20)
+
+#define GCLK_IDX_UART3 85
+#define GCLK_NAME_UART3 "UART3"
+#define GCLK_DEV_UART3 "CLKGATE_UART3"
+#define GCLK_REG_UART3 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_UART3 (1<<21)
+
+#define GCLK_IDX_SANA 86
+#define GCLK_NAME_SANA "SANA"
+#define GCLK_DEV_SANA "CLKGATE_SANA"
+#define GCLK_REG_SANA (HHI_GCLK_MPEG2)
+#define GCLK_MASK_SANA (1<<22)
+
+#define GCLK_IDX_RESERVED2_D 87
+#define GCLK_NAME_RESERVED2_D "RESERVED2_D"
+#define GCLK_DEV_RESERVED2_D "CLKGATE_RESERVED2_D"
+#define GCLK_REG_RESERVED2_D (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_D (1<<23)
+
+#define GCLK_IDX_RESERVED2_E 88
+#define GCLK_NAME_RESERVED2_E "RESERVED2_E"
+#define GCLK_DEV_RESERVED2_E "CLKGATE_RESERVED2_E"
+#define GCLK_REG_RESERVED2_E (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_E (1<<24)
+
+#define GCLK_IDX_VPU_INTR 89
+#define GCLK_NAME_VPU_INTR "VPU_INTR"
+#define GCLK_DEV_VPU_INTR "CLKGATE_VPU_INTR"
+#define GCLK_REG_VPU_INTR (HHI_GCLK_MPEG2)
+#define GCLK_MASK_VPU_INTR (1<<25)
+
+#define GCLK_IDX_SECURE_AHP_APB3 90
+#define GCLK_NAME_SECURE_AHP_APB3 "SECURE_AHP_APB3"
+#define GCLK_DEV_SECURE_AHP_APB3 "CLKGATE_SECURE_AHP_APB3"
+#define GCLK_REG_SECURE_AHP_APB3 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_SECURE_AHP_APB3 (1<<26)
+
+#define GCLK_IDX_RESERVED2_F 91
+#define GCLK_NAME_RESERVED2_F "RESERVED2_F"
+#define GCLK_DEV_RESERVED2_F "CLKGATE_RESERVED2_F"
+#define GCLK_REG_RESERVED2_F (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_F (1<<27)
+
+#define GCLK_IDX_RESERVED2_10 92
+#define GCLK_NAME_RESERVED2_10 "RESERVED2_10"
+#define GCLK_DEV_RESERVED2_10 "CLKGATE_RESERVED2_10"
+#define GCLK_REG_RESERVED2_10 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_10 (1<<28)
+
+#define GCLK_IDX_CLK81_TO_A9 93
+#define GCLK_NAME_CLK81_TO_A9 "CLK81_TO_A9"
+#define GCLK_DEV_CLK81_TO_A9 "CLKGATE_CLK81_TO_A9"
+#define GCLK_REG_CLK81_TO_A9 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_CLK81_TO_A9 (1<<29)
+
+#define GCLK_IDX_GIC 94
+#define GCLK_NAME_GIC "GIC"
+#define GCLK_DEV_GIC "CLKGATE_GIC"
+#define GCLK_REG_GIC (HHI_GCLK_MPEG2)
+#define GCLK_MASK_GIC (1<<30)
+
+#define GCLK_IDX_RESERVED2_12 95
+#define GCLK_NAME_RESERVED2_12 "RESERVED2_12"
+#define GCLK_DEV_RESERVED2_12 "CLKGATE_RESERVED2_12"
+#define GCLK_REG_RESERVED2_12 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_12 (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_RESERVED3_0 96
+#define GCLK_NAME_RESERVED3_0 "RESERVED3_0"
+#define GCLK_DEV_RESERVED3_0 "CLKGATE_RESERVED3_0"
+#define GCLK_REG_RESERVED3_0 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_0 (1<<0)
+
+#define GCLK_IDX_VCLK2_VENCI 97
+#define GCLK_NAME_VCLK2_VENCI "VCLK2_VENCI"
+#define GCLK_DEV_VCLK2_VENCI "CLKGATE_VCLK2_VENCI"
+#define GCLK_REG_VCLK2_VENCI (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCI (1<<1)
+
+#define GCLK_IDX_VCLK2_VENCI1 98
+#define GCLK_NAME_VCLK2_VENCI1 "VCLK2_VENCI1"
+#define GCLK_DEV_VCLK2_VENCI1 "CLKGATE_VCLK2_VENCI1"
+#define GCLK_REG_VCLK2_VENCI1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCI1 (1<<2)
+
+#define GCLK_IDX_VCLK2_VENCP 99
+#define GCLK_NAME_VCLK2_VENCP "VCLK2_VENCP"
+#define GCLK_DEV_VCLK2_VENCP "CLKGATE_VCLK2_VENCP"
+#define GCLK_REG_VCLK2_VENCP (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCP (1<<3)
+
+#define GCLK_IDX_VCLK2_VENCP1 100
+#define GCLK_NAME_VCLK2_VENCP1 "VCLK2_VENCP1"
+#define GCLK_DEV_VCLK2_VENCP1 "CLKGATE_VCLK2_VENCP1"
+#define GCLK_REG_VCLK2_VENCP1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCP1 (1<<4)
+
+#define GCLK_IDX_VCLK2_VENCT 101
+#define GCLK_NAME_VCLK2_VENCT "VCLK2_VENCT"
+#define GCLK_DEV_VCLK2_VENCT "CLKGATE_VCLK2_VENCT"
+#define GCLK_REG_VCLK2_VENCT (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCT (1<<5)
+
+#define GCLK_IDX_VCLK2_VENCT1 102
+#define GCLK_NAME_VCLK2_VENCT1 "VCLK2_VENCT1"
+#define GCLK_DEV_VCLK2_VENCT1 "CLKGATE_VCLK2_VENCT1"
+#define GCLK_REG_VCLK2_VENCT1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCT1 (1<<6)
+
+#define GCLK_IDX_VCLK2_OTHER 103
+#define GCLK_NAME_VCLK2_OTHER "VCLK2_OTHER"
+#define GCLK_DEV_VCLK2_OTHER "CLKGATE_VCLK2_OTHER"
+#define GCLK_REG_VCLK2_OTHER (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_OTHER (1<<7)
+
+#define GCLK_IDX_VCLK2_ENCI 104
+#define GCLK_NAME_VCLK2_ENCI "VCLK2_ENCI"
+#define GCLK_DEV_VCLK2_ENCI "CLKGATE_VCLK2_ENCI"
+#define GCLK_REG_VCLK2_ENCI (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCI (1<<8)
+
+#define GCLK_IDX_VCLK2_ENCP 105
+#define GCLK_NAME_VCLK2_ENCP "VCLK2_ENCP"
+#define GCLK_DEV_VCLK2_ENCP "CLKGATE_VCLK2_ENCP"
+#define GCLK_REG_VCLK2_ENCP (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCP (1<<9)
+
+#define GCLK_IDX_DAC_CLK 106
+#define GCLK_NAME_DAC_CLK "DAC_CLK"
+#define GCLK_DEV_DAC_CLK "CLKGATE_DAC_CLK"
+#define GCLK_REG_DAC_CLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_DAC_CLK (1<<10)
+
+#define GCLK_IDX_RESERVED3_1 107
+#define GCLK_NAME_RESERVED3_1 "RESERVED3_1"
+#define GCLK_DEV_RESERVED3_1 "CLKGATE_RESERVED3_1"
+#define GCLK_REG_RESERVED3_1 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_1 (1<<11)
+
+#define GCLK_IDX_RESERVED3_2 108
+#define GCLK_NAME_RESERVED3_2 "RESERVED3_2"
+#define GCLK_DEV_RESERVED3_2 "CLKGATE_RESERVED3_2"
+#define GCLK_REG_RESERVED3_2 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_2 (1<<12)
+
+#define GCLK_IDX_RESERVED3_3 109
+#define GCLK_NAME_RESERVED3_3 "RESERVED3_3"
+#define GCLK_DEV_RESERVED3_3 "CLKGATE_RESERVED3_3"
+#define GCLK_REG_RESERVED3_3 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_3 (1<<13)
+
+#define GCLK_IDX_AIU_AOCLK 110
+#define GCLK_NAME_AIU_AOCLK "AIU_AOCLK"
+#define GCLK_DEV_AIU_AOCLK "CLKGATE_AIU_AOCLK"
+#define GCLK_REG_AIU_AOCLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_AIU_AOCLK (1<<14)
+
+#define GCLK_IDX_RESERVED3_4 111
+#define GCLK_NAME_RESERVED3_4 "RESERVED3_4"
+#define GCLK_DEV_RESERVED3_4 "CLKGATE_RESERVED3_4"
+#define GCLK_REG_RESERVED3_4 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_4 (1<<15)
+
+#define GCLK_IDX_AIU_ICE958_AMCLK 112
+#define GCLK_NAME_AIU_ICE958_AMCLK "AIU_ICE958_AMCLK"
+#define GCLK_DEV_AIU_ICE958_AMCLK "CLKGATE_AIU_ICE958_AMCLK"
+#define GCLK_REG_AIU_ICE958_AMCLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_AIU_ICE958_AMCLK (1<<16)
+
+#define GCLK_IDX_RESERVED3_5 113
+#define GCLK_NAME_RESERVED3_5 "RESERVED3_5"
+#define GCLK_DEV_RESERVED3_5 "CLKGATE_RESERVED3_5"
+#define GCLK_REG_RESERVED3_5 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_5 (1<<17)
+
+#define GCLK_IDX_RESERVED3_6 114
+#define GCLK_NAME_RESERVED3_6 "RESERVED3_6"
+#define GCLK_DEV_RESERVED3_6 "CLKGATE_RESERVED3_6"
+#define GCLK_REG_RESERVED3_6 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_6 (1<<18)
+
+#define GCLK_IDX_RESERVED3_7 115
+#define GCLK_NAME_RESERVED3_7 "RESERVED3_7"
+#define GCLK_DEV_RESERVED3_7 "CLKGATE_RESERVED3_7"
+#define GCLK_REG_RESERVED3_7 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_7 (1<<19)
+
+#define GCLK_IDX_ENC480P 116
+#define GCLK_NAME_ENC480P "ENC480P"
+#define GCLK_DEV_ENC480P "CLKGATE_ENC480P"
+#define GCLK_REG_ENC480P (HHI_GCLK_OTHER)
+#define GCLK_MASK_ENC480P (1<<20)
+
+#define GCLK_IDX_RANDOM_NUM_GEN1 117
+#define GCLK_NAME_RANDOM_NUM_GEN1 "RANDOM_NUM_GEN1"
+#define GCLK_DEV_RANDOM_NUM_GEN1 "CLKGATE_RANDOM_NUM_GEN1"
+#define GCLK_REG_RANDOM_NUM_GEN1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RANDOM_NUM_GEN1 (1<<21)
+
+#define GCLK_IDX_VCLK2_ENCT 118
+#define GCLK_NAME_VCLK2_ENCT "GCLK_VENCL_INT"
+#define GCLK_DEV_VCLK2_ENCT "CLKGATE_GCLK_VENCL_INT"
+#define GCLK_REG_VCLK2_ENCT (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCT (1<<22)
+
+#define GCLK_IDX_VCLK2_ENCL 119
+#define GCLK_NAME_VCLK2_ENCL "VLKC2_ENCL"
+#define GCLK_DEV_VCLK2_ENCL "CLKGATE_VCLK2_ENCL"
+#define GCLK_REG_VCLK2_ENCL (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCL (1<<23)
+
+#define GCLK_IDX_MMC_CLK 120
+#define GCLK_NAME_MMC_CLK "MMC_CLK"
+#define GCLK_DEV_MMC_CLK "CLKGATE_MMC_CLK"
+#define GCLK_REG_MMC_CLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_MMC_CLK (1<<24)
+
+#define GCLK_IDX_VCLK2_VENCL 121
+#define GCLK_NAME_VCLK2_VENCL "VCLK2_VENCL"
+#define GCLK_DEV_VCLK2_VENCL "CLKGATE_VCLK2_VENCL"
+#define GCLK_REG_VCLK2_VENCL (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCL (1<<25)
+
+#define GCLK_IDX_VCLK2_OTHER1 122
+#define GCLK_NAME_VCLK2_OTHER1 "VCLK2_OTHER1"
+#define GCLK_DEV_VCLK2_OTHER1 "CLKGATE_VCLK2_OTHER1"
+#define GCLK_REG_VCLK2_OTHER1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_OTHER1 (1<<26)
+
+#define GCLK_IDX_RESERVED3_9 123
+#define GCLK_NAME_RESERVED3_9 "RESERVED3_9"
+#define GCLK_DEV_RESERVED3_9 "CLKGATE_RESERVED3_9"
+#define GCLK_REG_RESERVED3_9 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_9 (1<<27)
+
+#define GCLK_IDX_RESERVED3_A 124
+#define GCLK_NAME_RESERVED3_A "RESERVED3_A"
+#define GCLK_DEV_RESERVED3_A "CLKGATE_RESERVED3_A"
+#define GCLK_REG_RESERVED3_A (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_A (1<<28)
+
+#define GCLK_IDX_RESERVED3_B 125
+#define GCLK_NAME_RESERVED3_B "RESERVED3_B"
+#define GCLK_DEV_RESERVED3_B "CLKGATE_RESERVED3_B"
+#define GCLK_REG_RESERVED3_B (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_B (1<<29)
+
+#define GCLK_IDX_RESERVED3_C 126
+#define GCLK_NAME_RESERVED3_C "RESERVED3_C"
+#define GCLK_DEV_RESERVED3_C "CLKGATE_RESERVED3_C"
+#define GCLK_REG_RESERVED3_C (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_C (1<<30)
+
+#define GCLK_IDX_EDP_CLK 127
+#define GCLK_NAME_EDP_CLK "EDP_CLK"
+#define GCLK_DEV_EDP_CLK "CLKGATE_EDP_CLK"
+#define GCLK_REG_EDP_CLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_EDP_CLK (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_MEDIA_CPU 128
+#define GCLK_NAME_MEDIA_CPU "MEDIA_CPU"
+#define GCLK_DEV_MEDIA_CPU "CLKGATE_MEDIA_CPU"
+#define GCLK_REG_MEDIA_CPU (HHI_GCLK_AO)
+#define GCLK_MASK_MEDIA_CPU (1<<0)
+
+#define GCLK_IDX_AHB_SRAM 129
+#define GCLK_NAME_AHB_SRAM "AHB_SRAM"
+#define GCLK_DEV_AHB_SRAM "CLKGATE_AHB_SRAM"
+#define GCLK_REG_AHB_SRAM (HHI_GCLK_AO)
+#define GCLK_MASK_AHB_SRAM (1<<1)
+
+#define GCLK_IDX_AHB_BUS 130
+#define GCLK_NAME_AHB_BUS "AHB_BUS"
+#define GCLK_DEV_AHB_BUS "CLKGATE_AHB_BUS"
+#define GCLK_REG_AHB_BUS (HHI_GCLK_AO)
+#define GCLK_MASK_AHB_BUS (1<<2)
+
+#define GCLK_IDX_AO_REGS 131
+#define GCLK_NAME_AO_REGS "AO_REGS"
+#define GCLK_DEV_AO_REGS "CLKGATE_AO_REGS"
+#define GCLK_REG_AO_REGS (HHI_GCLK_AO)
+#define GCLK_MASK_AO_REGS (1<<3)
+
+#define GCLK_NAME_I2C_AO "I2C_AO"
+#define GCLK_REG_I2C_AO (HHI_GCLK_AO)
+#define GCLK_MASK_I2C_AO (1<<4)
+
+
+#define GCLK_IDX_CTS_ENCI 132
+#define GCLK_NAME_CTS_ENCI "CTS_ENCI"
+#define GCLK_DEV_CTS_ENCI "CLKGATE_CTS_ENCI"
+#define GCLK_REG_CTS_ENCI (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCI (1<<0)
+
+#define GCLK_IDX_CTS_ENCT 133
+#define GCLK_NAME_CTS_ENCT "CTS_ENCT"
+#define GCLK_DEV_CTS_ENCT "CLKGATE_CTS_ENCT"
+#define GCLK_REG_CTS_ENCT (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCT (1<<1)
+
+#define GCLK_IDX_CTS_ENCP 134
+#define GCLK_NAME_CTS_ENCP "CTS_ENCP"
+#define GCLK_DEV_CTS_ENCP "CLKGATE_CTS_ENCP"
+#define GCLK_REG_CTS_ENCP (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCP (1<<2)
+
+#define GCLK_IDX_CTS_ENCL 135
+#define GCLK_NAME_CTS_ENCL "CTS_ENCL"
+#define GCLK_DEV_CTS_ENCL "CLKGATE_CTS_ENCL"
+#define GCLK_REG_CTS_ENCL (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCL (1<<3)
+
+#define GCLK_IDX_CTS_VDAC 136
+#define GCLK_NAME_CTS_VDAC "CTS_VDAC"
+#define GCLK_DEV_CTS_VDAC "CLKGATE_CTS_VDAC"
+#define GCLK_REG_CTS_VDAC (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_VDAC (1<<4)
+
+#define GCLK_IDX_CTS_HDMI_TX_PIXEL 137
+#define GCLK_NAME_CTS_HDMI_TX_PIXEL "CTS_HDMI_TX_PIXEL"
+#define GCLK_DEV_CTS_HDMI_TX_PIXEL "CLKGATE_CTS_HDMI_TX_PIXEL"
+#define GCLK_REG_CTS_HDMI_TX_PIXEL (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_HDMI_TX_PIXEL (1<<5)
+
+#define GCLK_IDX_AUD 138
+#define GCLK_NAME_AUD "AUD"
+#define GCLK_DEV_AUD "CLKGATE_AUD"
+#define GCLK_REG_AUD (HHI_AUD_CLK_CNTL)
+#define GCLK_MASK_AUD (1<<23)
+
+
+#define GCLK_IDX_AUD2 138
+#define GCLK_NAME_AUD2 "AUD2"
+#define GCLK_DEV_AUD2 "CLKGATE_AUD2"
+#define GCLK_REG_AUD2 (HHI_AUD_CLK_CNTL)
+#define GCLK_MASK_AUD2 (1<<8)
+
+
+#define GCLK_NAME_AUD_CLK_2 "AUD_CLK_2"
+#define GCLK_REG_AUD_CLK_2 (HHI_AUD_CLK_CNTL2)
+#define GCLK_MASK_AUD_CLK_2 (1<<8)
+
+#define GCLK_IDX_AUD_CLK_3 138
+#define GCLK_NAME_AUD_CLK_3 "AUD_CLK"
+#define GCLK_DEV_AUD_CLK_3 "CLKGATE_AUD_CLK"
+#define GCLK_REG_AUD_CLK_3 (HHI_AUD_CLK_CNTL3)
+#define GCLK_MASK_AUD_CLK_3 (1<<16)
+
+#define GCLK_IDX_LCD_AN_PHY2 139
+#define GCLK_NAME_LCD_AN_PHY2 "LCD_AN_PHY2"
+#define GCLK_DEV_LCD_AN_PHY2 "CLKGATE_LCD_AN_PHY2"
+#define GCLK_REG_LCD_AN_PHY2 (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_LCD_AN_PHY2 (1<<7)
+
+#define GCLK_IDX_LCD_AN_PHY3 140
+#define GCLK_NAME_LCD_AN_PHY3 "LCD_AN_PHY3"
+#define GCLK_DEV_LCD_AN_PHY3 "CLKGATE_LCD_AN_PHY3"
+#define GCLK_REG_LCD_AN_PHY3 (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_LCD_AN_PHY3 (1<<6)
+
+#define GCLK_NAME_ATV_DEMO_VDAC "ATV_DEMO_VDAC"
+#define GCLK_REG_ATV_DEMO_VDAC (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_ATV_DEMO_VDAC (1<<8)
+
+#define GCLK_IDX_HDMI_PLL_CNTL 142
+#define GCLK_NAME_HDMI_PLL_CNTL "HDMI_PLL_CNTL"
+#define GCLK_DEV_HDMI_PLL_CNTL "GATE_HDMI_PLL_CNTL"
+#define GCLK_REG_HDMI_PLL_CNTL (HHI_HDMI_PLL_CNTL)
+#define GCLK_MASK_HDMI_PLL_CNTL (1<<30)
+
+#define GCLK_NAME_HDMITX_CLK "HDMITX_CLK"
+#define GCLK_REG_HDMITX_CLK (HHI_HDMI_CLK_CNTL)
+#define GCLK_MASK_HDMITX_CLK (1<<8)
+
+
+#define GCLK_NAME_HDMITX_CLK "HDMITX_CLK"
+#define GCLK_REG_HDMITX_CLK (HHI_HDMI_CLK_CNTL)
+#define GCLK_MASK_HDMITX_CLK (1<<8)
+
+#define GCLK_IDX_VDEC_CLK_1 144
+#define GCLK_NAME_VDEC_CLK_1 "VDEC_CLK_1"
+#define GCLK_DEV_VDEC_CLK_1 "CLKGATE_VDEC_CLK_1"
+#define GCLK_REG_VDEC_CLK_1 (HHI_VDEC_CLK_CNTL)
+#define GCLK_MASK_VDEC_CLK_1 (1<<8)
+
+#define GCLK_NAME_VDEC_CLK_2 "VDEC_CLK_2"
+#define GCLK_REG_VDEC_CLK_2 (HHI_VDEC3_CLK_CNTL)
+#define GCLK_MASK_VDEC_CLK_2 (1<<8)
+
+#define GCLK_NAME_VDEC2_CLK_1 "VDEC2_CLK_1"
+#define GCLK_REG_VDEC2_CLK_1 (HHI_VDEC2_CLK_CNTL)
+#define GCLK_MASK_VDEC2_CLK_1 (1<<8)
+
+#define GCLK_NAME_VDEC2_CLK_2 "VDEC2_CLK_2"
+#define GCLK_REG_VDEC2_CLK_2 (HHI_VDEC4_CLK_CNTL)
+#define GCLK_MASK_VDEC2_CLK_2 (1<<8)
+
+#define GCLK_IDX_HCODEC_CLK_1 145
+#define GCLK_NAME_HCODEC_CLK_1 "HCODEC_CLK"
+#define GCLK_DEV_HCODEC_CLK_1 "CLKGATE_HCODEC_CLK"
+#define GCLK_REG_HCODEC_CLK_1 (HHI_VDEC_CLK_CNTL)
+#define GCLK_MASK_HCODEC_CLK_1 (1<<24)
+
+#define GCLK_NAME_HCODEC_CLK_2 "HCODEC_CLK_2"
+#define GCLK_REG_HCODEC_CLK_2 (HHI_VDEC3_CLK_CNTL)
+#define GCLK_MASK_HCODEC_CLK_2 (1<<24)
+
+#define GCLK_NAME_HEVC_CLK_1 "HCODEC_CLK_1"
+#define GCLK_REG_HEVC_CLK_1 (HHI_VDEC2_CLK_CNTL)
+#define GCLK_MASK_HEVC_CLK_1 (1<<24)
+
+#define GCLK_NAME_HEVC_CLK_2 "HEVC_CLK_2"
+#define GCLK_REG_HEVC_CLK_2 (HHI_VDEC4_CLK_CNTL)
+#define GCLK_MASK_HEVC_CLK_2 (1<<24)
+
+#define GCLK_IDX_GEN_CLK 146
+#define GCLK_NAME_GEN_CLK "GEN_CLK"
+#define GCLK_DEV_GEN_CLK "CLKGATE_HCODEC_CLK"
+#define GCLK_REG_GEN_CLK (HHI_GEN_CLK_CNTL)
+#define GCLK_MASK_GEN_CLK (1<<11)
+
+#define GCLK_NAME_VPU_CLK_1 "VPU_CLK_1"
+#define GCLK_REG_VPU_CLK_1 (HHI_VPU_CLK_CNTL)
+#define GCLK_MASK_VPU_CLK_1 (1<<8)
+
+#define GCLK_NAME_VPU_CLK_2 "VPU_CLK_2"
+#define GCLK_REG_VPU_CLK_2 (HHI_VPU_CLK_CNTL)
+#define GCLK_MASK_VPU_CLK_2 (1<<24)
+
+
+#define GCLK_NAME_VPU_CLKB "VPU_CLKB"
+#define GCLK_REG_VPU_CLKB (HHI_VPU_CLKB_CNTL)
+#define GCLK_MASK_VPU_CLKB (1<<8)
+
+#define GCLK_NAME_VAPB_CLK_1 "VAPB_CLK_1"
+#define GCLK_REG_VAPB_CLK_1 (HHI_VAPBCLK_CNTL)
+#define GCLK_MASK_VAPB_CLK_1 (1<<8)
+
+#define GCLK_NAME_VAPB_CLK_2 "VAPB_CLK_2"
+#define GCLK_REG_VAPB_CLK_2 (HHI_VAPBCLK_CNTL)
+#define GCLK_MASK_VAPB_CLK_2 (1<<24)
+
+#define GCLK_NAME_MALI_CLK_1 "MALI_CLK_1"
+#define GCLK_REG_MALI_CLK_1 (HHI_MALI_CLK_CNTL)
+#define GCLK_MASK_MALI_CLK_1 (1<<8)
+
+#define GCLK_NAME_MALI_CLK_2 "MALI_CLK_2"
+#define GCLK_REG_MALI_CLK_2 (HHI_MALI_CLK_CNTL)
+#define GCLK_MASK_MALI_CLK_2 (1<<24)
+
+#define GCLK_NAME_PWM_A_CLK "PWM_A_CLK"
+#define GCLK_REG_PWM_A_CLK (CBUS_REG_ADDR(0x2156))
+#define GCLK_MASK_PWM_A_CLK (1<<15)
+
+#define GCLK_NAME_PWM_B_CLK "PWM_B_CLK"
+#define GCLK_REG_PWM_B_CLK (CBUS_REG_ADDR(0x2156))
+#define GCLK_MASK_PWM_B_CLK (1<<23)
+
+#define GCLK_NAME_PWM_C_CLK "PWM_C_CLK"
+#define GCLK_REG_PWM_C_CLK (CBUS_REG_ADDR(0x2196))
+#define GCLK_MASK_PWM_C_CLK (1<<15)
+
+#define GCLK_NAME_PWM_D_CLK "PWM_D_CLK"
+#define GCLK_REG_PWM_D_CLK (CBUS_REG_ADDR(0x2196))
+#define GCLK_MASK_PWM_D_CLK (1<<23)
+
+#define GCLK_NAME_PWM_E_CLK "PWM_E_CLK"
+#define GCLK_REG_PWM_E_CLK (CBUS_REG_ADDR(0x21b2))
+#define GCLK_MASK_PWM_E_CLK (1<<15)
+
+#define GCLK_NAME_PWM_F_CLK "PWM_D_CLK"
+#define GCLK_REG_PWM_F_CLK (CBUS_REG_ADDR(0x21b2))
+#define GCLK_MASK_PWM_F_CLK (1<<23)
+
+#define GCLK_NAME_VDIN_MEAS_CLK "VDIN_MEAS_CLK"
+#define GCLK_REG_VDIN_MEAS_CLK (HHI_VDIN_MEAS_CLK_CNTL)
+#define GCLK_MASK_VDIN_MEAS_CLK (1<<8)
+
+#define GCLK_NAME_MSR_CLK "MSR_CLK"
+#define GCLK_REG_MSR_CLK (CBUS_REG_ADDR(0x21d7))
+#define GCLK_MASK_MSR_CLK (1<<19)
+
+#define GCLK_NAME_MSR_HS_CLK "MSR_HS_CLK"
+#define GCLK_REG_MSR_HS_CLK (CBUS_REG_ADDR(0x21d9))
+#define GCLK_MASK_MSR_HS_CLK (1<<28)
+
+#define GCLK_NAME_32K_CLK "32K_CLK"
+#define GCLK_REG_32K_CLK (HHI_32K_CLK_CNTL)
+#define GCLK_MASK_32K_CLK (1<<15)
+
+
+
+#define GCLK_IDX_MAX 200
+
+extern short GCLK_ref[GCLK_IDX_MAX];
+
+#define REGISTER_CLK(_MOD) \
+static struct clk CLK_##_MOD = { \
+ .name = GCLK_NAME_##_MOD, \
+ .clock_index = GCLK_IDX_##_MOD, \
+ .clock_gate_reg_adr = GCLK_REG_##_MOD, \
+ .clock_gate_reg_mask = GCLK_MASK_##_MOD, \
+}
+
+#define CLK_LOOKUP_ITEM(_MOD) \
+ { \
+ .dev_id = GCLK_DEV_##_MOD, \
+ .con_id = GCLK_NAME_##_MOD, \
+ .clk = &CLK_##_MOD, \
+ }
+
+
+
+/**********************/
+/* internal audio dac control */
+#define ADAC_RESET (0x5000+0x00*4)
+#define ADAC_LATCH (0x5000+0x01*4)
+#define ADAC_POWER_CTRL_REG1 (0x5000+0x10*4)
+#define ADAC_POWER_CTRL_REG2 (0x5000+0x11*4)
+
+int audio_internal_dac_disable(void);
+
+/* video dac control */
+int video_dac_enable(unsigned char enable_mask);
+
+int video_dac_disable(void);
+
+
+#endif
diff --git a/arch/arm/mach-meson/s4/pwrc.c b/arch/arm/mach-meson/s4/pwrc.c
new file mode 100644
index 0000000..54d7603
--- /dev/null
+++ b/arch/arm/mach-meson/s4/pwrc.c
@@ -0,0 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+char* domain_name[] =
+{
+ "PM_DOS_HEVC",
+ "PM_DOS_VDEC",
+ "PM_VPU_HDMI",
+ "PM_USB_COMB",
+ "PM_GE2D",
+ "PM_ETH",
+ "PM_DEMOD",
+ "PM_AUDIO",
+};
diff --git a/arch/arm/mach-meson/s4/sdio.c b/arch/arm/mach-meson/s4/sdio.c
new file mode 100644
index 0000000..14ec635
--- /dev/null
+++ b/arch/arm/mach-meson/s4/sdio.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <asm/arch/io.h>
+#include <asm/arch/cpu_sdio.h>
+#include <asm/arch/secure_apb.h>
+#include <amlogic/cpu_id.h>
+#include <common.h>
+
+void cpu_sd_emmc_pwr_prepare(unsigned port)
+{
+}
+int cpu_sd_emmc_init(unsigned port)
+{
+ return 0;
+}
+
+/* return:
+ 0: insert
+ 1: not insert
+ */
+__weak int sd_emmc_detect(unsigned port)
+{
+ int ret = 0;
+
+ return ret;
+}
+
+
diff --git a/arch/arm/mach-meson/s4/timer.c b/arch/arm/mach-meson/s4/timer.c
new file mode 100644
index 0000000..8c16210
--- /dev/null
+++ b/arch/arm/mach-meson/s4/timer.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timer.h>
+#include <asm/types.h>
+
+uint32_t get_time(void)
+{
+ return readl(SYSCTRL_TIMERE);
+}
+
+void _udelay(unsigned int us)
+{
+#ifndef CONFIG_PXP_EMULATOR
+ unsigned int t0 = get_time();
+
+ while (get_time() - t0 <= us)
+ ;
+#endif
+}
diff --git a/arch/arm/mach-meson/s4/tsensor.c b/arch/arm/mach-meson/s4/tsensor.c
new file mode 100644
index 0000000..d037391
--- /dev/null
+++ b/arch/arm/mach-meson/s4/tsensor.c
@@ -0,0 +1,283 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <command.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/mailbox.h>
+#include <asm/arch/tsensor.h>
+#include <asm/arch/bl31_apis.h>
+#include <linux/arm-smccc.h>
+
+int tsensor_tz_calibration(unsigned int type, unsigned int data)
+{
+ int ret;
+
+ register long x0 asm("x0") = TSENSOR_CALI_SET;
+ register long x1 asm("x1") = type;
+ register long x2 asm("x2") = data;
+ register long x3 asm("x3") = 0;
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+ } while (0);
+ ret = x0;
+
+ if (!ret)
+ return -1;
+ else
+ return 0;
+}
+
+int thermal_cali_data_read(uint32_t type, uint32_t *outbuf, int32_t size)
+{
+ long sharemem_output_base = 0;
+ struct arm_smccc_res res;
+
+ sharemem_output_base = get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ arm_smccc_smc(TSENSOR_CALI_READ, type, 0, 0, 0, 0, 0, 0, &res);
+ flush_cache(sharemem_output_base, size);
+ memcpy((void *)outbuf, (void *)sharemem_output_base, size);
+ return 0;
+}
+
+int r1p1_codetotemp(unsigned long value, unsigned int u_efuse)
+{
+ int64_t temp;
+
+ temp = (value * ts_m) * (1 << 16) / (100 * (1 << 16) + ts_n * value);
+ if (u_efuse & 0x8000) {
+ temp = ((temp - (u_efuse & 0x7fff)) * ts_a / (1 << 16) - ts_b) / 10;
+ } else {
+ temp = ((temp + (u_efuse & 0x7fff)) * ts_a / (1 << 16) - ts_b) / 10;
+ }
+ return temp;
+}
+
+int r1p1_temp_read(int type)
+{
+ uint32_t ret;
+ unsigned int u_efuse;
+ unsigned int value_ts, value_all_ts;
+ int tmp = -1;
+ int i, cnt;
+ char buf[2];
+
+ switch (type) {
+ case 1:
+ /*enable thermal1*/
+ writel(T_CONTROL_DATA, TS_PLL_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL);
+ thermal_cali_data_read(1, &ret, 4);
+ printf("type: ret = %x\n", ret);
+ mdelay(5);
+ buf[0] = (ret) & 0xff;
+ buf[1] = (ret >> 8) & 0xff;
+ u_efuse = buf[1];
+ u_efuse = (u_efuse << 8) | buf[0];
+ value_ts = 0;
+ value_all_ts = 0;
+ cnt = 0;
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_PLL_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_PLL_STAT0) & 0xffff;
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ value_ts = value_all_ts / cnt;
+ printf("pll tsensor avg: 0x%x, u_efuse: 0x%x\n", value_ts, u_efuse);
+ if (value_ts == 0) {
+ printf("pll tsensor read temp is zero\n");
+ return -1;
+ }
+ tmp = r1p1_codetotemp(value_ts, u_efuse);
+ printf("temp1: %d\n", tmp);
+ break;
+ default:
+ printf("r1p1 tsensor trim type not support\n");
+ return -1;
+ }
+ return tmp;
+}
+
+unsigned int r1p1_temptocode(unsigned long value, int tempbase)
+{
+ unsigned long tmp1, tmp2, u_efuse, signbit;
+
+ printf("a b m n: %d, %d, %d, %d\n", ts_a, ts_b, ts_m, ts_n);
+ tmp1 = ((tempbase * 10 + ts_b) * (1 << 16)) / ts_a; /*ideal u*/
+ printf("%s : tmp1: 0x%lx\n", __func__, tmp1);
+ tmp2 = (ts_m * value * (1 << 16)) / ((1 << 16) * 100 + ts_n * value);
+ printf("%s : tmp2: 0x%lx\n", __func__, tmp2);
+ signbit = ((tmp1 > tmp2) ? 0 : 1);
+ u_efuse = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
+ u_efuse = (signbit << 15) | u_efuse;
+ return u_efuse;
+}
+
+int r1p1_temp_trim(int tempbase, int tempver, int type)
+{
+ unsigned int u_efuse, index_ts, index_ver;
+ unsigned int value_ts, value_all_ts;
+ int i, cnt;
+
+ printf("r1p1 temp trim type: 0x%x\n", type);
+ switch (type) {
+ case 0:
+ index_ver = 5;
+ tempver = tempver & 0x3;
+ if (tsensor_tz_calibration(index_ver, tempver) < 0)
+ printf("version tsensor thermal_calibration send error\n");
+ break;
+ case 1:
+ value_ts = 0;
+ value_all_ts = 0;
+ index_ts = 6;
+ cnt = 0;
+ /*enable thermal1*/
+ writel(T_CONTROL_DATA, TS_PLL_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL);
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_PLL_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_PLL_STAT0) & 0xffff;
+ printf("pll tsensor read: 0x%x\n", value_ts);
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ value_ts = value_all_ts / cnt;
+ printf("pll tsensor avg: 0x%x\n", value_ts);
+ if (value_ts == 0) {
+ printf("pll tsensor read temp is zero\n");
+ return -1;
+ }
+ u_efuse = r1p1_temptocode(value_ts, tempbase);
+ printf("ts efuse:%d\n", u_efuse);
+ if (u_efuse & 0x8000)
+ u_efuse = u_efuse | 0x4000;
+ u_efuse = u_efuse | 0x8000;
+ printf("ts efuse:0x%x, index: %d\n", u_efuse, index_ts);
+ if (tsensor_tz_calibration(index_ts, u_efuse) < 0) {
+ printf("pll tsensor thermal_calibration send error\n");
+ return -1;
+ }
+ break;
+ default:
+ printf("r1p1 tsensor trim type not support\n");
+ return -1;
+ break;
+ }
+ return 0;
+}
+
+int temp_read_entry(void)
+{
+ unsigned int ret, ver;
+ uint32_t data = 0;
+
+ thermal_cali_data_read(1, &data, 4);
+ ver = (data >> 24) & 0xff;
+ if (0 == (ver & T_VER_MASK)) {
+ printf("tsensor no trimmed: calidata:0x%x\n", data);
+ return -1;
+ }
+ ret = (ver & 0xf) >> 2;
+ switch (ret) {
+ case 0x0:
+ printf("temp type no support\n");
+ break;
+ case 0x2:
+ printf("temp type no support\n");
+ break;
+ case 0x1:
+ r1p1_temp_read(1);
+ printf("read the thermal\n");
+ break;
+ case 0x3:
+ printf("temp type no support\n");
+ return -1;
+ break;
+ default:
+ printf("thermal version not support!!!Please check!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int temp_trim_entry(int tempbase, int tempver)
+{
+ unsigned int ver;
+ uint32_t data;
+
+ thermal_cali_data_read(1, &data, 4);
+ ver = (data >> 24) & 0xff;
+ if (ver & T_VER_MASK) {
+ printf("tsensor trimmed: cali data: 0x%x\n", data);
+ return -1;
+ }
+
+ printf("tsensor input trim tempver, tempver:0x%x\n", tempver);
+ switch (tempver) {
+ case 0x84:
+ r1p1_temp_trim(tempbase, tempver, 1);
+ r1p1_temp_trim(tempbase, tempver, 0);
+ printf("triming the thermal by bbt-sw\n");
+ break;
+ case 0x85:
+ r1p1_temp_trim(tempbase, tempver, 1);
+ r1p1_temp_trim(tempbase, tempver, 0);
+ printf("triming the thermal by bbt-ops\n");
+ break;
+ case 0x87:
+ r1p1_temp_trim(tempbase, tempver, 1);
+ r1p1_temp_trim(tempbase, tempver, 0);
+ printf("triming the thermal by slt\n");
+ break;
+ default:
+ printf("thermal version not support!!!Please check!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int temp_cooling_entry(void)
+{
+#ifdef CONFIG_AML_TSENSOR_COOL
+ int temp;
+
+ while (1) {
+ temp = r1p1_temp_read(1);
+ if (temp <= CONFIG_HIGH_TEMP_COOL) {
+ printf("device cool done\n");
+ break;
+ }
+ mdelay(2000);
+ printf("warning: temp %d over %d, cooling\n", temp,
+ CONFIG_HIGH_TEMP_COOL);
+ }
+#endif
+ return 0;
+}
diff --git a/arch/arm/mach-meson/s4/usb.c b/arch/arm/mach-meson/s4/usb.c
new file mode 100644
index 0000000..f63052d
--- /dev/null
+++ b/arch/arm/mach-meson/s4/usb.c
@@ -0,0 +1,370 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <power/regulator.h>
+#include <clk.h>
+#include <asm/arch/usb.h>
+#include <amlogic/cpu_id.h>
+
+#include <linux/compat.h>
+#include <linux/ioport.h>
+#include <asm-generic/gpio.h>
+
+#define PHY20_RESET_LEVEL_BIT 8
+#define PHY21_RESET_LEVEL_BIT 9
+#define USB_RESET_BIT 4
+
+#define USB2_PHY_PLL_OFFSET_40 (0x09400414)
+#define USB2_PHY_PLL_OFFSET_44 (0x927E0000)
+#define USB2_PHY_PLL_OFFSET_48 (0xac5f69e5)
+
+#define USB2_PHY_PLL_OFFSET_10 (0x80000fff)
+#define USB2_PHY_PLL_OFFSET_34 (0x78000)
+#define USB2_REVB_PHY_PLL_OFFSET_34 (0x70000)
+
+#define USB2_PHY_PLL_OFFSET_38_CLEAR (0)
+#define USB2_PHY_PLL_OFFSET_38_SET (0xe0004)
+#define USB2_PHY_PLL_OFFSET_50 (0xfe18)
+#define USB2_PHY_PLL_OFFSET_54 (0x2a)
+
+#define TUNING_DISCONNECT_THRESHOLD 0x3C
+
+static struct phy usb_phys[2];
+
+int get_usbphy_baseinfo(struct phy *usb_phys)
+{
+ struct udevice *bus;
+ struct uclass *uc;
+ int ret, i;
+ int count;
+
+ if (usb_phys[0].dev && usb_phys[1].dev)
+ return 0;
+
+ ret = uclass_get(UCLASS_USB, &uc);
+ if (ret)
+ return ret;
+ uclass_foreach_dev(bus, uc) {
+ debug("bus->name=%s, bus->driver->name =%s\n",
+ bus->name, bus->driver->name);
+ count = dev_count_phandle_with_args(bus, "phys", "#phy-cells");
+ debug("usb phy count=%u\n", count);
+ if (count <= 0)
+ return count;
+ for (i = 0; i < count; i++) {
+ ret = generic_phy_get_by_index(bus, i, &usb_phys[i]);
+ if (ret && ret != -ENOENT) {
+ pr_err("Failed to get USB PHY%d for %s\n",
+ i, bus->name);
+ return ret;
+ }
+ ret = generic_phy_getinfo(&usb_phys[i]);
+ if (ret)
+ return ret;
+ }
+ }
+ return 0;
+}
+
+void usb_aml_detect_operation(int argc, char * const argv[])
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ struct phy_aml_usb3_priv *usb3_priv;
+ int ret;
+
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return;
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ usb3_priv = dev_get_priv(usb_phys[1].dev);
+
+ if (usb3_priv) {
+ printf("priv->usb3 port num = %d, config addr=0x%08x\n",
+ usb3_priv->usb3_port_num, usb3_priv->base_addr);
+ }
+ if (usb2_priv) {
+ printf("usb2 phy: config addr = 0x%08x, reset addr=0x%08x\n",
+ usb2_priv->base_addr, usb2_priv->reset_addr);
+
+ printf("usb2 phy: portnum=%d, phy-addr1= 0x%08x, phy-addr2= 0x%08x\n",
+ usb2_priv->u2_port_num, usb2_priv->usb_phy2_pll_base_addr[0],
+ usb2_priv->usb_phy2_pll_base_addr[1]);
+ printf("dwc2_a base addr: 0x%08x\n", usb2_priv->dwc2_a_addr);
+ }
+
+}
+
+#if 0
+static void set_pll_Calibration_default(uint32_t phy2_pll_base)
+{
+ u32 tmp;
+
+ //tmp = (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x8));
+ tmp = 0x7f;
+ tmp |= (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10));
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10))
+ = tmp;
+}
+#endif
+
+static void usb_set_calibration_trim(uint32_t volatile *phy2_pll_base)
+{
+ uint32_t cali, value, i;
+ uint8_t cali_en;
+
+ cali = readl(SYSCTRL_SEC_STATUS_REG12);
+ //printf("SYSCTRL_SEC_STATUS_REG12=0x%08x\n", cali);
+ /*****if cali_en ==0, set 0x10 to the default value: 0x1700****/
+ cali_en = (cali >> 12) & 0x1;
+ cali = cali >> 8;
+ if (cali_en) {
+ cali =cali & 0xf;
+ if (cali > 12)
+ cali = 12;
+ } else {
+ cali = 0x7;
+ }
+ value = (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10));
+ value &= (~0xfff);
+ for (i = 0; i < cali; i++)
+ value |= (1 << i);
+
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10))
+ = value;
+ printf("0x10 trim value=0x%08x\n", value);;
+}
+
+void usb_reset(unsigned int reset_addr, int bit){
+ *(volatile unsigned int *)(unsigned long)reset_addr = (1 << bit);
+}
+
+static void usb_enable_phy_pll (void)
+{
+ *(volatile uint32_t *)(unsigned long)RESETCTRL_RESET0_LEVEL |= (3 << PHY20_RESET_LEVEL_BIT);
+}
+
+void set_usb_pll(uint32_t phy2_pll_base)
+{
+
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))
+ = (USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET | USB_PHY2_ENABLE);
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44)) =
+ USB2_PHY_PLL_OFFSET_44;
+
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x48)) =
+ USB2_PHY_PLL_OFFSET_48;
+ udelay(100);
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x40))
+ = (((USB2_PHY_PLL_OFFSET_40) | (USB_PHY2_ENABLE))
+ & (~(USB_PHY2_RESET)));
+
+
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50))
+ = USB2_PHY_PLL_OFFSET_50;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x54))
+ = USB2_PHY_PLL_OFFSET_54;
+ usb_set_calibration_trim((uint32_t volatile *)(u64)phy2_pll_base);
+
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0xc)) =
+ TUNING_DISCONNECT_THRESHOLD;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x34))
+ = USB2_PHY_PLL_OFFSET_34;
+ debug("tuning_disconnect_threshold=0x%x\n", TUNING_DISCONNECT_THRESHOLD);
+}
+
+int usb_save_phy_dev (unsigned int number, struct phy *phy)
+{
+ usb_phys[number].dev = phy->dev;
+ usb_phys[number].id = phy->id;
+ return 0;
+}
+
+int usb2_phy_init (struct phy *phy) {
+ struct phy_aml_usb2_priv *priv = dev_get_priv(phy->dev);
+ struct u2p_aml_regs *u2p_aml_reg;
+ u2p_r0_t dev_u2p_r0;
+ u2p_r1_t dev_u2p_r1;
+ int i,cnt;
+
+ usb_save_phy_dev(0, phy);
+ usb_enable_phy_pll();
+
+ *(volatile unsigned int *)(unsigned long)priv->reset_addr = (1 << USB_RESET_BIT);
+
+ udelay(500);
+ priv->usbphy_reset_bit[0] = PHY20_RESET_LEVEL_BIT;
+ priv->usbphy_reset_bit[1] = PHY21_RESET_LEVEL_BIT;
+
+ for (i = 0; i < priv->u2_port_num; i++) {
+ u2p_aml_reg = (struct u2p_aml_regs *)((ulong)(priv->base_addr + i * PHY_REGISTER_SIZE));
+ dev_u2p_r0.d32 = u2p_aml_reg->u2p_r0;
+ dev_u2p_r0.b.host_device= 1;
+ dev_u2p_r0.b.POR= 0;
+ u2p_aml_reg->u2p_r0 = dev_u2p_r0.d32;
+ udelay(10);
+ *(volatile unsigned int *)(unsigned long)priv->reset_addr = (1 << priv->usbphy_reset_bit[i]);
+ udelay(50);
+
+ /* wait for phy ready */
+ dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
+ cnt = 0;
+ while (dev_u2p_r1.b.phy_rdy != 1) {
+ dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
+ /*we wait phy ready max 1ms, common is 100us*/
+ if (cnt > 200)
+ break;
+ else {
+ cnt++;
+ udelay(5);
+ }
+ }
+ }
+
+ for (i = 0; i < priv->u2_port_num; i++) {
+ debug("------set usb pll\n");
+ set_usb_pll(priv->usb_phy2_pll_base_addr[i]);
+ }
+ return 0;
+
+}
+
+int usb2_phy_tuning(uint32_t phy2_pll_base, int port)
+{
+ return 0;
+}
+
+/**************************************************************/
+/* device mode config */
+/**************************************************************/
+unsigned int usb_get_dwc_a_base_addr(void)
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ int ret;
+
+ if (!usb_phys[0].dev) {
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ return usb2_priv->dwc2_a_addr;
+}
+
+unsigned int usb_get_device_mode_phy_base(void)
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ int ret;
+
+ if (!usb_phys[0].dev) {
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ return usb2_priv->usb_phy2_pll_base_addr[1];
+}
+
+void usb_phy_tuning_reset(void)
+{
+ return ;
+}
+
+void usb_device_mode_init(void){
+ u2p_r0_t dev_u2p_r0;
+ u2p_r1_t dev_u2p_r1;
+
+ usb_r0_t dev_usb_r0;
+ usb_r4_t dev_usb_r4;
+ int cnt, ret;
+ u2p_aml_regs_t * u2p_aml_regs;
+ usb_aml_regs_t *usb_aml_regs;
+ struct phy_aml_usb2_priv *usb2_priv;
+ struct phy_aml_usb3_priv *usb3_priv;
+ unsigned int phy_base_addr, reset_addr;
+
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return;
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ usb3_priv = dev_get_priv(usb_phys[1].dev);
+ if (!usb2_priv || !usb3_priv) {
+ printf("get usb phy address from dts failed\n");
+ return;
+ }
+
+ u2p_aml_regs = (u2p_aml_regs_t * )((unsigned long)(usb2_priv->base_addr + PHY_REGISTER_SIZE));
+ usb_aml_regs = (usb_aml_regs_t * )((ulong)usb3_priv->base_addr);
+ phy_base_addr = usb2_priv->usb_phy2_pll_base_addr[1];
+ reset_addr = usb2_priv->reset_addr;
+
+ //printf("PHY2=0x%08x,PHY3=0x%08x\n", u2p_aml_regs, usb_aml_regs);
+ printf("PHY2=%p,PHY3=%p\n", u2p_aml_regs, usb_aml_regs);
+ if ((*(volatile uint32_t *)(unsigned long)(phy_base_addr + 0x38)) != 0) {
+ usb_phy_tuning_reset();
+ mdelay(150);
+ }
+
+ //step 1: usb controller reset
+ usb_reset(reset_addr, USB_RESET_BIT);
+
+ // step 3: enable usb INT internal USB
+ dev_usb_r0.d32 = usb_aml_regs->usb_r0;
+ dev_usb_r0.b.u2d_ss_scaledown_mode = 0;
+ dev_usb_r0.b.u2d_act = 1;
+ usb_aml_regs->usb_r0 = dev_usb_r0.d32;
+
+ // step 4: disable usb phy sleep
+ dev_usb_r4.d32 = usb_aml_regs->usb_r4;
+ dev_usb_r4.b.p21_SLEEPM0 = 1;
+ usb_aml_regs->usb_r4 = dev_usb_r4.d32;
+
+ // step 5: config phy21 device mode
+ dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0;
+ dev_u2p_r0.b.host_device= 0;
+ dev_u2p_r0.b.POR= 0;
+ u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32;
+
+ udelay(10);
+ //step 6: phy21 reset
+ usb_reset(reset_addr, PHY21_RESET_LEVEL_BIT);
+ udelay(50);
+
+ // step 6: wait for phy ready
+ dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
+ cnt = 0;
+ while ((dev_u2p_r1.d32 & 0x00000001) != 1) {
+ dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
+ if (cnt > 200)
+ break;
+ else {
+ cnt++;
+ udelay(5);
+ }
+ }
+
+ set_usb_pll(phy_base_addr);
+ //--------------------------------------------------
+
+ // ------------- usb phy21 initinal end ----------
+
+ //--------------------------------------------------
+
+}
+
diff --git a/arch/arm/mach-meson/sc2/Makefile b/arch/arm/mach-meson/sc2/Makefile
new file mode 100644
index 0000000..091200f
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/Makefile
@@ -0,0 +1,15 @@
+
+obj-y := sdio.o pinctrl_init.o
+obj-y += bl31_apis.o
+obj-y += cpu_reset.o
+obj-y += timer.o
+obj-y += mailbox.o
+#obj-y += gate_init.o
+#obj-y += power_cal.o
+obj-$(CONFIG_CMD_PLLTEST) += pll.o
+obj-$(CONFIG_CMD_AML_MTEST) += core.o
+obj-y += usb.o
+obj-$(CONFIG_AML_TSENSOR) += tsensor.o
+obj-$(CONFIG_AML_OSCRING) += oscring.o
+obj-$(CONFIG_AML_HDMITX20) += hdmitx_hw.o hdmitx_clk.o
+obj-y += aml_efuse.o
diff --git a/arch/arm/mach-meson/sc2/aml_efuse.c b/arch/arm/mach-meson/sc2/aml_efuse.c
new file mode 100644
index 0000000..9bbc421
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/aml_efuse.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ *
+ * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
+*/
+
+#include <common.h>
+#include <asm/arch/io.h>
+#include <amlogic/aml_efuse.h>
+#include <asm/arch/secure_apb.h>
+
+/*load license bit [0...127...255...511]*/
+#define OTP_BIT_LOAD(feat) (readl(OTP_LIC00 + (((feat)/32)<<2)) & (1<<((feat)%32)))
+
+#define FEAT_ENABLE_DEVICE_SCS_SIG_0 (10)
+#define FEAT_ENABLE_DEVICE_SCS_SIG_1 (11)
+#define IS_FEAT_EN_DEVICE_SCS_SIG() \
+ ((OTP_BIT_LOAD(FEAT_ENABLE_DEVICE_SCS_SIG_0) || \
+ OTP_BIT_LOAD(FEAT_ENABLE_DEVICE_SCS_SIG_1)) ? 1 : 0)
+/*check license bit*/
+#define OTP_BIT_CHECK(feat) (OTP_BIT_LOAD((feat)) ? 1 : 0)
+
+/* OTP_LIC block#3 ...*/
+#define FEAT_DISABLE_NBL2_SNOR (384+44)
+#define FEAT_DISABLE_NBL2_SNAND (384+45)
+#define FEAT_ENABLE_4BL2_SNOR (384+46)
+#define FEAT_ENABLE_8BL2_SNAND (384+47)
+#define FEAT_DISABLE_EMMC_USER (384+53)
+#define FEAT_DISABLE_EMMC_BOOT_0 (384+54)
+#define FEAT_DISABLE_EMMC_BOOT_1 (384+55)
+#define FEAT_DISABLE_NBL2_NAND (384+57)
+#define FEAT_DISABLE_8BL2_NAND (384+58)
+
+//function for EFUSE license query
+int IS_FEAT_BOOT_VERIFY(void)
+{
+ return IS_FEAT_EN_DEVICE_SCS_SIG();
+}
+
+int IS_FEAT_DIS_EMMC_USER(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_EMMC_USER);
+}
+
+int IS_FEAT_DIS_EMMC_BOOT_0(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_EMMC_BOOT_0);
+}
+
+int IS_FEAT_DIS_EMMC_BOOT_1(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_EMMC_BOOT_1);
+}
+
+int IS_FEAT_EN_4BL2_SNOR(void)
+{
+ return OTP_BIT_CHECK(FEAT_ENABLE_4BL2_SNOR);
+}
+
+int IS_FEAT_DIS_NBL2_SNOR(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_NBL2_SNOR);
+}
+
+int IS_FEAT_EN_8BL2_SNAND(void)
+{
+ return OTP_BIT_CHECK(FEAT_ENABLE_8BL2_SNAND);
+}
+
+int IS_FEAT_DIS_NBL2_SNAND(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_NBL2_SNAND);
+}
+
+int IS_FEAT_DIS_8BL2_NAND(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_8BL2_NAND);
+}
+
+int IS_FEAT_DIS_NBL2_NAND(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_NBL2_NAND);
+}
diff --git a/arch/arm/mach-meson/sc2/bl31_apis.c b/arch/arm/mach-meson/sc2/bl31_apis.c
new file mode 100644
index 0000000..9bbc004
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/bl31_apis.c
@@ -0,0 +1,578 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ * Trustzone API
+ */
+
+#include <asm/arch/io.h>
+#include <asm/arch/efuse.h>
+#include <asm/cache.h>
+#include <asm/arch/bl31_apis.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+
+static long sharemem_input_base;
+static long sharemem_output_base;
+
+long get_sharemem_info(unsigned long function_id)
+{
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ : "+r" (function_id));
+
+ return function_id;
+}
+
+int32_t set_boot_params(const keymaster_boot_params *boot_params)
+{
+ const unsigned cmd = SET_BOOT_PARAMS;
+
+ if (!boot_params)
+ return -1;
+
+ if (!sharemem_input_base)
+ sharemem_input_base =
+ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE);
+
+ memcpy((void *)sharemem_input_base,
+ (const void *)boot_params, sizeof(keymaster_boot_params));
+
+ asm __volatile__("" : : : "memory");
+ register uint64_t x0 asm("x0") = cmd;
+ register uint64_t x1 asm("x1") = sizeof(keymaster_boot_params);
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1));
+ } while (0);
+
+ return (!x0)? -1: 0;
+}
+
+#ifdef CONFIG_EFUSE
+int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg)
+{
+ int ret;
+ unsigned cmd, offset, size;
+ unsigned long *retcnt = (unsigned long *)(arg->retcnt_phy);
+
+ if (!sharemem_input_base)
+ sharemem_input_base =
+ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE);
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ if (arg->cmd == EFUSE_HAL_API_READ)
+ cmd = EFUSE_READ;
+ else if (arg->cmd == EFUSE_HAL_API_WRITE)
+ cmd = EFUSE_WRITE;
+ else
+ cmd = EFUSE_WRITE_PATTERN;
+ offset = arg->offset;
+ size = arg->size;
+
+ if (arg->cmd == EFUSE_HAL_API_WRITE)
+ memcpy((void *)sharemem_input_base,
+ (const void *)arg->buffer_phy, size);
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = cmd;
+ register uint64_t x1 asm("x1") = offset;
+ register uint64_t x2 asm("x2") = size;
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2));
+ } while (0);
+ ret = x0;
+ *retcnt = x0;
+
+ if ((arg->cmd == EFUSE_HAL_API_READ) && (ret != 0))
+ memcpy((void *)arg->buffer_phy,
+ (const void *)sharemem_output_base, ret);
+
+ if (!ret)
+ return -1;
+ else
+ return 0;
+}
+
+int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg)
+{
+ int32_t ret;
+ unsigned cmd = 0;
+
+ if (arg->cmd == EFUSE_HAL_API_USER_MAX)
+ cmd = EFUSE_USER_MAX;
+
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = cmd;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0));
+ } while (0);
+ ret = x0;
+
+ if (!ret)
+ return -1;
+ else
+ return ret;
+}
+
+ssize_t meson_trustzone_efuse_writepattern(const char *buf, size_t count)
+{
+ struct efuse_hal_api_arg arg;
+ unsigned long retcnt;
+
+ if (count != EFUSE_BYTES)
+ return 0; /* Past EOF */
+
+ arg.cmd = EFUSE_HAL_API_WRITE_PATTERN;
+ arg.offset = 0;
+ arg.size = count;
+ arg.buffer_phy = (unsigned long)buf;
+ arg.retcnt_phy = (unsigned long)&retcnt;
+ int ret;
+ ret = meson_trustzone_efuse(&arg);
+ return ret;
+}
+#endif
+
+uint64_t meson_trustzone_efuse_check(unsigned char *addr)
+{
+ uint64_t ret = 0;
+ struct sram_hal_api_arg arg = {};
+
+ arg.cmd = SRAM_HAL_API_CHECK_EFUSE;
+ arg.req_len = 0x1000000;
+ arg.res_len = 0;
+ arg.req_phy_addr = (unsigned long)addr;
+ arg.res_phy_addr = (unsigned long)NULL;
+
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = CALL_TRUSTZONE_HAL_API;
+ register uint64_t x1 asm("x1") = TRUSTZONE_HAL_API_SRAM;
+ register uint64_t x2 asm("x2") = (unsigned long)(&arg);
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2));
+ } while (0);
+
+ ret = x0;
+
+ return ret;
+}
+
+void debug_efuse_cmd(unsigned long cmd)
+{
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ : : "r" (cmd));
+}
+
+void bl31_debug_efuse_write_pattern(const char *buf)
+{
+ if (!sharemem_input_base)
+ sharemem_input_base =
+ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE);
+ memcpy((void *)sharemem_input_base, (const void *)buf, 512);
+
+ debug_efuse_cmd(DEBUG_EFUSE_WRITE_PATTERN);
+}
+
+void bl31_debug_efuse_read_pattern(char *buf)
+{
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+ debug_efuse_cmd(DEBUG_EFUSE_READ_PATTERN);
+
+ memcpy((void *)buf, (const void *)sharemem_output_base, 512);
+}
+
+void aml_set_jtag_state(unsigned state, unsigned select)
+{
+ uint64_t command;
+ if (state == JTAG_STATE_ON)
+ command = JTAG_ON;
+ else
+ command = JTAG_OFF;
+ asm __volatile__("" : : : "memory");
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : : "r" (command), "r"(select));
+}
+
+void wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value)
+{
+ register long x0 asm("x0") = 0x82000086;
+ register long x1 asm("x1") = cmd;
+ register long x2 asm("x2") = value;
+ register long x3 asm("x3") = 0;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+}
+
+unsigned aml_get_reboot_reason(void)
+{
+ unsigned reason;
+ uint64_t ret;
+
+ register uint64_t x0 asm("x0") = GET_REBOOT_REASON;
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ :"+r"(x0));
+ ret = x0;
+ reason = (unsigned)(ret&0xffffffff);
+ return reason;
+}
+
+void set_viu_probe_enable(void)
+{
+ register uint64_t x0 asm("x0") = VIU_PREOBE_EN;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ :"+r"(x0));
+}
+
+void power_set_dsp(unsigned int id, unsigned int powerflag)
+{
+ register long x0 asm("x0") = DSP_SEC_POWERSET;
+ register long x1 asm("x1") = id;
+ register long x2 asm("x2") = powerflag;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2));
+}
+
+void init_dsp(unsigned int id,unsigned int addr,unsigned int cfg0)
+{
+ register long x0 asm("x0") = START_HIFI4;
+ register long x1 asm("x1") = id;
+ register long x2 asm("x2") = addr;
+ register long x3 asm("x3") = cfg0;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+}
+
+
+unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2)
+{
+ register long x0 asm("x0") = function_id;
+ register long x1 asm("x1") = arg0;
+ register long x2 asm("x2") = arg1;
+ register long x3 asm("x3") = arg2;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+
+ return function_id;
+}
+
+/* clear boot sequence related registers */
+void aml_set_bootsequence(uint32_t val)
+{
+ register long x0 asm("x0") = SET_STORAGE_BOOTSEQUENCE;
+ register long x1 asm("x1") = val;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ :"+r"(x0)
+ : "r" (x1));
+
+ return;
+}
+
+void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2)
+{
+ register long x0 asm("x0") = function_id;
+ register long x1 asm("x1") = arg0;
+ register long x2 asm("x2") = arg1;
+ register long x3 asm("x3") = arg2;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+
+ return ;
+}
+
+unsigned long aml_sec_boot_check(unsigned long nType,
+ unsigned long pBuffer,
+ unsigned long nLength,
+ unsigned long nOption)
+{
+ uint64_t ret = 1;
+
+//#define AML_SECURE_LOG_TE
+
+#if defined(AML_SECURE_LOG_TE)
+ #define AML_GET_TE(a) do{a = *((volatile unsigned int*)0xc1109988);}while(0);
+ unsigned nT1,nT2,nT3;
+#else
+ #define AML_GET_TE(...)
+#endif
+
+ AML_GET_TE(nT1);
+
+ switch (nType) {
+ case AML_D_P_W_EFUSE_AMLOGIC:
+ case AML_D_P_W_EFUSE_SECURE_BOOT:
+ break;
+ default:
+ return 0;
+ }
+
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = AML_DATA_PROCESS;
+ register uint64_t x1 asm("x1") = nType;
+ register uint64_t x2 asm("x2") = pBuffer;
+ register uint64_t x3 asm("x3") = nLength;
+ register uint64_t x4 asm("x4") = nOption;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ __asmeq("%4", "x3")
+ __asmeq("%5", "x4")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2),"r"(x3),"r"(x4));
+ } while (0);
+
+ ret = x0;
+
+ AML_GET_TE(nT2);;
+
+ flush_dcache_range((unsigned long )pBuffer, (unsigned long )pBuffer+nLength);
+
+ AML_GET_TE(nT3);
+
+#if defined(AML_SECURE_LOG_TE)
+ printf("aml log : dec use %d(us) , flush cache used %d(us)\n",
+ nT2 - nT1, nT3 - nT2);
+#endif
+
+ return ret;
+}
+
+void set_usb_boot_function(unsigned long command)
+{
+ register long x0 asm("x0") = SET_USB_BOOT_FUNC;
+ register long x1 asm("x1") = command;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+}
+
+void set_boot_first_timeout(uint64_t arg0)
+{
+ register long x0 asm("x0") = SET_BOOT_FIRST;
+ register long x1 asm("x1") = arg0;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+}
+void aml_system_off(void)
+{
+ /* TODO: Add poweroff capability */
+ aml_reboot(0x82000042, 1, 0, 0);
+ aml_reboot(0x84000008, 0, 0, 0);
+}
+
+int __get_chip_id(unsigned char *buff, unsigned int size)
+{
+ if (buff == NULL || size < 16)
+ return -1;
+
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ if (sharemem_output_base) {
+ register long x0 asm("x0") = GET_CHIP_ID;
+ register long x1 asm("x1") = 2;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+
+ if (x0 == 0) {
+ int version = *((unsigned int *)sharemem_output_base);
+
+ if (version == 2) {
+ memcpy(buff, (void *)sharemem_output_base + 4, 16);
+ }
+ else {
+ /**
+ * Legacy 12-byte chip ID read out, transform data
+ * to expected order format.
+ */
+ uint32_t chip_info = 0;//readl(P_AO_SEC_SD_CFG8);
+ uint8_t *ch;
+ int i;
+
+ ((uint32_t *)buff)[0] =
+ ((chip_info & 0xff000000) | // Family ID
+ ((chip_info << 8) & 0xff0000) | // Chip Revision
+ ((chip_info >> 8) & 0xff00)); // Package ID
+
+ ((uint32_t *)buff)[0] = htonl(((uint32_t *)buff)[0]);
+
+ /* Transform into expected order for display */
+ ch = (uint8_t *)(sharemem_output_base + 4);
+ for (i = 0; i < 12; i++)
+ buff[i + 4] = ch[11 - i];
+ }
+
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
+int bl31_get_cornerinfo(uint8_t *outbuf, int size)
+{
+ int buff_len = 0;
+
+ if (outbuf == NULL) {
+ printf("BL33: corner efuse info storebuf is NULL\n");
+ return -1;
+ }
+
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ if (sharemem_output_base) {
+ register long x0 asm("x0") = OSCRING_EFUSE_GET;
+ register long x1 asm("x1") = size;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+ } while(0);
+ buff_len = x0;
+ if (buff_len <= size) {
+ memcpy(outbuf, (void *)sharemem_output_base, buff_len);
+ return 0;
+ } else {
+ printf("BL33: corner efuse info buf len %d over storebuf size %d\n", buff_len, size);
+ return -1;
+ }
+ }
+ return -1;
+}
+
+int32_t get_avbkey_from_fip(uint8_t *buf, uint32_t buflen)
+{
+ const unsigned cmd = GET_AVBKEY_FROM_FIP;
+ uint32_t retlen = 0;
+ uint32_t ret = 0;
+
+ if (!buf)
+ return -1;
+
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ asm __volatile__("" : : : "memory");
+ register uint64_t x0 asm("x0") = cmd;
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0));
+ } while (0);
+
+ if (!x0)
+ ret = -1;
+ retlen = x0;
+
+ if (ret != -1 && buflen >= retlen)
+ memcpy(buf, (const void *)sharemem_output_base, retlen);
+
+ return ret;
+}
diff --git a/arch/arm/mach-meson/sc2/core.c b/arch/arm/mach-meson/sc2/core.c
new file mode 100644
index 0000000..8640828
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/core.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/types.h>
+#include <asm/arch/cpu.h>
+#include <common.h>
+
+const unsigned int core_map[] = {
+ 0x0,
+ 0x1,
+ 0x2,
+ 0x3,
+};
+
+int get_core_mpidr(unsigned int cpuid)
+{
+ unsigned int coremax = (unsigned int)(sizeof(core_map)/sizeof(unsigned int));
+
+ if (cpuid >= coremax)
+ return -1;
+ return core_map[cpuid];
+}
+
+int get_core_idx(unsigned int mpidr)
+{
+ unsigned int clusterid, cpuid;
+
+ cpuid = mpidr & 0xff;
+ clusterid = mpidr & 0xff00;
+
+ cpuid += (clusterid >> 6);
+
+ if (cpuid >= NR_CPUS)
+ return -1;
+
+ return cpuid;
+}
+
+int get_core_max(void)
+{
+ return (sizeof(core_map)/sizeof(unsigned int));
+}
diff --git a/arch/arm/mach-meson/sc2/cpu_reset.c b/arch/arm/mach-meson/sc2/cpu_reset.c
new file mode 100644
index 0000000..ca0a42d
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/cpu_reset.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/types.h>
+#include <asm/arch/romboot.h>
+#include <asm/arch/cpu_reset.h>
+#include <asm/arch/io.h>
+#include <asm/arch/timer.h>
+#include <dm.h>
+#include <wdt.h>
+
+/*
+ *GPIOE_0 VDDEE_PWM
+ *GPIOE_1 VDDCPU_PWM
+ * */
+void set_pwm_to_input(void)
+{
+ //hxbao, need fine tune
+ #if 0
+ unsigned int val;
+
+ val = readl(AO_RTI_PINMUX_REG1);
+ val &= ~(0xff << 16);
+ writel(val, AO_RTI_PINMUX_REG1);/* clear pinmux */
+ val = readl(AO_GPIO_O_EN_N);
+ val &= ~(0x3 << 16);
+ val |= 0x3 << 16;
+ writel(val, AO_GPIO_O_EN_N);/* set input mode */
+ val = readl(AO_RTI_PULL_UP_EN_REG);
+ val &= ~(0x3 << 16);
+ writel(val, AO_RTI_PULL_UP_EN_REG);/* disable pull up/down */
+ #endif
+}
+
+void reset_system(void)
+{
+ struct udevice *watchdog_devp;
+ int ret;
+
+ set_pwm_to_input();
+
+ _udelay(10000); //wait print
+
+ ret = uclass_get_device_by_name(UCLASS_WDT, "watchdog", &watchdog_devp);
+ if (ret < 0) {
+ printf("failed to reset system because can't get wdt device\n");
+ return;
+ }
+ wdt_start(watchdog_devp, 0, 0);
+ while (1);
+}
+
+/* uboot reset interface */
+void reset_cpu(unsigned long flag){
+ reset_system();
+}
diff --git a/arch/arm/mach-meson/sc2/firmware/acs/Makefile b/arch/arm/mach-meson/sc2/firmware/acs/Makefile
new file mode 100644
index 0000000..01d869a
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/firmware/acs/Makefile
@@ -0,0 +1,437 @@
+#
+# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of ARM nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+#
+# Default values for build configurations
+#
+
+export CROSS_COMPILE=/opt/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-
+
+include $(buildsrc)/config.mk
+include $(buildtree)/include/autoconf.mk
+include $(buildtree)/.config
+
+# Build verbosity
+V := 0
+# Debug build
+BUILD_TYPE := ${BL2_BUILD_TYPE}
+# Build architecture
+ARCH := aarch64
+# Build platform
+#DEFAULT_PLAT := gx
+PLAT := ${SOC}
+export PLAT
+# SPD choice
+SPD := none
+# Base commit to perform code check on
+BASE_COMMIT := origin/master
+# NS timer register save and restore
+NS_TIMER_SWITCH := 0
+# By default, Bl1 acts as the reset handler, not BL31
+RESET_TO_BL31 := 0
+
+# Checkpatch ignores
+CHECK_IGNORE = --ignore COMPLEX_MACRO
+
+CHECKPATCH_ARGS = --no-tree --no-signoff ${CHECK_IGNORE}
+CHECKCODE_ARGS = --no-patch --no-tree --no-signoff ${CHECK_IGNORE}
+
+ifeq (${V},0)
+ Q=@
+ CHECKCODE_ARGS += --no-summary --terse
+else
+ Q=
+endif
+export Q
+
+ifeq (${GIT_VERSION},)
+ GIT_VERSION := $(shell git describe --abbrev=7 --dirty --always --tags)
+endif
+ifeq (${BUILDER},)
+ BUILDER := ${USER}@$(shell hostname)
+endif
+
+BL_COMMON_SOURCES := common/bl_common.c \
+ common/debug.c \
+ lib/aarch64/cache_helpers.S \
+ lib/aarch64/misc_helpers.S \
+ lib/aarch64/tlb_helpers.S \
+ lib/aarch64/xlat_helpers.c \
+ lib/stdlib/std.c \
+ lib/io_storage.c \
+ plat/common/aarch64/platform_helpers.S
+
+BUILD_BASE := $(buildtree)/firmware
+#BUILD_PLAT := ${BUILD_BASE}/${PLAT}
+BUILD_PLAT := $(buildtree)/board/${BOARDDIR}/firmware
+#BUILD_PLAT := $(buildtree)/${BOARDDIR}/firmware
+
+# Convenience function for adding build definitions
+# $(eval $(call add_define,FOO)) will have:
+# -DFOO if $(FOO) is empty; -DFOO=$(FOO) otherwise
+define add_define
+DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
+endef
+
+# Convenience function for verifying option has a boolean value
+# $(eval $(call assert_boolean,FOO)) will assert FOO is 0 or 1
+define assert_boolean
+$(and $(patsubst 0,,$(value $(1))),$(patsubst 1,,$(value $(1))),$(error $(1) must be boolean))
+endef
+
+ifeq (${PLAT},)
+ $(error "Error: Unknown platform. Please use PLAT=<platform name> to specify the platform.")
+endif
+
+all: msg_start
+
+msg_start:
+ @echo "Building ${BOARDDIR}/acs.bin"
+
+#include plat/${PLAT}/platform.mk
+#ifdef BL2_SOURCES
+NEED_BL2 := yes
+include acs.mk
+#endif
+
+# Include SPD Makefile if one has been specified
+ifneq (${SPD},none)
+ # We expect to locate an spd.mk under the specified SPD directory
+ SPD_MAKE := $(shell m="services/spd/${SPD}/${SPD}.mk"; [ -f "$$m" ] && echo "$$m")
+
+ ifeq (${SPD_MAKE},)
+ $(error Error: No services/spd/${SPD}/${SPD}.mk located)
+ endif
+ $(info Including ${SPD_MAKE})
+ include ${SPD_MAKE}
+
+ # If there's BL32 companion for the chosen SPD, and the SPD wants to build the
+ # BL2 from source, we expect that the SPD's Makefile would set NEED_BL32
+ # variable to "yes"
+endif
+
+.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool fip
+.SUFFIXES:
+
+INCLUDES += -Iinclude/bl2 \
+ -Iinclude/bl31 \
+ -Iinclude/common \
+ -Iinclude/drivers \
+ -Iinclude/drivers/arm \
+ -Iinclude/drivers/serial \
+ -Iinclude/lib \
+ -Iinclude/lib/aarch64 \
+ -Iinclude/plat/common \
+ -Iinclude/stdlib \
+ -Iinclude/stdlib/sys \
+ ${PLAT_INCLUDES} \
+ ${SPD_INCLUDES}
+
+# Process DEBUG flag
+$(eval $(call assert_boolean,DEBUG))
+$(eval $(call add_define,DEBUG))
+ifeq (${DEBUG},0)
+ $(eval $(call add_define,NDEBUG))
+else
+CFLAGS += -g
+ASFLAGS += -g -Wa,--gdwarf-2
+endif
+
+# Process NS_TIMER_SWITCH flag
+$(eval $(call assert_boolean,NS_TIMER_SWITCH))
+$(eval $(call add_define,NS_TIMER_SWITCH))
+
+# Process RESET_TO_BL31 flag
+$(eval $(call assert_boolean,RESET_TO_BL31))
+$(eval $(call add_define,RESET_TO_BL31))
+
+VPATH_LIST = $(buildsrc)/board/$(BOARDDIR)
+#VPATH_LIST = $(buildsrc)/$(BOARDDIR)
+VPATH_LIST:=$(VPATH_LIST:%=%/firmware/)
+
+vpath %.c $(VPATH_LIST)
+
+ASFLAGS += -nostdinc -ffreestanding -Wa,--fatal-warnings \
+ -mgeneral-regs-only -D__ASSEMBLY__ \
+ ${DEFINES} ${INCLUDES}
+CFLAGS += -nostdinc -pedantic -ffreestanding -Wall \
+ -Werror -mgeneral-regs-only -std=c99 -c -Os \
+ ${DEFINES} ${INCLUDES} $(VPATH_LIST:%=-I%)
+CFLAGS += -ffunction-sections -fdata-sections
+ASFLAGS += ${FIRMWARE_CPPFLAGS}
+CFLAGS += ${FIRMWARE_CPPFLAGS}
+CFLAGS += -Wno-unused
+
+LDFLAGS += --fatal-warnings -O1
+LDFLAGS += --gc-sections
+
+OCFLAGS += -j .dev_header -j .generic_param -j .clk_param \
+ -j .misc_param -j .store_param -j .ddr_param \
+ --gap-fill 0x0
+
+CC := ${CROSS_COMPILE}gcc
+CPP := ${CROSS_COMPILE}cpp
+AS := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OC := ${CROSS_COMPILE}objcopy
+OD := ${CROSS_COMPILE}objdump
+NM := ${CROSS_COMPILE}nm
+PP := ${CROSS_COMPILE}gcc -E ${CFLAGS}
+
+# Variables for use with Firmware Image Package
+FIPTOOLPATH ?= tools/fip_create
+FIPTOOL ?= ${FIPTOOLPATH}/fip_create
+fiptool: ${FIPTOOL}
+fip: ${BUILD_PLAT}/fip.bin
+
+locate-checkpatch:
+ifndef CHECKPATCH
+ $(error "Please set CHECKPATCH to point to the Linux checkpatch.pl file, eg: CHECKPATCH=../linux/script/checkpatch.pl")
+else
+ifeq (,$(wildcard ${CHECKPATCH}))
+ $(error "The file CHECKPATCH points to cannot be found, use eg: CHECKPATCH=../linux/script/checkpatch.pl")
+endif
+endif
+
+clean:
+ @echo " CLEAN"
+ ${Q}rm -rf ${BUILD_PLAT}
+ ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
+
+realclean distclean:
+ @echo " REALCLEAN"
+ ${Q}rm -rf ${BUILD_BASE}
+ ${Q}rm -f ${CURDIR}/cscope.*
+ ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
+
+checkcodebase: locate-checkpatch
+ @echo " CHECKING STYLE"
+ @if test -d .git ; then \
+ git ls-files | while read GIT_FILE ; do ${CHECKPATCH} ${CHECKCODE_ARGS} -f $$GIT_FILE ; done ; \
+ else \
+ find . -type f -not -iwholename "*.git*" -not -iwholename "*build*" -exec ${CHECKPATCH} ${CHECKCODE_ARGS} -f {} \; ; \
+ fi
+
+checkpatch: locate-checkpatch
+ @echo " CHECKING STYLE"
+ @git format-patch --stdout ${BASE_COMMIT} | ${CHECKPATCH} ${CHECKPATCH_ARGS} - || true
+
+${FIPTOOL}:
+ ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH}
+ @echo
+ @echo "Built $@ successfully"
+ @echo
+
+define match_goals
+$(strip $(foreach goal,$(1),$(filter $(goal),$(MAKECMDGOALS))))
+endef
+
+# List of rules that involve building things
+BUILD_TARGETS := all bl1 bl2 bl31 bl32 fip
+
+# Does the list of goals specified on the command line include a build target?
+ifneq ($(call match_goals,${BUILD_TARGETS}),)
+IS_ANYTHING_TO_BUILD := 1
+endif
+
+define MAKE_C
+
+$(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2))))
+$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ)))
+
+$(OBJ) : $(2)
+ @echo " CC $$<"
+ $$(Q)$$(CC) $$(CFLAGS) -c $$< -o $$@
+
+
+$(PREREQUISITES) : $(2)
+ @echo " DEPS $$@"
+ @mkdir -p $(1)
+ $$(Q)$$(CC) $$(CFLAGS) -M -MT $(OBJ) -MF $$@ $$<
+
+ifdef IS_ANYTHING_TO_BUILD
+-include $(PREREQUISITES)
+endif
+
+endef
+
+
+define MAKE_S
+
+$(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2))))
+$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ)))
+
+$(OBJ) : $(2)
+ @echo " AS $$<"
+ $$(Q)$$(AS) $$(ASFLAGS) -c $$< -o $$@
+
+$(PREREQUISITES) : $(2)
+ @echo " DEPS $$@"
+ @mkdir -p $(1)
+ $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(OBJ) -MF $$@ $$<
+
+ifdef IS_ANYTHING_TO_BUILD
+-include $(PREREQUISITES)
+endif
+
+endef
+
+
+define MAKE_LD
+
+$(eval PREREQUISITES := $(1).d)
+
+$(1) : $(2)
+ @echo " PP $$<"
+ $$(Q)$$(AS) $$(ASFLAGS) -P -E -o $$@ $$<
+
+$(PREREQUISITES) : $(2)
+ @echo " DEPS $$@"
+ @mkdir -p $$(dir $$@)
+ $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(1) -MF $$@ $$<
+
+ifdef IS_ANYTHING_TO_BUILD
+-include $(PREREQUISITES)
+endif
+
+endef
+
+
+define MAKE_OBJS
+ $(eval C_OBJS := $(filter %.c,$(2)))
+ $(eval REMAIN := $(filter-out %.c,$(2)))
+ $(eval $(foreach obj,$(C_OBJS),$(call MAKE_C,$(1),$(obj))))
+
+ $(eval S_OBJS := $(filter %.S,$(REMAIN)))
+ $(eval REMAIN := $(filter-out %.S,$(REMAIN)))
+ $(eval $(foreach obj,$(S_OBJS),$(call MAKE_S,$(1),$(obj))))
+
+ $(and $(REMAIN),$(error Unexpected source files present: $(REMAIN)))
+endef
+
+
+# NOTE: The line continuation '\' is required in the next define otherwise we
+# end up with a line-feed characer at the end of the last c filename.
+# Also bare this issue in mind if extending the list of supported filetypes.
+define SOURCES_TO_OBJS
+ $(notdir $(patsubst %.c,%.o,$(filter %.c,$(1)))) \
+ $(notdir $(patsubst %.S,%.o,$(filter %.S,$(1))))
+endef
+
+define MAKE_BL
+ $(eval BUILD_DIR := ${BUILD_PLAT})
+ $(eval SOURCES := $(SOURCES))
+ $(eval OBJS := $(addprefix $(BUILD_DIR)/,$(call SOURCES_TO_OBJS,$(SOURCES))))
+ $(eval LINKERFILE := $(BUILD_DIR)/acs.ld)
+ $(eval MAPFILE := $(BUILD_DIR)/acs.map)
+ $(eval ELF := $(BUILD_DIR)/acs.elf)
+ $(eval DUMP := $(BUILD_DIR)/acs.dump)
+ $(eval BIN := $(BUILD_DIR)/acs.bin)
+
+ $(eval $(call MAKE_OBJS,$(BUILD_DIR),$(SOURCES)))
+ $(eval $(call MAKE_LD,$(LINKERFILE),$(LINKERFILE_T)))
+
+$(BUILD_DIR) :
+ $$(Q)mkdir -p "$$@"
+
+$(ELF) : $(OBJS) $(LINKERFILE)
+ @echo " LD $$@"
+ @echo 'const char build_message[] = "Built : "__TIME__", "__DATE__". \\nver:${GIT_VERSION} - ${BUILDER}";' | \
+ $$(CC) $$(CFLAGS) -xc - -o $(BUILD_DIR)/build_message.o
+ $$(Q)$$(LD) -o $$@ $$(LDFLAGS) -Map=$(MAPFILE) --script $(LINKERFILE) \
+ $(BUILD_DIR)/build_message.o $(OBJS)
+
+$(DUMP) : $(ELF)
+ @echo " OD $$@"
+ $${Q}$${OD} -D -x $$< > $$@
+
+$(BIN) : $(ELF)
+ @echo " BIN $$@"
+ $$(Q)$$(OC) $$(OCFLAGS) -O binary $$< $$@.tmp
+ @dd if=/dev/zero of=$$@ bs=4096 count=7
+ @dd if=$$@.tmp of=$$@ conv=notrunc && rm -f $$@.tmp
+ @echo
+ @echo "Built $$@ successfully"
+ @echo
+
+.PHONY : bl$(1)
+bl$(1) : $(BUILD_DIR) $(DUMP) $(BIN)
+
+all : bl$(1)
+
+$(eval FIP_DEPS += $(if $2,$(BIN),))
+$(eval FIP_ARGS += $(if $2,--bl$(1) $(BIN),))
+
+endef
+
+ifeq (${NEED_BL2},yes)
+$(eval $(call MAKE_BL,2,in_fip))
+endif
+
+${BUILD_PLAT}/fip.bin: ${FIP_DEPS} ${BL33} ${FIPTOOL}
+ $(if ${BL33},,$(error "To build a FIP, please set BL33 to point to the Normal World binary, eg: BL33=../uefi/FVP_AARCH64_EFI.fd"))
+ ${Q}${FIPTOOL} --dump \
+ ${FIP_ARGS} \
+ --bl33 ${BL33} \
+ $@
+ @echo
+ @echo "Built $@ successfully"
+ @echo
+
+
+cscope:
+ @echo " CSCOPE"
+ ${Q}find ${CURDIR} -name "*.[chsS]" > cscope.files
+ ${Q}cscope -b -q -k
+
+help:
+ @echo "usage: ${MAKE} PLAT=<${HELP_PLATFORMS}> <all|bl1|bl2|bl31|distclean|clean|checkcodebase|checkpatch>"
+ @echo ""
+ @echo "PLAT is used to specify which platform you wish to build."
+ @echo "If no platform is specified, PLAT defaults to: ${DEFAULT_PLAT}"
+ @echo ""
+ @echo "Supported Targets:"
+ @echo " all Build the BL1, BL2 and BL31 binaries"
+ @echo " bl1 Build the BL1 binary"
+ @echo " bl2 Build the BL2 binary"
+ @echo " bl31 Build the BL31 binary"
+ @echo " checkcodebase Check the coding style of the entire source tree"
+ @echo " checkpatch Check the coding style on changes in the current"
+ @echo " branch against BASE_COMMIT (default origin/master)"
+ @echo " clean Clean the build for the selected platform"
+ @echo " cscope Generate cscope index"
+ @echo " distclean Remove all build artifacts for all platforms"
+ @echo " fiptool Build the Firmware Image Package(FIP) creation tool"
+ @echo ""
+ @echo "note: most build targets require PLAT to be set to a specific platform."
+ @echo ""
+ @echo "example: build all targets for the FVP platform:"
+ @echo " CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp all"
diff --git a/arch/arm/mach-meson/sc2/firmware/acs/acs.c b/arch/arm/mach-meson/sc2/firmware/acs/acs.c
new file mode 100644
index 0000000..f6f58e1
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/firmware/acs/acs.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <version.h>
+#include <asm/arch/acs.h>
+#include <asm/arch/timing.h>
+#include "timing.c"
+
+dev_param_hdr_t __param_hdr __attribute__ ((section(".dev_header"))) = {
+ .magic = DEV_PARAM_MAGIC,
+ .version = DEV_PARAM_VERSION,
+
+ .bl2_regs_magic = "bl2r_",
+ .bl2_regs_length = sizeof(__bl2_reg),
+
+ .board_clk_magic = "bclk_",
+ .board_clk_length = sizeof(__board_clk_setting),
+
+ .opt_reg_magic = "ops__",
+ .opt_reg_length = sizeof(__bl2_ops_reg),
+
+ .sto_set_magic = "store",
+ .sto_set_length = sizeof(__store_para),
+
+ .ddr_set_magic = "ddrs_",
+ .ddr_set_length = sizeof(__ddr_setting),
+};
+
diff --git a/arch/arm/mach-meson/sc2/firmware/acs/acs.ld.S b/arch/arm/mach-meson/sc2/firmware/acs/acs.ld.S
new file mode 100644
index 0000000..3f84ef3
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/firmware/acs/acs.ld.S
@@ -0,0 +1,55 @@
+
+OUTPUT_FORMAT("elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(acs_entry)
+
+SECTIONS
+{
+ . = 0x00007000;
+ . = ALIGN(4);
+ .entry : {
+ __RO_START__ = .;
+ *acs_entry.o(.text*)
+ *(.text*)
+ *(.data*)
+ *(.bss*)
+ }
+
+ . = 0x00000000;
+ .dev_header :
+ {
+ *(.dev_header*)
+ }
+
+ . = 0x00000200;
+ .generic_param :
+ {
+ *(.generic_param*)
+ }
+
+ . = 0x00005800;
+ .clk_param :
+ {
+ *(.clk_param*)
+ }
+
+ . = 0x00005c00;
+ .misc_param :
+ {
+ *(.misc_param*)
+ }
+
+ . = 0x00005e00;
+ .store_param :
+ {
+ *(.store_param*)
+ }
+
+ . = 0x00006000;
+ .ddr_param :
+ {
+ *(.ddr_param*)
+ }
+
+ ASSERT(. <= 0x00007000, "params image has exceeded its limit.")
+}
diff --git a/arch/arm/mach-meson/sc2/firmware/acs/acs.mk b/arch/arm/mach-meson/sc2/firmware/acs/acs.mk
new file mode 100644
index 0000000..0c63194
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/firmware/acs/acs.mk
@@ -0,0 +1,9 @@
+SOURCES += acs_entry.S
+
+ifdef CONFIG_MDUMP_COMPRESS
+SOURCES += ramdump.c
+endif
+
+SOURCES += acs.c
+
+LINKERFILE_T := acs.ld.S
diff --git a/arch/arm/mach-meson/sc2/firmware/acs/acs_entry.S b/arch/arm/mach-meson/sc2/firmware/acs/acs_entry.S
new file mode 100644
index 0000000..e6ec19b
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/firmware/acs/acs_entry.S
@@ -0,0 +1,14 @@
+
+ .globl acs_entry
+
+acs_entry:
+ .word __param_hdr
+ .word __bl2_reg
+ .word __board_clk_setting
+ .word __bl2_ops_reg
+ .word __store_para
+ .word __ddr_setting
+ .rept 10
+ .word 0x0
+ .endr
+
diff --git a/arch/arm/mach-meson/sc2/firmware/bl21/Makefile b/arch/arm/mach-meson/sc2/firmware/bl21/Makefile
new file mode 100644
index 0000000..b6d7d1a
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/firmware/bl21/Makefile
@@ -0,0 +1,3 @@
+all:
+ @echo "BL21 no action for A1 "
+
diff --git a/arch/arm/mach-meson/sc2/firmware/scp_task/Makefile b/arch/arm/mach-meson/sc2/firmware/scp_task/Makefile
new file mode 100644
index 0000000..925690d
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/firmware/scp_task/Makefile
@@ -0,0 +1,3 @@
+all:
+ echo "BL301 no action for A1"
+
diff --git a/arch/arm/mach-meson/sc2/gate_init.c b/arch/arm/mach-meson/sc2/gate_init.c
new file mode 100644
index 0000000..31629f6
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/gate_init.c
@@ -0,0 +1,366 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "power_gate.h"
+
+#define SECUREBOOT_FLAG_ADDR 0xc8100228
+
+#ifdef CONFIG_AML_CVBS
+extern unsigned int cvbs_mode;
+#endif
+void ee_gate_off(void)
+{
+ printf("ee_gate_off ...\n");
+ return;
+/* int secureboot = readl(SECUREBOOT_FLAG_ADDR)&(1<<5);*/
+
+#ifdef CONFIG_AML_CVBS
+ unsigned int cvbs_opened = 0;
+#endif
+
+#ifdef CONFIG_AML_CVBS
+ if ((cvbs_mode == 0) || (cvbs_mode == 1))
+ cvbs_opened = 1;
+#endif
+
+ /*
+ //if close , audio maybe have noise
+ CLK_GATE_OFF(AUD);
+ CLK_GATE_OFF(AUD2);
+ CLK_GATE_OFF(AUD_CLK_2);
+ CLK_GATE_OFF(AUD_CLK_3);
+ */
+ CLK_GATE_OFF(AUD_IN);
+ CLK_GATE_OFF(AIU_AUD_MIXER);
+ CLK_GATE_OFF(SANA);
+
+ /*kernel will reopen */
+ CLK_GATE_OFF(CTS_ENCL);
+ /* CLK_GATE_OFF(CTS_ENCT); */
+#if 0 /* HDMITX 480i60hz/576i50hz need this gate */
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0)
+ CLK_GATE_OFF(CTS_ENCI);
+#else
+ CLK_GATE_OFF(CTS_ENCI);
+#endif
+#endif
+ /* CLK_GATE_OFF(CTS_ENCP); */
+
+ /*close cvbs clock*/
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0) {
+ CLK_GATE_OFF(DAC_CLK);
+ CLK_GATE_OFF(CTS_VDAC);
+ }
+#else
+ CLK_GATE_OFF(DAC_CLK);
+ CLK_GATE_OFF(CTS_VDAC);
+#endif
+
+ /* usb clock close */
+ CLK_GATE_OFF(USB0);
+ CLK_GATE_OFF(USB1);
+ //CLK_GATE_OFF(USB_CLK); //g12a no reg
+ CLK_GATE_OFF(MISC_USB0_TO_DDR);
+ CLK_GATE_OFF(MISC_USB1_TO_DDR);
+
+ /* uarts close */
+ CLK_GATE_OFF(UART0);
+ CLK_GATE_OFF(UART1);
+ CLK_GATE_OFF(UART2);
+ CLK_GATE_OFF(UART3);
+
+ CLK_GATE_OFF(VCLK2_VENCP);
+ CLK_GATE_OFF(VCLK2_VENCT);
+ CLK_GATE_OFF(VCLK2_VENCT1);
+ CLK_GATE_OFF(VCLK2_OTHER);
+#if 0 /* HDMITX 480i60hz/576i50hz need HHI_GCLK_OTHER[8][2] */
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0) {
+ CLK_GATE_OFF(VCLK2_VENCI);
+ CLK_GATE_OFF(VCLK2_VENCI1);
+ }
+#else
+ CLK_GATE_OFF(VCLK2_VENCI);
+ CLK_GATE_OFF(VCLK2_VENCI1);
+#endif
+#endif
+ CLK_GATE_OFF(VCLK2_VENCL);
+ CLK_GATE_OFF(VCLK2_OTHER1);
+#if 0 /* HDMITX 480i60hz/576i50hz need HHI_GCLK_OTHER[8][2] */
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0)
+ CLK_GATE_OFF(VCLK2_ENCI);
+#else
+ CLK_GATE_OFF(VCLK2_ENCI);
+#endif
+#endif
+ CLK_GATE_OFF(VCLK2_ENCL);
+ CLK_GATE_OFF(VCLK2_ENCT);
+
+ CLK_GATE_OFF(VDEC_CLK_1);
+ CLK_GATE_OFF(VDEC_CLK_2);
+ CLK_GATE_OFF(VDEC2_CLK_1);
+ CLK_GATE_OFF(VDEC2_CLK_2);
+ CLK_GATE_OFF(HCODEC_CLK_1);
+ CLK_GATE_OFF(HCODEC_CLK_2);
+ /* CLK_GATE_OFF(HEVC_CLK_1 ); */
+ /* CLK_GATE_OFF(HEVC_CLK_2 ); */
+
+ //CLK_GATE_OFF(MMC_A_PCLK); //g12a no reg
+ //CLK_GATE_OFF(MMC_B_PCLK); //g12a no reg
+ //CLK_GATE_OFF(MMC_C_PCLK); //g12a no reg
+
+ CLK_GATE_OFF(LCD_AN_PHY2);
+ CLK_GATE_OFF(LCD_AN_PHY3);
+
+ CLK_GATE_OFF(ETHERNET);
+ //CLK_GATE_OFF(ETH_CLK); //g12a no reg
+
+ CLK_GATE_OFF(GE2D);
+ CLK_GATE_OFF(GEN_CLK);
+ //CLK_GATE_OFF(PCM_MCLK); //g12a no reg
+ //CLK_GATE_OFF(PCM_SCLK); //g12a no reg
+
+
+ CLK_GATE_OFF(HIU_PARSER_TOP);
+
+
+ /* can not off nand_clk */
+ /* CLK_GATE_OFF(NAND_CLK); */
+ /*
+ //HDMI no output
+ CLK_GATE_OFF(VCLK2_VENCP1);
+ CLK_GATE_OFF(VCLK2_ENCP);
+ */
+
+ /*
+ //if OFF, HDMI will report error!
+ CLK_GATE_OFF(HDMI_PCLK);
+ CLK_GATE_OFF(HDMI_PLL_CNTL);
+ CLK_GATE_OFF(HDMITX_CLK);
+ */
+
+ /*
+ //PWM B used for VCCK,PWM D used for VDDEE,ignoring
+ CLK_GATE_OFF(PWM_A_CLK);
+ CLK_GATE_OFF(PWM_B_CLK);
+ CLK_GATE_OFF(PWM_C_CLK);
+ CLK_GATE_OFF(PWM_D_CLK);
+ CLK_GATE_OFF(PWM_E_CLK);
+ CLK_GATE_OFF(PWM_F_CLK);
+ */
+
+
+ /* can not close
+ CLK_GATE_OFF(VPU_CLK_1);
+ CLK_GATE_OFF(VPU_CLK_2);
+ CLK_GATE_OFF(VPU_CLKB);
+ CLK_GATE_OFF(MALI_CLK_1);
+ CLK_GATE_OFF(MALI_CLK_2);
+ CLK_GATE_OFF(ATV_DEMO_VDAC);
+ CLK_GATE_OFF(EMMC_A);
+ CLK_GATE_OFF(EMMC_B);
+ CLK_GATE_OFF(EMMC_C);
+ CLK_GATE_OFF(EMMC_A_CLK);
+ CLK_GATE_OFF(EMMC_B_CLK);
+
+ CLK_GATE_OFF(MSR_CLK);
+ CLK_GATE_OFF(MSR_HS_CLK);
+ CLK_GATE_OFF(32K_CLK);
+ CLK_GATE_OFF(VAPB_CLK_1);
+ CLK_GATE_OFF(VAPB_CLK_2);
+ CLK_GATE_OFF(GIC);
+ CLK_GATE_OFF(I2C_AO); //no close for to use
+ CLK_GATE_OFF(AO_CPU);
+ CLK_GATE_OFF(ASSIST_MISC);
+ CLK_GATE_OFF(HIU_PARSER);
+ CLK_GATE_OFF(PERIPHS_TOP);
+ CLK_GATE_OFF(PL310_CBUS);
+ CLK_GATE_OFF(ISA);
+ CLK_GATE_OFF(SECURE_AHP_APB3);
+ CLK_GATE_OFF(VPU_INTR);
+ CLK_GATE_OFF(MMC_PCLK); //can not close
+ CLK_GATE_OFF(AIU_PCLK);
+ //can not connect pc
+ CLK_GATE_OFF(USB_GENERAL);
+ CLK_GATE_OFF(AHB_DATA_BUS);
+ CLK_GATE_OFF(AHB_CONTROL_BUS);
+ CLK_GATE_OFF(HDMI_INTR_SYNC); //should open
+ //can't suspend @ 2nd time
+ //CLK_GATE_OFF(RESET);
+
+ // close rom
+ //disable this bit will make other cpu can not be booted.
+ //CLK_GATE_OFF(ROM_CLK);
+
+*/
+ /*************************/
+ CLK_GATE_OFF(AHB_ARB0);
+ CLK_GATE_OFF(ASYNC_FIFO);
+ CLK_GATE_OFF(STREAM);
+ CLK_GATE_OFF(RANDOM_NUM_GEN);
+ CLK_GATE_OFF(RANDOM_NUM_GEN1);
+ CLK_GATE_OFF(SMART_CARD_MPEG_DOMAIN);
+ CLK_GATE_OFF(I2C);
+ CLK_GATE_OFF(SPI);
+ CLK_GATE_OFF(SPICC);
+ CLK_GATE_OFF(DOS);
+ CLK_GATE_OFF(SAR_ADC);
+ CLK_GATE_OFF(MISC_DVIN);
+ CLK_GATE_OFF(BT656);
+ CLK_GATE_OFF(BT656_2);
+ CLK_GATE_OFF(PDM);
+
+ /* close AIU */
+ CLK_GATE_OFF(AIU_IEC958);
+ CLK_GATE_OFF(AIU_ICE958_AMCLK);
+
+ CLK_GATE_OFF(AIU_AMCLK_MEASURE);
+ CLK_GATE_OFF(AIU_AIFIFO2);
+ CLK_GATE_OFF(AIU_MIXER_REG);
+ CLK_GATE_OFF(AIU_ADC);
+ CLK_GATE_OFF(AIU_TOP_LEVEL);
+ CLK_GATE_OFF(AIU_AOCLK);
+ CLK_GATE_OFF(AIU_AI_TOP_GLUE);
+ CLK_GATE_OFF(AIU_I2S_OUT);
+
+ CLK_GATE_OFF(ENC480P);
+
+ CLK_GATE_OFF(DEMUX);
+/*
+* EFUSE/BLK_MOV clock gate must be on,
+ kernel storage ops depend on them.
+ it can be reference PD#112732
+*/
+/*
+ if (secureboot) {
+ printf("secure boot ignore [ BLK_MOV, efuse ] clk gate\n");
+ } else {
+ CLK_GATE_OFF(EFUSE);
+ CLK_GATE_OFF(BLK_MOV);
+ }
+*/
+}
+
+void ee_gate_on(void)
+{
+
+ printf("ee_gate_on ...\n");
+
+ /*
+ //if close , audio maybe have noise
+ CLK_GATE_ON(AUD);
+ CLK_GATE_ON(AUD2);
+ CLK_GATE_ON(AUD_CLK_2);
+ CLK_GATE_ON(AUD_CLK_3);
+ */
+ CLK_GATE_ON(AUD_IN);
+ CLK_GATE_ON(AIU_AUD_MIXER);
+ CLK_GATE_ON(SANA);
+
+ /*kernel will reopen */
+ CLK_GATE_ON(CTS_ENCL);
+ /* CLK_GATE_ON(CTS_ENCT); */
+ CLK_GATE_ON(CTS_ENCI);
+ /* CLK_GATE_ON(CTS_ENCP); */
+
+ /*close cvbs clock*/
+ CLK_GATE_ON(DAC_CLK);
+ CLK_GATE_ON(CTS_VDAC);
+
+ /* usb clock close */
+ CLK_GATE_ON(USB0);
+ CLK_GATE_ON(USB1);
+ //CLK_GATE_ON(USB_CLK); //g12a no reg
+ CLK_GATE_ON(MISC_USB0_TO_DDR);
+ CLK_GATE_ON(MISC_USB1_TO_DDR);
+
+ /* uarts close */
+ CLK_GATE_ON(UART0);
+ CLK_GATE_ON(UART1);
+ CLK_GATE_ON(UART2);
+ CLK_GATE_ON(UART3);
+
+ CLK_GATE_ON(VCLK2_VENCP);
+ CLK_GATE_ON(VCLK2_VENCT);
+ CLK_GATE_ON(VCLK2_VENCT1);
+ CLK_GATE_ON(VCLK2_OTHER);
+ CLK_GATE_ON(VCLK2_VENCI);
+ CLK_GATE_ON(VCLK2_VENCI1);
+ CLK_GATE_ON(VCLK2_VENCL);
+ CLK_GATE_ON(VCLK2_OTHER1);
+
+
+ CLK_GATE_ON(VCLK2_ENCI);
+ CLK_GATE_ON(VCLK2_ENCL);
+ CLK_GATE_ON(VCLK2_ENCT);
+
+ CLK_GATE_ON(VDEC_CLK_1);
+ CLK_GATE_ON(VDEC_CLK_2);
+ CLK_GATE_ON(VDEC2_CLK_1);
+ CLK_GATE_ON(VDEC2_CLK_2);
+ CLK_GATE_ON(HCODEC_CLK_1);
+ CLK_GATE_ON(HCODEC_CLK_2);
+ /* CLK_GATE_ON(HEVC_CLK_1 ); */
+ /* CLK_GATE_ON(HEVC_CLK_2 ); */
+
+ //CLK_GATE_ON(MMC_A_PCLK); //g12a no reg
+ //CLK_GATE_ON(MMC_B_PCLK); //g12a no reg
+ //CLK_GATE_ON(MMC_C_PCLK); //g12a no reg
+
+ CLK_GATE_ON(LCD_AN_PHY2);
+ CLK_GATE_ON(LCD_AN_PHY3);
+
+ CLK_GATE_ON(ETHERNET);
+ //CLK_GATE_ON(ETH_CLK); //g12a no reg
+
+ CLK_GATE_ON(GE2D);
+ CLK_GATE_ON(GEN_CLK);
+ //CLK_GATE_ON(PCM_MCLK); //g12a no reg
+ //CLK_GATE_ON(PCM_SCLK); //g12a no reg
+
+
+ CLK_GATE_ON(HIU_PARSER_TOP);
+
+ /*************************/
+ CLK_GATE_ON(AHB_ARB0);
+ CLK_GATE_ON(ASYNC_FIFO);
+ CLK_GATE_ON(STREAM);
+ CLK_GATE_ON(RANDOM_NUM_GEN);
+ CLK_GATE_ON(RANDOM_NUM_GEN1);
+ CLK_GATE_ON(SMART_CARD_MPEG_DOMAIN);
+ CLK_GATE_ON(I2C);
+ CLK_GATE_ON(SPI);
+ CLK_GATE_ON(SPICC);
+ CLK_GATE_ON(DOS);
+ CLK_GATE_ON(SAR_ADC);
+ CLK_GATE_ON(MISC_DVIN);
+ CLK_GATE_ON(BT656);
+ CLK_GATE_ON(BT656_2);
+ CLK_GATE_ON(PDM);
+
+ /* close AIU */
+ CLK_GATE_ON(AIU_IEC958);
+ CLK_GATE_ON(AIU_ICE958_AMCLK);
+
+ CLK_GATE_ON(AIU_AMCLK_MEASURE);
+ CLK_GATE_ON(AIU_AIFIFO2);
+ CLK_GATE_ON(AIU_MIXER_REG);
+ CLK_GATE_ON(AIU_ADC);
+ CLK_GATE_ON(AIU_TOP_LEVEL);
+ CLK_GATE_ON(AIU_AOCLK);
+ CLK_GATE_ON(AIU_AI_TOP_GLUE);
+ CLK_GATE_ON(AIU_I2S_OUT);
+
+ CLK_GATE_ON(ENC480P);
+
+ CLK_GATE_ON(DEMUX);
+
+ CLK_GATE_ON(EFUSE);
+ CLK_GATE_ON(BLK_MOV);
+}
+
diff --git a/arch/arm/mach-meson/sc2/gpio.c b/arch/arm/mach-meson/sc2/gpio.c
new file mode 100644
index 0000000..7332773
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/gpio.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <linux/compiler.h>
+#include <amlogic/aml_gpio.h>
+#include <asm/arch/gpio.h>
+
+struct pin_mux_desc {
+ unsigned char domain;
+ unsigned char reg;
+ unsigned char bit;
+};
+
+#define MUX_AO_DOMAIN 0
+#define MUX_EE_DOMAIN 1
+
+#define PIN_MUX(d, r, b) \
+{ \
+ .domain = d, \
+ .reg = r, \
+ .bit = b, \
+}
+
+#define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
+{ \
+ .name = n, \
+ .first = f, \
+ .last = l, \
+ .regs = { \
+ [REG_PULLEN] = { (0xff634520 + (per<<2)), peb }, \
+ [REG_PULL] = { (0xff6344e8 + (pr<<2)), pb }, \
+ [REG_DIR] = { (0xff634440 + (dr<<2)), db }, \
+ [REG_OUT] = { (0xff634440 + (or<<2)), ob }, \
+ [REG_IN] = { (0xff634440 + (ir<<2)), ib }, \
+ }, \
+ }
+#define AOBANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
+{ \
+ .name = n, \
+ .first = f, \
+ .last = l, \
+ .regs = { \
+ [REG_PULLEN] = { (0xff800024 + (per<<2)), peb }, \
+ [REG_PULL] = { (0xff800024 + (pr<<2)), pb }, \
+ [REG_DIR] = { (0xff800024 + (dr<<2)), db }, \
+ [REG_OUT] = { (0xff800024 + (or<<2)), ob }, \
+ [REG_IN] = { (0xff800024 + (ir<<2)), ib }, \
+ }, \
+ }
+
+static struct pin_mux_desc pin_to_gpio[] = {
+ [GPIOAO(GPIOAO_0)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 0),
+ [GPIOAO(GPIOAO_1)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 4),
+ [GPIOAO(GPIOAO_2)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 8),
+ [GPIOAO(GPIOAO_3)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 12),
+ [GPIOAO(GPIOAO_4)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 16),
+ [GPIOAO(GPIOAO_5)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 20),
+ [GPIOAO(GPIOAO_6)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 24),
+ [GPIOAO(GPIOAO_7)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 28),
+ [GPIOAO(GPIOAO_8)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 0),
+ [GPIOAO(GPIOAO_9)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 4),
+ [GPIOAO(GPIOAO_10)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 8),
+ [GPIOAO(GPIOAO_11)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 12),
+ [GPIOAO(GPIOE_0)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 16),
+ [GPIOAO(GPIOE_1)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 20),
+ [GPIOAO(GPIOE_2)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 24),
+ [GPIOEE(GPIOZ_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 0),
+ [GPIOEE(GPIOZ_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 4),
+ [GPIOEE(GPIOZ_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 8),
+ [GPIOEE(GPIOZ_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 12),
+ [GPIOEE(GPIOZ_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 16),
+ [GPIOEE(GPIOZ_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 20),
+ [GPIOEE(GPIOZ_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 24),
+ [GPIOEE(GPIOZ_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 28),
+ [GPIOEE(GPIOZ_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 0),
+ [GPIOEE(GPIOZ_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 4),
+ [GPIOEE(GPIOZ_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 8),
+ [GPIOEE(GPIOZ_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 12),
+ [GPIOEE(GPIOZ_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 16),
+ [GPIOEE(GPIOZ_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 20),
+ [GPIOEE(GPIOZ_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 24),
+ [GPIOEE(GPIOZ_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 28),
+ [GPIOEE(GPIOH_0)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 0),
+ [GPIOEE(GPIOH_1)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 4),
+ [GPIOEE(GPIOH_2)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 8),
+ [GPIOEE(GPIOH_3)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 12),
+ [GPIOEE(GPIOH_4)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 16),
+ [GPIOEE(GPIOH_5)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 20),
+ [GPIOEE(GPIOH_6)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 24),
+ [GPIOEE(GPIOH_7)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 28),
+ [GPIOEE(GPIOH_8)] = PIN_MUX(MUX_EE_DOMAIN, 0xc, 0),
+ [GPIOEE(BOOT_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 0),
+ [GPIOEE(BOOT_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 4),
+ [GPIOEE(BOOT_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 8),
+ [GPIOEE(BOOT_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 12),
+ [GPIOEE(BOOT_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 16),
+ [GPIOEE(BOOT_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 20),
+ [GPIOEE(BOOT_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 24),
+ [GPIOEE(BOOT_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 28),
+ [GPIOEE(BOOT_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 0),
+ [GPIOEE(BOOT_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 4),
+ [GPIOEE(BOOT_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 8),
+ [GPIOEE(BOOT_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 12),
+ [GPIOEE(BOOT_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 16),
+ [GPIOEE(BOOT_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 20),
+ [GPIOEE(BOOT_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 24),
+ [GPIOEE(BOOT_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 28),
+ [GPIOEE(GPIOC_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 0),
+ [GPIOEE(GPIOC_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 4),
+ [GPIOEE(GPIOC_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 8),
+ [GPIOEE(GPIOC_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 12),
+ [GPIOEE(GPIOC_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 16),
+ [GPIOEE(GPIOC_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 20),
+ [GPIOEE(GPIOC_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 24),
+ [GPIOEE(GPIOC_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 28),
+ [GPIOEE(GPIOA_0)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 0),
+ [GPIOEE(GPIOA_1)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 4),
+ [GPIOEE(GPIOA_2)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 8),
+ [GPIOEE(GPIOA_3)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 12),
+ [GPIOEE(GPIOA_4)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 16),
+ [GPIOEE(GPIOA_5)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 20),
+ [GPIOEE(GPIOA_6)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 24),
+ [GPIOEE(GPIOA_7)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 28),
+ [GPIOEE(GPIOA_8)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 0),
+ [GPIOEE(GPIOA_9)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 4),
+ [GPIOEE(GPIOA_10)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 8),
+ [GPIOEE(GPIOA_11)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 12),
+ [GPIOEE(GPIOA_12)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 16),
+ [GPIOEE(GPIOA_13)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 20),
+ [GPIOEE(GPIOA_14)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 24),
+ [GPIOEE(GPIOA_15)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 28),
+ [GPIOEE(GPIOX_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 0),
+ [GPIOEE(GPIOX_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 4),
+ [GPIOEE(GPIOX_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 8),
+ [GPIOEE(GPIOX_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 12),
+ [GPIOEE(GPIOX_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 16),
+ [GPIOEE(GPIOX_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 20),
+ [GPIOEE(GPIOX_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 24),
+ [GPIOEE(GPIOX_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 28),
+ [GPIOEE(GPIOX_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 0),
+ [GPIOEE(GPIOX_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 4),
+ [GPIOEE(GPIOX_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 8),
+ [GPIOEE(GPIOX_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 12),
+ [GPIOEE(GPIOX_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 16),
+ [GPIOEE(GPIOX_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 20),
+ [GPIOEE(GPIOX_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 24),
+ [GPIOEE(GPIOX_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 28),
+ [GPIOEE(GPIOX_16)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 0),
+ [GPIOEE(GPIOX_17)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 4),
+ [GPIOEE(GPIOX_18)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 8),
+ [GPIOEE(GPIOX_19)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 12),
+};
+/*sequence of banks keep same as arch-g12a/gpio.h*/
+static struct meson_bank mesontxhd_banks[] = {
+ /*name first last pullen pull dir out in*/
+ AOBANK("GPIOAO_", GPIOAO(GPIOAO_0), GPIOAO(GPIOAO_11),
+ 3, 0, 2, 0, 0, 0, 4, 0, 1, 0),
+ AOBANK("GPIOE_", GPIOAO(GPIOE_0), GPIOAO(GPIOE_2),
+ 3, 16, 2, 16, 0, 16, 4, 16, 1, 16),
+ BANK("GPIOZ_", GPIOEE(GPIOZ_0), GPIOEE(GPIOZ_15),
+ 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
+ BANK("GPIOH_", GPIOEE(GPIOH_0), GPIOEE(GPIOH_8),
+ 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
+ BANK("BOOT_", GPIOEE(BOOT_0), GPIOEE(BOOT_15),
+ 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
+ BANK("GPIOC_", GPIOEE(GPIOC_0), GPIOEE(GPIOC_7),
+ 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
+ BANK("GPIOA_", GPIOEE(GPIOA_0), GPIOEE(GPIOA_15),
+ 5, 0, 5, 0, 16, 0, 17, 0, 18, 0),
+ BANK("GPIOX_", GPIOEE(GPIOX_0), GPIOEE(GPIOX_19),
+ 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
+};
+
+U_BOOT_DEVICES(txhd_gpios) = {
+ { "gpio_aml", &mesontxhd_banks[0] },
+ { "gpio_aml", &mesontxhd_banks[1] },
+ { "gpio_aml", &mesontxhd_banks[2] },
+ { "gpio_aml", &mesontxhd_banks[3] },
+ { "gpio_aml", &mesontxhd_banks[4] },
+ { "gpio_aml", &mesontxhd_banks[5] },
+ { "gpio_aml", &mesontxhd_banks[6] },
+ { "gpio_aml", &mesontxhd_banks[7] },
+};
+
+static unsigned long domain[]={
+ [MUX_AO_DOMAIN] = 0xff800014,
+ [MUX_EE_DOMAIN] = 0xff6346c0,
+};
+
+int clear_pinmux(unsigned int pin)
+{
+ struct pin_mux_desc *pmux_desc = &pin_to_gpio[pin];
+
+ regmap_update_bits(domain[pmux_desc->domain] + (pmux_desc->reg << 2),
+ 0xf << (pmux_desc->bit), 0 << (pmux_desc->bit));
+
+ return 0;
+}
+
+#ifdef CONFIG_AML_SPICC
+#include <asm/arch/secure_apb.h>
+/* generic pins control for spicc1.
+ * if deleted, you have to add it into all g12a board files as necessary.
+ * GPIOH_4: MOSI:regB[19:16]=3
+ * GPIOH_5: MISO:regB[23:20]=3
+ * GPIOH_7: CLK:regB[31:28]=3
+ */
+int spicc1_pinctrl_enable(bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_B);
+ val &= ~(0xf0ff << 16);
+ if (enable)
+ val |= 0x3033 << 16;
+ writel(val, P_PERIPHS_PIN_MUX_B);
+ return 0;
+}
+#endif /* CONFIG_AML_SPICC */
diff --git a/arch/arm/mach-meson/sc2/hdmitx_clk.c b/arch/arm/mach-meson/sc2/hdmitx_clk.c
new file mode 100755
index 0000000..efa27e5
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/hdmitx_clk.c
@@ -0,0 +1,870 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <amlogic/media/vout/hdmitx/hdmitx.h>
+#include "hdmitx_clk.h"
+
+static uint32_t frac_rate;
+
+#define msleep(i) udelay(i*1000)
+
+#define check_clk_config(para)\
+ if (para == -1)\
+ return;
+
+#define check_div() \
+ if (div == -1)\
+ return ;\
+ switch (div) {\
+ case 1:\
+ div = 0; break;\
+ case 2:\
+ div = 1; break;\
+ case 4:\
+ div = 2; break;\
+ case 6:\
+ div = 3; break;\
+ case 12:\
+ div = 4; break;\
+ default:\
+ break;\
+ }
+
+#define WAIT_FOR_PLL_LOCKED(_reg) \
+ do { \
+ unsigned int st = 0; \
+ int cnt = 10; \
+ unsigned int reg = _reg; \
+ while (cnt--) { \
+ msleep(5); \
+ st = (((hd_read_reg(reg) >> 30) & 0x3) == 3); \
+ if (st) \
+ break; \
+ else { \
+ /* reset hpll */ \
+ hd_set_reg_bits(reg, 1, 29, 1); \
+ hd_set_reg_bits(reg, 0, 29, 1); \
+ } \
+ } \
+ if (cnt < 9) \
+ printf("pll[0x%x] reset %d times\n", reg, 9 - cnt);\
+ } while (0)
+
+static void set_hdmitx_sys_clk(void)
+{
+ hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, 0, 9, 3);
+ hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, 0, 0, 7);
+ hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, 1, 8, 1);
+}
+
+/*
+ * When VCO outputs 6.0 GHz, if VCO unlock with default v1
+ * steps, then need reset with v2 or v3
+ */
+static bool set_hpll_hclk_v1(unsigned int m, unsigned int frac_val)
+{
+ int ret = 0;
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
+
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x0b3a0400 | (m & 0xff));
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x3, 28, 2);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, frac_val);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+
+ if (frac_val == 0x8148) {
+ if (((hdev->para->vic == HDMI_3840x2160p50_16x9) ||
+ (hdev->para->vic == HDMI_3840x2160p60_16x9) ||
+ (hdev->para->vic == HDMI_3840x2160p50_64x27) ||
+ (hdev->para->vic == HDMI_3840x2160p60_64x27)) &&
+ (hdev->para->cs != HDMI_COLOR_FORMAT_420)) {
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x11551293);
+ } else {
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x44331290);
+ }
+ } else {
+ if (hdmitx_find_vendor(hdev) &&
+ ((hdev->para->vic == HDMI_3840x2160p50_16x9) ||
+ (hdev->para->vic == HDMI_3840x2160p60_16x9) ||
+ (hdev->para->vic == HDMI_3840x2160p50_64x27) ||
+ (hdev->para->vic == HDMI_3840x2160p60_64x27) ||
+ (hdev->para->vic == HDMI_4096x2160p50_256x135) ||
+ (hdev->para->vic == HDMI_4096x2160p60_256x135)) &&
+ (hdev->para->cs != HDMI_COLOR_FORMAT_420)) {
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x11551293);
+ } else {
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a68dc00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x65771290);
+ }
+ }
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39272000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+
+ ret = (((hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0) >> 30) & 0x3) == 0x3);
+ return ret; /* return hpll locked status */
+}
+
+static bool set_hpll_hclk_v2(unsigned int m, unsigned int frac_val)
+{
+ int ret = 0;
+
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x0b3a0400 | (m & 0xff));
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x3, 28, 2);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, frac_val);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0xea68dc00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x65771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39272000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+
+ ret = (((hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0) >> 30) & 0x3) == 0x3);
+ return ret; /* return hpll locked status */
+}
+
+static bool set_hpll_hclk_v3(unsigned int m, unsigned int frac_val)
+{
+ int ret = 0;
+
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x0b3a0400 | (m & 0xff));
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x3, 28, 2);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, frac_val);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0xea68dc00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x65771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39272000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x55540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+
+ ret = (((hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0) >> 30) & 0x3) == 0x3);
+ return ret; /* return hpll locked status */
+}
+
+void set_hpll_clk_out(unsigned int clk)
+{
+ pr_info("config HPLL = %d frac_rate = %d\n", clk, frac_rate);
+ switch (clk) {
+ case 5940000:
+ if (set_hpll_hclk_v1(0xf7, frac_rate ? 0x8148 : 0x10000))
+ break;
+ if (set_hpll_hclk_v2(0x7b, 0x18000))
+ break;
+ if (set_hpll_hclk_v3(0xf7, 0x10000))
+ break;
+ break;
+ case 5850000:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004f3);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00018000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 5600000:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004e9);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x0000aaab);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);/*test*/
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 5405400:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004e1);
+ if (frac_rate)
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00000000);
+ else
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00007333);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 4897000:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004cc);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x0000d560);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x43231290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x29272000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540028);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 4455000:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004b9);
+ if (frac_rate)
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x0000e10e);
+ else
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00014000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x43231290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x29272000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540028);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 4324320:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004b4);
+ if (frac_rate)
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00000000);
+ else
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00005c29);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 3712500:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b00049a);
+ if (frac_rate)
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x000110e1);
+ else
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00016000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x43231290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x29272000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540028);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 3450000:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b00048f);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00018000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 3243240:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b000487);
+ if (frac_rate)
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00000000);
+ else
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x0000451f);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 3197500:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b000485);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00007555);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 2970000:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b00047b);
+ if (frac_rate)
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x000140b4);
+ else
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00018000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 4032000:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004a8);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ default:
+ printf("error hpll clk: %d\n", clk);
+ break;
+ }
+}
+
+static void set_hpll_sspll(struct hdmitx_dev *hdev)
+{
+ enum hdmi_vic vic = hdev->vic;
+
+ switch (vic) {
+ case HDMI_1920x1080p60_16x9:
+ case HDMI_1920x1080p50_16x9:
+ case HDMI_1280x720p60_16x9:
+ case HDMI_1280x720p50_16x9:
+ case HDMI_1920x1080i60_16x9:
+ case HDMI_1920x1080i50_16x9:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 1, 29, 1);
+ /* bit[22:20] hdmi_dpll_fref_sel
+ * bit[8] hdmi_dpll_ssc_en
+ * bit[7:4] hdmi_dpll_ssc_dep_sel
+ */
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL2, 1, 20, 3);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL2, 1, 8, 1);
+ /* 2: 1000ppm 1: 500ppm */
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL2, 2, 4, 4);
+ if (hdev->dongle_mode)
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL2, 4, 4, 4);
+ /* bit[15] hdmi_dpll_sdmnc_en */
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL3, 0, 15, 1);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0, 29, 1);
+ break;
+ default:
+ break;
+ }
+}
+
+static void set_hpll_od1(unsigned div)
+{
+ switch (div) {
+ case 1:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0, 16, 2);
+ break;
+ case 2:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 1, 16, 2);
+ break;
+ case 4:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 2, 16, 2);
+ break;
+ default:
+ break;
+ }
+}
+
+static void set_hpll_od2(unsigned div)
+{
+ switch (div) {
+ case 1:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0, 18, 2);
+ break;
+ case 2:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 1, 18, 2);
+ break;
+ case 4:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 2, 18, 2);
+ break;
+ default:
+ break;
+ }
+}
+
+static void set_hpll_od3(unsigned div)
+{
+ switch (div) {
+ case 1:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0, 20, 2);
+ break;
+ case 2:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 1, 20, 2);
+ break;
+ case 4:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 2, 20, 2);
+ break;
+ default:
+ printf("Err %s[%d]\n", __func__, __LINE__);
+ break;
+ }
+}
+
+// --------------------------------------------------
+// clocks_set_vid_clk_div
+// --------------------------------------------------
+// wire clk_final_en = control[19];
+// wire clk_div1 = control[18];
+// wire [1:0] clk_sel = control[17:16];
+// wire set_preset = control[15];
+// wire [14:0] shift_preset = control[14:0];
+static void set_hpll_od3_clk_div(int div_sel)
+{
+ int shift_val = 0;
+ int shift_sel = 0;
+
+ /* When div 6.25, need to reset vid_pll_div */
+ if (div_sel == VID_PLL_DIV_6p25) {
+ msleep(1);
+ hd_write_reg(P_RESETCTRL_RESET0, 1 << 19);
+ }
+ // Disable the output clock
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 18, 2);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 15, 1);
+
+ switch (div_sel) {
+ case VID_PLL_DIV_1: shift_val = 0xFFFF; shift_sel = 0; break;
+ case VID_PLL_DIV_2: shift_val = 0x0aaa; shift_sel = 0; break;
+ case VID_PLL_DIV_3: shift_val = 0x0db6; shift_sel = 0; break;
+ case VID_PLL_DIV_3p5: shift_val = 0x36cc; shift_sel = 1; break;
+ case VID_PLL_DIV_3p75: shift_val = 0x6666; shift_sel = 2; break;
+ case VID_PLL_DIV_4: shift_val = 0x0ccc; shift_sel = 0; break;
+ case VID_PLL_DIV_5: shift_val = 0x739c; shift_sel = 2; break;
+ case VID_PLL_DIV_6: shift_val = 0x0e38; shift_sel = 0; break;
+ case VID_PLL_DIV_6p25: shift_val = 0x0000; shift_sel = 3; break;
+ case VID_PLL_DIV_7: shift_val = 0x3c78; shift_sel = 1; break;
+ case VID_PLL_DIV_7p5: shift_val = 0x78f0; shift_sel = 2; break;
+ case VID_PLL_DIV_12: shift_val = 0x0fc0; shift_sel = 0; break;
+ case VID_PLL_DIV_14: shift_val = 0x3f80; shift_sel = 1; break;
+ case VID_PLL_DIV_15: shift_val = 0x7f80; shift_sel = 2; break;
+ case VID_PLL_DIV_2p5: shift_val = 0x5294; shift_sel = 2; break;
+ case VID_PLL_DIV_3p25: shift_val = 0x66cc; shift_sel = 2; break;
+ default:
+ debug("Error: clocks_set_vid_clk_div: Invalid parameter\n");
+ break;
+ }
+
+ if (shift_val == 0xffff ) { // if divide by 1
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 1, 18, 1);
+ } else {
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 18, 1);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 16, 2);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 15, 1);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 0, 15);
+
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, shift_sel, 16, 2);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 1, 15, 1);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, shift_val, 0, 15);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 15, 1);
+ }
+ // Enable the final output clock
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 1, 19, 1);
+}
+
+static void set_vid_clk_div(unsigned div)
+{
+ check_clk_config(div);
+ if (div == 0)
+ div = 1;
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL, 0, 16, 3); // select vid_pll_clk
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_DIV, div-1, 0, 8);
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL, 7, 0, 3);
+}
+
+static void set_hdmi_tx_pixel_div(unsigned div)
+{
+ check_div();
+ hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, div, 16, 4);
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL2, 1, 5, 1); //enable gate
+}
+
+static void set_encp_div(unsigned div)
+{
+ check_div();
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_DIV, div, 24, 4);
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL2, 1, 2, 1); //enable gate
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL, 1, 19, 1);
+}
+
+static void set_enci_div(unsigned div)
+{
+ check_div();
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_DIV, div, 28, 4);
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL2, 1, 0, 1); //enable gate
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL, 1, 19, 1);
+}
+
+/* mode hpll_clk_out od1 od2(PHY) od3
+ * vid_pll_div vid_clk_div hdmi_tx_pixel_div encp_div enci_div
+ */
+/* For colordepth 8bits */
+static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
+ {{HDMI_720x480i60_4x3, HDMI_720x480i60_16x9,
+ HDMI_720x576i50_4x3, HDMI_720x576i50_16x9, GROUP_END},
+ 1, VIU_ENCI, 4324320, 4, 4, 1, VID_PLL_DIV_5, 1, 2, -1, 2},
+ {{HDMI_720x576p50_4x3, HDMI_720x576p50_16x9,
+ HDMI_720x480p60_4x3, HDMI_720x480p60_16x9, GROUP_END},
+ 1, VIU_ENCP, 4324320, 4, 4, 1, VID_PLL_DIV_5, 1, 2, 2, -1},
+ {{HDMI_720x576p100_16x9,
+ HDMI_720x480p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4324320, 4, 2, 1, VID_PLL_DIV_5, 1, 2, 2, -1},
+ {{HDMI_1280x720p50_16x9,
+ HDMI_1280x720p60_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 4, 2, 1, VID_PLL_DIV_5, 1, 2, 2, -1},
+ {{HDMI_1920x1080i60_16x9,
+ HDMI_1920x1080i50_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 4, 2, 1, VID_PLL_DIV_5, 1, 2, 2, -1},
+ {{HDMI_1920x1080i100_16x9,
+ HDMI_1920x1080i120_16x9,
+ HDMI_1280x720p100_16x9,
+ HDMI_1280x720p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 4, 1, 1, VID_PLL_DIV_5, 1, 2, 2, -1},
+ {{HDMI_1920x1080p60_16x9,
+ HDMI_1920x1080p50_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 4, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ {{HDMI_1920x1080p30_16x9,
+ HDMI_1920x1080p24_16x9,
+ HDMI_1920x1080p25_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ {{HDMI_3840x2160p30_16x9,
+ HDMI_3840x2160p25_16x9,
+ HDMI_3840x2160p24_16x9,
+ HDMI_4096x2160p24_256x135,
+ HDMI_4096x2160p25_256x135,
+ HDMI_4096x2160p30_256x135,
+ HDMI_1920x1080p100_16x9,
+ HDMI_1920x1080p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_2160x1200p90hz,
+ GROUP_END},
+ 1, VIU_ENCP, 5371100, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ {{HDMI_3840x2160p60_16x9,
+ HDMI_3840x2160p50_16x9,
+ HDMI_4096x2160p60_256x135,
+ HDMI_4096x2160p50_256x135,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 1, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ {{HDMI_4096x2160p60_256x135_Y420,
+ HDMI_4096x2160p50_256x135_Y420,
+ HDMI_3840x2160p60_16x9_Y420,
+ HDMI_3840x2160p50_16x9_Y420,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 2, 1, 1, VID_PLL_DIV_5, 1, 2, 1, -1},
+ /* pll setting for VESA modes */
+ {{HDMIV_640x480p60hz, /* 4.028G / 16 = 251.75M */
+ GROUP_END},
+ 1, VIU_ENCP, 4028000, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_800x480p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4761600, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_800x600p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 3200000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_852x480p60hz,
+ HDMIV_854x480p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4838400, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1024x600p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4032000, 4, 2, 1, VID_PLL_DIV_5, 1, 2, 2, -1},
+ {{HDMIV_1024x768p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 5200000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1280x768p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 3180000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1280x800p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 5680000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1152x864p75hz,
+ HDMIV_1280x960p60hz,
+ HDMIV_1280x1024p60hz,
+ HDMIV_1600x900p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4320000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1600x1200p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 3240000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1360x768p60hz,
+ HDMIV_1366x768p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 3420000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1400x1050p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4870000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1440x900p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4260000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1440x2560p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4897000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1440x2560p70hz,
+ GROUP_END},
+ 1, VIU_ENCP, 5600000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1680x1050p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 5850000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1920x1200p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 3865000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_2560x1600p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 3485000, 1, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {
+ {
+ HDMIV_3440x1440p60hz, GROUP_END
+ },
+ 1, VIU_ENCP, 3197500, 1, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1
+ },
+ {
+ {
+ HDMIV_2400x1200p90hz, GROUP_END
+ },
+ 1, VIU_ENCP, 5600000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1
+ },
+};
+
+/* For colordepth 10bits */
+static struct hw_enc_clk_val_group setting_enc_clk_val_30[] = {
+ {{HDMI_720x480i60_4x3, HDMI_720x480i60_16x9,
+ HDMI_720x576i50_4x3, HDMI_720x576i50_16x9, GROUP_END},
+ 1, VIU_ENCI, 5405400, 4, 4, 1, VID_PLL_DIV_6p25, 1, 2, -1, 2},
+ {{HDMI_720x576p50_4x3, HDMI_720x576p50_16x9,
+ HDMI_720x480p60_4x3, HDMI_720x480p60_16x9, GROUP_END},
+ 1, VIU_ENCP, 5405400, 4, 4, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+ {{HDMI_720x576p100_16x9,
+ HDMI_720x480p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5405400, 4, 2, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+ {{HDMI_1280x720p50_16x9,
+ HDMI_1280x720p60_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 4, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+ {{HDMI_1920x1080i60_16x9,
+ HDMI_1920x1080i50_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 4, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+ {{HDMI_1920x1080i120_16x9,
+ HDMI_1920x1080i100_16x9,
+ HDMI_1280x720p100_16x9,
+ HDMI_1280x720p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 2, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+ {{HDMI_1920x1080p60_16x9,
+ HDMI_1920x1080p50_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 1, 2, 2, VID_PLL_DIV_6p25, 1, 1, 1, -1},
+ {{HDMI_1920x1080p120_16x9,
+ HDMI_1920x1080p100_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 1, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+ {{HDMI_1920x1080p30_16x9,
+ HDMI_1920x1080p24_16x9,
+ HDMI_1920x1080p25_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 2, 2, 2, VID_PLL_DIV_6p25, 1, 1, 1, -1},
+ {{HDMI_4096x2160p60_256x135_Y420,
+ HDMI_4096x2160p50_256x135_Y420,
+ HDMI_3840x2160p60_16x9_Y420,
+ HDMI_3840x2160p50_16x9_Y420,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 1, 1, 1, VID_PLL_DIV_6p25, 1, 2, 1, -1},
+ {{HDMI_3840x2160p24_16x9,
+ HDMI_3840x2160p25_16x9,
+ HDMI_3840x2160p30_16x9,
+ HDMI_4096x2160p24_256x135,
+ HDMI_4096x2160p25_256x135,
+ HDMI_4096x2160p30_256x135,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 1, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+};
+
+/* For colordepth 12bits */
+static struct hw_enc_clk_val_group setting_enc_clk_val_36[] = {
+ {{HDMI_720x480i60_4x3, HDMI_720x480i60_16x9,
+ HDMI_720x576i50_4x3, HDMI_720x576i50_16x9, GROUP_END},
+ 1, VIU_ENCI, 3243240, 2, 4, 1, VID_PLL_DIV_7p5, 1, 2, -1, 2},
+ {{HDMI_720x576p50_4x3, HDMI_720x576p50_16x9,
+ HDMI_720x480p60_4x3, HDMI_720x480p60_16x9, GROUP_END},
+ 1, VIU_ENCP, 3243240, 2, 4, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+ {{HDMI_720x576p100_16x9,
+ HDMI_720x480p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3243240, 2, 2, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+ {{HDMI_1280x720p50_16x9,
+ HDMI_1280x720p60_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 4, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+ {{HDMI_1920x1080i60_16x9,
+ HDMI_1920x1080i50_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 4, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+ {{HDMI_1920x1080i120_16x9,
+ HDMI_1920x1080i100_16x9,
+ HDMI_1280x720p100_16x9,
+ HDMI_1280x720p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 2, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+ {{HDMI_1920x1080p60_16x9,
+ HDMI_1920x1080p50_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 1, 2, 2, VID_PLL_DIV_7p5, 1, 1, 1, -1},
+ {{HDMI_1920x1080p120_16x9,
+ HDMI_1920x1080p100_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 1, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+ {{HDMI_1920x1080p30_16x9,
+ HDMI_1920x1080p24_16x9,
+ HDMI_1920x1080p25_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 2, 2, 2, VID_PLL_DIV_7p5, 1, 1, 1, -1},
+ {{HDMI_4096x2160p60_256x135_Y420,
+ HDMI_4096x2160p50_256x135_Y420,
+ HDMI_3840x2160p60_16x9_Y420,
+ HDMI_3840x2160p50_16x9_Y420,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 1, 1, 2, VID_PLL_DIV_3p25, 1, 2, 1, -1},
+ {{HDMI_3840x2160p24_16x9,
+ HDMI_3840x2160p25_16x9,
+ HDMI_3840x2160p30_16x9,
+ HDMI_4096x2160p24_256x135,
+ HDMI_4096x2160p25_256x135,
+ HDMI_4096x2160p30_256x135,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 1, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+};
+
+static void set_hdmitx_fe_clk(struct hdmitx_dev *hdev)
+{
+ unsigned int tmp = 0;
+ enum hdmi_vic vic = hdev->vic;
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL2, 1, 9, 1);
+
+ switch (vic) {
+ case HDMI_720x480i60_16x9:
+ case HDMI_720x576i50_16x9:
+ case HDMI_720x480i60_4x3:
+ case HDMI_720x576i50_4x3:
+ tmp = (hd_read_reg(P_CLKCTRL_VID_CLK_DIV) >> 28) & 0xf;
+ break;
+ default:
+ tmp = (hd_read_reg(P_CLKCTRL_VID_CLK_DIV) >> 24) & 0xf;
+ break;
+ }
+
+ hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, tmp, 20, 4);
+}
+
+static void set_hdmitx_clk_(struct hdmitx_dev *hdev, enum hdmi_color_depth cd)
+{
+ int i = 0;
+ int j = 0;
+ struct hw_enc_clk_val_group *p_enc = NULL;
+ enum hdmi_vic vic = hdev->vic;
+ char *sspll_dis = NULL;
+
+ if (cd == HDMI_COLOR_DEPTH_24B) {
+ p_enc = &setting_enc_clk_val_24[0];
+ for (j = 0; j < ARRAY_SIZE(setting_enc_clk_val_24); j++) {
+ for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i] != GROUP_END)); i ++) {
+ if (vic == p_enc[j].group[i])
+ goto next;
+ }
+ }
+ if (j == ARRAY_SIZE(setting_enc_clk_val_24)) {
+ debug("Not find VIC = %d for hpll setting\n", vic);
+ return;
+ }
+ } else if (cd == HDMI_COLOR_DEPTH_30B) {
+ p_enc = &setting_enc_clk_val_30[0];
+ for (j = 0; j < ARRAY_SIZE(setting_enc_clk_val_30); j++) {
+ for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i] != GROUP_END)); i ++) {
+ if (vic == p_enc[j].group[i])
+ goto next;
+ }
+ }
+ if (j == ARRAY_SIZE(setting_enc_clk_val_30)) {
+ debug("Not find VIC = %d for hpll setting\n", vic);
+ return;
+ }
+ } else if (cd == HDMI_COLOR_DEPTH_36B) {
+ p_enc = &setting_enc_clk_val_36[0];
+ for (j = 0; j < ARRAY_SIZE(setting_enc_clk_val_36); j++) {
+ for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i]
+ != GROUP_END)); i++) {
+ if (vic == p_enc[j].group[i])
+ goto next;
+ }
+ }
+ if (j == ARRAY_SIZE(setting_enc_clk_val_36)) {
+ printf("Not find VIC = %d for hpll setting\n", vic);
+ return;
+ }
+ } else {
+ printf("not support colordepth 48bits\n");
+ return;
+ }
+next:
+ set_hdmitx_sys_clk();
+ set_hpll_clk_out(p_enc[j].hpll_clk_out);
+ sspll_dis = env_get("sspll_dis");
+ if ((!sspll_dis || !strcmp(sspll_dis, "0")) &&
+ (cd == HDMI_COLOR_DEPTH_24B))
+ set_hpll_sspll(hdev);
+ set_hpll_od1(p_enc[j].od1);
+ set_hpll_od2(p_enc[j].od2);
+ set_hpll_od3(p_enc[j].od3);
+ set_hpll_od3_clk_div(p_enc[j].vid_pll_div);
+ debug("j = %d vid_clk_div = %d\n", j, p_enc[j].vid_clk_div);
+ set_vid_clk_div(p_enc[j].vid_clk_div);
+ set_hdmi_tx_pixel_div(p_enc[j].hdmi_tx_pixel_div);
+ set_encp_div(p_enc[j].encp_div);
+ set_enci_div(p_enc[j].enci_div);
+ set_hdmitx_fe_clk(hdev);
+}
+
+int hdmitx_likely_frac_rate_mode(char *m)
+{
+ if (strstr(m, "24hz") || strstr(m, "30hz") || strstr(m, "60hz")
+ || strstr(m, "120hz") || strstr(m, "240hz"))
+ return 1;
+ else
+ return 0;
+}
+
+void hdmitx_set_clk(struct hdmitx_dev *hdev)
+{
+ char *frac_rate_str = NULL;
+
+ frac_rate_str = env_get("frac_rate_policy");
+ if (frac_rate_str && (frac_rate_str[0] == '0'))
+ frac_rate = 0;
+ else if (hdmitx_likely_frac_rate_mode(hdev->para->ext_name))
+ frac_rate = 1;
+ hdev->frac_rate_policy = frac_rate;
+
+ if (hdev->para->cs != HDMI_COLOR_FORMAT_422)
+ set_hdmitx_clk_(hdev, hdev->para->cd);
+ else
+ set_hdmitx_clk_(hdev, HDMI_COLOR_DEPTH_24B);
+}
+
diff --git a/arch/arm/mach-meson/sc2/hdmitx_clk.h b/arch/arm/mach-meson/sc2/hdmitx_clk.h
new file mode 100644
index 0000000..d8fda6f
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/hdmitx_clk.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __HDMITX_COMMON_H__
+#define __HDMITX_COMMON_H__
+
+#include <common.h>
+#include <amlogic/media/vout/hdmitx/hdmitx.h>
+
+#define VID_PLL_DIV_1 0
+#define VID_PLL_DIV_2 1
+#define VID_PLL_DIV_3 2
+#define VID_PLL_DIV_3p5 3
+#define VID_PLL_DIV_3p75 4
+#define VID_PLL_DIV_4 5
+#define VID_PLL_DIV_5 6
+#define VID_PLL_DIV_6 7
+#define VID_PLL_DIV_6p25 8
+#define VID_PLL_DIV_7 9
+#define VID_PLL_DIV_7p5 10
+#define VID_PLL_DIV_12 11
+#define VID_PLL_DIV_14 12
+#define VID_PLL_DIV_15 13
+#define VID_PLL_DIV_2p5 14
+#define VID_PLL_DIV_3p25 15
+
+enum viu_type {
+ VIU_ENCL = 0,
+ VIU_ENCI,
+ VIU_ENCP,
+ VIU_ENCT,
+};
+
+typedef struct{
+ enum hdmi_vic vic;
+ unsigned viu_path;
+ enum viu_type viu_type;
+ unsigned hpll_clk_out;
+ unsigned od1;
+ unsigned od2;
+ unsigned od3;
+ unsigned vid_pll_div;
+ unsigned vid_clk_div;
+ unsigned hdmi_tx_pixel_div;
+ unsigned encp_div;
+ unsigned enci_div;
+}hw_enc_clk_val_t;
+
+#define GROUP_MAX 10
+#define GROUP_END -1
+struct hw_enc_clk_val_group {
+ enum hdmi_vic group[GROUP_MAX];
+ unsigned viu_path;
+ enum viu_type viu_type;
+ unsigned hpll_clk_out;
+ unsigned od1;
+ unsigned od2;
+ unsigned od3;
+ unsigned vid_pll_div;
+ unsigned vid_clk_div;
+ unsigned hdmi_tx_pixel_div;
+ unsigned encp_div;
+ unsigned enci_div;
+};
+
+#endif
diff --git a/arch/arm/mach-meson/sc2/hdmitx_hw.c b/arch/arm/mach-meson/sc2/hdmitx_hw.c
new file mode 100644
index 0000000..51c9fbf
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/hdmitx_hw.c
@@ -0,0 +1,314 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
+#include <amlogic/media/vout/hdmitx/hdmitx_reg.h>
+#include <amlogic/media/vout/hdmitx/mach_reg.h>
+#include <asm/arch/bl31_apis.h>
+#include "hdmitx_misc.h"
+
+static struct reg_map reg_maps[] = {
+ [CBUS_REG_IDX] = { /* CBUS */
+ .base_addr = 0xfe001000,
+ },
+ [PERIPHS_REG_IDX] = { /* PERIPHS */
+ .base_addr = 0xfe004000,
+ },
+ [VCBUS_REG_IDX] = { /* VPU */
+ .base_addr = 0xff000000,
+ },
+ [HHI_REG_IDX] = { /* HIU */
+ .base_addr = 0xfe000000,
+ },
+ [SYSCTRL_REG_IDX] = {
+ .base_addr = 0xfe010000,
+ },
+ [RESETCTRL_REG_IDX] = {
+ .base_addr = 0xfe002000,
+ },
+ [ANACTRL_REG_IDX] = {
+ .base_addr = 0xfe008000,
+ },
+ [PWRCTRL_REG_IDX] = {
+ .base_addr = 0xfe00c000,
+ },
+ [HDMITX_SEC_REG_IDX] = { /* HDMITX DWC LEVEL*/
+ .base_addr = 0xfe300000,
+ },
+ [HDMITX_REG_IDX] = { /* HDMITX TOP LEVEL*/
+ .base_addr = 0xfe308000,
+ },
+ [REG_IDX_END] = {
+ },
+};
+
+#define HDMITX_DWC_BASE_OFFSET (reg_maps[HDMITX_SEC_REG_IDX].base_addr)
+#define HDMITX_TOP_BASE_OFFSET (reg_maps[HDMITX_REG_IDX].base_addr)
+
+int hdmitx_get_hpd_state(void)
+{
+ int st = 0;
+
+ st = !!(hd_read_reg(P_PADCTRL_GPIOH_I) & (1 << 2));
+ return st;
+}
+
+void hdmitx_ddc_init(void)
+{
+ /*Mux DDC SDA/SCL*/
+ hd_set_reg_bits(P_PADCTRL_PIN_MUX_REGB, 1, 0, 4);
+ hd_set_reg_bits(P_PADCTRL_PIN_MUX_REGB, 1, 4, 4);
+}
+
+static uint32_t get_base_addr(uint32_t idx)
+{
+ if (idx >= REG_IDX_END)
+ return 0;
+ if (!reg_maps[idx].base_addr)
+ printf("%s[%d] idx = %d\n", __func__, __LINE__, idx);
+
+ return reg_maps[idx].base_addr;
+}
+
+uint32_t hd_get_paddr(uint32_t addr)
+{
+ uint32_t idx = (addr) >> BASE_REG_OFFSET;
+ uint32_t offset_addr = ((1 << BASE_REG_OFFSET) - 1) & (addr);
+ uint32_t paddr;
+
+ paddr = get_base_addr(idx) + offset_addr;
+ return paddr;
+}
+
+uint32_t hd_read_reg(uint32_t addr)
+{
+ uint32_t val;
+ uint32_t idx = (addr) >> BASE_REG_OFFSET;
+ uint32_t offset_addr = ((1 << BASE_REG_OFFSET) - 1) & (addr);
+ void *paddr;
+
+ paddr = (void *)((unsigned long)(get_base_addr(idx) + offset_addr));
+ val = readl(paddr);
+
+ return val;
+}
+
+void hd_write_reg(unsigned int addr, unsigned int val)
+{
+ uint32_t idx = (addr) >> BASE_REG_OFFSET;
+ uint32_t offset_addr = ((1 << BASE_REG_OFFSET) - 1) & (addr);
+ void *paddr;
+
+ paddr = (void *)((unsigned long)(get_base_addr(idx) + offset_addr));
+ writel(val, paddr);
+}
+
+void hd_set_reg_bits(unsigned int addr, unsigned int value,
+ unsigned int offset, unsigned int len)
+{
+ unsigned int data32 = 0;
+
+ data32 = hd_read_reg(addr);
+ data32 &= ~(((1 << len) - 1) << offset);
+ data32 |= (value & ((1 << len) - 1)) << offset;
+ hd_write_reg(addr, data32);
+}
+
+static unsigned int hdmitx_rd_reg_normal(unsigned int addr)
+{
+ unsigned int data;
+ register long x0 asm("x0") = 0x82000018;
+ register long x1 asm("x1") = (unsigned long)addr;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r"(x0) : "r"(x1)
+ );
+ data = (unsigned int)(x0&0xffffffff);
+
+ return data;
+}
+
+static void hdmitx_wr_reg_normal(unsigned int addr, unsigned int data)
+{
+ register long x0 asm("x0") = 0x82000019;
+ register long x1 asm("x1") = (unsigned long)addr;
+ register long x2 asm("x2") = data;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ "smc #0\n"
+ : : "r"(x0), "r"(x1), "r"(x2)
+ );
+}
+
+unsigned int hdmitx_rd_reg(unsigned int addr)
+{
+ unsigned int large_offset = addr >> 24;
+ unsigned int small_offset = addr & ((1 << 24) - 1);
+ unsigned long hdmitx_addr = 0;
+ unsigned int data;
+
+ switch (large_offset) {
+ case 0x10:
+ /*DWC*/
+ hdmitx_addr = HDMITX_DWC_BASE_OFFSET + small_offset;
+ data = readb(hdmitx_addr);
+ break;
+ case 0x11:
+ case 0x01:
+ data = hdmitx_rd_reg_normal(addr);
+ break;
+ case 0x00:
+ default:
+ /* TOP */
+ if ((small_offset >= 0x2000) && (small_offset <= 0x365E)) {
+ hdmitx_addr = HDMITX_TOP_BASE_OFFSET + small_offset;
+ data = readb(hdmitx_addr);
+ } else {
+ hdmitx_addr = HDMITX_TOP_BASE_OFFSET + (small_offset << 2);
+ data = readl(hdmitx_addr);
+ }
+ break;
+ }
+
+ return data;
+}
+
+void hdmitx_wr_reg(unsigned int addr, unsigned int data)
+{
+ unsigned int large_offset = addr >> 24;
+ unsigned int small_offset = addr & ((1 << 24) - 1);
+ unsigned long hdmitx_addr = 0;
+
+ switch (large_offset) {
+ case 0x10:
+ /*DWC*/
+ hdmitx_addr = HDMITX_DWC_BASE_OFFSET + small_offset;
+ writeb(data & 0xff, hdmitx_addr);
+ break;
+ case 0x11:
+ case 0x01:
+ /*SECURITY DWC/TOP*/
+ hdmitx_wr_reg_normal(addr, data);
+ break;
+ case 00:
+ default:
+ /*TOP*/
+ if ((small_offset >= 0x2000) && (small_offset <= 0x365E)) {
+ hdmitx_addr = HDMITX_TOP_BASE_OFFSET + small_offset;
+ writeb(data & 0xff, hdmitx_addr);
+ } else {
+ hdmitx_addr = HDMITX_TOP_BASE_OFFSET + (small_offset << 2);
+ writel(data, hdmitx_addr);
+ }
+ }
+}
+
+void hdmitx_set_reg_bits(unsigned int addr, unsigned int value,
+ unsigned int offset, unsigned int len)
+{
+ unsigned int data32 = 0;
+
+ data32 = hdmitx_rd_reg(addr);
+ data32 &= ~(((1 << len) - 1) << offset);
+ data32 |= (value & ((1 << len) - 1)) << offset;
+ hdmitx_wr_reg(addr, data32);
+}
+
+void hdmitx_poll_reg(unsigned int addr, unsigned int val, unsigned long timeout)
+{
+}
+
+unsigned int hdmitx_rd_check_reg(unsigned int addr, unsigned int exp_data,
+ unsigned int mask)
+{
+ return 0;
+}
+
+void hdmitx_hdcp_init(void)
+{
+ register long x0 asm("x0") = 0x82000012;
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ : : "r"(x0)
+ );
+}
+
+void hdmitx_set_phypara(enum hdmi_phy_para mode)
+{
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x0);
+/* P_ANACTRL_HDMIPHY_CTRL1 bit[1]: enable clock bit[0]: soft reset */
+#define RESET_HDMI_PHY() \
+do { \
+ hd_set_reg_bits(P_ANACTRL_HDMIPHY_CTRL1, 0xf, 0, 4); \
+ mdelay(2); \
+ hd_set_reg_bits(P_ANACTRL_HDMIPHY_CTRL1, 0xe, 0, 4); \
+ mdelay(2); \
+} while (0)
+
+ hd_set_reg_bits(P_ANACTRL_HDMIPHY_CTRL1, 0x0390, 16, 16);
+ hd_set_reg_bits(P_ANACTRL_HDMIPHY_CTRL1, 0x0, 0, 4);
+ RESET_HDMI_PHY();
+ RESET_HDMI_PHY();
+#undef RESET_HDMI_PHY
+
+ switch (mode) {
+ case HDMI_PHYPARA_6G: /* 5.94/4.5/3.7Gbps */
+ case HDMI_PHYPARA_4p5G:
+ case HDMI_PHYPARA_3p7G:
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x37eb65c4);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0x0000080b);
+ break;
+ case HDMI_PHYPARA_3G: /* 2.97Gbps */
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x33eb42a2);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0x00000003);
+ break;
+ case HDMI_PHYPARA_270M: /* 1.485Gbps, and below */
+ case HDMI_PHYPARA_DEF:
+ default:
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x33eb4252);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0x00000003);
+ break;
+ }
+}
+
+void hdmitx_turnoff(void)
+{
+ /* Close HDMITX PHY */
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0);
+ /* Disable HPLL */
+ hd_write_reg(ANACTRL_HDMIPLL_CTRL0, 0);
+}
+
+void hdmitx_test_prbs(void)
+{
+ unsigned int i;
+
+ for (i = 0; i < 4; i ++) {
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL1, 0x0390000f);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL1, 0x0390000e);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL1, 0x03904002);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL4, 0x0001efff | (i << 20));
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL1, 0xef904002);
+ mdelay(1);
+ if (i == 0)
+ printf("prbs clk: %08x\n",hd_read_reg(P_ANACTRL_HDMIPLL_CTRL6));
+ else
+ printf("prbs D[%d]: %08x\n", i -1, hd_read_reg(P_ANACTRL_HDMIPLL_CTRL6));
+ }
+}
diff --git a/arch/arm/mach-meson/sc2/hdmitx_misc.h b/arch/arm/mach-meson/sc2/hdmitx_misc.h
new file mode 100644
index 0000000..5e32df8
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/hdmitx_misc.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __HDMITX_MISC_H__
+#define __HDMITX_MISC_H__
+
+/* miscellaneous definition */
+
+/* REG_BASE: REGISTER_BASE_ADDR = 0xfe000000 */
+#define CLKCTRL_SYS_CLK_EN0_REG2 0x0013
+#define P_CLKCTRL_SYS_CLK_EN0_REG2 HHI_REG_ADDR(CLKCTRL_SYS_CLK_EN0_REG2)
+#define CLKCTRL_VID_CLK_CTRL 0x0030
+#define P_CLKCTRL_VID_CLK_CTRL HHI_REG_ADDR(CLKCTRL_VID_CLK_CTRL)
+#define CLKCTRL_VID_CLK_CTRL2 0x0031
+#define P_CLKCTRL_VID_CLK_CTRL2 HHI_REG_ADDR(CLKCTRL_VID_CLK_CTRL2)
+#define CLKCTRL_VID_CLK_DIV 0x0032
+#define P_CLKCTRL_VID_CLK_DIV HHI_REG_ADDR(CLKCTRL_VID_CLK_DIV)
+#define CLKCTRL_HDMI_CLK_CTRL 0x0038
+#define P_CLKCTRL_HDMI_CLK_CTRL HHI_REG_ADDR(CLKCTRL_HDMI_CLK_CTRL)
+#define CLKCTRL_VID_PLL_CLK_DIV 0x0039
+#define P_CLKCTRL_VID_PLL_CLK_DIV HHI_REG_ADDR(CLKCTRL_VID_PLL_CLK_DIV)
+#define CLKCTRL_HDCP22_CLK_CTRL 0x0040
+#define P_CLKCTRL_HDCP22_CLK_CTRL HHI_REG_ADDR(CLKCTRL_HDCP22_CLK_CTRL)
+
+/* REG_BASE: REGISTER_BASE_ADDR = 0xfe002000 */
+#define RESETCTRL_RESET0 0x0000
+#define P_RESETCTRL_RESET0 RESETCTRL_REG_ADDR(RESETCTRL_RESET0)
+#define RESETCTRL_RESET2 0x0002
+#define P_RESETCTRL_RESET2 RESETCTRL_REG_ADDR(RESETCTRL_RESET2)
+
+/* REG_BASE: REGISTER_BASE_ADDR = 0xfe008000 */
+#define ANACTRL_HDMIPLL_CTRL0 0x0070
+#define P_ANACTRL_HDMIPLL_CTRL0 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL0)
+#define ANACTRL_HDMIPLL_CTRL1 0x0071
+#define P_ANACTRL_HDMIPLL_CTRL1 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL1)
+#define ANACTRL_HDMIPLL_CTRL2 0x0072
+#define P_ANACTRL_HDMIPLL_CTRL2 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL2)
+#define ANACTRL_HDMIPLL_CTRL3 0x0073
+#define P_ANACTRL_HDMIPLL_CTRL3 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL3)
+#define ANACTRL_HDMIPLL_CTRL4 0x0074
+#define P_ANACTRL_HDMIPLL_CTRL4 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL4)
+#define ANACTRL_HDMIPLL_CTRL5 0x0075
+#define P_ANACTRL_HDMIPLL_CTRL5 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL5)
+#define ANACTRL_HDMIPLL_CTRL6 0x0076
+#define P_ANACTRL_HDMIPLL_CTRL6 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL6)
+#define ANACTRL_HDMIPLL_STS 0x0077
+#define P_ANACTRL_HDMIPLL_STS ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_STS)
+#define ANACTRL_HDMIPLL_VLOCK 0x0079
+#define P_ANACTRL_HDMIPLL_VLOCK ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_VLOCK)
+#define ANACTRL_HDMIPHY_CTRL0 0x0080
+#define P_ANACTRL_HDMIPHY_CTRL0 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL0)
+#define ANACTRL_HDMIPHY_CTRL1 0x0081
+#define P_ANACTRL_HDMIPHY_CTRL1 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL1)
+#define ANACTRL_HDMIPHY_CTRL2 0x0082
+#define P_ANACTRL_HDMIPHY_CTRL2 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL2)
+#define ANACTRL_HDMIPHY_CTRL3 0x0083
+#define P_ANACTRL_HDMIPHY_CTRL3 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL3)
+#define ANACTRL_HDMIPHY_CTRL4 0x0084
+#define P_ANACTRL_HDMIPHY_CTRL4 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL4)
+#define ANACTRL_HDMIPHY_CTRL5 0x0085
+#define P_ANACTRL_HDMIPHY_CTRL5 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL5)
+#define ANACTRL_HDMIPHY_STS 0x0086
+#define P_ANACTRL_HDMIPHY_STS ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_STS)
+
+/* REG_BASE: REGISTER_BASE_ADDR = 0xfe00c000 */
+#define PWRCTRL_MEM_PD11 0x001b
+#define P_PWRCTRL_MEM_PD11 PWRCTRL_REG_ADDR(PWRCTRL_MEM_PD11)
+
+#endif
diff --git a/arch/arm/mach-meson/sc2/mailbox.c b/arch/arm/mach-meson/sc2/mailbox.c
new file mode 100644
index 0000000..93cef28
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/mailbox.c
@@ -0,0 +1,153 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/arch/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/arch/mailbox.h>
+#include <asm/arch/secure_apb.h>
+
+#define aml_writel32(value, reg) writel(value, reg)
+#define aml_readl32(reg) readl(reg)
+
+
+static inline void mbwrite(uint32_t to, void *from, long count)
+{
+ int i = 0;
+ int len = count / 4 + (count % 4);
+ uint32_t *p = from;
+
+ while (len > 0) {
+ aml_writel32(p[i], to + (4 * i));
+ len--;
+ i++;
+ }
+}
+
+static inline void mbclean(uint32_t to, long count)
+{
+ int i = 0;
+ int len = count / 4 + (count % 4);
+
+ while (len > 0) {
+ aml_writel32(0, to + (4 * i));
+ len--;
+ i++;
+ }
+}
+
+int mhu_get_addr(uint32_t chan, uint32_t *mboxset, uint32_t *mboxsts,
+ uintptr_t *mboxpl, uint32_t *mboxwr, uint32_t *mboxrd,
+ uint32_t *mboxirqclr, uint32_t *mboxid)
+{
+ int ret = 0;
+
+ switch (chan) {
+ case AOCPU_REE_CHANNEL:
+ *mboxset = REE2AO_SET_ADDR;
+ *mboxsts = REE2AO_STS_ADDR;
+ *mboxwr = REE2AO_WR_ADDR;
+ *mboxrd = REE2AO_RD_ADDR;
+ *mboxirqclr = REE2AO_IRQCLR_ADDR;
+ *mboxid = REE2AO_MBOX_ID;
+ break;
+ default:
+ printf("[BL33]: no support chan 0x%x\n", chan);
+ ret = -1;
+ break;
+ };
+ return ret;
+}
+
+void mhu_message_start(uint32_t mboxsts)
+{
+ /* Make sure any previous command has finished */
+ while (aml_readl32(mboxsts) != 0);
+}
+
+void mhu_build_payload(uintptr_t mboxpl, uint32_t mboxwr, void *message, uint32_t size)
+{
+ if (size > (MHU_PAYLOAD_SIZE - MHU_DATA_OFFSET)) {
+ printf("bl33: scpi send input size error\n");
+ return;
+ }
+ if (size == 0)
+ return;
+ mbwrite(mboxwr + MHU_DATA_OFFSET, message, size);
+}
+
+void mhu_get_payload(uintptr_t mboxpl, uint32_t mboxwr, void *message, uint32_t size)
+{
+ if (size > (MHU_PAYLOAD_SIZE - MHU_DATA_OFFSET)) {
+ printf("bl33: scpi send input size error\n");
+ return;
+ }
+ if (size == 0)
+ return;
+ printf("bl33: scpi no support get revmessage\n");
+}
+
+void mhu_message_send(uint32_t mboxset, uint32_t command, uint32_t size)
+{
+ uint32_t mbox_cmd;
+ mbox_cmd = MHU_CMD_BUILD(command, size + MHU_DATA_OFFSET);
+ aml_writel32(mbox_cmd, mboxset);
+}
+
+uint32_t mhu_message_wait(uint32_t mboxsts)
+{
+ /* Wait for response from HIFI */
+ uint32_t response;
+
+ while ((response = aml_readl32(mboxsts)));
+
+ return response;
+}
+
+void mhu_message_end(uintptr_t mboxpl, uint32_t mboxwr, uint32_t mboxirqclr, uint32_t mboxid)
+{
+ mbclean(mboxwr, MHU_PAYLOAD_SIZE);
+ /* Clear any response we got by writing all ones to the CLEAR register */
+ aml_writel32(MHU_ACK_MASK(mboxid), mboxirqclr);
+}
+
+void mhu_init(void)
+{
+ aml_writel32(0xffffffffu, REE2AO_CLR_ADDR);
+ printf("[BL33] mhu init done -v2\n");
+}
+int scpi_send_data(uint32_t chan, uint32_t command,
+ void *sendmessage, uint32_t sendsize,
+ void *revmessage, uint32_t revsize)
+{
+ uint32_t mboxset = 0;
+ uint32_t mboxsts = 0;
+ uintptr_t mboxpl = 0;
+ uint32_t mboxwr = 0;
+ uint32_t mboxrd = 0;
+ uint32_t mboxirq = 0;
+ uint32_t mboxid = 0;
+ int ret = 0;
+
+ ret = mhu_get_addr(chan, &mboxset, &mboxsts,
+ &mboxpl, &mboxwr, &mboxrd,
+ &mboxirq, &mboxid);
+ if (ret) {
+ printf("bl33: mhu get addr fail\n");
+ return ret;
+ }
+ mhu_message_start(mboxsts);
+ if (sendmessage != NULL && sendsize != 0)
+ mhu_build_payload(mboxpl, mboxwr, sendmessage, sendsize);
+ mhu_message_send(mboxset, command, sendsize);
+ mhu_message_wait(mboxsts);
+ if (revmessage != NULL && revsize != 0)
+ mhu_get_payload(mboxpl, mboxrd, revmessage, revsize);
+ mhu_message_end(mboxpl, mboxwr, mboxirq, mboxid);
+ return ret;
+}
+
diff --git a/arch/arm/mach-meson/sc2/oscring.c b/arch/arm/mach-meson/sc2/oscring.c
new file mode 100644
index 0000000..de7fa03
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/oscring.c
@@ -0,0 +1,120 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/arch/io.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/oscring.h>
+
+void ring_powerinit(void)
+{
+ writel(0x18000a, RING_PWM_VCCK);/*set vcck 0.8v*/
+ writel(0x90009, RING_PWM_EE);/*set ee 0.8v*/
+}
+
+unsigned long clk_util_ring_msr(unsigned long clk_mux)
+{
+ unsigned int regval = 0;
+
+ writel(0, MSR_CLK_REG0);
+ /* Set the measurement gate to 64uS */
+ /* 64uS is enough for measure the frequence? */
+ setbits_le32(MSR_CLK_REG0, (10000 - 1));
+ /* Disable continuous measurement */
+ /* Disable interrupts */
+ clrbits_le32(MSR_CLK_REG0, (1 << 17) | (1 << 18));
+ clrbits_le32(MSR_CLK_REG0, 0x7f << 20);
+ setbits_le32(MSR_CLK_REG0, (clk_mux) << 20 | (1 << 19) | (1 << 16));
+ mdelay(10);
+ /* Wait for the measurement to be done */
+ regval = readl(MSR_CLK_REG0);
+ do {
+ regval = readl(MSR_CLK_REG0);
+ } while (regval & (1 << 31));
+
+ /* Disable measuring */
+ clrbits_le32(MSR_CLK_REG0, 1 << 16);
+ regval = (readl(MSR_CLK_REG2) + 31) & 0x000fffff;
+
+ return (regval / 10);
+}
+
+int ring_msr(int index)
+{
+ const char* clk_table[] = {
+ [17] = "dspa_osc_ring(SVT16) " ,
+ [16] = "axi_sram_osc_ring(SVT16) " ,
+ [15] = "sys_cpu_osc_ring3(LVT16) " ,
+ [14] = "sys_cpu_osc_ring2(ULVT16) " ,
+ [13] = "sys_cpu_osc_ring1(ULVT20) " ,
+ [12] = "sys_cpu_osc_ring0(ULVT16) " ,
+ [11] = "ddr_osc_ring(LVT16) " ,
+ [10] = "dos_osc_ring3(ULVT20) " ,
+ [9] = "dos_osc_ring2(LVT16) " ,
+ [8] = "dos_osc_ring1(SVT16) " ,
+ [7] = "dos_osc_ring0(SVT24) " ,
+ [6] = "vpu_osc_ring2(LVT16) " ,
+ [5] = "vpu_osc_ring1(LVT20) " ,
+ [4] = "vpu_osc_ring0(SVT24) " ,
+ [3] = "gpu_osc_ring2(SVT16) " ,
+ [2] = "gpu_osc_ring1(ULVT16) " ,
+ [1] = "gpu_osc_ring0(LVT16) " ,
+ [0] = "dmc_osc_ring(LVT16) " ,
+ };
+ const int tb[] = {180, 181, 182, 183, 184, 185, 186, 187, 188, 189,
+ 190, 191, 192, 193, 194, 195, 196, 197};
+ unsigned long i;
+ uint8_t efuseinfo[4] = {0, 0, 0, 0};
+
+ if ((index != 0xff) && (index != 0)) {
+ if (bl31_get_cornerinfo(efuseinfo, sizeof(efuseinfo) / sizeof(uint8_t)) != 0) {
+ printf("fail get efuse info\n");
+ return 0;
+ }
+ if ((index >= 1) && (index <= 3))
+ printf("%d\n", efuseinfo[index]);
+ else
+ printf("input data not support!\n");
+
+ return 0;
+ }
+ if (0xff != index) {
+ ring_powerinit();
+ printf("set vcck vddee to 800mv\n");
+ }
+ /*RING_OSCILLATOR 0x7f: set slow ring*/
+ writel(OSCRING_CTL_DATA0, OSCRING_CTL_REG0);
+ writel(OSCRING_CTL_DATA1, OSCRING_CTL_REG1);
+
+ for (i = 0; i < 18; i++) {
+ printf("%s :",clk_table[i]);
+ printf("%ld KHz",clk_util_ring_msr(tb[i]));
+ printf("\n");
+ }
+
+ if (bl31_get_cornerinfo(efuseinfo, sizeof(efuseinfo) / sizeof(uint8_t)) != 0) {
+ printf("fail get efuse info\n");
+ return 0;
+ }
+
+ printf("osc efuse info:\n");
+ for (i = 0; i < sizeof(efuseinfo) / sizeof(uint8_t); i++)
+ printf("0x%x, ", efuseinfo[i]);
+ printf("\n");
+
+ /*efuse to test value*/
+ printf("osc_ring_core0(20lvt), idd_ee, idd_cpu\n");
+
+ printf("%d KHz ", (efuseinfo[1] * 20));
+
+ for (i = 2; i <=3; i++) {
+ printf("%d uA ", (efuseinfo[i] * 400));
+ }
+ printf("\n");
+
+ return 0;
+}
diff --git a/arch/arm/mach-meson/sc2/pinctrl_init.c b/arch/arm/mach-meson/sc2/pinctrl_init.c
new file mode 100644
index 0000000..829ce28
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/pinctrl_init.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm/uclass.h>
+#include <linux/err.h>
+#include <asm/arch/pinctrl_init.h>
+
+int pinctrl_devices_active(int pinctrl_num)
+{
+ int ret;
+ int idx;
+ struct udevice *pinctrl;
+
+ for (idx = 0; idx < pinctrl_num; idx++) {
+ ret = uclass_get_device(UCLASS_PINCTRL, idx, &pinctrl);
+ if (ret) {
+ debug("%s: failed to active pinctrl device [%d]",
+ __func__, idx);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-meson/sc2/pll.c b/arch/arm/mach-meson/sc2/pll.c
new file mode 100644
index 0000000..29b1b9e
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/pll.c
@@ -0,0 +1,962 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/io.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/pll.h>
+#include <linux/arm-smccc.h>
+
+#define STR_PLL_TEST_ALL "all"
+#define STR_PLL_TEST_SYS "sys"
+#define STR_PLL_TEST_FIX "fix"
+#define STR_PLL_TEST_DDR "ddr"
+#define STR_PLL_TEST_HDMI "hdmi"
+#define STR_PLL_TEST_GP0 "gp0"
+#define STR_PLL_TEST_GP1 "gp1"
+#define STR_PLL_TEST_HIFI "hifi"
+#define STR_PLL_TEST_PCIE "pcie"
+#define STR_PLL_TEST_ETHPHY "ethphy"
+#define STR_PLL_TEST_USBPHY "usbphy"
+
+
+#define PLL_LOCK_CHECK_MAX 3
+
+#define RET_PLL_LOCK_FAIL 0x1000
+#define RET_CLK_NOT_MATCH 0x1
+#define SYS_PLL_DIV16_CNTL (1 << 24)
+#define SYS_CLK_DIV16_CNTL (1 << 1)
+#define SYS_PLL_TEST_DIV 4 /* div16 */
+#define HDMI_PLL_DIV_CNTL (1 << 18)
+#define HDMI_PLL_DIV_GATE (1 << 19)
+
+#define PLL_DIV16_OFFSET 4 /* div2/2/4 */
+
+#define RW_CPUCTRL_SYS_CPU_CLK 0
+#define SYS_PLL 1
+#define RW_CPUCTRL_SYS_CPU_CLK5 2
+#define GP1_PLL 3
+
+extern unsigned long clk_util_clk_msr(unsigned long clk_mux);
+
+gp0_pll_cfg_t gp0_pll_cfg = {
+ .gp0_pll[0] = {
+ .pll_clk = 6000, /* MHz */
+ .pll_cntl0 = 0x080304fa,
+ .pll_cntl1 = 0x00000000,
+ .pll_cntl2 = 0x00000000,
+ .pll_cntl3 = 0x48681c00,
+ .pll_cntl4 = 0x88770290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x56540000
+ },
+ .gp0_pll[1] = {
+ .pll_clk = 3000, /* MHz */
+ .pll_cntl0 = 0X0803047d,
+ .pll_cntl1 = 0x00006aab,
+ .pll_cntl2 = 0x00000000,
+ .pll_cntl3 = 0x6a295c00,
+ .pll_cntl4 = 0x65771290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x54540000
+ },
+};
+
+gp1_pll_cfg_t gp1_pll_cfg = {
+ .gp1_pll[0] = {
+ .pll_clk = 6000, /* MHz */
+ .pll_cntl0 = 0x080304fa,
+ .pll_cntl1 = 0x00000000,
+ .pll_cntl2 = 0x00000000,
+ .pll_cntl3 = 0x48681c00,
+ .pll_cntl4 = 0x88770290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x56540000
+ },
+ .gp1_pll[1] = {
+ .pll_clk = 3000, /* MHz */
+ .pll_cntl0 = 0X0803047d,
+ .pll_cntl1 = 0x00006aab,
+ .pll_cntl2 = 0x00000000,
+ .pll_cntl3 = 0x6a295c00,
+ .pll_cntl4 = 0x65771290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x54540000
+ },
+};
+
+hdmi_pll_cfg_t hdmi_pll_cfg = {
+ .hdmi_pll[0] = {
+ .pll_clk = 5940, /* MHz */
+ .pll_cntl0 = 0x0b3004f7,
+ .pll_cntl1 = 0x00010000,
+ .pll_cntl2 = 0x00000000,
+ .pll_cntl3 = 0x6a28dc00,
+ .pll_cntl4 = 0x65771290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x56540000
+ },
+ .hdmi_pll[1] = {
+ .pll_clk = 2970,
+ .pll_cntl0 = 0x0b00047b,
+ .pll_cntl1 = 0x00018000,
+ .pll_cntl2 = 0x00000000,
+ .pll_cntl3 = 0x6a29dc00,
+ .pll_cntl4 = 0x65771290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x54540000
+ },
+};
+
+uint32_t sys_pll_clk[] = {6000, 3000};
+sys_pll_cfg_t sys_pll_cfg = {
+ .sys_pll[0] = {
+ .cpu_clk = 6000,
+ .pll_cntl = 0X080004fa,
+ .pll_cntl1 = 0x0,
+ .pll_cntl2 = 0x0,
+ .pll_cntl3 = 0x48681c00,
+ .pll_cntl4 = 0x88770290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x56540000
+ },
+
+ .sys_pll[1] = {
+ .cpu_clk = 3000,
+ .pll_cntl = 0X0800047d,
+ .pll_cntl1 = 0x0,
+ .pll_cntl2 = 0x0,
+ .pll_cntl3 = 0x48681c00,
+ .pll_cntl4 = 0x88770290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x56540000
+ },
+};
+
+hifi_pll_cfg_t hifi_pll_cfg = {
+ .hifi_pll[0] = {
+ .pll_clk = 6005,
+ .pll_cntl0 = 0X080304fa,
+ .pll_cntl1 = 0X00006aab,
+ .pll_cntl2 = 0x0,
+ .pll_cntl3 = 0x6a285c00,
+ .pll_cntl4 = 0x65771290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x56540000
+ },
+
+ .hifi_pll[1] = {
+ .pll_clk = 3000,
+ .pll_cntl0 = 0X0803047d,
+ .pll_cntl1 = 0X00006aab,
+ .pll_cntl2 = 0x0,
+ .pll_cntl3 = 0x6a295c00,
+ .pll_cntl4 = 0x65771290,
+ .pll_cntl5 = 0x39272000,
+ .pll_cntl6 = 0x54540000
+ },
+};
+
+/*PCIE clk_out = 24M*m/2^(n+1)/OD*/
+static const struct pciepll_rate_table pcie_pll_rate_table[] = {
+ PLL_RATE(4800, 200, 1, 12),
+};
+
+static void pll_report(unsigned int flag, char * name)
+{
+ if (flag)
+ printf("%s pll test failed!\n", name);
+ else
+ printf("%s pll test pass!\n", name);
+ return;
+}
+
+static int clk_around(unsigned int clk, unsigned int cmp)
+{
+ if (cmp == 1)
+ cmp += 1;
+ if (((cmp-2) <= clk) && (clk <= (cmp+2)))
+ return 1;
+ else
+ return 0;
+}
+
+static void clocks_set_sys_cpu_clk(uint32_t freq)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(0x8200009C, RW_CPUCTRL_SYS_CPU_CLK, freq, 0, 0, 0,
+ 0, 0, &res);
+}
+
+static int sys_pll_init(sys_pll_set_t * sys_pll_set)
+{
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int lock_timeout = 0;
+ struct arm_smccc_res res;
+
+ do {
+ arm_smccc_smc(0x8200009C, SYS_PLL, sys_pll_set->pll_cntl, 0,
+ 0, 0, 0, 0, &res);
+ //Wr(ANACTRL_SYSPLL_CTRL0, sys_pll_set->pll_cntl);
+ //Wr(ANACTRL_SYSPLL_CTRL0, sys_pll_set->pll_cntl | (3 << 28));
+ //Wr(ANACTRL_SYSPLL_CTRL1, sys_pll_set->pll_cntl1);
+ //Wr(ANACTRL_SYSPLL_CTRL2, sys_pll_set->pll_cntl2);
+ //Wr(ANACTRL_SYSPLL_CTRL3, sys_pll_set->pll_cntl3);
+ //Wr(ANACTRL_SYSPLL_CTRL4, sys_pll_set->pll_cntl4);
+ //Wr(ANACTRL_SYSPLL_CTRL5, sys_pll_set->pll_cntl5);
+ //Wr(ANACTRL_SYSPLL_CTRL6, sys_pll_set->pll_cntl6);
+ //Wr(ANACTRL_SYSPLL_CTRL0, ((1<<29) | Rd(HHI_SYS_PLL_CNTL0)));
+ //Wr(ANACTRL_SYSPLL_CTRL0, Rd(HHI_SYS_PLL_CNTL0)&(~(1<<29)));
+ lock_timeout = 200;
+ do {
+ _udelay(2);
+ } while ((!((readl(ANACTRL_SYSPLL_STS) >> 31) & 0x1)) &&
+ --lock_timeout);
+ } while((!((readl(ANACTRL_SYSPLL_STS) >> 31) & 0x1)) && --lock_check);
+
+ if (lock_check != 0)
+ return 0;
+ else
+ return RET_PLL_LOCK_FAIL;
+}
+
+static int sys_pll_test(sys_pll_set_t * sys_pll_set)
+{
+ unsigned int clk_msr_val = 0;
+ unsigned int sys_clk = 0;
+ sys_pll_set_t sys_pll;
+ int ret = 0;
+
+ /* switch sys clk to oscillator */
+ clocks_set_sys_cpu_clk(0);
+
+ /* store current sys pll cntl */
+ sys_pll.pll_cntl = readl(ANACTRL_SYSPLL_CTRL0);
+ sys_pll.pll_cntl1 = readl(ANACTRL_SYSPLL_CTRL1);
+ sys_pll.pll_cntl2 = readl(ANACTRL_SYSPLL_CTRL2);
+ sys_pll.pll_cntl3 = readl(ANACTRL_SYSPLL_CTRL3);
+ sys_pll.pll_cntl4 = readl(ANACTRL_SYSPLL_CTRL4);
+ sys_pll.pll_cntl5 = readl(ANACTRL_SYSPLL_CTRL5);
+ sys_pll.pll_cntl6 = readl(ANACTRL_SYSPLL_CTRL6);
+
+ if (sys_pll_set->cpu_clk == 0) {
+ sys_clk = (24 / ((sys_pll_set->pll_cntl >> 10) & 0x1F) *
+ (sys_pll_set->pll_cntl & 0x1FF)) >>
+ ((sys_pll_set->pll_cntl >> 16) & 0x3);
+ } else {
+ sys_clk = sys_pll_set->cpu_clk;
+ }
+
+ if (0 == sys_pll_set->pll_cntl) {
+ printf("sys pll cntl equal NULL, skip\n");
+ return -1;
+ }
+
+ /* test sys pll */
+ ret = sys_pll_init(sys_pll_set);
+ _udelay(5);
+ if (ret) {
+ printf("SYS pll lock Failed! - %4d MHz\n", sys_clk);
+ } else {
+ printf("SYS pll lock OK! - %4d MHz. Div16 - %4d MHz. ",
+ sys_clk, sys_clk >> PLL_DIV16_OFFSET);
+ clk_msr_val = clk_util_clk_msr(23);
+ printf("CLKMSR(23) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, sys_clk >> SYS_PLL_TEST_DIV)) {
+ /* sys clk/pll div16 */
+ printf(": Match\n");
+ } else {
+ ret = RET_CLK_NOT_MATCH;
+ printf(": MisMatch\n");
+ }
+ }
+
+ /* restore sys pll */
+ sys_pll_init(&sys_pll);
+ clocks_set_sys_cpu_clk(1);
+
+ return ret;
+}
+
+static int sys_pll_test_all(sys_pll_cfg_t * sys_pll_cfg)
+{
+ unsigned int i = 0;
+ int ret = 0;
+
+ for (i = 0; i < (sizeof(sys_pll_cfg_t) / sizeof(sys_pll_set_t)); i++)
+ ret += sys_pll_test(&(sys_pll_cfg->sys_pll[i]));
+ return ret;
+}
+
+static void set_dsu_clk(uint32_t flag)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(0x8200009C, RW_CPUCTRL_SYS_CPU_CLK5, flag, 0, 0, 0,
+ 0, 0, &res);
+}
+
+static int gp1_pll_init(gp1_pll_set_t * gp1_pll_set)
+{
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int lock_timeout = 0;
+ struct arm_smccc_res res;
+
+ do {
+ arm_smccc_smc(0x8200009C, GP1_PLL, gp1_pll_set->pll_cntl0,
+ gp1_pll_set->pll_cntl3, gp1_pll_set->pll_cntl4,
+ 0, 0, 0, &res);
+ lock_timeout = 200;
+ do {
+ _udelay(2);
+ } while ((!((readl(ANACTRL_GP1PLL_STS) >> 31) & 0x1)) &&
+ --lock_timeout);
+ } while((!((readl(ANACTRL_GP1PLL_STS) >> 31) & 0x1)) && --lock_check);
+
+ if (lock_check != 0)
+ return 0;
+ else
+ return RET_PLL_LOCK_FAIL;
+}
+
+static int gp1_pll_test(gp1_pll_set_t * gp1_pll_set)
+{
+ unsigned int clk_msr_val = 0, od = 0;
+ unsigned int pll_clk = 0;
+ gp1_pll_set_t gp1_pll;
+ int ret = 0;
+
+ od = (gp1_pll_set->pll_cntl0 >> 16) & 0x7;
+ /* switch dsu clk to oscillator */
+ set_dsu_clk(0);
+
+ /* store current gp1 pll cntl */
+ gp1_pll.pll_cntl0 = readl(ANACTRL_GP1PLL_CTRL0);
+ gp1_pll.pll_cntl1 = readl(ANACTRL_GP1PLL_CTRL1);
+ gp1_pll.pll_cntl2 = readl(ANACTRL_GP1PLL_CTRL2);
+ gp1_pll.pll_cntl3 = readl(ANACTRL_GP1PLL_CTRL3);
+ gp1_pll.pll_cntl4 = readl(ANACTRL_GP1PLL_CTRL4);
+ gp1_pll.pll_cntl5 = readl(ANACTRL_GP1PLL_CTRL5);
+ gp1_pll.pll_cntl6 = readl(ANACTRL_GP1PLL_CTRL6);
+
+ if (gp1_pll_set->pll_clk == 0) {
+ pll_clk = (24 / ((gp1_pll_set->pll_cntl0 >> 10) & 0x1F) *
+ (gp1_pll_set->pll_cntl0 & 0x1FF));
+ } else {
+ pll_clk = gp1_pll_set->pll_clk;
+ }
+
+ if (0 == gp1_pll_set->pll_cntl0) {
+ printf("gp1 pll cntl equal NULL, skip\n");
+ return -1;
+ }
+
+ /* test gp1 pll */
+ ret = gp1_pll_init(gp1_pll_set);
+ _udelay(5);
+ if (ret) {
+ printf("GP1 pll lock Failed! - %4d MHz\n", pll_clk);
+ } else {
+ printf("GP1 pll lock OK! - %4d MHz>>%d - %4d MHz. ",
+ pll_clk, od, pll_clk >> od);
+ clk_msr_val = clk_util_clk_msr(21);
+ printf("CLKMSR(21) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk >> od)) {
+ printf(": Match\n");
+ } else {
+ ret = RET_CLK_NOT_MATCH;
+ printf(": MisMatch\n");
+ }
+ }
+
+ /* restore gp1 pll */
+ gp1_pll_init(&gp1_pll);
+ set_dsu_clk(1);
+
+ return ret;
+}
+
+static int gp1_pll_test_all(gp1_pll_cfg_t * gp1_pll_cfg)
+{
+ unsigned int i = 0;
+ int ret = 0;
+
+ for (i = 0; i < (sizeof(gp1_pll_cfg_t) / sizeof(gp1_pll_set_t)); i++)
+ ret += gp1_pll_test(&(gp1_pll_cfg->gp1_pll[i]));
+ return ret;
+}
+
+static int fix_pll_test(void)
+{
+ return 0;
+}
+
+static int ddr_pll_test(void)
+{
+ return 0;
+}
+
+static int hdmi_pll_init(hdmi_pll_set_t * hdmi_pll)
+{
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+
+ do {
+ writel(hdmi_pll->pll_cntl0, ANACTRL_HDMIPLL_CTRL0);
+ writel(hdmi_pll->pll_cntl0 | (3 << 28), ANACTRL_HDMIPLL_CTRL0);
+ writel(hdmi_pll->pll_cntl1, ANACTRL_HDMIPLL_CTRL1);
+ writel(hdmi_pll->pll_cntl2, ANACTRL_HDMIPLL_CTRL2);
+ writel(hdmi_pll->pll_cntl3, ANACTRL_HDMIPLL_CTRL3);
+ writel(hdmi_pll->pll_cntl4, ANACTRL_HDMIPLL_CTRL4);
+ writel(hdmi_pll->pll_cntl5, ANACTRL_HDMIPLL_CTRL5);
+ writel(hdmi_pll->pll_cntl6, ANACTRL_HDMIPLL_CTRL6);
+
+ writel(readl(ANACTRL_HDMIPLL_CTRL0) | (1 << 29),
+ ANACTRL_HDMIPLL_CTRL0);
+ _udelay(10);
+ writel(readl(ANACTRL_HDMIPLL_CTRL0) & (~(1 << 29)),
+ ANACTRL_HDMIPLL_CTRL0);
+ _udelay(100);
+ } while ((!(0x3==((readl(ANACTRL_HDMIPLL_STS) >> 30) & 0x3))) &&
+ --lock_check);
+ if (lock_check != 0)
+ return 0;
+ else
+ return RET_PLL_LOCK_FAIL;
+}
+
+static int hdmi_pll_test(hdmi_pll_set_t * hdmi_pll_set)
+{
+ unsigned int pll_clk = 0 , od = 0;
+ unsigned int pll_clk_div = 0;
+ unsigned int clk_msr_val = 0;
+ unsigned int clk_msr_reg = 0;
+ int ret = 0;
+
+ /* store pll div setting */
+ clk_msr_reg = readl(CLKCTRL_VID_PLL_CLK_DIV);
+ /* connect vid_pll_div to HDMIPLL directly */
+ clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 19);
+ clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 15);
+
+ /* div14 */
+ clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 18);
+ clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 0x3 << 16);
+ clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 15);
+ clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 0x7fff);
+ setbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 16);
+ setbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 15);
+ setbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 0x3f80);
+ clrbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 15);
+
+ setbits_le32(CLKCTRL_VID_PLL_CLK_DIV, 1 << 19);
+
+ /* test pll */
+ if (hdmi_pll_set->pll_clk == 0)
+ pll_clk = ((24 * (hdmi_pll_set->pll_cntl0 & 0xff)) /
+ ((hdmi_pll_set->pll_cntl0 >> 10) & 0x1f));
+ else
+ pll_clk = hdmi_pll_set->pll_clk;
+
+ _udelay(10);
+ ret = hdmi_pll_init(hdmi_pll_set);
+ if (ret) {
+ printf("HDMI pll lock Failed! - %4d MHz\n", pll_clk);
+ } else {
+ od = (hdmi_pll_set->pll_cntl0 >> 20) & 0x3;
+ pll_clk_div = (pll_clk >>od) / 14;
+ printf("HDMI pll lock OK! - %4d MHz>>%d and Div14 - %4d MHz. ",
+ pll_clk, od, pll_clk_div);
+ /* get [ 55][1485 MHz] vid_pll_div_clk_out */
+ clk_msr_val = clk_util_clk_msr(50);
+ printf("CLKMSR(50) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk_div)) {
+ printf(": Match\n");
+ } else {
+ ret = RET_CLK_NOT_MATCH;
+ printf(": MisMatch\n");
+ }
+ }
+
+ /* restore pll */
+ /* restore div cntl bit */
+ writel(clk_msr_reg, CLKCTRL_VID_PLL_CLK_DIV);
+
+ return ret;
+}
+
+static int hdmi_pll_test_all(hdmi_pll_cfg_t * hdmi_pll_cfg)
+{
+ unsigned int i = 0;
+ int ret = 0;
+
+ for (i = 0; i < (sizeof(hdmi_pll_cfg_t) / sizeof(hdmi_pll_set_t)); i++)
+ ret += hdmi_pll_test(&(hdmi_pll_cfg->hdmi_pll[i]));
+ return ret;
+}
+
+static int gp0_pll_test(gp0_pll_set_t * gp0_pll)
+{
+ unsigned int pll_clk = 0;
+ int ret = 0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0, od = 0;
+
+ od = (gp0_pll->pll_cntl0 >> 16) & 0x7;
+
+ if (gp0_pll->pll_clk == 0)
+ pll_clk = (24 / ((gp0_pll->pll_cntl0 >> 10) & 0x1F) *
+ (gp0_pll->pll_cntl0 & 0x1FF));
+ else
+ pll_clk = gp0_pll->pll_clk;
+
+ do {
+ writel(gp0_pll->pll_cntl0, ANACTRL_GP0PLL_CTRL0);
+ writel(gp0_pll->pll_cntl0 | (3 << 28), ANACTRL_GP0PLL_CTRL0);
+ writel(gp0_pll->pll_cntl1, ANACTRL_GP0PLL_CTRL1);
+ writel(gp0_pll->pll_cntl2, ANACTRL_GP0PLL_CTRL2);
+ writel(gp0_pll->pll_cntl3, ANACTRL_GP0PLL_CTRL3);
+ writel(gp0_pll->pll_cntl4, ANACTRL_GP0PLL_CTRL4);
+ writel(gp0_pll->pll_cntl5, ANACTRL_GP0PLL_CTRL5);
+ writel(gp0_pll->pll_cntl6, ANACTRL_GP0PLL_CTRL6);
+
+ writel(readl(ANACTRL_GP0PLL_CTRL0) | (1 << 29),
+ ANACTRL_GP0PLL_CTRL0);
+ _udelay(10);
+ writel(readl(ANACTRL_GP0PLL_CTRL0) & (~(1 << 29)),
+ ANACTRL_GP0PLL_CTRL0);
+ _udelay(100);
+ } while ((!((readl(ANACTRL_GP0PLL_STS) >> 31) & 0x1)) && --lock_check);
+
+ if (0 == lock_check) {
+ printf("GP0 pll lock Failed! - %4d MHz\n", pll_clk);
+ ret = RET_PLL_LOCK_FAIL;
+ } else {
+ printf("GP0 pll lock OK! - %4d MHz >>%d - %4d MHz. ",
+ pll_clk, od, pll_clk >> od);
+ /* get gp0_pll_clk */
+ clk_msr_val = clk_util_clk_msr(20);
+ printf("CLKMSR(20) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk >> od)) {
+ printf(": Match\n");
+ } else {
+ printf(": MisMatch\n");
+ ret = RET_CLK_NOT_MATCH;
+ }
+ }
+ return ret;
+}
+
+static int gp0_pll_test_all(gp0_pll_cfg_t * gp0_pll_cfg)
+{
+ unsigned int i = 0;
+ int ret = 0;
+ for (i = 0; i < (sizeof(gp0_pll_cfg_t) / sizeof(gp0_pll_set_t)); i++)
+ ret += gp0_pll_test(&(gp0_pll_cfg->gp0_pll[i]));
+ return ret;
+}
+
+static int hifi_pll_test(hifi_pll_set_t * hifi_pll)
+{
+ unsigned int pll_clk = 0;
+ int ret = 0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0, od = 0;
+
+ od = (hifi_pll->pll_cntl0 >> 16) & 0x3;
+
+ if (hifi_pll->pll_clk == 0)
+ pll_clk = (24 / ((hifi_pll->pll_cntl0 >> 10) & 0x1F) *
+ (hifi_pll->pll_cntl0 & 0x1FF));
+ else
+ pll_clk = hifi_pll->pll_clk;
+
+ do {
+ writel(hifi_pll->pll_cntl0, ANACTRL_HIFIPLL_CTRL0);
+ writel(hifi_pll->pll_cntl0 | (3 << 28), ANACTRL_HIFIPLL_CTRL0);
+ writel(hifi_pll->pll_cntl1, ANACTRL_HIFIPLL_CTRL1);
+ writel(hifi_pll->pll_cntl2, ANACTRL_HIFIPLL_CTRL2);
+ writel(hifi_pll->pll_cntl3, ANACTRL_HIFIPLL_CTRL3);
+ writel(hifi_pll->pll_cntl4, ANACTRL_HIFIPLL_CTRL4);
+ writel(hifi_pll->pll_cntl5, ANACTRL_HIFIPLL_CTRL5);
+ writel(hifi_pll->pll_cntl6, ANACTRL_HIFIPLL_CTRL6);
+ writel(readl(ANACTRL_HIFIPLL_CTRL0) | (1 << 29),
+ ANACTRL_HIFIPLL_CTRL0);
+ _udelay(10);
+ writel(readl(ANACTRL_HIFIPLL_CTRL0)&(~(1 << 29)),
+ ANACTRL_HIFIPLL_CTRL0);
+ _udelay(100);
+ } while ((!((readl(ANACTRL_HIFIPLL_STS) >> 31) & 0x1)) &&
+ --lock_check);
+ if (0 == lock_check) {
+ printf("HIFI pll lock Failed! - %4d MHz\n", pll_clk);
+ ret = RET_PLL_LOCK_FAIL;
+ } else {
+ printf("HIFI pll lock OK! - %4d MHz.Div8 - %4d MHz.",
+ pll_clk, pll_clk >> od);
+ /* get hifi_pll_clk */
+ clk_msr_val = clk_util_clk_msr(19);
+ printf("CLKMSR(19) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk >> od)) {
+ printf(": Match\n");
+ } else {
+ printf(": MisMatch\n");
+ ret = RET_CLK_NOT_MATCH;
+ }
+ }
+ return ret;
+}
+
+static int hifi_pll_test_all(hifi_pll_cfg_t * hifi_pll_cfg)
+{
+ unsigned int i = 0;
+ int ret = 0;
+
+ for (i = 0; i < (sizeof(hifi_pll_cfg_t) / sizeof(hifi_pll_set_t)); i++)
+ ret += hifi_pll_test(&(hifi_pll_cfg->hifi_pll[i]));
+ return ret;
+}
+
+static int pcie_pll_test(pcie_pll_set_t * pcie_pll)
+{
+ int ret = 0;
+ unsigned int i = 0, pll_clk = 0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+
+ for (i = 0; i < (sizeof(pcie_pll_rate_table) /
+ sizeof(pcie_pll_rate_table[0])); i++) {
+ if ((pcie_pll->pll_cntl0 & 0xFF) ==
+ pcie_pll_rate_table[i].m)
+ pll_clk = pcie_pll_rate_table[i].rate;
+ }
+
+ do {
+ writel(pcie_pll->pll_cntl0, ANACTRL_PCIEPLL_CTRL0);
+ writel(pcie_pll->pll_cntl0 | 0x30000000,
+ ANACTRL_PCIEPLL_CTRL0);
+ writel(pcie_pll->pll_cntl1, ANACTRL_PCIEPLL_CTRL1);
+ writel(pcie_pll->pll_cntl2, ANACTRL_PCIEPLL_CTRL2);
+ writel(pcie_pll->pll_cntl3, ANACTRL_PCIEPLL_CTRL3);
+ writel(pcie_pll->pll_cntl4, ANACTRL_PCIEPLL_CTRL4);
+ writel(pcie_pll->pll_cntl5, ANACTRL_PCIEPLL_CTRL5);
+ writel(pcie_pll->pll_cntl5 | 0x68, ANACTRL_PCIEPLL_CTRL5);
+ _udelay(20);
+ writel(pcie_pll->pll_cntl4 | 0x00800000,
+ ANACTRL_PCIEPLL_CTRL4);
+ _udelay(10);
+ writel(pcie_pll->pll_cntl0 | 0x34000000,
+ ANACTRL_PCIEPLL_CTRL0);
+ writel(((pcie_pll->pll_cntl0 & (~(1 << 29))) | (1 << 26)) |
+ (1 << 28), ANACTRL_PCIEPLL_CTRL0);
+ _udelay(10);
+ writel(pcie_pll->pll_cntl2 & (~(1 << 8)),
+ ANACTRL_PCIEPLL_CTRL2);
+ _udelay(10);
+ } while ((!((readl(ANACTRL_PCIEPLL_STS) >> 31) & 0x1)) &&
+ --lock_check);
+ if (0 == lock_check) {
+ printf("PCIE pll lock Failed! - %4d MHz\n", pll_clk);
+ ret = RET_PLL_LOCK_FAIL;
+ } else {
+ printf("PCIE pll lock OK! - %4d MHz.Div48 - %4d MHz. ",
+ pll_clk, pll_clk / 48);
+ /* get pcie_pll_clk */
+ clk_msr_val = clk_util_clk_msr(16);
+ printf("CLKMSR(16) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val, pll_clk / 48)) {
+ printf(": Match\n");
+ } else {
+ printf(": MisMatch\n");
+ ret = RET_CLK_NOT_MATCH;
+ }
+ }
+
+ return ret;
+}
+
+static int pcie_pll_test_all(void)
+{
+ unsigned int i = 0;
+ unsigned int lock_check = PLL_LOCK_CHECK_MAX;
+ unsigned int clk_msr_val = 0;
+ int ret = 0;
+
+ do {
+ writel(0x200c04c8, ANACTRL_PCIEPLL_CTRL0);
+ writel(0x300c04c8, ANACTRL_PCIEPLL_CTRL0);
+ writel(0x30000000, ANACTRL_PCIEPLL_CTRL1);
+ writel(0x00001100, ANACTRL_PCIEPLL_CTRL2);
+ writel(0x10058e00, ANACTRL_PCIEPLL_CTRL3);
+ writel(0x000100c0, ANACTRL_PCIEPLL_CTRL4);
+ writel(0x68000048, ANACTRL_PCIEPLL_CTRL5);
+ writel(0x68000068, ANACTRL_PCIEPLL_CTRL5);
+ _udelay(20);
+ writel(0x008100c0, ANACTRL_PCIEPLL_CTRL4);
+ _udelay(10);
+ writel(0x340c04c8, ANACTRL_PCIEPLL_CTRL0);
+ writel(0x140c04c8, ANACTRL_PCIEPLL_CTRL0);
+ _udelay(10);
+ writel(0x00001000, ANACTRL_PCIEPLL_CTRL2);
+ _udelay(10);
+ } while ((!((readl(ANACTRL_PCIEPLL_STS) >> 31) & 0x1)) &&
+ --lock_check);
+
+ if (0 == lock_check) {
+ printf("pcie pll lock Failed! - %4d MHz\n",
+ pcie_pll_rate_table[i].rate);
+ ret += RET_PLL_LOCK_FAIL;
+ } else {
+ printf("pcie pll lock OK! - %4d MHz.Div48 - %4d MHz.",
+ pcie_pll_rate_table[i].rate,
+ pcie_pll_rate_table[i].rate / 48);
+ /* get pcie_pll_clk */
+ clk_msr_val = clk_util_clk_msr(16);
+ printf("CLKMSR(16) - %4d MHz ", clk_msr_val);
+ if (clk_around(clk_msr_val,
+ pcie_pll_rate_table[i].rate / 48)) {
+ printf(": Match\n");
+ } else {
+ printf(": MisMatch\n");
+ ret += RET_CLK_NOT_MATCH;
+ }
+ }
+
+ return ret;
+}
+
+static int pll_test_all(unsigned char * pll_list)
+{
+ int ret = 0;
+ unsigned char i = 0;
+
+ for (i = 0; i < PLL_ENUM; i++) {
+ switch (pll_list[i]) {
+ case PLL_SYS:
+ ret = sys_pll_test_all(&sys_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_SYS);
+ break;
+ case PLL_FIX:
+ ret = fix_pll_test();
+ pll_report(ret, STR_PLL_TEST_FIX);
+ break;
+ case PLL_DDR:
+ ret = ddr_pll_test();
+ pll_report(ret, STR_PLL_TEST_DDR);
+ break;
+ case PLL_HDMI:
+ ret = hdmi_pll_test_all(&hdmi_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_HDMI);
+ break;
+ case PLL_GP0:
+ ret = gp0_pll_test_all(&gp0_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_GP0);
+ break;
+ case PLL_HIFI:
+ ret = hifi_pll_test_all(&hifi_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_HIFI);
+ break;
+ case PLL_PCIE:
+ ret = pcie_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_PCIE);
+ break;
+ case PLL_GP1:
+ ret = gp1_pll_test_all(&gp1_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_GP1);
+ break;
+ default:
+ break;
+ }
+ }
+ return ret;
+}
+
+int pll_test(int argc, char * const argv[])
+{
+ int ret = 0;
+ sys_pll_set_t sys_pll_set = {0};
+ hdmi_pll_set_t hdmi_pll_set = {0};
+ gp0_pll_set_t gp0_pll_set = {0};
+ gp1_pll_set_t gp1_pll_set = {0};
+ hifi_pll_set_t hifi_pll_set = {0};
+ pcie_pll_set_t pcie_pll_set = {0};
+
+ unsigned char plls[PLL_ENUM] = {
+ PLL_SYS,
+ 0xff,// PLL_FIX, //0xff will skip this pll
+ 0xff,// PLL_DDR,
+ PLL_HDMI,
+ PLL_GP0,
+ PLL_HIFI,
+ PLL_PCIE,
+ PLL_GP1,
+ 0xff,//PLL_USBPHY
+ };
+
+ if (0 == strcmp(STR_PLL_TEST_ALL, argv[1])) {
+ printf("Test all plls\n");
+ pll_test_all(plls);
+ } else if(0 == strcmp(STR_PLL_TEST_SYS, argv[1])) {
+ if (argc == 2) {
+ ret = sys_pll_test_all(&sys_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_SYS);
+ } else if (argc != 9) {
+ printf("%s pll test: args error\n", STR_PLL_TEST_SYS);
+ return -1;
+ } else {
+ sys_pll_set.pll_cntl = simple_strtoul(argv[2], NULL,
+ 16);
+ sys_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL,
+ 16);
+ sys_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL,
+ 16);
+ sys_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL,
+ 16);
+ sys_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL,
+ 16);
+ sys_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL,
+ 16);
+ sys_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL,
+ 16);
+ ret = sys_pll_test(&sys_pll_set);
+ pll_report(ret, STR_PLL_TEST_SYS);
+ }
+ } else if (0 == strcmp(STR_PLL_TEST_HDMI, argv[1])) {
+ if (argc == 2) {
+ ret = hdmi_pll_test_all(&hdmi_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_HDMI);
+ } else if (argc != 9) {
+ printf("%s pll test: args error\n", STR_PLL_TEST_HDMI);
+ return -1;
+ } else {
+ hdmi_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL,
+ 16);
+ hdmi_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL,
+ 16);
+ hdmi_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL,
+ 16);
+ hdmi_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL,
+ 16);
+ hdmi_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL,
+ 16);
+ hdmi_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL,
+ 16);
+ hdmi_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL,
+ 16);
+ ret = hdmi_pll_test(&hdmi_pll_set);
+ pll_report(ret, STR_PLL_TEST_HDMI);
+ }
+ } else if (0 == strcmp(STR_PLL_TEST_GP0, argv[1])) {
+ if (argc == 2) {
+ ret = gp0_pll_test_all(&gp0_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_GP0);
+ } else if (argc != 9) {
+ printf("%s pll test: args error\n", STR_PLL_TEST_GP0);
+ return -1;
+ } else {
+ gp0_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL,
+ 16);
+ gp0_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL,
+ 16);
+ gp0_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL,
+ 16);
+ gp0_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL,
+ 16);
+ gp0_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL,
+ 16);
+ gp0_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL,
+ 16);
+ gp0_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL,
+ 16);
+ ret = gp0_pll_test(&gp0_pll_set);
+ pll_report(ret, STR_PLL_TEST_GP0);
+ }
+ } else if (0 == strcmp(STR_PLL_TEST_HIFI, argv[1])) {
+ if (argc == 2) {
+ ret = hifi_pll_test_all(&hifi_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_HIFI);
+ } else if (argc != 9) {
+ printf("%s pll test:args error\n", STR_PLL_TEST_HIFI);
+ return -1;
+ } else {
+ hifi_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL,
+ 16);
+ hifi_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL,
+ 16);
+ hifi_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL,
+ 16);
+ hifi_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL,
+ 16);
+ hifi_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL,
+ 16);
+ hifi_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL,
+ 16);
+ hifi_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL,
+ 16);
+ ret = hifi_pll_test(&hifi_pll_set);
+ pll_report(ret, STR_PLL_TEST_HIFI);
+ }
+ } else if (0 == strcmp(STR_PLL_TEST_PCIE, argv[1])) {
+ if (argc == 2) {
+ ret = pcie_pll_test_all();
+ pll_report(ret, STR_PLL_TEST_PCIE);
+ } else if (argc != 8) {
+ printf("%s pll test: args error\n", STR_PLL_TEST_PCIE);
+ return -1;
+ } else {
+ pcie_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL,
+ 16);
+ pcie_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL,
+ 16);
+ pcie_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL,
+ 16);
+ pcie_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL,
+ 16);
+ pcie_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL,
+ 16);
+ pcie_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL,
+ 16);
+ ret = pcie_pll_test(&pcie_pll_set);
+ pll_report(ret, STR_PLL_TEST_PCIE);
+ }
+ } else if (0 == strcmp(STR_PLL_TEST_GP1, argv[1])) {
+ if (argc == 2) {
+ ret = gp1_pll_test_all(&gp1_pll_cfg);
+ pll_report(ret, STR_PLL_TEST_GP1);
+ } else if (argc != 9) {
+ printf("%s pll test: args error\n", STR_PLL_TEST_GP1);
+ return -1;
+ } else {
+ gp1_pll_set.pll_cntl0 = simple_strtoul(argv[2], NULL,
+ 16);
+ gp1_pll_set.pll_cntl1 = simple_strtoul(argv[3], NULL,
+ 16);
+ gp1_pll_set.pll_cntl2 = simple_strtoul(argv[4], NULL,
+ 16);
+ gp1_pll_set.pll_cntl3 = simple_strtoul(argv[5], NULL,
+ 16);
+ gp1_pll_set.pll_cntl4 = simple_strtoul(argv[6], NULL,
+ 16);
+ gp1_pll_set.pll_cntl5 = simple_strtoul(argv[7], NULL,
+ 16);
+ gp1_pll_set.pll_cntl6 = simple_strtoul(argv[8], NULL,
+ 16);
+ ret = gp1_pll_test(&gp1_pll_set);
+ pll_report(ret, STR_PLL_TEST_GP1);
+ }
+ } else if (0 == strcmp(STR_PLL_TEST_DDR, argv[1])) {
+ printf("%s pll not support now\n", STR_PLL_TEST_DDR);
+ return -1;
+ } else if (0 == strcmp(STR_PLL_TEST_FIX, argv[1])) {
+ printf("%s pll not support now\n", STR_PLL_TEST_FIX);
+ return -1;
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-meson/sc2/power_cal.c b/arch/arm/mach-meson/sc2/power_cal.c
new file mode 100644
index 0000000..e4f9c53
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/power_cal.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/io.h>
+#include <amlogic/saradc.h>
+#include <asm/arch/mailbox.h>
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2))))
+#define vcck_adc_channel 0x4
+#define ee_adc_channel 0x5
+#define default_ref_val 1800
+
+extern const int pwm_cal_voltage_table[][2];
+extern const int pwm_cal_voltage_table_ee[][2];
+extern int pwm_cal_voltage_table_size;
+extern int pwm_cal_voltage_table_ee_size;
+
+
+enum pwm_id {
+ pwm_vcck = 0,
+ pwm_ee,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+int32_t aml_delt_get(int adc_val, unsigned int voltage)
+{
+ unsigned int adc_volt;
+ int32_t delt;
+ int32_t div = 10; /*10mv is min step*/
+
+ if (adc_val != -1) {
+ adc_volt = default_ref_val*adc_val/1024;
+ printf("aml pwm cal adc_val = %x, adc_voltage = %d, def_voltage = %d\n",
+ adc_val, adc_volt, voltage);
+ } else {
+ adc_volt = voltage;
+ printf("warning:aml pwm cal adc get voltage error\n");
+ return 0;
+ }
+ delt = voltage - adc_volt;
+ delt = delt / div;
+ return delt;
+}
+
+void aml_set_voltage(unsigned int id, unsigned int voltage, int delt)
+{
+ int to;
+
+ switch (id) {
+ case pwm_vcck:
+ for (to = 0; to < pwm_cal_voltage_table_size; to++) {
+ if (pwm_cal_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ to +=delt;
+ if (to >= pwm_cal_voltage_table_size) {
+ to = pwm_cal_voltage_table_size - 1;
+ }
+ /*vcck volt set by dvfs and avs*/
+ //writel(pwm_voltage_table[to][0], PWM_PWM_A_ADRESS);
+ _udelay_(200);
+ break;
+
+ case pwm_ee:
+ for (to = 0; to < pwm_cal_voltage_table_ee_size; to++) {
+ if (pwm_cal_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ to +=delt;
+ if (to >= pwm_cal_voltage_table_ee_size) {
+ to = pwm_cal_voltage_table_ee_size - 1;
+ }
+ printf("aml pwm cal before ee_address: %x, ee_voltage: %x\n",
+ AO_PWM_PWM_B, readl(AO_PWM_PWM_B));
+ writel(pwm_cal_voltage_table_ee[to][0],AO_PWM_PWM_B);
+ _udelay_(1000);
+ printf("aml pwm cal after ee_address: %x, ee_voltage: %x\n",
+ AO_PWM_PWM_B, readl(AO_PWM_PWM_B));
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+int aml_cal_pwm(unsigned int ee_voltage, unsigned int vcck_voltage)
+{
+ int32_t ee_delt, vcck_delt;
+ unsigned int ee_val, vcck_val;
+ int ret;
+
+ /*txlx vcck ch4,vddee ch5*/
+ ret = adc_channel_single_shot_mode("adc", ADC_MODE_HIGH_PRECISION,
+ vcck_adc_channel, &vcck_val);
+ if (ret)
+ return ret;
+
+ ret = adc_channel_single_shot_mode("adc", ADC_MODE_HIGH_PRECISION,
+ ee_adc_channel, &ee_val);
+ if (ret)
+ return ret;
+
+ vcck_delt = aml_delt_get(vcck_val, vcck_voltage);
+ ee_delt = aml_delt_get(ee_val, ee_voltage);
+ send_pwm_delt(vcck_delt, ee_delt);
+ aml_set_voltage(pwm_ee, AML_VDDEE_INIT_VOLTAGE, ee_delt);
+ //aml_set_voltage(pwm_vcck, CONFIG_VCCK_INIT_VOLTAGE, vcck_delt);
+ printf("aml board pwm vcck: %x, ee: %x\n", vcck_delt, ee_delt);
+
+ return 0;
+}
+
+void aml_pwm_cal_init(int mode)
+{
+ printf("aml pwm cal init\n");
+ aml_cal_pwm(AML_VDDEE_INIT_VOLTAGE, AML_VCCK_INIT_VOLTAGE);
+}
diff --git a/arch/arm/mach-meson/sc2/power_gate.h b/arch/arm/mach-meson/sc2/power_gate.h
new file mode 100644
index 0000000..9ca1a9d
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/power_gate.h
@@ -0,0 +1,1161 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __POWER_MGR_HEADER_
+#define __POWER_MGR_HEADER_
+
+#include <asm/arch/io.h>
+#include <common.h>
+//#include <asm/arch-gxb/io.h>
+/* #include <asm/arch-gxb/register.h> */
+#include <asm/arch/secure_apb.h>
+/* clock gate control */
+
+#define DEBUG_MASK 0
+
+#define SET_CLK_GATE_MASK(reg, mask) __raw_writel((__raw_readl(reg)|mask), reg)
+#define CLEAR_CLK_GATE_MASK(reg, mask) \
+ __raw_writel((__raw_readl(reg)&(~mask)), reg)
+#define CLK_GATE_ON(_MOD) do { \
+ if (DEBUG_MASK) \
+ printf("on reg %24s before read :0x%x : 0x%x\n",\
+ GCLK_NAME_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ SET_CLK_GATE_MASK(GCLK_REG_##_MOD, \
+ (unsigned int)GCLK_MASK_##_MOD); \
+ if (DEBUG_MASK) \
+ printf("on reg %24s after read :0x%x : 0x%x\n",\
+ GCLK_NAME_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ } while (0)
+
+#define CLK_GATE_OFF(_MOD) do { \
+ if (DEBUG_MASK) \
+ printf("off reg[ %24s ][0x%08x]before read:0x%08x:0x%08x\n",\
+ GCLK_NAME_##_MOD, (int)GCLK_MASK_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ CLEAR_CLK_GATE_MASK(GCLK_REG_##_MOD, (unsigned int)GCLK_MASK_##_MOD);\
+ if (DEBUG_MASK)\
+ printf("off reg[ %24s ][0x%08x] read after:0x%08x:0x%08x\n",\
+ GCLK_NAME_##_MOD, \
+ (int)GCLK_MASK_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ } while (0)
+
+#define IS_CLK_GATE_ON(_MOD) (__raw_readl(GCLK_REG_##_MOD) & (GCLK_MASK_##_MOD))
+#define GATE_INIT(_MOD) GCLK_ref[GCLK_IDX_##_MOD] = IS_CLK_GATE_ON(_MOD) ? 1 : 0
+
+#define GCLK_IDX_DDR 0
+#define GCLK_NAME_DDR "DDR"
+#define GCLK_DEV_DDR "CLKGATE_DDR"
+#define GCLK_REG_DDR (HHI_GCLK_MPEG0)
+#define GCLK_MASK_DDR (1<<0)
+
+#define GCLK_IDX_DOS 1
+#define GCLK_NAME_DOS "DOS"
+#define GCLK_DEV_DOS "CLKGATE_DOS"
+#define GCLK_REG_DOS (HHI_GCLK_MPEG0)
+#define GCLK_MASK_DOS (1<<1)
+
+#define GCLK_IDX_RESERVED0_0 2
+#define GCLK_NAME_RESERVED0_0 "RESERVED0_0"
+#define GCLK_DEV_RESERVED0_0 "CLKGATE_RESERVED0_0"
+#define GCLK_REG_RESERVED0_0 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_0 (1<<2)
+
+#define GCLK_IDX_RESERVED0_1 3
+#define GCLK_NAME_RESERVED0_1 "RESERVED0_1"
+#define GCLK_DEV_RESERVED0_1 "CLKGATE_RESERVED0_1"
+#define GCLK_REG_RESERVED0_1 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_1 (1<<3)
+
+/* #define GCLK_IDX_AHB_BRIDGE 4 */
+/* #define GCLK_NAME_AHB_BRIDGE "AHB_BRIDGE" */
+/* #define GCLK_DEV_AHB_BRIDGE "CLKGATE_AHB_BRIDGE" */
+/* #define GCLK_REG_AHB_BRIDGE (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_AHB_BRIDGE (1<<4) */
+
+#define GCLK_IDX_ISA 5
+#define GCLK_NAME_ISA "ISA"
+#define GCLK_DEV_ISA "CLKGATE_ISA"
+#define GCLK_REG_ISA (HHI_GCLK_MPEG0)
+#define GCLK_MASK_ISA (1<<5)
+
+/* NEW ADD */
+#define GCLK_IDX_PL310_CBUS 6
+#define GCLK_NAME_PL310_CBUS "PL310_CBUS"
+#define GCLK_DEV_PL310_CBUS "CLKGATE_PL310_CBUS"
+#define GCLK_REG_PL310_CBUS (HHI_GCLK_MPEG0)
+#define GCLK_MASK_PL310_CBUS (1<<6)
+
+#define GCLK_IDX_PERIPHS_TOP 7
+#define GCLK_NAME_PERIPHS_TOP "PERIPHS_TOP"
+#define GCLK_DEV_PERIPHS_TOP "CLKGATE_PERIPHS_TOP"
+#define GCLK_REG_PERIPHS_TOP (HHI_GCLK_MPEG0)
+#define GCLK_MASK_PERIPHS_TOP (1<<7)
+
+#define GCLK_IDX_SPICC 8
+#define GCLK_NAME_SPICC "SPICC"
+#define GCLK_DEV_SPICC "CLKGATE_SPICC"
+#define GCLK_REG_SPICC (HHI_GCLK_MPEG0)
+#define GCLK_MASK_SPICC (1<<8)
+
+#define GCLK_IDX_I2C 9
+#define GCLK_NAME_I2C "I2C"
+#define GCLK_DEV_I2C "CLKGATE_I2C"
+#define GCLK_REG_I2C (HHI_GCLK_MPEG0)
+#define GCLK_MASK_I2C (1<<9)
+
+#define GCLK_IDX_SAR_ADC 10
+#define GCLK_NAME_SAR_ADC "SAR_ADC"
+#define GCLK_DEV_SAR_ADC "CLKGATE_SAR_ADC"
+//#define GCLK_REG_SAR_ADC (HHI_SAR_CLK_CNTL) //no HHI_SAR_CLK_CNTL on TXL
+#define GCLK_REG_SAR_ADC (AO_SAR_CLK)
+#define GCLK_MASK_SAR_ADC (1<<8)
+
+#define GCLK_IDX_SMART_CARD_MPEG_DOMAIN 11
+#define GCLK_NAME_SMART_CARD_MPEG_DOMAIN "SMART_CARD_MPEG_DOMAIN"
+#define GCLK_DEV_SMART_CARD_MPEG_DOMAIN "CLKGATE_SMART_CARD_MPEG_DOMAIN"
+#define GCLK_REG_SMART_CARD_MPEG_DOMAIN (HHI_GCLK_MPEG0)
+#define GCLK_MASK_SMART_CARD_MPEG_DOMAIN (1<<11)
+
+#define GCLK_IDX_RANDOM_NUM_GEN 12
+#define GCLK_NAME_RANDOM_NUM_GEN "RANDOM_NUM_GEN"
+#define GCLK_DEV_RANDOM_NUM_GEN "CLKGATE_RANDOM_NUM_GEN"
+#define GCLK_REG_RANDOM_NUM_GEN (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RANDOM_NUM_GEN (1<<12)
+
+#define GCLK_IDX_UART0 13
+#define GCLK_NAME_UART0 "UART0"
+#define GCLK_DEV_UART0 "CLKGATE_UART0"
+#define GCLK_REG_UART0 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_UART0 (1<<13)
+
+/* gxb no this clock gate */
+/* #define GCLK_IDX_SDHC 14 */
+/* #define GCLK_NAME_SDHC "SDHC" */
+/* #define GCLK_DEV_SDHC "CLKGATE_SDHC" */
+/* #define GCLK_REG_SDHC (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_SDHC (1<<14) */
+
+#define GCLK_IDX_STREAM 15
+#define GCLK_NAME_STREAM "STREAM"
+#define GCLK_DEV_STREAM "CLKGATE_STREAM"
+#define GCLK_REG_STREAM (HHI_GCLK_MPEG0)
+#define GCLK_MASK_STREAM (1<<15)
+
+#define GCLK_IDX_ASYNC_FIFO 16
+#define GCLK_NAME_ASYNC_FIFO "ASYNC_FIFO"
+#define GCLK_DEV_ASYNC_FIFO "CLKGATE_ASYNC_FIFO"
+#define GCLK_REG_ASYNC_FIFO (HHI_GCLK_MPEG0)
+#define GCLK_MASK_ASYNC_FIFO (1<<16)
+
+/* gxb no this clock gate */
+/* #define GCLK_IDX_SDIO 17 */
+/* #define GCLK_NAME_SDIO "SDIO" */
+/* #define GCLK_DEV_SDIO "CLKGATE_SDIO" */
+/* #define GCLK_REG_SDIO (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_SDIO (1<<17) */
+
+/* gxb no this clock gate */
+/* #define GCLK_IDX_AUD_BUF 18 */
+/* #define GCLK_NAME_AUD_BUF "AUD_BUF" */
+/* #define GCLK_DEV_AUD_BUF "CLKGATE_AUD_BUF" */
+/* #define GCLK_REG_AUD_BUF (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_AUD_BUF (1<<18) */
+
+#define GCLK_IDX_HIU_PARSER 19
+#define GCLK_NAME_HIU_PARSER "HIU_PARSER"
+#define GCLK_DEV_HIU_PARSER "CLKGATE_HIU_PARSER"
+#define GCLK_REG_HIU_PARSER (HHI_GCLK_MPEG0)
+#define GCLK_MASK_HIU_PARSER (1<<19)
+
+#define GCLK_IDX_RESERVED0_2 20
+#define GCLK_NAME_RESERVED0_2 "RESERVED0_2"
+#define GCLK_DEV_RESERVED0_2 "CLKGATE_RESERVED0_2"
+#define GCLK_REG_RESERVED0_2 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_2 (1<<20)
+
+/* NEW ADD */
+#define GCLK_IDX_RESERVED0_3 21
+#define GCLK_NAME_RESERVED0_3 "RESERVED0_3 "
+#define GCLK_DEV_RESERVED0_3 "CLKGATE_RESERVED0_3 "
+#define GCLK_REG_RESERVED0_3 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_3 (1<<21)
+
+#define GCLK_IDX_RESERVED0_4 22
+#define GCLK_NAME_RESERVED0_4 "RESERVED0_4"
+#define GCLK_DEV_RESERVED0_4 "CLKGATE_RESERVED0_4"
+#define GCLK_REG_RESERVED0_4 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_4 (1<<22)
+
+#define GCLK_IDX_ASSIST_MISC 23
+#define GCLK_NAME_ASSIST_MISC "ASSIST_MISC"
+#define GCLK_DEV_ASSIST_MISC "CLKGATE_ASSIST_MISC"
+#define GCLK_REG_ASSIST_MISC (HHI_GCLK_MPEG0)
+#define GCLK_MASK_ASSIST_MISC (1<<23)
+
+
+#define GCLK_IDX_EMMC_A 24
+#define GCLK_NAME_EMMC_A "EMMC_A"
+#define GCLK_DEV_EMMC_A "CLKGATE_EMMC_A"
+#define GCLK_REG_EMMC_A (HHI_GCLK_MPEG0)
+#define GCLK_MASK_EMMC_A (1<<24)
+
+#define GCLK_IDX_EMMC_B 25
+#define GCLK_NAME_EMMC_B "EMMC_B"
+#define GCLK_DEV_EMMC_B "CLKGATE_EMMC_B"
+#define GCLK_REG_EMMC_B (HHI_GCLK_MPEG0)
+#define GCLK_MASK_EMMC_B (1<<25)
+
+#define GCLK_IDX_EMMC_C 26
+#define GCLK_NAME_EMMC_C "EMMC_C"
+#define GCLK_DEV_EMMC_C "CLKGATE_EMMC_C"
+#define GCLK_REG_EMMC_C (HHI_GCLK_MPEG0)
+#define GCLK_MASK_EMMC_C (1<<26)
+
+#define GCLK_IDX_RESERVED0_8 27
+#define GCLK_NAME_RESERVED0_8 "RESERVED0_8"
+#define GCLK_DEV_RESERVED0_8 "CLKGATE_RESERVED0_8"
+#define GCLK_REG_RESERVED0_8 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_8 (1<<27)
+
+#define GCLK_IDX_RESERVED0_9 28
+#define GCLK_NAME_RESERVED0_9 "RESERVED0_9"
+#define GCLK_DEV_RESERVED0_9 "CLKGATE_RESERVED0_9"
+#define GCLK_REG_RESERVED0_9 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_9 (1<<28)
+
+#define GCLK_IDX_RESERVED0_A 29
+#define GCLK_NAME_RESERVED0_A "RESERVED0_A"
+#define GCLK_DEV_RESERVED0_A "CLKGATE_RESERVED0_A"
+#define GCLK_REG_RESERVED0_A (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_A (1<<29)
+
+#define GCLK_IDX_SPI 30
+#define GCLK_NAME_SPI "SPI"
+#define GCLK_DEV_SPI "CLKGATE_SPI"
+#define GCLK_REG_SPI (HHI_GCLK_MPEG0)
+#define GCLK_MASK_SPI (1<<30)
+
+#define GCLK_IDX_RESERVED0_B 31
+#define GCLK_NAME_RESERVED0_B "RESERVED0_B"
+#define GCLK_DEV_RESERVED0_B "CLKGATE_RESERVED0_B"
+#define GCLK_REG_RESERVED0_B (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_B (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_RESERVED1_1 32
+#define GCLK_NAME_RESERVED1_1 "RESERVED1_1"
+#define GCLK_DEV_RESERVED1_1 "CLKGATE_RESERVED1_1"
+#define GCLK_REG_RESERVED1_1 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_1 (1<<0)
+
+
+#define GCLK_IDX_RESERVED1_2 33
+#define GCLK_NAME_RESERVED1_2 "RESERVED1_2"
+#define GCLK_DEV_RESERVED1_2 "CLKGATE_RESERVED1_2"
+#define GCLK_REG_RESERVED1_2 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_2 (1<<1)
+
+
+#define GCLK_IDX_AUD_IN 34
+#define GCLK_NAME_AUD_IN "AUD_IN"
+#define GCLK_DEV_AUD_IN "CLKGATE_AUD_IN"
+#define GCLK_REG_AUD_IN (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AUD_IN (1<<2)
+
+#define GCLK_IDX_ETHERNET 35
+#define GCLK_NAME_ETHERNET "ETHERNET"
+#define GCLK_DEV_ETHERNET "CLKGATE_ETHERNET"
+#define GCLK_REG_ETHERNET (HHI_GCLK_MPEG1)
+#define GCLK_MASK_ETHERNET (1<<3)
+
+/* g12a no reg */
+#if 0
+#define GCLK_IDX_ETH_CLK 145
+#define GCLK_NAME_ETH_CLK "ETH_CLK"
+#define GCLK_REG_ETH_CLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_ETH_CLK (1<<3)
+#endif
+
+#define GCLK_IDX_DEMUX 36
+#define GCLK_NAME_DEMUX "DEMUX"
+#define GCLK_DEV_DEMUX "CLKGATE_DEMUX"
+#define GCLK_REG_DEMUX (HHI_GCLK_MPEG1)
+#define GCLK_MASK_DEMUX (1<<4)
+
+#define GCLK_IDX_RESERVED1_3 37
+#define GCLK_NAME_RESERVED1_3 "RESERVED1_3"
+#define GCLK_DEV_RESERVED1_3 "CLKGATE_RESERVED1_3"
+#define GCLK_REG_RESERVED1_3 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_3 (1<<5)
+
+#define GCLK_IDX_AIU_AI_TOP_GLUE 38
+#define GCLK_NAME_AIU_AI_TOP_GLUE "AIU_AI_TOP_GLUE"
+#define GCLK_DEV_AIU_AI_TOP_GLUE "CLKGATE_AIU_AI_TOP_GLUE"
+#define GCLK_REG_AIU_AI_TOP_GLUE (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AI_TOP_GLUE (1<<6)
+
+#define GCLK_IDX_AIU_IEC958 39
+#define GCLK_NAME_AIU_IEC958 "AIU_IEC958"
+#define GCLK_DEV_AIU_IEC958 "CLKGATE_AIU_IEC958"
+#define GCLK_REG_AIU_IEC958 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_IEC958 (1<<7)
+
+#define GCLK_IDX_AIU_I2S_OUT 40
+#define GCLK_NAME_AIU_I2S_OUT "AIU_I2S_OUT"
+#define GCLK_DEV_AIU_I2S_OUT "CLKGATE_AIU_I2S_OUT"
+#define GCLK_REG_AIU_I2S_OUT (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_I2S_OUT (1<<8)
+
+#define GCLK_IDX_AIU_AMCLK_MEASURE 41
+#define GCLK_NAME_AIU_AMCLK_MEASURE "AIU_AMCLK_MEASURE"
+#define GCLK_DEV_AIU_AMCLK_MEASURE "CLKGATE_AIU_AMCLK_MEASURE"
+#define GCLK_REG_AIU_AMCLK_MEASURE (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AMCLK_MEASURE (1<<9)
+
+#define GCLK_IDX_AIU_AIFIFO2 42
+#define GCLK_NAME_AIU_AIFIFO2 "AIU_AIFIFO2"
+#define GCLK_DEV_AIU_AIFIFO2 "CLKGATE_AIU_AIFIFO2"
+#define GCLK_REG_AIU_AIFIFO2 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AIFIFO2 (1<<10)
+
+#define GCLK_IDX_AIU_AUD_MIXER 43
+#define GCLK_NAME_AIU_AUD_MIXER "AIU_AUD_MIXER"
+#define GCLK_DEV_AIU_AUD_MIXER "CLKGATE_AIU_AUD_MIXER"
+#define GCLK_REG_AIU_AUD_MIXER (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AUD_MIXER (1<<11)
+
+#define GCLK_IDX_AIU_MIXER_REG 44
+#define GCLK_NAME_AIU_MIXER_REG "AIU_MIXER_REG"
+#define GCLK_DEV_AIU_MIXER_REG "CLKGATE_AIU_MIXER_REG"
+#define GCLK_REG_AIU_MIXER_REG (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_MIXER_REG (1<<12)
+
+#define GCLK_IDX_AIU_ADC 45
+#define GCLK_NAME_AIU_ADC "AIU_ADC"
+#define GCLK_DEV_AIU_ADC "CLKGATE_AIU_ADC"
+#define GCLK_REG_AIU_ADC (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_ADC (1<<13)
+
+#define GCLK_IDX_BLK_MOV 46
+#define GCLK_NAME_BLK_MOV "BLK_MOV"
+#define GCLK_DEV_BLK_MOV "CLKGATE_BLK_MOV"
+#define GCLK_REG_BLK_MOV (HHI_GCLK_MPEG1)
+#define GCLK_MASK_BLK_MOV (1<<14)
+
+/* NEW ADD */
+#define GCLK_IDX_AIU_TOP_LEVEL 47
+#define GCLK_NAME_AIU_TOP_LEVEL "AIU_TOP_LEVEL"
+#define GCLK_DEV_AIU_TOP_LEVEL "CLKGATE_AIU_TOP_LEVEL"
+#define GCLK_REG_AIU_TOP_LEVEL (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_TOP_LEVEL (1<<15)
+
+//g12a no reg
+#if 0
+#define GCLK_NAME_PCM_MCLK "PCM_MCLK"
+#define GCLK_REG_PCM_MCLK (HHI_PCM_CLK_CNTL)
+#define GCLK_MASK_PCM_MCLK (1<<9)
+
+#define GCLK_NAME_PCM_SCLK "PCM_SCLK"
+#define GCLK_REG_PCM_SCLK (HHI_PCM_CLK_CNTL)
+#define GCLK_MASK_PCM_SCLK (1<<22)
+#endif
+
+#define GCLK_IDX_UART1 48
+#define GCLK_NAME_UART1 "UART1"
+#define GCLK_DEV_UART1 "CLKGATE_UART1"
+#define GCLK_REG_UART1 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_UART1 (1<<16)
+
+#define GCLK_IDX_RESERVED1_4 49
+#define GCLK_NAME_RESERVED1_4 "RESERVED1_4"
+#define GCLK_DEV_RESERVED1_4 "CLKGATE_RESERVED1_4"
+#define GCLK_REG_RESERVED1_4 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_4 (1<<17)
+
+/* NEW ADD */
+#define GCLK_IDX_RESERVED1_5 50
+#define GCLK_NAME_RESERVED1_5 "RESERVED1_5"
+#define GCLK_DEV_RESERVED1_5 "CLKGATE_RESERVED1_5"
+#define GCLK_REG_RESERVED1_5 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_5 (1<<18)
+
+#define GCLK_IDX_RESERVED1_6 51
+#define GCLK_NAME_RESERVED1_6 "RESERVED1_6"
+#define GCLK_DEV_RESERVED1_6 "CLKGATE_RESERVED1_6"
+#define GCLK_REG_RESERVED1_6 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_6 (1<<19)
+
+#define GCLK_IDX_GE2D 52
+#define GCLK_NAME_GE2D "GE2D"
+#define GCLK_DEV_GE2D "CLKGATE_GE2D"
+#define GCLK_REG_GE2D (HHI_GCLK_MPEG1)
+#define GCLK_MASK_GE2D (1<<20)
+
+#define GCLK_IDX_USB0 53
+#define GCLK_NAME_USB0 "USB0"
+#define GCLK_DEV_USB0 "CLKGATE_USB0"
+#define GCLK_REG_USB0 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_USB0 (1<<21)
+
+#define GCLK_IDX_USB1 54
+#define GCLK_NAME_USB1 "USB1"
+#define GCLK_DEV_USB1 "CLKGATE_USB1"
+#define GCLK_REG_USB1 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_USB1 (1<<22)
+
+#define GCLK_IDX_RESET 55
+#define GCLK_NAME_RESET "RESET"
+#define GCLK_DEV_RESET "CLKGATE_RESET"
+#define GCLK_REG_RESET (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESET (1<<23)
+
+#define GCLK_IDX_NAND_CLK 56
+#define GCLK_NAME_NAND_CLK "NAND CLK"
+#define GCLK_DEV_NAND_CLK "HHI_NAND_CLK"
+#define GCLK_REG_NAND_CLK (HHI_NAND_CLK_CNTL)
+#define GCLK_MASK_NAND_CLK (1<<7)
+
+#define GCLK_IDX_HIU_PARSER_TOP 57
+#define GCLK_NAME_HIU_PARSER_TOP "HIU_PARSER_TOP"
+#define GCLK_DEV_HIU_PARSER_TOP "CLKGATE_HIU_PARSER_TOP"
+#define GCLK_REG_HIU_PARSER_TOP (HHI_GCLK_MPEG1)
+#define GCLK_MASK_HIU_PARSER_TOP (1<<25)
+
+/* NEW ADD */
+
+/* g12a no reg */
+#if 0
+#define GCLK_NAME_USB_CLK "USB_CLK"
+#define GCLK_REG_USB_CLK (HHI_USB_CLK_CNTL)
+#define GCLK_MASK_USB_CLK (1<<9)
+#endif
+
+#define GCLK_IDX_USB_GENERAL 58
+#define GCLK_NAME_USB_GENERAL "USB_GENERAL"
+#define GCLK_DEV_USB_GENERAL "CLKGATE_USB_GENERAL"
+#define GCLK_REG_USB_GENERAL (HHI_GCLK_MPEG1)
+#define GCLK_MASK_USB_GENERAL (1<<26)
+
+#define GCLK_IDX_RESERVED1_7 59
+#define GCLK_NAME_RESERVED1_7 "RESERVED1_7"
+#define GCLK_DEV_RESERVED1_7 "CLKGATE_RESERVED1_7"
+#define GCLK_REG_RESERVED1_7 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_7 (1<<27)
+
+/* #define GCLK_IDX_VDIN1 60 */
+/* #define GCLK_NAME_VDIN1 "VDIN1" */
+/* #define GCLK_DEV_VDIN1 "CLKGATE_VDIN1" */
+/* #define GCLK_REG_VDIN1 (HHI_GCLK_MPEG1) */
+/* #define GCLK_MASK_VDIN1 (1<<28) */
+
+#define GCLK_IDX_AHB_ARB0 61
+#define GCLK_NAME_AHB_ARB0 "AHB_ARB0"
+#define GCLK_DEV_AHB_ARB0 "CLKGATE_AHB_ARB0"
+#define GCLK_REG_AHB_ARB0 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AHB_ARB0 (1<<29)
+
+#define GCLK_IDX_EFUSE 62
+#define GCLK_NAME_EFUSE "EFUSE"
+#define GCLK_DEV_EFUSE "CLKGATE_EFUSE"
+#define GCLK_REG_EFUSE (HHI_GCLK_MPEG1)
+#define GCLK_MASK_EFUSE (1<<30)
+
+#define GCLK_IDX_ROM_CLK 63
+#define GCLK_NAME_ROM_CLK "ROM_CLK"
+#define GCLK_DEV_ROM_CLK "CLKGATE_ROM_CLK"
+#define GCLK_REG_ROM_CLK (HHI_GCLK_MPEG1)
+#define GCLK_MASK_ROM_CLK (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_RESERVED2_0 64
+#define GCLK_NAME_RESERVED2_0 "RESERVED2_0"
+#define GCLK_DEV_RESERVED2_0 "CLKGATE_RESERVED2_0"
+#define GCLK_REG_RESERVED2_0 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_0 (1<<0)
+
+#define GCLK_IDX_AHB_DATA_BUS 65
+#define GCLK_NAME_AHB_DATA_BUS "AHB_DATA_BUS"
+#define GCLK_DEV_AHB_DATA_BUS "CLKGATE_AHB_DATA_BUS"
+#define GCLK_REG_AHB_DATA_BUS (HHI_GCLK_MPEG2)
+#define GCLK_MASK_AHB_DATA_BUS (1<<1)
+
+#define GCLK_IDX_AHB_CONTROL_BUS 66
+#define GCLK_NAME_AHB_CONTROL_BUS "AHB_CONTROL_BUS"
+#define GCLK_DEV_AHB_CONTROL_BUS "CLKGATE_AHB_CONTROL_BUS"
+#define GCLK_REG_AHB_CONTROL_BUS (HHI_GCLK_MPEG2)
+#define GCLK_MASK_AHB_CONTROL_BUS (1<<2)
+
+#define GCLK_IDX_HDMI_INTR_SYNC 67
+#define GCLK_NAME_HDMI_INTR_SYNC "HDMI_INTR_SYNC"
+#define GCLK_DEV_HDMI_INTR_SYNC "CLKGATE_HDMI_INTR_SYNC"
+#define GCLK_REG_HDMI_INTR_SYNC (HHI_GCLK_MPEG2)
+#define GCLK_MASK_HDMI_INTR_SYNC (1<<3)
+
+#define GCLK_IDX_HDMI_PCLK 68
+#define GCLK_NAME_HDMI_PCLK "HDMI_PCLK"
+#define GCLK_DEV_HDMI_PCLK "CLKGATE_HDMI_PCLK"
+#define GCLK_REG_HDMI_PCLK (HHI_GCLK_MPEG2)
+#define GCLK_MASK_HDMI_PCLK (1<<4)
+
+#define GCLK_IDX_PDM 69
+#define GCLK_NAME_PDM "PDM"
+#define GCLK_DEV_PDM "CLKGATE_PDM"
+#define GCLK_REG_PDM (HHI_GCLK_MPEG2)
+#define GCLK_MASK_PDM (1<<5)
+
+#define GCLK_IDX_BT656 70
+#define GCLK_NAME_BT656 "BT656"
+#define GCLK_DEV_BT656 "CLKGATE_BT656"
+#define GCLK_REG_BT656 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_BT656 (1<<6)
+
+#define GCLK_IDX_BT656_2 71
+#define GCLK_NAME_BT656_2 "BT656_2"
+#define GCLK_DEV_BT656_2 "CLKGATE_BT656_2"
+#define GCLK_REG_BT656_2 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_BT656_2 (1<<7)
+
+#define GCLK_IDX_MISC_USB1_TO_DDR 72
+#define GCLK_NAME_MISC_USB1_TO_DDR "MISC_USB1_TO_DDR"
+#define GCLK_DEV_MISC_USB1_TO_DDR "CLKGATE_MISC_USB1_TO_DDR"
+#define GCLK_REG_MISC_USB1_TO_DDR (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MISC_USB1_TO_DDR (1<<8)
+
+#define GCLK_IDX_MISC_USB0_TO_DDR 73
+#define GCLK_NAME_MISC_USB0_TO_DDR "MISC_USB0_TO_DDR"
+#define GCLK_DEV_MISC_USB0_TO_DDR "CLKGATE_MISC_USB0_TO_DDR"
+#define GCLK_REG_MISC_USB0_TO_DDR (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MISC_USB0_TO_DDR (1<<9)
+
+#define GCLK_IDX_RESERVED2_4 74
+#define GCLK_NAME_RESERVED2_4 "RESERVED2_4"
+#define GCLK_DEV_RESERVED2_4 "CLKGATE_RESERVED2_4"
+#define GCLK_REG_RESERVED2_4 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_4 (1<<10)
+
+#define GCLK_IDX_MMC_PCLK 75
+#define GCLK_NAME_MMC_PCLK "MMC_PCLK"
+#define GCLK_DEV_MMC_PCLK "CLKGATE_MMC_PCLK"
+#define GCLK_REG_MMC_PCLK (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MMC_PCLK (1<<11)
+
+//g12a no reg
+#if 0
+#define GCLK_NAME_MMC_A_PCLK "MMC_A_PCLK"
+#define GCLK_REG_MMC_A_PCLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_MMC_A_PCLK (1<<2)
+
+#define GCLK_NAME_MMC_B_PCLK "MMC_B_PCLK"
+#define GCLK_REG_MMC_B_PCLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_MMC_B_PCLK (1<<1)
+
+#define GCLK_NAME_MMC_C_PCLK "MMC_C_PCLK"
+#define GCLK_REG_MMC_C_PCLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_MMC_C_PCLK (1<<0)
+#endif
+
+#define GCLK_NAME_EMMC_A_CLK "EMMC_A_CLK"
+#define GCLK_REG_EMMC_A_CLK (HHI_SD_EMMC_CLK_CNTL)
+#define GCLK_MASK_EMMC_A_CLK (1<<7)
+
+#define GCLK_NAME_EMMC_B_CLK "EMMC_B_CLK"
+#define GCLK_REG_EMMC_B_CLK (HHI_SD_EMMC_CLK_CNTL)
+#define GCLK_MASK_EMMC_B_CLK (1<<23)
+
+#define GCLK_IDX_MISC_DVIN 76
+#define GCLK_NAME_MISC_DVIN "MISC_DVIN"
+#define GCLK_DEV_MISC_DVIN "CLKGATE_MISC_DVIN"
+#define GCLK_REG_MISC_DVIN (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MISC_DVIN (1<<12)
+
+#define GCLK_IDX_RESERVED2_5 77
+#define GCLK_NAME_RESERVED2_5 "RESERVED2_5"
+#define GCLK_DEV_RESERVED2_5 "CLKGATE_RESERVED2_5"
+#define GCLK_REG_RESERVED2_5 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_5 (1<<13)
+
+#define GCLK_IDX_RESERVED2_6 78
+#define GCLK_NAME_RESERVED2_6 "RESERVED2_6"
+#define GCLK_DEV_RESERVED2_6 "CLKGATE_RESERVED2_6"
+#define GCLK_REG_RESERVED2_6 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_6 (1<<14)
+
+#define GCLK_IDX_UART2 79
+#define GCLK_NAME_UART2 "UART2"
+#define GCLK_DEV_UART2 "CLKGATE_UART2"
+#define GCLK_REG_UART2 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_UART2 (1<<15)
+
+#define GCLK_IDX_RESERVED2_7 80
+#define GCLK_NAME_RESERVED2_7 "RESERVED2_7"
+#define GCLK_DEV_RESERVED2_7 "CLKGATE_RESERVED2_7"
+#define GCLK_REG_RESERVED2_7 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_7 (1<<16)
+
+#define GCLK_IDX_RESERVED2_8 81
+#define GCLK_NAME_RESERVED2_8 "RESERVED2_8"
+#define GCLK_DEV_RESERVED2_8 "CLKGATE_RESERVED2_8"
+#define GCLK_REG_RESERVED2_8 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_8 (1<<17)
+
+#define GCLK_IDX_RESERVED2_9 82
+#define GCLK_NAME_RESERVED2_9 "RESERVED2_9"
+#define GCLK_DEV_RESERVED2_9 "CLKGATE_RESERVED2_9"
+#define GCLK_REG_RESERVED2_9 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_9 (1<<18)
+
+#define GCLK_IDX_RESERVED2_A 83
+#define GCLK_NAME_RESERVED2_A "RESERVED2_A"
+#define GCLK_DEV_RESERVED2_A "CLKGATE_RESERVED2_A"
+#define GCLK_REG_RESERVED2_A (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_A (1<<19)
+
+#define GCLK_IDX_RESERVED2_B 84
+#define GCLK_NAME_RESERVED2_B "RESERVED2_B"
+#define GCLK_DEV_RESERVED2_B "CLKGATE_RESERVED2_B"
+#define GCLK_REG_RESERVED2_B (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_B (1<<20)
+
+#define GCLK_IDX_UART3 85
+#define GCLK_NAME_UART3 "UART3"
+#define GCLK_DEV_UART3 "CLKGATE_UART3"
+#define GCLK_REG_UART3 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_UART3 (1<<21)
+
+#define GCLK_IDX_SANA 86
+#define GCLK_NAME_SANA "SANA"
+#define GCLK_DEV_SANA "CLKGATE_SANA"
+#define GCLK_REG_SANA (HHI_GCLK_MPEG2)
+#define GCLK_MASK_SANA (1<<22)
+
+#define GCLK_IDX_RESERVED2_D 87
+#define GCLK_NAME_RESERVED2_D "RESERVED2_D"
+#define GCLK_DEV_RESERVED2_D "CLKGATE_RESERVED2_D"
+#define GCLK_REG_RESERVED2_D (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_D (1<<23)
+
+#define GCLK_IDX_RESERVED2_E 88
+#define GCLK_NAME_RESERVED2_E "RESERVED2_E"
+#define GCLK_DEV_RESERVED2_E "CLKGATE_RESERVED2_E"
+#define GCLK_REG_RESERVED2_E (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_E (1<<24)
+
+#define GCLK_IDX_VPU_INTR 89
+#define GCLK_NAME_VPU_INTR "VPU_INTR"
+#define GCLK_DEV_VPU_INTR "CLKGATE_VPU_INTR"
+#define GCLK_REG_VPU_INTR (HHI_GCLK_MPEG2)
+#define GCLK_MASK_VPU_INTR (1<<25)
+
+#define GCLK_IDX_SECURE_AHP_APB3 90
+#define GCLK_NAME_SECURE_AHP_APB3 "SECURE_AHP_APB3"
+#define GCLK_DEV_SECURE_AHP_APB3 "CLKGATE_SECURE_AHP_APB3"
+#define GCLK_REG_SECURE_AHP_APB3 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_SECURE_AHP_APB3 (1<<26)
+
+#define GCLK_IDX_RESERVED2_F 91
+#define GCLK_NAME_RESERVED2_F "RESERVED2_F"
+#define GCLK_DEV_RESERVED2_F "CLKGATE_RESERVED2_F"
+#define GCLK_REG_RESERVED2_F (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_F (1<<27)
+
+#define GCLK_IDX_RESERVED2_10 92
+#define GCLK_NAME_RESERVED2_10 "RESERVED2_10"
+#define GCLK_DEV_RESERVED2_10 "CLKGATE_RESERVED2_10"
+#define GCLK_REG_RESERVED2_10 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_10 (1<<28)
+
+#define GCLK_IDX_CLK81_TO_A9 93
+#define GCLK_NAME_CLK81_TO_A9 "CLK81_TO_A9"
+#define GCLK_DEV_CLK81_TO_A9 "CLKGATE_CLK81_TO_A9"
+#define GCLK_REG_CLK81_TO_A9 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_CLK81_TO_A9 (1<<29)
+
+#define GCLK_IDX_GIC 94
+#define GCLK_NAME_GIC "GIC"
+#define GCLK_DEV_GIC "CLKGATE_GIC"
+#define GCLK_REG_GIC (HHI_GCLK_MPEG2)
+#define GCLK_MASK_GIC (1<<30)
+
+#define GCLK_IDX_RESERVED2_12 95
+#define GCLK_NAME_RESERVED2_12 "RESERVED2_12"
+#define GCLK_DEV_RESERVED2_12 "CLKGATE_RESERVED2_12"
+#define GCLK_REG_RESERVED2_12 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_12 (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_RESERVED3_0 96
+#define GCLK_NAME_RESERVED3_0 "RESERVED3_0"
+#define GCLK_DEV_RESERVED3_0 "CLKGATE_RESERVED3_0"
+#define GCLK_REG_RESERVED3_0 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_0 (1<<0)
+
+#define GCLK_IDX_VCLK2_VENCI 97
+#define GCLK_NAME_VCLK2_VENCI "VCLK2_VENCI"
+#define GCLK_DEV_VCLK2_VENCI "CLKGATE_VCLK2_VENCI"
+#define GCLK_REG_VCLK2_VENCI (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCI (1<<1)
+
+#define GCLK_IDX_VCLK2_VENCI1 98
+#define GCLK_NAME_VCLK2_VENCI1 "VCLK2_VENCI1"
+#define GCLK_DEV_VCLK2_VENCI1 "CLKGATE_VCLK2_VENCI1"
+#define GCLK_REG_VCLK2_VENCI1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCI1 (1<<2)
+
+#define GCLK_IDX_VCLK2_VENCP 99
+#define GCLK_NAME_VCLK2_VENCP "VCLK2_VENCP"
+#define GCLK_DEV_VCLK2_VENCP "CLKGATE_VCLK2_VENCP"
+#define GCLK_REG_VCLK2_VENCP (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCP (1<<3)
+
+#define GCLK_IDX_VCLK2_VENCP1 100
+#define GCLK_NAME_VCLK2_VENCP1 "VCLK2_VENCP1"
+#define GCLK_DEV_VCLK2_VENCP1 "CLKGATE_VCLK2_VENCP1"
+#define GCLK_REG_VCLK2_VENCP1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCP1 (1<<4)
+
+#define GCLK_IDX_VCLK2_VENCT 101
+#define GCLK_NAME_VCLK2_VENCT "VCLK2_VENCT"
+#define GCLK_DEV_VCLK2_VENCT "CLKGATE_VCLK2_VENCT"
+#define GCLK_REG_VCLK2_VENCT (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCT (1<<5)
+
+#define GCLK_IDX_VCLK2_VENCT1 102
+#define GCLK_NAME_VCLK2_VENCT1 "VCLK2_VENCT1"
+#define GCLK_DEV_VCLK2_VENCT1 "CLKGATE_VCLK2_VENCT1"
+#define GCLK_REG_VCLK2_VENCT1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCT1 (1<<6)
+
+#define GCLK_IDX_VCLK2_OTHER 103
+#define GCLK_NAME_VCLK2_OTHER "VCLK2_OTHER"
+#define GCLK_DEV_VCLK2_OTHER "CLKGATE_VCLK2_OTHER"
+#define GCLK_REG_VCLK2_OTHER (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_OTHER (1<<7)
+
+#define GCLK_IDX_VCLK2_ENCI 104
+#define GCLK_NAME_VCLK2_ENCI "VCLK2_ENCI"
+#define GCLK_DEV_VCLK2_ENCI "CLKGATE_VCLK2_ENCI"
+#define GCLK_REG_VCLK2_ENCI (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCI (1<<8)
+
+#define GCLK_IDX_VCLK2_ENCP 105
+#define GCLK_NAME_VCLK2_ENCP "VCLK2_ENCP"
+#define GCLK_DEV_VCLK2_ENCP "CLKGATE_VCLK2_ENCP"
+#define GCLK_REG_VCLK2_ENCP (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCP (1<<9)
+
+#define GCLK_IDX_DAC_CLK 106
+#define GCLK_NAME_DAC_CLK "DAC_CLK"
+#define GCLK_DEV_DAC_CLK "CLKGATE_DAC_CLK"
+#define GCLK_REG_DAC_CLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_DAC_CLK (1<<10)
+
+#define GCLK_IDX_RESERVED3_1 107
+#define GCLK_NAME_RESERVED3_1 "RESERVED3_1"
+#define GCLK_DEV_RESERVED3_1 "CLKGATE_RESERVED3_1"
+#define GCLK_REG_RESERVED3_1 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_1 (1<<11)
+
+#define GCLK_IDX_RESERVED3_2 108
+#define GCLK_NAME_RESERVED3_2 "RESERVED3_2"
+#define GCLK_DEV_RESERVED3_2 "CLKGATE_RESERVED3_2"
+#define GCLK_REG_RESERVED3_2 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_2 (1<<12)
+
+#define GCLK_IDX_RESERVED3_3 109
+#define GCLK_NAME_RESERVED3_3 "RESERVED3_3"
+#define GCLK_DEV_RESERVED3_3 "CLKGATE_RESERVED3_3"
+#define GCLK_REG_RESERVED3_3 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_3 (1<<13)
+
+#define GCLK_IDX_AIU_AOCLK 110
+#define GCLK_NAME_AIU_AOCLK "AIU_AOCLK"
+#define GCLK_DEV_AIU_AOCLK "CLKGATE_AIU_AOCLK"
+#define GCLK_REG_AIU_AOCLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_AIU_AOCLK (1<<14)
+
+#define GCLK_IDX_RESERVED3_4 111
+#define GCLK_NAME_RESERVED3_4 "RESERVED3_4"
+#define GCLK_DEV_RESERVED3_4 "CLKGATE_RESERVED3_4"
+#define GCLK_REG_RESERVED3_4 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_4 (1<<15)
+
+#define GCLK_IDX_AIU_ICE958_AMCLK 112
+#define GCLK_NAME_AIU_ICE958_AMCLK "AIU_ICE958_AMCLK"
+#define GCLK_DEV_AIU_ICE958_AMCLK "CLKGATE_AIU_ICE958_AMCLK"
+#define GCLK_REG_AIU_ICE958_AMCLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_AIU_ICE958_AMCLK (1<<16)
+
+#define GCLK_IDX_RESERVED3_5 113
+#define GCLK_NAME_RESERVED3_5 "RESERVED3_5"
+#define GCLK_DEV_RESERVED3_5 "CLKGATE_RESERVED3_5"
+#define GCLK_REG_RESERVED3_5 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_5 (1<<17)
+
+#define GCLK_IDX_RESERVED3_6 114
+#define GCLK_NAME_RESERVED3_6 "RESERVED3_6"
+#define GCLK_DEV_RESERVED3_6 "CLKGATE_RESERVED3_6"
+#define GCLK_REG_RESERVED3_6 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_6 (1<<18)
+
+#define GCLK_IDX_RESERVED3_7 115
+#define GCLK_NAME_RESERVED3_7 "RESERVED3_7"
+#define GCLK_DEV_RESERVED3_7 "CLKGATE_RESERVED3_7"
+#define GCLK_REG_RESERVED3_7 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_7 (1<<19)
+
+#define GCLK_IDX_ENC480P 116
+#define GCLK_NAME_ENC480P "ENC480P"
+#define GCLK_DEV_ENC480P "CLKGATE_ENC480P"
+#define GCLK_REG_ENC480P (HHI_GCLK_OTHER)
+#define GCLK_MASK_ENC480P (1<<20)
+
+#define GCLK_IDX_RANDOM_NUM_GEN1 117
+#define GCLK_NAME_RANDOM_NUM_GEN1 "RANDOM_NUM_GEN1"
+#define GCLK_DEV_RANDOM_NUM_GEN1 "CLKGATE_RANDOM_NUM_GEN1"
+#define GCLK_REG_RANDOM_NUM_GEN1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RANDOM_NUM_GEN1 (1<<21)
+
+#define GCLK_IDX_VCLK2_ENCT 118
+#define GCLK_NAME_VCLK2_ENCT "GCLK_VENCL_INT"
+#define GCLK_DEV_VCLK2_ENCT "CLKGATE_GCLK_VENCL_INT"
+#define GCLK_REG_VCLK2_ENCT (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCT (1<<22)
+
+#define GCLK_IDX_VCLK2_ENCL 119
+#define GCLK_NAME_VCLK2_ENCL "VLKC2_ENCL"
+#define GCLK_DEV_VCLK2_ENCL "CLKGATE_VCLK2_ENCL"
+#define GCLK_REG_VCLK2_ENCL (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCL (1<<23)
+
+#define GCLK_IDX_MMC_CLK 120
+#define GCLK_NAME_MMC_CLK "MMC_CLK"
+#define GCLK_DEV_MMC_CLK "CLKGATE_MMC_CLK"
+#define GCLK_REG_MMC_CLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_MMC_CLK (1<<24)
+
+#define GCLK_IDX_VCLK2_VENCL 121
+#define GCLK_NAME_VCLK2_VENCL "VCLK2_VENCL"
+#define GCLK_DEV_VCLK2_VENCL "CLKGATE_VCLK2_VENCL"
+#define GCLK_REG_VCLK2_VENCL (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCL (1<<25)
+
+#define GCLK_IDX_VCLK2_OTHER1 122
+#define GCLK_NAME_VCLK2_OTHER1 "VCLK2_OTHER1"
+#define GCLK_DEV_VCLK2_OTHER1 "CLKGATE_VCLK2_OTHER1"
+#define GCLK_REG_VCLK2_OTHER1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_OTHER1 (1<<26)
+
+#define GCLK_IDX_RESERVED3_9 123
+#define GCLK_NAME_RESERVED3_9 "RESERVED3_9"
+#define GCLK_DEV_RESERVED3_9 "CLKGATE_RESERVED3_9"
+#define GCLK_REG_RESERVED3_9 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_9 (1<<27)
+
+#define GCLK_IDX_RESERVED3_A 124
+#define GCLK_NAME_RESERVED3_A "RESERVED3_A"
+#define GCLK_DEV_RESERVED3_A "CLKGATE_RESERVED3_A"
+#define GCLK_REG_RESERVED3_A (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_A (1<<28)
+
+#define GCLK_IDX_RESERVED3_B 125
+#define GCLK_NAME_RESERVED3_B "RESERVED3_B"
+#define GCLK_DEV_RESERVED3_B "CLKGATE_RESERVED3_B"
+#define GCLK_REG_RESERVED3_B (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_B (1<<29)
+
+#define GCLK_IDX_RESERVED3_C 126
+#define GCLK_NAME_RESERVED3_C "RESERVED3_C"
+#define GCLK_DEV_RESERVED3_C "CLKGATE_RESERVED3_C"
+#define GCLK_REG_RESERVED3_C (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_C (1<<30)
+
+#define GCLK_IDX_EDP_CLK 127
+#define GCLK_NAME_EDP_CLK "EDP_CLK"
+#define GCLK_DEV_EDP_CLK "CLKGATE_EDP_CLK"
+#define GCLK_REG_EDP_CLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_EDP_CLK (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_MEDIA_CPU 128
+#define GCLK_NAME_MEDIA_CPU "MEDIA_CPU"
+#define GCLK_DEV_MEDIA_CPU "CLKGATE_MEDIA_CPU"
+#define GCLK_REG_MEDIA_CPU (HHI_GCLK_AO)
+#define GCLK_MASK_MEDIA_CPU (1<<0)
+
+#define GCLK_IDX_AHB_SRAM 129
+#define GCLK_NAME_AHB_SRAM "AHB_SRAM"
+#define GCLK_DEV_AHB_SRAM "CLKGATE_AHB_SRAM"
+#define GCLK_REG_AHB_SRAM (HHI_GCLK_AO)
+#define GCLK_MASK_AHB_SRAM (1<<1)
+
+#define GCLK_IDX_AHB_BUS 130
+#define GCLK_NAME_AHB_BUS "AHB_BUS"
+#define GCLK_DEV_AHB_BUS "CLKGATE_AHB_BUS"
+#define GCLK_REG_AHB_BUS (HHI_GCLK_AO)
+#define GCLK_MASK_AHB_BUS (1<<2)
+
+#define GCLK_IDX_AO_REGS 131
+#define GCLK_NAME_AO_REGS "AO_REGS"
+#define GCLK_DEV_AO_REGS "CLKGATE_AO_REGS"
+#define GCLK_REG_AO_REGS (HHI_GCLK_AO)
+#define GCLK_MASK_AO_REGS (1<<3)
+
+#define GCLK_NAME_I2C_AO "I2C_AO"
+#define GCLK_REG_I2C_AO (HHI_GCLK_AO)
+#define GCLK_MASK_I2C_AO (1<<4)
+
+
+#define GCLK_IDX_CTS_ENCI 132
+#define GCLK_NAME_CTS_ENCI "CTS_ENCI"
+#define GCLK_DEV_CTS_ENCI "CLKGATE_CTS_ENCI"
+#define GCLK_REG_CTS_ENCI (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCI (1<<0)
+
+#define GCLK_IDX_CTS_ENCT 133
+#define GCLK_NAME_CTS_ENCT "CTS_ENCT"
+#define GCLK_DEV_CTS_ENCT "CLKGATE_CTS_ENCT"
+#define GCLK_REG_CTS_ENCT (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCT (1<<1)
+
+#define GCLK_IDX_CTS_ENCP 134
+#define GCLK_NAME_CTS_ENCP "CTS_ENCP"
+#define GCLK_DEV_CTS_ENCP "CLKGATE_CTS_ENCP"
+#define GCLK_REG_CTS_ENCP (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCP (1<<2)
+
+#define GCLK_IDX_CTS_ENCL 135
+#define GCLK_NAME_CTS_ENCL "CTS_ENCL"
+#define GCLK_DEV_CTS_ENCL "CLKGATE_CTS_ENCL"
+#define GCLK_REG_CTS_ENCL (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCL (1<<3)
+
+#define GCLK_IDX_CTS_VDAC 136
+#define GCLK_NAME_CTS_VDAC "CTS_VDAC"
+#define GCLK_DEV_CTS_VDAC "CLKGATE_CTS_VDAC"
+#define GCLK_REG_CTS_VDAC (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_VDAC (1<<4)
+
+#define GCLK_IDX_CTS_HDMI_TX_PIXEL 137
+#define GCLK_NAME_CTS_HDMI_TX_PIXEL "CTS_HDMI_TX_PIXEL"
+#define GCLK_DEV_CTS_HDMI_TX_PIXEL "CLKGATE_CTS_HDMI_TX_PIXEL"
+#define GCLK_REG_CTS_HDMI_TX_PIXEL (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_HDMI_TX_PIXEL (1<<5)
+
+#define GCLK_IDX_AUD 138
+#define GCLK_NAME_AUD "AUD"
+#define GCLK_DEV_AUD "CLKGATE_AUD"
+#define GCLK_REG_AUD (HHI_AUD_CLK_CNTL)
+#define GCLK_MASK_AUD (1<<23)
+
+
+#define GCLK_IDX_AUD2 138
+#define GCLK_NAME_AUD2 "AUD2"
+#define GCLK_DEV_AUD2 "CLKGATE_AUD2"
+#define GCLK_REG_AUD2 (HHI_AUD_CLK_CNTL)
+#define GCLK_MASK_AUD2 (1<<8)
+
+
+#define GCLK_NAME_AUD_CLK_2 "AUD_CLK_2"
+#define GCLK_REG_AUD_CLK_2 (HHI_AUD_CLK_CNTL2)
+#define GCLK_MASK_AUD_CLK_2 (1<<8)
+
+#define GCLK_IDX_AUD_CLK_3 138
+#define GCLK_NAME_AUD_CLK_3 "AUD_CLK"
+#define GCLK_DEV_AUD_CLK_3 "CLKGATE_AUD_CLK"
+#define GCLK_REG_AUD_CLK_3 (HHI_AUD_CLK_CNTL3)
+#define GCLK_MASK_AUD_CLK_3 (1<<16)
+
+#define GCLK_IDX_LCD_AN_PHY2 139
+#define GCLK_NAME_LCD_AN_PHY2 "LCD_AN_PHY2"
+#define GCLK_DEV_LCD_AN_PHY2 "CLKGATE_LCD_AN_PHY2"
+#define GCLK_REG_LCD_AN_PHY2 (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_LCD_AN_PHY2 (1<<7)
+
+#define GCLK_IDX_LCD_AN_PHY3 140
+#define GCLK_NAME_LCD_AN_PHY3 "LCD_AN_PHY3"
+#define GCLK_DEV_LCD_AN_PHY3 "CLKGATE_LCD_AN_PHY3"
+#define GCLK_REG_LCD_AN_PHY3 (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_LCD_AN_PHY3 (1<<6)
+
+#define GCLK_NAME_ATV_DEMO_VDAC "ATV_DEMO_VDAC"
+#define GCLK_REG_ATV_DEMO_VDAC (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_ATV_DEMO_VDAC (1<<8)
+
+#define GCLK_IDX_HDMI_PLL_CNTL 142
+#define GCLK_NAME_HDMI_PLL_CNTL "HDMI_PLL_CNTL"
+#define GCLK_DEV_HDMI_PLL_CNTL "GATE_HDMI_PLL_CNTL"
+#define GCLK_REG_HDMI_PLL_CNTL (HHI_HDMI_PLL_CNTL)
+#define GCLK_MASK_HDMI_PLL_CNTL (1<<30)
+
+#define GCLK_NAME_HDMITX_CLK "HDMITX_CLK"
+#define GCLK_REG_HDMITX_CLK (HHI_HDMI_CLK_CNTL)
+#define GCLK_MASK_HDMITX_CLK (1<<8)
+
+
+#define GCLK_NAME_HDMITX_CLK "HDMITX_CLK"
+#define GCLK_REG_HDMITX_CLK (HHI_HDMI_CLK_CNTL)
+#define GCLK_MASK_HDMITX_CLK (1<<8)
+
+#define GCLK_IDX_VDEC_CLK_1 144
+#define GCLK_NAME_VDEC_CLK_1 "VDEC_CLK_1"
+#define GCLK_DEV_VDEC_CLK_1 "CLKGATE_VDEC_CLK_1"
+#define GCLK_REG_VDEC_CLK_1 (HHI_VDEC_CLK_CNTL)
+#define GCLK_MASK_VDEC_CLK_1 (1<<8)
+
+#define GCLK_NAME_VDEC_CLK_2 "VDEC_CLK_2"
+#define GCLK_REG_VDEC_CLK_2 (HHI_VDEC3_CLK_CNTL)
+#define GCLK_MASK_VDEC_CLK_2 (1<<8)
+
+#define GCLK_NAME_VDEC2_CLK_1 "VDEC2_CLK_1"
+#define GCLK_REG_VDEC2_CLK_1 (HHI_VDEC2_CLK_CNTL)
+#define GCLK_MASK_VDEC2_CLK_1 (1<<8)
+
+#define GCLK_NAME_VDEC2_CLK_2 "VDEC2_CLK_2"
+#define GCLK_REG_VDEC2_CLK_2 (HHI_VDEC4_CLK_CNTL)
+#define GCLK_MASK_VDEC2_CLK_2 (1<<8)
+
+#define GCLK_IDX_HCODEC_CLK_1 145
+#define GCLK_NAME_HCODEC_CLK_1 "HCODEC_CLK"
+#define GCLK_DEV_HCODEC_CLK_1 "CLKGATE_HCODEC_CLK"
+#define GCLK_REG_HCODEC_CLK_1 (HHI_VDEC_CLK_CNTL)
+#define GCLK_MASK_HCODEC_CLK_1 (1<<24)
+
+#define GCLK_NAME_HCODEC_CLK_2 "HCODEC_CLK_2"
+#define GCLK_REG_HCODEC_CLK_2 (HHI_VDEC3_CLK_CNTL)
+#define GCLK_MASK_HCODEC_CLK_2 (1<<24)
+
+#define GCLK_NAME_HEVC_CLK_1 "HCODEC_CLK_1"
+#define GCLK_REG_HEVC_CLK_1 (HHI_VDEC2_CLK_CNTL)
+#define GCLK_MASK_HEVC_CLK_1 (1<<24)
+
+#define GCLK_NAME_HEVC_CLK_2 "HEVC_CLK_2"
+#define GCLK_REG_HEVC_CLK_2 (HHI_VDEC4_CLK_CNTL)
+#define GCLK_MASK_HEVC_CLK_2 (1<<24)
+
+#define GCLK_IDX_GEN_CLK 146
+#define GCLK_NAME_GEN_CLK "GEN_CLK"
+#define GCLK_DEV_GEN_CLK "CLKGATE_HCODEC_CLK"
+#define GCLK_REG_GEN_CLK (HHI_GEN_CLK_CNTL)
+#define GCLK_MASK_GEN_CLK (1<<11)
+
+#define GCLK_NAME_VPU_CLK_1 "VPU_CLK_1"
+#define GCLK_REG_VPU_CLK_1 (HHI_VPU_CLK_CNTL)
+#define GCLK_MASK_VPU_CLK_1 (1<<8)
+
+#define GCLK_NAME_VPU_CLK_2 "VPU_CLK_2"
+#define GCLK_REG_VPU_CLK_2 (HHI_VPU_CLK_CNTL)
+#define GCLK_MASK_VPU_CLK_2 (1<<24)
+
+
+#define GCLK_NAME_VPU_CLKB "VPU_CLKB"
+#define GCLK_REG_VPU_CLKB (HHI_VPU_CLKB_CNTL)
+#define GCLK_MASK_VPU_CLKB (1<<8)
+
+#define GCLK_NAME_VAPB_CLK_1 "VAPB_CLK_1"
+#define GCLK_REG_VAPB_CLK_1 (HHI_VAPBCLK_CNTL)
+#define GCLK_MASK_VAPB_CLK_1 (1<<8)
+
+#define GCLK_NAME_VAPB_CLK_2 "VAPB_CLK_2"
+#define GCLK_REG_VAPB_CLK_2 (HHI_VAPBCLK_CNTL)
+#define GCLK_MASK_VAPB_CLK_2 (1<<24)
+
+#define GCLK_NAME_MALI_CLK_1 "MALI_CLK_1"
+#define GCLK_REG_MALI_CLK_1 (HHI_MALI_CLK_CNTL)
+#define GCLK_MASK_MALI_CLK_1 (1<<8)
+
+#define GCLK_NAME_MALI_CLK_2 "MALI_CLK_2"
+#define GCLK_REG_MALI_CLK_2 (HHI_MALI_CLK_CNTL)
+#define GCLK_MASK_MALI_CLK_2 (1<<24)
+
+#define GCLK_NAME_PWM_A_CLK "PWM_A_CLK"
+#define GCLK_REG_PWM_A_CLK (CBUS_REG_ADDR(0x2156))
+#define GCLK_MASK_PWM_A_CLK (1<<15)
+
+#define GCLK_NAME_PWM_B_CLK "PWM_B_CLK"
+#define GCLK_REG_PWM_B_CLK (CBUS_REG_ADDR(0x2156))
+#define GCLK_MASK_PWM_B_CLK (1<<23)
+
+#define GCLK_NAME_PWM_C_CLK "PWM_C_CLK"
+#define GCLK_REG_PWM_C_CLK (CBUS_REG_ADDR(0x2196))
+#define GCLK_MASK_PWM_C_CLK (1<<15)
+
+#define GCLK_NAME_PWM_D_CLK "PWM_D_CLK"
+#define GCLK_REG_PWM_D_CLK (CBUS_REG_ADDR(0x2196))
+#define GCLK_MASK_PWM_D_CLK (1<<23)
+
+#define GCLK_NAME_PWM_E_CLK "PWM_E_CLK"
+#define GCLK_REG_PWM_E_CLK (CBUS_REG_ADDR(0x21b2))
+#define GCLK_MASK_PWM_E_CLK (1<<15)
+
+#define GCLK_NAME_PWM_F_CLK "PWM_D_CLK"
+#define GCLK_REG_PWM_F_CLK (CBUS_REG_ADDR(0x21b2))
+#define GCLK_MASK_PWM_F_CLK (1<<23)
+
+#define GCLK_NAME_VDIN_MEAS_CLK "VDIN_MEAS_CLK"
+#define GCLK_REG_VDIN_MEAS_CLK (HHI_VDIN_MEAS_CLK_CNTL)
+#define GCLK_MASK_VDIN_MEAS_CLK (1<<8)
+
+#define GCLK_NAME_MSR_CLK "MSR_CLK"
+#define GCLK_REG_MSR_CLK (CBUS_REG_ADDR(0x21d7))
+#define GCLK_MASK_MSR_CLK (1<<19)
+
+#define GCLK_NAME_MSR_HS_CLK "MSR_HS_CLK"
+#define GCLK_REG_MSR_HS_CLK (CBUS_REG_ADDR(0x21d9))
+#define GCLK_MASK_MSR_HS_CLK (1<<28)
+
+#define GCLK_NAME_32K_CLK "32K_CLK"
+#define GCLK_REG_32K_CLK (HHI_32K_CLK_CNTL)
+#define GCLK_MASK_32K_CLK (1<<15)
+
+
+
+#define GCLK_IDX_MAX 200
+
+extern short GCLK_ref[GCLK_IDX_MAX];
+
+#define REGISTER_CLK(_MOD) \
+static struct clk CLK_##_MOD = { \
+ .name = GCLK_NAME_##_MOD, \
+ .clock_index = GCLK_IDX_##_MOD, \
+ .clock_gate_reg_adr = GCLK_REG_##_MOD, \
+ .clock_gate_reg_mask = GCLK_MASK_##_MOD, \
+}
+
+#define CLK_LOOKUP_ITEM(_MOD) \
+ { \
+ .dev_id = GCLK_DEV_##_MOD, \
+ .con_id = GCLK_NAME_##_MOD, \
+ .clk = &CLK_##_MOD, \
+ }
+
+
+
+/**********************/
+/* internal audio dac control */
+#define ADAC_RESET (0x5000+0x00*4)
+#define ADAC_LATCH (0x5000+0x01*4)
+#define ADAC_POWER_CTRL_REG1 (0x5000+0x10*4)
+#define ADAC_POWER_CTRL_REG2 (0x5000+0x11*4)
+
+int audio_internal_dac_disable(void);
+
+/* video dac control */
+int video_dac_enable(unsigned char enable_mask);
+
+int video_dac_disable(void);
+
+
+#endif
diff --git a/arch/arm/mach-meson/sc2/sdio.c b/arch/arm/mach-meson/sc2/sdio.c
new file mode 100644
index 0000000..14ec635
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/sdio.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <asm/arch/io.h>
+#include <asm/arch/cpu_sdio.h>
+#include <asm/arch/secure_apb.h>
+#include <amlogic/cpu_id.h>
+#include <common.h>
+
+void cpu_sd_emmc_pwr_prepare(unsigned port)
+{
+}
+int cpu_sd_emmc_init(unsigned port)
+{
+ return 0;
+}
+
+/* return:
+ 0: insert
+ 1: not insert
+ */
+__weak int sd_emmc_detect(unsigned port)
+{
+ int ret = 0;
+
+ return ret;
+}
+
+
diff --git a/arch/arm/mach-meson/sc2/timer.c b/arch/arm/mach-meson/sc2/timer.c
new file mode 100644
index 0000000..8c16210
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/timer.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timer.h>
+#include <asm/types.h>
+
+uint32_t get_time(void)
+{
+ return readl(SYSCTRL_TIMERE);
+}
+
+void _udelay(unsigned int us)
+{
+#ifndef CONFIG_PXP_EMULATOR
+ unsigned int t0 = get_time();
+
+ while (get_time() - t0 <= us)
+ ;
+#endif
+}
diff --git a/arch/arm/mach-meson/sc2/tsensor.c b/arch/arm/mach-meson/sc2/tsensor.c
new file mode 100644
index 0000000..a6b6741
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/tsensor.c
@@ -0,0 +1,340 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <command.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/mailbox.h>
+#include <asm/arch/tsensor.h>
+#include <asm/arch/bl31_apis.h>
+
+int tsensor_tz_calibration(unsigned int type, unsigned int data)
+{
+ int ret;
+
+ register long x0 asm("x0") = TSENSOR_CALI_SET;
+ register long x1 asm("x1") = type;
+ register long x2 asm("x2") = data;
+ register long x3 asm("x3") = 0;
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+ } while (0);
+ ret = x0;
+
+ if (!ret)
+ return -1;
+ else
+ return 0;
+}
+
+int r1p1_codetotemp(unsigned long value, unsigned int u_efuse)
+{
+ int64_t temp;
+
+ temp = (value * ts_m) * (1 << 16) / (100 * (1 << 16) + ts_n * value);
+ if (u_efuse & 0x8000) {
+ temp = ((temp - (u_efuse & 0x7fff)) * ts_a / (1 << 16) - ts_b) / 10;
+ } else {
+ temp = ((temp + (u_efuse & 0x7fff)) * ts_a / (1 << 16) - ts_b) / 10;
+ }
+ return temp;
+}
+
+int r1p1_temp_read(int type)
+{
+ unsigned int ret, u_efuse;
+ unsigned int value_ts, value_all_ts;
+ int tmp = -1;
+ int i, cnt;
+ char buf[2];
+
+ switch (type) {
+ case 1:
+ /*enable thermal1*/
+ writel(T_CONTROL_DATA, TS_PLL_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL);
+ ret = readl(SYSCTRL_SEC_STATUS_REG10);/*thermal1 cali data in reg CFG10*/
+ mdelay(5);
+ buf[0] = (ret) & 0xff;
+ buf[1] = (ret >> 8) & 0xff;
+ u_efuse = buf[1];
+ u_efuse = (u_efuse << 8) | buf[0];
+ value_ts = 0;
+ value_all_ts = 0;
+ cnt = 0;
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_PLL_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_PLL_STAT0) & 0xffff;
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ value_ts = value_all_ts / cnt;
+ printf("pll tsensor avg: 0x%x, u_efuse: 0x%x\n", value_ts, u_efuse);
+ if (value_ts == 0) {
+ printf("pll tsensor read temp is zero\n");
+ return -1;
+ }
+ tmp = r1p1_codetotemp(value_ts, u_efuse);
+ printf("temp1: %d\n", tmp);
+ break;
+ case 2:
+ /*enable thermal2*/
+ writel(T_CONTROL_DATA, TS_DDR_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL);
+ ret = readl(SYSCTRL_SEC_STATUS_REG28);/*thermal2 cali data in reg CFG28*/
+ mdelay(5);
+ buf[0] = (ret) & 0xff;
+ buf[1] = (ret >> 8) & 0xff;
+ u_efuse = buf[1];
+ u_efuse = (u_efuse << 8) | buf[0];
+ value_ts = 0;
+ value_all_ts = 0;
+ cnt = 0;
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_DDR_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_DDR_STAT0) & 0xffff;
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ value_ts = value_all_ts / cnt;
+ printf("ddr tsensor avg: 0x%x, u_efuse: 0x%x\n", value_ts, u_efuse);
+ if (value_ts == 0) {
+ printf("ddr tsensor read temp is zero\n");
+ return -1;
+ }
+ tmp = r1p1_codetotemp(value_ts, u_efuse);
+ printf("temp1: %d\n", tmp);
+ break;
+ default:
+ printf("r1p1 tsensor trim type not support\n");
+ return -1;
+ }
+ return tmp;
+}
+
+unsigned int r1p1_temptocode(unsigned long value, int tempbase)
+{
+ unsigned long tmp1, tmp2, u_efuse, signbit;
+
+ printf("a b m n: %d, %d, %d, %d\n", ts_a, ts_b, ts_m, ts_n);
+ tmp1 = ((tempbase * 10 + ts_b) * (1 << 16)) / ts_a; /*ideal u*/
+ printf("%s : tmp1: 0x%lx\n", __func__, tmp1);
+ tmp2 = (ts_m * value * (1 << 16)) / ((1 << 16) * 100 + ts_n * value);
+ printf("%s : tmp2: 0x%lx\n", __func__, tmp2);
+ signbit = ((tmp1 > tmp2) ? 0 : 1);
+ u_efuse = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
+ u_efuse = (signbit << 15) | u_efuse;
+ return u_efuse;
+}
+
+int r1p1_temp_trim(int tempbase, int tempver, int type)
+{
+ unsigned int u_efuse, index_ts, index_ver;
+ unsigned int value_ts, value_all_ts;
+ int i, cnt;
+
+ printf("r1p1 temp trim type: 0x%x\n", type);
+ switch (type) {
+ case 0:
+ index_ver = 5;
+ if (tsensor_tz_calibration(index_ver, tempver) < 0)
+ printf("version tsensor thermal_calibration send error\n");
+ break;
+ case 1:
+ value_ts = 0;
+ value_all_ts = 0;
+ index_ts = 6;
+ cnt = 0;
+ /*enable thermal1*/
+ writel(T_CONTROL_DATA, TS_PLL_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL);
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_PLL_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_PLL_STAT0) & 0xffff;
+ printf("pll tsensor read: 0x%x\n", value_ts);
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ value_ts = value_all_ts / cnt;
+ printf("pll tsensor avg: 0x%x\n", value_ts);
+ if (value_ts == 0) {
+ printf("pll tsensor read temp is zero\n");
+ return -1;
+ }
+ u_efuse = r1p1_temptocode(value_ts, tempbase);
+ printf("ts efuse:%d\n", u_efuse);
+ printf("ts efuse:0x%x, index: %d\n", u_efuse, index_ts);
+ if (tsensor_tz_calibration(index_ts, u_efuse) < 0) {
+ printf("pll tsensor thermal_calibration send error\n");
+ return -1;
+ }
+ break;
+ case 2:
+ value_ts = 0;
+ value_all_ts = 0;
+ index_ts = 7;
+ cnt = 0;
+ /*enable thermal1*/
+ writel(T_CONTROL_DATA, TS_DDR_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL);
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_DDR_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_DDR_STAT0) & 0xffff;
+ printf("ddr tsensor read: 0x%x\n", value_ts);
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ value_ts = value_all_ts / cnt;
+ printf("ddr tsensor avg: 0x%x\n", value_ts);
+ if (value_ts == 0) {
+ printf("ddr tsensor read temp is zero\n");
+ return -1;
+ }
+ u_efuse = r1p1_temptocode(value_ts, tempbase);
+ printf("ts efuse:%d\n", u_efuse);
+ printf("ts efuse:0x%x, index: %d\n", u_efuse, index_ts);
+ if (tsensor_tz_calibration(index_ts, u_efuse) < 0) {
+ printf("ddr tsensor thermal_calibration send error\n");
+ return -1;
+ }
+ break;
+ default:
+ printf("r1p1 tsensor trim type not support\n");
+ return -1;
+ break;
+ }
+ return 0;
+}
+
+int temp_read_entry(void)
+{
+ unsigned int ret, ver;
+
+ ret = readl(SYSCTRL_SEC_STATUS_REG10);
+ ver = (ret >> 24) & 0xff;
+ if (0 == (ver & T_VER_MASK)) {
+ printf("tsensor no trimmed: calidata:0x%x\n",
+ readl(SYSCTRL_SEC_STATUS_REG10));
+ return -1;
+ }
+ ret = (ver & 0xf) >> 2;
+ switch (ret) {
+ case 0x0:
+ printf("temp type no support\n");
+ break;
+ case 0x1:
+ printf("temp type no support\n");
+ break;
+ case 0x2:
+ r1p1_temp_read(1);
+ r1p1_temp_read(2);
+ printf("read the thermal\n");
+ break;
+ case 0x3:
+ printf("temp type no support\n");
+ return -1;
+ break;
+ default:
+ printf("thermal version not support!!!Please check!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int temp_trim_entry(int tempbase, int tempver)
+{
+ unsigned int ret, ver;
+
+ ret = readl(SYSCTRL_SEC_STATUS_REG10);
+ ver = (ret >> 24) & 0xff;
+ if (ver & T_VER_MASK) {
+ printf("tsensor trimmed: cali data: 0x%x\n",
+ readl(SYSCTRL_SEC_STATUS_REG10));
+ return -1;
+ }
+
+ printf("tsensor input trim tempver, tempver:0x%x\n", tempver);
+ switch (tempver) {
+ case 0x88:
+ r1p1_temp_trim(tempbase, tempver, 1);
+ r1p1_temp_trim(tempbase, tempver, 2);
+ r1p1_temp_trim(tempbase, tempver, 0);
+ printf("triming the thermal by bbt-sw\n");
+ break;
+ case 0x89:
+ r1p1_temp_trim(tempbase, tempver, 1);
+ r1p1_temp_trim(tempbase, tempver, 2);
+ r1p1_temp_trim(tempbase, tempver, 0);
+ printf("triming the thermal by bbt-ops\n");
+ break;
+ case 0x8b:
+ r1p1_temp_trim(tempbase, tempver, 1);
+ r1p1_temp_trim(tempbase, tempver, 2);
+ r1p1_temp_trim(tempbase, tempver, 0);
+ printf("triming the thermal by slt\n");
+ break;
+ default:
+ printf("thermal version not support!!!Please check!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int temp_cooling_entry(void)
+{
+#ifdef CONFIG_AML_TSENSOR_COOL
+ int temp, temp1;
+
+ while (1) {
+ temp = r1p1_temp_read(1);
+ temp1 = r1p1_temp_read(2);
+ temp = temp > temp1 ? temp : temp1;
+ if (temp <= CONFIG_HIGH_TEMP_COOL) {
+ printf("device cool done\n");
+ break;
+ }
+ mdelay(2000);
+ printf("warning: temp %d over %d, cooling\n", temp,
+ CONFIG_HIGH_TEMP_COOL);
+ }
+#endif
+ return 0;
+}
diff --git a/arch/arm/mach-meson/sc2/usb.c b/arch/arm/mach-meson/sc2/usb.c
new file mode 100644
index 0000000..c082641
--- /dev/null
+++ b/arch/arm/mach-meson/sc2/usb.c
@@ -0,0 +1,466 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <power/regulator.h>
+#include <clk.h>
+#include <asm/arch/usb.h>
+#include <amlogic/cpu_id.h>
+
+#include <linux/compat.h>
+#include <linux/ioport.h>
+#include <asm-generic/gpio.h>
+
+#define PHY20_RESET_LEVEL_BIT 8
+#define PHY21_RESET_LEVEL_BIT 9
+#define USB_RESET_BIT 4
+
+#define USB2_PHY_PLL_OFFSET_40 (0x09400414)
+#define USB2_PHY_PLL_OFFSET_44 (0x927E0000)
+#define USB2_PHY_PLL_OFFSET_48 (0xac5f69e5)
+
+#define USB2_PHY_PLL_OFFSET_10 (0x80000fff)
+#define USB2_PHY_PLL_OFFSET_34 (0x78000)
+#define USB2_REVB_PHY_PLL_OFFSET_34 (0x70000)
+
+#define USB2_PHY_PLL_OFFSET_38_CLEAR (0)
+#define USB2_PHY_PLL_OFFSET_38_SET (0xe0004)
+#define USB2_PHY_PLL_OFFSET_50 (0xfe18)
+#define USB2_PHY_PLL_OFFSET_54 (0x2a)
+
+#define TUNING_DISCONNECT_THRESHOLD 0x3C
+
+static int Rev_flag = 0;
+
+static struct phy usb_phys[2];
+
+/*Rev_flag == 0XB, g12b and revB, tl1 */
+/*Rev_flag == 1, sm1 */
+static void phy_aml_usb2_check_rev (void)
+{
+ cpu_id_t cpu_id = get_cpu_id();
+
+ if (cpu_id.family_id == MESON_CPU_MAJOR_ID_G12B) {
+ if (cpu_id.chip_rev == 0xb)
+ Rev_flag = 0xb;
+ else
+ Rev_flag = 0;
+ } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SM1) {
+ Rev_flag = MESON_CPU_MAJOR_ID_SM1;
+ } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_A1) {
+ Rev_flag = MESON_CPU_MAJOR_ID_A1;
+ } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_C1) {
+ Rev_flag = MESON_CPU_MAJOR_ID_C1;
+ } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2)
+ Rev_flag = MESON_CPU_MAJOR_ID_SC2;
+ return;
+}
+
+static int phy_aml_usb2_get_rev_type (void)
+{
+ int val = 0;
+
+ switch (Rev_flag) {
+ case MESON_CPU_MAJOR_ID_SM1:
+ case MESON_CPU_MAJOR_ID_A1:
+ case MESON_CPU_MAJOR_ID_C1:
+ case MESON_CPU_MAJOR_ID_SC2:
+ case 0xb:
+ val = 1;
+ break;
+ default:
+ printk("amlogic usb phy need tuning\n");
+ val = 0;
+ break;
+ }
+
+ return val;
+}
+
+int get_usbphy_baseinfo(struct phy *usb_phys)
+{
+ struct udevice *bus;
+ struct uclass *uc;
+ int ret, i;
+ int count;
+
+ if (usb_phys[0].dev && usb_phys[1].dev)
+ return 0;
+
+ ret = uclass_get(UCLASS_USB, &uc);
+ if (ret)
+ return ret;
+ uclass_foreach_dev(bus, uc) {
+ debug("bus->name=%s, bus->driver->name =%s\n",
+ bus->name, bus->driver->name);
+ count = dev_count_phandle_with_args(bus, "phys", "#phy-cells");
+ debug("usb phy count=%u\n", count);
+ if (count <= 0)
+ return count;
+ for (i = 0; i < count; i++) {
+ ret = generic_phy_get_by_index(bus, i, &usb_phys[i]);
+ if (ret && ret != -ENOENT) {
+ pr_err("Failed to get USB PHY%d for %s\n",
+ i, bus->name);
+ return ret;
+ }
+ ret = generic_phy_getinfo(&usb_phys[i]);
+ if (ret)
+ return ret;
+ }
+ }
+ return 0;
+}
+
+static void set_pll_Calibration_default(uint32_t phy2_pll_base)
+{
+ u32 tmp;
+
+ tmp = (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x8));
+ tmp &= 0xfff;
+ tmp |= (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10));
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10))
+ = tmp;
+}
+
+void usb_reset(unsigned int reset_addr, int bit){
+ *(volatile unsigned int *)(unsigned long)reset_addr = (1 << bit);
+}
+
+static void usb_enable_phy_pll (void)
+{
+ *(volatile uint32_t *)(unsigned long)RESETCTRL_RESET0_LEVEL |= (3 << PHY20_RESET_LEVEL_BIT);
+}
+
+static void usb_disable_phy_pll (void)
+{
+ *(volatile uint32_t *)RESETCTRL_RESET0_LEVEL &= ~(3 << PHY20_RESET_LEVEL_BIT);
+}
+
+void set_usb_pll(uint32_t phy2_pll_base)
+{
+ int hardware_rev;
+
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))
+ = (USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET | USB_PHY2_ENABLE);
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44)) =
+ USB2_PHY_PLL_OFFSET_44;
+ hardware_rev = phy_aml_usb2_get_rev_type();
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x48)) =
+ USB2_PHY_PLL_OFFSET_48;
+ udelay(100);
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x40))
+ = (((USB2_PHY_PLL_OFFSET_40) | (USB_PHY2_ENABLE))
+ & (~(USB_PHY2_RESET)));
+
+ if (hardware_rev) {
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50))
+ = USB2_PHY_PLL_OFFSET_50;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x54))
+ = USB2_PHY_PLL_OFFSET_54;
+ set_pll_Calibration_default(phy2_pll_base);
+ } else {
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50))
+ = USB2_PHY_PLL_OFFSET_50;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10))
+ = USB2_PHY_PLL_OFFSET_10;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x38))
+ = USB2_PHY_PLL_OFFSET_38_CLEAR;
+ }
+
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0xc)) =
+ TUNING_DISCONNECT_THRESHOLD;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x34))
+ = USB2_PHY_PLL_OFFSET_34;
+ debug("tuning_disconnect_threshold=0x%x\n", TUNING_DISCONNECT_THRESHOLD);
+}
+
+int usb_save_phy_dev (unsigned int number, struct phy *phy)
+{
+ usb_phys[number].dev = phy->dev;
+ usb_phys[number].id = phy->id;
+ return 0;
+}
+
+int usb2_phy_init (struct phy *phy) {
+ struct phy_aml_usb2_priv *priv = dev_get_priv(phy->dev);
+ struct u2p_aml_regs *u2p_aml_reg;
+ u2p_r0_t dev_u2p_r0;
+ u2p_r1_t dev_u2p_r1;
+ int i,cnt;
+
+ usb_save_phy_dev(0, phy);
+ usb_enable_phy_pll();
+ //usb_set_power_domain();
+ phy_aml_usb2_check_rev();
+
+ *(volatile unsigned int *)(unsigned long)priv->reset_addr = (1 << USB_RESET_BIT);
+
+ udelay(500);
+ priv->usbphy_reset_bit[0] = PHY20_RESET_LEVEL_BIT;
+ priv->usbphy_reset_bit[1] = PHY21_RESET_LEVEL_BIT;
+
+ for (i = 0; i < priv->u2_port_num; i++) {
+ u2p_aml_reg = (struct u2p_aml_regs *)((ulong)(priv->base_addr + i * PHY_REGISTER_SIZE));
+ dev_u2p_r0.d32 = u2p_aml_reg->u2p_r0;
+ dev_u2p_r0.b.host_device= 1;
+ dev_u2p_r0.b.POR= 0;
+ u2p_aml_reg->u2p_r0 = dev_u2p_r0.d32;
+ udelay(10);
+ *(volatile unsigned int *)(unsigned long)priv->reset_addr = (1 << priv->usbphy_reset_bit[i]);
+ udelay(50);
+
+ /* wait for phy ready */
+ dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
+ cnt = 0;
+ while (dev_u2p_r1.b.phy_rdy != 1) {
+ dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
+ /*we wait phy ready max 1ms, common is 100us*/
+ if (cnt > 200)
+ break;
+ else {
+ cnt++;
+ udelay(5);
+ }
+ }
+ }
+
+ for (i = 0; i < priv->u2_port_num; i++) {
+ debug("------set usb pll\n");
+ set_usb_pll(priv->usb_phy2_pll_base_addr[i]);
+ }
+ return 0;
+
+}
+
+int usb2_phy_tuning(uint32_t phy2_pll_base, int port)
+{
+ unsigned long phy_reg_base;
+ unsigned int pll_set38, pll_set34;
+ unsigned int rev_type = 0;
+
+ if (port > 2)
+ return 0;
+
+ pll_set38 = USB2_PHY_PLL_OFFSET_38_SET;
+ pll_set34 = USB2_PHY_PLL_OFFSET_34;
+
+ debug("pll38=0x%08x, pll34=0x%08x,\n",
+ pll_set38, pll_set34);
+
+
+ phy_reg_base = phy2_pll_base;
+
+ rev_type = phy_aml_usb2_get_rev_type();
+ if (rev_type) {
+ return 0;
+ }
+
+ (*(volatile uint32_t *)(phy_reg_base + 0x38)) = pll_set38;
+ (*(volatile uint32_t *)(phy_reg_base + 0x34)) = pll_set34;
+ return 0;
+}
+
+/**************************************************************/
+/* device mode config */
+/**************************************************************/
+unsigned int usb_get_dwc_a_base_addr(void)
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ int ret;
+
+ if (!usb_phys[0].dev) {
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ return usb2_priv->dwc2_a_addr;
+}
+
+unsigned int usb_get_device_mode_phy_base(void)
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ int ret;
+
+ if (!usb_phys[0].dev) {
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ return usb2_priv->usb_phy2_pll_base_addr[1];
+}
+
+void usb_phy_tuning_reset(void)
+{
+ unsigned long phy_reg_base = usb_get_device_mode_phy_base();
+ int rev_type;
+
+ if (phy_reg_base == 0)
+ return;
+ rev_type = phy_aml_usb2_get_rev_type();
+
+ if (rev_type)
+ return;
+
+ (*(volatile uint32_t *)(phy_reg_base + 0x38)) = USB2_PHY_PLL_OFFSET_38_CLEAR;
+ (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB2_PHY_PLL_OFFSET_34;
+}
+
+void usb_device_mode_init(void){
+ u2p_r0_t dev_u2p_r0;
+ u2p_r1_t dev_u2p_r1;
+
+ usb_r0_t dev_usb_r0;
+ usb_r4_t dev_usb_r4;
+ int cnt, ret;
+ u2p_aml_regs_t * u2p_aml_regs;
+ usb_aml_regs_t *usb_aml_regs;
+ struct phy_aml_usb2_priv *usb2_priv;
+ struct phy_aml_usb3_priv *usb3_priv;
+ unsigned int phy_base_addr, reset_addr;
+
+ phy_aml_usb2_check_rev();
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return;
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ usb3_priv = dev_get_priv(usb_phys[1].dev);
+ if (!usb2_priv || !usb3_priv) {
+ printf("get usb phy address from dts failed\n");
+ return;
+ }
+
+ u2p_aml_regs = (u2p_aml_regs_t * )((unsigned long)(usb2_priv->base_addr + PHY_REGISTER_SIZE));
+ usb_aml_regs = (usb_aml_regs_t * )((ulong)usb3_priv->base_addr);
+ phy_base_addr = usb2_priv->usb_phy2_pll_base_addr[1];
+ reset_addr = usb2_priv->reset_addr;
+
+ //printf("PHY2=0x%08x,PHY3=0x%08x\n", u2p_aml_regs, usb_aml_regs);
+ printf("PHY2=%p,PHY3=%p\n", u2p_aml_regs, usb_aml_regs);
+ if ((*(volatile uint32_t *)(unsigned long)(phy_base_addr + 0x38)) != 0) {
+ usb_phy_tuning_reset();
+ mdelay(150);
+ }
+
+ //step 1: usb controller reset
+ usb_reset(reset_addr, USB_RESET_BIT);
+
+ // step 3: enable usb INT internal USB
+ dev_usb_r0.d32 = usb_aml_regs->usb_r0;
+ dev_usb_r0.b.u2d_ss_scaledown_mode = 0;
+ dev_usb_r0.b.u2d_act = 1;
+ usb_aml_regs->usb_r0 = dev_usb_r0.d32;
+
+ // step 4: disable usb phy sleep
+ dev_usb_r4.d32 = usb_aml_regs->usb_r4;
+ dev_usb_r4.b.p21_SLEEPM0 = 1;
+ usb_aml_regs->usb_r4 = dev_usb_r4.d32;
+
+ // step 5: config phy21 device mode
+ dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0;
+ dev_u2p_r0.b.host_device= 0;
+ dev_u2p_r0.b.POR= 0;
+ u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32;
+
+ udelay(10);
+ //step 6: phy21 reset
+ usb_reset(reset_addr, PHY21_RESET_LEVEL_BIT);
+ udelay(50);
+
+ // step 6: wait for phy ready
+ dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
+ cnt = 0;
+ while ((dev_u2p_r1.d32 & 0x00000001) != 1) {
+ dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
+ if (cnt > 200)
+ break;
+ else {
+ cnt++;
+ udelay(5);
+ }
+ }
+
+ //set_usb_phy21_pll();
+ set_usb_pll(phy_base_addr);
+ //--------------------------------------------------
+
+ // ------------- usb phy21 initinal end ----------
+
+ //--------------------------------------------------
+
+}
+
+static void usb_disable_phy(uint32_t phy2_pll_base)
+{
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))=
+ ((USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET) & (~USB_PHY2_ENABLE));
+ udelay(5);
+}
+
+static void usb_print_usb_baseinfo
+ (struct phy_aml_usb2_priv *usb2_priv, struct phy_aml_usb3_priv *usb3_priv)
+{
+ if (usb3_priv) {
+ printf("priv->usb3 port num = %d, config addr=0x%08x\n",
+ usb3_priv->usb3_port_num, usb3_priv->base_addr);
+ }
+ if (usb2_priv) {
+ printf("usb2 phy: config addr = 0x%08x, reset addr=0x%08x\n",
+ usb2_priv->base_addr, usb2_priv->reset_addr);
+
+ printf("usb2 phy: portnum=%d, phy-addr1= 0x%08x, phy-addr2= 0x%08x\n",
+ usb2_priv->u2_port_num, usb2_priv->usb_phy2_pll_base_addr[0],
+ usb2_priv->usb_phy2_pll_base_addr[1]);
+ printf("dwc2_a base addr: 0x%08x\n", usb2_priv->dwc2_a_addr);
+ }
+ phy_aml_usb2_check_rev();
+ printf("PHY version is 0x%02x\n", Rev_flag);
+}
+
+int usb_aml_detect_operation(int argc, char * const argv[])
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ struct phy_aml_usb3_priv *usb3_priv;
+ int ret;
+
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return 0;
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ usb3_priv = dev_get_priv(usb_phys[1].dev);
+
+ if (argc >= 2) {
+ if (strncmp(argv[1], "disable", 7) == 0) {
+ usb_disable_phy_pll();
+ usb_disable_phy(usb2_priv->usb_phy2_pll_base_addr[0]);
+ usb_disable_phy(usb2_priv->usb_phy2_pll_base_addr[1]);
+ printf("disable USB phy\n");
+ return 0;
+ }
+
+ if (strncmp(argv[1], "info", 4) == 0) {
+ usb_print_usb_baseinfo(usb2_priv, usb3_priv);
+ return 0;
+ }
+ }
+ return CMD_RET_USAGE;
+}
+
diff --git a/arch/arm/mach-meson/t7/Makefile b/arch/arm/mach-meson/t7/Makefile
new file mode 100644
index 0000000..cc7aa5d
--- /dev/null
+++ b/arch/arm/mach-meson/t7/Makefile
@@ -0,0 +1,16 @@
+
+obj-y := sdio.o pinctrl_init.o
+obj-y += bl31_apis.o
+obj-y += cpu_reset.o
+obj-y += timer.o
+obj-y += mailbox.o
+#obj-y += gate_init.o
+#obj-y += power_cal.o
+obj-$(CONFIG_CMD_PLLTEST) += pll.o
+obj-$(CONFIG_CMD_AML_MTEST) += core.o
+obj-y += usb.o
+obj-$(CONFIG_AML_TSENSOR) += tsensor.o
+obj-$(CONFIG_AML_OSCRING) += oscring.o
+obj-$(CONFIG_AML_HDMITX20) += hdmitx_hw.o hdmitx_clk.o
+obj-y += aml_efuse.o
+obj-$(CONFIG_SECURE_POWER_CONTROL) += pwrc.o
diff --git a/arch/arm/mach-meson/t7/aml_efuse.c b/arch/arm/mach-meson/t7/aml_efuse.c
new file mode 100644
index 0000000..9bbc421
--- /dev/null
+++ b/arch/arm/mach-meson/t7/aml_efuse.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ *
+ * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
+*/
+
+#include <common.h>
+#include <asm/arch/io.h>
+#include <amlogic/aml_efuse.h>
+#include <asm/arch/secure_apb.h>
+
+/*load license bit [0...127...255...511]*/
+#define OTP_BIT_LOAD(feat) (readl(OTP_LIC00 + (((feat)/32)<<2)) & (1<<((feat)%32)))
+
+#define FEAT_ENABLE_DEVICE_SCS_SIG_0 (10)
+#define FEAT_ENABLE_DEVICE_SCS_SIG_1 (11)
+#define IS_FEAT_EN_DEVICE_SCS_SIG() \
+ ((OTP_BIT_LOAD(FEAT_ENABLE_DEVICE_SCS_SIG_0) || \
+ OTP_BIT_LOAD(FEAT_ENABLE_DEVICE_SCS_SIG_1)) ? 1 : 0)
+/*check license bit*/
+#define OTP_BIT_CHECK(feat) (OTP_BIT_LOAD((feat)) ? 1 : 0)
+
+/* OTP_LIC block#3 ...*/
+#define FEAT_DISABLE_NBL2_SNOR (384+44)
+#define FEAT_DISABLE_NBL2_SNAND (384+45)
+#define FEAT_ENABLE_4BL2_SNOR (384+46)
+#define FEAT_ENABLE_8BL2_SNAND (384+47)
+#define FEAT_DISABLE_EMMC_USER (384+53)
+#define FEAT_DISABLE_EMMC_BOOT_0 (384+54)
+#define FEAT_DISABLE_EMMC_BOOT_1 (384+55)
+#define FEAT_DISABLE_NBL2_NAND (384+57)
+#define FEAT_DISABLE_8BL2_NAND (384+58)
+
+//function for EFUSE license query
+int IS_FEAT_BOOT_VERIFY(void)
+{
+ return IS_FEAT_EN_DEVICE_SCS_SIG();
+}
+
+int IS_FEAT_DIS_EMMC_USER(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_EMMC_USER);
+}
+
+int IS_FEAT_DIS_EMMC_BOOT_0(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_EMMC_BOOT_0);
+}
+
+int IS_FEAT_DIS_EMMC_BOOT_1(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_EMMC_BOOT_1);
+}
+
+int IS_FEAT_EN_4BL2_SNOR(void)
+{
+ return OTP_BIT_CHECK(FEAT_ENABLE_4BL2_SNOR);
+}
+
+int IS_FEAT_DIS_NBL2_SNOR(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_NBL2_SNOR);
+}
+
+int IS_FEAT_EN_8BL2_SNAND(void)
+{
+ return OTP_BIT_CHECK(FEAT_ENABLE_8BL2_SNAND);
+}
+
+int IS_FEAT_DIS_NBL2_SNAND(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_NBL2_SNAND);
+}
+
+int IS_FEAT_DIS_8BL2_NAND(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_8BL2_NAND);
+}
+
+int IS_FEAT_DIS_NBL2_NAND(void)
+{
+ return OTP_BIT_CHECK(FEAT_DISABLE_NBL2_NAND);
+}
diff --git a/arch/arm/mach-meson/t7/bl31_apis.c b/arch/arm/mach-meson/t7/bl31_apis.c
new file mode 100644
index 0000000..9bbc004
--- /dev/null
+++ b/arch/arm/mach-meson/t7/bl31_apis.c
@@ -0,0 +1,578 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ * Trustzone API
+ */
+
+#include <asm/arch/io.h>
+#include <asm/arch/efuse.h>
+#include <asm/cache.h>
+#include <asm/arch/bl31_apis.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+
+static long sharemem_input_base;
+static long sharemem_output_base;
+
+long get_sharemem_info(unsigned long function_id)
+{
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ : "+r" (function_id));
+
+ return function_id;
+}
+
+int32_t set_boot_params(const keymaster_boot_params *boot_params)
+{
+ const unsigned cmd = SET_BOOT_PARAMS;
+
+ if (!boot_params)
+ return -1;
+
+ if (!sharemem_input_base)
+ sharemem_input_base =
+ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE);
+
+ memcpy((void *)sharemem_input_base,
+ (const void *)boot_params, sizeof(keymaster_boot_params));
+
+ asm __volatile__("" : : : "memory");
+ register uint64_t x0 asm("x0") = cmd;
+ register uint64_t x1 asm("x1") = sizeof(keymaster_boot_params);
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1));
+ } while (0);
+
+ return (!x0)? -1: 0;
+}
+
+#ifdef CONFIG_EFUSE
+int32_t meson_trustzone_efuse(struct efuse_hal_api_arg *arg)
+{
+ int ret;
+ unsigned cmd, offset, size;
+ unsigned long *retcnt = (unsigned long *)(arg->retcnt_phy);
+
+ if (!sharemem_input_base)
+ sharemem_input_base =
+ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE);
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ if (arg->cmd == EFUSE_HAL_API_READ)
+ cmd = EFUSE_READ;
+ else if (arg->cmd == EFUSE_HAL_API_WRITE)
+ cmd = EFUSE_WRITE;
+ else
+ cmd = EFUSE_WRITE_PATTERN;
+ offset = arg->offset;
+ size = arg->size;
+
+ if (arg->cmd == EFUSE_HAL_API_WRITE)
+ memcpy((void *)sharemem_input_base,
+ (const void *)arg->buffer_phy, size);
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = cmd;
+ register uint64_t x1 asm("x1") = offset;
+ register uint64_t x2 asm("x2") = size;
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2));
+ } while (0);
+ ret = x0;
+ *retcnt = x0;
+
+ if ((arg->cmd == EFUSE_HAL_API_READ) && (ret != 0))
+ memcpy((void *)arg->buffer_phy,
+ (const void *)sharemem_output_base, ret);
+
+ if (!ret)
+ return -1;
+ else
+ return 0;
+}
+
+int32_t meson_trustzone_efuse_get_max(struct efuse_hal_api_arg *arg)
+{
+ int32_t ret;
+ unsigned cmd = 0;
+
+ if (arg->cmd == EFUSE_HAL_API_USER_MAX)
+ cmd = EFUSE_USER_MAX;
+
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = cmd;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0));
+ } while (0);
+ ret = x0;
+
+ if (!ret)
+ return -1;
+ else
+ return ret;
+}
+
+ssize_t meson_trustzone_efuse_writepattern(const char *buf, size_t count)
+{
+ struct efuse_hal_api_arg arg;
+ unsigned long retcnt;
+
+ if (count != EFUSE_BYTES)
+ return 0; /* Past EOF */
+
+ arg.cmd = EFUSE_HAL_API_WRITE_PATTERN;
+ arg.offset = 0;
+ arg.size = count;
+ arg.buffer_phy = (unsigned long)buf;
+ arg.retcnt_phy = (unsigned long)&retcnt;
+ int ret;
+ ret = meson_trustzone_efuse(&arg);
+ return ret;
+}
+#endif
+
+uint64_t meson_trustzone_efuse_check(unsigned char *addr)
+{
+ uint64_t ret = 0;
+ struct sram_hal_api_arg arg = {};
+
+ arg.cmd = SRAM_HAL_API_CHECK_EFUSE;
+ arg.req_len = 0x1000000;
+ arg.res_len = 0;
+ arg.req_phy_addr = (unsigned long)addr;
+ arg.res_phy_addr = (unsigned long)NULL;
+
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = CALL_TRUSTZONE_HAL_API;
+ register uint64_t x1 asm("x1") = TRUSTZONE_HAL_API_SRAM;
+ register uint64_t x2 asm("x2") = (unsigned long)(&arg);
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2));
+ } while (0);
+
+ ret = x0;
+
+ return ret;
+}
+
+void debug_efuse_cmd(unsigned long cmd)
+{
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ : : "r" (cmd));
+}
+
+void bl31_debug_efuse_write_pattern(const char *buf)
+{
+ if (!sharemem_input_base)
+ sharemem_input_base =
+ get_sharemem_info(GET_SHARE_MEM_INPUT_BASE);
+ memcpy((void *)sharemem_input_base, (const void *)buf, 512);
+
+ debug_efuse_cmd(DEBUG_EFUSE_WRITE_PATTERN);
+}
+
+void bl31_debug_efuse_read_pattern(char *buf)
+{
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+ debug_efuse_cmd(DEBUG_EFUSE_READ_PATTERN);
+
+ memcpy((void *)buf, (const void *)sharemem_output_base, 512);
+}
+
+void aml_set_jtag_state(unsigned state, unsigned select)
+{
+ uint64_t command;
+ if (state == JTAG_STATE_ON)
+ command = JTAG_ON;
+ else
+ command = JTAG_OFF;
+ asm __volatile__("" : : : "memory");
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : : "r" (command), "r"(select));
+}
+
+void wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value)
+{
+ register long x0 asm("x0") = 0x82000086;
+ register long x1 asm("x1") = cmd;
+ register long x2 asm("x2") = value;
+ register long x3 asm("x3") = 0;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+}
+
+unsigned aml_get_reboot_reason(void)
+{
+ unsigned reason;
+ uint64_t ret;
+
+ register uint64_t x0 asm("x0") = GET_REBOOT_REASON;
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ :"+r"(x0));
+ ret = x0;
+ reason = (unsigned)(ret&0xffffffff);
+ return reason;
+}
+
+void set_viu_probe_enable(void)
+{
+ register uint64_t x0 asm("x0") = VIU_PREOBE_EN;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ :"+r"(x0));
+}
+
+void power_set_dsp(unsigned int id, unsigned int powerflag)
+{
+ register long x0 asm("x0") = DSP_SEC_POWERSET;
+ register long x1 asm("x1") = id;
+ register long x2 asm("x2") = powerflag;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2));
+}
+
+void init_dsp(unsigned int id,unsigned int addr,unsigned int cfg0)
+{
+ register long x0 asm("x0") = START_HIFI4;
+ register long x1 asm("x1") = id;
+ register long x2 asm("x2") = addr;
+ register long x3 asm("x3") = cfg0;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+}
+
+
+unsigned aml_reboot(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2)
+{
+ register long x0 asm("x0") = function_id;
+ register long x1 asm("x1") = arg0;
+ register long x2 asm("x2") = arg1;
+ register long x3 asm("x3") = arg2;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+
+ return function_id;
+}
+
+/* clear boot sequence related registers */
+void aml_set_bootsequence(uint32_t val)
+{
+ register long x0 asm("x0") = SET_STORAGE_BOOTSEQUENCE;
+ register long x1 asm("x1") = val;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ :"+r"(x0)
+ : "r" (x1));
+
+ return;
+}
+
+void aml_set_reboot_reason(uint64_t function_id, uint64_t arg0, uint64_t arg1, uint64_t arg2)
+{
+ register long x0 asm("x0") = function_id;
+ register long x1 asm("x1") = arg0;
+ register long x2 asm("x2") = arg1;
+ register long x3 asm("x3") = arg2;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+
+ return ;
+}
+
+unsigned long aml_sec_boot_check(unsigned long nType,
+ unsigned long pBuffer,
+ unsigned long nLength,
+ unsigned long nOption)
+{
+ uint64_t ret = 1;
+
+//#define AML_SECURE_LOG_TE
+
+#if defined(AML_SECURE_LOG_TE)
+ #define AML_GET_TE(a) do{a = *((volatile unsigned int*)0xc1109988);}while(0);
+ unsigned nT1,nT2,nT3;
+#else
+ #define AML_GET_TE(...)
+#endif
+
+ AML_GET_TE(nT1);
+
+ switch (nType) {
+ case AML_D_P_W_EFUSE_AMLOGIC:
+ case AML_D_P_W_EFUSE_SECURE_BOOT:
+ break;
+ default:
+ return 0;
+ }
+
+ asm __volatile__("" : : : "memory");
+
+ register uint64_t x0 asm("x0") = AML_DATA_PROCESS;
+ register uint64_t x1 asm("x1") = nType;
+ register uint64_t x2 asm("x2") = pBuffer;
+ register uint64_t x3 asm("x3") = nLength;
+ register uint64_t x4 asm("x4") = nOption;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ __asmeq("%4", "x3")
+ __asmeq("%5", "x4")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2),"r"(x3),"r"(x4));
+ } while (0);
+
+ ret = x0;
+
+ AML_GET_TE(nT2);;
+
+ flush_dcache_range((unsigned long )pBuffer, (unsigned long )pBuffer+nLength);
+
+ AML_GET_TE(nT3);
+
+#if defined(AML_SECURE_LOG_TE)
+ printf("aml log : dec use %d(us) , flush cache used %d(us)\n",
+ nT2 - nT1, nT3 - nT2);
+#endif
+
+ return ret;
+}
+
+void set_usb_boot_function(unsigned long command)
+{
+ register long x0 asm("x0") = SET_USB_BOOT_FUNC;
+ register long x1 asm("x1") = command;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+}
+
+void set_boot_first_timeout(uint64_t arg0)
+{
+ register long x0 asm("x0") = SET_BOOT_FIRST;
+ register long x1 asm("x1") = arg0;
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+}
+void aml_system_off(void)
+{
+ /* TODO: Add poweroff capability */
+ aml_reboot(0x82000042, 1, 0, 0);
+ aml_reboot(0x84000008, 0, 0, 0);
+}
+
+int __get_chip_id(unsigned char *buff, unsigned int size)
+{
+ if (buff == NULL || size < 16)
+ return -1;
+
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ if (sharemem_output_base) {
+ register long x0 asm("x0") = GET_CHIP_ID;
+ register long x1 asm("x1") = 2;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+
+ if (x0 == 0) {
+ int version = *((unsigned int *)sharemem_output_base);
+
+ if (version == 2) {
+ memcpy(buff, (void *)sharemem_output_base + 4, 16);
+ }
+ else {
+ /**
+ * Legacy 12-byte chip ID read out, transform data
+ * to expected order format.
+ */
+ uint32_t chip_info = 0;//readl(P_AO_SEC_SD_CFG8);
+ uint8_t *ch;
+ int i;
+
+ ((uint32_t *)buff)[0] =
+ ((chip_info & 0xff000000) | // Family ID
+ ((chip_info << 8) & 0xff0000) | // Chip Revision
+ ((chip_info >> 8) & 0xff00)); // Package ID
+
+ ((uint32_t *)buff)[0] = htonl(((uint32_t *)buff)[0]);
+
+ /* Transform into expected order for display */
+ ch = (uint8_t *)(sharemem_output_base + 4);
+ for (i = 0; i < 12; i++)
+ buff[i + 4] = ch[11 - i];
+ }
+
+ return 0;
+ }
+ }
+
+ return -1;
+}
+
+int bl31_get_cornerinfo(uint8_t *outbuf, int size)
+{
+ int buff_len = 0;
+
+ if (outbuf == NULL) {
+ printf("BL33: corner efuse info storebuf is NULL\n");
+ return -1;
+ }
+
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ if (sharemem_output_base) {
+ register long x0 asm("x0") = OSCRING_EFUSE_GET;
+ register long x1 asm("x1") = size;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1));
+ } while(0);
+ buff_len = x0;
+ if (buff_len <= size) {
+ memcpy(outbuf, (void *)sharemem_output_base, buff_len);
+ return 0;
+ } else {
+ printf("BL33: corner efuse info buf len %d over storebuf size %d\n", buff_len, size);
+ return -1;
+ }
+ }
+ return -1;
+}
+
+int32_t get_avbkey_from_fip(uint8_t *buf, uint32_t buflen)
+{
+ const unsigned cmd = GET_AVBKEY_FROM_FIP;
+ uint32_t retlen = 0;
+ uint32_t ret = 0;
+
+ if (!buf)
+ return -1;
+
+ if (!sharemem_output_base)
+ sharemem_output_base =
+ get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ asm __volatile__("" : : : "memory");
+ register uint64_t x0 asm("x0") = cmd;
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0));
+ } while (0);
+
+ if (!x0)
+ ret = -1;
+ retlen = x0;
+
+ if (ret != -1 && buflen >= retlen)
+ memcpy(buf, (const void *)sharemem_output_base, retlen);
+
+ return ret;
+}
diff --git a/arch/arm/mach-meson/t7/core.c b/arch/arm/mach-meson/t7/core.c
new file mode 100644
index 0000000..8640828
--- /dev/null
+++ b/arch/arm/mach-meson/t7/core.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/types.h>
+#include <asm/arch/cpu.h>
+#include <common.h>
+
+const unsigned int core_map[] = {
+ 0x0,
+ 0x1,
+ 0x2,
+ 0x3,
+};
+
+int get_core_mpidr(unsigned int cpuid)
+{
+ unsigned int coremax = (unsigned int)(sizeof(core_map)/sizeof(unsigned int));
+
+ if (cpuid >= coremax)
+ return -1;
+ return core_map[cpuid];
+}
+
+int get_core_idx(unsigned int mpidr)
+{
+ unsigned int clusterid, cpuid;
+
+ cpuid = mpidr & 0xff;
+ clusterid = mpidr & 0xff00;
+
+ cpuid += (clusterid >> 6);
+
+ if (cpuid >= NR_CPUS)
+ return -1;
+
+ return cpuid;
+}
+
+int get_core_max(void)
+{
+ return (sizeof(core_map)/sizeof(unsigned int));
+}
diff --git a/arch/arm/mach-meson/t7/cpu_reset.c b/arch/arm/mach-meson/t7/cpu_reset.c
new file mode 100644
index 0000000..ca0a42d
--- /dev/null
+++ b/arch/arm/mach-meson/t7/cpu_reset.c
@@ -0,0 +1,59 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/types.h>
+#include <asm/arch/romboot.h>
+#include <asm/arch/cpu_reset.h>
+#include <asm/arch/io.h>
+#include <asm/arch/timer.h>
+#include <dm.h>
+#include <wdt.h>
+
+/*
+ *GPIOE_0 VDDEE_PWM
+ *GPIOE_1 VDDCPU_PWM
+ * */
+void set_pwm_to_input(void)
+{
+ //hxbao, need fine tune
+ #if 0
+ unsigned int val;
+
+ val = readl(AO_RTI_PINMUX_REG1);
+ val &= ~(0xff << 16);
+ writel(val, AO_RTI_PINMUX_REG1);/* clear pinmux */
+ val = readl(AO_GPIO_O_EN_N);
+ val &= ~(0x3 << 16);
+ val |= 0x3 << 16;
+ writel(val, AO_GPIO_O_EN_N);/* set input mode */
+ val = readl(AO_RTI_PULL_UP_EN_REG);
+ val &= ~(0x3 << 16);
+ writel(val, AO_RTI_PULL_UP_EN_REG);/* disable pull up/down */
+ #endif
+}
+
+void reset_system(void)
+{
+ struct udevice *watchdog_devp;
+ int ret;
+
+ set_pwm_to_input();
+
+ _udelay(10000); //wait print
+
+ ret = uclass_get_device_by_name(UCLASS_WDT, "watchdog", &watchdog_devp);
+ if (ret < 0) {
+ printf("failed to reset system because can't get wdt device\n");
+ return;
+ }
+ wdt_start(watchdog_devp, 0, 0);
+ while (1);
+}
+
+/* uboot reset interface */
+void reset_cpu(unsigned long flag){
+ reset_system();
+}
diff --git a/arch/arm/mach-meson/t7/firmware/acs/Makefile b/arch/arm/mach-meson/t7/firmware/acs/Makefile
new file mode 100644
index 0000000..01d869a
--- /dev/null
+++ b/arch/arm/mach-meson/t7/firmware/acs/Makefile
@@ -0,0 +1,437 @@
+#
+# Copyright (c) 2013-2014, ARM Limited and Contributors. All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are met:
+#
+# Redistributions of source code must retain the above copyright notice, this
+# list of conditions and the following disclaimer.
+#
+# Redistributions in binary form must reproduce the above copyright notice,
+# this list of conditions and the following disclaimer in the documentation
+# and/or other materials provided with the distribution.
+#
+# Neither the name of ARM nor the names of its contributors may be used
+# to endorse or promote products derived from this software without specific
+# prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+# AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+# IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+# ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+# LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+# CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+# SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+# INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+# CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+# ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+
+#
+# Default values for build configurations
+#
+
+export CROSS_COMPILE=/opt/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-
+
+include $(buildsrc)/config.mk
+include $(buildtree)/include/autoconf.mk
+include $(buildtree)/.config
+
+# Build verbosity
+V := 0
+# Debug build
+BUILD_TYPE := ${BL2_BUILD_TYPE}
+# Build architecture
+ARCH := aarch64
+# Build platform
+#DEFAULT_PLAT := gx
+PLAT := ${SOC}
+export PLAT
+# SPD choice
+SPD := none
+# Base commit to perform code check on
+BASE_COMMIT := origin/master
+# NS timer register save and restore
+NS_TIMER_SWITCH := 0
+# By default, Bl1 acts as the reset handler, not BL31
+RESET_TO_BL31 := 0
+
+# Checkpatch ignores
+CHECK_IGNORE = --ignore COMPLEX_MACRO
+
+CHECKPATCH_ARGS = --no-tree --no-signoff ${CHECK_IGNORE}
+CHECKCODE_ARGS = --no-patch --no-tree --no-signoff ${CHECK_IGNORE}
+
+ifeq (${V},0)
+ Q=@
+ CHECKCODE_ARGS += --no-summary --terse
+else
+ Q=
+endif
+export Q
+
+ifeq (${GIT_VERSION},)
+ GIT_VERSION := $(shell git describe --abbrev=7 --dirty --always --tags)
+endif
+ifeq (${BUILDER},)
+ BUILDER := ${USER}@$(shell hostname)
+endif
+
+BL_COMMON_SOURCES := common/bl_common.c \
+ common/debug.c \
+ lib/aarch64/cache_helpers.S \
+ lib/aarch64/misc_helpers.S \
+ lib/aarch64/tlb_helpers.S \
+ lib/aarch64/xlat_helpers.c \
+ lib/stdlib/std.c \
+ lib/io_storage.c \
+ plat/common/aarch64/platform_helpers.S
+
+BUILD_BASE := $(buildtree)/firmware
+#BUILD_PLAT := ${BUILD_BASE}/${PLAT}
+BUILD_PLAT := $(buildtree)/board/${BOARDDIR}/firmware
+#BUILD_PLAT := $(buildtree)/${BOARDDIR}/firmware
+
+# Convenience function for adding build definitions
+# $(eval $(call add_define,FOO)) will have:
+# -DFOO if $(FOO) is empty; -DFOO=$(FOO) otherwise
+define add_define
+DEFINES += -D$(1)$(if $(value $(1)),=$(value $(1)),)
+endef
+
+# Convenience function for verifying option has a boolean value
+# $(eval $(call assert_boolean,FOO)) will assert FOO is 0 or 1
+define assert_boolean
+$(and $(patsubst 0,,$(value $(1))),$(patsubst 1,,$(value $(1))),$(error $(1) must be boolean))
+endef
+
+ifeq (${PLAT},)
+ $(error "Error: Unknown platform. Please use PLAT=<platform name> to specify the platform.")
+endif
+
+all: msg_start
+
+msg_start:
+ @echo "Building ${BOARDDIR}/acs.bin"
+
+#include plat/${PLAT}/platform.mk
+#ifdef BL2_SOURCES
+NEED_BL2 := yes
+include acs.mk
+#endif
+
+# Include SPD Makefile if one has been specified
+ifneq (${SPD},none)
+ # We expect to locate an spd.mk under the specified SPD directory
+ SPD_MAKE := $(shell m="services/spd/${SPD}/${SPD}.mk"; [ -f "$$m" ] && echo "$$m")
+
+ ifeq (${SPD_MAKE},)
+ $(error Error: No services/spd/${SPD}/${SPD}.mk located)
+ endif
+ $(info Including ${SPD_MAKE})
+ include ${SPD_MAKE}
+
+ # If there's BL32 companion for the chosen SPD, and the SPD wants to build the
+ # BL2 from source, we expect that the SPD's Makefile would set NEED_BL32
+ # variable to "yes"
+endif
+
+.PHONY: all msg_start clean realclean distclean cscope locate-checkpatch checkcodebase checkpatch fiptool fip
+.SUFFIXES:
+
+INCLUDES += -Iinclude/bl2 \
+ -Iinclude/bl31 \
+ -Iinclude/common \
+ -Iinclude/drivers \
+ -Iinclude/drivers/arm \
+ -Iinclude/drivers/serial \
+ -Iinclude/lib \
+ -Iinclude/lib/aarch64 \
+ -Iinclude/plat/common \
+ -Iinclude/stdlib \
+ -Iinclude/stdlib/sys \
+ ${PLAT_INCLUDES} \
+ ${SPD_INCLUDES}
+
+# Process DEBUG flag
+$(eval $(call assert_boolean,DEBUG))
+$(eval $(call add_define,DEBUG))
+ifeq (${DEBUG},0)
+ $(eval $(call add_define,NDEBUG))
+else
+CFLAGS += -g
+ASFLAGS += -g -Wa,--gdwarf-2
+endif
+
+# Process NS_TIMER_SWITCH flag
+$(eval $(call assert_boolean,NS_TIMER_SWITCH))
+$(eval $(call add_define,NS_TIMER_SWITCH))
+
+# Process RESET_TO_BL31 flag
+$(eval $(call assert_boolean,RESET_TO_BL31))
+$(eval $(call add_define,RESET_TO_BL31))
+
+VPATH_LIST = $(buildsrc)/board/$(BOARDDIR)
+#VPATH_LIST = $(buildsrc)/$(BOARDDIR)
+VPATH_LIST:=$(VPATH_LIST:%=%/firmware/)
+
+vpath %.c $(VPATH_LIST)
+
+ASFLAGS += -nostdinc -ffreestanding -Wa,--fatal-warnings \
+ -mgeneral-regs-only -D__ASSEMBLY__ \
+ ${DEFINES} ${INCLUDES}
+CFLAGS += -nostdinc -pedantic -ffreestanding -Wall \
+ -Werror -mgeneral-regs-only -std=c99 -c -Os \
+ ${DEFINES} ${INCLUDES} $(VPATH_LIST:%=-I%)
+CFLAGS += -ffunction-sections -fdata-sections
+ASFLAGS += ${FIRMWARE_CPPFLAGS}
+CFLAGS += ${FIRMWARE_CPPFLAGS}
+CFLAGS += -Wno-unused
+
+LDFLAGS += --fatal-warnings -O1
+LDFLAGS += --gc-sections
+
+OCFLAGS += -j .dev_header -j .generic_param -j .clk_param \
+ -j .misc_param -j .store_param -j .ddr_param \
+ --gap-fill 0x0
+
+CC := ${CROSS_COMPILE}gcc
+CPP := ${CROSS_COMPILE}cpp
+AS := ${CROSS_COMPILE}gcc
+AR := ${CROSS_COMPILE}ar
+LD := ${CROSS_COMPILE}ld
+OC := ${CROSS_COMPILE}objcopy
+OD := ${CROSS_COMPILE}objdump
+NM := ${CROSS_COMPILE}nm
+PP := ${CROSS_COMPILE}gcc -E ${CFLAGS}
+
+# Variables for use with Firmware Image Package
+FIPTOOLPATH ?= tools/fip_create
+FIPTOOL ?= ${FIPTOOLPATH}/fip_create
+fiptool: ${FIPTOOL}
+fip: ${BUILD_PLAT}/fip.bin
+
+locate-checkpatch:
+ifndef CHECKPATCH
+ $(error "Please set CHECKPATCH to point to the Linux checkpatch.pl file, eg: CHECKPATCH=../linux/script/checkpatch.pl")
+else
+ifeq (,$(wildcard ${CHECKPATCH}))
+ $(error "The file CHECKPATCH points to cannot be found, use eg: CHECKPATCH=../linux/script/checkpatch.pl")
+endif
+endif
+
+clean:
+ @echo " CLEAN"
+ ${Q}rm -rf ${BUILD_PLAT}
+ ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
+
+realclean distclean:
+ @echo " REALCLEAN"
+ ${Q}rm -rf ${BUILD_BASE}
+ ${Q}rm -f ${CURDIR}/cscope.*
+ ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH} clean
+
+checkcodebase: locate-checkpatch
+ @echo " CHECKING STYLE"
+ @if test -d .git ; then \
+ git ls-files | while read GIT_FILE ; do ${CHECKPATCH} ${CHECKCODE_ARGS} -f $$GIT_FILE ; done ; \
+ else \
+ find . -type f -not -iwholename "*.git*" -not -iwholename "*build*" -exec ${CHECKPATCH} ${CHECKCODE_ARGS} -f {} \; ; \
+ fi
+
+checkpatch: locate-checkpatch
+ @echo " CHECKING STYLE"
+ @git format-patch --stdout ${BASE_COMMIT} | ${CHECKPATCH} ${CHECKPATCH_ARGS} - || true
+
+${FIPTOOL}:
+ ${Q}${MAKE} --no-print-directory -C ${FIPTOOLPATH}
+ @echo
+ @echo "Built $@ successfully"
+ @echo
+
+define match_goals
+$(strip $(foreach goal,$(1),$(filter $(goal),$(MAKECMDGOALS))))
+endef
+
+# List of rules that involve building things
+BUILD_TARGETS := all bl1 bl2 bl31 bl32 fip
+
+# Does the list of goals specified on the command line include a build target?
+ifneq ($(call match_goals,${BUILD_TARGETS}),)
+IS_ANYTHING_TO_BUILD := 1
+endif
+
+define MAKE_C
+
+$(eval OBJ := $(1)/$(patsubst %.c,%.o,$(notdir $(2))))
+$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ)))
+
+$(OBJ) : $(2)
+ @echo " CC $$<"
+ $$(Q)$$(CC) $$(CFLAGS) -c $$< -o $$@
+
+
+$(PREREQUISITES) : $(2)
+ @echo " DEPS $$@"
+ @mkdir -p $(1)
+ $$(Q)$$(CC) $$(CFLAGS) -M -MT $(OBJ) -MF $$@ $$<
+
+ifdef IS_ANYTHING_TO_BUILD
+-include $(PREREQUISITES)
+endif
+
+endef
+
+
+define MAKE_S
+
+$(eval OBJ := $(1)/$(patsubst %.S,%.o,$(notdir $(2))))
+$(eval PREREQUISITES := $(patsubst %.o,%.d,$(OBJ)))
+
+$(OBJ) : $(2)
+ @echo " AS $$<"
+ $$(Q)$$(AS) $$(ASFLAGS) -c $$< -o $$@
+
+$(PREREQUISITES) : $(2)
+ @echo " DEPS $$@"
+ @mkdir -p $(1)
+ $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(OBJ) -MF $$@ $$<
+
+ifdef IS_ANYTHING_TO_BUILD
+-include $(PREREQUISITES)
+endif
+
+endef
+
+
+define MAKE_LD
+
+$(eval PREREQUISITES := $(1).d)
+
+$(1) : $(2)
+ @echo " PP $$<"
+ $$(Q)$$(AS) $$(ASFLAGS) -P -E -o $$@ $$<
+
+$(PREREQUISITES) : $(2)
+ @echo " DEPS $$@"
+ @mkdir -p $$(dir $$@)
+ $$(Q)$$(AS) $$(ASFLAGS) -M -MT $(1) -MF $$@ $$<
+
+ifdef IS_ANYTHING_TO_BUILD
+-include $(PREREQUISITES)
+endif
+
+endef
+
+
+define MAKE_OBJS
+ $(eval C_OBJS := $(filter %.c,$(2)))
+ $(eval REMAIN := $(filter-out %.c,$(2)))
+ $(eval $(foreach obj,$(C_OBJS),$(call MAKE_C,$(1),$(obj))))
+
+ $(eval S_OBJS := $(filter %.S,$(REMAIN)))
+ $(eval REMAIN := $(filter-out %.S,$(REMAIN)))
+ $(eval $(foreach obj,$(S_OBJS),$(call MAKE_S,$(1),$(obj))))
+
+ $(and $(REMAIN),$(error Unexpected source files present: $(REMAIN)))
+endef
+
+
+# NOTE: The line continuation '\' is required in the next define otherwise we
+# end up with a line-feed characer at the end of the last c filename.
+# Also bare this issue in mind if extending the list of supported filetypes.
+define SOURCES_TO_OBJS
+ $(notdir $(patsubst %.c,%.o,$(filter %.c,$(1)))) \
+ $(notdir $(patsubst %.S,%.o,$(filter %.S,$(1))))
+endef
+
+define MAKE_BL
+ $(eval BUILD_DIR := ${BUILD_PLAT})
+ $(eval SOURCES := $(SOURCES))
+ $(eval OBJS := $(addprefix $(BUILD_DIR)/,$(call SOURCES_TO_OBJS,$(SOURCES))))
+ $(eval LINKERFILE := $(BUILD_DIR)/acs.ld)
+ $(eval MAPFILE := $(BUILD_DIR)/acs.map)
+ $(eval ELF := $(BUILD_DIR)/acs.elf)
+ $(eval DUMP := $(BUILD_DIR)/acs.dump)
+ $(eval BIN := $(BUILD_DIR)/acs.bin)
+
+ $(eval $(call MAKE_OBJS,$(BUILD_DIR),$(SOURCES)))
+ $(eval $(call MAKE_LD,$(LINKERFILE),$(LINKERFILE_T)))
+
+$(BUILD_DIR) :
+ $$(Q)mkdir -p "$$@"
+
+$(ELF) : $(OBJS) $(LINKERFILE)
+ @echo " LD $$@"
+ @echo 'const char build_message[] = "Built : "__TIME__", "__DATE__". \\nver:${GIT_VERSION} - ${BUILDER}";' | \
+ $$(CC) $$(CFLAGS) -xc - -o $(BUILD_DIR)/build_message.o
+ $$(Q)$$(LD) -o $$@ $$(LDFLAGS) -Map=$(MAPFILE) --script $(LINKERFILE) \
+ $(BUILD_DIR)/build_message.o $(OBJS)
+
+$(DUMP) : $(ELF)
+ @echo " OD $$@"
+ $${Q}$${OD} -D -x $$< > $$@
+
+$(BIN) : $(ELF)
+ @echo " BIN $$@"
+ $$(Q)$$(OC) $$(OCFLAGS) -O binary $$< $$@.tmp
+ @dd if=/dev/zero of=$$@ bs=4096 count=7
+ @dd if=$$@.tmp of=$$@ conv=notrunc && rm -f $$@.tmp
+ @echo
+ @echo "Built $$@ successfully"
+ @echo
+
+.PHONY : bl$(1)
+bl$(1) : $(BUILD_DIR) $(DUMP) $(BIN)
+
+all : bl$(1)
+
+$(eval FIP_DEPS += $(if $2,$(BIN),))
+$(eval FIP_ARGS += $(if $2,--bl$(1) $(BIN),))
+
+endef
+
+ifeq (${NEED_BL2},yes)
+$(eval $(call MAKE_BL,2,in_fip))
+endif
+
+${BUILD_PLAT}/fip.bin: ${FIP_DEPS} ${BL33} ${FIPTOOL}
+ $(if ${BL33},,$(error "To build a FIP, please set BL33 to point to the Normal World binary, eg: BL33=../uefi/FVP_AARCH64_EFI.fd"))
+ ${Q}${FIPTOOL} --dump \
+ ${FIP_ARGS} \
+ --bl33 ${BL33} \
+ $@
+ @echo
+ @echo "Built $@ successfully"
+ @echo
+
+
+cscope:
+ @echo " CSCOPE"
+ ${Q}find ${CURDIR} -name "*.[chsS]" > cscope.files
+ ${Q}cscope -b -q -k
+
+help:
+ @echo "usage: ${MAKE} PLAT=<${HELP_PLATFORMS}> <all|bl1|bl2|bl31|distclean|clean|checkcodebase|checkpatch>"
+ @echo ""
+ @echo "PLAT is used to specify which platform you wish to build."
+ @echo "If no platform is specified, PLAT defaults to: ${DEFAULT_PLAT}"
+ @echo ""
+ @echo "Supported Targets:"
+ @echo " all Build the BL1, BL2 and BL31 binaries"
+ @echo " bl1 Build the BL1 binary"
+ @echo " bl2 Build the BL2 binary"
+ @echo " bl31 Build the BL31 binary"
+ @echo " checkcodebase Check the coding style of the entire source tree"
+ @echo " checkpatch Check the coding style on changes in the current"
+ @echo " branch against BASE_COMMIT (default origin/master)"
+ @echo " clean Clean the build for the selected platform"
+ @echo " cscope Generate cscope index"
+ @echo " distclean Remove all build artifacts for all platforms"
+ @echo " fiptool Build the Firmware Image Package(FIP) creation tool"
+ @echo ""
+ @echo "note: most build targets require PLAT to be set to a specific platform."
+ @echo ""
+ @echo "example: build all targets for the FVP platform:"
+ @echo " CROSS_COMPILE=aarch64-none-elf- make PLAT=fvp all"
diff --git a/arch/arm/mach-meson/t7/firmware/acs/acs.c b/arch/arm/mach-meson/t7/firmware/acs/acs.c
new file mode 100644
index 0000000..f6f58e1
--- /dev/null
+++ b/arch/arm/mach-meson/t7/firmware/acs/acs.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <version.h>
+#include <asm/arch/acs.h>
+#include <asm/arch/timing.h>
+#include "timing.c"
+
+dev_param_hdr_t __param_hdr __attribute__ ((section(".dev_header"))) = {
+ .magic = DEV_PARAM_MAGIC,
+ .version = DEV_PARAM_VERSION,
+
+ .bl2_regs_magic = "bl2r_",
+ .bl2_regs_length = sizeof(__bl2_reg),
+
+ .board_clk_magic = "bclk_",
+ .board_clk_length = sizeof(__board_clk_setting),
+
+ .opt_reg_magic = "ops__",
+ .opt_reg_length = sizeof(__bl2_ops_reg),
+
+ .sto_set_magic = "store",
+ .sto_set_length = sizeof(__store_para),
+
+ .ddr_set_magic = "ddrs_",
+ .ddr_set_length = sizeof(__ddr_setting),
+};
+
diff --git a/arch/arm/mach-meson/t7/firmware/acs/acs.ld.S b/arch/arm/mach-meson/t7/firmware/acs/acs.ld.S
new file mode 100644
index 0000000..3f84ef3
--- /dev/null
+++ b/arch/arm/mach-meson/t7/firmware/acs/acs.ld.S
@@ -0,0 +1,55 @@
+
+OUTPUT_FORMAT("elf64-littleaarch64")
+OUTPUT_ARCH(aarch64)
+ENTRY(acs_entry)
+
+SECTIONS
+{
+ . = 0x00007000;
+ . = ALIGN(4);
+ .entry : {
+ __RO_START__ = .;
+ *acs_entry.o(.text*)
+ *(.text*)
+ *(.data*)
+ *(.bss*)
+ }
+
+ . = 0x00000000;
+ .dev_header :
+ {
+ *(.dev_header*)
+ }
+
+ . = 0x00000200;
+ .generic_param :
+ {
+ *(.generic_param*)
+ }
+
+ . = 0x00005800;
+ .clk_param :
+ {
+ *(.clk_param*)
+ }
+
+ . = 0x00005c00;
+ .misc_param :
+ {
+ *(.misc_param*)
+ }
+
+ . = 0x00005e00;
+ .store_param :
+ {
+ *(.store_param*)
+ }
+
+ . = 0x00006000;
+ .ddr_param :
+ {
+ *(.ddr_param*)
+ }
+
+ ASSERT(. <= 0x00007000, "params image has exceeded its limit.")
+}
diff --git a/arch/arm/mach-meson/t7/firmware/acs/acs.mk b/arch/arm/mach-meson/t7/firmware/acs/acs.mk
new file mode 100644
index 0000000..0c63194
--- /dev/null
+++ b/arch/arm/mach-meson/t7/firmware/acs/acs.mk
@@ -0,0 +1,9 @@
+SOURCES += acs_entry.S
+
+ifdef CONFIG_MDUMP_COMPRESS
+SOURCES += ramdump.c
+endif
+
+SOURCES += acs.c
+
+LINKERFILE_T := acs.ld.S
diff --git a/arch/arm/mach-meson/t7/firmware/acs/acs_entry.S b/arch/arm/mach-meson/t7/firmware/acs/acs_entry.S
new file mode 100644
index 0000000..e6ec19b
--- /dev/null
+++ b/arch/arm/mach-meson/t7/firmware/acs/acs_entry.S
@@ -0,0 +1,14 @@
+
+ .globl acs_entry
+
+acs_entry:
+ .word __param_hdr
+ .word __bl2_reg
+ .word __board_clk_setting
+ .word __bl2_ops_reg
+ .word __store_para
+ .word __ddr_setting
+ .rept 10
+ .word 0x0
+ .endr
+
diff --git a/arch/arm/mach-meson/t7/firmware/bl21/Makefile b/arch/arm/mach-meson/t7/firmware/bl21/Makefile
new file mode 100644
index 0000000..b6d7d1a
--- /dev/null
+++ b/arch/arm/mach-meson/t7/firmware/bl21/Makefile
@@ -0,0 +1,3 @@
+all:
+ @echo "BL21 no action for A1 "
+
diff --git a/arch/arm/mach-meson/t7/firmware/scp_task/Makefile b/arch/arm/mach-meson/t7/firmware/scp_task/Makefile
new file mode 100644
index 0000000..925690d
--- /dev/null
+++ b/arch/arm/mach-meson/t7/firmware/scp_task/Makefile
@@ -0,0 +1,3 @@
+all:
+ echo "BL301 no action for A1"
+
diff --git a/arch/arm/mach-meson/t7/gate_init.c b/arch/arm/mach-meson/t7/gate_init.c
new file mode 100644
index 0000000..31629f6
--- /dev/null
+++ b/arch/arm/mach-meson/t7/gate_init.c
@@ -0,0 +1,366 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "power_gate.h"
+
+#define SECUREBOOT_FLAG_ADDR 0xc8100228
+
+#ifdef CONFIG_AML_CVBS
+extern unsigned int cvbs_mode;
+#endif
+void ee_gate_off(void)
+{
+ printf("ee_gate_off ...\n");
+ return;
+/* int secureboot = readl(SECUREBOOT_FLAG_ADDR)&(1<<5);*/
+
+#ifdef CONFIG_AML_CVBS
+ unsigned int cvbs_opened = 0;
+#endif
+
+#ifdef CONFIG_AML_CVBS
+ if ((cvbs_mode == 0) || (cvbs_mode == 1))
+ cvbs_opened = 1;
+#endif
+
+ /*
+ //if close , audio maybe have noise
+ CLK_GATE_OFF(AUD);
+ CLK_GATE_OFF(AUD2);
+ CLK_GATE_OFF(AUD_CLK_2);
+ CLK_GATE_OFF(AUD_CLK_3);
+ */
+ CLK_GATE_OFF(AUD_IN);
+ CLK_GATE_OFF(AIU_AUD_MIXER);
+ CLK_GATE_OFF(SANA);
+
+ /*kernel will reopen */
+ CLK_GATE_OFF(CTS_ENCL);
+ /* CLK_GATE_OFF(CTS_ENCT); */
+#if 0 /* HDMITX 480i60hz/576i50hz need this gate */
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0)
+ CLK_GATE_OFF(CTS_ENCI);
+#else
+ CLK_GATE_OFF(CTS_ENCI);
+#endif
+#endif
+ /* CLK_GATE_OFF(CTS_ENCP); */
+
+ /*close cvbs clock*/
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0) {
+ CLK_GATE_OFF(DAC_CLK);
+ CLK_GATE_OFF(CTS_VDAC);
+ }
+#else
+ CLK_GATE_OFF(DAC_CLK);
+ CLK_GATE_OFF(CTS_VDAC);
+#endif
+
+ /* usb clock close */
+ CLK_GATE_OFF(USB0);
+ CLK_GATE_OFF(USB1);
+ //CLK_GATE_OFF(USB_CLK); //g12a no reg
+ CLK_GATE_OFF(MISC_USB0_TO_DDR);
+ CLK_GATE_OFF(MISC_USB1_TO_DDR);
+
+ /* uarts close */
+ CLK_GATE_OFF(UART0);
+ CLK_GATE_OFF(UART1);
+ CLK_GATE_OFF(UART2);
+ CLK_GATE_OFF(UART3);
+
+ CLK_GATE_OFF(VCLK2_VENCP);
+ CLK_GATE_OFF(VCLK2_VENCT);
+ CLK_GATE_OFF(VCLK2_VENCT1);
+ CLK_GATE_OFF(VCLK2_OTHER);
+#if 0 /* HDMITX 480i60hz/576i50hz need HHI_GCLK_OTHER[8][2] */
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0) {
+ CLK_GATE_OFF(VCLK2_VENCI);
+ CLK_GATE_OFF(VCLK2_VENCI1);
+ }
+#else
+ CLK_GATE_OFF(VCLK2_VENCI);
+ CLK_GATE_OFF(VCLK2_VENCI1);
+#endif
+#endif
+ CLK_GATE_OFF(VCLK2_VENCL);
+ CLK_GATE_OFF(VCLK2_OTHER1);
+#if 0 /* HDMITX 480i60hz/576i50hz need HHI_GCLK_OTHER[8][2] */
+#ifdef CONFIG_AML_CVBS
+ if (cvbs_opened == 0)
+ CLK_GATE_OFF(VCLK2_ENCI);
+#else
+ CLK_GATE_OFF(VCLK2_ENCI);
+#endif
+#endif
+ CLK_GATE_OFF(VCLK2_ENCL);
+ CLK_GATE_OFF(VCLK2_ENCT);
+
+ CLK_GATE_OFF(VDEC_CLK_1);
+ CLK_GATE_OFF(VDEC_CLK_2);
+ CLK_GATE_OFF(VDEC2_CLK_1);
+ CLK_GATE_OFF(VDEC2_CLK_2);
+ CLK_GATE_OFF(HCODEC_CLK_1);
+ CLK_GATE_OFF(HCODEC_CLK_2);
+ /* CLK_GATE_OFF(HEVC_CLK_1 ); */
+ /* CLK_GATE_OFF(HEVC_CLK_2 ); */
+
+ //CLK_GATE_OFF(MMC_A_PCLK); //g12a no reg
+ //CLK_GATE_OFF(MMC_B_PCLK); //g12a no reg
+ //CLK_GATE_OFF(MMC_C_PCLK); //g12a no reg
+
+ CLK_GATE_OFF(LCD_AN_PHY2);
+ CLK_GATE_OFF(LCD_AN_PHY3);
+
+ CLK_GATE_OFF(ETHERNET);
+ //CLK_GATE_OFF(ETH_CLK); //g12a no reg
+
+ CLK_GATE_OFF(GE2D);
+ CLK_GATE_OFF(GEN_CLK);
+ //CLK_GATE_OFF(PCM_MCLK); //g12a no reg
+ //CLK_GATE_OFF(PCM_SCLK); //g12a no reg
+
+
+ CLK_GATE_OFF(HIU_PARSER_TOP);
+
+
+ /* can not off nand_clk */
+ /* CLK_GATE_OFF(NAND_CLK); */
+ /*
+ //HDMI no output
+ CLK_GATE_OFF(VCLK2_VENCP1);
+ CLK_GATE_OFF(VCLK2_ENCP);
+ */
+
+ /*
+ //if OFF, HDMI will report error!
+ CLK_GATE_OFF(HDMI_PCLK);
+ CLK_GATE_OFF(HDMI_PLL_CNTL);
+ CLK_GATE_OFF(HDMITX_CLK);
+ */
+
+ /*
+ //PWM B used for VCCK,PWM D used for VDDEE,ignoring
+ CLK_GATE_OFF(PWM_A_CLK);
+ CLK_GATE_OFF(PWM_B_CLK);
+ CLK_GATE_OFF(PWM_C_CLK);
+ CLK_GATE_OFF(PWM_D_CLK);
+ CLK_GATE_OFF(PWM_E_CLK);
+ CLK_GATE_OFF(PWM_F_CLK);
+ */
+
+
+ /* can not close
+ CLK_GATE_OFF(VPU_CLK_1);
+ CLK_GATE_OFF(VPU_CLK_2);
+ CLK_GATE_OFF(VPU_CLKB);
+ CLK_GATE_OFF(MALI_CLK_1);
+ CLK_GATE_OFF(MALI_CLK_2);
+ CLK_GATE_OFF(ATV_DEMO_VDAC);
+ CLK_GATE_OFF(EMMC_A);
+ CLK_GATE_OFF(EMMC_B);
+ CLK_GATE_OFF(EMMC_C);
+ CLK_GATE_OFF(EMMC_A_CLK);
+ CLK_GATE_OFF(EMMC_B_CLK);
+
+ CLK_GATE_OFF(MSR_CLK);
+ CLK_GATE_OFF(MSR_HS_CLK);
+ CLK_GATE_OFF(32K_CLK);
+ CLK_GATE_OFF(VAPB_CLK_1);
+ CLK_GATE_OFF(VAPB_CLK_2);
+ CLK_GATE_OFF(GIC);
+ CLK_GATE_OFF(I2C_AO); //no close for to use
+ CLK_GATE_OFF(AO_CPU);
+ CLK_GATE_OFF(ASSIST_MISC);
+ CLK_GATE_OFF(HIU_PARSER);
+ CLK_GATE_OFF(PERIPHS_TOP);
+ CLK_GATE_OFF(PL310_CBUS);
+ CLK_GATE_OFF(ISA);
+ CLK_GATE_OFF(SECURE_AHP_APB3);
+ CLK_GATE_OFF(VPU_INTR);
+ CLK_GATE_OFF(MMC_PCLK); //can not close
+ CLK_GATE_OFF(AIU_PCLK);
+ //can not connect pc
+ CLK_GATE_OFF(USB_GENERAL);
+ CLK_GATE_OFF(AHB_DATA_BUS);
+ CLK_GATE_OFF(AHB_CONTROL_BUS);
+ CLK_GATE_OFF(HDMI_INTR_SYNC); //should open
+ //can't suspend @ 2nd time
+ //CLK_GATE_OFF(RESET);
+
+ // close rom
+ //disable this bit will make other cpu can not be booted.
+ //CLK_GATE_OFF(ROM_CLK);
+
+*/
+ /*************************/
+ CLK_GATE_OFF(AHB_ARB0);
+ CLK_GATE_OFF(ASYNC_FIFO);
+ CLK_GATE_OFF(STREAM);
+ CLK_GATE_OFF(RANDOM_NUM_GEN);
+ CLK_GATE_OFF(RANDOM_NUM_GEN1);
+ CLK_GATE_OFF(SMART_CARD_MPEG_DOMAIN);
+ CLK_GATE_OFF(I2C);
+ CLK_GATE_OFF(SPI);
+ CLK_GATE_OFF(SPICC);
+ CLK_GATE_OFF(DOS);
+ CLK_GATE_OFF(SAR_ADC);
+ CLK_GATE_OFF(MISC_DVIN);
+ CLK_GATE_OFF(BT656);
+ CLK_GATE_OFF(BT656_2);
+ CLK_GATE_OFF(PDM);
+
+ /* close AIU */
+ CLK_GATE_OFF(AIU_IEC958);
+ CLK_GATE_OFF(AIU_ICE958_AMCLK);
+
+ CLK_GATE_OFF(AIU_AMCLK_MEASURE);
+ CLK_GATE_OFF(AIU_AIFIFO2);
+ CLK_GATE_OFF(AIU_MIXER_REG);
+ CLK_GATE_OFF(AIU_ADC);
+ CLK_GATE_OFF(AIU_TOP_LEVEL);
+ CLK_GATE_OFF(AIU_AOCLK);
+ CLK_GATE_OFF(AIU_AI_TOP_GLUE);
+ CLK_GATE_OFF(AIU_I2S_OUT);
+
+ CLK_GATE_OFF(ENC480P);
+
+ CLK_GATE_OFF(DEMUX);
+/*
+* EFUSE/BLK_MOV clock gate must be on,
+ kernel storage ops depend on them.
+ it can be reference PD#112732
+*/
+/*
+ if (secureboot) {
+ printf("secure boot ignore [ BLK_MOV, efuse ] clk gate\n");
+ } else {
+ CLK_GATE_OFF(EFUSE);
+ CLK_GATE_OFF(BLK_MOV);
+ }
+*/
+}
+
+void ee_gate_on(void)
+{
+
+ printf("ee_gate_on ...\n");
+
+ /*
+ //if close , audio maybe have noise
+ CLK_GATE_ON(AUD);
+ CLK_GATE_ON(AUD2);
+ CLK_GATE_ON(AUD_CLK_2);
+ CLK_GATE_ON(AUD_CLK_3);
+ */
+ CLK_GATE_ON(AUD_IN);
+ CLK_GATE_ON(AIU_AUD_MIXER);
+ CLK_GATE_ON(SANA);
+
+ /*kernel will reopen */
+ CLK_GATE_ON(CTS_ENCL);
+ /* CLK_GATE_ON(CTS_ENCT); */
+ CLK_GATE_ON(CTS_ENCI);
+ /* CLK_GATE_ON(CTS_ENCP); */
+
+ /*close cvbs clock*/
+ CLK_GATE_ON(DAC_CLK);
+ CLK_GATE_ON(CTS_VDAC);
+
+ /* usb clock close */
+ CLK_GATE_ON(USB0);
+ CLK_GATE_ON(USB1);
+ //CLK_GATE_ON(USB_CLK); //g12a no reg
+ CLK_GATE_ON(MISC_USB0_TO_DDR);
+ CLK_GATE_ON(MISC_USB1_TO_DDR);
+
+ /* uarts close */
+ CLK_GATE_ON(UART0);
+ CLK_GATE_ON(UART1);
+ CLK_GATE_ON(UART2);
+ CLK_GATE_ON(UART3);
+
+ CLK_GATE_ON(VCLK2_VENCP);
+ CLK_GATE_ON(VCLK2_VENCT);
+ CLK_GATE_ON(VCLK2_VENCT1);
+ CLK_GATE_ON(VCLK2_OTHER);
+ CLK_GATE_ON(VCLK2_VENCI);
+ CLK_GATE_ON(VCLK2_VENCI1);
+ CLK_GATE_ON(VCLK2_VENCL);
+ CLK_GATE_ON(VCLK2_OTHER1);
+
+
+ CLK_GATE_ON(VCLK2_ENCI);
+ CLK_GATE_ON(VCLK2_ENCL);
+ CLK_GATE_ON(VCLK2_ENCT);
+
+ CLK_GATE_ON(VDEC_CLK_1);
+ CLK_GATE_ON(VDEC_CLK_2);
+ CLK_GATE_ON(VDEC2_CLK_1);
+ CLK_GATE_ON(VDEC2_CLK_2);
+ CLK_GATE_ON(HCODEC_CLK_1);
+ CLK_GATE_ON(HCODEC_CLK_2);
+ /* CLK_GATE_ON(HEVC_CLK_1 ); */
+ /* CLK_GATE_ON(HEVC_CLK_2 ); */
+
+ //CLK_GATE_ON(MMC_A_PCLK); //g12a no reg
+ //CLK_GATE_ON(MMC_B_PCLK); //g12a no reg
+ //CLK_GATE_ON(MMC_C_PCLK); //g12a no reg
+
+ CLK_GATE_ON(LCD_AN_PHY2);
+ CLK_GATE_ON(LCD_AN_PHY3);
+
+ CLK_GATE_ON(ETHERNET);
+ //CLK_GATE_ON(ETH_CLK); //g12a no reg
+
+ CLK_GATE_ON(GE2D);
+ CLK_GATE_ON(GEN_CLK);
+ //CLK_GATE_ON(PCM_MCLK); //g12a no reg
+ //CLK_GATE_ON(PCM_SCLK); //g12a no reg
+
+
+ CLK_GATE_ON(HIU_PARSER_TOP);
+
+ /*************************/
+ CLK_GATE_ON(AHB_ARB0);
+ CLK_GATE_ON(ASYNC_FIFO);
+ CLK_GATE_ON(STREAM);
+ CLK_GATE_ON(RANDOM_NUM_GEN);
+ CLK_GATE_ON(RANDOM_NUM_GEN1);
+ CLK_GATE_ON(SMART_CARD_MPEG_DOMAIN);
+ CLK_GATE_ON(I2C);
+ CLK_GATE_ON(SPI);
+ CLK_GATE_ON(SPICC);
+ CLK_GATE_ON(DOS);
+ CLK_GATE_ON(SAR_ADC);
+ CLK_GATE_ON(MISC_DVIN);
+ CLK_GATE_ON(BT656);
+ CLK_GATE_ON(BT656_2);
+ CLK_GATE_ON(PDM);
+
+ /* close AIU */
+ CLK_GATE_ON(AIU_IEC958);
+ CLK_GATE_ON(AIU_ICE958_AMCLK);
+
+ CLK_GATE_ON(AIU_AMCLK_MEASURE);
+ CLK_GATE_ON(AIU_AIFIFO2);
+ CLK_GATE_ON(AIU_MIXER_REG);
+ CLK_GATE_ON(AIU_ADC);
+ CLK_GATE_ON(AIU_TOP_LEVEL);
+ CLK_GATE_ON(AIU_AOCLK);
+ CLK_GATE_ON(AIU_AI_TOP_GLUE);
+ CLK_GATE_ON(AIU_I2S_OUT);
+
+ CLK_GATE_ON(ENC480P);
+
+ CLK_GATE_ON(DEMUX);
+
+ CLK_GATE_ON(EFUSE);
+ CLK_GATE_ON(BLK_MOV);
+}
+
diff --git a/arch/arm/mach-meson/t7/gpio.c b/arch/arm/mach-meson/t7/gpio.c
new file mode 100644
index 0000000..7332773
--- /dev/null
+++ b/arch/arm/mach-meson/t7/gpio.c
@@ -0,0 +1,223 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <linux/compiler.h>
+#include <amlogic/aml_gpio.h>
+#include <asm/arch/gpio.h>
+
+struct pin_mux_desc {
+ unsigned char domain;
+ unsigned char reg;
+ unsigned char bit;
+};
+
+#define MUX_AO_DOMAIN 0
+#define MUX_EE_DOMAIN 1
+
+#define PIN_MUX(d, r, b) \
+{ \
+ .domain = d, \
+ .reg = r, \
+ .bit = b, \
+}
+
+#define BANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
+{ \
+ .name = n, \
+ .first = f, \
+ .last = l, \
+ .regs = { \
+ [REG_PULLEN] = { (0xff634520 + (per<<2)), peb }, \
+ [REG_PULL] = { (0xff6344e8 + (pr<<2)), pb }, \
+ [REG_DIR] = { (0xff634440 + (dr<<2)), db }, \
+ [REG_OUT] = { (0xff634440 + (or<<2)), ob }, \
+ [REG_IN] = { (0xff634440 + (ir<<2)), ib }, \
+ }, \
+ }
+#define AOBANK(n, f, l, per, peb, pr, pb, dr, db, or, ob, ir, ib) \
+{ \
+ .name = n, \
+ .first = f, \
+ .last = l, \
+ .regs = { \
+ [REG_PULLEN] = { (0xff800024 + (per<<2)), peb }, \
+ [REG_PULL] = { (0xff800024 + (pr<<2)), pb }, \
+ [REG_DIR] = { (0xff800024 + (dr<<2)), db }, \
+ [REG_OUT] = { (0xff800024 + (or<<2)), ob }, \
+ [REG_IN] = { (0xff800024 + (ir<<2)), ib }, \
+ }, \
+ }
+
+static struct pin_mux_desc pin_to_gpio[] = {
+ [GPIOAO(GPIOAO_0)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 0),
+ [GPIOAO(GPIOAO_1)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 4),
+ [GPIOAO(GPIOAO_2)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 8),
+ [GPIOAO(GPIOAO_3)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 12),
+ [GPIOAO(GPIOAO_4)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 16),
+ [GPIOAO(GPIOAO_5)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 20),
+ [GPIOAO(GPIOAO_6)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 24),
+ [GPIOAO(GPIOAO_7)] = PIN_MUX(MUX_AO_DOMAIN, 0x0, 28),
+ [GPIOAO(GPIOAO_8)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 0),
+ [GPIOAO(GPIOAO_9)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 4),
+ [GPIOAO(GPIOAO_10)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 8),
+ [GPIOAO(GPIOAO_11)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 12),
+ [GPIOAO(GPIOE_0)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 16),
+ [GPIOAO(GPIOE_1)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 20),
+ [GPIOAO(GPIOE_2)] = PIN_MUX(MUX_AO_DOMAIN, 0x1, 24),
+ [GPIOEE(GPIOZ_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 0),
+ [GPIOEE(GPIOZ_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 4),
+ [GPIOEE(GPIOZ_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 8),
+ [GPIOEE(GPIOZ_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 12),
+ [GPIOEE(GPIOZ_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 16),
+ [GPIOEE(GPIOZ_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 20),
+ [GPIOEE(GPIOZ_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 24),
+ [GPIOEE(GPIOZ_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x6, 28),
+ [GPIOEE(GPIOZ_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 0),
+ [GPIOEE(GPIOZ_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 4),
+ [GPIOEE(GPIOZ_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 8),
+ [GPIOEE(GPIOZ_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 12),
+ [GPIOEE(GPIOZ_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 16),
+ [GPIOEE(GPIOZ_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 20),
+ [GPIOEE(GPIOZ_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 24),
+ [GPIOEE(GPIOZ_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x7, 28),
+ [GPIOEE(GPIOH_0)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 0),
+ [GPIOEE(GPIOH_1)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 4),
+ [GPIOEE(GPIOH_2)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 8),
+ [GPIOEE(GPIOH_3)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 12),
+ [GPIOEE(GPIOH_4)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 16),
+ [GPIOEE(GPIOH_5)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 20),
+ [GPIOEE(GPIOH_6)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 24),
+ [GPIOEE(GPIOH_7)] = PIN_MUX(MUX_EE_DOMAIN, 0xb, 28),
+ [GPIOEE(GPIOH_8)] = PIN_MUX(MUX_EE_DOMAIN, 0xc, 0),
+ [GPIOEE(BOOT_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 0),
+ [GPIOEE(BOOT_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 4),
+ [GPIOEE(BOOT_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 8),
+ [GPIOEE(BOOT_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 12),
+ [GPIOEE(BOOT_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 16),
+ [GPIOEE(BOOT_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 20),
+ [GPIOEE(BOOT_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 24),
+ [GPIOEE(BOOT_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x0, 28),
+ [GPIOEE(BOOT_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 0),
+ [GPIOEE(BOOT_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 4),
+ [GPIOEE(BOOT_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 8),
+ [GPIOEE(BOOT_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 12),
+ [GPIOEE(BOOT_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 16),
+ [GPIOEE(BOOT_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 20),
+ [GPIOEE(BOOT_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 24),
+ [GPIOEE(BOOT_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x1, 28),
+ [GPIOEE(GPIOC_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 0),
+ [GPIOEE(GPIOC_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 4),
+ [GPIOEE(GPIOC_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 8),
+ [GPIOEE(GPIOC_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 12),
+ [GPIOEE(GPIOC_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 16),
+ [GPIOEE(GPIOC_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 20),
+ [GPIOEE(GPIOC_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 24),
+ [GPIOEE(GPIOC_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x9, 28),
+ [GPIOEE(GPIOA_0)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 0),
+ [GPIOEE(GPIOA_1)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 4),
+ [GPIOEE(GPIOA_2)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 8),
+ [GPIOEE(GPIOA_3)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 12),
+ [GPIOEE(GPIOA_4)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 16),
+ [GPIOEE(GPIOA_5)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 20),
+ [GPIOEE(GPIOA_6)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 24),
+ [GPIOEE(GPIOA_7)] = PIN_MUX(MUX_EE_DOMAIN, 0xd, 28),
+ [GPIOEE(GPIOA_8)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 0),
+ [GPIOEE(GPIOA_9)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 4),
+ [GPIOEE(GPIOA_10)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 8),
+ [GPIOEE(GPIOA_11)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 12),
+ [GPIOEE(GPIOA_12)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 16),
+ [GPIOEE(GPIOA_13)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 20),
+ [GPIOEE(GPIOA_14)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 24),
+ [GPIOEE(GPIOA_15)] = PIN_MUX(MUX_EE_DOMAIN, 0xe, 28),
+ [GPIOEE(GPIOX_0)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 0),
+ [GPIOEE(GPIOX_1)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 4),
+ [GPIOEE(GPIOX_2)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 8),
+ [GPIOEE(GPIOX_3)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 12),
+ [GPIOEE(GPIOX_4)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 16),
+ [GPIOEE(GPIOX_5)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 20),
+ [GPIOEE(GPIOX_6)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 24),
+ [GPIOEE(GPIOX_7)] = PIN_MUX(MUX_EE_DOMAIN, 0x3, 28),
+ [GPIOEE(GPIOX_8)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 0),
+ [GPIOEE(GPIOX_9)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 4),
+ [GPIOEE(GPIOX_10)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 8),
+ [GPIOEE(GPIOX_11)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 12),
+ [GPIOEE(GPIOX_12)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 16),
+ [GPIOEE(GPIOX_13)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 20),
+ [GPIOEE(GPIOX_14)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 24),
+ [GPIOEE(GPIOX_15)] = PIN_MUX(MUX_EE_DOMAIN, 0x4, 28),
+ [GPIOEE(GPIOX_16)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 0),
+ [GPIOEE(GPIOX_17)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 4),
+ [GPIOEE(GPIOX_18)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 8),
+ [GPIOEE(GPIOX_19)] = PIN_MUX(MUX_EE_DOMAIN, 0x5, 12),
+};
+/*sequence of banks keep same as arch-g12a/gpio.h*/
+static struct meson_bank mesontxhd_banks[] = {
+ /*name first last pullen pull dir out in*/
+ AOBANK("GPIOAO_", GPIOAO(GPIOAO_0), GPIOAO(GPIOAO_11),
+ 3, 0, 2, 0, 0, 0, 4, 0, 1, 0),
+ AOBANK("GPIOE_", GPIOAO(GPIOE_0), GPIOAO(GPIOE_2),
+ 3, 16, 2, 16, 0, 16, 4, 16, 1, 16),
+ BANK("GPIOZ_", GPIOEE(GPIOZ_0), GPIOEE(GPIOZ_15),
+ 4, 0, 4, 0, 12, 0, 13, 0, 14, 0),
+ BANK("GPIOH_", GPIOEE(GPIOH_0), GPIOEE(GPIOH_8),
+ 3, 0, 3, 0, 9, 0, 10, 0, 11, 0),
+ BANK("BOOT_", GPIOEE(BOOT_0), GPIOEE(BOOT_15),
+ 0, 0, 0, 0, 0, 0, 1, 0, 2, 0),
+ BANK("GPIOC_", GPIOEE(GPIOC_0), GPIOEE(GPIOC_7),
+ 1, 0, 1, 0, 3, 0, 4, 0, 5, 0),
+ BANK("GPIOA_", GPIOEE(GPIOA_0), GPIOEE(GPIOA_15),
+ 5, 0, 5, 0, 16, 0, 17, 0, 18, 0),
+ BANK("GPIOX_", GPIOEE(GPIOX_0), GPIOEE(GPIOX_19),
+ 2, 0, 2, 0, 6, 0, 7, 0, 8, 0),
+};
+
+U_BOOT_DEVICES(txhd_gpios) = {
+ { "gpio_aml", &mesontxhd_banks[0] },
+ { "gpio_aml", &mesontxhd_banks[1] },
+ { "gpio_aml", &mesontxhd_banks[2] },
+ { "gpio_aml", &mesontxhd_banks[3] },
+ { "gpio_aml", &mesontxhd_banks[4] },
+ { "gpio_aml", &mesontxhd_banks[5] },
+ { "gpio_aml", &mesontxhd_banks[6] },
+ { "gpio_aml", &mesontxhd_banks[7] },
+};
+
+static unsigned long domain[]={
+ [MUX_AO_DOMAIN] = 0xff800014,
+ [MUX_EE_DOMAIN] = 0xff6346c0,
+};
+
+int clear_pinmux(unsigned int pin)
+{
+ struct pin_mux_desc *pmux_desc = &pin_to_gpio[pin];
+
+ regmap_update_bits(domain[pmux_desc->domain] + (pmux_desc->reg << 2),
+ 0xf << (pmux_desc->bit), 0 << (pmux_desc->bit));
+
+ return 0;
+}
+
+#ifdef CONFIG_AML_SPICC
+#include <asm/arch/secure_apb.h>
+/* generic pins control for spicc1.
+ * if deleted, you have to add it into all g12a board files as necessary.
+ * GPIOH_4: MOSI:regB[19:16]=3
+ * GPIOH_5: MISO:regB[23:20]=3
+ * GPIOH_7: CLK:regB[31:28]=3
+ */
+int spicc1_pinctrl_enable(bool enable)
+{
+ unsigned int val;
+
+ val = readl(P_PERIPHS_PIN_MUX_B);
+ val &= ~(0xf0ff << 16);
+ if (enable)
+ val |= 0x3033 << 16;
+ writel(val, P_PERIPHS_PIN_MUX_B);
+ return 0;
+}
+#endif /* CONFIG_AML_SPICC */
diff --git a/arch/arm/mach-meson/t7/hdmitx_clk.c b/arch/arm/mach-meson/t7/hdmitx_clk.c
new file mode 100644
index 0000000..2a797c8
--- /dev/null
+++ b/arch/arm/mach-meson/t7/hdmitx_clk.c
@@ -0,0 +1,862 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <amlogic/media/vout/hdmitx/hdmitx.h>
+#include "hdmitx_clk.h"
+
+static uint32_t frac_rate;
+
+#define msleep(i) udelay(i*1000)
+
+#define check_clk_config(para)\
+ if (para == -1)\
+ return;
+
+#define check_div() \
+ if (div == -1)\
+ return ;\
+ switch (div) {\
+ case 1:\
+ div = 0; break;\
+ case 2:\
+ div = 1; break;\
+ case 4:\
+ div = 2; break;\
+ case 6:\
+ div = 3; break;\
+ case 12:\
+ div = 4; break;\
+ default:\
+ break;\
+ }
+
+#define WAIT_FOR_PLL_LOCKED(_reg) \
+ do { \
+ unsigned int st = 0; \
+ int cnt = 10; \
+ unsigned int reg = _reg; \
+ while (cnt--) { \
+ msleep(5); \
+ st = (((hd_read_reg(reg) >> 30) & 0x3) == 3); \
+ if (st) \
+ break; \
+ else { \
+ /* reset hpll */ \
+ hd_set_reg_bits(reg, 1, 29, 1); \
+ hd_set_reg_bits(reg, 0, 29, 1); \
+ } \
+ } \
+ if (cnt < 9) \
+ printf("pll[0x%x] reset %d times\n", reg, 9 - cnt);\
+ } while (0)
+
+static void set_hdmitx_sys_clk(void)
+{
+ hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, 0, 9, 3);
+ hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, 0, 0, 7);
+ hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, 1, 8, 1);
+}
+
+/*
+ * When VCO outputs 6.0 GHz, if VCO unlock with default v1
+ * steps, then need reset with v2 or v3
+ */
+static bool set_hpll_hclk_v1(unsigned int m, unsigned int frac_val)
+{
+ int ret = 0;
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
+
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x0b3a0400 | (m & 0xff));
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x3, 28, 2);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, frac_val);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+
+ if (frac_val == 0x8148) {
+ if (((hdev->para->vic == HDMI_3840x2160p50_16x9) ||
+ (hdev->para->vic == HDMI_3840x2160p60_16x9) ||
+ (hdev->para->vic == HDMI_3840x2160p50_64x27) ||
+ (hdev->para->vic == HDMI_3840x2160p60_64x27)) &&
+ (hdev->para->cs != HDMI_COLOR_FORMAT_420)) {
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x11551293);
+ } else {
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x44331290);
+ }
+ } else {
+ if (hdmitx_find_vendor(hdev) &&
+ ((hdev->para->vic == HDMI_3840x2160p50_16x9) ||
+ (hdev->para->vic == HDMI_3840x2160p60_16x9) ||
+ (hdev->para->vic == HDMI_3840x2160p50_64x27) ||
+ (hdev->para->vic == HDMI_3840x2160p60_64x27) ||
+ (hdev->para->vic == HDMI_4096x2160p50_256x135) ||
+ (hdev->para->vic == HDMI_4096x2160p60_256x135)) &&
+ (hdev->para->cs != HDMI_COLOR_FORMAT_420)) {
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x11551293);
+ } else {
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a68dc00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x65771290);
+ }
+ }
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39272000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+
+ ret = (((hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0) >> 30) & 0x3) == 0x3);
+ return ret; /* return hpll locked status */
+}
+
+static bool set_hpll_hclk_v2(unsigned int m, unsigned int frac_val)
+{
+ int ret = 0;
+
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x0b3a0400 | (m & 0xff));
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x3, 28, 2);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, frac_val);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0xea68dc00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x65771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39272000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+
+ ret = (((hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0) >> 30) & 0x3) == 0x3);
+ return ret; /* return hpll locked status */
+}
+
+static bool set_hpll_hclk_v3(unsigned int m, unsigned int frac_val)
+{
+ int ret = 0;
+
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x0b3a0400 | (m & 0xff));
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x3, 28, 2);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, frac_val);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0xea68dc00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x65771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39272000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x55540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+
+ ret = (((hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0) >> 30) & 0x3) == 0x3);
+ return ret; /* return hpll locked status */
+}
+
+void set_hpll_clk_out(unsigned int clk)
+{
+ pr_info("config HPLL = %d frac_rate = %d\n", clk, frac_rate);
+ switch (clk) {
+ case 5940000:
+ if (set_hpll_hclk_v1(0xf7, frac_rate ? 0x8148 : 0x10000))
+ break;
+ if (set_hpll_hclk_v2(0x7b, 0x18000))
+ break;
+ if (set_hpll_hclk_v3(0xf7, 0x10000))
+ break;
+ break;
+ case 5850000:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004f3);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00018000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 5600000:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004e9);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x0000aaab);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);/*test*/
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 5405400:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004e1);
+ if (frac_rate)
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00000000);
+ else
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00007333);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 4897000:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004cc);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x0000d560);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x43231290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x29272000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540028);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 4455000:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004b9);
+ if (frac_rate)
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x0000e10e);
+ else
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00014000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x43231290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x29272000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540028);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 4324320:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b0004b4);
+ if (frac_rate)
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00000000);
+ else
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00005c29);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 3712500:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b00049a);
+ if (frac_rate)
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x000110e1);
+ else
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00016000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x6a685c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x43231290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x29272000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x56540028);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 3450000:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b00048f);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00018000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 3243240:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b000487);
+ if (frac_rate)
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00000000);
+ else
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x0000451f);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 3197500:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b000485);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00007555);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ case 2970000:
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL0, 0x3b00047b);
+ if (frac_rate)
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x000140b4);
+ else
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL1, 0x00018000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ hd_write_reg(P_ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0x0, 29, 1);
+ WAIT_FOR_PLL_LOCKED(P_ANACTRL_HDMIPLL_CTRL0);
+ pr_info("HPLL: 0x%x\n", hd_read_reg(P_ANACTRL_HDMIPLL_CTRL0));
+ break;
+ default:
+ printf("error hpll clk: %d\n", clk);
+ break;
+ }
+}
+
+static void set_hpll_sspll(struct hdmitx_dev *hdev)
+{
+ enum hdmi_vic vic = hdev->vic;
+
+ switch (vic) {
+ case HDMI_1920x1080p60_16x9:
+ case HDMI_1920x1080p50_16x9:
+ case HDMI_1280x720p60_16x9:
+ case HDMI_1280x720p50_16x9:
+ case HDMI_1920x1080i60_16x9:
+ case HDMI_1920x1080i50_16x9:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 1, 29, 1);
+ /* bit[22:20] hdmi_dpll_fref_sel
+ * bit[8] hdmi_dpll_ssc_en
+ * bit[7:4] hdmi_dpll_ssc_dep_sel
+ */
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL2, 1, 20, 3);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL2, 1, 8, 1);
+ /* 2: 1000ppm 1: 500ppm */
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL2, 2, 4, 4);
+ if (hdev->dongle_mode)
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL2, 4, 4, 4);
+ /* bit[15] hdmi_dpll_sdmnc_en */
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL3, 0, 15, 1);
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0, 29, 1);
+ break;
+ default:
+ break;
+ }
+}
+
+static void set_hpll_od1(unsigned div)
+{
+ switch (div) {
+ case 1:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0, 16, 2);
+ break;
+ case 2:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 1, 16, 2);
+ break;
+ case 4:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 2, 16, 2);
+ break;
+ default:
+ break;
+ }
+}
+
+static void set_hpll_od2(unsigned div)
+{
+ switch (div) {
+ case 1:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0, 18, 2);
+ break;
+ case 2:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 1, 18, 2);
+ break;
+ case 4:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 2, 18, 2);
+ break;
+ default:
+ break;
+ }
+}
+
+static void set_hpll_od3(unsigned div)
+{
+ switch (div) {
+ case 1:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 0, 20, 2);
+ break;
+ case 2:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 1, 20, 2);
+ break;
+ case 4:
+ hd_set_reg_bits(P_ANACTRL_HDMIPLL_CTRL0, 2, 20, 2);
+ break;
+ default:
+ printf("Err %s[%d]\n", __func__, __LINE__);
+ break;
+ }
+}
+
+// --------------------------------------------------
+// clocks_set_vid_clk_div
+// --------------------------------------------------
+// wire clk_final_en = control[19];
+// wire clk_div1 = control[18];
+// wire [1:0] clk_sel = control[17:16];
+// wire set_preset = control[15];
+// wire [14:0] shift_preset = control[14:0];
+static void set_hpll_od3_clk_div(int div_sel)
+{
+ int shift_val = 0;
+ int shift_sel = 0;
+
+ /* When div 6.25, need to reset vid_pll_div */
+ if (div_sel == VID_PLL_DIV_6p25) {
+ msleep(1);
+ hd_write_reg(P_RESETCTRL_RESET0, 1 << 19);
+ }
+ // Disable the output clock
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 18, 2);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 15, 1);
+
+ switch (div_sel) {
+ case VID_PLL_DIV_1: shift_val = 0xFFFF; shift_sel = 0; break;
+ case VID_PLL_DIV_2: shift_val = 0x0aaa; shift_sel = 0; break;
+ case VID_PLL_DIV_3: shift_val = 0x0db6; shift_sel = 0; break;
+ case VID_PLL_DIV_3p5: shift_val = 0x36cc; shift_sel = 1; break;
+ case VID_PLL_DIV_3p75: shift_val = 0x6666; shift_sel = 2; break;
+ case VID_PLL_DIV_4: shift_val = 0x0ccc; shift_sel = 0; break;
+ case VID_PLL_DIV_5: shift_val = 0x739c; shift_sel = 2; break;
+ case VID_PLL_DIV_6: shift_val = 0x0e38; shift_sel = 0; break;
+ case VID_PLL_DIV_6p25: shift_val = 0x0000; shift_sel = 3; break;
+ case VID_PLL_DIV_7: shift_val = 0x3c78; shift_sel = 1; break;
+ case VID_PLL_DIV_7p5: shift_val = 0x78f0; shift_sel = 2; break;
+ case VID_PLL_DIV_12: shift_val = 0x0fc0; shift_sel = 0; break;
+ case VID_PLL_DIV_14: shift_val = 0x3f80; shift_sel = 1; break;
+ case VID_PLL_DIV_15: shift_val = 0x7f80; shift_sel = 2; break;
+ case VID_PLL_DIV_2p5: shift_val = 0x5294; shift_sel = 2; break;
+ case VID_PLL_DIV_3p25: shift_val = 0x66cc; shift_sel = 2; break;
+ default:
+ debug("Error: clocks_set_vid_clk_div: Invalid parameter\n");
+ break;
+ }
+
+ if (shift_val == 0xffff ) { // if divide by 1
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 1, 18, 1);
+ } else {
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 18, 1);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 16, 2);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 15, 1);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 0, 15);
+
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, shift_sel, 16, 2);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 1, 15, 1);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, shift_val, 0, 15);
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 0, 15, 1);
+ }
+ // Enable the final output clock
+ hd_set_reg_bits(P_CLKCTRL_VID_PLL_CLK_DIV, 1, 19, 1);
+}
+
+static void set_vid_clk_div(unsigned div)
+{
+ check_clk_config(div);
+ if (div == 0)
+ div = 1;
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL, 0, 16, 3); // select vid_pll_clk
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_DIV, div-1, 0, 8);
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL, 7, 0, 3);
+}
+
+static void set_hdmi_tx_pixel_div(unsigned div)
+{
+ check_div();
+ hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, div, 16, 4);
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL2, 1, 5, 1); //enable gate
+}
+
+static void set_encp_div(unsigned div)
+{
+ check_div();
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_DIV, div, 24, 4);
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL2, 1, 2, 1); //enable gate
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL, 1, 19, 1);
+}
+
+static void set_enci_div(unsigned div)
+{
+ check_div();
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_DIV, div, 28, 4);
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL2, 1, 0, 1); //enable gate
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL, 1, 19, 1);
+}
+
+/* mode hpll_clk_out od1 od2(PHY) od3
+ * vid_pll_div vid_clk_div hdmi_tx_pixel_div encp_div enci_div
+ */
+/* For colordepth 8bits */
+static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
+ {{HDMI_720x480i60_16x9,
+ HDMI_720x576i50_16x9,
+ GROUP_END},
+ 1, VIU_ENCI, 4324320, 4, 4, 1, VID_PLL_DIV_5, 1, 2, -1, 2},
+ {{HDMI_720x576p50_16x9,
+ HDMI_720x480p60_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4324320, 4, 4, 1, VID_PLL_DIV_5, 1, 2, 2, -1},
+ {{HDMI_720x576p100_16x9,
+ HDMI_720x480p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4324320, 4, 2, 1, VID_PLL_DIV_5, 1, 2, 2, -1},
+ {{HDMI_1280x720p50_16x9,
+ HDMI_1280x720p60_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 4, 2, 1, VID_PLL_DIV_5, 1, 2, 2, -1},
+ {{HDMI_1920x1080i60_16x9,
+ HDMI_1920x1080i50_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 4, 2, 1, VID_PLL_DIV_5, 1, 2, 2, -1},
+ {{HDMI_1920x1080i100_16x9,
+ HDMI_1920x1080i120_16x9,
+ HDMI_1280x720p100_16x9,
+ HDMI_1280x720p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 4, 1, 1, VID_PLL_DIV_5, 1, 2, 2, -1},
+ {{HDMI_1920x1080p60_16x9,
+ HDMI_1920x1080p50_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 4, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ {{HDMI_1920x1080p30_16x9,
+ HDMI_1920x1080p24_16x9,
+ HDMI_1920x1080p25_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 4, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ {{HDMI_3840x2160p30_16x9,
+ HDMI_3840x2160p25_16x9,
+ HDMI_3840x2160p24_16x9,
+ HDMI_4096x2160p24_256x135,
+ HDMI_4096x2160p25_256x135,
+ HDMI_4096x2160p30_256x135,
+ HDMI_1920x1080p100_16x9,
+ HDMI_1920x1080p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_2160x1200p90hz,
+ GROUP_END},
+ 1, VIU_ENCP, 5371100, 1, 2, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ {{HDMI_3840x2160p60_16x9,
+ HDMI_3840x2160p50_16x9,
+ HDMI_4096x2160p60_256x135,
+ HDMI_4096x2160p50_256x135,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 1, 1, 2, VID_PLL_DIV_5, 1, 1, 1, -1},
+ {{HDMI_4096x2160p60_256x135_Y420,
+ HDMI_4096x2160p50_256x135_Y420,
+ HDMI_3840x2160p60_16x9_Y420,
+ HDMI_3840x2160p50_16x9_Y420,
+ GROUP_END},
+ 1, VIU_ENCP, 5940000, 2, 1, 1, VID_PLL_DIV_5, 1, 2, 1, -1},
+ /* pll setting for VESA modes */
+ {{HDMIV_640x480p60hz, /* 4.028G / 16 = 251.75M */
+ GROUP_END},
+ 1, VIU_ENCP, 4028000, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_800x480p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4761600, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_800x600p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 3200000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_852x480p60hz,
+ HDMIV_854x480p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4838400, 4, 4, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1024x600p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4115866, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1024x768p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 5200000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1280x768p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 3180000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1280x800p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 5680000, 4, 2, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1152x864p75hz,
+ HDMIV_1280x960p60hz,
+ HDMIV_1280x1024p60hz,
+ HDMIV_1600x900p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4320000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1600x1200p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 3240000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1360x768p60hz,
+ HDMIV_1366x768p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 3420000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1400x1050p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4870000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1440x900p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4260000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1440x2560p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 4897000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1440x2560p70hz,
+ GROUP_END},
+ 1, VIU_ENCP, 5600000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1680x1050p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 5850000, 4, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_1920x1200p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 3865000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {{HDMIV_2560x1600p60hz,
+ GROUP_END},
+ 1, VIU_ENCP, 3485000, 1, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1},
+ {
+ {
+ HDMIV_3440x1440p60hz, GROUP_END
+ },
+ 1, VIU_ENCP, 3197500, 1, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1
+ },
+ {
+ {
+ HDMIV_2400x1200p90hz, GROUP_END
+ },
+ 1, VIU_ENCP, 5600000, 2, 1, 1, VID_PLL_DIV_5, 2, 1, 1, -1
+ },
+};
+
+/* For colordepth 10bits */
+static struct hw_enc_clk_val_group setting_enc_clk_val_30[] = {
+ {{HDMI_720x480i60_16x9,
+ HDMI_720x576i50_16x9,
+ GROUP_END},
+ 1, VIU_ENCI, 5405400, 4, 4, 1, VID_PLL_DIV_6p25, 1, 2, -1, 2},
+ {{HDMI_720x576p50_16x9,
+ HDMI_720x480p60_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5405400, 4, 4, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+ {{HDMI_720x576p100_16x9,
+ HDMI_720x480p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 5405400, 4, 2, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+ {{HDMI_1280x720p50_16x9,
+ HDMI_1280x720p60_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 4, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+ {{HDMI_1920x1080i60_16x9,
+ HDMI_1920x1080i50_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 4, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+ {{HDMI_1920x1080i120_16x9,
+ HDMI_1920x1080i100_16x9,
+ HDMI_1280x720p100_16x9,
+ HDMI_1280x720p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 2, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+ {{HDMI_1920x1080p60_16x9,
+ HDMI_1920x1080p50_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 1, 2, 2, VID_PLL_DIV_6p25, 1, 1, 1, -1},
+ {{HDMI_1920x1080p120_16x9,
+ HDMI_1920x1080p100_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 1, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+ {{HDMI_1920x1080p30_16x9,
+ HDMI_1920x1080p24_16x9,
+ HDMI_1920x1080p25_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 2, 2, 2, VID_PLL_DIV_6p25, 1, 1, 1, -1},
+ {{HDMI_4096x2160p60_256x135_Y420,
+ HDMI_4096x2160p50_256x135_Y420,
+ HDMI_3840x2160p60_16x9_Y420,
+ HDMI_3840x2160p50_16x9_Y420,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 1, 1, 1, VID_PLL_DIV_6p25, 1, 2, 1, -1},
+ {{HDMI_3840x2160p24_16x9,
+ HDMI_3840x2160p25_16x9,
+ HDMI_3840x2160p30_16x9,
+ HDMI_4096x2160p24_256x135,
+ HDMI_4096x2160p25_256x135,
+ HDMI_4096x2160p30_256x135,
+ GROUP_END},
+ 1, VIU_ENCP, 3712500, 1, 1, 1, VID_PLL_DIV_6p25, 1, 2, 2, -1},
+};
+
+/* For colordepth 12bits */
+static struct hw_enc_clk_val_group setting_enc_clk_val_36[] = {
+ {{HDMI_720x480i60_16x9,
+ HDMI_720x576i50_16x9,
+ GROUP_END},
+ 1, VIU_ENCI, 3243240, 2, 4, 1, VID_PLL_DIV_7p5, 1, 2, -1, 2},
+ {{HDMI_720x576p50_16x9,
+ HDMI_720x480p60_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3243240, 2, 4, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+ {{HDMI_720x576p100_16x9,
+ HDMI_720x480p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 3243240, 2, 2, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+ {{HDMI_1280x720p50_16x9,
+ HDMI_1280x720p60_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 4, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+ {{HDMI_1920x1080i60_16x9,
+ HDMI_1920x1080i50_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 4, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+ {{HDMI_1920x1080i120_16x9,
+ HDMI_1920x1080i100_16x9,
+ HDMI_1280x720p100_16x9,
+ HDMI_1280x720p120_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 2, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+ {{HDMI_1920x1080p60_16x9,
+ HDMI_1920x1080p50_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 1, 2, 2, VID_PLL_DIV_7p5, 1, 1, 1, -1},
+ {{HDMI_1920x1080p120_16x9,
+ HDMI_1920x1080p100_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 1, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+ {{HDMI_1920x1080p30_16x9,
+ HDMI_1920x1080p24_16x9,
+ HDMI_1920x1080p25_16x9,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 2, 2, 2, VID_PLL_DIV_7p5, 1, 1, 1, -1},
+ {{HDMI_4096x2160p60_256x135_Y420,
+ HDMI_4096x2160p50_256x135_Y420,
+ HDMI_3840x2160p60_16x9_Y420,
+ HDMI_3840x2160p50_16x9_Y420,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 1, 1, 2, VID_PLL_DIV_3p25, 1, 2, 1, -1},
+ {{HDMI_3840x2160p24_16x9,
+ HDMI_3840x2160p25_16x9,
+ HDMI_3840x2160p30_16x9,
+ HDMI_4096x2160p24_256x135,
+ HDMI_4096x2160p25_256x135,
+ HDMI_4096x2160p30_256x135,
+ GROUP_END},
+ 1, VIU_ENCP, 4455000, 1, 1, 1, VID_PLL_DIV_7p5, 1, 2, 2, -1},
+};
+
+static void set_hdmitx_fe_clk(struct hdmitx_dev *hdev)
+{
+ unsigned int tmp = 0;
+ enum hdmi_vic vic = hdev->vic;
+ hd_set_reg_bits(P_CLKCTRL_VID_CLK_CTRL2, 1, 9, 1);
+
+ switch (vic) {
+ case HDMI_720x480i60_16x9:
+ case HDMI_720x576i50_16x9:
+ tmp = (hd_read_reg(P_CLKCTRL_VID_CLK_DIV) >> 28) & 0xf;
+ break;
+ default:
+ tmp = (hd_read_reg(P_CLKCTRL_VID_CLK_DIV) >> 24) & 0xf;
+ break;
+ }
+
+ hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, tmp, 20, 4);
+}
+
+static void set_hdmitx_clk_(struct hdmitx_dev *hdev, enum hdmi_color_depth cd)
+{
+ int i = 0;
+ int j = 0;
+ struct hw_enc_clk_val_group *p_enc = NULL;
+ enum hdmi_vic vic = hdev->vic;
+ char *sspll_dis = NULL;
+
+ if (cd == HDMI_COLOR_DEPTH_24B) {
+ p_enc = &setting_enc_clk_val_24[0];
+ for (j = 0; j < ARRAY_SIZE(setting_enc_clk_val_24); j++) {
+ for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i] != GROUP_END)); i ++) {
+ if (vic == p_enc[j].group[i])
+ goto next;
+ }
+ }
+ if (j == ARRAY_SIZE(setting_enc_clk_val_24)) {
+ debug("Not find VIC = %d for hpll setting\n", vic);
+ return;
+ }
+ } else if (cd == HDMI_COLOR_DEPTH_30B) {
+ p_enc = &setting_enc_clk_val_30[0];
+ for (j = 0; j < ARRAY_SIZE(setting_enc_clk_val_30); j++) {
+ for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i] != GROUP_END)); i ++) {
+ if (vic == p_enc[j].group[i])
+ goto next;
+ }
+ }
+ if (j == ARRAY_SIZE(setting_enc_clk_val_30)) {
+ debug("Not find VIC = %d for hpll setting\n", vic);
+ return;
+ }
+ } else if (cd == HDMI_COLOR_DEPTH_36B) {
+ p_enc = &setting_enc_clk_val_36[0];
+ for (j = 0; j < ARRAY_SIZE(setting_enc_clk_val_36); j++) {
+ for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i]
+ != GROUP_END)); i++) {
+ if (vic == p_enc[j].group[i])
+ goto next;
+ }
+ }
+ if (j == ARRAY_SIZE(setting_enc_clk_val_36)) {
+ printf("Not find VIC = %d for hpll setting\n", vic);
+ return;
+ }
+ } else {
+ printf("not support colordepth 48bits\n");
+ return;
+ }
+next:
+ set_hdmitx_sys_clk();
+ set_hpll_clk_out(p_enc[j].hpll_clk_out);
+ sspll_dis = env_get("sspll_dis");
+ if ((!sspll_dis || !strcmp(sspll_dis, "0")) &&
+ (cd == HDMI_COLOR_DEPTH_24B))
+ set_hpll_sspll(hdev);
+ set_hpll_od1(p_enc[j].od1);
+ set_hpll_od2(p_enc[j].od2);
+ set_hpll_od3(p_enc[j].od3);
+ set_hpll_od3_clk_div(p_enc[j].vid_pll_div);
+ debug("j = %d vid_clk_div = %d\n", j, p_enc[j].vid_clk_div);
+ set_vid_clk_div(p_enc[j].vid_clk_div);
+ set_hdmi_tx_pixel_div(p_enc[j].hdmi_tx_pixel_div);
+ set_encp_div(p_enc[j].encp_div);
+ set_enci_div(p_enc[j].enci_div);
+ set_hdmitx_fe_clk(hdev);
+}
+
+static int likely_frac_rate_mode(char *m)
+{
+ if (strstr(m, "24hz") || strstr(m, "30hz") || strstr(m, "60hz")
+ || strstr(m, "120hz") || strstr(m, "240hz"))
+ return 1;
+ else
+ return 0;
+}
+
+void hdmitx_set_clk(struct hdmitx_dev *hdev)
+{
+ char *frac_rate_str = NULL;
+
+ frac_rate_str = env_get("frac_rate_policy");
+ if (frac_rate_str && (frac_rate_str[0] == '0'))
+ frac_rate = 0;
+ else if (likely_frac_rate_mode(hdev->para->ext_name))
+ frac_rate = 1;
+ hdev->frac_rate_policy = frac_rate;
+
+ if (hdev->para->cs != HDMI_COLOR_FORMAT_422)
+ set_hdmitx_clk_(hdev, hdev->para->cd);
+ else
+ set_hdmitx_clk_(hdev, HDMI_COLOR_DEPTH_24B);
+}
+
diff --git a/arch/arm/mach-meson/t7/hdmitx_clk.h b/arch/arm/mach-meson/t7/hdmitx_clk.h
new file mode 100644
index 0000000..d8fda6f
--- /dev/null
+++ b/arch/arm/mach-meson/t7/hdmitx_clk.h
@@ -0,0 +1,68 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __HDMITX_COMMON_H__
+#define __HDMITX_COMMON_H__
+
+#include <common.h>
+#include <amlogic/media/vout/hdmitx/hdmitx.h>
+
+#define VID_PLL_DIV_1 0
+#define VID_PLL_DIV_2 1
+#define VID_PLL_DIV_3 2
+#define VID_PLL_DIV_3p5 3
+#define VID_PLL_DIV_3p75 4
+#define VID_PLL_DIV_4 5
+#define VID_PLL_DIV_5 6
+#define VID_PLL_DIV_6 7
+#define VID_PLL_DIV_6p25 8
+#define VID_PLL_DIV_7 9
+#define VID_PLL_DIV_7p5 10
+#define VID_PLL_DIV_12 11
+#define VID_PLL_DIV_14 12
+#define VID_PLL_DIV_15 13
+#define VID_PLL_DIV_2p5 14
+#define VID_PLL_DIV_3p25 15
+
+enum viu_type {
+ VIU_ENCL = 0,
+ VIU_ENCI,
+ VIU_ENCP,
+ VIU_ENCT,
+};
+
+typedef struct{
+ enum hdmi_vic vic;
+ unsigned viu_path;
+ enum viu_type viu_type;
+ unsigned hpll_clk_out;
+ unsigned od1;
+ unsigned od2;
+ unsigned od3;
+ unsigned vid_pll_div;
+ unsigned vid_clk_div;
+ unsigned hdmi_tx_pixel_div;
+ unsigned encp_div;
+ unsigned enci_div;
+}hw_enc_clk_val_t;
+
+#define GROUP_MAX 10
+#define GROUP_END -1
+struct hw_enc_clk_val_group {
+ enum hdmi_vic group[GROUP_MAX];
+ unsigned viu_path;
+ enum viu_type viu_type;
+ unsigned hpll_clk_out;
+ unsigned od1;
+ unsigned od2;
+ unsigned od3;
+ unsigned vid_pll_div;
+ unsigned vid_clk_div;
+ unsigned hdmi_tx_pixel_div;
+ unsigned encp_div;
+ unsigned enci_div;
+};
+
+#endif
diff --git a/arch/arm/mach-meson/t7/hdmitx_hw.c b/arch/arm/mach-meson/t7/hdmitx_hw.c
new file mode 100644
index 0000000..51c9fbf
--- /dev/null
+++ b/arch/arm/mach-meson/t7/hdmitx_hw.c
@@ -0,0 +1,314 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
+#include <amlogic/media/vout/hdmitx/hdmitx_reg.h>
+#include <amlogic/media/vout/hdmitx/mach_reg.h>
+#include <asm/arch/bl31_apis.h>
+#include "hdmitx_misc.h"
+
+static struct reg_map reg_maps[] = {
+ [CBUS_REG_IDX] = { /* CBUS */
+ .base_addr = 0xfe001000,
+ },
+ [PERIPHS_REG_IDX] = { /* PERIPHS */
+ .base_addr = 0xfe004000,
+ },
+ [VCBUS_REG_IDX] = { /* VPU */
+ .base_addr = 0xff000000,
+ },
+ [HHI_REG_IDX] = { /* HIU */
+ .base_addr = 0xfe000000,
+ },
+ [SYSCTRL_REG_IDX] = {
+ .base_addr = 0xfe010000,
+ },
+ [RESETCTRL_REG_IDX] = {
+ .base_addr = 0xfe002000,
+ },
+ [ANACTRL_REG_IDX] = {
+ .base_addr = 0xfe008000,
+ },
+ [PWRCTRL_REG_IDX] = {
+ .base_addr = 0xfe00c000,
+ },
+ [HDMITX_SEC_REG_IDX] = { /* HDMITX DWC LEVEL*/
+ .base_addr = 0xfe300000,
+ },
+ [HDMITX_REG_IDX] = { /* HDMITX TOP LEVEL*/
+ .base_addr = 0xfe308000,
+ },
+ [REG_IDX_END] = {
+ },
+};
+
+#define HDMITX_DWC_BASE_OFFSET (reg_maps[HDMITX_SEC_REG_IDX].base_addr)
+#define HDMITX_TOP_BASE_OFFSET (reg_maps[HDMITX_REG_IDX].base_addr)
+
+int hdmitx_get_hpd_state(void)
+{
+ int st = 0;
+
+ st = !!(hd_read_reg(P_PADCTRL_GPIOH_I) & (1 << 2));
+ return st;
+}
+
+void hdmitx_ddc_init(void)
+{
+ /*Mux DDC SDA/SCL*/
+ hd_set_reg_bits(P_PADCTRL_PIN_MUX_REGB, 1, 0, 4);
+ hd_set_reg_bits(P_PADCTRL_PIN_MUX_REGB, 1, 4, 4);
+}
+
+static uint32_t get_base_addr(uint32_t idx)
+{
+ if (idx >= REG_IDX_END)
+ return 0;
+ if (!reg_maps[idx].base_addr)
+ printf("%s[%d] idx = %d\n", __func__, __LINE__, idx);
+
+ return reg_maps[idx].base_addr;
+}
+
+uint32_t hd_get_paddr(uint32_t addr)
+{
+ uint32_t idx = (addr) >> BASE_REG_OFFSET;
+ uint32_t offset_addr = ((1 << BASE_REG_OFFSET) - 1) & (addr);
+ uint32_t paddr;
+
+ paddr = get_base_addr(idx) + offset_addr;
+ return paddr;
+}
+
+uint32_t hd_read_reg(uint32_t addr)
+{
+ uint32_t val;
+ uint32_t idx = (addr) >> BASE_REG_OFFSET;
+ uint32_t offset_addr = ((1 << BASE_REG_OFFSET) - 1) & (addr);
+ void *paddr;
+
+ paddr = (void *)((unsigned long)(get_base_addr(idx) + offset_addr));
+ val = readl(paddr);
+
+ return val;
+}
+
+void hd_write_reg(unsigned int addr, unsigned int val)
+{
+ uint32_t idx = (addr) >> BASE_REG_OFFSET;
+ uint32_t offset_addr = ((1 << BASE_REG_OFFSET) - 1) & (addr);
+ void *paddr;
+
+ paddr = (void *)((unsigned long)(get_base_addr(idx) + offset_addr));
+ writel(val, paddr);
+}
+
+void hd_set_reg_bits(unsigned int addr, unsigned int value,
+ unsigned int offset, unsigned int len)
+{
+ unsigned int data32 = 0;
+
+ data32 = hd_read_reg(addr);
+ data32 &= ~(((1 << len) - 1) << offset);
+ data32 |= (value & ((1 << len) - 1)) << offset;
+ hd_write_reg(addr, data32);
+}
+
+static unsigned int hdmitx_rd_reg_normal(unsigned int addr)
+{
+ unsigned int data;
+ register long x0 asm("x0") = 0x82000018;
+ register long x1 asm("x1") = (unsigned long)addr;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ "smc #0\n"
+ : "+r"(x0) : "r"(x1)
+ );
+ data = (unsigned int)(x0&0xffffffff);
+
+ return data;
+}
+
+static void hdmitx_wr_reg_normal(unsigned int addr, unsigned int data)
+{
+ register long x0 asm("x0") = 0x82000019;
+ register long x1 asm("x1") = (unsigned long)addr;
+ register long x2 asm("x2") = data;
+
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ "smc #0\n"
+ : : "r"(x0), "r"(x1), "r"(x2)
+ );
+}
+
+unsigned int hdmitx_rd_reg(unsigned int addr)
+{
+ unsigned int large_offset = addr >> 24;
+ unsigned int small_offset = addr & ((1 << 24) - 1);
+ unsigned long hdmitx_addr = 0;
+ unsigned int data;
+
+ switch (large_offset) {
+ case 0x10:
+ /*DWC*/
+ hdmitx_addr = HDMITX_DWC_BASE_OFFSET + small_offset;
+ data = readb(hdmitx_addr);
+ break;
+ case 0x11:
+ case 0x01:
+ data = hdmitx_rd_reg_normal(addr);
+ break;
+ case 0x00:
+ default:
+ /* TOP */
+ if ((small_offset >= 0x2000) && (small_offset <= 0x365E)) {
+ hdmitx_addr = HDMITX_TOP_BASE_OFFSET + small_offset;
+ data = readb(hdmitx_addr);
+ } else {
+ hdmitx_addr = HDMITX_TOP_BASE_OFFSET + (small_offset << 2);
+ data = readl(hdmitx_addr);
+ }
+ break;
+ }
+
+ return data;
+}
+
+void hdmitx_wr_reg(unsigned int addr, unsigned int data)
+{
+ unsigned int large_offset = addr >> 24;
+ unsigned int small_offset = addr & ((1 << 24) - 1);
+ unsigned long hdmitx_addr = 0;
+
+ switch (large_offset) {
+ case 0x10:
+ /*DWC*/
+ hdmitx_addr = HDMITX_DWC_BASE_OFFSET + small_offset;
+ writeb(data & 0xff, hdmitx_addr);
+ break;
+ case 0x11:
+ case 0x01:
+ /*SECURITY DWC/TOP*/
+ hdmitx_wr_reg_normal(addr, data);
+ break;
+ case 00:
+ default:
+ /*TOP*/
+ if ((small_offset >= 0x2000) && (small_offset <= 0x365E)) {
+ hdmitx_addr = HDMITX_TOP_BASE_OFFSET + small_offset;
+ writeb(data & 0xff, hdmitx_addr);
+ } else {
+ hdmitx_addr = HDMITX_TOP_BASE_OFFSET + (small_offset << 2);
+ writel(data, hdmitx_addr);
+ }
+ }
+}
+
+void hdmitx_set_reg_bits(unsigned int addr, unsigned int value,
+ unsigned int offset, unsigned int len)
+{
+ unsigned int data32 = 0;
+
+ data32 = hdmitx_rd_reg(addr);
+ data32 &= ~(((1 << len) - 1) << offset);
+ data32 |= (value & ((1 << len) - 1)) << offset;
+ hdmitx_wr_reg(addr, data32);
+}
+
+void hdmitx_poll_reg(unsigned int addr, unsigned int val, unsigned long timeout)
+{
+}
+
+unsigned int hdmitx_rd_check_reg(unsigned int addr, unsigned int exp_data,
+ unsigned int mask)
+{
+ return 0;
+}
+
+void hdmitx_hdcp_init(void)
+{
+ register long x0 asm("x0") = 0x82000012;
+ asm volatile(
+ __asmeq("%0", "x0")
+ "smc #0\n"
+ : : "r"(x0)
+ );
+}
+
+void hdmitx_set_phypara(enum hdmi_phy_para mode)
+{
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x0);
+/* P_ANACTRL_HDMIPHY_CTRL1 bit[1]: enable clock bit[0]: soft reset */
+#define RESET_HDMI_PHY() \
+do { \
+ hd_set_reg_bits(P_ANACTRL_HDMIPHY_CTRL1, 0xf, 0, 4); \
+ mdelay(2); \
+ hd_set_reg_bits(P_ANACTRL_HDMIPHY_CTRL1, 0xe, 0, 4); \
+ mdelay(2); \
+} while (0)
+
+ hd_set_reg_bits(P_ANACTRL_HDMIPHY_CTRL1, 0x0390, 16, 16);
+ hd_set_reg_bits(P_ANACTRL_HDMIPHY_CTRL1, 0x0, 0, 4);
+ RESET_HDMI_PHY();
+ RESET_HDMI_PHY();
+#undef RESET_HDMI_PHY
+
+ switch (mode) {
+ case HDMI_PHYPARA_6G: /* 5.94/4.5/3.7Gbps */
+ case HDMI_PHYPARA_4p5G:
+ case HDMI_PHYPARA_3p7G:
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x37eb65c4);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0x0000080b);
+ break;
+ case HDMI_PHYPARA_3G: /* 2.97Gbps */
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x33eb42a2);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0x00000003);
+ break;
+ case HDMI_PHYPARA_270M: /* 1.485Gbps, and below */
+ case HDMI_PHYPARA_DEF:
+ default:
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0x33eb4252);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0x2ab0ff3b);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0x00000003);
+ break;
+ }
+}
+
+void hdmitx_turnoff(void)
+{
+ /* Close HDMITX PHY */
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL0, 0);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL3, 0);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL5, 0);
+ /* Disable HPLL */
+ hd_write_reg(ANACTRL_HDMIPLL_CTRL0, 0);
+}
+
+void hdmitx_test_prbs(void)
+{
+ unsigned int i;
+
+ for (i = 0; i < 4; i ++) {
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL1, 0x0390000f);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL1, 0x0390000e);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL1, 0x03904002);
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL4, 0x0001efff | (i << 20));
+ hd_write_reg(P_ANACTRL_HDMIPHY_CTRL1, 0xef904002);
+ mdelay(1);
+ if (i == 0)
+ printf("prbs clk: %08x\n",hd_read_reg(P_ANACTRL_HDMIPLL_CTRL6));
+ else
+ printf("prbs D[%d]: %08x\n", i -1, hd_read_reg(P_ANACTRL_HDMIPLL_CTRL6));
+ }
+}
diff --git a/arch/arm/mach-meson/t7/hdmitx_misc.h b/arch/arm/mach-meson/t7/hdmitx_misc.h
new file mode 100644
index 0000000..5e32df8
--- /dev/null
+++ b/arch/arm/mach-meson/t7/hdmitx_misc.h
@@ -0,0 +1,71 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __HDMITX_MISC_H__
+#define __HDMITX_MISC_H__
+
+/* miscellaneous definition */
+
+/* REG_BASE: REGISTER_BASE_ADDR = 0xfe000000 */
+#define CLKCTRL_SYS_CLK_EN0_REG2 0x0013
+#define P_CLKCTRL_SYS_CLK_EN0_REG2 HHI_REG_ADDR(CLKCTRL_SYS_CLK_EN0_REG2)
+#define CLKCTRL_VID_CLK_CTRL 0x0030
+#define P_CLKCTRL_VID_CLK_CTRL HHI_REG_ADDR(CLKCTRL_VID_CLK_CTRL)
+#define CLKCTRL_VID_CLK_CTRL2 0x0031
+#define P_CLKCTRL_VID_CLK_CTRL2 HHI_REG_ADDR(CLKCTRL_VID_CLK_CTRL2)
+#define CLKCTRL_VID_CLK_DIV 0x0032
+#define P_CLKCTRL_VID_CLK_DIV HHI_REG_ADDR(CLKCTRL_VID_CLK_DIV)
+#define CLKCTRL_HDMI_CLK_CTRL 0x0038
+#define P_CLKCTRL_HDMI_CLK_CTRL HHI_REG_ADDR(CLKCTRL_HDMI_CLK_CTRL)
+#define CLKCTRL_VID_PLL_CLK_DIV 0x0039
+#define P_CLKCTRL_VID_PLL_CLK_DIV HHI_REG_ADDR(CLKCTRL_VID_PLL_CLK_DIV)
+#define CLKCTRL_HDCP22_CLK_CTRL 0x0040
+#define P_CLKCTRL_HDCP22_CLK_CTRL HHI_REG_ADDR(CLKCTRL_HDCP22_CLK_CTRL)
+
+/* REG_BASE: REGISTER_BASE_ADDR = 0xfe002000 */
+#define RESETCTRL_RESET0 0x0000
+#define P_RESETCTRL_RESET0 RESETCTRL_REG_ADDR(RESETCTRL_RESET0)
+#define RESETCTRL_RESET2 0x0002
+#define P_RESETCTRL_RESET2 RESETCTRL_REG_ADDR(RESETCTRL_RESET2)
+
+/* REG_BASE: REGISTER_BASE_ADDR = 0xfe008000 */
+#define ANACTRL_HDMIPLL_CTRL0 0x0070
+#define P_ANACTRL_HDMIPLL_CTRL0 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL0)
+#define ANACTRL_HDMIPLL_CTRL1 0x0071
+#define P_ANACTRL_HDMIPLL_CTRL1 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL1)
+#define ANACTRL_HDMIPLL_CTRL2 0x0072
+#define P_ANACTRL_HDMIPLL_CTRL2 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL2)
+#define ANACTRL_HDMIPLL_CTRL3 0x0073
+#define P_ANACTRL_HDMIPLL_CTRL3 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL3)
+#define ANACTRL_HDMIPLL_CTRL4 0x0074
+#define P_ANACTRL_HDMIPLL_CTRL4 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL4)
+#define ANACTRL_HDMIPLL_CTRL5 0x0075
+#define P_ANACTRL_HDMIPLL_CTRL5 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL5)
+#define ANACTRL_HDMIPLL_CTRL6 0x0076
+#define P_ANACTRL_HDMIPLL_CTRL6 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL6)
+#define ANACTRL_HDMIPLL_STS 0x0077
+#define P_ANACTRL_HDMIPLL_STS ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_STS)
+#define ANACTRL_HDMIPLL_VLOCK 0x0079
+#define P_ANACTRL_HDMIPLL_VLOCK ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_VLOCK)
+#define ANACTRL_HDMIPHY_CTRL0 0x0080
+#define P_ANACTRL_HDMIPHY_CTRL0 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL0)
+#define ANACTRL_HDMIPHY_CTRL1 0x0081
+#define P_ANACTRL_HDMIPHY_CTRL1 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL1)
+#define ANACTRL_HDMIPHY_CTRL2 0x0082
+#define P_ANACTRL_HDMIPHY_CTRL2 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL2)
+#define ANACTRL_HDMIPHY_CTRL3 0x0083
+#define P_ANACTRL_HDMIPHY_CTRL3 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL3)
+#define ANACTRL_HDMIPHY_CTRL4 0x0084
+#define P_ANACTRL_HDMIPHY_CTRL4 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL4)
+#define ANACTRL_HDMIPHY_CTRL5 0x0085
+#define P_ANACTRL_HDMIPHY_CTRL5 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL5)
+#define ANACTRL_HDMIPHY_STS 0x0086
+#define P_ANACTRL_HDMIPHY_STS ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_STS)
+
+/* REG_BASE: REGISTER_BASE_ADDR = 0xfe00c000 */
+#define PWRCTRL_MEM_PD11 0x001b
+#define P_PWRCTRL_MEM_PD11 PWRCTRL_REG_ADDR(PWRCTRL_MEM_PD11)
+
+#endif
diff --git a/arch/arm/mach-meson/t7/mailbox.c b/arch/arm/mach-meson/t7/mailbox.c
new file mode 100644
index 0000000..342b6c0
--- /dev/null
+++ b/arch/arm/mach-meson/t7/mailbox.c
@@ -0,0 +1,161 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/arch/io.h>
+#include <command.h>
+#include <malloc.h>
+#include <asm/arch/mailbox.h>
+#include <asm/arch/secure_apb.h>
+
+#define aml_writel32(value, reg) writel(value, reg)
+#define aml_readl32(reg) readl(reg)
+
+
+static inline void mbwrite(uint32_t to, void *from, long count)
+{
+ int i = 0;
+ int len = count / 4 + (count % 4);
+ uint32_t *p = from;
+
+ while (len > 0) {
+ aml_writel32(p[i], to + (4 * i));
+ len--;
+ i++;
+ }
+}
+
+static inline void mbclean(uint32_t to, long count)
+{
+ int i = 0;
+ int len = count / 4 + (count % 4);
+
+ while (len > 0) {
+ aml_writel32(0, to + (4 * i));
+ len--;
+ i++;
+ }
+}
+
+int mhu_get_addr(uint32_t chan, uint32_t *mboxset, uint32_t *mboxsts,
+ uintptr_t *mboxpl, uint32_t *mboxwr, uint32_t *mboxrd,
+ uint32_t *mboxirqclr, uint32_t *mboxid)
+{
+ int ret = 0;
+
+ switch (chan) {
+ case AOCPU_REE_CHANNEL:
+ *mboxset = REE2AO_SET_ADDR;
+ *mboxsts = REE2AO_STS_ADDR;
+ *mboxwr = REE2AO_WR_ADDR;
+ *mboxrd = REE2AO_RD_ADDR;
+ *mboxirqclr = REE2AO_IRQCLR_ADDR;
+ *mboxid = REE2AO_MBOX_ID;
+ break;
+ default:
+ printf("[BL33]: no support chan 0x%x\n", chan);
+ ret = -1;
+ break;
+ };
+ return ret;
+}
+
+void mhu_message_start(uint32_t mboxsts)
+{
+ /* Make sure any previous command has finished */
+ while (aml_readl32(mboxsts) != 0);
+}
+
+void mhu_build_payload(uintptr_t mboxpl, uint32_t mboxwr, void *message, uint32_t size)
+{
+ if (size > (MHU_PAYLOAD_SIZE - MHU_DATA_OFFSET)) {
+ printf("bl33: scpi send input size error\n");
+ return;
+ }
+ if (size == 0)
+ return;
+ mbwrite(mboxwr + MHU_DATA_OFFSET, message, size);
+}
+
+void mhu_get_payload(uintptr_t mboxpl, uint32_t mboxwr, void *message, uint32_t size)
+{
+ if (size > (MHU_PAYLOAD_SIZE - MHU_DATA_OFFSET)) {
+ printf("bl33: scpi send input size error\n");
+ return;
+ }
+ if (size == 0)
+ return;
+ printf("bl33: scpi no support get revmessage\n");
+}
+
+void mhu_message_send(uint32_t mboxset, uint32_t command, uint32_t size)
+{
+ uint32_t mbox_cmd;
+ mbox_cmd = MHU_CMD_BUILD(command, size + MHU_DATA_OFFSET);
+ aml_writel32(mbox_cmd, mboxset);
+}
+
+uint32_t mhu_message_wait(uint32_t mboxsts)
+{
+ /* Wait for response from HIFI */
+ uint32_t response;
+
+ while ((response = aml_readl32(mboxsts)));
+
+ return response;
+}
+
+void mhu_message_end(uintptr_t mboxpl, uint32_t mboxwr, uint32_t mboxirqclr, uint32_t mboxid)
+{
+ uint64_t mask = 0;
+ uint32_t lmask = 0, hmask = 0;
+
+ mbclean(mboxwr, MHU_PAYLOAD_SIZE);
+ /* Clear any response we got by writing all ones to the CLEAR register */
+ mask = MHU_ACK_MASK(mboxid);
+
+ lmask = mask & 0xffffffff;
+ hmask = (mask >> 32) & 0xffffffff;
+ aml_writel32(lmask, REE2AO_IRQCLR_ADDR);
+ aml_writel32(hmask, REE2AO_IRQCLR_ADDR1);
+}
+
+void mhu_init(void)
+{
+ aml_writel32(0xffffffffu, REE2AO_CLR_ADDR);
+ printf("[BL33] mhu init done 121101-v2\n");
+}
+int scpi_send_data(uint32_t chan, uint32_t command,
+ void *sendmessage, uint32_t sendsize,
+ void *revmessage, uint32_t revsize)
+{
+ uint32_t mboxset = 0;
+ uint32_t mboxsts = 0;
+ uintptr_t mboxpl = 0;
+ uint32_t mboxwr = 0;
+ uint32_t mboxrd = 0;
+ uint32_t mboxirq = 0;
+ uint32_t mboxid = 0;
+ int ret = 0;
+
+ ret = mhu_get_addr(chan, &mboxset, &mboxsts,
+ &mboxpl, &mboxwr, &mboxrd,
+ &mboxirq, &mboxid);
+ if (ret) {
+ printf("bl33: mhu get addr fail\n");
+ return ret;
+ }
+ mhu_message_start(mboxsts);
+ if (sendmessage != NULL && sendsize != 0)
+ mhu_build_payload(mboxpl, mboxwr, sendmessage, sendsize);
+ mhu_message_send(mboxset, command, sendsize);
+ mhu_message_wait(mboxsts);
+ if (revmessage != NULL && revsize != 0)
+ mhu_get_payload(mboxpl, mboxrd, revmessage, revsize);
+ mhu_message_end(mboxpl, mboxwr, mboxirq, mboxid);
+ return ret;
+}
+
diff --git a/arch/arm/mach-meson/t7/oscring.c b/arch/arm/mach-meson/t7/oscring.c
new file mode 100644
index 0000000..fa1496f
--- /dev/null
+++ b/arch/arm/mach-meson/t7/oscring.c
@@ -0,0 +1,146 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <asm/arch/io.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/oscring.h>
+
+void ring_powerinit(void)
+{
+ writel(0x18000a, RING_PWM_VCCK_A);/*set vcck 0.8v*/
+ writel(0x18000a, RING_PWM_VCCK_B);/*set vcck 0.8v*/
+ writel(0x8000a, RING_PWM_EE);/*set ee 0.8v*/
+}
+
+unsigned long clk_util_ring_msr(unsigned long clk_mux)
+{
+ unsigned int regval = 0;
+
+ writel(0, MSR_CLK_REG0);
+ /* Set the measurement gate to 64uS */
+ /* 64uS is enough for measure the frequence? */
+ setbits_le32(MSR_CLK_REG0, (10000 - 1));
+ /* Disable continuous measurement */
+ /* Disable interrupts */
+ clrbits_le32(MSR_CLK_REG0, (1 << 17) | (1 << 18));
+ clrbits_le32(MSR_CLK_REG0, 0x7f << 20);
+ setbits_le32(MSR_CLK_REG0, (clk_mux) << 20 | (1 << 19) | (1 << 16));
+ mdelay(10);
+ /* Wait for the measurement to be done */
+ regval = readl(MSR_CLK_REG0);
+ do {
+ regval = readl(MSR_CLK_REG0);
+ } while (regval & (1 << 31));
+
+ /* Disable measuring */
+ clrbits_le32(MSR_CLK_REG0, 1 << 16);
+ regval = (readl(MSR_CLK_REG2) + 31) & 0x000fffff;
+
+ return (regval / 10);
+}
+
+int ring_msr(int index)
+{
+ const char* clk_table[] = {
+ [32] = "am_ring_osc_clk_out[32] " ,
+ [31] = "am_ring_osc_clk_out[31] " ,
+ [30] = "am_ring_osc_clk_out[30] " ,
+ [29] = "am_ring_osc_clk_out[29] " ,
+ [28] = "am_ring_osc_clk_out[28] " ,
+ [27] = "am_ring_osc_clk_out[27] " ,
+ [26] = "am_ring_osc_clk_out[26] " ,
+ [25] = "am_ring_osc_clk_out[25] " ,
+ [24] = "am_ring_osc_clk_out[24] " ,
+ [23] = "am_ring_osc_clk_out[23] " ,
+ [22] = "am_ring_osc_clk_out[22] " ,
+ [21] = "am_ring_osc_clk_out[21] " ,
+ [20] = "am_ring_osc_clk_out[20] " ,
+ [19] = "am_ring_osc_clk_out[19] " ,
+ [18] = "am_ring_osc_clk_out[18] " ,
+ [17] = "am_ring_osc_clk_out[17] " ,
+ [16] = "am_ring_osc_clk_out[16] " ,
+ [15] = "am_ring_osc_clk_out[15] " ,
+ [14] = "am_ring_osc_clk_out[14] " ,
+ [13] = "am_ring_osc_clk_out[13] " ,
+ [12] = "am_ring_osc_clk_out[12] " ,
+ [11] = "am_ring_osc_clk_out[11] " ,
+ [10] = "am_ring_osc_clk_out[10] " ,
+ [9] = "am_ring_osc_clk_out[9] " ,
+ [8] = "am_ring_osc_clk_out[8] " ,
+ [7] = "am_ring_osc_clk_out[7] " ,
+ [6] = "am_ring_osc_clk_out[6] " ,
+ [5] = "am_ring_osc_clk_out[5] " ,
+ [4] = "am_ring_osc_clk_out[4] " ,
+ [3] = "am_ring_osc_clk_out[3] " ,
+ [2] = "am_ring_osc_clk_out[2] " ,
+ [1] = "am_ring_osc_clk_out[1] " ,
+ [0] = "am_ring_osc_clk_out[0] " ,
+ };
+ const int tb[] = {180, 181, 182, 183, 184, 185, 186, 187, 188, 189,
+ 190, 191, 192, 193, 194, 195, 196, 197, 198, 199,
+ 206, 207, 208, 209, 210, 211, 212, 213, 214, 215,
+ 216, 217, 218};
+ unsigned long i;
+ uint8_t efuseinfo[12] = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0};
+
+ if ((index != 0xff) && (index != 0)) {
+ if (bl31_get_cornerinfo(efuseinfo, sizeof(efuseinfo) / sizeof(uint8_t)) != 0) {
+ printf("fail get efuse info\n");
+ return 0;
+ }
+ if ((index >= 1) && (index <= 11))
+ printf("%d\n", efuseinfo[index]);
+ else
+ printf("input data not support!\n");
+
+ return 0;
+ }
+ if (0xff != index) {
+ ring_powerinit();
+ printf("set vcck vddee to 800mv\n");
+ }
+ /*RING_OSCILLATOR 0x7f: set slow ring*/
+ writel(OSCRING_CTL_DATA0, OSCRING_CTL_REG0);
+ writel(OSCRING_CTL_DATA1, OSCRING_CTL_REG1);
+ writel(OSCRING_CTL_DATA2, OSCRING_CTL_REG2);
+
+ for (i = 0; i < 33; i++) {
+ printf("%s :",clk_table[i]);
+ printf("%ld KHz",clk_util_ring_msr(tb[i]));
+ printf("\n");
+ }
+
+ if (bl31_get_cornerinfo(efuseinfo, sizeof(efuseinfo) / sizeof(uint8_t)) != 0) {
+ printf("fail get efuse info\n");
+ return 0;
+ }
+
+ printf("osc efuse info:\n");
+ for (i = 0; i < 10; i++)
+ printf("0x%x, ", efuseinfo[i]);
+ printf("0x%x, ", efuseinfo[11]);
+ printf("\n");
+
+ /*efuse to test value*/
+ printf("idd_ee, idd_cpu_a53, a53_osc_ring, idd_cpu_a73, a73_osc_ring, idd_nn, nna_osc_ring, idd_gpu, gpu_osc_ring, vpu_osc_ring\n");
+
+ printf("%d uA ", (efuseinfo[1] * 400));
+ printf("%d uA ", (efuseinfo[2] * 400));
+ printf("%d KHz ", (efuseinfo[3] * 20));
+ printf("%d uA ", (efuseinfo[4] * 400));
+ printf("%d KHz ", (efuseinfo[5] * 20));
+ printf("%d uA ", (efuseinfo[6] * 400));
+ printf("%d KHz ", (efuseinfo[7] * 20));
+ printf("%d uA ", (efuseinfo[8] * 400));
+ printf("%d KHz ", (efuseinfo[9] * 20));
+ printf("%d KHz ", (efuseinfo[11] * 20));
+
+ printf("\n");
+
+ return 0;
+}
diff --git a/arch/arm/mach-meson/t7/pinctrl_init.c b/arch/arm/mach-meson/t7/pinctrl_init.c
new file mode 100644
index 0000000..829ce28
--- /dev/null
+++ b/arch/arm/mach-meson/t7/pinctrl_init.c
@@ -0,0 +1,27 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm/uclass.h>
+#include <linux/err.h>
+#include <asm/arch/pinctrl_init.h>
+
+int pinctrl_devices_active(int pinctrl_num)
+{
+ int ret;
+ int idx;
+ struct udevice *pinctrl;
+
+ for (idx = 0; idx < pinctrl_num; idx++) {
+ ret = uclass_get_device(UCLASS_PINCTRL, idx, &pinctrl);
+ if (ret) {
+ debug("%s: failed to active pinctrl device [%d]",
+ __func__, idx);
+ return -EINVAL;
+ }
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-meson/t7/pll.c b/arch/arm/mach-meson/t7/pll.c
new file mode 100644
index 0000000..07b6bcc
--- /dev/null
+++ b/arch/arm/mach-meson/t7/pll.c
@@ -0,0 +1,635 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/io.h>
+#include <asm/arch/secure_apb.h>
+#include <../clk-pll.h>
+#include <linux/kernel.h>
+
+#define SECURE_PLL_CLK 0x82000098
+#define SECURE_CPU_CLK 0x82000099
+
+/* PLL secure clock index */
+enum sec_pll {
+ SECID_SYS0_DCO_PLL = 0,
+ SECID_SYS0_DCO_PLL_DIS,
+ SECID_SYS0_PLL_OD,
+ SECID_SYS1_DCO_PLL,
+ SECID_SYS1_DCO_PLL_DIS,
+ SECID_SYS1_PLL_OD,
+ SECID_CPU_CLK_SEL,
+ SECID_CPU_CLK_RD,
+ SECID_CPU_CLK_DYN,
+ SECID_A73_CLK_SEL,
+ SECID_A73_CLK_RD,
+ SECID_A73_CLK_DYN,
+};
+
+static const struct pll_params_table t7_sys_pll_table[] = {
+ PLL_PARAMS(67, 1, 1), /*DCO=1608M OD=804MM*/
+ PLL_PARAMS(133, 1, 1), /*DCO=3192M OD=1596MM*/
+ { /* sentinel */ }
+};
+
+static unsigned int t7_sys_pll_default_rate[] = {804, 1596};
+
+struct meson_clk_pll_data t7_sys_pll = {
+ .name = "sys0",
+ .en = {
+ .reg = ANACTRL_SYS0PLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg = ANACTRL_SYS0PLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg = ANACTRL_SYS0PLL_CTRL0,
+ .shift = 16,
+ .width = 5,
+ },
+ .od = {
+ .reg = ANACTRL_SYS0PLL_CTRL0,
+ .shift = 12,
+ .width = 3,
+ },
+ .def_rate = t7_sys_pll_default_rate,
+ .def_cnt = ARRAY_SIZE(t7_sys_pll_default_rate),
+ .table = t7_sys_pll_table,
+ .l = {
+ .reg = ANACTRL_SYS0PLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg = ANACTRL_SYS0PLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .smc_id = SECURE_PLL_CLK,
+ .secid_disable = SECID_SYS0_DCO_PLL_DIS,
+ .secid = SECID_SYS0_DCO_PLL,
+ .clkmsr_id = 172,
+ .clkmsr_div16_en = 1
+};
+
+struct meson_clk_pll_data t7_sys1_pll = {
+ .name = "sys1",
+ .en = {
+ .reg = ANACTRL_SYS1PLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg = ANACTRL_SYS1PLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg = ANACTRL_SYS1PLL_CTRL0,
+ .shift = 16,
+ .width = 5,
+ },
+ .od = {
+ .reg = ANACTRL_SYS1PLL_CTRL0,
+ .shift = 12,
+ .width = 3,
+ },
+ .def_rate = t7_sys_pll_default_rate,
+ .def_cnt = ARRAY_SIZE(t7_sys_pll_default_rate),
+ .table = t7_sys_pll_table,
+ .l = {
+ .reg = ANACTRL_SYS1PLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg = ANACTRL_SYS1PLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .smc_id = SECURE_PLL_CLK,
+ .secid_disable = SECID_SYS1_DCO_PLL_DIS,
+ .secid = SECID_SYS1_DCO_PLL,
+ .clkmsr_id = 6,
+ .clkmsr_div16_en = 1
+};
+
+static unsigned int t7_gp0_pll_default_rate[] = {1500, 750, 1152};
+
+/* set the od = 2, clkmsr can not measure 6000M */
+static const struct pll_params_table t7_gp0_pll_table[] = {
+ PLL_PARAMS(250, 1, 2), /* DCO = 6000M PLL = 1500M */
+ PLL_PARAMS(125, 1, 2), /* DCO = 3000M PLL = 750M */
+ PLL_PARAMS(192, 1, 2), /* DCO = 4608M PLL = 1152M */
+ { /* sentinel */ }
+};
+
+static const struct reg_sequence t7_gp0_init_regs[] = {
+ { .reg = ANACTRL_GP0PLL_CTRL0, .def = 0x080304fa },
+ { .reg = ANACTRL_GP0PLL_CTRL0, .def = 0x380304fa },
+ { .reg = ANACTRL_GP0PLL_CTRL1, .def = 0x00000000 },
+ { .reg = ANACTRL_GP0PLL_CTRL2, .def = 0x00000000 },
+ { .reg = ANACTRL_GP0PLL_CTRL3, .def = 0x48681c00 },
+ { .reg = ANACTRL_GP0PLL_CTRL4, .def = 0x88770290 },
+ { .reg = ANACTRL_GP0PLL_CTRL5, .def = 0x39272000 },
+ { .reg = ANACTRL_GP0PLL_CTRL6, .def = 0x56540000, .delay_us = 50 },
+ { .reg = ANACTRL_GP0PLL_CTRL0, .def = 0x180304fa, .delay_us = 50 }
+};
+
+struct meson_clk_pll_data t7_gp0_pll = {
+ .name = "gp0",
+ .en = {
+ .reg = ANACTRL_GP0PLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg = ANACTRL_GP0PLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg = ANACTRL_GP0PLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .od = {
+ .reg = ANACTRL_GP0PLL_CTRL0,
+ .shift = 16,
+ .width = 3,
+ },
+ .def_rate = t7_gp0_pll_default_rate,
+ .def_cnt = ARRAY_SIZE(t7_gp0_pll_default_rate),
+ .table = t7_gp0_pll_table,
+ .init_regs = t7_gp0_init_regs,
+ .init_count = ARRAY_SIZE(t7_gp0_init_regs),
+ .l = {
+ .reg = ANACTRL_GP0PLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg = ANACTRL_GP0PLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .clkmsr_id = 20,
+};
+
+static unsigned int t7_gp1_pll_default_rate[] = {1596, 804};
+
+static const struct pll_params_table t7_gp1_pll_table[] = {
+ PLL_PARAMS(133, 1, 1), /* DCO = 3192M PLL = 1596M */
+ PLL_PARAMS(67, 1, 1), /* DCO = 1608M PLL = 804M */
+ { /* sentinel */ }
+};
+
+static const struct reg_sequence t7_gp1_init_regs[] = {
+ { .reg = ANACTRL_GP1PLL_CTRL0, .def = 0x20011086 },
+ { .reg = ANACTRL_GP1PLL_CTRL0, .def = 0x30011086 },
+ { .reg = ANACTRL_GP1PLL_CTRL1, .def = 0x1420500f },
+ { .reg = ANACTRL_GP1PLL_CTRL2, .def = 0x00023041 },
+ { .reg = ANACTRL_GP1PLL_CTRL3, .def = 0x0, .delay_us = 20 },
+ { .reg = ANACTRL_GP1PLL_CTRL0, .def = 0x10011086, .delay_us = 20 },
+ { .reg = ANACTRL_GP1PLL_CTRL2, .def = 0x00023001, .delay_us = 50 },
+};
+
+struct meson_clk_pll_data t7_gp1_pll = {
+ .name = "gp1",
+ .en = {
+ .reg = ANACTRL_GP1PLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg = ANACTRL_GP1PLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg = ANACTRL_GP1PLL_CTRL0,
+ .shift = 16,
+ .width = 5,
+ },
+ .od = {
+ .reg = ANACTRL_GP1PLL_CTRL0,
+ .shift = 12,
+ .width = 3,
+ },
+ .def_rate = t7_gp1_pll_default_rate,
+ .def_cnt = ARRAY_SIZE(t7_gp1_pll_default_rate),
+ .table = t7_gp1_pll_table,
+ .init_regs = t7_gp1_init_regs,
+ .init_count = ARRAY_SIZE(t7_gp1_init_regs),
+ .l = {
+ .reg = ANACTRL_GP1PLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg = ANACTRL_GP1PLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .clkmsr_id = 21,
+};
+
+static unsigned int t7_mclk_pll_default_rate[] = {50};
+
+static const struct reg_sequence t7_mclk_init_regs[] = {
+ { .reg = ANACTRL_MCLK_PLL_CNTL0, .def = 0x20011064 },
+ { .reg = ANACTRL_MCLK_PLL_CNTL0, .def = 0x30011064 },
+ { .reg = ANACTRL_MCLK_PLL_CNTL1, .def = 0x0480500f },
+ { .reg = ANACTRL_MCLK_PLL_CNTL2, .def = 0x00023041 },
+ { .reg = ANACTRL_MCLK_PLL_CNTL3, .def = 0x18180000 },
+ { .reg = ANACTRL_MCLK_PLL_CNTL4, .def = 0x00180303, .delay_us = 20 },
+ { .reg = ANACTRL_MCLK_PLL_CNTL0, .def = 0x10011064, .delay_us = 20 },
+ { .reg = ANACTRL_MCLK_PLL_CNTL2, .def = 0x00023001, .delay_us = 50 },
+};
+
+struct meson_clk_pll_data t7_mclk_pll = {
+ .name = "mclk",
+ .en = {
+ .reg = ANACTRL_MCLK_PLL_CNTL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg = ANACTRL_MCLK_PLL_CNTL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg = ANACTRL_MCLK_PLL_CNTL0,
+ .shift = 16,
+ .width = 5,
+ },
+ .od = {
+ .reg = ANACTRL_MCLK_PLL_CNTL0,
+ .shift = 12,
+ .width = 3,
+ },
+ .def_rate = t7_mclk_pll_default_rate,
+ .def_cnt = ARRAY_SIZE(t7_mclk_pll_default_rate),
+ .init_regs = t7_mclk_init_regs,
+ .init_count = ARRAY_SIZE(t7_mclk_init_regs),
+ .l = {
+ .reg = ANACTRL_MCLK_PLL_CNTL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg = ANACTRL_MCLK_PLL_CNTL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .clkmsr_id = 171,
+};
+
+static unsigned int t7_pcie_default_rate[] = {100};
+
+static const struct reg_sequence t7_pcie_init_regs[] = {
+ { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x200c04c8 },
+ { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x300c04c8 },
+ { .reg = ANACTRL_PCIEPLL_CTRL1, .def = 0x30000000 },
+ { .reg = ANACTRL_PCIEPLL_CTRL2, .def = 0x00001100 },
+ { .reg = ANACTRL_PCIEPLL_CTRL3, .def = 0x10058e00 },
+ { .reg = ANACTRL_PCIEPLL_CTRL4, .def = 0x000100c0 },
+ { .reg = ANACTRL_PCIEPLL_CTRL5, .def = 0x68000040 },
+ { .reg = ANACTRL_PCIEPLL_CTRL5, .def = 0x68000060, .delay_us = 20 },
+ { .reg = ANACTRL_PCIEPLL_CTRL4, .def = 0x008100c0, .delay_us = 10 },
+ { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x340c04c8 },
+ { .reg = ANACTRL_PCIEPLL_CTRL0, .def = 0x140c04c8, .delay_us = 10 },
+ { .reg = ANACTRL_PCIEPLL_CTRL2, .def = 0x00001000 }
+};
+
+struct meson_clk_pll_data t7_pcie_pll = {
+ .name = "pcie",
+ .en = {
+ .reg = ANACTRL_PCIEPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .def_rate = t7_pcie_default_rate,
+ .def_cnt = ARRAY_SIZE(t7_pcie_default_rate),
+ .init_regs = t7_pcie_init_regs,
+ .init_count = ARRAY_SIZE(t7_pcie_init_regs),
+ .l = {
+ .reg = ANACTRL_PCIEPLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg = ANACTRL_PCIEPLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .clkmsr_id = 16,
+};
+
+static unsigned int t7_hifi_pll_default_rate[] = {1500, 750};
+
+/* set the od = 2, clkmsr can not measure 6000M */
+static const struct pll_params_table t7_hifi_pll_table[] = {
+ PLL_PARAMS(250, 1, 2), /* DCO = 6000M PLL = 1500M */
+ PLL_PARAMS(125, 1, 2), /* DCO = 3000M PLL = 750M */
+ { /* sentinel */ }
+};
+
+static const struct reg_sequence t7_hifi_init_regs[] = {
+ { .reg = ANACTRL_HIFIPLL_CTRL0, .def = 0x080304fa },
+ { .reg = ANACTRL_HIFIPLL_CTRL0, .def = 0x380304fa },
+ //{ .reg = ANACTRL_HIFIPLL_CTRL1, .def = 0x00010e56 },
+ { .reg = ANACTRL_HIFIPLL_CTRL2, .def = 0x00000000 },
+ { .reg = ANACTRL_HIFIPLL_CTRL3, .def = 0x6a285c00 },
+ { .reg = ANACTRL_HIFIPLL_CTRL4, .def = 0x65771290 },
+ { .reg = ANACTRL_HIFIPLL_CTRL5, .def = 0x39272000 },
+ { .reg = ANACTRL_HIFIPLL_CTRL6, .def = 0x56540000, .delay_us = 50 },
+ { .reg = ANACTRL_HIFIPLL_CTRL0, .def = 0X180304fa, .delay_us = 50 },
+};
+
+struct meson_clk_pll_data t7_hifi_pll = {
+ .name = "hifi",
+ .en = {
+ .reg = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 28,
+ .width = 1,
+ },
+ .m = {
+ .reg = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 0,
+ .width = 8,
+ },
+ .n = {
+ .reg = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 10,
+ .width = 5,
+ },
+ .frac = {
+ .reg = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 0,
+ .width = 19,
+ },
+ .od = {
+ .reg = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 16,
+ .width = 5,
+ },
+ .def_rate = t7_hifi_pll_default_rate,
+ .def_cnt = ARRAY_SIZE(t7_hifi_pll_default_rate),
+ .table = t7_hifi_pll_table,
+ .init_regs = t7_hifi_init_regs,
+ .init_count = ARRAY_SIZE(t7_hifi_init_regs),
+ .l = {
+ .reg = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 31,
+ .width = 1,
+ },
+ .rst = {
+ .reg = ANACTRL_HIFIPLL_CTRL0,
+ .shift = 29,
+ .width = 1,
+ },
+ .clkmsr_id = 19,
+};
+
+static unsigned int t7_mpll_default_rate[] = {166};
+static const struct reg_sequence t7_mpll0_init_regs[] = {
+ { .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 },
+ { .reg = ANACTRL_MPLL_CTRL2, .def = 0x40000033 },
+};
+
+struct meson_clk_mpll_data t7_mpll0 = {
+ .name = "mpll0",
+ .sdm = {
+ .reg = ANACTRL_MPLL_CTRL1,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg = ANACTRL_MPLL_CTRL1,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg = ANACTRL_MPLL_CTRL1,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg = ANACTRL_MPLL_CTRL1,
+ .shift = 29,
+ .width = 1,
+ },
+ .en = {
+ .reg = ANACTRL_MPLL_CTRL1,
+ .shift = 31,
+ .width = 1,
+ },
+ .init_regs = t7_mpll0_init_regs,
+ .init_count = ARRAY_SIZE(t7_mpll0_init_regs),
+ .def_rate = t7_mpll_default_rate,
+ .def_cnt = ARRAY_SIZE(t7_mpll_default_rate),
+ .clkmsr_id = 11
+};
+
+static const struct reg_sequence t7_mpll1_init_regs[] = {
+ { .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 },
+ { .reg = ANACTRL_MPLL_CTRL4, .def = 0x40000033 },
+};
+
+struct meson_clk_mpll_data t7_mpll1 = {
+ .name = "mpll1",
+ .sdm = {
+ .reg = ANACTRL_MPLL_CTRL3,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg = ANACTRL_MPLL_CTRL3,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg = ANACTRL_MPLL_CTRL3,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg = ANACTRL_MPLL_CTRL3,
+ .shift = 29,
+ .width = 1,
+ },
+ .en = {
+ .reg = ANACTRL_MPLL_CTRL3,
+ .shift = 31,
+ .width = 1,
+ },
+ .init_regs = t7_mpll1_init_regs,
+ .init_count = ARRAY_SIZE(t7_mpll1_init_regs),
+ .def_rate = t7_mpll_default_rate,
+ .def_cnt = ARRAY_SIZE(t7_mpll_default_rate),
+ .clkmsr_id = 12
+};
+
+static const struct reg_sequence t7_mpll2_init_regs[] = {
+ { .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 },
+ { .reg = ANACTRL_MPLL_CTRL6, .def = 0x40000033 },
+};
+
+struct meson_clk_mpll_data t7_mpll2 = {
+ .name = "mpll2",
+ .sdm = {
+ .reg = ANACTRL_MPLL_CTRL5,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg = ANACTRL_MPLL_CTRL5,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg = ANACTRL_MPLL_CTRL5,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg = ANACTRL_MPLL_CTRL5,
+ .shift = 29,
+ .width = 1,
+ },
+ .en = {
+ .reg = ANACTRL_MPLL_CTRL5,
+ .shift = 31,
+ .width = 1,
+ },
+ .init_regs = t7_mpll2_init_regs,
+ .init_count = ARRAY_SIZE(t7_mpll2_init_regs),
+ .def_rate = t7_mpll_default_rate,
+ .def_cnt = ARRAY_SIZE(t7_mpll_default_rate),
+ .clkmsr_id = 13
+};
+
+static const struct reg_sequence t7_mpll3_init_regs[] = {
+ { .reg = ANACTRL_MPLL_CTRL0, .def = 0x00000543 },
+ { .reg = ANACTRL_MPLL_CTRL8, .def = 0x40000033 },
+};
+
+struct meson_clk_mpll_data t7_mpll3 = {
+ .name = "mpll3",
+ .sdm = {
+ .reg = ANACTRL_MPLL_CTRL7,
+ .shift = 0,
+ .width = 14,
+ },
+ .sdm_en = {
+ .reg = ANACTRL_MPLL_CTRL7,
+ .shift = 30,
+ .width = 1,
+ },
+ .n2 = {
+ .reg = ANACTRL_MPLL_CTRL7,
+ .shift = 20,
+ .width = 9,
+ },
+ .ssen = {
+ .reg = ANACTRL_MPLL_CTRL7,
+ .shift = 29,
+ .width = 1,
+ },
+ .en = {
+ .reg = ANACTRL_MPLL_CTRL7,
+ .shift = 31,
+ .width = 1,
+ },
+ .init_regs = t7_mpll3_init_regs,
+ .init_count = ARRAY_SIZE(t7_mpll3_init_regs),
+ .def_rate = t7_mpll_default_rate,
+ .def_cnt = ARRAY_SIZE(t7_mpll_default_rate),
+ .clkmsr_id = 14
+};
+
+void meson_sys_pll_test(struct meson_clk_pll_data *pll, unsigned int cpu_dyn)
+{
+ struct arm_smccc_res res;
+
+ /* set fixed clk to 1G, Switch to fixed clk first */
+ arm_smccc_smc(SECURE_CPU_CLK, cpu_dyn,
+ 1, 0, 0, 0, 0, 0, &res);
+
+ meson_switch_cpu_clk(SECURE_CPU_CLK, SECID_A73_CLK_SEL, 0);
+
+ /* set sys pll rate */
+ meson_secure_pll_test(&t7_sys_pll);
+
+ /* Switch back to sys pll */
+ meson_switch_cpu_clk(SECURE_CPU_CLK, SECID_A73_CLK_SEL, 1);
+}
+
+void meson_plls_test(void)
+{
+ /* test sys0 pll */
+ meson_sys_pll_test(&t7_sys_pll, SECID_A73_CLK_DYN);
+ //meson_secure_pll_test(&t7_sys1_pll, SECID_CPU_CLK_DYN);
+
+ /* non secure pll */
+ meson_pll_test(&t7_gp0_pll);
+ meson_pll_test_one(&t7_pcie_pll);
+ meson_pll_test(&t7_hifi_pll);
+ meson_pll_test(&t7_gp1_pll);
+ meson_pll_test_one(&t7_mclk_pll);
+ /* mpll */
+ meson_mpll_test(&t7_mpll0);
+ meson_mpll_test(&t7_mpll1);
+ meson_mpll_test(&t7_mpll2);
+ meson_mpll_test(&t7_mpll3);
+
+ return;
+}
+
+struct meson_clk_pll_data *t7_pll_list[] = {
+ &t7_sys_pll,
+ &t7_sys1_pll,
+ &t7_gp0_pll,
+ &t7_hifi_pll,
+ &t7_gp1_pll,
+};
+
+struct meson_clk_mpll_data *t7_mpll_list[] = {
+ &t7_mpll0,
+ &t7_mpll1,
+ &t7_mpll2,
+ &t7_mpll3
+};
+
+int pll_test(int argc, char * const argv[])
+{
+ if (0 == strcmp("all", argv[1]))
+ meson_plls_test();
+ else if (0 == strcmp("sys0", argv[1])) {
+ meson_sys_pll_test(&t7_sys_pll, SECID_A73_CLK_DYN);
+ }
+ else if (0 == strcmp("sys1", argv[1])) {
+ meson_sys_pll_test(&t7_sys1_pll, SECID_CPU_CLK_DYN);
+ }
+ else if (0 == strcmp("pcie", argv[1])) {
+ meson_pll_test_one(&t7_pcie_pll);
+ }
+ else if (0 == strcmp("mclk", argv[1])) {
+ meson_pll_test_one(&t7_mclk_pll);
+ }
+ else {
+ one_pll_test(t7_pll_list, ARRAY_SIZE(t7_pll_list),
+ t7_mpll_list, ARRAY_SIZE(t7_mpll_list), argv[1]);
+ }
+
+ return 0;
+}
diff --git a/arch/arm/mach-meson/t7/power_cal.c b/arch/arm/mach-meson/t7/power_cal.c
new file mode 100644
index 0000000..e4f9c53
--- /dev/null
+++ b/arch/arm/mach-meson/t7/power_cal.c
@@ -0,0 +1,135 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/io.h>
+#include <amlogic/saradc.h>
+#include <asm/arch/mailbox.h>
+
+#define P_EE_TIMER_E (*((volatile unsigned *)(0xffd00000 + (0x3c62 << 2))))
+#define vcck_adc_channel 0x4
+#define ee_adc_channel 0x5
+#define default_ref_val 1800
+
+extern const int pwm_cal_voltage_table[][2];
+extern const int pwm_cal_voltage_table_ee[][2];
+extern int pwm_cal_voltage_table_size;
+extern int pwm_cal_voltage_table_ee_size;
+
+
+enum pwm_id {
+ pwm_vcck = 0,
+ pwm_ee,
+};
+
+unsigned int _get_time(void)
+{
+ return P_EE_TIMER_E;
+}
+
+void _udelay_(unsigned int us)
+{
+ unsigned int t0 = _get_time();
+
+ while (_get_time() - t0 <= us)
+ ;
+}
+
+int32_t aml_delt_get(int adc_val, unsigned int voltage)
+{
+ unsigned int adc_volt;
+ int32_t delt;
+ int32_t div = 10; /*10mv is min step*/
+
+ if (adc_val != -1) {
+ adc_volt = default_ref_val*adc_val/1024;
+ printf("aml pwm cal adc_val = %x, adc_voltage = %d, def_voltage = %d\n",
+ adc_val, adc_volt, voltage);
+ } else {
+ adc_volt = voltage;
+ printf("warning:aml pwm cal adc get voltage error\n");
+ return 0;
+ }
+ delt = voltage - adc_volt;
+ delt = delt / div;
+ return delt;
+}
+
+void aml_set_voltage(unsigned int id, unsigned int voltage, int delt)
+{
+ int to;
+
+ switch (id) {
+ case pwm_vcck:
+ for (to = 0; to < pwm_cal_voltage_table_size; to++) {
+ if (pwm_cal_voltage_table[to][1] >= voltage) {
+ break;
+ }
+ }
+ to +=delt;
+ if (to >= pwm_cal_voltage_table_size) {
+ to = pwm_cal_voltage_table_size - 1;
+ }
+ /*vcck volt set by dvfs and avs*/
+ //writel(pwm_voltage_table[to][0], PWM_PWM_A_ADRESS);
+ _udelay_(200);
+ break;
+
+ case pwm_ee:
+ for (to = 0; to < pwm_cal_voltage_table_ee_size; to++) {
+ if (pwm_cal_voltage_table_ee[to][1] >= voltage) {
+ break;
+ }
+ }
+ to +=delt;
+ if (to >= pwm_cal_voltage_table_ee_size) {
+ to = pwm_cal_voltage_table_ee_size - 1;
+ }
+ printf("aml pwm cal before ee_address: %x, ee_voltage: %x\n",
+ AO_PWM_PWM_B, readl(AO_PWM_PWM_B));
+ writel(pwm_cal_voltage_table_ee[to][0],AO_PWM_PWM_B);
+ _udelay_(1000);
+ printf("aml pwm cal after ee_address: %x, ee_voltage: %x\n",
+ AO_PWM_PWM_B, readl(AO_PWM_PWM_B));
+ break;
+ default:
+ break;
+ }
+ _udelay_(200);
+}
+
+int aml_cal_pwm(unsigned int ee_voltage, unsigned int vcck_voltage)
+{
+ int32_t ee_delt, vcck_delt;
+ unsigned int ee_val, vcck_val;
+ int ret;
+
+ /*txlx vcck ch4,vddee ch5*/
+ ret = adc_channel_single_shot_mode("adc", ADC_MODE_HIGH_PRECISION,
+ vcck_adc_channel, &vcck_val);
+ if (ret)
+ return ret;
+
+ ret = adc_channel_single_shot_mode("adc", ADC_MODE_HIGH_PRECISION,
+ ee_adc_channel, &ee_val);
+ if (ret)
+ return ret;
+
+ vcck_delt = aml_delt_get(vcck_val, vcck_voltage);
+ ee_delt = aml_delt_get(ee_val, ee_voltage);
+ send_pwm_delt(vcck_delt, ee_delt);
+ aml_set_voltage(pwm_ee, AML_VDDEE_INIT_VOLTAGE, ee_delt);
+ //aml_set_voltage(pwm_vcck, CONFIG_VCCK_INIT_VOLTAGE, vcck_delt);
+ printf("aml board pwm vcck: %x, ee: %x\n", vcck_delt, ee_delt);
+
+ return 0;
+}
+
+void aml_pwm_cal_init(int mode)
+{
+ printf("aml pwm cal init\n");
+ aml_cal_pwm(AML_VDDEE_INIT_VOLTAGE, AML_VCCK_INIT_VOLTAGE);
+}
diff --git a/arch/arm/mach-meson/t7/power_gate.h b/arch/arm/mach-meson/t7/power_gate.h
new file mode 100644
index 0000000..9ca1a9d
--- /dev/null
+++ b/arch/arm/mach-meson/t7/power_gate.h
@@ -0,0 +1,1161 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __POWER_MGR_HEADER_
+#define __POWER_MGR_HEADER_
+
+#include <asm/arch/io.h>
+#include <common.h>
+//#include <asm/arch-gxb/io.h>
+/* #include <asm/arch-gxb/register.h> */
+#include <asm/arch/secure_apb.h>
+/* clock gate control */
+
+#define DEBUG_MASK 0
+
+#define SET_CLK_GATE_MASK(reg, mask) __raw_writel((__raw_readl(reg)|mask), reg)
+#define CLEAR_CLK_GATE_MASK(reg, mask) \
+ __raw_writel((__raw_readl(reg)&(~mask)), reg)
+#define CLK_GATE_ON(_MOD) do { \
+ if (DEBUG_MASK) \
+ printf("on reg %24s before read :0x%x : 0x%x\n",\
+ GCLK_NAME_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ SET_CLK_GATE_MASK(GCLK_REG_##_MOD, \
+ (unsigned int)GCLK_MASK_##_MOD); \
+ if (DEBUG_MASK) \
+ printf("on reg %24s after read :0x%x : 0x%x\n",\
+ GCLK_NAME_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ } while (0)
+
+#define CLK_GATE_OFF(_MOD) do { \
+ if (DEBUG_MASK) \
+ printf("off reg[ %24s ][0x%08x]before read:0x%08x:0x%08x\n",\
+ GCLK_NAME_##_MOD, (int)GCLK_MASK_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ CLEAR_CLK_GATE_MASK(GCLK_REG_##_MOD, (unsigned int)GCLK_MASK_##_MOD);\
+ if (DEBUG_MASK)\
+ printf("off reg[ %24s ][0x%08x] read after:0x%08x:0x%08x\n",\
+ GCLK_NAME_##_MOD, \
+ (int)GCLK_MASK_##_MOD, \
+ (unsigned int)GCLK_REG_##_MOD, \
+ __raw_readl(GCLK_REG_##_MOD)); \
+ } while (0)
+
+#define IS_CLK_GATE_ON(_MOD) (__raw_readl(GCLK_REG_##_MOD) & (GCLK_MASK_##_MOD))
+#define GATE_INIT(_MOD) GCLK_ref[GCLK_IDX_##_MOD] = IS_CLK_GATE_ON(_MOD) ? 1 : 0
+
+#define GCLK_IDX_DDR 0
+#define GCLK_NAME_DDR "DDR"
+#define GCLK_DEV_DDR "CLKGATE_DDR"
+#define GCLK_REG_DDR (HHI_GCLK_MPEG0)
+#define GCLK_MASK_DDR (1<<0)
+
+#define GCLK_IDX_DOS 1
+#define GCLK_NAME_DOS "DOS"
+#define GCLK_DEV_DOS "CLKGATE_DOS"
+#define GCLK_REG_DOS (HHI_GCLK_MPEG0)
+#define GCLK_MASK_DOS (1<<1)
+
+#define GCLK_IDX_RESERVED0_0 2
+#define GCLK_NAME_RESERVED0_0 "RESERVED0_0"
+#define GCLK_DEV_RESERVED0_0 "CLKGATE_RESERVED0_0"
+#define GCLK_REG_RESERVED0_0 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_0 (1<<2)
+
+#define GCLK_IDX_RESERVED0_1 3
+#define GCLK_NAME_RESERVED0_1 "RESERVED0_1"
+#define GCLK_DEV_RESERVED0_1 "CLKGATE_RESERVED0_1"
+#define GCLK_REG_RESERVED0_1 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_1 (1<<3)
+
+/* #define GCLK_IDX_AHB_BRIDGE 4 */
+/* #define GCLK_NAME_AHB_BRIDGE "AHB_BRIDGE" */
+/* #define GCLK_DEV_AHB_BRIDGE "CLKGATE_AHB_BRIDGE" */
+/* #define GCLK_REG_AHB_BRIDGE (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_AHB_BRIDGE (1<<4) */
+
+#define GCLK_IDX_ISA 5
+#define GCLK_NAME_ISA "ISA"
+#define GCLK_DEV_ISA "CLKGATE_ISA"
+#define GCLK_REG_ISA (HHI_GCLK_MPEG0)
+#define GCLK_MASK_ISA (1<<5)
+
+/* NEW ADD */
+#define GCLK_IDX_PL310_CBUS 6
+#define GCLK_NAME_PL310_CBUS "PL310_CBUS"
+#define GCLK_DEV_PL310_CBUS "CLKGATE_PL310_CBUS"
+#define GCLK_REG_PL310_CBUS (HHI_GCLK_MPEG0)
+#define GCLK_MASK_PL310_CBUS (1<<6)
+
+#define GCLK_IDX_PERIPHS_TOP 7
+#define GCLK_NAME_PERIPHS_TOP "PERIPHS_TOP"
+#define GCLK_DEV_PERIPHS_TOP "CLKGATE_PERIPHS_TOP"
+#define GCLK_REG_PERIPHS_TOP (HHI_GCLK_MPEG0)
+#define GCLK_MASK_PERIPHS_TOP (1<<7)
+
+#define GCLK_IDX_SPICC 8
+#define GCLK_NAME_SPICC "SPICC"
+#define GCLK_DEV_SPICC "CLKGATE_SPICC"
+#define GCLK_REG_SPICC (HHI_GCLK_MPEG0)
+#define GCLK_MASK_SPICC (1<<8)
+
+#define GCLK_IDX_I2C 9
+#define GCLK_NAME_I2C "I2C"
+#define GCLK_DEV_I2C "CLKGATE_I2C"
+#define GCLK_REG_I2C (HHI_GCLK_MPEG0)
+#define GCLK_MASK_I2C (1<<9)
+
+#define GCLK_IDX_SAR_ADC 10
+#define GCLK_NAME_SAR_ADC "SAR_ADC"
+#define GCLK_DEV_SAR_ADC "CLKGATE_SAR_ADC"
+//#define GCLK_REG_SAR_ADC (HHI_SAR_CLK_CNTL) //no HHI_SAR_CLK_CNTL on TXL
+#define GCLK_REG_SAR_ADC (AO_SAR_CLK)
+#define GCLK_MASK_SAR_ADC (1<<8)
+
+#define GCLK_IDX_SMART_CARD_MPEG_DOMAIN 11
+#define GCLK_NAME_SMART_CARD_MPEG_DOMAIN "SMART_CARD_MPEG_DOMAIN"
+#define GCLK_DEV_SMART_CARD_MPEG_DOMAIN "CLKGATE_SMART_CARD_MPEG_DOMAIN"
+#define GCLK_REG_SMART_CARD_MPEG_DOMAIN (HHI_GCLK_MPEG0)
+#define GCLK_MASK_SMART_CARD_MPEG_DOMAIN (1<<11)
+
+#define GCLK_IDX_RANDOM_NUM_GEN 12
+#define GCLK_NAME_RANDOM_NUM_GEN "RANDOM_NUM_GEN"
+#define GCLK_DEV_RANDOM_NUM_GEN "CLKGATE_RANDOM_NUM_GEN"
+#define GCLK_REG_RANDOM_NUM_GEN (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RANDOM_NUM_GEN (1<<12)
+
+#define GCLK_IDX_UART0 13
+#define GCLK_NAME_UART0 "UART0"
+#define GCLK_DEV_UART0 "CLKGATE_UART0"
+#define GCLK_REG_UART0 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_UART0 (1<<13)
+
+/* gxb no this clock gate */
+/* #define GCLK_IDX_SDHC 14 */
+/* #define GCLK_NAME_SDHC "SDHC" */
+/* #define GCLK_DEV_SDHC "CLKGATE_SDHC" */
+/* #define GCLK_REG_SDHC (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_SDHC (1<<14) */
+
+#define GCLK_IDX_STREAM 15
+#define GCLK_NAME_STREAM "STREAM"
+#define GCLK_DEV_STREAM "CLKGATE_STREAM"
+#define GCLK_REG_STREAM (HHI_GCLK_MPEG0)
+#define GCLK_MASK_STREAM (1<<15)
+
+#define GCLK_IDX_ASYNC_FIFO 16
+#define GCLK_NAME_ASYNC_FIFO "ASYNC_FIFO"
+#define GCLK_DEV_ASYNC_FIFO "CLKGATE_ASYNC_FIFO"
+#define GCLK_REG_ASYNC_FIFO (HHI_GCLK_MPEG0)
+#define GCLK_MASK_ASYNC_FIFO (1<<16)
+
+/* gxb no this clock gate */
+/* #define GCLK_IDX_SDIO 17 */
+/* #define GCLK_NAME_SDIO "SDIO" */
+/* #define GCLK_DEV_SDIO "CLKGATE_SDIO" */
+/* #define GCLK_REG_SDIO (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_SDIO (1<<17) */
+
+/* gxb no this clock gate */
+/* #define GCLK_IDX_AUD_BUF 18 */
+/* #define GCLK_NAME_AUD_BUF "AUD_BUF" */
+/* #define GCLK_DEV_AUD_BUF "CLKGATE_AUD_BUF" */
+/* #define GCLK_REG_AUD_BUF (HHI_GCLK_MPEG0) */
+/* #define GCLK_MASK_AUD_BUF (1<<18) */
+
+#define GCLK_IDX_HIU_PARSER 19
+#define GCLK_NAME_HIU_PARSER "HIU_PARSER"
+#define GCLK_DEV_HIU_PARSER "CLKGATE_HIU_PARSER"
+#define GCLK_REG_HIU_PARSER (HHI_GCLK_MPEG0)
+#define GCLK_MASK_HIU_PARSER (1<<19)
+
+#define GCLK_IDX_RESERVED0_2 20
+#define GCLK_NAME_RESERVED0_2 "RESERVED0_2"
+#define GCLK_DEV_RESERVED0_2 "CLKGATE_RESERVED0_2"
+#define GCLK_REG_RESERVED0_2 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_2 (1<<20)
+
+/* NEW ADD */
+#define GCLK_IDX_RESERVED0_3 21
+#define GCLK_NAME_RESERVED0_3 "RESERVED0_3 "
+#define GCLK_DEV_RESERVED0_3 "CLKGATE_RESERVED0_3 "
+#define GCLK_REG_RESERVED0_3 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_3 (1<<21)
+
+#define GCLK_IDX_RESERVED0_4 22
+#define GCLK_NAME_RESERVED0_4 "RESERVED0_4"
+#define GCLK_DEV_RESERVED0_4 "CLKGATE_RESERVED0_4"
+#define GCLK_REG_RESERVED0_4 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_4 (1<<22)
+
+#define GCLK_IDX_ASSIST_MISC 23
+#define GCLK_NAME_ASSIST_MISC "ASSIST_MISC"
+#define GCLK_DEV_ASSIST_MISC "CLKGATE_ASSIST_MISC"
+#define GCLK_REG_ASSIST_MISC (HHI_GCLK_MPEG0)
+#define GCLK_MASK_ASSIST_MISC (1<<23)
+
+
+#define GCLK_IDX_EMMC_A 24
+#define GCLK_NAME_EMMC_A "EMMC_A"
+#define GCLK_DEV_EMMC_A "CLKGATE_EMMC_A"
+#define GCLK_REG_EMMC_A (HHI_GCLK_MPEG0)
+#define GCLK_MASK_EMMC_A (1<<24)
+
+#define GCLK_IDX_EMMC_B 25
+#define GCLK_NAME_EMMC_B "EMMC_B"
+#define GCLK_DEV_EMMC_B "CLKGATE_EMMC_B"
+#define GCLK_REG_EMMC_B (HHI_GCLK_MPEG0)
+#define GCLK_MASK_EMMC_B (1<<25)
+
+#define GCLK_IDX_EMMC_C 26
+#define GCLK_NAME_EMMC_C "EMMC_C"
+#define GCLK_DEV_EMMC_C "CLKGATE_EMMC_C"
+#define GCLK_REG_EMMC_C (HHI_GCLK_MPEG0)
+#define GCLK_MASK_EMMC_C (1<<26)
+
+#define GCLK_IDX_RESERVED0_8 27
+#define GCLK_NAME_RESERVED0_8 "RESERVED0_8"
+#define GCLK_DEV_RESERVED0_8 "CLKGATE_RESERVED0_8"
+#define GCLK_REG_RESERVED0_8 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_8 (1<<27)
+
+#define GCLK_IDX_RESERVED0_9 28
+#define GCLK_NAME_RESERVED0_9 "RESERVED0_9"
+#define GCLK_DEV_RESERVED0_9 "CLKGATE_RESERVED0_9"
+#define GCLK_REG_RESERVED0_9 (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_9 (1<<28)
+
+#define GCLK_IDX_RESERVED0_A 29
+#define GCLK_NAME_RESERVED0_A "RESERVED0_A"
+#define GCLK_DEV_RESERVED0_A "CLKGATE_RESERVED0_A"
+#define GCLK_REG_RESERVED0_A (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_A (1<<29)
+
+#define GCLK_IDX_SPI 30
+#define GCLK_NAME_SPI "SPI"
+#define GCLK_DEV_SPI "CLKGATE_SPI"
+#define GCLK_REG_SPI (HHI_GCLK_MPEG0)
+#define GCLK_MASK_SPI (1<<30)
+
+#define GCLK_IDX_RESERVED0_B 31
+#define GCLK_NAME_RESERVED0_B "RESERVED0_B"
+#define GCLK_DEV_RESERVED0_B "CLKGATE_RESERVED0_B"
+#define GCLK_REG_RESERVED0_B (HHI_GCLK_MPEG0)
+#define GCLK_MASK_RESERVED0_B (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_RESERVED1_1 32
+#define GCLK_NAME_RESERVED1_1 "RESERVED1_1"
+#define GCLK_DEV_RESERVED1_1 "CLKGATE_RESERVED1_1"
+#define GCLK_REG_RESERVED1_1 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_1 (1<<0)
+
+
+#define GCLK_IDX_RESERVED1_2 33
+#define GCLK_NAME_RESERVED1_2 "RESERVED1_2"
+#define GCLK_DEV_RESERVED1_2 "CLKGATE_RESERVED1_2"
+#define GCLK_REG_RESERVED1_2 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_2 (1<<1)
+
+
+#define GCLK_IDX_AUD_IN 34
+#define GCLK_NAME_AUD_IN "AUD_IN"
+#define GCLK_DEV_AUD_IN "CLKGATE_AUD_IN"
+#define GCLK_REG_AUD_IN (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AUD_IN (1<<2)
+
+#define GCLK_IDX_ETHERNET 35
+#define GCLK_NAME_ETHERNET "ETHERNET"
+#define GCLK_DEV_ETHERNET "CLKGATE_ETHERNET"
+#define GCLK_REG_ETHERNET (HHI_GCLK_MPEG1)
+#define GCLK_MASK_ETHERNET (1<<3)
+
+/* g12a no reg */
+#if 0
+#define GCLK_IDX_ETH_CLK 145
+#define GCLK_NAME_ETH_CLK "ETH_CLK"
+#define GCLK_REG_ETH_CLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_ETH_CLK (1<<3)
+#endif
+
+#define GCLK_IDX_DEMUX 36
+#define GCLK_NAME_DEMUX "DEMUX"
+#define GCLK_DEV_DEMUX "CLKGATE_DEMUX"
+#define GCLK_REG_DEMUX (HHI_GCLK_MPEG1)
+#define GCLK_MASK_DEMUX (1<<4)
+
+#define GCLK_IDX_RESERVED1_3 37
+#define GCLK_NAME_RESERVED1_3 "RESERVED1_3"
+#define GCLK_DEV_RESERVED1_3 "CLKGATE_RESERVED1_3"
+#define GCLK_REG_RESERVED1_3 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_3 (1<<5)
+
+#define GCLK_IDX_AIU_AI_TOP_GLUE 38
+#define GCLK_NAME_AIU_AI_TOP_GLUE "AIU_AI_TOP_GLUE"
+#define GCLK_DEV_AIU_AI_TOP_GLUE "CLKGATE_AIU_AI_TOP_GLUE"
+#define GCLK_REG_AIU_AI_TOP_GLUE (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AI_TOP_GLUE (1<<6)
+
+#define GCLK_IDX_AIU_IEC958 39
+#define GCLK_NAME_AIU_IEC958 "AIU_IEC958"
+#define GCLK_DEV_AIU_IEC958 "CLKGATE_AIU_IEC958"
+#define GCLK_REG_AIU_IEC958 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_IEC958 (1<<7)
+
+#define GCLK_IDX_AIU_I2S_OUT 40
+#define GCLK_NAME_AIU_I2S_OUT "AIU_I2S_OUT"
+#define GCLK_DEV_AIU_I2S_OUT "CLKGATE_AIU_I2S_OUT"
+#define GCLK_REG_AIU_I2S_OUT (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_I2S_OUT (1<<8)
+
+#define GCLK_IDX_AIU_AMCLK_MEASURE 41
+#define GCLK_NAME_AIU_AMCLK_MEASURE "AIU_AMCLK_MEASURE"
+#define GCLK_DEV_AIU_AMCLK_MEASURE "CLKGATE_AIU_AMCLK_MEASURE"
+#define GCLK_REG_AIU_AMCLK_MEASURE (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AMCLK_MEASURE (1<<9)
+
+#define GCLK_IDX_AIU_AIFIFO2 42
+#define GCLK_NAME_AIU_AIFIFO2 "AIU_AIFIFO2"
+#define GCLK_DEV_AIU_AIFIFO2 "CLKGATE_AIU_AIFIFO2"
+#define GCLK_REG_AIU_AIFIFO2 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AIFIFO2 (1<<10)
+
+#define GCLK_IDX_AIU_AUD_MIXER 43
+#define GCLK_NAME_AIU_AUD_MIXER "AIU_AUD_MIXER"
+#define GCLK_DEV_AIU_AUD_MIXER "CLKGATE_AIU_AUD_MIXER"
+#define GCLK_REG_AIU_AUD_MIXER (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_AUD_MIXER (1<<11)
+
+#define GCLK_IDX_AIU_MIXER_REG 44
+#define GCLK_NAME_AIU_MIXER_REG "AIU_MIXER_REG"
+#define GCLK_DEV_AIU_MIXER_REG "CLKGATE_AIU_MIXER_REG"
+#define GCLK_REG_AIU_MIXER_REG (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_MIXER_REG (1<<12)
+
+#define GCLK_IDX_AIU_ADC 45
+#define GCLK_NAME_AIU_ADC "AIU_ADC"
+#define GCLK_DEV_AIU_ADC "CLKGATE_AIU_ADC"
+#define GCLK_REG_AIU_ADC (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_ADC (1<<13)
+
+#define GCLK_IDX_BLK_MOV 46
+#define GCLK_NAME_BLK_MOV "BLK_MOV"
+#define GCLK_DEV_BLK_MOV "CLKGATE_BLK_MOV"
+#define GCLK_REG_BLK_MOV (HHI_GCLK_MPEG1)
+#define GCLK_MASK_BLK_MOV (1<<14)
+
+/* NEW ADD */
+#define GCLK_IDX_AIU_TOP_LEVEL 47
+#define GCLK_NAME_AIU_TOP_LEVEL "AIU_TOP_LEVEL"
+#define GCLK_DEV_AIU_TOP_LEVEL "CLKGATE_AIU_TOP_LEVEL"
+#define GCLK_REG_AIU_TOP_LEVEL (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AIU_TOP_LEVEL (1<<15)
+
+//g12a no reg
+#if 0
+#define GCLK_NAME_PCM_MCLK "PCM_MCLK"
+#define GCLK_REG_PCM_MCLK (HHI_PCM_CLK_CNTL)
+#define GCLK_MASK_PCM_MCLK (1<<9)
+
+#define GCLK_NAME_PCM_SCLK "PCM_SCLK"
+#define GCLK_REG_PCM_SCLK (HHI_PCM_CLK_CNTL)
+#define GCLK_MASK_PCM_SCLK (1<<22)
+#endif
+
+#define GCLK_IDX_UART1 48
+#define GCLK_NAME_UART1 "UART1"
+#define GCLK_DEV_UART1 "CLKGATE_UART1"
+#define GCLK_REG_UART1 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_UART1 (1<<16)
+
+#define GCLK_IDX_RESERVED1_4 49
+#define GCLK_NAME_RESERVED1_4 "RESERVED1_4"
+#define GCLK_DEV_RESERVED1_4 "CLKGATE_RESERVED1_4"
+#define GCLK_REG_RESERVED1_4 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_4 (1<<17)
+
+/* NEW ADD */
+#define GCLK_IDX_RESERVED1_5 50
+#define GCLK_NAME_RESERVED1_5 "RESERVED1_5"
+#define GCLK_DEV_RESERVED1_5 "CLKGATE_RESERVED1_5"
+#define GCLK_REG_RESERVED1_5 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_5 (1<<18)
+
+#define GCLK_IDX_RESERVED1_6 51
+#define GCLK_NAME_RESERVED1_6 "RESERVED1_6"
+#define GCLK_DEV_RESERVED1_6 "CLKGATE_RESERVED1_6"
+#define GCLK_REG_RESERVED1_6 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_6 (1<<19)
+
+#define GCLK_IDX_GE2D 52
+#define GCLK_NAME_GE2D "GE2D"
+#define GCLK_DEV_GE2D "CLKGATE_GE2D"
+#define GCLK_REG_GE2D (HHI_GCLK_MPEG1)
+#define GCLK_MASK_GE2D (1<<20)
+
+#define GCLK_IDX_USB0 53
+#define GCLK_NAME_USB0 "USB0"
+#define GCLK_DEV_USB0 "CLKGATE_USB0"
+#define GCLK_REG_USB0 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_USB0 (1<<21)
+
+#define GCLK_IDX_USB1 54
+#define GCLK_NAME_USB1 "USB1"
+#define GCLK_DEV_USB1 "CLKGATE_USB1"
+#define GCLK_REG_USB1 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_USB1 (1<<22)
+
+#define GCLK_IDX_RESET 55
+#define GCLK_NAME_RESET "RESET"
+#define GCLK_DEV_RESET "CLKGATE_RESET"
+#define GCLK_REG_RESET (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESET (1<<23)
+
+#define GCLK_IDX_NAND_CLK 56
+#define GCLK_NAME_NAND_CLK "NAND CLK"
+#define GCLK_DEV_NAND_CLK "HHI_NAND_CLK"
+#define GCLK_REG_NAND_CLK (HHI_NAND_CLK_CNTL)
+#define GCLK_MASK_NAND_CLK (1<<7)
+
+#define GCLK_IDX_HIU_PARSER_TOP 57
+#define GCLK_NAME_HIU_PARSER_TOP "HIU_PARSER_TOP"
+#define GCLK_DEV_HIU_PARSER_TOP "CLKGATE_HIU_PARSER_TOP"
+#define GCLK_REG_HIU_PARSER_TOP (HHI_GCLK_MPEG1)
+#define GCLK_MASK_HIU_PARSER_TOP (1<<25)
+
+/* NEW ADD */
+
+/* g12a no reg */
+#if 0
+#define GCLK_NAME_USB_CLK "USB_CLK"
+#define GCLK_REG_USB_CLK (HHI_USB_CLK_CNTL)
+#define GCLK_MASK_USB_CLK (1<<9)
+#endif
+
+#define GCLK_IDX_USB_GENERAL 58
+#define GCLK_NAME_USB_GENERAL "USB_GENERAL"
+#define GCLK_DEV_USB_GENERAL "CLKGATE_USB_GENERAL"
+#define GCLK_REG_USB_GENERAL (HHI_GCLK_MPEG1)
+#define GCLK_MASK_USB_GENERAL (1<<26)
+
+#define GCLK_IDX_RESERVED1_7 59
+#define GCLK_NAME_RESERVED1_7 "RESERVED1_7"
+#define GCLK_DEV_RESERVED1_7 "CLKGATE_RESERVED1_7"
+#define GCLK_REG_RESERVED1_7 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_RESERVED1_7 (1<<27)
+
+/* #define GCLK_IDX_VDIN1 60 */
+/* #define GCLK_NAME_VDIN1 "VDIN1" */
+/* #define GCLK_DEV_VDIN1 "CLKGATE_VDIN1" */
+/* #define GCLK_REG_VDIN1 (HHI_GCLK_MPEG1) */
+/* #define GCLK_MASK_VDIN1 (1<<28) */
+
+#define GCLK_IDX_AHB_ARB0 61
+#define GCLK_NAME_AHB_ARB0 "AHB_ARB0"
+#define GCLK_DEV_AHB_ARB0 "CLKGATE_AHB_ARB0"
+#define GCLK_REG_AHB_ARB0 (HHI_GCLK_MPEG1)
+#define GCLK_MASK_AHB_ARB0 (1<<29)
+
+#define GCLK_IDX_EFUSE 62
+#define GCLK_NAME_EFUSE "EFUSE"
+#define GCLK_DEV_EFUSE "CLKGATE_EFUSE"
+#define GCLK_REG_EFUSE (HHI_GCLK_MPEG1)
+#define GCLK_MASK_EFUSE (1<<30)
+
+#define GCLK_IDX_ROM_CLK 63
+#define GCLK_NAME_ROM_CLK "ROM_CLK"
+#define GCLK_DEV_ROM_CLK "CLKGATE_ROM_CLK"
+#define GCLK_REG_ROM_CLK (HHI_GCLK_MPEG1)
+#define GCLK_MASK_ROM_CLK (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_RESERVED2_0 64
+#define GCLK_NAME_RESERVED2_0 "RESERVED2_0"
+#define GCLK_DEV_RESERVED2_0 "CLKGATE_RESERVED2_0"
+#define GCLK_REG_RESERVED2_0 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_0 (1<<0)
+
+#define GCLK_IDX_AHB_DATA_BUS 65
+#define GCLK_NAME_AHB_DATA_BUS "AHB_DATA_BUS"
+#define GCLK_DEV_AHB_DATA_BUS "CLKGATE_AHB_DATA_BUS"
+#define GCLK_REG_AHB_DATA_BUS (HHI_GCLK_MPEG2)
+#define GCLK_MASK_AHB_DATA_BUS (1<<1)
+
+#define GCLK_IDX_AHB_CONTROL_BUS 66
+#define GCLK_NAME_AHB_CONTROL_BUS "AHB_CONTROL_BUS"
+#define GCLK_DEV_AHB_CONTROL_BUS "CLKGATE_AHB_CONTROL_BUS"
+#define GCLK_REG_AHB_CONTROL_BUS (HHI_GCLK_MPEG2)
+#define GCLK_MASK_AHB_CONTROL_BUS (1<<2)
+
+#define GCLK_IDX_HDMI_INTR_SYNC 67
+#define GCLK_NAME_HDMI_INTR_SYNC "HDMI_INTR_SYNC"
+#define GCLK_DEV_HDMI_INTR_SYNC "CLKGATE_HDMI_INTR_SYNC"
+#define GCLK_REG_HDMI_INTR_SYNC (HHI_GCLK_MPEG2)
+#define GCLK_MASK_HDMI_INTR_SYNC (1<<3)
+
+#define GCLK_IDX_HDMI_PCLK 68
+#define GCLK_NAME_HDMI_PCLK "HDMI_PCLK"
+#define GCLK_DEV_HDMI_PCLK "CLKGATE_HDMI_PCLK"
+#define GCLK_REG_HDMI_PCLK (HHI_GCLK_MPEG2)
+#define GCLK_MASK_HDMI_PCLK (1<<4)
+
+#define GCLK_IDX_PDM 69
+#define GCLK_NAME_PDM "PDM"
+#define GCLK_DEV_PDM "CLKGATE_PDM"
+#define GCLK_REG_PDM (HHI_GCLK_MPEG2)
+#define GCLK_MASK_PDM (1<<5)
+
+#define GCLK_IDX_BT656 70
+#define GCLK_NAME_BT656 "BT656"
+#define GCLK_DEV_BT656 "CLKGATE_BT656"
+#define GCLK_REG_BT656 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_BT656 (1<<6)
+
+#define GCLK_IDX_BT656_2 71
+#define GCLK_NAME_BT656_2 "BT656_2"
+#define GCLK_DEV_BT656_2 "CLKGATE_BT656_2"
+#define GCLK_REG_BT656_2 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_BT656_2 (1<<7)
+
+#define GCLK_IDX_MISC_USB1_TO_DDR 72
+#define GCLK_NAME_MISC_USB1_TO_DDR "MISC_USB1_TO_DDR"
+#define GCLK_DEV_MISC_USB1_TO_DDR "CLKGATE_MISC_USB1_TO_DDR"
+#define GCLK_REG_MISC_USB1_TO_DDR (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MISC_USB1_TO_DDR (1<<8)
+
+#define GCLK_IDX_MISC_USB0_TO_DDR 73
+#define GCLK_NAME_MISC_USB0_TO_DDR "MISC_USB0_TO_DDR"
+#define GCLK_DEV_MISC_USB0_TO_DDR "CLKGATE_MISC_USB0_TO_DDR"
+#define GCLK_REG_MISC_USB0_TO_DDR (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MISC_USB0_TO_DDR (1<<9)
+
+#define GCLK_IDX_RESERVED2_4 74
+#define GCLK_NAME_RESERVED2_4 "RESERVED2_4"
+#define GCLK_DEV_RESERVED2_4 "CLKGATE_RESERVED2_4"
+#define GCLK_REG_RESERVED2_4 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_4 (1<<10)
+
+#define GCLK_IDX_MMC_PCLK 75
+#define GCLK_NAME_MMC_PCLK "MMC_PCLK"
+#define GCLK_DEV_MMC_PCLK "CLKGATE_MMC_PCLK"
+#define GCLK_REG_MMC_PCLK (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MMC_PCLK (1<<11)
+
+//g12a no reg
+#if 0
+#define GCLK_NAME_MMC_A_PCLK "MMC_A_PCLK"
+#define GCLK_REG_MMC_A_PCLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_MMC_A_PCLK (1<<2)
+
+#define GCLK_NAME_MMC_B_PCLK "MMC_B_PCLK"
+#define GCLK_REG_MMC_B_PCLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_MMC_B_PCLK (1<<1)
+
+#define GCLK_NAME_MMC_C_PCLK "MMC_C_PCLK"
+#define GCLK_REG_MMC_C_PCLK (HHI_MPLL_CNTL10)
+#define GCLK_MASK_MMC_C_PCLK (1<<0)
+#endif
+
+#define GCLK_NAME_EMMC_A_CLK "EMMC_A_CLK"
+#define GCLK_REG_EMMC_A_CLK (HHI_SD_EMMC_CLK_CNTL)
+#define GCLK_MASK_EMMC_A_CLK (1<<7)
+
+#define GCLK_NAME_EMMC_B_CLK "EMMC_B_CLK"
+#define GCLK_REG_EMMC_B_CLK (HHI_SD_EMMC_CLK_CNTL)
+#define GCLK_MASK_EMMC_B_CLK (1<<23)
+
+#define GCLK_IDX_MISC_DVIN 76
+#define GCLK_NAME_MISC_DVIN "MISC_DVIN"
+#define GCLK_DEV_MISC_DVIN "CLKGATE_MISC_DVIN"
+#define GCLK_REG_MISC_DVIN (HHI_GCLK_MPEG2)
+#define GCLK_MASK_MISC_DVIN (1<<12)
+
+#define GCLK_IDX_RESERVED2_5 77
+#define GCLK_NAME_RESERVED2_5 "RESERVED2_5"
+#define GCLK_DEV_RESERVED2_5 "CLKGATE_RESERVED2_5"
+#define GCLK_REG_RESERVED2_5 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_5 (1<<13)
+
+#define GCLK_IDX_RESERVED2_6 78
+#define GCLK_NAME_RESERVED2_6 "RESERVED2_6"
+#define GCLK_DEV_RESERVED2_6 "CLKGATE_RESERVED2_6"
+#define GCLK_REG_RESERVED2_6 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_6 (1<<14)
+
+#define GCLK_IDX_UART2 79
+#define GCLK_NAME_UART2 "UART2"
+#define GCLK_DEV_UART2 "CLKGATE_UART2"
+#define GCLK_REG_UART2 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_UART2 (1<<15)
+
+#define GCLK_IDX_RESERVED2_7 80
+#define GCLK_NAME_RESERVED2_7 "RESERVED2_7"
+#define GCLK_DEV_RESERVED2_7 "CLKGATE_RESERVED2_7"
+#define GCLK_REG_RESERVED2_7 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_7 (1<<16)
+
+#define GCLK_IDX_RESERVED2_8 81
+#define GCLK_NAME_RESERVED2_8 "RESERVED2_8"
+#define GCLK_DEV_RESERVED2_8 "CLKGATE_RESERVED2_8"
+#define GCLK_REG_RESERVED2_8 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_8 (1<<17)
+
+#define GCLK_IDX_RESERVED2_9 82
+#define GCLK_NAME_RESERVED2_9 "RESERVED2_9"
+#define GCLK_DEV_RESERVED2_9 "CLKGATE_RESERVED2_9"
+#define GCLK_REG_RESERVED2_9 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_9 (1<<18)
+
+#define GCLK_IDX_RESERVED2_A 83
+#define GCLK_NAME_RESERVED2_A "RESERVED2_A"
+#define GCLK_DEV_RESERVED2_A "CLKGATE_RESERVED2_A"
+#define GCLK_REG_RESERVED2_A (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_A (1<<19)
+
+#define GCLK_IDX_RESERVED2_B 84
+#define GCLK_NAME_RESERVED2_B "RESERVED2_B"
+#define GCLK_DEV_RESERVED2_B "CLKGATE_RESERVED2_B"
+#define GCLK_REG_RESERVED2_B (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_B (1<<20)
+
+#define GCLK_IDX_UART3 85
+#define GCLK_NAME_UART3 "UART3"
+#define GCLK_DEV_UART3 "CLKGATE_UART3"
+#define GCLK_REG_UART3 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_UART3 (1<<21)
+
+#define GCLK_IDX_SANA 86
+#define GCLK_NAME_SANA "SANA"
+#define GCLK_DEV_SANA "CLKGATE_SANA"
+#define GCLK_REG_SANA (HHI_GCLK_MPEG2)
+#define GCLK_MASK_SANA (1<<22)
+
+#define GCLK_IDX_RESERVED2_D 87
+#define GCLK_NAME_RESERVED2_D "RESERVED2_D"
+#define GCLK_DEV_RESERVED2_D "CLKGATE_RESERVED2_D"
+#define GCLK_REG_RESERVED2_D (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_D (1<<23)
+
+#define GCLK_IDX_RESERVED2_E 88
+#define GCLK_NAME_RESERVED2_E "RESERVED2_E"
+#define GCLK_DEV_RESERVED2_E "CLKGATE_RESERVED2_E"
+#define GCLK_REG_RESERVED2_E (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_E (1<<24)
+
+#define GCLK_IDX_VPU_INTR 89
+#define GCLK_NAME_VPU_INTR "VPU_INTR"
+#define GCLK_DEV_VPU_INTR "CLKGATE_VPU_INTR"
+#define GCLK_REG_VPU_INTR (HHI_GCLK_MPEG2)
+#define GCLK_MASK_VPU_INTR (1<<25)
+
+#define GCLK_IDX_SECURE_AHP_APB3 90
+#define GCLK_NAME_SECURE_AHP_APB3 "SECURE_AHP_APB3"
+#define GCLK_DEV_SECURE_AHP_APB3 "CLKGATE_SECURE_AHP_APB3"
+#define GCLK_REG_SECURE_AHP_APB3 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_SECURE_AHP_APB3 (1<<26)
+
+#define GCLK_IDX_RESERVED2_F 91
+#define GCLK_NAME_RESERVED2_F "RESERVED2_F"
+#define GCLK_DEV_RESERVED2_F "CLKGATE_RESERVED2_F"
+#define GCLK_REG_RESERVED2_F (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_F (1<<27)
+
+#define GCLK_IDX_RESERVED2_10 92
+#define GCLK_NAME_RESERVED2_10 "RESERVED2_10"
+#define GCLK_DEV_RESERVED2_10 "CLKGATE_RESERVED2_10"
+#define GCLK_REG_RESERVED2_10 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_10 (1<<28)
+
+#define GCLK_IDX_CLK81_TO_A9 93
+#define GCLK_NAME_CLK81_TO_A9 "CLK81_TO_A9"
+#define GCLK_DEV_CLK81_TO_A9 "CLKGATE_CLK81_TO_A9"
+#define GCLK_REG_CLK81_TO_A9 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_CLK81_TO_A9 (1<<29)
+
+#define GCLK_IDX_GIC 94
+#define GCLK_NAME_GIC "GIC"
+#define GCLK_DEV_GIC "CLKGATE_GIC"
+#define GCLK_REG_GIC (HHI_GCLK_MPEG2)
+#define GCLK_MASK_GIC (1<<30)
+
+#define GCLK_IDX_RESERVED2_12 95
+#define GCLK_NAME_RESERVED2_12 "RESERVED2_12"
+#define GCLK_DEV_RESERVED2_12 "CLKGATE_RESERVED2_12"
+#define GCLK_REG_RESERVED2_12 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED2_12 (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_RESERVED3_0 96
+#define GCLK_NAME_RESERVED3_0 "RESERVED3_0"
+#define GCLK_DEV_RESERVED3_0 "CLKGATE_RESERVED3_0"
+#define GCLK_REG_RESERVED3_0 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_0 (1<<0)
+
+#define GCLK_IDX_VCLK2_VENCI 97
+#define GCLK_NAME_VCLK2_VENCI "VCLK2_VENCI"
+#define GCLK_DEV_VCLK2_VENCI "CLKGATE_VCLK2_VENCI"
+#define GCLK_REG_VCLK2_VENCI (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCI (1<<1)
+
+#define GCLK_IDX_VCLK2_VENCI1 98
+#define GCLK_NAME_VCLK2_VENCI1 "VCLK2_VENCI1"
+#define GCLK_DEV_VCLK2_VENCI1 "CLKGATE_VCLK2_VENCI1"
+#define GCLK_REG_VCLK2_VENCI1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCI1 (1<<2)
+
+#define GCLK_IDX_VCLK2_VENCP 99
+#define GCLK_NAME_VCLK2_VENCP "VCLK2_VENCP"
+#define GCLK_DEV_VCLK2_VENCP "CLKGATE_VCLK2_VENCP"
+#define GCLK_REG_VCLK2_VENCP (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCP (1<<3)
+
+#define GCLK_IDX_VCLK2_VENCP1 100
+#define GCLK_NAME_VCLK2_VENCP1 "VCLK2_VENCP1"
+#define GCLK_DEV_VCLK2_VENCP1 "CLKGATE_VCLK2_VENCP1"
+#define GCLK_REG_VCLK2_VENCP1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCP1 (1<<4)
+
+#define GCLK_IDX_VCLK2_VENCT 101
+#define GCLK_NAME_VCLK2_VENCT "VCLK2_VENCT"
+#define GCLK_DEV_VCLK2_VENCT "CLKGATE_VCLK2_VENCT"
+#define GCLK_REG_VCLK2_VENCT (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCT (1<<5)
+
+#define GCLK_IDX_VCLK2_VENCT1 102
+#define GCLK_NAME_VCLK2_VENCT1 "VCLK2_VENCT1"
+#define GCLK_DEV_VCLK2_VENCT1 "CLKGATE_VCLK2_VENCT1"
+#define GCLK_REG_VCLK2_VENCT1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCT1 (1<<6)
+
+#define GCLK_IDX_VCLK2_OTHER 103
+#define GCLK_NAME_VCLK2_OTHER "VCLK2_OTHER"
+#define GCLK_DEV_VCLK2_OTHER "CLKGATE_VCLK2_OTHER"
+#define GCLK_REG_VCLK2_OTHER (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_OTHER (1<<7)
+
+#define GCLK_IDX_VCLK2_ENCI 104
+#define GCLK_NAME_VCLK2_ENCI "VCLK2_ENCI"
+#define GCLK_DEV_VCLK2_ENCI "CLKGATE_VCLK2_ENCI"
+#define GCLK_REG_VCLK2_ENCI (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCI (1<<8)
+
+#define GCLK_IDX_VCLK2_ENCP 105
+#define GCLK_NAME_VCLK2_ENCP "VCLK2_ENCP"
+#define GCLK_DEV_VCLK2_ENCP "CLKGATE_VCLK2_ENCP"
+#define GCLK_REG_VCLK2_ENCP (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCP (1<<9)
+
+#define GCLK_IDX_DAC_CLK 106
+#define GCLK_NAME_DAC_CLK "DAC_CLK"
+#define GCLK_DEV_DAC_CLK "CLKGATE_DAC_CLK"
+#define GCLK_REG_DAC_CLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_DAC_CLK (1<<10)
+
+#define GCLK_IDX_RESERVED3_1 107
+#define GCLK_NAME_RESERVED3_1 "RESERVED3_1"
+#define GCLK_DEV_RESERVED3_1 "CLKGATE_RESERVED3_1"
+#define GCLK_REG_RESERVED3_1 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_1 (1<<11)
+
+#define GCLK_IDX_RESERVED3_2 108
+#define GCLK_NAME_RESERVED3_2 "RESERVED3_2"
+#define GCLK_DEV_RESERVED3_2 "CLKGATE_RESERVED3_2"
+#define GCLK_REG_RESERVED3_2 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_2 (1<<12)
+
+#define GCLK_IDX_RESERVED3_3 109
+#define GCLK_NAME_RESERVED3_3 "RESERVED3_3"
+#define GCLK_DEV_RESERVED3_3 "CLKGATE_RESERVED3_3"
+#define GCLK_REG_RESERVED3_3 (HHI_GCLK_MPEG2)
+#define GCLK_MASK_RESERVED3_3 (1<<13)
+
+#define GCLK_IDX_AIU_AOCLK 110
+#define GCLK_NAME_AIU_AOCLK "AIU_AOCLK"
+#define GCLK_DEV_AIU_AOCLK "CLKGATE_AIU_AOCLK"
+#define GCLK_REG_AIU_AOCLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_AIU_AOCLK (1<<14)
+
+#define GCLK_IDX_RESERVED3_4 111
+#define GCLK_NAME_RESERVED3_4 "RESERVED3_4"
+#define GCLK_DEV_RESERVED3_4 "CLKGATE_RESERVED3_4"
+#define GCLK_REG_RESERVED3_4 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_4 (1<<15)
+
+#define GCLK_IDX_AIU_ICE958_AMCLK 112
+#define GCLK_NAME_AIU_ICE958_AMCLK "AIU_ICE958_AMCLK"
+#define GCLK_DEV_AIU_ICE958_AMCLK "CLKGATE_AIU_ICE958_AMCLK"
+#define GCLK_REG_AIU_ICE958_AMCLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_AIU_ICE958_AMCLK (1<<16)
+
+#define GCLK_IDX_RESERVED3_5 113
+#define GCLK_NAME_RESERVED3_5 "RESERVED3_5"
+#define GCLK_DEV_RESERVED3_5 "CLKGATE_RESERVED3_5"
+#define GCLK_REG_RESERVED3_5 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_5 (1<<17)
+
+#define GCLK_IDX_RESERVED3_6 114
+#define GCLK_NAME_RESERVED3_6 "RESERVED3_6"
+#define GCLK_DEV_RESERVED3_6 "CLKGATE_RESERVED3_6"
+#define GCLK_REG_RESERVED3_6 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_6 (1<<18)
+
+#define GCLK_IDX_RESERVED3_7 115
+#define GCLK_NAME_RESERVED3_7 "RESERVED3_7"
+#define GCLK_DEV_RESERVED3_7 "CLKGATE_RESERVED3_7"
+#define GCLK_REG_RESERVED3_7 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_7 (1<<19)
+
+#define GCLK_IDX_ENC480P 116
+#define GCLK_NAME_ENC480P "ENC480P"
+#define GCLK_DEV_ENC480P "CLKGATE_ENC480P"
+#define GCLK_REG_ENC480P (HHI_GCLK_OTHER)
+#define GCLK_MASK_ENC480P (1<<20)
+
+#define GCLK_IDX_RANDOM_NUM_GEN1 117
+#define GCLK_NAME_RANDOM_NUM_GEN1 "RANDOM_NUM_GEN1"
+#define GCLK_DEV_RANDOM_NUM_GEN1 "CLKGATE_RANDOM_NUM_GEN1"
+#define GCLK_REG_RANDOM_NUM_GEN1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RANDOM_NUM_GEN1 (1<<21)
+
+#define GCLK_IDX_VCLK2_ENCT 118
+#define GCLK_NAME_VCLK2_ENCT "GCLK_VENCL_INT"
+#define GCLK_DEV_VCLK2_ENCT "CLKGATE_GCLK_VENCL_INT"
+#define GCLK_REG_VCLK2_ENCT (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCT (1<<22)
+
+#define GCLK_IDX_VCLK2_ENCL 119
+#define GCLK_NAME_VCLK2_ENCL "VLKC2_ENCL"
+#define GCLK_DEV_VCLK2_ENCL "CLKGATE_VCLK2_ENCL"
+#define GCLK_REG_VCLK2_ENCL (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_ENCL (1<<23)
+
+#define GCLK_IDX_MMC_CLK 120
+#define GCLK_NAME_MMC_CLK "MMC_CLK"
+#define GCLK_DEV_MMC_CLK "CLKGATE_MMC_CLK"
+#define GCLK_REG_MMC_CLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_MMC_CLK (1<<24)
+
+#define GCLK_IDX_VCLK2_VENCL 121
+#define GCLK_NAME_VCLK2_VENCL "VCLK2_VENCL"
+#define GCLK_DEV_VCLK2_VENCL "CLKGATE_VCLK2_VENCL"
+#define GCLK_REG_VCLK2_VENCL (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_VENCL (1<<25)
+
+#define GCLK_IDX_VCLK2_OTHER1 122
+#define GCLK_NAME_VCLK2_OTHER1 "VCLK2_OTHER1"
+#define GCLK_DEV_VCLK2_OTHER1 "CLKGATE_VCLK2_OTHER1"
+#define GCLK_REG_VCLK2_OTHER1 (HHI_GCLK_OTHER)
+#define GCLK_MASK_VCLK2_OTHER1 (1<<26)
+
+#define GCLK_IDX_RESERVED3_9 123
+#define GCLK_NAME_RESERVED3_9 "RESERVED3_9"
+#define GCLK_DEV_RESERVED3_9 "CLKGATE_RESERVED3_9"
+#define GCLK_REG_RESERVED3_9 (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_9 (1<<27)
+
+#define GCLK_IDX_RESERVED3_A 124
+#define GCLK_NAME_RESERVED3_A "RESERVED3_A"
+#define GCLK_DEV_RESERVED3_A "CLKGATE_RESERVED3_A"
+#define GCLK_REG_RESERVED3_A (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_A (1<<28)
+
+#define GCLK_IDX_RESERVED3_B 125
+#define GCLK_NAME_RESERVED3_B "RESERVED3_B"
+#define GCLK_DEV_RESERVED3_B "CLKGATE_RESERVED3_B"
+#define GCLK_REG_RESERVED3_B (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_B (1<<29)
+
+#define GCLK_IDX_RESERVED3_C 126
+#define GCLK_NAME_RESERVED3_C "RESERVED3_C"
+#define GCLK_DEV_RESERVED3_C "CLKGATE_RESERVED3_C"
+#define GCLK_REG_RESERVED3_C (HHI_GCLK_OTHER)
+#define GCLK_MASK_RESERVED3_C (1<<30)
+
+#define GCLK_IDX_EDP_CLK 127
+#define GCLK_NAME_EDP_CLK "EDP_CLK"
+#define GCLK_DEV_EDP_CLK "CLKGATE_EDP_CLK"
+#define GCLK_REG_EDP_CLK (HHI_GCLK_OTHER)
+#define GCLK_MASK_EDP_CLK (1<<31)
+
+/**************************************************************/
+
+#define GCLK_IDX_MEDIA_CPU 128
+#define GCLK_NAME_MEDIA_CPU "MEDIA_CPU"
+#define GCLK_DEV_MEDIA_CPU "CLKGATE_MEDIA_CPU"
+#define GCLK_REG_MEDIA_CPU (HHI_GCLK_AO)
+#define GCLK_MASK_MEDIA_CPU (1<<0)
+
+#define GCLK_IDX_AHB_SRAM 129
+#define GCLK_NAME_AHB_SRAM "AHB_SRAM"
+#define GCLK_DEV_AHB_SRAM "CLKGATE_AHB_SRAM"
+#define GCLK_REG_AHB_SRAM (HHI_GCLK_AO)
+#define GCLK_MASK_AHB_SRAM (1<<1)
+
+#define GCLK_IDX_AHB_BUS 130
+#define GCLK_NAME_AHB_BUS "AHB_BUS"
+#define GCLK_DEV_AHB_BUS "CLKGATE_AHB_BUS"
+#define GCLK_REG_AHB_BUS (HHI_GCLK_AO)
+#define GCLK_MASK_AHB_BUS (1<<2)
+
+#define GCLK_IDX_AO_REGS 131
+#define GCLK_NAME_AO_REGS "AO_REGS"
+#define GCLK_DEV_AO_REGS "CLKGATE_AO_REGS"
+#define GCLK_REG_AO_REGS (HHI_GCLK_AO)
+#define GCLK_MASK_AO_REGS (1<<3)
+
+#define GCLK_NAME_I2C_AO "I2C_AO"
+#define GCLK_REG_I2C_AO (HHI_GCLK_AO)
+#define GCLK_MASK_I2C_AO (1<<4)
+
+
+#define GCLK_IDX_CTS_ENCI 132
+#define GCLK_NAME_CTS_ENCI "CTS_ENCI"
+#define GCLK_DEV_CTS_ENCI "CLKGATE_CTS_ENCI"
+#define GCLK_REG_CTS_ENCI (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCI (1<<0)
+
+#define GCLK_IDX_CTS_ENCT 133
+#define GCLK_NAME_CTS_ENCT "CTS_ENCT"
+#define GCLK_DEV_CTS_ENCT "CLKGATE_CTS_ENCT"
+#define GCLK_REG_CTS_ENCT (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCT (1<<1)
+
+#define GCLK_IDX_CTS_ENCP 134
+#define GCLK_NAME_CTS_ENCP "CTS_ENCP"
+#define GCLK_DEV_CTS_ENCP "CLKGATE_CTS_ENCP"
+#define GCLK_REG_CTS_ENCP (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCP (1<<2)
+
+#define GCLK_IDX_CTS_ENCL 135
+#define GCLK_NAME_CTS_ENCL "CTS_ENCL"
+#define GCLK_DEV_CTS_ENCL "CLKGATE_CTS_ENCL"
+#define GCLK_REG_CTS_ENCL (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_ENCL (1<<3)
+
+#define GCLK_IDX_CTS_VDAC 136
+#define GCLK_NAME_CTS_VDAC "CTS_VDAC"
+#define GCLK_DEV_CTS_VDAC "CLKGATE_CTS_VDAC"
+#define GCLK_REG_CTS_VDAC (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_VDAC (1<<4)
+
+#define GCLK_IDX_CTS_HDMI_TX_PIXEL 137
+#define GCLK_NAME_CTS_HDMI_TX_PIXEL "CTS_HDMI_TX_PIXEL"
+#define GCLK_DEV_CTS_HDMI_TX_PIXEL "CLKGATE_CTS_HDMI_TX_PIXEL"
+#define GCLK_REG_CTS_HDMI_TX_PIXEL (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_CTS_HDMI_TX_PIXEL (1<<5)
+
+#define GCLK_IDX_AUD 138
+#define GCLK_NAME_AUD "AUD"
+#define GCLK_DEV_AUD "CLKGATE_AUD"
+#define GCLK_REG_AUD (HHI_AUD_CLK_CNTL)
+#define GCLK_MASK_AUD (1<<23)
+
+
+#define GCLK_IDX_AUD2 138
+#define GCLK_NAME_AUD2 "AUD2"
+#define GCLK_DEV_AUD2 "CLKGATE_AUD2"
+#define GCLK_REG_AUD2 (HHI_AUD_CLK_CNTL)
+#define GCLK_MASK_AUD2 (1<<8)
+
+
+#define GCLK_NAME_AUD_CLK_2 "AUD_CLK_2"
+#define GCLK_REG_AUD_CLK_2 (HHI_AUD_CLK_CNTL2)
+#define GCLK_MASK_AUD_CLK_2 (1<<8)
+
+#define GCLK_IDX_AUD_CLK_3 138
+#define GCLK_NAME_AUD_CLK_3 "AUD_CLK"
+#define GCLK_DEV_AUD_CLK_3 "CLKGATE_AUD_CLK"
+#define GCLK_REG_AUD_CLK_3 (HHI_AUD_CLK_CNTL3)
+#define GCLK_MASK_AUD_CLK_3 (1<<16)
+
+#define GCLK_IDX_LCD_AN_PHY2 139
+#define GCLK_NAME_LCD_AN_PHY2 "LCD_AN_PHY2"
+#define GCLK_DEV_LCD_AN_PHY2 "CLKGATE_LCD_AN_PHY2"
+#define GCLK_REG_LCD_AN_PHY2 (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_LCD_AN_PHY2 (1<<7)
+
+#define GCLK_IDX_LCD_AN_PHY3 140
+#define GCLK_NAME_LCD_AN_PHY3 "LCD_AN_PHY3"
+#define GCLK_DEV_LCD_AN_PHY3 "CLKGATE_LCD_AN_PHY3"
+#define GCLK_REG_LCD_AN_PHY3 (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_LCD_AN_PHY3 (1<<6)
+
+#define GCLK_NAME_ATV_DEMO_VDAC "ATV_DEMO_VDAC"
+#define GCLK_REG_ATV_DEMO_VDAC (HHI_VID_CLK_CNTL2)
+#define GCLK_MASK_ATV_DEMO_VDAC (1<<8)
+
+#define GCLK_IDX_HDMI_PLL_CNTL 142
+#define GCLK_NAME_HDMI_PLL_CNTL "HDMI_PLL_CNTL"
+#define GCLK_DEV_HDMI_PLL_CNTL "GATE_HDMI_PLL_CNTL"
+#define GCLK_REG_HDMI_PLL_CNTL (HHI_HDMI_PLL_CNTL)
+#define GCLK_MASK_HDMI_PLL_CNTL (1<<30)
+
+#define GCLK_NAME_HDMITX_CLK "HDMITX_CLK"
+#define GCLK_REG_HDMITX_CLK (HHI_HDMI_CLK_CNTL)
+#define GCLK_MASK_HDMITX_CLK (1<<8)
+
+
+#define GCLK_NAME_HDMITX_CLK "HDMITX_CLK"
+#define GCLK_REG_HDMITX_CLK (HHI_HDMI_CLK_CNTL)
+#define GCLK_MASK_HDMITX_CLK (1<<8)
+
+#define GCLK_IDX_VDEC_CLK_1 144
+#define GCLK_NAME_VDEC_CLK_1 "VDEC_CLK_1"
+#define GCLK_DEV_VDEC_CLK_1 "CLKGATE_VDEC_CLK_1"
+#define GCLK_REG_VDEC_CLK_1 (HHI_VDEC_CLK_CNTL)
+#define GCLK_MASK_VDEC_CLK_1 (1<<8)
+
+#define GCLK_NAME_VDEC_CLK_2 "VDEC_CLK_2"
+#define GCLK_REG_VDEC_CLK_2 (HHI_VDEC3_CLK_CNTL)
+#define GCLK_MASK_VDEC_CLK_2 (1<<8)
+
+#define GCLK_NAME_VDEC2_CLK_1 "VDEC2_CLK_1"
+#define GCLK_REG_VDEC2_CLK_1 (HHI_VDEC2_CLK_CNTL)
+#define GCLK_MASK_VDEC2_CLK_1 (1<<8)
+
+#define GCLK_NAME_VDEC2_CLK_2 "VDEC2_CLK_2"
+#define GCLK_REG_VDEC2_CLK_2 (HHI_VDEC4_CLK_CNTL)
+#define GCLK_MASK_VDEC2_CLK_2 (1<<8)
+
+#define GCLK_IDX_HCODEC_CLK_1 145
+#define GCLK_NAME_HCODEC_CLK_1 "HCODEC_CLK"
+#define GCLK_DEV_HCODEC_CLK_1 "CLKGATE_HCODEC_CLK"
+#define GCLK_REG_HCODEC_CLK_1 (HHI_VDEC_CLK_CNTL)
+#define GCLK_MASK_HCODEC_CLK_1 (1<<24)
+
+#define GCLK_NAME_HCODEC_CLK_2 "HCODEC_CLK_2"
+#define GCLK_REG_HCODEC_CLK_2 (HHI_VDEC3_CLK_CNTL)
+#define GCLK_MASK_HCODEC_CLK_2 (1<<24)
+
+#define GCLK_NAME_HEVC_CLK_1 "HCODEC_CLK_1"
+#define GCLK_REG_HEVC_CLK_1 (HHI_VDEC2_CLK_CNTL)
+#define GCLK_MASK_HEVC_CLK_1 (1<<24)
+
+#define GCLK_NAME_HEVC_CLK_2 "HEVC_CLK_2"
+#define GCLK_REG_HEVC_CLK_2 (HHI_VDEC4_CLK_CNTL)
+#define GCLK_MASK_HEVC_CLK_2 (1<<24)
+
+#define GCLK_IDX_GEN_CLK 146
+#define GCLK_NAME_GEN_CLK "GEN_CLK"
+#define GCLK_DEV_GEN_CLK "CLKGATE_HCODEC_CLK"
+#define GCLK_REG_GEN_CLK (HHI_GEN_CLK_CNTL)
+#define GCLK_MASK_GEN_CLK (1<<11)
+
+#define GCLK_NAME_VPU_CLK_1 "VPU_CLK_1"
+#define GCLK_REG_VPU_CLK_1 (HHI_VPU_CLK_CNTL)
+#define GCLK_MASK_VPU_CLK_1 (1<<8)
+
+#define GCLK_NAME_VPU_CLK_2 "VPU_CLK_2"
+#define GCLK_REG_VPU_CLK_2 (HHI_VPU_CLK_CNTL)
+#define GCLK_MASK_VPU_CLK_2 (1<<24)
+
+
+#define GCLK_NAME_VPU_CLKB "VPU_CLKB"
+#define GCLK_REG_VPU_CLKB (HHI_VPU_CLKB_CNTL)
+#define GCLK_MASK_VPU_CLKB (1<<8)
+
+#define GCLK_NAME_VAPB_CLK_1 "VAPB_CLK_1"
+#define GCLK_REG_VAPB_CLK_1 (HHI_VAPBCLK_CNTL)
+#define GCLK_MASK_VAPB_CLK_1 (1<<8)
+
+#define GCLK_NAME_VAPB_CLK_2 "VAPB_CLK_2"
+#define GCLK_REG_VAPB_CLK_2 (HHI_VAPBCLK_CNTL)
+#define GCLK_MASK_VAPB_CLK_2 (1<<24)
+
+#define GCLK_NAME_MALI_CLK_1 "MALI_CLK_1"
+#define GCLK_REG_MALI_CLK_1 (HHI_MALI_CLK_CNTL)
+#define GCLK_MASK_MALI_CLK_1 (1<<8)
+
+#define GCLK_NAME_MALI_CLK_2 "MALI_CLK_2"
+#define GCLK_REG_MALI_CLK_2 (HHI_MALI_CLK_CNTL)
+#define GCLK_MASK_MALI_CLK_2 (1<<24)
+
+#define GCLK_NAME_PWM_A_CLK "PWM_A_CLK"
+#define GCLK_REG_PWM_A_CLK (CBUS_REG_ADDR(0x2156))
+#define GCLK_MASK_PWM_A_CLK (1<<15)
+
+#define GCLK_NAME_PWM_B_CLK "PWM_B_CLK"
+#define GCLK_REG_PWM_B_CLK (CBUS_REG_ADDR(0x2156))
+#define GCLK_MASK_PWM_B_CLK (1<<23)
+
+#define GCLK_NAME_PWM_C_CLK "PWM_C_CLK"
+#define GCLK_REG_PWM_C_CLK (CBUS_REG_ADDR(0x2196))
+#define GCLK_MASK_PWM_C_CLK (1<<15)
+
+#define GCLK_NAME_PWM_D_CLK "PWM_D_CLK"
+#define GCLK_REG_PWM_D_CLK (CBUS_REG_ADDR(0x2196))
+#define GCLK_MASK_PWM_D_CLK (1<<23)
+
+#define GCLK_NAME_PWM_E_CLK "PWM_E_CLK"
+#define GCLK_REG_PWM_E_CLK (CBUS_REG_ADDR(0x21b2))
+#define GCLK_MASK_PWM_E_CLK (1<<15)
+
+#define GCLK_NAME_PWM_F_CLK "PWM_D_CLK"
+#define GCLK_REG_PWM_F_CLK (CBUS_REG_ADDR(0x21b2))
+#define GCLK_MASK_PWM_F_CLK (1<<23)
+
+#define GCLK_NAME_VDIN_MEAS_CLK "VDIN_MEAS_CLK"
+#define GCLK_REG_VDIN_MEAS_CLK (HHI_VDIN_MEAS_CLK_CNTL)
+#define GCLK_MASK_VDIN_MEAS_CLK (1<<8)
+
+#define GCLK_NAME_MSR_CLK "MSR_CLK"
+#define GCLK_REG_MSR_CLK (CBUS_REG_ADDR(0x21d7))
+#define GCLK_MASK_MSR_CLK (1<<19)
+
+#define GCLK_NAME_MSR_HS_CLK "MSR_HS_CLK"
+#define GCLK_REG_MSR_HS_CLK (CBUS_REG_ADDR(0x21d9))
+#define GCLK_MASK_MSR_HS_CLK (1<<28)
+
+#define GCLK_NAME_32K_CLK "32K_CLK"
+#define GCLK_REG_32K_CLK (HHI_32K_CLK_CNTL)
+#define GCLK_MASK_32K_CLK (1<<15)
+
+
+
+#define GCLK_IDX_MAX 200
+
+extern short GCLK_ref[GCLK_IDX_MAX];
+
+#define REGISTER_CLK(_MOD) \
+static struct clk CLK_##_MOD = { \
+ .name = GCLK_NAME_##_MOD, \
+ .clock_index = GCLK_IDX_##_MOD, \
+ .clock_gate_reg_adr = GCLK_REG_##_MOD, \
+ .clock_gate_reg_mask = GCLK_MASK_##_MOD, \
+}
+
+#define CLK_LOOKUP_ITEM(_MOD) \
+ { \
+ .dev_id = GCLK_DEV_##_MOD, \
+ .con_id = GCLK_NAME_##_MOD, \
+ .clk = &CLK_##_MOD, \
+ }
+
+
+
+/**********************/
+/* internal audio dac control */
+#define ADAC_RESET (0x5000+0x00*4)
+#define ADAC_LATCH (0x5000+0x01*4)
+#define ADAC_POWER_CTRL_REG1 (0x5000+0x10*4)
+#define ADAC_POWER_CTRL_REG2 (0x5000+0x11*4)
+
+int audio_internal_dac_disable(void);
+
+/* video dac control */
+int video_dac_enable(unsigned char enable_mask);
+
+int video_dac_disable(void);
+
+
+#endif
diff --git a/arch/arm/mach-meson/t7/pwrc.c b/arch/arm/mach-meson/t7/pwrc.c
new file mode 100644
index 0000000..34f9c97
--- /dev/null
+++ b/arch/arm/mach-meson/t7/pwrc.c
@@ -0,0 +1,60 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+char* domain_name[] =
+{
+ "PM_DSPA",
+ "PM_DSPB",
+ "PM_DOS_HCODEC",
+ "PM_DOS_HEVC",
+ "PM_DOS_VDEC",
+ "PM_DOS_WAVE",
+ "PM_VPU_HDMI",
+ "PM_USB_COMB",
+ "PM_PCIE",
+ "PM_GE2D",
+ "PM_SRAMA",
+ "PM_SRAMB",
+ "PM_HDMIRX",
+ "PM_VI_CLK1",
+ "PM_VI_CLK2",
+ "PM_ETH",
+ "PM_ISP",
+ "PM_MIPI_ISP",
+ "PM_GDC",
+ "PM_DEWARP",
+ "PM_SDIO_A",
+ "PM_SDIO_B",
+ "PM_EMMC",
+ "PM_MALI_SC0",
+ "PM_MALI_SC1",
+ "PM_MALI_SC2",
+ "PM_MALI_SC3",
+ "PM_MALI_TOP",
+ "PM_NNA_CORE0",
+ "PM_NNA_CORE1",
+ "PM_NNA_CORE2",
+ "PM_NNA_CORE3",
+ "PM_NNA_TOP",
+ "PM_DDR0",
+ "PM_DDR1",
+ "PM_DMC0",
+ "PM_DMC1",
+ "PM_NOC",
+ "PM_NIC2",
+ "PM_NIC3",
+ "PM_CCI",
+ "PM_MIPI_DSI0",
+ "PM_SPICC0",
+ "PM_SPICC1",
+ "PM_SPICC2",
+ "PM_SPICC3",
+ "PM_SPICC4",
+ "PM_SPICC5",
+ "PM_EDP0",
+ "PM_EDP1",
+ "PM_MIPI_DSI1",
+ "PM_AUDIO",
+};
diff --git a/arch/arm/mach-meson/t7/sdio.c b/arch/arm/mach-meson/t7/sdio.c
new file mode 100644
index 0000000..14ec635
--- /dev/null
+++ b/arch/arm/mach-meson/t7/sdio.c
@@ -0,0 +1,32 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <asm/arch/io.h>
+#include <asm/arch/cpu_sdio.h>
+#include <asm/arch/secure_apb.h>
+#include <amlogic/cpu_id.h>
+#include <common.h>
+
+void cpu_sd_emmc_pwr_prepare(unsigned port)
+{
+}
+int cpu_sd_emmc_init(unsigned port)
+{
+ return 0;
+}
+
+/* return:
+ 0: insert
+ 1: not insert
+ */
+__weak int sd_emmc_detect(unsigned port)
+{
+ int ret = 0;
+
+ return ret;
+}
+
+
diff --git a/arch/arm/mach-meson/t7/timer.c b/arch/arm/mach-meson/t7/timer.c
new file mode 100644
index 0000000..8c16210
--- /dev/null
+++ b/arch/arm/mach-meson/t7/timer.c
@@ -0,0 +1,23 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timer.h>
+#include <asm/types.h>
+
+uint32_t get_time(void)
+{
+ return readl(SYSCTRL_TIMERE);
+}
+
+void _udelay(unsigned int us)
+{
+#ifndef CONFIG_PXP_EMULATOR
+ unsigned int t0 = get_time();
+
+ while (get_time() - t0 <= us)
+ ;
+#endif
+}
diff --git a/arch/arm/mach-meson/t7/tsensor.c b/arch/arm/mach-meson/t7/tsensor.c
new file mode 100644
index 0000000..0bb9ba8
--- /dev/null
+++ b/arch/arm/mach-meson/t7/tsensor.c
@@ -0,0 +1,615 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <command.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/mailbox.h>
+#include <asm/arch/tsensor.h>
+#include <asm/arch/bl31_apis.h>
+#include <linux/arm-smccc.h>
+#include <asm/arch/pwr_ctrl.h>
+int tsensor_tz_calibration(unsigned int type, unsigned int data)
+{
+ int ret;
+
+ register long x0 asm("x0") = TSENSOR_CALI_SET;
+ register long x1 asm("x1") = type;
+ register long x2 asm("x2") = data;
+ register long x3 asm("x3") = 0;
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x3")
+ "smc #0\n"
+ : "+r" (x0)
+ : "r" (x1), "r" (x2), "r" (x3));
+ } while (0);
+ ret = x0;
+
+ if (!ret)
+ return -1;
+ else
+ return 0;
+}
+
+int thermal_cali_data_read(uint32_t type, uint32_t *outbuf, int32_t size)
+{
+ long sharemem_output_base = 0;
+ struct arm_smccc_res res;
+
+ sharemem_output_base = get_sharemem_info(GET_SHARE_MEM_OUTPUT_BASE);
+
+ arm_smccc_smc(TSENSOR_CALI_READ, type, 0, 0, 0, 0, 0, 0, &res);
+ flush_cache(sharemem_output_base, size);
+ memcpy((void *)outbuf, (void *)sharemem_output_base, size);
+ return 0;
+}
+
+int r1p1_codetotemp(unsigned long value, unsigned int u_efuse)
+{
+ int64_t temp;
+
+ temp = (value * ts_m) * (1 << 16) / (100 * (1 << 16) + ts_n * value);
+ if (u_efuse & 0x8000) {
+ temp = ((temp - (u_efuse & 0x7fff)) * ts_a / (1 << 16) - ts_b) / 10;
+ } else {
+ temp = ((temp + (u_efuse & 0x7fff)) * ts_a / (1 << 16) - ts_b) / 10;
+ }
+ return temp;
+}
+
+int r1p1_temp_read(int type)
+{
+ uint32_t ret;
+ unsigned int u_efuse;
+ unsigned int value_ts, value_all_ts;
+ int tmp = -1;
+ int i, cnt;
+ char buf[2];
+
+ switch (type) {
+ case 1:
+ /*enable thermal1*/
+ writel(T_CONTROL_DATA, TS_A73_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL);
+ thermal_cali_data_read(1, &ret, 4);
+ printf("a73 tsensor cali data: ret = %x\n", ret);
+ mdelay(5);
+ buf[0] = (ret) & 0xff;
+ buf[1] = (ret >> 8) & 0xff;
+ u_efuse = buf[1];
+ u_efuse = (u_efuse << 8) | buf[0];
+ value_ts = 0;
+ value_all_ts = 0;
+ cnt = 0;
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_A73_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_A73_STAT0) & 0xffff;
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ value_ts = value_all_ts / cnt;
+ printf("a73 tsensor avg: 0x%x, u_efuse: 0x%x\n", value_ts, u_efuse);
+ if (value_ts == 0) {
+ printf("a73 tsensor read temp is zero\n");
+ return -1;
+ }
+ tmp = r1p1_codetotemp(value_ts, u_efuse);
+ printf("a73 tsensor temp: %d\n", tmp);
+ break;
+ case 3:
+ /*enable thermal3*/
+ writel(T_CONTROL_DATA, TS_GPU_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL);
+ thermal_cali_data_read(3, &ret, 4);
+ printf("gpu tsensor cali data: ret = %x\n", ret);
+ mdelay(5);
+ buf[0] = (ret) & 0xff;
+ buf[1] = (ret >> 8) & 0xff;
+ u_efuse = buf[1];
+ u_efuse = (u_efuse << 8) | buf[0];
+ value_ts = 0;
+ value_all_ts = 0;
+ cnt = 0;
+ pwr_ctrl_psci_smc(PM_MALI_TOP, PWR_ON);
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_GPU_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_GPU_STAT0) & 0xffff;
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ pwr_ctrl_psci_smc(PM_MALI_TOP, PWR_OFF);
+ value_ts = value_all_ts / cnt;
+ printf("gpu tsensor avg: 0x%x, u_efuse: 0x%x\n", value_ts, u_efuse);
+ if (value_ts == 0) {
+ printf("gpu tsensor read temp is zero\n");
+ return -1;
+ }
+ tmp = r1p1_codetotemp(value_ts, u_efuse);
+ printf("gpu tsensor temp: %d\n", tmp);
+ break;
+ case 4:
+ /*enable thermal4*/
+ writel(T_CONTROL_DATA, TS_NNA_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL);
+ thermal_cali_data_read(4, &ret, 4);
+ printf("nna tsensor cali data: ret = %x\n", ret);
+ mdelay(5);
+ buf[0] = (ret) & 0xff;
+ buf[1] = (ret >> 8) & 0xff;
+ u_efuse = buf[1];
+ u_efuse = (u_efuse << 8) | buf[0];
+ value_ts = 0;
+ value_all_ts = 0;
+ cnt = 0;
+ pwr_ctrl_psci_smc(PM_NNA_TOP, PWR_ON);
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_NNA_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_NNA_STAT0) & 0xffff;
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ pwr_ctrl_psci_smc(PM_NNA_TOP, PWR_OFF);
+ value_ts = value_all_ts / cnt;
+ printf("nna tsensor avg: 0x%x, u_efuse: 0x%x\n", value_ts, u_efuse);
+ if (value_ts == 0) {
+ printf("nna tsensor read temp is zero\n");
+ return -1;
+ }
+ tmp = r1p1_codetotemp(value_ts, u_efuse);
+ printf("nna tsensor temp: %d\n", tmp);
+ break;
+ case 5:
+ /*enable thermal2*/
+ writel(T_CONTROL_DATA, TS_HEVC_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL);
+ thermal_cali_data_read(5, &ret, 4);
+ printf("hevc tsensor cali data: ret = %x\n", ret);
+ mdelay(5);
+ buf[0] = (ret) & 0xff;
+ buf[1] = (ret >> 8) & 0xff;
+ u_efuse = buf[1];
+ u_efuse = (u_efuse << 8) | buf[0];
+ value_ts = 0;
+ value_all_ts = 0;
+ cnt = 0;
+ pwr_ctrl_psci_smc(PM_DOS_HEVC, PWR_ON);
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_HEVC_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_HEVC_STAT0) & 0xffff;
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ pwr_ctrl_psci_smc(PM_DOS_HEVC, PWR_OFF);
+ value_ts = value_all_ts / cnt;
+ printf("hevc tsensor avg: 0x%x, u_efuse: 0x%x\n", value_ts, u_efuse);
+ if (value_ts == 0) {
+ printf("hevc tsensor read temp is zero\n");
+ return -1;
+ }
+ tmp = r1p1_codetotemp(value_ts, u_efuse);
+ printf("hevc tsensor temp: %d\n", tmp);
+ break;
+ case 6:
+ /*enable thermal6*/
+ writel(T_CONTROL_DATA, TS_VPU_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL);
+ thermal_cali_data_read(6, &ret, 4);
+ mdelay(5);
+ if (ret & 0x80000000) {
+ printf("vpu tsensor cali data: ret = %x\n", ret);
+ buf[0] = (ret) & 0xff;
+ buf[1] = (ret >> 8) & 0xff;
+ u_efuse = buf[1];
+ u_efuse = (u_efuse << 8) | buf[0];
+ value_ts = 0;
+ value_all_ts = 0;
+ cnt = 0;
+ pwr_ctrl_psci_smc(PM_VPU_HDMI, PWR_ON);
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_VPU_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_VPU_STAT0) & 0xffff;
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ pwr_ctrl_psci_smc(PM_VPU_HDMI, PWR_OFF);
+ value_ts = value_all_ts / cnt;
+ printf("vpu tsensor avg: 0x%x, u_efuse: 0x%x\n", value_ts, u_efuse);
+ if (value_ts == 0) {
+ printf("hevc tsensor read temp is zero\n");
+ return -1;
+ }
+ tmp = r1p1_codetotemp(value_ts, u_efuse);
+ printf("vpu tsensor temp: %d\n", tmp);
+ }
+ break;
+ default:
+ printf("r1p1 tsensor trim type not support\n");
+ return -1;
+ }
+ return tmp;
+}
+
+unsigned int r1p1_temptocode(unsigned long value, int tempbase)
+{
+ unsigned long tmp1, tmp2, u_efuse, signbit;
+
+ printf("a b m n: %d, %d, %d, %d\n", ts_a, ts_b, ts_m, ts_n);
+ tmp1 = ((tempbase * 10 + ts_b) * (1 << 16)) / ts_a; /*ideal u*/
+ printf("%s : tmp1: 0x%lx\n", __func__, tmp1);
+ tmp2 = (ts_m * value * (1 << 16)) / ((1 << 16) * 100 + ts_n * value);
+ printf("%s : tmp2: 0x%lx\n", __func__, tmp2);
+ signbit = ((tmp1 > tmp2) ? 0 : 1);
+ u_efuse = (tmp1 > tmp2) ? (tmp1 - tmp2) : (tmp2 - tmp1);
+ u_efuse = (signbit << 15) | u_efuse;
+ return u_efuse;
+}
+
+int r1p1_temp_trim(int tempbase, int tempver, int type)
+{
+ unsigned int u_efuse, index_ts, index_ver;
+ unsigned int value_ts, value_all_ts;
+ int i, cnt;
+
+ printf("r1p1 temp trim type: 0x%x\n", type);
+ switch (type) {
+ case 0:
+ index_ver = 5;
+ if (tsensor_tz_calibration(index_ver, tempver) < 0)
+ printf("version tsensor thermal_calibration send error\n");
+ break;
+ case 1:
+ value_ts = 0;
+ value_all_ts = 0;
+ index_ts = 6;
+ cnt = 0;
+ /*enable thermal1*/
+ writel(T_CONTROL_DATA, TS_A73_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL);
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_A73_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_A73_STAT0) & 0xffff;
+ printf("a73 tsensor read: 0x%x\n", value_ts);
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ value_ts = value_all_ts / cnt;
+ printf("a73 tsensor avg: 0x%x\n", value_ts);
+ if (value_ts == 0) {
+ printf("pll tsensor read temp is zero\n");
+ return -1;
+ }
+ u_efuse = r1p1_temptocode(value_ts, tempbase);
+ printf("ts efuse:%d\n", u_efuse);
+ if (u_efuse & 0x8000)
+ u_efuse = u_efuse | 0x4000;
+ u_efuse = u_efuse | 0x8000;
+ printf("ts efuse:0x%x, index: %d\n", u_efuse, index_ts);
+ if (tsensor_tz_calibration(index_ts, u_efuse) < 0) {
+ printf("a73 tsensor thermal_calibration send error\n");
+ return -1;
+ }
+ break;
+ case 2:
+ value_ts = 0;
+ value_all_ts = 0;
+ index_ts = 7;
+ cnt = 0;
+ /*enable thermal2*/
+ writel(T_CONTROL_DATA, TS_A53_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL);
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_A53_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_A53_STAT0) & 0xffff;
+ printf("a53 tsensor read: 0x%x\n", value_ts);
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ value_ts = value_all_ts / cnt;
+ printf("a53 tsensor avg: 0x%x\n", value_ts);
+ if (value_ts == 0) {
+ printf("a53 tsensor read temp is zero\n");
+ return -1;
+ }
+ u_efuse = r1p1_temptocode(value_ts, tempbase);
+ printf("ts efuse:%d\n", u_efuse);
+ if (u_efuse & 0x8000)
+ u_efuse = u_efuse | 0x4000;
+ u_efuse = u_efuse | 0x8000;
+ printf("ts efuse:0x%x, index: %d\n", u_efuse, index_ts);
+ if (tsensor_tz_calibration(index_ts, u_efuse) < 0) {
+ printf("a53 tsensor thermal_calibration send error\n");
+ return -1;
+ }
+ case 3:
+ value_ts = 0;
+ value_all_ts = 0;
+ index_ts = 8;
+ cnt = 0;
+ /*enable thermal3*/
+ writel(T_CONTROL_DATA, TS_GPU_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL);
+ pwr_ctrl_psci_smc(PM_MALI_TOP, PWR_ON);
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_GPU_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_GPU_STAT0) & 0xffff;
+ printf("gpu tsensor read: 0x%x\n", value_ts);
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ pwr_ctrl_psci_smc(PM_MALI_TOP, PWR_OFF);
+ value_ts = value_all_ts / cnt;
+ printf("gpu tsensor avg: 0x%x\n", value_ts);
+ if (value_ts == 0) {
+ printf("gpu tsensor read temp is zero\n");
+ return -1;
+ }
+ u_efuse = r1p1_temptocode(value_ts, tempbase);
+ printf("ts efuse:%d\n", u_efuse);
+ if (u_efuse & 0x8000)
+ u_efuse = u_efuse | 0x4000;
+ u_efuse = u_efuse | 0x8000;
+ printf("ts efuse:0x%x, index: %d\n", u_efuse, index_ts);
+ if (tsensor_tz_calibration(index_ts, u_efuse) < 0) {
+ printf("gpu tsensor thermal_calibration send error\n");
+ return -1;
+ }
+ case 4:
+ value_ts = 0;
+ value_all_ts = 0;
+ index_ts = 9;
+ cnt = 0;
+ /*enable thermal4*/
+ writel(T_CONTROL_DATA, TS_NNA_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL);
+ pwr_ctrl_psci_smc(PM_NNA_TOP, PWR_ON);
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_NNA_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_NNA_STAT0) & 0xffff;
+ printf("nna tsensor read: 0x%x\n", value_ts);
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ pwr_ctrl_psci_smc(PM_NNA_TOP, PWR_OFF);
+ value_ts = value_all_ts / cnt;
+ printf("nna tsensor avg: 0x%x\n", value_ts);
+ if (value_ts == 0) {
+ printf("nna tsensor read temp is zero\n");
+ return -1;
+ }
+ u_efuse = r1p1_temptocode(value_ts, tempbase);
+ printf("ts efuse:%d\n", u_efuse);
+ if (u_efuse & 0x8000)
+ u_efuse = u_efuse | 0x4000;
+ u_efuse = u_efuse | 0x8000;
+ printf("ts efuse:0x%x, index: %d\n", u_efuse, index_ts);
+ if (tsensor_tz_calibration(index_ts, u_efuse) < 0) {
+ printf("nna tsensor thermal_calibration send error\n");
+ return -1;
+ }
+ case 5:
+ value_ts = 0;
+ value_all_ts = 0;
+ index_ts = 10;
+ cnt = 0;
+ /*enable thermal6*/
+ writel(T_CONTROL_DATA, TS_HEVC_CFG_REG1);
+ writel(T_TSCLK_DATA, CLKCTRL_TS_CLK_CTRL);
+ pwr_ctrl_psci_smc(PM_DOS_HEVC, PWR_ON);
+ for (i = 0; i <= 10; i ++) {
+ udelay(50);
+ value_ts = readl(TS_HEVC_STAT0) & 0xffff;
+ }
+ for (i = 0; i <= T_AVG_NUM; i ++) {
+ udelay(T_DLY_TIME);
+ value_ts = readl(TS_HEVC_STAT0) & 0xffff;
+ printf("hevc tsensor read: 0x%x\n", value_ts);
+ if ((value_ts >= T_VALUE_MIN) &&
+ (value_ts <= T_VALUE_MAX)) {
+ value_all_ts += value_ts;
+ cnt ++;
+ }
+ }
+ pwr_ctrl_psci_smc(PM_DOS_HEVC, PWR_OFF);
+ value_ts = value_all_ts / cnt;
+ printf("hevc tsensor avg: 0x%x\n", value_ts);
+ if (value_ts == 0) {
+ printf("hevc tsensor read temp is zero\n");
+ return -1;
+ }
+ u_efuse = r1p1_temptocode(value_ts, tempbase);
+ printf("ts efuse:%d\n", u_efuse);
+ if (u_efuse & 0x8000)
+ u_efuse = u_efuse | 0x4000;
+ u_efuse = u_efuse | 0x8000;
+ printf("ts efuse:0x%x, index: %d\n", u_efuse, index_ts);
+ if (tsensor_tz_calibration(index_ts, u_efuse) < 0) {
+ printf("hevc tsensor thermal_calibration send error\n");
+ return -1;
+ }
+ break;
+ default:
+ printf("r1p1 tsensor trim type not support\n");
+ return -1;
+ break;
+ }
+ return 0;
+}
+
+int temp_read_entry(void)
+{
+ unsigned int ret, ver;
+ uint32_t data = 0;
+
+ thermal_cali_data_read(1, &data, 4);
+ ver = (data >> 24) & 0xff;
+ if (0 == (ver & T_VER_MASK)) {
+ printf("tsensor no trimmed: calidata:0x%x\n", data);
+ return -1;
+ }
+ ret = (ver & 0xf) >> 2;
+ switch (ret) {
+ case 0x0:
+ printf("temp type no support\n");
+ break;
+ case 0x2:
+ printf("temp type no support\n");
+ break;
+ case 0x1:
+ r1p1_temp_read(1);
+ r1p1_temp_read(3);
+ r1p1_temp_read(4);
+ r1p1_temp_read(5);
+ r1p1_temp_read(6);
+ printf("read the thermal\n");
+ break;
+ case 0x3:
+ printf("temp type no support\n");
+ return -1;
+ break;
+ default:
+ printf("thermal version not support!!!Please check!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int temp_trim_entry(int tempbase, int tempver)
+{
+ unsigned int ver;
+ uint32_t data;
+
+ thermal_cali_data_read(1, &data, 4);
+ ver = (data >> 24) & 0xff;
+ if (ver & T_VER_MASK) {
+ printf("tsensor trimmed: cali data: 0x%x\n", data);
+ return -1;
+ }
+
+ printf("tsensor input trim tempver, tempver:0x%x\n", tempver);
+ switch (tempver) {
+ case 0x84:
+ r1p1_temp_trim(tempbase, tempver, 1);
+ r1p1_temp_trim(tempbase, tempver, 2);
+ r1p1_temp_trim(tempbase, tempver, 3);
+ r1p1_temp_trim(tempbase, tempver, 4);
+ r1p1_temp_trim(tempbase, tempver, 5);
+ r1p1_temp_trim(tempbase, tempver, 0);
+ printf("triming the thermal by bbt-sw\n");
+ break;
+ case 0x85:
+ r1p1_temp_trim(tempbase, tempver, 1);
+ r1p1_temp_trim(tempbase, tempver, 2);
+ r1p1_temp_trim(tempbase, tempver, 3);
+ r1p1_temp_trim(tempbase, tempver, 4);
+ r1p1_temp_trim(tempbase, tempver, 5);
+ r1p1_temp_trim(tempbase, tempver, 0);
+ printf("triming the thermal by bbt-ops\n");
+ break;
+ case 0x87:
+ r1p1_temp_trim(tempbase, tempver, 1);
+ r1p1_temp_trim(tempbase, tempver, 2);
+ r1p1_temp_trim(tempbase, tempver, 3);
+ r1p1_temp_trim(tempbase, tempver, 4);
+ r1p1_temp_trim(tempbase, tempver, 5);
+ r1p1_temp_trim(tempbase, tempver, 0);
+ printf("triming the thermal by slt\n");
+ break;
+ default:
+ printf("thermal version not support!!!Please check!\n");
+ return -1;
+ }
+ return 0;
+}
+
+int temp_cooling_entry(void)
+{
+#ifdef CONFIG_AML_TSENSOR_COOL
+ int temp, temp1, i;
+
+ while (1) {
+ temp = r1p1_temp_read(1);
+ for (i = 3; i < 6; i++) {
+ temp1 = r1p1_temp_read(i);
+ temp = temp > temp1 ? temp : temp1;
+ }
+ if (temp <= CONFIG_HIGH_TEMP_COOL) {
+ printf("device cool done\n");
+ break;
+ }
+ mdelay(2000);
+ printf("warning: temp %d over %d, cooling\n", temp,
+ CONFIG_HIGH_TEMP_COOL);
+ }
+#endif
+ return 0;
+}
diff --git a/arch/arm/mach-meson/t7/usb.c b/arch/arm/mach-meson/t7/usb.c
new file mode 100644
index 0000000..0905da4
--- /dev/null
+++ b/arch/arm/mach-meson/t7/usb.c
@@ -0,0 +1,399 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <bitfield.h>
+#include <dm.h>
+#include <errno.h>
+#include <generic-phy.h>
+#include <regmap.h>
+#include <power/regulator.h>
+#include <clk.h>
+#include <asm/arch/usb.h>
+#include <amlogic/cpu_id.h>
+
+#include <linux/compat.h>
+#include <linux/ioport.h>
+#include <asm-generic/gpio.h>
+
+#define PHY20_RESET_LEVEL_BIT 8
+#define PHY21_RESET_LEVEL_BIT 9
+#define USB_RESET_BIT 4
+
+#define USB2_PHY_PLL_OFFSET_40 (0x09400414)
+#define USB2_PHY_PLL_OFFSET_44 (0x927E0000)
+#define USB2_PHY_PLL_OFFSET_48 (0xac5f69e5)
+
+#define USB2_PHY_PLL_OFFSET_10 (0x80000fff)
+#define USB2_PHY_PLL_OFFSET_34 (0x78000)
+#define USB2_REVB_PHY_PLL_OFFSET_34 (0x70000)
+
+#define USB2_PHY_PLL_OFFSET_38_CLEAR (0)
+#define USB2_PHY_PLL_OFFSET_38_SET (0xe0004)
+#define USB2_PHY_PLL_OFFSET_50 (0xfe18)
+#define USB2_PHY_PLL_OFFSET_54 (0x2a)
+
+#define TUNING_DISCONNECT_THRESHOLD 0x3C
+
+#define PHY_21_BASE 0xfe03e000
+#define PHY_20_BASE 0xfe03c000
+#define PHY_COMP_BASE 0xfe03a000
+#define RESET_BASE 0xFE002000
+
+static int Rev_flag = 0;
+
+static struct phy usb_phys[4];
+
+/*Rev_flag == 0XB, g12b and revB, tl1 */
+/*Rev_flag == 1, sm1 */
+static void phy_aml_usb2_check_rev (void)
+{
+ cpu_id_t cpu_id = get_cpu_id();
+
+ if (cpu_id.family_id == MESON_CPU_MAJOR_ID_G12B) {
+ if (cpu_id.chip_rev == 0xb)
+ Rev_flag = 0xb;
+ else
+ Rev_flag = 0;
+ } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SM1) {
+ Rev_flag = MESON_CPU_MAJOR_ID_SM1;
+ } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_A1) {
+ Rev_flag = MESON_CPU_MAJOR_ID_A1;
+ } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_C1) {
+ Rev_flag = MESON_CPU_MAJOR_ID_C1;
+ } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) {
+ Rev_flag = MESON_CPU_MAJOR_ID_SC2;
+ } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_T7) {
+ Rev_flag = MESON_CPU_MAJOR_ID_T7;
+ }
+
+ return;
+}
+
+static int phy_aml_usb2_get_rev_type (void)
+{
+ int val = 0;
+
+ switch (Rev_flag) {
+ case MESON_CPU_MAJOR_ID_SM1:
+ case MESON_CPU_MAJOR_ID_A1:
+ case MESON_CPU_MAJOR_ID_C1:
+ case MESON_CPU_MAJOR_ID_SC2:
+ case MESON_CPU_MAJOR_ID_T7:
+ case 0xb:
+ val = 1;
+ break;
+ default:
+ printk("amlogic usb phy need tuning\n");
+ val = 0;
+ break;
+ }
+
+ return val;
+}
+
+int get_usbphy_baseinfo(struct phy *usb_phys)
+{
+ struct udevice *bus;
+ struct uclass *uc;
+ int ret, i;
+ int count;
+
+ if (usb_phys[0].dev && usb_phys[1].dev)
+ return 0;
+
+ ret = uclass_get(UCLASS_USB, &uc);
+ if (ret)
+ return ret;
+ uclass_foreach_dev(bus, uc) {
+ debug("bus->name=%s, bus->driver->name =%s\n",
+ bus->name, bus->driver->name);
+ count = dev_count_phandle_with_args(bus, "phys", "#phy-cells");
+ debug("usb phy count=%u\n", count);
+ if (count <= 0)
+ return count;
+ for (i = 0; i < count; i++) {
+ ret = generic_phy_get_by_index(bus, i, &usb_phys[i]);
+ if (ret && ret != -ENOENT) {
+ pr_err("Failed to get USB PHY%d for %s\n",
+ i, bus->name);
+ return ret;
+ }
+ ret = generic_phy_getinfo(&usb_phys[i]);
+ if (ret)
+ return ret;
+ }
+ }
+ return 0;
+}
+
+void usb_aml_detect_operation(int argc, char * const argv[])
+{
+ struct phy_aml_usb2_priv *usb2_priv;
+ struct phy_aml_usb3_priv *usb3_priv;
+ int ret;
+
+ ret = get_usbphy_baseinfo(usb_phys);
+ if (ret) {
+ printf("get usb dts failed\n");
+ return;
+ }
+ usb2_priv = dev_get_priv(usb_phys[0].dev);
+ usb3_priv = dev_get_priv(usb_phys[1].dev);
+
+ if (usb3_priv) {
+ printf("priv->usb3 port num = %d, config addr=0x%08x\n",
+ usb3_priv->usb3_port_num, usb3_priv->base_addr);
+ }
+ if (usb2_priv) {
+ printf("usb2 phy: config addr = 0x%08x, reset addr=0x%08x\n",
+ usb2_priv->base_addr, usb2_priv->reset_addr);
+
+ printf("usb2 phy: portnum=%d, phy-addr1= 0x%08x, phy-addr2= 0x%08x\n",
+ usb2_priv->u2_port_num, usb2_priv->usb_phy2_pll_base_addr[0],
+ usb2_priv->usb_phy2_pll_base_addr[1]);
+ printf("dwc2_a base addr: 0x%08x\n", usb2_priv->dwc2_a_addr);
+ }
+ phy_aml_usb2_check_rev();
+ printf("PHY version is 0x%02x\n", Rev_flag);
+}
+
+static void set_pll_Calibration_default(uint32_t phy2_pll_base)
+{
+ u32 tmp;
+
+ tmp = (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x8));
+ tmp &= 0xfff;
+ tmp |= (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10));
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10))
+ = tmp;
+}
+
+void usb_reset(unsigned int reset_addr, int bit){
+ *(volatile unsigned int *)(unsigned long)reset_addr = (1 << bit);
+}
+
+static void usb_enable_phy_pll (u32 base_addr)
+{
+ if (base_addr == PHY_20_BASE) {
+ *(volatile uint32_t *)(unsigned long)
+ RESETCTRL_RESET0_LEVEL |= (1 << PHY20_RESET_LEVEL_BIT);
+ } else if (base_addr == PHY_21_BASE) {
+ *(volatile uint32_t *)(unsigned long)
+ RESETCTRL_RESET0_LEVEL |= (1 << PHY21_RESET_LEVEL_BIT);
+ }
+}
+
+void set_usb_pll(uint32_t phy2_pll_base)
+{
+ int hardware_rev;
+
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))
+ = (USB2_PHY_PLL_OFFSET_40 | USB_PHY2_RESET | USB_PHY2_ENABLE);
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44)) =
+ USB2_PHY_PLL_OFFSET_44;
+ hardware_rev = phy_aml_usb2_get_rev_type();
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x48)) =
+ USB2_PHY_PLL_OFFSET_48;
+ udelay(100);
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x40))
+ = (((USB2_PHY_PLL_OFFSET_40) | (USB_PHY2_ENABLE))
+ & (~(USB_PHY2_RESET)));
+
+ if (hardware_rev) {
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50))
+ = USB2_PHY_PLL_OFFSET_50;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x54))
+ = USB2_PHY_PLL_OFFSET_54;
+ set_pll_Calibration_default(phy2_pll_base);
+ } else {
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50))
+ = USB2_PHY_PLL_OFFSET_50;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10))
+ = USB2_PHY_PLL_OFFSET_10;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x38))
+ = USB2_PHY_PLL_OFFSET_38_CLEAR;
+ }
+
+ (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0xc)) =
+ TUNING_DISCONNECT_THRESHOLD;
+ (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x34))
+ = USB2_PHY_PLL_OFFSET_34;
+ debug("tuning_disconnect_threshold=0x%x\n", TUNING_DISCONNECT_THRESHOLD);
+}
+
+int usb_save_phy_dev (unsigned int number, struct phy *phy)
+{
+ usb_phys[number].dev = phy->dev;
+ usb_phys[number].id = phy->id;
+ return 0;
+}
+
+void power_down_usb3(void)
+{
+ u32 val;
+#define USB_PHY30_BASE 0xFE062000
+
+ val = readl(USB_PHY30_BASE);
+ val &= (~(3 << 5));
+ val |= 0x1;
+ writel(val, USB_PHY30_BASE);
+ udelay(12);
+
+ val = readl(USB_PHY30_BASE + 0x18);
+ val &= (~(0x3 << 17));
+ val |= (0x1 << 17);
+ writel(val, USB_PHY30_BASE + 0x18);
+ udelay(12);
+}
+
+int usb2_phy_init (struct phy *phy) {
+ struct phy_aml_usb2_priv *priv = dev_get_priv(phy->dev);
+ struct u2p_aml_regs *u2p_aml_reg;
+ u2p_r0_t dev_u2p_r0;
+ u2p_r1_t dev_u2p_r1;
+ int i,cnt;
+
+ power_down_usb3();
+ usb_save_phy_dev(0, phy);
+ usb_enable_phy_pll(priv->base_addr);
+ //usb_set_power_domain();
+ phy_aml_usb2_check_rev();
+
+ if (priv->usb_phy2_pll_base_addr[0] == PHY_20_BASE) {
+ *(volatile unsigned int *)(unsigned long)priv->reset_addr = (1 << 6);
+
+ udelay(500);
+ priv->usbphy_reset_bit[0] = PHY20_RESET_LEVEL_BIT;
+ } else if (priv->usb_phy2_pll_base_addr[0] == PHY_21_BASE) {
+ *(volatile unsigned int *)(unsigned long)priv->reset_addr = (1 << 5);
+
+ udelay(500);
+ priv->usbphy_reset_bit[0] = PHY21_RESET_LEVEL_BIT;
+ }
+
+ for (i = 0; i < priv->u2_port_num; i++) {
+ u2p_aml_reg = (struct u2p_aml_regs *)((ulong)(priv->base_addr + i * PHY_REGISTER_SIZE));
+ dev_u2p_r0.d32 = u2p_aml_reg->u2p_r0;
+ dev_u2p_r0.b.host_device= 1;
+ dev_u2p_r0.b.POR= 0;
+ u2p_aml_reg->u2p_r0 = dev_u2p_r0.d32;
+ udelay(10);
+ *(volatile unsigned int *)(unsigned long)priv->reset_addr = (1 << priv->usbphy_reset_bit[i]);
+ udelay(50);
+
+ /* wait for phy ready */
+ dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
+ cnt = 0;
+ while (dev_u2p_r1.b.phy_rdy != 1) {
+ dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
+ /*we wait phy ready max 1ms, common is 100us*/
+ if (cnt > 200)
+ break;
+ else {
+ cnt++;
+ udelay(5);
+ }
+ }
+ }
+
+ for (i = 0; i < priv->u2_port_num; i++) {
+ debug("------set usb pll\n");
+ set_usb_pll(priv->usb_phy2_pll_base_addr[i]);
+ }
+ return 0;
+
+}
+
+int usb2_phy_tuning(uint32_t phy2_pll_base, int port)
+{
+ return 0;
+}
+
+/**************************************************************/
+/* device mode config */
+/**************************************************************/
+void usb_device_mode_init(int phy_num) {
+ u2p_r0_t dev_u2p_r0;
+ u2p_r1_t dev_u2p_r1;
+
+ usb_r0_t dev_usb_r0;
+ usb_r4_t dev_usb_r4;
+ int cnt;
+ u2p_aml_regs_t * u2p_aml_regs;
+ usb_aml_regs_t *usb_aml_regs;
+ unsigned int phy_base_addr, reset_addr;
+
+ phy_aml_usb2_check_rev();
+ if (phy_num == 1) {
+ u2p_aml_regs = (u2p_aml_regs_t * )((unsigned long)(PHY_COMP_BASE + PHY_REGISTER_SIZE));
+ usb_aml_regs = (usb_aml_regs_t * )((ulong)(PHY_COMP_BASE + 0x80));
+ phy_base_addr = PHY_21_BASE;
+ reset_addr = RESET_BASE;
+ } else {
+ u2p_aml_regs = (u2p_aml_regs_t * )((unsigned long)(PHY_COMP_BASE));
+ usb_aml_regs = (usb_aml_regs_t * )((ulong)(PHY_COMP_BASE + 0x80));
+ phy_base_addr = PHY_20_BASE;
+ reset_addr = RESET_BASE;
+ }
+
+ //printf("PHY2=0x%08x,PHY3=0x%08x\n", u2p_aml_regs, usb_aml_regs);
+ printf("PHY2=%p,PHY3=%p\n", u2p_aml_regs, usb_aml_regs);
+ //if ((*(volatile uint32_t *)(unsigned long)(phy_base_addr + 0x38)) != 0) {
+ //usb_phy_tuning_reset(phy_num);
+ //mdelay(150);
+ //}
+
+ //step 1: usb controller reset
+ usb_reset(reset_addr, USB_RESET_BIT);
+
+ // step 3: enable usb INT internal USB
+ dev_usb_r0.d32 = usb_aml_regs->usb_r0;
+ dev_usb_r0.b.u2d_ss_scaledown_mode = 0;
+ dev_usb_r0.b.u2d_act = 1;
+ usb_aml_regs->usb_r0 = dev_usb_r0.d32;
+
+ // step 4: disable usb phy sleep
+ dev_usb_r4.d32 = usb_aml_regs->usb_r4;
+ dev_usb_r4.b.p21_SLEEPM0 = 1;
+ usb_aml_regs->usb_r4 = dev_usb_r4.d32;
+
+ // step 5: config phy21 device mode
+ dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0;
+ dev_u2p_r0.b.host_device= 0;
+ dev_u2p_r0.b.POR= 0;
+ u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32;
+
+ udelay(10);
+ //step 6: phy21 reset
+ if (phy_num == 1) {
+ usb_reset(reset_addr, PHY21_RESET_LEVEL_BIT);
+ } else {
+ usb_reset(reset_addr, PHY20_RESET_LEVEL_BIT);
+ }
+ udelay(50);
+
+ // step 6: wait for phy ready
+ dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
+ cnt = 0;
+ while ((dev_u2p_r1.d32 & 0x00000001) != 1) {
+ dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
+ if (cnt > 200)
+ break;
+ else {
+ cnt++;
+ udelay(5);
+ }
+ }
+
+ //set_usb_phy21_pll();
+ set_usb_pll(phy_base_addr);
+ //--------------------------------------------------
+
+ // ------------- usb phy21 initinal end ----------
+
+ //--------------------------------------------------
+}
diff --git a/arch/arm/mach-mvebu/Kconfig b/arch/arm/mach-mvebu/Kconfig
index dc8167e..d1f7133 100644
--- a/arch/arm/mach-mvebu/Kconfig
+++ b/arch/arm/mach-mvebu/Kconfig
@@ -229,4 +229,3 @@
depends on SECURED_MODE_IMAGE
endif
-
diff --git a/arch/arm/mach-omap2/Kconfig b/arch/arm/mach-omap2/Kconfig
index 9a90bb8..58e545a 100644
--- a/arch/arm/mach-omap2/Kconfig
+++ b/arch/arm/mach-omap2/Kconfig
@@ -191,4 +191,3 @@
default "arch/arm/mach-omap2/u-boot-spl.lds"
endif
-
diff --git a/arch/arm/mach-omap2/am33xx/Kconfig b/arch/arm/mach-omap2/am33xx/Kconfig
index 7003a61..57284c4 100644
--- a/arch/arm/mach-omap2/am33xx/Kconfig
+++ b/arch/arm/mach-omap2/am33xx/Kconfig
@@ -304,4 +304,3 @@
image, this area is no longer used, and can be reclaimed
for run time use by the boot image.
endif
-
diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig
index f7421fe..0286b0d 100644
--- a/arch/arm/mach-omap2/omap3/Kconfig
+++ b/arch/arm/mach-omap2/omap3/Kconfig
@@ -221,4 +221,3 @@
source "board/lg/sniper/Kconfig"
endif
-
diff --git a/arch/arm/mach-omap2/omap4/Kconfig b/arch/arm/mach-omap2/omap4/Kconfig
index 5fd2761..49adb8e 100644
--- a/arch/arm/mach-omap2/omap4/Kconfig
+++ b/arch/arm/mach-omap2/omap4/Kconfig
@@ -27,4 +27,3 @@
source "board/amazon/kc1/Kconfig"
endif
-
diff --git a/arch/arm/mach-omap2/omap5/Kconfig b/arch/arm/mach-omap2/omap5/Kconfig
index f5b58fc..f083a4a 100644
--- a/arch/arm/mach-omap2/omap5/Kconfig
+++ b/arch/arm/mach-omap2/omap5/Kconfig
@@ -167,4 +167,3 @@
source "board/ti/am57xx/Kconfig"
endif
-
diff --git a/arch/arm/mach-orion5x/Kconfig b/arch/arm/mach-orion5x/Kconfig
index a4f4373..2984a3e 100644
--- a/arch/arm/mach-orion5x/Kconfig
+++ b/arch/arm/mach-orion5x/Kconfig
@@ -19,4 +19,3 @@
default "$(CPUDIR)/orion5x/u-boot-spl.lds" if ORION5X
endif
-
diff --git a/arch/arm/mach-owl/Kconfig b/arch/arm/mach-owl/Kconfig
index c47552c..199e772 100644
--- a/arch/arm/mach-owl/Kconfig
+++ b/arch/arm/mach-owl/Kconfig
@@ -25,4 +25,3 @@
source "board/ucRobotics/bubblegum_96/Kconfig"
endif
-
diff --git a/arch/arm/mach-qemu/Kconfig b/arch/arm/mach-qemu/Kconfig
index 9be04a3..a2e4b98 100644
--- a/arch/arm/mach-qemu/Kconfig
+++ b/arch/arm/mach-qemu/Kconfig
@@ -22,4 +22,3 @@
bool "Support qemu_arm64"
depends on ARCH_QEMU
select ARM64
-
diff --git a/arch/arm/mach-rmobile/Kconfig b/arch/arm/mach-rmobile/Kconfig
index bf6bbbf..c6e5f75 100644
--- a/arch/arm/mach-rmobile/Kconfig
+++ b/arch/arm/mach-rmobile/Kconfig
@@ -25,4 +25,3 @@
source "arch/arm/mach-rmobile/Kconfig.64"
endif
-
diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig
index ba34742..6dc8e3a 100644
--- a/arch/arm/mach-rockchip/Kconfig
+++ b/arch/arm/mach-rockchip/Kconfig
@@ -251,4 +251,3 @@
source "arch/arm/mach-rockchip/rk3399/Kconfig"
source "arch/arm/mach-rockchip/rv1108/Kconfig"
endif
-
diff --git a/arch/arm/mach-rockchip/rk3036/Kconfig b/arch/arm/mach-rockchip/rk3036/Kconfig
index 81755b7..c63db34 100644
--- a/arch/arm/mach-rockchip/rk3036/Kconfig
+++ b/arch/arm/mach-rockchip/rk3036/Kconfig
@@ -21,4 +21,3 @@
source "board/rockchip/kylin_rk3036/Kconfig"
endif
-
diff --git a/arch/arm/mach-rockchip/rk3128/Kconfig b/arch/arm/mach-rockchip/rk3128/Kconfig
index fb2c68f..40655a2 100644
--- a/arch/arm/mach-rockchip/rk3128/Kconfig
+++ b/arch/arm/mach-rockchip/rk3128/Kconfig
@@ -22,4 +22,3 @@
source "board/rockchip/evb_rk3128/Kconfig"
endif
-
diff --git a/arch/arm/mach-rockchip/rk3188/Kconfig b/arch/arm/mach-rockchip/rk3188/Kconfig
index 9244ed0..2bb3566 100644
--- a/arch/arm/mach-rockchip/rk3188/Kconfig
+++ b/arch/arm/mach-rockchip/rk3188/Kconfig
@@ -33,4 +33,3 @@
source "board/radxa/rock/Kconfig"
endif
-
diff --git a/arch/arm/mach-rockchip/rk322x/Kconfig b/arch/arm/mach-rockchip/rk322x/Kconfig
index 80be5a4..dc8071e 100644
--- a/arch/arm/mach-rockchip/rk322x/Kconfig
+++ b/arch/arm/mach-rockchip/rk322x/Kconfig
@@ -16,4 +16,3 @@
source "board/rockchip/evb_rk3229/Kconfig"
endif
-
diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig
index cfe5b1b..b5447e5 100644
--- a/arch/arm/mach-rockchip/rk3288/Kconfig
+++ b/arch/arm/mach-rockchip/rk3288/Kconfig
@@ -175,4 +175,3 @@
source "board/rockchip/tinker_rk3288/Kconfig"
endif
-
diff --git a/arch/arm/mach-rockchip/rk3328/Kconfig b/arch/arm/mach-rockchip/rk3328/Kconfig
index 603fbdd..43afba2 100644
--- a/arch/arm/mach-rockchip/rk3328/Kconfig
+++ b/arch/arm/mach-rockchip/rk3328/Kconfig
@@ -21,4 +21,3 @@
source "board/rockchip/evb_rk3328/Kconfig"
endif
-
diff --git a/arch/arm/mach-rockchip/rk3368/Kconfig b/arch/arm/mach-rockchip/rk3368/Kconfig
index 4a6e834..7c9b722 100644
--- a/arch/arm/mach-rockchip/rk3368/Kconfig
+++ b/arch/arm/mach-rockchip/rk3368/Kconfig
@@ -54,4 +54,3 @@
default "arch/arm/cpu/armv8/u-boot-spl.lds"
endif
-
diff --git a/arch/arm/mach-rockchip/rk3399/Kconfig b/arch/arm/mach-rockchip/rk3399/Kconfig
index ce3318d..8f18e33 100644
--- a/arch/arm/mach-rockchip/rk3399/Kconfig
+++ b/arch/arm/mach-rockchip/rk3399/Kconfig
@@ -66,4 +66,3 @@
source "board/vamrs/rock960_rk3399/Kconfig"
endif
-
diff --git a/arch/arm/mach-rockchip/rv1108/Kconfig b/arch/arm/mach-rockchip/rv1108/Kconfig
index 1df1ad0..8883aea 100644
--- a/arch/arm/mach-rockchip/rv1108/Kconfig
+++ b/arch/arm/mach-rockchip/rv1108/Kconfig
@@ -32,4 +32,3 @@
source board/elgin/elgin_rv1108/Kconfig
endif
-
diff --git a/arch/arm/mach-s5pc1xx/Kconfig b/arch/arm/mach-s5pc1xx/Kconfig
index ad39454..04acdaa 100644
--- a/arch/arm/mach-s5pc1xx/Kconfig
+++ b/arch/arm/mach-s5pc1xx/Kconfig
@@ -21,4 +21,3 @@
source "board/samsung/smdkc100/Kconfig"
endif
-
diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig
index 4626b00..e562d69 100644
--- a/arch/arm/mach-snapdragon/Kconfig
+++ b/arch/arm/mach-snapdragon/Kconfig
@@ -41,4 +41,3 @@
source "board/qualcomm/dragonboard820c/Kconfig"
endif
-
diff --git a/arch/arm/mach-socfpga/Kconfig b/arch/arm/mach-socfpga/Kconfig
index f9d98d5..5e87371 100644
--- a/arch/arm/mach-socfpga/Kconfig
+++ b/arch/arm/mach-socfpga/Kconfig
@@ -143,4 +143,3 @@
default "socfpga_vining_fpga" if TARGET_SOCFPGA_SAMTEC_VINING_FPGA
endif
-
diff --git a/arch/arm/mach-sti/Kconfig b/arch/arm/mach-sti/Kconfig
index cd03aca..f9a583a 100644
--- a/arch/arm/mach-sti/Kconfig
+++ b/arch/arm/mach-sti/Kconfig
@@ -29,4 +29,3 @@
source "board/st/stih410-b2260/Kconfig"
endif
-
diff --git a/arch/arm/mach-stm32/Kconfig b/arch/arm/mach-stm32/Kconfig
index a6b3c4b..cea5ee2 100644
--- a/arch/arm/mach-stm32/Kconfig
+++ b/arch/arm/mach-stm32/Kconfig
@@ -77,4 +77,3 @@
source "arch/arm/mach-stm32/stm32h7/Kconfig"
endif
-
diff --git a/arch/arm/mach-stm32/stm32f4/Kconfig b/arch/arm/mach-stm32/stm32f4/Kconfig
index 0989f1f..e8fae4d 100644
--- a/arch/arm/mach-stm32/stm32f4/Kconfig
+++ b/arch/arm/mach-stm32/stm32f4/Kconfig
@@ -14,4 +14,3 @@
source "board/st/stm32f469-discovery/Kconfig"
endif
-
diff --git a/arch/arm/mach-stm32/stm32f7/Kconfig b/arch/arm/mach-stm32/stm32f7/Kconfig
index d95d5bf..287e5ad 100644
--- a/arch/arm/mach-stm32/stm32f7/Kconfig
+++ b/arch/arm/mach-stm32/stm32f7/Kconfig
@@ -6,4 +6,3 @@
source "board/st/stm32f746-disco/Kconfig"
endif
-
diff --git a/arch/arm/mach-stm32/stm32h7/Kconfig b/arch/arm/mach-stm32/stm32h7/Kconfig
index f5062a1..55e6217 100644
--- a/arch/arm/mach-stm32/stm32h7/Kconfig
+++ b/arch/arm/mach-stm32/stm32h7/Kconfig
@@ -10,4 +10,3 @@
source "board/st/stm32h743-disco/Kconfig"
endif
-
diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig
index 610ed78..8a929fa 100644
--- a/arch/arm/mach-stm32mp/Kconfig
+++ b/arch/arm/mach-stm32mp/Kconfig
@@ -72,4 +72,3 @@
endif
endif
-
diff --git a/arch/arm/mach-sunxi/Kconfig b/arch/arm/mach-sunxi/Kconfig
index 1b1b999..3c54f51 100644
--- a/arch/arm/mach-sunxi/Kconfig
+++ b/arch/arm/mach-sunxi/Kconfig
@@ -990,4 +990,3 @@
utilizes the DRAM size will be enabled.
endif
-
diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c
deleted file mode 100644
index b74eaf2..0000000
--- a/arch/arm/mach-sunxi/board.c
+++ /dev/null
@@ -1,307 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * (C) Copyright 2012 Henrik Nordstrom <henrik@henriknordstrom.net>
- *
- * (C) Copyright 2007-2011
- * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
- * Tom Cubie <tangliang@allwinnertech.com>
- *
- * Some init for sunxi platform.
- */
-
-#include <common.h>
-#include <mmc.h>
-#include <i2c.h>
-#include <serial.h>
-#include <spl.h>
-#include <asm/gpio.h>
-#include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/gpio.h>
-#include <asm/arch/spl.h>
-#include <asm/arch/sys_proto.h>
-#include <asm/arch/timer.h>
-#include <asm/arch/tzpc.h>
-#include <asm/arch/mmc.h>
-
-#include <linux/compiler.h>
-
-struct fel_stash {
- uint32_t sp;
- uint32_t lr;
- uint32_t cpsr;
- uint32_t sctlr;
- uint32_t vbar;
- uint32_t cr;
-};
-
-struct fel_stash fel_stash __attribute__((section(".data")));
-
-#ifdef CONFIG_ARM64
-#include <asm/armv8/mmu.h>
-
-static struct mm_region sunxi_mem_map[] = {
- {
- /* SRAM, MMIO regions */
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0x40000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE
- }, {
- /* RAM */
- .virt = 0x40000000UL,
- .phys = 0x40000000UL,
- .size = 0xC0000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- /* List terminator */
- 0,
- }
-};
-struct mm_region *mem_map = sunxi_mem_map;
-#endif
-
-static int gpio_init(void)
-{
-#if CONFIG_CONS_INDEX == 1 && defined(CONFIG_UART0_PORT_F)
-#if defined(CONFIG_MACH_SUN4I) || \
- defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_R40)
- /* disable GPB22,23 as uart0 tx,rx to avoid conflict */
- sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUNXI_GPIO_INPUT);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUNXI_GPIO_INPUT);
-#endif
-#if defined(CONFIG_MACH_SUN8I) && !defined(CONFIG_MACH_SUN8I_R40)
- sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUN8I_GPF_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUN8I_GPF_UART0);
-#else
- sunxi_gpio_set_cfgpin(SUNXI_GPF(2), SUNXI_GPF_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPF(4), SUNXI_GPF_UART0);
-#endif
- sunxi_gpio_set_pull(SUNXI_GPF(4), 1);
-#elif CONFIG_CONS_INDEX == 1 && (defined(CONFIG_MACH_SUN4I) || \
- defined(CONFIG_MACH_SUN7I) || \
- defined(CONFIG_MACH_SUN8I_R40))
- sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB_UART0);
- sunxi_gpio_set_pull(SUNXI_GPB(23), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN5I)
- sunxi_gpio_set_cfgpin(SUNXI_GPB(19), SUN5I_GPB_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(20), SUN5I_GPB_UART0);
- sunxi_gpio_set_pull(SUNXI_GPB(20), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN6I)
- sunxi_gpio_set_cfgpin(SUNXI_GPH(20), SUN6I_GPH_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPH(21), SUN6I_GPH_UART0);
- sunxi_gpio_set_pull(SUNXI_GPH(21), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A33)
- sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_A33_GPB_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_A33_GPB_UART0);
- sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUNXI_H3_H5)
- sunxi_gpio_set_cfgpin(SUNXI_GPA(4), SUN8I_H3_GPA_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPA(5), SUN8I_H3_GPA_UART0);
- sunxi_gpio_set_pull(SUNXI_GPA(5), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I)
- sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN50I_GPB_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN50I_GPB_UART0);
- sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN50I_H6)
- sunxi_gpio_set_cfgpin(SUNXI_GPH(0), SUN50I_H6_GPH_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPH(1), SUN50I_H6_GPH_UART0);
- sunxi_gpio_set_pull(SUNXI_GPH(1), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_A83T)
- sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_A83T_GPB_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(10), SUN8I_A83T_GPB_UART0);
- sunxi_gpio_set_pull(SUNXI_GPB(10), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN8I_V3S)
- sunxi_gpio_set_cfgpin(SUNXI_GPB(8), SUN8I_V3S_GPB_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(9), SUN8I_V3S_GPB_UART0);
- sunxi_gpio_set_pull(SUNXI_GPB(9), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 1 && defined(CONFIG_MACH_SUN9I)
- sunxi_gpio_set_cfgpin(SUNXI_GPH(12), SUN9I_GPH_UART0);
- sunxi_gpio_set_cfgpin(SUNXI_GPH(13), SUN9I_GPH_UART0);
- sunxi_gpio_set_pull(SUNXI_GPH(13), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 2 && defined(CONFIG_MACH_SUN5I)
- sunxi_gpio_set_cfgpin(SUNXI_GPG(3), SUN5I_GPG_UART1);
- sunxi_gpio_set_cfgpin(SUNXI_GPG(4), SUN5I_GPG_UART1);
- sunxi_gpio_set_pull(SUNXI_GPG(4), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 3 && defined(CONFIG_MACH_SUN8I)
- sunxi_gpio_set_cfgpin(SUNXI_GPB(0), SUN8I_GPB_UART2);
- sunxi_gpio_set_cfgpin(SUNXI_GPB(1), SUN8I_GPB_UART2);
- sunxi_gpio_set_pull(SUNXI_GPB(1), SUNXI_GPIO_PULL_UP);
-#elif CONFIG_CONS_INDEX == 5 && defined(CONFIG_MACH_SUN8I)
- sunxi_gpio_set_cfgpin(SUNXI_GPL(2), SUN8I_GPL_R_UART);
- sunxi_gpio_set_cfgpin(SUNXI_GPL(3), SUN8I_GPL_R_UART);
- sunxi_gpio_set_pull(SUNXI_GPL(3), SUNXI_GPIO_PULL_UP);
-#else
-#error Unsupported console port number. Please fix pin mux settings in board.c
-#endif
-
- return 0;
-}
-
-#if defined(CONFIG_SPL_BOARD_LOAD_IMAGE) && defined(CONFIG_SPL_BUILD)
-static int spl_board_load_image(struct spl_image_info *spl_image,
- struct spl_boot_device *bootdev)
-{
- debug("Returning to FEL sp=%x, lr=%x\n", fel_stash.sp, fel_stash.lr);
- return_to_fel(fel_stash.sp, fel_stash.lr);
-
- return 0;
-}
-SPL_LOAD_IMAGE_METHOD("FEL", 0, BOOT_DEVICE_BOARD, spl_board_load_image);
-#endif
-
-void s_init(void)
-{
- /*
- * Undocumented magic taken from boot0, without this DRAM
- * access gets messed up (seems cache related).
- * The boot0 sources describe this as: "config ema for cache sram"
- */
-#if defined CONFIG_MACH_SUN6I
- setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
-#elif defined CONFIG_MACH_SUN8I
- __maybe_unused uint version;
-
- /* Unlock sram version info reg, read it, relock */
- setbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
- version = readl(SUNXI_SRAMC_BASE + 0x24) >> 16;
- clrbits_le32(SUNXI_SRAMC_BASE + 0x24, (1 << 15));
-
- /*
- * Ideally this would be a switch case, but we do not know exactly
- * which versions there are and which version needs which settings,
- * so reproduce the per SoC code from the BSP.
- */
-#if defined CONFIG_MACH_SUN8I_A23
- if (version == 0x1650)
- setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0x1800);
- else /* 0x1661 ? */
- setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
-#elif defined CONFIG_MACH_SUN8I_A33
- if (version != 0x1667)
- setbits_le32(SUNXI_SRAMC_BASE + 0x44, 0xc0);
-#endif
- /* A83T BSP never modifies SUNXI_SRAMC_BASE + 0x44 */
- /* No H3 BSP, boot0 seems to not modify SUNXI_SRAMC_BASE + 0x44 */
-#endif
-
-#if !defined(CONFIG_ARM_CORTEX_CPU_IS_UP) && !defined(CONFIG_ARM64)
- /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */
- asm volatile(
- "mrc p15, 0, r0, c1, c0, 1\n"
- "orr r0, r0, #1 << 6\n"
- "mcr p15, 0, r0, c1, c0, 1\n"
- ::: "r0");
-#endif
-#if defined CONFIG_MACH_SUN6I || defined CONFIG_MACH_SUN8I_H3
- /* Enable non-secure access to some peripherals */
- tzpc_init();
-#endif
-
- clock_init();
- timer_init();
- gpio_init();
-#ifndef CONFIG_DM_I2C
- i2c_init_board();
-#endif
- eth_init_board();
-}
-
-/* The sunxi internal brom will try to loader external bootloader
- * from mmc0, nand flash, mmc2.
- */
-uint32_t sunxi_get_boot_device(void)
-{
- int boot_source;
-
- /*
- * When booting from the SD card or NAND memory, the "eGON.BT0"
- * signature is expected to be found in memory at the address 0x0004
- * (see the "mksunxiboot" tool, which generates this header).
- *
- * When booting in the FEL mode over USB, this signature is patched in
- * memory and replaced with something else by the 'fel' tool. This other
- * signature is selected in such a way, that it can't be present in a
- * valid bootable SD card image (because the BROM would refuse to
- * execute the SPL in this case).
- *
- * This checks for the signature and if it is not found returns to
- * the FEL code in the BROM to wait and receive the main u-boot
- * binary over USB. If it is found, it determines where SPL was
- * read from.
- */
- if (!is_boot0_magic(SPL_ADDR + 4)) /* eGON.BT0 */
- return BOOT_DEVICE_BOARD;
-
- boot_source = readb(SPL_ADDR + 0x28);
- switch (boot_source) {
- case SUNXI_BOOTED_FROM_MMC0:
- return BOOT_DEVICE_MMC1;
- case SUNXI_BOOTED_FROM_NAND:
- return BOOT_DEVICE_NAND;
- case SUNXI_BOOTED_FROM_MMC2:
- return BOOT_DEVICE_MMC2;
- case SUNXI_BOOTED_FROM_SPI:
- return BOOT_DEVICE_SPI;
- }
-
- panic("Unknown boot source %d\n", boot_source);
- return -1; /* Never reached */
-}
-
-#ifdef CONFIG_SPL_BUILD
-u32 spl_boot_device(void)
-{
- return sunxi_get_boot_device();
-}
-
-void board_init_f(ulong dummy)
-{
- spl_init();
- preloader_console_init();
-
-#ifdef CONFIG_SPL_I2C_SUPPORT
- /* Needed early by sunxi_board_init if PMU is enabled */
- i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
-#endif
- sunxi_board_init();
-}
-#endif
-
-void reset_cpu(ulong addr)
-{
-#if defined(CONFIG_SUNXI_GEN_SUN4I) || defined(CONFIG_MACH_SUN8I_R40)
- static const struct sunxi_wdog *wdog =
- &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
-
- /* Set the watchdog for its shortest interval (.5s) and wait */
- writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
- writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
-
- while (1) {
- /* sun5i sometimes gets stuck without this */
- writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode);
- }
-#elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6)
- static const struct sunxi_wdog *wdog =
- ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
-
- /* Set the watchdog for its shortest interval (.5s) and wait */
- writel(WDT_CFG_RESET, &wdog->cfg);
- writel(WDT_MODE_EN, &wdog->mode);
- writel(WDT_CTRL_KEY | WDT_CTRL_RESTART, &wdog->ctl);
- while (1) { }
-#endif
-}
-
-#if !defined(CONFIG_SYS_DCACHE_OFF) && !defined(CONFIG_ARM64)
-void enable_caches(void)
-{
- /* Enable D-cache. I-cache is already enabled in start.S */
- dcache_enable();
-}
-#endif
diff --git a/arch/arm/mach-tegra/Kconfig b/arch/arm/mach-tegra/Kconfig
index 59d9d38..86b1cd1 100644
--- a/arch/arm/mach-tegra/Kconfig
+++ b/arch/arm/mach-tegra/Kconfig
@@ -156,4 +156,3 @@
button.
endif
-
diff --git a/arch/arm/mach-tegra/tegra114/Kconfig b/arch/arm/mach-tegra/tegra114/Kconfig
index 74dcd36..5f0f909 100644
--- a/arch/arm/mach-tegra/tegra114/Kconfig
+++ b/arch/arm/mach-tegra/tegra114/Kconfig
@@ -16,4 +16,3 @@
source "board/nvidia/dalmore/Kconfig"
endif
-
diff --git a/arch/arm/mach-tegra/tegra124/Kconfig b/arch/arm/mach-tegra/tegra124/Kconfig
index 6afa175..6fa31ea 100644
--- a/arch/arm/mach-tegra/tegra124/Kconfig
+++ b/arch/arm/mach-tegra/tegra124/Kconfig
@@ -55,4 +55,3 @@
source "board/toradex/apalis-tk1/Kconfig"
endif
-
diff --git a/arch/arm/mach-tegra/tegra186/Kconfig b/arch/arm/mach-tegra/tegra186/Kconfig
index 4d1181f..479c095 100644
--- a/arch/arm/mach-tegra/tegra186/Kconfig
+++ b/arch/arm/mach-tegra/tegra186/Kconfig
@@ -27,4 +27,3 @@
source "board/nvidia/p2771-0000/Kconfig"
endif
-
diff --git a/arch/arm/mach-tegra/tegra20/Kconfig b/arch/arm/mach-tegra/tegra20/Kconfig
index cc1d105..5c4d35b 100644
--- a/arch/arm/mach-tegra/tegra20/Kconfig
+++ b/arch/arm/mach-tegra/tegra20/Kconfig
@@ -56,4 +56,3 @@
source "board/toradex/colibri_t20/Kconfig"
endif
-
diff --git a/arch/arm/mach-tegra/tegra210/Kconfig b/arch/arm/mach-tegra/tegra210/Kconfig
index cfa3734..250738a 100644
--- a/arch/arm/mach-tegra/tegra210/Kconfig
+++ b/arch/arm/mach-tegra/tegra210/Kconfig
@@ -49,4 +49,3 @@
source "board/nvidia/p2571/Kconfig"
endif
-
diff --git a/arch/arm/mach-tegra/tegra30/Kconfig b/arch/arm/mach-tegra/tegra30/Kconfig
index 6e60b5f..85b8ce2 100644
--- a/arch/arm/mach-tegra/tegra30/Kconfig
+++ b/arch/arm/mach-tegra/tegra30/Kconfig
@@ -36,4 +36,3 @@
source "board/avionic-design/tec-ng/Kconfig"
endif
-
diff --git a/arch/arm/mach-uniphier/Kconfig b/arch/arm/mach-uniphier/Kconfig
index 35de557..bfb445a 100644
--- a/arch/arm/mach-uniphier/Kconfig
+++ b/arch/arm/mach-uniphier/Kconfig
@@ -120,4 +120,3 @@
config SYS_SOC
default "uniphier-v7" if ARCH_UNIPHIER_LD4_SLD8 || ARCH_UNIPHIER_V7_MULTI
endif
-
diff --git a/arch/arm/mach-versal/Kconfig b/arch/arm/mach-versal/Kconfig
index acf7b0a..9cee97b 100644
--- a/arch/arm/mach-versal/Kconfig
+++ b/arch/arm/mach-versal/Kconfig
@@ -42,4 +42,3 @@
depends on OF_BOARD
endif
-
diff --git a/arch/arm/mach-zynq/Kconfig b/arch/arm/mach-zynq/Kconfig
index 3e82518..a599ed6 100644
--- a/arch/arm/mach-zynq/Kconfig
+++ b/arch/arm/mach-zynq/Kconfig
@@ -71,4 +71,3 @@
default 52000000
endif
-
diff --git a/arch/arm/mach-zynqmp-r5/Kconfig b/arch/arm/mach-zynqmp-r5/Kconfig
index 552c02e..5e01754 100644
--- a/arch/arm/mach-zynqmp-r5/Kconfig
+++ b/arch/arm/mach-zynqmp-r5/Kconfig
@@ -25,4 +25,3 @@
default 0x600
endif
-
diff --git a/arch/m68k/Kconfig b/arch/m68k/Kconfig
index 8c331f7..1f6df5c 100644
--- a/arch/m68k/Kconfig
+++ b/arch/m68k/Kconfig
@@ -225,4 +225,3 @@
source "board/sysam/stmark2/Kconfig"
endmenu
-
diff --git a/arch/microblaze/Kconfig b/arch/microblaze/Kconfig
index a3b90b7..5cc68d6 100644
--- a/arch/microblaze/Kconfig
+++ b/arch/microblaze/Kconfig
@@ -26,4 +26,3 @@
default "arch/microblaze/cpu/u-boot-spl.lds"
endmenu
-
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index bc0a82a..194f4f3 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconfig
@@ -479,4 +479,3 @@
endif
endmenu
-
diff --git a/arch/mips/mach-ath79/Kconfig b/arch/mips/mach-ath79/Kconfig
index 9f70624..bc86f59 100644
--- a/arch/mips/mach-ath79/Kconfig
+++ b/arch/mips/mach-ath79/Kconfig
@@ -55,4 +55,3 @@
source "board/tplink/wdr4300/Kconfig"
endmenu
-
diff --git a/arch/mips/mach-bmips/Kconfig b/arch/mips/mach-bmips/Kconfig
index 74eac2b..b259a93 100644
--- a/arch/mips/mach-bmips/Kconfig
+++ b/arch/mips/mach-bmips/Kconfig
@@ -278,4 +278,3 @@
source "board/sfr/nb4_ser/Kconfig"
endmenu
-
diff --git a/arch/mips/mach-jz47xx/Kconfig b/arch/mips/mach-jz47xx/Kconfig
index d16829f..dcaac01 100644
--- a/arch/mips/mach-jz47xx/Kconfig
+++ b/arch/mips/mach-jz47xx/Kconfig
@@ -24,4 +24,3 @@
source "board/imgtec/ci20/Kconfig"
endmenu
-
diff --git a/arch/mips/mach-mscc/Kconfig b/arch/mips/mach-mscc/Kconfig
index 7496e11..0e35b77 100644
--- a/arch/mips/mach-mscc/Kconfig
+++ b/arch/mips/mach-mscc/Kconfig
@@ -84,4 +84,3 @@
source "board/mscc/luton/Kconfig"
endmenu
-
diff --git a/arch/mips/mach-mt7620/Kconfig b/arch/mips/mach-mt7620/Kconfig
index dbafb87..4ebcb4b 100644
--- a/arch/mips/mach-mt7620/Kconfig
+++ b/arch/mips/mach-mt7620/Kconfig
@@ -134,4 +134,3 @@
source "board/seeed/linkit-smart-7688/Kconfig"
endmenu
-
diff --git a/arch/mips/mach-pic32/Kconfig b/arch/mips/mach-pic32/Kconfig
index 6bd850a..5f13bf1 100644
--- a/arch/mips/mach-pic32/Kconfig
+++ b/arch/mips/mach-pic32/Kconfig
@@ -34,4 +34,3 @@
source "board/microchip/pic32mzda/Kconfig"
endmenu
-
diff --git a/arch/nds32/Kconfig b/arch/nds32/Kconfig
index 6b1683a..d72ff46 100644
--- a/arch/nds32/Kconfig
+++ b/arch/nds32/Kconfig
@@ -20,4 +20,3 @@
source "board/AndesTech/adp-ae3xx/Kconfig"
endmenu
-
diff --git a/arch/nios2/Kconfig b/arch/nios2/Kconfig
index ac60b5c..bb4fb2a 100644
--- a/arch/nios2/Kconfig
+++ b/arch/nios2/Kconfig
@@ -12,4 +12,3 @@
should be included from include/config.h.
endmenu
-
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig
index 8f954ee..c727d91 100644
--- a/arch/powerpc/Kconfig
+++ b/arch/powerpc/Kconfig
@@ -45,4 +45,3 @@
source "arch/powerpc/cpu/mpc8xx/Kconfig"
endmenu
-
diff --git a/arch/powerpc/cpu/mpc83xx/Kconfig b/arch/powerpc/cpu/mpc83xx/Kconfig
index 2c9f9cd..571cf8f 100644
--- a/arch/powerpc/cpu/mpc83xx/Kconfig
+++ b/arch/powerpc/cpu/mpc83xx/Kconfig
@@ -115,4 +115,3 @@
source "board/gdsys/mpc8308/Kconfig"
endmenu
-
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig
index b50b916..309ca29 100644
--- a/arch/powerpc/cpu/mpc85xx/Kconfig
+++ b/arch/powerpc/cpu/mpc85xx/Kconfig
@@ -1590,4 +1590,3 @@
source "board/Arcturus/ucp1020/Kconfig"
endmenu
-
diff --git a/arch/powerpc/cpu/mpc86xx/Kconfig b/arch/powerpc/cpu/mpc86xx/Kconfig
index a7e7867..2cc180d 100644
--- a/arch/powerpc/cpu/mpc86xx/Kconfig
+++ b/arch/powerpc/cpu/mpc86xx/Kconfig
@@ -67,4 +67,3 @@
source "board/xes/xpedite517x/Kconfig"
endmenu
-
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index 7ee95ff..b0e90a0 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -177,4 +177,3 @@
source "board/cssi/MCR3000/Kconfig"
endmenu
-
diff --git a/arch/riscv/Kconfig b/arch/riscv/Kconfig
index 6944f22..c45e4d7 100644
--- a/arch/riscv/Kconfig
+++ b/arch/riscv/Kconfig
@@ -117,4 +117,3 @@
default 0x1000
endmenu
-
diff --git a/arch/riscv/cpu/ax25/Kconfig b/arch/riscv/cpu/ax25/Kconfig
index 936929a..e9dbca2 100644
--- a/arch/riscv/cpu/ax25/Kconfig
+++ b/arch/riscv/cpu/ax25/Kconfig
@@ -12,4 +12,3 @@
Provide Andes Technology AndeStar V5 families specific cache support.
endif
-
diff --git a/arch/riscv/cpu/qemu/Kconfig b/arch/riscv/cpu/qemu/Kconfig
index 82b4b4d..f48751e 100644
--- a/arch/riscv/cpu/qemu/Kconfig
+++ b/arch/riscv/cpu/qemu/Kconfig
@@ -10,4 +10,3 @@
imply RISCV_TIMER
imply SIFIVE_CLINT if RISCV_MMODE
imply CMD_CPU
-
diff --git a/arch/sandbox/Kconfig b/arch/sandbox/Kconfig
index d71bea3..2a08533 100644
--- a/arch/sandbox/Kconfig
+++ b/arch/sandbox/Kconfig
@@ -47,4 +47,3 @@
default 64 if HOST_64BIT
endmenu
-
diff --git a/arch/sh/Kconfig b/arch/sh/Kconfig
index 30b366e..d20761e 100644
--- a/arch/sh/Kconfig
+++ b/arch/sh/Kconfig
@@ -150,4 +150,3 @@
source "board/shmin/Kconfig"
endmenu
-
diff --git a/arch/sh/lib/Kconfig b/arch/sh/lib/Kconfig
index 0e8d7bc..cec8d09 100644
--- a/arch/sh/lib/Kconfig
+++ b/arch/sh/lib/Kconfig
@@ -4,4 +4,3 @@
help
This is special SH-specific command to boot a zImage (compressed
Linux image) on SH-architecture boards.
-
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 8060ef7..e052093 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@ -783,4 +783,3 @@
This is most likely due to a large ACPI DSDT table is used.
endmenu
-
diff --git a/arch/x86/cpu/baytrail/Kconfig b/arch/x86/cpu/baytrail/Kconfig
index 33f864b..d2c3473 100644
--- a/arch/x86/cpu/baytrail/Kconfig
+++ b/arch/x86/cpu/baytrail/Kconfig
@@ -40,4 +40,3 @@
select DEBUG_UART_BOARD_INIT
endif
-
diff --git a/arch/x86/cpu/braswell/Kconfig b/arch/x86/cpu/braswell/Kconfig
index f391260..2676fe6 100644
--- a/arch/x86/cpu/braswell/Kconfig
+++ b/arch/x86/cpu/braswell/Kconfig
@@ -31,4 +31,3 @@
default 0xfff20000
endif
-
diff --git a/arch/x86/cpu/broadwell/Kconfig b/arch/x86/cpu/broadwell/Kconfig
index ad628df..5b015c8 100644
--- a/arch/x86/cpu/broadwell/Kconfig
+++ b/arch/x86/cpu/broadwell/Kconfig
@@ -40,4 +40,3 @@
default 0x800000
endif
-
diff --git a/arch/x86/cpu/coreboot/Kconfig b/arch/x86/cpu/coreboot/Kconfig
index 9eda459..93f61f2 100644
--- a/arch/x86/cpu/coreboot/Kconfig
+++ b/arch/x86/cpu/coreboot/Kconfig
@@ -26,4 +26,3 @@
imply CBMEM_CONSOLE
endif
-
diff --git a/arch/x86/cpu/efi/Kconfig b/arch/x86/cpu/efi/Kconfig
index 9e631a9..e0975d3 100644
--- a/arch/x86/cpu/efi/Kconfig
+++ b/arch/x86/cpu/efi/Kconfig
@@ -9,4 +9,3 @@
default 0x20000
endif
-
diff --git a/arch/x86/cpu/ivybridge/Kconfig b/arch/x86/cpu/ivybridge/Kconfig
index 1dd6970..5f0e608 100644
--- a/arch/x86/cpu/ivybridge/Kconfig
+++ b/arch/x86/cpu/ivybridge/Kconfig
@@ -72,4 +72,3 @@
default y
endif
-
diff --git a/arch/x86/cpu/qemu/Kconfig b/arch/x86/cpu/qemu/Kconfig
index 27aa66d..fdf558d 100644
--- a/arch/x86/cpu/qemu/Kconfig
+++ b/arch/x86/cpu/qemu/Kconfig
@@ -32,4 +32,3 @@
This device is defined in ACPI specification, with 16 bytes in size.
endif
-
diff --git a/arch/x86/cpu/quark/Kconfig b/arch/x86/cpu/quark/Kconfig
index bee49d6..3a18cb0 100644
--- a/arch/x86/cpu/quark/Kconfig
+++ b/arch/x86/cpu/quark/Kconfig
@@ -135,4 +135,3 @@
default 400
endif
-
diff --git a/arch/x86/cpu/queensbay/Kconfig b/arch/x86/cpu/queensbay/Kconfig
index 6578e2a..c9e0fda 100644
--- a/arch/x86/cpu/queensbay/Kconfig
+++ b/arch/x86/cpu/queensbay/Kconfig
@@ -65,4 +65,3 @@
card's VGA BIOS and use that card for the graphics console.
endif
-
diff --git a/arch/x86/cpu/tangier/Kconfig b/arch/x86/cpu/tangier/Kconfig
index 501d0ce..a3bd167 100644
--- a/arch/x86/cpu/tangier/Kconfig
+++ b/arch/x86/cpu/tangier/Kconfig
@@ -32,4 +32,3 @@
default 0xf9100000
endif
-
diff --git a/arch/xtensa/Kconfig b/arch/xtensa/Kconfig
index a71ff6d..2ba7132 100644
--- a/arch/xtensa/Kconfig
+++ b/arch/xtensa/Kconfig
@@ -19,4 +19,3 @@
source "board/cadence/xtfpga/Kconfig"
endmenu
-
diff --git a/board/8dtech/eco5pk/Kconfig b/board/8dtech/eco5pk/Kconfig
index f2b0c84..5553566 100644
--- a/board/8dtech/eco5pk/Kconfig
+++ b/board/8dtech/eco5pk/Kconfig
@@ -10,4 +10,3 @@
default "eco5pk"
endif
-
diff --git a/board/AndesTech/adp-ae3xx/Kconfig b/board/AndesTech/adp-ae3xx/Kconfig
index 42cd3eb..8ec69d6 100644
--- a/board/AndesTech/adp-ae3xx/Kconfig
+++ b/board/AndesTech/adp-ae3xx/Kconfig
@@ -16,4 +16,3 @@
default "adp-ae3xx"
endif
-
diff --git a/board/AndesTech/adp-ag101p/Kconfig b/board/AndesTech/adp-ag101p/Kconfig
index 2f5cfa5..5e8aa22 100644
--- a/board/AndesTech/adp-ag101p/Kconfig
+++ b/board/AndesTech/adp-ag101p/Kconfig
@@ -16,4 +16,3 @@
default "adp-ag101p"
endif
-
diff --git a/board/AndesTech/ax25-ae350/Kconfig b/board/AndesTech/ax25-ae350/Kconfig
index 4fa080a..44cb302 100644
--- a/board/AndesTech/ax25-ae350/Kconfig
+++ b/board/AndesTech/ax25-ae350/Kconfig
@@ -26,4 +26,3 @@
select RISCV_NDS
endif
-
diff --git a/board/Arcturus/ucp1020/Kconfig b/board/Arcturus/ucp1020/Kconfig
index 9e1c0eb..fe2c3be 100644
--- a/board/Arcturus/ucp1020/Kconfig
+++ b/board/Arcturus/ucp1020/Kconfig
@@ -34,4 +34,3 @@
endif
endif
-
diff --git a/board/Barix/ipam390/Kconfig b/board/Barix/ipam390/Kconfig
index 48c0452..b85d4da 100644
--- a/board/Barix/ipam390/Kconfig
+++ b/board/Barix/ipam390/Kconfig
@@ -10,4 +10,3 @@
default "ipam390"
endif
-
diff --git a/board/BuR/brppt1/Kconfig b/board/BuR/brppt1/Kconfig
index 2b6071b..e006c80 100644
--- a/board/BuR/brppt1/Kconfig
+++ b/board/BuR/brppt1/Kconfig
@@ -13,4 +13,3 @@
default "brppt1"
endif
-
diff --git a/board/BuR/brxre1/Kconfig b/board/BuR/brxre1/Kconfig
index 8694b1e..389e523 100644
--- a/board/BuR/brxre1/Kconfig
+++ b/board/BuR/brxre1/Kconfig
@@ -13,4 +13,3 @@
default "brxre1"
endif
-
diff --git a/board/BuS/eb_cpu5282/Kconfig b/board/BuS/eb_cpu5282/Kconfig
index 118d358..237dc1b 100644
--- a/board/BuS/eb_cpu5282/Kconfig
+++ b/board/BuS/eb_cpu5282/Kconfig
@@ -13,4 +13,3 @@
default "eb_cpu5282"
endif
-
diff --git a/board/CarMediaLab/flea3/Kconfig b/board/CarMediaLab/flea3/Kconfig
index 5a62f4c..7113f2b 100644
--- a/board/CarMediaLab/flea3/Kconfig
+++ b/board/CarMediaLab/flea3/Kconfig
@@ -13,4 +13,3 @@
default "flea3"
endif
-
diff --git a/board/LaCie/edminiv2/Kconfig b/board/LaCie/edminiv2/Kconfig
index e6ad572..ac3fe3f 100644
--- a/board/LaCie/edminiv2/Kconfig
+++ b/board/LaCie/edminiv2/Kconfig
@@ -10,4 +10,3 @@
default "edminiv2"
endif
-
diff --git a/board/LaCie/net2big_v2/Kconfig b/board/LaCie/net2big_v2/Kconfig
index 4385176..ba460db 100644
--- a/board/LaCie/net2big_v2/Kconfig
+++ b/board/LaCie/net2big_v2/Kconfig
@@ -10,4 +10,3 @@
default "lacie_kw"
endif
-
diff --git a/board/LaCie/netspace_v2/Kconfig b/board/LaCie/netspace_v2/Kconfig
index 149f76b..930b822 100644
--- a/board/LaCie/netspace_v2/Kconfig
+++ b/board/LaCie/netspace_v2/Kconfig
@@ -10,4 +10,3 @@
default "lacie_kw"
endif
-
diff --git a/board/Marvell/aspenite/Kconfig b/board/Marvell/aspenite/Kconfig
index 3f3ce14..4dd49c4 100644
--- a/board/Marvell/aspenite/Kconfig
+++ b/board/Marvell/aspenite/Kconfig
@@ -13,4 +13,3 @@
default "aspenite"
endif
-
diff --git a/board/Marvell/dreamplug/Kconfig b/board/Marvell/dreamplug/Kconfig
index bd53248..f65ff73 100644
--- a/board/Marvell/dreamplug/Kconfig
+++ b/board/Marvell/dreamplug/Kconfig
@@ -10,4 +10,3 @@
default "dreamplug"
endif
-
diff --git a/board/Marvell/gplugd/Kconfig b/board/Marvell/gplugd/Kconfig
index 9632c8a..d944816 100644
--- a/board/Marvell/gplugd/Kconfig
+++ b/board/Marvell/gplugd/Kconfig
@@ -13,4 +13,3 @@
default "gplugd"
endif
-
diff --git a/board/Marvell/guruplug/Kconfig b/board/Marvell/guruplug/Kconfig
index e75adf5..529e6e3 100644
--- a/board/Marvell/guruplug/Kconfig
+++ b/board/Marvell/guruplug/Kconfig
@@ -10,4 +10,3 @@
default "guruplug"
endif
-
diff --git a/board/Marvell/openrd/Kconfig b/board/Marvell/openrd/Kconfig
index 5c40ed8..124b66d 100644
--- a/board/Marvell/openrd/Kconfig
+++ b/board/Marvell/openrd/Kconfig
@@ -10,4 +10,3 @@
default "openrd"
endif
-
diff --git a/board/Marvell/sheevaplug/Kconfig b/board/Marvell/sheevaplug/Kconfig
index 0cd781b..e5f9284 100644
--- a/board/Marvell/sheevaplug/Kconfig
+++ b/board/Marvell/sheevaplug/Kconfig
@@ -10,4 +10,3 @@
default "sheevaplug"
endif
-
diff --git a/board/Seagate/dockstar/Kconfig b/board/Seagate/dockstar/Kconfig
index c2ace8e..b50cd3b 100644
--- a/board/Seagate/dockstar/Kconfig
+++ b/board/Seagate/dockstar/Kconfig
@@ -10,4 +10,3 @@
default "dockstar"
endif
-
diff --git a/board/Seagate/goflexhome/Kconfig b/board/Seagate/goflexhome/Kconfig
index 47059ad..0cbeaf7 100644
--- a/board/Seagate/goflexhome/Kconfig
+++ b/board/Seagate/goflexhome/Kconfig
@@ -10,4 +10,3 @@
default "goflexhome"
endif
-
diff --git a/board/Seagate/nas220/Kconfig b/board/Seagate/nas220/Kconfig
index 446377c..0fa529c 100644
--- a/board/Seagate/nas220/Kconfig
+++ b/board/Seagate/nas220/Kconfig
@@ -10,4 +10,3 @@
default "nas220"
endif
-
diff --git a/board/Synology/ds109/Kconfig b/board/Synology/ds109/Kconfig
index 869ff0b..a7c75ae 100644
--- a/board/Synology/ds109/Kconfig
+++ b/board/Synology/ds109/Kconfig
@@ -10,4 +10,3 @@
default "ds109"
endif
-
diff --git a/board/abilis/tb100/Kconfig b/board/abilis/tb100/Kconfig
index c02f9c9..904a92c 100644
--- a/board/abilis/tb100/Kconfig
+++ b/board/abilis/tb100/Kconfig
@@ -13,4 +13,3 @@
default "tb100"
endif
-
diff --git a/board/advantech/Kconfig b/board/advantech/Kconfig
index 334f4e5..a8d4969 100644
--- a/board/advantech/Kconfig
+++ b/board/advantech/Kconfig
@@ -26,4 +26,3 @@
source "board/advantech/som-db5800-som-6867/Kconfig"
endif
-
diff --git a/board/advantech/dms-ba16/Kconfig b/board/advantech/dms-ba16/Kconfig
index 232a1d5..040eb86 100644
--- a/board/advantech/dms-ba16/Kconfig
+++ b/board/advantech/dms-ba16/Kconfig
@@ -29,4 +29,3 @@
default "advantech_dms-ba16"
endif
-
diff --git a/board/advantech/som-db5800-som-6867/Kconfig b/board/advantech/som-db5800-som-6867/Kconfig
index 5f9a05b..35d58fc 100644
--- a/board/advantech/som-db5800-som-6867/Kconfig
+++ b/board/advantech/som-db5800-som-6867/Kconfig
@@ -27,4 +27,3 @@
default 0xe0000000
endif
-
diff --git a/board/alliedtelesis/SBx81LIFKW/Kconfig b/board/alliedtelesis/SBx81LIFKW/Kconfig
index 610ff4e..5c2609b 100644
--- a/board/alliedtelesis/SBx81LIFKW/Kconfig
+++ b/board/alliedtelesis/SBx81LIFKW/Kconfig
@@ -10,4 +10,3 @@
default "SBx81LIFKW"
endif
-
diff --git a/board/alliedtelesis/SBx81LIFXCAT/Kconfig b/board/alliedtelesis/SBx81LIFXCAT/Kconfig
index dcb96d4..524c290 100644
--- a/board/alliedtelesis/SBx81LIFXCAT/Kconfig
+++ b/board/alliedtelesis/SBx81LIFXCAT/Kconfig
@@ -10,4 +10,3 @@
default "SBx81LIFXCAT"
endif
-
diff --git a/board/alphaproject/ap_sh4a_4a/Kconfig b/board/alphaproject/ap_sh4a_4a/Kconfig
index 05a1837..4692851 100644
--- a/board/alphaproject/ap_sh4a_4a/Kconfig
+++ b/board/alphaproject/ap_sh4a_4a/Kconfig
@@ -10,4 +10,3 @@
default "ap_sh4a_4a"
endif
-
diff --git a/board/altera/arria10-socdk/Kconfig b/board/altera/arria10-socdk/Kconfig
index 0191ddc..b80cc6d 100644
--- a/board/altera/arria10-socdk/Kconfig
+++ b/board/altera/arria10-socdk/Kconfig
@@ -16,4 +16,3 @@
default "socfpga_arria10"
endif
-
diff --git a/board/amarula/vyasa-rk3288/Kconfig b/board/amarula/vyasa-rk3288/Kconfig
index 0a285df..8b8c308 100644
--- a/board/amarula/vyasa-rk3288/Kconfig
+++ b/board/amarula/vyasa-rk3288/Kconfig
@@ -10,4 +10,3 @@
default "vyasa-rk3288"
endif
-
diff --git a/board/amazon/kc1/Kconfig b/board/amazon/kc1/Kconfig
index 52016a0..1b46a8f 100644
--- a/board/amazon/kc1/Kconfig
+++ b/board/amazon/kc1/Kconfig
@@ -10,4 +10,3 @@
default "kc1"
endif
-
diff --git a/board/amlogic/Kconfig b/board/amlogic/Kconfig
old mode 100644
new mode 100755
index 66edf24..7fde763
--- a/board/amlogic/Kconfig
+++ b/board/amlogic/Kconfig
@@ -1,10 +1,46 @@
# function list
+config PXP_EMULATOR
+ bool "Amlogic Pxp emulater flag"
+ help
+ Support PXP environment
+
+config PXP_DDR
+ bool "Amlogic Pxp ddr flag"
+ help
+ Support PXP ddr environment
+ If this config is open, then DDR is running under PXP/PTM mode,
+ Which is simulation by software. The behavivor is not same
+ as real SOC. This config must be closed if running on real
+ chips.
+
+config PXP_STO
+ bool "Amlogic Pxp storage flag"
+ help
+ Support PxP storage preload mode.
+ When it's enabled, data were load to ram background.
+ When it's disabled, data were load to the storage media
+ module which makes the routine works much more like the
+ silicon chip.
+
+config PXP_SCS
+ bool "Amlogic Pxp scs flag"
+ help
+ Support PXP scs environment
+ If this option is open, then SCS check may be disabled for
+ fast PXP bring up. This config should be closed if SCS feature
+ is ready.
+
config AML_BL33_COMPRESS_ENABLE
bool "Amlogic U-boot compress"
help
Support U-boot compress function
+config AML_CRYPTO_AES
+ bool "Amlogic Crypto AES for Secure Boot"
+ help
+ "Support AES for Amlogic Secure Boot"
+
config AML_SECURE_BOOT_V3
bool "Amlogic SecureBoot V3"
help
@@ -25,6 +61,12 @@
help
"Support U-boot encrypt function"
+config UBOOT_RUN_IN_SRAM
+ bool "Amlogic U-boot run in sram"
+ default n
+ help
+ "Support Amlogic U-boot run in SRAM"
+
config AML_TSENSOR
bool "Amlogic Temp Sensor"
help
@@ -55,12 +97,31 @@
help
"Support bl32 function"
+config RAMDISK_MEM_ADDR
+ hex
+ default 0x0a000000
+ help
+ "select ramdisk load address"
+
+config DTB_MEM_ADDR
+ hex
+ default 0x01000000
+ help
+ "select Device tree load address"
+
config MULTI_DTB
bool "Amlogic Multi-DT function"
default n
help
"Support Multi-DT function"
+config DDR_FULL_FW
+ bool "full ddr fw support for soc using advanced boot loader"
+ default n
+ help
+ Support full ddr fw for soc using advanced boot loader as
+ bl2, such as sc2/t7/s4/t3....
+
if MESON_GXBB
config TARGET_ODROID_C2
@@ -102,6 +163,545 @@
# G12A series boards
+if MESON_A1
+
+config SYS_SOC
+ default "a1"
+
+choice
+ prompt "A1 Board"
+
+config A1_AD401_NOR_RTOS
+ bool "A1_AD401_NOR_RTOS"
+ select TARGET_A1_AD401
+ select MTD_SPI_FLASH
+ select SYSTEM_RTOS
+ help
+ Select A1 AD401 NOR RTOS board config
+
+config A1_AD401_NAND_RTOS
+ bool "A1_AD401_NAND_RTOS"
+ select TARGET_A1_AD401
+ #select SPI_NAND
+ select MTD_SPI_NAND
+ select SYSTEM_RTOS
+ help
+ Select A1 AD401 NOR RTOS board config
+
+config A1_AD401_NAND_LINUX
+ bool "A1_AD401_NAND_LINUX"
+ select TARGET_A1_AD401
+ #select SPI_NAND
+ select MTD_SPI_NAND
+ help
+ Select A1 AD401 NOR RTOS board config
+
+config A1_AD402_NOR_RTOS
+ bool "A1_AD402_NOR_RTOS"
+ select TARGET_A1_AD402
+ select MTD_SPI_FLASH
+ select SYSTEM_RTOS
+ help
+ Select A1 AD402 NOR RTOS board config
+
+config A1_AD402_NAND_RTOS
+ bool "A1_AD402_NAND_RTOS"
+ select TARGET_A1_AD402
+ #select SPI_NAND
+ select MTD_SPI_NAND
+ select SYSTEM_RTOS
+ help
+ Select A1 AD402 NOR RTOS board config
+
+config A1_AD402_NAND_LINUX
+ bool "A1_AD402_NAND_LINUX"
+ select TARGET_A1_AD402
+ #select SPI_NAND
+ select MTD_SPI_NAND
+ help
+ Select A1 AD402 NOR RTOS board config
+
+config A1_AD409_NOR_RTOS
+ bool "A1_AD409_NOR_RTOS"
+ select TARGET_A1_AD409
+ select MTD_SPI_FLASH
+ select SYSTEM_RTOS
+ help
+ Select A1 AD409 NOR RTOS board config
+
+config A1_AD409_NAND_RTOS
+ bool "A1_AD409_NAND_RTOS"
+ select TARGET_A1_AD409
+ #select SPI_NAND
+ select MTD_SPI_NAND
+ select SYSTEM_RTOS
+ help
+ Select A1 AD409 NOR RTOS board config
+
+config A1_AD409_NAND_LINUX
+ bool "A1_AD409_NAND_LINUX"
+ select TARGET_A1_AD409
+ #select SPI_NAND
+ select MTD_SPI_NAND
+ help
+ Select A1 AD409 NOR RTOS board config
+
+endchoice
+
+config TARGET_A1_AD401
+ bool "A1 AD401 board"
+ depends on A1_AD401_NOR_RTOS || A1_AD401_NAND_RTOS || A1_AD401_NAND_LINUX
+
+config TARGET_A1_AD402
+ bool "A1 AD402 board"
+ depends on A1_AD402_NOR_RTOS || A1_AD402_NAND_RTOS || A1_AD402_NAND_LINUX
+
+config TARGET_A1_AD409
+ bool "A1 AD409 board"
+ depends on A1_AD409_NOR_RTOS || A1_AD409_NAND_RTOS || A1_AD409_NAND_LINUX
+
+config SYSTEM_RTOS
+ bool "SYSTEM_RTOS_PARTITION"
+ default n
+ depends on A1_AD401_NOR_RTOS || A1_AD402_NOR_RTOS || A1_AD409_NOR_RTOS || A1_AD401_NAND_RTOS || A1_AD402_NAND_RTOS || A1_AD409_NAND_RTOS
+ help
+ Select SYSTEM RTOS partition table
+
+endif
+
+
+if MESON_C1
+
+config SYS_SOC
+ default "c1"
+
+choice
+ prompt "C1 Board"
+
+config C1_AE409
+ bool "C1_AE409"
+ select TARGET_C1_AE409
+ help
+ Select C1 SKT(AE409) config
+
+config C1_AE400
+ bool "C1_AE400"
+ select TARGET_C1_AE400
+ help
+ Select C1 AE400 config
+
+config C1_AE401
+ bool "C1_AE401"
+ select TARGET_C1_AE401
+ help
+ Select C1 AE401 config
+
+config C1_AE402
+ bool "C1_AE402"
+ select TARGET_C1_AE402
+ help
+ Select C1 AE402 config
+
+endchoice
+
+config TARGET_C1_AE409
+ bool "C1 AE409 board"
+ depends on C1_AE409
+
+config TARGET_C1_AE400
+ bool "C1 AE400 board"
+ depends on C1_AE400
+
+config TARGET_C1_AE401
+ bool "C1 AE401 board"
+ depends on C1_AE401
+
+config TARGET_C1_AE402
+ bool "C1 AE402 board"
+ depends on C1_AE402
+
+endif
+
+if MESON_S4
+
+config SYS_SOC
+ default "s4"
+
+config DDRFW_TYPE
+ string "S4 DDR FW Type"
+ default "ddr4"
+
+config CHIPSET_NAME
+ string "S4 CHIPSET NAME"
+ default "s905y4"
+
+config CHIPSET_VARIANT
+ string "S4 CHIPSET VARIANT"
+ default ""
+
+config AMLOGIC_KEY_TYPE
+ string "S4 AMLOGIC KEY TYPE"
+ default "dev-keys"
+
+config BL30_SELECT
+ string "S4 BL30 board config"
+ default "sc2_ah219"
+
+choice
+ prompt "S4 Board"
+
+config S4_SKT
+ bool "S4_SKT"
+ select TARGET_S4_SKT
+ help
+ Select S4 SKT(XXXX) config
+
+config S4_AP222
+ bool "S4_AP222"
+ select TARGET_S4_AP222
+ help
+ Select S4 AP222(XXXX) config
+
+config S4_AP229
+ bool "S4_AP229"
+ select TARGET_S4_AP229
+ help
+ Select S4 AP229(XXXX) config
+
+config S4_AQ222
+ bool "S4_AQ222"
+ select TARGET_S4_AQ222
+ help
+ Select S4 AQ222(XXXX) config
+
+config S4_AQ229
+ bool "S4_AQ229"
+ select TARGET_S4_AQ229
+ help
+ Select S4 AQ229(XXXX) config
+
+
+config S4_T211
+ bool "S4_T211"
+ select TARGET_S4_T211
+ help
+ Select S4 T211(XXXX) config
+
+config S4_AP201
+ bool "S4_AP201"
+ select TARGET_S4_AP201
+ help
+ Select S4 AP201(XXXX) config
+
+endchoice
+
+config TARGET_S4_SKT
+ bool "S4 SKT board"
+ depends on S4_SKT
+
+config TARGET_S4_AP222
+ bool "S4 AP222 board"
+ depends on S4_AP222
+
+config TARGET_S4_AP229
+ bool "S4 AP229 board"
+ depends on S4_AP229
+
+config TARGET_S4_AQ222
+ bool "S4 AQ222 board"
+ depends on S4_AQ222
+
+config TARGET_S4_AQ229
+ bool "S4 AQ229 board"
+ depends on S4_AQ229
+
+config TARGET_S4_T211
+ bool "S4 T211 board"
+ depends on S4_T211
+
+config TARGET_S4_AP201
+ bool "S4 AP201 board"
+ depends on S4_AP201
+
+endif
+
+if MESON_SC2
+
+config SYS_SOC
+ default "sc2"
+
+config DDRFW_TYPE
+ string "SC2 DDR FW Type"
+ default "ddr4"
+
+config CHIPSET_NAME
+ string "SC2 CHIPSET NAME"
+ default "S905X4"
+
+config CHIPSET_VARIANT
+ string "SC2 CHIPSET VARIANT"
+ default ""
+
+config AMLOGIC_KEY_TYPE
+ string "SC2 AMLOGIC KEY TYPE"
+ default "dev-keys"
+
+config BL30_SELECT
+ string "SC2 BL30 board config"
+ default "sc2_ah219"
+
+choice
+ prompt "SC2 Board"
+
+config SC2_SKT
+ bool "SC2_SKT"
+ select TARGET_SC2_SKT
+ help
+ Select SC2 SKT(XXXX) config
+
+config SC2_AH219
+ bool "SC2_AH219"
+ select TARGET_SC2_AH219
+ help
+ Select SC2 AH219 config
+
+config SC2_AH212
+ bool "SC2_AH212"
+ select TARGET_SC2_AH212
+ help
+ Select SC2 AH212 config
+
+config SC2_AH232
+ bool "SC2_AH232"
+ select TARGET_SC2_AH232
+ help
+ Select SC2 AH232 config
+
+config SC2_AH212_DDR3
+ bool "SC2_AH212_DDR3"
+ select TARGET_SC2_AH212_DDR3
+ help
+ Select SC2 AH212 DDR3 config
+
+config SC2_AH212_LPDDR3
+ bool "SC2_AH212_LPDDR3"
+ select TARGET_SC2_AH212_LPDDR3
+ help
+ Select SC2 AH212 LPDDR3 config
+
+config SC2_AH212_LPDDR4
+ bool "SC2_AH212_LPDDR4"
+ select TARGET_SC2_AH212_LPDDR4
+ help
+ Select SC2 AH212 LPDDR4 config
+
+endchoice
+
+config TARGET_SC2_SKT
+ bool "SC2 SKT board"
+ depends on SC2_SKT
+
+config TARGET_SC2_AH219
+ bool "SC2 AH219 board"
+ depends on SC2_AH219
+
+config TARGET_SC2_AH212
+ bool "SC2 AH212 board"
+ depends on SC2_AH212
+
+config TARGET_SC2_AH232
+ bool "SC2 AH232 board"
+ depends on SC2_AH232
+
+config TARGET_SC2_AH212_DDR3
+ bool "SC2 AH212 ddr3 board"
+ depends on SC2_AH212_DDR3
+
+config TARGET_SC2_AH212_LPDDR3
+ bool "SC2 AH212 lpddr3 board"
+ depends on SC2_AH212_LPDDR3
+
+config TARGET_SC2_AH212_LPDDR4
+ bool "SC2 AH212 lpddr4 board"
+ depends on SC2_AH212_LPDDR4
+
+endif
+
+if MESON_T7
+
+config SYS_SOC
+ default "t7"
+
+config DDRFW_TYPE
+ string "T7 DDR FW Type"
+ default "ddr4"
+
+config CHIPSET_NAME
+ string "T7 CHIPSET NAME"
+ default "POP1"
+
+config CHIPSET_VARIANT
+ string "T7 CHIPSET VARIANT"
+ default ""
+
+config AMLOGIC_KEY_TYPE
+ string "T7 AMLOGIC KEY TYPE"
+ default "dev-keys"
+
+config BL30_SELECT
+ string "T7 BL30 board config"
+ default "sc2_ah219"
+
+choice
+ prompt "T7 Board"
+
+config T7_SKT
+ bool "T7_SKT"
+ select TARGET_T7_SKT
+ help
+ Select T7 SKT(XXXX) config
+
+config T7_AN408_LPDDR4X
+ bool "T7_AN408_LPDDR4X"
+ select TARGET_T7_AN408_LPDDR4X
+ help
+ Select T7 AN408 LPDDR4X config
+
+config T7_AN409_DDR4
+ bool "T7_AN409_DDR4"
+ select TARGET_T7_AN409_DDR4
+ help
+ Select T7 AN409 DDR4 config
+
+config T7_AN400_LPDDR4X
+ bool "T7_AN400_LPDDR4X"
+ select TARGET_T7_AN400_LPDDR4X
+ help
+ Select T7 AN400 LPDDR4X config
+
+config T7_T319
+ bool "T7_T319"
+ select TARGET_T7_T319
+ help
+ Select T7 T319 config
+
+config T7_AN40A1
+ bool "T7_AN40A1"
+ select TARGET_T7_AN40A1
+ help
+ Select T7 AN40A1 config
+
+config T7_AN400P_LPDDR4X
+ bool "T7_AN400P_LPDDR4X"
+ select TARGET_T7_AN400P_LPDDR4X
+ help
+ Select T7 AN400P LPDDR4X config
+
+endchoice
+
+config TARGET_T7_SKT
+ bool "T7 SKT board"
+ depends on T7_SKT
+
+config TARGET_T7_AN408_LPDDR4X
+ bool "T7 AN408 lpddr4x board"
+ depends on T7_AN408_LPDDR4X
+
+config TARGET_T7_AN409_DDR4
+ bool "T7 AN409 ddr4 board"
+ depends on T7_AN409_DDR4
+
+config TARGET_T7_AN400_LPDDR4X
+ bool "T7 AN400 lpddr4x board"
+ depends on T7_AN400_LPDDR4X
+
+config TARGET_T7_T319
+ bool "T7 T319 board"
+ depends on T7_T319
+
+config TARGET_T7_AN40A1
+ bool "T7 AN40A1 board"
+ depends on T7_AN40A1
+
+config TARGET_T7_AN400P_LPDDR4X
+ bool "T7 AN400P lpddr4x board"
+ depends on T7_AN400P_LPDDR4X
+
+endif
+
+if MESON_C2
+
+config SYS_SOC
+ default "c2"
+
+choice
+ prompt "C2 Board"
+
+config C2_SKT
+ bool "C2_SKT"
+ select TARGET_C2_SKT
+ help
+ Select C2 SKT config mainly for pxp
+
+config C2_AF409
+ bool "C2_AF409"
+ select TARGET_C2_AF409
+ help
+ Select C2_AF409 (SKT) config
+
+config C2_AF400
+ bool "C2_AF400"
+ select TARGET_C2_AF400
+ help
+ Select C2_AF400 config
+
+config C2_AF401
+ bool "C2_AF401"
+ select TARGET_C2_AF401
+ help
+ Select C2_AF401 config
+
+config C2_AF402
+ bool "C2_AF402"
+ select TARGET_C2_AF402
+ help
+ Select C2_AF402 config
+
+config C2_AF419
+ bool "C2_AF419"
+ select TARGET_C2_AF419
+ help
+ Select C2_AF419 config
+
+endchoice
+
+config TARGET_C2_SKT
+ bool "C2 SKT board"
+ depends on C2_SKT
+
+config TARGET_C2_AF409
+ bool "C2 AF409 board"
+ depends on C2_AF409
+
+
+config TARGET_C2_AF400
+ bool "C2 AF400 board"
+ depends on C2_AF400
+
+config TARGET_C2_AF401
+ bool "C2 AF401 board"
+ depends on C2_AF401
+
+config TARGET_C2_AF402
+ bool "C2 AF402 board"
+ depends on C2_AF402
+
+config TARGET_C2_AF419
+ bool "C2 AF419 board"
+ depends on C2_AF419
+
+endif
+
if MESON_G12A
config SYS_SOC
@@ -116,9 +716,6 @@
config TARGET_SM1_AC200_V1
bool "SM1_AC200_V1"
-config TARGET_SM1_ELAINE_P0
- bool "SM1_ELAINE_P0"
-
endif
if MESON_G12B
@@ -133,24 +730,76 @@
# Amlogic boards
+source "board/amlogic/a1_ad409/Kconfig"
+
+source "board/amlogic/a1_ad401/Kconfig"
+
+source "board/amlogic/a1_ad402/Kconfig"
+
+source "board/amlogic/c1_ae400/Kconfig"
+
+source "board/amlogic/c1_ae401/Kconfig"
+
+source "board/amlogic/c1_ae402/Kconfig"
+
+source "board/amlogic/c1_ae409/Kconfig"
+
+source "board/amlogic/s4_skt/Kconfig"
+
+source "board/amlogic/s4_ap222/Kconfig"
+
+source "board/amlogic/s4_ap229/Kconfig"
+
+source "board/amlogic/s4_aq222/Kconfig"
+
+source "board/amlogic/s4_aq229/Kconfig"
+
+source "board/amlogic/s4_t211/Kconfig"
+
+source "board/amlogic/s4_ap201/Kconfig"
+
+source "board/amlogic/sc2_skt/Kconfig"
+
+source "board/amlogic/sc2_ah219/Kconfig"
+
+source "board/amlogic/sc2_ah212/Kconfig"
+
+source "board/amlogic/sc2_ah232/Kconfig"
+
+source "board/amlogic/sc2_ah212_ddr3/Kconfig"
+
+source "board/amlogic/sc2_ah212_lpddr3/Kconfig"
+
+source "board/amlogic/sc2_ah212_lpddr4/Kconfig"
+
+source "board/amlogic/c2_skt/Kconfig"
+
+source "board/amlogic/c2_af409/Kconfig"
+
+source "board/amlogic/c2_af400/Kconfig"
+
+source "board/amlogic/c2_af401/Kconfig"
+
+source "board/amlogic/c2_af402/Kconfig"
+
+source "board/amlogic/c2_af419/Kconfig"
+
source "board/amlogic/g12a_u200_v1/Kconfig"
source "board/amlogic/g12b_w400_v1/Kconfig"
source "board/amlogic/sm1_ac200_v1/Kconfig"
-source "board/amlogic/g12b_newman_px/Kconfig"
+source "board/amlogic/t7_skt/Kconfig"
-source "board/amlogic/g12b_newman_bx/Kconfig"
+source "board/amlogic/t7_an408_lpddr4x/Kconfig"
-source "board/amlogic/g12b_puddy_px/Kconfig"
+source "board/amlogic/t7_an409_ddr4/Kconfig"
-source "board/amlogic/sm1_elaine_p0/Kconfig"
+source "board/amlogic/t7_an400_lpddr4x/Kconfig"
-source "board/amlogic/sm1_elaine_p1/Kconfig"
+source "board/amlogic/t7_t319/Kconfig"
-source "board/amlogic/sm1_elaine_p2/Kconfig"
+source "board/amlogic/t7_an40a1/Kconfig"
-source "board/amlogic/sm1_elaine_b1/Kconfig"
-
-source "board/amlogic/sm1_elaine_bx/Kconfig"
+source "board/amlogic/t7_an400p_lpddr4x/Kconfig"
diff --git a/board/amlogic/a1_ad401/Kconfig b/board/amlogic/a1_ad401/Kconfig
new file mode 100644
index 0000000..ef8c026
--- /dev/null
+++ b/board/amlogic/a1_ad401/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_A1_AD401
+
+config SYS_SOC
+ default "a1"
+
+config SYS_BOARD
+ default "a1_ad401"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "a1_ad401"
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default y
+ help
+ support plltest command
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+endif
diff --git a/board/amlogic/a1_ad401/Makefile b/board/amlogic/a1_ad401/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/a1_ad401/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/a1_ad401/a1_ad401.c b/board/amlogic/a1_ad401/a1_ad401.c
new file mode 100644
index 0000000..1b2f939
--- /dev/null
+++ b/board/amlogic/a1_ad401/a1_ad401.c
@@ -0,0 +1,323 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <linux/mtd/partitions.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_a1_clk(void)
+{
+ struct udevice *a1_clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &a1_clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &a1_clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+void board_init_mem(void) {
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+ /* reset uart A for BT*/
+ writel(0x4000000, RESETCTRL_RESET1);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ active_a1_clk();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ return 0;
+}
+
+phys_size_t get_dram_size(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+}
+
+phys_size_t get_effective_memsize(void)
+{
+#ifdef CONFIG_UBOOT_RUN_IN_SRAM
+ return 0x180000; /* SRAM 1.5MB */
+#else
+ return get_dram_size();
+#endif /* CONFIG_UBOOT_RUN_IN_SRAM */
+}
+
+#ifdef CONFIG_UBOOT_RUN_IN_SRAM
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ return (PHYS_SDRAM_1_BASE+PHYS_SDRAM_1_SIZE);
+}
+#endif
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = 0;
+ gd->bd->bi_dram[0].size = get_dram_size();
+ return 0;
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x7FE00000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0xFFE00000UL,
+ .phys = 0xFFE00000UL,
+ .size = 0x00200000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+#ifdef CONFIG_SYSTEM_RTOS
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "dspA",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "dspB",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+#else /*CONFIG_SYSTEM_RTOS*/
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "misc",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 13 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 10 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 72 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+#endif /*CONFIG_SYSTEM_RTOS*/
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "misc",
+ .offset = 0,
+ .size = 8 * SZ_8K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 1 * SZ_1M,
+ },
+ {
+ .name = "dspA",
+ .offset = 0,
+ .size = 1 * SZ_512K,
+ },
+ {
+ .name = "dspB",
+ .offset = 0,
+ .size = 1 * SZ_512K,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+
+uint64_t spiflash_bootloader_size(void)
+{
+ return 1 * SZ_1M;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/a1_ad401/aml-user-key.sig b/board/amlogic/a1_ad401/aml-user-key.sig
new file mode 100644
index 0000000..ceac711
--- /dev/null
+++ b/board/amlogic/a1_ad401/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/a1_ad401/firmware/timing.c b/board/amlogic/a1_ad401/firmware/timing.c
new file mode 100644
index 0000000..5b289ad
--- /dev/null
+++ b/board/amlogic/a1_ad401/firmware/timing.c
@@ -0,0 +1,391 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define DDR_SIZE 0
+#define CPU_CLK 1200
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+
+/* ddr configs */
+#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+
+#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+
+
+#define PSRAM_CHIP_LOGIC_INDEX_SOC 1
+
+#define PSRAM_CHIP_LOGIC_INDEX_WINBOND_3_CMD_W955D8MKY 0x20
+#define PSRAM_CHIP_LOGIC_INDEX_WINBOND_3_CMD_W956D8MKY 0x21
+#define PSRAM_CHIP_LOGIC_INDEX_AP_MEMORY_3_CMD 0x30
+
+//#define PSRAM_ENABLE
+#ifdef PSRAM_ENABLE
+#define PSRAM_CHIP_LOGIC_INDEX PSRAM_CHIP_LOGIC_INDEX_AP_MEMORY_3_CMD
+#endif
+
+/* please config __psram_setting[] if board use psram */
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = {
+{
+ /* ddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_16BIT_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ /* DRAMFreq = 192, 256, 384, 512, 768-1536 */
+ .DRAMFreq = {768, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xfc,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 128,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 0
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ /* DRAMFreq = 192, 256, 384, 512, 768-1536 */
+ .DRAMFreq = {768, 0, 0, 0},
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+};
+
+psram_set_t __psram_setting[] = {
+#ifdef PSRAM_ENABLE
+{
+ .psram_mr = {0}, /* 12 uint8 */
+ .psram_board_mask = 0,
+ //.psram_amlogic_protocol_id = PSRAM_CHIP_LOGIC_INDEX_AP_MEMORY_3_CMD,
+ //.psram_amlogic_protocol_id = PSRAM_CHIP_LOGIC_INDEX_WINBOND_3_CMD_W955D8MKY,
+ .psram_amlogic_protocol_id = PSRAM_CHIP_LOGIC_INDEX,
+
+ .psram_test_function = {0}, /* 2 uint8 */
+ .psram_vendor_id = 0,
+ .psram_device_id = 0,
+ .psram_soc_drv = 0,
+ .psram_dram_drv = 0,
+ .psram_ac_timing0 = 0,
+ .psram_ac_timing1 = 0,
+ .psram_ac_timing2 = 0,
+ .psram_mode_crtl = 0,
+ /* psram_frequency = 24, 64, 96, 128, 192, 256 */
+ .psram_frequency = 0xffff,//192,
+ .psram_size = 8,
+ .psram_mode_crtl_bl33 = 0,
+ .psram_pin_crtl = 0,
+ .psram_lcd_ctrl = 0,
+ .psram_pin_dq_in_delay = {0}, /* 8 uint8 */
+ .psram_pin_dq_out_delay = {0}, /* 8 uint8 */
+ .psram_pin_dq_out_oe_delay = {0}, /* 8 uint8 */
+ .psram_pin_dm_out_delay = 0,
+ .psram_pin_dm_out_oe_delay = 0,
+ .psram_pin_cs_out_delay = 0,
+ .psram_pin_dqsp_in_delay = 0,
+ .psram_pin_dqsn_in_delay = 0,
+ .psram_pin_ckp_out_delay = 0,
+ .psram_pin_ckn_out_delay = 0,
+ .psram_pin_rden_delay = 0,
+ .psram_bdlr_delay = 0,
+},
+#else
+ {0},
+#endif
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = AML_CUSTOMER_ID,
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 800)
+ #define VCCK_VAL_REG 0x00150007
+#elif (VCCK_VAL == 810)
+ #define VCCK_VAL_REG 0x00140008
+#elif (VCCK_VAL == 820)
+ #define VCCK_VAL_REG 0x00130009
+#elif (VCCK_VAL == 830)
+ #define VCCK_VAL_REG 0x0012000a
+#elif (VCCK_VAL == 840)
+ #define VCCK_VAL_REG 0x0011000b
+#elif (VCCK_VAL == 850)
+ #define VCCK_VAL_REG 0x0010000c
+#elif (VCCK_VAL == 860)
+ #define VCCK_VAL_REG 0x000f000d
+#elif (VCCK_VAL == 870)
+ #define VCCK_VAL_REG 0x000e000e
+#elif (VCCK_VAL == 880)
+ #define VCCK_VAL_REG 0x000d000f
+#elif (VCCK_VAL == 890)
+ #define VCCK_VAL_REG 0x000c0010
+#elif (VCCK_VAL == 900)
+ #define VCCK_VAL_REG 0x000b0011
+#elif (VCCK_VAL == 910)
+ #define VCCK_VAL_REG 0x000a0012
+#elif (VCCK_VAL == 920)
+ #define VCCK_VAL_REG 0x00090013
+#elif (VCCK_VAL == 930)
+ #define VCCK_VAL_REG 0x00080014
+#elif (VCCK_VAL == 940)
+ #define VCCK_VAL_REG 0x00070015
+#elif (VCCK_VAL == 950)
+ #define VCCK_VAL_REG 0x00060016
+#elif (VCCK_VAL == 960)
+ #define VCCK_VAL_REG 0x00050017
+#elif (VCCK_VAL == 970)
+ #define VCCK_VAL_REG 0x00040018
+#elif (VCCK_VAL == 980)
+ #define VCCK_VAL_REG 0x00030019
+#elif (VCCK_VAL == 990)
+ #define VCCK_VAL_REG 0x0002001a
+#elif (VCCK_VAL == 1000)
+ #define VCCK_VAL_REG 0x0001001b
+#elif (VCCK_VAL == 1010)
+ #define VCCK_VAL_REG 0x0000001c
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE PWM table */
+#if (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x0010000c
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x000f000d
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x000e000e
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x000d000f
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x000c0010
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x000b0011
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x000a0012
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x00090013
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x00080014
+#elif (VDDEE_VAL == 890)
+ #define VDDEE_VAL_REG 0x00070015
+#elif (VDDEE_VAL == 900)
+ #define VDDEE_VAL_REG 0x00060016
+#elif (VDDEE_VAL == 910)
+ #define VDDEE_VAL_REG 0x00050017
+#elif (VDDEE_VAL == 920)
+ #define VDDEE_VAL_REG 0x00040018
+#elif (VDDEE_VAL == 930)
+ #define VDDEE_VAL_REG 0x00030019
+#elif (VDDEE_VAL == 940)
+ #define VDDEE_VAL_REG 0x0002001a
+#elif (VDDEE_VAL == 950)
+ #define VDDEE_VAL_REG 0x0001001b
+#elif (VDDEE_VAL == 960)
+ #define VDDEE_VAL_REG 0x0000001c
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
+#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
+#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
+#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
+#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ {0, 0, 0xffffffff, 0, 0, 0},
+};
diff --git a/board/amlogic/a1_ad402/Kconfig b/board/amlogic/a1_ad402/Kconfig
new file mode 100644
index 0000000..932e38b
--- /dev/null
+++ b/board/amlogic/a1_ad402/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_A1_AD402
+
+config SYS_SOC
+ default "a1"
+
+config SYS_BOARD
+ default "a1_ad402"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "a1_ad402"
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default y
+ help
+ support plltest command
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+endif
diff --git a/board/amlogic/a1_ad402/Makefile b/board/amlogic/a1_ad402/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/a1_ad402/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/a1_ad402/a1_ad402.c b/board/amlogic/a1_ad402/a1_ad402.c
new file mode 100644
index 0000000..5774602
--- /dev/null
+++ b/board/amlogic/a1_ad402/a1_ad402.c
@@ -0,0 +1,323 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <linux/mtd/partitions.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_a1_clk(void)
+{
+ struct udevice *a1_clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &a1_clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &a1_clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+void board_init_mem(void) {
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+ /* reset uart A for BT*/
+ writel(0x4000000, RESETCTRL_RESET1);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ active_a1_clk();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ return 0;
+}
+
+phys_size_t get_dram_size(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+}
+
+phys_size_t get_effective_memsize(void)
+{
+#ifdef CONFIG_UBOOT_RUN_IN_SRAM
+ return 0x180000; /* SRAM 1.5MB */
+#else
+ return get_dram_size();
+#endif /* CONFIG_UBOOT_RUN_IN_SRAM */
+}
+
+#ifdef CONFIG_UBOOT_RUN_IN_SRAM
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ return (PHYS_SDRAM_1_BASE + PHYS_SDRAM_1_SIZE);
+}
+#endif
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = 0;
+ gd->bd->bi_dram[0].size = get_dram_size();
+ return 0;
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x7FE00000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ .virt = 0xFFE00000UL,
+ .phys = 0xFFE00000UL,
+ .size = 0x00200000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+#ifdef CONFIG_SYSTEM_RTOS
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "dspA",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "dspB",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+#else /*CONFIG_SYSTEM_RTOS*/
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "misc",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 13 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 10 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 72 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+#endif /*CONFIG_SYSTEM_RTOS*/
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "misc",
+ .offset = 0,
+ .size = 8 * SZ_8K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 1 * SZ_1M,
+ },
+ {
+ .name = "dspA",
+ .offset = 0,
+ .size = 1 * SZ_512K,
+ },
+ {
+ .name = "dspB",
+ .offset = 0,
+ .size = 1 * SZ_512K,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+
+uint64_t spiflash_bootloader_size(void)
+{
+ return 1 * SZ_1M;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/a1_ad402/aml-user-key.sig b/board/amlogic/a1_ad402/aml-user-key.sig
new file mode 100755
index 0000000..ceac711
--- /dev/null
+++ b/board/amlogic/a1_ad402/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/a1_ad402/firmware/timing.c b/board/amlogic/a1_ad402/firmware/timing.c
new file mode 100644
index 0000000..eac89ca
--- /dev/null
+++ b/board/amlogic/a1_ad402/firmware/timing.c
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define DDR_SIZE 0
+#define CPU_CLK 1200
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+
+/* ddr configs */
+#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+
+#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+
+
+#define PSRAM_CHIP_LOGIC_INDEX_SOC 1
+
+#define PSRAM_CHIP_LOGIC_INDEX_WINBOND_3_CMD_W955D8MKY 0x20
+#define PSRAM_CHIP_LOGIC_INDEX_WINBOND_3_CMD_W956D8MKY 0x21
+#define PSRAM_CHIP_LOGIC_INDEX_AP_MEMORY_3_CMD 0x30
+
+//#define PSRAM_ENABLE
+#ifdef PSRAM_ENABLE
+#define PSRAM_CHIP_LOGIC_INDEX PSRAM_CHIP_LOGIC_INDEX_AP_MEMORY_3_CMD
+#endif
+
+/* please config __psram_setting[] if board use psram */
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = {
+{
+ /* ddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_16BIT_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ /* DRAMFreq = 192, 256, 384, 512, 768-1536 */
+ .DRAMFreq = {768, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xfc,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 128,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 0
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ /* DRAMFreq = 192, 256, 384, 512, 768-1536 */
+ .DRAMFreq = {768, 0, 0, 0},
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+};
+
+psram_set_t __psram_setting[] = {
+#ifdef PSRAM_ENABLE
+{
+ .psram_mr = {0}, /* 12 uint8 */
+ .psram_board_mask = 0,
+ //.psram_amlogic_protocol_id = PSRAM_CHIP_LOGIC_INDEX_AP_MEMORY_3_CMD,
+ //.psram_amlogic_protocol_id = PSRAM_CHIP_LOGIC_INDEX_WINBOND_3_CMD_W955D8MKY,
+ .psram_amlogic_protocol_id = PSRAM_CHIP_LOGIC_INDEX,
+
+ .psram_test_function = {0}, /* 2 uint8 */
+ .psram_vendor_id = 0,
+ .psram_device_id = 0,
+ .psram_soc_drv = 0,
+ .psram_dram_drv = 0,
+ .psram_ac_timing0 = 0,
+ .psram_ac_timing1 = 0,
+ .psram_ac_timing2 = 0,
+ .psram_mode_crtl = 0,
+ /* psram_frequency = 24, 64, 96, 128, 192, 256 */
+ .psram_frequency = 0xffff,//192,
+ .psram_size = 8,
+ .psram_mode_crtl_bl33 = 0,
+ .psram_pin_crtl = 0,
+ .psram_lcd_ctrl = 0,
+ .psram_pin_dq_in_delay = {0}, /* 8 uint8 */
+ .psram_pin_dq_out_delay = {0}, /* 8 uint8 */
+ .psram_pin_dq_out_oe_delay = {0}, /* 8 uint8 */
+ .psram_pin_dm_out_delay = 0,
+ .psram_pin_dm_out_oe_delay = 0,
+ .psram_pin_cs_out_delay = 0,
+ .psram_pin_dqsp_in_delay = 0,
+ .psram_pin_dqsn_in_delay = 0,
+ .psram_pin_ckp_out_delay = 0,
+ .psram_pin_ckn_out_delay = 0,
+ .psram_pin_rden_delay = 0,
+ .psram_bdlr_delay = 0,
+},
+#else
+ {0},
+#endif
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = AML_CUSTOMER_ID,
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+#define VDDCORE_VAL AML_VDDCORE_INIT_VOLTAGE
+/* If AML_VDDCORE_INIT_VOLTAGE_SEL is 1, the voltage of vddcore
+ * will be controlled by efuse. if 0, it is controlled by
+ * AML_VDDCORE_INIT_VOLTAGE
+ */
+#define VDD_VAL_SEL AML_VDDCORE_INIT_VOLTAGE_SEL
+#define BL2_EE_ADD AML_VDDCORE_INIT_EFUSE_MARGIN /* margin */
+#define FT_VMIN_OFFSET AML_VDDCORE_INIT_EFUSE_OFFSET /*vmin efuse offset*/
+#define FT_BASE_VOLT AML_VDDCORE_INIT_EFUSE_BASE_V0LT
+
+/* for PWM use */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
+#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
+#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
+#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
+#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
+
+#define P_PADCTRL_PIN_MUX_REG7 0xfe00041c
+#define P_PADCTRL_GPIOF_DS 0xfe000554
+#define CLK_PWM_CLK_EF_CTRL ((0x0033 << 2) + 0xfe000800)
+#define P_PWMEF_MISC_REG_EF 0xfe005408
+#define VDDCORE_TABLE_END 0XFFFFFFFF
+#define P_PWMEF_PWM_F 0xfe005404
+
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ {0, 0, 0xffffffff, 0, 0, 0},
+
+ /* power key */
+ /* step1: CHK HW */
+ {(uint64_t)PADCTRL_GPIOF_I, 9, 0, 0, BL2_INIT_STAGE_POWERKEY_CHK_HW, 0},
+
+ /* step2: match power key config */
+ /* GPIOF[BIT9]=0 power key press, =1 power key up */
+ {0x0, POWERKEY_CFG0, 0, 0, BL2_INIT_STAGE_POWERKEY_CFG_GROUP, 0},
+ {0x1, POWERKEY_CFG1, 0, 0, BL2_INIT_STAGE_POWERKEY_CFG_GROUP, 0},
+
+ /* step3: config power key */
+ /* power key press config*/
+ {PADCTRL_PIN_MUX_REG7, 0, 0xf << 12, 0, BL2_INIT_STAGE_POWERKEY_INIT | POWERKEY_CFG0, 0},
+ {PADCTRL_GPIOF_OEN, 0, 1 << 11, 0, BL2_INIT_STAGE_POWERKEY_INIT | POWERKEY_CFG0, 0},
+ {PADCTRL_GPIOF_O, 1 << 11, 0, 0, BL2_INIT_STAGE_POWERKEY_INIT | POWERKEY_CFG0, 0},
+ /* power key up config*/
+
+ /* vddcore voltage init, controled by pwm f,
+ * Do not initialize the pwm duty register here,
+ * initialize in bl2 according to efuse
+ */
+ {P_PWMEF_MISC_REG_EF, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
+ {CLK_PWM_CLK_EF_CTRL, 1 << 24 , ((0x3 << 25) | (0xff << 16)), 0, BL2_INIT_STAGE_1, 0},
+ {P_PADCTRL_GPIOF_DS, 0x3 << 24, 0x3 << 24, 0, BL2_INIT_STAGE_1, 0},
+ {P_PADCTRL_PIN_MUX_REG7,(0x2 << 16), (0xf << 16), 0, BL2_INIT_STAGE_1, 0},
+
+ /* Transfer voltage table temporarily use __bl2_reg to transfer */
+ {0x00000022, 1041, 0x00010021, 1031, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x00020020, 1021, 0x0003001f, 1011, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x0004001e, 1001, 0x0005001d, 990, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x0006001c, 980, 0x0007001b, 970, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x0008001a, 960, 0x00090019, 950, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x000a0018, 940, 0x000b0017, 930, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x000c0016, 920, 0x000d0015, 910, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x000e0014, 900, 0x000f0013, 890, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x00100012, 880, 0x00110011, 870, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x00120010, 860, 0x0013000f, 850, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x0014000e, 840, 0x0015000d, 830, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x0016000c, 820, 0x0017000b, 810, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x0018000a, 800, 0x00190009, 790, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x001a0008, 780, 0x001b0007, 770, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x001c0006, 760, 0x001d0005, 750, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x001e0004, 740, 0x001f0003, 730, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x00200002, 720, 0x00210001, 710, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ /* If there are invalid parameters at the end, use VDDCORE_TABLE_END to fill */
+ {0x00220000, 700, VDDCORE_TABLE_END, 0, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+
+ /* Transfer customer voltage, pwm duty register addr, sel flag */
+ {P_PWMEF_PWM_F, VDDCORE_VAL, VDD_VAL_SEL, 0, BL2_INIT_STAGE_VDDCORE_CONFIG, 0},
+ {BL2_EE_ADD, FT_VMIN_OFFSET, FT_BASE_VOLT, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0},
+};
diff --git a/board/amlogic/a1_ad409/Kconfig b/board/amlogic/a1_ad409/Kconfig
new file mode 100644
index 0000000..2b6ecdf
--- /dev/null
+++ b/board/amlogic/a1_ad409/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_A1_AD409
+
+config SYS_SOC
+ default "a1"
+
+config SYS_BOARD
+ default "a1_ad409"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "a1_ad409"
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default y
+ help
+ support plltest command
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+endif
diff --git a/board/amlogic/a1_ad409/Makefile b/board/amlogic/a1_ad409/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/a1_ad409/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/a1_ad409/a1_ad409.c b/board/amlogic/a1_ad409/a1_ad409.c
new file mode 100644
index 0000000..117ff94
--- /dev/null
+++ b/board/amlogic/a1_ad409/a1_ad409.c
@@ -0,0 +1,334 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <linux/mtd/partitions.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_a1_clk(void)
+{
+ struct udevice *a1_clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &a1_clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &a1_clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+void board_init_mem(void) {
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+ /* reset uart A for BT*/
+ writel(0x4000000, RESETCTRL_RESET1);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ active_a1_clk();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ return 0;
+}
+
+phys_size_t get_dram_size(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+}
+
+phys_size_t get_effective_memsize(void)
+{
+#ifdef CONFIG_UBOOT_RUN_IN_SRAM
+ return 0x180000; /* SRAM 1.5MB */
+#else
+ return get_dram_size();
+#endif /* CONFIG_UBOOT_RUN_IN_SRAM */
+}
+
+#ifdef CONFIG_UBOOT_RUN_IN_SRAM
+ulong board_get_usable_ram_top(ulong total_size)
+{
+ return (PHYS_SDRAM_1_BASE + PHYS_SDRAM_1_SIZE);
+}
+#endif
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = 0;
+ gd->bd->bi_dram[0].size = get_dram_size();
+ return 0;
+}
+
+static struct mm_region bd_mem_map[] = {
+ {.virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE},
+ {.virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x60000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN},
+ {.virt = 0xE0000000UL,
+ .phys = 0xE0000000UL,
+ .size = 0x10000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE},
+ {.virt = 0xF0000000UL,
+ .phys = 0xF0000000UL,
+ .size = 0x0FE00000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN},
+ {.virt = 0xFFE00000UL,
+ .phys = 0xFFE00000UL,
+ .size = 0x00200000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE},
+ {
+ /* List terminator */
+ 0,
+ }};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+#ifdef CONFIG_SYSTEM_RTOS
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "dspA",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "dspB",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+#else /*CONFIG_SYSTEM_RTOS*/
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+#endif /*CONFIG_SYSTEM_RTOS*/
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 1 * SZ_1M,
+ },
+ {
+ .name = "dspA",
+ .offset = 0,
+ .size = 1 * SZ_512K,
+ },
+ {
+ .name = "dspB",
+ .offset = 0,
+ .size = 1 * SZ_512K,
+ },
+ {
+ .name = "rsv",
+ .offset = 0,
+ .size = 0x2A0000,
+ },
+ {
+ .name = "xip",
+ .offset = 0,
+ .size = 0x100000,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+
+uint64_t spiflash_bootloader_size(void)
+{
+ return 1 * SZ_1M;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/a1_ad409/aml-user-key.sig b/board/amlogic/a1_ad409/aml-user-key.sig
new file mode 100644
index 0000000..ceac711
--- /dev/null
+++ b/board/amlogic/a1_ad409/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/a1_ad409/firmware/timing.c b/board/amlogic/a1_ad409/firmware/timing.c
new file mode 100644
index 0000000..e4d410b
--- /dev/null
+++ b/board/amlogic/a1_ad409/firmware/timing.c
@@ -0,0 +1,369 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define DDR_SIZE 0
+#define CPU_CLK 1200
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+
+/* ddr configs */
+#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+
+#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+
+
+#define PSRAM_CHIP_LOGIC_INDEX_SOC 1
+
+#define PSRAM_CHIP_LOGIC_INDEX_WINBOND_3_CMD_W955D8MKY 0x20
+#define PSRAM_CHIP_LOGIC_INDEX_WINBOND_3_CMD_W956D8MKY 0x21
+#define PSRAM_CHIP_LOGIC_INDEX_AP_MEMORY_3_CMD 0x30
+
+#define G12_D2PLL_CMD_DMC_FULL_TEST 0x01
+#define G12_D2PLL_CMD_OVER_RIDE 0x02
+#define G12_D2PLL_CMD_OVER_RIDE_PLUS_FULLTEST 0x03
+#define G12_D2PLL_CMD_OVER_RIDE_TRAINING_HDTL 0x04
+#define G12_D2PLL_CMD_PRINT_DDR_INFORMATION 0x05
+#define G12_D2PLL_CMD_WINDOW_TEST 0x11
+#define G12_D2PLL_CMD_WINDOW_TEST_AND_STICKY_OVERRIDE 0x12
+#define G12_D2PLL_CMD_SUSPEND_TEST 0x21
+#define G12_D2PLL_CMD_FREQUENCY_TABLE_TEST 0x31
+#define G12_D2PLL_CMD_SWEEP_EE_VOLTAGE_FREQUENCY_TABLE_TEST 0x32
+#define G12_D2PLL_CMD_DDR_EYE_TEST 0x41
+#define G12_D2PLL_CMD_DDR_EYE_TEST_AND_STICKY_OVERRIDE 0x42
+//#define PSRAM_ENABLE
+#ifdef PSRAM_ENABLE
+#define PSRAM_CHIP_LOGIC_INDEX PSRAM_CHIP_LOGIC_INDEX_AP_MEMORY_3_CMD
+#endif
+
+/* please config __psram_setting[] if board use psram */
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = {
+{
+ /* ddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_16BIT_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ /* DRAMFreq = 192, 256, 384, 512, 768-1536 */
+ .DRAMFreq = {768, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xfc,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 0
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_16BIT_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ /* DRAMFreq = 192, 256, 384, 512, 768-1536 */
+ .DRAMFreq = {768, 0, 0, 0},
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xfc,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 10,//0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+#if 0
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 7<< 10 | 8 << 15 | 9 << 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 13 << 15 | 14 << 20 | 15 << 25 ),
+ [2] = ( 16|( 17 << 5) |( 18 << 10) |( 19 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 12<< 5 | 20 << 10 | 6<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+};
+
+psram_set_t __psram_setting[] = {
+#ifdef PSRAM_ENABLE
+{
+ .psram_mr = {0}, /* 12 uint8 */
+ .psram_board_mask = 0,
+ .psram_amlogic_protocol_id = PSRAM_CHIP_LOGIC_INDEX,
+ //.psram_test_function = {G12_D2PLL_CMD_WINDOW_TEST,0}, /* 2 uint8 */
+ .psram_vendor_id = 0,
+ .psram_device_id = 0,
+ .psram_soc_drv = 0,
+ .psram_dram_drv = 0,
+ .psram_ac_timing0 = 0,
+ .psram_ac_timing1 = 0,
+ .psram_ac_timing2 = 0,
+ .psram_mode_crtl = 0,
+ /* psram_frequency = 24, 64, 96, 128, 192, 256 */
+ .psram_frequency = 0xffff,//192,,
+ .psram_size = 8,
+ .psram_mode_crtl_bl33 = 0,
+ .psram_pin_crtl = 0,
+ .psram_lcd_ctrl = 0,
+ .psram_pin_dq_in_delay = {0}, /* 8 uint8 */
+ .psram_pin_dq_out_delay = {0}, /* 8 uint8 */
+ .psram_pin_dq_out_oe_delay = {0}, /* 8 uint8 */
+ .psram_pin_dm_out_delay = 0,
+ .psram_pin_dm_out_oe_delay = 0,
+ .psram_pin_cs_out_delay = 0,
+ .psram_pin_dqsp_in_delay = 0,
+ .psram_pin_dqsn_in_delay = 0,
+ .psram_pin_ckp_out_delay = 0,
+ .psram_pin_ckn_out_delay = 0,
+ .psram_pin_rden_delay = 0,
+ .psram_bdlr_delay = 0,
+},
+#else
+ {0},
+#endif
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = AML_CUSTOMER_ID,
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+#define VDDCORE_VAL AML_VDDCORE_INIT_VOLTAGE
+/* If AML_VDDCORE_INIT_VOLTAGE_SEL is 1, the voltage of vddcore
+ * will be controlled by efuse. if 0, it is controlled by
+ * AML_VDDCORE_INIT_VOLTAGE
+ */
+#define VDD_VAL_SEL AML_VDDCORE_INIT_VOLTAGE_SEL
+#define BL2_EE_ADD AML_VDDCORE_INIT_EFUSE_MARGIN /* margin */
+#define FT_VMIN_OFFSET AML_VDDCORE_INIT_EFUSE_OFFSET /*vmin efuse offset*/
+#define FT_BASE_VOLT AML_VDDCORE_INIT_EFUSE_BASE_V0LT
+
+/* for PWM use */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define P_PADCTRL_PIN_MUX_REG7 0xfe00041c
+#define P_PADCTRL_GPIOF_DS 0xfe000554
+
+/* pwm clock and pwm controller */
+#define CLK_PWM_CLK_AB_CTRL 0xfe0008c4
+#define P_PWMAB_PWM_A 0xfe002400
+//#define P_PWMAB_PWM_B 0xfe002404
+#define P_PWMAB_MISC_REG_AB 0xfe002408
+#define VDDCORE_TABLE_END 0XFFFFFFFF
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ {0, 0, 0xffffffff, 0, 0, 0},
+ /* vddcore voltage init, controled by pwm A,
+ * Do not initialize the pwm duty register here,
+ * initialize in bl2 according to efuse
+ */
+ /*{P_PWMAB_PWM_A, 0x0017000b, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},*/
+ {P_PWMAB_MISC_REG_AB, ((1 << 15) | (1 << 0)), (0x7f << 8), 0, BL2_INIT_STAGE_1, 0},
+ {CLK_PWM_CLK_AB_CTRL, 1 << 8 , ((0x3 << 9) | (0xff << 0)), 0, BL2_INIT_STAGE_1, 0},
+ {P_PADCTRL_GPIOF_DS, 0x3 << 20, 0x3 << 20, 0, BL2_INIT_STAGE_1, 0},
+ {P_PADCTRL_PIN_MUX_REG7,(0x1 << 8), (0xf << 8), 0, BL2_INIT_STAGE_1, 0},
+
+ /* Transfer voltage table temporarily use __bl2_reg to transfer */
+ {0x00000022, 1039, 0x00010021, 1029, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x00020020, 1019, 0x0003001f, 1009, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x0004001e, 999, 0x0005001d, 989, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x0006001c, 978, 0x0007001b, 968, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x0008001a, 958, 0x00090019, 948, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x000a0018, 938, 0x000b0017, 927, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x000c0016, 917, 0x000d0015, 907, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x000e0014, 897, 0x000f0013, 887, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x00100012, 876, 0x00110011, 866, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x00120010, 856, 0x0013000f, 846, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x0014000e, 836, 0x0015000d, 826, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x0016000c, 815, 0x0017000b, 805, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x0018000a, 795, 0x00190009, 785, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x001a0008, 775, 0x001b0007, 764, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x001c0006, 754, 0x001d0005, 744, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x001e0004, 734, 0x001f0003, 724, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ {0x00200002, 714, 0x00210001, 703, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+ /* If there are invalid parameters at the end, use VDDCORE_TABLE_END to fill */
+ {0x00220000, 693, VDDCORE_TABLE_END, 0, BL2_INIT_STAGE_VDDCORE_TABLE, 0},
+
+ /* Transfer customer voltage, pwm duty register addr, sel flag */
+ {P_PWMAB_PWM_A, VDDCORE_VAL, VDD_VAL_SEL, 0, BL2_INIT_STAGE_VDDCORE_CONFIG, 0},
+ {BL2_EE_ADD, FT_VMIN_OFFSET, FT_BASE_VOLT, 0, BL2_INIT_STAGE_VDDCORE_CONFIG_1, 0},
+};
diff --git a/board/amlogic/c1_ae400/Kconfig b/board/amlogic/c1_ae400/Kconfig
new file mode 100644
index 0000000..c777cf0
--- /dev/null
+++ b/board/amlogic/c1_ae400/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_C1_AE400
+
+config SYS_SOC
+ default "c1"
+
+config SYS_BOARD
+ default "c1_ae400"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "c1_ae400"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default y
+ help
+ support plltest command
+
+endif
diff --git a/board/amlogic/c1_ae400/Makefile b/board/amlogic/c1_ae400/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/c1_ae400/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/c1_ae400/aml-user-key.sig b/board/amlogic/c1_ae400/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/c1_ae400/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/c1_ae400/c1_ae400.c b/board/amlogic/c1_ae400/c1_ae400.c
new file mode 100644
index 0000000..9718a45
--- /dev/null
+++ b/board/amlogic/c1_ae400/c1_ae400.c
@@ -0,0 +1,308 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+void board_init_mem(void) {
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ active_clk();
+
+ run_command("gpio c GPIOA_10", 0);
+ run_command("gpio c GPIOA_12", 0);
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+#ifdef UBOOT_RUN_IN_SRAM
+ return 0x180000; /* SRAM 1.5MB */
+#else
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+#endif /* UBOOT_RUN_IN_SRAM */
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 1 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+/*
+* mtd nand partition table, only care the size!
+* offset will be calculated by nand driver.
+*/
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+/* MUST NOT CHANGE this part unless u know what you are doing!
+* inherent parition for descrete bootloader to store fip
+* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+* name must be same with TPL_PART_NAME
+*/
+{
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 32*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 32*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 304*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c1_ae400/firmware/ramdump.c b/board/amlogic/c1_ae400/firmware/ramdump.c
new file mode 100644
index 0000000..d0ae3ff
--- /dev/null
+++ b/board/amlogic/c1_ae400/firmware/ramdump.c
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifdef CONFIG_MDUMP_COMPRESS
+#include "ramdump.h"
+
+struct ram_compress_full __ramdump_data = {
+ .store_phy_addr = (void *)CONFIG_COMPRESSED_DATA_ADDR,
+ .full_memsize = CONFIG_DDR_TOTAL_SIZE,
+ .section_count = CONFIG_COMPRESS_SECTION,
+ .sections = {
+ {
+ /* memory afer compressed data address */
+ .phy_addr = (void *)CONFIG_COMPRESSED_DATA_ADDR,
+ .section_size = CONFIG_DDR_TOTAL_SIZE -
+ CONFIG_COMPRESSED_DATA_ADDR,
+ .section_index = 4,
+ .compress_type = RAM_COMPRESS_NORMAL,
+ },
+ {
+ /* memory before bl2 */
+ .phy_addr = (void *)CONFIG_COMPRESS_START_ADDR,
+ .section_size = CONFIG_BL2_IGNORE_ADDR -
+ CONFIG_COMPRESS_START_ADDR,
+ .section_index = 1,
+ .compress_type = RAM_COMPRESS_NORMAL,
+ },
+ {
+ /* memory in reserved bl2 */
+ .phy_addr = (void *)CONFIG_BL2_IGNORE_ADDR,
+ .section_size = CONFIG_BL2_IGNORE_SIZE,
+ .section_index = 2,
+ .compress_type = RAM_COMPRESS_SET,
+ .set_value = 0x0,
+ },
+ {
+ /* segment 4: normal compress */
+ .phy_addr = (void *)CONFIG_SEG4_ADDR,
+ .section_size = CONFIG_COMPRESSED_DATA_ADDR -
+ CONFIG_SEG4_ADDR,
+ .section_index = 3,
+ .compress_type = RAM_COMPRESS_NORMAL,
+ }
+ },
+};
+#endif /* CONFIG_MDUMP_COMPRESS */
+
diff --git a/board/amlogic/c1_ae400/firmware/ramdump.h b/board/amlogic/c1_ae400/firmware/ramdump.h
new file mode 100644
index 0000000..de49681
--- /dev/null
+++ b/board/amlogic/c1_ae400/firmware/ramdump.h
@@ -0,0 +1,81 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __RAM_DUMP_H__
+#define __RAM_DUMP_H__
+
+#include <config.h>
+#ifdef CONFIG_MDUMP_COMPRESS
+#define CONFIG_COMPRESS_SECTION 4
+
+#if CONFIG_COMPRESS_SECTION > 8
+#error ---> CONFIG_COMPRESS_SECTION out of range, max should be 8
+#endif
+/*
+ * Full Memory lay out for RAM compress:
+ *
+ * DDR_TOP -> +--------+
+ * | |
+ * | |
+ * | 4 |
+ * | |
+ * | |
+ * |~~~~~~~~| <- store compressing data
+ * |~~~~~~~~|
+ * |~~~~~~~~|
+ * |~~~~~~~~|
+ * |~~~~~~~~|
+ * |~~~~~~~~|
+ * |~~~~~~~~|
+ * |~~~~~~~~|
+ * |~~~~~~~~|
+ * COMPRESSED_DATA -> +--------+
+ * | |
+ * | 3 |
+ * | |
+ * BL2_IGNORE_END -> +--------+ -- IGNORE_SIZE
+ * ||||||||||
+ * ||||2|||||
+ * ||||||||||
+ * BL2_IGNORE_ADDR -> +--------+
+ * | |
+ * | 1 |
+ * | |
+ * COMPRESS_START_ADDR -> +--------+
+ */
+#define CONFIG_DDR_TOTAL_SIZE (CONFIG_DDR_SIZE << 20)
+#define CONFIG_COMPRESSED_DATA_ADDR (0x10000000)
+#define CONFIG_COMPRESSED_DATA_ADDR1 (0x08000000)
+
+#define CONFIG_COMPRESS_START_ADDR (0x00000000)
+#define CONFIG_BL2_IGNORE_ADDR (0x05000000)
+//#define CONFIG_BL2_IGNORE_SIZE (0x00300000)
+#define CONFIG_BL2_IGNORE_SIZE (0x00400000)
+#define CONFIG_SEG4_ADDR (CONFIG_BL2_IGNORE_ADDR + \
+ CONFIG_BL2_IGNORE_SIZE)
+
+enum {
+ RAM_COMPRESS_NORMAL = 1,
+ RAM_COMPRESS_COPY = 2,
+ RAM_COMPRESS_SET = 3 /* set ram content to same vale */
+};
+
+struct ram_compress_section {
+ void *phy_addr;
+ unsigned int section_size;
+ unsigned int section_index : 8;
+ unsigned int compress_type : 8;
+ unsigned int set_value : 16;
+};
+
+struct ram_compress_full {
+ void *store_phy_addr;
+ unsigned int full_memsize;
+ unsigned int section_count;
+ struct ram_compress_section sections[CONFIG_COMPRESS_SECTION];
+};
+
+#endif
+#endif /* __RAM_DUMP_H__ */
diff --git a/board/amlogic/c1_ae400/firmware/timing.c b/board/amlogic/c1_ae400/firmware/timing.c
new file mode 100644
index 0000000..4161c36
--- /dev/null
+++ b/board/amlogic/c1_ae400/firmware/timing.c
@@ -0,0 +1,476 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+
+/* ddr configs */
+#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+
+#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = {
+{
+ // c1 4layer 2pcs ddr3 rank0
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
+},
+{
+ // c1 4layer 2pcs ddr3 rank0 768MB
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0,//CONFIG_DDR0_16BIT_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ /* DRAMFreq = 192, 256, 384, 512, 768-1536 */
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 768,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
+},
+{
+ // c1 4layer 2pcs ddr4 rank0
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1176, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {16,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
+},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = AML_CUSTOMER_ID,
+ .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */
+ .log_ctrl = (1<<7) | /* (1<<7), print bl2 log into buffer */
+#ifdef CONFIG_SILENT_CONSOLE
+ (1<<6), /* do not print log buffer */
+#else
+ (0<<6), /* print log buffer before run bl31 */
+#endif
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1040)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1030)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1020)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1010)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 1000)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 990)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 980)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 970)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 960)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 950)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 940)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 930)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 920)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 910)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 900)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 890)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 880)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 870)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 860)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 850)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 840)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 830)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 820)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 810)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 800)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 790)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 780)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 770)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 760)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 750)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 740)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 730)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 720)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 710)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 700)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/
+#if (VDDEE_VAL == 741)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 751)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 761)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 771)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 781)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 791)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 801)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 811)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 821)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 831)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 841)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 851)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 861)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 871)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 881)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 891)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 902)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 912)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 922)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/*
+ * GPIOE_0 PWM_A VDDEE_PWM
+ *
+ * GPIOE_1 PWM_B VCCK_PWM
+ */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400)
+
+/* pwm clock and pwm controller */
+#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800)
+#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400)
+#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400)
+#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400)
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ {0, 0, 0xffffffff, 0, 0, 0},
+ {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0},
+ /* enable vddcpu dc-dc, set GPIOD_10 high */
+ {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ /* set pwm A and pwm B clock rate to 24M, enable them */
+ {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3*/
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/c1_ae401/Kconfig b/board/amlogic/c1_ae401/Kconfig
new file mode 100644
index 0000000..cf62b03
--- /dev/null
+++ b/board/amlogic/c1_ae401/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_C1_AE401
+
+config SYS_SOC
+ default "c1"
+
+config SYS_BOARD
+ default "c1_ae401"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "c1_ae401"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default y
+ help
+ support plltest command
+
+endif
diff --git a/board/amlogic/c1_ae401/Makefile b/board/amlogic/c1_ae401/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/c1_ae401/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/c1_ae401/aml-user-key.sig b/board/amlogic/c1_ae401/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/c1_ae401/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/c1_ae401/c1_ae401.c b/board/amlogic/c1_ae401/c1_ae401.c
new file mode 100644
index 0000000..c17eaa7
--- /dev/null
+++ b/board/amlogic/c1_ae401/c1_ae401.c
@@ -0,0 +1,303 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+void board_init_mem(void) {
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ active_clk();
+
+ run_command("gpio c GPIOA_10", 0);
+ run_command("gpio c GPIOA_12", 0);
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+#ifdef UBOOT_RUN_IN_SRAM
+ return 0x180000; /* SRAM 1.5MB */
+#else
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+#endif /* UBOOT_RUN_IN_SRAM */
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 1 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+/* MUST NOT CHANGE this part unless u know what you are doing!
+* inherent parition for descrete bootloader to store fip
+* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+* name must be same with TPL_PART_NAME
+*/
+{
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 32*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 32*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 304*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c1_ae401/firmware/timing.c b/board/amlogic/c1_ae401/firmware/timing.c
new file mode 100644
index 0000000..4161c36
--- /dev/null
+++ b/board/amlogic/c1_ae401/firmware/timing.c
@@ -0,0 +1,476 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+
+/* ddr configs */
+#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+
+#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = {
+{
+ // c1 4layer 2pcs ddr3 rank0
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
+},
+{
+ // c1 4layer 2pcs ddr3 rank0 768MB
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0,//CONFIG_DDR0_16BIT_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ /* DRAMFreq = 192, 256, 384, 512, 768-1536 */
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 768,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
+},
+{
+ // c1 4layer 2pcs ddr4 rank0
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1176, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {16,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
+},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = AML_CUSTOMER_ID,
+ .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */
+ .log_ctrl = (1<<7) | /* (1<<7), print bl2 log into buffer */
+#ifdef CONFIG_SILENT_CONSOLE
+ (1<<6), /* do not print log buffer */
+#else
+ (0<<6), /* print log buffer before run bl31 */
+#endif
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1040)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1030)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1020)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1010)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 1000)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 990)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 980)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 970)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 960)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 950)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 940)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 930)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 920)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 910)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 900)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 890)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 880)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 870)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 860)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 850)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 840)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 830)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 820)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 810)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 800)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 790)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 780)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 770)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 760)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 750)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 740)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 730)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 720)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 710)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 700)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/
+#if (VDDEE_VAL == 741)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 751)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 761)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 771)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 781)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 791)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 801)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 811)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 821)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 831)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 841)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 851)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 861)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 871)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 881)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 891)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 902)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 912)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 922)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/*
+ * GPIOE_0 PWM_A VDDEE_PWM
+ *
+ * GPIOE_1 PWM_B VCCK_PWM
+ */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400)
+
+/* pwm clock and pwm controller */
+#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800)
+#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400)
+#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400)
+#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400)
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ {0, 0, 0xffffffff, 0, 0, 0},
+ {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0},
+ /* enable vddcpu dc-dc, set GPIOD_10 high */
+ {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ /* set pwm A and pwm B clock rate to 24M, enable them */
+ {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3*/
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/c1_ae402/Kconfig b/board/amlogic/c1_ae402/Kconfig
new file mode 100644
index 0000000..49f620a
--- /dev/null
+++ b/board/amlogic/c1_ae402/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_C1_AE402
+
+config SYS_SOC
+ default "c1"
+
+config SYS_BOARD
+ default "c1_ae402"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "c1_ae402"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default y
+ help
+ support plltest command
+
+endif
diff --git a/board/amlogic/c1_ae402/Makefile b/board/amlogic/c1_ae402/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/c1_ae402/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/c1_ae402/aml-user-key.sig b/board/amlogic/c1_ae402/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/c1_ae402/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/c1_ae402/c1_ae402.c b/board/amlogic/c1_ae402/c1_ae402.c
new file mode 100644
index 0000000..7cbd07e
--- /dev/null
+++ b/board/amlogic/c1_ae402/c1_ae402.c
@@ -0,0 +1,269 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+void board_init_mem(void) {
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ active_clk();
+
+ run_command("gpio c GPIOA_10", 0);
+ run_command("gpio c GPIOA_12", 0);
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+#ifdef UBOOT_RUN_IN_SRAM
+ return 0x180000; /* SRAM 1.5MB */
+#else
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+#endif /* UBOOT_RUN_IN_SRAM */
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+/* MUST NOT CHANGE this part unless u know what you are doing!
+* inherent parition for descrete bootloader to store fip
+* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+* name must be same with TPL_PART_NAME
+*/
+{
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 32*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 32*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 304*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c1_ae402/firmware/timing.c b/board/amlogic/c1_ae402/firmware/timing.c
new file mode 100644
index 0000000..4161c36
--- /dev/null
+++ b/board/amlogic/c1_ae402/firmware/timing.c
@@ -0,0 +1,476 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+
+/* ddr configs */
+#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+
+#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = {
+{
+ // c1 4layer 2pcs ddr3 rank0
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
+},
+{
+ // c1 4layer 2pcs ddr3 rank0 768MB
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0,//CONFIG_DDR0_16BIT_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ /* DRAMFreq = 192, 256, 384, 512, 768-1536 */
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 768,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
+},
+{
+ // c1 4layer 2pcs ddr4 rank0
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1176, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {16,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
+},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = AML_CUSTOMER_ID,
+ .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */
+ .log_ctrl = (1<<7) | /* (1<<7), print bl2 log into buffer */
+#ifdef CONFIG_SILENT_CONSOLE
+ (1<<6), /* do not print log buffer */
+#else
+ (0<<6), /* print log buffer before run bl31 */
+#endif
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1040)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1030)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1020)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1010)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 1000)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 990)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 980)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 970)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 960)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 950)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 940)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 930)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 920)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 910)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 900)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 890)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 880)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 870)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 860)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 850)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 840)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 830)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 820)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 810)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 800)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 790)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 780)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 770)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 760)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 750)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 740)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 730)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 720)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 710)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 700)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/
+#if (VDDEE_VAL == 741)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 751)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 761)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 771)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 781)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 791)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 801)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 811)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 821)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 831)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 841)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 851)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 861)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 871)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 881)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 891)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 902)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 912)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 922)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/*
+ * GPIOE_0 PWM_A VDDEE_PWM
+ *
+ * GPIOE_1 PWM_B VCCK_PWM
+ */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400)
+
+/* pwm clock and pwm controller */
+#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800)
+#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400)
+#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400)
+#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400)
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ {0, 0, 0xffffffff, 0, 0, 0},
+ {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0},
+ /* enable vddcpu dc-dc, set GPIOD_10 high */
+ {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ /* set pwm A and pwm B clock rate to 24M, enable them */
+ {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3*/
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/c1_ae409/Kconfig b/board/amlogic/c1_ae409/Kconfig
new file mode 100644
index 0000000..c8d2b93
--- /dev/null
+++ b/board/amlogic/c1_ae409/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_C1_AE409
+
+config SYS_SOC
+ default "c1"
+
+config SYS_BOARD
+ default "c1_ae409"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "c1_ae409"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default y
+ help
+ support plltest command
+
+endif
diff --git a/board/amlogic/c1_ae409/Makefile b/board/amlogic/c1_ae409/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/c1_ae409/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/c1_ae409/aml-key/bl2aesiv b/board/amlogic/c1_ae409/aml-key/bl2aesiv
new file mode 100755
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c1_ae409/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/c1_ae409/aml-key/bl2aeskey b/board/amlogic/c1_ae409/aml-key/bl2aeskey
new file mode 100755
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c1_ae409/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/c1_ae409/aml-key/bl3xaesiv b/board/amlogic/c1_ae409/aml-key/bl3xaesiv
new file mode 100755
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c1_ae409/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/c1_ae409/aml-key/bl3xaeskey b/board/amlogic/c1_ae409/aml-key/bl3xaeskey
new file mode 100755
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c1_ae409/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/c1_ae409/aml-key/kernelaesiv b/board/amlogic/c1_ae409/aml-key/kernelaesiv
new file mode 100755
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c1_ae409/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/c1_ae409/aml-key/kernelaeskey b/board/amlogic/c1_ae409/aml-key/kernelaeskey
new file mode 100755
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c1_ae409/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/c1_ae409/aml-user-key.sig b/board/amlogic/c1_ae409/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/c1_ae409/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/c1_ae409/c1_ae409.c b/board/amlogic/c1_ae409/c1_ae409.c
new file mode 100644
index 0000000..2992507
--- /dev/null
+++ b/board/amlogic/c1_ae409/c1_ae409.c
@@ -0,0 +1,300 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+void board_init_mem(void) {
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ active_clk();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+#ifdef UBOOT_RUN_IN_SRAM
+ return 0x180000; /* SRAM 1.5MB */
+#else
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+#endif /* UBOOT_RUN_IN_SRAM */
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 1 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+/* MUST NOT CHANGE this part unless u know what you are doing!
+* inherent parition for descrete bootloader to store fip
+* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+* name must be same with TPL_PART_NAME
+*/
+{
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 32*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 32*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 304*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c1_ae409/firmware/timing.c b/board/amlogic/c1_ae409/firmware/timing.c
new file mode 100644
index 0000000..f32ad39
--- /dev/null
+++ b/board/amlogic/c1_ae409/firmware/timing.c
@@ -0,0 +1,393 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+
+/* ddr configs */
+#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+
+#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = {
+{
+ /* ddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0,//CONFIG_DDR0_16BIT_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ /* DRAMFreq = 192, 256, 384, 512, 768-1536 */
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 768,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1176, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {16,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+};
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = AML_CUSTOMER_ID,
+ .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */
+ .log_ctrl = (1<<7) | /* (1<<7), print bl2 log into buffer */
+#ifdef CONFIG_SILENT_CONSOLE
+ (1<<6), /* do not print log buffer */
+#else
+ (0<<6), /* print log buffer before run bl31 */
+#endif
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1040)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1030)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1020)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1010)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 1000)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 990)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 980)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 970)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 960)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 950)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 940)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 930)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 920)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 910)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 900)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 890)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 880)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 870)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 860)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 850)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 840)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 830)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 820)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 810)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 800)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 790)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 780)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 770)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 760)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 750)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 740)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 730)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 720)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 710)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 700)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/
+#if (VDDEE_VAL == 741)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 751)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 761)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 771)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 781)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 791)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 801)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 811)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 821)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 831)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 841)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 851)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 861)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 871)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 881)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 891)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 902)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 912)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 922)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/*
+ * GPIOE_0 PWM_A VDDEE_PWM
+ *
+ * GPIOE_1 PWM_B VCCK_PWM
+ */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400)
+
+/* pwm clock and pwm controller */
+#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800)
+#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400)
+#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400)
+#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400)
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ {0, 0, 0xffffffff, 0, 0, 0},
+ {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0},
+ /* enable vddcpu dc-dc, set GPIOD_10 high */
+ {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ /* set pwm A and pwm B clock rate to 24M, enable them */
+ {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3*/
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/c2_af400/Kconfig b/board/amlogic/c2_af400/Kconfig
new file mode 100644
index 0000000..47dd569
--- /dev/null
+++ b/board/amlogic/c2_af400/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_C2_AF400
+
+config SYS_SOC
+ default "c2"
+
+config SYS_BOARD
+ default "c2_af400"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "c2_af400"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default y
+ help
+ support plltest command
+
+endif
diff --git a/board/amlogic/c2_af400/Makefile b/board/amlogic/c2_af400/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/c2_af400/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_af400/aml-key/bl2aesiv b/board/amlogic/c2_af400/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c2_af400/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/c2_af400/aml-key/bl2aeskey b/board/amlogic/c2_af400/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c2_af400/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/c2_af400/aml-key/bl3xaesiv b/board/amlogic/c2_af400/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c2_af400/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/c2_af400/aml-key/bl3xaeskey b/board/amlogic/c2_af400/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c2_af400/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/c2_af400/aml-key/kernelaesiv b/board/amlogic/c2_af400/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c2_af400/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/c2_af400/aml-key/kernelaeskey b/board/amlogic/c2_af400/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c2_af400/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/c2_af400/aml-user-key.sig b/board/amlogic/c2_af400/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/c2_af400/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/c2_af400/c2_af400.c b/board/amlogic/c2_af400/c2_af400.c
new file mode 100644
index 0000000..ef52f5f
--- /dev/null
+++ b/board/amlogic/c2_af400/c2_af400.c
@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+unsigned int get_dram_size(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+}
+
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = 0;
+ gd->bd->bi_dram[0].size = get_dram_size();
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+void board_init_mem(void) {
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+}
+
+/* set dts props */
+void aml_config_dtb(void)
+{
+ cpu_id_t cpuid = get_cpu_id();
+ if (MESON_CPU_MAJOR_ID_C2 != cpuid.family_id)
+ return;
+
+ run_command("fdt address $dtb_mem_addr", 0);
+ printf("%s %d\n", __func__, __LINE__);
+ if (cpuid.chip_rev == 0xA) {
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt rm /soc/emmc mmc-hs400-1_8v", 0);
+ run_command("fdt rm /soc/emmc fixed-emmc-driver-type", 0);
+ run_command("fdt print /soc/emmc", 0);
+ } else {
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt set /soc/bus/pinctrl/emmc/mux drive-strength <4>", 0);
+ run_command("fdt set /soc/bus/pinctrl/emmc/mux1 drive-strength <4>", 0);
+ run_command("fdt set /soc/bus/pinctrl/emmc_clk_gate/mux drive-strength <4>", 0);
+ run_command("fdt print /soc/bus/pinctrl/emmc", 0);
+ run_command("fdt print /soc/bus/pinctrl/emmc_clk_gate", 0);
+ }
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ active_clk();
+
+ run_command("gpio c GPIOA_10", 0);
+ run_command("gpio c GPIOA_12", 0);
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ aml_config_dtb();
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+#ifdef UBOOT_RUN_IN_SRAM
+ return 0x180000; /* SRAM 1.5MB */
+#else
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+#endif /* UBOOT_RUN_IN_SRAM */
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/*
+* mtd nand partition table, only care the size!
+* offset will be calculated by nand driver.
+*/
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+/* MUST NOT CHANGE this part unless u know what you are doing!
+* inherent parition for descrete bootloader to store fip
+* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+* name must be same with TPL_PART_NAME
+*/
+{
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 32*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 32*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 304*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "misc",
+ .offset = 0,
+ .size = 8 * SZ_8K,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_af400/firmware/timing.c b/board/amlogic/c2_af400/firmware/timing.c
new file mode 100644
index 0000000..2674e8e
--- /dev/null
+++ b/board/amlogic/c2_af400/firmware/timing.c
@@ -0,0 +1,3504 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+#define TIMMING_MAX_CONFIG 1
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = {
+#if 1//timing_config,af400
+{
+ //af400
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-20,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128-20,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,},
+ #endif
+ #if 0
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,50,40,50,40,50,40,50},//total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {
+ (0 << 7) | 6, (0 << 7) | 16, (0 << 7) | 10, (0 << 7) | 3,
+ (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0,
+ (0 << 7) | 2, (0 << 7) | 4, (0 << 7) | 4, (0 << 7) | 10,
+ (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0,
+ },
+
+ //pinmux setting
+ #if 1 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af400
+
+#if 0//timing_config,af409
+{
+ //af409
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,90,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,90,128,128,128,128,128,
+ 256,256,256,256,256,256,256,256,
+ 256,256,256,256,256,256,256,256,
+ 256,256,256,256,256,256,256,256,
+ 256,256,256,256,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,},
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {266,266,266,266,0+300-128,0+300-128,0+300-128,0+300-128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,},
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,50,40,50,40,50,40,50} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 1 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af409
+
+#if 0//timing_config,af419
+{
+ //af419
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-40,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128-40,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,},
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000154,// 340
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x0000014f,// 335
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000013b,// 315
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000159,// 345
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000019e,// 414
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000189,// 393
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000183,// 387
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001a6,// 422
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001ab,// 427
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000192,// 402
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000018d,// 397
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x00000192,// 402
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x00000196,// 406
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000180,// 384
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000180,// 384
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000173,// 371
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000018e,// 398
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x00000186,// 390
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000179,// 377
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x00000184,// 388
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x00000180,// 384
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x0000017d,// 381
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000016d,// 365
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x0000018c,// 396
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x0000017e,// 382
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x0000018f,// 399
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x00000183,// 387
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x0000018d,// 397
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x0000017e,// 382
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x00000197,// 407
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000018e,// 398
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000199,// 409
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000181,// 385
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000017b,// 379
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000018f,// 399
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000189,// 393
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 1 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af419
+
+#if 0//timing_config,af401 DDR3
+{
+ //af401 DDR3
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_512MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,CONFIG_DDR0_SIZE_768MB
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT,
+ .cfg_board_common_setting. fast_boot = {0},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 912,//1008,912,792,667
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-20,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128-20,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,},
+ #endif
+ #if 0
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896-128,896-128,896-128,896-128,896-128,896-128,896-128,896-128} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000069,// 105
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x0000007d,// 125
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000069,// 105
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000019,// 25
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000000ad,// 173
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x0000009c,// 156
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x0000009e,// 158
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000000a9,// 169
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000b5,// 181
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000b8,// 184
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000b6,// 182
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000aa,// 170
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a5,// 165
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000c8,// 200
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000c7,// 199
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000bf,// 191
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000ba,// 186
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000b4,// 180
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000ab,// 171
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b6,// 182
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ac,// 172
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000ae,// 174
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000b4,// 180
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000c4,// 196
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000ba,// 186
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000c4,// 196
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000ba,// 186
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c8,// 200
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d2,// 210
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c5,// 197
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000b7,// 183
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000b7,// 183
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000b9,// 185
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000c1,// 193
+
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037e,// 894
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000036a,// 874
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000378,// 888
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000370,// 880
+
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000087,// 135
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000008b,// 139
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000072,// 114
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x00000093,// 147
+
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000003a,// 58
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000053,// 83
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000056,// 86
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000056,// 86
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000077,// 119
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000038,// 56
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000055,// 85
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x0000003e,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x0000004b,// 75
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000004b,// 75
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000094,// 148
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000038,// 56
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000040,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000055,// 85
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000049,// 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000056,// 86
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000061,// 97
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000053,// 83
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x0000005a,// 90
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000040,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000047,// 71
+ #endif
+
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32+5,32,32+5,32,32+5,32,32+5,},//total 44
+
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter = {DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR3,} ,
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 1 //real DDR3
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af401 DDR3
+
+#if 0 //timing_config,af400 LPDDR4 rank01
+{
+ //af400 LPDDR4 rank01
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_1024MB,
+ .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,//DDR_WRITE_READ_DBI_DISABLE,DDR_READ_DBI_ENABLE
+ //.cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_READ_DBI_ENABLE,//DDR_WRITE_READ_DBI_DISABLE ,
+ //.cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_READ_DBI_ENABLE|DDR_WRITE_DBI_ENABLE,//DDR_WRITE_READ_DBI_DISABLE ,
+ //enable write dbi need dq pinmux correct,since of write mask pattern is fixed in current design
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_DDR3_32BIT
+ .cfg_board_common_setting.fast_boot = { 0 },
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_80_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_80_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 300,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 330, //330
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
+#if 0
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 0, 0, 0, 0, 0, 0, 0, 0, //0,0,0,0,0,0,0,0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ }, //total 36
+#endif
+#if 1
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0,
+ 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ }, //total 36
+#endif
+
+#if 0
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay = {
+ 128, 128, 128, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+#endif
+#if 1 //default cs cke 0 ,other AC=128
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay = {
+ 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0,
+ 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ }, //total 36
+#endif
+#if 0
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay = {
+ 64 + 128, 30 + 128 + 13, 30 + 128, 30 + 128, 17 + 128, 30 + 128, 30 + 128, 30 + 128
+ },
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = {
+ 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128,
+ 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33,
+ 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128,
+ 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128,
+ 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128,
+ 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128,
+ 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128,
+ 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128,
+ 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128,
+ },
+
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = {
+ 1357, 1400, 1400, 1400, 1357, 1400, 1400, 1400
+ }, //total 8 //edge mode
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay = {
+ 64, 64, 64, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, //total 72
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref = {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 26, 32, 26,
+ 32, 26, 32, 26
+ }, //total 44
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref = {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
+#endif
+
+#if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d, // 125
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000069, // 105
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000087, // 135
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x00000073, // 115
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x00000087, // 135
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x00000069, // 105
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x00000091, // 145
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x00000087, // 135
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x00000251, // 593
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x00000250, // 592
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x0000024c, // 588
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x00000256, // 598
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x0000025a, // 602
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x0000025d, // 605
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x00000251, // 593
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x0000025b, // 603
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x00000255, // 597
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x00000241, // 577
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x00000248, // 584
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x0000023e, // 574
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x00000245, // 581
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x0000024d, // 589
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x00000247, // 583
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x00000245, // 581
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x00000246, // 582
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x00000243, // 579
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x00000257, // 599
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x0000025d, // 605
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x00000254, // 596
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x00000260, // 608
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x00000261, // 609
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x0000025f, // 607
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x0000025a, // 602
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x0000025f, // 607
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x00000259, // 601
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x00000253, // 595
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x0000025d, // 605
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x00000250, // 592
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x00000263, // 611
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x00000254, // 596
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x00000252, // 594
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x00000251, // 593
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x00000252, // 594
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x0000025b, // 603
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d, // 125
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000069, // 105
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000087, // 135
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x00000073, // 115
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0 + 4] = 0x0000007d, // 125
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1 + 4] = 0x00000069, // 105
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2 + 4] = 0x00000087, // 135
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3 + 4] = 0x00000073, // 115
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0 + 36] = 0x00000251, // 593
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1 + 36] = 0x00000250, // 592
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2 + 36] = 0x0000024c, // 588
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3 + 36] = 0x00000256, // 598
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4 + 36] = 0x0000025a, // 602
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5 + 36] = 0x0000025d, // 605
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6 + 36] = 0x00000251, // 593
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7 + 36] = 0x0000025b, // 603
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8 + 36] = 0x00000255, // 597
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9 + 36] = 0x00000241, // 577
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10 + 36] = 0x00000248, // 584
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11 + 36] = 0x0000023e, // 574
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12 + 36] = 0x00000245, // 581
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13 + 36] = 0x0000024d, // 589
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14 + 36] = 0x00000247, // 583
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15 + 36] = 0x00000245, // 581
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16 + 36] = 0x00000246, // 582
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17 + 36] = 0x00000243, // 579
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18 + 36] = 0x00000257, // 599
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19 + 36] = 0x0000025d, // 605
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20 + 36] = 0x00000254, // 596
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21 + 36] = 0x00000260, // 608
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22 + 36] = 0x00000261, // 609
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23 + 36] = 0x0000025f, // 607
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24 + 36] = 0x0000025a, // 602
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25 + 36] = 0x0000025f, // 607
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26 + 36] = 0x00000259, // 601
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27 + 36] = 0x00000253, // 595
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28 + 36] = 0x0000025d, // 605
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29 + 36] = 0x00000250, // 592
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30 + 36] = 0x00000263, // 611
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31 + 36] = 0x00000254, // 596
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32 + 36] = 0x00000252, // 594
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33 + 36] = 0x00000251, // 593
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34 + 36] = 0x00000252, // 594
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35 + 36] = 0x0000025b, // 603
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x00000744, // 1860
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x00000744, // 1860
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x00000744, // 1860
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000744, // 1860
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0 + 4] = 0x00000744, // 1860
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1 + 4] = 0x00000744, // 1860
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2 + 4] = 0x00000744, // 1860
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3 + 4] = 0x00000744, // 1860
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007a, // 122
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x00000072, // 114
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x00000079, // 121
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x00000076, // 118
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0 + 4] = 0x0000007a, // 122
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1 + 4] = 0x00000072, // 114
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2 + 4] = 0x00000079, // 121
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3 + 4] = 0x00000076, // 118
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x0000003a, // 58
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004c, // 76
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x00000036, // 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049, // 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000056, // 86
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000036, // 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000032, // 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x0000003e, // 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x00000041, // 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x0000004e, // 78
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048, // 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x0000003e, // 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047, // 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000005b, // 91
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x0000004a, // 74
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = 0x0000003f, // 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = 0x0000003e, // 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x00000033, // 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000003e, // 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000052, // 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0 + 36] = 0x0000003a, // 58
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1 + 36] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2 + 36] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3 + 36] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4 + 36] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5 + 36] = 0x0000004c, // 76
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6 + 36] = 0x00000036, // 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7 + 36] = 0x00000049, // 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8 + 36] = 0x00000056, // 86
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9 + 36] = 0x00000036, // 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10 + 36] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11 + 36] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12 + 36] = 0x00000032, // 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13 + 36] = 0x0000003e, // 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14 + 36] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15 + 36] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16 + 36] = 0x00000041, // 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17 + 36] = 0x0000004e, // 78
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18 + 36] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19 + 36] = 0x00000048, // 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20 + 36] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21 + 36] = 0x0000003e, // 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22 + 36] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23 + 36] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24 + 36] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25 + 36] = 0x00000047, // 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26 + 36] = 0x0000005b, // 91
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27 + 36] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28 + 36] = 0x0000004a, // 74
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29 + 36] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30 + 36] = 0x0000003f, // 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31 + 36] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32 + 36] = 0x0000003e, // 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33 + 36] = 0x00000033, // 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34 + 36] = 0x0000003e, // 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35 + 36] = 0x00000052, // 82
+#endif
+#if 1
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[0] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[1] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[2] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[3] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[4] = 0x00000019, // 25
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[5] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[6] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[7] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[8] = 0x00000018, // 32 //0x20
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[9] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[10] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[11] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[12] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[13] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[14] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[15] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[16] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[17] = 0x00000018, // 32
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[18] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[19] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[20] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[21] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[22] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[23] = 0x00000019, // 25
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[24] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[25] = 0x00000019, // 25
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[26] = 0x00000018, // 32
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[27] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[28] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[29] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[30] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[31] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[32] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[33] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[34] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[35] = 0x00000018, // 32
+#endif
+#if 1
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[36] = 0x00000018, // 32
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[37] = 0x00000020 - 8, // 34
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[38] = 0x00000018, // 32
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[39] = 0x00000020 - 8, // 34
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[40] = 0x00000018, // 32
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[41] = 0x00000020 - 8, // 34
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[42] = 0x00000018, // 32
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[43] = 0x00000020 - 8, // 34
+#endif
+#if 1
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[0] = 0x00000000, // 0X5b,// 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[1] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[2] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[3] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[4] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[5] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[6] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[7] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[8] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[9] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[10] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[11] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[12] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[13] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[14] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[15] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[16] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[17] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[18] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[19] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[20] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[21] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[22] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[23] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[24] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[25] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[26] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[27] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[28] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[29] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[30] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[31] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[32] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[33] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[34] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[35] = 0x00000000, // 0
+#endif
+
+ //lpddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux = {
+ 0, 0, 0, 1, 0, 1, 0, 5,
+ 0, 1, 0, 0, 4, 0, 5, 0,
+ 1, 3, 3, 4, 2, 0, 0, 0,
+ 0, 0, 0, 2, 0, 0, 0, 0,
+ 0, 0,
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+#if 0
+ .cfg_board_common_setting.ddr_dq_remap = {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+#endif
+
+#if 1
+ .cfg_board_common_setting.ddr_dq_remap = {
+ 0, 4, 1, 2, 3, 5, 7, 6,
+ 12, 13, 9, 11, 8, 15, 14, 10,
+ 20, 21, 22, 23, 16, 17, 19, 18,
+ 31, 29, 30, 28, 24, 26, 27, 25,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+#endif
+
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG,
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].ac_trace_delay = {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+
+ .cfg_ddr_training_delay_ps[1].write_dqs_delay = {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = {
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ },
+ .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = {
+ 192, 192, 192, 192, 192, 192, 192, 192
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dqs_delay = {
+ 64, 64, 64, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, //total 72
+ .cfg_ddr_training_delay_ps[1].soc_bit_vref = {
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40
+ }, //total 44
+ .cfg_ddr_training_delay_ps[1].dram_bit_vref = {
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },//ddr_set_t end
+},
+#endif //end af400 LPDDR4 rank01
+
+#if 0 //timing_config,af400 LPDDR4 rank0
+{
+ //af400 LPDDR4 rank0
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,//DDR_WRITE_READ_DBI_DISABLE,DDR_READ_DBI_ENABLE
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_DDR3_32BIT
+ .cfg_board_common_setting.fast_boot = { 0 },
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_80_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_80_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 300,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 330, //330
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
+#if 0
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 0, 0, 0, 0, 0, 0, 0, 0, //0,0,0,0,0,0,0,0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0,
+ }, //total 36
+#endif
+#if 1
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0,
+ 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ }, //total 36
+#endif
+
+#if 0
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay = {
+ 128, 128, 128, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+#endif
+#if 1 //default cs cke 0 ,other AC=128
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay = {
+ 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0,
+ 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128, 128 + 20 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ }, //total 36
+#endif
+#if 0
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay = {
+ 64 + 128, 30 + 128 + 13, 30 + 128, 30 + 128, 17 + 128, 30 + 128, 30 + 128, 30 + 128
+ },
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay = {
+ 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128, 64 + 37 + 128 + 256 + 128,
+ 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33, 64 + 30 + 128 + 256 + 128 - 33,
+ 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128,
+ 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128, 64 + 17 + 128 + 256 + 128,
+ 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128,
+ 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128,
+ 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128,
+ 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128,
+ 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128, 64 + 30 + 128 + 256 + 128,
+ },
+
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay = {
+ 1357, 1400, 1400, 1400, 1357, 1400, 1400, 1400
+ }, //total 8 //edge mode
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay = {
+ 64, 64, 64, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay = {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, //total 72
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref = {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 26, 32, 26,
+ 32, 26, 32, 26
+ }, //total 44
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref = {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
+#endif
+
+#if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d, // 125
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000069, // 105
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000087, // 135
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x00000073, // 115
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4] = 0x00000087, // 135
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5] = 0x00000069, // 105
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6] = 0x00000091, // 145
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7] = 0x00000087, // 135
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0] = 0x00000251, // 593
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1] = 0x00000250, // 592
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2] = 0x0000024c, // 588
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3] = 0x00000256, // 598
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4] = 0x0000025a, // 602
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5] = 0x0000025d, // 605
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6] = 0x00000251, // 593
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7] = 0x0000025b, // 603
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8] = 0x00000255, // 597
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9] = 0x00000241, // 577
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10] = 0x00000248, // 584
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11] = 0x0000023e, // 574
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12] = 0x00000245, // 581
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13] = 0x0000024d, // 589
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14] = 0x00000247, // 583
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15] = 0x00000245, // 581
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16] = 0x00000246, // 582
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17] = 0x00000243, // 579
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18] = 0x00000257, // 599
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19] = 0x0000025d, // 605
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20] = 0x00000254, // 596
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21] = 0x00000260, // 608
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22] = 0x00000261, // 609
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23] = 0x0000025f, // 607
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24] = 0x0000025a, // 602
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25] = 0x0000025f, // 607
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26] = 0x00000259, // 601
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27] = 0x00000253, // 595
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28] = 0x0000025d, // 605
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29] = 0x00000250, // 592
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30] = 0x00000263, // 611
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31] = 0x00000254, // 596
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32] = 0x00000252, // 594
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33] = 0x00000251, // 593
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34] = 0x00000252, // 594
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35] = 0x0000025b, // 603
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0] = 0x0000007d, // 125
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1] = 0x00000069, // 105
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2] = 0x00000087, // 135
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3] = 0x00000073, // 115
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0 + 4] = 0x0000007d, // 125
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1 + 4] = 0x00000069, // 105
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2 + 4] = 0x00000087, // 135
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3 + 4] = 0x00000073, // 115
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0 + 36] = 0x00000251, // 593
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1 + 36] = 0x00000250, // 592
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2 + 36] = 0x0000024c, // 588
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3 + 36] = 0x00000256, // 598
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4 + 36] = 0x0000025a, // 602
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5 + 36] = 0x0000025d, // 605
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6 + 36] = 0x00000251, // 593
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7 + 36] = 0x0000025b, // 603
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8 + 36] = 0x00000255, // 597
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9 + 36] = 0x00000241, // 577
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10 + 36] = 0x00000248, // 584
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11 + 36] = 0x0000023e, // 574
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12 + 36] = 0x00000245, // 581
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13 + 36] = 0x0000024d, // 589
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14 + 36] = 0x00000247, // 583
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15 + 36] = 0x00000245, // 581
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16 + 36] = 0x00000246, // 582
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17 + 36] = 0x00000243, // 579
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18 + 36] = 0x00000257, // 599
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19 + 36] = 0x0000025d, // 605
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20 + 36] = 0x00000254, // 596
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21 + 36] = 0x00000260, // 608
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22 + 36] = 0x00000261, // 609
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23 + 36] = 0x0000025f, // 607
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24 + 36] = 0x0000025a, // 602
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25 + 36] = 0x0000025f, // 607
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26 + 36] = 0x00000259, // 601
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27 + 36] = 0x00000253, // 595
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28 + 36] = 0x0000025d, // 605
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29 + 36] = 0x00000250, // 592
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30 + 36] = 0x00000263, // 611
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31 + 36] = 0x00000254, // 596
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32 + 36] = 0x00000252, // 594
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33 + 36] = 0x00000251, // 593
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34 + 36] = 0x00000252, // 594
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35 + 36] = 0x0000025b, // 603
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0] = 0x00000744, // 1860
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1] = 0x00000744, // 1860
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2] = 0x00000744, // 1860
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3] = 0x00000744, // 1860
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0 + 4] = 0x00000744, // 1860
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1 + 4] = 0x00000744, // 1860
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2 + 4] = 0x00000744, // 1860
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3 + 4] = 0x00000744, // 1860
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0] = 0x0000007a, // 122
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1] = 0x00000072, // 114
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2] = 0x00000079, // 121
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3] = 0x00000076, // 118
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0 + 4] = 0x0000007a, // 122
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1 + 4] = 0x00000072, // 114
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2 + 4] = 0x00000079, // 121
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3 + 4] = 0x00000076, // 118
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0] = 0x0000003a, // 58
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5] = 0x0000004c, // 76
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6] = 0x00000036, // 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7] = 0x00000049, // 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8] = 0x00000056, // 86
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9] = 0x00000036, // 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12] = 0x00000032, // 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13] = 0x0000003e, // 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16] = 0x00000041, // 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17] = 0x0000004e, // 78
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19] = 0x00000048, // 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21] = 0x0000003e, // 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25] = 0x00000047, // 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26] = 0x0000005b, // 91
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28] = 0x0000004a, // 74
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30] = 0x0000003f, // 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32] = 0x0000003e, // 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33] = 0x00000033, // 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34] = 0x0000003e, // 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35] = 0x00000052, // 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0 + 36] = 0x0000003a, // 58
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1 + 36] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2 + 36] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3 + 36] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4 + 36] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5 + 36] = 0x0000004c, // 76
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6 + 36] = 0x00000036, // 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7 + 36] = 0x00000049, // 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8 + 36] = 0x00000056, // 86
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9 + 36] = 0x00000036, // 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10 + 36] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11 + 36] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12 + 36] = 0x00000032, // 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13 + 36] = 0x0000003e, // 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14 + 36] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15 + 36] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16 + 36] = 0x00000041, // 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17 + 36] = 0x0000004e, // 78
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18 + 36] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19 + 36] = 0x00000048, // 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20 + 36] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21 + 36] = 0x0000003e, // 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22 + 36] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23 + 36] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24 + 36] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25 + 36] = 0x00000047, // 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26 + 36] = 0x0000005b, // 91
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27 + 36] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28 + 36] = 0x0000004a, // 74
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29 + 36] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30 + 36] = 0x0000003f, // 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31 + 36] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32 + 36] = 0x0000003e, // 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33 + 36] = 0x00000033, // 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34 + 36] = 0x0000003e, // 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35 + 36] = 0x00000052, // 82
+#endif
+#if 1
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[0] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[1] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[2] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[3] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[4] = 0x00000019, // 25
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[5] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[6] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[7] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[8] = 0x00000018, // 32 //0x20
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[9] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[10] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[11] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[12] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[13] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[14] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[15] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[16] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[17] = 0x00000018, // 32
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[18] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[19] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[20] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[21] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[22] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[23] = 0x00000019, // 25
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[24] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[25] = 0x00000019, // 25
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[26] = 0x00000018, // 32
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[27] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[28] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[29] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[30] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[31] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[32] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[33] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[34] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[35] = 0x00000018, // 32
+#endif
+#if 1
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[36] = 0x00000018, // 32
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[37] = 0x00000020 - 8, // 34
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[38] = 0x00000018, // 32
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[39] = 0x00000020 - 8, // 34
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[40] = 0x00000018, // 32
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[41] = 0x00000020 - 8, // 34
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[42] = 0x00000018, // 32
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref[43] = 0x00000020 - 8, // 34
+#endif
+#if 1
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[0] = 0x00000000, // 0X5b,// 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[1] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[2] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[3] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[4] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[5] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[6] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[7] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[8] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[9] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[10] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[11] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[12] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[13] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[14] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[15] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[16] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[17] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[18] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[19] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[20] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[21] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[22] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[23] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[24] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[25] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[26] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[27] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[28] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[29] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[30] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[31] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[32] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[33] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[34] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref[35] = 0x00000000, // 0
+#endif
+
+ //lpddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux = {
+ 0, 0, 0, 1, 0, 1, 0, 5,
+ 0, 1, 0, 0, 4, 0, 5, 0,
+ 1, 3, 3, 4, 2, 0, 0, 0,
+ 0, 0, 0, 2, 0, 0, 0, 0,
+ 0, 0,
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+#if 0
+ .cfg_board_common_setting.ddr_dq_remap = {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+#endif
+
+#if 1
+ .cfg_board_common_setting.ddr_dq_remap = {
+ 0, 4, 1, 2, 3, 5, 7, 6,
+ 12, 13, 9, 11, 8, 15, 14, 10,
+ 20, 21, 22, 23, 16, 17, 19, 18,
+ 31, 29, 30, 28, 24, 26, 27, 25,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+#endif
+
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = TIMMING_MAX_CONFIG,
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].ac_trace_delay = {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+
+ .cfg_ddr_training_delay_ps[1].write_dqs_delay = {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ .cfg_ddr_training_delay_ps[1].write_dq_bit_delay = {
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ },
+ .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay = {
+ 192, 192, 192, 192, 192, 192, 192, 192
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dqs_delay = {
+ 64, 64, 64, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dq_bit_delay = {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, //total 72
+ .cfg_ddr_training_delay_ps[1].soc_bit_vref = {
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40
+ }, //total 44
+ .cfg_ddr_training_delay_ps[1].dram_bit_vref = {
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },//ddr_set_t end
+},
+#endif //end af400 LPDDR4 rank0
+
+#if 0//timing_config,af409 LPDDR4
+{
+ //af409
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0},
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ #if 0
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ },//total 36
+ #endif
+ #if 1
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 0,0,0,0,0,0,0,0,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,},
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,},
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,40,32,40,32,40,32,40} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 1 //lpddr4
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 0, 1,
+ 0, 5, 1, 2, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 8,15,11,13,9,12,14,10,
+ 3,0,6,4,5,7,2,1,
+ 17,18,23,22,20,21,19,16,
+ 28,30,27,25,26,24,29,31,
+ 33,32,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af409 LPDDR4
+
+#if 0 //timing_config,for dd3 pxp
+//ddr_set_t ddr_set_t_default=
+{
+ .cfg_board_common_setting. timming_magic = 0 ,
+ .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_version = 0 ,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_real_size = 0 , //0
+ .cfg_board_common_setting. fast_boot = {0} ,
+ .cfg_board_common_setting. ddr_func = 0 ,
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK ,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3 ,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 ,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 ,
+ .cfg_board_common_setting. dram_cs0_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs1_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB ,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB ,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 ,
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE ,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC ,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE ,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE ,
+ .cfg_board_common_setting. org_tdqs2dq = 0 ,
+ .cfg_board_common_setting. reserve1_test_function = {0} ,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT ,
+ #if 0
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ } ,
+
+ //ac_group0-ac_group1
+ #endif
+ #if 1
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ } ,
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0 ,
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 14,13,12,15,8,9,11,10,
+ 20,21,22,23,16,17,19,18,
+ 24,25,28,26,31,30,27,29,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,3,1,0,6,7,4,5,
+ 11,10,9,8,15,14,13,12,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ //1,0,3,2,5,4,7,6,
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,7,1,5,3,6,0,4,
+ 10,11,15,13,14,9,8,12,
+ 24,29,26,31,25,28,27,30,
+ 23,18,21,19,22,17,20,16,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35,
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ .cfg_board_common_setting. ddr_vddee_setting = {0} ,
+
+
+ .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[0]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #if 0
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 123,124,0,126,127,0,0,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,} ,
+ #endif
+ #if 0 //real board
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,} ,
+
+
+ #endif
+
+ #if 1 //for pxp
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} ,
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {128+512,128+512,128+512,128+512,128+512,128+512,128+512,128+512} , //total 8
+
+ #else
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} ,
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1094,1094,1094,1094,1094,1094,1094,1094} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896,896,896,896,896,896,896,896} , //total 8
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,
+ 42,42,42,42,42,42,42,42,42,42,
+ 42,42,42,42,42,58,42,58,42,58,42,58,} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+
+ .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[1]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #if 0
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ } , //total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64} ,
+ //total 72
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40} , //total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} ,
+},
+#endif //end for dd3 pxp
+
+#if 0 //timing_config,for ddr4 pxp remap
+//ddr_set_t ddr_set_t_default=
+{
+ .cfg_board_common_setting. timming_magic = 0 ,
+ .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_version = 0 ,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_real_size = 0 , //0
+ .cfg_board_common_setting. fast_boot = {0} ,
+ .cfg_board_common_setting. ddr_func = 0 ,
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK ,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4 ,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0 ,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 ,
+ .cfg_board_common_setting. dram_cs0_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs1_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB ,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB ,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 ,
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE ,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC ,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE ,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE ,
+ .cfg_board_common_setting. org_tdqs2dq = 0 ,
+ .cfg_board_common_setting. reserve1_test_function = {0} ,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT ,
+ #if 1 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 0
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ } ,
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0 ,
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 14,13,12,15,8,9,11,10,
+ 20,21,22,23,16,17,19,18,
+ 24,25,28,26,31,30,27,29,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,3,1,0,6,7,4,5,
+ 11,10,9,8,15,14,13,12,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ //1,0,3,2,5,4,7,6,
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,7,1,5,3,6,0,4,
+ 10,11,15,13,14,9,8,12,
+ 24,29,26,31,25,28,27,30,
+ 23,18,21,19,22,17,20,16,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ .cfg_board_common_setting. ddr_vddee_setting = {0} ,
+
+
+ .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM , //for pxp dram weak driver model
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[0]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #if 0
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ } , //total 36
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64} ,
+ //total 72
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {0,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,50,40,50,40,50,40,50} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {0,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[1]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #if 0
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ } , //total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64} ,
+ //total 72
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40} , //total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} ,
+},
+#endif //end for ddr4 pxp remap
+};
+//ddr timing end
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = AML_CUSTOMER_ID,
+ .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */
+ .log_ctrl = (1<<7) | /* (1<<7), print bl2 log into buffer */
+#ifdef CONFIG_SILENT_CONSOLE
+ (1<<6), /* do not print log buffer */
+#else
+ (0<<6), /* print log buffer before run bl31 */
+#endif
+.ddr_timming_save_mode = 1,
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/
+#if (VDDEE_VAL == 711)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 721)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 731)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 741)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 751)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 761)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 771)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 781)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 791)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 801)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 811)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 821)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 831)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 841)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 851)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 861)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 871)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 881)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 891)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/*
+ * GPIOE_0 PWM_A VDDEE_PWM
+ *
+ * GPIOE_1 PWM_B VCCK_PWM
+ */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400)
+
+/* pwm clock and pwm controller */
+#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800)
+#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400)
+#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400)
+#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400)
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ {0, 0, 0xffffffff, 0, 0, 0},
+ {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0},
+ /* enable vddcpu dc-dc, set GPIOD_10 high */
+ {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ /* set pwm A and pwm B clock rate to 24M, enable them */
+ {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3*/
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/c2_af401/Kconfig b/board/amlogic/c2_af401/Kconfig
new file mode 100644
index 0000000..74ba913
--- /dev/null
+++ b/board/amlogic/c2_af401/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_C2_AF401
+
+config SYS_SOC
+ default "c2"
+
+config SYS_BOARD
+ default "c2_af401"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "c2_af401"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default y
+ help
+ support plltest command
+
+endif
diff --git a/board/amlogic/c2_af401/Makefile b/board/amlogic/c2_af401/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/c2_af401/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_af401/aml-key/bl2aesiv b/board/amlogic/c2_af401/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c2_af401/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/c2_af401/aml-key/bl2aeskey b/board/amlogic/c2_af401/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c2_af401/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/c2_af401/aml-key/bl3xaesiv b/board/amlogic/c2_af401/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c2_af401/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/c2_af401/aml-key/bl3xaeskey b/board/amlogic/c2_af401/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c2_af401/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/c2_af401/aml-key/kernelaesiv b/board/amlogic/c2_af401/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c2_af401/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/c2_af401/aml-key/kernelaeskey b/board/amlogic/c2_af401/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c2_af401/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/c2_af401/aml-user-key.sig b/board/amlogic/c2_af401/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/c2_af401/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/c2_af401/c2_af401.c b/board/amlogic/c2_af401/c2_af401.c
new file mode 100644
index 0000000..ef52f5f
--- /dev/null
+++ b/board/amlogic/c2_af401/c2_af401.c
@@ -0,0 +1,346 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+unsigned int get_dram_size(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+}
+
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = 0;
+ gd->bd->bi_dram[0].size = get_dram_size();
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+void board_init_mem(void) {
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+}
+
+/* set dts props */
+void aml_config_dtb(void)
+{
+ cpu_id_t cpuid = get_cpu_id();
+ if (MESON_CPU_MAJOR_ID_C2 != cpuid.family_id)
+ return;
+
+ run_command("fdt address $dtb_mem_addr", 0);
+ printf("%s %d\n", __func__, __LINE__);
+ if (cpuid.chip_rev == 0xA) {
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt rm /soc/emmc mmc-hs400-1_8v", 0);
+ run_command("fdt rm /soc/emmc fixed-emmc-driver-type", 0);
+ run_command("fdt print /soc/emmc", 0);
+ } else {
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt set /soc/bus/pinctrl/emmc/mux drive-strength <4>", 0);
+ run_command("fdt set /soc/bus/pinctrl/emmc/mux1 drive-strength <4>", 0);
+ run_command("fdt set /soc/bus/pinctrl/emmc_clk_gate/mux drive-strength <4>", 0);
+ run_command("fdt print /soc/bus/pinctrl/emmc", 0);
+ run_command("fdt print /soc/bus/pinctrl/emmc_clk_gate", 0);
+ }
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ active_clk();
+
+ run_command("gpio c GPIOA_10", 0);
+ run_command("gpio c GPIOA_12", 0);
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ aml_config_dtb();
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+#ifdef UBOOT_RUN_IN_SRAM
+ return 0x180000; /* SRAM 1.5MB */
+#else
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+#endif /* UBOOT_RUN_IN_SRAM */
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/*
+* mtd nand partition table, only care the size!
+* offset will be calculated by nand driver.
+*/
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+/* MUST NOT CHANGE this part unless u know what you are doing!
+* inherent parition for descrete bootloader to store fip
+* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+* name must be same with TPL_PART_NAME
+*/
+{
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 32*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 32*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 304*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "misc",
+ .offset = 0,
+ .size = 8 * SZ_8K,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_af401/firmware/timing.c b/board/amlogic/c2_af401/firmware/timing.c
new file mode 100644
index 0000000..c8131f4
--- /dev/null
+++ b/board/amlogic/c2_af401/firmware/timing.c
@@ -0,0 +1,3104 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+#define TIMMING_MAX_CONFIG 1
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = {
+#if 0//timing_config,af400
+{
+ //af400
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-20,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay = {
+ 128,128,128-20,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,},
+ #endif
+ #if 0
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,50,40,50,40,50,40,50},//total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {
+ (0 << 7) | 6, (0 << 7) | 16, (0 << 7) | 10, (0 << 7) | 3,
+ (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0,
+ (0 << 7) | 2, (0 << 7) | 4, (0 << 7) | 4, (0 << 7) | 10,
+ (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0,
+ },
+
+ //pinmux setting
+ #if 1 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af400
+
+#if 0//timing_config,af409
+{
+ //af409
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,90,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,90,128,128,128,128,256,
+ 256,256,256,256,256,256,256,256,
+ 256,256,256,256,256,256,256,256,
+ 256,256,256,256,256,256,256,256,
+ 256,256,256,256,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,},
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {266,266,266,266,0+300-128,0+300-128,0+300-128,0+300-128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,},
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,50,40,50,40,50,40,50} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 1 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af409
+
+#if 0//timing_config,af419
+{
+ //af419
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-40,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128-40,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,},
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000154,// 340
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x0000014f,// 335
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000013b,// 315
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000159,// 345
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000019e,// 414
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000189,// 393
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000183,// 387
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001a6,// 422
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001ab,// 427
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000192,// 402
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000018d,// 397
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x00000192,// 402
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x00000196,// 406
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000180,// 384
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000180,// 384
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000173,// 371
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000018e,// 398
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x00000186,// 390
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000179,// 377
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x00000184,// 388
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x00000180,// 384
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x0000017d,// 381
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000016d,// 365
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x0000018c,// 396
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x0000017e,// 382
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x0000018f,// 399
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x00000183,// 387
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x0000018d,// 397
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x0000017e,// 382
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x00000197,// 407
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000018e,// 398
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000199,// 409
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000181,// 385
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000017b,// 379
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000018f,// 399
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000189,// 393
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 1 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af419
+
+#if 1//timing_config,af401 DDR3
+{
+ //af401 DDR3
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_512MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,CONFIG_DDR0_SIZE_768MB
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT,
+ .cfg_board_common_setting. fast_boot = {0},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 912,//1008,912,792,667
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-20,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128-20,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,},
+ #endif
+ #if 0
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896-128,896-128,896-128,896-128,896-128,896-128,896-128,896-128} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000069,// 105
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x0000007d,// 125
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000069,// 105
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000019,// 25
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000000ad,// 173
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x0000009c,// 156
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x0000009e,// 158
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000000a9,// 169
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000b5,// 181
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000b8,// 184
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000b6,// 182
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000aa,// 170
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a5,// 165
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000c8,// 200
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000c7,// 199
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000bf,// 191
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000ba,// 186
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000b4,// 180
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000ab,// 171
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b6,// 182
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ac,// 172
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000ae,// 174
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000b4,// 180
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000c4,// 196
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000ba,// 186
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000c4,// 196
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000ba,// 186
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c8,// 200
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d2,// 210
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c5,// 197
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000b7,// 183
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000b7,// 183
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000b9,// 185
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000c1,// 193
+
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037e,// 894
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000036a,// 874
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000378,// 888
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000370,// 880
+
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000087,// 135
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000008b,// 139
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000072,// 114
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x00000093,// 147
+
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000003a,// 58
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000053,// 83
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000056,// 86
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000056,// 86
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000077,// 119
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000038,// 56
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000055,// 85
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x0000003e,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x0000004b,// 75
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000004b,// 75
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000094,// 148
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000038,// 56
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000040,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000055,// 85
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000049,// 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000056,// 86
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000061,// 97
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000053,// 83
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x0000005a,// 90
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000040,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000047,// 71
+ #endif
+
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32+5,32,32+5,32,32+5,32,32+5,},//total 44
+
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter = {DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR3,} ,
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 1 //real DDR3
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af401 DDR3
+
+#if 0//timing_config,google DDR3 board
+{
+ //google DDR3 board
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,CONFIG_DDR0_SIZE_768MB
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT,
+ .cfg_board_common_setting. fast_boot = {0},
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 912,//1008,912,792,667
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-20,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128-20,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,},
+ #endif
+ #if 0
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896-128,896-128,896-128,896-128,896-128,896-128,896-128,896-128} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000007d,// 125
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000091,// 145
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000091,// 145
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x0000009b,// 155
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000000c2,// 194
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000000b0,// 176
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000000b0,// 176
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000c0,// 192
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000c3,// 195
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b4,// 180
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000be,// 190
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ba,// 186
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d5,// 213
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d0,// 208
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000cc,// 204
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000c3,// 195
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000be,// 190
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000c0,// 192
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000c8,// 200
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000e0,// 224
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000e5,// 229
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000e2,// 226
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000ec,// 236
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000ec,// 236
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000e7,// 231
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000e4,// 228
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000e9,// 233
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000e6,// 230
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000eb,// 235
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000f5,// 245
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000e7,// 231
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000fd,// 253
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000e8,// 232
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000e4,// 228
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ee,// 238
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ec,// 236
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000f2,// 242
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000038c,// 908
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000037a,// 890
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x0000039a,// 922
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000395,// 917
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007f-0x30,// 127
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000007d-0x30,// 125
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x0000006d-0x30,// 109
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000006f-0x30,// 111
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000048-0x30,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000044-0x30,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000038-0x30,// 56
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x0000003b-0x30,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000049-0x30,// 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x0000004b-0x30,// 75
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003b-0x30,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000049-0x30,// 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000040-0x30,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000052-0x30,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000039-0x30,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000040-0x30,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000045-0x30,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042-0x30,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000034-0x30,// 52
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000003c-0x30,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000086-0x30,// 134
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000003f-0x30,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000048-0x30,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000037-0x30,// 55
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000048-0x30,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=(0x0000004e)-0x30,// 78
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000044-0x30,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000042-0x30,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000047-0x30,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x0000007f-0x30,// 127
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000040-0x30,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000052-0x30,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d-0x30,// 61
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=(0x0000004e)-0x30,// 78
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003c-0x30,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=(0x0000003e)-0x30,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000003f-0x30,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x0000004c-0x30,// 76
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000091-0x30,// 145
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32+5,32,32+5,32,32+5,32,32+5,},//total 44
+
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter = {DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR3,} ,
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 1 //real DDR3
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end google DDR3 board
+
+#if 0//timing_config,af400 LPDDR4
+{
+ //af400
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,//DDR_WRITE_READ_DBI_DISABLE,DDR_READ_DBI_ENABLE
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_DDR3_32BIT
+ .cfg_board_common_setting. fast_boot = {0},
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 667,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_80_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_80_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 300,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 330,//330
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1//default cs cke 0 ,other AC=128
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,0,0, //0,0,0,0,0,0,0,0,
+ 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,
+ 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,
+ 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,
+ 128+128,128+128,128+128,128+128,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ } ,
+ #endif
+ #if 1
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1024,1024,1024,1024,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ #endif
+
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref = {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 26, 32, 26,
+ 32, 26, 32, 26
+ }, //total 44
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref = {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 1 //lpddr4
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 0, 1,
+ 0, 5, 0, 1, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0,
+ },
+ #endif
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 8,15,11,13,9,12,14,10,
+ 3,0,6,4,5,7,2,1,
+ 17,18,23,22,20,21,19,16,
+ 28,30,27,25,26,24,29,31,
+ 33,32,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af400 lpddr4
+
+#if 0//timing_config,af409 LPDDR4
+{
+ //af409
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0},
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ #if 0
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ },//total 36
+ #endif
+ #if 1
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 0,0,0,0,0,0,0,0,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,},
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,},
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,40,32,40,32,40,32,40} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 1 //lpddr4
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 0, 1,
+ 0, 5, 1, 2, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 8,15,11,13,9,12,14,10,
+ 3,0,6,4,5,7,2,1,
+ 17,18,23,22,20,21,19,16,
+ 28,30,27,25,26,24,29,31,
+ 33,32,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af409 LPDDR4
+
+#if 0 //timing_config,for dd3 pxp
+//ddr_set_t ddr_set_t_default=
+{
+ .cfg_board_common_setting. timming_magic = 0 ,
+ .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_version = 0 ,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_real_size = 0 , //0
+ .cfg_board_common_setting. fast_boot = {0} ,
+ .cfg_board_common_setting. ddr_func = 0 ,
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK ,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3 ,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 ,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 ,
+ .cfg_board_common_setting. dram_cs0_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs1_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB ,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB ,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 ,
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE ,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC ,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE ,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE ,
+ .cfg_board_common_setting. org_tdqs2dq = 0 ,
+ .cfg_board_common_setting. reserve1_test_function = {0} ,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT ,
+ #if 0
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ } ,
+
+ //ac_group0-ac_group1
+ #endif
+ #if 1
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ } ,
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0 ,
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 14,13,12,15,8,9,11,10,
+ 20,21,22,23,16,17,19,18,
+ 24,25,28,26,31,30,27,29,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,3,1,0,6,7,4,5,
+ 11,10,9,8,15,14,13,12,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ //1,0,3,2,5,4,7,6,
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,7,1,5,3,6,0,4,
+ 10,11,15,13,14,9,8,12,
+ 24,29,26,31,25,28,27,30,
+ 23,18,21,19,22,17,20,16,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35,
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ .cfg_board_common_setting. ddr_vddee_setting = {0} ,
+
+
+ .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[0]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #if 0
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 123,124,0,126,127,0,0,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,} ,
+ #endif
+ #if 0 //real board
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,} ,
+
+
+ #endif
+
+ #if 1 //for pxp
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} ,
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {128+512,128+512,128+512,128+512,128+512,128+512,128+512,128+512} , //total 8
+
+ #else
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} ,
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1094,1094,1094,1094,1094,1094,1094,1094} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896,896,896,896,896,896,896,896} , //total 8
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,
+ 42,42,42,42,42,42,42,42,42,42,
+ 42,42,42,42,42,58,42,58,42,58,42,58,} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+
+ .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[1]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #if 0
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ } , //total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64} ,
+ //total 72
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40} , //total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} ,
+},
+#endif //end for dd3 pxp
+
+#if 0 //timing_config,for ddr4 pxp remap
+//ddr_set_t ddr_set_t_default=
+{
+ .cfg_board_common_setting. timming_magic = 0 ,
+ .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_version = 0 ,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_real_size = 0 , //0
+ .cfg_board_common_setting. fast_boot = {0} ,
+ .cfg_board_common_setting. ddr_func = 0 ,
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK ,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4 ,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0 ,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 ,
+ .cfg_board_common_setting. dram_cs0_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs1_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB ,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB ,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 ,
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE ,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC ,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE ,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE ,
+ .cfg_board_common_setting. org_tdqs2dq = 0 ,
+ .cfg_board_common_setting. reserve1_test_function = {0} ,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT ,
+ #if 1 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 0
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ } ,
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0 ,
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 14,13,12,15,8,9,11,10,
+ 20,21,22,23,16,17,19,18,
+ 24,25,28,26,31,30,27,29,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,3,1,0,6,7,4,5,
+ 11,10,9,8,15,14,13,12,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ //1,0,3,2,5,4,7,6,
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,7,1,5,3,6,0,4,
+ 10,11,15,13,14,9,8,12,
+ 24,29,26,31,25,28,27,30,
+ 23,18,21,19,22,17,20,16,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ .cfg_board_common_setting. ddr_vddee_setting = {0} ,
+
+
+ .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM , //for pxp dram weak driver model
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[0]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #if 0
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ } , //total 36
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64} ,
+ //total 72
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {0,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,50,40,50,40,50,40,50} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {0,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[1]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #if 0
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ } , //total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64} ,
+ //total 72
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40} , //total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} ,
+},
+#endif //end for ddr4 pxp remap
+};
+//ddr timing end
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = AML_CUSTOMER_ID,
+ .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */
+ .log_ctrl = (1<<7) | /* (1<<7), print bl2 log into buffer */
+#ifdef CONFIG_SILENT_CONSOLE
+ (1<<6), /* do not print log buffer */
+#else
+ (0<<6), /* print log buffer before run bl31 */
+#endif
+.ddr_timming_save_mode = 1,
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/
+#if (VDDEE_VAL == 711)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 721)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 731)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 741)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 751)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 761)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 771)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 781)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 791)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 801)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 811)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 821)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 831)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 841)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 851)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 861)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 871)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 881)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 891)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/*
+ * GPIOE_0 PWM_A VDDEE_PWM
+ *
+ * GPIOE_1 PWM_B VCCK_PWM
+ */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400)
+
+/* pwm clock and pwm controller */
+#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800)
+#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400)
+#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400)
+#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400)
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ {0, 0, 0xffffffff, 0, 0, 0},
+ {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0},
+ /* enable vddcpu dc-dc, set GPIOD_10 high */
+ {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ /* set pwm A and pwm B clock rate to 24M, enable them */
+ {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3*/
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/c2_af402/Kconfig b/board/amlogic/c2_af402/Kconfig
new file mode 100644
index 0000000..0412bea
--- /dev/null
+++ b/board/amlogic/c2_af402/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_C2_AF402
+
+config SYS_SOC
+ default "c2"
+
+config SYS_BOARD
+ default "c2_af402"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "c2_af402"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default y
+ help
+ support plltest command
+
+endif
diff --git a/board/amlogic/c2_af402/Makefile b/board/amlogic/c2_af402/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/c2_af402/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_af402/aml-key/bl2aesiv b/board/amlogic/c2_af402/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c2_af402/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/c2_af402/aml-key/bl2aeskey b/board/amlogic/c2_af402/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c2_af402/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/c2_af402/aml-key/bl3xaesiv b/board/amlogic/c2_af402/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c2_af402/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/c2_af402/aml-key/bl3xaeskey b/board/amlogic/c2_af402/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c2_af402/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/c2_af402/aml-key/kernelaesiv b/board/amlogic/c2_af402/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c2_af402/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/c2_af402/aml-key/kernelaeskey b/board/amlogic/c2_af402/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c2_af402/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/c2_af402/aml-user-key.sig b/board/amlogic/c2_af402/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/c2_af402/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/c2_af402/c2_af402.c b/board/amlogic/c2_af402/c2_af402.c
new file mode 100644
index 0000000..3fbf756
--- /dev/null
+++ b/board/amlogic/c2_af402/c2_af402.c
@@ -0,0 +1,332 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+unsigned int get_dram_size(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+}
+
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = 0;
+ gd->bd->bi_dram[0].size = get_dram_size();
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+void board_init_mem(void) {
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+}
+
+/* set dts props */
+void aml_config_dtb(void)
+{
+ cpu_id_t cpuid = get_cpu_id();
+ if (MESON_CPU_MAJOR_ID_C2 != cpuid.family_id)
+ return;
+
+ run_command("fdt address $dtb_mem_addr", 0);
+ printf("%s %d\n", __func__, __LINE__);
+ if (cpuid.chip_rev == 0xA) {
+#if 0
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt rm /soc/emmc mmc-hs400-1_8v", 0);
+ run_command("fdt rm /soc/emmc fixed-emmc-driver-type", 0);
+ run_command("fdt print /soc/emmc", 0);
+#endif
+ } else {
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt set /soc/bus/pinctrl/emmc/mux drive-strength <4>", 0);
+ run_command("fdt set /soc/bus/pinctrl/emmc/mux1 drive-strength <4>", 0);
+ run_command("fdt set /soc/bus/pinctrl/emmc_clk_gate/mux drive-strength <4>", 0);
+ run_command("fdt print /soc/bus/pinctrl/emmc", 0);
+ run_command("fdt print /soc/bus/pinctrl/emmc_clk_gate", 0);
+ }
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ active_clk();
+
+ run_command("gpio c GPIOA_10", 0);
+ run_command("gpio c GPIOA_12", 0);
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ aml_config_dtb();
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+#ifdef UBOOT_RUN_IN_SRAM
+ return 0x180000; /* SRAM 1.5MB */
+#else
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+#endif /* UBOOT_RUN_IN_SRAM */
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/*
+* mtd nand partition table, only care the size!
+* offset will be calculated by nand driver.
+*/
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+/* MUST NOT CHANGE this part unless u know what you are doing!
+* inherent parition for descrete bootloader to store fip
+* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+* name must be same with TPL_PART_NAME
+*/
+{
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 32*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 8 * SZ_1M,
+ },
+ {
+ .name = "vendor",
+ .offset = 0,
+ .size = 32 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "misc",
+ .offset = 0,
+ .size = 8 * SZ_8K,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_af402/firmware/timing.c b/board/amlogic/c2_af402/firmware/timing.c
new file mode 100644
index 0000000..65d072d
--- /dev/null
+++ b/board/amlogic/c2_af402/firmware/timing.c
@@ -0,0 +1,3096 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+#define TIMMING_MAX_CONFIG 1
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = {
+#if 0//timing_config,af400
+{
+ //af400
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)},
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-20,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128-20,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,},
+ #endif
+ #if 0
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,50,40,50,40,50,40,50},//total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {
+ (0 << 7) | 6, (0 << 7) | 16, (0 << 7) | 10, (0 << 7) | 3,
+ (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0,
+ (0 << 7) | 2, (0 << 7) | 4, (0 << 7) | 4, (0 << 7) | 10,
+ (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0,
+ },
+
+ //pinmux setting
+ #if 1 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af400
+
+#if 0//timing_config,af409
+{
+ //af409
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)},
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,90,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,90,128,128,128,128,128,
+ 256,256,256,256,256,256,256,256,
+ 256,256,256,256,256,256,256,256,
+ 256,256,256,256,256,256,256,256,
+ 256,256,256,256,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,},
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {266,266,266,266,0+300-128,0+300-128,0+300-128,0+300-128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,},
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,50,40,50,40,50,40,50} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 1 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af409
+
+#if 0//timing_config,af419
+{
+ //af419
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)},
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-40,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128-40,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,},
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000154,// 340
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x0000014f,// 335
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000013b,// 315
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000159,// 345
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000019e,// 414
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000189,// 393
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000183,// 387
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001a6,// 422
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001ab,// 427
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000192,// 402
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000018d,// 397
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x00000192,// 402
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x00000196,// 406
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000180,// 384
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000180,// 384
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000173,// 371
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000018e,// 398
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x00000186,// 390
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000179,// 377
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x00000184,// 388
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x00000180,// 384
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x0000017d,// 381
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000016d,// 365
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x0000018c,// 396
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x0000017e,// 382
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x0000018f,// 399
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x00000183,// 387
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x0000018d,// 397
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x0000017e,// 382
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x00000197,// 407
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000018e,// 398
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000199,// 409
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000181,// 385
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000017b,// 379
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000018f,// 399
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000189,// 393
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 1 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af419
+
+#if 1//timing_config,af402 DDR3
+{
+ //af402 DDR3
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_16BIT_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,CONFIG_DDR0_SIZE_768MB
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR0_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_16BIT,
+ .cfg_board_common_setting. fast_boot = {0},
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 912,//1008,912,792,667
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-20,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128-20,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,},
+ #endif
+ #if 0
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896-128,896-128,896-128,896-128,896-128,896-128,896-128,896-128} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000069,// 105
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x0000007d,// 125
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000069,// 105
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000019,// 25
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000000ad,// 173
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x0000009c,// 156
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x0000009e,// 158
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000000a9,// 169
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000b5,// 181
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000b8,// 184
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000b6,// 182
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000aa,// 170
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a5,// 165
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000c8,// 200
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000c7,// 199
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000bf,// 191
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000ba,// 186
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000b4,// 180
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000ab,// 171
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b6,// 182
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ac,// 172
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000ae,// 174
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000b4,// 180
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000c4,// 196
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000ba,// 186
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000c4,// 196
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000ba,// 186
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c8,// 200
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d2,// 210
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c5,// 197
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000b7,// 183
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000b7,// 183
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000b9,// 185
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000c1,// 193
+
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037e,// 894
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000036a,// 874
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000378,// 888
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000370,// 880
+
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000087,// 135
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000008b,// 139
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000072,// 114
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x00000093,// 147
+
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000003a,// 58
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000053,// 83
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000056,// 86
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000056,// 86
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000077,// 119
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000038,// 56
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000055,// 85
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x0000003e,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x0000004b,// 75
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000004b,// 75
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000094,// 148
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000038,// 56
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000040,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000055,// 85
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000049,// 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000056,// 86
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000061,// 97
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000053,// 83
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x0000005a,// 90
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000040,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000047,// 71
+ #endif
+
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32+5,32,32+5,32,32+5,32,32+5,},//total 44
+
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter = {DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR3,} ,
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 1 //real DDR3
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = 0xFC,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af402 DDR3
+
+#if 0//timing_config,google DDR3 board
+{
+ //google DDR3 board
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,CONFIG_DDR0_SIZE_768MB
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT,
+ .cfg_board_common_setting. fast_boot = {0},
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 912,//1008,912,792,667
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-20,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128-20,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,},
+ #endif
+ #if 0
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896-128,896-128,896-128,896-128,896-128,896-128,896-128,896-128} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000007d,// 125
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000091,// 145
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000091,// 145
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x0000009b,// 155
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000000c2,// 194
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000000b0,// 176
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000000b0,// 176
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000c0,// 192
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000c3,// 195
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b4,// 180
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000be,// 190
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ba,// 186
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d5,// 213
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d0,// 208
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000cc,// 204
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000c3,// 195
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000be,// 190
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000c0,// 192
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000c8,// 200
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000e0,// 224
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000e5,// 229
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000e2,// 226
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000ec,// 236
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000ec,// 236
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000e7,// 231
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000e4,// 228
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000e9,// 233
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000e6,// 230
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000eb,// 235
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000f5,// 245
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000e7,// 231
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000fd,// 253
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000e8,// 232
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000e4,// 228
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ee,// 238
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ec,// 236
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000f2,// 242
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000038c,// 908
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000037a,// 890
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x0000039a,// 922
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000395,// 917
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007f-0x30,// 127
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000007d-0x30,// 125
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x0000006d-0x30,// 109
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000006f-0x30,// 111
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000048-0x30,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000044-0x30,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000038-0x30,// 56
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x0000003b-0x30,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000049-0x30,// 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x0000004b-0x30,// 75
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003b-0x30,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000049-0x30,// 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000040-0x30,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000052-0x30,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000039-0x30,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000040-0x30,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000045-0x30,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042-0x30,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000034-0x30,// 52
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000003c-0x30,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000086-0x30,// 134
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000003f-0x30,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000048-0x30,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000037-0x30,// 55
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000048-0x30,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=(0x0000004e)-0x30,// 78
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000044-0x30,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000042-0x30,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000047-0x30,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x0000007f-0x30,// 127
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000040-0x30,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000052-0x30,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d-0x30,// 61
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=(0x0000004e)-0x30,// 78
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003c-0x30,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=(0x0000003e)-0x30,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000003f-0x30,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x0000004c-0x30,// 76
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000091-0x30,// 145
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32+5,32,32+5,32,32+5,32,32+5,},//total 44
+
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter = {DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR3,} ,
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 1 //real DDR3
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end google DDR3 board
+
+#if 0//timing_config,af400 LPDDR4
+{
+ //af400
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,//DDR_WRITE_READ_DBI_DISABLE,DDR_READ_DBI_ENABLE
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_DDR3_32BIT
+ .cfg_board_common_setting. fast_boot = {0},
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 667,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_80_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_80_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 300,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 330,//330
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1//default cs cke 0 ,other AC=128
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,0,0, //0,0,0,0,0,0,0,0,
+ 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,
+ 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,
+ 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,
+ 128+128,128+128,128+128,128+128,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ } ,
+ #endif
+ #if 1
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1024,1024,1024,1024,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ #endif
+
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref = {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 26, 32, 26,
+ 32, 26, 32, 26
+ }, //total 44
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref = {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 1 //lpddr4
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 0, 1,
+ 0, 5, 0, 1, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0,
+ },
+ #endif
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 8,15,11,13,9,12,14,10,
+ 3,0,6,4,5,7,2,1,
+ 17,18,23,22,20,21,19,16,
+ 28,30,27,25,26,24,29,31,
+ 33,32,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af400 lpddr4
+
+#if 0//timing_config,af409 LPDDR4
+{
+ //af409
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0},
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ #if 0
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ },//total 36
+ #endif
+ #if 1
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 0,0,0,0,0,0,0,0,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,},
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,},
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,40,32,40,32,40,32,40} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 1 //lpddr4
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 0, 1,
+ 0, 5, 1, 2, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 8,15,11,13,9,12,14,10,
+ 3,0,6,4,5,7,2,1,
+ 17,18,23,22,20,21,19,16,
+ 28,30,27,25,26,24,29,31,
+ 33,32,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af409 LPDDR4
+
+#if 0 //timing_config,for dd3 pxp
+//ddr_set_t ddr_set_t_default=
+{
+ .cfg_board_common_setting. timming_magic = 0 ,
+ .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_version = 0 ,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_real_size = 0 , //0
+ .cfg_board_common_setting. fast_boot = {0} ,
+ .cfg_board_common_setting. ddr_func = 0 ,
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK ,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3 ,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 ,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 ,
+ .cfg_board_common_setting. dram_cs0_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs1_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB ,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB ,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 ,
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE ,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC ,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE ,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE ,
+ .cfg_board_common_setting. org_tdqs2dq = 0 ,
+ .cfg_board_common_setting. reserve1_test_function = {0} ,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT ,
+ #if 0
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ } ,
+
+ //ac_group0-ac_group1
+ #endif
+ #if 1
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ } ,
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0 ,
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 14,13,12,15,8,9,11,10,
+ 20,21,22,23,16,17,19,18,
+ 24,25,28,26,31,30,27,29,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,3,1,0,6,7,4,5,
+ 11,10,9,8,15,14,13,12,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ //1,0,3,2,5,4,7,6,
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,7,1,5,3,6,0,4,
+ 10,11,15,13,14,9,8,12,
+ 24,29,26,31,25,28,27,30,
+ 23,18,21,19,22,17,20,16,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35,
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ .cfg_board_common_setting. ddr_vddee_setting = {0} ,
+
+
+ .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[0]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #if 0
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 123,124,0,126,127,0,0,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,} ,
+ #endif
+ #if 0 //real board
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,} ,
+
+
+ #endif
+
+ #if 1 //for pxp
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} ,
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {128+512,128+512,128+512,128+512,128+512,128+512,128+512,128+512} , //total 8
+
+ #else
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} ,
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1094,1094,1094,1094,1094,1094,1094,1094} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896,896,896,896,896,896,896,896} , //total 8
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,
+ 42,42,42,42,42,42,42,42,42,42,
+ 42,42,42,42,42,58,42,58,42,58,42,58,} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+
+ .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[1]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #if 0
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ } , //total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64} ,
+ //total 72
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40} , //total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} ,
+},
+#endif //end for dd3 pxp
+
+#if 0 //timing_config,for ddr4 pxp remap
+//ddr_set_t ddr_set_t_default=
+{
+ .cfg_board_common_setting. timming_magic = 0 ,
+ .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_version = 0 ,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_real_size = 0 , //0
+ .cfg_board_common_setting. fast_boot = {0} ,
+ .cfg_board_common_setting. ddr_func = 0 ,
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK ,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4 ,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0 ,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 ,
+ .cfg_board_common_setting. dram_cs0_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs1_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB ,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB ,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 ,
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE ,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC ,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE ,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE ,
+ .cfg_board_common_setting. org_tdqs2dq = 0 ,
+ .cfg_board_common_setting. reserve1_test_function = {0} ,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT ,
+ #if 1 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 0
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ } ,
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0 ,
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 14,13,12,15,8,9,11,10,
+ 20,21,22,23,16,17,19,18,
+ 24,25,28,26,31,30,27,29,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,3,1,0,6,7,4,5,
+ 11,10,9,8,15,14,13,12,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ //1,0,3,2,5,4,7,6,
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,7,1,5,3,6,0,4,
+ 10,11,15,13,14,9,8,12,
+ 24,29,26,31,25,28,27,30,
+ 23,18,21,19,22,17,20,16,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ .cfg_board_common_setting. ddr_vddee_setting = {0} ,
+
+
+ .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM , //for pxp dram weak driver model
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[0]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #if 0
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ } , //total 36
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64} ,
+ //total 72
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {0,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,50,40,50,40,50,40,50} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {0,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[1]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #if 0
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ } , //total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64} ,
+ //total 72
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40} , //total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} ,
+},
+#endif //end for ddr4 pxp remap
+};
+//ddr timing end
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = AML_CUSTOMER_ID,
+ .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */
+ .log_ctrl = (1<<7) | /* (1<<7), print bl2 log into buffer */
+#ifdef CONFIG_SILENT_CONSOLE
+ (1<<6), /* do not print log buffer */
+#else
+ (0<<6), /* print log buffer before run bl31 */
+#endif
+.ddr_timming_save_mode = 1,
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/
+#if (VDDEE_VAL == 711)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 721)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 731)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 741)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 751)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 761)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 771)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 781)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 791)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 801)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 811)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 821)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 831)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 841)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 851)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 861)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 871)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 881)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 891)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/*
+ * GPIOE_0 PWM_A VDDEE_PWM
+ *
+ * GPIOE_1 PWM_B VCCK_PWM
+ */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400)
+
+/* pwm clock and pwm controller */
+#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800)
+#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400)
+#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400)
+#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400)
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ {0, 0, 0xffffffff, 0, 0, 0},
+ {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0},
+ /* enable vddcpu dc-dc, set GPIOD_10 high */
+ {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ /* set pwm A and pwm B clock rate to 24M, enable them */
+ {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3*/
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/c2_af409/Kconfig b/board/amlogic/c2_af409/Kconfig
new file mode 100644
index 0000000..b4c91c2
--- /dev/null
+++ b/board/amlogic/c2_af409/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_C2_AF409
+
+config SYS_SOC
+ default "c2"
+
+config SYS_BOARD
+ default "c2_af409"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "c2_af409"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default y
+ help
+ support plltest command
+
+endif
diff --git a/board/amlogic/c2_af409/Makefile b/board/amlogic/c2_af409/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/c2_af409/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_af409/aml-key/bl2aesiv b/board/amlogic/c2_af409/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c2_af409/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/c2_af409/aml-key/bl2aeskey b/board/amlogic/c2_af409/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c2_af409/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/c2_af409/aml-key/bl3xaesiv b/board/amlogic/c2_af409/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c2_af409/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/c2_af409/aml-key/bl3xaeskey b/board/amlogic/c2_af409/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c2_af409/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/c2_af409/aml-key/kernelaesiv b/board/amlogic/c2_af409/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c2_af409/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/c2_af409/aml-key/kernelaeskey b/board/amlogic/c2_af409/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c2_af409/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/c2_af409/aml-user-key.sig b/board/amlogic/c2_af409/aml-user-key.sig
new file mode 100755
index 0000000..088d1cf
--- /dev/null
+++ b/board/amlogic/c2_af409/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/c2_af409/c2_af409.c b/board/amlogic/c2_af409/c2_af409.c
new file mode 100644
index 0000000..6f4538b
--- /dev/null
+++ b/board/amlogic/c2_af409/c2_af409.c
@@ -0,0 +1,352 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+unsigned int get_dram_size(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+}
+
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = 0;
+ gd->bd->bi_dram[0].size = get_dram_size();
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ struct udevice *i2c = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ /*active gpio i2c */
+ err = uclass_get_device_by_name(UCLASS_I2C,
+ "i2c-gpio-0", &i2c);
+ if (err) {
+ pr_err("Can't find i2c-gpio-0 (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+void board_init_mem(void) {
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+}
+
+/* set dts props */
+void aml_config_dtb(void)
+{
+ cpu_id_t cpuid = get_cpu_id();
+ if (MESON_CPU_MAJOR_ID_C2 != cpuid.family_id)
+ return;
+
+ run_command("fdt address $dtb_mem_addr", 0);
+ printf("%s %d\n", __func__, __LINE__);
+ if (cpuid.chip_rev == 0xA) {
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt rm /soc/emmc mmc-hs400-1_8v", 0);
+ run_command("fdt rm /soc/emmc fixed-emmc-driver-type", 0);
+ run_command("fdt print /soc/emmc", 0);
+ } else {
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt set /soc/bus/pinctrl/emmc/mux drive-strength <4>", 0);
+ run_command("fdt set /soc/bus/pinctrl/emmc/mux1 drive-strength <4>", 0);
+ run_command("fdt set /soc/bus/pinctrl/emmc_clk_gate/mux drive-strength <4>", 0);
+ run_command("fdt print /soc/bus/pinctrl/emmc", 0);
+ run_command("fdt print /soc/bus/pinctrl/emmc_clk_gate", 0);
+ }
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ active_clk();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ aml_config_dtb();
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+#ifdef UBOOT_RUN_IN_SRAM
+ return 0x180000; /* SRAM 1.5MB */
+#else
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+#endif /* UBOOT_RUN_IN_SRAM */
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/*
+* mtd nand partition table, only care the size!
+* offset will be calculated by nand driver.
+*/
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+/* MUST NOT CHANGE this part unless u know what you are doing!
+* inherent parition for descrete bootloader to store fip
+* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+* name must be same with TPL_PART_NAME
+*/
+{
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 32*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 32*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 304*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "misc",
+ .offset = 0,
+ .size = 8 * SZ_8K,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_af409/firmware/timing.c b/board/amlogic/c2_af409/firmware/timing.c
new file mode 100644
index 0000000..6064ceb
--- /dev/null
+++ b/board/amlogic/c2_af409/firmware/timing.c
@@ -0,0 +1,3591 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+#define TIMMING_MAX_CONFIG 1
+
+//#define T406_LPDDR4 1
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = {
+#if 0//timing_config,af400
+{
+ //af400
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-20,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay = {
+ 128,128,128-20,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,},
+ #endif
+ #if 0
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,50,40,50,40,50,40,50},//total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {
+ (0 << 7) | 6, (0 << 7) | 16, (0 << 7) | 10, (0 << 7) | 3,
+ (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0,
+ (0 << 7) | 2, (0 << 7) | 4, (0 << 7) | 4, (0 << 7) | 10,
+ (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0,
+ },
+
+ //pinmux setting
+ #if 1 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af400
+
+#if 1 //timing_config,af409
+{
+
+ //af409
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,90,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay = {
+ 128,128,90,128,128,128,128,256,
+ 256,256,256,256,256,256,256,256,
+ 256,256,256,256,256,256,256,256,
+ 256,256,256,256,256,256,256,256,
+ 256,256,256,256,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,},
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {266,266,266,266,0+300-128,0+300-128,0+300-128,0+300-128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,},
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,50,40,50,40,50,40,50} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 1 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af409
+
+#if 0//timing_config,af419
+{
+ //af419
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-40,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay = {
+ 128,128,128-40,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,},
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000154,// 340
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x0000014f,// 335
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000013b,// 315
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000159,// 345
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000019e,// 414
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000189,// 393
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000183,// 387
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001a6,// 422
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001ab,// 427
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000192,// 402
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000018d,// 397
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x00000192,// 402
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x00000196,// 406
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000180,// 384
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000180,// 384
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000173,// 371
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000018e,// 398
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x00000186,// 390
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000179,// 377
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x00000184,// 388
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x00000180,// 384
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x0000017d,// 381
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000016d,// 365
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x0000018c,// 396
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x0000017e,// 382
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x0000018f,// 399
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x00000183,// 387
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x0000018d,// 397
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x0000017e,// 382
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x00000197,// 407
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000018e,// 398
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000199,// 409
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000181,// 385
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000017b,// 379
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000018f,// 399
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000189,// 393
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 1 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af419
+
+#if 0//timing_config,real DDR3
+{
+ //real DDR3
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,CONFIG_DDR0_SIZE_768MB
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT,
+ .cfg_board_common_setting. fast_boot = {0},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 912,//1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-20,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128-20,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,},
+ #endif
+ #if 0
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896-128,896-128,896-128,896-128,896-128,896-128,896-128,896-128} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000007d,// 125
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000091,// 145
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000091,// 145
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x0000009b,// 155
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000000c2,// 194
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000000b0,// 176
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000000b0,// 176
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000c0,// 192
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000c3,// 195
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b4,// 180
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000be,// 190
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ba,// 186
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d5,// 213
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d0,// 208
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000cc,// 204
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000c3,// 195
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000be,// 190
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000c0,// 192
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000c8,// 200
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000e0,// 224
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000e5,// 229
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000e2,// 226
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000ec,// 236
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000ec,// 236
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000e7,// 231
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000e4,// 228
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000e9,// 233
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000e6,// 230
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000eb,// 235
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000f5,// 245
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000e7,// 231
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000fd,// 253
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000e8,// 232
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000e4,// 228
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ee,// 238
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ec,// 236
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000f2,// 242
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000038c,// 908
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000037a,// 890
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x0000039a,// 922
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000395,// 917
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007f-0x30,// 127
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000007d-0x30,// 125
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x0000006d-0x30,// 109
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000006f-0x30,// 111
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000048-0x30,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000044-0x30,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000038-0x30,// 56
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x0000003b-0x30,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000049-0x30,// 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x0000004b-0x30,// 75
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003b-0x30,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000049-0x30,// 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000040-0x30,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000052-0x30,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000039-0x30,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000040-0x30,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000045-0x30,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042-0x30,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000034-0x30,// 52
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000003c-0x30,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000086-0x30,// 134
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000003f-0x30,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000048-0x30,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000037-0x30,// 55
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000048-0x30,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=(0x0000004e)-0x30,// 78
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000044-0x30,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000042-0x30,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000047-0x30,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x0000007f-0x30,// 127
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000040-0x30,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000052-0x30,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d-0x30,// 61
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=(0x0000004e)-0x30,// 78
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003c-0x30,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=(0x0000003e)-0x30,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000003f-0x30,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x0000004c-0x30,// 76
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000091-0x30,// 145
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32+5,32,32+5,32,32+5,32,32+5,},//total 44
+
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter = {DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR3,} ,
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 1 //real DDR3
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end real DDR3
+
+#if 0//timing_config,af400 LPDDR4
+{
+ //af400
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,//DDR_WRITE_READ_DBI_DISABLE,DDR_READ_DBI_ENABLE
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_DDR3_32BIT
+ .cfg_board_common_setting. fast_boot = {0},
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 667,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_80_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_80_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 300,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 330,//330
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1//default cs cke 0 ,other AC=128
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,0,0, //0,0,0,0,0,0,0,0,
+ 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,
+ 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,
+ 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,
+ 128+128,128+128,128+128,128+128,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ } ,
+ #endif
+ #if 1
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1024,1024,1024,1024,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ #endif
+
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,26,32,26,32,26,32,26} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 1 //lpddr4
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 0, 1,
+ 0, 5, 0, 1, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0,
+ },
+ #endif
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 8,15,11,13,9,12,14,10,
+ 3,0,6,4,5,7,2,1,
+ 17,18,23,22,20,21,19,16,
+ 28,30,27,25,26,24,29,31,
+ 33,32,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af400 lpddr4
+
+#if 0//timing_config,af409 LPDDR4
+{
+ //af409
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0},
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ #if 0
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ },//total 36
+ #endif
+ #if 1
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 0,0,0,0,0,0,0,0,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,},
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,},
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,40,32,40,32,40,32,40} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 1 //lpddr4
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 0, 1,
+ 0, 5, 1, 2, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 8,15,11,13,9,12,14,10,
+ 3,0,6,4,5,7,2,1,
+ 17,18,23,22,20,21,19,16,
+ 28,30,27,25,26,24,29,31,
+ 33,32,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af409 LPDDR4
+
+#if 0 //timing_config,for dd3 pxp
+//ddr_set_t ddr_set_t_default=
+{
+ .cfg_board_common_setting. timming_magic = 0 ,
+ .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_version = 0 ,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_real_size = 0 , //0
+ .cfg_board_common_setting. fast_boot = {0} ,
+ .cfg_board_common_setting. ddr_func = 0 ,
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK ,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3 ,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 ,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 ,
+ .cfg_board_common_setting. dram_cs0_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs1_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB ,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB ,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 ,
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE ,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC ,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE ,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE ,
+ .cfg_board_common_setting. org_tdqs2dq = 0 ,
+ .cfg_board_common_setting. reserve1_test_function = {0} ,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT ,
+ #if 0
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ } ,
+
+ //ac_group0-ac_group1
+ #endif
+ #if 1
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ } ,
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0 ,
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 14,13,12,15,8,9,11,10,
+ 20,21,22,23,16,17,19,18,
+ 24,25,28,26,31,30,27,29,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,3,1,0,6,7,4,5,
+ 11,10,9,8,15,14,13,12,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ //1,0,3,2,5,4,7,6,
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,7,1,5,3,6,0,4,
+ 10,11,15,13,14,9,8,12,
+ 24,29,26,31,25,28,27,30,
+ 23,18,21,19,22,17,20,16,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35,
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ .cfg_board_common_setting. ddr_vddee_setting = {0} ,
+
+
+ .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[0]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #if 0
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 123,124,0,126,127,0,0,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,} ,
+ #endif
+ #if 0 //real board
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,} ,
+
+
+ #endif
+
+ #if 1 //for pxp
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} ,
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {128+512,128+512,128+512,128+512,128+512,128+512,128+512,128+512} , //total 8
+
+ #else
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} ,
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1094,1094,1094,1094,1094,1094,1094,1094} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896,896,896,896,896,896,896,896} , //total 8
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,
+ 42,42,42,42,42,42,42,42,42,42,
+ 42,42,42,42,42,58,42,58,42,58,42,58,} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+
+ .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[1]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #if 0
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ } , //total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64} ,
+ //total 72
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40} , //total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} ,
+},
+#endif //end for dd3 pxp
+
+#if 0 //timing_config,for ddr4 pxp remap
+//ddr_set_t ddr_set_t_default=
+{
+ .cfg_board_common_setting. timming_magic = 0 ,
+ .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_version = 0 ,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_real_size = 0 , //0
+ .cfg_board_common_setting. fast_boot = {0} ,
+ .cfg_board_common_setting. ddr_func = 0 ,
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK ,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4 ,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0 ,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 ,
+ .cfg_board_common_setting. dram_cs0_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs1_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB ,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB ,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 ,
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE ,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC ,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE ,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE ,
+ .cfg_board_common_setting. org_tdqs2dq = 0 ,
+ .cfg_board_common_setting. reserve1_test_function = {0} ,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT ,
+ #if 1 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 0
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ } ,
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0 ,
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 14,13,12,15,8,9,11,10,
+ 20,21,22,23,16,17,19,18,
+ 24,25,28,26,31,30,27,29,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,3,1,0,6,7,4,5,
+ 11,10,9,8,15,14,13,12,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ //1,0,3,2,5,4,7,6,
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,7,1,5,3,6,0,4,
+ 10,11,15,13,14,9,8,12,
+ 24,29,26,31,25,28,27,30,
+ 23,18,21,19,22,17,20,16,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ .cfg_board_common_setting. ddr_vddee_setting = {0} ,
+
+
+ .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM , //for pxp dram weak driver model
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[0]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #if 0
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ } , //total 36
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64} ,
+ //total 72
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {0,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,50,40,50,40,50,40,50} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {0,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[1]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #if 0
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ } , //total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64} ,
+ //total 72
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40} , //total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} ,
+},
+#endif //end for ddr4 pxp remap
+
+
+#ifdef T406_LPDDR4 //timing_config,for T406 LPDDR4
+//ddr_set_t ddr_set_t_default=
+{
+//old fast_boot[0]=0x00000000,// 0
+.cfg_board_common_setting.fast_boot[0]=0x000000fd,// 253
+.cfg_board_common_setting.fast_boot[1]=0x00000000,// 0
+.cfg_board_common_setting.fast_boot[2]=0x00000000,// 0
+.cfg_board_common_setting.fast_boot[3]=0x00000000,// 0
+.cfg_board_common_setting.timming_magic=0x00000000,// 0
+.cfg_board_common_setting.timming_max_valid_configs=0x00000001,// 1
+.cfg_board_common_setting.timming_struct_version=0x00000000,// 0
+.cfg_board_common_setting.timming_struct_org_size=0x000004bc,// 1212
+.cfg_board_common_setting.timming_struct_real_size=0x00000000,// 0
+.cfg_board_common_setting.ddr_func=0x00000000,// 0
+.cfg_board_common_setting.board_id=0x000000ff,// 255
+.cfg_board_common_setting.DramType=0x00000002,// 2
+.cfg_board_common_setting.dram_rank_config=0x00000007,// 7
+.cfg_board_common_setting.DisabledDbyte=0x000000f0,// 240
+.cfg_board_common_setting.dram_cs0_base_add=0x00000000,// 0
+.cfg_board_common_setting.dram_cs1_base_add=0x00000000,// 0
+.cfg_board_common_setting.dram_cs0_size_MB=0x00000400,// 1024
+.cfg_board_common_setting.dram_cs1_size_MB=0x00000400,// 1024
+.cfg_board_common_setting.dram_x4x8x16_mode=0x00000000,// 0
+.cfg_board_common_setting.Is2Ttiming=0x00000000,// 0
+.cfg_board_common_setting.log_level=0x00000001,// 1
+.cfg_board_common_setting.ddr_rdbi_wr_enable=0x00000000,// 0
+.cfg_board_common_setting.pll_ssc_mode=0x00000000,// 0
+.cfg_board_common_setting.org_tdqs2dq=0x00000000,// 0
+.cfg_board_common_setting.reserve1_test_function[0]=0x00000000,// 0
+.cfg_board_common_setting.reserve1_test_function[1]=0x00000000,// 0
+.cfg_board_common_setting.ddr_dmc_remap[0]=0x14941cc5,// 345251013
+.cfg_board_common_setting.ddr_dmc_remap[1]=0x1ee6000b,// 518389771
+.cfg_board_common_setting.ddr_dmc_remap[2]=0x2f6ace51,// 795528785
+.cfg_board_common_setting.ddr_dmc_remap[3]=0x3bcdeb38,// 1003350840
+.cfg_board_common_setting.ddr_dmc_remap[4]=0x000a41be,// 672190
+.cfg_board_common_setting.ac_pinmux[0]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[1]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[2]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[3]=0x00000001,// 1
+.cfg_board_common_setting.ac_pinmux[4]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[5]=0x00000001,// 1
+.cfg_board_common_setting.ac_pinmux[6]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[7]=0x00000005,// 5
+.cfg_board_common_setting.ac_pinmux[8]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[9]=0x00000001,// 1
+.cfg_board_common_setting.ac_pinmux[10]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[11]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[12]=0x00000004,// 4
+.cfg_board_common_setting.ac_pinmux[13]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[14]=0x00000005,// 5
+.cfg_board_common_setting.ac_pinmux[15]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[16]=0x00000001,// 1
+.cfg_board_common_setting.ac_pinmux[17]=0x00000003,// 3
+.cfg_board_common_setting.ac_pinmux[18]=0x00000003,// 3
+.cfg_board_common_setting.ac_pinmux[19]=0x00000004,// 4
+.cfg_board_common_setting.ac_pinmux[20]=0x00000002,// 2
+.cfg_board_common_setting.ac_pinmux[21]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[22]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[23]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[24]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[25]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[26]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[27]=0x00000002,// 2
+.cfg_board_common_setting.ac_pinmux[28]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[29]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[30]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[31]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[32]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[33]=0x00000000,// 0
+.cfg_board_common_setting.ac_pinmux[34]=0x00000000,// 0
+.cfg_board_common_setting.ddr_dqs_swap=0x00000000,// 0
+.cfg_board_common_setting.ddr_dq_remap[0]=0x00000000,// 0
+.cfg_board_common_setting.ddr_dq_remap[1]=0x00000004,// 4
+.cfg_board_common_setting.ddr_dq_remap[2]=0x00000001,// 1
+.cfg_board_common_setting.ddr_dq_remap[3]=0x00000002,// 2
+.cfg_board_common_setting.ddr_dq_remap[4]=0x00000003,// 3
+.cfg_board_common_setting.ddr_dq_remap[5]=0x00000005,// 5
+.cfg_board_common_setting.ddr_dq_remap[6]=0x00000007,// 7
+.cfg_board_common_setting.ddr_dq_remap[7]=0x00000006,// 6
+.cfg_board_common_setting.ddr_dq_remap[8]=0x0000000c,// 12
+.cfg_board_common_setting.ddr_dq_remap[9]=0x0000000d,// 13
+.cfg_board_common_setting.ddr_dq_remap[10]=0x00000009,// 9
+.cfg_board_common_setting.ddr_dq_remap[11]=0x0000000b,// 11
+.cfg_board_common_setting.ddr_dq_remap[12]=0x00000008,// 8
+.cfg_board_common_setting.ddr_dq_remap[13]=0x0000000f,// 15
+.cfg_board_common_setting.ddr_dq_remap[14]=0x0000000e,// 14
+.cfg_board_common_setting.ddr_dq_remap[15]=0x0000000a,// 10
+.cfg_board_common_setting.ddr_dq_remap[16]=0x00000014,// 20
+.cfg_board_common_setting.ddr_dq_remap[17]=0x00000015,// 21
+.cfg_board_common_setting.ddr_dq_remap[18]=0x00000016,// 22
+.cfg_board_common_setting.ddr_dq_remap[19]=0x00000017,// 23
+.cfg_board_common_setting.ddr_dq_remap[20]=0x00000010,// 16
+.cfg_board_common_setting.ddr_dq_remap[21]=0x00000011,// 17
+.cfg_board_common_setting.ddr_dq_remap[22]=0x00000013,// 19
+.cfg_board_common_setting.ddr_dq_remap[23]=0x00000012,// 18
+.cfg_board_common_setting.ddr_dq_remap[24]=0x0000001f,// 31
+.cfg_board_common_setting.ddr_dq_remap[25]=0x0000001d,// 29
+.cfg_board_common_setting.ddr_dq_remap[26]=0x0000001e,// 30
+.cfg_board_common_setting.ddr_dq_remap[27]=0x0000001c,// 28
+.cfg_board_common_setting.ddr_dq_remap[28]=0x00000018,// 24
+.cfg_board_common_setting.ddr_dq_remap[29]=0x0000001a,// 26
+.cfg_board_common_setting.ddr_dq_remap[30]=0x0000001b,// 27
+.cfg_board_common_setting.ddr_dq_remap[31]=0x00000019,// 25
+.cfg_board_common_setting.ddr_dq_remap[32]=0x00000020,// 32
+.cfg_board_common_setting.ddr_dq_remap[33]=0x00000021,// 33
+.cfg_board_common_setting.ddr_dq_remap[34]=0x00000022,// 34
+.cfg_board_common_setting.ddr_dq_remap[35]=0x00000023,// 35
+.cfg_board_common_setting.ddr_vddee_setting[0]=0x00000000,// 0
+.cfg_board_common_setting.ddr_vddee_setting[1]=0x00000000,// 0
+.cfg_board_common_setting.ddr_vddee_setting[2]=0x00000000,// 0
+.cfg_board_common_setting.ddr_vddee_setting[3]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].DRAMFreq=0x00000528,// 1320
+.cfg_board_SI_setting_ps[0].PllBypassEn=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].training_SequenceCtrl=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ddr_odt_config=0x00000001,// 1
+.cfg_board_SI_setting_ps[0].clk_drv_ohm=0x00000028,// 40
+.cfg_board_SI_setting_ps[0].cs_drv_ohm=0x00000028,// 40
+.cfg_board_SI_setting_ps[0].ac_drv_ohm=0x00000028,// 40
+.cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p=0x00000028,// 40
+.cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n=0x00000028,// 40
+.cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n=0x00000050,// 80
+.cfg_board_SI_setting_ps[0].dram_data_drv_ohm=0x00000028,// 40
+.cfg_board_SI_setting_ps[0].dram_data_odt_ohm=0x00000050,// 80
+.cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].dram_ac_odt_ohm=0x00000078,// 120
+.cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm=0x00000028,// 40
+.cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting=0x00000001,// 1
+.cfg_board_SI_setting_ps[0].reserve2=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].vref_ac_permil =0x0000012c,// 300
+.cfg_board_SI_setting_ps[0].vref_soc_data_permil =0x000000a0,// 160
+.cfg_board_SI_setting_ps[0].vref_dram_data_permil=0x0000014a,// 330
+.cfg_board_SI_setting_ps[0].max_core_timmming_frequency=0x00000640,// 1600
+.cfg_board_SI_setting_ps[0].training_phase_parameter[0]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].training_phase_parameter[1]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[0]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[1]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[2]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[3]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[4]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[5]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[6]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[7]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[8]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[9]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[10]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[11]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[12]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[13]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[14]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[15]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[16]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[17]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[18]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[19]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[20]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[21]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[22]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[23]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[24]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[25]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[26]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[27]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[28]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[29]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[30]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[31]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[32]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[33]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[34]=0x00000000,// 0
+.cfg_board_SI_setting_ps[0].ac_trace_delay_org[35]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[0]=0x000000c0,// 192
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[1]=0x000000c0,// 192
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[2]=0x000000c0,// 192
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[3]=0x000000c0,// 192
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[4]=0x000000c0,// 192
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[5]=0x000000c0,// 192
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[6]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[7]=0x00000114,// 0
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[8]=0x00000114,// 276
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[9]=0x00000114,// 276
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[10]=0x0000013c,// 316
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[11]=0x00000114,// 276
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[12]=0x00000100,// 256
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[13]=0x00000100,// 256
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[14]=0x00000100,// 256
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[15]=0x00000100,// 256
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[16]=0x00000100,// 256
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[17]=0x00000100,// 256
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[18]=0x00000100,// 256
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[19]=0x00000100,// 256
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[20]=0x00000100,// 256
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[21]=0x00000100,// 256
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[22]=0x00000100,// 256
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[23]=0x00000100,// 256
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[24]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[25]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[26]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[27]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[28]=0x00000100,// 256
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[29]=0x00000100,// 256
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[30]=0x00000100,// 256
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[31]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[32]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[33]=0x00000100,// 256
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[34]=0x00000100,// 256
+.cfg_ddr_training_delay_ps[0].ac_trace_delay[35]=0x00000100,// 256
+.cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000007d,// 125
+.cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000069,// 105
+.cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000087,// 135
+.cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000073,// 115
+.cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x0000007d,// 125
+.cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000069,// 105
+.cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000087,// 135
+.cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000073,// 115
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x00000163,// 355
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000161,// 353
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x0000015c,// 348
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000016a,// 362
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x00000170,// 368
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000173,// 371
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x00000161,// 353
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x0000016d,// 365
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x00000167,// 359
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000152,// 338
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000159,// 345
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000150,// 336
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x00000156,// 342
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000015c,// 348
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x00000158,// 344
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000159,// 345
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x0000015a,// 346
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x00000156,// 342
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x0000016b,// 363
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x00000174,// 372
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x00000166,// 358
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x00000175,// 373
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x00000173,// 371
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x00000175,// 373
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x0000016c,// 364
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x00000173,// 371
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x0000016e,// 366
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x00000165,// 357
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x00000170,// 368
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x00000160,// 352
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000176,// 374
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000164,// 356
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x00000164,// 356
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x00000163,// 355
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x00000161,// 353
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x0000016b,// 363
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000163,// 355
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000161,// 353
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x0000015c,// 348
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x0000016a,// 362
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000170,// 368
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000173,// 371
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000161,// 353
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x0000016d,// 365
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000167,// 359
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000152,// 338
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000159,// 345
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000150,// 336
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000156,// 342
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x0000015c,// 348
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000158,// 344
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000159,// 345
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x0000015a,// 346
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000156,// 342
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x0000016b,// 363
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000174,// 372
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000166,// 358
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000175,// 373
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000173,// 371
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000175,// 373
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x0000016c,// 364
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000173,// 371
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x0000016e,// 366
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000165,// 357
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000170,// 368
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000160,// 352
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000176,// 374
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000164,// 356
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000164,// 356
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000163,// 355
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000161,// 353
+.cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x0000016b,// 363
+.cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x000002fd,// 765
+.cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000030f,// 783
+.cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x000002f1,// 753
+.cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x000002fa,// 762
+.cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x000002fd,// 765
+.cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x0000030f,// 783
+.cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x000002f1,// 753
+.cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x000002fa,// 762
+.cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117
+.cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108
+.cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x0000006c,// 108
+.cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x00000070,// 112
+.cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000075,// 117
+.cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x0000006c,// 108
+.cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x0000006c,// 108
+.cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000070,// 112
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000036,// 54
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003f,// 63
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000034,// 52
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000038,// 56
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000044,// 68
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000045,// 69
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000034,// 52
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000042,// 66
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x0000003c,// 60
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000033,// 51
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000033,// 51
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000031,// 49
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000031,// 49
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000037,// 55
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000033,// 51
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x00000039,// 57
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000033,// 51
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000034,// 52
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000040,// 64
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000037,// 55
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x0000003f,// 63
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000040,// 64
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000035,// 53
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000042,// 66
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x0000003a,// 58
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000038,// 56
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000046,// 70
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000039,// 57
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x0000003b,// 59
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000038,// 56
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000038,// 56
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000038,// 56
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000036,// 54
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x0000003f,// 63
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000034,// 52
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000038,// 56
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000044,// 68
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000045,// 69
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000034,// 52
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000042,// 66
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x0000003c,// 60
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000033,// 51
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000033,// 51
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000031,// 49
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000031,// 49
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000037,// 55
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000033,// 51
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000039,// 57
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000033,// 51
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000034,// 52
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000040,// 64
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000037,// 55
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x0000003f,// 63
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000040,// 64
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000035,// 53
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000042,// 66
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x0000003a,// 58
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000038,// 56
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000046,// 70
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000039,// 57
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x0000003b,// 59
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000038,// 56
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000031,// 49
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000038,// 56
+.cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000038,// 56
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[0]=0x00000017,// 23
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[1]=0x00000016,// 22
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[2]=0x00000018,// 24
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[3]=0x00000017,// 23
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[4]=0x00000016,// 22
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[5]=0x00000017,// 23
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[6]=0x00000016,// 22
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[7]=0x00000017,// 23
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[8]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[9]=0x00000018,// 24
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[10]=0x00000017,// 23
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[11]=0x00000015,// 21
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[12]=0x00000015,// 21
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[13]=0x00000017,// 23
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[14]=0x00000015,// 21
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[15]=0x00000018,// 24
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[16]=0x00000017,// 23
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[17]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[18]=0x00000017,// 23
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[19]=0x00000018,// 24
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[20]=0x00000018,// 24
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[21]=0x00000018,// 24
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[22]=0x00000017,// 23
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[23]=0x00000017,// 23
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[24]=0x00000018,// 24
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[25]=0x00000017,// 23
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[26]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[27]=0x00000018,// 24
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[28]=0x00000015,// 21
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[29]=0x00000017,// 23
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[30]=0x00000017,// 23
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[31]=0x00000017,// 23
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[32]=0x00000018,// 24
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[33]=0x00000018,// 24
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[34]=0x00000018,// 24
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[35]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[36]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[37]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[38]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[39]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[40]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[41]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[42]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[0].soc_bit_vref[43]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[0]=0x00000050,// 80
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[1]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[2]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[3]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[4]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[5]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[6]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[7]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[8]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[9]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[10]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[11]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[12]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[13]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[14]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[15]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[16]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[17]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[18]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[19]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[20]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[21]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[22]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[23]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[24]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[25]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[26]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[27]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[28]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[29]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[30]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[31]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[32]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[33]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[34]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].dram_bit_vref[35]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].reserve_training_parameter[0]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].reserve_training_parameter[1]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].reserve_training_parameter[2]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].reserve_training_parameter[3]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].reserve_training_parameter[4]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].reserve_training_parameter[5]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].reserve_training_parameter[6]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[0].reserve_training_parameter[7]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].DRAMFreq=0x0000029b,// 667
+.cfg_board_SI_setting_ps[1].PllBypassEn=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].training_SequenceCtrl=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ddr_odt_config=0x00000001,// 1
+.cfg_board_SI_setting_ps[1].clk_drv_ohm=0x00000028,// 40
+.cfg_board_SI_setting_ps[1].cs_drv_ohm=0x00000028,// 40
+.cfg_board_SI_setting_ps[1].ac_drv_ohm=0x00000028,// 40
+.cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p=0x00000028,// 40
+.cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n=0x00000028,// 40
+.cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p=0x0000003c,// 60
+.cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].dram_data_drv_ohm=0x00000022,// 34
+.cfg_board_SI_setting_ps[1].dram_data_odt_ohm=0x0000003c,// 60
+.cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].dram_ac_odt_ohm=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm=0x00000028,// 40
+.cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting=0x00000001,// 1
+.cfg_board_SI_setting_ps[1].reserve2=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].vref_ac_permil =0x00000000,// 0
+.cfg_board_SI_setting_ps[1].vref_soc_data_permil =0x000000a0,// 160
+.cfg_board_SI_setting_ps[1].vref_dram_data_permil=0x0000012c,// 300
+.cfg_board_SI_setting_ps[1].max_core_timmming_frequency=0x00000640,// 1600
+.cfg_board_SI_setting_ps[1].training_phase_parameter[0]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].training_phase_parameter[1]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[0]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[1]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[2]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[3]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[4]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[5]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[6]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[7]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[8]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[9]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[10]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[11]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[12]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[13]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[14]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[15]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[16]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[17]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[18]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[19]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[20]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[21]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[22]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[23]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[24]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[25]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[26]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[27]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[28]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[29]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[30]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[31]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[32]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[33]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[34]=0x00000000,// 0
+.cfg_board_SI_setting_ps[1].ac_trace_delay_org[35]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[0]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[1]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[2]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[3]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[4]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[5]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[6]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[7]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[8]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[9]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[10]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[11]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[12]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[13]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[14]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[15]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[16]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[17]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[18]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[19]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[20]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[21]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[22]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[23]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[24]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[25]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[26]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[27]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[28]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[29]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[30]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[31]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[32]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[33]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[34]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].ac_trace_delay[35]=0x00000080,// 128
+.cfg_ddr_training_delay_ps[1].write_dqs_delay[0]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].write_dqs_delay[1]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].write_dqs_delay[2]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].write_dqs_delay[3]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].write_dqs_delay[4]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].write_dqs_delay[5]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].write_dqs_delay[6]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].write_dqs_delay[7]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[0]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[1]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[2]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[3]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[4]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[5]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[6]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[7]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[8]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[9]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[10]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[11]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[12]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[13]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[14]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[15]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[16]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[17]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[18]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[19]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[20]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[21]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[22]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[23]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[24]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[25]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[26]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[27]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[28]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[29]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[30]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[31]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[32]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[33]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[34]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[35]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[36]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[37]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[38]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[39]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[40]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[41]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[42]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[43]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[44]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[45]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[46]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[47]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[48]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[49]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[50]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[51]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[52]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[53]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[54]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[55]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[56]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[57]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[58]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[59]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[60]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[61]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[62]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[63]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[64]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[65]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[66]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[67]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[68]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[69]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[70]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].write_dq_bit_delay[71]=0x00000032,// 50
+.cfg_ddr_training_delay_ps[1].read_dqs_gate_delay[0]=0x000000c0,// 192
+.cfg_ddr_training_delay_ps[1].read_dqs_gate_delay[1]=0x000000c0,// 192
+.cfg_ddr_training_delay_ps[1].read_dqs_gate_delay[2]=0x000000c0,// 192
+.cfg_ddr_training_delay_ps[1].read_dqs_gate_delay[3]=0x000000c0,// 192
+.cfg_ddr_training_delay_ps[1].read_dqs_gate_delay[4]=0x000000c0,// 192
+.cfg_ddr_training_delay_ps[1].read_dqs_gate_delay[5]=0x000000c0,// 192
+.cfg_ddr_training_delay_ps[1].read_dqs_gate_delay[6]=0x000000c0,// 192
+.cfg_ddr_training_delay_ps[1].read_dqs_gate_delay[7]=0x000000c0,// 192
+.cfg_ddr_training_delay_ps[1].read_dqs_delay[0]=0x00000040,// 64
+.cfg_ddr_training_delay_ps[1].read_dqs_delay[1]=0x00000040,// 64
+.cfg_ddr_training_delay_ps[1].read_dqs_delay[2]=0x00000040,// 64
+.cfg_ddr_training_delay_ps[1].read_dqs_delay[3]=0x00000040,// 64
+.cfg_ddr_training_delay_ps[1].read_dqs_delay[4]=0x00000040,// 64
+.cfg_ddr_training_delay_ps[1].read_dqs_delay[5]=0x00000040,// 64
+.cfg_ddr_training_delay_ps[1].read_dqs_delay[6]=0x00000040,// 64
+.cfg_ddr_training_delay_ps[1].read_dqs_delay[7]=0x00000040,// 64
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[0]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[1]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[2]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[3]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[4]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[5]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[6]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[7]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[8]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[9]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[10]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[11]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[12]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[13]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[14]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[15]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[16]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[17]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[18]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[19]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[20]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[21]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[22]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[23]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[24]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[25]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[26]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[27]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[28]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[29]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[30]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[31]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[32]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[33]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[34]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[35]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[36]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[37]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[38]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[39]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[40]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[41]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[42]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[43]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[44]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[45]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[46]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[47]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[48]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[49]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[50]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[51]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[52]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[53]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[54]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[55]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[56]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[57]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[58]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[59]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[60]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[61]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[62]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[63]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[64]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[65]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[66]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[67]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[68]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[69]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[70]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].read_dq_bit_delay[71]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[0]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[1]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[2]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[3]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[4]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[5]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[6]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[7]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[8]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[9]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[10]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[11]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[12]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[13]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[14]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[15]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[16]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[17]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[18]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[19]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[20]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[21]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[22]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[23]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[24]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[25]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[26]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[27]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[28]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[29]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[30]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[31]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[32]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[33]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[34]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[35]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[36]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[37]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[38]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[39]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[40]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[41]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[42]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].soc_bit_vref[43]=0x00000010,// 16
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[0]=0x00000050,// 80
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[1]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[2]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[3]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[4]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[5]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[6]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[7]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[8]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[9]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[10]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[11]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[12]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[13]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[14]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[15]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[16]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[17]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[18]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[19]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[20]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[21]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[22]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[23]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[24]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[25]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[26]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[27]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[28]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[29]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[30]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[31]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[32]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[33]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[34]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].dram_bit_vref[35]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].reserve_training_parameter[0]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].reserve_training_parameter[1]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].reserve_training_parameter[2]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].reserve_training_parameter[3]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].reserve_training_parameter[4]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].reserve_training_parameter[5]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].reserve_training_parameter[6]=0x00000000,// 0
+.cfg_ddr_training_delay_ps[1].reserve_training_parameter[7]=0x00000000,// 0
+},
+#endif
+};
+
+//ddr timing end
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = AML_CUSTOMER_ID,
+ .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */
+ .log_ctrl = (1<<7) | /* (1<<7), print bl2 log into buffer */
+#ifdef CONFIG_SILENT_CONSOLE
+ (1<<6), /* do not print log buffer */
+#else
+ (0<<6), /* print log buffer before run bl31 */
+#endif
+.ddr_timming_save_mode = 1,
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/
+#if (VDDEE_VAL == 711)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 721)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 731)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 741)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 751)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 761)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 771)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 781)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 791)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 801)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 811)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 821)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 831)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 841)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 851)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 861)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 871)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 881)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 891)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/*
+ * GPIOE_0 PWM_A VDDEE_PWM
+ *
+ * GPIOE_1 PWM_B VCCK_PWM
+ */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400)
+
+/* pwm clock and pwm controller */
+#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800)
+#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400)
+#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400)
+#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400)
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ {0, 0, 0xffffffff, 0, 0, 0},
+ {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0},
+ /* enable vddcpu dc-dc, set GPIOD_10 high */
+ {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ /* set pwm A and pwm B clock rate to 24M, enable them */
+ {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3*/
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/c2_af419/Kconfig b/board/amlogic/c2_af419/Kconfig
new file mode 100644
index 0000000..99396e9
--- /dev/null
+++ b/board/amlogic/c2_af419/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_C2_AF419
+
+config SYS_SOC
+ default "c2"
+
+config SYS_BOARD
+ default "c2_af419"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "c2_af419"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default y
+ help
+ support plltest command
+
+endif
diff --git a/board/amlogic/c2_af419/Makefile b/board/amlogic/c2_af419/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/c2_af419/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_af419/aml-key/bl2aesiv b/board/amlogic/c2_af419/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c2_af419/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/c2_af419/aml-key/bl2aeskey b/board/amlogic/c2_af419/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c2_af419/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/c2_af419/aml-key/bl3xaesiv b/board/amlogic/c2_af419/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c2_af419/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/c2_af419/aml-key/bl3xaeskey b/board/amlogic/c2_af419/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c2_af419/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/c2_af419/aml-key/kernelaesiv b/board/amlogic/c2_af419/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c2_af419/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/c2_af419/aml-key/kernelaeskey b/board/amlogic/c2_af419/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c2_af419/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/c2_af419/aml-user-key.sig b/board/amlogic/c2_af419/aml-user-key.sig
new file mode 100644
index 0000000..088d1cf
--- /dev/null
+++ b/board/amlogic/c2_af419/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/c2_af419/c2_af419.c b/board/amlogic/c2_af419/c2_af419.c
new file mode 100644
index 0000000..49b7edf
--- /dev/null
+++ b/board/amlogic/c2_af419/c2_af419.c
@@ -0,0 +1,343 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+unsigned int get_dram_size(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+}
+
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = 0;
+ gd->bd->bi_dram[0].size = get_dram_size();
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+void board_init_mem(void) {
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+}
+
+/* set dts props */
+void aml_config_dtb(void)
+{
+ cpu_id_t cpuid = get_cpu_id();
+ if (MESON_CPU_MAJOR_ID_C2 != cpuid.family_id)
+ return;
+
+ run_command("fdt address $dtb_mem_addr", 0);
+ printf("%s %d\n", __func__, __LINE__);
+ if (cpuid.chip_rev == 0xA) {
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt rm /soc/emmc mmc-hs400-1_8v", 0);
+ run_command("fdt rm /soc/emmc fixed-emmc-driver-type", 0);
+ run_command("fdt print /soc/emmc", 0);
+ } else {
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt set /soc/bus/pinctrl/emmc/mux drive-strength <4>", 0);
+ run_command("fdt set /soc/bus/pinctrl/emmc/mux1 drive-strength <4>", 0);
+ run_command("fdt set /soc/bus/pinctrl/emmc_clk_gate/mux drive-strength <4>", 0);
+ run_command("fdt print /soc/bus/pinctrl/emmc", 0);
+ run_command("fdt print /soc/bus/pinctrl/emmc_clk_gate", 0);
+ }
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ active_clk();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ aml_config_dtb();
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+#ifdef UBOOT_RUN_IN_SRAM
+ return 0x180000; /* SRAM 1.5MB */
+#else
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+#endif /* UBOOT_RUN_IN_SRAM */
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/*
+* mtd nand partition table, only care the size!
+* offset will be calculated by nand driver.
+*/
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+/* MUST NOT CHANGE this part unless u know what you are doing!
+* inherent parition for descrete bootloader to store fip
+* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+* name must be same with TPL_PART_NAME
+*/
+{
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 32*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 32*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 304*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "misc",
+ .offset = 0,
+ .size = 8 * SZ_8K,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_af419/firmware/timing.c b/board/amlogic/c2_af419/firmware/timing.c
new file mode 100644
index 0000000..e286d13
--- /dev/null
+++ b/board/amlogic/c2_af419/firmware/timing.c
@@ -0,0 +1,2769 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+#define TIMMING_MAX_CONFIG 1
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = {
+#if 0//timing_config,af400
+{
+ //af400
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-20,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128-20,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,},
+ #endif
+ #if 0
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,50,40,50,40,50,40,50},//total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {
+ (0 << 7) | 6, (0 << 7) | 16, (0 << 7) | 10, (0 << 7) | 3,
+ (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0,
+ (0 << 7) | 2, (0 << 7) | 4, (0 << 7) | 4, (0 << 7) | 10,
+ (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0,
+ },
+
+ //pinmux setting
+ #if 1 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af400
+
+#if 0//timing_config,af409
+{
+ //af409
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,90,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,90,128,128,128,128,384,
+ 256,256,256,256,256,256,256,256,
+ 256,256,256,256,256,256,256,256,
+ 256,256,256,256,256,256,256,256,
+ 256,256,256,256,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,},
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {266,266,266,266,0+300-128,0+300-128,0+300-128,0+300-128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,},
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,50,40,50,40,50,40,50} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 1 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af409
+
+#if 1//timing_config,af419
+{
+ //af419
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-40,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128-40,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,},
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000154,// 340
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x0000014f,// 335
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000013b,// 315
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000159,// 345
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000019e,// 414
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000189,// 393
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000183,// 387
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001a6,// 422
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001ab,// 427
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000192,// 402
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000018d,// 397
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x00000192,// 402
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x00000196,// 406
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000180,// 384
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000180,// 384
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000173,// 371
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000018e,// 398
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x00000186,// 390
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000179,// 377
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x00000184,// 388
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x00000180,// 384
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x0000017d,// 381
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000016d,// 365
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x0000018c,// 396
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x0000017e,// 382
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x0000018f,// 399
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x00000183,// 387
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x0000018d,// 397
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x0000017e,// 382
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x00000197,// 407
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000018e,// 398
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000199,// 409
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000181,// 385
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000017b,// 379
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000018f,// 399
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000189,// 393
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 1 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af419
+
+#if 0//timing_config,real DDR3
+{
+ //real DDR3
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,CONFIG_DDR0_SIZE_768MB
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT,
+ .cfg_board_common_setting. fast_boot = {0},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 912,//1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-20,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128-20,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,},
+ #endif
+ #if 0
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896-128,896-128,896-128,896-128,896-128,896-128,896-128,896-128} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000007d,// 125
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000091,// 145
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000091,// 145
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x0000009b,// 155
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000000c2,// 194
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000000b0,// 176
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000000b0,// 176
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000c0,// 192
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000c3,// 195
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b4,// 180
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000be,// 190
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ba,// 186
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d5,// 213
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d0,// 208
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000cc,// 204
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000c3,// 195
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000be,// 190
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000c0,// 192
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000c8,// 200
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000e0,// 224
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000e5,// 229
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000e2,// 226
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000ec,// 236
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000ec,// 236
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000e7,// 231
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000e4,// 228
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000e9,// 233
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000e6,// 230
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000eb,// 235
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000f5,// 245
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000e7,// 231
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000fd,// 253
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000e8,// 232
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000e4,// 228
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ee,// 238
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ec,// 236
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000f2,// 242
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000038c,// 908
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000037a,// 890
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x0000039a,// 922
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000395,// 917
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007f-0x30,// 127
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000007d-0x30,// 125
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x0000006d-0x30,// 109
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000006f-0x30,// 111
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000048-0x30,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000044-0x30,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000038-0x30,// 56
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x0000003b-0x30,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000049-0x30,// 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x0000004b-0x30,// 75
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003b-0x30,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000049-0x30,// 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000040-0x30,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000052-0x30,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000039-0x30,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000040-0x30,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000045-0x30,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042-0x30,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000034-0x30,// 52
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000003c-0x30,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000086-0x30,// 134
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000003f-0x30,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000048-0x30,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000037-0x30,// 55
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000048-0x30,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=(0x0000004e)-0x30,// 78
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000044-0x30,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000042-0x30,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000047-0x30,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x0000007f-0x30,// 127
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000040-0x30,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000052-0x30,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d-0x30,// 61
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=(0x0000004e)-0x30,// 78
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003c-0x30,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=(0x0000003e)-0x30,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000003f-0x30,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x0000004c-0x30,// 76
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000091-0x30,// 145
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32+5,32,32+5,32,32+5,32,32+5,},//total 44
+
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter = {DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR3,} ,
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 1 //real DDR3
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end real DDR3
+
+#if 0//timing_config,af400 LPDDR4
+{
+ //af400
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,//DDR_WRITE_READ_DBI_DISABLE,DDR_READ_DBI_ENABLE
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_DDR3_32BIT
+ .cfg_board_common_setting. fast_boot = {0},
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 667,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_80_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_80_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 300,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 330,//330
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1//default cs cke 0 ,other AC=128
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,0,256, //0,0,0,0,0,0,0,0,
+ 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,
+ 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,
+ 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,
+ 128+128,128+128,128+128,128+128,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ } ,
+ #endif
+ #if 1
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1024,1024,1024,1024,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ #endif
+
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,26,32,26,32,26,32,26} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 1 //lpddr4
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 0, 1,
+ 0, 5, 0, 1, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0,
+ },
+ #endif
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 8,15,11,13,9,12,14,10,
+ 3,0,6,4,5,7,2,1,
+ 17,18,23,22,20,21,19,16,
+ 28,30,27,25,26,24,29,31,
+ 33,32,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af400 lpddr4
+
+#if 0//timing_config,af409 LPDDR4
+{
+ //af409
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0},
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ #if 0
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ },//total 36
+ #endif
+ #if 1
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 0,0,0,0,0,0,0,0,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,},
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,},
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,40,32,40,32,40,32,40} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 1 //lpddr4
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 0, 1,
+ 0, 5, 1, 2, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 8,15,11,13,9,12,14,10,
+ 3,0,6,4,5,7,2,1,
+ 17,18,23,22,20,21,19,16,
+ 28,30,27,25,26,24,29,31,
+ 33,32,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af409 LPDDR4
+
+#if 0 //timing_config,for dd3 pxp
+//ddr_set_t ddr_set_t_default=
+{
+ .cfg_board_common_setting. timming_magic = 0 ,
+ .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_version = 0 ,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_real_size = 0 , //0
+ .cfg_board_common_setting. fast_boot = {0} ,
+ .cfg_board_common_setting. ddr_func = 0 ,
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK ,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3 ,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 ,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 ,
+ .cfg_board_common_setting. dram_cs0_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs1_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB ,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB ,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 ,
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE ,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC ,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE ,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE ,
+ .cfg_board_common_setting. org_tdqs2dq = 0 ,
+ .cfg_board_common_setting. reserve1_test_function = {0} ,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT ,
+ #if 0
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ } ,
+
+ //ac_group0-ac_group1
+ #endif
+ #if 1
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ } ,
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0 ,
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 14,13,12,15,8,9,11,10,
+ 20,21,22,23,16,17,19,18,
+ 24,25,28,26,31,30,27,29,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,3,1,0,6,7,4,5,
+ 11,10,9,8,15,14,13,12,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ //1,0,3,2,5,4,7,6,
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,7,1,5,3,6,0,4,
+ 10,11,15,13,14,9,8,12,
+ 24,29,26,31,25,28,27,30,
+ 23,18,21,19,22,17,20,16,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35,
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ .cfg_board_common_setting. ddr_vddee_setting = {0} ,
+
+
+ .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[0]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #if 0
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 123,124,0,126,127,0,0,128,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,} ,
+ #endif
+ #if 0 //real board
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,} ,
+
+
+ #endif
+
+ #if 1 //for pxp
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} ,
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {128+512,128+512,128+512,128+512,128+512,128+512,128+512,128+512} , //total 8
+
+ #else
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} ,
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1094,1094,1094,1094,1094,1094,1094,1094} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896,896,896,896,896,896,896,896} , //total 8
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,
+ 42,42,42,42,42,42,42,42,42,42,
+ 42,42,42,42,42,58,42,58,42,58,42,58,} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+
+ .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[1]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #if 0
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ } , //total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64} ,
+ //total 72
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40} , //total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} ,
+},
+#endif //end for dd3 pxp
+
+#if 0 //timing_config,for ddr4 pxp remap
+//ddr_set_t ddr_set_t_default=
+{
+ .cfg_board_common_setting. timming_magic = 0 ,
+ .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_version = 0 ,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_real_size = 0 , //0
+ .cfg_board_common_setting. fast_boot = {0} ,
+ .cfg_board_common_setting. ddr_func = 0 ,
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK ,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4 ,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0 ,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 ,
+ .cfg_board_common_setting. dram_cs0_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs1_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB ,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB ,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 ,
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE ,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC ,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE ,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE ,
+ .cfg_board_common_setting. org_tdqs2dq = 0 ,
+ .cfg_board_common_setting. reserve1_test_function = {0} ,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT ,
+ #if 1 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 0
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ } ,
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0 ,
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 14,13,12,15,8,9,11,10,
+ 20,21,22,23,16,17,19,18,
+ 24,25,28,26,31,30,27,29,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,3,1,0,6,7,4,5,
+ 11,10,9,8,15,14,13,12,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ //1,0,3,2,5,4,7,6,
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,7,1,5,3,6,0,4,
+ 10,11,15,13,14,9,8,12,
+ 24,29,26,31,25,28,27,30,
+ 23,18,21,19,22,17,20,16,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ .cfg_board_common_setting. ddr_vddee_setting = {0} ,
+
+
+ .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM , //for pxp dram weak driver model
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[0]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #if 0
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ } , //total 36
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64} ,
+ //total 72
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {0,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,50,40,50,40,50,40,50} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {0,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[1]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #if 0
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ } , //total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64} ,
+ //total 72
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40} , //total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} ,
+},
+#endif //end for ddr4 pxp remap
+};
+//ddr timing end
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = AML_CUSTOMER_ID,
+ .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */
+ .log_ctrl = (1<<7) | /* (1<<7), print bl2 log into buffer */
+#ifdef CONFIG_SILENT_CONSOLE
+ (1<<6), /* do not print log buffer */
+#else
+ (0<<6), /* print log buffer before run bl31 */
+#endif
+.ddr_timming_save_mode = 1,
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/
+#if (VDDEE_VAL == 711)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 721)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 731)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 741)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 751)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 761)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 771)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 781)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 791)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 801)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 811)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 821)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 831)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 841)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 851)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 861)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 871)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 881)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 891)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/*
+ * GPIOE_0 PWM_A VDDEE_PWM
+ *
+ * GPIOE_1 PWM_B VCCK_PWM
+ */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400)
+
+/* pwm clock and pwm controller */
+#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800)
+#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400)
+#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400)
+#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400)
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ {0, 0, 0xffffffff, 0, 0, 0},
+ {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0},
+ /* enable vddcpu dc-dc, set GPIOD_10 high */
+ {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ /* set pwm A and pwm B clock rate to 24M, enable them */
+ {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3*/
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/c2_skt/Kconfig b/board/amlogic/c2_skt/Kconfig
new file mode 100644
index 0000000..3c4a8af
--- /dev/null
+++ b/board/amlogic/c2_skt/Kconfig
@@ -0,0 +1,25 @@
+if TARGET_C2_SKT
+
+config SYS_SOC
+ default "c2"
+
+config SYS_BOARD
+ default "c2_skt"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "c2_skt"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default y
+ help
+ support plltest command
+
+endif
diff --git a/board/amlogic/c2_skt/Makefile b/board/amlogic/c2_skt/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/c2_skt/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/c2_skt/aml-key/bl2aesiv b/board/amlogic/c2_skt/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c2_skt/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/c2_skt/aml-key/bl2aeskey b/board/amlogic/c2_skt/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c2_skt/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/c2_skt/aml-key/bl3xaesiv b/board/amlogic/c2_skt/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c2_skt/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/c2_skt/aml-key/bl3xaeskey b/board/amlogic/c2_skt/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c2_skt/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/c2_skt/aml-key/kernelaesiv b/board/amlogic/c2_skt/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/c2_skt/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/c2_skt/aml-key/kernelaeskey b/board/amlogic/c2_skt/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/c2_skt/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/c2_skt/aml-user-key.sig b/board/amlogic/c2_skt/aml-user-key.sig
new file mode 100755
index 0000000..088d1cf
--- /dev/null
+++ b/board/amlogic/c2_skt/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/c2_skt/c2_skt.c b/board/amlogic/c2_skt/c2_skt.c
new file mode 100644
index 0000000..efd5c5e
--- /dev/null
+++ b/board/amlogic/c2_skt/c2_skt.c
@@ -0,0 +1,341 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+unsigned int get_dram_size(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+}
+
+
+int dram_init_banksize(void)
+{
+ gd->bd->bi_dram[0].start = 0;
+ gd->bd->bi_dram[0].size = get_dram_size();
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+void board_init_mem(void) {
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+}
+
+/* set dts props */
+void aml_config_dtb(void)
+{
+ cpu_id_t cpuid = get_cpu_id();
+ if (MESON_CPU_MAJOR_ID_C2 != cpuid.family_id)
+ return;
+
+ run_command("fdt address $dtb_mem_addr", 0);
+ printf("%s %d\n", __func__, __LINE__);
+ if (cpuid.chip_rev == 0xA) {
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt rm /soc/emmc mmc-hs400-1_8v", 0);
+ run_command("fdt rm /soc/emmc fixed-emmc-driver-type", 0);
+ run_command("fdt print /soc/emmc", 0);
+ } else {
+ printf("%s %d\n", __func__, __LINE__);
+ run_command("fdt set /soc/bus/pinctrl/emmc/mux drive-strength <4>", 0);
+ run_command("fdt set /soc/bus/pinctrl/emmc/mux1 drive-strength <4>", 0);
+ run_command("fdt set /soc/bus/pinctrl/emmc_clk_gate/mux drive-strength <4>", 0);
+ run_command("fdt print /soc/bus/pinctrl/emmc", 0);
+ run_command("fdt print /soc/bus/pinctrl/emmc_clk_gate", 0);
+ }
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ active_clk();
+
+ return 0;
+}
+
+int board_late_init(void)
+{
+#ifdef CONFIG_PXP_EMULATOR
+ printf("board late init\n");
+#else
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+#endif
+
+ aml_config_dtb();
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+#ifdef UBOOT_RUN_IN_SRAM
+ return 0x180000; /* SRAM 1.5MB */
+#else
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+#endif /* UBOOT_RUN_IN_SRAM */
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+/* MUST NOT CHANGE this part unless u know what you are doing!
+* inherent parition for descrete bootloader to store fip
+* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
+* name must be same with TPL_PART_NAME
+*/
+{
+ .name = "tpl",
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 32*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 32*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 304*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "misc",
+ .offset = 0,
+ .size = 8 * SZ_8K,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/c2_skt/firmware/timing.c b/board/amlogic/c2_skt/firmware/timing.c
new file mode 100644
index 0000000..b7a8b0f
--- /dev/null
+++ b/board/amlogic/c2_skt/firmware/timing.c
@@ -0,0 +1,2769 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+#define TIMMING_MAX_CONFIG 1
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = {
+#if 0//timing_config,af400
+{
+ //af400
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_48_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-20,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128-20,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,},
+ #endif
+ #if 0
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000073,// 115
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000087,// 135
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000080,// 128
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000009f,// 159
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000095,// 149
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000092,// 146
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x0000009f,// 159
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000bb,// 187
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000cd,// 205
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b1,// 177
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000c5,// 197
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ad,// 173
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000a1,// 161
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000a2,// 162
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d1,// 209
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000d0,// 208
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000a7,// 167
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000a9,// 169
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000b9,// 185
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000ae,// 174
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000b1,// 177
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000b2,// 178
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000bd,// 189
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000d1,// 209
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000d0,// 208
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000c6,// 198
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000d1,// 209
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000bf,// 191
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000d3,// 211
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000dc,// 220
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000ae,// 174
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000a1,// 161
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ab,// 171
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ac,// 172
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000bd,// 189
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000037a,// 890
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000359,// 857
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000352,// 850
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000034f,// 847
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000075,// 117
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000006c,// 108
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000058,// 88
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000007c,// 124
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000034,// 52
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000002b,// 43
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000032,// 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000062,// 98
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000058,// 88
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000028,// 40
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000028,// 40
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000036,// 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000026,// 38
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002c,// 44
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000002a,// 42
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000032,// 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000029,// 41
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x0000003e,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d,// 61
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x0000002e,// 46
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000002f,// 47
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,50,40,50,40,50,40,50},//total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = {
+ (0 << 7) | 6, (0 << 7) | 16, (0 << 7) | 10, (0 << 7) | 3,
+ (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0,
+ (0 << 7) | 2, (0 << 7) | 4, (0 << 7) | 4, (0 << 7) | 10,
+ (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0, (0 << 7) | 0,
+ },
+
+ //pinmux setting
+ #if 1 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af400
+
+#if 1//timing_config,af409
+{
+ //af409
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,90,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,90,128,128,128,128,256,
+ 256,256,256,256,256,256,256,256,
+ 256,256,256,256,256,256,256,256,
+ 256,256,256,256,256,256,256,256,
+ 256,256,256,256,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,},
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {266,266,266,266,0+300-128,0+300-128,0+300-128,0+300-128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,
+ 50+266,50+266,50+266,50+266,50+266,50+266,50+266,50+266,},
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,50,40,50,40,50,40,50} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 1 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af409
+
+#if 0//timing_config,af419
+{
+ //af419
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_AUTO_SIZE,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_2048MB,1024MB,512MB,0MB,256,128,1536,768,3072,4096
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0,0,(1<<3)|(4)},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1200,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-40,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128-40,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,},
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000154,// 340
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x0000014f,// 335
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x0000013b,// 315
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000159,// 345
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000019e,// 414
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000189,// 393
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000183,// 387
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000001a6,// 422
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000001ab,// 427
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000192,// 402
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000018d,// 397
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x00000192,// 402
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x00000196,// 406
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000180,// 384
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000180,// 384
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000173,// 371
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000018e,// 398
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x00000186,// 390
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000179,// 377
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x00000184,// 388
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x00000180,// 384
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x0000017d,// 381
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000016d,// 365
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x0000018c,// 396
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x0000017e,// 382
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x0000018f,// 399
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x00000183,// 387
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x0000018d,// 397
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x0000017e,// 382
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x00000197,// 407
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000018e,// 398
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000199,// 409
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000181,// 385
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000017b,// 379
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000018f,// 399
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000189,// 393
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 1 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af419
+
+#if 0//timing_config,real DDR3
+{
+ //real DDR3
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,CONFIG_DDR0_SIZE_768MB
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT,
+ .cfg_board_common_setting. fast_boot = {0},
+ .cfg_board_common_setting. fast_boot[0] = 0x1,
+ .cfg_board_common_setting. fast_boot[3] = 0x46,
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 912,//1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 128,128,128-20,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128-20,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,},
+ #endif
+ #if 0
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896-128,896-128,896-128,896-128,896-128,896-128,896-128,896-128} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x0000007d,// 125
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000091,// 145
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000091,// 145
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x0000009b,// 155
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000a0,// 160
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x000000c2,// 194
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000000b0,// 176
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x000000b0,// 176
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000c0,// 192
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000c3,// 195
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000b4,// 180
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000be,// 190
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000ba,// 186
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000d5,// 213
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x000000c1,// 193
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000d0,// 208
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x000000cc,// 204
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000c3,// 195
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x000000be,// 190
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000c0,// 192
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x000000c8,// 200
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x000000e0,// 224
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000e5,// 229
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000e2,// 226
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000ec,// 236
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x000000ec,// 236
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000e7,// 231
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000e4,// 228
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000e9,// 233
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000e6,// 230
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x000000eb,// 235
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000f5,// 245
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x000000e7,// 231
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000fd,// 253
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x000000e8,// 232
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000e4,// 228
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000ee,// 238
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000ec,// 236
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000f2,// 242
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000038c,// 908
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000037a,// 890
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x0000039a,// 922
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000395,// 917
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000007f-0x30,// 127
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x0000007d-0x30,// 125
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x0000006d-0x30,// 109
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000006f-0x30,// 111
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000048-0x30,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000044-0x30,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x00000038-0x30,// 56
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x0000003b-0x30,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000049-0x30,// 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x0000004b-0x30,// 75
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000003b-0x30,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000049-0x30,// 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000040-0x30,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000052-0x30,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000039-0x30,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000040-0x30,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000045-0x30,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000042-0x30,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000034-0x30,// 52
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000003c-0x30,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000086-0x30,// 134
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000003f-0x30,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x00000048-0x30,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000037-0x30,// 55
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000048-0x30,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=(0x0000004e)-0x30,// 78
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000044-0x30,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000042-0x30,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000047-0x30,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x0000007f-0x30,// 127
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000040-0x30,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000052-0x30,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x0000003d-0x30,// 61
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=(0x0000004e)-0x30,// 78
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003c-0x30,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=(0x0000003e)-0x30,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000003f-0x30,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x0000004c-0x30,// 76
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000091-0x30,// 145
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,
+ 32,32+5,32,32+5,32,32+5,32,32+5,},//total 44
+
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter = {DDR_SOC_READ_DQS_GATE_MODE_EDGE_MODE_1_DDR3,} ,
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 1 //real DDR3
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end real DDR3
+
+#if 0//timing_config,af400 LPDDR4
+{
+ //af400
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,//CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,//DDR_WRITE_READ_DBI_DISABLE,DDR_READ_DBI_ENABLE
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_DDR3_32BIT
+ .cfg_board_common_setting. fast_boot = {0},
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 667,//1320,1200,1104,1008,912,792
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_80_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_80_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 300,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 330,//330
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1//default cs cke 0 ,other AC=128
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,0,256, //0,0,0,0,0,0,0,0,
+ 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,
+ 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,
+ 128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,
+ 128+128,128+128,128+128,128+128,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128+128,128+128,128+128,128+128,128+128,128+128,128+128,128+128,} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ 64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,64+128+128+256+128,
+ } ,
+ #endif
+ #if 1
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1024,1024,1024,1024,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ #endif
+
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,26,32,26,32,26,32,26} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 1 //lpddr4
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 0, 1,
+ 0, 5, 0, 1, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0,
+ },
+ #endif
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 8,15,11,13,9,12,14,10,
+ 3,0,6,4,5,7,2,1,
+ 17,18,23,22,20,21,19,16,
+ 28,30,27,25,26,24,29,31,
+ 33,32,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af400 lpddr4
+
+#if 0//timing_config,af409 LPDDR4
+{
+ //af409
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT,
+ .cfg_board_common_setting. fast_boot = {0},
+
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_48_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = {0},
+ #if 0
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ },//total 36
+ #endif
+ #if 1
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org = {
+ 0,0,0,0,0,0,0,0,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ //write delay line setting
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0+256,0+256,0+256,0+256,0+256,0+256,0+256,0+256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,
+ 50+256,50+256,50+256,50+256,50+256,50+256,50+256,50+256,},
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,},
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,40,32,40,32,40,32,40} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ //pinmux setting
+ #if 0 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 1 //lpddr4
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 0, 1,
+ 0, 5, 1, 2, 0, 0, 4, 0, 5, 0, 1, 3, 3, 4, 2, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ },
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0,
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 8,15,11,13,9,12,14,10,
+ 3,0,6,4,5,7,2,1,
+ 17,18,23,22,20,21,19,16,
+ 28,30,27,25,26,24,29,31,
+ 33,32,34,35
+ },//d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ .cfg_board_common_setting. timming_magic = 0x66223333,//ddr_set_t start
+ .cfg_board_common_setting. timming_max_valid_configs = TIMMING_MAX_CONFIG,//sizeof(__ddr_setting)/sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_version = 0,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting. timming_struct_real_size = 0, //0
+ .cfg_board_common_setting. ddr_func = 0,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting. dram_cs0_base_add = 0,
+ .cfg_board_common_setting. dram_cs1_base_add = 0,
+
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_1T_MODE,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting. org_tdqs2dq = 0,
+ .cfg_board_common_setting. reserve1_test_function = {0},
+ .cfg_board_common_setting. ddr_vddee_setting = {0},
+
+ //DDR frequercy 2
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 600,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = {0},
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ },//total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0},
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32},
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,},
+ #endif
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192},//total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64},//total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0},//total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {
+ 0,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40},//total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {
+ 0,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32},//total 36
+
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = {0},//ddr_set_t end
+},
+#endif //end af409 LPDDR4
+
+#if 0 //timing_config,for dd3 pxp
+//ddr_set_t ddr_set_t_default=
+{
+ .cfg_board_common_setting. timming_magic = 0 ,
+ .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_version = 0 ,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_real_size = 0 , //0
+ .cfg_board_common_setting. fast_boot = {0} ,
+ .cfg_board_common_setting. ddr_func = 0 ,
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK ,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR3 ,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 ,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 ,
+ .cfg_board_common_setting. dram_cs0_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs1_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_768MB ,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB ,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 ,
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE ,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC ,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE ,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE ,
+ .cfg_board_common_setting. org_tdqs2dq = 0 ,
+ .cfg_board_common_setting. reserve1_test_function = {0} ,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT ,
+ #if 0
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ } ,
+
+ //ac_group0-ac_group1
+ #endif
+ #if 1
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ } ,
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0 ,
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 14,13,12,15,8,9,11,10,
+ 20,21,22,23,16,17,19,18,
+ 24,25,28,26,31,30,27,29,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,3,1,0,6,7,4,5,
+ 11,10,9,8,15,14,13,12,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ //1,0,3,2,5,4,7,6,
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,7,1,5,3,6,0,4,
+ 10,11,15,13,14,9,8,12,
+ 24,29,26,31,25,28,27,30,
+ 23,18,21,19,22,17,20,16,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35,
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ .cfg_board_common_setting. ddr_vddee_setting = {0} ,
+
+
+ .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[0]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ },//total 36
+ #if 0
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 123,124,0,126,127,0,0,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,} ,
+ #endif
+ #if 0 //real board
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,} ,
+
+
+ #endif
+
+ #if 1 //for pxp
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {256,256,256,256,256,256,256,256} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} ,
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {128+512,128+512,128+512,128+512,128+512,128+512,128+512,128+512} , //total 8
+
+ #else
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,
+ 64+128,64+128,64+128,64+128,64+128,64+128,64+128,64+128,} ,
+
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {1094,1094,1094,1094,1094,1094,1094,1094} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {896,896,896,896,896,896,896,896} , //total 8
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,
+ 42,42,42,42,42,42,42,42,42,42,
+ 42,42,42,42,42,58,42,58,42,58,42,58,} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+
+ .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[1]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #if 0
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ } , //total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64} ,
+ //total 72
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40} , //total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} ,
+},
+#endif //end for dd3 pxp
+
+#if 0 //timing_config,for ddr4 pxp remap
+//ddr_set_t ddr_set_t_default=
+{
+ .cfg_board_common_setting. timming_magic = 0 ,
+ .cfg_board_common_setting. timming_max_valid_configs = sizeof(ddr_set_t_default)/sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_version = 0 ,
+ .cfg_board_common_setting. timming_struct_org_size = sizeof(ddr_set_t) ,
+ .cfg_board_common_setting. timming_struct_real_size = 0 , //0
+ .cfg_board_common_setting. fast_boot = {0} ,
+ .cfg_board_common_setting. ddr_func = 0 ,
+ .cfg_board_common_setting. board_id = CONFIG_BOARD_ID_MASK ,
+ .cfg_board_common_setting. DramType = CONFIG_DDR_TYPE_DDR4 ,
+ .cfg_board_common_setting. dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0 ,
+ .cfg_board_common_setting. DisabledDbyte = CONFIG_DISABLE_D32_D63 ,
+ .cfg_board_common_setting. dram_cs0_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs1_base_add = 0 ,
+ .cfg_board_common_setting. dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB ,
+ .cfg_board_common_setting. dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB ,
+ .cfg_board_common_setting. dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16 ,
+ .cfg_board_common_setting. Is2Ttiming = CONFIG_USE_DDR_2T_MODE ,
+ .cfg_board_common_setting. log_level = LOG_LEVEL_BASIC ,
+ .cfg_board_common_setting. ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE ,
+ .cfg_board_common_setting. pll_ssc_mode = DDR_PLL_SSC_DISABLE ,
+ .cfg_board_common_setting. org_tdqs2dq = 0 ,
+ .cfg_board_common_setting. reserve1_test_function = {0} ,
+ .cfg_board_common_setting. ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT ,
+ #if 1 //af409
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 8, 27, 10, 2, 9, 21, 5, 14, 1, 0, 25, 13, 12, 4, 7, 22, 0, 0, 0, 0, 6, 3, 20, 0, 0, 15, 26, 11,
+ },
+ #endif
+ #if 0 //af419
+ .cfg_board_common_setting. ac_pinmux = {
+ 0, 0, 0, 1, 2, 3,
+ 27, 12, 21, 9, 8, 0, 14, 10, 6, 7, 20, 5, 22, 13, 15, 2, 0, 0, 0, 0, 11, 26, 4, 0, 0, 25, 3, 1,
+ },
+ #endif
+ #if 0
+ .cfg_board_common_setting. ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 0, 0, 0, 0, 20, 21, 22, 0, 0, 25, 26, 27, 0
+ } ,
+ #endif
+ .cfg_board_common_setting. ddr_dqs_swap = 0 ,
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 14,13,12,15,8,9,11,10,
+ 20,21,22,23,16,17,19,18,
+ 24,25,28,26,31,30,27,29,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,3,1,0,6,7,4,5,
+ 11,10,9,8,15,14,13,12,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 3,2,0,1,7,6,5,4,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ //1,0,3,2,5,4,7,6,
+ #endif
+ #if 0
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 2,7,1,5,3,6,0,4,
+ 10,11,15,13,14,9,8,12,
+ 24,29,26,31,25,28,27,30,
+ 23,18,21,19,22,17,20,16,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+
+ #if 1
+ .cfg_board_common_setting. ddr_dq_remap = {
+ 0,1,2,3,4,5,6,7,
+ 8,9,10,11,12,13,14,15,
+ 16,17,18,19,20,21,22,23,
+ 24,25,26,27,28,29,30,31,
+ 32,33,34,35
+ } , //d0-d31 dm0 dm1 dm2 dm3
+ #endif
+ .cfg_board_common_setting. ddr_vddee_setting = {0} ,
+
+
+ .cfg_board_SI_setting_ps[0]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[0]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[0]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[0]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM , //for pxp dram weak driver model
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[0]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[0]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[0]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[0]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[0]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #if 0
+ .cfg_board_SI_setting_ps[0]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,384,384,384,384,
+ 384,384,384,384,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ } , //total 36
+ #endif
+ #if 1
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {128,128,128,128,128,128,128,128} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,
+ 192,192,192,192,192,192,192,192,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[0]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ .cfg_ddr_training_delay_ps[0]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64} ,
+ //total 72
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {0,0,0,0,0,0,0,0} , //total 8 //edge mode
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[0]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[0]. soc_bit_vref = {0,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,50,40,50,40,50,40,50} , //total 44
+ .cfg_ddr_training_delay_ps[0]. dram_bit_vref = {0,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[0]. reserve_training_parameter = {0} ,
+ //.cfg_ddr_training_delay_ps[0].reserve_training_parameter={((1<<7)|1),},
+
+ .cfg_board_SI_setting_ps[1]. DRAMFreq = 667 ,
+ .cfg_board_SI_setting_ps[1]. PllBypassEn = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_SequenceCtrl = 0 ,
+ .cfg_board_SI_setting_ps[1]. ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0 ,
+ .cfg_board_SI_setting_ps[1]. clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM ,
+ .cfg_board_SI_setting_ps[1]. dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM ,
+ .cfg_board_SI_setting_ps[1]. lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ ,
+ .cfg_board_SI_setting_ps[1]. reserve2 = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_ac_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_soc_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. vref_dram_data_permil = 0 ,
+ .cfg_board_SI_setting_ps[1]. max_core_timmming_frequency = 0 ,
+ .cfg_board_SI_setting_ps[1]. training_phase_parameter = {0} ,
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #if 0
+ .cfg_board_SI_setting_ps[1]. ac_trace_delay_org = {
+ 123,124,125,126,127,128,128,128,
+ 129,128,127,126,125,124,123,122,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,128,128,128,128,
+ 128,128,128,128,
+ } , //total 36
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. ac_trace_delay = {
+ 0,0,0,0,0,0,0,0, //0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,
+ } , //total 36
+ #endif
+ .cfg_ddr_training_delay_ps[1]. write_dqs_delay = {0,0,0,0,0,0,0,0} ,
+ //.cfg_ddr_training_delay_ps[0]. write_dqs_delay = {32,32,32,32,32,32,32,32} ,
+ #if 1
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,
+ 50,50,50,50,50,50,50,50,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,
+ 10,10,10,10,10,10,10,10,} ,
+ #endif
+ #if 0
+ .cfg_ddr_training_delay_ps[1]. write_dq_bit_delay = {64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64,
+ 64,64,64,64,64,64,64,64} ,
+ //total 72
+ #endif
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {256,256,256,256,256,256,256,256} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_gate_delay = {192,192,192,192,192,192,192,192} , //total 8
+ //.cfg_ddr_training_delay_ps[0]. read_dqs_gate_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dqs_delay = {64,64,64,64,64,64,64,64} , //total 8
+ .cfg_ddr_training_delay_ps[1]. read_dq_bit_delay = {0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0,
+ 0,0,0,0,0,0,0,0} , //total 72
+ .cfg_ddr_training_delay_ps[1]. soc_bit_vref = {40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40,
+ 40,40,40,40,40,40,40,40,40,40,40} , //total 44
+ .cfg_ddr_training_delay_ps[1]. dram_bit_vref = {32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32,32,32,32,32,32,32,32,32,
+ 32,32,32} , //total 36
+ .cfg_ddr_training_delay_ps[1]. reserve_training_parameter = {0} ,
+},
+#endif //end for ddr4 pxp remap
+};
+//ddr timing end
+
+pll_set_t __pll_setting = {
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .spi_ctrl = 0,
+ .lCustomerID = AML_CUSTOMER_ID,
+ .log_chl = 0x3, /* 0x77: all channel enable. 0xFF: with stream info */
+ .log_ctrl = (1<<7) | /* (1<<7), print bl2 log into buffer */
+#ifdef CONFIG_SILENT_CONSOLE
+ (1<<6), /* do not print log buffer */
+#else
+ (0<<6), /* print log buffer before run bl31 */
+#endif
+.ddr_timming_save_mode = 1,
+};
+
+ddr_reg_t __ddr_reg[] = {
+ /* demo, user defined override register */
+ {0xaabbccdd, 0, 0, 0, 0, 0},
+ {0x11223344, 0, 0, 0, 0, 0},
+ {0, 0, 0, 0, 0, 0},
+};
+
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG: VDDEE PWM table 0.69v-0.89v*/
+#if (VDDEE_VAL == 711)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 721)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 731)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 741)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 751)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 761)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 771)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 781)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 791)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 801)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 811)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 821)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 831)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 841)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 851)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 861)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 871)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 881)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 891)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+/* for PWM use */
+/*
+ * GPIOE_0 PWM_A VDDEE_PWM
+ *
+ * GPIOE_1 PWM_B VCCK_PWM
+ */
+/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
+#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe000400)
+#define PADCTRL_GPIOE_DS ((0x0035 << 2) + 0xfe000400)
+
+/* pwm clock and pwm controller */
+#define CLKTREE_PWM_CLK_AB_CTRL ((0x0031 << 2) + 0xfe000800)
+#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe002400)
+#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe002400)
+#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe002400)
+
+bl2_reg_t __bl2_reg[] = {
+ /* demo, user defined override register */
+ {0, 0, 0xffffffff, 0, 0, 0},
+ {PWMAB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ {PWMAB_MISC_REG_AB, 0x3 << 0, 0x3, 0, BL2_INIT_STAGE_1, 0},
+ /* enable vddcpu dc-dc, set GPIOD_10 high */
+ {PADCTRL_GPIOD_OEN, 0x0 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_GPIOD_O, 0x1 << 10, 0x1 << 10, 0, BL2_INIT_STAGE_1, 0},
+ /* set pwm A and pwm B clock rate to 24M, enable them */
+ {CLKTREE_PWM_CLK_AB_CTRL,1 << 8 | 1 << 24 , 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3*/
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3, 0xf, 0, BL2_INIT_STAGE_1, 0},
+ {PADCTRL_PIN_MUX_REG2, 0x3 << 4, 0xf << 4, 0, BL2_INIT_STAGE_1, 0},
+};
diff --git a/board/amlogic/configs/a1_ad401.h b/board/amlogic/configs/a1_ad401.h
new file mode 100644
index 0000000..a36e020
--- /dev/null
+++ b/board/amlogic/configs/a1_ad401.h
@@ -0,0 +1,370 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+#define AML_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+#define AML_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
+
+/* configs for CEC */
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif// #ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x00020000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=adnl 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "boot_part=boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml_uart,0xfe002000 "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "if keyman read mac_wifi ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac_wifi=${mac_wifi} androidboot.mac_wifi=${mac_wifi};"\
+ "fi;"\
+ "if keyman read mac_bt ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac_bt=${mac_bt} androidboot.mac_bt=${mac_bt};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run storeargs;"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (8*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+/* #define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24 */
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+#define UBOOT_RUN_IN_SRAM
+#ifdef CONFIG_UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (1*1024*1024)
+#endif
+
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 4
+#define USB_PHY21_BIT 6
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+#define CONFIG_CPU_ARMV8
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x100000
+
+#endif
diff --git a/board/amlogic/configs/a1_ad402.h b/board/amlogic/configs/a1_ad402.h
new file mode 100644
index 0000000..f0eb569
--- /dev/null
+++ b/board/amlogic/configs/a1_ad402.h
@@ -0,0 +1,378 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+#define AML_VDDCORE_INIT_VOLTAGE 840 // VCCK power up voltage
+ /* If AML_VDDCORE_INIT_VOLTAGE_SEL is 1, the voltage of vddee
+ * will be controlled by efuse. if 0, it is controlled by
+ * AML_VDDCORE_INIT_VOLTAGE
+ */
+#define AML_VDDCORE_INIT_VOLTAGE_SEL 1
+#define AML_VDDCORE_INIT_EFUSE_MARGIN 30
+#define AML_VDDCORE_INIT_EFUSE_OFFSET 0xc8
+#define AML_VDDCORE_INIT_EFUSE_BASE_V0LT 680
+
+/* configs for CEC */
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif// #ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x00020000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=adnl 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "boot_part=boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml_uart,0xfe002000 "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "if keyman read mac_wifi ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac_wifi=${mac_wifi} androidboot.mac_wifi=${mac_wifi};"\
+ "fi;"\
+ "if keyman read mac_bt ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac_bt=${mac_bt} androidboot.mac_bt=${mac_bt};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run storeargs;"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (8*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+/* #define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24 */
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+#define UBOOT_RUN_IN_SRAM
+#ifdef CONFIG_UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (1*1024*1024)
+#endif
+
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 4
+#define USB_PHY21_BIT 6
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#if 0
+#define CONFIG_AML_PARTITION 1
+#endif
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+#define CONFIG_CPU_ARMV8
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x100000
+
+#endif
diff --git a/board/amlogic/configs/a1_ad409.h b/board/amlogic/configs/a1_ad409.h
new file mode 100644
index 0000000..e6e2278
--- /dev/null
+++ b/board/amlogic/configs/a1_ad409.h
@@ -0,0 +1,383 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VDDCORE_INIT_VOLTAGE 805 // VCCK power up voltage
+/* If AML_VDDCORE_INIT_VOLTAGE_SEL is 1, the voltage of vddee
+ * will be controlled by efuse. if 0, it is controlled by
+ * AML_VDDCORE_INIT_VOLTAGE
+ */
+#define AML_VDDCORE_INIT_VOLTAGE_SEL 1
+#define AML_VDDCORE_INIT_EFUSE_MARGIN 30
+#define AML_VDDCORE_INIT_EFUSE_OFFSET 0xc8
+#define AML_VDDCORE_INIT_EFUSE_BASE_V0LT 680
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x00020000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=adnl 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "boot_part=boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xfe002000"\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run storeargs;"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (8*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+#define UBOOT_RUN_IN_SRAM
+#ifdef CONFIG_UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (1*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 4
+#define USB_PHY21_BIT 6
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+#define CONFIG_CPU_ARMV8
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x100000
+
+#endif
+
diff --git a/board/amlogic/configs/c1_ae400.h b/board/amlogic/configs/c1_ae400.h
new file mode 100644
index 0000000..b080705
--- /dev/null
+++ b/board/amlogic/configs/c1_ae400.h
@@ -0,0 +1,404 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 940 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x01080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=adnl 1000\0" \
+ "usb_force_upgrade=0\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "boot_part=boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xfe002000"\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "if itest ${usb_force_upgrade} == 1; then adnl; fi;"\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_boot_part;"\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run storeargs;"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (8*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (2*16*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+//#define CONFIG_MESON_NFC
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) || defined (CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC)
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE 1
+ #define CONFIG_CMD_UBI 1
+ #define CONFIG_CMD_UBIFS 1
+ #define CONFIG_RBTREE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_MTD_UBI_WL_THRESHOLD 4096
+ #define CONFIG_MTD_UBI_BEB_LIMIT 20
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+/* top hide for NBG file */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use hardware sha2
+//#define CONFIG_AML_HW_SHA2
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_MDUMP_COMPRESS 1
+
+#define BL32_SHARE_MEM_SIZE 0x100000
+
+#endif
+
diff --git a/board/amlogic/configs/c1_ae401.h b/board/amlogic/configs/c1_ae401.h
new file mode 100644
index 0000000..9ef638c
--- /dev/null
+++ b/board/amlogic/configs/c1_ae401.h
@@ -0,0 +1,404 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 940 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x01080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=adnl 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "boot_part=boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} boot 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xfe002000"\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} boot 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run storeargs;"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (8*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (2*16*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+//#define CONFIG_MESON_NFC
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) || defined (CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC)
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE 1
+ #define CONFIG_CMD_UBI 1
+ #define CONFIG_CMD_UBIFS 1
+ #define CONFIG_RBTREE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_MTD_UBI_WL_THRESHOLD 4096
+ #define CONFIG_MTD_UBI_BEB_LIMIT 20
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined(CONFIG_MTD_SPI_NAND)
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+/* top hide for NBG file */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use hardware sha2
+//#define CONFIG_AML_HW_SHA2
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x100000
+
+#endif
+
diff --git a/board/amlogic/configs/c1_ae402.h b/board/amlogic/configs/c1_ae402.h
new file mode 100644
index 0000000..9ef638c
--- /dev/null
+++ b/board/amlogic/configs/c1_ae402.h
@@ -0,0 +1,404 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 940 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x01080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=adnl 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "boot_part=boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} boot 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xfe002000"\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} boot 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run storeargs;"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (8*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (2*16*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+//#define CONFIG_MESON_NFC
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) || defined (CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC)
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE 1
+ #define CONFIG_CMD_UBI 1
+ #define CONFIG_CMD_UBIFS 1
+ #define CONFIG_RBTREE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_MTD_UBI_WL_THRESHOLD 4096
+ #define CONFIG_MTD_UBI_BEB_LIMIT 20
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined(CONFIG_MTD_SPI_NAND)
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+/* top hide for NBG file */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use hardware sha2
+//#define CONFIG_AML_HW_SHA2
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x100000
+
+#endif
+
diff --git a/board/amlogic/configs/c1_ae409.h b/board/amlogic/configs/c1_ae409.h
new file mode 100644
index 0000000..d4e7209
--- /dev/null
+++ b/board/amlogic/configs/c1_ae409.h
@@ -0,0 +1,413 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 940 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#if 0
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x01080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=adnl 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "boot_part=boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xfe002000"\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run storeargs;"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (8*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (2*16*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) || defined (CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC)
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE 1
+ #define CONFIG_CMD_UBI 1
+ #define CONFIG_CMD_UBIFS 1
+ #define CONFIG_RBTREE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_MTD_UBI_WL_THRESHOLD 4096
+ #define CONFIG_MTD_UBI_BEB_LIMIT 20
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+/* top hide for NBG file */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x100000
+
+#endif
+
diff --git a/board/amlogic/configs/c2_af400.h b/board/amlogic/configs/c2_af400.h
new file mode 100644
index 0000000..933bc1b
--- /dev/null
+++ b/board/amlogic/configs/c2_af400.h
@@ -0,0 +1,416 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#if 0
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x01080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=adnl 1000\0" \
+ "usb_force_upgrade=0\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "boot_part=boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe002000"\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "if test ${usb_force_upgrade} = 1; then adnl; fi;"\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "ddr_auto_fast_boot_check 6;"\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run storeargs;"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (8*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (2*16*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) || defined (CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC)
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE 1
+ #define CONFIG_CMD_UBI 1
+ #define CONFIG_CMD_UBIFS 1
+ #define CONFIG_RBTREE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_MTD_UBI_WL_THRESHOLD 4096
+ #define CONFIG_MTD_UBI_BEB_LIMIT 20
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+/* top hide for NBG file */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x100000
+
+#endif
+
diff --git a/board/amlogic/configs/c2_af401.h b/board/amlogic/configs/c2_af401.h
new file mode 100644
index 0000000..f2e9379
--- /dev/null
+++ b/board/amlogic/configs/c2_af401.h
@@ -0,0 +1,410 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#if 0
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x01080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=adnl 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "boot_part=boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe002000"\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "ddr_auto_fast_boot_check 6;"\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run storeargs;"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (8*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (2*16*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) || defined (CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC)
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE 1
+ #define CONFIG_CMD_UBI 1
+ #define CONFIG_CMD_UBIFS 1
+ #define CONFIG_RBTREE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_MTD_UBI_WL_THRESHOLD 4096
+ #define CONFIG_MTD_UBI_BEB_LIMIT 20
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+/* top hide for NBG file */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x100000
+
+#endif
+
diff --git a/board/amlogic/configs/c2_af402.h b/board/amlogic/configs/c2_af402.h
new file mode 100644
index 0000000..a9e0ed7
--- /dev/null
+++ b/board/amlogic/configs/c2_af402.h
@@ -0,0 +1,387 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#if 0
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+#if 0
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+#endif
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#if 0
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x01080000\0"\
+ "otg_device=1\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "usb_burning=adnl 1000\0" \
+ "usb_force_upgrade=0\0" \
+ "fdt_high=0x8000000\0"\
+ "initrd_high=0x8000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "boot_part=boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe002000"\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "if test ${usb_force_upgrade} = 1; then adnl; fi;"\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} androidboot.bootloader=${bootloader_version} "\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs};"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs};"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "bootcmd=run storeboot\0"
+#if 0
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run storeargs;"
+#else
+#define CONFIG_PREBOOT \
+ "run storeargs;"
+#endif
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (8*1024)
+//#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#if 0
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#endif
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (2*16*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if 0
+#if defined(CONFIG_SPI_NAND) || defined (CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC)
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE 1
+ #define CONFIG_CMD_UBI 1
+ #define CONFIG_CMD_UBIFS 1
+ #define CONFIG_RBTREE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_MTD_UBI_WL_THRESHOLD 4096
+ #define CONFIG_MTD_UBI_BEB_LIMIT 20
+#endif
+#else
+ #define CONFIG_CMD_MTDPARTS 1
+#endif
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+#if 0
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+#endif
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+//#define CONFIG_SHA1 1
+//#define CONFIG_MD5 1
+
+/* commands */
+#if 0
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#endif
+//#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+//#define CONFIG_LIBAVB 1
+/* top hide for NBG file */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000
+
+#define CONFIG_CPU_ARMV8
+#if 0
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+#endif
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#endif
+
diff --git a/board/amlogic/configs/c2_af409.h b/board/amlogic/configs/c2_af409.h
new file mode 100644
index 0000000..813dbf9
--- /dev/null
+++ b/board/amlogic/configs/c2_af409.h
@@ -0,0 +1,414 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#if 0
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x01080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=adnl 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "boot_part=boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe002000"\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "ddr_auto_fast_boot_check 6;"\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run storeargs;"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (8*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (2*16*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) || defined (CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC)
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE 1
+ #define CONFIG_CMD_UBI 1
+ #define CONFIG_CMD_UBIFS 1
+ #define CONFIG_RBTREE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_MTD_UBI_WL_THRESHOLD 4096
+ #define CONFIG_MTD_UBI_BEB_LIMIT 20
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+/* top hide for NBG file */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x100000
+
+#endif
+
diff --git a/board/amlogic/configs/c2_af419.h b/board/amlogic/configs/c2_af419.h
new file mode 100644
index 0000000..813dbf9
--- /dev/null
+++ b/board/amlogic/configs/c2_af419.h
@@ -0,0 +1,414 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#if 0
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x01080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=adnl 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "boot_part=boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe002000"\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "ddr_auto_fast_boot_check 6;"\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run storeargs;"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (8*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (2*16*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) || defined (CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC)
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE 1
+ #define CONFIG_CMD_UBI 1
+ #define CONFIG_CMD_UBIFS 1
+ #define CONFIG_RBTREE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_MTD_UBI_WL_THRESHOLD 4096
+ #define CONFIG_MTD_UBI_BEB_LIMIT 20
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+/* top hide for NBG file */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x100000
+
+#endif
+
diff --git a/board/amlogic/configs/c2_skt.h b/board/amlogic/configs/c2_skt.h
new file mode 100644
index 0000000..abce987
--- /dev/null
+++ b/board/amlogic/configs/c2_skt.h
@@ -0,0 +1,424 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 801 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#if 0
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x01080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=adnl 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "boot_part=boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe002000"\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "ddr_auto_fast_boot_check 6;"\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+
+#ifdef CONFIG_PXP_EMULATOR
+#define CONFIG_PREBOOT "echo preboot for pxp"
+/* need change defconfig for this
+#define CONFIG_BOOTCOMMAND \
+ "setenv bootargs console=ttyS0 earlycon=meson,0xfe002000 loglevel=9;\
+ setenv dtb_mem_addr 0x6000000;fdt addr 0x6000000;booti 0x8000000 0x7000000 0x6000000;"
+*/
+#define CONFIG_ENV_IS_NOWHERE 1
+#else
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run storeargs;"
+#endif
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (8*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (2*16*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) || defined (CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC)
+ #define CONFIG_CMD_NAND 1
+ #define CONFIG_MTD_DEVICE 1
+ #define CONFIG_CMD_UBI 1
+ #define CONFIG_CMD_UBIFS 1
+ #define CONFIG_RBTREE 1
+ #define CONFIG_CMD_MTDPARTS 1
+ #define CONFIG_MTD_PARTITIONS 1
+ #define CONFIG_MTD_UBI_WL_THRESHOLD 4096
+ #define CONFIG_MTD_UBI_BEB_LIMIT 20
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined(CONFIG_MTD_SPI_NAND)
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+/* top hide for NBG file */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00400000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x100000
+
+#endif
+
diff --git a/board/amlogic/configs/g12a_u200_v1.h b/board/amlogic/configs/g12a_u200_v1.h
new file mode 100644
index 0000000..833ef92
--- /dev/null
+++ b/board/amlogic/configs/g12a_u200_v1.h
@@ -0,0 +1,618 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __G12A_U200_V1_H__
+#define __G12A_U200_V1_H__
+
+#include <asm/arch/cpu.h>
+
+/* #define CONFIG_SYS_GENERIC_BOARD 1 */
+/*
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+*/
+
+/*
+ * platform power init config
+ */
+#if 0
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
+#define CONFIG_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
+#endif
+
+#define AML_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+#define AML_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
+
+/* configs for CEC */
+#if 0
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+/*if use bt-wakeup,open it*/
+#define CONFIG_BT_WAKEUP
+#endif
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#if 0
+#define CONFIG_CMD_SARADC 1
+#define CONFIG_SARADC_CH 2
+#endif
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#if 0
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+/* #define CONFIG_AML_MESON_SERIAL 1 */
+#if 0
+#define CONFIG_SERIAL_MULTI 1
+#endif
+
+/* Enable ir remote wake up for bl30 */
+#if 0
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+#endif
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#if 0
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+#endif
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=3080000\0"\
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "lock=10001000\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "reboot_mode_android=""normal""\0"\
+ "Irq_check_en=0\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if test ${reboot_mode} = normal; then "\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else "\
+ "boot_cooling;"\
+ "fi;fi;"\
+ "get_system_as_root_mode;"\
+ "echo system_mode: ${system_mode};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv fs_type ""ro rootwait skip_initramfs"";"\
+ "run storeargs;"\
+ "fi;"\
+ "get_avb_mode;"\
+ "echo active_slot: ${active_slot};"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if test ${avb2} = 0; then "\
+ "if test ${active_slot} = _a; then "\
+ "setenv bootargs ${bootargs} root=/dev/mmcblk0p23;"\
+ "else if test ${active_slot} = _b; then "\
+ "setenv bootargs ${bootargs} root=/dev/mmcblk0p24;"\
+ "fi;fi;"\
+ "fi;"\
+ "imgread dtb _aml_dtb 0x01000000; fdt addr 0x01000000;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "get_rebootmode;"\
+ "echo reboot_mode:::: ${reboot_mode};"\
+ "if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "fi;fi;"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "if keyman read region_code ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=US;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "forceupdate;" \
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+/* #define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24 */
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#if 0
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+#endif
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#if 0
+#define CONFIG_STORE_COMPATIBLE 1
+#endif
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+#if 0
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+/* #define CONFIG_CMD_BMP 1 */
+#endif
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+
+/* UBOOT fastboot config */
+#if 0
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "u200"
+#endif
+
+/* UBOOT Facotry usb/sdcard burning config */
+/* #define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning */
+#if 0
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isnt power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+#endif
+
+#if 0
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+#endif
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#if 0
+#define CONFIG_EFUSE 1
+#endif
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+#if 0
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+#endif
+/* #define CONFIG_CMD_FDT 1 */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#if 0
+#define CONFIG_AML_PARTITION 1
+#endif
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+#if 0
+#define CONFIG_MDUMP_COMPRESS 1
+#endif
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#if 0
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_CMD_LOADB 1
+#endif
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 /* hide 128MB for kernel reserve */
+#define CONFIG_LIBAVB 1
+
+#define CONFIG_CPU_ARMV8
+
+#define CONFIG_MULTI_DTB 1
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* for SRAM size limitation just disable NAND
+ as the socket board default has no NAND */
+/* #undef CONFIG_AML_NAND */
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#if 0
+#define CONFIG_SECURE_STORAGE 1
+#endif
+
+/* build with uboot auto test */
+/* #define CONFIG_AML_UBOOT_AUTO_TEST 1 */
+
+/* board customer ID */
+/* #define CONFIG_CUSTOMER_ID (0x6472616F624C4D41) */
+
+#if 0
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#endif
+
+/* Choose One of Ethernet Type */
+#undef CONFIG_ETHERNET_NONE
+#define ETHERNET_INTERNAL_PHY
+#undef ETHERNET_EXTERNAL_PHY
+
+#if 0
+#define CONFIG_CMD_AML_MTEST 1
+#endif
+#if defined(CONFIG_CMD_AML_MTEST)
+#if !defined(CONFIG_SYS_MEM_TOP_HIDE)
+#error CONFIG_CMD_AML_MTEST depends on CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+#if !(CONFIG_SYS_MEM_TOP_HIDE)
+#error CONFIG_SYS_MEM_TOP_HIDE should not be zero;
+#endif
+#endif
+
+#endif
+
diff --git a/board/amlogic/configs/g12b_w400_v1.h b/board/amlogic/configs/g12b_w400_v1.h
new file mode 100644
index 0000000..11fe0f1
--- /dev/null
+++ b/board/amlogic/configs/g12b_w400_v1.h
@@ -0,0 +1,663 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __G12B_W400_V1_H__
+#define __G12B_W400_V1_H__
+
+#include <asm/arch/cpu.h>
+
+/* #define CONFIG_SYS_GENERIC_BOARD 1 */
+/*
+#ifndef CONFIG_AML_MESON
+#warning "include warning"
+#endif
+*/
+
+/*
+ * platform power init config
+ */
+#if 0
+#define CONFIG_PLATFORM_POWER_INIT
+#define CONFIG_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
+#define CONFIG_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+#define CONFIG_VDDEE_SLEEP_VOLTAGE 770 // VDDEE suspend voltage
+#endif
+
+#define AML_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+#define AML_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
+
+/* configs for CEC */
+#if 0
+#define CONFIG_CEC_OSD_NAME "AML_TV"
+#define CONFIG_CEC_WAKEUP
+/*if use bt-wakeup,open it*/
+#define CONFIG_BT_WAKEUP
+#endif
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* config saradc*/
+#if 0
+#define CONFIG_CMD_SARADC 1
+#define CONFIG_SARADC_CH 2
+#endif
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+/* #define CONFIG_AML_MESON_SERIAL 1 */
+#if 0
+#define CONFIG_SERIAL_MULTI 1
+#endif
+
+/* Enable ir remote wake up for bl30 */
+#if 0
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+#endif
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#if 0
+#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+#endif
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=1080000\0"\
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x1000000\0" \
+ "fb_addr=0x3d800000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=update 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "try_auto_burn=update 700 750;\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "sdc_burning=sdc_burn ${sdcburncfg}\0"\
+ "wipe_data=successful\0"\
+ "wipe_cache=successful\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "lock=10001000\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "reboot_mode_android=""normal""\0"\
+ "Irq_check_en=0\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then "\
+ "run init_display; run storeargs; run update;"\
+ "else fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if test ${reboot_mode} = normal; then "\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else "\
+ "boot_cooling;"\
+ "fi;fi;"\
+ "get_system_as_root_mode;"\
+ "echo system_mode: ${system_mode};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv fs_type ""ro rootwait skip_initramfs"";"\
+ "run storeargs;"\
+ "fi;"\
+ "get_avb_mode;"\
+ "echo active_slot: ${active_slot};"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if test ${avb2} = 0; then "\
+ "if test ${active_slot} = _a; then "\
+ "setenv bootargs ${bootargs} root=/dev/mmcblk0p23;"\
+ "else if test ${active_slot} = _b; then "\
+ "setenv bootargs ${bootargs} root=/dev/mmcblk0p24;"\
+ "fi;fi;"\
+ "fi;"\
+ "imgread dtb _aml_dtb 0x01000000; fdt addr 0x01000000;"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "run update;"\
+ "\0"\
+ "factory_reset_poweroff_protect="\
+ "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
+ "if test ${wipe_data} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; "\
+ "if test ${wipe_cache} = failed; then "\
+ "run init_display; run storeargs;"\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "fi; \0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run sdc_burning; "\
+ "if mmcinfo; then "\
+ "run recovery_from_sdcard;"\
+ "fi;"\
+ "if usb start 0; then "\
+ "run recovery_from_udisk;"\
+ "fi;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload mmc 0 ${loadaddr} recovery.img; then "\
+ "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload usb 0 ${loadaddr} recovery.img; then "\
+ "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
+ "wipeisb; "\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "get_rebootmode;"\
+ "echo reboot_mode:::: ${reboot_mode};"\
+ "if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "fi;fi;"\
+ "\0"\
+ "cmdline_keys="\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
+ "setenv serial 1234567890;"\
+ "fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "if keyman read region_code ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=US;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOAO_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+ "irremote_update="\
+ "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
+ "echo read irkey ok!; " \
+ "if itest ${irkey_value} == 0xe31cfb04; then " \
+ "run update;" \
+ "else if itest ${irkey_value} == 0xb748fb04; then " \
+ "run update;\n" \
+ "fi;fi;" \
+ "fi;\0" \
+
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run factory_reset_poweroff_protect;"\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "forceupdate;" \
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+
+#define CONFIG_BOOTCOMMAND "run storeboot"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+/* #define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24 */
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#if 0
+#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
+#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
+#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+#endif
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#if 0
+#define CONFIG_STORE_COMPATIBLE 1
+#endif
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+/* support for mtd */
+
+/* #define CONFIG_AML_MTD 1*/
+
+/* support for nftl */
+/*#define CONFIG_AML_NAND 1*/
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#ifdef CONFIG_AML_MTD
+
+/* bootlaoder is construct by bl2 and fip
+ * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
+ * will not be stored continuously, and nand layout
+ * would be bl2|rsv|fip|normal, but not
+ * bl2|fip|rsv|noraml anymore
+ */
+#if 0
+#define CONFIG_DISCRETE_BOOTLOADER
+#endif
+
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+#if 0
+#define CONFIG_TPL_SIZE_PER_COPY 0x200000
+#define CONFIG_TPL_COPY_NUM 4
+#define CONFIG_TPL_PART_NAME "tpl"
+/* for bl2, restricted by romboot */
+/* SKT 1024 pages only support 4 block, so 4 copies */
+#define CONFIG_BL2_COPY_NUM 4
+#endif
+#endif /* CONFIG_DISCRETE_BOOTLOADER */
+
+/* #define CONFIG_CMD_NAND 1 */
+#define CONFIG_MTD_DEVICE y
+/* mtd parts of ourown.*/
+#define CONFIG_AML_MTDPART 1
+/* mtd parts by env default way.*/
+/*
+#define MTDIDS_NAME_STR "aml_nand.0"
+#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
+#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
+ "3M@8192K(logo)," \
+ "10M(recovery)," \
+ "8M(kernel)," \
+ "40M(rootfs)," \
+ "-(data)"
+*/
+#define CONFIG_CMD_UBI
+#define CONFIG_CMD_UBIFS
+#define CONFIG_MTD_UBI_WL_THRESHOLD 4096
+#define CONFIG_MTD_UBI_BEB_LIMIT 20
+#define CONFIG_RBTREE
+#define CONFIG_CMD_NAND_TORTURE 1
+#define CONFIG_CMD_MTDPARTS 1
+#define CONFIG_SYS_MAX_NAND_DEVICE 2
+#define CONFIG_SYS_NAND_BASE_LIST {0}
+#endif
+/* endof CONFIG_AML_MTD */
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+
+#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+#if 0
+#define CONFIG_AML_CANVAS 1
+#define CONFIG_AML_OSD 1
+#define CONFIG_OSD_SCALE_ENABLE 1
+/* #define CONFIG_CMD_BMP 1 */
+#endif
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F69E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+
+#define AML_TXLX_USB 1
+
+/* UBOOT fastboot config */
+#if 0
+#define CONFIG_CMD_FASTBOOT 1
+#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
+#define CONFIG_FASTBOOT_FLASH 1
+#define CONFIG_USB_GADGET 1
+#define CONFIG_USBDOWNLOAD_GADGET 1
+#define CONFIG_SYS_CACHELINE_SIZE 64
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
+#define CONFIG_DEVICE_PRODUCT "g12b_w400"
+#endif
+
+/* UBOOT Facotry usb/sdcard burning config */
+/* #define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning */
+#if 0
+#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
+#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isnt power-key for factory sdcard burning
+#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
+#endif
+
+#if 0
+#define CONFIG_AML_SECURITY_KEY 1
+#define CONFIG_UNIFY_KEY_MANAGE 1
+#endif
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+/* other devices */
+#if 0
+#define CONFIG_EFUSE 1
+#endif
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+#if 0
+#define CONFIG_CMD_CACHE 1
+#define CONFIG_CMD_BOOTI 1
+#define CONFIG_CMD_EFUSE 1
+#define CONFIG_CMD_MEMORY 1
+#define CONFIG_CMD_FAT 1
+#define CONFIG_CMD_GPIO 1
+#define CONFIG_CMD_REBOOT 1
+#define CONFIG_CMD_ECHO 1
+#define CONFIG_CMD_JTAG 1
+#define CONFIG_CMD_AUTOSCRIPT 1
+#define CONFIG_CMD_MISC 1
+#endif
+/* #define CONFIG_CMD_FDT 1 */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+#if 0
+#define CONFIG_AML_PARTITION 1
+#endif
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+#if 0
+#define CONFIG_MDUMP_COMPRESS 1
+#endif
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#if 0
+#define CONFIG_NEED_BL301 1
+#define CONFIG_NEED_BL32 1
+#define CONFIG_CMD_RSVMEM 1
+#define CONFIG_FIP_IMG_SUPPORT 1
+#define CONFIG_SYS_LONGHELP 1
+#define CONFIG_CMD_MISC 1
+#define CONFIG_CMD_ITEST 1
+#define CONFIG_CMD_CPU_TEMP 1
+#define CONFIG_CMD_LOADB 1
+#endif
+#define CONFIG_FIP_IMG_SUPPORT 1
+/* #define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 */ /* hide 128MB for kernel reserve */
+#define CONFIG_LIBAVB 1
+
+#define CONFIG_CPU_ARMV8
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* for SRAM size limitation just disable NAND
+ as the socket board default has no NAND */
+/* #undef CONFIG_AML_NAND */
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#if 0
+#define CONFIG_SECURE_STORAGE 1
+#endif
+
+/* build with uboot auto test */
+/* #define CONFIG_AML_UBOOT_AUTO_TEST 1 */
+
+/* board customer ID */
+/* #define CONFIG_CUSTOMER_ID (0x6472616F624C4D41) */
+
+#if 0
+#if defined(CONFIG_CUSTOMER_ID)
+ #undef CONFIG_AML_CUSTOMER_ID
+ #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
+#endif
+#endif
+
+/* Choose One of Ethernet Type */
+#undef CONFIG_ETHERNET_NONE
+#define ETHERNET_INTERNAL_PHY
+#undef ETHERNET_EXTERNAL_PHY
+
+#if 0
+#define CONFIG_CMD_AML_MTEST 1
+#endif
+#if defined(CONFIG_CMD_AML_MTEST)
+#if !defined(CONFIG_SYS_MEM_TOP_HIDE)
+#error CONFIG_CMD_AML_MTEST depends on CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+#if !(CONFIG_SYS_MEM_TOP_HIDE)
+#error CONFIG_SYS_MEM_TOP_HIDE should not be zero;
+#endif
+#endif
+
+#endif
+
diff --git a/board/amlogic/configs/s4_ap201.h b/board/amlogic/configs/s4_ap201.h
new file mode 100644
index 0000000..9514b78
--- /dev/null
+++ b/board/amlogic/configs/s4_ap201.h
@@ -0,0 +1,506 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 799 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*if disable uboot console, enable it*/
+//#define CONFIG_SILENT_CONSOLE
+#ifdef CONFIG_SILENT_CONSOLE
+#undef CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC
+#endif
+
+/*low console baudrate*/
+#define CONFIG_LOW_CONSOLE_BAUD 0
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#ifndef CONFIG_PXP_DDR
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif// #ifndef CONFIG_PXP_DDR
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb ${boot_part} ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x03080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "hdr_policy=0\0" \
+ "usb_burning=" CONFIG_USB_TOOL_ENTRY "\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "loglevel=8\0" \
+ "lock=10101000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "vendor_boot_part=vendor_boot\0"\
+ "board=ap201\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init " CONFIG_KNL_LOG_LEVEL "console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe07a000 "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "hdr_policy=${hdr_policy} hdr_priority=${hdr_priority} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot 0;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "get_system_as_root_mode;"\
+ "echo system_mode in storeboot: ${system_mode};"\
+ "get_avb_mode;"\
+ "echo active_slot in storeboot: ${active_slot};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+ "if test ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else "\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "if test ${partiton_mode} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv loadaddr_kernel 0x3080000;"\
+ "setenv dtb_mem_addr 0x1000000;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "echo ab mode, read dtb from kernel;"\
+ "setenv common_dtb_load ""imgread dtb ${boot_part} ${dtb_mem_addr}"";"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "get_rebootmode;"\
+ "echo reboot_mode:::: ${reboot_mode};"\
+ "if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "hdmitx hpd;hdmitx get_preferred_mode;hdmitx get_parse_edid;setenv dolby_status 0;setenv dolby_vision_on 0;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};vpp hdrpkt;"\
+ "fi;fi;"\
+ "\0"\
+ "storage_param="\
+ "store param;"\
+ "setenv bootargs ${bootargs} ${mtdbootparts}; "\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "factory_provision init;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#ifndef CONFIG_PXP_DDR
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+#else
+#define CONFIG_PREBOOT "echo preboot"
+#endif
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (96*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+/* #define CONFIG_CMD_PLLTEST 1 */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+#define CONFIG_FAT_WRITE 1
+#define CONFIG_AML_FACTORY_PROVISION 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */
+#define CONFIG_UPDATE_MMU_TABLE
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
diff --git a/board/amlogic/configs/s4_ap222.h b/board/amlogic/configs/s4_ap222.h
new file mode 100644
index 0000000..e5e5ca6
--- /dev/null
+++ b/board/amlogic/configs/s4_ap222.h
@@ -0,0 +1,506 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 799 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*if disable uboot console, enable it*/
+//#define CONFIG_SILENT_CONSOLE
+#ifdef CONFIG_SILENT_CONSOLE
+#undef CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC
+#endif
+
+/*low console baudrate*/
+#define CONFIG_LOW_CONSOLE_BAUD 0
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#ifndef CONFIG_PXP_DDR
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif// #ifndef CONFIG_PXP_DDR
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb ${boot_part} ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x03080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "hdr_policy=0\0" \
+ "usb_burning=" CONFIG_USB_TOOL_ENTRY "\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "loglevel=8\0" \
+ "lock=10101000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "vendor_boot_part=vendor_boot\0"\
+ "board=oppen\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init " CONFIG_KNL_LOG_LEVEL "console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe07a000 "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "hdr_policy=${hdr_policy} hdr_priority=${hdr_priority} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot 0;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "get_system_as_root_mode;"\
+ "echo system_mode in storeboot: ${system_mode};"\
+ "get_avb_mode;"\
+ "echo active_slot in storeboot: ${active_slot};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+ "if test ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else "\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "if test ${partiton_mode} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv loadaddr_kernel 0x3080000;"\
+ "setenv dtb_mem_addr 0x1000000;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "echo ab mode, read dtb from kernel;"\
+ "setenv common_dtb_load ""imgread dtb ${boot_part} ${dtb_mem_addr}"";"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "get_rebootmode;"\
+ "echo reboot_mode:::: ${reboot_mode};"\
+ "if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "hdmitx hpd;hdmitx get_preferred_mode;hdmitx get_parse_edid;setenv dolby_status 0;setenv dolby_vision_on 0;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};vpp hdrpkt;"\
+ "fi;fi;"\
+ "\0"\
+ "storage_param="\
+ "store param;"\
+ "setenv bootargs ${bootargs} ${mtdbootparts}; "\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "factory_provision init;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#ifndef CONFIG_PXP_DDR
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+#else
+#define CONFIG_PREBOOT "echo preboot"
+#endif
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (96*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+/* #define CONFIG_CMD_PLLTEST 1 */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+#define CONFIG_FAT_WRITE 1
+#define CONFIG_AML_FACTORY_PROVISION 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+#define CONFIG_CPU_ARMV8
+
+/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */
+#define CONFIG_UPDATE_MMU_TABLE
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
diff --git a/board/amlogic/configs/s4_ap229.h b/board/amlogic/configs/s4_ap229.h
new file mode 100644
index 0000000..3dab27e
--- /dev/null
+++ b/board/amlogic/configs/s4_ap229.h
@@ -0,0 +1,506 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 799 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*if disable uboot console, enable it*/
+//#define CONFIG_SILENT_CONSOLE
+#ifdef CONFIG_SILENT_CONSOLE
+#undef CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC
+#endif
+
+/*low console baudrate*/
+#define CONFIG_LOW_CONSOLE_BAUD 0
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#ifndef CONFIG_PXP_DDR
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif// #ifndef CONFIG_PXP_DDR
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb ${boot_part} ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x03080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "hdr_policy=0\0" \
+ "usb_burning=" CONFIG_USB_TOOL_ENTRY "\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "loglevel=8\0" \
+ "lock=10101000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "vendor_boot_part=vendor_boot\0"\
+ "board=s4_skt\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init " CONFIG_KNL_LOG_LEVEL "console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe07a000 "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "hdr_policy=${hdr_policy} hdr_priority=${hdr_priority} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot 0;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "get_system_as_root_mode;"\
+ "echo system_mode in storeboot: ${system_mode};"\
+ "get_avb_mode;"\
+ "echo active_slot in storeboot: ${active_slot};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+ "if test ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else "\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "if test ${partiton_mode} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv loadaddr_kernel 0x3080000;"\
+ "setenv dtb_mem_addr 0x1000000;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "echo ab mode, read dtb from kernel;"\
+ "setenv common_dtb_load ""imgread dtb ${boot_part} ${dtb_mem_addr}"";"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "get_rebootmode;"\
+ "echo reboot_mode:::: ${reboot_mode};"\
+ "if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "hdmitx hpd;hdmitx get_preferred_mode;hdmitx get_parse_edid;setenv dolby_status 0;setenv dolby_vision_on 0;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};vpp hdrpkt;"\
+ "fi;fi;"\
+ "\0"\
+ "storage_param="\
+ "store param;"\
+ "setenv bootargs ${bootargs} ${mtdbootparts}; "\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "factory_provision init;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#ifndef CONFIG_PXP_DDR
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+#else
+#define CONFIG_PREBOOT "echo preboot"
+#endif
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (96*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+#define CONFIG_CMD_PLLTEST 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+#define CONFIG_FAT_WRITE 1
+#define CONFIG_AML_FACTORY_PROVISION 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+#define CONFIG_CPU_ARMV8
+
+/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */
+#define CONFIG_UPDATE_MMU_TABLE
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
diff --git a/board/amlogic/configs/s4_aq222.h b/board/amlogic/configs/s4_aq222.h
new file mode 100644
index 0000000..aee9049
--- /dev/null
+++ b/board/amlogic/configs/s4_aq222.h
@@ -0,0 +1,506 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 799 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*if disable uboot console, enable it*/
+//#define CONFIG_SILENT_CONSOLE
+#ifdef CONFIG_SILENT_CONSOLE
+#undef CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC
+#endif
+
+/*low console baudrate*/
+#define CONFIG_LOW_CONSOLE_BAUD 0
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#ifndef CONFIG_PXP_DDR
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif// #ifndef CONFIG_PXP_DDR
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb ${boot_part} ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x03080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "hdr_policy=0\0" \
+ "usb_burning=" CONFIG_USB_TOOL_ENTRY "\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "loglevel=8\0" \
+ "lock=10101000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "vendor_boot_part=vendor_boot\0"\
+ "board=planck\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init " CONFIG_KNL_LOG_LEVEL "console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe07a000 "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "hdr_policy=${hdr_policy} hdr_priority=${hdr_priority} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot 0;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "get_system_as_root_mode;"\
+ "echo system_mode in storeboot: ${system_mode};"\
+ "get_avb_mode;"\
+ "echo active_slot in storeboot: ${active_slot};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+ "if test ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else "\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "if test ${partiton_mode} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv loadaddr_kernel 0x3080000;"\
+ "setenv dtb_mem_addr 0x1000000;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "echo ab mode, read dtb from kernel;"\
+ "setenv common_dtb_load ""imgread dtb ${boot_part} ${dtb_mem_addr}"";"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "get_rebootmode;"\
+ "echo reboot_mode:::: ${reboot_mode};"\
+ "if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "hdmitx hpd;hdmitx get_preferred_mode;hdmitx get_parse_edid;setenv dolby_status 0;setenv dolby_vision_on 0;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};vpp hdrpkt;"\
+ "fi;fi;"\
+ "\0"\
+ "storage_param="\
+ "store param;"\
+ "setenv bootargs ${bootargs} ${mtdbootparts}; "\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "factory_provision init;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#ifndef CONFIG_PXP_DDR
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+#else
+#define CONFIG_PREBOOT "echo preboot"
+#endif
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (96*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 5
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+/* #define CONFIG_CMD_PLLTEST 1 */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+#define CONFIG_FAT_WRITE 1
+#define CONFIG_AML_FACTORY_PROVISION 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+#define CONFIG_CPU_ARMV8
+
+/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */
+#define CONFIG_UPDATE_MMU_TABLE
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
diff --git a/board/amlogic/configs/s4_aq229.h b/board/amlogic/configs/s4_aq229.h
new file mode 100644
index 0000000..3502c2e
--- /dev/null
+++ b/board/amlogic/configs/s4_aq229.h
@@ -0,0 +1,506 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 799 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*if disable uboot console, enable it*/
+//#define CONFIG_SILENT_CONSOLE
+#ifdef CONFIG_SILENT_CONSOLE
+#undef CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC
+#endif
+
+/*low console baudrate*/
+#define CONFIG_LOW_CONSOLE_BAUD 0
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#ifndef CONFIG_PXP_DDR
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif// #ifndef CONFIG_PXP_DDR
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb ${boot_part} ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x03080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "hdr_policy=0\0" \
+ "usb_burning=" CONFIG_USB_TOOL_ENTRY "\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "loglevel=8\0" \
+ "lock=10101000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "vendor_boot_part=vendor_boot\0"\
+ "board=s4x2_skt\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init " CONFIG_KNL_LOG_LEVEL "console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe07a000 "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "hdr_policy=${hdr_policy} hdr_priority=${hdr_priority} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot 0;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "get_system_as_root_mode;"\
+ "echo system_mode in storeboot: ${system_mode};"\
+ "get_avb_mode;"\
+ "echo active_slot in storeboot: ${active_slot};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+ "if test ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else "\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "if test ${partiton_mode} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv loadaddr_kernel 0x3080000;"\
+ "setenv dtb_mem_addr 0x1000000;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "echo ab mode, read dtb from kernel;"\
+ "setenv common_dtb_load ""imgread dtb ${boot_part} ${dtb_mem_addr}"";"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "get_rebootmode;"\
+ "echo reboot_mode:::: ${reboot_mode};"\
+ "if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "hdmitx hpd;hdmitx get_preferred_mode;hdmitx get_parse_edid;setenv dolby_status 0;setenv dolby_vision_on 0;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};vpp hdrpkt;"\
+ "fi;fi;"\
+ "\0"\
+ "storage_param="\
+ "store param;"\
+ "setenv bootargs ${bootargs} ${mtdbootparts}; "\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "factory_provision init;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#ifndef CONFIG_PXP_DDR
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+#else
+#define CONFIG_PREBOOT "echo preboot"
+#endif
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (96*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 5
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+#define CONFIG_CMD_PLLTEST 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+#define CONFIG_FAT_WRITE 1
+#define CONFIG_AML_FACTORY_PROVISION 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */
+#define CONFIG_UPDATE_MMU_TABLE
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
diff --git a/board/amlogic/configs/s4_skt.h b/board/amlogic/configs/s4_skt.h
new file mode 100644
index 0000000..84200a2
--- /dev/null
+++ b/board/amlogic/configs/s4_skt.h
@@ -0,0 +1,498 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 799 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*low console baudrate*/
+#define CONFIG_LOW_CONSOLE_BAUD 0
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+//#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x03080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "hdr_policy=0\0" \
+ "usb_burning=adnl 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "vendor_boot_part=vendor_boot\0"\
+ "board=ohm\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xfe002000"\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "hdr_policy=${hdr_policy} hdr_priority=${hdr_priority} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "get_system_as_root_mode;"\
+ "echo system_mode in storeboot: ${system_mode};"\
+ "get_avb_mode;"\
+ "echo active_slot in storeboot: ${active_slot};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "echo come to vendor_boot true;"\
+ "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "fi;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+ "if test ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else "\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "if test ${partiton_mode} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv loadaddr_kernel 0x3080000;"\
+ "setenv dtb_mem_addr 0x1000000;"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "get_rebootmode;"\
+ "echo reboot_mode:::: ${reboot_mode};"\
+ "if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "hdmitx hpd;hdmitx get_preferred_mode;hdmitx get_parse_edid;setenv dolby_status 0;setenv dolby_vision_on 0;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};vpp hdrpkt;"\
+ "fi;fi;"\
+ "\0"\
+ "storage_param="\
+ "store param;"\
+ "setenv bootargs ${bootargs} ${mtdbootparts}; "\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "factory_provision init;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#if 0
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+#else
+#define CONFIG_PREBOOT "echo preboot"
+#endif
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (64*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+/* #define CONFIG_CMD_PLLTEST 1 */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+#define CONFIG_FAT_WRITE 1
+#define CONFIG_AML_FACTORY_PROVISION 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+#define CONFIG_CPU_ARMV8
+
+/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */
+#define CONFIG_UPDATE_MMU_TABLE
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
diff --git a/board/amlogic/configs/s4_t211.h b/board/amlogic/configs/s4_t211.h
new file mode 100644
index 0000000..d535864
--- /dev/null
+++ b/board/amlogic/configs/s4_t211.h
@@ -0,0 +1,358 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 799 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+
+/*y_led brightness val*/
+#define YELLOW_LED_VAL 0x00090013
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*low console baudrate*/
+#define CONFIG_LOW_CONSOLE_BAUD 0
+
+#define CONFIG_VENDOR_NAME "Google"
+#define CONFIG_PRODUCT_NAME "Chromecast HD"
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb ${boot_part} ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+#define CONFIG_VIDEO_BMP_GZIP
+#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE (2 << 20)
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x03080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=dummy_l\0" \
+ "hdmitx_hpd_wait_ms=0\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "fstab_suffix=f2fs\0" \
+ "hdr_policy=1\0" \
+ "usb_burning=adnl 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "lock=10101000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "vendor_boot_part=vendor_boot\0"\
+ "board=boreal\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init "\
+ "loop.max_part=4 "\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${consoleargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "hdr_policy=${hdr_policy} hdr_priority=${hdr_priority} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "setenv bootargs ${bootargs} " \
+ "androidboot.board_variant=${board_variant} " \
+ "androidboot.fstab_suffix=${fstab_suffix} " \
+ "androidboot.serialno=${serial#} " \
+ "mac_wifi=${mac_wifi} " \
+ "androidboot.mac_wifi=${mac_wifi} " \
+ "mac_bt=${mac_bt} " \
+ "androidboot.mac_bt=${mac_bt} " \
+ "androidboot.hardware.sku=${sku} " \
+ "androidboot.wificountrycode=${region_code} " \
+ "androidboot.oem.locales=${locales} "\
+ "androidboot.oem.key1=ATV00100022-${sku};" \
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot 0;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "if gpio input GPIOD_10; then "\
+ "echo FDR button pressed;"\
+ /* Try to boot RMA image first, then the recovery */\
+ "run boot_rma;"\
+ "run recovery_from_flash;"\
+ "fi;"\
+ "bcb uboot-command;"\
+ "run switch_bootmode;"\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "get_system_as_root_mode;"\
+ "echo system_mode in storeboot: ${system_mode};"\
+ "get_avb_mode;"\
+ "echo active_slot in storeboot: ${active_slot};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv loadaddr_kernel 0x3080000;"\
+ "setenv dtb_mem_addr 0x1000000;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "echo ab mode, read dtb from kernel;"\
+ "setenv common_dtb_load ""imgread dtb ${boot_part} ${dtb_mem_addr}"";"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "get_rebootmode;"\
+ "echo reboot_mode:::: ${reboot_mode};"\
+ "if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "setenv outputmode dummy_l;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "setenv outputmode dummy_l;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "hdmitx hpd;hdmitx get_preferred_mode;hdmitx get_parse_edid;setenv dolby_status 0;setenv dolby_vision_on 0;osd open;osd clear;bmp display $logo_addr;bmp scale;vout output ${outputmode};vpp hdrpkt;"\
+ "fi;fi;"\
+ "\0"\
+ "storage_param="\
+ "store param;"\
+ "setenv bootargs ${bootargs} ${mtdbootparts}; "\
+ "\0"\
+ "boot_rma="\
+ "if test ${active_slot} = _a; then "\
+ "setenv rma_slot _b; "\
+ "else "\
+ "setenv rma_slot _a; "\
+ "fi; "\
+ "tcpc start; "\
+ "usb start; "\
+ "if size usb 0 boot.img && "\
+ " itest ${filesize} <= 0x4000000 && "\
+ " load usb 0 ${loadaddr} boot.img ${filesize} && "\
+ " store write ${loadaddr} boot${rma_slot} 0 ${filesize} && "\
+ " size usb 0 vendor_boot.img && "\
+ " itest ${filesize} <= 0x4000000 && "\
+ " load usb 0 ${loadaddr} vendor_boot.img ${filesize} && "\
+ " store write ${loadaddr} vendor_boot${rma_slot} 0 ${filesize} && "\
+ " size usb 0 dtbo.img && "\
+ " itest ${filesize} <= 0x200000 && "\
+ " load usb 0 ${loadaddr} dtbo.img ${filesize} && "\
+ " store write ${loadaddr} dtbo${rma_slot} 0 ${filesize} && "\
+ " size usb 0 vbmeta_system.img && "\
+ " itest ${filesize} <= 0x100000 && "\
+ " load usb 0 ${loadaddr} vbmeta_system.img ${filesize} && "\
+ " store write ${loadaddr} vbmeta_system${rma_slot} 0 ${filesize} && "\
+ " size usb 0 vbmeta.img && "\
+ " itest ${filesize} <= 0x100000 && "\
+ " load usb 0 ${loadaddr} vbmeta.img ${filesize} && "\
+ " store write ${loadaddr} vbmeta${rma_slot} 0 ${filesize}; then "\
+ "setenv active_slot ${rma_slot}; "\
+ "setenv boot_part boot${rma_slot}; "\
+ "setenv vendor_boot_part vendor_boot${rma_slot}; "\
+ "if test ${rma_slot} = _a; then "\
+ "setenv slot-suffixes 0; "\
+ "else "\
+ "setenv slot-suffixes 1; "\
+ "fi; "\
+ "setenv use_external_avb_key 1; "\
+ "setenv bootargs ${bootargs} androidboot.rma=true; "\
+ "run recovery_from_flash; "\
+ "fi; "\
+ "\0"
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run init_display;"\
+ "run storeargs;"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* cpu */
+#define CONFIG_CPU_CLK 1704 //MHz. Range: 100-1800 should be multiple of 24
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (192*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+#define CONFIG_CPU_ARMV8
+
+/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */
+#define CONFIG_UPDATE_MMU_TABLE
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
+/* AVB KEYS USED */
+// TODO(b/206911824): remove default flag in production
+#define CONFIG_AVB2_KPUB_DEFAULT
+#define CONFIG_AVB2_KPUB_VENDOR_MULTIPLE
diff --git a/board/amlogic/configs/sc2_ah212.h b/board/amlogic/configs/sc2_ah212.h
new file mode 100644
index 0000000..f16de44
--- /dev/null
+++ b/board/amlogic/configs/sc2_ah212.h
@@ -0,0 +1,507 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 810 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*if disable uboot console, enable it*/
+//#define CONFIG_SILENT_CONSOLE
+#ifdef CONFIG_SILENT_CONSOLE
+#undef CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC
+#endif
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb ${boot_part} ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x03080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "colorattribute=444,8bit\0"\
+ "cvbsmode=576cvbs\0" \
+ "vout_init=disable\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "hdmichecksum=0x00000000\0" \
+ "dolby_status=0\0" \
+ "dolby_vision_on=0\0" \
+ "frac_rate_policy=1\0" \
+ "hdr_policy=0\0" \
+ "hdmi_read_edid=1\0" \
+ "usb_burning=" CONFIG_USB_TOOL_ENTRY "\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "lock=10101000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "vendor_boot_part=vendor_boot\0"\
+ "board=ohm\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init" CONFIG_KNL_LOG_LEVEL "console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe07a000 "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run init_display;run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run init_display;run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},${vout_init} panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} " \
+ "hdr_policy=${hdr_policy} hdr_priority=${hdr_priority} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot 0;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "run storage_param;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "get_system_as_root_mode;"\
+ "echo system_mode in storeboot: ${system_mode};"\
+ "get_avb_mode;"\
+ "echo active_slot in storeboot: ${active_slot};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+ "if test ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else "\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "if test ${partiton_mode} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv loadaddr_kernel 0x3080000;"\
+ "setenv dtb_mem_addr 0x1000000;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "echo ab mode, read dtb from kernel;"\
+ "setenv common_dtb_load ""imgread dtb ${boot_part} ${dtb_mem_addr}"";"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "get_rebootmode;"\
+ "echo reboot_mode:::: ${reboot_mode};"\
+ "if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "hdmitx hpd;hdmitx get_preferred_mode;hdmitx get_parse_edid;setenv dolby_status 0;setenv dolby_vision_on 0;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};vpp hdrpkt;"\
+ "fi;fi;"\
+ "\0"\
+ "storage_param="\
+ "store param;"\
+ "setenv bootargs ${bootargs} ${mtdbootparts}; "\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "factory_provision init;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#if 1
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+#else
+#define CONFIG_PREBOOT "echo preboot"
+#endif
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (96*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+#define CONFIG_CMD_NET 1
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */
+//#define CONFIG_UPDATE_MMU_TABLE
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+#define CONFIG_CMD_STARTDSP
+
+//use hardware sha2
+//#define CONFIG_AML_HW_SHA2
+
+#define CONFIG_MULTI_DTB 1
+#define CONFIG_AUTO_ADAPT_DDR_DTB 1
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
diff --git a/board/amlogic/configs/sc2_ah212_ddr3.h b/board/amlogic/configs/sc2_ah212_ddr3.h
new file mode 100644
index 0000000..d456612
--- /dev/null
+++ b/board/amlogic/configs/sc2_ah212_ddr3.h
@@ -0,0 +1,508 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 810 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*if disable uboot console, enable it*/
+//#define CONFIG_SILENT_CONSOLE
+#ifdef CONFIG_SILENT_CONSOLE
+#undef CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC
+#endif
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb ${boot_part} ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x03080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "colorattribute=444,8bit\0"\
+ "cvbsmode=576cvbs\0" \
+ "vout_init=disable\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "hdmichecksum=0x00000000\0" \
+ "dolby_status=0\0" \
+ "dolby_vision_on=0\0" \
+ "frac_rate_policy=1\0" \
+ "hdr_policy=0\0" \
+ "hdmi_read_edid=1\0" \
+ "usb_burning=" CONFIG_USB_TOOL_ENTRY "\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "lock=10101000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "vendor_boot_part=vendor_boot\0"\
+ "board=ohm\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init" CONFIG_KNL_LOG_LEVEL "console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe07a000 "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run init_display;run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run init_display;run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},${vout_init} panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} " \
+ "hdr_policy=${hdr_policy} hdr_priority=${hdr_priority} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot 0;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "run storage_param;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "get_system_as_root_mode;"\
+ "echo system_mode in storeboot: ${system_mode};"\
+ "get_avb_mode;"\
+ "echo active_slot in storeboot: ${active_slot};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+ "if test ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else "\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "if test ${partiton_mode} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv loadaddr_kernel 0x3080000;"\
+ "setenv dtb_mem_addr 0x1000000;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "echo ab mode, read dtb from kernel;"\
+ "setenv common_dtb_load ""imgread dtb ${boot_part} ${dtb_mem_addr}"";"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "get_rebootmode;"\
+ "echo reboot_mode:::: ${reboot_mode};"\
+ "if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "hdmitx hpd;hdmitx get_preferred_mode;hdmitx get_parse_edid;setenv dolby_status 0;setenv dolby_vision_on 0;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};vpp hdrpkt;"\
+ "fi;fi;"\
+ "\0"\
+ "storage_param="\
+ "store param;"\
+ "setenv bootargs ${bootargs} ${mtdbootparts}; "\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "factory_provision init;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#if 1
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+#else
+#define CONFIG_PREBOOT "echo preboot"
+#endif
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (96*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+#define CONFIG_CMD_NET 1
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */
+//#define CONFIG_UPDATE_MMU_TABLE
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+#define CONFIG_CMD_STARTDSP
+
+//use hardware sha2
+//#define CONFIG_AML_HW_SHA2
+
+#define CONFIG_MULTI_DTB 1
+#define CONFIG_AUTO_ADAPT_DDR_DTB 1
+
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
diff --git a/board/amlogic/configs/sc2_ah212_lpddr3.h b/board/amlogic/configs/sc2_ah212_lpddr3.h
new file mode 100644
index 0000000..99ee44b
--- /dev/null
+++ b/board/amlogic/configs/sc2_ah212_lpddr3.h
@@ -0,0 +1,508 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 810 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*if disable uboot console, enable it*/
+//#define CONFIG_SILENT_CONSOLE
+#ifdef CONFIG_SILENT_CONSOLE
+#undef CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC
+#endif
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb ${boot_part} ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x03080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "colorattribute=444,8bit\0"\
+ "cvbsmode=576cvbs\0" \
+ "vout_init=disable\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "hdmichecksum=0x00000000\0" \
+ "dolby_status=0\0" \
+ "dolby_vision_on=0\0" \
+ "frac_rate_policy=1\0" \
+ "hdr_policy=0\0" \
+ "hdmi_read_edid=1\0" \
+ "usb_burning=adnl 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "lock=10101000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "vendor_boot_part=vendor_boot\0"\
+ "board=ohm\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe07a000 "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run init_display;run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run init_display;run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},${vout_init} panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} " \
+ "hdr_policy=${hdr_policy} hdr_priority=${hdr_priority} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot 0;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "run storage_param;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "get_system_as_root_mode;"\
+ "echo system_mode in storeboot: ${system_mode};"\
+ "get_avb_mode;"\
+ "echo active_slot in storeboot: ${active_slot};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+ "if test ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else "\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "if test ${partiton_mode} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv loadaddr_kernel 0x3080000;"\
+ "setenv dtb_mem_addr 0x1000000;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "echo ab mode, read dtb from kernel;"\
+ "setenv common_dtb_load ""imgread dtb ${boot_part} ${dtb_mem_addr}"";"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "get_rebootmode;"\
+ "echo reboot_mode:::: ${reboot_mode};"\
+ "if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "hdmitx hpd;hdmitx get_preferred_mode;hdmitx get_parse_edid;setenv dolby_status 0;setenv dolby_vision_on 0;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};vpp hdrpkt;"\
+ "fi;fi;"\
+ "\0"\
+ "storage_param="\
+ "store param;"\
+ "setenv bootargs ${bootargs} ${mtdbootparts}; "\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "factory_provision init;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#if 1
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+#else
+#define CONFIG_PREBOOT "echo preboot"
+#endif
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (96*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+#define CONFIG_CMD_NET 1
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */
+//#define CONFIG_UPDATE_MMU_TABLE
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+#define CONFIG_CMD_STARTDSP
+
+//use hardware sha2
+//#define CONFIG_AML_HW_SHA2
+
+#define CONFIG_MULTI_DTB 1
+#define CONFIG_AUTO_ADAPT_DDR_DTB 1
+
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
diff --git a/board/amlogic/configs/sc2_ah212_lpddr4.h b/board/amlogic/configs/sc2_ah212_lpddr4.h
new file mode 100644
index 0000000..d456612
--- /dev/null
+++ b/board/amlogic/configs/sc2_ah212_lpddr4.h
@@ -0,0 +1,508 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 810 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*if disable uboot console, enable it*/
+//#define CONFIG_SILENT_CONSOLE
+#ifdef CONFIG_SILENT_CONSOLE
+#undef CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC
+#endif
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb ${boot_part} ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x03080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "colorattribute=444,8bit\0"\
+ "cvbsmode=576cvbs\0" \
+ "vout_init=disable\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "hdmichecksum=0x00000000\0" \
+ "dolby_status=0\0" \
+ "dolby_vision_on=0\0" \
+ "frac_rate_policy=1\0" \
+ "hdr_policy=0\0" \
+ "hdmi_read_edid=1\0" \
+ "usb_burning=" CONFIG_USB_TOOL_ENTRY "\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "lock=10101000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "vendor_boot_part=vendor_boot\0"\
+ "board=ohm\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init" CONFIG_KNL_LOG_LEVEL "console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe07a000 "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run init_display;run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run init_display;run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},${vout_init} panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} " \
+ "hdr_policy=${hdr_policy} hdr_priority=${hdr_priority} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot 0;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "run storage_param;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "get_system_as_root_mode;"\
+ "echo system_mode in storeboot: ${system_mode};"\
+ "get_avb_mode;"\
+ "echo active_slot in storeboot: ${active_slot};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+ "if test ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else "\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "if test ${partiton_mode} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv loadaddr_kernel 0x3080000;"\
+ "setenv dtb_mem_addr 0x1000000;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "echo ab mode, read dtb from kernel;"\
+ "setenv common_dtb_load ""imgread dtb ${boot_part} ${dtb_mem_addr}"";"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "get_rebootmode;"\
+ "echo reboot_mode:::: ${reboot_mode};"\
+ "if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "hdmitx hpd;hdmitx get_preferred_mode;hdmitx get_parse_edid;setenv dolby_status 0;setenv dolby_vision_on 0;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};vpp hdrpkt;"\
+ "fi;fi;"\
+ "\0"\
+ "storage_param="\
+ "store param;"\
+ "setenv bootargs ${bootargs} ${mtdbootparts}; "\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "factory_provision init;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#if 1
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+#else
+#define CONFIG_PREBOOT "echo preboot"
+#endif
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (96*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+#define CONFIG_CMD_NET 1
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */
+//#define CONFIG_UPDATE_MMU_TABLE
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+#define CONFIG_CMD_STARTDSP
+
+//use hardware sha2
+//#define CONFIG_AML_HW_SHA2
+
+#define CONFIG_MULTI_DTB 1
+#define CONFIG_AUTO_ADAPT_DDR_DTB 1
+
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
diff --git a/board/amlogic/configs/sc2_ah219.h b/board/amlogic/configs/sc2_ah219.h
new file mode 100644
index 0000000..813ba52
--- /dev/null
+++ b/board/amlogic/configs/sc2_ah219.h
@@ -0,0 +1,499 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 810 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb ${boot_part} ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x03080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "colorattribute=444,8bit\0"\
+ "cvbsmode=576cvbs\0" \
+ "vout_init=disable\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "hdmichecksum=0x00000000\0" \
+ "dolby_status=0\0" \
+ "dolby_vision_on=0\0" \
+ "frac_rate_policy=1\0" \
+ "hdr_policy=0\0" \
+ "hdmi_read_edid=1\0" \
+ "usb_burning=" CONFIG_USB_TOOL_ENTRY "\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "lock=10101000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "vendor_boot_part=vendor_boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init" CONFIG_KNL_LOG_LEVEL "console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe07a000 "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run init_display;run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run init_display;run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},${vout_init} panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} " \
+ "hdr_policy=${hdr_policy} hdr_priority=${hdr_priority} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot 0;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "run storage_param;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "get_system_as_root_mode;"\
+ "echo system_mode in storeboot: ${system_mode};"\
+ "get_avb_mode;"\
+ "echo active_slot in storeboot: ${active_slot};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+ "if test ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else "\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "if test ${partiton_mode} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv loadaddr_kernel 0x3080000;"\
+ "setenv dtb_mem_addr 0x1000000;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "echo ab mode, read dtb from kernel;"\
+ "setenv common_dtb_load ""imgread dtb ${boot_part} ${dtb_mem_addr}"";"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "get_rebootmode;"\
+ "echo reboot_mode:::: ${reboot_mode};"\
+ "if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "hdmitx hpd;hdmitx get_preferred_mode;hdmitx get_parse_edid;setenv dolby_status 0;setenv dolby_vision_on 0;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};vpp hdrpkt;"\
+ "fi;fi;"\
+ "\0"\
+ "storage_param="\
+ "store param;"\
+ "setenv bootargs ${bootargs} ${mtdbootparts}; "\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "factory_provision init;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#if 1
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+#else
+#define CONFIG_PREBOOT "echo preboot"
+#endif
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (96*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+#define CONFIG_CMD_NET 1
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+#define CONFIG_CMD_PLLTEST 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+#define CONFIG_CMD_STARTDSP
+
+//use hardware sha2
+//#define CONFIG_AML_HW_SHA2
+
+#define CONFIG_MULTI_DTB 1
+/*#define CONFIG_AUTO_ADAPT_DDR_DTB 1 */
+
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
diff --git a/board/amlogic/configs/sc2_ah232.h b/board/amlogic/configs/sc2_ah232.h
new file mode 100644
index 0000000..aecd249
--- /dev/null
+++ b/board/amlogic/configs/sc2_ah232.h
@@ -0,0 +1,512 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 810 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*if disable uboot console, enable it*/
+//#define CONFIG_SILENT_CONSOLE
+#ifdef CONFIG_SILENT_CONSOLE
+#undef CONFIG_SILENT_CONSOLE_UPDATE_ON_RELOC
+#endif
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb ${boot_part} ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x03080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "colorattribute=444,8bit\0"\
+ "cvbsmode=576cvbs\0" \
+ "vout_init=disable\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "hdmichecksum=0x00000000\0" \
+ "dolby_status=0\0" \
+ "dolby_vision_on=0\0" \
+ "frac_rate_policy=1\0" \
+ "hdr_policy=0\0" \
+ "hdmi_read_edid=1\0" \
+ "usb_burning=" CONFIG_USB_TOOL_ENTRY "\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "lock=10101000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "vendor_boot_part=vendor_boot\0"\
+ "board=ohm\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init" CONFIG_KNL_LOG_LEVEL "console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe07a000 "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run init_display;run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run init_display;run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},${vout_init} panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "hdmichecksum=${hdmichecksum} dolby_vision_on=${dolby_vision_on} " \
+ "hdr_policy=${hdr_policy} hdr_priority=${hdr_priority} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot 0;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "run storage_param;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "get_system_as_root_mode;"\
+ "echo system_mode in storeboot: ${system_mode};"\
+ "get_avb_mode;"\
+ "echo active_slot in storeboot: ${active_slot};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "echo come to vendor_boot true;"\
+ "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "fi;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset};"\
+ "if test ${upgrade_step} == 3; then "\
+ "if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;"\
+ "if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; wipeisb; bootm ${loadaddr}; fi;"\
+ "else "\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "if test ${partiton_mode} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv loadaddr_kernel 0x3080000;"\
+ "setenv dtb_mem_addr 0x1000000;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "echo ab mode, read dtb from kernel;"\
+ "setenv common_dtb_load ""imgread dtb ${boot_part} ${dtb_mem_addr}"";"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "get_rebootmode;"\
+ "echo reboot_mode:::: ${reboot_mode};"\
+ "if test ${reboot_mode} = quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv reboot_mode_android ""quiescent"";"\
+ "setenv dolby_status 0;"\
+ "setenv dolby_vision_on 0;"\
+ "run storeargs;"\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "osd open;osd clear;"\
+ "else "\
+ "setenv reboot_mode_android ""normal"";"\
+ "run storeargs;"\
+ "hdmitx hpd;hdmitx get_preferred_mode;hdmitx get_parse_edid;setenv dolby_status 0;setenv dolby_vision_on 0;osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode};vpp hdrpkt;"\
+ "fi;fi;"\
+ "\0"\
+ "storage_param="\
+ "store param;"\
+ "setenv bootargs ${bootargs} ${mtdbootparts}; "\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "factory_provision init;"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#if 1
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "bcb uboot-command;"\
+ "run switch_bootmode;"
+#else
+#define CONFIG_PREBOOT "echo preboot"
+#endif
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (96*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+#define CONFIG_CMD_NET 1
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */
+//#define CONFIG_UPDATE_MMU_TABLE
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+#define CONFIG_CMD_STARTDSP
+
+//use hardware sha2
+//#define CONFIG_AML_HW_SHA2
+
+#define CONFIG_MULTI_DTB 1
+#define CONFIG_AUTO_ADAPT_DDR_DTB 1
+
+
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#endif
+
diff --git a/board/amlogic/configs/sc2_skt.h b/board/amlogic/configs/sc2_skt.h
new file mode 100644
index 0000000..334818b
--- /dev/null
+++ b/board/amlogic/configs/sc2_skt.h
@@ -0,0 +1,418 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 810 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#if 0
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x03080000\0"\
+ "otg_device=1\0" \
+ "panel_type=lcd_1\0" \
+ "outputmode=1080p60hz\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=adnl 1000\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "boot_part=boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xfe002000"\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 loop.max_part=4 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "run storage_param;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "storage_param="\
+ "store param;"\
+ "setenv bootargs ${bootargs} ${mtdbootparts}; "\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#if 0
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run storeargs;"\
+ "run upgrade_key;"
+#else
+#define CONFIG_PREBOOT "echo preboot"
+#endif
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (64*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+/* #define CONFIG_CMD_NET 1 */
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+#define CONFIG_CMD_PLLTEST 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+#define CONFIG_CMD_STARTDSP
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+/* #define CONFIG_MULTI_DTB 1 */
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
diff --git a/board/amlogic/configs/t7_an400_lpddr4x.h b/board/amlogic/configs/t7_an400_lpddr4x.h
new file mode 100644
index 0000000..0c594a5
--- /dev/null
+++ b/board/amlogic/configs/t7_an400_lpddr4x.h
@@ -0,0 +1,479 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_A_INIT_VOLTAGE 889 // VCCK A power up voltage
+#define AML_VCCK_B_INIT_VOLTAGE 889 // VCCK B power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 831 // VDDEE power up voltage
+#define AML_VDDGPU_INIT_VOLTAGE 831 // VDDGPU power up voltage
+#define AML_VDDNPU_INIT_VOLTAGE 831 // VDDNPU power up voltage
+#define AML_VDDDDR_INIT_VOLTAGE 831 // VDDDDR power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#if 0
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*low console baudrate*/
+#define CONFIG_LOW_CONSOLE_BAUD 0
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+//#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x01080000\0"\
+ "otg_device=1\0" \
+ "panel_type=vbyone_0\0" \
+ "panel1_type=vbyone_0\0" \
+ "panel2_type=lvds_1\0" \
+ "lcd_ctrl=0x00000000\0" \
+ "lcd1_ctrl=0x00000000\0" \
+ "lcd2_ctrl=0x00000000\0" \
+ "lcd_debug=0x00000000\0" \
+ "outputmode=panel2\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=" CONFIG_USB_TOOL_ENTRY "\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=permissive\0" \
+ "recovery_part=recovery\0"\
+ "lock=10101000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "vendor_boot_part=vendor_boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init" CONFIG_KNL_LOG_LEVEL "console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe078000 "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run init_display;run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run init_display;run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable "\
+ "panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} lcd_debug=${lcd_debug} "\
+ "panel1_type=${panel1_type} lcd1_ctrl=${lcd1_ctrl} panel2_type=${panel2_type} lcd2_ctrl=${lcd2_ctrl} "\
+ "hdmimode=${hdmimode} outputmode=${outputmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "echo reboot_mode : ${reboot_mode};"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot 1;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "get_system_as_root_mode;"\
+ "echo system_mode in storeboot: ${system_mode};"\
+ "get_avb_mode;"\
+ "echo active_slot in storeboot: ${active_slot};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "if test ${partiton_mode} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv loadaddr_kernel 0x2080000;"\
+ "setenv dtb_mem_addr 0x1f00000;"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "bcb uboot-command;" \
+ "run switch_bootmode;"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (64*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+/* LCD */
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+#define AML_T7_DISPLAY
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+#define CONFIG_CMD_NET 1
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+#define CONFIG_CMD_PLLTEST 1
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use startdsp command
+#define CONFIG_CMD_STARTDSP
+
+//use dache command
+#define CONFIG_CMD_CACHE
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+#define CONFIG_MULTI_DTB 1
+
+/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */
+#define CONFIG_UPDATE_MMU_TABLE
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
diff --git a/board/amlogic/configs/t7_an400p_lpddr4x.h b/board/amlogic/configs/t7_an400p_lpddr4x.h
new file mode 100644
index 0000000..a81e4da
--- /dev/null
+++ b/board/amlogic/configs/t7_an400p_lpddr4x.h
@@ -0,0 +1,480 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ * voltage range define in board/amlogic/t7_an400p_lpddr4x/firmware/timing.c
+ */
+
+#define AML_VCCK_A_INIT_VOLTAGE 889 // VCCK A power up voltage
+#define AML_VCCK_B_INIT_VOLTAGE 940 // VCCK B power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 840 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#if 0
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*low console baudrate*/
+#define CONFIG_LOW_CONSOLE_BAUD 0
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+//#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x01080000\0"\
+ "otg_device=1\0" \
+ "panel_type=vbyone_0\0" \
+ "panel1_type=vbyone_0\0" \
+ "panel2_type=lvds_1\0" \
+ "lcd_ctrl=0x00000000\0" \
+ "lcd1_ctrl=0x00000000\0" \
+ "lcd2_ctrl=0x00000000\0" \
+ "lcd_debug=0x00000000\0" \
+ "outputmode=panel2\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=" CONFIG_USB_TOOL_ENTRY "\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=permissive\0" \
+ "recovery_part=recovery\0"\
+ "lock=10101000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "vendor_boot_part=vendor_boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init" CONFIG_KNL_LOG_LEVEL "console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe078000 "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run init_display;run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run init_display;run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable "\
+ "panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} lcd_debug=${lcd_debug} "\
+ "panel1_type=${panel1_type} lcd1_ctrl=${lcd1_ctrl} panel2_type=${panel2_type} lcd2_ctrl=${lcd2_ctrl} "\
+ "hdmimode=${hdmimode} outputmode=${outputmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "echo reboot_mode : ${reboot_mode};"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot 1;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "get_system_as_root_mode;"\
+ "echo system_mode in storeboot: ${system_mode};"\
+ "get_avb_mode;"\
+ "echo active_slot in storeboot: ${active_slot};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "if test ${partiton_mode} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv loadaddr_kernel 0x2080000;"\
+ "setenv dtb_mem_addr 0x1f00000;"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "bcb uboot-command;" \
+ "run switch_bootmode;"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (64*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+/* LCD */
+
+/*pmic bd71837*/
+#define CONFIG_PMIC_BD71837 1
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+#define AML_T7_DISPLAY
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+#define CONFIG_CMD_NET 1
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+/* #define CONFIG_CMD_PLLTEST 1 */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use startdsp command
+#define CONFIG_CMD_STARTDSP
+
+//use dache command
+#define CONFIG_CMD_CACHE
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+#define CONFIG_MULTI_DTB 1
+
+/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */
+#define CONFIG_UPDATE_MMU_TABLE
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
diff --git a/board/amlogic/configs/t7_an408_lpddr4x.h b/board/amlogic/configs/t7_an408_lpddr4x.h
new file mode 100644
index 0000000..d892604
--- /dev/null
+++ b/board/amlogic/configs/t7_an408_lpddr4x.h
@@ -0,0 +1,479 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_A_INIT_VOLTAGE 889 // VCCK A power up voltage
+#define AML_VCCK_B_INIT_VOLTAGE 889 // VCCK B power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 831 // VDDEE power up voltage
+#define AML_VDDGPU_INIT_VOLTAGE 831 // VDDGPU power up voltage
+#define AML_VDDNPU_INIT_VOLTAGE 831 // VDDNPU power up voltage
+#define AML_VDDDDR_INIT_VOLTAGE 831 // VDDDDR power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#if 0
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*low console baudrate*/
+#define CONFIG_LOW_CONSOLE_BAUD 0
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+//#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x01080000\0"\
+ "otg_device=1\0" \
+ "panel_type=vbyone_0\0" \
+ "panel1_type=vbyone_0\0" \
+ "panel2_type=lvds_1\0" \
+ "lcd_ctrl=0x00000000\0" \
+ "lcd1_ctrl=0x00000000\0" \
+ "lcd2_ctrl=0x00000000\0" \
+ "lcd_debug=0x00000000\0" \
+ "outputmode=panel2\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=" CONFIG_USB_TOOL_ENTRY "\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=permissive\0" \
+ "recovery_part=recovery\0"\
+ "lock=10101000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "vendor_boot_part=vendor_boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init" CONFIG_KNL_LOG_LEVEL "console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe078000 "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run init_display;run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run init_display;run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable "\
+ "panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} lcd_debug=${lcd_debug} "\
+ "panel1_type=${panel1_type} lcd1_ctrl=${lcd1_ctrl} panel2_type=${panel2_type} lcd2_ctrl=${lcd2_ctrl} "\
+ "hdmimode=${hdmimode} outputmode=${outputmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "echo reboot_mode : ${reboot_mode};"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot 1;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "get_system_as_root_mode;"\
+ "echo system_mode in storeboot: ${system_mode};"\
+ "get_avb_mode;"\
+ "echo active_slot in storeboot: ${active_slot};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "if test ${partiton_mode} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv loadaddr_kernel 0x2080000;"\
+ "setenv dtb_mem_addr 0x1f00000;"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "bcb uboot-command;" \
+ "run switch_bootmode;"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (64*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+/* LCD */
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+#define AML_T7_DISPLAY
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+#define CONFIG_CMD_NET 1
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+/* #define CONFIG_CMD_PLLTEST 1 */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use startdsp command
+#define CONFIG_CMD_STARTDSP
+
+//use dache command
+#define CONFIG_CMD_CACHE
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+#define CONFIG_MULTI_DTB 1
+
+/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */
+#define CONFIG_UPDATE_MMU_TABLE
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
diff --git a/board/amlogic/configs/t7_an409_ddr4.h b/board/amlogic/configs/t7_an409_ddr4.h
new file mode 100644
index 0000000..d892604
--- /dev/null
+++ b/board/amlogic/configs/t7_an409_ddr4.h
@@ -0,0 +1,479 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_A_INIT_VOLTAGE 889 // VCCK A power up voltage
+#define AML_VCCK_B_INIT_VOLTAGE 889 // VCCK B power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 831 // VDDEE power up voltage
+#define AML_VDDGPU_INIT_VOLTAGE 831 // VDDGPU power up voltage
+#define AML_VDDNPU_INIT_VOLTAGE 831 // VDDNPU power up voltage
+#define AML_VDDDDR_INIT_VOLTAGE 831 // VDDDDR power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#if 0
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*low console baudrate*/
+#define CONFIG_LOW_CONSOLE_BAUD 0
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+//#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x01080000\0"\
+ "otg_device=1\0" \
+ "panel_type=vbyone_0\0" \
+ "panel1_type=vbyone_0\0" \
+ "panel2_type=lvds_1\0" \
+ "lcd_ctrl=0x00000000\0" \
+ "lcd1_ctrl=0x00000000\0" \
+ "lcd2_ctrl=0x00000000\0" \
+ "lcd_debug=0x00000000\0" \
+ "outputmode=panel2\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=" CONFIG_USB_TOOL_ENTRY "\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=permissive\0" \
+ "recovery_part=recovery\0"\
+ "lock=10101000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "vendor_boot_part=vendor_boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init" CONFIG_KNL_LOG_LEVEL "console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe078000 "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run init_display;run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run init_display;run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable "\
+ "panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} lcd_debug=${lcd_debug} "\
+ "panel1_type=${panel1_type} lcd1_ctrl=${lcd1_ctrl} panel2_type=${panel2_type} lcd2_ctrl=${lcd2_ctrl} "\
+ "hdmimode=${hdmimode} outputmode=${outputmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "echo reboot_mode : ${reboot_mode};"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot 1;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "get_system_as_root_mode;"\
+ "echo system_mode in storeboot: ${system_mode};"\
+ "get_avb_mode;"\
+ "echo active_slot in storeboot: ${active_slot};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "if test ${partiton_mode} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv loadaddr_kernel 0x2080000;"\
+ "setenv dtb_mem_addr 0x1f00000;"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "bcb uboot-command;" \
+ "run switch_bootmode;"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (64*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+/* LCD */
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+#define AML_T7_DISPLAY
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+#define CONFIG_CMD_NET 1
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+/* #define CONFIG_CMD_PLLTEST 1 */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use startdsp command
+#define CONFIG_CMD_STARTDSP
+
+//use dache command
+#define CONFIG_CMD_CACHE
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+#define CONFIG_MULTI_DTB 1
+
+/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */
+#define CONFIG_UPDATE_MMU_TABLE
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
diff --git a/board/amlogic/configs/t7_an40a1.h b/board/amlogic/configs/t7_an40a1.h
new file mode 100644
index 0000000..2bbc4dd
--- /dev/null
+++ b/board/amlogic/configs/t7_an40a1.h
@@ -0,0 +1,479 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_A_INIT_VOLTAGE 889 // VCCK A power up voltage
+#define AML_VCCK_B_INIT_VOLTAGE 940 // VCCK B power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 840 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#if 0
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*low console baudrate*/
+#define CONFIG_LOW_CONSOLE_BAUD 0
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+//#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x01080000\0"\
+ "otg_device=1\0" \
+ "panel_type=vbyone_0\0" \
+ "panel1_type=vbyone_0\0" \
+ "panel2_type=lvds_1\0" \
+ "lcd_ctrl=0x00000000\0" \
+ "lcd1_ctrl=0x00000000\0" \
+ "lcd2_ctrl=0x00000000\0" \
+ "lcd_debug=0x00000000\0" \
+ "outputmode=panel2\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=" CONFIG_USB_TOOL_ENTRY "\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=permissive\0" \
+ "recovery_part=recovery\0"\
+ "lock=10101000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "vendor_boot_part=vendor_boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init" CONFIG_KNL_LOG_LEVEL "console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe078000 "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run init_display;run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run init_display;run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable "\
+ "panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} lcd_debug=${lcd_debug} "\
+ "panel1_type=${panel1_type} lcd1_ctrl=${lcd1_ctrl} panel2_type=${panel2_type} lcd2_ctrl=${lcd2_ctrl} "\
+ "hdmimode=${hdmimode} outputmode=${outputmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "echo reboot_mode : ${reboot_mode};"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot 1;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "get_system_as_root_mode;"\
+ "echo system_mode in storeboot: ${system_mode};"\
+ "get_avb_mode;"\
+ "echo active_slot in storeboot: ${active_slot};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "if test ${partiton_mode} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv loadaddr_kernel 0x2080000;"\
+ "setenv dtb_mem_addr 0x1f00000;"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "bcb uboot-command;" \
+ "run switch_bootmode;"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (64*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+/* LCD */
+
+/*pmic bd71837*/
+#define CONFIG_PMIC_BD71837 1
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+#define AML_T7_DISPLAY
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+#define CONFIG_CMD_NET 1
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+/* #define CONFIG_CMD_PLLTEST 1 */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use startdsp command
+#define CONFIG_CMD_STARTDSP
+
+//use dache command
+#define CONFIG_CMD_CACHE
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+#define CONFIG_MULTI_DTB 1
+
+/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */
+#define CONFIG_UPDATE_MMU_TABLE
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
diff --git a/board/amlogic/configs/t7_skt.h b/board/amlogic/configs/t7_skt.h
new file mode 100644
index 0000000..cbf7661
--- /dev/null
+++ b/board/amlogic/configs/t7_skt.h
@@ -0,0 +1,434 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_INIT_VOLTAGE 939 //VCCK power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#if 0
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*low console baudrate*/
+#define CONFIG_LOW_CONSOLE_BAUD 0
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+//#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x03080000\0"\
+ "otg_device=1\0" \
+ "panel_type=vbyone_0\0" \
+ "panel1_type=vbyone_0\0" \
+ "panel2_type=lvds_1\0" \
+ "lcd_debug_para=3\0" \
+ "lcd_ctrl=0x00000000\0" \
+ "lcd1_ctrl=0x00000000\0" \
+ "lcd2_ctrl=0x00000000\0" \
+ "lcd_debug=0x00000000\0" \
+ "outputmode=panel2\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=" CONFIG_USB_TOOL_ENTRY "\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=enforcing\0" \
+ "recovery_part=recovery\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "boot_part=boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init" CONFIG_KNL_LOG_LEVEL "console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xfe002000"\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} ${fs_type} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable "\
+ "panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} lcd_debug=${lcd_debug} "\
+ "panel1_type=${panel1_type} lcd1_ctrl=${lcd1_ctrl} panel2_type=${panel2_type} lcd2_ctrl=${lcd2_ctrl} "\
+ "hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} "\
+ "frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_valid_slot;"\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#if 0
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run storeargs;"\
+ "run upgrade_key;"
+#else
+#define CONFIG_PREBOOT "echo preboot"
+#endif
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (64*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+
+/* LCD */
+#define CONFIG_AML_LCD_PXP 1
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+#define AML_T7_DISPLAY
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+#define CONFIG_CMD_NET 1
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+/* #define CONFIG_CMD_PLLTEST 1 */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use startdsp command
+#define CONFIG_CMD_STARTDSP
+
+//use dache command
+#define CONFIG_CMD_CACHE
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+#define CONFIG_MULTI_DTB 1
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
diff --git a/board/amlogic/configs/t7_t319.h b/board/amlogic/configs/t7_t319.h
new file mode 100644
index 0000000..07776cb
--- /dev/null
+++ b/board/amlogic/configs/t7_t319.h
@@ -0,0 +1,474 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BOARD_CFG_H__
+#define __BOARD_CFG_H__
+
+#include <asm/arch/cpu.h>
+
+/*
+ * platform power init config
+ */
+
+#define AML_VCCK_A_INIT_VOLTAGE 889 // VCCK A power up voltage
+#define AML_VCCK_B_INIT_VOLTAGE 940 // VCCK B power up voltage
+#define AML_VDDEE_INIT_VOLTAGE 840 // VDDEE power up voltage
+
+/* SMP Definitinos */
+#define CPU_RELEASE_ADDR secondary_boot_func
+
+/* Bootloader Control Block function
+ That is used for recovery and the bootloader to talk to each other
+ */
+#if 0
+#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+#endif
+
+/* Serial config */
+#define CONFIG_CONS_INDEX 2
+#define CONFIG_BAUDRATE 115200
+
+/*low console baudrate*/
+#define CONFIG_LOW_CONSOLE_BAUD 0
+
+/* Enable ir remote wake up for bl30 */
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
+#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
+
+/*config the default parameters for adc power key*/
+#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
+#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
+
+//#define CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+#define CONFIG_DTB_LOAD "imgread dtb boot ${dtb_mem_addr}"
+#else
+#define CONFIG_DTB_LOAD "imgread dtb _aml_dtb ${dtb_mem_addr}"
+#endif//#ifdef CONFIG_DTB_BIND_KERNEL //load dtb from kernel, such as boot partition
+
+/* args/envs */
+#define CONFIG_SYS_MAXARGS 64
+#define CONFIG_EXTRA_ENV_SETTINGS \
+ "firstboot=1\0"\
+ "silent=1\0"\
+ "upgrade_step=0\0"\
+ "jtag=disable\0"\
+ "loadaddr=0x00020000\0"\
+ "os_ident_addr=0x00500000\0"\
+ "loadaddr_rtos=0x00001000\0"\
+ "loadaddr_kernel=0x01080000\0"\
+ "otg_device=1\0" \
+ "panel_type=edp_0\0" \
+ "lcd_ctrl=0x00000000\0" \
+ "lcd_debug=0x00000000\0" \
+ "outputmode=panel\0" \
+ "hdmimode=1080p60hz\0" \
+ "cvbsmode=576cvbs\0" \
+ "display_width=1920\0" \
+ "display_height=1080\0" \
+ "display_bpp=16\0" \
+ "display_color_index=16\0" \
+ "display_layer=osd0\0" \
+ "display_color_fg=0xffff\0" \
+ "display_color_bg=0\0" \
+ "dtb_mem_addr=0x01000000\0" \
+ "fb_addr=0x00300000\0" \
+ "fb_width=1920\0" \
+ "fb_height=1080\0" \
+ "frac_rate_policy=1\0" \
+ "usb_burning=" CONFIG_USB_TOOL_ENTRY "\0" \
+ "fdt_high=0x20000000\0"\
+ "sdcburncfg=aml_sdc_burn.ini\0"\
+ "EnableSelinux=permissive\0" \
+ "recovery_part=recovery\0"\
+ "lock=10101000\0"\
+ "recovery_offset=0\0"\
+ "cvbs_drv=0\0"\
+ "osd_reverse=0\0"\
+ "video_reverse=0\0"\
+ "active_slot=normal\0"\
+ "boot_part=boot\0"\
+ "vendor_boot_part=vendor_boot\0"\
+ "Irq_check_en=0\0"\
+ "common_dtb_load=" CONFIG_DTB_LOAD "\0"\
+ "get_os_type=if store read ${os_ident_addr} ${boot_part} 0 0x1000; then os_ident ${os_ident_addr}; fi\0"\
+ "fatload_dev=usb\0"\
+ "fs_type=""rootfstype=ramfs""\0"\
+ "initargs="\
+ "init=/init" CONFIG_KNL_LOG_LEVEL "console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe078000 "\
+ "ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
+ "\0"\
+ "upgrade_check="\
+ "echo recovery_status=${recovery_status};"\
+ "if itest.s \"${recovery_status}\" == \"in_progress\"; then "\
+ "run init_display;run storeargs; run recovery_from_flash;"\
+ "else fi;"\
+ "echo upgrade_step=${upgrade_step}; "\
+ "if itest ${upgrade_step} == 3; then run init_display;run storeargs; run update; fi;"\
+ "\0"\
+ "storeargs="\
+ "get_bootloaderversion;" \
+ "setenv bootargs ${initargs} otg_device=${otg_device} "\
+ "logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable "\
+ "panel_type=${panel_type} lcd_ctrl=${lcd_ctrl} lcd_debug=${lcd_debug} "\
+ "hdmimode=${hdmimode} outputmode=${outputmode} "\
+ "osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} "\
+ "androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
+ "setenv bootargs ${bootargs} androidboot.bootloader=${bootloader_version} androidboot.hardware=amlogic;"\
+ "run cmdline_keys;"\
+ "\0"\
+ "switch_bootmode="\
+ "get_rebootmode;"\
+ "echo reboot_mode : ${reboot_mode};"\
+ "if test ${reboot_mode} = factory_reset; then "\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = update; then "\
+ "run update;"\
+ "else if test ${reboot_mode} = quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "else if test ${reboot_mode} = recovery_quiescent; then "\
+ "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
+ "run recovery_from_flash;"\
+ "else if test ${reboot_mode} = cold_boot; then "\
+ "else if test ${reboot_mode} = fastboot; then "\
+ "fastboot 1;"\
+ "fi;fi;fi;fi;fi;fi;"\
+ "\0" \
+ "storeboot="\
+ "run get_os_type;"\
+ "if test ${os_type} = rtos; then "\
+ "setenv loadaddr ${loadaddr_rtos};"\
+ "store read ${loadaddr} ${boot_part} 0 0x400000;"\
+ "bootm ${loadaddr};"\
+ "else if test ${os_type} = kernel; then "\
+ "get_system_as_root_mode;"\
+ "echo system_mode in storeboot: ${system_mode};"\
+ "get_avb_mode;"\
+ "echo active_slot in storeboot: ${active_slot};"\
+ "if test ${system_mode} = 1; then "\
+ "setenv bootargs ${bootargs} ro rootwait skip_initramfs;"\
+ "else "\
+ "setenv bootargs ${bootargs} androidboot.force_normal_boot=1;"\
+ "fi;"\
+ "if test ${active_slot} != normal; then "\
+ "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
+ "fi;"\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else echo wrong OS format ${os_type}; fi;fi;"\
+ "echo try upgrade as booting failure; run update;"\
+ "\0" \
+ "update="\
+ /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
+ "run usb_burning; "\
+ "run recovery_from_sdcard;"\
+ "run recovery_from_udisk;"\
+ "run recovery_from_flash;"\
+ "\0"\
+ "recovery_from_fat_dev="\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
+ "if fatload ${fatload_dev} 0 ${loadaddr} recovery.img; then "\
+ "if fatload ${fatload_dev} 0 ${dtb_mem_addr} dtb.img; then echo ${fatload_dev} dtb.img loaded; fi;"\
+ "setenv bootargs ${bootargs} ${fs_type};"\
+ "bootm ${loadaddr};fi;"\
+ "\0"\
+ "recovery_from_udisk="\
+ "setenv fatload_dev usb;"\
+ "if usb start 0; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_sdcard="\
+ "setenv fatload_dev mmc;"\
+ "if mmcinfo; then run recovery_from_fat_dev; fi;"\
+ "\0"\
+ "recovery_from_flash="\
+ "echo active_slot: ${active_slot};"\
+ "setenv loadaddr ${loadaddr_kernel};"\
+ "if test ${active_slot} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
+ "if imgread dtb recovery ${dtb_mem_addr}; then "\
+ "else echo restore dtb; run common_dtb_load;"\
+ "fi;"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if fdt addr ${dtb_mem_addr}; then else echo retry common dtb; run common_dtb_load; fi;"\
+ "if test ${partiton_mode} = normal; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
+ "else "\
+ "setenv bootargs ${bootargs} ${fs_type} aml_dt=${aml_dt} recovery_part=${recovery_part} recovery_offset=${recovery_offset} androidboot.slot_suffix=${active_slot};"\
+ "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
+ "fi;"\
+ "fi;"\
+ "fi;"\
+ "\0"\
+ "bcb_cmd="\
+ "get_avb_mode;"\
+ "get_valid_slot;"\
+ "if test ${vendor_boot_mode} = true; then "\
+ "setenv loadaddr_kernel 0x2080000;"\
+ "setenv dtb_mem_addr 0x1f00000;"\
+ "fi;"\
+ "\0"\
+ "init_display="\
+ "osd open;osd clear;imgread pic logo bootup $loadaddr;bmp display $bootup_offset;bmp scale;vout output ${outputmode}"\
+ "\0"\
+ "cmdline_keys="\
+ "setenv usid 1234567890; setenv region_code US;"\
+ "if keyman init 0x1234; then "\
+ "if keyman read usid ${loadaddr} str; then fi;"\
+ "if keyman read region_code ${loadaddr} str; then fi;"\
+ "if keyman read mac ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
+ "fi;"\
+ "if keyman read deviceid ${loadaddr} str; then "\
+ "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
+ "fi;"\
+ "fi;"\
+ "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
+ "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
+ "setenv serial ${usid}; setenv serial# ${usid};"\
+ "\0"\
+ "upgrade_key="\
+ "if gpio input GPIOD_3; then "\
+ "echo detect upgrade key; run update;"\
+ "fi;"\
+ "\0"\
+
+#define CONFIG_PREBOOT \
+ "run bcb_cmd; "\
+ "run upgrade_check;"\
+ "run init_display;"\
+ "run storeargs;"\
+ "run upgrade_key;" \
+ "bcb uboot-command;" \
+ "run switch_bootmode;"
+
+/* #define CONFIG_ENV_IS_NOWHERE 1 */
+#define CONFIG_ENV_SIZE (64*1024)
+#define CONFIG_FIT 1
+#define CONFIG_OF_LIBFDT 1
+#define CONFIG_ANDROID_BOOT_IMAGE 1
+#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
+
+/* ATTENTION */
+/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
+
+/* running in sram */
+//#define UBOOT_RUN_IN_SRAM
+#ifdef UBOOT_RUN_IN_SRAM
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+/* Size of malloc() pool */
+#define CONFIG_SYS_MALLOC_LEN (256*1024)
+#else
+#define CONFIG_SYS_INIT_SP_ADDR (0x00200000)
+#define CONFIG_SYS_MALLOC_LEN (64*1024*1024)
+#endif
+
+//#define CONFIG_NR_DRAM_BANKS 1
+/* ddr functions */
+#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
+#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
+#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
+#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
+#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
+#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
+
+/* storage: emmc/nand/sd */
+#define CONFIG_ENV_OVERWRITE
+/* #define CONFIG_CMD_SAVEENV */
+/* fixme, need fix*/
+
+#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
+#error env in amlnand/mmc already be compatible;
+#endif
+
+/*
+* storage
+* |---------|---------|
+* | |
+* emmc<--Compatible-->nand
+* |-------|-------|
+* | |
+* MTD<-Exclusive->NFTL
+* |
+* |***************|***************|
+* slc-nand SPI-nand SPI-nor
+* (raw nand)
+*/
+/* axg only support slc nand */
+/* swither for mtd nand which is for slc only. */
+
+
+#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+#if (defined(CONFIG_AML_NAND) || defined(CONFIG_MESON_NFC)) && defined(CONFIG_MESON_FBOOT)
+#error CONFIG_AML_NAND/CONFIG_MESON_NFC CONFIG _MESON_FBOOT can not support at the sametime;
+#endif
+
+#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MTD_SPI_NAND) && defined(CONFIG_MESON_NFC)
+#error CONFIG_SPI_NAND/CONFIG_MTD_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
+#endif
+
+/* #define CONFIG_AML_SD_EMMC 1 */
+#ifdef CONFIG_AML_SD_EMMC
+ #define CONFIG_GENERIC_MMC 1
+ #define CONFIG_CMD_MMC 1
+ #define CONFIG_CMD_GPT 1
+ #define CONFIG_SYS_MMC_ENV_DEV 1
+ #define CONFIG_EMMC_DDR52_EN 0
+ #define CONFIG_EMMC_DDR52_CLK 35000000
+#endif
+#define CONFIG_PARTITIONS 1
+#if 0
+#define CONFIG_SYS_NO_FLASH 1
+#endif
+
+#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND || defined CONFIG_MTD_SPI_NAND
+ #define CONFIG_SYS_MAX_NAND_DEVICE 2
+#endif
+
+/* vpu */
+#define AML_VPU_CLK_LEVEL_DFT 7
+/* LCD */
+
+/*pmic bd71837*/
+#define CONFIG_PMIC_BD71837 1
+
+/* osd */
+#define OSD_SCALE_ENABLE
+#define AML_OSD_HIGH_VERSION
+#define AML_T7_DISPLAY
+
+/* USB
+ * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
+ * Enable CONFIG_MUSB_UDD for Device functionalities.
+ */
+/* #define CONFIG_MUSB_UDC 1 */
+/* #define CONFIG_CMD_USB 1 */
+
+#define USB_PHY2_PLL_PARAMETER_1 0x09400414
+#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
+#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
+
+#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
+#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
+#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
+#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
+#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
+
+#define AML_TXLX_USB 1
+#define AML_USB_V2 1
+#define USB_GENERAL_BIT 3
+#define USB_PHY21_BIT 4
+
+/* UBOOT fastboot config */
+
+
+/* UBOOT Facotry usb/sdcard burning config */
+
+/* net */
+#define CONFIG_CMD_NET 1
+#define CONFIG_ETH_DESIGNWARE
+#if defined(CONFIG_CMD_NET)
+ #define CONFIG_DESIGNWARE_ETH 1
+ #define CONFIG_PHYLIB 1
+ #define CONFIG_NET_MULTI 1
+ #define CONFIG_CMD_PING 1
+ #define CONFIG_CMD_DHCP 1
+ #define CONFIG_CMD_RARP 1
+ #define CONFIG_HOSTNAME "arm_gxbb"
+#if 0
+ #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
+#endif
+ #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
+ #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
+ #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
+ #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
+ #define CONFIG_NETMASK 255.255.255.0
+#endif /* (CONFIG_CMD_NET) */
+
+#define MAC_ADDR_NEW 1
+
+/* other devices */
+#define CONFIG_SHA1 1
+#define CONFIG_MD5 1
+
+/* commands */
+/* #define CONFIG_CMD_PLLTEST 1 */
+
+/*file system*/
+#define CONFIG_DOS_PARTITION 1
+#define CONFIG_EFI_PARTITION 1
+/* #define CONFIG_MMC 1 */
+#define CONFIG_FS_FAT 1
+#define CONFIG_FS_EXT4 1
+#define CONFIG_LZO 1
+
+/* Cache Definitions */
+/* #define CONFIG_SYS_DCACHE_OFF */
+/* #define CONFIG_SYS_ICACHE_OFF */
+
+/* other functions */
+#define CONFIG_LIBAVB 1
+
+/* define CONFIG_SYS_MEM_TOP_HIDE 8M space for free buffer */
+#define CONFIG_SYS_MEM_TOP_HIDE 0x00800000
+
+#define CONFIG_CPU_ARMV8
+
+//use sha2 command
+#define CONFIG_CMD_SHA2
+
+//use startdsp command
+#define CONFIG_CMD_STARTDSP
+
+//use dache command
+#define CONFIG_CMD_CACHE
+
+//use hardware sha2
+#define CONFIG_AML_HW_SHA2
+
+#define CONFIG_MULTI_DTB 1
+
+/* define CONFIG_UPDATE_MMU_TABLE for need update mmu */
+#define CONFIG_UPDATE_MMU_TABLE
+
+/* support secure boot */
+#define CONFIG_AML_SECURE_UBOOT 1
+
+#if defined(CONFIG_AML_SECURE_UBOOT)
+
+/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
+#define CONFIG_AML_CRYPTO_UBOOT 1
+//#define CONFIG_AML_SIGNED_UBOOT 1
+/* unify build for generate encrypted kernel image
+ SRC : "board/amlogic/(board)/boot.img"
+ DST : "fip/boot.img.encrypt" */
+/* #define CONFIG_AML_CRYPTO_IMG 1 */
+
+#endif /* CONFIG_AML_SECURE_UBOOT */
+
+#define CONFIG_FIP_IMG_SUPPORT 1
+
+#define BL32_SHARE_MEM_SIZE 0x800000
+
+#endif
+
diff --git a/board/amlogic/defconfigs/a1_ad401_nand_linux_defconfig b/board/amlogic/defconfigs/a1_ad401_nand_linux_defconfig
new file mode 100644
index 0000000..d6ca433
--- /dev/null
+++ b/board/amlogic/defconfigs/a1_ad401_nand_linux_defconfig
@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_A1=y
+CONFIG_UBOOT_RUN_IN_SRAM=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_A1_AD401_NAND_LINUX=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=2
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="ad401# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_RSVMEM is not set
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-a1-a113l-ad401"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_A1=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_LED=y
+CONFIG_AML_LED_PWM=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_AML_MTDPART=y
+CONFIG_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_A1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/a1_ad401_nand_rtos_defconfig b/board/amlogic/defconfigs/a1_ad401_nand_rtos_defconfig
new file mode 100644
index 0000000..7642ac9
--- /dev/null
+++ b/board/amlogic/defconfigs/a1_ad401_nand_rtos_defconfig
@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_A1=y
+CONFIG_UBOOT_RUN_IN_SRAM=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_A1_AD401_NAND_RTOS=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=2
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="ad401# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_RSVMEM is not set
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-a1-a113l-ad401"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_A1=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_LED=y
+CONFIG_AML_LED_PWM=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_AML_MTDPART=y
+CONFIG_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_A1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/a1_ad401_nor_rtos_defconfig b/board/amlogic/defconfigs/a1_ad401_nor_rtos_defconfig
new file mode 100644
index 0000000..b283faa
--- /dev/null
+++ b/board/amlogic/defconfigs/a1_ad401_nor_rtos_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_A1=y
+CONFIG_UBOOT_RUN_IN_SRAM=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="ad401# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_RSVMEM is not set
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-a1-a113l-ad401"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_A1=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_LED=y
+CONFIG_AML_LED_PWM=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_AML_MTDPART=y
+CONFIG_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_A1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/a1_ad402_nand_linux_defconfig b/board/amlogic/defconfigs/a1_ad402_nand_linux_defconfig
new file mode 100644
index 0000000..6ae5670
--- /dev/null
+++ b/board/amlogic/defconfigs/a1_ad402_nand_linux_defconfig
@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_A1=y
+CONFIG_UBOOT_RUN_IN_SRAM=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_A1_AD402_NAND_LINUX=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=2
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="ad402# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_RSVMEM is not set
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-a1-a113l-ad402"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_A1=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_LED=y
+CONFIG_AML_LED_PWM=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_AML_MTDPART=y
+CONFIG_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_A1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/a1_ad402_nand_rtos_defconfig b/board/amlogic/defconfigs/a1_ad402_nand_rtos_defconfig
new file mode 100644
index 0000000..1966a60
--- /dev/null
+++ b/board/amlogic/defconfigs/a1_ad402_nand_rtos_defconfig
@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_A1=y
+CONFIG_UBOOT_RUN_IN_SRAM=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_A1_AD402_NAND_RTOS=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=2
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="ad402# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_RSVMEM is not set
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-a1-a113l-ad402"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_A1=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_LED=y
+CONFIG_AML_LED_PWM=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_AML_MTDPART=y
+CONFIG_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_A1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/a1_ad402_nor_rtos_defconfig b/board/amlogic/defconfigs/a1_ad402_nor_rtos_defconfig
new file mode 100644
index 0000000..f6842a9
--- /dev/null
+++ b/board/amlogic/defconfigs/a1_ad402_nor_rtos_defconfig
@@ -0,0 +1,99 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_A1=y
+CONFIG_UBOOT_RUN_IN_SRAM=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="ad402# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_RSVMEM is not set
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-a1-a113l-ad402"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_A1=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_LED=y
+CONFIG_AML_LED_PWM=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_AML_MTDPART=y
+CONFIG_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_A1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/a1_ad409_nand_linux_defconfig b/board/amlogic/defconfigs/a1_ad409_nand_linux_defconfig
new file mode 100644
index 0000000..c9ffa83
--- /dev/null
+++ b/board/amlogic/defconfigs/a1_ad409_nand_linux_defconfig
@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_A1=y
+CONFIG_UBOOT_RUN_IN_SRAM=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_A1_AD409_NAND_LINUX=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=2
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="ad409# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_RSVMEM is not set
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-a1-a113l-ad409"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_A1=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_LED=y
+CONFIG_AML_LED_PWM=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_AML_MTDPART=y
+CONFIG_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_A1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/a1_ad409_nand_rtos_defconfig b/board/amlogic/defconfigs/a1_ad409_nand_rtos_defconfig
new file mode 100644
index 0000000..8704c83
--- /dev/null
+++ b/board/amlogic/defconfigs/a1_ad409_nand_rtos_defconfig
@@ -0,0 +1,98 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_A1=y
+CONFIG_UBOOT_RUN_IN_SRAM=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_A1_AD409_NAND_RTOS=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=2
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="ad409# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_RSVMEM is not set
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-a1-a113l-ad409"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_A1=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_LED=y
+CONFIG_AML_LED_PWM=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_AML_MTDPART=y
+CONFIG_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_A1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/a1_ad409_nor_rtos_defconfig b/board/amlogic/defconfigs/a1_ad409_nor_rtos_defconfig
new file mode 100644
index 0000000..daa737a
--- /dev/null
+++ b/board/amlogic/defconfigs/a1_ad409_nor_rtos_defconfig
@@ -0,0 +1,101 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_A1=y
+CONFIG_UBOOT_RUN_IN_SRAM=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_A1_AD409_NOR_RTOS=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="ad409# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_RSVMEM is not set
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-a1-a113l-ad409"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_A1=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_LED=y
+CONFIG_AML_LED_PWM=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_AML_MTDPART=y
+CONFIG_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_SPI_FLASH=y
+CONFIG_SPI_FLASH_GIGADEVICE=y
+CONFIG_SPI_FLASH_MACRONIX=y
+CONFIG_SPI_FLASH_WINBOND=y
+CONFIG_SPI_FLASH_EON=y
+CONFIG_SPI_FLASH_MTD=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_A1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/a1_pxp_defconfig b/board/amlogic/defconfigs/a1_pxp_defconfig
new file mode 100644
index 0000000..aaac89c
--- /dev/null
+++ b/board/amlogic/defconfigs/a1_pxp_defconfig
@@ -0,0 +1,90 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_A1=y
+CONFIG_PXP_EMULATOR=y
+CONFIG_UBOOT_RUN_IN_SRAM=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_A1_AD409_NAND_LINUX=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="ad409# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_RSVMEM is not set
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-a1-a113l-ad409"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_A1=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_AML_MTDPART=y
+CONFIG_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_A1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/c1_ae400_defconfig b/board/amlogic/defconfigs/c1_ae400_defconfig
new file mode 100644
index 0000000..63d7b46
--- /dev/null
+++ b/board/amlogic/defconfigs/c1_ae400_defconfig
@@ -0,0 +1,101 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_C1=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_C1_AE400=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="c1_ae400# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_MTDPARTS=y
+# CONFIG_CMD_RSVMEM is not set
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-c1-c308x-ae400"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_C1=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FASTBOOT_FLASH_NAND=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_MESON_NFC=y
+# CONFIG_MTD_SPI_NAND is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_C1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/c1_ae401_defconfig b/board/amlogic/defconfigs/c1_ae401_defconfig
new file mode 100644
index 0000000..03d9acd
--- /dev/null
+++ b/board/amlogic/defconfigs/c1_ae401_defconfig
@@ -0,0 +1,101 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_C1=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_C1_AE401=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="c1_ae401# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_MTDPARTS=y
+# CONFIG_CMD_RSVMEM is not set
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-c1-c308x-ae401"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_C1=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FASTBOOT_FLASH_NAND=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_MESON_NFC=y
+# CONFIG_MTD_SPI_NAND is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_C1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/c1_ae402_defconfig b/board/amlogic/defconfigs/c1_ae402_defconfig
new file mode 100644
index 0000000..bcb4b4c
--- /dev/null
+++ b/board/amlogic/defconfigs/c1_ae402_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_C1=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_C1_AE402=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="c1_ae402# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_MTDPARTS=y
+# CONFIG_CMD_RSVMEM is not set
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-c1-c308x-ae402"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_C1=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_MESON_NFC=y
+# CONFIG_MTD_SPI_NAND is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_C1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/c1_ae409_defconfig b/board/amlogic/defconfigs/c1_ae409_defconfig
new file mode 100644
index 0000000..c3169cb
--- /dev/null
+++ b/board/amlogic/defconfigs/c1_ae409_defconfig
@@ -0,0 +1,102 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_C1=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="c1_ae409# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_CACHE=y
+CONFIG_CMD_MTDPARTS=y
+# CONFIG_CMD_RSVMEM is not set
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-c1-c308x-ae409"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_C1=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_FASTBOOT_FLASH_NAND=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_MESON_NFC=y
+# CONFIG_MTD_SPI_NAND is not set
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_AMLOGIC=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_C1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/c1_pxp_defconfig b/board/amlogic/defconfigs/c1_pxp_defconfig
new file mode 100644
index 0000000..0fe8369
--- /dev/null
+++ b/board/amlogic/defconfigs/c1_pxp_defconfig
@@ -0,0 +1,89 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_C1=y
+CONFIG_PXP_EMULATOR=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_C1_AE409=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="c1_pxp# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_RSVMEM is not set
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-c1-c308x-ae409"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_C1=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_AML_MTDPART=y
+CONFIG_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_C1=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/c2_af400_defconfig b/board/amlogic/defconfigs/c2_af400_defconfig
new file mode 100644
index 0000000..c1c88d1
--- /dev/null
+++ b/board/amlogic/defconfigs/c2_af400_defconfig
@@ -0,0 +1,94 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_C2=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_C2_AF400=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="c2_af400# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c305x-af400"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_C2=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_C2=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_MESON_NFC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_C2=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/c2_af401_defconfig b/board/amlogic/defconfigs/c2_af401_defconfig
new file mode 100644
index 0000000..b90c765
--- /dev/null
+++ b/board/amlogic/defconfigs/c2_af401_defconfig
@@ -0,0 +1,94 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_C2=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_C2_AF401=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="c2_af401# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c305x-af401"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_C2=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_C2=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_MESON_NFC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_C2=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/c2_af402_defconfig b/board/amlogic/defconfigs/c2_af402_defconfig
new file mode 100644
index 0000000..5fca4a3
--- /dev/null
+++ b/board/amlogic/defconfigs/c2_af402_defconfig
@@ -0,0 +1,94 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_C2=y
+CONFIG_AML_BL33_COMPRESS_ENABLE=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_C2_AF402=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+# CONFIG_DISTRO_DEFAULTS is not set
+CONFIG_ANDROID_BOOT_IMAGE=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_HUSH_PARSER=y
+CONFIG_SYS_PROMPT="c2_af402# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_CONSOLE is not set
+# CONFIG_CMD_DSPRUN is not set
+# CONFIG_CMD_DSPSET is not set
+# CONFIG_CMD_ELF is not set
+# CONFIG_CMD_IMI is not set
+# CONFIG_CMD_XIMG is not set
+# CONFIG_CMD_EXPORTENV is not set
+# CONFIG_CMD_IMPORTENV is not set
+# CONFIG_CMD_EDITENV is not set
+# CONFIG_CMD_LZMADEC is not set
+# CONFIG_CMD_UNZIP is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
+# CONFIG_CMD_NAND is not set
+CONFIG_AML_STORAGE=y
+CONFIG_CMD_SF=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SOURCE is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+# CONFIG_CMD_RSVMEM is not set
+# CONFIG_CMD_DDR_TEST is not set
+CONFIG_CMD_WATCHDOG=y
+# CONFIG_CMD_EFUSE is not set
+# CONFIG_PARTITIONS is not set
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c305x-af402"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_NET is not set
+CONFIG_HAVE_BLOCK_DEVICE=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_C2=y
+CONFIG_DM_GPIO=y
+# CONFIG_INPUT is not set
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_C2=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+# CONFIG_EFI_LOADER is not set
diff --git a/board/amlogic/defconfigs/c2_af409_defconfig b/board/amlogic/defconfigs/c2_af409_defconfig
new file mode 100644
index 0000000..a0ff91c
--- /dev/null
+++ b/board/amlogic/defconfigs/c2_af409_defconfig
@@ -0,0 +1,95 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_C2=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_C2_AF409=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="c2_af409# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c305x-af409"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_C2=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_C2=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_MESON_NFC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_C2=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/c2_af419_defconfig b/board/amlogic/defconfigs/c2_af419_defconfig
new file mode 100644
index 0000000..ccd591d
--- /dev/null
+++ b/board/amlogic/defconfigs/c2_af419_defconfig
@@ -0,0 +1,94 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_C2=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_C2_AF419=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="c2_af419# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-c2-c305x-af419"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_C2=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_C2=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_MESON_NFC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_C2=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/c2_pxp_defconfig b/board/amlogic/defconfigs/c2_pxp_defconfig
new file mode 100644
index 0000000..9461d3e
--- /dev/null
+++ b/board/amlogic/defconfigs/c2_pxp_defconfig
@@ -0,0 +1,90 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_C2=y
+CONFIG_PXP_EMULATOR=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_NEED_BL32=y
+CONFIG_C2_SKT=y
+CONFIG_DEBUG_UART_BASE=0xfe001c00
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="c2_pxp# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_AML_STORAGE=y
+CONFIG_CMD_RSVMEM=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-c2-pxp"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SARADC_MESON_C2=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_C2=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+# CONFIG_MMC is not set
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_MESON_NFC=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_C2=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPIFCV2=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_SECURE_POWER_CONTROL=y
diff --git a/board/amlogic/defconfigs/g12a_u200_v1_defconfig b/board/amlogic/defconfigs/g12a_u200_v1_defconfig
new file mode 100644
index 0000000..f061e1f
--- /dev/null
+++ b/board/amlogic/defconfigs/g12a_u200_v1_defconfig
@@ -0,0 +1,106 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_MESON_G12A=y
+CONFIG_FIP_IMG_SUPPORT=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_AML_OSCRING=n
+CONFIG_NEED_BL32=y
+CONFIG_TARGET_G12A_U200_V1=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=1
+CONFIG_BOOTCOMMAND="run storeboot"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="g12a_u200_v1# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_DSPRUN is not set
+# CONFIG_CMD_DSPSET is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_MTD=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_AML_STORAGE=y
+CONFIG_BOOTLOADER_CONTROL_BLOCK=y
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_AML_PARTITION=y
+CONFIG_AML_GPT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-s905d2-u200"
+CONFIG_ENV_IS_IN_STORAGE=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_G12=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+#CONFIG_SPI_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_AML_V2_FACTORY_BURN=y
+CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
+CONFIG_SD_BURNING_SUPPORT_UI=y
+CONFIG_USB_BURNING_TOOL=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_CANVAS=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_CVBS=y
+CONFIG_AML_LCD=y
+CONFIG_AML_LCD_TABLET=y
+CONFIG_AML_LCD_BACKLIGHT=y
+#CONFIG_MESON_NFC=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_EFUSE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/g12b_w400_v1_defconfig b/board/amlogic/defconfigs/g12b_w400_v1_defconfig
new file mode 100644
index 0000000..1f39e96
--- /dev/null
+++ b/board/amlogic/defconfigs/g12b_w400_v1_defconfig
@@ -0,0 +1,105 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x01000000
+CONFIG_MESON_G12B=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_AML_OSCRING=y
+CONFIG_NEED_BL32=y
+CONFIG_TARGET_G12B_W400_V1=y
+CONFIG_DEBUG_UART_BASE=0xff803000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=1
+CONFIG_BOOTCOMMAND="run storeboot"
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="g12b_w400_v1# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_DSPRUN is not set
+# CONFIG_CMD_DSPSET is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
+CONFIG_CMD_MMC=y
+CONFIG_CMD_SF=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+CONFIG_CMD_MTDPARTS=y
+CONFIG_AML_STORAGE=y
+CONFIG_BOOTLOADER_CONTROL_BLOCK=y
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_AML_PARTITION=y
+CONFIG_AML_GPT=y
+CONFIG_OF_CONTROL=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-w400"
+CONFIG_ENV_IS_IN_STORAGE=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_G12=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_NAND=y
+CONFIG_DM_SPI_FLASH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_G12A=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_AML_SPIFC=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_FASTBOOT_DWC_PCD=y
+CONFIG_AML_V2_FACTORY_BURN=y
+CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
+CONFIG_SD_BURNING_SUPPORT_UI=y
+CONFIG_USB_BURNING_TOOL=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_CANVAS=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_CVBS=y
+CONFIG_AML_LCD=y
+CONFIG_AML_LCD_TABLET=y
+CONFIG_AML_LCD_BACKLIGHT=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_EFUSE=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/s4_ap201_defconfig b/board/amlogic/defconfigs/s4_ap201_defconfig
new file mode 100644
index 0000000..1b75cd0
--- /dev/null
+++ b/board/amlogic/defconfigs/s4_ap201_defconfig
@@ -0,0 +1,110 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_S4=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_CHIPSET_NAME="ra188"
+CONFIG_BL30_SELECT="s4_ap201"
+CONFIG_S4_AP201=y
+CONFIG_DEBUG_UART_BASE=0xfe07a000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="s4_ap201# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_DSPSET is not set
+CONFIG_CMD_DTIMG=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_PINMUX is not set
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-s4-ap201"
+CONFIG_ENV_IS_IN_STORAGE=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_S4=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_MESON_NFC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_AMLOGIC=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_S4=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_CRG=y
+CONFIG_USB_GADGET=y
+CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_CANVAS=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_CVBS=y
+CONFIG_AML_HDMITX=y
+CONFIG_AML_HDMITX20=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_MESON_LEDS_STATE_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/s4_ap222_defconfig b/board/amlogic/defconfigs/s4_ap222_defconfig
new file mode 100644
index 0000000..83edada
--- /dev/null
+++ b/board/amlogic/defconfigs/s4_ap222_defconfig
@@ -0,0 +1,109 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_S4=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_BL30_SELECT="s4_ap222"
+CONFIG_S4_AP222=y
+CONFIG_DEBUG_UART_BASE=0xfe07a000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="s4_ap222# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_DSPSET is not set
+CONFIG_CMD_DTIMG=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_PINMUX is not set
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-s4-ap222"
+CONFIG_ENV_IS_IN_STORAGE=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_S4=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_MESON_NFC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_AMLOGIC=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_S4=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_CRG=y
+CONFIG_USB_GADGET=y
+CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_CANVAS=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_CVBS=y
+CONFIG_AML_HDMITX=y
+CONFIG_AML_HDMITX20=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_MESON_LEDS_STATE_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/s4_ap229_defconfig b/board/amlogic/defconfigs/s4_ap229_defconfig
new file mode 100644
index 0000000..c9e429e
--- /dev/null
+++ b/board/amlogic/defconfigs/s4_ap229_defconfig
@@ -0,0 +1,109 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_S4=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_BL30_SELECT="s4_ap229"
+CONFIG_S4_AP229=y
+CONFIG_DEBUG_UART_BASE=0xfe07a000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="s4_ap229# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_DSPSET is not set
+CONFIG_CMD_DTIMG=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_PINMUX is not set
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-s4-ap229"
+CONFIG_ENV_IS_IN_STORAGE=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_S4=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_MESON_NFC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_AMLOGIC=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_S4=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_CRG=y
+CONFIG_USB_GADGET=y
+CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_CANVAS=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_CVBS=y
+CONFIG_AML_HDMITX=y
+CONFIG_AML_HDMITX20=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_MESON_LEDS_STATE_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/s4_aq222_defconfig b/board/amlogic/defconfigs/s4_aq222_defconfig
new file mode 100644
index 0000000..d5cea47
--- /dev/null
+++ b/board/amlogic/defconfigs/s4_aq222_defconfig
@@ -0,0 +1,110 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_S4=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_CHIPSET_NAME="s805x2"
+CONFIG_BL30_SELECT="s4_aq222"
+CONFIG_S4_AQ222=y
+CONFIG_DEBUG_UART_BASE=0xfe07a000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="s4_aq222# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_DSPSET is not set
+CONFIG_CMD_DTIMG=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_PINMUX is not set
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-s4-aq222"
+CONFIG_ENV_IS_IN_STORAGE=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_S4=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_MESON_NFC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_AMLOGIC=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_S4=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_CRG=y
+CONFIG_USB_GADGET=y
+CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_CANVAS=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_CVBS=y
+CONFIG_AML_HDMITX=y
+CONFIG_AML_HDMITX20=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_MESON_LEDS_STATE_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/s4_aq229_defconfig b/board/amlogic/defconfigs/s4_aq229_defconfig
new file mode 100644
index 0000000..854012a
--- /dev/null
+++ b/board/amlogic/defconfigs/s4_aq229_defconfig
@@ -0,0 +1,110 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_S4=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_CHIPSET_NAME="s805x2"
+CONFIG_BL30_SELECT="s4_aq222"
+CONFIG_S4_AQ229=y
+CONFIG_DEBUG_UART_BASE=0xfe07a000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="s4_aq229# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_DSPSET is not set
+CONFIG_CMD_DTIMG=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_PINMUX is not set
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-s4-aq229"
+CONFIG_ENV_IS_IN_STORAGE=y
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_S4=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_MESON_NFC=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_AMLOGIC=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_S4=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_CRG=y
+CONFIG_USB_GADGET=y
+CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_CANVAS=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_CVBS=y
+CONFIG_AML_HDMITX=y
+CONFIG_AML_HDMITX20=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_MESON_LEDS_STATE_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/s4_pxp_defconfig b/board/amlogic/defconfigs/s4_pxp_defconfig
new file mode 100644
index 0000000..01a3926
--- /dev/null
+++ b/board/amlogic/defconfigs/s4_pxp_defconfig
@@ -0,0 +1,95 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_S4=y
+CONFIG_PXP_EMULATOR=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_BL30_SELECT="s4_skt"
+# CONFIG_AML_REBOOT is not set
+CONFIG_DEBUG_UART_BASE=0xfe07a000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="echo bootcmd"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="s4_pxp# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_DSPSET is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_PINMUX is not set
+CONFIG_CMD_USB=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_NET is not set
+CONFIG_CMD_BMP=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+# CONFIG_CMD_DDR_TEST is not set
+# CONFIG_CMD_OS_IDENT is not set
+# CONFIG_AML_ROBUST is not set
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+# CONFIG_CMD_EFUSE is not set
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-s4-pxp"
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_S4=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_MESON_NFC=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_S4=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_CRG=y
+CONFIG_USB_GADGET=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_CANVAS=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_HDMITX=y
+CONFIG_AML_HDMITX20=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_MESON_LEDS_STATE_CONTROL=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
diff --git a/board/amlogic/defconfigs/s4_t211_defconfig b/board/amlogic/defconfigs/s4_t211_defconfig
new file mode 100644
index 0000000..bc8f787
--- /dev/null
+++ b/board/amlogic/defconfigs/s4_t211_defconfig
@@ -0,0 +1,113 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_S4=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_CHIPSET_NAME="s805x2g"
+CONFIG_BL30_SELECT="s4_t211"
+CONFIG_S4_T211=y
+CONFIG_DEBUG_UART_BASE=0xfe07a000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=-2
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="boreal# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_DSPSET is not set
+CONFIG_CMD_DTIMG=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+# CONFIG_CMD_FLASH is not set
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_GPT=y
+CONFIG_CMD_GPT_RENAME=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_PINMUX is not set
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_BOOTLOADER_CONTROL_BLOCK=y
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+# CONFIG_CMD_EFUSE is not set
+CONFIG_CMD_TCPC=y
+CONFIG_AML_PARTITION=y
+# CONFIG_AML_GPT is not set
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-s4-t211"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_NET is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_S4=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_S4=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DM_PWM=y
+CONFIG_PWM_MESON=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_CRG=y
+CONFIG_USB_GADGET=y
+CONFIG_FASTBOOT_DWC_PCD=y
+CONFIG_TYPEC=y
+CONFIG_TYPEC_TCPM=y
+CONFIG_TYPEC_TCPCI=y
+CONFIG_TYPEC_RT1711H=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_CANVAS=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_CVBS=y
+CONFIG_AML_HDMITX=y
+CONFIG_AML_HDMITX20=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_LIBAVB=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
+CONFIG_MD5=y
+CONFIG_OF_LIBFDT_OVERLAY=y
+CONFIG_CHROMECAST=y
diff --git a/board/amlogic/defconfigs/sc2_ah212_ddr3_defconfig b/board/amlogic/defconfigs/sc2_ah212_ddr3_defconfig
new file mode 100644
index 0000000..f636d4a
--- /dev/null
+++ b/board/amlogic/defconfigs/sc2_ah212_ddr3_defconfig
@@ -0,0 +1,115 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_SC2=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_DDRFW_TYPE="lpddr3"
+CONFIG_CHIPSET_NAME="s905x4"
+CONFIG_BL30_SELECT="sc2_ah212"
+CONFIG_SC2_AH212_LPDDR3=y
+CONFIG_DEBUG_UART_BASE=0xfe07a000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="sc2_ah212_lpddr3# "
+# CONFIG_CMD_BDI is not set
+CONFIG_CMD_DTIMG=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+CONFIG_CMD_IR=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_CMD_INI=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-sc2-s905x4-ah212-ddr3"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_SC2=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_AML_MTDPART=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_AMLOGIC=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_SC2=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_CANVAS=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_CVBS=y
+CONFIG_AML_HDMITX=y
+CONFIG_AML_HDMITX20=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_FAT_WRITE=y
+CONFIG_AML_FACTORY_PROVISION=y
+CONFIG_MESON_LEDS_STATE_CONTROL=y
+CONFIG_MESON_IR=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/sc2_ah212_defconfig b/board/amlogic/defconfigs/sc2_ah212_defconfig
new file mode 100644
index 0000000..13eb2c3
--- /dev/null
+++ b/board/amlogic/defconfigs/sc2_ah212_defconfig
@@ -0,0 +1,115 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_SC2=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_DDR_FULL_FW=y
+CONFIG_CHIPSET_NAME="s905x4"
+CONFIG_BL30_SELECT="sc2_ah212"
+CONFIG_SC2_AH212=y
+CONFIG_DEBUG_UART_BASE=0xfe07a000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="sc2_ah212# "
+# CONFIG_CMD_BDI is not set
+CONFIG_CMD_DTIMG=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+CONFIG_CMD_IR=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_CMD_INI=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-sc2-s905x4-ah212"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_SC2=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_AML_MTDPART=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_AMLOGIC=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_SC2=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_CANVAS=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_CVBS=y
+CONFIG_AML_HDMITX=y
+CONFIG_AML_HDMITX20=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_FAT_WRITE=y
+CONFIG_AML_FACTORY_PROVISION=y
+CONFIG_MESON_LEDS_STATE_CONTROL=y
+CONFIG_MESON_IR=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/sc2_ah212_lpddr3_defconfig b/board/amlogic/defconfigs/sc2_ah212_lpddr3_defconfig
new file mode 100644
index 0000000..f636d4a
--- /dev/null
+++ b/board/amlogic/defconfigs/sc2_ah212_lpddr3_defconfig
@@ -0,0 +1,115 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_SC2=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_DDRFW_TYPE="lpddr3"
+CONFIG_CHIPSET_NAME="s905x4"
+CONFIG_BL30_SELECT="sc2_ah212"
+CONFIG_SC2_AH212_LPDDR3=y
+CONFIG_DEBUG_UART_BASE=0xfe07a000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="sc2_ah212_lpddr3# "
+# CONFIG_CMD_BDI is not set
+CONFIG_CMD_DTIMG=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+CONFIG_CMD_IR=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_CMD_INI=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-sc2-s905x4-ah212-ddr3"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_SC2=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_AML_MTDPART=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_AMLOGIC=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_SC2=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_CANVAS=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_CVBS=y
+CONFIG_AML_HDMITX=y
+CONFIG_AML_HDMITX20=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_FAT_WRITE=y
+CONFIG_AML_FACTORY_PROVISION=y
+CONFIG_MESON_LEDS_STATE_CONTROL=y
+CONFIG_MESON_IR=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/sc2_ah212_lpddr4_defconfig b/board/amlogic/defconfigs/sc2_ah212_lpddr4_defconfig
new file mode 100644
index 0000000..e4edb37
--- /dev/null
+++ b/board/amlogic/defconfigs/sc2_ah212_lpddr4_defconfig
@@ -0,0 +1,115 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_SC2=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_DDRFW_TYPE="lpddr4"
+CONFIG_CHIPSET_NAME="s905x4"
+CONFIG_BL30_SELECT="sc2_ah212"
+CONFIG_SC2_AH212_LPDDR4=y
+CONFIG_DEBUG_UART_BASE=0xfe07a000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="sc2_ah212_lpddr4# "
+# CONFIG_CMD_BDI is not set
+CONFIG_CMD_DTIMG=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+CONFIG_CMD_IR=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_CMD_INI=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-sc2-s905x4-ah212-ddr3"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_SC2=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_AML_MTDPART=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_AMLOGIC=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_SC2=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_CANVAS=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_CVBS=y
+CONFIG_AML_HDMITX=y
+CONFIG_AML_HDMITX20=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_FAT_WRITE=y
+CONFIG_AML_FACTORY_PROVISION=y
+CONFIG_MESON_LEDS_STATE_CONTROL=y
+CONFIG_MESON_IR=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/sc2_ah219_defconfig b/board/amlogic/defconfigs/sc2_ah219_defconfig
new file mode 100644
index 0000000..11580d8
--- /dev/null
+++ b/board/amlogic/defconfigs/sc2_ah219_defconfig
@@ -0,0 +1,116 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_SC2=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_DDR_FULL_FW=y
+CONFIG_CHIPSET_NAME="s905x4"
+CONFIG_SC2_AH219=y
+CONFIG_DEBUG_UART_BASE=0xfe07a000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="sc2_ah219# "
+# CONFIG_CMD_BDI is not set
+CONFIG_CMD_DTIMG=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+CONFIG_CMD_IR=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_CMD_INI=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-sc2-s905x4-ah219"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_SC2=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_AMLOGIC=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_SC2=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_CANVAS=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_CVBS=y
+CONFIG_AML_HDMITX=y
+CONFIG_AML_HDMITX20=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_FAT_WRITE=y
+CONFIG_AML_FACTORY_PROVISION=y
+CONFIG_MESON_LEDS_STATE_CONTROL=y
+CONFIG_MESON_IR=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/sc2_ah219_s905c2eng_defconfig b/board/amlogic/defconfigs/sc2_ah219_s905c2eng_defconfig
new file mode 100644
index 0000000..bf2b213
--- /dev/null
+++ b/board/amlogic/defconfigs/sc2_ah219_s905c2eng_defconfig
@@ -0,0 +1,115 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_SC2=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_CHIPSET_NAME="s905c2eng"
+CONFIG_AMLOGIC_KEY_TYPE="test-keys"
+CONFIG_SC2_AH219=y
+CONFIG_DEBUG_UART_BASE=0xfe07a000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="sc2_ah219# "
+# CONFIG_CMD_BDI is not set
+CONFIG_CMD_DTIMG=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+CONFIG_CMD_IR=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=y
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-sc2-s905x4-ah219"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_SC2=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=y
+CONFIG_NAND=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_AMLOGIC=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_SC2=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_CANVAS=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_CVBS=y
+CONFIG_AML_HDMITX=y
+CONFIG_AML_HDMITX20=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_FAT_WRITE=y
+CONFIG_AML_FACTORY_PROVISION=y
+CONFIG_MESON_LEDS_STATE_CONTROL=y
+CONFIG_MESON_IR=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/sc2_ah232_defconfig b/board/amlogic/defconfigs/sc2_ah232_defconfig
new file mode 100644
index 0000000..854c9b6
--- /dev/null
+++ b/board/amlogic/defconfigs/sc2_ah232_defconfig
@@ -0,0 +1,115 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_SC2=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_DDR_FULL_FW=y
+CONFIG_CHIPSET_NAME="s905c2"
+CONFIG_BL30_SELECT="sc2_ah212"
+CONFIG_SC2_AH232=y
+CONFIG_DEBUG_UART_BASE=0xfe07a000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="sc2_ah232# "
+# CONFIG_CMD_BDI is not set
+CONFIG_CMD_DTIMG=y
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_CMD_MTD=y
+CONFIG_AML_STORAGE=y
+CONFIG_CMD_SPI=y
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+CONFIG_CMD_IR=y
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+CONFIG_CMD_CACHE=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_CMD_INI=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-sc2-s905c2-ah232"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_SC2=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_DM_I2C_GPIO=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS200_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_AML_MTDPART=y
+CONFIG_PHYLIB=y
+CONFIG_PHY_AMLOGIC=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_SC2=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=y
+CONFIG_DM_SPI=y
+CONFIG_AML_SPICC=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_DWC3=y
+CONFIG_USB_GADGET=y
+CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_CANVAS=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_CVBS=y
+CONFIG_AML_HDMITX=y
+CONFIG_AML_HDMITX20=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_FAT_WRITE=y
+CONFIG_AML_FACTORY_PROVISION=y
+CONFIG_MESON_LEDS_STATE_CONTROL=y
+CONFIG_MESON_IR=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
+CONFIG_OF_LIBFDT_OVERLAY=y
diff --git a/board/amlogic/defconfigs/sc2_pxp_defconfig b/board/amlogic/defconfigs/sc2_pxp_defconfig
new file mode 100644
index 0000000..5f64726
--- /dev/null
+++ b/board/amlogic/defconfigs/sc2_pxp_defconfig
@@ -0,0 +1,100 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_SC2=y
+CONFIG_PXP_EMULATOR=y
+CONFIG_AML_TSENSOR=n
+CONFIG_AML_TSENSOR_COOL=n
+CONFIG_NEED_BL32=n
+CONFIG_SC2_SKT=y
+CONFIG_DEBUG_UART_BASE=0xfe07a000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="echo bootcmd"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="sc2_pxp# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+CONFIG_CMD_DSPSET=n
+CONFIG_CMD_EFUSE=n
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MTD=y
+CONFIG_CMD_SF=n
+CONFIG_CMD_USB=n
+CONFIG_CMD_SARADC=n
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_MTDPARTS=n
+CONFIG_AML_STORAGE=y
+CONFIG_CMD_RSVMEM=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=n
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-sc2-pxp"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_SC2=y
+CONFIG_USB_FUNCTION_FASTBOOT=n
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_CMD_MMC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_MTD=n
+CONFIG_AML_MTDPART=y
+CONFIG_NAND=n
+CONFIG_DM_SPI_FLASH=n
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=n
+CONFIG_AML_USB2_PHY=n
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_SC2=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_SPI=n
+CONFIG_DM_SPI=n
+CONFIG_AML_SPIFCV2=n
+CONFIG_USB=n
+CONFIG_DM_USB=n
+CONFIG_AML_USB=n
+CONFIG_USB_XHCI_HCD=n
+CONFIG_USB_XHCI_DWC3=n
+CONFIG_USB_GADGET=n
+CONFIG_USB_GADGET_VENDOR_NUM=0x1b8e
+CONFIG_AML_V3_FACTORY_BURN=n
+CONFIG_AML_V3_USB_TOOl=n
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_CANVAS=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_HDMITX20=y
+CONFIG_EFUSE=n
+CONFIG_SHA1=y
+CONFIG_SHA256=y
+CONFIG_OF_LIBFDT_OVERLAY=n
+CONFIG_SECURE_POWER_CONTROL=y
diff --git a/board/amlogic/defconfigs/t7_an400_lpddr4x_defconfig b/board/amlogic/defconfigs/t7_an400_lpddr4x_defconfig
new file mode 100644
index 0000000..5c696f1
--- /dev/null
+++ b/board/amlogic/defconfigs/t7_an400_lpddr4x_defconfig
@@ -0,0 +1,106 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_T7=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_DDR_FULL_FW=y
+CONFIG_DDRFW_TYPE="lpddr4"
+CONFIG_CHIPSET_NAME="a311d2"
+CONFIG_BL30_SELECT="t7_an400_lpddr4x"
+CONFIG_T7_AN400_LPDDR4X=y
+CONFIG_DEBUG_UART_BASE=0xfe078000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=2
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="t7_an400_lpddr4x# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_DSPSET is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_PINMUX is not set
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+# CONFIG_CMD_MISC is not set
+CONFIG_BOOTLOADER_CONTROL_BLOCK=y
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_CMD_INI=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-t7-an400-lpddr4x"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_T7=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_T7=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_CRG=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_CRG=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_LCD=y
+CONFIG_AML_LCD_TV=y
+CONFIG_AML_LCD_TABLET=y
+CONFIG_AML_LCD_BACKLIGHT=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_MESON_LEDS_STATE_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
diff --git a/board/amlogic/defconfigs/t7_an400p_lpddr4x_defconfig b/board/amlogic/defconfigs/t7_an400p_lpddr4x_defconfig
new file mode 100644
index 0000000..4dba6aa
--- /dev/null
+++ b/board/amlogic/defconfigs/t7_an400p_lpddr4x_defconfig
@@ -0,0 +1,106 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_T7=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_DDR_FULL_FW=y
+CONFIG_DDRFW_TYPE="lpddr4"
+CONFIG_CHIPSET_NAME="a311d2"
+CONFIG_BL30_SELECT="t7_an400p_lpddr4x"
+CONFIG_T7_AN400P_LPDDR4X=y
+CONFIG_DEBUG_UART_BASE=0xfe078000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=2
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="t7_an400p_lpddr4x# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_DSPSET is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_PINMUX is not set
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+# CONFIG_CMD_MISC is not set
+CONFIG_BOOTLOADER_CONTROL_BLOCK=y
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_CMD_INI=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-t7-an400p-lpddr4x"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_T7=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_T7=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_CRG=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_CRG=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_LCD=y
+CONFIG_AML_LCD_TV=y
+CONFIG_AML_LCD_TABLET=y
+CONFIG_AML_LCD_BACKLIGHT=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_MESON_LEDS_STATE_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
diff --git a/board/amlogic/defconfigs/t7_an408_lpddr4x_defconfig b/board/amlogic/defconfigs/t7_an408_lpddr4x_defconfig
new file mode 100644
index 0000000..251df38
--- /dev/null
+++ b/board/amlogic/defconfigs/t7_an408_lpddr4x_defconfig
@@ -0,0 +1,106 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_T7=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_DDR_FULL_FW=y
+CONFIG_DDRFW_TYPE="lpddr4"
+CONFIG_CHIPSET_NAME="a311d2"
+CONFIG_BL30_SELECT="t7_an408_lpddr4x"
+CONFIG_T7_AN408_LPDDR4X=y
+CONFIG_DEBUG_UART_BASE=0xfe078000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=2
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="t7_an408_lpddr4x# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_DSPSET is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_PINMUX is not set
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+# CONFIG_CMD_MISC is not set
+CONFIG_BOOTLOADER_CONTROL_BLOCK=y
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_CMD_INI=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-t7-an408-lpddr4x"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_T7=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_T7=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_CRG=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_CRG=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_LCD=y
+CONFIG_AML_LCD_TV=y
+CONFIG_AML_LCD_TABLET=y
+CONFIG_AML_LCD_BACKLIGHT=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_MESON_LEDS_STATE_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
diff --git a/board/amlogic/defconfigs/t7_an409_ddr4_defconfig b/board/amlogic/defconfigs/t7_an409_ddr4_defconfig
new file mode 100644
index 0000000..5c02858
--- /dev/null
+++ b/board/amlogic/defconfigs/t7_an409_ddr4_defconfig
@@ -0,0 +1,105 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_T7=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_DDR_FULL_FW=y
+CONFIG_CHIPSET_NAME="a311d2"
+CONFIG_BL30_SELECT="t7_an409_ddr4"
+CONFIG_T7_AN409_DDR4=y
+CONFIG_DEBUG_UART_BASE=0xfe078000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=2
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="t7_an409_ddr4# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_DSPSET is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_PINMUX is not set
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+# CONFIG_CMD_MISC is not set
+CONFIG_BOOTLOADER_CONTROL_BLOCK=y
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_CMD_INI=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-t7-an409-ddr4"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_T7=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_T7=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_CRG=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_CRG=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_LCD=y
+CONFIG_AML_LCD_TV=y
+CONFIG_AML_LCD_TABLET=y
+CONFIG_AML_LCD_BACKLIGHT=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_MESON_LEDS_STATE_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
diff --git a/board/amlogic/defconfigs/t7_an40a1_defconfig b/board/amlogic/defconfigs/t7_an40a1_defconfig
new file mode 100644
index 0000000..1680055
--- /dev/null
+++ b/board/amlogic/defconfigs/t7_an40a1_defconfig
@@ -0,0 +1,106 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_T7=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_DDR_FULL_FW=y
+CONFIG_DDRFW_TYPE="lpddr4"
+CONFIG_CHIPSET_NAME="pop1"
+CONFIG_BL30_SELECT="t7_an40a1"
+CONFIG_T7_AN40A1=y
+CONFIG_DEBUG_UART_BASE=0xfe078000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=2
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="t7_an40a1# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_DSPSET is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_PINMUX is not set
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+# CONFIG_CMD_MISC is not set
+CONFIG_BOOTLOADER_CONTROL_BLOCK=y
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_CMD_INI=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-t7-an40a1"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_T7=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_T7=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_CRG=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_CRG=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_LCD=y
+CONFIG_AML_LCD_TV=y
+CONFIG_AML_LCD_TABLET=y
+CONFIG_AML_LCD_BACKLIGHT=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_MESON_LEDS_STATE_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
diff --git a/board/amlogic/defconfigs/t7_pxp_defconfig b/board/amlogic/defconfigs/t7_pxp_defconfig
new file mode 100644
index 0000000..7201410
--- /dev/null
+++ b/board/amlogic/defconfigs/t7_pxp_defconfig
@@ -0,0 +1,87 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_T7=y
+CONFIG_PXP_EMULATOR=y
+CONFIG_PXP_DDR=y
+CONFIG_PXP_SCS=y
+CONFIG_BL30_SELECT="t7_skt"
+# CONFIG_AML_REBOOT is not set
+CONFIG_DEBUG_UART_BASE=0xfe078000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTCOMMAND="echo bootcmd"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="t7_pxp# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_DSPSET is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_PINMUX is not set
+CONFIG_CMD_USB=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_NET=y
+CONFIG_CMD_BMP=y
+# CONFIG_CMD_MISC is not set
+CONFIG_CMD_RSVMEM=y
+# CONFIG_CMD_OS_IDENT is not set
+CONFIG_CMD_WATCHDOG=y
+# CONFIG_CMD_EFUSE is not set
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-t7-pxp"
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_T7=y
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_T7=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_CRG=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_CRG=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_LCD=y
+CONFIG_AML_LCD_TV=y
+CONFIG_AML_LCD_TABLET=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_SHA1=y
+CONFIG_SHA256=y
+CONFIG_DM_ETH=y
diff --git a/board/amlogic/defconfigs/t7_t319_defconfig b/board/amlogic/defconfigs/t7_t319_defconfig
new file mode 100644
index 0000000..3faad62
--- /dev/null
+++ b/board/amlogic/defconfigs/t7_t319_defconfig
@@ -0,0 +1,105 @@
+CONFIG_ARM=y
+CONFIG_ARCH_MESON=y
+CONFIG_SYS_TEXT_BASE=0x00000000
+CONFIG_MESON_T7=y
+CONFIG_AML_TSENSOR=y
+CONFIG_AML_TSENSOR_COOL=y
+CONFIG_DDR_FULL_FW=y
+CONFIG_DDRFW_TYPE="lpddr4"
+CONFIG_CHIPSET_NAME="pop1"
+CONFIG_BL30_SELECT="t7_t319"
+CONFIG_T7_T319=y
+CONFIG_DEBUG_UART_BASE=0xfe078000
+CONFIG_DEBUG_UART_CLOCK=24000000
+CONFIG_DEBUG_UART=y
+# CONFIG_ANDROID_BOOT_IMAGE is not set
+CONFIG_OF_BOARD_SETUP=y
+CONFIG_BOOTDELAY=2
+CONFIG_BOOTCOMMAND="run storeboot"
+CONFIG_BOARD_LATE_INIT=y
+# CONFIG_DISPLAY_CPUINFO is not set
+# CONFIG_DISPLAY_BOARDINFO is not set
+CONFIG_SYS_PROMPT="t7_t319# "
+# CONFIG_CMD_BDI is not set
+# CONFIG_CMD_DSPSET is not set
+# CONFIG_CMD_IMI is not set
+CONFIG_CMD_CLKMSR=y
+CONFIG_CMD_GPIO=y
+CONFIG_CMD_I2C=y
+# CONFIG_CMD_LOADB is not set
+# CONFIG_CMD_LOADS is not set
+CONFIG_CMD_MMC=y
+CONFIG_AML_STORAGE=y
+# CONFIG_CMD_PINMUX is not set
+CONFIG_CMD_USB=y
+CONFIG_CMD_SARADC=y
+# CONFIG_CMD_ITEST is not set
+# CONFIG_CMD_SETEXPR is not set
+CONFIG_CMD_BMP=y
+# CONFIG_CMD_MISC is not set
+CONFIG_BOOTLOADER_CONTROL_BLOCK=y
+CONFIG_CMD_BOOTCTOL_AVB=y
+CONFIG_CMD_WATCHDOG=y
+CONFIG_CMD_JTAG=y
+CONFIG_CMD_INI=y
+CONFIG_AML_PARTITION=y
+CONFIG_OF_CONTROL=y
+CONFIG_OF_EMBED=y
+CONFIG_DEFAULT_DEVICE_TREE="meson-t7-t319"
+CONFIG_ENV_IS_IN_STORAGE=y
+# CONFIG_REGMAP is not set
+CONFIG_ADC=y
+CONFIG_SARADC_MESON_G12A=y
+CONFIG_CLK=y
+CONFIG_CLK_MESON=y
+CONFIG_CLK_MESON_T7=y
+CONFIG_USB_FUNCTION_FASTBOOT=y
+CONFIG_FASTBOOT_FLASH=y
+CONFIG_FASTBOOT_FLASH_MMC_DEV=1
+CONFIG_DM_GPIO=y
+CONFIG_DM_I2C=y
+CONFIG_SYS_I2C_MESON=y
+CONFIG_MISC=y
+CONFIG_DM_MMC=y
+CONFIG_MMC_HS400_SUPPORT=y
+CONFIG_MMC_MESON_GX=y
+CONFIG_DM_ETH=y
+CONFIG_PHY=y
+CONFIG_AML_USB3_PHY=y
+CONFIG_AML_USB2_PHY=y
+CONFIG_PINCTRL=y
+CONFIG_PINCONF=y
+CONFIG_PINCTRL_MESON_T7=y
+CONFIG_DM_REGULATOR=y
+CONFIG_DEBUG_UART_MESON=y
+CONFIG_DEBUG_UART_ANNOUNCE=y
+CONFIG_DEBUG_UART_SKIP_INIT=y
+CONFIG_MESON_SERIAL=y
+CONFIG_TEE=y
+CONFIG_OPTEE=y
+CONFIG_USB=y
+CONFIG_DM_USB=y
+CONFIG_AML_USB=y
+CONFIG_USB_XHCI_HCD=y
+CONFIG_USB_XHCI_CRG=y
+CONFIG_USB_GADGET=y
+CONFIG_USB_GADGET_CRG=y
+CONFIG_AML_V3_FACTORY_BURN=y
+CONFIG_AML_V3_USB_TOOl=y
+CONFIG_WDT=y
+CONFIG_WDT_MESON=y
+CONFIG_AML_DRIVER=y
+CONFIG_AML_MEDIA=y
+CONFIG_AML_VOUT=y
+CONFIG_AML_OSD=y
+CONFIG_AML_VPP=y
+CONFIG_AML_VPU=y
+CONFIG_AML_LCD=y
+CONFIG_AML_LCD_TV=y
+CONFIG_AML_LCD_TABLET=y
+CONFIG_AML_LCD_BACKLIGHT=y
+CONFIG_UNIFY_KEY_MANAGE=y
+CONFIG_SECURE_STORAGE=y
+CONFIG_SECURE_POWER_CONTROL=y
+CONFIG_EFUSE=y
+CONFIG_SHA1=y
diff --git a/board/amlogic/g12a_u200_v1/Kconfig b/board/amlogic/g12a_u200_v1/Kconfig
index 3fa92af..16d608b 100644
--- a/board/amlogic/g12a_u200_v1/Kconfig
+++ b/board/amlogic/g12a_u200_v1/Kconfig
@@ -13,4 +13,3 @@
default "g12a_u200_v1"
endif
-
diff --git a/board/amlogic/g12a_u200_v1/eth_setup.c b/board/amlogic/g12a_u200_v1/eth_setup.c
index 6cbcd95..c5aac45 100644
--- a/board/amlogic/g12a_u200_v1/eth_setup.c
+++ b/board/amlogic/g12a_u200_v1/eth_setup.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * board/amlogic/txl_skt_v1/eth_setup.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <common.h>
#include <malloc.h>
diff --git a/board/amlogic/g12a_u200_v1/firmware/ramdump.c b/board/amlogic/g12a_u200_v1/firmware/ramdump.c
index e03dcd2..d0ae3ff 100644
--- a/board/amlogic/g12a_u200_v1/firmware/ramdump.c
+++ b/board/amlogic/g12a_u200_v1/firmware/ramdump.c
@@ -1,3 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifdef CONFIG_MDUMP_COMPRESS
#include "ramdump.h"
diff --git a/board/amlogic/g12a_u200_v1/firmware/ramdump.h b/board/amlogic/g12a_u200_v1/firmware/ramdump.h
index 0671567..1dbfeb8 100644
--- a/board/amlogic/g12a_u200_v1/firmware/ramdump.h
+++ b/board/amlogic/g12a_u200_v1/firmware/ramdump.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __RAM_DUMP_H__
#define __RAM_DUMP_H__
diff --git a/board/amlogic/g12a_u200_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/g12a_u200_v1/firmware/scp_task/pwm_ctrl.h
index 93b0335..ff7f6d5 100644
--- a/board/amlogic/g12a_u200_v1/firmware/scp_task/pwm_ctrl.h
+++ b/board/amlogic/g12a_u200_v1/firmware/scp_task/pwm_ctrl.h
@@ -1,7 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
-*board/amlogic/txl_p321_v1/firmware/scp_task/pwm_vol_tab.h
-*table for Dynamic Voltage/Frequency Scaling
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __PWM_CTRL_H__
#define __PWM_CTRL_H__
diff --git a/board/amlogic/g12a_u200_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/g12a_u200_v1/firmware/scp_task/pwr_ctrl.c
index f77a278..24000c6 100644
--- a/board/amlogic/g12a_u200_v1/firmware/scp_task/pwr_ctrl.c
+++ b/board/amlogic/g12a_u200_v1/firmware/scp_task/pwr_ctrl.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * board/amlogic/txl_skt_v1/firmware/scp_task/pwr_ctrl.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <gpio.h>
#include "pwm_ctrl.h"
diff --git a/board/amlogic/g12a_u200_v1/firmware/timing.c b/board/amlogic/g12a_u200_v1/firmware/timing.c
index 8da2106..6fba580 100644
--- a/board/amlogic/g12a_u200_v1/firmware/timing.c
+++ b/board/amlogic/g12a_u200_v1/firmware/timing.c
@@ -1,31 +1,14 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * board/amlogic/txl_skt_v1/firmware/timing.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <asm/arch/secure_apb.h>
#include <asm/arch/timing.h>
#include <asm/arch/ddr_define.h>
/* board clk defines */
-#define DDR_SIZE 0
-#define CPU_CLK 1200
+#define CPU_CLK 1200
/* ddr config support multiple configs for boards which use same bootloader:
* config steps:
@@ -60,19 +43,92 @@
*
*/
-ddr_set_t __ddr_setting[] = {
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = {
{
- /* g12a skt (u209) ddr4 */
+ // g12a 4layer 4pcs ddr4 rank01 (1320)(T204)
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1320, 0, 0, 0},
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0xffff,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 80,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 80, //60,
+ .dram_ac_odt_ohm = 0,
+ .dram_data_wr_odt_ohm = 120,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 8200/12,//700,
+ .vref_dram_permil = 9200/12,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {32+10,32,32+10,32+10,32,32,32+10,32+10,32+10,32+8},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
+ .training_offset = (1<<3) | (4<<0),//read dqs offset after training,bit3=0 right move,bit3=1 left move,bit[2:0] offset step
+},
+{
+ // g12a 4layer 2pcs ddr4 rank0 (1320)(U200)
.board_id = CONFIG_BOARD_ID_MASK,
.version = 1,
.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
.DramType = CONFIG_DDR_TYPE_DDR4,
- .DRAMFreq = {1200, 0, 0, 0},
+ .DRAMFreq = {1320, 0, 0, 0},
.ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
.ddr_base_addr = CFG_DDR_BASE_ADDR,
.ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
.DisabledDbyte = 0xf0,
.Is2Ttiming = 1,
@@ -80,8 +136,8 @@
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0,
.training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -103,7 +159,7 @@
.vref_dram_permil = 0,//700,
//.vref_reverse = 0,
//.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
- .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ac_trace_delay = {32-10,32,32,32,32,32,32,32,32,32},
.ddr_dmc_remap = {
[0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
[1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
@@ -130,10 +186,10 @@
.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
.ddr_func = DDR_FUNC,
.magic = DRAM_CFG_MAGIC,
- .bitTimeControl_2d = 1,
+ .fast_boot[0] = 1,
},
{
- /* g12a skt (u209) ddr3 */
+ // g12a 4layer 4pcs ddr3 rank01 (912)(U212)
.board_id = CONFIG_BOARD_ID_MASK,
.version = 1,
.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
@@ -141,8 +197,8 @@
.DRAMFreq = {912, 0, 0, 0},
.ddr_base_addr = CFG_DDR_BASE_ADDR,
.ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
.DisabledDbyte = 0xf0,
.Is2Ttiming = 1,
@@ -150,8 +206,8 @@
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0xffff,
.training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0c0c,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -188,7 +244,7 @@
.ddr_dmc_remap = {
[0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
[1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
[3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
[4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
},
@@ -212,7 +268,89 @@
.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
.ddr_func = DDR_FUNC,
.magic = DRAM_CFG_MAGIC,
- .bitTimeControl_2d = 1,
+ .fast_boot[0] = 1,
+},
+{
+ // g12a 4layer 2pcs ddr3 rank0 (912)
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
},
{
/* g12a skt (u209) lpddr4 */
@@ -225,8 +363,8 @@
.DRAMFreq = {1392, 0, 0, 0},
.ddr_base_addr = CFG_DDR_BASE_ADDR,
.ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
.DisabledDbyte = 0xf0,
.Is2Ttiming = 0,
@@ -234,8 +372,8 @@
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0xffff,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -287,7 +425,8 @@
.ddr_func = DDR_FUNC,
.magic = DRAM_CFG_MAGIC,
.diagnose = CONFIG_DIAGNOSE_DISABLE,
- .bitTimeControl_2d = 1,
+ .bitTimeControl_2d = 1,
+ .fast_boot[0] = 1,
},
{
/* g12a Y2 dongle */
@@ -300,8 +439,8 @@
.DRAMFreq = {1392, 0, 0, 0},
.ddr_base_addr = CFG_DDR_BASE_ADDR,
.ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
.DisabledDbyte = 0xf0,
.Is2Ttiming = 0,
@@ -309,8 +448,8 @@
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -360,7 +499,9 @@
.ddr_func = DDR_FUNC,
.magic = DRAM_CFG_MAGIC,
.bitTimeControl_2d = 1,
+ .fast_boot[0] = 1,
},
+#if 0
{
/* lpddr3 */
.board_id = CONFIG_BOARD_ID_MASK,
@@ -372,8 +513,8 @@
.DRAMFreq = {600, 0, 0, 0},
.ddr_base_addr = CFG_DDR_BASE_ADDR,
.ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
.DisabledDbyte = 0xf0,
.Is2Ttiming = 0,
@@ -381,8 +522,8 @@
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0xffff,//1024,
.training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x00c,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
@@ -420,7 +561,10 @@
.ddr_func = DDR_FUNC,
.magic = DRAM_CFG_MAGIC,
.diagnose = CONFIG_DIAGNOSE_DISABLE,
+ .bitTimeControl_2d = 1,
+ .fast_boot[0] = 1,
},
+#endif
};
pll_set_t __pll_setting = {
diff --git a/board/amlogic/g12a_u200_v1/g12a_u200_v1.c b/board/amlogic/g12a_u200_v1/g12a_u200_v1.c
index 48963c8..533afcd 100644
--- a/board/amlogic/g12a_u200_v1/g12a_u200_v1.c
+++ b/board/amlogic/g12a_u200_v1/g12a_u200_v1.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * board/amlogic/txl_skt_v1/txl_skt_v1.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <common.h>
#include <malloc.h>
@@ -25,7 +9,7 @@
#include <environment.h>
#include <fdt_support.h>
#include <linux/libfdt.h>
-#include <asm/arch/cpu_id.h>
+#include <amlogic/cpu_id.h>
#include <asm/arch/secure_apb.h>
#include <asm/arch/pinctrl_init.h>
#ifdef CONFIG_AML_VPU
@@ -618,11 +602,6 @@
struct mm_region *mem_map = bd_mem_map;
-void board_nand_init(void) {
- printf("board_nand_init\n");
- return;
-}
-
int print_cpuinfo(void) {
printf("print_cpuinfo\n");
return 0;
@@ -638,3 +617,38 @@
/* eg: bl31/32 rsv */
return 0;
}
+
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "dspA",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "dspB",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
diff --git a/board/amlogic/g12a_u200_v1/lcd.c b/board/amlogic/g12a_u200_v1/lcd.c
index c7dc36c..2a02bd0 100644
--- a/board/amlogic/g12a_u200_v1/lcd.c
+++ b/board/amlogic/g12a_u200_v1/lcd.c
@@ -1,25 +1,15 @@
-/*
- * AMLOGIC LCD panel driver.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include <common.h>
#include <amlogic/media/vout/lcd/aml_lcd.h>
#ifdef CONFIG_AML_LCD_EXTERN
-#include "lcd_extern.h"
+//#include "lcd_extern.h"
#endif
-static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
"GPIOZ_9", /* panel rst */
"GPIOZ_8", /* panel power */
"invalid", /* ending flag */
@@ -129,7 +119,7 @@
0xff, 0, //ending
};
-static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
"GPIOH_4", /* BL_EN */
"GPIOH_5", /* BL_PWM */
"invalid", /* ending flag */
@@ -230,7 +220,7 @@
},
};
-static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+static struct lcd_pinmux_ctrl_s lcd_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
{
.name = "bl_pwm_on_pin", //GPIOH_5
.pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
@@ -241,154 +231,69 @@
},
};
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xc0, 2, 0x01, 0x2b,
+ 0xc0, 2, 0x02, 0x05,
+ 0xc0, 2, 0x03, 0x00,
+ 0xc0, 2, 0x04, 0x00,
+ 0xc0, 2, 0x05, 0x0c,
+ 0xc0, 2, 0x06, 0x04,
+ 0xc0, 2, 0x07, 0x21,
+ 0xc0, 2, 0x08, 0x0f,
+ 0xc0, 2, 0x09, 0x04,
+ 0xc0, 2, 0x0a, 0x00,
+ 0xc0, 2, 0x0b, 0x04,
+ 0xc0, 2, 0xff, 0x00,
+ 0xfd, 1, 100, /* delay 100ms */
+ 0xff, 0, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0} },
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0} },
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "invalid",
+ /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .type = LCD_EXTERN_MAX,
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x20, /* 7bit i2c address */
+ .i2c_addr2 = 0x74, /* 7bit i2c address, 0xff for none */
+ /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_1,
+ .cmd_size = 0xff,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
#ifdef CONFIG_AML_BL_EXTERN
static unsigned char bl_ext_init_on[BL_EXTERN_INIT_ON_MAX] = {
0xff, 0, //ending flag
};
+
static unsigned char bl_ext_init_off[BL_EXTERN_INIT_OFF_MAX] = {
0xff, 0, //ending flag
};
-#endif
-/* **********************************************
- * driver struct, usually no need modify!
- * ********************************************** */
-static struct dsi_config_s lcd_mipi_config = {
- .lane_num = 4,
- .bit_rate_max = 1000, /* MHz */
- .factor_numerator = 0,
- .factor_denominator = 100,
- .operation_mode_init = 1, /* 0=video mode, 1=command mode */
- .operation_mode_display = 0, /* 0=video mode, 1=command mode */
- .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
- .clk_always_hs = 1, /* 0=disable, 1=enable */
- .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
-
- .dsi_init_on = mipi_init_on_table,
- .dsi_init_off = mipi_init_off_table,
- .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
- .check_en = 0,
- .check_state = 0,
-};
-
-static struct lcd_power_ctrl_s lcd_power_ctrl = {
- .power_on_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
- .power_off_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
-};
-
-struct lcd_config_s lcd_config_dft = {
- .lcd_mode = LCD_MODE_TABLET,
- .lcd_key_valid = 0,
- .lcd_clk_path = 0,
- .lcd_basic = {
- .model_name = "default",
- .lcd_type = LCD_TYPE_MAX,
- .lcd_bits = 8,
- .h_active = 768,
- .v_active = 1024,
- .h_period = 948,
- .v_period = 1140,
-
- .screen_width = 119,
- .screen_height = 159,
- },
-
- .lcd_timing = {
- .clk_auto = 1,
- .lcd_clk = 64843200,
- .ss_level = 0,
- .fr_adjust_type = 0,
-
- .hsync_width = 64,
- .hsync_bp = 56,
- .hsync_pol = 0,
- .vsync_width = 50,
- .vsync_bp = 30,
- .vsync_pol = 0,
- },
-
- .lcd_control = {
- .mipi_config= &lcd_mipi_config,
- },
- .lcd_power = &lcd_power_ctrl,
-
- .pinctrl_ver = 2,
- .lcd_pinmux = lcd_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_LCD_EXTERN
-struct lcd_extern_common_s ext_common_dft = {
- .lcd_ext_key_valid = 0,
- .i2c_bus = LCD_EXTERN_I2C_BUS_0, /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
- .i2c_gpio_sck = LCD_EXT_I2C_GPIO_SCK,
- .i2c_gpio_sda = LCD_EXT_I2C_GPIO_SDA,
- .spi_gpio_cs = LCD_EXT_SPI_GPIO_CS,
- .spi_gpio_clk = LCD_EXT_SPI_GPIO_CLK,
- .spi_gpio_data = LCD_EXT_SPI_GPIO_DATA,
-
- .lcd_ext_pinmux = lcd_ext_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
- .pinmux_gpio_off = LCD_EXT_PINMUX_GPIO_OFF,
-};
-
-struct lcd_extern_config_s ext_config_dtf = {
- .index = 0,
- .name = "ext_default",
- .type = LCD_EXTERN_MAX, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 0, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
-};
-#endif
-
-struct bl_config_s bl_config_dft = {
- .name = "default",
- .bl_key_valid = 0,
-
- .level_default = 100,
- .level_min = 10,
- .level_max = 255,
- .level_mid = 128,
- .level_mid_mapping = 128,
- .level = 0,
-
- .method = BL_CTRL_MAX,
- .power_on_delay = 200,
- .power_off_delay = 200,
-
- .en_gpio = 0xff,
- .en_gpio_on = 1,
- .en_gpio_off = 0,
-
- .bl_pwm = NULL,
- .bl_pwm_combo0 = NULL,
- .bl_pwm_combo1 = NULL,
- .pwm_on_delay = 10,
- .pwm_off_delay = 10,
-
- .bl_extern_index = 0xff,
-
- .pinctrl_ver = 2,
- .bl_pinmux = bl_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_BL_EXTERN
struct bl_extern_config_s bl_extern_config_dtf = {
.index = BL_EXTERN_INDEX_INVALID,
.name = "none",
@@ -406,55 +311,32 @@
.init_off_cnt = sizeof(bl_ext_init_off),
};
#endif
-/* ********************************************** */
+
+/***************************************************
+ * lcd default config
+ ***************************************************/
+static struct lcd_dft_config_s lcd_dft_conf = {
+ .lcd_gpio = lcd_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd_config,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd_bl_gpio,
+ .bl_pinmux = lcd_bl_pinmux_ctrl,
+};
void lcd_config_bsp_init(void)
{
- int i, j;
- char *str;
- struct ext_lcd_config_s *ext_lcd = NULL;
+ struct aml_lcd_data_s *pdata = aml_lcd_get_data();
- /* init config, usually no need modify */
- for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
- break;
- strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
- }
- for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
- strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
- for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
- break;
- strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
- }
- for (j = i; j < BL_GPIO_NUM_MAX; j++)
- strcpy(bl_config_dft.gpio_name[j], "invalid");
-
-#ifdef CONFIG_AML_LCD_EXTERN
- for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
- break;
- strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
- }
- for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
- strcpy(ext_common_dft.gpio_name[j], "invalid");
-#endif
-
- /* select special config */
- str = env_get("panel_type");
- if (str == NULL)
- return;
- for (i = 0 ; i < LCD_NUM_MAX ; i++) {
- ext_lcd = &ext_lcd_config[i];
- if (strcmp(ext_lcd->panel_type, str) == 0) {
-#ifdef CONFIG_AML_LCD_EXTERN
- j = ext_lcd->if_attr_val9; /* mipi extern_index */
- if (j < sizeof(ext_config)/sizeof(struct lcd_extern_config_s)) {
- memcpy(&ext_config_dtf, &ext_config[j],
- sizeof(struct lcd_extern_config_s));
- }
-#endif
- break;
- }
- }
+ if (pdata)
+ pdata->dft_conf[0] = &lcd_dft_conf;
}
+
diff --git a/board/amlogic/g12a_u200_v1/lcd_extern.h b/board/amlogic/g12a_u200_v1/lcd_extern.h
index fb82b41..c5edab0 100644
--- a/board/amlogic/g12a_u200_v1/lcd_extern.h
+++ b/board/amlogic/g12a_u200_v1/lcd_extern.h
@@ -1,18 +1,8 @@
-/*
- * board/amlogic/g12a_u200_v1/lcd_extern.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef _DFT_LCD_EXTERN_H_
#define _DFT_LCD_EXTERN_H_
diff --git a/board/amlogic/g12b_newman_bx/Kconfig b/board/amlogic/g12b_newman_bx/Kconfig
deleted file mode 100644
index 002c37c..0000000
--- a/board/amlogic/g12b_newman_bx/Kconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-if TARGET_G12B_NEWMAN_BX
-
-config SYS_BOARD
- default "g12b_newman_bx"
-
-config SYS_VENDOR
- default "amlogic"
-
-config SYS_CONFIG_NAME
- default "g12b_newman_bx"
-
-config CONFIG_AML_ANTIROLLBACK
- bool
- default n
-
-config ZIRCON_BOOT_IMAGE
- bool "Zircon boot image support"
- default n
-
-endif
-
diff --git a/board/amlogic/g12b_newman_bx/Makefile b/board/amlogic/g12b_newman_bx/Makefile
deleted file mode 100644
index e2f2b99..0000000
--- a/board/amlogic/g12b_newman_bx/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-
-obj-y += $(BOARD).o eth_setup.o
-obj-$(CONFIG_AML_LCD) += lcd.o
-obj-$(CONFIG_ZIRCON_BOOT_IMAGE) += zircon.o
diff --git a/board/amlogic/g12b_newman_bx/aml-user-key.sig b/board/amlogic/g12b_newman_bx/aml-user-key.sig
deleted file mode 100644
index 2ceabc1..0000000
--- a/board/amlogic/g12b_newman_bx/aml-user-key.sig
+++ /dev/null
Binary files differ
diff --git a/board/amlogic/g12b_newman_bx/eth_setup.c b/board/amlogic/g12b_newman_bx/eth_setup.c
deleted file mode 100644
index 85a1b35..0000000
--- a/board/amlogic/g12b_newman_bx/eth_setup.c
+++ /dev/null
@@ -1,51 +0,0 @@
-
-/*
- * board/amlogic/g12b_w400_v1/eth_setup.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <malloc.h>
-#include <errno.h>
-#include <environment.h>
-#include <fdt_support.h>
-#include <linux/libfdt.h>
-#include <asm/arch/eth_setup.h>
-/*
- *
- *setup eth device board socket
- *
- */
-struct eth_board_socket* eth_board_setup(char *name){
- struct eth_board_socket* new_board;
- new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
- if (NULL == new_board) return NULL;
- if (name != NULL) {
- new_board->name=(char*)malloc(strlen(name));
- strncpy(new_board->name,name,strlen(name));
- }else{
- new_board->name="gxb";
- }
-
- new_board->eth_pinmux_setup=NULL ;
- new_board->eth_clock_configure=NULL;
- new_board->eth_hw_reset=NULL;
- return new_board;
-}
-//pinmux HHI_GCLK_MPEG1[bit 3]
-//
diff --git a/board/amlogic/g12b_newman_bx/firmware/scp_task/pwm_ctrl.h b/board/amlogic/g12b_newman_bx/firmware/scp_task/pwm_ctrl.h
deleted file mode 100644
index 549ce96..0000000
--- a/board/amlogic/g12b_newman_bx/firmware/scp_task/pwm_ctrl.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
-*board/amlogic/g12b_newman_bx/firmware/scp_task/pwm_ctrl.h
-*table for Dynamic Voltage/Frequency Scaling
-*/
-#ifndef __PWM_CTRL_H__
-#define __PWM_CTRL_H__
-
-static int pwm_voltage_table_ee[][2] = {
- { 0x1c0000, 681},
- { 0x1b0001, 691},
- { 0x1a0002, 701},
- { 0x190003, 711},
- { 0x180004, 721},
- { 0x170005, 731},
- { 0x160006, 741},
- { 0x150007, 751},
- { 0x140008, 761},
- { 0x130009, 772},
- { 0x12000a, 782},
- { 0x11000b, 792},
- { 0x10000c, 802},
- { 0x0f000d, 812},
- { 0x0e000e, 822},
- { 0x0d000f, 832},
- { 0x0c0010, 842},
- { 0x0b0011, 852},
- { 0x0a0012, 862},
- { 0x090013, 872},
- { 0x080014, 882},
- { 0x070015, 892},
- { 0x060016, 902},
- { 0x050017, 912},
- { 0x040018, 922},
- { 0x030019, 932},
- { 0x02001a, 942},
- { 0x01001b, 952},
- { 0x00001c, 962}
-};
-
-#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/g12b_newman_bx/firmware/scp_task/pwr_ctrl.c b/board/amlogic/g12b_newman_bx/firmware/scp_task/pwr_ctrl.c
deleted file mode 100644
index 9e68da7..0000000
--- a/board/amlogic/g12b_newman_bx/firmware/scp_task/pwr_ctrl.c
+++ /dev/null
@@ -1,143 +0,0 @@
-
-/*
- * board/amlogic/g12b_newman_bx/firmware/scp_task/pwr_ctrl.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <gpio.h>
-#include "pwm_ctrl.h"
-#ifdef CONFIG_CEC_WAKEUP
-#include <cec_tx_reg.h>
-#endif
-
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
-static void set_vddee_voltage(unsigned int target_voltage)
-{
- unsigned int to;
-
- for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
- if (pwm_voltage_table_ee[to][1] >= target_voltage) {
- break;
- }
- }
-
- if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
- to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
- }
-
- writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
-}
-
-static void power_off_at_24M(unsigned int suspend_from)
-{
- /*set test_n low to power off vcck & vcc 3.3v*/
- writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
- writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
- writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
-
- /*step down ee voltage*/
- set_vddee_voltage(AML_VDDEE_SLEEP_VOLTAGE);
-}
-
-static void power_on_at_24M(unsigned int suspend_from)
-{
- /*step up ee voltage*/
- set_vddee_voltage(AML_VDDEE_INIT_VOLTAGE);
-
- /*set test_n low to power on vcck & vcc 3.3v*/
- writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
- writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
- writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
- _udelay(100);
-}
-
-void get_wakeup_source(void *response, unsigned int suspend_from)
-{
- struct wakeup_info *p = (struct wakeup_info *)response;
- unsigned val;
- unsigned i = 0;
-
- p->status = RESPONSE_OK;
- val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
- BT_WAKEUP_SRC);
-
- p->sources = val;
- p->gpio_info_count = i;
-
-}
-extern void __switch_idle_task(void);
-
-static unsigned int detect_key(unsigned int suspend_from)
-{
- int exit_reason = 0;
- unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
- unsigned char adc_key_cnt = 0;
- init_remote();
- saradc_enable();
-#ifdef CONFIG_CEC_WAKEUP
- if (hdmi_cec_func_config & 0x1) {
- remote_cec_hw_reset();
- cec_node_init();
- }
-#endif
-
- do {
- #ifdef CONFIG_CEC_WAKEUP
- if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
- irq[IRQ_AO_CECB] = 0xFFFFFFFF;
- if (cec_power_on_check())
- exit_reason = CEC_WAKEUP;
- }
- #endif
- if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
- irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
- if (remote_detect_key())
- exit_reason = REMOTE_WAKEUP;
- }
-
- if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
- irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
- if (check_adc_key_resume()) {
- adc_key_cnt++;
- /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
- if (2 == adc_key_cnt)
- exit_reason = POWER_KEY_WAKEUP;
- } else {
- adc_key_cnt = 0;
- }
- }
-
- if (exit_reason)
- break;
- else
- __switch_idle_task();
- } while (1);
-
- saradc_disable();
-
- return exit_reason;
-}
-
-static void pwr_op_init(struct pwr_op *pwr_op)
-{
- pwr_op->power_off_at_24M = power_off_at_24M;
- pwr_op->power_on_at_24M = power_on_at_24M;
- pwr_op->detect_key = detect_key;
- pwr_op->get_wakeup_source = get_wakeup_source;
-}
diff --git a/board/amlogic/g12b_newman_bx/firmware/timing.c b/board/amlogic/g12b_newman_bx/firmware/timing.c
deleted file mode 100755
index 7db84a9..0000000
--- a/board/amlogic/g12b_newman_bx/firmware/timing.c
+++ /dev/null
@@ -1,609 +0,0 @@
-
-/*
- * board/amlogic/g12b_newman_bx/firmware/timing.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/timing.h>
-#include <asm/arch/ddr_define.h>
-
-/* board clk defines */
-#define DDR_SIZE 0
-#define CPU_CLK 1200
-
-/* ddr config support multiple configs for boards which use same bootloader:
- * config steps:
- * 1. add a new data struct in __ddr_setting[]
- * 2. config correct board_id, ddr_type, freq, etc..
- */
-
-
-/* CAUTION!! */
-/* Confirm ddr configs with hardware designer,
- * if you don't know how to config, then don't edit it
- */
-
-/* Key configs */
-/*
- * board_id: check hardware adc config
- * dram_rank_config:
- * #define CONFIG_DDR_CHL_AUTO 0xF
- * #define CONFIG_DDR0_16BIT_CH0 0x1
- * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
- * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
- * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
- * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
- * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
- * DramType:
- * #define CONFIG_DDR_TYPE_DDR3 0
- * #define CONFIG_DDR_TYPE_DDR4 1
- * #define CONFIG_DDR_TYPE_LPDDR4 2
- * #define CONFIG_DDR_TYPE_LPDDR3 3
- * DRAMFreq:
- * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
- *
- */
-
-
-/* ddr configs */
-#define DDR_RFC_TYPE_DDR3_512Mbx1 0
-#define DDR_RFC_TYPE_DDR3_512Mbx2 1
-#define DDR_RFC_TYPE_DDR3_512Mbx4 2
-#define DDR_RFC_TYPE_DDR3_512Mbx8 3
-#define DDR_RFC_TYPE_DDR3_512Mbx16 4
-#define DDR_RFC_TYPE_DDR4_2Gbx1 5
-#define DDR_RFC_TYPE_DDR4_2Gbx2 6
-#define DDR_RFC_TYPE_DDR4_2Gbx4 7
-#define DDR_RFC_TYPE_DDR4_2Gbx8 8
-
-#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
-#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
-#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
-
-ddr_set_t __ddr_setting[] = {
-#ifdef CONFIG_DDR_TIMING_DDR4
-{
- /* g12a skt (u209) ddr4 */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
- .DramType = CONFIG_DDR_TYPE_DDR4,
- .DRAMFreq = {912, 0, 0, 0},
- .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 1,
- .HdtCtrl = 0xC8,
- .dram_cs0_size_MB = 2048,
- .dram_cs1_size_MB = 0,
- .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, // // 2rank use 0x23 0x13 1rank use 0x30 0x30 Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //2rank use 0d0d 1rank use 0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .pll_ssc_mode = 0,
- .clk_drv_ohm = 40,
- .cs_drv_ohm = 40,
- .ac_drv_ohm = 40,
- .soc_data_drv_ohm_p = 34,
- .soc_data_drv_ohm_n = 34,
- .soc_data_odt_ohm_p = 60,
- .soc_data_odt_ohm_n = 0,
- .dram_data_drv_ohm = 48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
- .dram_data_odt_ohm = 60,
- .dram_ac_odt_ohm = 0,
- .soc_clk_slew_rate = 0x3ff,
- .soc_cs_slew_rate = 0x3ff,
- .soc_ac_slew_rate = 0x3ff,
- .soc_data_slew_rate = 0x2ff,
- .vref_output_permil = 500,
- .vref_receiver_permil = 700,
- .vref_dram_permil = 700,
- .ac_trace_delay = {00,00},
- .ac_pinmux = {00,00},
- .ddr_dmc_remap = {
- [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
- [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
- },
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap = {00,00},
- .dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
- .pll_ssc_mode = 0,
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
-},
-#endif
-#ifdef CONFIG_DDR_TIMING_DDR3
-{
- /* g12a skt (u209) ddr3 */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- .dram_rank_config = CONFIG_DDR0_16BIT_RANK01_CH0,
- .DramType = CONFIG_DDR_TYPE_DDR3,
- .DRAMFreq = {912, 0, 0, 0},
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 1,
- .HdtCtrl = 0xC8,
- .dram_cs0_size_MB = 1024,
- .dram_cs1_size_MB = 1024,
- .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, // // 2rank use 0x23 0x13 1rank use 0x30 0x30 Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //2rank use 0d0d 1rank use 0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .pll_ssc_mode = 0,
- .clk_drv_ohm = 40,
- .cs_drv_ohm = 40,
- .ac_drv_ohm = 40,
- .soc_data_drv_ohm_p = 34,
- .soc_data_drv_ohm_n = 34,
- .soc_data_odt_ohm_p = 60, //48,
- .soc_data_odt_ohm_n = 0,
- .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
- .dram_data_odt_ohm = 60,
- .dram_ac_odt_ohm = 0,
- .soc_clk_slew_rate = 0x300,
- .soc_cs_slew_rate = 0x300,
- .soc_ac_slew_rate = 0x300,
- .soc_data_slew_rate = 0x200,
- .vref_output_permil = 500,
- .vref_receiver_permil = 500, //700,
- .vref_dram_permil = 500, //700,
- .ac_trace_delay = {00,00},
- .ac_pinmux = {00,00},
- .ddr_dmc_remap = {
- [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
- [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
- },
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap = {00,00},
- .dram_rtt_nom_wr_park = {00,00},
-
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
-},
-#endif
-{
- /* g12a (google) lpddr4 */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- .fast_boot[0]=6,
- //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
- .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01,
- .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1,
- .DramType = CONFIG_DDR_TYPE_LPDDR4,
- .DRAMFreq = {1584, 0, 0, 0},
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 0,
- .HdtCtrl = 0xa,
- .dram_cs0_size_MB = 2048,//1024,
- .dram_cs1_size_MB = 0,//1024,
- .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, // // 2rank use 0x23 0x13 1rank use 0x30 0x30 Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //2rank use 0d0d 1rank use 0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .pll_ssc_mode = 0,
- .clk_drv_ohm = 48,
- .cs_drv_ohm = 48,
- .ac_drv_ohm = 48,
- .soc_data_drv_ohm_p = 48,
- .soc_data_drv_ohm_n = 48,
- .soc_data_odt_ohm_p = 0,
- .soc_data_odt_ohm_n = 48,
- .dram_data_drv_ohm = 48, //lpddr4 sdram only240/1-6
- .dram_data_odt_ohm = 48,//120,// 120,
- .dram_ac_odt_ohm = 120,
- .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
- .soc_clk_slew_rate = 0x3ff,//0x253,
- .soc_cs_slew_rate = 0x100,//0x253,
- .soc_ac_slew_rate = 0x100,//0x253,
- .soc_data_slew_rate = 0x1ff,
- .vref_output_permil = 350,//200,
- .vref_receiver_permil = 0,
- .vref_dram_permil = 0,
- //.vref_reverse = 0,
- .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
- //.ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
- .ac_pinmux = {00,00},
- .ddr_dmc_remap = {
- [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
- [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
- [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
- },
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap =
-//{3,2,0,1,7,6,5,4,14,13,12,15,8,9,11,10,20,21,22,23,16,17,19,18,24,25,28,26,31,30,27,29},
- {3,2,0,1,7,6,5,4, 10,9,14,11,8,12,13,15, 20,21,23,22,18,17,19,16, 28,26,25,24,31,30,27,29},
- .dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
- .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
- .diagnose = CONFIG_DIAGNOSE_DISABLE,
- .bitTimeControl_2d = 1,
- .slt_test_function[0]=DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT,
- //.dqs_adjust={100,100,100,100,100,100,100,100,
- // 100,100,100,100,100,100,100,100,
- //}, //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read
-},
-{
- /* use for repair */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
- .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01,
- .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1,
- .DramType = CONFIG_DDR_TYPE_LPDDR4,
- .DRAMFreq = {1584, 0, 0, 0},
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 0,
- .HdtCtrl = 0xa,
- .dram_cs0_size_MB = 2048,//1024,
- .dram_cs1_size_MB = 0,//1024,
- .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, // // 2rank use 0x23 0x13 1rank use 0x30 0x30 Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //2rank use 0d0d 1rank use 0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .pll_ssc_mode = 0,
- .clk_drv_ohm = 40,
- .cs_drv_ohm = 40,
- .ac_drv_ohm = 40,
- .soc_data_drv_ohm_p = 40,
- .soc_data_drv_ohm_n = 40,
- .soc_data_odt_ohm_p = 0,
- .soc_data_odt_ohm_n = 48,
- .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
- .dram_data_odt_ohm = 40,//120,// 120,
- .dram_ac_odt_ohm = 120,
- .lpddr4_dram_vout_voltage_1_3_2_5_setting = 0,///1, 1/3vddq 0 2/5 vddq
- .soc_clk_slew_rate = 0x3ff,//0x253,
- .soc_cs_slew_rate = 0x100,//0x253,
- .soc_ac_slew_rate = 0x100,//0x253,
- .soc_data_slew_rate = 0x1ff,
- .vref_output_permil = 350,//200,
- .vref_receiver_permil = 0,
- .vref_dram_permil = 0,
- //.vref_reverse = 0,
- .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
- //.ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
- .ac_pinmux = {00,00},
- .ddr_dmc_remap = {
- [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
- [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
- [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
- },
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap =
-//{3,2,0,1,7,6,5,4,14,13,12,15,8,9,11,10,20,21,22,23,16,17,19,18,24,25,28,26,31,30,27,29},
- {3,2,0,1,7,6,5,4, 10,9,14,11,8,12,13,15, 20,21,23,22,18,17,19,16, 28,26,25,24,31,30,27,29},
- .dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
- .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
- .diagnose = CONFIG_DIAGNOSE_DISABLE,
- .bitTimeControl_2d = 1,
- //.dqs_adjust={100,100,100,100,100,100,100,100,
- // 100,100,100,100,100,100,100,100,
- //}, //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read
-},
-{
- /* use for fastboot */
- .board_id= CONFIG_BOARD_ID_MASK,
-},
-};
-
-pll_set_t __pll_setting = {
- .cpu_clk = CPU_CLK / 24 * 24,
-#ifdef CONFIG_PXP_EMULATOR
- .pxp = 1,
-#else
- .pxp = 0,
-#endif
- .spi_ctrl = 0,
- .lCustomerID = AML_CUSTOMER_ID,
-};
-
-ddr_reg_t __ddr_reg[] = {
- /* demo, user defined override register */
- {0xaabbccdd, 0, 0, 0, 0, 0},
- {0x11223344, 0, 0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0},
-};
-
-#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
-#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
-/* VCCK PWM table */
-#if (VCCK_VAL == 800)
- #define VCCK_VAL_REG 0x00150007
-#elif (VCCK_VAL == 810)
- #define VCCK_VAL_REG 0x00140008
-#elif (VCCK_VAL == 820)
- #define VCCK_VAL_REG 0x00130009
-#elif (VCCK_VAL == 830)
- #define VCCK_VAL_REG 0x0012000a
-#elif (VCCK_VAL == 840)
- #define VCCK_VAL_REG 0x0011000b
-#elif (VCCK_VAL == 850)
- #define VCCK_VAL_REG 0x0010000c
-#elif (VCCK_VAL == 860)
- #define VCCK_VAL_REG 0x000f000d
-#elif (VCCK_VAL == 870)
- #define VCCK_VAL_REG 0x000e000e
-#elif (VCCK_VAL == 880)
- #define VCCK_VAL_REG 0x000d000f
-#elif (VCCK_VAL == 890)
- #define VCCK_VAL_REG 0x000c0010
-#elif (VCCK_VAL == 900)
- #define VCCK_VAL_REG 0x000b0011
-#elif (VCCK_VAL == 910)
- #define VCCK_VAL_REG 0x000a0012
-#elif (VCCK_VAL == 920)
- #define VCCK_VAL_REG 0x00090013
-#elif (VCCK_VAL == 930)
- #define VCCK_VAL_REG 0x00080014
-#elif (VCCK_VAL == 940)
- #define VCCK_VAL_REG 0x00070015
-#elif (VCCK_VAL == 950)
- #define VCCK_VAL_REG 0x00060016
-#elif (VCCK_VAL == 960)
- #define VCCK_VAL_REG 0x00050017
-#elif (VCCK_VAL == 970)
- #define VCCK_VAL_REG 0x00040018
-#elif (VCCK_VAL == 980)
- #define VCCK_VAL_REG 0x00030019
-#elif (VCCK_VAL == 990)
- #define VCCK_VAL_REG 0x0002001a
-#elif (VCCK_VAL == 1000)
- #define VCCK_VAL_REG 0x0001001b
-#elif (VCCK_VAL == 1010)
- #define VCCK_VAL_REG 0x0000001c
-#else
- #error "VCCK val out of range\n"
-#endif
-
-/* VDDEE_VAL_REG0: VDDEE PWM table 0.67v-0.97v*/
-/* VDDEE_VAL_REG1: VDDEE PWM table 0.69v-0.89v*/
-#if (VDDEE_VAL == 800)
- #define VDDEE_VAL_REG0 0x0010000c
- #define VDDEE_VAL_REG1 0x0008000a
-#elif (VDDEE_VAL == 810)
- #define VDDEE_VAL_REG0 0x000f000d
- #define VDDEE_VAL_REG1 0x0007000b
-#elif (VDDEE_VAL == 820)
- #define VDDEE_VAL_REG0 0x000e000e
- #define VDDEE_VAL_REG1 0x0006000c
-#elif (VDDEE_VAL == 830)
- #define VDDEE_VAL_REG0 0x000d000f
- #define VDDEE_VAL_REG1 0x0005000d
-#elif (VDDEE_VAL == 840)
- #define VDDEE_VAL_REG0 0x000c0010
- #define VDDEE_VAL_REG1 0x0004000e
-#elif (VDDEE_VAL == 850)
- #define VDDEE_VAL_REG0 0x000b0011
- #define VDDEE_VAL_REG1 0x0003000f
-#elif (VDDEE_VAL == 860)
- #define VDDEE_VAL_REG0 0x000a0012
- #define VDDEE_VAL_REG1 0x00020010
-#elif (VDDEE_VAL == 870)
- #define VDDEE_VAL_REG0 0x00090013
- #define VDDEE_VAL_REG1 0x00010011
-#elif (VDDEE_VAL == 880)
- #define VDDEE_VAL_REG0 0x00080014
- #define VDDEE_VAL_REG1 0x00000012
-#else
- #error "VDDEE val out of range\n"
-#endif
-
-/* for PWM use */
-/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
-#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
-/* GPIOC output enable reg */
-#define GPIO_O_EN_N_REG1 ((0xff634400 + (0x13 << 2)))
-/* GPIOA output enable reg */
-#define GPIO_O_EN_N_REG5 ((0xff634400 + (0x20 << 2)))
-#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
-#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
-/* GPIOC input reg */
-#define GPIO_I_REG1 ((0xff634400 + (0x15 << 2)))
-/* GOUIA input reg */
-#define GPIO_I_REG5 ((0xff634400 + (0x22 << 2)))
-/* GPIOC pull up enable reg */
-#define GPIO_PULL_UP_EN_REG1 ((0xff634400 + (0x49 << 2)))
-/* GPIOA pull up enable reg */
-#define GPIO_PULL_UP_EN_REG5 ((0xff634400 + (0x4d << 2)))
-#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
-#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
-/* GPIOC pinmux reg */
-#define GPIO_PIN_MUX_REG9 ((0xff634400 + (0xb9 << 2)))
-/* GPIOA pinmux reg */
-#define GPIO_PIN_MUX_REGE ((0xff634400 + (0xbe << 2)))
-
-
-bl2_reg_t __bl2_reg[] = {
- /* demo, user defined override register */
- /* eg: PWM init */
-
- /* PWM_AO_D */
- /* VCCK_VAL_REG: check PWM table */
- {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
- {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
-
- /* PWM_AO_B */
-
- /* step1: GPIOC5, GPIOC4, GPIOC6, GPIOA12, GPIOA11 pre-init */
- /* disable pullup/pulldown */
- {GPIO_PULL_UP_EN_REG1, (0 << 4), (7 << 4), 0, BL2_INIT_STAGE_PWM_PRE_INIT, 0},
- {GPIO_PULL_UP_EN_REG5, (0 << 11), (3 << 11), 0, BL2_INIT_STAGE_PWM_PRE_INIT, 0},
- /* enable input */
- {GPIO_O_EN_N_REG1, (7 << 4), (7 << 4), 0, BL2_INIT_STAGE_PWM_PRE_INIT, 0},
- {GPIO_O_EN_N_REG5, (3 << 11), (3 << 11), 0, BL2_INIT_STAGE_PWM_PRE_INIT, 0},
- /* pinmux to gpio */
- {GPIO_PIN_MUX_REG9, (0 << 16), (0xfff << 16), 0, BL2_INIT_STAGE_PWM_PRE_INIT, 0},
- {GPIO_PIN_MUX_REGE, (0 << 11), (0xff << 12), 0, BL2_INIT_STAGE_PWM_PRE_INIT, 0},
-
- /* step2: check board config */
- /* HW_ID_0:GPIOA_11
- * HW_ID_1:GPIOA_12
- * HW_ID_2:GPIOC_6
- * HW_ID_3:GPIOC_4
- * HW_ID_4:GPIOC_5
- */
- {GPIO_I_REG1, 5, 0, 0, BL2_INIT_STAGE_PWM_CHK_HW, 0},
- {GPIO_I_REG1, 4, 0, 0, BL2_INIT_STAGE_PWM_CHK_HW, 0},
- {GPIO_I_REG1, 6, 0, 0, BL2_INIT_STAGE_PWM_CHK_HW, 0},
- {GPIO_I_REG5, 12, 0, 0, BL2_INIT_STAGE_PWM_CHK_HW, 0},
- {GPIO_I_REG5, 11, 0, 0, BL2_INIT_STAGE_PWM_CHK_HW, 0},
-
- /* step3: match PWM config */
- /* -----------------------------
- * |newman | option| build |
- * -----------------------------
- * |BRD_ID | 4 | 3 | 2 | 1 | 0 |
- * -----------------------------
- * | | 0 | 1 | 0 | 0 | 0 |
- * -----------------------------
- * | | 0 | 1 | 0 | 0 | 1 |
- * -----------------------------
- * | P1 | 0 | 1 | 0 | 1 | 0 |
- * -----------------------------
- * | P2 | 0 | 1 | 0 | 1 | 1 |
- * -----------------------------
- * | P2RW | 0 | 1 | 1 | 0 | 0 |
- * -----------------------------
- * | P2.1 | 0 | 1 | 1 | 0 | 1 |
- * -----------------------------
- * | EVT | 0 | 1 | 1 | 1 | 0 |
- * -----------------------------
- * | | 0 | 1 | 1 | 1 | 1 |
- * -----------------------------
- * | DVT | 1 | 0 | 0 | 0 | 0 |
- * -----------------------------
- *
- * option = b'01 and build < b'011, use PWM_CFG0
- * option = b'01 and build = b'011, use PWM_CFG2 GPIOE_0 output low
- * option = b'01 and build > b'011, use PWM_CFG1
- * option = b'10, use PWM_CFG1
- */
- {0x8, PWM_CFG0, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0x9, PWM_CFG0, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0xa, PWM_CFG0, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0xb, PWM_CFG2, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0xc, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0xd, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0xe, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0xf, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0x10, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0x11, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0x12, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
-
- /* step4: config PWM */
- /* PWM_CFG0: VDDEE PWM table 0.67v ~ 0.97v */
- {AO_PWM_PWM_B, VDDEE_VAL_REG0, 0xffffffff, 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0},
- {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0},
- {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0},
- /* PWM_CFG1: VDDEE PWM table 0.69v ~ 0.89v */
- {AO_PWM_PWM_B, VDDEE_VAL_REG1, 0xffffffff, 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0},
- {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0},
- {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0},
-
- /* PWM_CFG2: VDDEE PWM low; table 0.69v ~ 0.90v */
- {AO_PIN_MUX_REG1, 0, (0xF << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG2, 0},
- {AO_GPIO_O_EN_N, 0, (0x1 << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG2, 0},
- {AO_GPIO_O, 0, (0x1 << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG2, 0},
-
- //GPIOAO_4 set high
- {AO_GPIO_O_EN_N, (0<<4), (1<<4), 0, BL2_INIT_STAGE_1, 0},
- {AO_GPIO_O, (1<<4), (1<<4), 0, BL2_INIT_STAGE_1, 0},
- /* Enable 5V_EN */
- {GPIO_O_EN_N_REG3, (0 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
- {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- /* Enable VCCK */
- {AO_SEC_REG0, (1 << 0), 0x1, 0, BL2_INIT_STAGE_1, 0},
- {AO_GPIO_O, 0x80000000, 0x80000000, 0, BL2_INIT_STAGE_1, 0},
-};
diff --git a/board/amlogic/g12b_newman_bx/g12b_newman_bx.c b/board/amlogic/g12b_newman_bx/g12b_newman_bx.c
deleted file mode 100644
index 87ccefd..0000000
--- a/board/amlogic/g12b_newman_bx/g12b_newman_bx.c
+++ /dev/null
@@ -1,1188 +0,0 @@
-
-/*
- * board/amlogic/g12b_newman_px/g12b_newman_px.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <malloc.h>
-#include <errno.h>
-#include <environment.h>
-#include <fdt_support.h>
-#include <linux/libfdt.h>
-#include <asm/arch/cpu_id.h>
-#ifdef CONFIG_SYS_I2C_MESON
-#include <i2c.h>
-#include <dt-bindings/i2c/meson-i2c.h>
-#endif
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/pinctrl_init.h>
-#ifdef CONFIG_AML_VPU
-#include <amlogic/media/vpu/vpu.h>
-#endif
-#ifdef CONFIG_AML_VPP
-#include <amlogic/media/vpp/vpp.h>
-#endif
-#ifdef CONFIG_AML_V2_FACTORY_BURN
-#include <amlogic/aml_v2_burning.h>
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
-#ifdef CONFIG_AML_HDMITX
-#include <amlogic/media/vout/hdmitx.h>
-#endif
-#ifdef CONFIG_AML_LCD
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#endif
-#include <asm/arch/eth_setup.h>
-#include <phy.h>
-#include <linux/mtd/partitions.h>
-#include <linux/sizes.h>
-#include <asm-generic/gpio.h>
-#include <dm.h>
-#ifdef CONFIG_AML_SPIFC
-#include <amlogic/spifc.h>
-#endif
-#ifdef CONFIG_AML_SPICC
-#include <amlogic/spicc.h>
-#endif
-#include <asm/armv8/mmu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-//new static eth setup
-struct eth_board_socket* eth_board_skt;
-
-int do_get_ddictype (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-#if defined(CONFIG_NAND_FTS) || defined(CONFIG_MMC_FTS)
-#if defined(CONFIG_NAND_FTS)
- extern bool amlnf_is_inited(void);
- if (!amlnf_is_inited()) {
-#endif
-
-#if defined(CONFIG_MMC_FTS)
- extern bool amlmmc_is_inited(void);
- if (!amlmmc_is_inited()) {
-#endif
- env_set("ddic_type", "FITI");
- return 0;
- }
-
- flash_ts_init();
-
- const char *fts_key = "ddic.type";
-
- char fts_value[256] = { 0 };
- flash_ts_get(fts_key, fts_value, sizeof(fts_value));
-
- printf("FTS read: ddic.type -> %s\n", fts_value);
-
- if (strncmp(fts_value, "NOVATEK", sizeof(fts_value)) == 0) {
- env_set("ddic_type", "NOVATEK");
- } else {
- env_set("ddic_type", "FITI");
- }
-#endif
- return 0;
-}
-
-U_BOOT_CMD(
- get_ddictype, 1, 0, do_get_ddictype,
- "get ddic type",
- " This command will get and setenv 'ddic_type'\n"
-);
-
-int do_get_cpu_rev(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- cpu_id_t cpu_id = get_cpu_id();
- char rev[3] = { 0 };
-
- if (cpu_id.family_id == MESON_CPU_MAJOR_ID_G12B) {
- rev[0] = cpu_id.chip_rev;
- snprintf(rev, sizeof(rev), "%x", cpu_id.chip_rev);
- } else {
- snprintf(rev, sizeof(rev), "%d", -1);
- }
-
- env_set("cpu_rev", rev);
-
- return 0;
-}
-
-U_BOOT_CMD(
- get_cpu_rev, 1, 0, do_get_cpu_rev,
- "get cpu revision",
- " This command will get and setenv 'cpu_rev'\n"
-);
-
-// Disable pull-up resistors for GPIOA_11, GPIOA_12, GPIOC_4, GPIOC_5, GPIOC_6,
-// and GPIOH_3 so the mute switch status and HW ID can be read.
-// Disable pull-up resistors for GPIOAO_1
-static void gpio_disable_pullup(void)
-{
- int ret;
-
- ret = readl(PAD_PULL_UP_EN_REG5);
- writel(ret & (~(1 << 11)), PAD_PULL_UP_EN_REG5);
-
- ret = readl(PAD_PULL_UP_EN_REG5);
- writel(ret & (~(1 << 12)), PAD_PULL_UP_EN_REG5);
-
- ret = readl(PAD_PULL_UP_EN_REG1);
- writel(ret & (~(1 << 4)), PAD_PULL_UP_EN_REG1);
-
- ret = readl(PAD_PULL_UP_EN_REG1);
- writel(ret & (~(1 << 5)), PAD_PULL_UP_EN_REG1);
-
- ret = readl(PAD_PULL_UP_EN_REG1);
- writel(ret & (~(1 << 6)), PAD_PULL_UP_EN_REG1);
-
- ret = readl(PAD_PULL_UP_EN_REG3);
- writel(ret & (~(1 << 3)), PAD_PULL_UP_EN_REG3);
-
- // UART RX (GPIOAO_1)
- ret = readl(AO_RTI_PULL_UP_REG);
- writel(ret & (~(1 << 1)), AO_RTI_PULL_UP_REG);
-}
-
-int do_get_newman_hw_id(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- unsigned int hw_id = 0, ret = 0;
- char hw_id_str[8] = {0}; // eg: 0x0A
-
- // Reading from highest bit to lowest bit
- // HW_ID_4: GPIOC_5
- ret = readl(P_PREG_PAD_GPIO1_I);
- hw_id |= (ret & (1<<5)) >> 5;
- hw_id = hw_id << 1;
-
- // HW_ID_3: GPIOC_4
- ret = readl(P_PREG_PAD_GPIO1_I);
- hw_id |= (ret & (1<<4)) >> 4;
- hw_id = hw_id << 1;
-
- // HW_ID_2: GPIOC_6
- ret = readl(P_PREG_PAD_GPIO1_I);
- hw_id |= (ret & (1<<6)) >> 6;
- hw_id = hw_id << 1;
-
- // HW_ID_1: GPIOA_12
- ret = readl(P_PREG_PAD_GPIO5_I);
- hw_id |= (ret & (1<<12)) >> 12;
- hw_id = hw_id << 1;
-
- // HW_ID_0: GPIOA_11
- ret = readl(P_PREG_PAD_GPIO5_I);
- hw_id |= (ret & (1<<11)) >> 11;
-
- snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id);
- env_set("hw_id", hw_id_str);
- return 0;
-}
-
-U_BOOT_CMD(
- get_newman_hw_id, 1, 0, do_get_newman_hw_id,
- "get newman's HW_ID and setenv 'hw_id'\n",
- "get_newman_hw_id"
-);
-
-int serial_set_pin_port(unsigned long port_base)
-{
- //UART in "Always On Module"
- //GPIOAO_0==tx,GPIOAO_1==rx
- //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
- return 0;
-}
-
-//SOC_BL_ENABLE
-//#define BL_ENABLE_PIN GPIOEE(GPIOA_10)
-#define BL_ENABLE_PIN_NAME "GPIOA_10"
-
-static void enable_backlight(bool enable)
-{
- int ret;
- struct gpio_desc bl_pow_desc;
-
- ret = dm_gpio_lookup_name("gpioa_10", &bl_pow_desc);
- if (ret) {
- printf("%s: not found\n", "gpioa_10");
- return ret;
- }
-
- ret = dm_gpio_request(&bl_pow_desc, BL_ENABLE_PIN_NAME);
- if (ret && ret != -EBUSY) {
- printf("gpio: requesting pin %s failed\n", BL_ENABLE_PIN_NAME);
- return;
- }
- //gpio_direction_output(BL_ENABLE_PIN, enable ? 1 : 0);
- ret = dm_gpio_set_dir_flags(&bl_pow_desc, GPIOD_IS_OUT);
- if (ret) {
- printf("set direction failed\n");
- return ret;
- }
-
- dm_gpio_set_value(&bl_pow_desc, enable ? 1 : 0);
-}
-
-int dram_init(void)
-{
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-/* secondary_boot_func
- * this function should be write with asm, here, is is only for compiling pass
- * */
-void secondary_boot_func(void)
-{
-}
-#ifdef ETHERNET_INTERNAL_PHY
-void internalPhyConfig(struct phy_device *phydev)
-{
-}
-
-static int dwmac_meson_cfg_pll(void)
-{
- writel(0x39C0040A, P_ETH_PLL_CTL0);
- writel(0x927E0000, P_ETH_PLL_CTL1);
- writel(0xAC5F49E5, P_ETH_PLL_CTL2);
- writel(0x00000000, P_ETH_PLL_CTL3);
- udelay(200);
- writel(0x19C0040A, P_ETH_PLL_CTL0);
- return 0;
-}
-
-static int dwmac_meson_cfg_analog(void)
-{
- /*Analog*/
- writel(0x20200000, P_ETH_PLL_CTL5);
- writel(0x0000c002, P_ETH_PLL_CTL6);
- writel(0x00000023, P_ETH_PLL_CTL7);
-
- return 0;
-}
-
-static int dwmac_meson_cfg_ctrl(void)
-{
- /*config phyid should between a 0~0xffffffff*/
- /*please don't use 44000181, this has been used by internal phy*/
- writel(0x33000180, P_ETH_PHY_CNTL0);
-
- /*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/
- writel(0x260, P_ETH_PHY_CNTL2);
-
- writel(0x74043, P_ETH_PHY_CNTL1);
- writel(0x34043, P_ETH_PHY_CNTL1);
- writel(0x74043, P_ETH_PHY_CNTL1);
- return 0;
-}
-
-static void setup_net_chip(void)
-{
- eth_aml_reg0_t eth_reg0;
-
- eth_reg0.d32 = 0;
- eth_reg0.b.phy_intf_sel = 4;
- eth_reg0.b.rx_clk_rmii_invert = 0;
- eth_reg0.b.rgmii_tx_clk_src = 0;
- eth_reg0.b.rgmii_tx_clk_phase = 0;
- eth_reg0.b.rgmii_tx_clk_ratio = 4;
- eth_reg0.b.phy_ref_clk_enable = 1;
- eth_reg0.b.clk_rmii_i_invert = 1;
- eth_reg0.b.clk_en = 1;
- eth_reg0.b.adj_enable = 1;
- eth_reg0.b.adj_setup = 0;
- eth_reg0.b.adj_delay = 9;
- eth_reg0.b.adj_skew = 0;
- eth_reg0.b.cali_start = 0;
- eth_reg0.b.cali_rise = 0;
- eth_reg0.b.cali_sel = 0;
- eth_reg0.b.rgmii_rx_reuse = 0;
- eth_reg0.b.eth_urgent = 0;
- setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
-
- dwmac_meson_cfg_pll();
- dwmac_meson_cfg_analog();
- dwmac_meson_cfg_ctrl();
-
- /* eth core clock */
- setbits_le32(HHI_GCLK_MPEG1, (0x1 << 3));
- /* eth phy clock */
- setbits_le32(HHI_GCLK_MPEG0, (0x1 << 4));
-
- /* eth phy pll, clk50m */
- setbits_le32(HHI_FIX_PLL_CNTL3, (0x1 << 5));
-
- /* power on memory */
- clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
-}
-#endif
-
-#ifdef ETHERNET_EXTERNAL_PHY
-
-static int dwmac_meson_cfg_drive_strength(void)
-{
- writel(0xaaaaaaa5, P_PAD_DS_REG4A);
- return 0;
-}
-
-static void setup_net_chip_ext(void)
-{
- eth_aml_reg0_t eth_reg0;
- writel(0x11111111, P_PERIPHS_PIN_MUX_6);
- writel(0x111111, P_PERIPHS_PIN_MUX_7);
-
- eth_reg0.d32 = 0;
- eth_reg0.b.phy_intf_sel = 1;
- eth_reg0.b.rx_clk_rmii_invert = 0;
- eth_reg0.b.rgmii_tx_clk_src = 0;
- eth_reg0.b.rgmii_tx_clk_phase = 1;
- eth_reg0.b.rgmii_tx_clk_ratio = 4;
- eth_reg0.b.phy_ref_clk_enable = 1;
- eth_reg0.b.clk_rmii_i_invert = 0;
- eth_reg0.b.clk_en = 1;
- eth_reg0.b.adj_enable = 0;
- eth_reg0.b.adj_setup = 0;
- eth_reg0.b.adj_delay = 0;
- eth_reg0.b.adj_skew = 0;
- eth_reg0.b.cali_start = 0;
- eth_reg0.b.cali_rise = 0;
- eth_reg0.b.cali_sel = 0;
- eth_reg0.b.rgmii_rx_reuse = 0;
- eth_reg0.b.eth_urgent = 0;
- setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
-
- setbits_le32(HHI_GCLK_MPEG1, 0x1 << 3);
- /* power on memory */
- clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
-}
-#endif
-extern struct eth_board_socket* eth_board_setup(char *name);
-extern int designware_initialize(ulong base_addr, u32 interface);
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_ETHERNET_NONE
- return 0;
-#endif
-
-#ifdef ETHERNET_EXTERNAL_PHY
- dwmac_meson_cfg_drive_strength();
- setup_net_chip_ext();
-#endif
-#ifdef ETHERNET_INTERNAL_PHY
- setup_net_chip();
-#endif
- udelay(1000);
- designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
- return 0;
-}
-
-#if CONFIG_AML_SD_EMMC
-#include <mmc.h>
-#include <asm/arch/sd_emmc.h>
-static int sd_emmc_init(unsigned port)
-{
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
- //todo add card detect
- /* check card detect */
- clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
- setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
- setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
- setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
- break;
- case SDIO_PORT_C:
- //enable pull up
- //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
- break;
- default:
- break;
- }
-
- return cpu_sd_emmc_init(port);
-}
-
-extern unsigned sd_debug_board_1bit_flag;
-
-
-static void sd_emmc_pwr_prepare(unsigned port)
-{
- cpu_sd_emmc_pwr_prepare(port);
-}
-
-static void sd_emmc_pwr_on(unsigned port)
-{
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
-// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
-// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
- /// @todo NOT FINISH
- break;
- case SDIO_PORT_C:
- break;
- default:
- break;
- }
- return;
-}
-static void sd_emmc_pwr_off(unsigned port)
-{
- /// @todo NOT FINISH
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
-// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
-// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
- break;
- case SDIO_PORT_C:
- break;
- default:
- break;
- }
- return;
-}
-
-// #define CONFIG_TSD 1
-static void board_mmc_register(unsigned port)
-{
- struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
- if (aml_priv == NULL)
- return;
-
- aml_priv->sd_emmc_init=sd_emmc_init;
- aml_priv->sd_emmc_detect=sd_emmc_detect;
- aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
- aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
- aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
- aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
-
- if (NULL == aml_priv->desc_buf)
- printf(" desc_buf Dma alloc Fail!\n");
- else
- printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
-
- sd_emmc_register(aml_priv);
-}
-int board_mmc_init(bd_t *bis)
-{
-#if 0
-#ifdef CONFIG_VLSI_EMULATOR
- //board_mmc_register(SDIO_PORT_A);
-#else
- //board_mmc_register(SDIO_PORT_B);
-#endif
- board_mmc_register(SDIO_PORT_B);
- board_mmc_register(SDIO_PORT_C);
-// board_mmc_register(SDIO_PORT_B1);
-#endif
- return 0;
-}
-#endif
-
-/* Skip the first line and parse one uint
- * Return negative if not found */
-int parse_backlight_calibration_file_string(const char *str)
-{
- if (str == NULL)
- return -EINVAL;
-
- str = strchr(str, '\n');
- if (str == NULL)
- return -EINVAL;
- ++str;
-
- return simple_strtoul(str, NULL, 10);
-}
-
-/* If zero, this value has not been set and the default brightness should not be
- * overwritten. To store zero, store a non-zero value with its bottom 12 bits
- * all zero, like 0x1000.
- */
-int get_persistent_brightness(void)
-{
- u32 brightness_sticky_val = readl(AO_RTI_STICKY_REG2);
- if (brightness_sticky_val != 0)
- return (brightness_sticky_val & 0x0fff) >> 1;
- return -1;
-}
-
-int do_configure_backlight(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
-#ifdef CONFIG_SYS_I2C_MESON
- int ret, i, attempt;
- const int retries = 3;
- char *addr_cal;
- int calibrated_current, persistent_brightness;
-
- /* Values to write:
- * [0]: Brightness register control only, backlight enabled
- * [1-2]: Standby disabled, 23 mA MAX_CURRENT,
- * CURRENT scale = 20 * 4095 / 23
- * [3]: Enable undervoltage protection at 2.5 V, "disable" backlight
- * (i2c only), disable set resistors
- * [4]: 6-phase, 6 drivers, 9.6kHz PWM rate
- * [5]: EN_DRV3, EN_DRV2, boost inductor current limit = 1.6 A
- * [6]: VBOOST_MAX = 25 V, JUMP_EN = 0
- * [7]: STEP_UP = 105 mV, STEP_DN = 105 mV, LED_FAULT_TH = 3V,
- * LED_COMP_HYST = DRIVER_HEADROOM + 750 mV
- * [8-9]: 12-bit brightness (default: 33.3%)
- * Important: Write brightness last to apply current calibration */
- const __u8 addrs[] = {0x01, 0xa0, 0xa1, 0xa2, 0xa5, 0xa7, 0xa9, 0xae,
- 0x10, 0x11};
- __u8 values[] = {0x85, 0xd3, 0x4b, 0x20, 0x04, 0xf4, 0x60, 0x09,
- 0x55, 0x05};
- const int n_bytes = sizeof(addrs) / sizeof(addrs[0]);
- struct udevice *bl_devp = NULL;
-
- if (argc > 2) {
- printf("%s: Too many args: %d\n", __func__, argc);
- return CMD_RET_USAGE;
- }
-
- if (argc == 2) {
- addr_cal = (char *)simple_strtoul(argv[1], NULL, 16);
- calibrated_current =
- parse_backlight_calibration_file_string(addr_cal);
- if (calibrated_current >= 0 && calibrated_current <= 4095) {
- /* CURRENT_LSB */
- values[1] = 0xff & calibrated_current;
- /* CURRENT_MSB */
- values[2] = (values[2] & 0xf0) |
- (0x0f & (calibrated_current >> 8));
- }
- }
-
- // Apply persistent brightness if found
- persistent_brightness = get_persistent_brightness();
- if (persistent_brightness >= 0) {
- pr_info("Applying persistent_brightness=%d\n", persistent_brightness);
- /* Get LSB and MSB */
- values[n_bytes - 2] = persistent_brightness & 0xff;
- values[n_bytes - 1] = persistent_brightness >> 8 & 0x0f;
- } else {
- pr_info("Persistent_brightness not set\n");
- }
-
- enable_backlight(true);
-
- ret = i2c_get_chip_for_busnum(MESON_I2C_M3, 0X2c, 1, &bl_devp);
- if (ret) {
- printf("%s(%d):i2c get bus fail!\n", __func__, __LINE__);
- }
-
- for (i = 0; i < n_bytes; ++i) {
- for (attempt = 0; attempt < retries; ++attempt) {
- ret = dm_i2c_write(bl_devp, addrs[i], &values[i], 1);
- if (ret)
- printf("%s: Attempt=%d to write byte=0x%02x to reg=0x%02x of backlight failed\n",
- __func__, attempt, values[i], addrs[i]);
- else
- break;
- }
- }
- return ret;
-#else
- enable_backlight(true);
- return 0;
-#endif /* CONFIG_SYS_I2C_MESON */
-}
-
-U_BOOT_CMD(
- configure_backlight, 2, 0, do_configure_backlight,
- "configures the lp8556 backlight",
- "Usage: configure_backlight [calibration_string_addr]\n"\
- " Sets up required parameters of the backlight.\n"\
- " Default calibration is 100%.\n"\
- " calibration_str_addr (optional):\n"\
- " Address of the calibration file string to parse.\n"
-);
-
-#ifdef CONFIG_AML_LCD
-/* Parses one line of the gamma calibration file. */
-/* Returns true on success. */
-#define GAMMA_SIZE (256)
-bool parse_gamma_string(const char *str, uint16_t *table)
-{
- char buf[4] = {'\0'};
- int i;
-
- for (i = 0; i < GAMMA_SIZE; ++i) {
- strncpy(buf, &str[3 * i], 3);
- table[i] = simple_strtol(buf, NULL, 16);
- }
-
- return true;
-}
-
-/* Check header then parse RGB gamma tables */
-/* Returns negative value on error */
-int parse_gamma_calibration_file_string(const char *str, u16 *r, u16 *g, u16 *b)
-{
- static const char supported_header_prefix[] = "Gamma Calibration 1.";
- static const int length = sizeof(supported_header_prefix) - 1;
- char *tables[3] = {r, g, b};
- const char *start, *end;
- int i;
-
- if (!str)
- return -EINVAL;
-
- // Check header prefix - only care about major version.
- if (strncmp(str, supported_header_prefix, length) != 0) {
- printf("Unknown gamma header: \"%.*s\"\n", length, str);
- return -EINVAL;
- }
-
- // Parse all three tables
- end = strchr(str, '\n');
- for (i = 0; i < 3; ++i) {
- start = end + 1;
- end = strchr(start, '\n');
-
- if ((end - start) / 3 != GAMMA_SIZE) {
- printf("Gamma table has invalid length.\n");
- return -EINVAL;
- }
- if (!parse_gamma_string(start, tables[i])) {
- printf("Could not parse gamma table %d.\n", i);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-#endif // CONFIG_AML_LCD
-
-int do_configure_gamma(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
-#ifdef CONFIG_AML_LCD
- static const int N_CHAN = 3;
- char *addr_cal;
- u16 gamma_tables[N_CHAN][GAMMA_SIZE];
- int i, j;
-
- if (argc == 1) {
- // Set to default
- for (i = 0; i < N_CHAN; ++i) {
- for (j = 0; j < GAMMA_SIZE; ++j)
- gamma_tables[i][j] = j << 2; /* 10-bit */
- }
- } else if (argc == 2) {
- // Load from passed file string
- addr_cal = (char *)simple_strtoul(argv[1], NULL, 16);
- if (parse_gamma_calibration_file_string(addr_cal,
- &gamma_tables[0],
- &gamma_tables[1],
- &gamma_tables[2]) != 0)
- return -EINVAL; // Error logged
- } else {
- return CMD_RET_USAGE;
- }
-
- vpp_set_rgb_gamma_table(&gamma_tables[0], &gamma_tables[1],
- &gamma_tables[2]);
-#endif // CONFIG_AML_LCD
- return 0;
-}
-
-U_BOOT_CMD(configure_gamma, 2, 0, do_configure_gamma,
- "configures gamma the gamma tables with the provided calibration\n",
- "Usage: configure_gamma [calibration_string_addr]\n"\
- " Applies the provided calibration file.\n"\
- " If a file is not provided, sets tables to default.\n"\
- " calibration_str_addr (optional):\n"\
- " Address of the calibration file string to parse.\n"
-);
-
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
-int board_early_init_f(void){
- /*add board early init function here*/
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
-#include <asm/arch/usb-v2.h>
-#include <asm/arch/gpio.h>
-#define CONFIG_GXL_USB_U2_PORT_NUM 2
-
-#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
-#define CONFIG_GXL_USB_U3_PORT_NUM 1
-#else
-#define CONFIG_GXL_USB_U3_PORT_NUM 0
-#endif
-
-static void gpio_set_vbus_power(char is_power_on)
-{
- int ret;
-
- ret = gpio_request(CONFIG_USB_GPIO_PWR,
- CONFIG_USB_GPIO_PWR_NAME);
- if (ret && ret != -EBUSY) {
- printf("gpio: requesting pin %u failed\n",
- CONFIG_USB_GPIO_PWR);
- return;
- }
-
- if (is_power_on) {
- gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
- } else {
- gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
- }
-}
-
-struct amlogic_usb_config g_usb_config_GXL_skt={
- CONFIG_GXL_XHCI_BASE,
- USB_ID_MODE_HARDWARE,
- gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
- CONFIG_GXL_USB_PHY2_BASE,
- CONFIG_GXL_USB_PHY3_BASE,
- CONFIG_GXL_USB_U2_PORT_NUM,
- CONFIG_GXL_USB_U3_PORT_NUM,
- .usb_phy2_pll_base_addr = {
- CONFIG_USB_PHY_20,
- CONFIG_USB_PHY_21,
- }
-};
-
-#endif /*CONFIG_USB_XHCI_AMLOGIC*/
-
-#ifdef CONFIG_AML_HDMITX20
-static void hdmi_tx_set_hdmi_5v(void)
-{
-}
-#endif
-
-#ifdef CONFIG_AML_SPIFC
-/*
- * BOOT_3: NOR_HOLDn:reg0[15:12]=3
- * BOOT_4: NOR_D:reg0[19:16]=3
- * BOOT_5: NOR_Q:reg0[23:20]=3
- * BOOT_6: NOR_C:reg0[27:24]=3
- * BOOT_7: NOR_WPn:reg0[31:28]=3
- * BOOT_14: NOR_CS:reg1[27:24]=3
- */
-#define SPIFC_NUM_CS 1
-static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
-
-static int spifc_pinctrl_enable(void *pinctrl, bool enable)
-{
- unsigned int val;
-
- val = readl(P_PERIPHS_PIN_MUX_0);
- val &= ~(0xfffff << 12);
- if (enable)
- val |= 0x33333 << 12;
- writel(val, P_PERIPHS_PIN_MUX_0);
-
- val = readl(P_PERIPHS_PIN_MUX_1);
- val &= ~(0xf << 24);
- writel(val, P_PERIPHS_PIN_MUX_1);
- return 0;
-}
-
-#if 0
-static const struct spifc_platdata spifc_platdata = {
- .reg = 0xffd14000,
- .mem_map = 0xf6000000,
- .pinctrl_enable = spifc_pinctrl_enable,
- .num_chipselect = SPIFC_NUM_CS,
- .cs_gpios = spifc_cs_gpios,
-};
-
-U_BOOT_DEVICE(spifc) = {
- .name = "spifc",
- .platdata = &spifc_platdata,
-};
-#endif
-#endif /* CONFIG_AML_SPIFC */
-
-#if 0
-#ifdef CONFIG_AML_SPICC
-/* generic config in arch gpio/clock.c */
-extern int spicc1_clk_set_rate(int rate);
-extern int spicc1_clk_enable(bool enable);
-extern int spicc1_pinctrl_enable(bool enable);
-
-static const struct spicc_platdata spicc1_platdata = {
- .compatible = "amlogic,meson-g12a-spicc",
- .reg = (void __iomem *)0xffd15000,
- .clk_rate = 666666666,
- .clk_set_rate = spicc1_clk_set_rate,
- .clk_enable = spicc1_clk_enable,
- .pinctrl_enable = spicc1_pinctrl_enable,
- /* case one slave without cs: {"no_cs", 0} */
- .cs_gpio_names = {"GPIOH_6", 0},
-};
-
-U_BOOT_DEVICE(spicc1) = {
- .name = "spicc",
- .platdata = &spicc1_platdata,
-};
-#endif /* CONFIG_AML_SPICC */
-#endif
-
-extern void aml_pwm_cal_init(int mode);
-
-int board_init(void)
-{
- int ret = 0;
- unsigned char value = 0;
-#ifdef CONFIG_SYS_I2C_MESON
- struct udevice *lcd_devp = NULL;
-#endif
- //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
- //As NOT NEED other board init If USB BOOT MODE
-#ifdef CONFIG_AML_V2_FACTORY_BURN
- *(volatile uint32_t *)P_RESET1_LEVEL |= (3 << 16);
- if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
- aml_try_factory_usb_burning(0, gd->bd);
- }
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
-#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
- board_usb_pll_disable(&g_usb_config_GXL_skt);
- board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
-#endif /*CONFIG_USB_XHCI_AMLOGIC*/
- pinctrl_devices_active(PIN_CONTROLLER_NUM);
- enable_backlight(false);
-
-#ifdef CONFIG_SYS_I2C_MESON
- //board_i2c_init();
- // LCD_BIAS_EN is controlled by GPIOH_8
- /* clear GPIOH_8 pinmux */
- ret = readl(P_PERIPHS_PIN_MUX_C);
- writel(ret & (~(0xf)), P_PERIPHS_PIN_MUX_C);
- /* set input mode */
- ret = readl(P_PREG_PAD_GPIO3_EN_N);
- writel(ret | (1<<8), P_PREG_PAD_GPIO3_EN_N);
-
- udelay(1000);
-
- //set lcd bias voltage
- value = 0x0f; // +/- 5.5V
-
- ret = i2c_get_chip_for_busnum(MESON_I2C_M3, 0X3E, 1, &lcd_devp);
- if (ret) {
- printf("%s(%d):i2c get bus fail!\n", __func__, __LINE__);
- }
-
- ret = dm_i2c_write(lcd_devp, 0x0, &value, 1); // VPOS
- if (ret)
- printf("Failed to set VPOS to 5.5V for LCD\n");
-
- ret = dm_i2c_write(lcd_devp, 0x1, &value, 1); // VNEG
- if (ret)
- printf("Failed to set VNEG to -5.5V for LCD\n");
-#endif
-#if 0
- aml_pwm_cal_init(0);
-#endif//
-#ifdef CONFIG_AML_NAND
- extern int amlnf_init(unsigned char flag);
- amlnf_init(0);
-#endif
-
- gpio_disable_pullup();
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- printf("board late init\n");
- run_command("mmc dev 1", 0);
- run_command("defenv", 0);
- run_command("run detect_panel", 0);
-#if 0
- //update env before anyone using it
- run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
- "if test ${reboot_mode} = factory_reset; then "\
- "defenv_reserv;save; fi;", 0);
- run_command("if itest ${upgrade_step} == 1; then "\
- "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
- /*add board late init function here*/
-#ifndef DTB_BIND_KERNEL
- int ret;
- ret = run_command("store dtb read $dtb_mem_addr", 1);
- if (ret) {
- printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
-#ifdef CONFIG_DTB_MEM_ADDR
- char cmd[64];
- printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
- sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
- ret = run_command(cmd, 1);
- if (ret) {
- printf("%s(): %s fail\n", __func__, cmd);
- }
-#endif
- }
-#elif defined(CONFIG_DTB_MEM_ADDR)
- {
- char cmd[128];
- int ret;
- if (!getenv("dtb_mem_addr")) {
- sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
- run_command(cmd, 0);
- }
- sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
- ret = run_command(cmd, 0);
- if (ret) {
- printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
- }
- }
-#endif// #ifndef DTB_BIND_KERNEL
-
- /* load unifykey */
- run_command("keyunify init 0x1234", 0);
-#endif
-/*open vpu hdmitx and cvbs driver*/
-#ifdef CONFIG_AML_VPU
- vpu_probe();
-#endif
-
-#ifdef CONFIG_AML_VPP
- vpp_init();
-#endif
-
-#ifdef CONFIG_AML_HDMITX
- hdmi_tx_init();
-#endif
-
-#ifdef CONFIG_CMD_CVBS
- run_command("cvbs init", 0);
-#endif
-
-#ifdef CONFIG_AML_LCD
- lcd_probe();
-#endif
-
-#if 0
- /**/
- aml_config_dtb();
-#endif
-#ifdef CONFIG_AML_V2_FACTORY_BURN
- if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
- aml_try_factory_usb_burning(1, gd->bd);
- aml_try_factory_sdcard_burning(0, gd->bd);
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_AML_TINY_USBTOOL
-int usb_get_update_result(void)
-{
- unsigned long upgrade_step;
- upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
- printf("upgrade_step = %d\n", (int)upgrade_step);
- if (upgrade_step == 1)
- {
- run_command("defenv", 1);
- run_command("setenv upgrade_step 2", 1);
- run_command("saveenv", 1);
- return 0;
- }
- else
- {
- return -1;
- }
-}
-#endif
-
-phys_size_t get_effective_memsize(void)
-{
- // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
-#if defined(CONFIG_SYS_MEM_TOP_HIDE)
- return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
-#else
- return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
-#endif
-}
-
-#ifdef CONFIG_MULTI_DTB
-int checkhw(char * name)
-{
- /*
- * read board hw id
- * set and select the dts according the board hw id.
- *
- * hwid = 1 p321 v1
- * hwid = 2 p321 v2
- */
- unsigned int hwid = 1;
- char loc_name[64] = {0};
-
- /* read hwid */
- hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
-
- printf("checkhw: hwid = %d\n", hwid);
-
-
- switch (hwid) {
- case 1:
- strcpy(loc_name, "txl_p321_v1\0");
- break;
- case 2:
- strcpy(loc_name, "txl_p321_v2\0");
- break;
- default:
- strcpy(loc_name, "txl_p321_v1");
- break;
- }
- strcpy(name, loc_name);
- setenv("aml_dt", loc_name);
- return 0;
-}
-#endif
-
-static struct mm_region bd_mem_map[] = {
- {
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = bd_mem_map;
-
-void board_nand_init(void) {
- printf("board_nand_init\n");
- return;
-}
-
-int print_cpuinfo(void) {
- printf("print_cpuinfo\n");
- return 0;
-}
-
-int mach_cpu_init(void) {
- printf("mach_cpu_init\n");
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- /* eg: bl31/32 rsv */
- return 0;
-}
-
-/* workaround for VDDEE issue */
-/* VCCK PWM table */
-#define VCCK_VAL_REG_800 0x00150007
-#define VCCK_VAL_REG_810 0x00140008
-#define VCCK_VAL_REG_820 0x00130009
-#define VCCK_VAL_REG_830 0x0012000a
-#define VCCK_VAL_REG_840 0x0011000b
-#define VCCK_VAL_REG_850 0x0010000c
-#define VCCK_VAL_REG_860 0x000f000d
-#define VCCK_VAL_REG_870 0x000e000e
-#define VCCK_VAL_REG_880 0x000d000f
-#define VCCK_VAL_REG_890 0x000c0010
-#define VCCK_VAL_REG_900 0x000b0011
-#define VCCK_VAL_REG_910 0x000a0012
-#define VCCK_VAL_REG_920 0x00090013
-#define VCCK_VAL_REG_930 0x00080014
-#define VCCK_VAL_REG_940 0x00070015
-#define VCCK_VAL_REG_950 0x00060016
-#define VCCK_VAL_REG_960 0x00050017
-#define VCCK_VAL_REG_970 0x00040018
-#define VCCK_VAL_REG_980 0x00030019
-#define VCCK_VAL_REG_990 0x0002001a
-#define VCCK_VAL_REG_1000 0x0001001b
-#define VCCK_VAL_REG_1010 0x0000001c
-#define VCCK_VAL_REG_DEFAULT1 0x00500008
-#define VCCK_VAL_REG_DEFAULT2 0x00860086
-
-
-/* VDDEE PWM table */
-#define VDDEE_VAL_REG_800 0x0010000c
-#define VDDEE_VAL_REG_810 0x000f000d
-#define VDDEE_VAL_REG_820 0x000e000e
-#define VDDEE_VAL_REG_830 0x000d000f
-#define VDDEE_VAL_REG_840 0x000c0010
-#define VDDEE_VAL_REG_850 0x000b0011
-#define VDDEE_VAL_REG_860 0x000a0012
-#define VDDEE_VAL_REG_870 0x00090013
-#define VDDEE_VAL_REG_880 0x00080014
-#define VDDEE_VAL_REG_890 0x00070015
-#define VDDEE_VAL_REG_900 0x00060016
-#define VDDEE_VAL_REG_910 0x00050017
-#define VDDEE_VAL_REG_920 0x00040018
-#define VDDEE_VAL_REG_930 0x00030019
-#define VDDEE_VAL_REG_940 0x0002001a
-#define VDDEE_VAL_REG_950 0x0001001b
-#define VDDEE_VAL_REG_960 0x0000001c
-#define VDDEE_VAL_REG_DEFAULT 0x00500008
-
-void reset_misc(void)
-{
- unsigned int value;
-
- /* adjust VDDCPU_B to Hiz value step by step */
- writel(VCCK_VAL_REG_830, AO_PWM_PWM_D);
- udelay(1);
- writel(VCCK_VAL_REG_860, AO_PWM_PWM_D);
- udelay(1);
-
- /* GPIOE_0 & GPIOE_1 & GPIOE_2 to gpio pin */
- value = readl(AO_RTI_PINMUX_REG1);
- value &= ~(0xfff << 16);
- writel(value, AO_RTI_PINMUX_REG1);
-
- /* disable pwm_ao_b - VDDEE */
- value = readl(AO_PWM_MISC_REG_AB);
- value &= ~((0x1 << 1) | (0x1 << 23));
- writel(value, AO_PWM_MISC_REG_AB);
- writel(VDDEE_VAL_REG_DEFAULT, AO_PWM_PWM_B);
-
- /* disable pwm_ao_d - VDDCPU_B*/
- value = readl(AO_PWM_MISC_REG_CD);
- value &= ~((0x1 << 1) | (0x1 << 23));
- writel(value, AO_PWM_MISC_REG_CD);
- writel(VCCK_VAL_REG_DEFAULT1, AO_PWM_PWM_D);
-
- /* disable pwm_a - VDDCPU_A */
- value = readl(P_PWM_MISC_REG_AB);
- value &= ~((0x1 << 0) | (0x1 << 15));
- writel(value, P_PWM_MISC_REG_AB);
- writel(VCCK_VAL_REG_DEFAULT2, P_PWM_PWM_A);
-}
diff --git a/board/amlogic/g12b_newman_bx/lcd.c b/board/amlogic/g12b_newman_bx/lcd.c
deleted file mode 100644
index 65d862b..0000000
--- a/board/amlogic/g12b_newman_bx/lcd.c
+++ /dev/null
@@ -1,558 +0,0 @@
-/*
- * AMLOGIC LCD panel driver.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#ifdef CONFIG_AML_LCD_EXTERN
-#include "lcd_extern.h"
-#endif
-
-static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
- "GPIOH_6", /* panel rst */
- "GPIOZ_8", /* panel power */
- "invalid", /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step[] = {
- {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,50,}, /* lcd_reset */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,50,}, /* lcd_reset */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step_TL050FHV02CT[] = {
- {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd reset: 0 */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_TL050FHV02CT[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step_TL070WSH27[] = {
- {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd reset: 0 */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_TL070WSH27[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,10,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
- 0x05, 1, 0x11,
- 0xfd, 1, 20,
- 0x05, 1, 0x29,
- 0xfd, 1, 20,
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
- 0x05, 1, 0x28,
- 0xfd, 1, 10,
- 0x05, 1, 0x10,
- 0xfd, 1, 10,
- 0xff, 0, //ending
-};
-
-static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
- 0xfd, 1, 10,
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
- 0xff, 0, //ending
-};
-
-static unsigned char mipi_init_on_table_TL050FHV02CT[DSI_INIT_ON_MAX] = {//table size < 100
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_TL050FHV02CT[DSI_INIT_OFF_MAX] = {//table size < 50
- 0xff, 0, //ending
-};
-
-static unsigned char mipi_init_on_table_TL070WSH27[DSI_INIT_ON_MAX] = {//table size < 100
- 0x05, 1, 0x11,
- 0xfd, 1, 100,
- 0x05, 1, 0x29,
- 0xfd, 1, 20,
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_TL070WSH27[DSI_INIT_OFF_MAX] = {//table size < 50
- 0x05, 1, 0x28,
- 0xfd, 1, 100,
- 0x05, 1, 0x10,
- 0xfd, 1, 10,
- 0xff, 0, //ending
-};
-
-
-static unsigned char mipi_init_on_table_TV070WSM[DSI_INIT_ON_MAX] = {//table size < 100
- 0xff, 10,
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
- 0xff, 100, /* delay */
- 0xff, 0xff, //ending flag
-};
-
-static unsigned char mipi_init_off_table_TV070WSM[DSI_INIT_OFF_MAX] = {//table size < 50
- 0xff,0xff, //ending flag
-};
-
-
-static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
- "invalid", /* ending flag */
-};
-
-struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
- {/* B080XAN01*/
- "lcd_0",LCD_MIPI,8,
- /* basic timing */
- 768,1024,948,1140,64,56,0,50,30,0,
- /* clk_attr */
- 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
- /* cmd init */
- mipi_init_on_table, mipi_init_off_table,
- /* power step */
- lcd_power_on_step, lcd_power_off_step,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* P070ACB_FT*/
- "lcd_1",LCD_MIPI,8,
- /* basic timing */
- 600,1024,770,1070,10,80,0,6,20,0,
- /* clk_attr */
- 0,0,1,49434000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,400,0,1,0,2,0,0,Rsv_val,1,
- /* cmd init */
- mipi_init_on_table_P070ACB, mipi_init_off_table_P070ACB,
- /* power step */
- lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* TL050FHV02CT*/
- "lcd_2",LCD_MIPI,8,
- /* basic timing */
- 1080,1920,1125,2100,5,30,0,44,108,0,
- /* clk_attr */
- 0,0,1,118125000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,960,0,1,0,2,1,0,Rsv_val,2,
- /* cmd init */
- mipi_init_on_table_TL050FHV02CT, mipi_init_off_table_TL050FHV02CT,
- /* power step */
- lcd_power_on_step_TL050FHV02CT, lcd_power_off_step_TL050FHV02CT,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* TL070WSH27*/
- "lcd_3",LCD_MIPI,8,
- /* basic timing */
- 1024,600,1250,630,80,100,0,5,20,0,
- /* clk_attr */
- 0,0,1,47250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,300,0,1,0,2,1,0,Rsv_val,Rsv_val,
- /* cmd init */
- mipi_init_on_table_TL070WSH27, mipi_init_off_table_TL070WSH27,
- /* power step */
- lcd_power_on_step_TL070WSH27, lcd_power_off_step_TL070WSH27,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* BOE TV101WXM*/
- "boe_nvtk_10",LCD_MIPI,8,
- /* basic timing */
- 800,1280,900,1312,24,48,0,4,12,0,
- /* clk_attr */
- 0,0,1,70956000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,568,0,1,0,2,0,0,Rsv_val,3,
- /* cmd init */
- mipi_init_on_table_TV070WSM, mipi_init_off_table_TV070WSM,
- /* power step */
- lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_MAX,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* INNOLUX G101B158 */
- "inx_nvtk_10",LCD_MIPI,8,
- /* basic timing */
- 800,1280,880,1314,18,18,0,4,10,0,
- /* clk_attr */
- 0,0,1,69380000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,560,0,1,0,2,0,0,Rsv_val,4,
- /* cmd init */
- mipi_init_on_table_P070ACB, mipi_init_off_table_P070ACB,
- /* power step */
- lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_MAX,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* BOE TV101WXM FT */
- "boe_fiti_10",LCD_MIPI,8,
- /* basic timing */
- 800,1280,890,1324,20,50,0,4,20,0,
- /* clk_attr */
- 0,0,1,70701600,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,566,0,1,0,2,0,0,Rsv_val,5,
- /* cmd init */
- mipi_init_on_table_TV070WSM, mipi_init_off_table_TV070WSM,
- /* power step */
- lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_MAX,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* INNOLUX G101B158 FT */
- "inx_fiti_10",LCD_MIPI,8,
- /* basic timing */
- 800,1280,890,1324,24,20,0,4,20,0,
- /* clk_attr */
- 0,0,1,70701600,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,566,0,1,0,2,0,0,Rsv_val,6,
- /* cmd init */
- mipi_init_on_table_P070ACB, mipi_init_off_table_P070ACB,
- /* power step */
- lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_MAX,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {.panel_type = "invalid"},
-};
-
-static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
- {
- .name = "lcd_pin",
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
- },
- {
- .name = "invalid",
- },
-};
-
-static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
- {
- .name = "invalid",
- },
-};
-
-#ifdef CONFIG_AML_BL_EXTERN
-static unsigned char bl_ext_init_on[BL_EXTERN_INIT_ON_MAX] = {
- 0xff, 0, //ending flag
-};
-static unsigned char bl_ext_init_off[BL_EXTERN_INIT_OFF_MAX] = {
- 0xff, 0, //ending flag
-};
-#endif
-
-/* **********************************************
- * driver struct, usually no need modify!
- * ********************************************** */
-static struct dsi_config_s lcd_mipi_config = {
- .lane_num = 4,
- .bit_rate_max = 1000, /* MHz */
- .factor_numerator = 0,
- .factor_denominator = 100,
- .operation_mode_init = 1, /* 0=video mode, 1=command mode */
- .operation_mode_display = 0, /* 0=video mode, 1=command mode */
- .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
- .clk_always_hs = 1, /* 0=disable, 1=enable */
- .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
-
- .dsi_init_on = mipi_init_on_table,
- .dsi_init_off = mipi_init_off_table,
- .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
- .check_en = 0,
- .check_state = 0,
-};
-
-static struct lcd_power_ctrl_s lcd_power_ctrl = {
- .power_on_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
- .power_off_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
-};
-
-struct lcd_config_s lcd_config_dft = {
- .lcd_mode = LCD_MODE_TABLET,
- .lcd_key_valid = 0,
- .lcd_clk_path = 0,
- .lcd_basic = {
- .model_name = "default",
- .lcd_type = LCD_TYPE_MAX,
- .lcd_bits = 8,
- .h_active = 768,
- .v_active = 1024,
- .h_period = 948,
- .v_period = 1140,
-
- .screen_width = 119,
- .screen_height = 159,
- },
-
- .lcd_timing = {
- .clk_auto = 1,
- .lcd_clk = 64843200,
- .ss_level = 0,
- .fr_adjust_type = 0,
-
- .hsync_width = 64,
- .hsync_bp = 56,
- .hsync_pol = 0,
- .vsync_width = 50,
- .vsync_bp = 30,
- .vsync_pol = 0,
- },
-
- .lcd_control = {
- .mipi_config= &lcd_mipi_config,
- },
- .lcd_power = &lcd_power_ctrl,
-
- .pinctrl_ver = 2,
- .lcd_pinmux = lcd_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_LCD_EXTERN
-struct lcd_extern_common_s ext_common_dft = {
- .lcd_ext_key_valid = 0,
- .i2c_bus = LCD_EXTERN_I2C_BUS_0, /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
- .i2c_gpio_sck = LCD_EXT_I2C_GPIO_SCK,
- .i2c_gpio_sda = LCD_EXT_I2C_GPIO_SDA,
- .spi_gpio_cs = LCD_EXT_SPI_GPIO_CS,
- .spi_gpio_clk = LCD_EXT_SPI_GPIO_CLK,
- .spi_gpio_data = LCD_EXT_SPI_GPIO_DATA,
-
- .lcd_ext_pinmux = lcd_ext_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
- .pinmux_gpio_off = LCD_EXT_PINMUX_GPIO_OFF,
-};
-
-struct lcd_extern_config_s ext_config_dtf = {
- .index = 0,
- .name = "ext_default",
- .type = LCD_EXTERN_MAX, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 0, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
-};
-#endif
-
-struct bl_config_s bl_config_dft = {
- .name = "default",
- .bl_key_valid = 0,
-
- .level_default = 100,
- .level_min = 10,
- .level_max = 255,
- .level_mid = 128,
- .level_mid_mapping = 128,
- .level = 0,
-
- .method = BL_CTRL_MAX,
- .power_on_delay = 20,
- .power_off_delay = 20,
-
- .en_gpio = 0xff,
- .en_gpio_on = 1,
- .en_gpio_off = 0,
-
- .bl_pwm = NULL,
- .bl_pwm_combo0 = NULL,
- .bl_pwm_combo1 = NULL,
- .pwm_on_delay = 10,
- .pwm_off_delay = 10,
-
- .bl_extern_index = 0xff,
-
- .pinctrl_ver = 2,
- .bl_pinmux = bl_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_BL_EXTERN
-struct bl_extern_config_s bl_extern_config_dtf = {
- .index = BL_EXTERN_INDEX_INVALID,
- .name = "none",
- .type = BL_EXTERN_MAX,
- .i2c_addr = 0xff,
- .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
- .dim_min = 10,
- .dim_max = 255,
-
- .init_loaded = 0,
- .cmd_size = 0xff,
- .init_on = bl_ext_init_on,
- .init_off = bl_ext_init_off,
- .init_on_cnt = sizeof(bl_ext_init_on),
- .init_off_cnt = sizeof(bl_ext_init_off),
-};
-#endif
-/* ********************************************** */
-
-void lcd_config_bsp_init(void)
-{
- int i, j;
- char *str;
- struct ext_lcd_config_s *ext_lcd = NULL;
-
- /* init config, usually no need modify */
- for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
- break;
- strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
- }
- for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
- strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
- for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
- break;
- strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
- }
- for (j = i; j < BL_GPIO_NUM_MAX; j++)
- strcpy(bl_config_dft.gpio_name[j], "invalid");
-
-#ifdef CONFIG_AML_LCD_EXTERN
- for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
- break;
- strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
- }
- for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
- strcpy(ext_common_dft.gpio_name[j], "invalid");
-#endif
-
- /* select special config */
- str = env_get("panel_type");
- if (str == NULL)
- return;
- for (i = 0 ; i < LCD_NUM_MAX ; i++) {
- ext_lcd = &ext_lcd_config[i];
- if (strcmp(ext_lcd->panel_type, str) == 0) {
-#ifdef CONFIG_AML_LCD_EXTERN
- j = ext_lcd->if_attr_val9; /* mipi extern_index */
- if (j < sizeof(ext_config)/sizeof(struct lcd_extern_config_s)) {
- memcpy(&ext_config_dtf, &ext_config[j],
- sizeof(struct lcd_extern_config_s));
- }
-#endif
- break;
- }
- }
-}
diff --git a/board/amlogic/g12b_newman_bx/lcd_extern.h b/board/amlogic/g12b_newman_bx/lcd_extern.h
deleted file mode 100644
index c0a3c2b..0000000
--- a/board/amlogic/g12b_newman_bx/lcd_extern.h
+++ /dev/null
@@ -1,1860 +0,0 @@
-/*
- * board/amlogic/g12a_u200_v1/lcd_extern.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _DFT_LCD_EXTERN_H_
-#define _DFT_LCD_EXTERN_H_
-
-#define LCD_EXT_I2C_GPIO_SCK 0xff /* 0xff for invalid */
-#define LCD_EXT_I2C_GPIO_SDA 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_CS 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_CLK 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_DATA 0xff /* 0xff for invalid */
-#define LCD_EXT_PINMUX_GPIO_OFF 0
-
-static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
- "invalid", /* ending flag */
-};
-
-static struct lcd_pinmux_ctrl_s lcd_ext_pinmux_ctrl[LCD_PINMX_MAX] = {
- {
- .name = "invalid",
- },
-};
-
-static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
- 0xff, 0, //ending flag
-};
-
-static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
- 0xff, 0, //ending flag
-};
-
-static unsigned char ext_init_on_table_P070ACB_FT[LCD_EXTERN_INIT_ON_MAX] = {
- 0x23,2,0xE0,0x00,//Page 0
- 0x23,2,0xE1,0x93,// PASSWORD
- 0x23,2,0xE2,0x65,
- 0x23,2,0xE3,0xF8,
- 0x23,2,0x80,0x03,
- 0x23,2,0xE0,0x01,//Page 01
- 0x23,2,0x0C,0x74,//Set PWRIC
- 0x23,2,0x17,0x00,//Set Gamma Power
- 0x23,2,0x18,0xEF,//VGMP=5.1V
- 0x23,2,0x19,0x00,
- 0x23,2,0x1A,0x00,
- 0x23,2,0x1B,0xEF,//VGMN=-5.1V
- 0x23,2,0x1C,0x00,
- 0x23,2,0x1F,0x70,//Set Gate Power
- 0x23,2,0x20,0x2D,
- 0x23,2,0x21,0x2D,
- 0x23,2,0x22,0x7E,
- 0x23,2,0x26,0xF3,//VDDD from IOVCC
- 0x23,2,0x37,0x09,//SetPanel
- 0x23,2,0x38,0x04,//SET RGBCYC
- 0x23,2,0x39,0x00,
- 0x23,2,0x3A,0x01,
- 0x23,2,0x3C,0x90,
- 0x23,2,0x3D,0xFF,
- 0x23,2,0x3E,0xFF,
- 0x23,2,0x3F,0xFF,
- 0x23,2,0x40,0x02,//Set TCON
- 0x23,2,0x41,0x80,
- 0x23,2,0x42,0x99,
- 0x23,2,0x43,0x14,
- 0x23,2,0x44,0x19,
- 0x23,2,0x45,0x5A,
- 0x23,2,0x4B,0x04,
- 0x23,2,0x55,0x02,//power voltage
- 0x23,2,0x56,0x01,
- 0x23,2,0x57,0x69,
- 0x23,2,0x58,0x0A,
- 0x23,2,0x59,0x0A,
- 0x23,2,0x5A,0x2E,//VGH = 16.2V
- 0x23,2,0x5B,0x19,//VGL = -12V
- 0x23,2,0x5C,0x15,
- 0x23,2,0x5D,0x77,//Gamma
- 0x23,2,0x5E,0x56,
- 0x23,2,0x5F,0x45,
- 0x23,2,0x60,0x38,
- 0x23,2,0x61,0x35,
- 0x23,2,0x62,0x27,
- 0x23,2,0x63,0x2D,
- 0x23,2,0x64,0x18,
- 0x23,2,0x65,0x33,
- 0x23,2,0x66,0x34,
- 0x23,2,0x67,0x35,
- 0x23,2,0x68,0x56,
- 0x23,2,0x69,0x45,
- 0x23,2,0x6A,0x4F,
- 0x23,2,0x6B,0x42,
- 0x23,2,0x6C,0x40,
- 0x23,2,0x6D,0x34,
- 0x23,2,0x6E,0x25,
- 0x23,2,0x6F,0x02,
- 0x23,2,0x70,0x77,
- 0x23,2,0x71,0x56,
- 0x23,2,0x72,0x45,
- 0x23,2,0x73,0x38,
- 0x23,2,0x74,0x35,
- 0x23,2,0x75,0x27,
- 0x23,2,0x76,0x2D,
- 0x23,2,0x77,0x18,
- 0x23,2,0x78,0x33,
- 0x23,2,0x79,0x34,
- 0x23,2,0x7A,0x35,
- 0x23,2,0x7B,0x56,
- 0x23,2,0x7C,0x45,
- 0x23,2,0x7D,0x4F,
- 0x23,2,0x7E,0x42,
- 0x23,2,0x7F,0x40,
- 0x23,2,0x80,0x34,
- 0x23,2,0x81,0x25,
- 0x23,2,0x82,0x02,
- 0x23,2,0xE0,0x02,//Page2
- 0x23,2,0x00,0x53,//GIP_L Pin mapping RESET_EVEN
- 0x23,2,0x01,0x55,//VSSG_EVEN
- 0x23,2,0x02,0x55,//VSSA_EVEN
- 0x23,2,0x03,0x51,//STV2_EVEN
- 0x23,2,0x04,0x77,//VDD2_EVEN
- 0x23,2,0x05,0x57,//VDD1_EVEN
- 0x23,2,0x06,0x1F,
- 0x23,2,0x07,0x4F, //CK12
- 0x23,2,0x08,0x4D, //CK10
- 0x23,2,0x09,0x1F,
- 0x23,2,0x0A,0x4B, //CK8
- 0x23,2,0x0B,0x49, //CK6
- 0x23,2,0x0C,0x1F,
- 0x23,2,0x0D,0x47, //CK4
- 0x23,2,0x0E,0x45, //CK2
- 0x23,2,0x0F,0x41, //STV1_EVEN
- 0x23,2,0x10,0x1F,
- 0x23,2,0x11,0x1F,
- 0x23,2,0x12,0x1F,
- 0x23,2,0x13,0x55, //VGG
- 0x23,2,0x14,0x1F,
- 0x23,2,0x15,0x1F,
- 0x23,2,0x16,0x52,//GIP_R Pin mapping RESET_ODD
- 0x23,2,0x17,0x55, //VSSG_ODD
- 0x23,2,0x18,0x55, //VSSA_ODD
- 0x23,2,0x19,0x50, //STV2_ODD
- 0x23,2,0x1A,0x77,//VDD2_ODD
- 0x23,2,0x1B,0x57,//VDD1_ODD
- 0x23,2,0x1C,0x1F,
- 0x23,2,0x1D,0x4E, //CK11
- 0x23,2,0x1E,0x4C, //CK9
- 0x23,2,0x1F,0x1F,
- 0x23,2,0x20,0x4A, //CK7
- 0x23,2,0x21,0x48, //CK5
- 0x23,2,0x22,0x1F,
- 0x23,2,0x23,0x46, //CK3
- 0x23,2,0x24,0x44, //CK1
- 0x23,2,0x25,0x40,//STV1_ODD
- 0x23,2,0x26,0x1F,
- 0x23,2,0x27,0x1F,
- 0x23,2,0x28,0x1F,
- 0x23,2,0x29,0x1F,
- 0x23,2,0x2A,0x1F,
- 0x23,2,0x2B,0x55, //VGG
- 0x23,2,0x2C,0x12,//GIP_L_GS Pin mapping
- 0x23,2,0x2D,0x15,
- 0x23,2,0x2E,0x15,
- 0x23,2,0x2F,0x00,
- 0x23,2,0x30,0x37,
- 0x23,2,0x31,0x17,
- 0x23,2,0x32,0x1F,
- 0x23,2,0x33,0x08,
- 0x23,2,0x34,0x0A,
- 0x23,2,0x35,0x1F,
- 0x23,2,0x36,0x0C,
- 0x23,2,0x37,0x0E,
- 0x23,2,0x38,0x1F,
- 0x23,2,0x39,0x04,
- 0x23,2,0x3A,0x06,
- 0x23,2,0x3B,0x10,
- 0x23,2,0x3C,0x1F,
- 0x23,2,0x3D,0x1F,
- 0x23,2,0x3E,0x1F,
- 0x23,2,0x3F,0x15,
- 0x23,2,0x40,0x1F,
- 0x23,2,0x41,0x1F,
- 0x23,2,0x42,0x13,//GIP_R_GS Pin mapping
- 0x23,2,0x43,0x15,
- 0x23,2,0x44,0x15,
- 0x23,2,0x45,0x01,
- 0x23,2,0x46,0x37,
- 0x23,2,0x47,0x17,
- 0x23,2,0x48,0x1F,
- 0x23,2,0x49,0x09,
- 0x23,2,0x4A,0x0B,
- 0x23,2,0x4B,0x1F,
- 0x23,2,0x4C,0x0D,
- 0x23,2,0x4D,0x0F,
- 0x23,2,0x4E,0x1F,
- 0x23,2,0x4F,0x05,
- 0x23,2,0x50,0x07,
- 0x23,2,0x51,0x11,
- 0x23,2,0x52,0x1F,
- 0x23,2,0x53,0x1F,
- 0x23,2,0x54,0x1F,
- 0x23,2,0x55,0x1F,
- 0x23,2,0x56,0x1F,
- 0x23,2,0x57,0x15,
- 0x23,2,0x58,0x40,//GIP Timing
- 0x23,2,0x59,0x00,
- 0x23,2,0x5A,0x00,
- 0x23,2,0x5B,0x10,
- 0x23,2,0x5C,0x14,
- 0x23,2,0x5D,0x40,
- 0x23,2,0x5E,0x01,
- 0x23,2,0x5F,0x02,
- 0x23,2,0x60,0x40,
- 0x23,2,0x61,0x03,
- 0x23,2,0x62,0x04,
- 0x23,2,0x63,0x7A,
- 0x23,2,0x64,0x7A,
- 0x23,2,0x65,0x74,
- 0x23,2,0x66,0x16,
- 0x23,2,0x67,0xB4,
- 0x23,2,0x68,0x16,
- 0x23,2,0x69,0x7A,
- 0x23,2,0x6A,0x7A,
- 0x23,2,0x6B,0x0C,
- 0x23,2,0x6C,0x00,
- 0x23,2,0x6D,0x04,
- 0x23,2,0x6E,0x04,
- 0x23,2,0x6F,0x88,
- 0x23,2,0x70,0x00,
- 0x23,2,0x71,0x00,
- 0x23,2,0x72,0x06,
- 0x23,2,0x73,0x7B,
- 0x23,2,0x74,0x00,
- 0x23,2,0x75,0xBC,
- 0x23,2,0x76,0x00,
- 0x23,2,0x77,0x04,
- 0x23,2,0x78,0x2C,
- 0x23,2,0x79,0x00,
- 0x23,2,0x7A,0x00,
- 0x23,2,0x7B,0x00,
- 0x23,2,0x7C,0x00,
- 0x23,2,0x7D,0x03,
- 0x23,2,0x7E,0x7B,
- 0x23,2,0xE0,0x04,//Page4
- 0x23,2,0x09,0x11,//Set RGBCYC2
- 0x23,2,0x0E,0x48,
- 0x23,2,0x2B,0x2B,//ESD Protect
- 0x23,2,0x2E,0x44,
- 0x23,2,0xE0,0x00,//Page0
- 0x23,2,0xE6,0x02,//Watch dog
- 0x23,2,0xE7,0x0C,
- 0x05,1,0x11,//sleep out
- 0xfd, 1,120,
- 0x05,1,0x29,//display on
- 0x05,1,0x35,
- 0xfd, 1, 20, /* delay(ms) */
- 0xFF, 0, /* ending flag */
-};
-
-static unsigned char ext_init_off_table_P070ACB_FT[LCD_EXTERN_INIT_OFF_MAX] = {
- 0x05, 1, 0x28, /* display off */
- 0xfd, 1, 10, /* delay 10ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xfd, 1, 150, /* delay 150ms */
- 0xFF, 0, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_TL050FHV02CT[LCD_EXTERN_INIT_ON_MAX] = {
- //LCD driver initialization
- 0x23, 2, 0XFF, 0X05,
- 0x23, 2, 0XFB, 0X01,
- 0x23, 2, 0XC5, 0X01, //TURN ON
- 0xfd, 1, 100,
-
- //AUO4.97+NT35596_intial
- 0x23, 2, 0XFF, 0XEE, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X1F, 0X45,
- 0x23, 2, 0X24, 0X4F,
- 0x23, 2, 0X38, 0XC8,
- 0x23, 2, 0X39, 0X2C,
- 0x23, 2, 0X1E, 0XBB,
- 0x23, 2, 0X1D, 0X0F,
- 0x23, 2, 0X7E, 0XB1,
-
- 0x23, 2, 0XFF, 0X00, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X35, 0X01,
-
- 0x23, 2, 0XFF, 0X01, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X00, 0X01,
- 0x23, 2, 0X01, 0X55,
- 0x23, 2, 0X02, 0X40,
- 0x23, 2, 0X05, 0X40,
- 0x23, 2, 0X06, 0X4A,
- 0x23, 2, 0X07, 0X24,
- 0x23, 2, 0X08, 0X0C,
- 0x23, 2, 0X0B, 0X87,
- 0x23, 2, 0X0C, 0X87,
- 0x23, 2, 0X0E, 0XB0,
- 0x23, 2, 0X0F, 0XB3,
- 0x23, 2, 0X11, 0X10,
- 0x23, 2, 0X12, 0X10,
- 0x23, 2, 0X13, 0X05,
- 0x23, 2, 0X14, 0X4A,
- 0x23, 2, 0X15, 0X18,
- 0x23, 2, 0X16, 0X18,
- 0x23, 2, 0X18, 0X00,
- 0x23, 2, 0X19, 0X77,
- 0x23, 2, 0X1A, 0X55,
- 0x23, 2, 0X1B, 0X13,
- 0x23, 2, 0X1C, 0X00,
- 0x23, 2, 0X1D, 0X00,
- 0x23, 2, 0X1E, 0X13,
- 0x23, 2, 0X1F, 0X00,
- 0x23, 2, 0X23, 0X00,
- 0x23, 2, 0X24, 0X00,
- 0x23, 2, 0X25, 0X00,
- 0x23, 2, 0X26, 0X00,
- 0x23, 2, 0X27, 0X00,
- 0x23, 2, 0X28, 0X00,
- 0x23, 2, 0X35, 0X00,
- 0x23, 2, 0X66, 0X00,
- 0x23, 2, 0X58, 0X82,
- 0x23, 2, 0X59, 0X02,
- 0x23, 2, 0X5A, 0X02,
- 0x23, 2, 0X5B, 0X02,
- 0x23, 2, 0X5C, 0X82,
- 0x23, 2, 0X5D, 0X82,
- 0x23, 2, 0X5E, 0X02,
- 0x23, 2, 0X5F, 0X02,
- 0x23, 2, 0X72, 0X31,
-
- 0x23, 2, 0XFF, 0X05, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X00, 0X01,
- 0x23, 2, 0X01, 0X0B,
- 0x23, 2, 0X02, 0X0C,
- 0x23, 2, 0X03, 0X09,
- 0x23, 2, 0X04, 0X0A,
- 0x23, 2, 0X05, 0X00,
- 0x23, 2, 0X06, 0X0F,
- 0x23, 2, 0X07, 0X10,
- 0x23, 2, 0X08, 0X00,
- 0x23, 2, 0X09, 0X00,
- 0x23, 2, 0X0A, 0X00,
- 0x23, 2, 0X0B, 0X00,
- 0x23, 2, 0X0C, 0X00,
- 0x23, 2, 0X0D, 0X13,
- 0x23, 2, 0X0E, 0X15,
- 0x23, 2, 0X0F, 0X17,
- 0x23, 2, 0X10, 0X01,
- 0x23, 2, 0X11, 0X0B,
- 0x23, 2, 0X12, 0X0C,
- 0x23, 2, 0X13, 0X09,
- 0x23, 2, 0X14, 0X0A,
- 0x23, 2, 0X15, 0X00,
- 0x23, 2, 0X16, 0X0F,
- 0x23, 2, 0X17, 0X10,
- 0x23, 2, 0X18, 0X00,
- 0x23, 2, 0X19, 0X00,
- 0x23, 2, 0X1A, 0X00,
- 0x23, 2, 0X1B, 0X00,
- 0x23, 2, 0X1C, 0X00,
- 0x23, 2, 0X1D, 0X13,
- 0x23, 2, 0X1E, 0X15,
- 0x23, 2, 0X1F, 0X17,
- 0x23, 2, 0X20, 0X00,
- 0x23, 2, 0X21, 0X03,
- 0x23, 2, 0X22, 0X01,
- 0x23, 2, 0X23, 0X40,
- 0x23, 2, 0X24, 0X40,
- 0x23, 2, 0X25, 0XED,
- 0x23, 2, 0X29, 0X58,
- 0x23, 2, 0X2A, 0X12,
- 0x23, 2, 0X2B, 0X01,
- 0x23, 2, 0X4B, 0X06,
- 0x23, 2, 0X4C, 0X11,
- 0x23, 2, 0X4D, 0X20,
- 0x23, 2, 0X4E, 0X02,
- 0x23, 2, 0X4F, 0X02,
- 0x23, 2, 0X50, 0X20,
- 0x23, 2, 0X51, 0X61,
- 0x23, 2, 0X52, 0X01,
- 0x23, 2, 0X53, 0X63,
- 0x23, 2, 0X54, 0X77,
- 0x23, 2, 0X55, 0XED,
- 0x23, 2, 0X5B, 0X00,
- 0x23, 2, 0X5C, 0X00,
- 0x23, 2, 0X5D, 0X00,
- 0x23, 2, 0X5E, 0X00,
- 0x23, 2, 0X5F, 0X15,
- 0x23, 2, 0X60, 0X75,
- 0x23, 2, 0X61, 0X00,
- 0x23, 2, 0X62, 0X00,
- 0x23, 2, 0X63, 0X00,
- 0x23, 2, 0X64, 0X00,
- 0x23, 2, 0X65, 0X00,
- 0x23, 2, 0X66, 0X00,
- 0x23, 2, 0X67, 0X00,
- 0x23, 2, 0X68, 0X04,
- 0x23, 2, 0X69, 0X00,
- 0x23, 2, 0X6A, 0X00,
- 0x23, 2, 0X6C, 0X40,
- 0x23, 2, 0X75, 0X01,
- 0x23, 2, 0X76, 0X01,
- 0x23, 2, 0X7A, 0X80,
- 0x23, 2, 0X7B, 0XC5,
- 0x23, 2, 0X7C, 0XD8,
- 0x23, 2, 0X7D, 0X60,
- 0x23, 2, 0X7F, 0X15,
- 0x23, 2, 0X80, 0X81,
- 0x23, 2, 0X83, 0X05,
- 0x23, 2, 0X93, 0X08,
- 0x23, 2, 0X94, 0X10,
- 0x23, 2, 0X8A, 0X00,
- 0x23, 2, 0X9B, 0X0F,
- 0x23, 2, 0XEA, 0XFF,
- 0x23, 2, 0XEC, 0X00,
-
- 0x23, 2, 0XFF, 0X01, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X75, 0X00, //Gamma R+
- 0x23, 2, 0X76, 0X18,
- 0x23, 2, 0X77, 0X00,
- 0x23, 2, 0X78, 0X38,
- 0x23, 2, 0X79, 0X00,
- 0x23, 2, 0X7A, 0X65,
- 0x23, 2, 0X7B, 0X00,
- 0x23, 2, 0X7C, 0X84,
- 0x23, 2, 0X7D, 0X00,
- 0x23, 2, 0X7E, 0X9B,
- 0x23, 2, 0X7F, 0X00,
- 0x23, 2, 0X80, 0XAF,
- 0x23, 2, 0X81, 0X00,
- 0x23, 2, 0X82, 0XC1,
- 0x23, 2, 0X83, 0X00,
- 0x23, 2, 0X84, 0XD2,
- 0x23, 2, 0X85, 0X00,
- 0x23, 2, 0X86, 0XDF,
- 0x23, 2, 0X87, 0X01,
- 0x23, 2, 0X88, 0X11,
- 0x23, 2, 0X89, 0X01,
- 0x23, 2, 0X8A, 0X38,
- 0x23, 2, 0X8B, 0X01,
- 0x23, 2, 0X8C, 0X76,
- 0x23, 2, 0X8D, 0X01,
- 0x23, 2, 0X8E, 0XA7,
- 0x23, 2, 0X8F, 0X01,
- 0x23, 2, 0X90, 0XF3,
- 0x23, 2, 0X91, 0X02,
- 0x23, 2, 0X92, 0X2F,
- 0x23, 2, 0X93, 0X02,
- 0x23, 2, 0X94, 0X30,
- 0x23, 2, 0X95, 0X02,
- 0x23, 2, 0X96, 0X66,
- 0x23, 2, 0X97, 0X02,
- 0x23, 2, 0X98, 0XA0,
- 0x23, 2, 0X99, 0X02,
- 0x23, 2, 0X9A, 0XC5,
- 0x23, 2, 0X9B, 0X02,
- 0x23, 2, 0X9C, 0XF8,
- 0x23, 2, 0X9D, 0X03,
- 0x23, 2, 0X9E, 0X1B,
- 0x23, 2, 0X9F, 0X03,
- 0x23, 2, 0XA0, 0X46,
- 0x23, 2, 0XA2, 0X03,
- 0x23, 2, 0XA3, 0X52,
- 0x23, 2, 0XA4, 0X03,
- 0x23, 2, 0XA5, 0X62,
- 0x23, 2, 0XA6, 0X03,
- 0x23, 2, 0XA7, 0X71,
- 0x23, 2, 0XA9, 0X03,
- 0x23, 2, 0XAA, 0X83,
- 0x23, 2, 0XAB, 0X03,
- 0x23, 2, 0XAC, 0X94,
- 0x23, 2, 0XAD, 0X03,
- 0x23, 2, 0XAE, 0XA3,
- 0x23, 2, 0XAF, 0X03,
- 0x23, 2, 0XB0, 0XAD,
- 0x23, 2, 0XB1, 0X03,
- 0x23, 2, 0XB2, 0XCC,
-
- 0x23, 2, 0XB3, 0X00, //Gamma R-
- 0x23, 2, 0XB4, 0X18,
- 0x23, 2, 0XB5, 0X00,
- 0x23, 2, 0XB6, 0X38,
- 0x23, 2, 0XB7, 0X00,
- 0x23, 2, 0XB8, 0X65,
- 0x23, 2, 0XB9, 0X00,
- 0x23, 2, 0XBA, 0X84,
- 0x23, 2, 0XBB, 0X00,
- 0x23, 2, 0XBC, 0X9B,
- 0x23, 2, 0XBD, 0X00,
- 0x23, 2, 0XBE, 0XAF,
- 0x23, 2, 0XBF, 0X00,
- 0x23, 2, 0XC0, 0XC1,
- 0x23, 2, 0XC1, 0X00,
- 0x23, 2, 0XC2, 0XD2,
- 0x23, 2, 0XC3, 0X00,
- 0x23, 2, 0XC4, 0XDF,
- 0x23, 2, 0XC5, 0X01,
- 0x23, 2, 0XC6, 0X11,
- 0x23, 2, 0XC7, 0X01,
- 0x23, 2, 0XC8, 0X38,
- 0x23, 2, 0XC9, 0X01,
- 0x23, 2, 0XCA, 0X76,
- 0x23, 2, 0XCB, 0X01,
- 0x23, 2, 0XCC, 0XA7,
- 0x23, 2, 0XCD, 0X01,
- 0x23, 2, 0XCE, 0XF3,
- 0x23, 2, 0XCF, 0X02,
- 0x23, 2, 0XD0, 0X2F,
- 0x23, 2, 0XD1, 0X02,
- 0x23, 2, 0XD2, 0X30,
- 0x23, 2, 0XD3, 0X02,
- 0x23, 2, 0XD4, 0X66,
- 0x23, 2, 0XD5, 0X02,
- 0x23, 2, 0XD6, 0XA0,
- 0x23, 2, 0XD7, 0X02,
- 0x23, 2, 0XD8, 0XC5,
- 0x23, 2, 0XD9, 0X02,
- 0x23, 2, 0XDA, 0XF8,
- 0x23, 2, 0XDB, 0X03,
- 0x23, 2, 0XDC, 0X1B,
- 0x23, 2, 0XDD, 0X03,
- 0x23, 2, 0XDE, 0X46,
- 0x23, 2, 0XDF, 0X03,
- 0x23, 2, 0XE0, 0X52,
- 0x23, 2, 0XE1, 0X03,
- 0x23, 2, 0XE2, 0X62,
- 0x23, 2, 0XE3, 0X03,
- 0x23, 2, 0XE4, 0X71,
- 0x23, 2, 0XE5, 0X03,
- 0x23, 2, 0XE6, 0X83,
- 0x23, 2, 0XE7, 0X03,
- 0x23, 2, 0XE8, 0X94,
- 0x23, 2, 0XE9, 0X03,
- 0x23, 2, 0XEA, 0XA3,
- 0x23, 2, 0XEB, 0X03,
- 0x23, 2, 0XEC, 0XAD,
- 0x23, 2, 0XED, 0X03,
- 0x23, 2, 0XEE, 0XCC,
-
- 0x23, 2, 0XEF, 0X00, //Gamma G+
- 0x23, 2, 0XF0, 0X18,
- 0x23, 2, 0XF1, 0X00,
- 0x23, 2, 0XF2, 0X38,
- 0x23, 2, 0XF3, 0X00,
- 0x23, 2, 0XF4, 0X65,
- 0x23, 2, 0XF5, 0X00,
- 0x23, 2, 0XF6, 0X84,
- 0x23, 2, 0XF7, 0X00,
- 0x23, 2, 0XF8, 0X9B,
- 0x23, 2, 0XF9, 0X00,
- 0x23, 2, 0XFA, 0XAF,
- 0x23, 2, 0XFF, 0X02, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X00, 0X00,
- 0x23, 2, 0X01, 0XC1,
- 0x23, 2, 0X02, 0X00,
- 0x23, 2, 0X03, 0XD2,
- 0x23, 2, 0X04, 0X00,
- 0x23, 2, 0X05, 0XDF,
- 0x23, 2, 0X06, 0X01,
- 0x23, 2, 0X07, 0X11,
- 0x23, 2, 0X08, 0X01,
- 0x23, 2, 0X09, 0X38,
- 0x23, 2, 0X0A, 0X01,
- 0x23, 2, 0X0B, 0X76,
- 0x23, 2, 0X0C, 0X01,
- 0x23, 2, 0X0D, 0XA7,
- 0x23, 2, 0X0E, 0X01,
- 0x23, 2, 0X0F, 0XF3,
- 0x23, 2, 0X10, 0X02,
- 0x23, 2, 0X11, 0X2F,
- 0x23, 2, 0X12, 0X02,
- 0x23, 2, 0X13, 0X30,
- 0x23, 2, 0X14, 0X02,
- 0x23, 2, 0X15, 0X66,
- 0x23, 2, 0X16, 0X02,
- 0x23, 2, 0X17, 0XA0,
- 0x23, 2, 0X18, 0X02,
- 0x23, 2, 0X19, 0XC5,
- 0x23, 2, 0X1A, 0X02,
- 0x23, 2, 0X1B, 0XF8,
- 0x23, 2, 0X1C, 0X03,
- 0x23, 2, 0X1D, 0X1B,
- 0x23, 2, 0X1E, 0X03,
- 0x23, 2, 0X1F, 0X46,
- 0x23, 2, 0X20, 0X03,
- 0x23, 2, 0X21, 0X52,
- 0x23, 2, 0X22, 0X03,
- 0x23, 2, 0X23, 0X62,
- 0x23, 2, 0X24, 0X03,
- 0x23, 2, 0X25, 0X71,
- 0x23, 2, 0X26, 0X03,
- 0x23, 2, 0X27, 0X83,
- 0x23, 2, 0X28, 0X03,
- 0x23, 2, 0X29, 0X94,
- 0x23, 2, 0X2A, 0X03,
- 0x23, 2, 0X2B, 0XA3,
- 0x23, 2, 0X2D, 0X03,
- 0x23, 2, 0X2F, 0XAD,
- 0x23, 2, 0X30, 0X03,
- 0x23, 2, 0X31, 0XCC,
-
- 0x23, 2, 0X32, 0X00, //Gamma G-
- 0x23, 2, 0X33, 0X18,
- 0x23, 2, 0X34, 0X00,
- 0x23, 2, 0X35, 0X38,
- 0x23, 2, 0X36, 0X00,
- 0x23, 2, 0X37, 0X65,
- 0x23, 2, 0X38, 0X00,
- 0x23, 2, 0X39, 0X84,
- 0x23, 2, 0X3A, 0X00,
- 0x23, 2, 0X3B, 0X9B,
- 0x23, 2, 0X3D, 0X00,
- 0x23, 2, 0X3F, 0XAF,
- 0x23, 2, 0X40, 0X00,
- 0x23, 2, 0X41, 0XC1,
- 0x23, 2, 0X42, 0X00,
- 0x23, 2, 0X43, 0XD2,
- 0x23, 2, 0X44, 0X00,
- 0x23, 2, 0X45, 0XDF,
- 0x23, 2, 0X46, 0X01,
- 0x23, 2, 0X47, 0X11,
- 0x23, 2, 0X48, 0X01,
- 0x23, 2, 0X49, 0X38,
- 0x23, 2, 0X4A, 0X01,
- 0x23, 2, 0X4B, 0X76,
- 0x23, 2, 0X4C, 0X01,
- 0x23, 2, 0X4D, 0XA7,
- 0x23, 2, 0X4E, 0X01,
- 0x23, 2, 0X4F, 0XF3,
- 0x23, 2, 0X50, 0X02,
- 0x23, 2, 0X51, 0X2F,
- 0x23, 2, 0X52, 0X02,
- 0x23, 2, 0X53, 0X30,
- 0x23, 2, 0X54, 0X02,
- 0x23, 2, 0X55, 0X66,
- 0x23, 2, 0X56, 0X02,
- 0x23, 2, 0X58, 0XA0,
- 0x23, 2, 0X59, 0X02,
- 0x23, 2, 0X5A, 0XC5,
- 0x23, 2, 0X5B, 0X02,
- 0x23, 2, 0X5C, 0XF8,
- 0x23, 2, 0X5D, 0X03,
- 0x23, 2, 0X5E, 0X1B,
- 0x23, 2, 0X5F, 0X03,
- 0x23, 2, 0X60, 0X46,
- 0x23, 2, 0X61, 0X03,
- 0x23, 2, 0X62, 0X52,
- 0x23, 2, 0X63, 0X03,
- 0x23, 2, 0X64, 0X62,
- 0x23, 2, 0X65, 0X03,
- 0x23, 2, 0X66, 0X71,
- 0x23, 2, 0X67, 0X03,
- 0x23, 2, 0X68, 0X83,
- 0x23, 2, 0X69, 0X03,
- 0x23, 2, 0X6A, 0X94,
- 0x23, 2, 0X6B, 0X03,
- 0x23, 2, 0X6C, 0XA3,
- 0x23, 2, 0X6D, 0X03,
- 0x23, 2, 0X6E, 0XAD,
- 0x23, 2, 0X6F, 0X03,
- 0x23, 2, 0X70, 0XCC,
-
- 0x23, 2, 0X71, 0X00, //Gamma B+
- 0x23, 2, 0X72, 0X18,
- 0x23, 2, 0X73, 0X00,
- 0x23, 2, 0X74, 0X38,
- 0x23, 2, 0X75, 0X00,
- 0x23, 2, 0X76, 0X65,
- 0x23, 2, 0X77, 0X00,
- 0x23, 2, 0X78, 0X84,
- 0x23, 2, 0X79, 0X00,
- 0x23, 2, 0X7A, 0X9B,
- 0x23, 2, 0X7B, 0X00,
- 0x23, 2, 0X7C, 0XAF,
- 0x23, 2, 0X7D, 0X00,
- 0x23, 2, 0X7E, 0XC1,
- 0x23, 2, 0X7F, 0X00,
- 0x23, 2, 0X80, 0XD2,
- 0x23, 2, 0X81, 0X00,
- 0x23, 2, 0X82, 0XDF,
- 0x23, 2, 0X83, 0X01,
- 0x23, 2, 0X84, 0X11,
- 0x23, 2, 0X85, 0X01,
- 0x23, 2, 0X86, 0X38,
- 0x23, 2, 0X87, 0X01,
- 0x23, 2, 0X88, 0X76,
- 0x23, 2, 0X89, 0X01,
- 0x23, 2, 0X8A, 0XA7,
- 0x23, 2, 0X8B, 0X01,
- 0x23, 2, 0X8C, 0XF3,
- 0x23, 2, 0X8D, 0X02,
- 0x23, 2, 0X8E, 0X2F,
- 0x23, 2, 0X8F, 0X02,
- 0x23, 2, 0X90, 0X30,
- 0x23, 2, 0X91, 0X02,
- 0x23, 2, 0X92, 0X66,
- 0x23, 2, 0X93, 0X02,
- 0x23, 2, 0X94, 0XA0,
- 0x23, 2, 0X95, 0X02,
- 0x23, 2, 0X96, 0XC5,
- 0x23, 2, 0X97, 0X02,
- 0x23, 2, 0X98, 0XF8,
- 0x23, 2, 0X99, 0X03,
- 0x23, 2, 0X9A, 0X1B,
- 0x23, 2, 0X9B, 0X03,
- 0x23, 2, 0X9C, 0X46,
- 0x23, 2, 0X9D, 0X03,
- 0x23, 2, 0X9E, 0X52,
- 0x23, 2, 0X9F, 0X03,
- 0x23, 2, 0XA0, 0X62,
- 0x23, 2, 0XA2, 0X03,
- 0x23, 2, 0XA3, 0X71,
- 0x23, 2, 0XA4, 0X03,
- 0x23, 2, 0XA5, 0X83,
- 0x23, 2, 0XA6, 0X03,
- 0x23, 2, 0XA7, 0X94,
- 0x23, 2, 0XA9, 0X03,
- 0x23, 2, 0XAA, 0XA3,
- 0x23, 2, 0XAB, 0X03,
- 0x23, 2, 0XAC, 0XAD,
- 0x23, 2, 0XAD, 0X03,
- 0x23, 2, 0XAE, 0XCC,
-
- 0x23, 2, 0XAF, 0X00, //Gamma B-
- 0x23, 2, 0XB0, 0X18,
- 0x23, 2, 0XB1, 0X00,
- 0x23, 2, 0XB2, 0X38,
- 0x23, 2, 0XB3, 0X00,
- 0x23, 2, 0XB4, 0X65,
- 0x23, 2, 0XB5, 0X00,
- 0x23, 2, 0XB6, 0X84,
- 0x23, 2, 0XB7, 0X00,
- 0x23, 2, 0XB8, 0X9B,
- 0x23, 2, 0XB9, 0X00,
- 0x23, 2, 0XBA, 0XAF,
- 0x23, 2, 0XBB, 0X00,
- 0x23, 2, 0XBC, 0XC1,
- 0x23, 2, 0XBD, 0X00,
- 0x23, 2, 0XBE, 0XD2,
- 0x23, 2, 0XBF, 0X00,
- 0x23, 2, 0XC0, 0XDF,
- 0x23, 2, 0XC1, 0X01,
- 0x23, 2, 0XC2, 0X11,
- 0x23, 2, 0XC3, 0X01,
- 0x23, 2, 0XC4, 0X38,
- 0x23, 2, 0XC5, 0X01,
- 0x23, 2, 0XC6, 0X76,
- 0x23, 2, 0XC7, 0X01,
- 0x23, 2, 0XC8, 0XA7,
- 0x23, 2, 0XC9, 0X01,
- 0x23, 2, 0XCA, 0XF3,
- 0x23, 2, 0XCB, 0X02,
- 0x23, 2, 0XCC, 0X2F,
- 0x23, 2, 0XCD, 0X02,
- 0x23, 2, 0XCE, 0X30,
- 0x23, 2, 0XCF, 0X02,
- 0x23, 2, 0XD0, 0X66,
- 0x23, 2, 0XD1, 0X02,
- 0x23, 2, 0XD2, 0XA0,
- 0x23, 2, 0XD3, 0X02,
- 0x23, 2, 0XD4, 0XC5,
- 0x23, 2, 0XD5, 0X02,
- 0x23, 2, 0XD6, 0XF8,
- 0x23, 2, 0XD7, 0X03,
- 0x23, 2, 0XD8, 0X1B,
- 0x23, 2, 0XD9, 0X03,
- 0x23, 2, 0XDA, 0X46,
- 0x23, 2, 0XDB, 0X03,
- 0x23, 2, 0XDC, 0X52,
- 0x23, 2, 0XDD, 0X03,
- 0x23, 2, 0XDE, 0X62,
- 0x23, 2, 0XDF, 0X03,
- 0x23, 2, 0XE0, 0X71,
- 0x23, 2, 0XE1, 0X03,
- 0x23, 2, 0XE2, 0X83,
- 0x23, 2, 0XE3, 0X03,
- 0x23, 2, 0XE4, 0X94,
- 0x23, 2, 0XE5, 0X03,
- 0x23, 2, 0XE6, 0XA3,
- 0x23, 2, 0XE7, 0X03,
- 0x23, 2, 0XE8, 0XAD,
- 0x23, 2, 0XE9, 0X03,
- 0x23, 2, 0XEA, 0XCC,
-
- 0x23, 2, 0XFF, 0X01, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0XFF, 0X02, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0XFF, 0X04, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0XFF, 0X00, //CMD page select
-
- 0x23, 2, 0XD3, 0X05,
- 0x23, 2, 0XD4, 0X04,
-
- 0x23, 2, 0X11, 0X00, //Sleep out
- 0xfd, 1, 100, //delay 100ms
- 0x23, 2, 0XFF, 0X00,
-
- 0x23, 2, 0X35, 0X00, //TE on
-
- 0x23, 2, 0X29, 0X00, //Display on
- 0xfd, 1, 100, //delay 100ms
- 0xff, 0, /* ending flag */
-};
-
-static unsigned char ext_init_off_table_TL050FHV02CT[LCD_EXTERN_INIT_OFF_MAX] = {
- 0x05, 1, 0x28, /* display off */
- 0xfd, 1, 10, /* delay 10ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xfd, 1, 150, /* delay 150ms */
- 0xFF, 0, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_TV101WXM[LCD_EXTERN_INIT_ON_MAX] = {
- 0xFF, 120,
- 0x29, 5, 0xFF, 0xAA, 0x55, 0x25, 0x01,
- 0x23, 2, 0xFC, 0x08,
- 0xFF, 1,
- 0x23, 2, 0xFC, 0x00,
- 0x29, 5, 0xFF, 0xAA, 0x55, 0x25, 0x00,
- 0xFF, 20,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x00,
- 0x29, 3, 0xB1, 0x68, 0x01,
- 0x29, 5, 0xB8, 0x01, 0x02, 0x02, 0x02,
- 0x23, 2, 0xB6, 0x11,
- 0x29, 3, 0xBB, 0x63, 0x63,
- 0x29, 3, 0xBC, 0x00, 0x00,
- 0x29, 6, 0xBD, 0x02, 0xBB, 0x11, 0x10, 0x00,
- 0x23, 2, 0xC8, 0x80,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x01,
- 0x29, 3, 0xB3, 0x28, 0x28,
- 0x29, 3, 0xB4, 0x14, 0x14,
- 0x29, 3, 0xB9, 0x44, 0x44,
- 0x29, 3, 0xBA, 0x24, 0x24,
- 0x29, 3, 0xBC, 0x70, 0x00,
- 0x29, 3, 0xBD, 0x70, 0x00,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x02,
- 0x23, 2, 0xEE, 0x03,
- 0x29, 17, 0xB0, 0x01, 0x04, 0x01, 0x08, 0x01, 0x11, 0x01, 0x19, 0x01, 0x21, 0x01, 0x30, 0x01, 0x3D, 0x01, 0x55,
- 0x29, 17, 0xB1, 0x01, 0x6B, 0x01, 0x94, 0x01, 0xB5, 0x01, 0xED, 0x02, 0x20, 0x02, 0x22, 0x02, 0x53, 0x02, 0x8F,
- 0x29, 17, 0xB2, 0x02, 0xB4, 0x02, 0xE5, 0x03, 0x03, 0x03, 0x30, 0x03, 0x51, 0x03, 0x76, 0x03, 0x96, 0x03, 0xB8,
- 0x29, 5, 0xB3, 0x03, 0xCF, 0x03, 0xD2,
- 0x29, 17, 0xB4, 0x00, 0x00, 0x00, 0x13, 0x00, 0x31, 0x00, 0x4B, 0x00, 0x61, 0x00, 0x87, 0x00, 0xA7, 0x00, 0xDB,
- 0x29, 17, 0xB5, 0x01, 0x04, 0x01, 0x43, 0x01, 0x76, 0x01, 0xC9, 0x02, 0x05, 0x02, 0x06, 0x02, 0x3F, 0x02, 0x7D,
- 0x29, 17, 0xB6, 0x02, 0xA3, 0x02, 0xD3, 0x02, 0xF6, 0x03, 0x23, 0x03, 0x44, 0x03, 0x6C, 0x03, 0x8A, 0x03, 0xAE,
- 0x29, 5, 0xB7, 0x03, 0xCF, 0x03, 0xD2,
- 0x29, 17, 0xB8, 0x00, 0x41, 0x00, 0x4A, 0x00, 0x5D, 0x00, 0x6D, 0x00, 0x7E, 0x00, 0x9A, 0x00, 0xB4, 0x00, 0xDF,
- 0x29, 17, 0xB9, 0x01, 0x04, 0x01, 0x43, 0x01, 0x74, 0x01, 0xC6, 0x02, 0x03, 0x02, 0x09, 0x02, 0x40, 0x02, 0x7E,
- 0x29, 17, 0xBA, 0x02, 0xA4, 0x02, 0xD6, 0x02, 0xF7, 0x03, 0x25, 0x03, 0x44, 0x03, 0x6C, 0x03, 0x88, 0x03, 0xA8,
- 0x29, 5, 0xBB, 0x03, 0xD0, 0x03, 0xD2,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x03,
- 0x29, 3, 0xB0, 0x00, 0x00,
- 0x29, 3, 0xB1, 0x00, 0x00,
- 0x29, 6, 0xB2, 0x05, 0x01, 0x55, 0x00, 0x1A,
- 0x29, 6, 0xB3, 0x05, 0x01, 0x55, 0x00, 0x1A,
- 0x29, 6, 0xBA, 0x53, 0x01, 0x55, 0x00, 0x3A,
- 0x23, 2, 0xC4, 0x60,
- 0x23, 2, 0xC5, 0x40,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x04,
- 0x29, 5, 0xB1, 0x03, 0x02, 0x05, 0x07,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x05,
- 0x29, 6, 0xBD, 0x01, 0x03, 0x00, 0x00, 0x03,
- 0x23, 2, 0xC0, 0x09,
- 0x23, 2, 0xC1, 0x07,
- 0x29, 3, 0xC8, 0x07, 0x38,
- 0x23, 2, 0xD0, 0x00,
- 0x23, 2, 0xE5, 0x03,
- 0x23, 2, 0xE6, 0x03,
- 0x23, 2, 0xE9, 0x03,
- 0x23, 2, 0xEA, 0x03,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x06,
- 0x29, 3, 0xB0, 0x2D, 0x2D,
- 0x29, 3, 0xB1, 0x01, 0x01,
- 0x29, 3, 0xB2, 0x03, 0x03,
- 0x29, 3, 0xB3, 0x2E, 0x2E,
- 0x29, 3, 0xB4, 0x2E, 0x2D,
- 0x29, 3, 0xB5, 0x2D, 0x13,
- 0x29, 3, 0xB6, 0x13, 0x11,
- 0x29, 3, 0xB7, 0x11, 0x36,
- 0x29, 3, 0xB8, 0x36, 0x15,
- 0x29, 3, 0xB9, 0x15, 0x2E,
- 0x29, 3, 0xBA, 0x2E, 0x14,
- 0x29, 3, 0xBB, 0x14, 0x35,
- 0x29, 3, 0xBC, 0x35, 0x10,
- 0x29, 3, 0xBD, 0x10, 0x12,
- 0x29, 3, 0xBE, 0x12, 0x2D,
- 0x29, 3, 0xBF, 0x2D, 0x2E,
- 0x29, 3, 0xC0, 0x2E, 0x2E,
- 0x29, 3, 0xC1, 0x02, 0x02,
- 0x29, 3, 0xC2, 0x00, 0x00,
- 0x29, 3, 0xC3, 0x2D, 0x2D,
- 0x29, 3, 0xE5, 0x34, 0x34,
- 0x29, 3, 0xC4, 0x2E, 0x2E,
- 0x29, 3, 0xC5, 0x02, 0x02,
- 0x29, 3, 0xC6, 0x00, 0x00,
- 0x29, 3, 0xC7, 0x2D, 0x2D,
- 0x29, 3, 0xC8, 0x2E, 0x2D,
- 0x29, 3, 0xC9, 0x2D, 0x14,
- 0x29, 3, 0xCA, 0x14, 0x35,
- 0x29, 3, 0xCB, 0x35, 0x10,
- 0x29, 3, 0xCC, 0x10, 0x12,
- 0x29, 3, 0xCD, 0x12, 0x2E,
- 0x29, 3, 0xCE, 0x2E, 0x13,
- 0x29, 3, 0xCF, 0x13, 0x11,
- 0x29, 3, 0xD0, 0x11, 0x36,
- 0x29, 3, 0xD1, 0x36, 0x15,
- 0x29, 3, 0xD2, 0x15, 0x2D,
- 0x29, 3, 0xD3, 0x2D, 0x2E,
- 0x29, 3, 0xD4, 0x2D, 0x2D,
- 0x29, 3, 0xD5, 0x01, 0x01,
- 0x29, 3, 0xD6, 0x03, 0x03,
- 0x29, 3, 0xD7, 0x2E, 0x2E,
- 0x29, 3, 0xE6, 0x34, 0x34,
- 0x29, 6, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x29, 6, 0xD9, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x00, 0x00,
- 0x23, 2, 0x35, 0x00,
- 0x13, 1, 0x11,
- 0xFF, 120,
- 0x13, 1, 0x29,
-
- 0xFF, 0xFF,
-};
-
-static unsigned char ext_init_off_table_TV101WXM[] = {
- 0x05, 1, 0x28, /* display off */
- 0xFF, 10, /* delay 10ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xFF, 150, /* delay 150ms */
- 0xFF, 0xFF, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_G101B158[LCD_EXTERN_INIT_ON_MAX] = {
- 0xff, 120, /* delay */
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x00,
- 0x29, 3, 0xB1,0x68,0x01,
- 0x15, 2, 0xB5,0xC8,
- 0x29, 6, 0xBD,0x02,0xB0,0x10,0x10,0x00,
-
- 0x15, 2, 0xBC,0x05,
- 0x15, 2, 0xC7,0x00,
- 0x15, 2, 0xC8,0x80,
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x01,
- 0x29, 3, 0xB3,0x2D,0x2D,
- 0x29, 3, 0xB4,0x19,0x19,
- 0x15, 2, 0xB5,0x06,
- 0x29, 3, 0xB9,0x35,0x35,
- 0x29, 3, 0xBA,0x25,0x25,
- 0x29, 3, 0xBC,0x90,0x00,
- 0x29, 3, 0xBD,0x90,0x00,
-
- 0x15, 2, 0xC0,0x0C,
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x02,
- 0x15, 2, 0xEE,0x02,
-
- 0x29, 7, 0xB0,0x00,0x00,0x00,0x32,0x00,0x64,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xB0,0x00,0x83,0x00,0x9C,0x00,0xC3,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xB0,0x00,0xDF,0x01,0x0E,
-
- 0x29, 7, 0xB1,0x01,0x33,0x01,0x6C,0x01,0x99,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xB1,0x01,0xDF,0x02,0x18,0x02,0x1A,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xB1,0x02,0x4E,0x02,0x87,
-
- 0x29, 7, 0xB2,0x02,0xAC,0x02,0xDB,0x02,0xFC,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xB2,0x03,0x24,0x03,0x46,0x03,0x71,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xB2,0x03,0x8C,0x03,0xB1,
-
- 0x29, 5, 0xB3,0x03,0xED,0x03,0Xff,
-
- 0x29, 7, 0xBC,0x00,0x00,0x00,0x32,0x00,0x64,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xBC,0x00,0x83,0x00,0x9C,0x00,0xC3,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xBC,0x00,0xDF,0x01,0x0E,
-
- 0x29, 7, 0xBD,0x01,0x33,0x01,0x6C,0x01,0x99,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xBD,0x01,0xDF,0x02,0x18,0x02,0x1A,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xBD,0x02,0x4E,0x02,0x87,
-
- 0x29, 7, 0xBE,0x02,0xAC,0x02,0xDB,0x02,0xFC,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xBE,0x03,0x24,0x03,0x46,0x03,0x71,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xBE,0x03,0x8C,0x03,0xB1,
-
- 0x29, 5, 0xBF,0x03,0xED,0x03,0xFF,
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x03,
- 0x29, 6, 0xB2,0x05,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xB6,0x05,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xB7,0x05,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xBA,0x57,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xBB,0x57,0x00,0x00,0x00,0x00,
- 0x29, 5, 0xC0,0x00,0x34,0x00,0x00,
- 0x29, 5, 0xC1,0x00,0x00,0x34,0x00,
- 0x15, 2, 0xC4,0x40,
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x04,
- 0x29, 4, 0xB1,0x03,0x02,0x05,
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x05,
- 0x29, 3, 0xB0,0x17,0x06,
- 0x29, 3, 0xB1,0x17,0x06,
- 0x29, 3, 0xB2,0x17,0x06,
- 0x29, 3, 0xB3,0x17,0x06,
- 0x29, 3, 0xB4,0x17,0x06,
- 0x15, 2, 0xBB,0x02,
- 0x29, 6, 0xBD,0x03,0x01,0x03,0x03,0x01,
- 0x15, 2, 0xC0,0x05,
-
- 0x15, 2, 0xC4,0x82,
- 0x15, 2, 0xC5,0xA2,
- 0x29, 3, 0xC8,0x03,0x30,
- 0x29, 3, 0xC9,0x03,0x31,
-
- 0x29, 4, 0xCC,0x00,0x00,0x3C,
- 0x29, 4, 0xCD,0x00,0x00,0x3C,
-
- 0x29, 6, 0xD1,0x00,0x05,0x07,0x00,0x00,
- 0x29, 6, 0xD2,0x00,0x25,0x09,0x00,0x00,
-
- 0x15, 2, 0xE5,0x06,
- 0x15, 2, 0xE6,0x06,
- 0x15, 2, 0xE7,0x06,
- 0x15, 2, 0xE8,0x06,
- 0x15, 2, 0xE9,0x06,
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x06,
- 0x29, 3, 0xB0,0x0A,0x2D,
- 0x29, 3, 0xB1,0x2D,0x08,
- 0x29, 3, 0xB2,0x2A,0x29,
- 0x29, 3, 0xB3,0x34,0x1A,
- 0x29, 3, 0xB4,0x18,0x16,
- 0x29, 3, 0xB5,0x14,0x12,
- 0x29, 3, 0xB6,0x10,0x00,
- 0x29, 3, 0xB7,0x34,0x34,
- 0x29, 3, 0xB8,0x32,0x34,
- 0x29, 3, 0xB9,0x34,0x34,
- 0x29, 3, 0xBA,0x34,0x34,
- 0x29, 3, 0xBB,0x34,0x34,
- 0x29, 3, 0xBC,0x34,0x34,
- 0x29, 3, 0xBD,0x01,0x11,
- 0x29, 3, 0xBE,0x13,0x15,
- 0x29, 3, 0xBF,0x17,0x19,
- 0x29, 3, 0xC0,0x1B,0x34,
- 0x29, 3, 0xC1,0x29,0x2A,
- 0x29, 3, 0xC2,0x09,0x2D,
- 0x29, 3, 0xC3,0x2D,0x0B,
- 0x29, 3, 0xC4,0x0B,0x2D,
- 0x29, 3, 0xC5,0x2D,0x01,
- 0x29, 3, 0xC6,0x2A,0x29,
- 0x29, 3, 0xC7,0x34,0x19,
- 0x29, 3, 0xC8,0x1B,0x11,
- 0x29, 3, 0xC9,0x13,0x15,
- 0x29, 3, 0xCA,0x17,0x09,
- 0x29, 3, 0xCB,0x34,0x34,
- 0x29, 3, 0xCC,0x34,0x34,
- 0x29, 3, 0xCD,0x34,0x34,
- 0x29, 3, 0xCE,0x34,0x34,
- 0x29, 3, 0xCF,0x34,0x34,
- 0x29, 3, 0xD0,0x34,0x34,
- 0x29, 3, 0xD1,0x08,0x16,
- 0x29, 3, 0xD2,0x14,0x12,
- 0x29, 3, 0xD3,0x10,0x1A,
- 0x29, 3, 0xD4,0x18,0x34,
- 0x29, 3, 0xD5,0x29,0x2A,
- 0x29, 3, 0xD6,0x00,0x2D,
- 0x29, 3, 0xD7,0x2D,0x0A,
-
- 0x29, 6, 0xD8,0x00,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xD9,0x00,0x00,0x00,0x00,0x00,
-
- 0x29, 3, 0xE5,0x34,0x34,
- 0x29, 3, 0xE6,0x34,0x34,
-
- 0x15, 2, 0xE7,0x00,
- 0x29, 3, 0xE8,0x34,0x34,
- 0x29, 3, 0xE9,0x34,0x34,
- 0x15, 2, 0xEA,0x00,
-
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x00,0x00,
-
- 0x23, 2, 0x35,0x00,
-
-#if 1
- 0x13, 1, 0x11,
- 0xff, 150,
- 0x13, 1, 0x29,
-#else //bist mode
- 0xff, 150,
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x00,
- 0xff, 10,
- 0x29, 5, 0xEE,0x87,0x78,0x02,0x40,
- 0xff, 10,
- 0x29, 6, 0xEF,0x00,0x07,0xFF,0xFF,0x00,
-#endif
- 0xff, 20,
- 0xFF, 0xFF, /* ending flag */
-
-};
-
-static unsigned char ext_init_off_table_G101B158[] = {
- 0x05, 1, 0x28, /* display off */
- 0xFF, 10, /* delay 10ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xFF, 150, /* delay 150ms */
- 0xFF, 0xFF, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_TV101WXM_FT[LCD_EXTERN_INIT_ON_MAX] = {
- 0xFF, 120,
- 0x23, 2, 0xE0, 0x00,
- 0x23, 2, 0xE1, 0x93,
- 0x23, 2, 0xE2, 0x65,
- 0x23, 2, 0xE3, 0xF8,
- 0x23, 2, 0x80, 0x03,
- 0x23, 2, 0xE0, 0x01,
- 0x23, 2, 0x00, 0x00,
- 0x23, 2, 0x01, 0x6F,
- 0x23, 2, 0x17, 0x00,
- 0x23, 2, 0x18, 0xAF,
- 0x23, 2, 0x19, 0x01,
- 0x23, 2, 0x1A, 0x00,
- 0x23, 2, 0x1B, 0xAF,
- 0x23, 2, 0x1C, 0x01,
- 0x23, 2, 0x1F, 0x3E,
- 0x23, 2, 0x20, 0x28,
- 0x23, 2, 0x21, 0x28,
- 0x23, 2, 0x22, 0x7E,
- 0x23, 2, 0x35, 0x26,
- 0x23, 2, 0x37, 0x09,
- 0x23, 2, 0x38, 0x04,
- 0x23, 2, 0x39, 0x00,
- 0x23, 2, 0x3A, 0x01,
- 0x23, 2, 0x3C, 0x78,
- 0x23, 2, 0x3D, 0xFF,
- 0x23, 2, 0x3E, 0xFF,
- 0x23, 2, 0x3F, 0x7F,
- 0x23, 2, 0x40, 0x06,
- 0x23, 2, 0x41, 0xA0,
- 0x23, 2, 0x42, 0x81,
- 0x23, 2, 0x43, 0x08,
- 0x23, 2, 0x44, 0x0B,
- 0x23, 2, 0x45, 0x28,
- 0x23, 2, 0x55, 0x0F,
- 0x23, 2, 0x57, 0x69,
- 0x23, 2, 0x59, 0x0A,
- 0x23, 2, 0x5A, 0x28,
- 0x23, 2, 0x5B, 0x14,
- 0x23, 2, 0x5D, 0x7F,
- 0x23, 2, 0x5E, 0x6A,
- 0x23, 2, 0x5F, 0x5A,
- 0x23, 2, 0x60, 0x4E,
- 0x23, 2, 0x61, 0x4A,
- 0x23, 2, 0x62, 0x3A,
- 0x23, 2, 0x63, 0x3C,
- 0x23, 2, 0x64, 0x23,
- 0x23, 2, 0x65, 0x39,
- 0x23, 2, 0x66, 0x35,
- 0x23, 2, 0x67, 0x34,
- 0x23, 2, 0x68, 0x51,
- 0x23, 2, 0x69, 0x3E,
- 0x23, 2, 0x6A, 0x44,
- 0x23, 2, 0x6B, 0x34,
- 0x23, 2, 0x6C, 0x2E,
- 0x23, 2, 0x6D, 0x21,
- 0x23, 2, 0x6E, 0x0E,
- 0x23, 2, 0x6F, 0x00,
- 0x23, 2, 0x70, 0x7F,
- 0x23, 2, 0x71, 0x6A,
- 0x23, 2, 0x72, 0x5A,
- 0x23, 2, 0x73, 0x4E,
- 0x23, 2, 0x74, 0x4A,
- 0x23, 2, 0x75, 0x3A,
- 0x23, 2, 0x76, 0x3C,
- 0x23, 2, 0x77, 0x23,
- 0x23, 2, 0x78, 0x39,
- 0x23, 2, 0x79, 0x35,
- 0x23, 2, 0x7A, 0x34,
- 0x23, 2, 0x7B, 0x51,
- 0x23, 2, 0x7C, 0x3E,
- 0x23, 2, 0x7D, 0x44,
- 0x23, 2, 0x7E, 0x34,
- 0x23, 2, 0x7F, 0x2E,
- 0x23, 2, 0x80, 0x21,
- 0x23, 2, 0x81, 0x0E,
- 0x23, 2, 0x82, 0x00,
- 0x23, 2, 0xE0, 0x02,
- 0x23, 2, 0x00, 0x1E,
- 0x23, 2, 0x01, 0x1E,
- 0x23, 2, 0x02, 0x41,
- 0x23, 2, 0x03, 0x41,
- 0x23, 2, 0x04, 0x43,
- 0x23, 2, 0x05, 0x43,
- 0x23, 2, 0x06, 0x1F,
- 0x23, 2, 0x07, 0x1F,
- 0x23, 2, 0x08, 0x35,
- 0x23, 2, 0x09, 0x1F,
- 0x23, 2, 0x0A, 0x15,
- 0x23, 2, 0x0B, 0x15,
- 0x23, 2, 0x0C, 0x1F,
- 0x23, 2, 0x0D, 0x47,
- 0x23, 2, 0x0E, 0x47,
- 0x23, 2, 0x0F, 0x45,
- 0x23, 2, 0x10, 0x45,
- 0x23, 2, 0x11, 0x4B,
- 0x23, 2, 0x12, 0x4B,
- 0x23, 2, 0x13, 0x49,
- 0x23, 2, 0x14, 0x49,
- 0x23, 2, 0x15, 0x1F,
- 0x23, 2, 0x16, 0x1E,
- 0x23, 2, 0x17, 0x1E,
- 0x23, 2, 0x18, 0x40,
- 0x23, 2, 0x19, 0x40,
- 0x23, 2, 0x1A, 0x42,
- 0x23, 2, 0x1B, 0x42,
- 0x23, 2, 0x1C, 0x1F,
- 0x23, 2, 0x1D, 0x1F,
- 0x23, 2, 0x1E, 0x35,
- 0x23, 2, 0x1F, 0x1F,
- 0x23, 2, 0x20, 0x15,
- 0x23, 2, 0x21, 0x15,
- 0x23, 2, 0x22, 0x1F,
- 0x23, 2, 0x23, 0x46,
- 0x23, 2, 0x24, 0x46,
- 0x23, 2, 0x25, 0x44,
- 0x23, 2, 0x26, 0x44,
- 0x23, 2, 0x27, 0x4A,
- 0x23, 2, 0x28, 0x4A,
- 0x23, 2, 0x29, 0x48,
- 0x23, 2, 0x2A, 0x48,
- 0x23, 2, 0x2B, 0x1F,
- 0x23, 2, 0x58, 0x40,
- 0x23, 2, 0x5B, 0x30,
- 0x23, 2, 0x5C, 0x0F,
- 0x23, 2, 0x5D, 0x30,
- 0x23, 2, 0x5E, 0x01,
- 0x23, 2, 0x5F, 0x02,
- 0x23, 2, 0x63, 0x14,
- 0x23, 2, 0x64, 0x6A,
- 0x23, 2, 0x67, 0x73,
- 0x23, 2, 0x68, 0x11,
- 0x23, 2, 0x69, 0x14,
- 0x23, 2, 0x6A, 0x6A,
- 0x23, 2, 0x6B, 0x08,
- 0x23, 2, 0x6C, 0x00,
- 0x23, 2, 0x6D, 0x00,
- 0x23, 2, 0x6E, 0x00,
- 0x23, 2, 0x6F, 0x88,
- 0x23, 2, 0x77, 0xDD,
- 0x23, 2, 0x79, 0x0E,
- 0x23, 2, 0x7A, 0x0F,
- 0x23, 2, 0x7D, 0x14,
- 0x23, 2, 0x7E, 0x82,
- 0x23, 2, 0xE0, 0x04,
- 0x23, 2, 0x09, 0x11,
- 0x23, 2, 0x0E, 0x48,
- 0x23, 2, 0x2B, 0x2B,
- 0x23, 2, 0x2D, 0x03,
- 0x23, 2, 0x2E, 0x44,
- 0x23, 2, 0xE0, 0x00,
- 0x23, 2, 0xE6, 0x02,
- 0x23, 2, 0xE7, 0x0C,
- 0x05, 1, 0x11,
- 0xFF, 100,
- 0x23, 2, 0xE0, 0x03,
- 0x23, 2, 0x2B, 0x01,
- 0x23, 2, 0x2C, 0x00,
- 0x23, 2, 0x30, 0x03,
- 0x23, 2, 0x31, 0xFC,
- 0x23, 2, 0x32, 0x03,
- 0x23, 2, 0x33, 0xF8,
- 0x23, 2, 0x34, 0x03,
- 0x23, 2, 0x35, 0xF0,
- 0x23, 2, 0x36, 0x03,
- 0x23, 2, 0x37, 0xE8,
- 0x23, 2, 0x38, 0x03,
- 0x23, 2, 0x39, 0xE0,
- 0x23, 2, 0x3A, 0x03,
- 0x23, 2, 0x3B, 0xD0,
- 0x23, 2, 0x3C, 0x03,
- 0x23, 2, 0x3D, 0xC0,
- 0x23, 2, 0x3E, 0x03,
- 0x23, 2, 0x3F, 0xA0,
- 0x23, 2, 0x40, 0x03,
- 0x23, 2, 0x41, 0x80,
- 0x23, 2, 0x42, 0x03,
- 0x23, 2, 0x43, 0x40,
- 0x23, 2, 0x44, 0x03,
- 0x23, 2, 0x45, 0x00,
- 0x23, 2, 0x46, 0x02,
- 0x23, 2, 0x47, 0x80,
- 0x23, 2, 0x48, 0x02,
- 0x23, 2, 0x49, 0x00,
- 0x23, 2, 0x4A, 0x01,
- 0x23, 2, 0x4B, 0xFC,
- 0x23, 2, 0x4C, 0x01,
- 0x23, 2, 0x4D, 0x7C,
- 0x23, 2, 0x4E, 0x00,
- 0x23, 2, 0x4F, 0xFC,
- 0x23, 2, 0x50, 0x00,
- 0x23, 2, 0x51, 0xBC,
- 0x23, 2, 0x52, 0x00,
- 0x23, 2, 0x53, 0x7C,
- 0x23, 2, 0x54, 0x00,
- 0x23, 2, 0x55, 0x5C,
- 0x23, 2, 0x56, 0x00,
- 0x23, 2, 0x57, 0x3C,
- 0x23, 2, 0x58, 0x00,
- 0x23, 2, 0x59, 0x2C,
- 0x23, 2, 0x5A, 0x00,
- 0x23, 2, 0x5B, 0x1C,
- 0x23, 2, 0x5C, 0x00,
- 0x23, 2, 0x5D, 0x14,
- 0x23, 2, 0x5E, 0x00,
- 0x23, 2, 0x5F, 0x0C,
- 0x23, 2, 0x60, 0x00,
- 0x23, 2, 0x61, 0x04,
- 0x23, 2, 0x62, 0x00,
- 0x23, 2, 0x63, 0x00,
- 0x23, 2, 0x64, 0x03,
- 0x23, 2, 0x65, 0xC9,
- 0x23, 2, 0x66, 0x03,
- 0x23, 2, 0x67, 0xC6,
- 0x23, 2, 0x68, 0x03,
- 0x23, 2, 0x69, 0xBE,
- 0x23, 2, 0x6A, 0x03,
- 0x23, 2, 0x6B, 0xB7,
- 0x23, 2, 0x6C, 0x03,
- 0x23, 2, 0x6D, 0xB1,
- 0x23, 2, 0x6E, 0x03,
- 0x23, 2, 0x6F, 0xA3,
- 0x23, 2, 0x70, 0x03,
- 0x23, 2, 0x71, 0x96,
- 0x23, 2, 0x72, 0x03,
- 0x23, 2, 0x73, 0x79,
- 0x23, 2, 0x74, 0x03,
- 0x23, 2, 0x75, 0x5D,
- 0x23, 2, 0x76, 0x03,
- 0x23, 2, 0x77, 0x26,
- 0x23, 2, 0x78, 0x02,
- 0x23, 2, 0x79, 0xE9,
- 0x23, 2, 0x7A, 0x02,
- 0x23, 2, 0x7B, 0x6E,
- 0x23, 2, 0x7C, 0x01,
- 0x23, 2, 0x7D, 0xF3,
- 0x23, 2, 0x7E, 0x01,
- 0x23, 2, 0x7F, 0xEF,
- 0x23, 2, 0x80, 0x01,
- 0x23, 2, 0x81, 0x73,
- 0x23, 2, 0x82, 0x00,
- 0x23, 2, 0x83, 0xF5,
- 0x23, 2, 0x84, 0x00,
- 0x23, 2, 0x85, 0xB4,
- 0x23, 2, 0x86, 0x00,
- 0x23, 2, 0x87, 0x79,
- 0x23, 2, 0x88, 0x00,
- 0x23, 2, 0x89, 0x5D,
- 0x23, 2, 0x8A, 0x00,
- 0x23, 2, 0x8B, 0x3C,
- 0x23, 2, 0x8C, 0x00,
- 0x23, 2, 0x8D, 0x2B,
- 0x23, 2, 0x8E, 0x00,
- 0x23, 2, 0x8F, 0x1C,
- 0x23, 2, 0x90, 0x00,
- 0x23, 2, 0x91, 0x14,
- 0x23, 2, 0x92, 0x00,
- 0x23, 2, 0x93, 0x0C,
- 0x23, 2, 0x94, 0x00,
- 0x23, 2, 0x95, 0x04,
- 0x23, 2, 0x96, 0x00,
- 0x23, 2, 0x97, 0x00,
- 0x23, 2, 0xE0, 0x00,
- 0x05, 1, 0x29,
- 0xFF, 0xFF,
-};
-static unsigned char ext_init_off_table_TV101WXM_FT[LCD_EXTERN_INIT_OFF_MAX] = {
- 0XFF, 5, /* delay 5ms */
- 0x05, 1, 0x28, /* display off */
- 0xFF, 50, /* delay 50ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xFF, 150, /* delay 150ms */
- 0xFF, 0xFF, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_G101B158_FT[LCD_EXTERN_INIT_ON_MAX] = {
- 0x23, 2, 0xE0, 0x00,
- 0x23, 2, 0xE1, 0x93,
- 0x23, 2, 0xE2, 0x65,
- 0x23, 2, 0xE3, 0xF8,
- 0x23, 2, 0x80, 0x03,
-
- 0x23, 2, 0xE0, 0x01,
- 0x23, 2, 0x00, 0x00,
- 0x23, 2, 0x01, 0x5D,
- 0x23, 2, 0x03, 0x00,
- 0x23, 2, 0x04, 0x64,
-
- 0x23, 2, 0x17, 0x00,
- 0x23, 2, 0x18, 0xC7,//BF=4.5V,c7=4.6v, D7=4.8V
- 0x23, 2, 0x19, 0x01,//0.3V
- 0x23, 2, 0x1A, 0x00,
- 0x23, 2, 0x1B, 0xC7,
- 0x23, 2, 0x1C, 0x01,
-
- 0x23, 2, 0x1F, 0x70, //VGH_REG=16.2V
- 0x23, 2, 0x20, 0x2D, //VGL_REG=-12V
- 0x23, 2, 0x21, 0x2D, //VGL_REG2=-12V
- 0x23, 2, 0x22, 0x7E,
-
- 0x23, 2, 0x35, 0x28, //SAP
-
- 0x23, 2, 0x37, 0x19, //SS=1,BGR=1
-
- 0x23, 2, 0x38, 0x05, //JDT=101 zigzag inversion
- 0x23, 2, 0x39, 0x00,
- 0x23, 2, 0x3A, 0x01,
- 0x23, 2, 0x3C, 0x7C, //SET EQ3 for TE_H
- 0x23, 2, 0x3D, 0xFF, //SET CHGEN_ON, modify 20140806
- 0x23, 2, 0x3E, 0xFF, //SET CHGEN_OFF, modify 20140806
- 0x23, 2, 0x3F, 0x7F, //SET CHGEN_OFF2, modify 20140806
-
-
- 0x23, 2, 0x40, 0x06, //RSO=
- 0x23, 2, 0x41, 0xA0, //LN=640->1280 line
- 0x23, 2, 0x43, 0x14, //VFP=20
- 0x23, 2, 0x44, 0x17, //VBP=24
- 0x23, 2, 0x45, 0x2C, //HBP=44
-
- 0x23, 2, 0x55, 0x0F, //DCDCM=1111
- 0x23, 2, 0x57, 0x68,
- 0x23, 2, 0x59, 0x0A, //VCL = -2.5V
- 0x23, 2, 0x5A, 0x2E, //VGH = 16.2V
- 0x23, 2, 0x5B, 0x1A, //VGL = -12V
- 0x23, 2, 0x5C, 0x15, //pump clk
-
-
- 0x23, 2, 0x5D, 0x7F,
- 0x23, 2, 0x5E, 0x61,
- 0x23, 2, 0x5F, 0x50,
- 0x23, 2, 0x60, 0x43,
- 0x23, 2, 0x61, 0x3E,
- 0x23, 2, 0x62, 0x2E,
- 0x23, 2, 0x63, 0x33,
- 0x23, 2, 0x64, 0x1C,
- 0x23, 2, 0x65, 0x34,
- 0x23, 2, 0x66, 0x33,
- 0x23, 2, 0x67, 0x32,
- 0x23, 2, 0x68, 0x50,
- 0x23, 2, 0x69, 0x3E,
- 0x23, 2, 0x6A, 0x46,
- 0x23, 2, 0x6B, 0x37,
- 0x23, 2, 0x6C, 0x32,
- 0x23, 2, 0x6D, 0x24,
- 0x23, 2, 0x6E, 0x12,
- 0x23, 2, 0x6F, 0x02,
- 0x23, 2, 0x70, 0x7F,
- 0x23, 2, 0x71, 0x61,
- 0x23, 2, 0x72, 0x50,
- 0x23, 2, 0x73, 0x43,
- 0x23, 2, 0x74, 0x3E,
- 0x23, 2, 0x75, 0x2E,
- 0x23, 2, 0x76, 0x33,
- 0x23, 2, 0x77, 0x1C,
- 0x23, 2, 0x78, 0x34,
- 0x23, 2, 0x79, 0x33,
- 0x23, 2, 0x7A, 0x32,
- 0x23, 2, 0x7B, 0x50,
- 0x23, 2, 0x7C, 0x3E,
- 0x23, 2, 0x7D, 0x46,
- 0x23, 2, 0x7E, 0x37,
- 0x23, 2, 0x7F, 0x32,
- 0x23, 2, 0x80, 0x24,
- 0x23, 2, 0x81, 0x12,
- 0x23, 2, 0x82, 0x02,
-
-
- 0x23, 2, 0xE0, 0x02,
-
- 0x23, 2, 0x00, 0x52,//RESET_EVEN
- 0x23, 2, 0x01, 0x55,//VSSG_EVEN
- 0x23, 2, 0x02, 0x55,//VSSG_EVEN
- 0x23, 2, 0x03, 0x50,//STV2_ODD
- 0x23, 2, 0x04, 0x77,//VDD2_ODD
- 0x23, 2, 0x05, 0x57,//VDD1_ODD
- 0x23, 2, 0x06, 0x55,//x
- 0x23, 2, 0x07, 0x4E,//CK11
- 0x23, 2, 0x08, 0x4C,//CK9
- 0x23, 2, 0x09, 0x5F,//x
- 0x23, 2, 0x0A, 0x4A,//CK7
- 0x23, 2, 0x0B, 0x48,//CK5
- 0x23, 2, 0x0C, 0x55,//x
- 0x23, 2, 0x0D, 0x46,//CK3
- 0x23, 2, 0x0E, 0x44,//CK1
- 0x23, 2, 0x0F, 0x40,//STV1_ODD
- 0x23, 2, 0x10, 0x55,//x
- 0x23, 2, 0x11, 0x55,//x
- 0x23, 2, 0x12, 0x55,//x
- 0x23, 2, 0x13, 0x55,//x
- 0x23, 2, 0x14, 0x55,//x
- 0x23, 2, 0x15, 0x55,//x
-
- 0x23, 2, 0x16, 0x53,//RESET__EVEN
- 0x23, 2, 0x17, 0x55,//VSSG_EVEN
- 0x23, 2, 0x18, 0x55,//VSSG_EVEN
- 0x23, 2, 0x19, 0x51,//STV2_EVEN
- 0x23, 2, 0x1A, 0x77,//VDD2_EVEN
- 0x23, 2, 0x1B, 0x57,//VDD1_EVEN
- 0x23, 2, 0x1C, 0x55,//x
- 0x23, 2, 0x1D, 0x4F,//CK12
- 0x23, 2, 0x1E, 0x4D,//CK10
- 0x23, 2, 0x1F, 0x5F,//x
- 0x23, 2, 0x20, 0x4B,//CK8
- 0x23, 2, 0x21, 0x49,//CK6
- 0x23, 2, 0x22, 0x55,//x
- 0x23, 2, 0x23, 0x47,//CK4
- 0x23, 2, 0x24, 0x45,//CK2
- 0x23, 2, 0x25, 0x41,//STV1_EVEN
- 0x23, 2, 0x26, 0x55,//x
- 0x23, 2, 0x27, 0x55,//x
- 0x23, 2, 0x28, 0x55,//x
- 0x23, 2, 0x29, 0x55,//x
- 0x23, 2, 0x2A, 0x55,//x
- 0x23, 2, 0x2B, 0x55,//x
-
- 0x23, 2, 0x2C, 0x13,//RESET_EVEN
- 0x23, 2, 0x2D, 0x15,//VSSG_EVEN
- 0x23, 2, 0x2E, 0x15,//VSSG_EVEN
- 0x23, 2, 0x2F, 0x01,//STV2_ODD
- 0x23, 2, 0x30, 0x37,//VDD2_ODD
- 0x23, 2, 0x31, 0x17,//VDD1_ODD
- 0x23, 2, 0x32, 0x15,//x
- 0x23, 2, 0x33, 0x0D,//CK11
- 0x23, 2, 0x34, 0x0F,//CK9
- 0x23, 2, 0x35, 0x15,//x
- 0x23, 2, 0x36, 0x05,//CK7
- 0x23, 2, 0x37, 0x07,//CK5
- 0x23, 2, 0x38, 0x15,//x
- 0x23, 2, 0x39, 0x09,//CK3
- 0x23, 2, 0x3A, 0x0B,//CK1
- 0x23, 2, 0x3B, 0x11,//STV1_ODD
- 0x23, 2, 0x3C, 0x15,//x
- 0x23, 2, 0x3D, 0x15,//x
- 0x23, 2, 0x3E, 0x15,//x
- 0x23, 2, 0x3F, 0x15,//x
- 0x23, 2, 0x40, 0x15,//x
- 0x23, 2, 0x41, 0x15,//x
-
- 0x23, 2, 0x42, 0x12,//RESET__EVEN
- 0x23, 2, 0x43, 0x15,//VSSG_EVEN
- 0x23, 2, 0x44, 0x15,//VSSG_EVEN
- 0x23, 2, 0x45, 0x00,//STV2_EVEN
- 0x23, 2, 0x46, 0x37,//VDD2_EVEN
- 0x23, 2, 0x47, 0x17,//VDD1_EVEN
- 0x23, 2, 0x48, 0x15,//x
- 0x23, 2, 0x49, 0x0C,//CK12
- 0x23, 2, 0x4A, 0x0E,//CK10
- 0x23, 2, 0x4B, 0x15,//x
- 0x23, 2, 0x4C, 0x04,//CK8
- 0x23, 2, 0x4D, 0x06,//CK6
- 0x23, 2, 0x4E, 0x15,//x
- 0x23, 2, 0x4F, 0x08,//CK4
- 0x23, 2, 0x50, 0x0A,//CK2
- 0x23, 2, 0x51, 0x10,//STV1_EVEN
- 0x23, 2, 0x52, 0x15,//x
- 0x23, 2, 0x53, 0x15,//x
- 0x23, 2, 0x54, 0x15,//x
- 0x23, 2, 0x55, 0x15,//x
- 0x23, 2, 0x56, 0x15,//x
- 0x23, 2, 0x57, 0x15,//x
-
- 0x23, 2, 0x58, 0x40,
- 0x23, 2, 0x5B, 0x10,
- 0x23, 2, 0x5C, 0x12,//STV_S0
- 0x23, 2, 0x5D, 0x40,
- 0x23, 2, 0x5E, 0x00,
- 0x23, 2, 0x5F, 0x00,
- 0x23, 2, 0x60, 0x40,//ETV_W
- 0x23, 2, 0x61, 0x03,
- 0x23, 2, 0x62, 0x04,
- 0x23, 2, 0x63, 0x6C,//CKV_ON
- 0x23, 2, 0x64, 0x6C,//CKV_OFF
- 0x23, 2, 0x65, 0x75,
- 0x23, 2, 0x66, 0x14,//ETV_S0
- 0x23, 2, 0x67, 0xB4, //ckv_num/ckv_w
- 0x23, 2, 0x68, 0x14, //CKV_S0
- 0x23, 2, 0x69, 0x6C,//CKV_ON
- 0x23, 2, 0x6A, 0x6C,//CKV_OFF
- 0x23, 2, 0x6B, 0x0C, //dummy
- 0x23, 2, 0x6D, 0x04,//GGND1
- 0x23, 2, 0x6E, 0x00,//GGND2
- 0x23, 2, 0x6F, 0x88,
- 0x23, 2, 0x75, 0xBB,//FLM_EN
- 0x23, 2, 0x76, 0x02,
- 0x23, 2, 0x77, 0x00,
- 0x23, 2, 0x78, 0x02,//FLM_OFF
-
- 0x23, 2, 0xE0, 0x03,
- 0x23, 2, 0xAF, 0x20,//Adjust CABC
-
-
- 0x23, 2, 0xE0, 0x04,
- 0x23, 2, 0x09, 0x11,
- 0x23, 2, 0x0E, 0x48, //Source EQ option
- 0x23, 2, 0x2B, 0x2B,
- 0x23, 2, 0x2D, 0x03,//defult 0x01
- 0x23, 2, 0x2E, 0x44,
- 0x23, 2, 0x41, 0xFF,//Adjust CABC
-
- 0x23, 2, 0xE0, 0x05,
- 0x23, 2, 0x12, 0x72,//VCI GAS detect voltage
-
- 0x23, 2, 0xE0, 0x00,
- 0x23, 2, 0xE6, 0x02,//WD_Timer
- 0x23, 2, 0xE7, 0x0C,//WD_Timer
-
- 0x23, 2, 0x53, 0x2C,//CABC dimming
-
- 0x05, 1, 0x11, // SLPOUT
- 0xff, 120,
-
- 0x23, 2, 0xE0, 0x03,
- 0x23, 2, 0x2B, 0x01,//DGC_EN
- 0xff, 10,
- 0x23, 2, 0x2C, 0x01,//DGC_SEL
-
- 0x23, 2, 0x30, 0x03,
- 0x23, 2, 0x31, 0xDE,
- 0x23, 2, 0x32, 0x03,
- 0x23, 2, 0x33, 0xDA,
- 0x23, 2, 0x34, 0x03,
- 0x23, 2, 0x35, 0xD1,
- 0x23, 2, 0x36, 0x03,
- 0x23, 2, 0x37, 0xC9,
- 0x23, 2, 0x38, 0x03,
- 0x23, 2, 0x39, 0xC1,
- 0x23, 2, 0x3A, 0x03,
- 0x23, 2, 0x3B, 0xB3,
- 0x23, 2, 0x3C, 0x03,
- 0x23, 2, 0x3D, 0xA4,
- 0x23, 2, 0x3E, 0x03,
- 0x23, 2, 0x3F, 0x83,
- 0x23, 2, 0x40, 0x03,
- 0x23, 2, 0x41, 0x62,
- 0x23, 2, 0x42, 0x03,
- 0x23, 2, 0x43, 0x23,
- 0x23, 2, 0x44, 0x02,
- 0x23, 2, 0x45, 0xE4,
- 0x23, 2, 0x46, 0x02,
- 0x23, 2, 0x47, 0x67,
- 0x23, 2, 0x48, 0x01,
- 0x23, 2, 0x49, 0xEC,
- 0x23, 2, 0x4A, 0x01,
- 0x23, 2, 0x4B, 0xE8,
- 0x23, 2, 0x4C, 0x01,
- 0x23, 2, 0x4D, 0x6D,
- 0x23, 2, 0x4E, 0x00,
- 0x23, 2, 0x4F, 0xF2,
- 0x23, 2, 0x50, 0x00,
- 0x23, 2, 0x51, 0xB2,
- 0x23, 2, 0x52, 0x00,
- 0x23, 2, 0x53, 0x76,
- 0x23, 2, 0x54, 0x00,
- 0x23, 2, 0x55, 0x58,
- 0x23, 2, 0x56, 0x00,
- 0x23, 2, 0x57, 0x39,
- 0x23, 2, 0x58, 0x00,
- 0x23, 2, 0x59, 0x2A,
- 0x23, 2, 0x5A, 0x00,
- 0x23, 2, 0x5B, 0x1B,
- 0x23, 2, 0x5C, 0x00,
- 0x23, 2, 0x5D, 0x13,
- 0x23, 2, 0x5E, 0x00,
- 0x23, 2, 0x5F, 0x0B,
- 0x23, 2, 0x60, 0x00,
- 0x23, 2, 0x61, 0x04,
- 0x23, 2, 0x62, 0x00,
- 0x23, 2, 0x63, 0x00,
-
- 0x23, 2, 0x64, 0x03,
- 0x23, 2, 0x65, 0xE7,
- 0x23, 2, 0x66, 0x03,
- 0x23, 2, 0x67, 0xE4,
- 0x23, 2, 0x68, 0x03,
- 0x23, 2, 0x69, 0xDD,
- 0x23, 2, 0x6A, 0x03,
- 0x23, 2, 0x6B, 0xD5,
- 0x23, 2, 0x6C, 0x03,
- 0x23, 2, 0x6D, 0xCE,
- 0x23, 2, 0x6E, 0x03,
- 0x23, 2, 0x6F, 0xBF,
- 0x23, 2, 0x70, 0x03,
- 0x23, 2, 0x71, 0xB2,
- 0x23, 2, 0x72, 0x03,
- 0x23, 2, 0x73, 0x93,
- 0x23, 2, 0x74, 0x03,
- 0x23, 2, 0x75, 0x71,
- 0x23, 2, 0x76, 0x03,
- 0x23, 2, 0x77, 0x33,
- 0x23, 2, 0x78, 0x02,
- 0x23, 2, 0x79, 0xF4,
- 0x23, 2, 0x7A, 0x02,
- 0x23, 2, 0x7B, 0x75,
- 0x23, 2, 0x7C, 0x01,
- 0x23, 2, 0x7D, 0xF7,
- 0x23, 2, 0x7E, 0x01,
- 0x23, 2, 0x7F, 0xF3,
- 0x23, 2, 0x80, 0x01,
- 0x23, 2, 0x81, 0x75,
- 0x23, 2, 0x82, 0x00,
- 0x23, 2, 0x83, 0xF7,
- 0x23, 2, 0x84, 0x00,
- 0x23, 2, 0x85, 0xB6,
- 0x23, 2, 0x86, 0x00,
- 0x23, 2, 0x87, 0x7C,
- 0x23, 2, 0x88, 0x00,
- 0x23, 2, 0x89, 0x5E,
- 0x23, 2, 0x8A, 0x00,
- 0x23, 2, 0x8B, 0x3F,
- 0x23, 2, 0x8C, 0x00,
- 0x23, 2, 0x8D, 0x2E,
- 0x23, 2, 0x8E, 0x00,
- 0x23, 2, 0x8F, 0x1D,
- 0x23, 2, 0x90, 0x00,
- 0x23, 2, 0x91, 0x15,
- 0x23, 2, 0x92, 0x00,
- 0x23, 2, 0x93, 0x0C,
- 0x23, 2, 0x94, 0x00,
- 0x23, 2, 0x95, 0x04,
- 0x23, 2, 0x96, 0x00,
- 0x23, 2, 0x97, 0x00,
-
- 0x23, 2, 0xE0, 0x00,
-
- 0x05, 1, 0x29, // DSPON
- 0xff, 5,
- 0xff, 0xff,
-};
-
-static unsigned char ext_init_off_table_G101B158_FT[LCD_EXTERN_INIT_OFF_MAX] = {
- 0XFF, 5, /* delay 5ms */
- 0x05, 1, 0x28, /* display off */
- 0xFF, 50, /* delay 50ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xFF, 150, /* delay 150ms */
- 0xFF, 0xFF, /* ending flag */
-};
-
-static struct lcd_extern_config_s ext_config[LCD_EXTERN_NUM_MAX] = {
- {
- .index = 0,
- .name = "ext_default",
- .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 0, /* 0=disable, 1=enable */
- .i2c_addr = 0x1c, /* 7bit i2c address */
- .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for invalid */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- { /* P070ACB_FT */
- .index = 1,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_P070ACB_FT,
- .table_init_on_cnt = sizeof(ext_init_on_table_P070ACB_FT),
- .table_init_off = ext_init_off_table_P070ACB_FT,
- .table_init_off_cnt = sizeof(ext_init_off_table_P070ACB_FT),
- },
- { /* TL050FHV02CT */
- .index = 2,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_TL050FHV02CT,
- .table_init_on_cnt = sizeof(ext_init_on_table_TL050FHV02CT),
- .table_init_off = ext_init_off_table_TL050FHV02CT,
- .table_init_off_cnt = sizeof(ext_init_off_table_TL050FHV02CT),
- },
- { /* boe_nvtk_10 */
- .index = 3,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_TV101WXM,
- .table_init_on_cnt = sizeof(ext_init_on_table_TV101WXM),
- .table_init_off = ext_init_off_table_TV101WXM,
- .table_init_off_cnt = sizeof(ext_init_off_table_TV101WXM),
- },
- { /* inx_nvtk_10 */
- .index = 4,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_G101B158,
- .table_init_on_cnt = sizeof(ext_init_on_table_G101B158),
- .table_init_off = ext_init_off_table_G101B158,
- .table_init_off_cnt = sizeof(ext_init_off_table_G101B158),
- },
- { /* boe_fiti_10 */
- .index = 5,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_TV101WXM_FT,
- .table_init_on_cnt = sizeof(ext_init_on_table_TV101WXM_FT),
- .table_init_off = ext_init_off_table_TV101WXM_FT,
- .table_init_off_cnt = sizeof(ext_init_off_table_TV101WXM_FT),
- },
- { /* inx_fiti_10 */
- .index = 6,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_G101B158_FT,
- .table_init_on_cnt = sizeof(ext_init_on_table_G101B158_FT),
- .table_init_off = ext_init_off_table_G101B158_FT,
- .table_init_off_cnt = sizeof(ext_init_off_table_G101B158_FT),
- },
- {
- .index = LCD_EXTERN_INDEX_INVALID,
- },
-};
-
-#endif
-
diff --git a/board/amlogic/g12b_newman_bx/zircon.c b/board/amlogic/g12b_newman_bx/zircon.c
deleted file mode 100644
index 9f17186..0000000
--- a/board/amlogic/g12b_newman_bx/zircon.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * Copyright (c) 2018 The Fuchsia Authors
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common.h>
-#include <fs.h>
-#include <version.h>
-#include <zircon/zircon.h>
-
-#define PDEV_VID_GOOGLE 3
-#define PDEV_PID_SHERLOCK 5
-
-#define NVRAM_LENGTH (8 * 1024)
-
-static const zbi_cpu_config_t cpu_config = {
- .cluster_count = 1,
- .clusters = {
- {
- .cpu_count = 4,
- },
- },
-};
-
-static const zbi_mem_range_t mem_config[] = {
- {
- .type = ZBI_MEM_RANGE_RAM,
- .length = 0x60000000, // 1.5 GB
- },
- {
- .type = ZBI_MEM_RANGE_PERIPHERAL,
- .paddr = 0xf5800000,
- .length = 0x0a800000,
- },
- /* secmon_reserved:linux,secmon */
- {
- .type = ZBI_MEM_RANGE_RESERVED,
- .paddr = 0x05000000,
- .length = 0x2400000,
- },
- /* logo_reserved:linux,meson-fb */
- {
- .type = ZBI_MEM_RANGE_RESERVED,
- .paddr = 0x5f800000,
- .length = 0x800000,
- },
-};
-
-static const dcfg_simple_t uart_driver = {
- .mmio_phys = 0xff803000,
- .irq = 225,
-};
-
-static const dcfg_arm_gicv2_driver_t gicv2_driver = {
- .mmio_phys = 0xffc00000,
- .gicd_offset = 0x1000,
- .gicc_offset = 0x2000,
- .gich_offset = 0x4000,
- .gicv_offset = 0x6000,
- .ipi_base = 5,
-};
-
-static const dcfg_arm_psci_driver_t psci_driver = {
- .use_hvc = false,
- .reboot_args = { 1, 0, 0 },
- .reboot_bootloader_args = { 4, 0, 0 },
- .reboot_recovery_args = { 2, 0, 0 },
-};
-
-static const dcfg_arm_generic_timer_driver_t timer_driver = {
- .irq_phys = 30,
-};
-
-static const zbi_platform_id_t platform_id = {
- .vid = PDEV_VID_GOOGLE,
- .pid = PDEV_PID_SHERLOCK,
- .board_name = "sherlock",
-};
-
-enum {
- PART_TPL,
- PART_FTS,
- PART_FACTORY,
- PART_ZIRCON_B,
- PART_ZIRCON_A,
- PART_ZIRCON_R,
- PART_FVM,
- PART_SYS_CONFIG,
- PART_MIGRATION,
- PART_COUNT,
-};
-
-#define NEWMAN_FACTORY_IF "mmc"
-#define NEWMAN_FACTORY_PART "1:5"
-#define FACTORY_MAC_ADDR_BUFF_LEN 30
-#define NEWMAN_FACTORY_MACADDR_FILE "mac_addr"
-#define FACTORY_MAC_ADDR_FILE_LEN 25
-
-static int add_mac_addresses(zbi_header_t* zbi) {
- char buffer[FACTORY_MAC_ADDR_BUFF_LEN];
- u64 fullmac[2];
- u8 mac_addr[6];
- int len_read;
- int mac_num, i;
-
- if (fs_set_blk_dev(NEWMAN_FACTORY_IF, NEWMAN_FACTORY_PART,
- FS_TYPE_EXT)) {
- printf("set_blk_dev %s-%s failed.\n",
- NEWMAN_FACTORY_IF, NEWMAN_FACTORY_PART);
- return -1;
- }
-
- if (fs_read(NEWMAN_FACTORY_MACADDR_FILE, buffer, 0,
- FACTORY_MAC_ADDR_BUFF_LEN, &len_read)) {
- printf("Failed to read Mac Addresses from Factory partition\n");
- }
- if (len_read != FACTORY_MAC_ADDR_FILE_LEN) {
- printf("Factory MAC Addr File length (%d) incorrect.\n",
- len_read);
- return -1;
- }
- buffer[len_read] = '\0';
-
- /*
- * "buffer" should now contain two hex strings separated by \n,
- * for a total of 25 bytes. Separate into 2 C strings and convert.
- */
- buffer[len_read/2] = '\0';
- fullmac[0] = simple_strtoull(buffer, NULL, 16);
- fullmac[1] = simple_strtoull(&buffer[(len_read/2)+1], NULL, 16);
-
- for (mac_num = 0; mac_num < ARRAY_SIZE(fullmac); mac_num++) {
- for (i = ARRAY_SIZE(mac_addr)-1; i >= 0; i--) {
- mac_addr[i] = (u8) (fullmac[mac_num] & 0xff);
- fullmac[mac_num] >>= 8;
- }
- zircon_append_boot_item(zbi, ZBI_TYPE_DRV_MAC_ADDRESS, mac_num,
- mac_addr, sizeof(mac_addr));
- }
-
- return 0;
-}
-
-int zircon_preboot(zbi_header_t *zbi)
-{
- /* add CPU configuration */
- zircon_append_boot_item(zbi, ZBI_TYPE_CPU_CONFIG, 0, &cpu_config,
- sizeof(zbi_cpu_config_t) +
- sizeof(zbi_cpu_cluster_t) *
- cpu_config.cluster_count);
-
- /*
- * allocate crashlog save area before 0x5f800000-0x60000000
- * reserved area
- */
- zbi_nvram_t nvram;
-
- nvram.base = 0x5f800000 - NVRAM_LENGTH;
- nvram.length = NVRAM_LENGTH;
- zircon_append_boot_item(zbi, ZBI_TYPE_NVRAM, 0, &nvram, sizeof(nvram));
-
- /* add memory configuration */
- zircon_append_boot_item(zbi, ZBI_TYPE_MEM_CONFIG, 0, &mem_config,
- sizeof(mem_config));
-
- /* add kernel drivers */
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_AMLOGIC_UART,
- &uart_driver, sizeof(uart_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_GIC_V2,
- &gicv2_driver, sizeof(gicv2_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_PSCI,
- &psci_driver, sizeof(psci_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER,
- KDRV_ARM_GENERIC_TIMER,
- &timer_driver, sizeof(timer_driver));
-
- char uboot_ver[] = "bootloader.name=" U_BOOT_VERSION_STRING;
- // Zircon's cmdline parameters cannot contain spaces so
- // convert spaces in autogenerated U-boot version string
- // to underscores.
- // See zircon/docs/kernel_cmdline.md
- int i;
- int len = strlen(uboot_ver);
- for (i = 0; i < len; i++) {
- if (uboot_ver[i] == ' ') {
- uboot_ver[i] = '_';
- }
- }
-
- zircon_append_boot_item(zbi, ZBI_TYPE_CMDLINE, 0, uboot_ver,
- strlen(uboot_ver) + 1);
-
- /* add platform ID */
- zircon_append_boot_item(zbi, ZBI_TYPE_PLATFORM_ID, 0, &platform_id,
- sizeof(platform_id));
-
- int ret = add_mac_addresses(zbi);
-
- if (ret < 0) {
- printf("ERROR: unable to read MAC addresses from the"
- " factory partition!\n");
- }
- return 0;
-}
diff --git a/board/amlogic/g12b_newman_px/Kconfig b/board/amlogic/g12b_newman_px/Kconfig
deleted file mode 100644
index 887a747..0000000
--- a/board/amlogic/g12b_newman_px/Kconfig
+++ /dev/null
@@ -1,25 +0,0 @@
-if TARGET_G12B_NEWMAN_PX
-
-config SYS_BOARD
- default "g12b_newman_px"
-
-config SYS_VENDOR
- default "amlogic"
-
-config SYS_CONFIG_NAME
- default "g12b_newman_px"
-
-config CONFIG_AML_ANTIROLLBACK
- bool
- default n
-
-config G12B_NEWMAN_P2_1
- bool "Additional support for amlogic g12b newman p2.1 board"
- default n
-
-config ZIRCON_BOOT_IMAGE
- bool "Zircon boot image support"
- default n
-
-endif
-
diff --git a/board/amlogic/g12b_newman_px/Makefile b/board/amlogic/g12b_newman_px/Makefile
deleted file mode 100644
index e2f2b99..0000000
--- a/board/amlogic/g12b_newman_px/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-
-obj-y += $(BOARD).o eth_setup.o
-obj-$(CONFIG_AML_LCD) += lcd.o
-obj-$(CONFIG_ZIRCON_BOOT_IMAGE) += zircon.o
diff --git a/board/amlogic/g12b_newman_px/aml-user-key.sig b/board/amlogic/g12b_newman_px/aml-user-key.sig
deleted file mode 100644
index 2ceabc1..0000000
--- a/board/amlogic/g12b_newman_px/aml-user-key.sig
+++ /dev/null
Binary files differ
diff --git a/board/amlogic/g12b_newman_px/eth_setup.c b/board/amlogic/g12b_newman_px/eth_setup.c
deleted file mode 100644
index 85a1b35..0000000
--- a/board/amlogic/g12b_newman_px/eth_setup.c
+++ /dev/null
@@ -1,51 +0,0 @@
-
-/*
- * board/amlogic/g12b_w400_v1/eth_setup.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <malloc.h>
-#include <errno.h>
-#include <environment.h>
-#include <fdt_support.h>
-#include <linux/libfdt.h>
-#include <asm/arch/eth_setup.h>
-/*
- *
- *setup eth device board socket
- *
- */
-struct eth_board_socket* eth_board_setup(char *name){
- struct eth_board_socket* new_board;
- new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
- if (NULL == new_board) return NULL;
- if (name != NULL) {
- new_board->name=(char*)malloc(strlen(name));
- strncpy(new_board->name,name,strlen(name));
- }else{
- new_board->name="gxb";
- }
-
- new_board->eth_pinmux_setup=NULL ;
- new_board->eth_clock_configure=NULL;
- new_board->eth_hw_reset=NULL;
- return new_board;
-}
-//pinmux HHI_GCLK_MPEG1[bit 3]
-//
diff --git a/board/amlogic/g12b_newman_px/firmware/scp_task/pwm_ctrl.h b/board/amlogic/g12b_newman_px/firmware/scp_task/pwm_ctrl.h
deleted file mode 100644
index 9e1824b..0000000
--- a/board/amlogic/g12b_newman_px/firmware/scp_task/pwm_ctrl.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
-*board/amlogic/g12b_newman_px/firmware/scp_task/pwm_ctrl.h
-*table for Dynamic Voltage/Frequency Scaling
-*/
-#ifndef __PWM_CTRL_H__
-#define __PWM_CTRL_H__
-
-static int pwm_voltage_table_ee[][2] = {
- { 0x1c0000, 681},
- { 0x1b0001, 691},
- { 0x1a0002, 701},
- { 0x190003, 711},
- { 0x180004, 721},
- { 0x170005, 731},
- { 0x160006, 741},
- { 0x150007, 751},
- { 0x140008, 761},
- { 0x130009, 772},
- { 0x12000a, 782},
- { 0x11000b, 792},
- { 0x10000c, 802},
- { 0x0f000d, 812},
- { 0x0e000e, 822},
- { 0x0d000f, 832},
- { 0x0c0010, 842},
- { 0x0b0011, 852},
- { 0x0a0012, 862},
- { 0x090013, 872},
- { 0x080014, 882},
- { 0x070015, 892},
- { 0x060016, 902},
- { 0x050017, 912},
- { 0x040018, 922},
- { 0x030019, 932},
- { 0x02001a, 942},
- { 0x01001b, 952},
- { 0x00001c, 962}
-};
-
-#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/g12b_newman_px/firmware/scp_task/pwr_ctrl.c b/board/amlogic/g12b_newman_px/firmware/scp_task/pwr_ctrl.c
deleted file mode 100644
index e5715c9..0000000
--- a/board/amlogic/g12b_newman_px/firmware/scp_task/pwr_ctrl.c
+++ /dev/null
@@ -1,143 +0,0 @@
-
-/*
- * board/amlogic/g12b_w400_v1/firmware/scp_task/pwr_ctrl.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <gpio.h>
-#include "pwm_ctrl.h"
-#ifdef CONFIG_CEC_WAKEUP
-#include <cec_tx_reg.h>
-#endif
-
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
-static void set_vddee_voltage(unsigned int target_voltage)
-{
- unsigned int to;
-
- for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
- if (pwm_voltage_table_ee[to][1] >= target_voltage) {
- break;
- }
- }
-
- if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
- to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
- }
-
- writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
-}
-
-static void power_off_at_24M(unsigned int suspend_from)
-{
- /*set test_n low to power off vcck & vcc 3.3v*/
- writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
- writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
- writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
-
- /*step down ee voltage*/
- set_vddee_voltage(AML_VDDEE_SLEEP_VOLTAGE);
-}
-
-static void power_on_at_24M(unsigned int suspend_from)
-{
- /*step up ee voltage*/
- set_vddee_voltage(AML_VDDEE_INIT_VOLTAGE);
-
- /*set test_n low to power on vcck & vcc 3.3v*/
- writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
- writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
- writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
- _udelay(100);
-}
-
-void get_wakeup_source(void *response, unsigned int suspend_from)
-{
- struct wakeup_info *p = (struct wakeup_info *)response;
- unsigned val;
- unsigned i = 0;
-
- p->status = RESPONSE_OK;
- val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
- BT_WAKEUP_SRC);
-
- p->sources = val;
- p->gpio_info_count = i;
-
-}
-extern void __switch_idle_task(void);
-
-static unsigned int detect_key(unsigned int suspend_from)
-{
- int exit_reason = 0;
- unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
- unsigned char adc_key_cnt = 0;
- init_remote();
- saradc_enable();
-#ifdef CONFIG_CEC_WAKEUP
- if (hdmi_cec_func_config & 0x1) {
- remote_cec_hw_reset();
- cec_node_init();
- }
-#endif
-
- do {
- #ifdef CONFIG_CEC_WAKEUP
- if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
- irq[IRQ_AO_CECB] = 0xFFFFFFFF;
- if (cec_power_on_check())
- exit_reason = CEC_WAKEUP;
- }
- #endif
- if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
- irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
- if (remote_detect_key())
- exit_reason = REMOTE_WAKEUP;
- }
-
- if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
- irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
- if (check_adc_key_resume()) {
- adc_key_cnt++;
- /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
- if (2 == adc_key_cnt)
- exit_reason = POWER_KEY_WAKEUP;
- } else {
- adc_key_cnt = 0;
- }
- }
-
- if (exit_reason)
- break;
- else
- __switch_idle_task();
- } while (1);
-
- saradc_disable();
-
- return exit_reason;
-}
-
-static void pwr_op_init(struct pwr_op *pwr_op)
-{
- pwr_op->power_off_at_24M = power_off_at_24M;
- pwr_op->power_on_at_24M = power_on_at_24M;
- pwr_op->detect_key = detect_key;
- pwr_op->get_wakeup_source = get_wakeup_source;
-}
diff --git a/board/amlogic/g12b_newman_px/firmware/timing.c b/board/amlogic/g12b_newman_px/firmware/timing.c
deleted file mode 100755
index f3f4dac..0000000
--- a/board/amlogic/g12b_newman_px/firmware/timing.c
+++ /dev/null
@@ -1,606 +0,0 @@
-
-/*
- * board/amlogic/g12b_newman_bx/firmware/timing.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/timing.h>
-#include <asm/arch/ddr_define.h>
-
-/* board clk defines */
-#define DDR_SIZE 0
-#define CPU_CLK 1200
-
-/* ddr config support multiple configs for boards which use same bootloader:
- * config steps:
- * 1. add a new data struct in __ddr_setting[]
- * 2. config correct board_id, ddr_type, freq, etc..
- */
-
-
-/* CAUTION!! */
-/* Confirm ddr configs with hardware designer,
- * if you don't know how to config, then don't edit it
- */
-
-/* Key configs */
-/*
- * board_id: check hardware adc config
- * dram_rank_config:
- * #define CONFIG_DDR_CHL_AUTO 0xF
- * #define CONFIG_DDR0_16BIT_CH0 0x1
- * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
- * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
- * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
- * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
- * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
- * DramType:
- * #define CONFIG_DDR_TYPE_DDR3 0
- * #define CONFIG_DDR_TYPE_DDR4 1
- * #define CONFIG_DDR_TYPE_LPDDR4 2
- * #define CONFIG_DDR_TYPE_LPDDR3 3
- * DRAMFreq:
- * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
- *
- */
-
-
-/* ddr configs */
-#define DDR_RFC_TYPE_DDR3_512Mbx1 0
-#define DDR_RFC_TYPE_DDR3_512Mbx2 1
-#define DDR_RFC_TYPE_DDR3_512Mbx4 2
-#define DDR_RFC_TYPE_DDR3_512Mbx8 3
-#define DDR_RFC_TYPE_DDR3_512Mbx16 4
-#define DDR_RFC_TYPE_DDR4_2Gbx1 5
-#define DDR_RFC_TYPE_DDR4_2Gbx2 6
-#define DDR_RFC_TYPE_DDR4_2Gbx4 7
-#define DDR_RFC_TYPE_DDR4_2Gbx8 8
-
-#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
-#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
-#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
-
-ddr_set_t __ddr_setting[] = {
-#ifdef CONFIG_DDR_TIMING_DDR4
-{
- /* g12a skt (u209) ddr4 */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
- .DramType = CONFIG_DDR_TYPE_DDR4,
- .DRAMFreq = {912, 0, 0, 0},
- .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 1,
- .HdtCtrl = 0xC8,
- .dram_cs0_size_MB = 2048,
- .dram_cs1_size_MB = 0,
- .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, // // 2rank use 0x23 0x13 1rank use 0x30 0x30 Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //2rank use 0d0d 1rank use 0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .pll_ssc_mode = 0,
- .clk_drv_ohm = 40,
- .cs_drv_ohm = 40,
- .ac_drv_ohm = 40,
- .soc_data_drv_ohm_p = 34,
- .soc_data_drv_ohm_n = 34,
- .soc_data_odt_ohm_p = 60,
- .soc_data_odt_ohm_n = 0,
- .dram_data_drv_ohm = 48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
- .dram_data_odt_ohm = 60,
- .dram_ac_odt_ohm = 0,
- .soc_clk_slew_rate = 0x3ff,
- .soc_cs_slew_rate = 0x3ff,
- .soc_ac_slew_rate = 0x3ff,
- .soc_data_slew_rate = 0x2ff,
- .vref_output_permil = 500,
- .vref_receiver_permil = 700,
- .vref_dram_permil = 700,
- .ac_trace_delay = {00,00},
- .ac_pinmux = {00,00},
- .ddr_dmc_remap = {
- [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
- [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
- },
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap = {00,00},
- .dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
- .pll_ssc_mode = 0,
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
-},
-#endif
-#ifdef CONFIG_DDR_TIMING_DDR3
-{
- /* g12a skt (u209) ddr3 */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- .dram_rank_config = CONFIG_DDR0_16BIT_RANK01_CH0,
- .DramType = CONFIG_DDR_TYPE_DDR3,
- .DRAMFreq = {912, 0, 0, 0},
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 1,
- .HdtCtrl = 0xC8,
- .dram_cs0_size_MB = 1024,
- .dram_cs1_size_MB = 1024,
- .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, // // 2rank use 0x23 0x13 1rank use 0x30 0x30 Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //2rank use 0d0d 1rank use 0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .pll_ssc_mode = 0,
- .clk_drv_ohm = 40,
- .cs_drv_ohm = 40,
- .ac_drv_ohm = 40,
- .soc_data_drv_ohm_p = 34,
- .soc_data_drv_ohm_n = 34,
- .soc_data_odt_ohm_p = 60, //48,
- .soc_data_odt_ohm_n = 0,
- .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
- .dram_data_odt_ohm = 60,
- .dram_ac_odt_ohm = 0,
- .soc_clk_slew_rate = 0x300,
- .soc_cs_slew_rate = 0x300,
- .soc_ac_slew_rate = 0x300,
- .soc_data_slew_rate = 0x200,
- .vref_output_permil = 500,
- .vref_receiver_permil = 500, //700,
- .vref_dram_permil = 500, //700,
- .ac_trace_delay = {00,00},
- .ac_pinmux = {00,00},
- .ddr_dmc_remap = {
- [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
- [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
- },
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap = {00,00},
- .dram_rtt_nom_wr_park = {00,00},
-
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
-},
-#endif
-{
- /* g12a (google) lpddr4 */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- .fast_boot[0]=6,
- //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
- .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01,
- .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1,
- .DramType = CONFIG_DDR_TYPE_LPDDR4,
-#ifdef CONFIG_G12B_NEWMAN_P2_1
- .DRAMFreq = {1584, 0, 0, 0},
-#else
- .DRAMFreq = {1392, 0, 0, 0},
-#endif
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 0,
- .HdtCtrl = 0xa,
- .dram_cs0_size_MB = 2048,//1024,
- .dram_cs1_size_MB = 0,//1024,
- .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, // // 2rank use 0x23 0x13 1rank use 0x30 0x30 Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //2rank use 0d0d 1rank use 0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .pll_ssc_mode = 0,
- .clk_drv_ohm = 48,
- .cs_drv_ohm = 48,
- .ac_drv_ohm = 48,
- .soc_data_drv_ohm_p = 48,
- .soc_data_drv_ohm_n = 48,
- .soc_data_odt_ohm_p = 0,
- .soc_data_odt_ohm_n = 48,
- .dram_data_drv_ohm = 48, //lpddr4 sdram only240/1-6
- .dram_data_odt_ohm = 48,//120,// 120,
- .dram_ac_odt_ohm = 120,
- .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
- .soc_clk_slew_rate = 0x3ff,//0x253,
- .soc_cs_slew_rate = 0x100,//0x253,
- .soc_ac_slew_rate = 0x100,//0x253,
- .soc_data_slew_rate = 0x1ff,
- .vref_output_permil = 350,//200,
- .vref_receiver_permil = 0,
- .vref_dram_permil = 0,
- //.vref_reverse = 0,
- .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
- //.ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
- .ac_pinmux = {00,00},
- .ddr_dmc_remap = {
- [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
- [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
- [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
- },
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap =
-//{3,2,0,1,7,6,5,4,14,13,12,15,8,9,11,10,20,21,22,23,16,17,19,18,24,25,28,26,31,30,27,29},
- {3,2,0,1,7,6,5,4, 10,9,14,11,8,12,13,15, 20,21,23,22,18,17,19,16, 28,26,25,24,31,30,27,29},
- .dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
- .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
- .diagnose = CONFIG_DIAGNOSE_DISABLE,
- .bitTimeControl_2d = 1,
- .slt_test_function[0]=DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT,
- //.dqs_adjust={100,100,100,100,100,100,100,100,
- // 100,100,100,100,100,100,100,100,
- //}, //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read
-},
-{
- /* use for repair */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
- .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01,
- .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1,
- .DramType = CONFIG_DDR_TYPE_LPDDR4,
- .DRAMFreq = {1584, 0, 0, 0},
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 0,
- .HdtCtrl = 0xa,
- .dram_cs0_size_MB = 2048,//1024,
- .dram_cs1_size_MB = 0,//1024,
- .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, // // 2rank use 0x23 0x13 1rank use 0x30 0x30 Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //2rank use 0d0d 1rank use 0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .pll_ssc_mode = 0,
- .clk_drv_ohm = 40,
- .cs_drv_ohm = 40,
- .ac_drv_ohm = 40,
- .soc_data_drv_ohm_p = 40,
- .soc_data_drv_ohm_n = 40,
- .soc_data_odt_ohm_p = 0,
- .soc_data_odt_ohm_n = 48,
- .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
- .dram_data_odt_ohm = 40,//120,// 120,
- .dram_ac_odt_ohm = 120,
- .lpddr4_dram_vout_voltage_1_3_2_5_setting = 0,///1, 1/3vddq 0 2/5 vddq
- .soc_clk_slew_rate = 0x3ff,//0x253,
- .soc_cs_slew_rate = 0x100,//0x253,
- .soc_ac_slew_rate = 0x100,//0x253,
- .soc_data_slew_rate = 0x1ff,
- .vref_output_permil = 350,//200,
- .vref_receiver_permil = 0,
- .vref_dram_permil = 0,
- //.vref_reverse = 0,
- .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
- //.ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
- .ac_pinmux = {00,00},
- .ddr_dmc_remap = {
- [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
- [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
- [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
- },
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap =
-//{3,2,0,1,7,6,5,4,14,13,12,15,8,9,11,10,20,21,22,23,16,17,19,18,24,25,28,26,31,30,27,29},
- {3,2,0,1,7,6,5,4, 10,9,14,11,8,12,13,15, 20,21,23,22,18,17,19,16, 28,26,25,24,31,30,27,29},
- .dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
- .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
- .diagnose = CONFIG_DIAGNOSE_DISABLE,
- .bitTimeControl_2d = 1,
- //.dqs_adjust={100,100,100,100,100,100,100,100,
- // 100,100,100,100,100,100,100,100,
- //}, //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read
-},
-{
- /* use for fastboot */
- .board_id= CONFIG_BOARD_ID_MASK,
-},
-};
-
-pll_set_t __pll_setting = {
- .cpu_clk = CPU_CLK / 24 * 24,
-#ifdef CONFIG_PXP_EMULATOR
- .pxp = 1,
-#else
- .pxp = 0,
-#endif
- .spi_ctrl = 0,
- .lCustomerID = AML_CUSTOMER_ID,
-};
-
-ddr_reg_t __ddr_reg[] = {
- /* demo, user defined override register */
- {0xaabbccdd, 0, 0, 0, 0, 0},
- {0x11223344, 0, 0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0},
-};
-
-#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
-#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
-/* VCCK PWM table */
-#if (VCCK_VAL == 800)
- #define VCCK_VAL_REG 0x00150007
-#elif (VCCK_VAL == 810)
- #define VCCK_VAL_REG 0x00140008
-#elif (VCCK_VAL == 820)
- #define VCCK_VAL_REG 0x00130009
-#elif (VCCK_VAL == 830)
- #define VCCK_VAL_REG 0x0012000a
-#elif (VCCK_VAL == 840)
- #define VCCK_VAL_REG 0x0011000b
-#elif (VCCK_VAL == 850)
- #define VCCK_VAL_REG 0x0010000c
-#elif (VCCK_VAL == 860)
- #define VCCK_VAL_REG 0x000f000d
-#elif (VCCK_VAL == 870)
- #define VCCK_VAL_REG 0x000e000e
-#elif (VCCK_VAL == 880)
- #define VCCK_VAL_REG 0x000d000f
-#elif (VCCK_VAL == 890)
- #define VCCK_VAL_REG 0x000c0010
-#elif (VCCK_VAL == 900)
- #define VCCK_VAL_REG 0x000b0011
-#elif (VCCK_VAL == 910)
- #define VCCK_VAL_REG 0x000a0012
-#elif (VCCK_VAL == 920)
- #define VCCK_VAL_REG 0x00090013
-#elif (VCCK_VAL == 930)
- #define VCCK_VAL_REG 0x00080014
-#elif (VCCK_VAL == 940)
- #define VCCK_VAL_REG 0x00070015
-#elif (VCCK_VAL == 950)
- #define VCCK_VAL_REG 0x00060016
-#elif (VCCK_VAL == 960)
- #define VCCK_VAL_REG 0x00050017
-#elif (VCCK_VAL == 970)
- #define VCCK_VAL_REG 0x00040018
-#elif (VCCK_VAL == 980)
- #define VCCK_VAL_REG 0x00030019
-#elif (VCCK_VAL == 990)
- #define VCCK_VAL_REG 0x0002001a
-#elif (VCCK_VAL == 1000)
- #define VCCK_VAL_REG 0x0001001b
-#elif (VCCK_VAL == 1010)
- #define VCCK_VAL_REG 0x0000001c
-#else
- #error "VCCK val out of range\n"
-#endif
-
-/* VDDEE_VAL_REG0: VDDEE PWM table 0.67v-0.97v*/
-/* VDDEE_VAL_REG1: VDDEE PWM table 0.69v-0.89v*/
-#if (VDDEE_VAL == 800)
- #define VDDEE_VAL_REG0 0x0010000c
- #define VDDEE_VAL_REG1 0x0008000a
-#elif (VDDEE_VAL == 810)
- #define VDDEE_VAL_REG0 0x000f000d
- #define VDDEE_VAL_REG1 0x0007000b
-#elif (VDDEE_VAL == 820)
- #define VDDEE_VAL_REG0 0x000e000e
- #define VDDEE_VAL_REG1 0x0006000c
-#elif (VDDEE_VAL == 830)
- #define VDDEE_VAL_REG0 0x000d000f
- #define VDDEE_VAL_REG1 0x0005000d
-#elif (VDDEE_VAL == 840)
- #define VDDEE_VAL_REG0 0x000c0010
- #define VDDEE_VAL_REG1 0x0004000e
-#elif (VDDEE_VAL == 850)
- #define VDDEE_VAL_REG0 0x000b0011
- #define VDDEE_VAL_REG1 0x0003000f
-#elif (VDDEE_VAL == 860)
- #define VDDEE_VAL_REG0 0x000a0012
- #define VDDEE_VAL_REG1 0x00020010
-#elif (VDDEE_VAL == 870)
- #define VDDEE_VAL_REG0 0x00090013
- #define VDDEE_VAL_REG1 0x00010011
-#elif (VDDEE_VAL == 880)
- #define VDDEE_VAL_REG0 0x00080014
- #define VDDEE_VAL_REG1 0x00000012
-#else
- #error "VDDEE val out of range\n"
-#endif
-
-/* for PWM use */
-/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
-#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
-/* GPIOC output enable reg */
-#define GPIO_O_EN_N_REG1 ((0xff634400 + (0x13 << 2)))
-/* GPIOA output enable reg */
-#define GPIO_O_EN_N_REG5 ((0xff634400 + (0x20 << 2)))
-#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
-#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
-/* GPIOC input reg */
-#define GPIO_I_REG1 ((0xff634400 + (0x15 << 2)))
-/* GOUIA input reg */
-#define GPIO_I_REG5 ((0xff634400 + (0x22 << 2)))
-/* GPIOC pull up enable reg */
-#define GPIO_PULL_UP_EN_REG1 ((0xff634400 + (0x49 << 2)))
-/* GPIOA pull up enable reg */
-#define GPIO_PULL_UP_EN_REG5 ((0xff634400 + (0x4d << 2)))
-#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
-#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
-/* GPIOC pinmux reg */
-#define GPIO_PIN_MUX_REG9 ((0xff634400 + (0xb9 << 2)))
-/* GPIOA pinmux reg */
-#define GPIO_PIN_MUX_REGE ((0xff634400 + (0xbe << 2)))
-
-
-bl2_reg_t __bl2_reg[] = {
- /* demo, user defined override register */
- /* eg: PWM init */
-
- /* PWM_AO_D */
- /* VCCK_VAL_REG: check PWM table */
- {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
- {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
-
- /* PWM_AO_B */
-
- /* step1: GPIOC5, GPIOC4, GPIOC6, GPIOA12, GPIOA11 pre-init */
- /* disable pullup/pulldown */
- {GPIO_PULL_UP_EN_REG1, (0 << 4), (7 << 4), 0, BL2_INIT_STAGE_PWM_PRE_INIT, 0},
- {GPIO_PULL_UP_EN_REG5, (0 << 11), (3 << 11), 0, BL2_INIT_STAGE_PWM_PRE_INIT, 0},
- /* enable input */
- {GPIO_O_EN_N_REG1, (7 << 4), (7 << 4), 0, BL2_INIT_STAGE_PWM_PRE_INIT, 0},
- {GPIO_O_EN_N_REG5, (3 << 11), (3 << 11), 0, BL2_INIT_STAGE_PWM_PRE_INIT, 0},
- /* pinmux to gpio */
- {GPIO_PIN_MUX_REG9, (0 << 16), (0xfff << 16), 0, BL2_INIT_STAGE_PWM_PRE_INIT, 0},
- {GPIO_PIN_MUX_REGE, (0 << 11), (0xff << 12), 0, BL2_INIT_STAGE_PWM_PRE_INIT, 0},
-
- /* step2: check board config */
- /* HW_ID_0:GPIOA_11
- * HW_ID_1:GPIOA_12
- * HW_ID_2:GPIOC_6
- * HW_ID_3:GPIOC_4
- * HW_ID_4:GPIOC_5
- */
- {GPIO_I_REG1, 5, 0, 0, BL2_INIT_STAGE_PWM_CHK_HW, 0},
- {GPIO_I_REG1, 4, 0, 0, BL2_INIT_STAGE_PWM_CHK_HW, 0},
- {GPIO_I_REG1, 6, 0, 0, BL2_INIT_STAGE_PWM_CHK_HW, 0},
- {GPIO_I_REG5, 12, 0, 0, BL2_INIT_STAGE_PWM_CHK_HW, 0},
- {GPIO_I_REG5, 11, 0, 0, BL2_INIT_STAGE_PWM_CHK_HW, 0},
-
- /* step3: match PWM config */
- /* -----------------------------
- * |newman | option| build |
- * -----------------------------
- * |BRD_ID | 4 | 3 | 2 | 1 | 0 |
- * -----------------------------
- * | | 0 | 1 | 0 | 0 | 0 |
- * -----------------------------
- * | | 0 | 1 | 0 | 0 | 1 |
- * -----------------------------
- * | P1 | 0 | 1 | 0 | 1 | 0 |
- * -----------------------------
- * | P2 | 0 | 1 | 0 | 1 | 1 |
- * -----------------------------
- * | P2RW | 0 | 1 | 1 | 0 | 0 |
- * -----------------------------
- * | P2.1 | 0 | 1 | 1 | 0 | 1 |
- * -----------------------------
- * | EVT | 0 | 1 | 1 | 1 | 0 |
- * -----------------------------
- * | | 0 | 1 | 1 | 1 | 1 |
- * -----------------------------
- *
- * option = b'01 and build < b'011, use PWM_CFG0
- * option = b'01 and build = b'011, use PWM_CFG2 GPIOE_0 output low
- * option = b'01 and build > b'011, use PWM_CFG1
- */
- {0x8, PWM_CFG0, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0x9, PWM_CFG0, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0xa, PWM_CFG0, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0xb, PWM_CFG2, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0xc, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0xd, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0xe, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0xf, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
-
- /* step4: config PWM */
- /* PWM_CFG0: VDDEE PWM table 0.67v ~ 0.97v */
- {AO_PWM_PWM_B, VDDEE_VAL_REG0, 0xffffffff, 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0},
- {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0},
- {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0},
- /* PWM_CFG1: VDDEE PWM table 0.69v ~ 0.89v */
- {AO_PWM_PWM_B, VDDEE_VAL_REG1, 0xffffffff, 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0},
- {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0},
- {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0},
-
- /* PWM_CFG2: VDDEE PWM low; table 0.69v ~ 0.90v */
- {AO_PIN_MUX_REG1, 0, (0xF << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG2, 0},
- {AO_GPIO_O_EN_N, 0, (0x1 << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG2, 0},
- {AO_GPIO_O, 0, (0x1 << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG2, 0},
-
- //GPIOAO_4 set high
- {AO_GPIO_O_EN_N, (0<<4), (1<<4), 0, BL2_INIT_STAGE_1, 0},
- {AO_GPIO_O, (1<<4), (1<<4), 0, BL2_INIT_STAGE_1, 0},
- /* Enable 5V_EN */
- {GPIO_O_EN_N_REG3, (0 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
- {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- /* Enable VCCK */
- {AO_SEC_REG0, (1 << 0), 0x1, 0, BL2_INIT_STAGE_1, 0},
- {AO_GPIO_O, 0x80000000, 0x80000000, 0, BL2_INIT_STAGE_1, 0},};
diff --git a/board/amlogic/g12b_newman_px/g12b_newman_px.c b/board/amlogic/g12b_newman_px/g12b_newman_px.c
deleted file mode 100755
index b6b4ff0..0000000
--- a/board/amlogic/g12b_newman_px/g12b_newman_px.c
+++ /dev/null
@@ -1,1160 +0,0 @@
-
-/*
- * board/amlogic/g12b_newman_px/g12b_newman_px.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <malloc.h>
-#include <errno.h>
-#include <environment.h>
-#include <fdt_support.h>
-#include <linux/libfdt.h>
-#include <asm/arch/cpu_id.h>
-#ifdef CONFIG_SYS_I2C_MESON
-#include <i2c.h>
-#include <dt-bindings/i2c/meson-i2c.h>
-#endif
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/pinctrl_init.h>
-#ifdef CONFIG_AML_VPU
-#include <amlogic/media/vpu/vpu.h>
-#endif
-#ifdef CONFIG_AML_VPP
-#include <amlogic/media/vpp/vpp.h>
-#endif
-#ifdef CONFIG_AML_V2_FACTORY_BURN
-#include <amlogic/aml_v2_burning.h>
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
-#ifdef CONFIG_AML_HDMITX
-#include <amlogic/media/vout/hdmitx.h>
-#endif
-#ifdef CONFIG_AML_LCD
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#endif
-#include <asm/arch/eth_setup.h>
-#include <phy.h>
-#include <linux/mtd/partitions.h>
-#include <linux/sizes.h>
-#include <asm-generic/gpio.h>
-#include <dm.h>
-#ifdef CONFIG_AML_SPIFC
-#include <amlogic/spifc.h>
-#endif
-#ifdef CONFIG_AML_SPICC
-#include <amlogic/spicc.h>
-#endif
-#include <asm/armv8/mmu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-//new static eth setup
-struct eth_board_socket* eth_board_skt;
-
-int do_get_ddictype (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-#if defined(CONFIG_NAND_FTS) || defined(CONFIG_MMC_FTS)
-#if defined(CONFIG_NAND_FTS)
- extern bool amlnf_is_inited(void);
- if (!amlnf_is_inited()) {
-#endif
-
-#if defined(CONFIG_MMC_FTS)
- extern bool amlmmc_is_inited(void);
- if (!amlmmc_is_inited()) {
-#endif
- env_set("ddic_type", "FITI");
- return 0;
- }
-
- flash_ts_init();
-
- const char *fts_key = "ddic.type";
-
- char fts_value[256] = { 0 };
- flash_ts_get(fts_key, fts_value, sizeof(fts_value));
-
- printf("FTS read: ddic.type -> %s\n", fts_value);
-
- if (strncmp(fts_value, "NOVATEK", sizeof(fts_value)) == 0) {
- env_set("ddic_type", "NOVATEK");
- } else {
- env_set("ddic_type", "FITI");
- }
-#endif
- return 0;
-}
-
-U_BOOT_CMD(
- get_ddictype, 1, 0, do_get_ddictype,
- "get ddic type",
- " This command will get and setenv 'ddic_type'\n"
-);
-
-// Disable pull-up resistors for GPIOA_11, GPIOA_12, GPIOC_4, GPIOC_5, GPIOC_6,
-// and GPIOH_3 so the mute switch status and HW ID can be read.
-static void gpio_disable_pullup(void)
-{
- int ret;
-
- ret = readl(PAD_PULL_UP_EN_REG5);
- writel(ret & (~(1 << 11)), PAD_PULL_UP_EN_REG5);
-
- ret = readl(PAD_PULL_UP_EN_REG5);
- writel(ret & (~(1 << 12)), PAD_PULL_UP_EN_REG5);
-
- ret = readl(PAD_PULL_UP_EN_REG1);
- writel(ret & (~(1 << 4)), PAD_PULL_UP_EN_REG1);
-
- ret = readl(PAD_PULL_UP_EN_REG1);
- writel(ret & (~(1 << 5)), PAD_PULL_UP_EN_REG1);
-
- ret = readl(PAD_PULL_UP_EN_REG1);
- writel(ret & (~(1 << 6)), PAD_PULL_UP_EN_REG1);
-
- ret = readl(PAD_PULL_UP_EN_REG3);
- writel(ret & (~(1 << 3)), PAD_PULL_UP_EN_REG3);
-}
-
-int do_get_newman_hw_id(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- unsigned int hw_id = 0, ret = 0;
- char hw_id_str[8] = {0}; // eg: 0x0A
-
- // Reading from highest bit to lowest bit
- // HW_ID_4: GPIOC_5
- ret = readl(P_PREG_PAD_GPIO1_I);
- hw_id |= (ret & (1<<5)) >> 5;
- hw_id = hw_id << 1;
-
- // HW_ID_3: GPIOC_4
- ret = readl(P_PREG_PAD_GPIO1_I);
- hw_id |= (ret & (1<<4)) >> 4;
- hw_id = hw_id << 1;
-
- // HW_ID_2: GPIOC_6
- ret = readl(P_PREG_PAD_GPIO1_I);
- hw_id |= (ret & (1<<6)) >> 6;
- hw_id = hw_id << 1;
-
- // HW_ID_1: GPIOA_12
- ret = readl(P_PREG_PAD_GPIO5_I);
- hw_id |= (ret & (1<<12)) >> 12;
- hw_id = hw_id << 1;
-
- // HW_ID_0: GPIOA_11
- ret = readl(P_PREG_PAD_GPIO5_I);
- hw_id |= (ret & (1<<11)) >> 11;
-
- snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id);
- env_set("hw_id", hw_id_str);
- return 0;
-}
-
-U_BOOT_CMD(
- get_newman_hw_id, 1, 0, do_get_newman_hw_id,
- "get newman's HW_ID and setenv 'hw_id'\n",
- "get_newman_hw_id"
-);
-
-int serial_set_pin_port(unsigned long port_base)
-{
- //UART in "Always On Module"
- //GPIOAO_0==tx,GPIOAO_1==rx
- //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
- return 0;
-}
-
-//SOC_BL_ENABLE
-//#define BL_ENABLE_PIN GPIOEE(GPIOA_10)
-#define BL_ENABLE_PIN_NAME "GPIOA_10"
-
-static void enable_backlight(bool enable)
-{
- int ret;
- struct gpio_desc bl_pow_desc;
-
- ret = dm_gpio_lookup_name("gpioa_10", &bl_pow_desc);
- if (ret) {
- printf("%s: not found\n", "gpioa_10");
- return ret;
- }
-
- ret = dm_gpio_request(&bl_pow_desc, BL_ENABLE_PIN_NAME);
- if (ret && ret != -EBUSY) {
- printf("gpio: requesting pin %s failed\n", BL_ENABLE_PIN_NAME);
- return;
- }
- //gpio_direction_output(BL_ENABLE_PIN, enable ? 1 : 0);
- ret = dm_gpio_set_dir_flags(&bl_pow_desc, GPIOD_IS_OUT);
- if (ret) {
- printf("set direction failed\n");
- return ret;
- }
-
- dm_gpio_set_value(&bl_pow_desc, enable ? 1 : 0);
-}
-
-int dram_init(void)
-{
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-/* secondary_boot_func
- * this function should be write with asm, here, is is only for compiling pass
- * */
-void secondary_boot_func(void)
-{
-}
-#ifdef ETHERNET_INTERNAL_PHY
-void internalPhyConfig(struct phy_device *phydev)
-{
-}
-
-static int dwmac_meson_cfg_pll(void)
-{
- writel(0x39C0040A, P_ETH_PLL_CTL0);
- writel(0x927E0000, P_ETH_PLL_CTL1);
- writel(0xAC5F49E5, P_ETH_PLL_CTL2);
- writel(0x00000000, P_ETH_PLL_CTL3);
- udelay(200);
- writel(0x19C0040A, P_ETH_PLL_CTL0);
- return 0;
-}
-
-static int dwmac_meson_cfg_analog(void)
-{
- /*Analog*/
- writel(0x20200000, P_ETH_PLL_CTL5);
- writel(0x0000c002, P_ETH_PLL_CTL6);
- writel(0x00000023, P_ETH_PLL_CTL7);
-
- return 0;
-}
-
-static int dwmac_meson_cfg_ctrl(void)
-{
- /*config phyid should between a 0~0xffffffff*/
- /*please don't use 44000181, this has been used by internal phy*/
- writel(0x33000180, P_ETH_PHY_CNTL0);
-
- /*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/
- writel(0x260, P_ETH_PHY_CNTL2);
-
- writel(0x74043, P_ETH_PHY_CNTL1);
- writel(0x34043, P_ETH_PHY_CNTL1);
- writel(0x74043, P_ETH_PHY_CNTL1);
- return 0;
-}
-
-static void setup_net_chip(void)
-{
- eth_aml_reg0_t eth_reg0;
-
- eth_reg0.d32 = 0;
- eth_reg0.b.phy_intf_sel = 4;
- eth_reg0.b.rx_clk_rmii_invert = 0;
- eth_reg0.b.rgmii_tx_clk_src = 0;
- eth_reg0.b.rgmii_tx_clk_phase = 0;
- eth_reg0.b.rgmii_tx_clk_ratio = 4;
- eth_reg0.b.phy_ref_clk_enable = 1;
- eth_reg0.b.clk_rmii_i_invert = 1;
- eth_reg0.b.clk_en = 1;
- eth_reg0.b.adj_enable = 1;
- eth_reg0.b.adj_setup = 0;
- eth_reg0.b.adj_delay = 9;
- eth_reg0.b.adj_skew = 0;
- eth_reg0.b.cali_start = 0;
- eth_reg0.b.cali_rise = 0;
- eth_reg0.b.cali_sel = 0;
- eth_reg0.b.rgmii_rx_reuse = 0;
- eth_reg0.b.eth_urgent = 0;
- setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
-
- dwmac_meson_cfg_pll();
- dwmac_meson_cfg_analog();
- dwmac_meson_cfg_ctrl();
-
- /* eth core clock */
- setbits_le32(HHI_GCLK_MPEG1, (0x1 << 3));
- /* eth phy clock */
- setbits_le32(HHI_GCLK_MPEG0, (0x1 << 4));
-
- /* eth phy pll, clk50m */
- setbits_le32(HHI_FIX_PLL_CNTL3, (0x1 << 5));
-
- /* power on memory */
- clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
-}
-#endif
-
-#ifdef ETHERNET_EXTERNAL_PHY
-
-static int dwmac_meson_cfg_drive_strength(void)
-{
- writel(0xaaaaaaa5, P_PAD_DS_REG4A);
- return 0;
-}
-
-static void setup_net_chip_ext(void)
-{
- eth_aml_reg0_t eth_reg0;
- writel(0x11111111, P_PERIPHS_PIN_MUX_6);
- writel(0x111111, P_PERIPHS_PIN_MUX_7);
-
- eth_reg0.d32 = 0;
- eth_reg0.b.phy_intf_sel = 1;
- eth_reg0.b.rx_clk_rmii_invert = 0;
- eth_reg0.b.rgmii_tx_clk_src = 0;
- eth_reg0.b.rgmii_tx_clk_phase = 1;
- eth_reg0.b.rgmii_tx_clk_ratio = 4;
- eth_reg0.b.phy_ref_clk_enable = 1;
- eth_reg0.b.clk_rmii_i_invert = 0;
- eth_reg0.b.clk_en = 1;
- eth_reg0.b.adj_enable = 0;
- eth_reg0.b.adj_setup = 0;
- eth_reg0.b.adj_delay = 0;
- eth_reg0.b.adj_skew = 0;
- eth_reg0.b.cali_start = 0;
- eth_reg0.b.cali_rise = 0;
- eth_reg0.b.cali_sel = 0;
- eth_reg0.b.rgmii_rx_reuse = 0;
- eth_reg0.b.eth_urgent = 0;
- setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
-
- setbits_le32(HHI_GCLK_MPEG1, 0x1 << 3);
- /* power on memory */
- clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
-}
-#endif
-extern struct eth_board_socket* eth_board_setup(char *name);
-extern int designware_initialize(ulong base_addr, u32 interface);
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_ETHERNET_NONE
- return 0;
-#endif
-
-#ifdef ETHERNET_EXTERNAL_PHY
- dwmac_meson_cfg_drive_strength();
- setup_net_chip_ext();
-#endif
-#ifdef ETHERNET_INTERNAL_PHY
- setup_net_chip();
-#endif
- udelay(1000);
- designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
- return 0;
-}
-
-#if CONFIG_AML_SD_EMMC
-#include <mmc.h>
-#include <asm/arch/sd_emmc.h>
-static int sd_emmc_init(unsigned port)
-{
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
- //todo add card detect
- /* check card detect */
- clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
- setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
- setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
- setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
- break;
- case SDIO_PORT_C:
- //enable pull up
- //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
- break;
- default:
- break;
- }
-
- return cpu_sd_emmc_init(port);
-}
-
-extern unsigned sd_debug_board_1bit_flag;
-
-
-static void sd_emmc_pwr_prepare(unsigned port)
-{
- cpu_sd_emmc_pwr_prepare(port);
-}
-
-static void sd_emmc_pwr_on(unsigned port)
-{
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
-// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
-// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
- /// @todo NOT FINISH
- break;
- case SDIO_PORT_C:
- break;
- default:
- break;
- }
- return;
-}
-static void sd_emmc_pwr_off(unsigned port)
-{
- /// @todo NOT FINISH
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
-// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
-// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
- break;
- case SDIO_PORT_C:
- break;
- default:
- break;
- }
- return;
-}
-
-// #define CONFIG_TSD 1
-static void board_mmc_register(unsigned port)
-{
- struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
- if (aml_priv == NULL)
- return;
-
- aml_priv->sd_emmc_init=sd_emmc_init;
- aml_priv->sd_emmc_detect=sd_emmc_detect;
- aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
- aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
- aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
- aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
-
- if (NULL == aml_priv->desc_buf)
- printf(" desc_buf Dma alloc Fail!\n");
- else
- printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
-
- sd_emmc_register(aml_priv);
-}
-int board_mmc_init(bd_t *bis)
-{
-#if 0
-#ifdef CONFIG_VLSI_EMULATOR
- //board_mmc_register(SDIO_PORT_A);
-#else
- //board_mmc_register(SDIO_PORT_B);
-#endif
- board_mmc_register(SDIO_PORT_B);
- board_mmc_register(SDIO_PORT_C);
-// board_mmc_register(SDIO_PORT_B1);
-#endif
- return 0;
-}
-#endif
-
-/* Skip the first line and parse one uint
- * Return negative if not found */
-int parse_backlight_calibration_file_string(const char *str)
-{
- if (str == NULL)
- return -EINVAL;
-
- str = strchr(str, '\n');
- if (str == NULL)
- return -EINVAL;
- ++str;
-
- return simple_strtoul(str, NULL, 10);
-}
-
-/* If zero, this value has not been set and the default brightness should not be
- * overwritten. To store zero, store a non-zero value with its bottom 12 bits
- * all zero, like 0x1000.
- */
-int get_persistent_brightness(void)
-{
- u32 brightness_sticky_val = readl(AO_RTI_STICKY_REG2);
- if (brightness_sticky_val != 0)
- return (brightness_sticky_val & 0x0fff) >> 1;
- return -1;
-}
-
-int do_configure_backlight(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
-#ifdef CONFIG_SYS_I2C_MESON
- int ret, i, attempt;
- const int retries = 3;
- char *addr_cal;
- int calibrated_current, persistent_brightness;
-
- /* Values to write:
- * [0]: Brightness register control only, backlight enabled
- * [1-2]: Standby disabled, 23 mA MAX_CURRENT,
- * CURRENT scale = 20 * 4095 / 23
- * [3]: Enable undervoltage protection at 2.5 V, "disable" backlight
- * (i2c only), disable set resistors
- * [4]: 6-phase, 6 drivers, 9.6kHz PWM rate
- * [5]: EN_DRV3, EN_DRV2, boost inductor current limit = 1.6 A
- * [6]: VBOOST_MAX = 25 V, JUMP_EN = 0
- * [7]: STEP_UP = 105 mV, STEP_DN = 105 mV, LED_FAULT_TH = 3V,
- * LED_COMP_HYST = DRIVER_HEADROOM + 750 mV
- * [8-9]: 12-bit brightness (default: 33.3%)
- * Important: Write brightness last to apply current calibration */
- const __u8 addrs[] = {0x01, 0xa0, 0xa1, 0xa2, 0xa5, 0xa7, 0xa9, 0xae,
- 0x10, 0x11};
- __u8 values[] = {0x85, 0xd3, 0x4b, 0x20, 0x04, 0xf4, 0x60, 0x09,
- 0x55, 0x05};
- const int n_bytes = sizeof(addrs) / sizeof(addrs[0]);
- struct udevice *bl_devp = NULL;
-
- if (argc > 2) {
- printf("%s: Too many args: %d\n", __func__, argc);
- return CMD_RET_USAGE;
- }
-
- if (argc == 2) {
- addr_cal = (char *)simple_strtoul(argv[1], NULL, 16);
- calibrated_current =
- parse_backlight_calibration_file_string(addr_cal);
- if (calibrated_current >= 0 && calibrated_current <= 4095) {
- /* CURRENT_LSB */
- values[1] = 0xff & calibrated_current;
- /* CURRENT_MSB */
- values[2] = (values[2] & 0xf0) |
- (0x0f & (calibrated_current >> 8));
- }
- }
-
- // Apply persistent brightness if found
- persistent_brightness = get_persistent_brightness();
- if (persistent_brightness >= 0) {
- pr_info("Applying persistent_brightness=%d\n", persistent_brightness);
- /* Get LSB and MSB */
- values[n_bytes - 2] = persistent_brightness & 0xff;
- values[n_bytes - 1] = persistent_brightness >> 8 & 0x0f;
- } else {
- pr_info("Persistent_brightness not set\n");
- }
-
- enable_backlight(true);
-
- ret = i2c_get_chip_for_busnum(MESON_I2C_M3, 0X2c, 1, &bl_devp);
- if (ret) {
- printf("%s(%d):i2c get bus fail!\n", __func__, __LINE__);
- }
-
- for (i = 0; i < n_bytes; ++i) {
- for (attempt = 0; attempt < retries; ++attempt) {
- ret = dm_i2c_write(bl_devp, addrs[i], &values[i], 1);
- if (ret)
- printf("%s: Attempt=%d to write byte=0x%02x to reg=0x%02x of backlight failed\n",
- __func__, attempt, values[i], addrs[i]);
- else
- break;
- }
- }
- return ret;
-#else
- enable_backlight(true);
- return 0;
-#endif /* CONFIG_SYS_I2C_MESON */
-}
-
-U_BOOT_CMD(
- configure_backlight, 2, 0, do_configure_backlight,
- "configures the lp8556 backlight",
- "Usage: configure_backlight [calibration_string_addr]\n"\
- " Sets up required parameters of the backlight.\n"\
- " Default calibration is 100%.\n"\
- " calibration_str_addr (optional):\n"\
- " Address of the calibration file string to parse.\n"
-);
-
-#ifdef CONFIG_AML_LCD
-/* Parses one line of the gamma calibration file. */
-/* Returns true on success. */
-#define GAMMA_SIZE (256)
-bool parse_gamma_string(const char *str, uint16_t *table)
-{
- char buf[4] = {'\0'};
- int i;
-
- for (i = 0; i < GAMMA_SIZE; ++i) {
- strncpy(buf, &str[3 * i], 3);
- table[i] = simple_strtol(buf, NULL, 16);
- }
-
- return true;
-}
-
-/* Check header then parse RGB gamma tables */
-/* Returns negative value on error */
-int parse_gamma_calibration_file_string(const char *str, u16 *r, u16 *g, u16 *b)
-{
- static const char supported_header_prefix[] = "Gamma Calibration 1.";
- static const int length = sizeof(supported_header_prefix) - 1;
- char *tables[3] = {r, g, b};
- const char *start, *end;
- int i;
-
- if (!str)
- return -EINVAL;
-
- // Check header prefix - only care about major version.
- if (strncmp(str, supported_header_prefix, length) != 0) {
- printf("Unknown gamma header: \"%.*s\"\n", length, str);
- return -EINVAL;
- }
-
- // Parse all three tables
- end = strchr(str, '\n');
- for (i = 0; i < 3; ++i) {
- start = end + 1;
- end = strchr(start, '\n');
-
- if ((end - start) / 3 != GAMMA_SIZE) {
- printf("Gamma table has invalid length.\n");
- return -EINVAL;
- }
- if (!parse_gamma_string(start, tables[i])) {
- printf("Could not parse gamma table %d.\n", i);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-#endif // CONFIG_AML_LCD
-
-int do_configure_gamma(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
-#ifdef CONFIG_AML_LCD
- static const int N_CHAN = 3;
- char *addr_cal;
- u16 gamma_tables[N_CHAN][GAMMA_SIZE];
- int i, j;
-
- if (argc == 1) {
- // Set to default
- for (i = 0; i < N_CHAN; ++i) {
- for (j = 0; j < GAMMA_SIZE; ++j)
- gamma_tables[i][j] = j << 2; /* 10-bit */
- }
- } else if (argc == 2) {
- // Load from passed file string
- addr_cal = (char *)simple_strtoul(argv[1], NULL, 16);
- if (parse_gamma_calibration_file_string(addr_cal,
- &gamma_tables[0],
- &gamma_tables[1],
- &gamma_tables[2]) != 0)
- return -EINVAL; // Error logged
- } else {
- return CMD_RET_USAGE;
- }
-
- vpp_set_rgb_gamma_table(&gamma_tables[0], &gamma_tables[1],
- &gamma_tables[2]);
-#endif // CONFIG_AML_LCD
- return 0;
-}
-
-U_BOOT_CMD(configure_gamma, 2, 0, do_configure_gamma,
- "configures gamma the gamma tables with the provided calibration\n",
- "Usage: configure_gamma [calibration_string_addr]\n"\
- " Applies the provided calibration file.\n"\
- " If a file is not provided, sets tables to default.\n"\
- " calibration_str_addr (optional):\n"\
- " Address of the calibration file string to parse.\n"
-);
-
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
-int board_early_init_f(void){
- /*add board early init function here*/
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
-#include <asm/arch/usb-v2.h>
-#include <asm/arch/gpio.h>
-#define CONFIG_GXL_USB_U2_PORT_NUM 2
-
-#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
-#define CONFIG_GXL_USB_U3_PORT_NUM 1
-#else
-#define CONFIG_GXL_USB_U3_PORT_NUM 0
-#endif
-
-static void gpio_set_vbus_power(char is_power_on)
-{
- int ret;
-
- ret = gpio_request(CONFIG_USB_GPIO_PWR,
- CONFIG_USB_GPIO_PWR_NAME);
- if (ret && ret != -EBUSY) {
- printf("gpio: requesting pin %u failed\n",
- CONFIG_USB_GPIO_PWR);
- return;
- }
-
- if (is_power_on) {
- gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
- } else {
- gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
- }
-}
-
-struct amlogic_usb_config g_usb_config_GXL_skt={
- CONFIG_GXL_XHCI_BASE,
- USB_ID_MODE_HARDWARE,
- gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
- CONFIG_GXL_USB_PHY2_BASE,
- CONFIG_GXL_USB_PHY3_BASE,
- CONFIG_GXL_USB_U2_PORT_NUM,
- CONFIG_GXL_USB_U3_PORT_NUM,
- .usb_phy2_pll_base_addr = {
- CONFIG_USB_PHY_20,
- CONFIG_USB_PHY_21,
- }
-};
-
-#endif /*CONFIG_USB_XHCI_AMLOGIC*/
-
-#ifdef CONFIG_AML_HDMITX20
-static void hdmi_tx_set_hdmi_5v(void)
-{
-}
-#endif
-
-#ifdef CONFIG_AML_SPIFC
-/*
- * BOOT_3: NOR_HOLDn:reg0[15:12]=3
- * BOOT_4: NOR_D:reg0[19:16]=3
- * BOOT_5: NOR_Q:reg0[23:20]=3
- * BOOT_6: NOR_C:reg0[27:24]=3
- * BOOT_7: NOR_WPn:reg0[31:28]=3
- * BOOT_14: NOR_CS:reg1[27:24]=3
- */
-#define SPIFC_NUM_CS 1
-static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
-
-static int spifc_pinctrl_enable(void *pinctrl, bool enable)
-{
- unsigned int val;
-
- val = readl(P_PERIPHS_PIN_MUX_0);
- val &= ~(0xfffff << 12);
- if (enable)
- val |= 0x33333 << 12;
- writel(val, P_PERIPHS_PIN_MUX_0);
-
- val = readl(P_PERIPHS_PIN_MUX_1);
- val &= ~(0xf << 24);
- writel(val, P_PERIPHS_PIN_MUX_1);
- return 0;
-}
-
-#if 0
-static const struct spifc_platdata spifc_platdata = {
- .reg = 0xffd14000,
- .mem_map = 0xf6000000,
- .pinctrl_enable = spifc_pinctrl_enable,
- .num_chipselect = SPIFC_NUM_CS,
- .cs_gpios = spifc_cs_gpios,
-};
-
-U_BOOT_DEVICE(spifc) = {
- .name = "spifc",
- .platdata = &spifc_platdata,
-};
-#endif
-#endif /* CONFIG_AML_SPIFC */
-
-#if 0
-#ifdef CONFIG_AML_SPICC
-/* generic config in arch gpio/clock.c */
-extern int spicc1_clk_set_rate(int rate);
-extern int spicc1_clk_enable(bool enable);
-extern int spicc1_pinctrl_enable(bool enable);
-
-static const struct spicc_platdata spicc1_platdata = {
- .compatible = "amlogic,meson-g12a-spicc",
- .reg = (void __iomem *)0xffd15000,
- .clk_rate = 666666666,
- .clk_set_rate = spicc1_clk_set_rate,
- .clk_enable = spicc1_clk_enable,
- .pinctrl_enable = spicc1_pinctrl_enable,
- /* case one slave without cs: {"no_cs", 0} */
- .cs_gpio_names = {"GPIOH_6", 0},
-};
-
-U_BOOT_DEVICE(spicc1) = {
- .name = "spicc",
- .platdata = &spicc1_platdata,
-};
-#endif /* CONFIG_AML_SPICC */
-#endif
-
-extern void aml_pwm_cal_init(int mode);
-
-int board_init(void)
-{
- int ret = 0;
- unsigned char value = 0;
-#ifdef CONFIG_SYS_I2C_MESON
- struct udevice *lcd_devp = NULL;
-#endif
- //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
- //As NOT NEED other board init If USB BOOT MODE
-#ifdef CONFIG_AML_V2_FACTORY_BURN
- *(volatile uint32_t *)P_RESET1_LEVEL |= (3 << 16);
- if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
- aml_try_factory_usb_burning(0, gd->bd);
- }
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
-#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
- board_usb_pll_disable(&g_usb_config_GXL_skt);
- board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
-#endif /*CONFIG_USB_XHCI_AMLOGIC*/
- pinctrl_devices_active(PIN_CONTROLLER_NUM);
- enable_backlight(false);
-
-#ifdef CONFIG_SYS_I2C_MESON
- //board_i2c_init();
- // LCD_BIAS_EN is controlled by GPIOH_8
- /* clear GPIOH_8 pinmux */
- ret = readl(P_PERIPHS_PIN_MUX_C);
- writel(ret & (~(0xf)), P_PERIPHS_PIN_MUX_C);
- /* set input mode */
- ret = readl(P_PREG_PAD_GPIO3_EN_N);
- writel(ret | (1<<8), P_PREG_PAD_GPIO3_EN_N);
-
- udelay(1000);
-
- //set lcd bias voltage
- value = 0x0f; // +/- 5.5V
-
- ret = i2c_get_chip_for_busnum(MESON_I2C_M3, 0X3E, 1, &lcd_devp);
- if (ret) {
- printf("%s(%d):i2c get bus fail!\n", __func__, __LINE__);
- }
-
- ret = dm_i2c_write(lcd_devp, 0x0, &value, 1); // VPOS
- if (ret)
- printf("Failed to set VPOS to 5.5V for LCD\n");
-
- ret = dm_i2c_write(lcd_devp, 0x1, &value, 1); // VNEG
- if (ret)
- printf("Failed to set VNEG to -5.5V for LCD\n");
-#endif
-#if 0
- aml_pwm_cal_init(0);
-#endif//
-#ifdef CONFIG_AML_NAND
- extern int amlnf_init(unsigned char flag);
- amlnf_init(0);
-#endif
-
- gpio_disable_pullup();
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- printf("board late init\n");
- run_command("mmc dev 1", 0);
- run_command("defenv", 0);
- run_command("run detect_panel", 0);
-#if 0
- //update env before anyone using it
- run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
- "if test ${reboot_mode} = factory_reset; then "\
- "defenv_reserv;save; fi;", 0);
- run_command("if itest ${upgrade_step} == 1; then "\
- "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
- /*add board late init function here*/
-#ifndef DTB_BIND_KERNEL
- int ret;
- ret = run_command("store dtb read $dtb_mem_addr", 1);
- if (ret) {
- printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
-#ifdef CONFIG_DTB_MEM_ADDR
- char cmd[64];
- printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
- sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
- ret = run_command(cmd, 1);
- if (ret) {
- printf("%s(): %s fail\n", __func__, cmd);
- }
-#endif
- }
-#elif defined(CONFIG_DTB_MEM_ADDR)
- {
- char cmd[128];
- int ret;
- if (!getenv("dtb_mem_addr")) {
- sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
- run_command(cmd, 0);
- }
- sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
- ret = run_command(cmd, 0);
- if (ret) {
- printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
- }
- }
-#endif// #ifndef DTB_BIND_KERNEL
-
- /* load unifykey */
- run_command("keyunify init 0x1234", 0);
-#endif
-/*open vpu hdmitx and cvbs driver*/
-#ifdef CONFIG_AML_VPU
- vpu_probe();
-#endif
-
-#ifdef CONFIG_AML_VPP
- vpp_init();
-#endif
-
-#ifdef CONFIG_AML_HDMITX
- hdmi_tx_init();
-#endif
-
-#ifdef CONFIG_CMD_CVBS
- run_command("cvbs init", 0);
-#endif
-
-#ifdef CONFIG_AML_LCD
- lcd_probe();
-#endif
-
-#if 0
- /**/
- aml_config_dtb();
-#endif
-#ifdef CONFIG_AML_V2_FACTORY_BURN
- if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
- aml_try_factory_usb_burning(1, gd->bd);
- aml_try_factory_sdcard_burning(0, gd->bd);
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_AML_TINY_USBTOOL
-int usb_get_update_result(void)
-{
- unsigned long upgrade_step;
- upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
- printf("upgrade_step = %d\n", (int)upgrade_step);
- if (upgrade_step == 1)
- {
- run_command("defenv", 1);
- run_command("setenv upgrade_step 2", 1);
- run_command("saveenv", 1);
- return 0;
- }
- else
- {
- return -1;
- }
-}
-#endif
-
-phys_size_t get_effective_memsize(void)
-{
- // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
-#if defined(CONFIG_SYS_MEM_TOP_HIDE)
- return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
-#else
- return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
-#endif
-}
-
-#ifdef CONFIG_MULTI_DTB
-int checkhw(char * name)
-{
- /*
- * read board hw id
- * set and select the dts according the board hw id.
- *
- * hwid = 1 p321 v1
- * hwid = 2 p321 v2
- */
- unsigned int hwid = 1;
- char loc_name[64] = {0};
-
- /* read hwid */
- hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
-
- printf("checkhw: hwid = %d\n", hwid);
-
-
- switch (hwid) {
- case 1:
- strcpy(loc_name, "txl_p321_v1\0");
- break;
- case 2:
- strcpy(loc_name, "txl_p321_v2\0");
- break;
- default:
- strcpy(loc_name, "txl_p321_v1");
- break;
- }
- strcpy(name, loc_name);
- setenv("aml_dt", loc_name);
- return 0;
-}
-#endif
-
-static struct mm_region bd_mem_map[] = {
- {
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = bd_mem_map;
-
-void board_nand_init(void) {
- printf("board_nand_init\n");
- return;
-}
-
-int print_cpuinfo(void) {
- printf("print_cpuinfo\n");
- return 0;
-}
-
-int mach_cpu_init(void) {
- printf("mach_cpu_init\n");
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- /* eg: bl31/32 rsv */
- return 0;
-}
-
-/* workaround for VDDEE issue */
-/* VCCK PWM table */
-#define VCCK_VAL_REG_800 0x00150007
-#define VCCK_VAL_REG_810 0x00140008
-#define VCCK_VAL_REG_820 0x00130009
-#define VCCK_VAL_REG_830 0x0012000a
-#define VCCK_VAL_REG_840 0x0011000b
-#define VCCK_VAL_REG_850 0x0010000c
-#define VCCK_VAL_REG_860 0x000f000d
-#define VCCK_VAL_REG_870 0x000e000e
-#define VCCK_VAL_REG_880 0x000d000f
-#define VCCK_VAL_REG_890 0x000c0010
-#define VCCK_VAL_REG_900 0x000b0011
-#define VCCK_VAL_REG_910 0x000a0012
-#define VCCK_VAL_REG_920 0x00090013
-#define VCCK_VAL_REG_930 0x00080014
-#define VCCK_VAL_REG_940 0x00070015
-#define VCCK_VAL_REG_950 0x00060016
-#define VCCK_VAL_REG_960 0x00050017
-#define VCCK_VAL_REG_970 0x00040018
-#define VCCK_VAL_REG_980 0x00030019
-#define VCCK_VAL_REG_990 0x0002001a
-#define VCCK_VAL_REG_1000 0x0001001b
-#define VCCK_VAL_REG_1010 0x0000001c
-#define VCCK_VAL_REG_DEFAULT1 0x00500008
-#define VCCK_VAL_REG_DEFAULT2 0x00860086
-
-
-/* VDDEE PWM table */
-#define VDDEE_VAL_REG_800 0x0010000c
-#define VDDEE_VAL_REG_810 0x000f000d
-#define VDDEE_VAL_REG_820 0x000e000e
-#define VDDEE_VAL_REG_830 0x000d000f
-#define VDDEE_VAL_REG_840 0x000c0010
-#define VDDEE_VAL_REG_850 0x000b0011
-#define VDDEE_VAL_REG_860 0x000a0012
-#define VDDEE_VAL_REG_870 0x00090013
-#define VDDEE_VAL_REG_880 0x00080014
-#define VDDEE_VAL_REG_890 0x00070015
-#define VDDEE_VAL_REG_900 0x00060016
-#define VDDEE_VAL_REG_910 0x00050017
-#define VDDEE_VAL_REG_920 0x00040018
-#define VDDEE_VAL_REG_930 0x00030019
-#define VDDEE_VAL_REG_940 0x0002001a
-#define VDDEE_VAL_REG_950 0x0001001b
-#define VDDEE_VAL_REG_960 0x0000001c
-#define VDDEE_VAL_REG_DEFAULT 0x00500008
-
-void reset_misc(void)
-{
- unsigned int value;
-
- /* adjust VDDCPU_B to Hiz value step by step */
- writel(VCCK_VAL_REG_830, AO_PWM_PWM_D);
- udelay(1);
- writel(VCCK_VAL_REG_860, AO_PWM_PWM_D);
- udelay(1);
-
- /* GPIOE_0 & GPIOE_1 & GPIOE_2 to gpio pin */
- value = readl(AO_RTI_PINMUX_REG1);
- value &= ~(0xfff << 16);
- writel(value, AO_RTI_PINMUX_REG1);
-
- /* disable pwm_ao_b - VDDEE */
- value = readl(AO_PWM_MISC_REG_AB);
- value &= ~((0x1 << 1) | (0x1 << 23));
- writel(value, AO_PWM_MISC_REG_AB);
- writel(VDDEE_VAL_REG_DEFAULT, AO_PWM_PWM_B);
-
- /* disable pwm_ao_d - VDDCPU_B*/
- value = readl(AO_PWM_MISC_REG_CD);
- value &= ~((0x1 << 1) | (0x1 << 23));
- writel(value, AO_PWM_MISC_REG_CD);
- writel(VCCK_VAL_REG_DEFAULT1, AO_PWM_PWM_D);
-
- /* disable pwm_a - VDDCPU_A */
- value = readl(P_PWM_MISC_REG_AB);
- value &= ~((0x1 << 0) | (0x1 << 15));
- writel(value, P_PWM_MISC_REG_AB);
- writel(VCCK_VAL_REG_DEFAULT2, P_PWM_PWM_A);
-}
diff --git a/board/amlogic/g12b_newman_px/lcd.c b/board/amlogic/g12b_newman_px/lcd.c
deleted file mode 100644
index 65d862b..0000000
--- a/board/amlogic/g12b_newman_px/lcd.c
+++ /dev/null
@@ -1,558 +0,0 @@
-/*
- * AMLOGIC LCD panel driver.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#ifdef CONFIG_AML_LCD_EXTERN
-#include "lcd_extern.h"
-#endif
-
-static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
- "GPIOH_6", /* panel rst */
- "GPIOZ_8", /* panel power */
- "invalid", /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step[] = {
- {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,50,}, /* lcd_reset */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,50,}, /* lcd_reset */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step_TL050FHV02CT[] = {
- {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd reset: 0 */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_TL050FHV02CT[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step_TL070WSH27[] = {
- {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd reset: 0 */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_TL070WSH27[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,10,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
- 0x05, 1, 0x11,
- 0xfd, 1, 20,
- 0x05, 1, 0x29,
- 0xfd, 1, 20,
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
- 0x05, 1, 0x28,
- 0xfd, 1, 10,
- 0x05, 1, 0x10,
- 0xfd, 1, 10,
- 0xff, 0, //ending
-};
-
-static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
- 0xfd, 1, 10,
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
- 0xff, 0, //ending
-};
-
-static unsigned char mipi_init_on_table_TL050FHV02CT[DSI_INIT_ON_MAX] = {//table size < 100
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_TL050FHV02CT[DSI_INIT_OFF_MAX] = {//table size < 50
- 0xff, 0, //ending
-};
-
-static unsigned char mipi_init_on_table_TL070WSH27[DSI_INIT_ON_MAX] = {//table size < 100
- 0x05, 1, 0x11,
- 0xfd, 1, 100,
- 0x05, 1, 0x29,
- 0xfd, 1, 20,
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_TL070WSH27[DSI_INIT_OFF_MAX] = {//table size < 50
- 0x05, 1, 0x28,
- 0xfd, 1, 100,
- 0x05, 1, 0x10,
- 0xfd, 1, 10,
- 0xff, 0, //ending
-};
-
-
-static unsigned char mipi_init_on_table_TV070WSM[DSI_INIT_ON_MAX] = {//table size < 100
- 0xff, 10,
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
- 0xff, 100, /* delay */
- 0xff, 0xff, //ending flag
-};
-
-static unsigned char mipi_init_off_table_TV070WSM[DSI_INIT_OFF_MAX] = {//table size < 50
- 0xff,0xff, //ending flag
-};
-
-
-static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
- "invalid", /* ending flag */
-};
-
-struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
- {/* B080XAN01*/
- "lcd_0",LCD_MIPI,8,
- /* basic timing */
- 768,1024,948,1140,64,56,0,50,30,0,
- /* clk_attr */
- 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
- /* cmd init */
- mipi_init_on_table, mipi_init_off_table,
- /* power step */
- lcd_power_on_step, lcd_power_off_step,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* P070ACB_FT*/
- "lcd_1",LCD_MIPI,8,
- /* basic timing */
- 600,1024,770,1070,10,80,0,6,20,0,
- /* clk_attr */
- 0,0,1,49434000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,400,0,1,0,2,0,0,Rsv_val,1,
- /* cmd init */
- mipi_init_on_table_P070ACB, mipi_init_off_table_P070ACB,
- /* power step */
- lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* TL050FHV02CT*/
- "lcd_2",LCD_MIPI,8,
- /* basic timing */
- 1080,1920,1125,2100,5,30,0,44,108,0,
- /* clk_attr */
- 0,0,1,118125000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,960,0,1,0,2,1,0,Rsv_val,2,
- /* cmd init */
- mipi_init_on_table_TL050FHV02CT, mipi_init_off_table_TL050FHV02CT,
- /* power step */
- lcd_power_on_step_TL050FHV02CT, lcd_power_off_step_TL050FHV02CT,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* TL070WSH27*/
- "lcd_3",LCD_MIPI,8,
- /* basic timing */
- 1024,600,1250,630,80,100,0,5,20,0,
- /* clk_attr */
- 0,0,1,47250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,300,0,1,0,2,1,0,Rsv_val,Rsv_val,
- /* cmd init */
- mipi_init_on_table_TL070WSH27, mipi_init_off_table_TL070WSH27,
- /* power step */
- lcd_power_on_step_TL070WSH27, lcd_power_off_step_TL070WSH27,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* BOE TV101WXM*/
- "boe_nvtk_10",LCD_MIPI,8,
- /* basic timing */
- 800,1280,900,1312,24,48,0,4,12,0,
- /* clk_attr */
- 0,0,1,70956000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,568,0,1,0,2,0,0,Rsv_val,3,
- /* cmd init */
- mipi_init_on_table_TV070WSM, mipi_init_off_table_TV070WSM,
- /* power step */
- lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_MAX,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* INNOLUX G101B158 */
- "inx_nvtk_10",LCD_MIPI,8,
- /* basic timing */
- 800,1280,880,1314,18,18,0,4,10,0,
- /* clk_attr */
- 0,0,1,69380000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,560,0,1,0,2,0,0,Rsv_val,4,
- /* cmd init */
- mipi_init_on_table_P070ACB, mipi_init_off_table_P070ACB,
- /* power step */
- lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_MAX,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* BOE TV101WXM FT */
- "boe_fiti_10",LCD_MIPI,8,
- /* basic timing */
- 800,1280,890,1324,20,50,0,4,20,0,
- /* clk_attr */
- 0,0,1,70701600,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,566,0,1,0,2,0,0,Rsv_val,5,
- /* cmd init */
- mipi_init_on_table_TV070WSM, mipi_init_off_table_TV070WSM,
- /* power step */
- lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_MAX,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* INNOLUX G101B158 FT */
- "inx_fiti_10",LCD_MIPI,8,
- /* basic timing */
- 800,1280,890,1324,24,20,0,4,20,0,
- /* clk_attr */
- 0,0,1,70701600,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,566,0,1,0,2,0,0,Rsv_val,6,
- /* cmd init */
- mipi_init_on_table_P070ACB, mipi_init_off_table_P070ACB,
- /* power step */
- lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_MAX,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {.panel_type = "invalid"},
-};
-
-static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
- {
- .name = "lcd_pin",
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
- },
- {
- .name = "invalid",
- },
-};
-
-static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
- {
- .name = "invalid",
- },
-};
-
-#ifdef CONFIG_AML_BL_EXTERN
-static unsigned char bl_ext_init_on[BL_EXTERN_INIT_ON_MAX] = {
- 0xff, 0, //ending flag
-};
-static unsigned char bl_ext_init_off[BL_EXTERN_INIT_OFF_MAX] = {
- 0xff, 0, //ending flag
-};
-#endif
-
-/* **********************************************
- * driver struct, usually no need modify!
- * ********************************************** */
-static struct dsi_config_s lcd_mipi_config = {
- .lane_num = 4,
- .bit_rate_max = 1000, /* MHz */
- .factor_numerator = 0,
- .factor_denominator = 100,
- .operation_mode_init = 1, /* 0=video mode, 1=command mode */
- .operation_mode_display = 0, /* 0=video mode, 1=command mode */
- .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
- .clk_always_hs = 1, /* 0=disable, 1=enable */
- .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
-
- .dsi_init_on = mipi_init_on_table,
- .dsi_init_off = mipi_init_off_table,
- .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
- .check_en = 0,
- .check_state = 0,
-};
-
-static struct lcd_power_ctrl_s lcd_power_ctrl = {
- .power_on_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
- .power_off_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
-};
-
-struct lcd_config_s lcd_config_dft = {
- .lcd_mode = LCD_MODE_TABLET,
- .lcd_key_valid = 0,
- .lcd_clk_path = 0,
- .lcd_basic = {
- .model_name = "default",
- .lcd_type = LCD_TYPE_MAX,
- .lcd_bits = 8,
- .h_active = 768,
- .v_active = 1024,
- .h_period = 948,
- .v_period = 1140,
-
- .screen_width = 119,
- .screen_height = 159,
- },
-
- .lcd_timing = {
- .clk_auto = 1,
- .lcd_clk = 64843200,
- .ss_level = 0,
- .fr_adjust_type = 0,
-
- .hsync_width = 64,
- .hsync_bp = 56,
- .hsync_pol = 0,
- .vsync_width = 50,
- .vsync_bp = 30,
- .vsync_pol = 0,
- },
-
- .lcd_control = {
- .mipi_config= &lcd_mipi_config,
- },
- .lcd_power = &lcd_power_ctrl,
-
- .pinctrl_ver = 2,
- .lcd_pinmux = lcd_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_LCD_EXTERN
-struct lcd_extern_common_s ext_common_dft = {
- .lcd_ext_key_valid = 0,
- .i2c_bus = LCD_EXTERN_I2C_BUS_0, /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
- .i2c_gpio_sck = LCD_EXT_I2C_GPIO_SCK,
- .i2c_gpio_sda = LCD_EXT_I2C_GPIO_SDA,
- .spi_gpio_cs = LCD_EXT_SPI_GPIO_CS,
- .spi_gpio_clk = LCD_EXT_SPI_GPIO_CLK,
- .spi_gpio_data = LCD_EXT_SPI_GPIO_DATA,
-
- .lcd_ext_pinmux = lcd_ext_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
- .pinmux_gpio_off = LCD_EXT_PINMUX_GPIO_OFF,
-};
-
-struct lcd_extern_config_s ext_config_dtf = {
- .index = 0,
- .name = "ext_default",
- .type = LCD_EXTERN_MAX, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 0, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
-};
-#endif
-
-struct bl_config_s bl_config_dft = {
- .name = "default",
- .bl_key_valid = 0,
-
- .level_default = 100,
- .level_min = 10,
- .level_max = 255,
- .level_mid = 128,
- .level_mid_mapping = 128,
- .level = 0,
-
- .method = BL_CTRL_MAX,
- .power_on_delay = 20,
- .power_off_delay = 20,
-
- .en_gpio = 0xff,
- .en_gpio_on = 1,
- .en_gpio_off = 0,
-
- .bl_pwm = NULL,
- .bl_pwm_combo0 = NULL,
- .bl_pwm_combo1 = NULL,
- .pwm_on_delay = 10,
- .pwm_off_delay = 10,
-
- .bl_extern_index = 0xff,
-
- .pinctrl_ver = 2,
- .bl_pinmux = bl_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_BL_EXTERN
-struct bl_extern_config_s bl_extern_config_dtf = {
- .index = BL_EXTERN_INDEX_INVALID,
- .name = "none",
- .type = BL_EXTERN_MAX,
- .i2c_addr = 0xff,
- .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
- .dim_min = 10,
- .dim_max = 255,
-
- .init_loaded = 0,
- .cmd_size = 0xff,
- .init_on = bl_ext_init_on,
- .init_off = bl_ext_init_off,
- .init_on_cnt = sizeof(bl_ext_init_on),
- .init_off_cnt = sizeof(bl_ext_init_off),
-};
-#endif
-/* ********************************************** */
-
-void lcd_config_bsp_init(void)
-{
- int i, j;
- char *str;
- struct ext_lcd_config_s *ext_lcd = NULL;
-
- /* init config, usually no need modify */
- for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
- break;
- strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
- }
- for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
- strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
- for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
- break;
- strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
- }
- for (j = i; j < BL_GPIO_NUM_MAX; j++)
- strcpy(bl_config_dft.gpio_name[j], "invalid");
-
-#ifdef CONFIG_AML_LCD_EXTERN
- for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
- break;
- strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
- }
- for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
- strcpy(ext_common_dft.gpio_name[j], "invalid");
-#endif
-
- /* select special config */
- str = env_get("panel_type");
- if (str == NULL)
- return;
- for (i = 0 ; i < LCD_NUM_MAX ; i++) {
- ext_lcd = &ext_lcd_config[i];
- if (strcmp(ext_lcd->panel_type, str) == 0) {
-#ifdef CONFIG_AML_LCD_EXTERN
- j = ext_lcd->if_attr_val9; /* mipi extern_index */
- if (j < sizeof(ext_config)/sizeof(struct lcd_extern_config_s)) {
- memcpy(&ext_config_dtf, &ext_config[j],
- sizeof(struct lcd_extern_config_s));
- }
-#endif
- break;
- }
- }
-}
diff --git a/board/amlogic/g12b_newman_px/lcd_extern.h b/board/amlogic/g12b_newman_px/lcd_extern.h
deleted file mode 100644
index c0a3c2b..0000000
--- a/board/amlogic/g12b_newman_px/lcd_extern.h
+++ /dev/null
@@ -1,1860 +0,0 @@
-/*
- * board/amlogic/g12a_u200_v1/lcd_extern.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _DFT_LCD_EXTERN_H_
-#define _DFT_LCD_EXTERN_H_
-
-#define LCD_EXT_I2C_GPIO_SCK 0xff /* 0xff for invalid */
-#define LCD_EXT_I2C_GPIO_SDA 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_CS 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_CLK 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_DATA 0xff /* 0xff for invalid */
-#define LCD_EXT_PINMUX_GPIO_OFF 0
-
-static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
- "invalid", /* ending flag */
-};
-
-static struct lcd_pinmux_ctrl_s lcd_ext_pinmux_ctrl[LCD_PINMX_MAX] = {
- {
- .name = "invalid",
- },
-};
-
-static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
- 0xff, 0, //ending flag
-};
-
-static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
- 0xff, 0, //ending flag
-};
-
-static unsigned char ext_init_on_table_P070ACB_FT[LCD_EXTERN_INIT_ON_MAX] = {
- 0x23,2,0xE0,0x00,//Page 0
- 0x23,2,0xE1,0x93,// PASSWORD
- 0x23,2,0xE2,0x65,
- 0x23,2,0xE3,0xF8,
- 0x23,2,0x80,0x03,
- 0x23,2,0xE0,0x01,//Page 01
- 0x23,2,0x0C,0x74,//Set PWRIC
- 0x23,2,0x17,0x00,//Set Gamma Power
- 0x23,2,0x18,0xEF,//VGMP=5.1V
- 0x23,2,0x19,0x00,
- 0x23,2,0x1A,0x00,
- 0x23,2,0x1B,0xEF,//VGMN=-5.1V
- 0x23,2,0x1C,0x00,
- 0x23,2,0x1F,0x70,//Set Gate Power
- 0x23,2,0x20,0x2D,
- 0x23,2,0x21,0x2D,
- 0x23,2,0x22,0x7E,
- 0x23,2,0x26,0xF3,//VDDD from IOVCC
- 0x23,2,0x37,0x09,//SetPanel
- 0x23,2,0x38,0x04,//SET RGBCYC
- 0x23,2,0x39,0x00,
- 0x23,2,0x3A,0x01,
- 0x23,2,0x3C,0x90,
- 0x23,2,0x3D,0xFF,
- 0x23,2,0x3E,0xFF,
- 0x23,2,0x3F,0xFF,
- 0x23,2,0x40,0x02,//Set TCON
- 0x23,2,0x41,0x80,
- 0x23,2,0x42,0x99,
- 0x23,2,0x43,0x14,
- 0x23,2,0x44,0x19,
- 0x23,2,0x45,0x5A,
- 0x23,2,0x4B,0x04,
- 0x23,2,0x55,0x02,//power voltage
- 0x23,2,0x56,0x01,
- 0x23,2,0x57,0x69,
- 0x23,2,0x58,0x0A,
- 0x23,2,0x59,0x0A,
- 0x23,2,0x5A,0x2E,//VGH = 16.2V
- 0x23,2,0x5B,0x19,//VGL = -12V
- 0x23,2,0x5C,0x15,
- 0x23,2,0x5D,0x77,//Gamma
- 0x23,2,0x5E,0x56,
- 0x23,2,0x5F,0x45,
- 0x23,2,0x60,0x38,
- 0x23,2,0x61,0x35,
- 0x23,2,0x62,0x27,
- 0x23,2,0x63,0x2D,
- 0x23,2,0x64,0x18,
- 0x23,2,0x65,0x33,
- 0x23,2,0x66,0x34,
- 0x23,2,0x67,0x35,
- 0x23,2,0x68,0x56,
- 0x23,2,0x69,0x45,
- 0x23,2,0x6A,0x4F,
- 0x23,2,0x6B,0x42,
- 0x23,2,0x6C,0x40,
- 0x23,2,0x6D,0x34,
- 0x23,2,0x6E,0x25,
- 0x23,2,0x6F,0x02,
- 0x23,2,0x70,0x77,
- 0x23,2,0x71,0x56,
- 0x23,2,0x72,0x45,
- 0x23,2,0x73,0x38,
- 0x23,2,0x74,0x35,
- 0x23,2,0x75,0x27,
- 0x23,2,0x76,0x2D,
- 0x23,2,0x77,0x18,
- 0x23,2,0x78,0x33,
- 0x23,2,0x79,0x34,
- 0x23,2,0x7A,0x35,
- 0x23,2,0x7B,0x56,
- 0x23,2,0x7C,0x45,
- 0x23,2,0x7D,0x4F,
- 0x23,2,0x7E,0x42,
- 0x23,2,0x7F,0x40,
- 0x23,2,0x80,0x34,
- 0x23,2,0x81,0x25,
- 0x23,2,0x82,0x02,
- 0x23,2,0xE0,0x02,//Page2
- 0x23,2,0x00,0x53,//GIP_L Pin mapping RESET_EVEN
- 0x23,2,0x01,0x55,//VSSG_EVEN
- 0x23,2,0x02,0x55,//VSSA_EVEN
- 0x23,2,0x03,0x51,//STV2_EVEN
- 0x23,2,0x04,0x77,//VDD2_EVEN
- 0x23,2,0x05,0x57,//VDD1_EVEN
- 0x23,2,0x06,0x1F,
- 0x23,2,0x07,0x4F, //CK12
- 0x23,2,0x08,0x4D, //CK10
- 0x23,2,0x09,0x1F,
- 0x23,2,0x0A,0x4B, //CK8
- 0x23,2,0x0B,0x49, //CK6
- 0x23,2,0x0C,0x1F,
- 0x23,2,0x0D,0x47, //CK4
- 0x23,2,0x0E,0x45, //CK2
- 0x23,2,0x0F,0x41, //STV1_EVEN
- 0x23,2,0x10,0x1F,
- 0x23,2,0x11,0x1F,
- 0x23,2,0x12,0x1F,
- 0x23,2,0x13,0x55, //VGG
- 0x23,2,0x14,0x1F,
- 0x23,2,0x15,0x1F,
- 0x23,2,0x16,0x52,//GIP_R Pin mapping RESET_ODD
- 0x23,2,0x17,0x55, //VSSG_ODD
- 0x23,2,0x18,0x55, //VSSA_ODD
- 0x23,2,0x19,0x50, //STV2_ODD
- 0x23,2,0x1A,0x77,//VDD2_ODD
- 0x23,2,0x1B,0x57,//VDD1_ODD
- 0x23,2,0x1C,0x1F,
- 0x23,2,0x1D,0x4E, //CK11
- 0x23,2,0x1E,0x4C, //CK9
- 0x23,2,0x1F,0x1F,
- 0x23,2,0x20,0x4A, //CK7
- 0x23,2,0x21,0x48, //CK5
- 0x23,2,0x22,0x1F,
- 0x23,2,0x23,0x46, //CK3
- 0x23,2,0x24,0x44, //CK1
- 0x23,2,0x25,0x40,//STV1_ODD
- 0x23,2,0x26,0x1F,
- 0x23,2,0x27,0x1F,
- 0x23,2,0x28,0x1F,
- 0x23,2,0x29,0x1F,
- 0x23,2,0x2A,0x1F,
- 0x23,2,0x2B,0x55, //VGG
- 0x23,2,0x2C,0x12,//GIP_L_GS Pin mapping
- 0x23,2,0x2D,0x15,
- 0x23,2,0x2E,0x15,
- 0x23,2,0x2F,0x00,
- 0x23,2,0x30,0x37,
- 0x23,2,0x31,0x17,
- 0x23,2,0x32,0x1F,
- 0x23,2,0x33,0x08,
- 0x23,2,0x34,0x0A,
- 0x23,2,0x35,0x1F,
- 0x23,2,0x36,0x0C,
- 0x23,2,0x37,0x0E,
- 0x23,2,0x38,0x1F,
- 0x23,2,0x39,0x04,
- 0x23,2,0x3A,0x06,
- 0x23,2,0x3B,0x10,
- 0x23,2,0x3C,0x1F,
- 0x23,2,0x3D,0x1F,
- 0x23,2,0x3E,0x1F,
- 0x23,2,0x3F,0x15,
- 0x23,2,0x40,0x1F,
- 0x23,2,0x41,0x1F,
- 0x23,2,0x42,0x13,//GIP_R_GS Pin mapping
- 0x23,2,0x43,0x15,
- 0x23,2,0x44,0x15,
- 0x23,2,0x45,0x01,
- 0x23,2,0x46,0x37,
- 0x23,2,0x47,0x17,
- 0x23,2,0x48,0x1F,
- 0x23,2,0x49,0x09,
- 0x23,2,0x4A,0x0B,
- 0x23,2,0x4B,0x1F,
- 0x23,2,0x4C,0x0D,
- 0x23,2,0x4D,0x0F,
- 0x23,2,0x4E,0x1F,
- 0x23,2,0x4F,0x05,
- 0x23,2,0x50,0x07,
- 0x23,2,0x51,0x11,
- 0x23,2,0x52,0x1F,
- 0x23,2,0x53,0x1F,
- 0x23,2,0x54,0x1F,
- 0x23,2,0x55,0x1F,
- 0x23,2,0x56,0x1F,
- 0x23,2,0x57,0x15,
- 0x23,2,0x58,0x40,//GIP Timing
- 0x23,2,0x59,0x00,
- 0x23,2,0x5A,0x00,
- 0x23,2,0x5B,0x10,
- 0x23,2,0x5C,0x14,
- 0x23,2,0x5D,0x40,
- 0x23,2,0x5E,0x01,
- 0x23,2,0x5F,0x02,
- 0x23,2,0x60,0x40,
- 0x23,2,0x61,0x03,
- 0x23,2,0x62,0x04,
- 0x23,2,0x63,0x7A,
- 0x23,2,0x64,0x7A,
- 0x23,2,0x65,0x74,
- 0x23,2,0x66,0x16,
- 0x23,2,0x67,0xB4,
- 0x23,2,0x68,0x16,
- 0x23,2,0x69,0x7A,
- 0x23,2,0x6A,0x7A,
- 0x23,2,0x6B,0x0C,
- 0x23,2,0x6C,0x00,
- 0x23,2,0x6D,0x04,
- 0x23,2,0x6E,0x04,
- 0x23,2,0x6F,0x88,
- 0x23,2,0x70,0x00,
- 0x23,2,0x71,0x00,
- 0x23,2,0x72,0x06,
- 0x23,2,0x73,0x7B,
- 0x23,2,0x74,0x00,
- 0x23,2,0x75,0xBC,
- 0x23,2,0x76,0x00,
- 0x23,2,0x77,0x04,
- 0x23,2,0x78,0x2C,
- 0x23,2,0x79,0x00,
- 0x23,2,0x7A,0x00,
- 0x23,2,0x7B,0x00,
- 0x23,2,0x7C,0x00,
- 0x23,2,0x7D,0x03,
- 0x23,2,0x7E,0x7B,
- 0x23,2,0xE0,0x04,//Page4
- 0x23,2,0x09,0x11,//Set RGBCYC2
- 0x23,2,0x0E,0x48,
- 0x23,2,0x2B,0x2B,//ESD Protect
- 0x23,2,0x2E,0x44,
- 0x23,2,0xE0,0x00,//Page0
- 0x23,2,0xE6,0x02,//Watch dog
- 0x23,2,0xE7,0x0C,
- 0x05,1,0x11,//sleep out
- 0xfd, 1,120,
- 0x05,1,0x29,//display on
- 0x05,1,0x35,
- 0xfd, 1, 20, /* delay(ms) */
- 0xFF, 0, /* ending flag */
-};
-
-static unsigned char ext_init_off_table_P070ACB_FT[LCD_EXTERN_INIT_OFF_MAX] = {
- 0x05, 1, 0x28, /* display off */
- 0xfd, 1, 10, /* delay 10ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xfd, 1, 150, /* delay 150ms */
- 0xFF, 0, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_TL050FHV02CT[LCD_EXTERN_INIT_ON_MAX] = {
- //LCD driver initialization
- 0x23, 2, 0XFF, 0X05,
- 0x23, 2, 0XFB, 0X01,
- 0x23, 2, 0XC5, 0X01, //TURN ON
- 0xfd, 1, 100,
-
- //AUO4.97+NT35596_intial
- 0x23, 2, 0XFF, 0XEE, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X1F, 0X45,
- 0x23, 2, 0X24, 0X4F,
- 0x23, 2, 0X38, 0XC8,
- 0x23, 2, 0X39, 0X2C,
- 0x23, 2, 0X1E, 0XBB,
- 0x23, 2, 0X1D, 0X0F,
- 0x23, 2, 0X7E, 0XB1,
-
- 0x23, 2, 0XFF, 0X00, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X35, 0X01,
-
- 0x23, 2, 0XFF, 0X01, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X00, 0X01,
- 0x23, 2, 0X01, 0X55,
- 0x23, 2, 0X02, 0X40,
- 0x23, 2, 0X05, 0X40,
- 0x23, 2, 0X06, 0X4A,
- 0x23, 2, 0X07, 0X24,
- 0x23, 2, 0X08, 0X0C,
- 0x23, 2, 0X0B, 0X87,
- 0x23, 2, 0X0C, 0X87,
- 0x23, 2, 0X0E, 0XB0,
- 0x23, 2, 0X0F, 0XB3,
- 0x23, 2, 0X11, 0X10,
- 0x23, 2, 0X12, 0X10,
- 0x23, 2, 0X13, 0X05,
- 0x23, 2, 0X14, 0X4A,
- 0x23, 2, 0X15, 0X18,
- 0x23, 2, 0X16, 0X18,
- 0x23, 2, 0X18, 0X00,
- 0x23, 2, 0X19, 0X77,
- 0x23, 2, 0X1A, 0X55,
- 0x23, 2, 0X1B, 0X13,
- 0x23, 2, 0X1C, 0X00,
- 0x23, 2, 0X1D, 0X00,
- 0x23, 2, 0X1E, 0X13,
- 0x23, 2, 0X1F, 0X00,
- 0x23, 2, 0X23, 0X00,
- 0x23, 2, 0X24, 0X00,
- 0x23, 2, 0X25, 0X00,
- 0x23, 2, 0X26, 0X00,
- 0x23, 2, 0X27, 0X00,
- 0x23, 2, 0X28, 0X00,
- 0x23, 2, 0X35, 0X00,
- 0x23, 2, 0X66, 0X00,
- 0x23, 2, 0X58, 0X82,
- 0x23, 2, 0X59, 0X02,
- 0x23, 2, 0X5A, 0X02,
- 0x23, 2, 0X5B, 0X02,
- 0x23, 2, 0X5C, 0X82,
- 0x23, 2, 0X5D, 0X82,
- 0x23, 2, 0X5E, 0X02,
- 0x23, 2, 0X5F, 0X02,
- 0x23, 2, 0X72, 0X31,
-
- 0x23, 2, 0XFF, 0X05, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X00, 0X01,
- 0x23, 2, 0X01, 0X0B,
- 0x23, 2, 0X02, 0X0C,
- 0x23, 2, 0X03, 0X09,
- 0x23, 2, 0X04, 0X0A,
- 0x23, 2, 0X05, 0X00,
- 0x23, 2, 0X06, 0X0F,
- 0x23, 2, 0X07, 0X10,
- 0x23, 2, 0X08, 0X00,
- 0x23, 2, 0X09, 0X00,
- 0x23, 2, 0X0A, 0X00,
- 0x23, 2, 0X0B, 0X00,
- 0x23, 2, 0X0C, 0X00,
- 0x23, 2, 0X0D, 0X13,
- 0x23, 2, 0X0E, 0X15,
- 0x23, 2, 0X0F, 0X17,
- 0x23, 2, 0X10, 0X01,
- 0x23, 2, 0X11, 0X0B,
- 0x23, 2, 0X12, 0X0C,
- 0x23, 2, 0X13, 0X09,
- 0x23, 2, 0X14, 0X0A,
- 0x23, 2, 0X15, 0X00,
- 0x23, 2, 0X16, 0X0F,
- 0x23, 2, 0X17, 0X10,
- 0x23, 2, 0X18, 0X00,
- 0x23, 2, 0X19, 0X00,
- 0x23, 2, 0X1A, 0X00,
- 0x23, 2, 0X1B, 0X00,
- 0x23, 2, 0X1C, 0X00,
- 0x23, 2, 0X1D, 0X13,
- 0x23, 2, 0X1E, 0X15,
- 0x23, 2, 0X1F, 0X17,
- 0x23, 2, 0X20, 0X00,
- 0x23, 2, 0X21, 0X03,
- 0x23, 2, 0X22, 0X01,
- 0x23, 2, 0X23, 0X40,
- 0x23, 2, 0X24, 0X40,
- 0x23, 2, 0X25, 0XED,
- 0x23, 2, 0X29, 0X58,
- 0x23, 2, 0X2A, 0X12,
- 0x23, 2, 0X2B, 0X01,
- 0x23, 2, 0X4B, 0X06,
- 0x23, 2, 0X4C, 0X11,
- 0x23, 2, 0X4D, 0X20,
- 0x23, 2, 0X4E, 0X02,
- 0x23, 2, 0X4F, 0X02,
- 0x23, 2, 0X50, 0X20,
- 0x23, 2, 0X51, 0X61,
- 0x23, 2, 0X52, 0X01,
- 0x23, 2, 0X53, 0X63,
- 0x23, 2, 0X54, 0X77,
- 0x23, 2, 0X55, 0XED,
- 0x23, 2, 0X5B, 0X00,
- 0x23, 2, 0X5C, 0X00,
- 0x23, 2, 0X5D, 0X00,
- 0x23, 2, 0X5E, 0X00,
- 0x23, 2, 0X5F, 0X15,
- 0x23, 2, 0X60, 0X75,
- 0x23, 2, 0X61, 0X00,
- 0x23, 2, 0X62, 0X00,
- 0x23, 2, 0X63, 0X00,
- 0x23, 2, 0X64, 0X00,
- 0x23, 2, 0X65, 0X00,
- 0x23, 2, 0X66, 0X00,
- 0x23, 2, 0X67, 0X00,
- 0x23, 2, 0X68, 0X04,
- 0x23, 2, 0X69, 0X00,
- 0x23, 2, 0X6A, 0X00,
- 0x23, 2, 0X6C, 0X40,
- 0x23, 2, 0X75, 0X01,
- 0x23, 2, 0X76, 0X01,
- 0x23, 2, 0X7A, 0X80,
- 0x23, 2, 0X7B, 0XC5,
- 0x23, 2, 0X7C, 0XD8,
- 0x23, 2, 0X7D, 0X60,
- 0x23, 2, 0X7F, 0X15,
- 0x23, 2, 0X80, 0X81,
- 0x23, 2, 0X83, 0X05,
- 0x23, 2, 0X93, 0X08,
- 0x23, 2, 0X94, 0X10,
- 0x23, 2, 0X8A, 0X00,
- 0x23, 2, 0X9B, 0X0F,
- 0x23, 2, 0XEA, 0XFF,
- 0x23, 2, 0XEC, 0X00,
-
- 0x23, 2, 0XFF, 0X01, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X75, 0X00, //Gamma R+
- 0x23, 2, 0X76, 0X18,
- 0x23, 2, 0X77, 0X00,
- 0x23, 2, 0X78, 0X38,
- 0x23, 2, 0X79, 0X00,
- 0x23, 2, 0X7A, 0X65,
- 0x23, 2, 0X7B, 0X00,
- 0x23, 2, 0X7C, 0X84,
- 0x23, 2, 0X7D, 0X00,
- 0x23, 2, 0X7E, 0X9B,
- 0x23, 2, 0X7F, 0X00,
- 0x23, 2, 0X80, 0XAF,
- 0x23, 2, 0X81, 0X00,
- 0x23, 2, 0X82, 0XC1,
- 0x23, 2, 0X83, 0X00,
- 0x23, 2, 0X84, 0XD2,
- 0x23, 2, 0X85, 0X00,
- 0x23, 2, 0X86, 0XDF,
- 0x23, 2, 0X87, 0X01,
- 0x23, 2, 0X88, 0X11,
- 0x23, 2, 0X89, 0X01,
- 0x23, 2, 0X8A, 0X38,
- 0x23, 2, 0X8B, 0X01,
- 0x23, 2, 0X8C, 0X76,
- 0x23, 2, 0X8D, 0X01,
- 0x23, 2, 0X8E, 0XA7,
- 0x23, 2, 0X8F, 0X01,
- 0x23, 2, 0X90, 0XF3,
- 0x23, 2, 0X91, 0X02,
- 0x23, 2, 0X92, 0X2F,
- 0x23, 2, 0X93, 0X02,
- 0x23, 2, 0X94, 0X30,
- 0x23, 2, 0X95, 0X02,
- 0x23, 2, 0X96, 0X66,
- 0x23, 2, 0X97, 0X02,
- 0x23, 2, 0X98, 0XA0,
- 0x23, 2, 0X99, 0X02,
- 0x23, 2, 0X9A, 0XC5,
- 0x23, 2, 0X9B, 0X02,
- 0x23, 2, 0X9C, 0XF8,
- 0x23, 2, 0X9D, 0X03,
- 0x23, 2, 0X9E, 0X1B,
- 0x23, 2, 0X9F, 0X03,
- 0x23, 2, 0XA0, 0X46,
- 0x23, 2, 0XA2, 0X03,
- 0x23, 2, 0XA3, 0X52,
- 0x23, 2, 0XA4, 0X03,
- 0x23, 2, 0XA5, 0X62,
- 0x23, 2, 0XA6, 0X03,
- 0x23, 2, 0XA7, 0X71,
- 0x23, 2, 0XA9, 0X03,
- 0x23, 2, 0XAA, 0X83,
- 0x23, 2, 0XAB, 0X03,
- 0x23, 2, 0XAC, 0X94,
- 0x23, 2, 0XAD, 0X03,
- 0x23, 2, 0XAE, 0XA3,
- 0x23, 2, 0XAF, 0X03,
- 0x23, 2, 0XB0, 0XAD,
- 0x23, 2, 0XB1, 0X03,
- 0x23, 2, 0XB2, 0XCC,
-
- 0x23, 2, 0XB3, 0X00, //Gamma R-
- 0x23, 2, 0XB4, 0X18,
- 0x23, 2, 0XB5, 0X00,
- 0x23, 2, 0XB6, 0X38,
- 0x23, 2, 0XB7, 0X00,
- 0x23, 2, 0XB8, 0X65,
- 0x23, 2, 0XB9, 0X00,
- 0x23, 2, 0XBA, 0X84,
- 0x23, 2, 0XBB, 0X00,
- 0x23, 2, 0XBC, 0X9B,
- 0x23, 2, 0XBD, 0X00,
- 0x23, 2, 0XBE, 0XAF,
- 0x23, 2, 0XBF, 0X00,
- 0x23, 2, 0XC0, 0XC1,
- 0x23, 2, 0XC1, 0X00,
- 0x23, 2, 0XC2, 0XD2,
- 0x23, 2, 0XC3, 0X00,
- 0x23, 2, 0XC4, 0XDF,
- 0x23, 2, 0XC5, 0X01,
- 0x23, 2, 0XC6, 0X11,
- 0x23, 2, 0XC7, 0X01,
- 0x23, 2, 0XC8, 0X38,
- 0x23, 2, 0XC9, 0X01,
- 0x23, 2, 0XCA, 0X76,
- 0x23, 2, 0XCB, 0X01,
- 0x23, 2, 0XCC, 0XA7,
- 0x23, 2, 0XCD, 0X01,
- 0x23, 2, 0XCE, 0XF3,
- 0x23, 2, 0XCF, 0X02,
- 0x23, 2, 0XD0, 0X2F,
- 0x23, 2, 0XD1, 0X02,
- 0x23, 2, 0XD2, 0X30,
- 0x23, 2, 0XD3, 0X02,
- 0x23, 2, 0XD4, 0X66,
- 0x23, 2, 0XD5, 0X02,
- 0x23, 2, 0XD6, 0XA0,
- 0x23, 2, 0XD7, 0X02,
- 0x23, 2, 0XD8, 0XC5,
- 0x23, 2, 0XD9, 0X02,
- 0x23, 2, 0XDA, 0XF8,
- 0x23, 2, 0XDB, 0X03,
- 0x23, 2, 0XDC, 0X1B,
- 0x23, 2, 0XDD, 0X03,
- 0x23, 2, 0XDE, 0X46,
- 0x23, 2, 0XDF, 0X03,
- 0x23, 2, 0XE0, 0X52,
- 0x23, 2, 0XE1, 0X03,
- 0x23, 2, 0XE2, 0X62,
- 0x23, 2, 0XE3, 0X03,
- 0x23, 2, 0XE4, 0X71,
- 0x23, 2, 0XE5, 0X03,
- 0x23, 2, 0XE6, 0X83,
- 0x23, 2, 0XE7, 0X03,
- 0x23, 2, 0XE8, 0X94,
- 0x23, 2, 0XE9, 0X03,
- 0x23, 2, 0XEA, 0XA3,
- 0x23, 2, 0XEB, 0X03,
- 0x23, 2, 0XEC, 0XAD,
- 0x23, 2, 0XED, 0X03,
- 0x23, 2, 0XEE, 0XCC,
-
- 0x23, 2, 0XEF, 0X00, //Gamma G+
- 0x23, 2, 0XF0, 0X18,
- 0x23, 2, 0XF1, 0X00,
- 0x23, 2, 0XF2, 0X38,
- 0x23, 2, 0XF3, 0X00,
- 0x23, 2, 0XF4, 0X65,
- 0x23, 2, 0XF5, 0X00,
- 0x23, 2, 0XF6, 0X84,
- 0x23, 2, 0XF7, 0X00,
- 0x23, 2, 0XF8, 0X9B,
- 0x23, 2, 0XF9, 0X00,
- 0x23, 2, 0XFA, 0XAF,
- 0x23, 2, 0XFF, 0X02, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X00, 0X00,
- 0x23, 2, 0X01, 0XC1,
- 0x23, 2, 0X02, 0X00,
- 0x23, 2, 0X03, 0XD2,
- 0x23, 2, 0X04, 0X00,
- 0x23, 2, 0X05, 0XDF,
- 0x23, 2, 0X06, 0X01,
- 0x23, 2, 0X07, 0X11,
- 0x23, 2, 0X08, 0X01,
- 0x23, 2, 0X09, 0X38,
- 0x23, 2, 0X0A, 0X01,
- 0x23, 2, 0X0B, 0X76,
- 0x23, 2, 0X0C, 0X01,
- 0x23, 2, 0X0D, 0XA7,
- 0x23, 2, 0X0E, 0X01,
- 0x23, 2, 0X0F, 0XF3,
- 0x23, 2, 0X10, 0X02,
- 0x23, 2, 0X11, 0X2F,
- 0x23, 2, 0X12, 0X02,
- 0x23, 2, 0X13, 0X30,
- 0x23, 2, 0X14, 0X02,
- 0x23, 2, 0X15, 0X66,
- 0x23, 2, 0X16, 0X02,
- 0x23, 2, 0X17, 0XA0,
- 0x23, 2, 0X18, 0X02,
- 0x23, 2, 0X19, 0XC5,
- 0x23, 2, 0X1A, 0X02,
- 0x23, 2, 0X1B, 0XF8,
- 0x23, 2, 0X1C, 0X03,
- 0x23, 2, 0X1D, 0X1B,
- 0x23, 2, 0X1E, 0X03,
- 0x23, 2, 0X1F, 0X46,
- 0x23, 2, 0X20, 0X03,
- 0x23, 2, 0X21, 0X52,
- 0x23, 2, 0X22, 0X03,
- 0x23, 2, 0X23, 0X62,
- 0x23, 2, 0X24, 0X03,
- 0x23, 2, 0X25, 0X71,
- 0x23, 2, 0X26, 0X03,
- 0x23, 2, 0X27, 0X83,
- 0x23, 2, 0X28, 0X03,
- 0x23, 2, 0X29, 0X94,
- 0x23, 2, 0X2A, 0X03,
- 0x23, 2, 0X2B, 0XA3,
- 0x23, 2, 0X2D, 0X03,
- 0x23, 2, 0X2F, 0XAD,
- 0x23, 2, 0X30, 0X03,
- 0x23, 2, 0X31, 0XCC,
-
- 0x23, 2, 0X32, 0X00, //Gamma G-
- 0x23, 2, 0X33, 0X18,
- 0x23, 2, 0X34, 0X00,
- 0x23, 2, 0X35, 0X38,
- 0x23, 2, 0X36, 0X00,
- 0x23, 2, 0X37, 0X65,
- 0x23, 2, 0X38, 0X00,
- 0x23, 2, 0X39, 0X84,
- 0x23, 2, 0X3A, 0X00,
- 0x23, 2, 0X3B, 0X9B,
- 0x23, 2, 0X3D, 0X00,
- 0x23, 2, 0X3F, 0XAF,
- 0x23, 2, 0X40, 0X00,
- 0x23, 2, 0X41, 0XC1,
- 0x23, 2, 0X42, 0X00,
- 0x23, 2, 0X43, 0XD2,
- 0x23, 2, 0X44, 0X00,
- 0x23, 2, 0X45, 0XDF,
- 0x23, 2, 0X46, 0X01,
- 0x23, 2, 0X47, 0X11,
- 0x23, 2, 0X48, 0X01,
- 0x23, 2, 0X49, 0X38,
- 0x23, 2, 0X4A, 0X01,
- 0x23, 2, 0X4B, 0X76,
- 0x23, 2, 0X4C, 0X01,
- 0x23, 2, 0X4D, 0XA7,
- 0x23, 2, 0X4E, 0X01,
- 0x23, 2, 0X4F, 0XF3,
- 0x23, 2, 0X50, 0X02,
- 0x23, 2, 0X51, 0X2F,
- 0x23, 2, 0X52, 0X02,
- 0x23, 2, 0X53, 0X30,
- 0x23, 2, 0X54, 0X02,
- 0x23, 2, 0X55, 0X66,
- 0x23, 2, 0X56, 0X02,
- 0x23, 2, 0X58, 0XA0,
- 0x23, 2, 0X59, 0X02,
- 0x23, 2, 0X5A, 0XC5,
- 0x23, 2, 0X5B, 0X02,
- 0x23, 2, 0X5C, 0XF8,
- 0x23, 2, 0X5D, 0X03,
- 0x23, 2, 0X5E, 0X1B,
- 0x23, 2, 0X5F, 0X03,
- 0x23, 2, 0X60, 0X46,
- 0x23, 2, 0X61, 0X03,
- 0x23, 2, 0X62, 0X52,
- 0x23, 2, 0X63, 0X03,
- 0x23, 2, 0X64, 0X62,
- 0x23, 2, 0X65, 0X03,
- 0x23, 2, 0X66, 0X71,
- 0x23, 2, 0X67, 0X03,
- 0x23, 2, 0X68, 0X83,
- 0x23, 2, 0X69, 0X03,
- 0x23, 2, 0X6A, 0X94,
- 0x23, 2, 0X6B, 0X03,
- 0x23, 2, 0X6C, 0XA3,
- 0x23, 2, 0X6D, 0X03,
- 0x23, 2, 0X6E, 0XAD,
- 0x23, 2, 0X6F, 0X03,
- 0x23, 2, 0X70, 0XCC,
-
- 0x23, 2, 0X71, 0X00, //Gamma B+
- 0x23, 2, 0X72, 0X18,
- 0x23, 2, 0X73, 0X00,
- 0x23, 2, 0X74, 0X38,
- 0x23, 2, 0X75, 0X00,
- 0x23, 2, 0X76, 0X65,
- 0x23, 2, 0X77, 0X00,
- 0x23, 2, 0X78, 0X84,
- 0x23, 2, 0X79, 0X00,
- 0x23, 2, 0X7A, 0X9B,
- 0x23, 2, 0X7B, 0X00,
- 0x23, 2, 0X7C, 0XAF,
- 0x23, 2, 0X7D, 0X00,
- 0x23, 2, 0X7E, 0XC1,
- 0x23, 2, 0X7F, 0X00,
- 0x23, 2, 0X80, 0XD2,
- 0x23, 2, 0X81, 0X00,
- 0x23, 2, 0X82, 0XDF,
- 0x23, 2, 0X83, 0X01,
- 0x23, 2, 0X84, 0X11,
- 0x23, 2, 0X85, 0X01,
- 0x23, 2, 0X86, 0X38,
- 0x23, 2, 0X87, 0X01,
- 0x23, 2, 0X88, 0X76,
- 0x23, 2, 0X89, 0X01,
- 0x23, 2, 0X8A, 0XA7,
- 0x23, 2, 0X8B, 0X01,
- 0x23, 2, 0X8C, 0XF3,
- 0x23, 2, 0X8D, 0X02,
- 0x23, 2, 0X8E, 0X2F,
- 0x23, 2, 0X8F, 0X02,
- 0x23, 2, 0X90, 0X30,
- 0x23, 2, 0X91, 0X02,
- 0x23, 2, 0X92, 0X66,
- 0x23, 2, 0X93, 0X02,
- 0x23, 2, 0X94, 0XA0,
- 0x23, 2, 0X95, 0X02,
- 0x23, 2, 0X96, 0XC5,
- 0x23, 2, 0X97, 0X02,
- 0x23, 2, 0X98, 0XF8,
- 0x23, 2, 0X99, 0X03,
- 0x23, 2, 0X9A, 0X1B,
- 0x23, 2, 0X9B, 0X03,
- 0x23, 2, 0X9C, 0X46,
- 0x23, 2, 0X9D, 0X03,
- 0x23, 2, 0X9E, 0X52,
- 0x23, 2, 0X9F, 0X03,
- 0x23, 2, 0XA0, 0X62,
- 0x23, 2, 0XA2, 0X03,
- 0x23, 2, 0XA3, 0X71,
- 0x23, 2, 0XA4, 0X03,
- 0x23, 2, 0XA5, 0X83,
- 0x23, 2, 0XA6, 0X03,
- 0x23, 2, 0XA7, 0X94,
- 0x23, 2, 0XA9, 0X03,
- 0x23, 2, 0XAA, 0XA3,
- 0x23, 2, 0XAB, 0X03,
- 0x23, 2, 0XAC, 0XAD,
- 0x23, 2, 0XAD, 0X03,
- 0x23, 2, 0XAE, 0XCC,
-
- 0x23, 2, 0XAF, 0X00, //Gamma B-
- 0x23, 2, 0XB0, 0X18,
- 0x23, 2, 0XB1, 0X00,
- 0x23, 2, 0XB2, 0X38,
- 0x23, 2, 0XB3, 0X00,
- 0x23, 2, 0XB4, 0X65,
- 0x23, 2, 0XB5, 0X00,
- 0x23, 2, 0XB6, 0X84,
- 0x23, 2, 0XB7, 0X00,
- 0x23, 2, 0XB8, 0X9B,
- 0x23, 2, 0XB9, 0X00,
- 0x23, 2, 0XBA, 0XAF,
- 0x23, 2, 0XBB, 0X00,
- 0x23, 2, 0XBC, 0XC1,
- 0x23, 2, 0XBD, 0X00,
- 0x23, 2, 0XBE, 0XD2,
- 0x23, 2, 0XBF, 0X00,
- 0x23, 2, 0XC0, 0XDF,
- 0x23, 2, 0XC1, 0X01,
- 0x23, 2, 0XC2, 0X11,
- 0x23, 2, 0XC3, 0X01,
- 0x23, 2, 0XC4, 0X38,
- 0x23, 2, 0XC5, 0X01,
- 0x23, 2, 0XC6, 0X76,
- 0x23, 2, 0XC7, 0X01,
- 0x23, 2, 0XC8, 0XA7,
- 0x23, 2, 0XC9, 0X01,
- 0x23, 2, 0XCA, 0XF3,
- 0x23, 2, 0XCB, 0X02,
- 0x23, 2, 0XCC, 0X2F,
- 0x23, 2, 0XCD, 0X02,
- 0x23, 2, 0XCE, 0X30,
- 0x23, 2, 0XCF, 0X02,
- 0x23, 2, 0XD0, 0X66,
- 0x23, 2, 0XD1, 0X02,
- 0x23, 2, 0XD2, 0XA0,
- 0x23, 2, 0XD3, 0X02,
- 0x23, 2, 0XD4, 0XC5,
- 0x23, 2, 0XD5, 0X02,
- 0x23, 2, 0XD6, 0XF8,
- 0x23, 2, 0XD7, 0X03,
- 0x23, 2, 0XD8, 0X1B,
- 0x23, 2, 0XD9, 0X03,
- 0x23, 2, 0XDA, 0X46,
- 0x23, 2, 0XDB, 0X03,
- 0x23, 2, 0XDC, 0X52,
- 0x23, 2, 0XDD, 0X03,
- 0x23, 2, 0XDE, 0X62,
- 0x23, 2, 0XDF, 0X03,
- 0x23, 2, 0XE0, 0X71,
- 0x23, 2, 0XE1, 0X03,
- 0x23, 2, 0XE2, 0X83,
- 0x23, 2, 0XE3, 0X03,
- 0x23, 2, 0XE4, 0X94,
- 0x23, 2, 0XE5, 0X03,
- 0x23, 2, 0XE6, 0XA3,
- 0x23, 2, 0XE7, 0X03,
- 0x23, 2, 0XE8, 0XAD,
- 0x23, 2, 0XE9, 0X03,
- 0x23, 2, 0XEA, 0XCC,
-
- 0x23, 2, 0XFF, 0X01, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0XFF, 0X02, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0XFF, 0X04, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0XFF, 0X00, //CMD page select
-
- 0x23, 2, 0XD3, 0X05,
- 0x23, 2, 0XD4, 0X04,
-
- 0x23, 2, 0X11, 0X00, //Sleep out
- 0xfd, 1, 100, //delay 100ms
- 0x23, 2, 0XFF, 0X00,
-
- 0x23, 2, 0X35, 0X00, //TE on
-
- 0x23, 2, 0X29, 0X00, //Display on
- 0xfd, 1, 100, //delay 100ms
- 0xff, 0, /* ending flag */
-};
-
-static unsigned char ext_init_off_table_TL050FHV02CT[LCD_EXTERN_INIT_OFF_MAX] = {
- 0x05, 1, 0x28, /* display off */
- 0xfd, 1, 10, /* delay 10ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xfd, 1, 150, /* delay 150ms */
- 0xFF, 0, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_TV101WXM[LCD_EXTERN_INIT_ON_MAX] = {
- 0xFF, 120,
- 0x29, 5, 0xFF, 0xAA, 0x55, 0x25, 0x01,
- 0x23, 2, 0xFC, 0x08,
- 0xFF, 1,
- 0x23, 2, 0xFC, 0x00,
- 0x29, 5, 0xFF, 0xAA, 0x55, 0x25, 0x00,
- 0xFF, 20,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x00,
- 0x29, 3, 0xB1, 0x68, 0x01,
- 0x29, 5, 0xB8, 0x01, 0x02, 0x02, 0x02,
- 0x23, 2, 0xB6, 0x11,
- 0x29, 3, 0xBB, 0x63, 0x63,
- 0x29, 3, 0xBC, 0x00, 0x00,
- 0x29, 6, 0xBD, 0x02, 0xBB, 0x11, 0x10, 0x00,
- 0x23, 2, 0xC8, 0x80,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x01,
- 0x29, 3, 0xB3, 0x28, 0x28,
- 0x29, 3, 0xB4, 0x14, 0x14,
- 0x29, 3, 0xB9, 0x44, 0x44,
- 0x29, 3, 0xBA, 0x24, 0x24,
- 0x29, 3, 0xBC, 0x70, 0x00,
- 0x29, 3, 0xBD, 0x70, 0x00,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x02,
- 0x23, 2, 0xEE, 0x03,
- 0x29, 17, 0xB0, 0x01, 0x04, 0x01, 0x08, 0x01, 0x11, 0x01, 0x19, 0x01, 0x21, 0x01, 0x30, 0x01, 0x3D, 0x01, 0x55,
- 0x29, 17, 0xB1, 0x01, 0x6B, 0x01, 0x94, 0x01, 0xB5, 0x01, 0xED, 0x02, 0x20, 0x02, 0x22, 0x02, 0x53, 0x02, 0x8F,
- 0x29, 17, 0xB2, 0x02, 0xB4, 0x02, 0xE5, 0x03, 0x03, 0x03, 0x30, 0x03, 0x51, 0x03, 0x76, 0x03, 0x96, 0x03, 0xB8,
- 0x29, 5, 0xB3, 0x03, 0xCF, 0x03, 0xD2,
- 0x29, 17, 0xB4, 0x00, 0x00, 0x00, 0x13, 0x00, 0x31, 0x00, 0x4B, 0x00, 0x61, 0x00, 0x87, 0x00, 0xA7, 0x00, 0xDB,
- 0x29, 17, 0xB5, 0x01, 0x04, 0x01, 0x43, 0x01, 0x76, 0x01, 0xC9, 0x02, 0x05, 0x02, 0x06, 0x02, 0x3F, 0x02, 0x7D,
- 0x29, 17, 0xB6, 0x02, 0xA3, 0x02, 0xD3, 0x02, 0xF6, 0x03, 0x23, 0x03, 0x44, 0x03, 0x6C, 0x03, 0x8A, 0x03, 0xAE,
- 0x29, 5, 0xB7, 0x03, 0xCF, 0x03, 0xD2,
- 0x29, 17, 0xB8, 0x00, 0x41, 0x00, 0x4A, 0x00, 0x5D, 0x00, 0x6D, 0x00, 0x7E, 0x00, 0x9A, 0x00, 0xB4, 0x00, 0xDF,
- 0x29, 17, 0xB9, 0x01, 0x04, 0x01, 0x43, 0x01, 0x74, 0x01, 0xC6, 0x02, 0x03, 0x02, 0x09, 0x02, 0x40, 0x02, 0x7E,
- 0x29, 17, 0xBA, 0x02, 0xA4, 0x02, 0xD6, 0x02, 0xF7, 0x03, 0x25, 0x03, 0x44, 0x03, 0x6C, 0x03, 0x88, 0x03, 0xA8,
- 0x29, 5, 0xBB, 0x03, 0xD0, 0x03, 0xD2,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x03,
- 0x29, 3, 0xB0, 0x00, 0x00,
- 0x29, 3, 0xB1, 0x00, 0x00,
- 0x29, 6, 0xB2, 0x05, 0x01, 0x55, 0x00, 0x1A,
- 0x29, 6, 0xB3, 0x05, 0x01, 0x55, 0x00, 0x1A,
- 0x29, 6, 0xBA, 0x53, 0x01, 0x55, 0x00, 0x3A,
- 0x23, 2, 0xC4, 0x60,
- 0x23, 2, 0xC5, 0x40,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x04,
- 0x29, 5, 0xB1, 0x03, 0x02, 0x05, 0x07,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x05,
- 0x29, 6, 0xBD, 0x01, 0x03, 0x00, 0x00, 0x03,
- 0x23, 2, 0xC0, 0x09,
- 0x23, 2, 0xC1, 0x07,
- 0x29, 3, 0xC8, 0x07, 0x38,
- 0x23, 2, 0xD0, 0x00,
- 0x23, 2, 0xE5, 0x03,
- 0x23, 2, 0xE6, 0x03,
- 0x23, 2, 0xE9, 0x03,
- 0x23, 2, 0xEA, 0x03,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x06,
- 0x29, 3, 0xB0, 0x2D, 0x2D,
- 0x29, 3, 0xB1, 0x01, 0x01,
- 0x29, 3, 0xB2, 0x03, 0x03,
- 0x29, 3, 0xB3, 0x2E, 0x2E,
- 0x29, 3, 0xB4, 0x2E, 0x2D,
- 0x29, 3, 0xB5, 0x2D, 0x13,
- 0x29, 3, 0xB6, 0x13, 0x11,
- 0x29, 3, 0xB7, 0x11, 0x36,
- 0x29, 3, 0xB8, 0x36, 0x15,
- 0x29, 3, 0xB9, 0x15, 0x2E,
- 0x29, 3, 0xBA, 0x2E, 0x14,
- 0x29, 3, 0xBB, 0x14, 0x35,
- 0x29, 3, 0xBC, 0x35, 0x10,
- 0x29, 3, 0xBD, 0x10, 0x12,
- 0x29, 3, 0xBE, 0x12, 0x2D,
- 0x29, 3, 0xBF, 0x2D, 0x2E,
- 0x29, 3, 0xC0, 0x2E, 0x2E,
- 0x29, 3, 0xC1, 0x02, 0x02,
- 0x29, 3, 0xC2, 0x00, 0x00,
- 0x29, 3, 0xC3, 0x2D, 0x2D,
- 0x29, 3, 0xE5, 0x34, 0x34,
- 0x29, 3, 0xC4, 0x2E, 0x2E,
- 0x29, 3, 0xC5, 0x02, 0x02,
- 0x29, 3, 0xC6, 0x00, 0x00,
- 0x29, 3, 0xC7, 0x2D, 0x2D,
- 0x29, 3, 0xC8, 0x2E, 0x2D,
- 0x29, 3, 0xC9, 0x2D, 0x14,
- 0x29, 3, 0xCA, 0x14, 0x35,
- 0x29, 3, 0xCB, 0x35, 0x10,
- 0x29, 3, 0xCC, 0x10, 0x12,
- 0x29, 3, 0xCD, 0x12, 0x2E,
- 0x29, 3, 0xCE, 0x2E, 0x13,
- 0x29, 3, 0xCF, 0x13, 0x11,
- 0x29, 3, 0xD0, 0x11, 0x36,
- 0x29, 3, 0xD1, 0x36, 0x15,
- 0x29, 3, 0xD2, 0x15, 0x2D,
- 0x29, 3, 0xD3, 0x2D, 0x2E,
- 0x29, 3, 0xD4, 0x2D, 0x2D,
- 0x29, 3, 0xD5, 0x01, 0x01,
- 0x29, 3, 0xD6, 0x03, 0x03,
- 0x29, 3, 0xD7, 0x2E, 0x2E,
- 0x29, 3, 0xE6, 0x34, 0x34,
- 0x29, 6, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x29, 6, 0xD9, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x00, 0x00,
- 0x23, 2, 0x35, 0x00,
- 0x13, 1, 0x11,
- 0xFF, 120,
- 0x13, 1, 0x29,
-
- 0xFF, 0xFF,
-};
-
-static unsigned char ext_init_off_table_TV101WXM[] = {
- 0x05, 1, 0x28, /* display off */
- 0xFF, 10, /* delay 10ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xFF, 150, /* delay 150ms */
- 0xFF, 0xFF, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_G101B158[LCD_EXTERN_INIT_ON_MAX] = {
- 0xff, 120, /* delay */
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x00,
- 0x29, 3, 0xB1,0x68,0x01,
- 0x15, 2, 0xB5,0xC8,
- 0x29, 6, 0xBD,0x02,0xB0,0x10,0x10,0x00,
-
- 0x15, 2, 0xBC,0x05,
- 0x15, 2, 0xC7,0x00,
- 0x15, 2, 0xC8,0x80,
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x01,
- 0x29, 3, 0xB3,0x2D,0x2D,
- 0x29, 3, 0xB4,0x19,0x19,
- 0x15, 2, 0xB5,0x06,
- 0x29, 3, 0xB9,0x35,0x35,
- 0x29, 3, 0xBA,0x25,0x25,
- 0x29, 3, 0xBC,0x90,0x00,
- 0x29, 3, 0xBD,0x90,0x00,
-
- 0x15, 2, 0xC0,0x0C,
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x02,
- 0x15, 2, 0xEE,0x02,
-
- 0x29, 7, 0xB0,0x00,0x00,0x00,0x32,0x00,0x64,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xB0,0x00,0x83,0x00,0x9C,0x00,0xC3,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xB0,0x00,0xDF,0x01,0x0E,
-
- 0x29, 7, 0xB1,0x01,0x33,0x01,0x6C,0x01,0x99,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xB1,0x01,0xDF,0x02,0x18,0x02,0x1A,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xB1,0x02,0x4E,0x02,0x87,
-
- 0x29, 7, 0xB2,0x02,0xAC,0x02,0xDB,0x02,0xFC,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xB2,0x03,0x24,0x03,0x46,0x03,0x71,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xB2,0x03,0x8C,0x03,0xB1,
-
- 0x29, 5, 0xB3,0x03,0xED,0x03,0Xff,
-
- 0x29, 7, 0xBC,0x00,0x00,0x00,0x32,0x00,0x64,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xBC,0x00,0x83,0x00,0x9C,0x00,0xC3,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xBC,0x00,0xDF,0x01,0x0E,
-
- 0x29, 7, 0xBD,0x01,0x33,0x01,0x6C,0x01,0x99,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xBD,0x01,0xDF,0x02,0x18,0x02,0x1A,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xBD,0x02,0x4E,0x02,0x87,
-
- 0x29, 7, 0xBE,0x02,0xAC,0x02,0xDB,0x02,0xFC,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xBE,0x03,0x24,0x03,0x46,0x03,0x71,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xBE,0x03,0x8C,0x03,0xB1,
-
- 0x29, 5, 0xBF,0x03,0xED,0x03,0xFF,
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x03,
- 0x29, 6, 0xB2,0x05,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xB6,0x05,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xB7,0x05,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xBA,0x57,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xBB,0x57,0x00,0x00,0x00,0x00,
- 0x29, 5, 0xC0,0x00,0x34,0x00,0x00,
- 0x29, 5, 0xC1,0x00,0x00,0x34,0x00,
- 0x15, 2, 0xC4,0x40,
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x04,
- 0x29, 4, 0xB1,0x03,0x02,0x05,
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x05,
- 0x29, 3, 0xB0,0x17,0x06,
- 0x29, 3, 0xB1,0x17,0x06,
- 0x29, 3, 0xB2,0x17,0x06,
- 0x29, 3, 0xB3,0x17,0x06,
- 0x29, 3, 0xB4,0x17,0x06,
- 0x15, 2, 0xBB,0x02,
- 0x29, 6, 0xBD,0x03,0x01,0x03,0x03,0x01,
- 0x15, 2, 0xC0,0x05,
-
- 0x15, 2, 0xC4,0x82,
- 0x15, 2, 0xC5,0xA2,
- 0x29, 3, 0xC8,0x03,0x30,
- 0x29, 3, 0xC9,0x03,0x31,
-
- 0x29, 4, 0xCC,0x00,0x00,0x3C,
- 0x29, 4, 0xCD,0x00,0x00,0x3C,
-
- 0x29, 6, 0xD1,0x00,0x05,0x07,0x00,0x00,
- 0x29, 6, 0xD2,0x00,0x25,0x09,0x00,0x00,
-
- 0x15, 2, 0xE5,0x06,
- 0x15, 2, 0xE6,0x06,
- 0x15, 2, 0xE7,0x06,
- 0x15, 2, 0xE8,0x06,
- 0x15, 2, 0xE9,0x06,
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x06,
- 0x29, 3, 0xB0,0x0A,0x2D,
- 0x29, 3, 0xB1,0x2D,0x08,
- 0x29, 3, 0xB2,0x2A,0x29,
- 0x29, 3, 0xB3,0x34,0x1A,
- 0x29, 3, 0xB4,0x18,0x16,
- 0x29, 3, 0xB5,0x14,0x12,
- 0x29, 3, 0xB6,0x10,0x00,
- 0x29, 3, 0xB7,0x34,0x34,
- 0x29, 3, 0xB8,0x32,0x34,
- 0x29, 3, 0xB9,0x34,0x34,
- 0x29, 3, 0xBA,0x34,0x34,
- 0x29, 3, 0xBB,0x34,0x34,
- 0x29, 3, 0xBC,0x34,0x34,
- 0x29, 3, 0xBD,0x01,0x11,
- 0x29, 3, 0xBE,0x13,0x15,
- 0x29, 3, 0xBF,0x17,0x19,
- 0x29, 3, 0xC0,0x1B,0x34,
- 0x29, 3, 0xC1,0x29,0x2A,
- 0x29, 3, 0xC2,0x09,0x2D,
- 0x29, 3, 0xC3,0x2D,0x0B,
- 0x29, 3, 0xC4,0x0B,0x2D,
- 0x29, 3, 0xC5,0x2D,0x01,
- 0x29, 3, 0xC6,0x2A,0x29,
- 0x29, 3, 0xC7,0x34,0x19,
- 0x29, 3, 0xC8,0x1B,0x11,
- 0x29, 3, 0xC9,0x13,0x15,
- 0x29, 3, 0xCA,0x17,0x09,
- 0x29, 3, 0xCB,0x34,0x34,
- 0x29, 3, 0xCC,0x34,0x34,
- 0x29, 3, 0xCD,0x34,0x34,
- 0x29, 3, 0xCE,0x34,0x34,
- 0x29, 3, 0xCF,0x34,0x34,
- 0x29, 3, 0xD0,0x34,0x34,
- 0x29, 3, 0xD1,0x08,0x16,
- 0x29, 3, 0xD2,0x14,0x12,
- 0x29, 3, 0xD3,0x10,0x1A,
- 0x29, 3, 0xD4,0x18,0x34,
- 0x29, 3, 0xD5,0x29,0x2A,
- 0x29, 3, 0xD6,0x00,0x2D,
- 0x29, 3, 0xD7,0x2D,0x0A,
-
- 0x29, 6, 0xD8,0x00,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xD9,0x00,0x00,0x00,0x00,0x00,
-
- 0x29, 3, 0xE5,0x34,0x34,
- 0x29, 3, 0xE6,0x34,0x34,
-
- 0x15, 2, 0xE7,0x00,
- 0x29, 3, 0xE8,0x34,0x34,
- 0x29, 3, 0xE9,0x34,0x34,
- 0x15, 2, 0xEA,0x00,
-
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x00,0x00,
-
- 0x23, 2, 0x35,0x00,
-
-#if 1
- 0x13, 1, 0x11,
- 0xff, 150,
- 0x13, 1, 0x29,
-#else //bist mode
- 0xff, 150,
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x00,
- 0xff, 10,
- 0x29, 5, 0xEE,0x87,0x78,0x02,0x40,
- 0xff, 10,
- 0x29, 6, 0xEF,0x00,0x07,0xFF,0xFF,0x00,
-#endif
- 0xff, 20,
- 0xFF, 0xFF, /* ending flag */
-
-};
-
-static unsigned char ext_init_off_table_G101B158[] = {
- 0x05, 1, 0x28, /* display off */
- 0xFF, 10, /* delay 10ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xFF, 150, /* delay 150ms */
- 0xFF, 0xFF, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_TV101WXM_FT[LCD_EXTERN_INIT_ON_MAX] = {
- 0xFF, 120,
- 0x23, 2, 0xE0, 0x00,
- 0x23, 2, 0xE1, 0x93,
- 0x23, 2, 0xE2, 0x65,
- 0x23, 2, 0xE3, 0xF8,
- 0x23, 2, 0x80, 0x03,
- 0x23, 2, 0xE0, 0x01,
- 0x23, 2, 0x00, 0x00,
- 0x23, 2, 0x01, 0x6F,
- 0x23, 2, 0x17, 0x00,
- 0x23, 2, 0x18, 0xAF,
- 0x23, 2, 0x19, 0x01,
- 0x23, 2, 0x1A, 0x00,
- 0x23, 2, 0x1B, 0xAF,
- 0x23, 2, 0x1C, 0x01,
- 0x23, 2, 0x1F, 0x3E,
- 0x23, 2, 0x20, 0x28,
- 0x23, 2, 0x21, 0x28,
- 0x23, 2, 0x22, 0x7E,
- 0x23, 2, 0x35, 0x26,
- 0x23, 2, 0x37, 0x09,
- 0x23, 2, 0x38, 0x04,
- 0x23, 2, 0x39, 0x00,
- 0x23, 2, 0x3A, 0x01,
- 0x23, 2, 0x3C, 0x78,
- 0x23, 2, 0x3D, 0xFF,
- 0x23, 2, 0x3E, 0xFF,
- 0x23, 2, 0x3F, 0x7F,
- 0x23, 2, 0x40, 0x06,
- 0x23, 2, 0x41, 0xA0,
- 0x23, 2, 0x42, 0x81,
- 0x23, 2, 0x43, 0x08,
- 0x23, 2, 0x44, 0x0B,
- 0x23, 2, 0x45, 0x28,
- 0x23, 2, 0x55, 0x0F,
- 0x23, 2, 0x57, 0x69,
- 0x23, 2, 0x59, 0x0A,
- 0x23, 2, 0x5A, 0x28,
- 0x23, 2, 0x5B, 0x14,
- 0x23, 2, 0x5D, 0x7F,
- 0x23, 2, 0x5E, 0x6A,
- 0x23, 2, 0x5F, 0x5A,
- 0x23, 2, 0x60, 0x4E,
- 0x23, 2, 0x61, 0x4A,
- 0x23, 2, 0x62, 0x3A,
- 0x23, 2, 0x63, 0x3C,
- 0x23, 2, 0x64, 0x23,
- 0x23, 2, 0x65, 0x39,
- 0x23, 2, 0x66, 0x35,
- 0x23, 2, 0x67, 0x34,
- 0x23, 2, 0x68, 0x51,
- 0x23, 2, 0x69, 0x3E,
- 0x23, 2, 0x6A, 0x44,
- 0x23, 2, 0x6B, 0x34,
- 0x23, 2, 0x6C, 0x2E,
- 0x23, 2, 0x6D, 0x21,
- 0x23, 2, 0x6E, 0x0E,
- 0x23, 2, 0x6F, 0x00,
- 0x23, 2, 0x70, 0x7F,
- 0x23, 2, 0x71, 0x6A,
- 0x23, 2, 0x72, 0x5A,
- 0x23, 2, 0x73, 0x4E,
- 0x23, 2, 0x74, 0x4A,
- 0x23, 2, 0x75, 0x3A,
- 0x23, 2, 0x76, 0x3C,
- 0x23, 2, 0x77, 0x23,
- 0x23, 2, 0x78, 0x39,
- 0x23, 2, 0x79, 0x35,
- 0x23, 2, 0x7A, 0x34,
- 0x23, 2, 0x7B, 0x51,
- 0x23, 2, 0x7C, 0x3E,
- 0x23, 2, 0x7D, 0x44,
- 0x23, 2, 0x7E, 0x34,
- 0x23, 2, 0x7F, 0x2E,
- 0x23, 2, 0x80, 0x21,
- 0x23, 2, 0x81, 0x0E,
- 0x23, 2, 0x82, 0x00,
- 0x23, 2, 0xE0, 0x02,
- 0x23, 2, 0x00, 0x1E,
- 0x23, 2, 0x01, 0x1E,
- 0x23, 2, 0x02, 0x41,
- 0x23, 2, 0x03, 0x41,
- 0x23, 2, 0x04, 0x43,
- 0x23, 2, 0x05, 0x43,
- 0x23, 2, 0x06, 0x1F,
- 0x23, 2, 0x07, 0x1F,
- 0x23, 2, 0x08, 0x35,
- 0x23, 2, 0x09, 0x1F,
- 0x23, 2, 0x0A, 0x15,
- 0x23, 2, 0x0B, 0x15,
- 0x23, 2, 0x0C, 0x1F,
- 0x23, 2, 0x0D, 0x47,
- 0x23, 2, 0x0E, 0x47,
- 0x23, 2, 0x0F, 0x45,
- 0x23, 2, 0x10, 0x45,
- 0x23, 2, 0x11, 0x4B,
- 0x23, 2, 0x12, 0x4B,
- 0x23, 2, 0x13, 0x49,
- 0x23, 2, 0x14, 0x49,
- 0x23, 2, 0x15, 0x1F,
- 0x23, 2, 0x16, 0x1E,
- 0x23, 2, 0x17, 0x1E,
- 0x23, 2, 0x18, 0x40,
- 0x23, 2, 0x19, 0x40,
- 0x23, 2, 0x1A, 0x42,
- 0x23, 2, 0x1B, 0x42,
- 0x23, 2, 0x1C, 0x1F,
- 0x23, 2, 0x1D, 0x1F,
- 0x23, 2, 0x1E, 0x35,
- 0x23, 2, 0x1F, 0x1F,
- 0x23, 2, 0x20, 0x15,
- 0x23, 2, 0x21, 0x15,
- 0x23, 2, 0x22, 0x1F,
- 0x23, 2, 0x23, 0x46,
- 0x23, 2, 0x24, 0x46,
- 0x23, 2, 0x25, 0x44,
- 0x23, 2, 0x26, 0x44,
- 0x23, 2, 0x27, 0x4A,
- 0x23, 2, 0x28, 0x4A,
- 0x23, 2, 0x29, 0x48,
- 0x23, 2, 0x2A, 0x48,
- 0x23, 2, 0x2B, 0x1F,
- 0x23, 2, 0x58, 0x40,
- 0x23, 2, 0x5B, 0x30,
- 0x23, 2, 0x5C, 0x0F,
- 0x23, 2, 0x5D, 0x30,
- 0x23, 2, 0x5E, 0x01,
- 0x23, 2, 0x5F, 0x02,
- 0x23, 2, 0x63, 0x14,
- 0x23, 2, 0x64, 0x6A,
- 0x23, 2, 0x67, 0x73,
- 0x23, 2, 0x68, 0x11,
- 0x23, 2, 0x69, 0x14,
- 0x23, 2, 0x6A, 0x6A,
- 0x23, 2, 0x6B, 0x08,
- 0x23, 2, 0x6C, 0x00,
- 0x23, 2, 0x6D, 0x00,
- 0x23, 2, 0x6E, 0x00,
- 0x23, 2, 0x6F, 0x88,
- 0x23, 2, 0x77, 0xDD,
- 0x23, 2, 0x79, 0x0E,
- 0x23, 2, 0x7A, 0x0F,
- 0x23, 2, 0x7D, 0x14,
- 0x23, 2, 0x7E, 0x82,
- 0x23, 2, 0xE0, 0x04,
- 0x23, 2, 0x09, 0x11,
- 0x23, 2, 0x0E, 0x48,
- 0x23, 2, 0x2B, 0x2B,
- 0x23, 2, 0x2D, 0x03,
- 0x23, 2, 0x2E, 0x44,
- 0x23, 2, 0xE0, 0x00,
- 0x23, 2, 0xE6, 0x02,
- 0x23, 2, 0xE7, 0x0C,
- 0x05, 1, 0x11,
- 0xFF, 100,
- 0x23, 2, 0xE0, 0x03,
- 0x23, 2, 0x2B, 0x01,
- 0x23, 2, 0x2C, 0x00,
- 0x23, 2, 0x30, 0x03,
- 0x23, 2, 0x31, 0xFC,
- 0x23, 2, 0x32, 0x03,
- 0x23, 2, 0x33, 0xF8,
- 0x23, 2, 0x34, 0x03,
- 0x23, 2, 0x35, 0xF0,
- 0x23, 2, 0x36, 0x03,
- 0x23, 2, 0x37, 0xE8,
- 0x23, 2, 0x38, 0x03,
- 0x23, 2, 0x39, 0xE0,
- 0x23, 2, 0x3A, 0x03,
- 0x23, 2, 0x3B, 0xD0,
- 0x23, 2, 0x3C, 0x03,
- 0x23, 2, 0x3D, 0xC0,
- 0x23, 2, 0x3E, 0x03,
- 0x23, 2, 0x3F, 0xA0,
- 0x23, 2, 0x40, 0x03,
- 0x23, 2, 0x41, 0x80,
- 0x23, 2, 0x42, 0x03,
- 0x23, 2, 0x43, 0x40,
- 0x23, 2, 0x44, 0x03,
- 0x23, 2, 0x45, 0x00,
- 0x23, 2, 0x46, 0x02,
- 0x23, 2, 0x47, 0x80,
- 0x23, 2, 0x48, 0x02,
- 0x23, 2, 0x49, 0x00,
- 0x23, 2, 0x4A, 0x01,
- 0x23, 2, 0x4B, 0xFC,
- 0x23, 2, 0x4C, 0x01,
- 0x23, 2, 0x4D, 0x7C,
- 0x23, 2, 0x4E, 0x00,
- 0x23, 2, 0x4F, 0xFC,
- 0x23, 2, 0x50, 0x00,
- 0x23, 2, 0x51, 0xBC,
- 0x23, 2, 0x52, 0x00,
- 0x23, 2, 0x53, 0x7C,
- 0x23, 2, 0x54, 0x00,
- 0x23, 2, 0x55, 0x5C,
- 0x23, 2, 0x56, 0x00,
- 0x23, 2, 0x57, 0x3C,
- 0x23, 2, 0x58, 0x00,
- 0x23, 2, 0x59, 0x2C,
- 0x23, 2, 0x5A, 0x00,
- 0x23, 2, 0x5B, 0x1C,
- 0x23, 2, 0x5C, 0x00,
- 0x23, 2, 0x5D, 0x14,
- 0x23, 2, 0x5E, 0x00,
- 0x23, 2, 0x5F, 0x0C,
- 0x23, 2, 0x60, 0x00,
- 0x23, 2, 0x61, 0x04,
- 0x23, 2, 0x62, 0x00,
- 0x23, 2, 0x63, 0x00,
- 0x23, 2, 0x64, 0x03,
- 0x23, 2, 0x65, 0xC9,
- 0x23, 2, 0x66, 0x03,
- 0x23, 2, 0x67, 0xC6,
- 0x23, 2, 0x68, 0x03,
- 0x23, 2, 0x69, 0xBE,
- 0x23, 2, 0x6A, 0x03,
- 0x23, 2, 0x6B, 0xB7,
- 0x23, 2, 0x6C, 0x03,
- 0x23, 2, 0x6D, 0xB1,
- 0x23, 2, 0x6E, 0x03,
- 0x23, 2, 0x6F, 0xA3,
- 0x23, 2, 0x70, 0x03,
- 0x23, 2, 0x71, 0x96,
- 0x23, 2, 0x72, 0x03,
- 0x23, 2, 0x73, 0x79,
- 0x23, 2, 0x74, 0x03,
- 0x23, 2, 0x75, 0x5D,
- 0x23, 2, 0x76, 0x03,
- 0x23, 2, 0x77, 0x26,
- 0x23, 2, 0x78, 0x02,
- 0x23, 2, 0x79, 0xE9,
- 0x23, 2, 0x7A, 0x02,
- 0x23, 2, 0x7B, 0x6E,
- 0x23, 2, 0x7C, 0x01,
- 0x23, 2, 0x7D, 0xF3,
- 0x23, 2, 0x7E, 0x01,
- 0x23, 2, 0x7F, 0xEF,
- 0x23, 2, 0x80, 0x01,
- 0x23, 2, 0x81, 0x73,
- 0x23, 2, 0x82, 0x00,
- 0x23, 2, 0x83, 0xF5,
- 0x23, 2, 0x84, 0x00,
- 0x23, 2, 0x85, 0xB4,
- 0x23, 2, 0x86, 0x00,
- 0x23, 2, 0x87, 0x79,
- 0x23, 2, 0x88, 0x00,
- 0x23, 2, 0x89, 0x5D,
- 0x23, 2, 0x8A, 0x00,
- 0x23, 2, 0x8B, 0x3C,
- 0x23, 2, 0x8C, 0x00,
- 0x23, 2, 0x8D, 0x2B,
- 0x23, 2, 0x8E, 0x00,
- 0x23, 2, 0x8F, 0x1C,
- 0x23, 2, 0x90, 0x00,
- 0x23, 2, 0x91, 0x14,
- 0x23, 2, 0x92, 0x00,
- 0x23, 2, 0x93, 0x0C,
- 0x23, 2, 0x94, 0x00,
- 0x23, 2, 0x95, 0x04,
- 0x23, 2, 0x96, 0x00,
- 0x23, 2, 0x97, 0x00,
- 0x23, 2, 0xE0, 0x00,
- 0x05, 1, 0x29,
- 0xFF, 0xFF,
-};
-static unsigned char ext_init_off_table_TV101WXM_FT[LCD_EXTERN_INIT_OFF_MAX] = {
- 0XFF, 5, /* delay 5ms */
- 0x05, 1, 0x28, /* display off */
- 0xFF, 50, /* delay 50ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xFF, 150, /* delay 150ms */
- 0xFF, 0xFF, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_G101B158_FT[LCD_EXTERN_INIT_ON_MAX] = {
- 0x23, 2, 0xE0, 0x00,
- 0x23, 2, 0xE1, 0x93,
- 0x23, 2, 0xE2, 0x65,
- 0x23, 2, 0xE3, 0xF8,
- 0x23, 2, 0x80, 0x03,
-
- 0x23, 2, 0xE0, 0x01,
- 0x23, 2, 0x00, 0x00,
- 0x23, 2, 0x01, 0x5D,
- 0x23, 2, 0x03, 0x00,
- 0x23, 2, 0x04, 0x64,
-
- 0x23, 2, 0x17, 0x00,
- 0x23, 2, 0x18, 0xC7,//BF=4.5V,c7=4.6v, D7=4.8V
- 0x23, 2, 0x19, 0x01,//0.3V
- 0x23, 2, 0x1A, 0x00,
- 0x23, 2, 0x1B, 0xC7,
- 0x23, 2, 0x1C, 0x01,
-
- 0x23, 2, 0x1F, 0x70, //VGH_REG=16.2V
- 0x23, 2, 0x20, 0x2D, //VGL_REG=-12V
- 0x23, 2, 0x21, 0x2D, //VGL_REG2=-12V
- 0x23, 2, 0x22, 0x7E,
-
- 0x23, 2, 0x35, 0x28, //SAP
-
- 0x23, 2, 0x37, 0x19, //SS=1,BGR=1
-
- 0x23, 2, 0x38, 0x05, //JDT=101 zigzag inversion
- 0x23, 2, 0x39, 0x00,
- 0x23, 2, 0x3A, 0x01,
- 0x23, 2, 0x3C, 0x7C, //SET EQ3 for TE_H
- 0x23, 2, 0x3D, 0xFF, //SET CHGEN_ON, modify 20140806
- 0x23, 2, 0x3E, 0xFF, //SET CHGEN_OFF, modify 20140806
- 0x23, 2, 0x3F, 0x7F, //SET CHGEN_OFF2, modify 20140806
-
-
- 0x23, 2, 0x40, 0x06, //RSO=
- 0x23, 2, 0x41, 0xA0, //LN=640->1280 line
- 0x23, 2, 0x43, 0x14, //VFP=20
- 0x23, 2, 0x44, 0x17, //VBP=24
- 0x23, 2, 0x45, 0x2C, //HBP=44
-
- 0x23, 2, 0x55, 0x0F, //DCDCM=1111
- 0x23, 2, 0x57, 0x68,
- 0x23, 2, 0x59, 0x0A, //VCL = -2.5V
- 0x23, 2, 0x5A, 0x2E, //VGH = 16.2V
- 0x23, 2, 0x5B, 0x1A, //VGL = -12V
- 0x23, 2, 0x5C, 0x15, //pump clk
-
-
- 0x23, 2, 0x5D, 0x7F,
- 0x23, 2, 0x5E, 0x61,
- 0x23, 2, 0x5F, 0x50,
- 0x23, 2, 0x60, 0x43,
- 0x23, 2, 0x61, 0x3E,
- 0x23, 2, 0x62, 0x2E,
- 0x23, 2, 0x63, 0x33,
- 0x23, 2, 0x64, 0x1C,
- 0x23, 2, 0x65, 0x34,
- 0x23, 2, 0x66, 0x33,
- 0x23, 2, 0x67, 0x32,
- 0x23, 2, 0x68, 0x50,
- 0x23, 2, 0x69, 0x3E,
- 0x23, 2, 0x6A, 0x46,
- 0x23, 2, 0x6B, 0x37,
- 0x23, 2, 0x6C, 0x32,
- 0x23, 2, 0x6D, 0x24,
- 0x23, 2, 0x6E, 0x12,
- 0x23, 2, 0x6F, 0x02,
- 0x23, 2, 0x70, 0x7F,
- 0x23, 2, 0x71, 0x61,
- 0x23, 2, 0x72, 0x50,
- 0x23, 2, 0x73, 0x43,
- 0x23, 2, 0x74, 0x3E,
- 0x23, 2, 0x75, 0x2E,
- 0x23, 2, 0x76, 0x33,
- 0x23, 2, 0x77, 0x1C,
- 0x23, 2, 0x78, 0x34,
- 0x23, 2, 0x79, 0x33,
- 0x23, 2, 0x7A, 0x32,
- 0x23, 2, 0x7B, 0x50,
- 0x23, 2, 0x7C, 0x3E,
- 0x23, 2, 0x7D, 0x46,
- 0x23, 2, 0x7E, 0x37,
- 0x23, 2, 0x7F, 0x32,
- 0x23, 2, 0x80, 0x24,
- 0x23, 2, 0x81, 0x12,
- 0x23, 2, 0x82, 0x02,
-
-
- 0x23, 2, 0xE0, 0x02,
-
- 0x23, 2, 0x00, 0x52,//RESET_EVEN
- 0x23, 2, 0x01, 0x55,//VSSG_EVEN
- 0x23, 2, 0x02, 0x55,//VSSG_EVEN
- 0x23, 2, 0x03, 0x50,//STV2_ODD
- 0x23, 2, 0x04, 0x77,//VDD2_ODD
- 0x23, 2, 0x05, 0x57,//VDD1_ODD
- 0x23, 2, 0x06, 0x55,//x
- 0x23, 2, 0x07, 0x4E,//CK11
- 0x23, 2, 0x08, 0x4C,//CK9
- 0x23, 2, 0x09, 0x5F,//x
- 0x23, 2, 0x0A, 0x4A,//CK7
- 0x23, 2, 0x0B, 0x48,//CK5
- 0x23, 2, 0x0C, 0x55,//x
- 0x23, 2, 0x0D, 0x46,//CK3
- 0x23, 2, 0x0E, 0x44,//CK1
- 0x23, 2, 0x0F, 0x40,//STV1_ODD
- 0x23, 2, 0x10, 0x55,//x
- 0x23, 2, 0x11, 0x55,//x
- 0x23, 2, 0x12, 0x55,//x
- 0x23, 2, 0x13, 0x55,//x
- 0x23, 2, 0x14, 0x55,//x
- 0x23, 2, 0x15, 0x55,//x
-
- 0x23, 2, 0x16, 0x53,//RESET__EVEN
- 0x23, 2, 0x17, 0x55,//VSSG_EVEN
- 0x23, 2, 0x18, 0x55,//VSSG_EVEN
- 0x23, 2, 0x19, 0x51,//STV2_EVEN
- 0x23, 2, 0x1A, 0x77,//VDD2_EVEN
- 0x23, 2, 0x1B, 0x57,//VDD1_EVEN
- 0x23, 2, 0x1C, 0x55,//x
- 0x23, 2, 0x1D, 0x4F,//CK12
- 0x23, 2, 0x1E, 0x4D,//CK10
- 0x23, 2, 0x1F, 0x5F,//x
- 0x23, 2, 0x20, 0x4B,//CK8
- 0x23, 2, 0x21, 0x49,//CK6
- 0x23, 2, 0x22, 0x55,//x
- 0x23, 2, 0x23, 0x47,//CK4
- 0x23, 2, 0x24, 0x45,//CK2
- 0x23, 2, 0x25, 0x41,//STV1_EVEN
- 0x23, 2, 0x26, 0x55,//x
- 0x23, 2, 0x27, 0x55,//x
- 0x23, 2, 0x28, 0x55,//x
- 0x23, 2, 0x29, 0x55,//x
- 0x23, 2, 0x2A, 0x55,//x
- 0x23, 2, 0x2B, 0x55,//x
-
- 0x23, 2, 0x2C, 0x13,//RESET_EVEN
- 0x23, 2, 0x2D, 0x15,//VSSG_EVEN
- 0x23, 2, 0x2E, 0x15,//VSSG_EVEN
- 0x23, 2, 0x2F, 0x01,//STV2_ODD
- 0x23, 2, 0x30, 0x37,//VDD2_ODD
- 0x23, 2, 0x31, 0x17,//VDD1_ODD
- 0x23, 2, 0x32, 0x15,//x
- 0x23, 2, 0x33, 0x0D,//CK11
- 0x23, 2, 0x34, 0x0F,//CK9
- 0x23, 2, 0x35, 0x15,//x
- 0x23, 2, 0x36, 0x05,//CK7
- 0x23, 2, 0x37, 0x07,//CK5
- 0x23, 2, 0x38, 0x15,//x
- 0x23, 2, 0x39, 0x09,//CK3
- 0x23, 2, 0x3A, 0x0B,//CK1
- 0x23, 2, 0x3B, 0x11,//STV1_ODD
- 0x23, 2, 0x3C, 0x15,//x
- 0x23, 2, 0x3D, 0x15,//x
- 0x23, 2, 0x3E, 0x15,//x
- 0x23, 2, 0x3F, 0x15,//x
- 0x23, 2, 0x40, 0x15,//x
- 0x23, 2, 0x41, 0x15,//x
-
- 0x23, 2, 0x42, 0x12,//RESET__EVEN
- 0x23, 2, 0x43, 0x15,//VSSG_EVEN
- 0x23, 2, 0x44, 0x15,//VSSG_EVEN
- 0x23, 2, 0x45, 0x00,//STV2_EVEN
- 0x23, 2, 0x46, 0x37,//VDD2_EVEN
- 0x23, 2, 0x47, 0x17,//VDD1_EVEN
- 0x23, 2, 0x48, 0x15,//x
- 0x23, 2, 0x49, 0x0C,//CK12
- 0x23, 2, 0x4A, 0x0E,//CK10
- 0x23, 2, 0x4B, 0x15,//x
- 0x23, 2, 0x4C, 0x04,//CK8
- 0x23, 2, 0x4D, 0x06,//CK6
- 0x23, 2, 0x4E, 0x15,//x
- 0x23, 2, 0x4F, 0x08,//CK4
- 0x23, 2, 0x50, 0x0A,//CK2
- 0x23, 2, 0x51, 0x10,//STV1_EVEN
- 0x23, 2, 0x52, 0x15,//x
- 0x23, 2, 0x53, 0x15,//x
- 0x23, 2, 0x54, 0x15,//x
- 0x23, 2, 0x55, 0x15,//x
- 0x23, 2, 0x56, 0x15,//x
- 0x23, 2, 0x57, 0x15,//x
-
- 0x23, 2, 0x58, 0x40,
- 0x23, 2, 0x5B, 0x10,
- 0x23, 2, 0x5C, 0x12,//STV_S0
- 0x23, 2, 0x5D, 0x40,
- 0x23, 2, 0x5E, 0x00,
- 0x23, 2, 0x5F, 0x00,
- 0x23, 2, 0x60, 0x40,//ETV_W
- 0x23, 2, 0x61, 0x03,
- 0x23, 2, 0x62, 0x04,
- 0x23, 2, 0x63, 0x6C,//CKV_ON
- 0x23, 2, 0x64, 0x6C,//CKV_OFF
- 0x23, 2, 0x65, 0x75,
- 0x23, 2, 0x66, 0x14,//ETV_S0
- 0x23, 2, 0x67, 0xB4, //ckv_num/ckv_w
- 0x23, 2, 0x68, 0x14, //CKV_S0
- 0x23, 2, 0x69, 0x6C,//CKV_ON
- 0x23, 2, 0x6A, 0x6C,//CKV_OFF
- 0x23, 2, 0x6B, 0x0C, //dummy
- 0x23, 2, 0x6D, 0x04,//GGND1
- 0x23, 2, 0x6E, 0x00,//GGND2
- 0x23, 2, 0x6F, 0x88,
- 0x23, 2, 0x75, 0xBB,//FLM_EN
- 0x23, 2, 0x76, 0x02,
- 0x23, 2, 0x77, 0x00,
- 0x23, 2, 0x78, 0x02,//FLM_OFF
-
- 0x23, 2, 0xE0, 0x03,
- 0x23, 2, 0xAF, 0x20,//Adjust CABC
-
-
- 0x23, 2, 0xE0, 0x04,
- 0x23, 2, 0x09, 0x11,
- 0x23, 2, 0x0E, 0x48, //Source EQ option
- 0x23, 2, 0x2B, 0x2B,
- 0x23, 2, 0x2D, 0x03,//defult 0x01
- 0x23, 2, 0x2E, 0x44,
- 0x23, 2, 0x41, 0xFF,//Adjust CABC
-
- 0x23, 2, 0xE0, 0x05,
- 0x23, 2, 0x12, 0x72,//VCI GAS detect voltage
-
- 0x23, 2, 0xE0, 0x00,
- 0x23, 2, 0xE6, 0x02,//WD_Timer
- 0x23, 2, 0xE7, 0x0C,//WD_Timer
-
- 0x23, 2, 0x53, 0x2C,//CABC dimming
-
- 0x05, 1, 0x11, // SLPOUT
- 0xff, 120,
-
- 0x23, 2, 0xE0, 0x03,
- 0x23, 2, 0x2B, 0x01,//DGC_EN
- 0xff, 10,
- 0x23, 2, 0x2C, 0x01,//DGC_SEL
-
- 0x23, 2, 0x30, 0x03,
- 0x23, 2, 0x31, 0xDE,
- 0x23, 2, 0x32, 0x03,
- 0x23, 2, 0x33, 0xDA,
- 0x23, 2, 0x34, 0x03,
- 0x23, 2, 0x35, 0xD1,
- 0x23, 2, 0x36, 0x03,
- 0x23, 2, 0x37, 0xC9,
- 0x23, 2, 0x38, 0x03,
- 0x23, 2, 0x39, 0xC1,
- 0x23, 2, 0x3A, 0x03,
- 0x23, 2, 0x3B, 0xB3,
- 0x23, 2, 0x3C, 0x03,
- 0x23, 2, 0x3D, 0xA4,
- 0x23, 2, 0x3E, 0x03,
- 0x23, 2, 0x3F, 0x83,
- 0x23, 2, 0x40, 0x03,
- 0x23, 2, 0x41, 0x62,
- 0x23, 2, 0x42, 0x03,
- 0x23, 2, 0x43, 0x23,
- 0x23, 2, 0x44, 0x02,
- 0x23, 2, 0x45, 0xE4,
- 0x23, 2, 0x46, 0x02,
- 0x23, 2, 0x47, 0x67,
- 0x23, 2, 0x48, 0x01,
- 0x23, 2, 0x49, 0xEC,
- 0x23, 2, 0x4A, 0x01,
- 0x23, 2, 0x4B, 0xE8,
- 0x23, 2, 0x4C, 0x01,
- 0x23, 2, 0x4D, 0x6D,
- 0x23, 2, 0x4E, 0x00,
- 0x23, 2, 0x4F, 0xF2,
- 0x23, 2, 0x50, 0x00,
- 0x23, 2, 0x51, 0xB2,
- 0x23, 2, 0x52, 0x00,
- 0x23, 2, 0x53, 0x76,
- 0x23, 2, 0x54, 0x00,
- 0x23, 2, 0x55, 0x58,
- 0x23, 2, 0x56, 0x00,
- 0x23, 2, 0x57, 0x39,
- 0x23, 2, 0x58, 0x00,
- 0x23, 2, 0x59, 0x2A,
- 0x23, 2, 0x5A, 0x00,
- 0x23, 2, 0x5B, 0x1B,
- 0x23, 2, 0x5C, 0x00,
- 0x23, 2, 0x5D, 0x13,
- 0x23, 2, 0x5E, 0x00,
- 0x23, 2, 0x5F, 0x0B,
- 0x23, 2, 0x60, 0x00,
- 0x23, 2, 0x61, 0x04,
- 0x23, 2, 0x62, 0x00,
- 0x23, 2, 0x63, 0x00,
-
- 0x23, 2, 0x64, 0x03,
- 0x23, 2, 0x65, 0xE7,
- 0x23, 2, 0x66, 0x03,
- 0x23, 2, 0x67, 0xE4,
- 0x23, 2, 0x68, 0x03,
- 0x23, 2, 0x69, 0xDD,
- 0x23, 2, 0x6A, 0x03,
- 0x23, 2, 0x6B, 0xD5,
- 0x23, 2, 0x6C, 0x03,
- 0x23, 2, 0x6D, 0xCE,
- 0x23, 2, 0x6E, 0x03,
- 0x23, 2, 0x6F, 0xBF,
- 0x23, 2, 0x70, 0x03,
- 0x23, 2, 0x71, 0xB2,
- 0x23, 2, 0x72, 0x03,
- 0x23, 2, 0x73, 0x93,
- 0x23, 2, 0x74, 0x03,
- 0x23, 2, 0x75, 0x71,
- 0x23, 2, 0x76, 0x03,
- 0x23, 2, 0x77, 0x33,
- 0x23, 2, 0x78, 0x02,
- 0x23, 2, 0x79, 0xF4,
- 0x23, 2, 0x7A, 0x02,
- 0x23, 2, 0x7B, 0x75,
- 0x23, 2, 0x7C, 0x01,
- 0x23, 2, 0x7D, 0xF7,
- 0x23, 2, 0x7E, 0x01,
- 0x23, 2, 0x7F, 0xF3,
- 0x23, 2, 0x80, 0x01,
- 0x23, 2, 0x81, 0x75,
- 0x23, 2, 0x82, 0x00,
- 0x23, 2, 0x83, 0xF7,
- 0x23, 2, 0x84, 0x00,
- 0x23, 2, 0x85, 0xB6,
- 0x23, 2, 0x86, 0x00,
- 0x23, 2, 0x87, 0x7C,
- 0x23, 2, 0x88, 0x00,
- 0x23, 2, 0x89, 0x5E,
- 0x23, 2, 0x8A, 0x00,
- 0x23, 2, 0x8B, 0x3F,
- 0x23, 2, 0x8C, 0x00,
- 0x23, 2, 0x8D, 0x2E,
- 0x23, 2, 0x8E, 0x00,
- 0x23, 2, 0x8F, 0x1D,
- 0x23, 2, 0x90, 0x00,
- 0x23, 2, 0x91, 0x15,
- 0x23, 2, 0x92, 0x00,
- 0x23, 2, 0x93, 0x0C,
- 0x23, 2, 0x94, 0x00,
- 0x23, 2, 0x95, 0x04,
- 0x23, 2, 0x96, 0x00,
- 0x23, 2, 0x97, 0x00,
-
- 0x23, 2, 0xE0, 0x00,
-
- 0x05, 1, 0x29, // DSPON
- 0xff, 5,
- 0xff, 0xff,
-};
-
-static unsigned char ext_init_off_table_G101B158_FT[LCD_EXTERN_INIT_OFF_MAX] = {
- 0XFF, 5, /* delay 5ms */
- 0x05, 1, 0x28, /* display off */
- 0xFF, 50, /* delay 50ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xFF, 150, /* delay 150ms */
- 0xFF, 0xFF, /* ending flag */
-};
-
-static struct lcd_extern_config_s ext_config[LCD_EXTERN_NUM_MAX] = {
- {
- .index = 0,
- .name = "ext_default",
- .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 0, /* 0=disable, 1=enable */
- .i2c_addr = 0x1c, /* 7bit i2c address */
- .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for invalid */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- { /* P070ACB_FT */
- .index = 1,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_P070ACB_FT,
- .table_init_on_cnt = sizeof(ext_init_on_table_P070ACB_FT),
- .table_init_off = ext_init_off_table_P070ACB_FT,
- .table_init_off_cnt = sizeof(ext_init_off_table_P070ACB_FT),
- },
- { /* TL050FHV02CT */
- .index = 2,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_TL050FHV02CT,
- .table_init_on_cnt = sizeof(ext_init_on_table_TL050FHV02CT),
- .table_init_off = ext_init_off_table_TL050FHV02CT,
- .table_init_off_cnt = sizeof(ext_init_off_table_TL050FHV02CT),
- },
- { /* boe_nvtk_10 */
- .index = 3,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_TV101WXM,
- .table_init_on_cnt = sizeof(ext_init_on_table_TV101WXM),
- .table_init_off = ext_init_off_table_TV101WXM,
- .table_init_off_cnt = sizeof(ext_init_off_table_TV101WXM),
- },
- { /* inx_nvtk_10 */
- .index = 4,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_G101B158,
- .table_init_on_cnt = sizeof(ext_init_on_table_G101B158),
- .table_init_off = ext_init_off_table_G101B158,
- .table_init_off_cnt = sizeof(ext_init_off_table_G101B158),
- },
- { /* boe_fiti_10 */
- .index = 5,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_TV101WXM_FT,
- .table_init_on_cnt = sizeof(ext_init_on_table_TV101WXM_FT),
- .table_init_off = ext_init_off_table_TV101WXM_FT,
- .table_init_off_cnt = sizeof(ext_init_off_table_TV101WXM_FT),
- },
- { /* inx_fiti_10 */
- .index = 6,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_G101B158_FT,
- .table_init_on_cnt = sizeof(ext_init_on_table_G101B158_FT),
- .table_init_off = ext_init_off_table_G101B158_FT,
- .table_init_off_cnt = sizeof(ext_init_off_table_G101B158_FT),
- },
- {
- .index = LCD_EXTERN_INDEX_INVALID,
- },
-};
-
-#endif
-
diff --git a/board/amlogic/g12b_newman_px/zircon.c b/board/amlogic/g12b_newman_px/zircon.c
deleted file mode 100644
index 3491ad8..0000000
--- a/board/amlogic/g12b_newman_px/zircon.c
+++ /dev/null
@@ -1,198 +0,0 @@
-/*
- * Copyright (c) 2018 The Fuchsia Authors
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common.h>
-#include <fs.h>
-#include <version.h>
-#include <zircon/zircon.h>
-
-#define PDEV_VID_GOOGLE 3
-#define PDEV_PID_SHERLOCK 5
-
-#define NVRAM_LENGTH (8 * 1024)
-
-static const zbi_cpu_config_t cpu_config = {
- .cluster_count = 1,
- .clusters = {
- {
- .cpu_count = 4,
- },
- },
-};
-
-static const zbi_mem_range_t mem_config[] = {
- {
- .type = ZBI_MEM_RANGE_RAM,
- .length = 0x60000000, // 1.5 GB
- },
- {
- .type = ZBI_MEM_RANGE_PERIPHERAL,
- .paddr = 0xf5800000,
- .length = 0x0a800000,
- },
- /* secmon_reserved:linux,secmon */
- {
- .type = ZBI_MEM_RANGE_RESERVED,
- .paddr = 0x05000000,
- .length = 0x2400000,
- },
- /* logo_reserved:linux,meson-fb */
- {
- .type = ZBI_MEM_RANGE_RESERVED,
- .paddr = 0x5f800000,
- .length = 0x800000,
- },
-};
-
-static const dcfg_simple_t uart_driver = {
- .mmio_phys = 0xff803000,
- .irq = 225,
-};
-
-static const dcfg_arm_gicv2_driver_t gicv2_driver = {
- .mmio_phys = 0xffc00000,
- .gicd_offset = 0x1000,
- .gicc_offset = 0x2000,
- .gich_offset = 0x4000,
- .gicv_offset = 0x6000,
- .ipi_base = 5,
-};
-
-static const dcfg_arm_psci_driver_t psci_driver = {
- .use_hvc = false,
- .reboot_args = { 1, 0, 0 },
- .reboot_bootloader_args = { 4, 0, 0 },
- .reboot_recovery_args = { 2, 0, 0 },
-};
-
-static const dcfg_arm_generic_timer_driver_t timer_driver = {
- .irq_phys = 30,
-};
-
-static const zbi_platform_id_t platform_id = {
- .vid = PDEV_VID_GOOGLE,
- .pid = PDEV_PID_SHERLOCK,
- .board_name = "sherlock",
-};
-
-#define NEWMAN_FACTORY_IF "mmc"
-#define NEWMAN_FACTORY_PART "1:5"
-#define FACTORY_MAC_ADDR_BUFF_LEN 30
-#define NEWMAN_FACTORY_MACADDR_FILE "mac_addr"
-#define FACTORY_MAC_ADDR_FILE_LEN 25
-
-static int add_mac_addresses(zbi_header_t* zbi) {
- char buffer[FACTORY_MAC_ADDR_BUFF_LEN];
- u64 fullmac[2];
- u8 mac_addr[6];
- int len_read;
- int mac_num, i;
-
- if (fs_set_blk_dev(NEWMAN_FACTORY_IF, NEWMAN_FACTORY_PART,
- FS_TYPE_EXT)) {
- printf("set_blk_dev %s-%s failed.\n",
- NEWMAN_FACTORY_IF, NEWMAN_FACTORY_PART);
- return -1;
- }
-
- if (fs_read(NEWMAN_FACTORY_MACADDR_FILE, buffer, 0,
- FACTORY_MAC_ADDR_BUFF_LEN, &len_read)) {
- printf("Failed to read Mac Addresses from Factory partition\n");
- }
- if (len_read != FACTORY_MAC_ADDR_FILE_LEN) {
- printf("Factory MAC Addr File length (%d) incorrect.\n",
- len_read);
- return -1;
- }
-
- buffer[len_read] = '\0';
-
- /*
- * "buffer" should now contain two hex strings separated by \n,
- * for a total of 25 bytes. Separate into 2 C strings and convert.
- */
- buffer[len_read/2] = '\0';
- fullmac[0] = simple_strtoull(buffer, NULL, 16);
- fullmac[1] = simple_strtoull(&buffer[(len_read/2)+1], NULL, 16);
-
- for (mac_num = 0; mac_num < ARRAY_SIZE(fullmac); mac_num++) {
- for (i = ARRAY_SIZE(mac_addr)-1; i >= 0; i--) {
- mac_addr[i] = (u8) (fullmac[mac_num] & 0xff);
- fullmac[mac_num] >>= 8;
- }
- zircon_append_boot_item(zbi, ZBI_TYPE_DRV_MAC_ADDRESS, mac_num,
- mac_addr, sizeof(mac_addr));
- }
-
- return 0;
-}
-
-int zircon_preboot(zbi_header_t *zbi)
-{
- /* add CPU configuration */
- zircon_append_boot_item(zbi, ZBI_TYPE_CPU_CONFIG, 0, &cpu_config,
- sizeof(zbi_cpu_config_t) +
- sizeof(zbi_cpu_cluster_t) *
- cpu_config.cluster_count);
-
- /*
- * allocate crashlog save area before 0x5f800000-0x60000000
- * reserved area
- */
- zbi_nvram_t nvram;
-
- nvram.base = 0x5f800000 - NVRAM_LENGTH;
- nvram.length = NVRAM_LENGTH;
- zircon_append_boot_item(zbi, ZBI_TYPE_NVRAM, 0, &nvram, sizeof(nvram));
-
- /* add memory configuration */
- zircon_append_boot_item(zbi, ZBI_TYPE_MEM_CONFIG, 0, &mem_config,
- sizeof(mem_config));
-
- /* add kernel drivers */
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_AMLOGIC_UART,
- &uart_driver, sizeof(uart_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_GIC_V2,
- &gicv2_driver, sizeof(gicv2_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_PSCI,
- &psci_driver, sizeof(psci_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER,
- KDRV_ARM_GENERIC_TIMER,
- &timer_driver, sizeof(timer_driver));
-
- const char* bootloader_type = "bootloader-type=U-Boot";
- zircon_append_boot_item(zbi, ZBI_TYPE_CMDLINE, 0,
- bootloader_type,
- strlen(bootloader_type)+1);
-
- char uboot_ver[] = "bootloader.name=" U_BOOT_VERSION_STRING;
- // Zircon's cmdline parameters cannot contain spaces so
- // convert spaces in autogenerated U-boot version string
- // to underscores.
- // See zircon/docs/kernel_cmdline.md
- int i;
- int len = strlen(uboot_ver);
- for (i = 0; i < len; i++) {
- if (uboot_ver[i] == ' ') {
- uboot_ver[i] = '_';
- }
- }
-
- zircon_append_boot_item(zbi, ZBI_TYPE_CMDLINE, 0, uboot_ver,
- strlen(uboot_ver) + 1);
-
- /* add platform ID */
- zircon_append_boot_item(zbi, ZBI_TYPE_PLATFORM_ID, 0, &platform_id,
- sizeof(platform_id));
-
- int ret = add_mac_addresses(zbi);
-
- if (ret < 0) {
- printf("ERROR: unable to read MAC addresses from the"
- " factory partition!\n");
- }
- return 0;
-}
diff --git a/board/amlogic/g12b_puddy_px/Kconfig b/board/amlogic/g12b_puddy_px/Kconfig
deleted file mode 100644
index b6787d8..0000000
--- a/board/amlogic/g12b_puddy_px/Kconfig
+++ /dev/null
@@ -1,20 +0,0 @@
-if TARGET_G12B_PUDDY_PX
-
-config SYS_BOARD
- default "g12b_puddy_px"
-
-config SYS_VENDOR
- default "amlogic"
-
-config SYS_CONFIG_NAME
- default "g12b_puddy_px"
-
-config CONFIG_AML_ANTIROLLBACK
- bool
- default n
-
-config ZIRCON_BOOT_IMAGE
- bool "Zircon boot image support"
- default n
-
-endif
diff --git a/board/amlogic/g12b_puddy_px/Makefile b/board/amlogic/g12b_puddy_px/Makefile
deleted file mode 100644
index e2f2b99..0000000
--- a/board/amlogic/g12b_puddy_px/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-
-obj-y += $(BOARD).o eth_setup.o
-obj-$(CONFIG_AML_LCD) += lcd.o
-obj-$(CONFIG_ZIRCON_BOOT_IMAGE) += zircon.o
diff --git a/board/amlogic/g12b_puddy_px/aml-user-key.sig b/board/amlogic/g12b_puddy_px/aml-user-key.sig
deleted file mode 100644
index 2ceabc1..0000000
--- a/board/amlogic/g12b_puddy_px/aml-user-key.sig
+++ /dev/null
Binary files differ
diff --git a/board/amlogic/g12b_puddy_px/eth_setup.c b/board/amlogic/g12b_puddy_px/eth_setup.c
deleted file mode 100644
index 85a1b35..0000000
--- a/board/amlogic/g12b_puddy_px/eth_setup.c
+++ /dev/null
@@ -1,51 +0,0 @@
-
-/*
- * board/amlogic/g12b_w400_v1/eth_setup.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <malloc.h>
-#include <errno.h>
-#include <environment.h>
-#include <fdt_support.h>
-#include <linux/libfdt.h>
-#include <asm/arch/eth_setup.h>
-/*
- *
- *setup eth device board socket
- *
- */
-struct eth_board_socket* eth_board_setup(char *name){
- struct eth_board_socket* new_board;
- new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
- if (NULL == new_board) return NULL;
- if (name != NULL) {
- new_board->name=(char*)malloc(strlen(name));
- strncpy(new_board->name,name,strlen(name));
- }else{
- new_board->name="gxb";
- }
-
- new_board->eth_pinmux_setup=NULL ;
- new_board->eth_clock_configure=NULL;
- new_board->eth_hw_reset=NULL;
- return new_board;
-}
-//pinmux HHI_GCLK_MPEG1[bit 3]
-//
diff --git a/board/amlogic/g12b_puddy_px/firmware/acs.bin b/board/amlogic/g12b_puddy_px/firmware/acs.bin
deleted file mode 100755
index 9b7f075..0000000
--- a/board/amlogic/g12b_puddy_px/firmware/acs.bin
+++ /dev/null
Binary files differ
diff --git a/board/amlogic/g12b_puddy_px/firmware/acs.elf b/board/amlogic/g12b_puddy_px/firmware/acs.elf
deleted file mode 100755
index 94f8149..0000000
--- a/board/amlogic/g12b_puddy_px/firmware/acs.elf
+++ /dev/null
Binary files differ
diff --git a/board/amlogic/g12b_puddy_px/firmware/scp_task/pwm_ctrl.h b/board/amlogic/g12b_puddy_px/firmware/scp_task/pwm_ctrl.h
deleted file mode 100644
index 7adc97d..0000000
--- a/board/amlogic/g12b_puddy_px/firmware/scp_task/pwm_ctrl.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
-*board/amlogic/g12b_puddy_px/firmware/scp_task/pwm_ctrl.h
-*table for Dynamic Voltage/Frequency Scaling
-*/
-#ifndef __PWM_CTRL_H__
-#define __PWM_CTRL_H__
-
-static int pwm_voltage_table_ee[][2] = {
- { 0x1c0000, 681},
- { 0x1b0001, 691},
- { 0x1a0002, 701},
- { 0x190003, 711},
- { 0x180004, 721},
- { 0x170005, 731},
- { 0x160006, 741},
- { 0x150007, 751},
- { 0x140008, 761},
- { 0x130009, 772},
- { 0x12000a, 782},
- { 0x11000b, 792},
- { 0x10000c, 802},
- { 0x0f000d, 812},
- { 0x0e000e, 822},
- { 0x0d000f, 832},
- { 0x0c0010, 842},
- { 0x0b0011, 852},
- { 0x0a0012, 862},
- { 0x090013, 872},
- { 0x080014, 882},
- { 0x070015, 892},
- { 0x060016, 902},
- { 0x050017, 912},
- { 0x040018, 922},
- { 0x030019, 932},
- { 0x02001a, 942},
- { 0x01001b, 952},
- { 0x00001c, 962}
-};
-
-#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/g12b_puddy_px/firmware/scp_task/pwr_ctrl.c b/board/amlogic/g12b_puddy_px/firmware/scp_task/pwr_ctrl.c
deleted file mode 100644
index c1d7518..0000000
--- a/board/amlogic/g12b_puddy_px/firmware/scp_task/pwr_ctrl.c
+++ /dev/null
@@ -1,143 +0,0 @@
-
-/*
- * board/amlogic/g12b_puddy_px/firmware/scp_task/pwr_ctrl.c
- *
- * Copyright (C) 2019 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <gpio.h>
-#include "pwm_ctrl.h"
-#ifdef CONFIG_CEC_WAKEUP
-#include <cec_tx_reg.h>
-#endif
-
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
-static void set_vddee_voltage(unsigned int target_voltage)
-{
- unsigned int to;
-
- for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
- if (pwm_voltage_table_ee[to][1] >= target_voltage) {
- break;
- }
- }
-
- if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
- to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
- }
-
- writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
-}
-
-static void power_off_at_24M(unsigned int suspend_from)
-{
- /*set test_n low to power off vcck & vcc 3.3v*/
- writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
- writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
- writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
-
- /*step down ee voltage*/
- set_vddee_voltage(AML_VDDEE_SLEEP_VOLTAGE);
-}
-
-static void power_on_at_24M(unsigned int suspend_from)
-{
- /*step up ee voltage*/
- set_vddee_voltage(AML_VDDEE_INIT_VOLTAGE);
-
- /*set test_n low to power on vcck & vcc 3.3v*/
- writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
- writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
- writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
- _udelay(100);
-}
-
-void get_wakeup_source(void *response, unsigned int suspend_from)
-{
- struct wakeup_info *p = (struct wakeup_info *)response;
- unsigned val;
- unsigned i = 0;
-
- p->status = RESPONSE_OK;
- val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
- BT_WAKEUP_SRC);
-
- p->sources = val;
- p->gpio_info_count = i;
-
-}
-extern void __switch_idle_task(void);
-
-static unsigned int detect_key(unsigned int suspend_from)
-{
- int exit_reason = 0;
- unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
- unsigned char adc_key_cnt = 0;
- init_remote();
- saradc_enable();
-#ifdef CONFIG_CEC_WAKEUP
- if (hdmi_cec_func_config & 0x1) {
- remote_cec_hw_reset();
- cec_node_init();
- }
-#endif
-
- do {
- #ifdef CONFIG_CEC_WAKEUP
- if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
- irq[IRQ_AO_CECB] = 0xFFFFFFFF;
- if (cec_power_on_check())
- exit_reason = CEC_WAKEUP;
- }
- #endif
- if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
- irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
- if (remote_detect_key())
- exit_reason = REMOTE_WAKEUP;
- }
-
- if (irq[IRQ_AO_TIMERA] == IRQ_AO_TIMERA_NUM) {
- irq[IRQ_AO_TIMERA] = 0xFFFFFFFF;
- if (check_adc_key_resume()) {
- adc_key_cnt++;
- /*using variable 'adc_key_cnt' to eliminate the dithering of the key*/
- if (2 == adc_key_cnt)
- exit_reason = POWER_KEY_WAKEUP;
- } else {
- adc_key_cnt = 0;
- }
- }
-
- if (exit_reason)
- break;
- else
- __switch_idle_task();
- } while (1);
-
- saradc_disable();
-
- return exit_reason;
-}
-
-static void pwr_op_init(struct pwr_op *pwr_op)
-{
- pwr_op->power_off_at_24M = power_off_at_24M;
- pwr_op->power_on_at_24M = power_on_at_24M;
- pwr_op->detect_key = detect_key;
- pwr_op->get_wakeup_source = get_wakeup_source;
-}
diff --git a/board/amlogic/g12b_puddy_px/firmware/timing.c b/board/amlogic/g12b_puddy_px/firmware/timing.c
deleted file mode 100755
index 734cf2e..0000000
--- a/board/amlogic/g12b_puddy_px/firmware/timing.c
+++ /dev/null
@@ -1,609 +0,0 @@
-
-/*
- * board/amlogic/g12b_puddy_px/firmware/timing.c
- *
- * Copyright (C) 2019 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/timing.h>
-#include <asm/arch/ddr_define.h>
-
-/* board clk defines */
-#define DDR_SIZE 0
-#define CPU_CLK 1200
-
-/* ddr config support multiple configs for boards which use same bootloader:
- * config steps:
- * 1. add a new data struct in __ddr_setting[]
- * 2. config correct board_id, ddr_type, freq, etc..
- */
-
-
-/* CAUTION!! */
-/* Confirm ddr configs with hardware designer,
- * if you don't know how to config, then don't edit it
- */
-
-/* Key configs */
-/*
- * board_id: check hardware adc config
- * dram_rank_config:
- * #define CONFIG_DDR_CHL_AUTO 0xF
- * #define CONFIG_DDR0_16BIT_CH0 0x1
- * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
- * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
- * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
- * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
- * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
- * DramType:
- * #define CONFIG_DDR_TYPE_DDR3 0
- * #define CONFIG_DDR_TYPE_DDR4 1
- * #define CONFIG_DDR_TYPE_LPDDR4 2
- * #define CONFIG_DDR_TYPE_LPDDR3 3
- * DRAMFreq:
- * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
- *
- */
-
-
-/* ddr configs */
-#define DDR_RFC_TYPE_DDR3_512Mbx1 0
-#define DDR_RFC_TYPE_DDR3_512Mbx2 1
-#define DDR_RFC_TYPE_DDR3_512Mbx4 2
-#define DDR_RFC_TYPE_DDR3_512Mbx8 3
-#define DDR_RFC_TYPE_DDR3_512Mbx16 4
-#define DDR_RFC_TYPE_DDR4_2Gbx1 5
-#define DDR_RFC_TYPE_DDR4_2Gbx2 6
-#define DDR_RFC_TYPE_DDR4_2Gbx4 7
-#define DDR_RFC_TYPE_DDR4_2Gbx8 8
-
-#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
-#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
-#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
-
-ddr_set_t __ddr_setting[] = {
-#ifdef CONFIG_DDR_TIMING_DDR4
-{
- /* g12a skt (u209) ddr4 */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
- .DramType = CONFIG_DDR_TYPE_DDR4,
- .DRAMFreq = {912, 0, 0, 0},
- .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 1,
- .HdtCtrl = 0xC8,
- .dram_cs0_size_MB = 2048,
- .dram_cs1_size_MB = 0,
- .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, // // 2rank use 0x23 0x13 1rank use 0x30 0x30 Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //2rank use 0d0d 1rank use 0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .pll_ssc_mode = 0,
- .clk_drv_ohm = 40,
- .cs_drv_ohm = 40,
- .ac_drv_ohm = 40,
- .soc_data_drv_ohm_p = 34,
- .soc_data_drv_ohm_n = 34,
- .soc_data_odt_ohm_p = 60,
- .soc_data_odt_ohm_n = 0,
- .dram_data_drv_ohm = 48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
- .dram_data_odt_ohm = 60,
- .dram_ac_odt_ohm = 0,
- .soc_clk_slew_rate = 0x3ff,
- .soc_cs_slew_rate = 0x3ff,
- .soc_ac_slew_rate = 0x3ff,
- .soc_data_slew_rate = 0x2ff,
- .vref_output_permil = 500,
- .vref_receiver_permil = 700,
- .vref_dram_permil = 700,
- .ac_trace_delay = {00,00},
- .ac_pinmux = {00,00},
- .ddr_dmc_remap = {
- [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
- [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
- },
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap = {00,00},
- .dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
- .pll_ssc_mode = 0,
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
-},
-#endif
-#ifdef CONFIG_DDR_TIMING_DDR3
-{
- /* g12a skt (u209) ddr3 */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- .dram_rank_config = CONFIG_DDR0_16BIT_RANK01_CH0,
- .DramType = CONFIG_DDR_TYPE_DDR3,
- .DRAMFreq = {912, 0, 0, 0},
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 1,
- .HdtCtrl = 0xC8,
- .dram_cs0_size_MB = 1024,
- .dram_cs1_size_MB = 1024,
- .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, // // 2rank use 0x23 0x13 1rank use 0x30 0x30 Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //2rank use 0d0d 1rank use 0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .pll_ssc_mode = 0,
- .clk_drv_ohm = 40,
- .cs_drv_ohm = 40,
- .ac_drv_ohm = 40,
- .soc_data_drv_ohm_p = 34,
- .soc_data_drv_ohm_n = 34,
- .soc_data_odt_ohm_p = 60, //48,
- .soc_data_odt_ohm_n = 0,
- .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
- .dram_data_odt_ohm = 60,
- .dram_ac_odt_ohm = 0,
- .soc_clk_slew_rate = 0x300,
- .soc_cs_slew_rate = 0x300,
- .soc_ac_slew_rate = 0x300,
- .soc_data_slew_rate = 0x200,
- .vref_output_permil = 500,
- .vref_receiver_permil = 500, //700,
- .vref_dram_permil = 500, //700,
- .ac_trace_delay = {00,00},
- .ac_pinmux = {00,00},
- .ddr_dmc_remap = {
- [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
- [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
- },
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap = {00,00},
- .dram_rtt_nom_wr_park = {00,00},
-
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
-},
-#endif
-{
- /* g12a (google) lpddr4 */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- .fast_boot[0]=6,
- //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
- .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01,
- .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1,
- .DramType = CONFIG_DDR_TYPE_LPDDR4,
- .DRAMFreq = {1584, 0, 0, 0},
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 0,
- .HdtCtrl = 0xa,
- .dram_cs0_size_MB = 2048,//1024,
- .dram_cs1_size_MB = 0,//1024,
- .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, // // 2rank use 0x23 0x13 1rank use 0x30 0x30 Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //2rank use 0d0d 1rank use 0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .pll_ssc_mode = 0,
- .clk_drv_ohm = 48,
- .cs_drv_ohm = 48,
- .ac_drv_ohm = 48,
- .soc_data_drv_ohm_p = 48,
- .soc_data_drv_ohm_n = 48,
- .soc_data_odt_ohm_p = 0,
- .soc_data_odt_ohm_n = 48,
- .dram_data_drv_ohm = 48, //lpddr4 sdram only240/1-6
- .dram_data_odt_ohm = 48,//120,// 120,
- .dram_ac_odt_ohm = 120,
- .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
- .soc_clk_slew_rate = 0x3ff,//0x253,
- .soc_cs_slew_rate = 0x100,//0x253,
- .soc_ac_slew_rate = 0x100,//0x253,
- .soc_data_slew_rate = 0x1ff,
- .vref_output_permil = 350,//200,
- .vref_receiver_permil = 0,
- .vref_dram_permil = 0,
- //.vref_reverse = 0,
- .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
- //.ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
- .ac_pinmux = {00,00},
- .ddr_dmc_remap = {
- [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
- [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
- [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
- },
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap =
-//{3,2,0,1,7,6,5,4,14,13,12,15,8,9,11,10,20,21,22,23,16,17,19,18,24,25,28,26,31,30,27,29},
- {3,2,0,1,7,6,5,4, 10,9,14,11,8,12,13,15, 20,21,23,22,18,17,19,16, 28,26,25,24,31,30,27,29},
- .dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
- .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
- .diagnose = CONFIG_DIAGNOSE_DISABLE,
- .bitTimeControl_2d = 1,
- .slt_test_function[0]=DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT,
- //.dqs_adjust={100,100,100,100,100,100,100,100,
- // 100,100,100,100,100,100,100,100,
- //}, //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read
-},
-{
- /* use for repair */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
- .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH01,
- .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1,
- .DramType = CONFIG_DDR_TYPE_LPDDR4,
- .DRAMFreq = {1584, 0, 0, 0},
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 0,
- .HdtCtrl = 0xa,
- .dram_cs0_size_MB = 2048,//1024,
- .dram_cs1_size_MB = 0,//1024,
- .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, // // 2rank use 0x23 0x13 1rank use 0x30 0x30 Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //2rank use 0d0d 1rank use 0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .pll_ssc_mode = 0,
- .clk_drv_ohm = 40,
- .cs_drv_ohm = 40,
- .ac_drv_ohm = 40,
- .soc_data_drv_ohm_p = 40,
- .soc_data_drv_ohm_n = 40,
- .soc_data_odt_ohm_p = 0,
- .soc_data_odt_ohm_n = 48,
- .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
- .dram_data_odt_ohm = 40,//120,// 120,
- .dram_ac_odt_ohm = 120,
- .lpddr4_dram_vout_voltage_1_3_2_5_setting = 0,///1, 1/3vddq 0 2/5 vddq
- .soc_clk_slew_rate = 0x3ff,//0x253,
- .soc_cs_slew_rate = 0x100,//0x253,
- .soc_ac_slew_rate = 0x100,//0x253,
- .soc_data_slew_rate = 0x1ff,
- .vref_output_permil = 350,//200,
- .vref_receiver_permil = 0,
- .vref_dram_permil = 0,
- //.vref_reverse = 0,
- .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
- //.ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
- .ac_pinmux = {00,00},
- .ddr_dmc_remap = {
- [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
- [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
- [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
- },
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap =
-//{3,2,0,1,7,6,5,4,14,13,12,15,8,9,11,10,20,21,22,23,16,17,19,18,24,25,28,26,31,30,27,29},
- {3,2,0,1,7,6,5,4, 10,9,14,11,8,12,13,15, 20,21,23,22,18,17,19,16, 28,26,25,24,31,30,27,29},
- .dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
- .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
- .diagnose = CONFIG_DIAGNOSE_DISABLE,
- .bitTimeControl_2d = 1,
- //.dqs_adjust={100,100,100,100,100,100,100,100,
- // 100,100,100,100,100,100,100,100,
- //}, //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read
-},
-{
- /* use for fastboot */
- .board_id= CONFIG_BOARD_ID_MASK,
-},
-};
-
-pll_set_t __pll_setting = {
- .cpu_clk = CPU_CLK / 24 * 24,
-#ifdef CONFIG_PXP_EMULATOR
- .pxp = 1,
-#else
- .pxp = 0,
-#endif
- .spi_ctrl = 0,
- .lCustomerID = AML_CUSTOMER_ID,
-};
-
-ddr_reg_t __ddr_reg[] = {
- /* demo, user defined override register */
- {0xaabbccdd, 0, 0, 0, 0, 0},
- {0x11223344, 0, 0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0},
-};
-
-#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
-#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
-/* VCCK PWM table */
-#if (VCCK_VAL == 800)
- #define VCCK_VAL_REG 0x00150007
-#elif (VCCK_VAL == 810)
- #define VCCK_VAL_REG 0x00140008
-#elif (VCCK_VAL == 820)
- #define VCCK_VAL_REG 0x00130009
-#elif (VCCK_VAL == 830)
- #define VCCK_VAL_REG 0x0012000a
-#elif (VCCK_VAL == 840)
- #define VCCK_VAL_REG 0x0011000b
-#elif (VCCK_VAL == 850)
- #define VCCK_VAL_REG 0x0010000c
-#elif (VCCK_VAL == 860)
- #define VCCK_VAL_REG 0x000f000d
-#elif (VCCK_VAL == 870)
- #define VCCK_VAL_REG 0x000e000e
-#elif (VCCK_VAL == 880)
- #define VCCK_VAL_REG 0x000d000f
-#elif (VCCK_VAL == 890)
- #define VCCK_VAL_REG 0x000c0010
-#elif (VCCK_VAL == 900)
- #define VCCK_VAL_REG 0x000b0011
-#elif (VCCK_VAL == 910)
- #define VCCK_VAL_REG 0x000a0012
-#elif (VCCK_VAL == 920)
- #define VCCK_VAL_REG 0x00090013
-#elif (VCCK_VAL == 930)
- #define VCCK_VAL_REG 0x00080014
-#elif (VCCK_VAL == 940)
- #define VCCK_VAL_REG 0x00070015
-#elif (VCCK_VAL == 950)
- #define VCCK_VAL_REG 0x00060016
-#elif (VCCK_VAL == 960)
- #define VCCK_VAL_REG 0x00050017
-#elif (VCCK_VAL == 970)
- #define VCCK_VAL_REG 0x00040018
-#elif (VCCK_VAL == 980)
- #define VCCK_VAL_REG 0x00030019
-#elif (VCCK_VAL == 990)
- #define VCCK_VAL_REG 0x0002001a
-#elif (VCCK_VAL == 1000)
- #define VCCK_VAL_REG 0x0001001b
-#elif (VCCK_VAL == 1010)
- #define VCCK_VAL_REG 0x0000001c
-#else
- #error "VCCK val out of range\n"
-#endif
-
-/* VDDEE_VAL_REG0: VDDEE PWM table 0.67v-0.97v*/
-/* VDDEE_VAL_REG1: VDDEE PWM table 0.69v-0.89v*/
-#if (VDDEE_VAL == 800)
- #define VDDEE_VAL_REG0 0x0010000c
- #define VDDEE_VAL_REG1 0x0008000a
-#elif (VDDEE_VAL == 810)
- #define VDDEE_VAL_REG0 0x000f000d
- #define VDDEE_VAL_REG1 0x0007000b
-#elif (VDDEE_VAL == 820)
- #define VDDEE_VAL_REG0 0x000e000e
- #define VDDEE_VAL_REG1 0x0006000c
-#elif (VDDEE_VAL == 830)
- #define VDDEE_VAL_REG0 0x000d000f
- #define VDDEE_VAL_REG1 0x0005000d
-#elif (VDDEE_VAL == 840)
- #define VDDEE_VAL_REG0 0x000c0010
- #define VDDEE_VAL_REG1 0x0004000e
-#elif (VDDEE_VAL == 850)
- #define VDDEE_VAL_REG0 0x000b0011
- #define VDDEE_VAL_REG1 0x0003000f
-#elif (VDDEE_VAL == 860)
- #define VDDEE_VAL_REG0 0x000a0012
- #define VDDEE_VAL_REG1 0x00020010
-#elif (VDDEE_VAL == 870)
- #define VDDEE_VAL_REG0 0x00090013
- #define VDDEE_VAL_REG1 0x00010011
-#elif (VDDEE_VAL == 880)
- #define VDDEE_VAL_REG0 0x00080014
- #define VDDEE_VAL_REG1 0x00000012
-#else
- #error "VDDEE val out of range\n"
-#endif
-
-/* for PWM use */
-/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
-#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
-/* GPIOC output enable reg */
-#define GPIO_O_EN_N_REG1 ((0xff634400 + (0x13 << 2)))
-/* GPIOA output enable reg */
-#define GPIO_O_EN_N_REG5 ((0xff634400 + (0x20 << 2)))
-#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
-#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
-/* GPIOC input reg */
-#define GPIO_I_REG1 ((0xff634400 + (0x15 << 2)))
-/* GOUIA input reg */
-#define GPIO_I_REG5 ((0xff634400 + (0x22 << 2)))
-/* GPIOC pull up enable reg */
-#define GPIO_PULL_UP_EN_REG1 ((0xff634400 + (0x49 << 2)))
-/* GPIOA pull up enable reg */
-#define GPIO_PULL_UP_EN_REG5 ((0xff634400 + (0x4d << 2)))
-#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
-#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
-/* GPIOC pinmux reg */
-#define GPIO_PIN_MUX_REG9 ((0xff634400 + (0xb9 << 2)))
-/* GPIOA pinmux reg */
-#define GPIO_PIN_MUX_REGE ((0xff634400 + (0xbe << 2)))
-
-
-bl2_reg_t __bl2_reg[] = {
- /* demo, user defined override register */
- /* eg: PWM init */
-
- /* PWM_AO_D */
- /* VCCK_VAL_REG: check PWM table */
- {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
- {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
-
- /* PWM_AO_B */
-
- /* step1: GPIOC5, GPIOC4, GPIOC6, GPIOA12, GPIOA11 pre-init */
- /* disable pullup/pulldown */
- {GPIO_PULL_UP_EN_REG1, (0 << 4), (7 << 4), 0, BL2_INIT_STAGE_PWM_PRE_INIT, 0},
- {GPIO_PULL_UP_EN_REG5, (0 << 11), (3 << 11), 0, BL2_INIT_STAGE_PWM_PRE_INIT, 0},
- /* enable input */
- {GPIO_O_EN_N_REG1, (7 << 4), (7 << 4), 0, BL2_INIT_STAGE_PWM_PRE_INIT, 0},
- {GPIO_O_EN_N_REG5, (3 << 11), (3 << 11), 0, BL2_INIT_STAGE_PWM_PRE_INIT, 0},
- /* pinmux to gpio */
- {GPIO_PIN_MUX_REG9, (0 << 16), (0xfff << 16), 0, BL2_INIT_STAGE_PWM_PRE_INIT, 0},
- {GPIO_PIN_MUX_REGE, (0 << 11), (0xff << 12), 0, BL2_INIT_STAGE_PWM_PRE_INIT, 0},
-
- /* step2: check board config */
- /* HW_ID_0:GPIOA_11
- * HW_ID_1:GPIOA_12
- * HW_ID_2:GPIOC_6
- * HW_ID_3:GPIOC_4
- * HW_ID_4:GPIOC_5
- */
- {GPIO_I_REG1, 5, 0, 0, BL2_INIT_STAGE_PWM_CHK_HW, 0},
- {GPIO_I_REG1, 4, 0, 0, BL2_INIT_STAGE_PWM_CHK_HW, 0},
- {GPIO_I_REG1, 6, 0, 0, BL2_INIT_STAGE_PWM_CHK_HW, 0},
- {GPIO_I_REG5, 12, 0, 0, BL2_INIT_STAGE_PWM_CHK_HW, 0},
- {GPIO_I_REG5, 11, 0, 0, BL2_INIT_STAGE_PWM_CHK_HW, 0},
-
- /* step3: match PWM config */
- /* -----------------------------
- * |puddy | option| build |
- * -----------------------------
- * |BRD_ID | 4 | 3 | 2 | 1 | 0 |
- * -----------------------------
- * | | 0 | 1 | 0 | 0 | 0 |
- * -----------------------------
- * | | 0 | 1 | 0 | 0 | 1 |
- * -----------------------------
- * | P1 | 0 | 1 | 0 | 1 | 0 |
- * -----------------------------
- * | P2 | 0 | 1 | 0 | 1 | 1 |
- * -----------------------------
- * | P2RW | 0 | 1 | 1 | 0 | 0 |
- * -----------------------------
- * | P2.1 | 0 | 1 | 1 | 0 | 1 |
- * -----------------------------
- * | EVT | 0 | 1 | 1 | 1 | 0 |
- * -----------------------------
- * | | 0 | 1 | 1 | 1 | 1 |
- * -----------------------------
- * | DVT | 1 | 0 | 0 | 0 | 0 |
- * -----------------------------
- *
- * option = b'01 and build < b'011, use PWM_CFG0
- * option = b'01 and build = b'011, use PWM_CFG2 GPIOE_0 output low
- * option = b'01 and build > b'011, use PWM_CFG1
- * option = b'10, use PWM_CFG1
- */
- {0x8, PWM_CFG0, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0x9, PWM_CFG0, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0xa, PWM_CFG0, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0xb, PWM_CFG2, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0xc, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0xd, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0xe, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0xf, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0x10, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0x11, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
- {0x12, PWM_CFG1, 0, 0, BL2_INIT_STAGE_PWM_CFG_GROUP, 0},
-
- /* step4: config PWM */
- /* PWM_CFG0: VDDEE PWM table 0.67v ~ 0.97v */
- {AO_PWM_PWM_B, VDDEE_VAL_REG0, 0xffffffff, 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0},
- {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0},
- {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG0, 0},
- /* PWM_CFG1: VDDEE PWM table 0.69v ~ 0.89v */
- {AO_PWM_PWM_B, VDDEE_VAL_REG1, 0xffffffff, 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0},
- {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0},
- {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG1, 0},
-
- /* PWM_CFG2: VDDEE PWM low; table 0.69v ~ 0.90v */
- {AO_PIN_MUX_REG1, 0, (0xF << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG2, 0},
- {AO_GPIO_O_EN_N, 0, (0x1 << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG2, 0},
- {AO_GPIO_O, 0, (0x1 << 16), 0, BL2_INIT_STAGE_PWM_INIT | PWM_CFG2, 0},
-
- //GPIOAO_4 set high
- {AO_GPIO_O_EN_N, (0<<4), (1<<4), 0, BL2_INIT_STAGE_1, 0},
- {AO_GPIO_O, (1<<4), (1<<4), 0, BL2_INIT_STAGE_1, 0},
- /* Enable 5V_EN */
- {GPIO_O_EN_N_REG3, (0 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
- {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- /* Enable VCCK */
- {AO_SEC_REG0, (1 << 0), 0x1, 0, BL2_INIT_STAGE_1, 0},
- {AO_GPIO_O, 0x80000000, 0x80000000, 0, BL2_INIT_STAGE_1, 0},
-};
diff --git a/board/amlogic/g12b_puddy_px/g12b_puddy_px.c b/board/amlogic/g12b_puddy_px/g12b_puddy_px.c
deleted file mode 100644
index 1d08671..0000000
--- a/board/amlogic/g12b_puddy_px/g12b_puddy_px.c
+++ /dev/null
@@ -1,1218 +0,0 @@
-
-/*
- * board/amlogic/g12b_puddy_px/g12b_puddy_px.c
- *
- * Copyright (C) 2019 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <malloc.h>
-#include <errno.h>
-#include <environment.h>
-#include <fdt_support.h>
-#include <linux/libfdt.h>
-#include <asm/arch/cpu_id.h>
-#ifdef CONFIG_SYS_I2C_MESON
-#include <i2c.h>
-#include <dt-bindings/i2c/meson-i2c.h>
-#endif
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/pinctrl_init.h>
-#ifdef CONFIG_AML_VPU
-#include <amlogic/media/vpu/vpu.h>
-#endif
-#ifdef CONFIG_AML_VPP
-#include <amlogic/media/vpp/vpp.h>
-#endif
-#ifdef CONFIG_AML_V2_FACTORY_BURN
-#include <amlogic/aml_v2_burning.h>
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
-#ifdef CONFIG_AML_HDMITX
-#include <amlogic/media/vout/hdmitx.h>
-#endif
-#ifdef CONFIG_AML_LCD
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#endif
-#include <asm/arch/eth_setup.h>
-#include <phy.h>
-#include <linux/mtd/partitions.h>
-#include <linux/sizes.h>
-#include <asm-generic/gpio.h>
-#include <dm.h>
-#ifdef CONFIG_AML_SPIFC
-#include <amlogic/spifc.h>
-#endif
-#ifdef CONFIG_AML_SPICC
-#include <amlogic/spicc.h>
-#endif
-#include <asm/armv8/mmu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-//new static eth setup
-struct eth_board_socket* eth_board_skt;
-
-int do_get_ddictype (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-#if defined(CONFIG_NAND_FTS) || defined(CONFIG_MMC_FTS)
-#if defined(CONFIG_NAND_FTS)
- extern bool amlnf_is_inited(void);
- if (!amlnf_is_inited()) {
-#endif
-
-#if defined(CONFIG_MMC_FTS)
- extern bool amlmmc_is_inited(void);
- if (!amlmmc_is_inited()) {
-#endif
- env_set("ddic_type", "FITI");
- return 0;
- }
-
- flash_ts_init();
-
- const char *fts_key = "ddic.type";
-
- char fts_value[256] = { 0 };
- flash_ts_get(fts_key, fts_value, sizeof(fts_value));
-
- pr_info("FTS read: ddic.type -> %s\n", fts_value);
-
- if (strncmp(fts_value, "NOVATEK", sizeof(fts_value)) == 0) {
- env_set("ddic_type", "NOVATEK");
- } else {
- env_set("ddic_type", "FITI");
- }
-#endif
- return 0;
-}
-
-U_BOOT_CMD(
- get_ddictype, 1, 0, do_get_ddictype,
- "get ddic type",
- " This command will get and setenv 'ddic_type'\n"
-);
-
-// Disable pull-up resistor GPIOH_3 so the mute switch status can be read.
-// Disable pull-up resistors GPIOA_11 & GPIOA_12 so the HW ID can be read.
-// The other HW ID GPIOS (GPIOH_0, GPIOH_1, GPIOH_2) are OD pins.
-// Disable pull-up resistor for GPIOA0_1 for UART.
-static void gpio_disable_pullup(void)
-{
- int ret;
-
- ret = readl(PAD_PULL_UP_EN_REG5);
- writel(ret & (~(1 << 11)), PAD_PULL_UP_EN_REG5);
-
- ret = readl(PAD_PULL_UP_EN_REG5);
- writel(ret & (~(1 << 12)), PAD_PULL_UP_EN_REG5);
-
- ret = readl(PAD_PULL_UP_EN_REG3);
- writel(ret & (~(1 << 3)), PAD_PULL_UP_EN_REG3);
-
- // UART RX (GPIOAO_1)
- ret = readl(AO_RTI_PULL_UP_REG);
- writel(ret & (~(1 << 1)), AO_RTI_PULL_UP_REG);
-}
-
-int do_get_puddy_hw_id(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- unsigned int hw_id = 0, ret = 0;
- char hw_id_str[8] = {0}; // eg: 0x0A
-
- // Reading from highest bit to lowest bit
- // HW_ID_4: GPIOH_2
- ret = readl(P_PREG_PAD_GPIO3_I);
- hw_id |= (ret & (1<<2)) >> 2;
- hw_id = hw_id << 1;
-
- // HW_ID_3: GPIOH_1
- ret = readl(P_PREG_PAD_GPIO3_I);
- hw_id |= (ret & (1<<1)) >> 1;
- hw_id = hw_id << 1;
-
- // HW_ID_2: GPIOH_0
- ret = readl(P_PREG_PAD_GPIO3_I);
- hw_id |= (ret & 1);
- hw_id = hw_id << 1;
-
- // HW_ID_1: GPIOA_12
- ret = readl(P_PREG_PAD_GPIO5_I);
- hw_id |= (ret & (1<<12)) >> 12;
- hw_id = hw_id << 1;
-
- // HW_ID_0: GPIOA_11
- ret = readl(P_PREG_PAD_GPIO5_I);
- hw_id |= (ret & (1<<11)) >> 11;
-
- snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id);
- env_set("hw_id", hw_id_str);
- return 0;
-}
-
-U_BOOT_CMD(
- get_puddy_hw_id, 1, 0, do_get_puddy_hw_id,
- "get puddy's HW_ID and setenv 'hw_id'\n",
- "get_puddy_hw_id"
-);
-
-int serial_set_pin_port(unsigned long port_base)
-{
- //UART in "Always On Module"
- //GPIOAO_0==tx,GPIOAO_1==rx
- //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
- return 0;
-}
-
-#define SOC_ADCMUX_SEL "GPIOA_0"
-static void soc_adcmux_sel(bool enable)
-{
- int ret;
- struct gpio_desc soc_adcmux_desc;
-
- ret = dm_gpio_lookup_name("gpioa_0", &soc_adcmux_desc);
- if (ret) {
- printf("%s: not found\n", "gpioa_0");
- return ret;
- }
-
- ret = dm_gpio_request(&soc_adcmux_desc, SOC_ADCMUX_SEL);
- if (ret && ret != -EBUSY) {
- printf("gpio: requesting pin %s failed\n", SOC_ADCMUX_SEL);
- return;
- }
- ret = dm_gpio_set_dir_flags(&soc_adcmux_desc, GPIOD_IS_OUT);
- if (ret) {
- printf("set direction failed\n");
- return ret;
- }
-
- dm_gpio_set_value(&soc_adcmux_desc, enable ? 1 : 0);
-}
-
-#define USB_HOST_ENABLE_PIN_NAME "GPIOA_13"
-static void enable_usb_host(bool enable)
-{
- int ret;
- struct gpio_desc usb_host_desc;
-
- ret = dm_gpio_lookup_name("gpioa_13", &usb_host_desc);
- if (ret) {
- printf("%s: not found\n", "gpioa_13");
- return ret;
- }
-
- ret = dm_gpio_request(&usb_host_desc, USB_HOST_ENABLE_PIN_NAME);
- if (ret && ret != -EBUSY) {
- printf("gpio: requesting pin %s failed\n", USB_HOST_ENABLE_PIN_NAME);
- return;
- }
- ret = dm_gpio_set_dir_flags(&usb_host_desc, GPIOD_IS_OUT);
- if (ret) {
- printf("set direction failed\n");
- return ret;
- }
-
- dm_gpio_set_value(&usb_host_desc, enable ? 1 : 0);
-}
-
-
-//SOC_BL_ENABLE
-//#define BL_ENABLE_PIN GPIOEE(GPIOA_10)
-#define BL_ENABLE_PIN_NAME "GPIOA_10"
-
-static void enable_backlight(bool enable)
-{
- int ret;
- struct gpio_desc bl_pow_desc;
-
- ret = dm_gpio_lookup_name("gpioa_10", &bl_pow_desc);
- if (ret) {
- printf("%s: not found\n", "gpioa_10");
- return ret;
- }
-
- ret = dm_gpio_request(&bl_pow_desc, BL_ENABLE_PIN_NAME);
- if (ret && ret != -EBUSY) {
- printf("gpio: requesting pin %s failed\n", BL_ENABLE_PIN_NAME);
- return;
- }
- //gpio_direction_output(BL_ENABLE_PIN, enable ? 1 : 0);
- ret = dm_gpio_set_dir_flags(&bl_pow_desc, GPIOD_IS_OUT);
- if (ret) {
- printf("set direction failed\n");
- return ret;
- }
-
- dm_gpio_set_value(&bl_pow_desc, enable ? 1 : 0);
-}
-
-int dram_init(void)
-{
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-/* secondary_boot_func
- * this function should be write with asm, here, is is only for compiling pass
- * */
-void secondary_boot_func(void)
-{
-}
-#ifdef ETHERNET_INTERNAL_PHY
-void internalPhyConfig(struct phy_device *phydev)
-{
-}
-
-static int dwmac_meson_cfg_pll(void)
-{
- writel(0x39C0040A, P_ETH_PLL_CTL0);
- writel(0x927E0000, P_ETH_PLL_CTL1);
- writel(0xAC5F49E5, P_ETH_PLL_CTL2);
- writel(0x00000000, P_ETH_PLL_CTL3);
- udelay(200);
- writel(0x19C0040A, P_ETH_PLL_CTL0);
- return 0;
-}
-
-static int dwmac_meson_cfg_analog(void)
-{
- /*Analog*/
- writel(0x20200000, P_ETH_PLL_CTL5);
- writel(0x0000c002, P_ETH_PLL_CTL6);
- writel(0x00000023, P_ETH_PLL_CTL7);
-
- return 0;
-}
-
-static int dwmac_meson_cfg_ctrl(void)
-{
- /*config phyid should between a 0~0xffffffff*/
- /*please don't use 44000181, this has been used by internal phy*/
- writel(0x33000180, P_ETH_PHY_CNTL0);
-
- /*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/
- writel(0x260, P_ETH_PHY_CNTL2);
-
- writel(0x74043, P_ETH_PHY_CNTL1);
- writel(0x34043, P_ETH_PHY_CNTL1);
- writel(0x74043, P_ETH_PHY_CNTL1);
- return 0;
-}
-
-static void setup_net_chip(void)
-{
- eth_aml_reg0_t eth_reg0;
-
- eth_reg0.d32 = 0;
- eth_reg0.b.phy_intf_sel = 4;
- eth_reg0.b.rx_clk_rmii_invert = 0;
- eth_reg0.b.rgmii_tx_clk_src = 0;
- eth_reg0.b.rgmii_tx_clk_phase = 0;
- eth_reg0.b.rgmii_tx_clk_ratio = 4;
- eth_reg0.b.phy_ref_clk_enable = 1;
- eth_reg0.b.clk_rmii_i_invert = 1;
- eth_reg0.b.clk_en = 1;
- eth_reg0.b.adj_enable = 1;
- eth_reg0.b.adj_setup = 0;
- eth_reg0.b.adj_delay = 9;
- eth_reg0.b.adj_skew = 0;
- eth_reg0.b.cali_start = 0;
- eth_reg0.b.cali_rise = 0;
- eth_reg0.b.cali_sel = 0;
- eth_reg0.b.rgmii_rx_reuse = 0;
- eth_reg0.b.eth_urgent = 0;
- setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
-
- dwmac_meson_cfg_pll();
- dwmac_meson_cfg_analog();
- dwmac_meson_cfg_ctrl();
-
- /* eth core clock */
- setbits_le32(HHI_GCLK_MPEG1, (0x1 << 3));
- /* eth phy clock */
- setbits_le32(HHI_GCLK_MPEG0, (0x1 << 4));
-
- /* eth phy pll, clk50m */
- setbits_le32(HHI_FIX_PLL_CNTL3, (0x1 << 5));
-
- /* power on memory */
- clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
-}
-#endif
-
-#ifdef ETHERNET_EXTERNAL_PHY
-
-static int dwmac_meson_cfg_drive_strength(void)
-{
- writel(0xaaaaaaa5, P_PAD_DS_REG4A);
- return 0;
-}
-
-static void setup_net_chip_ext(void)
-{
- eth_aml_reg0_t eth_reg0;
- writel(0x11111111, P_PERIPHS_PIN_MUX_6);
- writel(0x111111, P_PERIPHS_PIN_MUX_7);
-
- eth_reg0.d32 = 0;
- eth_reg0.b.phy_intf_sel = 1;
- eth_reg0.b.rx_clk_rmii_invert = 0;
- eth_reg0.b.rgmii_tx_clk_src = 0;
- eth_reg0.b.rgmii_tx_clk_phase = 1;
- eth_reg0.b.rgmii_tx_clk_ratio = 4;
- eth_reg0.b.phy_ref_clk_enable = 1;
- eth_reg0.b.clk_rmii_i_invert = 0;
- eth_reg0.b.clk_en = 1;
- eth_reg0.b.adj_enable = 0;
- eth_reg0.b.adj_setup = 0;
- eth_reg0.b.adj_delay = 0;
- eth_reg0.b.adj_skew = 0;
- eth_reg0.b.cali_start = 0;
- eth_reg0.b.cali_rise = 0;
- eth_reg0.b.cali_sel = 0;
- eth_reg0.b.rgmii_rx_reuse = 0;
- eth_reg0.b.eth_urgent = 0;
- setbits_le32(P_PREG_ETH_REG0, eth_reg0.d32);// rmii mode
-
- setbits_le32(HHI_GCLK_MPEG1, 0x1 << 3);
- /* power on memory */
- clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
-}
-#endif
-extern struct eth_board_socket* eth_board_setup(char *name);
-extern int designware_initialize(ulong base_addr, u32 interface);
-
-int board_eth_init(bd_t *bis)
-{
-#ifdef CONFIG_ETHERNET_NONE
- return 0;
-#endif
-
-#ifdef ETHERNET_EXTERNAL_PHY
- dwmac_meson_cfg_drive_strength();
- setup_net_chip_ext();
-#endif
-#ifdef ETHERNET_INTERNAL_PHY
- setup_net_chip();
-#endif
- udelay(1000);
- designware_initialize(ETH_BASE, PHY_INTERFACE_MODE_RMII);
- return 0;
-}
-
-#if CONFIG_AML_SD_EMMC
-#include <mmc.h>
-#include <asm/arch/sd_emmc.h>
-static int sd_emmc_init(unsigned port)
-{
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
- //todo add card detect
- /* check card detect */
- clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
- setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
- setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
- setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
- break;
- case SDIO_PORT_C:
- //enable pull up
- //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
- break;
- default:
- break;
- }
-
- return cpu_sd_emmc_init(port);
-}
-
-extern unsigned sd_debug_board_1bit_flag;
-
-
-static void sd_emmc_pwr_prepare(unsigned port)
-{
- cpu_sd_emmc_pwr_prepare(port);
-}
-
-static void sd_emmc_pwr_on(unsigned port)
-{
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
-// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
-// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
- /// @todo NOT FINISH
- break;
- case SDIO_PORT_C:
- break;
- default:
- break;
- }
- return;
-}
-static void sd_emmc_pwr_off(unsigned port)
-{
- /// @todo NOT FINISH
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
-// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
-// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
- break;
- case SDIO_PORT_C:
- break;
- default:
- break;
- }
- return;
-}
-
-// #define CONFIG_TSD 1
-static void board_mmc_register(unsigned port)
-{
- struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
- if (aml_priv == NULL)
- return;
-
- aml_priv->sd_emmc_init=sd_emmc_init;
- aml_priv->sd_emmc_detect=sd_emmc_detect;
- aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
- aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
- aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
- aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
-
- if (NULL == aml_priv->desc_buf)
- printf(" desc_buf Dma alloc Fail!\n");
- else
- printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
-
- sd_emmc_register(aml_priv);
-}
-int board_mmc_init(bd_t *bis)
-{
-#if 0
-#ifdef CONFIG_VLSI_EMULATOR
- //board_mmc_register(SDIO_PORT_A);
-#else
- //board_mmc_register(SDIO_PORT_B);
-#endif
- board_mmc_register(SDIO_PORT_B);
- board_mmc_register(SDIO_PORT_C);
-// board_mmc_register(SDIO_PORT_B1);
-#endif
- return 0;
-}
-#endif
-
-/* Skip the first line and parse one uint
- * Return negative if not found */
-int parse_backlight_calibration_file_string(const char *str)
-{
- if (str == NULL)
- return -EINVAL;
-
- str = strchr(str, '\n');
- if (str == NULL)
- return -EINVAL;
- ++str;
-
- return simple_strtoul(str, NULL, 10);
-}
-
-/* If zero, this value has not been set and the default brightness should not be
- * overwritten. To store zero, store a non-zero value with its bottom 12 bits
- * all zero, like 0x1000.
- */
-int get_persistent_brightness(void)
-{
- u32 brightness_sticky_val = readl(AO_RTI_STICKY_REG2);
- if (brightness_sticky_val != 0)
- return (brightness_sticky_val & 0x0fff) >> 1;
- return -1;
-}
-
-int do_configure_backlight(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
-#ifdef CONFIG_SYS_I2C_MESON
- int ret, i, attempt;
- const int retries = 3;
- char *addr_cal;
- int calibrated_current, persistent_brightness;
-
- /* Values to write:
- * [0]: Brightness register control only, backlight enabled
- * [1-2]: Standby disabled, 23 mA MAX_CURRENT,
- * CURRENT scale = 20 * 4095 / 23
- * [3]: Enable undervoltage protection at 2.5 V, "disable" backlight
- * (i2c only), disable set resistors
- * [4]: 6-phase, 6 drivers, 9.6kHz PWM rate
- * [5]: EN_DRV3, EN_DRV2, boost inductor current limit = 1.6 A
- * [6]: VBOOST_MAX = 25 V, JUMP_EN = 0
- * [7]: STEP_UP = 105 mV, STEP_DN = 105 mV, LED_FAULT_TH = 3V,
- * LED_COMP_HYST = DRIVER_HEADROOM + 750 mV
- * [8-9]: 12-bit brightness (default: 33.3%)
- * Important: Write brightness last to apply current calibration */
- const __u8 addrs[] = {0x01, 0xa0, 0xa1, 0xa2, 0xa5, 0xa7, 0xa9, 0xae,
- 0x10, 0x11};
- __u8 values[] = {0x85, 0xd3, 0x4b, 0x20, 0x04, 0xf4, 0x60, 0x09,
- 0x55, 0x05};
- const int n_bytes = sizeof(addrs) / sizeof(addrs[0]);
- struct udevice *bl_devp = NULL;
-
- if (argc > 2) {
- printf("%s: Too many args: %d\n", __func__, argc);
- return CMD_RET_USAGE;
- }
-
- if (argc == 2) {
- addr_cal = (char *)simple_strtoul(argv[1], NULL, 16);
- calibrated_current =
- parse_backlight_calibration_file_string(addr_cal);
- if (calibrated_current >= 0 && calibrated_current <= 4095) {
- /* CURRENT_LSB */
- values[1] = 0xff & calibrated_current;
- /* CURRENT_MSB */
- values[2] = (values[2] & 0xf0) |
- (0x0f & (calibrated_current >> 8));
- }
- }
-
- // Apply persistent brightness if found
- persistent_brightness = get_persistent_brightness();
- if (persistent_brightness >= 0) {
- pr_info("Applying persistent_brightness=%d\n", persistent_brightness);
- /* Get LSB and MSB */
- values[n_bytes - 2] = persistent_brightness & 0xff;
- values[n_bytes - 1] = persistent_brightness >> 8 & 0x0f;
- } else {
- pr_info("Persistent_brightness not set\n");
- }
-
- enable_backlight(true);
-
- ret = i2c_get_chip_for_busnum(MESON_I2C_M3, 0X2c, 1, &bl_devp);
- if (ret) {
- printf("%s(%d):i2c get bus fail!\n", __func__, __LINE__);
- }
-
- for (i = 0; i < n_bytes; ++i) {
- for (attempt = 0; attempt < retries; ++attempt) {
- ret = dm_i2c_write(bl_devp, addrs[i], &values[i], 1);
- if (ret)
- printf("%s: Attempt=%d to write byte=0x%02x to reg=0x%02x of backlight failed\n",
- __func__, attempt, values[i], addrs[i]);
- else
- break;
- }
- }
- return ret;
-#else
- enable_backlight(true);
- return 0;
-#endif /* CONFIG_SYS_I2C_MESON */
-}
-
-U_BOOT_CMD(
- configure_backlight, 2, 0, do_configure_backlight,
- "configures the lp8556 backlight",
- "Usage: configure_backlight [calibration_string_addr]\n"\
- " Sets up required parameters of the backlight.\n"\
- " Default calibration is 100%.\n"\
- " calibration_str_addr (optional):\n"\
- " Address of the calibration file string to parse.\n"
-);
-
-#ifdef CONFIG_AML_LCD
-/* Parses one line of the gamma calibration file. */
-/* Returns true on success. */
-#define GAMMA_SIZE (256)
-bool parse_gamma_string(const char *str, uint16_t *table)
-{
- char buf[4] = {'\0'};
- int i;
-
- for (i = 0; i < GAMMA_SIZE; ++i) {
- strncpy(buf, &str[3 * i], 3);
- table[i] = simple_strtol(buf, NULL, 16);
- }
-
- return true;
-}
-
-/* Check header then parse RGB gamma tables */
-/* Returns negative value on error */
-int parse_gamma_calibration_file_string(const char *str, u16 *r, u16 *g, u16 *b)
-{
- static const char supported_header_prefix[] = "Gamma Calibration 1.";
- static const int length = sizeof(supported_header_prefix) - 1;
- char *tables[3] = {r, g, b};
- const char *start, *end;
- int i;
-
- if (!str)
- return -EINVAL;
-
- // Check header prefix - only care about major version.
- if (strncmp(str, supported_header_prefix, length) != 0) {
- printf("Unknown gamma header: \"%.*s\"\n", length, str);
- return -EINVAL;
- }
-
- // Parse all three tables
- end = strchr(str, '\n');
- for (i = 0; i < 3; ++i) {
- start = end + 1;
- end = strchr(start, '\n');
-
- if ((end - start) / 3 != GAMMA_SIZE) {
- printf("Gamma table has invalid length.\n");
- return -EINVAL;
- }
- if (!parse_gamma_string(start, tables[i])) {
- printf("Could not parse gamma table %d.\n", i);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-#endif // CONFIG_AML_LCD
-
-int do_configure_gamma(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
-#ifdef CONFIG_AML_LCD
- static const int N_CHAN = 3;
- char *addr_cal;
- u16 gamma_tables[N_CHAN][GAMMA_SIZE];
- int i, j;
-
- if (argc == 1) {
- // Set to default
- for (i = 0; i < N_CHAN; ++i) {
- for (j = 0; j < GAMMA_SIZE; ++j)
- gamma_tables[i][j] = j << 2; /* 10-bit */
- }
- } else if (argc == 2) {
- // Load from passed file string
- addr_cal = (char *)simple_strtoul(argv[1], NULL, 16);
- if (parse_gamma_calibration_file_string(addr_cal,
- &gamma_tables[0],
- &gamma_tables[1],
- &gamma_tables[2]) != 0)
- return -EINVAL; // Error logged
- } else {
- return CMD_RET_USAGE;
- }
-
- vpp_set_rgb_gamma_table(&gamma_tables[0], &gamma_tables[1],
- &gamma_tables[2]);
-#endif // CONFIG_AML_LCD
- return 0;
-}
-
-U_BOOT_CMD(configure_gamma, 2, 0, do_configure_gamma,
- "configures gamma the gamma tables with the provided calibration\n",
- "Usage: configure_gamma [calibration_string_addr]\n"\
- " Applies the provided calibration file.\n"\
- " If a file is not provided, sets tables to default.\n"\
- " calibration_str_addr (optional):\n"\
- " Address of the calibration file string to parse.\n"
-);
-
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
-int board_early_init_f(void){
- /*add board early init function here*/
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
-#include <asm/arch/usb-v2.h>
-#include <asm/arch/gpio.h>
-#define CONFIG_GXL_USB_U2_PORT_NUM 2
-
-#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
-#define CONFIG_GXL_USB_U3_PORT_NUM 1
-#else
-#define CONFIG_GXL_USB_U3_PORT_NUM 0
-#endif
-
-static void gpio_set_vbus_power(char is_power_on)
-{
- int ret;
-
- ret = gpio_request(CONFIG_USB_GPIO_PWR,
- CONFIG_USB_GPIO_PWR_NAME);
- if (ret && ret != -EBUSY) {
- printf("gpio: requesting pin %u failed\n",
- CONFIG_USB_GPIO_PWR);
- return;
- }
-
- if (is_power_on) {
- gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
- } else {
- gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
- }
-}
-
-struct amlogic_usb_config g_usb_config_GXL_skt={
- CONFIG_GXL_XHCI_BASE,
- USB_ID_MODE_HARDWARE,
- gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
- CONFIG_GXL_USB_PHY2_BASE,
- CONFIG_GXL_USB_PHY3_BASE,
- CONFIG_GXL_USB_U2_PORT_NUM,
- CONFIG_GXL_USB_U3_PORT_NUM,
- .usb_phy2_pll_base_addr = {
- CONFIG_USB_PHY_20,
- CONFIG_USB_PHY_21,
- }
-};
-
-#endif /*CONFIG_USB_XHCI_AMLOGIC*/
-
-#ifdef CONFIG_AML_HDMITX20
-static void hdmi_tx_set_hdmi_5v(void)
-{
-}
-#endif
-
-#ifdef CONFIG_AML_SPIFC
-/*
- * BOOT_3: NOR_HOLDn:reg0[15:12]=3
- * BOOT_4: NOR_D:reg0[19:16]=3
- * BOOT_5: NOR_Q:reg0[23:20]=3
- * BOOT_6: NOR_C:reg0[27:24]=3
- * BOOT_7: NOR_WPn:reg0[31:28]=3
- * BOOT_14: NOR_CS:reg1[27:24]=3
- */
-#define SPIFC_NUM_CS 1
-static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
-
-static int spifc_pinctrl_enable(void *pinctrl, bool enable)
-{
- unsigned int val;
-
- val = readl(P_PERIPHS_PIN_MUX_0);
- val &= ~(0xfffff << 12);
- if (enable)
- val |= 0x33333 << 12;
- writel(val, P_PERIPHS_PIN_MUX_0);
-
- val = readl(P_PERIPHS_PIN_MUX_1);
- val &= ~(0xf << 24);
- writel(val, P_PERIPHS_PIN_MUX_1);
- return 0;
-}
-
-#if 0
-static const struct spifc_platdata spifc_platdata = {
- .reg = 0xffd14000,
- .mem_map = 0xf6000000,
- .pinctrl_enable = spifc_pinctrl_enable,
- .num_chipselect = SPIFC_NUM_CS,
- .cs_gpios = spifc_cs_gpios,
-};
-
-U_BOOT_DEVICE(spifc) = {
- .name = "spifc",
- .platdata = &spifc_platdata,
-};
-#endif
-#endif /* CONFIG_AML_SPIFC */
-
-#if 0
-#ifdef CONFIG_AML_SPICC
-/* generic config in arch gpio/clock.c */
-extern int spicc1_clk_set_rate(int rate);
-extern int spicc1_clk_enable(bool enable);
-extern int spicc1_pinctrl_enable(bool enable);
-
-static const struct spicc_platdata spicc1_platdata = {
- .compatible = "amlogic,meson-g12a-spicc",
- .reg = (void __iomem *)0xffd15000,
- .clk_rate = 666666666,
- .clk_set_rate = spicc1_clk_set_rate,
- .clk_enable = spicc1_clk_enable,
- .pinctrl_enable = spicc1_pinctrl_enable,
- /* case one slave without cs: {"no_cs", 0} */
- .cs_gpio_names = {"GPIOH_6", 0},
-};
-
-U_BOOT_DEVICE(spicc1) = {
- .name = "spicc",
- .platdata = &spicc1_platdata,
-};
-#endif /* CONFIG_AML_SPICC */
-#endif
-
-extern void aml_pwm_cal_init(int mode);
-
-int board_init(void)
-{
- int ret = 0;
- unsigned char value = 0;
-#ifdef CONFIG_SYS_I2C_MESON
- struct udevice *lcd_devp = NULL;
-#endif
- //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
- //As NOT NEED other board init If USB BOOT MODE
-#ifdef CONFIG_AML_V2_FACTORY_BURN
- *(volatile uint32_t *)P_RESET1_LEVEL |= (3 << 16);
- if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
- aml_try_factory_usb_burning(0, gd->bd);
- }
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
-#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
- board_usb_pll_disable(&g_usb_config_GXL_skt);
- board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
-#endif /*CONFIG_USB_XHCI_AMLOGIC*/
- pinctrl_devices_active(PIN_CONTROLLER_NUM);
- enable_backlight(false);
-
-#ifdef CONFIG_SYS_I2C_MESON
- //board_i2c_init();
- //GPIOZ_11 needs to be pulled down first to fit power on sequence
- /* clear GPIOZ_11 pinmux */
- ret = readl(P_PERIPHS_PIN_MUX_7);
- writel(ret & (~(0xf<<12)), P_PERIPHS_PIN_MUX_7);
- /* set GPIOZ_11 output mode */
- ret = readl(P_PREG_PAD_GPIO4_EN_N);
- writel(ret & (~(1<<11)), P_PREG_PAD_GPIO4_EN_N);
- /* set GPIOZ_11 output low */
- ret = readl(P_PREG_PAD_GPIO4_O);
- writel(ret & (~(1<<11)), P_PREG_PAD_GPIO4_O);
- udelay(1000);
-
- //set lcd bias voltage
- value = 0x0f; // +/- 5.5V
-
- ret = i2c_get_chip_for_busnum(MESON_I2C_M3, 0X3E, 1, &lcd_devp);
- if (ret) {
- printf("%s(%d):i2c get bus fail!\n", __func__, __LINE__);
- }
-
- ret = dm_i2c_write(lcd_devp, 0x0, &value, 1); // VPOS
- if (ret)
- printf("Failed to set VPOS to 5.5V for LCD\n");
-
- ret = dm_i2c_write(lcd_devp, 0x1, &value, 1); // VNEG
- if (ret)
- printf("Failed to set VNEG to -5.5V for LCD\n");
-#endif
-#if 0
- aml_pwm_cal_init(0);
-#endif//
-#ifdef CONFIG_AML_NAND
- extern int amlnf_init(unsigned char flag);
- amlnf_init(0);
-#endif
-
- gpio_disable_pullup();
-
- // Enable USB Host for Puddy px
- enable_usb_host(true);
-
- // Pull SOC_ADC_MUX_SEL High for Puddy px
- soc_adcmux_sel(true);
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- printf("board late init\n");
- run_command("mmc dev 1", 0);
- run_command("defenv", 0);
- run_command("run detect_panel", 0);
-#if 0
- //update env before anyone using it
- run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
- "if test ${reboot_mode} = factory_reset; then "\
- "defenv_reserv;save; fi;", 0);
- run_command("if itest ${upgrade_step} == 1; then "\
- "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
- /*add board late init function here*/
-#ifndef DTB_BIND_KERNEL
- int ret;
- ret = run_command("store dtb read $dtb_mem_addr", 1);
- if (ret) {
- printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
-#ifdef CONFIG_DTB_MEM_ADDR
- char cmd[64];
- printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
- sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
- ret = run_command(cmd, 1);
- if (ret) {
- printf("%s(): %s fail\n", __func__, cmd);
- }
-#endif
- }
-#elif defined(CONFIG_DTB_MEM_ADDR)
- {
- char cmd[128];
- int ret;
- if (!getenv("dtb_mem_addr")) {
- sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
- run_command(cmd, 0);
- }
- sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
- ret = run_command(cmd, 0);
- if (ret) {
- printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
- }
- }
-#endif// #ifndef DTB_BIND_KERNEL
-
- /* load unifykey */
- run_command("keyunify init 0x1234", 0);
-#endif
-/*open vpu hdmitx and cvbs driver*/
-#ifdef CONFIG_AML_VPU
- vpu_probe();
-#endif
-
-#ifdef CONFIG_AML_VPP
- vpp_init();
-#endif
-
-#ifdef CONFIG_AML_HDMITX
- hdmi_tx_init();
-#endif
-
-#ifdef CONFIG_CMD_CVBS
- run_command("cvbs init", 0);
-#endif
-
-#ifdef CONFIG_AML_LCD
- lcd_probe();
-#endif
-
-#if 0
- /**/
- aml_config_dtb();
-#endif
-#ifdef CONFIG_AML_V2_FACTORY_BURN
- if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
- aml_try_factory_usb_burning(1, gd->bd);
- aml_try_factory_sdcard_burning(0, gd->bd);
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
-
- return 0;
-}
-#endif
-
-#ifdef CONFIG_AML_TINY_USBTOOL
-int usb_get_update_result(void)
-{
- unsigned long upgrade_step;
- upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
- printf("upgrade_step = %d\n", (int)upgrade_step);
- if (upgrade_step == 1)
- {
- run_command("defenv", 1);
- run_command("setenv upgrade_step 2", 1);
- run_command("saveenv", 1);
- return 0;
- }
- else
- {
- return -1;
- }
-}
-#endif
-
-phys_size_t get_effective_memsize(void)
-{
- // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
-#if defined(CONFIG_SYS_MEM_TOP_HIDE)
- return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
-#else
- return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
-#endif
-}
-
-#ifdef CONFIG_MULTI_DTB
-int checkhw(char * name)
-{
- /*
- * read board hw id
- * set and select the dts according the board hw id.
- *
- * hwid = 1 p321 v1
- * hwid = 2 p321 v2
- */
- unsigned int hwid = 1;
- char loc_name[64] = {0};
-
- /* read hwid */
- hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
-
- printf("checkhw: hwid = %d\n", hwid);
-
-
- switch (hwid) {
- case 1:
- strcpy(loc_name, "txl_p321_v1\0");
- break;
- case 2:
- strcpy(loc_name, "txl_p321_v2\0");
- break;
- default:
- strcpy(loc_name, "txl_p321_v1");
- break;
- }
- strcpy(name, loc_name);
- setenv("aml_dt", loc_name);
- return 0;
-}
-#endif
-
-static struct mm_region bd_mem_map[] = {
- {
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = bd_mem_map;
-
-void board_nand_init(void) {
- printf("board_nand_init\n");
- return;
-}
-
-int print_cpuinfo(void) {
- printf("print_cpuinfo\n");
- return 0;
-}
-
-int mach_cpu_init(void) {
- printf("mach_cpu_init\n");
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- /* eg: bl31/32 rsv */
- return 0;
-}
-
-/* workaround for VDDEE issue */
-/* VCCK PWM table */
-#define VCCK_VAL_REG_800 0x00150007
-#define VCCK_VAL_REG_810 0x00140008
-#define VCCK_VAL_REG_820 0x00130009
-#define VCCK_VAL_REG_830 0x0012000a
-#define VCCK_VAL_REG_840 0x0011000b
-#define VCCK_VAL_REG_850 0x0010000c
-#define VCCK_VAL_REG_860 0x000f000d
-#define VCCK_VAL_REG_870 0x000e000e
-#define VCCK_VAL_REG_880 0x000d000f
-#define VCCK_VAL_REG_890 0x000c0010
-#define VCCK_VAL_REG_900 0x000b0011
-#define VCCK_VAL_REG_910 0x000a0012
-#define VCCK_VAL_REG_920 0x00090013
-#define VCCK_VAL_REG_930 0x00080014
-#define VCCK_VAL_REG_940 0x00070015
-#define VCCK_VAL_REG_950 0x00060016
-#define VCCK_VAL_REG_960 0x00050017
-#define VCCK_VAL_REG_970 0x00040018
-#define VCCK_VAL_REG_980 0x00030019
-#define VCCK_VAL_REG_990 0x0002001a
-#define VCCK_VAL_REG_1000 0x0001001b
-#define VCCK_VAL_REG_1010 0x0000001c
-#define VCCK_VAL_REG_DEFAULT1 0x00500008
-#define VCCK_VAL_REG_DEFAULT2 0x00860086
-
-
-/* VDDEE PWM table */
-#define VDDEE_VAL_REG_800 0x0010000c
-#define VDDEE_VAL_REG_810 0x000f000d
-#define VDDEE_VAL_REG_820 0x000e000e
-#define VDDEE_VAL_REG_830 0x000d000f
-#define VDDEE_VAL_REG_840 0x000c0010
-#define VDDEE_VAL_REG_850 0x000b0011
-#define VDDEE_VAL_REG_860 0x000a0012
-#define VDDEE_VAL_REG_870 0x00090013
-#define VDDEE_VAL_REG_880 0x00080014
-#define VDDEE_VAL_REG_890 0x00070015
-#define VDDEE_VAL_REG_900 0x00060016
-#define VDDEE_VAL_REG_910 0x00050017
-#define VDDEE_VAL_REG_920 0x00040018
-#define VDDEE_VAL_REG_930 0x00030019
-#define VDDEE_VAL_REG_940 0x0002001a
-#define VDDEE_VAL_REG_950 0x0001001b
-#define VDDEE_VAL_REG_960 0x0000001c
-#define VDDEE_VAL_REG_DEFAULT 0x00500008
-
-void reset_misc(void)
-{
- unsigned int value;
-
- /* adjust VDDCPU_B to Hiz value step by step */
- writel(VCCK_VAL_REG_830, AO_PWM_PWM_D);
- udelay(1);
- writel(VCCK_VAL_REG_860, AO_PWM_PWM_D);
- udelay(1);
-
- /* GPIOE_0 & GPIOE_1 & GPIOE_2 to gpio pin */
- value = readl(AO_RTI_PINMUX_REG1);
- value &= ~(0xfff << 16);
- writel(value, AO_RTI_PINMUX_REG1);
-
- /* disable pwm_ao_b - VDDEE */
- value = readl(AO_PWM_MISC_REG_AB);
- value &= ~((0x1 << 1) | (0x1 << 23));
- writel(value, AO_PWM_MISC_REG_AB);
- writel(VDDEE_VAL_REG_DEFAULT, AO_PWM_PWM_B);
-
- /* disable pwm_ao_d - VDDCPU_B*/
- value = readl(AO_PWM_MISC_REG_CD);
- value &= ~((0x1 << 1) | (0x1 << 23));
- writel(value, AO_PWM_MISC_REG_CD);
- writel(VCCK_VAL_REG_DEFAULT1, AO_PWM_PWM_D);
-
- /* disable pwm_a - VDDCPU_A */
- value = readl(P_PWM_MISC_REG_AB);
- value &= ~((0x1 << 0) | (0x1 << 15));
- writel(value, P_PWM_MISC_REG_AB);
- writel(VCCK_VAL_REG_DEFAULT2, P_PWM_PWM_A);
-}
diff --git a/board/amlogic/g12b_puddy_px/lcd.c b/board/amlogic/g12b_puddy_px/lcd.c
deleted file mode 100644
index 65d862b..0000000
--- a/board/amlogic/g12b_puddy_px/lcd.c
+++ /dev/null
@@ -1,558 +0,0 @@
-/*
- * AMLOGIC LCD panel driver.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#ifdef CONFIG_AML_LCD_EXTERN
-#include "lcd_extern.h"
-#endif
-
-static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
- "GPIOH_6", /* panel rst */
- "GPIOZ_8", /* panel power */
- "invalid", /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step[] = {
- {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,50,}, /* lcd_reset */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,50,}, /* lcd_reset */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step_TL050FHV02CT[] = {
- {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd reset: 0 */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_TL050FHV02CT[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step_TL070WSH27[] = {
- {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd reset: 0 */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_TL070WSH27[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,10,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
- 0x05, 1, 0x11,
- 0xfd, 1, 20,
- 0x05, 1, 0x29,
- 0xfd, 1, 20,
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
- 0x05, 1, 0x28,
- 0xfd, 1, 10,
- 0x05, 1, 0x10,
- 0xfd, 1, 10,
- 0xff, 0, //ending
-};
-
-static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
- 0xfd, 1, 10,
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
- 0xff, 0, //ending
-};
-
-static unsigned char mipi_init_on_table_TL050FHV02CT[DSI_INIT_ON_MAX] = {//table size < 100
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_TL050FHV02CT[DSI_INIT_OFF_MAX] = {//table size < 50
- 0xff, 0, //ending
-};
-
-static unsigned char mipi_init_on_table_TL070WSH27[DSI_INIT_ON_MAX] = {//table size < 100
- 0x05, 1, 0x11,
- 0xfd, 1, 100,
- 0x05, 1, 0x29,
- 0xfd, 1, 20,
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_TL070WSH27[DSI_INIT_OFF_MAX] = {//table size < 50
- 0x05, 1, 0x28,
- 0xfd, 1, 100,
- 0x05, 1, 0x10,
- 0xfd, 1, 10,
- 0xff, 0, //ending
-};
-
-
-static unsigned char mipi_init_on_table_TV070WSM[DSI_INIT_ON_MAX] = {//table size < 100
- 0xff, 10,
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
- 0xff, 100, /* delay */
- 0xff, 0xff, //ending flag
-};
-
-static unsigned char mipi_init_off_table_TV070WSM[DSI_INIT_OFF_MAX] = {//table size < 50
- 0xff,0xff, //ending flag
-};
-
-
-static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
- "invalid", /* ending flag */
-};
-
-struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
- {/* B080XAN01*/
- "lcd_0",LCD_MIPI,8,
- /* basic timing */
- 768,1024,948,1140,64,56,0,50,30,0,
- /* clk_attr */
- 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
- /* cmd init */
- mipi_init_on_table, mipi_init_off_table,
- /* power step */
- lcd_power_on_step, lcd_power_off_step,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* P070ACB_FT*/
- "lcd_1",LCD_MIPI,8,
- /* basic timing */
- 600,1024,770,1070,10,80,0,6,20,0,
- /* clk_attr */
- 0,0,1,49434000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,400,0,1,0,2,0,0,Rsv_val,1,
- /* cmd init */
- mipi_init_on_table_P070ACB, mipi_init_off_table_P070ACB,
- /* power step */
- lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* TL050FHV02CT*/
- "lcd_2",LCD_MIPI,8,
- /* basic timing */
- 1080,1920,1125,2100,5,30,0,44,108,0,
- /* clk_attr */
- 0,0,1,118125000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,960,0,1,0,2,1,0,Rsv_val,2,
- /* cmd init */
- mipi_init_on_table_TL050FHV02CT, mipi_init_off_table_TL050FHV02CT,
- /* power step */
- lcd_power_on_step_TL050FHV02CT, lcd_power_off_step_TL050FHV02CT,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* TL070WSH27*/
- "lcd_3",LCD_MIPI,8,
- /* basic timing */
- 1024,600,1250,630,80,100,0,5,20,0,
- /* clk_attr */
- 0,0,1,47250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,300,0,1,0,2,1,0,Rsv_val,Rsv_val,
- /* cmd init */
- mipi_init_on_table_TL070WSH27, mipi_init_off_table_TL070WSH27,
- /* power step */
- lcd_power_on_step_TL070WSH27, lcd_power_off_step_TL070WSH27,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* BOE TV101WXM*/
- "boe_nvtk_10",LCD_MIPI,8,
- /* basic timing */
- 800,1280,900,1312,24,48,0,4,12,0,
- /* clk_attr */
- 0,0,1,70956000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,568,0,1,0,2,0,0,Rsv_val,3,
- /* cmd init */
- mipi_init_on_table_TV070WSM, mipi_init_off_table_TV070WSM,
- /* power step */
- lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_MAX,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* INNOLUX G101B158 */
- "inx_nvtk_10",LCD_MIPI,8,
- /* basic timing */
- 800,1280,880,1314,18,18,0,4,10,0,
- /* clk_attr */
- 0,0,1,69380000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,560,0,1,0,2,0,0,Rsv_val,4,
- /* cmd init */
- mipi_init_on_table_P070ACB, mipi_init_off_table_P070ACB,
- /* power step */
- lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_MAX,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* BOE TV101WXM FT */
- "boe_fiti_10",LCD_MIPI,8,
- /* basic timing */
- 800,1280,890,1324,20,50,0,4,20,0,
- /* clk_attr */
- 0,0,1,70701600,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,566,0,1,0,2,0,0,Rsv_val,5,
- /* cmd init */
- mipi_init_on_table_TV070WSM, mipi_init_off_table_TV070WSM,
- /* power step */
- lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_MAX,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* INNOLUX G101B158 FT */
- "inx_fiti_10",LCD_MIPI,8,
- /* basic timing */
- 800,1280,890,1324,24,20,0,4,20,0,
- /* clk_attr */
- 0,0,1,70701600,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,566,0,1,0,2,0,0,Rsv_val,6,
- /* cmd init */
- mipi_init_on_table_P070ACB, mipi_init_off_table_P070ACB,
- /* power step */
- lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_MAX,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {.panel_type = "invalid"},
-};
-
-static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
- {
- .name = "lcd_pin",
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
- },
- {
- .name = "invalid",
- },
-};
-
-static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
- {
- .name = "invalid",
- },
-};
-
-#ifdef CONFIG_AML_BL_EXTERN
-static unsigned char bl_ext_init_on[BL_EXTERN_INIT_ON_MAX] = {
- 0xff, 0, //ending flag
-};
-static unsigned char bl_ext_init_off[BL_EXTERN_INIT_OFF_MAX] = {
- 0xff, 0, //ending flag
-};
-#endif
-
-/* **********************************************
- * driver struct, usually no need modify!
- * ********************************************** */
-static struct dsi_config_s lcd_mipi_config = {
- .lane_num = 4,
- .bit_rate_max = 1000, /* MHz */
- .factor_numerator = 0,
- .factor_denominator = 100,
- .operation_mode_init = 1, /* 0=video mode, 1=command mode */
- .operation_mode_display = 0, /* 0=video mode, 1=command mode */
- .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
- .clk_always_hs = 1, /* 0=disable, 1=enable */
- .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
-
- .dsi_init_on = mipi_init_on_table,
- .dsi_init_off = mipi_init_off_table,
- .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
- .check_en = 0,
- .check_state = 0,
-};
-
-static struct lcd_power_ctrl_s lcd_power_ctrl = {
- .power_on_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
- .power_off_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
-};
-
-struct lcd_config_s lcd_config_dft = {
- .lcd_mode = LCD_MODE_TABLET,
- .lcd_key_valid = 0,
- .lcd_clk_path = 0,
- .lcd_basic = {
- .model_name = "default",
- .lcd_type = LCD_TYPE_MAX,
- .lcd_bits = 8,
- .h_active = 768,
- .v_active = 1024,
- .h_period = 948,
- .v_period = 1140,
-
- .screen_width = 119,
- .screen_height = 159,
- },
-
- .lcd_timing = {
- .clk_auto = 1,
- .lcd_clk = 64843200,
- .ss_level = 0,
- .fr_adjust_type = 0,
-
- .hsync_width = 64,
- .hsync_bp = 56,
- .hsync_pol = 0,
- .vsync_width = 50,
- .vsync_bp = 30,
- .vsync_pol = 0,
- },
-
- .lcd_control = {
- .mipi_config= &lcd_mipi_config,
- },
- .lcd_power = &lcd_power_ctrl,
-
- .pinctrl_ver = 2,
- .lcd_pinmux = lcd_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_LCD_EXTERN
-struct lcd_extern_common_s ext_common_dft = {
- .lcd_ext_key_valid = 0,
- .i2c_bus = LCD_EXTERN_I2C_BUS_0, /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
- .i2c_gpio_sck = LCD_EXT_I2C_GPIO_SCK,
- .i2c_gpio_sda = LCD_EXT_I2C_GPIO_SDA,
- .spi_gpio_cs = LCD_EXT_SPI_GPIO_CS,
- .spi_gpio_clk = LCD_EXT_SPI_GPIO_CLK,
- .spi_gpio_data = LCD_EXT_SPI_GPIO_DATA,
-
- .lcd_ext_pinmux = lcd_ext_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
- .pinmux_gpio_off = LCD_EXT_PINMUX_GPIO_OFF,
-};
-
-struct lcd_extern_config_s ext_config_dtf = {
- .index = 0,
- .name = "ext_default",
- .type = LCD_EXTERN_MAX, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 0, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
-};
-#endif
-
-struct bl_config_s bl_config_dft = {
- .name = "default",
- .bl_key_valid = 0,
-
- .level_default = 100,
- .level_min = 10,
- .level_max = 255,
- .level_mid = 128,
- .level_mid_mapping = 128,
- .level = 0,
-
- .method = BL_CTRL_MAX,
- .power_on_delay = 20,
- .power_off_delay = 20,
-
- .en_gpio = 0xff,
- .en_gpio_on = 1,
- .en_gpio_off = 0,
-
- .bl_pwm = NULL,
- .bl_pwm_combo0 = NULL,
- .bl_pwm_combo1 = NULL,
- .pwm_on_delay = 10,
- .pwm_off_delay = 10,
-
- .bl_extern_index = 0xff,
-
- .pinctrl_ver = 2,
- .bl_pinmux = bl_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_BL_EXTERN
-struct bl_extern_config_s bl_extern_config_dtf = {
- .index = BL_EXTERN_INDEX_INVALID,
- .name = "none",
- .type = BL_EXTERN_MAX,
- .i2c_addr = 0xff,
- .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
- .dim_min = 10,
- .dim_max = 255,
-
- .init_loaded = 0,
- .cmd_size = 0xff,
- .init_on = bl_ext_init_on,
- .init_off = bl_ext_init_off,
- .init_on_cnt = sizeof(bl_ext_init_on),
- .init_off_cnt = sizeof(bl_ext_init_off),
-};
-#endif
-/* ********************************************** */
-
-void lcd_config_bsp_init(void)
-{
- int i, j;
- char *str;
- struct ext_lcd_config_s *ext_lcd = NULL;
-
- /* init config, usually no need modify */
- for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
- break;
- strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
- }
- for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
- strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
- for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
- break;
- strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
- }
- for (j = i; j < BL_GPIO_NUM_MAX; j++)
- strcpy(bl_config_dft.gpio_name[j], "invalid");
-
-#ifdef CONFIG_AML_LCD_EXTERN
- for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
- break;
- strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
- }
- for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
- strcpy(ext_common_dft.gpio_name[j], "invalid");
-#endif
-
- /* select special config */
- str = env_get("panel_type");
- if (str == NULL)
- return;
- for (i = 0 ; i < LCD_NUM_MAX ; i++) {
- ext_lcd = &ext_lcd_config[i];
- if (strcmp(ext_lcd->panel_type, str) == 0) {
-#ifdef CONFIG_AML_LCD_EXTERN
- j = ext_lcd->if_attr_val9; /* mipi extern_index */
- if (j < sizeof(ext_config)/sizeof(struct lcd_extern_config_s)) {
- memcpy(&ext_config_dtf, &ext_config[j],
- sizeof(struct lcd_extern_config_s));
- }
-#endif
- break;
- }
- }
-}
diff --git a/board/amlogic/g12b_puddy_px/lcd_extern.h b/board/amlogic/g12b_puddy_px/lcd_extern.h
deleted file mode 100644
index c0a3c2b..0000000
--- a/board/amlogic/g12b_puddy_px/lcd_extern.h
+++ /dev/null
@@ -1,1860 +0,0 @@
-/*
- * board/amlogic/g12a_u200_v1/lcd_extern.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _DFT_LCD_EXTERN_H_
-#define _DFT_LCD_EXTERN_H_
-
-#define LCD_EXT_I2C_GPIO_SCK 0xff /* 0xff for invalid */
-#define LCD_EXT_I2C_GPIO_SDA 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_CS 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_CLK 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_DATA 0xff /* 0xff for invalid */
-#define LCD_EXT_PINMUX_GPIO_OFF 0
-
-static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
- "invalid", /* ending flag */
-};
-
-static struct lcd_pinmux_ctrl_s lcd_ext_pinmux_ctrl[LCD_PINMX_MAX] = {
- {
- .name = "invalid",
- },
-};
-
-static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
- 0xff, 0, //ending flag
-};
-
-static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
- 0xff, 0, //ending flag
-};
-
-static unsigned char ext_init_on_table_P070ACB_FT[LCD_EXTERN_INIT_ON_MAX] = {
- 0x23,2,0xE0,0x00,//Page 0
- 0x23,2,0xE1,0x93,// PASSWORD
- 0x23,2,0xE2,0x65,
- 0x23,2,0xE3,0xF8,
- 0x23,2,0x80,0x03,
- 0x23,2,0xE0,0x01,//Page 01
- 0x23,2,0x0C,0x74,//Set PWRIC
- 0x23,2,0x17,0x00,//Set Gamma Power
- 0x23,2,0x18,0xEF,//VGMP=5.1V
- 0x23,2,0x19,0x00,
- 0x23,2,0x1A,0x00,
- 0x23,2,0x1B,0xEF,//VGMN=-5.1V
- 0x23,2,0x1C,0x00,
- 0x23,2,0x1F,0x70,//Set Gate Power
- 0x23,2,0x20,0x2D,
- 0x23,2,0x21,0x2D,
- 0x23,2,0x22,0x7E,
- 0x23,2,0x26,0xF3,//VDDD from IOVCC
- 0x23,2,0x37,0x09,//SetPanel
- 0x23,2,0x38,0x04,//SET RGBCYC
- 0x23,2,0x39,0x00,
- 0x23,2,0x3A,0x01,
- 0x23,2,0x3C,0x90,
- 0x23,2,0x3D,0xFF,
- 0x23,2,0x3E,0xFF,
- 0x23,2,0x3F,0xFF,
- 0x23,2,0x40,0x02,//Set TCON
- 0x23,2,0x41,0x80,
- 0x23,2,0x42,0x99,
- 0x23,2,0x43,0x14,
- 0x23,2,0x44,0x19,
- 0x23,2,0x45,0x5A,
- 0x23,2,0x4B,0x04,
- 0x23,2,0x55,0x02,//power voltage
- 0x23,2,0x56,0x01,
- 0x23,2,0x57,0x69,
- 0x23,2,0x58,0x0A,
- 0x23,2,0x59,0x0A,
- 0x23,2,0x5A,0x2E,//VGH = 16.2V
- 0x23,2,0x5B,0x19,//VGL = -12V
- 0x23,2,0x5C,0x15,
- 0x23,2,0x5D,0x77,//Gamma
- 0x23,2,0x5E,0x56,
- 0x23,2,0x5F,0x45,
- 0x23,2,0x60,0x38,
- 0x23,2,0x61,0x35,
- 0x23,2,0x62,0x27,
- 0x23,2,0x63,0x2D,
- 0x23,2,0x64,0x18,
- 0x23,2,0x65,0x33,
- 0x23,2,0x66,0x34,
- 0x23,2,0x67,0x35,
- 0x23,2,0x68,0x56,
- 0x23,2,0x69,0x45,
- 0x23,2,0x6A,0x4F,
- 0x23,2,0x6B,0x42,
- 0x23,2,0x6C,0x40,
- 0x23,2,0x6D,0x34,
- 0x23,2,0x6E,0x25,
- 0x23,2,0x6F,0x02,
- 0x23,2,0x70,0x77,
- 0x23,2,0x71,0x56,
- 0x23,2,0x72,0x45,
- 0x23,2,0x73,0x38,
- 0x23,2,0x74,0x35,
- 0x23,2,0x75,0x27,
- 0x23,2,0x76,0x2D,
- 0x23,2,0x77,0x18,
- 0x23,2,0x78,0x33,
- 0x23,2,0x79,0x34,
- 0x23,2,0x7A,0x35,
- 0x23,2,0x7B,0x56,
- 0x23,2,0x7C,0x45,
- 0x23,2,0x7D,0x4F,
- 0x23,2,0x7E,0x42,
- 0x23,2,0x7F,0x40,
- 0x23,2,0x80,0x34,
- 0x23,2,0x81,0x25,
- 0x23,2,0x82,0x02,
- 0x23,2,0xE0,0x02,//Page2
- 0x23,2,0x00,0x53,//GIP_L Pin mapping RESET_EVEN
- 0x23,2,0x01,0x55,//VSSG_EVEN
- 0x23,2,0x02,0x55,//VSSA_EVEN
- 0x23,2,0x03,0x51,//STV2_EVEN
- 0x23,2,0x04,0x77,//VDD2_EVEN
- 0x23,2,0x05,0x57,//VDD1_EVEN
- 0x23,2,0x06,0x1F,
- 0x23,2,0x07,0x4F, //CK12
- 0x23,2,0x08,0x4D, //CK10
- 0x23,2,0x09,0x1F,
- 0x23,2,0x0A,0x4B, //CK8
- 0x23,2,0x0B,0x49, //CK6
- 0x23,2,0x0C,0x1F,
- 0x23,2,0x0D,0x47, //CK4
- 0x23,2,0x0E,0x45, //CK2
- 0x23,2,0x0F,0x41, //STV1_EVEN
- 0x23,2,0x10,0x1F,
- 0x23,2,0x11,0x1F,
- 0x23,2,0x12,0x1F,
- 0x23,2,0x13,0x55, //VGG
- 0x23,2,0x14,0x1F,
- 0x23,2,0x15,0x1F,
- 0x23,2,0x16,0x52,//GIP_R Pin mapping RESET_ODD
- 0x23,2,0x17,0x55, //VSSG_ODD
- 0x23,2,0x18,0x55, //VSSA_ODD
- 0x23,2,0x19,0x50, //STV2_ODD
- 0x23,2,0x1A,0x77,//VDD2_ODD
- 0x23,2,0x1B,0x57,//VDD1_ODD
- 0x23,2,0x1C,0x1F,
- 0x23,2,0x1D,0x4E, //CK11
- 0x23,2,0x1E,0x4C, //CK9
- 0x23,2,0x1F,0x1F,
- 0x23,2,0x20,0x4A, //CK7
- 0x23,2,0x21,0x48, //CK5
- 0x23,2,0x22,0x1F,
- 0x23,2,0x23,0x46, //CK3
- 0x23,2,0x24,0x44, //CK1
- 0x23,2,0x25,0x40,//STV1_ODD
- 0x23,2,0x26,0x1F,
- 0x23,2,0x27,0x1F,
- 0x23,2,0x28,0x1F,
- 0x23,2,0x29,0x1F,
- 0x23,2,0x2A,0x1F,
- 0x23,2,0x2B,0x55, //VGG
- 0x23,2,0x2C,0x12,//GIP_L_GS Pin mapping
- 0x23,2,0x2D,0x15,
- 0x23,2,0x2E,0x15,
- 0x23,2,0x2F,0x00,
- 0x23,2,0x30,0x37,
- 0x23,2,0x31,0x17,
- 0x23,2,0x32,0x1F,
- 0x23,2,0x33,0x08,
- 0x23,2,0x34,0x0A,
- 0x23,2,0x35,0x1F,
- 0x23,2,0x36,0x0C,
- 0x23,2,0x37,0x0E,
- 0x23,2,0x38,0x1F,
- 0x23,2,0x39,0x04,
- 0x23,2,0x3A,0x06,
- 0x23,2,0x3B,0x10,
- 0x23,2,0x3C,0x1F,
- 0x23,2,0x3D,0x1F,
- 0x23,2,0x3E,0x1F,
- 0x23,2,0x3F,0x15,
- 0x23,2,0x40,0x1F,
- 0x23,2,0x41,0x1F,
- 0x23,2,0x42,0x13,//GIP_R_GS Pin mapping
- 0x23,2,0x43,0x15,
- 0x23,2,0x44,0x15,
- 0x23,2,0x45,0x01,
- 0x23,2,0x46,0x37,
- 0x23,2,0x47,0x17,
- 0x23,2,0x48,0x1F,
- 0x23,2,0x49,0x09,
- 0x23,2,0x4A,0x0B,
- 0x23,2,0x4B,0x1F,
- 0x23,2,0x4C,0x0D,
- 0x23,2,0x4D,0x0F,
- 0x23,2,0x4E,0x1F,
- 0x23,2,0x4F,0x05,
- 0x23,2,0x50,0x07,
- 0x23,2,0x51,0x11,
- 0x23,2,0x52,0x1F,
- 0x23,2,0x53,0x1F,
- 0x23,2,0x54,0x1F,
- 0x23,2,0x55,0x1F,
- 0x23,2,0x56,0x1F,
- 0x23,2,0x57,0x15,
- 0x23,2,0x58,0x40,//GIP Timing
- 0x23,2,0x59,0x00,
- 0x23,2,0x5A,0x00,
- 0x23,2,0x5B,0x10,
- 0x23,2,0x5C,0x14,
- 0x23,2,0x5D,0x40,
- 0x23,2,0x5E,0x01,
- 0x23,2,0x5F,0x02,
- 0x23,2,0x60,0x40,
- 0x23,2,0x61,0x03,
- 0x23,2,0x62,0x04,
- 0x23,2,0x63,0x7A,
- 0x23,2,0x64,0x7A,
- 0x23,2,0x65,0x74,
- 0x23,2,0x66,0x16,
- 0x23,2,0x67,0xB4,
- 0x23,2,0x68,0x16,
- 0x23,2,0x69,0x7A,
- 0x23,2,0x6A,0x7A,
- 0x23,2,0x6B,0x0C,
- 0x23,2,0x6C,0x00,
- 0x23,2,0x6D,0x04,
- 0x23,2,0x6E,0x04,
- 0x23,2,0x6F,0x88,
- 0x23,2,0x70,0x00,
- 0x23,2,0x71,0x00,
- 0x23,2,0x72,0x06,
- 0x23,2,0x73,0x7B,
- 0x23,2,0x74,0x00,
- 0x23,2,0x75,0xBC,
- 0x23,2,0x76,0x00,
- 0x23,2,0x77,0x04,
- 0x23,2,0x78,0x2C,
- 0x23,2,0x79,0x00,
- 0x23,2,0x7A,0x00,
- 0x23,2,0x7B,0x00,
- 0x23,2,0x7C,0x00,
- 0x23,2,0x7D,0x03,
- 0x23,2,0x7E,0x7B,
- 0x23,2,0xE0,0x04,//Page4
- 0x23,2,0x09,0x11,//Set RGBCYC2
- 0x23,2,0x0E,0x48,
- 0x23,2,0x2B,0x2B,//ESD Protect
- 0x23,2,0x2E,0x44,
- 0x23,2,0xE0,0x00,//Page0
- 0x23,2,0xE6,0x02,//Watch dog
- 0x23,2,0xE7,0x0C,
- 0x05,1,0x11,//sleep out
- 0xfd, 1,120,
- 0x05,1,0x29,//display on
- 0x05,1,0x35,
- 0xfd, 1, 20, /* delay(ms) */
- 0xFF, 0, /* ending flag */
-};
-
-static unsigned char ext_init_off_table_P070ACB_FT[LCD_EXTERN_INIT_OFF_MAX] = {
- 0x05, 1, 0x28, /* display off */
- 0xfd, 1, 10, /* delay 10ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xfd, 1, 150, /* delay 150ms */
- 0xFF, 0, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_TL050FHV02CT[LCD_EXTERN_INIT_ON_MAX] = {
- //LCD driver initialization
- 0x23, 2, 0XFF, 0X05,
- 0x23, 2, 0XFB, 0X01,
- 0x23, 2, 0XC5, 0X01, //TURN ON
- 0xfd, 1, 100,
-
- //AUO4.97+NT35596_intial
- 0x23, 2, 0XFF, 0XEE, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X1F, 0X45,
- 0x23, 2, 0X24, 0X4F,
- 0x23, 2, 0X38, 0XC8,
- 0x23, 2, 0X39, 0X2C,
- 0x23, 2, 0X1E, 0XBB,
- 0x23, 2, 0X1D, 0X0F,
- 0x23, 2, 0X7E, 0XB1,
-
- 0x23, 2, 0XFF, 0X00, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X35, 0X01,
-
- 0x23, 2, 0XFF, 0X01, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X00, 0X01,
- 0x23, 2, 0X01, 0X55,
- 0x23, 2, 0X02, 0X40,
- 0x23, 2, 0X05, 0X40,
- 0x23, 2, 0X06, 0X4A,
- 0x23, 2, 0X07, 0X24,
- 0x23, 2, 0X08, 0X0C,
- 0x23, 2, 0X0B, 0X87,
- 0x23, 2, 0X0C, 0X87,
- 0x23, 2, 0X0E, 0XB0,
- 0x23, 2, 0X0F, 0XB3,
- 0x23, 2, 0X11, 0X10,
- 0x23, 2, 0X12, 0X10,
- 0x23, 2, 0X13, 0X05,
- 0x23, 2, 0X14, 0X4A,
- 0x23, 2, 0X15, 0X18,
- 0x23, 2, 0X16, 0X18,
- 0x23, 2, 0X18, 0X00,
- 0x23, 2, 0X19, 0X77,
- 0x23, 2, 0X1A, 0X55,
- 0x23, 2, 0X1B, 0X13,
- 0x23, 2, 0X1C, 0X00,
- 0x23, 2, 0X1D, 0X00,
- 0x23, 2, 0X1E, 0X13,
- 0x23, 2, 0X1F, 0X00,
- 0x23, 2, 0X23, 0X00,
- 0x23, 2, 0X24, 0X00,
- 0x23, 2, 0X25, 0X00,
- 0x23, 2, 0X26, 0X00,
- 0x23, 2, 0X27, 0X00,
- 0x23, 2, 0X28, 0X00,
- 0x23, 2, 0X35, 0X00,
- 0x23, 2, 0X66, 0X00,
- 0x23, 2, 0X58, 0X82,
- 0x23, 2, 0X59, 0X02,
- 0x23, 2, 0X5A, 0X02,
- 0x23, 2, 0X5B, 0X02,
- 0x23, 2, 0X5C, 0X82,
- 0x23, 2, 0X5D, 0X82,
- 0x23, 2, 0X5E, 0X02,
- 0x23, 2, 0X5F, 0X02,
- 0x23, 2, 0X72, 0X31,
-
- 0x23, 2, 0XFF, 0X05, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X00, 0X01,
- 0x23, 2, 0X01, 0X0B,
- 0x23, 2, 0X02, 0X0C,
- 0x23, 2, 0X03, 0X09,
- 0x23, 2, 0X04, 0X0A,
- 0x23, 2, 0X05, 0X00,
- 0x23, 2, 0X06, 0X0F,
- 0x23, 2, 0X07, 0X10,
- 0x23, 2, 0X08, 0X00,
- 0x23, 2, 0X09, 0X00,
- 0x23, 2, 0X0A, 0X00,
- 0x23, 2, 0X0B, 0X00,
- 0x23, 2, 0X0C, 0X00,
- 0x23, 2, 0X0D, 0X13,
- 0x23, 2, 0X0E, 0X15,
- 0x23, 2, 0X0F, 0X17,
- 0x23, 2, 0X10, 0X01,
- 0x23, 2, 0X11, 0X0B,
- 0x23, 2, 0X12, 0X0C,
- 0x23, 2, 0X13, 0X09,
- 0x23, 2, 0X14, 0X0A,
- 0x23, 2, 0X15, 0X00,
- 0x23, 2, 0X16, 0X0F,
- 0x23, 2, 0X17, 0X10,
- 0x23, 2, 0X18, 0X00,
- 0x23, 2, 0X19, 0X00,
- 0x23, 2, 0X1A, 0X00,
- 0x23, 2, 0X1B, 0X00,
- 0x23, 2, 0X1C, 0X00,
- 0x23, 2, 0X1D, 0X13,
- 0x23, 2, 0X1E, 0X15,
- 0x23, 2, 0X1F, 0X17,
- 0x23, 2, 0X20, 0X00,
- 0x23, 2, 0X21, 0X03,
- 0x23, 2, 0X22, 0X01,
- 0x23, 2, 0X23, 0X40,
- 0x23, 2, 0X24, 0X40,
- 0x23, 2, 0X25, 0XED,
- 0x23, 2, 0X29, 0X58,
- 0x23, 2, 0X2A, 0X12,
- 0x23, 2, 0X2B, 0X01,
- 0x23, 2, 0X4B, 0X06,
- 0x23, 2, 0X4C, 0X11,
- 0x23, 2, 0X4D, 0X20,
- 0x23, 2, 0X4E, 0X02,
- 0x23, 2, 0X4F, 0X02,
- 0x23, 2, 0X50, 0X20,
- 0x23, 2, 0X51, 0X61,
- 0x23, 2, 0X52, 0X01,
- 0x23, 2, 0X53, 0X63,
- 0x23, 2, 0X54, 0X77,
- 0x23, 2, 0X55, 0XED,
- 0x23, 2, 0X5B, 0X00,
- 0x23, 2, 0X5C, 0X00,
- 0x23, 2, 0X5D, 0X00,
- 0x23, 2, 0X5E, 0X00,
- 0x23, 2, 0X5F, 0X15,
- 0x23, 2, 0X60, 0X75,
- 0x23, 2, 0X61, 0X00,
- 0x23, 2, 0X62, 0X00,
- 0x23, 2, 0X63, 0X00,
- 0x23, 2, 0X64, 0X00,
- 0x23, 2, 0X65, 0X00,
- 0x23, 2, 0X66, 0X00,
- 0x23, 2, 0X67, 0X00,
- 0x23, 2, 0X68, 0X04,
- 0x23, 2, 0X69, 0X00,
- 0x23, 2, 0X6A, 0X00,
- 0x23, 2, 0X6C, 0X40,
- 0x23, 2, 0X75, 0X01,
- 0x23, 2, 0X76, 0X01,
- 0x23, 2, 0X7A, 0X80,
- 0x23, 2, 0X7B, 0XC5,
- 0x23, 2, 0X7C, 0XD8,
- 0x23, 2, 0X7D, 0X60,
- 0x23, 2, 0X7F, 0X15,
- 0x23, 2, 0X80, 0X81,
- 0x23, 2, 0X83, 0X05,
- 0x23, 2, 0X93, 0X08,
- 0x23, 2, 0X94, 0X10,
- 0x23, 2, 0X8A, 0X00,
- 0x23, 2, 0X9B, 0X0F,
- 0x23, 2, 0XEA, 0XFF,
- 0x23, 2, 0XEC, 0X00,
-
- 0x23, 2, 0XFF, 0X01, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X75, 0X00, //Gamma R+
- 0x23, 2, 0X76, 0X18,
- 0x23, 2, 0X77, 0X00,
- 0x23, 2, 0X78, 0X38,
- 0x23, 2, 0X79, 0X00,
- 0x23, 2, 0X7A, 0X65,
- 0x23, 2, 0X7B, 0X00,
- 0x23, 2, 0X7C, 0X84,
- 0x23, 2, 0X7D, 0X00,
- 0x23, 2, 0X7E, 0X9B,
- 0x23, 2, 0X7F, 0X00,
- 0x23, 2, 0X80, 0XAF,
- 0x23, 2, 0X81, 0X00,
- 0x23, 2, 0X82, 0XC1,
- 0x23, 2, 0X83, 0X00,
- 0x23, 2, 0X84, 0XD2,
- 0x23, 2, 0X85, 0X00,
- 0x23, 2, 0X86, 0XDF,
- 0x23, 2, 0X87, 0X01,
- 0x23, 2, 0X88, 0X11,
- 0x23, 2, 0X89, 0X01,
- 0x23, 2, 0X8A, 0X38,
- 0x23, 2, 0X8B, 0X01,
- 0x23, 2, 0X8C, 0X76,
- 0x23, 2, 0X8D, 0X01,
- 0x23, 2, 0X8E, 0XA7,
- 0x23, 2, 0X8F, 0X01,
- 0x23, 2, 0X90, 0XF3,
- 0x23, 2, 0X91, 0X02,
- 0x23, 2, 0X92, 0X2F,
- 0x23, 2, 0X93, 0X02,
- 0x23, 2, 0X94, 0X30,
- 0x23, 2, 0X95, 0X02,
- 0x23, 2, 0X96, 0X66,
- 0x23, 2, 0X97, 0X02,
- 0x23, 2, 0X98, 0XA0,
- 0x23, 2, 0X99, 0X02,
- 0x23, 2, 0X9A, 0XC5,
- 0x23, 2, 0X9B, 0X02,
- 0x23, 2, 0X9C, 0XF8,
- 0x23, 2, 0X9D, 0X03,
- 0x23, 2, 0X9E, 0X1B,
- 0x23, 2, 0X9F, 0X03,
- 0x23, 2, 0XA0, 0X46,
- 0x23, 2, 0XA2, 0X03,
- 0x23, 2, 0XA3, 0X52,
- 0x23, 2, 0XA4, 0X03,
- 0x23, 2, 0XA5, 0X62,
- 0x23, 2, 0XA6, 0X03,
- 0x23, 2, 0XA7, 0X71,
- 0x23, 2, 0XA9, 0X03,
- 0x23, 2, 0XAA, 0X83,
- 0x23, 2, 0XAB, 0X03,
- 0x23, 2, 0XAC, 0X94,
- 0x23, 2, 0XAD, 0X03,
- 0x23, 2, 0XAE, 0XA3,
- 0x23, 2, 0XAF, 0X03,
- 0x23, 2, 0XB0, 0XAD,
- 0x23, 2, 0XB1, 0X03,
- 0x23, 2, 0XB2, 0XCC,
-
- 0x23, 2, 0XB3, 0X00, //Gamma R-
- 0x23, 2, 0XB4, 0X18,
- 0x23, 2, 0XB5, 0X00,
- 0x23, 2, 0XB6, 0X38,
- 0x23, 2, 0XB7, 0X00,
- 0x23, 2, 0XB8, 0X65,
- 0x23, 2, 0XB9, 0X00,
- 0x23, 2, 0XBA, 0X84,
- 0x23, 2, 0XBB, 0X00,
- 0x23, 2, 0XBC, 0X9B,
- 0x23, 2, 0XBD, 0X00,
- 0x23, 2, 0XBE, 0XAF,
- 0x23, 2, 0XBF, 0X00,
- 0x23, 2, 0XC0, 0XC1,
- 0x23, 2, 0XC1, 0X00,
- 0x23, 2, 0XC2, 0XD2,
- 0x23, 2, 0XC3, 0X00,
- 0x23, 2, 0XC4, 0XDF,
- 0x23, 2, 0XC5, 0X01,
- 0x23, 2, 0XC6, 0X11,
- 0x23, 2, 0XC7, 0X01,
- 0x23, 2, 0XC8, 0X38,
- 0x23, 2, 0XC9, 0X01,
- 0x23, 2, 0XCA, 0X76,
- 0x23, 2, 0XCB, 0X01,
- 0x23, 2, 0XCC, 0XA7,
- 0x23, 2, 0XCD, 0X01,
- 0x23, 2, 0XCE, 0XF3,
- 0x23, 2, 0XCF, 0X02,
- 0x23, 2, 0XD0, 0X2F,
- 0x23, 2, 0XD1, 0X02,
- 0x23, 2, 0XD2, 0X30,
- 0x23, 2, 0XD3, 0X02,
- 0x23, 2, 0XD4, 0X66,
- 0x23, 2, 0XD5, 0X02,
- 0x23, 2, 0XD6, 0XA0,
- 0x23, 2, 0XD7, 0X02,
- 0x23, 2, 0XD8, 0XC5,
- 0x23, 2, 0XD9, 0X02,
- 0x23, 2, 0XDA, 0XF8,
- 0x23, 2, 0XDB, 0X03,
- 0x23, 2, 0XDC, 0X1B,
- 0x23, 2, 0XDD, 0X03,
- 0x23, 2, 0XDE, 0X46,
- 0x23, 2, 0XDF, 0X03,
- 0x23, 2, 0XE0, 0X52,
- 0x23, 2, 0XE1, 0X03,
- 0x23, 2, 0XE2, 0X62,
- 0x23, 2, 0XE3, 0X03,
- 0x23, 2, 0XE4, 0X71,
- 0x23, 2, 0XE5, 0X03,
- 0x23, 2, 0XE6, 0X83,
- 0x23, 2, 0XE7, 0X03,
- 0x23, 2, 0XE8, 0X94,
- 0x23, 2, 0XE9, 0X03,
- 0x23, 2, 0XEA, 0XA3,
- 0x23, 2, 0XEB, 0X03,
- 0x23, 2, 0XEC, 0XAD,
- 0x23, 2, 0XED, 0X03,
- 0x23, 2, 0XEE, 0XCC,
-
- 0x23, 2, 0XEF, 0X00, //Gamma G+
- 0x23, 2, 0XF0, 0X18,
- 0x23, 2, 0XF1, 0X00,
- 0x23, 2, 0XF2, 0X38,
- 0x23, 2, 0XF3, 0X00,
- 0x23, 2, 0XF4, 0X65,
- 0x23, 2, 0XF5, 0X00,
- 0x23, 2, 0XF6, 0X84,
- 0x23, 2, 0XF7, 0X00,
- 0x23, 2, 0XF8, 0X9B,
- 0x23, 2, 0XF9, 0X00,
- 0x23, 2, 0XFA, 0XAF,
- 0x23, 2, 0XFF, 0X02, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X00, 0X00,
- 0x23, 2, 0X01, 0XC1,
- 0x23, 2, 0X02, 0X00,
- 0x23, 2, 0X03, 0XD2,
- 0x23, 2, 0X04, 0X00,
- 0x23, 2, 0X05, 0XDF,
- 0x23, 2, 0X06, 0X01,
- 0x23, 2, 0X07, 0X11,
- 0x23, 2, 0X08, 0X01,
- 0x23, 2, 0X09, 0X38,
- 0x23, 2, 0X0A, 0X01,
- 0x23, 2, 0X0B, 0X76,
- 0x23, 2, 0X0C, 0X01,
- 0x23, 2, 0X0D, 0XA7,
- 0x23, 2, 0X0E, 0X01,
- 0x23, 2, 0X0F, 0XF3,
- 0x23, 2, 0X10, 0X02,
- 0x23, 2, 0X11, 0X2F,
- 0x23, 2, 0X12, 0X02,
- 0x23, 2, 0X13, 0X30,
- 0x23, 2, 0X14, 0X02,
- 0x23, 2, 0X15, 0X66,
- 0x23, 2, 0X16, 0X02,
- 0x23, 2, 0X17, 0XA0,
- 0x23, 2, 0X18, 0X02,
- 0x23, 2, 0X19, 0XC5,
- 0x23, 2, 0X1A, 0X02,
- 0x23, 2, 0X1B, 0XF8,
- 0x23, 2, 0X1C, 0X03,
- 0x23, 2, 0X1D, 0X1B,
- 0x23, 2, 0X1E, 0X03,
- 0x23, 2, 0X1F, 0X46,
- 0x23, 2, 0X20, 0X03,
- 0x23, 2, 0X21, 0X52,
- 0x23, 2, 0X22, 0X03,
- 0x23, 2, 0X23, 0X62,
- 0x23, 2, 0X24, 0X03,
- 0x23, 2, 0X25, 0X71,
- 0x23, 2, 0X26, 0X03,
- 0x23, 2, 0X27, 0X83,
- 0x23, 2, 0X28, 0X03,
- 0x23, 2, 0X29, 0X94,
- 0x23, 2, 0X2A, 0X03,
- 0x23, 2, 0X2B, 0XA3,
- 0x23, 2, 0X2D, 0X03,
- 0x23, 2, 0X2F, 0XAD,
- 0x23, 2, 0X30, 0X03,
- 0x23, 2, 0X31, 0XCC,
-
- 0x23, 2, 0X32, 0X00, //Gamma G-
- 0x23, 2, 0X33, 0X18,
- 0x23, 2, 0X34, 0X00,
- 0x23, 2, 0X35, 0X38,
- 0x23, 2, 0X36, 0X00,
- 0x23, 2, 0X37, 0X65,
- 0x23, 2, 0X38, 0X00,
- 0x23, 2, 0X39, 0X84,
- 0x23, 2, 0X3A, 0X00,
- 0x23, 2, 0X3B, 0X9B,
- 0x23, 2, 0X3D, 0X00,
- 0x23, 2, 0X3F, 0XAF,
- 0x23, 2, 0X40, 0X00,
- 0x23, 2, 0X41, 0XC1,
- 0x23, 2, 0X42, 0X00,
- 0x23, 2, 0X43, 0XD2,
- 0x23, 2, 0X44, 0X00,
- 0x23, 2, 0X45, 0XDF,
- 0x23, 2, 0X46, 0X01,
- 0x23, 2, 0X47, 0X11,
- 0x23, 2, 0X48, 0X01,
- 0x23, 2, 0X49, 0X38,
- 0x23, 2, 0X4A, 0X01,
- 0x23, 2, 0X4B, 0X76,
- 0x23, 2, 0X4C, 0X01,
- 0x23, 2, 0X4D, 0XA7,
- 0x23, 2, 0X4E, 0X01,
- 0x23, 2, 0X4F, 0XF3,
- 0x23, 2, 0X50, 0X02,
- 0x23, 2, 0X51, 0X2F,
- 0x23, 2, 0X52, 0X02,
- 0x23, 2, 0X53, 0X30,
- 0x23, 2, 0X54, 0X02,
- 0x23, 2, 0X55, 0X66,
- 0x23, 2, 0X56, 0X02,
- 0x23, 2, 0X58, 0XA0,
- 0x23, 2, 0X59, 0X02,
- 0x23, 2, 0X5A, 0XC5,
- 0x23, 2, 0X5B, 0X02,
- 0x23, 2, 0X5C, 0XF8,
- 0x23, 2, 0X5D, 0X03,
- 0x23, 2, 0X5E, 0X1B,
- 0x23, 2, 0X5F, 0X03,
- 0x23, 2, 0X60, 0X46,
- 0x23, 2, 0X61, 0X03,
- 0x23, 2, 0X62, 0X52,
- 0x23, 2, 0X63, 0X03,
- 0x23, 2, 0X64, 0X62,
- 0x23, 2, 0X65, 0X03,
- 0x23, 2, 0X66, 0X71,
- 0x23, 2, 0X67, 0X03,
- 0x23, 2, 0X68, 0X83,
- 0x23, 2, 0X69, 0X03,
- 0x23, 2, 0X6A, 0X94,
- 0x23, 2, 0X6B, 0X03,
- 0x23, 2, 0X6C, 0XA3,
- 0x23, 2, 0X6D, 0X03,
- 0x23, 2, 0X6E, 0XAD,
- 0x23, 2, 0X6F, 0X03,
- 0x23, 2, 0X70, 0XCC,
-
- 0x23, 2, 0X71, 0X00, //Gamma B+
- 0x23, 2, 0X72, 0X18,
- 0x23, 2, 0X73, 0X00,
- 0x23, 2, 0X74, 0X38,
- 0x23, 2, 0X75, 0X00,
- 0x23, 2, 0X76, 0X65,
- 0x23, 2, 0X77, 0X00,
- 0x23, 2, 0X78, 0X84,
- 0x23, 2, 0X79, 0X00,
- 0x23, 2, 0X7A, 0X9B,
- 0x23, 2, 0X7B, 0X00,
- 0x23, 2, 0X7C, 0XAF,
- 0x23, 2, 0X7D, 0X00,
- 0x23, 2, 0X7E, 0XC1,
- 0x23, 2, 0X7F, 0X00,
- 0x23, 2, 0X80, 0XD2,
- 0x23, 2, 0X81, 0X00,
- 0x23, 2, 0X82, 0XDF,
- 0x23, 2, 0X83, 0X01,
- 0x23, 2, 0X84, 0X11,
- 0x23, 2, 0X85, 0X01,
- 0x23, 2, 0X86, 0X38,
- 0x23, 2, 0X87, 0X01,
- 0x23, 2, 0X88, 0X76,
- 0x23, 2, 0X89, 0X01,
- 0x23, 2, 0X8A, 0XA7,
- 0x23, 2, 0X8B, 0X01,
- 0x23, 2, 0X8C, 0XF3,
- 0x23, 2, 0X8D, 0X02,
- 0x23, 2, 0X8E, 0X2F,
- 0x23, 2, 0X8F, 0X02,
- 0x23, 2, 0X90, 0X30,
- 0x23, 2, 0X91, 0X02,
- 0x23, 2, 0X92, 0X66,
- 0x23, 2, 0X93, 0X02,
- 0x23, 2, 0X94, 0XA0,
- 0x23, 2, 0X95, 0X02,
- 0x23, 2, 0X96, 0XC5,
- 0x23, 2, 0X97, 0X02,
- 0x23, 2, 0X98, 0XF8,
- 0x23, 2, 0X99, 0X03,
- 0x23, 2, 0X9A, 0X1B,
- 0x23, 2, 0X9B, 0X03,
- 0x23, 2, 0X9C, 0X46,
- 0x23, 2, 0X9D, 0X03,
- 0x23, 2, 0X9E, 0X52,
- 0x23, 2, 0X9F, 0X03,
- 0x23, 2, 0XA0, 0X62,
- 0x23, 2, 0XA2, 0X03,
- 0x23, 2, 0XA3, 0X71,
- 0x23, 2, 0XA4, 0X03,
- 0x23, 2, 0XA5, 0X83,
- 0x23, 2, 0XA6, 0X03,
- 0x23, 2, 0XA7, 0X94,
- 0x23, 2, 0XA9, 0X03,
- 0x23, 2, 0XAA, 0XA3,
- 0x23, 2, 0XAB, 0X03,
- 0x23, 2, 0XAC, 0XAD,
- 0x23, 2, 0XAD, 0X03,
- 0x23, 2, 0XAE, 0XCC,
-
- 0x23, 2, 0XAF, 0X00, //Gamma B-
- 0x23, 2, 0XB0, 0X18,
- 0x23, 2, 0XB1, 0X00,
- 0x23, 2, 0XB2, 0X38,
- 0x23, 2, 0XB3, 0X00,
- 0x23, 2, 0XB4, 0X65,
- 0x23, 2, 0XB5, 0X00,
- 0x23, 2, 0XB6, 0X84,
- 0x23, 2, 0XB7, 0X00,
- 0x23, 2, 0XB8, 0X9B,
- 0x23, 2, 0XB9, 0X00,
- 0x23, 2, 0XBA, 0XAF,
- 0x23, 2, 0XBB, 0X00,
- 0x23, 2, 0XBC, 0XC1,
- 0x23, 2, 0XBD, 0X00,
- 0x23, 2, 0XBE, 0XD2,
- 0x23, 2, 0XBF, 0X00,
- 0x23, 2, 0XC0, 0XDF,
- 0x23, 2, 0XC1, 0X01,
- 0x23, 2, 0XC2, 0X11,
- 0x23, 2, 0XC3, 0X01,
- 0x23, 2, 0XC4, 0X38,
- 0x23, 2, 0XC5, 0X01,
- 0x23, 2, 0XC6, 0X76,
- 0x23, 2, 0XC7, 0X01,
- 0x23, 2, 0XC8, 0XA7,
- 0x23, 2, 0XC9, 0X01,
- 0x23, 2, 0XCA, 0XF3,
- 0x23, 2, 0XCB, 0X02,
- 0x23, 2, 0XCC, 0X2F,
- 0x23, 2, 0XCD, 0X02,
- 0x23, 2, 0XCE, 0X30,
- 0x23, 2, 0XCF, 0X02,
- 0x23, 2, 0XD0, 0X66,
- 0x23, 2, 0XD1, 0X02,
- 0x23, 2, 0XD2, 0XA0,
- 0x23, 2, 0XD3, 0X02,
- 0x23, 2, 0XD4, 0XC5,
- 0x23, 2, 0XD5, 0X02,
- 0x23, 2, 0XD6, 0XF8,
- 0x23, 2, 0XD7, 0X03,
- 0x23, 2, 0XD8, 0X1B,
- 0x23, 2, 0XD9, 0X03,
- 0x23, 2, 0XDA, 0X46,
- 0x23, 2, 0XDB, 0X03,
- 0x23, 2, 0XDC, 0X52,
- 0x23, 2, 0XDD, 0X03,
- 0x23, 2, 0XDE, 0X62,
- 0x23, 2, 0XDF, 0X03,
- 0x23, 2, 0XE0, 0X71,
- 0x23, 2, 0XE1, 0X03,
- 0x23, 2, 0XE2, 0X83,
- 0x23, 2, 0XE3, 0X03,
- 0x23, 2, 0XE4, 0X94,
- 0x23, 2, 0XE5, 0X03,
- 0x23, 2, 0XE6, 0XA3,
- 0x23, 2, 0XE7, 0X03,
- 0x23, 2, 0XE8, 0XAD,
- 0x23, 2, 0XE9, 0X03,
- 0x23, 2, 0XEA, 0XCC,
-
- 0x23, 2, 0XFF, 0X01, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0XFF, 0X02, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0XFF, 0X04, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0XFF, 0X00, //CMD page select
-
- 0x23, 2, 0XD3, 0X05,
- 0x23, 2, 0XD4, 0X04,
-
- 0x23, 2, 0X11, 0X00, //Sleep out
- 0xfd, 1, 100, //delay 100ms
- 0x23, 2, 0XFF, 0X00,
-
- 0x23, 2, 0X35, 0X00, //TE on
-
- 0x23, 2, 0X29, 0X00, //Display on
- 0xfd, 1, 100, //delay 100ms
- 0xff, 0, /* ending flag */
-};
-
-static unsigned char ext_init_off_table_TL050FHV02CT[LCD_EXTERN_INIT_OFF_MAX] = {
- 0x05, 1, 0x28, /* display off */
- 0xfd, 1, 10, /* delay 10ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xfd, 1, 150, /* delay 150ms */
- 0xFF, 0, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_TV101WXM[LCD_EXTERN_INIT_ON_MAX] = {
- 0xFF, 120,
- 0x29, 5, 0xFF, 0xAA, 0x55, 0x25, 0x01,
- 0x23, 2, 0xFC, 0x08,
- 0xFF, 1,
- 0x23, 2, 0xFC, 0x00,
- 0x29, 5, 0xFF, 0xAA, 0x55, 0x25, 0x00,
- 0xFF, 20,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x00,
- 0x29, 3, 0xB1, 0x68, 0x01,
- 0x29, 5, 0xB8, 0x01, 0x02, 0x02, 0x02,
- 0x23, 2, 0xB6, 0x11,
- 0x29, 3, 0xBB, 0x63, 0x63,
- 0x29, 3, 0xBC, 0x00, 0x00,
- 0x29, 6, 0xBD, 0x02, 0xBB, 0x11, 0x10, 0x00,
- 0x23, 2, 0xC8, 0x80,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x01,
- 0x29, 3, 0xB3, 0x28, 0x28,
- 0x29, 3, 0xB4, 0x14, 0x14,
- 0x29, 3, 0xB9, 0x44, 0x44,
- 0x29, 3, 0xBA, 0x24, 0x24,
- 0x29, 3, 0xBC, 0x70, 0x00,
- 0x29, 3, 0xBD, 0x70, 0x00,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x02,
- 0x23, 2, 0xEE, 0x03,
- 0x29, 17, 0xB0, 0x01, 0x04, 0x01, 0x08, 0x01, 0x11, 0x01, 0x19, 0x01, 0x21, 0x01, 0x30, 0x01, 0x3D, 0x01, 0x55,
- 0x29, 17, 0xB1, 0x01, 0x6B, 0x01, 0x94, 0x01, 0xB5, 0x01, 0xED, 0x02, 0x20, 0x02, 0x22, 0x02, 0x53, 0x02, 0x8F,
- 0x29, 17, 0xB2, 0x02, 0xB4, 0x02, 0xE5, 0x03, 0x03, 0x03, 0x30, 0x03, 0x51, 0x03, 0x76, 0x03, 0x96, 0x03, 0xB8,
- 0x29, 5, 0xB3, 0x03, 0xCF, 0x03, 0xD2,
- 0x29, 17, 0xB4, 0x00, 0x00, 0x00, 0x13, 0x00, 0x31, 0x00, 0x4B, 0x00, 0x61, 0x00, 0x87, 0x00, 0xA7, 0x00, 0xDB,
- 0x29, 17, 0xB5, 0x01, 0x04, 0x01, 0x43, 0x01, 0x76, 0x01, 0xC9, 0x02, 0x05, 0x02, 0x06, 0x02, 0x3F, 0x02, 0x7D,
- 0x29, 17, 0xB6, 0x02, 0xA3, 0x02, 0xD3, 0x02, 0xF6, 0x03, 0x23, 0x03, 0x44, 0x03, 0x6C, 0x03, 0x8A, 0x03, 0xAE,
- 0x29, 5, 0xB7, 0x03, 0xCF, 0x03, 0xD2,
- 0x29, 17, 0xB8, 0x00, 0x41, 0x00, 0x4A, 0x00, 0x5D, 0x00, 0x6D, 0x00, 0x7E, 0x00, 0x9A, 0x00, 0xB4, 0x00, 0xDF,
- 0x29, 17, 0xB9, 0x01, 0x04, 0x01, 0x43, 0x01, 0x74, 0x01, 0xC6, 0x02, 0x03, 0x02, 0x09, 0x02, 0x40, 0x02, 0x7E,
- 0x29, 17, 0xBA, 0x02, 0xA4, 0x02, 0xD6, 0x02, 0xF7, 0x03, 0x25, 0x03, 0x44, 0x03, 0x6C, 0x03, 0x88, 0x03, 0xA8,
- 0x29, 5, 0xBB, 0x03, 0xD0, 0x03, 0xD2,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x03,
- 0x29, 3, 0xB0, 0x00, 0x00,
- 0x29, 3, 0xB1, 0x00, 0x00,
- 0x29, 6, 0xB2, 0x05, 0x01, 0x55, 0x00, 0x1A,
- 0x29, 6, 0xB3, 0x05, 0x01, 0x55, 0x00, 0x1A,
- 0x29, 6, 0xBA, 0x53, 0x01, 0x55, 0x00, 0x3A,
- 0x23, 2, 0xC4, 0x60,
- 0x23, 2, 0xC5, 0x40,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x04,
- 0x29, 5, 0xB1, 0x03, 0x02, 0x05, 0x07,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x05,
- 0x29, 6, 0xBD, 0x01, 0x03, 0x00, 0x00, 0x03,
- 0x23, 2, 0xC0, 0x09,
- 0x23, 2, 0xC1, 0x07,
- 0x29, 3, 0xC8, 0x07, 0x38,
- 0x23, 2, 0xD0, 0x00,
- 0x23, 2, 0xE5, 0x03,
- 0x23, 2, 0xE6, 0x03,
- 0x23, 2, 0xE9, 0x03,
- 0x23, 2, 0xEA, 0x03,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x06,
- 0x29, 3, 0xB0, 0x2D, 0x2D,
- 0x29, 3, 0xB1, 0x01, 0x01,
- 0x29, 3, 0xB2, 0x03, 0x03,
- 0x29, 3, 0xB3, 0x2E, 0x2E,
- 0x29, 3, 0xB4, 0x2E, 0x2D,
- 0x29, 3, 0xB5, 0x2D, 0x13,
- 0x29, 3, 0xB6, 0x13, 0x11,
- 0x29, 3, 0xB7, 0x11, 0x36,
- 0x29, 3, 0xB8, 0x36, 0x15,
- 0x29, 3, 0xB9, 0x15, 0x2E,
- 0x29, 3, 0xBA, 0x2E, 0x14,
- 0x29, 3, 0xBB, 0x14, 0x35,
- 0x29, 3, 0xBC, 0x35, 0x10,
- 0x29, 3, 0xBD, 0x10, 0x12,
- 0x29, 3, 0xBE, 0x12, 0x2D,
- 0x29, 3, 0xBF, 0x2D, 0x2E,
- 0x29, 3, 0xC0, 0x2E, 0x2E,
- 0x29, 3, 0xC1, 0x02, 0x02,
- 0x29, 3, 0xC2, 0x00, 0x00,
- 0x29, 3, 0xC3, 0x2D, 0x2D,
- 0x29, 3, 0xE5, 0x34, 0x34,
- 0x29, 3, 0xC4, 0x2E, 0x2E,
- 0x29, 3, 0xC5, 0x02, 0x02,
- 0x29, 3, 0xC6, 0x00, 0x00,
- 0x29, 3, 0xC7, 0x2D, 0x2D,
- 0x29, 3, 0xC8, 0x2E, 0x2D,
- 0x29, 3, 0xC9, 0x2D, 0x14,
- 0x29, 3, 0xCA, 0x14, 0x35,
- 0x29, 3, 0xCB, 0x35, 0x10,
- 0x29, 3, 0xCC, 0x10, 0x12,
- 0x29, 3, 0xCD, 0x12, 0x2E,
- 0x29, 3, 0xCE, 0x2E, 0x13,
- 0x29, 3, 0xCF, 0x13, 0x11,
- 0x29, 3, 0xD0, 0x11, 0x36,
- 0x29, 3, 0xD1, 0x36, 0x15,
- 0x29, 3, 0xD2, 0x15, 0x2D,
- 0x29, 3, 0xD3, 0x2D, 0x2E,
- 0x29, 3, 0xD4, 0x2D, 0x2D,
- 0x29, 3, 0xD5, 0x01, 0x01,
- 0x29, 3, 0xD6, 0x03, 0x03,
- 0x29, 3, 0xD7, 0x2E, 0x2E,
- 0x29, 3, 0xE6, 0x34, 0x34,
- 0x29, 6, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x29, 6, 0xD9, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x00, 0x00,
- 0x23, 2, 0x35, 0x00,
- 0x13, 1, 0x11,
- 0xFF, 120,
- 0x13, 1, 0x29,
-
- 0xFF, 0xFF,
-};
-
-static unsigned char ext_init_off_table_TV101WXM[] = {
- 0x05, 1, 0x28, /* display off */
- 0xFF, 10, /* delay 10ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xFF, 150, /* delay 150ms */
- 0xFF, 0xFF, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_G101B158[LCD_EXTERN_INIT_ON_MAX] = {
- 0xff, 120, /* delay */
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x00,
- 0x29, 3, 0xB1,0x68,0x01,
- 0x15, 2, 0xB5,0xC8,
- 0x29, 6, 0xBD,0x02,0xB0,0x10,0x10,0x00,
-
- 0x15, 2, 0xBC,0x05,
- 0x15, 2, 0xC7,0x00,
- 0x15, 2, 0xC8,0x80,
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x01,
- 0x29, 3, 0xB3,0x2D,0x2D,
- 0x29, 3, 0xB4,0x19,0x19,
- 0x15, 2, 0xB5,0x06,
- 0x29, 3, 0xB9,0x35,0x35,
- 0x29, 3, 0xBA,0x25,0x25,
- 0x29, 3, 0xBC,0x90,0x00,
- 0x29, 3, 0xBD,0x90,0x00,
-
- 0x15, 2, 0xC0,0x0C,
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x02,
- 0x15, 2, 0xEE,0x02,
-
- 0x29, 7, 0xB0,0x00,0x00,0x00,0x32,0x00,0x64,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xB0,0x00,0x83,0x00,0x9C,0x00,0xC3,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xB0,0x00,0xDF,0x01,0x0E,
-
- 0x29, 7, 0xB1,0x01,0x33,0x01,0x6C,0x01,0x99,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xB1,0x01,0xDF,0x02,0x18,0x02,0x1A,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xB1,0x02,0x4E,0x02,0x87,
-
- 0x29, 7, 0xB2,0x02,0xAC,0x02,0xDB,0x02,0xFC,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xB2,0x03,0x24,0x03,0x46,0x03,0x71,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xB2,0x03,0x8C,0x03,0xB1,
-
- 0x29, 5, 0xB3,0x03,0xED,0x03,0Xff,
-
- 0x29, 7, 0xBC,0x00,0x00,0x00,0x32,0x00,0x64,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xBC,0x00,0x83,0x00,0x9C,0x00,0xC3,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xBC,0x00,0xDF,0x01,0x0E,
-
- 0x29, 7, 0xBD,0x01,0x33,0x01,0x6C,0x01,0x99,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xBD,0x01,0xDF,0x02,0x18,0x02,0x1A,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xBD,0x02,0x4E,0x02,0x87,
-
- 0x29, 7, 0xBE,0x02,0xAC,0x02,0xDB,0x02,0xFC,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xBE,0x03,0x24,0x03,0x46,0x03,0x71,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xBE,0x03,0x8C,0x03,0xB1,
-
- 0x29, 5, 0xBF,0x03,0xED,0x03,0xFF,
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x03,
- 0x29, 6, 0xB2,0x05,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xB6,0x05,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xB7,0x05,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xBA,0x57,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xBB,0x57,0x00,0x00,0x00,0x00,
- 0x29, 5, 0xC0,0x00,0x34,0x00,0x00,
- 0x29, 5, 0xC1,0x00,0x00,0x34,0x00,
- 0x15, 2, 0xC4,0x40,
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x04,
- 0x29, 4, 0xB1,0x03,0x02,0x05,
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x05,
- 0x29, 3, 0xB0,0x17,0x06,
- 0x29, 3, 0xB1,0x17,0x06,
- 0x29, 3, 0xB2,0x17,0x06,
- 0x29, 3, 0xB3,0x17,0x06,
- 0x29, 3, 0xB4,0x17,0x06,
- 0x15, 2, 0xBB,0x02,
- 0x29, 6, 0xBD,0x03,0x01,0x03,0x03,0x01,
- 0x15, 2, 0xC0,0x05,
-
- 0x15, 2, 0xC4,0x82,
- 0x15, 2, 0xC5,0xA2,
- 0x29, 3, 0xC8,0x03,0x30,
- 0x29, 3, 0xC9,0x03,0x31,
-
- 0x29, 4, 0xCC,0x00,0x00,0x3C,
- 0x29, 4, 0xCD,0x00,0x00,0x3C,
-
- 0x29, 6, 0xD1,0x00,0x05,0x07,0x00,0x00,
- 0x29, 6, 0xD2,0x00,0x25,0x09,0x00,0x00,
-
- 0x15, 2, 0xE5,0x06,
- 0x15, 2, 0xE6,0x06,
- 0x15, 2, 0xE7,0x06,
- 0x15, 2, 0xE8,0x06,
- 0x15, 2, 0xE9,0x06,
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x06,
- 0x29, 3, 0xB0,0x0A,0x2D,
- 0x29, 3, 0xB1,0x2D,0x08,
- 0x29, 3, 0xB2,0x2A,0x29,
- 0x29, 3, 0xB3,0x34,0x1A,
- 0x29, 3, 0xB4,0x18,0x16,
- 0x29, 3, 0xB5,0x14,0x12,
- 0x29, 3, 0xB6,0x10,0x00,
- 0x29, 3, 0xB7,0x34,0x34,
- 0x29, 3, 0xB8,0x32,0x34,
- 0x29, 3, 0xB9,0x34,0x34,
- 0x29, 3, 0xBA,0x34,0x34,
- 0x29, 3, 0xBB,0x34,0x34,
- 0x29, 3, 0xBC,0x34,0x34,
- 0x29, 3, 0xBD,0x01,0x11,
- 0x29, 3, 0xBE,0x13,0x15,
- 0x29, 3, 0xBF,0x17,0x19,
- 0x29, 3, 0xC0,0x1B,0x34,
- 0x29, 3, 0xC1,0x29,0x2A,
- 0x29, 3, 0xC2,0x09,0x2D,
- 0x29, 3, 0xC3,0x2D,0x0B,
- 0x29, 3, 0xC4,0x0B,0x2D,
- 0x29, 3, 0xC5,0x2D,0x01,
- 0x29, 3, 0xC6,0x2A,0x29,
- 0x29, 3, 0xC7,0x34,0x19,
- 0x29, 3, 0xC8,0x1B,0x11,
- 0x29, 3, 0xC9,0x13,0x15,
- 0x29, 3, 0xCA,0x17,0x09,
- 0x29, 3, 0xCB,0x34,0x34,
- 0x29, 3, 0xCC,0x34,0x34,
- 0x29, 3, 0xCD,0x34,0x34,
- 0x29, 3, 0xCE,0x34,0x34,
- 0x29, 3, 0xCF,0x34,0x34,
- 0x29, 3, 0xD0,0x34,0x34,
- 0x29, 3, 0xD1,0x08,0x16,
- 0x29, 3, 0xD2,0x14,0x12,
- 0x29, 3, 0xD3,0x10,0x1A,
- 0x29, 3, 0xD4,0x18,0x34,
- 0x29, 3, 0xD5,0x29,0x2A,
- 0x29, 3, 0xD6,0x00,0x2D,
- 0x29, 3, 0xD7,0x2D,0x0A,
-
- 0x29, 6, 0xD8,0x00,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xD9,0x00,0x00,0x00,0x00,0x00,
-
- 0x29, 3, 0xE5,0x34,0x34,
- 0x29, 3, 0xE6,0x34,0x34,
-
- 0x15, 2, 0xE7,0x00,
- 0x29, 3, 0xE8,0x34,0x34,
- 0x29, 3, 0xE9,0x34,0x34,
- 0x15, 2, 0xEA,0x00,
-
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x00,0x00,
-
- 0x23, 2, 0x35,0x00,
-
-#if 1
- 0x13, 1, 0x11,
- 0xff, 150,
- 0x13, 1, 0x29,
-#else //bist mode
- 0xff, 150,
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x00,
- 0xff, 10,
- 0x29, 5, 0xEE,0x87,0x78,0x02,0x40,
- 0xff, 10,
- 0x29, 6, 0xEF,0x00,0x07,0xFF,0xFF,0x00,
-#endif
- 0xff, 20,
- 0xFF, 0xFF, /* ending flag */
-
-};
-
-static unsigned char ext_init_off_table_G101B158[] = {
- 0x05, 1, 0x28, /* display off */
- 0xFF, 10, /* delay 10ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xFF, 150, /* delay 150ms */
- 0xFF, 0xFF, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_TV101WXM_FT[LCD_EXTERN_INIT_ON_MAX] = {
- 0xFF, 120,
- 0x23, 2, 0xE0, 0x00,
- 0x23, 2, 0xE1, 0x93,
- 0x23, 2, 0xE2, 0x65,
- 0x23, 2, 0xE3, 0xF8,
- 0x23, 2, 0x80, 0x03,
- 0x23, 2, 0xE0, 0x01,
- 0x23, 2, 0x00, 0x00,
- 0x23, 2, 0x01, 0x6F,
- 0x23, 2, 0x17, 0x00,
- 0x23, 2, 0x18, 0xAF,
- 0x23, 2, 0x19, 0x01,
- 0x23, 2, 0x1A, 0x00,
- 0x23, 2, 0x1B, 0xAF,
- 0x23, 2, 0x1C, 0x01,
- 0x23, 2, 0x1F, 0x3E,
- 0x23, 2, 0x20, 0x28,
- 0x23, 2, 0x21, 0x28,
- 0x23, 2, 0x22, 0x7E,
- 0x23, 2, 0x35, 0x26,
- 0x23, 2, 0x37, 0x09,
- 0x23, 2, 0x38, 0x04,
- 0x23, 2, 0x39, 0x00,
- 0x23, 2, 0x3A, 0x01,
- 0x23, 2, 0x3C, 0x78,
- 0x23, 2, 0x3D, 0xFF,
- 0x23, 2, 0x3E, 0xFF,
- 0x23, 2, 0x3F, 0x7F,
- 0x23, 2, 0x40, 0x06,
- 0x23, 2, 0x41, 0xA0,
- 0x23, 2, 0x42, 0x81,
- 0x23, 2, 0x43, 0x08,
- 0x23, 2, 0x44, 0x0B,
- 0x23, 2, 0x45, 0x28,
- 0x23, 2, 0x55, 0x0F,
- 0x23, 2, 0x57, 0x69,
- 0x23, 2, 0x59, 0x0A,
- 0x23, 2, 0x5A, 0x28,
- 0x23, 2, 0x5B, 0x14,
- 0x23, 2, 0x5D, 0x7F,
- 0x23, 2, 0x5E, 0x6A,
- 0x23, 2, 0x5F, 0x5A,
- 0x23, 2, 0x60, 0x4E,
- 0x23, 2, 0x61, 0x4A,
- 0x23, 2, 0x62, 0x3A,
- 0x23, 2, 0x63, 0x3C,
- 0x23, 2, 0x64, 0x23,
- 0x23, 2, 0x65, 0x39,
- 0x23, 2, 0x66, 0x35,
- 0x23, 2, 0x67, 0x34,
- 0x23, 2, 0x68, 0x51,
- 0x23, 2, 0x69, 0x3E,
- 0x23, 2, 0x6A, 0x44,
- 0x23, 2, 0x6B, 0x34,
- 0x23, 2, 0x6C, 0x2E,
- 0x23, 2, 0x6D, 0x21,
- 0x23, 2, 0x6E, 0x0E,
- 0x23, 2, 0x6F, 0x00,
- 0x23, 2, 0x70, 0x7F,
- 0x23, 2, 0x71, 0x6A,
- 0x23, 2, 0x72, 0x5A,
- 0x23, 2, 0x73, 0x4E,
- 0x23, 2, 0x74, 0x4A,
- 0x23, 2, 0x75, 0x3A,
- 0x23, 2, 0x76, 0x3C,
- 0x23, 2, 0x77, 0x23,
- 0x23, 2, 0x78, 0x39,
- 0x23, 2, 0x79, 0x35,
- 0x23, 2, 0x7A, 0x34,
- 0x23, 2, 0x7B, 0x51,
- 0x23, 2, 0x7C, 0x3E,
- 0x23, 2, 0x7D, 0x44,
- 0x23, 2, 0x7E, 0x34,
- 0x23, 2, 0x7F, 0x2E,
- 0x23, 2, 0x80, 0x21,
- 0x23, 2, 0x81, 0x0E,
- 0x23, 2, 0x82, 0x00,
- 0x23, 2, 0xE0, 0x02,
- 0x23, 2, 0x00, 0x1E,
- 0x23, 2, 0x01, 0x1E,
- 0x23, 2, 0x02, 0x41,
- 0x23, 2, 0x03, 0x41,
- 0x23, 2, 0x04, 0x43,
- 0x23, 2, 0x05, 0x43,
- 0x23, 2, 0x06, 0x1F,
- 0x23, 2, 0x07, 0x1F,
- 0x23, 2, 0x08, 0x35,
- 0x23, 2, 0x09, 0x1F,
- 0x23, 2, 0x0A, 0x15,
- 0x23, 2, 0x0B, 0x15,
- 0x23, 2, 0x0C, 0x1F,
- 0x23, 2, 0x0D, 0x47,
- 0x23, 2, 0x0E, 0x47,
- 0x23, 2, 0x0F, 0x45,
- 0x23, 2, 0x10, 0x45,
- 0x23, 2, 0x11, 0x4B,
- 0x23, 2, 0x12, 0x4B,
- 0x23, 2, 0x13, 0x49,
- 0x23, 2, 0x14, 0x49,
- 0x23, 2, 0x15, 0x1F,
- 0x23, 2, 0x16, 0x1E,
- 0x23, 2, 0x17, 0x1E,
- 0x23, 2, 0x18, 0x40,
- 0x23, 2, 0x19, 0x40,
- 0x23, 2, 0x1A, 0x42,
- 0x23, 2, 0x1B, 0x42,
- 0x23, 2, 0x1C, 0x1F,
- 0x23, 2, 0x1D, 0x1F,
- 0x23, 2, 0x1E, 0x35,
- 0x23, 2, 0x1F, 0x1F,
- 0x23, 2, 0x20, 0x15,
- 0x23, 2, 0x21, 0x15,
- 0x23, 2, 0x22, 0x1F,
- 0x23, 2, 0x23, 0x46,
- 0x23, 2, 0x24, 0x46,
- 0x23, 2, 0x25, 0x44,
- 0x23, 2, 0x26, 0x44,
- 0x23, 2, 0x27, 0x4A,
- 0x23, 2, 0x28, 0x4A,
- 0x23, 2, 0x29, 0x48,
- 0x23, 2, 0x2A, 0x48,
- 0x23, 2, 0x2B, 0x1F,
- 0x23, 2, 0x58, 0x40,
- 0x23, 2, 0x5B, 0x30,
- 0x23, 2, 0x5C, 0x0F,
- 0x23, 2, 0x5D, 0x30,
- 0x23, 2, 0x5E, 0x01,
- 0x23, 2, 0x5F, 0x02,
- 0x23, 2, 0x63, 0x14,
- 0x23, 2, 0x64, 0x6A,
- 0x23, 2, 0x67, 0x73,
- 0x23, 2, 0x68, 0x11,
- 0x23, 2, 0x69, 0x14,
- 0x23, 2, 0x6A, 0x6A,
- 0x23, 2, 0x6B, 0x08,
- 0x23, 2, 0x6C, 0x00,
- 0x23, 2, 0x6D, 0x00,
- 0x23, 2, 0x6E, 0x00,
- 0x23, 2, 0x6F, 0x88,
- 0x23, 2, 0x77, 0xDD,
- 0x23, 2, 0x79, 0x0E,
- 0x23, 2, 0x7A, 0x0F,
- 0x23, 2, 0x7D, 0x14,
- 0x23, 2, 0x7E, 0x82,
- 0x23, 2, 0xE0, 0x04,
- 0x23, 2, 0x09, 0x11,
- 0x23, 2, 0x0E, 0x48,
- 0x23, 2, 0x2B, 0x2B,
- 0x23, 2, 0x2D, 0x03,
- 0x23, 2, 0x2E, 0x44,
- 0x23, 2, 0xE0, 0x00,
- 0x23, 2, 0xE6, 0x02,
- 0x23, 2, 0xE7, 0x0C,
- 0x05, 1, 0x11,
- 0xFF, 100,
- 0x23, 2, 0xE0, 0x03,
- 0x23, 2, 0x2B, 0x01,
- 0x23, 2, 0x2C, 0x00,
- 0x23, 2, 0x30, 0x03,
- 0x23, 2, 0x31, 0xFC,
- 0x23, 2, 0x32, 0x03,
- 0x23, 2, 0x33, 0xF8,
- 0x23, 2, 0x34, 0x03,
- 0x23, 2, 0x35, 0xF0,
- 0x23, 2, 0x36, 0x03,
- 0x23, 2, 0x37, 0xE8,
- 0x23, 2, 0x38, 0x03,
- 0x23, 2, 0x39, 0xE0,
- 0x23, 2, 0x3A, 0x03,
- 0x23, 2, 0x3B, 0xD0,
- 0x23, 2, 0x3C, 0x03,
- 0x23, 2, 0x3D, 0xC0,
- 0x23, 2, 0x3E, 0x03,
- 0x23, 2, 0x3F, 0xA0,
- 0x23, 2, 0x40, 0x03,
- 0x23, 2, 0x41, 0x80,
- 0x23, 2, 0x42, 0x03,
- 0x23, 2, 0x43, 0x40,
- 0x23, 2, 0x44, 0x03,
- 0x23, 2, 0x45, 0x00,
- 0x23, 2, 0x46, 0x02,
- 0x23, 2, 0x47, 0x80,
- 0x23, 2, 0x48, 0x02,
- 0x23, 2, 0x49, 0x00,
- 0x23, 2, 0x4A, 0x01,
- 0x23, 2, 0x4B, 0xFC,
- 0x23, 2, 0x4C, 0x01,
- 0x23, 2, 0x4D, 0x7C,
- 0x23, 2, 0x4E, 0x00,
- 0x23, 2, 0x4F, 0xFC,
- 0x23, 2, 0x50, 0x00,
- 0x23, 2, 0x51, 0xBC,
- 0x23, 2, 0x52, 0x00,
- 0x23, 2, 0x53, 0x7C,
- 0x23, 2, 0x54, 0x00,
- 0x23, 2, 0x55, 0x5C,
- 0x23, 2, 0x56, 0x00,
- 0x23, 2, 0x57, 0x3C,
- 0x23, 2, 0x58, 0x00,
- 0x23, 2, 0x59, 0x2C,
- 0x23, 2, 0x5A, 0x00,
- 0x23, 2, 0x5B, 0x1C,
- 0x23, 2, 0x5C, 0x00,
- 0x23, 2, 0x5D, 0x14,
- 0x23, 2, 0x5E, 0x00,
- 0x23, 2, 0x5F, 0x0C,
- 0x23, 2, 0x60, 0x00,
- 0x23, 2, 0x61, 0x04,
- 0x23, 2, 0x62, 0x00,
- 0x23, 2, 0x63, 0x00,
- 0x23, 2, 0x64, 0x03,
- 0x23, 2, 0x65, 0xC9,
- 0x23, 2, 0x66, 0x03,
- 0x23, 2, 0x67, 0xC6,
- 0x23, 2, 0x68, 0x03,
- 0x23, 2, 0x69, 0xBE,
- 0x23, 2, 0x6A, 0x03,
- 0x23, 2, 0x6B, 0xB7,
- 0x23, 2, 0x6C, 0x03,
- 0x23, 2, 0x6D, 0xB1,
- 0x23, 2, 0x6E, 0x03,
- 0x23, 2, 0x6F, 0xA3,
- 0x23, 2, 0x70, 0x03,
- 0x23, 2, 0x71, 0x96,
- 0x23, 2, 0x72, 0x03,
- 0x23, 2, 0x73, 0x79,
- 0x23, 2, 0x74, 0x03,
- 0x23, 2, 0x75, 0x5D,
- 0x23, 2, 0x76, 0x03,
- 0x23, 2, 0x77, 0x26,
- 0x23, 2, 0x78, 0x02,
- 0x23, 2, 0x79, 0xE9,
- 0x23, 2, 0x7A, 0x02,
- 0x23, 2, 0x7B, 0x6E,
- 0x23, 2, 0x7C, 0x01,
- 0x23, 2, 0x7D, 0xF3,
- 0x23, 2, 0x7E, 0x01,
- 0x23, 2, 0x7F, 0xEF,
- 0x23, 2, 0x80, 0x01,
- 0x23, 2, 0x81, 0x73,
- 0x23, 2, 0x82, 0x00,
- 0x23, 2, 0x83, 0xF5,
- 0x23, 2, 0x84, 0x00,
- 0x23, 2, 0x85, 0xB4,
- 0x23, 2, 0x86, 0x00,
- 0x23, 2, 0x87, 0x79,
- 0x23, 2, 0x88, 0x00,
- 0x23, 2, 0x89, 0x5D,
- 0x23, 2, 0x8A, 0x00,
- 0x23, 2, 0x8B, 0x3C,
- 0x23, 2, 0x8C, 0x00,
- 0x23, 2, 0x8D, 0x2B,
- 0x23, 2, 0x8E, 0x00,
- 0x23, 2, 0x8F, 0x1C,
- 0x23, 2, 0x90, 0x00,
- 0x23, 2, 0x91, 0x14,
- 0x23, 2, 0x92, 0x00,
- 0x23, 2, 0x93, 0x0C,
- 0x23, 2, 0x94, 0x00,
- 0x23, 2, 0x95, 0x04,
- 0x23, 2, 0x96, 0x00,
- 0x23, 2, 0x97, 0x00,
- 0x23, 2, 0xE0, 0x00,
- 0x05, 1, 0x29,
- 0xFF, 0xFF,
-};
-static unsigned char ext_init_off_table_TV101WXM_FT[LCD_EXTERN_INIT_OFF_MAX] = {
- 0XFF, 5, /* delay 5ms */
- 0x05, 1, 0x28, /* display off */
- 0xFF, 50, /* delay 50ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xFF, 150, /* delay 150ms */
- 0xFF, 0xFF, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_G101B158_FT[LCD_EXTERN_INIT_ON_MAX] = {
- 0x23, 2, 0xE0, 0x00,
- 0x23, 2, 0xE1, 0x93,
- 0x23, 2, 0xE2, 0x65,
- 0x23, 2, 0xE3, 0xF8,
- 0x23, 2, 0x80, 0x03,
-
- 0x23, 2, 0xE0, 0x01,
- 0x23, 2, 0x00, 0x00,
- 0x23, 2, 0x01, 0x5D,
- 0x23, 2, 0x03, 0x00,
- 0x23, 2, 0x04, 0x64,
-
- 0x23, 2, 0x17, 0x00,
- 0x23, 2, 0x18, 0xC7,//BF=4.5V,c7=4.6v, D7=4.8V
- 0x23, 2, 0x19, 0x01,//0.3V
- 0x23, 2, 0x1A, 0x00,
- 0x23, 2, 0x1B, 0xC7,
- 0x23, 2, 0x1C, 0x01,
-
- 0x23, 2, 0x1F, 0x70, //VGH_REG=16.2V
- 0x23, 2, 0x20, 0x2D, //VGL_REG=-12V
- 0x23, 2, 0x21, 0x2D, //VGL_REG2=-12V
- 0x23, 2, 0x22, 0x7E,
-
- 0x23, 2, 0x35, 0x28, //SAP
-
- 0x23, 2, 0x37, 0x19, //SS=1,BGR=1
-
- 0x23, 2, 0x38, 0x05, //JDT=101 zigzag inversion
- 0x23, 2, 0x39, 0x00,
- 0x23, 2, 0x3A, 0x01,
- 0x23, 2, 0x3C, 0x7C, //SET EQ3 for TE_H
- 0x23, 2, 0x3D, 0xFF, //SET CHGEN_ON, modify 20140806
- 0x23, 2, 0x3E, 0xFF, //SET CHGEN_OFF, modify 20140806
- 0x23, 2, 0x3F, 0x7F, //SET CHGEN_OFF2, modify 20140806
-
-
- 0x23, 2, 0x40, 0x06, //RSO=
- 0x23, 2, 0x41, 0xA0, //LN=640->1280 line
- 0x23, 2, 0x43, 0x14, //VFP=20
- 0x23, 2, 0x44, 0x17, //VBP=24
- 0x23, 2, 0x45, 0x2C, //HBP=44
-
- 0x23, 2, 0x55, 0x0F, //DCDCM=1111
- 0x23, 2, 0x57, 0x68,
- 0x23, 2, 0x59, 0x0A, //VCL = -2.5V
- 0x23, 2, 0x5A, 0x2E, //VGH = 16.2V
- 0x23, 2, 0x5B, 0x1A, //VGL = -12V
- 0x23, 2, 0x5C, 0x15, //pump clk
-
-
- 0x23, 2, 0x5D, 0x7F,
- 0x23, 2, 0x5E, 0x61,
- 0x23, 2, 0x5F, 0x50,
- 0x23, 2, 0x60, 0x43,
- 0x23, 2, 0x61, 0x3E,
- 0x23, 2, 0x62, 0x2E,
- 0x23, 2, 0x63, 0x33,
- 0x23, 2, 0x64, 0x1C,
- 0x23, 2, 0x65, 0x34,
- 0x23, 2, 0x66, 0x33,
- 0x23, 2, 0x67, 0x32,
- 0x23, 2, 0x68, 0x50,
- 0x23, 2, 0x69, 0x3E,
- 0x23, 2, 0x6A, 0x46,
- 0x23, 2, 0x6B, 0x37,
- 0x23, 2, 0x6C, 0x32,
- 0x23, 2, 0x6D, 0x24,
- 0x23, 2, 0x6E, 0x12,
- 0x23, 2, 0x6F, 0x02,
- 0x23, 2, 0x70, 0x7F,
- 0x23, 2, 0x71, 0x61,
- 0x23, 2, 0x72, 0x50,
- 0x23, 2, 0x73, 0x43,
- 0x23, 2, 0x74, 0x3E,
- 0x23, 2, 0x75, 0x2E,
- 0x23, 2, 0x76, 0x33,
- 0x23, 2, 0x77, 0x1C,
- 0x23, 2, 0x78, 0x34,
- 0x23, 2, 0x79, 0x33,
- 0x23, 2, 0x7A, 0x32,
- 0x23, 2, 0x7B, 0x50,
- 0x23, 2, 0x7C, 0x3E,
- 0x23, 2, 0x7D, 0x46,
- 0x23, 2, 0x7E, 0x37,
- 0x23, 2, 0x7F, 0x32,
- 0x23, 2, 0x80, 0x24,
- 0x23, 2, 0x81, 0x12,
- 0x23, 2, 0x82, 0x02,
-
-
- 0x23, 2, 0xE0, 0x02,
-
- 0x23, 2, 0x00, 0x52,//RESET_EVEN
- 0x23, 2, 0x01, 0x55,//VSSG_EVEN
- 0x23, 2, 0x02, 0x55,//VSSG_EVEN
- 0x23, 2, 0x03, 0x50,//STV2_ODD
- 0x23, 2, 0x04, 0x77,//VDD2_ODD
- 0x23, 2, 0x05, 0x57,//VDD1_ODD
- 0x23, 2, 0x06, 0x55,//x
- 0x23, 2, 0x07, 0x4E,//CK11
- 0x23, 2, 0x08, 0x4C,//CK9
- 0x23, 2, 0x09, 0x5F,//x
- 0x23, 2, 0x0A, 0x4A,//CK7
- 0x23, 2, 0x0B, 0x48,//CK5
- 0x23, 2, 0x0C, 0x55,//x
- 0x23, 2, 0x0D, 0x46,//CK3
- 0x23, 2, 0x0E, 0x44,//CK1
- 0x23, 2, 0x0F, 0x40,//STV1_ODD
- 0x23, 2, 0x10, 0x55,//x
- 0x23, 2, 0x11, 0x55,//x
- 0x23, 2, 0x12, 0x55,//x
- 0x23, 2, 0x13, 0x55,//x
- 0x23, 2, 0x14, 0x55,//x
- 0x23, 2, 0x15, 0x55,//x
-
- 0x23, 2, 0x16, 0x53,//RESET__EVEN
- 0x23, 2, 0x17, 0x55,//VSSG_EVEN
- 0x23, 2, 0x18, 0x55,//VSSG_EVEN
- 0x23, 2, 0x19, 0x51,//STV2_EVEN
- 0x23, 2, 0x1A, 0x77,//VDD2_EVEN
- 0x23, 2, 0x1B, 0x57,//VDD1_EVEN
- 0x23, 2, 0x1C, 0x55,//x
- 0x23, 2, 0x1D, 0x4F,//CK12
- 0x23, 2, 0x1E, 0x4D,//CK10
- 0x23, 2, 0x1F, 0x5F,//x
- 0x23, 2, 0x20, 0x4B,//CK8
- 0x23, 2, 0x21, 0x49,//CK6
- 0x23, 2, 0x22, 0x55,//x
- 0x23, 2, 0x23, 0x47,//CK4
- 0x23, 2, 0x24, 0x45,//CK2
- 0x23, 2, 0x25, 0x41,//STV1_EVEN
- 0x23, 2, 0x26, 0x55,//x
- 0x23, 2, 0x27, 0x55,//x
- 0x23, 2, 0x28, 0x55,//x
- 0x23, 2, 0x29, 0x55,//x
- 0x23, 2, 0x2A, 0x55,//x
- 0x23, 2, 0x2B, 0x55,//x
-
- 0x23, 2, 0x2C, 0x13,//RESET_EVEN
- 0x23, 2, 0x2D, 0x15,//VSSG_EVEN
- 0x23, 2, 0x2E, 0x15,//VSSG_EVEN
- 0x23, 2, 0x2F, 0x01,//STV2_ODD
- 0x23, 2, 0x30, 0x37,//VDD2_ODD
- 0x23, 2, 0x31, 0x17,//VDD1_ODD
- 0x23, 2, 0x32, 0x15,//x
- 0x23, 2, 0x33, 0x0D,//CK11
- 0x23, 2, 0x34, 0x0F,//CK9
- 0x23, 2, 0x35, 0x15,//x
- 0x23, 2, 0x36, 0x05,//CK7
- 0x23, 2, 0x37, 0x07,//CK5
- 0x23, 2, 0x38, 0x15,//x
- 0x23, 2, 0x39, 0x09,//CK3
- 0x23, 2, 0x3A, 0x0B,//CK1
- 0x23, 2, 0x3B, 0x11,//STV1_ODD
- 0x23, 2, 0x3C, 0x15,//x
- 0x23, 2, 0x3D, 0x15,//x
- 0x23, 2, 0x3E, 0x15,//x
- 0x23, 2, 0x3F, 0x15,//x
- 0x23, 2, 0x40, 0x15,//x
- 0x23, 2, 0x41, 0x15,//x
-
- 0x23, 2, 0x42, 0x12,//RESET__EVEN
- 0x23, 2, 0x43, 0x15,//VSSG_EVEN
- 0x23, 2, 0x44, 0x15,//VSSG_EVEN
- 0x23, 2, 0x45, 0x00,//STV2_EVEN
- 0x23, 2, 0x46, 0x37,//VDD2_EVEN
- 0x23, 2, 0x47, 0x17,//VDD1_EVEN
- 0x23, 2, 0x48, 0x15,//x
- 0x23, 2, 0x49, 0x0C,//CK12
- 0x23, 2, 0x4A, 0x0E,//CK10
- 0x23, 2, 0x4B, 0x15,//x
- 0x23, 2, 0x4C, 0x04,//CK8
- 0x23, 2, 0x4D, 0x06,//CK6
- 0x23, 2, 0x4E, 0x15,//x
- 0x23, 2, 0x4F, 0x08,//CK4
- 0x23, 2, 0x50, 0x0A,//CK2
- 0x23, 2, 0x51, 0x10,//STV1_EVEN
- 0x23, 2, 0x52, 0x15,//x
- 0x23, 2, 0x53, 0x15,//x
- 0x23, 2, 0x54, 0x15,//x
- 0x23, 2, 0x55, 0x15,//x
- 0x23, 2, 0x56, 0x15,//x
- 0x23, 2, 0x57, 0x15,//x
-
- 0x23, 2, 0x58, 0x40,
- 0x23, 2, 0x5B, 0x10,
- 0x23, 2, 0x5C, 0x12,//STV_S0
- 0x23, 2, 0x5D, 0x40,
- 0x23, 2, 0x5E, 0x00,
- 0x23, 2, 0x5F, 0x00,
- 0x23, 2, 0x60, 0x40,//ETV_W
- 0x23, 2, 0x61, 0x03,
- 0x23, 2, 0x62, 0x04,
- 0x23, 2, 0x63, 0x6C,//CKV_ON
- 0x23, 2, 0x64, 0x6C,//CKV_OFF
- 0x23, 2, 0x65, 0x75,
- 0x23, 2, 0x66, 0x14,//ETV_S0
- 0x23, 2, 0x67, 0xB4, //ckv_num/ckv_w
- 0x23, 2, 0x68, 0x14, //CKV_S0
- 0x23, 2, 0x69, 0x6C,//CKV_ON
- 0x23, 2, 0x6A, 0x6C,//CKV_OFF
- 0x23, 2, 0x6B, 0x0C, //dummy
- 0x23, 2, 0x6D, 0x04,//GGND1
- 0x23, 2, 0x6E, 0x00,//GGND2
- 0x23, 2, 0x6F, 0x88,
- 0x23, 2, 0x75, 0xBB,//FLM_EN
- 0x23, 2, 0x76, 0x02,
- 0x23, 2, 0x77, 0x00,
- 0x23, 2, 0x78, 0x02,//FLM_OFF
-
- 0x23, 2, 0xE0, 0x03,
- 0x23, 2, 0xAF, 0x20,//Adjust CABC
-
-
- 0x23, 2, 0xE0, 0x04,
- 0x23, 2, 0x09, 0x11,
- 0x23, 2, 0x0E, 0x48, //Source EQ option
- 0x23, 2, 0x2B, 0x2B,
- 0x23, 2, 0x2D, 0x03,//defult 0x01
- 0x23, 2, 0x2E, 0x44,
- 0x23, 2, 0x41, 0xFF,//Adjust CABC
-
- 0x23, 2, 0xE0, 0x05,
- 0x23, 2, 0x12, 0x72,//VCI GAS detect voltage
-
- 0x23, 2, 0xE0, 0x00,
- 0x23, 2, 0xE6, 0x02,//WD_Timer
- 0x23, 2, 0xE7, 0x0C,//WD_Timer
-
- 0x23, 2, 0x53, 0x2C,//CABC dimming
-
- 0x05, 1, 0x11, // SLPOUT
- 0xff, 120,
-
- 0x23, 2, 0xE0, 0x03,
- 0x23, 2, 0x2B, 0x01,//DGC_EN
- 0xff, 10,
- 0x23, 2, 0x2C, 0x01,//DGC_SEL
-
- 0x23, 2, 0x30, 0x03,
- 0x23, 2, 0x31, 0xDE,
- 0x23, 2, 0x32, 0x03,
- 0x23, 2, 0x33, 0xDA,
- 0x23, 2, 0x34, 0x03,
- 0x23, 2, 0x35, 0xD1,
- 0x23, 2, 0x36, 0x03,
- 0x23, 2, 0x37, 0xC9,
- 0x23, 2, 0x38, 0x03,
- 0x23, 2, 0x39, 0xC1,
- 0x23, 2, 0x3A, 0x03,
- 0x23, 2, 0x3B, 0xB3,
- 0x23, 2, 0x3C, 0x03,
- 0x23, 2, 0x3D, 0xA4,
- 0x23, 2, 0x3E, 0x03,
- 0x23, 2, 0x3F, 0x83,
- 0x23, 2, 0x40, 0x03,
- 0x23, 2, 0x41, 0x62,
- 0x23, 2, 0x42, 0x03,
- 0x23, 2, 0x43, 0x23,
- 0x23, 2, 0x44, 0x02,
- 0x23, 2, 0x45, 0xE4,
- 0x23, 2, 0x46, 0x02,
- 0x23, 2, 0x47, 0x67,
- 0x23, 2, 0x48, 0x01,
- 0x23, 2, 0x49, 0xEC,
- 0x23, 2, 0x4A, 0x01,
- 0x23, 2, 0x4B, 0xE8,
- 0x23, 2, 0x4C, 0x01,
- 0x23, 2, 0x4D, 0x6D,
- 0x23, 2, 0x4E, 0x00,
- 0x23, 2, 0x4F, 0xF2,
- 0x23, 2, 0x50, 0x00,
- 0x23, 2, 0x51, 0xB2,
- 0x23, 2, 0x52, 0x00,
- 0x23, 2, 0x53, 0x76,
- 0x23, 2, 0x54, 0x00,
- 0x23, 2, 0x55, 0x58,
- 0x23, 2, 0x56, 0x00,
- 0x23, 2, 0x57, 0x39,
- 0x23, 2, 0x58, 0x00,
- 0x23, 2, 0x59, 0x2A,
- 0x23, 2, 0x5A, 0x00,
- 0x23, 2, 0x5B, 0x1B,
- 0x23, 2, 0x5C, 0x00,
- 0x23, 2, 0x5D, 0x13,
- 0x23, 2, 0x5E, 0x00,
- 0x23, 2, 0x5F, 0x0B,
- 0x23, 2, 0x60, 0x00,
- 0x23, 2, 0x61, 0x04,
- 0x23, 2, 0x62, 0x00,
- 0x23, 2, 0x63, 0x00,
-
- 0x23, 2, 0x64, 0x03,
- 0x23, 2, 0x65, 0xE7,
- 0x23, 2, 0x66, 0x03,
- 0x23, 2, 0x67, 0xE4,
- 0x23, 2, 0x68, 0x03,
- 0x23, 2, 0x69, 0xDD,
- 0x23, 2, 0x6A, 0x03,
- 0x23, 2, 0x6B, 0xD5,
- 0x23, 2, 0x6C, 0x03,
- 0x23, 2, 0x6D, 0xCE,
- 0x23, 2, 0x6E, 0x03,
- 0x23, 2, 0x6F, 0xBF,
- 0x23, 2, 0x70, 0x03,
- 0x23, 2, 0x71, 0xB2,
- 0x23, 2, 0x72, 0x03,
- 0x23, 2, 0x73, 0x93,
- 0x23, 2, 0x74, 0x03,
- 0x23, 2, 0x75, 0x71,
- 0x23, 2, 0x76, 0x03,
- 0x23, 2, 0x77, 0x33,
- 0x23, 2, 0x78, 0x02,
- 0x23, 2, 0x79, 0xF4,
- 0x23, 2, 0x7A, 0x02,
- 0x23, 2, 0x7B, 0x75,
- 0x23, 2, 0x7C, 0x01,
- 0x23, 2, 0x7D, 0xF7,
- 0x23, 2, 0x7E, 0x01,
- 0x23, 2, 0x7F, 0xF3,
- 0x23, 2, 0x80, 0x01,
- 0x23, 2, 0x81, 0x75,
- 0x23, 2, 0x82, 0x00,
- 0x23, 2, 0x83, 0xF7,
- 0x23, 2, 0x84, 0x00,
- 0x23, 2, 0x85, 0xB6,
- 0x23, 2, 0x86, 0x00,
- 0x23, 2, 0x87, 0x7C,
- 0x23, 2, 0x88, 0x00,
- 0x23, 2, 0x89, 0x5E,
- 0x23, 2, 0x8A, 0x00,
- 0x23, 2, 0x8B, 0x3F,
- 0x23, 2, 0x8C, 0x00,
- 0x23, 2, 0x8D, 0x2E,
- 0x23, 2, 0x8E, 0x00,
- 0x23, 2, 0x8F, 0x1D,
- 0x23, 2, 0x90, 0x00,
- 0x23, 2, 0x91, 0x15,
- 0x23, 2, 0x92, 0x00,
- 0x23, 2, 0x93, 0x0C,
- 0x23, 2, 0x94, 0x00,
- 0x23, 2, 0x95, 0x04,
- 0x23, 2, 0x96, 0x00,
- 0x23, 2, 0x97, 0x00,
-
- 0x23, 2, 0xE0, 0x00,
-
- 0x05, 1, 0x29, // DSPON
- 0xff, 5,
- 0xff, 0xff,
-};
-
-static unsigned char ext_init_off_table_G101B158_FT[LCD_EXTERN_INIT_OFF_MAX] = {
- 0XFF, 5, /* delay 5ms */
- 0x05, 1, 0x28, /* display off */
- 0xFF, 50, /* delay 50ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xFF, 150, /* delay 150ms */
- 0xFF, 0xFF, /* ending flag */
-};
-
-static struct lcd_extern_config_s ext_config[LCD_EXTERN_NUM_MAX] = {
- {
- .index = 0,
- .name = "ext_default",
- .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 0, /* 0=disable, 1=enable */
- .i2c_addr = 0x1c, /* 7bit i2c address */
- .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for invalid */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- { /* P070ACB_FT */
- .index = 1,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_P070ACB_FT,
- .table_init_on_cnt = sizeof(ext_init_on_table_P070ACB_FT),
- .table_init_off = ext_init_off_table_P070ACB_FT,
- .table_init_off_cnt = sizeof(ext_init_off_table_P070ACB_FT),
- },
- { /* TL050FHV02CT */
- .index = 2,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_TL050FHV02CT,
- .table_init_on_cnt = sizeof(ext_init_on_table_TL050FHV02CT),
- .table_init_off = ext_init_off_table_TL050FHV02CT,
- .table_init_off_cnt = sizeof(ext_init_off_table_TL050FHV02CT),
- },
- { /* boe_nvtk_10 */
- .index = 3,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_TV101WXM,
- .table_init_on_cnt = sizeof(ext_init_on_table_TV101WXM),
- .table_init_off = ext_init_off_table_TV101WXM,
- .table_init_off_cnt = sizeof(ext_init_off_table_TV101WXM),
- },
- { /* inx_nvtk_10 */
- .index = 4,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_G101B158,
- .table_init_on_cnt = sizeof(ext_init_on_table_G101B158),
- .table_init_off = ext_init_off_table_G101B158,
- .table_init_off_cnt = sizeof(ext_init_off_table_G101B158),
- },
- { /* boe_fiti_10 */
- .index = 5,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_TV101WXM_FT,
- .table_init_on_cnt = sizeof(ext_init_on_table_TV101WXM_FT),
- .table_init_off = ext_init_off_table_TV101WXM_FT,
- .table_init_off_cnt = sizeof(ext_init_off_table_TV101WXM_FT),
- },
- { /* inx_fiti_10 */
- .index = 6,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_G101B158_FT,
- .table_init_on_cnt = sizeof(ext_init_on_table_G101B158_FT),
- .table_init_off = ext_init_off_table_G101B158_FT,
- .table_init_off_cnt = sizeof(ext_init_off_table_G101B158_FT),
- },
- {
- .index = LCD_EXTERN_INDEX_INVALID,
- },
-};
-
-#endif
-
diff --git a/board/amlogic/g12b_puddy_px/zircon.c b/board/amlogic/g12b_puddy_px/zircon.c
deleted file mode 100644
index ec0b698..0000000
--- a/board/amlogic/g12b_puddy_px/zircon.c
+++ /dev/null
@@ -1,205 +0,0 @@
-/*
- * Copyright (c) 2018 The Fuchsia Authors
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common.h>
-#include <fs.h>
-#include <version.h>
-#include <zircon/zircon.h>
-
-#define PDEV_VID_GOOGLE 3
-#define PDEV_PID_SHERLOCK 5
-
-#define NVRAM_LENGTH (8 * 1024)
-
-static const zbi_cpu_config_t cpu_config = {
- .cluster_count = 1,
- .clusters = {
- {
- .cpu_count = 4,
- },
- },
-};
-
-static const zbi_mem_range_t mem_config[] = {
- {
- .type = ZBI_MEM_RANGE_RAM,
- .length = 0x60000000, // 1.5 GB
- },
- {
- .type = ZBI_MEM_RANGE_PERIPHERAL,
- .paddr = 0xf5800000,
- .length = 0x0a800000,
- },
- /* secmon_reserved:linux,secmon */
- {
- .type = ZBI_MEM_RANGE_RESERVED,
- .paddr = 0x05000000,
- .length = 0x2400000,
- },
- /* logo_reserved:linux,meson-fb */
- {
- .type = ZBI_MEM_RANGE_RESERVED,
- .paddr = 0x5f800000,
- .length = 0x800000,
- },
-};
-
-static const dcfg_simple_t uart_driver = {
- .mmio_phys = 0xff803000,
- .irq = 225,
-};
-
-static const dcfg_arm_gicv2_driver_t gicv2_driver = {
- .mmio_phys = 0xffc00000,
- .gicd_offset = 0x1000,
- .gicc_offset = 0x2000,
- .gich_offset = 0x4000,
- .gicv_offset = 0x6000,
- .ipi_base = 5,
-};
-
-static const dcfg_arm_psci_driver_t psci_driver = {
- .use_hvc = false,
- .reboot_args = { 1, 0, 0 },
- .reboot_bootloader_args = { 4, 0, 0 },
- .reboot_recovery_args = { 2, 0, 0 },
-};
-
-static const dcfg_arm_generic_timer_driver_t timer_driver = {
- .irq_phys = 30,
-};
-
-static const zbi_platform_id_t platform_id = {
- .vid = PDEV_VID_GOOGLE,
- .pid = PDEV_PID_SHERLOCK,
- .board_name = "sherlock",
-};
-
-enum {
- PART_TPL,
- PART_FTS,
- PART_FACTORY,
- PART_ZIRCON_B,
- PART_ZIRCON_A,
- PART_ZIRCON_R,
- PART_FVM,
- PART_SYS_CONFIG,
- PART_MIGRATION,
- PART_COUNT,
-};
-
-#define PUDDY_FACTORY_IF "mmc"
-#define PUDDY_FACTORY_PART "1:5"
-#define FACTORY_MAC_ADDR_BUFF_LEN 30
-#define PUDDY_FACTORY_MACADDR_FILE "mac_addr"
-#define FACTORY_MAC_ADDR_FILE_LEN 25
-
-static int add_mac_addresses(zbi_header_t* zbi) {
- char buffer[FACTORY_MAC_ADDR_BUFF_LEN];
- u64 fullmac[2];
- u8 mac_addr[6];
- int len_read;
- int mac_num, i;
-
- if (fs_set_blk_dev(PUDDY_FACTORY_IF, PUDDY_FACTORY_PART,
- FS_TYPE_EXT)) {
- printf("set_blk_dev %s-%s failed.\n",
- PUDDY_FACTORY_IF, PUDDY_FACTORY_PART);
- return -1;
- }
-
- if (fs_read(PUDDY_FACTORY_MACADDR_FILE, buffer, 0,
- FACTORY_MAC_ADDR_BUFF_LEN, &len_read)) {
- printf("Failed to read Mac Addresses from Factory partition\n");
- }
- if (len_read != FACTORY_MAC_ADDR_FILE_LEN) {
- printf("Factory MAC Addr File length (%d) incorrect.\n",
- len_read);
- return -1;
- }
- buffer[len_read] = '\0';
-
- /*
- * "buffer" should now contain two hex strings separated by \n,
- * for a total of 25 bytes. Separate into 2 C strings and convert.
- */
- buffer[len_read/2] = '\0';
- fullmac[0] = simple_strtoull(buffer, NULL, 16);
- fullmac[1] = simple_strtoull(&buffer[(len_read/2)+1], NULL, 16);
-
- for (mac_num = 0; mac_num < ARRAY_SIZE(fullmac); mac_num++) {
- for (i = ARRAY_SIZE(mac_addr)-1; i >= 0; i--) {
- mac_addr[i] = (u8) (fullmac[mac_num] & 0xff);
- fullmac[mac_num] >>= 8;
- }
- zircon_append_boot_item(zbi, ZBI_TYPE_DRV_MAC_ADDRESS, mac_num,
- mac_addr, sizeof(mac_addr));
- }
-
- return 0;
-}
-
-int zircon_preboot(zbi_header_t *zbi)
-{
- /* add CPU configuration */
- zircon_append_boot_item(zbi, ZBI_TYPE_CPU_CONFIG, 0, &cpu_config,
- sizeof(zbi_cpu_config_t) +
- sizeof(zbi_cpu_cluster_t) *
- cpu_config.cluster_count);
-
- /*
- * allocate crashlog save area before 0x5f800000-0x60000000
- * reserved area
- */
- zbi_nvram_t nvram;
-
- nvram.base = 0x5f800000 - NVRAM_LENGTH;
- nvram.length = NVRAM_LENGTH;
- zircon_append_boot_item(zbi, ZBI_TYPE_NVRAM, 0, &nvram, sizeof(nvram));
-
- /* add memory configuration */
- zircon_append_boot_item(zbi, ZBI_TYPE_MEM_CONFIG, 0, &mem_config,
- sizeof(mem_config));
-
- /* add kernel drivers */
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_AMLOGIC_UART,
- &uart_driver, sizeof(uart_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_GIC_V2,
- &gicv2_driver, sizeof(gicv2_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_PSCI,
- &psci_driver, sizeof(psci_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER,
- KDRV_ARM_GENERIC_TIMER,
- &timer_driver, sizeof(timer_driver));
-
- char[] uboot_ver = "bootloader.name=" U_BOOT_VERSION_STRING;
- // Zircon's cmdline parameters cannot contain spaces so
- // convert spaces in autogenerated U-boot version string
- // to underscores.
- // See zircon/docs/kernel_cmdline.md
- int i;
- int len = strlen(uboot_ver);
- for (i = 0; i < len; i++) {
- if (uboot_ver[i] == ' ') {
- uboot_ver[i] = '_';
- }
- }
-
- zircon_append_boot_item(zbi, ZBI_TYPE_CMDLINE, 0, uboot_ver,
- strlen(uboot_ver) + 1);
-
- /* add platform ID */
- zircon_append_boot_item(zbi, ZBI_TYPE_PLATFORM_ID, 0, &platform_id,
- sizeof(platform_id));
-
- int ret = add_mac_addresses(zbi);
-
- if (ret < 0) {
- printf("ERROR: unable to read MAC addresses from the"
- " factory partition!\n");
- }
- return 0;
-}
diff --git a/board/amlogic/g12b_w400_v1/Kconfig b/board/amlogic/g12b_w400_v1/Kconfig
index f95e26d..47bbe1d 100644
--- a/board/amlogic/g12b_w400_v1/Kconfig
+++ b/board/amlogic/g12b_w400_v1/Kconfig
@@ -14,4 +14,3 @@
default n
endif
-
diff --git a/board/amlogic/g12b_w400_v1/eth_setup.c b/board/amlogic/g12b_w400_v1/eth_setup.c
index 85a1b35..c5aac45 100644
--- a/board/amlogic/g12b_w400_v1/eth_setup.c
+++ b/board/amlogic/g12b_w400_v1/eth_setup.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * board/amlogic/g12b_w400_v1/eth_setup.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <common.h>
#include <malloc.h>
diff --git a/board/amlogic/g12b_w400_v1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/g12b_w400_v1/firmware/scp_task/pwm_ctrl.h
index 5d65f49..c78287a 100644
--- a/board/amlogic/g12b_w400_v1/firmware/scp_task/pwm_ctrl.h
+++ b/board/amlogic/g12b_w400_v1/firmware/scp_task/pwm_ctrl.h
@@ -1,7 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
-*board/amlogic/g12b_w400_v1/firmware/scp_task/pwm_ctrl.h
-*table for Dynamic Voltage/Frequency Scaling
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __PWM_CTRL_H__
#define __PWM_CTRL_H__
diff --git a/board/amlogic/g12b_w400_v1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/g12b_w400_v1/firmware/scp_task/pwr_ctrl.c
index 506a03a..f51c07c 100644
--- a/board/amlogic/g12b_w400_v1/firmware/scp_task/pwr_ctrl.c
+++ b/board/amlogic/g12b_w400_v1/firmware/scp_task/pwr_ctrl.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * board/amlogic/g12b_w400_v1/firmware/scp_task/pwr_ctrl.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <gpio.h>
#include "pwm_ctrl.h"
diff --git a/board/amlogic/g12b_w400_v1/firmware/timing.c b/board/amlogic/g12b_w400_v1/firmware/timing.c
index ebba5ce..3978115 100644
--- a/board/amlogic/g12b_w400_v1/firmware/timing.c
+++ b/board/amlogic/g12b_w400_v1/firmware/timing.c
@@ -1,31 +1,14 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * board/amlogic/g12b_w400_v1/firmware/timing.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <asm/arch/secure_apb.h>
#include <asm/arch/timing.h>
#include <asm/arch/ddr_define.h>
/* board clk defines */
-#define DDR_SIZE 0
-#define CPU_CLK 1200
+#define CPU_CLK 1200
/* ddr config support multiple configs for boards which use same bootloader:
* config steps:
@@ -60,19 +43,93 @@
*
*/
-ddr_set_t __ddr_setting[] = {
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_settings"))) = {
{
- /* ddr4 */
+ // g12a 4layer 4pcs ddr4 rank01 (1320)(T204)
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1320, 0, 0, 0},
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0xffff,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 80,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 80, //60,
+ .dram_ac_odt_ohm = 0,
+ .dram_data_wr_odt_ohm = 120,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 8200/12,//700,
+ .vref_dram_permil = 9200/12,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {32+10,32,32+10,32+10,32,32,32+10,32+10,32+10,32+8},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .magic = DRAM_CFG_MAGIC,
+ .bitTimeControl_2d = 1, //training time setting,=1,200ms;=7,2s;
+ .fast_boot[0] = 1,
+ .training_offset = (1<<3) | (4<<0),//read dqs offset after training,bit3=0 right move,bit3=1 left move,bit[2:0] offset step
+},
+{
+ // g12a 4layer 2pcs ddr4 rank0 (1320)(U200)
.board_id = CONFIG_BOARD_ID_MASK,
.version = 1,
.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
.DramType = CONFIG_DDR_TYPE_DDR4,
- .DRAMFreq = {1200, 0, 0, 0},
+ .DRAMFreq = {1320, 0, 0, 0},
.ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
.ddr_base_addr = CFG_DDR_BASE_ADDR,
.ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
.DisabledDbyte = 0xf0,
.Is2Ttiming = 1,
@@ -80,8 +137,8 @@
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0,
.training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -103,7 +160,7 @@
.vref_dram_permil = 0,//700,
//.vref_reverse = 0,
//.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
- .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ .ac_trace_delay = {32-10,32,32,32,32,32,32,32,32,32},
.ddr_dmc_remap = {
[0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
[1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
@@ -130,9 +187,11 @@
.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
.ddr_func = DDR_FUNC,
.magic = DRAM_CFG_MAGIC,
+ .bitTimeControl_2d = 1, //training time setting,=1,200ms;=7,2s;
+ .fast_boot[0] = 1,
},
{
- /* ddr3 */
+ // g12a 4layer 4pcs ddr3 rank01 (912)(U212)
.board_id = CONFIG_BOARD_ID_MASK,
.version = 1,
.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
@@ -140,8 +199,8 @@
.DRAMFreq = {912, 0, 0, 0},
.ddr_base_addr = CFG_DDR_BASE_ADDR,
.ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
.DisabledDbyte = 0xf0,
.Is2Ttiming = 1,
@@ -149,8 +208,8 @@
.dram_cs0_size_MB = 0xffff,
.dram_cs1_size_MB = 0xffff,
.training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0c0c,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -187,7 +246,7 @@
.ddr_dmc_remap = {
[0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
[1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
[3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
[4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
},
@@ -211,6 +270,91 @@
.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
.ddr_func = DDR_FUNC,
.magic = DRAM_CFG_MAGIC,
+ .bitTimeControl_2d = 1, //training time setting,=1,200ms;=7,2s;
+ .fast_boot[0] = 1,
+},
+{
+ // g12a 4layer 2pcs ddr3 rank0 (912)
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .bitTimeControl_2d = 1, //training time setting,=1,200ms;=7,2s;
+ .fast_boot[0] = 1,
},
{
/* lpddr4 */
@@ -223,8 +367,8 @@
.DRAMFreq = {1392, 0, 0, 0},
.ddr_base_addr = CFG_DDR_BASE_ADDR,
.ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
.DisabledDbyte = 0xf0,
.Is2Ttiming = 0,
@@ -232,8 +376,8 @@
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0xffff,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -285,6 +429,8 @@
.ddr_func = DDR_FUNC,
.magic = DRAM_CFG_MAGIC,
.diagnose = CONFIG_DIAGNOSE_DISABLE,
+ .bitTimeControl_2d = 1,
+ .fast_boot[0] = 1,
},
{
/* Y2 dongle */
@@ -297,8 +443,8 @@
.DRAMFreq = {1392, 0, 0, 0},
.ddr_base_addr = CFG_DDR_BASE_ADDR,
.ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
.DisabledDbyte = 0xf0,
.Is2Ttiming = 0,
@@ -306,8 +452,8 @@
.dram_cs0_size_MB = 0xffff,//1024,
.dram_cs1_size_MB = 0,//1024,
.training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x30,0x30,0x30,0x30}, // // Odt pattern for accesses //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0808,
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
.PllBypassEn = 0, //bit0-ps0,bit1-ps1
.ddr_rdbi_wr_enable = 0,
.clk_drv_ohm = 40,
@@ -356,6 +502,8 @@
.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
.ddr_func = DDR_FUNC,
.magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
+ .bitTimeControl_2d = 1,
},
};
diff --git a/board/amlogic/g12b_w400_v1/g12b_w400_v1.c b/board/amlogic/g12b_w400_v1/g12b_w400_v1.c
index da2334e..8a4ce47 100644
--- a/board/amlogic/g12b_w400_v1/g12b_w400_v1.c
+++ b/board/amlogic/g12b_w400_v1/g12b_w400_v1.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * board/amlogic/g12b_w400_v1/g12b_w400_v1.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <common.h>
#include <malloc.h>
@@ -25,7 +9,7 @@
#include <environment.h>
#include <fdt_support.h>
#include <linux/libfdt.h>
-#include <asm/arch/cpu_id.h>
+#include <amlogic/cpu_id.h>
#include <asm/arch/secure_apb.h>
#include <asm/arch/pinctrl_init.h>
#ifdef CONFIG_AML_VPU
@@ -349,61 +333,6 @@
}
#endif
-/*
- * mtd nand partition table, only care the size!
- * offset will be calculated by nand driver.
- */
-#ifdef CONFIG_AML_MTD
-static struct mtd_partition normal_partition_info[] = {
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- /* MUST NOT CHANGE this part unless u know what you are doing!
- * inherent parition for descrete bootloader to store fip
- * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
- * name must be same with TPL_PART_NAME
- */
- {
- .name = "tpl",
- .offset = 0,
- .size = 0,
- },
-#endif
- {
- .name = "logo",
- .offset = 0,
- .size = 2*SZ_1M,
- },
- {
- .name = "recovery",
- .offset = 0,
- .size = 16*SZ_1M,
- },
- {
- .name = "boot",
- .offset = 0,
- .size = 15*SZ_1M,
- },
- {
- .name = "system",
- .offset = 0,
- .size = 280*SZ_1M,
- },
- /* last partition get the rest capacity */
- {
- .name = "data",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-struct mtd_partition *get_aml_mtd_partition(void)
-{
- return normal_partition_info;
-}
-int get_aml_partition_count(void)
-{
- return ARRAY_SIZE(normal_partition_info);
-}
-#endif /* CONFIG_AML_MTD */
-
#ifdef CONFIG_AML_SPIFC
/*
* BOOT_3: NOR_HOLDn:reg0[15:12]=3
@@ -414,6 +343,8 @@
* BOOT_14: NOR_CS:reg1[27:24]=3
*/
#define SPIFC_NUM_CS 1
+
+#if 0
static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
static int spifc_pinctrl_enable(void *pinctrl, bool enable)
@@ -432,7 +363,6 @@
return 0;
}
-#if 0
static const struct spifc_platdata spifc_platdata = {
.reg = 0xffd14000,
.mem_map = 0xf6000000,
@@ -695,3 +625,38 @@
/* eg: bl31/32 rsv */
return 0;
}
+
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "dspA",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "dspB",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
\ No newline at end of file
diff --git a/board/amlogic/g12b_w400_v1/lcd.c b/board/amlogic/g12b_w400_v1/lcd.c
index bebe03f..aa5a96b 100644
--- a/board/amlogic/g12b_w400_v1/lcd.c
+++ b/board/amlogic/g12b_w400_v1/lcd.c
@@ -1,25 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * AMLOGIC LCD panel driver.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
#include <amlogic/media/vout/lcd/aml_lcd.h>
#ifdef CONFIG_AML_LCD_EXTERN
-#include "lcd_extern.h"
+//#include "lcd_extern.h"
#endif
-static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
+static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
"GPIOZ_9", /* panel rst */
"GPIOZ_8", /* panel power */
"invalid", /* ending flag */
@@ -129,7 +119,7 @@
0xff, 0, //ending
};
-static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
+static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
"GPIOH_4", /* BL_EN */
"GPIOH_5", /* BL_PWM */
"invalid", /* ending flag */
@@ -230,7 +220,7 @@
},
};
-static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+static struct lcd_pinmux_ctrl_s lcd_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
{
.name = "bl_pwm_on_pin", //GPIOH_5
.pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
@@ -241,154 +231,69 @@
},
};
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xc0, 2, 0x01, 0x2b,
+ 0xc0, 2, 0x02, 0x05,
+ 0xc0, 2, 0x03, 0x00,
+ 0xc0, 2, 0x04, 0x00,
+ 0xc0, 2, 0x05, 0x0c,
+ 0xc0, 2, 0x06, 0x04,
+ 0xc0, 2, 0x07, 0x21,
+ 0xc0, 2, 0x08, 0x0f,
+ 0xc0, 2, 0x09, 0x04,
+ 0xc0, 2, 0x0a, 0x00,
+ 0xc0, 2, 0x0b, 0x04,
+ 0xc0, 2, 0xff, 0x00,
+ 0xfd, 1, 100, /* delay 100ms */
+ 0xff, 0, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0} },
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0} },
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "invalid",
+ /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .type = LCD_EXTERN_MAX,
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x20, /* 7bit i2c address */
+ .i2c_addr2 = 0x74, /* 7bit i2c address, 0xff for none */
+ /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_1,
+ .cmd_size = 0xff,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
#ifdef CONFIG_AML_BL_EXTERN
static unsigned char bl_ext_init_on[BL_EXTERN_INIT_ON_MAX] = {
0xff, 0, //ending flag
};
+
static unsigned char bl_ext_init_off[BL_EXTERN_INIT_OFF_MAX] = {
0xff, 0, //ending flag
};
-#endif
-/* **********************************************
- * driver struct, usually no need modify!
- * ********************************************** */
-static struct dsi_config_s lcd_mipi_config = {
- .lane_num = 4,
- .bit_rate_max = 1000, /* MHz */
- .factor_numerator = 0,
- .factor_denominator = 100,
- .operation_mode_init = 1, /* 0=video mode, 1=command mode */
- .operation_mode_display = 0, /* 0=video mode, 1=command mode */
- .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
- .clk_always_hs = 1, /* 0=disable, 1=enable */
- .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
-
- .dsi_init_on = mipi_init_on_table,
- .dsi_init_off = mipi_init_off_table,
- .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
- .check_en = 0,
- .check_state = 0,
-};
-
-static struct lcd_power_ctrl_s lcd_power_ctrl = {
- .power_on_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
- .power_off_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
-};
-
-struct lcd_config_s lcd_config_dft = {
- .lcd_mode = LCD_MODE_TABLET,
- .lcd_key_valid = 0,
- .lcd_clk_path = 0,
- .lcd_basic = {
- .model_name = "default",
- .lcd_type = LCD_TYPE_MAX,
- .lcd_bits = 8,
- .h_active = 768,
- .v_active = 1024,
- .h_period = 948,
- .v_period = 1140,
-
- .screen_width = 119,
- .screen_height = 159,
- },
-
- .lcd_timing = {
- .clk_auto = 1,
- .lcd_clk = 64843200,
- .ss_level = 0,
- .fr_adjust_type = 0,
-
- .hsync_width = 64,
- .hsync_bp = 56,
- .hsync_pol = 0,
- .vsync_width = 50,
- .vsync_bp = 30,
- .vsync_pol = 0,
- },
-
- .lcd_control = {
- .mipi_config= &lcd_mipi_config,
- },
- .lcd_power = &lcd_power_ctrl,
-
- .pinctrl_ver = 2,
- .lcd_pinmux = lcd_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_LCD_EXTERN
-struct lcd_extern_common_s ext_common_dft = {
- .lcd_ext_key_valid = 0,
- .i2c_bus = LCD_EXTERN_I2C_BUS_0, /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
- .i2c_gpio_sck = LCD_EXT_I2C_GPIO_SCK,
- .i2c_gpio_sda = LCD_EXT_I2C_GPIO_SDA,
- .spi_gpio_cs = LCD_EXT_SPI_GPIO_CS,
- .spi_gpio_clk = LCD_EXT_SPI_GPIO_CLK,
- .spi_gpio_data = LCD_EXT_SPI_GPIO_DATA,
-
- .lcd_ext_pinmux = lcd_ext_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
- .pinmux_gpio_off = LCD_EXT_PINMUX_GPIO_OFF,
-};
-
-struct lcd_extern_config_s ext_config_dtf = {
- .index = 0,
- .name = "ext_default",
- .type = LCD_EXTERN_MAX, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 0, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
-};
-#endif
-
-struct bl_config_s bl_config_dft = {
- .name = "default",
- .bl_key_valid = 0,
-
- .level_default = 100,
- .level_min = 10,
- .level_max = 255,
- .level_mid = 128,
- .level_mid_mapping = 128,
- .level = 0,
-
- .method = BL_CTRL_MAX,
- .power_on_delay = 200,
- .power_off_delay = 200,
-
- .en_gpio = 0xff,
- .en_gpio_on = 1,
- .en_gpio_off = 0,
-
- .bl_pwm = NULL,
- .bl_pwm_combo0 = NULL,
- .bl_pwm_combo1 = NULL,
- .pwm_on_delay = 10,
- .pwm_off_delay = 10,
-
- .bl_extern_index = 0xff,
-
- .pinctrl_ver = 2,
- .bl_pinmux = bl_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_BL_EXTERN
struct bl_extern_config_s bl_extern_config_dtf = {
.index = BL_EXTERN_INDEX_INVALID,
.name = "none",
@@ -406,55 +311,32 @@
.init_off_cnt = sizeof(bl_ext_init_off),
};
#endif
-/* ********************************************** */
+
+/***************************************************
+ * lcd default config
+ ***************************************************/
+static struct lcd_dft_config_s lcd_dft_conf = {
+ .lcd_gpio = lcd_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd_config,
+ .lcd_pinmux = lcd_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd_bl_gpio,
+ .bl_pinmux = lcd_bl_pinmux_ctrl,
+};
void lcd_config_bsp_init(void)
{
- int i, j;
- char *str;
- struct ext_lcd_config_s *ext_lcd = NULL;
+ struct aml_lcd_data_s *pdata = aml_lcd_get_data();
- /* init config, usually no need modify */
- for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
- break;
- strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
- }
- for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
- strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
- for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
- break;
- strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
- }
- for (j = i; j < BL_GPIO_NUM_MAX; j++)
- strcpy(bl_config_dft.gpio_name[j], "invalid");
-
-#ifdef CONFIG_AML_LCD_EXTERN
- for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
- break;
- strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
- }
- for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
- strcpy(ext_common_dft.gpio_name[j], "invalid");
-#endif
-
- /* select special config */
- str = env_get("panel_type");
- if (str == NULL)
- return;
- for (i = 0 ; i < LCD_NUM_MAX ; i++) {
- ext_lcd = &ext_lcd_config[i];
- if (strcmp(ext_lcd->panel_type, str) == 0) {
-#ifdef CONFIG_AML_LCD_EXTERN
- j = ext_lcd->if_attr_val9; /* mipi extern_index */
- if (j < sizeof(ext_config)/sizeof(struct lcd_extern_config_s)) {
- memcpy(&ext_config_dtf, &ext_config[j],
- sizeof(struct lcd_extern_config_s));
- }
-#endif
- break;
- }
- }
+ if (pdata)
+ pdata->dft_conf[0] = &lcd_dft_conf;
}
+
diff --git a/board/amlogic/g12b_w400_v1/lcd_extern.h b/board/amlogic/g12b_w400_v1/lcd_extern.h
index d6c3905..90990e0 100644
--- a/board/amlogic/g12b_w400_v1/lcd_extern.h
+++ b/board/amlogic/g12b_w400_v1/lcd_extern.h
@@ -1,16 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * board/amlogic/g12a_u200_v1/lcd_extern.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef _DFT_LCD_EXTERN_H_
diff --git a/board/amlogic/s4_ap201/Kconfig b/board/amlogic/s4_ap201/Kconfig
new file mode 100644
index 0000000..e745662
--- /dev/null
+++ b/board/amlogic/s4_ap201/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_S4_AP201
+
+config SYS_SOC
+ default "s4"
+
+config SYS_BOARD
+ default "s4_ap201"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "s4_ap201"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+endif
diff --git a/board/amlogic/s4_ap201/Makefile b/board/amlogic/s4_ap201/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/s4_ap201/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/s4_ap201/aml-key/bl2aesiv b/board/amlogic/s4_ap201/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_ap201/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/s4_ap201/aml-key/bl2aeskey b/board/amlogic/s4_ap201/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_ap201/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/s4_ap201/aml-key/bl3xaesiv b/board/amlogic/s4_ap201/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_ap201/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/s4_ap201/aml-key/bl3xaeskey b/board/amlogic/s4_ap201/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_ap201/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/s4_ap201/aml-key/kernelaesiv b/board/amlogic/s4_ap201/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_ap201/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/s4_ap201/aml-key/kernelaeskey b/board/amlogic/s4_ap201/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_ap201/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/s4_ap201/aml-user-key.sig b/board/amlogic/s4_ap201/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/s4_ap201/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/s4_ap201/firmware/timing.c b/board/amlogic/s4_ap201/firmware/timing.c
new file mode 100644
index 0000000..22e9c3b
--- /dev/null
+++ b/board/amlogic/s4_ap201/firmware/timing.c
@@ -0,0 +1,1331 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+#if 1
+{
+ //timing_config,4layer 4pcs ddr4 rank01, ap222.
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[0]) / sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0, 0,(1 << 3) | (2) },
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_1024MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ //af419 ac pinmux
+ #if 0
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3, 27, 12,
+ 21, 9, 8, 0, 14, 10, 6, 7,
+ 20, 5, 22, 13, 15, 2, 0, 0,
+ 0, 0, 11, 26, 4, 0, 0, 25,
+ 3, 1,
+ },
+ #endif
+ //s4 ddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 27, 10, 25, 5, 28, 11, 24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1176,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT01_CS1_ODT01__R_CS0_ODT1_CS1_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR4_WR_ODT_240_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 128,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ },
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000e1,// 225
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000eb,// 235
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000e1,// 225
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000d7,// 215
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000d7,// 215
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000e1,// 225
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000e1,// 225
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000d7,// 215
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x00000130,// 304
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000120,// 288
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000132,// 306
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x00000125,// 293
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x0000012b,// 299
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000115,// 277
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x00000131,// 305
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x0000012d,// 301
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x00000124,// 292
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000134,// 308
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000115,// 277
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x00000141,// 321
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x00000129,// 297
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000137,// 311
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x00000120,// 288
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x0000012a,// 298
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x00000112,// 274
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x00000119,// 281
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x00000115,// 277
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x0000012b,// 299
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x0000011c,// 284
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x00000116,// 278
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x00000120,// 288
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x0000012b,// 299
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x00000113,// 275
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000117,// 279
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000126,// 294
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x00000117,// 279
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000011c,// 284
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x00000113,// 275
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x0000012d,// 301
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000125,// 293
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x0000011e,// 286
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x0000011a,// 282
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000108,// 264
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000121,// 289
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x0000011b,// 283
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x0000012a,// 298
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x0000010c,// 268
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000118,// 280
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000115,// 277
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x0000012f,// 303
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000126,// 294
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000118,// 280
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x0000011d,// 285
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000139,// 313
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x0000011b,// 283
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x0000011e,// 286
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000123,// 291
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000118,// 280
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x0000011b,// 283
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x0000011e,// 286
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x0000012d,// 301
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x0000012c,// 300
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000117,// 279
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000122,// 290
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000118,// 280
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000119,// 281
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x0000011c,// 284
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000118,// 280
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000122,// 290
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x00000376,// 886
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000372,// 882
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000366,// 870
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000036c,// 876
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000378,// 888
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000373,// 883
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x0000036d,// 877
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000371,// 881
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000059,// 89
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000063,// 99
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000075,// 117
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000071,// 113
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000086,// 134
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000079,// 121
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000086,// 134
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000028,// 40
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000003a,// 58
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x0000002e,// 46
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000028,// 40
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x0000002f,// 47
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000031,// 49
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x0000002a,// 42
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000002c,// 44
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x0000004a,// 74
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000034,// 52
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002d,// 45
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000036,// 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000002b,// 43
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000036,// 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x0000004a,// 74
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000038,// 56
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000037,// 55
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000037,// 55
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000027,// 39
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000032,// 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x0000002b,// 43
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000029,// 41
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x0000002a,// 42
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x0000002f,// 47
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x0000004a,// 74
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000041,// 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x0000003f,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000031,// 49
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000049,// 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000040,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000041,// 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x0000004c,// 76
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003a,// 58
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000055,// 85
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x0000005b,// 91
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000053,// 83
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000037,// 55
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x0000004a,// 74
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000053,// 83
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000037,// 55
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000004c,// 76
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x0000003e,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x0000003e,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x0000004a,// 74
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000040,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000046,// 70
+ #endif
+ //total 72
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 48, 40, 48,
+ 40, 48, 40, 48
+ }, //total 44
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
+
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].ac_trace_delay =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].write_dqs_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ .cfg_ddr_training_delay_ps[1].write_dq_bit_delay =
+ {
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ },
+ .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay =
+ {
+ 192, 192, 192, 192, 192, 192, 192, 192
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dqs_delay =
+ {
+ 64, 64, 64, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dq_bit_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, //total 72
+ .cfg_ddr_training_delay_ps[1].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40
+ }, //total 44
+ .cfg_ddr_training_delay_ps[1].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },
+},
+#endif
+#if 0
+{
+ //timing_config,4layer 2pcs ddr4 rank0, gangzhen pcb.
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[0]) / sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0, 0,(1 << 3) | (4) },
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_2048MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ //af419 ac pinmux
+ #if 0
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3, 27, 12,
+ 21, 9, 8, 0, 14, 10, 6, 7,
+ 20, 5, 22, 13, 15, 2, 0, 0,
+ 0, 0, 11, 26, 4, 0, 0, 25,
+ 3, 1,
+ },
+ #endif
+ //s4 ddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 27, 10, 25, 5, 28, 11, 24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 128,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ },
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000c8,// 200
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000c3,// 195
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000b4,// 180
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000010b,// 267
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000000f7,// 247
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000105,// 261
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000f5,// 245
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000e4,// 228
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000ff,// 255
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000fe,// 254
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000f8,// 248
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x0000010e,// 270
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000f3,// 243
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000106,// 262
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000fa,// 250
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000fa,// 250
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000107,// 263
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000fd,// 253
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000e9,// 233
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000ff,// 255
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000ef,// 239
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000f8,// 248
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000f2,// 242
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000fa,// 250
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000f3,// 243
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x00000111,// 273
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000ec,// 236
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x00000103,// 259
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000f9,// 249
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x0000010c,// 268
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000f3,// 243
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000f9,// 249
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000f6,// 246
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000ff,// 255
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000032d,// 813
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000032a,// 810
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000337,// 823
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000344,// 836
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000008c,// 140
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000078,// 120
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x0000007a,// 122
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x00000063,// 99
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000004b,// 75
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x0000003f,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x0000004c,// 76
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000004e,// 78
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x0000003a,// 58
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000053,// 83
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000002e,// 46
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000003a,// 58
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000040,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000002f,// 47
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000054,// 84
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000032,// 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000041,// 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x0000003d,// 61
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+ //total 72
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 48, 40, 48,
+ 40, 48, 40, 48
+ }, //total 44
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
+
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].ac_trace_delay =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].write_dqs_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ .cfg_ddr_training_delay_ps[1].write_dq_bit_delay =
+ {
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ },
+ .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay =
+ {
+ 192, 192, 192, 192, 192, 192, 192, 192
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dqs_delay =
+ {
+ 64, 64, 64, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dq_bit_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, //total 72
+ .cfg_ddr_training_delay_ps[1].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40
+ }, //total 44
+ .cfg_ddr_training_delay_ps[1].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },
+},
+#endif
+{
+ //timing_config,4layer 2pcs ddr4 rank0, ap229.
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[1]) / sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0, 0,(1 << 3) | (4) },
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_2048MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ //af419 ac pinmux
+ #if 0
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3, 27, 12,
+ 21, 9, 8, 0, 14, 10, 6, 7,
+ 20, 5, 22, 13, 15, 2, 0, 0,
+ 0, 0, 11, 26, 4, 0, 0, 25,
+ 3, 1,
+ },
+ #endif
+ //s4 ddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 27, 10, 25, 5, 28, 11, 24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 128,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ },
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000131,// 305
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000136,// 310
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x0000017d,// 381
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x00000174,// 372
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x00000176,// 374
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000160,// 352
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x0000016e,// 366
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000175,// 373
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000143,// 323
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000017b,// 379
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000172,// 370
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x00000178,// 376
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000014f,// 335
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x00000165,// 357
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x00000160,// 352
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x00000175,// 373
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x00000168,// 360
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x00000173,// 371
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x00000178,// 376
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000015f,// 351
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000153,// 339
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000170,// 368
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000015a,// 346
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000015d,// 349
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x00000153,// 339
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x00000421,// 1057
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000420,// 1056
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x0000041a,// 1050
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000041a,// 1050
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000085,// 133
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000093,// 147
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000099,// 153
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000008a,// 138
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000054,// 84
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x0000004f,// 79
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000066,// 102
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000067,// 103
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x0000006c,// 108
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000004f,// 79
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x0000006a,// 106
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000055,// 85
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000041,// 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000069,// 105
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000003f,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+ //total 72
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 48, 40, 48,
+ 40, 48, 40, 48
+ }, //total 44
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
+
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].ac_trace_delay =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].write_dqs_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ .cfg_ddr_training_delay_ps[1].write_dq_bit_delay =
+ {
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ },
+ .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay =
+ {
+ 192, 192, 192, 192, 192, 192, 192, 192
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dqs_delay =
+ {
+ 64, 64, 64, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dq_bit_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, //total 72
+ .cfg_ddr_training_delay_ps[1].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40
+ }, //total 44
+ .cfg_ddr_training_delay_ps[1].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },
+},
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_DDR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .low_console_baud = CONFIG_LOW_CONSOLE_BAUD,
+};
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ {0, 0, 0xffffffff, 0, 0, 0},
+};
+
+/* gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+
+ /* config vddee and vcck pwm - pwm_h and pwm_j*/
+ {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ /* set pwm h and pwm j clock rate to 24M, enable them */
+ {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 24), 0xffffffff, 0, 0, 0},
+ {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 24) , 0xffffffff, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3 */
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0},
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0},
+};
+
+#define DEV_FIP_SIZE 0x300000
+#define DDR_FIP_SIZE 0x40000
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common = {
+ .version = 0x01,
+ .device_fip_container_size = DEV_FIP_SIZE,
+ .device_fip_container_copies = 4,
+ .ddr_fip_container_size = DDR_FIP_SIZE,
+ },
+ .nand = {
+ .version = 0x01,
+ .bbt_pages = 0x1,
+ .bbt_start_block = 20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (1 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 64,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/s4_ap201/fw_arb.cfg b/board/amlogic/s4_ap201/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/s4_ap201/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/s4_ap201/s4_ap201.c b/board/amlogic/s4_ap201/s4_ap201.c
new file mode 100644
index 0000000..f8fa71e
--- /dev/null
+++ b/board/amlogic/s4_ap201/s4_ap201.c
@@ -0,0 +1,391 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#include <amlogic/aml_mtd.h>
+
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
+#endif
+#ifdef CONFIG_AML_CVBS
+#include <amlogic/media/vout/aml_cvbs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+#if !defined(CONFIG_PXP_DDR) //bypass below operations for pxp
+ aml_set_bootsequence(0);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ #if 0
+ active_clk();
+ #endif
+ run_command("gpio set GPIOH_7", 0);
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+#endif// #if !defined(CONFIG_PXP_DDR) //bypass below operations for pxp
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ //default uboot env need before anyone use it
+ if (env_get("default_env")) {
+ printf("factory reset, need default all uboot env.\n");
+ run_command("defenv_reserv; setenv upgrade_step 2; saveenv;", 0);
+ }
+
+#if !defined(CONFIG_PXP_DDR) //bypass below operations for pxp
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+ run_command("run bcb_cmd", 0);
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+#endif// #if !defined(CONFIG_PXP_DDR) //bypass below operations for pxp
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ cvbs_init();
+#endif
+ run_command("amlsecurecheck", 0);
+ run_command("update_tries", 0);
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ (((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) - CONFIG_SYS_MEM_TOP_HIDE);
+#else
+ return ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf1000000UL,
+ .phys = 0xf1000000UL,
+ .size = 0x0f000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ /* update mmu table from bl2 ddr auto detect size */
+#ifdef CONFIG_UPDATE_MMU_TABLE
+ unsigned long nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4);
+ bd_mem_map[0].size = nddrSize;
+#endif
+ //printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+const char * const _env_args_reserve_[] =
+{
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/s4_ap222/Kconfig b/board/amlogic/s4_ap222/Kconfig
new file mode 100644
index 0000000..801edfd
--- /dev/null
+++ b/board/amlogic/s4_ap222/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_S4_AP222
+
+config SYS_SOC
+ default "s4"
+
+config SYS_BOARD
+ default "s4_ap222"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "s4_ap222"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+endif
diff --git a/board/amlogic/s4_ap222/Makefile b/board/amlogic/s4_ap222/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/s4_ap222/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/s4_ap222/aml-key/bl2aesiv b/board/amlogic/s4_ap222/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_ap222/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/s4_ap222/aml-key/bl2aeskey b/board/amlogic/s4_ap222/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_ap222/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/s4_ap222/aml-key/bl3xaesiv b/board/amlogic/s4_ap222/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_ap222/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/s4_ap222/aml-key/bl3xaeskey b/board/amlogic/s4_ap222/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_ap222/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/s4_ap222/aml-key/kernelaesiv b/board/amlogic/s4_ap222/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_ap222/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/s4_ap222/aml-key/kernelaeskey b/board/amlogic/s4_ap222/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_ap222/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/s4_ap222/aml-user-key.sig b/board/amlogic/s4_ap222/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/s4_ap222/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/s4_ap222/firmware/timing.c b/board/amlogic/s4_ap222/firmware/timing.c
new file mode 100644
index 0000000..22e9c3b
--- /dev/null
+++ b/board/amlogic/s4_ap222/firmware/timing.c
@@ -0,0 +1,1331 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+#if 1
+{
+ //timing_config,4layer 4pcs ddr4 rank01, ap222.
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[0]) / sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0, 0,(1 << 3) | (2) },
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_1024MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ //af419 ac pinmux
+ #if 0
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3, 27, 12,
+ 21, 9, 8, 0, 14, 10, 6, 7,
+ 20, 5, 22, 13, 15, 2, 0, 0,
+ 0, 0, 11, 26, 4, 0, 0, 25,
+ 3, 1,
+ },
+ #endif
+ //s4 ddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 27, 10, 25, 5, 28, 11, 24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1176,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT01_CS1_ODT01__R_CS0_ODT1_CS1_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR4_WR_ODT_240_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 128,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ },
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000e1,// 225
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000eb,// 235
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000e1,// 225
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000d7,// 215
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000d7,// 215
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000e1,// 225
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000e1,// 225
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000d7,// 215
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x00000130,// 304
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000120,// 288
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000132,// 306
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x00000125,// 293
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x0000012b,// 299
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000115,// 277
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x00000131,// 305
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x0000012d,// 301
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x00000124,// 292
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000134,// 308
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000115,// 277
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x00000141,// 321
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x00000129,// 297
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000137,// 311
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x00000120,// 288
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x0000012a,// 298
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x00000112,// 274
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x00000119,// 281
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x00000115,// 277
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x0000012b,// 299
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x0000011c,// 284
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x00000116,// 278
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x00000120,// 288
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x0000012b,// 299
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x00000113,// 275
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000117,// 279
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000126,// 294
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x00000117,// 279
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000011c,// 284
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x00000113,// 275
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x0000012d,// 301
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000125,// 293
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x0000011e,// 286
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x0000011a,// 282
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000108,// 264
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000121,// 289
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x0000011b,// 283
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x0000012a,// 298
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x0000010c,// 268
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000118,// 280
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000115,// 277
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x0000012f,// 303
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000126,// 294
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000118,// 280
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x0000011d,// 285
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000139,// 313
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x0000011b,// 283
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x0000011e,// 286
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000123,// 291
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000118,// 280
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x0000011b,// 283
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x0000011e,// 286
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x0000012d,// 301
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x0000012c,// 300
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000117,// 279
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000122,// 290
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000118,// 280
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000119,// 281
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x0000011c,// 284
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000118,// 280
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000122,// 290
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x00000376,// 886
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000372,// 882
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000366,// 870
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000036c,// 876
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000378,// 888
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000373,// 883
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x0000036d,// 877
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000371,// 881
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000059,// 89
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000063,// 99
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000075,// 117
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000071,// 113
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000086,// 134
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000079,// 121
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000086,// 134
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000028,// 40
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000003a,// 58
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x0000002e,// 46
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000028,// 40
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x0000002f,// 47
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000031,// 49
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x0000002a,// 42
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000002c,// 44
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x0000004a,// 74
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000034,// 52
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002d,// 45
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000036,// 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000002b,// 43
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000036,// 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x0000004a,// 74
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000038,// 56
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000037,// 55
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000037,// 55
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000027,// 39
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000032,// 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x0000002b,// 43
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000029,// 41
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x0000002a,// 42
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x0000002f,// 47
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x0000004a,// 74
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000041,// 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x0000003f,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000031,// 49
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000049,// 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000040,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000041,// 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x0000004c,// 76
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003a,// 58
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000055,// 85
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x0000005b,// 91
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000053,// 83
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000037,// 55
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x0000004a,// 74
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000053,// 83
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000037,// 55
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000004c,// 76
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x0000003e,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x0000003e,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x0000004a,// 74
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000040,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000046,// 70
+ #endif
+ //total 72
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 48, 40, 48,
+ 40, 48, 40, 48
+ }, //total 44
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
+
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].ac_trace_delay =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].write_dqs_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ .cfg_ddr_training_delay_ps[1].write_dq_bit_delay =
+ {
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ },
+ .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay =
+ {
+ 192, 192, 192, 192, 192, 192, 192, 192
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dqs_delay =
+ {
+ 64, 64, 64, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dq_bit_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, //total 72
+ .cfg_ddr_training_delay_ps[1].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40
+ }, //total 44
+ .cfg_ddr_training_delay_ps[1].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },
+},
+#endif
+#if 0
+{
+ //timing_config,4layer 2pcs ddr4 rank0, gangzhen pcb.
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[0]) / sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0, 0,(1 << 3) | (4) },
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_2048MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ //af419 ac pinmux
+ #if 0
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3, 27, 12,
+ 21, 9, 8, 0, 14, 10, 6, 7,
+ 20, 5, 22, 13, 15, 2, 0, 0,
+ 0, 0, 11, 26, 4, 0, 0, 25,
+ 3, 1,
+ },
+ #endif
+ //s4 ddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 27, 10, 25, 5, 28, 11, 24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 128,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ },
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000c8,// 200
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000c3,// 195
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000b4,// 180
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000010b,// 267
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000000f7,// 247
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000105,// 261
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000f5,// 245
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000e4,// 228
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000ff,// 255
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000fe,// 254
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000f8,// 248
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x0000010e,// 270
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000f3,// 243
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000106,// 262
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000fa,// 250
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000fa,// 250
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000107,// 263
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000fd,// 253
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000e9,// 233
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000ff,// 255
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000ef,// 239
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000f8,// 248
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000f2,// 242
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000fa,// 250
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000f3,// 243
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x00000111,// 273
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000ec,// 236
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x00000103,// 259
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000f9,// 249
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x0000010c,// 268
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000f3,// 243
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000f9,// 249
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000f6,// 246
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000ff,// 255
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000032d,// 813
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000032a,// 810
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000337,// 823
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000344,// 836
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000008c,// 140
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000078,// 120
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x0000007a,// 122
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x00000063,// 99
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000004b,// 75
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x0000003f,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x0000004c,// 76
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000004e,// 78
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x0000003a,// 58
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000053,// 83
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000002e,// 46
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000003a,// 58
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000040,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000002f,// 47
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000054,// 84
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000032,// 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000041,// 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x0000003d,// 61
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+ //total 72
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 48, 40, 48,
+ 40, 48, 40, 48
+ }, //total 44
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
+
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].ac_trace_delay =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].write_dqs_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ .cfg_ddr_training_delay_ps[1].write_dq_bit_delay =
+ {
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ },
+ .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay =
+ {
+ 192, 192, 192, 192, 192, 192, 192, 192
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dqs_delay =
+ {
+ 64, 64, 64, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dq_bit_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, //total 72
+ .cfg_ddr_training_delay_ps[1].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40
+ }, //total 44
+ .cfg_ddr_training_delay_ps[1].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },
+},
+#endif
+{
+ //timing_config,4layer 2pcs ddr4 rank0, ap229.
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[1]) / sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0, 0,(1 << 3) | (4) },
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_2048MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ //af419 ac pinmux
+ #if 0
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3, 27, 12,
+ 21, 9, 8, 0, 14, 10, 6, 7,
+ 20, 5, 22, 13, 15, 2, 0, 0,
+ 0, 0, 11, 26, 4, 0, 0, 25,
+ 3, 1,
+ },
+ #endif
+ //s4 ddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 27, 10, 25, 5, 28, 11, 24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 128,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ },
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000131,// 305
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000136,// 310
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x0000017d,// 381
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x00000174,// 372
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x00000176,// 374
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000160,// 352
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x0000016e,// 366
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000175,// 373
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000143,// 323
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000017b,// 379
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000172,// 370
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x00000178,// 376
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000014f,// 335
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x00000165,// 357
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x00000160,// 352
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x00000175,// 373
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x00000168,// 360
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x00000173,// 371
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x00000178,// 376
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000015f,// 351
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000153,// 339
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000170,// 368
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000015a,// 346
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000015d,// 349
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x00000153,// 339
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x00000421,// 1057
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000420,// 1056
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x0000041a,// 1050
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000041a,// 1050
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000085,// 133
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000093,// 147
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000099,// 153
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000008a,// 138
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000054,// 84
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x0000004f,// 79
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000066,// 102
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000067,// 103
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x0000006c,// 108
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000004f,// 79
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x0000006a,// 106
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000055,// 85
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000041,// 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000069,// 105
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000003f,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+ //total 72
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 48, 40, 48,
+ 40, 48, 40, 48
+ }, //total 44
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
+
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].ac_trace_delay =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].write_dqs_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ .cfg_ddr_training_delay_ps[1].write_dq_bit_delay =
+ {
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ },
+ .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay =
+ {
+ 192, 192, 192, 192, 192, 192, 192, 192
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dqs_delay =
+ {
+ 64, 64, 64, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dq_bit_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, //total 72
+ .cfg_ddr_training_delay_ps[1].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40
+ }, //total 44
+ .cfg_ddr_training_delay_ps[1].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },
+},
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_DDR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .low_console_baud = CONFIG_LOW_CONSOLE_BAUD,
+};
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ {0, 0, 0xffffffff, 0, 0, 0},
+};
+
+/* gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+
+ /* config vddee and vcck pwm - pwm_h and pwm_j*/
+ {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ /* set pwm h and pwm j clock rate to 24M, enable them */
+ {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 24), 0xffffffff, 0, 0, 0},
+ {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 24) , 0xffffffff, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3 */
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0},
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0},
+};
+
+#define DEV_FIP_SIZE 0x300000
+#define DDR_FIP_SIZE 0x40000
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common = {
+ .version = 0x01,
+ .device_fip_container_size = DEV_FIP_SIZE,
+ .device_fip_container_copies = 4,
+ .ddr_fip_container_size = DDR_FIP_SIZE,
+ },
+ .nand = {
+ .version = 0x01,
+ .bbt_pages = 0x1,
+ .bbt_start_block = 20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (1 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 64,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/s4_ap222/fw_arb.cfg b/board/amlogic/s4_ap222/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/s4_ap222/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/s4_ap222/s4_ap222.c b/board/amlogic/s4_ap222/s4_ap222.c
new file mode 100644
index 0000000..e2406be
--- /dev/null
+++ b/board/amlogic/s4_ap222/s4_ap222.c
@@ -0,0 +1,392 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#include <amlogic/aml_mtd.h>
+
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
+#endif
+#ifdef CONFIG_AML_CVBS
+#include <amlogic/media/vout/aml_cvbs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+#if !defined(CONFIG_PXP_DDR) //bypass below operations for pxp
+ aml_set_bootsequence(0);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ #if 0
+ active_clk();
+ #endif
+ run_command("gpio set GPIOH_7", 0);
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+#endif// #if !defined(CONFIG_PXP_DDR) //bypass below operations for pxp
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ //default uboot env need before anyone use it
+ if (env_get("default_env")) {
+ printf("factory reset, need default all uboot env.\n");
+ run_command("defenv_reserv; setenv upgrade_step 2; saveenv;", 0);
+ }
+
+#if !defined(CONFIG_PXP_DDR) //bypass below operations for pxp
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+ run_command("run bcb_cmd", 0);
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+#endif// #if !defined(CONFIG_PXP_DDR) //bypass below operations for pxp
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ cvbs_init();
+#endif
+ run_command("amlsecurecheck", 0);
+ run_command("update_tries", 0);
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ (((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) - CONFIG_SYS_MEM_TOP_HIDE);
+#else
+ return ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf1000000UL,
+ .phys = 0xf1000000UL,
+ .size = 0x0f000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ /* update mmu table from bl2 ddr auto detect size */
+#ifdef CONFIG_UPDATE_MMU_TABLE
+ unsigned long nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4);
+ bd_mem_map[0].size = nddrSize;
+#endif
+
+ //printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+const char * const _env_args_reserve_[] =
+{
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/s4_ap229/Kconfig b/board/amlogic/s4_ap229/Kconfig
new file mode 100644
index 0000000..8b139f5
--- /dev/null
+++ b/board/amlogic/s4_ap229/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_S4_AP229
+
+config SYS_SOC
+ default "s4"
+
+config SYS_BOARD
+ default "s4_ap229"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "s4_ap229"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+endif
diff --git a/board/amlogic/s4_ap229/Makefile b/board/amlogic/s4_ap229/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/s4_ap229/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/s4_ap229/aml-key/bl2aesiv b/board/amlogic/s4_ap229/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_ap229/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/s4_ap229/aml-key/bl2aeskey b/board/amlogic/s4_ap229/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_ap229/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/s4_ap229/aml-key/bl3xaesiv b/board/amlogic/s4_ap229/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_ap229/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/s4_ap229/aml-key/bl3xaeskey b/board/amlogic/s4_ap229/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_ap229/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/s4_ap229/aml-key/kernelaesiv b/board/amlogic/s4_ap229/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_ap229/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/s4_ap229/aml-key/kernelaeskey b/board/amlogic/s4_ap229/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_ap229/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/s4_ap229/aml-user-key.sig b/board/amlogic/s4_ap229/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/s4_ap229/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/s4_ap229/firmware/timing.c b/board/amlogic/s4_ap229/firmware/timing.c
new file mode 100644
index 0000000..d6ff018
--- /dev/null
+++ b/board/amlogic/s4_ap229/firmware/timing.c
@@ -0,0 +1,951 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+{
+ //timing_config,4layer 2pcs ddr4 rank0, ap229.
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[0]) / sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0, 0,(1 << 3) | (4) },
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_2048MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ //af419 ac pinmux
+ #if 0
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3, 27, 12,
+ 21, 9, 8, 0, 14, 10, 6, 7,
+ 20, 5, 22, 13, 15, 2, 0, 0,
+ 0, 0, 11, 26, 4, 0, 0, 25,
+ 3, 1,
+ },
+ #endif
+ //s4 ddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 27, 10, 25, 5, 28, 11, 24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 128,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ },
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000131,// 305
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000136,// 310
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x0000017d,// 381
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x00000174,// 372
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x00000176,// 374
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000160,// 352
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x0000016e,// 366
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000175,// 373
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000143,// 323
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000017b,// 379
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000172,// 370
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x00000178,// 376
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000014f,// 335
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x00000165,// 357
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x00000160,// 352
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x00000175,// 373
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x00000168,// 360
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x00000173,// 371
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x00000178,// 376
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000015f,// 351
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000153,// 339
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000170,// 368
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000015a,// 346
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000015d,// 349
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x00000153,// 339
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x00000421,// 1057
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000420,// 1056
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x0000041a,// 1050
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000041a,// 1050
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000085,// 133
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000093,// 147
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000099,// 153
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000008a,// 138
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000054,// 84
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x0000004f,// 79
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000066,// 102
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000067,// 103
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x0000006c,// 108
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000004f,// 79
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x0000006a,// 106
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000055,// 85
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000041,// 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000069,// 105
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000003f,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+ //total 72
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 48, 40, 48,
+ 40, 48, 40, 48
+ }, //total 44
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
+
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].ac_trace_delay =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].write_dqs_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ .cfg_ddr_training_delay_ps[1].write_dq_bit_delay =
+ {
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ },
+ .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay =
+ {
+ 192, 192, 192, 192, 192, 192, 192, 192
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dqs_delay =
+ {
+ 64, 64, 64, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dq_bit_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, //total 72
+ .cfg_ddr_training_delay_ps[1].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40
+ }, //total 44
+ .cfg_ddr_training_delay_ps[1].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },
+},
+{
+ //timing_config,4layer 2pcs ddr4 rank0, ap229.
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[1]) / sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0, 0,(1 << 3) | (4) },
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ //af419 ac pinmux
+ #if 0
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3, 27, 12,
+ 21, 9, 8, 0, 14, 10, 6, 7,
+ 20, 5, 22, 13, 15, 2, 0, 0,
+ 0, 0, 11, 26, 4, 0, 0, 25,
+ 3, 1,
+ },
+ #endif
+ //s4 ddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 27, 10, 25, 5, 28, 11, 24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 128,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ },
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000131,// 305
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000136,// 310
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x0000017d,// 381
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x00000174,// 372
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x00000176,// 374
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000160,// 352
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x0000016e,// 366
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000175,// 373
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000143,// 323
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000017b,// 379
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000172,// 370
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x00000178,// 376
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000014f,// 335
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x00000165,// 357
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x00000160,// 352
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x00000175,// 373
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x00000168,// 360
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x00000173,// 371
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x00000178,// 376
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000015f,// 351
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000153,// 339
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000170,// 368
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000015a,// 346
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000015d,// 349
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x00000153,// 339
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x00000421,// 1057
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000420,// 1056
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x0000041a,// 1050
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000041a,// 1050
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000085,// 133
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000093,// 147
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000099,// 153
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000008a,// 138
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000054,// 84
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x0000004f,// 79
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000066,// 102
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000067,// 103
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x0000006c,// 108
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000004f,// 79
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x0000006a,// 106
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000055,// 85
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000041,// 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000069,// 105
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000003f,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+ //total 72
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 48, 40, 48,
+ 40, 48, 40, 48
+ }, //total 44
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
+
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].ac_trace_delay =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].write_dqs_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ .cfg_ddr_training_delay_ps[1].write_dq_bit_delay =
+ {
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ },
+ .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay =
+ {
+ 192, 192, 192, 192, 192, 192, 192, 192
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dqs_delay =
+ {
+ 64, 64, 64, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dq_bit_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, //total 72
+ .cfg_ddr_training_delay_ps[1].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40
+ }, //total 44
+ .cfg_ddr_training_delay_ps[1].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },
+},
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_DDR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .low_console_baud = CONFIG_LOW_CONSOLE_BAUD,
+};
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ {0, 0, 0xffffffff, 0, 0, 0},
+};
+
+/* gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+
+ /* config vddee and vcck pwm - pwm_h and pwm_j*/
+ {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ /* set pwm h and pwm j clock rate to 24M, enable them */
+ {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 24), 0xffffffff, 0, 0, 0},
+ {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 24) , 0xffffffff, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3 */
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0},
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0},
+};
+
+#define DEV_FIP_SIZE 0x300000
+#define DDR_FIP_SIZE 0x40000
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common = {
+ .version = 0x01,
+ .device_fip_container_size = DEV_FIP_SIZE,
+ .device_fip_container_copies = 4,
+ .ddr_fip_container_size = DDR_FIP_SIZE,
+ },
+ .nand = {
+ .version = 0x01,
+ .bbt_pages = 0x1,
+ .bbt_start_block = 20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (1 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 64,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/s4_ap229/fw_arb.cfg b/board/amlogic/s4_ap229/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/s4_ap229/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/s4_ap229/s4_ap229.c b/board/amlogic/s4_ap229/s4_ap229.c
new file mode 100644
index 0000000..f341612
--- /dev/null
+++ b/board/amlogic/s4_ap229/s4_ap229.c
@@ -0,0 +1,390 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#include <amlogic/aml_mtd.h>
+
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
+#endif
+#ifdef CONFIG_AML_CVBS
+#include <amlogic/media/vout/aml_cvbs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+#if !defined(CONFIG_PXP_DDR) //bypass below operations for pxp
+ aml_set_bootsequence(0);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ active_clk();
+ run_command("gpio set GPIOH_7", 0);
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+#endif// #if !defined(CONFIG_PXP_DDR) //bypass below operations for pxp
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ //default uboot env need before anyone use it
+ if (env_get("default_env")) {
+ printf("factory reset, need default all uboot env.\n");
+ run_command("defenv_reserv; setenv upgrade_step 2; saveenv;", 0);
+ }
+
+#if !defined(CONFIG_PXP_DDR) //bypass below operations for pxp
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+ run_command("run bcb_cmd", 0);
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+#endif// #if !defined(CONFIG_PXP_DDR) //bypass below operations for pxp
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ cvbs_init();
+#endif
+ run_command("amlsecurecheck", 0);
+ run_command("update_tries", 0);
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ (((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) - CONFIG_SYS_MEM_TOP_HIDE);
+#else
+ return ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf1000000UL,
+ .phys = 0xf1000000UL,
+ .size = 0x0f000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ /* update mmu table from bl2 ddr auto detect size */
+#ifdef CONFIG_UPDATE_MMU_TABLE
+ unsigned long nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4);
+ bd_mem_map[0].size = nddrSize;
+#endif
+
+ //printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+const char * const _env_args_reserve_[] =
+{
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/s4_aq222/Kconfig b/board/amlogic/s4_aq222/Kconfig
new file mode 100644
index 0000000..593ddf7
--- /dev/null
+++ b/board/amlogic/s4_aq222/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_S4_AQ222
+
+config SYS_SOC
+ default "s4"
+
+config SYS_BOARD
+ default "s4_aq222"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "s4_aq222"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+endif
diff --git a/board/amlogic/s4_aq222/Makefile b/board/amlogic/s4_aq222/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/s4_aq222/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/s4_aq222/aml-key/bl2aesiv b/board/amlogic/s4_aq222/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_aq222/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/s4_aq222/aml-key/bl2aeskey b/board/amlogic/s4_aq222/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_aq222/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/s4_aq222/aml-key/bl3xaesiv b/board/amlogic/s4_aq222/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_aq222/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/s4_aq222/aml-key/bl3xaeskey b/board/amlogic/s4_aq222/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_aq222/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/s4_aq222/aml-key/kernelaesiv b/board/amlogic/s4_aq222/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_aq222/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/s4_aq222/aml-key/kernelaeskey b/board/amlogic/s4_aq222/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_aq222/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/s4_aq222/aml-user-key.sig b/board/amlogic/s4_aq222/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/s4_aq222/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/s4_aq222/firmware/timing.c b/board/amlogic/s4_aq222/firmware/timing.c
new file mode 100644
index 0000000..22e9c3b
--- /dev/null
+++ b/board/amlogic/s4_aq222/firmware/timing.c
@@ -0,0 +1,1331 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+#if 1
+{
+ //timing_config,4layer 4pcs ddr4 rank01, ap222.
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[0]) / sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0, 0,(1 << 3) | (2) },
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_1024MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ //af419 ac pinmux
+ #if 0
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3, 27, 12,
+ 21, 9, 8, 0, 14, 10, 6, 7,
+ 20, 5, 22, 13, 15, 2, 0, 0,
+ 0, 0, 11, 26, 4, 0, 0, 25,
+ 3, 1,
+ },
+ #endif
+ //s4 ddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 27, 10, 25, 5, 28, 11, 24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1176,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT01_CS1_ODT01__R_CS0_ODT1_CS1_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR4_WR_ODT_240_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 128,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ },
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000e1,// 225
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000eb,// 235
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000e1,// 225
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000d7,// 215
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x000000d7,// 215
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x000000e1,// 225
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x000000e1,// 225
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x000000d7,// 215
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x00000130,// 304
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000120,// 288
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000132,// 306
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x00000125,// 293
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x0000012b,// 299
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000115,// 277
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x00000131,// 305
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x0000012d,// 301
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x00000124,// 292
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000134,// 308
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000115,// 277
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x00000141,// 321
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x00000129,// 297
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000137,// 311
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x00000120,// 288
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x0000012a,// 298
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x00000112,// 274
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x00000119,// 281
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x00000115,// 277
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x0000012b,// 299
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x0000011c,// 284
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x00000116,// 278
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x00000120,// 288
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x0000012b,// 299
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x00000113,// 275
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000117,// 279
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000126,// 294
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x00000117,// 279
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000011c,// 284
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x00000113,// 275
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x0000012d,// 301
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000125,// 293
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x0000011e,// 286
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x0000011a,// 282
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000108,// 264
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000121,// 289
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x0000011b,// 283
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x0000012a,// 298
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x0000010c,// 268
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000118,// 280
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000115,// 277
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x0000012f,// 303
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x0000011f,// 287
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000126,// 294
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000118,// 280
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x0000011d,// 285
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000139,// 313
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x0000011b,// 283
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x0000011e,// 286
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000123,// 291
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000118,// 280
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x0000011b,// 283
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x0000011e,// 286
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x0000012d,// 301
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x0000012c,// 300
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000117,// 279
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000122,// 290
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000118,// 280
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000119,// 281
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x0000011c,// 284
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000118,// 280
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000122,// 290
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x00000376,// 886
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000372,// 882
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000366,// 870
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000036c,// 876
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000378,// 888
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000373,// 883
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x0000036d,// 877
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000371,// 881
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000059,// 89
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000063,// 99
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000075,// 117
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000071,// 113
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000086,// 134
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000079,// 121
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000086,// 134
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x00000028,// 40
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000003a,// 58
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x0000002e,// 46
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000028,// 40
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x0000002f,// 47
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000031,// 49
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x0000002a,// 42
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000002c,// 44
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x0000004a,// 74
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x00000034,// 52
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000002d,// 45
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000036,// 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000002b,// 43
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000036,// 54
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x0000002c,// 44
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x0000004a,// 74
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000003b,// 59
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x00000038,// 56
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000037,// 55
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000037,// 55
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000027,// 39
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000032,// 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x0000002b,// 43
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x0000003e,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000029,// 41
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000031,// 49
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x0000002a,// 42
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x0000002f,// 47
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x0000004a,// 74
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000041,// 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x0000003f,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000031,// 49
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000049,// 73
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000040,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000041,// 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x0000004c,// 76
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x0000003a,// 58
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000055,// 85
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x0000005b,// 91
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000053,// 83
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000037,// 55
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x0000004a,// 74
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000053,// 83
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000037,// 55
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x0000004c,// 76
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x0000003e,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x0000003e,// 62
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x0000004a,// 74
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000040,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000046,// 70
+ #endif
+ //total 72
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 48, 40, 48,
+ 40, 48, 40, 48
+ }, //total 44
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
+
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].ac_trace_delay =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].write_dqs_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ .cfg_ddr_training_delay_ps[1].write_dq_bit_delay =
+ {
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ },
+ .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay =
+ {
+ 192, 192, 192, 192, 192, 192, 192, 192
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dqs_delay =
+ {
+ 64, 64, 64, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dq_bit_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, //total 72
+ .cfg_ddr_training_delay_ps[1].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40
+ }, //total 44
+ .cfg_ddr_training_delay_ps[1].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },
+},
+#endif
+#if 0
+{
+ //timing_config,4layer 2pcs ddr4 rank0, gangzhen pcb.
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[0]) / sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0, 0,(1 << 3) | (4) },
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_2048MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ //af419 ac pinmux
+ #if 0
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3, 27, 12,
+ 21, 9, 8, 0, 14, 10, 6, 7,
+ 20, 5, 22, 13, 15, 2, 0, 0,
+ 0, 0, 11, 26, 4, 0, 0, 25,
+ 3, 1,
+ },
+ #endif
+ //s4 ddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 27, 10, 25, 5, 28, 11, 24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 128,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ },
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x000000c8,// 200
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x000000c3,// 195
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x000000b4,// 180
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x000000af,// 175
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000010b,// 267
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x000000f7,// 247
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x00000105,// 261
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x000000f5,// 245
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x000000e4,// 228
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x000000ff,// 255
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x000000fe,// 254
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x000000f8,// 248
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x0000010e,// 270
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x000000f3,// 243
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x00000106,// 262
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x000000fa,// 250
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x000000fa,// 250
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000107,// 263
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x000000fd,// 253
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x000000e9,// 233
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x000000ff,// 255
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x000000ef,// 239
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x00000100,// 256
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x000000f8,// 248
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x000000f2,// 242
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x000000fa,// 250
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x000000f3,// 243
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x00000111,// 273
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x000000ec,// 236
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x00000103,// 259
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x000000f9,// 249
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x0000010c,// 268
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x000000f3,// 243
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x000000f9,// 249
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x000000f6,// 246
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x000000ff,// 255
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x0000032d,// 813
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x0000032a,// 810
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x00000337,// 823
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x00000344,// 836
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x0000008c,// 140
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000078,// 120
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x0000007a,// 122
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x00000063,// 99
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000004b,// 75
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x0000003f,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x0000004c,// 76
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x0000004e,// 78
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x0000003a,// 58
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000053,// 83
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x0000002e,// 46
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000003a,// 58
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000040,// 64
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000050,// 80
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000002f,// 47
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000047,// 71
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000054,// 84
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000043,// 67
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000032,// 50
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x00000041,// 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x0000003d,// 61
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+ //total 72
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 48, 40, 48,
+ 40, 48, 40, 48
+ }, //total 44
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
+
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].ac_trace_delay =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].write_dqs_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ .cfg_ddr_training_delay_ps[1].write_dq_bit_delay =
+ {
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ },
+ .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay =
+ {
+ 192, 192, 192, 192, 192, 192, 192, 192
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dqs_delay =
+ {
+ 64, 64, 64, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dq_bit_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, //total 72
+ .cfg_ddr_training_delay_ps[1].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40
+ }, //total 44
+ .cfg_ddr_training_delay_ps[1].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },
+},
+#endif
+{
+ //timing_config,4layer 2pcs ddr4 rank0, ap229.
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[1]) / sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0, 0,(1 << 3) | (4) },
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_2048MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ //af419 ac pinmux
+ #if 0
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3, 27, 12,
+ 21, 9, 8, 0, 14, 10, 6, 7,
+ 20, 5, 22, 13, 15, 2, 0, 0,
+ 0, 0, 11, 26, 4, 0, 0, 25,
+ 3, 1,
+ },
+ #endif
+ //s4 ddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 27, 10, 25, 5, 28, 11, 24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 128,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ },
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000131,// 305
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000136,// 310
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x0000017d,// 381
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x00000174,// 372
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x00000176,// 374
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000160,// 352
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x0000016e,// 366
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000175,// 373
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000143,// 323
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000017b,// 379
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000172,// 370
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x00000178,// 376
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000014f,// 335
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x00000165,// 357
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x00000160,// 352
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x00000175,// 373
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x00000168,// 360
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x00000173,// 371
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x00000178,// 376
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000015f,// 351
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000153,// 339
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000170,// 368
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000015a,// 346
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000015d,// 349
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x00000153,// 339
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x00000421,// 1057
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000420,// 1056
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x0000041a,// 1050
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000041a,// 1050
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000085,// 133
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000093,// 147
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000099,// 153
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000008a,// 138
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000054,// 84
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x0000004f,// 79
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000066,// 102
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000067,// 103
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x0000006c,// 108
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000004f,// 79
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x0000006a,// 106
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000055,// 85
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000041,// 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000069,// 105
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000003f,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+ //total 72
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 48, 40, 48,
+ 40, 48, 40, 48
+ }, //total 44
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
+
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].ac_trace_delay =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].write_dqs_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ .cfg_ddr_training_delay_ps[1].write_dq_bit_delay =
+ {
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ },
+ .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay =
+ {
+ 192, 192, 192, 192, 192, 192, 192, 192
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dqs_delay =
+ {
+ 64, 64, 64, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dq_bit_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, //total 72
+ .cfg_ddr_training_delay_ps[1].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40
+ }, //total 44
+ .cfg_ddr_training_delay_ps[1].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },
+},
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_DDR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .low_console_baud = CONFIG_LOW_CONSOLE_BAUD,
+};
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ {0, 0, 0xffffffff, 0, 0, 0},
+};
+
+/* gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+
+ /* config vddee and vcck pwm - pwm_h and pwm_j*/
+ {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ /* set pwm h and pwm j clock rate to 24M, enable them */
+ {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 24), 0xffffffff, 0, 0, 0},
+ {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 24) , 0xffffffff, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3 */
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0},
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0},
+};
+
+#define DEV_FIP_SIZE 0x300000
+#define DDR_FIP_SIZE 0x40000
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common = {
+ .version = 0x01,
+ .device_fip_container_size = DEV_FIP_SIZE,
+ .device_fip_container_copies = 4,
+ .ddr_fip_container_size = DDR_FIP_SIZE,
+ },
+ .nand = {
+ .version = 0x01,
+ .bbt_pages = 0x1,
+ .bbt_start_block = 20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (1 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 64,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/s4_aq222/fw_arb.cfg b/board/amlogic/s4_aq222/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/s4_aq222/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/s4_aq222/s4_aq222.c b/board/amlogic/s4_aq222/s4_aq222.c
new file mode 100644
index 0000000..85754ad
--- /dev/null
+++ b/board/amlogic/s4_aq222/s4_aq222.c
@@ -0,0 +1,393 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#include <amlogic/aml_mtd.h>
+
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
+#endif
+#ifdef CONFIG_AML_CVBS
+#include <amlogic/media/vout/aml_cvbs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+#if !defined(CONFIG_PXP_DDR) //bypass below operations for pxp
+ aml_set_bootsequence(0);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ #if 0
+ active_clk();
+ #endif
+#endif
+ run_command("gpio set GPIOH_7", 0);
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ //default uboot env need before anyone use it
+ if (env_get("default_env")) {
+ printf("factory reset, need default all uboot env.\n");
+ run_command("defenv_reserv; setenv upgrade_step 2; saveenv;", 0);
+ }
+
+#if !defined(CONFIG_PXP_DDR) //bypass below operations for pxp
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+ run_command("run bcb_cmd", 0);
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+#endif// #if !defined(CONFIG_PXP_DDR) //bypass below operations for pxp
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ cvbs_init();
+#endif
+ run_command("amlsecurecheck", 0);
+ run_command("update_tries", 0);
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ (((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) - CONFIG_SYS_MEM_TOP_HIDE);
+#else
+ return ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf1000000UL,
+ .phys = 0xf1000000UL,
+ .size = 0x0f000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ /* update mmu table from bl2 ddr auto detect size */
+#ifdef CONFIG_UPDATE_MMU_TABLE
+ unsigned long nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4);
+ bd_mem_map[0].size = nddrSize;
+#endif
+
+ //printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+const char * const _env_args_reserve_[] =
+{
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/s4_aq229/Kconfig b/board/amlogic/s4_aq229/Kconfig
new file mode 100644
index 0000000..da68be2
--- /dev/null
+++ b/board/amlogic/s4_aq229/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_S4_AQ229
+
+config SYS_SOC
+ default "s4"
+
+config SYS_BOARD
+ default "s4_aq229"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "s4_aq229"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+endif
diff --git a/board/amlogic/s4_aq229/Makefile b/board/amlogic/s4_aq229/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/s4_aq229/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/s4_aq229/aml-key/bl2aesiv b/board/amlogic/s4_aq229/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_aq229/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/s4_aq229/aml-key/bl2aeskey b/board/amlogic/s4_aq229/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_aq229/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/s4_aq229/aml-key/bl3xaesiv b/board/amlogic/s4_aq229/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_aq229/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/s4_aq229/aml-key/bl3xaeskey b/board/amlogic/s4_aq229/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_aq229/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/s4_aq229/aml-key/kernelaesiv b/board/amlogic/s4_aq229/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_aq229/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/s4_aq229/aml-key/kernelaeskey b/board/amlogic/s4_aq229/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_aq229/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/s4_aq229/aml-user-key.sig b/board/amlogic/s4_aq229/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/s4_aq229/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/s4_aq229/firmware/timing.c b/board/amlogic/s4_aq229/firmware/timing.c
new file mode 100644
index 0000000..3b6ab5c
--- /dev/null
+++ b/board/amlogic/s4_aq229/firmware/timing.c
@@ -0,0 +1,951 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+{
+ //timing_config,4layer 2pcs ddr4 rank0, aq229.
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[0]) / sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0, 0,(1 << 3) | (4) },
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_2048MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ //af419 ac pinmux
+ #if 0
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3, 27, 12,
+ 21, 9, 8, 0, 14, 10, 6, 7,
+ 20, 5, 22, 13, 15, 2, 0, 0,
+ 0, 0, 11, 26, 4, 0, 0, 25,
+ 3, 1,
+ },
+ #endif
+ //s4 ddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 27, 10, 25, 5, 28, 11, 24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 128,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ },
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000131,// 305
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000136,// 310
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x0000017d,// 381
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x00000174,// 372
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x00000176,// 374
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000160,// 352
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x0000016e,// 366
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000175,// 373
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000143,// 323
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000017b,// 379
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000172,// 370
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x00000178,// 376
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000014f,// 335
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x00000165,// 357
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x00000160,// 352
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x00000175,// 373
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x00000168,// 360
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x00000173,// 371
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x00000178,// 376
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000015f,// 351
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000153,// 339
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000170,// 368
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000015a,// 346
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000015d,// 349
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x00000153,// 339
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x00000421,// 1057
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000420,// 1056
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x0000041a,// 1050
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000041a,// 1050
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000085,// 133
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000093,// 147
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000099,// 153
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000008a,// 138
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000054,// 84
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x0000004f,// 79
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000066,// 102
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000067,// 103
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x0000006c,// 108
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000004f,// 79
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x0000006a,// 106
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000055,// 85
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000041,// 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000069,// 105
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000003f,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+ //total 72
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 48, 40, 48,
+ 40, 48, 40, 48
+ }, //total 44
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
+
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].ac_trace_delay =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].write_dqs_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ .cfg_ddr_training_delay_ps[1].write_dq_bit_delay =
+ {
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ },
+ .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay =
+ {
+ 192, 192, 192, 192, 192, 192, 192, 192
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dqs_delay =
+ {
+ 64, 64, 64, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dq_bit_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, //total 72
+ .cfg_ddr_training_delay_ps[1].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40
+ }, //total 44
+ .cfg_ddr_training_delay_ps[1].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },
+},
+{
+ //timing_config,4layer 2pcs ddr4 rank0, ap229.
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[1]) / sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0, 0,(1 << 3) | (4) },
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ //af419 ac pinmux
+ #if 0
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3, 27, 12,
+ 21, 9, 8, 0, 14, 10, 6, 7,
+ 20, 5, 22, 13, 15, 2, 0, 0,
+ 0, 0, 11, 26, 4, 0, 0, 25,
+ 3, 1,
+ },
+ #endif
+ //s4 ddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 27, 10, 25, 5, 28, 11, 24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 128,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ },
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000131,// 305
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000136,// 310
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x0000017d,// 381
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x00000174,// 372
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x00000176,// 374
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000160,// 352
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x0000016e,// 366
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000175,// 373
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000143,// 323
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000017b,// 379
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000172,// 370
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x00000178,// 376
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000014f,// 335
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x00000165,// 357
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x00000160,// 352
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x00000175,// 373
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x00000168,// 360
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x00000173,// 371
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x00000178,// 376
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000015f,// 351
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000153,// 339
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000170,// 368
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000015a,// 346
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000015d,// 349
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x00000153,// 339
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x00000421,// 1057
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000420,// 1056
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x0000041a,// 1050
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000041a,// 1050
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000085,// 133
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000093,// 147
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000099,// 153
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000008a,// 138
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000054,// 84
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x0000004f,// 79
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000066,// 102
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000067,// 103
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x0000006c,// 108
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000004f,// 79
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x0000006a,// 106
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000055,// 85
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000041,// 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000069,// 105
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000003f,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+ //total 72
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 48, 40, 48,
+ 40, 48, 40, 48
+ }, //total 44
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
+
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].ac_trace_delay =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].write_dqs_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ .cfg_ddr_training_delay_ps[1].write_dq_bit_delay =
+ {
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ },
+ .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay =
+ {
+ 192, 192, 192, 192, 192, 192, 192, 192
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dqs_delay =
+ {
+ 64, 64, 64, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dq_bit_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, //total 72
+ .cfg_ddr_training_delay_ps[1].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40
+ }, //total 44
+ .cfg_ddr_training_delay_ps[1].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },
+},
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_DDR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .low_console_baud = CONFIG_LOW_CONSOLE_BAUD,
+};
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ {0, 0, 0xffffffff, 0, 0, 0},
+};
+
+/* gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+
+ /* config vddee and vcck pwm - pwm_h and pwm_j*/
+ {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ /* set pwm h and pwm j clock rate to 24M, enable them */
+ {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 24), 0xffffffff, 0, 0, 0},
+ {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 24) , 0xffffffff, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3 */
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0},
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0},
+};
+
+#define DEV_FIP_SIZE 0x300000
+#define DDR_FIP_SIZE 0x40000
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common = {
+ .version = 0x01,
+ .device_fip_container_size = DEV_FIP_SIZE,
+ .device_fip_container_copies = 4,
+ .ddr_fip_container_size = DDR_FIP_SIZE,
+ },
+ .nand = {
+ .version = 0x01,
+ .bbt_pages = 0x1,
+ .bbt_start_block = 20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (1 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 64,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/s4_aq229/fw_arb.cfg b/board/amlogic/s4_aq229/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/s4_aq229/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/s4_aq229/s4_aq229.c b/board/amlogic/s4_aq229/s4_aq229.c
new file mode 100644
index 0000000..10ef27e
--- /dev/null
+++ b/board/amlogic/s4_aq229/s4_aq229.c
@@ -0,0 +1,391 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#include <amlogic/aml_mtd.h>
+
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
+#endif
+#ifdef CONFIG_AML_CVBS
+#include <amlogic/media/vout/aml_cvbs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+#if !defined(CONFIG_PXP_DDR) //bypass below operations for pxp
+ aml_set_bootsequence(0);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ #if 0
+ active_clk();
+ #endif
+#endif
+ run_command("gpio set GPIOH_7", 0);
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ //default uboot env need before anyone use it
+ if (env_get("default_env")) {
+ printf("factory reset, need default all uboot env.\n");
+ run_command("defenv_reserv; setenv upgrade_step 2; saveenv;", 0);
+ }
+
+#if !defined(CONFIG_PXP_DDR) //bypass below operations for pxp
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+ run_command("run bcb_cmd", 0);
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+#endif// #if !defined(CONFIG_PXP_DDR) //bypass below operations for pxp
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ cvbs_init();
+#endif
+ run_command("amlsecurecheck", 0);
+ run_command("update_tries", 0);
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ (((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) - CONFIG_SYS_MEM_TOP_HIDE);
+#else
+ return ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf1000000UL,
+ .phys = 0xf1000000UL,
+ .size = 0x0f000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ /* update mmu table from bl2 ddr auto detect size */
+#ifdef CONFIG_UPDATE_MMU_TABLE
+ unsigned long nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4);
+ bd_mem_map[0].size = nddrSize;
+#endif
+ //printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+const char * const _env_args_reserve_[] =
+{
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/s4_skt/Kconfig b/board/amlogic/s4_skt/Kconfig
new file mode 100644
index 0000000..dad01b6
--- /dev/null
+++ b/board/amlogic/s4_skt/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_S4_SKT
+
+config SYS_SOC
+ default "s4"
+
+config SYS_BOARD
+ default "s4_skt"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "s4_skt"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+endif
diff --git a/board/amlogic/s4_skt/Makefile b/board/amlogic/s4_skt/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/s4_skt/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/s4_skt/aml-key/bl2aesiv b/board/amlogic/s4_skt/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_skt/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/s4_skt/aml-key/bl2aeskey b/board/amlogic/s4_skt/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_skt/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/s4_skt/aml-key/bl3xaesiv b/board/amlogic/s4_skt/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_skt/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/s4_skt/aml-key/bl3xaeskey b/board/amlogic/s4_skt/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_skt/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/s4_skt/aml-key/kernelaesiv b/board/amlogic/s4_skt/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_skt/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/s4_skt/aml-key/kernelaeskey b/board/amlogic/s4_skt/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_skt/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/s4_skt/aml-user-key.sig b/board/amlogic/s4_skt/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/s4_skt/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/s4_skt/firmware/timing.c b/board/amlogic/s4_skt/firmware/timing.c
new file mode 100644
index 0000000..d6ff018
--- /dev/null
+++ b/board/amlogic/s4_skt/firmware/timing.c
@@ -0,0 +1,951 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+{
+ //timing_config,4layer 2pcs ddr4 rank0, ap229.
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[0]) / sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0, 0,(1 << 3) | (4) },
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_2048MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ //af419 ac pinmux
+ #if 0
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3, 27, 12,
+ 21, 9, 8, 0, 14, 10, 6, 7,
+ 20, 5, 22, 13, 15, 2, 0, 0,
+ 0, 0, 11, 26, 4, 0, 0, 25,
+ 3, 1,
+ },
+ #endif
+ //s4 ddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 27, 10, 25, 5, 28, 11, 24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 128,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ },
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000131,// 305
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000136,// 310
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x0000017d,// 381
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x00000174,// 372
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x00000176,// 374
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000160,// 352
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x0000016e,// 366
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000175,// 373
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000143,// 323
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000017b,// 379
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000172,// 370
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x00000178,// 376
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000014f,// 335
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x00000165,// 357
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x00000160,// 352
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x00000175,// 373
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x00000168,// 360
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x00000173,// 371
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x00000178,// 376
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000015f,// 351
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000153,// 339
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000170,// 368
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000015a,// 346
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000015d,// 349
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x00000153,// 339
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x00000421,// 1057
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000420,// 1056
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x0000041a,// 1050
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000041a,// 1050
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000085,// 133
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000093,// 147
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000099,// 153
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000008a,// 138
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000054,// 84
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x0000004f,// 79
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000066,// 102
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000067,// 103
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x0000006c,// 108
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000004f,// 79
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x0000006a,// 106
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000055,// 85
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000041,// 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000069,// 105
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000003f,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+ //total 72
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 48, 40, 48,
+ 40, 48, 40, 48
+ }, //total 44
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
+
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].ac_trace_delay =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].write_dqs_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ .cfg_ddr_training_delay_ps[1].write_dq_bit_delay =
+ {
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ },
+ .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay =
+ {
+ 192, 192, 192, 192, 192, 192, 192, 192
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dqs_delay =
+ {
+ 64, 64, 64, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dq_bit_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, //total 72
+ .cfg_ddr_training_delay_ps[1].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40
+ }, //total 44
+ .cfg_ddr_training_delay_ps[1].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },
+},
+{
+ //timing_config,4layer 2pcs ddr4 rank0, ap229.
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[1]) / sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0, 0,(1 << 3) | (4) },
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting.pll_ssc_mode = DDR_PLL_SSC_DISABLE,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ //af419 ac pinmux
+ #if 0
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3, 27, 12,
+ 21, 9, 8, 0, 14, 10, 6, 7,
+ 20, 5, 22, 13, 15, 2, 0, 0,
+ 0, 0, 11, 26, 4, 0, 0, 25,
+ 3, 1,
+ },
+ #endif
+ //s4 ddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 27, 10, 25, 5, 28, 11, 24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ .cfg_board_SI_setting_ps[0].DRAMFreq = 1320,
+ .cfg_board_SI_setting_ps[0].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[0].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[0].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[0].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[0].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[0].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[0].reserve2 = 0,
+ .cfg_board_SI_setting_ps[0].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[0].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[0].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[0].ac_trace_delay_org =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 128,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].ac_trace_delay =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ },
+
+ #if 1
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[0]=0x00000131,// 305
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[1]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[2]=0x00000136,// 310
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[3]=0x00000127,// 295
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[4]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[5]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[6]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dqs_delay[7]=0x00000102,// 258
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[0]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[1]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[2]=0x0000017d,// 381
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[3]=0x00000174,// 372
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[4]=0x00000176,// 374
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[5]=0x00000160,// 352
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[6]=0x0000017c,// 380
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[7]=0x0000017a,// 378
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[8]=0x0000016e,// 366
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[9]=0x00000175,// 373
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[10]=0x00000143,// 323
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[11]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[12]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[13]=0x0000017b,// 379
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[14]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[15]=0x00000172,// 370
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[16]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[17]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[18]=0x00000178,// 376
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[19]=0x0000014f,// 335
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[20]=0x00000165,// 357
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[21]=0x00000160,// 352
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[22]=0x00000175,// 373
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[23]=0x00000168,// 360
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[24]=0x0000015e,// 350
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[25]=0x00000173,// 371
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[26]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[27]=0x00000178,// 376
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[28]=0x0000015c,// 348
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[29]=0x0000015f,// 351
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[30]=0x00000153,// 339
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[31]=0x00000170,// 368
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[32]=0x0000015a,// 346
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[33]=0x0000015d,// 349
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[34]=0x00000153,// 339
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[35]=0x00000164,// 356
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].write_dq_bit_delay[71]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[0]=0x00000421,// 1057
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[1]=0x00000420,// 1056
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[2]=0x0000041a,// 1050
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[3]=0x0000041a,// 1050
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_gate_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[0]=0x00000085,// 133
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[1]=0x00000093,// 147
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[2]=0x00000099,// 153
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[3]=0x0000008a,// 138
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[4]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[5]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[6]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dqs_delay[7]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[0]=0x00000054,// 84
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[1]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[2]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[3]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[4]=0x0000004f,// 79
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[5]=0x00000030,// 48
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[6]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[7]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[8]=0x00000048,// 72
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[9]=0x00000066,// 102
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[10]=0x00000039,// 57
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[11]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[12]=0x00000042,// 66
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[13]=0x00000067,// 103
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[14]=0x0000004d,// 77
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[15]=0x0000005f,// 95
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[16]=0x00000046,// 70
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[17]=0x00000051,// 81
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[18]=0x00000057,// 87
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[19]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[20]=0x00000052,// 82
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[21]=0x00000045,// 69
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[22]=0x0000006c,// 108
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[23]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[24]=0x0000004f,// 79
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[25]=0x0000006a,// 106
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[26]=0x00000055,// 85
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[27]=0x00000060,// 96
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[28]=0x0000003c,// 60
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[29]=0x00000041,// 65
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[30]=0x00000035,// 53
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[31]=0x00000069,// 105
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[32]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[33]=0x0000003f,// 63
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[34]=0x00000033,// 51
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[35]=0x00000044,// 68
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[36]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[37]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[38]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[39]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[40]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[41]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[42]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[43]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[44]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[45]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[46]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[47]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[48]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[49]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[50]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[51]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[52]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[53]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[54]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[55]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[56]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[57]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[58]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[59]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[60]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[61]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[62]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[63]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[64]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[65]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[66]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[67]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[68]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[69]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[70]=0x00000000,// 0
+ .cfg_ddr_training_delay_ps[0].read_dq_bit_delay[71]=0x00000000,// 0
+ #endif
+ //total 72
+ .cfg_ddr_training_delay_ps[0].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 48, 40, 48,
+ 40, 48, 40, 48
+ }, //total 44
+ .cfg_ddr_training_delay_ps[0].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[0].reserve_training_parameter = { 0 },
+
+ .cfg_board_SI_setting_ps[1].DRAMFreq = 667,
+ .cfg_board_SI_setting_ps[1].PllBypassEn = 0,
+ .cfg_board_SI_setting_ps[1].training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps[1].ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps[1].clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps[1].dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps[1].lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps[1].reserve2 = 0,
+ .cfg_board_SI_setting_ps[1].vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps[1].max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps[1].training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps[1].ac_trace_delay_org =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].ac_trace_delay =
+ {
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128, 128, 128, 128, 128,
+ 128, 128, 128, 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].write_dqs_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+ .cfg_ddr_training_delay_ps[1].write_dq_bit_delay =
+ {
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ 50, 50, 50, 50, 50, 50, 50, 50,
+ },
+ .cfg_ddr_training_delay_ps[1].read_dqs_gate_delay =
+ {
+ 192, 192, 192, 192, 192, 192, 192, 192
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dqs_delay =
+ {
+ 64, 64, 64, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps[1].read_dq_bit_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ }, //total 72
+ .cfg_ddr_training_delay_ps[1].soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40
+ }, //total 44
+ .cfg_ddr_training_delay_ps[1].dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps[1].reserve_training_parameter = { 0 },
+},
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_DDR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .low_console_baud = CONFIG_LOW_CONSOLE_BAUD,
+};
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ {0, 0, 0xffffffff, 0, 0, 0},
+};
+
+/* gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+
+ /* config vddee and vcck pwm - pwm_h and pwm_j*/
+ {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ /* set pwm h and pwm j clock rate to 24M, enable them */
+ {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 24), 0xffffffff, 0, 0, 0},
+ {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 24) , 0xffffffff, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3 */
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0},
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0},
+};
+
+#define DEV_FIP_SIZE 0x300000
+#define DDR_FIP_SIZE 0x40000
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common = {
+ .version = 0x01,
+ .device_fip_container_size = DEV_FIP_SIZE,
+ .device_fip_container_copies = 4,
+ .ddr_fip_container_size = DDR_FIP_SIZE,
+ },
+ .nand = {
+ .version = 0x01,
+ .bbt_pages = 0x1,
+ .bbt_start_block = 20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (1 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 64,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/s4_skt/fw_arb.cfg b/board/amlogic/s4_skt/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/s4_skt/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/s4_skt/s4_skt.c b/board/amlogic/s4_skt/s4_skt.c
new file mode 100644
index 0000000..89cc56d
--- /dev/null
+++ b/board/amlogic/s4_skt/s4_skt.c
@@ -0,0 +1,385 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#include <amlogic/aml_mtd.h>
+
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
+#endif
+#ifdef CONFIG_AML_CVBS
+#include <amlogic/media/vout/aml_cvbs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+#if 0 //bypass below operations for pxp
+ aml_set_bootsequence(0);
+ #if 0
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ active_clk();
+ #endif
+#endif
+ run_command("gpio set GPIOH_7", 0);
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ #if 0
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+ run_command("run bcb_cmd", 0);
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ #endif
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ cvbs_init();
+#endif
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ (((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) - CONFIG_SYS_MEM_TOP_HIDE);
+#else
+ return ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf1000000UL,
+ .phys = 0xf1000000UL,
+ .size = 0x0f000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ /* update mmu table from bl2 ddr auto detect size */
+#ifdef CONFIG_UPDATE_MMU_TABLE
+ unsigned long nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4);
+ bd_mem_map[0].size = nddrSize;
+#endif
+
+ //printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+const char * const _env_args_reserve_[] =
+{
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/s4_t211/Kconfig b/board/amlogic/s4_t211/Kconfig
new file mode 100644
index 0000000..5d85d2a
--- /dev/null
+++ b/board/amlogic/s4_t211/Kconfig
@@ -0,0 +1,38 @@
+if TARGET_S4_T211
+
+config SYS_SOC
+ default "s4"
+
+config SYS_BOARD
+ default "s4_t211"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "s4_t211"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default y
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+
+config DEBUG_BOARD_VARIANT_PROD
+ bool "debug BOARD_VARIANT_PROD"
+ default n
+ help
+ Make get_board_vairant() always return BOARD_VARIANT_PROD for
+ debugging
+
+endif
diff --git a/board/amlogic/s4_t211/Makefile b/board/amlogic/s4_t211/Makefile
new file mode 100644
index 0000000..fb3c9ba
--- /dev/null
+++ b/board/amlogic/s4_t211/Makefile
@@ -0,0 +1,11 @@
+SOURCE_LOGO_FILE := res/images/logo.bmp.gz
+TARGET_LOGO_FILE_C := $(src)/res_images_logo_bmp_gz.c
+$(TARGET_LOGO_FILE_C): $(srctree)/$(src)/$(SOURCE_LOGO_FILE)
+ cd $(srctree)/$(src); xxd -i $(SOURCE_LOGO_FILE) > $(abspath $@)
+
+obj-y += $(BOARD).o
+obj-y += $(basename $(notdir $(TARGET_LOGO_FILE_C))).o
+
+# b/206911824: vendor public key
+obj-$(CONFIG_CMD_BOOTCTOL_AVB) += avb_kpub_vendor.o
+
diff --git a/board/amlogic/s4_t211/aml-key/bl2aesiv b/board/amlogic/s4_t211/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_t211/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/s4_t211/aml-key/bl2aeskey b/board/amlogic/s4_t211/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_t211/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/s4_t211/aml-key/bl3xaesiv b/board/amlogic/s4_t211/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_t211/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/s4_t211/aml-key/bl3xaeskey b/board/amlogic/s4_t211/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_t211/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/s4_t211/aml-key/kernelaesiv b/board/amlogic/s4_t211/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/s4_t211/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/s4_t211/aml-key/kernelaeskey b/board/amlogic/s4_t211/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/s4_t211/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/s4_t211/aml-user-key.sig b/board/amlogic/s4_t211/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/s4_t211/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/s4_t211/avb_kpub_vendor.c b/board/amlogic/s4_t211/avb_kpub_vendor.c
new file mode 100644
index 0000000..e09246b
--- /dev/null
+++ b/board/amlogic/s4_t211/avb_kpub_vendor.c
@@ -0,0 +1,212 @@
+#include <stdint.h>
+#include <stddef.h>
+
+// TODO(b/206911824): check the release key used in production
+
+#define AVB2_USE_PROD_KEY
+const uint8_t avb2_kpub_vendor_prod[] = {
+ 0x00, 0x00, 0x10, 0x00, 0xc2, 0x89, 0xc2, 0x17, 0x8b, 0x91, 0x56, 0x31,
+ 0x76, 0x55, 0xf8, 0x0f, 0x27, 0x12, 0xfc, 0x76, 0xfe, 0x23, 0xde, 0x9a,
+ 0xe0, 0x8f, 0xf5, 0xf0, 0xfd, 0xa9, 0x28, 0x9a, 0x76, 0x6c, 0x77, 0xb9,
+ 0x0c, 0xc5, 0xee, 0xba, 0x47, 0xd8, 0x5b, 0x07, 0xf0, 0x40, 0x30, 0xfc,
+ 0x05, 0x75, 0x3c, 0x37, 0x89, 0xe0, 0x6c, 0x22, 0x23, 0xe1, 0x68, 0x9d,
+ 0x25, 0x4c, 0xe5, 0x34, 0x17, 0x77, 0xb7, 0xa4, 0xa2, 0xf6, 0x23, 0xa9,
+ 0xda, 0x9d, 0x96, 0x55, 0xea, 0xe4, 0x16, 0xe8, 0x0d, 0xce, 0x0b, 0x97,
+ 0x01, 0xbd, 0x8a, 0x69, 0xff, 0xe9, 0x5c, 0x31, 0x33, 0x6a, 0x36, 0x16,
+ 0x61, 0x62, 0x82, 0x87, 0x98, 0x0b, 0x76, 0x8d, 0x5b, 0x13, 0xd7, 0xa1,
+ 0x0e, 0xcf, 0x05, 0xaa, 0x75, 0xa1, 0xda, 0xf4, 0xff, 0x1a, 0x7a, 0xa4,
+ 0x16, 0x7c, 0x24, 0xdc, 0xf2, 0x5b, 0x5c, 0x1f, 0xa6, 0x37, 0x93, 0x47,
+ 0x11, 0x04, 0x5f, 0xf8, 0xf2, 0xa3, 0x36, 0xcc, 0x26, 0xbe, 0xbd, 0xa8,
+ 0xe2, 0x4c, 0x29, 0x5f, 0x67, 0x47, 0x13, 0x9a, 0x18, 0x12, 0xa1, 0xe8,
+ 0xfc, 0x93, 0x85, 0x3d, 0x74, 0xf0, 0x48, 0x6f, 0x1e, 0xaf, 0x90, 0x31,
+ 0x9a, 0x3e, 0xb0, 0x7a, 0x50, 0x29, 0x9b, 0x41, 0xf9, 0x13, 0x83, 0x1a,
+ 0xf5, 0xf3, 0x97, 0x11, 0xf8, 0xbd, 0x19, 0x6a, 0x03, 0x1b, 0x22, 0x01,
+ 0xd7, 0x9d, 0xec, 0xe2, 0xca, 0xcc, 0x52, 0xdb, 0x3b, 0x99, 0x19, 0x19,
+ 0x6d, 0x2c, 0x75, 0xb0, 0xcd, 0xa1, 0x17, 0xbd, 0xa4, 0x61, 0xa0, 0x4a,
+ 0xaa, 0x06, 0xb1, 0xfc, 0x63, 0xd1, 0xd7, 0xd4, 0xc1, 0xac, 0x39, 0x76,
+ 0x58, 0x20, 0x83, 0xb8, 0x81, 0x7a, 0xe9, 0x75, 0x14, 0x8a, 0x4f, 0x39,
+ 0x69, 0x93, 0x6a, 0xe5, 0xa4, 0x11, 0x6e, 0x5d, 0x70, 0x80, 0xd6, 0xfc,
+ 0x64, 0xf0, 0x8d, 0xbb, 0x35, 0xaa, 0x9d, 0x42, 0xcf, 0xb5, 0x13, 0x64,
+ 0x7d, 0x0c, 0x14, 0x81, 0xa1, 0xdd, 0x68, 0x06, 0x3c, 0x10, 0xf4, 0xbf,
+ 0x57, 0xb3, 0x4e, 0xfd, 0x0f, 0xed, 0x8b, 0x3f, 0xc0, 0x05, 0xff, 0xa1,
+ 0x39, 0x48, 0x0d, 0x0e, 0x7f, 0xde, 0x14, 0xb7, 0x3c, 0xea, 0x9e, 0xfc,
+ 0x48, 0xcc, 0x80, 0x43, 0x3e, 0x44, 0xed, 0xd3, 0x42, 0x00, 0x2a, 0x8d,
+ 0xfe, 0x76, 0x65, 0xdc, 0x96, 0x17, 0xd7, 0x5e, 0xdc, 0x41, 0xe6, 0x72,
+ 0x85, 0x3d, 0x2b, 0xc7, 0xcc, 0xda, 0x12, 0xce, 0xa3, 0xf6, 0x1c, 0x16,
+ 0x12, 0x9c, 0xae, 0x76, 0xce, 0xf2, 0x9f, 0x5f, 0xff, 0xea, 0x43, 0xfe,
+ 0x11, 0x32, 0x1d, 0x63, 0x29, 0x96, 0xc2, 0x93, 0xc6, 0x71, 0x0a, 0xb2,
+ 0x3d, 0x0a, 0xbb, 0x6e, 0x9e, 0xa6, 0x7e, 0x7b, 0xe9, 0x01, 0xf3, 0xfd,
+ 0x86, 0xc9, 0x7e, 0x04, 0x49, 0xb7, 0x10, 0x2c, 0x9a, 0x6c, 0xed, 0x19,
+ 0x88, 0x4c, 0x78, 0x91, 0x48, 0x43, 0xe4, 0x1f, 0x55, 0x5e, 0xbf, 0xd6,
+ 0xc3, 0x19, 0x1b, 0xba, 0x00, 0x20, 0x0b, 0x8a, 0x98, 0x4b, 0x36, 0x65,
+ 0x0d, 0x7b, 0xff, 0x96, 0x60, 0xd8, 0xcf, 0x9c, 0x41, 0x89, 0x6d, 0x24,
+ 0x41, 0x5e, 0x70, 0x18, 0x6c, 0x14, 0x14, 0x93, 0x0b, 0x27, 0x32, 0x03,
+ 0xd1, 0xf1, 0xde, 0x2d, 0xc9, 0x70, 0xea, 0x9a, 0xef, 0x76, 0x09, 0xc7,
+ 0x5e, 0x00, 0xf1, 0x9e, 0xc0, 0x9c, 0x37, 0xc9, 0x58, 0xa3, 0x80, 0x7f,
+ 0xe5, 0x97, 0x32, 0xd8, 0xe9, 0x3b, 0xe9, 0x3b, 0xf3, 0x68, 0x4f, 0x56,
+ 0x70, 0x53, 0x93, 0x0b, 0x02, 0x00, 0x7d, 0x43, 0xe3, 0x7f, 0xee, 0x3b,
+ 0x8e, 0x07, 0xf1, 0x36, 0x3a, 0x83, 0xba, 0x9d, 0x6c, 0x81, 0xf0, 0x75,
+ 0x39, 0xd3, 0x23, 0x71, 0x84, 0x4d, 0x7d, 0x70, 0x01, 0xbd, 0xa5, 0x86,
+ 0x4a, 0x0f, 0xfa, 0x36, 0x08, 0xaa, 0xf2, 0x26, 0x97, 0x0a, 0x58, 0x8a,
+ 0x36, 0xf2, 0x6a, 0x59, 0x4b, 0x39, 0x3b, 0x5c, 0x09, 0xa7, 0x7d, 0x0d,
+ 0x90, 0x33, 0x18, 0xf2, 0x4c, 0x0e, 0xcb, 0xf2, 0x44, 0xc1, 0xab, 0xb7,
+ 0xcd, 0x0f, 0x02, 0x65, 0xc9, 0x3e, 0x23, 0xed, 0x2b, 0x3e, 0x60, 0x8b,
+ 0xee, 0xd5, 0xe4, 0x89, 0x97, 0x51, 0x5f, 0x5c, 0xda, 0x6b, 0x0c, 0x2a,
+ 0x1e, 0x14, 0x99, 0xa5, 0x4c, 0x1f, 0xe1, 0x6c, 0xa2, 0xfc, 0x41, 0x04,
+ 0x34, 0x33, 0xc3, 0x38, 0x47, 0x58, 0x27, 0xa9, 0xb5, 0x60, 0x50, 0x41,
+ 0xc7, 0x64, 0xd6, 0x5f, 0xda, 0x0c, 0xa1, 0xf2, 0x29, 0x16, 0x4e, 0xc6,
+ 0x09, 0x3d, 0x96, 0x95, 0xf6, 0x43, 0x85, 0x07, 0xd5, 0xd5, 0xd7, 0x4c,
+ 0x01, 0xb9, 0xd3, 0x23, 0x83, 0x00, 0xed, 0xb3, 0x94, 0xe5, 0x44, 0x2c,
+ 0x2f, 0x20, 0x01, 0xc9, 0xbf, 0x41, 0x70, 0x71, 0xcb, 0x94, 0x4f, 0x8c,
+ 0xfb, 0x44, 0xd8, 0x7d, 0x96, 0x61, 0x73, 0xc0, 0x09, 0x9c, 0x93, 0xb9,
+ 0xc4, 0xbb, 0x9f, 0x32, 0xf0, 0x37, 0xf4, 0x88, 0xa9, 0x8b, 0x58, 0xe1,
+ 0xe1, 0x53, 0x6a, 0x43, 0xd1, 0x78, 0xa2, 0x31, 0x46, 0x64, 0x2e, 0x5d,
+ 0xc0, 0x6e, 0xe5, 0x7f, 0xbf, 0x93, 0x05, 0x62, 0x0f, 0x80, 0x61, 0xec,
+ 0xee, 0xa4, 0x55, 0xc5, 0x81, 0x38, 0xba, 0x46, 0xaa, 0xf5, 0x58, 0x84,
+ 0x38, 0x46, 0xb1, 0x9b, 0xd8, 0x8d, 0x29, 0x79, 0x06, 0x96, 0xe7, 0x83,
+ 0x8a, 0x78, 0x8f, 0x7c, 0xad, 0x69, 0xe9, 0xfe, 0x89, 0x70, 0x23, 0x42,
+ 0xa0, 0xc3, 0x81, 0x35, 0x0a, 0x6a, 0x68, 0xaa, 0x6c, 0x00, 0x04, 0x2a,
+ 0x4a, 0x36, 0xc9, 0x36, 0x92, 0xa2, 0x86, 0x0b, 0x8b, 0xea, 0x90, 0x76,
+ 0xae, 0x49, 0xc8, 0x39, 0xa6, 0xf8, 0xdd, 0xde, 0x09, 0x48, 0xfe, 0x19,
+ 0xaf, 0x31, 0x58, 0xdb, 0x95, 0xab, 0xcd, 0x8b, 0xa6, 0x21, 0x3c, 0x43,
+ 0x2c, 0x4f, 0x91, 0xa5, 0xae, 0xb5, 0xad, 0xa2, 0x1c, 0x22, 0x8d, 0x81,
+ 0xd1, 0xd7, 0xd3, 0xc1, 0xae, 0x5b, 0xae, 0xdb, 0xa7, 0x4b, 0xe0, 0x16,
+ 0x18, 0xe7, 0x66, 0x36, 0x32, 0x15, 0x0b, 0x85, 0x59, 0x55, 0x61, 0x76,
+ 0x69, 0xe9, 0x0a, 0x79, 0x92, 0x8c, 0x6e, 0x8d, 0xc7, 0x90, 0xb9, 0xcc,
+ 0x47, 0xda, 0xc9, 0x69, 0x18, 0x97, 0xb4, 0x81, 0x12, 0xdb, 0x62, 0x0f,
+ 0x27, 0xe0, 0x0d, 0x7e, 0xdf, 0x72, 0x44, 0x02, 0x5e, 0x7d, 0x49, 0x7b,
+ 0x33, 0x1a, 0x3f, 0x7e, 0x03, 0x83, 0x2e, 0x9e, 0x92, 0xe2, 0xf4, 0x98,
+ 0xbb, 0xd4, 0x03, 0x11, 0x40, 0x12, 0x71, 0x84, 0x97, 0xf0, 0xb7, 0x0c,
+ 0x52, 0x4b, 0x83, 0x31, 0xd5, 0x7f, 0xe9, 0x3f, 0xb5, 0xd9, 0xa3, 0xdc,
+ 0x5a, 0xeb, 0xdd, 0x01, 0x08, 0x42, 0x58, 0x36, 0xfc, 0xc9, 0x1c, 0x9c,
+ 0x98, 0xd4, 0x63, 0xc8, 0x8a, 0x30, 0x7a, 0xf9, 0xb6, 0xb3, 0xb8, 0xed,
+ 0xee, 0xef, 0x87, 0xd6, 0xc8, 0x5e, 0x7f, 0x7e, 0x83, 0x28, 0xce, 0x3b,
+ 0x55, 0x3b, 0x70, 0xa3, 0xc1, 0xaf, 0x83, 0x00, 0x5e, 0x46, 0x24, 0xf1,
+ 0x20, 0x99, 0x33, 0xd2, 0x5b, 0x1d, 0x98, 0xf6, 0xbb, 0xa2, 0x61, 0xff,
+ 0x59, 0x2e, 0x8e, 0x00, 0xf5, 0xf0, 0x11, 0x85, 0x0b, 0xa1, 0xe6, 0x73,
+ 0x73, 0x36, 0x36, 0x35, 0xc5, 0x54, 0xeb, 0xdd, 0x0f, 0xf1, 0x09, 0x0f,
+ 0x0a, 0xa4, 0xdc, 0x94, 0xf1, 0x82, 0x7a, 0xe8, 0x69, 0xd2, 0xc1, 0xc3,
+ 0xd4, 0x9a, 0xa8, 0x62, 0x5c, 0x33, 0xc9, 0xea, 0x8b, 0xe2, 0xc8, 0x29,
+ 0x84, 0xd4, 0xdb, 0xe5, 0x36, 0xfe, 0x67, 0xae, 0xb0, 0xc6, 0x7a, 0xed,
+ 0xb6, 0xe5, 0xcb, 0x1b, 0xab, 0x7b, 0x29, 0x2a, 0xa2, 0x2a, 0x96, 0xc5,
+ 0x4f, 0xf0, 0xe5, 0x12, 0xd0, 0xd4, 0x03, 0xce, 0xd7, 0x5e, 0x11, 0x8d,
+ 0x2f, 0xc5, 0x99, 0x1d, 0xc0, 0x1d, 0x7b, 0x60, 0x97, 0x81, 0x29, 0x9d
+};
+
+const uint8_t * const avb2_kpub_vendor[] = {
+#ifdef AVB2_USE_PROD_KEY
+ avb2_kpub_vendor_prod,
+#endif
+};
+
+const size_t avb2_kpub_vendor_len[] = {
+#ifdef AVB2_USE_PROD_KEY
+ sizeof(avb2_kpub_vendor_prod) / sizeof(uint8_t),
+#endif
+};
+
+const size_t avb2_kpub_vendor_num = sizeof(avb2_kpub_vendor) / sizeof(uint8_t*);
+
+
+const uint8_t avb2_kpub_vendor_external_prod[] = {
+ 0x00, 0x00, 0x10, 0x00, 0xb6, 0x49, 0xec, 0xad, 0xba, 0xaf, 0x44, 0x6f,
+ 0xbd, 0x0e, 0x7f, 0x15, 0x93, 0x39, 0xb6, 0x29, 0x72, 0x71, 0x1d, 0x3d,
+ 0xd7, 0x7b, 0xac, 0x5d, 0x98, 0xac, 0x17, 0x3f, 0xbf, 0x3d, 0x70, 0x7c,
+ 0x10, 0xd2, 0xa8, 0x6e, 0x10, 0xd6, 0x0f, 0xe1, 0x71, 0x5e, 0x0b, 0x1f,
+ 0x97, 0x91, 0x98, 0x4b, 0x90, 0x28, 0x15, 0x32, 0x07, 0xd3, 0x70, 0x8d,
+ 0x85, 0xa4, 0xa0, 0x0f, 0x18, 0x7b, 0x22, 0xd5, 0x10, 0xe4, 0xac, 0x9a,
+ 0x03, 0x8a, 0xd6, 0x99, 0x14, 0x42, 0x21, 0x3e, 0x60, 0xca, 0xaf, 0x20,
+ 0xed, 0x26, 0x7f, 0x95, 0xda, 0xf4, 0xe8, 0x97, 0x91, 0xa8, 0xb8, 0x43,
+ 0xf1, 0xe4, 0x6b, 0x70, 0x82, 0x8a, 0x8c, 0xd7, 0xc8, 0x3e, 0xe0, 0x6d,
+ 0x52, 0x57, 0xc9, 0xa0, 0x45, 0x0f, 0x0c, 0x43, 0x22, 0x77, 0x06, 0x21,
+ 0x31, 0xfc, 0x99, 0x6b, 0xb6, 0xc9, 0x2c, 0x0b, 0xdf, 0xb7, 0xab, 0xb3,
+ 0xb0, 0xe1, 0x73, 0xa0, 0x32, 0x89, 0xf5, 0xac, 0x27, 0x39, 0x95, 0x91,
+ 0x62, 0x09, 0x4d, 0x6d, 0x24, 0x7f, 0x4a, 0x88, 0x4f, 0xe8, 0x3b, 0xf5,
+ 0xed, 0xef, 0x4f, 0x56, 0xb3, 0xbd, 0xeb, 0xd4, 0xcf, 0x0e, 0x4a, 0xca,
+ 0xe5, 0x30, 0x27, 0xd2, 0xec, 0x5f, 0xf4, 0x66, 0x1c, 0x1c, 0x2c, 0xeb,
+ 0x2c, 0xd2, 0xa8, 0x4f, 0x86, 0x7f, 0x8b, 0x62, 0x57, 0x1c, 0xe3, 0xf3,
+ 0x95, 0x47, 0x5b, 0x55, 0xd9, 0x56, 0xdc, 0xb4, 0x78, 0xaa, 0x3c, 0x4c,
+ 0x5d, 0x2b, 0xc6, 0x68, 0xd4, 0xeb, 0x6f, 0x64, 0xd8, 0x3e, 0xd1, 0xcb,
+ 0x03, 0x3e, 0x59, 0xf4, 0x3c, 0xa2, 0xd2, 0x03, 0x15, 0x4e, 0x25, 0x68,
+ 0x9f, 0x3e, 0xcb, 0x8e, 0x68, 0x25, 0x34, 0xd3, 0x5d, 0x45, 0x01, 0xd7,
+ 0xcf, 0x24, 0xe3, 0xd6, 0x51, 0xa9, 0xf4, 0x9e, 0x30, 0x9e, 0xc8, 0x6c,
+ 0xcc, 0xb4, 0x27, 0x34, 0x50, 0x8c, 0x49, 0x85, 0x6e, 0xd7, 0x7f, 0xa2,
+ 0xfd, 0x52, 0xca, 0x64, 0xf0, 0x94, 0xe3, 0xae, 0x01, 0xa0, 0xb5, 0xdb,
+ 0x49, 0x23, 0xf1, 0xa6, 0x6e, 0xc8, 0xb2, 0x40, 0x7c, 0x06, 0xa5, 0xd1,
+ 0xf5, 0xd2, 0x3a, 0xbd, 0x71, 0x3a, 0x3e, 0x60, 0x09, 0xb9, 0xf2, 0x2b,
+ 0xf6, 0x3b, 0x75, 0x59, 0x85, 0x8d, 0xb7, 0xb9, 0x77, 0x4a, 0x52, 0x27,
+ 0xff, 0x9c, 0xad, 0xfe, 0xf5, 0xf3, 0x58, 0xeb, 0xd0, 0x86, 0x13, 0xa4,
+ 0x0d, 0xc5, 0x2e, 0xb8, 0x57, 0x6a, 0x3a, 0xc4, 0xec, 0x1c, 0x19, 0xbc,
+ 0x07, 0x1e, 0xaf, 0xa0, 0x00, 0x3a, 0xe1, 0x72, 0x09, 0xd4, 0xec, 0x1d,
+ 0x88, 0x65, 0x90, 0x1c, 0x2f, 0xec, 0x24, 0x6d, 0xac, 0x0b, 0x2f, 0x7c,
+ 0xc4, 0xb0, 0xa8, 0x62, 0xc7, 0x27, 0x12, 0x13, 0x1f, 0x6e, 0x88, 0x45,
+ 0xb5, 0xa3, 0x2d, 0x9c, 0x55, 0xb1, 0xa8, 0x28, 0x48, 0xd2, 0xe5, 0x15,
+ 0xd6, 0x49, 0x2a, 0x8d, 0x60, 0x0b, 0xc8, 0xf0, 0x53, 0xb0, 0x17, 0xfa,
+ 0x30, 0x48, 0x23, 0x7a, 0x4c, 0xce, 0x81, 0x40, 0x40, 0x92, 0x2a, 0x95,
+ 0xd2, 0xc9, 0xa8, 0xbc, 0x36, 0x71, 0xe4, 0x93, 0x23, 0xe4, 0x37, 0xcd,
+ 0xe1, 0xe8, 0x0b, 0x8b, 0x9d, 0x56, 0xf3, 0x1c, 0xfe, 0x2a, 0xe6, 0x2c,
+ 0x4e, 0xfc, 0x8a, 0x1e, 0xa3, 0xe5, 0xd3, 0x95, 0x22, 0x99, 0x79, 0xbe,
+ 0x30, 0xe9, 0x34, 0x02, 0xfc, 0x77, 0x15, 0x71, 0xf3, 0xf4, 0x36, 0x05,
+ 0x11, 0x26, 0xa3, 0xcb, 0x25, 0x01, 0xd8, 0xde, 0xbe, 0x64, 0xb6, 0x67,
+ 0xdc, 0x10, 0xbf, 0xad, 0xe4, 0xd3, 0x97, 0xa2, 0x1f, 0x72, 0xe1, 0x7d,
+ 0x59, 0x9f, 0x23, 0xfb, 0x60, 0x6b, 0x07, 0x6a, 0xb8, 0x8a, 0x86, 0xf1,
+ 0x68, 0xc4, 0xe3, 0xe3, 0x1b, 0xa3, 0xb2, 0x0f, 0x80, 0x38, 0x38, 0xbd,
+ 0x3c, 0x5c, 0x67, 0x66, 0xc5, 0x0d, 0xac, 0x92, 0xbf, 0xb2, 0x00, 0xd9,
+ 0x8e, 0x55, 0xa8, 0xdb, 0x0b, 0xa3, 0xe8, 0x75, 0xfb, 0x1e, 0x66, 0x7d,
+ 0x3e, 0xf9, 0x61, 0x10, 0x6b, 0xb4, 0x90, 0x95, 0x97, 0xc4, 0xac, 0x72,
+ 0x39, 0x44, 0x8d, 0x46, 0x08, 0x75, 0x8c, 0xa8, 0x61, 0xd5, 0x26, 0x22,
+ 0x21, 0xe7, 0x86, 0xba, 0x97, 0xb9, 0x72, 0x5b, 0xe8, 0x4c, 0x1c, 0x6e,
+ 0xdb, 0xf6, 0x80, 0xcc, 0x59, 0x29, 0xe1, 0xd2, 0x96, 0xcd, 0x12, 0xbf,
+ 0x0c, 0x13, 0xf6, 0x5a, 0x03, 0x59, 0xfe, 0x61, 0x6f, 0xa9, 0xb8, 0xc5,
+ 0xb8, 0xf1, 0x78, 0xc2, 0x69, 0xbf, 0xe1, 0xdc, 0xcb, 0xde, 0x93, 0xa9,
+ 0x83, 0x5b, 0xc5, 0x49, 0xf8, 0x50, 0xb1, 0x01, 0x0d, 0xba, 0x33, 0xd8,
+ 0x0b, 0xc3, 0x76, 0x76, 0x7a, 0x7a, 0x76, 0x09, 0xe8, 0xe4, 0x81, 0xca,
+ 0x97, 0xfe, 0x18, 0xfa, 0x6c, 0x90, 0x29, 0xe4, 0xd0, 0x9b, 0x90, 0x70,
+ 0xac, 0xa5, 0xc5, 0x5c, 0x13, 0x7a, 0x97, 0x0e, 0x98, 0xb8, 0x35, 0x2c,
+ 0x11, 0xf8, 0xde, 0x50, 0x6c, 0xdd, 0x1b, 0xfd, 0xf4, 0x57, 0x66, 0x34,
+ 0x3b, 0x07, 0x61, 0x12, 0xdc, 0x90, 0x15, 0xfa, 0xa2, 0xfb, 0x56, 0x56,
+ 0x07, 0x13, 0xbd, 0x7b, 0xcb, 0x59, 0x66, 0x44, 0x6e, 0xc8, 0xbc, 0xdd,
+ 0x01, 0x3a, 0x5a, 0xb6, 0x9e, 0x65, 0xe0, 0x27, 0x62, 0x31, 0x27, 0x7d,
+ 0xf5, 0x1a, 0x33, 0x7d, 0x55, 0x70, 0x92, 0xcf, 0x18, 0xb3, 0x62, 0x8d,
+ 0xcb, 0x2a, 0x0f, 0xbe, 0xa4, 0xa9, 0xee, 0xf7, 0xe6, 0x23, 0xf3, 0x30,
+ 0x1b, 0xcd, 0x67, 0x8e, 0xf6, 0x21, 0xfd, 0x1e, 0x76, 0x39, 0xd6, 0xf5,
+ 0x48, 0xc7, 0x33, 0x5e, 0xc6, 0xd6, 0xad, 0x90, 0x7e, 0xbb, 0xbc, 0x2f,
+ 0x14, 0xe7, 0xf1, 0x8b, 0x73, 0xb1, 0xa2, 0xe3, 0xdf, 0x15, 0x98, 0x63,
+ 0xd6, 0xc2, 0x0b, 0xe3, 0x94, 0xab, 0x3b, 0x70, 0xbd, 0xb9, 0x48, 0xc6,
+ 0x0f, 0xa1, 0xbd, 0xa9, 0x06, 0x26, 0x80, 0x1d, 0x3e, 0x28, 0xa6, 0xcd,
+ 0xb2, 0x2d, 0x28, 0x1f, 0x70, 0xb1, 0x85, 0x86, 0x73, 0x7c, 0x86, 0x32,
+ 0x13, 0x41, 0xa6, 0xc7, 0xa0, 0xc1, 0xd6, 0x22, 0xd3, 0xff, 0x25, 0xb0,
+ 0x6d, 0x2a, 0xc7, 0x95, 0x4d, 0x30, 0x28, 0x7e, 0x02, 0x49, 0xa3, 0x2f,
+ 0x77, 0xe3, 0x6d, 0x8e, 0x16, 0x2e, 0x18, 0x85, 0x1c, 0xed, 0x41, 0x8f,
+ 0xef, 0xca, 0x24, 0x84, 0xa3, 0x50, 0x10, 0x30, 0x08, 0x88, 0x88, 0x32,
+ 0x06, 0xc7, 0xa6, 0x5a, 0x55, 0xa2, 0x18, 0x08, 0x4d, 0xdf, 0x88, 0xd1,
+ 0x64, 0xd0, 0x06, 0x92, 0x69, 0xa2, 0x21, 0x85, 0x64, 0x58, 0x36, 0xf2,
+ 0x24, 0x22, 0x16, 0xb7, 0xd8, 0xfa, 0x8a, 0x0b, 0x3c, 0x5c, 0xff, 0xa4,
+ 0xec, 0x79, 0xcd, 0xbe, 0xe3, 0x04, 0x96, 0x3c, 0xce, 0x24, 0x27, 0x14,
+ 0x88, 0x82, 0x8b, 0xf9, 0x6c, 0x7a, 0x3f, 0x60, 0x25, 0xbd, 0x78, 0x6c,
+ 0x28, 0x8b, 0x84, 0xcc, 0x12, 0xda, 0xec, 0xea, 0x5f, 0xa7, 0x57, 0x60,
+ 0x59, 0x90, 0x70, 0xb1, 0x48, 0x25, 0xd6, 0xa2, 0x68, 0x82, 0xde, 0xdb,
+ 0x05, 0x9d, 0xc8, 0x0f, 0x7b, 0x86, 0x32, 0xb7, 0x67, 0xbb, 0x6c, 0x48,
+ 0x13, 0xc9, 0x4e, 0x55, 0x0b, 0xaa, 0x82, 0xbd, 0x04, 0x66, 0x05, 0x8e,
+ 0x78, 0xb6, 0x18, 0x9b, 0xbd, 0x84, 0xf2, 0x98, 0x8e, 0x75, 0xa5, 0x6c,
+ 0xc7, 0xb4, 0x5b, 0xb7, 0xdd, 0xd9, 0x58, 0x03, 0x52, 0x62, 0x08, 0x57,
+ 0x72, 0x98, 0xd9, 0xa6, 0x86, 0x92, 0x87, 0x7f, 0x16, 0x02, 0x9c, 0x00,
+ 0x5c, 0x9e, 0x2a, 0xc0, 0xe5, 0xdd, 0x40, 0x8a, 0xfa, 0x5a, 0xe0, 0x51,
+ 0x17, 0x45, 0xe9, 0x87, 0x27, 0x44, 0xed, 0x67, 0x21, 0xd0, 0xd1, 0xf7,
+ 0xf8, 0xf5, 0xb6, 0x8a, 0x93, 0xe1, 0xeb, 0xcf, 0x52, 0xd0, 0xe9, 0x10,
+ 0x7d, 0x99, 0x1d, 0x4b, 0x7c, 0xb3, 0xd2, 0x78, 0x3e, 0x89, 0x5c, 0x64
+};
+
+const uint8_t * const avb2_kpub_vendor_external[] = {
+#ifdef AVB2_USE_PROD_KEY
+ avb2_kpub_vendor_external_prod,
+#endif
+};
+
+const size_t avb2_kpub_vendor_external_len[] = {
+#ifdef AVB2_USE_PROD_KEY
+ sizeof(avb2_kpub_vendor_external_prod) / sizeof(uint8_t),
+#endif
+};
+
+const size_t avb2_kpub_vendor_external_num = sizeof(avb2_kpub_vendor_external) / sizeof(uint8_t*);
diff --git a/board/amlogic/s4_t211/device-keys_emmc/boot-blobs/template/s805x2g/rootrsa-0/bb1st.bin b/board/amlogic/s4_t211/device-keys_emmc/boot-blobs/template/s805x2g/rootrsa-0/bb1st.bin
new file mode 100755
index 0000000..a9a344b
--- /dev/null
+++ b/board/amlogic/s4_t211/device-keys_emmc/boot-blobs/template/s805x2g/rootrsa-0/bb1st.bin
Binary files differ
diff --git a/board/amlogic/s4_t211/device-keys_emmc/fip/aes/s805x2g/protkey/genkey-prot-bl30.bin b/board/amlogic/s4_t211/device-keys_emmc/fip/aes/s805x2g/protkey/genkey-prot-bl30.bin
new file mode 100755
index 0000000..f09875a
--- /dev/null
+++ b/board/amlogic/s4_t211/device-keys_emmc/fip/aes/s805x2g/protkey/genkey-prot-bl30.bin
@@ -0,0 +1 @@
+?ö|ïG
¨u%1!f¶Wü$.ý28Õéá¥\Z÷¶
\ No newline at end of file
diff --git a/board/amlogic/s4_t211/device-keys_emmc/fip/aes/s805x2g/protkey/genkey-prot-bl33.bin b/board/amlogic/s4_t211/device-keys_emmc/fip/aes/s805x2g/protkey/genkey-prot-bl33.bin
new file mode 100755
index 0000000..465b349
--- /dev/null
+++ b/board/amlogic/s4_t211/device-keys_emmc/fip/aes/s805x2g/protkey/genkey-prot-bl33.bin
@@ -0,0 +1,2 @@
+?T
+AÆéåòËªÌ ÝÑ,åEáÓVâ _µ¸ÝÉ
\ No newline at end of file
diff --git a/board/amlogic/s4_t211/device-keys_emmc/fip/aes/s805x2g/protkey/genkey-prot-krnl.bin b/board/amlogic/s4_t211/device-keys_emmc/fip/aes/s805x2g/protkey/genkey-prot-krnl.bin
new file mode 100755
index 0000000..7caef3d
--- /dev/null
+++ b/board/amlogic/s4_t211/device-keys_emmc/fip/aes/s805x2g/protkey/genkey-prot-krnl.bin
Binary files differ
diff --git a/board/amlogic/s4_t211/device-keys_emmc/fip/template/s805x2g/rootrsa-0/device-fip-header.bin b/board/amlogic/s4_t211/device-keys_emmc/fip/template/s805x2g/rootrsa-0/device-fip-header.bin
new file mode 100755
index 0000000..0435ce4
--- /dev/null
+++ b/board/amlogic/s4_t211/device-keys_emmc/fip/template/s805x2g/rootrsa-0/device-fip-header.bin
Binary files differ
diff --git a/board/amlogic/s4_t211/device-keys_usb/boot-blobs/template/s805x2g/rootrsa-0/bb1st.bin b/board/amlogic/s4_t211/device-keys_usb/boot-blobs/template/s805x2g/rootrsa-0/bb1st.bin
new file mode 100755
index 0000000..3099919
--- /dev/null
+++ b/board/amlogic/s4_t211/device-keys_usb/boot-blobs/template/s805x2g/rootrsa-0/bb1st.bin
Binary files differ
diff --git a/board/amlogic/s4_t211/device-keys_usb/fip/aes/s805x2g/protkey/genkey-prot-bl30.bin b/board/amlogic/s4_t211/device-keys_usb/fip/aes/s805x2g/protkey/genkey-prot-bl30.bin
new file mode 100755
index 0000000..f09875a
--- /dev/null
+++ b/board/amlogic/s4_t211/device-keys_usb/fip/aes/s805x2g/protkey/genkey-prot-bl30.bin
@@ -0,0 +1 @@
+?ö|ïG
¨u%1!f¶Wü$.ý28Õéá¥\Z÷¶
\ No newline at end of file
diff --git a/board/amlogic/s4_t211/device-keys_usb/fip/aes/s805x2g/protkey/genkey-prot-bl33.bin b/board/amlogic/s4_t211/device-keys_usb/fip/aes/s805x2g/protkey/genkey-prot-bl33.bin
new file mode 100755
index 0000000..465b349
--- /dev/null
+++ b/board/amlogic/s4_t211/device-keys_usb/fip/aes/s805x2g/protkey/genkey-prot-bl33.bin
@@ -0,0 +1,2 @@
+?T
+AÆéåòËªÌ ÝÑ,åEáÓVâ _µ¸ÝÉ
\ No newline at end of file
diff --git a/board/amlogic/s4_t211/device-keys_usb/fip/aes/s805x2g/protkey/genkey-prot-krnl.bin b/board/amlogic/s4_t211/device-keys_usb/fip/aes/s805x2g/protkey/genkey-prot-krnl.bin
new file mode 100755
index 0000000..7caef3d
--- /dev/null
+++ b/board/amlogic/s4_t211/device-keys_usb/fip/aes/s805x2g/protkey/genkey-prot-krnl.bin
Binary files differ
diff --git a/board/amlogic/s4_t211/device-keys_usb/fip/template/s805x2g/rootrsa-0/device-fip-header.bin b/board/amlogic/s4_t211/device-keys_usb/fip/template/s805x2g/rootrsa-0/device-fip-header.bin
new file mode 100755
index 0000000..0435ce4
--- /dev/null
+++ b/board/amlogic/s4_t211/device-keys_usb/fip/template/s805x2g/rootrsa-0/device-fip-header.bin
Binary files differ
diff --git a/board/amlogic/s4_t211/firmware/timing.c b/board/amlogic/s4_t211/firmware/timing.c
new file mode 100644
index 0000000..89045ef
--- /dev/null
+++ b/board/amlogic/s4_t211/firmware/timing.c
@@ -0,0 +1,2775 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK CONFIG_CPU_CLK
+#define DDR_ID_ACS_ADC ((3 << 6) | (8)) //bit 6 adc_channel bit 0-5 adc value,chan 3 value 8 is layer 2
+
+//*/
+#define DDR_RESV_CHECK_ID_ENABLE 0Xfe
+#define SAR_ADC_DDR_ID_BASE 0
+#define SAR_ADC_DDR_ID_STEP 80
+#define CARMEL_BOARD_1G_1G_ADC_ID SAR_ADC_DDR_ID_BASE + SAR_ADC_DDR_ID_STEP //85 0-125 step 0
+#define CARMEL_BOARD_2G_1G_ADC_ID SAR_ADC_DDR_ID_BASE + SAR_ADC_DDR_ID_STEP + SAR_ADC_DDR_ID_STEP //167 126-200 step 1
+#define DDR_TIMMING_OFFSET(X) (unsigned int)(unsigned long)(&(((ddr_set_ps0_only_t *)(0))->X))
+#define DDR_TIMMING_OFFSET_SIZE(X) sizeof(((ddr_set_ps0_only_t *)(0))->X)
+#define DDR_TIMMING_TUNE_TIMMING0(DDR_ID, PARA, VALUE) { DDR_ID, DDR_TIMMING_OFFSET(PARA), VALUE, DDR_TIMMING_OFFSET_SIZE(PARA), 0, DDR_RESV_CHECK_ID_ENABLE }
+#define DDR_TIMMING_TUNE_TIMMING1(DDR_ID, PARA, VALUE) { DDR_ID, sizeof(((ddr_set_ps0_only_t) + DDR_TIMMING_OFFSET(PARA), VALUE, DDR_TIMMING_OFFSET_SIZE(PARA), 0, DDR_RESV_CHECK_ID_ENABLE }
+
+
+
+//bit24-31 define ID and size
+#define DDR_ID_FROM_EFUSE (0Xff<<24)
+#define DDR_ID_FROM_ADC (0Xfe<<24)
+#define DDR_ID_FROM_GPIO_CONFIG1 (0xfdu<<24)
+#define DDR_ID_START_MASK (0XFFDDCCBB)
+
+#define DDR_ADC_CH0 (0X0<<6)
+#define DDR_ADC_CH1 (0X1<<6)
+#define DDR_ADC_CH2 (0X2<<6)
+#define DDR_ADC_CH3 (0X3<<6)
+
+#define DDR_ADC_VALUE0 (0X0<<0)
+#define DDR_ADC_VALUE1 (0X1<<0)
+#define DDR_ADC_VALUE2 (0X2<<0)
+#define DDR_ADC_VALUE3 (0X3<<0)
+#define DDR_ADC_VALUE4 (0X4<<0)
+#define DDR_ADC_VALUE5 (0X5<<0)
+#define DDR_ADC_VALUE6 (0X6<<0)
+#define DDR_ADC_VALUE7 (0X7<<0)
+#define DDR_ADC_VALUE8 (0X8<<0)
+#define DDR_ADC_VALUE9 (0X9<<0)
+#define DDR_ADC_VALUE10 (0Xa<<0)
+#define DDR_ADC_VALUE11 (0Xb<<0)
+#define DDR_ADC_VALUE12 (0Xc<<0)
+#define DDR_ADC_VALUE13 (0Xd<<0)
+#define DDR_ADC_VALUE14 (0Xe<<0)
+#define DDR_ADC_VALUE15 (0Xf<<0)
+
+typedef struct ddr_para_data {
+ //start from DDR_ID_START_MASK,ddr_id;//bit0-23 ddr_id value,bit 24-31 ddr_id source ,0xfe source from adc ,0xfd source from gpio_default_config
+ //reg_offset //bit 0-15 parameter offset value,bit16-23 overrid size,bit24-31 mux ddr_id source
+ //unsigned int reg_offset;
+ //unsigned int value;
+ uint32_t value : 16; //bit0-15 only support data size =1byte or 2bytes,no support int value
+ uint32_t reg_offset : 12;//bit16-27
+ uint32_t data_size : 4;//bit28-31 if data size =15,then will mean DDR_ID start
+
+} ddr_para_data_t;
+
+typedef struct ddr_para_data_start {
+
+ uint32_t id_value : 24; //bit0-23 efuse id or ddr id
+ //uint32_t id_adc_ch : 2;//bit6-7
+ uint32_t id_src_from : 8;//bit24-31 ddr id from adc or gpio
+} ddr_para_data_start_t;
+//#define DDR_TIMMING_OFFSET(X) (unsigned int)(unsigned long)(&(((ddr_set_ps0_only_t *)(0))->X))
+//#define DDR_TIMMING_OFFSET_SIZE(X) sizeof(((ddr_set_ps0_only_t *)(0))->X)
+//#define DDR_TIMMING_TUNE_TIMMING0(DDR_ID, PARA, VALUE) { DDR_ID, DDR_TIMMING_OFFSET(PARA), VALUE, DDR_TIMMING_OFFSET_SIZE(PARA), 0, DDR_RESV_CHECK_ID_ENABLE }
+//#define DDR_TIMMING_TUNE_TIMMING1(DDR_ID, PARA, VALUE) { DDR_ID, sizeof(((ddr_set_ps0_only_t) + DDR_TIMMING_OFFSET(PARA), VALUE, DDR_TIMMING_OFFSET_SIZE(PARA), 0, DDR_RESV_CHECK_ID_ENABLE }
+#define DDR_TIMMING_TUNE_TIMMING0_F(PARA, VALUE) (((DDR_TIMMING_OFFSET(PARA))<<16)|((DDR_TIMMING_OFFSET_SIZE(PARA))<<28)|VALUE)
+#define DDR_TIMMING_TUNE_TIMMING1_F(PARA, VALUE) (((sizeof(ddr_set_ps0_only_t) +DDR_TIMMING_OFFSET(PARA))<<16)|((DDR_TIMMING_OFFSET_SIZE(PARA))<<28)|VALUE)
+
+#define DDR_TIMMING_TUNE_START(id_src_from, id_adc_ch, id_value) (id_src_from|id_adc_ch|id_value)
+#define DDR_TIMMING_TUNE_STRUCT_SIZE(a) sizeof(a)
+
+#if 1
+uint32_t __bl2_ddr_reg_data[] __attribute__ ((section(".ddr_2acs_data"))) = {
+ DDR_TIMMING_TUNE_START(DDR_ID_FROM_GPIO_CONFIG1, 0, 0),
+ //data start
+ DDR_TIMMING_TUNE_TIMMING0_F(cfg_board_SI_setting_ps.dram_data_odt_ohm, DDR_DRAM_DDR4_ODT_40_OHM),
+ DDR_TIMMING_TUNE_TIMMING0_F(cfg_board_SI_setting_ps.vref_dram_data_permil, 790),
+};
+////_ddr_para_2nd_setting
+//*/
+uint32_t __ddr_parameter_reg_index[] __attribute__ ((section(".ddr_2acs_index"))) = {
+ DDR_ID_START_MASK,
+ DDR_TIMMING_TUNE_STRUCT_SIZE(__bl2_ddr_reg_data),
+ //0,
+};
+#endif
+
+//#define DDR_FUNC_CONFIG_DFE_FUNCTION (1 << 29)
+//#define DDR_FUNC_CONFIG_DDR_X4_BIT_DRAM_RESERVE_PARAMETER (1 << 27)
+//#define S4_LPDDR4 1 //use for 1rank lpddr4
+
+//#define S4_LPDDR4_DONGLE_LAYER_4 1 //use for 1rank lpddr4
+//#define S4_LPDDR4_DONGLE_LAYER_6 1 //use for 1rank lpddr4
+
+//#define S4_LPDDR4_2RANK 1
+//#define S4_DDR4_2RANK 1
+#define S4_DDR4_1RANK 1
+//#define S4_DDR3 1
+ddr_set_ps0_only_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+#if 1 //timing_config,T211
+ {
+ //T211
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[0]) / sizeof(ddr_set_ps0_only_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_ps0_only_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 1, 0, 0, 0xc6, },
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1536MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE,DDR_READ_DBI_ENABLE
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .cfg_board_common_setting.pll_ssc_mode = (1 << 20) | (1 << 8) | (2 << 4) | 0, //center_ssc_1000ppm,//SSC_DISABLE,(1 << 20) | (0 << 8) | (2 << 4) | 0,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ //af419 ac pinmux
+#if 0
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3, 27, 12,
+ 21, 9, 8, 0, 14, 10, 6, 7,
+ 20, 5, 22, 13, 15, 2, 0, 0,
+ 0, 0, 11, 26, 4, 0, 0, 25,
+ 3, 1,
+ },
+#endif
+ //s4 ddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 27, 10, 25, 5, 28, 11,24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ .cfg_board_common_setting.ddr_vddee_setting[1] = (0x3 << 24) |
+ (0x93 << 16) | (0x83 << 8) | (0xd << 0),
+ .cfg_board_SI_setting_ps.DRAMFreq = 1320,
+ .cfg_board_SI_setting_ps.PllBypassEn = 0,
+ .cfg_board_SI_setting_ps.training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps.ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps.clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_34_OHM,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_34_OHM,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_80_OHM,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps.dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps.dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_48_OHM,
+ .cfg_board_SI_setting_ps.dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps.dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps.dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps.dfe_offset = 0,
+ .cfg_board_SI_setting_ps.vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps.vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps.vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps.max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps.training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps.ac_trace_delay_org =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 128,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+ .cfg_ddr_training_delay_ps.ac_trace_delay =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ },
+
+#if 1
+ .cfg_ddr_training_delay_ps.write_dqs_delay[0] = 0x0000080 + 50 + 80, // 340
+ .cfg_ddr_training_delay_ps.write_dqs_delay[1] = 0x0000080 + 50 + 80, // 335
+ .cfg_ddr_training_delay_ps.write_dqs_delay[2] = 0x0000080 + 50 + 80, // 315
+ .cfg_ddr_training_delay_ps.write_dqs_delay[3] = 0x0000080 + 50 + 80, // 345
+ .cfg_ddr_training_delay_ps.write_dqs_delay[4] = 0x0000080 + 50 + 80, // 256
+ .cfg_ddr_training_delay_ps.write_dqs_delay[5] = 0x0000080 + 50 + 80, // 256
+ .cfg_ddr_training_delay_ps.write_dqs_delay[6] = 0x0000080 + 50 + 80, // 256
+ .cfg_ddr_training_delay_ps.write_dqs_delay[7] = 0x0000080 + 50 + 80, // 256
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[0] = 0x00000c0 + 50 + 80, // 414
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[1] = 0x00000c0 + 50 + 80, // 393
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[2] = 0x00000c0 + 50 + 80, // 387
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[3] = 0x00000c0 + 50 + 80, // 422
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[4] = 0x00000c0 + 50 + 80, // 427
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[5] = 0x00000c0 + 50 + 80, // 402
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[6] = 0x00000c0 + 50 + 80, // 397
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[7] = 0x00000c0 + 50 + 80, // 402
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[8] = 0x00000c0 + 50 + 80, // 406
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[9] = 0x00000c0 + 50 + 80, // 384
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[10] = 0x00000c0 + 50 + 80, // 384
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[11] = 0x00000c0 + 50 + 80, // 371
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[12] = 0x00000c0 + 50 + 80, // 380
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[13] = 0x00000c0 + 50 + 80, // 398
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[14] = 0x00000c0 + 50 + 80, // 390
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[15] = 0x00000c0 + 50 + 80, // 377
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[16] = 0x00000c0 + 50 + 80, // 388
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[17] = 0x00000c0 + 50 + 80, // 384
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[18] = 0x00000c0 + 50 + 80, // 381
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[19] = 0x00000c0 + 50 + 80, // 365
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[20] = 0x00000c0 + 50 + 80, // 378
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[21] = 0x00000c0 + 50 + 80, // 396
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[22] = 0x00000c0 + 50 + 80, // 382
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[23] = 0x00000c0 + 50 + 80, // 399
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[24] = 0x00000c0 + 50 + 80, // 387
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[25] = 0x00000c0 + 50 + 80, // 397
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[26] = 0x00000c0 + 50 + 80, // 382
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[27] = 0x00000c0 + 50 + 80, // 380
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[28] = 0x00000c0 + 50 + 80, // 407
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[29] = 0x00000c0 + 50 + 80, // 398
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[30] = 0x00000c0 + 50 + 80, // 409
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[31] = 0x00000c0 + 50 + 80, // 385
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[32] = 0x00000c0 + 50 + 80, // 379
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[33] = 0x00000c0 + 50 + 80, // 399
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[34] = 0x00000c0 + 50 + 80, // 380
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[35] = 0x00000c0 + 50 + 80, // 393
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[36] = 0x0000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[37] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[38] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[39] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[40] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[41] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[42] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[43] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[44] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[45] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[46] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[47] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[48] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[49] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[50] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[51] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[52] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[53] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[54] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[55] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[56] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[57] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[58] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[59] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[60] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[61] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[62] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[63] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[64] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[65] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[66] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[67] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[68] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[69] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[70] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[71] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay =
+ {
+ 128 * 7, 128 * 7, 128 * 7, 128 * 7, 128 * 7, 128 * 7, 128 * 7, 128 * 7
+ }, //total 8
+ .cfg_ddr_training_delay_ps.read_dqs_delay =
+ {
+ 64, 64, 80, 64, 64, 64, 64, 64
+ }, //total 8
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay =
+ {
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0
+ },
+#endif
+ //total 72
+ .cfg_ddr_training_delay_ps.soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 48, 40, 48,
+ 40, 48, 40, 48
+ }, //total 44
+ .cfg_ddr_training_delay_ps.dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps.reserve_training_parameter = { 0xa + 4, 0x5 + 5, 0xa + 4, 0x7 + 8, 0, 0, 0, 0, 0x4, 0x4, 0x82, 0x3 },
+
+ .cfg_board_SI_setting_ps.vref_soc_data_permil = 0x0, // 0
+ .cfg_board_SI_setting_ps.vref_dram_data_permil = 0x000002bc, // 700
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[0] = 0x00000080, // 128
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[1] = 0x00000080, // 128
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[2] = 0x00000058, // 88
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[3] = 0x00000080, // 128
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[4] = 0x00000080, // 128
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[5] = 0x00000080, // 128
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[6] = 0x00000080, // 128
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[7] = 0x00000080, // 128
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[8] = 0x00000180, // 384
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[9] = 0x00000180, // 384
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[10] = 0x00000100, // 256
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[11] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[12] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[13] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[14] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[15] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[16] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[17] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[18] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[19] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[20] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[21] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[22] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[23] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[24] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[25] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[26] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[27] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[28] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[29] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[30] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[31] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[32] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[33] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[34] = 0x00000000, // 0
+ .cfg_board_SI_setting_ps.ac_trace_delay_org[35] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.ac_trace_delay[0] = 0x00000080, // 128
+ .cfg_ddr_training_delay_ps.ac_trace_delay[1] = 0x00000080, // 128
+ .cfg_ddr_training_delay_ps.ac_trace_delay[2] = 0x00000058, // 88
+ .cfg_ddr_training_delay_ps.ac_trace_delay[3] = 0x00000080, // 128
+ .cfg_ddr_training_delay_ps.ac_trace_delay[4] = 0x00000080, // 128
+ .cfg_ddr_training_delay_ps.ac_trace_delay[5] = 0x00000080, // 128
+ .cfg_ddr_training_delay_ps.ac_trace_delay[6] = 0x00000080, // 128
+ .cfg_ddr_training_delay_ps.ac_trace_delay[7] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[8] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[9] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[10] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[11] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[12] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[13] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[14] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[15] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[16] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[17] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[18] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[19] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[20] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[21] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[22] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[23] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[24] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.ac_trace_delay[25] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.ac_trace_delay[26] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.ac_trace_delay[27] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.ac_trace_delay[28] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[29] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[30] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[31] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[32] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[33] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[34] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.ac_trace_delay[35] = 0x00000180, // 384
+ .cfg_ddr_training_delay_ps.write_dqs_delay[0] = 0x000000b0, // 176
+ .cfg_ddr_training_delay_ps.write_dqs_delay[1] = 0x000000c4, // 196
+ .cfg_ddr_training_delay_ps.write_dqs_delay[2] = 0x000000c7, // 199
+ .cfg_ddr_training_delay_ps.write_dqs_delay[3] = 0x000000a7, // 167
+ .cfg_ddr_training_delay_ps.write_dqs_delay[4] = 0x00000102, // 258
+ .cfg_ddr_training_delay_ps.write_dqs_delay[5] = 0x00000102, // 258
+ .cfg_ddr_training_delay_ps.write_dqs_delay[6] = 0x00000102, // 258
+ .cfg_ddr_training_delay_ps.write_dqs_delay[7] = 0x00000102, // 258
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[0] = 0x000000ec, // 236
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[1] = 0x000000db, // 219
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[2] = 0x000000e7, // 231
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[3] = 0x000000e3, // 227
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[4] = 0x000000da, // 218
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[5] = 0x000000c9, // 201
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[6] = 0x000000e6, // 230
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[7] = 0x000000e9, // 233
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[8] = 0x000000da, // 218
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[9] = 0x0000010b, // 267
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[10] = 0x000000e8, // 232
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[11] = 0x000000f9, // 249
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[12] = 0x000000f3, // 243
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[13] = 0x000000f7, // 247
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[14] = 0x000000f4, // 244
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[15] = 0x00000104, // 260
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[16] = 0x000000f9, // 249
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[17] = 0x000000fc, // 252
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[18] = 0x000000fa, // 250
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[19] = 0x000000e0, // 224
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[20] = 0x000000f3, // 243
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[21] = 0x000000e4, // 228
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[22] = 0x000000f9, // 249
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[23] = 0x000000f5, // 245
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[24] = 0x000000f0, // 240
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[25] = 0x000000f5, // 245
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[26] = 0x000000ec, // 236
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[27] = 0x000000f5, // 245
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[28] = 0x000000ce, // 206
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[29] = 0x000000e9, // 233
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[30] = 0x000000de, // 222
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[31] = 0x000000ef, // 239
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[32] = 0x000000d8, // 216
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[33] = 0x000000df, // 223
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[34] = 0x000000d9, // 217
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[35] = 0x000000e0, // 224
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[36] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[37] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[38] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[39] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[40] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[41] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[42] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[43] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[44] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[45] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[46] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[47] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[48] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[49] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[50] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[51] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[52] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[53] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[54] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[55] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[56] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[57] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[58] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[59] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[60] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[61] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[62] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[63] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[64] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[65] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[66] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[67] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[68] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[69] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[70] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[71] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[0] = 0x0000009e,
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[1] = 0x00000099,
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[2] = 0x000000ea,
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[3] = 0x000000bc,
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[4] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[5] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[6] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[7] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_delay[0] = 0x00000086, // 134
+ .cfg_ddr_training_delay_ps.read_dqs_delay[1] = 0x0000007f, // 127
+ .cfg_ddr_training_delay_ps.read_dqs_delay[2] = 0x0000006f, // 111
+ .cfg_ddr_training_delay_ps.read_dqs_delay[3] = 0x00000066, // 102
+ .cfg_ddr_training_delay_ps.read_dqs_delay[4] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_delay[5] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_delay[6] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_delay[7] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[0] = 0x00000059, // 89
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[1] = 0x00000047, // 71
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[2] = 0x00000055, // 85
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[3] = 0x0000004b, // 75
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[4] = 0x0000004e, // 78
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[5] = 0x00000036, // 54
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[6] = 0x00000056, // 86
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[7] = 0x0000004b, // 75
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[8] = 0x0000004c, // 76
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[9] = 0x00000059, // 89
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[10] = 0x00000036, // 54
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[11] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[12] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[13] = 0x0000004d, // 77
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[14] = 0x00000041, // 65
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[15] = 0x00000058, // 88
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[16] = 0x0000003f, // 63
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[17] = 0x00000045, // 69
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[18] = 0x00000055, // 85
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[19] = 0x00000034, // 52
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[20] = 0x00000049, // 73
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[21] = 0x00000038, // 56
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[22] = 0x00000057, // 87
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[23] = 0x0000004d, // 77
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[24] = 0x0000004d, // 77
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[25] = 0x00000047, // 71
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[26] = 0x00000048, // 72
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[27] = 0x00000061, // 97
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[28] = 0x00000039, // 57
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[29] = 0x0000004e, // 78
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[30] = 0x0000003f, // 63
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[31] = 0x0000005c, // 92
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[32] = 0x00000036, // 54
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[33] = 0x00000056, // 86
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[34] = 0x00000047, // 71
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[35] = 0x0000004a, // 74
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[36] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[37] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[38] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[39] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[40] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[41] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[42] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[43] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[44] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[45] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[46] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[47] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[48] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[49] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[50] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[51] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[52] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[53] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[54] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[55] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[56] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[57] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[58] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[59] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[60] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[61] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[62] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[63] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[64] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[65] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[66] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[67] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[68] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[69] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[70] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[71] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.soc_bit_vref[0] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.soc_bit_vref[1] = 0x00000026, // 38
+ .cfg_ddr_training_delay_ps.soc_bit_vref[2] = 0x00000029, // 41
+ .cfg_ddr_training_delay_ps.soc_bit_vref[3] = 0x00000025, // 37
+ .cfg_ddr_training_delay_ps.soc_bit_vref[4] = 0x00000024, // 36
+ .cfg_ddr_training_delay_ps.soc_bit_vref[5] = 0x0000002b, // 43
+ .cfg_ddr_training_delay_ps.soc_bit_vref[6] = 0x00000027, // 39
+ .cfg_ddr_training_delay_ps.soc_bit_vref[7] = 0x00000027, // 39
+ .cfg_ddr_training_delay_ps.soc_bit_vref[8] = 0x00000026, // 38
+ .cfg_ddr_training_delay_ps.soc_bit_vref[9] = 0x00000027, // 39
+ .cfg_ddr_training_delay_ps.soc_bit_vref[10] = 0x00000022, // 34
+ .cfg_ddr_training_delay_ps.soc_bit_vref[11] = 0x00000023, // 35
+ .cfg_ddr_training_delay_ps.soc_bit_vref[12] = 0x00000023, // 35
+ .cfg_ddr_training_delay_ps.soc_bit_vref[13] = 0x00000023, // 35
+ .cfg_ddr_training_delay_ps.soc_bit_vref[14] = 0x00000023, // 35
+ .cfg_ddr_training_delay_ps.soc_bit_vref[15] = 0x00000024, // 36
+ .cfg_ddr_training_delay_ps.soc_bit_vref[16] = 0x00000026, // 38
+ .cfg_ddr_training_delay_ps.soc_bit_vref[17] = 0x00000026, // 38
+ .cfg_ddr_training_delay_ps.soc_bit_vref[18] = 0x00000027, // 39
+ .cfg_ddr_training_delay_ps.soc_bit_vref[19] = 0x00000028, // 40
+ .cfg_ddr_training_delay_ps.soc_bit_vref[20] = 0x00000025, // 37
+ .cfg_ddr_training_delay_ps.soc_bit_vref[21] = 0x00000024, // 36
+ .cfg_ddr_training_delay_ps.soc_bit_vref[22] = 0x00000024, // 36
+ .cfg_ddr_training_delay_ps.soc_bit_vref[23] = 0x00000025, // 37
+ .cfg_ddr_training_delay_ps.soc_bit_vref[24] = 0x0000002a, // 42
+ .cfg_ddr_training_delay_ps.soc_bit_vref[25] = 0x00000026, // 38
+ .cfg_ddr_training_delay_ps.soc_bit_vref[26] = 0x00000026, // 38
+ .cfg_ddr_training_delay_ps.soc_bit_vref[27] = 0x00000023, // 35
+ .cfg_ddr_training_delay_ps.soc_bit_vref[28] = 0x00000026, // 38
+ .cfg_ddr_training_delay_ps.soc_bit_vref[29] = 0x00000024, // 36
+ .cfg_ddr_training_delay_ps.soc_bit_vref[30] = 0x00000028, // 40
+ .cfg_ddr_training_delay_ps.soc_bit_vref[31] = 0x00000027, // 39
+ .cfg_ddr_training_delay_ps.soc_bit_vref[32] = 0x00000026, // 38
+ .cfg_ddr_training_delay_ps.soc_bit_vref[33] = 0x00000026, // 38
+ .cfg_ddr_training_delay_ps.soc_bit_vref[34] = 0x00000025, // 37
+ .cfg_ddr_training_delay_ps.soc_bit_vref[35] = 0x00000026, // 38
+ .cfg_ddr_training_delay_ps.soc_bit_vref[36] = 0x00000026, // 38
+ .cfg_ddr_training_delay_ps.soc_bit_vref[37] = 0x00000030, // 48
+ .cfg_ddr_training_delay_ps.soc_bit_vref[38] = 0x00000026, // 38
+ .cfg_ddr_training_delay_ps.soc_bit_vref[39] = 0x0000002f, // 47
+ .cfg_ddr_training_delay_ps.soc_bit_vref[40] = 0x00000026, // 38
+ .cfg_ddr_training_delay_ps.soc_bit_vref[41] = 0x0000002f, // 47
+ .cfg_ddr_training_delay_ps.soc_bit_vref[42] = 0x00000026, // 38
+ .cfg_ddr_training_delay_ps.soc_bit_vref[43] = 0x0000002b, // 43
+ },
+#endif //end T211
+#if S4_DDR3
+ {
+ //timing_config,T212_DONGLE 4layer LPDDR4 rank01
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[0]) / sizeof(ddr_set_ps0_only_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_ps0_only_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0 },
+ .cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION | DDR_FUNC_CONFIG_DDR_X4_BIT_DRAM_RESERVE_PARAMETER, //DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR3,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, //CONFIG_DDR0_32BIT_RANK01_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_2048MB, //CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE,DDR_READ_DBI_ENABLE
+ .cfg_board_common_setting.pll_ssc_mode = (1 << 20) | (1 << 8) | (2 << 4) | 0, //center_ssc_1000ppm,//SSC_DISABLE,(1 << 20) | (0 << 8) | (2 << 4) | 0,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR3_32BIT, //DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_DDR3_32BIT
+
+ //s4 ddr3 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 11, 14, 13, 5, 25, 6,27, 0, 15, 7, 26, 9, 4, 20, 8, 21, 0, 0, 0, 0, 10, 2, 3, 0, 0, 1, 12, 22, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps.DRAMFreq = 792,
+ .cfg_board_SI_setting_ps.PllBypassEn = 0,
+ .cfg_board_SI_setting_ps.training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps.ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps.clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps.dram_data_drv_ohm = DDR_DRAM_DDR3_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.dram_data_odt_ohm = DDR_DRAM_DDR3_ODT_120_OHM,
+ .cfg_board_SI_setting_ps.dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps.dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_120_OHM,
+ .cfg_board_SI_setting_ps.dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps.dfe_offset = 0,
+ .cfg_board_SI_setting_ps.vref_ac_permil = 300,
+ .cfg_board_SI_setting_ps.vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps.vref_dram_data_permil = 330, //330
+ .cfg_board_SI_setting_ps.max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps.training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps.ac_trace_delay_org =
+ {
+ 64 + 128, 64 + 128, 128, 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0,
+ 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128 - 44, 128 + 20 + 128 - 36, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps.ac_trace_delay =
+ {
+ 64 + 128, 64 + 128, 128 - 60, 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0,
+ 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128 - 44, 128 + 20 + 128 - 36, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ },
+
+#if 1
+ .cfg_ddr_training_delay_ps.write_dqs_delay[0] = 128, // 110
+ .cfg_ddr_training_delay_ps.write_dqs_delay[1] = 128 + 0, // 140
+ .cfg_ddr_training_delay_ps.write_dqs_delay[2] = 128 + 0, // 110
+ .cfg_ddr_training_delay_ps.write_dqs_delay[3] = 128 + 0, // 140
+ .cfg_ddr_training_delay_ps.write_dqs_delay[4] = 0x0000006e, // 110
+ .cfg_ddr_training_delay_ps.write_dqs_delay[5] = 0x00000082, // 130
+ .cfg_ddr_training_delay_ps.write_dqs_delay[6] = 0x0000006e, // 110
+ .cfg_ddr_training_delay_ps.write_dqs_delay[7] = 0x0000008c, // 140
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[0] = 128 + 64,
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[1] = 128 + 64,
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[2] = 128 + 64,
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[3] = 128 + 64,
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[4] = 128 + 64,
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[5] = 128 + 64,
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[6] = 128 + 64,
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[7] = 128 + 64,
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[8] = 128 + 64,
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[9] = 128 + 64 + 40, // 366
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[10] = 128 + 64 + 40, // 325
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[11] = 128 + 64 + 40, // 343
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[12] = 128 + 64 + 40, // 345
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[13] = 128 + 64 + 40, // 361
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[14] = 128 + 64 + 40, // 344
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[15] = 128 + 64 + 40, // 354
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[16] = 128 + 64 + 40, // 344
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[17] = 128 + 64 + 40, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[18] = 128 + 64 + 90, // 349
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[19] = 128 + 64 + 90, // 322
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[20] = 128 + 64 + 90, // 327
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[21] = 128 + 64 + 90, // 316
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[22] = 128 + 64 + 90, // 335
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[23] = 128 + 64 + 90, // 319
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[24] = 128 + 64 + 90, // 330
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[25] = 128 + 64 + 90, // 331
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[26] = 128 + 64 + 90, // 333
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[27] = 128 + 64 + 90, // 366
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[28] = 128 + 64 + 90, // 334
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[29] = 128 + 64 + 90, // 356
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[30] = 128 + 64 + 90, // 350
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[31] = 128 + 64 + 90, // 363
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[32] = 128 + 64 + 90, // 345
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[33] = 128 + 64 + 90, // 355
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[34] = 128 + 64 + 90, // 345
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[35] = 128 + 64 + 90, // 350
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[36] = 0x00000155, // 341
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[37] = 0x00000145, // 325
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[38] = 0x0000014e, // 334
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[39] = 0x0000014f, // 335
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[40] = 0x0000014e, // 334
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[41] = 0x00000138, // 312
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[42] = 0x0000014d, // 333
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[43] = 0x00000154, // 340
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[44] = 0x00000145, // 325
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[45] = 0x00000166, // 358
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[46] = 0x0000013e, // 318
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[47] = 0x00000151, // 337
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[48] = 0x00000151, // 337
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[49] = 0x00000161, // 353
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[50] = 0x00000152, // 338
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[51] = 0x0000015c, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[52] = 0x00000150, // 336
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[53] = 0x00000153, // 339
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[54] = 0x00000160, // 352
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[55] = 0x00000144, // 324
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[56] = 0x0000014c, // 332
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[57] = 0x00000140, // 320
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[58] = 0x00000152, // 338
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[59] = 0x00000142, // 322
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[60] = 0x0000014d, // 333
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[61] = 0x0000014e, // 334
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[62] = 0x00000150, // 336
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[63] = 0x00000172, // 370
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[64] = 0x00000153, // 339
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[65] = 0x00000168, // 360
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[66] = 0x00000162, // 354
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[67] = 0x0000016e, // 366
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[68] = 0x0000015c, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[69] = 0x00000166, // 358
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[70] = 0x0000015c, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[71] = 0x00000163, // 355
+
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[0] = 650, // 933
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[1] = 660, // 921
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[2] = 770, // 938
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[3] = 720, // 910
+
+
+
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[4] = 700, // 846
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[5] = 700, // 1092
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[6] = 700, // 852
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[7] = 700, // 823
+ .cfg_ddr_training_delay_ps.read_dqs_delay[0] = 0x0000007f, // 127
+ .cfg_ddr_training_delay_ps.read_dqs_delay[1] = 0x00000085, // 133
+ .cfg_ddr_training_delay_ps.read_dqs_delay[2] = 0x00000079, // 121
+ .cfg_ddr_training_delay_ps.read_dqs_delay[3] = 0x00000086, // 134
+ .cfg_ddr_training_delay_ps.read_dqs_delay[4] = 0x00000081, // 129
+ .cfg_ddr_training_delay_ps.read_dqs_delay[5] = 0x00000089, // 137
+ .cfg_ddr_training_delay_ps.read_dqs_delay[6] = 0x00000085, // 133
+ .cfg_ddr_training_delay_ps.read_dqs_delay[7] = 0x00000092, // 146
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[0] = 0x0000004a, // 70
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[1] = 0x0000003a, // 55
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[2] = 0x0000003a, // 71
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[3] = 0x0000004e, // 65
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[4] = 0x00000043, // 72
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[5] = 0x0000004c, // 53
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[6] = 0x0000003b, // 71
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[7] = 0x0000004f, // 60
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[8] = 0x00000044, // 64
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[9] = 0x00000052, // 82
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[10] = 0x00000031, // 49
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[11] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[12] = 0x00000039, // 57
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[13] = 0x00000053, // 83
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[14] = 0x0000003f, // 63
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[15] = 0x00000053, // 83
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[16] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[17] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[18] = 0x00000059, // 89
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[19] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[20] = 0x00000043, // 67
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[21] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[22] = 0x0000004c, // 76
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[23] = 0x00000038, // 56
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[24] = 0x00000045, // 69
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[25] = 0x0000003f, // 63
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[26] = 0x00000041, // 65
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[27] = 0x0000005d, // 93
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[28] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[29] = 0x0000004b, // 75
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[30] = 0x00000040, // 64
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[31] = 0x0000005e, // 94
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[32] = 0x00000039, // 57
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[33] = 0x00000054, // 84
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[34] = 0x00000042, // 66
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[35] = 0x00000049, // 73
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[36] = 0x0000004a, // 74
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[37] = 0x00000039, // 57
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[38] = 0x0000004c, // 76
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[39] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[40] = 0x0000004b, // 75
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[41] = 0x00000036, // 54
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[42] = 0x0000004d, // 77
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[43] = 0x0000003f, // 63
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[44] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[45] = 0x00000055, // 85
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[46] = 0x00000032, // 50
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[47] = 0x00000048, // 72
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[48] = 0x0000003d, // 61
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[49] = 0x00000057, // 87
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[50] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[51] = 0x00000055, // 85
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[52] = 0x00000040, // 64
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[53] = 0x00000047, // 71
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[54] = 0x00000062, // 98
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[55] = 0x0000003d, // 61
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[56] = 0x0000004f, // 79
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[57] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[58] = 0x00000056, // 86
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[59] = 0x00000042, // 66
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[60] = 0x00000050, // 80
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[61] = 0x00000049, // 73
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[62] = 0x0000004b, // 75
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[63] = 0x00000067, // 103
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[64] = 0x0000003d, // 61
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[65] = 0x00000055, // 85
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[66] = 0x0000004a, // 74
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[67] = 0x00000066, // 102
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[68] = 0x00000042, // 66
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[69] = 0x0000005e, // 94
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[70] = 0x0000004b, // 75
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[71] = 0x00000052, // 82
+#endif
+#if 1
+ .cfg_ddr_training_delay_ps.soc_bit_vref[0] = 0, //32//0x00000018,// 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[1] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[2] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[3] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[4] = 0x20, // 25
+ .cfg_ddr_training_delay_ps.soc_bit_vref[5] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[6] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[7] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[8] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[9] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[10] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[11] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[12] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[13] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[14] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[15] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[16] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[17] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[18] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[19] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[20] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[21] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[22] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[23] = 0x20, // 25
+ .cfg_ddr_training_delay_ps.soc_bit_vref[24] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[25] = 0x20, // 25
+ .cfg_ddr_training_delay_ps.soc_bit_vref[26] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[27] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[28] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[29] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[30] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[31] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[32] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[33] = 0x24, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[34] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[35] = 0x24, // 24
+#endif
+#if 1
+ .cfg_ddr_training_delay_ps.soc_bit_vref[36] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[37] = 0x24, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[38] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[39] = 0x24, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[40] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[41] = 0x24, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[42] = 0x20, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[43] = 0x24, // 24
+#endif
+#if 1
+ .cfg_ddr_training_delay_ps.dram_bit_vref[0] = 0x00000000, // 0X5b,// 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[1] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[2] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[3] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[4] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[5] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[6] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[7] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[8] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[9] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[10] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[11] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[12] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[13] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[14] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[15] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[16] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[17] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[18] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[19] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[20] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[21] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[22] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[23] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[24] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[25] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[26] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[27] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[28] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[29] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[30] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[31] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[32] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[33] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[34] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[35] = 0x00000000, // 0
+#endif
+
+ .cfg_ddr_training_delay_ps.reserve_training_parameter = { 0, 0, 0, 0, 8, 8, 8, 8, 0, 0, 0, 0, 0x80 + 0x10, 0x80 + 0x10, 0x80 + 0x10, 0x80 + 0x10 },
+
+ },
+#endif //end T212_DONGLE 4layer LPDDR4 rank01
+#if S4_LPDDR4
+ {
+ //timing_config,T212_DONGLE 4layer LPDDR4 rank01
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[0]) / sizeof(ddr_set_ps0_only_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_ps0_only_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0 },
+ //.cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0, //CONFIG_DDR0_32BIT_RANK01_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, //CONFIG_DDR0_SIZE_2048MB,// CONFIG_DDR0_SIZE_1024MB, //CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR0_SIZE_0MB, //CONFIG_DDR0_SIZE_2048MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_READ_DBI_ENABLE, //DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE,DDR_READ_DBI_ENABLE
+ .cfg_board_common_setting.pll_ssc_mode = (1 << 20) | (1 << 8) | (2 << 4) | 0, //center_ssc_1000ppm,//SSC_DISABLE,(1 << 20) | (0 << 8) | (2 << 4) | 0,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, //DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_DDR3_32BIT
+
+ //s4 lpddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 0, 1, 2, 0,
+ 5, 1, 0, 0, 0, 1, 0, 2,
+ 0, 3, 0, 3, 5, 0, 0, 0,
+ 0, 0, 4, 4, 0, 0, 0, 0,
+ 0, 0, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 8, 12, 13, 11, 14, 9, 10, 15,
+ 0, 2, 5, 6, 3, 7, 1, 4,
+ 27, 31, 28, 24, 25, 29, 26, 30,
+ 21, 18, 22, 19, 16, 17, 23, 20,
+ 33, 32, 35, 34
+ },
+
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 15, 8, 12, 13, 11, 14, 10, 9,
+ 7, 3, 0, 1, 4, 5, 2, 6,
+ 16, 19, 23, 21, 18, 22, 20, 17,
+ 31, 27, 30, 26, 25, 29, 24, 28,
+ 33, 32, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps.DRAMFreq = 1320,
+ .cfg_board_SI_setting_ps.PllBypassEn = 0,
+ .cfg_board_SI_setting_ps.training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps.ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps.clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_80_OHM,
+ .cfg_board_SI_setting_ps.dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_80_OHM,
+
+
+//lpddr4 r
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_34_OHM,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_34_OHM,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_80_OHM,
+ .cfg_board_SI_setting_ps.dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+
+ .cfg_board_SI_setting_ps.dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps.dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_120_OHM,
+ .cfg_board_SI_setting_ps.dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps.dfe_offset = 0,
+ .cfg_board_SI_setting_ps.vref_ac_permil = 300,
+ .cfg_board_SI_setting_ps.vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps.vref_dram_data_permil = 330, //330
+ .cfg_board_SI_setting_ps.max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps.training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps.ac_trace_delay_org =
+ {
+ 64 + 128, 64 + 128, 128, 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0,
+ 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128 - 44, 128 + 20 + 128 - 36, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps.ac_trace_delay =
+ {
+ 64 + 128, 64 + 128, 128, 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0,
+ 128 + 0 + 128 - 15, 128 + 0 + 128 - 15, 128 + 60 + 128 - 44, 128 + 20 + 128 - 36, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ },
+
+#if 1
+ .cfg_ddr_training_delay_ps.write_dqs_delay[0] = 0x0000006e, // 110
+ .cfg_ddr_training_delay_ps.write_dqs_delay[1] = 0x0000008c, // 140
+ .cfg_ddr_training_delay_ps.write_dqs_delay[2] = 0x0000006e, // 110
+ .cfg_ddr_training_delay_ps.write_dqs_delay[3] = 0x0000008c, // 140
+ .cfg_ddr_training_delay_ps.write_dqs_delay[4] = 0x0000006e, // 110
+ .cfg_ddr_training_delay_ps.write_dqs_delay[5] = 0x00000082, // 130
+ .cfg_ddr_training_delay_ps.write_dqs_delay[6] = 0x0000006e, // 110
+ .cfg_ddr_training_delay_ps.write_dqs_delay[7] = 0x0000008c, // 140
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[0] = 0x00000153, // 339
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[1] = 0x00000144, // 324
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[2] = 0x0000014c, // 332
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[3] = 0x0000014d, // 333
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[4] = 0x0000014b, // 331
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[5] = 0x00000135, // 309
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[6] = 0x0000014c, // 332
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[7] = 0x00000152, // 338
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[8] = 0x00000142, // 322
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[9] = 0x0000016e, // 366
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[10] = 0x00000145, // 325
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[11] = 0x00000157, // 343
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[12] = 0x00000159, // 345
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[13] = 0x00000169, // 361
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[14] = 0x00000158, // 344
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[15] = 0x00000162, // 354
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[16] = 0x00000158, // 344
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[17] = 0x0000015c, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[18] = 0x0000015d, // 349
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[19] = 0x00000142, // 322
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[20] = 0x00000147, // 327
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[21] = 0x0000013c, // 316
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[22] = 0x0000014f, // 335
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[23] = 0x0000013f, // 319
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[24] = 0x0000014a, // 330
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[25] = 0x0000014b, // 331
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[26] = 0x0000014d, // 333
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[27] = 0x0000016e, // 366
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[28] = 0x0000014e, // 334
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[29] = 0x00000164, // 356
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[30] = 0x0000015e, // 350
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[31] = 0x0000016b, // 363
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[32] = 0x00000159, // 345
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[33] = 0x00000163, // 355
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[34] = 0x00000159, // 345
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[35] = 0x0000015e, // 350
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[36] = 0x00000155, // 341
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[37] = 0x00000145, // 325
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[38] = 0x0000014e, // 334
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[39] = 0x0000014f, // 335
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[40] = 0x0000014e, // 334
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[41] = 0x00000138, // 312
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[42] = 0x0000014d, // 333
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[43] = 0x00000154, // 340
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[44] = 0x00000145, // 325
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[45] = 0x00000166, // 358
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[46] = 0x0000013e, // 318
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[47] = 0x00000151, // 337
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[48] = 0x00000151, // 337
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[49] = 0x00000161, // 353
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[50] = 0x00000152, // 338
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[51] = 0x0000015c, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[52] = 0x00000150, // 336
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[53] = 0x00000153, // 339
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[54] = 0x00000160, // 352
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[55] = 0x00000144, // 324
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[56] = 0x0000014c, // 332
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[57] = 0x00000140, // 320
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[58] = 0x00000152, // 338
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[59] = 0x00000142, // 322
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[60] = 0x0000014d, // 333
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[61] = 0x0000014e, // 334
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[62] = 0x00000150, // 336
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[63] = 0x00000172, // 370
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[64] = 0x00000153, // 339
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[65] = 0x00000168, // 360
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[66] = 0x00000162, // 354
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[67] = 0x0000016e, // 366
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[68] = 0x0000015c, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[69] = 0x00000166, // 358
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[70] = 0x0000015c, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[71] = 0x00000163, // 355
+
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[0] = 0x000003a5, // 933
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[1] = 0x00000399, // 921
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[2] = 0x000003aa, // 938
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[3] = 0x0000038e, // 910
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[4] = 0x0000034e, // 846
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[5] = 0x00000444, // 1092
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[6] = 0x00000354, // 852
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[7] = 0x00000337, // 823
+ .cfg_ddr_training_delay_ps.read_dqs_delay[0] = 0x0000007f, // 127
+ .cfg_ddr_training_delay_ps.read_dqs_delay[1] = 0x00000085, // 133
+ .cfg_ddr_training_delay_ps.read_dqs_delay[2] = 0x00000079, // 121
+ .cfg_ddr_training_delay_ps.read_dqs_delay[3] = 0x00000086, // 134
+ .cfg_ddr_training_delay_ps.read_dqs_delay[4] = 0x00000081, // 129
+ .cfg_ddr_training_delay_ps.read_dqs_delay[5] = 0x00000089, // 137
+ .cfg_ddr_training_delay_ps.read_dqs_delay[6] = 0x00000085, // 133
+ .cfg_ddr_training_delay_ps.read_dqs_delay[7] = 0x00000092, // 146
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[0] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[1] = 0x00000037, // 55
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[2] = 0x00000047, // 71
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[3] = 0x00000041, // 65
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[4] = 0x00000048, // 72
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[5] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[6] = 0x00000047, // 71
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[7] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[8] = 0x00000040, // 64
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[9] = 0x00000052, // 82
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[10] = 0x00000031, // 49
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[11] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[12] = 0x00000039, // 57
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[13] = 0x00000053, // 83
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[14] = 0x0000003f, // 63
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[15] = 0x00000053, // 83
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[16] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[17] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[18] = 0x00000059, // 89
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[19] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[20] = 0x00000043, // 67
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[21] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[22] = 0x0000004c, // 76
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[23] = 0x00000038, // 56
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[24] = 0x00000045, // 69
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[25] = 0x0000003f, // 63
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[26] = 0x00000041, // 65
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[27] = 0x0000005d, // 93
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[28] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[29] = 0x0000004b, // 75
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[30] = 0x00000040, // 64
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[31] = 0x0000005e, // 94
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[32] = 0x00000039, // 57
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[33] = 0x00000054, // 84
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[34] = 0x00000042, // 66
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[35] = 0x00000049, // 73
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[36] = 0x0000004a, // 74
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[37] = 0x00000039, // 57
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[38] = 0x0000004c, // 76
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[39] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[40] = 0x0000004b, // 75
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[41] = 0x00000036, // 54
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[42] = 0x0000004d, // 77
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[43] = 0x0000003f, // 63
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[44] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[45] = 0x00000055, // 85
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[46] = 0x00000032, // 50
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[47] = 0x00000048, // 72
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[48] = 0x0000003d, // 61
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[49] = 0x00000057, // 87
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[50] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[51] = 0x00000055, // 85
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[52] = 0x00000040, // 64
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[53] = 0x00000047, // 71
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[54] = 0x00000062, // 98
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[55] = 0x0000003d, // 61
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[56] = 0x0000004f, // 79
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[57] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[58] = 0x00000056, // 86
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[59] = 0x00000042, // 66
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[60] = 0x00000050, // 80
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[61] = 0x00000049, // 73
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[62] = 0x0000004b, // 75
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[63] = 0x00000067, // 103
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[64] = 0x0000003d, // 61
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[65] = 0x00000055, // 85
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[66] = 0x0000004a, // 74
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[67] = 0x00000066, // 102
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[68] = 0x00000042, // 66
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[69] = 0x0000005e, // 94
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[70] = 0x0000004b, // 75
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[71] = 0x00000052, // 82
+#endif
+#if 1
+ .cfg_ddr_training_delay_ps.soc_bit_vref[0] = 0, //24 //0x00000018,// 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[1] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[2] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[3] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[4] = 0x00000019, // 25
+ .cfg_ddr_training_delay_ps.soc_bit_vref[5] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[6] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[7] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[8] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[9] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[10] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[11] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[12] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[13] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[14] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[15] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[16] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[17] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[18] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[19] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[20] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[21] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[22] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[23] = 0x00000019, // 25
+ .cfg_ddr_training_delay_ps.soc_bit_vref[24] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[25] = 0x00000019, // 25
+ .cfg_ddr_training_delay_ps.soc_bit_vref[26] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[27] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[28] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[29] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[30] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[31] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[32] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[33] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[34] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[35] = 0x00000018, // 24
+#endif
+#if 1
+ .cfg_ddr_training_delay_ps.soc_bit_vref[36] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[37] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[38] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[39] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[40] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[41] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[42] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[43] = 0x00000018, // 24
+#endif
+#if 1
+ .cfg_ddr_training_delay_ps.dram_bit_vref[0] = 0x00000000, // 0X5b,// 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[1] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[2] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[3] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[4] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[5] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[6] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[7] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[8] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[9] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[10] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[11] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[12] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[13] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[14] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[15] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[16] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[17] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[18] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[19] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[20] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[21] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[22] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[23] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[24] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[25] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[26] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[27] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[28] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[29] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[30] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[31] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[32] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[33] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[34] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[35] = 0x00000000, // 0
+#endif
+
+#ifdef S4_LPDDR4_DONGLE_LAYER_4
+ .cfg_ddr_training_delay_ps.reserve_training_parameter = { 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x0, 0x80 + 0x8, 0x80 + 0x10, 0x80 + 0x8, 0x80 + 0x10, 0x80 + 0x10, 0x80 + 0x10, 0x80 + 0x10, 0x80 + 0x10 },
+#endif
+#ifdef S4_LPDDR4_DONGLE_LAYER_6
+ .cfg_ddr_training_delay_ps.reserve_training_parameter = { 0x8, 0x8, 0x8, 0x8, 8, 8, 8, 8, 0x80 + 0x8, 0x80 + 0x0, 0x80 + 0x8, 0x80 + 0x8, 0x80 + 0x10, 0x80 + 0x10, 0x80 + 0x10, 0x80 + 0x10 },
+#endif
+ },
+#endif //end T212_DONGLE 4layer LPDDR4 rank01
+
+#if S4_LPDDR4_2RANK
+ {
+ //timing_config,T212_DONGLE 4layer LPDDR4 rank01
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[0]) / sizeof(ddr_set_ps0_only_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_ps0_only_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0 },
+ //.cfg_board_common_setting.ddr_func = DDR_FUNC_CONFIG_DFE_FUNCTION,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0, //CONFIG_DDR0_32BIT_RANK01_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB, //CONFIG_DDR0_SIZE_2048MB,// CONFIG_DDR0_SIZE_1024MB, //CONFIG_DDR0_SIZE_AUTO_SIZE,CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR0_SIZE_1024MB, //CONFIG_DDR0_SIZE_2048MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_1T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE, //DDR_READ_DBI_ENABLE,//DDR_WRITE_READ_DBI_DISABLE, //DDR_WRITE_READ_DBI_DISABLE,DDR_READ_DBI_ENABLE
+ .cfg_board_common_setting.pll_ssc_mode = (1 << 20) | (1 << 8) | (2 << 4) | 0, //center_ssc_1000ppm,//SSC_DISABLE,(1 << 20) | (0 << 8) | (2 << 4) | 0,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_LPDDR4_32BIT, //DDR_DMC_REMAP_LPDDR4_32BIT,//DDR_DMC_REMAP_DDR3_32BIT
+
+ //s4 lpddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 0, 1, 2, 0,
+ 5, 1, 0, 0, 0, 1, 0, 2,
+ 0, 3, 0, 3, 5, 0, 0, 0,
+ 0, 0, 4, 4, 0, 0, 0, 0,
+ 0, 0, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 8, 12, 13, 11, 14, 9, 10, 15,
+ 0, 2, 5, 6, 3, 7, 1, 4,
+ 27, 31, 28, 24, 25, 29, 26, 30,
+ 21, 18, 22, 19, 16, 17, 23, 20,
+ 33, 32, 35, 34
+ },
+
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 15, 8, 12, 13, 11, 14, 10, 9,
+ 7, 3, 0, 1, 4, 5, 2, 6,
+ 16, 19, 23, 21, 18, 22, 20, 17,
+ 31, 27, 30, 26, 25, 29, 24, 28,
+ 33, 32, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ //DDR frequercy 1
+ .cfg_board_SI_setting_ps.DRAMFreq = 1320,
+ .cfg_board_SI_setting_ps.PllBypassEn = 0,
+ .cfg_board_SI_setting_ps.training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps.ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps.clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_80_OHM,
+ .cfg_board_SI_setting_ps.dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_80_OHM,
+
+
+//lpddr4 r
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_34_OHM,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_34_OHM,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_80_OHM,
+ .cfg_board_SI_setting_ps.dram_data_drv_ohm = DDR_DRAM_LPDDR4_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.dram_data_odt_ohm = DDR_DRAM_LPDDR4_ODT_48_OHM,
+
+ .cfg_board_SI_setting_ps.dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps.dram_ac_odt_ohm = DDR_DRAM_LPDDR4_AC_ODT_120_OHM,
+ .cfg_board_SI_setting_ps.dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps.dfe_offset = 1,
+ .cfg_board_SI_setting_ps.vref_ac_permil = 300,
+ .cfg_board_SI_setting_ps.vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps.vref_dram_data_permil = 330, //330
+ .cfg_board_SI_setting_ps.max_core_timmming_frequency = 0, //1176,
+ .cfg_board_SI_setting_ps.training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps.ac_trace_delay_org =
+ {
+ 64 + 128, 64 + 128, 128, 128, 64 + 128, 64 + 128, 0 + 128, 0 + 128, //0,0,0,0,0,0,0,0,
+ 128 + 20 + 128, 128 + 20 + 128, 128 + 60 + 128 - 44, 128 + 20 + 128 - 36, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ }, //total 36
+ .cfg_ddr_training_delay_ps.ac_trace_delay =
+ {
+ 64 + 128, 64 + 128, 128, 128, 64 + 128, 64 + 128, 0 + 128, 128 + 128, //0,0,0,0,0,0,0,0,
+ 128 + 0 + 128 - 15 - 10, 128 + 0 + 128 - 15 - 20, 128 + 60 + 128 - 44, 128 + 20 + 128 - 36, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128, 128 + 0 + 128,
+ },
+
+#if 1
+ .cfg_ddr_training_delay_ps.write_dqs_delay[0] = 0x0000006e, // 110
+ .cfg_ddr_training_delay_ps.write_dqs_delay[1] = 0x0000008c, // 140
+ .cfg_ddr_training_delay_ps.write_dqs_delay[2] = 0x0000006e, // 110
+ .cfg_ddr_training_delay_ps.write_dqs_delay[3] = 0x0000008c, // 140
+ .cfg_ddr_training_delay_ps.write_dqs_delay[4] = 0x0000006e, // 110
+ .cfg_ddr_training_delay_ps.write_dqs_delay[5] = 0x00000082, // 130
+ .cfg_ddr_training_delay_ps.write_dqs_delay[6] = 0x0000006e, // 110
+ .cfg_ddr_training_delay_ps.write_dqs_delay[7] = 0x0000008c, // 140
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[0] = 0x00000153, // 339
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[1] = 0x00000144, // 324
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[2] = 0x0000014c, // 332
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[3] = 0x0000014d, // 333
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[4] = 0x0000014b, // 331
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[5] = 0x00000135, // 309
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[6] = 0x0000014c, // 332
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[7] = 0x00000152, // 338
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[8] = 0x00000142, // 322
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[9] = 0x0000016e, // 366
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[10] = 0x00000145, // 325
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[11] = 0x00000157, // 343
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[12] = 0x00000159, // 345
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[13] = 0x00000169, // 361
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[14] = 0x00000158, // 344
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[15] = 0x00000162, // 354
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[16] = 0x00000158, // 344
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[17] = 0x0000015c, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[18] = 0x0000015d, // 349
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[19] = 0x00000142, // 322
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[20] = 0x00000147, // 327
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[21] = 0x0000013c, // 316
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[22] = 0x0000014f, // 335
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[23] = 0x0000013f, // 319
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[24] = 0x0000014a, // 330
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[25] = 0x0000014b, // 331
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[26] = 0x0000014d, // 333
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[27] = 0x0000016e, // 366
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[28] = 0x0000014e, // 334
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[29] = 0x00000164, // 356
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[30] = 0x0000015e, // 350
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[31] = 0x0000016b, // 363
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[32] = 0x00000159, // 345
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[33] = 0x00000163, // 355
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[34] = 0x00000159, // 345
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[35] = 0x0000015e, // 350
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[36] = 0x00000155, // 341
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[37] = 0x00000145, // 325
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[38] = 0x0000014e, // 334
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[39] = 0x0000014f, // 335
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[40] = 0x0000014e, // 334
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[41] = 0x00000138, // 312
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[42] = 0x0000014d, // 333
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[43] = 0x00000154, // 340
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[44] = 0x00000145, // 325
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[45] = 0x00000166, // 358
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[46] = 0x0000013e, // 318
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[47] = 0x00000151, // 337
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[48] = 0x00000151, // 337
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[49] = 0x00000161, // 353
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[50] = 0x00000152, // 338
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[51] = 0x0000015c, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[52] = 0x00000150, // 336
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[53] = 0x00000153, // 339
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[54] = 0x00000160, // 352
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[55] = 0x00000144, // 324
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[56] = 0x0000014c, // 332
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[57] = 0x00000140, // 320
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[58] = 0x00000152, // 338
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[59] = 0x00000142, // 322
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[60] = 0x0000014d, // 333
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[61] = 0x0000014e, // 334
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[62] = 0x00000150, // 336
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[63] = 0x00000172, // 370
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[64] = 0x00000153, // 339
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[65] = 0x00000168, // 360
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[66] = 0x00000162, // 354
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[67] = 0x0000016e, // 366
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[68] = 0x0000015c, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[69] = 0x00000166, // 358
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[70] = 0x0000015c, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[71] = 0x00000163, // 355
+
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[0] = 0x000003a5, // 933
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[1] = 0x00000399, // 921
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[2] = 0x000003aa, // 938
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[3] = 0x0000038e, // 910
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[4] = 0x0000034e, // 846
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[5] = 0x00000444, // 1092
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[6] = 0x00000354, // 852
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[7] = 0x00000337, // 823
+ .cfg_ddr_training_delay_ps.read_dqs_delay[0] = 0x0000007f, // 127
+ .cfg_ddr_training_delay_ps.read_dqs_delay[1] = 0x00000085, // 133
+ .cfg_ddr_training_delay_ps.read_dqs_delay[2] = 0x00000079, // 121
+ .cfg_ddr_training_delay_ps.read_dqs_delay[3] = 0x00000086, // 134
+ .cfg_ddr_training_delay_ps.read_dqs_delay[4] = 0x00000081, // 129
+ .cfg_ddr_training_delay_ps.read_dqs_delay[5] = 0x00000089, // 137
+ .cfg_ddr_training_delay_ps.read_dqs_delay[6] = 0x00000085, // 133
+ .cfg_ddr_training_delay_ps.read_dqs_delay[7] = 0x00000092, // 146
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[0] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[1] = 0x00000037, // 55
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[2] = 0x00000047, // 71
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[3] = 0x00000041, // 65
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[4] = 0x00000048, // 72
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[5] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[6] = 0x00000047, // 71
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[7] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[8] = 0x00000040, // 64
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[9] = 0x00000052, // 82
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[10] = 0x00000031, // 49
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[11] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[12] = 0x00000039, // 57
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[13] = 0x00000053, // 83
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[14] = 0x0000003f, // 63
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[15] = 0x00000053, // 83
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[16] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[17] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[18] = 0x00000059, // 89
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[19] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[20] = 0x00000043, // 67
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[21] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[22] = 0x0000004c, // 76
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[23] = 0x00000038, // 56
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[24] = 0x00000045, // 69
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[25] = 0x0000003f, // 63
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[26] = 0x00000041, // 65
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[27] = 0x0000005d, // 93
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[28] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[29] = 0x0000004b, // 75
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[30] = 0x00000040, // 64
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[31] = 0x0000005e, // 94
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[32] = 0x00000039, // 57
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[33] = 0x00000054, // 84
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[34] = 0x00000042, // 66
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[35] = 0x00000049, // 73
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[36] = 0x0000004a, // 74
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[37] = 0x00000039, // 57
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[38] = 0x0000004c, // 76
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[39] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[40] = 0x0000004b, // 75
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[41] = 0x00000036, // 54
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[42] = 0x0000004d, // 77
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[43] = 0x0000003f, // 63
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[44] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[45] = 0x00000055, // 85
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[46] = 0x00000032, // 50
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[47] = 0x00000048, // 72
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[48] = 0x0000003d, // 61
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[49] = 0x00000057, // 87
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[50] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[51] = 0x00000055, // 85
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[52] = 0x00000040, // 64
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[53] = 0x00000047, // 71
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[54] = 0x00000062, // 98
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[55] = 0x0000003d, // 61
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[56] = 0x0000004f, // 79
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[57] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[58] = 0x00000056, // 86
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[59] = 0x00000042, // 66
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[60] = 0x00000050, // 80
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[61] = 0x00000049, // 73
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[62] = 0x0000004b, // 75
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[63] = 0x00000067, // 103
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[64] = 0x0000003d, // 61
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[65] = 0x00000055, // 85
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[66] = 0x0000004a, // 74
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[67] = 0x00000066, // 102
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[68] = 0x00000042, // 66
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[69] = 0x0000005e, // 94
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[70] = 0x0000004b, // 75
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[71] = 0x00000052, // 82
+#endif
+#if 1
+ .cfg_ddr_training_delay_ps.soc_bit_vref[0] = 0, //24 //0x00000018,// 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[1] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[2] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[3] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[4] = 0x00000019, // 25
+ .cfg_ddr_training_delay_ps.soc_bit_vref[5] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[6] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[7] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[8] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[9] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[10] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[11] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[12] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[13] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[14] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[15] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[16] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[17] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[18] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[19] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[20] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[21] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[22] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[23] = 0x00000019, // 25
+ .cfg_ddr_training_delay_ps.soc_bit_vref[24] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[25] = 0x00000019, // 25
+ .cfg_ddr_training_delay_ps.soc_bit_vref[26] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[27] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[28] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[29] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[30] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[31] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[32] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[33] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[34] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[35] = 0x00000018, // 24
+#endif
+#if 1
+ .cfg_ddr_training_delay_ps.soc_bit_vref[36] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[37] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[38] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[39] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[40] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[41] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[42] = 0x00000018, // 24
+ .cfg_ddr_training_delay_ps.soc_bit_vref[43] = 0x00000018, // 24
+#endif
+#if 1
+ .cfg_ddr_training_delay_ps.dram_bit_vref[0] = 0x00000000, // 0X5b,// 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[1] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[2] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[3] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[4] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[5] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[6] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[7] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[8] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[9] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[10] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[11] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[12] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[13] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[14] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[15] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[16] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[17] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[18] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[19] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[20] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[21] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[22] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[23] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[24] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[25] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[26] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[27] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[28] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[29] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[30] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[31] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[32] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[33] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[34] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.dram_bit_vref[35] = 0x00000000, // 0
+#endif
+
+ //.cfg_ddr_training_delay_ps.reserve_training_parameter = { 0x8, 0x8, 0x8, 0x8, 8, 8, 8, 8, 0x80 + 0x10, 0x80 + 0x10, 0x80 + 0x10, 0x80 + 0x10, 0x80 + 0x10, 0x80 + 0x10, 0x80 + 0x10, 0x80 + 0x10 },
+ .cfg_ddr_training_delay_ps.reserve_training_parameter = { 0x80 + 0x0, 0x80 + 0x0, 0x80 + 0x0, 0x80 + 0x0, 0x80 + 0x0, 0x80 + 0x0, 0x80 + 0x0, 0x80 + 0x0, 0x80 + 0x8, 0x80 + 0x8, 0x80 + 0x8, 0x80 + 0x8, 0x80 + 0x10, 0x80 + 0x10, 0x80 + 0x10, 0x80 + 0x10 },
+
+ },
+#endif //end T212_DONGLE 4layer LPDDR4 rank01
+#if S4_DDR4_2RANK
+ {
+ //timing_config,4layer 4pcs ddr4 rank01, ap222.
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[0]) / sizeof(ddr_set_ps0_only_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_ps0_only_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0, 0, (1 << 3) | (2) },
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_1024MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_1024MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting.pll_ssc_mode = (1 << 20) | (1 << 8) | (2 << 4) | 0, //center_ssc_1000ppm,//SSC_DISABLE,(1 << 20) | (0 << 8) | (2 << 4) | 0,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ //af419 ac pinmux
+#if 0
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3, 27, 12,
+ 21, 9, 8, 0, 14, 10, 6, 7,
+ 20, 5, 22, 13, 15, 2, 0, 0,
+ 0, 0, 11, 26, 4, 0, 0, 25,
+ 3, 1,
+ },
+#endif
+ //s4 ddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 27, 10, 25, 5, 28, 11,24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ .cfg_board_SI_setting_ps.DRAMFreq = 1176,
+ .cfg_board_SI_setting_ps.PllBypassEn = 0,
+ .cfg_board_SI_setting_ps.training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps.ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT01_CS1_ODT01__R_CS0_ODT1_CS1_ODT0,
+ .cfg_board_SI_setting_ps.clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_34_OHM,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_34_OHM,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_120_OHM,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps.dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps.dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.dram_data_wr_odt_ohm = DDR_DRAM_DDR4_WR_ODT_240_OHM,
+ .cfg_board_SI_setting_ps.dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps.dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps.dfe_offset = 0,
+ .cfg_board_SI_setting_ps.vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps.vref_soc_data_permil = 750, //820,// 750,
+ .cfg_board_SI_setting_ps.vref_dram_data_permil = 750,
+ .cfg_board_SI_setting_ps.max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps.training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps.ac_trace_delay_org =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 128,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+ .cfg_ddr_training_delay_ps.ac_trace_delay =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ },
+
+#if 1
+ .cfg_ddr_training_delay_ps.write_dqs_delay[0] = 0x000000e1, // 225
+ .cfg_ddr_training_delay_ps.write_dqs_delay[1] = 0x000000eb, // 235
+ .cfg_ddr_training_delay_ps.write_dqs_delay[2] = 0x000000e1, // 225
+ .cfg_ddr_training_delay_ps.write_dqs_delay[3] = 0x000000d7, // 215
+ .cfg_ddr_training_delay_ps.write_dqs_delay[4] = 0x000000d7, // 215
+ .cfg_ddr_training_delay_ps.write_dqs_delay[5] = 0x000000e1, // 225
+ .cfg_ddr_training_delay_ps.write_dqs_delay[6] = 0x000000e1, // 225
+ .cfg_ddr_training_delay_ps.write_dqs_delay[7] = 0x000000d7, // 215
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[0] = 0x00000130, // 304
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[1] = 0x00000120, // 288
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[2] = 0x00000132, // 306
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[3] = 0x00000125, // 293
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[4] = 0x0000012b, // 299
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[5] = 0x00000115, // 277
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[6] = 0x00000131, // 305
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[7] = 0x0000012d, // 301
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[8] = 0x00000124, // 292
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[9] = 0x00000134, // 308
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[10] = 0x00000115, // 277
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[11] = 0x00000127, // 295
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[12] = 0x0000011f, // 287
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[13] = 0x00000141, // 321
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[14] = 0x00000129, // 297
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[15] = 0x00000137, // 311
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[16] = 0x00000120, // 288
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[17] = 0x0000012a, // 298
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[18] = 0x00000127, // 295
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[19] = 0x00000112, // 274
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[20] = 0x00000119, // 281
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[21] = 0x00000115, // 277
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[22] = 0x0000012b, // 299
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[23] = 0x0000011c, // 284
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[24] = 0x00000116, // 278
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[25] = 0x00000120, // 288
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[26] = 0x0000011f, // 287
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[27] = 0x0000012b, // 299
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[28] = 0x00000113, // 275
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[29] = 0x0000011f, // 287
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[30] = 0x00000117, // 279
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[31] = 0x00000126, // 294
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[32] = 0x00000117, // 279
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[33] = 0x0000011c, // 284
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[34] = 0x00000113, // 275
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[35] = 0x0000011f, // 287
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[36] = 0x0000012d, // 301
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[37] = 0x0000011f, // 287
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[38] = 0x00000125, // 293
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[39] = 0x0000011e, // 286
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[40] = 0x0000011a, // 282
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[41] = 0x00000108, // 264
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[42] = 0x00000121, // 289
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[43] = 0x0000011f, // 287
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[44] = 0x0000011b, // 283
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[45] = 0x0000012a, // 298
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[46] = 0x0000010c, // 268
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[47] = 0x00000118, // 280
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[48] = 0x00000115, // 277
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[49] = 0x0000012f, // 303
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[50] = 0x0000011f, // 287
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[51] = 0x00000126, // 294
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[52] = 0x00000118, // 280
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[53] = 0x0000011d, // 285
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[54] = 0x00000139, // 313
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[55] = 0x0000011b, // 283
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[56] = 0x0000011e, // 286
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[57] = 0x00000123, // 291
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[58] = 0x00000127, // 295
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[59] = 0x00000118, // 280
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[60] = 0x0000011b, // 283
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[61] = 0x0000011e, // 286
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[62] = 0x0000012d, // 301
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[63] = 0x0000012c, // 300
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[64] = 0x00000117, // 279
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[65] = 0x00000122, // 290
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[66] = 0x00000118, // 280
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[67] = 0x00000127, // 295
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[68] = 0x00000119, // 281
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[69] = 0x0000011c, // 284
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[70] = 0x00000118, // 280
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[71] = 0x00000122, // 290
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[0] = 0x00000376, // 886
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[1] = 0x00000372, // 882
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[2] = 0x00000366, // 870
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[3] = 0x0000036c, // 876
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[4] = 0x00000378, // 888
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[5] = 0x00000373, // 883
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[6] = 0x0000036d, // 877
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[7] = 0x00000371, // 881
+ .cfg_ddr_training_delay_ps.read_dqs_delay[0] = 0x00000059, // 89
+ .cfg_ddr_training_delay_ps.read_dqs_delay[1] = 0x00000063, // 99
+ .cfg_ddr_training_delay_ps.read_dqs_delay[2] = 0x00000075, // 117
+ .cfg_ddr_training_delay_ps.read_dqs_delay[3] = 0x00000060, // 96
+ .cfg_ddr_training_delay_ps.read_dqs_delay[4] = 0x00000071, // 113
+ .cfg_ddr_training_delay_ps.read_dqs_delay[5] = 0x00000086, // 134
+ .cfg_ddr_training_delay_ps.read_dqs_delay[6] = 0x00000079, // 121
+ .cfg_ddr_training_delay_ps.read_dqs_delay[7] = 0x00000086, // 134
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[0] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[1] = 0x00000028, // 40
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[2] = 0x0000003a, // 58
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[3] = 0x0000002e, // 46
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[4] = 0x00000033, // 51
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[5] = 0x00000028, // 40
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[6] = 0x00000039, // 57
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[7] = 0x0000002f, // 47
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[8] = 0x00000031, // 49
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[9] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[10] = 0x0000002a, // 42
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[11] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[12] = 0x0000002c, // 44
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[13] = 0x0000004a, // 74
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[14] = 0x00000034, // 52
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[15] = 0x00000042, // 66
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[16] = 0x0000002d, // 45
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[17] = 0x00000036, // 54
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[18] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[19] = 0x0000002b, // 43
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[20] = 0x00000036, // 54
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[21] = 0x0000002c, // 44
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[22] = 0x0000004a, // 74
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[23] = 0x00000039, // 57
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[24] = 0x0000003b, // 59
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[25] = 0x00000038, // 56
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[26] = 0x00000037, // 55
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[27] = 0x00000037, // 55
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[28] = 0x00000027, // 39
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[29] = 0x00000032, // 50
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[30] = 0x0000002b, // 43
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[31] = 0x0000003e, // 62
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[32] = 0x00000029, // 41
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[33] = 0x00000031, // 49
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[34] = 0x0000002a, // 42
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[35] = 0x0000002f, // 47
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[36] = 0x0000004a, // 74
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[37] = 0x00000041, // 65
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[38] = 0x00000045, // 69
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[39] = 0x0000003f, // 63
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[40] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[41] = 0x00000031, // 49
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[42] = 0x00000049, // 73
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[43] = 0x00000040, // 64
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[44] = 0x00000041, // 65
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[45] = 0x00000050, // 80
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[46] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[47] = 0x0000004c, // 76
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[48] = 0x0000003a, // 58
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[49] = 0x00000060, // 96
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[50] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[51] = 0x00000055, // 85
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[52] = 0x00000039, // 57
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[53] = 0x00000047, // 71
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[54] = 0x0000005b, // 91
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[55] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[56] = 0x00000053, // 83
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[57] = 0x00000043, // 67
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[58] = 0x00000052, // 82
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[59] = 0x00000043, // 67
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[60] = 0x00000051, // 81
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[61] = 0x00000037, // 55
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[62] = 0x0000004a, // 74
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[63] = 0x00000053, // 83
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[64] = 0x00000037, // 55
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[65] = 0x0000004c, // 76
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[66] = 0x0000003e, // 62
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[67] = 0x00000057, // 87
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[68] = 0x0000003e, // 62
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[69] = 0x0000004a, // 74
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[70] = 0x00000040, // 64
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[71] = 0x00000046, // 70
+#endif
+ //total 72
+ .cfg_ddr_training_delay_ps.soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 48, 40, 48,
+ 40, 48, 40, 48
+ }, //total 44
+ .cfg_ddr_training_delay_ps.dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ //.cfg_ddr_training_delay_ps.reserve_training_parameter = { 0x80+10, 0x80+10,0x80+10,0x80+10,0x80+10,0x80+10,0x80+10,0x80+10,0x80+10, 0x80+10,0x80+10,0x80+10,0x80+10,0x80+10,0x80+10,0x80+10},
+ .cfg_ddr_training_delay_ps.reserve_training_parameter = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0x80 + 10, 0, 0x80 + 5 },
+
+ },
+#endif
+#ifdef S4_DDR4_1RANK
+ {
+ //timing_config,4layer 2pcs ddr4 rank0, ap229.
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[0]) / sizeof(ddr_set_ps0_only_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_ps0_only_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0, 0, (1 << 3) | (4) },
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_2048MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting.pll_ssc_mode = (1 << 20) | (1 << 8) | (2 << 4) | 0, //center_ssc_1000ppm,//SSC_DISABLE,(1 << 20) | (0 << 8) | (2 << 4) | 0,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ //af419 ac pinmux
+#if 0
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3, 27, 12,
+ 21, 9, 8, 0, 14, 10, 6, 7,
+ 20, 5, 22, 13, 15, 2, 0, 0,
+ 0, 0, 11, 26, 4, 0, 0, 25,
+ 3, 1,
+ },
+#endif
+ //s4 ddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 27, 10, 25, 5, 28, 11,24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ .cfg_board_SI_setting_ps.DRAMFreq = 1320,
+ .cfg_board_SI_setting_ps.PllBypassEn = 0,
+ .cfg_board_SI_setting_ps.training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps.ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps.clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps.dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps.dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps.dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps.dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps.dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps.dfe_offset = 0,
+ .cfg_board_SI_setting_ps.vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps.vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps.vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps.max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps.training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps.ac_trace_delay_org =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 128,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+ .cfg_ddr_training_delay_ps.ac_trace_delay =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ },
+
+#if 1
+ .cfg_ddr_training_delay_ps.write_dqs_delay[0] = 0x00000131, // 305
+ .cfg_ddr_training_delay_ps.write_dqs_delay[1] = 0x00000127, // 295
+ .cfg_ddr_training_delay_ps.write_dqs_delay[2] = 0x00000136, // 310
+ .cfg_ddr_training_delay_ps.write_dqs_delay[3] = 0x00000127, // 295
+ .cfg_ddr_training_delay_ps.write_dqs_delay[4] = 0x00000102, // 258
+ .cfg_ddr_training_delay_ps.write_dqs_delay[5] = 0x00000102, // 258
+ .cfg_ddr_training_delay_ps.write_dqs_delay[6] = 0x00000102, // 258
+ .cfg_ddr_training_delay_ps.write_dqs_delay[7] = 0x00000102, // 258
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[0] = 0x0000017a, // 378
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[1] = 0x00000164, // 356
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[2] = 0x0000017d, // 381
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[3] = 0x00000174, // 372
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[4] = 0x00000176, // 374
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[5] = 0x00000160, // 352
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[6] = 0x0000017c, // 380
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[7] = 0x0000017a, // 378
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[8] = 0x0000016e, // 366
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[9] = 0x00000175, // 373
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[10] = 0x00000143, // 323
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[11] = 0x0000015c, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[12] = 0x0000015e, // 350
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[13] = 0x0000017b, // 379
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[14] = 0x0000015c, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[15] = 0x00000172, // 370
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[16] = 0x0000015c, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[17] = 0x0000015e, // 350
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[18] = 0x00000178, // 376
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[19] = 0x0000014f, // 335
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[20] = 0x00000165, // 357
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[21] = 0x00000160, // 352
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[22] = 0x00000175, // 373
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[23] = 0x00000168, // 360
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[24] = 0x0000015e, // 350
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[25] = 0x00000173, // 371
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[26] = 0x00000164, // 356
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[27] = 0x00000178, // 376
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[28] = 0x0000015c, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[29] = 0x0000015f, // 351
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[30] = 0x00000153, // 339
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[31] = 0x00000170, // 368
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[32] = 0x0000015a, // 346
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[33] = 0x0000015d, // 349
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[34] = 0x00000153, // 339
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[35] = 0x00000164, // 356
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[36] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[37] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[38] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[39] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[40] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[41] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[42] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[43] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[44] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[45] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[46] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[47] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[48] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[49] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[50] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[51] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[52] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[53] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[54] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[55] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[56] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[57] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[58] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[59] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[60] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[61] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[62] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[63] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[64] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[65] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[66] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[67] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[68] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[69] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[70] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[71] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[0] = 0x00000421, // 1057
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[1] = 0x00000420, // 1056
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[2] = 0x0000041a, // 1050
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[3] = 0x0000041a, // 1050
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[4] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[5] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[6] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[7] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_delay[0] = 0x00000085, // 133
+ .cfg_ddr_training_delay_ps.read_dqs_delay[1] = 0x00000093, // 147
+ .cfg_ddr_training_delay_ps.read_dqs_delay[2] = 0x00000099, // 153
+ .cfg_ddr_training_delay_ps.read_dqs_delay[3] = 0x0000008a, // 138
+ .cfg_ddr_training_delay_ps.read_dqs_delay[4] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_delay[5] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_delay[6] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_delay[7] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[0] = 0x00000054, // 84
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[1] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[2] = 0x0000004d, // 77
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[3] = 0x00000048, // 72
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[4] = 0x0000004f, // 79
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[5] = 0x00000030, // 48
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[6] = 0x00000057, // 87
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[7] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[8] = 0x00000048, // 72
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[9] = 0x00000066, // 102
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[10] = 0x00000039, // 57
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[11] = 0x00000052, // 82
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[12] = 0x00000042, // 66
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[13] = 0x00000067, // 103
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[14] = 0x0000004d, // 77
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[15] = 0x0000005f, // 95
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[16] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[17] = 0x00000051, // 81
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[18] = 0x00000057, // 87
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[19] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[20] = 0x00000052, // 82
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[21] = 0x00000045, // 69
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[22] = 0x0000006c, // 108
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[23] = 0x00000060, // 96
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[24] = 0x0000004f, // 79
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[25] = 0x0000006a, // 106
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[26] = 0x00000055, // 85
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[27] = 0x00000060, // 96
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[28] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[29] = 0x00000041, // 65
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[30] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[31] = 0x00000069, // 105
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[32] = 0x00000033, // 51
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[33] = 0x0000003f, // 63
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[34] = 0x00000033, // 51
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[35] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[36] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[37] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[38] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[39] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[40] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[41] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[42] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[43] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[44] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[45] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[46] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[47] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[48] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[49] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[50] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[51] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[52] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[53] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[54] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[55] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[56] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[57] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[58] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[59] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[60] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[61] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[62] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[63] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[64] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[65] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[66] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[67] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[68] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[69] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[70] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[71] = 0x00000000, // 0
+#endif
+ //total 72
+ .cfg_ddr_training_delay_ps.soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 48, 40, 48,
+ 40, 48, 40, 48
+ }, //total 44
+ .cfg_ddr_training_delay_ps.dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps.reserve_training_parameter = { 0 },
+ },
+#endif
+#if 0
+ {
+ //timing_config,4layer 2pcs ddr4 rank0, ap229.
+ .cfg_board_common_setting.timming_magic = 0,
+ .cfg_board_common_setting.timming_max_valid_configs = sizeof(__ddr_setting[1]) / sizeof(ddr_set_ps0_only_t),
+ .cfg_board_common_setting.timming_struct_version = 0,
+ .cfg_board_common_setting.timming_struct_org_size = sizeof(ddr_set_ps0_only_t),
+ .cfg_board_common_setting.timming_struct_real_size = 0, //0
+ .cfg_board_common_setting.fast_boot = { 0, 0, (1 << 3) | (4) },
+ .cfg_board_common_setting.ddr_func = 0,
+ .cfg_board_common_setting.board_id = CONFIG_BOARD_ID_MASK,
+ .cfg_board_common_setting.DramType = CONFIG_DDR_TYPE_DDR4,
+ .cfg_board_common_setting.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .cfg_board_common_setting.DisabledDbyte = CONFIG_DISABLE_D32_D63,
+ .cfg_board_common_setting.dram_cs0_base_add = 0,
+ .cfg_board_common_setting.dram_cs1_base_add = 0,
+ .cfg_board_common_setting.dram_cs0_size_MB = CONFIG_DDR0_SIZE_2048MB,
+ .cfg_board_common_setting.dram_cs1_size_MB = CONFIG_DDR1_SIZE_0MB,
+ .cfg_board_common_setting.dram_x4x8x16_mode = CONFIG_DRAM_MODE_X16,
+ .cfg_board_common_setting.Is2Ttiming = CONFIG_USE_DDR_2T_MODE,
+ .cfg_board_common_setting.log_level = LOG_LEVEL_BASIC,
+ .cfg_board_common_setting.ddr_rdbi_wr_enable = DDR_WRITE_READ_DBI_DISABLE,
+ .cfg_board_common_setting.pll_ssc_mode = (1 << 20) | (1 << 8) | (2 << 4) | 0, //center_ssc_1000ppm,//SSC_DISABLE,(1 << 20) | (0 << 8) | (2 << 4) | 0,
+ .cfg_board_common_setting.org_tdqs2dq = 0,
+ .cfg_board_common_setting.reserve1_test_function = { 0 },
+ .cfg_board_common_setting.ddr_dmc_remap = DDR_DMC_REMAP_DDR4_32BIT,
+ //af419 ac pinmux
+#if 0
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3, 27, 12,
+ 21, 9, 8, 0, 14, 10, 6, 7,
+ 20, 5, 22, 13, 15, 2, 0, 0,
+ 0, 0, 11, 26, 4, 0, 0, 25,
+ 3, 1,
+ },
+#endif
+ //s4 ddr4 ac pinmux
+ .cfg_board_common_setting.ac_pinmux =
+ {
+ 0, 0, 0, 1, 2, 3,
+ 27, 10, 25, 5, 28, 11,24, 0, 26, 7, 4, 21, 2, 20, 8, 13, 0, 0, 0, 0, 6, 12, 3, 0, 0, 9, 1, 23, 0
+ },
+ .cfg_board_common_setting.ddr_dqs_swap = 0,
+ .cfg_board_common_setting.ddr_dq_remap =
+ {
+ 0, 1, 2, 3, 4, 5, 6, 7,
+ 8, 9, 10, 11, 12, 13, 14, 15,
+ 16, 17, 18, 19, 20, 21, 22, 23,
+ 24, 25, 26, 27, 28, 29, 30, 31,
+ 32, 33, 34, 35
+ }, //d0-d31 dm0 dm1 dm2 dm3
+ .cfg_board_common_setting.ddr_vddee_setting = { 0 },
+ .cfg_board_SI_setting_ps.DRAMFreq = 1320,
+ .cfg_board_SI_setting_ps.PllBypassEn = 0,
+ .cfg_board_SI_setting_ps.training_SequenceCtrl = 0,
+ .cfg_board_SI_setting_ps.ddr_odt_config = DDR_DRAM_ODT_W_CS0_ODT0,
+ .cfg_board_SI_setting_ps.clk_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.cs_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.ac_drv_ohm = DDR_SOC_AC_DRV_40_OHM,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_p = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.soc_data_drv_ohm_n = DDR_SOC_DATA_DRV_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_p = DDR_SOC_DATA_DRV_ODT_60_OHM,
+ .cfg_board_SI_setting_ps.soc_data_odt_ohm_n = DDR_SOC_DATA_DRV_ODT_0_OHM,
+ .cfg_board_SI_setting_ps.dram_data_drv_ohm = DDR_DRAM_DDR4_DRV_34_OHM,
+ .cfg_board_SI_setting_ps.dram_data_odt_ohm = DDR_DRAM_DDR4_ODT_60_OHM,
+ .cfg_board_SI_setting_ps.dram_data_wr_odt_ohm = DDR_DRAM_DDR_WR_ODT_0_OHM,
+ .cfg_board_SI_setting_ps.dram_ac_odt_ohm = DDR_DRAM_DDR_AC_ODT_0_OHM,
+ .cfg_board_SI_setting_ps.dram_data_drv_pull_up_calibration_ohm = DDR_DRAM_LPDDR4_ODT_40_OHM,
+ .cfg_board_SI_setting_ps.lpddr4_dram_vout_voltage_range_setting = DDR_DRAM_LPDDR4_OUTPUT_1_3_VDDQ,
+ .cfg_board_SI_setting_ps.dfe_offset = 0,
+ .cfg_board_SI_setting_ps.vref_ac_permil = 0,
+ .cfg_board_SI_setting_ps.vref_soc_data_permil = 0,
+ .cfg_board_SI_setting_ps.vref_dram_data_permil = 0,
+ .cfg_board_SI_setting_ps.max_core_timmming_frequency = 0,
+ .cfg_board_SI_setting_ps.training_phase_parameter = { 0 },
+ .cfg_board_SI_setting_ps.ac_trace_delay_org =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 128,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ }, //total 36
+ .cfg_ddr_training_delay_ps.ac_trace_delay =
+ {
+ 128, 128, 128 - 40, 128, 128, 128, 128, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384, 384, 384, 384, 384,
+ 384, 384, 384, 384,
+ },
+
+#if 1
+ .cfg_ddr_training_delay_ps.write_dqs_delay[0] = 0x00000131, // 305
+ .cfg_ddr_training_delay_ps.write_dqs_delay[1] = 0x00000127, // 295
+ .cfg_ddr_training_delay_ps.write_dqs_delay[2] = 0x00000136, // 310
+ .cfg_ddr_training_delay_ps.write_dqs_delay[3] = 0x00000127, // 295
+ .cfg_ddr_training_delay_ps.write_dqs_delay[4] = 0x00000102, // 258
+ .cfg_ddr_training_delay_ps.write_dqs_delay[5] = 0x00000102, // 258
+ .cfg_ddr_training_delay_ps.write_dqs_delay[6] = 0x00000102, // 258
+ .cfg_ddr_training_delay_ps.write_dqs_delay[7] = 0x00000102, // 258
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[0] = 0x0000017a, // 378
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[1] = 0x00000164, // 356
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[2] = 0x0000017d, // 381
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[3] = 0x00000174, // 372
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[4] = 0x00000176, // 374
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[5] = 0x00000160, // 352
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[6] = 0x0000017c, // 380
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[7] = 0x0000017a, // 378
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[8] = 0x0000016e, // 366
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[9] = 0x00000175, // 373
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[10] = 0x00000143, // 323
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[11] = 0x0000015c, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[12] = 0x0000015e, // 350
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[13] = 0x0000017b, // 379
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[14] = 0x0000015c, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[15] = 0x00000172, // 370
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[16] = 0x0000015c, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[17] = 0x0000015e, // 350
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[18] = 0x00000178, // 376
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[19] = 0x0000014f, // 335
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[20] = 0x00000165, // 357
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[21] = 0x00000160, // 352
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[22] = 0x00000175, // 373
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[23] = 0x00000168, // 360
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[24] = 0x0000015e, // 350
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[25] = 0x00000173, // 371
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[26] = 0x00000164, // 356
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[27] = 0x00000178, // 376
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[28] = 0x0000015c, // 348
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[29] = 0x0000015f, // 351
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[30] = 0x00000153, // 339
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[31] = 0x00000170, // 368
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[32] = 0x0000015a, // 346
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[33] = 0x0000015d, // 349
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[34] = 0x00000153, // 339
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[35] = 0x00000164, // 356
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[36] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[37] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[38] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[39] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[40] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[41] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[42] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[43] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[44] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[45] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[46] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[47] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[48] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[49] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[50] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[51] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[52] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[53] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[54] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[55] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[56] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[57] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[58] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[59] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[60] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[61] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[62] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[63] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[64] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[65] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[66] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[67] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[68] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[69] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[70] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.write_dq_bit_delay[71] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[0] = 0x00000421, // 1057
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[1] = 0x00000420, // 1056
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[2] = 0x0000041a, // 1050
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[3] = 0x0000041a, // 1050
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[4] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[5] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[6] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_gate_delay[7] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_delay[0] = 0x00000085, // 133
+ .cfg_ddr_training_delay_ps.read_dqs_delay[1] = 0x00000093, // 147
+ .cfg_ddr_training_delay_ps.read_dqs_delay[2] = 0x00000099, // 153
+ .cfg_ddr_training_delay_ps.read_dqs_delay[3] = 0x0000008a, // 138
+ .cfg_ddr_training_delay_ps.read_dqs_delay[4] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_delay[5] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_delay[6] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dqs_delay[7] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[0] = 0x00000054, // 84
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[1] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[2] = 0x0000004d, // 77
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[3] = 0x00000048, // 72
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[4] = 0x0000004f, // 79
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[5] = 0x00000030, // 48
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[6] = 0x00000057, // 87
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[7] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[8] = 0x00000048, // 72
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[9] = 0x00000066, // 102
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[10] = 0x00000039, // 57
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[11] = 0x00000052, // 82
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[12] = 0x00000042, // 66
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[13] = 0x00000067, // 103
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[14] = 0x0000004d, // 77
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[15] = 0x0000005f, // 95
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[16] = 0x00000046, // 70
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[17] = 0x00000051, // 81
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[18] = 0x00000057, // 87
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[19] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[20] = 0x00000052, // 82
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[21] = 0x00000045, // 69
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[22] = 0x0000006c, // 108
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[23] = 0x00000060, // 96
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[24] = 0x0000004f, // 79
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[25] = 0x0000006a, // 106
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[26] = 0x00000055, // 85
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[27] = 0x00000060, // 96
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[28] = 0x0000003c, // 60
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[29] = 0x00000041, // 65
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[30] = 0x00000035, // 53
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[31] = 0x00000069, // 105
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[32] = 0x00000033, // 51
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[33] = 0x0000003f, // 63
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[34] = 0x00000033, // 51
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[35] = 0x00000044, // 68
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[36] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[37] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[38] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[39] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[40] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[41] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[42] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[43] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[44] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[45] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[46] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[47] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[48] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[49] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[50] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[51] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[52] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[53] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[54] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[55] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[56] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[57] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[58] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[59] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[60] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[61] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[62] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[63] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[64] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[65] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[66] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[67] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[68] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[69] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[70] = 0x00000000, // 0
+ .cfg_ddr_training_delay_ps.read_dq_bit_delay[71] = 0x00000000, // 0
+#endif
+ //total 72
+ .cfg_ddr_training_delay_ps.soc_bit_vref =
+ {
+ 0, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 40, 40, 40,
+ 40, 40, 40, 40, 40, 48, 40, 48,
+ 40, 48, 40, 48
+ }, //total 44
+ .cfg_ddr_training_delay_ps.dram_bit_vref =
+ {
+ 0, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32, 32, 32, 32, 32,
+ 32, 32, 32, 32
+ }, //total 36
+ .cfg_ddr_training_delay_ps.reserve_training_parameter = { 0 },
+ },
+#endif
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_DDR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .low_console_baud = CONFIG_LOW_CONSOLE_BAUD,
+};
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+#define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+#define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+#define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+#define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+#define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+#define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+#define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+#define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+#define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+#define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+#define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+#define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+#define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+#define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+#define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+#define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+#define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+#define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+#define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+#define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+#define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+#define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+#define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+#define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+#define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+#define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+#define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+#define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+#define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+#define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+#define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+#define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+#define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+#define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+#define VCCK_VAL_REG 0x00220000
+#else
+#error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 700)
+#define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 710)
+#define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 720)
+#define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 730)
+#define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 740)
+#define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 750)
+#define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 760)
+#define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 770)
+#define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 780)
+#define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 790)
+#define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 800)
+#define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 810)
+#define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 820)
+#define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 830)
+#define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 840)
+#define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 850)
+#define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 860)
+#define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 870)
+#define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 880)
+#define VDDEE_VAL_REG 0x12
+#else
+#error "VDDEE val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ { 0, 0, 0xffffffff, 0, 0, 0 },
+};
+
+/* gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+#if 0
+ /* config vddee and vcck pwm - pwm_h and pwm_j*/
+ { PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0 },
+ { PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0 },
+ /* set pwm h and pwm j clock rate to 24M, enable them */
+ { CLKCTRL_PWM_CLK_GH_CTRL, (1 << 24), 0xffffffff, 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 24), 0xffffffff, 0, 0, 0 },
+ /* set GPIOE_0 GPIOE_1 drive strength to 3 */
+ { PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0 },
+ /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
+ { PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0 },
+ { PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0 },
+#else
+ /*enable y_led (gpioao_4)*/
+ { PWMAB_PWM_B, YELLOW_LED_VAL, 0xffffffff, 0, 0, 0 },
+ { PWMAB_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AB_CTRL, (0x1 << 24), (0x1 << 24), 0, 0, 0 },
+ { PADCTRL_PIN_MUX_REGG, (3 << 16), (0xf << 16), 0, 0, 0 },
+ /* enable vddcpu dc-dc, set TEST_N to high */
+ { PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
+ { PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0 },
+ /* GPIO pull enable */
+ { PADCTRL_GPIOX_PULL_EN, (0x0 << 8), (0xff << 8), 0, BL2_INIT_STAGE_1, 0 }, /* Disable GPIOX_8 ~ GPIOX_15 */
+ /* GPIO direction */
+ { PADCTRL_GPIOX_OEN, (0x0 << 6), (0x1 << 6), 0, BL2_INIT_STAGE_1, 0 }, /* GPIOX_6: Out */
+ /* GPIO output */
+ { PADCTRL_GPIOX_O, (0x1 << 6), (0x1 << 6), 0, BL2_INIT_STAGE_1, 0 }, /* GPIOX_6: High */
+ /* GPIO pinmux */
+ { PADCTRL_PIN_MUX_REG3, (0x0 << 24), (0xf << 24), 0, BL2_INIT_STAGE_1, 0 }, /* GPIOX_6 [27:24] */
+#endif
+};
+
+#define DEV_FIP_SIZE 0x300000
+#define DDR_FIP_SIZE 0x40000
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common ={
+ .version = 0x01,
+ .device_fip_container_size = DEV_FIP_SIZE,
+ .device_fip_container_copies = 4,
+ .ddr_fip_container_size = DDR_FIP_SIZE,
+ },
+ .nand ={
+ .version = 0x01,
+ .bbt_pages = 0x1,
+ .bbt_start_block = 20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (1 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 64,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/s4_t211/fw_arb.cfg b/board/amlogic/s4_t211/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/s4_t211/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/s4_t211/partition_table.h b/board/amlogic/s4_t211/partition_table.h
new file mode 100644
index 0000000..ba1259c
--- /dev/null
+++ b/board/amlogic/s4_t211/partition_table.h
@@ -0,0 +1,123 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Google LLC
+ */
+
+#ifndef _BOARD_AMLOGIC_S4_T211_PARTITION_TABLE_H_
+#define _BOARD_AMLOGIC_S4_T211_PARTITION_TABLE_H_
+
+#include <chromecast/partition.h>
+#include <linux/sizes.h>
+
+#define CHROMECAST_BOOTLOADER_SIZE (3 * SZ_1M + 512 * SZ_1K)
+
+// go/boreal-partition
+const chromecast_partition_table_t boreal_partition_table = {
+ .align = SZ_1M,
+ .reserved = SZ_1M, // reserved space for second GPT
+ .partitions = {
+ {
+ .name = "reserved",
+ .start = 36 * SZ_1M,
+ .size = 64 * SZ_1M,
+ },
+ {
+ .name = "env",
+ .size = 8 * SZ_1M,
+ .migrate_op = CHROMECAST_PARTITION_MIGRATE_OP_ERASE,
+ },
+ {
+ .name = "frp",
+ .size = 1 * SZ_1M,
+ .migrate_op = CHROMECAST_PARTITION_MIGRATE_OP_ERASE,
+ },
+ {
+ .name = "misc",
+ .size = 1 * SZ_1M,
+ .migrate_op = CHROMECAST_PARTITION_MIGRATE_OP_ERASE,
+ },
+ {
+ .name = "tee",
+ .size = 16 * SZ_1M,
+ .migrate_op = CHROMECAST_PARTITION_MIGRATE_OP_ERASE,
+ },
+ {
+ .name = "cri_data",
+ .size = 8 * SZ_1M,
+ .migrate_op = CHROMECAST_PARTITION_MIGRATE_OP_ERASE,
+ },
+ {
+ .name = "param",
+ .size = 8 * SZ_1M,
+ .migrate_op = CHROMECAST_PARTITION_MIGRATE_OP_ERASE,
+ },
+ {
+ .name = "factory",
+ .size = 8 * SZ_1M,
+ },
+ {
+ .name = "bootloader_a",
+ .size = CHROMECAST_BOOTLOADER_SIZE,
+ },
+ {
+ .name = "bootloader_b",
+ .size = CHROMECAST_BOOTLOADER_SIZE,
+ },
+ {
+ .name = "boot_a",
+ .size = 64 * SZ_1M,
+ },
+ {
+ .name = "boot_b",
+ .size = 64 * SZ_1M,
+ },
+ {
+ .name = "vendor_boot_a",
+ .size = 64 * SZ_1M,
+ },
+ {
+ .name = "vendor_boot_b",
+ .size = 64 * SZ_1M,
+ },
+ {
+ .name = "dtbo_a",
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "dtbo_b",
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "metadata",
+ .size = 16 * SZ_1M,
+ .migrate_op = CHROMECAST_PARTITION_MIGRATE_OP_ERASE,
+ },
+ {
+ .name = "vbmeta_a",
+ .size = 1 * SZ_1M,
+ },
+ {
+ .name = "vbmeta_b",
+ .size = 1 * SZ_1M,
+ },
+ {
+ .name = "vbmeta_system_a",
+ .size = 1 * SZ_1M,
+ },
+ {
+ .name = "vbmeta_system_b",
+ .size = 1 * SZ_1M,
+ },
+ {
+ .name = "super",
+ .size = 2560ULL * SZ_1M,
+ },
+ {
+ .name = "userdata",
+ .size = 0, // use the rest of the spaces
+ .migrate_op = CHROMECAST_PARTITION_MIGRATE_OP_ERASE,
+ },
+ },
+};
+
+#endif // _BOARD_AMLOGIC_S4_T211_PARTITION_TABLE_H_
diff --git a/board/amlogic/s4_t211/res/images/README.txt b/board/amlogic/s4_t211/res/images/README.txt
new file mode 100644
index 0000000..994ee39
--- /dev/null
+++ b/board/amlogic/s4_t211/res/images/README.txt
@@ -0,0 +1,5 @@
+1. Convert an image to logo BMP.
+ $ convert <image> -define bmp:subtype=RGB565 logo.bmp
+
+2. Compress it.
+ $ gzip logo.bmp
diff --git a/board/amlogic/s4_t211/res/images/logo.bmp.gz b/board/amlogic/s4_t211/res/images/logo.bmp.gz
new file mode 100644
index 0000000..f19598e
--- /dev/null
+++ b/board/amlogic/s4_t211/res/images/logo.bmp.gz
Binary files differ
diff --git a/board/amlogic/s4_t211/s4_t211.c b/board/amlogic/s4_t211/s4_t211.c
new file mode 100644
index 0000000..3e89874
--- /dev/null
+++ b/board/amlogic/s4_t211/s4_t211.c
@@ -0,0 +1,348 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <blk.h>
+#include <board_variant.h>
+#include <chromecast/partition.h>
+#include <chromecast/factory.h>
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <emmc_partitions.h>
+#include <environment.h>
+#include <stdio.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <amlogic/aml_efuse.h>
+#include <amlogic/storage.h>
+#include <asm/arch/bl31_apis.h>
+#include <asm/gpio.h>
+
+#include "partition_table.h"
+
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
+#endif
+#ifdef CONFIG_AML_CVBS
+#include <amlogic/media/vout/aml_cvbs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+extern unsigned char res_images_logo_bmp_gz[];
+extern unsigned int res_images_logo_bmp_gz_len;
+
+#define BOOT_INDEX_EMMC_USER 0x10
+#define BOOT_INDEX_EMMC_BOOT0 0x11
+#define BOOT_INDEX_EMMC_BOOT1 0x12
+#define BOOT_INDEX_USB 0x50
+#define GPIOZ_4 "GPIOZ_4"
+#define GPIOZ_6 "GPIOZ_6"
+#define GPIOZ_7 "GPIOZ_7"
+
+static int get_boot_index(void)
+{
+ return readl(SYSCTRL_SEC_STATUS_REG2) & 0xff;
+}
+
+int get_board_variant(void)
+{
+#ifdef CONFIG_DEBUG_BOARD_VARIANT_PROD
+ return BOARD_VARIANT_PROD;
+#else
+ static int board_variant = BOARD_VARIANT_UNKNOWN;
+
+ if (board_variant == BOARD_VARIANT_UNKNOWN) {
+ if (IS_FEAT_DIS_NORMAL_DEVICE_ROOTCERT_0() == 0 &&
+ IS_FEAT_DIS_DFU_DEVICE_ROOTCERT_0() == 0)
+ board_variant = BOARD_VARIANT_DEV;
+ else
+ board_variant = BOARD_VARIANT_PROD;
+ }
+
+ return board_variant;
+#endif
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+ run_command("gpio set GPIOH_7", 0);
+}
+#endif
+
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+ aml_set_bootsequence(0);
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+ return 0;
+}
+
+int read_gpio(const char *str_gpio)
+{
+ unsigned int gpio;
+ int ret;
+ ret = gpio_lookup_name(str_gpio, NULL, NULL, &gpio);
+ if (ret) {
+ printf("GPIO: '%s' not found\n", str_gpio);
+ return -1;
+ }
+ /* grab the pin before we tweak it */
+ ret = gpio_request(gpio, "cmd_gpio");
+ if (ret && ret != -EBUSY) {
+ printf("gpio: requesting pin %u failed\n", gpio);
+ return -1;
+ }
+ gpio_direction_input(gpio);
+ int value = gpio_get_value(gpio);
+ gpio_free(gpio);
+ return value;
+}
+
+void env_set_board_id(void)
+{
+ // See go/boreal-pinmux.
+ int hw_id[] = {read_gpio(GPIOZ_6), read_gpio(GPIOZ_7), read_gpio(GPIOZ_4)};
+ int hw_id_length = (int) (sizeof(hw_id) / sizeof(hw_id[0]));
+ int board_id = 0;
+
+ for (int i = 0; i < hw_id_length; i++)
+ {
+ if (hw_id[i] < 0) {
+ printf("Failed to read board id from hw_id[%d]\n", i);
+ return;
+ }
+ board_id += (hw_id[i] << i);
+ }
+
+ printf("Store board id: %d\n", board_id);
+ env_set_ulong("board_id", board_id);
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ char *env_fstab_suffix;
+ env_fstab_suffix = env_get("fstab_suffix");
+ if (!env_fstab_suffix) {
+ env_set("fstab_suffix", "ext4");
+ }
+
+ run_command("defenv_reserv", 0);
+
+ void *bootloader_buf = NULL;
+ int boot_idx = get_boot_index();
+
+ printf("%s: boot_idx: %#x\n", __func__, boot_idx);
+
+ if (boot_idx == BOOT_INDEX_EMMC_USER) {
+ // Migrate from AML partition table to GPT
+ // The boot address in the user partition will be occupied by GPT
+ bootloader_buf = malloc(CHROMECAST_BOOTLOADER_SIZE);
+ if (!bootloader_buf) {
+ printf("%s: unable to allocate memory for bootloader_buf\n",
+ __func__);
+ } else {
+ printf("%s: copy bootloader to boot0 and boot1\n",
+ __func__);
+ store_boot_read("bootloader", 0,
+ CHROMECAST_BOOTLOADER_SIZE,
+ bootloader_buf);
+ store_boot_write("bootloader", 1,
+ CHROMECAST_BOOTLOADER_SIZE,
+ bootloader_buf);
+ store_boot_write("bootloader", 2,
+ CHROMECAST_BOOTLOADER_SIZE,
+ bootloader_buf);
+ }
+ }
+
+ struct blk_desc *dev_desc = NULL;
+ dev_desc = blk_get_dev("mmc", 1);
+ if (dev_desc) {
+ init_chromecast_partitions(dev_desc, &boreal_partition_table);
+ load_chromecast_factory_configs(dev_desc);
+ } else {
+ printf("%s: failed to get mmc 1\n", __func__);
+ }
+
+ // reinit aml mmc partitions
+ mmc_device_init(find_mmc_device(1));
+
+ if (bootloader_buf) {
+ printf("%s: copy bootloader to bootloader_a/b\n", __func__);
+ store_write("bootloader_a", 0,
+ CHROMECAST_BOOTLOADER_SIZE, bootloader_buf);
+ store_write("bootloader_b", 0,
+ CHROMECAST_BOOTLOADER_SIZE, bootloader_buf);
+ free(bootloader_buf);
+ }
+
+ env_set_board_id();
+
+ // The env partition could be changed, save the env.
+ env_save();
+
+ env_set_hex("logo_addr", (ulong) res_images_logo_bmp_gz);
+
+ if (get_board_variant() != BOARD_VARIANT_DEV) {
+ // set bootdelay to -2 to not check for abort
+ env_set("bootdelay", "-2");
+ env_set("consoleargs", "console=ttynull");
+ env_set("board_variant", "prod");
+ } else {
+ // autoboot with no delay but can be stopped by key input
+ env_set("bootdelay", "0");
+ env_set("consoleargs", "console=ttyS0,921600 no_console_suspend earlycon=aml-uart,0xfe07a000");
+ env_set("board_variant", "dev");
+ }
+
+ if (boot_idx == BOOT_INDEX_USB) {
+ run_command("fastboot 0", 0);
+ }
+
+ board_init_mem();
+ run_command("run bcb_cmd", 0);
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ cvbs_init();
+#endif
+ run_command("amlsecurecheck", 0);
+ run_command("update_tries", 0);
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ (((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) - CONFIG_SYS_MEM_TOP_HIDE);
+#else
+ return ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf1000000UL,
+ .phys = 0xf1000000UL,
+ .size = 0x0f000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ /* update mmu table from bl2 ddr auto detect size */
+#ifdef CONFIG_UPDATE_MMU_TABLE
+ unsigned long nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4) > 0xf1000000 ? 0xf1000000 : \
+ ((readl(SYSCTRL_SEC_STATUS_REG4) & 0xFFF80000) << 4);
+ bd_mem_map[0].size = nddrSize;
+#endif
+
+ //printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+const char * const _env_args_reserve_[] =
+{
+ "lock",
+ "fstab_suffix",
+ "bootloader_version",
+ "hdr_policy",
+ "hdr_priority",
+ "hdmichecksum",
+ "hdmimode",
+ "outputmode",
+ "colorattribute",
+ "hdmi_colorspace",
+ "hdmi_colordepth",
+ "1080p60hz_deepcolor",
+ "1080p50hz_deepcolor",
+ "1080p30hz_deepcolor",
+ "1080p25hz_deepcolor",
+ "1080p24hz_deepcolor",
+ "720p60hz_deepcolor",
+ "720p50hz_deepcolor",
+ "1080i60hz_deepcolor",
+ "1080i50hz_deepcolor",
+ "576p50hz_deepcolor",
+ "480p60hz_deepcolor",
+ "digitaudiooutput",
+ "is.bestmode",
+ NULL//Keep NULL be last to tell END
+};
diff --git a/board/amlogic/sc2_ah212/Kconfig b/board/amlogic/sc2_ah212/Kconfig
new file mode 100644
index 0000000..ec3b787
--- /dev/null
+++ b/board/amlogic/sc2_ah212/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_SC2_AH212
+
+config SYS_SOC
+ default "sc2"
+
+config SYS_BOARD
+ default "sc2_ah212"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "sc2_ah212"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+endif
diff --git a/board/amlogic/sc2_ah212/Makefile b/board/amlogic/sc2_ah212/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/sc2_ah212/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/sc2_ah212/aml-key/bl2aesiv b/board/amlogic/sc2_ah212/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/sc2_ah212/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/sc2_ah212/aml-key/bl2aeskey b/board/amlogic/sc2_ah212/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/sc2_ah212/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/sc2_ah212/aml-key/bl3xaesiv b/board/amlogic/sc2_ah212/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/sc2_ah212/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/sc2_ah212/aml-key/bl3xaeskey b/board/amlogic/sc2_ah212/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/sc2_ah212/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/sc2_ah212/aml-key/kernelaesiv b/board/amlogic/sc2_ah212/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/sc2_ah212/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/sc2_ah212/aml-key/kernelaeskey b/board/amlogic/sc2_ah212/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/sc2_ah212/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/sc2_ah212/aml-user-key.sig b/board/amlogic/sc2_ah212/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/sc2_ah212/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/sc2_ah212/avb2_kpub.c b/board/amlogic/sc2_ah212/avb2_kpub.c
new file mode 100644
index 0000000..459f49c
--- /dev/null
+++ b/board/amlogic/sc2_ah212/avb2_kpub.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifdef CONFIG_AVB2_KPUB_VENDOR
+const char avb2_kpub_vendor[] = {
+0x00,0x00,0x10,0x00,0x0a,0x4c,0x05,0xb1,0xb3,0x10,0x1c,0xf5,0x89,0x5b,0x97,0x6d,
+0xdd,0x0f,0x1a,0x5d,0x4f,0x3a,0x53,0xba,0xbe,0x2a,0x56,0x9f,0x55,0xb1,0x20,0x0d,
+0x73,0x84,0xc3,0xbf,0xcf,0x7b,0x27,0x0f,0x25,0xd7,0xe1,0x7e,0x94,0x8a,0x0f,0xd3,
+0xe8,0x82,0xf2,0x31,0x2e,0xb2,0x88,0xde,0xda,0x25,0x99,0xae,0xc8,0xa2,0x11,0x4e,
+0x6a,0xd2,0x9c,0x68,0x72,0xc0,0x0b,0xda,0x1a,0xe7,0xe1,0x34,0xc0,0x19,0x74,0xbc,
+0xaa,0x27,0x69,0x52,0x70,0xee,0xca,0xc3,0xee,0x0d,0x6e,0xc0,0x70,0x04,0x9a,0x87,
+0x5b,0x53,0xdb,0xf6,0xfc,0xb0,0xa4,0xe0,0xed,0x16,0x37,0x6a,0xcb,0x4b,0x84,0xd8,
+0x77,0x40,0x7a,0x17,0xd3,0xe0,0x0f,0x46,0x16,0x5f,0x7f,0x6e,0x12,0xad,0xc9,0x00,
+0x66,0xd1,0x25,0x9f,0x94,0xb1,0xf7,0xf4,0xde,0x76,0x1b,0xc0,0xab,0x66,0xe2,0x54,
+0x9b,0x2b,0x2d,0x28,0x07,0x74,0xae,0x1d,0x94,0xe3,0x3d,0x2e,0xbe,0x29,0x2b,0xd3,
+0xcc,0x2d,0x57,0xf2,0x29,0x5c,0x4f,0x30,0x9a,0x80,0x0d,0xfb,0xf9,0xa3,0xf8,0x8b,
+0x05,0xcf,0xc0,0xc3,0x32,0x94,0xb6,0x1a,0x3b,0x31,0x70,0x90,0x52,0x47,0x78,0xb5,
+0x38,0xe4,0xef,0x22,0xe6,0xea,0xb0,0x4e,0xd5,0x25,0xeb,0x7e,0xd0,0x44,0x96,0xfb,
+0x3b,0x5e,0xa3,0x7a,0xa7,0xd2,0xae,0xba,0x56,0x48,0x0b,0xf2,0xfe,0xce,0xd7,0x1d,
+0x42,0x01,0x7c,0x46,0xea,0xfb,0x08,0xdb,0x3b,0x91,0xc7,0xc5,0x41,0xa7,0x39,0x70,
+0x62,0x8a,0x92,0xee,0xcc,0xdb,0x3f,0x66,0x13,0xd1,0xb2,0xb0,0x1b,0x19,0xd7,0xc3,
+0x7c,0x89,0x2a,0x24,0xbd,0xaf,0x6e,0xf9,0xe5,0xc1,0xd5,0x6b,0x2d,0xa1,0x8d,0x40,
+0xd7,0x4b,0x7c,0x49,0xe0,0x02,0x7e,0xa0,0xd7,0x68,0x91,0x40,0xb6,0x29,0x8d,0xd5,
+0x3b,0xc0,0x3a,0x68,0x26,0x75,0x19,0x72,0x1c,0xa0,0xb0,0x7f,0x64,0x77,0x95,0x9b,
+0x46,0x97,0xb2,0xea,0xa0,0x6a,0x60,0x56,0x6b,0xee,0x1e,0xd6,0xd3,0x54,0x8b,0x4e,
+0xc6,0x55,0x13,0xaa,0xba,0x63,0xe9,0xba,0x93,0x2e,0x47,0xea,0x7c,0x37,0x7e,0x75,
+0x19,0x29,0x7b,0x00,0xfa,0xf4,0x63,0xeb,0x66,0xea,0xbf,0x07,0x9a,0x01,0x73,0x03,
+0x70,0xd8,0xc2,0x3f,0xe1,0xc0,0xf0,0x03,0x5b,0xf1,0x95,0xce,0x2c,0xc7,0x42,0xcf,
+0x70,0x5c,0x75,0x37,0x29,0x97,0x15,0x32,0xea,0x95,0xbd,0x57,0x22,0xb8,0xca,0xf3,
+0x35,0xb4,0xb1,0x7b,0x64,0x52,0x43,0x19,0xa8,0x4a,0xe4,0x4a,0xe3,0xed,0x72,0xb1,
+0xb9,0xc4,0x5c,0xb3,0xc8,0x95,0xfe,0xb1,0x74,0xc5,0x53,0x37,0xc5,0xba,0x04,0x08,
+0x06,0x0e,0xdd,0xe7,0x4c,0xff,0xba,0xc4,0x43,0x5c,0xf0,0x90,0x4c,0x06,0xa5,0xf5,
+0xad,0xb5,0x0f,0xf5,0x20,0xd7,0x52,0x3d,0x4a,0x33,0xdf,0x1c,0xa7,0x5b,0x55,0x8c,
+0xc1,0x5c,0xd1,0x71,0xaf,0x19,0xf0,0x7a,0xaf,0x5a,0x86,0xbc,0x90,0xae,0x1c,0x35,
+0xb7,0x41,0x56,0xf7,0xda,0x30,0xbc,0x29,0x32,0xe8,0xaa,0xd8,0xcd,0x1c,0xea,0xc9,
+0xdc,0x72,0x64,0xae,0x9b,0xec,0x29,0x8e,0x69,0x2a,0x7e,0xf0,0x2c,0x22,0xdc,0xbb,
+0x56,0xa3,0xbc,0x49,0x21,0x8b,0xde,0xed,0x37,0x9a,0x4d,0x65,0xef,0x94,0xc5,0xde,
+0xfa,0xe8,0xf1,0x46,0xe8,0x64,0xdc,0xaf,0x6a,0x3f,0x3b,0x46,0xa9,0xcd,0xb0,0x9a,
+0x4a,0x99,0x9c,0x69,0xc9,0x63,0x24,0xd8,0xf4,0x4a,0xcf,0x10,0xde,0x2f,0x87,0xe6,
+0x66,0x57,0x1d,0xb3,0x1f,0xce,0xbe,0x68,0x6f,0x0b,0xce,0x7d,0x5c,0x6a,0x84,0x32,
+0xec,0x23,0x25,0x46,0xbb,0xf2,0x58,0x93,0x93,0x37,0x38,0xd3,0x50,0x41,0x6e,0xb5,
+0x48,0xd2,0xbd,0xce,0xf0,0x45,0xd9,0x59,0xc4,0xfb,0xa4,0x05,0xbf,0x12,0x93,0x79,
+0x19,0xcd,0xe0,0xb5,0x5d,0x3a,0xc8,0x85,0x76,0xe9,0x3c,0x43,0xc4,0xdb,0xf1,0x99,
+0x99,0x27,0x86,0x6d,0xfd,0x64,0x7b,0x19,0x94,0xb3,0xab,0x3c,0x66,0x08,0x9b,0xe2,
+0x74,0xa1,0xf6,0x1e,0xc3,0x07,0xc9,0x78,0xc3,0x11,0x91,0x01,0x0d,0x23,0x8a,0x91,
+0x8e,0x41,0x9f,0x38,0xd0,0x83,0x14,0xef,0x48,0xf4,0x95,0xfe,0x8f,0x7c,0xd8,0xa5,
+0x8f,0x9a,0x49,0xc8,0xbe,0x44,0x8e,0x57,0xcf,0xe0,0x0f,0xdb,0x05,0xa0,0x02,0xed,
+0xf3,0xe1,0x99,0x48,0xbc,0xd5,0xf3,0xae,0xf3,0xd3,0x91,0x79,0x9e,0xd9,0xa8,0x5c,
+0xd1,0x19,0xc3,0x54,0xf6,0x10,0x21,0x4d,0x37,0x91,0x86,0x5a,0x6d,0xcb,0xd5,0x9f,
+0xe2,0x9b,0x3e,0x37,0x1b,0x82,0x97,0x79,0x9e,0x89,0xad,0x13,0xf4,0x9f,0x26,0xa9,
+0xcd,0x79,0x07,0x7c,0x42,0x0e,0x0c,0xee,0x23,0x77,0x70,0x1c,0x01,0x0f,0xa5,0xce,
+0x40,0x81,0x8e,0x56,0x8d,0x6b,0x14,0x4c,0x82,0x2c,0x7e,0x5d,0x31,0x27,0x30,0x1a,
+0x88,0x67,0xf7,0x94,0x9a,0x19,0xd8,0x5f,0x7f,0xed,0xc4,0xba,0xf3,0x2e,0x7f,0xaa,
+0x86,0x31,0x06,0xd1,0x94,0xdc,0x58,0xed,0x27,0xf6,0x53,0x1c,0xea,0xc1,0xb3,0x57,
+0x5d,0x52,0x5c,0x0b,0x9a,0x8f,0x15,0x7a,0x2f,0x7b,0xd7,0xe5,0x39,0xf7,0x29,0xa9,
+0x47,0x99,0xf7,0x0e,0xd4,0x9e,0x58,0x35,0x7f,0x4c,0x6c,0x8d,0xe4,0x1e,0x07,0xb3,
+0xca,0x35,0xca,0x23,0xda,0xa1,0xb9,0x11,0x58,0x75,0x66,0xe0,0x95,0x40,0x93,0xc5,
+0xe5,0x95,0x18,0x06,0xeb,0x3f,0x08,0x3b,0x81,0x11,0x48,0x75,0xda,0xb4,0x1d,0x13,
+0xa5,0xf1,0xf3,0x85,0xd0,0x2d,0x68,0x80,0x11,0x60,0x2b,0x18,0x47,0x16,0x7c,0xe0,
+0x54,0xd6,0xa6,0x05,0x95,0x4a,0xae,0xf5,0xdc,0x41,0x33,0x7b,0x59,0xff,0x4d,0xb2,
+0x5d,0xc5,0x2a,0x4d,0x64,0x21,0xfc,0x98,0xb5,0xf6,0x35,0x25,0x79,0x08,0xed,0x56,
+0x61,0xaf,0x33,0x9f,0x14,0xc8,0x22,0xbe,0xa6,0x8f,0xc9,0xf8,0x4d,0xb1,0xeb,0xcb,
+0x04,0x44,0x89,0x2f,0x7d,0x18,0x58,0x0e,0x0e,0x3a,0x26,0x95,0xe6,0xb0,0x57,0x2d,
+0xd8,0xda,0xfc,0x4f,0xb8,0x46,0x52,0xd0,0xdb,0xc3,0x5f,0x73,0xa1,0xa8,0x13,0xd1,
+0x4f,0xe4,0xf6,0x6d,0x0f,0xe0,0xc5,0x80,0xf6,0xc5,0x74,0xc1,0x2e,0x85,0x47,0x36,
+0x61,0x94,0x2d,0xe5,0xfa,0xf0,0xaf,0x3a,0x99,0x4f,0x24,0xa2,0x27,0x23,0x34,0x9b,
+0xf1,0xb1,0x8b,0x60,0x09,0x28,0x6a,0xb5,0xe2,0x1f,0xa8,0x3d,0x85,0xdb,0x33,0x1a,
+0x61,0x29,0x94,0xb4,0x2a,0xd7,0x88,0x9f,0x80,0x7e,0xbc,0x03,0x4e,0xe0,0xeb,0x0c,
+0x76,0xe3,0xd4,0xc2,0x24,0x94,0x0f,0xe8,0xbd,0x2d,0xf8,0x43,0x9f,0xd4,0x7e,0x9c,
+0x60,0x5f,0x0a,0xa7,0xc2,0x39,0x27,0x77
+};
+
+const int avb2_kpub_vendor_len = sizeof(avb2_kpub_vendor) / sizeof(char);
+#endif /* CONFIG_AVB2_KPUB_VENDOR */
diff --git a/board/amlogic/sc2_ah212/config.mk b/board/amlogic/sc2_ah212/config.mk
new file mode 100644
index 0000000..183bd11
--- /dev/null
+++ b/board/amlogic/sc2_ah212/config.mk
@@ -0,0 +1 @@
+PLATFORM_CPPFLAGS += -DCONFIG_AVB2_KPUB_VENDOR=1
diff --git a/board/amlogic/sc2_ah212/firmware/timing.c b/board/amlogic/sc2_ah212/firmware/timing.c
new file mode 100644
index 0000000..e0478bb
--- /dev/null
+++ b/board/amlogic/sc2_ah212/firmware/timing.c
@@ -0,0 +1,388 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+#define DSU_CLK 1200
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+{
+ // g12a 4layer 2pcs ddr3 rank0
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
+},
+{
+ // g12a 4layer 2pcs ddr4 rank0 (1320)(U200)
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1320, 0, 0, 0},
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {32-10,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
+},
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+ .dsu_clk = DSU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+};
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ {0, 0, 0xffffffff, 0, 0, 0},
+};
+
+/* gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+ /* demo, user defined override register */
+ {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ /* enable vddcpu dc-dc, set TEST_N to high */
+ {PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0},
+ {PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0},
+ /* set pwm h and pwm j clock rate to 24M, enable them */
+ {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0},
+ {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3 */
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0},
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0},
+};
+
+#define DEV_FIP_SIZE 0x300000
+#define DDR_FIP_SIZE 0x40000
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common = {
+ .version = 0x01,
+ .device_fip_container_size = DEV_FIP_SIZE,
+ .device_fip_container_copies = 4,
+ .ddr_fip_container_size = DDR_FIP_SIZE,
+ },
+ .nand = {
+ .version = 0x01,
+ .bbt_pages = 0x01,
+ .bbt_start_block = 20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (1 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 64,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/sc2_ah212/fw_arb.cfg b/board/amlogic/sc2_ah212/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/sc2_ah212/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/sc2_ah212/sc2_ah212.c b/board/amlogic/sc2_ah212/sc2_ah212.c
new file mode 100644
index 0000000..587bb30
--- /dev/null
+++ b/board/amlogic/sc2_ah212/sc2_ah212.c
@@ -0,0 +1,484 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_ext.h>
+#endif
+#ifdef CONFIG_AML_CVBS
+#include <amlogic/media/vout/aml_cvbs.h>
+#endif
+
+#include "avb2_kpub.c"
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+
+static const char ddr_type_info[6][8] =
+{
+ "DDR3\0", //CONFIG_DDR_TYPE_DDR3 //0
+ "DDR4\0", //CONFIG_DDR_TYPE_DDR4 //1
+ "LPDDR4\0", //CONFIG_DDR_TYPE_LPDDR4 //2
+ "LPDDR3\0", //CONFIG_DDR_TYPE_LPDDR3 //3
+ "LPDDR2\0", //CONFIG_DDR_TYPE_LPDDR2 //4
+ "LPDDR4X\0", //CONFIG_DDR_TYPE_LPDDR4X //5
+};
+
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ unsigned int ddr_type;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ env_tmp = env_get("boot_ddr_type");
+ if (!env_tmp) {
+ ddr_type = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0x00070000) >> 16);
+ env_set("boot_ddr_type", 0);
+ env_set("boot_ddr_type", ddr_type_info[ddr_type]);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+ aml_set_bootsequence(0);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ #if 0
+ active_clk();
+ #endif
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ run_command("gpio clr GPIOH_8", 0);
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ //default uboot env need before anyone use it
+ if (env_get("default_env")) {
+ printf("factory reset, need default all uboot env.\n");
+ run_command("defenv_reserv; setenv upgrade_step 2; saveenv;", 0);
+ }
+
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+ run_command("run bcb_cmd", 0);
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ /* reset vout init state */
+ run_command("setenv vout_init disable", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+
+#ifdef CONFIG_AML_CVBS
+ cvbs_init();
+#endif
+ run_command("amlsecurecheck", 0);
+ run_command("update_tries", 0);
+ return 0;
+}
+
+unsigned int get_ddr_memsize(void)
+{
+ unsigned int ddr_size;
+#if 0
+ /*if soc don't support automatic get ddr size,
+ then it get ddr size with software method*/
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+#else
+ /*auto get ddr size from hardware method*/
+ ddr_size = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4;
+#endif
+ return ddr_size;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf1000000UL,
+ .phys = 0xf1000000UL,
+ .size = 0x0f000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ /* update mmu table from bl2 ddr auto detect size */
+#ifdef CONFIG_UPDATE_MMU_TABLE
+ unsigned int nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4;
+ switch (nddrSize)
+ {
+ case (CONFIG_1G_SIZE):
+ case (CONFIG_2G_SIZE):
+ case (CONFIG_3G_SIZE):
+ case (CONFIG_DDR_MAX_SIZE):
+ bd_mem_map[0].size = nddrSize;
+ break;
+ default :
+ printf("aml log : ERROR DDR detect size not match MMU !");
+ break;
+ }
+#endif
+
+ //printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 1 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+
+uint64_t spiflash_bootloader_size(void)
+{
+ return 3 * SZ_1M;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+#ifdef CONFIG_AUTO_ADAPT_DDR_DTB
+ unsigned int ddr_size = 0;
+ char loc_name[64] = {0};
+ char *mem_size = env_get("mem_size");
+
+ ddr_size = get_ddr_memsize();
+
+ printf("%s:%d ddr_size:0x%x\r\n",__func__,__LINE__,ddr_size);
+ switch (ddr_size) {
+ case CONFIG_2G_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah212\0");
+
+ /* if limit memory size */
+ if (mem_size && !strcmp(mem_size, "1g")) {
+ strcpy(loc_name, "sc2_s905x4_ah212-1g\0");
+ }
+ break;
+ case CONFIG_1G_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah212-1g\0");
+ break;
+ case CONFIG_3G_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah212-3g\0");
+ break;
+ case CONFIG_DDR_MAX_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah212-4g\0");
+ break;
+ default:
+ printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size);
+ strcpy(loc_name, "sc2_s905x4_ah212_unsupport\0");
+ break;
+ }
+
+ strcpy(name, loc_name);
+ env_set("aml_dt", loc_name);
+ return 0;
+#else
+ strcpy(name, "sc2_s905x4_ah212\0");
+ env_set("aml_dt", "sc2_s905x4_ah212\0");
+ return 0;
+#endif
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/sc2_ah212_ddr3/Kconfig b/board/amlogic/sc2_ah212_ddr3/Kconfig
new file mode 100644
index 0000000..7d4efc9
--- /dev/null
+++ b/board/amlogic/sc2_ah212_ddr3/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_SC2_AH212_DDR3
+
+config SYS_SOC
+ default "sc2"
+
+config SYS_BOARD
+ default "sc2_ah212_ddr3"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "sc2_ah212_ddr3"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+endif
diff --git a/board/amlogic/sc2_ah212_ddr3/Makefile b/board/amlogic/sc2_ah212_ddr3/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/sc2_ah212_ddr3/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/sc2_ah212_ddr3/aml-key/bl2aesiv b/board/amlogic/sc2_ah212_ddr3/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/sc2_ah212_ddr3/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/sc2_ah212_ddr3/aml-key/bl2aeskey b/board/amlogic/sc2_ah212_ddr3/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/sc2_ah212_ddr3/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/sc2_ah212_ddr3/aml-key/bl3xaesiv b/board/amlogic/sc2_ah212_ddr3/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/sc2_ah212_ddr3/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/sc2_ah212_ddr3/aml-key/bl3xaeskey b/board/amlogic/sc2_ah212_ddr3/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/sc2_ah212_ddr3/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/sc2_ah212_ddr3/aml-key/kernelaesiv b/board/amlogic/sc2_ah212_ddr3/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/sc2_ah212_ddr3/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/sc2_ah212_ddr3/aml-key/kernelaeskey b/board/amlogic/sc2_ah212_ddr3/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/sc2_ah212_ddr3/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/sc2_ah212_ddr3/aml-user-key.sig b/board/amlogic/sc2_ah212_ddr3/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/sc2_ah212_ddr3/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/sc2_ah212_ddr3/firmware/timing.c b/board/amlogic/sc2_ah212_ddr3/firmware/timing.c
new file mode 100644
index 0000000..02e538b
--- /dev/null
+++ b/board/amlogic/sc2_ah212_ddr3/firmware/timing.c
@@ -0,0 +1,399 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+#define DSU_CLK 1200
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+{
+ // U212 4layer 4pcs ddr3 rank01
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0xffff,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
+},
+{
+ // 4layer 2pcs ddr3 rank0
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
+},
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+ .dsu_clk = DSU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+};
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ {0, 0, 0xffffffff, 0, 0, 0},
+};
+
+/* gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+ /* demo, user defined override register */
+ {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ /* enable vddcpu dc-dc, set TEST_N to high */
+ {PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0},
+ {PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0},
+ /* set pwm h and pwm j clock rate to 24M, enable them */
+ {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0},
+ {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3 */
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0},
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0},
+};
+
+#define DEV_FIP_SIZE 0x300000
+#define DDR_FIP_SIZE 0x40000
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common = {
+ .version = 0x01,
+ .device_fip_container_size = DEV_FIP_SIZE,
+ .device_fip_container_copies = 4,
+ .ddr_fip_container_size = DDR_FIP_SIZE,
+ },
+ .nand = {
+ .version = 0x01,
+ .bbt_pages = 0x01,
+ .bbt_start_block = 20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (1 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 64,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/sc2_ah212_ddr3/fw_arb.cfg b/board/amlogic/sc2_ah212_ddr3/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/sc2_ah212_ddr3/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/sc2_ah212_ddr3/sc2_ah212_ddr3.c b/board/amlogic/sc2_ah212_ddr3/sc2_ah212_ddr3.c
new file mode 100644
index 0000000..4108aed
--- /dev/null
+++ b/board/amlogic/sc2_ah212_ddr3/sc2_ah212_ddr3.c
@@ -0,0 +1,475 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_ext.h>
+#endif
+#ifdef CONFIG_AML_CVBS
+#include <amlogic/media/vout/aml_cvbs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+
+static const char ddr_type_info[6][8] =
+{
+ "DDR3\0", //CONFIG_DDR_TYPE_DDR3 //0
+ "DDR4\0", //CONFIG_DDR_TYPE_DDR4 //1
+ "LPDDR4\0", //CONFIG_DDR_TYPE_LPDDR4 //2
+ "LPDDR3\0", //CONFIG_DDR_TYPE_LPDDR3 //3
+ "LPDDR2\0", //CONFIG_DDR_TYPE_LPDDR2 //4
+ "LPDDR4X\0", //CONFIG_DDR_TYPE_LPDDR4X //5
+};
+
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ unsigned int ddr_type;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ env_tmp = env_get("boot_ddr_type");
+ if (!env_tmp) {
+ ddr_type = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0x00070000) >> 16);
+ env_set("boot_ddr_type", 0);
+ env_set("boot_ddr_type", ddr_type_info[ddr_type]);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+ aml_set_bootsequence(0);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ #if 0
+ active_clk();
+ #endif
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ run_command("gpio clr GPIOH_8", 0);
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+ run_command("run bcb_cmd", 0);
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ /* reset vout init state */
+ run_command("setenv vout_init disable", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+
+#ifdef CONFIG_AML_CVBS
+ cvbs_init();
+#endif
+ run_command("amlsecurecheck", 0);
+ run_command("update_tries", 0);
+ return 0;
+}
+
+unsigned int get_ddr_memsize(void)
+{
+ unsigned int ddr_size;
+#if 0
+ /*if soc don't support automatic get ddr size,
+ then it get ddr size with software method*/
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+#else
+ /*auto get ddr size from hardware method*/
+ ddr_size = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4;
+#endif
+ return ddr_size;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf1000000UL,
+ .phys = 0xf1000000UL,
+ .size = 0x0f000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ /* update mmu table from bl2 ddr auto detect size */
+#ifdef CONFIG_UPDATE_MMU_TABLE
+ unsigned int nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4;
+ switch (nddrSize)
+ {
+ case (CONFIG_1G_SIZE):
+ case (CONFIG_2G_SIZE):
+ case (CONFIG_3G_SIZE):
+ case (CONFIG_DDR_MAX_SIZE):
+ bd_mem_map[0].size = nddrSize;
+ break;
+ default :
+ printf("aml log : ERROR DDR detect size not match MMU !");
+ break;
+ }
+#endif
+
+ //printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 1 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+
+uint64_t spiflash_bootloader_size(void)
+{
+ return 3 * SZ_1M;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+#ifdef CONFIG_AUTO_ADAPT_DDR_DTB
+ unsigned int ddr_size = 0;
+ char loc_name[64] = {0};
+ char *mem_size = env_get("mem_size");
+
+ ddr_size = get_ddr_memsize();
+
+ printf("%s:%d ddr_size:0x%x\r\n",__func__,__LINE__,ddr_size);
+ switch (ddr_size) {
+ case CONFIG_2G_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah212\0");
+
+ /* if limit memory size */
+ if (mem_size && !strcmp(mem_size, "1g")) {
+ strcpy(loc_name, "sc2_s905x4_ah212-1g\0");
+ }
+ break;
+ case CONFIG_1G_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah212-1g\0");
+ break;
+ case CONFIG_3G_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah212-3g\0");
+ break;
+ case CONFIG_DDR_MAX_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah212-4g\0");
+ break;
+ default:
+ printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size);
+ strcpy(loc_name, "sc2_s905x4_ah212_unsupport\0");
+ break;
+ }
+
+ strcpy(name, loc_name);
+ env_set("aml_dt", loc_name);
+ return 0;
+#else
+ strcpy(name, "sc2_s905x4_ah212\0");
+ env_set("aml_dt", "sc2_s905x4_ah212\0");
+ return 0;
+#endif
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/sc2_ah212_lpddr3/Kconfig b/board/amlogic/sc2_ah212_lpddr3/Kconfig
new file mode 100644
index 0000000..cf65ade
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr3/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_SC2_AH212_LPDDR3
+
+config SYS_SOC
+ default "sc2"
+
+config SYS_BOARD
+ default "sc2_ah212_lpddr3"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "sc2_ah212_lpddr3"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+endif
diff --git a/board/amlogic/sc2_ah212_lpddr3/Makefile b/board/amlogic/sc2_ah212_lpddr3/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr3/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/sc2_ah212_lpddr3/aml-key/bl2aesiv b/board/amlogic/sc2_ah212_lpddr3/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr3/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr3/aml-key/bl2aeskey b/board/amlogic/sc2_ah212_lpddr3/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr3/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr3/aml-key/bl3xaesiv b/board/amlogic/sc2_ah212_lpddr3/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr3/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr3/aml-key/bl3xaeskey b/board/amlogic/sc2_ah212_lpddr3/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr3/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr3/aml-key/kernelaesiv b/board/amlogic/sc2_ah212_lpddr3/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr3/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr3/aml-key/kernelaeskey b/board/amlogic/sc2_ah212_lpddr3/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr3/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr3/aml-user-key.sig b/board/amlogic/sc2_ah212_lpddr3/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr3/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr3/firmware/timing.c b/board/amlogic/sc2_ah212_lpddr3/firmware/timing.c
new file mode 100644
index 0000000..067d55c
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr3/firmware/timing.c
@@ -0,0 +1,383 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+#define DSU_CLK 1200
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+{
+ // 2layer lpddr3 rank01
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR3,
+ .DRAMFreq = {400, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0xffff,//1024,
+ .training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 60,
+ .cs_drv_ohm = 60,
+ .ac_drv_ohm = 60,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 30, //
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x3ff,//0x253,
+ .soc_ac_slew_rate = 0x3ff,//0x253,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 800,//200,
+ .vref_receiver_permil = 700,//875, //700 for drv 40 odt 60 is better ,why?
+ .vref_dram_permil = 600,//875,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {10,2,10,10,10,0x0,0x0,0x0,0x0,0x0},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 29 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 30 << 25 ),
+ [4] = ( 31| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {21/8,8/8,31/8,1/8},// {2,7,1,4,5,6,0,3,9,8},
+ .ddr_lpddr34_dq_remap = {1,2,7,4,0,3,5,6, 8,12,14,9,11,10,15,13, 21,22,16,17,23,20,19,18, 31,29,26,27,30,28,25,24},
+ //{21,22,16,17,23,20,19,18,8,12,14,9,11,10,15,13,31,29,26,27,30,28,25,24,1,2,7,4,0,3,5,6},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+ .training_offset = (0<<3) | (4<<0),//read dqs offset after training,bit3=0 right move,bit3=1 left move,bit[2:0] offset step
+},
+{
+ // 2layer lpddr3 rank0
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_4Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR3,
+ .DRAMFreq = {600, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0,//1024,
+ .training_SequenceCtrl = {0x131f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 60,
+ .cs_drv_ohm = 60,
+ .ac_drv_ohm = 60,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 30, //
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x3ff,//0x253,
+ .soc_ac_slew_rate = 0x3ff,//0x253,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 800,//200,
+ .vref_receiver_permil = 700,//875, //700 for drv 40 odt 60 is better ,why?
+ .vref_dram_permil = 600,//875,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {10,2,10,10,10,0x0,0x0,0x0,0x0,0x0},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 29 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 30 << 25 ),
+ [4] = ( 31| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {21/8,8/8,31/8,1/8},// {2,7,1,4,5,6,0,3,9,8},
+ .ddr_lpddr34_dq_remap = {1,2,7,4,0,3,5,6, 8,12,14,9,11,10,15,13, 21,22,16,17,23,20,19,18, 31,29,26,27,30,28,25,24},
+ //{21,22,16,17,23,20,19,18,8,12,14,9,11,10,15,13,31,29,26,27,30,28,25,24,1,2,7,4,0,3,5,6},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+ .training_offset = (0<<3) | (4<<0),//read dqs offset after training,bit3=0 right move,bit3=1 left move,bit[2:0] offset step
+},
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+ .dsu_clk = DSU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+};
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ {0, 0, 0xffffffff, 0, 0, 0},
+};
+
+/* gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+ /* demo, user defined override register */
+ {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ /* enable vddcpu dc-dc, set TEST_N to high */
+ {PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0},
+ {PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0},
+ /* set pwm h and pwm j clock rate to 24M, enable them */
+ {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0},
+ {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3 */
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0},
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0},
+};
+
+#define DEV_FIP_SIZE 0x300000
+#define DDR_FIP_SIZE 0x40000
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common = {
+ .version = 0x01,
+ .device_fip_container_size = DEV_FIP_SIZE,
+ .device_fip_container_copies = 4,
+ .ddr_fip_container_size = DDR_FIP_SIZE,
+ },
+ .nand = {
+ .version = 0x01,
+ .bbt_pages = 0x01,
+ .bbt_start_block = 20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (1 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 64,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/sc2_ah212_lpddr3/fw_arb.cfg b/board/amlogic/sc2_ah212_lpddr3/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr3/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/sc2_ah212_lpddr3/sc2_ah212_lpddr3.c b/board/amlogic/sc2_ah212_lpddr3/sc2_ah212_lpddr3.c
new file mode 100644
index 0000000..550ca7c
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr3/sc2_ah212_lpddr3.c
@@ -0,0 +1,476 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_ext.h>
+#endif
+#ifdef CONFIG_AML_CVBS
+#include <amlogic/media/vout/aml_cvbs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+
+static const char ddr_type_info[6][8] =
+{
+ "DDR3\0", //CONFIG_DDR_TYPE_DDR3 //0
+ "DDR4\0", //CONFIG_DDR_TYPE_DDR4 //1
+ "LPDDR4\0", //CONFIG_DDR_TYPE_LPDDR4 //2
+ "LPDDR3\0", //CONFIG_DDR_TYPE_LPDDR3 //3
+ "LPDDR2\0", //CONFIG_DDR_TYPE_LPDDR2 //4
+ "LPDDR4X\0", //CONFIG_DDR_TYPE_LPDDR4X //5
+};
+
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ unsigned int ddr_type;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ env_tmp = env_get("boot_ddr_type");
+ if (!env_tmp) {
+ ddr_type = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0x00070000) >> 16);
+ env_set("boot_ddr_type", 0);
+ env_set("boot_ddr_type", ddr_type_info[ddr_type]);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+ aml_set_bootsequence(0);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ #if 0
+ active_clk();
+ #endif
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ run_command("gpio clr GPIOH_8", 0);
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+ run_command("run bcb_cmd", 0);
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ /* reset vout init state */
+ run_command("setenv vout_init disable", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+
+#ifdef CONFIG_AML_CVBS
+ cvbs_init();
+#endif
+ run_command("amlsecurecheck", 0);
+ run_command("update_tries", 0);
+ return 0;
+}
+
+unsigned int get_ddr_memsize(void)
+{
+ unsigned int ddr_size;
+#if 0
+ /*if soc don't support automatic get ddr size,
+ then it get ddr size with software method*/
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+#else
+ /*auto get ddr size from hardware method*/
+ ddr_size = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4;
+#endif
+ return ddr_size;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf1000000UL,
+ .phys = 0xf1000000UL,
+ .size = 0x0f000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ /* update mmu table from bl2 ddr auto detect size */
+#ifdef CONFIG_UPDATE_MMU_TABLE
+ unsigned int nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4;
+ switch (nddrSize)
+ {
+ case (CONFIG_1G_SIZE):
+ case (CONFIG_2G_SIZE):
+ case (CONFIG_3G_SIZE):
+ case (CONFIG_DDR_MAX_SIZE):
+ bd_mem_map[0].size = nddrSize;
+ break;
+ default :
+ printf("aml log : ERROR DDR detect size not match MMU !");
+ break;
+ }
+#endif
+
+ //printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 1 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+
+uint64_t spiflash_bootloader_size(void)
+{
+ return 3 * SZ_1M;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+#ifdef CONFIG_AUTO_ADAPT_DDR_DTB
+ unsigned int ddr_size = 0;
+ char loc_name[64] = {0};
+ char *mem_size = env_get("mem_size");
+
+ ddr_size = get_ddr_memsize();
+
+ printf("%s:%d ddr_size:0x%x\r\n",__func__,__LINE__,ddr_size);
+ switch (ddr_size) {
+ case CONFIG_2G_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah212\0");
+
+ /* if limit memory size */
+ if (mem_size && !strcmp(mem_size, "1g")) {
+ strcpy(loc_name, "sc2_s905x4_ah212-1g\0");
+ }
+ break;
+ case CONFIG_1G_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah212-1g\0");
+ break;
+ case CONFIG_3G_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah212-3g\0");
+ break;
+ case CONFIG_DDR_MAX_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah212-4g\0");
+ break;
+ default:
+ printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size);
+ strcpy(loc_name, "sc2_s905x4_ah212_unsupport\0");
+ break;
+ }
+
+ strcpy(name, loc_name);
+ env_set("aml_dt", loc_name);
+ return 0;
+#else
+ strcpy(name, "sc2_s905x4_ah212\0");
+ env_set("aml_dt", "sc2_s905x4_ah212\0");
+ return 0;
+#endif
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/sc2_ah212_lpddr4/Kconfig b/board/amlogic/sc2_ah212_lpddr4/Kconfig
new file mode 100644
index 0000000..3c8ec71
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr4/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_SC2_AH212_LPDDR4
+
+config SYS_SOC
+ default "sc2"
+
+config SYS_BOARD
+ default "sc2_ah212_lpddr4"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "sc2_ah212_lpddr4"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+endif
diff --git a/board/amlogic/sc2_ah212_lpddr4/Makefile b/board/amlogic/sc2_ah212_lpddr4/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr4/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/sc2_ah212_lpddr4/aml-key/bl2aesiv b/board/amlogic/sc2_ah212_lpddr4/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr4/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr4/aml-key/bl2aeskey b/board/amlogic/sc2_ah212_lpddr4/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr4/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr4/aml-key/bl3xaesiv b/board/amlogic/sc2_ah212_lpddr4/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr4/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr4/aml-key/bl3xaeskey b/board/amlogic/sc2_ah212_lpddr4/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr4/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr4/aml-key/kernelaesiv b/board/amlogic/sc2_ah212_lpddr4/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr4/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr4/aml-key/kernelaeskey b/board/amlogic/sc2_ah212_lpddr4/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr4/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr4/aml-user-key.sig b/board/amlogic/sc2_ah212_lpddr4/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr4/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/sc2_ah212_lpddr4/firmware/timing.c b/board/amlogic/sc2_ah212_lpddr4/firmware/timing.c
new file mode 100644
index 0000000..0a7d879
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr4/firmware/timing.c
@@ -0,0 +1,379 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+#define DSU_CLK 1200
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+{
+ // 2layer lpddr4 rank01
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1008, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0xffff,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {3,0,2,1,7,6,5,4, 13,12,15,14,10,8,11,9, 19,21,22,20,16,18,17,23, 26,27,25,24,31,29,30,28},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .diagnose = CONFIG_DIAGNOSE_DISABLE,
+},
+{
+ // 2layer lpddr4 rank0
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .DRAMFreq = {1008, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xa,
+ .dram_cs0_size_MB = 0xffff,//1024,
+ .dram_cs1_size_MB = 0,//1024,
+ .training_SequenceCtrl = {0x131f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 0,
+ .soc_data_odt_ohm_n = 120,
+ .dram_data_drv_ohm = 40, //lpddr4 sdram only240/1-6
+ .dram_data_odt_ohm = 120,
+ .dram_ac_odt_ohm = 120,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting = 1,///1, 1/3vddq 0 2/5 vddq
+ .soc_clk_slew_rate = 0x3ff,//0x253,
+ .soc_cs_slew_rate = 0x100,//0x253,
+ .soc_ac_slew_rate = 0x100,//0x253,
+ .soc_data_slew_rate = 0x1ff,
+ .vref_output_permil = 350,//200,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {00,0x0,0,0,0,0,0x0,00},
+ .ac_pinmux = {00,00},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 6 << 5 | 7 << 10 | 8<< 15 | 9<< 20 | 10 << 25 ),
+ [1] = ( 11| 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25 ),
+ [2] = ( 18| 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 12 << 5 | 13 << 10 | 14<< 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {3,0,2,1,7,6,5,4, 13,12,15,14,10,8,11,9, 19,21,22,20,16,18,17,23, 26,27,25,24,31,29,30,28},
+ .dram_rtt_nom_wr_park = {00,00},
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+ .dsu_clk = DSU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+};
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ {0, 0, 0xffffffff, 0, 0, 0},
+};
+
+/* gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+ /* demo, user defined override register */
+ {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ /* enable vddcpu dc-dc, set TEST_N to high */
+ {PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0},
+ {PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0},
+ /* set pwm h and pwm j clock rate to 24M, enable them */
+ {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0},
+ {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3 */
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0},
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0},
+};
+
+#define DEV_FIP_SIZE 0x300000
+#define DDR_FIP_SIZE 0x40000
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common = {
+ .version = 0x01,
+ .device_fip_container_size = DEV_FIP_SIZE,
+ .device_fip_container_copies = 4,
+ .ddr_fip_container_size = DDR_FIP_SIZE,
+ },
+ .nand = {
+ .version = 0x01,
+ .bbt_pages = 0x01,
+ .bbt_start_block = 20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (1 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 64,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/sc2_ah212_lpddr4/fw_arb.cfg b/board/amlogic/sc2_ah212_lpddr4/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr4/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/sc2_ah212_lpddr4/sc2_ah212_lpddr4.c b/board/amlogic/sc2_ah212_lpddr4/sc2_ah212_lpddr4.c
new file mode 100644
index 0000000..3010797
--- /dev/null
+++ b/board/amlogic/sc2_ah212_lpddr4/sc2_ah212_lpddr4.c
@@ -0,0 +1,476 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_ext.h>
+#endif
+#ifdef CONFIG_AML_CVBS
+#include <amlogic/media/vout/aml_cvbs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+
+static const char ddr_type_info[6][8] =
+{
+ "DDR3\0", //CONFIG_DDR_TYPE_DDR3 //0
+ "DDR4\0", //CONFIG_DDR_TYPE_DDR4 //1
+ "LPDDR4\0", //CONFIG_DDR_TYPE_LPDDR4 //2
+ "LPDDR3\0", //CONFIG_DDR_TYPE_LPDDR3 //3
+ "LPDDR2\0", //CONFIG_DDR_TYPE_LPDDR2 //4
+ "LPDDR4X\0", //CONFIG_DDR_TYPE_LPDDR4X //5
+};
+
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ unsigned int ddr_type;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ env_tmp = env_get("boot_ddr_type");
+ if (!env_tmp) {
+ ddr_type = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0x00070000) >> 16);
+ env_set("boot_ddr_type", 0);
+ env_set("boot_ddr_type", ddr_type_info[ddr_type]);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+ aml_set_bootsequence(0);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ #if 0
+ active_clk();
+ #endif
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ run_command("gpio clr GPIOH_8", 0);
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+ run_command("run bcb_cmd", 0);
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ /* reset vout init state */
+ run_command("setenv vout_init disable", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+
+#ifdef CONFIG_AML_CVBS
+ cvbs_init();
+#endif
+ run_command("amlsecurecheck", 0);
+ run_command("update_tries", 0);
+ return 0;
+}
+
+unsigned int get_ddr_memsize(void)
+{
+ unsigned int ddr_size;
+#if 0
+ /*if soc don't support automatic get ddr size,
+ then it get ddr size with software method*/
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+#else
+ /*auto get ddr size from hardware method*/
+ ddr_size = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4;
+#endif
+ return ddr_size;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf1000000UL,
+ .phys = 0xf1000000UL,
+ .size = 0x0f000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ //update mmu table from bl2 ddr auto detect size
+#ifdef CONFIG_UPDATE_MMU_TABLE
+ unsigned int nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4;
+ switch (nddrSize)
+ {
+ case (CONFIG_1G_SIZE):
+ case (CONFIG_2G_SIZE):
+ case (CONFIG_3G_SIZE):
+ case (CONFIG_DDR_MAX_SIZE):
+ bd_mem_map[0].size = nddrSize;
+ break;
+ default :
+ printf("aml log : ERROR DDR detect size not match MMU !");
+ break;
+ }
+#endif
+
+ //printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 1 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+
+uint64_t spiflash_bootloader_size(void)
+{
+ return 3 * SZ_1M;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+#ifdef CONFIG_AUTO_ADAPT_DDR_DTB
+ unsigned int ddr_size = 0;
+ char loc_name[64] = {0};
+ char *mem_size = env_get("mem_size");
+
+ ddr_size = get_ddr_memsize();
+
+ printf("%s:%d ddr_size:0x%x\r\n",__func__,__LINE__,ddr_size);
+ switch (ddr_size) {
+ case CONFIG_2G_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah212\0");
+
+ /* if limit memory size */
+ if (mem_size && !strcmp(mem_size, "1g")) {
+ strcpy(loc_name, "sc2_s905x4_ah212-1g\0");
+ }
+ break;
+ case CONFIG_1G_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah212-1g\0");
+ break;
+ case CONFIG_3G_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah212-3g\0");
+ break;
+ case CONFIG_DDR_MAX_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah212-4g\0");
+ break;
+ default:
+ printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size);
+ strcpy(loc_name, "sc2_s905x4_ah212_unsupport\0");
+ break;
+ }
+
+ strcpy(name, loc_name);
+ env_set("aml_dt", loc_name);
+ return 0;
+#else
+ strcpy(name, "sc2_s905x4_ah212\0");
+ env_set("aml_dt", "sc2_s905x4_ah212\0");
+ return 0;
+#endif
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/sc2_ah219/Kconfig b/board/amlogic/sc2_ah219/Kconfig
new file mode 100644
index 0000000..b8e4142
--- /dev/null
+++ b/board/amlogic/sc2_ah219/Kconfig
@@ -0,0 +1,31 @@
+if TARGET_SC2_AH219
+
+config SYS_SOC
+ default "sc2"
+
+config SYS_BOARD
+ default "sc2_ah219"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "sc2_ah219"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+
+endif
diff --git a/board/amlogic/sc2_ah219/Makefile b/board/amlogic/sc2_ah219/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/sc2_ah219/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/sc2_ah219/aml-key/bl2aesiv b/board/amlogic/sc2_ah219/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/sc2_ah219/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/sc2_ah219/aml-key/bl2aeskey b/board/amlogic/sc2_ah219/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/sc2_ah219/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/sc2_ah219/aml-key/bl3xaesiv b/board/amlogic/sc2_ah219/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/sc2_ah219/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/sc2_ah219/aml-key/bl3xaeskey b/board/amlogic/sc2_ah219/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/sc2_ah219/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/sc2_ah219/aml-key/kernelaesiv b/board/amlogic/sc2_ah219/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/sc2_ah219/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/sc2_ah219/aml-key/kernelaeskey b/board/amlogic/sc2_ah219/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/sc2_ah219/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/sc2_ah219/aml-user-key.sig b/board/amlogic/sc2_ah219/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/sc2_ah219/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/sc2_ah219/firmware/timing.c b/board/amlogic/sc2_ah219/firmware/timing.c
new file mode 100644
index 0000000..cbd6126
--- /dev/null
+++ b/board/amlogic/sc2_ah219/firmware/timing.c
@@ -0,0 +1,411 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+#define DSU_CLK 1200
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+{
+ // g12a 4layer 2pcs ddr3 rank0
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
+},
+{
+ // g12a 4layer 2pcs ddr4 rank0 (1320)(U200)
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1320, 0, 0, 0},
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {32-10,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
+},
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+ .dsu_clk = DSU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+};
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ {0, 0, 0xffffffff, 0, 0, 0},
+};
+
+/* gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+ /* demo, user defined override register */
+ {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ /* enable vddcpu dc-dc, set TEST_N to high */
+ {PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0},
+ {PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0},
+ /* set pwm h and pwm j clock rate to 24M, enable them */
+ {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0},
+ {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3 */
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0},
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0},
+};
+
+#define DEV_FIP_SIZE 0x300000
+#define DDR_FIP_SIZE 0x40000
+#ifdef CONFIG_MTD_SPI_NAND
+/* for spinand storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common = {
+ .version = 0x01,
+ .device_fip_container_size = DEV_FIP_SIZE,
+ .device_fip_container_copies = 4,
+ .ddr_fip_container_size = DDR_FIP_SIZE,
+ },
+ .nand = {
+ .version = 0x01,
+ .bbt_pages = 1, // TODO: BL2E BBT
+ .bbt_start_block = 20,
+ .discrete_mode = 1,
+ .setup_data.spi_nand_page_size = 2048,
+ .reserved.spi_nand_planes_per_lun = 1,
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 64,
+ .use_param_page_list = 0,
+ },
+};
+#else
+/* for slcnand storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common = {
+ .version = 0x01,
+ .device_fip_container_size = DEV_FIP_SIZE,
+ .device_fip_container_copies = 4,
+ .ddr_fip_container_size = DDR_FIP_SIZE,
+ },
+ .nand = {
+ .version = 0x01,
+ .bbt_pages = 0x01,
+ .bbt_start_block = 20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (1 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 64,
+ .use_param_page_list = 0,
+ },
+};
+#endif
diff --git a/board/amlogic/sc2_ah219/fw_arb.cfg b/board/amlogic/sc2_ah219/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/sc2_ah219/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/sc2_ah219/sc2_ah219.c b/board/amlogic/sc2_ah219/sc2_ah219.c
new file mode 100644
index 0000000..4678e8f
--- /dev/null
+++ b/board/amlogic/sc2_ah219/sc2_ah219.c
@@ -0,0 +1,468 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#include <amlogic/aml_mtd.h>
+
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_ext.h>
+#endif
+#ifdef CONFIG_AML_CVBS
+#include <amlogic/media/vout/aml_cvbs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+
+static const char ddr_type_info[6][8] =
+{
+ "DDR3\0", //CONFIG_DDR_TYPE_DDR3 //0
+ "DDR4\0", //CONFIG_DDR_TYPE_DDR4 //1
+ "LPDDR4\0", //CONFIG_DDR_TYPE_LPDDR4 //2
+ "LPDDR3\0", //CONFIG_DDR_TYPE_LPDDR3 //3
+ "LPDDR2\0", //CONFIG_DDR_TYPE_LPDDR2 //4
+ "LPDDR4X\0", //CONFIG_DDR_TYPE_LPDDR4X //5
+};
+
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ unsigned int ddr_type;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ env_tmp = env_get("boot_ddr_type");
+ if (!env_tmp) {
+ ddr_type = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0x00070000) >> 16);
+ env_set("boot_ddr_type", 0);
+ env_set("boot_ddr_type", ddr_type_info[ddr_type]);
+ }
+
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+ aml_set_bootsequence(0);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ #if 0
+ active_clk();
+ #endif
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ //default uboot env need before anyone use it
+ if (env_get("default_env")) {
+ printf("factory reset, need default all uboot env.\n");
+ run_command("defenv_reserv; setenv upgrade_step 2; saveenv;", 0);
+ }
+
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+ run_command("run bcb_cmd", 0);
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ /* reset vout init state */
+ run_command("setenv vout_init disable", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+#ifdef CONFIG_AML_CVBS
+ cvbs_init();
+#endif
+ run_command("amlsecurecheck", 0);
+ run_command("update_tries", 0);
+ return 0;
+}
+
+unsigned int get_ddr_memsize(void)
+{
+ unsigned int ddr_size;
+#if 0
+ /*if soc don't support automatic get ddr size,
+ then it get ddr size with software method*/
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+#else
+ /*auto get ddr size from hardware method*/
+ ddr_size = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4;
+#endif
+ return ddr_size;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ //printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 1 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+
+uint64_t spiflash_bootloader_size(void)
+{
+ return 3 * SZ_1M;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+}
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+#ifdef CONFIG_AUTO_ADAPT_DDR_DTB
+ unsigned int ddr_size = 0;
+ char loc_name[64] = {0};
+ char *mem_size = env_get("mem_size");
+
+ ddr_size = get_ddr_memsize();
+
+ printf("%s:%d ddr_size:0x%x\r\n",__func__,__LINE__,ddr_size);
+ switch (ddr_size) {
+ case CONFIG_2G_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah219\0");
+
+ /* if limit memory size */
+ if (mem_size && !strcmp(mem_size, "1g")) {
+ strcpy(loc_name, "sc2_s905x4_ah219-1g\0");
+ }
+ break;
+ case CONFIG_1G_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah219-1g\0");
+ break;
+ case CONFIG_3G_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah219-3g\0");
+ break;
+ case CONFIG_DDR_MAX_SIZE:
+ strcpy(loc_name, "sc2_s905x4_ah219-4g\0");
+ break;
+ default:
+ printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size);
+ strcpy(loc_name, "sc2_s905x4_ah219_unsupport\0");
+ break;
+ }
+
+ strcpy(name, loc_name);
+ env_set("aml_dt", loc_name);
+ return 0;
+#else
+ strcpy(name, "sc2_s905x4_ah219\0");
+ env_set("aml_dt", "sc2_s905x4_ah219\0");
+ return 0;
+#endif
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/sc2_ah232/Kconfig b/board/amlogic/sc2_ah232/Kconfig
new file mode 100644
index 0000000..dab32a5
--- /dev/null
+++ b/board/amlogic/sc2_ah232/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_SC2_AH232
+
+config SYS_SOC
+ default "sc2"
+
+config SYS_BOARD
+ default "sc2_ah232"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "sc2_ah232"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+endif
diff --git a/board/amlogic/sc2_ah232/Makefile b/board/amlogic/sc2_ah232/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/sc2_ah232/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/sc2_ah232/firmware/timing.c b/board/amlogic/sc2_ah232/firmware/timing.c
new file mode 100644
index 0000000..e0478bb
--- /dev/null
+++ b/board/amlogic/sc2_ah232/firmware/timing.c
@@ -0,0 +1,388 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+#define DSU_CLK 1200
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+{
+ // g12a 4layer 2pcs ddr3 rank0
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
+},
+{
+ // g12a 4layer 2pcs ddr4 rank0 (1320)(U200)
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1320, 0, 0, 0},
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.imem_load_addr = 0xFFFC0000, //sram
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {32-10,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .fast_boot[0] = 1,
+},
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+ .dsu_clk = DSU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+};
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ {0, 0, 0xffffffff, 0, 0, 0},
+};
+
+/* gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+ /* demo, user defined override register */
+ {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ /* enable vddcpu dc-dc, set TEST_N to high */
+ {PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0},
+ {PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0},
+ /* set pwm h and pwm j clock rate to 24M, enable them */
+ {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0},
+ {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3 */
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0},
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0},
+};
+
+#define DEV_FIP_SIZE 0x300000
+#define DDR_FIP_SIZE 0x40000
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common = {
+ .version = 0x01,
+ .device_fip_container_size = DEV_FIP_SIZE,
+ .device_fip_container_copies = 4,
+ .ddr_fip_container_size = DDR_FIP_SIZE,
+ },
+ .nand = {
+ .version = 0x01,
+ .bbt_pages = 0x01,
+ .bbt_start_block = 20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (1 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 64,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/sc2_ah232/fw_arb.cfg b/board/amlogic/sc2_ah232/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/sc2_ah232/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/sc2_ah232/sc2_ah232.c b/board/amlogic/sc2_ah232/sc2_ah232.c
new file mode 100644
index 0000000..31dc66a
--- /dev/null
+++ b/board/amlogic/sc2_ah232/sc2_ah232.c
@@ -0,0 +1,482 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_ext.h>
+#endif
+#ifdef CONFIG_AML_CVBS
+#include <amlogic/media/vout/aml_cvbs.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+
+static const char ddr_type_info[6][8] =
+{
+ "DDR3\0", //CONFIG_DDR_TYPE_DDR3 //0
+ "DDR4\0", //CONFIG_DDR_TYPE_DDR4 //1
+ "LPDDR4\0", //CONFIG_DDR_TYPE_LPDDR4 //2
+ "LPDDR3\0", //CONFIG_DDR_TYPE_LPDDR3 //3
+ "LPDDR2\0", //CONFIG_DDR_TYPE_LPDDR2 //4
+ "LPDDR4X\0", //CONFIG_DDR_TYPE_LPDDR4X //5
+};
+
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ unsigned int ddr_type;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ env_tmp = env_get("boot_ddr_type");
+ if (!env_tmp) {
+ ddr_type = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0x00070000) >> 16);
+ env_set("boot_ddr_type", 0);
+ env_set("boot_ddr_type", ddr_type_info[ddr_type]);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+ aml_set_bootsequence(0);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ #if 0
+ active_clk();
+ #endif
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ run_command("gpio clr GPIOH_8", 0);
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ //default uboot env need before anyone use it
+ if (env_get("default_env")) {
+ printf("factory reset, need default all uboot env.\n");
+ run_command("defenv_reserv; setenv upgrade_step 2; saveenv;", 0);
+ }
+
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+ run_command("run bcb_cmd", 0);
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ /* reset vout init state */
+ run_command("setenv vout_init disable", 0);
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+
+#ifdef CONFIG_AML_CVBS
+ cvbs_init();
+#endif
+ run_command("amlsecurecheck", 0);
+ run_command("update_tries", 0);
+ return 0;
+}
+
+unsigned int get_ddr_memsize(void)
+{
+ unsigned int ddr_size;
+#if 0
+ /*if soc don't support automatic get ddr size,
+ then it get ddr size with software method*/
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
+ ddr_size += gd->bd->bi_dram[i].size;
+ }
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ ddr_size += CONFIG_SYS_MEM_TOP_HIDE;
+#endif
+#else
+ /*auto get ddr size from hardware method*/
+ ddr_size = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4;
+#endif
+ return ddr_size;
+}
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf1000000UL,
+ .phys = 0xf1000000UL,
+ .size = 0x0f000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ /* update mmu table from bl2 ddr auto detect size */
+#ifdef CONFIG_UPDATE_MMU_TABLE
+ unsigned int nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFF80000) << 4;
+ switch (nddrSize)
+ {
+ case (CONFIG_1G_SIZE):
+ case (CONFIG_2G_SIZE):
+ case (CONFIG_3G_SIZE):
+ case (CONFIG_DDR_MAX_SIZE):
+ bd_mem_map[0].size = nddrSize;
+ break;
+ default :
+ printf("aml log : ERROR DDR detect size not match MMU !");
+ break;
+ }
+#endif
+
+ //printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 1 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+
+uint64_t spiflash_bootloader_size(void)
+{
+ return 3 * SZ_1M;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+#ifdef CONFIG_AUTO_ADAPT_DDR_DTB
+ unsigned int ddr_size = 0;
+ char loc_name[64] = {0};
+ char *mem_size = env_get("mem_size");
+
+ ddr_size = get_ddr_memsize();
+
+ printf("%s:%d ddr_size:0x%x\r\n",__func__,__LINE__,ddr_size);
+ switch (ddr_size) {
+ case CONFIG_2G_SIZE:
+ strcpy(loc_name, "sc2_s905c2_232\0");
+
+ /* if limit memory size */
+ if (mem_size && !strcmp(mem_size, "1g")) {
+ strcpy(loc_name, "sc2_s905c2_232-1g\0");
+ }
+ break;
+ case CONFIG_1G_SIZE:
+ strcpy(loc_name, "sc2_s905c2_232-1g\0");
+ break;
+ case CONFIG_3G_SIZE:
+ strcpy(loc_name, "sc2_s905c2_232-3g\0");
+ break;
+ case CONFIG_DDR_MAX_SIZE:
+ strcpy(loc_name, "sc2_s905c2_232-4g\0");
+ break;
+ default:
+ printf("DDR size: 0x%x, multi-dt doesn't support\n", ddr_size);
+ strcpy(loc_name, "sc2_s905c2_232_unsupport\0");
+ break;
+ }
+
+ strcpy(name, loc_name);
+ env_set("aml_dt", loc_name);
+ return 0;
+#else
+ strcpy(name, "sc2_s905c2_232\0");
+ env_set("aml_dt", "sc2_s905c2_232\0");
+ return 0;
+#endif
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/sc2_skt/Kconfig b/board/amlogic/sc2_skt/Kconfig
new file mode 100644
index 0000000..5bdd867
--- /dev/null
+++ b/board/amlogic/sc2_skt/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_SC2_SKT
+
+config SYS_SOC
+ default "sc2"
+
+config SYS_BOARD
+ default "sc2_skt"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "sc2_skt"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+endif
diff --git a/board/amlogic/sc2_skt/Makefile b/board/amlogic/sc2_skt/Makefile
new file mode 100644
index 0000000..0403c0c
--- /dev/null
+++ b/board/amlogic/sc2_skt/Makefile
@@ -0,0 +1 @@
+obj-y += $(BOARD).o
diff --git a/board/amlogic/sc2_skt/aml-key/bl2aesiv b/board/amlogic/sc2_skt/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/sc2_skt/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/sc2_skt/aml-key/bl2aeskey b/board/amlogic/sc2_skt/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/sc2_skt/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/sc2_skt/aml-key/bl3xaesiv b/board/amlogic/sc2_skt/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/sc2_skt/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/sc2_skt/aml-key/bl3xaeskey b/board/amlogic/sc2_skt/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/sc2_skt/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/sc2_skt/aml-key/kernelaesiv b/board/amlogic/sc2_skt/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/sc2_skt/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/sc2_skt/aml-key/kernelaeskey b/board/amlogic/sc2_skt/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/sc2_skt/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/sc2_skt/aml-user-key.sig b/board/amlogic/sc2_skt/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/sc2_skt/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/sc2_skt/firmware/timing.c b/board/amlogic/sc2_skt/firmware/timing.c
new file mode 100644
index 0000000..27a55e9
--- /dev/null
+++ b/board/amlogic/sc2_skt/firmware/timing.c
@@ -0,0 +1,399 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+
+/* ddr configs */
+#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+
+#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+{
+ /* ddr3 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_16BIT_RANK0_CH0,//CONFIG_DDR0_16BIT_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR3,
+ /* DRAMFreq = 192, 256, 384, 512, 768-1536 */
+ .DRAMFreq = {912, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 768,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 34,
+ .soc_data_drv_ohm_n = 34,
+ .soc_data_odt_ohm_p = 60, //48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x300,
+ .soc_cs_slew_rate = 0x300,
+ .soc_ac_slew_rate = 0x300,
+ .soc_data_slew_rate = 0x200,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 500, //700,
+ .vref_dram_permil = 500, //700,
+ //.vref_reverse = 0,
+ .ac_trace_delay = {32,32,32,32,32,32,32,32,32,32},
+ //{00,00},
+ .ac_pinmux = {00,00},
+#if 1
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+#else
+ //16bit
+ .ddr_dmc_remap = {
+ [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
+ [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
+ [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
+ [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
+ },
+#endif
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+{
+ /* ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ .dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq = {1176, 0, 0, 0},
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ //.dmem_load_size = 0x1000, //4K
+
+ .DisabledDbyte = 0xf0,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ .dram_cs0_size_MB = 0xffff,
+ .dram_cs1_size_MB = 0,
+ .training_SequenceCtrl = {0x31f,0x61}, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0,
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 34,//48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,//700,
+ .vref_dram_permil = 0,//700,
+ //.vref_reverse = 0,
+ //.ac_trace_delay = {0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay = {16,32,32,32,32,32,32,32,32,32},
+ .ddr_dmc_remap = {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ .ddr_lpddr34_ca_remap = {00,00},
+ .ddr_lpddr34_dq_remap = {00,00},
+ .dram_rtt_nom_wr_park = {00,00},
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+},
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+};
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+ #define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+ #define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+ #define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+ #define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+ #define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+ #define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+ #define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+ #define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+ #define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+ #define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+ #define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+ #define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+ #define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+ #define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+ #define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+ #define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+ #define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+ #define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+ #define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+ #define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+ #define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+ #define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+ #define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+ #define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+ #define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+ #define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+ #define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+ #define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+ #define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+ #define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+ #define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+ #define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+ #define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+ #define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+ #define VCCK_VAL_REG 0x00220000
+#else
+ #error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 700)
+ #define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 710)
+ #define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 720)
+ #define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 730)
+ #define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 740)
+ #define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 750)
+ #define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 760)
+ #define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 770)
+ #define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 780)
+ #define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 790)
+ #define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 800)
+ #define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 810)
+ #define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 820)
+ #define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 830)
+ #define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 840)
+ #define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 850)
+ #define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 860)
+ #define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 870)
+ #define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 880)
+ #define VDDEE_VAL_REG 0x12
+#else
+ #error "VDDEE val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ {0, 0, 0xffffffff, 0, 0, 0},
+};
+
+/* gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+ /* demo, user defined override register */
+ {PWMGH_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMIJ_PWM_B, VCCK_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWMGH_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ {PWMIJ_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ /* enable vddcpu dc-dc, set TEST_N to high */
+ {PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0},
+ {PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0},
+ /* set pwm h and pwm j clock rate to 24M, enable them */
+ {CLKCTRL_PWM_CLK_GH_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0},
+ {CLKCTRL_PWM_CLK_IJ_CTRL, (1 << 8 | 1 << 24) , 0xffffffff, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 drive strength to 3 */
+ {PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0},
+ /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0},
+ {PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0},
+};
+
+#define DEV_FIP_SIZE 0x300000
+#define DDR_FIP_SIZE 0x40000
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common = {
+ .version = 0x01,
+ .device_fip_container_size = DEV_FIP_SIZE,
+ .device_fip_container_copies = 4,
+ .ddr_fip_container_size = DDR_FIP_SIZE,
+ },
+ .nand = {
+ .version = 0x01,
+ .bbt_pages = 0x01,
+ .bbt_start_block = 20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (1 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 64,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/sc2_skt/fw_arb.cfg b/board/amlogic/sc2_skt/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/sc2_skt/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/sc2_skt/sc2_skt.c b/board/amlogic/sc2_skt/sc2_skt.c
new file mode 100644
index 0000000..2da6d4b
--- /dev/null
+++ b/board/amlogic/sc2_skt/sc2_skt.c
@@ -0,0 +1,354 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+ aml_set_bootsequence(0);
+ #if 0
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ active_clk();
+ #endif
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ #if 0
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+ #endif
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x80000000UL,
+ .phys = 0x80000000UL,
+ .size = 0x80000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ //printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_spinand_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/sm1_ac200_v1/Kconfig b/board/amlogic/sm1_ac200_v1/Kconfig
index c4f59b9..2806f76 100644
--- a/board/amlogic/sm1_ac200_v1/Kconfig
+++ b/board/amlogic/sm1_ac200_v1/Kconfig
@@ -10,4 +10,3 @@
default "g12a_u200_v1"
endif
-
diff --git a/board/amlogic/sm1_elaine_b1/Kconfig b/board/amlogic/sm1_elaine_b1/Kconfig
deleted file mode 100755
index 0ff53d2..0000000
--- a/board/amlogic/sm1_elaine_b1/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_SM1_ELAINE_B1
-
-config SYS_SOC
- default "g12a"
-
-config SYS_BOARD
- default "sm1_elaine_b1"
-
-config SYS_VENDOR
- default "amlogic"
-
-config SYS_CONFIG_NAME
- default "sm1_elaine_b1"
-
-endif
diff --git a/board/amlogic/sm1_elaine_b1/Makefile b/board/amlogic/sm1_elaine_b1/Makefile
deleted file mode 100755
index 82a876d..0000000
--- a/board/amlogic/sm1_elaine_b1/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-
-obj-y += $(BOARD).o
-obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/sm1_elaine_b1/aml-user-key.sig b/board/amlogic/sm1_elaine_b1/aml-user-key.sig
deleted file mode 100755
index 2ceabc1..0000000
--- a/board/amlogic/sm1_elaine_b1/aml-user-key.sig
+++ /dev/null
Binary files differ
diff --git a/board/amlogic/sm1_elaine_b1/firmware/ramdump.c b/board/amlogic/sm1_elaine_b1/firmware/ramdump.c
deleted file mode 100755
index e03dcd2..0000000
--- a/board/amlogic/sm1_elaine_b1/firmware/ramdump.c
+++ /dev/null
@@ -1,45 +0,0 @@
-
-#ifdef CONFIG_MDUMP_COMPRESS
-#include "ramdump.h"
-
-struct ram_compress_full __ramdump_data = {
- .store_phy_addr = (void *)CONFIG_COMPRESSED_DATA_ADDR,
- .full_memsize = CONFIG_DDR_TOTAL_SIZE,
- .section_count = CONFIG_COMPRESS_SECTION,
- .sections = {
- {
- /* memory afer compressed data address */
- .phy_addr = (void *)CONFIG_COMPRESSED_DATA_ADDR,
- .section_size = CONFIG_DDR_TOTAL_SIZE -
- CONFIG_COMPRESSED_DATA_ADDR,
- .section_index = 4,
- .compress_type = RAM_COMPRESS_NORMAL,
- },
- {
- /* memory before bl2 */
- .phy_addr = (void *)CONFIG_COMPRESS_START_ADDR,
- .section_size = CONFIG_BL2_IGNORE_ADDR -
- CONFIG_COMPRESS_START_ADDR,
- .section_index = 1,
- .compress_type = RAM_COMPRESS_NORMAL,
- },
- {
- /* memory in reserved bl2 */
- .phy_addr = (void *)CONFIG_BL2_IGNORE_ADDR,
- .section_size = CONFIG_BL2_IGNORE_SIZE,
- .section_index = 2,
- .compress_type = RAM_COMPRESS_SET,
- .set_value = 0x0,
- },
- {
- /* segment 4: normal compress */
- .phy_addr = (void *)CONFIG_SEG4_ADDR,
- .section_size = CONFIG_COMPRESSED_DATA_ADDR -
- CONFIG_SEG4_ADDR,
- .section_index = 3,
- .compress_type = RAM_COMPRESS_NORMAL,
- }
- },
-};
-#endif /* CONFIG_MDUMP_COMPRESS */
-
diff --git a/board/amlogic/sm1_elaine_b1/firmware/ramdump.h b/board/amlogic/sm1_elaine_b1/firmware/ramdump.h
deleted file mode 100755
index 0671567..0000000
--- a/board/amlogic/sm1_elaine_b1/firmware/ramdump.h
+++ /dev/null
@@ -1,75 +0,0 @@
-#ifndef __RAM_DUMP_H__
-#define __RAM_DUMP_H__
-
-#include <config.h>
-#ifdef CONFIG_MDUMP_COMPRESS
-#define CONFIG_COMPRESS_SECTION 4
-
-#if CONFIG_COMPRESS_SECTION > 8
-#error ---> CONFIG_COMPRESS_SECTION out of range, max should be 8
-#endif
-/*
- * Full Memory lay out for RAM compress:
- *
- * DDR_TOP -> +--------+
- * | |
- * | |
- * | 4 |
- * | |
- * | |
- * |~~~~~~~~| <- store compressing data
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * COMPRESSED_DATA -> +--------+
- * | |
- * | 3 |
- * | |
- * BL2_IGNORE_END -> +--------+ -- IGNORE_SIZE
- * ||||||||||
- * ||||2|||||
- * ||||||||||
- * BL2_IGNORE_ADDR -> +--------+
- * | |
- * | 1 |
- * | |
- * COMPRESS_START_ADDR -> +--------+
- */
-#define CONFIG_DDR_TOTAL_SIZE (CONFIG_DDR_SIZE << 20)
-#define CONFIG_COMPRESSED_DATA_ADDR (0x10000000)
-#define CONFIG_COMPRESSED_DATA_ADDR1 (0x08000000)
-
-#define CONFIG_COMPRESS_START_ADDR (0x00000000)
-#define CONFIG_BL2_IGNORE_ADDR (0x05000000)
-#define CONFIG_BL2_IGNORE_SIZE (0x00300000)
-#define CONFIG_SEG4_ADDR (CONFIG_BL2_IGNORE_ADDR + \
- CONFIG_BL2_IGNORE_SIZE)
-
-enum {
- RAM_COMPRESS_NORMAL = 1,
- RAM_COMPRESS_COPY = 2,
- RAM_COMPRESS_SET = 3 /* set ram content to same vale */
-};
-
-struct ram_compress_section {
- void *phy_addr;
- unsigned int section_size;
- unsigned int section_index : 8;
- unsigned int compress_type : 8;
- unsigned int set_value : 16;
-};
-
-struct ram_compress_full {
- void *store_phy_addr;
- unsigned int full_memsize;
- unsigned int section_count;
- struct ram_compress_section sections[CONFIG_COMPRESS_SECTION];
-};
-
-#endif
-#endif /* __RAM_DUMP_H__ */
diff --git a/board/amlogic/sm1_elaine_b1/firmware/scp_task/dvfs_board.c b/board/amlogic/sm1_elaine_b1/firmware/scp_task/dvfs_board.c
deleted file mode 100755
index 943bc82..0000000
--- a/board/amlogic/sm1_elaine_b1/firmware/scp_task/dvfs_board.c
+++ /dev/null
@@ -1,194 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_b1/firmware/scp_task/dvfs_board.c
- *
- * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-/*
-int pwm_voltage_table[ ][2] = {
- { 0x1c0000, 860},
- { 0x1b0001, 870},
- { 0x1a0002, 880},
- { 0x190003, 890},
- { 0x180004, 900},
- { 0x170005, 910},
- { 0x160006, 920},
- { 0x150007, 930},
- { 0x140008, 940},
- { 0x130009, 950},
- { 0x12000a, 960},
- { 0x11000b, 970},
- { 0x10000c, 980},
- { 0x0f000d, 990},
- { 0x0e000e, 1000},
- { 0x0d000f, 1010},
- { 0x0c0010, 1020},
- { 0x0b0011, 1030},
- { 0x0a0012, 1040},
- { 0x090013, 1050},
- { 0x080014, 1060},
- { 0x070015, 1070},
- { 0x060016, 1080},
- { 0x050017, 1090},
- { 0x040018, 1100},
- { 0x030019, 1110},
- { 0x02001a, 1120},
- { 0x01001b, 1130},
- { 0x00001c, 1140}
-};
-*/
-#include "pwm_ctrl.h"
-
-#define CHIP_ADJUST 20
-#define RIPPLE_ADJUST 30
-struct scpi_opp_entry cpu_dvfs_tbl[] = {
- DVFS( 100000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS( 250000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS( 500000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1200000000, 940+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1296000000, 980+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1416000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
-};
-
-
-#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
-#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
-#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2))))
-
-#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2))))
-#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
-
-
-enum pwm_id {
- pwm_a = 0,
-};
-
-
-void pwm_init(int id)
-{
- /*
- * TODO: support more pwm controllers, right now only support PWM_B
- */
- unsigned int reg;
- reg = P_PWM_MISC_REG_AB;
- reg &= ~(0x7f << 8);
- reg |= ((1 << 15) | (1 << 0));
- P_PWM_MISC_REG_AB = reg;
- /*
- * default set to max voltage
- */
- //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
- reg = P_PIN_MUX_REG3;
- reg &= ~((1 << 21) | 1 << 12);
- P_PIN_MUX_REG3 = reg;
-
- reg = P_PIN_MUX_REG10;
- reg &= ~(1 << 16);
- P_PIN_MUX_REG10 = reg;//clear reg10
- reg = P_PIN_MUX_REG4;
- reg &= ~(1 << 26); // clear PWM_VS
- reg |= (1 << 17); // enable PWM_A
- P_PIN_MUX_REG4 = reg;
-
-
- _udelay(200);
-}
-
-int dvfs_get_voltage(void)
-{
- int i = 0;
- unsigned int reg_val;
-
- reg_val = P_PWM_PWM_A;
- for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
- if (pwm_voltage_table[i][0] == reg_val) {
- return i;
- }
- }
- if (i >= ARRAY_SIZE(pwm_voltage_table)) {
- return -1;
- }
- return -1;
-}
-
-void set_dvfs(unsigned int domain, unsigned int index)
-{
- int cur, to;
- static int init_flag = 0;
-
- if (!init_flag) {
- pwm_init(pwm_a);
- init_flag = 1;
- }
- cur = dvfs_get_voltage();
- for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
- if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
- break;
- }
- }
- if (to >= ARRAY_SIZE(pwm_voltage_table)) {
- to = ARRAY_SIZE(pwm_voltage_table) - 1;
- }
- if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
- P_PWM_PWM_A = pwm_voltage_table[to][0];
- _udelay(200);
- return ;
- }
- while (cur != to) {
- /*
- * if target step is far away from current step, don't change
- * voltage by one-step-done. You should change voltage step by
- * step to make sure voltage output is stable
- */
- if (cur < to) {
- if (cur < to - 3) {
- cur += 3;
- } else {
- cur = to;
- }
- } else {
- if (cur > to + 3) {
- cur -= 3;
- } else {
- cur = to;
- }
- }
- P_PWM_PWM_A = pwm_voltage_table[cur][0];
- _udelay(100);
- }
- _udelay(200);
-}
-void get_dvfs_info_board(unsigned int domain,
- unsigned char *info_out, unsigned int *size_out)
-{
- unsigned int cnt;
- cnt = ARRAY_SIZE(cpu_dvfs_tbl);
-
- buf_opp.latency = 200;
- buf_opp.count = cnt;
- memset(&buf_opp.opp[0], 0,
- MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
-
- memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
- cnt * sizeof(struct scpi_opp_entry));
-
- memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
- *size_out = sizeof(struct scpi_opp);
- return;
-}
diff --git a/board/amlogic/sm1_elaine_b1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/sm1_elaine_b1/firmware/scp_task/pwm_ctrl.h
deleted file mode 100755
index 8020e26..0000000
--- a/board/amlogic/sm1_elaine_b1/firmware/scp_task/pwm_ctrl.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
-*board/amlogic/sm1_elaine_b1/firmware/scp_task/pwm_vol_tab.h
-*table for Dynamic Voltage/Frequency Scaling
-*/
-#ifndef __PWM_CTRL_H__
-#define __PWM_CTRL_H__
-
-static int pwm_voltage_table_ee[][2] = {
- { 0x1c0000, 681},
- { 0x1b0001, 691},
- { 0x1a0002, 701},
- { 0x190003, 711},
- { 0x180004, 721},
- { 0x170005, 731},
- { 0x160006, 741},
- { 0x150007, 751},
- { 0x140008, 761},
- { 0x130009, 772},
- { 0x12000a, 782},
- { 0x11000b, 792},
- { 0x10000c, 802},
- { 0x0f000d, 812},
- { 0x0e000e, 822},
- { 0x0d000f, 832},
- { 0x0c0010, 842},
- { 0x0b0011, 852},
- { 0x0a0012, 862},
- { 0x090013, 872},
- { 0x080014, 882},
- { 0x070015, 892},
- { 0x060016, 902},
- { 0x050017, 912},
- { 0x040018, 922},
- { 0x030019, 932},
- { 0x02001a, 942},
- { 0x01001b, 952},
- { 0x00001c, 962}
-};
-
-#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/sm1_elaine_b1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/sm1_elaine_b1/firmware/scp_task/pwr_ctrl.c
deleted file mode 100755
index 1707e3f..0000000
--- a/board/amlogic/sm1_elaine_b1/firmware/scp_task/pwr_ctrl.c
+++ /dev/null
@@ -1,196 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_b1/firmware/scp_task/pwr_ctrl.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <gpio.h>
-#include "pwm_ctrl.h"
-#ifdef CONFIG_CEC_WAKEUP
-#include <cec_tx_reg.h>
-#endif
-
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
-static void set_vddee_voltage(unsigned int target_voltage)
-{
- unsigned int to;
-
- for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
- if (pwm_voltage_table_ee[to][1] >= target_voltage) {
- break;
- }
- }
-
- if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
- to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
- }
-
- writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
-}
-
-static void power_off_at_24M(unsigned int suspend_from)
-{
- /*set gpioH_8 low to power off vcc 5v*/
- writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
- writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
-
- /*set test_n low to power off vcck & vcc 3.3v*/
- writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
- writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
- writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
-
- /*step down ee voltage*/
- set_vddee_voltage(AML_VDDEE_SLEEP_VOLTAGE);
-}
-
-static void power_on_at_24M(unsigned int suspend_from)
-{
- /*step up ee voltage*/
- set_vddee_voltage(AML_VDDEE_INIT_VOLTAGE);
-
- /*set test_n low to power on vcck & vcc 3.3v*/
- writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
- writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
- writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
- _udelay(100);
-
- /*set gpioH_8 low to power on vcc 5v*/
- writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
- writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
- _udelay(10000);
-
-}
-
-void get_wakeup_source(void *response, unsigned int suspend_from)
-{
- struct wakeup_info *p = (struct wakeup_info *)response;
- struct wakeup_gpio_info *gpio;
- unsigned val;
- unsigned i = 0;
-
- p->status = RESPONSE_OK;
- val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
- ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC | ETH_PHY_GPIO_SRC
- | CECB_WAKEUP_SRC);
-
- p->sources = val;
-
- /* Power Key: AO_GPIO[3]*/
- gpio = &(p->gpio_info[i]);
- gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
- gpio->gpio_in_idx = GPIOAO_3;
- gpio->gpio_in_ao = 1;
- gpio->gpio_out_idx = -1;
- gpio->gpio_out_ao = -1;
- gpio->irq = IRQ_AO_GPIO0_NUM;
- gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
- p->gpio_info_count = ++i;
-
- /*Eth:GPIOZ_14*/
- gpio = &(p->gpio_info[i]);
- gpio->wakeup_id = ETH_PHY_GPIO_SRC;
- gpio->gpio_in_idx = GPIOZ_14;
- gpio->gpio_in_ao = 0;
- gpio->gpio_out_idx = -1;
- gpio->gpio_out_ao = -1;
- gpio->irq = IRQ_GPIO1_NUM;
- gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
- p->gpio_info_count = ++i;
-
- /*bt wake host*/
- gpio = &(p->gpio_info[i]);
- gpio->wakeup_id = BT_WAKEUP_SRC;
- gpio->gpio_in_idx = GPIOX_18;
- gpio->gpio_in_ao = 0;
- gpio->gpio_out_idx = -1;
- gpio->gpio_out_ao = -1;
- gpio->irq = IRQ_GPIO0_NUM;
- gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
- p->gpio_info_count = ++i;
-}
-extern void __switch_idle_task(void);
-
-static unsigned int detect_key(unsigned int suspend_from)
-{
- int exit_reason = 0;
- unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
- init_remote();
-#ifdef CONFIG_CEC_WAKEUP
- if (hdmi_cec_func_config & 0x1) {
- remote_cec_hw_reset();
- cec_node_init();
- }
-#endif
-
- do {
- #ifdef CONFIG_CEC_WAKEUP
- if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
- irq[IRQ_AO_CECB] = 0xFFFFFFFF;
- if (cec_power_on_check())
- exit_reason = CEC_WAKEUP;
- }
- #endif
- if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
- irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
- if (remote_detect_key())
- exit_reason = REMOTE_WAKEUP;
- }
-
- if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) {
- irq[IRQ_VRTC] = 0xFFFFFFFF;
- exit_reason = RTC_WAKEUP;
- }
-
- if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
- irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
- if ((readl(AO_GPIO_I) & (1<<3)) == 0)
- exit_reason = POWER_KEY_WAKEUP;
- }
-#if 0
- if (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM) {
- irq[IRQ_GPIO1] = 0xFFFFFFFF;
- if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 14))
- && (readl(PREG_PAD_GPIO4_EN_N) & (0x01 << 14)))
- exit_reason = ETH_PHY_GPIO;
- }
-#endif
- if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
- irq[IRQ_GPIO0] = 0xFFFFFFFF;
- if (!(readl(PREG_PAD_GPIO2_I) & (0x01 << 18))
- && (readl(PREG_PAD_GPIO2_O) & (0x01 << 17))
- && !(readl(PREG_PAD_GPIO2_EN_N) & (0x01 << 17)))
- exit_reason = BT_WAKEUP;
- }
-
- if (exit_reason)
- break;
- else
- __switch_idle_task();
- } while (1);
-
- return exit_reason;
-}
-
-static void pwr_op_init(struct pwr_op *pwr_op)
-{
- pwr_op->power_off_at_24M = power_off_at_24M;
- pwr_op->power_on_at_24M = power_on_at_24M;
- pwr_op->detect_key = detect_key;
- pwr_op->get_wakeup_source = get_wakeup_source;
-}
diff --git a/board/amlogic/sm1_elaine_b1/firmware/timing.c b/board/amlogic/sm1_elaine_b1/firmware/timing.c
deleted file mode 100755
index 87a2ad0..0000000
--- a/board/amlogic/sm1_elaine_b1/firmware/timing.c
+++ /dev/null
@@ -1,462 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_b1/firmware/timing.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/timing.h>
-#include <asm/arch/ddr_define.h>
-
-/* board clk defines */
-#define DDR_SIZE 0
-#define CPU_CLK 1200
-
-/* ddr config support multiple configs for boards which use same bootloader:
- * config steps:
- * 1. add a new data struct in __ddr_setting[]
- * 2. config correct board_id, ddr_type, freq, etc..
- */
-
-
-/* CAUTION!! */
-/* Confirm ddr configs with hardware designer,
- * if you don't know how to config, then don't edit it
- */
-
-/* Key configs */
-/*
- * board_id: check hardware adc config
- * dram_rank_config:
- * #define CONFIG_DDR_CHL_AUTO 0xF
- * #define CONFIG_DDR0_16BIT_CH0 0x1
- * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
- * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
- * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
- * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
- * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
- * DramType:
- * #define CONFIG_DDR_TYPE_DDR3 0
- * #define CONFIG_DDR_TYPE_DDR4 1
- * #define CONFIG_DDR_TYPE_LPDDR4 2
- * #define CONFIG_DDR_TYPE_LPDDR3 3
- * DRAMFreq:
- * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
- *
- */
-
-
-/* ddr configs */
-#define DDR_RFC_TYPE_DDR3_512Mbx1 0
-#define DDR_RFC_TYPE_DDR3_512Mbx2 1
-#define DDR_RFC_TYPE_DDR3_512Mbx4 2
-#define DDR_RFC_TYPE_DDR3_512Mbx8 3
-#define DDR_RFC_TYPE_DDR3_512Mbx16 4
-#define DDR_RFC_TYPE_DDR4_2Gbx1 5
-#define DDR_RFC_TYPE_DDR4_2Gbx2 6
-#define DDR_RFC_TYPE_DDR4_2Gbx4 7
-#define DDR_RFC_TYPE_DDR4_2Gbx8 8
-
-#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
-#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
-#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
-
-#if CONFIG_DDR_LOGS_ENABLED
-#define LOG_FLAG 0x4
-#else
-#define LOG_FLAG 0xA
-#endif
-
-ddr_set_t __ddr_setting[] = {
- {
- /* Elaine ddr3 */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
- .DramType = CONFIG_DDR_TYPE_DDR3,
- .DRAMFreq = {912, 0, 0, 0},
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 1,
- .HdtCtrl = LOG_FLAG,
- .dram_cs0_size_MB = 1024,
- .dram_cs1_size_MB = 1024,
- .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .clk_drv_ohm = 40,
- .cs_drv_ohm = 40,
- .ac_drv_ohm = 40,
- .soc_data_drv_ohm_p = 34,
- .soc_data_drv_ohm_n = 34,
- .soc_data_odt_ohm_p = 60, //48,
- .soc_data_odt_ohm_n = 0,
- .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
- .dram_data_odt_ohm = 60,
- .dram_ac_odt_ohm = 0,
- .soc_clk_slew_rate = 0x300,
- .soc_cs_slew_rate = 0x300,
- .soc_ac_slew_rate = 0x300,
- .soc_data_slew_rate = 0x200,
- .vref_output_permil = 500,
- .vref_receiver_permil = 500, //700,
- .vref_dram_permil = 500, //700,
-// .vref_reverse = 0,
- .ac_trace_delay ={32,32,32,32,32,32,32,32,32,32},
- //{00,00},
- .ac_pinmux = {00,00},
-#if 1
- .ddr_dmc_remap = {
- [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
- [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
- },
-#else
- //16bit
- .ddr_dmc_remap = {
- [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
- [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
- [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
- [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
- },
-#endif
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap = {00,00},
- .dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
- .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
-},
-{
- /* g12a skt (u209) ddr3 */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
- .DramType = CONFIG_DDR_TYPE_DDR3,
- .DRAMFreq = {912, 0, 0, 0},
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 1,
- .HdtCtrl = LOG_FLAG,
- .dram_cs0_size_MB = 1024,
- .dram_cs1_size_MB = 512,
- .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .pll_ssc_mode = 0,
- .clk_drv_ohm = 40,
- .cs_drv_ohm = 40,
- .ac_drv_ohm = 40,
- .soc_data_drv_ohm_p = 34,
- .soc_data_drv_ohm_n = 34,
- .soc_data_odt_ohm_p = 60, //48,
- .soc_data_odt_ohm_n = 0,
- .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
- .dram_data_odt_ohm = 60,
- .dram_ac_odt_ohm = 0,
- .soc_clk_slew_rate = 0x300,
- .soc_cs_slew_rate = 0x300,
- .soc_ac_slew_rate = 0x300,
- .soc_data_slew_rate = 0x200,
- .vref_output_permil = 500,
- .vref_receiver_permil = 500, //700,
- .vref_dram_permil = 500, //700,
- //{00,00},
- .ac_pinmux = {00,00},
-#if 1
- .ddr_dmc_remap = {
- [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
- [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
- },
-#else
- //16bit
- .ddr_dmc_remap = {
- [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
- [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
- [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
- [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
- },
-#endif
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap = {00,00},
- .dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
- .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
- .slt_test_function = {DMC_TEST_SLT_ENABLE_DDR_SKIP_TRAINING, 0},
- .dfi_hwtmrl = 4,
-
- .ac_trace_delay = {
- 32, 32, 32, 32,
- 32, 32, 32, 32,
- 32, 32,
- },
-
- .write_dqs_delay = {
- 163, 163, 163, 163,
- 167, 167, 165, 165,
- 159, 159, 163, 163,
- 165, 165, 161, 161,
- },
-
- .read_dqs_delay = {
- 13, 13, 14, 14,
- 14, 14, 15, 14,
- 14, 14, 14, 15,
- 14, 13, 14, 14,
- },
-
- .write_dq_bit_delay = {
- 20, 21, 19, 21,
- 21, 21, 22, 20,
- 22, 21, 20, 20,
- 19, 21, 18, 21,
- 20, 20, 24, 20,
- 22, 25, 24, 25,
- 26, 26, 23, 20,
- 21, 20, 23, 21,
- 21, 23, 23, 20,
- 48, 49, 48, 50,
- 50, 50, 51, 49,
- 49, 21, 21, 19,
- 20, 21, 19, 20,
- 21, 20, 22, 18,
- 20, 23, 23, 24,
- 24, 24, 22, 17,
- 18, 17, 20, 18,
- 18, 21, 20, 19,
- },
-
- .read_dq_bit_delay = {
- 15, 15, 15, 23,
- 31, 31, 31, 29,
- 0 , 23, 19, 11,
- 17, 35, 23, 31,
- 31, 0 , 15, 3 ,
- 9 , 15, 27, 27,
- 35, 35, 0 , 13,
- 15, 11, 19, 25,
- 19, 31, 31, 0 ,
- 15, 17, 15, 19,
- 31, 33, 31, 27,
- 0 , 19, 19, 15,
- 13, 31, 23, 27,
- 31, 0 , 13, 3 ,
- 5 , 11, 23, 27,
- 31, 27, 0 , 13,
- 13, 9 , 19, 23,
- 23, 27, 27, 0 ,
- },
-
- .read_dqs_gate_delay = {
- 225, 227, 223, 225,
- 223, 225, 223, 227,
- 223, 225, 223, 225,
- 225, 227, 227, 229,
- },
-
-},
-};
-
-pll_set_t __pll_setting = {
- .cpu_clk = CPU_CLK / 24 * 24,
-#ifdef CONFIG_PXP_EMULATOR
- .pxp = 1,
-#else
- .pxp = 0,
-#endif
- .spi_ctrl = 0,
- .lCustomerID = AML_CUSTOMER_ID,
-#ifdef CONFIG_DEBUG_MODE
- .debug_mode = CONFIG_DEBUG_MODE,
- .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
- .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
-#endif
-};
-
-ddr_reg_t __ddr_reg[] = {
- /* demo, user defined override register */
- {0xaabbccdd, 0, 0, 0, 0, 0},
- {0x11223344, 0, 0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0},
-};
-
-#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
-#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
-/* VCCK PWM table */
-#if (VCCK_VAL == 800)
- #define VCCK_VAL_REG 0x00150007
-#elif (VCCK_VAL == 810)
- #define VCCK_VAL_REG 0x00140008
-#elif (VCCK_VAL == 820)
- #define VCCK_VAL_REG 0x00130009
-#elif (VCCK_VAL == 830)
- #define VCCK_VAL_REG 0x0012000a
-#elif (VCCK_VAL == 840)
- #define VCCK_VAL_REG 0x0011000b
-#elif (VCCK_VAL == 850)
- #define VCCK_VAL_REG 0x0010000c
-#elif (VCCK_VAL == 860)
- #define VCCK_VAL_REG 0x000f000d
-#elif (VCCK_VAL == 870)
- #define VCCK_VAL_REG 0x000e000e
-#elif (VCCK_VAL == 880)
- #define VCCK_VAL_REG 0x000d000f
-#elif (VCCK_VAL == 890)
- #define VCCK_VAL_REG 0x000c0010
-#elif (VCCK_VAL == 900)
- #define VCCK_VAL_REG 0x000b0011
-#elif (VCCK_VAL == 910)
- #define VCCK_VAL_REG 0x000a0012
-#elif (VCCK_VAL == 920)
- #define VCCK_VAL_REG 0x00090013
-#elif (VCCK_VAL == 930)
- #define VCCK_VAL_REG 0x00080014
-#elif (VCCK_VAL == 940)
- #define VCCK_VAL_REG 0x00070015
-#elif (VCCK_VAL == 950)
- #define VCCK_VAL_REG 0x00060016
-#elif (VCCK_VAL == 960)
- #define VCCK_VAL_REG 0x00050017
-#elif (VCCK_VAL == 970)
- #define VCCK_VAL_REG 0x00040018
-#elif (VCCK_VAL == 980)
- #define VCCK_VAL_REG 0x00030019
-#elif (VCCK_VAL == 990)
- #define VCCK_VAL_REG 0x0002001a
-#elif (VCCK_VAL == 1000)
- #define VCCK_VAL_REG 0x0001001b
-#elif (VCCK_VAL == 1010)
- #define VCCK_VAL_REG 0x0000001c
-#else
- #error "VCCK val out of range\n"
-#endif
-
-/* VDDEE PWM table */
-#if (VDDEE_VAL == 800)
- #define VDDEE_VAL_REG 0x0010000c
-#elif (VDDEE_VAL == 810)
- #define VDDEE_VAL_REG 0x000f000d
-#elif (VDDEE_VAL == 820)
- #define VDDEE_VAL_REG 0x000e000e
-#elif (VDDEE_VAL == 830)
- #define VDDEE_VAL_REG 0x000d000f
-#elif (VDDEE_VAL == 840)
- #define VDDEE_VAL_REG 0x000c0010
-#elif (VDDEE_VAL == 850)
- #define VDDEE_VAL_REG 0x000b0011
-#elif (VDDEE_VAL == 860)
- #define VDDEE_VAL_REG 0x000a0012
-#elif (VDDEE_VAL == 870)
- #define VDDEE_VAL_REG 0x00090013
-#elif (VDDEE_VAL == 880)
- #define VDDEE_VAL_REG 0x00080014
-#elif (VDDEE_VAL == 890)
- #define VDDEE_VAL_REG 0x00070015
-#elif (VDDEE_VAL == 900)
- #define VDDEE_VAL_REG 0x00060016
-#elif (VDDEE_VAL == 910)
- #define VDDEE_VAL_REG 0x00050017
-#elif (VDDEE_VAL == 920)
- #define VDDEE_VAL_REG 0x00040018
-#elif (VDDEE_VAL == 930)
- #define VDDEE_VAL_REG 0x00030019
-#elif (VDDEE_VAL == 940)
- #define VDDEE_VAL_REG 0x0002001a
-#elif (VDDEE_VAL == 950)
- #define VDDEE_VAL_REG 0x0001001b
-#elif (VDDEE_VAL == 960)
- #define VDDEE_VAL_REG 0x0000001c
-#else
- #error "VDDEE val out of range\n"
-#endif
-
-/* for PWM use */
-/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
-#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
-#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
-#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
-#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
-#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
-
-bl2_reg_t __bl2_reg[] = {
- /* demo, user defined override register */
- /* eg: PWM init */
-
- /* PWM_AO_D */
- /* VCCK_VAL_REG: check PWM table */
- {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
- {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
- /* PWM_AO_B */
- /* VDDEE_VAL_REG: check PWM table */
- {AO_PWM_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
- {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_1, 0},
- /* Enable 5V_EN */
- {GPIO_O_EN_N_REG3, (0 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
- {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- /* Enable VCCK */
- {AO_SEC_REG0, (1 << 0), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- {AO_GPIO_O, 0x80000000, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
-};
diff --git a/board/amlogic/sm1_elaine_b1/lcd.c b/board/amlogic/sm1_elaine_b1/lcd.c
deleted file mode 100755
index a0d6847..0000000
--- a/board/amlogic/sm1_elaine_b1/lcd.c
+++ /dev/null
@@ -1,422 +0,0 @@
-/*
- * AMLOGIC TV LCD panel driver.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#ifdef CONFIG_AML_LCD_EXTERN
-#include "lcd_extern.h"
-#endif
-
-static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
- "GPIOH_6", /* panel rst */
- "GPIOZ_8", /* panel power */
- "invalid", /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step[] = {
- {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
- {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,50,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
- {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_on_step_KD070D82[] = {
- {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_KD070D82[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
- 0x05, 1, 0x11,
- 0xfd, 1, 20,
- 0x05, 1, 0x29,
- 0xfd, 1, 20,
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
- 0x05, 1, 0x28,
- 0xfd, 1, 10,
- 0x05, 1, 0x10,
- 0xfd, 1, 10,
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
- 0xfd, 1, 10,
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
- 0xff, 0, //ending
-};
-
-static unsigned char mipi_init_on_table_KD070D82[DSI_INIT_ON_MAX] = {//table size < 100
- 0xfd, 1, 10,
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_KD070D82[DSI_INIT_OFF_MAX] = {//table size < 50
- 0xff, 0, //ending
-};
-
-static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
- "GPIOH_4", /* BL_EN */
- "GPIOH_5", /* BL_PWM */
- "invalid", /* ending flag */
-};
-
-struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
- {/* TV070WSM_FT9364*/
- "boe_fiti9364_7",LCD_MIPI,8,
- /* basic timing */
- 600,1024,700,1053,24,36,0,2,8,0,
- /* clk_attr */
- 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,360,0,1,0,2,0,0,Rsv_val,3,
- /* cmd init */
- mipi_init_on_table, mipi_init_off_table,
- /* power step */
- lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* P070ACB_FT9364*/
- "inx_fiti9364_7",LCD_MIPI,8,
- /* basic timing */
- 600,1024,770,1070,10,80,0,6,20,0,
- /* clk_attr */
- 0,0,1,49434000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,400,0,1,0,2,0,0,Rsv_val,1,
- /* cmd init */
- mipi_init_on_table_P070ACB, mipi_init_off_table_P070ACB,
- /* power step */
- lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* KD070D82_FT9364*/
- "kd_fiti9364_7",LCD_MIPI,8,
- /* basic timing */
- 600,1024,770,1070,10,80,0,6,20,0,
- /* clk_attr */
- 0,0,1,49434000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,400,0,1,0,2,0,0,Rsv_val,2,
- /* cmd init */
- mipi_init_on_table_KD070D82, mipi_init_off_table_KD070D82,
- /* power step */
- lcd_power_on_step_KD070D82, lcd_power_off_step_KD070D82,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {.panel_type = "invalid"},
-};
-
-static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
- {
- .name = "lcd_pin",
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
- },
- {
- .name = "invalid",
- },
-};
-
-static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
- {
- .name = "bl_pwm_on_pin", //GPIOH_5
- .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
- },
- {
- .name = "invalid",
- },
-};
-
-#ifdef CONFIG_AML_BL_EXTERN
-static unsigned char bl_ext_init_on[BL_EXTERN_INIT_ON_MAX] = {
- 0xff, 0, //ending flag
-};
-static unsigned char bl_ext_init_off[BL_EXTERN_INIT_OFF_MAX] = {
- 0xff, 0, //ending flag
-};
-#endif
-
-/* **********************************************
- * driver struct, usually no need modify!
- * ********************************************** */
-static struct dsi_config_s lcd_mipi_config = {
- .lane_num = 4,
- .bit_rate_max = 1000, /* MHz */
- .factor_numerator = 0,
- .factor_denominator = 100,
- .operation_mode_init = 1, /* 0=video mode, 1=command mode */
- .operation_mode_display = 0, /* 0=video mode, 1=command mode */
- .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
- .clk_always_hs = 1, /* 0=disable, 1=enable */
- .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
-
- .dsi_init_on = mipi_init_on_table,
- .dsi_init_off = mipi_init_off_table,
- .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
- .check_en = 0,
- .check_state = 0,
-};
-
-static struct lcd_power_ctrl_s lcd_power_ctrl = {
- .power_on_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
- .power_off_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
-};
-
-struct lcd_config_s lcd_config_dft = {
- .lcd_mode = LCD_MODE_TABLET,
- .lcd_key_valid = 0,
- .lcd_clk_path = 0,
- .lcd_basic = {
- .model_name = "default",
- .lcd_type = LCD_TYPE_MAX,
- .lcd_bits = 8,
- .h_active = 768,
- .v_active = 1024,
- .h_period = 948,
- .v_period = 1140,
-
- .screen_width = 119,
- .screen_height = 159,
- },
-
- .lcd_timing = {
- .clk_auto = 1,
- .lcd_clk = 64843200,
- .ss_level = 0,
- .fr_adjust_type = 0,
-
- .hsync_width = 64,
- .hsync_bp = 56,
- .hsync_pol = 0,
- .vsync_width = 50,
- .vsync_bp = 30,
- .vsync_pol = 0,
- },
-
- .lcd_control = {
- .mipi_config= &lcd_mipi_config,
- },
- .lcd_power = &lcd_power_ctrl,
-
- .pinctrl_ver = 2,
- .lcd_pinmux = lcd_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_LCD_EXTERN
-struct lcd_extern_common_s ext_common_dft = {
- .lcd_ext_key_valid = 0,
- .i2c_bus = LCD_EXTERN_I2C_BUS_0, /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
- .i2c_gpio_sck = LCD_EXT_I2C_GPIO_SCK,
- .i2c_gpio_sda = LCD_EXT_I2C_GPIO_SDA,
- .spi_gpio_cs = LCD_EXT_SPI_GPIO_CS,
- .spi_gpio_clk = LCD_EXT_SPI_GPIO_CLK,
- .spi_gpio_data = LCD_EXT_SPI_GPIO_DATA,
-
- .lcd_ext_pinmux = lcd_ext_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
- .pinmux_gpio_off = LCD_EXT_PINMUX_GPIO_OFF,
-};
-
-struct lcd_extern_config_s ext_config_dtf = {
- .index = 0,
- .name = "ext_default",
- .type = LCD_EXTERN_MAX, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 0, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
-};
-#endif
-
-struct bl_config_s bl_config_dft = {
- .name = "default",
- .bl_key_valid = 0,
-
- .level_default = 100,
- .level_min = 10,
- .level_max = 255,
- .level_mid = 128,
- .level_mid_mapping = 128,
- .level = 0,
-
- .method = BL_CTRL_MAX,
- .power_on_delay = 20,
- .power_off_delay = 20,
-
- .en_gpio = 0xff,
- .en_gpio_on = 1,
- .en_gpio_off = 0,
-
- .bl_pwm = NULL,
- .bl_pwm_combo0 = NULL,
- .bl_pwm_combo1 = NULL,
- .pwm_on_delay = 10,
- .pwm_off_delay = 10,
-
- .bl_extern_index = 0xff,
-
- .pinctrl_ver = 2,
- .bl_pinmux = bl_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_BL_EXTERN
-struct bl_extern_config_s bl_extern_config_dtf = {
- .index = BL_EXTERN_INDEX_INVALID,
- .name = "none",
- .type = BL_EXTERN_MAX,
- .i2c_addr = 0xff,
- .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
- .dim_min = 10,
- .dim_max = 255,
-
- .init_loaded = 0,
- .cmd_size = 0xff,
- .init_on = bl_ext_init_on,
- .init_off = bl_ext_init_off,
- .init_on_cnt = sizeof(bl_ext_init_on),
- .init_off_cnt = sizeof(bl_ext_init_off),
-};
-#endif
-/* ********************************************** */
-
-void lcd_config_bsp_init(void)
-{
- int i, j;
- char *str;
- struct ext_lcd_config_s *ext_lcd = NULL;
-
- /* init config, usually no need modify */
- for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
- break;
- strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
- }
- for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
- strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
- for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
- break;
- strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
- }
- for (j = i; j < BL_GPIO_NUM_MAX; j++)
- strcpy(bl_config_dft.gpio_name[j], "invalid");
-
-#ifdef CONFIG_AML_LCD_EXTERN
- for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
- break;
- strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
- }
- for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
- strcpy(ext_common_dft.gpio_name[j], "invalid");
-#endif
-
- /* select special config */
- str = env_get("panel_type");
- if (str == NULL)
- return;
- for (i = 0 ; i < LCD_NUM_MAX ; i++) {
- ext_lcd = &ext_lcd_config[i];
- if (strcmp(ext_lcd->panel_type, str) == 0) {
-#ifdef CONFIG_AML_LCD_EXTERN
- j = ext_lcd->if_attr_val9; /* mipi extern_index */
- if (j < sizeof(ext_config)/sizeof(struct lcd_extern_config_s)) {
- memcpy(&ext_config_dtf, &ext_config[j],
- sizeof(struct lcd_extern_config_s));
- }
-#endif
- break;
- }
- }
-}
diff --git a/board/amlogic/sm1_elaine_b1/lcd_extern.h b/board/amlogic/sm1_elaine_b1/lcd_extern.h
deleted file mode 100755
index 4f50120..0000000
--- a/board/amlogic/sm1_elaine_b1/lcd_extern.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * board/amlogic/sm1_elaine_b1/lcd_extern.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _DFT_LCD_EXTERN_H_
-#define _DFT_LCD_EXTERN_H_
-
-#define LCD_EXT_I2C_GPIO_SCK 0xff /* 0xff for invalid */
-#define LCD_EXT_I2C_GPIO_SDA 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_CS 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_CLK 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_DATA 0xff /* 0xff for invalid */
-#define LCD_EXT_PINMUX_GPIO_OFF 0
-
-static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
- "invalid", /* ending flag */
-};
-
-static struct lcd_pinmux_ctrl_s lcd_ext_pinmux_ctrl[LCD_PINMX_MAX] = {
- {
- .name = "invalid",
- },
-};
-
-static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
- 0xff, 0, //ending flag
-};
-
-static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
- 0xff, 0, //ending flag
-};
-
-static struct lcd_extern_config_s ext_config[LCD_EXTERN_NUM_MAX] = {
- {
- .index = 0,
- .name = "ext_default",
- .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 0, /* 0=disable, 1=enable */
- .i2c_addr = 0x1c, /* 7bit i2c address */
- .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for invalid */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- { /* P070ACB_FT9364 */
- .index = 1,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- /*we define initial codes in panel.dtsi*/
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- { /* KD070D82_FT9364*/
- .index = 2,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- /*we define initial codes in panel.dtsi*/
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- { /* TV070WSM_FT9364*/
- .index = 3,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- /*we define initial codes in panel.dtsi*/
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- {
- .index = LCD_EXTERN_INDEX_INVALID,
- },
-};
-
-#endif
-
diff --git a/board/amlogic/sm1_elaine_b1/pwm_table.c b/board/amlogic/sm1_elaine_b1/pwm_table.c
deleted file mode 100755
index 18dc638..0000000
--- a/board/amlogic/sm1_elaine_b1/pwm_table.c
+++ /dev/null
@@ -1,71 +0,0 @@
-#include <common.h>
-
-const int pwm_cal_voltage_table[][2] = {
- { 0x1c0000, 860},
- { 0x1b0001, 870},
- { 0x1a0002, 880},
- { 0x190003, 890},
- { 0x180004, 900},
- { 0x170005, 910},
- { 0x160006, 920},
- { 0x150007, 930},
- { 0x140008, 940},
- { 0x130009, 950},
- { 0x12000a, 960},
- { 0x11000b, 970},
- { 0x10000c, 980},
- { 0x0f000d, 990},
- { 0x0e000e, 1000},
- { 0x0d000f, 1010},
- { 0x0c0010, 1020},
- { 0x0b0011, 1030},
- { 0x0a0012, 1040},
- { 0x090013, 1050},
- { 0x080014, 1060},
- { 0x070015, 1070},
- { 0x060016, 1080},
- { 0x050017, 1090},
- { 0x040018, 1100},
- { 0x030019, 1110},
- { 0x02001a, 1120},
- { 0x01001b, 1130},
- { 0x00001c, 1140}
-};
-const int pwm_cal_voltage_table_ee[][2] = {
- { 0x1c0000, 810},
- { 0x1b0001, 820},
- { 0x1a0002, 830},
- { 0x190003, 840},
- { 0x180004, 850},
- { 0x170005, 860},
- { 0x160006, 870},
- { 0x150007, 880},
- { 0x140008, 890},
- { 0x130009, 900},
- { 0x12000a, 910},
- { 0x11000b, 920},
- { 0x10000c, 930},
- { 0x0f000d, 940},
- { 0x0e000e, 950},
- { 0x0d000f, 960},
- { 0x0c0010, 970},
- { 0x0b0011, 980},
- { 0x0a0012, 990},
- { 0x090013, 1000},
- { 0x080014, 1010},
- { 0x070015, 1020},
- { 0x060016, 1030},
- { 0x050017, 1040},
- { 0x040018, 1050},
- { 0x030019, 1060},
- { 0x02001a, 1070},
- { 0x01001b, 1080},
- { 0x00001c, 1090}
-};
-
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
-int pwm_cal_voltage_table_size = ARRAY_SIZE(pwm_cal_voltage_table);
-int pwm_cal_voltage_table_ee_size = ARRAY_SIZE(pwm_cal_voltage_table_ee);
-
-
diff --git a/board/amlogic/sm1_elaine_b1/sm1_elaine_b1.c b/board/amlogic/sm1_elaine_b1/sm1_elaine_b1.c
deleted file mode 100755
index 60620de..0000000
--- a/board/amlogic/sm1_elaine_b1/sm1_elaine_b1.c
+++ /dev/null
@@ -1,1165 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_b1/sm1_elaine_b1.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <malloc.h>
-#include <errno.h>
-#include <environment.h>
-#include <fdt_support.h>
-#include <linux/libfdt.h>
-#include <asm/arch/cpu_id.h>
-#ifdef CONFIG_SYS_I2C_MESON
-#include <i2c.h>
-#include <dt-bindings/i2c/meson-i2c.h>
-#endif
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/pinctrl_init.h>
-#ifdef CONFIG_AML_VPU
-#include <amlogic/media/vpu/vpu.h>
-#endif
-#ifdef CONFIG_AML_VPP
-#include <amlogic/media/vpp/vpp.h>
-#endif
-#ifdef CONFIG_AML_V2_FACTORY_BURN
-#include <amlogic/aml_v2_burning.h>
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
-#ifdef CONFIG_AML_HDMITX
-#include <amlogic/media/vout/hdmitx.h>
-#endif
-#ifdef CONFIG_AML_LCD
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#endif
-#include <asm/arch/bl31_apis.h>
-#include <asm/arch/eth_setup.h>
-#include <phy.h>
-#include <linux/mtd/partitions.h>
-#include <linux/sizes.h>
-#include <asm-generic/gpio.h>
-#include <dm.h>
-#ifdef CONFIG_AML_SPIFC
-#include <amlogic/spifc.h>
-#endif
-#ifdef CONFIG_AML_SPICC
-#include <amlogic/spicc.h>
-#endif
-#include <asm/armv8/mmu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int persistent_brightness = -1;
-
-int do_check_fdr_for_backlight_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-#if defined(CONFIG_NAND_FTS) || defined(CONFIG_MMC_FTS)
-#if defined(CONFIG_NAND_FTS)
- extern bool amlnf_is_inited(void);
- if(!amlnf_is_inited()) {
-#endif
-
-#if defined(CONFIG_MMC_FTS)
- extern bool amlmmc_is_inited(void);
- if (!amlmmc_is_inited()) {
-#endif
-
- return 0;
- }
-
- flash_ts_init();
-
- static const char *fts_key = "bootloader.recovery";
- static const char *fdr = "--wipe_data";
- static const int fdr_len = sizeof(fdr) - 1;
- int i;
-
- char fts_value[256] = { 0 };
- flash_ts_get(fts_key, fts_value, sizeof(fts_value));
- int fts_len = strnlen(fts_value, sizeof(fts_value));
- for (i = 0; i <= fts_len - fdr_len; i++) {
- if (0 == strncmp(fts_value+i, fdr, fdr_len)) {
- printf("Reset persistent brightness.\n");
- writel(0, AO_RTI_STICKY_REG2);
- break;
- }
- }
-#endif
-
- return 0;
-}
-
-U_BOOT_CMD(
- check_fdr_for_backlight_brightness, 1, 0, do_check_fdr_for_backlight_brightness,
- "check FDR for backlight brightness",
- " This command will clear backlight brightness level stored in the sticky register when doing FDR\n"
-);
-
-int serial_set_pin_port(unsigned long port_base)
-{
- //UART in "Always On Module"
- //GPIOAO_0==tx,GPIOAO_1==rx
- //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
- return 0;
-}
-
-//SOC_VDDCPU_DVFS0
-//#define VDD_CPU_DVFS0_EN_1 GPIOEE(GPIOZ_13)
-#define VDD_CPU_DVFS0_EN_1_NAME "GPIOZ_13"
-
-//SOC_VDDEE_DVFS0
-//#define VDD_GPU_DVFS0_EN_1 GPIOEE(GPIOA_13)
-#define VDD_GPU_DVFS0_EN_1_NAME "GPIOA_13"
-
-//SOC_VDDEE_DVFS1
-//#define VDD_GPU_DVFS1_EN_1 GPIOEE(GPIOZ_0)
-#define VDD_GPU_DVFS1_EN_1_NAME "GPIOZ_0"
-
-/* setting gpio output/input, and setting High/low level */
-static void gpio_func_set(bool enable, const char* gpio_name, int direction)
-{
- int ret;
- struct gpio_desc gpio_set_desc;
-
- ret = dm_gpio_lookup_name(gpio_name, &gpio_set_desc);
- if (ret) {
- printf("%s: not found\n", gpio_name);
- return ret;
- }
-
- ret = dm_gpio_request(&gpio_set_desc, gpio_name);
- if (ret && ret != -EBUSY) {
- printf("gpio: requesting pin %s failed\n", gpio_name);
- return;
- }
- //gpio_direction_output(BL_ENABLE_PIN, enable ? 1 : 0);
- ret = dm_gpio_set_dir_flags(&gpio_set_desc, direction);
- if (ret) {
- printf("set direction failed\n");
- return ret;
- }
-
- if ( direction == GPIOD_IS_OUT)
- dm_gpio_set_value(&gpio_set_desc, enable ? 1 : 0);
-}
-static void CPU_GPU_Voltage_init(void)
-{
- int ret;
- // setting GPIOZ_13 output & High
- gpio_func_set(1, VDD_CPU_DVFS0_EN_1_NAME, GPIOD_IS_OUT);
-
- //GPU , setting GPIOA_13 output & low
- gpio_func_set(0, VDD_GPU_DVFS0_EN_1_NAME, GPIOD_IS_OUT);
-
- // setting GPIOZ_0 output & low
- gpio_func_set(1, VDD_GPU_DVFS1_EN_1_NAME, GPIOD_IS_OUT);
-}
-
-// Disable GPIOZ_2, GPIOZ_3, GPIOZ_7, GPIOZ_8, GPIOZ_0, GPIOAO_4's pull-up
-// so the mute switch and HW id can be read.
-static void gpio_disable_pull(void)
-{
- int ret;
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 2)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 7)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 8)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 3)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(AO_RTI_PULL_UP_EN_REG);
- writel(ret & (~(1 << 4)), AO_RTI_PULL_UP_EN_REG);
-}
-
-int do_get_elaine_hw_id(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- unsigned int hw_id = 0, ret = 0;
- char hw_id_str[8] = {0}; // eg: 0x0A
-
- // Reading from highest bit to lowest bit
- // HW_ID_4: GPIOAO_4
- ret = readl(P_AO_GPIO_I);
- hw_id |= (ret & (1<<4)) >> 4;
- hw_id = hw_id << 1;
-
- // HW_ID_3: GPIOZ_0
- ret = readl(P_PREG_PAD_GPIO4_I);
- hw_id |= (ret & 1);
- hw_id = hw_id << 1;
-
- // HW_ID_2: GPIOZ_3
- ret = readl(P_PREG_PAD_GPIO4_I);
- hw_id |= (ret & (1<<3)) >> 3;
- hw_id = hw_id << 1;
-
- // HW_ID_1: GPIOZ_8
- ret = readl(P_PREG_PAD_GPIO4_I);
- hw_id |= (ret & (1<<8)) >> 8;
- hw_id = hw_id << 1;
-
- // HW_ID_0: GPIOZ_7
- ret = readl(P_PREG_PAD_GPIO4_I);
- hw_id |= (ret & (1<<7)) >> 7;
-
- snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id);
- env_set("hw_id", hw_id_str);
- return 0;
-}
-
-U_BOOT_CMD(
- get_elaine_hw_id, 1, 0, do_get_elaine_hw_id,
- "get elaine's HW_ID and env_set 'hw_id'\n",
- "get_elaine_hw_id"
-);
-
-#define BOOST_ENABLE_PIN_NAME "GPIOA_0"
-int do_enable_amp_boost(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- gpio_func_set(1, BOOST_ENABLE_PIN_NAME, GPIOD_IS_OUT);
-}
-
-U_BOOT_CMD(
- enable_amp_boost, 1, 0, do_enable_amp_boost,
- "Enable the audio amplifier boost\n",
- "enable_boost"
-);
-
-//SOC_DISP_ID
-//#define DISP_ID_PIN GPIOEE(GPIOH_5)
-#define DISP_ID_PIN_NAME "GPIOH_5"
-
-static void panel_detect_init(void)
-{
- // setting GPIOH_5 output & High
- gpio_func_set(1, DISP_ID_PIN_NAME, GPIOD_IS_IN);
-}
-
-//SOC_BL_ENABLE
-//#define BL_ENABLE_PIN GPIOEE(GPIOA_10)
-#define BL_ENABLE_PIN_NAME "GPIOA_10"
-
-static void enable_backlight(bool enable)
-{
- // setting GPIOH_5 output & High
- gpio_func_set(enable, BL_ENABLE_PIN_NAME, GPIOD_IS_OUT);
-}
-
-int dram_init(void)
-{
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-/* secondary_boot_func
- * this function should be write with asm, here, is is only for compiling pass
- * */
-void secondary_boot_func(void)
-{
-}
-
-#if CONFIG_AML_SD_EMMC
-#include <mmc.h>
-#include <asm/arch/sd_emmc.h>
-static int sd_emmc_init(unsigned port)
-{
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
- //todo add card detect
- /* check card detect */
- clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
- setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
- setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
- setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
- break;
- case SDIO_PORT_C:
- //enable pull up
- //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
- break;
- default:
- break;
- }
-
- return cpu_sd_emmc_init(port);
-}
-
-extern unsigned sd_debug_board_1bit_flag;
-
-static void sd_emmc_pwr_prepare(unsigned port)
-{
- cpu_sd_emmc_pwr_prepare(port);
-}
-
-static void sd_emmc_pwr_on(unsigned port)
-{
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
-// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
-// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
- /// @todo NOT FINISH
- break;
- case SDIO_PORT_C:
- break;
- default:
- break;
- }
- return;
-}
-static void sd_emmc_pwr_off(unsigned port)
-{
- /// @todo NOT FINISH
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
-// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
-// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
- break;
- case SDIO_PORT_C:
- break;
- default:
- break;
- }
- return;
-}
-
-// #define CONFIG_TSD 1
-static void board_mmc_register(unsigned port)
-{
- struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
- if (aml_priv == NULL)
- return;
-
- aml_priv->sd_emmc_init=sd_emmc_init;
- aml_priv->sd_emmc_detect=sd_emmc_detect;
- aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
- aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
- aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
- aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
-
- if (NULL == aml_priv->desc_buf)
- printf(" desc_buf Dma alloc Fail!\n");
- else
- printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
-
- sd_emmc_register(aml_priv);
-}
-int board_mmc_init(bd_t *bis)
-{
-#ifdef CONFIG_VLSI_EMULATOR
- //board_mmc_register(SDIO_PORT_A);
-#else
- //board_mmc_register(SDIO_PORT_B);
-#endif
- board_mmc_register(SDIO_PORT_B);
- board_mmc_register(SDIO_PORT_C);
-// board_mmc_register(SDIO_PORT_B1);
- return 0;
-}
-#endif
-
-/* Skip the first line and parse one uint
- * Return negative if not found */
-int parse_calibration_file_string(const char *str)
-{
- if (str == NULL)
- return -EINVAL;
-
- str = strchr(str, '\n');
- if (str == NULL)
- return -EINVAL;
- ++str;
-
- return simple_strtoul(str, NULL, 10);
-}
-
-/* If zero, this value has not been set and the default brightness should not be
- * overwritten. To store zero, store a non-zero value with its bottom 12 bits
- * all zero, like 0x1000.
- */
-int get_persistent_brightness_from_reg(void)
-{
- u32 brightness_sticky_val = readl(AO_RTI_STICKY_REG2);
- if (brightness_sticky_val != 0)
- return (brightness_sticky_val & 0x0fff) >> 1;
- return -1;
-}
-
-int do_configure_backlight(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
-#ifdef CONFIG_SYS_I2C_MESON
- int ret, i, attempt;
- const int retries = 3;
- char *addr_cal;
- int calibrated_current;
-
- /* Values to write:
- * [0]: Brightness register control only, backlight enabled
- * [1-2]: Standby disabled, 20mA MAX_CURRENT, CURRENT scale 1/2
- * [3]: Enable undervoltage protection at 5.2 V, "disable" backlight
- * (i2c only), disable set resistors
- * [4]: 9.6kHz PWM rate, 3 phase drivers
- * [5]: EN_DRV3, EN_DRV2, boost inductor current limit = 1.6 A
- * [6]: VBOOST_MAX = 25 V, JUMP_EN = 0
- * [7]: STEP_UP = 105 mV, STEP_DN = 105 mV, LED_FAULT_TH = 3V,
- * LED_COMP_HYST = DRIVER_HEADROOM + 750 mV
- * [8-9]: 12-bit brightness (default: 100%)
- * Important: Write brightness last to apply current calibration */
- const __u8 addrs[] = {0x01, 0xa0, 0xa1, 0xa2, 0xa5, 0xa7, 0xa9, 0xae,
- 0x10, 0x11};
- __u8 values[] = {0x85, 0xff, 0x37, 0x30, 0x54, 0xf4, 0x60, 0x09, 0xff,
- 0x0f};
- const int n_bytes = sizeof(values)/sizeof(values[0]);
- struct udevice *bl_devp = NULL;
-
- if (argc > 2) {
- printf("%s: Too many args: %d\n", __func__, argc);
- return CMD_RET_USAGE;
- }
-
- if (argc == 2) {
- addr_cal = (char *)simple_strtoul(argv[1], NULL, 16);
- calibrated_current = parse_calibration_file_string(addr_cal);
- if (calibrated_current >= 0 && calibrated_current <= 4095) {
- /* CURRENT_LSB */
- values[1] = 0xff & calibrated_current;
- /* CURRENT_MSB */
- values[2] = (values[2] & 0xf0) |
- (0x0f & (calibrated_current >> 8));
- }
- }
-
- // Apply persistent brightness if found
- if (persistent_brightness >= 0) {
-#ifdef BL33_DEBUG_PRINT
- printf("Applying persistent_brightness=%d\n", persistent_brightness);
-#endif
- /* Get LSB and MSB */
- values[n_bytes - 2] = persistent_brightness & 0xff;
- values[n_bytes - 1] = persistent_brightness >> 8 & 0x0f;
- } else {
-#ifdef BL33_DEBUG_PRINT
- printf("Persistent_brightness not set\n");
-#endif
- }
-
- enable_backlight(true);
-
- ret = i2c_get_chip_for_busnum(MESON_I2C_M3, 0X2c, 1, &bl_devp);
- if (ret) {
- printf("%s(%d):i2c get bus fail!\n", __func__, __LINE__);
- return -1;
- }
- //i2c_set_bus_num(AML_I2C_MASTER_D);
- for (i = 0; i < n_bytes; ++i) {
- for (attempt = 0; attempt < retries; ++attempt) {
- ret = dm_i2c_write(bl_devp, addrs[i], &values[i], 1);
- if (ret)
- printf("%s: Attempt=%d to write byte=0x%02x to reg=0x%02x of backlight failed\n",
- __func__, attempt, values[i], addrs[i]);
- else
- break;
- }
- }
-
- return ret;
-#else
- enable_backlight(true);
-
- return 0;
-#endif /* CONFIG_SYS_I2C_MESON */
-}
-
-U_BOOT_CMD(
- configure_backlight, 2, 0, do_configure_backlight,
- "configures the lp8556 backlight",
- "Usage: configure_backlight [calibration_string_addr]\n"\
- " Sets up required parameters of the backlight.\n"\
- " Default calibration is 100%.\n"\
- " calibration_str_addr (optional):\n"\
- " Address of calibration file string to parse.\n"
-);
-
-int do_get_cached_brightness(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- char *file_str_addr;
-
- if (argc > 2) {
- printf("%s: Too many args: %d\n", __func__, argc);
- return CMD_RET_USAGE;
- }
-
- // Apply persistent brightness if found in sticky register.
- persistent_brightness = get_persistent_brightness_from_reg();
- if (persistent_brightness >= 0) {
- return 0;
- }
-
- if (argc != 2) {
- return 0;
- }
-
-#ifdef BL33_DEBUG_PRINT
- printf("Don't have the sticky register set. Will read from cached brightness on disk.", persistent_brightness);
-#endif
-
- file_str_addr = (char *)simple_strtoul(argv[1], NULL, 16);
-
- if (file_str_addr) {
- // The file should be consist of one number.
- persistent_brightness = simple_strtoul(file_str_addr, NULL, 10);
-#ifdef BL33_DEBUG_PRINT
- printf("Applying brightness from file %d", file_str_addr, persistent_brightness);
-#endif
- }
- return 0;
-}
-
-U_BOOT_CMD(
- get_cached_brightness, 2, 0, do_get_cached_brightness,
- "Gets the cached backlight value",
- "Usage: get_cached_brightness [brightness_str_address]\n"\
- " Gets the cached backlight value.\n"\
- " brightness_str_addr (optional):\n"\
- " Address of cached brightness file string to parse.\n"
-);
-
-#ifdef CONFIG_AML_LCD
-/* Parses one line of the gamma calibration file. */
-/* Returns true on success. */
-#define GAMMA_SIZE (256)
-bool parse_gamma_string(const char *str, uint16_t *table)
-{
- char buf[4] = {'\0'};
- int i;
-
- for (i = 0; i < GAMMA_SIZE; ++i) {
- strncpy(buf, &str[3 * i], 3);
- table[i] = simple_strtol(buf, NULL, 16);
- }
-
- return true;
-}
-
-/* Check header then parse RGB gamma tables */
-/* Returns negative value on error */
-int parse_gamma_calibration_file_string(const char *str, u16 *r, u16 *g, u16 *b)
-{
- static const char supported_header_prefix[] = "Gamma Calibration 1.";
- static const int length = sizeof(supported_header_prefix) - 1;
- char *tables[3] = {r, g, b};
- const char *start, *end;
- int i;
-
- if (!str)
- return -EINVAL;
-
- // Check header prefix - only care about major version.
- if (strncmp(str, supported_header_prefix, length) != 0) {
- printf("Unknown gamma header: \"%.*s\"\n", length, str);
- return -EINVAL;
- }
-
- // Parse all three tables
- end = strchr(str, '\n');
- for (i = 0; i < 3; ++i) {
- start = end + 1;
- end = strchr(start, '\n');
-
- if ((end - start) / 3 != GAMMA_SIZE) {
- printf("Gamma table has invalid length.\n");
- return -EINVAL;
- }
- if (!parse_gamma_string(start, tables[i])) {
- printf("Could not parse gamma table %d.\n", i);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-#endif // CONFIG_AML_LCD
-
-int do_configure_gamma(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
-#ifdef CONFIG_AML_LCD
- static const int N_CHAN = 3;
- char *addr_cal;
- u16 gamma_tables[N_CHAN][GAMMA_SIZE];
- int i, j;
-
- if (argc == 1) {
- // Set to default
- for (i = 0; i < N_CHAN; ++i) {
- for (j = 0; j < GAMMA_SIZE; ++j)
- gamma_tables[i][j] = j << 2; /* 10-bit */
- }
- } else if (argc == 2) {
- // Load from passed file string
- addr_cal = (char *)simple_strtoul(argv[1], NULL, 16);
- if (parse_gamma_calibration_file_string(addr_cal,
- &gamma_tables[0],
- &gamma_tables[1],
- &gamma_tables[2]) != 0)
- return -EINVAL; // Error logged
- } else {
- return CMD_RET_USAGE;
- }
-
- vpp_set_rgb_gamma_table(&gamma_tables[0], &gamma_tables[1],
- &gamma_tables[2]);
-#endif // CONFIG_AML_LCD
- return 0;
-}
-
-U_BOOT_CMD(configure_gamma, 2, 0, do_configure_gamma,
- "configures gamma the gamma tables with the provided calibration\n",
- "Usage: configure_gamma [calibration_string_addr]\n"\
- " Applies the provided calibration file.\n"\
- " If a file is not provided, sets tables to default.\n"\
- " calibration_str_addr (optional):\n"\
- " Address of the calibration file string to parse.\n"
-);
-
-int do_get_chiptype(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- char *type[] = {"SS", "TT", "FF"};
- unsigned int dvfs_id = aml_get_dvfs_id();
- printf("get dvfs_id:%d\n", dvfs_id);
- if (dvfs_id > 2) {
- printf("fail to get dvfs id\n");
- dvfs_id = 0;
- }
- env_set("chip_type", type[dvfs_id]);
- return 0;
-}
-U_BOOT_CMD(get_chiptype, 1, 0, do_get_chiptype,
- "get elaine's chip type and env_set 'chip_type'\n",
- "get_chiptype"
-);
-
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
-int board_early_init_f(void){
- /*add board early init function here*/
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
-#include <asm/arch/usb-v2.h>
-#include <asm/arch/gpio.h>
-#define CONFIG_GXL_USB_U2_PORT_NUM 2
-
-#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
-#define CONFIG_GXL_USB_U3_PORT_NUM 1
-#else
-#define CONFIG_GXL_USB_U3_PORT_NUM 0
-#endif
-
-static void gpio_set_vbus_power(char is_power_on)
-{
- int ret;
-
- ret = gpio_request(CONFIG_USB_GPIO_PWR,
- CONFIG_USB_GPIO_PWR_NAME);
- if (ret && ret != -EBUSY) {
- printf("gpio: requesting pin %u failed\n",
- CONFIG_USB_GPIO_PWR);
- return;
- }
-
- if (is_power_on) {
- gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
- } else {
- gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
- }
-}
-
-struct amlogic_usb_config g_usb_config_GXL_skt={
- CONFIG_GXL_XHCI_BASE,
- USB_ID_MODE_HARDWARE,
- gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
- CONFIG_GXL_USB_PHY2_BASE,
- CONFIG_GXL_USB_PHY3_BASE,
- CONFIG_GXL_USB_U2_PORT_NUM,
- CONFIG_GXL_USB_U3_PORT_NUM,
- .usb_phy2_pll_base_addr = {
- CONFIG_USB_PHY_20,
- CONFIG_USB_PHY_21,
- }
-};
-
-#endif /*CONFIG_USB_XHCI_AMLOGIC*/
-
-#ifdef CONFIG_AML_HDMITX20
-static void hdmi_tx_set_hdmi_5v(void)
-{
-}
-#endif
-
-/*
- * mtd nand partition table, only care the size!
- * offset will be calculated by nand driver.
- */
-#ifdef CONFIG_AML_MTD
-static struct mtd_partition normal_partition_info[] = {
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- /* MUST NOT CHANGE this part unless u know what you are doing!
- * inherent parition for descrete bootloader to store fip
- * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
- * name must be same with TPL_PART_NAME
- */
- {
- .name = "tpl",
- .offset = 0,
- .size = 0,
- },
-#endif
- {
- .name = "fts",
- .offset = 0,
- .size = 1*SZ_1M,
- },
- {
- .name = "factory",
- .offset = 0,
- .size = 8*SZ_1M,
- },
- {
- .name = "recovery",
- .offset = 0,
- .size = 16*SZ_1M,
- },
- {
- .name = "boot",
- .offset = 0,
- .size = 16*SZ_1M,
- },
- {
- .name = "system",
- .offset = 0,
- .size = 220*SZ_1M,
- },
- /* last partition get the rest capacity */
- {
- .name = "cache",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-struct mtd_partition *get_aml_mtd_partition(void)
-{
- return normal_partition_info;
-}
-int get_aml_partition_count(void)
-{
- return ARRAY_SIZE(normal_partition_info);
-}
-#endif /* CONFIG_AML_MTD */
-
-#ifdef CONFIG_AML_SPIFC
-/*
- * BOOT_3: NOR_HOLDn:reg0[15:12]=3
- * BOOT_4: NOR_D:reg0[19:16]=3
- * BOOT_5: NOR_Q:reg0[23:20]=3
- * BOOT_6: NOR_C:reg0[27:24]=3
- * BOOT_7: NOR_WPn:reg0[31:28]=3
- * BOOT_14: NOR_CS:reg1[27:24]=3
- */
-#define SPIFC_NUM_CS 1
-static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
-
-static int spifc_pinctrl_enable(void *pinctrl, bool enable)
-{
- unsigned int val;
-
- val = readl(P_PERIPHS_PIN_MUX_0);
- val &= ~(0xfffff << 12);
- if (enable)
- val |= 0x33333 << 12;
- writel(val, P_PERIPHS_PIN_MUX_0);
-
- val = readl(P_PERIPHS_PIN_MUX_1);
- val &= ~(0xf << 24);
- writel(val, P_PERIPHS_PIN_MUX_1);
- return 0;
-}
-
-#if 0
-static const struct spifc_platdata spifc_platdata = {
- .reg = 0xffd14000,
- .mem_map = 0xf6000000,
- .pinctrl_enable = spifc_pinctrl_enable,
- .num_chipselect = SPIFC_NUM_CS,
- .cs_gpios = spifc_cs_gpios,
-};
-
-U_BOOT_DEVICE(spifc) = {
- .name = "spifc",
- .platdata = &spifc_platdata,
-};
-#endif
-#endif /* CONFIG_AML_SPIFC */
-
-#if 0
-#ifdef CONFIG_AML_SPICC
-/* generic config in arch gpio/clock.c */
-extern int spicc1_clk_set_rate(int rate);
-extern int spicc1_clk_enable(bool enable);
-extern int spicc1_pinctrl_enable(bool enable);
-
-static const struct spicc_platdata spicc1_platdata = {
- .compatible = "amlogic,meson-g12a-spicc",
- .reg = (void __iomem *)0xffd15000,
- .clk_rate = 666666666,
- .clk_set_rate = spicc1_clk_set_rate,
- .clk_enable = spicc1_clk_enable,
- .pinctrl_enable = spicc1_pinctrl_enable,
- /* case one slave without cs: {"no_cs", 0} */
- .cs_gpio_names = {"GPIOH_6", 0},
-};
-
-U_BOOT_DEVICE(spicc1) = {
- .name = "spicc",
- .platdata = &spicc1_platdata,
-};
-#endif /* CONFIG_AML_SPICC */
-#endif
-
-extern void aml_pwm_cal_init(int mode);
-
-int board_init(void)
-{
- printf("board init\n");
-
- /*in kernel P_RESET1_LEVEL has been clear,
- * uboot need set these bits about usb,
- * otherwise the usb has problem.
- */
- *(volatile uint32_t *)P_RESET1_LEVEL |= (3 << 16);
- //CPU_GPU_Voltage_init();
- enable_backlight(false);
- panel_detect_init();
-//Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
-//As NOT NEED other board init If USB BOOT MODE
-#ifdef CONFIG_AML_V2_FACTORY_BURN
- if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
- aml_try_factory_usb_burning(0, gd->bd);
- }
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
-
- pinctrl_devices_active(PIN_CONTROLLER_NUM);
-#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
- board_usb_pll_disable(&g_usb_config_GXL_skt);
- board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
-#endif /*CONFIG_USB_XHCI_AMLOGIC*/
-
- /* TODO(b/110040521): This is the earliest the backlight can be started,
- * but the LCD is not running yet. */
-
-#if 0
- aml_pwm_cal_init(0);
-#endif//
-#ifdef CONFIG_AML_NAND
- extern int amlnf_init(unsigned char flag);
- amlnf_init(0);
-#endif
- gpio_disable_pull();
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- printf("board late init\n");
- run_command("mmc dev 1", 0);
- run_command("run detect_panel", 0);
-#if 0
- //update env before anyone using it
- run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
- "if test ${reboot_mode} = factory_reset; then "\
- "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
- run_command("if itest ${upgrade_step} == 1; then "\
- "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
- /*add board late init function here*/
-#ifndef DTB_BIND_KERNEL
- int ret;
- ret = run_command("store dtb read $dtb_mem_addr", 1);
- if (ret) {
- printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
-#ifdef CONFIG_DTB_MEM_ADDR
- char cmd[64];
- printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
- sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
- ret = run_command(cmd, 1);
- if (ret) {
- printf("%s(): %s fail\n", __func__, cmd);
- }
-#endif
- }
-#elif defined(CONFIG_DTB_MEM_ADDR)
- {
- char cmd[128];
- int ret;
- if (!getenv("dtb_mem_addr")) {
- sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
- run_command(cmd, 0);
- }
- sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
- ret = run_command(cmd, 0);
- if (ret) {
- printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
- }
- }
-#endif// #ifndef DTB_BIND_KERNEL
-
- /* load unifykey */
- run_command("keyunify init 0x1234", 0);
-#endif
-/*open vpu hdmitx and cvbs driver*/
-#ifdef CONFIG_AML_VPU
- vpu_probe();
-#endif
-
-#ifdef CONFIG_AML_VPP
- vpp_init();
-#endif
-
-#ifdef CONFIG_AML_HDMITX
- hdmi_tx_init();
-#endif
-#ifdef CONFIG_AML_CVBS
- run_command("cvbs init", 0);
-#endif
-#ifdef CONFIG_AML_LCD
- lcd_probe();
-#endif
-
-#ifdef CONFIG_AML_V2_FACTORY_BURN
- if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
- aml_try_factory_usb_burning(1, gd->bd);
- aml_try_factory_sdcard_burning(0, gd->bd);
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
- return 0;
-}
-#endif
-
-#ifdef CONFIG_AML_TINY_USBTOOL
-int usb_get_update_result(void)
-{
- unsigned long upgrade_step;
- upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
- printf("upgrade_step = %d\n", (int)upgrade_step);
- if (upgrade_step == 1)
- {
- run_command("defenv", 1);
- run_command("env_set upgrade_step 2", 1);
- run_command("saveenv", 1);
- return 0;
- }
- else
- {
- return -1;
- }
-}
-#endif
-
-phys_size_t get_effective_memsize(void)
-{
- // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
-#if defined(CONFIG_SYS_MEM_TOP_HIDE)
- return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
-#else
- return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
-#endif
-}
-
-#ifdef CONFIG_MULTI_DTB
-int checkhw(char * name)
-{
- /*
- * read board hw id
- * set and select the dts according the board hw id.
- *
- * hwid = 1 p321 v1
- * hwid = 2 p321 v2
- */
- unsigned int hwid = 1;
- char loc_name[64] = {0};
-
- /* read hwid */
- hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
-
- printf("checkhw: hwid = %d\n", hwid);
-
-
- switch (hwid) {
- case 1:
- strcpy(loc_name, "txl_p321_v1\0");
- break;
- case 2:
- strcpy(loc_name, "txl_p321_v2\0");
- break;
- default:
- strcpy(loc_name, "txl_p321_v1");
- break;
- }
- strcpy(name, loc_name);
- env_set("aml_dt", loc_name);
- return 0;
-}
-#endif
-
-/* workaround for VDDEE issue */
-/* VCCK PWM table */
-#define VCCK_VAL_REG_800 0x00150007
-#define VCCK_VAL_REG_810 0x00140008
-#define VCCK_VAL_REG_820 0x00130009
-#define VCCK_VAL_REG_830 0x0012000a
-#define VCCK_VAL_REG_840 0x0011000b
-#define VCCK_VAL_REG_850 0x0010000c
-#define VCCK_VAL_REG_860 0x000f000d
-#define VCCK_VAL_REG_870 0x000e000e
-#define VCCK_VAL_REG_880 0x000d000f
-#define VCCK_VAL_REG_890 0x000c0010
-#define VCCK_VAL_REG_900 0x000b0011
-#define VCCK_VAL_REG_910 0x000a0012
-#define VCCK_VAL_REG_920 0x00090013
-#define VCCK_VAL_REG_930 0x00080014
-#define VCCK_VAL_REG_940 0x00070015
-#define VCCK_VAL_REG_950 0x00060016
-#define VCCK_VAL_REG_960 0x00050017
-#define VCCK_VAL_REG_970 0x00040018
-#define VCCK_VAL_REG_980 0x00030019
-#define VCCK_VAL_REG_990 0x0002001a
-#define VCCK_VAL_REG_1000 0x0001001b
-#define VCCK_VAL_REG_1010 0x0000001c
-#define VCCK_VAL_REG_DEFAULT 0x00500008
-
-/* VDDEE PWM table */
-#define VDDEE_VAL_REG_800 0x0010000c
-#define VDDEE_VAL_REG_810 0x000f000d
-#define VDDEE_VAL_REG_820 0x000e000e
-#define VDDEE_VAL_REG_830 0x000d000f
-#define VDDEE_VAL_REG_840 0x000c0010
-#define VDDEE_VAL_REG_850 0x000b0011
-#define VDDEE_VAL_REG_860 0x000a0012
-#define VDDEE_VAL_REG_870 0x00090013
-#define VDDEE_VAL_REG_880 0x00080014
-#define VDDEE_VAL_REG_890 0x00070015
-#define VDDEE_VAL_REG_900 0x00060016
-#define VDDEE_VAL_REG_910 0x00050017
-#define VDDEE_VAL_REG_920 0x00040018
-#define VDDEE_VAL_REG_930 0x00030019
-#define VDDEE_VAL_REG_940 0x0002001a
-#define VDDEE_VAL_REG_950 0x0001001b
-#define VDDEE_VAL_REG_960 0x0000001c
-#define VDDEE_VAL_REG_DEFAULT 0x00500008
-
-void reset_misc(void)
-{
- unsigned int value;
-
- /* adjust VDDCPU to Hiz value step by step */
- writel(VCCK_VAL_REG_830, AO_PWM_PWM_D);
- udelay(1);
- writel(VCCK_VAL_REG_860, AO_PWM_PWM_D);
- udelay(1);
-
- /* GPIOE_0 & GPIOE_1 to gpio pin */
- value = readl(AO_RTI_PINMUX_REG1);
- value &= ~(0xff << 16);
- writel(value, AO_RTI_PINMUX_REG1);
-
- /* disable pwm_ao_b - VDDEE */
- value = readl(AO_PWM_MISC_REG_AB);
- value &= ~((0x1 << 1) | (0x1 << 23));
- writel(value, AO_PWM_MISC_REG_AB);
- writel(VDDEE_VAL_REG_DEFAULT, AO_PWM_PWM_B);
-
- /* disable pwm_ao_d - VDDCPU_B*/
- value = readl(AO_PWM_MISC_REG_CD);
- value &= ~((0x1 << 1) | (0x1 << 23));
- writel(value, AO_PWM_MISC_REG_CD);
- writel(VCCK_VAL_REG_DEFAULT, AO_PWM_PWM_D);
-}
-
-static struct mm_region bd_mem_map[] = {
- {
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = bd_mem_map;
-
-void board_nand_init(void) {
- printf("board_nand_init\n");
- return;
-}
-
-int print_cpuinfo(void) {
- printf("print_cpuinfo\n");
- return 0;
-}
-
-int mach_cpu_init(void) {
- printf("mach_cpu_init\n");
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- /* eg: bl31/32 rsv */
- return 0;
-}
diff --git a/board/amlogic/sm1_elaine_b1/zircon.c b/board/amlogic/sm1_elaine_b1/zircon.c
deleted file mode 100644
index 8e6888f..0000000
--- a/board/amlogic/sm1_elaine_b1/zircon.c
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * Copyright (c) 2018 The Fuchsia Authors
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common.h>
-#include <linux/mtd/partitions.h>
-#include <nand.h>
-#include <part.h>
-#include <emmc_storage.h>
-#include <zircon/zircon.h>
-
-#define PDEV_VID_GOOGLE 3
-#define PDEV_PID_ASTRO 3
-
-#define NVRAM_LENGTH (8 * 1024)
-
-const char* BOOTLOADER_VERSION = "zircon-bootloader=0.10";
-
-static const zbi_cpu_config_t cpu_config = {
- .cluster_count = 1,
- .clusters = {
- {
- .cpu_count = 4,
- },
- },
-};
-
-static const zbi_mem_range_t mem_config[] = {
- {
- .type = ZBI_MEM_RANGE_RAM,
- .length = 0x60000000, // 1.5 GB
- },
- {
- .type = ZBI_MEM_RANGE_PERIPHERAL,
- .paddr = 0xf5800000,
- .length = 0x0a800000,
- },
- // secmon_reserved:linux,secmon
- {
- .type = ZBI_MEM_RANGE_RESERVED,
- .paddr = 0x05000000,
- .length = 0x2400000,
- },
- // logo_reserved:linux,meson-fb
- {
- .type = ZBI_MEM_RANGE_RESERVED,
- .paddr = 0x5f800000,
- .length = 0x800000,
- },
-};
-
-static const dcfg_simple_t uart_driver = {
- .mmio_phys = 0xff803000,
- .irq = 225,
-};
-
-static const dcfg_arm_gicv2_driver_t gicv2_driver = {
- .mmio_phys = 0xffc00000,
- .gicd_offset = 0x1000,
- .gicc_offset = 0x2000,
- .gich_offset = 0x4000,
- .gicv_offset = 0x6000,
- .ipi_base = 5,
-};
-
-static const dcfg_arm_psci_driver_t psci_driver = {
- .use_hvc = false,
- .reboot_args = { 1, 0, 0 },
- .reboot_bootloader_args = { 4, 0, 0 },
- .reboot_recovery_args = { 2, 0, 0 },
-};
-
-static const dcfg_arm_generic_timer_driver_t timer_driver = {
- .irq_phys = 30,
-};
-
-static const zbi_platform_id_t platform_id = {
- .vid = PDEV_VID_GOOGLE,
- .pid = PDEV_PID_ASTRO,
- .board_name = "astro",
-};
-
-enum {
- PART_TPL,
- PART_FTS,
- PART_FACTORY,
- PART_ZIRCON_B,
- PART_ZIRCON_A,
- PART_ZIRCON_R,
- PART_FVM,
- PART_SYS_CONFIG,
- PART_MIGRATION,
- PART_COUNT,
-};
-
-#define RECOVERY_SIZE (16 * 1024 * 1024)
-#define SYS_CONFIG_SIZE (1 * 1024 * 1024)
-#define MIGRATION_SIZE (3 * 1024 * 1024)
-
-static zbi_partition_map_t partition_map = {
- // .block_count filled in below
- // .block_size filled in below
- .guid = {},
- .partition_count = PART_COUNT,
- .partitions = {
- {
- .type_guid = GUID_BOOTLOADER_VALUE,
- .name = "tpl",
- },
- {
- .name = "fts",
- },
- {
- .name = "factory",
- },
- {
- .type_guid = GUID_ZIRCON_R_VALUE,
- .name = "zircon-r",
- },
- {
- .type_guid = GUID_ZIRCON_A_VALUE,
- .name = "zircon-a",
- },
- {
- .type_guid = GUID_ZIRCON_B_VALUE,
- .name = "zircon-b",
- },
- {
- .type_guid = GUID_FVM_VALUE,
- .name = "fvm",
- },
- {
- .type_guid = GUID_SYS_CONFIG_VALUE,
- .name = "sys-config",
- },
- {
- .name = "migration",
- },
- },
-};
-
-extern struct mtd_partition *get_aml_mtd_partition(void);
-extern int get_aml_partition_count(void);
-
-static void add_partition_map(zbi_header_t* zbi) {
- struct mtd_partition* tpl_part = NULL;
- struct mtd_partition* fts_part = NULL;
- struct mtd_partition* factory_part = NULL;
- struct mtd_partition* recovery_part = NULL;
- struct mtd_partition* boot_part = NULL;
- struct mtd_partition* system_part = NULL;
- struct mtd_partition* partitions = get_aml_mtd_partition();
- int partition_count = get_aml_partition_count();
- int i;
-
- for (i = 0; i < partition_count; i++) {
- struct mtd_partition* part = &partitions[i];
- if (!strcmp("tpl", part->name)) {
- tpl_part = part;
- } else if (!strcmp("fts", part->name)) {
- fts_part = part;
- } else if (!strcmp("factory", part->name)) {
- factory_part = part;
- } else if (!strcmp("recovery", part->name)) {
- recovery_part = part;
- } else if (!strcmp("boot", part->name)) {
- boot_part = part;
- } else if (!strcmp("system", part->name)) {
- system_part = part;
- }
- }
-
- if (!tpl_part) {
- printf("could not find tpl partition\n");
- return;
- }
- if (!fts_part) {
- printf("could not find fts partition\n");
- return;
- }
- if (!factory_part) {
- printf("could not find factory partition\n");
- return;
- }
- if (!recovery_part) {
- printf("could not find recovery partition\n");
- return;
- }
- if (!boot_part) {
- printf("could not find boot partition\n");
- return;
- }
- if (!system_part) {
- printf("could not find system partition\n");
- return;
- }
-
- uint32_t block_size = nand_info[1].writesize;
- uint64_t total_size = nand_info[1].size;
-
- partition_map.block_size = block_size;
- partition_map.block_count = total_size / block_size;
-
- // map tpl partition to BOOTLOADER
- partition_map.partitions[PART_TPL].first_block = tpl_part->offset / block_size;
- partition_map.partitions[PART_TPL].last_block =
- ((tpl_part->offset + tpl_part->size) / block_size) - 1;
- // map fts partition to "fts"
- partition_map.partitions[PART_FTS].first_block = fts_part->offset / block_size;
- partition_map.partitions[PART_FTS].last_block =
- ((fts_part->offset + fts_part->size) / block_size) - 1;
- // map factory partition to "factory"
- partition_map.partitions[PART_FACTORY].first_block = factory_part->offset / block_size;
- partition_map.partitions[PART_FACTORY].last_block =
- ((factory_part->offset + factory_part->size) / block_size) - 1;
- // map recovery partition to ZIRCON_B
- partition_map.partitions[PART_ZIRCON_B].first_block = recovery_part->offset / block_size;
- partition_map.partitions[PART_ZIRCON_B].last_block =
- ((recovery_part->offset + recovery_part->size) / block_size) - 1;
- // map boot partition to ZIRCON_A
- partition_map.partitions[PART_ZIRCON_A].first_block = boot_part->offset / block_size;
- partition_map.partitions[PART_ZIRCON_A].last_block =
- ((boot_part->offset + boot_part->size) / block_size) - 1;
- // ZIRCON_R partition at start of system
- partition_map.partitions[PART_ZIRCON_R].first_block = system_part->offset / block_size;
- partition_map.partitions[PART_ZIRCON_R].last_block =
- partition_map.partitions[PART_ZIRCON_R].first_block +
- (RECOVERY_SIZE / block_size) - 1;
- // FVM follows ZIRCON_R
- partition_map.partitions[PART_FVM].first_block =
- partition_map.partitions[PART_ZIRCON_R].last_block + 1;
- partition_map.partitions[PART_FVM].last_block =
- ((total_size - SYS_CONFIG_SIZE - MIGRATION_SIZE) / block_size) - 1;
- // SYS_CONFIG follows FVM
- partition_map.partitions[PART_SYS_CONFIG].first_block =
- partition_map.partitions[PART_FVM].last_block + 1;
- partition_map.partitions[PART_SYS_CONFIG].last_block =
- partition_map.partitions[PART_SYS_CONFIG].first_block +
- (SYS_CONFIG_SIZE / block_size) - 1;
- // MIGRATION follows SYS_CONFIG
- partition_map.partitions[PART_MIGRATION].first_block =
- partition_map.partitions[PART_SYS_CONFIG].last_block + 1;
- partition_map.partitions[PART_MIGRATION].last_block =
- partition_map.partitions[PART_MIGRATION].first_block +
- (MIGRATION_SIZE / block_size) - 1;
-
- printf("Zircon partitions:\n");
- for (i = 0; i < PART_COUNT; i++) {
- printf(" 0x%016llx - 0x%016llx : %s\n",
- partition_map.partitions[i].first_block * block_size,
- (partition_map.partitions[i].last_block + 1) * block_size,
- partition_map.partitions[i].name);
- }
-
- zircon_append_boot_item(zbi, ZBI_TYPE_DRV_PARTITION_MAP, 0, &partition_map,
- sizeof(zbi_partition_map_t) +
- partition_map.partition_count * sizeof(zbi_partition_t));
-}
-
-int zircon_preboot(zbi_header_t* zbi) {
- // add CPU configuration
- zircon_append_boot_item(zbi, ZBI_TYPE_CPU_CONFIG, 0, &cpu_config,
- sizeof(zbi_cpu_config_t) +
- sizeof(zbi_cpu_cluster_t) * cpu_config.cluster_count);
-
- // allocate crashlog save area before 0x5f800000-0x60000000 reserved area
- zbi_nvram_t nvram;
- nvram.base = 0x5f800000 - NVRAM_LENGTH;
- nvram.length = NVRAM_LENGTH;
- zircon_append_boot_item(zbi, ZBI_TYPE_NVRAM, 0, &nvram, sizeof(nvram));
-
- // add memory configuration
- zircon_append_boot_item(zbi, ZBI_TYPE_MEM_CONFIG, 0, &mem_config, sizeof(mem_config));
-
- // add kernel drivers
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_AMLOGIC_UART, &uart_driver,
- sizeof(uart_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_GIC_V2, &gicv2_driver,
- sizeof(gicv2_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_PSCI, &psci_driver,
- sizeof(psci_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_GENERIC_TIMER, &timer_driver,
- sizeof(timer_driver));
-
- zircon_append_boot_item(zbi, ZBI_TYPE_CMDLINE, 0, BOOTLOADER_VERSION, strlen(BOOTLOADER_VERSION) + 1);
-
- // add platform ID
- zircon_append_boot_item(zbi, ZBI_TYPE_PLATFORM_ID, 0, &platform_id, sizeof(platform_id));
-
- add_partition_map(zbi);
-
- return 0;
-}
diff --git a/board/amlogic/sm1_elaine_bx/Kconfig b/board/amlogic/sm1_elaine_bx/Kconfig
deleted file mode 100755
index d831f86..0000000
--- a/board/amlogic/sm1_elaine_bx/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_SM1_ELAINE_BX
-
-config SYS_SOC
- default "g12a"
-
-config SYS_BOARD
- default "sm1_elaine_bx"
-
-config SYS_VENDOR
- default "amlogic"
-
-config SYS_CONFIG_NAME
- default "sm1_elaine_bx"
-
-endif
diff --git a/board/amlogic/sm1_elaine_bx/Makefile b/board/amlogic/sm1_elaine_bx/Makefile
deleted file mode 100755
index 82a876d..0000000
--- a/board/amlogic/sm1_elaine_bx/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-
-obj-y += $(BOARD).o
-obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/sm1_elaine_bx/aml-user-key.sig b/board/amlogic/sm1_elaine_bx/aml-user-key.sig
deleted file mode 100755
index 2ceabc1..0000000
--- a/board/amlogic/sm1_elaine_bx/aml-user-key.sig
+++ /dev/null
Binary files differ
diff --git a/board/amlogic/sm1_elaine_bx/firmware/ramdump.c b/board/amlogic/sm1_elaine_bx/firmware/ramdump.c
deleted file mode 100755
index e03dcd2..0000000
--- a/board/amlogic/sm1_elaine_bx/firmware/ramdump.c
+++ /dev/null
@@ -1,45 +0,0 @@
-
-#ifdef CONFIG_MDUMP_COMPRESS
-#include "ramdump.h"
-
-struct ram_compress_full __ramdump_data = {
- .store_phy_addr = (void *)CONFIG_COMPRESSED_DATA_ADDR,
- .full_memsize = CONFIG_DDR_TOTAL_SIZE,
- .section_count = CONFIG_COMPRESS_SECTION,
- .sections = {
- {
- /* memory afer compressed data address */
- .phy_addr = (void *)CONFIG_COMPRESSED_DATA_ADDR,
- .section_size = CONFIG_DDR_TOTAL_SIZE -
- CONFIG_COMPRESSED_DATA_ADDR,
- .section_index = 4,
- .compress_type = RAM_COMPRESS_NORMAL,
- },
- {
- /* memory before bl2 */
- .phy_addr = (void *)CONFIG_COMPRESS_START_ADDR,
- .section_size = CONFIG_BL2_IGNORE_ADDR -
- CONFIG_COMPRESS_START_ADDR,
- .section_index = 1,
- .compress_type = RAM_COMPRESS_NORMAL,
- },
- {
- /* memory in reserved bl2 */
- .phy_addr = (void *)CONFIG_BL2_IGNORE_ADDR,
- .section_size = CONFIG_BL2_IGNORE_SIZE,
- .section_index = 2,
- .compress_type = RAM_COMPRESS_SET,
- .set_value = 0x0,
- },
- {
- /* segment 4: normal compress */
- .phy_addr = (void *)CONFIG_SEG4_ADDR,
- .section_size = CONFIG_COMPRESSED_DATA_ADDR -
- CONFIG_SEG4_ADDR,
- .section_index = 3,
- .compress_type = RAM_COMPRESS_NORMAL,
- }
- },
-};
-#endif /* CONFIG_MDUMP_COMPRESS */
-
diff --git a/board/amlogic/sm1_elaine_bx/firmware/ramdump.h b/board/amlogic/sm1_elaine_bx/firmware/ramdump.h
deleted file mode 100755
index 0671567..0000000
--- a/board/amlogic/sm1_elaine_bx/firmware/ramdump.h
+++ /dev/null
@@ -1,75 +0,0 @@
-#ifndef __RAM_DUMP_H__
-#define __RAM_DUMP_H__
-
-#include <config.h>
-#ifdef CONFIG_MDUMP_COMPRESS
-#define CONFIG_COMPRESS_SECTION 4
-
-#if CONFIG_COMPRESS_SECTION > 8
-#error ---> CONFIG_COMPRESS_SECTION out of range, max should be 8
-#endif
-/*
- * Full Memory lay out for RAM compress:
- *
- * DDR_TOP -> +--------+
- * | |
- * | |
- * | 4 |
- * | |
- * | |
- * |~~~~~~~~| <- store compressing data
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * COMPRESSED_DATA -> +--------+
- * | |
- * | 3 |
- * | |
- * BL2_IGNORE_END -> +--------+ -- IGNORE_SIZE
- * ||||||||||
- * ||||2|||||
- * ||||||||||
- * BL2_IGNORE_ADDR -> +--------+
- * | |
- * | 1 |
- * | |
- * COMPRESS_START_ADDR -> +--------+
- */
-#define CONFIG_DDR_TOTAL_SIZE (CONFIG_DDR_SIZE << 20)
-#define CONFIG_COMPRESSED_DATA_ADDR (0x10000000)
-#define CONFIG_COMPRESSED_DATA_ADDR1 (0x08000000)
-
-#define CONFIG_COMPRESS_START_ADDR (0x00000000)
-#define CONFIG_BL2_IGNORE_ADDR (0x05000000)
-#define CONFIG_BL2_IGNORE_SIZE (0x00300000)
-#define CONFIG_SEG4_ADDR (CONFIG_BL2_IGNORE_ADDR + \
- CONFIG_BL2_IGNORE_SIZE)
-
-enum {
- RAM_COMPRESS_NORMAL = 1,
- RAM_COMPRESS_COPY = 2,
- RAM_COMPRESS_SET = 3 /* set ram content to same vale */
-};
-
-struct ram_compress_section {
- void *phy_addr;
- unsigned int section_size;
- unsigned int section_index : 8;
- unsigned int compress_type : 8;
- unsigned int set_value : 16;
-};
-
-struct ram_compress_full {
- void *store_phy_addr;
- unsigned int full_memsize;
- unsigned int section_count;
- struct ram_compress_section sections[CONFIG_COMPRESS_SECTION];
-};
-
-#endif
-#endif /* __RAM_DUMP_H__ */
diff --git a/board/amlogic/sm1_elaine_bx/firmware/scp_task/dvfs_board.c b/board/amlogic/sm1_elaine_bx/firmware/scp_task/dvfs_board.c
deleted file mode 100755
index accb38f..0000000
--- a/board/amlogic/sm1_elaine_bx/firmware/scp_task/dvfs_board.c
+++ /dev/null
@@ -1,194 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_p1/firmware/scp_task/dvfs_board.c
- *
- * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-/*
-int pwm_voltage_table[ ][2] = {
- { 0x1c0000, 860},
- { 0x1b0001, 870},
- { 0x1a0002, 880},
- { 0x190003, 890},
- { 0x180004, 900},
- { 0x170005, 910},
- { 0x160006, 920},
- { 0x150007, 930},
- { 0x140008, 940},
- { 0x130009, 950},
- { 0x12000a, 960},
- { 0x11000b, 970},
- { 0x10000c, 980},
- { 0x0f000d, 990},
- { 0x0e000e, 1000},
- { 0x0d000f, 1010},
- { 0x0c0010, 1020},
- { 0x0b0011, 1030},
- { 0x0a0012, 1040},
- { 0x090013, 1050},
- { 0x080014, 1060},
- { 0x070015, 1070},
- { 0x060016, 1080},
- { 0x050017, 1090},
- { 0x040018, 1100},
- { 0x030019, 1110},
- { 0x02001a, 1120},
- { 0x01001b, 1130},
- { 0x00001c, 1140}
-};
-*/
-#include "pwm_ctrl.h"
-
-#define CHIP_ADJUST 20
-#define RIPPLE_ADJUST 30
-struct scpi_opp_entry cpu_dvfs_tbl[] = {
- DVFS( 100000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS( 250000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS( 500000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1200000000, 940+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1296000000, 980+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1416000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
-};
-
-
-#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
-#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
-#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2))))
-
-#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2))))
-#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
-
-
-enum pwm_id {
- pwm_a = 0,
-};
-
-
-void pwm_init(int id)
-{
- /*
- * TODO: support more pwm controllers, right now only support PWM_B
- */
- unsigned int reg;
- reg = P_PWM_MISC_REG_AB;
- reg &= ~(0x7f << 8);
- reg |= ((1 << 15) | (1 << 0));
- P_PWM_MISC_REG_AB = reg;
- /*
- * default set to max voltage
- */
- //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
- reg = P_PIN_MUX_REG3;
- reg &= ~((1 << 21) | 1 << 12);
- P_PIN_MUX_REG3 = reg;
-
- reg = P_PIN_MUX_REG10;
- reg &= ~(1 << 16);
- P_PIN_MUX_REG10 = reg;//clear reg10
- reg = P_PIN_MUX_REG4;
- reg &= ~(1 << 26); // clear PWM_VS
- reg |= (1 << 17); // enable PWM_A
- P_PIN_MUX_REG4 = reg;
-
-
- _udelay(200);
-}
-
-int dvfs_get_voltage(void)
-{
- int i = 0;
- unsigned int reg_val;
-
- reg_val = P_PWM_PWM_A;
- for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
- if (pwm_voltage_table[i][0] == reg_val) {
- return i;
- }
- }
- if (i >= ARRAY_SIZE(pwm_voltage_table)) {
- return -1;
- }
- return -1;
-}
-
-void set_dvfs(unsigned int domain, unsigned int index)
-{
- int cur, to;
- static int init_flag = 0;
-
- if (!init_flag) {
- pwm_init(pwm_a);
- init_flag = 1;
- }
- cur = dvfs_get_voltage();
- for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
- if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
- break;
- }
- }
- if (to >= ARRAY_SIZE(pwm_voltage_table)) {
- to = ARRAY_SIZE(pwm_voltage_table) - 1;
- }
- if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
- P_PWM_PWM_A = pwm_voltage_table[to][0];
- _udelay(200);
- return ;
- }
- while (cur != to) {
- /*
- * if target step is far away from current step, don't change
- * voltage by one-step-done. You should change voltage step by
- * step to make sure voltage output is stable
- */
- if (cur < to) {
- if (cur < to - 3) {
- cur += 3;
- } else {
- cur = to;
- }
- } else {
- if (cur > to + 3) {
- cur -= 3;
- } else {
- cur = to;
- }
- }
- P_PWM_PWM_A = pwm_voltage_table[cur][0];
- _udelay(100);
- }
- _udelay(200);
-}
-void get_dvfs_info_board(unsigned int domain,
- unsigned char *info_out, unsigned int *size_out)
-{
- unsigned int cnt;
- cnt = ARRAY_SIZE(cpu_dvfs_tbl);
-
- buf_opp.latency = 200;
- buf_opp.count = cnt;
- memset(&buf_opp.opp[0], 0,
- MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
-
- memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
- cnt * sizeof(struct scpi_opp_entry));
-
- memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
- *size_out = sizeof(struct scpi_opp);
- return;
-}
diff --git a/board/amlogic/sm1_elaine_bx/firmware/scp_task/pwm_ctrl.h b/board/amlogic/sm1_elaine_bx/firmware/scp_task/pwm_ctrl.h
deleted file mode 100755
index 0f815f8..0000000
--- a/board/amlogic/sm1_elaine_bx/firmware/scp_task/pwm_ctrl.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
-*board/amlogic/sm1_elaine_p1/firmware/scp_task/pwm_vol_tab.h
-*table for Dynamic Voltage/Frequency Scaling
-*/
-#ifndef __PWM_CTRL_H__
-#define __PWM_CTRL_H__
-
-static int pwm_voltage_table_ee[][2] = {
- { 0x1c0000, 681},
- { 0x1b0001, 691},
- { 0x1a0002, 701},
- { 0x190003, 711},
- { 0x180004, 721},
- { 0x170005, 731},
- { 0x160006, 741},
- { 0x150007, 751},
- { 0x140008, 761},
- { 0x130009, 772},
- { 0x12000a, 782},
- { 0x11000b, 792},
- { 0x10000c, 802},
- { 0x0f000d, 812},
- { 0x0e000e, 822},
- { 0x0d000f, 832},
- { 0x0c0010, 842},
- { 0x0b0011, 852},
- { 0x0a0012, 862},
- { 0x090013, 872},
- { 0x080014, 882},
- { 0x070015, 892},
- { 0x060016, 902},
- { 0x050017, 912},
- { 0x040018, 922},
- { 0x030019, 932},
- { 0x02001a, 942},
- { 0x01001b, 952},
- { 0x00001c, 962}
-};
-
-#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/sm1_elaine_bx/firmware/scp_task/pwr_ctrl.c b/board/amlogic/sm1_elaine_bx/firmware/scp_task/pwr_ctrl.c
deleted file mode 100755
index 7289735..0000000
--- a/board/amlogic/sm1_elaine_bx/firmware/scp_task/pwr_ctrl.c
+++ /dev/null
@@ -1,196 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_p1/firmware/scp_task/pwr_ctrl.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <gpio.h>
-#include "pwm_ctrl.h"
-#ifdef CONFIG_CEC_WAKEUP
-#include <cec_tx_reg.h>
-#endif
-
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
-static void set_vddee_voltage(unsigned int target_voltage)
-{
- unsigned int to;
-
- for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
- if (pwm_voltage_table_ee[to][1] >= target_voltage) {
- break;
- }
- }
-
- if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
- to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
- }
-
- writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
-}
-
-static void power_off_at_24M(unsigned int suspend_from)
-{
- /*set gpioH_8 low to power off vcc 5v*/
- writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
- writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
-
- /*set test_n low to power off vcck & vcc 3.3v*/
- writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
- writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
- writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
-
- /*step down ee voltage*/
- set_vddee_voltage(AML_VDDEE_SLEEP_VOLTAGE);
-}
-
-static void power_on_at_24M(unsigned int suspend_from)
-{
- /*step up ee voltage*/
- set_vddee_voltage(AML_VDDEE_INIT_VOLTAGE);
-
- /*set test_n low to power on vcck & vcc 3.3v*/
- writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
- writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
- writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
- _udelay(100);
-
- /*set gpioH_8 low to power on vcc 5v*/
- writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
- writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
- _udelay(10000);
-
-}
-
-void get_wakeup_source(void *response, unsigned int suspend_from)
-{
- struct wakeup_info *p = (struct wakeup_info *)response;
- struct wakeup_gpio_info *gpio;
- unsigned val;
- unsigned i = 0;
-
- p->status = RESPONSE_OK;
- val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
- ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC | ETH_PHY_GPIO_SRC
- | CECB_WAKEUP_SRC);
-
- p->sources = val;
-
- /* Power Key: AO_GPIO[3]*/
- gpio = &(p->gpio_info[i]);
- gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
- gpio->gpio_in_idx = GPIOAO_3;
- gpio->gpio_in_ao = 1;
- gpio->gpio_out_idx = -1;
- gpio->gpio_out_ao = -1;
- gpio->irq = IRQ_AO_GPIO0_NUM;
- gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
- p->gpio_info_count = ++i;
-
- /*Eth:GPIOZ_14*/
- gpio = &(p->gpio_info[i]);
- gpio->wakeup_id = ETH_PHY_GPIO_SRC;
- gpio->gpio_in_idx = GPIOZ_14;
- gpio->gpio_in_ao = 0;
- gpio->gpio_out_idx = -1;
- gpio->gpio_out_ao = -1;
- gpio->irq = IRQ_GPIO1_NUM;
- gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
- p->gpio_info_count = ++i;
-
- /*bt wake host*/
- gpio = &(p->gpio_info[i]);
- gpio->wakeup_id = BT_WAKEUP_SRC;
- gpio->gpio_in_idx = GPIOX_18;
- gpio->gpio_in_ao = 0;
- gpio->gpio_out_idx = -1;
- gpio->gpio_out_ao = -1;
- gpio->irq = IRQ_GPIO0_NUM;
- gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
- p->gpio_info_count = ++i;
-}
-extern void __switch_idle_task(void);
-
-static unsigned int detect_key(unsigned int suspend_from)
-{
- int exit_reason = 0;
- unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
- init_remote();
-#ifdef CONFIG_CEC_WAKEUP
- if (hdmi_cec_func_config & 0x1) {
- remote_cec_hw_reset();
- cec_node_init();
- }
-#endif
-
- do {
- #ifdef CONFIG_CEC_WAKEUP
- if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
- irq[IRQ_AO_CECB] = 0xFFFFFFFF;
- if (cec_power_on_check())
- exit_reason = CEC_WAKEUP;
- }
- #endif
- if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
- irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
- if (remote_detect_key())
- exit_reason = REMOTE_WAKEUP;
- }
-
- if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) {
- irq[IRQ_VRTC] = 0xFFFFFFFF;
- exit_reason = RTC_WAKEUP;
- }
-
- if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
- irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
- if ((readl(AO_GPIO_I) & (1<<3)) == 0)
- exit_reason = POWER_KEY_WAKEUP;
- }
-#if 0
- if (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM) {
- irq[IRQ_GPIO1] = 0xFFFFFFFF;
- if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 14))
- && (readl(PREG_PAD_GPIO4_EN_N) & (0x01 << 14)))
- exit_reason = ETH_PHY_GPIO;
- }
-#endif
- if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
- irq[IRQ_GPIO0] = 0xFFFFFFFF;
- if (!(readl(PREG_PAD_GPIO2_I) & (0x01 << 18))
- && (readl(PREG_PAD_GPIO2_O) & (0x01 << 17))
- && !(readl(PREG_PAD_GPIO2_EN_N) & (0x01 << 17)))
- exit_reason = BT_WAKEUP;
- }
-
- if (exit_reason)
- break;
- else
- __switch_idle_task();
- } while (1);
-
- return exit_reason;
-}
-
-static void pwr_op_init(struct pwr_op *pwr_op)
-{
- pwr_op->power_off_at_24M = power_off_at_24M;
- pwr_op->power_on_at_24M = power_on_at_24M;
- pwr_op->detect_key = detect_key;
- pwr_op->get_wakeup_source = get_wakeup_source;
-}
diff --git a/board/amlogic/sm1_elaine_bx/firmware/timing.c b/board/amlogic/sm1_elaine_bx/firmware/timing.c
deleted file mode 100755
index 8c785e8..0000000
--- a/board/amlogic/sm1_elaine_bx/firmware/timing.c
+++ /dev/null
@@ -1,462 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_p1/firmware/timing.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/timing.h>
-#include <asm/arch/ddr_define.h>
-
-/* board clk defines */
-#define DDR_SIZE 0
-#define CPU_CLK 1200
-
-/* ddr config support multiple configs for boards which use same bootloader:
- * config steps:
- * 1. add a new data struct in __ddr_setting[]
- * 2. config correct board_id, ddr_type, freq, etc..
- */
-
-
-/* CAUTION!! */
-/* Confirm ddr configs with hardware designer,
- * if you don't know how to config, then don't edit it
- */
-
-/* Key configs */
-/*
- * board_id: check hardware adc config
- * dram_rank_config:
- * #define CONFIG_DDR_CHL_AUTO 0xF
- * #define CONFIG_DDR0_16BIT_CH0 0x1
- * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
- * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
- * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
- * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
- * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
- * DramType:
- * #define CONFIG_DDR_TYPE_DDR3 0
- * #define CONFIG_DDR_TYPE_DDR4 1
- * #define CONFIG_DDR_TYPE_LPDDR4 2
- * #define CONFIG_DDR_TYPE_LPDDR3 3
- * DRAMFreq:
- * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
- *
- */
-
-
-/* ddr configs */
-#define DDR_RFC_TYPE_DDR3_512Mbx1 0
-#define DDR_RFC_TYPE_DDR3_512Mbx2 1
-#define DDR_RFC_TYPE_DDR3_512Mbx4 2
-#define DDR_RFC_TYPE_DDR3_512Mbx8 3
-#define DDR_RFC_TYPE_DDR3_512Mbx16 4
-#define DDR_RFC_TYPE_DDR4_2Gbx1 5
-#define DDR_RFC_TYPE_DDR4_2Gbx2 6
-#define DDR_RFC_TYPE_DDR4_2Gbx4 7
-#define DDR_RFC_TYPE_DDR4_2Gbx8 8
-
-#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
-#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
-#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
-
-#if CONFIG_DDR_LOGS_ENABLED
-#define LOG_FLAG 0x4
-#else
-#define LOG_FLAG 0xA
-#endif
-
-ddr_set_t __ddr_setting[] = {
- {
- /* Elaine ddr3 */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
- .DramType = CONFIG_DDR_TYPE_DDR3,
- .DRAMFreq = {912, 0, 0, 0},
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 1,
- .HdtCtrl = LOG_FLAG,
- .dram_cs0_size_MB = 1024,
- .dram_cs1_size_MB = 1024,
- .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .clk_drv_ohm = 40,
- .cs_drv_ohm = 40,
- .ac_drv_ohm = 40,
- .soc_data_drv_ohm_p = 34,
- .soc_data_drv_ohm_n = 34,
- .soc_data_odt_ohm_p = 60, //48,
- .soc_data_odt_ohm_n = 0,
- .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
- .dram_data_odt_ohm = 60,
- .dram_ac_odt_ohm = 0,
- .soc_clk_slew_rate = 0x300,
- .soc_cs_slew_rate = 0x300,
- .soc_ac_slew_rate = 0x300,
- .soc_data_slew_rate = 0x200,
- .vref_output_permil = 500,
- .vref_receiver_permil = 500, //700,
- .vref_dram_permil = 500, //700,
-// .vref_reverse = 0,
- .ac_trace_delay ={32,32,32,32,32,32,32,32,32,32},
- //{00,00},
- .ac_pinmux = {00,00},
-#if 1
- .ddr_dmc_remap = {
- [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
- [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
- },
-#else
- //16bit
- .ddr_dmc_remap = {
- [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
- [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
- [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
- [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
- },
-#endif
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap = {00,00},
- .dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
- .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
-},
-{
- /* g12a skt (u209) ddr3 */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
- .DramType = CONFIG_DDR_TYPE_DDR3,
- .DRAMFreq = {912, 0, 0, 0},
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 1,
- .HdtCtrl = LOG_FLAG,
- .dram_cs0_size_MB = 1024,
- .dram_cs1_size_MB = 512,
- .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .pll_ssc_mode = 0,
- .clk_drv_ohm = 40,
- .cs_drv_ohm = 40,
- .ac_drv_ohm = 40,
- .soc_data_drv_ohm_p = 34,
- .soc_data_drv_ohm_n = 34,
- .soc_data_odt_ohm_p = 60, //48,
- .soc_data_odt_ohm_n = 0,
- .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
- .dram_data_odt_ohm = 60,
- .dram_ac_odt_ohm = 0,
- .soc_clk_slew_rate = 0x300,
- .soc_cs_slew_rate = 0x300,
- .soc_ac_slew_rate = 0x300,
- .soc_data_slew_rate = 0x200,
- .vref_output_permil = 500,
- .vref_receiver_permil = 500, //700,
- .vref_dram_permil = 500, //700,
- //{00,00},
- .ac_pinmux = {00,00},
-#if 1
- .ddr_dmc_remap = {
- [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
- [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
- },
-#else
- //16bit
- .ddr_dmc_remap = {
- [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
- [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
- [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
- [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
- },
-#endif
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap = {00,00},
- .dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
- .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
- .slt_test_function = {DMC_TEST_SLT_ENABLE_DDR_SKIP_TRAINING, 0},
- .dfi_hwtmrl = 4,
-
- .ac_trace_delay = {
- 32, 32, 32, 32,
- 32, 32, 32, 32,
- 32, 32,
- },
-
- .write_dqs_delay = {
- 163, 163, 163, 163,
- 167, 167, 165, 165,
- 159, 159, 163, 163,
- 165, 165, 161, 161,
- },
-
- .read_dqs_delay = {
- 13, 13, 14, 14,
- 14, 14, 15, 14,
- 14, 14, 14, 15,
- 14, 13, 14, 14,
- },
-
- .write_dq_bit_delay = {
- 20, 21, 19, 21,
- 21, 21, 22, 20,
- 22, 21, 20, 20,
- 19, 21, 18, 21,
- 20, 20, 24, 20,
- 22, 25, 24, 25,
- 26, 26, 23, 20,
- 21, 20, 23, 21,
- 21, 23, 23, 20,
- 48, 49, 48, 50,
- 50, 50, 51, 49,
- 49, 21, 21, 19,
- 20, 21, 19, 20,
- 21, 20, 22, 18,
- 20, 23, 23, 24,
- 24, 24, 22, 17,
- 18, 17, 20, 18,
- 18, 21, 20, 19,
- },
-
- .read_dq_bit_delay = {
- 15, 15, 15, 23,
- 31, 31, 31, 29,
- 0 , 23, 19, 11,
- 17, 35, 23, 31,
- 31, 0 , 15, 3 ,
- 9 , 15, 27, 27,
- 35, 35, 0 , 13,
- 15, 11, 19, 25,
- 19, 31, 31, 0 ,
- 15, 17, 15, 19,
- 31, 33, 31, 27,
- 0 , 19, 19, 15,
- 13, 31, 23, 27,
- 31, 0 , 13, 3 ,
- 5 , 11, 23, 27,
- 31, 27, 0 , 13,
- 13, 9 , 19, 23,
- 23, 27, 27, 0 ,
- },
-
- .read_dqs_gate_delay = {
- 225, 227, 223, 225,
- 223, 225, 223, 227,
- 223, 225, 223, 225,
- 225, 227, 227, 229,
- },
-
-},
-};
-
-pll_set_t __pll_setting = {
- .cpu_clk = CPU_CLK / 24 * 24,
-#ifdef CONFIG_PXP_EMULATOR
- .pxp = 1,
-#else
- .pxp = 0,
-#endif
- .spi_ctrl = 0,
- .lCustomerID = AML_CUSTOMER_ID,
-#ifdef CONFIG_DEBUG_MODE
- .debug_mode = CONFIG_DEBUG_MODE,
- .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
- .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
-#endif
-};
-
-ddr_reg_t __ddr_reg[] = {
- /* demo, user defined override register */
- {0xaabbccdd, 0, 0, 0, 0, 0},
- {0x11223344, 0, 0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0},
-};
-
-#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
-#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
-/* VCCK PWM table */
-#if (VCCK_VAL == 800)
- #define VCCK_VAL_REG 0x00150007
-#elif (VCCK_VAL == 810)
- #define VCCK_VAL_REG 0x00140008
-#elif (VCCK_VAL == 820)
- #define VCCK_VAL_REG 0x00130009
-#elif (VCCK_VAL == 830)
- #define VCCK_VAL_REG 0x0012000a
-#elif (VCCK_VAL == 840)
- #define VCCK_VAL_REG 0x0011000b
-#elif (VCCK_VAL == 850)
- #define VCCK_VAL_REG 0x0010000c
-#elif (VCCK_VAL == 860)
- #define VCCK_VAL_REG 0x000f000d
-#elif (VCCK_VAL == 870)
- #define VCCK_VAL_REG 0x000e000e
-#elif (VCCK_VAL == 880)
- #define VCCK_VAL_REG 0x000d000f
-#elif (VCCK_VAL == 890)
- #define VCCK_VAL_REG 0x000c0010
-#elif (VCCK_VAL == 900)
- #define VCCK_VAL_REG 0x000b0011
-#elif (VCCK_VAL == 910)
- #define VCCK_VAL_REG 0x000a0012
-#elif (VCCK_VAL == 920)
- #define VCCK_VAL_REG 0x00090013
-#elif (VCCK_VAL == 930)
- #define VCCK_VAL_REG 0x00080014
-#elif (VCCK_VAL == 940)
- #define VCCK_VAL_REG 0x00070015
-#elif (VCCK_VAL == 950)
- #define VCCK_VAL_REG 0x00060016
-#elif (VCCK_VAL == 960)
- #define VCCK_VAL_REG 0x00050017
-#elif (VCCK_VAL == 970)
- #define VCCK_VAL_REG 0x00040018
-#elif (VCCK_VAL == 980)
- #define VCCK_VAL_REG 0x00030019
-#elif (VCCK_VAL == 990)
- #define VCCK_VAL_REG 0x0002001a
-#elif (VCCK_VAL == 1000)
- #define VCCK_VAL_REG 0x0001001b
-#elif (VCCK_VAL == 1010)
- #define VCCK_VAL_REG 0x0000001c
-#else
- #error "VCCK val out of range\n"
-#endif
-
-/* VDDEE PWM table */
-#if (VDDEE_VAL == 800)
- #define VDDEE_VAL_REG 0x0010000c
-#elif (VDDEE_VAL == 810)
- #define VDDEE_VAL_REG 0x000f000d
-#elif (VDDEE_VAL == 820)
- #define VDDEE_VAL_REG 0x000e000e
-#elif (VDDEE_VAL == 830)
- #define VDDEE_VAL_REG 0x000d000f
-#elif (VDDEE_VAL == 840)
- #define VDDEE_VAL_REG 0x000c0010
-#elif (VDDEE_VAL == 850)
- #define VDDEE_VAL_REG 0x000b0011
-#elif (VDDEE_VAL == 860)
- #define VDDEE_VAL_REG 0x000a0012
-#elif (VDDEE_VAL == 870)
- #define VDDEE_VAL_REG 0x00090013
-#elif (VDDEE_VAL == 880)
- #define VDDEE_VAL_REG 0x00080014
-#elif (VDDEE_VAL == 890)
- #define VDDEE_VAL_REG 0x00070015
-#elif (VDDEE_VAL == 900)
- #define VDDEE_VAL_REG 0x00060016
-#elif (VDDEE_VAL == 910)
- #define VDDEE_VAL_REG 0x00050017
-#elif (VDDEE_VAL == 920)
- #define VDDEE_VAL_REG 0x00040018
-#elif (VDDEE_VAL == 930)
- #define VDDEE_VAL_REG 0x00030019
-#elif (VDDEE_VAL == 940)
- #define VDDEE_VAL_REG 0x0002001a
-#elif (VDDEE_VAL == 950)
- #define VDDEE_VAL_REG 0x0001001b
-#elif (VDDEE_VAL == 960)
- #define VDDEE_VAL_REG 0x0000001c
-#else
- #error "VDDEE val out of range\n"
-#endif
-
-/* for PWM use */
-/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
-#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
-#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
-#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
-#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
-#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
-
-bl2_reg_t __bl2_reg[] = {
- /* demo, user defined override register */
- /* eg: PWM init */
-
- /* PWM_AO_D */
- /* VCCK_VAL_REG: check PWM table */
- {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
- {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
- /* PWM_AO_B */
- /* VDDEE_VAL_REG: check PWM table */
- {AO_PWM_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
- {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_1, 0},
- /* Enable 5V_EN */
- {GPIO_O_EN_N_REG3, (0 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
- {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- /* Enable VCCK */
- {AO_SEC_REG0, (1 << 0), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- {AO_GPIO_O, 0x80000000, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
-};
diff --git a/board/amlogic/sm1_elaine_bx/lcd.c b/board/amlogic/sm1_elaine_bx/lcd.c
deleted file mode 100755
index c0d034a..0000000
--- a/board/amlogic/sm1_elaine_bx/lcd.c
+++ /dev/null
@@ -1,451 +0,0 @@
-/*
- * AMLOGIC TV LCD panel driver.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#ifdef CONFIG_AML_LCD_EXTERN
-#include "lcd_extern.h"
-#endif
-
-static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
- "GPIOH_6", /* panel rst */
- "GPIOZ_8", /* panel power */
- "invalid", /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step[] = {
- {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
- {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,50,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_on_step_KD070D82[] = {
- {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_KD070D82[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
- 0x05, 1, 0x11,
- 0xfd, 1, 20,
- 0x05, 1, 0x29,
- 0xfd, 1, 20,
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
- 0x05, 1, 0x28,
- 0xfd, 1, 10,
- 0x05, 1, 0x10,
- 0xfd, 1, 10,
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
- 0xfd, 1, 10,
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
- 0xff, 0, //ending
-};
-
-static unsigned char mipi_init_on_table_KD070D82[DSI_INIT_ON_MAX] = {//table size < 100
- 0xfd, 1, 10,
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_KD070D82[DSI_INIT_OFF_MAX] = {//table size < 50
- 0xff, 0, //ending
-};
-
-static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
- "GPIOH_4", /* BL_EN */
- "GPIOH_5", /* BL_PWM */
- "invalid", /* ending flag */
-};
-
-struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
- {/* TV070WSM_FT9364*/
- "boe_fiti9364_7",LCD_MIPI,8,
- /* basic timing */
- 600,1024,700,1053,24,36,0,2,8,0,
- /* clk_attr */
- 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,360,0,1,0,2,0,0,Rsv_val,1,
- /* cmd init */
- mipi_init_on_table, mipi_init_off_table,
- /* power step */
- lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* TV070WSM_FT9365*/
- "boe_fiti9365_7",LCD_MIPI,8,
- /* basic timing */
- 600,1024,700,1053,24,36,0,2,8,0,
- /* clk_attr */
- 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,360,0,1,0,2,0,0,Rsv_val,2,
- /* cmd init */
- mipi_init_on_table, mipi_init_off_table,
- /* power step */
- lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* KD070D82_FT9364*/
- "kd_fiti9364_7",LCD_MIPI,8,
- /* basic timing */
- 600,1024,770,1070,10,80,0,6,20,0,
- /* clk_attr */
- 0,0,1,49434000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,400,0,1,0,2,0,0,Rsv_val,3,
- /* cmd init */
- mipi_init_on_table_KD070D82, mipi_init_off_table_KD070D82,
- /* power step */
- lcd_power_on_step_KD070D82, lcd_power_off_step_KD070D82,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* KD070D82_FT9365*/
- "kd_fiti9365_7",LCD_MIPI,8,
- /* basic timing */
- 600,1024,770,1070,10,80,0,6,20,0,
- /* clk_attr */
- 0,0,1,49434000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,400,0,1,0,2,0,0,Rsv_val,4,
- /* cmd init */
- mipi_init_on_table_KD070D82, mipi_init_off_table_KD070D82,
- /* power step */
- lcd_power_on_step_KD070D82, lcd_power_off_step_KD070D82,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* TV070WSM_ST7703I*/
- "boe_sit7703_7",LCD_MIPI,8,
- /* basic timing */
- 600,1024,770,1070,10,80,0,6,20,0,
- /* clk_attr */
- 0,0,1,49434000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,400,0,1,0,2,0,0,Rsv_val,5,
- /* cmd init */
- mipi_init_on_table, mipi_init_off_table,
- /* power step */
- lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {.panel_type = "invalid"},
-};
-
-static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
- {
- .name = "lcd_pin",
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
- },
- {
- .name = "invalid",
- },
-};
-
-static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
- {
- .name = "bl_pwm_on_pin", //GPIOH_5
- .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
- },
- {
- .name = "invalid",
- },
-};
-
-#ifdef CONFIG_AML_BL_EXTERN
-static unsigned char bl_ext_init_on[BL_EXTERN_INIT_ON_MAX] = {
- 0xff, 0, //ending flag
-};
-static unsigned char bl_ext_init_off[BL_EXTERN_INIT_OFF_MAX] = {
- 0xff, 0, //ending flag
-};
-#endif
-
-/* **********************************************
- * driver struct, usually no need modify!
- * ********************************************** */
-static struct dsi_config_s lcd_mipi_config = {
- .lane_num = 4,
- .bit_rate_max = 1000, /* MHz */
- .factor_numerator = 0,
- .factor_denominator = 100,
- .operation_mode_init = 1, /* 0=video mode, 1=command mode */
- .operation_mode_display = 0, /* 0=video mode, 1=command mode */
- .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
- .clk_always_hs = 1, /* 0=disable, 1=enable */
- .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
-
- .dsi_init_on = mipi_init_on_table,
- .dsi_init_off = mipi_init_off_table,
- .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
- .check_en = 0,
- .check_state = 0,
-};
-
-static struct lcd_power_ctrl_s lcd_power_ctrl = {
- .power_on_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
- .power_off_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
-};
-
-struct lcd_config_s lcd_config_dft = {
- .lcd_mode = LCD_MODE_TABLET,
- .lcd_key_valid = 0,
- .lcd_clk_path = 0,
- .lcd_basic = {
- .model_name = "default",
- .lcd_type = LCD_TYPE_MAX,
- .lcd_bits = 8,
- .h_active = 768,
- .v_active = 1024,
- .h_period = 948,
- .v_period = 1140,
-
- .screen_width = 119,
- .screen_height = 159,
- },
-
- .lcd_timing = {
- .clk_auto = 1,
- .lcd_clk = 64843200,
- .ss_level = 0,
- .fr_adjust_type = 0,
-
- .hsync_width = 64,
- .hsync_bp = 56,
- .hsync_pol = 0,
- .vsync_width = 50,
- .vsync_bp = 30,
- .vsync_pol = 0,
- },
-
- .lcd_control = {
- .mipi_config= &lcd_mipi_config,
- },
- .lcd_power = &lcd_power_ctrl,
-
- .pinctrl_ver = 2,
- .lcd_pinmux = lcd_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_LCD_EXTERN
-struct lcd_extern_common_s ext_common_dft = {
- .lcd_ext_key_valid = 0,
- .i2c_bus = LCD_EXTERN_I2C_BUS_0, /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
- .i2c_gpio_sck = LCD_EXT_I2C_GPIO_SCK,
- .i2c_gpio_sda = LCD_EXT_I2C_GPIO_SDA,
- .spi_gpio_cs = LCD_EXT_SPI_GPIO_CS,
- .spi_gpio_clk = LCD_EXT_SPI_GPIO_CLK,
- .spi_gpio_data = LCD_EXT_SPI_GPIO_DATA,
-
- .lcd_ext_pinmux = lcd_ext_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
- .pinmux_gpio_off = LCD_EXT_PINMUX_GPIO_OFF,
-};
-
-struct lcd_extern_config_s ext_config_dtf = {
- .index = 0,
- .name = "ext_default",
- .type = LCD_EXTERN_MAX, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 0, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
-};
-#endif
-
-struct bl_config_s bl_config_dft = {
- .name = "default",
- .bl_key_valid = 0,
-
- .level_default = 100,
- .level_min = 10,
- .level_max = 255,
- .level_mid = 128,
- .level_mid_mapping = 128,
- .level = 0,
-
- .method = BL_CTRL_MAX,
- .power_on_delay = 20,
- .power_off_delay = 20,
-
- .en_gpio = 0xff,
- .en_gpio_on = 1,
- .en_gpio_off = 0,
-
- .bl_pwm = NULL,
- .bl_pwm_combo0 = NULL,
- .bl_pwm_combo1 = NULL,
- .pwm_on_delay = 10,
- .pwm_off_delay = 10,
-
- .bl_extern_index = 0xff,
-
- .pinctrl_ver = 2,
- .bl_pinmux = bl_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_BL_EXTERN
-struct bl_extern_config_s bl_extern_config_dtf = {
- .index = BL_EXTERN_INDEX_INVALID,
- .name = "none",
- .type = BL_EXTERN_MAX,
- .i2c_addr = 0xff,
- .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
- .dim_min = 10,
- .dim_max = 255,
-
- .init_loaded = 0,
- .cmd_size = 0xff,
- .init_on = bl_ext_init_on,
- .init_off = bl_ext_init_off,
- .init_on_cnt = sizeof(bl_ext_init_on),
- .init_off_cnt = sizeof(bl_ext_init_off),
-};
-#endif
-/* ********************************************** */
-
-void lcd_config_bsp_init(void)
-{
- int i, j;
- char *str;
- struct ext_lcd_config_s *ext_lcd = NULL;
-
- /* init config, usually no need modify */
- for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
- break;
- strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
- }
- for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
- strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
- for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
- break;
- strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
- }
- for (j = i; j < BL_GPIO_NUM_MAX; j++)
- strcpy(bl_config_dft.gpio_name[j], "invalid");
-
-#ifdef CONFIG_AML_LCD_EXTERN
- for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
- break;
- strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
- }
- for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
- strcpy(ext_common_dft.gpio_name[j], "invalid");
-#endif
-
- /* select special config */
- str = env_get("panel_type");
- if (str == NULL)
- return;
- for (i = 0 ; i < LCD_NUM_MAX ; i++) {
- ext_lcd = &ext_lcd_config[i];
- if (strcmp(ext_lcd->panel_type, str) == 0) {
-#ifdef CONFIG_AML_LCD_EXTERN
- j = ext_lcd->if_attr_val9; /* mipi extern_index */
- if (j < sizeof(ext_config)/sizeof(struct lcd_extern_config_s)) {
- memcpy(&ext_config_dtf, &ext_config[j],
- sizeof(struct lcd_extern_config_s));
- }
-#endif
- break;
- }
- }
-}
diff --git a/board/amlogic/sm1_elaine_bx/lcd_extern.h b/board/amlogic/sm1_elaine_bx/lcd_extern.h
deleted file mode 100755
index e49e89f..0000000
--- a/board/amlogic/sm1_elaine_bx/lcd_extern.h
+++ /dev/null
@@ -1,124 +0,0 @@
-/*
- * board/amlogic/sm1_elaine_bx/lcd_extern.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _DFT_LCD_EXTERN_H_
-#define _DFT_LCD_EXTERN_H_
-
-#define LCD_EXT_I2C_GPIO_SCK 0xff /* 0xff for invalid */
-#define LCD_EXT_I2C_GPIO_SDA 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_CS 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_CLK 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_DATA 0xff /* 0xff for invalid */
-#define LCD_EXT_PINMUX_GPIO_OFF 0
-
-static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
- "invalid", /* ending flag */
-};
-
-static struct lcd_pinmux_ctrl_s lcd_ext_pinmux_ctrl[LCD_PINMX_MAX] = {
- {
- .name = "invalid",
- },
-};
-
-static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
- 0xff, 0, //ending flag
-};
-
-static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
- 0xff, 0, //ending flag
-};
-
-static struct lcd_extern_config_s ext_config[LCD_EXTERN_NUM_MAX] = {
- {
- .index = 0,
- .name = "ext_default",
- .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 0, /* 0=disable, 1=enable */
- .i2c_addr = 0x1c, /* 7bit i2c address */
- .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for invalid */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- { /* TV070WSM_FT9364 */
- .index = 1,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- /*we define initial codes in panel.dtsi*/
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- { /* TV070WSM_FT9365 */
- .index = 2,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- /*we define initial codes in panel.dtsi*/
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- { /* KD070D82_FT9364*/
- .index = 3,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- /*we define initial codes in panel.dtsi*/
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- { /* KD070D82_FT9365*/
- .index = 4,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- /*we define initial codes in panel.dtsi*/
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- { /* TV070WSM_ST7703I*/
- .index = 5,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- /*we define initial codes in panel.dtsi*/
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- {
- .index = LCD_EXTERN_INDEX_INVALID,
- },
-};
-
-#endif
-
diff --git a/board/amlogic/sm1_elaine_bx/pwm_table.c b/board/amlogic/sm1_elaine_bx/pwm_table.c
deleted file mode 100755
index 18dc638..0000000
--- a/board/amlogic/sm1_elaine_bx/pwm_table.c
+++ /dev/null
@@ -1,71 +0,0 @@
-#include <common.h>
-
-const int pwm_cal_voltage_table[][2] = {
- { 0x1c0000, 860},
- { 0x1b0001, 870},
- { 0x1a0002, 880},
- { 0x190003, 890},
- { 0x180004, 900},
- { 0x170005, 910},
- { 0x160006, 920},
- { 0x150007, 930},
- { 0x140008, 940},
- { 0x130009, 950},
- { 0x12000a, 960},
- { 0x11000b, 970},
- { 0x10000c, 980},
- { 0x0f000d, 990},
- { 0x0e000e, 1000},
- { 0x0d000f, 1010},
- { 0x0c0010, 1020},
- { 0x0b0011, 1030},
- { 0x0a0012, 1040},
- { 0x090013, 1050},
- { 0x080014, 1060},
- { 0x070015, 1070},
- { 0x060016, 1080},
- { 0x050017, 1090},
- { 0x040018, 1100},
- { 0x030019, 1110},
- { 0x02001a, 1120},
- { 0x01001b, 1130},
- { 0x00001c, 1140}
-};
-const int pwm_cal_voltage_table_ee[][2] = {
- { 0x1c0000, 810},
- { 0x1b0001, 820},
- { 0x1a0002, 830},
- { 0x190003, 840},
- { 0x180004, 850},
- { 0x170005, 860},
- { 0x160006, 870},
- { 0x150007, 880},
- { 0x140008, 890},
- { 0x130009, 900},
- { 0x12000a, 910},
- { 0x11000b, 920},
- { 0x10000c, 930},
- { 0x0f000d, 940},
- { 0x0e000e, 950},
- { 0x0d000f, 960},
- { 0x0c0010, 970},
- { 0x0b0011, 980},
- { 0x0a0012, 990},
- { 0x090013, 1000},
- { 0x080014, 1010},
- { 0x070015, 1020},
- { 0x060016, 1030},
- { 0x050017, 1040},
- { 0x040018, 1050},
- { 0x030019, 1060},
- { 0x02001a, 1070},
- { 0x01001b, 1080},
- { 0x00001c, 1090}
-};
-
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
-int pwm_cal_voltage_table_size = ARRAY_SIZE(pwm_cal_voltage_table);
-int pwm_cal_voltage_table_ee_size = ARRAY_SIZE(pwm_cal_voltage_table_ee);
-
-
diff --git a/board/amlogic/sm1_elaine_bx/sm1_elaine_bx.c b/board/amlogic/sm1_elaine_bx/sm1_elaine_bx.c
deleted file mode 100755
index 2e1ff3d..0000000
--- a/board/amlogic/sm1_elaine_bx/sm1_elaine_bx.c
+++ /dev/null
@@ -1,1231 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_p1/sm1_elaine_bx.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <malloc.h>
-#include <errno.h>
-#include <environment.h>
-#include <fdt_support.h>
-#include <linux/libfdt.h>
-#include <asm/arch/cpu_id.h>
-#ifdef CONFIG_SYS_I2C_MESON
-#include <i2c.h>
-#include <dt-bindings/i2c/meson-i2c.h>
-#endif
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/pinctrl_init.h>
-#ifdef CONFIG_AML_VPU
-#include <amlogic/media/vpu/vpu.h>
-#endif
-#ifdef CONFIG_AML_VPP
-#include <amlogic/media/vpp/vpp.h>
-#endif
-#ifdef CONFIG_AML_V2_FACTORY_BURN
-#include <amlogic/aml_v2_burning.h>
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
-#ifdef CONFIG_AML_HDMITX
-#include <amlogic/media/vout/hdmitx.h>
-#endif
-#ifdef CONFIG_AML_LCD
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#endif
-#include <asm/arch/bl31_apis.h>
-#include <asm/arch/eth_setup.h>
-#include <phy.h>
-#include <linux/mtd/partitions.h>
-#include <linux/sizes.h>
-#include <asm-generic/gpio.h>
-#include <dm.h>
-#ifdef CONFIG_AML_SPIFC
-#include <amlogic/spifc.h>
-#endif
-#ifdef CONFIG_AML_SPICC
-#include <amlogic/spicc.h>
-#endif
-#include <asm/armv8/mmu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int persistent_brightness = -1;
-
-int do_check_fdr_for_backlight_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-#if defined(CONFIG_NAND_FTS) || defined(CONFIG_MMC_FTS)
-#if defined(CONFIG_NAND_FTS)
- extern bool amlnf_is_inited(void);
- if(!amlnf_is_inited()) {
-#endif
-
-#if defined(CONFIG_MMC_FTS)
- extern bool amlmmc_is_inited(void);
- if (!amlmmc_is_inited()) {
-#endif
-
- return 0;
- }
-
- flash_ts_init();
-
- static const char *fts_key = "bootloader.recovery";
- static const char *fdr = "--wipe_data";
- static const int fdr_len = sizeof(fdr) - 1;
- int i;
-
- char fts_value[256] = { 0 };
- flash_ts_get(fts_key, fts_value, sizeof(fts_value));
- int fts_len = strnlen(fts_value, sizeof(fts_value));
- for (i = 0; i <= fts_len - fdr_len; i++) {
- if (0 == strncmp(fts_value+i, fdr, fdr_len)) {
- printf("Reset persistent brightness.\n");
- writel(0, AO_RTI_STICKY_REG2);
- break;
- }
- }
-#endif
-
- return 0;
-}
-
-U_BOOT_CMD(
- check_fdr_for_backlight_brightness, 1, 0, do_check_fdr_for_backlight_brightness,
- "check FDR for backlight brightness",
- " This command will clear backlight brightness level stored in the sticky register when doing FDR\n"
-);
-
-int serial_set_pin_port(unsigned long port_base)
-{
- //UART in "Always On Module"
- //GPIOAO_0==tx,GPIOAO_1==rx
- //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
- return 0;
-}
-
-//SOC_VDDCPU_DVFS0
-//#define VDD_CPU_DVFS0_EN_1 GPIOEE(GPIOZ_13)
-#define VDD_CPU_DVFS0_EN_1_NAME "GPIOZ_13"
-
-//SOC_VDDEE_DVFS0
-//#define VDD_GPU_DVFS0_EN_1 GPIOEE(GPIOA_13)
-#define VDD_GPU_DVFS0_EN_1_NAME "GPIOA_13"
-
-//SOC_VDDEE_DVFS1
-//#define VDD_GPU_DVFS1_EN_1 GPIOEE(GPIOZ_0)
-#define VDD_GPU_DVFS1_EN_1_NAME "GPIOZ_0"
-
-/* setting gpio output/input, and setting High/low level */
-static void gpio_func_set(bool enable, const char* gpio_name, int direction)
-{
- int ret;
- struct gpio_desc gpio_set_desc;
-
- ret = dm_gpio_lookup_name(gpio_name, &gpio_set_desc);
- if (ret) {
- printf("%s: not found\n", gpio_name);
- return ret;
- }
-
- ret = dm_gpio_request(&gpio_set_desc, gpio_name);
- if (ret && ret != -EBUSY) {
- printf("gpio: requesting pin %s failed\n", gpio_name);
- return;
- }
- //gpio_direction_output(BL_ENABLE_PIN, enable ? 1 : 0);
- ret = dm_gpio_set_dir_flags(&gpio_set_desc, direction);
- if (ret) {
- printf("set direction failed\n");
- return ret;
- }
-
- if ( direction == GPIOD_IS_OUT)
- dm_gpio_set_value(&gpio_set_desc, enable ? 1 : 0);
-}
-static void CPU_GPU_Voltage_init(void)
-{
- int ret;
- // setting GPIOZ_13 output & High
- gpio_func_set(1, VDD_CPU_DVFS0_EN_1_NAME, GPIOD_IS_OUT);
-
- //GPU , setting GPIOA_13 output & low
- gpio_func_set(0, VDD_GPU_DVFS0_EN_1_NAME, GPIOD_IS_OUT);
-
- // setting GPIOZ_0 output & low
- gpio_func_set(1, VDD_GPU_DVFS1_EN_1_NAME, GPIOD_IS_OUT);
-}
-
-// Disable GPIOZ_2, GPIOZ_3, GPIOZ_7, GPIOZ_8, GPIOZ_0, GPIOAO_4's pull-up
-// so the mute switch and HW id can be read.
-static void gpio_disable_pull(void)
-{
- int ret;
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 2)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 7)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 8)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 3)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(AO_RTI_PULL_UP_EN_REG);
- writel(ret & (~(1 << 4)), AO_RTI_PULL_UP_EN_REG);
-}
-
-int do_get_elaine_hw_id(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- unsigned int hw_id = 0, ret = 0;
- char hw_id_str[8] = {0}; // eg: 0x0A
-
- // Reading from highest bit to lowest bit
- // HW_ID_4: GPIOAO_4
- ret = readl(P_AO_GPIO_I);
- hw_id |= (ret & (1<<4)) >> 4;
- hw_id = hw_id << 1;
-
- // HW_ID_3: GPIOZ_0
- ret = readl(P_PREG_PAD_GPIO4_I);
- hw_id |= (ret & 1);
- hw_id = hw_id << 1;
-
- // HW_ID_2: GPIOZ_3
- ret = readl(P_PREG_PAD_GPIO4_I);
- hw_id |= (ret & (1<<3)) >> 3;
- hw_id = hw_id << 1;
-
- // HW_ID_1: GPIOZ_8
- ret = readl(P_PREG_PAD_GPIO4_I);
- hw_id |= (ret & (1<<8)) >> 8;
- hw_id = hw_id << 1;
-
- // HW_ID_0: GPIOZ_7
- ret = readl(P_PREG_PAD_GPIO4_I);
- hw_id |= (ret & (1<<7)) >> 7;
-
- snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id);
- env_set("hw_id", hw_id_str);
- return 0;
-}
-
-U_BOOT_CMD(
- get_elaine_hw_id, 1, 0, do_get_elaine_hw_id,
- "get elaine's HW_ID and env_set 'hw_id'\n",
- "get_elaine_hw_id"
-);
-
-#define BOOST_ENABLE_PIN_NAME "GPIOA_0"
-int do_enable_amp_boost(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- gpio_func_set(1, BOOST_ENABLE_PIN_NAME, GPIOD_IS_OUT);
-}
-
-U_BOOT_CMD(
- enable_amp_boost, 1, 0, do_enable_amp_boost,
- "Enable the audio amplifier boost\n",
- "enable_boost"
-);
-
-//SOC_DISP_ID
-//#define DISP_ID_PIN GPIOEE(GPIOH_5)
-#define DISP_ID_PIN_NAME "GPIOH_5"
-
-static void panel_detect_init(void)
-{
- // setting GPIOH_5 output & High
- gpio_func_set(1, DISP_ID_PIN_NAME, GPIOD_IS_IN);
-}
-
-//SOC_BL_ENABLE
-//#define BL_ENABLE_PIN GPIOEE(GPIOA_10)
-#define BL_ENABLE_PIN_NAME "GPIOA_10"
-
-static void enable_backlight(bool enable)
-{
- // setting GPIOH_5 output & High
- gpio_func_set(enable, BL_ENABLE_PIN_NAME, GPIOD_IS_OUT);
-}
-
-int dram_init(void)
-{
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-/* secondary_boot_func
- * this function should be write with asm, here, is is only for compiling pass
- * */
-void secondary_boot_func(void)
-{
-}
-
-#if CONFIG_AML_SD_EMMC
-#include <mmc.h>
-#include <asm/arch/sd_emmc.h>
-static int sd_emmc_init(unsigned port)
-{
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
- //todo add card detect
- /* check card detect */
- clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
- setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
- setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
- setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
- break;
- case SDIO_PORT_C:
- //enable pull up
- //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
- break;
- default:
- break;
- }
-
- return cpu_sd_emmc_init(port);
-}
-
-extern unsigned sd_debug_board_1bit_flag;
-
-static void sd_emmc_pwr_prepare(unsigned port)
-{
- cpu_sd_emmc_pwr_prepare(port);
-}
-
-static void sd_emmc_pwr_on(unsigned port)
-{
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
-// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
-// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
- /// @todo NOT FINISH
- break;
- case SDIO_PORT_C:
- break;
- default:
- break;
- }
- return;
-}
-static void sd_emmc_pwr_off(unsigned port)
-{
- /// @todo NOT FINISH
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
-// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
-// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
- break;
- case SDIO_PORT_C:
- break;
- default:
- break;
- }
- return;
-}
-
-// #define CONFIG_TSD 1
-static void board_mmc_register(unsigned port)
-{
- struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
- if (aml_priv == NULL)
- return;
-
- aml_priv->sd_emmc_init=sd_emmc_init;
- aml_priv->sd_emmc_detect=sd_emmc_detect;
- aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
- aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
- aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
- aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
-
- if (NULL == aml_priv->desc_buf)
- printf(" desc_buf Dma alloc Fail!\n");
- else
- printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
-
- sd_emmc_register(aml_priv);
-}
-int board_mmc_init(bd_t *bis)
-{
-#ifdef CONFIG_VLSI_EMULATOR
- //board_mmc_register(SDIO_PORT_A);
-#else
- //board_mmc_register(SDIO_PORT_B);
-#endif
- board_mmc_register(SDIO_PORT_B);
- board_mmc_register(SDIO_PORT_C);
-// board_mmc_register(SDIO_PORT_B1);
- return 0;
-}
-#endif
-
-/* Skip the first line and parse one uint
- * Return negative if not found */
-int parse_calibration_file_string(const char *str)
-{
- if (str == NULL)
- return -EINVAL;
-
- str = strchr(str, '\n');
- if (str == NULL)
- return -EINVAL;
- ++str;
-
- return simple_strtoul(str, NULL, 10);
-}
-
-/* If zero, this value has not been set and the default brightness should not be
- * overwritten. To store zero, store a non-zero value with its bottom 12 bits
- * all zero, like 0x1000.
- */
-int get_persistent_brightness_from_reg(void)
-{
- u32 brightness_sticky_val = readl(AO_RTI_STICKY_REG2);
- if (brightness_sticky_val != 0)
- return (brightness_sticky_val & 0x0fff) >> 1;
- return -1;
-}
-
-int do_configure_backlight(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
-#ifdef CONFIG_SYS_I2C_MESON
- int ret, i, attempt;
- const int retries = 3;
- char *addr_cal;
- int calibrated_current;
-
- /* Values to write:
- * [0]: Brightness register control only, backlight enabled
- * [1-2]: Standby disabled, 20mA MAX_CURRENT, CURRENT scale 1/2
- * [3]: Enable undervoltage protection at 5.2 V, "disable" backlight
- * (i2c only), disable set resistors
- * [4]: 9.6kHz PWM rate, 3 phase drivers
- * [5]: EN_DRV3, EN_DRV2, boost inductor current limit = 1.6 A
- * [6]: VBOOST_MAX = 25 V, JUMP_EN = 0
- * [7]: STEP_UP = 105 mV, STEP_DN = 105 mV, LED_FAULT_TH = 3V,
- * LED_COMP_HYST = DRIVER_HEADROOM + 750 mV
- * [8-9]: 12-bit brightness (default: 100%)
- * Important: Write brightness last to apply current calibration */
- const __u8 addrs[] = {0x01, 0xa0, 0xa1, 0xa2, 0xa5, 0xa7, 0xa9, 0xae,
- 0x10, 0x11};
- __u8 values[] = {0x85, 0xff, 0x37, 0x30, 0x54, 0xf4, 0x60, 0x09, 0xff,
- 0x0f};
- const int n_bytes = sizeof(values)/sizeof(values[0]);
- struct udevice *bl_devp = NULL;
-
- if (argc > 2) {
- printf("%s: Too many args: %d\n", __func__, argc);
- return CMD_RET_USAGE;
- }
-
- if (argc == 2) {
- addr_cal = (char *)simple_strtoul(argv[1], NULL, 16);
- calibrated_current = parse_calibration_file_string(addr_cal);
- if (calibrated_current >= 0 && calibrated_current <= 4095) {
- /* CURRENT_LSB */
- values[1] = 0xff & calibrated_current;
- /* CURRENT_MSB */
- values[2] = (values[2] & 0xf0) |
- (0x0f & (calibrated_current >> 8));
- }
- }
-
- // Apply persistent brightness if found
- if (persistent_brightness >= 0) {
-#ifdef BL33_DEBUG_PRINT
- printf("Applying persistent_brightness=%d\n", persistent_brightness);
-#endif
- /* Get LSB and MSB */
- values[n_bytes - 2] = persistent_brightness & 0xff;
- values[n_bytes - 1] = persistent_brightness >> 8 & 0x0f;
- } else {
-#ifdef BL33_DEBUG_PRINT
- printf("Persistent_brightness not set\n");
-#endif
- }
-
- enable_backlight(true);
-
- ret = i2c_get_chip_for_busnum(MESON_I2C_M3, 0X2c, 1, &bl_devp);
- if (ret) {
- printf("%s(%d):i2c get bus fail!\n", __func__, __LINE__);
- return -1;
- }
- //i2c_set_bus_num(AML_I2C_MASTER_D);
- for (i = 0; i < n_bytes; ++i) {
- for (attempt = 0; attempt < retries; ++attempt) {
- ret = dm_i2c_write(bl_devp, addrs[i], &values[i], 1);
- if (ret)
- printf("%s: Attempt=%d to write byte=0x%02x to reg=0x%02x of backlight failed\n",
- __func__, attempt, values[i], addrs[i]);
- else
- break;
- }
- }
-
- return ret;
-#else
- enable_backlight(true);
-
- return 0;
-#endif /* CONFIG_SYS_I2C_MESON */
-}
-
-U_BOOT_CMD(
- configure_backlight, 2, 0, do_configure_backlight,
- "configures the lp8556 backlight",
- "Usage: configure_backlight [calibration_string_addr]\n"\
- " Sets up required parameters of the backlight.\n"\
- " Default calibration is 100%.\n"\
- " calibration_str_addr (optional):\n"\
- " Address of calibration file string to parse.\n"
-);
-
-#ifdef CONFIG_AML_LCD
-int lcd_enable_extern(char* mode)
-{
- struct aml_lcd_drv_s *lcd_drv = NULL;
-
- lcd_drv = aml_lcd_get_driver();
- if (lcd_drv && lcd_drv->lcd_enable) {
- lcd_drv->lcd_enable(mode);
- }
- return 0;
-}
-int st7703i_init()
-{
- /*set new panel_type*/
- env_set("panel_type", "boe_sit7703_7");
-
- /*lcd_probe again*/
- /*get dts info to struct*/
- lcd_probe();
- return 0;
-}
-
-int do_get_lcd_extern_panel_type(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- int i, reg_cnt = 0;
- unsigned long ddic_reg = 0;
- unsigned int st7703i_reg = 0;
- unsigned int st7703i_flag = 0;
- struct aml_lcd_drv_s *lcd_drv = NULL;
- unsigned int boe_fiti9365_check_reg = 0x936504;
- unsigned int boe_st7703i_check_reg[3] = {0x38, 0x21, 0x1F};
-
- lcd_drv = aml_lcd_get_driver();
- /*set default panel_type*/
- if (!strcmp(env_get("panel_type"), "boe_fiti9365_7")) {
- /*lcd enable & lcd disable to get ddic_reg*/
- lcd_enable_extern(env_get("outputmode"));
- if (lcd_drv && lcd_drv->lcd_disable) {
- lcd_drv->lcd_disable();
- }
- /*read ddic register value & check ddic reg value*/
- /*only save bit0~bit31*/
- ddic_reg = simple_strtoul(env_get("ddic_reg"), NULL, 16);
- reg_cnt = ddic_reg >> 24;
- if ((reg_cnt == 3) && (boe_fiti9365_check_reg == (ddic_reg & 0xffffff))) {
- return 0;/*boe_fiti9365_7*/
- } else {
- /*set panel_type to boe_sit7703_7 and retry*/
- st7703i_init();
- return 1;
- }
- }
- return 0;
-}
-
-U_BOOT_CMD(
- get_lcd_extern_panel_type, 1, 0, do_get_lcd_extern_panel_type,
- "get lcd exetern panel type flag\n",
- "Usage: get_lcd_extern_panel_type\n"\
- " return value: 1(panel_type=boe_7703_7)\n"\
- " 0(panel_type=boe_fiti9365_7\n"
-);
-#endif/*CONFIG_AML_LCD*/
-
-int do_get_cached_brightness(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- char *file_str_addr;
-
- if (argc > 2) {
- printf("%s: Too many args: %d\n", __func__, argc);
- return CMD_RET_USAGE;
- }
-
- // Apply persistent brightness if found in sticky register.
- persistent_brightness = get_persistent_brightness_from_reg();
- if (persistent_brightness >= 0) {
- return 0;
- }
-
- if (argc != 2) {
- return 0;
- }
-
-#ifdef BL33_DEBUG_PRINT
- printf("Don't have the sticky register set. Will read from cached brightness on disk.", persistent_brightness);
-#endif
-
- file_str_addr = (char *)simple_strtoul(argv[1], NULL, 16);
-
- if (file_str_addr) {
- // The file should be consist of one number.
- persistent_brightness = simple_strtoul(file_str_addr, NULL, 10);
-#ifdef BL33_DEBUG_PRINT
- printf("Applying brightness from file %d", file_str_addr, persistent_brightness);
-#endif
- }
- return 0;
-}
-
-U_BOOT_CMD(
- get_cached_brightness, 2, 0, do_get_cached_brightness,
- "Gets the cached backlight value",
- "Usage: get_cached_brightness [brightness_str_address]\n"\
- " Gets the cached backlight value.\n"\
- " brightness_str_addr (optional):\n"\
- " Address of cached brightness file string to parse.\n"
-);
-
-#ifdef CONFIG_AML_LCD
-/* Parses one line of the gamma calibration file. */
-/* Returns true on success. */
-#define GAMMA_SIZE (256)
-bool parse_gamma_string(const char *str, uint16_t *table)
-{
- char buf[4] = {'\0'};
- int i;
-
- for (i = 0; i < GAMMA_SIZE; ++i) {
- strncpy(buf, &str[3 * i], 3);
- table[i] = simple_strtol(buf, NULL, 16);
- }
-
- return true;
-}
-
-/* Check header then parse RGB gamma tables */
-/* Returns negative value on error */
-int parse_gamma_calibration_file_string(const char *str, u16 *r, u16 *g, u16 *b)
-{
- static const char supported_header_prefix[] = "Gamma Calibration 1.";
- static const int length = sizeof(supported_header_prefix) - 1;
- char *tables[3] = {r, g, b};
- const char *start, *end;
- int i;
-
- if (!str)
- return -EINVAL;
-
- // Check header prefix - only care about major version.
- if (strncmp(str, supported_header_prefix, length) != 0) {
- printf("Unknown gamma header: \"%.*s\"\n", length, str);
- return -EINVAL;
- }
-
- // Parse all three tables
- end = strchr(str, '\n');
- for (i = 0; i < 3; ++i) {
- start = end + 1;
- end = strchr(start, '\n');
-
- if ((end - start) / 3 != GAMMA_SIZE) {
- printf("Gamma table has invalid length.\n");
- return -EINVAL;
- }
- if (!parse_gamma_string(start, tables[i])) {
- printf("Could not parse gamma table %d.\n", i);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-#endif // CONFIG_AML_LCD
-
-int do_configure_gamma(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
-#ifdef CONFIG_AML_LCD
- static const int N_CHAN = 3;
- char *addr_cal;
- u16 gamma_tables[N_CHAN][GAMMA_SIZE];
- int i, j;
-
- if (argc == 1) {
- // Set to default
- for (i = 0; i < N_CHAN; ++i) {
- for (j = 0; j < GAMMA_SIZE; ++j)
- gamma_tables[i][j] = j << 2; /* 10-bit */
- }
- } else if (argc == 2) {
- // Load from passed file string
- addr_cal = (char *)simple_strtoul(argv[1], NULL, 16);
- if (parse_gamma_calibration_file_string(addr_cal,
- &gamma_tables[0],
- &gamma_tables[1],
- &gamma_tables[2]) != 0)
- return -EINVAL; // Error logged
- } else {
- return CMD_RET_USAGE;
- }
-
- vpp_set_rgb_gamma_table(&gamma_tables[0], &gamma_tables[1],
- &gamma_tables[2]);
-#endif // CONFIG_AML_LCD
- return 0;
-}
-
-U_BOOT_CMD(configure_gamma, 2, 0, do_configure_gamma,
- "configures gamma the gamma tables with the provided calibration\n",
- "Usage: configure_gamma [calibration_string_addr]\n"\
- " Applies the provided calibration file.\n"\
- " If a file is not provided, sets tables to default.\n"\
- " calibration_str_addr (optional):\n"\
- " Address of the calibration file string to parse.\n"
-);
-
-int do_get_chiptype(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- char *type[] = {"SS", "TT", "FF"};
- unsigned int dvfs_id = aml_get_dvfs_id();
- printf("get dvfs_id:%d\n", dvfs_id);
- if (dvfs_id > 2) {
- printf("fail to get dvfs id\n");
- dvfs_id = 0;
- }
- env_set("chip_type", type[dvfs_id]);
- return 0;
-}
-U_BOOT_CMD(get_chiptype, 1, 0, do_get_chiptype,
- "get elaine's chip type and env_set 'chip_type'\n",
- "get_chiptype"
-);
-
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
-int board_early_init_f(void){
- /*add board early init function here*/
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
-#include <asm/arch/usb-v2.h>
-#include <asm/arch/gpio.h>
-#define CONFIG_GXL_USB_U2_PORT_NUM 2
-
-#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
-#define CONFIG_GXL_USB_U3_PORT_NUM 1
-#else
-#define CONFIG_GXL_USB_U3_PORT_NUM 0
-#endif
-
-static void gpio_set_vbus_power(char is_power_on)
-{
- int ret;
-
- ret = gpio_request(CONFIG_USB_GPIO_PWR,
- CONFIG_USB_GPIO_PWR_NAME);
- if (ret && ret != -EBUSY) {
- printf("gpio: requesting pin %u failed\n",
- CONFIG_USB_GPIO_PWR);
- return;
- }
-
- if (is_power_on) {
- gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
- } else {
- gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
- }
-}
-
-struct amlogic_usb_config g_usb_config_GXL_skt={
- CONFIG_GXL_XHCI_BASE,
- USB_ID_MODE_HARDWARE,
- gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
- CONFIG_GXL_USB_PHY2_BASE,
- CONFIG_GXL_USB_PHY3_BASE,
- CONFIG_GXL_USB_U2_PORT_NUM,
- CONFIG_GXL_USB_U3_PORT_NUM,
- .usb_phy2_pll_base_addr = {
- CONFIG_USB_PHY_20,
- CONFIG_USB_PHY_21,
- }
-};
-
-#endif /*CONFIG_USB_XHCI_AMLOGIC*/
-
-#ifdef CONFIG_AML_HDMITX20
-static void hdmi_tx_set_hdmi_5v(void)
-{
-}
-#endif
-
-/*
- * mtd nand partition table, only care the size!
- * offset will be calculated by nand driver.
- */
-#ifdef CONFIG_AML_MTD
-static struct mtd_partition normal_partition_info[] = {
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- /* MUST NOT CHANGE this part unless u know what you are doing!
- * inherent parition for descrete bootloader to store fip
- * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
- * name must be same with TPL_PART_NAME
- */
- {
- .name = "tpl",
- .offset = 0,
- .size = 0,
- },
-#endif
- {
- .name = "fts",
- .offset = 0,
- .size = 1*SZ_1M,
- },
- {
- .name = "factory",
- .offset = 0,
- .size = 8*SZ_1M,
- },
- {
- .name = "recovery",
- .offset = 0,
- .size = 16*SZ_1M,
- },
- {
- .name = "boot",
- .offset = 0,
- .size = 16*SZ_1M,
- },
- {
- .name = "system",
- .offset = 0,
- .size = 220*SZ_1M,
- },
- /* last partition get the rest capacity */
- {
- .name = "cache",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-struct mtd_partition *get_aml_mtd_partition(void)
-{
- return normal_partition_info;
-}
-int get_aml_partition_count(void)
-{
- return ARRAY_SIZE(normal_partition_info);
-}
-#endif /* CONFIG_AML_MTD */
-
-#ifdef CONFIG_AML_SPIFC
-/*
- * BOOT_3: NOR_HOLDn:reg0[15:12]=3
- * BOOT_4: NOR_D:reg0[19:16]=3
- * BOOT_5: NOR_Q:reg0[23:20]=3
- * BOOT_6: NOR_C:reg0[27:24]=3
- * BOOT_7: NOR_WPn:reg0[31:28]=3
- * BOOT_14: NOR_CS:reg1[27:24]=3
- */
-#define SPIFC_NUM_CS 1
-static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
-
-static int spifc_pinctrl_enable(void *pinctrl, bool enable)
-{
- unsigned int val;
-
- val = readl(P_PERIPHS_PIN_MUX_0);
- val &= ~(0xfffff << 12);
- if (enable)
- val |= 0x33333 << 12;
- writel(val, P_PERIPHS_PIN_MUX_0);
-
- val = readl(P_PERIPHS_PIN_MUX_1);
- val &= ~(0xf << 24);
- writel(val, P_PERIPHS_PIN_MUX_1);
- return 0;
-}
-
-#if 0
-static const struct spifc_platdata spifc_platdata = {
- .reg = 0xffd14000,
- .mem_map = 0xf6000000,
- .pinctrl_enable = spifc_pinctrl_enable,
- .num_chipselect = SPIFC_NUM_CS,
- .cs_gpios = spifc_cs_gpios,
-};
-
-U_BOOT_DEVICE(spifc) = {
- .name = "spifc",
- .platdata = &spifc_platdata,
-};
-#endif
-#endif /* CONFIG_AML_SPIFC */
-
-#if 0
-#ifdef CONFIG_AML_SPICC
-/* generic config in arch gpio/clock.c */
-extern int spicc1_clk_set_rate(int rate);
-extern int spicc1_clk_enable(bool enable);
-extern int spicc1_pinctrl_enable(bool enable);
-
-static const struct spicc_platdata spicc1_platdata = {
- .compatible = "amlogic,meson-g12a-spicc",
- .reg = (void __iomem *)0xffd15000,
- .clk_rate = 666666666,
- .clk_set_rate = spicc1_clk_set_rate,
- .clk_enable = spicc1_clk_enable,
- .pinctrl_enable = spicc1_pinctrl_enable,
- /* case one slave without cs: {"no_cs", 0} */
- .cs_gpio_names = {"GPIOH_6", 0},
-};
-
-U_BOOT_DEVICE(spicc1) = {
- .name = "spicc",
- .platdata = &spicc1_platdata,
-};
-#endif /* CONFIG_AML_SPICC */
-#endif
-
-extern void aml_pwm_cal_init(int mode);
-
-int board_init(void)
-{
- printf("board init\n");
-
- /*in kernel P_RESET1_LEVEL has been clear,
- * uboot need set these bits about usb,
- * otherwise the usb has problem.
- */
- *(volatile uint32_t *)P_RESET1_LEVEL |= (3 << 16);
- //CPU_GPU_Voltage_init();
- enable_backlight(false);
- panel_detect_init();
-//Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
-//As NOT NEED other board init If USB BOOT MODE
-#ifdef CONFIG_AML_V2_FACTORY_BURN
- if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
- aml_try_factory_usb_burning(0, gd->bd);
- }
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
-
- pinctrl_devices_active(PIN_CONTROLLER_NUM);
-#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
- board_usb_pll_disable(&g_usb_config_GXL_skt);
- board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
-#endif /*CONFIG_USB_XHCI_AMLOGIC*/
-
- /* TODO(b/110040521): This is the earliest the backlight can be started,
- * but the LCD is not running yet. */
-
-#if 0
- aml_pwm_cal_init(0);
-#endif//
-#ifdef CONFIG_AML_NAND
- extern int amlnf_init(unsigned char flag);
- amlnf_init(0);
-#endif
- gpio_disable_pull();
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- printf("board late init\n");
- run_command("mmc dev 1", 0);
- run_command("run detect_panel", 0);
-#if 0
- //update env before anyone using it
- run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
- "if test ${reboot_mode} = factory_reset; then "\
- "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
- run_command("if itest ${upgrade_step} == 1; then "\
- "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
- /*add board late init function here*/
-#ifndef DTB_BIND_KERNEL
- int ret;
- ret = run_command("store dtb read $dtb_mem_addr", 1);
- if (ret) {
- printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
-#ifdef CONFIG_DTB_MEM_ADDR
- char cmd[64];
- printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
- sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
- ret = run_command(cmd, 1);
- if (ret) {
- printf("%s(): %s fail\n", __func__, cmd);
- }
-#endif
- }
-#elif defined(CONFIG_DTB_MEM_ADDR)
- {
- char cmd[128];
- int ret;
- if (!getenv("dtb_mem_addr")) {
- sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
- run_command(cmd, 0);
- }
- sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
- ret = run_command(cmd, 0);
- if (ret) {
- printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
- }
- }
-#endif// #ifndef DTB_BIND_KERNEL
-
- /* load unifykey */
- run_command("keyunify init 0x1234", 0);
-#endif
-/*open vpu hdmitx and cvbs driver*/
-#ifdef CONFIG_AML_VPU
- vpu_probe();
-#endif
-
-#ifdef CONFIG_AML_VPP
- vpp_init();
-#endif
-
-#ifdef CONFIG_AML_HDMITX
- hdmi_tx_init();
-#endif
-#ifdef CONFIG_AML_CVBS
- run_command("cvbs init", 0);
-#endif
-#ifdef CONFIG_AML_LCD
- lcd_probe();
-#endif
- run_command("get_lcd_extern_panel_type", 0);
-
-#ifdef CONFIG_AML_V2_FACTORY_BURN
- if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
- aml_try_factory_usb_burning(1, gd->bd);
- aml_try_factory_sdcard_burning(0, gd->bd);
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
- return 0;
-}
-#endif
-
-#ifdef CONFIG_AML_TINY_USBTOOL
-int usb_get_update_result(void)
-{
- unsigned long upgrade_step;
- upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
- printf("upgrade_step = %d\n", (int)upgrade_step);
- if (upgrade_step == 1)
- {
- run_command("defenv", 1);
- run_command("env_set upgrade_step 2", 1);
- run_command("saveenv", 1);
- return 0;
- }
- else
- {
- return -1;
- }
-}
-#endif
-
-phys_size_t get_effective_memsize(void)
-{
- // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
-#if defined(CONFIG_SYS_MEM_TOP_HIDE)
- return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
-#else
- return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
-#endif
-}
-
-#ifdef CONFIG_MULTI_DTB
-int checkhw(char * name)
-{
- /*
- * read board hw id
- * set and select the dts according the board hw id.
- *
- * hwid = 1 p321 v1
- * hwid = 2 p321 v2
- */
- unsigned int hwid = 1;
- char loc_name[64] = {0};
-
- /* read hwid */
- hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
-
- printf("checkhw: hwid = %d\n", hwid);
-
-
- switch (hwid) {
- case 1:
- strcpy(loc_name, "txl_p321_v1\0");
- break;
- case 2:
- strcpy(loc_name, "txl_p321_v2\0");
- break;
- default:
- strcpy(loc_name, "txl_p321_v1");
- break;
- }
- strcpy(name, loc_name);
- env_set("aml_dt", loc_name);
- return 0;
-}
-#endif
-
-/* workaround for VDDEE issue */
-/* VCCK PWM table */
-#define VCCK_VAL_REG_800 0x00150007
-#define VCCK_VAL_REG_810 0x00140008
-#define VCCK_VAL_REG_820 0x00130009
-#define VCCK_VAL_REG_830 0x0012000a
-#define VCCK_VAL_REG_840 0x0011000b
-#define VCCK_VAL_REG_850 0x0010000c
-#define VCCK_VAL_REG_860 0x000f000d
-#define VCCK_VAL_REG_870 0x000e000e
-#define VCCK_VAL_REG_880 0x000d000f
-#define VCCK_VAL_REG_890 0x000c0010
-#define VCCK_VAL_REG_900 0x000b0011
-#define VCCK_VAL_REG_910 0x000a0012
-#define VCCK_VAL_REG_920 0x00090013
-#define VCCK_VAL_REG_930 0x00080014
-#define VCCK_VAL_REG_940 0x00070015
-#define VCCK_VAL_REG_950 0x00060016
-#define VCCK_VAL_REG_960 0x00050017
-#define VCCK_VAL_REG_970 0x00040018
-#define VCCK_VAL_REG_980 0x00030019
-#define VCCK_VAL_REG_990 0x0002001a
-#define VCCK_VAL_REG_1000 0x0001001b
-#define VCCK_VAL_REG_1010 0x0000001c
-#define VCCK_VAL_REG_DEFAULT 0x00500008
-
-/* VDDEE PWM table */
-#define VDDEE_VAL_REG_800 0x0010000c
-#define VDDEE_VAL_REG_810 0x000f000d
-#define VDDEE_VAL_REG_820 0x000e000e
-#define VDDEE_VAL_REG_830 0x000d000f
-#define VDDEE_VAL_REG_840 0x000c0010
-#define VDDEE_VAL_REG_850 0x000b0011
-#define VDDEE_VAL_REG_860 0x000a0012
-#define VDDEE_VAL_REG_870 0x00090013
-#define VDDEE_VAL_REG_880 0x00080014
-#define VDDEE_VAL_REG_890 0x00070015
-#define VDDEE_VAL_REG_900 0x00060016
-#define VDDEE_VAL_REG_910 0x00050017
-#define VDDEE_VAL_REG_920 0x00040018
-#define VDDEE_VAL_REG_930 0x00030019
-#define VDDEE_VAL_REG_940 0x0002001a
-#define VDDEE_VAL_REG_950 0x0001001b
-#define VDDEE_VAL_REG_960 0x0000001c
-#define VDDEE_VAL_REG_DEFAULT 0x00500008
-
-void reset_misc(void)
-{
- unsigned int value;
-
- /* adjust VDDCPU to Hiz value step by step */
- writel(VCCK_VAL_REG_830, AO_PWM_PWM_D);
- udelay(1);
- writel(VCCK_VAL_REG_860, AO_PWM_PWM_D);
- udelay(1);
-
- /* GPIOE_0 & GPIOE_1 to gpio pin */
- value = readl(AO_RTI_PINMUX_REG1);
- value &= ~(0xff << 16);
- writel(value, AO_RTI_PINMUX_REG1);
-
- /* disable pwm_ao_b - VDDEE */
- value = readl(AO_PWM_MISC_REG_AB);
- value &= ~((0x1 << 1) | (0x1 << 23));
- writel(value, AO_PWM_MISC_REG_AB);
- writel(VDDEE_VAL_REG_DEFAULT, AO_PWM_PWM_B);
-
- /* disable pwm_ao_d - VDDCPU_B*/
- value = readl(AO_PWM_MISC_REG_CD);
- value &= ~((0x1 << 1) | (0x1 << 23));
- writel(value, AO_PWM_MISC_REG_CD);
- writel(VCCK_VAL_REG_DEFAULT, AO_PWM_PWM_D);
-}
-
-static struct mm_region bd_mem_map[] = {
- {
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = bd_mem_map;
-
-void board_nand_init(void) {
- printf("board_nand_init\n");
- return;
-}
-
-int print_cpuinfo(void) {
- printf("print_cpuinfo\n");
- return 0;
-}
-
-int mach_cpu_init(void) {
- printf("mach_cpu_init\n");
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- /* eg: bl31/32 rsv */
- return 0;
-}
diff --git a/board/amlogic/sm1_elaine_bx/zircon.c b/board/amlogic/sm1_elaine_bx/zircon.c
deleted file mode 100644
index 8e6888f..0000000
--- a/board/amlogic/sm1_elaine_bx/zircon.c
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * Copyright (c) 2018 The Fuchsia Authors
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common.h>
-#include <linux/mtd/partitions.h>
-#include <nand.h>
-#include <part.h>
-#include <emmc_storage.h>
-#include <zircon/zircon.h>
-
-#define PDEV_VID_GOOGLE 3
-#define PDEV_PID_ASTRO 3
-
-#define NVRAM_LENGTH (8 * 1024)
-
-const char* BOOTLOADER_VERSION = "zircon-bootloader=0.10";
-
-static const zbi_cpu_config_t cpu_config = {
- .cluster_count = 1,
- .clusters = {
- {
- .cpu_count = 4,
- },
- },
-};
-
-static const zbi_mem_range_t mem_config[] = {
- {
- .type = ZBI_MEM_RANGE_RAM,
- .length = 0x60000000, // 1.5 GB
- },
- {
- .type = ZBI_MEM_RANGE_PERIPHERAL,
- .paddr = 0xf5800000,
- .length = 0x0a800000,
- },
- // secmon_reserved:linux,secmon
- {
- .type = ZBI_MEM_RANGE_RESERVED,
- .paddr = 0x05000000,
- .length = 0x2400000,
- },
- // logo_reserved:linux,meson-fb
- {
- .type = ZBI_MEM_RANGE_RESERVED,
- .paddr = 0x5f800000,
- .length = 0x800000,
- },
-};
-
-static const dcfg_simple_t uart_driver = {
- .mmio_phys = 0xff803000,
- .irq = 225,
-};
-
-static const dcfg_arm_gicv2_driver_t gicv2_driver = {
- .mmio_phys = 0xffc00000,
- .gicd_offset = 0x1000,
- .gicc_offset = 0x2000,
- .gich_offset = 0x4000,
- .gicv_offset = 0x6000,
- .ipi_base = 5,
-};
-
-static const dcfg_arm_psci_driver_t psci_driver = {
- .use_hvc = false,
- .reboot_args = { 1, 0, 0 },
- .reboot_bootloader_args = { 4, 0, 0 },
- .reboot_recovery_args = { 2, 0, 0 },
-};
-
-static const dcfg_arm_generic_timer_driver_t timer_driver = {
- .irq_phys = 30,
-};
-
-static const zbi_platform_id_t platform_id = {
- .vid = PDEV_VID_GOOGLE,
- .pid = PDEV_PID_ASTRO,
- .board_name = "astro",
-};
-
-enum {
- PART_TPL,
- PART_FTS,
- PART_FACTORY,
- PART_ZIRCON_B,
- PART_ZIRCON_A,
- PART_ZIRCON_R,
- PART_FVM,
- PART_SYS_CONFIG,
- PART_MIGRATION,
- PART_COUNT,
-};
-
-#define RECOVERY_SIZE (16 * 1024 * 1024)
-#define SYS_CONFIG_SIZE (1 * 1024 * 1024)
-#define MIGRATION_SIZE (3 * 1024 * 1024)
-
-static zbi_partition_map_t partition_map = {
- // .block_count filled in below
- // .block_size filled in below
- .guid = {},
- .partition_count = PART_COUNT,
- .partitions = {
- {
- .type_guid = GUID_BOOTLOADER_VALUE,
- .name = "tpl",
- },
- {
- .name = "fts",
- },
- {
- .name = "factory",
- },
- {
- .type_guid = GUID_ZIRCON_R_VALUE,
- .name = "zircon-r",
- },
- {
- .type_guid = GUID_ZIRCON_A_VALUE,
- .name = "zircon-a",
- },
- {
- .type_guid = GUID_ZIRCON_B_VALUE,
- .name = "zircon-b",
- },
- {
- .type_guid = GUID_FVM_VALUE,
- .name = "fvm",
- },
- {
- .type_guid = GUID_SYS_CONFIG_VALUE,
- .name = "sys-config",
- },
- {
- .name = "migration",
- },
- },
-};
-
-extern struct mtd_partition *get_aml_mtd_partition(void);
-extern int get_aml_partition_count(void);
-
-static void add_partition_map(zbi_header_t* zbi) {
- struct mtd_partition* tpl_part = NULL;
- struct mtd_partition* fts_part = NULL;
- struct mtd_partition* factory_part = NULL;
- struct mtd_partition* recovery_part = NULL;
- struct mtd_partition* boot_part = NULL;
- struct mtd_partition* system_part = NULL;
- struct mtd_partition* partitions = get_aml_mtd_partition();
- int partition_count = get_aml_partition_count();
- int i;
-
- for (i = 0; i < partition_count; i++) {
- struct mtd_partition* part = &partitions[i];
- if (!strcmp("tpl", part->name)) {
- tpl_part = part;
- } else if (!strcmp("fts", part->name)) {
- fts_part = part;
- } else if (!strcmp("factory", part->name)) {
- factory_part = part;
- } else if (!strcmp("recovery", part->name)) {
- recovery_part = part;
- } else if (!strcmp("boot", part->name)) {
- boot_part = part;
- } else if (!strcmp("system", part->name)) {
- system_part = part;
- }
- }
-
- if (!tpl_part) {
- printf("could not find tpl partition\n");
- return;
- }
- if (!fts_part) {
- printf("could not find fts partition\n");
- return;
- }
- if (!factory_part) {
- printf("could not find factory partition\n");
- return;
- }
- if (!recovery_part) {
- printf("could not find recovery partition\n");
- return;
- }
- if (!boot_part) {
- printf("could not find boot partition\n");
- return;
- }
- if (!system_part) {
- printf("could not find system partition\n");
- return;
- }
-
- uint32_t block_size = nand_info[1].writesize;
- uint64_t total_size = nand_info[1].size;
-
- partition_map.block_size = block_size;
- partition_map.block_count = total_size / block_size;
-
- // map tpl partition to BOOTLOADER
- partition_map.partitions[PART_TPL].first_block = tpl_part->offset / block_size;
- partition_map.partitions[PART_TPL].last_block =
- ((tpl_part->offset + tpl_part->size) / block_size) - 1;
- // map fts partition to "fts"
- partition_map.partitions[PART_FTS].first_block = fts_part->offset / block_size;
- partition_map.partitions[PART_FTS].last_block =
- ((fts_part->offset + fts_part->size) / block_size) - 1;
- // map factory partition to "factory"
- partition_map.partitions[PART_FACTORY].first_block = factory_part->offset / block_size;
- partition_map.partitions[PART_FACTORY].last_block =
- ((factory_part->offset + factory_part->size) / block_size) - 1;
- // map recovery partition to ZIRCON_B
- partition_map.partitions[PART_ZIRCON_B].first_block = recovery_part->offset / block_size;
- partition_map.partitions[PART_ZIRCON_B].last_block =
- ((recovery_part->offset + recovery_part->size) / block_size) - 1;
- // map boot partition to ZIRCON_A
- partition_map.partitions[PART_ZIRCON_A].first_block = boot_part->offset / block_size;
- partition_map.partitions[PART_ZIRCON_A].last_block =
- ((boot_part->offset + boot_part->size) / block_size) - 1;
- // ZIRCON_R partition at start of system
- partition_map.partitions[PART_ZIRCON_R].first_block = system_part->offset / block_size;
- partition_map.partitions[PART_ZIRCON_R].last_block =
- partition_map.partitions[PART_ZIRCON_R].first_block +
- (RECOVERY_SIZE / block_size) - 1;
- // FVM follows ZIRCON_R
- partition_map.partitions[PART_FVM].first_block =
- partition_map.partitions[PART_ZIRCON_R].last_block + 1;
- partition_map.partitions[PART_FVM].last_block =
- ((total_size - SYS_CONFIG_SIZE - MIGRATION_SIZE) / block_size) - 1;
- // SYS_CONFIG follows FVM
- partition_map.partitions[PART_SYS_CONFIG].first_block =
- partition_map.partitions[PART_FVM].last_block + 1;
- partition_map.partitions[PART_SYS_CONFIG].last_block =
- partition_map.partitions[PART_SYS_CONFIG].first_block +
- (SYS_CONFIG_SIZE / block_size) - 1;
- // MIGRATION follows SYS_CONFIG
- partition_map.partitions[PART_MIGRATION].first_block =
- partition_map.partitions[PART_SYS_CONFIG].last_block + 1;
- partition_map.partitions[PART_MIGRATION].last_block =
- partition_map.partitions[PART_MIGRATION].first_block +
- (MIGRATION_SIZE / block_size) - 1;
-
- printf("Zircon partitions:\n");
- for (i = 0; i < PART_COUNT; i++) {
- printf(" 0x%016llx - 0x%016llx : %s\n",
- partition_map.partitions[i].first_block * block_size,
- (partition_map.partitions[i].last_block + 1) * block_size,
- partition_map.partitions[i].name);
- }
-
- zircon_append_boot_item(zbi, ZBI_TYPE_DRV_PARTITION_MAP, 0, &partition_map,
- sizeof(zbi_partition_map_t) +
- partition_map.partition_count * sizeof(zbi_partition_t));
-}
-
-int zircon_preboot(zbi_header_t* zbi) {
- // add CPU configuration
- zircon_append_boot_item(zbi, ZBI_TYPE_CPU_CONFIG, 0, &cpu_config,
- sizeof(zbi_cpu_config_t) +
- sizeof(zbi_cpu_cluster_t) * cpu_config.cluster_count);
-
- // allocate crashlog save area before 0x5f800000-0x60000000 reserved area
- zbi_nvram_t nvram;
- nvram.base = 0x5f800000 - NVRAM_LENGTH;
- nvram.length = NVRAM_LENGTH;
- zircon_append_boot_item(zbi, ZBI_TYPE_NVRAM, 0, &nvram, sizeof(nvram));
-
- // add memory configuration
- zircon_append_boot_item(zbi, ZBI_TYPE_MEM_CONFIG, 0, &mem_config, sizeof(mem_config));
-
- // add kernel drivers
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_AMLOGIC_UART, &uart_driver,
- sizeof(uart_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_GIC_V2, &gicv2_driver,
- sizeof(gicv2_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_PSCI, &psci_driver,
- sizeof(psci_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_GENERIC_TIMER, &timer_driver,
- sizeof(timer_driver));
-
- zircon_append_boot_item(zbi, ZBI_TYPE_CMDLINE, 0, BOOTLOADER_VERSION, strlen(BOOTLOADER_VERSION) + 1);
-
- // add platform ID
- zircon_append_boot_item(zbi, ZBI_TYPE_PLATFORM_ID, 0, &platform_id, sizeof(platform_id));
-
- add_partition_map(zbi);
-
- return 0;
-}
diff --git a/board/amlogic/sm1_elaine_p0/Kconfig b/board/amlogic/sm1_elaine_p0/Kconfig
deleted file mode 100755
index 444be85..0000000
--- a/board/amlogic/sm1_elaine_p0/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_SM1_ELAINE_P0
-
-config SYS_SOC
- default "g12a"
-
-config SYS_BOARD
- default "sm1_elaine_p0"
-
-config SYS_VENDOR
- default "amlogic"
-
-config SYS_CONFIG_NAME
- default "sm1_elaine_p0"
-
-endif
diff --git a/board/amlogic/sm1_elaine_p0/Makefile b/board/amlogic/sm1_elaine_p0/Makefile
deleted file mode 100755
index fb7f59a..0000000
--- a/board/amlogic/sm1_elaine_p0/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-
-obj-y += $(BOARD).o eth_setup.o
-obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/sm1_elaine_p0/aml-user-key.sig b/board/amlogic/sm1_elaine_p0/aml-user-key.sig
deleted file mode 100755
index 2ceabc1..0000000
--- a/board/amlogic/sm1_elaine_p0/aml-user-key.sig
+++ /dev/null
Binary files differ
diff --git a/board/amlogic/sm1_elaine_p0/eth_setup.c b/board/amlogic/sm1_elaine_p0/eth_setup.c
deleted file mode 100755
index 6cbcd95..0000000
--- a/board/amlogic/sm1_elaine_p0/eth_setup.c
+++ /dev/null
@@ -1,51 +0,0 @@
-
-/*
- * board/amlogic/txl_skt_v1/eth_setup.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <malloc.h>
-#include <errno.h>
-#include <environment.h>
-#include <fdt_support.h>
-#include <linux/libfdt.h>
-#include <asm/arch/eth_setup.h>
-/*
- *
- *setup eth device board socket
- *
- */
-struct eth_board_socket* eth_board_setup(char *name){
- struct eth_board_socket* new_board;
- new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
- if (NULL == new_board) return NULL;
- if (name != NULL) {
- new_board->name=(char*)malloc(strlen(name));
- strncpy(new_board->name,name,strlen(name));
- }else{
- new_board->name="gxb";
- }
-
- new_board->eth_pinmux_setup=NULL ;
- new_board->eth_clock_configure=NULL;
- new_board->eth_hw_reset=NULL;
- return new_board;
-}
-//pinmux HHI_GCLK_MPEG1[bit 3]
-//
diff --git a/board/amlogic/sm1_elaine_p0/firmware/ramdump.c b/board/amlogic/sm1_elaine_p0/firmware/ramdump.c
deleted file mode 100755
index e03dcd2..0000000
--- a/board/amlogic/sm1_elaine_p0/firmware/ramdump.c
+++ /dev/null
@@ -1,45 +0,0 @@
-
-#ifdef CONFIG_MDUMP_COMPRESS
-#include "ramdump.h"
-
-struct ram_compress_full __ramdump_data = {
- .store_phy_addr = (void *)CONFIG_COMPRESSED_DATA_ADDR,
- .full_memsize = CONFIG_DDR_TOTAL_SIZE,
- .section_count = CONFIG_COMPRESS_SECTION,
- .sections = {
- {
- /* memory afer compressed data address */
- .phy_addr = (void *)CONFIG_COMPRESSED_DATA_ADDR,
- .section_size = CONFIG_DDR_TOTAL_SIZE -
- CONFIG_COMPRESSED_DATA_ADDR,
- .section_index = 4,
- .compress_type = RAM_COMPRESS_NORMAL,
- },
- {
- /* memory before bl2 */
- .phy_addr = (void *)CONFIG_COMPRESS_START_ADDR,
- .section_size = CONFIG_BL2_IGNORE_ADDR -
- CONFIG_COMPRESS_START_ADDR,
- .section_index = 1,
- .compress_type = RAM_COMPRESS_NORMAL,
- },
- {
- /* memory in reserved bl2 */
- .phy_addr = (void *)CONFIG_BL2_IGNORE_ADDR,
- .section_size = CONFIG_BL2_IGNORE_SIZE,
- .section_index = 2,
- .compress_type = RAM_COMPRESS_SET,
- .set_value = 0x0,
- },
- {
- /* segment 4: normal compress */
- .phy_addr = (void *)CONFIG_SEG4_ADDR,
- .section_size = CONFIG_COMPRESSED_DATA_ADDR -
- CONFIG_SEG4_ADDR,
- .section_index = 3,
- .compress_type = RAM_COMPRESS_NORMAL,
- }
- },
-};
-#endif /* CONFIG_MDUMP_COMPRESS */
-
diff --git a/board/amlogic/sm1_elaine_p0/firmware/ramdump.h b/board/amlogic/sm1_elaine_p0/firmware/ramdump.h
deleted file mode 100755
index 0671567..0000000
--- a/board/amlogic/sm1_elaine_p0/firmware/ramdump.h
+++ /dev/null
@@ -1,75 +0,0 @@
-#ifndef __RAM_DUMP_H__
-#define __RAM_DUMP_H__
-
-#include <config.h>
-#ifdef CONFIG_MDUMP_COMPRESS
-#define CONFIG_COMPRESS_SECTION 4
-
-#if CONFIG_COMPRESS_SECTION > 8
-#error ---> CONFIG_COMPRESS_SECTION out of range, max should be 8
-#endif
-/*
- * Full Memory lay out for RAM compress:
- *
- * DDR_TOP -> +--------+
- * | |
- * | |
- * | 4 |
- * | |
- * | |
- * |~~~~~~~~| <- store compressing data
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * COMPRESSED_DATA -> +--------+
- * | |
- * | 3 |
- * | |
- * BL2_IGNORE_END -> +--------+ -- IGNORE_SIZE
- * ||||||||||
- * ||||2|||||
- * ||||||||||
- * BL2_IGNORE_ADDR -> +--------+
- * | |
- * | 1 |
- * | |
- * COMPRESS_START_ADDR -> +--------+
- */
-#define CONFIG_DDR_TOTAL_SIZE (CONFIG_DDR_SIZE << 20)
-#define CONFIG_COMPRESSED_DATA_ADDR (0x10000000)
-#define CONFIG_COMPRESSED_DATA_ADDR1 (0x08000000)
-
-#define CONFIG_COMPRESS_START_ADDR (0x00000000)
-#define CONFIG_BL2_IGNORE_ADDR (0x05000000)
-#define CONFIG_BL2_IGNORE_SIZE (0x00300000)
-#define CONFIG_SEG4_ADDR (CONFIG_BL2_IGNORE_ADDR + \
- CONFIG_BL2_IGNORE_SIZE)
-
-enum {
- RAM_COMPRESS_NORMAL = 1,
- RAM_COMPRESS_COPY = 2,
- RAM_COMPRESS_SET = 3 /* set ram content to same vale */
-};
-
-struct ram_compress_section {
- void *phy_addr;
- unsigned int section_size;
- unsigned int section_index : 8;
- unsigned int compress_type : 8;
- unsigned int set_value : 16;
-};
-
-struct ram_compress_full {
- void *store_phy_addr;
- unsigned int full_memsize;
- unsigned int section_count;
- struct ram_compress_section sections[CONFIG_COMPRESS_SECTION];
-};
-
-#endif
-#endif /* __RAM_DUMP_H__ */
diff --git a/board/amlogic/sm1_elaine_p0/firmware/scp_task/dvfs_board.c b/board/amlogic/sm1_elaine_p0/firmware/scp_task/dvfs_board.c
deleted file mode 100755
index cdcb418..0000000
--- a/board/amlogic/sm1_elaine_p0/firmware/scp_task/dvfs_board.c
+++ /dev/null
@@ -1,194 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_p0/firmware/scp_task/dvfs_board.c
- *
- * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-/*
-int pwm_voltage_table[ ][2] = {
- { 0x1c0000, 860},
- { 0x1b0001, 870},
- { 0x1a0002, 880},
- { 0x190003, 890},
- { 0x180004, 900},
- { 0x170005, 910},
- { 0x160006, 920},
- { 0x150007, 930},
- { 0x140008, 940},
- { 0x130009, 950},
- { 0x12000a, 960},
- { 0x11000b, 970},
- { 0x10000c, 980},
- { 0x0f000d, 990},
- { 0x0e000e, 1000},
- { 0x0d000f, 1010},
- { 0x0c0010, 1020},
- { 0x0b0011, 1030},
- { 0x0a0012, 1040},
- { 0x090013, 1050},
- { 0x080014, 1060},
- { 0x070015, 1070},
- { 0x060016, 1080},
- { 0x050017, 1090},
- { 0x040018, 1100},
- { 0x030019, 1110},
- { 0x02001a, 1120},
- { 0x01001b, 1130},
- { 0x00001c, 1140}
-};
-*/
-#include "pwm_ctrl.h"
-
-#define CHIP_ADJUST 20
-#define RIPPLE_ADJUST 30
-struct scpi_opp_entry cpu_dvfs_tbl[] = {
- DVFS( 100000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS( 250000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS( 500000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1200000000, 940+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1296000000, 980+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1416000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
-};
-
-
-#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
-#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
-#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2))))
-
-#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2))))
-#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
-
-
-enum pwm_id {
- pwm_a = 0,
-};
-
-
-void pwm_init(int id)
-{
- /*
- * TODO: support more pwm controllers, right now only support PWM_B
- */
- unsigned int reg;
- reg = P_PWM_MISC_REG_AB;
- reg &= ~(0x7f << 8);
- reg |= ((1 << 15) | (1 << 0));
- P_PWM_MISC_REG_AB = reg;
- /*
- * default set to max voltage
- */
- //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
- reg = P_PIN_MUX_REG3;
- reg &= ~((1 << 21) | 1 << 12);
- P_PIN_MUX_REG3 = reg;
-
- reg = P_PIN_MUX_REG10;
- reg &= ~(1 << 16);
- P_PIN_MUX_REG10 = reg;//clear reg10
- reg = P_PIN_MUX_REG4;
- reg &= ~(1 << 26); // clear PWM_VS
- reg |= (1 << 17); // enable PWM_A
- P_PIN_MUX_REG4 = reg;
-
-
- _udelay(200);
-}
-
-int dvfs_get_voltage(void)
-{
- int i = 0;
- unsigned int reg_val;
-
- reg_val = P_PWM_PWM_A;
- for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
- if (pwm_voltage_table[i][0] == reg_val) {
- return i;
- }
- }
- if (i >= ARRAY_SIZE(pwm_voltage_table)) {
- return -1;
- }
- return -1;
-}
-
-void set_dvfs(unsigned int domain, unsigned int index)
-{
- int cur, to;
- static int init_flag = 0;
-
- if (!init_flag) {
- pwm_init(pwm_a);
- init_flag = 1;
- }
- cur = dvfs_get_voltage();
- for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
- if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
- break;
- }
- }
- if (to >= ARRAY_SIZE(pwm_voltage_table)) {
- to = ARRAY_SIZE(pwm_voltage_table) - 1;
- }
- if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
- P_PWM_PWM_A = pwm_voltage_table[to][0];
- _udelay(200);
- return ;
- }
- while (cur != to) {
- /*
- * if target step is far away from current step, don't change
- * voltage by one-step-done. You should change voltage step by
- * step to make sure voltage output is stable
- */
- if (cur < to) {
- if (cur < to - 3) {
- cur += 3;
- } else {
- cur = to;
- }
- } else {
- if (cur > to + 3) {
- cur -= 3;
- } else {
- cur = to;
- }
- }
- P_PWM_PWM_A = pwm_voltage_table[cur][0];
- _udelay(100);
- }
- _udelay(200);
-}
-void get_dvfs_info_board(unsigned int domain,
- unsigned char *info_out, unsigned int *size_out)
-{
- unsigned int cnt;
- cnt = ARRAY_SIZE(cpu_dvfs_tbl);
-
- buf_opp.latency = 200;
- buf_opp.count = cnt;
- memset(&buf_opp.opp[0], 0,
- MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
-
- memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
- cnt * sizeof(struct scpi_opp_entry));
-
- memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
- *size_out = sizeof(struct scpi_opp);
- return;
-}
diff --git a/board/amlogic/sm1_elaine_p0/firmware/scp_task/pwm_ctrl.h b/board/amlogic/sm1_elaine_p0/firmware/scp_task/pwm_ctrl.h
deleted file mode 100755
index 60df2b5..0000000
--- a/board/amlogic/sm1_elaine_p0/firmware/scp_task/pwm_ctrl.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
-*board/amlogic/sm1_elaine_p0/firmware/scp_task/pwm_vol_tab.h
-*table for Dynamic Voltage/Frequency Scaling
-*/
-#ifndef __PWM_CTRL_H__
-#define __PWM_CTRL_H__
-
-static int pwm_voltage_table_ee[][2] = {
- { 0x1c0000, 681},
- { 0x1b0001, 691},
- { 0x1a0002, 701},
- { 0x190003, 711},
- { 0x180004, 721},
- { 0x170005, 731},
- { 0x160006, 741},
- { 0x150007, 751},
- { 0x140008, 761},
- { 0x130009, 772},
- { 0x12000a, 782},
- { 0x11000b, 792},
- { 0x10000c, 802},
- { 0x0f000d, 812},
- { 0x0e000e, 822},
- { 0x0d000f, 832},
- { 0x0c0010, 842},
- { 0x0b0011, 852},
- { 0x0a0012, 862},
- { 0x090013, 872},
- { 0x080014, 882},
- { 0x070015, 892},
- { 0x060016, 902},
- { 0x050017, 912},
- { 0x040018, 922},
- { 0x030019, 932},
- { 0x02001a, 942},
- { 0x01001b, 952},
- { 0x00001c, 962}
-};
-
-#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/sm1_elaine_p0/firmware/scp_task/pwr_ctrl.c b/board/amlogic/sm1_elaine_p0/firmware/scp_task/pwr_ctrl.c
deleted file mode 100755
index fd78e2e..0000000
--- a/board/amlogic/sm1_elaine_p0/firmware/scp_task/pwr_ctrl.c
+++ /dev/null
@@ -1,196 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_p0/firmware/scp_task/pwr_ctrl.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <gpio.h>
-#include "pwm_ctrl.h"
-#ifdef CONFIG_CEC_WAKEUP
-#include <cec_tx_reg.h>
-#endif
-
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
-static void set_vddee_voltage(unsigned int target_voltage)
-{
- unsigned int to;
-
- for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
- if (pwm_voltage_table_ee[to][1] >= target_voltage) {
- break;
- }
- }
-
- if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
- to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
- }
-
- writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
-}
-
-static void power_off_at_24M(unsigned int suspend_from)
-{
- /*set gpioH_8 low to power off vcc 5v*/
- writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
- writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
-
- /*set test_n low to power off vcck & vcc 3.3v*/
- writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
- writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
- writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
-
- /*step down ee voltage*/
- set_vddee_voltage(AML_VDDEE_SLEEP_VOLTAGE);
-}
-
-static void power_on_at_24M(unsigned int suspend_from)
-{
- /*step up ee voltage*/
- set_vddee_voltage(AML_VDDEE_INIT_VOLTAGE);
-
- /*set test_n low to power on vcck & vcc 3.3v*/
- writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
- writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
- writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
- _udelay(100);
-
- /*set gpioH_8 low to power on vcc 5v*/
- writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
- writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
- _udelay(10000);
-
-}
-
-void get_wakeup_source(void *response, unsigned int suspend_from)
-{
- struct wakeup_info *p = (struct wakeup_info *)response;
- struct wakeup_gpio_info *gpio;
- unsigned val;
- unsigned i = 0;
-
- p->status = RESPONSE_OK;
- val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
- ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC | ETH_PHY_GPIO_SRC
- | CECB_WAKEUP_SRC);
-
- p->sources = val;
-
- /* Power Key: AO_GPIO[3]*/
- gpio = &(p->gpio_info[i]);
- gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
- gpio->gpio_in_idx = GPIOAO_3;
- gpio->gpio_in_ao = 1;
- gpio->gpio_out_idx = -1;
- gpio->gpio_out_ao = -1;
- gpio->irq = IRQ_AO_GPIO0_NUM;
- gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
- p->gpio_info_count = ++i;
-
- /*Eth:GPIOZ_14*/
- gpio = &(p->gpio_info[i]);
- gpio->wakeup_id = ETH_PHY_GPIO_SRC;
- gpio->gpio_in_idx = GPIOZ_14;
- gpio->gpio_in_ao = 0;
- gpio->gpio_out_idx = -1;
- gpio->gpio_out_ao = -1;
- gpio->irq = IRQ_GPIO1_NUM;
- gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
- p->gpio_info_count = ++i;
-
- /*bt wake host*/
- gpio = &(p->gpio_info[i]);
- gpio->wakeup_id = BT_WAKEUP_SRC;
- gpio->gpio_in_idx = GPIOX_18;
- gpio->gpio_in_ao = 0;
- gpio->gpio_out_idx = -1;
- gpio->gpio_out_ao = -1;
- gpio->irq = IRQ_GPIO0_NUM;
- gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
- p->gpio_info_count = ++i;
-}
-extern void __switch_idle_task(void);
-
-static unsigned int detect_key(unsigned int suspend_from)
-{
- int exit_reason = 0;
- unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
- init_remote();
-#ifdef CONFIG_CEC_WAKEUP
- if (hdmi_cec_func_config & 0x1) {
- remote_cec_hw_reset();
- cec_node_init();
- }
-#endif
-
- do {
- #ifdef CONFIG_CEC_WAKEUP
- if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
- irq[IRQ_AO_CECB] = 0xFFFFFFFF;
- if (cec_power_on_check())
- exit_reason = CEC_WAKEUP;
- }
- #endif
- if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
- irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
- if (remote_detect_key())
- exit_reason = REMOTE_WAKEUP;
- }
-
- if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) {
- irq[IRQ_VRTC] = 0xFFFFFFFF;
- exit_reason = RTC_WAKEUP;
- }
-
- if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
- irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
- if ((readl(AO_GPIO_I) & (1<<3)) == 0)
- exit_reason = POWER_KEY_WAKEUP;
- }
-#if 0
- if (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM) {
- irq[IRQ_GPIO1] = 0xFFFFFFFF;
- if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 14))
- && (readl(PREG_PAD_GPIO4_EN_N) & (0x01 << 14)))
- exit_reason = ETH_PHY_GPIO;
- }
-#endif
- if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
- irq[IRQ_GPIO0] = 0xFFFFFFFF;
- if (!(readl(PREG_PAD_GPIO2_I) & (0x01 << 18))
- && (readl(PREG_PAD_GPIO2_O) & (0x01 << 17))
- && !(readl(PREG_PAD_GPIO2_EN_N) & (0x01 << 17)))
- exit_reason = BT_WAKEUP;
- }
-
- if (exit_reason)
- break;
- else
- __switch_idle_task();
- } while (1);
-
- return exit_reason;
-}
-
-static void pwr_op_init(struct pwr_op *pwr_op)
-{
- pwr_op->power_off_at_24M = power_off_at_24M;
- pwr_op->power_on_at_24M = power_on_at_24M;
- pwr_op->detect_key = detect_key;
- pwr_op->get_wakeup_source = get_wakeup_source;
-}
diff --git a/board/amlogic/sm1_elaine_p0/firmware/timing.c b/board/amlogic/sm1_elaine_p0/firmware/timing.c
deleted file mode 100755
index 0700a96..0000000
--- a/board/amlogic/sm1_elaine_p0/firmware/timing.c
+++ /dev/null
@@ -1,462 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_p0/firmware/timing.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/timing.h>
-#include <asm/arch/ddr_define.h>
-
-/* board clk defines */
-#define DDR_SIZE 0
-#define CPU_CLK 1200
-
-/* ddr config support multiple configs for boards which use same bootloader:
- * config steps:
- * 1. add a new data struct in __ddr_setting[]
- * 2. config correct board_id, ddr_type, freq, etc..
- */
-
-
-/* CAUTION!! */
-/* Confirm ddr configs with hardware designer,
- * if you don't know how to config, then don't edit it
- */
-
-/* Key configs */
-/*
- * board_id: check hardware adc config
- * dram_rank_config:
- * #define CONFIG_DDR_CHL_AUTO 0xF
- * #define CONFIG_DDR0_16BIT_CH0 0x1
- * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
- * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
- * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
- * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
- * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
- * DramType:
- * #define CONFIG_DDR_TYPE_DDR3 0
- * #define CONFIG_DDR_TYPE_DDR4 1
- * #define CONFIG_DDR_TYPE_LPDDR4 2
- * #define CONFIG_DDR_TYPE_LPDDR3 3
- * DRAMFreq:
- * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
- *
- */
-
-
-/* ddr configs */
-#define DDR_RFC_TYPE_DDR3_512Mbx1 0
-#define DDR_RFC_TYPE_DDR3_512Mbx2 1
-#define DDR_RFC_TYPE_DDR3_512Mbx4 2
-#define DDR_RFC_TYPE_DDR3_512Mbx8 3
-#define DDR_RFC_TYPE_DDR3_512Mbx16 4
-#define DDR_RFC_TYPE_DDR4_2Gbx1 5
-#define DDR_RFC_TYPE_DDR4_2Gbx2 6
-#define DDR_RFC_TYPE_DDR4_2Gbx4 7
-#define DDR_RFC_TYPE_DDR4_2Gbx8 8
-
-#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
-#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
-#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
-
-#if CONFIG_DDR_LOGS_ENABLED
-#define LOG_FLAG 0x9
-#else
-#define LOG_FLAG 0xA
-#endif
-
-ddr_set_t __ddr_setting[] = {
- {
- /* g12a skt (u209) ddr3 */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
- .DramType = CONFIG_DDR_TYPE_DDR3,
- .DRAMFreq = {912, 0, 0, 0},
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 1,
- .HdtCtrl = 0xa,
- .dram_cs0_size_MB = 1024,
- .dram_cs1_size_MB = 512,
- .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .clk_drv_ohm = 40,
- .cs_drv_ohm = 40,
- .ac_drv_ohm = 40,
- .soc_data_drv_ohm_p = 34,
- .soc_data_drv_ohm_n = 34,
- .soc_data_odt_ohm_p = 60, //48,
- .soc_data_odt_ohm_n = 0,
- .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
- .dram_data_odt_ohm = 60,
- .dram_ac_odt_ohm = 0,
- .soc_clk_slew_rate = 0x300,
- .soc_cs_slew_rate = 0x300,
- .soc_ac_slew_rate = 0x300,
- .soc_data_slew_rate = 0x200,
- .vref_output_permil = 500,
- .vref_receiver_permil = 500, //700,
- .vref_dram_permil = 500, //700,
-// .vref_reverse = 0,
- .ac_trace_delay ={32,32,32,32,32,32,32,32,32,32},
- //{00,00},
- .ac_pinmux = {00,00},
-#if 1
- .ddr_dmc_remap = {
- [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
- [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
- },
-#else
- //16bit
- .ddr_dmc_remap = {
- [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
- [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
- [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
- [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
- },
-#endif
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap = {00,00},
- .dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
- .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
-},
-{
- /* g12a skt (u209) ddr3 */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
- .DramType = CONFIG_DDR_TYPE_DDR3,
- .DRAMFreq = {912, 0, 0, 0},
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 1,
- .HdtCtrl = LOG_FLAG,
- .dram_cs0_size_MB = 1024,
- .dram_cs1_size_MB = 512,
- .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .pll_ssc_mode = 0,
- .clk_drv_ohm = 40,
- .cs_drv_ohm = 40,
- .ac_drv_ohm = 40,
- .soc_data_drv_ohm_p = 34,
- .soc_data_drv_ohm_n = 34,
- .soc_data_odt_ohm_p = 60, //48,
- .soc_data_odt_ohm_n = 0,
- .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
- .dram_data_odt_ohm = 60,
- .dram_ac_odt_ohm = 0,
- .soc_clk_slew_rate = 0x300,
- .soc_cs_slew_rate = 0x300,
- .soc_ac_slew_rate = 0x300,
- .soc_data_slew_rate = 0x200,
- .vref_output_permil = 500,
- .vref_receiver_permil = 500, //700,
- .vref_dram_permil = 500, //700,
- //{00,00},
- .ac_pinmux = {00,00},
-#if 1
- .ddr_dmc_remap = {
- [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
- [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
- },
-#else
- //16bit
- .ddr_dmc_remap = {
- [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
- [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
- [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
- [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
- },
-#endif
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap = {00,00},
- .dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
- .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
- .slt_test_function = {DMC_TEST_SLT_ENABLE_DDR_SKIP_TRAINING, 0},
- .dfi_hwtmrl = 4,
-
- .ac_trace_delay = {
- 32, 32, 32, 32,
- 32, 32, 32, 32,
- 32, 32,
- },
-
- .write_dqs_delay = {
- 163, 163, 163, 163,
- 167, 167, 165, 165,
- 159, 159, 163, 163,
- 165, 165, 161, 161,
- },
-
- .read_dqs_delay = {
- 13, 13, 14, 14,
- 14, 14, 15, 14,
- 14, 14, 14, 15,
- 14, 13, 14, 14,
- },
-
- .write_dq_bit_delay = {
- 20, 21, 19, 21,
- 21, 21, 22, 20,
- 22, 21, 20, 20,
- 19, 21, 18, 21,
- 20, 20, 24, 20,
- 22, 25, 24, 25,
- 26, 26, 23, 20,
- 21, 20, 23, 21,
- 21, 23, 23, 20,
- 48, 49, 48, 50,
- 50, 50, 51, 49,
- 49, 21, 21, 19,
- 20, 21, 19, 20,
- 21, 20, 22, 18,
- 20, 23, 23, 24,
- 24, 24, 22, 17,
- 18, 17, 20, 18,
- 18, 21, 20, 19,
- },
-
- .read_dq_bit_delay = {
- 15, 15, 15, 23,
- 31, 31, 31, 29,
- 0 , 23, 19, 11,
- 17, 35, 23, 31,
- 31, 0 , 15, 3 ,
- 9 , 15, 27, 27,
- 35, 35, 0 , 13,
- 15, 11, 19, 25,
- 19, 31, 31, 0 ,
- 15, 17, 15, 19,
- 31, 33, 31, 27,
- 0 , 19, 19, 15,
- 13, 31, 23, 27,
- 31, 0 , 13, 3 ,
- 5 , 11, 23, 27,
- 31, 27, 0 , 13,
- 13, 9 , 19, 23,
- 23, 27, 27, 0 ,
- },
-
- .read_dqs_gate_delay = {
- 225, 227, 223, 225,
- 223, 225, 223, 227,
- 223, 225, 223, 225,
- 225, 227, 227, 229,
- },
-
-},
-};
-
-pll_set_t __pll_setting = {
- .cpu_clk = CPU_CLK / 24 * 24,
-#ifdef CONFIG_PXP_EMULATOR
- .pxp = 1,
-#else
- .pxp = 0,
-#endif
- .spi_ctrl = 0,
- .lCustomerID = AML_CUSTOMER_ID,
-#ifdef CONFIG_DEBUG_MODE
- .debug_mode = CONFIG_DEBUG_MODE,
- .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
- .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
-#endif
-};
-
-ddr_reg_t __ddr_reg[] = {
- /* demo, user defined override register */
- {0xaabbccdd, 0, 0, 0, 0, 0},
- {0x11223344, 0, 0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0},
-};
-
-#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
-#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
-/* VCCK PWM table */
-#if (VCCK_VAL == 800)
- #define VCCK_VAL_REG 0x00150007
-#elif (VCCK_VAL == 810)
- #define VCCK_VAL_REG 0x00140008
-#elif (VCCK_VAL == 820)
- #define VCCK_VAL_REG 0x00130009
-#elif (VCCK_VAL == 830)
- #define VCCK_VAL_REG 0x0012000a
-#elif (VCCK_VAL == 840)
- #define VCCK_VAL_REG 0x0011000b
-#elif (VCCK_VAL == 850)
- #define VCCK_VAL_REG 0x0010000c
-#elif (VCCK_VAL == 860)
- #define VCCK_VAL_REG 0x000f000d
-#elif (VCCK_VAL == 870)
- #define VCCK_VAL_REG 0x000e000e
-#elif (VCCK_VAL == 880)
- #define VCCK_VAL_REG 0x000d000f
-#elif (VCCK_VAL == 890)
- #define VCCK_VAL_REG 0x000c0010
-#elif (VCCK_VAL == 900)
- #define VCCK_VAL_REG 0x000b0011
-#elif (VCCK_VAL == 910)
- #define VCCK_VAL_REG 0x000a0012
-#elif (VCCK_VAL == 920)
- #define VCCK_VAL_REG 0x00090013
-#elif (VCCK_VAL == 930)
- #define VCCK_VAL_REG 0x00080014
-#elif (VCCK_VAL == 940)
- #define VCCK_VAL_REG 0x00070015
-#elif (VCCK_VAL == 950)
- #define VCCK_VAL_REG 0x00060016
-#elif (VCCK_VAL == 960)
- #define VCCK_VAL_REG 0x00050017
-#elif (VCCK_VAL == 970)
- #define VCCK_VAL_REG 0x00040018
-#elif (VCCK_VAL == 980)
- #define VCCK_VAL_REG 0x00030019
-#elif (VCCK_VAL == 990)
- #define VCCK_VAL_REG 0x0002001a
-#elif (VCCK_VAL == 1000)
- #define VCCK_VAL_REG 0x0001001b
-#elif (VCCK_VAL == 1010)
- #define VCCK_VAL_REG 0x0000001c
-#else
- #error "VCCK val out of range\n"
-#endif
-
-/* VDDEE PWM table */
-#if (VDDEE_VAL == 800)
- #define VDDEE_VAL_REG 0x0010000c
-#elif (VDDEE_VAL == 810)
- #define VDDEE_VAL_REG 0x000f000d
-#elif (VDDEE_VAL == 820)
- #define VDDEE_VAL_REG 0x000e000e
-#elif (VDDEE_VAL == 830)
- #define VDDEE_VAL_REG 0x000d000f
-#elif (VDDEE_VAL == 840)
- #define VDDEE_VAL_REG 0x000c0010
-#elif (VDDEE_VAL == 850)
- #define VDDEE_VAL_REG 0x000b0011
-#elif (VDDEE_VAL == 860)
- #define VDDEE_VAL_REG 0x000a0012
-#elif (VDDEE_VAL == 870)
- #define VDDEE_VAL_REG 0x00090013
-#elif (VDDEE_VAL == 880)
- #define VDDEE_VAL_REG 0x00080014
-#elif (VDDEE_VAL == 890)
- #define VDDEE_VAL_REG 0x00070015
-#elif (VDDEE_VAL == 900)
- #define VDDEE_VAL_REG 0x00060016
-#elif (VDDEE_VAL == 910)
- #define VDDEE_VAL_REG 0x00050017
-#elif (VDDEE_VAL == 920)
- #define VDDEE_VAL_REG 0x00040018
-#elif (VDDEE_VAL == 930)
- #define VDDEE_VAL_REG 0x00030019
-#elif (VDDEE_VAL == 940)
- #define VDDEE_VAL_REG 0x0002001a
-#elif (VDDEE_VAL == 950)
- #define VDDEE_VAL_REG 0x0001001b
-#elif (VDDEE_VAL == 960)
- #define VDDEE_VAL_REG 0x0000001c
-#else
- #error "VDDEE val out of range\n"
-#endif
-
-/* for PWM use */
-/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
-#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
-#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
-#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
-#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
-#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
-
-bl2_reg_t __bl2_reg[] = {
- /* demo, user defined override register */
- /* eg: PWM init */
-
- /* PWM_AO_D */
- /* VCCK_VAL_REG: check PWM table */
- {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
- {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
- /* PWM_AO_B */
- /* VDDEE_VAL_REG: check PWM table */
- {AO_PWM_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
- {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_1, 0},
- /* Enable 5V_EN */
- {GPIO_O_EN_N_REG3, (0 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
- {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- /* Enable VCCK */
- {AO_SEC_REG0, (1 << 0), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- {AO_GPIO_O, 0x80000000, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
-};
diff --git a/board/amlogic/sm1_elaine_p0/lcd.c b/board/amlogic/sm1_elaine_p0/lcd.c
deleted file mode 100755
index 969c86f..0000000
--- a/board/amlogic/sm1_elaine_p0/lcd.c
+++ /dev/null
@@ -1,489 +0,0 @@
-/*
- * AMLOGIC TV LCD panel driver.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#ifdef CONFIG_AML_LCD_EXTERN
-#include "lcd_extern.h"
-#endif
-
-static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
- "GPIOH_6", /* panel rst */
- "GPIOZ_8", /* panel power */
- "invalid", /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step[] = {
- {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
- {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,50,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
- {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step_TL050FHV02CT[] = {
- {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd reset: 0 */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_TL050FHV02CT[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step_TL070WSH27[] = {
- {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd reset: 0 */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd reset: 1 */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_TL070WSH27[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,10,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
- 0x05, 1, 0x11,
- 0xfd, 1, 20,
- 0x05, 1, 0x29,
- 0xfd, 1, 20,
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
- 0x05, 1, 0x28,
- 0xfd, 1, 10,
- 0x05, 1, 0x10,
- 0xfd, 1, 10,
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
- 0xfd, 1, 10,
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
- 0xff, 0, //ending
-};
-
-static unsigned char mipi_init_on_table_TL050FHV02CT[DSI_INIT_ON_MAX] = {//table size < 100
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_TL050FHV02CT[DSI_INIT_OFF_MAX] = {//table size < 50
- 0xff, 0, //ending
-};
-
-static unsigned char mipi_init_on_table_TL070WSH27[DSI_INIT_ON_MAX] = {//table size < 100
- 0x05, 1, 0x11,
- 0xfd, 1, 100,
- 0x05, 1, 0x29,
- 0xfd, 1, 20,
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_TL070WSH27[DSI_INIT_OFF_MAX] = {//table size < 50
- 0x05, 1, 0x28,
- 0xfd, 1, 100,
- 0x05, 1, 0x10,
- 0xfd, 1, 10,
- 0xff, 0, //ending
-};
-
-static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
- "GPIOH_4", /* BL_EN */
- "GPIOH_5", /* BL_PWM */
- "invalid", /* ending flag */
-};
-
-struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
- {/* B080XAN01*/
- "lcd_0",LCD_MIPI,8,
- /* basic timing */
- 768,1024,948,1140,64,56,0,50,30,0,
- /* clk_attr */
- 0,0,1,64843200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,550,0,1,0,2,1,0,Rsv_val,Rsv_val,
- /* cmd init */
- mipi_init_on_table, mipi_init_off_table,
- /* power step */
- lcd_power_on_step, lcd_power_off_step,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* TV070WSM*/
- "lcd_1",LCD_MIPI,8,
- /* basic timing */
- 600,1024,700,1053,24,36,0,2,8,0,
- /* clk_attr */
- 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,360,0,1,0,2,0,0,Rsv_val,1,
- /* cmd init */
- mipi_init_on_table, mipi_init_off_table,
- /* power step */
- lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_EXTERN,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* P070ACB*/
- "lcd_2",LCD_MIPI,8,
- /* basic timing */
- 600,1024,680,1194,24,36,0,10,80,0,
- /* clk_attr */
- 0,0,1,48715200,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,400,0,1,0,2,0,0,Rsv_val,2,
- /* cmd init */
- mipi_init_on_table, mipi_init_off_table,
- /* power step */
- lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_EXTERN,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* TV070WSM_FT*/
- "lcd_3",LCD_MIPI,8,
- /* basic timing */
- 600,1024,700,1053,24,36,0,2,8,0,
- /* clk_attr */
- 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,360,0,1,0,2,0,0,Rsv_val,3,
- /* cmd init */
- mipi_init_on_table, mipi_init_off_table,
- /* power step */
- lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* P070ACB_FT*/
- "lcd_4",LCD_MIPI,8,
- /* basic timing */
- 600,1024,770,1070,10,80,0,6,20,0,
- /* clk_attr */
- 0,0,1,49434000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,400,0,1,0,2,0,0,Rsv_val,1,
- /* cmd init */
- mipi_init_on_table_P070ACB, mipi_init_off_table_P070ACB,
- /* power step */
- lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {.panel_type = "invalid"},
-};
-
-static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
- {
- .name = "lcd_pin",
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
- },
- {
- .name = "invalid",
- },
-};
-
-static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
- {
- .name = "bl_pwm_on_pin", //GPIOH_5
- .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
- },
- {
- .name = "invalid",
- },
-};
-
-#ifdef CONFIG_AML_BL_EXTERN
-static unsigned char bl_ext_init_on[BL_EXTERN_INIT_ON_MAX] = {
- 0xff, 0, //ending flag
-};
-static unsigned char bl_ext_init_off[BL_EXTERN_INIT_OFF_MAX] = {
- 0xff, 0, //ending flag
-};
-#endif
-
-/* **********************************************
- * driver struct, usually no need modify!
- * ********************************************** */
-static struct dsi_config_s lcd_mipi_config = {
- .lane_num = 4,
- .bit_rate_max = 1000, /* MHz */
- .factor_numerator = 0,
- .factor_denominator = 100,
- .operation_mode_init = 1, /* 0=video mode, 1=command mode */
- .operation_mode_display = 0, /* 0=video mode, 1=command mode */
- .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
- .clk_always_hs = 1, /* 0=disable, 1=enable */
- .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
-
- .dsi_init_on = mipi_init_on_table,
- .dsi_init_off = mipi_init_off_table,
- .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
- .check_en = 0,
- .check_state = 0,
-};
-
-static struct lcd_power_ctrl_s lcd_power_ctrl = {
- .power_on_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
- .power_off_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
-};
-
-struct lcd_config_s lcd_config_dft = {
- .lcd_mode = LCD_MODE_TABLET,
- .lcd_key_valid = 0,
- .lcd_clk_path = 0,
- .lcd_basic = {
- .model_name = "default",
- .lcd_type = LCD_TYPE_MAX,
- .lcd_bits = 8,
- .h_active = 768,
- .v_active = 1024,
- .h_period = 948,
- .v_period = 1140,
-
- .screen_width = 119,
- .screen_height = 159,
- },
-
- .lcd_timing = {
- .clk_auto = 1,
- .lcd_clk = 64843200,
- .ss_level = 0,
- .fr_adjust_type = 0,
-
- .hsync_width = 64,
- .hsync_bp = 56,
- .hsync_pol = 0,
- .vsync_width = 50,
- .vsync_bp = 30,
- .vsync_pol = 0,
- },
-
- .lcd_control = {
- .mipi_config= &lcd_mipi_config,
- },
- .lcd_power = &lcd_power_ctrl,
-
- .pinctrl_ver = 2,
- .lcd_pinmux = lcd_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_LCD_EXTERN
-struct lcd_extern_common_s ext_common_dft = {
- .lcd_ext_key_valid = 0,
- .i2c_bus = LCD_EXTERN_I2C_BUS_0, /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
- .i2c_gpio_sck = LCD_EXT_I2C_GPIO_SCK,
- .i2c_gpio_sda = LCD_EXT_I2C_GPIO_SDA,
- .spi_gpio_cs = LCD_EXT_SPI_GPIO_CS,
- .spi_gpio_clk = LCD_EXT_SPI_GPIO_CLK,
- .spi_gpio_data = LCD_EXT_SPI_GPIO_DATA,
-
- .lcd_ext_pinmux = lcd_ext_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
- .pinmux_gpio_off = LCD_EXT_PINMUX_GPIO_OFF,
-};
-
-struct lcd_extern_config_s ext_config_dtf = {
- .index = 0,
- .name = "ext_default",
- .type = LCD_EXTERN_MAX, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 0, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
-};
-#endif
-
-struct bl_config_s bl_config_dft = {
- .name = "default",
- .bl_key_valid = 0,
-
- .level_default = 100,
- .level_min = 10,
- .level_max = 255,
- .level_mid = 128,
- .level_mid_mapping = 128,
- .level = 0,
-
- .method = BL_CTRL_MAX,
- .power_on_delay = 20,
- .power_off_delay = 20,
-
- .en_gpio = 0xff,
- .en_gpio_on = 1,
- .en_gpio_off = 0,
-
- .bl_pwm = NULL,
- .bl_pwm_combo0 = NULL,
- .bl_pwm_combo1 = NULL,
- .pwm_on_delay = 10,
- .pwm_off_delay = 10,
-
- .bl_extern_index = 0xff,
-
- .pinctrl_ver = 2,
- .bl_pinmux = bl_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_BL_EXTERN
-struct bl_extern_config_s bl_extern_config_dtf = {
- .index = BL_EXTERN_INDEX_INVALID,
- .name = "none",
- .type = BL_EXTERN_MAX,
- .i2c_addr = 0xff,
- .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
- .dim_min = 10,
- .dim_max = 255,
-
- .init_loaded = 0,
- .cmd_size = 0xff,
- .init_on = bl_ext_init_on,
- .init_off = bl_ext_init_off,
- .init_on_cnt = sizeof(bl_ext_init_on),
- .init_off_cnt = sizeof(bl_ext_init_off),
-};
-#endif
-/* ********************************************** */
-
-void lcd_config_bsp_init(void)
-{
- int i, j;
- char *str;
- struct ext_lcd_config_s *ext_lcd = NULL;
-
- /* init config, usually no need modify */
- for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
- break;
- strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
- }
- for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
- strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
- for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
- break;
- strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
- }
- for (j = i; j < BL_GPIO_NUM_MAX; j++)
- strcpy(bl_config_dft.gpio_name[j], "invalid");
-
-#ifdef CONFIG_AML_LCD_EXTERN
- for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
- break;
- strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
- }
- for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
- strcpy(ext_common_dft.gpio_name[j], "invalid");
-#endif
-
- /* select special config */
- str = env_get("panel_type");
- if (str == NULL)
- return;
- for (i = 0 ; i < LCD_NUM_MAX ; i++) {
- ext_lcd = &ext_lcd_config[i];
- if (strcmp(ext_lcd->panel_type, str) == 0) {
-#ifdef CONFIG_AML_LCD_EXTERN
- j = ext_lcd->if_attr_val9; /* mipi extern_index */
- if (j < sizeof(ext_config)/sizeof(struct lcd_extern_config_s)) {
- memcpy(&ext_config_dtf, &ext_config[j],
- sizeof(struct lcd_extern_config_s));
- }
-#endif
- break;
- }
- }
-}
diff --git a/board/amlogic/sm1_elaine_p0/lcd_extern.h b/board/amlogic/sm1_elaine_p0/lcd_extern.h
deleted file mode 100755
index cdcaf4c..0000000
--- a/board/amlogic/sm1_elaine_p0/lcd_extern.h
+++ /dev/null
@@ -1,1860 +0,0 @@
-/*
- * board/amlogic/g12a_u200_v1/lcd_extern.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _DFT_LCD_EXTERN_H_
-#define _DFT_LCD_EXTERN_H_
-
-#define LCD_EXT_I2C_GPIO_SCK 0xff /* 0xff for invalid */
-#define LCD_EXT_I2C_GPIO_SDA 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_CS 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_CLK 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_DATA 0xff /* 0xff for invalid */
-#define LCD_EXT_PINMUX_GPIO_OFF 0
-
-static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
- "invalid", /* ending flag */
-};
-
-static struct lcd_pinmux_ctrl_s lcd_ext_pinmux_ctrl[LCD_PINMX_MAX] = {
- {
- .name = "invalid",
- },
-};
-
-static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
- 0xff, 0, //ending flag
-};
-
-static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
- 0xff, 0, //ending flag
-};
-
-static unsigned char ext_init_on_table_P070ACB_FT[LCD_EXTERN_INIT_ON_MAX] = {
- 0x23,2,0xE0,0x00,//Page 0
- 0x23,2,0xE1,0x93,// PASSWORD
- 0x23,2,0xE2,0x65,
- 0x23,2,0xE3,0xF8,
- 0x23,2,0x80,0x03,
- 0x23,2,0xE0,0x01,//Page 01
- 0x23,2,0x0C,0x74,//Set PWRIC
- 0x23,2,0x17,0x00,//Set Gamma Power
- 0x23,2,0x18,0xEF,//VGMP=5.1V
- 0x23,2,0x19,0x00,
- 0x23,2,0x1A,0x00,
- 0x23,2,0x1B,0xEF,//VGMN=-5.1V
- 0x23,2,0x1C,0x00,
- 0x23,2,0x1F,0x70,//Set Gate Power
- 0x23,2,0x20,0x2D,
- 0x23,2,0x21,0x2D,
- 0x23,2,0x22,0x7E,
- 0x23,2,0x26,0xF3,//VDDD from IOVCC
- 0x23,2,0x37,0x09,//SetPanel
- 0x23,2,0x38,0x04,//SET RGBCYC
- 0x23,2,0x39,0x00,
- 0x23,2,0x3A,0x01,
- 0x23,2,0x3C,0x90,
- 0x23,2,0x3D,0xFF,
- 0x23,2,0x3E,0xFF,
- 0x23,2,0x3F,0xFF,
- 0x23,2,0x40,0x02,//Set TCON
- 0x23,2,0x41,0x80,
- 0x23,2,0x42,0x99,
- 0x23,2,0x43,0x14,
- 0x23,2,0x44,0x19,
- 0x23,2,0x45,0x5A,
- 0x23,2,0x4B,0x04,
- 0x23,2,0x55,0x02,//power voltage
- 0x23,2,0x56,0x01,
- 0x23,2,0x57,0x69,
- 0x23,2,0x58,0x0A,
- 0x23,2,0x59,0x0A,
- 0x23,2,0x5A,0x2E,//VGH = 16.2V
- 0x23,2,0x5B,0x19,//VGL = -12V
- 0x23,2,0x5C,0x15,
- 0x23,2,0x5D,0x77,//Gamma
- 0x23,2,0x5E,0x56,
- 0x23,2,0x5F,0x45,
- 0x23,2,0x60,0x38,
- 0x23,2,0x61,0x35,
- 0x23,2,0x62,0x27,
- 0x23,2,0x63,0x2D,
- 0x23,2,0x64,0x18,
- 0x23,2,0x65,0x33,
- 0x23,2,0x66,0x34,
- 0x23,2,0x67,0x35,
- 0x23,2,0x68,0x56,
- 0x23,2,0x69,0x45,
- 0x23,2,0x6A,0x4F,
- 0x23,2,0x6B,0x42,
- 0x23,2,0x6C,0x40,
- 0x23,2,0x6D,0x34,
- 0x23,2,0x6E,0x25,
- 0x23,2,0x6F,0x02,
- 0x23,2,0x70,0x77,
- 0x23,2,0x71,0x56,
- 0x23,2,0x72,0x45,
- 0x23,2,0x73,0x38,
- 0x23,2,0x74,0x35,
- 0x23,2,0x75,0x27,
- 0x23,2,0x76,0x2D,
- 0x23,2,0x77,0x18,
- 0x23,2,0x78,0x33,
- 0x23,2,0x79,0x34,
- 0x23,2,0x7A,0x35,
- 0x23,2,0x7B,0x56,
- 0x23,2,0x7C,0x45,
- 0x23,2,0x7D,0x4F,
- 0x23,2,0x7E,0x42,
- 0x23,2,0x7F,0x40,
- 0x23,2,0x80,0x34,
- 0x23,2,0x81,0x25,
- 0x23,2,0x82,0x02,
- 0x23,2,0xE0,0x02,//Page2
- 0x23,2,0x00,0x53,//GIP_L Pin mapping RESET_EVEN
- 0x23,2,0x01,0x55,//VSSG_EVEN
- 0x23,2,0x02,0x55,//VSSA_EVEN
- 0x23,2,0x03,0x51,//STV2_EVEN
- 0x23,2,0x04,0x77,//VDD2_EVEN
- 0x23,2,0x05,0x57,//VDD1_EVEN
- 0x23,2,0x06,0x1F,
- 0x23,2,0x07,0x4F, //CK12
- 0x23,2,0x08,0x4D, //CK10
- 0x23,2,0x09,0x1F,
- 0x23,2,0x0A,0x4B, //CK8
- 0x23,2,0x0B,0x49, //CK6
- 0x23,2,0x0C,0x1F,
- 0x23,2,0x0D,0x47, //CK4
- 0x23,2,0x0E,0x45, //CK2
- 0x23,2,0x0F,0x41, //STV1_EVEN
- 0x23,2,0x10,0x1F,
- 0x23,2,0x11,0x1F,
- 0x23,2,0x12,0x1F,
- 0x23,2,0x13,0x55, //VGG
- 0x23,2,0x14,0x1F,
- 0x23,2,0x15,0x1F,
- 0x23,2,0x16,0x52,//GIP_R Pin mapping RESET_ODD
- 0x23,2,0x17,0x55, //VSSG_ODD
- 0x23,2,0x18,0x55, //VSSA_ODD
- 0x23,2,0x19,0x50, //STV2_ODD
- 0x23,2,0x1A,0x77,//VDD2_ODD
- 0x23,2,0x1B,0x57,//VDD1_ODD
- 0x23,2,0x1C,0x1F,
- 0x23,2,0x1D,0x4E, //CK11
- 0x23,2,0x1E,0x4C, //CK9
- 0x23,2,0x1F,0x1F,
- 0x23,2,0x20,0x4A, //CK7
- 0x23,2,0x21,0x48, //CK5
- 0x23,2,0x22,0x1F,
- 0x23,2,0x23,0x46, //CK3
- 0x23,2,0x24,0x44, //CK1
- 0x23,2,0x25,0x40,//STV1_ODD
- 0x23,2,0x26,0x1F,
- 0x23,2,0x27,0x1F,
- 0x23,2,0x28,0x1F,
- 0x23,2,0x29,0x1F,
- 0x23,2,0x2A,0x1F,
- 0x23,2,0x2B,0x55, //VGG
- 0x23,2,0x2C,0x12,//GIP_L_GS Pin mapping
- 0x23,2,0x2D,0x15,
- 0x23,2,0x2E,0x15,
- 0x23,2,0x2F,0x00,
- 0x23,2,0x30,0x37,
- 0x23,2,0x31,0x17,
- 0x23,2,0x32,0x1F,
- 0x23,2,0x33,0x08,
- 0x23,2,0x34,0x0A,
- 0x23,2,0x35,0x1F,
- 0x23,2,0x36,0x0C,
- 0x23,2,0x37,0x0E,
- 0x23,2,0x38,0x1F,
- 0x23,2,0x39,0x04,
- 0x23,2,0x3A,0x06,
- 0x23,2,0x3B,0x10,
- 0x23,2,0x3C,0x1F,
- 0x23,2,0x3D,0x1F,
- 0x23,2,0x3E,0x1F,
- 0x23,2,0x3F,0x15,
- 0x23,2,0x40,0x1F,
- 0x23,2,0x41,0x1F,
- 0x23,2,0x42,0x13,//GIP_R_GS Pin mapping
- 0x23,2,0x43,0x15,
- 0x23,2,0x44,0x15,
- 0x23,2,0x45,0x01,
- 0x23,2,0x46,0x37,
- 0x23,2,0x47,0x17,
- 0x23,2,0x48,0x1F,
- 0x23,2,0x49,0x09,
- 0x23,2,0x4A,0x0B,
- 0x23,2,0x4B,0x1F,
- 0x23,2,0x4C,0x0D,
- 0x23,2,0x4D,0x0F,
- 0x23,2,0x4E,0x1F,
- 0x23,2,0x4F,0x05,
- 0x23,2,0x50,0x07,
- 0x23,2,0x51,0x11,
- 0x23,2,0x52,0x1F,
- 0x23,2,0x53,0x1F,
- 0x23,2,0x54,0x1F,
- 0x23,2,0x55,0x1F,
- 0x23,2,0x56,0x1F,
- 0x23,2,0x57,0x15,
- 0x23,2,0x58,0x40,//GIP Timing
- 0x23,2,0x59,0x00,
- 0x23,2,0x5A,0x00,
- 0x23,2,0x5B,0x10,
- 0x23,2,0x5C,0x14,
- 0x23,2,0x5D,0x40,
- 0x23,2,0x5E,0x01,
- 0x23,2,0x5F,0x02,
- 0x23,2,0x60,0x40,
- 0x23,2,0x61,0x03,
- 0x23,2,0x62,0x04,
- 0x23,2,0x63,0x7A,
- 0x23,2,0x64,0x7A,
- 0x23,2,0x65,0x74,
- 0x23,2,0x66,0x16,
- 0x23,2,0x67,0xB4,
- 0x23,2,0x68,0x16,
- 0x23,2,0x69,0x7A,
- 0x23,2,0x6A,0x7A,
- 0x23,2,0x6B,0x0C,
- 0x23,2,0x6C,0x00,
- 0x23,2,0x6D,0x04,
- 0x23,2,0x6E,0x04,
- 0x23,2,0x6F,0x88,
- 0x23,2,0x70,0x00,
- 0x23,2,0x71,0x00,
- 0x23,2,0x72,0x06,
- 0x23,2,0x73,0x7B,
- 0x23,2,0x74,0x00,
- 0x23,2,0x75,0xBC,
- 0x23,2,0x76,0x00,
- 0x23,2,0x77,0x04,
- 0x23,2,0x78,0x2C,
- 0x23,2,0x79,0x00,
- 0x23,2,0x7A,0x00,
- 0x23,2,0x7B,0x00,
- 0x23,2,0x7C,0x00,
- 0x23,2,0x7D,0x03,
- 0x23,2,0x7E,0x7B,
- 0x23,2,0xE0,0x04,//Page4
- 0x23,2,0x09,0x11,//Set RGBCYC2
- 0x23,2,0x0E,0x48,
- 0x23,2,0x2B,0x2B,//ESD Protect
- 0x23,2,0x2E,0x44,
- 0x23,2,0xE0,0x00,//Page0
- 0x23,2,0xE6,0x02,//Watch dog
- 0x23,2,0xE7,0x0C,
- 0x05,1,0x11,//sleep out
- 0xfd, 1,120,
- 0x05,1,0x29,//display on
- 0x05,1,0x35,
- 0xfd, 1, 20, /* delay(ms) */
- 0xFF, 0, /* ending flag */
-};
-
-static unsigned char ext_init_off_table_P070ACB_FT[LCD_EXTERN_INIT_OFF_MAX] = {
- 0x05, 1, 0x28, /* display off */
- 0xfd, 1, 10, /* delay 10ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xfd, 1, 150, /* delay 150ms */
- 0xFF, 0, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_TL050FHV02CT[LCD_EXTERN_INIT_ON_MAX] = {
- //LCD driver initialization
- 0x23, 2, 0XFF, 0X05,
- 0x23, 2, 0XFB, 0X01,
- 0x23, 2, 0XC5, 0X01, //TURN ON
- 0xfd, 1, 100,
-
- //AUO4.97+NT35596_intial
- 0x23, 2, 0XFF, 0XEE, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X1F, 0X45,
- 0x23, 2, 0X24, 0X4F,
- 0x23, 2, 0X38, 0XC8,
- 0x23, 2, 0X39, 0X2C,
- 0x23, 2, 0X1E, 0XBB,
- 0x23, 2, 0X1D, 0X0F,
- 0x23, 2, 0X7E, 0XB1,
-
- 0x23, 2, 0XFF, 0X00, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X35, 0X01,
-
- 0x23, 2, 0XFF, 0X01, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X00, 0X01,
- 0x23, 2, 0X01, 0X55,
- 0x23, 2, 0X02, 0X40,
- 0x23, 2, 0X05, 0X40,
- 0x23, 2, 0X06, 0X4A,
- 0x23, 2, 0X07, 0X24,
- 0x23, 2, 0X08, 0X0C,
- 0x23, 2, 0X0B, 0X87,
- 0x23, 2, 0X0C, 0X87,
- 0x23, 2, 0X0E, 0XB0,
- 0x23, 2, 0X0F, 0XB3,
- 0x23, 2, 0X11, 0X10,
- 0x23, 2, 0X12, 0X10,
- 0x23, 2, 0X13, 0X05,
- 0x23, 2, 0X14, 0X4A,
- 0x23, 2, 0X15, 0X18,
- 0x23, 2, 0X16, 0X18,
- 0x23, 2, 0X18, 0X00,
- 0x23, 2, 0X19, 0X77,
- 0x23, 2, 0X1A, 0X55,
- 0x23, 2, 0X1B, 0X13,
- 0x23, 2, 0X1C, 0X00,
- 0x23, 2, 0X1D, 0X00,
- 0x23, 2, 0X1E, 0X13,
- 0x23, 2, 0X1F, 0X00,
- 0x23, 2, 0X23, 0X00,
- 0x23, 2, 0X24, 0X00,
- 0x23, 2, 0X25, 0X00,
- 0x23, 2, 0X26, 0X00,
- 0x23, 2, 0X27, 0X00,
- 0x23, 2, 0X28, 0X00,
- 0x23, 2, 0X35, 0X00,
- 0x23, 2, 0X66, 0X00,
- 0x23, 2, 0X58, 0X82,
- 0x23, 2, 0X59, 0X02,
- 0x23, 2, 0X5A, 0X02,
- 0x23, 2, 0X5B, 0X02,
- 0x23, 2, 0X5C, 0X82,
- 0x23, 2, 0X5D, 0X82,
- 0x23, 2, 0X5E, 0X02,
- 0x23, 2, 0X5F, 0X02,
- 0x23, 2, 0X72, 0X31,
-
- 0x23, 2, 0XFF, 0X05, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X00, 0X01,
- 0x23, 2, 0X01, 0X0B,
- 0x23, 2, 0X02, 0X0C,
- 0x23, 2, 0X03, 0X09,
- 0x23, 2, 0X04, 0X0A,
- 0x23, 2, 0X05, 0X00,
- 0x23, 2, 0X06, 0X0F,
- 0x23, 2, 0X07, 0X10,
- 0x23, 2, 0X08, 0X00,
- 0x23, 2, 0X09, 0X00,
- 0x23, 2, 0X0A, 0X00,
- 0x23, 2, 0X0B, 0X00,
- 0x23, 2, 0X0C, 0X00,
- 0x23, 2, 0X0D, 0X13,
- 0x23, 2, 0X0E, 0X15,
- 0x23, 2, 0X0F, 0X17,
- 0x23, 2, 0X10, 0X01,
- 0x23, 2, 0X11, 0X0B,
- 0x23, 2, 0X12, 0X0C,
- 0x23, 2, 0X13, 0X09,
- 0x23, 2, 0X14, 0X0A,
- 0x23, 2, 0X15, 0X00,
- 0x23, 2, 0X16, 0X0F,
- 0x23, 2, 0X17, 0X10,
- 0x23, 2, 0X18, 0X00,
- 0x23, 2, 0X19, 0X00,
- 0x23, 2, 0X1A, 0X00,
- 0x23, 2, 0X1B, 0X00,
- 0x23, 2, 0X1C, 0X00,
- 0x23, 2, 0X1D, 0X13,
- 0x23, 2, 0X1E, 0X15,
- 0x23, 2, 0X1F, 0X17,
- 0x23, 2, 0X20, 0X00,
- 0x23, 2, 0X21, 0X03,
- 0x23, 2, 0X22, 0X01,
- 0x23, 2, 0X23, 0X40,
- 0x23, 2, 0X24, 0X40,
- 0x23, 2, 0X25, 0XED,
- 0x23, 2, 0X29, 0X58,
- 0x23, 2, 0X2A, 0X12,
- 0x23, 2, 0X2B, 0X01,
- 0x23, 2, 0X4B, 0X06,
- 0x23, 2, 0X4C, 0X11,
- 0x23, 2, 0X4D, 0X20,
- 0x23, 2, 0X4E, 0X02,
- 0x23, 2, 0X4F, 0X02,
- 0x23, 2, 0X50, 0X20,
- 0x23, 2, 0X51, 0X61,
- 0x23, 2, 0X52, 0X01,
- 0x23, 2, 0X53, 0X63,
- 0x23, 2, 0X54, 0X77,
- 0x23, 2, 0X55, 0XED,
- 0x23, 2, 0X5B, 0X00,
- 0x23, 2, 0X5C, 0X00,
- 0x23, 2, 0X5D, 0X00,
- 0x23, 2, 0X5E, 0X00,
- 0x23, 2, 0X5F, 0X15,
- 0x23, 2, 0X60, 0X75,
- 0x23, 2, 0X61, 0X00,
- 0x23, 2, 0X62, 0X00,
- 0x23, 2, 0X63, 0X00,
- 0x23, 2, 0X64, 0X00,
- 0x23, 2, 0X65, 0X00,
- 0x23, 2, 0X66, 0X00,
- 0x23, 2, 0X67, 0X00,
- 0x23, 2, 0X68, 0X04,
- 0x23, 2, 0X69, 0X00,
- 0x23, 2, 0X6A, 0X00,
- 0x23, 2, 0X6C, 0X40,
- 0x23, 2, 0X75, 0X01,
- 0x23, 2, 0X76, 0X01,
- 0x23, 2, 0X7A, 0X80,
- 0x23, 2, 0X7B, 0XC5,
- 0x23, 2, 0X7C, 0XD8,
- 0x23, 2, 0X7D, 0X60,
- 0x23, 2, 0X7F, 0X15,
- 0x23, 2, 0X80, 0X81,
- 0x23, 2, 0X83, 0X05,
- 0x23, 2, 0X93, 0X08,
- 0x23, 2, 0X94, 0X10,
- 0x23, 2, 0X8A, 0X00,
- 0x23, 2, 0X9B, 0X0F,
- 0x23, 2, 0XEA, 0XFF,
- 0x23, 2, 0XEC, 0X00,
-
- 0x23, 2, 0XFF, 0X01, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X75, 0X00, //Gamma R+
- 0x23, 2, 0X76, 0X18,
- 0x23, 2, 0X77, 0X00,
- 0x23, 2, 0X78, 0X38,
- 0x23, 2, 0X79, 0X00,
- 0x23, 2, 0X7A, 0X65,
- 0x23, 2, 0X7B, 0X00,
- 0x23, 2, 0X7C, 0X84,
- 0x23, 2, 0X7D, 0X00,
- 0x23, 2, 0X7E, 0X9B,
- 0x23, 2, 0X7F, 0X00,
- 0x23, 2, 0X80, 0XAF,
- 0x23, 2, 0X81, 0X00,
- 0x23, 2, 0X82, 0XC1,
- 0x23, 2, 0X83, 0X00,
- 0x23, 2, 0X84, 0XD2,
- 0x23, 2, 0X85, 0X00,
- 0x23, 2, 0X86, 0XDF,
- 0x23, 2, 0X87, 0X01,
- 0x23, 2, 0X88, 0X11,
- 0x23, 2, 0X89, 0X01,
- 0x23, 2, 0X8A, 0X38,
- 0x23, 2, 0X8B, 0X01,
- 0x23, 2, 0X8C, 0X76,
- 0x23, 2, 0X8D, 0X01,
- 0x23, 2, 0X8E, 0XA7,
- 0x23, 2, 0X8F, 0X01,
- 0x23, 2, 0X90, 0XF3,
- 0x23, 2, 0X91, 0X02,
- 0x23, 2, 0X92, 0X2F,
- 0x23, 2, 0X93, 0X02,
- 0x23, 2, 0X94, 0X30,
- 0x23, 2, 0X95, 0X02,
- 0x23, 2, 0X96, 0X66,
- 0x23, 2, 0X97, 0X02,
- 0x23, 2, 0X98, 0XA0,
- 0x23, 2, 0X99, 0X02,
- 0x23, 2, 0X9A, 0XC5,
- 0x23, 2, 0X9B, 0X02,
- 0x23, 2, 0X9C, 0XF8,
- 0x23, 2, 0X9D, 0X03,
- 0x23, 2, 0X9E, 0X1B,
- 0x23, 2, 0X9F, 0X03,
- 0x23, 2, 0XA0, 0X46,
- 0x23, 2, 0XA2, 0X03,
- 0x23, 2, 0XA3, 0X52,
- 0x23, 2, 0XA4, 0X03,
- 0x23, 2, 0XA5, 0X62,
- 0x23, 2, 0XA6, 0X03,
- 0x23, 2, 0XA7, 0X71,
- 0x23, 2, 0XA9, 0X03,
- 0x23, 2, 0XAA, 0X83,
- 0x23, 2, 0XAB, 0X03,
- 0x23, 2, 0XAC, 0X94,
- 0x23, 2, 0XAD, 0X03,
- 0x23, 2, 0XAE, 0XA3,
- 0x23, 2, 0XAF, 0X03,
- 0x23, 2, 0XB0, 0XAD,
- 0x23, 2, 0XB1, 0X03,
- 0x23, 2, 0XB2, 0XCC,
-
- 0x23, 2, 0XB3, 0X00, //Gamma R-
- 0x23, 2, 0XB4, 0X18,
- 0x23, 2, 0XB5, 0X00,
- 0x23, 2, 0XB6, 0X38,
- 0x23, 2, 0XB7, 0X00,
- 0x23, 2, 0XB8, 0X65,
- 0x23, 2, 0XB9, 0X00,
- 0x23, 2, 0XBA, 0X84,
- 0x23, 2, 0XBB, 0X00,
- 0x23, 2, 0XBC, 0X9B,
- 0x23, 2, 0XBD, 0X00,
- 0x23, 2, 0XBE, 0XAF,
- 0x23, 2, 0XBF, 0X00,
- 0x23, 2, 0XC0, 0XC1,
- 0x23, 2, 0XC1, 0X00,
- 0x23, 2, 0XC2, 0XD2,
- 0x23, 2, 0XC3, 0X00,
- 0x23, 2, 0XC4, 0XDF,
- 0x23, 2, 0XC5, 0X01,
- 0x23, 2, 0XC6, 0X11,
- 0x23, 2, 0XC7, 0X01,
- 0x23, 2, 0XC8, 0X38,
- 0x23, 2, 0XC9, 0X01,
- 0x23, 2, 0XCA, 0X76,
- 0x23, 2, 0XCB, 0X01,
- 0x23, 2, 0XCC, 0XA7,
- 0x23, 2, 0XCD, 0X01,
- 0x23, 2, 0XCE, 0XF3,
- 0x23, 2, 0XCF, 0X02,
- 0x23, 2, 0XD0, 0X2F,
- 0x23, 2, 0XD1, 0X02,
- 0x23, 2, 0XD2, 0X30,
- 0x23, 2, 0XD3, 0X02,
- 0x23, 2, 0XD4, 0X66,
- 0x23, 2, 0XD5, 0X02,
- 0x23, 2, 0XD6, 0XA0,
- 0x23, 2, 0XD7, 0X02,
- 0x23, 2, 0XD8, 0XC5,
- 0x23, 2, 0XD9, 0X02,
- 0x23, 2, 0XDA, 0XF8,
- 0x23, 2, 0XDB, 0X03,
- 0x23, 2, 0XDC, 0X1B,
- 0x23, 2, 0XDD, 0X03,
- 0x23, 2, 0XDE, 0X46,
- 0x23, 2, 0XDF, 0X03,
- 0x23, 2, 0XE0, 0X52,
- 0x23, 2, 0XE1, 0X03,
- 0x23, 2, 0XE2, 0X62,
- 0x23, 2, 0XE3, 0X03,
- 0x23, 2, 0XE4, 0X71,
- 0x23, 2, 0XE5, 0X03,
- 0x23, 2, 0XE6, 0X83,
- 0x23, 2, 0XE7, 0X03,
- 0x23, 2, 0XE8, 0X94,
- 0x23, 2, 0XE9, 0X03,
- 0x23, 2, 0XEA, 0XA3,
- 0x23, 2, 0XEB, 0X03,
- 0x23, 2, 0XEC, 0XAD,
- 0x23, 2, 0XED, 0X03,
- 0x23, 2, 0XEE, 0XCC,
-
- 0x23, 2, 0XEF, 0X00, //Gamma G+
- 0x23, 2, 0XF0, 0X18,
- 0x23, 2, 0XF1, 0X00,
- 0x23, 2, 0XF2, 0X38,
- 0x23, 2, 0XF3, 0X00,
- 0x23, 2, 0XF4, 0X65,
- 0x23, 2, 0XF5, 0X00,
- 0x23, 2, 0XF6, 0X84,
- 0x23, 2, 0XF7, 0X00,
- 0x23, 2, 0XF8, 0X9B,
- 0x23, 2, 0XF9, 0X00,
- 0x23, 2, 0XFA, 0XAF,
- 0x23, 2, 0XFF, 0X02, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0X00, 0X00,
- 0x23, 2, 0X01, 0XC1,
- 0x23, 2, 0X02, 0X00,
- 0x23, 2, 0X03, 0XD2,
- 0x23, 2, 0X04, 0X00,
- 0x23, 2, 0X05, 0XDF,
- 0x23, 2, 0X06, 0X01,
- 0x23, 2, 0X07, 0X11,
- 0x23, 2, 0X08, 0X01,
- 0x23, 2, 0X09, 0X38,
- 0x23, 2, 0X0A, 0X01,
- 0x23, 2, 0X0B, 0X76,
- 0x23, 2, 0X0C, 0X01,
- 0x23, 2, 0X0D, 0XA7,
- 0x23, 2, 0X0E, 0X01,
- 0x23, 2, 0X0F, 0XF3,
- 0x23, 2, 0X10, 0X02,
- 0x23, 2, 0X11, 0X2F,
- 0x23, 2, 0X12, 0X02,
- 0x23, 2, 0X13, 0X30,
- 0x23, 2, 0X14, 0X02,
- 0x23, 2, 0X15, 0X66,
- 0x23, 2, 0X16, 0X02,
- 0x23, 2, 0X17, 0XA0,
- 0x23, 2, 0X18, 0X02,
- 0x23, 2, 0X19, 0XC5,
- 0x23, 2, 0X1A, 0X02,
- 0x23, 2, 0X1B, 0XF8,
- 0x23, 2, 0X1C, 0X03,
- 0x23, 2, 0X1D, 0X1B,
- 0x23, 2, 0X1E, 0X03,
- 0x23, 2, 0X1F, 0X46,
- 0x23, 2, 0X20, 0X03,
- 0x23, 2, 0X21, 0X52,
- 0x23, 2, 0X22, 0X03,
- 0x23, 2, 0X23, 0X62,
- 0x23, 2, 0X24, 0X03,
- 0x23, 2, 0X25, 0X71,
- 0x23, 2, 0X26, 0X03,
- 0x23, 2, 0X27, 0X83,
- 0x23, 2, 0X28, 0X03,
- 0x23, 2, 0X29, 0X94,
- 0x23, 2, 0X2A, 0X03,
- 0x23, 2, 0X2B, 0XA3,
- 0x23, 2, 0X2D, 0X03,
- 0x23, 2, 0X2F, 0XAD,
- 0x23, 2, 0X30, 0X03,
- 0x23, 2, 0X31, 0XCC,
-
- 0x23, 2, 0X32, 0X00, //Gamma G-
- 0x23, 2, 0X33, 0X18,
- 0x23, 2, 0X34, 0X00,
- 0x23, 2, 0X35, 0X38,
- 0x23, 2, 0X36, 0X00,
- 0x23, 2, 0X37, 0X65,
- 0x23, 2, 0X38, 0X00,
- 0x23, 2, 0X39, 0X84,
- 0x23, 2, 0X3A, 0X00,
- 0x23, 2, 0X3B, 0X9B,
- 0x23, 2, 0X3D, 0X00,
- 0x23, 2, 0X3F, 0XAF,
- 0x23, 2, 0X40, 0X00,
- 0x23, 2, 0X41, 0XC1,
- 0x23, 2, 0X42, 0X00,
- 0x23, 2, 0X43, 0XD2,
- 0x23, 2, 0X44, 0X00,
- 0x23, 2, 0X45, 0XDF,
- 0x23, 2, 0X46, 0X01,
- 0x23, 2, 0X47, 0X11,
- 0x23, 2, 0X48, 0X01,
- 0x23, 2, 0X49, 0X38,
- 0x23, 2, 0X4A, 0X01,
- 0x23, 2, 0X4B, 0X76,
- 0x23, 2, 0X4C, 0X01,
- 0x23, 2, 0X4D, 0XA7,
- 0x23, 2, 0X4E, 0X01,
- 0x23, 2, 0X4F, 0XF3,
- 0x23, 2, 0X50, 0X02,
- 0x23, 2, 0X51, 0X2F,
- 0x23, 2, 0X52, 0X02,
- 0x23, 2, 0X53, 0X30,
- 0x23, 2, 0X54, 0X02,
- 0x23, 2, 0X55, 0X66,
- 0x23, 2, 0X56, 0X02,
- 0x23, 2, 0X58, 0XA0,
- 0x23, 2, 0X59, 0X02,
- 0x23, 2, 0X5A, 0XC5,
- 0x23, 2, 0X5B, 0X02,
- 0x23, 2, 0X5C, 0XF8,
- 0x23, 2, 0X5D, 0X03,
- 0x23, 2, 0X5E, 0X1B,
- 0x23, 2, 0X5F, 0X03,
- 0x23, 2, 0X60, 0X46,
- 0x23, 2, 0X61, 0X03,
- 0x23, 2, 0X62, 0X52,
- 0x23, 2, 0X63, 0X03,
- 0x23, 2, 0X64, 0X62,
- 0x23, 2, 0X65, 0X03,
- 0x23, 2, 0X66, 0X71,
- 0x23, 2, 0X67, 0X03,
- 0x23, 2, 0X68, 0X83,
- 0x23, 2, 0X69, 0X03,
- 0x23, 2, 0X6A, 0X94,
- 0x23, 2, 0X6B, 0X03,
- 0x23, 2, 0X6C, 0XA3,
- 0x23, 2, 0X6D, 0X03,
- 0x23, 2, 0X6E, 0XAD,
- 0x23, 2, 0X6F, 0X03,
- 0x23, 2, 0X70, 0XCC,
-
- 0x23, 2, 0X71, 0X00, //Gamma B+
- 0x23, 2, 0X72, 0X18,
- 0x23, 2, 0X73, 0X00,
- 0x23, 2, 0X74, 0X38,
- 0x23, 2, 0X75, 0X00,
- 0x23, 2, 0X76, 0X65,
- 0x23, 2, 0X77, 0X00,
- 0x23, 2, 0X78, 0X84,
- 0x23, 2, 0X79, 0X00,
- 0x23, 2, 0X7A, 0X9B,
- 0x23, 2, 0X7B, 0X00,
- 0x23, 2, 0X7C, 0XAF,
- 0x23, 2, 0X7D, 0X00,
- 0x23, 2, 0X7E, 0XC1,
- 0x23, 2, 0X7F, 0X00,
- 0x23, 2, 0X80, 0XD2,
- 0x23, 2, 0X81, 0X00,
- 0x23, 2, 0X82, 0XDF,
- 0x23, 2, 0X83, 0X01,
- 0x23, 2, 0X84, 0X11,
- 0x23, 2, 0X85, 0X01,
- 0x23, 2, 0X86, 0X38,
- 0x23, 2, 0X87, 0X01,
- 0x23, 2, 0X88, 0X76,
- 0x23, 2, 0X89, 0X01,
- 0x23, 2, 0X8A, 0XA7,
- 0x23, 2, 0X8B, 0X01,
- 0x23, 2, 0X8C, 0XF3,
- 0x23, 2, 0X8D, 0X02,
- 0x23, 2, 0X8E, 0X2F,
- 0x23, 2, 0X8F, 0X02,
- 0x23, 2, 0X90, 0X30,
- 0x23, 2, 0X91, 0X02,
- 0x23, 2, 0X92, 0X66,
- 0x23, 2, 0X93, 0X02,
- 0x23, 2, 0X94, 0XA0,
- 0x23, 2, 0X95, 0X02,
- 0x23, 2, 0X96, 0XC5,
- 0x23, 2, 0X97, 0X02,
- 0x23, 2, 0X98, 0XF8,
- 0x23, 2, 0X99, 0X03,
- 0x23, 2, 0X9A, 0X1B,
- 0x23, 2, 0X9B, 0X03,
- 0x23, 2, 0X9C, 0X46,
- 0x23, 2, 0X9D, 0X03,
- 0x23, 2, 0X9E, 0X52,
- 0x23, 2, 0X9F, 0X03,
- 0x23, 2, 0XA0, 0X62,
- 0x23, 2, 0XA2, 0X03,
- 0x23, 2, 0XA3, 0X71,
- 0x23, 2, 0XA4, 0X03,
- 0x23, 2, 0XA5, 0X83,
- 0x23, 2, 0XA6, 0X03,
- 0x23, 2, 0XA7, 0X94,
- 0x23, 2, 0XA9, 0X03,
- 0x23, 2, 0XAA, 0XA3,
- 0x23, 2, 0XAB, 0X03,
- 0x23, 2, 0XAC, 0XAD,
- 0x23, 2, 0XAD, 0X03,
- 0x23, 2, 0XAE, 0XCC,
-
- 0x23, 2, 0XAF, 0X00, //Gamma B-
- 0x23, 2, 0XB0, 0X18,
- 0x23, 2, 0XB1, 0X00,
- 0x23, 2, 0XB2, 0X38,
- 0x23, 2, 0XB3, 0X00,
- 0x23, 2, 0XB4, 0X65,
- 0x23, 2, 0XB5, 0X00,
- 0x23, 2, 0XB6, 0X84,
- 0x23, 2, 0XB7, 0X00,
- 0x23, 2, 0XB8, 0X9B,
- 0x23, 2, 0XB9, 0X00,
- 0x23, 2, 0XBA, 0XAF,
- 0x23, 2, 0XBB, 0X00,
- 0x23, 2, 0XBC, 0XC1,
- 0x23, 2, 0XBD, 0X00,
- 0x23, 2, 0XBE, 0XD2,
- 0x23, 2, 0XBF, 0X00,
- 0x23, 2, 0XC0, 0XDF,
- 0x23, 2, 0XC1, 0X01,
- 0x23, 2, 0XC2, 0X11,
- 0x23, 2, 0XC3, 0X01,
- 0x23, 2, 0XC4, 0X38,
- 0x23, 2, 0XC5, 0X01,
- 0x23, 2, 0XC6, 0X76,
- 0x23, 2, 0XC7, 0X01,
- 0x23, 2, 0XC8, 0XA7,
- 0x23, 2, 0XC9, 0X01,
- 0x23, 2, 0XCA, 0XF3,
- 0x23, 2, 0XCB, 0X02,
- 0x23, 2, 0XCC, 0X2F,
- 0x23, 2, 0XCD, 0X02,
- 0x23, 2, 0XCE, 0X30,
- 0x23, 2, 0XCF, 0X02,
- 0x23, 2, 0XD0, 0X66,
- 0x23, 2, 0XD1, 0X02,
- 0x23, 2, 0XD2, 0XA0,
- 0x23, 2, 0XD3, 0X02,
- 0x23, 2, 0XD4, 0XC5,
- 0x23, 2, 0XD5, 0X02,
- 0x23, 2, 0XD6, 0XF8,
- 0x23, 2, 0XD7, 0X03,
- 0x23, 2, 0XD8, 0X1B,
- 0x23, 2, 0XD9, 0X03,
- 0x23, 2, 0XDA, 0X46,
- 0x23, 2, 0XDB, 0X03,
- 0x23, 2, 0XDC, 0X52,
- 0x23, 2, 0XDD, 0X03,
- 0x23, 2, 0XDE, 0X62,
- 0x23, 2, 0XDF, 0X03,
- 0x23, 2, 0XE0, 0X71,
- 0x23, 2, 0XE1, 0X03,
- 0x23, 2, 0XE2, 0X83,
- 0x23, 2, 0XE3, 0X03,
- 0x23, 2, 0XE4, 0X94,
- 0x23, 2, 0XE5, 0X03,
- 0x23, 2, 0XE6, 0XA3,
- 0x23, 2, 0XE7, 0X03,
- 0x23, 2, 0XE8, 0XAD,
- 0x23, 2, 0XE9, 0X03,
- 0x23, 2, 0XEA, 0XCC,
-
- 0x23, 2, 0XFF, 0X01, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0XFF, 0X02, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0XFF, 0X04, //CMD page select
- 0x23, 2, 0XFB, 0X01, //NON-RELOAD CMD
- 0x23, 2, 0XFF, 0X00, //CMD page select
-
- 0x23, 2, 0XD3, 0X05,
- 0x23, 2, 0XD4, 0X04,
-
- 0x23, 2, 0X11, 0X00, //Sleep out
- 0xfd, 1, 100, //delay 100ms
- 0x23, 2, 0XFF, 0X00,
-
- 0x23, 2, 0X35, 0X00, //TE on
-
- 0x23, 2, 0X29, 0X00, //Display on
- 0xfd, 1, 100, //delay 100ms
- 0xff, 0, /* ending flag */
-};
-
-static unsigned char ext_init_off_table_TL050FHV02CT[LCD_EXTERN_INIT_OFF_MAX] = {
- 0x05, 1, 0x28, /* display off */
- 0xfd, 1, 10, /* delay 10ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xfd, 1, 150, /* delay 150ms */
- 0xFF, 0, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_TV101WXM[LCD_EXTERN_INIT_ON_MAX] = {
- 0xFF, 120,
- 0x29, 5, 0xFF, 0xAA, 0x55, 0x25, 0x01,
- 0x23, 2, 0xFC, 0x08,
- 0xFF, 1,
- 0x23, 2, 0xFC, 0x00,
- 0x29, 5, 0xFF, 0xAA, 0x55, 0x25, 0x00,
- 0xFF, 20,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x00,
- 0x29, 3, 0xB1, 0x68, 0x01,
- 0x29, 5, 0xB8, 0x01, 0x02, 0x02, 0x02,
- 0x23, 2, 0xB6, 0x11,
- 0x29, 3, 0xBB, 0x63, 0x63,
- 0x29, 3, 0xBC, 0x00, 0x00,
- 0x29, 6, 0xBD, 0x02, 0xBB, 0x11, 0x10, 0x00,
- 0x23, 2, 0xC8, 0x80,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x01,
- 0x29, 3, 0xB3, 0x28, 0x28,
- 0x29, 3, 0xB4, 0x14, 0x14,
- 0x29, 3, 0xB9, 0x44, 0x44,
- 0x29, 3, 0xBA, 0x24, 0x24,
- 0x29, 3, 0xBC, 0x70, 0x00,
- 0x29, 3, 0xBD, 0x70, 0x00,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x02,
- 0x23, 2, 0xEE, 0x03,
- 0x29, 17, 0xB0, 0x01, 0x04, 0x01, 0x08, 0x01, 0x11, 0x01, 0x19, 0x01, 0x21, 0x01, 0x30, 0x01, 0x3D, 0x01, 0x55,
- 0x29, 17, 0xB1, 0x01, 0x6B, 0x01, 0x94, 0x01, 0xB5, 0x01, 0xED, 0x02, 0x20, 0x02, 0x22, 0x02, 0x53, 0x02, 0x8F,
- 0x29, 17, 0xB2, 0x02, 0xB4, 0x02, 0xE5, 0x03, 0x03, 0x03, 0x30, 0x03, 0x51, 0x03, 0x76, 0x03, 0x96, 0x03, 0xB8,
- 0x29, 5, 0xB3, 0x03, 0xCF, 0x03, 0xD2,
- 0x29, 17, 0xB4, 0x00, 0x00, 0x00, 0x13, 0x00, 0x31, 0x00, 0x4B, 0x00, 0x61, 0x00, 0x87, 0x00, 0xA7, 0x00, 0xDB,
- 0x29, 17, 0xB5, 0x01, 0x04, 0x01, 0x43, 0x01, 0x76, 0x01, 0xC9, 0x02, 0x05, 0x02, 0x06, 0x02, 0x3F, 0x02, 0x7D,
- 0x29, 17, 0xB6, 0x02, 0xA3, 0x02, 0xD3, 0x02, 0xF6, 0x03, 0x23, 0x03, 0x44, 0x03, 0x6C, 0x03, 0x8A, 0x03, 0xAE,
- 0x29, 5, 0xB7, 0x03, 0xCF, 0x03, 0xD2,
- 0x29, 17, 0xB8, 0x00, 0x41, 0x00, 0x4A, 0x00, 0x5D, 0x00, 0x6D, 0x00, 0x7E, 0x00, 0x9A, 0x00, 0xB4, 0x00, 0xDF,
- 0x29, 17, 0xB9, 0x01, 0x04, 0x01, 0x43, 0x01, 0x74, 0x01, 0xC6, 0x02, 0x03, 0x02, 0x09, 0x02, 0x40, 0x02, 0x7E,
- 0x29, 17, 0xBA, 0x02, 0xA4, 0x02, 0xD6, 0x02, 0xF7, 0x03, 0x25, 0x03, 0x44, 0x03, 0x6C, 0x03, 0x88, 0x03, 0xA8,
- 0x29, 5, 0xBB, 0x03, 0xD0, 0x03, 0xD2,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x03,
- 0x29, 3, 0xB0, 0x00, 0x00,
- 0x29, 3, 0xB1, 0x00, 0x00,
- 0x29, 6, 0xB2, 0x05, 0x01, 0x55, 0x00, 0x1A,
- 0x29, 6, 0xB3, 0x05, 0x01, 0x55, 0x00, 0x1A,
- 0x29, 6, 0xBA, 0x53, 0x01, 0x55, 0x00, 0x3A,
- 0x23, 2, 0xC4, 0x60,
- 0x23, 2, 0xC5, 0x40,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x04,
- 0x29, 5, 0xB1, 0x03, 0x02, 0x05, 0x07,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x05,
- 0x29, 6, 0xBD, 0x01, 0x03, 0x00, 0x00, 0x03,
- 0x23, 2, 0xC0, 0x09,
- 0x23, 2, 0xC1, 0x07,
- 0x29, 3, 0xC8, 0x07, 0x38,
- 0x23, 2, 0xD0, 0x00,
- 0x23, 2, 0xE5, 0x03,
- 0x23, 2, 0xE6, 0x03,
- 0x23, 2, 0xE9, 0x03,
- 0x23, 2, 0xEA, 0x03,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x08, 0x06,
- 0x29, 3, 0xB0, 0x2D, 0x2D,
- 0x29, 3, 0xB1, 0x01, 0x01,
- 0x29, 3, 0xB2, 0x03, 0x03,
- 0x29, 3, 0xB3, 0x2E, 0x2E,
- 0x29, 3, 0xB4, 0x2E, 0x2D,
- 0x29, 3, 0xB5, 0x2D, 0x13,
- 0x29, 3, 0xB6, 0x13, 0x11,
- 0x29, 3, 0xB7, 0x11, 0x36,
- 0x29, 3, 0xB8, 0x36, 0x15,
- 0x29, 3, 0xB9, 0x15, 0x2E,
- 0x29, 3, 0xBA, 0x2E, 0x14,
- 0x29, 3, 0xBB, 0x14, 0x35,
- 0x29, 3, 0xBC, 0x35, 0x10,
- 0x29, 3, 0xBD, 0x10, 0x12,
- 0x29, 3, 0xBE, 0x12, 0x2D,
- 0x29, 3, 0xBF, 0x2D, 0x2E,
- 0x29, 3, 0xC0, 0x2E, 0x2E,
- 0x29, 3, 0xC1, 0x02, 0x02,
- 0x29, 3, 0xC2, 0x00, 0x00,
- 0x29, 3, 0xC3, 0x2D, 0x2D,
- 0x29, 3, 0xE5, 0x34, 0x34,
- 0x29, 3, 0xC4, 0x2E, 0x2E,
- 0x29, 3, 0xC5, 0x02, 0x02,
- 0x29, 3, 0xC6, 0x00, 0x00,
- 0x29, 3, 0xC7, 0x2D, 0x2D,
- 0x29, 3, 0xC8, 0x2E, 0x2D,
- 0x29, 3, 0xC9, 0x2D, 0x14,
- 0x29, 3, 0xCA, 0x14, 0x35,
- 0x29, 3, 0xCB, 0x35, 0x10,
- 0x29, 3, 0xCC, 0x10, 0x12,
- 0x29, 3, 0xCD, 0x12, 0x2E,
- 0x29, 3, 0xCE, 0x2E, 0x13,
- 0x29, 3, 0xCF, 0x13, 0x11,
- 0x29, 3, 0xD0, 0x11, 0x36,
- 0x29, 3, 0xD1, 0x36, 0x15,
- 0x29, 3, 0xD2, 0x15, 0x2D,
- 0x29, 3, 0xD3, 0x2D, 0x2E,
- 0x29, 3, 0xD4, 0x2D, 0x2D,
- 0x29, 3, 0xD5, 0x01, 0x01,
- 0x29, 3, 0xD6, 0x03, 0x03,
- 0x29, 3, 0xD7, 0x2E, 0x2E,
- 0x29, 3, 0xE6, 0x34, 0x34,
- 0x29, 6, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x29, 6, 0xD9, 0x00, 0x00, 0x00, 0x00, 0x00,
- 0x29, 6, 0xF0, 0x55, 0xAA, 0x52, 0x00, 0x00,
- 0x23, 2, 0x35, 0x00,
- 0x13, 1, 0x11,
- 0xFF, 120,
- 0x13, 1, 0x29,
-
- 0xFF, 0xFF,
-};
-
-static unsigned char ext_init_off_table_TV101WXM[] = {
- 0x05, 1, 0x28, /* display off */
- 0xFF, 10, /* delay 10ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xFF, 150, /* delay 150ms */
- 0xFF, 0xFF, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_G101B158[LCD_EXTERN_INIT_ON_MAX] = {
- 0xff, 120, /* delay */
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x00,
- 0x29, 3, 0xB1,0x68,0x01,
- 0x15, 2, 0xB5,0xC8,
- 0x29, 6, 0xBD,0x02,0xB0,0x10,0x10,0x00,
-
- 0x15, 2, 0xBC,0x05,
- 0x15, 2, 0xC7,0x00,
- 0x15, 2, 0xC8,0x80,
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x01,
- 0x29, 3, 0xB3,0x2D,0x2D,
- 0x29, 3, 0xB4,0x19,0x19,
- 0x15, 2, 0xB5,0x06,
- 0x29, 3, 0xB9,0x35,0x35,
- 0x29, 3, 0xBA,0x25,0x25,
- 0x29, 3, 0xBC,0x90,0x00,
- 0x29, 3, 0xBD,0x90,0x00,
-
- 0x15, 2, 0xC0,0x0C,
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x02,
- 0x15, 2, 0xEE,0x02,
-
- 0x29, 7, 0xB0,0x00,0x00,0x00,0x32,0x00,0x64,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xB0,0x00,0x83,0x00,0x9C,0x00,0xC3,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xB0,0x00,0xDF,0x01,0x0E,
-
- 0x29, 7, 0xB1,0x01,0x33,0x01,0x6C,0x01,0x99,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xB1,0x01,0xDF,0x02,0x18,0x02,0x1A,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xB1,0x02,0x4E,0x02,0x87,
-
- 0x29, 7, 0xB2,0x02,0xAC,0x02,0xDB,0x02,0xFC,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xB2,0x03,0x24,0x03,0x46,0x03,0x71,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xB2,0x03,0x8C,0x03,0xB1,
-
- 0x29, 5, 0xB3,0x03,0xED,0x03,0Xff,
-
- 0x29, 7, 0xBC,0x00,0x00,0x00,0x32,0x00,0x64,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xBC,0x00,0x83,0x00,0x9C,0x00,0xC3,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xBC,0x00,0xDF,0x01,0x0E,
-
- 0x29, 7, 0xBD,0x01,0x33,0x01,0x6C,0x01,0x99,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xBD,0x01,0xDF,0x02,0x18,0x02,0x1A,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xBD,0x02,0x4E,0x02,0x87,
-
- 0x29, 7, 0xBE,0x02,0xAC,0x02,0xDB,0x02,0xFC,
- 0x15, 2, 0x6F,0x06,
- 0x29, 7, 0xBE,0x03,0x24,0x03,0x46,0x03,0x71,
- 0x15, 2, 0x6F,0x0C,
- 0x29, 5, 0xBE,0x03,0x8C,0x03,0xB1,
-
- 0x29, 5, 0xBF,0x03,0xED,0x03,0xFF,
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x03,
- 0x29, 6, 0xB2,0x05,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xB6,0x05,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xB7,0x05,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xBA,0x57,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xBB,0x57,0x00,0x00,0x00,0x00,
- 0x29, 5, 0xC0,0x00,0x34,0x00,0x00,
- 0x29, 5, 0xC1,0x00,0x00,0x34,0x00,
- 0x15, 2, 0xC4,0x40,
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x04,
- 0x29, 4, 0xB1,0x03,0x02,0x05,
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x05,
- 0x29, 3, 0xB0,0x17,0x06,
- 0x29, 3, 0xB1,0x17,0x06,
- 0x29, 3, 0xB2,0x17,0x06,
- 0x29, 3, 0xB3,0x17,0x06,
- 0x29, 3, 0xB4,0x17,0x06,
- 0x15, 2, 0xBB,0x02,
- 0x29, 6, 0xBD,0x03,0x01,0x03,0x03,0x01,
- 0x15, 2, 0xC0,0x05,
-
- 0x15, 2, 0xC4,0x82,
- 0x15, 2, 0xC5,0xA2,
- 0x29, 3, 0xC8,0x03,0x30,
- 0x29, 3, 0xC9,0x03,0x31,
-
- 0x29, 4, 0xCC,0x00,0x00,0x3C,
- 0x29, 4, 0xCD,0x00,0x00,0x3C,
-
- 0x29, 6, 0xD1,0x00,0x05,0x07,0x00,0x00,
- 0x29, 6, 0xD2,0x00,0x25,0x09,0x00,0x00,
-
- 0x15, 2, 0xE5,0x06,
- 0x15, 2, 0xE6,0x06,
- 0x15, 2, 0xE7,0x06,
- 0x15, 2, 0xE8,0x06,
- 0x15, 2, 0xE9,0x06,
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x06,
- 0x29, 3, 0xB0,0x0A,0x2D,
- 0x29, 3, 0xB1,0x2D,0x08,
- 0x29, 3, 0xB2,0x2A,0x29,
- 0x29, 3, 0xB3,0x34,0x1A,
- 0x29, 3, 0xB4,0x18,0x16,
- 0x29, 3, 0xB5,0x14,0x12,
- 0x29, 3, 0xB6,0x10,0x00,
- 0x29, 3, 0xB7,0x34,0x34,
- 0x29, 3, 0xB8,0x32,0x34,
- 0x29, 3, 0xB9,0x34,0x34,
- 0x29, 3, 0xBA,0x34,0x34,
- 0x29, 3, 0xBB,0x34,0x34,
- 0x29, 3, 0xBC,0x34,0x34,
- 0x29, 3, 0xBD,0x01,0x11,
- 0x29, 3, 0xBE,0x13,0x15,
- 0x29, 3, 0xBF,0x17,0x19,
- 0x29, 3, 0xC0,0x1B,0x34,
- 0x29, 3, 0xC1,0x29,0x2A,
- 0x29, 3, 0xC2,0x09,0x2D,
- 0x29, 3, 0xC3,0x2D,0x0B,
- 0x29, 3, 0xC4,0x0B,0x2D,
- 0x29, 3, 0xC5,0x2D,0x01,
- 0x29, 3, 0xC6,0x2A,0x29,
- 0x29, 3, 0xC7,0x34,0x19,
- 0x29, 3, 0xC8,0x1B,0x11,
- 0x29, 3, 0xC9,0x13,0x15,
- 0x29, 3, 0xCA,0x17,0x09,
- 0x29, 3, 0xCB,0x34,0x34,
- 0x29, 3, 0xCC,0x34,0x34,
- 0x29, 3, 0xCD,0x34,0x34,
- 0x29, 3, 0xCE,0x34,0x34,
- 0x29, 3, 0xCF,0x34,0x34,
- 0x29, 3, 0xD0,0x34,0x34,
- 0x29, 3, 0xD1,0x08,0x16,
- 0x29, 3, 0xD2,0x14,0x12,
- 0x29, 3, 0xD3,0x10,0x1A,
- 0x29, 3, 0xD4,0x18,0x34,
- 0x29, 3, 0xD5,0x29,0x2A,
- 0x29, 3, 0xD6,0x00,0x2D,
- 0x29, 3, 0xD7,0x2D,0x0A,
-
- 0x29, 6, 0xD8,0x00,0x00,0x00,0x00,0x00,
- 0x29, 6, 0xD9,0x00,0x00,0x00,0x00,0x00,
-
- 0x29, 3, 0xE5,0x34,0x34,
- 0x29, 3, 0xE6,0x34,0x34,
-
- 0x15, 2, 0xE7,0x00,
- 0x29, 3, 0xE8,0x34,0x34,
- 0x29, 3, 0xE9,0x34,0x34,
- 0x15, 2, 0xEA,0x00,
-
-
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x00,0x00,
-
- 0x23, 2, 0x35,0x00,
-
-#if 1
- 0x13, 1, 0x11,
- 0xff, 150,
- 0x13, 1, 0x29,
-#else //bist mode
- 0xff, 150,
- 0x29, 6, 0xF0,0x55,0xAA,0x52,0x08,0x00,
- 0xff, 10,
- 0x29, 5, 0xEE,0x87,0x78,0x02,0x40,
- 0xff, 10,
- 0x29, 6, 0xEF,0x00,0x07,0xFF,0xFF,0x00,
-#endif
- 0xff, 20,
- 0xFF, 0xFF, /* ending flag */
-
-};
-
-static unsigned char ext_init_off_table_G101B158[] = {
- 0x05, 1, 0x28, /* display off */
- 0xFF, 10, /* delay 10ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xFF, 150, /* delay 150ms */
- 0xFF, 0xFF, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_TV101WXM_FT[LCD_EXTERN_INIT_ON_MAX] = {
- 0xFF, 120,
- 0x23, 2, 0xE0, 0x00,
- 0x23, 2, 0xE1, 0x93,
- 0x23, 2, 0xE2, 0x65,
- 0x23, 2, 0xE3, 0xF8,
- 0x23, 2, 0x80, 0x03,
- 0x23, 2, 0xE0, 0x01,
- 0x23, 2, 0x00, 0x00,
- 0x23, 2, 0x01, 0x6F,
- 0x23, 2, 0x17, 0x00,
- 0x23, 2, 0x18, 0xAF,
- 0x23, 2, 0x19, 0x01,
- 0x23, 2, 0x1A, 0x00,
- 0x23, 2, 0x1B, 0xAF,
- 0x23, 2, 0x1C, 0x01,
- 0x23, 2, 0x1F, 0x3E,
- 0x23, 2, 0x20, 0x28,
- 0x23, 2, 0x21, 0x28,
- 0x23, 2, 0x22, 0x7E,
- 0x23, 2, 0x35, 0x26,
- 0x23, 2, 0x37, 0x09,
- 0x23, 2, 0x38, 0x04,
- 0x23, 2, 0x39, 0x00,
- 0x23, 2, 0x3A, 0x01,
- 0x23, 2, 0x3C, 0x78,
- 0x23, 2, 0x3D, 0xFF,
- 0x23, 2, 0x3E, 0xFF,
- 0x23, 2, 0x3F, 0x7F,
- 0x23, 2, 0x40, 0x06,
- 0x23, 2, 0x41, 0xA0,
- 0x23, 2, 0x42, 0x81,
- 0x23, 2, 0x43, 0x08,
- 0x23, 2, 0x44, 0x0B,
- 0x23, 2, 0x45, 0x28,
- 0x23, 2, 0x55, 0x0F,
- 0x23, 2, 0x57, 0x69,
- 0x23, 2, 0x59, 0x0A,
- 0x23, 2, 0x5A, 0x28,
- 0x23, 2, 0x5B, 0x14,
- 0x23, 2, 0x5D, 0x7F,
- 0x23, 2, 0x5E, 0x6A,
- 0x23, 2, 0x5F, 0x5A,
- 0x23, 2, 0x60, 0x4E,
- 0x23, 2, 0x61, 0x4A,
- 0x23, 2, 0x62, 0x3A,
- 0x23, 2, 0x63, 0x3C,
- 0x23, 2, 0x64, 0x23,
- 0x23, 2, 0x65, 0x39,
- 0x23, 2, 0x66, 0x35,
- 0x23, 2, 0x67, 0x34,
- 0x23, 2, 0x68, 0x51,
- 0x23, 2, 0x69, 0x3E,
- 0x23, 2, 0x6A, 0x44,
- 0x23, 2, 0x6B, 0x34,
- 0x23, 2, 0x6C, 0x2E,
- 0x23, 2, 0x6D, 0x21,
- 0x23, 2, 0x6E, 0x0E,
- 0x23, 2, 0x6F, 0x00,
- 0x23, 2, 0x70, 0x7F,
- 0x23, 2, 0x71, 0x6A,
- 0x23, 2, 0x72, 0x5A,
- 0x23, 2, 0x73, 0x4E,
- 0x23, 2, 0x74, 0x4A,
- 0x23, 2, 0x75, 0x3A,
- 0x23, 2, 0x76, 0x3C,
- 0x23, 2, 0x77, 0x23,
- 0x23, 2, 0x78, 0x39,
- 0x23, 2, 0x79, 0x35,
- 0x23, 2, 0x7A, 0x34,
- 0x23, 2, 0x7B, 0x51,
- 0x23, 2, 0x7C, 0x3E,
- 0x23, 2, 0x7D, 0x44,
- 0x23, 2, 0x7E, 0x34,
- 0x23, 2, 0x7F, 0x2E,
- 0x23, 2, 0x80, 0x21,
- 0x23, 2, 0x81, 0x0E,
- 0x23, 2, 0x82, 0x00,
- 0x23, 2, 0xE0, 0x02,
- 0x23, 2, 0x00, 0x1E,
- 0x23, 2, 0x01, 0x1E,
- 0x23, 2, 0x02, 0x41,
- 0x23, 2, 0x03, 0x41,
- 0x23, 2, 0x04, 0x43,
- 0x23, 2, 0x05, 0x43,
- 0x23, 2, 0x06, 0x1F,
- 0x23, 2, 0x07, 0x1F,
- 0x23, 2, 0x08, 0x35,
- 0x23, 2, 0x09, 0x1F,
- 0x23, 2, 0x0A, 0x15,
- 0x23, 2, 0x0B, 0x15,
- 0x23, 2, 0x0C, 0x1F,
- 0x23, 2, 0x0D, 0x47,
- 0x23, 2, 0x0E, 0x47,
- 0x23, 2, 0x0F, 0x45,
- 0x23, 2, 0x10, 0x45,
- 0x23, 2, 0x11, 0x4B,
- 0x23, 2, 0x12, 0x4B,
- 0x23, 2, 0x13, 0x49,
- 0x23, 2, 0x14, 0x49,
- 0x23, 2, 0x15, 0x1F,
- 0x23, 2, 0x16, 0x1E,
- 0x23, 2, 0x17, 0x1E,
- 0x23, 2, 0x18, 0x40,
- 0x23, 2, 0x19, 0x40,
- 0x23, 2, 0x1A, 0x42,
- 0x23, 2, 0x1B, 0x42,
- 0x23, 2, 0x1C, 0x1F,
- 0x23, 2, 0x1D, 0x1F,
- 0x23, 2, 0x1E, 0x35,
- 0x23, 2, 0x1F, 0x1F,
- 0x23, 2, 0x20, 0x15,
- 0x23, 2, 0x21, 0x15,
- 0x23, 2, 0x22, 0x1F,
- 0x23, 2, 0x23, 0x46,
- 0x23, 2, 0x24, 0x46,
- 0x23, 2, 0x25, 0x44,
- 0x23, 2, 0x26, 0x44,
- 0x23, 2, 0x27, 0x4A,
- 0x23, 2, 0x28, 0x4A,
- 0x23, 2, 0x29, 0x48,
- 0x23, 2, 0x2A, 0x48,
- 0x23, 2, 0x2B, 0x1F,
- 0x23, 2, 0x58, 0x40,
- 0x23, 2, 0x5B, 0x30,
- 0x23, 2, 0x5C, 0x0F,
- 0x23, 2, 0x5D, 0x30,
- 0x23, 2, 0x5E, 0x01,
- 0x23, 2, 0x5F, 0x02,
- 0x23, 2, 0x63, 0x14,
- 0x23, 2, 0x64, 0x6A,
- 0x23, 2, 0x67, 0x73,
- 0x23, 2, 0x68, 0x11,
- 0x23, 2, 0x69, 0x14,
- 0x23, 2, 0x6A, 0x6A,
- 0x23, 2, 0x6B, 0x08,
- 0x23, 2, 0x6C, 0x00,
- 0x23, 2, 0x6D, 0x00,
- 0x23, 2, 0x6E, 0x00,
- 0x23, 2, 0x6F, 0x88,
- 0x23, 2, 0x77, 0xDD,
- 0x23, 2, 0x79, 0x0E,
- 0x23, 2, 0x7A, 0x0F,
- 0x23, 2, 0x7D, 0x14,
- 0x23, 2, 0x7E, 0x82,
- 0x23, 2, 0xE0, 0x04,
- 0x23, 2, 0x09, 0x11,
- 0x23, 2, 0x0E, 0x48,
- 0x23, 2, 0x2B, 0x2B,
- 0x23, 2, 0x2D, 0x03,
- 0x23, 2, 0x2E, 0x44,
- 0x23, 2, 0xE0, 0x00,
- 0x23, 2, 0xE6, 0x02,
- 0x23, 2, 0xE7, 0x0C,
- 0x05, 1, 0x11,
- 0xFF, 100,
- 0x23, 2, 0xE0, 0x03,
- 0x23, 2, 0x2B, 0x01,
- 0x23, 2, 0x2C, 0x00,
- 0x23, 2, 0x30, 0x03,
- 0x23, 2, 0x31, 0xFC,
- 0x23, 2, 0x32, 0x03,
- 0x23, 2, 0x33, 0xF8,
- 0x23, 2, 0x34, 0x03,
- 0x23, 2, 0x35, 0xF0,
- 0x23, 2, 0x36, 0x03,
- 0x23, 2, 0x37, 0xE8,
- 0x23, 2, 0x38, 0x03,
- 0x23, 2, 0x39, 0xE0,
- 0x23, 2, 0x3A, 0x03,
- 0x23, 2, 0x3B, 0xD0,
- 0x23, 2, 0x3C, 0x03,
- 0x23, 2, 0x3D, 0xC0,
- 0x23, 2, 0x3E, 0x03,
- 0x23, 2, 0x3F, 0xA0,
- 0x23, 2, 0x40, 0x03,
- 0x23, 2, 0x41, 0x80,
- 0x23, 2, 0x42, 0x03,
- 0x23, 2, 0x43, 0x40,
- 0x23, 2, 0x44, 0x03,
- 0x23, 2, 0x45, 0x00,
- 0x23, 2, 0x46, 0x02,
- 0x23, 2, 0x47, 0x80,
- 0x23, 2, 0x48, 0x02,
- 0x23, 2, 0x49, 0x00,
- 0x23, 2, 0x4A, 0x01,
- 0x23, 2, 0x4B, 0xFC,
- 0x23, 2, 0x4C, 0x01,
- 0x23, 2, 0x4D, 0x7C,
- 0x23, 2, 0x4E, 0x00,
- 0x23, 2, 0x4F, 0xFC,
- 0x23, 2, 0x50, 0x00,
- 0x23, 2, 0x51, 0xBC,
- 0x23, 2, 0x52, 0x00,
- 0x23, 2, 0x53, 0x7C,
- 0x23, 2, 0x54, 0x00,
- 0x23, 2, 0x55, 0x5C,
- 0x23, 2, 0x56, 0x00,
- 0x23, 2, 0x57, 0x3C,
- 0x23, 2, 0x58, 0x00,
- 0x23, 2, 0x59, 0x2C,
- 0x23, 2, 0x5A, 0x00,
- 0x23, 2, 0x5B, 0x1C,
- 0x23, 2, 0x5C, 0x00,
- 0x23, 2, 0x5D, 0x14,
- 0x23, 2, 0x5E, 0x00,
- 0x23, 2, 0x5F, 0x0C,
- 0x23, 2, 0x60, 0x00,
- 0x23, 2, 0x61, 0x04,
- 0x23, 2, 0x62, 0x00,
- 0x23, 2, 0x63, 0x00,
- 0x23, 2, 0x64, 0x03,
- 0x23, 2, 0x65, 0xC9,
- 0x23, 2, 0x66, 0x03,
- 0x23, 2, 0x67, 0xC6,
- 0x23, 2, 0x68, 0x03,
- 0x23, 2, 0x69, 0xBE,
- 0x23, 2, 0x6A, 0x03,
- 0x23, 2, 0x6B, 0xB7,
- 0x23, 2, 0x6C, 0x03,
- 0x23, 2, 0x6D, 0xB1,
- 0x23, 2, 0x6E, 0x03,
- 0x23, 2, 0x6F, 0xA3,
- 0x23, 2, 0x70, 0x03,
- 0x23, 2, 0x71, 0x96,
- 0x23, 2, 0x72, 0x03,
- 0x23, 2, 0x73, 0x79,
- 0x23, 2, 0x74, 0x03,
- 0x23, 2, 0x75, 0x5D,
- 0x23, 2, 0x76, 0x03,
- 0x23, 2, 0x77, 0x26,
- 0x23, 2, 0x78, 0x02,
- 0x23, 2, 0x79, 0xE9,
- 0x23, 2, 0x7A, 0x02,
- 0x23, 2, 0x7B, 0x6E,
- 0x23, 2, 0x7C, 0x01,
- 0x23, 2, 0x7D, 0xF3,
- 0x23, 2, 0x7E, 0x01,
- 0x23, 2, 0x7F, 0xEF,
- 0x23, 2, 0x80, 0x01,
- 0x23, 2, 0x81, 0x73,
- 0x23, 2, 0x82, 0x00,
- 0x23, 2, 0x83, 0xF5,
- 0x23, 2, 0x84, 0x00,
- 0x23, 2, 0x85, 0xB4,
- 0x23, 2, 0x86, 0x00,
- 0x23, 2, 0x87, 0x79,
- 0x23, 2, 0x88, 0x00,
- 0x23, 2, 0x89, 0x5D,
- 0x23, 2, 0x8A, 0x00,
- 0x23, 2, 0x8B, 0x3C,
- 0x23, 2, 0x8C, 0x00,
- 0x23, 2, 0x8D, 0x2B,
- 0x23, 2, 0x8E, 0x00,
- 0x23, 2, 0x8F, 0x1C,
- 0x23, 2, 0x90, 0x00,
- 0x23, 2, 0x91, 0x14,
- 0x23, 2, 0x92, 0x00,
- 0x23, 2, 0x93, 0x0C,
- 0x23, 2, 0x94, 0x00,
- 0x23, 2, 0x95, 0x04,
- 0x23, 2, 0x96, 0x00,
- 0x23, 2, 0x97, 0x00,
- 0x23, 2, 0xE0, 0x00,
- 0x05, 1, 0x29,
- 0xFF, 0xFF,
-};
-static unsigned char ext_init_off_table_TV101WXM_FT[LCD_EXTERN_INIT_OFF_MAX] = {
- 0XFF, 5, /* delay 5ms */
- 0x05, 1, 0x28, /* display off */
- 0xFF, 50, /* delay 50ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xFF, 150, /* delay 150ms */
- 0xFF, 0xFF, /* ending flag */
-};
-
-static unsigned char ext_init_on_table_G101B158_FT[LCD_EXTERN_INIT_ON_MAX] = {
- 0x23, 2, 0xE0, 0x00,
- 0x23, 2, 0xE1, 0x93,
- 0x23, 2, 0xE2, 0x65,
- 0x23, 2, 0xE3, 0xF8,
- 0x23, 2, 0x80, 0x03,
-
- 0x23, 2, 0xE0, 0x01,
- 0x23, 2, 0x00, 0x00,
- 0x23, 2, 0x01, 0x5D,
- 0x23, 2, 0x03, 0x00,
- 0x23, 2, 0x04, 0x64,
-
- 0x23, 2, 0x17, 0x00,
- 0x23, 2, 0x18, 0xC7,//BF=4.5V,c7=4.6v, D7=4.8V
- 0x23, 2, 0x19, 0x01,//0.3V
- 0x23, 2, 0x1A, 0x00,
- 0x23, 2, 0x1B, 0xC7,
- 0x23, 2, 0x1C, 0x01,
-
- 0x23, 2, 0x1F, 0x70, //VGH_REG=16.2V
- 0x23, 2, 0x20, 0x2D, //VGL_REG=-12V
- 0x23, 2, 0x21, 0x2D, //VGL_REG2=-12V
- 0x23, 2, 0x22, 0x7E,
-
- 0x23, 2, 0x35, 0x28, //SAP
-
- 0x23, 2, 0x37, 0x19, //SS=1,BGR=1
-
- 0x23, 2, 0x38, 0x05, //JDT=101 zigzag inversion
- 0x23, 2, 0x39, 0x00,
- 0x23, 2, 0x3A, 0x01,
- 0x23, 2, 0x3C, 0x7C, //SET EQ3 for TE_H
- 0x23, 2, 0x3D, 0xFF, //SET CHGEN_ON, modify 20140806
- 0x23, 2, 0x3E, 0xFF, //SET CHGEN_OFF, modify 20140806
- 0x23, 2, 0x3F, 0x7F, //SET CHGEN_OFF2, modify 20140806
-
-
- 0x23, 2, 0x40, 0x06, //RSO=
- 0x23, 2, 0x41, 0xA0, //LN=640->1280 line
- 0x23, 2, 0x43, 0x14, //VFP=20
- 0x23, 2, 0x44, 0x17, //VBP=24
- 0x23, 2, 0x45, 0x2C, //HBP=44
-
- 0x23, 2, 0x55, 0x0F, //DCDCM=1111
- 0x23, 2, 0x57, 0x68,
- 0x23, 2, 0x59, 0x0A, //VCL = -2.5V
- 0x23, 2, 0x5A, 0x2E, //VGH = 16.2V
- 0x23, 2, 0x5B, 0x1A, //VGL = -12V
- 0x23, 2, 0x5C, 0x15, //pump clk
-
-
- 0x23, 2, 0x5D, 0x7F,
- 0x23, 2, 0x5E, 0x61,
- 0x23, 2, 0x5F, 0x50,
- 0x23, 2, 0x60, 0x43,
- 0x23, 2, 0x61, 0x3E,
- 0x23, 2, 0x62, 0x2E,
- 0x23, 2, 0x63, 0x33,
- 0x23, 2, 0x64, 0x1C,
- 0x23, 2, 0x65, 0x34,
- 0x23, 2, 0x66, 0x33,
- 0x23, 2, 0x67, 0x32,
- 0x23, 2, 0x68, 0x50,
- 0x23, 2, 0x69, 0x3E,
- 0x23, 2, 0x6A, 0x46,
- 0x23, 2, 0x6B, 0x37,
- 0x23, 2, 0x6C, 0x32,
- 0x23, 2, 0x6D, 0x24,
- 0x23, 2, 0x6E, 0x12,
- 0x23, 2, 0x6F, 0x02,
- 0x23, 2, 0x70, 0x7F,
- 0x23, 2, 0x71, 0x61,
- 0x23, 2, 0x72, 0x50,
- 0x23, 2, 0x73, 0x43,
- 0x23, 2, 0x74, 0x3E,
- 0x23, 2, 0x75, 0x2E,
- 0x23, 2, 0x76, 0x33,
- 0x23, 2, 0x77, 0x1C,
- 0x23, 2, 0x78, 0x34,
- 0x23, 2, 0x79, 0x33,
- 0x23, 2, 0x7A, 0x32,
- 0x23, 2, 0x7B, 0x50,
- 0x23, 2, 0x7C, 0x3E,
- 0x23, 2, 0x7D, 0x46,
- 0x23, 2, 0x7E, 0x37,
- 0x23, 2, 0x7F, 0x32,
- 0x23, 2, 0x80, 0x24,
- 0x23, 2, 0x81, 0x12,
- 0x23, 2, 0x82, 0x02,
-
-
- 0x23, 2, 0xE0, 0x02,
-
- 0x23, 2, 0x00, 0x52,//RESET_EVEN
- 0x23, 2, 0x01, 0x55,//VSSG_EVEN
- 0x23, 2, 0x02, 0x55,//VSSG_EVEN
- 0x23, 2, 0x03, 0x50,//STV2_ODD
- 0x23, 2, 0x04, 0x77,//VDD2_ODD
- 0x23, 2, 0x05, 0x57,//VDD1_ODD
- 0x23, 2, 0x06, 0x55,//x
- 0x23, 2, 0x07, 0x4E,//CK11
- 0x23, 2, 0x08, 0x4C,//CK9
- 0x23, 2, 0x09, 0x5F,//x
- 0x23, 2, 0x0A, 0x4A,//CK7
- 0x23, 2, 0x0B, 0x48,//CK5
- 0x23, 2, 0x0C, 0x55,//x
- 0x23, 2, 0x0D, 0x46,//CK3
- 0x23, 2, 0x0E, 0x44,//CK1
- 0x23, 2, 0x0F, 0x40,//STV1_ODD
- 0x23, 2, 0x10, 0x55,//x
- 0x23, 2, 0x11, 0x55,//x
- 0x23, 2, 0x12, 0x55,//x
- 0x23, 2, 0x13, 0x55,//x
- 0x23, 2, 0x14, 0x55,//x
- 0x23, 2, 0x15, 0x55,//x
-
- 0x23, 2, 0x16, 0x53,//RESET__EVEN
- 0x23, 2, 0x17, 0x55,//VSSG_EVEN
- 0x23, 2, 0x18, 0x55,//VSSG_EVEN
- 0x23, 2, 0x19, 0x51,//STV2_EVEN
- 0x23, 2, 0x1A, 0x77,//VDD2_EVEN
- 0x23, 2, 0x1B, 0x57,//VDD1_EVEN
- 0x23, 2, 0x1C, 0x55,//x
- 0x23, 2, 0x1D, 0x4F,//CK12
- 0x23, 2, 0x1E, 0x4D,//CK10
- 0x23, 2, 0x1F, 0x5F,//x
- 0x23, 2, 0x20, 0x4B,//CK8
- 0x23, 2, 0x21, 0x49,//CK6
- 0x23, 2, 0x22, 0x55,//x
- 0x23, 2, 0x23, 0x47,//CK4
- 0x23, 2, 0x24, 0x45,//CK2
- 0x23, 2, 0x25, 0x41,//STV1_EVEN
- 0x23, 2, 0x26, 0x55,//x
- 0x23, 2, 0x27, 0x55,//x
- 0x23, 2, 0x28, 0x55,//x
- 0x23, 2, 0x29, 0x55,//x
- 0x23, 2, 0x2A, 0x55,//x
- 0x23, 2, 0x2B, 0x55,//x
-
- 0x23, 2, 0x2C, 0x13,//RESET_EVEN
- 0x23, 2, 0x2D, 0x15,//VSSG_EVEN
- 0x23, 2, 0x2E, 0x15,//VSSG_EVEN
- 0x23, 2, 0x2F, 0x01,//STV2_ODD
- 0x23, 2, 0x30, 0x37,//VDD2_ODD
- 0x23, 2, 0x31, 0x17,//VDD1_ODD
- 0x23, 2, 0x32, 0x15,//x
- 0x23, 2, 0x33, 0x0D,//CK11
- 0x23, 2, 0x34, 0x0F,//CK9
- 0x23, 2, 0x35, 0x15,//x
- 0x23, 2, 0x36, 0x05,//CK7
- 0x23, 2, 0x37, 0x07,//CK5
- 0x23, 2, 0x38, 0x15,//x
- 0x23, 2, 0x39, 0x09,//CK3
- 0x23, 2, 0x3A, 0x0B,//CK1
- 0x23, 2, 0x3B, 0x11,//STV1_ODD
- 0x23, 2, 0x3C, 0x15,//x
- 0x23, 2, 0x3D, 0x15,//x
- 0x23, 2, 0x3E, 0x15,//x
- 0x23, 2, 0x3F, 0x15,//x
- 0x23, 2, 0x40, 0x15,//x
- 0x23, 2, 0x41, 0x15,//x
-
- 0x23, 2, 0x42, 0x12,//RESET__EVEN
- 0x23, 2, 0x43, 0x15,//VSSG_EVEN
- 0x23, 2, 0x44, 0x15,//VSSG_EVEN
- 0x23, 2, 0x45, 0x00,//STV2_EVEN
- 0x23, 2, 0x46, 0x37,//VDD2_EVEN
- 0x23, 2, 0x47, 0x17,//VDD1_EVEN
- 0x23, 2, 0x48, 0x15,//x
- 0x23, 2, 0x49, 0x0C,//CK12
- 0x23, 2, 0x4A, 0x0E,//CK10
- 0x23, 2, 0x4B, 0x15,//x
- 0x23, 2, 0x4C, 0x04,//CK8
- 0x23, 2, 0x4D, 0x06,//CK6
- 0x23, 2, 0x4E, 0x15,//x
- 0x23, 2, 0x4F, 0x08,//CK4
- 0x23, 2, 0x50, 0x0A,//CK2
- 0x23, 2, 0x51, 0x10,//STV1_EVEN
- 0x23, 2, 0x52, 0x15,//x
- 0x23, 2, 0x53, 0x15,//x
- 0x23, 2, 0x54, 0x15,//x
- 0x23, 2, 0x55, 0x15,//x
- 0x23, 2, 0x56, 0x15,//x
- 0x23, 2, 0x57, 0x15,//x
-
- 0x23, 2, 0x58, 0x40,
- 0x23, 2, 0x5B, 0x10,
- 0x23, 2, 0x5C, 0x12,//STV_S0
- 0x23, 2, 0x5D, 0x40,
- 0x23, 2, 0x5E, 0x00,
- 0x23, 2, 0x5F, 0x00,
- 0x23, 2, 0x60, 0x40,//ETV_W
- 0x23, 2, 0x61, 0x03,
- 0x23, 2, 0x62, 0x04,
- 0x23, 2, 0x63, 0x6C,//CKV_ON
- 0x23, 2, 0x64, 0x6C,//CKV_OFF
- 0x23, 2, 0x65, 0x75,
- 0x23, 2, 0x66, 0x14,//ETV_S0
- 0x23, 2, 0x67, 0xB4, //ckv_num/ckv_w
- 0x23, 2, 0x68, 0x14, //CKV_S0
- 0x23, 2, 0x69, 0x6C,//CKV_ON
- 0x23, 2, 0x6A, 0x6C,//CKV_OFF
- 0x23, 2, 0x6B, 0x0C, //dummy
- 0x23, 2, 0x6D, 0x04,//GGND1
- 0x23, 2, 0x6E, 0x00,//GGND2
- 0x23, 2, 0x6F, 0x88,
- 0x23, 2, 0x75, 0xBB,//FLM_EN
- 0x23, 2, 0x76, 0x02,
- 0x23, 2, 0x77, 0x00,
- 0x23, 2, 0x78, 0x02,//FLM_OFF
-
- 0x23, 2, 0xE0, 0x03,
- 0x23, 2, 0xAF, 0x20,//Adjust CABC
-
-
- 0x23, 2, 0xE0, 0x04,
- 0x23, 2, 0x09, 0x11,
- 0x23, 2, 0x0E, 0x48, //Source EQ option
- 0x23, 2, 0x2B, 0x2B,
- 0x23, 2, 0x2D, 0x03,//defult 0x01
- 0x23, 2, 0x2E, 0x44,
- 0x23, 2, 0x41, 0xFF,//Adjust CABC
-
- 0x23, 2, 0xE0, 0x05,
- 0x23, 2, 0x12, 0x72,//VCI GAS detect voltage
-
- 0x23, 2, 0xE0, 0x00,
- 0x23, 2, 0xE6, 0x02,//WD_Timer
- 0x23, 2, 0xE7, 0x0C,//WD_Timer
-
- 0x23, 2, 0x53, 0x2C,//CABC dimming
-
- 0x05, 1, 0x11, // SLPOUT
- 0xff, 120,
-
- 0x23, 2, 0xE0, 0x03,
- 0x23, 2, 0x2B, 0x01,//DGC_EN
- 0xff, 10,
- 0x23, 2, 0x2C, 0x01,//DGC_SEL
-
- 0x23, 2, 0x30, 0x03,
- 0x23, 2, 0x31, 0xDE,
- 0x23, 2, 0x32, 0x03,
- 0x23, 2, 0x33, 0xDA,
- 0x23, 2, 0x34, 0x03,
- 0x23, 2, 0x35, 0xD1,
- 0x23, 2, 0x36, 0x03,
- 0x23, 2, 0x37, 0xC9,
- 0x23, 2, 0x38, 0x03,
- 0x23, 2, 0x39, 0xC1,
- 0x23, 2, 0x3A, 0x03,
- 0x23, 2, 0x3B, 0xB3,
- 0x23, 2, 0x3C, 0x03,
- 0x23, 2, 0x3D, 0xA4,
- 0x23, 2, 0x3E, 0x03,
- 0x23, 2, 0x3F, 0x83,
- 0x23, 2, 0x40, 0x03,
- 0x23, 2, 0x41, 0x62,
- 0x23, 2, 0x42, 0x03,
- 0x23, 2, 0x43, 0x23,
- 0x23, 2, 0x44, 0x02,
- 0x23, 2, 0x45, 0xE4,
- 0x23, 2, 0x46, 0x02,
- 0x23, 2, 0x47, 0x67,
- 0x23, 2, 0x48, 0x01,
- 0x23, 2, 0x49, 0xEC,
- 0x23, 2, 0x4A, 0x01,
- 0x23, 2, 0x4B, 0xE8,
- 0x23, 2, 0x4C, 0x01,
- 0x23, 2, 0x4D, 0x6D,
- 0x23, 2, 0x4E, 0x00,
- 0x23, 2, 0x4F, 0xF2,
- 0x23, 2, 0x50, 0x00,
- 0x23, 2, 0x51, 0xB2,
- 0x23, 2, 0x52, 0x00,
- 0x23, 2, 0x53, 0x76,
- 0x23, 2, 0x54, 0x00,
- 0x23, 2, 0x55, 0x58,
- 0x23, 2, 0x56, 0x00,
- 0x23, 2, 0x57, 0x39,
- 0x23, 2, 0x58, 0x00,
- 0x23, 2, 0x59, 0x2A,
- 0x23, 2, 0x5A, 0x00,
- 0x23, 2, 0x5B, 0x1B,
- 0x23, 2, 0x5C, 0x00,
- 0x23, 2, 0x5D, 0x13,
- 0x23, 2, 0x5E, 0x00,
- 0x23, 2, 0x5F, 0x0B,
- 0x23, 2, 0x60, 0x00,
- 0x23, 2, 0x61, 0x04,
- 0x23, 2, 0x62, 0x00,
- 0x23, 2, 0x63, 0x00,
-
- 0x23, 2, 0x64, 0x03,
- 0x23, 2, 0x65, 0xE7,
- 0x23, 2, 0x66, 0x03,
- 0x23, 2, 0x67, 0xE4,
- 0x23, 2, 0x68, 0x03,
- 0x23, 2, 0x69, 0xDD,
- 0x23, 2, 0x6A, 0x03,
- 0x23, 2, 0x6B, 0xD5,
- 0x23, 2, 0x6C, 0x03,
- 0x23, 2, 0x6D, 0xCE,
- 0x23, 2, 0x6E, 0x03,
- 0x23, 2, 0x6F, 0xBF,
- 0x23, 2, 0x70, 0x03,
- 0x23, 2, 0x71, 0xB2,
- 0x23, 2, 0x72, 0x03,
- 0x23, 2, 0x73, 0x93,
- 0x23, 2, 0x74, 0x03,
- 0x23, 2, 0x75, 0x71,
- 0x23, 2, 0x76, 0x03,
- 0x23, 2, 0x77, 0x33,
- 0x23, 2, 0x78, 0x02,
- 0x23, 2, 0x79, 0xF4,
- 0x23, 2, 0x7A, 0x02,
- 0x23, 2, 0x7B, 0x75,
- 0x23, 2, 0x7C, 0x01,
- 0x23, 2, 0x7D, 0xF7,
- 0x23, 2, 0x7E, 0x01,
- 0x23, 2, 0x7F, 0xF3,
- 0x23, 2, 0x80, 0x01,
- 0x23, 2, 0x81, 0x75,
- 0x23, 2, 0x82, 0x00,
- 0x23, 2, 0x83, 0xF7,
- 0x23, 2, 0x84, 0x00,
- 0x23, 2, 0x85, 0xB6,
- 0x23, 2, 0x86, 0x00,
- 0x23, 2, 0x87, 0x7C,
- 0x23, 2, 0x88, 0x00,
- 0x23, 2, 0x89, 0x5E,
- 0x23, 2, 0x8A, 0x00,
- 0x23, 2, 0x8B, 0x3F,
- 0x23, 2, 0x8C, 0x00,
- 0x23, 2, 0x8D, 0x2E,
- 0x23, 2, 0x8E, 0x00,
- 0x23, 2, 0x8F, 0x1D,
- 0x23, 2, 0x90, 0x00,
- 0x23, 2, 0x91, 0x15,
- 0x23, 2, 0x92, 0x00,
- 0x23, 2, 0x93, 0x0C,
- 0x23, 2, 0x94, 0x00,
- 0x23, 2, 0x95, 0x04,
- 0x23, 2, 0x96, 0x00,
- 0x23, 2, 0x97, 0x00,
-
- 0x23, 2, 0xE0, 0x00,
-
- 0x05, 1, 0x29, // DSPON
- 0xff, 5,
- 0xff, 0xff,
-};
-
-static unsigned char ext_init_off_table_G101B158_FT[LCD_EXTERN_INIT_OFF_MAX] = {
- 0XFF, 5, /* delay 5ms */
- 0x05, 1, 0x28, /* display off */
- 0xFF, 50, /* delay 50ms */
- 0x05, 1, 0x10, /* sleep in */
- 0xFF, 150, /* delay 150ms */
- 0xFF, 0xFF, /* ending flag */
-};
-
-static struct lcd_extern_config_s ext_config[LCD_EXTERN_NUM_MAX] = {
- {
- .index = 0,
- .name = "ext_default",
- .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 0, /* 0=disable, 1=enable */
- .i2c_addr = 0x1c, /* 7bit i2c address */
- .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for invalid */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- { /* P070ACB_FT */
- .index = 1,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_P070ACB_FT,
- .table_init_on_cnt = sizeof(ext_init_on_table_P070ACB_FT),
- .table_init_off = ext_init_off_table_P070ACB_FT,
- .table_init_off_cnt = sizeof(ext_init_off_table_P070ACB_FT),
- },
- { /* TL050FHV02CT */
- .index = 2,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_TL050FHV02CT,
- .table_init_on_cnt = sizeof(ext_init_on_table_TL050FHV02CT),
- .table_init_off = ext_init_off_table_TL050FHV02CT,
- .table_init_off_cnt = sizeof(ext_init_off_table_TL050FHV02CT),
- },
- { /* boe_nvtk_10 */
- .index = 3,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_TV101WXM,
- .table_init_on_cnt = sizeof(ext_init_on_table_TV101WXM),
- .table_init_off = ext_init_off_table_TV101WXM,
- .table_init_off_cnt = sizeof(ext_init_off_table_TV101WXM),
- },
- { /* inx_nvtk_10 */
- .index = 4,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_G101B158,
- .table_init_on_cnt = sizeof(ext_init_on_table_G101B158),
- .table_init_off = ext_init_off_table_G101B158,
- .table_init_off_cnt = sizeof(ext_init_off_table_G101B158),
- },
- { /* boe_fiti_10 */
- .index = 5,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_TV101WXM_FT,
- .table_init_on_cnt = sizeof(ext_init_on_table_TV101WXM_FT),
- .table_init_off = ext_init_off_table_TV101WXM_FT,
- .table_init_off_cnt = sizeof(ext_init_off_table_TV101WXM_FT),
- },
- { /* inx_fiti_10 */
- .index = 6,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table_G101B158_FT,
- .table_init_on_cnt = sizeof(ext_init_on_table_G101B158_FT),
- .table_init_off = ext_init_off_table_G101B158_FT,
- .table_init_off_cnt = sizeof(ext_init_off_table_G101B158_FT),
- },
- {
- .index = LCD_EXTERN_INDEX_INVALID,
- },
-};
-
-#endif
-
diff --git a/board/amlogic/sm1_elaine_p0/pwm_table.c b/board/amlogic/sm1_elaine_p0/pwm_table.c
deleted file mode 100755
index 18dc638..0000000
--- a/board/amlogic/sm1_elaine_p0/pwm_table.c
+++ /dev/null
@@ -1,71 +0,0 @@
-#include <common.h>
-
-const int pwm_cal_voltage_table[][2] = {
- { 0x1c0000, 860},
- { 0x1b0001, 870},
- { 0x1a0002, 880},
- { 0x190003, 890},
- { 0x180004, 900},
- { 0x170005, 910},
- { 0x160006, 920},
- { 0x150007, 930},
- { 0x140008, 940},
- { 0x130009, 950},
- { 0x12000a, 960},
- { 0x11000b, 970},
- { 0x10000c, 980},
- { 0x0f000d, 990},
- { 0x0e000e, 1000},
- { 0x0d000f, 1010},
- { 0x0c0010, 1020},
- { 0x0b0011, 1030},
- { 0x0a0012, 1040},
- { 0x090013, 1050},
- { 0x080014, 1060},
- { 0x070015, 1070},
- { 0x060016, 1080},
- { 0x050017, 1090},
- { 0x040018, 1100},
- { 0x030019, 1110},
- { 0x02001a, 1120},
- { 0x01001b, 1130},
- { 0x00001c, 1140}
-};
-const int pwm_cal_voltage_table_ee[][2] = {
- { 0x1c0000, 810},
- { 0x1b0001, 820},
- { 0x1a0002, 830},
- { 0x190003, 840},
- { 0x180004, 850},
- { 0x170005, 860},
- { 0x160006, 870},
- { 0x150007, 880},
- { 0x140008, 890},
- { 0x130009, 900},
- { 0x12000a, 910},
- { 0x11000b, 920},
- { 0x10000c, 930},
- { 0x0f000d, 940},
- { 0x0e000e, 950},
- { 0x0d000f, 960},
- { 0x0c0010, 970},
- { 0x0b0011, 980},
- { 0x0a0012, 990},
- { 0x090013, 1000},
- { 0x080014, 1010},
- { 0x070015, 1020},
- { 0x060016, 1030},
- { 0x050017, 1040},
- { 0x040018, 1050},
- { 0x030019, 1060},
- { 0x02001a, 1070},
- { 0x01001b, 1080},
- { 0x00001c, 1090}
-};
-
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
-int pwm_cal_voltage_table_size = ARRAY_SIZE(pwm_cal_voltage_table);
-int pwm_cal_voltage_table_ee_size = ARRAY_SIZE(pwm_cal_voltage_table_ee);
-
-
diff --git a/board/amlogic/sm1_elaine_p0/sm1_elaine_p0.c b/board/amlogic/sm1_elaine_p0/sm1_elaine_p0.c
deleted file mode 100755
index 79a7082..0000000
--- a/board/amlogic/sm1_elaine_p0/sm1_elaine_p0.c
+++ /dev/null
@@ -1,1056 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_p0/sm1_elaine_p0.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <malloc.h>
-#include <errno.h>
-#include <environment.h>
-#include <fdt_support.h>
-#include <linux/libfdt.h>
-#include <asm/arch/cpu_id.h>
-#ifdef CONFIG_SYS_I2C_MESON
-#include <i2c.h>
-#include <dt-bindings/i2c/meson-i2c.h>
-#endif
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/pinctrl_init.h>
-#ifdef CONFIG_AML_VPU
-#include <amlogic/media/vpu/vpu.h>
-#endif
-#ifdef CONFIG_AML_VPP
-#include <amlogic/media/vpp/vpp.h>
-#endif
-#ifdef CONFIG_AML_V2_FACTORY_BURN
-#include <amlogic/aml_v2_burning.h>
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
-#ifdef CONFIG_AML_HDMITX
-#include <amlogic/media/vout/hdmitx.h>
-#endif
-#ifdef CONFIG_AML_LCD
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#endif
-#include <asm/arch/eth_setup.h>
-#include <phy.h>
-#include <linux/mtd/partitions.h>
-#include <linux/sizes.h>
-#include <asm-generic/gpio.h>
-#include <dm.h>
-#ifdef CONFIG_AML_SPIFC
-#include <amlogic/spifc.h>
-#endif
-#ifdef CONFIG_AML_SPICC
-#include <amlogic/spicc.h>
-#endif
-#include <asm/armv8/mmu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-
-int do_get_ddictype (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-#if defined(CONFIG_NAND_FTS) || defined(CONFIG_MMC_FTS)
-#if defined(CONFIG_NAND_FTS)
- extern bool amlnf_is_inited(void);
- if (!amlnf_is_inited()) {
-#endif
-#if defined(CONFIG_MMC_FTS)
- extern bool amlmmc_is_inited(void);
- if (!amlmmc_is_inited()) {
-#endif
- env_set("ddic_type", "NOVATEK");
- return 0;
- }
- flash_ts_init();
-
- const char *fts_key = "ddic.type";
-
- char fts_value[256] = { 0 };
- flash_ts_get(fts_key, fts_value, sizeof(fts_value));
-
- printf("FTS read: ddic.type -> %s\n", fts_value);
-
- if (strncmp(fts_value, "FITI", sizeof(fts_value)) == 0) {
- env_set("ddic_type", "FITI");
- } else {
- env_set("ddic_type", "NOVATEK");
- }
-#endif
- return 0;
-}
-
-U_BOOT_CMD(
- get_ddictype, 1, 0, do_get_ddictype,
- "get ddic type",
- " This command will get and setenv 'ddic_type'\n"
-);
-
-int do_check_fdr_for_backlight_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-#if defined(CONFIG_NAND_FTS) || defined(CONFIG_MMC_FTS)
-#if defined(CONFIG_NAND_FTS)
- extern bool amlnf_is_inited(void);
- if(!amlnf_is_inited()) {
-#endif
-
-#if defined(CONFIG_MMC_FTS)
- extern bool amlmmc_is_inited(void);
- if (!amlmmc_is_inited()) {
-#endif
-
- return 0;
- }
-
- flash_ts_init();
-
- static const char *fts_key = "bootloader.recovery";
- static const char *fdr = "--wipe_data";
- static const int fdr_len = sizeof(fdr) - 1;
- int i;
-
- char fts_value[256] = { 0 };
- flash_ts_get(fts_key, fts_value, sizeof(fts_value));
- int fts_len = strnlen(fts_value, sizeof(fts_value));
- for (i = 0; i <= fts_len - fdr_len; i++) {
- if (0 == strncmp(fts_value+i, fdr, fdr_len)) {
- printf("Reset persistent brightness.\n");
- writel(0, AO_RTI_STICKY_REG2);
- break;
- }
- }
-#endif
-
- return 0;
-}
-
-U_BOOT_CMD(
- check_fdr_for_backlight_brightness, 1, 0, do_check_fdr_for_backlight_brightness,
- "check FDR for backlight brightness",
- " This command will clear backlight brightness level stored in the sticky register when doing FDR\n"
-);
-
-int serial_set_pin_port(unsigned long port_base)
-{
- //UART in "Always On Module"
- //GPIOAO_0==tx,GPIOAO_1==rx
- //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
- return 0;
-}
-
-//SOC_VDDCPU_DVFS0
-//#define VDD_CPU_DVFS0_EN_1 GPIOEE(GPIOZ_13)
-#define VDD_CPU_DVFS0_EN_1_NAME "GPIOZ_13"
-
-//SOC_VDDEE_DVFS0
-//#define VDD_GPU_DVFS0_EN_1 GPIOEE(GPIOA_13)
-#define VDD_GPU_DVFS0_EN_1_NAME "GPIOA_13"
-
-//SOC_VDDEE_DVFS1
-//#define VDD_GPU_DVFS1_EN_1 GPIOEE(GPIOZ_0)
-#define VDD_GPU_DVFS1_EN_1_NAME "GPIOZ_0"
-
-/* setting gpio output/input, and setting High/low level */
-static void gpio_func_set(bool enable, const char* gpio_name, int direction)
-{
- int ret;
- struct gpio_desc gpio_set_desc;
-
- ret = dm_gpio_lookup_name(gpio_name, &gpio_set_desc);
- if (ret) {
- printf("%s: not found\n", gpio_name);
- return;
- }
-
- ret = dm_gpio_request(&gpio_set_desc, gpio_name);
- if (ret && ret != -EBUSY) {
- printf("gpio: requesting pin %s failed\n", gpio_name);
- return;
- }
-
- ret = dm_gpio_set_dir_flags(&gpio_set_desc, direction);
- if (ret) {
- printf("set direction failed\n");
- return;
- }
-
- if ( direction == GPIOD_IS_OUT)
- dm_gpio_set_value(&gpio_set_desc, enable ? 1 : 0);
-}
-static void CPU_GPU_Voltage_init(void)
-{
- int ret;
- // setting GPIOZ_13 output & High
- gpio_func_set(1, VDD_CPU_DVFS0_EN_1_NAME, GPIOD_IS_OUT);
-
- //GPU , setting GPIOA_13 output & low
- gpio_func_set(0, VDD_GPU_DVFS0_EN_1_NAME, GPIOD_IS_OUT);
-
- // setting GPIOZ_0 output & low
- gpio_func_set(1, VDD_GPU_DVFS1_EN_1_NAME, GPIOD_IS_OUT);
-}
-
-// Disable GPIOZ_2, GPIOZ_3, GPIOZ_7, GPIOZ_8, GPIOC_7, GPIOH_8's pull-up
-// so the mute switch and HW id can be read.
-static void gpio_disable_pull(void)
-{
- int ret;
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 2)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 7)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 8)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 3)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG1);
- writel(ret & (~(1 << 7)), PAD_PULL_UP_EN_REG1);
-
- ret = readl(PAD_PULL_UP_EN_REG3);
- writel(ret & (~(1 << 8)), PAD_PULL_UP_EN_REG3);
-}
-
-int do_get_elaine_hw_id(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- unsigned int hw_id = 0, ret = 0;
- char hw_id_str[8] = {0}; // eg: 0x0A
-
- // Reading from highest bit to lowest bit
- // HW_ID_4: GPIOH_8
- ret = readl(P_PREG_PAD_GPIO3_I);
- hw_id |= (ret & (1<<8)) >> 8;
- hw_id = hw_id << 1;
-
- // HW_ID_3: GPIOC_7
- ret = readl(P_PREG_PAD_GPIO1_I);
- hw_id |= (ret & (1<<7)) >> 7;
- hw_id = hw_id << 1;
-
- // HW_ID_2: GPIOZ_3
- ret = readl(P_PREG_PAD_GPIO4_I);
- hw_id |= (ret & (1<<3)) >> 3;
- hw_id = hw_id << 1;
-
- // HW_ID_1: GPIOZ_8
- ret = readl(P_PREG_PAD_GPIO4_I);
- hw_id |= (ret & (1<<8)) >> 8;
- hw_id = hw_id << 1;
-
- // HW_ID_0: GPIOZ_7
- ret = readl(P_PREG_PAD_GPIO4_I);
- hw_id |= (ret & (1<<7)) >> 7;
-
- snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id);
- env_set("hw_id", hw_id_str);
- return 0;
-}
-
-U_BOOT_CMD(
- get_elaine_hw_id, 1, 0, do_get_elaine_hw_id,
- "get elaine's HW_ID and env_set 'hw_id'\n",
- "get_elaine_hw_id"
-);
-
-
-#define USB_HOST_ENABLE_PIN_NAME "GPIOZ_11"
-static void enable_usb_host(bool enable)
-{
- int ret;
- struct gpio_desc usb_host_desc;
-
- ret = dm_gpio_lookup_name(USB_HOST_ENABLE_PIN_NAME, &usb_host_desc);
- if (ret) {
- printf("%s: not found\n", USB_HOST_ENABLE_PIN_NAME);
- return;
- }
-
- ret = dm_gpio_request(&usb_host_desc, USB_HOST_ENABLE_PIN_NAME);
- if (ret && ret != -EBUSY) {
- printf("gpio: requesting pin %s failed\n", USB_HOST_ENABLE_PIN_NAME);
- return;
- }
- ret = dm_gpio_set_dir_flags(&usb_host_desc, GPIOD_IS_OUT);
- if (ret) {
- printf("set direction failed\n");
- return;
- }
-
- dm_gpio_set_value(&usb_host_desc, enable ? 1 : 0);
-}
-
-//SOC_BL_ENABLE
-//#define BL_ENABLE_PIN GPIOEE(GPIOA_10)
-#define BL_ENABLE_PIN_NAME "GPIOA_10"
-
-static void enable_backlight(bool enable)
-{
- // setting GPIOA_10 output & High
- gpio_func_set(enable, BL_ENABLE_PIN_NAME, GPIOD_IS_OUT);
-}
-
-int dram_init(void)
-{
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-/* secondary_boot_func
- * this function should be write with asm, here, is is only for compiling pass
- * */
-void secondary_boot_func(void)
-{
-}
-
-#if CONFIG_AML_SD_EMMC
-#include <mmc.h>
-#include <asm/arch/sd_emmc.h>
-static int sd_emmc_init(unsigned port)
-{
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
- //todo add card detect
- /* check card detect */
- clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
- setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
- setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
- setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
- break;
- case SDIO_PORT_C:
- //enable pull up
- //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
- break;
- default:
- break;
- }
-
- return cpu_sd_emmc_init(port);
-}
-
-extern unsigned sd_debug_board_1bit_flag;
-
-static void sd_emmc_pwr_prepare(unsigned port)
-{
- cpu_sd_emmc_pwr_prepare(port);
-}
-
-static void sd_emmc_pwr_on(unsigned port)
-{
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
-// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
-// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
- /// @todo NOT FINISH
- break;
- case SDIO_PORT_C:
- break;
- default:
- break;
- }
- return;
-}
-static void sd_emmc_pwr_off(unsigned port)
-{
- /// @todo NOT FINISH
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
-// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
-// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
- break;
- case SDIO_PORT_C:
- break;
- default:
- break;
- }
- return;
-}
-
-// #define CONFIG_TSD 1
-static void board_mmc_register(unsigned port)
-{
- struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
- if (aml_priv == NULL)
- return;
-
- aml_priv->sd_emmc_init=sd_emmc_init;
- aml_priv->sd_emmc_detect=sd_emmc_detect;
- aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
- aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
- aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
- aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
-
- if (NULL == aml_priv->desc_buf)
- printf(" desc_buf Dma alloc Fail!\n");
- else
- printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
-
- sd_emmc_register(aml_priv);
-}
-int board_mmc_init(bd_t *bis)
-{
-#ifdef CONFIG_VLSI_EMULATOR
- //board_mmc_register(SDIO_PORT_A);
-#else
- //board_mmc_register(SDIO_PORT_B);
-#endif
- board_mmc_register(SDIO_PORT_B);
- board_mmc_register(SDIO_PORT_C);
-// board_mmc_register(SDIO_PORT_B1);
- return 0;
-}
-#endif
-
-/* Skip the first line and parse one uint
- * Return negative if not found */
-int parse_calibration_file_string(const char *str)
-{
- if (str == NULL)
- return -EINVAL;
-
- str = strchr(str, '\n');
- if (str == NULL)
- return -EINVAL;
- ++str;
-
- return simple_strtoul(str, NULL, 10);
-}
-
-/* If zero, this value has not been set and the default brightness should not be
- * overwritten. To store zero, store a non-zero value with its bottom 12 bits
- * all zero, like 0x1000.
- */
-int get_persistent_brightness(void)
-{
- u32 brightness_sticky_val = readl(AO_RTI_STICKY_REG2);
- if (brightness_sticky_val != 0)
- return (brightness_sticky_val & 0x0fff) >> 1;
- return -1;
-}
-
-int do_configure_backlight(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
-#ifdef CONFIG_SYS_I2C_MESON
- int ret, i, attempt;
- const int retries = 3;
- char *addr_cal;
- int calibrated_current, persistent_brightness;
-
- /* Values to write:
- * [0]: Brightness register control only, backlight enabled
- * [1-2]: Standby disabled, 20mA MAX_CURRENT, CURRENT scale 1/2
- * [3]: Enable undervoltage protection at 5.2 V, "disable" backlight
- * (i2c only), disable set resistors
- * [4]: 9.6kHz PWM rate, 3 phase drivers
- * [5]: EN_DRV3, EN_DRV2, boost inductor current limit = 1.6 A
- * [6]: VBOOST_MAX = 25 V, JUMP_EN = 0
- * [7]: STEP_UP = 105 mV, STEP_DN = 105 mV, LED_FAULT_TH = 3V,
- * LED_COMP_HYST = DRIVER_HEADROOM + 750 mV
- * [8-9]: 12-bit brightness (default: 100%)
- * Important: Write brightness last to apply current calibration */
- const __u8 addrs[] = {0x01, 0xa0, 0xa1, 0xa2, 0xa5, 0xa7, 0xa9, 0xae,
- 0x10, 0x11};
- __u8 values[] = {0x85, 0xff, 0x37, 0x30, 0x54, 0xf4, 0x60, 0x09, 0xff,
- 0x0f};
- const int n_bytes = sizeof(values)/sizeof(values[0]);
- struct udevice *bl_devp = NULL;
-
- if (argc > 2) {
- printf("%s: Too many args: %d\n", __func__, argc);
- return CMD_RET_USAGE;
- }
-
- if (argc == 2) {
- addr_cal = (char *)simple_strtoul(argv[1], NULL, 16);
- calibrated_current = parse_calibration_file_string(addr_cal);
- if (calibrated_current >= 0 && calibrated_current <= 4095) {
- /* CURRENT_LSB */
- values[1] = 0xff & calibrated_current;
- /* CURRENT_MSB */
- values[2] = (values[2] & 0xf0) |
- (0x0f & (calibrated_current >> 8));
- }
- }
-
- // Apply persistent brightness if found
- persistent_brightness = get_persistent_brightness();
- if (persistent_brightness >= 0) {
- pr_info("Applying persistent_brightness=%d\n", persistent_brightness);
- /* Get LSB and MSB */
- values[n_bytes - 2] = persistent_brightness & 0xff;
- values[n_bytes - 1] = persistent_brightness >> 8 & 0x0f;
- } else {
- pr_info("Persistent_brightness not set\n");
- }
-
- enable_backlight(true);
-
- ret = i2c_get_chip_for_busnum(MESON_I2C_M3, 0X2c, 1, &bl_devp);
- if (ret) {
- printf("%s(%d):i2c get bus fail!\n", __func__, __LINE__);
- return -1;
- }
-
- for (i = 0; i < n_bytes; ++i) {
- for (attempt = 0; attempt < retries; ++attempt) {
- ret = dm_i2c_write(bl_devp, addrs[i], &values[i], 1);
- if (ret)
- printf("%s: Attempt=%d to write byte=0x%02x to reg=0x%02x of backlight failed\n",
- __func__, attempt, values[i], addrs[i]);
- else
- break;
- }
- }
-
- return ret;
-#else
- enable_backlight(true);
-
- return 0;
-#endif /* CONFIG_SYS_I2C_MESON */
-}
-
-U_BOOT_CMD(
- configure_backlight, 2, 0, do_configure_backlight,
- "configures the lp8556 backlight",
- "Usage: configure_backlight [calibration_string_addr]\n"\
- " Sets up required parameters of the backlight.\n"\
- " Default calibration is 100%.\n"\
- " calibration_str_addr (optional):\n"\
- " Address of calibration file string to parse.\n"
-);
-
-#ifdef CONFIG_AML_LCD
-/* Parses one line of the gamma calibration file. */
-/* Returns true on success. */
-#define GAMMA_SIZE (256)
-bool parse_gamma_string(const char *str, uint16_t *table)
-{
- char buf[4] = {'\0'};
- int i;
-
- for (i = 0; i < GAMMA_SIZE; ++i) {
- strncpy(buf, &str[3 * i], 3);
- table[i] = simple_strtol(buf, NULL, 16);
- }
-
- return true;
-}
-
-/* Check header then parse RGB gamma tables */
-/* Returns negative value on error */
-int parse_gamma_calibration_file_string(const char *str, u16 *r, u16 *g, u16 *b)
-{
- static const char supported_header_prefix[] = "Gamma Calibration 1.";
- static const int length = sizeof(supported_header_prefix) - 1;
- char *tables[3] = {r, g, b};
- const char *start, *end;
- int i;
-
- if (!str)
- return -EINVAL;
-
- // Check header prefix - only care about major version.
- if (strncmp(str, supported_header_prefix, length) != 0) {
- printf("Unknown gamma header: \"%.*s\"\n", length, str);
- return -EINVAL;
- }
-
- // Parse all three tables
- end = strchr(str, '\n');
- for (i = 0; i < 3; ++i) {
- start = end + 1;
- end = strchr(start, '\n');
-
- if ((end - start) / 3 != GAMMA_SIZE) {
- printf("Gamma table has invalid length.\n");
- return -EINVAL;
- }
- if (!parse_gamma_string(start, tables[i])) {
- printf("Could not parse gamma table %d.\n", i);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-#endif // CONFIG_AML_LCD
-
-int do_configure_gamma(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
-#ifdef CONFIG_AML_LCD
- static const int N_CHAN = 3;
- char *addr_cal;
- u16 gamma_tables[N_CHAN][GAMMA_SIZE];
- int i, j;
-
- if (argc == 1) {
- // Set to default
- for (i = 0; i < N_CHAN; ++i) {
- for (j = 0; j < GAMMA_SIZE; ++j)
- gamma_tables[i][j] = j << 2; /* 10-bit */
- }
- } else if (argc == 2) {
- // Load from passed file string
- addr_cal = (char *)simple_strtoul(argv[1], NULL, 16);
- if (parse_gamma_calibration_file_string(addr_cal,
- &gamma_tables[0],
- &gamma_tables[1],
- &gamma_tables[2]) != 0)
- return -EINVAL; // Error logged
- } else {
- return CMD_RET_USAGE;
- }
-
- vpp_set_rgb_gamma_table(&gamma_tables[0], &gamma_tables[1],
- &gamma_tables[2]);
-#endif // CONFIG_AML_LCD
- return 0;
-}
-
-U_BOOT_CMD(configure_gamma, 2, 0, do_configure_gamma,
- "configures gamma the gamma tables with the provided calibration\n",
- "Usage: configure_gamma [calibration_string_addr]\n"\
- " Applies the provided calibration file.\n"\
- " If a file is not provided, sets tables to default.\n"\
- " calibration_str_addr (optional):\n"\
- " Address of the calibration file string to parse.\n"
-);
-
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
-int board_early_init_f(void){
- /*add board early init function here*/
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
-#include <asm/arch/usb-v2.h>
-#include <asm/arch/gpio.h>
-#define CONFIG_GXL_USB_U2_PORT_NUM 2
-
-#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
-#define CONFIG_GXL_USB_U3_PORT_NUM 1
-#else
-#define CONFIG_GXL_USB_U3_PORT_NUM 0
-#endif
-
-static void gpio_set_vbus_power(char is_power_on)
-{
- int ret;
-
- ret = gpio_request(CONFIG_USB_GPIO_PWR,
- CONFIG_USB_GPIO_PWR_NAME);
- if (ret && ret != -EBUSY) {
- printf("gpio: requesting pin %u failed\n",
- CONFIG_USB_GPIO_PWR);
- return;
- }
-
- if (is_power_on) {
- gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
- } else {
- gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
- }
-}
-
-struct amlogic_usb_config g_usb_config_GXL_skt={
- CONFIG_GXL_XHCI_BASE,
- USB_ID_MODE_HARDWARE,
- gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
- CONFIG_GXL_USB_PHY2_BASE,
- CONFIG_GXL_USB_PHY3_BASE,
- CONFIG_GXL_USB_U2_PORT_NUM,
- CONFIG_GXL_USB_U3_PORT_NUM,
- .usb_phy2_pll_base_addr = {
- CONFIG_USB_PHY_20,
- CONFIG_USB_PHY_21,
- }
-};
-
-#endif /*CONFIG_USB_XHCI_AMLOGIC*/
-
-#ifdef CONFIG_AML_HDMITX20
-static void hdmi_tx_set_hdmi_5v(void)
-{
-}
-#endif
-
-/*
- * mtd nand partition table, only care the size!
- * offset will be calculated by nand driver.
- */
-#ifdef CONFIG_AML_MTD
-static struct mtd_partition normal_partition_info[] = {
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- /* MUST NOT CHANGE this part unless u know what you are doing!
- * inherent parition for descrete bootloader to store fip
- * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
- * name must be same with TPL_PART_NAME
- */
- {
- .name = "tpl",
- .offset = 0,
- .size = 0,
- },
-#endif
- {
- .name = "fts",
- .offset = 0,
- .size = 1*SZ_1M,
- },
- {
- .name = "factory",
- .offset = 0,
- .size = 8*SZ_1M,
- },
- {
- .name = "recovery",
- .offset = 0,
- .size = 16*SZ_1M,
- },
- {
- .name = "boot",
- .offset = 0,
- .size = 16*SZ_1M,
- },
- {
- .name = "system",
- .offset = 0,
- .size = 220*SZ_1M,
- },
- /* last partition get the rest capacity */
- {
- .name = "cache",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-struct mtd_partition *get_aml_mtd_partition(void)
-{
- return normal_partition_info;
-}
-int get_aml_partition_count(void)
-{
- return ARRAY_SIZE(normal_partition_info);
-}
-#endif /* CONFIG_AML_MTD */
-
-#ifdef CONFIG_AML_SPIFC
-/*
- * BOOT_3: NOR_HOLDn:reg0[15:12]=3
- * BOOT_4: NOR_D:reg0[19:16]=3
- * BOOT_5: NOR_Q:reg0[23:20]=3
- * BOOT_6: NOR_C:reg0[27:24]=3
- * BOOT_7: NOR_WPn:reg0[31:28]=3
- * BOOT_14: NOR_CS:reg1[27:24]=3
- */
-#define SPIFC_NUM_CS 1
-static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
-
-static int spifc_pinctrl_enable(void *pinctrl, bool enable)
-{
- unsigned int val;
-
- val = readl(P_PERIPHS_PIN_MUX_0);
- val &= ~(0xfffff << 12);
- if (enable)
- val |= 0x33333 << 12;
- writel(val, P_PERIPHS_PIN_MUX_0);
-
- val = readl(P_PERIPHS_PIN_MUX_1);
- val &= ~(0xf << 24);
- writel(val, P_PERIPHS_PIN_MUX_1);
- return 0;
-}
-
-#endif /* CONFIG_AML_SPIFC */
-
-extern void aml_pwm_cal_init(int mode);
-
-int board_init(void)
-{
- printf("board init\n");
-
- /*in kernel P_RESET1_LEVEL has been clear,
- * uboot need set these bits about usb,
- * otherwise the usb has problem.
- */
- *(volatile uint32_t *)P_RESET1_LEVEL |= (3 << 16);
- //CPU_GPU_Voltage_init();
- enable_backlight(false);
- //Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
- //As NOT NEED other board init If USB BOOT MODE
-#ifdef CONFIG_AML_V2_FACTORY_BURN
- if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
- aml_try_factory_usb_burning(0, gd->bd);
- }
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
-
- pinctrl_devices_active(PIN_CONTROLLER_NUM);
-#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
- board_usb_pll_disable(&g_usb_config_GXL_skt);
- board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
-#endif /*CONFIG_USB_XHCI_AMLOGIC*/
-
- /* TODO(b/110040521): This is the earliest the backlight can be started,
- * but the LCD is not running yet. */
-
-#ifdef CONFIG_AML_NAND
- extern int amlnf_init(unsigned char flag);
- amlnf_init(0);
-#endif
- gpio_disable_pull();
-
- // Enable USB Host for elaine p0
- enable_usb_host(true);
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- printf("board late init\n");
- run_command("mmc dev 1", 0);
- run_command("run detect_panel", 0);
-#ifdef CONFIG_AML_VPU
- vpu_probe();
-#endif
-
-#ifdef CONFIG_AML_VPP
- vpp_init();
-#endif
-
-#ifdef CONFIG_AML_HDMITX
- hdmi_tx_init();
-#endif
-#ifdef CONFIG_AML_CVBS
- run_command("cvbs init", 0);
-#endif
-#ifdef CONFIG_AML_LCD
- lcd_probe();
-#endif
-
-#ifdef CONFIG_AML_V2_FACTORY_BURN
- if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
- aml_try_factory_usb_burning(1, gd->bd);
- aml_try_factory_sdcard_burning(0, gd->bd);
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
- return 0;
-}
-#endif
-
-#ifdef CONFIG_AML_TINY_USBTOOL
-int usb_get_update_result(void)
-{
- unsigned long upgrade_step;
- upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
- printf("upgrade_step = %d\n", (int)upgrade_step);
- if (upgrade_step == 1)
- {
- run_command("defenv", 1);
- run_command("env_set upgrade_step 2", 1);
- run_command("saveenv", 1);
- return 0;
- }
- else
- {
- return -1;
- }
-}
-#endif
-
-phys_size_t get_effective_memsize(void)
-{
- // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
-#if defined(CONFIG_SYS_MEM_TOP_HIDE)
- return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
-#else
- return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
-#endif
-}
-
-#ifdef CONFIG_MULTI_DTB
-int checkhw(char * name)
-{
- /*
- * read board hw id
- * set and select the dts according the board hw id.
- *
- * hwid = 1 p321 v1
- * hwid = 2 p321 v2
- */
- unsigned int hwid = 1;
- char loc_name[64] = {0};
-
- /* read hwid */
- hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
-
- printf("checkhw: hwid = %d\n", hwid);
-
-
- switch (hwid) {
- case 1:
- strcpy(loc_name, "txl_p321_v1\0");
- break;
- case 2:
- strcpy(loc_name, "txl_p321_v2\0");
- break;
- default:
- strcpy(loc_name, "txl_p321_v1");
- break;
- }
- strcpy(name, loc_name);
- env_set("aml_dt", loc_name);
- return 0;
-}
-#endif
-
-/* workaround for VDDEE issue */
-/* VCCK PWM table */
-#define VCCK_VAL_REG_800 0x00150007
-#define VCCK_VAL_REG_810 0x00140008
-#define VCCK_VAL_REG_820 0x00130009
-#define VCCK_VAL_REG_830 0x0012000a
-#define VCCK_VAL_REG_840 0x0011000b
-#define VCCK_VAL_REG_850 0x0010000c
-#define VCCK_VAL_REG_860 0x000f000d
-#define VCCK_VAL_REG_870 0x000e000e
-#define VCCK_VAL_REG_880 0x000d000f
-#define VCCK_VAL_REG_890 0x000c0010
-#define VCCK_VAL_REG_900 0x000b0011
-#define VCCK_VAL_REG_910 0x000a0012
-#define VCCK_VAL_REG_920 0x00090013
-#define VCCK_VAL_REG_930 0x00080014
-#define VCCK_VAL_REG_940 0x00070015
-#define VCCK_VAL_REG_950 0x00060016
-#define VCCK_VAL_REG_960 0x00050017
-#define VCCK_VAL_REG_970 0x00040018
-#define VCCK_VAL_REG_980 0x00030019
-#define VCCK_VAL_REG_990 0x0002001a
-#define VCCK_VAL_REG_1000 0x0001001b
-#define VCCK_VAL_REG_1010 0x0000001c
-#define VCCK_VAL_REG_DEFAULT 0x00500008
-
-/* VDDEE PWM table */
-#define VDDEE_VAL_REG_800 0x0010000c
-#define VDDEE_VAL_REG_810 0x000f000d
-#define VDDEE_VAL_REG_820 0x000e000e
-#define VDDEE_VAL_REG_830 0x000d000f
-#define VDDEE_VAL_REG_840 0x000c0010
-#define VDDEE_VAL_REG_850 0x000b0011
-#define VDDEE_VAL_REG_860 0x000a0012
-#define VDDEE_VAL_REG_870 0x00090013
-#define VDDEE_VAL_REG_880 0x00080014
-#define VDDEE_VAL_REG_890 0x00070015
-#define VDDEE_VAL_REG_900 0x00060016
-#define VDDEE_VAL_REG_910 0x00050017
-#define VDDEE_VAL_REG_920 0x00040018
-#define VDDEE_VAL_REG_930 0x00030019
-#define VDDEE_VAL_REG_940 0x0002001a
-#define VDDEE_VAL_REG_950 0x0001001b
-#define VDDEE_VAL_REG_960 0x0000001c
-#define VDDEE_VAL_REG_DEFAULT 0x00500008
-
-void reset_misc(void)
-{
- unsigned int value;
-
- /* adjust VDDCPU to Hiz value step by step */
- writel(VCCK_VAL_REG_830, AO_PWM_PWM_D);
- udelay(1);
- writel(VCCK_VAL_REG_860, AO_PWM_PWM_D);
- udelay(1);
-
- /* GPIOE_0 & GPIOE_1 to gpio pin */
- value = readl(AO_RTI_PINMUX_REG1);
- value &= ~(0xff << 16);
- writel(value, AO_RTI_PINMUX_REG1);
-
- /* disable pwm_ao_b - VDDEE */
- value = readl(AO_PWM_MISC_REG_AB);
- value &= ~((0x1 << 1) | (0x1 << 23));
- writel(value, AO_PWM_MISC_REG_AB);
- writel(VDDEE_VAL_REG_DEFAULT, AO_PWM_PWM_B);
-
- /* disable pwm_ao_d - VDDCPU_B*/
- value = readl(AO_PWM_MISC_REG_CD);
- value &= ~((0x1 << 1) | (0x1 << 23));
- writel(value, AO_PWM_MISC_REG_CD);
- writel(VCCK_VAL_REG_DEFAULT, AO_PWM_PWM_D);
-}
-
-static struct mm_region bd_mem_map[] = {
- {
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = bd_mem_map;
-
-void board_nand_init(void) {
- printf("board_nand_init\n");
- return;
-}
-
-int print_cpuinfo(void) {
- printf("print_cpuinfo\n");
- return 0;
-}
-
-int mach_cpu_init(void) {
- printf("mach_cpu_init\n");
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- /* eg: bl31/32 rsv */
- return 0;
-}
diff --git a/board/amlogic/sm1_elaine_p0/zircon.c b/board/amlogic/sm1_elaine_p0/zircon.c
deleted file mode 100644
index 8e6888f..0000000
--- a/board/amlogic/sm1_elaine_p0/zircon.c
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * Copyright (c) 2018 The Fuchsia Authors
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common.h>
-#include <linux/mtd/partitions.h>
-#include <nand.h>
-#include <part.h>
-#include <emmc_storage.h>
-#include <zircon/zircon.h>
-
-#define PDEV_VID_GOOGLE 3
-#define PDEV_PID_ASTRO 3
-
-#define NVRAM_LENGTH (8 * 1024)
-
-const char* BOOTLOADER_VERSION = "zircon-bootloader=0.10";
-
-static const zbi_cpu_config_t cpu_config = {
- .cluster_count = 1,
- .clusters = {
- {
- .cpu_count = 4,
- },
- },
-};
-
-static const zbi_mem_range_t mem_config[] = {
- {
- .type = ZBI_MEM_RANGE_RAM,
- .length = 0x60000000, // 1.5 GB
- },
- {
- .type = ZBI_MEM_RANGE_PERIPHERAL,
- .paddr = 0xf5800000,
- .length = 0x0a800000,
- },
- // secmon_reserved:linux,secmon
- {
- .type = ZBI_MEM_RANGE_RESERVED,
- .paddr = 0x05000000,
- .length = 0x2400000,
- },
- // logo_reserved:linux,meson-fb
- {
- .type = ZBI_MEM_RANGE_RESERVED,
- .paddr = 0x5f800000,
- .length = 0x800000,
- },
-};
-
-static const dcfg_simple_t uart_driver = {
- .mmio_phys = 0xff803000,
- .irq = 225,
-};
-
-static const dcfg_arm_gicv2_driver_t gicv2_driver = {
- .mmio_phys = 0xffc00000,
- .gicd_offset = 0x1000,
- .gicc_offset = 0x2000,
- .gich_offset = 0x4000,
- .gicv_offset = 0x6000,
- .ipi_base = 5,
-};
-
-static const dcfg_arm_psci_driver_t psci_driver = {
- .use_hvc = false,
- .reboot_args = { 1, 0, 0 },
- .reboot_bootloader_args = { 4, 0, 0 },
- .reboot_recovery_args = { 2, 0, 0 },
-};
-
-static const dcfg_arm_generic_timer_driver_t timer_driver = {
- .irq_phys = 30,
-};
-
-static const zbi_platform_id_t platform_id = {
- .vid = PDEV_VID_GOOGLE,
- .pid = PDEV_PID_ASTRO,
- .board_name = "astro",
-};
-
-enum {
- PART_TPL,
- PART_FTS,
- PART_FACTORY,
- PART_ZIRCON_B,
- PART_ZIRCON_A,
- PART_ZIRCON_R,
- PART_FVM,
- PART_SYS_CONFIG,
- PART_MIGRATION,
- PART_COUNT,
-};
-
-#define RECOVERY_SIZE (16 * 1024 * 1024)
-#define SYS_CONFIG_SIZE (1 * 1024 * 1024)
-#define MIGRATION_SIZE (3 * 1024 * 1024)
-
-static zbi_partition_map_t partition_map = {
- // .block_count filled in below
- // .block_size filled in below
- .guid = {},
- .partition_count = PART_COUNT,
- .partitions = {
- {
- .type_guid = GUID_BOOTLOADER_VALUE,
- .name = "tpl",
- },
- {
- .name = "fts",
- },
- {
- .name = "factory",
- },
- {
- .type_guid = GUID_ZIRCON_R_VALUE,
- .name = "zircon-r",
- },
- {
- .type_guid = GUID_ZIRCON_A_VALUE,
- .name = "zircon-a",
- },
- {
- .type_guid = GUID_ZIRCON_B_VALUE,
- .name = "zircon-b",
- },
- {
- .type_guid = GUID_FVM_VALUE,
- .name = "fvm",
- },
- {
- .type_guid = GUID_SYS_CONFIG_VALUE,
- .name = "sys-config",
- },
- {
- .name = "migration",
- },
- },
-};
-
-extern struct mtd_partition *get_aml_mtd_partition(void);
-extern int get_aml_partition_count(void);
-
-static void add_partition_map(zbi_header_t* zbi) {
- struct mtd_partition* tpl_part = NULL;
- struct mtd_partition* fts_part = NULL;
- struct mtd_partition* factory_part = NULL;
- struct mtd_partition* recovery_part = NULL;
- struct mtd_partition* boot_part = NULL;
- struct mtd_partition* system_part = NULL;
- struct mtd_partition* partitions = get_aml_mtd_partition();
- int partition_count = get_aml_partition_count();
- int i;
-
- for (i = 0; i < partition_count; i++) {
- struct mtd_partition* part = &partitions[i];
- if (!strcmp("tpl", part->name)) {
- tpl_part = part;
- } else if (!strcmp("fts", part->name)) {
- fts_part = part;
- } else if (!strcmp("factory", part->name)) {
- factory_part = part;
- } else if (!strcmp("recovery", part->name)) {
- recovery_part = part;
- } else if (!strcmp("boot", part->name)) {
- boot_part = part;
- } else if (!strcmp("system", part->name)) {
- system_part = part;
- }
- }
-
- if (!tpl_part) {
- printf("could not find tpl partition\n");
- return;
- }
- if (!fts_part) {
- printf("could not find fts partition\n");
- return;
- }
- if (!factory_part) {
- printf("could not find factory partition\n");
- return;
- }
- if (!recovery_part) {
- printf("could not find recovery partition\n");
- return;
- }
- if (!boot_part) {
- printf("could not find boot partition\n");
- return;
- }
- if (!system_part) {
- printf("could not find system partition\n");
- return;
- }
-
- uint32_t block_size = nand_info[1].writesize;
- uint64_t total_size = nand_info[1].size;
-
- partition_map.block_size = block_size;
- partition_map.block_count = total_size / block_size;
-
- // map tpl partition to BOOTLOADER
- partition_map.partitions[PART_TPL].first_block = tpl_part->offset / block_size;
- partition_map.partitions[PART_TPL].last_block =
- ((tpl_part->offset + tpl_part->size) / block_size) - 1;
- // map fts partition to "fts"
- partition_map.partitions[PART_FTS].first_block = fts_part->offset / block_size;
- partition_map.partitions[PART_FTS].last_block =
- ((fts_part->offset + fts_part->size) / block_size) - 1;
- // map factory partition to "factory"
- partition_map.partitions[PART_FACTORY].first_block = factory_part->offset / block_size;
- partition_map.partitions[PART_FACTORY].last_block =
- ((factory_part->offset + factory_part->size) / block_size) - 1;
- // map recovery partition to ZIRCON_B
- partition_map.partitions[PART_ZIRCON_B].first_block = recovery_part->offset / block_size;
- partition_map.partitions[PART_ZIRCON_B].last_block =
- ((recovery_part->offset + recovery_part->size) / block_size) - 1;
- // map boot partition to ZIRCON_A
- partition_map.partitions[PART_ZIRCON_A].first_block = boot_part->offset / block_size;
- partition_map.partitions[PART_ZIRCON_A].last_block =
- ((boot_part->offset + boot_part->size) / block_size) - 1;
- // ZIRCON_R partition at start of system
- partition_map.partitions[PART_ZIRCON_R].first_block = system_part->offset / block_size;
- partition_map.partitions[PART_ZIRCON_R].last_block =
- partition_map.partitions[PART_ZIRCON_R].first_block +
- (RECOVERY_SIZE / block_size) - 1;
- // FVM follows ZIRCON_R
- partition_map.partitions[PART_FVM].first_block =
- partition_map.partitions[PART_ZIRCON_R].last_block + 1;
- partition_map.partitions[PART_FVM].last_block =
- ((total_size - SYS_CONFIG_SIZE - MIGRATION_SIZE) / block_size) - 1;
- // SYS_CONFIG follows FVM
- partition_map.partitions[PART_SYS_CONFIG].first_block =
- partition_map.partitions[PART_FVM].last_block + 1;
- partition_map.partitions[PART_SYS_CONFIG].last_block =
- partition_map.partitions[PART_SYS_CONFIG].first_block +
- (SYS_CONFIG_SIZE / block_size) - 1;
- // MIGRATION follows SYS_CONFIG
- partition_map.partitions[PART_MIGRATION].first_block =
- partition_map.partitions[PART_SYS_CONFIG].last_block + 1;
- partition_map.partitions[PART_MIGRATION].last_block =
- partition_map.partitions[PART_MIGRATION].first_block +
- (MIGRATION_SIZE / block_size) - 1;
-
- printf("Zircon partitions:\n");
- for (i = 0; i < PART_COUNT; i++) {
- printf(" 0x%016llx - 0x%016llx : %s\n",
- partition_map.partitions[i].first_block * block_size,
- (partition_map.partitions[i].last_block + 1) * block_size,
- partition_map.partitions[i].name);
- }
-
- zircon_append_boot_item(zbi, ZBI_TYPE_DRV_PARTITION_MAP, 0, &partition_map,
- sizeof(zbi_partition_map_t) +
- partition_map.partition_count * sizeof(zbi_partition_t));
-}
-
-int zircon_preboot(zbi_header_t* zbi) {
- // add CPU configuration
- zircon_append_boot_item(zbi, ZBI_TYPE_CPU_CONFIG, 0, &cpu_config,
- sizeof(zbi_cpu_config_t) +
- sizeof(zbi_cpu_cluster_t) * cpu_config.cluster_count);
-
- // allocate crashlog save area before 0x5f800000-0x60000000 reserved area
- zbi_nvram_t nvram;
- nvram.base = 0x5f800000 - NVRAM_LENGTH;
- nvram.length = NVRAM_LENGTH;
- zircon_append_boot_item(zbi, ZBI_TYPE_NVRAM, 0, &nvram, sizeof(nvram));
-
- // add memory configuration
- zircon_append_boot_item(zbi, ZBI_TYPE_MEM_CONFIG, 0, &mem_config, sizeof(mem_config));
-
- // add kernel drivers
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_AMLOGIC_UART, &uart_driver,
- sizeof(uart_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_GIC_V2, &gicv2_driver,
- sizeof(gicv2_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_PSCI, &psci_driver,
- sizeof(psci_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_GENERIC_TIMER, &timer_driver,
- sizeof(timer_driver));
-
- zircon_append_boot_item(zbi, ZBI_TYPE_CMDLINE, 0, BOOTLOADER_VERSION, strlen(BOOTLOADER_VERSION) + 1);
-
- // add platform ID
- zircon_append_boot_item(zbi, ZBI_TYPE_PLATFORM_ID, 0, &platform_id, sizeof(platform_id));
-
- add_partition_map(zbi);
-
- return 0;
-}
diff --git a/board/amlogic/sm1_elaine_p1/Kconfig b/board/amlogic/sm1_elaine_p1/Kconfig
deleted file mode 100755
index 038f204..0000000
--- a/board/amlogic/sm1_elaine_p1/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_SM1_ELAINE_P1
-
-config SYS_SOC
- default "g12a"
-
-config SYS_BOARD
- default "sm1_elaine_p1"
-
-config SYS_VENDOR
- default "amlogic"
-
-config SYS_CONFIG_NAME
- default "sm1_elaine_p1"
-
-endif
diff --git a/board/amlogic/sm1_elaine_p1/Makefile b/board/amlogic/sm1_elaine_p1/Makefile
deleted file mode 100755
index fb7f59a..0000000
--- a/board/amlogic/sm1_elaine_p1/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-
-obj-y += $(BOARD).o eth_setup.o
-obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/sm1_elaine_p1/aml-user-key.sig b/board/amlogic/sm1_elaine_p1/aml-user-key.sig
deleted file mode 100755
index 2ceabc1..0000000
--- a/board/amlogic/sm1_elaine_p1/aml-user-key.sig
+++ /dev/null
Binary files differ
diff --git a/board/amlogic/sm1_elaine_p1/eth_setup.c b/board/amlogic/sm1_elaine_p1/eth_setup.c
deleted file mode 100755
index 6cbcd95..0000000
--- a/board/amlogic/sm1_elaine_p1/eth_setup.c
+++ /dev/null
@@ -1,51 +0,0 @@
-
-/*
- * board/amlogic/txl_skt_v1/eth_setup.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <malloc.h>
-#include <errno.h>
-#include <environment.h>
-#include <fdt_support.h>
-#include <linux/libfdt.h>
-#include <asm/arch/eth_setup.h>
-/*
- *
- *setup eth device board socket
- *
- */
-struct eth_board_socket* eth_board_setup(char *name){
- struct eth_board_socket* new_board;
- new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
- if (NULL == new_board) return NULL;
- if (name != NULL) {
- new_board->name=(char*)malloc(strlen(name));
- strncpy(new_board->name,name,strlen(name));
- }else{
- new_board->name="gxb";
- }
-
- new_board->eth_pinmux_setup=NULL ;
- new_board->eth_clock_configure=NULL;
- new_board->eth_hw_reset=NULL;
- return new_board;
-}
-//pinmux HHI_GCLK_MPEG1[bit 3]
-//
diff --git a/board/amlogic/sm1_elaine_p1/firmware/ramdump.c b/board/amlogic/sm1_elaine_p1/firmware/ramdump.c
deleted file mode 100755
index e03dcd2..0000000
--- a/board/amlogic/sm1_elaine_p1/firmware/ramdump.c
+++ /dev/null
@@ -1,45 +0,0 @@
-
-#ifdef CONFIG_MDUMP_COMPRESS
-#include "ramdump.h"
-
-struct ram_compress_full __ramdump_data = {
- .store_phy_addr = (void *)CONFIG_COMPRESSED_DATA_ADDR,
- .full_memsize = CONFIG_DDR_TOTAL_SIZE,
- .section_count = CONFIG_COMPRESS_SECTION,
- .sections = {
- {
- /* memory afer compressed data address */
- .phy_addr = (void *)CONFIG_COMPRESSED_DATA_ADDR,
- .section_size = CONFIG_DDR_TOTAL_SIZE -
- CONFIG_COMPRESSED_DATA_ADDR,
- .section_index = 4,
- .compress_type = RAM_COMPRESS_NORMAL,
- },
- {
- /* memory before bl2 */
- .phy_addr = (void *)CONFIG_COMPRESS_START_ADDR,
- .section_size = CONFIG_BL2_IGNORE_ADDR -
- CONFIG_COMPRESS_START_ADDR,
- .section_index = 1,
- .compress_type = RAM_COMPRESS_NORMAL,
- },
- {
- /* memory in reserved bl2 */
- .phy_addr = (void *)CONFIG_BL2_IGNORE_ADDR,
- .section_size = CONFIG_BL2_IGNORE_SIZE,
- .section_index = 2,
- .compress_type = RAM_COMPRESS_SET,
- .set_value = 0x0,
- },
- {
- /* segment 4: normal compress */
- .phy_addr = (void *)CONFIG_SEG4_ADDR,
- .section_size = CONFIG_COMPRESSED_DATA_ADDR -
- CONFIG_SEG4_ADDR,
- .section_index = 3,
- .compress_type = RAM_COMPRESS_NORMAL,
- }
- },
-};
-#endif /* CONFIG_MDUMP_COMPRESS */
-
diff --git a/board/amlogic/sm1_elaine_p1/firmware/ramdump.h b/board/amlogic/sm1_elaine_p1/firmware/ramdump.h
deleted file mode 100755
index 0671567..0000000
--- a/board/amlogic/sm1_elaine_p1/firmware/ramdump.h
+++ /dev/null
@@ -1,75 +0,0 @@
-#ifndef __RAM_DUMP_H__
-#define __RAM_DUMP_H__
-
-#include <config.h>
-#ifdef CONFIG_MDUMP_COMPRESS
-#define CONFIG_COMPRESS_SECTION 4
-
-#if CONFIG_COMPRESS_SECTION > 8
-#error ---> CONFIG_COMPRESS_SECTION out of range, max should be 8
-#endif
-/*
- * Full Memory lay out for RAM compress:
- *
- * DDR_TOP -> +--------+
- * | |
- * | |
- * | 4 |
- * | |
- * | |
- * |~~~~~~~~| <- store compressing data
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * COMPRESSED_DATA -> +--------+
- * | |
- * | 3 |
- * | |
- * BL2_IGNORE_END -> +--------+ -- IGNORE_SIZE
- * ||||||||||
- * ||||2|||||
- * ||||||||||
- * BL2_IGNORE_ADDR -> +--------+
- * | |
- * | 1 |
- * | |
- * COMPRESS_START_ADDR -> +--------+
- */
-#define CONFIG_DDR_TOTAL_SIZE (CONFIG_DDR_SIZE << 20)
-#define CONFIG_COMPRESSED_DATA_ADDR (0x10000000)
-#define CONFIG_COMPRESSED_DATA_ADDR1 (0x08000000)
-
-#define CONFIG_COMPRESS_START_ADDR (0x00000000)
-#define CONFIG_BL2_IGNORE_ADDR (0x05000000)
-#define CONFIG_BL2_IGNORE_SIZE (0x00300000)
-#define CONFIG_SEG4_ADDR (CONFIG_BL2_IGNORE_ADDR + \
- CONFIG_BL2_IGNORE_SIZE)
-
-enum {
- RAM_COMPRESS_NORMAL = 1,
- RAM_COMPRESS_COPY = 2,
- RAM_COMPRESS_SET = 3 /* set ram content to same vale */
-};
-
-struct ram_compress_section {
- void *phy_addr;
- unsigned int section_size;
- unsigned int section_index : 8;
- unsigned int compress_type : 8;
- unsigned int set_value : 16;
-};
-
-struct ram_compress_full {
- void *store_phy_addr;
- unsigned int full_memsize;
- unsigned int section_count;
- struct ram_compress_section sections[CONFIG_COMPRESS_SECTION];
-};
-
-#endif
-#endif /* __RAM_DUMP_H__ */
diff --git a/board/amlogic/sm1_elaine_p1/firmware/scp_task/dvfs_board.c b/board/amlogic/sm1_elaine_p1/firmware/scp_task/dvfs_board.c
deleted file mode 100755
index accb38f..0000000
--- a/board/amlogic/sm1_elaine_p1/firmware/scp_task/dvfs_board.c
+++ /dev/null
@@ -1,194 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_p1/firmware/scp_task/dvfs_board.c
- *
- * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-/*
-int pwm_voltage_table[ ][2] = {
- { 0x1c0000, 860},
- { 0x1b0001, 870},
- { 0x1a0002, 880},
- { 0x190003, 890},
- { 0x180004, 900},
- { 0x170005, 910},
- { 0x160006, 920},
- { 0x150007, 930},
- { 0x140008, 940},
- { 0x130009, 950},
- { 0x12000a, 960},
- { 0x11000b, 970},
- { 0x10000c, 980},
- { 0x0f000d, 990},
- { 0x0e000e, 1000},
- { 0x0d000f, 1010},
- { 0x0c0010, 1020},
- { 0x0b0011, 1030},
- { 0x0a0012, 1040},
- { 0x090013, 1050},
- { 0x080014, 1060},
- { 0x070015, 1070},
- { 0x060016, 1080},
- { 0x050017, 1090},
- { 0x040018, 1100},
- { 0x030019, 1110},
- { 0x02001a, 1120},
- { 0x01001b, 1130},
- { 0x00001c, 1140}
-};
-*/
-#include "pwm_ctrl.h"
-
-#define CHIP_ADJUST 20
-#define RIPPLE_ADJUST 30
-struct scpi_opp_entry cpu_dvfs_tbl[] = {
- DVFS( 100000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS( 250000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS( 500000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1200000000, 940+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1296000000, 980+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1416000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
-};
-
-
-#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
-#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
-#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2))))
-
-#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2))))
-#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
-
-
-enum pwm_id {
- pwm_a = 0,
-};
-
-
-void pwm_init(int id)
-{
- /*
- * TODO: support more pwm controllers, right now only support PWM_B
- */
- unsigned int reg;
- reg = P_PWM_MISC_REG_AB;
- reg &= ~(0x7f << 8);
- reg |= ((1 << 15) | (1 << 0));
- P_PWM_MISC_REG_AB = reg;
- /*
- * default set to max voltage
- */
- //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
- reg = P_PIN_MUX_REG3;
- reg &= ~((1 << 21) | 1 << 12);
- P_PIN_MUX_REG3 = reg;
-
- reg = P_PIN_MUX_REG10;
- reg &= ~(1 << 16);
- P_PIN_MUX_REG10 = reg;//clear reg10
- reg = P_PIN_MUX_REG4;
- reg &= ~(1 << 26); // clear PWM_VS
- reg |= (1 << 17); // enable PWM_A
- P_PIN_MUX_REG4 = reg;
-
-
- _udelay(200);
-}
-
-int dvfs_get_voltage(void)
-{
- int i = 0;
- unsigned int reg_val;
-
- reg_val = P_PWM_PWM_A;
- for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
- if (pwm_voltage_table[i][0] == reg_val) {
- return i;
- }
- }
- if (i >= ARRAY_SIZE(pwm_voltage_table)) {
- return -1;
- }
- return -1;
-}
-
-void set_dvfs(unsigned int domain, unsigned int index)
-{
- int cur, to;
- static int init_flag = 0;
-
- if (!init_flag) {
- pwm_init(pwm_a);
- init_flag = 1;
- }
- cur = dvfs_get_voltage();
- for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
- if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
- break;
- }
- }
- if (to >= ARRAY_SIZE(pwm_voltage_table)) {
- to = ARRAY_SIZE(pwm_voltage_table) - 1;
- }
- if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
- P_PWM_PWM_A = pwm_voltage_table[to][0];
- _udelay(200);
- return ;
- }
- while (cur != to) {
- /*
- * if target step is far away from current step, don't change
- * voltage by one-step-done. You should change voltage step by
- * step to make sure voltage output is stable
- */
- if (cur < to) {
- if (cur < to - 3) {
- cur += 3;
- } else {
- cur = to;
- }
- } else {
- if (cur > to + 3) {
- cur -= 3;
- } else {
- cur = to;
- }
- }
- P_PWM_PWM_A = pwm_voltage_table[cur][0];
- _udelay(100);
- }
- _udelay(200);
-}
-void get_dvfs_info_board(unsigned int domain,
- unsigned char *info_out, unsigned int *size_out)
-{
- unsigned int cnt;
- cnt = ARRAY_SIZE(cpu_dvfs_tbl);
-
- buf_opp.latency = 200;
- buf_opp.count = cnt;
- memset(&buf_opp.opp[0], 0,
- MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
-
- memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
- cnt * sizeof(struct scpi_opp_entry));
-
- memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
- *size_out = sizeof(struct scpi_opp);
- return;
-}
diff --git a/board/amlogic/sm1_elaine_p1/firmware/scp_task/pwm_ctrl.h b/board/amlogic/sm1_elaine_p1/firmware/scp_task/pwm_ctrl.h
deleted file mode 100755
index 0f815f8..0000000
--- a/board/amlogic/sm1_elaine_p1/firmware/scp_task/pwm_ctrl.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
-*board/amlogic/sm1_elaine_p1/firmware/scp_task/pwm_vol_tab.h
-*table for Dynamic Voltage/Frequency Scaling
-*/
-#ifndef __PWM_CTRL_H__
-#define __PWM_CTRL_H__
-
-static int pwm_voltage_table_ee[][2] = {
- { 0x1c0000, 681},
- { 0x1b0001, 691},
- { 0x1a0002, 701},
- { 0x190003, 711},
- { 0x180004, 721},
- { 0x170005, 731},
- { 0x160006, 741},
- { 0x150007, 751},
- { 0x140008, 761},
- { 0x130009, 772},
- { 0x12000a, 782},
- { 0x11000b, 792},
- { 0x10000c, 802},
- { 0x0f000d, 812},
- { 0x0e000e, 822},
- { 0x0d000f, 832},
- { 0x0c0010, 842},
- { 0x0b0011, 852},
- { 0x0a0012, 862},
- { 0x090013, 872},
- { 0x080014, 882},
- { 0x070015, 892},
- { 0x060016, 902},
- { 0x050017, 912},
- { 0x040018, 922},
- { 0x030019, 932},
- { 0x02001a, 942},
- { 0x01001b, 952},
- { 0x00001c, 962}
-};
-
-#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/sm1_elaine_p1/firmware/scp_task/pwr_ctrl.c b/board/amlogic/sm1_elaine_p1/firmware/scp_task/pwr_ctrl.c
deleted file mode 100755
index 7289735..0000000
--- a/board/amlogic/sm1_elaine_p1/firmware/scp_task/pwr_ctrl.c
+++ /dev/null
@@ -1,196 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_p1/firmware/scp_task/pwr_ctrl.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <gpio.h>
-#include "pwm_ctrl.h"
-#ifdef CONFIG_CEC_WAKEUP
-#include <cec_tx_reg.h>
-#endif
-
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
-static void set_vddee_voltage(unsigned int target_voltage)
-{
- unsigned int to;
-
- for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
- if (pwm_voltage_table_ee[to][1] >= target_voltage) {
- break;
- }
- }
-
- if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
- to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
- }
-
- writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
-}
-
-static void power_off_at_24M(unsigned int suspend_from)
-{
- /*set gpioH_8 low to power off vcc 5v*/
- writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
- writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
-
- /*set test_n low to power off vcck & vcc 3.3v*/
- writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
- writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
- writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
-
- /*step down ee voltage*/
- set_vddee_voltage(AML_VDDEE_SLEEP_VOLTAGE);
-}
-
-static void power_on_at_24M(unsigned int suspend_from)
-{
- /*step up ee voltage*/
- set_vddee_voltage(AML_VDDEE_INIT_VOLTAGE);
-
- /*set test_n low to power on vcck & vcc 3.3v*/
- writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
- writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
- writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
- _udelay(100);
-
- /*set gpioH_8 low to power on vcc 5v*/
- writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
- writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
- _udelay(10000);
-
-}
-
-void get_wakeup_source(void *response, unsigned int suspend_from)
-{
- struct wakeup_info *p = (struct wakeup_info *)response;
- struct wakeup_gpio_info *gpio;
- unsigned val;
- unsigned i = 0;
-
- p->status = RESPONSE_OK;
- val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
- ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC | ETH_PHY_GPIO_SRC
- | CECB_WAKEUP_SRC);
-
- p->sources = val;
-
- /* Power Key: AO_GPIO[3]*/
- gpio = &(p->gpio_info[i]);
- gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
- gpio->gpio_in_idx = GPIOAO_3;
- gpio->gpio_in_ao = 1;
- gpio->gpio_out_idx = -1;
- gpio->gpio_out_ao = -1;
- gpio->irq = IRQ_AO_GPIO0_NUM;
- gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
- p->gpio_info_count = ++i;
-
- /*Eth:GPIOZ_14*/
- gpio = &(p->gpio_info[i]);
- gpio->wakeup_id = ETH_PHY_GPIO_SRC;
- gpio->gpio_in_idx = GPIOZ_14;
- gpio->gpio_in_ao = 0;
- gpio->gpio_out_idx = -1;
- gpio->gpio_out_ao = -1;
- gpio->irq = IRQ_GPIO1_NUM;
- gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
- p->gpio_info_count = ++i;
-
- /*bt wake host*/
- gpio = &(p->gpio_info[i]);
- gpio->wakeup_id = BT_WAKEUP_SRC;
- gpio->gpio_in_idx = GPIOX_18;
- gpio->gpio_in_ao = 0;
- gpio->gpio_out_idx = -1;
- gpio->gpio_out_ao = -1;
- gpio->irq = IRQ_GPIO0_NUM;
- gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
- p->gpio_info_count = ++i;
-}
-extern void __switch_idle_task(void);
-
-static unsigned int detect_key(unsigned int suspend_from)
-{
- int exit_reason = 0;
- unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
- init_remote();
-#ifdef CONFIG_CEC_WAKEUP
- if (hdmi_cec_func_config & 0x1) {
- remote_cec_hw_reset();
- cec_node_init();
- }
-#endif
-
- do {
- #ifdef CONFIG_CEC_WAKEUP
- if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
- irq[IRQ_AO_CECB] = 0xFFFFFFFF;
- if (cec_power_on_check())
- exit_reason = CEC_WAKEUP;
- }
- #endif
- if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
- irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
- if (remote_detect_key())
- exit_reason = REMOTE_WAKEUP;
- }
-
- if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) {
- irq[IRQ_VRTC] = 0xFFFFFFFF;
- exit_reason = RTC_WAKEUP;
- }
-
- if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
- irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
- if ((readl(AO_GPIO_I) & (1<<3)) == 0)
- exit_reason = POWER_KEY_WAKEUP;
- }
-#if 0
- if (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM) {
- irq[IRQ_GPIO1] = 0xFFFFFFFF;
- if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 14))
- && (readl(PREG_PAD_GPIO4_EN_N) & (0x01 << 14)))
- exit_reason = ETH_PHY_GPIO;
- }
-#endif
- if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
- irq[IRQ_GPIO0] = 0xFFFFFFFF;
- if (!(readl(PREG_PAD_GPIO2_I) & (0x01 << 18))
- && (readl(PREG_PAD_GPIO2_O) & (0x01 << 17))
- && !(readl(PREG_PAD_GPIO2_EN_N) & (0x01 << 17)))
- exit_reason = BT_WAKEUP;
- }
-
- if (exit_reason)
- break;
- else
- __switch_idle_task();
- } while (1);
-
- return exit_reason;
-}
-
-static void pwr_op_init(struct pwr_op *pwr_op)
-{
- pwr_op->power_off_at_24M = power_off_at_24M;
- pwr_op->power_on_at_24M = power_on_at_24M;
- pwr_op->detect_key = detect_key;
- pwr_op->get_wakeup_source = get_wakeup_source;
-}
diff --git a/board/amlogic/sm1_elaine_p1/firmware/timing.c b/board/amlogic/sm1_elaine_p1/firmware/timing.c
deleted file mode 100755
index 8c785e8..0000000
--- a/board/amlogic/sm1_elaine_p1/firmware/timing.c
+++ /dev/null
@@ -1,462 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_p1/firmware/timing.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/timing.h>
-#include <asm/arch/ddr_define.h>
-
-/* board clk defines */
-#define DDR_SIZE 0
-#define CPU_CLK 1200
-
-/* ddr config support multiple configs for boards which use same bootloader:
- * config steps:
- * 1. add a new data struct in __ddr_setting[]
- * 2. config correct board_id, ddr_type, freq, etc..
- */
-
-
-/* CAUTION!! */
-/* Confirm ddr configs with hardware designer,
- * if you don't know how to config, then don't edit it
- */
-
-/* Key configs */
-/*
- * board_id: check hardware adc config
- * dram_rank_config:
- * #define CONFIG_DDR_CHL_AUTO 0xF
- * #define CONFIG_DDR0_16BIT_CH0 0x1
- * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
- * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
- * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
- * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
- * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
- * DramType:
- * #define CONFIG_DDR_TYPE_DDR3 0
- * #define CONFIG_DDR_TYPE_DDR4 1
- * #define CONFIG_DDR_TYPE_LPDDR4 2
- * #define CONFIG_DDR_TYPE_LPDDR3 3
- * DRAMFreq:
- * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
- *
- */
-
-
-/* ddr configs */
-#define DDR_RFC_TYPE_DDR3_512Mbx1 0
-#define DDR_RFC_TYPE_DDR3_512Mbx2 1
-#define DDR_RFC_TYPE_DDR3_512Mbx4 2
-#define DDR_RFC_TYPE_DDR3_512Mbx8 3
-#define DDR_RFC_TYPE_DDR3_512Mbx16 4
-#define DDR_RFC_TYPE_DDR4_2Gbx1 5
-#define DDR_RFC_TYPE_DDR4_2Gbx2 6
-#define DDR_RFC_TYPE_DDR4_2Gbx4 7
-#define DDR_RFC_TYPE_DDR4_2Gbx8 8
-
-#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
-#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
-#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
-
-#if CONFIG_DDR_LOGS_ENABLED
-#define LOG_FLAG 0x4
-#else
-#define LOG_FLAG 0xA
-#endif
-
-ddr_set_t __ddr_setting[] = {
- {
- /* Elaine ddr3 */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
- .DramType = CONFIG_DDR_TYPE_DDR3,
- .DRAMFreq = {912, 0, 0, 0},
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 1,
- .HdtCtrl = LOG_FLAG,
- .dram_cs0_size_MB = 1024,
- .dram_cs1_size_MB = 1024,
- .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .clk_drv_ohm = 40,
- .cs_drv_ohm = 40,
- .ac_drv_ohm = 40,
- .soc_data_drv_ohm_p = 34,
- .soc_data_drv_ohm_n = 34,
- .soc_data_odt_ohm_p = 60, //48,
- .soc_data_odt_ohm_n = 0,
- .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
- .dram_data_odt_ohm = 60,
- .dram_ac_odt_ohm = 0,
- .soc_clk_slew_rate = 0x300,
- .soc_cs_slew_rate = 0x300,
- .soc_ac_slew_rate = 0x300,
- .soc_data_slew_rate = 0x200,
- .vref_output_permil = 500,
- .vref_receiver_permil = 500, //700,
- .vref_dram_permil = 500, //700,
-// .vref_reverse = 0,
- .ac_trace_delay ={32,32,32,32,32,32,32,32,32,32},
- //{00,00},
- .ac_pinmux = {00,00},
-#if 1
- .ddr_dmc_remap = {
- [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
- [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
- },
-#else
- //16bit
- .ddr_dmc_remap = {
- [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
- [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
- [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
- [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
- },
-#endif
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap = {00,00},
- .dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
- .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
-},
-{
- /* g12a skt (u209) ddr3 */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
- .DramType = CONFIG_DDR_TYPE_DDR3,
- .DRAMFreq = {912, 0, 0, 0},
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 1,
- .HdtCtrl = LOG_FLAG,
- .dram_cs0_size_MB = 1024,
- .dram_cs1_size_MB = 512,
- .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .pll_ssc_mode = 0,
- .clk_drv_ohm = 40,
- .cs_drv_ohm = 40,
- .ac_drv_ohm = 40,
- .soc_data_drv_ohm_p = 34,
- .soc_data_drv_ohm_n = 34,
- .soc_data_odt_ohm_p = 60, //48,
- .soc_data_odt_ohm_n = 0,
- .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
- .dram_data_odt_ohm = 60,
- .dram_ac_odt_ohm = 0,
- .soc_clk_slew_rate = 0x300,
- .soc_cs_slew_rate = 0x300,
- .soc_ac_slew_rate = 0x300,
- .soc_data_slew_rate = 0x200,
- .vref_output_permil = 500,
- .vref_receiver_permil = 500, //700,
- .vref_dram_permil = 500, //700,
- //{00,00},
- .ac_pinmux = {00,00},
-#if 1
- .ddr_dmc_remap = {
- [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
- [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
- },
-#else
- //16bit
- .ddr_dmc_remap = {
- [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
- [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
- [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
- [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
- },
-#endif
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap = {00,00},
- .dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
- .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
- .slt_test_function = {DMC_TEST_SLT_ENABLE_DDR_SKIP_TRAINING, 0},
- .dfi_hwtmrl = 4,
-
- .ac_trace_delay = {
- 32, 32, 32, 32,
- 32, 32, 32, 32,
- 32, 32,
- },
-
- .write_dqs_delay = {
- 163, 163, 163, 163,
- 167, 167, 165, 165,
- 159, 159, 163, 163,
- 165, 165, 161, 161,
- },
-
- .read_dqs_delay = {
- 13, 13, 14, 14,
- 14, 14, 15, 14,
- 14, 14, 14, 15,
- 14, 13, 14, 14,
- },
-
- .write_dq_bit_delay = {
- 20, 21, 19, 21,
- 21, 21, 22, 20,
- 22, 21, 20, 20,
- 19, 21, 18, 21,
- 20, 20, 24, 20,
- 22, 25, 24, 25,
- 26, 26, 23, 20,
- 21, 20, 23, 21,
- 21, 23, 23, 20,
- 48, 49, 48, 50,
- 50, 50, 51, 49,
- 49, 21, 21, 19,
- 20, 21, 19, 20,
- 21, 20, 22, 18,
- 20, 23, 23, 24,
- 24, 24, 22, 17,
- 18, 17, 20, 18,
- 18, 21, 20, 19,
- },
-
- .read_dq_bit_delay = {
- 15, 15, 15, 23,
- 31, 31, 31, 29,
- 0 , 23, 19, 11,
- 17, 35, 23, 31,
- 31, 0 , 15, 3 ,
- 9 , 15, 27, 27,
- 35, 35, 0 , 13,
- 15, 11, 19, 25,
- 19, 31, 31, 0 ,
- 15, 17, 15, 19,
- 31, 33, 31, 27,
- 0 , 19, 19, 15,
- 13, 31, 23, 27,
- 31, 0 , 13, 3 ,
- 5 , 11, 23, 27,
- 31, 27, 0 , 13,
- 13, 9 , 19, 23,
- 23, 27, 27, 0 ,
- },
-
- .read_dqs_gate_delay = {
- 225, 227, 223, 225,
- 223, 225, 223, 227,
- 223, 225, 223, 225,
- 225, 227, 227, 229,
- },
-
-},
-};
-
-pll_set_t __pll_setting = {
- .cpu_clk = CPU_CLK / 24 * 24,
-#ifdef CONFIG_PXP_EMULATOR
- .pxp = 1,
-#else
- .pxp = 0,
-#endif
- .spi_ctrl = 0,
- .lCustomerID = AML_CUSTOMER_ID,
-#ifdef CONFIG_DEBUG_MODE
- .debug_mode = CONFIG_DEBUG_MODE,
- .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
- .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
-#endif
-};
-
-ddr_reg_t __ddr_reg[] = {
- /* demo, user defined override register */
- {0xaabbccdd, 0, 0, 0, 0, 0},
- {0x11223344, 0, 0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0},
-};
-
-#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
-#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
-/* VCCK PWM table */
-#if (VCCK_VAL == 800)
- #define VCCK_VAL_REG 0x00150007
-#elif (VCCK_VAL == 810)
- #define VCCK_VAL_REG 0x00140008
-#elif (VCCK_VAL == 820)
- #define VCCK_VAL_REG 0x00130009
-#elif (VCCK_VAL == 830)
- #define VCCK_VAL_REG 0x0012000a
-#elif (VCCK_VAL == 840)
- #define VCCK_VAL_REG 0x0011000b
-#elif (VCCK_VAL == 850)
- #define VCCK_VAL_REG 0x0010000c
-#elif (VCCK_VAL == 860)
- #define VCCK_VAL_REG 0x000f000d
-#elif (VCCK_VAL == 870)
- #define VCCK_VAL_REG 0x000e000e
-#elif (VCCK_VAL == 880)
- #define VCCK_VAL_REG 0x000d000f
-#elif (VCCK_VAL == 890)
- #define VCCK_VAL_REG 0x000c0010
-#elif (VCCK_VAL == 900)
- #define VCCK_VAL_REG 0x000b0011
-#elif (VCCK_VAL == 910)
- #define VCCK_VAL_REG 0x000a0012
-#elif (VCCK_VAL == 920)
- #define VCCK_VAL_REG 0x00090013
-#elif (VCCK_VAL == 930)
- #define VCCK_VAL_REG 0x00080014
-#elif (VCCK_VAL == 940)
- #define VCCK_VAL_REG 0x00070015
-#elif (VCCK_VAL == 950)
- #define VCCK_VAL_REG 0x00060016
-#elif (VCCK_VAL == 960)
- #define VCCK_VAL_REG 0x00050017
-#elif (VCCK_VAL == 970)
- #define VCCK_VAL_REG 0x00040018
-#elif (VCCK_VAL == 980)
- #define VCCK_VAL_REG 0x00030019
-#elif (VCCK_VAL == 990)
- #define VCCK_VAL_REG 0x0002001a
-#elif (VCCK_VAL == 1000)
- #define VCCK_VAL_REG 0x0001001b
-#elif (VCCK_VAL == 1010)
- #define VCCK_VAL_REG 0x0000001c
-#else
- #error "VCCK val out of range\n"
-#endif
-
-/* VDDEE PWM table */
-#if (VDDEE_VAL == 800)
- #define VDDEE_VAL_REG 0x0010000c
-#elif (VDDEE_VAL == 810)
- #define VDDEE_VAL_REG 0x000f000d
-#elif (VDDEE_VAL == 820)
- #define VDDEE_VAL_REG 0x000e000e
-#elif (VDDEE_VAL == 830)
- #define VDDEE_VAL_REG 0x000d000f
-#elif (VDDEE_VAL == 840)
- #define VDDEE_VAL_REG 0x000c0010
-#elif (VDDEE_VAL == 850)
- #define VDDEE_VAL_REG 0x000b0011
-#elif (VDDEE_VAL == 860)
- #define VDDEE_VAL_REG 0x000a0012
-#elif (VDDEE_VAL == 870)
- #define VDDEE_VAL_REG 0x00090013
-#elif (VDDEE_VAL == 880)
- #define VDDEE_VAL_REG 0x00080014
-#elif (VDDEE_VAL == 890)
- #define VDDEE_VAL_REG 0x00070015
-#elif (VDDEE_VAL == 900)
- #define VDDEE_VAL_REG 0x00060016
-#elif (VDDEE_VAL == 910)
- #define VDDEE_VAL_REG 0x00050017
-#elif (VDDEE_VAL == 920)
- #define VDDEE_VAL_REG 0x00040018
-#elif (VDDEE_VAL == 930)
- #define VDDEE_VAL_REG 0x00030019
-#elif (VDDEE_VAL == 940)
- #define VDDEE_VAL_REG 0x0002001a
-#elif (VDDEE_VAL == 950)
- #define VDDEE_VAL_REG 0x0001001b
-#elif (VDDEE_VAL == 960)
- #define VDDEE_VAL_REG 0x0000001c
-#else
- #error "VDDEE val out of range\n"
-#endif
-
-/* for PWM use */
-/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
-#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
-#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
-#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
-#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
-#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
-
-bl2_reg_t __bl2_reg[] = {
- /* demo, user defined override register */
- /* eg: PWM init */
-
- /* PWM_AO_D */
- /* VCCK_VAL_REG: check PWM table */
- {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
- {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
- /* PWM_AO_B */
- /* VDDEE_VAL_REG: check PWM table */
- {AO_PWM_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
- {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_1, 0},
- /* Enable 5V_EN */
- {GPIO_O_EN_N_REG3, (0 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
- {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- /* Enable VCCK */
- {AO_SEC_REG0, (1 << 0), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- {AO_GPIO_O, 0x80000000, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
-};
diff --git a/board/amlogic/sm1_elaine_p1/lcd.c b/board/amlogic/sm1_elaine_p1/lcd.c
deleted file mode 100755
index ae176bd..0000000
--- a/board/amlogic/sm1_elaine_p1/lcd.c
+++ /dev/null
@@ -1,422 +0,0 @@
-/*
- * AMLOGIC TV LCD panel driver.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#ifdef CONFIG_AML_LCD_EXTERN
-#include "lcd_extern.h"
-#endif
-
-static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
- "GPIOH_6", /* panel rst */
- "GPIOZ_8", /* panel power */
- "invalid", /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step[] = {
- {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
- {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,50,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
- {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_on_step_KD070D82[] = {
- {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_KD070D82[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
- 0x05, 1, 0x11,
- 0xfd, 1, 20,
- 0x05, 1, 0x29,
- 0xfd, 1, 20,
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
- 0x05, 1, 0x28,
- 0xfd, 1, 10,
- 0x05, 1, 0x10,
- 0xfd, 1, 10,
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
- 0xfd, 1, 10,
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
- 0xff, 0, //ending
-};
-
-static unsigned char mipi_init_on_table_KD070D82[DSI_INIT_ON_MAX] = {//table size < 100
- 0xfd, 1, 10,
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_KD070D82[DSI_INIT_OFF_MAX] = {//table size < 50
- 0xff, 0, //ending
-};
-
-static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
- "GPIOH_4", /* BL_EN */
- "GPIOH_5", /* BL_PWM */
- "invalid", /* ending flag */
-};
-
-struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
- {/* TV070WSM_FT*/
- "boe_fiti_7",LCD_MIPI,8,
- /* basic timing */
- 600,1024,700,1053,24,36,0,2,8,0,
- /* clk_attr */
- 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,360,0,1,0,2,0,0,Rsv_val,3,
- /* cmd init */
- mipi_init_on_table, mipi_init_off_table,
- /* power step */
- lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* P070ACB_FT*/
- "inx_fiti_7",LCD_MIPI,8,
- /* basic timing */
- 600,1024,770,1070,10,80,0,6,20,0,
- /* clk_attr */
- 0,0,1,49434000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,400,0,1,0,2,0,0,Rsv_val,1,
- /* cmd init */
- mipi_init_on_table_P070ACB, mipi_init_off_table_P070ACB,
- /* power step */
- lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* KD070D82_FT*/
- "kd_fiti_7",LCD_MIPI,8,
- /* basic timing */
- 600,1024,770,1070,10,80,0,6,20,0,
- /* clk_attr */
- 0,0,1,49434000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,400,0,1,0,2,0,0,Rsv_val,2,
- /* cmd init */
- mipi_init_on_table_KD070D82, mipi_init_off_table_KD070D82,
- /* power step */
- lcd_power_on_step_KD070D82, lcd_power_off_step_KD070D82,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {.panel_type = "invalid"},
-};
-
-static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
- {
- .name = "lcd_pin",
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
- },
- {
- .name = "invalid",
- },
-};
-
-static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
- {
- .name = "bl_pwm_on_pin", //GPIOH_5
- .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
- },
- {
- .name = "invalid",
- },
-};
-
-#ifdef CONFIG_AML_BL_EXTERN
-static unsigned char bl_ext_init_on[BL_EXTERN_INIT_ON_MAX] = {
- 0xff, 0, //ending flag
-};
-static unsigned char bl_ext_init_off[BL_EXTERN_INIT_OFF_MAX] = {
- 0xff, 0, //ending flag
-};
-#endif
-
-/* **********************************************
- * driver struct, usually no need modify!
- * ********************************************** */
-static struct dsi_config_s lcd_mipi_config = {
- .lane_num = 4,
- .bit_rate_max = 1000, /* MHz */
- .factor_numerator = 0,
- .factor_denominator = 100,
- .operation_mode_init = 1, /* 0=video mode, 1=command mode */
- .operation_mode_display = 0, /* 0=video mode, 1=command mode */
- .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
- .clk_always_hs = 1, /* 0=disable, 1=enable */
- .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
-
- .dsi_init_on = mipi_init_on_table,
- .dsi_init_off = mipi_init_off_table,
- .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
- .check_en = 0,
- .check_state = 0,
-};
-
-static struct lcd_power_ctrl_s lcd_power_ctrl = {
- .power_on_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
- .power_off_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
-};
-
-struct lcd_config_s lcd_config_dft = {
- .lcd_mode = LCD_MODE_TABLET,
- .lcd_key_valid = 0,
- .lcd_clk_path = 0,
- .lcd_basic = {
- .model_name = "default",
- .lcd_type = LCD_TYPE_MAX,
- .lcd_bits = 8,
- .h_active = 768,
- .v_active = 1024,
- .h_period = 948,
- .v_period = 1140,
-
- .screen_width = 119,
- .screen_height = 159,
- },
-
- .lcd_timing = {
- .clk_auto = 1,
- .lcd_clk = 64843200,
- .ss_level = 0,
- .fr_adjust_type = 0,
-
- .hsync_width = 64,
- .hsync_bp = 56,
- .hsync_pol = 0,
- .vsync_width = 50,
- .vsync_bp = 30,
- .vsync_pol = 0,
- },
-
- .lcd_control = {
- .mipi_config= &lcd_mipi_config,
- },
- .lcd_power = &lcd_power_ctrl,
-
- .pinctrl_ver = 2,
- .lcd_pinmux = lcd_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_LCD_EXTERN
-struct lcd_extern_common_s ext_common_dft = {
- .lcd_ext_key_valid = 0,
- .i2c_bus = LCD_EXTERN_I2C_BUS_0, /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
- .i2c_gpio_sck = LCD_EXT_I2C_GPIO_SCK,
- .i2c_gpio_sda = LCD_EXT_I2C_GPIO_SDA,
- .spi_gpio_cs = LCD_EXT_SPI_GPIO_CS,
- .spi_gpio_clk = LCD_EXT_SPI_GPIO_CLK,
- .spi_gpio_data = LCD_EXT_SPI_GPIO_DATA,
-
- .lcd_ext_pinmux = lcd_ext_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
- .pinmux_gpio_off = LCD_EXT_PINMUX_GPIO_OFF,
-};
-
-struct lcd_extern_config_s ext_config_dtf = {
- .index = 0,
- .name = "ext_default",
- .type = LCD_EXTERN_MAX, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 0, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
-};
-#endif
-
-struct bl_config_s bl_config_dft = {
- .name = "default",
- .bl_key_valid = 0,
-
- .level_default = 100,
- .level_min = 10,
- .level_max = 255,
- .level_mid = 128,
- .level_mid_mapping = 128,
- .level = 0,
-
- .method = BL_CTRL_MAX,
- .power_on_delay = 20,
- .power_off_delay = 20,
-
- .en_gpio = 0xff,
- .en_gpio_on = 1,
- .en_gpio_off = 0,
-
- .bl_pwm = NULL,
- .bl_pwm_combo0 = NULL,
- .bl_pwm_combo1 = NULL,
- .pwm_on_delay = 10,
- .pwm_off_delay = 10,
-
- .bl_extern_index = 0xff,
-
- .pinctrl_ver = 2,
- .bl_pinmux = bl_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_BL_EXTERN
-struct bl_extern_config_s bl_extern_config_dtf = {
- .index = BL_EXTERN_INDEX_INVALID,
- .name = "none",
- .type = BL_EXTERN_MAX,
- .i2c_addr = 0xff,
- .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
- .dim_min = 10,
- .dim_max = 255,
-
- .init_loaded = 0,
- .cmd_size = 0xff,
- .init_on = bl_ext_init_on,
- .init_off = bl_ext_init_off,
- .init_on_cnt = sizeof(bl_ext_init_on),
- .init_off_cnt = sizeof(bl_ext_init_off),
-};
-#endif
-/* ********************************************** */
-
-void lcd_config_bsp_init(void)
-{
- int i, j;
- char *str;
- struct ext_lcd_config_s *ext_lcd = NULL;
-
- /* init config, usually no need modify */
- for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
- break;
- strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
- }
- for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
- strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
- for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
- break;
- strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
- }
- for (j = i; j < BL_GPIO_NUM_MAX; j++)
- strcpy(bl_config_dft.gpio_name[j], "invalid");
-
-#ifdef CONFIG_AML_LCD_EXTERN
- for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
- break;
- strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
- }
- for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
- strcpy(ext_common_dft.gpio_name[j], "invalid");
-#endif
-
- /* select special config */
- str = env_get("panel_type");
- if (str == NULL)
- return;
- for (i = 0 ; i < LCD_NUM_MAX ; i++) {
- ext_lcd = &ext_lcd_config[i];
- if (strcmp(ext_lcd->panel_type, str) == 0) {
-#ifdef CONFIG_AML_LCD_EXTERN
- j = ext_lcd->if_attr_val9; /* mipi extern_index */
- if (j < sizeof(ext_config)/sizeof(struct lcd_extern_config_s)) {
- memcpy(&ext_config_dtf, &ext_config[j],
- sizeof(struct lcd_extern_config_s));
- }
-#endif
- break;
- }
- }
-}
diff --git a/board/amlogic/sm1_elaine_p1/lcd_extern.h b/board/amlogic/sm1_elaine_p1/lcd_extern.h
deleted file mode 100755
index a004b0e..0000000
--- a/board/amlogic/sm1_elaine_p1/lcd_extern.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * board/amlogic/g12a_u200_v1/lcd_extern.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _DFT_LCD_EXTERN_H_
-#define _DFT_LCD_EXTERN_H_
-
-#define LCD_EXT_I2C_GPIO_SCK 0xff /* 0xff for invalid */
-#define LCD_EXT_I2C_GPIO_SDA 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_CS 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_CLK 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_DATA 0xff /* 0xff for invalid */
-#define LCD_EXT_PINMUX_GPIO_OFF 0
-
-static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
- "invalid", /* ending flag */
-};
-
-static struct lcd_pinmux_ctrl_s lcd_ext_pinmux_ctrl[LCD_PINMX_MAX] = {
- {
- .name = "invalid",
- },
-};
-
-static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
- 0xff, 0, //ending flag
-};
-
-static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
- 0xff, 0, //ending flag
-};
-
-static struct lcd_extern_config_s ext_config[LCD_EXTERN_NUM_MAX] = {
- {
- .index = 0,
- .name = "ext_default",
- .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 0, /* 0=disable, 1=enable */
- .i2c_addr = 0x1c, /* 7bit i2c address */
- .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for invalid */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- { /* P070ACB_FT */
- .index = 1,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- /*we define initial codes in panel.dtsi*/
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- { /* KD070D82_FT */
- .index = 2,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- /*we define initial codes in panel.dtsi*/
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- { /* TV070WSM_FT */
- .index = 3,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- /*we define initial codes in panel.dtsi*/
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
-
- {
- .index = LCD_EXTERN_INDEX_INVALID,
- },
-};
-
-#endif
-
diff --git a/board/amlogic/sm1_elaine_p1/pwm_table.c b/board/amlogic/sm1_elaine_p1/pwm_table.c
deleted file mode 100755
index 18dc638..0000000
--- a/board/amlogic/sm1_elaine_p1/pwm_table.c
+++ /dev/null
@@ -1,71 +0,0 @@
-#include <common.h>
-
-const int pwm_cal_voltage_table[][2] = {
- { 0x1c0000, 860},
- { 0x1b0001, 870},
- { 0x1a0002, 880},
- { 0x190003, 890},
- { 0x180004, 900},
- { 0x170005, 910},
- { 0x160006, 920},
- { 0x150007, 930},
- { 0x140008, 940},
- { 0x130009, 950},
- { 0x12000a, 960},
- { 0x11000b, 970},
- { 0x10000c, 980},
- { 0x0f000d, 990},
- { 0x0e000e, 1000},
- { 0x0d000f, 1010},
- { 0x0c0010, 1020},
- { 0x0b0011, 1030},
- { 0x0a0012, 1040},
- { 0x090013, 1050},
- { 0x080014, 1060},
- { 0x070015, 1070},
- { 0x060016, 1080},
- { 0x050017, 1090},
- { 0x040018, 1100},
- { 0x030019, 1110},
- { 0x02001a, 1120},
- { 0x01001b, 1130},
- { 0x00001c, 1140}
-};
-const int pwm_cal_voltage_table_ee[][2] = {
- { 0x1c0000, 810},
- { 0x1b0001, 820},
- { 0x1a0002, 830},
- { 0x190003, 840},
- { 0x180004, 850},
- { 0x170005, 860},
- { 0x160006, 870},
- { 0x150007, 880},
- { 0x140008, 890},
- { 0x130009, 900},
- { 0x12000a, 910},
- { 0x11000b, 920},
- { 0x10000c, 930},
- { 0x0f000d, 940},
- { 0x0e000e, 950},
- { 0x0d000f, 960},
- { 0x0c0010, 970},
- { 0x0b0011, 980},
- { 0x0a0012, 990},
- { 0x090013, 1000},
- { 0x080014, 1010},
- { 0x070015, 1020},
- { 0x060016, 1030},
- { 0x050017, 1040},
- { 0x040018, 1050},
- { 0x030019, 1060},
- { 0x02001a, 1070},
- { 0x01001b, 1080},
- { 0x00001c, 1090}
-};
-
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
-int pwm_cal_voltage_table_size = ARRAY_SIZE(pwm_cal_voltage_table);
-int pwm_cal_voltage_table_ee_size = ARRAY_SIZE(pwm_cal_voltage_table_ee);
-
-
diff --git a/board/amlogic/sm1_elaine_p1/sm1_elaine_p1.c b/board/amlogic/sm1_elaine_p1/sm1_elaine_p1.c
deleted file mode 100755
index dccba64..0000000
--- a/board/amlogic/sm1_elaine_p1/sm1_elaine_p1.c
+++ /dev/null
@@ -1,1104 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_p1/sm1_elaine_p1.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <malloc.h>
-#include <errno.h>
-#include <environment.h>
-#include <fdt_support.h>
-#include <linux/libfdt.h>
-#include <asm/arch/cpu_id.h>
-#ifdef CONFIG_SYS_I2C_MESON
-#include <i2c.h>
-#include <dt-bindings/i2c/meson-i2c.h>
-#endif
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/pinctrl_init.h>
-#ifdef CONFIG_AML_VPU
-#include <amlogic/media/vpu/vpu.h>
-#endif
-#ifdef CONFIG_AML_VPP
-#include <amlogic/media/vpp/vpp.h>
-#endif
-#ifdef CONFIG_AML_V2_FACTORY_BURN
-#include <amlogic/aml_v2_burning.h>
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
-#ifdef CONFIG_AML_HDMITX
-#include <amlogic/media/vout/hdmitx.h>
-#endif
-#ifdef CONFIG_AML_LCD
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#endif
-#include <asm/arch/bl31_apis.h>
-#include <asm/arch/eth_setup.h>
-#include <phy.h>
-#include <linux/mtd/partitions.h>
-#include <linux/sizes.h>
-#include <asm-generic/gpio.h>
-#include <dm.h>
-#ifdef CONFIG_AML_SPIFC
-#include <amlogic/spifc.h>
-#endif
-#ifdef CONFIG_AML_SPICC
-#include <amlogic/spicc.h>
-#endif
-#include <asm/armv8/mmu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-int do_check_fdr_for_backlight_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-#if defined(CONFIG_NAND_FTS) || defined(CONFIG_MMC_FTS)
-#if defined(CONFIG_NAND_FTS)
- extern bool amlnf_is_inited(void);
- if(!amlnf_is_inited()) {
-#endif
-
-#if defined(CONFIG_MMC_FTS)
- extern bool amlmmc_is_inited(void);
- if (!amlmmc_is_inited()) {
-#endif
-
- return 0;
- }
-
- flash_ts_init();
-
- static const char *fts_key = "bootloader.recovery";
- static const char *fdr = "--wipe_data";
- static const int fdr_len = sizeof(fdr) - 1;
- int i;
-
- char fts_value[256] = { 0 };
- flash_ts_get(fts_key, fts_value, sizeof(fts_value));
- int fts_len = strnlen(fts_value, sizeof(fts_value));
- for (i = 0; i <= fts_len - fdr_len; i++) {
- if (0 == strncmp(fts_value+i, fdr, fdr_len)) {
- printf("Reset persistent brightness.\n");
- writel(0, AO_RTI_STICKY_REG2);
- break;
- }
- }
-#endif
-
- return 0;
-}
-
-U_BOOT_CMD(
- check_fdr_for_backlight_brightness, 1, 0, do_check_fdr_for_backlight_brightness,
- "check FDR for backlight brightness",
- " This command will clear backlight brightness level stored in the sticky register when doing FDR\n"
-);
-
-int serial_set_pin_port(unsigned long port_base)
-{
- //UART in "Always On Module"
- //GPIOAO_0==tx,GPIOAO_1==rx
- //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
- return 0;
-}
-
-//SOC_VDDCPU_DVFS0
-//#define VDD_CPU_DVFS0_EN_1 GPIOEE(GPIOZ_13)
-#define VDD_CPU_DVFS0_EN_1_NAME "GPIOZ_13"
-
-//SOC_VDDEE_DVFS0
-//#define VDD_GPU_DVFS0_EN_1 GPIOEE(GPIOA_13)
-#define VDD_GPU_DVFS0_EN_1_NAME "GPIOA_13"
-
-//SOC_VDDEE_DVFS1
-//#define VDD_GPU_DVFS1_EN_1 GPIOEE(GPIOZ_0)
-#define VDD_GPU_DVFS1_EN_1_NAME "GPIOZ_0"
-
-/* setting gpio output/input, and setting High/low level */
-static void gpio_func_set(bool enable, const char* gpio_name, int direction)
-{
- int ret;
- struct gpio_desc gpio_set_desc;
-
- ret = dm_gpio_lookup_name(gpio_name, &gpio_set_desc);
- if (ret) {
- printf("%s: not found\n", gpio_name);
- return ret;
- }
-
- ret = dm_gpio_request(&gpio_set_desc, gpio_name);
- if (ret && ret != -EBUSY) {
- printf("gpio: requesting pin %s failed\n", gpio_name);
- return;
- }
- //gpio_direction_output(BL_ENABLE_PIN, enable ? 1 : 0);
- ret = dm_gpio_set_dir_flags(&gpio_set_desc, direction);
- if (ret) {
- printf("set direction failed\n");
- return ret;
- }
-
- if ( direction == GPIOD_IS_OUT)
- dm_gpio_set_value(&gpio_set_desc, enable ? 1 : 0);
-}
-static void CPU_GPU_Voltage_init(void)
-{
- int ret;
- // setting GPIOZ_13 output & High
- gpio_func_set(1, VDD_CPU_DVFS0_EN_1_NAME, GPIOD_IS_OUT);
-
- //GPU , setting GPIOA_13 output & low
- gpio_func_set(0, VDD_GPU_DVFS0_EN_1_NAME, GPIOD_IS_OUT);
-
- // setting GPIOZ_0 output & low
- gpio_func_set(1, VDD_GPU_DVFS1_EN_1_NAME, GPIOD_IS_OUT);
-}
-
-// Disable GPIOZ_2, GPIOZ_3, GPIOZ_7, GPIOZ_8, GPIOZ_0, GPIOAO_4's pull-up
-// so the mute switch and HW id can be read.
-static void gpio_disable_pull(void)
-{
- int ret;
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 2)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 7)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 8)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 3)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(AO_RTI_PULL_UP_EN_REG);
- writel(ret & (~(1 << 4)), AO_RTI_PULL_UP_EN_REG);
-}
-
-int do_get_elaine_hw_id(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- unsigned int hw_id = 0, ret = 0;
- char hw_id_str[8] = {0}; // eg: 0x0A
-
- // Reading from highest bit to lowest bit
- // HW_ID_4: GPIOAO_4
- ret = readl(P_AO_GPIO_I);
- hw_id |= (ret & (1<<4)) >> 4;
- hw_id = hw_id << 1;
-
- // HW_ID_3: GPIOZ_0
- ret = readl(P_PREG_PAD_GPIO4_I);
- hw_id |= (ret & 1);
- hw_id = hw_id << 1;
-
- // HW_ID_2: GPIOZ_3
- ret = readl(P_PREG_PAD_GPIO4_I);
- hw_id |= (ret & (1<<3)) >> 3;
- hw_id = hw_id << 1;
-
- // HW_ID_1: GPIOZ_8
- ret = readl(P_PREG_PAD_GPIO4_I);
- hw_id |= (ret & (1<<8)) >> 8;
- hw_id = hw_id << 1;
-
- // HW_ID_0: GPIOZ_7
- ret = readl(P_PREG_PAD_GPIO4_I);
- hw_id |= (ret & (1<<7)) >> 7;
-
- snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id);
- env_set("hw_id", hw_id_str);
- return 0;
-}
-
-U_BOOT_CMD(
- get_elaine_hw_id, 1, 0, do_get_elaine_hw_id,
- "get elaine's HW_ID and env_set 'hw_id'\n",
- "get_elaine_hw_id"
-);
-
-
-
-//SOC_DISP_ID
-//#define DISP_ID_PIN GPIOEE(GPIOH_5)
-#define DISP_ID_PIN_NAME "GPIOH_5"
-
-static void panel_detect_init(void)
-{
- // setting GPIOH_5 output & High
- gpio_func_set(1, DISP_ID_PIN_NAME, GPIOD_IS_IN);
-}
-
-//SOC_BL_ENABLE
-//#define BL_ENABLE_PIN GPIOEE(GPIOA_10)
-#define BL_ENABLE_PIN_NAME "GPIOA_10"
-
-static void enable_backlight(bool enable)
-{
- // setting GPIOH_5 output & High
- gpio_func_set(enable, BL_ENABLE_PIN_NAME, GPIOD_IS_OUT);
-}
-
-int dram_init(void)
-{
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-/* secondary_boot_func
- * this function should be write with asm, here, is is only for compiling pass
- * */
-void secondary_boot_func(void)
-{
-}
-
-#if CONFIG_AML_SD_EMMC
-#include <mmc.h>
-#include <asm/arch/sd_emmc.h>
-static int sd_emmc_init(unsigned port)
-{
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
- //todo add card detect
- /* check card detect */
- clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
- setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
- setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
- setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
- break;
- case SDIO_PORT_C:
- //enable pull up
- //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
- break;
- default:
- break;
- }
-
- return cpu_sd_emmc_init(port);
-}
-
-extern unsigned sd_debug_board_1bit_flag;
-
-static void sd_emmc_pwr_prepare(unsigned port)
-{
- cpu_sd_emmc_pwr_prepare(port);
-}
-
-static void sd_emmc_pwr_on(unsigned port)
-{
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
-// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
-// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
- /// @todo NOT FINISH
- break;
- case SDIO_PORT_C:
- break;
- default:
- break;
- }
- return;
-}
-static void sd_emmc_pwr_off(unsigned port)
-{
- /// @todo NOT FINISH
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
-// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
-// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
- break;
- case SDIO_PORT_C:
- break;
- default:
- break;
- }
- return;
-}
-
-// #define CONFIG_TSD 1
-static void board_mmc_register(unsigned port)
-{
- struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
- if (aml_priv == NULL)
- return;
-
- aml_priv->sd_emmc_init=sd_emmc_init;
- aml_priv->sd_emmc_detect=sd_emmc_detect;
- aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
- aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
- aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
- aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
-
- if (NULL == aml_priv->desc_buf)
- printf(" desc_buf Dma alloc Fail!\n");
- else
- printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
-
- sd_emmc_register(aml_priv);
-}
-int board_mmc_init(bd_t *bis)
-{
-#ifdef CONFIG_VLSI_EMULATOR
- //board_mmc_register(SDIO_PORT_A);
-#else
- //board_mmc_register(SDIO_PORT_B);
-#endif
- board_mmc_register(SDIO_PORT_B);
- board_mmc_register(SDIO_PORT_C);
-// board_mmc_register(SDIO_PORT_B1);
- return 0;
-}
-#endif
-
-/* Skip the first line and parse one uint
- * Return negative if not found */
-int parse_calibration_file_string(const char *str)
-{
- if (str == NULL)
- return -EINVAL;
-
- str = strchr(str, '\n');
- if (str == NULL)
- return -EINVAL;
- ++str;
-
- return simple_strtoul(str, NULL, 10);
-}
-
-/* If zero, this value has not been set and the default brightness should not be
- * overwritten. To store zero, store a non-zero value with its bottom 12 bits
- * all zero, like 0x1000.
- */
-int get_persistent_brightness(void)
-{
- u32 brightness_sticky_val = readl(AO_RTI_STICKY_REG2);
- if (brightness_sticky_val != 0)
- return (brightness_sticky_val & 0x0fff) >> 1;
- return -1;
-}
-
-int do_configure_backlight(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
-#ifdef CONFIG_SYS_I2C_MESON
- int ret, i, attempt;
- const int retries = 3;
- char *addr_cal;
- int calibrated_current, persistent_brightness;
-
- /* Values to write:
- * [0]: Brightness register control only, backlight enabled
- * [1-2]: Standby disabled, 20mA MAX_CURRENT, CURRENT scale 1/2
- * [3]: Enable undervoltage protection at 5.2 V, "disable" backlight
- * (i2c only), disable set resistors
- * [4]: 9.6kHz PWM rate, 3 phase drivers
- * [5]: EN_DRV3, EN_DRV2, boost inductor current limit = 1.6 A
- * [6]: VBOOST_MAX = 25 V, JUMP_EN = 0
- * [7]: STEP_UP = 105 mV, STEP_DN = 105 mV, LED_FAULT_TH = 3V,
- * LED_COMP_HYST = DRIVER_HEADROOM + 750 mV
- * [8-9]: 12-bit brightness (default: 100%)
- * Important: Write brightness last to apply current calibration */
- const __u8 addrs[] = {0x01, 0xa0, 0xa1, 0xa2, 0xa5, 0xa7, 0xa9, 0xae,
- 0x10, 0x11};
- __u8 values[] = {0x85, 0xff, 0x37, 0x30, 0x54, 0xf4, 0x60, 0x09, 0xff,
- 0x0f};
- const int n_bytes = sizeof(values)/sizeof(values[0]);
- struct udevice *bl_devp = NULL;
-
- if (argc > 2) {
- printf("%s: Too many args: %d\n", __func__, argc);
- return CMD_RET_USAGE;
- }
-
- if (argc == 2) {
- addr_cal = (char *)simple_strtoul(argv[1], NULL, 16);
- calibrated_current = parse_calibration_file_string(addr_cal);
- if (calibrated_current >= 0 && calibrated_current <= 4095) {
- /* CURRENT_LSB */
- values[1] = 0xff & calibrated_current;
- /* CURRENT_MSB */
- values[2] = (values[2] & 0xf0) |
- (0x0f & (calibrated_current >> 8));
- }
- }
-
- // Apply persistent brightness if found
- persistent_brightness = get_persistent_brightness();
- if (persistent_brightness >= 0) {
- pr_info("Applying persistent_brightness=%d\n", persistent_brightness);
- /* Get LSB and MSB */
- values[n_bytes - 2] = persistent_brightness & 0xff;
- values[n_bytes - 1] = persistent_brightness >> 8 & 0x0f;
- } else {
- pr_info("Persistent_brightness not set\n");
- }
-
- enable_backlight(true);
-
- ret = i2c_get_chip_for_busnum(MESON_I2C_M3, 0X2c, 1, &bl_devp);
- if (ret) {
- printf("%s(%d):i2c get bus fail!\n", __func__, __LINE__);
- return -1;
- }
- //i2c_set_bus_num(AML_I2C_MASTER_D);
- for (i = 0; i < n_bytes; ++i) {
- for (attempt = 0; attempt < retries; ++attempt) {
- ret = dm_i2c_write(bl_devp, addrs[i], &values[i], 1);
- if (ret)
- printf("%s: Attempt=%d to write byte=0x%02x to reg=0x%02x of backlight failed\n",
- __func__, attempt, values[i], addrs[i]);
- else
- break;
- }
- }
-
- return ret;
-#else
- enable_backlight(true);
-
- return 0;
-#endif /* CONFIG_SYS_I2C_MESON */
-}
-
-U_BOOT_CMD(
- configure_backlight, 2, 0, do_configure_backlight,
- "configures the lp8556 backlight",
- "Usage: configure_backlight [calibration_string_addr]\n"\
- " Sets up required parameters of the backlight.\n"\
- " Default calibration is 100%.\n"\
- " calibration_str_addr (optional):\n"\
- " Address of calibration file string to parse.\n"
-);
-
-#ifdef CONFIG_AML_LCD
-/* Parses one line of the gamma calibration file. */
-/* Returns true on success. */
-#define GAMMA_SIZE (256)
-bool parse_gamma_string(const char *str, uint16_t *table)
-{
- char buf[4] = {'\0'};
- int i;
-
- for (i = 0; i < GAMMA_SIZE; ++i) {
- strncpy(buf, &str[3 * i], 3);
- table[i] = simple_strtol(buf, NULL, 16);
- }
-
- return true;
-}
-
-/* Check header then parse RGB gamma tables */
-/* Returns negative value on error */
-int parse_gamma_calibration_file_string(const char *str, u16 *r, u16 *g, u16 *b)
-{
- static const char supported_header_prefix[] = "Gamma Calibration 1.";
- static const int length = sizeof(supported_header_prefix) - 1;
- char *tables[3] = {r, g, b};
- const char *start, *end;
- int i;
-
- if (!str)
- return -EINVAL;
-
- // Check header prefix - only care about major version.
- if (strncmp(str, supported_header_prefix, length) != 0) {
- printf("Unknown gamma header: \"%.*s\"\n", length, str);
- return -EINVAL;
- }
-
- // Parse all three tables
- end = strchr(str, '\n');
- for (i = 0; i < 3; ++i) {
- start = end + 1;
- end = strchr(start, '\n');
-
- if ((end - start) / 3 != GAMMA_SIZE) {
- printf("Gamma table has invalid length.\n");
- return -EINVAL;
- }
- if (!parse_gamma_string(start, tables[i])) {
- printf("Could not parse gamma table %d.\n", i);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-#endif // CONFIG_AML_LCD
-
-int do_configure_gamma(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
-#ifdef CONFIG_AML_LCD
- static const int N_CHAN = 3;
- char *addr_cal;
- u16 gamma_tables[N_CHAN][GAMMA_SIZE];
- int i, j;
-
- if (argc == 1) {
- // Set to default
- for (i = 0; i < N_CHAN; ++i) {
- for (j = 0; j < GAMMA_SIZE; ++j)
- gamma_tables[i][j] = j << 2; /* 10-bit */
- }
- } else if (argc == 2) {
- // Load from passed file string
- addr_cal = (char *)simple_strtoul(argv[1], NULL, 16);
- if (parse_gamma_calibration_file_string(addr_cal,
- &gamma_tables[0],
- &gamma_tables[1],
- &gamma_tables[2]) != 0)
- return -EINVAL; // Error logged
- } else {
- return CMD_RET_USAGE;
- }
-
- vpp_set_rgb_gamma_table(&gamma_tables[0], &gamma_tables[1],
- &gamma_tables[2]);
-#endif // CONFIG_AML_LCD
- return 0;
-}
-
-U_BOOT_CMD(configure_gamma, 2, 0, do_configure_gamma,
- "configures gamma the gamma tables with the provided calibration\n",
- "Usage: configure_gamma [calibration_string_addr]\n"\
- " Applies the provided calibration file.\n"\
- " If a file is not provided, sets tables to default.\n"\
- " calibration_str_addr (optional):\n"\
- " Address of the calibration file string to parse.\n"
-);
-
-int do_get_chiptype(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- char *type[] = {"SS", "TT", "FF"};
- unsigned int dvfs_id = aml_get_dvfs_id();
- printf("get dvfs_id:%d\n", dvfs_id);
- if (dvfs_id > 2) {
- printf("fail to get dvfs id\n");
- dvfs_id = 0;
- }
- env_set("chip_type", type[dvfs_id]);
- return 0;
-}
-U_BOOT_CMD(get_chiptype, 1, 0, do_get_chiptype,
- "get elaine's chip type and env_set 'chip_type'\n",
- "get_chiptype"
-);
-
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
-int board_early_init_f(void){
- /*add board early init function here*/
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
-#include <asm/arch/usb-v2.h>
-#include <asm/arch/gpio.h>
-#define CONFIG_GXL_USB_U2_PORT_NUM 2
-
-#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
-#define CONFIG_GXL_USB_U3_PORT_NUM 1
-#else
-#define CONFIG_GXL_USB_U3_PORT_NUM 0
-#endif
-
-static void gpio_set_vbus_power(char is_power_on)
-{
- int ret;
-
- ret = gpio_request(CONFIG_USB_GPIO_PWR,
- CONFIG_USB_GPIO_PWR_NAME);
- if (ret && ret != -EBUSY) {
- printf("gpio: requesting pin %u failed\n",
- CONFIG_USB_GPIO_PWR);
- return;
- }
-
- if (is_power_on) {
- gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
- } else {
- gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
- }
-}
-
-struct amlogic_usb_config g_usb_config_GXL_skt={
- CONFIG_GXL_XHCI_BASE,
- USB_ID_MODE_HARDWARE,
- gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
- CONFIG_GXL_USB_PHY2_BASE,
- CONFIG_GXL_USB_PHY3_BASE,
- CONFIG_GXL_USB_U2_PORT_NUM,
- CONFIG_GXL_USB_U3_PORT_NUM,
- .usb_phy2_pll_base_addr = {
- CONFIG_USB_PHY_20,
- CONFIG_USB_PHY_21,
- }
-};
-
-#endif /*CONFIG_USB_XHCI_AMLOGIC*/
-
-#ifdef CONFIG_AML_HDMITX20
-static void hdmi_tx_set_hdmi_5v(void)
-{
-}
-#endif
-
-/*
- * mtd nand partition table, only care the size!
- * offset will be calculated by nand driver.
- */
-#ifdef CONFIG_AML_MTD
-static struct mtd_partition normal_partition_info[] = {
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- /* MUST NOT CHANGE this part unless u know what you are doing!
- * inherent parition for descrete bootloader to store fip
- * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
- * name must be same with TPL_PART_NAME
- */
- {
- .name = "tpl",
- .offset = 0,
- .size = 0,
- },
-#endif
- {
- .name = "fts",
- .offset = 0,
- .size = 1*SZ_1M,
- },
- {
- .name = "factory",
- .offset = 0,
- .size = 8*SZ_1M,
- },
- {
- .name = "recovery",
- .offset = 0,
- .size = 16*SZ_1M,
- },
- {
- .name = "boot",
- .offset = 0,
- .size = 16*SZ_1M,
- },
- {
- .name = "system",
- .offset = 0,
- .size = 220*SZ_1M,
- },
- /* last partition get the rest capacity */
- {
- .name = "cache",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-struct mtd_partition *get_aml_mtd_partition(void)
-{
- return normal_partition_info;
-}
-int get_aml_partition_count(void)
-{
- return ARRAY_SIZE(normal_partition_info);
-}
-#endif /* CONFIG_AML_MTD */
-
-#ifdef CONFIG_AML_SPIFC
-/*
- * BOOT_3: NOR_HOLDn:reg0[15:12]=3
- * BOOT_4: NOR_D:reg0[19:16]=3
- * BOOT_5: NOR_Q:reg0[23:20]=3
- * BOOT_6: NOR_C:reg0[27:24]=3
- * BOOT_7: NOR_WPn:reg0[31:28]=3
- * BOOT_14: NOR_CS:reg1[27:24]=3
- */
-#define SPIFC_NUM_CS 1
-static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
-
-static int spifc_pinctrl_enable(void *pinctrl, bool enable)
-{
- unsigned int val;
-
- val = readl(P_PERIPHS_PIN_MUX_0);
- val &= ~(0xfffff << 12);
- if (enable)
- val |= 0x33333 << 12;
- writel(val, P_PERIPHS_PIN_MUX_0);
-
- val = readl(P_PERIPHS_PIN_MUX_1);
- val &= ~(0xf << 24);
- writel(val, P_PERIPHS_PIN_MUX_1);
- return 0;
-}
-
-#if 0
-static const struct spifc_platdata spifc_platdata = {
- .reg = 0xffd14000,
- .mem_map = 0xf6000000,
- .pinctrl_enable = spifc_pinctrl_enable,
- .num_chipselect = SPIFC_NUM_CS,
- .cs_gpios = spifc_cs_gpios,
-};
-
-U_BOOT_DEVICE(spifc) = {
- .name = "spifc",
- .platdata = &spifc_platdata,
-};
-#endif
-#endif /* CONFIG_AML_SPIFC */
-
-#if 0
-#ifdef CONFIG_AML_SPICC
-/* generic config in arch gpio/clock.c */
-extern int spicc1_clk_set_rate(int rate);
-extern int spicc1_clk_enable(bool enable);
-extern int spicc1_pinctrl_enable(bool enable);
-
-static const struct spicc_platdata spicc1_platdata = {
- .compatible = "amlogic,meson-g12a-spicc",
- .reg = (void __iomem *)0xffd15000,
- .clk_rate = 666666666,
- .clk_set_rate = spicc1_clk_set_rate,
- .clk_enable = spicc1_clk_enable,
- .pinctrl_enable = spicc1_pinctrl_enable,
- /* case one slave without cs: {"no_cs", 0} */
- .cs_gpio_names = {"GPIOH_6", 0},
-};
-
-U_BOOT_DEVICE(spicc1) = {
- .name = "spicc",
- .platdata = &spicc1_platdata,
-};
-#endif /* CONFIG_AML_SPICC */
-#endif
-
-extern void aml_pwm_cal_init(int mode);
-
-int board_init(void)
-{
- printf("board init\n");
-
- /*in kernel P_RESET1_LEVEL has been clear,
- * uboot need set these bits about usb,
- * otherwise the usb has problem.
- */
- *(volatile uint32_t *)P_RESET1_LEVEL |= (3 << 16);
- //CPU_GPU_Voltage_init();
- enable_backlight(false);
- panel_detect_init();
-//Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
-//As NOT NEED other board init If USB BOOT MODE
-#ifdef CONFIG_AML_V2_FACTORY_BURN
- if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
- aml_try_factory_usb_burning(0, gd->bd);
- }
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
-
- pinctrl_devices_active(PIN_CONTROLLER_NUM);
-#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
- board_usb_pll_disable(&g_usb_config_GXL_skt);
- board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
-#endif /*CONFIG_USB_XHCI_AMLOGIC*/
-
- /* TODO(b/110040521): This is the earliest the backlight can be started,
- * but the LCD is not running yet. */
-
-#if 0
- aml_pwm_cal_init(0);
-#endif//
-#ifdef CONFIG_AML_NAND
- extern int amlnf_init(unsigned char flag);
- amlnf_init(0);
-#endif
- gpio_disable_pull();
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- printf("board late init\n");
- run_command("mmc dev 1", 0);
- run_command("run detect_panel", 0);
-#if 0
- //update env before anyone using it
- run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
- "if test ${reboot_mode} = factory_reset; then "\
- "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
- run_command("if itest ${upgrade_step} == 1; then "\
- "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
- /*add board late init function here*/
-#ifndef DTB_BIND_KERNEL
- int ret;
- ret = run_command("store dtb read $dtb_mem_addr", 1);
- if (ret) {
- printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
-#ifdef CONFIG_DTB_MEM_ADDR
- char cmd[64];
- printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
- sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
- ret = run_command(cmd, 1);
- if (ret) {
- printf("%s(): %s fail\n", __func__, cmd);
- }
-#endif
- }
-#elif defined(CONFIG_DTB_MEM_ADDR)
- {
- char cmd[128];
- int ret;
- if (!getenv("dtb_mem_addr")) {
- sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
- run_command(cmd, 0);
- }
- sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
- ret = run_command(cmd, 0);
- if (ret) {
- printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
- }
- }
-#endif// #ifndef DTB_BIND_KERNEL
-
- /* load unifykey */
- run_command("keyunify init 0x1234", 0);
-#endif
-/*open vpu hdmitx and cvbs driver*/
-#ifdef CONFIG_AML_VPU
- vpu_probe();
-#endif
-
-#ifdef CONFIG_AML_VPP
- vpp_init();
-#endif
-
-#ifdef CONFIG_AML_HDMITX
- hdmi_tx_init();
-#endif
-#ifdef CONFIG_AML_CVBS
- run_command("cvbs init", 0);
-#endif
-#ifdef CONFIG_AML_LCD
- lcd_probe();
-#endif
-
-#ifdef CONFIG_AML_V2_FACTORY_BURN
- if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
- aml_try_factory_usb_burning(1, gd->bd);
- aml_try_factory_sdcard_burning(0, gd->bd);
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
- return 0;
-}
-#endif
-
-#ifdef CONFIG_AML_TINY_USBTOOL
-int usb_get_update_result(void)
-{
- unsigned long upgrade_step;
- upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
- printf("upgrade_step = %d\n", (int)upgrade_step);
- if (upgrade_step == 1)
- {
- run_command("defenv", 1);
- run_command("env_set upgrade_step 2", 1);
- run_command("saveenv", 1);
- return 0;
- }
- else
- {
- return -1;
- }
-}
-#endif
-
-phys_size_t get_effective_memsize(void)
-{
- // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
-#if defined(CONFIG_SYS_MEM_TOP_HIDE)
- return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
-#else
- return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
-#endif
-}
-
-#ifdef CONFIG_MULTI_DTB
-int checkhw(char * name)
-{
- /*
- * read board hw id
- * set and select the dts according the board hw id.
- *
- * hwid = 1 p321 v1
- * hwid = 2 p321 v2
- */
- unsigned int hwid = 1;
- char loc_name[64] = {0};
-
- /* read hwid */
- hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
-
- printf("checkhw: hwid = %d\n", hwid);
-
-
- switch (hwid) {
- case 1:
- strcpy(loc_name, "txl_p321_v1\0");
- break;
- case 2:
- strcpy(loc_name, "txl_p321_v2\0");
- break;
- default:
- strcpy(loc_name, "txl_p321_v1");
- break;
- }
- strcpy(name, loc_name);
- env_set("aml_dt", loc_name);
- return 0;
-}
-#endif
-
-/* workaround for VDDEE issue */
-/* VCCK PWM table */
-#define VCCK_VAL_REG_800 0x00150007
-#define VCCK_VAL_REG_810 0x00140008
-#define VCCK_VAL_REG_820 0x00130009
-#define VCCK_VAL_REG_830 0x0012000a
-#define VCCK_VAL_REG_840 0x0011000b
-#define VCCK_VAL_REG_850 0x0010000c
-#define VCCK_VAL_REG_860 0x000f000d
-#define VCCK_VAL_REG_870 0x000e000e
-#define VCCK_VAL_REG_880 0x000d000f
-#define VCCK_VAL_REG_890 0x000c0010
-#define VCCK_VAL_REG_900 0x000b0011
-#define VCCK_VAL_REG_910 0x000a0012
-#define VCCK_VAL_REG_920 0x00090013
-#define VCCK_VAL_REG_930 0x00080014
-#define VCCK_VAL_REG_940 0x00070015
-#define VCCK_VAL_REG_950 0x00060016
-#define VCCK_VAL_REG_960 0x00050017
-#define VCCK_VAL_REG_970 0x00040018
-#define VCCK_VAL_REG_980 0x00030019
-#define VCCK_VAL_REG_990 0x0002001a
-#define VCCK_VAL_REG_1000 0x0001001b
-#define VCCK_VAL_REG_1010 0x0000001c
-#define VCCK_VAL_REG_DEFAULT 0x00500008
-
-/* VDDEE PWM table */
-#define VDDEE_VAL_REG_800 0x0010000c
-#define VDDEE_VAL_REG_810 0x000f000d
-#define VDDEE_VAL_REG_820 0x000e000e
-#define VDDEE_VAL_REG_830 0x000d000f
-#define VDDEE_VAL_REG_840 0x000c0010
-#define VDDEE_VAL_REG_850 0x000b0011
-#define VDDEE_VAL_REG_860 0x000a0012
-#define VDDEE_VAL_REG_870 0x00090013
-#define VDDEE_VAL_REG_880 0x00080014
-#define VDDEE_VAL_REG_890 0x00070015
-#define VDDEE_VAL_REG_900 0x00060016
-#define VDDEE_VAL_REG_910 0x00050017
-#define VDDEE_VAL_REG_920 0x00040018
-#define VDDEE_VAL_REG_930 0x00030019
-#define VDDEE_VAL_REG_940 0x0002001a
-#define VDDEE_VAL_REG_950 0x0001001b
-#define VDDEE_VAL_REG_960 0x0000001c
-#define VDDEE_VAL_REG_DEFAULT 0x00500008
-
-void reset_misc(void)
-{
- unsigned int value;
-
- /* adjust VDDCPU to Hiz value step by step */
- writel(VCCK_VAL_REG_830, AO_PWM_PWM_D);
- udelay(1);
- writel(VCCK_VAL_REG_860, AO_PWM_PWM_D);
- udelay(1);
-
- /* GPIOE_0 & GPIOE_1 to gpio pin */
- value = readl(AO_RTI_PINMUX_REG1);
- value &= ~(0xff << 16);
- writel(value, AO_RTI_PINMUX_REG1);
-
- /* disable pwm_ao_b - VDDEE */
- value = readl(AO_PWM_MISC_REG_AB);
- value &= ~((0x1 << 1) | (0x1 << 23));
- writel(value, AO_PWM_MISC_REG_AB);
- writel(VDDEE_VAL_REG_DEFAULT, AO_PWM_PWM_B);
-
- /* disable pwm_ao_d - VDDCPU_B*/
- value = readl(AO_PWM_MISC_REG_CD);
- value &= ~((0x1 << 1) | (0x1 << 23));
- writel(value, AO_PWM_MISC_REG_CD);
- writel(VCCK_VAL_REG_DEFAULT, AO_PWM_PWM_D);
-}
-
-static struct mm_region bd_mem_map[] = {
- {
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = bd_mem_map;
-
-void board_nand_init(void) {
- printf("board_nand_init\n");
- return;
-}
-
-int print_cpuinfo(void) {
- printf("print_cpuinfo\n");
- return 0;
-}
-
-int mach_cpu_init(void) {
- printf("mach_cpu_init\n");
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- /* eg: bl31/32 rsv */
- return 0;
-}
diff --git a/board/amlogic/sm1_elaine_p1/zircon.c b/board/amlogic/sm1_elaine_p1/zircon.c
deleted file mode 100644
index 8e6888f..0000000
--- a/board/amlogic/sm1_elaine_p1/zircon.c
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * Copyright (c) 2018 The Fuchsia Authors
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common.h>
-#include <linux/mtd/partitions.h>
-#include <nand.h>
-#include <part.h>
-#include <emmc_storage.h>
-#include <zircon/zircon.h>
-
-#define PDEV_VID_GOOGLE 3
-#define PDEV_PID_ASTRO 3
-
-#define NVRAM_LENGTH (8 * 1024)
-
-const char* BOOTLOADER_VERSION = "zircon-bootloader=0.10";
-
-static const zbi_cpu_config_t cpu_config = {
- .cluster_count = 1,
- .clusters = {
- {
- .cpu_count = 4,
- },
- },
-};
-
-static const zbi_mem_range_t mem_config[] = {
- {
- .type = ZBI_MEM_RANGE_RAM,
- .length = 0x60000000, // 1.5 GB
- },
- {
- .type = ZBI_MEM_RANGE_PERIPHERAL,
- .paddr = 0xf5800000,
- .length = 0x0a800000,
- },
- // secmon_reserved:linux,secmon
- {
- .type = ZBI_MEM_RANGE_RESERVED,
- .paddr = 0x05000000,
- .length = 0x2400000,
- },
- // logo_reserved:linux,meson-fb
- {
- .type = ZBI_MEM_RANGE_RESERVED,
- .paddr = 0x5f800000,
- .length = 0x800000,
- },
-};
-
-static const dcfg_simple_t uart_driver = {
- .mmio_phys = 0xff803000,
- .irq = 225,
-};
-
-static const dcfg_arm_gicv2_driver_t gicv2_driver = {
- .mmio_phys = 0xffc00000,
- .gicd_offset = 0x1000,
- .gicc_offset = 0x2000,
- .gich_offset = 0x4000,
- .gicv_offset = 0x6000,
- .ipi_base = 5,
-};
-
-static const dcfg_arm_psci_driver_t psci_driver = {
- .use_hvc = false,
- .reboot_args = { 1, 0, 0 },
- .reboot_bootloader_args = { 4, 0, 0 },
- .reboot_recovery_args = { 2, 0, 0 },
-};
-
-static const dcfg_arm_generic_timer_driver_t timer_driver = {
- .irq_phys = 30,
-};
-
-static const zbi_platform_id_t platform_id = {
- .vid = PDEV_VID_GOOGLE,
- .pid = PDEV_PID_ASTRO,
- .board_name = "astro",
-};
-
-enum {
- PART_TPL,
- PART_FTS,
- PART_FACTORY,
- PART_ZIRCON_B,
- PART_ZIRCON_A,
- PART_ZIRCON_R,
- PART_FVM,
- PART_SYS_CONFIG,
- PART_MIGRATION,
- PART_COUNT,
-};
-
-#define RECOVERY_SIZE (16 * 1024 * 1024)
-#define SYS_CONFIG_SIZE (1 * 1024 * 1024)
-#define MIGRATION_SIZE (3 * 1024 * 1024)
-
-static zbi_partition_map_t partition_map = {
- // .block_count filled in below
- // .block_size filled in below
- .guid = {},
- .partition_count = PART_COUNT,
- .partitions = {
- {
- .type_guid = GUID_BOOTLOADER_VALUE,
- .name = "tpl",
- },
- {
- .name = "fts",
- },
- {
- .name = "factory",
- },
- {
- .type_guid = GUID_ZIRCON_R_VALUE,
- .name = "zircon-r",
- },
- {
- .type_guid = GUID_ZIRCON_A_VALUE,
- .name = "zircon-a",
- },
- {
- .type_guid = GUID_ZIRCON_B_VALUE,
- .name = "zircon-b",
- },
- {
- .type_guid = GUID_FVM_VALUE,
- .name = "fvm",
- },
- {
- .type_guid = GUID_SYS_CONFIG_VALUE,
- .name = "sys-config",
- },
- {
- .name = "migration",
- },
- },
-};
-
-extern struct mtd_partition *get_aml_mtd_partition(void);
-extern int get_aml_partition_count(void);
-
-static void add_partition_map(zbi_header_t* zbi) {
- struct mtd_partition* tpl_part = NULL;
- struct mtd_partition* fts_part = NULL;
- struct mtd_partition* factory_part = NULL;
- struct mtd_partition* recovery_part = NULL;
- struct mtd_partition* boot_part = NULL;
- struct mtd_partition* system_part = NULL;
- struct mtd_partition* partitions = get_aml_mtd_partition();
- int partition_count = get_aml_partition_count();
- int i;
-
- for (i = 0; i < partition_count; i++) {
- struct mtd_partition* part = &partitions[i];
- if (!strcmp("tpl", part->name)) {
- tpl_part = part;
- } else if (!strcmp("fts", part->name)) {
- fts_part = part;
- } else if (!strcmp("factory", part->name)) {
- factory_part = part;
- } else if (!strcmp("recovery", part->name)) {
- recovery_part = part;
- } else if (!strcmp("boot", part->name)) {
- boot_part = part;
- } else if (!strcmp("system", part->name)) {
- system_part = part;
- }
- }
-
- if (!tpl_part) {
- printf("could not find tpl partition\n");
- return;
- }
- if (!fts_part) {
- printf("could not find fts partition\n");
- return;
- }
- if (!factory_part) {
- printf("could not find factory partition\n");
- return;
- }
- if (!recovery_part) {
- printf("could not find recovery partition\n");
- return;
- }
- if (!boot_part) {
- printf("could not find boot partition\n");
- return;
- }
- if (!system_part) {
- printf("could not find system partition\n");
- return;
- }
-
- uint32_t block_size = nand_info[1].writesize;
- uint64_t total_size = nand_info[1].size;
-
- partition_map.block_size = block_size;
- partition_map.block_count = total_size / block_size;
-
- // map tpl partition to BOOTLOADER
- partition_map.partitions[PART_TPL].first_block = tpl_part->offset / block_size;
- partition_map.partitions[PART_TPL].last_block =
- ((tpl_part->offset + tpl_part->size) / block_size) - 1;
- // map fts partition to "fts"
- partition_map.partitions[PART_FTS].first_block = fts_part->offset / block_size;
- partition_map.partitions[PART_FTS].last_block =
- ((fts_part->offset + fts_part->size) / block_size) - 1;
- // map factory partition to "factory"
- partition_map.partitions[PART_FACTORY].first_block = factory_part->offset / block_size;
- partition_map.partitions[PART_FACTORY].last_block =
- ((factory_part->offset + factory_part->size) / block_size) - 1;
- // map recovery partition to ZIRCON_B
- partition_map.partitions[PART_ZIRCON_B].first_block = recovery_part->offset / block_size;
- partition_map.partitions[PART_ZIRCON_B].last_block =
- ((recovery_part->offset + recovery_part->size) / block_size) - 1;
- // map boot partition to ZIRCON_A
- partition_map.partitions[PART_ZIRCON_A].first_block = boot_part->offset / block_size;
- partition_map.partitions[PART_ZIRCON_A].last_block =
- ((boot_part->offset + boot_part->size) / block_size) - 1;
- // ZIRCON_R partition at start of system
- partition_map.partitions[PART_ZIRCON_R].first_block = system_part->offset / block_size;
- partition_map.partitions[PART_ZIRCON_R].last_block =
- partition_map.partitions[PART_ZIRCON_R].first_block +
- (RECOVERY_SIZE / block_size) - 1;
- // FVM follows ZIRCON_R
- partition_map.partitions[PART_FVM].first_block =
- partition_map.partitions[PART_ZIRCON_R].last_block + 1;
- partition_map.partitions[PART_FVM].last_block =
- ((total_size - SYS_CONFIG_SIZE - MIGRATION_SIZE) / block_size) - 1;
- // SYS_CONFIG follows FVM
- partition_map.partitions[PART_SYS_CONFIG].first_block =
- partition_map.partitions[PART_FVM].last_block + 1;
- partition_map.partitions[PART_SYS_CONFIG].last_block =
- partition_map.partitions[PART_SYS_CONFIG].first_block +
- (SYS_CONFIG_SIZE / block_size) - 1;
- // MIGRATION follows SYS_CONFIG
- partition_map.partitions[PART_MIGRATION].first_block =
- partition_map.partitions[PART_SYS_CONFIG].last_block + 1;
- partition_map.partitions[PART_MIGRATION].last_block =
- partition_map.partitions[PART_MIGRATION].first_block +
- (MIGRATION_SIZE / block_size) - 1;
-
- printf("Zircon partitions:\n");
- for (i = 0; i < PART_COUNT; i++) {
- printf(" 0x%016llx - 0x%016llx : %s\n",
- partition_map.partitions[i].first_block * block_size,
- (partition_map.partitions[i].last_block + 1) * block_size,
- partition_map.partitions[i].name);
- }
-
- zircon_append_boot_item(zbi, ZBI_TYPE_DRV_PARTITION_MAP, 0, &partition_map,
- sizeof(zbi_partition_map_t) +
- partition_map.partition_count * sizeof(zbi_partition_t));
-}
-
-int zircon_preboot(zbi_header_t* zbi) {
- // add CPU configuration
- zircon_append_boot_item(zbi, ZBI_TYPE_CPU_CONFIG, 0, &cpu_config,
- sizeof(zbi_cpu_config_t) +
- sizeof(zbi_cpu_cluster_t) * cpu_config.cluster_count);
-
- // allocate crashlog save area before 0x5f800000-0x60000000 reserved area
- zbi_nvram_t nvram;
- nvram.base = 0x5f800000 - NVRAM_LENGTH;
- nvram.length = NVRAM_LENGTH;
- zircon_append_boot_item(zbi, ZBI_TYPE_NVRAM, 0, &nvram, sizeof(nvram));
-
- // add memory configuration
- zircon_append_boot_item(zbi, ZBI_TYPE_MEM_CONFIG, 0, &mem_config, sizeof(mem_config));
-
- // add kernel drivers
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_AMLOGIC_UART, &uart_driver,
- sizeof(uart_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_GIC_V2, &gicv2_driver,
- sizeof(gicv2_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_PSCI, &psci_driver,
- sizeof(psci_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_GENERIC_TIMER, &timer_driver,
- sizeof(timer_driver));
-
- zircon_append_boot_item(zbi, ZBI_TYPE_CMDLINE, 0, BOOTLOADER_VERSION, strlen(BOOTLOADER_VERSION) + 1);
-
- // add platform ID
- zircon_append_boot_item(zbi, ZBI_TYPE_PLATFORM_ID, 0, &platform_id, sizeof(platform_id));
-
- add_partition_map(zbi);
-
- return 0;
-}
diff --git a/board/amlogic/sm1_elaine_p2/Kconfig b/board/amlogic/sm1_elaine_p2/Kconfig
deleted file mode 100755
index db1a990..0000000
--- a/board/amlogic/sm1_elaine_p2/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-if TARGET_SM1_ELAINE_P2
-
-config SYS_SOC
- default "g12a"
-
-config SYS_BOARD
- default "sm1_elaine_p2"
-
-config SYS_VENDOR
- default "amlogic"
-
-config SYS_CONFIG_NAME
- default "sm1_elaine_p2"
-
-endif
diff --git a/board/amlogic/sm1_elaine_p2/Makefile b/board/amlogic/sm1_elaine_p2/Makefile
deleted file mode 100755
index fb7f59a..0000000
--- a/board/amlogic/sm1_elaine_p2/Makefile
+++ /dev/null
@@ -1,3 +0,0 @@
-
-obj-y += $(BOARD).o eth_setup.o
-obj-$(CONFIG_AML_LCD) += lcd.o
diff --git a/board/amlogic/sm1_elaine_p2/aml-user-key.sig b/board/amlogic/sm1_elaine_p2/aml-user-key.sig
deleted file mode 100755
index 2ceabc1..0000000
--- a/board/amlogic/sm1_elaine_p2/aml-user-key.sig
+++ /dev/null
Binary files differ
diff --git a/board/amlogic/sm1_elaine_p2/eth_setup.c b/board/amlogic/sm1_elaine_p2/eth_setup.c
deleted file mode 100755
index 6cbcd95..0000000
--- a/board/amlogic/sm1_elaine_p2/eth_setup.c
+++ /dev/null
@@ -1,51 +0,0 @@
-
-/*
- * board/amlogic/txl_skt_v1/eth_setup.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <malloc.h>
-#include <errno.h>
-#include <environment.h>
-#include <fdt_support.h>
-#include <linux/libfdt.h>
-#include <asm/arch/eth_setup.h>
-/*
- *
- *setup eth device board socket
- *
- */
-struct eth_board_socket* eth_board_setup(char *name){
- struct eth_board_socket* new_board;
- new_board= (struct eth_board_socket*) malloc(sizeof(struct eth_board_socket));
- if (NULL == new_board) return NULL;
- if (name != NULL) {
- new_board->name=(char*)malloc(strlen(name));
- strncpy(new_board->name,name,strlen(name));
- }else{
- new_board->name="gxb";
- }
-
- new_board->eth_pinmux_setup=NULL ;
- new_board->eth_clock_configure=NULL;
- new_board->eth_hw_reset=NULL;
- return new_board;
-}
-//pinmux HHI_GCLK_MPEG1[bit 3]
-//
diff --git a/board/amlogic/sm1_elaine_p2/firmware/ramdump.c b/board/amlogic/sm1_elaine_p2/firmware/ramdump.c
deleted file mode 100755
index e03dcd2..0000000
--- a/board/amlogic/sm1_elaine_p2/firmware/ramdump.c
+++ /dev/null
@@ -1,45 +0,0 @@
-
-#ifdef CONFIG_MDUMP_COMPRESS
-#include "ramdump.h"
-
-struct ram_compress_full __ramdump_data = {
- .store_phy_addr = (void *)CONFIG_COMPRESSED_DATA_ADDR,
- .full_memsize = CONFIG_DDR_TOTAL_SIZE,
- .section_count = CONFIG_COMPRESS_SECTION,
- .sections = {
- {
- /* memory afer compressed data address */
- .phy_addr = (void *)CONFIG_COMPRESSED_DATA_ADDR,
- .section_size = CONFIG_DDR_TOTAL_SIZE -
- CONFIG_COMPRESSED_DATA_ADDR,
- .section_index = 4,
- .compress_type = RAM_COMPRESS_NORMAL,
- },
- {
- /* memory before bl2 */
- .phy_addr = (void *)CONFIG_COMPRESS_START_ADDR,
- .section_size = CONFIG_BL2_IGNORE_ADDR -
- CONFIG_COMPRESS_START_ADDR,
- .section_index = 1,
- .compress_type = RAM_COMPRESS_NORMAL,
- },
- {
- /* memory in reserved bl2 */
- .phy_addr = (void *)CONFIG_BL2_IGNORE_ADDR,
- .section_size = CONFIG_BL2_IGNORE_SIZE,
- .section_index = 2,
- .compress_type = RAM_COMPRESS_SET,
- .set_value = 0x0,
- },
- {
- /* segment 4: normal compress */
- .phy_addr = (void *)CONFIG_SEG4_ADDR,
- .section_size = CONFIG_COMPRESSED_DATA_ADDR -
- CONFIG_SEG4_ADDR,
- .section_index = 3,
- .compress_type = RAM_COMPRESS_NORMAL,
- }
- },
-};
-#endif /* CONFIG_MDUMP_COMPRESS */
-
diff --git a/board/amlogic/sm1_elaine_p2/firmware/ramdump.h b/board/amlogic/sm1_elaine_p2/firmware/ramdump.h
deleted file mode 100755
index 0671567..0000000
--- a/board/amlogic/sm1_elaine_p2/firmware/ramdump.h
+++ /dev/null
@@ -1,75 +0,0 @@
-#ifndef __RAM_DUMP_H__
-#define __RAM_DUMP_H__
-
-#include <config.h>
-#ifdef CONFIG_MDUMP_COMPRESS
-#define CONFIG_COMPRESS_SECTION 4
-
-#if CONFIG_COMPRESS_SECTION > 8
-#error ---> CONFIG_COMPRESS_SECTION out of range, max should be 8
-#endif
-/*
- * Full Memory lay out for RAM compress:
- *
- * DDR_TOP -> +--------+
- * | |
- * | |
- * | 4 |
- * | |
- * | |
- * |~~~~~~~~| <- store compressing data
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * |~~~~~~~~|
- * COMPRESSED_DATA -> +--------+
- * | |
- * | 3 |
- * | |
- * BL2_IGNORE_END -> +--------+ -- IGNORE_SIZE
- * ||||||||||
- * ||||2|||||
- * ||||||||||
- * BL2_IGNORE_ADDR -> +--------+
- * | |
- * | 1 |
- * | |
- * COMPRESS_START_ADDR -> +--------+
- */
-#define CONFIG_DDR_TOTAL_SIZE (CONFIG_DDR_SIZE << 20)
-#define CONFIG_COMPRESSED_DATA_ADDR (0x10000000)
-#define CONFIG_COMPRESSED_DATA_ADDR1 (0x08000000)
-
-#define CONFIG_COMPRESS_START_ADDR (0x00000000)
-#define CONFIG_BL2_IGNORE_ADDR (0x05000000)
-#define CONFIG_BL2_IGNORE_SIZE (0x00300000)
-#define CONFIG_SEG4_ADDR (CONFIG_BL2_IGNORE_ADDR + \
- CONFIG_BL2_IGNORE_SIZE)
-
-enum {
- RAM_COMPRESS_NORMAL = 1,
- RAM_COMPRESS_COPY = 2,
- RAM_COMPRESS_SET = 3 /* set ram content to same vale */
-};
-
-struct ram_compress_section {
- void *phy_addr;
- unsigned int section_size;
- unsigned int section_index : 8;
- unsigned int compress_type : 8;
- unsigned int set_value : 16;
-};
-
-struct ram_compress_full {
- void *store_phy_addr;
- unsigned int full_memsize;
- unsigned int section_count;
- struct ram_compress_section sections[CONFIG_COMPRESS_SECTION];
-};
-
-#endif
-#endif /* __RAM_DUMP_H__ */
diff --git a/board/amlogic/sm1_elaine_p2/firmware/scp_task/dvfs_board.c b/board/amlogic/sm1_elaine_p2/firmware/scp_task/dvfs_board.c
deleted file mode 100755
index accb38f..0000000
--- a/board/amlogic/sm1_elaine_p2/firmware/scp_task/dvfs_board.c
+++ /dev/null
@@ -1,194 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_p1/firmware/scp_task/dvfs_board.c
- *
- * Copyright (C) 2016 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-/*
-int pwm_voltage_table[ ][2] = {
- { 0x1c0000, 860},
- { 0x1b0001, 870},
- { 0x1a0002, 880},
- { 0x190003, 890},
- { 0x180004, 900},
- { 0x170005, 910},
- { 0x160006, 920},
- { 0x150007, 930},
- { 0x140008, 940},
- { 0x130009, 950},
- { 0x12000a, 960},
- { 0x11000b, 970},
- { 0x10000c, 980},
- { 0x0f000d, 990},
- { 0x0e000e, 1000},
- { 0x0d000f, 1010},
- { 0x0c0010, 1020},
- { 0x0b0011, 1030},
- { 0x0a0012, 1040},
- { 0x090013, 1050},
- { 0x080014, 1060},
- { 0x070015, 1070},
- { 0x060016, 1080},
- { 0x050017, 1090},
- { 0x040018, 1100},
- { 0x030019, 1110},
- { 0x02001a, 1120},
- { 0x01001b, 1130},
- { 0x00001c, 1140}
-};
-*/
-#include "pwm_ctrl.h"
-
-#define CHIP_ADJUST 20
-#define RIPPLE_ADJUST 30
-struct scpi_opp_entry cpu_dvfs_tbl[] = {
- DVFS( 100000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS( 250000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS( 500000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS( 667000000, 900+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1000000000, 910+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1200000000, 940+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1296000000, 980+CHIP_ADJUST+RIPPLE_ADJUST),
- DVFS(1416000000, 1050+CHIP_ADJUST+RIPPLE_ADJUST),
-};
-
-
-#define P_PIN_MUX_REG3 (*((volatile unsigned *)(0xff634400 + (0x2f << 2))))
-#define P_PIN_MUX_REG4 (*((volatile unsigned *)(0xff634400 + (0x30 << 2))))
-#define P_PIN_MUX_REG10 (*((volatile unsigned *)(0xff634400 + (0x36 << 2))))
-
-#define P_PWM_MISC_REG_AB (*((volatile unsigned *)(0xffd1b000 + (0x02 << 2))))
-#define P_PWM_PWM_A (*((volatile unsigned *)(0xffd1b000 + (0x0 << 2))))
-
-
-enum pwm_id {
- pwm_a = 0,
-};
-
-
-void pwm_init(int id)
-{
- /*
- * TODO: support more pwm controllers, right now only support PWM_B
- */
- unsigned int reg;
- reg = P_PWM_MISC_REG_AB;
- reg &= ~(0x7f << 8);
- reg |= ((1 << 15) | (1 << 0));
- P_PWM_MISC_REG_AB = reg;
- /*
- * default set to max voltage
- */
- //P_PWM_PWM_A = pwm_voltage_table[ARRAY_SIZE(pwm_voltage_table) - 1][0];
- reg = P_PIN_MUX_REG3;
- reg &= ~((1 << 21) | 1 << 12);
- P_PIN_MUX_REG3 = reg;
-
- reg = P_PIN_MUX_REG10;
- reg &= ~(1 << 16);
- P_PIN_MUX_REG10 = reg;//clear reg10
- reg = P_PIN_MUX_REG4;
- reg &= ~(1 << 26); // clear PWM_VS
- reg |= (1 << 17); // enable PWM_A
- P_PIN_MUX_REG4 = reg;
-
-
- _udelay(200);
-}
-
-int dvfs_get_voltage(void)
-{
- int i = 0;
- unsigned int reg_val;
-
- reg_val = P_PWM_PWM_A;
- for (i = 0; i < ARRAY_SIZE(pwm_voltage_table); i++) {
- if (pwm_voltage_table[i][0] == reg_val) {
- return i;
- }
- }
- if (i >= ARRAY_SIZE(pwm_voltage_table)) {
- return -1;
- }
- return -1;
-}
-
-void set_dvfs(unsigned int domain, unsigned int index)
-{
- int cur, to;
- static int init_flag = 0;
-
- if (!init_flag) {
- pwm_init(pwm_a);
- init_flag = 1;
- }
- cur = dvfs_get_voltage();
- for (to = 0; to < ARRAY_SIZE(pwm_voltage_table); to++) {
- if (pwm_voltage_table[to][1] >= cpu_dvfs_tbl[index].volt_mv) {
- break;
- }
- }
- if (to >= ARRAY_SIZE(pwm_voltage_table)) {
- to = ARRAY_SIZE(pwm_voltage_table) - 1;
- }
- if (cur < 0 || cur >=ARRAY_SIZE(pwm_voltage_table)) {
- P_PWM_PWM_A = pwm_voltage_table[to][0];
- _udelay(200);
- return ;
- }
- while (cur != to) {
- /*
- * if target step is far away from current step, don't change
- * voltage by one-step-done. You should change voltage step by
- * step to make sure voltage output is stable
- */
- if (cur < to) {
- if (cur < to - 3) {
- cur += 3;
- } else {
- cur = to;
- }
- } else {
- if (cur > to + 3) {
- cur -= 3;
- } else {
- cur = to;
- }
- }
- P_PWM_PWM_A = pwm_voltage_table[cur][0];
- _udelay(100);
- }
- _udelay(200);
-}
-void get_dvfs_info_board(unsigned int domain,
- unsigned char *info_out, unsigned int *size_out)
-{
- unsigned int cnt;
- cnt = ARRAY_SIZE(cpu_dvfs_tbl);
-
- buf_opp.latency = 200;
- buf_opp.count = cnt;
- memset(&buf_opp.opp[0], 0,
- MAX_DVFS_OPPS * sizeof(struct scpi_opp_entry));
-
- memcpy(&buf_opp.opp[0], cpu_dvfs_tbl ,
- cnt * sizeof(struct scpi_opp_entry));
-
- memcpy(info_out, &buf_opp, sizeof(struct scpi_opp));
- *size_out = sizeof(struct scpi_opp);
- return;
-}
diff --git a/board/amlogic/sm1_elaine_p2/firmware/scp_task/pwm_ctrl.h b/board/amlogic/sm1_elaine_p2/firmware/scp_task/pwm_ctrl.h
deleted file mode 100755
index 0f815f8..0000000
--- a/board/amlogic/sm1_elaine_p2/firmware/scp_task/pwm_ctrl.h
+++ /dev/null
@@ -1,40 +0,0 @@
-/*
-*board/amlogic/sm1_elaine_p1/firmware/scp_task/pwm_vol_tab.h
-*table for Dynamic Voltage/Frequency Scaling
-*/
-#ifndef __PWM_CTRL_H__
-#define __PWM_CTRL_H__
-
-static int pwm_voltage_table_ee[][2] = {
- { 0x1c0000, 681},
- { 0x1b0001, 691},
- { 0x1a0002, 701},
- { 0x190003, 711},
- { 0x180004, 721},
- { 0x170005, 731},
- { 0x160006, 741},
- { 0x150007, 751},
- { 0x140008, 761},
- { 0x130009, 772},
- { 0x12000a, 782},
- { 0x11000b, 792},
- { 0x10000c, 802},
- { 0x0f000d, 812},
- { 0x0e000e, 822},
- { 0x0d000f, 832},
- { 0x0c0010, 842},
- { 0x0b0011, 852},
- { 0x0a0012, 862},
- { 0x090013, 872},
- { 0x080014, 882},
- { 0x070015, 892},
- { 0x060016, 902},
- { 0x050017, 912},
- { 0x040018, 922},
- { 0x030019, 932},
- { 0x02001a, 942},
- { 0x01001b, 952},
- { 0x00001c, 962}
-};
-
-#endif //__PWM_CTRL_H__
diff --git a/board/amlogic/sm1_elaine_p2/firmware/scp_task/pwr_ctrl.c b/board/amlogic/sm1_elaine_p2/firmware/scp_task/pwr_ctrl.c
deleted file mode 100755
index 7289735..0000000
--- a/board/amlogic/sm1_elaine_p2/firmware/scp_task/pwr_ctrl.c
+++ /dev/null
@@ -1,196 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_p1/firmware/scp_task/pwr_ctrl.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <gpio.h>
-#include "pwm_ctrl.h"
-#ifdef CONFIG_CEC_WAKEUP
-#include <cec_tx_reg.h>
-#endif
-
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
-static void set_vddee_voltage(unsigned int target_voltage)
-{
- unsigned int to;
-
- for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
- if (pwm_voltage_table_ee[to][1] >= target_voltage) {
- break;
- }
- }
-
- if (to >= ARRAY_SIZE(pwm_voltage_table_ee)) {
- to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
- }
-
- writel(pwm_voltage_table_ee[to][0],AO_PWM_PWM_B);
-}
-
-static void power_off_at_24M(unsigned int suspend_from)
-{
- /*set gpioH_8 low to power off vcc 5v*/
- writel(readl(PREG_PAD_GPIO3_EN_N) & (~(1 << 8)), PREG_PAD_GPIO3_EN_N);
- writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
-
- /*set test_n low to power off vcck & vcc 3.3v*/
- writel(readl(AO_GPIO_O) & (~(1 << 31)), AO_GPIO_O);
- writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
- writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
-
- /*step down ee voltage*/
- set_vddee_voltage(AML_VDDEE_SLEEP_VOLTAGE);
-}
-
-static void power_on_at_24M(unsigned int suspend_from)
-{
- /*step up ee voltage*/
- set_vddee_voltage(AML_VDDEE_INIT_VOLTAGE);
-
- /*set test_n low to power on vcck & vcc 3.3v*/
- writel(readl(AO_GPIO_O) | (1 << 31), AO_GPIO_O);
- writel(readl(AO_GPIO_O_EN_N) & (~(1 << 31)), AO_GPIO_O_EN_N);
- writel(readl(AO_RTI_PIN_MUX_REG1) & (~(0xf << 28)), AO_RTI_PIN_MUX_REG1);
- _udelay(100);
-
- /*set gpioH_8 low to power on vcc 5v*/
- writel(readl(PREG_PAD_GPIO3_EN_N) | (1 << 8), PREG_PAD_GPIO3_EN_N);
- writel(readl(PERIPHS_PIN_MUX_C) & (~(0xf)), PERIPHS_PIN_MUX_C);
- _udelay(10000);
-
-}
-
-void get_wakeup_source(void *response, unsigned int suspend_from)
-{
- struct wakeup_info *p = (struct wakeup_info *)response;
- struct wakeup_gpio_info *gpio;
- unsigned val;
- unsigned i = 0;
-
- p->status = RESPONSE_OK;
- val = (POWER_KEY_WAKEUP_SRC | AUTO_WAKEUP_SRC | REMOTE_WAKEUP_SRC |
- ETH_PHY_WAKEUP_SRC | BT_WAKEUP_SRC | ETH_PHY_GPIO_SRC
- | CECB_WAKEUP_SRC);
-
- p->sources = val;
-
- /* Power Key: AO_GPIO[3]*/
- gpio = &(p->gpio_info[i]);
- gpio->wakeup_id = POWER_KEY_WAKEUP_SRC;
- gpio->gpio_in_idx = GPIOAO_3;
- gpio->gpio_in_ao = 1;
- gpio->gpio_out_idx = -1;
- gpio->gpio_out_ao = -1;
- gpio->irq = IRQ_AO_GPIO0_NUM;
- gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
- p->gpio_info_count = ++i;
-
- /*Eth:GPIOZ_14*/
- gpio = &(p->gpio_info[i]);
- gpio->wakeup_id = ETH_PHY_GPIO_SRC;
- gpio->gpio_in_idx = GPIOZ_14;
- gpio->gpio_in_ao = 0;
- gpio->gpio_out_idx = -1;
- gpio->gpio_out_ao = -1;
- gpio->irq = IRQ_GPIO1_NUM;
- gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
- p->gpio_info_count = ++i;
-
- /*bt wake host*/
- gpio = &(p->gpio_info[i]);
- gpio->wakeup_id = BT_WAKEUP_SRC;
- gpio->gpio_in_idx = GPIOX_18;
- gpio->gpio_in_ao = 0;
- gpio->gpio_out_idx = -1;
- gpio->gpio_out_ao = -1;
- gpio->irq = IRQ_GPIO0_NUM;
- gpio->trig_type = GPIO_IRQ_FALLING_EDGE;
- p->gpio_info_count = ++i;
-}
-extern void __switch_idle_task(void);
-
-static unsigned int detect_key(unsigned int suspend_from)
-{
- int exit_reason = 0;
- unsigned *irq = (unsigned *)WAKEUP_SRC_IRQ_ADDR_BASE;
- init_remote();
-#ifdef CONFIG_CEC_WAKEUP
- if (hdmi_cec_func_config & 0x1) {
- remote_cec_hw_reset();
- cec_node_init();
- }
-#endif
-
- do {
- #ifdef CONFIG_CEC_WAKEUP
- if (irq[IRQ_AO_CECB] == IRQ_AO_CEC2_NUM) {
- irq[IRQ_AO_CECB] = 0xFFFFFFFF;
- if (cec_power_on_check())
- exit_reason = CEC_WAKEUP;
- }
- #endif
- if (irq[IRQ_AO_IR_DEC] == IRQ_AO_IR_DEC_NUM) {
- irq[IRQ_AO_IR_DEC] = 0xFFFFFFFF;
- if (remote_detect_key())
- exit_reason = REMOTE_WAKEUP;
- }
-
- if (irq[IRQ_VRTC] == IRQ_VRTC_NUM) {
- irq[IRQ_VRTC] = 0xFFFFFFFF;
- exit_reason = RTC_WAKEUP;
- }
-
- if (irq[IRQ_AO_GPIO0] == IRQ_AO_GPIO0_NUM) {
- irq[IRQ_AO_GPIO0] = 0xFFFFFFFF;
- if ((readl(AO_GPIO_I) & (1<<3)) == 0)
- exit_reason = POWER_KEY_WAKEUP;
- }
-#if 0
- if (irq[IRQ_GPIO1] == IRQ_GPIO1_NUM) {
- irq[IRQ_GPIO1] = 0xFFFFFFFF;
- if (!(readl(PREG_PAD_GPIO4_I) & (0x01 << 14))
- && (readl(PREG_PAD_GPIO4_EN_N) & (0x01 << 14)))
- exit_reason = ETH_PHY_GPIO;
- }
-#endif
- if (irq[IRQ_GPIO0] == IRQ_GPIO0_NUM) {
- irq[IRQ_GPIO0] = 0xFFFFFFFF;
- if (!(readl(PREG_PAD_GPIO2_I) & (0x01 << 18))
- && (readl(PREG_PAD_GPIO2_O) & (0x01 << 17))
- && !(readl(PREG_PAD_GPIO2_EN_N) & (0x01 << 17)))
- exit_reason = BT_WAKEUP;
- }
-
- if (exit_reason)
- break;
- else
- __switch_idle_task();
- } while (1);
-
- return exit_reason;
-}
-
-static void pwr_op_init(struct pwr_op *pwr_op)
-{
- pwr_op->power_off_at_24M = power_off_at_24M;
- pwr_op->power_on_at_24M = power_on_at_24M;
- pwr_op->detect_key = detect_key;
- pwr_op->get_wakeup_source = get_wakeup_source;
-}
diff --git a/board/amlogic/sm1_elaine_p2/firmware/timing.c b/board/amlogic/sm1_elaine_p2/firmware/timing.c
deleted file mode 100755
index 8c785e8..0000000
--- a/board/amlogic/sm1_elaine_p2/firmware/timing.c
+++ /dev/null
@@ -1,462 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_p1/firmware/timing.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/timing.h>
-#include <asm/arch/ddr_define.h>
-
-/* board clk defines */
-#define DDR_SIZE 0
-#define CPU_CLK 1200
-
-/* ddr config support multiple configs for boards which use same bootloader:
- * config steps:
- * 1. add a new data struct in __ddr_setting[]
- * 2. config correct board_id, ddr_type, freq, etc..
- */
-
-
-/* CAUTION!! */
-/* Confirm ddr configs with hardware designer,
- * if you don't know how to config, then don't edit it
- */
-
-/* Key configs */
-/*
- * board_id: check hardware adc config
- * dram_rank_config:
- * #define CONFIG_DDR_CHL_AUTO 0xF
- * #define CONFIG_DDR0_16BIT_CH0 0x1
- * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
- * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
- * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
- * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
- * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
- * DramType:
- * #define CONFIG_DDR_TYPE_DDR3 0
- * #define CONFIG_DDR_TYPE_DDR4 1
- * #define CONFIG_DDR_TYPE_LPDDR4 2
- * #define CONFIG_DDR_TYPE_LPDDR3 3
- * DRAMFreq:
- * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
- *
- */
-
-
-/* ddr configs */
-#define DDR_RFC_TYPE_DDR3_512Mbx1 0
-#define DDR_RFC_TYPE_DDR3_512Mbx2 1
-#define DDR_RFC_TYPE_DDR3_512Mbx4 2
-#define DDR_RFC_TYPE_DDR3_512Mbx8 3
-#define DDR_RFC_TYPE_DDR3_512Mbx16 4
-#define DDR_RFC_TYPE_DDR4_2Gbx1 5
-#define DDR_RFC_TYPE_DDR4_2Gbx2 6
-#define DDR_RFC_TYPE_DDR4_2Gbx4 7
-#define DDR_RFC_TYPE_DDR4_2Gbx8 8
-
-#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
-#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
-#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
-
-#if CONFIG_DDR_LOGS_ENABLED
-#define LOG_FLAG 0x4
-#else
-#define LOG_FLAG 0xA
-#endif
-
-ddr_set_t __ddr_setting[] = {
- {
- /* Elaine ddr3 */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
- .DramType = CONFIG_DDR_TYPE_DDR3,
- .DRAMFreq = {912, 0, 0, 0},
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 1,
- .HdtCtrl = LOG_FLAG,
- .dram_cs0_size_MB = 1024,
- .dram_cs1_size_MB = 1024,
- .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .clk_drv_ohm = 40,
- .cs_drv_ohm = 40,
- .ac_drv_ohm = 40,
- .soc_data_drv_ohm_p = 34,
- .soc_data_drv_ohm_n = 34,
- .soc_data_odt_ohm_p = 60, //48,
- .soc_data_odt_ohm_n = 0,
- .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
- .dram_data_odt_ohm = 60,
- .dram_ac_odt_ohm = 0,
- .soc_clk_slew_rate = 0x300,
- .soc_cs_slew_rate = 0x300,
- .soc_ac_slew_rate = 0x300,
- .soc_data_slew_rate = 0x200,
- .vref_output_permil = 500,
- .vref_receiver_permil = 500, //700,
- .vref_dram_permil = 500, //700,
-// .vref_reverse = 0,
- .ac_trace_delay ={32,32,32,32,32,32,32,32,32,32},
- //{00,00},
- .ac_pinmux = {00,00},
-#if 1
- .ddr_dmc_remap = {
- [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
- [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
- },
-#else
- //16bit
- .ddr_dmc_remap = {
- [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
- [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20 << 15) |( 21 << 20) | (22 << 25 )),
- [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
- [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
- },
-#endif
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap = {00,00},
- .dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
- .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
-},
-{
- /* g12a skt (u209) ddr3 */
- .board_id = CONFIG_BOARD_ID_MASK,
- .version = 1,
- .dram_rank_config = CONFIG_DDR0_32BIT_RANK01_CH0,
- .DramType = CONFIG_DDR_TYPE_DDR3,
- .DRAMFreq = {912, 0, 0, 0},
- .ddr_base_addr = CFG_DDR_BASE_ADDR,
- .ddr_start_offset = CFG_DDR_START_OFFSET,
- .imem_load_addr = 0xFFFC0000, //sram
- .dmem_load_size = 0x1000, //4K
-
- .DisabledDbyte = 0xf0,
- .Is2Ttiming = 1,
- .HdtCtrl = LOG_FLAG,
- .dram_cs0_size_MB = 1024,
- .dram_cs1_size_MB = 512,
- .training_SequenceCtrl = {0x31f,0}, //ddr3 0x21f 0x31f
- .phy_odt_config_rank = {0x23,0x13}, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
- .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
- .PllBypassEn = 0, //bit0-ps0,bit1-ps1
- .ddr_rdbi_wr_enable = 0,
- .pll_ssc_mode = 0,
- .clk_drv_ohm = 40,
- .cs_drv_ohm = 40,
- .ac_drv_ohm = 40,
- .soc_data_drv_ohm_p = 34,
- .soc_data_drv_ohm_n = 34,
- .soc_data_odt_ohm_p = 60, //48,
- .soc_data_odt_ohm_n = 0,
- .dram_data_drv_ohm = 34, //ddr4 sdram only 34 or 48, skt board use 34 better
- .dram_data_odt_ohm = 60,
- .dram_ac_odt_ohm = 0,
- .soc_clk_slew_rate = 0x300,
- .soc_cs_slew_rate = 0x300,
- .soc_ac_slew_rate = 0x300,
- .soc_data_slew_rate = 0x200,
- .vref_output_permil = 500,
- .vref_receiver_permil = 500, //700,
- .vref_dram_permil = 500, //700,
- //{00,00},
- .ac_pinmux = {00,00},
-#if 1
- .ddr_dmc_remap = {
- [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
- [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
- [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
- [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
- },
-#else
- //16bit
- .ddr_dmc_remap = {
- [0] = ( 0 | 5 << 5 | 6<< 10 | 7 << 15 | 8 << 20 | 9 << 25 ),
- [1] = ( 10| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
- [2] = ( 17|( 18 << 5) |( 19 << 10) |( 20< 15) |( 21 << 20) | (22 << 25 )),
- [3] = ( 23| 24 << 5 | 25 << 10 | 26 << 15 | 27 << 20 | 28 << 25 ),
- [4] = ( 29| 11<< 5 | 12 << 10 | 13<< 15 | 0 << 20 | 0 << 25 ),
- },
-#endif
- .ddr_lpddr34_ca_remap = {00,00},
- .ddr_lpddr34_dq_remap = {00,00},
- .dram_rtt_nom_wr_park = {00,00},
-
- /* pll ssc config:
- *
- * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
- * ppm = strength * 500
- * mode: 0=center, 1=up, 2=down
- *
- * eg:
- * 1. config 1000ppm center ss. then mode=0, strength=2
- * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
- * 2. config 3000ppm down ss. then mode=2, strength=6
- * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
- */
- .pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
- .ddr_func = DDR_FUNC,
- .magic = DRAM_CFG_MAGIC,
- .slt_test_function = {DMC_TEST_SLT_ENABLE_DDR_SKIP_TRAINING, 0},
- .dfi_hwtmrl = 4,
-
- .ac_trace_delay = {
- 32, 32, 32, 32,
- 32, 32, 32, 32,
- 32, 32,
- },
-
- .write_dqs_delay = {
- 163, 163, 163, 163,
- 167, 167, 165, 165,
- 159, 159, 163, 163,
- 165, 165, 161, 161,
- },
-
- .read_dqs_delay = {
- 13, 13, 14, 14,
- 14, 14, 15, 14,
- 14, 14, 14, 15,
- 14, 13, 14, 14,
- },
-
- .write_dq_bit_delay = {
- 20, 21, 19, 21,
- 21, 21, 22, 20,
- 22, 21, 20, 20,
- 19, 21, 18, 21,
- 20, 20, 24, 20,
- 22, 25, 24, 25,
- 26, 26, 23, 20,
- 21, 20, 23, 21,
- 21, 23, 23, 20,
- 48, 49, 48, 50,
- 50, 50, 51, 49,
- 49, 21, 21, 19,
- 20, 21, 19, 20,
- 21, 20, 22, 18,
- 20, 23, 23, 24,
- 24, 24, 22, 17,
- 18, 17, 20, 18,
- 18, 21, 20, 19,
- },
-
- .read_dq_bit_delay = {
- 15, 15, 15, 23,
- 31, 31, 31, 29,
- 0 , 23, 19, 11,
- 17, 35, 23, 31,
- 31, 0 , 15, 3 ,
- 9 , 15, 27, 27,
- 35, 35, 0 , 13,
- 15, 11, 19, 25,
- 19, 31, 31, 0 ,
- 15, 17, 15, 19,
- 31, 33, 31, 27,
- 0 , 19, 19, 15,
- 13, 31, 23, 27,
- 31, 0 , 13, 3 ,
- 5 , 11, 23, 27,
- 31, 27, 0 , 13,
- 13, 9 , 19, 23,
- 23, 27, 27, 0 ,
- },
-
- .read_dqs_gate_delay = {
- 225, 227, 223, 225,
- 223, 225, 223, 227,
- 223, 225, 223, 225,
- 225, 227, 227, 229,
- },
-
-},
-};
-
-pll_set_t __pll_setting = {
- .cpu_clk = CPU_CLK / 24 * 24,
-#ifdef CONFIG_PXP_EMULATOR
- .pxp = 1,
-#else
- .pxp = 0,
-#endif
- .spi_ctrl = 0,
- .lCustomerID = AML_CUSTOMER_ID,
-#ifdef CONFIG_DEBUG_MODE
- .debug_mode = CONFIG_DEBUG_MODE,
- .ddr_clk_debug = CONFIG_DDR_CLK_DEBUG,
- .cpu_clk_debug = CONFIG_CPU_CLK_DEBUG,
-#endif
-};
-
-ddr_reg_t __ddr_reg[] = {
- /* demo, user defined override register */
- {0xaabbccdd, 0, 0, 0, 0, 0},
- {0x11223344, 0, 0, 0, 0, 0},
- {0, 0, 0, 0, 0, 0},
-};
-
-#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
-#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
-/* VCCK PWM table */
-#if (VCCK_VAL == 800)
- #define VCCK_VAL_REG 0x00150007
-#elif (VCCK_VAL == 810)
- #define VCCK_VAL_REG 0x00140008
-#elif (VCCK_VAL == 820)
- #define VCCK_VAL_REG 0x00130009
-#elif (VCCK_VAL == 830)
- #define VCCK_VAL_REG 0x0012000a
-#elif (VCCK_VAL == 840)
- #define VCCK_VAL_REG 0x0011000b
-#elif (VCCK_VAL == 850)
- #define VCCK_VAL_REG 0x0010000c
-#elif (VCCK_VAL == 860)
- #define VCCK_VAL_REG 0x000f000d
-#elif (VCCK_VAL == 870)
- #define VCCK_VAL_REG 0x000e000e
-#elif (VCCK_VAL == 880)
- #define VCCK_VAL_REG 0x000d000f
-#elif (VCCK_VAL == 890)
- #define VCCK_VAL_REG 0x000c0010
-#elif (VCCK_VAL == 900)
- #define VCCK_VAL_REG 0x000b0011
-#elif (VCCK_VAL == 910)
- #define VCCK_VAL_REG 0x000a0012
-#elif (VCCK_VAL == 920)
- #define VCCK_VAL_REG 0x00090013
-#elif (VCCK_VAL == 930)
- #define VCCK_VAL_REG 0x00080014
-#elif (VCCK_VAL == 940)
- #define VCCK_VAL_REG 0x00070015
-#elif (VCCK_VAL == 950)
- #define VCCK_VAL_REG 0x00060016
-#elif (VCCK_VAL == 960)
- #define VCCK_VAL_REG 0x00050017
-#elif (VCCK_VAL == 970)
- #define VCCK_VAL_REG 0x00040018
-#elif (VCCK_VAL == 980)
- #define VCCK_VAL_REG 0x00030019
-#elif (VCCK_VAL == 990)
- #define VCCK_VAL_REG 0x0002001a
-#elif (VCCK_VAL == 1000)
- #define VCCK_VAL_REG 0x0001001b
-#elif (VCCK_VAL == 1010)
- #define VCCK_VAL_REG 0x0000001c
-#else
- #error "VCCK val out of range\n"
-#endif
-
-/* VDDEE PWM table */
-#if (VDDEE_VAL == 800)
- #define VDDEE_VAL_REG 0x0010000c
-#elif (VDDEE_VAL == 810)
- #define VDDEE_VAL_REG 0x000f000d
-#elif (VDDEE_VAL == 820)
- #define VDDEE_VAL_REG 0x000e000e
-#elif (VDDEE_VAL == 830)
- #define VDDEE_VAL_REG 0x000d000f
-#elif (VDDEE_VAL == 840)
- #define VDDEE_VAL_REG 0x000c0010
-#elif (VDDEE_VAL == 850)
- #define VDDEE_VAL_REG 0x000b0011
-#elif (VDDEE_VAL == 860)
- #define VDDEE_VAL_REG 0x000a0012
-#elif (VDDEE_VAL == 870)
- #define VDDEE_VAL_REG 0x00090013
-#elif (VDDEE_VAL == 880)
- #define VDDEE_VAL_REG 0x00080014
-#elif (VDDEE_VAL == 890)
- #define VDDEE_VAL_REG 0x00070015
-#elif (VDDEE_VAL == 900)
- #define VDDEE_VAL_REG 0x00060016
-#elif (VDDEE_VAL == 910)
- #define VDDEE_VAL_REG 0x00050017
-#elif (VDDEE_VAL == 920)
- #define VDDEE_VAL_REG 0x00040018
-#elif (VDDEE_VAL == 930)
- #define VDDEE_VAL_REG 0x00030019
-#elif (VDDEE_VAL == 940)
- #define VDDEE_VAL_REG 0x0002001a
-#elif (VDDEE_VAL == 950)
- #define VDDEE_VAL_REG 0x0001001b
-#elif (VDDEE_VAL == 960)
- #define VDDEE_VAL_REG 0x0000001c
-#else
- #error "VDDEE val out of range\n"
-#endif
-
-/* for PWM use */
-/* PWM driver check http://scgit.amlogic.com:8080/#/c/38093/ */
-#define GPIO_O_EN_N_REG3 ((0xff634400 + (0x19 << 2)))
-#define GPIO_O_REG3 ((0xff634400 + (0x1a << 2)))
-#define GPIO_I_REG3 ((0xff634400 + (0x1b << 2)))
-#define AO_PIN_MUX_REG0 ((0xff800000 + (0x05 << 2)))
-#define AO_PIN_MUX_REG1 ((0xff800000 + (0x06 << 2)))
-
-bl2_reg_t __bl2_reg[] = {
- /* demo, user defined override register */
- /* eg: PWM init */
-
- /* PWM_AO_D */
- /* VCCK_VAL_REG: check PWM table */
- {AO_PWM_PWM_D, VCCK_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- {AO_PWM_MISC_REG_CD, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
- {AO_PIN_MUX_REG1, (3 << 20), (0xF << 20), 0, BL2_INIT_STAGE_1, 0},
- /* PWM_AO_B */
- /* VDDEE_VAL_REG: check PWM table */
- {AO_PWM_PWM_B, VDDEE_VAL_REG, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- {AO_PWM_MISC_REG_AB, ((1 << 23) | (1 << 1)), (0x7f << 16), 0, BL2_INIT_STAGE_1, 0},
- {AO_PIN_MUX_REG1, (3 << 16), (0xF << 16), 0, BL2_INIT_STAGE_1, 0},
- /* Enable 5V_EN */
- {GPIO_O_EN_N_REG3, (0 << 8), (1 << 8), 0, BL2_INIT_STAGE_1, 0},
- {GPIO_O_REG3, (1 << 8), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- /* Enable VCCK */
- {AO_SEC_REG0, (1 << 0), 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
- {AO_GPIO_O, 0x80000000, 0xffffffff, 0, BL2_INIT_STAGE_1, 0},
-};
diff --git a/board/amlogic/sm1_elaine_p2/lcd.c b/board/amlogic/sm1_elaine_p2/lcd.c
deleted file mode 100755
index a0d6847..0000000
--- a/board/amlogic/sm1_elaine_p2/lcd.c
+++ /dev/null
@@ -1,422 +0,0 @@
-/*
- * AMLOGIC TV LCD panel driver.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#include <common.h>
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#ifdef CONFIG_AML_LCD_EXTERN
-#include "lcd_extern.h"
-#endif
-
-static char lcd_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
- "GPIOH_6", /* panel rst */
- "GPIOZ_8", /* panel power */
- "invalid", /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step[] = {
- {LCD_POWER_TYPE_CPU, 1,0,100,}, /* lcd power */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 0,1,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,50,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,10,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static struct lcd_power_step_s lcd_power_on_step_TV070WSM[] = {
- {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_TV070WSM[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,50,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_on_step_P070ACB[] = {
- {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_P070ACB[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_on_step_KD070D82[] = {
- {LCD_POWER_TYPE_CPU, 1,0,200,}, /* lcd power */
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-static struct lcd_power_step_s lcd_power_off_step_KD070D82[] = {
- {LCD_POWER_TYPE_SIGNAL,0,0,0,}, /* signal */
- {LCD_POWER_TYPE_CPU, 0,0,20,}, /* lcd_reset */
- {LCD_POWER_TYPE_CPU, 1,1,100,}, /* power off */
- {LCD_POWER_TYPE_MAX, 0,0,0,}, /* ending flag */
-};
-
-static unsigned char mipi_init_on_table[DSI_INIT_ON_MAX] = {//table size < 100
- 0x05, 1, 0x11,
- 0xfd, 1, 20,
- 0x05, 1, 0x29,
- 0xfd, 1, 20,
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table[DSI_INIT_OFF_MAX] = {//table size < 50
- 0x05, 1, 0x28,
- 0xfd, 1, 10,
- 0x05, 1, 0x10,
- 0xfd, 1, 10,
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_on_table_P070ACB[DSI_INIT_ON_MAX] = {//table size < 100
- 0xfd, 1, 10,
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_P070ACB[DSI_INIT_OFF_MAX] = {//table size < 50
- 0xff, 0, //ending
-};
-
-static unsigned char mipi_init_on_table_KD070D82[DSI_INIT_ON_MAX] = {//table size < 100
- 0xfd, 1, 10,
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xf0, 3, 0, 0, 10, /* reset low, delay 10ms */
- 0xf0, 3, 0, 1, 30, /* reset high, delay 30ms */
- 0xfc, 2, 0x04, 3, /* check_reg, check_cnt */
- 0xff, 0, //ending
-};
-static unsigned char mipi_init_off_table_KD070D82[DSI_INIT_OFF_MAX] = {//table size < 50
- 0xff, 0, //ending
-};
-
-static char lcd_bl_gpio[BL_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX] = {
- "GPIOH_4", /* BL_EN */
- "GPIOH_5", /* BL_PWM */
- "invalid", /* ending flag */
-};
-
-struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX] = {
- {/* TV070WSM_FT9364*/
- "boe_fiti9364_7",LCD_MIPI,8,
- /* basic timing */
- 600,1024,700,1053,24,36,0,2,8,0,
- /* clk_attr */
- 0,0,1,44250000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,360,0,1,0,2,0,0,Rsv_val,3,
- /* cmd init */
- mipi_init_on_table, mipi_init_off_table,
- /* power step */
- lcd_power_on_step_TV070WSM, lcd_power_off_step_TV070WSM,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* P070ACB_FT9364*/
- "inx_fiti9364_7",LCD_MIPI,8,
- /* basic timing */
- 600,1024,770,1070,10,80,0,6,20,0,
- /* clk_attr */
- 0,0,1,49434000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,400,0,1,0,2,0,0,Rsv_val,1,
- /* cmd init */
- mipi_init_on_table_P070ACB, mipi_init_off_table_P070ACB,
- /* power step */
- lcd_power_on_step_P070ACB, lcd_power_off_step_P070ACB,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {/* KD070D82_FT9364*/
- "kd_fiti9364_7",LCD_MIPI,8,
- /* basic timing */
- 600,1024,770,1070,10,80,0,6,20,0,
- /* clk_attr */
- 0,0,1,49434000,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- /* mipi_attr */
- 4,400,0,1,0,2,0,0,Rsv_val,2,
- /* cmd init */
- mipi_init_on_table_KD070D82, mipi_init_off_table_KD070D82,
- /* power step */
- lcd_power_on_step_KD070D82, lcd_power_off_step_KD070D82,
- /* backlight */
- 100,255,10,128,128,
- BL_CTRL_PWM,0,1,0,200,200,
- BL_PWM_NEGATIVE,BL_PWM_F,180,100,25,1,1,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- Rsv_val,Rsv_val,Rsv_val,Rsv_val,
- 10,10,Rsv_val},
-
- {.panel_type = "invalid"},
-};
-
-static struct lcd_pinmux_ctrl_s lcd_pinmux_ctrl[LCD_PINMX_MAX] = {
- {
- .name = "lcd_pin",
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
- },
- {
- .name = "invalid",
- },
-};
-
-static struct lcd_pinmux_ctrl_s bl_pinmux_ctrl[BL_PINMUX_MAX] = {
- {
- .name = "bl_pwm_on_pin", //GPIOH_5
- .pinmux_set = {{11, 0x00400000}, {LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{11, 0x00f00000}, {LCD_PINMUX_END, 0x0}},
- },
- {
- .name = "invalid",
- },
-};
-
-#ifdef CONFIG_AML_BL_EXTERN
-static unsigned char bl_ext_init_on[BL_EXTERN_INIT_ON_MAX] = {
- 0xff, 0, //ending flag
-};
-static unsigned char bl_ext_init_off[BL_EXTERN_INIT_OFF_MAX] = {
- 0xff, 0, //ending flag
-};
-#endif
-
-/* **********************************************
- * driver struct, usually no need modify!
- * ********************************************** */
-static struct dsi_config_s lcd_mipi_config = {
- .lane_num = 4,
- .bit_rate_max = 1000, /* MHz */
- .factor_numerator = 0,
- .factor_denominator = 100,
- .operation_mode_init = 1, /* 0=video mode, 1=command mode */
- .operation_mode_display = 0, /* 0=video mode, 1=command mode */
- .video_mode_type = 2, /* 0=sync_pulse, 1=sync_event, 2=burst */
- .clk_always_hs = 1, /* 0=disable, 1=enable */
- .phy_switch = 0, /* 0=auto, 1=standard, 2=slow */
-
- .dsi_init_on = mipi_init_on_table,
- .dsi_init_off = mipi_init_off_table,
- .extern_init = 0xff, /* ext_index if needed, 0xff for invalid */
- .check_en = 0,
- .check_state = 0,
-};
-
-static struct lcd_power_ctrl_s lcd_power_ctrl = {
- .power_on_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
- .power_off_step = {
- {
- .type = LCD_POWER_TYPE_MAX, /* ending flag */
- },
- },
-};
-
-struct lcd_config_s lcd_config_dft = {
- .lcd_mode = LCD_MODE_TABLET,
- .lcd_key_valid = 0,
- .lcd_clk_path = 0,
- .lcd_basic = {
- .model_name = "default",
- .lcd_type = LCD_TYPE_MAX,
- .lcd_bits = 8,
- .h_active = 768,
- .v_active = 1024,
- .h_period = 948,
- .v_period = 1140,
-
- .screen_width = 119,
- .screen_height = 159,
- },
-
- .lcd_timing = {
- .clk_auto = 1,
- .lcd_clk = 64843200,
- .ss_level = 0,
- .fr_adjust_type = 0,
-
- .hsync_width = 64,
- .hsync_bp = 56,
- .hsync_pol = 0,
- .vsync_width = 50,
- .vsync_bp = 30,
- .vsync_pol = 0,
- },
-
- .lcd_control = {
- .mipi_config= &lcd_mipi_config,
- },
- .lcd_power = &lcd_power_ctrl,
-
- .pinctrl_ver = 2,
- .lcd_pinmux = lcd_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_LCD_EXTERN
-struct lcd_extern_common_s ext_common_dft = {
- .lcd_ext_key_valid = 0,
- .i2c_bus = LCD_EXTERN_I2C_BUS_0, /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
- .i2c_gpio_sck = LCD_EXT_I2C_GPIO_SCK,
- .i2c_gpio_sda = LCD_EXT_I2C_GPIO_SDA,
- .spi_gpio_cs = LCD_EXT_SPI_GPIO_CS,
- .spi_gpio_clk = LCD_EXT_SPI_GPIO_CLK,
- .spi_gpio_data = LCD_EXT_SPI_GPIO_DATA,
-
- .lcd_ext_pinmux = lcd_ext_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
- .pinmux_gpio_off = LCD_EXT_PINMUX_GPIO_OFF,
-};
-
-struct lcd_extern_config_s ext_config_dtf = {
- .index = 0,
- .name = "ext_default",
- .type = LCD_EXTERN_MAX, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 0, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
-};
-#endif
-
-struct bl_config_s bl_config_dft = {
- .name = "default",
- .bl_key_valid = 0,
-
- .level_default = 100,
- .level_min = 10,
- .level_max = 255,
- .level_mid = 128,
- .level_mid_mapping = 128,
- .level = 0,
-
- .method = BL_CTRL_MAX,
- .power_on_delay = 20,
- .power_off_delay = 20,
-
- .en_gpio = 0xff,
- .en_gpio_on = 1,
- .en_gpio_off = 0,
-
- .bl_pwm = NULL,
- .bl_pwm_combo0 = NULL,
- .bl_pwm_combo1 = NULL,
- .pwm_on_delay = 10,
- .pwm_off_delay = 10,
-
- .bl_extern_index = 0xff,
-
- .pinctrl_ver = 2,
- .bl_pinmux = bl_pinmux_ctrl,
- .pinmux_set = {{LCD_PINMUX_END, 0x0}},
- .pinmux_clr = {{LCD_PINMUX_END, 0x0}},
-};
-
-#ifdef CONFIG_AML_BL_EXTERN
-struct bl_extern_config_s bl_extern_config_dtf = {
- .index = BL_EXTERN_INDEX_INVALID,
- .name = "none",
- .type = BL_EXTERN_MAX,
- .i2c_addr = 0xff,
- .i2c_bus = BL_EXTERN_I2C_BUS_MAX,
- .dim_min = 10,
- .dim_max = 255,
-
- .init_loaded = 0,
- .cmd_size = 0xff,
- .init_on = bl_ext_init_on,
- .init_off = bl_ext_init_off,
- .init_on_cnt = sizeof(bl_ext_init_on),
- .init_off_cnt = sizeof(bl_ext_init_off),
-};
-#endif
-/* ********************************************** */
-
-void lcd_config_bsp_init(void)
-{
- int i, j;
- char *str;
- struct ext_lcd_config_s *ext_lcd = NULL;
-
- /* init config, usually no need modify */
- for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_cpu_gpio[i], "invalid") == 0)
- break;
- strcpy(lcd_power_ctrl.cpu_gpio[i], lcd_cpu_gpio[i]);
- }
- for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
- strcpy(lcd_power_ctrl.cpu_gpio[j], "invalid");
- for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_bl_gpio[i], "invalid") == 0)
- break;
- strcpy(bl_config_dft.gpio_name[i], lcd_bl_gpio[i]);
- }
- for (j = i; j < BL_GPIO_NUM_MAX; j++)
- strcpy(bl_config_dft.gpio_name[j], "invalid");
-
-#ifdef CONFIG_AML_LCD_EXTERN
- for (i = 0; i < LCD_EXTERN_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_ext_gpio[i], "invalid") == 0)
- break;
- strcpy(ext_common_dft.gpio_name[i], lcd_ext_gpio[i]);
- }
- for (j = i; j < LCD_EXTERN_GPIO_NUM_MAX; j++)
- strcpy(ext_common_dft.gpio_name[j], "invalid");
-#endif
-
- /* select special config */
- str = env_get("panel_type");
- if (str == NULL)
- return;
- for (i = 0 ; i < LCD_NUM_MAX ; i++) {
- ext_lcd = &ext_lcd_config[i];
- if (strcmp(ext_lcd->panel_type, str) == 0) {
-#ifdef CONFIG_AML_LCD_EXTERN
- j = ext_lcd->if_attr_val9; /* mipi extern_index */
- if (j < sizeof(ext_config)/sizeof(struct lcd_extern_config_s)) {
- memcpy(&ext_config_dtf, &ext_config[j],
- sizeof(struct lcd_extern_config_s));
- }
-#endif
- break;
- }
- }
-}
diff --git a/board/amlogic/sm1_elaine_p2/lcd_extern.h b/board/amlogic/sm1_elaine_p2/lcd_extern.h
deleted file mode 100755
index b88a613..0000000
--- a/board/amlogic/sm1_elaine_p2/lcd_extern.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * board/amlogic/sm1_elaine_p2/lcd_extern.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _DFT_LCD_EXTERN_H_
-#define _DFT_LCD_EXTERN_H_
-
-#define LCD_EXT_I2C_GPIO_SCK 0xff /* 0xff for invalid */
-#define LCD_EXT_I2C_GPIO_SDA 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_CS 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_CLK 0xff /* 0xff for invalid */
-#define LCD_EXT_SPI_GPIO_DATA 0xff /* 0xff for invalid */
-#define LCD_EXT_PINMUX_GPIO_OFF 0
-
-static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX] = {
- "invalid", /* ending flag */
-};
-
-static struct lcd_pinmux_ctrl_s lcd_ext_pinmux_ctrl[LCD_PINMX_MAX] = {
- {
- .name = "invalid",
- },
-};
-
-static unsigned char ext_init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
- 0xff, 0, //ending flag
-};
-
-static unsigned char ext_init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
- 0xff, 0, //ending flag
-};
-
-static struct lcd_extern_config_s ext_config[LCD_EXTERN_NUM_MAX] = {
- {
- .index = 0,
- .name = "ext_default",
- .type = LCD_EXTERN_I2C, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 0, /* 0=disable, 1=enable */
- .i2c_addr = 0x1c, /* 7bit i2c address */
- .i2c_addr2 = 0xff, /* 7bit i2c address, 0xff for invalid */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- { /* P070ACB_FT9364 */
- .index = 1,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- /*we define initial codes in panel.dtsi*/
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- { /* KD070D82_FT9364 */
- .index = 2,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- /*we define initial codes in panel.dtsi*/
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
- { /* TV070WSM_FT9364 */
- .index = 3,
- .name = "mipi_default",
- .type = LCD_EXTERN_MIPI, /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI, LCD_EXTERN_MAX */
- .status = 1, /* 0=disable, 1=enable */
- .cmd_size = LCD_EXT_CMD_SIZE_DYNAMIC,
- /*we define initial codes in panel.dtsi*/
- .table_init_on = ext_init_on_table,
- .table_init_on_cnt = sizeof(ext_init_on_table),
- .table_init_off = ext_init_off_table,
- .table_init_off_cnt = sizeof(ext_init_off_table),
- },
-
- {
- .index = LCD_EXTERN_INDEX_INVALID,
- },
-};
-
-#endif
-
diff --git a/board/amlogic/sm1_elaine_p2/pwm_table.c b/board/amlogic/sm1_elaine_p2/pwm_table.c
deleted file mode 100755
index 18dc638..0000000
--- a/board/amlogic/sm1_elaine_p2/pwm_table.c
+++ /dev/null
@@ -1,71 +0,0 @@
-#include <common.h>
-
-const int pwm_cal_voltage_table[][2] = {
- { 0x1c0000, 860},
- { 0x1b0001, 870},
- { 0x1a0002, 880},
- { 0x190003, 890},
- { 0x180004, 900},
- { 0x170005, 910},
- { 0x160006, 920},
- { 0x150007, 930},
- { 0x140008, 940},
- { 0x130009, 950},
- { 0x12000a, 960},
- { 0x11000b, 970},
- { 0x10000c, 980},
- { 0x0f000d, 990},
- { 0x0e000e, 1000},
- { 0x0d000f, 1010},
- { 0x0c0010, 1020},
- { 0x0b0011, 1030},
- { 0x0a0012, 1040},
- { 0x090013, 1050},
- { 0x080014, 1060},
- { 0x070015, 1070},
- { 0x060016, 1080},
- { 0x050017, 1090},
- { 0x040018, 1100},
- { 0x030019, 1110},
- { 0x02001a, 1120},
- { 0x01001b, 1130},
- { 0x00001c, 1140}
-};
-const int pwm_cal_voltage_table_ee[][2] = {
- { 0x1c0000, 810},
- { 0x1b0001, 820},
- { 0x1a0002, 830},
- { 0x190003, 840},
- { 0x180004, 850},
- { 0x170005, 860},
- { 0x160006, 870},
- { 0x150007, 880},
- { 0x140008, 890},
- { 0x130009, 900},
- { 0x12000a, 910},
- { 0x11000b, 920},
- { 0x10000c, 930},
- { 0x0f000d, 940},
- { 0x0e000e, 950},
- { 0x0d000f, 960},
- { 0x0c0010, 970},
- { 0x0b0011, 980},
- { 0x0a0012, 990},
- { 0x090013, 1000},
- { 0x080014, 1010},
- { 0x070015, 1020},
- { 0x060016, 1030},
- { 0x050017, 1040},
- { 0x040018, 1050},
- { 0x030019, 1060},
- { 0x02001a, 1070},
- { 0x01001b, 1080},
- { 0x00001c, 1090}
-};
-
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
-int pwm_cal_voltage_table_size = ARRAY_SIZE(pwm_cal_voltage_table);
-int pwm_cal_voltage_table_ee_size = ARRAY_SIZE(pwm_cal_voltage_table_ee);
-
-
diff --git a/board/amlogic/sm1_elaine_p2/sm1_elaine_p2.c b/board/amlogic/sm1_elaine_p2/sm1_elaine_p2.c
deleted file mode 100755
index fc96071..0000000
--- a/board/amlogic/sm1_elaine_p2/sm1_elaine_p2.c
+++ /dev/null
@@ -1,1165 +0,0 @@
-
-/*
- * board/amlogic/sm1_elaine_p1/sm1_elaine_p2.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <malloc.h>
-#include <errno.h>
-#include <environment.h>
-#include <fdt_support.h>
-#include <linux/libfdt.h>
-#include <asm/arch/cpu_id.h>
-#ifdef CONFIG_SYS_I2C_MESON
-#include <i2c.h>
-#include <dt-bindings/i2c/meson-i2c.h>
-#endif
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/pinctrl_init.h>
-#ifdef CONFIG_AML_VPU
-#include <amlogic/media/vpu/vpu.h>
-#endif
-#ifdef CONFIG_AML_VPP
-#include <amlogic/media/vpp/vpp.h>
-#endif
-#ifdef CONFIG_AML_V2_FACTORY_BURN
-#include <amlogic/aml_v2_burning.h>
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
-#ifdef CONFIG_AML_HDMITX
-#include <amlogic/media/vout/hdmitx.h>
-#endif
-#ifdef CONFIG_AML_LCD
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#endif
-#include <asm/arch/bl31_apis.h>
-#include <asm/arch/eth_setup.h>
-#include <phy.h>
-#include <linux/mtd/partitions.h>
-#include <linux/sizes.h>
-#include <asm-generic/gpio.h>
-#include <dm.h>
-#ifdef CONFIG_AML_SPIFC
-#include <amlogic/spifc.h>
-#endif
-#ifdef CONFIG_AML_SPICC
-#include <amlogic/spicc.h>
-#endif
-#include <asm/armv8/mmu.h>
-
-DECLARE_GLOBAL_DATA_PTR;
-
-static int persistent_brightness = -1;
-
-int do_check_fdr_for_backlight_brightness(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-#if defined(CONFIG_NAND_FTS) || defined(CONFIG_MMC_FTS)
-#if defined(CONFIG_NAND_FTS)
- extern bool amlnf_is_inited(void);
- if(!amlnf_is_inited()) {
-#endif
-
-#if defined(CONFIG_MMC_FTS)
- extern bool amlmmc_is_inited(void);
- if (!amlmmc_is_inited()) {
-#endif
-
- return 0;
- }
-
- flash_ts_init();
-
- static const char *fts_key = "bootloader.recovery";
- static const char *fdr = "--wipe_data";
- static const int fdr_len = sizeof(fdr) - 1;
- int i;
-
- char fts_value[256] = { 0 };
- flash_ts_get(fts_key, fts_value, sizeof(fts_value));
- int fts_len = strnlen(fts_value, sizeof(fts_value));
- for (i = 0; i <= fts_len - fdr_len; i++) {
- if (0 == strncmp(fts_value+i, fdr, fdr_len)) {
- printf("Reset persistent brightness.\n");
- writel(0, AO_RTI_STICKY_REG2);
- break;
- }
- }
-#endif
-
- return 0;
-}
-
-U_BOOT_CMD(
- check_fdr_for_backlight_brightness, 1, 0, do_check_fdr_for_backlight_brightness,
- "check FDR for backlight brightness",
- " This command will clear backlight brightness level stored in the sticky register when doing FDR\n"
-);
-
-int serial_set_pin_port(unsigned long port_base)
-{
- //UART in "Always On Module"
- //GPIOAO_0==tx,GPIOAO_1==rx
- //setbits_le32(P_AO_RTI_PIN_MUX_REG,3<<11);
- return 0;
-}
-
-//SOC_VDDCPU_DVFS0
-//#define VDD_CPU_DVFS0_EN_1 GPIOEE(GPIOZ_13)
-#define VDD_CPU_DVFS0_EN_1_NAME "GPIOZ_13"
-
-//SOC_VDDEE_DVFS0
-//#define VDD_GPU_DVFS0_EN_1 GPIOEE(GPIOA_13)
-#define VDD_GPU_DVFS0_EN_1_NAME "GPIOA_13"
-
-//SOC_VDDEE_DVFS1
-//#define VDD_GPU_DVFS1_EN_1 GPIOEE(GPIOZ_0)
-#define VDD_GPU_DVFS1_EN_1_NAME "GPIOZ_0"
-
-/* setting gpio output/input, and setting High/low level */
-static void gpio_func_set(bool enable, const char* gpio_name, int direction)
-{
- int ret;
- struct gpio_desc gpio_set_desc;
-
- ret = dm_gpio_lookup_name(gpio_name, &gpio_set_desc);
- if (ret) {
- printf("%s: not found\n", gpio_name);
- return ret;
- }
-
- ret = dm_gpio_request(&gpio_set_desc, gpio_name);
- if (ret && ret != -EBUSY) {
- printf("gpio: requesting pin %s failed\n", gpio_name);
- return;
- }
- //gpio_direction_output(BL_ENABLE_PIN, enable ? 1 : 0);
- ret = dm_gpio_set_dir_flags(&gpio_set_desc, direction);
- if (ret) {
- printf("set direction failed\n");
- return ret;
- }
-
- if ( direction == GPIOD_IS_OUT)
- dm_gpio_set_value(&gpio_set_desc, enable ? 1 : 0);
-}
-static void CPU_GPU_Voltage_init(void)
-{
- int ret;
- // setting GPIOZ_13 output & High
- gpio_func_set(1, VDD_CPU_DVFS0_EN_1_NAME, GPIOD_IS_OUT);
-
- //GPU , setting GPIOA_13 output & low
- gpio_func_set(0, VDD_GPU_DVFS0_EN_1_NAME, GPIOD_IS_OUT);
-
- // setting GPIOZ_0 output & low
- gpio_func_set(1, VDD_GPU_DVFS1_EN_1_NAME, GPIOD_IS_OUT);
-}
-
-// Disable GPIOZ_2, GPIOZ_3, GPIOZ_7, GPIOZ_8, GPIOZ_0, GPIOAO_4's pull-up
-// so the mute switch and HW id can be read.
-static void gpio_disable_pull(void)
-{
- int ret;
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 2)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 7)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 8)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1 << 3)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(PAD_PULL_UP_EN_REG4);
- writel(ret & (~(1)), PAD_PULL_UP_EN_REG4);
-
- ret = readl(AO_RTI_PULL_UP_EN_REG);
- writel(ret & (~(1 << 4)), AO_RTI_PULL_UP_EN_REG);
-}
-
-int do_get_elaine_hw_id(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- unsigned int hw_id = 0, ret = 0;
- char hw_id_str[8] = {0}; // eg: 0x0A
-
- // Reading from highest bit to lowest bit
- // HW_ID_4: GPIOAO_4
- ret = readl(P_AO_GPIO_I);
- hw_id |= (ret & (1<<4)) >> 4;
- hw_id = hw_id << 1;
-
- // HW_ID_3: GPIOZ_0
- ret = readl(P_PREG_PAD_GPIO4_I);
- hw_id |= (ret & 1);
- hw_id = hw_id << 1;
-
- // HW_ID_2: GPIOZ_3
- ret = readl(P_PREG_PAD_GPIO4_I);
- hw_id |= (ret & (1<<3)) >> 3;
- hw_id = hw_id << 1;
-
- // HW_ID_1: GPIOZ_8
- ret = readl(P_PREG_PAD_GPIO4_I);
- hw_id |= (ret & (1<<8)) >> 8;
- hw_id = hw_id << 1;
-
- // HW_ID_0: GPIOZ_7
- ret = readl(P_PREG_PAD_GPIO4_I);
- hw_id |= (ret & (1<<7)) >> 7;
-
- snprintf(hw_id_str, sizeof(hw_id_str), "0x%02x", hw_id);
- env_set("hw_id", hw_id_str);
- return 0;
-}
-
-U_BOOT_CMD(
- get_elaine_hw_id, 1, 0, do_get_elaine_hw_id,
- "get elaine's HW_ID and env_set 'hw_id'\n",
- "get_elaine_hw_id"
-);
-
-#define BOOST_ENABLE_PIN_NAME "GPIOA_0"
-int do_enable_amp_boost(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- gpio_func_set(1, BOOST_ENABLE_PIN_NAME, GPIOD_IS_OUT);
-}
-
-U_BOOT_CMD(
- enable_amp_boost, 1, 0, do_enable_amp_boost,
- "Enable the audio amplifier boost\n",
- "enable_boost"
-);
-
-//SOC_DISP_ID
-//#define DISP_ID_PIN GPIOEE(GPIOH_5)
-#define DISP_ID_PIN_NAME "GPIOH_5"
-
-static void panel_detect_init(void)
-{
- // setting GPIOH_5 output & High
- gpio_func_set(1, DISP_ID_PIN_NAME, GPIOD_IS_IN);
-}
-
-//SOC_BL_ENABLE
-//#define BL_ENABLE_PIN GPIOEE(GPIOA_10)
-#define BL_ENABLE_PIN_NAME "GPIOA_10"
-
-static void enable_backlight(bool enable)
-{
- // setting GPIOH_5 output & High
- gpio_func_set(enable, BL_ENABLE_PIN_NAME, GPIOD_IS_OUT);
-}
-
-int dram_init(void)
-{
- gd->ram_size = PHYS_SDRAM_1_SIZE;
- return 0;
-}
-
-/* secondary_boot_func
- * this function should be write with asm, here, is is only for compiling pass
- * */
-void secondary_boot_func(void)
-{
-}
-
-#if CONFIG_AML_SD_EMMC
-#include <mmc.h>
-#include <asm/arch/sd_emmc.h>
-static int sd_emmc_init(unsigned port)
-{
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
- //todo add card detect
- /* check card detect */
- clrbits_le32(P_PERIPHS_PIN_MUX_9, 0xF << 24);
- setbits_le32(P_PREG_PAD_GPIO1_EN_N, 1 << 6);
- setbits_le32(P_PAD_PULL_UP_EN_REG1, 1 << 6);
- setbits_le32(P_PAD_PULL_UP_REG1, 1 << 6);
- break;
- case SDIO_PORT_C:
- //enable pull up
- //clrbits_le32(P_PAD_PULL_UP_REG3, 0xff<<0);
- break;
- default:
- break;
- }
-
- return cpu_sd_emmc_init(port);
-}
-
-extern unsigned sd_debug_board_1bit_flag;
-
-static void sd_emmc_pwr_prepare(unsigned port)
-{
- cpu_sd_emmc_pwr_prepare(port);
-}
-
-static void sd_emmc_pwr_on(unsigned port)
-{
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
-// clrbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
-// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
- /// @todo NOT FINISH
- break;
- case SDIO_PORT_C:
- break;
- default:
- break;
- }
- return;
-}
-static void sd_emmc_pwr_off(unsigned port)
-{
- /// @todo NOT FINISH
- switch (port)
- {
- case SDIO_PORT_A:
- break;
- case SDIO_PORT_B:
-// setbits_le32(P_PREG_PAD_GPIO5_O,(1<<31)); //CARD_8
-// clrbits_le32(P_PREG_PAD_GPIO5_EN_N,(1<<31));
- break;
- case SDIO_PORT_C:
- break;
- default:
- break;
- }
- return;
-}
-
-// #define CONFIG_TSD 1
-static void board_mmc_register(unsigned port)
-{
- struct aml_card_sd_info *aml_priv=cpu_sd_emmc_get(port);
- if (aml_priv == NULL)
- return;
-
- aml_priv->sd_emmc_init=sd_emmc_init;
- aml_priv->sd_emmc_detect=sd_emmc_detect;
- aml_priv->sd_emmc_pwr_off=sd_emmc_pwr_off;
- aml_priv->sd_emmc_pwr_on=sd_emmc_pwr_on;
- aml_priv->sd_emmc_pwr_prepare=sd_emmc_pwr_prepare;
- aml_priv->desc_buf = malloc(NEWSD_MAX_DESC_MUN*(sizeof(struct sd_emmc_desc_info)));
-
- if (NULL == aml_priv->desc_buf)
- printf(" desc_buf Dma alloc Fail!\n");
- else
- printf("aml_priv->desc_buf = 0x%p\n",aml_priv->desc_buf);
-
- sd_emmc_register(aml_priv);
-}
-int board_mmc_init(bd_t *bis)
-{
-#ifdef CONFIG_VLSI_EMULATOR
- //board_mmc_register(SDIO_PORT_A);
-#else
- //board_mmc_register(SDIO_PORT_B);
-#endif
- board_mmc_register(SDIO_PORT_B);
- board_mmc_register(SDIO_PORT_C);
-// board_mmc_register(SDIO_PORT_B1);
- return 0;
-}
-#endif
-
-/* Skip the first line and parse one uint
- * Return negative if not found */
-int parse_calibration_file_string(const char *str)
-{
- if (str == NULL)
- return -EINVAL;
-
- str = strchr(str, '\n');
- if (str == NULL)
- return -EINVAL;
- ++str;
-
- return simple_strtoul(str, NULL, 10);
-}
-
-/* If zero, this value has not been set and the default brightness should not be
- * overwritten. To store zero, store a non-zero value with its bottom 12 bits
- * all zero, like 0x1000.
- */
-int get_persistent_brightness_from_reg(void)
-{
- u32 brightness_sticky_val = readl(AO_RTI_STICKY_REG2);
- if (brightness_sticky_val != 0)
- return (brightness_sticky_val & 0x0fff) >> 1;
- return -1;
-}
-
-int do_configure_backlight(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
-#ifdef CONFIG_SYS_I2C_MESON
- int ret, i, attempt;
- const int retries = 3;
- char *addr_cal;
- int calibrated_current;
-
- /* Values to write:
- * [0]: Brightness register control only, backlight enabled
- * [1-2]: Standby disabled, 20mA MAX_CURRENT, CURRENT scale 1/2
- * [3]: Enable undervoltage protection at 5.2 V, "disable" backlight
- * (i2c only), disable set resistors
- * [4]: 9.6kHz PWM rate, 3 phase drivers
- * [5]: EN_DRV3, EN_DRV2, boost inductor current limit = 1.6 A
- * [6]: VBOOST_MAX = 25 V, JUMP_EN = 0
- * [7]: STEP_UP = 105 mV, STEP_DN = 105 mV, LED_FAULT_TH = 3V,
- * LED_COMP_HYST = DRIVER_HEADROOM + 750 mV
- * [8-9]: 12-bit brightness (default: 100%)
- * Important: Write brightness last to apply current calibration */
- const __u8 addrs[] = {0x01, 0xa0, 0xa1, 0xa2, 0xa5, 0xa7, 0xa9, 0xae,
- 0x10, 0x11};
- __u8 values[] = {0x85, 0xff, 0x37, 0x30, 0x54, 0xf4, 0x60, 0x09, 0xff,
- 0x0f};
- const int n_bytes = sizeof(values)/sizeof(values[0]);
- struct udevice *bl_devp = NULL;
-
- if (argc > 2) {
- printf("%s: Too many args: %d\n", __func__, argc);
- return CMD_RET_USAGE;
- }
-
- if (argc == 2) {
- addr_cal = (char *)simple_strtoul(argv[1], NULL, 16);
- calibrated_current = parse_calibration_file_string(addr_cal);
- if (calibrated_current >= 0 && calibrated_current <= 4095) {
- /* CURRENT_LSB */
- values[1] = 0xff & calibrated_current;
- /* CURRENT_MSB */
- values[2] = (values[2] & 0xf0) |
- (0x0f & (calibrated_current >> 8));
- }
- }
-
- // Apply persistent brightness if found
- if (persistent_brightness >= 0) {
-#ifdef BL33_DEBUG_PRINT
- printf("Applying persistent_brightness=%d\n", persistent_brightness);
-#endif
- /* Get LSB and MSB */
- values[n_bytes - 2] = persistent_brightness & 0xff;
- values[n_bytes - 1] = persistent_brightness >> 8 & 0x0f;
- } else {
-#ifdef BL33_DEBUG_PRINT
- printf("Persistent_brightness not set\n");
-#endif
- }
-
- enable_backlight(true);
-
- ret = i2c_get_chip_for_busnum(MESON_I2C_M3, 0X2c, 1, &bl_devp);
- if (ret) {
- printf("%s(%d):i2c get bus fail!\n", __func__, __LINE__);
- return -1;
- }
- //i2c_set_bus_num(AML_I2C_MASTER_D);
- for (i = 0; i < n_bytes; ++i) {
- for (attempt = 0; attempt < retries; ++attempt) {
- ret = dm_i2c_write(bl_devp, addrs[i], &values[i], 1);
- if (ret)
- printf("%s: Attempt=%d to write byte=0x%02x to reg=0x%02x of backlight failed\n",
- __func__, attempt, values[i], addrs[i]);
- else
- break;
- }
- }
-
- return ret;
-#else
- enable_backlight(true);
-
- return 0;
-#endif /* CONFIG_SYS_I2C_MESON */
-}
-
-U_BOOT_CMD(
- configure_backlight, 2, 0, do_configure_backlight,
- "configures the lp8556 backlight",
- "Usage: configure_backlight [calibration_string_addr]\n"\
- " Sets up required parameters of the backlight.\n"\
- " Default calibration is 100%.\n"\
- " calibration_str_addr (optional):\n"\
- " Address of calibration file string to parse.\n"
-);
-
-int do_get_cached_brightness(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- char *file_str_addr;
-
- if (argc > 2) {
- printf("%s: Too many args: %d\n", __func__, argc);
- return CMD_RET_USAGE;
- }
-
- // Apply persistent brightness if found in sticky register.
- persistent_brightness = get_persistent_brightness_from_reg();
- if (persistent_brightness >= 0) {
- return 0;
- }
-
- if (argc != 2) {
- return 0;
- }
-
-#ifdef BL33_DEBUG_PRINT
- printf("Don't have the sticky register set. Will read from cached brightness on disk.", persistent_brightness);
-#endif
-
- file_str_addr = (char *)simple_strtoul(argv[1], NULL, 16);
-
- if (file_str_addr) {
- // The file should be consist of one number.
- persistent_brightness = simple_strtoul(file_str_addr, NULL, 10);
-#ifdef BL33_DEBUG_PRINT
- printf("Applying brightness from file %d", file_str_addr, persistent_brightness);
-#endif
- }
- return 0;
-}
-
-U_BOOT_CMD(
- get_cached_brightness, 2, 0, do_get_cached_brightness,
- "Gets the cached backlight value",
- "Usage: get_cached_brightness [brightness_str_address]\n"\
- " Gets the cached backlight value.\n"\
- " brightness_str_addr (optional):\n"\
- " Address of cached brightness file string to parse.\n"
-);
-
-#ifdef CONFIG_AML_LCD
-/* Parses one line of the gamma calibration file. */
-/* Returns true on success. */
-#define GAMMA_SIZE (256)
-bool parse_gamma_string(const char *str, uint16_t *table)
-{
- char buf[4] = {'\0'};
- int i;
-
- for (i = 0; i < GAMMA_SIZE; ++i) {
- strncpy(buf, &str[3 * i], 3);
- table[i] = simple_strtol(buf, NULL, 16);
- }
-
- return true;
-}
-
-/* Check header then parse RGB gamma tables */
-/* Returns negative value on error */
-int parse_gamma_calibration_file_string(const char *str, u16 *r, u16 *g, u16 *b)
-{
- static const char supported_header_prefix[] = "Gamma Calibration 1.";
- static const int length = sizeof(supported_header_prefix) - 1;
- char *tables[3] = {r, g, b};
- const char *start, *end;
- int i;
-
- if (!str)
- return -EINVAL;
-
- // Check header prefix - only care about major version.
- if (strncmp(str, supported_header_prefix, length) != 0) {
- printf("Unknown gamma header: \"%.*s\"\n", length, str);
- return -EINVAL;
- }
-
- // Parse all three tables
- end = strchr(str, '\n');
- for (i = 0; i < 3; ++i) {
- start = end + 1;
- end = strchr(start, '\n');
-
- if ((end - start) / 3 != GAMMA_SIZE) {
- printf("Gamma table has invalid length.\n");
- return -EINVAL;
- }
- if (!parse_gamma_string(start, tables[i])) {
- printf("Could not parse gamma table %d.\n", i);
- return -EINVAL;
- }
- }
-
- return 0;
-}
-#endif // CONFIG_AML_LCD
-
-int do_configure_gamma(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
-#ifdef CONFIG_AML_LCD
- static const int N_CHAN = 3;
- char *addr_cal;
- u16 gamma_tables[N_CHAN][GAMMA_SIZE];
- int i, j;
-
- if (argc == 1) {
- // Set to default
- for (i = 0; i < N_CHAN; ++i) {
- for (j = 0; j < GAMMA_SIZE; ++j)
- gamma_tables[i][j] = j << 2; /* 10-bit */
- }
- } else if (argc == 2) {
- // Load from passed file string
- addr_cal = (char *)simple_strtoul(argv[1], NULL, 16);
- if (parse_gamma_calibration_file_string(addr_cal,
- &gamma_tables[0],
- &gamma_tables[1],
- &gamma_tables[2]) != 0)
- return -EINVAL; // Error logged
- } else {
- return CMD_RET_USAGE;
- }
-
- vpp_set_rgb_gamma_table(&gamma_tables[0], &gamma_tables[1],
- &gamma_tables[2]);
-#endif // CONFIG_AML_LCD
- return 0;
-}
-
-U_BOOT_CMD(configure_gamma, 2, 0, do_configure_gamma,
- "configures gamma the gamma tables with the provided calibration\n",
- "Usage: configure_gamma [calibration_string_addr]\n"\
- " Applies the provided calibration file.\n"\
- " If a file is not provided, sets tables to default.\n"\
- " calibration_str_addr (optional):\n"\
- " Address of the calibration file string to parse.\n"
-);
-
-int do_get_chiptype(cmd_tbl_t *cmdtp, int flag, int argc,
- char * const argv[])
-{
- char *type[] = {"SS", "TT", "FF"};
- unsigned int dvfs_id = aml_get_dvfs_id();
- printf("get dvfs_id:%d\n", dvfs_id);
- if (dvfs_id > 2) {
- printf("fail to get dvfs id\n");
- dvfs_id = 0;
- }
- env_set("chip_type", type[dvfs_id]);
- return 0;
-}
-U_BOOT_CMD(get_chiptype, 1, 0, do_get_chiptype,
- "get elaine's chip type and env_set 'chip_type'\n",
- "get_chiptype"
-);
-
-#if defined(CONFIG_BOARD_EARLY_INIT_F)
-int board_early_init_f(void){
- /*add board early init function here*/
- return 0;
-}
-#endif
-
-#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
-#include <asm/arch/usb-v2.h>
-#include <asm/arch/gpio.h>
-#define CONFIG_GXL_USB_U2_PORT_NUM 2
-
-#ifdef CONFIG_USB_XHCI_AMLOGIC_USB3_V2
-#define CONFIG_GXL_USB_U3_PORT_NUM 1
-#else
-#define CONFIG_GXL_USB_U3_PORT_NUM 0
-#endif
-
-static void gpio_set_vbus_power(char is_power_on)
-{
- int ret;
-
- ret = gpio_request(CONFIG_USB_GPIO_PWR,
- CONFIG_USB_GPIO_PWR_NAME);
- if (ret && ret != -EBUSY) {
- printf("gpio: requesting pin %u failed\n",
- CONFIG_USB_GPIO_PWR);
- return;
- }
-
- if (is_power_on) {
- gpio_direction_output(CONFIG_USB_GPIO_PWR, 1);
- } else {
- gpio_direction_output(CONFIG_USB_GPIO_PWR, 0);
- }
-}
-
-struct amlogic_usb_config g_usb_config_GXL_skt={
- CONFIG_GXL_XHCI_BASE,
- USB_ID_MODE_HARDWARE,
- gpio_set_vbus_power,//gpio_set_vbus_power, //set_vbus_power
- CONFIG_GXL_USB_PHY2_BASE,
- CONFIG_GXL_USB_PHY3_BASE,
- CONFIG_GXL_USB_U2_PORT_NUM,
- CONFIG_GXL_USB_U3_PORT_NUM,
- .usb_phy2_pll_base_addr = {
- CONFIG_USB_PHY_20,
- CONFIG_USB_PHY_21,
- }
-};
-
-#endif /*CONFIG_USB_XHCI_AMLOGIC*/
-
-#ifdef CONFIG_AML_HDMITX20
-static void hdmi_tx_set_hdmi_5v(void)
-{
-}
-#endif
-
-/*
- * mtd nand partition table, only care the size!
- * offset will be calculated by nand driver.
- */
-#ifdef CONFIG_AML_MTD
-static struct mtd_partition normal_partition_info[] = {
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- /* MUST NOT CHANGE this part unless u know what you are doing!
- * inherent parition for descrete bootloader to store fip
- * size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
- * name must be same with TPL_PART_NAME
- */
- {
- .name = "tpl",
- .offset = 0,
- .size = 0,
- },
-#endif
- {
- .name = "fts",
- .offset = 0,
- .size = 1*SZ_1M,
- },
- {
- .name = "factory",
- .offset = 0,
- .size = 8*SZ_1M,
- },
- {
- .name = "recovery",
- .offset = 0,
- .size = 16*SZ_1M,
- },
- {
- .name = "boot",
- .offset = 0,
- .size = 16*SZ_1M,
- },
- {
- .name = "system",
- .offset = 0,
- .size = 220*SZ_1M,
- },
- /* last partition get the rest capacity */
- {
- .name = "cache",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
- },
-};
-struct mtd_partition *get_aml_mtd_partition(void)
-{
- return normal_partition_info;
-}
-int get_aml_partition_count(void)
-{
- return ARRAY_SIZE(normal_partition_info);
-}
-#endif /* CONFIG_AML_MTD */
-
-#ifdef CONFIG_AML_SPIFC
-/*
- * BOOT_3: NOR_HOLDn:reg0[15:12]=3
- * BOOT_4: NOR_D:reg0[19:16]=3
- * BOOT_5: NOR_Q:reg0[23:20]=3
- * BOOT_6: NOR_C:reg0[27:24]=3
- * BOOT_7: NOR_WPn:reg0[31:28]=3
- * BOOT_14: NOR_CS:reg1[27:24]=3
- */
-#define SPIFC_NUM_CS 1
-static int spifc_cs_gpios[SPIFC_NUM_CS] = {54};
-
-static int spifc_pinctrl_enable(void *pinctrl, bool enable)
-{
- unsigned int val;
-
- val = readl(P_PERIPHS_PIN_MUX_0);
- val &= ~(0xfffff << 12);
- if (enable)
- val |= 0x33333 << 12;
- writel(val, P_PERIPHS_PIN_MUX_0);
-
- val = readl(P_PERIPHS_PIN_MUX_1);
- val &= ~(0xf << 24);
- writel(val, P_PERIPHS_PIN_MUX_1);
- return 0;
-}
-
-#if 0
-static const struct spifc_platdata spifc_platdata = {
- .reg = 0xffd14000,
- .mem_map = 0xf6000000,
- .pinctrl_enable = spifc_pinctrl_enable,
- .num_chipselect = SPIFC_NUM_CS,
- .cs_gpios = spifc_cs_gpios,
-};
-
-U_BOOT_DEVICE(spifc) = {
- .name = "spifc",
- .platdata = &spifc_platdata,
-};
-#endif
-#endif /* CONFIG_AML_SPIFC */
-
-#if 0
-#ifdef CONFIG_AML_SPICC
-/* generic config in arch gpio/clock.c */
-extern int spicc1_clk_set_rate(int rate);
-extern int spicc1_clk_enable(bool enable);
-extern int spicc1_pinctrl_enable(bool enable);
-
-static const struct spicc_platdata spicc1_platdata = {
- .compatible = "amlogic,meson-g12a-spicc",
- .reg = (void __iomem *)0xffd15000,
- .clk_rate = 666666666,
- .clk_set_rate = spicc1_clk_set_rate,
- .clk_enable = spicc1_clk_enable,
- .pinctrl_enable = spicc1_pinctrl_enable,
- /* case one slave without cs: {"no_cs", 0} */
- .cs_gpio_names = {"GPIOH_6", 0},
-};
-
-U_BOOT_DEVICE(spicc1) = {
- .name = "spicc",
- .platdata = &spicc1_platdata,
-};
-#endif /* CONFIG_AML_SPICC */
-#endif
-
-extern void aml_pwm_cal_init(int mode);
-
-int board_init(void)
-{
- printf("board init\n");
-
- /*in kernel P_RESET1_LEVEL has been clear,
- * uboot need set these bits about usb,
- * otherwise the usb has problem.
- */
- *(volatile uint32_t *)P_RESET1_LEVEL |= (3 << 16);
- //CPU_GPU_Voltage_init();
- enable_backlight(false);
- panel_detect_init();
-//Please keep CONFIG_AML_V2_FACTORY_BURN at first place of board_init
-//As NOT NEED other board init If USB BOOT MODE
-#ifdef CONFIG_AML_V2_FACTORY_BURN
- if ((0x1b8ec003 != readl(P_PREG_STICKY_REG2)) && (0x1b8ec004 != readl(P_PREG_STICKY_REG2))) {
- aml_try_factory_usb_burning(0, gd->bd);
- }
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
-
- pinctrl_devices_active(PIN_CONTROLLER_NUM);
-#ifdef CONFIG_USB_XHCI_AMLOGIC_V2
- board_usb_pll_disable(&g_usb_config_GXL_skt);
- board_usb_init(&g_usb_config_GXL_skt,BOARD_USB_MODE_HOST);
-#endif /*CONFIG_USB_XHCI_AMLOGIC*/
-
- /* TODO(b/110040521): This is the earliest the backlight can be started,
- * but the LCD is not running yet. */
-
-#if 0
- aml_pwm_cal_init(0);
-#endif//
-#ifdef CONFIG_AML_NAND
- extern int amlnf_init(unsigned char flag);
- amlnf_init(0);
-#endif
- gpio_disable_pull();
-
- return 0;
-}
-
-#ifdef CONFIG_BOARD_LATE_INIT
-int board_late_init(void)
-{
- printf("board late init\n");
- run_command("mmc dev 1", 0);
- run_command("run detect_panel", 0);
-#if 0
- //update env before anyone using it
- run_command("get_rebootmode; echo reboot_mode=${reboot_mode}; "\
- "if test ${reboot_mode} = factory_reset; then "\
- "defenv_reserv aml_dt;setenv upgrade_step 2;save; fi;", 0);
- run_command("if itest ${upgrade_step} == 1; then "\
- "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
- /*add board late init function here*/
-#ifndef DTB_BIND_KERNEL
- int ret;
- ret = run_command("store dtb read $dtb_mem_addr", 1);
- if (ret) {
- printf("%s(): [store dtb read $dtb_mem_addr] fail\n", __func__);
-#ifdef CONFIG_DTB_MEM_ADDR
- char cmd[64];
- printf("load dtb to %x\n", CONFIG_DTB_MEM_ADDR);
- sprintf(cmd, "store dtb read %x", CONFIG_DTB_MEM_ADDR);
- ret = run_command(cmd, 1);
- if (ret) {
- printf("%s(): %s fail\n", __func__, cmd);
- }
-#endif
- }
-#elif defined(CONFIG_DTB_MEM_ADDR)
- {
- char cmd[128];
- int ret;
- if (!getenv("dtb_mem_addr")) {
- sprintf(cmd, "setenv dtb_mem_addr 0x%x", CONFIG_DTB_MEM_ADDR);
- run_command(cmd, 0);
- }
- sprintf(cmd, "imgread dtb boot ${dtb_mem_addr}");
- ret = run_command(cmd, 0);
- if (ret) {
- printf("%s(): cmd[%s] fail, ret=%d\n", __func__, cmd, ret);
- }
- }
-#endif// #ifndef DTB_BIND_KERNEL
-
- /* load unifykey */
- run_command("keyunify init 0x1234", 0);
-#endif
-/*open vpu hdmitx and cvbs driver*/
-#ifdef CONFIG_AML_VPU
- vpu_probe();
-#endif
-
-#ifdef CONFIG_AML_VPP
- vpp_init();
-#endif
-
-#ifdef CONFIG_AML_HDMITX
- hdmi_tx_init();
-#endif
-#ifdef CONFIG_AML_CVBS
- run_command("cvbs init", 0);
-#endif
-#ifdef CONFIG_AML_LCD
- lcd_probe();
-#endif
-
-#ifdef CONFIG_AML_V2_FACTORY_BURN
- if (0x1b8ec003 == readl(P_PREG_STICKY_REG2))
- aml_try_factory_usb_burning(1, gd->bd);
- aml_try_factory_sdcard_burning(0, gd->bd);
-#endif// #ifdef CONFIG_AML_V2_FACTORY_BURN
- return 0;
-}
-#endif
-
-#ifdef CONFIG_AML_TINY_USBTOOL
-int usb_get_update_result(void)
-{
- unsigned long upgrade_step;
- upgrade_step = simple_strtoul (getenv ("upgrade_step"), NULL, 16);
- printf("upgrade_step = %d\n", (int)upgrade_step);
- if (upgrade_step == 1)
- {
- run_command("defenv", 1);
- run_command("env_set upgrade_step 2", 1);
- run_command("saveenv", 1);
- return 0;
- }
- else
- {
- return -1;
- }
-}
-#endif
-
-phys_size_t get_effective_memsize(void)
-{
- // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
-#if defined(CONFIG_SYS_MEM_TOP_HIDE)
- return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
-#else
- return (((readl(AO_SEC_GP_CFG0)) & 0xFFFF0000) << 4);
-#endif
-}
-
-#ifdef CONFIG_MULTI_DTB
-int checkhw(char * name)
-{
- /*
- * read board hw id
- * set and select the dts according the board hw id.
- *
- * hwid = 1 p321 v1
- * hwid = 2 p321 v2
- */
- unsigned int hwid = 1;
- char loc_name[64] = {0};
-
- /* read hwid */
- hwid = (readl(P_AO_SEC_GP_CFG0) >> 8) & 0xFF;
-
- printf("checkhw: hwid = %d\n", hwid);
-
-
- switch (hwid) {
- case 1:
- strcpy(loc_name, "txl_p321_v1\0");
- break;
- case 2:
- strcpy(loc_name, "txl_p321_v2\0");
- break;
- default:
- strcpy(loc_name, "txl_p321_v1");
- break;
- }
- strcpy(name, loc_name);
- env_set("aml_dt", loc_name);
- return 0;
-}
-#endif
-
-/* workaround for VDDEE issue */
-/* VCCK PWM table */
-#define VCCK_VAL_REG_800 0x00150007
-#define VCCK_VAL_REG_810 0x00140008
-#define VCCK_VAL_REG_820 0x00130009
-#define VCCK_VAL_REG_830 0x0012000a
-#define VCCK_VAL_REG_840 0x0011000b
-#define VCCK_VAL_REG_850 0x0010000c
-#define VCCK_VAL_REG_860 0x000f000d
-#define VCCK_VAL_REG_870 0x000e000e
-#define VCCK_VAL_REG_880 0x000d000f
-#define VCCK_VAL_REG_890 0x000c0010
-#define VCCK_VAL_REG_900 0x000b0011
-#define VCCK_VAL_REG_910 0x000a0012
-#define VCCK_VAL_REG_920 0x00090013
-#define VCCK_VAL_REG_930 0x00080014
-#define VCCK_VAL_REG_940 0x00070015
-#define VCCK_VAL_REG_950 0x00060016
-#define VCCK_VAL_REG_960 0x00050017
-#define VCCK_VAL_REG_970 0x00040018
-#define VCCK_VAL_REG_980 0x00030019
-#define VCCK_VAL_REG_990 0x0002001a
-#define VCCK_VAL_REG_1000 0x0001001b
-#define VCCK_VAL_REG_1010 0x0000001c
-#define VCCK_VAL_REG_DEFAULT 0x00500008
-
-/* VDDEE PWM table */
-#define VDDEE_VAL_REG_800 0x0010000c
-#define VDDEE_VAL_REG_810 0x000f000d
-#define VDDEE_VAL_REG_820 0x000e000e
-#define VDDEE_VAL_REG_830 0x000d000f
-#define VDDEE_VAL_REG_840 0x000c0010
-#define VDDEE_VAL_REG_850 0x000b0011
-#define VDDEE_VAL_REG_860 0x000a0012
-#define VDDEE_VAL_REG_870 0x00090013
-#define VDDEE_VAL_REG_880 0x00080014
-#define VDDEE_VAL_REG_890 0x00070015
-#define VDDEE_VAL_REG_900 0x00060016
-#define VDDEE_VAL_REG_910 0x00050017
-#define VDDEE_VAL_REG_920 0x00040018
-#define VDDEE_VAL_REG_930 0x00030019
-#define VDDEE_VAL_REG_940 0x0002001a
-#define VDDEE_VAL_REG_950 0x0001001b
-#define VDDEE_VAL_REG_960 0x0000001c
-#define VDDEE_VAL_REG_DEFAULT 0x00500008
-
-void reset_misc(void)
-{
- unsigned int value;
-
- /* adjust VDDCPU to Hiz value step by step */
- writel(VCCK_VAL_REG_830, AO_PWM_PWM_D);
- udelay(1);
- writel(VCCK_VAL_REG_860, AO_PWM_PWM_D);
- udelay(1);
-
- /* GPIOE_0 & GPIOE_1 to gpio pin */
- value = readl(AO_RTI_PINMUX_REG1);
- value &= ~(0xff << 16);
- writel(value, AO_RTI_PINMUX_REG1);
-
- /* disable pwm_ao_b - VDDEE */
- value = readl(AO_PWM_MISC_REG_AB);
- value &= ~((0x1 << 1) | (0x1 << 23));
- writel(value, AO_PWM_MISC_REG_AB);
- writel(VDDEE_VAL_REG_DEFAULT, AO_PWM_PWM_B);
-
- /* disable pwm_ao_d - VDDCPU_B*/
- value = readl(AO_PWM_MISC_REG_CD);
- value &= ~((0x1 << 1) | (0x1 << 23));
- writel(value, AO_PWM_MISC_REG_CD);
- writel(VCCK_VAL_REG_DEFAULT, AO_PWM_PWM_D);
-}
-
-static struct mm_region bd_mem_map[] = {
- {
- .virt = 0x0UL,
- .phys = 0x0UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
- PTE_BLOCK_INNER_SHARE
- }, {
- .virt = 0x80000000UL,
- .phys = 0x80000000UL,
- .size = 0x80000000UL,
- .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
- PTE_BLOCK_NON_SHARE |
- PTE_BLOCK_PXN | PTE_BLOCK_UXN
- }, {
- /* List terminator */
- 0,
- }
-};
-
-struct mm_region *mem_map = bd_mem_map;
-
-void board_nand_init(void) {
- printf("board_nand_init\n");
- return;
-}
-
-int print_cpuinfo(void) {
- printf("print_cpuinfo\n");
- return 0;
-}
-
-int mach_cpu_init(void) {
- printf("mach_cpu_init\n");
- return 0;
-}
-
-int ft_board_setup(void *blob, bd_t *bd)
-{
- /* eg: bl31/32 rsv */
- return 0;
-}
diff --git a/board/amlogic/sm1_elaine_p2/zircon.c b/board/amlogic/sm1_elaine_p2/zircon.c
deleted file mode 100644
index 8e6888f..0000000
--- a/board/amlogic/sm1_elaine_p2/zircon.c
+++ /dev/null
@@ -1,295 +0,0 @@
-/*
- * Copyright (c) 2018 The Fuchsia Authors
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#include <common.h>
-#include <linux/mtd/partitions.h>
-#include <nand.h>
-#include <part.h>
-#include <emmc_storage.h>
-#include <zircon/zircon.h>
-
-#define PDEV_VID_GOOGLE 3
-#define PDEV_PID_ASTRO 3
-
-#define NVRAM_LENGTH (8 * 1024)
-
-const char* BOOTLOADER_VERSION = "zircon-bootloader=0.10";
-
-static const zbi_cpu_config_t cpu_config = {
- .cluster_count = 1,
- .clusters = {
- {
- .cpu_count = 4,
- },
- },
-};
-
-static const zbi_mem_range_t mem_config[] = {
- {
- .type = ZBI_MEM_RANGE_RAM,
- .length = 0x60000000, // 1.5 GB
- },
- {
- .type = ZBI_MEM_RANGE_PERIPHERAL,
- .paddr = 0xf5800000,
- .length = 0x0a800000,
- },
- // secmon_reserved:linux,secmon
- {
- .type = ZBI_MEM_RANGE_RESERVED,
- .paddr = 0x05000000,
- .length = 0x2400000,
- },
- // logo_reserved:linux,meson-fb
- {
- .type = ZBI_MEM_RANGE_RESERVED,
- .paddr = 0x5f800000,
- .length = 0x800000,
- },
-};
-
-static const dcfg_simple_t uart_driver = {
- .mmio_phys = 0xff803000,
- .irq = 225,
-};
-
-static const dcfg_arm_gicv2_driver_t gicv2_driver = {
- .mmio_phys = 0xffc00000,
- .gicd_offset = 0x1000,
- .gicc_offset = 0x2000,
- .gich_offset = 0x4000,
- .gicv_offset = 0x6000,
- .ipi_base = 5,
-};
-
-static const dcfg_arm_psci_driver_t psci_driver = {
- .use_hvc = false,
- .reboot_args = { 1, 0, 0 },
- .reboot_bootloader_args = { 4, 0, 0 },
- .reboot_recovery_args = { 2, 0, 0 },
-};
-
-static const dcfg_arm_generic_timer_driver_t timer_driver = {
- .irq_phys = 30,
-};
-
-static const zbi_platform_id_t platform_id = {
- .vid = PDEV_VID_GOOGLE,
- .pid = PDEV_PID_ASTRO,
- .board_name = "astro",
-};
-
-enum {
- PART_TPL,
- PART_FTS,
- PART_FACTORY,
- PART_ZIRCON_B,
- PART_ZIRCON_A,
- PART_ZIRCON_R,
- PART_FVM,
- PART_SYS_CONFIG,
- PART_MIGRATION,
- PART_COUNT,
-};
-
-#define RECOVERY_SIZE (16 * 1024 * 1024)
-#define SYS_CONFIG_SIZE (1 * 1024 * 1024)
-#define MIGRATION_SIZE (3 * 1024 * 1024)
-
-static zbi_partition_map_t partition_map = {
- // .block_count filled in below
- // .block_size filled in below
- .guid = {},
- .partition_count = PART_COUNT,
- .partitions = {
- {
- .type_guid = GUID_BOOTLOADER_VALUE,
- .name = "tpl",
- },
- {
- .name = "fts",
- },
- {
- .name = "factory",
- },
- {
- .type_guid = GUID_ZIRCON_R_VALUE,
- .name = "zircon-r",
- },
- {
- .type_guid = GUID_ZIRCON_A_VALUE,
- .name = "zircon-a",
- },
- {
- .type_guid = GUID_ZIRCON_B_VALUE,
- .name = "zircon-b",
- },
- {
- .type_guid = GUID_FVM_VALUE,
- .name = "fvm",
- },
- {
- .type_guid = GUID_SYS_CONFIG_VALUE,
- .name = "sys-config",
- },
- {
- .name = "migration",
- },
- },
-};
-
-extern struct mtd_partition *get_aml_mtd_partition(void);
-extern int get_aml_partition_count(void);
-
-static void add_partition_map(zbi_header_t* zbi) {
- struct mtd_partition* tpl_part = NULL;
- struct mtd_partition* fts_part = NULL;
- struct mtd_partition* factory_part = NULL;
- struct mtd_partition* recovery_part = NULL;
- struct mtd_partition* boot_part = NULL;
- struct mtd_partition* system_part = NULL;
- struct mtd_partition* partitions = get_aml_mtd_partition();
- int partition_count = get_aml_partition_count();
- int i;
-
- for (i = 0; i < partition_count; i++) {
- struct mtd_partition* part = &partitions[i];
- if (!strcmp("tpl", part->name)) {
- tpl_part = part;
- } else if (!strcmp("fts", part->name)) {
- fts_part = part;
- } else if (!strcmp("factory", part->name)) {
- factory_part = part;
- } else if (!strcmp("recovery", part->name)) {
- recovery_part = part;
- } else if (!strcmp("boot", part->name)) {
- boot_part = part;
- } else if (!strcmp("system", part->name)) {
- system_part = part;
- }
- }
-
- if (!tpl_part) {
- printf("could not find tpl partition\n");
- return;
- }
- if (!fts_part) {
- printf("could not find fts partition\n");
- return;
- }
- if (!factory_part) {
- printf("could not find factory partition\n");
- return;
- }
- if (!recovery_part) {
- printf("could not find recovery partition\n");
- return;
- }
- if (!boot_part) {
- printf("could not find boot partition\n");
- return;
- }
- if (!system_part) {
- printf("could not find system partition\n");
- return;
- }
-
- uint32_t block_size = nand_info[1].writesize;
- uint64_t total_size = nand_info[1].size;
-
- partition_map.block_size = block_size;
- partition_map.block_count = total_size / block_size;
-
- // map tpl partition to BOOTLOADER
- partition_map.partitions[PART_TPL].first_block = tpl_part->offset / block_size;
- partition_map.partitions[PART_TPL].last_block =
- ((tpl_part->offset + tpl_part->size) / block_size) - 1;
- // map fts partition to "fts"
- partition_map.partitions[PART_FTS].first_block = fts_part->offset / block_size;
- partition_map.partitions[PART_FTS].last_block =
- ((fts_part->offset + fts_part->size) / block_size) - 1;
- // map factory partition to "factory"
- partition_map.partitions[PART_FACTORY].first_block = factory_part->offset / block_size;
- partition_map.partitions[PART_FACTORY].last_block =
- ((factory_part->offset + factory_part->size) / block_size) - 1;
- // map recovery partition to ZIRCON_B
- partition_map.partitions[PART_ZIRCON_B].first_block = recovery_part->offset / block_size;
- partition_map.partitions[PART_ZIRCON_B].last_block =
- ((recovery_part->offset + recovery_part->size) / block_size) - 1;
- // map boot partition to ZIRCON_A
- partition_map.partitions[PART_ZIRCON_A].first_block = boot_part->offset / block_size;
- partition_map.partitions[PART_ZIRCON_A].last_block =
- ((boot_part->offset + boot_part->size) / block_size) - 1;
- // ZIRCON_R partition at start of system
- partition_map.partitions[PART_ZIRCON_R].first_block = system_part->offset / block_size;
- partition_map.partitions[PART_ZIRCON_R].last_block =
- partition_map.partitions[PART_ZIRCON_R].first_block +
- (RECOVERY_SIZE / block_size) - 1;
- // FVM follows ZIRCON_R
- partition_map.partitions[PART_FVM].first_block =
- partition_map.partitions[PART_ZIRCON_R].last_block + 1;
- partition_map.partitions[PART_FVM].last_block =
- ((total_size - SYS_CONFIG_SIZE - MIGRATION_SIZE) / block_size) - 1;
- // SYS_CONFIG follows FVM
- partition_map.partitions[PART_SYS_CONFIG].first_block =
- partition_map.partitions[PART_FVM].last_block + 1;
- partition_map.partitions[PART_SYS_CONFIG].last_block =
- partition_map.partitions[PART_SYS_CONFIG].first_block +
- (SYS_CONFIG_SIZE / block_size) - 1;
- // MIGRATION follows SYS_CONFIG
- partition_map.partitions[PART_MIGRATION].first_block =
- partition_map.partitions[PART_SYS_CONFIG].last_block + 1;
- partition_map.partitions[PART_MIGRATION].last_block =
- partition_map.partitions[PART_MIGRATION].first_block +
- (MIGRATION_SIZE / block_size) - 1;
-
- printf("Zircon partitions:\n");
- for (i = 0; i < PART_COUNT; i++) {
- printf(" 0x%016llx - 0x%016llx : %s\n",
- partition_map.partitions[i].first_block * block_size,
- (partition_map.partitions[i].last_block + 1) * block_size,
- partition_map.partitions[i].name);
- }
-
- zircon_append_boot_item(zbi, ZBI_TYPE_DRV_PARTITION_MAP, 0, &partition_map,
- sizeof(zbi_partition_map_t) +
- partition_map.partition_count * sizeof(zbi_partition_t));
-}
-
-int zircon_preboot(zbi_header_t* zbi) {
- // add CPU configuration
- zircon_append_boot_item(zbi, ZBI_TYPE_CPU_CONFIG, 0, &cpu_config,
- sizeof(zbi_cpu_config_t) +
- sizeof(zbi_cpu_cluster_t) * cpu_config.cluster_count);
-
- // allocate crashlog save area before 0x5f800000-0x60000000 reserved area
- zbi_nvram_t nvram;
- nvram.base = 0x5f800000 - NVRAM_LENGTH;
- nvram.length = NVRAM_LENGTH;
- zircon_append_boot_item(zbi, ZBI_TYPE_NVRAM, 0, &nvram, sizeof(nvram));
-
- // add memory configuration
- zircon_append_boot_item(zbi, ZBI_TYPE_MEM_CONFIG, 0, &mem_config, sizeof(mem_config));
-
- // add kernel drivers
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_AMLOGIC_UART, &uart_driver,
- sizeof(uart_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_GIC_V2, &gicv2_driver,
- sizeof(gicv2_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_PSCI, &psci_driver,
- sizeof(psci_driver));
- zircon_append_boot_item(zbi, ZBI_TYPE_KERNEL_DRIVER, KDRV_ARM_GENERIC_TIMER, &timer_driver,
- sizeof(timer_driver));
-
- zircon_append_boot_item(zbi, ZBI_TYPE_CMDLINE, 0, BOOTLOADER_VERSION, strlen(BOOTLOADER_VERSION) + 1);
-
- // add platform ID
- zircon_append_boot_item(zbi, ZBI_TYPE_PLATFORM_ID, 0, &platform_id, sizeof(platform_id));
-
- add_partition_map(zbi);
-
- return 0;
-}
diff --git a/board/amlogic/sm1_skt_v1/Kconfig b/board/amlogic/sm1_skt_v1/Kconfig
index 3ab4f3f..672130a 100644
--- a/board/amlogic/sm1_skt_v1/Kconfig
+++ b/board/amlogic/sm1_skt_v1/Kconfig
@@ -20,4 +20,3 @@
default "sm1_skt_v1"
endif
-
diff --git a/board/amlogic/t7_an400_lpddr4x/Kconfig b/board/amlogic/t7_an400_lpddr4x/Kconfig
new file mode 100644
index 0000000..c0bd295
--- /dev/null
+++ b/board/amlogic/t7_an400_lpddr4x/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_T7_AN400_LPDDR4X
+
+config SYS_SOC
+ default "t7"
+
+config SYS_BOARD
+ default "t7_an400_lpddr4x"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "t7_an400_lpddr4x"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+endif
diff --git a/board/amlogic/t7_an400_lpddr4x/Makefile b/board/amlogic/t7_an400_lpddr4x/Makefile
new file mode 100644
index 0000000..1e920e7
--- /dev/null
+++ b/board/amlogic/t7_an400_lpddr4x/Makefile
@@ -0,0 +1,3 @@
+obj-y += $(BOARD).o
+obj-$(CONFIG_AML_LCD) += lcd.o
+
diff --git a/board/amlogic/t7_an400_lpddr4x/firmware/timing.c b/board/amlogic/t7_an400_lpddr4x/firmware/timing.c
new file mode 100644
index 0000000..4a6378d
--- /dev/null
+++ b/board/amlogic/t7_an400_lpddr4x/firmware/timing.c
@@ -0,0 +1,1081 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+#define ENABLE_LPDDR4X_MODE 1
+
+#define AN_408_DDR0_1G_DDR1_0G 0
+#define AN_408_DDR0_2G_DDR1_0G 1
+#define AN_408_DDR0_1G_DDR1_1G 2
+#define AN_408_DDR0_2G_DDR1_1G 3
+#define AN_408_DDR0_2G_DDR1_2G 4
+#define AN_408_DDR0_2G_DDR1_2G_RANK01 5
+#define AN_408_DDR0_4G_DDR1_4G_RANK01 6
+
+#define DDR_SIZE_TYPE_1 AN_408_DDR0_2G_DDR1_1G //AN_408_DDR0_2G_DDR1_0G//AN_408_DDR0_2G_DDR1_1G//AN_408_DDR0_1G_DDR1_1G
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+#if 0
+ {
+ /* tl1 skt (x309) ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq ={ 1200, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x31f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0x23, 0x13 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x0, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 48, //48, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay ={ 32 + 20, 32 + 20, 32 + 20, 32 + 20, 32, 32 + 0, 32 + 20, 32 + 20, 32 + 20, 32 + 20},
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25),
+ [1] = (12 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 13 << 5 | 14 << 10 | 6 << 15 | 0 << 20 | 0 << 25),
+ },
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 00, 00 },
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC_COPY_CHANNEL_CFG, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux =
+ {
+ 2,
+ 5,
+ 20,
+ 14,
+ 8,
+ 24,
+ 4,
+ 13,
+ 25,
+ 12,
+ 10,
+ 23,
+ 26,
+ 18,
+ 0,
+ 0,
+ 0,
+ 9,
+ 1,
+ 19,
+ 0,
+ 22,
+ 11,
+ 7,
+ 6,
+ 3,
+ 0,
+ 0,
+ },
+ .dfi_pinmux =
+ {
+ 18,
+ 15,
+ 16,
+ 12,
+ 5,
+ 20,
+ 10,
+ 7,
+ 0,
+ 11,
+ 14,
+ 8,
+ 23,
+ 17,
+ 3,
+ 13,
+ 22,
+ 2,
+ 21,
+ 19,
+ 6,
+ 4,
+ 1,
+ 0,
+ 0,
+ 0,
+ },
+ },
+#endif
+#if 1
+ {
+ //.fast_boot[0]=0x000000fd,// 253
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .enable_lpddr4x_mode = ENABLE_LPDDR4X_MODE,
+ .DRAMFreq ={ 2016, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xc8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_4G_DDR1_4G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x131f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0, 0 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x3, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 60,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 240,
+ .soc_clk_slew_rate = 0x1ff,
+ .soc_cs_slew_rate = 0x1ff,
+ .soc_ac_slew_rate = 0x1ff,
+ .soc_data_slew_rate = 0x5ff,
+ .vref_output_permil = 629, //300
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 300,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting=0,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay ={ 32 + 10, 32, 0, 0, 0, 32 + 10, 32, 0, 0, 0},
+ //.ac_trace_delay ={ 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32, 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32 + 0},
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25),
+ [1] = (11 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 12 << 5 | 13 << 10 | 14 << 15 | 0 << 20 | 0 << 25),
+ },
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 7, 1, 5, 0, 2, 3, 4, 6,
+ 8, 15, 12, 13, 9, 10, 11, 14,
+ 22, 18, 21, 20, 17, 23, 16, 19,
+ 29, 30, 28, 31, 24, 27, 26, 25 },
+
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, // DDR_FUNC,
+ //.ddr_func = 0, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux ={ 2, 3, 1, 0, 5, 4, 0, 0, 0, 0,
+ 1, 3, 5, 2, 4, 0, 0, 0, 0 },
+
+ .dfi_pinmux =
+ {
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 0,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 0,
+ 0,
+ 0,
+ },
+ },
+
+ {
+ //.fast_boot[0]=0x000000fd,// 253
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .enable_lpddr4x_mode = ENABLE_LPDDR4X_MODE,
+ .DRAMFreq ={ 2016, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xc8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_4G_DDR1_4G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x131f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0, 0 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x3, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 60,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 240,
+ .soc_clk_slew_rate = 0x1ff,
+ .soc_cs_slew_rate = 0x1ff,
+ .soc_ac_slew_rate = 0x1ff,
+ .soc_data_slew_rate = 0x5ff,
+ .vref_output_permil = 629,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 300,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting=0,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ //.ac_trace_delay ={ 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32, 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32 + 0},
+ .ac_trace_delay ={ 32 + 10, 32, 0, 0, 0, 32 + 10, 32, 0, 0, 0},
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25),
+ [1] = (11 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 12 << 5 | 13 << 10 | 14 << 15 | 0 << 20 | 0 << 25),
+ },
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 4, 6, 5, 0, 7, 1, 2, 3,
+ 15, 11, 13, 14, 12, 9, 8, 10,
+ 21, 19, 22, 16, 18, 17, 23, 20,
+ 29, 30, 26, 25, 24, 27, 31, 28 },
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, // DDR_FUNC,
+ //.ddr_func = 0, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux ={ 2, 3, 1, 0, 5, 4, 0, 0, 0, 0,
+ 1, 3, 5, 2, 4, 0, 0, 0, 0 },
+
+ .dfi_pinmux =
+ {
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 0,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 0,
+ 0,
+ 0,
+ },
+ },
+#endif
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .low_console_baud = CONFIG_LOW_CONSOLE_BAUD,
+};
+
+#define VCCK_A_VAL AML_VCCK_A_INIT_VOLTAGE
+#define VCCK_B_VAL AML_VCCK_B_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+#define VDD_GPU_VAL AML_VDDGPU_INIT_VOLTAGE
+#define VDD_NPU_VAL AML_VDDNPU_INIT_VOLTAGE
+#define VDD_DDR_VAL AML_VDDDDR_INIT_VOLTAGE
+
+/* VCCK_A PWM table */
+#if (VCCK_A_VAL == 1039)
+#define VCCK_A_VAL_REG 0x00000022
+#elif (VCCK_A_VAL == 1029)
+#define VCCK_A_VAL_REG 0x00010021
+#elif (VCCK_A_VAL == 1019)
+#define VCCK_A_VAL_REG 0x00020020
+#elif (VCCK_A_VAL == 1009)
+#define VCCK_A_VAL_REG 0x0003001f
+#elif (VCCK_A_VAL == 999)
+#define VCCK_A_VAL_REG 0x0004001e
+#elif (VCCK_A_VAL == 989)
+#define VCCK_A_VAL_REG 0x0005001d
+#elif (VCCK_A_VAL == 979)
+#define VCCK_A_VAL_REG 0x0006001c
+#elif (VCCK_A_VAL == 969)
+#define VCCK_A_VAL_REG 0x0007001b
+#elif (VCCK_A_VAL == 959)
+#define VCCK_A_VAL_REG 0x0008001a
+#elif (VCCK_A_VAL == 949)
+#define VCCK_A_VAL_REG 0x00090019
+#elif (VCCK_A_VAL == 939)
+#define VCCK_A_VAL_REG 0x000a0018
+#elif (VCCK_A_VAL == 929)
+#define VCCK_A_VAL_REG 0x000b0017
+#elif (VCCK_A_VAL == 919)
+#define VCCK_A_VAL_REG 0x000c0016
+#elif (VCCK_A_VAL == 909)
+#define VCCK_A_VAL_REG 0x000d0015
+#elif (VCCK_A_VAL == 899)
+#define VCCK_A_VAL_REG 0x000e0014
+#elif (VCCK_A_VAL == 889)
+#define VCCK_A_VAL_REG 0x000f0013
+#elif (VCCK_A_VAL == 879)
+#define VCCK_A_VAL_REG 0x00100012
+#elif (VCCK_A_VAL == 869)
+#define VCCK_A_VAL_REG 0x00110011
+#elif (VCCK_A_VAL == 859)
+#define VCCK_A_VAL_REG 0x00120010
+#elif (VCCK_A_VAL == 849)
+#define VCCK_A_VAL_REG 0x0013000f
+#elif (VCCK_A_VAL == 839)
+#define VCCK_A_VAL_REG 0x0014000e
+#elif (VCCK_A_VAL == 829)
+#define VCCK_A_VAL_REG 0x0015000d
+#elif (VCCK_A_VAL == 819)
+#define VCCK_A_VAL_REG 0x0016000c
+#elif (VCCK_A_VAL == 809)
+#define VCCK_A_VAL_REG 0x0017000b
+#elif (VCCK_A_VAL == 799)
+#define VCCK_A_VAL_REG 0x0018000a
+#elif (VCCK_A_VAL == 789)
+#define VCCK_A_VAL_REG 0x00190009
+#elif (VCCK_A_VAL == 779)
+#define VCCK_A_VAL_REG 0x001a0008
+#elif (VCCK_A_VAL == 769)
+#define VCCK_A_VAL_REG 0x001b0007
+#elif (VCCK_A_VAL == 759)
+#define VCCK_A_VAL_REG 0x001c0006
+#elif (VCCK_A_VAL == 749)
+#define VCCK_A_VAL_REG 0x001d0005
+#elif (VCCK_A_VAL == 739)
+#define VCCK_A_VAL_REG 0x001e0004
+#elif (VCCK_A_VAL == 729)
+#define VCCK_A_VAL_REG 0x001f0003
+#elif (VCCK_A_VAL == 719)
+#define VCCK_A_VAL_REG 0x00200002
+#elif (VCCK_A_VAL == 709)
+#define VCCK_A_VAL_REG 0x00210001
+#elif (VCCK_A_VAL == 699)
+#define VCCK_A_VAL_REG 0x00220000
+#else
+#error "VCCK_A val out of range\n"
+#endif
+
+/* VCCK_B PWM table */
+#if (VCCK_B_VAL == 1039)
+#define VCCK_B_VAL_REG 0x00000022
+#elif (VCCK_B_VAL == 1029)
+#define VCCK_B_VAL_REG 0x00010021
+#elif (VCCK_B_VAL == 1019)
+#define VCCK_B_VAL_REG 0x00020020
+#elif (VCCK_B_VAL == 1009)
+#define VCCK_B_VAL_REG 0x0003001f
+#elif (VCCK_B_VAL == 999)
+#define VCCK_B_VAL_REG 0x0004001e
+#elif (VCCK_B_VAL == 989)
+#define VCCK_B_VAL_REG 0x0005001d
+#elif (VCCK_B_VAL == 979)
+#define VCCK_B_VAL_REG 0x0006001c
+#elif (VCCK_B_VAL == 969)
+#define VCCK_B_VAL_REG 0x0007001b
+#elif (VCCK_B_VAL == 959)
+#define VCCK_B_VAL_REG 0x0008001a
+#elif (VCCK_B_VAL == 949)
+#define VCCK_B_VAL_REG 0x00090019
+#elif (VCCK_B_VAL == 939)
+#define VCCK_B_VAL_REG 0x000a0018
+#elif (VCCK_B_VAL == 929)
+#define VCCK_B_VAL_REG 0x000b0017
+#elif (VCCK_B_VAL == 919)
+#define VCCK_B_VAL_REG 0x000c0016
+#elif (VCCK_B_VAL == 909)
+#define VCCK_B_VAL_REG 0x000d0015
+#elif (VCCK_B_VAL == 899)
+#define VCCK_B_VAL_REG 0x000e0014
+#elif (VCCK_B_VAL == 889)
+#define VCCK_B_VAL_REG 0x000f0013
+#elif (VCCK_B_VAL == 879)
+#define VCCK_B_VAL_REG 0x00100012
+#elif (VCCK_B_VAL == 869)
+#define VCCK_B_VAL_REG 0x00110011
+#elif (VCCK_B_VAL == 859)
+#define VCCK_B_VAL_REG 0x00120010
+#elif (VCCK_B_VAL == 849)
+#define VCCK_B_VAL_REG 0x0013000f
+#elif (VCCK_B_VAL == 839)
+#define VCCK_B_VAL_REG 0x0014000e
+#elif (VCCK_B_VAL == 829)
+#define VCCK_B_VAL_REG 0x0015000d
+#elif (VCCK_B_VAL == 819)
+#define VCCK_B_VAL_REG 0x0016000c
+#elif (VCCK_B_VAL == 809)
+#define VCCK_B_VAL_REG 0x0017000b
+#elif (VCCK_B_VAL == 799)
+#define VCCK_B_VAL_REG 0x0018000a
+#elif (VCCK_B_VAL == 789)
+#define VCCK_B_VAL_REG 0x00190009
+#elif (VCCK_B_VAL == 779)
+#define VCCK_B_VAL_REG 0x001a0008
+#elif (VCCK_B_VAL == 769)
+#define VCCK_B_VAL_REG 0x001b0007
+#elif (VCCK_B_VAL == 759)
+#define VCCK_B_VAL_REG 0x001c0006
+#elif (VCCK_B_VAL == 749)
+#define VCCK_B_VAL_REG 0x001d0005
+#elif (VCCK_B_VAL == 739)
+#define VCCK_B_VAL_REG 0x001e0004
+#elif (VCCK_B_VAL == 729)
+#define VCCK_B_VAL_REG 0x001f0003
+#elif (VCCK_B_VAL == 719)
+#define VCCK_B_VAL_REG 0x00200002
+#elif (VCCK_B_VAL == 709)
+#define VCCK_B_VAL_REG 0x00210001
+#elif (VCCK_B_VAL == 699)
+#define VCCK_B_VAL_REG 0x00220000
+#else
+#error "VCCK_B val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 711)
+#define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 721)
+#define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 731)
+#define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 741)
+#define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 751)
+#define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 761)
+#define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 771)
+#define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 781)
+#define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 791)
+#define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 801)
+#define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 811)
+#define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 821)
+#define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 831)
+#define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 841)
+#define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 851)
+#define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 861)
+#define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 871)
+#define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 881)
+#define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 891)
+#define VDDEE_VAL_REG 0x12
+#else
+#error "VDDEE val out of range\n"
+#endif
+
+/* VDD_GPU PWM table */
+#if (VDD_GPU_VAL == 711)
+#define VDD_GPU_VAL_REG 0x120000
+#elif (VDD_GPU_VAL == 721)
+#define VDD_GPU_VAL_REG 0x110001
+#elif (VDD_GPU_VAL == 731)
+#define VDD_GPU_VAL_REG 0x100002
+#elif (VDD_GPU_VAL == 741)
+#define VDD_GPU_VAL_REG 0xf0003
+#elif (VDD_GPU_VAL == 751)
+#define VDD_GPU_VAL_REG 0xe0004
+#elif (VDD_GPU_VAL == 761)
+#define VDD_GPU_VAL_REG 0xd0005
+#elif (VDD_GPU_VAL == 771)
+#define VDD_GPU_VAL_REG 0xc0006
+#elif (VDD_GPU_VAL == 781)
+#define VDD_GPU_VAL_REG 0xb0007
+#elif (VDD_GPU_VAL == 791)
+#define VDD_GPU_VAL_REG 0xa0008
+#elif (VDD_GPU_VAL == 801)
+#define VDD_GPU_VAL_REG 0x90009
+#elif (VDD_GPU_VAL == 811)
+#define VDD_GPU_VAL_REG 0x8000a
+#elif (VDD_GPU_VAL == 821)
+#define VDD_GPU_VAL_REG 0x7000b
+#elif (VDD_GPU_VAL == 831)
+#define VDD_GPU_VAL_REG 0x6000c
+#elif (VDD_GPU_VAL == 841)
+#define VDD_GPU_VAL_REG 0x5000d
+#elif (VDD_GPU_VAL == 851)
+#define VDD_GPU_VAL_REG 0x4000e
+#elif (VDD_GPU_VAL == 861)
+#define VDD_GPU_VAL_REG 0x3000f
+#elif (VDD_GPU_VAL == 871)
+#define VDD_GPU_VAL_REG 0x20010
+#elif (VDD_GPU_VAL == 881)
+#define VDD_GPU_VAL_REG 0x10011
+#elif (VDD_GPU_VAL == 891)
+#define VDD_GPU_VAL_REG 0x12
+#else
+#error "VDD_GPU val out of range\n"
+#endif
+
+/* VDD_NPU PWM table */
+#if (VDD_NPU_VAL == 711)
+#define VDD_NPU_VAL_REG 0x120000
+#elif (VDD_NPU_VAL == 721)
+#define VDD_NPU_VAL_REG 0x110001
+#elif (VDD_NPU_VAL == 731)
+#define VDD_NPU_VAL_REG 0x100002
+#elif (VDD_NPU_VAL == 741)
+#define VDD_NPU_VAL_REG 0xf0003
+#elif (VDD_NPU_VAL == 751)
+#define VDD_NPU_VAL_REG 0xe0004
+#elif (VDD_NPU_VAL == 761)
+#define VDD_NPU_VAL_REG 0xd0005
+#elif (VDD_NPU_VAL == 771)
+#define VDD_NPU_VAL_REG 0xc0006
+#elif (VDD_NPU_VAL == 781)
+#define VDD_NPU_VAL_REG 0xb0007
+#elif (VDD_NPU_VAL == 791)
+#define VDD_NPU_VAL_REG 0xa0008
+#elif (VDD_NPU_VAL == 801)
+#define VDD_NPU_VAL_REG 0x90009
+#elif (VDD_NPU_VAL == 811)
+#define VDD_NPU_VAL_REG 0x8000a
+#elif (VDD_NPU_VAL == 821)
+#define VDD_NPU_VAL_REG 0x7000b
+#elif (VDD_NPU_VAL == 831)
+#define VDD_NPU_VAL_REG 0x6000c
+#elif (VDD_NPU_VAL == 841)
+#define VDD_NPU_VAL_REG 0x5000d
+#elif (VDD_NPU_VAL == 851)
+#define VDD_NPU_VAL_REG 0x4000e
+#elif (VDD_NPU_VAL == 861)
+#define VDD_NPU_VAL_REG 0x3000f
+#elif (VDD_NPU_VAL == 871)
+#define VDD_NPU_VAL_REG 0x20010
+#elif (VDD_NPU_VAL == 881)
+#define VDD_NPU_VAL_REG 0x10011
+#elif (VDD_NPU_VAL == 891)
+#define VDD_NPU_VAL_REG 0x12
+#else
+#error "VDD_NPU val out of range\n"
+#endif
+
+/* VDD_DDR PWM table */
+#if (VDD_DDR_VAL == 711)
+#define VDD_DDR_VAL_REG 0x120000
+#elif (VDD_DDR_VAL == 721)
+#define VDD_DDR_VAL_REG 0x110001
+#elif (VDD_DDR_VAL == 731)
+#define VDD_DDR_VAL_REG 0x100002
+#elif (VDD_DDR_VAL == 741)
+#define VDD_DDR_VAL_REG 0xf0003
+#elif (VDD_DDR_VAL == 751)
+#define VDD_DDR_VAL_REG 0xe0004
+#elif (VDD_DDR_VAL == 761)
+#define VDD_DDR_VAL_REG 0xd0005
+#elif (VDD_DDR_VAL == 771)
+#define VDD_DDR_VAL_REG 0xc0006
+#elif (VDD_DDR_VAL == 781)
+#define VDD_DDR_VAL_REG 0xb0007
+#elif (VDD_DDR_VAL == 791)
+#define VDD_DDR_VAL_REG 0xa0008
+#elif (VDD_DDR_VAL == 801)
+#define VDD_DDR_VAL_REG 0x90009
+#elif (VDD_DDR_VAL == 811)
+#define VDD_DDR_VAL_REG 0x8000a
+#elif (VDD_DDR_VAL == 821)
+#define VDD_DDR_VAL_REG 0x7000b
+#elif (VDD_DDR_VAL == 831)
+#define VDD_DDR_VAL_REG 0x6000c
+#elif (VDD_DDR_VAL == 841)
+#define VDD_DDR_VAL_REG 0x5000d
+#elif (VDD_DDR_VAL == 851)
+#define VDD_DDR_VAL_REG 0x4000e
+#elif (VDD_DDR_VAL == 861)
+#define VDD_DDR_VAL_REG 0x3000f
+#elif (VDD_DDR_VAL == 871)
+#define VDD_DDR_VAL_REG 0x20010
+#elif (VDD_DDR_VAL == 881)
+#define VDD_DDR_VAL_REG 0x10011
+#elif (VDD_DDR_VAL == 891)
+#define VDD_DDR_VAL_REG 0x12
+#else
+#error "VDD_DDR val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ { 0, 0, 0xffffffff, 0, 0, 0 },
+};
+
+/* for PWM use */
+/*
+ * GPIOE_0 PWMAO_A VDDEE
+ * GPIOE_1 PWMAO_B VCCK_B
+ * GPIOE_3 PWMAO_D VCCK_A
+ * GPIOE_4 PWMAO_E VDDGPU
+ * GPIOE_5 PWMAO_F VDDNPU
+ * GPIOE_6 PWMAO_G VDDDDR
+ */
+/* gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+ /* demo, user defined override register */
+ /* config vddee pwm - pwmao_a */
+ { PWM_AO_AB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_AB_MISC_REG_AB, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_AB_CTRL, (0x1 << 8), (0x7FF << 0), 0, 0, 0 },
+ /* config vcck a pwm - pwmao_d */
+ { PWM_AO_CD_PWM_B, VCCK_A_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_CD_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_CD_CTRL, (0x1 << 24), (0x7FF << 16), 0, 0, 0 },
+ /* config vcck b pwm - pwmao_b */
+ { PWM_AO_AB_PWM_B, VCCK_B_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_AB_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_AB_CTRL, (0x1 << 24), (0x7FF << 16), 0, 0, 0 },
+ /* config vddgpu pwm - pwmao_e */
+ { PWM_AO_EF_PWM_A, VDD_GPU_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_EF_MISC_REG_AB, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_EF_CTRL, (0x1 << 8), (0x7FF << 0), 0, 0, 0 },
+ /* config vddnpu pwm - pwmao_f */
+ { PWM_AO_EF_PWM_B, VDD_NPU_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_EF_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_EF_CTRL, (0x1 << 24), (0x7FF << 16), 0, 0, 0 },
+ /* config vddddr pwm - pwmao_g */
+ { PWM_AO_GH_PWM_A, VDD_DDR_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_GH_MISC_REG_AB, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_GH_CTRL, (0x1 << 8), (0x7FF << 0), 0, 0, 0 },
+
+ /* enable vddee */
+ /* set gpioe_0 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 0), (0x3 << 0), 0, 0, 0 },
+ /* mux gpioe_0 to pwmao_a */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 0), (0xf << 0), 0, 0, 0 },
+
+ /* enable vddgpu */
+ /* set gpioe_4 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 8), (0x3 << 8), 0, 0, 0 },
+ /* mux gpioe_4 to pwmao_e */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 16), (0xf << 16), 0, 0, 0 },
+ /* set TEST_N to high(defualt high) */
+ //{PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0},
+ //{PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0},
+
+ /* enable vddnpu */
+ /* set gpioe_5 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 10), (0x3 << 10), 0, 0, 0 },
+ /* mux gpioe_5 to pwmao_F */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 20), (0xf << 20), 0, 0, 0 },
+
+ /* enable vcck b */
+ /* set gpioe_1 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 2), (0x3 << 2), 0, 0, 0 },
+ /* mux gpioe_1 to pwmao_b */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 4), (0xf << 4), 0, 0, 0 },
+
+ /* enable vcck a */
+ /* set gpioe_3 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 6), (0x3 << 6), 0, 0, 0 },
+ /* mux gpioe_3 to pwmao_d */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 12), (0xf << 12), 0, 0, 0 },
+ /* set gpiod_2 to high(defualt high) */
+ //{PADCTRL_GPIOD_O, (0x1 << 2), (0x1 << 2), 0, 0, 0},
+ //{PADCTRL_GPIOD_OEN, (0x0 << 2), (0x1 << 2), 0, 0, 0},
+ //{PADCTRL_PIN_MUX_REGA, (0x0 << 8), (0xf << 8), 0, 0, 0},
+
+ /* enable vddddr */
+ /* set gpioe_6 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 12), (0x3 << 12), 0, 0, 0 },
+ /* mux gpioe_6 to pwmao_g */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 24), (0xf << 24), 0, 0, 0 },
+};
+
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common ={
+ .version = 0x01,
+ .device_fip_container_size = 0x280000,
+ .device_fip_container_copies = 4,
+ },
+ .nand ={
+ .version = 0x01,
+ .bbt_pages = 0x1,
+ .bbt_start_block = 0x20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (4 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 128,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/t7_an400_lpddr4x/fw_arb.cfg b/board/amlogic/t7_an400_lpddr4x/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/t7_an400_lpddr4x/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/t7_an400_lpddr4x/lcd.c b/board/amlogic/t7_an400_lpddr4x/lcd.c
new file mode 100644
index 0000000..eac94dd
--- /dev/null
+++ b/board/amlogic/t7_an400_lpddr4x/lcd.c
@@ -0,0 +1,563 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+
+/***************************************************
+ * lcd_0
+ ***************************************************/
+static char lcd0_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOY_0", /* 12V */
+ "GPIOY_4", /* rst */
+ "invalid", /* ending flag */
+};
+
+static char lcd0_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOY_12", /* enable */
+ "GPIOY_1", /* pwm_e */
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0, 1, 50,}, /* panel vcc */
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_CPU, 0, 0, 200,}, /* panel vcc */
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_on_step_mipi[] = {
+ {LCD_POWER_TYPE_CPU, 1, 0, 0,}, /* rst */
+ {LCD_POWER_TYPE_CPU, 0, 0, 500,}, /* panel vcc */
+ {LCD_POWER_TYPE_CPU, 0, 1, 100,}, /* panel vcc */
+ {LCD_POWER_TYPE_CPU, 1, 1, 20,}, /* rst */
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_off_step_mipi[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_CPU, 1, 0, 0,}, /* rst */
+ {LCD_POWER_TYPE_CPU, 0, 0, 200,}, /* panel vcc */
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static unsigned char mipi_init_on_table_dft[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xfd, 1, 100,
+ 0x05, 1, 0x29,
+ 0xfd, 1, 20,
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table_dft[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xfd, 1, 100,
+ 0x05, 1, 0x10,
+ 0xfd, 1, 10,
+ 0xff, 0, //ending
+};
+
+struct ext_lcd_config_s ext_lcd0_config[LCD_NUM_MAX] = {
+ {/* normal*/
+ "lvds_0", LCD_LVDS, 8,
+ /* basic timing */
+ 1366, 768, 1569, 806, 56, 64, 0, 3, 28, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 0, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 2-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 2, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 1-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_1", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 1, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {"edp_0", LCD_EDP, 8,
+ /* basic timing */
+ 1920, 1080, 2200, 1120, 44, 148, 0, 5, 30, 0,
+ /* clk_attr */
+ 1, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* edp_attr */
+ 2, 1, 0, 0, 0, 0, 0, 0, 0x5, 0x1,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/* TL070WSH27*/
+ "mipi_0",LCD_MIPI,8,
+ /* basic timing */
+ 1024, 600, 1250, 630, 80, 100, 0, 5, 20, 0,
+ /* clk_attr */
+ 0, 0, 1, 47250000, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* mipi_attr */
+ 4, 300, 0, 1, 0, 2, 1, 0, Rsv_val, Rsv_val,
+ /* cmd init */
+ mipi_init_on_table_dft, mipi_init_off_table_dft,
+ /* power step */
+ lcd0_power_on_step_mipi, lcd0_power_off_step_mipi,
+ /* backlight */
+ 100, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_NEGATIVE, BL_PWM_E, 180, 100, 25, 1, 1,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd0_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_vbyone_pin", //GPIOY_10/12
+ .pinmux_set = {{0x14, 0x00030300}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x000f0f00}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "lcd_edp_pin", //GPIOY_10
+ .pinmux_set = {{0x14, 0x00000400}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x00000f00}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s lcd0_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", /*GPIOY_1*/
+ .pinmux_set = {{0x13, 0x00000030}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x13, 0x000000f0}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xc0, 2, 0x01, 0x2b,
+ 0xc0, 2, 0x02, 0x05,
+ 0xc0, 2, 0x03, 0x00,
+ 0xc0, 2, 0x04, 0x00,
+ 0xc0, 2, 0x05, 0x0c,
+ 0xc0, 2, 0x06, 0x04,
+ 0xc0, 2, 0x07, 0x21,
+ 0xc0, 2, 0x08, 0x0f,
+ 0xc0, 2, 0x09, 0x04,
+ 0xc0, 2, 0x0a, 0x00,
+ 0xc0, 2, 0x0b, 0x04,
+ 0xc0, 2, 0xff, 0x00,
+ 0xfd, 1, 100, /* delay 100ms */
+ 0xff, 0, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0} },
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0} },
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "invalid",
+ /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .type = LCD_EXTERN_MAX,
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x20, /* 7bit i2c address */
+ .i2c_addr2 = 0x74, /* 7bit i2c address, 0xff for none */
+ /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_1,
+ .cmd_size = 0xff,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+/***************************************************
+ * lcd_1
+ ***************************************************/
+static char lcd1_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOY_14", /* 12V */
+ "GPIOY_6", /* rst */
+ "invalid", /* ending flag */
+};
+
+static char lcd1_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOY_13", /* enable */
+ "GPIOY_8", /* pwm_f */
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0, 1, 50,}, /* panel vcc */
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_CPU, 0, 0, 200,}, /* panel vcc */
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_on_step_mipi[] = {
+ {LCD_POWER_TYPE_CPU, 1, 0, 0,}, /* rst */
+ {LCD_POWER_TYPE_CPU, 0, 0, 500,}, /* panel vcc */
+ {LCD_POWER_TYPE_CPU, 0, 1, 100,}, /* panel vcc */
+ {LCD_POWER_TYPE_CPU, 1, 1, 20,}, /* rst */
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_off_step_mipi[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_CPU, 1, 0, 0,}, /* rst */
+ {LCD_POWER_TYPE_CPU, 0, 0, 200,}, /* panel vcc */
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd1_config[LCD_NUM_MAX] = {
+ {/* normal*/
+ "lvds_0", LCD_LVDS, 8,
+ /* basic timing */
+ 1366, 768, 1569, 806, 56, 64, 0, 3, 28, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 0, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 2-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 2, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_F, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 1-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_1", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 1, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_F, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {"edp_0", LCD_EDP, 8,
+ /* basic timing */
+ 1920, 1080, 2200, 1120, 44, 148, 0, 5, 30, 0,
+ /* clk_attr */
+ 1, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* edp_attr */
+ 2, 1, 0, 0, 0, 0, 0, 0, 0x5, 0x1,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_F, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/* TL070WSH27*/
+ "mipi_0",LCD_MIPI,8,
+ /* basic timing */
+ 1024, 600, 1250, 630, 80, 100, 0, 5, 20, 0,
+ /* clk_attr */
+ 0, 0, 1, 47250000, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* mipi_attr */
+ 4, 300, 0, 1, 0, 2, 1, 0, Rsv_val, Rsv_val,
+ /* cmd init */
+ mipi_init_on_table_dft, mipi_init_off_table_dft,
+ /* power step */
+ lcd1_power_on_step_mipi, lcd1_power_off_step_mipi,
+ /* backlight */
+ 100, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_NEGATIVE, BL_PWM_F, 180, 100, 25, 1, 1,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd1_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_vbyone_pin", //GPIOY_11/13
+ .pinmux_set = {{0x14, 0x00303000}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x00f0f000}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "lcd_edp_pin", //GPIOY_11
+ .pinmux_set = {{0x14, 0x00004000}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x0000f000}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s lcd1_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", /*GPIOY_8*/
+ .pinmux_set = {{0x14, 0x00000003}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x0000000f}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+/***************************************************
+ * lcd_2
+ ***************************************************/
+static char lcd2_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOY_14",
+ "invalid", /* ending flag */
+};
+
+static char lcd2_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd2_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0, 1, 20,}, /* panel vcc */
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd2_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_CPU, 0, 0, 200,}, /* panel vcc */
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd2_config[LCD_NUM_MAX] = { //only support lvds
+ {/* normal*/
+ "lvds_0", LCD_LVDS, 8,
+ /* basic timing */
+ 1366, 768, 1569, 806, 56, 64, 0, 3, 28, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 0, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd2_power_on_step, lcd2_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/* for HDMI convert*/
+ "lvds_1", LCD_LVDS, 8,
+ /* basic timing */
+ 1920, 1080, 2200, 1125, 44, 148, 0, 5, 36, 0,
+ /* clk_attr */
+ 4, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 1, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd2_power_on_step, lcd2_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_MAX, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd2_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s lcd2_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "invalid",
+ },
+};
+
+/***************************************************
+ * lcd default config
+ ***************************************************/
+static struct lcd_dft_config_s lcd_dft_conf[] = {
+ {//index 0
+ .lcd_gpio = lcd0_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd0_config,
+ .lcd_pinmux = lcd0_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd0_bl_gpio,
+ .bl_pinmux = lcd0_bl_pinmux_ctrl,
+ },
+ {//index 1
+ .lcd_gpio = lcd1_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd1_config,
+ .lcd_pinmux = lcd1_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd1_bl_gpio,
+ .bl_pinmux = lcd1_bl_pinmux_ctrl,
+ },
+ {//index 2
+ .lcd_gpio = lcd2_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd2_config,
+ .lcd_pinmux = lcd2_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd2_bl_gpio,
+ .bl_pinmux = lcd2_bl_pinmux_ctrl,
+ }
+};
+
+void lcd_config_bsp_init(void)
+{
+ struct aml_lcd_data_s *pdata = aml_lcd_get_data();
+
+ if (pdata) {
+ pdata->dft_conf[0] = &lcd_dft_conf[0];
+ pdata->dft_conf[1] = &lcd_dft_conf[1];
+ pdata->dft_conf[2] = &lcd_dft_conf[2];
+ }
+}
diff --git a/board/amlogic/t7_an400_lpddr4x/t7_an400_lpddr4x.c b/board/amlogic/t7_an400_lpddr4x/t7_an400_lpddr4x.c
new file mode 100644
index 0000000..55fbdca
--- /dev/null
+++ b/board/amlogic/t7_an400_lpddr4x/t7_an400_lpddr4x.c
@@ -0,0 +1,403 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_VOUT
+#include <amlogic/media/vout/aml_vout.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/media/vout/lcd/lcd_vout.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+ aml_set_bootsequence(0);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+#if 0 //bypass below operations for pxp
+ active_clk();
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+#endif
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ /*set vcc5V*/
+ run_command("gpio set GPIOH_1", 0);
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+ run_command("run bcb_cmd", 0);
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+#ifdef CONFIG_AML_VOUT
+ vout_probe();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0xe0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x100000000UL,
+ .phys = 0x100000000UL,
+ .size = 0x120000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xe0000000UL,
+ .phys = 0xe0000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ //printf("\nmach_cpu_init\n");
+#ifdef CONFIG_UPDATE_MMU_TABLE
+ unsigned long nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4;
+ if ( nddrSize <= 0xe0000000 )
+ {
+ bd_mem_map[0].size = nddrSize;
+ bd_mem_map[1].virt = 0;
+ bd_mem_map[1].phys = 0;
+ bd_mem_map[1].size = 0;
+ }
+#endif
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+#endif
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ strcpy(name, "t7_a311d2_an400\0");
+ env_set("aml_dt", "t7_a311d2_an400\0");
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/t7_an400p_lpddr4x/Kconfig b/board/amlogic/t7_an400p_lpddr4x/Kconfig
new file mode 100644
index 0000000..8351f9b
--- /dev/null
+++ b/board/amlogic/t7_an400p_lpddr4x/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_T7_AN400P_LPDDR4X
+
+config SYS_SOC
+ default "t7"
+
+config SYS_BOARD
+ default "t7_an400p_lpddr4x"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "t7_an400p_lpddr4x"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+endif
diff --git a/board/amlogic/t7_an400p_lpddr4x/Makefile b/board/amlogic/t7_an400p_lpddr4x/Makefile
new file mode 100644
index 0000000..1e920e7
--- /dev/null
+++ b/board/amlogic/t7_an400p_lpddr4x/Makefile
@@ -0,0 +1,3 @@
+obj-y += $(BOARD).o
+obj-$(CONFIG_AML_LCD) += lcd.o
+
diff --git a/board/amlogic/t7_an400p_lpddr4x/firmware/timing.c b/board/amlogic/t7_an400p_lpddr4x/firmware/timing.c
new file mode 100644
index 0000000..d89cd68
--- /dev/null
+++ b/board/amlogic/t7_an400p_lpddr4x/firmware/timing.c
@@ -0,0 +1,950 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+#define ENABLE_LPDDR4X_MODE 1
+
+#define AN_408_DDR0_1G_DDR1_0G 0
+#define AN_408_DDR0_2G_DDR1_0G 1
+#define AN_408_DDR0_1G_DDR1_1G 2
+#define AN_408_DDR0_2G_DDR1_1G 3
+#define AN_408_DDR0_2G_DDR1_2G 4
+#define AN_408_DDR0_2G_DDR1_2G_RANK01 5
+#define AN_408_DDR0_4G_DDR1_4G_RANK01 6
+
+#define DDR_SIZE_TYPE_1 AN_408_DDR0_1G_DDR1_1G //AN_408_DDR0_2G_DDR1_0G//AN_408_DDR0_2G_DDR1_1G//AN_408_DDR0_1G_DDR1_1G
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+#if 0
+ {
+ /* tl1 skt (x309) ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq ={ 1200, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x31f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0x23, 0x13 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x0, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 48, //48, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay ={ 32 + 20, 32 + 20, 32 + 20, 32 + 20, 32, 32 + 0, 32 + 20, 32 + 20, 32 + 20, 32 + 20},
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25),
+ [1] = (12 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 13 << 5 | 14 << 10 | 6 << 15 | 0 << 20 | 0 << 25),
+ },
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 00, 00 },
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC_COPY_CHANNEL_CFG, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux =
+ {
+ 2,
+ 5,
+ 20,
+ 14,
+ 8,
+ 24,
+ 4,
+ 13,
+ 25,
+ 12,
+ 10,
+ 23,
+ 26,
+ 18,
+ 0,
+ 0,
+ 0,
+ 9,
+ 1,
+ 19,
+ 0,
+ 22,
+ 11,
+ 7,
+ 6,
+ 3,
+ 0,
+ 0,
+ },
+ .dfi_pinmux =
+ {
+ 18,
+ 15,
+ 16,
+ 12,
+ 5,
+ 20,
+ 10,
+ 7,
+ 0,
+ 11,
+ 14,
+ 8,
+ 23,
+ 17,
+ 3,
+ 13,
+ 22,
+ 2,
+ 21,
+ 19,
+ 6,
+ 4,
+ 1,
+ 0,
+ 0,
+ 0,
+ },
+ },
+#endif
+#if 1
+ {
+ //.fast_boot[0]=0x000000fd,// 253
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .enable_lpddr4x_mode = ENABLE_LPDDR4X_MODE,
+ .DRAMFreq ={ 2016, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xc8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_4G_DDR1_4G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x131f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0, 0 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x3, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 60,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 240,
+ .soc_clk_slew_rate = 0x1ff,
+ .soc_cs_slew_rate = 0x1ff,
+ .soc_ac_slew_rate = 0x1ff,
+ .soc_data_slew_rate = 0x5ff,
+ .vref_output_permil = 629, //300
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 300,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting=0,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay ={ 32 + 10, 32, 0, 0, 0, 32 + 10, 32, 0, 0, 0},
+ //.ac_trace_delay ={ 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32, 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32 + 0},
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25),
+ [1] = (11 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 12 << 5 | 13 << 10 | 14 << 15 | 0 << 20 | 0 << 25),
+ },
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 7, 1, 5, 0, 2, 3, 4, 6,
+ 8, 15, 12, 13, 9, 10, 11, 14,
+ 22, 18, 21, 20, 17, 23, 16, 19,
+ 29, 30, 28, 31, 24, 27, 26, 25 },
+
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, // DDR_FUNC,
+ //.ddr_func = 0, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux ={ 2, 3, 1, 0, 5, 4, 0, 0, 0, 0,
+ 1, 3, 5, 2, 4, 0, 0, 0, 0 },
+
+ .dfi_pinmux =
+ {
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 0,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 0,
+ 0,
+ 0,
+ },
+ },
+
+ {
+ //.fast_boot[0]=0x000000fd,// 253
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .enable_lpddr4x_mode = ENABLE_LPDDR4X_MODE,
+ .DRAMFreq ={ 2016, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xc8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_4G_DDR1_4G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x131f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0, 0 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x3, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 60,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 240,
+ .soc_clk_slew_rate = 0x1ff,
+ .soc_cs_slew_rate = 0x1ff,
+ .soc_ac_slew_rate = 0x1ff,
+ .soc_data_slew_rate = 0x5ff,
+ .vref_output_permil = 629,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 300,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting=0,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ //.ac_trace_delay ={ 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32, 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32 + 0},
+ .ac_trace_delay ={ 32 + 10, 32, 0, 0, 0, 32 + 10, 32, 0, 0, 0},
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25),
+ [1] = (11 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 12 << 5 | 13 << 10 | 14 << 15 | 0 << 20 | 0 << 25),
+ },
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 4, 6, 5, 0, 7, 1, 2, 3,
+ 15, 11, 13, 14, 12, 9, 8, 10,
+ 21, 19, 22, 16, 18, 17, 23, 20,
+ 29, 30, 26, 25, 24, 27, 31, 28 },
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, // DDR_FUNC,
+ //.ddr_func = 0, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux ={ 2, 3, 1, 0, 5, 4, 0, 0, 0, 0,
+ 1, 3, 5, 2, 4, 0, 0, 0, 0 },
+
+ .dfi_pinmux =
+ {
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 0,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 0,
+ 0,
+ 0,
+ },
+ },
+#endif
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .low_console_baud = CONFIG_LOW_CONSOLE_BAUD,
+};
+
+#define VCCK_A_VAL AML_VCCK_A_INIT_VOLTAGE
+#define VCCK_B_VAL AML_VCCK_B_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK_A uses DCDC PWM table */
+#if (VCCK_A_VAL == 1039)
+#define VCCK_A_VAL_REG 0x00000022
+#elif (VCCK_A_VAL == 1029)
+#define VCCK_A_VAL_REG 0x00010021
+#elif (VCCK_A_VAL == 1019)
+#define VCCK_A_VAL_REG 0x00020020
+#elif (VCCK_A_VAL == 1009)
+#define VCCK_A_VAL_REG 0x0003001f
+#elif (VCCK_A_VAL == 999)
+#define VCCK_A_VAL_REG 0x0004001e
+#elif (VCCK_A_VAL == 989)
+#define VCCK_A_VAL_REG 0x0005001d
+#elif (VCCK_A_VAL == 979)
+#define VCCK_A_VAL_REG 0x0006001c
+#elif (VCCK_A_VAL == 969)
+#define VCCK_A_VAL_REG 0x0007001b
+#elif (VCCK_A_VAL == 959)
+#define VCCK_A_VAL_REG 0x0008001a
+#elif (VCCK_A_VAL == 949)
+#define VCCK_A_VAL_REG 0x00090019
+#elif (VCCK_A_VAL == 939)
+#define VCCK_A_VAL_REG 0x000a0018
+#elif (VCCK_A_VAL == 929)
+#define VCCK_A_VAL_REG 0x000b0017
+#elif (VCCK_A_VAL == 919)
+#define VCCK_A_VAL_REG 0x000c0016
+#elif (VCCK_A_VAL == 909)
+#define VCCK_A_VAL_REG 0x000d0015
+#elif (VCCK_A_VAL == 899)
+#define VCCK_A_VAL_REG 0x000e0014
+#elif (VCCK_A_VAL == 889)
+#define VCCK_A_VAL_REG 0x000f0013
+#elif (VCCK_A_VAL == 879)
+#define VCCK_A_VAL_REG 0x00100012
+#elif (VCCK_A_VAL == 869)
+#define VCCK_A_VAL_REG 0x00110011
+#elif (VCCK_A_VAL == 859)
+#define VCCK_A_VAL_REG 0x00120010
+#elif (VCCK_A_VAL == 849)
+#define VCCK_A_VAL_REG 0x0013000f
+#elif (VCCK_A_VAL == 839)
+#define VCCK_A_VAL_REG 0x0014000e
+#elif (VCCK_A_VAL == 829)
+#define VCCK_A_VAL_REG 0x0015000d
+#elif (VCCK_A_VAL == 819)
+#define VCCK_A_VAL_REG 0x0016000c
+#elif (VCCK_A_VAL == 809)
+#define VCCK_A_VAL_REG 0x0017000b
+#elif (VCCK_A_VAL == 799)
+#define VCCK_A_VAL_REG 0x0018000a
+#elif (VCCK_A_VAL == 789)
+#define VCCK_A_VAL_REG 0x00190009
+#elif (VCCK_A_VAL == 779)
+#define VCCK_A_VAL_REG 0x001a0008
+#elif (VCCK_A_VAL == 769)
+#define VCCK_A_VAL_REG 0x001b0007
+#elif (VCCK_A_VAL == 759)
+#define VCCK_A_VAL_REG 0x001c0006
+#elif (VCCK_A_VAL == 749)
+#define VCCK_A_VAL_REG 0x001d0005
+#elif (VCCK_A_VAL == 739)
+#define VCCK_A_VAL_REG 0x001e0004
+#elif (VCCK_A_VAL == 729)
+#define VCCK_A_VAL_REG 0x001f0003
+#elif (VCCK_A_VAL == 719)
+#define VCCK_A_VAL_REG 0x00200002
+#elif (VCCK_A_VAL == 709)
+#define VCCK_A_VAL_REG 0x00210001
+#elif (VCCK_A_VAL == 699)
+#define VCCK_A_VAL_REG 0x00220000
+#else
+#error "VCCK_A val out of range\n"
+#endif
+
+/* VCCK_B uses PMIC table */
+#if (VCCK_B_VAL == 1040)
+#define VCCK_B_VAL_REG 0x22
+#elif (VCCK_B_VAL == 1030)
+#define VCCK_B_VAL_REG 0x21
+#elif (VCCK_B_VAL == 1020)
+#define VCCK_B_VAL_REG 0x20
+#elif (VCCK_B_VAL == 1010)
+#define VCCK_B_VAL_REG 0x1f
+#elif (VCCK_B_VAL == 1000)
+#define VCCK_B_VAL_REG 0x1e
+#elif (VCCK_B_VAL == 990)
+#define VCCK_B_VAL_REG 0x1d
+#elif (VCCK_B_VAL == 980)
+#define VCCK_B_VAL_REG 0x1c
+#elif (VCCK_B_VAL == 970)
+#define VCCK_B_VAL_REG 0x1b
+#elif (VCCK_B_VAL == 960)
+#define VCCK_B_VAL_REG 0x1a
+#elif (VCCK_B_VAL == 950)
+#define VCCK_B_VAL_REG 0x19
+#elif (VCCK_B_VAL == 940)
+#define VCCK_B_VAL_REG 0x18
+#elif (VCCK_B_VAL == 930)
+#define VCCK_B_VAL_REG 0x17
+#elif (VCCK_B_VAL == 920)
+#define VCCK_B_VAL_REG 0x16
+#elif (VCCK_B_VAL == 910)
+#define VCCK_B_VAL_REG 0x15
+#elif (VCCK_B_VAL == 900)
+#define VCCK_B_VAL_REG 0x14
+#elif (VCCK_B_VAL == 890)
+#define VCCK_B_VAL_REG 0x13
+#elif (VCCK_B_VAL == 880)
+#define VCCK_B_VAL_REG 0x12
+#elif (VCCK_B_VAL == 870)
+#define VCCK_B_VAL_REG 0x11
+#elif (VCCK_B_VAL == 860)
+#define VCCK_B_VAL_REG 0x10
+#elif (VCCK_B_VAL == 850)
+#define VCCK_B_VAL_REG 0xf
+#elif (VCCK_B_VAL == 840)
+#define VCCK_B_VAL_REG 0xe
+#elif (VCCK_B_VAL == 830)
+#define VCCK_B_VAL_REG 0xd
+#elif (VCCK_B_VAL == 820)
+#define VCCK_B_VAL_REG 0xc
+#elif (VCCK_B_VAL == 810)
+#define VCCK_B_VAL_REG 0xb
+#elif (VCCK_B_VAL == 800)
+#define VCCK_B_VAL_REG 0xa
+#elif (VCCK_B_VAL == 790)
+#define VCCK_B_VAL_REG 0x9
+#elif (VCCK_B_VAL == 780)
+#define VCCK_B_VAL_REG 0x8
+#elif (VCCK_B_VAL == 770)
+#define VCCK_B_VAL_REG 0x7
+#elif (VCCK_B_VAL == 760)
+#define VCCK_B_VAL_REG 0x6
+#elif (VCCK_B_VAL == 750)
+#define VCCK_B_VAL_REG 0x5
+#elif (VCCK_B_VAL == 740)
+#define VCCK_B_VAL_REG 0x4
+#elif (VCCK_B_VAL == 730)
+#define VCCK_B_VAL_REG 0x3
+#elif (VCCK_B_VAL == 720)
+#define VCCK_B_VAL_REG 0x2
+#elif (VCCK_B_VAL == 710)
+#define VCCK_B_VAL_REG 0x1
+#elif (VCCK_B_VAL == 700)
+#define VCCK_B_VAL_REG 0x0
+#else
+#error "\nVCCK_B val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 1040)
+#define VDDEE_VAL_REG 0x22
+#elif (VDDEE_VAL == 1030)
+#define VDDEE_VAL_REG 0x21
+#elif (VDDEE_VAL == 1020)
+#define VDDEE_VAL_REG 0x20
+#elif (VDDEE_VAL == 1010)
+#define VDDEE_VAL_REG 0x1f
+#elif (VDDEE_VAL == 1000)
+#define VDDEE_VAL_REG 0x1e
+#elif (VDDEE_VAL == 990)
+#define VDDEE_VAL_REG 0x1d
+#elif (VDDEE_VAL == 980)
+#define VDDEE_VAL_REG 0x1c
+#elif (VDDEE_VAL == 970)
+#define VDDEE_VAL_REG 0x1b
+#elif (VDDEE_VAL == 960)
+#define VDDEE_VAL_REG 0x1a
+#elif (VDDEE_VAL == 950)
+#define VDDEE_VAL_REG 0x19
+#elif (VDDEE_VAL == 940)
+#define VDDEE_VAL_REG 0x18
+#elif (VDDEE_VAL == 930)
+#define VDDEE_VAL_REG 0x17
+#elif (VDDEE_VAL == 920)
+#define VDDEE_VAL_REG 0x16
+#elif (VDDEE_VAL == 910)
+#define VDDEE_VAL_REG 0x15
+#elif (VDDEE_VAL == 900)
+#define VDDEE_VAL_REG 0x14
+#elif (VDDEE_VAL == 890)
+#define VDDEE_VAL_REG 0x13
+#elif (VDDEE_VAL == 880)
+#define VDDEE_VAL_REG 0x12
+#elif (VDDEE_VAL == 870)
+#define VDDEE_VAL_REG 0x11
+#elif (VDDEE_VAL == 860)
+#define VDDEE_VAL_REG 0x10
+#elif (VDDEE_VAL == 850)
+#define VDDEE_VAL_REG 0xf
+#elif (VDDEE_VAL == 840)
+#define VDDEE_VAL_REG 0xe
+#elif (VDDEE_VAL == 830)
+#define VDDEE_VAL_REG 0xd
+#elif (VDDEE_VAL == 820)
+#define VDDEE_VAL_REG 0xc
+#elif (VDDEE_VAL == 810)
+#define VDDEE_VAL_REG 0xb
+#elif (VDDEE_VAL == 800)
+#define VDDEE_VAL_REG 0xa
+#elif (VDDEE_VAL == 790)
+#define VDDEE_VAL_REG 0x9
+#elif (VDDEE_VAL == 780)
+#define VDDEE_VAL_REG 0x8
+#elif (VDDEE_VAL == 770)
+#define VDDEE_VAL_REG 0x7
+#elif (VDDEE_VAL == 760)
+#define VDDEE_VAL_REG 0x6
+#elif (VDDEE_VAL == 750)
+#define VDDEE_VAL_REG 0x5
+#elif (VDDEE_VAL == 740)
+#define VDDEE_VAL_REG 0x4
+#elif (VDDEE_VAL == 730)
+#define VDDEE_VAL_REG 0x3
+#elif (VDDEE_VAL == 720)
+#define VDDEE_VAL_REG 0x2
+#elif (VDDEE_VAL == 710)
+#define VDDEE_VAL_REG 0x1
+#elif (VDDEE_VAL == 700)
+#define VDDEE_VAL_REG 0x0
+#else
+#error "\nVDDEE val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ { 0, 0, 0xffffffff, 0, 0, 0 },
+};
+
+#define I2C_BUS 0x2
+#define I2C_AO_A 6 /*from bl2 i2c meson_i2c.h*/
+#define I2C_DEV_ADDR 0x4b
+#define BD71837_REG_BUCK2_CTRL 0x06
+#define BD71837_REG_BUCK3_CTRL 0x07
+#define BD71837_REG_BUCK2_VOLT_RUN 0x10
+#define BD71837_REG_BUCK3_VOLT_RUN 0x12
+#define BD71837_REG_REGLOCK 0x2f
+#define BD71837_REG_MUXSW_EN 0x30
+
+/* pmu/gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+ /* set TEST_N to high */
+ { PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
+ { PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0 },
+
+ /* config vcck a pwm - pwmao_d */
+ { PWM_AO_CD_PWM_B, VCCK_A_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_CD_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_CD_CTRL, (0x1 << 24), (0x7FF << 16), 0, 0, 0 },
+
+ /* enable pwmao_d, Wait for pmic to enable VCCK A */
+ /* set gpioe_3 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 6), (0x3 << 6), 0, 0, 0 },
+ /* mux gpioe_3 to pwmao_d */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 12), (0xf << 12), 0, 0, 0 },
+
+ /*set pinmux GPIOD_2(I2CM_AO_A_SCL) and GPIOD_3(I2CM_AO_A_SDA) for pmic*/
+ { PADCTRL_GPIOD_DS, (0xf << 4), (0xf << 4), 0, 0, 0 },
+ { PADCTRL_GPIOD_PULL_EN, (0x3 << 2), (0x3 << 2), 0, 0, 0 },
+ { PADCTRL_GPIOD_PULL_UP, (0x3 << 2), (0x3 << 2), 0, 0, 0 },
+ { PADCTRL_PIN_MUX_REGA, (0x11 << 8), (0xff << 8), 0, 0, 0 },
+ { BD71837_REG_REGLOCK, 1, (1 << 4), 0, (I2C_BUS << 4) | (I2C_AO_A), I2C_DEV_ADDR },
+ /*set vddee voltage*/
+ { BD71837_REG_BUCK2_VOLT_RUN, VDDEE_VAL_REG, 0x3f, 0, \
+ (I2C_BUS << 4) | (I2C_AO_A), I2C_DEV_ADDR },
+ /*set vddcpub voltage*/
+ { BD71837_REG_BUCK3_VOLT_RUN, VCCK_B_VAL_REG, 0x3f, 0, \
+ (I2C_BUS << 4) | (I2C_AO_A), I2C_DEV_ADDR },
+ { BD71837_REG_MUXSW_EN, 1, 1, 0, \
+ (I2C_BUS << 4) | (I2C_AO_A), I2C_DEV_ADDR },
+
+ /* make watchdog send reset signal, !!please dont't copy below to other board
+ * which have no pmic or reset will not work
+ */
+ { PADCTRL_PIN_MUX_REGB, (0x1 << 16), (0xf << 16), 0, 0, 0 },
+ { RESETCTRL_WATCHDOG_CTRL1, (0x3ffff << 0), (0x3ffff << 0), 0, 0, 0 },
+ { RESETCTRL_SEC_WATCHDOG_CTRL1, (0x3ffff << 0), (0x3ffff << 0), 0, 0, 0 },
+ { PADCTRL_WD_RSTO_CTRL, (1 << 0), (1 << 0), 0, 0, 0 },
+};
+
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common ={
+ .version = 0x01,
+ .device_fip_container_size = 0x280000,
+ .device_fip_container_copies = 4,
+ },
+ .nand ={
+ .version = 0x01,
+ .bbt_pages = 0x1,
+ .bbt_start_block = 0x20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (4 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 128,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/t7_an400p_lpddr4x/fw_arb.cfg b/board/amlogic/t7_an400p_lpddr4x/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/t7_an400p_lpddr4x/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/t7_an400p_lpddr4x/lcd.c b/board/amlogic/t7_an400p_lpddr4x/lcd.c
new file mode 100644
index 0000000..eac94dd
--- /dev/null
+++ b/board/amlogic/t7_an400p_lpddr4x/lcd.c
@@ -0,0 +1,563 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+
+/***************************************************
+ * lcd_0
+ ***************************************************/
+static char lcd0_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOY_0", /* 12V */
+ "GPIOY_4", /* rst */
+ "invalid", /* ending flag */
+};
+
+static char lcd0_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOY_12", /* enable */
+ "GPIOY_1", /* pwm_e */
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0, 1, 50,}, /* panel vcc */
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_CPU, 0, 0, 200,}, /* panel vcc */
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_on_step_mipi[] = {
+ {LCD_POWER_TYPE_CPU, 1, 0, 0,}, /* rst */
+ {LCD_POWER_TYPE_CPU, 0, 0, 500,}, /* panel vcc */
+ {LCD_POWER_TYPE_CPU, 0, 1, 100,}, /* panel vcc */
+ {LCD_POWER_TYPE_CPU, 1, 1, 20,}, /* rst */
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_off_step_mipi[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_CPU, 1, 0, 0,}, /* rst */
+ {LCD_POWER_TYPE_CPU, 0, 0, 200,}, /* panel vcc */
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static unsigned char mipi_init_on_table_dft[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xfd, 1, 100,
+ 0x05, 1, 0x29,
+ 0xfd, 1, 20,
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table_dft[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xfd, 1, 100,
+ 0x05, 1, 0x10,
+ 0xfd, 1, 10,
+ 0xff, 0, //ending
+};
+
+struct ext_lcd_config_s ext_lcd0_config[LCD_NUM_MAX] = {
+ {/* normal*/
+ "lvds_0", LCD_LVDS, 8,
+ /* basic timing */
+ 1366, 768, 1569, 806, 56, 64, 0, 3, 28, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 0, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 2-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 2, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 1-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_1", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 1, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {"edp_0", LCD_EDP, 8,
+ /* basic timing */
+ 1920, 1080, 2200, 1120, 44, 148, 0, 5, 30, 0,
+ /* clk_attr */
+ 1, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* edp_attr */
+ 2, 1, 0, 0, 0, 0, 0, 0, 0x5, 0x1,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/* TL070WSH27*/
+ "mipi_0",LCD_MIPI,8,
+ /* basic timing */
+ 1024, 600, 1250, 630, 80, 100, 0, 5, 20, 0,
+ /* clk_attr */
+ 0, 0, 1, 47250000, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* mipi_attr */
+ 4, 300, 0, 1, 0, 2, 1, 0, Rsv_val, Rsv_val,
+ /* cmd init */
+ mipi_init_on_table_dft, mipi_init_off_table_dft,
+ /* power step */
+ lcd0_power_on_step_mipi, lcd0_power_off_step_mipi,
+ /* backlight */
+ 100, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_NEGATIVE, BL_PWM_E, 180, 100, 25, 1, 1,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd0_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_vbyone_pin", //GPIOY_10/12
+ .pinmux_set = {{0x14, 0x00030300}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x000f0f00}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "lcd_edp_pin", //GPIOY_10
+ .pinmux_set = {{0x14, 0x00000400}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x00000f00}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s lcd0_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", /*GPIOY_1*/
+ .pinmux_set = {{0x13, 0x00000030}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x13, 0x000000f0}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xc0, 2, 0x01, 0x2b,
+ 0xc0, 2, 0x02, 0x05,
+ 0xc0, 2, 0x03, 0x00,
+ 0xc0, 2, 0x04, 0x00,
+ 0xc0, 2, 0x05, 0x0c,
+ 0xc0, 2, 0x06, 0x04,
+ 0xc0, 2, 0x07, 0x21,
+ 0xc0, 2, 0x08, 0x0f,
+ 0xc0, 2, 0x09, 0x04,
+ 0xc0, 2, 0x0a, 0x00,
+ 0xc0, 2, 0x0b, 0x04,
+ 0xc0, 2, 0xff, 0x00,
+ 0xfd, 1, 100, /* delay 100ms */
+ 0xff, 0, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0} },
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0} },
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "invalid",
+ /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .type = LCD_EXTERN_MAX,
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x20, /* 7bit i2c address */
+ .i2c_addr2 = 0x74, /* 7bit i2c address, 0xff for none */
+ /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_1,
+ .cmd_size = 0xff,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+/***************************************************
+ * lcd_1
+ ***************************************************/
+static char lcd1_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOY_14", /* 12V */
+ "GPIOY_6", /* rst */
+ "invalid", /* ending flag */
+};
+
+static char lcd1_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOY_13", /* enable */
+ "GPIOY_8", /* pwm_f */
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0, 1, 50,}, /* panel vcc */
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_CPU, 0, 0, 200,}, /* panel vcc */
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_on_step_mipi[] = {
+ {LCD_POWER_TYPE_CPU, 1, 0, 0,}, /* rst */
+ {LCD_POWER_TYPE_CPU, 0, 0, 500,}, /* panel vcc */
+ {LCD_POWER_TYPE_CPU, 0, 1, 100,}, /* panel vcc */
+ {LCD_POWER_TYPE_CPU, 1, 1, 20,}, /* rst */
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_off_step_mipi[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_CPU, 1, 0, 0,}, /* rst */
+ {LCD_POWER_TYPE_CPU, 0, 0, 200,}, /* panel vcc */
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd1_config[LCD_NUM_MAX] = {
+ {/* normal*/
+ "lvds_0", LCD_LVDS, 8,
+ /* basic timing */
+ 1366, 768, 1569, 806, 56, 64, 0, 3, 28, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 0, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 2-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 2, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_F, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 1-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_1", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 1, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_F, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {"edp_0", LCD_EDP, 8,
+ /* basic timing */
+ 1920, 1080, 2200, 1120, 44, 148, 0, 5, 30, 0,
+ /* clk_attr */
+ 1, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* edp_attr */
+ 2, 1, 0, 0, 0, 0, 0, 0, 0x5, 0x1,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_F, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/* TL070WSH27*/
+ "mipi_0",LCD_MIPI,8,
+ /* basic timing */
+ 1024, 600, 1250, 630, 80, 100, 0, 5, 20, 0,
+ /* clk_attr */
+ 0, 0, 1, 47250000, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* mipi_attr */
+ 4, 300, 0, 1, 0, 2, 1, 0, Rsv_val, Rsv_val,
+ /* cmd init */
+ mipi_init_on_table_dft, mipi_init_off_table_dft,
+ /* power step */
+ lcd1_power_on_step_mipi, lcd1_power_off_step_mipi,
+ /* backlight */
+ 100, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_NEGATIVE, BL_PWM_F, 180, 100, 25, 1, 1,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd1_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_vbyone_pin", //GPIOY_11/13
+ .pinmux_set = {{0x14, 0x00303000}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x00f0f000}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "lcd_edp_pin", //GPIOY_11
+ .pinmux_set = {{0x14, 0x00004000}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x0000f000}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s lcd1_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", /*GPIOY_8*/
+ .pinmux_set = {{0x14, 0x00000003}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x0000000f}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+/***************************************************
+ * lcd_2
+ ***************************************************/
+static char lcd2_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOY_14",
+ "invalid", /* ending flag */
+};
+
+static char lcd2_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd2_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0, 1, 20,}, /* panel vcc */
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd2_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_CPU, 0, 0, 200,}, /* panel vcc */
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd2_config[LCD_NUM_MAX] = { //only support lvds
+ {/* normal*/
+ "lvds_0", LCD_LVDS, 8,
+ /* basic timing */
+ 1366, 768, 1569, 806, 56, 64, 0, 3, 28, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 0, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd2_power_on_step, lcd2_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/* for HDMI convert*/
+ "lvds_1", LCD_LVDS, 8,
+ /* basic timing */
+ 1920, 1080, 2200, 1125, 44, 148, 0, 5, 36, 0,
+ /* clk_attr */
+ 4, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 1, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd2_power_on_step, lcd2_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_MAX, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd2_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s lcd2_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "invalid",
+ },
+};
+
+/***************************************************
+ * lcd default config
+ ***************************************************/
+static struct lcd_dft_config_s lcd_dft_conf[] = {
+ {//index 0
+ .lcd_gpio = lcd0_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd0_config,
+ .lcd_pinmux = lcd0_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd0_bl_gpio,
+ .bl_pinmux = lcd0_bl_pinmux_ctrl,
+ },
+ {//index 1
+ .lcd_gpio = lcd1_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd1_config,
+ .lcd_pinmux = lcd1_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd1_bl_gpio,
+ .bl_pinmux = lcd1_bl_pinmux_ctrl,
+ },
+ {//index 2
+ .lcd_gpio = lcd2_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd2_config,
+ .lcd_pinmux = lcd2_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd2_bl_gpio,
+ .bl_pinmux = lcd2_bl_pinmux_ctrl,
+ }
+};
+
+void lcd_config_bsp_init(void)
+{
+ struct aml_lcd_data_s *pdata = aml_lcd_get_data();
+
+ if (pdata) {
+ pdata->dft_conf[0] = &lcd_dft_conf[0];
+ pdata->dft_conf[1] = &lcd_dft_conf[1];
+ pdata->dft_conf[2] = &lcd_dft_conf[2];
+ }
+}
diff --git a/board/amlogic/t7_an400p_lpddr4x/t7_an400p_lpddr4x.c b/board/amlogic/t7_an400p_lpddr4x/t7_an400p_lpddr4x.c
new file mode 100644
index 0000000..3422ca2
--- /dev/null
+++ b/board/amlogic/t7_an400p_lpddr4x/t7_an400p_lpddr4x.c
@@ -0,0 +1,406 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_VOUT
+#include <amlogic/media/vout/aml_vout.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/media/vout/lcd/lcd_vout.h>
+#endif
+#include <asm/arch/pmic_bd71837.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+ pmic_bd71837_init();
+
+ aml_set_bootsequence(0);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+#if 0 //bypass below operations for pxp
+ active_clk();
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+#endif
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ /*set vcc5V*/
+ run_command("gpio set GPIOH_1", 0);
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+ run_command("run bcb_cmd", 0);
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+#ifdef CONFIG_AML_VOUT
+ vout_probe();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0xe0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x100000000UL,
+ .phys = 0x100000000UL,
+ .size = 0x120000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xe0000000UL,
+ .phys = 0xe0000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ //printf("\nmach_cpu_init\n");
+#ifdef CONFIG_UPDATE_MMU_TABLE
+ unsigned long nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4;
+ if ( nddrSize <= 0xe0000000 )
+ {
+ bd_mem_map[0].size = nddrSize;
+ bd_mem_map[1].virt = 0;
+ bd_mem_map[1].phys = 0;
+ bd_mem_map[1].size = 0;
+ }
+#endif
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+#endif
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ strcpy(name, "t7_a311d2_an400p\0");
+ env_set("aml_dt", "t7_a311d2_an400p\0");
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/t7_an408_lpddr4x/Kconfig b/board/amlogic/t7_an408_lpddr4x/Kconfig
new file mode 100644
index 0000000..6aa8c56
--- /dev/null
+++ b/board/amlogic/t7_an408_lpddr4x/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_T7_AN408_LPDDR4X
+
+config SYS_SOC
+ default "t7"
+
+config SYS_BOARD
+ default "t7_an408_lpddr4x"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "t7_an408_lpddr4x"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+endif
diff --git a/board/amlogic/t7_an408_lpddr4x/Makefile b/board/amlogic/t7_an408_lpddr4x/Makefile
new file mode 100644
index 0000000..1e920e7
--- /dev/null
+++ b/board/amlogic/t7_an408_lpddr4x/Makefile
@@ -0,0 +1,3 @@
+obj-y += $(BOARD).o
+obj-$(CONFIG_AML_LCD) += lcd.o
+
diff --git a/board/amlogic/t7_an408_lpddr4x/firmware/timing.c b/board/amlogic/t7_an408_lpddr4x/firmware/timing.c
new file mode 100644
index 0000000..ca6b268
--- /dev/null
+++ b/board/amlogic/t7_an408_lpddr4x/firmware/timing.c
@@ -0,0 +1,1081 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+#define ENABLE_LPDDR4X_MODE 1
+
+#define AN_408_DDR0_1G_DDR1_0G 0
+#define AN_408_DDR0_2G_DDR1_0G 1
+#define AN_408_DDR0_1G_DDR1_1G 2
+#define AN_408_DDR0_2G_DDR1_1G 3
+#define AN_408_DDR0_2G_DDR1_2G 4
+#define AN_408_DDR0_2G_DDR1_2G_RANK01 5
+#define AN_408_DDR0_4G_DDR1_4G_RANK01 6
+
+#define DDR_SIZE_TYPE_1 AN_408_DDR0_1G_DDR1_1G //AN_408_DDR0_2G_DDR1_0G//AN_408_DDR0_2G_DDR1_1G//AN_408_DDR0_1G_DDR1_1G
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+#if 0
+ {
+ /* tl1 skt (x309) ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq ={ 1200, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x31f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0x23, 0x13 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x0, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 48, //48, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay ={ 32 + 20, 32 + 20, 32 + 20, 32 + 20, 32, 32 + 0, 32 + 20, 32 + 20, 32 + 20, 32 + 20},
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25),
+ [1] = (12 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 13 << 5 | 14 << 10 | 6 << 15 | 0 << 20 | 0 << 25),
+ },
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 00, 00 },
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC_COPY_CHANNEL_CFG, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux =
+ {
+ 2,
+ 5,
+ 20,
+ 14,
+ 8,
+ 24,
+ 4,
+ 13,
+ 25,
+ 12,
+ 10,
+ 23,
+ 26,
+ 18,
+ 0,
+ 0,
+ 0,
+ 9,
+ 1,
+ 19,
+ 0,
+ 22,
+ 11,
+ 7,
+ 6,
+ 3,
+ 0,
+ 0,
+ },
+ .dfi_pinmux =
+ {
+ 18,
+ 15,
+ 16,
+ 12,
+ 5,
+ 20,
+ 10,
+ 7,
+ 0,
+ 11,
+ 14,
+ 8,
+ 23,
+ 17,
+ 3,
+ 13,
+ 22,
+ 2,
+ 21,
+ 19,
+ 6,
+ 4,
+ 1,
+ 0,
+ 0,
+ 0,
+ },
+ },
+#endif
+#if 1
+ {
+ //.fast_boot[0]=0x000000fd,// 253
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .enable_lpddr4x_mode = ENABLE_LPDDR4X_MODE,
+ .DRAMFreq ={ 2016, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xc8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_4G_DDR1_4G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x131f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0, 0 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x3, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 60,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 240,
+ .soc_clk_slew_rate = 0x1ff,
+ .soc_cs_slew_rate = 0x1ff,
+ .soc_ac_slew_rate = 0x1ff,
+ .soc_data_slew_rate = 0x5ff,
+ .vref_output_permil = 629, //300
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 300,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting=0,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay ={ 32 + 10, 32, 0, 0, 0, 32 + 10, 32, 0, 0, 0},
+ //.ac_trace_delay ={ 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32, 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32 + 0},
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25),
+ [1] = (11 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 12 << 5 | 13 << 10 | 14 << 15 | 0 << 20 | 0 << 25),
+ },
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 7, 1, 5, 0, 2, 3, 4, 6,
+ 8, 15, 12, 13, 9, 10, 11, 14,
+ 22, 18, 21, 20, 17, 23, 16, 19,
+ 29, 30, 28, 31, 24, 27, 26, 25 },
+
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, // DDR_FUNC,
+ //.ddr_func = 0, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux ={ 2, 3, 1, 0, 5, 4, 0, 0, 0, 0,
+ 1, 3, 5, 2, 4, 0, 0, 0, 0 },
+
+ .dfi_pinmux =
+ {
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 0,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 0,
+ 0,
+ 0,
+ },
+ },
+
+ {
+ //.fast_boot[0]=0x000000fd,// 253
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .enable_lpddr4x_mode = ENABLE_LPDDR4X_MODE,
+ .DRAMFreq ={ 2016, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xc8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_4G_DDR1_4G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x131f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0, 0 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x3, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 60,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 240,
+ .soc_clk_slew_rate = 0x1ff,
+ .soc_cs_slew_rate = 0x1ff,
+ .soc_ac_slew_rate = 0x1ff,
+ .soc_data_slew_rate = 0x5ff,
+ .vref_output_permil = 629,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 300,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting=0,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ //.ac_trace_delay ={ 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32, 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32 + 0},
+ .ac_trace_delay ={ 32 + 10, 32, 0, 0, 0, 32 + 10, 32, 0, 0, 0},
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25),
+ [1] = (11 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 12 << 5 | 13 << 10 | 14 << 15 | 0 << 20 | 0 << 25),
+ },
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 4, 6, 5, 0, 7, 1, 2, 3,
+ 15, 11, 13, 14, 12, 9, 8, 10,
+ 21, 19, 22, 16, 18, 17, 23, 20,
+ 29, 30, 26, 25, 24, 27, 31, 28 },
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, // DDR_FUNC,
+ //.ddr_func = 0, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux ={ 2, 3, 1, 0, 5, 4, 0, 0, 0, 0,
+ 1, 3, 5, 2, 4, 0, 0, 0, 0 },
+
+ .dfi_pinmux =
+ {
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 0,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 0,
+ 0,
+ 0,
+ },
+ },
+#endif
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .low_console_baud = CONFIG_LOW_CONSOLE_BAUD,
+};
+
+#define VCCK_A_VAL AML_VCCK_A_INIT_VOLTAGE
+#define VCCK_B_VAL AML_VCCK_B_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+#define VDD_GPU_VAL AML_VDDGPU_INIT_VOLTAGE
+#define VDD_NPU_VAL AML_VDDNPU_INIT_VOLTAGE
+#define VDD_DDR_VAL AML_VDDDDR_INIT_VOLTAGE
+
+/* VCCK_A PWM table */
+#if (VCCK_A_VAL == 1039)
+#define VCCK_A_VAL_REG 0x00000022
+#elif (VCCK_A_VAL == 1029)
+#define VCCK_A_VAL_REG 0x00010021
+#elif (VCCK_A_VAL == 1019)
+#define VCCK_A_VAL_REG 0x00020020
+#elif (VCCK_A_VAL == 1009)
+#define VCCK_A_VAL_REG 0x0003001f
+#elif (VCCK_A_VAL == 999)
+#define VCCK_A_VAL_REG 0x0004001e
+#elif (VCCK_A_VAL == 989)
+#define VCCK_A_VAL_REG 0x0005001d
+#elif (VCCK_A_VAL == 979)
+#define VCCK_A_VAL_REG 0x0006001c
+#elif (VCCK_A_VAL == 969)
+#define VCCK_A_VAL_REG 0x0007001b
+#elif (VCCK_A_VAL == 959)
+#define VCCK_A_VAL_REG 0x0008001a
+#elif (VCCK_A_VAL == 949)
+#define VCCK_A_VAL_REG 0x00090019
+#elif (VCCK_A_VAL == 939)
+#define VCCK_A_VAL_REG 0x000a0018
+#elif (VCCK_A_VAL == 929)
+#define VCCK_A_VAL_REG 0x000b0017
+#elif (VCCK_A_VAL == 919)
+#define VCCK_A_VAL_REG 0x000c0016
+#elif (VCCK_A_VAL == 909)
+#define VCCK_A_VAL_REG 0x000d0015
+#elif (VCCK_A_VAL == 899)
+#define VCCK_A_VAL_REG 0x000e0014
+#elif (VCCK_A_VAL == 889)
+#define VCCK_A_VAL_REG 0x000f0013
+#elif (VCCK_A_VAL == 879)
+#define VCCK_A_VAL_REG 0x00100012
+#elif (VCCK_A_VAL == 869)
+#define VCCK_A_VAL_REG 0x00110011
+#elif (VCCK_A_VAL == 859)
+#define VCCK_A_VAL_REG 0x00120010
+#elif (VCCK_A_VAL == 849)
+#define VCCK_A_VAL_REG 0x0013000f
+#elif (VCCK_A_VAL == 839)
+#define VCCK_A_VAL_REG 0x0014000e
+#elif (VCCK_A_VAL == 829)
+#define VCCK_A_VAL_REG 0x0015000d
+#elif (VCCK_A_VAL == 819)
+#define VCCK_A_VAL_REG 0x0016000c
+#elif (VCCK_A_VAL == 809)
+#define VCCK_A_VAL_REG 0x0017000b
+#elif (VCCK_A_VAL == 799)
+#define VCCK_A_VAL_REG 0x0018000a
+#elif (VCCK_A_VAL == 789)
+#define VCCK_A_VAL_REG 0x00190009
+#elif (VCCK_A_VAL == 779)
+#define VCCK_A_VAL_REG 0x001a0008
+#elif (VCCK_A_VAL == 769)
+#define VCCK_A_VAL_REG 0x001b0007
+#elif (VCCK_A_VAL == 759)
+#define VCCK_A_VAL_REG 0x001c0006
+#elif (VCCK_A_VAL == 749)
+#define VCCK_A_VAL_REG 0x001d0005
+#elif (VCCK_A_VAL == 739)
+#define VCCK_A_VAL_REG 0x001e0004
+#elif (VCCK_A_VAL == 729)
+#define VCCK_A_VAL_REG 0x001f0003
+#elif (VCCK_A_VAL == 719)
+#define VCCK_A_VAL_REG 0x00200002
+#elif (VCCK_A_VAL == 709)
+#define VCCK_A_VAL_REG 0x00210001
+#elif (VCCK_A_VAL == 699)
+#define VCCK_A_VAL_REG 0x00220000
+#else
+#error "VCCK_A val out of range\n"
+#endif
+
+/* VCCK_B PWM table */
+#if (VCCK_B_VAL == 1039)
+#define VCCK_B_VAL_REG 0x00000022
+#elif (VCCK_B_VAL == 1029)
+#define VCCK_B_VAL_REG 0x00010021
+#elif (VCCK_B_VAL == 1019)
+#define VCCK_B_VAL_REG 0x00020020
+#elif (VCCK_B_VAL == 1009)
+#define VCCK_B_VAL_REG 0x0003001f
+#elif (VCCK_B_VAL == 999)
+#define VCCK_B_VAL_REG 0x0004001e
+#elif (VCCK_B_VAL == 989)
+#define VCCK_B_VAL_REG 0x0005001d
+#elif (VCCK_B_VAL == 979)
+#define VCCK_B_VAL_REG 0x0006001c
+#elif (VCCK_B_VAL == 969)
+#define VCCK_B_VAL_REG 0x0007001b
+#elif (VCCK_B_VAL == 959)
+#define VCCK_B_VAL_REG 0x0008001a
+#elif (VCCK_B_VAL == 949)
+#define VCCK_B_VAL_REG 0x00090019
+#elif (VCCK_B_VAL == 939)
+#define VCCK_B_VAL_REG 0x000a0018
+#elif (VCCK_B_VAL == 929)
+#define VCCK_B_VAL_REG 0x000b0017
+#elif (VCCK_B_VAL == 919)
+#define VCCK_B_VAL_REG 0x000c0016
+#elif (VCCK_B_VAL == 909)
+#define VCCK_B_VAL_REG 0x000d0015
+#elif (VCCK_B_VAL == 899)
+#define VCCK_B_VAL_REG 0x000e0014
+#elif (VCCK_B_VAL == 889)
+#define VCCK_B_VAL_REG 0x000f0013
+#elif (VCCK_B_VAL == 879)
+#define VCCK_B_VAL_REG 0x00100012
+#elif (VCCK_B_VAL == 869)
+#define VCCK_B_VAL_REG 0x00110011
+#elif (VCCK_B_VAL == 859)
+#define VCCK_B_VAL_REG 0x00120010
+#elif (VCCK_B_VAL == 849)
+#define VCCK_B_VAL_REG 0x0013000f
+#elif (VCCK_B_VAL == 839)
+#define VCCK_B_VAL_REG 0x0014000e
+#elif (VCCK_B_VAL == 829)
+#define VCCK_B_VAL_REG 0x0015000d
+#elif (VCCK_B_VAL == 819)
+#define VCCK_B_VAL_REG 0x0016000c
+#elif (VCCK_B_VAL == 809)
+#define VCCK_B_VAL_REG 0x0017000b
+#elif (VCCK_B_VAL == 799)
+#define VCCK_B_VAL_REG 0x0018000a
+#elif (VCCK_B_VAL == 789)
+#define VCCK_B_VAL_REG 0x00190009
+#elif (VCCK_B_VAL == 779)
+#define VCCK_B_VAL_REG 0x001a0008
+#elif (VCCK_B_VAL == 769)
+#define VCCK_B_VAL_REG 0x001b0007
+#elif (VCCK_B_VAL == 759)
+#define VCCK_B_VAL_REG 0x001c0006
+#elif (VCCK_B_VAL == 749)
+#define VCCK_B_VAL_REG 0x001d0005
+#elif (VCCK_B_VAL == 739)
+#define VCCK_B_VAL_REG 0x001e0004
+#elif (VCCK_B_VAL == 729)
+#define VCCK_B_VAL_REG 0x001f0003
+#elif (VCCK_B_VAL == 719)
+#define VCCK_B_VAL_REG 0x00200002
+#elif (VCCK_B_VAL == 709)
+#define VCCK_B_VAL_REG 0x00210001
+#elif (VCCK_B_VAL == 699)
+#define VCCK_B_VAL_REG 0x00220000
+#else
+#error "VCCK_B val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 711)
+#define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 721)
+#define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 731)
+#define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 741)
+#define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 751)
+#define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 761)
+#define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 771)
+#define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 781)
+#define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 791)
+#define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 801)
+#define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 811)
+#define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 821)
+#define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 831)
+#define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 841)
+#define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 851)
+#define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 861)
+#define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 871)
+#define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 881)
+#define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 891)
+#define VDDEE_VAL_REG 0x12
+#else
+#error "VDDEE val out of range\n"
+#endif
+
+/* VDD_GPU PWM table */
+#if (VDD_GPU_VAL == 711)
+#define VDD_GPU_VAL_REG 0x120000
+#elif (VDD_GPU_VAL == 721)
+#define VDD_GPU_VAL_REG 0x110001
+#elif (VDD_GPU_VAL == 731)
+#define VDD_GPU_VAL_REG 0x100002
+#elif (VDD_GPU_VAL == 741)
+#define VDD_GPU_VAL_REG 0xf0003
+#elif (VDD_GPU_VAL == 751)
+#define VDD_GPU_VAL_REG 0xe0004
+#elif (VDD_GPU_VAL == 761)
+#define VDD_GPU_VAL_REG 0xd0005
+#elif (VDD_GPU_VAL == 771)
+#define VDD_GPU_VAL_REG 0xc0006
+#elif (VDD_GPU_VAL == 781)
+#define VDD_GPU_VAL_REG 0xb0007
+#elif (VDD_GPU_VAL == 791)
+#define VDD_GPU_VAL_REG 0xa0008
+#elif (VDD_GPU_VAL == 801)
+#define VDD_GPU_VAL_REG 0x90009
+#elif (VDD_GPU_VAL == 811)
+#define VDD_GPU_VAL_REG 0x8000a
+#elif (VDD_GPU_VAL == 821)
+#define VDD_GPU_VAL_REG 0x7000b
+#elif (VDD_GPU_VAL == 831)
+#define VDD_GPU_VAL_REG 0x6000c
+#elif (VDD_GPU_VAL == 841)
+#define VDD_GPU_VAL_REG 0x5000d
+#elif (VDD_GPU_VAL == 851)
+#define VDD_GPU_VAL_REG 0x4000e
+#elif (VDD_GPU_VAL == 861)
+#define VDD_GPU_VAL_REG 0x3000f
+#elif (VDD_GPU_VAL == 871)
+#define VDD_GPU_VAL_REG 0x20010
+#elif (VDD_GPU_VAL == 881)
+#define VDD_GPU_VAL_REG 0x10011
+#elif (VDD_GPU_VAL == 891)
+#define VDD_GPU_VAL_REG 0x12
+#else
+#error "VDD_GPU val out of range\n"
+#endif
+
+/* VDD_NPU PWM table */
+#if (VDD_NPU_VAL == 711)
+#define VDD_NPU_VAL_REG 0x120000
+#elif (VDD_NPU_VAL == 721)
+#define VDD_NPU_VAL_REG 0x110001
+#elif (VDD_NPU_VAL == 731)
+#define VDD_NPU_VAL_REG 0x100002
+#elif (VDD_NPU_VAL == 741)
+#define VDD_NPU_VAL_REG 0xf0003
+#elif (VDD_NPU_VAL == 751)
+#define VDD_NPU_VAL_REG 0xe0004
+#elif (VDD_NPU_VAL == 761)
+#define VDD_NPU_VAL_REG 0xd0005
+#elif (VDD_NPU_VAL == 771)
+#define VDD_NPU_VAL_REG 0xc0006
+#elif (VDD_NPU_VAL == 781)
+#define VDD_NPU_VAL_REG 0xb0007
+#elif (VDD_NPU_VAL == 791)
+#define VDD_NPU_VAL_REG 0xa0008
+#elif (VDD_NPU_VAL == 801)
+#define VDD_NPU_VAL_REG 0x90009
+#elif (VDD_NPU_VAL == 811)
+#define VDD_NPU_VAL_REG 0x8000a
+#elif (VDD_NPU_VAL == 821)
+#define VDD_NPU_VAL_REG 0x7000b
+#elif (VDD_NPU_VAL == 831)
+#define VDD_NPU_VAL_REG 0x6000c
+#elif (VDD_NPU_VAL == 841)
+#define VDD_NPU_VAL_REG 0x5000d
+#elif (VDD_NPU_VAL == 851)
+#define VDD_NPU_VAL_REG 0x4000e
+#elif (VDD_NPU_VAL == 861)
+#define VDD_NPU_VAL_REG 0x3000f
+#elif (VDD_NPU_VAL == 871)
+#define VDD_NPU_VAL_REG 0x20010
+#elif (VDD_NPU_VAL == 881)
+#define VDD_NPU_VAL_REG 0x10011
+#elif (VDD_NPU_VAL == 891)
+#define VDD_NPU_VAL_REG 0x12
+#else
+#error "VDD_NPU val out of range\n"
+#endif
+
+/* VDD_DDR PWM table */
+#if (VDD_DDR_VAL == 711)
+#define VDD_DDR_VAL_REG 0x120000
+#elif (VDD_DDR_VAL == 721)
+#define VDD_DDR_VAL_REG 0x110001
+#elif (VDD_DDR_VAL == 731)
+#define VDD_DDR_VAL_REG 0x100002
+#elif (VDD_DDR_VAL == 741)
+#define VDD_DDR_VAL_REG 0xf0003
+#elif (VDD_DDR_VAL == 751)
+#define VDD_DDR_VAL_REG 0xe0004
+#elif (VDD_DDR_VAL == 761)
+#define VDD_DDR_VAL_REG 0xd0005
+#elif (VDD_DDR_VAL == 771)
+#define VDD_DDR_VAL_REG 0xc0006
+#elif (VDD_DDR_VAL == 781)
+#define VDD_DDR_VAL_REG 0xb0007
+#elif (VDD_DDR_VAL == 791)
+#define VDD_DDR_VAL_REG 0xa0008
+#elif (VDD_DDR_VAL == 801)
+#define VDD_DDR_VAL_REG 0x90009
+#elif (VDD_DDR_VAL == 811)
+#define VDD_DDR_VAL_REG 0x8000a
+#elif (VDD_DDR_VAL == 821)
+#define VDD_DDR_VAL_REG 0x7000b
+#elif (VDD_DDR_VAL == 831)
+#define VDD_DDR_VAL_REG 0x6000c
+#elif (VDD_DDR_VAL == 841)
+#define VDD_DDR_VAL_REG 0x5000d
+#elif (VDD_DDR_VAL == 851)
+#define VDD_DDR_VAL_REG 0x4000e
+#elif (VDD_DDR_VAL == 861)
+#define VDD_DDR_VAL_REG 0x3000f
+#elif (VDD_DDR_VAL == 871)
+#define VDD_DDR_VAL_REG 0x20010
+#elif (VDD_DDR_VAL == 881)
+#define VDD_DDR_VAL_REG 0x10011
+#elif (VDD_DDR_VAL == 891)
+#define VDD_DDR_VAL_REG 0x12
+#else
+#error "VDD_DDR val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ { 0, 0, 0xffffffff, 0, 0, 0 },
+};
+
+/* for PWM use */
+/*
+ * GPIOE_0 PWMAO_A VDDEE
+ * GPIOE_1 PWMAO_B VCCK_B
+ * GPIOE_3 PWMAO_D VCCK_A
+ * GPIOE_4 PWMAO_E VDDGPU
+ * GPIOE_5 PWMAO_F VDDNPU
+ * GPIOE_6 PWMAO_G VDDDDR
+ */
+/* gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+ /* demo, user defined override register */
+ /* config vddee pwm - pwmao_a */
+ { PWM_AO_AB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_AB_MISC_REG_AB, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_AB_CTRL, (0x1 << 8), (0x7FF << 0), 0, 0, 0 },
+ /* config vcck a pwm - pwmao_d */
+ { PWM_AO_CD_PWM_B, VCCK_A_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_CD_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_CD_CTRL, (0x1 << 24), (0x7FF << 16), 0, 0, 0 },
+ /* config vcck b pwm - pwmao_b */
+ { PWM_AO_AB_PWM_B, VCCK_B_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_AB_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_AB_CTRL, (0x1 << 24), (0x7FF << 16), 0, 0, 0 },
+ /* config vddgpu pwm - pwmao_e */
+ { PWM_AO_EF_PWM_A, VDD_GPU_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_EF_MISC_REG_AB, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_EF_CTRL, (0x1 << 8), (0x7FF << 0), 0, 0, 0 },
+ /* config vddnpu pwm - pwmao_f */
+ { PWM_AO_EF_PWM_B, VDD_NPU_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_EF_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_EF_CTRL, (0x1 << 24), (0x7FF << 16), 0, 0, 0 },
+ /* config vddddr pwm - pwmao_g */
+ { PWM_AO_GH_PWM_A, VDD_DDR_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_GH_MISC_REG_AB, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_GH_CTRL, (0x1 << 8), (0x7FF << 0), 0, 0, 0 },
+
+ /* enable vddee */
+ /* set gpioe_0 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 0), (0x3 << 0), 0, 0, 0 },
+ /* mux gpioe_0 to pwmao_a */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 0), (0xf << 0), 0, 0, 0 },
+
+ /* enable vddgpu */
+ /* set gpioe_4 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 8), (0x3 << 8), 0, 0, 0 },
+ /* mux gpioe_4 to pwmao_e */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 16), (0xf << 16), 0, 0, 0 },
+ /* set TEST_N to high(defualt high) */
+ //{PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0},
+ //{PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0},
+
+ /* enable vddnpu */
+ /* set gpioe_5 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 10), (0x3 << 10), 0, 0, 0 },
+ /* mux gpioe_5 to pwmao_F */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 20), (0xf << 20), 0, 0, 0 },
+
+ /* enable vcck b */
+ /* set gpioe_1 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 2), (0x3 << 2), 0, 0, 0 },
+ /* mux gpioe_1 to pwmao_b */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 4), (0xf << 4), 0, 0, 0 },
+
+ /* enable vcck a */
+ /* set gpioe_3 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 6), (0x3 << 6), 0, 0, 0 },
+ /* mux gpioe_3 to pwmao_d */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 12), (0xf << 12), 0, 0, 0 },
+ /* set gpiod_2 to high(defualt high) */
+ //{PADCTRL_GPIOD_O, (0x1 << 2), (0x1 << 2), 0, 0, 0},
+ //{PADCTRL_GPIOD_OEN, (0x0 << 2), (0x1 << 2), 0, 0, 0},
+ //{PADCTRL_PIN_MUX_REGA, (0x0 << 8), (0xf << 8), 0, 0, 0},
+
+ /* enable vddddr */
+ /* set gpioe_6 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 12), (0x3 << 12), 0, 0, 0 },
+ /* mux gpioe_6 to pwmao_g */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 24), (0xf << 24), 0, 0, 0 },
+};
+
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common ={
+ .version = 0x01,
+ .device_fip_container_size = 0x280000,
+ .device_fip_container_copies = 4,
+ },
+ .nand ={
+ .version = 0x01,
+ .bbt_pages = 0x1,
+ .bbt_start_block = 0x20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (4 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 128,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/t7_an408_lpddr4x/fw_arb.cfg b/board/amlogic/t7_an408_lpddr4x/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/t7_an408_lpddr4x/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/t7_an408_lpddr4x/lcd.c b/board/amlogic/t7_an408_lpddr4x/lcd.c
new file mode 100644
index 0000000..eac94dd
--- /dev/null
+++ b/board/amlogic/t7_an408_lpddr4x/lcd.c
@@ -0,0 +1,563 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+
+/***************************************************
+ * lcd_0
+ ***************************************************/
+static char lcd0_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOY_0", /* 12V */
+ "GPIOY_4", /* rst */
+ "invalid", /* ending flag */
+};
+
+static char lcd0_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOY_12", /* enable */
+ "GPIOY_1", /* pwm_e */
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0, 1, 50,}, /* panel vcc */
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_CPU, 0, 0, 200,}, /* panel vcc */
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_on_step_mipi[] = {
+ {LCD_POWER_TYPE_CPU, 1, 0, 0,}, /* rst */
+ {LCD_POWER_TYPE_CPU, 0, 0, 500,}, /* panel vcc */
+ {LCD_POWER_TYPE_CPU, 0, 1, 100,}, /* panel vcc */
+ {LCD_POWER_TYPE_CPU, 1, 1, 20,}, /* rst */
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_off_step_mipi[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_CPU, 1, 0, 0,}, /* rst */
+ {LCD_POWER_TYPE_CPU, 0, 0, 200,}, /* panel vcc */
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static unsigned char mipi_init_on_table_dft[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xfd, 1, 100,
+ 0x05, 1, 0x29,
+ 0xfd, 1, 20,
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table_dft[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xfd, 1, 100,
+ 0x05, 1, 0x10,
+ 0xfd, 1, 10,
+ 0xff, 0, //ending
+};
+
+struct ext_lcd_config_s ext_lcd0_config[LCD_NUM_MAX] = {
+ {/* normal*/
+ "lvds_0", LCD_LVDS, 8,
+ /* basic timing */
+ 1366, 768, 1569, 806, 56, 64, 0, 3, 28, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 0, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 2-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 2, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 1-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_1", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 1, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {"edp_0", LCD_EDP, 8,
+ /* basic timing */
+ 1920, 1080, 2200, 1120, 44, 148, 0, 5, 30, 0,
+ /* clk_attr */
+ 1, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* edp_attr */
+ 2, 1, 0, 0, 0, 0, 0, 0, 0x5, 0x1,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/* TL070WSH27*/
+ "mipi_0",LCD_MIPI,8,
+ /* basic timing */
+ 1024, 600, 1250, 630, 80, 100, 0, 5, 20, 0,
+ /* clk_attr */
+ 0, 0, 1, 47250000, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* mipi_attr */
+ 4, 300, 0, 1, 0, 2, 1, 0, Rsv_val, Rsv_val,
+ /* cmd init */
+ mipi_init_on_table_dft, mipi_init_off_table_dft,
+ /* power step */
+ lcd0_power_on_step_mipi, lcd0_power_off_step_mipi,
+ /* backlight */
+ 100, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_NEGATIVE, BL_PWM_E, 180, 100, 25, 1, 1,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd0_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_vbyone_pin", //GPIOY_10/12
+ .pinmux_set = {{0x14, 0x00030300}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x000f0f00}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "lcd_edp_pin", //GPIOY_10
+ .pinmux_set = {{0x14, 0x00000400}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x00000f00}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s lcd0_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", /*GPIOY_1*/
+ .pinmux_set = {{0x13, 0x00000030}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x13, 0x000000f0}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xc0, 2, 0x01, 0x2b,
+ 0xc0, 2, 0x02, 0x05,
+ 0xc0, 2, 0x03, 0x00,
+ 0xc0, 2, 0x04, 0x00,
+ 0xc0, 2, 0x05, 0x0c,
+ 0xc0, 2, 0x06, 0x04,
+ 0xc0, 2, 0x07, 0x21,
+ 0xc0, 2, 0x08, 0x0f,
+ 0xc0, 2, 0x09, 0x04,
+ 0xc0, 2, 0x0a, 0x00,
+ 0xc0, 2, 0x0b, 0x04,
+ 0xc0, 2, 0xff, 0x00,
+ 0xfd, 1, 100, /* delay 100ms */
+ 0xff, 0, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0} },
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0} },
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "invalid",
+ /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .type = LCD_EXTERN_MAX,
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x20, /* 7bit i2c address */
+ .i2c_addr2 = 0x74, /* 7bit i2c address, 0xff for none */
+ /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_1,
+ .cmd_size = 0xff,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+/***************************************************
+ * lcd_1
+ ***************************************************/
+static char lcd1_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOY_14", /* 12V */
+ "GPIOY_6", /* rst */
+ "invalid", /* ending flag */
+};
+
+static char lcd1_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOY_13", /* enable */
+ "GPIOY_8", /* pwm_f */
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0, 1, 50,}, /* panel vcc */
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_CPU, 0, 0, 200,}, /* panel vcc */
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_on_step_mipi[] = {
+ {LCD_POWER_TYPE_CPU, 1, 0, 0,}, /* rst */
+ {LCD_POWER_TYPE_CPU, 0, 0, 500,}, /* panel vcc */
+ {LCD_POWER_TYPE_CPU, 0, 1, 100,}, /* panel vcc */
+ {LCD_POWER_TYPE_CPU, 1, 1, 20,}, /* rst */
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_off_step_mipi[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_CPU, 1, 0, 0,}, /* rst */
+ {LCD_POWER_TYPE_CPU, 0, 0, 200,}, /* panel vcc */
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd1_config[LCD_NUM_MAX] = {
+ {/* normal*/
+ "lvds_0", LCD_LVDS, 8,
+ /* basic timing */
+ 1366, 768, 1569, 806, 56, 64, 0, 3, 28, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 0, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 2-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 2, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_F, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 1-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_1", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 1, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_F, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {"edp_0", LCD_EDP, 8,
+ /* basic timing */
+ 1920, 1080, 2200, 1120, 44, 148, 0, 5, 30, 0,
+ /* clk_attr */
+ 1, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* edp_attr */
+ 2, 1, 0, 0, 0, 0, 0, 0, 0x5, 0x1,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_F, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/* TL070WSH27*/
+ "mipi_0",LCD_MIPI,8,
+ /* basic timing */
+ 1024, 600, 1250, 630, 80, 100, 0, 5, 20, 0,
+ /* clk_attr */
+ 0, 0, 1, 47250000, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* mipi_attr */
+ 4, 300, 0, 1, 0, 2, 1, 0, Rsv_val, Rsv_val,
+ /* cmd init */
+ mipi_init_on_table_dft, mipi_init_off_table_dft,
+ /* power step */
+ lcd1_power_on_step_mipi, lcd1_power_off_step_mipi,
+ /* backlight */
+ 100, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 200, 200,
+ BL_PWM_NEGATIVE, BL_PWM_F, 180, 100, 25, 1, 1,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd1_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_vbyone_pin", //GPIOY_11/13
+ .pinmux_set = {{0x14, 0x00303000}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x00f0f000}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "lcd_edp_pin", //GPIOY_11
+ .pinmux_set = {{0x14, 0x00004000}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x0000f000}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s lcd1_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", /*GPIOY_8*/
+ .pinmux_set = {{0x14, 0x00000003}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x0000000f}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+/***************************************************
+ * lcd_2
+ ***************************************************/
+static char lcd2_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOY_14",
+ "invalid", /* ending flag */
+};
+
+static char lcd2_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd2_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0, 1, 20,}, /* panel vcc */
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd2_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_CPU, 0, 0, 200,}, /* panel vcc */
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd2_config[LCD_NUM_MAX] = { //only support lvds
+ {/* normal*/
+ "lvds_0", LCD_LVDS, 8,
+ /* basic timing */
+ 1366, 768, 1569, 806, 56, 64, 0, 3, 28, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 0, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd2_power_on_step, lcd2_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/* for HDMI convert*/
+ "lvds_1", LCD_LVDS, 8,
+ /* basic timing */
+ 1920, 1080, 2200, 1125, 44, 148, 0, 5, 36, 0,
+ /* clk_attr */
+ 4, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 1, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd2_power_on_step, lcd2_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_MAX, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd2_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s lcd2_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "invalid",
+ },
+};
+
+/***************************************************
+ * lcd default config
+ ***************************************************/
+static struct lcd_dft_config_s lcd_dft_conf[] = {
+ {//index 0
+ .lcd_gpio = lcd0_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd0_config,
+ .lcd_pinmux = lcd0_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd0_bl_gpio,
+ .bl_pinmux = lcd0_bl_pinmux_ctrl,
+ },
+ {//index 1
+ .lcd_gpio = lcd1_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd1_config,
+ .lcd_pinmux = lcd1_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd1_bl_gpio,
+ .bl_pinmux = lcd1_bl_pinmux_ctrl,
+ },
+ {//index 2
+ .lcd_gpio = lcd2_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd2_config,
+ .lcd_pinmux = lcd2_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd2_bl_gpio,
+ .bl_pinmux = lcd2_bl_pinmux_ctrl,
+ }
+};
+
+void lcd_config_bsp_init(void)
+{
+ struct aml_lcd_data_s *pdata = aml_lcd_get_data();
+
+ if (pdata) {
+ pdata->dft_conf[0] = &lcd_dft_conf[0];
+ pdata->dft_conf[1] = &lcd_dft_conf[1];
+ pdata->dft_conf[2] = &lcd_dft_conf[2];
+ }
+}
diff --git a/board/amlogic/t7_an408_lpddr4x/t7_an408_lpddr4x.c b/board/amlogic/t7_an408_lpddr4x/t7_an408_lpddr4x.c
new file mode 100644
index 0000000..c7880d3
--- /dev/null
+++ b/board/amlogic/t7_an408_lpddr4x/t7_an408_lpddr4x.c
@@ -0,0 +1,403 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_VOUT
+#include <amlogic/media/vout/aml_vout.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/media/vout/lcd/lcd_vout.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+ aml_set_bootsequence(0);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+#if 0
+ active_clk();
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+#endif
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ /*set vcc5V*/
+ run_command("gpio set GPIOH_1", 0);
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+ run_command("run bcb_cmd", 0);
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+#ifdef CONFIG_AML_VOUT
+ vout_probe();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0xe0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x100000000UL,
+ .phys = 0x100000000UL,
+ .size = 0x120000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xe0000000UL,
+ .phys = 0xe0000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ //printf("\nmach_cpu_init\n");
+#ifdef CONFIG_UPDATE_MMU_TABLE
+ unsigned long nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4;
+ if ( nddrSize <= 0xe0000000 )
+ {
+ bd_mem_map[0].size = nddrSize;
+ bd_mem_map[1].virt = 0;
+ bd_mem_map[1].phys = 0;
+ bd_mem_map[1].size = 0;
+ }
+#endif
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+#endif
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ strcpy(name, "t7_a311d2_an408\0");
+ env_set("aml_dt", "t7_a311d2_an408\0");
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/t7_an409_ddr4/Kconfig b/board/amlogic/t7_an409_ddr4/Kconfig
new file mode 100644
index 0000000..75f8d1b
--- /dev/null
+++ b/board/amlogic/t7_an409_ddr4/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_T7_AN409_DDR4
+
+config SYS_SOC
+ default "t7"
+
+config SYS_BOARD
+ default "t7_an409_ddr4"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "t7_an409_ddr4"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+endif
diff --git a/board/amlogic/t7_an409_ddr4/Makefile b/board/amlogic/t7_an409_ddr4/Makefile
new file mode 100644
index 0000000..1e920e7
--- /dev/null
+++ b/board/amlogic/t7_an409_ddr4/Makefile
@@ -0,0 +1,3 @@
+obj-y += $(BOARD).o
+obj-$(CONFIG_AML_LCD) += lcd.o
+
diff --git a/board/amlogic/t7_an409_ddr4/firmware/timing.c b/board/amlogic/t7_an409_ddr4/firmware/timing.c
new file mode 100644
index 0000000..7e2b533
--- /dev/null
+++ b/board/amlogic/t7_an409_ddr4/firmware/timing.c
@@ -0,0 +1,1101 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+#define ENABLE_LPDDR4X_MODE 1
+
+#define AN_408_DDR0_1G_DDR1_0G 0
+#define AN_408_DDR0_2G_DDR1_0G 1
+#define AN_408_DDR0_1G_DDR1_1G 2
+#define AN_408_DDR0_2G_DDR1_1G 3
+#define AN_408_DDR0_2G_DDR1_2G 4
+#define AN_408_DDR0_2G_DDR1_2G_RANK01 5
+#define AN_408_DDR0_4G_DDR1_4G_RANK01 6
+
+#define DDR_SIZE_TYPE_1 AN_408_DDR0_1G_DDR1_1G //AN_408_DDR0_2G_DDR1_0G//AN_408_DDR0_2G_DDR1_1G//AN_408_DDR0_1G_DDR1_1G
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+#if 1
+ {
+ /* tl1 skt (x309) ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq ={ 1200, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x31f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0x23, 0x13 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x0, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 48, //48, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay ={ 32 + 20, 32 + 20, 32 + 20, 32 + 20, 32, 32 + 0, 32 + 20, 32 + 20, 32 + 20, 32 + 20},
+ #if 0
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25),
+ [1] = (11 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 12 << 5 | 13 << 10 | 14 << 15 | 0 << 20 | 0 << 25),
+ },
+ #endif
+ #if 1
+ .ddr_dmc_remap =
+ {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ #endif
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 00, 00 },
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC_COPY_CHANNEL_CFG, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux =
+ {
+ 2,
+ 5,
+ 20,
+ 14,
+ 8,
+ 24,
+ 4,
+ 13,
+ 25,
+ 12,
+ 10,
+ 23,
+ 26,
+ 18,
+ 0,
+ 0,
+ 0,
+ 9,
+ 1,
+ 19,
+ 0,
+ 22,
+ 11,
+ 7,
+ 6,
+ 3,
+ 0,
+ 0,
+ },
+ .dfi_pinmux =
+ {
+ 18,
+ 15,
+ 16,
+ 12,
+ 5,
+ 20,
+ 10,
+ 7,
+ 0,
+ 11,
+ 14,
+ 8,
+ 23,
+ 17,
+ 3,
+ 13,
+ 22,
+ 2,
+ 21,
+ 19,
+ 6,
+ 4,
+ 1,
+ 0,
+ 0,
+ 0,
+ },
+ },
+#endif
+#if 1
+ {
+ //.fast_boot[0]=0x000000fd,// 253
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .enable_lpddr4x_mode = ENABLE_LPDDR4X_MODE,
+ .DRAMFreq ={ 1200, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xc8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_4G_DDR1_4G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x131f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0x23, 0x13 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x0, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 40,
+ .soc_data_odt_ohm_n = 40,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 40, //60,
+ .dram_ac_odt_ohm = 240,
+ .soc_clk_slew_rate = 0x1ff,
+ .soc_cs_slew_rate = 0x1ff,
+ .soc_ac_slew_rate = 0x1ff,
+ .soc_data_slew_rate = 0x5ff,
+ .vref_output_permil = 000, //300
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 200,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay ={ 32 + 10, 32, 0, 0, 0, 32 + 10, 32, 0, 0, 0},
+ //.ac_trace_delay ={ 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32, 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32 + 0},
+ #if 0
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25),
+ [1] = (11 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 12 << 5 | 13 << 10 | 14 << 15 | 0 << 20 | 0 << 25),
+ },
+ #endif
+ #if 1
+ .ddr_dmc_remap =
+ {
+ [0] = ( 5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25 ),
+ [1] = ( 12| 0 << 5 | 0 << 10 | 14 << 15 | 15 << 20 | 16 << 25 ),
+ [2] = ( 17| 18 << 5 | 19 << 10 | 21 << 15 | 22 << 20 | 23 << 25 ),
+ [3] = ( 24| 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25 ),
+ [4] = ( 30| 13 << 5 | 20 << 10 | 6 << 15 | 0 << 20 | 0 << 25 ),
+ },
+ #endif
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 7, 1, 5, 0, 2, 3, 4, 6,
+ 8, 15, 12, 13, 9, 10, 11, 14,
+ 22, 18, 21, 20, 17, 23, 16, 19,
+ 29, 30, 28, 31, 24, 27, 26, 25 },
+
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = 0, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux ={ 2, 3, 1, 0, 5, 4, 0, 0, 0, 0,
+ 1, 3, 5, 2, 4, 0, 0, 0, 0 },
+
+ .dfi_pinmux =
+ {
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 0,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 0,
+ 0,
+ 0,
+ },
+ },
+
+ {
+ //.fast_boot[0]=0x000000fd,// 253
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .enable_lpddr4x_mode = ENABLE_LPDDR4X_MODE,
+ .DRAMFreq ={ 1200, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xc8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_4G_DDR1_4G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x131f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0x23, 0x13 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x0, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 40,
+ .soc_data_odt_ohm_n = 40,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 40, //60,
+ .dram_ac_odt_ohm = 240,
+ .soc_clk_slew_rate = 0x1ff,
+ .soc_cs_slew_rate = 0x1ff,
+ .soc_ac_slew_rate = 0x1ff,
+ .soc_data_slew_rate = 0x5ff,
+ .vref_output_permil = 000,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 200,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ //.ac_trace_delay ={ 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32, 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32 + 0},
+ .ac_trace_delay ={ 32 + 10, 32, 0, 0, 0, 32 + 10, 32, 0, 0, 0},
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25),
+ [1] = (11 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 12 << 5 | 13 << 10 | 14 << 15 | 0 << 20 | 0 << 25),
+ },
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 4, 6, 5, 0, 7, 1, 2, 3,
+ 15, 11, 13, 14, 12, 9, 8, 10,
+ 21, 19, 22, 16, 18, 17, 23, 20,
+ 29, 30, 26, 25, 24, 27, 31, 28 },
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = 0, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux ={ 2, 3, 1, 0, 5, 4, 0, 0, 0, 0,
+ 1, 3, 5, 2, 4, 0, 0, 0, 0 },
+
+ .dfi_pinmux =
+ {
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 0,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 0,
+ 0,
+ 0,
+ },
+ },
+#endif
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .low_console_baud = CONFIG_LOW_CONSOLE_BAUD,
+};
+
+#define VCCK_A_VAL AML_VCCK_A_INIT_VOLTAGE
+#define VCCK_B_VAL AML_VCCK_B_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+#define VDD_GPU_VAL AML_VDDGPU_INIT_VOLTAGE
+#define VDD_NPU_VAL AML_VDDNPU_INIT_VOLTAGE
+#define VDD_DDR_VAL AML_VDDDDR_INIT_VOLTAGE
+
+/* VCCK_A PWM table */
+#if (VCCK_A_VAL == 1039)
+#define VCCK_A_VAL_REG 0x00000022
+#elif (VCCK_A_VAL == 1029)
+#define VCCK_A_VAL_REG 0x00010021
+#elif (VCCK_A_VAL == 1019)
+#define VCCK_A_VAL_REG 0x00020020
+#elif (VCCK_A_VAL == 1009)
+#define VCCK_A_VAL_REG 0x0003001f
+#elif (VCCK_A_VAL == 999)
+#define VCCK_A_VAL_REG 0x0004001e
+#elif (VCCK_A_VAL == 989)
+#define VCCK_A_VAL_REG 0x0005001d
+#elif (VCCK_A_VAL == 979)
+#define VCCK_A_VAL_REG 0x0006001c
+#elif (VCCK_A_VAL == 969)
+#define VCCK_A_VAL_REG 0x0007001b
+#elif (VCCK_A_VAL == 959)
+#define VCCK_A_VAL_REG 0x0008001a
+#elif (VCCK_A_VAL == 949)
+#define VCCK_A_VAL_REG 0x00090019
+#elif (VCCK_A_VAL == 939)
+#define VCCK_A_VAL_REG 0x000a0018
+#elif (VCCK_A_VAL == 929)
+#define VCCK_A_VAL_REG 0x000b0017
+#elif (VCCK_A_VAL == 919)
+#define VCCK_A_VAL_REG 0x000c0016
+#elif (VCCK_A_VAL == 909)
+#define VCCK_A_VAL_REG 0x000d0015
+#elif (VCCK_A_VAL == 899)
+#define VCCK_A_VAL_REG 0x000e0014
+#elif (VCCK_A_VAL == 889)
+#define VCCK_A_VAL_REG 0x000f0013
+#elif (VCCK_A_VAL == 879)
+#define VCCK_A_VAL_REG 0x00100012
+#elif (VCCK_A_VAL == 869)
+#define VCCK_A_VAL_REG 0x00110011
+#elif (VCCK_A_VAL == 859)
+#define VCCK_A_VAL_REG 0x00120010
+#elif (VCCK_A_VAL == 849)
+#define VCCK_A_VAL_REG 0x0013000f
+#elif (VCCK_A_VAL == 839)
+#define VCCK_A_VAL_REG 0x0014000e
+#elif (VCCK_A_VAL == 829)
+#define VCCK_A_VAL_REG 0x0015000d
+#elif (VCCK_A_VAL == 819)
+#define VCCK_A_VAL_REG 0x0016000c
+#elif (VCCK_A_VAL == 809)
+#define VCCK_A_VAL_REG 0x0017000b
+#elif (VCCK_A_VAL == 799)
+#define VCCK_A_VAL_REG 0x0018000a
+#elif (VCCK_A_VAL == 789)
+#define VCCK_A_VAL_REG 0x00190009
+#elif (VCCK_A_VAL == 779)
+#define VCCK_A_VAL_REG 0x001a0008
+#elif (VCCK_A_VAL == 769)
+#define VCCK_A_VAL_REG 0x001b0007
+#elif (VCCK_A_VAL == 759)
+#define VCCK_A_VAL_REG 0x001c0006
+#elif (VCCK_A_VAL == 749)
+#define VCCK_A_VAL_REG 0x001d0005
+#elif (VCCK_A_VAL == 739)
+#define VCCK_A_VAL_REG 0x001e0004
+#elif (VCCK_A_VAL == 729)
+#define VCCK_A_VAL_REG 0x001f0003
+#elif (VCCK_A_VAL == 719)
+#define VCCK_A_VAL_REG 0x00200002
+#elif (VCCK_A_VAL == 709)
+#define VCCK_A_VAL_REG 0x00210001
+#elif (VCCK_A_VAL == 699)
+#define VCCK_A_VAL_REG 0x00220000
+#else
+#error "VCCK_A val out of range\n"
+#endif
+
+/* VCCK_B PWM table */
+#if (VCCK_B_VAL == 1039)
+#define VCCK_B_VAL_REG 0x00000022
+#elif (VCCK_B_VAL == 1029)
+#define VCCK_B_VAL_REG 0x00010021
+#elif (VCCK_B_VAL == 1019)
+#define VCCK_B_VAL_REG 0x00020020
+#elif (VCCK_B_VAL == 1009)
+#define VCCK_B_VAL_REG 0x0003001f
+#elif (VCCK_B_VAL == 999)
+#define VCCK_B_VAL_REG 0x0004001e
+#elif (VCCK_B_VAL == 989)
+#define VCCK_B_VAL_REG 0x0005001d
+#elif (VCCK_B_VAL == 979)
+#define VCCK_B_VAL_REG 0x0006001c
+#elif (VCCK_B_VAL == 969)
+#define VCCK_B_VAL_REG 0x0007001b
+#elif (VCCK_B_VAL == 959)
+#define VCCK_B_VAL_REG 0x0008001a
+#elif (VCCK_B_VAL == 949)
+#define VCCK_B_VAL_REG 0x00090019
+#elif (VCCK_B_VAL == 939)
+#define VCCK_B_VAL_REG 0x000a0018
+#elif (VCCK_B_VAL == 929)
+#define VCCK_B_VAL_REG 0x000b0017
+#elif (VCCK_B_VAL == 919)
+#define VCCK_B_VAL_REG 0x000c0016
+#elif (VCCK_B_VAL == 909)
+#define VCCK_B_VAL_REG 0x000d0015
+#elif (VCCK_B_VAL == 899)
+#define VCCK_B_VAL_REG 0x000e0014
+#elif (VCCK_B_VAL == 889)
+#define VCCK_B_VAL_REG 0x000f0013
+#elif (VCCK_B_VAL == 879)
+#define VCCK_B_VAL_REG 0x00100012
+#elif (VCCK_B_VAL == 869)
+#define VCCK_B_VAL_REG 0x00110011
+#elif (VCCK_B_VAL == 859)
+#define VCCK_B_VAL_REG 0x00120010
+#elif (VCCK_B_VAL == 849)
+#define VCCK_B_VAL_REG 0x0013000f
+#elif (VCCK_B_VAL == 839)
+#define VCCK_B_VAL_REG 0x0014000e
+#elif (VCCK_B_VAL == 829)
+#define VCCK_B_VAL_REG 0x0015000d
+#elif (VCCK_B_VAL == 819)
+#define VCCK_B_VAL_REG 0x0016000c
+#elif (VCCK_B_VAL == 809)
+#define VCCK_B_VAL_REG 0x0017000b
+#elif (VCCK_B_VAL == 799)
+#define VCCK_B_VAL_REG 0x0018000a
+#elif (VCCK_B_VAL == 789)
+#define VCCK_B_VAL_REG 0x00190009
+#elif (VCCK_B_VAL == 779)
+#define VCCK_B_VAL_REG 0x001a0008
+#elif (VCCK_B_VAL == 769)
+#define VCCK_B_VAL_REG 0x001b0007
+#elif (VCCK_B_VAL == 759)
+#define VCCK_B_VAL_REG 0x001c0006
+#elif (VCCK_B_VAL == 749)
+#define VCCK_B_VAL_REG 0x001d0005
+#elif (VCCK_B_VAL == 739)
+#define VCCK_B_VAL_REG 0x001e0004
+#elif (VCCK_B_VAL == 729)
+#define VCCK_B_VAL_REG 0x001f0003
+#elif (VCCK_B_VAL == 719)
+#define VCCK_B_VAL_REG 0x00200002
+#elif (VCCK_B_VAL == 709)
+#define VCCK_B_VAL_REG 0x00210001
+#elif (VCCK_B_VAL == 699)
+#define VCCK_B_VAL_REG 0x00220000
+#else
+#error "VCCK_B val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 711)
+#define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 721)
+#define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 731)
+#define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 741)
+#define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 751)
+#define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 761)
+#define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 771)
+#define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 781)
+#define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 791)
+#define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 801)
+#define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 811)
+#define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 821)
+#define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 831)
+#define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 841)
+#define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 851)
+#define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 861)
+#define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 871)
+#define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 881)
+#define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 891)
+#define VDDEE_VAL_REG 0x12
+#else
+#error "VDDEE val out of range\n"
+#endif
+
+/* VDD_GPU PWM table */
+#if (VDD_GPU_VAL == 711)
+#define VDD_GPU_VAL_REG 0x120000
+#elif (VDD_GPU_VAL == 721)
+#define VDD_GPU_VAL_REG 0x110001
+#elif (VDD_GPU_VAL == 731)
+#define VDD_GPU_VAL_REG 0x100002
+#elif (VDD_GPU_VAL == 741)
+#define VDD_GPU_VAL_REG 0xf0003
+#elif (VDD_GPU_VAL == 751)
+#define VDD_GPU_VAL_REG 0xe0004
+#elif (VDD_GPU_VAL == 761)
+#define VDD_GPU_VAL_REG 0xd0005
+#elif (VDD_GPU_VAL == 771)
+#define VDD_GPU_VAL_REG 0xc0006
+#elif (VDD_GPU_VAL == 781)
+#define VDD_GPU_VAL_REG 0xb0007
+#elif (VDD_GPU_VAL == 791)
+#define VDD_GPU_VAL_REG 0xa0008
+#elif (VDD_GPU_VAL == 801)
+#define VDD_GPU_VAL_REG 0x90009
+#elif (VDD_GPU_VAL == 811)
+#define VDD_GPU_VAL_REG 0x8000a
+#elif (VDD_GPU_VAL == 821)
+#define VDD_GPU_VAL_REG 0x7000b
+#elif (VDD_GPU_VAL == 831)
+#define VDD_GPU_VAL_REG 0x6000c
+#elif (VDD_GPU_VAL == 841)
+#define VDD_GPU_VAL_REG 0x5000d
+#elif (VDD_GPU_VAL == 851)
+#define VDD_GPU_VAL_REG 0x4000e
+#elif (VDD_GPU_VAL == 861)
+#define VDD_GPU_VAL_REG 0x3000f
+#elif (VDD_GPU_VAL == 871)
+#define VDD_GPU_VAL_REG 0x20010
+#elif (VDD_GPU_VAL == 881)
+#define VDD_GPU_VAL_REG 0x10011
+#elif (VDD_GPU_VAL == 891)
+#define VDD_GPU_VAL_REG 0x12
+#else
+#error "VDD_GPU val out of range\n"
+#endif
+
+/* VDD_NPU PWM table */
+#if (VDD_NPU_VAL == 711)
+#define VDD_NPU_VAL_REG 0x120000
+#elif (VDD_NPU_VAL == 721)
+#define VDD_NPU_VAL_REG 0x110001
+#elif (VDD_NPU_VAL == 731)
+#define VDD_NPU_VAL_REG 0x100002
+#elif (VDD_NPU_VAL == 741)
+#define VDD_NPU_VAL_REG 0xf0003
+#elif (VDD_NPU_VAL == 751)
+#define VDD_NPU_VAL_REG 0xe0004
+#elif (VDD_NPU_VAL == 761)
+#define VDD_NPU_VAL_REG 0xd0005
+#elif (VDD_NPU_VAL == 771)
+#define VDD_NPU_VAL_REG 0xc0006
+#elif (VDD_NPU_VAL == 781)
+#define VDD_NPU_VAL_REG 0xb0007
+#elif (VDD_NPU_VAL == 791)
+#define VDD_NPU_VAL_REG 0xa0008
+#elif (VDD_NPU_VAL == 801)
+#define VDD_NPU_VAL_REG 0x90009
+#elif (VDD_NPU_VAL == 811)
+#define VDD_NPU_VAL_REG 0x8000a
+#elif (VDD_NPU_VAL == 821)
+#define VDD_NPU_VAL_REG 0x7000b
+#elif (VDD_NPU_VAL == 831)
+#define VDD_NPU_VAL_REG 0x6000c
+#elif (VDD_NPU_VAL == 841)
+#define VDD_NPU_VAL_REG 0x5000d
+#elif (VDD_NPU_VAL == 851)
+#define VDD_NPU_VAL_REG 0x4000e
+#elif (VDD_NPU_VAL == 861)
+#define VDD_NPU_VAL_REG 0x3000f
+#elif (VDD_NPU_VAL == 871)
+#define VDD_NPU_VAL_REG 0x20010
+#elif (VDD_NPU_VAL == 881)
+#define VDD_NPU_VAL_REG 0x10011
+#elif (VDD_NPU_VAL == 891)
+#define VDD_NPU_VAL_REG 0x12
+#else
+#error "VDD_NPU val out of range\n"
+#endif
+
+/* VDD_DDR PWM table */
+#if (VDD_DDR_VAL == 711)
+#define VDD_DDR_VAL_REG 0x120000
+#elif (VDD_DDR_VAL == 721)
+#define VDD_DDR_VAL_REG 0x110001
+#elif (VDD_DDR_VAL == 731)
+#define VDD_DDR_VAL_REG 0x100002
+#elif (VDD_DDR_VAL == 741)
+#define VDD_DDR_VAL_REG 0xf0003
+#elif (VDD_DDR_VAL == 751)
+#define VDD_DDR_VAL_REG 0xe0004
+#elif (VDD_DDR_VAL == 761)
+#define VDD_DDR_VAL_REG 0xd0005
+#elif (VDD_DDR_VAL == 771)
+#define VDD_DDR_VAL_REG 0xc0006
+#elif (VDD_DDR_VAL == 781)
+#define VDD_DDR_VAL_REG 0xb0007
+#elif (VDD_DDR_VAL == 791)
+#define VDD_DDR_VAL_REG 0xa0008
+#elif (VDD_DDR_VAL == 801)
+#define VDD_DDR_VAL_REG 0x90009
+#elif (VDD_DDR_VAL == 811)
+#define VDD_DDR_VAL_REG 0x8000a
+#elif (VDD_DDR_VAL == 821)
+#define VDD_DDR_VAL_REG 0x7000b
+#elif (VDD_DDR_VAL == 831)
+#define VDD_DDR_VAL_REG 0x6000c
+#elif (VDD_DDR_VAL == 841)
+#define VDD_DDR_VAL_REG 0x5000d
+#elif (VDD_DDR_VAL == 851)
+#define VDD_DDR_VAL_REG 0x4000e
+#elif (VDD_DDR_VAL == 861)
+#define VDD_DDR_VAL_REG 0x3000f
+#elif (VDD_DDR_VAL == 871)
+#define VDD_DDR_VAL_REG 0x20010
+#elif (VDD_DDR_VAL == 881)
+#define VDD_DDR_VAL_REG 0x10011
+#elif (VDD_DDR_VAL == 891)
+#define VDD_DDR_VAL_REG 0x12
+#else
+#error "VDD_DDR val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ { 0, 0, 0xffffffff, 0, 0, 0 },
+};
+
+/* for PWM use */
+/*
+ * GPIOE_0 PWMAO_A VDDEE
+ * GPIOE_1 PWMAO_B VCCK_B
+ * GPIOE_3 PWMAO_D VCCK_A
+ * GPIOE_4 PWMAO_E VDDGPU
+ * GPIOE_5 PWMAO_F VDDNPU
+ * GPIOE_6 PWMAO_G VDDDDR
+ */
+/* gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+ /* demo, user defined override register */
+ /* config vddee pwm - pwmao_a */
+ { PWM_AO_AB_PWM_A, VDDEE_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_AB_MISC_REG_AB, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_AB_CTRL, (0x1 << 8), (0x7FF << 0), 0, 0, 0 },
+ /* config vcck a pwm - pwmao_d */
+ { PWM_AO_CD_PWM_B, VCCK_A_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_CD_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_CD_CTRL, (0x1 << 24), (0x7FF << 16), 0, 0, 0 },
+ /* config vcck b pwm - pwmao_b */
+ { PWM_AO_AB_PWM_B, VCCK_B_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_AB_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_AB_CTRL, (0x1 << 24), (0x7FF << 16), 0, 0, 0 },
+ /* config vddgpu pwm - pwmao_e */
+ { PWM_AO_EF_PWM_A, VDD_GPU_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_EF_MISC_REG_AB, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_EF_CTRL, (0x1 << 8), (0x7FF << 0), 0, 0, 0 },
+ /* config vddnpu pwm - pwmao_f */
+ { PWM_AO_EF_PWM_B, VDD_NPU_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_EF_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_EF_CTRL, (0x1 << 24), (0x7FF << 16), 0, 0, 0 },
+ /* config vddddr pwm - pwmao_g */
+ { PWM_AO_GH_PWM_A, VDD_DDR_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_GH_MISC_REG_AB, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_GH_CTRL, (0x1 << 8), (0x7FF << 0), 0, 0, 0 },
+
+ /* enable vddee */
+ /* set gpioe_0 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 0), (0x3 << 0), 0, 0, 0 },
+ /* mux gpioe_0 to pwmao_a */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 0), (0xf << 0), 0, 0, 0 },
+
+ /* enable vddgpu */
+ /* set gpioe_4 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 8), (0x3 << 8), 0, 0, 0 },
+ /* mux gpioe_4 to pwmao_e */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 16), (0xf << 16), 0, 0, 0 },
+ /* set TEST_N to high(defualt high) */
+ //{PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0},
+ //{PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0},
+
+ /* enable vddnpu */
+ /* set gpioe_5 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 10), (0x3 << 10), 0, 0, 0 },
+ /* mux gpioe_5 to pwmao_F */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 20), (0xf << 20), 0, 0, 0 },
+
+ /* enable vcck b */
+ /* set gpioe_1 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 2), (0x3 << 2), 0, 0, 0 },
+ /* mux gpioe_1 to pwmao_b */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 4), (0xf << 4), 0, 0, 0 },
+
+ /* enable vcck a */
+ /* set gpioe_3 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 6), (0x3 << 6), 0, 0, 0 },
+ /* mux gpioe_3 to pwmao_d */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 12), (0xf << 12), 0, 0, 0 },
+ /* set gpiod_2 to high(defualt high) */
+ //{PADCTRL_GPIOD_O, (0x1 << 2), (0x1 << 2), 0, 0, 0},
+ //{PADCTRL_GPIOD_OEN, (0x0 << 2), (0x1 << 2), 0, 0, 0},
+ //{PADCTRL_PIN_MUX_REGA, (0x0 << 8), (0xf << 8), 0, 0, 0},
+
+ /* enable vddddr */
+ /* set gpioe_6 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 12), (0x3 << 12), 0, 0, 0 },
+ /* mux gpioe_6 to pwmao_g */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 24), (0xf << 24), 0, 0, 0 },
+};
+
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common ={
+ .version = 0x01,
+ .device_fip_container_size = 0x280000,
+ .device_fip_container_copies = 4,
+ },
+ .nand ={
+ .version = 0x01,
+ .bbt_pages = 0x1,
+ .bbt_start_block = 0x20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (4 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 128,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/t7_an409_ddr4/fw_arb.cfg b/board/amlogic/t7_an409_ddr4/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/t7_an409_ddr4/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/t7_an409_ddr4/lcd.c b/board/amlogic/t7_an409_ddr4/lcd.c
new file mode 100644
index 0000000..7452887
--- /dev/null
+++ b/board/amlogic/t7_an409_ddr4/lcd.c
@@ -0,0 +1,536 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+
+/***************************************************
+ * lcd_0
+ ***************************************************/
+static char lcd0_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static char lcd0_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_on_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_off_step[] = {
+ {LCD_POWER_TYPE_CPU, 0, 0, 200,}, /* panel vcc */
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_on_step_mipi[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_off_step_mipi[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static unsigned char mipi_init_on_table_dft[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xfd, 1, 100,
+ 0x05, 1, 0x29,
+ 0xfd, 1, 20,
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table_dft[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xfd, 1, 100,
+ 0x05, 1, 0x10,
+ 0xfd, 1, 10,
+ 0xff, 0, //ending
+};
+
+struct ext_lcd_config_s ext_lcd0_config[LCD_NUM_MAX] = {
+ {/* normal*/
+ "lvds_0", LCD_LVDS, 8,
+ /* basic timing */
+ 1366, 768, 1569, 806, 56, 64, 0, 3, 28, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 0, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 2-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 2, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 1-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_1", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 1, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {"edp_0", LCD_EDP, 8,
+ /* basic timing */
+ 1920, 1080, 2200, 1120, 44, 148, 0, 5, 30, 0,
+ /* clk_attr */
+ 1, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* edp_attr */
+ 2, 1, 0, 0, 0, 0, 0, 0, 0x5, 0x1,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/* TL070WSH27*/
+ "mipi_0",LCD_MIPI,8,
+ /* basic timing */
+ 1024, 600, 1250, 630, 80, 100, 0, 5, 20, 0,
+ /* clk_attr */
+ 0, 0, 1, 47250000, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* mipi_attr */
+ 4, 300, 0, 1, 0, 2, 1, 0, Rsv_val, Rsv_val,
+ /* cmd init */
+ mipi_init_on_table_dft, mipi_init_off_table_dft,
+ /* power step */
+ lcd0_power_on_step_mipi, lcd0_power_off_step_mipi,
+ /* backlight */
+ 100, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_NEGATIVE, BL_PWM_E, 180, 100, 25, 1, 1,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd0_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_vbyone_pin", //GPIOY_10/12
+ .pinmux_set = {{0x14, 0x00030300}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x000f0f00}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "lcd_edp_pin", //GPIOY_10
+ .pinmux_set = {{0x14, 0x00000400}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x00000f00}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s lcd0_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", /*GPIOY_1*/
+ .pinmux_set = {{0x13, 0x00000030}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x13, 0x000000f0}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xc0, 2, 0x01, 0x2b,
+ 0xc0, 2, 0x02, 0x05,
+ 0xc0, 2, 0x03, 0x00,
+ 0xc0, 2, 0x04, 0x00,
+ 0xc0, 2, 0x05, 0x0c,
+ 0xc0, 2, 0x06, 0x04,
+ 0xc0, 2, 0x07, 0x21,
+ 0xc0, 2, 0x08, 0x0f,
+ 0xc0, 2, 0x09, 0x04,
+ 0xc0, 2, 0x0a, 0x00,
+ 0xc0, 2, 0x0b, 0x04,
+ 0xc0, 2, 0xff, 0x00,
+ 0xfd, 1, 100, /* delay 100ms */
+ 0xff, 0, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0} },
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0} },
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "invalid",
+ /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .type = LCD_EXTERN_MAX,
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x20, /* 7bit i2c address */
+ .i2c_addr2 = 0x74, /* 7bit i2c address, 0xff for none */
+ /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_1,
+ .cmd_size = 0xff,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+/***************************************************
+ * lcd_1
+ ***************************************************/
+static char lcd1_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static char lcd1_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_on_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_on_step_mipi[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_off_step_mipi[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd1_config[LCD_NUM_MAX] = {
+ {/* normal*/
+ "lvds_0", LCD_LVDS, 8,
+ /* basic timing */
+ 1366, 768, 1569, 806, 56, 64, 0, 3, 28, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 0, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 2-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 2, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_F, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 1-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_1", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 1, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_F, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {"edp_0", LCD_EDP, 8,
+ /* basic timing */
+ 1920, 1080, 2200, 1120, 44, 148, 0, 5, 30, 0,
+ /* clk_attr */
+ 1, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* edp_attr */
+ 2, 1, 0, 0, 0, 0, 0, 0, 0x5, 0x1,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_F, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/* TL070WSH27*/
+ "mipi_0",LCD_MIPI,8,
+ /* basic timing */
+ 1024, 600, 1250, 630, 80, 100, 0, 5, 20, 0,
+ /* clk_attr */
+ 0, 0, 1, 47250000, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* mipi_attr */
+ 4, 300, 0, 1, 0, 2, 1, 0, Rsv_val, Rsv_val,
+ /* cmd init */
+ mipi_init_on_table_dft, mipi_init_off_table_dft,
+ /* power step */
+ lcd1_power_on_step_mipi, lcd1_power_off_step_mipi,
+ /* backlight */
+ 100, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_NEGATIVE, BL_PWM_F, 180, 100, 25, 1, 1,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd1_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_vbyone_pin", //GPIOY_11/13
+ .pinmux_set = {{0x14, 0x00303000}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x00f0f000}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "lcd_edp_pin", //GPIOY_11
+ .pinmux_set = {{0x14, 0x00004000}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x0000f000}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s lcd1_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", /*GPIOY_8*/
+ .pinmux_set = {{0x14, 0x00000003}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x0000000f}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+/***************************************************
+ * lcd_2
+ ***************************************************/
+static char lcd2_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static char lcd2_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd2_power_on_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd2_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd2_config[LCD_NUM_MAX] = { //only support lvds
+ {/* normal*/
+ "lvds_0", LCD_LVDS, 8,
+ /* basic timing */
+ 1366, 768, 1569, 806, 56, 64, 0, 3, 28, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 0, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd2_power_on_step, lcd2_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/* for HDMI convert*/
+ "lvds_1", LCD_LVDS, 8,
+ /* basic timing */
+ 1920, 1080, 2200, 1125, 44, 148, 0, 5, 36, 0,
+ /* clk_attr */
+ 4, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 1, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd2_power_on_step, lcd2_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_MAX, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd2_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s lcd2_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "invalid",
+ },
+};
+
+/***************************************************
+ * lcd default config
+ ***************************************************/
+static struct lcd_dft_config_s lcd_dft_conf[] = {
+ {//index 0
+ .lcd_gpio = lcd0_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd0_config,
+ .lcd_pinmux = lcd0_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd0_bl_gpio,
+ .bl_pinmux = lcd0_bl_pinmux_ctrl,
+ },
+ {//index 1
+ .lcd_gpio = lcd1_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd1_config,
+ .lcd_pinmux = lcd1_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd1_bl_gpio,
+ .bl_pinmux = lcd1_bl_pinmux_ctrl,
+ },
+ {//index 2
+ .lcd_gpio = lcd2_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd2_config,
+ .lcd_pinmux = lcd2_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd2_bl_gpio,
+ .bl_pinmux = lcd2_bl_pinmux_ctrl,
+ }
+};
+
+void lcd_config_bsp_init(void)
+{
+ struct aml_lcd_data_s *pdata = aml_lcd_get_data();
+
+ if (pdata) {
+ pdata->dft_conf[0] = &lcd_dft_conf[0];
+ pdata->dft_conf[1] = &lcd_dft_conf[1];
+ pdata->dft_conf[2] = &lcd_dft_conf[2];
+ }
+}
diff --git a/board/amlogic/t7_an409_ddr4/t7_an409_ddr4.c b/board/amlogic/t7_an409_ddr4/t7_an409_ddr4.c
new file mode 100644
index 0000000..29a0ed3
--- /dev/null
+++ b/board/amlogic/t7_an409_ddr4/t7_an409_ddr4.c
@@ -0,0 +1,403 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_VOUT
+#include <amlogic/media/vout/aml_vout.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/media/vout/lcd/lcd_vout.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+ aml_set_bootsequence(0);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+#if 0 //bypass below operations for pxp
+ active_clk();
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+#endif
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ /*set vcc5V*/
+ run_command("gpio set GPIOH_1", 0);
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+ run_command("run bcb_cmd", 0);
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+#ifdef CONFIG_AML_VOUT
+ vout_probe();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0xe0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x100000000UL,
+ .phys = 0x100000000UL,
+ .size = 0x120000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xe0000000UL,
+ .phys = 0xe0000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ //printf("\nmach_cpu_init\n");
+#ifdef CONFIG_UPDATE_MMU_TABLE
+ unsigned long nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4;
+ if ( nddrSize <= 0xe0000000 )
+ {
+ bd_mem_map[0].size = nddrSize;
+ bd_mem_map[1].virt = 0;
+ bd_mem_map[1].phys = 0;
+ bd_mem_map[1].size = 0;
+ }
+#endif
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+#endif
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ strcpy(name, "t7_a311d2_an409\0");
+ env_set("aml_dt", "t7_a311d2_an409\0");
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/t7_an40a1/Kconfig b/board/amlogic/t7_an40a1/Kconfig
new file mode 100644
index 0000000..fa54a53
--- /dev/null
+++ b/board/amlogic/t7_an40a1/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_T7_AN40A1
+
+config SYS_SOC
+ default "t7"
+
+config SYS_BOARD
+ default "t7_an40a1"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "t7_an40a1"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+endif
diff --git a/board/amlogic/t7_an40a1/Makefile b/board/amlogic/t7_an40a1/Makefile
new file mode 100644
index 0000000..1e920e7
--- /dev/null
+++ b/board/amlogic/t7_an40a1/Makefile
@@ -0,0 +1,3 @@
+obj-y += $(BOARD).o
+obj-$(CONFIG_AML_LCD) += lcd.o
+
diff --git a/board/amlogic/t7_an40a1/firmware/timing.c b/board/amlogic/t7_an40a1/firmware/timing.c
new file mode 100644
index 0000000..74f4823
--- /dev/null
+++ b/board/amlogic/t7_an40a1/firmware/timing.c
@@ -0,0 +1,959 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+#define ENABLE_LPDDR4X_MODE 1
+
+#define AN_408_DDR0_1G_DDR1_0G 0
+#define AN_408_DDR0_2G_DDR1_0G 1
+#define AN_408_DDR0_1G_DDR1_1G 2
+#define AN_408_DDR0_2G_DDR1_1G 3
+#define AN_408_DDR0_2G_DDR1_2G 4
+#define AN_408_DDR0_2G_DDR1_2G_RANK01 5
+#define AN_408_DDR0_4G_DDR1_4G_RANK01 6
+
+#define DDR_SIZE_TYPE_1 AN_408_DDR0_1G_DDR1_1G //AN_408_DDR0_2G_DDR1_0G//AN_408_DDR0_2G_DDR1_1G//AN_408_DDR0_1G_DDR1_1G
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+#if 0
+ {
+ /* tl1 skt (x309) ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq ={ 1200, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x31f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0x23, 0x13 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x0, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 48, //48, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay ={ 32 + 20, 32 + 20, 32 + 20, 32 + 20, 32, 32 + 0, 32 + 20, 32 + 20, 32 + 20, 32 + 20},
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25),
+ [1] = (12 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 13 << 5 | 14 << 10 | 6 << 15 | 0 << 20 | 0 << 25),
+ },
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 00, 00 },
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC_COPY_CHANNEL_CFG, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux =
+ {
+ 2,
+ 5,
+ 20,
+ 14,
+ 8,
+ 24,
+ 4,
+ 13,
+ 25,
+ 12,
+ 10,
+ 23,
+ 26,
+ 18,
+ 0,
+ 0,
+ 0,
+ 9,
+ 1,
+ 19,
+ 0,
+ 22,
+ 11,
+ 7,
+ 6,
+ 3,
+ 0,
+ 0,
+ },
+ .dfi_pinmux =
+ {
+ 18,
+ 15,
+ 16,
+ 12,
+ 5,
+ 20,
+ 10,
+ 7,
+ 0,
+ 11,
+ 14,
+ 8,
+ 23,
+ 17,
+ 3,
+ 13,
+ 22,
+ 2,
+ 21,
+ 19,
+ 6,
+ 4,
+ 1,
+ 0,
+ 0,
+ 0,
+ },
+ },
+#endif
+#if 1
+ {
+ //.fast_boot[0]=0x000000fd,// 253
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .enable_lpddr4x_mode = ENABLE_LPDDR4X_MODE,
+ .DRAMFreq ={ 2016, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xc8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_4G_DDR1_4G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x131f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0, 0 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x3, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 60,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 240,
+ .soc_clk_slew_rate = 0x1ff,
+ .soc_cs_slew_rate = 0x1ff,
+ .soc_ac_slew_rate = 0x1ff,
+ .soc_data_slew_rate = 0x5ff,
+ .vref_output_permil = 629, //300
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 300,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting=0,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay ={ 32 + 10, 32, 0, 0, 0, 32 + 10, 32, 0, 0, 0},
+ //.ac_trace_delay ={ 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32, 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32 + 0},
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25),
+ [1] = (11 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 12 << 5 | 13 << 10 | 14 << 15 | 0 << 20 | 0 << 25),
+ },
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 7, 1, 5, 0, 2, 3, 4, 6,
+ 8, 15, 12, 13, 9, 10, 11, 14,
+ 22, 18, 21, 20, 17, 23, 16, 19,
+ 29, 30, 28, 31, 24, 27, 26, 25 },
+
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, // DDR_FUNC,
+ //.ddr_func = 0, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux ={ 2, 3, 1, 0, 5, 4, 0, 0, 0, 0,
+ 1, 3, 5, 2, 4, 0, 0, 0, 0 },
+
+ .dfi_pinmux =
+ {
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 0,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 0,
+ 0,
+ 0,
+ },
+ },
+
+ {
+ //.fast_boot[0]=0x000000fd,// 253
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .enable_lpddr4x_mode = ENABLE_LPDDR4X_MODE,
+ .DRAMFreq ={ 2016, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xc8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_4G_DDR1_4G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x131f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0, 0 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x3, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 60,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 240,
+ .soc_clk_slew_rate = 0x1ff,
+ .soc_cs_slew_rate = 0x1ff,
+ .soc_ac_slew_rate = 0x1ff,
+ .soc_data_slew_rate = 0x5ff,
+ .vref_output_permil = 629,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 300,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting=0,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ //.ac_trace_delay ={ 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32, 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32 + 0},
+ .ac_trace_delay ={ 32 + 10, 32, 0, 0, 0, 32 + 10, 32, 0, 0, 0},
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25),
+ [1] = (11 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 12 << 5 | 13 << 10 | 14 << 15 | 0 << 20 | 0 << 25),
+ },
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 4, 6, 5, 0, 7, 1, 2, 3,
+ 15, 11, 13, 14, 12, 9, 8, 10,
+ 21, 19, 22, 16, 18, 17, 23, 20,
+ 29, 30, 26, 25, 24, 27, 31, 28 },
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, // DDR_FUNC,
+ //.ddr_func = 0, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux ={ 2, 3, 1, 0, 5, 4, 0, 0, 0, 0,
+ 1, 3, 5, 2, 4, 0, 0, 0, 0 },
+
+ .dfi_pinmux =
+ {
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 0,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 0,
+ 0,
+ 0,
+ },
+ },
+#endif
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .low_console_baud = CONFIG_LOW_CONSOLE_BAUD,
+};
+
+#define VCCK_A_VAL AML_VCCK_A_INIT_VOLTAGE
+#define VCCK_B_VAL AML_VCCK_B_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK_A uses DCDC PWM table */
+#if (VCCK_A_VAL == 1039)
+#define VCCK_A_VAL_REG 0x00000022
+#elif (VCCK_A_VAL == 1029)
+#define VCCK_A_VAL_REG 0x00010021
+#elif (VCCK_A_VAL == 1019)
+#define VCCK_A_VAL_REG 0x00020020
+#elif (VCCK_A_VAL == 1009)
+#define VCCK_A_VAL_REG 0x0003001f
+#elif (VCCK_A_VAL == 999)
+#define VCCK_A_VAL_REG 0x0004001e
+#elif (VCCK_A_VAL == 989)
+#define VCCK_A_VAL_REG 0x0005001d
+#elif (VCCK_A_VAL == 979)
+#define VCCK_A_VAL_REG 0x0006001c
+#elif (VCCK_A_VAL == 969)
+#define VCCK_A_VAL_REG 0x0007001b
+#elif (VCCK_A_VAL == 959)
+#define VCCK_A_VAL_REG 0x0008001a
+#elif (VCCK_A_VAL == 949)
+#define VCCK_A_VAL_REG 0x00090019
+#elif (VCCK_A_VAL == 939)
+#define VCCK_A_VAL_REG 0x000a0018
+#elif (VCCK_A_VAL == 929)
+#define VCCK_A_VAL_REG 0x000b0017
+#elif (VCCK_A_VAL == 919)
+#define VCCK_A_VAL_REG 0x000c0016
+#elif (VCCK_A_VAL == 909)
+#define VCCK_A_VAL_REG 0x000d0015
+#elif (VCCK_A_VAL == 899)
+#define VCCK_A_VAL_REG 0x000e0014
+#elif (VCCK_A_VAL == 889)
+#define VCCK_A_VAL_REG 0x000f0013
+#elif (VCCK_A_VAL == 879)
+#define VCCK_A_VAL_REG 0x00100012
+#elif (VCCK_A_VAL == 869)
+#define VCCK_A_VAL_REG 0x00110011
+#elif (VCCK_A_VAL == 859)
+#define VCCK_A_VAL_REG 0x00120010
+#elif (VCCK_A_VAL == 849)
+#define VCCK_A_VAL_REG 0x0013000f
+#elif (VCCK_A_VAL == 839)
+#define VCCK_A_VAL_REG 0x0014000e
+#elif (VCCK_A_VAL == 829)
+#define VCCK_A_VAL_REG 0x0015000d
+#elif (VCCK_A_VAL == 819)
+#define VCCK_A_VAL_REG 0x0016000c
+#elif (VCCK_A_VAL == 809)
+#define VCCK_A_VAL_REG 0x0017000b
+#elif (VCCK_A_VAL == 799)
+#define VCCK_A_VAL_REG 0x0018000a
+#elif (VCCK_A_VAL == 789)
+#define VCCK_A_VAL_REG 0x00190009
+#elif (VCCK_A_VAL == 779)
+#define VCCK_A_VAL_REG 0x001a0008
+#elif (VCCK_A_VAL == 769)
+#define VCCK_A_VAL_REG 0x001b0007
+#elif (VCCK_A_VAL == 759)
+#define VCCK_A_VAL_REG 0x001c0006
+#elif (VCCK_A_VAL == 749)
+#define VCCK_A_VAL_REG 0x001d0005
+#elif (VCCK_A_VAL == 739)
+#define VCCK_A_VAL_REG 0x001e0004
+#elif (VCCK_A_VAL == 729)
+#define VCCK_A_VAL_REG 0x001f0003
+#elif (VCCK_A_VAL == 719)
+#define VCCK_A_VAL_REG 0x00200002
+#elif (VCCK_A_VAL == 709)
+#define VCCK_A_VAL_REG 0x00210001
+#elif (VCCK_A_VAL == 699)
+#define VCCK_A_VAL_REG 0x00220000
+#else
+#error "VCCK_A val out of range\n"
+#endif
+
+/* VCCK_B uses PMIC table */
+#if (VCCK_B_VAL == 1040)
+#define VCCK_B_VAL_REG 0x22
+#elif (VCCK_B_VAL == 1030)
+#define VCCK_B_VAL_REG 0x21
+#elif (VCCK_B_VAL == 1020)
+#define VCCK_B_VAL_REG 0x20
+#elif (VCCK_B_VAL == 1010)
+#define VCCK_B_VAL_REG 0x1f
+#elif (VCCK_B_VAL == 1000)
+#define VCCK_B_VAL_REG 0x1e
+#elif (VCCK_B_VAL == 990)
+#define VCCK_B_VAL_REG 0x1d
+#elif (VCCK_B_VAL == 980)
+#define VCCK_B_VAL_REG 0x1c
+#elif (VCCK_B_VAL == 970)
+#define VCCK_B_VAL_REG 0x1b
+#elif (VCCK_B_VAL == 960)
+#define VCCK_B_VAL_REG 0x1a
+#elif (VCCK_B_VAL == 950)
+#define VCCK_B_VAL_REG 0x19
+#elif (VCCK_B_VAL == 940)
+#define VCCK_B_VAL_REG 0x18
+#elif (VCCK_B_VAL == 930)
+#define VCCK_B_VAL_REG 0x17
+#elif (VCCK_B_VAL == 920)
+#define VCCK_B_VAL_REG 0x16
+#elif (VCCK_B_VAL == 910)
+#define VCCK_B_VAL_REG 0x15
+#elif (VCCK_B_VAL == 900)
+#define VCCK_B_VAL_REG 0x14
+#elif (VCCK_B_VAL == 890)
+#define VCCK_B_VAL_REG 0x13
+#elif (VCCK_B_VAL == 880)
+#define VCCK_B_VAL_REG 0x12
+#elif (VCCK_B_VAL == 870)
+#define VCCK_B_VAL_REG 0x11
+#elif (VCCK_B_VAL == 860)
+#define VCCK_B_VAL_REG 0x10
+#elif (VCCK_B_VAL == 850)
+#define VCCK_B_VAL_REG 0xf
+#elif (VCCK_B_VAL == 840)
+#define VCCK_B_VAL_REG 0xe
+#elif (VCCK_B_VAL == 830)
+#define VCCK_B_VAL_REG 0xd
+#elif (VCCK_B_VAL == 820)
+#define VCCK_B_VAL_REG 0xc
+#elif (VCCK_B_VAL == 810)
+#define VCCK_B_VAL_REG 0xb
+#elif (VCCK_B_VAL == 800)
+#define VCCK_B_VAL_REG 0xa
+#elif (VCCK_B_VAL == 790)
+#define VCCK_B_VAL_REG 0x9
+#elif (VCCK_B_VAL == 780)
+#define VCCK_B_VAL_REG 0x8
+#elif (VCCK_B_VAL == 770)
+#define VCCK_B_VAL_REG 0x7
+#elif (VCCK_B_VAL == 760)
+#define VCCK_B_VAL_REG 0x6
+#elif (VCCK_B_VAL == 750)
+#define VCCK_B_VAL_REG 0x5
+#elif (VCCK_B_VAL == 740)
+#define VCCK_B_VAL_REG 0x4
+#elif (VCCK_B_VAL == 730)
+#define VCCK_B_VAL_REG 0x3
+#elif (VCCK_B_VAL == 720)
+#define VCCK_B_VAL_REG 0x2
+#elif (VCCK_B_VAL == 710)
+#define VCCK_B_VAL_REG 0x1
+#elif (VCCK_B_VAL == 700)
+#define VCCK_B_VAL_REG 0x0
+#else
+#error "\nVCCK_B val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 1040)
+#define VDDEE_VAL_REG 0x22
+#elif (VDDEE_VAL == 1030)
+#define VDDEE_VAL_REG 0x21
+#elif (VDDEE_VAL == 1020)
+#define VDDEE_VAL_REG 0x20
+#elif (VDDEE_VAL == 1010)
+#define VDDEE_VAL_REG 0x1f
+#elif (VDDEE_VAL == 1000)
+#define VDDEE_VAL_REG 0x1e
+#elif (VDDEE_VAL == 990)
+#define VDDEE_VAL_REG 0x1d
+#elif (VDDEE_VAL == 980)
+#define VDDEE_VAL_REG 0x1c
+#elif (VDDEE_VAL == 970)
+#define VDDEE_VAL_REG 0x1b
+#elif (VDDEE_VAL == 960)
+#define VDDEE_VAL_REG 0x1a
+#elif (VDDEE_VAL == 950)
+#define VDDEE_VAL_REG 0x19
+#elif (VDDEE_VAL == 940)
+#define VDDEE_VAL_REG 0x18
+#elif (VDDEE_VAL == 930)
+#define VDDEE_VAL_REG 0x17
+#elif (VDDEE_VAL == 920)
+#define VDDEE_VAL_REG 0x16
+#elif (VDDEE_VAL == 910)
+#define VDDEE_VAL_REG 0x15
+#elif (VDDEE_VAL == 900)
+#define VDDEE_VAL_REG 0x14
+#elif (VDDEE_VAL == 890)
+#define VDDEE_VAL_REG 0x13
+#elif (VDDEE_VAL == 880)
+#define VDDEE_VAL_REG 0x12
+#elif (VDDEE_VAL == 870)
+#define VDDEE_VAL_REG 0x11
+#elif (VDDEE_VAL == 860)
+#define VDDEE_VAL_REG 0x10
+#elif (VDDEE_VAL == 850)
+#define VDDEE_VAL_REG 0xf
+#elif (VDDEE_VAL == 840)
+#define VDDEE_VAL_REG 0xe
+#elif (VDDEE_VAL == 830)
+#define VDDEE_VAL_REG 0xd
+#elif (VDDEE_VAL == 820)
+#define VDDEE_VAL_REG 0xc
+#elif (VDDEE_VAL == 810)
+#define VDDEE_VAL_REG 0xb
+#elif (VDDEE_VAL == 800)
+#define VDDEE_VAL_REG 0xa
+#elif (VDDEE_VAL == 790)
+#define VDDEE_VAL_REG 0x9
+#elif (VDDEE_VAL == 780)
+#define VDDEE_VAL_REG 0x8
+#elif (VDDEE_VAL == 770)
+#define VDDEE_VAL_REG 0x7
+#elif (VDDEE_VAL == 760)
+#define VDDEE_VAL_REG 0x6
+#elif (VDDEE_VAL == 750)
+#define VDDEE_VAL_REG 0x5
+#elif (VDDEE_VAL == 740)
+#define VDDEE_VAL_REG 0x4
+#elif (VDDEE_VAL == 730)
+#define VDDEE_VAL_REG 0x3
+#elif (VDDEE_VAL == 720)
+#define VDDEE_VAL_REG 0x2
+#elif (VDDEE_VAL == 710)
+#define VDDEE_VAL_REG 0x1
+#elif (VDDEE_VAL == 700)
+#define VDDEE_VAL_REG 0x0
+#else
+#error "\nVDDEE val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ { 0, 0, 0xffffffff, 0, 0, 0 },
+};
+
+#define I2C_BUS 0x2
+#define I2C_AO_A 6 /*from bl2 i2c meson_i2c.h*/
+#define I2C_DEV_ADDR 0x4b
+#define BD71837_REG_BUCK2_CTRL 0x06
+#define BD71837_REG_BUCK3_CTRL 0x07
+#define BD71837_REG_BUCK2_VOLT_RUN 0x10
+#define BD71837_REG_BUCK3_VOLT_RUN 0x12
+#define BD71837_REG_REGLOCK 0x2f
+#define BD71837_REG_MUXSW_EN 0x30
+
+/* pmu/gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+ /* set TEST_N to high */
+ {PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0},
+ {PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0},
+
+ /* config vcck a pwm - pwmao_d */
+ {PWM_AO_CD_PWM_B, VCCK_A_VAL_REG, 0xffffffff, 0, 0, 0},
+ {PWM_AO_CD_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0},
+ {CLKCTRL_PWM_CLK_AO_CD_CTRL, (0x1 << 24), (0x7FF << 16), 0, 0, 0},
+
+ /* enable pwmao_d, Wait for pmic to enable VCCK A */
+ /* set gpioe_3 ds to max */
+ {PADCTRL_GPIOE_DS, (0x3 << 6), (0x3 << 6), 0, 0, 0},
+ /* mux gpioe_3 to pwmao_d */
+ {PADCTRL_PIN_MUX_REGC, (0x1 << 12), (0xf << 12), 0, 0, 0},
+
+
+ /* pull low gpioy_5 make tp rst low*/
+ {PADCTRL_PIN_MUX_REGA, (0 << 20), (0xf << 20), 0, 0, 0},
+ {PADCTRL_GPIOY_O, (0 << 5), (1 << 5), 0, 0, 0},
+ {PADCTRL_GPIOY_OEN, (0 << 5), (1 << 5), 0, 0, 0},
+
+ /* disable tp int bias */
+ {PADCTRL_GPIOM_PULL_EN, (0 << 5), (1 << 5), 0, 0, 0},
+
+ /*set pinmux GPIOD_2(I2CM_AO_A_SCL) and GPIOD_3(I2CM_AO_A_SDA) for pmic*/
+ {PADCTRL_GPIOD_DS, (0xf << 4), (0xf << 4), 0, 0, 0},
+ {PADCTRL_GPIOD_PULL_EN, (0x3 << 2), (0x3 << 2), 0, 0, 0},
+ {PADCTRL_GPIOD_PULL_UP, (0x3 << 2), (0x3 << 2), 0, 0, 0},
+ {PADCTRL_PIN_MUX_REGA, (0x11 << 8), (0xff << 8), 0, 0, 0},
+ {BD71837_REG_REGLOCK, 1, (1 << 4), 0, (I2C_BUS << 4) | (I2C_AO_A), I2C_DEV_ADDR},
+ /*set vddee voltage*/
+ {BD71837_REG_BUCK2_VOLT_RUN, VDDEE_VAL_REG, 0x3f, 0, \
+ (I2C_BUS << 4) | (I2C_AO_A), I2C_DEV_ADDR},
+ /*set vddcpub voltage*/
+ {BD71837_REG_BUCK3_VOLT_RUN, VCCK_B_VAL_REG, 0x3f, 0, \
+ (I2C_BUS << 4) | (I2C_AO_A), I2C_DEV_ADDR},
+ {BD71837_REG_MUXSW_EN, 1, 1, 0, \
+ (I2C_BUS << 4) | (I2C_AO_A), I2C_DEV_ADDR},
+
+ /* make watchdog send reset signal, !!Please dont't copy below to other board
+ * which have no pmic or reset will not work
+ */
+ {PADCTRL_PIN_MUX_REGB, (0x1 << 16), (0xf << 16), 0, 0, 0},
+ {RESETCTRL_WATCHDOG_CTRL1, (0x3ffff << 0), (0x3ffff << 0), 0, 0, 0},
+ {RESETCTRL_SEC_WATCHDOG_CTRL1, (0x3ffff << 0), (0x3ffff << 0), 0, 0, 0},
+ {PADCTRL_WD_RSTO_CTRL, (1 << 0), (1 << 0), 0, 0, 0},
+};
+
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common = {
+ .version = 0x01,
+ .device_fip_container_size = 0x280000,
+ .device_fip_container_copies = 4,
+ },
+ .nand ={
+ .version = 0x01,
+ .bbt_pages = 0x1,
+ .bbt_start_block = 0x20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (4 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 128,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/t7_an40a1/fw_arb.cfg b/board/amlogic/t7_an40a1/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/t7_an40a1/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/t7_an40a1/lcd.c b/board/amlogic/t7_an40a1/lcd.c
new file mode 100644
index 0000000..d0707d9
--- /dev/null
+++ b/board/amlogic/t7_an40a1/lcd.c
@@ -0,0 +1,536 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+
+/***************************************************
+ * lcd_0
+ ***************************************************/
+static char lcd0_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static char lcd0_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_on_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_off_step[] = {
+ {LCD_POWER_TYPE_CPU, 0, 0, 200,}, /* panel vcc */
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_on_step_mipi[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_off_step_mipi[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static unsigned char mipi_init_on_table_dft[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xfd, 1, 100,
+ 0x05, 1, 0x29,
+ 0xfd, 1, 20,
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table_dft[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xfd, 1, 100,
+ 0x05, 1, 0x10,
+ 0xfd, 1, 10,
+ 0xff, 0, //ending
+};
+
+struct ext_lcd_config_s ext_lcd0_config[LCD_NUM_MAX] = {
+ {/* normal*/
+ "lvds_0", LCD_LVDS, 8,
+ /* basic timing */
+ 1366, 768, 1569, 806, 56, 64, 0, 3, 28, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 0, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 2-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 2, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 1-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_1", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 1, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {"edp_0", LCD_EDP, 8,
+ /* basic timing */
+ 1920, 1080, 2200, 1120, 44, 148, 0, 5, 30, 0,
+ /* clk_attr */
+ 1, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* edp_attr */
+ 2, 1, 0, 0, 0, 0, 0, 0, 0x5, 0x1,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/* TL070WSH27*/
+ "mipi_0",LCD_MIPI,8,
+ /* basic timing */
+ 1024, 600, 1250, 630, 80, 100, 0, 5, 20, 0,
+ /* clk_attr */
+ 0, 0, 1, 47250000, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* mipi_attr */
+ 4, 300, 0, 1, 0, 2, 1, 0, Rsv_val, Rsv_val,
+ /* cmd init */
+ mipi_init_on_table_dft, mipi_init_off_table_dft,
+ /* power step */
+ lcd0_power_on_step_mipi, lcd0_power_off_step_mipi,
+ /* backlight */
+ 100, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_NEGATIVE, BL_PWM_E, 180, 100, 25, 1, 1,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd0_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_vbyone_pin", //GPIOY_10/12
+ .pinmux_set = {{0x14, 0x00030300}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x000f0f00}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "lcd_edp_pin", //GPIOY_10
+ .pinmux_set = {{0x14, 0x00000400}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x00000f00}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s lcd0_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", /*GPIOY_1*/
+ .pinmux_set = {{0x13, 0x00000030}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x13, 0x000000f0}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xc0, 2, 0x01, 0x2b,
+ 0xc0, 2, 0x02, 0x05,
+ 0xc0, 2, 0x03, 0x00,
+ 0xc0, 2, 0x04, 0x00,
+ 0xc0, 2, 0x05, 0x0c,
+ 0xc0, 2, 0x06, 0x04,
+ 0xc0, 2, 0x07, 0x21,
+ 0xc0, 2, 0x08, 0x0f,
+ 0xc0, 2, 0x09, 0x04,
+ 0xc0, 2, 0x0a, 0x00,
+ 0xc0, 2, 0x0b, 0x04,
+ 0xc0, 2, 0xff, 0x00,
+ 0xfd, 1, 100, /* delay 100ms */
+ 0xff, 0, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0} },
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0} },
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "invalid",
+ /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .type = LCD_EXTERN_MAX,
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x20, /* 7bit i2c address */
+ .i2c_addr2 = 0x74, /* 7bit i2c address, 0xff for none */
+ /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_1,
+ .cmd_size = 0xff,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+/***************************************************
+ * lcd_1
+ ***************************************************/
+static char lcd1_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static char lcd1_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_on_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_on_step_mipi[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_off_step_mipi[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd1_config[LCD_NUM_MAX] = {
+ {/* normal*/
+ "lvds_0", LCD_LVDS, 8,
+ /* basic timing */
+ 1366, 768, 1569, 806, 56, 64, 0, 3, 28, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 0, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 2-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 2, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_F, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 1-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_1", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 1, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_F, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {"edp_0", LCD_EDP, 8,
+ /* basic timing */
+ 1920, 1080, 2200, 1120, 44, 148, 0, 5, 30, 0,
+ /* clk_attr */
+ 1, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* edp_attr */
+ 2, 1, 0, 0, 0, 0, 0, 0, 0x5, 0x1,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_F, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/* TL070WSH27*/
+ "mipi_0",LCD_MIPI,8,
+ /* basic timing */
+ 1024, 600, 1250, 630, 80, 100, 0, 5, 20, 0,
+ /* clk_attr */
+ 0, 0, 1, 47250000, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* mipi_attr */
+ 4, 300, 0, 1, 0, 2, 1, 0, Rsv_val, Rsv_val,
+ /* cmd init */
+ mipi_init_on_table_dft, mipi_init_off_table_dft,
+ /* power step */
+ lcd1_power_on_step_mipi, lcd1_power_off_step_mipi,
+ /* backlight */
+ 100, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_NEGATIVE, BL_PWM_F, 180, 100, 25, 1, 1,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd1_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_vbyone_pin", //GPIOY_11/13
+ .pinmux_set = {{0x14, 0x00303000}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x00f0f000}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "lcd_edp_pin", //GPIOY_11
+ .pinmux_set = {{0x14, 0x00004000}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x0000f000}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s lcd1_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", /*GPIOY_8*/
+ .pinmux_set = {{0x14, 0x00000003}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x0000000f}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+/***************************************************
+ * lcd_2
+ ***************************************************/
+static char lcd2_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static char lcd2_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd2_power_on_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd2_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd2_config[LCD_NUM_MAX] = { //only support lvds
+ {/* normal*/
+ "lvds_0", LCD_LVDS, 8,
+ /* basic timing */
+ 1366, 768, 1569, 806, 56, 64, 0, 3, 28, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 0, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd2_power_on_step, lcd2_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/* for HDMI convert*/
+ "lvds_1", LCD_LVDS, 8,
+ /* basic timing */
+ 1920, 1080, 2200, 1125, 44, 148, 0, 5, 36, 0,
+ /* clk_attr */
+ 4, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 1, 0, 0, 0, 0xf, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd2_power_on_step, lcd2_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_MAX, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd2_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s lcd2_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "invalid",
+ },
+};
+
+/***************************************************
+ * lcd default config
+ ***************************************************/
+static struct lcd_dft_config_s lcd_dft_conf[] = {
+ {//index 0
+ .lcd_gpio = lcd0_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd0_config,
+ .lcd_pinmux = lcd0_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd0_bl_gpio,
+ .bl_pinmux = lcd0_bl_pinmux_ctrl,
+ },
+ {//index 1
+ .lcd_gpio = lcd1_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd1_config,
+ .lcd_pinmux = lcd1_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd1_bl_gpio,
+ .bl_pinmux = lcd1_bl_pinmux_ctrl,
+ },
+ {//index 2
+ .lcd_gpio = lcd2_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd2_config,
+ .lcd_pinmux = lcd2_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd2_bl_gpio,
+ .bl_pinmux = lcd2_bl_pinmux_ctrl,
+ }
+};
+
+void lcd_config_bsp_init(void)
+{
+ struct aml_lcd_data_s *pdata = aml_lcd_get_data();
+
+ if (pdata) {
+ pdata->dft_conf[0] = &lcd_dft_conf[0];
+ pdata->dft_conf[1] = &lcd_dft_conf[1];
+ pdata->dft_conf[2] = &lcd_dft_conf[2];
+ }
+}
diff --git a/board/amlogic/t7_an40a1/t7_an40a1.c b/board/amlogic/t7_an40a1/t7_an40a1.c
new file mode 100644
index 0000000..1cf12e3
--- /dev/null
+++ b/board/amlogic/t7_an40a1/t7_an40a1.c
@@ -0,0 +1,404 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_VOUT
+#include <amlogic/media/vout/aml_vout.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/media/vout/lcd/lcd_vout.h>
+#endif
+#include <asm/arch/pmic_bd71837.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+ pmic_bd71837_init();
+
+ aml_set_bootsequence(0);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+#if 0
+ active_clk();
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+#endif
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+ run_command("run bcb_cmd", 0);
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+#ifdef CONFIG_AML_VOUT
+ vout_probe();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0xe0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x100000000UL,
+ .phys = 0x100000000UL,
+ .size = 0x120000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xe0000000UL,
+ .phys = 0xe0000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ //printf("\nmach_cpu_init\n");
+#ifdef CONFIG_UPDATE_MMU_TABLE
+ unsigned long nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4;
+ if ( nddrSize <= 0xe0000000 )
+ {
+ bd_mem_map[0].size = nddrSize;
+ bd_mem_map[1].virt = 0;
+ bd_mem_map[1].phys = 0;
+ bd_mem_map[1].size = 0;
+ }
+#endif
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+#endif
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ strcpy(name, "t7_pop1_an40a1\0");
+ env_set("aml_dt", "t7_pop1_an40a1\0");
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/t7_skt/Kconfig b/board/amlogic/t7_skt/Kconfig
new file mode 100644
index 0000000..6938962
--- /dev/null
+++ b/board/amlogic/t7_skt/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_T7_SKT
+
+config SYS_SOC
+ default "t7"
+
+config SYS_BOARD
+ default "t7_skt"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "t7_skt"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+endif
diff --git a/board/amlogic/t7_skt/Makefile b/board/amlogic/t7_skt/Makefile
new file mode 100644
index 0000000..1e920e7
--- /dev/null
+++ b/board/amlogic/t7_skt/Makefile
@@ -0,0 +1,3 @@
+obj-y += $(BOARD).o
+obj-$(CONFIG_AML_LCD) += lcd.o
+
diff --git a/board/amlogic/t7_skt/aml-key/bl2aesiv b/board/amlogic/t7_skt/aml-key/bl2aesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/t7_skt/aml-key/bl2aesiv
Binary files differ
diff --git a/board/amlogic/t7_skt/aml-key/bl2aeskey b/board/amlogic/t7_skt/aml-key/bl2aeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/t7_skt/aml-key/bl2aeskey
Binary files differ
diff --git a/board/amlogic/t7_skt/aml-key/bl3xaesiv b/board/amlogic/t7_skt/aml-key/bl3xaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/t7_skt/aml-key/bl3xaesiv
Binary files differ
diff --git a/board/amlogic/t7_skt/aml-key/bl3xaeskey b/board/amlogic/t7_skt/aml-key/bl3xaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/t7_skt/aml-key/bl3xaeskey
Binary files differ
diff --git a/board/amlogic/t7_skt/aml-key/kernelaesiv b/board/amlogic/t7_skt/aml-key/kernelaesiv
new file mode 100644
index 0000000..01d633b
--- /dev/null
+++ b/board/amlogic/t7_skt/aml-key/kernelaesiv
Binary files differ
diff --git a/board/amlogic/t7_skt/aml-key/kernelaeskey b/board/amlogic/t7_skt/aml-key/kernelaeskey
new file mode 100644
index 0000000..91c9e46
--- /dev/null
+++ b/board/amlogic/t7_skt/aml-key/kernelaeskey
Binary files differ
diff --git a/board/amlogic/t7_skt/aml-user-key.sig b/board/amlogic/t7_skt/aml-user-key.sig
new file mode 100644
index 0000000..0f89a75
--- /dev/null
+++ b/board/amlogic/t7_skt/aml-user-key.sig
Binary files differ
diff --git a/board/amlogic/t7_skt/firmware/timing.c b/board/amlogic/t7_skt/firmware/timing.c
new file mode 100644
index 0000000..2dd3b82
--- /dev/null
+++ b/board/amlogic/t7_skt/firmware/timing.c
@@ -0,0 +1,809 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+#define ENABLE_LPDDR4X_MODE 1
+
+#define AN_408_DDR0_1G_DDR1_0G 0
+#define AN_408_DDR0_2G_DDR1_0G 1
+#define AN_408_DDR0_1G_DDR1_1G 2
+#define AN_408_DDR0_2G_DDR1_1G 3
+#define AN_408_DDR0_2G_DDR1_2G 4
+#define AN_408_DDR0_2G_DDR1_2G_RANK01 5
+#define AN_408_DDR0_4G_DDR1_4G_RANK01 6
+
+#define DDR_SIZE_TYPE_1 AN_408_DDR0_1G_DDR1_1G //AN_408_DDR0_2G_DDR1_0G//AN_408_DDR0_2G_DDR1_1G//AN_408_DDR0_1G_DDR1_1G
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+#if 0
+ {
+ /* tl1 skt (x309) ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq ={ 1200, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x31f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0x23, 0x13 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x0, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 48, //48, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay ={ 32 + 20, 32 + 20, 32 + 20, 32 + 20, 32, 32 + 0, 32 + 20, 32 + 20, 32 + 20, 32 + 20},
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25),
+ [1] = (12 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 13 << 5 | 14 << 10 | 6 << 15 | 0 << 20 | 0 << 25),
+ },
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 00, 00 },
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC_COPY_CHANNEL_CFG, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux =
+ {
+ 2,
+ 5,
+ 20,
+ 14,
+ 8,
+ 24,
+ 4,
+ 13,
+ 25,
+ 12,
+ 10,
+ 23,
+ 26,
+ 18,
+ 0,
+ 0,
+ 0,
+ 9,
+ 1,
+ 19,
+ 0,
+ 22,
+ 11,
+ 7,
+ 6,
+ 3,
+ 0,
+ 0,
+ },
+ .dfi_pinmux =
+ {
+ 18,
+ 15,
+ 16,
+ 12,
+ 5,
+ 20,
+ 10,
+ 7,
+ 0,
+ 11,
+ 14,
+ 8,
+ 23,
+ 17,
+ 3,
+ 13,
+ 22,
+ 2,
+ 21,
+ 19,
+ 6,
+ 4,
+ 1,
+ 0,
+ 0,
+ 0,
+ },
+ },
+#endif
+#if 1
+ {
+ //.fast_boot[0]=0x000000fd,// 253
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .enable_lpddr4x_mode = ENABLE_LPDDR4X_MODE,
+ .DRAMFreq ={ 2016, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xc8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_4G_DDR1_4G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x131f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0, 0 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x3, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 60,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 240,
+ .soc_clk_slew_rate = 0x1ff,
+ .soc_cs_slew_rate = 0x1ff,
+ .soc_ac_slew_rate = 0x1ff,
+ .soc_data_slew_rate = 0x5ff,
+ .vref_output_permil = 629, //300
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 300,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting=0,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay ={ 32 + 10, 32, 0, 0, 0, 32 + 10, 32, 0, 0, 0},
+ //.ac_trace_delay ={ 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32, 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32 + 0},
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25),
+ [1] = (11 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 12 << 5 | 13 << 10 | 14 << 15 | 0 << 20 | 0 << 25),
+ },
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 7, 1, 5, 0, 2, 3, 4, 6,
+ 8, 15, 12, 13, 9, 10, 11, 14,
+ 22, 18, 21, 20, 17, 23, 16, 19,
+ 29, 30, 28, 31, 24, 27, 26, 25 },
+
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, // DDR_FUNC,
+ //.ddr_func = 0, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux ={ 2, 3, 1, 0, 5, 4, 0, 0, 0, 0,
+ 1, 3, 5, 2, 4, 0, 0, 0, 0 },
+
+ .dfi_pinmux =
+ {
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 0,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 0,
+ 0,
+ 0,
+ },
+ },
+
+ {
+ //.fast_boot[0]=0x000000fd,// 253
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .enable_lpddr4x_mode = ENABLE_LPDDR4X_MODE,
+ .DRAMFreq ={ 2016, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xc8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_4G_DDR1_4G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x131f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0, 0 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x3, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 60,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 240,
+ .soc_clk_slew_rate = 0x1ff,
+ .soc_cs_slew_rate = 0x1ff,
+ .soc_ac_slew_rate = 0x1ff,
+ .soc_data_slew_rate = 0x5ff,
+ .vref_output_permil = 629,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 300,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting=0,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ //.ac_trace_delay ={ 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32, 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32 + 0},
+ .ac_trace_delay ={ 32 + 10, 32, 0, 0, 0, 32 + 10, 32, 0, 0, 0},
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25),
+ [1] = (11 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 12 << 5 | 13 << 10 | 14 << 15 | 0 << 20 | 0 << 25),
+ },
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 4, 6, 5, 0, 7, 1, 2, 3,
+ 15, 11, 13, 14, 12, 9, 8, 10,
+ 21, 19, 22, 16, 18, 17, 23, 20,
+ 29, 30, 26, 25, 24, 27, 31, 28 },
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, // DDR_FUNC,
+ //.ddr_func = 0, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux ={ 2, 3, 1, 0, 5, 4, 0, 0, 0, 0,
+ 1, 3, 5, 2, 4, 0, 0, 0, 0 },
+
+ .dfi_pinmux =
+ {
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 0,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 0,
+ 0,
+ 0,
+ },
+ },
+#endif
+};
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .low_console_baud = CONFIG_LOW_CONSOLE_BAUD,
+};
+
+
+#define VCCK_VAL AML_VCCK_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK PWM table */
+#if (VCCK_VAL == 1039)
+#define VCCK_VAL_REG 0x00000022
+#elif (VCCK_VAL == 1029)
+#define VCCK_VAL_REG 0x00010021
+#elif (VCCK_VAL == 1019)
+#define VCCK_VAL_REG 0x00020020
+#elif (VCCK_VAL == 1009)
+#define VCCK_VAL_REG 0x0003001f
+#elif (VCCK_VAL == 999)
+#define VCCK_VAL_REG 0x0004001e
+#elif (VCCK_VAL == 989)
+#define VCCK_VAL_REG 0x0005001d
+#elif (VCCK_VAL == 979)
+#define VCCK_VAL_REG 0x0006001c
+#elif (VCCK_VAL == 969)
+#define VCCK_VAL_REG 0x0007001b
+#elif (VCCK_VAL == 959)
+#define VCCK_VAL_REG 0x0008001a
+#elif (VCCK_VAL == 949)
+#define VCCK_VAL_REG 0x00090019
+#elif (VCCK_VAL == 939)
+#define VCCK_VAL_REG 0x000a0018
+#elif (VCCK_VAL == 929)
+#define VCCK_VAL_REG 0x000b0017
+#elif (VCCK_VAL == 919)
+#define VCCK_VAL_REG 0x000c0016
+#elif (VCCK_VAL == 909)
+#define VCCK_VAL_REG 0x000d0015
+#elif (VCCK_VAL == 899)
+#define VCCK_VAL_REG 0x000e0014
+#elif (VCCK_VAL == 889)
+#define VCCK_VAL_REG 0x000f0013
+#elif (VCCK_VAL == 879)
+#define VCCK_VAL_REG 0x00100012
+#elif (VCCK_VAL == 869)
+#define VCCK_VAL_REG 0x00110011
+#elif (VCCK_VAL == 859)
+#define VCCK_VAL_REG 0x00120010
+#elif (VCCK_VAL == 849)
+#define VCCK_VAL_REG 0x0013000f
+#elif (VCCK_VAL == 839)
+#define VCCK_VAL_REG 0x0014000e
+#elif (VCCK_VAL == 829)
+#define VCCK_VAL_REG 0x0015000d
+#elif (VCCK_VAL == 819)
+#define VCCK_VAL_REG 0x0016000c
+#elif (VCCK_VAL == 809)
+#define VCCK_VAL_REG 0x0017000b
+#elif (VCCK_VAL == 799)
+#define VCCK_VAL_REG 0x0018000a
+#elif (VCCK_VAL == 789)
+#define VCCK_VAL_REG 0x00190009
+#elif (VCCK_VAL == 779)
+#define VCCK_VAL_REG 0x001a0008
+#elif (VCCK_VAL == 769)
+#define VCCK_VAL_REG 0x001b0007
+#elif (VCCK_VAL == 759)
+#define VCCK_VAL_REG 0x001c0006
+#elif (VCCK_VAL == 749)
+#define VCCK_VAL_REG 0x001d0005
+#elif (VCCK_VAL == 739)
+#define VCCK_VAL_REG 0x001e0004
+#elif (VCCK_VAL == 729)
+#define VCCK_VAL_REG 0x001f0003
+#elif (VCCK_VAL == 719)
+#define VCCK_VAL_REG 0x00200002
+#elif (VCCK_VAL == 709)
+#define VCCK_VAL_REG 0x00210001
+#elif (VCCK_VAL == 699)
+#define VCCK_VAL_REG 0x00220000
+#else
+#error "VCCK val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 700)
+#define VDDEE_VAL_REG 0x120000
+#elif (VDDEE_VAL == 710)
+#define VDDEE_VAL_REG 0x110001
+#elif (VDDEE_VAL == 720)
+#define VDDEE_VAL_REG 0x100002
+#elif (VDDEE_VAL == 730)
+#define VDDEE_VAL_REG 0xf0003
+#elif (VDDEE_VAL == 740)
+#define VDDEE_VAL_REG 0xe0004
+#elif (VDDEE_VAL == 750)
+#define VDDEE_VAL_REG 0xd0005
+#elif (VDDEE_VAL == 760)
+#define VDDEE_VAL_REG 0xc0006
+#elif (VDDEE_VAL == 770)
+#define VDDEE_VAL_REG 0xb0007
+#elif (VDDEE_VAL == 780)
+#define VDDEE_VAL_REG 0xa0008
+#elif (VDDEE_VAL == 790)
+#define VDDEE_VAL_REG 0x90009
+#elif (VDDEE_VAL == 800)
+#define VDDEE_VAL_REG 0x8000a
+#elif (VDDEE_VAL == 810)
+#define VDDEE_VAL_REG 0x7000b
+#elif (VDDEE_VAL == 820)
+#define VDDEE_VAL_REG 0x6000c
+#elif (VDDEE_VAL == 830)
+#define VDDEE_VAL_REG 0x5000d
+#elif (VDDEE_VAL == 840)
+#define VDDEE_VAL_REG 0x4000e
+#elif (VDDEE_VAL == 850)
+#define VDDEE_VAL_REG 0x3000f
+#elif (VDDEE_VAL == 860)
+#define VDDEE_VAL_REG 0x20010
+#elif (VDDEE_VAL == 870)
+#define VDDEE_VAL_REG 0x10011
+#elif (VDDEE_VAL == 880)
+#define VDDEE_VAL_REG 0x12
+#else
+#error "VDDEE val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ { 0, 0, 0xffffffff, 0, 0, 0 },
+};
+
+/* gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+ /* demo, user defined override register */
+
+ /* enable vddcpu dc-dc, set TEST_N to high */
+ { PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
+ { PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0 },
+
+ /* set pwm h and pwm j clock rate to 24M, enable them */
+
+ /* set GPIOE_0 GPIOE_1 drive strength to 3 */
+ { PADCTRL_GPIOE_DS, 0xf, 0xf, 0, 0, 0 },
+ /* set GPIOE_0 GPIOE_1 mux to pwmh pwmj */
+ { PADCTRL_PIN_MUX_REGI, (0x3 << 0), (0xf << 0), 0, 0, 0 },
+ { PADCTRL_PIN_MUX_REGI, (0x3 << 4), (0xf << 4), 0, 0, 0 },
+};
+
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common ={
+ .version = 0x01,
+ .device_fip_container_size = 0x280000,
+ .device_fip_container_copies = 4,
+ },
+ .nand ={
+ .version = 0x01,
+ .bbt_pages = 0x1,
+ .bbt_start_block = 0x20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (4 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 128,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/t7_skt/fw_arb.cfg b/board/amlogic/t7_skt/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/t7_skt/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/t7_skt/lcd.c b/board/amlogic/t7_skt/lcd.c
new file mode 100644
index 0000000..7452887
--- /dev/null
+++ b/board/amlogic/t7_skt/lcd.c
@@ -0,0 +1,536 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+
+/***************************************************
+ * lcd_0
+ ***************************************************/
+static char lcd0_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static char lcd0_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_on_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_off_step[] = {
+ {LCD_POWER_TYPE_CPU, 0, 0, 200,}, /* panel vcc */
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_on_step_mipi[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_off_step_mipi[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static unsigned char mipi_init_on_table_dft[DSI_INIT_ON_MAX] = {//table size < 100
+ 0x05, 1, 0x11,
+ 0xfd, 1, 100,
+ 0x05, 1, 0x29,
+ 0xfd, 1, 20,
+ 0xff, 0, //ending
+};
+static unsigned char mipi_init_off_table_dft[DSI_INIT_OFF_MAX] = {//table size < 50
+ 0x05, 1, 0x28,
+ 0xfd, 1, 100,
+ 0x05, 1, 0x10,
+ 0xfd, 1, 10,
+ 0xff, 0, //ending
+};
+
+struct ext_lcd_config_s ext_lcd0_config[LCD_NUM_MAX] = {
+ {/* normal*/
+ "lvds_0", LCD_LVDS, 8,
+ /* basic timing */
+ 1366, 768, 1569, 806, 56, 64, 0, 3, 28, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 0, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 2-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 2, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 1-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_1", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 1, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {"edp_0", LCD_EDP, 8,
+ /* basic timing */
+ 1920, 1080, 2200, 1120, 44, 148, 0, 5, 30, 0,
+ /* clk_attr */
+ 1, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* edp_attr */
+ 2, 1, 0, 0, 0, 0, 0, 0, 0x5, 0x1,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/* TL070WSH27*/
+ "mipi_0",LCD_MIPI,8,
+ /* basic timing */
+ 1024, 600, 1250, 630, 80, 100, 0, 5, 20, 0,
+ /* clk_attr */
+ 0, 0, 1, 47250000, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* mipi_attr */
+ 4, 300, 0, 1, 0, 2, 1, 0, Rsv_val, Rsv_val,
+ /* cmd init */
+ mipi_init_on_table_dft, mipi_init_off_table_dft,
+ /* power step */
+ lcd0_power_on_step_mipi, lcd0_power_off_step_mipi,
+ /* backlight */
+ 100, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_NEGATIVE, BL_PWM_E, 180, 100, 25, 1, 1,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd0_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_vbyone_pin", //GPIOY_10/12
+ .pinmux_set = {{0x14, 0x00030300}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x000f0f00}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "lcd_edp_pin", //GPIOY_10
+ .pinmux_set = {{0x14, 0x00000400}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x00000f00}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s lcd0_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", /*GPIOY_1*/
+ .pinmux_set = {{0x13, 0x00000030}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x13, 0x000000f0}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xc0, 2, 0x01, 0x2b,
+ 0xc0, 2, 0x02, 0x05,
+ 0xc0, 2, 0x03, 0x00,
+ 0xc0, 2, 0x04, 0x00,
+ 0xc0, 2, 0x05, 0x0c,
+ 0xc0, 2, 0x06, 0x04,
+ 0xc0, 2, 0x07, 0x21,
+ 0xc0, 2, 0x08, 0x0f,
+ 0xc0, 2, 0x09, 0x04,
+ 0xc0, 2, 0x0a, 0x00,
+ 0xc0, 2, 0x0b, 0x04,
+ 0xc0, 2, 0xff, 0x00,
+ 0xfd, 1, 100, /* delay 100ms */
+ 0xff, 0, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0} },
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0} },
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "invalid",
+ /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .type = LCD_EXTERN_MAX,
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x20, /* 7bit i2c address */
+ .i2c_addr2 = 0x74, /* 7bit i2c address, 0xff for none */
+ /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_1,
+ .cmd_size = 0xff,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+/***************************************************
+ * lcd_1
+ ***************************************************/
+static char lcd1_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static char lcd1_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_on_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_on_step_mipi[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd1_power_off_step_mipi[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd1_config[LCD_NUM_MAX] = {
+ {/* normal*/
+ "lvds_0", LCD_LVDS, 8,
+ /* basic timing */
+ 1366, 768, 1569, 806, 56, 64, 0, 3, 28, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 0, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 2-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_0", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 2, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_F, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/*public 1-region vx1 : 3840x2160@60hz 8lane */
+ "vbyone_1", LCD_VBYONE, 10,
+ /* basic timing */
+ 3840, 2160, 4400, 2250, 33, 477, 0, 6, 81, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* vbyone_attr */
+ 8, 1, 4, 4, 0x7, 0x1, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_F, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {"edp_0", LCD_EDP, 8,
+ /* basic timing */
+ 1920, 1080, 2200, 1120, 44, 148, 0, 5, 30, 0,
+ /* clk_attr */
+ 1, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* edp_attr */
+ 2, 1, 0, 0, 0, 0, 0, 0, 0x5, 0x1,
+ NULL, NULL,
+ /* power step */
+ lcd1_power_on_step, lcd1_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_F, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/* TL070WSH27*/
+ "mipi_0",LCD_MIPI,8,
+ /* basic timing */
+ 1024, 600, 1250, 630, 80, 100, 0, 5, 20, 0,
+ /* clk_attr */
+ 0, 0, 1, 47250000, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* mipi_attr */
+ 4, 300, 0, 1, 0, 2, 1, 0, Rsv_val, Rsv_val,
+ /* cmd init */
+ mipi_init_on_table_dft, mipi_init_off_table_dft,
+ /* power step */
+ lcd1_power_on_step_mipi, lcd1_power_off_step_mipi,
+ /* backlight */
+ 100, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_NEGATIVE, BL_PWM_F, 180, 100, 25, 1, 1,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd1_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_vbyone_pin", //GPIOY_11/13
+ .pinmux_set = {{0x14, 0x00303000}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x00f0f000}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "lcd_edp_pin", //GPIOY_11
+ .pinmux_set = {{0x14, 0x00004000}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x0000f000}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s lcd1_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", /*GPIOY_8*/
+ .pinmux_set = {{0x14, 0x00000003}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x0000000f}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+/***************************************************
+ * lcd_2
+ ***************************************************/
+static char lcd2_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static char lcd2_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd2_power_on_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd2_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd2_config[LCD_NUM_MAX] = { //only support lvds
+ {/* normal*/
+ "lvds_0", LCD_LVDS, 8,
+ /* basic timing */
+ 1366, 768, 1569, 806, 56, 64, 0, 3, 28, 0,
+ /* clk_attr */
+ 2, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 0, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd2_power_on_step, lcd2_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_E, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {/* for HDMI convert*/
+ "lvds_1", LCD_LVDS, 8,
+ /* basic timing */
+ 1920, 1080, 2200, 1125, 44, 148, 0, 5, 36, 0,
+ /* clk_attr */
+ 4, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* lvds_attr */
+ 1, 1, 0, 0, 0, 0x3, 0x0, Rsv_val, Rsv_val, Rsv_val,
+ NULL, NULL,
+ /* power step */
+ lcd2_power_on_step, lcd2_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_MAX, 0, 1, 0, 200, 200,
+ BL_PWM_POSITIVE, BL_PWM_MAX, 180, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd2_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s lcd2_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "invalid",
+ },
+};
+
+/***************************************************
+ * lcd default config
+ ***************************************************/
+static struct lcd_dft_config_s lcd_dft_conf[] = {
+ {//index 0
+ .lcd_gpio = lcd0_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd0_config,
+ .lcd_pinmux = lcd0_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd0_bl_gpio,
+ .bl_pinmux = lcd0_bl_pinmux_ctrl,
+ },
+ {//index 1
+ .lcd_gpio = lcd1_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd1_config,
+ .lcd_pinmux = lcd1_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd1_bl_gpio,
+ .bl_pinmux = lcd1_bl_pinmux_ctrl,
+ },
+ {//index 2
+ .lcd_gpio = lcd2_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd2_config,
+ .lcd_pinmux = lcd2_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd2_bl_gpio,
+ .bl_pinmux = lcd2_bl_pinmux_ctrl,
+ }
+};
+
+void lcd_config_bsp_init(void)
+{
+ struct aml_lcd_data_s *pdata = aml_lcd_get_data();
+
+ if (pdata) {
+ pdata->dft_conf[0] = &lcd_dft_conf[0];
+ pdata->dft_conf[1] = &lcd_dft_conf[1];
+ pdata->dft_conf[2] = &lcd_dft_conf[2];
+ }
+}
diff --git a/board/amlogic/t7_skt/t7_skt.c b/board/amlogic/t7_skt/t7_skt.c
new file mode 100644
index 0000000..2dfb632
--- /dev/null
+++ b/board/amlogic/t7_skt/t7_skt.c
@@ -0,0 +1,377 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_VOUT
+#include <amlogic/media/vout/aml_vout.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/media/vout/lcd/lcd_vout.h>
+#endif
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+ aml_set_bootsequence(0);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+#if 0
+ active_clk();
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+#endif
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ /*set vcc5V*/
+ run_command("gpio set GPIOH_1", 0);
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+#ifdef CONFIG_AML_VOUT
+ vout_probe();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0xf1000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xf1000000UL,
+ .phys = 0xf1000000UL,
+ .size = 0x0f000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ //printf("\nmach_cpu_init\n");
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+#endif
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ strcpy(name, "t7_pxp\0");
+ env_set("aml_dt", "t7_pxp\0");
+ return 0;
+}
+#endif
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/amlogic/t7_t319/Kconfig b/board/amlogic/t7_t319/Kconfig
new file mode 100644
index 0000000..8260ee2
--- /dev/null
+++ b/board/amlogic/t7_t319/Kconfig
@@ -0,0 +1,30 @@
+if TARGET_T7_T319
+
+config SYS_SOC
+ default "t7"
+
+config SYS_BOARD
+ default "t7_t319"
+
+config SYS_VENDOR
+ default "amlogic"
+
+config SYS_CONFIG_NAME
+ default "t7_t319"
+
+config DTB_BIND_KERNEL
+ bool "load dtb from boot part but not flash rsv"
+ default n
+
+config CMD_PLLTEST
+ bool "support plltest command"
+ default n
+ help
+ support plltest command
+
+config AML_REBOOT
+ bool "reboot cmd"
+ default y
+ help
+ support uboot reboot cmd
+endif
diff --git a/board/amlogic/t7_t319/Makefile b/board/amlogic/t7_t319/Makefile
new file mode 100644
index 0000000..1e920e7
--- /dev/null
+++ b/board/amlogic/t7_t319/Makefile
@@ -0,0 +1,3 @@
+obj-y += $(BOARD).o
+obj-$(CONFIG_AML_LCD) += lcd.o
+
diff --git a/board/amlogic/t7_t319/firmware/timing.c b/board/amlogic/t7_t319/firmware/timing.c
new file mode 100644
index 0000000..3408b3e
--- /dev/null
+++ b/board/amlogic/t7_t319/firmware/timing.c
@@ -0,0 +1,959 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timing.h>
+#include <asm/arch/ddr_define.h>
+
+/* board clk defines */
+#define CPU_CLK 1512
+
+/* ddr config support multiple configs for boards which use same bootloader:
+ * config steps:
+ * 1. add a new data struct in __ddr_setting[]
+ * 2. config correct board_id, ddr_type, freq, etc..
+ */
+
+
+/* CAUTION!! */
+/* Confirm ddr configs with hardware designer,
+ * if you don't know how to config, then don't edit it
+ */
+
+/* Key configs */
+/*
+ * board_id: check hardware adc config
+ * dram_rank_config:
+ * #define CONFIG_DDR_CHL_AUTO 0xF
+ * #define CONFIG_DDR0_16BIT_CH0 0x1
+ * #define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+ * #define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+ * #define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+ * #define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+ * DramType:
+ * #define CONFIG_DDR_TYPE_DDR3 0
+ * #define CONFIG_DDR_TYPE_DDR4 1
+ * #define CONFIG_DDR_TYPE_LPDDR4 2
+ * #define CONFIG_DDR_TYPE_LPDDR3 3
+ * DRAMFreq:
+ * {pstate0, pstate1, pstate2, pstate3} //more than one pstate means use dynamic freq
+ *
+ */
+
+#define ENABLE_LPDDR4X_MODE 1
+
+#define AN_408_DDR0_1G_DDR1_0G 0
+#define AN_408_DDR0_2G_DDR1_0G 1
+#define AN_408_DDR0_1G_DDR1_1G 2
+#define AN_408_DDR0_2G_DDR1_1G 3
+#define AN_408_DDR0_2G_DDR1_2G 4
+#define AN_408_DDR0_2G_DDR1_2G_RANK01 5
+#define AN_408_DDR0_4G_DDR1_4G_RANK01 6
+
+#define DDR_SIZE_TYPE_1 AN_408_DDR0_1G_DDR1_1G //AN_408_DDR0_2G_DDR1_0G//AN_408_DDR0_2G_DDR1_1G//AN_408_DDR0_1G_DDR1_1G
+
+ddr_set_t __ddr_setting[] __attribute__ ((section(".ddr_param"))) = {
+#if 0
+ {
+ /* tl1 skt (x309) ddr4 */
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_DDR4,
+ .DRAMFreq ={ 1200, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_DDR4_2Gbx8,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 1,
+ .HdtCtrl = 0xC8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x31f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0x23, 0x13 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x0, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 48,
+ .soc_data_odt_ohm_n = 0,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 48, //48, //60,
+ .dram_ac_odt_ohm = 0,
+ .soc_clk_slew_rate = 0x3ff,
+ .soc_cs_slew_rate = 0x3ff,
+ .soc_ac_slew_rate = 0x3ff,
+ .soc_data_slew_rate = 0x2ff,
+ .vref_output_permil = 500,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 0,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay ={ 32 + 20, 32 + 20, 32 + 20, 32 + 20, 32, 32 + 0, 32 + 20, 32 + 20, 32 + 20, 32 + 20},
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 7 << 5 | 8 << 10 | 9 << 15 | 10 << 20 | 11 << 25),
+ [1] = (12 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 13 << 5 | 14 << 10 | 6 << 15 | 0 << 20 | 0 << 25),
+ },
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 00, 00 },
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC_COPY_CHANNEL_CFG, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux =
+ {
+ 2,
+ 5,
+ 20,
+ 14,
+ 8,
+ 24,
+ 4,
+ 13,
+ 25,
+ 12,
+ 10,
+ 23,
+ 26,
+ 18,
+ 0,
+ 0,
+ 0,
+ 9,
+ 1,
+ 19,
+ 0,
+ 22,
+ 11,
+ 7,
+ 6,
+ 3,
+ 0,
+ 0,
+ },
+ .dfi_pinmux =
+ {
+ 18,
+ 15,
+ 16,
+ 12,
+ 5,
+ 20,
+ 10,
+ 7,
+ 0,
+ 11,
+ 14,
+ 8,
+ 23,
+ 17,
+ 3,
+ 13,
+ 22,
+ 2,
+ 21,
+ 19,
+ 6,
+ 4,
+ 1,
+ 0,
+ 0,
+ 0,
+ },
+ },
+#endif
+#if 1
+ {
+ //.fast_boot[0]=0x000000fd,// 253
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .enable_lpddr4x_mode = ENABLE_LPDDR4X_MODE,
+ .DRAMFreq ={ 2016, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xc8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_4G_DDR1_4G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x131f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0, 0 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x3, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 60,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 240,
+ .soc_clk_slew_rate = 0x1ff,
+ .soc_cs_slew_rate = 0x1ff,
+ .soc_ac_slew_rate = 0x1ff,
+ .soc_data_slew_rate = 0x5ff,
+ .vref_output_permil = 629, //300
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 300,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting=0,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ .ac_trace_delay ={ 32 + 10, 32, 0, 0, 0, 32 + 10, 32, 0, 0, 0},
+ //.ac_trace_delay ={ 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32, 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32 + 0},
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25),
+ [1] = (11 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 12 << 5 | 13 << 10 | 14 << 15 | 0 << 20 | 0 << 25),
+ },
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 7, 1, 5, 0, 2, 3, 4, 6,
+ 8, 15, 12, 13, 9, 10, 11, 14,
+ 22, 18, 21, 20, 17, 23, 16, 19,
+ 29, 30, 28, 31, 24, 27, 26, 25 },
+
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, // DDR_FUNC,
+ //.ddr_func = 0, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux ={ 2, 3, 1, 0, 5, 4, 0, 0, 0, 0,
+ 1, 3, 5, 2, 4, 0, 0, 0, 0 },
+
+ .dfi_pinmux =
+ {
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 0,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 0,
+ 0,
+ 0,
+ },
+ },
+
+ {
+ //.fast_boot[0]=0x000000fd,// 253
+ .board_id = CONFIG_BOARD_ID_MASK,
+ .version = 1,
+ //.dram_rank_config = CONFIG_DDR0_32BIT_RANK0_CH0,
+ .DramType = CONFIG_DDR_TYPE_LPDDR4,
+ .enable_lpddr4x_mode = ENABLE_LPDDR4X_MODE,
+ .DRAMFreq ={ 2016, 0, 0, 0 },
+ .ddr_rfc_type = DDR_RFC_TYPE_LPDDR4_8Gbx1,
+ .ddr_base_addr = CFG_DDR_BASE_ADDR,
+ .ddr_start_offset = CFG_DDR_START_OFFSET,
+ .DisabledDbyte[0] = 0xf0, //bit 0 -3 ch0 cs0 ,bit 4-7 ch0 cs1,
+ .DisabledDbyte[1] = 0xf0, //bit 0 -3 ch1 cs0 ,bit 4-7 ch1 cs1,
+ .Is2Ttiming = 0,
+ .HdtCtrl = 0xc8,
+ //.dram_ch0_size_MB = 0xffff,
+ //.dram_ch1_size_MB = 0,
+#if (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_0G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_1G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_1G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX0 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_2G_DDR1_2G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX2 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#elif (DDR_SIZE_TYPE_1 == AN_408_DDR0_4G_DDR1_4G_RANK01)
+ .dram_ch0_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+ .dram_ch1_size_MB =
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS0_BYTE_23_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET) +
+ (DRAM_SIZE_ID_256MBX4 << CONFIG_CS1_BYTE_01_SIZE_256_ID_OFFSET),
+#endif
+ .training_SequenceCtrl ={ 0x131f, 0x61 }, //ddr3 0x21f 0x31f
+ .phy_odt_config_rank ={ 0, 0 }, //use 0x23 0x13 compatibility with 1rank and 2rank //targeting rank 0. [3:0] is used //for write ODT [7:4] is used for //read ODT
+ .dfi_odt_config = 0x0d0d, //use 0d0d compatibility with 1rank and 2rank //0808
+ .PllBypassEn = 0, //bit0-ps0,bit1-ps1
+ .ddr_rdbi_wr_enable = 0x3, //bit 0 read-dbi,bit 1 write dbi
+ .clk_drv_ohm = 40,
+ .cs_drv_ohm = 40,
+ .ac_drv_ohm = 40,
+ .soc_data_drv_ohm_p = 40,
+ .soc_data_drv_ohm_n = 40,
+ .soc_data_odt_ohm_p = 60,
+ .soc_data_odt_ohm_n = 60,
+ .dram_data_drv_ohm = 40, //48, //34, //ddr4 sdram only 34 or 48, skt board use 34 better
+ .dram_data_odt_ohm = 60, //60,
+ .dram_ac_odt_ohm = 240,
+ .soc_clk_slew_rate = 0x1ff,
+ .soc_cs_slew_rate = 0x1ff,
+ .soc_ac_slew_rate = 0x1ff,
+ .soc_data_slew_rate = 0x5ff,
+ .vref_output_permil = 629,
+ .vref_receiver_permil = 0,
+ .vref_dram_permil = 300,
+ .lpddr4_dram_vout_voltage_1_3_2_5_setting=0,
+ //.vref_reverse = 0,
+ //.ac_trace_delay ={0x0,0x0},// {0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40,0x40},
+ //.ac_trace_delay ={ 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32, 32 + 10, 32 + 0, 32 + 2, 32 + 2, 32 + 0},
+ .ac_trace_delay ={ 32 + 10, 32, 0, 0, 0, 32 + 10, 32, 0, 0, 0},
+ .ddr_dmc_remap =
+ {
+ [0] = (5 | 6 << 5 | 7 << 10 | 8 << 15 | 9 << 20 | 10 << 25),
+ [1] = (11 | 0 << 5 | 0 << 10 | 15 << 15 | 16 << 20 | 17 << 25),
+ [2] = (18 | 19 << 5 | 20 << 10 | 21 << 15 | 22 << 20 | 23 << 25),
+ [3] = (24 | 25 << 5 | 26 << 10 | 27 << 15 | 28 << 20 | 29 << 25),
+ [4] = (30 | 12 << 5 | 13 << 10 | 14 << 15 | 0 << 20 | 0 << 25),
+ },
+ .ddr_lpddr34_ca_remap ={ 00, 00 },
+ .ddr_lpddr34_dq_remap ={ 4, 6, 5, 0, 7, 1, 2, 3,
+ 15, 11, 13, 14, 12, 9, 8, 10,
+ 21, 19, 22, 16, 18, 17, 23, 20,
+ 29, 30, 26, 25, 24, 27, 31, 28 },
+ .dram_rtt_nom_wr_park ={ 00, 00 },
+
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ //.pll_ssc_mode = (1<<20) | (1<<8) | (2<<4) | 0,//center_ssc_1000ppm
+ .ddr_func = DDR_FUNC | DDR_FUNC_CONFIG_DFE_FUNCTION, // DDR_FUNC,
+ //.ddr_func = 0, // DDR_FUNC,
+ .magic = DRAM_CFG_MAGIC,
+ .slt_test_function ={ 0x0, 0x0 }, //{0x1,0x0},enable slt 4 DRAMFreq test;{0x0,0x0},disable slt 4 DRAMFreq test;
+ .fast_boot[0] = 0,
+ .ac_pinmux ={ 2, 3, 1, 0, 5, 4, 0, 0, 0, 0,
+ 1, 3, 5, 2, 4, 0, 0, 0, 0 },
+
+ .dfi_pinmux =
+ {
+ 1,
+ 2,
+ 3,
+ 4,
+ 5,
+ 6,
+ 7,
+ 8,
+ 0,
+ 10,
+ 11,
+ 12,
+ 13,
+ 14,
+ 15,
+ 16,
+ 17,
+ 18,
+ 19,
+ 20,
+ 21,
+ 22,
+ 23,
+ 0,
+ 0,
+ 0,
+ },
+ },
+#endif
+};
+
+
+board_clk_set_t __board_clk_setting
+__attribute__ ((section(".clk_param"))) = {
+ /* clock settings for bl2 */
+ .cpu_clk = CPU_CLK / 24 * 24,
+#ifdef CONFIG_PXP_EMULATOR
+ .pxp = 1,
+#else
+ .pxp = 0,
+#endif
+ .low_console_baud = CONFIG_LOW_CONSOLE_BAUD,
+};
+
+#define VCCK_A_VAL AML_VCCK_A_INIT_VOLTAGE
+#define VCCK_B_VAL AML_VCCK_B_INIT_VOLTAGE
+#define VDDEE_VAL AML_VDDEE_INIT_VOLTAGE
+/* VCCK_A uses DCDC PWM table */
+#if (VCCK_A_VAL == 1039)
+#define VCCK_A_VAL_REG 0x00000022
+#elif (VCCK_A_VAL == 1029)
+#define VCCK_A_VAL_REG 0x00010021
+#elif (VCCK_A_VAL == 1019)
+#define VCCK_A_VAL_REG 0x00020020
+#elif (VCCK_A_VAL == 1009)
+#define VCCK_A_VAL_REG 0x0003001f
+#elif (VCCK_A_VAL == 999)
+#define VCCK_A_VAL_REG 0x0004001e
+#elif (VCCK_A_VAL == 989)
+#define VCCK_A_VAL_REG 0x0005001d
+#elif (VCCK_A_VAL == 979)
+#define VCCK_A_VAL_REG 0x0006001c
+#elif (VCCK_A_VAL == 969)
+#define VCCK_A_VAL_REG 0x0007001b
+#elif (VCCK_A_VAL == 959)
+#define VCCK_A_VAL_REG 0x0008001a
+#elif (VCCK_A_VAL == 949)
+#define VCCK_A_VAL_REG 0x00090019
+#elif (VCCK_A_VAL == 939)
+#define VCCK_A_VAL_REG 0x000a0018
+#elif (VCCK_A_VAL == 929)
+#define VCCK_A_VAL_REG 0x000b0017
+#elif (VCCK_A_VAL == 919)
+#define VCCK_A_VAL_REG 0x000c0016
+#elif (VCCK_A_VAL == 909)
+#define VCCK_A_VAL_REG 0x000d0015
+#elif (VCCK_A_VAL == 899)
+#define VCCK_A_VAL_REG 0x000e0014
+#elif (VCCK_A_VAL == 889)
+#define VCCK_A_VAL_REG 0x000f0013
+#elif (VCCK_A_VAL == 879)
+#define VCCK_A_VAL_REG 0x00100012
+#elif (VCCK_A_VAL == 869)
+#define VCCK_A_VAL_REG 0x00110011
+#elif (VCCK_A_VAL == 859)
+#define VCCK_A_VAL_REG 0x00120010
+#elif (VCCK_A_VAL == 849)
+#define VCCK_A_VAL_REG 0x0013000f
+#elif (VCCK_A_VAL == 839)
+#define VCCK_A_VAL_REG 0x0014000e
+#elif (VCCK_A_VAL == 829)
+#define VCCK_A_VAL_REG 0x0015000d
+#elif (VCCK_A_VAL == 819)
+#define VCCK_A_VAL_REG 0x0016000c
+#elif (VCCK_A_VAL == 809)
+#define VCCK_A_VAL_REG 0x0017000b
+#elif (VCCK_A_VAL == 799)
+#define VCCK_A_VAL_REG 0x0018000a
+#elif (VCCK_A_VAL == 789)
+#define VCCK_A_VAL_REG 0x00190009
+#elif (VCCK_A_VAL == 779)
+#define VCCK_A_VAL_REG 0x001a0008
+#elif (VCCK_A_VAL == 769)
+#define VCCK_A_VAL_REG 0x001b0007
+#elif (VCCK_A_VAL == 759)
+#define VCCK_A_VAL_REG 0x001c0006
+#elif (VCCK_A_VAL == 749)
+#define VCCK_A_VAL_REG 0x001d0005
+#elif (VCCK_A_VAL == 739)
+#define VCCK_A_VAL_REG 0x001e0004
+#elif (VCCK_A_VAL == 729)
+#define VCCK_A_VAL_REG 0x001f0003
+#elif (VCCK_A_VAL == 719)
+#define VCCK_A_VAL_REG 0x00200002
+#elif (VCCK_A_VAL == 709)
+#define VCCK_A_VAL_REG 0x00210001
+#elif (VCCK_A_VAL == 699)
+#define VCCK_A_VAL_REG 0x00220000
+#else
+#error "VCCK_A val out of range\n"
+#endif
+
+/* VCCK_B uses PMIC table */
+#if (VCCK_B_VAL == 1040)
+#define VCCK_B_VAL_REG 0x22
+#elif (VCCK_B_VAL == 1030)
+#define VCCK_B_VAL_REG 0x21
+#elif (VCCK_B_VAL == 1020)
+#define VCCK_B_VAL_REG 0x20
+#elif (VCCK_B_VAL == 1010)
+#define VCCK_B_VAL_REG 0x1f
+#elif (VCCK_B_VAL == 1000)
+#define VCCK_B_VAL_REG 0x1e
+#elif (VCCK_B_VAL == 990)
+#define VCCK_B_VAL_REG 0x1d
+#elif (VCCK_B_VAL == 980)
+#define VCCK_B_VAL_REG 0x1c
+#elif (VCCK_B_VAL == 970)
+#define VCCK_B_VAL_REG 0x1b
+#elif (VCCK_B_VAL == 960)
+#define VCCK_B_VAL_REG 0x1a
+#elif (VCCK_B_VAL == 950)
+#define VCCK_B_VAL_REG 0x19
+#elif (VCCK_B_VAL == 940)
+#define VCCK_B_VAL_REG 0x18
+#elif (VCCK_B_VAL == 930)
+#define VCCK_B_VAL_REG 0x17
+#elif (VCCK_B_VAL == 920)
+#define VCCK_B_VAL_REG 0x16
+#elif (VCCK_B_VAL == 910)
+#define VCCK_B_VAL_REG 0x15
+#elif (VCCK_B_VAL == 900)
+#define VCCK_B_VAL_REG 0x14
+#elif (VCCK_B_VAL == 890)
+#define VCCK_B_VAL_REG 0x13
+#elif (VCCK_B_VAL == 880)
+#define VCCK_B_VAL_REG 0x12
+#elif (VCCK_B_VAL == 870)
+#define VCCK_B_VAL_REG 0x11
+#elif (VCCK_B_VAL == 860)
+#define VCCK_B_VAL_REG 0x10
+#elif (VCCK_B_VAL == 850)
+#define VCCK_B_VAL_REG 0xf
+#elif (VCCK_B_VAL == 840)
+#define VCCK_B_VAL_REG 0xe
+#elif (VCCK_B_VAL == 830)
+#define VCCK_B_VAL_REG 0xd
+#elif (VCCK_B_VAL == 820)
+#define VCCK_B_VAL_REG 0xc
+#elif (VCCK_B_VAL == 810)
+#define VCCK_B_VAL_REG 0xb
+#elif (VCCK_B_VAL == 800)
+#define VCCK_B_VAL_REG 0xa
+#elif (VCCK_B_VAL == 790)
+#define VCCK_B_VAL_REG 0x9
+#elif (VCCK_B_VAL == 780)
+#define VCCK_B_VAL_REG 0x8
+#elif (VCCK_B_VAL == 770)
+#define VCCK_B_VAL_REG 0x7
+#elif (VCCK_B_VAL == 760)
+#define VCCK_B_VAL_REG 0x6
+#elif (VCCK_B_VAL == 750)
+#define VCCK_B_VAL_REG 0x5
+#elif (VCCK_B_VAL == 740)
+#define VCCK_B_VAL_REG 0x4
+#elif (VCCK_B_VAL == 730)
+#define VCCK_B_VAL_REG 0x3
+#elif (VCCK_B_VAL == 720)
+#define VCCK_B_VAL_REG 0x2
+#elif (VCCK_B_VAL == 710)
+#define VCCK_B_VAL_REG 0x1
+#elif (VCCK_B_VAL == 700)
+#define VCCK_B_VAL_REG 0x0
+#else
+#error "\nVCCK_B val out of range\n"
+#endif
+
+/* VDDEE_VAL_REG */
+#if (VDDEE_VAL == 1040)
+#define VDDEE_VAL_REG 0x22
+#elif (VDDEE_VAL == 1030)
+#define VDDEE_VAL_REG 0x21
+#elif (VDDEE_VAL == 1020)
+#define VDDEE_VAL_REG 0x20
+#elif (VDDEE_VAL == 1010)
+#define VDDEE_VAL_REG 0x1f
+#elif (VDDEE_VAL == 1000)
+#define VDDEE_VAL_REG 0x1e
+#elif (VDDEE_VAL == 990)
+#define VDDEE_VAL_REG 0x1d
+#elif (VDDEE_VAL == 980)
+#define VDDEE_VAL_REG 0x1c
+#elif (VDDEE_VAL == 970)
+#define VDDEE_VAL_REG 0x1b
+#elif (VDDEE_VAL == 960)
+#define VDDEE_VAL_REG 0x1a
+#elif (VDDEE_VAL == 950)
+#define VDDEE_VAL_REG 0x19
+#elif (VDDEE_VAL == 940)
+#define VDDEE_VAL_REG 0x18
+#elif (VDDEE_VAL == 930)
+#define VDDEE_VAL_REG 0x17
+#elif (VDDEE_VAL == 920)
+#define VDDEE_VAL_REG 0x16
+#elif (VDDEE_VAL == 910)
+#define VDDEE_VAL_REG 0x15
+#elif (VDDEE_VAL == 900)
+#define VDDEE_VAL_REG 0x14
+#elif (VDDEE_VAL == 890)
+#define VDDEE_VAL_REG 0x13
+#elif (VDDEE_VAL == 880)
+#define VDDEE_VAL_REG 0x12
+#elif (VDDEE_VAL == 870)
+#define VDDEE_VAL_REG 0x11
+#elif (VDDEE_VAL == 860)
+#define VDDEE_VAL_REG 0x10
+#elif (VDDEE_VAL == 850)
+#define VDDEE_VAL_REG 0xf
+#elif (VDDEE_VAL == 840)
+#define VDDEE_VAL_REG 0xe
+#elif (VDDEE_VAL == 830)
+#define VDDEE_VAL_REG 0xd
+#elif (VDDEE_VAL == 820)
+#define VDDEE_VAL_REG 0xc
+#elif (VDDEE_VAL == 810)
+#define VDDEE_VAL_REG 0xb
+#elif (VDDEE_VAL == 800)
+#define VDDEE_VAL_REG 0xa
+#elif (VDDEE_VAL == 790)
+#define VDDEE_VAL_REG 0x9
+#elif (VDDEE_VAL == 780)
+#define VDDEE_VAL_REG 0x8
+#elif (VDDEE_VAL == 770)
+#define VDDEE_VAL_REG 0x7
+#elif (VDDEE_VAL == 760)
+#define VDDEE_VAL_REG 0x6
+#elif (VDDEE_VAL == 750)
+#define VDDEE_VAL_REG 0x5
+#elif (VDDEE_VAL == 740)
+#define VDDEE_VAL_REG 0x4
+#elif (VDDEE_VAL == 730)
+#define VDDEE_VAL_REG 0x3
+#elif (VDDEE_VAL == 720)
+#define VDDEE_VAL_REG 0x2
+#elif (VDDEE_VAL == 710)
+#define VDDEE_VAL_REG 0x1
+#elif (VDDEE_VAL == 700)
+#define VDDEE_VAL_REG 0x0
+#else
+#error "\nVDDEE val out of range\n"
+#endif
+
+bl2_reg_t __bl2_reg[] __attribute__ ((section(".generic_param"))) = {
+ //hxbao, need fine tune
+ { 0, 0, 0xffffffff, 0, 0, 0 },
+};
+
+#define I2C_BUS 0x2
+#define I2C_AO_A 6 /*from bl2 i2c meson_i2c.h*/
+#define I2C_DEV_ADDR 0x4b
+#define BD71837_REG_BUCK2_CTRL 0x06
+#define BD71837_REG_BUCK3_CTRL 0x07
+#define BD71837_REG_BUCK2_VOLT_RUN 0x10
+#define BD71837_REG_BUCK3_VOLT_RUN 0x12
+#define BD71837_REG_REGLOCK 0x2f
+#define BD71837_REG_MUXSW_EN 0x30
+
+/* pmu/gpio/pinmux/pwm init */
+register_ops_t __bl2_ops_reg[MAX_REG_OPS_ENTRIES]
+__attribute__ ((section(".misc_param"))) = {
+ /* set TEST_N to high */
+ { PADCTRL_TESTN_O, (0x1 << 0), (0x1 << 0), 0, 0, 0 },
+ { PADCTRL_TESTN_OEN, (0x0 << 0), (0x1 << 0), 0, 0, 0 },
+
+ /* config vcck a pwm - pwmao_d */
+ { PWM_AO_CD_PWM_B, VCCK_A_VAL_REG, 0xffffffff, 0, 0, 0 },
+ { PWM_AO_CD_MISC_REG_AB, (0x1 << 1), (0x1 << 1), 0, 0, 0 },
+ { CLKCTRL_PWM_CLK_AO_CD_CTRL, (0x1 << 24), (0x7FF << 16), 0, 0, 0 },
+
+ /* enable pwmao_d, Wait for pmic to enable VCCK A */
+ /* set gpioe_3 ds to max */
+ { PADCTRL_GPIOE_DS, (0x3 << 6), (0x3 << 6), 0, 0, 0 },
+ /* mux gpioe_3 to pwmao_d */
+ { PADCTRL_PIN_MUX_REGC, (0x1 << 12), (0xf << 12), 0, 0, 0 },
+
+ /* pull low gpioy_5 make tp rst low*/
+ {PADCTRL_PIN_MUX_REGA, (0 << 20), (0xf << 20), 0, 0, 0},
+ {PADCTRL_GPIOY_O, (0 << 5), (1 << 5), 0, 0, 0},
+ {PADCTRL_GPIOY_OEN, (0 << 5), (1 << 5), 0, 0, 0},
+
+ /* disable tp int bias */
+ {PADCTRL_GPIOM_PULL_EN, (0 << 5), (1 << 5), 0, 0, 0},
+
+ /*set pinmux GPIOD_2(I2CM_AO_A_SCL) and GPIOD_3(I2CM_AO_A_SDA) for pmic*/
+ { PADCTRL_GPIOD_DS, (0xf << 4), (0xf << 4), 0, 0, 0 },
+ { PADCTRL_GPIOD_PULL_EN, (0x3 << 2), (0x3 << 2), 0, 0, 0 },
+ { PADCTRL_GPIOD_PULL_UP, (0x3 << 2), (0x3 << 2), 0, 0, 0 },
+ { PADCTRL_PIN_MUX_REGA, (0x11 << 8), (0xff << 8), 0, 0, 0 },
+ { BD71837_REG_REGLOCK, 1, (1 << 4), 0, (I2C_BUS << 4) | (I2C_AO_A), I2C_DEV_ADDR },
+ /*set vddee voltage*/
+ { BD71837_REG_BUCK2_VOLT_RUN, VDDEE_VAL_REG, 0x3f, 0, \
+ (I2C_BUS << 4) | (I2C_AO_A), I2C_DEV_ADDR },
+ /*set vddcpub voltage*/
+ { BD71837_REG_BUCK3_VOLT_RUN, VCCK_B_VAL_REG, 0x3f, 0, \
+ (I2C_BUS << 4) | (I2C_AO_A), I2C_DEV_ADDR },
+ { BD71837_REG_MUXSW_EN, 1, 1, 0, \
+ (I2C_BUS << 4) | (I2C_AO_A), I2C_DEV_ADDR },
+
+ /* make watchdog send reset signal, !!Please dont't copy below to other board
+ * which have no pmic or reset will not work
+ */
+ { PADCTRL_PIN_MUX_REGB, (0x1 << 16), (0xf << 16), 0, 0, 0 },
+ { RESETCTRL_WATCHDOG_CTRL1, (0x3ffff << 0), (0x3ffff << 0), 0, 0, 0 },
+ { RESETCTRL_SEC_WATCHDOG_CTRL1, (0x3ffff << 0), (0x3ffff << 0), 0, 0, 0 },
+ { PADCTRL_WD_RSTO_CTRL, (1 << 0), (1 << 0), 0, 0, 0 },
+};
+
+/* for all the storage parameter */
+storage_parameter_t __store_para __attribute__ ((section(".store_param"))) = {
+ .common ={
+ .version = 0x01,
+ .device_fip_container_size = 0x280000,
+ .device_fip_container_copies = 4,
+ },
+ .nand ={
+ .version = 0x01,
+ .bbt_pages = 0x1,
+ .bbt_start_block = 0x20,
+ .discrete_mode = 1,
+ .setup_data.nand_setup_data = (2 << 20) | \
+ (0 << 19) | \
+ (1 << 17) | \
+ (4 << 14) | \
+ (0 << 13) | \
+ (64 << 6) | \
+ (4 << 0),
+ .reserved_area_blk_cnt = 48,
+ .page_per_block = 128,
+ .use_param_page_list = 0,
+ },
+};
diff --git a/board/amlogic/t7_t319/fw_arb.cfg b/board/amlogic/t7_t319/fw_arb.cfg
new file mode 100644
index 0000000..5237e72
--- /dev/null
+++ b/board/amlogic/t7_t319/fw_arb.cfg
@@ -0,0 +1,16 @@
+# Configure Firmware Anti-rollback Versions
+device_scs_vers=0x0
+device_tee_vers=0x0
+device_ree_vers=0x0
+
+# Configure Segmentation ID
+DEVICE_SCS_SEGID=0x0
+DEVICE_VENDOR_SEGID=0x0
+
+###############################################################
+DEVICE_SCS_VERS=0x$(printf %x $(((1 << $device_scs_vers) - 1)))
+DEVICE_TEE_VERS=0x$(printf %x $(((1 << $device_tee_vers) - 1)))
+DEVICE_REE_VERS=0x$(printf %x $(((1 << $device_ree_vers) - 1)))
+echo $DEVICE_SCS_VERS
+echo $DEVICE_TEE_VERS
+echo $DEVICE_REE_VERS
diff --git a/board/amlogic/t7_t319/lcd.c b/board/amlogic/t7_t319/lcd.c
new file mode 100644
index 0000000..e797fb5
--- /dev/null
+++ b/board/amlogic/t7_t319/lcd.c
@@ -0,0 +1,148 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+
+/***************************************************
+ * lcd_0
+ ***************************************************/
+static char lcd0_cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "gpio_test_n0", /* panel vcc */
+ "invalid", /* ending flag */
+};
+
+static char lcd0_bl_gpio[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "GPIOH_1", /* enable */
+ "GPIOD_5", /* pwm_ao_h */
+ "invalid", /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_on_step[] = {
+ {LCD_POWER_TYPE_CPU, 0, 1, 50,}, /* panel vcc */
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 0,},
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+static struct lcd_power_step_s lcd0_power_off_step[] = {
+ {LCD_POWER_TYPE_SIGNAL, 0, 0, 10,},
+ {LCD_POWER_TYPE_CPU, 0, 0, 500,}, /* panel vcc */
+ {LCD_POWER_TYPE_MAX, 0, 0, 0,}, /* ending flag */
+};
+
+struct ext_lcd_config_s ext_lcd0_config[LCD_NUM_MAX] = {
+ {"edp_0", LCD_EDP, 8,
+ /* basic timing */
+ 1920, 1080, 2200, 1120, 44, 148, 0, 5, 30, 0,
+ /* clk_attr */
+ 1, 0, 1, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ /* edp_attr */
+ 2, 1, 0, 0, 0, 0, 0, 0, 0x5, 0x1,
+ NULL, NULL,
+ /* power step */
+ lcd0_power_on_step, lcd0_power_off_step,
+ /* backlight */
+ 60, 255, 10, 128, 128,
+ BL_CTRL_PWM, 0, 1, 0, 60, 60,
+ BL_PWM_POSITIVE, BL_PWM_AO_H, 2000, 100, 25, 1, 0,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ Rsv_val, Rsv_val, Rsv_val, Rsv_val,
+ 10, 10, Rsv_val},
+
+ {.panel_type = "invalid"},
+};
+
+static struct lcd_pinmux_ctrl_s lcd0_pinmux_ctrl[LCD_PINMX_MAX] = {
+ {
+ .name = "lcd_edp_pin", //GPIOY_10
+ .pinmux_set = {{0x14, 0x00000400}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0x14, 0x00000f00}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+static struct lcd_pinmux_ctrl_s lcd0_bl_pinmux_ctrl[BL_PINMUX_MAX] = {
+ {
+ .name = "bl_pwm_on_pin", /*GPIOD_5*/
+ .pinmux_set = {{0xa, 0x00200000}, {LCD_PINMUX_END, 0x0} },
+
+ .pinmux_clr = {{0xa, 0x00f00000}, {LCD_PINMUX_END, 0x0} },
+ },
+ {
+ .name = "invalid",
+ },
+};
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static char lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX] = {
+ "invalid", /* ending flag */
+};
+
+static unsigned char init_on_table[LCD_EXTERN_INIT_ON_MAX] = {
+ 0xff, 0, /* ending */
+};
+
+static unsigned char init_off_table[LCD_EXTERN_INIT_OFF_MAX] = {
+ 0xff, 0, /* ending */
+};
+
+struct lcd_extern_common_s ext_common_dft = {
+ .lcd_ext_key_valid = 0,
+ .lcd_ext_num = 1,
+ .pinmux_set = {{LCD_PINMUX_END, 0x0} },
+ .pinmux_clr = {{LCD_PINMUX_END, 0x0} },
+};
+
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX] = {
+ {
+ .index = 0,
+ .name = "invalid",
+ /* LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MAX */
+ .type = LCD_EXTERN_MAX,
+ .status = 0, /* 0=disable, 1=enable */
+ .i2c_addr = 0x20, /* 7bit i2c address */
+ .i2c_addr2 = 0x74, /* 7bit i2c address, 0xff for none */
+ /* LCD_EXTERN_I2C_BUS_0/1/2/3/4 */
+ .i2c_bus = LCD_EXTERN_I2C_BUS_1,
+ .cmd_size = 0xff,
+ .table_init_on = init_on_table,
+ .table_init_off = init_off_table,
+ },
+ {
+ .index = LCD_EXTERN_INDEX_INVALID,
+ },
+};
+#endif
+
+/***************************************************
+ * lcd default config
+ ***************************************************/
+static struct lcd_dft_config_s lcd_dft_conf = {
+ .lcd_gpio = lcd0_cpu_gpio,
+ .key_valid = 0,
+ .clk_path = 0,
+ .mode = LCD_MODE_TABLET,
+ .ext_lcd = ext_lcd0_config,
+ .lcd_pinmux = lcd0_pinmux_ctrl,
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ .ext_gpio = lcd_ext_gpio[0],
+ .ext_common = &ext_common_dft,
+ .ext_conf = ext_config_dtf,
+#endif
+ .bl_gpio = lcd0_bl_gpio,
+ .bl_pinmux = lcd0_bl_pinmux_ctrl,
+};
+
+void lcd_config_bsp_init(void)
+{
+ struct aml_lcd_data_s *pdata = aml_lcd_get_data();
+
+ if (pdata)
+ pdata->dft_conf[0] = &lcd_dft_conf;
+}
diff --git a/board/amlogic/t7_t319/t7_t319.c b/board/amlogic/t7_t319/t7_t319.c
new file mode 100644
index 0000000..0e1bcd6
--- /dev/null
+++ b/board/amlogic/t7_t319/t7_t319.c
@@ -0,0 +1,406 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <errno.h>
+#include <environment.h>
+#include <fdt_support.h>
+#include <linux/libfdt.h>
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/pinctrl_init.h>
+#include <linux/sizes.h>
+#include <asm-generic/gpio.h>
+#include <dm.h>
+#include <asm/armv8/mmu.h>
+#include <amlogic/aml_v3_burning.h>
+#include <amlogic/aml_v2_burning.h>
+#include <linux/mtd/partitions.h>
+#include <asm/arch/bl31_apis.h>
+#ifdef CONFIG_AML_VPU
+#include <amlogic/media/vpu/vpu.h>
+#endif
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#ifdef CONFIG_AML_VOUT
+#include <amlogic/media/vout/aml_vout.h>
+#endif
+#ifdef CONFIG_AML_HDMITX20
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
+#endif
+#ifdef CONFIG_AML_LCD
+#include <amlogic/media/vout/lcd/lcd_vout.h>
+#endif
+#include <asm/arch/pmic_bd71837.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+void sys_led_init(void)
+{
+}
+
+int serial_set_pin_port(unsigned long port_base)
+{
+ return 0;
+}
+
+int dram_init(void)
+{
+ gd->ram_size = PHYS_SDRAM_1_SIZE;
+ return 0;
+}
+
+/* secondary_boot_func
+ * this function should be write with asm, here, is is only for compiling pass
+ * */
+void secondary_boot_func(void)
+{
+}
+
+int board_eth_init(bd_t *bis)
+{
+ return 0;
+}
+
+int active_clk(void)
+{
+ struct udevice *clk = NULL;
+ int err;
+
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "xtal-clk", &clk);
+ if (err) {
+ pr_err("Can't find xtal-clk clock (%d)\n", err);
+ return err;
+ }
+ err = uclass_get_device_by_name(UCLASS_CLK,
+ "clock-controller@0", &clk);
+ if (err) {
+ pr_err("Can't find clock-controller@0 clock (%d)\n", err);
+ return err;
+ }
+
+ return 0;
+}
+
+
+#ifdef CONFIG_AML_HDMITX20
+static void hdmitx_set_hdmi_5v(void)
+{
+ /*Power on VCC_5V for HDMI_5V*/
+}
+#endif
+void board_init_mem(void) {
+ #if 1
+ /* config bootm low size, make sure whole dram/psram space can be used */
+ phys_size_t ram_size;
+ char *env_tmp;
+ env_tmp = env_get("bootm_size");
+ if (!env_tmp) {
+ ram_size = (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4);
+ env_set_hex("bootm_low", 0);
+ env_set_hex("bootm_size", ram_size);
+ }
+ #endif
+}
+
+int board_init(void)
+{
+ printf("board init\n");
+
+ /* The non-secure watchdog is enabled in BL2 TEE, disable it */
+ run_command("watchdog off", 0);
+ printf("watchdog disable\n");
+
+ pmic_bd71837_init();
+
+ aml_set_bootsequence(0);
+ //Please keep try usb boot first in board_init, as other init before usb may cause burning failure
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if ((0x1b8ec003 != readl(SYSCTRL_SEC_STICKY_REG2)) && (0x1b8ec004 != readl(SYSCTRL_SEC_STICKY_REG2)))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+#if 0
+ active_clk();
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_hdmi_5v();
+ hdmitx_init();
+#endif
+#endif
+ pinctrl_devices_active(PIN_CONTROLLER_NUM);
+ return 0;
+}
+
+int board_late_init(void)
+{
+ printf("board late init\n");
+
+ run_command("echo upgrade_step $upgrade_step; if itest ${upgrade_step} == 1; then "\
+ "defenv_reserv; setenv upgrade_step 2; saveenv; fi;", 0);
+ board_init_mem();
+ run_command("run bcb_cmd", 0);
+
+#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+ if ( run_command("run common_dtb_load", 0) ) {
+ printf("Fail in load dtb with cmd[%s]\n", env_get("common_dtb_load"));
+ } else {
+ //load dtb here then users can directly use 'fdt' command
+ run_command("if fdt addr ${dtb_mem_addr}; then else echo no valid dtb at ${dtb_mem_addr};fi;", 0);
+ }
+#endif//#ifndef CONFIG_SYSTEM_RTOS //prue rtos not need dtb
+
+#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE //try auto upgrade from ext-sdcard
+ aml_try_factory_sdcard_burning(0, gd->bd);
+#endif//#ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
+ //auto enter usb mode after board_late_init if 'adnl.exe setvar burnsteps 0x1b8ec003'
+#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+ if (0x1b8ec003 == readl(SYSCTRL_SEC_STICKY_REG2))
+ { aml_v3_factory_usb_burning(0, gd->bd); }
+#endif//#if defined(CONFIG_AML_V3_FACTORY_BURN) && defined(CONFIG_AML_V3_USB_TOOl)
+
+#ifdef CONFIG_AML_VPU
+ vpu_probe();
+#endif
+#ifdef CONFIG_AML_VPP
+ vpp_init();
+#endif
+#ifdef CONFIG_AML_VOUT
+ vout_probe();
+#endif
+#ifdef CONFIG_AML_LCD
+ lcd_probe();
+#endif
+
+ bd71837_set_muxsw_switch(1);
+ return 0;
+}
+
+
+phys_size_t get_effective_memsize(void)
+{
+ // >>16 -> MB, <<20 -> real size, so >>16<<20 = <<4
+#if defined(CONFIG_SYS_MEM_TOP_HIDE)
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4) - CONFIG_SYS_MEM_TOP_HIDE;
+#else
+ return (((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4);
+#endif /* CONFIG_SYS_MEM_TOP_HIDE */
+
+}
+
+static struct mm_region bd_mem_map[] = {
+ {
+ .virt = 0x00000000UL,
+ .phys = 0x00000000UL,
+ .size = 0xe0000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0x100000000UL,
+ .phys = 0x100000000UL,
+ .size = 0x120000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
+ PTE_BLOCK_INNER_SHARE
+ }, {
+ .virt = 0xe0000000UL,
+ .phys = 0xe0000000UL,
+ .size = 0x20000000UL,
+ .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
+ PTE_BLOCK_NON_SHARE |
+ PTE_BLOCK_PXN | PTE_BLOCK_UXN
+ }, {
+ /* List terminator */
+ 0,
+ }
+};
+
+struct mm_region *mem_map = bd_mem_map;
+
+int mach_cpu_init(void) {
+ //printf("\nmach_cpu_init\n");
+#ifdef CONFIG_UPDATE_MMU_TABLE
+ unsigned long nddrSize = ((readl(SYSCTRL_SEC_STATUS_REG4)) & 0xFFFFFFFF0000) << 4;
+ if ( nddrSize <= 0xe0000000 )
+ {
+ bd_mem_map[0].size = nddrSize;
+ bd_mem_map[1].virt = 0;
+ bd_mem_map[1].phys = 0;
+ bd_mem_map[1].size = 0;
+ }
+#endif
+ return 0;
+}
+
+int ft_board_setup(void *blob, bd_t *bd)
+{
+ /* eg: bl31/32 rsv */
+ return 0;
+}
+
+/* partition table for spinor flash */
+#ifdef CONFIG_SPI_FLASH
+static const struct mtd_partition spiflash_partitions[] = {
+ {
+ .name = "env",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "dtb",
+ .offset = 0,
+ .size = 1 * SZ_256K,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "user",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+
+const struct mtd_partition *get_spiflash_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spiflash_partitions);
+ return spiflash_partitions;
+}
+#endif /* CONFIG_SPI_FLASH */
+
+#ifdef CONFIG_MESON_NFC
+static struct mtd_partition normal_partition_info[] = {
+#ifdef CONFIG_DISCRETE_BOOTLOADER
+{
+ .name = BOOT_BL2E,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_BL2X,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DDRFIP,
+ .offset = 0,
+ .size = 0,
+},
+{
+ .name = BOOT_DEVFIP,
+ .offset = 0,
+ .size = 0,
+},
+#endif
+{
+ .name = "logo",
+ .offset = 0,
+ .size = 2*SZ_1M,
+},
+{
+ .name = "recovery",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "boot",
+ .offset = 0,
+ .size = 16*SZ_1M,
+},
+{
+ .name = "system",
+ .offset = 0,
+ .size = 64*SZ_1M,
+},
+/* last partition get the rest capacity */
+{
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+},
+};
+
+struct mtd_partition *get_aml_mtd_partition(void)
+{
+ return normal_partition_info;
+}
+
+int get_aml_partition_count(void)
+{
+ return ARRAY_SIZE(normal_partition_info);
+}
+
+#endif
+
+/* partition table */
+/* partition table for spinand flash */
+#if (defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND))
+static const struct mtd_partition spinand_partitions[] = {
+ {
+ .name = "logo",
+ .offset = 0,
+ .size = 2 * SZ_1M,
+ },
+ {
+ .name = "recovery",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "boot",
+ .offset = 0,
+ .size = 16 * SZ_1M,
+ },
+ {
+ .name = "system",
+ .offset = 0,
+ .size = 64 * SZ_1M,
+ },
+ /* last partition get the rest capacity */
+ {
+ .name = "data",
+ .offset = MTDPART_OFS_APPEND,
+ .size = MTDPART_SIZ_FULL,
+ }
+};
+const struct mtd_partition *get_partition_table(int *partitions)
+{
+ *partitions = ARRAY_SIZE(spinand_partitions);
+ return spinand_partitions;
+}
+#endif /* CONFIG_SPI_NAND */
+
+#ifdef CONFIG_MULTI_DTB
+int checkhw(char * name)
+{
+ strcpy(name, "t7_pop1_t319\0");
+ env_set("aml_dt", "t7_pop1_t319\0");
+ return 0;
+}
+#endif
+
+const char * const _env_args_reserve_[] =
+{
+ "lock",
+ "upgrade_step",
+ "bootloader_version",
+
+ NULL//Keep NULL be last to tell END
+};
+
+int __attribute__((weak)) mmc_initialize(bd_t *bis){ return 0;}
+
+int __attribute__((weak)) do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]){ return 0;}
+
+void __attribute__((weak)) set_working_fdt_addr(ulong addr) {}
+
+int __attribute__((weak)) ofnode_read_u32_default(ofnode node, const char *propname, u32 def) {return 0;}
+
+void __attribute__((weak)) md5_wd (unsigned char *input, int len, unsigned char output[16], unsigned int chunk_sz){}
diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig
index 4e1ad00..e416c9a 100644
--- a/board/aristainetos/Kconfig
+++ b/board/aristainetos/Kconfig
@@ -27,4 +27,3 @@
default "aristainetos2b"
endif
-
diff --git a/board/armadeus/apf27/Kconfig b/board/armadeus/apf27/Kconfig
index 4c3400a..a342d2e 100644
--- a/board/armadeus/apf27/Kconfig
+++ b/board/armadeus/apf27/Kconfig
@@ -16,4 +16,3 @@
default "apf27"
endif
-
diff --git a/board/armadeus/opos6uldev/Kconfig b/board/armadeus/opos6uldev/Kconfig
index 00aa6c4..e66f060 100644
--- a/board/armadeus/opos6uldev/Kconfig
+++ b/board/armadeus/opos6uldev/Kconfig
@@ -13,4 +13,3 @@
default "arch/arm/mach-imx/spl_sd.cfg"
endif
-
diff --git a/board/armltd/vexpress/Kconfig b/board/armltd/vexpress/Kconfig
index 4b4266f..2e15e0d 100644
--- a/board/armltd/vexpress/Kconfig
+++ b/board/armltd/vexpress/Kconfig
@@ -36,4 +36,3 @@
default "vexpress_ca9x4"
endif
-
diff --git a/board/armltd/vexpress64/Kconfig b/board/armltd/vexpress64/Kconfig
index 86dabcf..e05f353 100644
--- a/board/armltd/vexpress64/Kconfig
+++ b/board/armltd/vexpress64/Kconfig
@@ -10,4 +10,3 @@
default "vexpress_aemv8a"
endif
-
diff --git a/board/aspeed/evb_ast2500/Kconfig b/board/aspeed/evb_ast2500/Kconfig
index 1ec1db5..73a8ae8 100644
--- a/board/aspeed/evb_ast2500/Kconfig
+++ b/board/aspeed/evb_ast2500/Kconfig
@@ -10,4 +10,3 @@
default "evb_ast2500"
endif
-
diff --git a/board/astro/mcf5373l/Kconfig b/board/astro/mcf5373l/Kconfig
index 20c76ba..a7c04ce 100644
--- a/board/astro/mcf5373l/Kconfig
+++ b/board/astro/mcf5373l/Kconfig
@@ -13,4 +13,3 @@
default "astro_mcf5373l"
endif
-
diff --git a/board/atmark-techno/armadillo-800eva/Kconfig b/board/atmark-techno/armadillo-800eva/Kconfig
index e8fcb99..cd37dd4 100644
--- a/board/atmark-techno/armadillo-800eva/Kconfig
+++ b/board/atmark-techno/armadillo-800eva/Kconfig
@@ -10,4 +10,3 @@
default "armadillo-800eva"
endif
-
diff --git a/board/atmel/at91rm9200ek/Kconfig b/board/atmel/at91rm9200ek/Kconfig
index 7c2d275..952351d 100644
--- a/board/atmel/at91rm9200ek/Kconfig
+++ b/board/atmel/at91rm9200ek/Kconfig
@@ -10,4 +10,3 @@
default "at91rm9200ek"
endif
-
diff --git a/board/atmel/at91sam9260ek/Kconfig b/board/atmel/at91sam9260ek/Kconfig
index 589ede4..3844f08 100644
--- a/board/atmel/at91sam9260ek/Kconfig
+++ b/board/atmel/at91sam9260ek/Kconfig
@@ -10,4 +10,3 @@
default "at91sam9260ek"
endif
-
diff --git a/board/atmel/at91sam9261ek/Kconfig b/board/atmel/at91sam9261ek/Kconfig
index f2ff02c..2971b3c 100644
--- a/board/atmel/at91sam9261ek/Kconfig
+++ b/board/atmel/at91sam9261ek/Kconfig
@@ -10,4 +10,3 @@
default "at91sam9261ek"
endif
-
diff --git a/board/atmel/at91sam9263ek/Kconfig b/board/atmel/at91sam9263ek/Kconfig
index 5de0246..3f0873f 100644
--- a/board/atmel/at91sam9263ek/Kconfig
+++ b/board/atmel/at91sam9263ek/Kconfig
@@ -10,4 +10,3 @@
default "at91sam9263ek"
endif
-
diff --git a/board/atmel/at91sam9m10g45ek/Kconfig b/board/atmel/at91sam9m10g45ek/Kconfig
index 4db644b..211c411 100644
--- a/board/atmel/at91sam9m10g45ek/Kconfig
+++ b/board/atmel/at91sam9m10g45ek/Kconfig
@@ -10,4 +10,3 @@
default "at91sam9m10g45ek"
endif
-
diff --git a/board/atmel/at91sam9n12ek/Kconfig b/board/atmel/at91sam9n12ek/Kconfig
index cecd533..816003a 100644
--- a/board/atmel/at91sam9n12ek/Kconfig
+++ b/board/atmel/at91sam9n12ek/Kconfig
@@ -10,4 +10,3 @@
default "at91sam9n12ek"
endif
-
diff --git a/board/atmel/at91sam9rlek/Kconfig b/board/atmel/at91sam9rlek/Kconfig
index 82dbccd..81a839a 100644
--- a/board/atmel/at91sam9rlek/Kconfig
+++ b/board/atmel/at91sam9rlek/Kconfig
@@ -10,4 +10,3 @@
default "at91sam9rlek"
endif
-
diff --git a/board/atmel/at91sam9x5ek/Kconfig b/board/atmel/at91sam9x5ek/Kconfig
index c1b1161..3f92754 100644
--- a/board/atmel/at91sam9x5ek/Kconfig
+++ b/board/atmel/at91sam9x5ek/Kconfig
@@ -10,4 +10,3 @@
default "at91sam9x5ek"
endif
-
diff --git a/board/atmel/sama5d27_som1_ek/Kconfig b/board/atmel/sama5d27_som1_ek/Kconfig
index f344cd8..3276214 100644
--- a/board/atmel/sama5d27_som1_ek/Kconfig
+++ b/board/atmel/sama5d27_som1_ek/Kconfig
@@ -13,4 +13,3 @@
default "sama5d27_som1_ek"
endif
-
diff --git a/board/atmel/sama5d2_ptc_ek/Kconfig b/board/atmel/sama5d2_ptc_ek/Kconfig
index a09f8ab..8b202d6 100644
--- a/board/atmel/sama5d2_ptc_ek/Kconfig
+++ b/board/atmel/sama5d2_ptc_ek/Kconfig
@@ -13,4 +13,3 @@
default "sama5d2_ptc_ek"
endif
-
diff --git a/board/atmel/sama5d2_xplained/Kconfig b/board/atmel/sama5d2_xplained/Kconfig
index d4d4007..55712e9 100644
--- a/board/atmel/sama5d2_xplained/Kconfig
+++ b/board/atmel/sama5d2_xplained/Kconfig
@@ -13,4 +13,3 @@
default "sama5d2_xplained"
endif
-
diff --git a/board/atmel/sama5d3_xplained/Kconfig b/board/atmel/sama5d3_xplained/Kconfig
index 4289de6..2df751a 100644
--- a/board/atmel/sama5d3_xplained/Kconfig
+++ b/board/atmel/sama5d3_xplained/Kconfig
@@ -10,4 +10,3 @@
default "sama5d3_xplained"
endif
-
diff --git a/board/atmel/sama5d3xek/Kconfig b/board/atmel/sama5d3xek/Kconfig
index 902b1b8..abd1ad8 100644
--- a/board/atmel/sama5d3xek/Kconfig
+++ b/board/atmel/sama5d3xek/Kconfig
@@ -10,4 +10,3 @@
default "sama5d3xek"
endif
-
diff --git a/board/atmel/sama5d4_xplained/Kconfig b/board/atmel/sama5d4_xplained/Kconfig
index 8285485..2cb03cb 100644
--- a/board/atmel/sama5d4_xplained/Kconfig
+++ b/board/atmel/sama5d4_xplained/Kconfig
@@ -10,4 +10,3 @@
default "sama5d4_xplained"
endif
-
diff --git a/board/atmel/sama5d4ek/Kconfig b/board/atmel/sama5d4ek/Kconfig
index 0214e4f..1a63403 100644
--- a/board/atmel/sama5d4ek/Kconfig
+++ b/board/atmel/sama5d4ek/Kconfig
@@ -10,4 +10,3 @@
default "sama5d4ek"
endif
-
diff --git a/board/avionic-design/medcom-wide/Kconfig b/board/avionic-design/medcom-wide/Kconfig
index 1d8795c..267647c 100644
--- a/board/avionic-design/medcom-wide/Kconfig
+++ b/board/avionic-design/medcom-wide/Kconfig
@@ -10,4 +10,3 @@
default "medcom-wide"
endif
-
diff --git a/board/avionic-design/plutux/Kconfig b/board/avionic-design/plutux/Kconfig
index 77ec583..09a3ac9 100644
--- a/board/avionic-design/plutux/Kconfig
+++ b/board/avionic-design/plutux/Kconfig
@@ -10,4 +10,3 @@
default "plutux"
endif
-
diff --git a/board/avionic-design/tec-ng/Kconfig b/board/avionic-design/tec-ng/Kconfig
index 0a39fd3..36a0cec 100644
--- a/board/avionic-design/tec-ng/Kconfig
+++ b/board/avionic-design/tec-ng/Kconfig
@@ -10,4 +10,3 @@
default "tec-ng"
endif
-
diff --git a/board/avionic-design/tec/Kconfig b/board/avionic-design/tec/Kconfig
index 06009a5..bc9751b 100644
--- a/board/avionic-design/tec/Kconfig
+++ b/board/avionic-design/tec/Kconfig
@@ -10,4 +10,3 @@
default "tec"
endif
-
diff --git a/board/bachmann/ot1200/Kconfig b/board/bachmann/ot1200/Kconfig
index 75331a6..4ccb60a 100644
--- a/board/bachmann/ot1200/Kconfig
+++ b/board/bachmann/ot1200/Kconfig
@@ -10,4 +10,3 @@
default "ot1200"
endif
-
diff --git a/board/barco/platinum/Kconfig b/board/barco/platinum/Kconfig
index 85e3ef1..cc0648c 100644
--- a/board/barco/platinum/Kconfig
+++ b/board/barco/platinum/Kconfig
@@ -29,4 +29,3 @@
default "platinum_titanium"
endif
-
diff --git a/board/barco/titanium/Kconfig b/board/barco/titanium/Kconfig
index b596476..21bc36e 100644
--- a/board/barco/titanium/Kconfig
+++ b/board/barco/titanium/Kconfig
@@ -10,4 +10,3 @@
default "titanium"
endif
-
diff --git a/board/beckhoff/mx53cx9020/Kconfig b/board/beckhoff/mx53cx9020/Kconfig
index a62048e..dcdafb6 100644
--- a/board/beckhoff/mx53cx9020/Kconfig
+++ b/board/beckhoff/mx53cx9020/Kconfig
@@ -10,4 +10,3 @@
default "mx53cx9020"
endif
-
diff --git a/board/birdland/bav335x/Kconfig b/board/birdland/bav335x/Kconfig
index 5fd6bd6..4005366 100644
--- a/board/birdland/bav335x/Kconfig
+++ b/board/birdland/bav335x/Kconfig
@@ -21,4 +21,3 @@
Overwrite this if you have an older Rev.A and want ethernet support.
endif
-
diff --git a/board/bluegiga/apx4devkit/Kconfig b/board/bluegiga/apx4devkit/Kconfig
index d728779..f327fa1 100644
--- a/board/bluegiga/apx4devkit/Kconfig
+++ b/board/bluegiga/apx4devkit/Kconfig
@@ -13,4 +13,3 @@
default "apx4devkit"
endif
-
diff --git a/board/bluewater/gurnard/Kconfig b/board/bluewater/gurnard/Kconfig
index 4780c66..e2cd9f0 100644
--- a/board/bluewater/gurnard/Kconfig
+++ b/board/bluewater/gurnard/Kconfig
@@ -10,4 +10,3 @@
default "snapper9g45"
endif
-
diff --git a/board/bluewater/snapper9260/Kconfig b/board/bluewater/snapper9260/Kconfig
index a4e6ab7..b8e9cbc 100644
--- a/board/bluewater/snapper9260/Kconfig
+++ b/board/bluewater/snapper9260/Kconfig
@@ -10,4 +10,3 @@
default "snapper9260"
endif
-
diff --git a/board/bosch/shc/Kconfig b/board/bosch/shc/Kconfig
index 40d8f95..e0e56e6 100644
--- a/board/bosch/shc/Kconfig
+++ b/board/bosch/shc/Kconfig
@@ -85,4 +85,3 @@
endchoice
endif
-
diff --git a/board/boundary/nitrogen6x/Kconfig b/board/boundary/nitrogen6x/Kconfig
index 515aa8b..f4db56d 100644
--- a/board/boundary/nitrogen6x/Kconfig
+++ b/board/boundary/nitrogen6x/Kconfig
@@ -10,4 +10,3 @@
default "nitrogen6x"
endif
-
diff --git a/board/broadcom/bcm23550_w1d/Kconfig b/board/broadcom/bcm23550_w1d/Kconfig
index aa27222..007a127 100644
--- a/board/broadcom/bcm23550_w1d/Kconfig
+++ b/board/broadcom/bcm23550_w1d/Kconfig
@@ -13,4 +13,3 @@
default "bcm23550_w1d"
endif
-
diff --git a/board/broadcom/bcm28155_ap/Kconfig b/board/broadcom/bcm28155_ap/Kconfig
index 3935f2f..f1b4e08 100644
--- a/board/broadcom/bcm28155_ap/Kconfig
+++ b/board/broadcom/bcm28155_ap/Kconfig
@@ -13,4 +13,3 @@
default "bcm28155_ap"
endif
-
diff --git a/board/broadcom/bcm968380gerg/Kconfig b/board/broadcom/bcm968380gerg/Kconfig
index 0993025..c33e25d 100644
--- a/board/broadcom/bcm968380gerg/Kconfig
+++ b/board/broadcom/bcm968380gerg/Kconfig
@@ -10,4 +10,3 @@
default "broadcom_bcm968380gerg"
endif
-
diff --git a/board/broadcom/bcm968580xref/Kconfig b/board/broadcom/bcm968580xref/Kconfig
index e5b8ad3..b573036 100644
--- a/board/broadcom/bcm968580xref/Kconfig
+++ b/board/broadcom/bcm968580xref/Kconfig
@@ -15,4 +15,3 @@
bool "Support Broadcom bcm968580xref"
depends on ARCH_BCM6858
select ARM64
-
diff --git a/board/broadcom/bcmcygnus/Kconfig b/board/broadcom/bcmcygnus/Kconfig
index 2a9db2b..faba4cf 100644
--- a/board/broadcom/bcmcygnus/Kconfig
+++ b/board/broadcom/bcmcygnus/Kconfig
@@ -13,4 +13,3 @@
default "bcm_ep_board"
endif
-
diff --git a/board/broadcom/bcmns2/Kconfig b/board/broadcom/bcmns2/Kconfig
index 3bd13f1..3ac6724 100644
--- a/board/broadcom/bcmns2/Kconfig
+++ b/board/broadcom/bcmns2/Kconfig
@@ -13,4 +13,3 @@
default "bcm_northstar2"
endif
-
diff --git a/board/broadcom/bcmnsp/Kconfig b/board/broadcom/bcmnsp/Kconfig
index 75314cb..a975082 100644
--- a/board/broadcom/bcmnsp/Kconfig
+++ b/board/broadcom/bcmnsp/Kconfig
@@ -13,4 +13,3 @@
default "bcm_ep_board"
endif
-
diff --git a/board/bticino/mamoj/Kconfig b/board/bticino/mamoj/Kconfig
index fed4fad..e5aec58 100644
--- a/board/bticino/mamoj/Kconfig
+++ b/board/bticino/mamoj/Kconfig
@@ -10,4 +10,3 @@
default "imx6dl-mamoj"
endif
-
diff --git a/board/buffalo/lsxl/Kconfig b/board/buffalo/lsxl/Kconfig
index b5ec937..ef78896 100644
--- a/board/buffalo/lsxl/Kconfig
+++ b/board/buffalo/lsxl/Kconfig
@@ -10,4 +10,3 @@
default "lsxl"
endif
-
diff --git a/board/cadence/xtfpga/Kconfig b/board/cadence/xtfpga/Kconfig
index c14577d..69296be 100644
--- a/board/cadence/xtfpga/Kconfig
+++ b/board/cadence/xtfpga/Kconfig
@@ -37,4 +37,3 @@
default 0x38000000 if XTFPGA_KC705
endif
-
diff --git a/board/calao/usb_a9263/Kconfig b/board/calao/usb_a9263/Kconfig
index a1e8ec9..19e446d 100644
--- a/board/calao/usb_a9263/Kconfig
+++ b/board/calao/usb_a9263/Kconfig
@@ -10,4 +10,3 @@
default "usb_a9263"
endif
-
diff --git a/board/cavium/thunderx/Kconfig b/board/cavium/thunderx/Kconfig
index 7b45270..927d876 100644
--- a/board/cavium/thunderx/Kconfig
+++ b/board/cavium/thunderx/Kconfig
@@ -25,4 +25,3 @@
and node count.
endif
-
diff --git a/board/ccv/xpress/Kconfig b/board/ccv/xpress/Kconfig
index 0bcabf4..9157013 100644
--- a/board/ccv/xpress/Kconfig
+++ b/board/ccv/xpress/Kconfig
@@ -10,4 +10,3 @@
default "xpress"
endif
-
diff --git a/board/cei/cei-tk1-som/Kconfig b/board/cei/cei-tk1-som/Kconfig
index d962273..5fcb51f 100644
--- a/board/cei/cei-tk1-som/Kconfig
+++ b/board/cei/cei-tk1-som/Kconfig
@@ -10,4 +10,3 @@
default "cei-tk1-som"
endif
-
diff --git a/board/chipspark/popmetal_rk3288/Kconfig b/board/chipspark/popmetal_rk3288/Kconfig
index 11a0751..a5f4043 100644
--- a/board/chipspark/popmetal_rk3288/Kconfig
+++ b/board/chipspark/popmetal_rk3288/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/cirrus/edb93xx/Kconfig b/board/cirrus/edb93xx/Kconfig
index 49d035b..c5f4897 100644
--- a/board/cirrus/edb93xx/Kconfig
+++ b/board/cirrus/edb93xx/Kconfig
@@ -13,4 +13,3 @@
default "edb93xx"
endif
-
diff --git a/board/cloudengines/pogo_e02/Kconfig b/board/cloudengines/pogo_e02/Kconfig
index ec4d795..eaa68d9 100644
--- a/board/cloudengines/pogo_e02/Kconfig
+++ b/board/cloudengines/pogo_e02/Kconfig
@@ -10,4 +10,3 @@
default "pogo_e02"
endif
-
diff --git a/board/cobra5272/Kconfig b/board/cobra5272/Kconfig
index e31ad03..ba04622 100644
--- a/board/cobra5272/Kconfig
+++ b/board/cobra5272/Kconfig
@@ -10,4 +10,3 @@
default "cobra5272"
endif
-
diff --git a/board/compal/paz00/Kconfig b/board/compal/paz00/Kconfig
index 6679d5e..30ba11d 100644
--- a/board/compal/paz00/Kconfig
+++ b/board/compal/paz00/Kconfig
@@ -10,4 +10,3 @@
default "paz00"
endif
-
diff --git a/board/compulab/cl-som-am57x/Kconfig b/board/compulab/cl-som-am57x/Kconfig
index 05204a2..85fc9a1 100644
--- a/board/compulab/cl-som-am57x/Kconfig
+++ b/board/compulab/cl-som-am57x/Kconfig
@@ -10,4 +10,3 @@
default "cl-som-am57x"
endif
-
diff --git a/board/compulab/cl-som-imx7/Kconfig b/board/compulab/cl-som-imx7/Kconfig
index 2ee4785..6d69cf3 100644
--- a/board/compulab/cl-som-imx7/Kconfig
+++ b/board/compulab/cl-som-imx7/Kconfig
@@ -26,4 +26,3 @@
default 1
endif
-
diff --git a/board/compulab/cm_fx6/Kconfig b/board/compulab/cm_fx6/Kconfig
index fd49d08..59070c5 100644
--- a/board/compulab/cm_fx6/Kconfig
+++ b/board/compulab/cm_fx6/Kconfig
@@ -10,4 +10,3 @@
default "cm_fx6"
endif
-
diff --git a/board/compulab/cm_t335/Kconfig b/board/compulab/cm_t335/Kconfig
index 8d81a61..683efde 100644
--- a/board/compulab/cm_t335/Kconfig
+++ b/board/compulab/cm_t335/Kconfig
@@ -13,4 +13,3 @@
default "cm_t335"
endif
-
diff --git a/board/compulab/cm_t35/Kconfig b/board/compulab/cm_t35/Kconfig
index 78ab1b6..d87741f 100644
--- a/board/compulab/cm_t35/Kconfig
+++ b/board/compulab/cm_t35/Kconfig
@@ -10,4 +10,3 @@
default "cm_t35"
endif
-
diff --git a/board/compulab/cm_t3517/Kconfig b/board/compulab/cm_t3517/Kconfig
index 5e03c00..2f5473d 100644
--- a/board/compulab/cm_t3517/Kconfig
+++ b/board/compulab/cm_t3517/Kconfig
@@ -10,4 +10,3 @@
default "cm_t3517"
endif
-
diff --git a/board/compulab/cm_t43/Kconfig b/board/compulab/cm_t43/Kconfig
index 9cc0227..a191889 100644
--- a/board/compulab/cm_t43/Kconfig
+++ b/board/compulab/cm_t43/Kconfig
@@ -13,4 +13,3 @@
default "cm_t43"
endif
-
diff --git a/board/compulab/cm_t54/Kconfig b/board/compulab/cm_t54/Kconfig
index 2f9dde3..52d3880 100644
--- a/board/compulab/cm_t54/Kconfig
+++ b/board/compulab/cm_t54/Kconfig
@@ -10,4 +10,3 @@
default "cm_t54"
endif
-
diff --git a/board/compulab/trimslice/Kconfig b/board/compulab/trimslice/Kconfig
index 9d94017..3576914 100644
--- a/board/compulab/trimslice/Kconfig
+++ b/board/compulab/trimslice/Kconfig
@@ -10,4 +10,3 @@
default "trimslice"
endif
-
diff --git a/board/comtrend/ar5315u/Kconfig b/board/comtrend/ar5315u/Kconfig
index 1caa50e..4baae40 100644
--- a/board/comtrend/ar5315u/Kconfig
+++ b/board/comtrend/ar5315u/Kconfig
@@ -10,4 +10,3 @@
default "comtrend_ar5315u"
endif
-
diff --git a/board/comtrend/ar5387un/Kconfig b/board/comtrend/ar5387un/Kconfig
index 8d69376..45ab7e2 100644
--- a/board/comtrend/ar5387un/Kconfig
+++ b/board/comtrend/ar5387un/Kconfig
@@ -10,4 +10,3 @@
default "comtrend_ar5387un"
endif
-
diff --git a/board/comtrend/ct5361/Kconfig b/board/comtrend/ct5361/Kconfig
index b8a0b92..d77d814 100644
--- a/board/comtrend/ct5361/Kconfig
+++ b/board/comtrend/ct5361/Kconfig
@@ -10,4 +10,3 @@
default "comtrend_ct5361"
endif
-
diff --git a/board/comtrend/vr3032u/Kconfig b/board/comtrend/vr3032u/Kconfig
index b485ed4..6f552cf 100644
--- a/board/comtrend/vr3032u/Kconfig
+++ b/board/comtrend/vr3032u/Kconfig
@@ -10,4 +10,3 @@
default "comtrend_vr3032u"
endif
-
diff --git a/board/comtrend/wap5813n/Kconfig b/board/comtrend/wap5813n/Kconfig
index 774eea2..2f2a14f 100644
--- a/board/comtrend/wap5813n/Kconfig
+++ b/board/comtrend/wap5813n/Kconfig
@@ -10,4 +10,3 @@
default "comtrend_wap5813n"
endif
-
diff --git a/board/congatec/Kconfig b/board/congatec/Kconfig
index a2b9642..e9fa153 100644
--- a/board/congatec/Kconfig
+++ b/board/congatec/Kconfig
@@ -38,4 +38,3 @@
source "board/congatec/conga-qeval20-qa3-e3845/Kconfig"
endif
-
diff --git a/board/congatec/cgtqmx6eval/Kconfig b/board/congatec/cgtqmx6eval/Kconfig
index 6964871..773551b 100644
--- a/board/congatec/cgtqmx6eval/Kconfig
+++ b/board/congatec/cgtqmx6eval/Kconfig
@@ -10,4 +10,3 @@
default "cgtqmx6eval"
endif
-
diff --git a/board/congatec/conga-qeval20-qa3-e3845/Kconfig b/board/congatec/conga-qeval20-qa3-e3845/Kconfig
index 485253f..6469250 100644
--- a/board/congatec/conga-qeval20-qa3-e3845/Kconfig
+++ b/board/congatec/conga-qeval20-qa3-e3845/Kconfig
@@ -28,4 +28,3 @@
config PCIE_ECAM_BASE
default 0xe0000000
-
diff --git a/board/coreboot/Kconfig b/board/coreboot/Kconfig
index 3375a05..05a72d3 100644
--- a/board/coreboot/Kconfig
+++ b/board/coreboot/Kconfig
@@ -23,4 +23,3 @@
source "board/coreboot/coreboot/Kconfig"
endif
-
diff --git a/board/coreboot/coreboot/Kconfig b/board/coreboot/coreboot/Kconfig
index c5e036a..5bd6465 100644
--- a/board/coreboot/coreboot/Kconfig
+++ b/board/coreboot/coreboot/Kconfig
@@ -32,4 +32,3 @@
This option specifies the board specific Cache-As-RAM (CAR) size.
endif
-
diff --git a/board/corscience/tricorder/Kconfig b/board/corscience/tricorder/Kconfig
index e0c5ba5..345ac83 100644
--- a/board/corscience/tricorder/Kconfig
+++ b/board/corscience/tricorder/Kconfig
@@ -10,4 +10,3 @@
default "tricorder"
endif
-
diff --git a/board/creative/xfi3/Kconfig b/board/creative/xfi3/Kconfig
index a43e7d0..7b681cd 100644
--- a/board/creative/xfi3/Kconfig
+++ b/board/creative/xfi3/Kconfig
@@ -13,4 +13,3 @@
default "xfi3"
endif
-
diff --git a/board/cssi/MCR3000/Kconfig b/board/cssi/MCR3000/Kconfig
index 3478227..ecfd90f 100644
--- a/board/cssi/MCR3000/Kconfig
+++ b/board/cssi/MCR3000/Kconfig
@@ -13,4 +13,3 @@
default 0x04000000
endif
-
diff --git a/board/d-link/dns325/Kconfig b/board/d-link/dns325/Kconfig
index 1a5b10d..f6341ad 100644
--- a/board/d-link/dns325/Kconfig
+++ b/board/d-link/dns325/Kconfig
@@ -10,4 +10,3 @@
default "dns325"
endif
-
diff --git a/board/davinci/da8xxevm/Kconfig b/board/davinci/da8xxevm/Kconfig
index fcdcf1b..e0df97c 100644
--- a/board/davinci/da8xxevm/Kconfig
+++ b/board/davinci/da8xxevm/Kconfig
@@ -51,4 +51,3 @@
endif
source "board/ti/common/Kconfig"
-
diff --git a/board/davinci/ea20/Kconfig b/board/davinci/ea20/Kconfig
index 3d822ab..ae5b16e 100644
--- a/board/davinci/ea20/Kconfig
+++ b/board/davinci/ea20/Kconfig
@@ -10,4 +10,3 @@
default "ea20"
endif
-
diff --git a/board/dfi/Kconfig b/board/dfi/Kconfig
index 3b2faa2..267ac50 100644
--- a/board/dfi/Kconfig
+++ b/board/dfi/Kconfig
@@ -38,4 +38,3 @@
source "board/dfi/dfi-bt700/Kconfig"
endif
-
diff --git a/board/dfi/dfi-bt700/Kconfig b/board/dfi/dfi-bt700/Kconfig
index dbeb1b3..50c7b2a 100644
--- a/board/dfi/dfi-bt700/Kconfig
+++ b/board/dfi/dfi-bt700/Kconfig
@@ -28,4 +28,3 @@
config PCIE_ECAM_BASE
default 0xe0000000
-
diff --git a/board/dhelectronics/dh_imx6/Kconfig b/board/dhelectronics/dh_imx6/Kconfig
index b1a3b58..0cfef9b 100644
--- a/board/dhelectronics/dh_imx6/Kconfig
+++ b/board/dhelectronics/dh_imx6/Kconfig
@@ -10,4 +10,3 @@
default "dh_imx6"
endif
-
diff --git a/board/eets/pdu001/Kconfig b/board/eets/pdu001/Kconfig
index fbaf17b..e64ae28 100644
--- a/board/eets/pdu001/Kconfig
+++ b/board/eets/pdu001/Kconfig
@@ -48,4 +48,3 @@
endchoice
endif
-
diff --git a/board/efi/Kconfig b/board/efi/Kconfig
index c314826..291bd2c 100644
--- a/board/efi/Kconfig
+++ b/board/efi/Kconfig
@@ -26,4 +26,3 @@
source "board/efi/efi-x86_payload/Kconfig"
endif
-
diff --git a/board/efi/efi-x86_app/Kconfig b/board/efi/efi-x86_app/Kconfig
index 019b464..ae87bf3 100644
--- a/board/efi/efi-x86_app/Kconfig
+++ b/board/efi/efi-x86_app/Kconfig
@@ -13,4 +13,3 @@
default "efi-x86_app"
endif
-
diff --git a/board/efi/efi-x86_payload/Kconfig b/board/efi/efi-x86_payload/Kconfig
index 547d8e8..08dd0c2 100644
--- a/board/efi/efi-x86_payload/Kconfig
+++ b/board/efi/efi-x86_payload/Kconfig
@@ -38,4 +38,3 @@
imply RTL8169
endif
-
diff --git a/board/egnite/ethernut5/Kconfig b/board/egnite/ethernut5/Kconfig
index 54b1f5a..5a6c1c5 100644
--- a/board/egnite/ethernut5/Kconfig
+++ b/board/egnite/ethernut5/Kconfig
@@ -10,4 +10,3 @@
default "ethernut5"
endif
-
diff --git a/board/el/el6x/Kconfig b/board/el/el6x/Kconfig
index 1b9cd97..aa9bf25 100644
--- a/board/el/el6x/Kconfig
+++ b/board/el/el6x/Kconfig
@@ -23,4 +23,3 @@
default "zc5601"
endif
-
diff --git a/board/elgin/elgin_rv1108/Kconfig b/board/elgin/elgin_rv1108/Kconfig
index 904c21d..be92431 100644
--- a/board/elgin/elgin_rv1108/Kconfig
+++ b/board/elgin/elgin_rv1108/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/embest/mx6boards/Kconfig b/board/embest/mx6boards/Kconfig
index b73429e..24d01f2 100644
--- a/board/embest/mx6boards/Kconfig
+++ b/board/embest/mx6boards/Kconfig
@@ -10,4 +10,3 @@
default "embestmx6boards"
endif
-
diff --git a/board/emulation/Kconfig b/board/emulation/Kconfig
index bc9a457..f821458 100644
--- a/board/emulation/Kconfig
+++ b/board/emulation/Kconfig
@@ -28,4 +28,3 @@
source "board/emulation/qemu-x86/Kconfig"
endif
-
diff --git a/board/emulation/qemu-arm/Kconfig b/board/emulation/qemu-arm/Kconfig
index 5f74455..02ae4d9 100644
--- a/board/emulation/qemu-arm/Kconfig
+++ b/board/emulation/qemu-arm/Kconfig
@@ -11,4 +11,3 @@
imply VIRTIO_BLK
endif
-
diff --git a/board/emulation/qemu-riscv/Kconfig b/board/emulation/qemu-riscv/Kconfig
index 0eade10..0d865ac 100644
--- a/board/emulation/qemu-riscv/Kconfig
+++ b/board/emulation/qemu-riscv/Kconfig
@@ -36,4 +36,3 @@
imply SIFIVE_SERIAL
endif
-
diff --git a/board/emulation/qemu-x86/Kconfig b/board/emulation/qemu-x86/Kconfig
index 0a0d096..6d19299 100644
--- a/board/emulation/qemu-x86/Kconfig
+++ b/board/emulation/qemu-x86/Kconfig
@@ -26,4 +26,3 @@
imply VIRTIO_BLK
endif
-
diff --git a/board/engicam/imx6q/Kconfig b/board/engicam/imx6q/Kconfig
index 6a0dbcb..48eb60c 100644
--- a/board/engicam/imx6q/Kconfig
+++ b/board/engicam/imx6q/Kconfig
@@ -10,4 +10,3 @@
default "imx6-engicam"
endif
-
diff --git a/board/engicam/imx6ul/Kconfig b/board/engicam/imx6ul/Kconfig
index a55cb2c..e91dd15 100644
--- a/board/engicam/imx6ul/Kconfig
+++ b/board/engicam/imx6ul/Kconfig
@@ -10,4 +10,3 @@
default "imx6-engicam"
endif
-
diff --git a/board/esd/meesc/Kconfig b/board/esd/meesc/Kconfig
index 3385df7..150348a 100644
--- a/board/esd/meesc/Kconfig
+++ b/board/esd/meesc/Kconfig
@@ -10,4 +10,3 @@
default "meesc"
endif
-
diff --git a/board/esd/vme8349/Kconfig b/board/esd/vme8349/Kconfig
index d2c1ea6..b8d9432 100644
--- a/board/esd/vme8349/Kconfig
+++ b/board/esd/vme8349/Kconfig
@@ -10,4 +10,3 @@
default "vme8349"
endif
-
diff --git a/board/espt/Kconfig b/board/espt/Kconfig
index 1f9c42d..0294926 100644
--- a/board/espt/Kconfig
+++ b/board/espt/Kconfig
@@ -7,4 +7,3 @@
default "espt"
endif
-
diff --git a/board/firefly/firefly-rk3288/Kconfig b/board/firefly/firefly-rk3288/Kconfig
index 99ba112..1c2bca8 100644
--- a/board/firefly/firefly-rk3288/Kconfig
+++ b/board/firefly/firefly-rk3288/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/freescale/b4860qds/Kconfig b/board/freescale/b4860qds/Kconfig
index 7374863..9bb667a 100644
--- a/board/freescale/b4860qds/Kconfig
+++ b/board/freescale/b4860qds/Kconfig
@@ -12,4 +12,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/bsc9131rdb/Kconfig b/board/freescale/bsc9131rdb/Kconfig
index 2199935..dd9f765 100644
--- a/board/freescale/bsc9131rdb/Kconfig
+++ b/board/freescale/bsc9131rdb/Kconfig
@@ -10,4 +10,3 @@
default "BSC9131RDB"
endif
-
diff --git a/board/freescale/bsc9132qds/Kconfig b/board/freescale/bsc9132qds/Kconfig
index fa67fb1..e5499e6 100644
--- a/board/freescale/bsc9132qds/Kconfig
+++ b/board/freescale/bsc9132qds/Kconfig
@@ -12,4 +12,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/c29xpcie/Kconfig b/board/freescale/c29xpcie/Kconfig
index 4b1dd91..51e25c3 100644
--- a/board/freescale/c29xpcie/Kconfig
+++ b/board/freescale/c29xpcie/Kconfig
@@ -12,4 +12,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/common/Kconfig b/board/freescale/common/Kconfig
index 622181b..8b89c10 100644
--- a/board/freescale/common/Kconfig
+++ b/board/freescale/common/Kconfig
@@ -36,4 +36,3 @@
help
This option enables LTC3882 voltage monitor set
functionality. It is used by common VID driver.
-
diff --git a/board/freescale/corenet_ds/Kconfig b/board/freescale/corenet_ds/Kconfig
index f26e132..98b1add 100644
--- a/board/freescale/corenet_ds/Kconfig
+++ b/board/freescale/corenet_ds/Kconfig
@@ -57,4 +57,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/imx8mq_evk/Kconfig b/board/freescale/imx8mq_evk/Kconfig
index 20847a0..421b081 100644
--- a/board/freescale/imx8mq_evk/Kconfig
+++ b/board/freescale/imx8mq_evk/Kconfig
@@ -10,4 +10,3 @@
default "imx8mq_evk"
endif
-
diff --git a/board/freescale/imx8qxp_mek/Kconfig b/board/freescale/imx8qxp_mek/Kconfig
index d450255..b67300d 100644
--- a/board/freescale/imx8qxp_mek/Kconfig
+++ b/board/freescale/imx8qxp_mek/Kconfig
@@ -12,4 +12,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/ls1012afrdm/Kconfig b/board/freescale/ls1012afrdm/Kconfig
index 5468022..55b414e 100644
--- a/board/freescale/ls1012afrdm/Kconfig
+++ b/board/freescale/ls1012afrdm/Kconfig
@@ -82,4 +82,3 @@
if TARGET_LS1012AFRDM || TARGET_LS1012AFRWY
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/ls1012aqds/Kconfig b/board/freescale/ls1012aqds/Kconfig
index cd1dda0..8844557 100644
--- a/board/freescale/ls1012aqds/Kconfig
+++ b/board/freescale/ls1012aqds/Kconfig
@@ -73,4 +73,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/ls1012ardb/Kconfig b/board/freescale/ls1012ardb/Kconfig
index f8d1d77..51efd0f 100644
--- a/board/freescale/ls1012ardb/Kconfig
+++ b/board/freescale/ls1012ardb/Kconfig
@@ -110,4 +110,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/ls1021aiot/Kconfig b/board/freescale/ls1021aiot/Kconfig
index 030f0e7..c6b1606 100644
--- a/board/freescale/ls1021aiot/Kconfig
+++ b/board/freescale/ls1021aiot/Kconfig
@@ -15,4 +15,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/ls1021aqds/Kconfig b/board/freescale/ls1021aqds/Kconfig
index 7f7e45f..60b8472 100644
--- a/board/freescale/ls1021aqds/Kconfig
+++ b/board/freescale/ls1021aqds/Kconfig
@@ -15,4 +15,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/ls1021atwr/Kconfig b/board/freescale/ls1021atwr/Kconfig
index aa974ea..a4641cb 100644
--- a/board/freescale/ls1021atwr/Kconfig
+++ b/board/freescale/ls1021atwr/Kconfig
@@ -15,4 +15,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/ls1043aqds/Kconfig b/board/freescale/ls1043aqds/Kconfig
index 5341565..182900e 100644
--- a/board/freescale/ls1043aqds/Kconfig
+++ b/board/freescale/ls1043aqds/Kconfig
@@ -31,4 +31,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/ls1043ardb/Kconfig b/board/freescale/ls1043ardb/Kconfig
index 8eabccb..3d9e295 100644
--- a/board/freescale/ls1043ardb/Kconfig
+++ b/board/freescale/ls1043ardb/Kconfig
@@ -39,4 +39,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/ls1046aqds/Kconfig b/board/freescale/ls1046aqds/Kconfig
index 43e5fcb..1616dcc 100644
--- a/board/freescale/ls1046aqds/Kconfig
+++ b/board/freescale/ls1046aqds/Kconfig
@@ -31,4 +31,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/ls1046ardb/Kconfig b/board/freescale/ls1046ardb/Kconfig
index 56b9671..4c31e0e 100644
--- a/board/freescale/ls1046ardb/Kconfig
+++ b/board/freescale/ls1046ardb/Kconfig
@@ -29,4 +29,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/ls1088a/Kconfig b/board/freescale/ls1088a/Kconfig
index d704bf7..8bb828e 100644
--- a/board/freescale/ls1088a/Kconfig
+++ b/board/freescale/ls1088a/Kconfig
@@ -59,4 +59,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/ls2080a/Kconfig b/board/freescale/ls2080a/Kconfig
index c8bc8cd..b503351 100644
--- a/board/freescale/ls2080a/Kconfig
+++ b/board/freescale/ls2080a/Kconfig
@@ -33,4 +33,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/ls2080aqds/Kconfig b/board/freescale/ls2080aqds/Kconfig
index 6def848..6b2b645 100644
--- a/board/freescale/ls2080aqds/Kconfig
+++ b/board/freescale/ls2080aqds/Kconfig
@@ -32,4 +32,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/ls2080ardb/Kconfig b/board/freescale/ls2080ardb/Kconfig
index cdd46e8..678d582 100644
--- a/board/freescale/ls2080ardb/Kconfig
+++ b/board/freescale/ls2080ardb/Kconfig
@@ -33,4 +33,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/m5208evbe/Kconfig b/board/freescale/m5208evbe/Kconfig
index faba632..9b416af 100644
--- a/board/freescale/m5208evbe/Kconfig
+++ b/board/freescale/m5208evbe/Kconfig
@@ -13,4 +13,3 @@
default "M5208EVBE"
endif
-
diff --git a/board/freescale/m52277evb/Kconfig b/board/freescale/m52277evb/Kconfig
index 0279e48..c427892 100644
--- a/board/freescale/m52277evb/Kconfig
+++ b/board/freescale/m52277evb/Kconfig
@@ -13,4 +13,3 @@
default "M52277EVB"
endif
-
diff --git a/board/freescale/m5235evb/Kconfig b/board/freescale/m5235evb/Kconfig
index 73fe30f..fc83419 100644
--- a/board/freescale/m5235evb/Kconfig
+++ b/board/freescale/m5235evb/Kconfig
@@ -13,4 +13,3 @@
default "M5235EVB"
endif
-
diff --git a/board/freescale/m5249evb/Kconfig b/board/freescale/m5249evb/Kconfig
index 1ca996a..0f62477 100644
--- a/board/freescale/m5249evb/Kconfig
+++ b/board/freescale/m5249evb/Kconfig
@@ -13,4 +13,3 @@
default "M5249EVB"
endif
-
diff --git a/board/freescale/m5253demo/Kconfig b/board/freescale/m5253demo/Kconfig
index 3e70d05..303d29b 100644
--- a/board/freescale/m5253demo/Kconfig
+++ b/board/freescale/m5253demo/Kconfig
@@ -13,4 +13,3 @@
default "M5253DEMO"
endif
-
diff --git a/board/freescale/m5272c3/Kconfig b/board/freescale/m5272c3/Kconfig
index deb9b13..aee0b23 100644
--- a/board/freescale/m5272c3/Kconfig
+++ b/board/freescale/m5272c3/Kconfig
@@ -13,4 +13,3 @@
default "M5272C3"
endif
-
diff --git a/board/freescale/m5275evb/Kconfig b/board/freescale/m5275evb/Kconfig
index 43afcbc..5a6de9c 100644
--- a/board/freescale/m5275evb/Kconfig
+++ b/board/freescale/m5275evb/Kconfig
@@ -13,4 +13,3 @@
default "M5275EVB"
endif
-
diff --git a/board/freescale/m5282evb/Kconfig b/board/freescale/m5282evb/Kconfig
index 640e018..2ffdd52 100644
--- a/board/freescale/m5282evb/Kconfig
+++ b/board/freescale/m5282evb/Kconfig
@@ -13,4 +13,3 @@
default "M5282EVB"
endif
-
diff --git a/board/freescale/m53017evb/Kconfig b/board/freescale/m53017evb/Kconfig
index 2f2d112..8ab89e5 100644
--- a/board/freescale/m53017evb/Kconfig
+++ b/board/freescale/m53017evb/Kconfig
@@ -13,4 +13,3 @@
default "M53017EVB"
endif
-
diff --git a/board/freescale/m5329evb/Kconfig b/board/freescale/m5329evb/Kconfig
index ec2fe8c..930fbba 100644
--- a/board/freescale/m5329evb/Kconfig
+++ b/board/freescale/m5329evb/Kconfig
@@ -13,4 +13,3 @@
default "M5329EVB"
endif
-
diff --git a/board/freescale/m5373evb/Kconfig b/board/freescale/m5373evb/Kconfig
index d054ffd..67d049d 100644
--- a/board/freescale/m5373evb/Kconfig
+++ b/board/freescale/m5373evb/Kconfig
@@ -13,4 +13,3 @@
default "M5373EVB"
endif
-
diff --git a/board/freescale/m54418twr/Kconfig b/board/freescale/m54418twr/Kconfig
index 3d84870..4199a3f 100644
--- a/board/freescale/m54418twr/Kconfig
+++ b/board/freescale/m54418twr/Kconfig
@@ -13,4 +13,3 @@
default "M54418TWR"
endif
-
diff --git a/board/freescale/m54451evb/Kconfig b/board/freescale/m54451evb/Kconfig
index 18d958a..f460e51 100644
--- a/board/freescale/m54451evb/Kconfig
+++ b/board/freescale/m54451evb/Kconfig
@@ -13,4 +13,3 @@
default "M54451EVB"
endif
-
diff --git a/board/freescale/m54455evb/Kconfig b/board/freescale/m54455evb/Kconfig
index 7e6fc21..096bce8 100644
--- a/board/freescale/m54455evb/Kconfig
+++ b/board/freescale/m54455evb/Kconfig
@@ -13,4 +13,3 @@
default "M54455EVB"
endif
-
diff --git a/board/freescale/m547xevb/Kconfig b/board/freescale/m547xevb/Kconfig
index f61f60b..8cfe20a 100644
--- a/board/freescale/m547xevb/Kconfig
+++ b/board/freescale/m547xevb/Kconfig
@@ -13,4 +13,3 @@
default "M5475EVB"
endif
-
diff --git a/board/freescale/m548xevb/Kconfig b/board/freescale/m548xevb/Kconfig
index ce25f9d..da924e3 100644
--- a/board/freescale/m548xevb/Kconfig
+++ b/board/freescale/m548xevb/Kconfig
@@ -13,4 +13,3 @@
default "M5485EVB"
endif
-
diff --git a/board/freescale/mpc8308rdb/Kconfig b/board/freescale/mpc8308rdb/Kconfig
index 7fd4a86..48d25e5 100644
--- a/board/freescale/mpc8308rdb/Kconfig
+++ b/board/freescale/mpc8308rdb/Kconfig
@@ -10,4 +10,3 @@
default "MPC8308RDB"
endif
-
diff --git a/board/freescale/mpc8313erdb/Kconfig b/board/freescale/mpc8313erdb/Kconfig
index a4a6916..145608f 100644
--- a/board/freescale/mpc8313erdb/Kconfig
+++ b/board/freescale/mpc8313erdb/Kconfig
@@ -10,4 +10,3 @@
default "MPC8313ERDB"
endif
-
diff --git a/board/freescale/mpc8315erdb/Kconfig b/board/freescale/mpc8315erdb/Kconfig
index 032831f..f76b0d1 100644
--- a/board/freescale/mpc8315erdb/Kconfig
+++ b/board/freescale/mpc8315erdb/Kconfig
@@ -10,4 +10,3 @@
default "MPC8315ERDB"
endif
-
diff --git a/board/freescale/mpc8323erdb/Kconfig b/board/freescale/mpc8323erdb/Kconfig
index 9042912..acf8122 100644
--- a/board/freescale/mpc8323erdb/Kconfig
+++ b/board/freescale/mpc8323erdb/Kconfig
@@ -10,4 +10,3 @@
default "MPC8323ERDB"
endif
-
diff --git a/board/freescale/mpc832xemds/Kconfig b/board/freescale/mpc832xemds/Kconfig
index 0a4f293..e4cfa15 100644
--- a/board/freescale/mpc832xemds/Kconfig
+++ b/board/freescale/mpc832xemds/Kconfig
@@ -10,4 +10,3 @@
default "MPC832XEMDS"
endif
-
diff --git a/board/freescale/mpc8349emds/Kconfig b/board/freescale/mpc8349emds/Kconfig
index 8d5df30..51f0b34 100644
--- a/board/freescale/mpc8349emds/Kconfig
+++ b/board/freescale/mpc8349emds/Kconfig
@@ -10,4 +10,3 @@
default "MPC8349EMDS"
endif
-
diff --git a/board/freescale/mpc8349itx/Kconfig b/board/freescale/mpc8349itx/Kconfig
index 86f8b87..ce3fffd 100644
--- a/board/freescale/mpc8349itx/Kconfig
+++ b/board/freescale/mpc8349itx/Kconfig
@@ -10,4 +10,3 @@
default "MPC8349ITX"
endif
-
diff --git a/board/freescale/mpc837xemds/Kconfig b/board/freescale/mpc837xemds/Kconfig
index 03c53b5..20d29db 100644
--- a/board/freescale/mpc837xemds/Kconfig
+++ b/board/freescale/mpc837xemds/Kconfig
@@ -10,4 +10,3 @@
default "MPC837XEMDS"
endif
-
diff --git a/board/freescale/mpc837xerdb/Kconfig b/board/freescale/mpc837xerdb/Kconfig
index 257950c..03415f9 100644
--- a/board/freescale/mpc837xerdb/Kconfig
+++ b/board/freescale/mpc837xerdb/Kconfig
@@ -10,4 +10,3 @@
default "MPC837XERDB"
endif
-
diff --git a/board/freescale/mpc8536ds/Kconfig b/board/freescale/mpc8536ds/Kconfig
index 416746b..1a6a9d4 100644
--- a/board/freescale/mpc8536ds/Kconfig
+++ b/board/freescale/mpc8536ds/Kconfig
@@ -10,4 +10,3 @@
default "MPC8536DS"
endif
-
diff --git a/board/freescale/mpc8541cds/Kconfig b/board/freescale/mpc8541cds/Kconfig
index 5fe171b..034eab2 100644
--- a/board/freescale/mpc8541cds/Kconfig
+++ b/board/freescale/mpc8541cds/Kconfig
@@ -10,4 +10,3 @@
default "MPC8541CDS"
endif
-
diff --git a/board/freescale/mpc8544ds/Kconfig b/board/freescale/mpc8544ds/Kconfig
index 757ff5c..c3e25b8 100644
--- a/board/freescale/mpc8544ds/Kconfig
+++ b/board/freescale/mpc8544ds/Kconfig
@@ -10,4 +10,3 @@
default "MPC8544DS"
endif
-
diff --git a/board/freescale/mpc8548cds/Kconfig b/board/freescale/mpc8548cds/Kconfig
index f7304e4..09f3b0b 100644
--- a/board/freescale/mpc8548cds/Kconfig
+++ b/board/freescale/mpc8548cds/Kconfig
@@ -10,4 +10,3 @@
default "MPC8548CDS"
endif
-
diff --git a/board/freescale/mpc8555cds/Kconfig b/board/freescale/mpc8555cds/Kconfig
index 36ad619..04bd572 100644
--- a/board/freescale/mpc8555cds/Kconfig
+++ b/board/freescale/mpc8555cds/Kconfig
@@ -10,4 +10,3 @@
default "MPC8555CDS"
endif
-
diff --git a/board/freescale/mpc8568mds/Kconfig b/board/freescale/mpc8568mds/Kconfig
index 112538d..4e178c5 100644
--- a/board/freescale/mpc8568mds/Kconfig
+++ b/board/freescale/mpc8568mds/Kconfig
@@ -10,4 +10,3 @@
default "MPC8568MDS"
endif
-
diff --git a/board/freescale/mpc8569mds/Kconfig b/board/freescale/mpc8569mds/Kconfig
index 6e31edc..4871857 100644
--- a/board/freescale/mpc8569mds/Kconfig
+++ b/board/freescale/mpc8569mds/Kconfig
@@ -10,4 +10,3 @@
default "MPC8569MDS"
endif
-
diff --git a/board/freescale/mpc8572ds/Kconfig b/board/freescale/mpc8572ds/Kconfig
index 9cb08b7..38132cf 100644
--- a/board/freescale/mpc8572ds/Kconfig
+++ b/board/freescale/mpc8572ds/Kconfig
@@ -10,4 +10,3 @@
default "MPC8572DS"
endif
-
diff --git a/board/freescale/mpc8610hpcd/Kconfig b/board/freescale/mpc8610hpcd/Kconfig
index 2e9b919..8f713be 100644
--- a/board/freescale/mpc8610hpcd/Kconfig
+++ b/board/freescale/mpc8610hpcd/Kconfig
@@ -10,4 +10,3 @@
default "MPC8610HPCD"
endif
-
diff --git a/board/freescale/mpc8641hpcn/Kconfig b/board/freescale/mpc8641hpcn/Kconfig
index 1c3a1de..ae45d63 100644
--- a/board/freescale/mpc8641hpcn/Kconfig
+++ b/board/freescale/mpc8641hpcn/Kconfig
@@ -10,4 +10,3 @@
default "MPC8641HPCN"
endif
-
diff --git a/board/freescale/mx23evk/Kconfig b/board/freescale/mx23evk/Kconfig
index 9366187..51a8f9f 100644
--- a/board/freescale/mx23evk/Kconfig
+++ b/board/freescale/mx23evk/Kconfig
@@ -13,4 +13,3 @@
default "mx23evk"
endif
-
diff --git a/board/freescale/mx25pdk/Kconfig b/board/freescale/mx25pdk/Kconfig
index bcb6e21..af06b4c 100644
--- a/board/freescale/mx25pdk/Kconfig
+++ b/board/freescale/mx25pdk/Kconfig
@@ -13,4 +13,3 @@
default "mx25pdk"
endif
-
diff --git a/board/freescale/mx28evk/Kconfig b/board/freescale/mx28evk/Kconfig
index 0324c4a..39777bd 100644
--- a/board/freescale/mx28evk/Kconfig
+++ b/board/freescale/mx28evk/Kconfig
@@ -13,4 +13,3 @@
default "mx28evk"
endif
-
diff --git a/board/freescale/mx31pdk/Kconfig b/board/freescale/mx31pdk/Kconfig
index 92c8c83..b9fc2d5 100644
--- a/board/freescale/mx31pdk/Kconfig
+++ b/board/freescale/mx31pdk/Kconfig
@@ -16,4 +16,3 @@
default "mx31pdk"
endif
-
diff --git a/board/freescale/mx35pdk/Kconfig b/board/freescale/mx35pdk/Kconfig
index f649e29..021d19e 100644
--- a/board/freescale/mx35pdk/Kconfig
+++ b/board/freescale/mx35pdk/Kconfig
@@ -13,4 +13,3 @@
default "mx35pdk"
endif
-
diff --git a/board/freescale/mx51evk/Kconfig b/board/freescale/mx51evk/Kconfig
index 19a7a3b..f9b69cb 100644
--- a/board/freescale/mx51evk/Kconfig
+++ b/board/freescale/mx51evk/Kconfig
@@ -13,4 +13,3 @@
default "mx51evk"
endif
-
diff --git a/board/freescale/mx53ard/Kconfig b/board/freescale/mx53ard/Kconfig
index 9ecffd8..41f46a0 100644
--- a/board/freescale/mx53ard/Kconfig
+++ b/board/freescale/mx53ard/Kconfig
@@ -13,4 +13,3 @@
default "mx53ard"
endif
-
diff --git a/board/freescale/mx53evk/Kconfig b/board/freescale/mx53evk/Kconfig
index ceb137e..c226c1c 100644
--- a/board/freescale/mx53evk/Kconfig
+++ b/board/freescale/mx53evk/Kconfig
@@ -13,4 +13,3 @@
default "mx53evk"
endif
-
diff --git a/board/freescale/mx53loco/Kconfig b/board/freescale/mx53loco/Kconfig
index 8df277b..5ca1672 100644
--- a/board/freescale/mx53loco/Kconfig
+++ b/board/freescale/mx53loco/Kconfig
@@ -13,4 +13,3 @@
default "mx53loco"
endif
-
diff --git a/board/freescale/mx53smd/Kconfig b/board/freescale/mx53smd/Kconfig
index fcf6679..1195d33 100644
--- a/board/freescale/mx53smd/Kconfig
+++ b/board/freescale/mx53smd/Kconfig
@@ -13,4 +13,3 @@
default "mx53smd"
endif
-
diff --git a/board/freescale/mx6qarm2/Kconfig b/board/freescale/mx6qarm2/Kconfig
index 69f4f26..8ab8b46 100644
--- a/board/freescale/mx6qarm2/Kconfig
+++ b/board/freescale/mx6qarm2/Kconfig
@@ -10,4 +10,3 @@
default "mx6qarm2"
endif
-
diff --git a/board/freescale/mx6sabreauto/Kconfig b/board/freescale/mx6sabreauto/Kconfig
index 0ebc6d3..5b4faf6 100644
--- a/board/freescale/mx6sabreauto/Kconfig
+++ b/board/freescale/mx6sabreauto/Kconfig
@@ -10,4 +10,3 @@
default "mx6sabreauto"
endif
-
diff --git a/board/freescale/mx6sabresd/Kconfig b/board/freescale/mx6sabresd/Kconfig
index d66b7c1..e87dea0 100644
--- a/board/freescale/mx6sabresd/Kconfig
+++ b/board/freescale/mx6sabresd/Kconfig
@@ -10,4 +10,3 @@
default "mx6sabresd"
endif
-
diff --git a/board/freescale/mx6slevk/Kconfig b/board/freescale/mx6slevk/Kconfig
index 37d3f38..18482b5 100644
--- a/board/freescale/mx6slevk/Kconfig
+++ b/board/freescale/mx6slevk/Kconfig
@@ -10,4 +10,3 @@
default "mx6slevk"
endif
-
diff --git a/board/freescale/mx6sllevk/Kconfig b/board/freescale/mx6sllevk/Kconfig
index 3174a22..4ba9bbf 100644
--- a/board/freescale/mx6sllevk/Kconfig
+++ b/board/freescale/mx6sllevk/Kconfig
@@ -10,4 +10,3 @@
default "mx6sllevk"
endif
-
diff --git a/board/freescale/mx6sxsabreauto/Kconfig b/board/freescale/mx6sxsabreauto/Kconfig
index 273c1c1..ae2ea02 100644
--- a/board/freescale/mx6sxsabreauto/Kconfig
+++ b/board/freescale/mx6sxsabreauto/Kconfig
@@ -10,4 +10,3 @@
default "mx6sxsabreauto"
endif
-
diff --git a/board/freescale/mx6sxsabresd/Kconfig b/board/freescale/mx6sxsabresd/Kconfig
index b09fb54..fcfac0a 100644
--- a/board/freescale/mx6sxsabresd/Kconfig
+++ b/board/freescale/mx6sxsabresd/Kconfig
@@ -10,4 +10,3 @@
default "mx6sxsabresd"
endif
-
diff --git a/board/freescale/mx6ul_14x14_evk/Kconfig b/board/freescale/mx6ul_14x14_evk/Kconfig
index 0f8d0b7..8210cd3 100644
--- a/board/freescale/mx6ul_14x14_evk/Kconfig
+++ b/board/freescale/mx6ul_14x14_evk/Kconfig
@@ -10,4 +10,3 @@
default "mx6ul_14x14_evk"
endif
-
diff --git a/board/freescale/mx6ullevk/Kconfig b/board/freescale/mx6ullevk/Kconfig
index 3d5ed35..7eec497 100644
--- a/board/freescale/mx6ullevk/Kconfig
+++ b/board/freescale/mx6ullevk/Kconfig
@@ -10,4 +10,3 @@
default "mx6ullevk"
endif
-
diff --git a/board/freescale/mx7dsabresd/Kconfig b/board/freescale/mx7dsabresd/Kconfig
index aaa1b9f..c6a969c 100644
--- a/board/freescale/mx7dsabresd/Kconfig
+++ b/board/freescale/mx7dsabresd/Kconfig
@@ -10,4 +10,3 @@
default "mx7dsabresd"
endif
-
diff --git a/board/freescale/mx7ulp_evk/Kconfig b/board/freescale/mx7ulp_evk/Kconfig
index a3efba9..ff44831 100644
--- a/board/freescale/mx7ulp_evk/Kconfig
+++ b/board/freescale/mx7ulp_evk/Kconfig
@@ -10,4 +10,3 @@
default "mx7ulp_evk"
endif
-
diff --git a/board/freescale/p1010rdb/Kconfig b/board/freescale/p1010rdb/Kconfig
index cb419b2..3adac4a 100644
--- a/board/freescale/p1010rdb/Kconfig
+++ b/board/freescale/p1010rdb/Kconfig
@@ -12,4 +12,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/p1022ds/Kconfig b/board/freescale/p1022ds/Kconfig
index d29efa3..f1792de 100644
--- a/board/freescale/p1022ds/Kconfig
+++ b/board/freescale/p1022ds/Kconfig
@@ -10,4 +10,3 @@
default "P1022DS"
endif
-
diff --git a/board/freescale/p1023rdb/Kconfig b/board/freescale/p1023rdb/Kconfig
index 770d00f..1e4cd10 100644
--- a/board/freescale/p1023rdb/Kconfig
+++ b/board/freescale/p1023rdb/Kconfig
@@ -10,4 +10,3 @@
default "P1023RDB"
endif
-
diff --git a/board/freescale/p1_p2_rdb_pc/Kconfig b/board/freescale/p1_p2_rdb_pc/Kconfig
index e8f33b1..2f9640b 100644
--- a/board/freescale/p1_p2_rdb_pc/Kconfig
+++ b/board/freescale/p1_p2_rdb_pc/Kconfig
@@ -17,4 +17,3 @@
default "p1_p2_rdb_pc"
endif
-
diff --git a/board/freescale/p1_twr/Kconfig b/board/freescale/p1_twr/Kconfig
index 649f637..8f9a8d4 100644
--- a/board/freescale/p1_twr/Kconfig
+++ b/board/freescale/p1_twr/Kconfig
@@ -10,4 +10,3 @@
default "p1_twr"
endif
-
diff --git a/board/freescale/p2041rdb/Kconfig b/board/freescale/p2041rdb/Kconfig
index 2d03398..7e187dd 100644
--- a/board/freescale/p2041rdb/Kconfig
+++ b/board/freescale/p2041rdb/Kconfig
@@ -12,4 +12,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/qemu-ppce500/Kconfig b/board/freescale/qemu-ppce500/Kconfig
index 2e7aace..236cd17 100644
--- a/board/freescale/qemu-ppce500/Kconfig
+++ b/board/freescale/qemu-ppce500/Kconfig
@@ -10,4 +10,3 @@
default "qemu-ppce500"
endif
-
diff --git a/board/freescale/s32v234evb/Kconfig b/board/freescale/s32v234evb/Kconfig
index ec887af..e71dfc4 100644
--- a/board/freescale/s32v234evb/Kconfig
+++ b/board/freescale/s32v234evb/Kconfig
@@ -21,4 +21,3 @@
default "s32v234evb"
endif
-
diff --git a/board/freescale/t102xqds/Kconfig b/board/freescale/t102xqds/Kconfig
index 92f0e22..87818a8 100644
--- a/board/freescale/t102xqds/Kconfig
+++ b/board/freescale/t102xqds/Kconfig
@@ -12,4 +12,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/t102xrdb/Kconfig b/board/freescale/t102xrdb/Kconfig
index c4f7632..6deeb24 100644
--- a/board/freescale/t102xrdb/Kconfig
+++ b/board/freescale/t102xrdb/Kconfig
@@ -12,4 +12,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/t1040qds/Kconfig b/board/freescale/t1040qds/Kconfig
index f8a3f34..ec3ff0c 100644
--- a/board/freescale/t1040qds/Kconfig
+++ b/board/freescale/t1040qds/Kconfig
@@ -12,4 +12,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/t104xrdb/Kconfig b/board/freescale/t104xrdb/Kconfig
index 9fe35c3..e6e46fa 100644
--- a/board/freescale/t104xrdb/Kconfig
+++ b/board/freescale/t104xrdb/Kconfig
@@ -14,4 +14,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/t208xqds/Kconfig b/board/freescale/t208xqds/Kconfig
index 63a4a0c..5a435c2 100644
--- a/board/freescale/t208xqds/Kconfig
+++ b/board/freescale/t208xqds/Kconfig
@@ -12,4 +12,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/t208xrdb/Kconfig b/board/freescale/t208xrdb/Kconfig
index 6805fa5..6f0b012 100644
--- a/board/freescale/t208xrdb/Kconfig
+++ b/board/freescale/t208xrdb/Kconfig
@@ -12,4 +12,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/t4qds/Kconfig b/board/freescale/t4qds/Kconfig
index 6728ef2..f7c1a0c 100644
--- a/board/freescale/t4qds/Kconfig
+++ b/board/freescale/t4qds/Kconfig
@@ -12,4 +12,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/t4rdb/Kconfig b/board/freescale/t4rdb/Kconfig
index b5ac845..a94a57e 100644
--- a/board/freescale/t4rdb/Kconfig
+++ b/board/freescale/t4rdb/Kconfig
@@ -12,4 +12,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/freescale/vf610twr/Kconfig b/board/freescale/vf610twr/Kconfig
index 502df10..3b90ed6 100644
--- a/board/freescale/vf610twr/Kconfig
+++ b/board/freescale/vf610twr/Kconfig
@@ -10,4 +10,3 @@
default "vf610twr"
endif
-
diff --git a/board/gardena/smart-gateway-mt7688/Kconfig b/board/gardena/smart-gateway-mt7688/Kconfig
index 0078b5b..3653f8a 100644
--- a/board/gardena/smart-gateway-mt7688/Kconfig
+++ b/board/gardena/smart-gateway-mt7688/Kconfig
@@ -10,4 +10,3 @@
default "gardena-smart-gateway-mt7688"
endif
-
diff --git a/board/gateworks/gw_ventana/Kconfig b/board/gateworks/gw_ventana/Kconfig
index ccc6f10..5d1bae4 100644
--- a/board/gateworks/gw_ventana/Kconfig
+++ b/board/gateworks/gw_ventana/Kconfig
@@ -23,4 +23,3 @@
gsc wd - enables / disables the watchdog
endif
-
diff --git a/board/gdsys/mpc8308/Kconfig b/board/gdsys/mpc8308/Kconfig
index e0c2bfc..9d99f68 100644
--- a/board/gdsys/mpc8308/Kconfig
+++ b/board/gdsys/mpc8308/Kconfig
@@ -39,4 +39,3 @@
bool "Enable 'ioloop' and 'ioreflect' commands"
help
These commands provide FPGA tests.
-
diff --git a/board/gdsys/p1022/Kconfig b/board/gdsys/p1022/Kconfig
index 49dd2aa..8514d08 100644
--- a/board/gdsys/p1022/Kconfig
+++ b/board/gdsys/p1022/Kconfig
@@ -10,4 +10,3 @@
default "controlcenterd"
endif
-
diff --git a/board/ge/bx50v3/Kconfig b/board/ge/bx50v3/Kconfig
index 623bf4e..0593856 100644
--- a/board/ge/bx50v3/Kconfig
+++ b/board/ge/bx50v3/Kconfig
@@ -18,4 +18,3 @@
source "board/ge/common/Kconfig"
endif
-
diff --git a/board/ge/common/Kconfig b/board/ge/common/Kconfig
index 580c8d7..637b264 100644
--- a/board/ge/common/Kconfig
+++ b/board/ge/common/Kconfig
@@ -12,4 +12,3 @@
config SYS_VPD_EEPROM_I2C_ADDR_LEN
int "Number of bytes to use for VPD EEPROM address"
default 1
-
diff --git a/board/ge/mx53ppd/Kconfig b/board/ge/mx53ppd/Kconfig
index e984503..bebb2fa 100644
--- a/board/ge/mx53ppd/Kconfig
+++ b/board/ge/mx53ppd/Kconfig
@@ -16,4 +16,3 @@
source "board/ge/common/Kconfig"
endif
-
diff --git a/board/geekbuying/geekbox/Kconfig b/board/geekbuying/geekbox/Kconfig
index 1285a6b..41aa8fb 100644
--- a/board/geekbuying/geekbox/Kconfig
+++ b/board/geekbuying/geekbox/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/google/Kconfig b/board/google/Kconfig
index cfe40c1..d98a5e8 100644
--- a/board/google/Kconfig
+++ b/board/google/Kconfig
@@ -59,4 +59,3 @@
source "board/google/chromebook_samus/Kconfig"
endif
-
diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig
index 71dfb1e..944716d 100644
--- a/board/google/chromebook_link/Kconfig
+++ b/board/google/chromebook_link/Kconfig
@@ -40,4 +40,3 @@
default 0x20000
endif
-
diff --git a/board/google/chromebook_samus/Kconfig b/board/google/chromebook_samus/Kconfig
index 877ed57..afbfe53 100644
--- a/board/google/chromebook_samus/Kconfig
+++ b/board/google/chromebook_samus/Kconfig
@@ -39,4 +39,3 @@
default 0x40000
endif
-
diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig
index ca41a0c..875df9d 100644
--- a/board/google/chromebox_panther/Kconfig
+++ b/board/google/chromebox_panther/Kconfig
@@ -33,4 +33,3 @@
default 0x20000
endif
-
diff --git a/board/google/veyron/Kconfig b/board/google/veyron/Kconfig
index 7547efa..770e9aa 100644
--- a/board/google/veyron/Kconfig
+++ b/board/google/veyron/Kconfig
@@ -45,4 +45,3 @@
def_bool y
endif
-
diff --git a/board/grinn/chiliboard/Kconfig b/board/grinn/chiliboard/Kconfig
index e74dd34..20056e8 100644
--- a/board/grinn/chiliboard/Kconfig
+++ b/board/grinn/chiliboard/Kconfig
@@ -13,4 +13,3 @@
default "am33xx"
endif
-
diff --git a/board/grinn/liteboard/Kconfig b/board/grinn/liteboard/Kconfig
index 5a3900f..e035872 100644
--- a/board/grinn/liteboard/Kconfig
+++ b/board/grinn/liteboard/Kconfig
@@ -10,4 +10,3 @@
default "liteboard"
endif
-
diff --git a/board/gumstix/duovero/Kconfig b/board/gumstix/duovero/Kconfig
index 0919345..2f8558a 100644
--- a/board/gumstix/duovero/Kconfig
+++ b/board/gumstix/duovero/Kconfig
@@ -10,4 +10,3 @@
default "duovero"
endif
-
diff --git a/board/gumstix/pepper/Kconfig b/board/gumstix/pepper/Kconfig
index 7f540c7..6f94612 100644
--- a/board/gumstix/pepper/Kconfig
+++ b/board/gumstix/pepper/Kconfig
@@ -13,4 +13,3 @@
default "pepper"
endif
-
diff --git a/board/h2200/Kconfig b/board/h2200/Kconfig
index 700e9e7..c0e0c1e 100644
--- a/board/h2200/Kconfig
+++ b/board/h2200/Kconfig
@@ -7,4 +7,3 @@
default "h2200"
endif
-
diff --git a/board/hisilicon/hikey/Kconfig b/board/hisilicon/hikey/Kconfig
index cfb48ea..f7f1055 100644
--- a/board/hisilicon/hikey/Kconfig
+++ b/board/hisilicon/hikey/Kconfig
@@ -13,4 +13,3 @@
default "hikey"
endif
-
diff --git a/board/hisilicon/poplar/Kconfig b/board/hisilicon/poplar/Kconfig
index dfab7d9..3397295 100644
--- a/board/hisilicon/poplar/Kconfig
+++ b/board/hisilicon/poplar/Kconfig
@@ -13,4 +13,3 @@
default "poplar"
endif
-
diff --git a/board/htkw/mcx/Kconfig b/board/htkw/mcx/Kconfig
index 6845d88..25ba548 100644
--- a/board/htkw/mcx/Kconfig
+++ b/board/htkw/mcx/Kconfig
@@ -10,4 +10,3 @@
default "mcx"
endif
-
diff --git a/board/huawei/hg556a/Kconfig b/board/huawei/hg556a/Kconfig
index 47f2f00..88622d0 100644
--- a/board/huawei/hg556a/Kconfig
+++ b/board/huawei/hg556a/Kconfig
@@ -10,4 +10,3 @@
default "huawei_hg556a"
endif
-
diff --git a/board/ids/ids8313/Kconfig b/board/ids/ids8313/Kconfig
index 0732c39..d165b4b 100644
--- a/board/ids/ids8313/Kconfig
+++ b/board/ids/ids8313/Kconfig
@@ -10,4 +10,3 @@
default "ids8313"
endif
-
diff --git a/board/imgtec/boston/Kconfig b/board/imgtec/boston/Kconfig
index 1f1c814..ab76a3c 100644
--- a/board/imgtec/boston/Kconfig
+++ b/board/imgtec/boston/Kconfig
@@ -14,4 +14,3 @@
default 0xffffffff9fc00000 if 64BIT
endif
-
diff --git a/board/imgtec/ci20/Kconfig b/board/imgtec/ci20/Kconfig
index 57fa6ea..82bf65d 100644
--- a/board/imgtec/ci20/Kconfig
+++ b/board/imgtec/ci20/Kconfig
@@ -13,4 +13,3 @@
default 0x80000000
endif
-
diff --git a/board/imgtec/malta/Kconfig b/board/imgtec/malta/Kconfig
index 6006f0a..98eb4d1 100644
--- a/board/imgtec/malta/Kconfig
+++ b/board/imgtec/malta/Kconfig
@@ -14,4 +14,3 @@
default 0xffffffffbe000000 if 64BIT
endif
-
diff --git a/board/imgtec/xilfpga/Kconfig b/board/imgtec/xilfpga/Kconfig
index 6081351..b078278 100644
--- a/board/imgtec/xilfpga/Kconfig
+++ b/board/imgtec/xilfpga/Kconfig
@@ -13,4 +13,3 @@
default 0x80C00000
endif
-
diff --git a/board/intel/Kconfig b/board/intel/Kconfig
index c993369..5131836 100644
--- a/board/intel/Kconfig
+++ b/board/intel/Kconfig
@@ -84,4 +84,3 @@
source "board/intel/minnowmax/Kconfig"
endif
-
diff --git a/board/intel/bayleybay/Kconfig b/board/intel/bayleybay/Kconfig
index 00b087d..a622499 100644
--- a/board/intel/bayleybay/Kconfig
+++ b/board/intel/bayleybay/Kconfig
@@ -26,4 +26,3 @@
default 0xe0000000
endif
-
diff --git a/board/intel/cherryhill/Kconfig b/board/intel/cherryhill/Kconfig
index 873d78f..a4fa004 100644
--- a/board/intel/cherryhill/Kconfig
+++ b/board/intel/cherryhill/Kconfig
@@ -23,4 +23,3 @@
select SPI_FLASH_MACRONIX
endif
-
diff --git a/board/intel/cougarcanyon2/Kconfig b/board/intel/cougarcanyon2/Kconfig
index 1beb510..ed76448 100644
--- a/board/intel/cougarcanyon2/Kconfig
+++ b/board/intel/cougarcanyon2/Kconfig
@@ -25,4 +25,3 @@
select SPI_FLASH_WINBOND
endif
-
diff --git a/board/intel/crownbay/Kconfig b/board/intel/crownbay/Kconfig
index d480aaf..1eed227 100644
--- a/board/intel/crownbay/Kconfig
+++ b/board/intel/crownbay/Kconfig
@@ -24,4 +24,3 @@
select SPI_FLASH_SST
endif
-
diff --git a/board/intel/edison/Kconfig b/board/intel/edison/Kconfig
index 1af7883..ef9b14a 100644
--- a/board/intel/edison/Kconfig
+++ b/board/intel/edison/Kconfig
@@ -30,4 +30,3 @@
select MD5
endif
-
diff --git a/board/intel/galileo/Kconfig b/board/intel/galileo/Kconfig
index 4365c99..1416c89 100644
--- a/board/intel/galileo/Kconfig
+++ b/board/intel/galileo/Kconfig
@@ -34,4 +34,3 @@
This can be "Galileo" for GEN1 Galileo board.
endif
-
diff --git a/board/intel/minnowmax/Kconfig b/board/intel/minnowmax/Kconfig
index 9090737..543468c 100644
--- a/board/intel/minnowmax/Kconfig
+++ b/board/intel/minnowmax/Kconfig
@@ -26,4 +26,3 @@
default 0xe0000000
endif
-
diff --git a/board/inversepath/usbarmory/Kconfig b/board/inversepath/usbarmory/Kconfig
index 09139d4..c2cd544 100644
--- a/board/inversepath/usbarmory/Kconfig
+++ b/board/inversepath/usbarmory/Kconfig
@@ -13,4 +13,3 @@
default "usbarmory"
endif
-
diff --git a/board/iomega/iconnect/Kconfig b/board/iomega/iconnect/Kconfig
index a25c42c..e56b029 100644
--- a/board/iomega/iconnect/Kconfig
+++ b/board/iomega/iconnect/Kconfig
@@ -10,4 +10,3 @@
default "iconnect"
endif
-
diff --git a/board/isee/igep003x/Kconfig b/board/isee/igep003x/Kconfig
index e57eee9..68a68fc 100644
--- a/board/isee/igep003x/Kconfig
+++ b/board/isee/igep003x/Kconfig
@@ -13,4 +13,3 @@
default "am335x_igep003x"
endif
-
diff --git a/board/isee/igep00x0/Kconfig b/board/isee/igep00x0/Kconfig
index 19f7dc8..aa46882 100644
--- a/board/isee/igep00x0/Kconfig
+++ b/board/isee/igep00x0/Kconfig
@@ -10,4 +10,3 @@
default "omap3_igep00x0"
endif
-
diff --git a/board/k+p/kp_imx53/Kconfig b/board/k+p/kp_imx53/Kconfig
index 1f68a3a..017c1e3 100644
--- a/board/k+p/kp_imx53/Kconfig
+++ b/board/k+p/kp_imx53/Kconfig
@@ -13,4 +13,3 @@
default "kp_imx53"
endif
-
diff --git a/board/k+p/kp_imx6q_tpc/Kconfig b/board/k+p/kp_imx6q_tpc/Kconfig
index 3da9997..62e3497 100644
--- a/board/k+p/kp_imx6q_tpc/Kconfig
+++ b/board/k+p/kp_imx6q_tpc/Kconfig
@@ -10,4 +10,3 @@
default "kp_imx6q_tpc"
endif
-
diff --git a/board/keymile/km83xx/Kconfig b/board/keymile/km83xx/Kconfig
index 4681ecc..d6c594c 100644
--- a/board/keymile/km83xx/Kconfig
+++ b/board/keymile/km83xx/Kconfig
@@ -36,4 +36,3 @@
default "tuxx1"
endif
-
diff --git a/board/keymile/km_arm/Kconfig b/board/keymile/km_arm/Kconfig
index 3771c11..3476780 100644
--- a/board/keymile/km_arm/Kconfig
+++ b/board/keymile/km_arm/Kconfig
@@ -10,4 +10,3 @@
default "km_kirkwood"
endif
-
diff --git a/board/keymile/kmp204x/Kconfig b/board/keymile/kmp204x/Kconfig
index f09ed06..7b45a13 100644
--- a/board/keymile/kmp204x/Kconfig
+++ b/board/keymile/kmp204x/Kconfig
@@ -10,4 +10,3 @@
default "kmp204x"
endif
-
diff --git a/board/kmc/kzm9g/Kconfig b/board/kmc/kzm9g/Kconfig
index 54c734f..f163efd 100644
--- a/board/kmc/kzm9g/Kconfig
+++ b/board/kmc/kzm9g/Kconfig
@@ -10,4 +10,3 @@
default "kzm9g"
endif
-
diff --git a/board/kosagi/novena/Kconfig b/board/kosagi/novena/Kconfig
index e9776bf..c5cbaab 100644
--- a/board/kosagi/novena/Kconfig
+++ b/board/kosagi/novena/Kconfig
@@ -10,4 +10,3 @@
default "novena"
endif
-
diff --git a/board/l+g/vinco/Kconfig b/board/l+g/vinco/Kconfig
index c6b596d..229b5ea 100644
--- a/board/l+g/vinco/Kconfig
+++ b/board/l+g/vinco/Kconfig
@@ -10,4 +10,3 @@
default "vinco"
endif
-
diff --git a/board/laird/wb45n/Kconfig b/board/laird/wb45n/Kconfig
index 5cb69b8..2a67337 100644
--- a/board/laird/wb45n/Kconfig
+++ b/board/laird/wb45n/Kconfig
@@ -10,4 +10,3 @@
default "wb45n"
endif
-
diff --git a/board/laird/wb50n/Kconfig b/board/laird/wb50n/Kconfig
index 74d7b04..2e7090e 100644
--- a/board/laird/wb50n/Kconfig
+++ b/board/laird/wb50n/Kconfig
@@ -10,4 +10,3 @@
default "wb50n"
endif
-
diff --git a/board/lego/ev3/Kconfig b/board/lego/ev3/Kconfig
index a9856bf..14b3f0c 100644
--- a/board/lego/ev3/Kconfig
+++ b/board/lego/ev3/Kconfig
@@ -10,4 +10,3 @@
default "legoev3"
endif
-
diff --git a/board/lg/sniper/Kconfig b/board/lg/sniper/Kconfig
index f23a0f4..3f18d21 100644
--- a/board/lg/sniper/Kconfig
+++ b/board/lg/sniper/Kconfig
@@ -10,4 +10,3 @@
default "sniper"
endif
-
diff --git a/board/liebherr/display5/Kconfig b/board/liebherr/display5/Kconfig
index 3bdaa9d..b096c89 100644
--- a/board/liebherr/display5/Kconfig
+++ b/board/liebherr/display5/Kconfig
@@ -16,4 +16,3 @@
default "display5"
endif
-
diff --git a/board/liebherr/mccmon6/Kconfig b/board/liebherr/mccmon6/Kconfig
index 3b0f00a..4cc7fc2 100644
--- a/board/liebherr/mccmon6/Kconfig
+++ b/board/liebherr/mccmon6/Kconfig
@@ -10,4 +10,3 @@
default "mccmon6"
endif
-
diff --git a/board/logicpd/am3517evm/Kconfig b/board/logicpd/am3517evm/Kconfig
index 88d829b..743e500 100644
--- a/board/logicpd/am3517evm/Kconfig
+++ b/board/logicpd/am3517evm/Kconfig
@@ -12,4 +12,3 @@
source "board/ti/common/Kconfig"
endif
-
diff --git a/board/logicpd/imx6/Kconfig b/board/logicpd/imx6/Kconfig
index c1b6f60..f5e2f58 100644
--- a/board/logicpd/imx6/Kconfig
+++ b/board/logicpd/imx6/Kconfig
@@ -10,4 +10,3 @@
default "imx6_logic"
endif
-
diff --git a/board/logicpd/omap3som/Kconfig b/board/logicpd/omap3som/Kconfig
index fbebf2c..68d40dc 100644
--- a/board/logicpd/omap3som/Kconfig
+++ b/board/logicpd/omap3som/Kconfig
@@ -12,4 +12,3 @@
source "board/ti/common/Kconfig"
endif
-
diff --git a/board/logicpd/zoom1/Kconfig b/board/logicpd/zoom1/Kconfig
index 07ec9b1..d76cb66 100644
--- a/board/logicpd/zoom1/Kconfig
+++ b/board/logicpd/zoom1/Kconfig
@@ -10,4 +10,3 @@
default "omap3_zoom1"
endif
-
diff --git a/board/mediatek/mt7623/Kconfig b/board/mediatek/mt7623/Kconfig
index 0461fec..a8c670e 100644
--- a/board/mediatek/mt7623/Kconfig
+++ b/board/mediatek/mt7623/Kconfig
@@ -11,4 +11,3 @@
default "lk=1"
endif
-
diff --git a/board/mediatek/mt7629/Kconfig b/board/mediatek/mt7629/Kconfig
index 6676d1f..6055164 100644
--- a/board/mediatek/mt7629/Kconfig
+++ b/board/mediatek/mt7629/Kconfig
@@ -15,4 +15,3 @@
default "media=nor"
endif
-
diff --git a/board/menlo/m53menlo/Kconfig b/board/menlo/m53menlo/Kconfig
index 4d096ce..1953f50 100644
--- a/board/menlo/m53menlo/Kconfig
+++ b/board/menlo/m53menlo/Kconfig
@@ -13,4 +13,3 @@
default "m53menlo"
endif
-
diff --git a/board/microchip/pic32mzda/Kconfig b/board/microchip/pic32mzda/Kconfig
index 8eba580..4f08e98 100644
--- a/board/microchip/pic32mzda/Kconfig
+++ b/board/microchip/pic32mzda/Kconfig
@@ -14,4 +14,3 @@
default 0x9d004000
endif
-
diff --git a/board/micronas/vct/Kconfig b/board/micronas/vct/Kconfig
index a61ac36..df7c029 100644
--- a/board/micronas/vct/Kconfig
+++ b/board/micronas/vct/Kconfig
@@ -50,4 +50,3 @@
endmenu
endif
-
diff --git a/board/mini-box/picosam9g45/Kconfig b/board/mini-box/picosam9g45/Kconfig
index e31ba0f..98ec0c4 100644
--- a/board/mini-box/picosam9g45/Kconfig
+++ b/board/mini-box/picosam9g45/Kconfig
@@ -10,4 +10,3 @@
default "picosam9g45"
endif
-
diff --git a/board/mpc8308_p1m/Kconfig b/board/mpc8308_p1m/Kconfig
index 37a1194..b7e39da 100644
--- a/board/mpc8308_p1m/Kconfig
+++ b/board/mpc8308_p1m/Kconfig
@@ -7,4 +7,3 @@
default "mpc8308_p1m"
endif
-
diff --git a/board/mpr2/Kconfig b/board/mpr2/Kconfig
index 11b2a7a..54176e8 100644
--- a/board/mpr2/Kconfig
+++ b/board/mpr2/Kconfig
@@ -7,4 +7,3 @@
default "mpr2"
endif
-
diff --git a/board/mqmaker/miqi_rk3288/Kconfig b/board/mqmaker/miqi_rk3288/Kconfig
index eca03b2..232a112 100644
--- a/board/mqmaker/miqi_rk3288/Kconfig
+++ b/board/mqmaker/miqi_rk3288/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/ms7720se/Kconfig b/board/ms7720se/Kconfig
index e728235..8331327 100644
--- a/board/ms7720se/Kconfig
+++ b/board/ms7720se/Kconfig
@@ -7,4 +7,3 @@
default "ms7720se"
endif
-
diff --git a/board/ms7722se/Kconfig b/board/ms7722se/Kconfig
index eaad979..39027c9 100644
--- a/board/ms7722se/Kconfig
+++ b/board/ms7722se/Kconfig
@@ -7,4 +7,3 @@
default "ms7722se"
endif
-
diff --git a/board/ms7750se/Kconfig b/board/ms7750se/Kconfig
index 15c9503..2c0b88c 100644
--- a/board/ms7750se/Kconfig
+++ b/board/ms7750se/Kconfig
@@ -7,4 +7,3 @@
default "ms7750se"
endif
-
diff --git a/board/mscc/luton/Kconfig b/board/mscc/luton/Kconfig
index d16804a..e119980 100644
--- a/board/mscc/luton/Kconfig
+++ b/board/mscc/luton/Kconfig
@@ -12,4 +12,3 @@
default "luton"
endif
-
diff --git a/board/mscc/ocelot/Kconfig b/board/mscc/ocelot/Kconfig
index ac99858..9ddc088 100644
--- a/board/mscc/ocelot/Kconfig
+++ b/board/mscc/ocelot/Kconfig
@@ -12,4 +12,3 @@
default "ocelot"
endif
-
diff --git a/board/netgear/cg3100d/Kconfig b/board/netgear/cg3100d/Kconfig
index 804115d..632c22d 100644
--- a/board/netgear/cg3100d/Kconfig
+++ b/board/netgear/cg3100d/Kconfig
@@ -10,4 +10,3 @@
default "netgear_cg3100d"
endif
-
diff --git a/board/netgear/dgnd3700v2/Kconfig b/board/netgear/dgnd3700v2/Kconfig
index 4c03300..11af188 100644
--- a/board/netgear/dgnd3700v2/Kconfig
+++ b/board/netgear/dgnd3700v2/Kconfig
@@ -10,4 +10,3 @@
default "netgear_dgnd3700v2"
endif
-
diff --git a/board/nokia/rx51/Kconfig b/board/nokia/rx51/Kconfig
index 7fd78ff..ec6a571 100644
--- a/board/nokia/rx51/Kconfig
+++ b/board/nokia/rx51/Kconfig
@@ -10,4 +10,3 @@
default "nokia_rx51"
endif
-
diff --git a/board/nvidia/beaver/Kconfig b/board/nvidia/beaver/Kconfig
index 5e169ba..23f7c94 100644
--- a/board/nvidia/beaver/Kconfig
+++ b/board/nvidia/beaver/Kconfig
@@ -10,4 +10,3 @@
default "beaver"
endif
-
diff --git a/board/nvidia/cardhu/Kconfig b/board/nvidia/cardhu/Kconfig
index 5872293..63ace66 100644
--- a/board/nvidia/cardhu/Kconfig
+++ b/board/nvidia/cardhu/Kconfig
@@ -10,4 +10,3 @@
default "cardhu"
endif
-
diff --git a/board/nvidia/dalmore/Kconfig b/board/nvidia/dalmore/Kconfig
index 7fb5b2b..96eaa01 100644
--- a/board/nvidia/dalmore/Kconfig
+++ b/board/nvidia/dalmore/Kconfig
@@ -10,4 +10,3 @@
default "dalmore"
endif
-
diff --git a/board/nvidia/e2220-1170/Kconfig b/board/nvidia/e2220-1170/Kconfig
index 2823bc7..0a30f49 100644
--- a/board/nvidia/e2220-1170/Kconfig
+++ b/board/nvidia/e2220-1170/Kconfig
@@ -10,4 +10,3 @@
default "e2220-1170"
endif
-
diff --git a/board/nvidia/harmony/Kconfig b/board/nvidia/harmony/Kconfig
index e45a2af..328c946 100644
--- a/board/nvidia/harmony/Kconfig
+++ b/board/nvidia/harmony/Kconfig
@@ -10,4 +10,3 @@
default "harmony"
endif
-
diff --git a/board/nvidia/jetson-tk1/Kconfig b/board/nvidia/jetson-tk1/Kconfig
index 940d09a..d90a74e 100644
--- a/board/nvidia/jetson-tk1/Kconfig
+++ b/board/nvidia/jetson-tk1/Kconfig
@@ -10,4 +10,3 @@
default "jetson-tk1"
endif
-
diff --git a/board/nvidia/nyan-big/Kconfig b/board/nvidia/nyan-big/Kconfig
index f69e61b..341c8d7 100644
--- a/board/nvidia/nyan-big/Kconfig
+++ b/board/nvidia/nyan-big/Kconfig
@@ -10,4 +10,3 @@
default "nyan-big"
endif
-
diff --git a/board/nvidia/p2371-0000/Kconfig b/board/nvidia/p2371-0000/Kconfig
index 4f6a4b2..f94be12 100644
--- a/board/nvidia/p2371-0000/Kconfig
+++ b/board/nvidia/p2371-0000/Kconfig
@@ -10,4 +10,3 @@
default "p2371-0000"
endif
-
diff --git a/board/nvidia/p2371-2180/Kconfig b/board/nvidia/p2371-2180/Kconfig
index 355bae0..8622bda 100644
--- a/board/nvidia/p2371-2180/Kconfig
+++ b/board/nvidia/p2371-2180/Kconfig
@@ -10,4 +10,3 @@
default "p2371-2180"
endif
-
diff --git a/board/nvidia/p2571/Kconfig b/board/nvidia/p2571/Kconfig
index 8390a09..7bc4874 100644
--- a/board/nvidia/p2571/Kconfig
+++ b/board/nvidia/p2571/Kconfig
@@ -10,4 +10,3 @@
default "p2571"
endif
-
diff --git a/board/nvidia/p2771-0000/Kconfig b/board/nvidia/p2771-0000/Kconfig
index 0d04224..1b1116f 100644
--- a/board/nvidia/p2771-0000/Kconfig
+++ b/board/nvidia/p2771-0000/Kconfig
@@ -14,4 +14,3 @@
default "p2771-0000"
endif
-
diff --git a/board/nvidia/seaboard/Kconfig b/board/nvidia/seaboard/Kconfig
index 409957a..0924bde 100644
--- a/board/nvidia/seaboard/Kconfig
+++ b/board/nvidia/seaboard/Kconfig
@@ -10,4 +10,3 @@
default "seaboard"
endif
-
diff --git a/board/nvidia/venice2/Kconfig b/board/nvidia/venice2/Kconfig
index f9e5def..6905f00 100644
--- a/board/nvidia/venice2/Kconfig
+++ b/board/nvidia/venice2/Kconfig
@@ -10,4 +10,3 @@
default "venice2"
endif
-
diff --git a/board/nvidia/ventana/Kconfig b/board/nvidia/ventana/Kconfig
index 69fe01d..c1ad7b7 100644
--- a/board/nvidia/ventana/Kconfig
+++ b/board/nvidia/ventana/Kconfig
@@ -10,4 +10,3 @@
default "ventana"
endif
-
diff --git a/board/olimex/mx23_olinuxino/Kconfig b/board/olimex/mx23_olinuxino/Kconfig
index f387840..0b151c9 100644
--- a/board/olimex/mx23_olinuxino/Kconfig
+++ b/board/olimex/mx23_olinuxino/Kconfig
@@ -13,4 +13,3 @@
default "mx23_olinuxino"
endif
-
diff --git a/board/omicron/calimain/Kconfig b/board/omicron/calimain/Kconfig
index 7207bbf..1ec48e6 100644
--- a/board/omicron/calimain/Kconfig
+++ b/board/omicron/calimain/Kconfig
@@ -10,4 +10,3 @@
default "calimain"
endif
-
diff --git a/board/overo/Kconfig b/board/overo/Kconfig
index cb99b23..74572a6 100644
--- a/board/overo/Kconfig
+++ b/board/overo/Kconfig
@@ -7,4 +7,3 @@
default "omap3_overo"
endif
-
diff --git a/board/pandora/Kconfig b/board/pandora/Kconfig
index f01d49c..0b33818 100644
--- a/board/pandora/Kconfig
+++ b/board/pandora/Kconfig
@@ -7,4 +7,3 @@
default "omap3_pandora"
endif
-
diff --git a/board/phytec/pcm051/Kconfig b/board/phytec/pcm051/Kconfig
index 345ea54..2cc0d88 100644
--- a/board/phytec/pcm051/Kconfig
+++ b/board/phytec/pcm051/Kconfig
@@ -13,4 +13,3 @@
default "pcm051"
endif
-
diff --git a/board/phytec/pcm052/Kconfig b/board/phytec/pcm052/Kconfig
index 775e9b0..4fde21c 100644
--- a/board/phytec/pcm052/Kconfig
+++ b/board/phytec/pcm052/Kconfig
@@ -31,4 +31,3 @@
default 512
endif
-
diff --git a/board/phytec/pcm058/Kconfig b/board/phytec/pcm058/Kconfig
index f1d3914..d099275 100644
--- a/board/phytec/pcm058/Kconfig
+++ b/board/phytec/pcm058/Kconfig
@@ -10,4 +10,3 @@
default "pcm058"
endif
-
diff --git a/board/phytec/pfla02/Kconfig b/board/phytec/pfla02/Kconfig
index bf011b2..f4da68b 100644
--- a/board/phytec/pfla02/Kconfig
+++ b/board/phytec/pfla02/Kconfig
@@ -16,4 +16,3 @@
of RAM
endif
-
diff --git a/board/phytec/phycore_rk3288/Kconfig b/board/phytec/phycore_rk3288/Kconfig
index a964eba..57cd8e2 100644
--- a/board/phytec/phycore_rk3288/Kconfig
+++ b/board/phytec/phycore_rk3288/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/ppcag/bg0900/Kconfig b/board/ppcag/bg0900/Kconfig
index 84d00fb..d7f2368 100644
--- a/board/ppcag/bg0900/Kconfig
+++ b/board/ppcag/bg0900/Kconfig
@@ -13,4 +13,3 @@
default "bg0900"
endif
-
diff --git a/board/qca/ap121/Kconfig b/board/qca/ap121/Kconfig
index 49d663a..4fd6a71 100644
--- a/board/qca/ap121/Kconfig
+++ b/board/qca/ap121/Kconfig
@@ -25,4 +25,3 @@
default 32
endif
-
diff --git a/board/qca/ap143/Kconfig b/board/qca/ap143/Kconfig
index d5297e2..74c632a 100644
--- a/board/qca/ap143/Kconfig
+++ b/board/qca/ap143/Kconfig
@@ -25,4 +25,3 @@
default 32
endif
-
diff --git a/board/qemu-mips/Kconfig b/board/qemu-mips/Kconfig
index 59de237..e696a12 100644
--- a/board/qemu-mips/Kconfig
+++ b/board/qemu-mips/Kconfig
@@ -24,4 +24,3 @@
default 32
endif
-
diff --git a/board/qualcomm/dragonboard410c/Kconfig b/board/qualcomm/dragonboard410c/Kconfig
index 9c52969..03bd7ae 100644
--- a/board/qualcomm/dragonboard410c/Kconfig
+++ b/board/qualcomm/dragonboard410c/Kconfig
@@ -13,4 +13,3 @@
default "dragonboard410c"
endif
-
diff --git a/board/qualcomm/dragonboard820c/Kconfig b/board/qualcomm/dragonboard820c/Kconfig
index 09806c1..aff9af5 100644
--- a/board/qualcomm/dragonboard820c/Kconfig
+++ b/board/qualcomm/dragonboard820c/Kconfig
@@ -13,4 +13,3 @@
default "dragonboard820c"
endif
-
diff --git a/board/quipos/cairo/Kconfig b/board/quipos/cairo/Kconfig
index 771dc58..8df9421 100644
--- a/board/quipos/cairo/Kconfig
+++ b/board/quipos/cairo/Kconfig
@@ -10,4 +10,3 @@
default "omap3_cairo"
endif
-
diff --git a/board/radxa/rock/Kconfig b/board/radxa/rock/Kconfig
index b48d773..855b9b6 100644
--- a/board/radxa/rock/Kconfig
+++ b/board/radxa/rock/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/radxa/rock2/Kconfig b/board/radxa/rock2/Kconfig
index 050f4c2..c2ff9e9 100644
--- a/board/radxa/rock2/Kconfig
+++ b/board/radxa/rock2/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/raidsonic/ib62x0/Kconfig b/board/raidsonic/ib62x0/Kconfig
index f69a2b0..129aac8 100644
--- a/board/raidsonic/ib62x0/Kconfig
+++ b/board/raidsonic/ib62x0/Kconfig
@@ -10,4 +10,3 @@
default "ib62x0"
endif
-
diff --git a/board/renesas/MigoR/Kconfig b/board/renesas/MigoR/Kconfig
index 1029052..25b170a 100644
--- a/board/renesas/MigoR/Kconfig
+++ b/board/renesas/MigoR/Kconfig
@@ -10,4 +10,3 @@
default "MigoR"
endif
-
diff --git a/board/renesas/alt/Kconfig b/board/renesas/alt/Kconfig
index de92f0b..39d53c1 100644
--- a/board/renesas/alt/Kconfig
+++ b/board/renesas/alt/Kconfig
@@ -19,4 +19,3 @@
DIP switch of board in order to use this function.
endif
-
diff --git a/board/renesas/ap325rxa/Kconfig b/board/renesas/ap325rxa/Kconfig
index 3e95904..c8f2de2 100644
--- a/board/renesas/ap325rxa/Kconfig
+++ b/board/renesas/ap325rxa/Kconfig
@@ -10,4 +10,3 @@
default "ap325rxa"
endif
-
diff --git a/board/renesas/blanche/Kconfig b/board/renesas/blanche/Kconfig
index e3ba350..ac4730a 100644
--- a/board/renesas/blanche/Kconfig
+++ b/board/renesas/blanche/Kconfig
@@ -10,4 +10,3 @@
default "blanche"
endif
-
diff --git a/board/renesas/draak/Kconfig b/board/renesas/draak/Kconfig
index 8b02dd7..9106387 100644
--- a/board/renesas/draak/Kconfig
+++ b/board/renesas/draak/Kconfig
@@ -13,4 +13,3 @@
default "draak"
endif
-
diff --git a/board/renesas/eagle/Kconfig b/board/renesas/eagle/Kconfig
index 62e8d33..1e0710e 100644
--- a/board/renesas/eagle/Kconfig
+++ b/board/renesas/eagle/Kconfig
@@ -13,4 +13,3 @@
default "eagle"
endif
-
diff --git a/board/renesas/ebisu/Kconfig b/board/renesas/ebisu/Kconfig
index 023be52..f500a94 100644
--- a/board/renesas/ebisu/Kconfig
+++ b/board/renesas/ebisu/Kconfig
@@ -13,4 +13,3 @@
default "ebisu"
endif
-
diff --git a/board/renesas/ecovec/Kconfig b/board/renesas/ecovec/Kconfig
index 74ddf34..08cde83 100644
--- a/board/renesas/ecovec/Kconfig
+++ b/board/renesas/ecovec/Kconfig
@@ -10,4 +10,3 @@
default "ecovec"
endif
-
diff --git a/board/renesas/gose/Kconfig b/board/renesas/gose/Kconfig
index 98f81f5..930a445 100644
--- a/board/renesas/gose/Kconfig
+++ b/board/renesas/gose/Kconfig
@@ -10,4 +10,3 @@
default "gose"
endif
-
diff --git a/board/renesas/koelsch/Kconfig b/board/renesas/koelsch/Kconfig
index 8a73be9..6475f02 100644
--- a/board/renesas/koelsch/Kconfig
+++ b/board/renesas/koelsch/Kconfig
@@ -10,4 +10,3 @@
default "koelsch"
endif
-
diff --git a/board/renesas/lager/Kconfig b/board/renesas/lager/Kconfig
index 264de8f..e990c20 100644
--- a/board/renesas/lager/Kconfig
+++ b/board/renesas/lager/Kconfig
@@ -10,4 +10,3 @@
default "lager"
endif
-
diff --git a/board/renesas/porter/Kconfig b/board/renesas/porter/Kconfig
index 24df2fb..a6f621b 100644
--- a/board/renesas/porter/Kconfig
+++ b/board/renesas/porter/Kconfig
@@ -10,4 +10,3 @@
default "porter"
endif
-
diff --git a/board/renesas/r0p7734/Kconfig b/board/renesas/r0p7734/Kconfig
index 18c923f..7f24f41 100644
--- a/board/renesas/r0p7734/Kconfig
+++ b/board/renesas/r0p7734/Kconfig
@@ -10,4 +10,3 @@
default "r0p7734"
endif
-
diff --git a/board/renesas/r2dplus/Kconfig b/board/renesas/r2dplus/Kconfig
index 8884b8d..6597870 100644
--- a/board/renesas/r2dplus/Kconfig
+++ b/board/renesas/r2dplus/Kconfig
@@ -10,4 +10,3 @@
default "r2dplus"
endif
-
diff --git a/board/renesas/r7780mp/Kconfig b/board/renesas/r7780mp/Kconfig
index f708555..050cc4c 100644
--- a/board/renesas/r7780mp/Kconfig
+++ b/board/renesas/r7780mp/Kconfig
@@ -10,4 +10,3 @@
default "r7780mp"
endif
-
diff --git a/board/renesas/rsk7203/Kconfig b/board/renesas/rsk7203/Kconfig
index 4aa71b4..10b8786 100644
--- a/board/renesas/rsk7203/Kconfig
+++ b/board/renesas/rsk7203/Kconfig
@@ -10,4 +10,3 @@
default "rsk7203"
endif
-
diff --git a/board/renesas/rsk7264/Kconfig b/board/renesas/rsk7264/Kconfig
index f83f1ae..755d289 100644
--- a/board/renesas/rsk7264/Kconfig
+++ b/board/renesas/rsk7264/Kconfig
@@ -10,4 +10,3 @@
default "rsk7264"
endif
-
diff --git a/board/renesas/rsk7269/Kconfig b/board/renesas/rsk7269/Kconfig
index ee8dfe9..ab5cd0e 100644
--- a/board/renesas/rsk7269/Kconfig
+++ b/board/renesas/rsk7269/Kconfig
@@ -10,4 +10,3 @@
default "rsk7269"
endif
-
diff --git a/board/renesas/salvator-x/Kconfig b/board/renesas/salvator-x/Kconfig
index df8e0a6..ed4c479 100644
--- a/board/renesas/salvator-x/Kconfig
+++ b/board/renesas/salvator-x/Kconfig
@@ -13,4 +13,3 @@
default "salvator-x"
endif
-
diff --git a/board/renesas/sh7752evb/Kconfig b/board/renesas/sh7752evb/Kconfig
index 34411ae..7f40888 100644
--- a/board/renesas/sh7752evb/Kconfig
+++ b/board/renesas/sh7752evb/Kconfig
@@ -10,4 +10,3 @@
default "sh7752evb"
endif
-
diff --git a/board/renesas/sh7753evb/Kconfig b/board/renesas/sh7753evb/Kconfig
index 2cb30c0..be88924 100644
--- a/board/renesas/sh7753evb/Kconfig
+++ b/board/renesas/sh7753evb/Kconfig
@@ -10,4 +10,3 @@
default "sh7753evb"
endif
-
diff --git a/board/renesas/sh7757lcr/Kconfig b/board/renesas/sh7757lcr/Kconfig
index c92fa44..3fba80d 100644
--- a/board/renesas/sh7757lcr/Kconfig
+++ b/board/renesas/sh7757lcr/Kconfig
@@ -10,4 +10,3 @@
default "sh7757lcr"
endif
-
diff --git a/board/renesas/sh7763rdp/Kconfig b/board/renesas/sh7763rdp/Kconfig
index 68cf5ca..101d2b5 100644
--- a/board/renesas/sh7763rdp/Kconfig
+++ b/board/renesas/sh7763rdp/Kconfig
@@ -10,4 +10,3 @@
default "sh7763rdp"
endif
-
diff --git a/board/renesas/sh7785lcr/Kconfig b/board/renesas/sh7785lcr/Kconfig
index 07b412b..e204c76 100644
--- a/board/renesas/sh7785lcr/Kconfig
+++ b/board/renesas/sh7785lcr/Kconfig
@@ -10,4 +10,3 @@
default "sh7785lcr"
endif
-
diff --git a/board/renesas/silk/Kconfig b/board/renesas/silk/Kconfig
index ae6485e..07aee0e 100644
--- a/board/renesas/silk/Kconfig
+++ b/board/renesas/silk/Kconfig
@@ -10,4 +10,3 @@
default "silk"
endif
-
diff --git a/board/renesas/stout/Kconfig b/board/renesas/stout/Kconfig
index 6700d47..cbbc6dd 100644
--- a/board/renesas/stout/Kconfig
+++ b/board/renesas/stout/Kconfig
@@ -10,4 +10,3 @@
default "stout"
endif
-
diff --git a/board/renesas/ulcb/Kconfig b/board/renesas/ulcb/Kconfig
index 887c20a..1e9a10d 100644
--- a/board/renesas/ulcb/Kconfig
+++ b/board/renesas/ulcb/Kconfig
@@ -13,4 +13,3 @@
default "ulcb"
endif
-
diff --git a/board/rockchip/evb_px5/Kconfig b/board/rockchip/evb_px5/Kconfig
index 1fd9203..9a04ee7 100644
--- a/board/rockchip/evb_px5/Kconfig
+++ b/board/rockchip/evb_px5/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/rockchip/evb_rk3036/Kconfig b/board/rockchip/evb_rk3036/Kconfig
index ea88796..ef45f62 100644
--- a/board/rockchip/evb_rk3036/Kconfig
+++ b/board/rockchip/evb_rk3036/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/rockchip/evb_rk3128/Kconfig b/board/rockchip/evb_rk3128/Kconfig
index 66692a2..5b3095a 100644
--- a/board/rockchip/evb_rk3128/Kconfig
+++ b/board/rockchip/evb_rk3128/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/rockchip/evb_rk3229/Kconfig b/board/rockchip/evb_rk3229/Kconfig
index 44adc54..361dcb1 100644
--- a/board/rockchip/evb_rk3229/Kconfig
+++ b/board/rockchip/evb_rk3229/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/rockchip/evb_rk3288/Kconfig b/board/rockchip/evb_rk3288/Kconfig
index 732286b..8ab07f4 100644
--- a/board/rockchip/evb_rk3288/Kconfig
+++ b/board/rockchip/evb_rk3288/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/rockchip/evb_rk3328/Kconfig b/board/rockchip/evb_rk3328/Kconfig
index d32d6f4..ef446b4 100644
--- a/board/rockchip/evb_rk3328/Kconfig
+++ b/board/rockchip/evb_rk3328/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/rockchip/evb_rk3399/Kconfig b/board/rockchip/evb_rk3399/Kconfig
index f7de660..412b81c 100644
--- a/board/rockchip/evb_rk3399/Kconfig
+++ b/board/rockchip/evb_rk3399/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/rockchip/evb_rv1108/Kconfig b/board/rockchip/evb_rv1108/Kconfig
index b8bc33e..4a76e0b 100644
--- a/board/rockchip/evb_rv1108/Kconfig
+++ b/board/rockchip/evb_rv1108/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/rockchip/fennec_rk3288/Kconfig b/board/rockchip/fennec_rk3288/Kconfig
index 776f7b3..1dcfcf0 100644
--- a/board/rockchip/fennec_rk3288/Kconfig
+++ b/board/rockchip/fennec_rk3288/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/rockchip/kylin_rk3036/Kconfig b/board/rockchip/kylin_rk3036/Kconfig
index 2abc41b..8d35b4e 100644
--- a/board/rockchip/kylin_rk3036/Kconfig
+++ b/board/rockchip/kylin_rk3036/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/rockchip/sheep_rk3368/Kconfig b/board/rockchip/sheep_rk3368/Kconfig
index 742ad67..d39b5e8 100644
--- a/board/rockchip/sheep_rk3368/Kconfig
+++ b/board/rockchip/sheep_rk3368/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/rockchip/tinker_rk3288/Kconfig b/board/rockchip/tinker_rk3288/Kconfig
index f744a61..bca6c37 100644
--- a/board/rockchip/tinker_rk3288/Kconfig
+++ b/board/rockchip/tinker_rk3288/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/ronetix/pm9261/Kconfig b/board/ronetix/pm9261/Kconfig
index 58377b9..8c54198 100644
--- a/board/ronetix/pm9261/Kconfig
+++ b/board/ronetix/pm9261/Kconfig
@@ -10,4 +10,3 @@
default "pm9261"
endif
-
diff --git a/board/ronetix/pm9263/Kconfig b/board/ronetix/pm9263/Kconfig
index d866c6f..5b47d34 100644
--- a/board/ronetix/pm9263/Kconfig
+++ b/board/ronetix/pm9263/Kconfig
@@ -10,4 +10,3 @@
default "pm9263"
endif
-
diff --git a/board/ronetix/pm9g45/Kconfig b/board/ronetix/pm9g45/Kconfig
index 2d9b3c2..ad5309f 100644
--- a/board/ronetix/pm9g45/Kconfig
+++ b/board/ronetix/pm9g45/Kconfig
@@ -10,4 +10,3 @@
default "pm9g45"
endif
-
diff --git a/board/sagem/f@st1704/Kconfig b/board/sagem/f@st1704/Kconfig
index 2a68fa9..4566fcc 100644
--- a/board/sagem/f@st1704/Kconfig
+++ b/board/sagem/f@st1704/Kconfig
@@ -10,4 +10,3 @@
default "sagem_f@st1704"
endif
-
diff --git a/board/samsung/arndale/Kconfig b/board/samsung/arndale/Kconfig
index bd0d20e..b620974 100644
--- a/board/samsung/arndale/Kconfig
+++ b/board/samsung/arndale/Kconfig
@@ -10,4 +10,3 @@
default "arndale"
endif
-
diff --git a/board/samsung/espresso7420/Kconfig b/board/samsung/espresso7420/Kconfig
index 2fa7348..62251c5 100644
--- a/board/samsung/espresso7420/Kconfig
+++ b/board/samsung/espresso7420/Kconfig
@@ -14,4 +14,3 @@
default "espresso7420"
endif
-
diff --git a/board/samsung/goni/Kconfig b/board/samsung/goni/Kconfig
index 1c1ccfd..cbbf5a9 100644
--- a/board/samsung/goni/Kconfig
+++ b/board/samsung/goni/Kconfig
@@ -13,4 +13,3 @@
default "s5p_goni"
endif
-
diff --git a/board/samsung/odroid/Kconfig b/board/samsung/odroid/Kconfig
index 5747072..8b52a0d 100644
--- a/board/samsung/odroid/Kconfig
+++ b/board/samsung/odroid/Kconfig
@@ -10,4 +10,3 @@
default "odroid"
endif
-
diff --git a/board/samsung/origen/Kconfig b/board/samsung/origen/Kconfig
index bb69bee..63e3efe 100644
--- a/board/samsung/origen/Kconfig
+++ b/board/samsung/origen/Kconfig
@@ -10,4 +10,3 @@
default "origen"
endif
-
diff --git a/board/samsung/smdk5250/Kconfig b/board/samsung/smdk5250/Kconfig
index 5fe5dff..11ffaee 100644
--- a/board/samsung/smdk5250/Kconfig
+++ b/board/samsung/smdk5250/Kconfig
@@ -36,4 +36,3 @@
default "spring"
endif
-
diff --git a/board/samsung/smdk5420/Kconfig b/board/samsung/smdk5420/Kconfig
index 53df716..a9d62ff 100644
--- a/board/samsung/smdk5420/Kconfig
+++ b/board/samsung/smdk5420/Kconfig
@@ -49,4 +49,3 @@
default "smdk5420"
endif
-
diff --git a/board/samsung/smdkc100/Kconfig b/board/samsung/smdkc100/Kconfig
index 36462db..d2157b4 100644
--- a/board/samsung/smdkc100/Kconfig
+++ b/board/samsung/smdkc100/Kconfig
@@ -13,4 +13,3 @@
default "smdkc100"
endif
-
diff --git a/board/samsung/smdkv310/Kconfig b/board/samsung/smdkv310/Kconfig
index 9b59784..a6fd657 100644
--- a/board/samsung/smdkv310/Kconfig
+++ b/board/samsung/smdkv310/Kconfig
@@ -10,4 +10,3 @@
default "smdkv310"
endif
-
diff --git a/board/samsung/trats/Kconfig b/board/samsung/trats/Kconfig
index da8b6ee..7e8377b 100644
--- a/board/samsung/trats/Kconfig
+++ b/board/samsung/trats/Kconfig
@@ -10,4 +10,3 @@
default "trats"
endif
-
diff --git a/board/samsung/trats2/Kconfig b/board/samsung/trats2/Kconfig
index 39c05bd..5670e14 100644
--- a/board/samsung/trats2/Kconfig
+++ b/board/samsung/trats2/Kconfig
@@ -10,4 +10,3 @@
default "trats2"
endif
-
diff --git a/board/samsung/universal_c210/Kconfig b/board/samsung/universal_c210/Kconfig
index 3390d1e..e692668 100644
--- a/board/samsung/universal_c210/Kconfig
+++ b/board/samsung/universal_c210/Kconfig
@@ -10,4 +10,3 @@
default "s5pc210_universal"
endif
-
diff --git a/board/samtec/vining_2000/Kconfig b/board/samtec/vining_2000/Kconfig
index 06c4168..3447c27 100644
--- a/board/samtec/vining_2000/Kconfig
+++ b/board/samtec/vining_2000/Kconfig
@@ -10,4 +10,3 @@
default "vining_2000"
endif
-
diff --git a/board/sandisk/sansa_fuze_plus/Kconfig b/board/sandisk/sansa_fuze_plus/Kconfig
index 7d34c14..ab4a292 100644
--- a/board/sandisk/sansa_fuze_plus/Kconfig
+++ b/board/sandisk/sansa_fuze_plus/Kconfig
@@ -13,4 +13,3 @@
default "sansa_fuze_plus"
endif
-
diff --git a/board/sbc8349/Kconfig b/board/sbc8349/Kconfig
index a4b664f..129d6b9 100644
--- a/board/sbc8349/Kconfig
+++ b/board/sbc8349/Kconfig
@@ -7,4 +7,3 @@
default "sbc8349"
endif
-
diff --git a/board/sbc8548/Kconfig b/board/sbc8548/Kconfig
index 0b4886d..626cbdf 100644
--- a/board/sbc8548/Kconfig
+++ b/board/sbc8548/Kconfig
@@ -7,4 +7,3 @@
default "sbc8548"
endif
-
diff --git a/board/sbc8641d/Kconfig b/board/sbc8641d/Kconfig
index 4bedf2c..8dfc90c 100644
--- a/board/sbc8641d/Kconfig
+++ b/board/sbc8641d/Kconfig
@@ -7,4 +7,3 @@
default "sbc8641d"
endif
-
diff --git a/board/schulercontrol/sc_sps_1/Kconfig b/board/schulercontrol/sc_sps_1/Kconfig
index e52a69d..2461d0c 100644
--- a/board/schulercontrol/sc_sps_1/Kconfig
+++ b/board/schulercontrol/sc_sps_1/Kconfig
@@ -13,4 +13,3 @@
default "sc_sps_1"
endif
-
diff --git a/board/seco/Kconfig b/board/seco/Kconfig
index d07eccd..af16697 100644
--- a/board/seco/Kconfig
+++ b/board/seco/Kconfig
@@ -63,4 +63,3 @@
default "secomx6quq7" if SECOMX6_UQ7 && SECOMX6Q
endif
-
diff --git a/board/seeed/linkit-smart-7688/Kconfig b/board/seeed/linkit-smart-7688/Kconfig
index 6d272fc..a9d6328 100644
--- a/board/seeed/linkit-smart-7688/Kconfig
+++ b/board/seeed/linkit-smart-7688/Kconfig
@@ -10,4 +10,3 @@
default "linkit-smart-7688"
endif
-
diff --git a/board/sfr/nb4_ser/Kconfig b/board/sfr/nb4_ser/Kconfig
index f8ead7e..78aefb5 100644
--- a/board/sfr/nb4_ser/Kconfig
+++ b/board/sfr/nb4_ser/Kconfig
@@ -10,4 +10,3 @@
default "sfr_nb4_ser"
endif
-
diff --git a/board/shmin/Kconfig b/board/shmin/Kconfig
index e1eaf7a..467580c 100644
--- a/board/shmin/Kconfig
+++ b/board/shmin/Kconfig
@@ -7,4 +7,3 @@
default "shmin"
endif
-
diff --git a/board/siemens/corvus/Kconfig b/board/siemens/corvus/Kconfig
index 48d4586..69fe0f0 100644
--- a/board/siemens/corvus/Kconfig
+++ b/board/siemens/corvus/Kconfig
@@ -10,4 +10,3 @@
default "corvus"
endif
-
diff --git a/board/siemens/draco/Kconfig b/board/siemens/draco/Kconfig
index 1fe5a44..a699c7d 100644
--- a/board/siemens/draco/Kconfig
+++ b/board/siemens/draco/Kconfig
@@ -61,4 +61,3 @@
default "etamin"
endif
-
diff --git a/board/siemens/pxm2/Kconfig b/board/siemens/pxm2/Kconfig
index 9d08f1d..62604ec 100644
--- a/board/siemens/pxm2/Kconfig
+++ b/board/siemens/pxm2/Kconfig
@@ -13,4 +13,3 @@
default "pxm2"
endif
-
diff --git a/board/siemens/rut/Kconfig b/board/siemens/rut/Kconfig
index 9147db2..3371077 100644
--- a/board/siemens/rut/Kconfig
+++ b/board/siemens/rut/Kconfig
@@ -13,4 +13,3 @@
default "rut"
endif
-
diff --git a/board/siemens/smartweb/Kconfig b/board/siemens/smartweb/Kconfig
index b26a9bd..0871bcc 100644
--- a/board/siemens/smartweb/Kconfig
+++ b/board/siemens/smartweb/Kconfig
@@ -10,4 +10,3 @@
default "smartweb"
endif
-
diff --git a/board/siemens/taurus/Kconfig b/board/siemens/taurus/Kconfig
index abdb726..cf71e4c 100644
--- a/board/siemens/taurus/Kconfig
+++ b/board/siemens/taurus/Kconfig
@@ -10,4 +10,3 @@
default "taurus"
endif
-
diff --git a/board/silica/pengwyn/Kconfig b/board/silica/pengwyn/Kconfig
index 9414de1..f2e1098 100644
--- a/board/silica/pengwyn/Kconfig
+++ b/board/silica/pengwyn/Kconfig
@@ -13,4 +13,3 @@
default "pengwyn"
endif
-
diff --git a/board/sks-kinkel/sksimx6/Kconfig b/board/sks-kinkel/sksimx6/Kconfig
index 6a77cff..3efdf9d 100644
--- a/board/sks-kinkel/sksimx6/Kconfig
+++ b/board/sks-kinkel/sksimx6/Kconfig
@@ -9,4 +9,3 @@
config SYS_CONFIG_NAME
default "sksimx6"
endif
-
diff --git a/board/socrates/Kconfig b/board/socrates/Kconfig
index 7b1e5e7..ca945c2 100644
--- a/board/socrates/Kconfig
+++ b/board/socrates/Kconfig
@@ -7,4 +7,3 @@
default "socrates"
endif
-
diff --git a/board/solidrun/mx6cuboxi/Kconfig b/board/solidrun/mx6cuboxi/Kconfig
index 254b724..741c175 100644
--- a/board/solidrun/mx6cuboxi/Kconfig
+++ b/board/solidrun/mx6cuboxi/Kconfig
@@ -10,4 +10,3 @@
default "mx6cuboxi"
endif
-
diff --git a/board/spear/spear300/Kconfig b/board/spear/spear300/Kconfig
index 40dcc4d..27360f3 100644
--- a/board/spear/spear300/Kconfig
+++ b/board/spear/spear300/Kconfig
@@ -13,4 +13,3 @@
default "spear3xx_evb"
endif
-
diff --git a/board/spear/spear310/Kconfig b/board/spear/spear310/Kconfig
index a856940..0c95fa3 100644
--- a/board/spear/spear310/Kconfig
+++ b/board/spear/spear310/Kconfig
@@ -13,4 +13,3 @@
default "spear3xx_evb"
endif
-
diff --git a/board/spear/spear320/Kconfig b/board/spear/spear320/Kconfig
index 6ae6373..df17623 100644
--- a/board/spear/spear320/Kconfig
+++ b/board/spear/spear320/Kconfig
@@ -13,4 +13,3 @@
default "spear3xx_evb"
endif
-
diff --git a/board/spear/spear600/Kconfig b/board/spear/spear600/Kconfig
index b85a94b..d562e64 100644
--- a/board/spear/spear600/Kconfig
+++ b/board/spear/spear600/Kconfig
@@ -13,4 +13,3 @@
default "spear6xx_evb"
endif
-
diff --git a/board/spear/x600/Kconfig b/board/spear/x600/Kconfig
index 45309ca..59f2b1e 100644
--- a/board/spear/x600/Kconfig
+++ b/board/spear/x600/Kconfig
@@ -16,4 +16,3 @@
default "x600"
endif
-
diff --git a/board/st/stih410-b2260/Kconfig b/board/st/stih410-b2260/Kconfig
index ea1b14b..590add0 100644
--- a/board/st/stih410-b2260/Kconfig
+++ b/board/st/stih410-b2260/Kconfig
@@ -17,4 +17,3 @@
default "stih410-b2260"
endif
-
diff --git a/board/st/stm32f429-discovery/Kconfig b/board/st/stm32f429-discovery/Kconfig
index 89623eb..e73d11b 100644
--- a/board/st/stm32f429-discovery/Kconfig
+++ b/board/st/stm32f429-discovery/Kconfig
@@ -17,4 +17,3 @@
default "stm32f429-discovery"
endif
-
diff --git a/board/st/stm32f429-evaluation/Kconfig b/board/st/stm32f429-evaluation/Kconfig
index 5a73294..ca4bb3d 100644
--- a/board/st/stm32f429-evaluation/Kconfig
+++ b/board/st/stm32f429-evaluation/Kconfig
@@ -17,4 +17,3 @@
default "stm32f429-evaluation"
endif
-
diff --git a/board/st/stm32f469-discovery/Kconfig b/board/st/stm32f469-discovery/Kconfig
index ef85c9a..de61b6f 100644
--- a/board/st/stm32f469-discovery/Kconfig
+++ b/board/st/stm32f469-discovery/Kconfig
@@ -17,4 +17,3 @@
default "stm32f469-discovery"
endif
-
diff --git a/board/st/stm32f746-disco/Kconfig b/board/st/stm32f746-disco/Kconfig
index 9e0f419..09289d2 100644
--- a/board/st/stm32f746-disco/Kconfig
+++ b/board/st/stm32f746-disco/Kconfig
@@ -17,4 +17,3 @@
default "stm32f746-disco"
endif
-
diff --git a/board/st/stm32h743-disco/Kconfig b/board/st/stm32h743-disco/Kconfig
index 332090c..7d6ec1d 100644
--- a/board/st/stm32h743-disco/Kconfig
+++ b/board/st/stm32h743-disco/Kconfig
@@ -17,4 +17,3 @@
default "stm32h743-disco"
endif
-
diff --git a/board/st/stm32h743-eval/Kconfig b/board/st/stm32h743-eval/Kconfig
index eb32bcb..ea879b1 100644
--- a/board/st/stm32h743-eval/Kconfig
+++ b/board/st/stm32h743-eval/Kconfig
@@ -17,4 +17,3 @@
default "stm32h743-eval"
endif
-
diff --git a/board/st/stm32mp1/Kconfig b/board/st/stm32mp1/Kconfig
index a952e92..5ab9415 100644
--- a/board/st/stm32mp1/Kconfig
+++ b/board/st/stm32mp1/Kconfig
@@ -10,4 +10,3 @@
default "stm32mp1"
endif
-
diff --git a/board/st/stv0991/Kconfig b/board/st/stv0991/Kconfig
index 1ace477..007712f 100644
--- a/board/st/stv0991/Kconfig
+++ b/board/st/stv0991/Kconfig
@@ -13,4 +13,3 @@
default "stv0991"
endif
-
diff --git a/board/synopsys/Kconfig b/board/synopsys/Kconfig
index 7bb3642..27e5509 100644
--- a/board/synopsys/Kconfig
+++ b/board/synopsys/Kconfig
@@ -7,4 +7,3 @@
default "nsim"
endif
-
diff --git a/board/synopsys/axs10x/Kconfig b/board/synopsys/axs10x/Kconfig
index 5423c5e..dd1305a 100644
--- a/board/synopsys/axs10x/Kconfig
+++ b/board/synopsys/axs10x/Kconfig
@@ -10,4 +10,3 @@
default "axs10x"
endif
-
diff --git a/board/synopsys/emsdp/Kconfig b/board/synopsys/emsdp/Kconfig
index cf280dc..8228bb5 100644
--- a/board/synopsys/emsdp/Kconfig
+++ b/board/synopsys/emsdp/Kconfig
@@ -10,4 +10,3 @@
default "emsdp"
endif
-
diff --git a/board/synopsys/hsdk/Kconfig b/board/synopsys/hsdk/Kconfig
index ff9923e..e8c00a6 100644
--- a/board/synopsys/hsdk/Kconfig
+++ b/board/synopsys/hsdk/Kconfig
@@ -10,4 +10,3 @@
default "hsdk"
endif
-
diff --git a/board/synopsys/iot_devkit/Kconfig b/board/synopsys/iot_devkit/Kconfig
index 07a4d31..ad956b2 100644
--- a/board/synopsys/iot_devkit/Kconfig
+++ b/board/synopsys/iot_devkit/Kconfig
@@ -10,4 +10,3 @@
default "iot_devkit"
endif
-
diff --git a/board/sysam/stmark2/Kconfig b/board/sysam/stmark2/Kconfig
index 8a935c6..87ab7ab 100644
--- a/board/sysam/stmark2/Kconfig
+++ b/board/sysam/stmark2/Kconfig
@@ -13,4 +13,3 @@
default "stmark2"
endif
-
diff --git a/board/syteco/zmx25/Kconfig b/board/syteco/zmx25/Kconfig
index de639a7..59a415d 100644
--- a/board/syteco/zmx25/Kconfig
+++ b/board/syteco/zmx25/Kconfig
@@ -13,4 +13,3 @@
default "zmx25"
endif
-
diff --git a/board/tbs/tbs2910/Kconfig b/board/tbs/tbs2910/Kconfig
index cda7e17..2e5e1d4 100644
--- a/board/tbs/tbs2910/Kconfig
+++ b/board/tbs/tbs2910/Kconfig
@@ -16,4 +16,3 @@
default "board/tbs/tbs2910/tbs2910.cfg"
endif
-
diff --git a/board/tcl/sl50/Kconfig b/board/tcl/sl50/Kconfig
index 89f89d1..1b3f5cf 100644
--- a/board/tcl/sl50/Kconfig
+++ b/board/tcl/sl50/Kconfig
@@ -13,4 +13,3 @@
default "am335x_sl50"
endif
-
diff --git a/board/technexion/pico-imx6ul/Kconfig b/board/technexion/pico-imx6ul/Kconfig
index 0f6789a..81acd61 100644
--- a/board/technexion/pico-imx6ul/Kconfig
+++ b/board/technexion/pico-imx6ul/Kconfig
@@ -13,4 +13,3 @@
default "pico-imx6ul"
endif
-
diff --git a/board/technexion/pico-imx7d/Kconfig b/board/technexion/pico-imx7d/Kconfig
index 15dae46..f4ae18c 100644
--- a/board/technexion/pico-imx7d/Kconfig
+++ b/board/technexion/pico-imx7d/Kconfig
@@ -13,4 +13,3 @@
default "pico-imx7d"
endif
-
diff --git a/board/technexion/tao3530/Kconfig b/board/technexion/tao3530/Kconfig
index 750bac7..27bc91f 100644
--- a/board/technexion/tao3530/Kconfig
+++ b/board/technexion/tao3530/Kconfig
@@ -10,4 +10,3 @@
default "tao3530"
endif
-
diff --git a/board/technexion/twister/Kconfig b/board/technexion/twister/Kconfig
index 5103ce6..4c0ace8 100644
--- a/board/technexion/twister/Kconfig
+++ b/board/technexion/twister/Kconfig
@@ -10,4 +10,3 @@
default "twister"
endif
-
diff --git a/board/technologic/ts4600/Kconfig b/board/technologic/ts4600/Kconfig
index 6dc1935..d0dc2e1 100644
--- a/board/technologic/ts4600/Kconfig
+++ b/board/technologic/ts4600/Kconfig
@@ -13,4 +13,3 @@
default "ts4600"
endif
-
diff --git a/board/technologic/ts4800/Kconfig b/board/technologic/ts4800/Kconfig
index 7fdcf2c..a28d5e4 100644
--- a/board/technologic/ts4800/Kconfig
+++ b/board/technologic/ts4800/Kconfig
@@ -13,4 +13,3 @@
default "ts4800"
endif
-
diff --git a/board/teejet/mt_ventoux/Kconfig b/board/teejet/mt_ventoux/Kconfig
index 9fc13d3..fd7196a 100644
--- a/board/teejet/mt_ventoux/Kconfig
+++ b/board/teejet/mt_ventoux/Kconfig
@@ -10,4 +10,3 @@
default "mt_ventoux"
endif
-
diff --git a/board/theobroma-systems/lion_rk3368/Kconfig b/board/theobroma-systems/lion_rk3368/Kconfig
index df3cf24..fddbf82 100644
--- a/board/theobroma-systems/lion_rk3368/Kconfig
+++ b/board/theobroma-systems/lion_rk3368/Kconfig
@@ -19,4 +19,3 @@
default 0x3c000 if ENV_IS_IN_SPI_FLASH
endif
-
diff --git a/board/theobroma-systems/puma_rk3399/Kconfig b/board/theobroma-systems/puma_rk3399/Kconfig
index 4fcc404..8a94cbd 100644
--- a/board/theobroma-systems/puma_rk3399/Kconfig
+++ b/board/theobroma-systems/puma_rk3399/Kconfig
@@ -19,4 +19,3 @@
default 0x3c000 if ENV_IS_IN_SPI_FLASH
endif
-
diff --git a/board/ti/am335x/Kconfig b/board/ti/am335x/Kconfig
index 25bcf0f..b66ca1a 100644
--- a/board/ti/am335x/Kconfig
+++ b/board/ti/am335x/Kconfig
@@ -22,4 +22,3 @@
source "board/ti/common/Kconfig"
endif
-
diff --git a/board/ti/am3517crane/Kconfig b/board/ti/am3517crane/Kconfig
index ac68dc4..ad025a3 100644
--- a/board/ti/am3517crane/Kconfig
+++ b/board/ti/am3517crane/Kconfig
@@ -10,4 +10,3 @@
default "am3517_crane"
endif
-
diff --git a/board/ti/am43xx/Kconfig b/board/ti/am43xx/Kconfig
index a816836..9cb80cc 100644
--- a/board/ti/am43xx/Kconfig
+++ b/board/ti/am43xx/Kconfig
@@ -15,4 +15,3 @@
source "board/ti/common/Kconfig"
endif
-
diff --git a/board/ti/am57xx/Kconfig b/board/ti/am57xx/Kconfig
index 7065cc8..0c56682 100644
--- a/board/ti/am57xx/Kconfig
+++ b/board/ti/am57xx/Kconfig
@@ -12,4 +12,3 @@
source "board/ti/common/Kconfig"
endif
-
diff --git a/board/ti/am65x/Kconfig b/board/ti/am65x/Kconfig
index 079be07..d4b36db 100644
--- a/board/ti/am65x/Kconfig
+++ b/board/ti/am65x/Kconfig
@@ -50,4 +50,3 @@
default "arch/arm/mach-omap2/u-boot-spl.lds"
endif
-
diff --git a/board/ti/beagle/Kconfig b/board/ti/beagle/Kconfig
index 26d0c08..c2eff9e 100644
--- a/board/ti/beagle/Kconfig
+++ b/board/ti/beagle/Kconfig
@@ -10,4 +10,3 @@
default "omap3_beagle"
endif
-
diff --git a/board/ti/common/Kconfig b/board/ti/common/Kconfig
index 6dbf6f9..b1956b8 100644
--- a/board/ti/common/Kconfig
+++ b/board/ti/common/Kconfig
@@ -41,4 +41,3 @@
imply CMD_SPI
imply CMD_TIME
imply CMD_USB if USB
-
diff --git a/board/ti/dra7xx/Kconfig b/board/ti/dra7xx/Kconfig
index 7be1bc5..f6a8e07 100644
--- a/board/ti/dra7xx/Kconfig
+++ b/board/ti/dra7xx/Kconfig
@@ -12,4 +12,3 @@
source "board/ti/common/Kconfig"
endif
-
diff --git a/board/ti/evm/Kconfig b/board/ti/evm/Kconfig
index fbf4e16..4f490dd 100644
--- a/board/ti/evm/Kconfig
+++ b/board/ti/evm/Kconfig
@@ -10,4 +10,3 @@
default "omap3_evm"
endif
-
diff --git a/board/ti/ks2_evm/Kconfig b/board/ti/ks2_evm/Kconfig
index 6d37a4c..9477f53 100644
--- a/board/ti/ks2_evm/Kconfig
+++ b/board/ti/ks2_evm/Kconfig
@@ -51,4 +51,3 @@
endif
source "board/ti/common/Kconfig"
-
diff --git a/board/ti/omap5_uevm/Kconfig b/board/ti/omap5_uevm/Kconfig
index 32e8a1e..aa13844 100644
--- a/board/ti/omap5_uevm/Kconfig
+++ b/board/ti/omap5_uevm/Kconfig
@@ -10,4 +10,3 @@
default "omap5_uevm"
endif
-
diff --git a/board/ti/panda/Kconfig b/board/ti/panda/Kconfig
index 03a8870..8f277b6 100644
--- a/board/ti/panda/Kconfig
+++ b/board/ti/panda/Kconfig
@@ -10,4 +10,3 @@
default "omap4_panda"
endif
-
diff --git a/board/ti/sdp4430/Kconfig b/board/ti/sdp4430/Kconfig
index 0a45b52..36f1852 100644
--- a/board/ti/sdp4430/Kconfig
+++ b/board/ti/sdp4430/Kconfig
@@ -13,4 +13,3 @@
bool "Enable board-specific battery command"
endif
-
diff --git a/board/ti/ti814x/Kconfig b/board/ti/ti814x/Kconfig
index c42fec1..2960099 100644
--- a/board/ti/ti814x/Kconfig
+++ b/board/ti/ti814x/Kconfig
@@ -13,4 +13,3 @@
default "ti814x_evm"
endif
-
diff --git a/board/ti/ti816x/Kconfig b/board/ti/ti816x/Kconfig
index 10f6257..95973b4 100644
--- a/board/ti/ti816x/Kconfig
+++ b/board/ti/ti816x/Kconfig
@@ -13,4 +13,3 @@
default "ti816x_evm"
endif
-
diff --git a/board/timll/devkit3250/Kconfig b/board/timll/devkit3250/Kconfig
index 349116d..5129c2d 100644
--- a/board/timll/devkit3250/Kconfig
+++ b/board/timll/devkit3250/Kconfig
@@ -10,4 +10,3 @@
default "devkit3250"
endif
-
diff --git a/board/timll/devkit8000/Kconfig b/board/timll/devkit8000/Kconfig
index bd49449..3c63ced 100644
--- a/board/timll/devkit8000/Kconfig
+++ b/board/timll/devkit8000/Kconfig
@@ -10,4 +10,3 @@
default "devkit8000"
endif
-
diff --git a/board/toradex/apalis-tk1/Kconfig b/board/toradex/apalis-tk1/Kconfig
index da34990..159b8fb 100644
--- a/board/toradex/apalis-tk1/Kconfig
+++ b/board/toradex/apalis-tk1/Kconfig
@@ -36,4 +36,3 @@
source "board/toradex/common/Kconfig"
endif
-
diff --git a/board/toradex/apalis_imx6/Kconfig b/board/toradex/apalis_imx6/Kconfig
index 97a3ecf..14f8c10 100644
--- a/board/toradex/apalis_imx6/Kconfig
+++ b/board/toradex/apalis_imx6/Kconfig
@@ -53,4 +53,3 @@
source "board/toradex/common/Kconfig"
endif
-
diff --git a/board/toradex/apalis_t30/Kconfig b/board/toradex/apalis_t30/Kconfig
index aee322e..9cd4970 100644
--- a/board/toradex/apalis_t30/Kconfig
+++ b/board/toradex/apalis_t30/Kconfig
@@ -37,4 +37,3 @@
source "board/toradex/common/Kconfig"
endif
-
diff --git a/board/toradex/colibri-imx6ull/Kconfig b/board/toradex/colibri-imx6ull/Kconfig
index d83e67d..3ce9885 100644
--- a/board/toradex/colibri-imx6ull/Kconfig
+++ b/board/toradex/colibri-imx6ull/Kconfig
@@ -27,4 +27,3 @@
source "board/toradex/common/Kconfig"
endif
-
diff --git a/board/toradex/colibri_imx6/Kconfig b/board/toradex/colibri_imx6/Kconfig
index 3961fb6..d2ad1ce 100644
--- a/board/toradex/colibri_imx6/Kconfig
+++ b/board/toradex/colibri_imx6/Kconfig
@@ -42,4 +42,3 @@
source "board/toradex/common/Kconfig"
endif
-
diff --git a/board/toradex/colibri_imx7/Kconfig b/board/toradex/colibri_imx7/Kconfig
index fc82124..d33ec63 100644
--- a/board/toradex/colibri_imx7/Kconfig
+++ b/board/toradex/colibri_imx7/Kconfig
@@ -74,4 +74,3 @@
source "board/toradex/common/Kconfig"
endif
-
diff --git a/board/toradex/colibri_pxa270/Kconfig b/board/toradex/colibri_pxa270/Kconfig
index 5289239..f646baa 100644
--- a/board/toradex/colibri_pxa270/Kconfig
+++ b/board/toradex/colibri_pxa270/Kconfig
@@ -21,4 +21,3 @@
source "board/toradex/common/Kconfig"
endif
-
diff --git a/board/toradex/colibri_t20/Kconfig b/board/toradex/colibri_t20/Kconfig
index 9128572..a43acdd 100644
--- a/board/toradex/colibri_t20/Kconfig
+++ b/board/toradex/colibri_t20/Kconfig
@@ -21,4 +21,3 @@
source "board/toradex/common/Kconfig"
endif
-
diff --git a/board/toradex/colibri_t30/Kconfig b/board/toradex/colibri_t30/Kconfig
index 204a5ff..68ef82b 100644
--- a/board/toradex/colibri_t30/Kconfig
+++ b/board/toradex/colibri_t30/Kconfig
@@ -28,4 +28,3 @@
source "board/toradex/common/Kconfig"
endif
-
diff --git a/board/toradex/colibri_vf/Kconfig b/board/toradex/colibri_vf/Kconfig
index f58a344..5f7129d 100644
--- a/board/toradex/colibri_vf/Kconfig
+++ b/board/toradex/colibri_vf/Kconfig
@@ -24,4 +24,3 @@
source "board/toradex/common/Kconfig"
endif
-
diff --git a/board/toradex/common/Kconfig b/board/toradex/common/Kconfig
index 0548bd1..11f4aab 100644
--- a/board/toradex/common/Kconfig
+++ b/board/toradex/common/Kconfig
@@ -67,4 +67,3 @@
second Ethernet address as environment variable (eth1addr).
endif
-
diff --git a/board/tplink/wdr4300/Kconfig b/board/tplink/wdr4300/Kconfig
index 92fb6fd..67a0228 100644
--- a/board/tplink/wdr4300/Kconfig
+++ b/board/tplink/wdr4300/Kconfig
@@ -28,4 +28,3 @@
default 32
endif
-
diff --git a/board/tqc/tqm834x/Kconfig b/board/tqc/tqm834x/Kconfig
index 26ef963..028b846 100644
--- a/board/tqc/tqm834x/Kconfig
+++ b/board/tqc/tqm834x/Kconfig
@@ -10,4 +10,3 @@
default "TQM834x"
endif
-
diff --git a/board/tqc/tqma6/Kconfig b/board/tqc/tqma6/Kconfig
index d30c580..6df4134 100644
--- a/board/tqc/tqma6/Kconfig
+++ b/board/tqc/tqma6/Kconfig
@@ -80,4 +80,3 @@
default "board/tqc/tqma6/tqma6s.cfg" if TQMA6S
endif
-
diff --git a/board/ucRobotics/bubblegum_96/Kconfig b/board/ucRobotics/bubblegum_96/Kconfig
index c789609..2dd40d9 100644
--- a/board/ucRobotics/bubblegum_96/Kconfig
+++ b/board/ucRobotics/bubblegum_96/Kconfig
@@ -13,4 +13,3 @@
default "bubblegum_96"
endif
-
diff --git a/board/udoo/Kconfig b/board/udoo/Kconfig
index 6c4c859..78617a2 100644
--- a/board/udoo/Kconfig
+++ b/board/udoo/Kconfig
@@ -7,4 +7,3 @@
default "udoo"
endif
-
diff --git a/board/udoo/neo/Kconfig b/board/udoo/neo/Kconfig
index 66a50de..8f474df 100644
--- a/board/udoo/neo/Kconfig
+++ b/board/udoo/neo/Kconfig
@@ -10,4 +10,3 @@
default "udoo_neo"
endif
-
diff --git a/board/vamrs/rock960_rk3399/Kconfig b/board/vamrs/rock960_rk3399/Kconfig
index e95caed..cacc53f 100644
--- a/board/vamrs/rock960_rk3399/Kconfig
+++ b/board/vamrs/rock960_rk3399/Kconfig
@@ -13,4 +13,3 @@
def_bool y
endif
-
diff --git a/board/varisys/cyrus/Kconfig b/board/varisys/cyrus/Kconfig
index 15c64f9..a0389f8 100644
--- a/board/varisys/cyrus/Kconfig
+++ b/board/varisys/cyrus/Kconfig
@@ -12,4 +12,3 @@
source "board/freescale/common/Kconfig"
endif
-
diff --git a/board/ve8313/Kconfig b/board/ve8313/Kconfig
index a8ab3df..a63744b 100644
--- a/board/ve8313/Kconfig
+++ b/board/ve8313/Kconfig
@@ -7,4 +7,3 @@
default "ve8313"
endif
-
diff --git a/board/vscom/baltos/Kconfig b/board/vscom/baltos/Kconfig
index 8cae231..b721ed1 100644
--- a/board/vscom/baltos/Kconfig
+++ b/board/vscom/baltos/Kconfig
@@ -13,4 +13,3 @@
default "baltos"
endif
-
diff --git a/board/wandboard/Kconfig b/board/wandboard/Kconfig
index e140fd7..def6369 100644
--- a/board/wandboard/Kconfig
+++ b/board/wandboard/Kconfig
@@ -7,4 +7,3 @@
default "wandboard"
endif
-
diff --git a/board/warp/Kconfig b/board/warp/Kconfig
index 69d2e4c..dc02636 100644
--- a/board/warp/Kconfig
+++ b/board/warp/Kconfig
@@ -7,4 +7,3 @@
default "warp"
endif
-
diff --git a/board/warp7/Kconfig b/board/warp7/Kconfig
index a5b4eea..c089bca 100644
--- a/board/warp7/Kconfig
+++ b/board/warp7/Kconfig
@@ -21,4 +21,3 @@
The address the FDT file should be loaded to.
endif
-
diff --git a/board/woodburn/Kconfig b/board/woodburn/Kconfig
index cac5a97..4699526 100644
--- a/board/woodburn/Kconfig
+++ b/board/woodburn/Kconfig
@@ -23,4 +23,3 @@
default "woodburn_sd"
endif
-
diff --git a/board/work-microwave/work_92105/Kconfig b/board/work-microwave/work_92105/Kconfig
index 4eeb5a2..32632f5 100644
--- a/board/work-microwave/work_92105/Kconfig
+++ b/board/work-microwave/work_92105/Kconfig
@@ -22,4 +22,3 @@
This allows PMIC registers to be read and written.
endif
-
diff --git a/board/xes/xpedite517x/Kconfig b/board/xes/xpedite517x/Kconfig
index 298939b..91bbd22 100644
--- a/board/xes/xpedite517x/Kconfig
+++ b/board/xes/xpedite517x/Kconfig
@@ -10,4 +10,3 @@
default "xpedite517x"
endif
-
diff --git a/board/xes/xpedite520x/Kconfig b/board/xes/xpedite520x/Kconfig
index 3a6b072..9c0c246 100644
--- a/board/xes/xpedite520x/Kconfig
+++ b/board/xes/xpedite520x/Kconfig
@@ -10,4 +10,3 @@
default "xpedite520x"
endif
-
diff --git a/board/xes/xpedite537x/Kconfig b/board/xes/xpedite537x/Kconfig
index c4f20df..35b3917 100644
--- a/board/xes/xpedite537x/Kconfig
+++ b/board/xes/xpedite537x/Kconfig
@@ -10,4 +10,3 @@
default "xpedite537x"
endif
-
diff --git a/board/xes/xpedite550x/Kconfig b/board/xes/xpedite550x/Kconfig
index 77f617d..1b00137 100644
--- a/board/xes/xpedite550x/Kconfig
+++ b/board/xes/xpedite550x/Kconfig
@@ -10,4 +10,3 @@
default "xpedite550x"
endif
-
diff --git a/board/xilinx/Kconfig b/board/xilinx/Kconfig
index d563ed9..37bec5f 100644
--- a/board/xilinx/Kconfig
+++ b/board/xilinx/Kconfig
@@ -39,4 +39,3 @@
before the build.
endif
-
diff --git a/board/xilinx/microblaze-generic/Kconfig b/board/xilinx/microblaze-generic/Kconfig
index b7a2b2c..f2fa0f7 100644
--- a/board/xilinx/microblaze-generic/Kconfig
+++ b/board/xilinx/microblaze-generic/Kconfig
@@ -39,4 +39,3 @@
default "7.10.d"
endif
-
diff --git a/board/xilinx/zynq/Kconfig b/board/xilinx/zynq/Kconfig
index 635fcba..d6f4063 100644
--- a/board/xilinx/zynq/Kconfig
+++ b/board/xilinx/zynq/Kconfig
@@ -31,4 +31,3 @@
BOOT.BIN using Xilinx bootgen tool.
endif
-
diff --git a/board/xilinx/zynqmp/Kconfig b/board/xilinx/zynqmp/Kconfig
index a55df47..7d1f739 100644
--- a/board/xilinx/zynqmp/Kconfig
+++ b/board/xilinx/zynqmp/Kconfig
@@ -16,4 +16,3 @@
BOOT.BIN using Xilinx bootgen tool.
endif
-
diff --git a/board/zipitz2/Kconfig b/board/zipitz2/Kconfig
index 66d9b38..c663504 100644
--- a/board/zipitz2/Kconfig
+++ b/board/zipitz2/Kconfig
@@ -7,4 +7,3 @@
default "zipitz2"
endif
-
diff --git a/board/zyxel/nsa310s/Kconfig b/board/zyxel/nsa310s/Kconfig
index c1457bb..801d696 100644
--- a/board/zyxel/nsa310s/Kconfig
+++ b/board/zyxel/nsa310s/Kconfig
@@ -16,4 +16,3 @@
default "nsa310s"
endif
-
diff --git a/build_uboot.sh b/build_uboot.sh
deleted file mode 100755
index a78b8c1..0000000
--- a/build_uboot.sh
+++ /dev/null
@@ -1,165 +0,0 @@
-#!/bin/bash
-set -x
-exec_name=$0
-
-set -o errtrace
-trap 'echo Fatal error: script ${exec_name} aborting at line $LINENO, command \"$BASH_COMMAND\" returned $?; exit 1' ERR
-
-cpu_num=$(grep -c processor /proc/cpuinfo)
-
-DIR="$( cd "$( dirname "${BASH_SOURCE[0]}" )" && pwd )"
-echo DIR:$DIR
-
-function usage(){
- echo "Usage: ${exec_name} <board> [workspace path]"
- echo "supported boards: estelle-p1, estelle-p2"
- echo " newman-p2, newman-p2_1, newman-b1, newman-b3, newman-b4"
- echo " legion-p1"
- echo " puddy-p0"
- echo " elaine-p1, elaine-p2, elaine-b1, elaine-b3, elaine-b4"
-}
-
-readonly fct_options="--ddrenable --bftenable"
-readonly fsi_folder="bootloader"
-readonly fct_folder="factory/bootloader"
-readonly fsi="$fsi_folder:"
-readonly fct="$fct_folder:$fct_options"
-
-function building_uboot(){
- soc_family_name=$1
- local_name=$2
- rev=$3
- board_name=$4
- cfg_suffix=$6
-
- config=${local_name}_${rev}${cfg_suffix}
-
- for cfg in "$fsi" "$fct"; do
- local folder="${cfg%:*}"
- local options="${cfg#*:}"
- local print_flag="${folder%/*}"
-
- echo "building u-boot for ${board} in ${folder}"
-
- if [ ${print_flag} == "factory" ]; then
- print_flag=debug
- else
- print_flag=$5
- fi
- echo "print_flag: $print_flag"
-
- ./mk ${config} --board_name $board_name --bl2 fip/${soc_family_name}/bl2.bin --bl30 fip/${soc_family_name}/bl30.bin --bl31 fip/${soc_family_name}/bl31.img --bl32 fip/${soc_family_name}/bl32.img $print_flag $options
-
- # make T=1 to use latest git commit time as build timestamp.
-
- echo "mk done\n"
-
- local product=`echo ${board} | cut -d "-" -f1`
- local bootloader_path=${workspace_path}/vendor/amlogic/${product}/prebuilt/${folder}
-
- if [ ! -z $workspace_path ]; then
- mkdir -p ${bootloader_path}
- if [ "$product" == "estelle" ] || [ "$product" == "newman" ] || [ "$product" == "legion" ] || [ "$product" == "puddy" ] || [ "$product" == "elaine" ] ; then
- # Copy bl2 and bl3x images for bootloader signing under eureka source.
- cp fip/build/bl2_new.bin ${bootloader_path}/bl2_new.bin.${board}
- cp fip/build/bl30_new.bin ${bootloader_path}/bl30_new.bin.${board}
- cp fip/build/bl31.img ${bootloader_path}/bl31.img.${board}
- cp fip/build/bl32.img ${bootloader_path}/bl32.img.${board}
- cp fip/build/bl33.bin ${bootloader_path}/bl33.bin.${board}
-
- # Copy ddr bin for bootloader signing under eureka source.
- # TODO(ljchen): Remove hard code of ddr files under vendor/amlogic.
- cp fip/${soc_family_name}/ddr4_1d.fw ${bootloader_path}/
- cp fip/${soc_family_name}/ddr4_2d.fw ${bootloader_path}/
- cp fip/${soc_family_name}/ddr3_1d.fw ${bootloader_path}/
- cp fip/${soc_family_name}/piei.fw ${bootloader_path}/
- cp fip/${soc_family_name}/lpddr4_1d.fw ${bootloader_path}/
- cp fip/${soc_family_name}/lpddr4_2d.fw ${bootloader_path}/
- cp fip/${soc_family_name}/diag_lpddr4.fw ${bootloader_path}/
- cp fip/${soc_family_name}/aml_ddr.fw ${bootloader_path}/
-
- else
- cp fip/${soc_family_name}/u-boot.bin.usb.bl2 ${bootloader_path}/u-boot.bin.usb.bl2
- cp fip/${soc_family_name}/u-boot.bin.usb.tpl ${bootloader_path}/u-boot.bin.usb.tpl
- cp fip/${soc_family_name}/u-boot.bin ${bootloader_path}/u-boot.bin
- fi
- fi
- done
-}
-
-if (( $# < 1 ))
-then
- usage
- exit 2
-fi
-
-pushd $DIR
-
-readonly board=$1
-readonly workspace_path=$2
-readonly cross_compile=$DIR/../amlogic/linaro/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-
-readonly cross_compile_t32=$DIR/../amlogic/linaro/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-
-readonly vendor_amlogic=$DIR/../vendor/amlogic
-
-dbg_flag="debug"
-zircon_cfg=""
-
-if [ "$3" = "release" -o "$4" = "release" ]; then
- dbg_flag="release"
-elif [ "$4" = "zircon" -o "$5" = "zircon" ]; then
- zircon_cfg="_zircon"
-fi
-
-
-export ENABLE_UBOOT_UPDATE=1
-
-case $board in
- estelle-p1)
- building_uboot g12a g12a_estelle p1 $board
- ;;
- estelle-p2)
- building_uboot g12a g12a_estelle p2 $board
- ;;
- newman-p2)
- building_uboot g12b g12b_newman px $board $dbg_flag $zircon_cfg
- ;;
- newman-p2_1)
- building_uboot g12b g12b_newman p2_1 $board $dbg_flag $zircon_cfg
- ;;
- newman-b1|newman-b3)
- building_uboot g12b g12b_newman bx $board $dbg_flag $zircon_cfg
- ;;
- newman-b4)
- export ENABLE_UBOOT_UPDATE=0
- building_uboot g12b g12b_newman bx $board $dbg_flag $zircon_cfg
- ;;
- legion-p1)
- building_uboot g12a gl2a_legion p1 $board
- ;;
- puddy-p0)
- building_uboot g12b g12b_puddy px $board $dbg_flag $zircon_cfg
- ;;
- elaine-p0)
- building_uboot sm1 sm1_elaine p0 $board $dbg_flag
- ;;
- elaine-p1)
- building_uboot sm1 sm1_elaine p1 $board $dbg_flag
- ;;
- elaine-p2)
- building_uboot sm1 sm1_elaine p2 $board $dbg_flag
- ;;
- elaine-b1)
- building_uboot sm1 sm1_elaine b1 $board $dbg_flag
- ;;
- elaine-b3)
- building_uboot sm1 sm1_elaine bx $board $dbg_flag
- ;;
- elaine-b4)
- export ENABLE_UBOOT_UPDATE=0
- building_uboot sm1 sm1_elaine bx $board $dbg_flag
- ;;
- *)
- echo "unknown board: $board"
- exit 1
-esac
-popd
diff --git a/check_compile.sh b/check_compile.sh
new file mode 100755
index 0000000..ac7ba68
--- /dev/null
+++ b/check_compile.sh
@@ -0,0 +1,200 @@
+#!/bin/bash
+
+#------------IMPORTANT------------#
+#--RUN THIS SCRIPT BEFOR COMMIT---#
+#---------------------------------#
+
+# Author: xiaobo.gu@amlogic.com
+# Init version: 20160329
+
+#usage:
+#
+#./check_compile.sh -check amlogic board configs
+#./check_compile.sh cus -check customer board configs
+#./check_compile.sh all -check both amlogic and customer boards
+
+
+folder_board="board/amlogic/defconfigs"
+customer_folder="customer/board/defconfigs"
+
+echo "************** Amlogic Compile Check Tool **************"
+
+# filters define:
+# cus: all customer board
+# all: all boards
+# other:
+# gxb: all gxbaby board
+# gxtvbb: all gxtvbb board
+# skt: all socket board
+# p200: p200 board
+# etc.....
+declare filter="$1"
+
+# ARRAY_CFG store config names
+declare -a ARRAY_CFG
+declare -a ARRAY_CFG_C
+# TOTAL_CFG store config total num
+declare -i TOTAL_CFG
+declare -i TOTAL_CFG_C
+
+# if filter!=cus, then include amlogic configs
+# get all configs name from board folder
+if [ "$2" != "" -a "$3" == "" ]
+then
+ ARRAY_CFG[$TOTAL_CFG]=$2
+ TOTAL_CFG=$TOTAL_CFG+1
+fi
+if [ "$2" != "" -a "$3" != "" ]
+then
+ ARRAY_CFG[$TOTAL_CFG]=$3
+ TOTAL_CFG=$TOTAL_CFG+1
+fi
+
+
+if [ "$1" != "cus" -a "$2" == "" -a "$3" == "" ]
+then
+ filter=$1
+ for file in ${folder_board}/*; do
+ temp_file=`basename $file`
+ # del "_defconfig"
+ temp_file=${temp_file%_*}
+ echo "$temp_file"
+ ARRAY_CFG[$TOTAL_CFG]=$temp_file
+ TOTAL_CFG=$TOTAL_CFG+1
+ done
+fi
+
+# if filter==all || filter==cus, then include customer configs
+# get all customer configs name from customer board folder
+if [ "$1" == "cus" ] || [ "$1" == "all" ]
+then
+ filter=""
+ if [ -e ${customer_folder} ];then
+ for file in ${customer_folder}/*; do
+ temp_file=`basename $file`
+ temp_file=${temp_file%_*}
+ #echo $temp_file
+ ARRAY_CFG_C[$TOTAL_CFG_C]=$temp_file
+ TOTAL_CFG_C=$TOTAL_CFG_C+1
+ done
+ fi
+fi
+
+echo "************************ START *************************"
+
+# compile check start
+# RESULT store compile result
+declare RESULT=""
+declare -i LOOP_NUM=0
+# counter variables
+declare -i PASS_COUNTER=0
+declare -i FAIL_COUNTER=0
+
+# print bar and alignment
+declare -i BAR_TOTAL=30
+declare -i BAR_LOOP
+
+# trying fix scp task compile failure misreport issue
+declare -i BUILD_COUNTER=3
+declare -i BUILD_RESULT=0
+
+RESULT=$RESULT"########### Compile Check Result ###########\n"
+
+if [ "$1" != "cus" ]
+then
+ RESULT=$RESULT"--------------------------------------------\n"
+ RESULT=$RESULT"############## Amlogic Boards ##############\n"
+ # loop all cfgs
+ for cfg in ${ARRAY_CFG[@]}
+ do
+ # find filter in config name
+ if [[ $(echo $cfg | grep "${filter}") == "" ]]
+ then
+ # skip !filter configs
+ continue
+ fi
+ LOOP_NUM=$LOOP_NUM+1
+ RESULT=$RESULT' '
+ # print '0' charactors for alignment
+ BAR_LOOP=3-`expr length $LOOP_NUM`
+ if [ "$BAR_LOOP" -gt "0" ]
+ then
+ for tmp in `seq $BAR_LOOP`;do RESULT=$RESULT'0';done
+ fi
+ RESULT=$RESULT$LOOP_NUM' '
+ RESULT=$RESULT$cfg' '
+ # print '-' charactors for alignment
+ BAR_LOOP=BAR_TOTAL-`expr length $cfg`
+ if [ "$BAR_LOOP" -gt "0" ]
+ then
+ for tmp in `seq $BAR_LOOP`;do RESULT=$RESULT'-';done
+ fi
+ # compile
+ BUILD_COUNTER=3
+ BUILD_RESULT=0
+ while [ "${BUILD_COUNTER}" -gt "0" ]; do
+ BUILD_COUNTER=$((BUILD_COUNTER - 1))
+ make distclean
+ make $cfg'_defconfig'
+ make -j
+ # check last 'make -j' result
+ if [ $? != 0 ]; then
+ BUILD_RESULT=$((BUILD_RESULT + 1))
+ else
+ BUILD_RESULT=0
+ BUILD_COUNTER=0
+ fi
+ done
+ # check compile result
+ if [ ${BUILD_RESULT} != 0 ]; then
+ RESULT=$RESULT'- failed\n'
+ FAIL_COUNTER=$FAIL_COUNTER+1
+ else
+ RESULT=$RESULT'- pass\n'
+ PASS_COUNTER=$PASS_COUNTER+1
+ fi
+ # print result
+ echo -e $RESULT
+ #echo $cfg
+ done
+fi
+
+# check customer configs
+if [ "$1" == "cus" ] || [ "$1" == "all" ]
+then
+ RESULT=$RESULT"--------------------------------------------\n"
+ RESULT=$RESULT"############## Customer Boards #############\n"
+ for cfg in ${ARRAY_CFG_C[@]}
+ do
+ LOOP_NUM=$LOOP_NUM+1
+ RESULT=$RESULT' '
+ BAR_LOOP=3-`expr length $LOOP_NUM`
+ if [ "$BAR_LOOP" -gt "0" ]
+ then
+ for tmp in `seq $BAR_LOOP`;do RESULT=$RESULT'0';done
+ fi
+ RESULT=$RESULT$LOOP_NUM' '
+ RESULT=$RESULT$cfg' '
+ BAR_LOOP=BAR_TOTAL-`expr length $cfg`
+ if [ "$BAR_LOOP" -gt "0" ]
+ then
+ for tmp in `seq $BAR_LOOP`;do RESULT=$RESULT'-';done
+ fi
+ make distclean
+ make $cfg'_defconfig'
+ make -j
+ if [ $? != 0 ]
+ then
+ RESULT=$RESULT'- failed\n'
+ FAIL_COUNTER=$FAIL_COUNTER+1
+ else
+ RESULT=$RESULT'- pass\n'
+ PASS_COUNTER=$PASS_COUNTER+1
+ fi
+ echo -e $RESULT
+ done
+fi
+
+echo -e "#################### END ###################\n"
+
+exit $FAIL_COUNTER
diff --git a/cmd/Kconfig b/cmd/Kconfig
index d0407db..b417b7d 100644
--- a/cmd/Kconfig
+++ b/cmd/Kconfig
@@ -53,13 +53,6 @@
This string is displayed in the command line to the left of the
cursor.
-config CLI_ENABLED
- bool "CLI Enabled"
- default n
- help
- Enables U-Boot command line interface. If this is not enabled,
- no command line access will be available.
-
menu "Autoboot options"
config AUTOBOOT
@@ -202,6 +195,7 @@
config CMD_BOOTD
bool "bootd"
default y
+ depends on !AML_DISABLE_DEV_CMDS
help
Run the command stored in the environment "bootcmd", i.e.
"bootd" does the same thing as "run bootcmd".
@@ -214,12 +208,14 @@
config CMD_BOOTZ
bool "bootz"
+ depends on !AML_DISABLE_DEV_CMDS
help
Boot the Linux zImage
config CMD_BOOTI
bool "booti"
depends on ARM64
+ depends on !AML_DISABLE_DEV_CMDS
default y
help
Boot an AArch64 Linux Kernel image from memory.
@@ -253,6 +249,19 @@
for testing that EFI is working at a basic level, and for bringing
up EFI support on a new architecture.
+
+config CMD_DSPRUN
+ bool "dsprun cmd"
+ default y
+ help
+ support dsprun cmd
+
+config CMD_DSPSET
+ bool "dspset cmd"
+ default y
+ help
+ support dspset cmd
+
source lib/efi_selftest/Kconfig
config CMD_BOOTMENU
@@ -284,7 +293,7 @@
config CMD_GO
bool "go"
- default y
+ default n
help
Start an application at a given address.
@@ -526,6 +535,7 @@
config CMD_MEMORY
bool "md, mm, nm, mw, cp, cmp, base, loop"
default y
+ depends on !AML_DISABLE_DEV_CMDS
help
Memory commands.
md - memory display
@@ -636,6 +646,11 @@
clock values from associated drivers. However currently no command
exists for this.
+config CMD_CLKMSR
+ bool "clkmsr - Show clock measurement for different clock index"
+ help
+ Show clock measurement for different clock index
+
config CMD_DEMO
bool "demo - Demonstration commands for driver model"
depends on DM
@@ -885,9 +900,15 @@
default y if NAND_SUNXI
default y if MESON_NFC
default y if SPI_NAND
+ default y if MTD_SPI_NAND
help
NAND support.
+config AML_STORAGE
+ bool "aml storage support"
+ help
+ storage cmd support
+
if CMD_NAND
config CMD_NAND_TRIMFFS
bool "nand write.trimffs"
@@ -1104,6 +1125,10 @@
help
SARADC support.
+config CMD_IR
+ bool "ir"
+ help
+ IR support.
endmenu
@@ -1124,6 +1149,7 @@
config CMD_SOURCE
bool "source"
default y
+ depends on !AML_DISABLE_DEV_CMDS
help
Run script from memory
@@ -1893,6 +1919,8 @@
avb verify - run full verification chain
endmenu
+source "cmd/amlogic/Kconfig"
+
config CMD_UBI
tristate "Enable UBI - Unsorted block images commands"
select CRC32
@@ -1921,13 +1949,29 @@
help
CMD_WATCHDOG support.
+config CMD_JTAG
+ bool "CMD_JTAG"
+ depends on MISC
+ depends on !AML_DISABLE_DEV_CMDS
+ help
+ CMD_JTAG support.
+
config CMD_EFUSE
bool "support efuse command"
default y
help
support efuse command
+config CMD_INI
+ bool "support ini command"
+ default n
+ help
+ support ini command
+
+config CMD_TCPC
+ bool "tcpc command"
+ default n
+ help
+ support tcpc command
+
endmenu
-
-source "cmd/amlogic/Kconfig"
-
diff --git a/cmd/Makefile b/cmd/Makefile
index 4695061..fa6d98a 100644
--- a/cmd/Makefile
+++ b/cmd/Makefile
@@ -10,6 +10,7 @@
obj-y += help.o
obj-y += version.o
obj-$(CONFIG_CMD_MMC) += aml_mmc.o
+obj-$(CONFIG_SPI_NAND) += spi_nand.o
# command
obj-$(CONFIG_CMD_AES) += aes.o
@@ -33,6 +34,7 @@
obj-$(CONFIG_CMD_CACHE) += cache.o
obj-$(CONFIG_CMD_CBFS) += cbfs.o
obj-$(CONFIG_CMD_CLK) += clk.o
+obj-$(CONFIG_CMD_CLKMSR)+= clkmsr.o
obj-$(CONFIG_CMD_CLS) += cls.o
obj-$(CONFIG_CMD_CONFIG) += config.o
obj-$(CONFIG_CMD_CONITRACE) += conitrace.o
@@ -71,10 +73,14 @@
obj-$(CONFIG_CMD_HVC) += smccc.o
obj-$(CONFIG_CMD_I2C) += i2c.o
obj-$(CONFIG_CMD_WATCHDOG) += watchdog.o
+obj-$(CONFIG_CMD_JTAG) += jtag.o
obj-$(CONFIG_CMD_IOTRACE) += iotrace.o
obj-$(CONFIG_CMD_HASH) += hash.o
obj-$(CONFIG_CMD_IDE) += ide.o disk.o
obj-$(CONFIG_CMD_INI) += ini.o
+ifdef CONFIG_CMD_INI
+obj-y += amlogic/ini/model.o amlogic/ini/model_data_check.o amlogic/ini/ini_proxy.o amlogic/ini/UnifyKey.o amlogic/ini/ini_platform.o amlogic/ini/ini_io.o amlogic/ini/ini_handler.o amlogic/ini/ini_core.o amlogic/ini/ini_log.o
+endif
obj-$(CONFIG_CMD_IRQ) += irq.o
obj-$(CONFIG_CMD_ITEST) += itest.o
obj-$(CONFIG_CMD_JFFS2) += jffs2.o
@@ -100,6 +106,7 @@
obj-$(CONFIG_CMD_MTD) += mtd.o
obj-$(CONFIG_CMD_MTDPARTS) += mtdparts.o
obj-$(CONFIG_CMD_NAND) += nand.o
+obj-$(CONFIG_AML_STORAGE) += storage.o
obj-$(CONFIG_CMD_NET) += net.o
obj-$(CONFIG_CMD_ONENAND) += onenand.o
obj-$(CONFIG_CMD_OSD) += osd.o
@@ -164,6 +171,9 @@
obj-$(CONFIG_CMD_ETHSW) += ethsw.o
obj-$(CONFIG_CMD_AXI) += axi.o
obj-$(CONFIG_CMD_SARADC) += saradc.o
+obj-$(CONFIG_CMD_STARTDSP) += cmd_startdsp.o
+obj-$(CONFIG_CMD_IR) += irkey.o
+obj-$(CONFIG_CMD_TCPC) += tcpc.o
# Power
obj-$(CONFIG_CMD_PMIC) += pmic.o
@@ -179,11 +189,18 @@
obj-$(CONFIG_ARCH_MVEBU) += mvebu/
endif # !CONFIG_SPL_BUILD
+obj-$(CONFIG_CMD_DSPRUN) += cmd_dsprun.o
+obj-$(CONFIG_CMD_DSPSET) += cmd_dspset.o
+
# core command
obj-y += nvedit.o
obj-$(CONFIG_TI_COMMON_CMD_OPTIONS) += ti/
-obj-$(CONFIG_AML_CMD) += amlogic/
+obj-$(CONFIG_AML_DRIVER) += amlogic/
+
+obj-$(CONFIG_AML_TSENSOR) += amlogic/cmd_tsensor.o
+obj-$(CONFIG_AML_OSCRING) += amlogic/cmd_ringmsr.o
+
filechk_data_gz = (echo "static const char data_gz[] ="; cat $< | scripts/bin2c; echo ";")
diff --git a/cmd/aml_mmc.c b/cmd/aml_mmc.c
index 3a19cb1..f27242c 100644
--- a/cmd/aml_mmc.c
+++ b/cmd/aml_mmc.c
@@ -1,24 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2003
- * Kyle Harris, kharris@nexus-tech.net
- *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -32,7 +14,7 @@
#include <asm/arch/cpu_sdio.h>
#include <asm/arch/sd_emmc.h>
#include <linux/sizes.h>
-#include <asm/arch-g12a/cpu_id.h>
+#include <amlogic/cpu_id.h>
#include <amlogic/aml_mmc.h>
/* info system. */
@@ -78,11 +60,11 @@
/* max 2MB for emmc in blks */
#define UBOOT_SIZE (0x1000)
-
extern int mmc_key_write(unsigned char *buf, unsigned int size, uint32_t *actual_lenth);
extern int mmc_key_read(unsigned char *buf, unsigned int size, uint32_t *actual_lenth);
-int info_disprotect = 0;
+/* move this out to storage */
+//int info_disprotect = 0;
int mmc_read_status(struct mmc *mmc, int timeout)
@@ -216,17 +198,13 @@
*/
int amlmmc_erase_bootloader(int dev, int map)
{
- int ret = 0, i, count = 3, mmc_part_nonius = MMC_PART_USER;
+ int ret = 0, i, count = 3;
int blk_shift;
unsigned long n;
char *partname[3] = {"user", "boot0", "boot1"};
cpu_id_t cpu_id = get_cpu_id();
struct mmc *mmc = find_mmc_device(dev);
-#if defined(CONFIG_AML_GPT)
- mmc_part_nonius = MMC_PART_BOOT0;
-#endif
-
/* do nothing */
if (0 == map)
goto _out;
@@ -246,7 +224,7 @@
blk_shift = ffs(mmc->read_bl_len) -1;
/* erase bootloader in user/boot0/boot1 */
- for (i = mmc_part_nonius; i < count; i++) {
+ for (i = 0; i < count; i++) {
if (map & (0x1 << i)) {
if (!blk_select_hwpart_devnum(IF_TYPE_MMC, 1, i)) {
lbaint_t start = 0, blkcnt;
@@ -275,10 +253,10 @@
blkcnt = CONFIG_EMMC_BOOT1_TOUCH_REGION >> blk_shift;
}
#endif/* CONFIG_EMMC_BOOT1_TOUCH_REGION */
-#ifdef CONFIG_AML_GPT
- if (i == 0)
- continue;
-#endif
+
+ if (i == 0 && (aml_gpt_valid(mmc) == 0))
+ continue;
+
printf("Erasing blocks " LBAFU " to " LBAFU " @ %s\n",
start, blkcnt, partname[i]);
n = blk_derase(mmc_get_blk_desc(mmc), start, blkcnt);
@@ -307,17 +285,13 @@
*/
int amlmmc_write_bootloader(int dev, int map, unsigned int size, const void *src)
{
- int ret = 0, i, count = 3, mmc_part_nonius = MMC_PART_USER;
+ int ret = 0, i, count = 3;
unsigned long n;
char *partname[3] = {"user", "boot0", "boot1"};
struct mmc *mmc = find_mmc_device(dev);
lbaint_t start = GXB_START_BLK, blkcnt;
cpu_id_t cpu_id = get_cpu_id();
-#if defined(CONFIG_AML_GPT)
- mmc_part_nonius = MMC_PART_BOOT0;
-#endif
-
/* do nothing */
if (0 == map)
goto _out;
@@ -340,9 +314,9 @@
blkcnt = (size + mmc->read_bl_len - 1) / mmc->read_bl_len;
/* erase bootloader in user/boot0/boot1 */
- for (i = mmc_part_nonius; i < count; i++) {
+ for (i = 0; i < count; i++) {
if (map & (0x1 << i)) {
- if (!blk_select_hwpart(mmc->dev,i)) {
+ if (!blk_select_hwpart_devnum(IF_TYPE_MMC, 1, i)) {
/* some customer may use boot1 higher 2M as private data. */
#ifdef CONFIG_EMMC_BOOT1_TOUCH_REGION
if (2 == i && CONFIG_EMMC_BOOT1_TOUCH_REGION <= size) {
@@ -351,10 +325,9 @@
break;
}
#endif /* CONFIG_EMMC_BOOT1_TOUCH_REGION */
-#ifdef CONFIG_AML_GPT
- if (i == 0)
- continue;
-#endif
+ if (i == 0 && (aml_gpt_valid(mmc) == 0))
+ continue;
+
printf("Wrting blocks " LBAFU " to " LBAFU " @ %s\n",
start, blkcnt, partname[i]);
n = blk_dwrite(mmc_get_blk_desc(mmc), start, blkcnt, src);
@@ -427,6 +400,10 @@
mmc = find_mmc_device(dev);
tmp_shift = ffs(mmc->read_bl_len) -1;
+ if (tmp_shift < 0) {
+ printf("bad shift.\n");
+ return 1;
+ }
cnt = size >> tmp_shift;
blk = offset_addr >> tmp_shift;
/* sz_byte = size - (cnt<<tmp_shift); */
@@ -546,6 +523,10 @@
mmc_init(mmc);
blk_shift = ffs(mmc->read_bl_len) -1;
+ if (blk_shift < 0) {
+ printf("bad shift.\n");
+ return 1;
+ }
part_info = find_mmc_partition_by_name(MMC_BOOT_NAME);
if (part_info == NULL) {
@@ -605,6 +586,10 @@
mmc_init(mmc);
blk_shift = ffs(mmc->read_bl_len) -1;
+ if (blk_shift < 0) {
+ printf("bad shift.\n");
+ return 1;
+ }
if (emmckey_is_protected(mmc)
&& (strncmp(name, MMC_RESERVED_NAME, sizeof(MMC_RESERVED_NAME)) == 0x00)) {
printf("\"%s-partition\" is been protecting and should no be erased!\n",
@@ -629,6 +614,7 @@
static int amlmmc_erase_whole(int argc, char *const argv[])
{
+ char *name = NULL;
int dev;
u32 n = 0;
int blk_shift;
@@ -638,12 +624,21 @@
struct mmc *mmc;
int map;
- dev = CONFIG_SYS_MMC_BOOT_DEV;
+ name = "logo";
+ dev = find_dev_num_by_partition_name(name);
+ if (dev < 0) {
+ printf("Cannot find dev.\n");
+ return 1;
+ }
mmc = find_mmc_device(dev);
if (!mmc)
return 1;
mmc_init(mmc);
blk_shift = ffs(mmc->read_bl_len) -1;
+ if (blk_shift < 0) {
+ printf("bad shift.\n");
+ return 1;
+ }
start_blk = 0;
if (emmckey_is_protected(mmc)) {
@@ -663,7 +658,7 @@
if (n == 0) { // not error
// (2) erase all the area after reserve-partition
start_blk = (part_info->offset + part_info->size + PARTITION_RESERVED)
- >> blk_shift;
+ >> blk_shift;
u64 erase_cnt = (mmc->capacity >> blk_shift) - start_blk;
n = blk_derase(mmc_get_blk_desc(mmc), start_blk, erase_cnt);
}
@@ -680,6 +675,7 @@
static int amlmmc_erase_non_cache(int arc, char *const argv[])
{
+ char *name = NULL;
int dev;
u32 n = 0;
int blk_shift;
@@ -688,51 +684,60 @@
struct mmc *mmc;
int map;
- dev = CONFIG_SYS_MMC_BOOT_DEV;
- mmc = find_mmc_device(dev);
- if (!mmc)
+ name = "logo";
+ dev = find_dev_num_by_partition_name(name);
+ if (dev < 0) {
+ printf("Cannot find dev.\n");
+ return 1;
+ }
+ mmc = find_mmc_device(dev);
+ if (!mmc)
+ return 1;
+ mmc_init(mmc);
+ blk_shift = ffs(mmc->read_bl_len) -1;
+ if (blk_shift < 0) {
+ printf("bad shift.\n");
return 1;
- mmc_init(mmc);
- blk_shift = ffs(mmc->read_bl_len) -1;
- if (emmckey_is_protected(mmc)) {
- part_info = find_mmc_partition_by_name(MMC_RESERVED_NAME);
- if (part_info == NULL) {
- return 1;
- }
+ }
+ if (emmckey_is_protected(mmc)) {
+ part_info = find_mmc_partition_by_name(MMC_RESERVED_NAME);
+ if (part_info == NULL) {
+ return 1;
+ }
- blk = part_info->offset;
- // it means: there should be other partitions before reserve-partition.
+ blk = part_info->offset;
+ // it means: there should be other partitions before reserve-partition.
if (blk > 0) {
blk -= PARTITION_RESERVED;
- }
- blk >>= blk_shift;
- blk -= start_blk;
- // (1) erase all the area before reserve-partition
- if (blk > 0) {
- n = blk_derase(mmc_get_blk_desc(mmc), start_blk, blk);
- // printf("(1) erase blk: 0 --> %llx %s\n", blk, (n == 0) ? "OK" : "ERROR");
- }
- if (n == 0) { // not error
- // (2) erase all the area after reserve-partition
- part_info = find_mmc_partition_by_name(MMC_CACHE_NAME);
- if (part_info == NULL) {
- return 1;
- }
- start_blk = (part_info->offset + part_info->size + PARTITION_RESERVED)
- >> blk_shift;
- u64 erase_cnt = (mmc->capacity >> blk_shift) - start_blk;
- n = blk_derase(mmc_get_blk_desc(mmc), start_blk, erase_cnt);
- }
- } else {
- n = blk_derase(mmc_get_blk_desc(mmc), start_blk, 0); // erase the whole card
- }
- map = AML_BL_BOOT;
- if (n == 0) {
- n = amlmmc_erase_bootloader(dev, map);
- if (n)
- printf("erase bootloader in boot partition failed\n");
- }
- return (n == 0) ? 0 : 1;
+ }
+ blk >>= blk_shift;
+ blk -= start_blk;
+ // (1) erase all the area before reserve-partition
+ if (blk > 0) {
+ n = blk_derase(mmc_get_blk_desc(mmc), start_blk, blk);
+ // printf("(1) erase blk: 0 --> %llx %s\n", blk, (n == 0) ? "OK" : "ERROR");
+ }
+ if (n == 0) { // not error
+ // (2) erase all the area after reserve-partition
+ part_info = find_mmc_partition_by_name(MMC_CACHE_NAME);
+ if (part_info == NULL) {
+ return 1;
+ }
+ start_blk = (part_info->offset + part_info->size + PARTITION_RESERVED)
+ >> blk_shift;
+ u64 erase_cnt = (mmc->capacity >> blk_shift) - start_blk;
+ n = blk_derase(mmc_get_blk_desc(mmc), start_blk, erase_cnt);
+ }
+ } else {
+ n = blk_derase(mmc_get_blk_desc(mmc), start_blk, 0); // erase the whole card
+ }
+ map = AML_BL_BOOT;
+ if (n == 0) {
+ n = amlmmc_erase_bootloader(dev, map);
+ if (n)
+ printf("erase bootloader in boot partition failed\n");
+ }
+ return (n == 0) ? 0 : 1;
}
static int amlmmc_erase_dev(int argc, char *const argv[])
@@ -744,15 +749,10 @@
{
int map;
int rc;
- int dev;
-#ifndef CONFIG_AML_GPT
char *name = NULL;
-#endif
+ int dev;
map = AML_BL_ALL;
-#if defined(CONFIG_AML_GPT)
- dev = CONFIG_SYS_MMC_BOOT_DEV;
-#else
name = "bootloader";
dev = find_dev_num_by_partition_name(name);
@@ -760,7 +760,7 @@
printf("Cannot find dev.\n");
return 1;
}
-#endif
+
rc = amlmmc_erase_bootloader(dev, map);
return rc;
}
@@ -891,6 +891,10 @@
return 1;
int blk_shift = ffs( mmc->read_bl_len) -1;
+ if (blk_shift < 0) {
+ printf("bad shift.\n");
+ return 1;
+ }
cnt = size >> blk_shift;
blk = offset >> blk_shift;
sz_byte = size - (cnt<<blk_shift);
@@ -1025,6 +1029,10 @@
return 1;
blk_shift = ffs( mmc->read_bl_len) - 1;
+ if (blk_shift < 0) {
+ printf("bad shift.\n");
+ return 1;
+ }
cnt = size >> blk_shift;
blk = offset >> blk_shift;
sz_byte = size - (cnt<<blk_shift);
@@ -1671,6 +1679,10 @@
wp_grp_size = write_protect_group_size(mmc, ext_csd);
blk_shift = ffs(mmc->read_bl_len) -1;
+ if (blk_shift < 0) {
+ printf("bad shift.\n");
+ return 1;
+ }
part_info = find_mmc_partition_by_name(name);
if (part_info == NULL)
@@ -1808,8 +1820,10 @@
err = compute_write_protect_range(mmc, name, ext_csd,
&wp_grp_size, &start, &part_end);
- if (err)
+ if (err) {
+ free(addr);
return 1;
+ }
group_start = start;
@@ -1874,10 +1888,16 @@
}
blk_shift = ffs(mmc->read_bl_len) - 1;
+ if (blk_shift < 0) {
+ printf("bad shift.\n");
+ free(addr);
+ return 1;
+ }
mmc_boundary = mmc->capacity>>blk_shift;
if ((part_end + 1) > mmc_boundary) {
printf("Error: the operation cross the boundary of mmc\n");
+ free(addr);
return 1;
}
@@ -1997,6 +2017,10 @@
}
blk_shift = ffs(mmc->read_bl_len) - 1;
+ if (blk_shift < 0) {
+ printf("bad shift.\n");
+ return 1;
+ }
mmc_boundary = mmc->capacity>>blk_shift;
if ((part_end + 1) > mmc_boundary) {
@@ -2213,6 +2237,10 @@
}
blk_shift = ffs(mmc->read_bl_len) - 1;
+ if (blk_shift < 0) {
+ printf("bad shift.\n");
+ return 1;
+ }
mmc_boundary = mmc->capacity>>blk_shift;
if ((part_end + 1) > mmc_boundary) {
@@ -2409,6 +2437,10 @@
}
blk_shift = ffs(mmc->read_bl_len) - 1;
+ if (blk_shift < 0) {
+ printf("bad shift.\n");
+ return 1;
+ }
mmc_boundary = mmc->capacity>>blk_shift;
if ((part_end + 1) > mmc_boundary) {
@@ -3009,7 +3041,6 @@
return ret;
}
-
int dtb_write(void *addr)
{
int ret = 0;
@@ -3071,12 +3102,23 @@
unsigned char *temp = NULL;
if (!buffer)
return 1;
+ temp = malloc (AML_DTB_IMG_MAX_SZ);
+ if (!temp)
+ return 1;
+ memcpy(temp, buffer, AML_DTB_IMG_MAX_SZ);
+ /* todo, check new dts imcoming.... */
+ ret = check_valid_dts(temp);
+ free(temp);
/* todo, check new dts imcoming.... */
/* ret = check_valid_dts(buffer);*/
/* only the dts new is valid */
if (!ret) {
free_partitions();
- get_partition_from_dts(buffer);
+ ret = get_partition_from_dts(buffer);
+ if (ret) {
+ printf("Fail to get partition talbe from dts\n");
+ goto _out;
+ }
if (0 == mmc_device_init(_dtb_init())) {
printf("partition table success\n");
ret = 0;
@@ -3216,6 +3258,34 @@
return ret;
}
+int emmc_erase_rsv(struct mmc *mmc, char *rsv_part)
+{
+ u64 cnt = 0, n = 0, blk = 0;
+ struct partitions *part = NULL;
+ struct virtual_partition *vpart = NULL;
+
+ if (rsv_part == NULL)
+ return -1;
+
+ vpart = aml_get_virtual_partition_by_name(MMC_DTB_NAME);
+ part = aml_get_partition_by_name(MMC_RESERVED_NAME);
+ if (strcmp(rsv_part, "dtb") == 0) {
+ blk = (part->offset + vpart->offset) / mmc->read_bl_len;
+ cnt = (vpart->size * 2) / mmc->read_bl_len;
+ if (cnt != 0)
+ n = blk_derase(mmc_get_blk_desc(mmc), blk, cnt);
+ printf("%s is erased %s\n",
+ rsv_part, (n == 0) ? "OK" : "ERROR");
+ return (n == 0) ? 0 : 1;
+ } else if (strcmp(rsv_part, "key") == 0) {
+ n = mmc_key_erase();
+ printf("%s is erased %s\n",
+ rsv_part, (n == 0) ? "OK" : "ERROR");
+ return (n == 0) ? 0 : 1;
+ }
+ return 1;
+}
+
int do_emmc_erase(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int dev;
@@ -3344,7 +3414,6 @@
return 0;
}
-
int do_emmc_fb_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int ret = 0;
@@ -3425,29 +3494,6 @@
return ret;
}
-int do_emmc_part_write(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- int ret = 0;
- void *addr = NULL;
-
- if (argc != 3)
- return CMD_RET_USAGE;
-
- ret = run_command("mmc dev 1", 0);
- if (ret != 0)
- printf("mmc dev 1 failed!\n");
- /*erase MBR*/
- ret = run_command("amlmmc erase 1 0 1", 0);
- if (ret != 0) {
- printf("amlmmc erase 1 0 1 failed!\n");
- return -1;
- }
-
- addr = (void *)simple_strtoul(argv[2], NULL, 16);
- ret = emmc_update_ept(addr);
- return ret;
-}
-
int do_emmc_key_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
int ret = 0;
@@ -3481,13 +3527,8 @@
size = simple_strtoull(argv[3], NULL, 16);
ret = mmc_key_write(addr, size,actual_lenth);
return ret;
-
-
}
-
-
-
static cmd_tbl_t cmd_emmc[] = {
U_BOOT_CMD_MKENT(dtb_read, 4, 0, do_emmc_dtb_read, "", ""),
U_BOOT_CMD_MKENT(dtb_write, 4, 0, do_emmc_dtb_write, "", ""),
@@ -3496,7 +3537,6 @@
U_BOOT_CMD_MKENT(fastboot_write, 4, 0, do_emmc_fb_write, "", ""),
U_BOOT_CMD_MKENT(key_read, 4, 0, do_emmc_key_read, "", ""),
U_BOOT_CMD_MKENT(key_write, 4, 0, do_emmc_key_write, "", ""),
- U_BOOT_CMD_MKENT(part_write, 3, 0, do_emmc_part_write, "", ""),
};
static int do_emmc_dtb_key(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -3512,7 +3552,6 @@
return cp->cmd(cmdtp, flag, argc, argv);
}
-
U_BOOT_CMD(
emmc, 4, 1, do_emmc_dtb_key,
"EMMC sub system",
@@ -3524,6 +3563,5 @@
"emmc fastboot_write addr size\n"
"emmc key_read addr size\n"
"emmc key_write addr size\n"
- "emmc part_write addr\n"
);
diff --git a/cmd/amlogic/Kconfig b/cmd/amlogic/Kconfig
index b31754a..ae672e4 100644
--- a/cmd/amlogic/Kconfig
+++ b/cmd/amlogic/Kconfig
@@ -1,19 +1,27 @@
-config AML_CMD
- bool "Amlogic command"
- default y
- help
- support amlogic commands
+menu "Amlogic commands"
-config AML_RPMB_DISABLE
+config AML_RPMB
+ depends on OPTEE
bool "support RPMB set in bootargs"
- default n
+ default y
help
Support RPMB set in bootargs.
-config AML_STORAGE
- bool "aml storage support"
+config AML_STORE_WRAPPER
+ depends on AML_STORAGE
+ bool "wrapper for store"
+ default y
help
- storage cmd support
+ based on AML_STORAGE
+ read/write don't care bad blocks
+
+config AML_STORE_WRAPPER
+ depends on AML_STORAGE
+ bool "wrapper for store"
+ default y
+ help
+ based on AML_STORAGE
+ read/write don't care bad blocks
config AML_IMG_READ
depends on AML_STORAGE
@@ -29,6 +37,18 @@
help
support reserv env from c array
+config BOOTLOADER_CONTROL_BLOCK
+ bool "bootloader control block support"
+ default n
+ help
+ used for recovery and the bootloader to talk to each other
+
+config CMD_BOOTCTOL_AVB
+ bool "avb cmd"
+ default n
+ help
+ support avb related cmds
+
config CMD_RSVMEM
bool "rsvmem cmd"
default y
@@ -43,148 +63,66 @@
config CMD_DDR_TEST
bool "ddr test cmd"
- default n
+ default y
help
support ddr_test cmd
-config CMD_REBOOT
- bool "CMD_REBOOT"
- depends on MMC_FTS || NAND_FTS
- help
- CMD_REBOOT support.
-
-config CMD_FACTORY_BOOT
- bool "CMD_FACTORY_BOOT"
- depends on MMC_FTS || NAND_FTS
- help
- CMD_FACTORY_BOOT support.
-
-config MMC_FTS
- bool "MMC_FTS"
+config CMD_OS_IDENT
+ bool "os_ident"
default y
help
- MMC_FTS support.
+ Ident OS type
-config NAND_FTS
- bool "NAND_FTS"
+config AML_ROBUST
+ bool "envs for robust upgrade"
+ depends on AML_STORAGE
+ default y
+ help
+ "envs for robust upgrade like defendkey"
+
+config CMD_AUTOSCR
+ bool "legacy autoscr cmd"
+ default y
+ depends on CMD_SOURCE
+ help
+ Run script in memory
+
+#prduct mode start---->
+config NO_FASTBOOT_FLASHING
+ depends on FASTBOOT
+ bool "support fastboot lock/unlock"
+ default n
+
+config DISABLE_AML_SERIAL
+ bool "disable debug serial tx/rx"
+ depends on MESON_SERIAL
+ select SILENT_CONSOLE
+ default n
+
+config USB_TOOL_ENTRY
+ string "support usb burn tool in run update"
+ default "echo productmode" if AML_PRODUCT_MODE
+ default "adnl 1200" if !AML_PRODUCT_MODE
+
+config KNL_LOG_LEVEL
+ string "restrict kernel log level"
+ default " loglevel=1 " if AML_PRODUCT_MODE
+ default " " if !AML_PRODUCT_MODE
+
+config AML_DISABLE_DEV_CMDS
+ bool "disable unsafe developing commands"
default n
help
- NAND_FTS support.
+ "Disable un-safe developing commands for product mode"
-config AML_RPMB_DISABLE
- bool "support RPMB set in bootargs"
+config AML_PRODUCT_MODE
+ bool "amlogic product/security mode"
default n
+ imply NO_FASTBOOT_FLASHING
+ imply DISABLE_AML_SERIAL
+ imply AML_DISABLE_DEV_CMDS
help
- Support RPMB set in bootargs.
+ recommend enable when product is ready for producing
+#prduct mode end<----
-config CMD_DDR_D2PLL
- bool "d2pll cmd"
- default n
- help
- support d2pll cmd
-
-config CMD_DDR_TEST
- bool "ddr test cmd"
- default n
- help
- support ddr_test cmd
-
-config IMG_SECURE_CHECK_SZ
- int "secure boot size limitation"
- default 0
- help
- Check if boot image size is larger than
- the secure boot size limitation
-
-config CMD_AVB
- bool "avb operations"
- default n
- help
- support avb operations
-
-config CMD_CVBS
- bool "cvbs command for video"
- depends on CMDLINE && AML_CVBS
- default n
- help
- support cvbs operations
-
-config CMD_LCD
- bool "lcd command for video"
- depends on CMDLINE && AML_LCD
- default n
- help
- support lcd operations
-
-config AML_CMD_OSD
- bool "osd command for video"
- depends on CMDLINE && AML_OSD
- default n
- help
- support osd operations
-
-config CMD_VPU
- bool "vpu command for video"
- depends on CMDLINE && AML_VPU
- default n
- help
- support vpu operations
-
-config CMD_VPP
- bool "vpp command for video"
- depends on CMDLINE && AML_VPP
- default n
- help
- support vpp operations
-
-config CMD_VOUT
- bool "output video"
- depends on CMDLINE && AML_VOUT
- default n
- help
- support vout operations
-
-config CMD_HDMITX
- bool "hdmi sub-system"
- depends on CMDLINE && AML_HDMITX
- default n
- help
- support hdmi operations
-
-config CMD_TSENSOR
- bool "cpu temp-system"
- default n
- help
- support temp-system operations
-
-config CMD_OSCRING
- bool "Amlogic measure ring"
- default n
- help
- for get chip ring info
-
-config CMD_STORAGE
- bool "STORE sub-system"
- default n
- help
- support store command
-
-config BOOTLOADER_CONTROL_BLOCK
- bool "support bootloader control block"
- default n
- help
- support bcb avb bootctrl module
-
-config CMD_BOOTCTOL_AVB
- bool "support avb boot"
- depends on BOOTLOADER_CONTROL_BLOCK
- default n
- help
- support avb operation command
-
-config G_AB_SYSTEM
- bool "support ab boot for bootloader system"
- depends on CMD_BOOTCTOL_AVB
- default n
- help
- support ab system operation
+endmenu
diff --git a/cmd/amlogic/Makefile b/cmd/amlogic/Makefile
index 8104e74..1312ea3 100644
--- a/cmd/amlogic/Makefile
+++ b/cmd/amlogic/Makefile
@@ -1,37 +1,45 @@
# SPDX-License-Identifier: GPL-2.0+
#
-obj-$(CONFIG_CMD_VPU) += cmd_vpu.o
-obj-$(CONFIG_CMD_VPP) += cmd_vpp.o
-obj-$(CONFIG_CMD_VOUT) += cmd_vout.o
-obj-$(CONFIG_CMD_CVBS) += cmd_cvbs.o
-obj-$(CONFIG_CMD_HDMITX) += cmd_hdmitx.o
-obj-$(CONFIG_CMD_LCD) += cmd_lcd.o
-obj-$(CONFIG_AML_CMD_OSD) += cmd_osd.o
+obj-$(CONFIG_AML_VPU) += cmd_vpu.o
+obj-$(CONFIG_AML_VPP) += cmd_vpp.o
+obj-$(CONFIG_AML_VOUT) += cmd_vout.o
+obj-$(CONFIG_AML_CVBS) += cmd_cvbs.o
+obj-$(CONFIG_AML_HDMITX) += cmd_hdmitx.o
+obj-$(CONFIG_AML_LCD) += cmd_lcd.o
+obj-$(CONFIG_AML_OSD) += cmd_osd.o
+obj-$(CONFIG_AML_DOLBY) += cmd_dolbyvision.o
+obj-$(CONFIG_CMD_PLLTEST) += cmd_plltest.o
+obj-$(CONFIG_AML_STORE_WRAPPER) += store_wrapper.o
obj-$(CONFIG_AML_IMG_READ) += imgread.o
obj-$(CONFIG_AML_DEFENV) += defenv_without.o
+obj-$(CONFIG_AML_ROBUST) += bootloader_status.o
-# amlogic commands
-obj-$(CONFIG_CMD_REBOOT) += cmd_reboot.o flash_ts.o nand_ts.o mmc_ts.o
-obj-$(CONFIG_CMD_FACTORY_BOOT) += cmd_factory_boot.o flash_ts.o nand_ts.o mmc_ts.o
-
+obj-$(CONFIG_AML_REBOOT) += cmd_reboot.o
obj-$(CONFIG_CMD_RSVMEM) += cmd_rsvmem.o
+obj-y += cmd_version.o
+
ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK
obj-y += cmd_bcb.o
+obj-y += get_bcb_boot_part.o
+obj-y += cmd_dynamic.o
ifdef CONFIG_CMD_BOOTCTOL_AVB
+ifdef CONFIG_CMD_BOOTCTOL_VAB
+obj-y += cmd_bootctl_vab.o
+else
obj-y += cmd_bootctl_avb.o
+endif
else
obj-y += cmd_bootctl.o
endif
endif
-ifndef CONFIG_AML_RPMB_DISABLE
-obj-y += cmd_rpmb.o
-endif
-obj-y += cmd_avb.o
-obj-$(CONFIG_CMD_TSENSOR) += cmd_tsensor.o
-obj-$(CONFIG_CMD_OSCRING) += cmd_ringmsr.o
+obj-$(CONFIG_AML_RPMB) += cmd_rpmb.o
+obj-$(CONFIG_CMD_BOOTCTOL_AVB) += cmd_avb.o
obj-$(CONFIG_CMD_DDR_D2PLL) += cmd_d2pll.o
-obj-$(CONFIG_CMD_DDR_TEST) += cmd_ddr_test.o
-obj-$(CONFIG_CMD_STORAGE) += storage.o
+obj-$(CONFIG_CMD_DDR_TEST) += cmd_ddr_test_g12.o
+
+obj-$(CONFIG_CMD_OS_IDENT) += os_ident.o
+obj-$(CONFIG_AML_FACTORY_PROVISION) += cmd_factory_provision.o
+obj-$(CONFIG_SECURE_POWER_CONTROL) += cmd_power.o
diff --git a/cmd/amlogic/bootloader_status.c b/cmd/amlogic/bootloader_status.c
new file mode 100644
index 0000000..6960967
--- /dev/null
+++ b/cmd/amlogic/bootloader_status.c
@@ -0,0 +1,522 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <linux/kernel.h>
+#include <amlogic/aml_efuse.h>
+#include <amlogic/cpu_id.h>
+#include <amlogic/storage.h>
+#include <partition_table.h>
+#include <fastboot.h>
+#include <emmc_partitions.h>
+
+#ifndef IS_FEAT_BOOT_VERIFY
+#define IS_FEAT_BOOT_VERIFY() 0
+#endif// #ifndef IS_FEAT_BOOT_VERIFY
+int __attribute__((weak)) store_logic_read(const char *name, loff_t off, size_t size, void *buf)
+{ return store_read(name, off, size, buf);}
+
+typedef boot_img_hdr_t boot_img_hdr;
+
+#define debugP(fmt...) //printf("[DbgBootSta]L%d:", __LINE__),printf(fmt)
+#define errorP(fmt...) printf("ErrBootSta(L%d):", __LINE__),printf(fmt)
+#define wrnP(fmt...) printf("wrn:"fmt)
+#define MsgP(fmt...) printf("[BootSta]"fmt)
+
+//check SWPL-31296 for details
+static int do_get_bootloader_status(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ bool printStat = false;
+ bool saveenv = false;
+ debugP("Initial value for argc=%d\n", argc);
+ while (argc > 1 && **(argv + 1) == '-') {
+ char *arg = *++argv;
+
+ --argc;
+ while (*++arg) {
+ switch (*arg) {
+ case 'p': /* print */
+ printStat = true;
+ break;
+ case 's': /* saveenv */
+ saveenv = true;
+ break;
+ default:
+ return CMD_RET_USAGE;
+ }
+ }
+ }
+ debugP("Final value for argc=%d\n", argc);
+ //1,forUpgrade_socType, cpu familyId
+ const cpu_id_t cpuid = get_cpu_id();
+ const int familyId = cpuid.family_id;
+ env_set_hex("forUpgrade_socType", familyId);
+
+ //2,forUpgrade_secureBoot
+ const bool secureboot = IS_FEAT_BOOT_VERIFY();
+ env_set("forUpgrade_secureBoot", secureboot ? "true" : "false");
+
+ //3,forUpgrade_robustOta
+ bool supportRobustOta = false;
+ switch (familyId) {
+ case MESON_CPU_MAJOR_ID_SC2:
+ case MESON_CPU_MAJOR_ID_S4:
+ supportRobustOta = true;
+ break;
+ default:break;
+ }
+ env_set("forUpgrade_robustOta", supportRobustOta ? "true" : "false");
+
+ //4,forUpgrade_flashType
+ const char* BootDevices[] = {
+ "BOOT_EMMC", "BOOT_SD",
+ "BOOT_NAND_NFTL", "BOOT_NAND_MTD",
+ "BOOT_SNAND", "BOOT_SNOR",
+ };
+ const char* bootDevice = "BOOT_NONE";
+ enum boot_type_e bootType = store_get_type();
+ int i = 0;
+ for (; i < ARRAY_SIZE(BootDevices); ++i) {
+ if ((1<<i) != bootType) continue;
+ bootDevice = BootDevices[i];
+ break;
+ }
+ env_set("forUpgrade_flashType", bootDevice);
+
+ //5,forUpgrade_bootloaderCopies, how many copies supported
+ int bootCopies = 1;
+ switch (bootType) {
+ case BOOT_EMMC: bootCopies = 3; break;
+ default:break;
+ }
+ env_set_ulong("forUpgrade_bootloaderCopies", bootCopies);
+
+ //6,forUpgrade_bootloaderIndex
+ //for emmc, 0/1/2 is user/boot0/boot1
+ const int bootCpyIndex = store_bootup_bootidx("bootloader");
+ env_set_ulong("forUpgrade_bootloaderIndex", bootCpyIndex);
+
+ //7,get first boot index, for defendkey
+ const int firstBootCpyIndex = store_boot_copy_start();
+ env_set_ulong("forUpgrade_1stBootIndex", firstBootCpyIndex);
+
+ if (printStat) run_command("printenv forUpgrade_socType forUpgrade_secureBoot "
+ " forUpgrade_robustOta forUpgrade_flashType forUpgrade_bootloaderCopies "
+ " forUpgrade_bootloaderIndex forUpgrade_1stBootIndex", 0);
+
+ if (saveenv) run_command("saveenv", 0);
+
+ return CMD_RET_SUCCESS;
+}
+
+static void run_recovery_from_flash(void) {
+ env_set("dolby_status","0");
+ run_command("run init_display", 0);
+ run_command("run storeargs", 0);
+ run_command("run recovery_from_flash", 0);
+}
+
+static void run_recovery_from_cache(void) {
+
+ char *loadaddr_kernel = env_get("loadaddr_kernel");
+ if (loadaddr_kernel != NULL) {
+ env_set("loadaddr",loadaddr_kernel);
+ } else {
+ env_set("loadaddr","0x01080000");
+ }
+ env_set("dolby_status","0");
+ run_command("run init_display", 0);
+ run_command("run storeargs", 0);
+ run_command("if ext4load mmc 1:2 ${dtb_mem_addr} /recovery/dtb.img; then echo cache dtb.img loaded; fi;", 0);
+ run_command("if ext4load mmc 1:2 ${loadaddr} /recovery/recovery.img; then echo cache recovery.img loaded; fi;", 0);
+
+ env_set("check_result","recovery_succ");
+ run_command("bootm ${loadaddr}", 0);
+ env_set("check_result","recovery_fail");
+ env_set("reboot_status","reboot_recovery");
+ run_command("saveenv", 0);
+ run_command("reboot", 0);//need reboot old bootloader
+}
+
+int write_bootloader_back(const char* bootloaderindex, int dstindex) {
+ int iRet = 0;
+ int copy = 0;
+ int ret = -1;
+ unsigned char* buffer = NULL;
+ if (strcmp(bootloaderindex, "1") == 0) {
+ copy = 1;
+ } else if (strcmp(bootloaderindex, "2") == 0) {
+ copy = 2;
+ } else if (strcmp(bootloaderindex, "0") == 0) {
+ copy = 0;
+ }
+
+ buffer = (unsigned char *)malloc(0x2000 * 512);
+ if (!buffer)
+ {
+ printf("ERROR! fail to allocate memory ...\n");
+ goto exit;
+ }
+ memset(buffer, 0, 0x2000 * 512);
+ iRet = store_boot_read("bootloader", copy, 0, buffer);
+ if (iRet) {
+ errorP("Fail read bootloader from rsv with sz\n");
+ goto exit;
+ }
+ iRet = store_boot_write("bootloader", dstindex, 0, buffer);
+ if (iRet) {
+ printf("Failed to write bootloader\n");
+ goto exit;
+ } else {
+ ret = 0;
+ }
+
+exit:
+ if (buffer)
+ {
+ free(buffer);
+ buffer = NULL;
+ }
+ return ret;
+}
+
+static void aml_recovery(void) {
+ char *mode = NULL;
+ char command[32];
+ char miscbuf[4096] = {0};
+
+ run_command("get_rebootmode", 0);
+
+ //get reboot_mode
+ mode = env_get("reboot_mode");
+ if (mode == NULL) {
+ wrnP("can not get reboot mode, so skip recovery check\n");
+ } else {
+ if ((!strcmp(mode, "factory_reset")) || (!strcmp(mode, "update"))) {
+ env_set("dolby_status","0");
+ }
+ }
+
+#ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK
+ int ret = 0;
+ extern int boot_info_open_partition(char *miscbuf);
+ ret = boot_info_open_partition(miscbuf);
+ if (ret != 0) {
+ wrnP("open misc partition failed, so skip recovery check");
+ return;
+ }
+#endif
+
+ //if run recovery, need disable dolby
+ memcpy(command, miscbuf, 32);
+ if (!memcmp(command, "boot-recovery", strlen("boot-recovery"))) {
+ env_set("dolby_status","0");
+ return;
+ }
+}
+
+static int do_secureboot_check(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
+ int code_boot = 0;
+ int match_flag = 0;
+ char *rebootstatus = NULL;
+ char *checkresult = NULL;
+ char *bootloaderindex = NULL;
+ char *expect_index = NULL;
+ char *robustota = NULL;
+ char *mode = NULL;
+ char *update_env = NULL;
+ char *rebootmode = NULL;
+ int ret = -1;
+#ifdef CONFIG_MMC_MESON_GX
+ struct mmc *mmc = find_mmc_device(1);
+#endif
+
+ //if recovery mode, need disable dv, if factoryreset, need default uboot env
+ aml_recovery();
+
+ run_command("get_rebootmode", 0);
+ rebootmode = env_get("reboot_mode");
+ printf("rebootmode is %s\n", rebootmode);
+ if (rebootmode && (strcmp(rebootmode, "rescueparty") == 0)) {
+ printf("rebootmode is rescueparty, need rollback\n");
+ char *slot;
+
+#ifdef CONFIG_MMC_MESON_GX
+ if (mmc)
+ ret = aml_gpt_valid(mmc);
+#endif
+
+#ifdef CONFIG_FASTBOOT
+ struct misc_virtual_ab_message message;
+
+ set_mergestatus_cancel(&message);
+#endif
+
+ slot = env_get("slot-suffixes");
+ if (!slot) {
+ run_command("get_valid_slot", 0);
+ slot = env_get("slot-suffixes");
+ }
+ if (strcmp(slot, "0") == 0) {
+ if (ret != 0) {
+ wrnP("normal mode\n");
+ write_bootloader_back("2", 0);
+ env_set("expect_index", "0");
+ } else {
+ wrnP("gpt mode\n");
+ env_set("expect_index", "2");
+ }
+ wrnP("back to slot b\n");
+ run_command("set_active_slot b", 0);
+ } else if (strcmp(slot, "1") == 0) {
+ if (ret != 0) {
+ wrnP("normal mode\n");
+ write_bootloader_back("1", 0);
+ env_set("expect_index", "0");
+ } else {
+ wrnP("gpt mode\n");
+ env_set("expect_index", "1");
+ }
+ wrnP("back to slot a\n");
+ run_command("set_active_slot a", 0);
+ }
+
+ env_set("update_env", "1");
+ env_set("reboot_status", "reboot_next");
+ run_command("saveenv", 0);
+ run_command("reset", 0);
+ }
+
+ //check_result init
+ checkresult = env_get("check_result");
+ if (checkresult == NULL) {
+ env_set("check_result","succ");
+ }
+
+ //reboot_status init
+ rebootstatus = env_get("reboot_status");
+ if (rebootstatus == NULL) {
+ env_set("reboot_status","reboot_init");
+ rebootstatus = env_get("reboot_status");
+ }
+
+ if (rebootstatus == NULL) {
+ printf("rebootstatus is NULL, skip check\n");
+ return -1;
+ }
+
+ //no secure check need
+ if (!strcmp(rebootstatus, "reboot_init")) {
+ printf("rebootstatus is reboot_init, skip check\n");
+ return -1;
+ }
+
+ //check reboot_end
+ if (!strcmp(rebootstatus, "reboot_end")) {
+ env_set("reboot_status","reboot_init");
+ run_command("saveenv", 0);
+ }
+
+ //get reboot_mode
+ mode = env_get("reboot_mode");
+ if (mode == NULL) {
+ wrnP("can not get reboot mode, so skip secure check\n");
+ return -1;
+ }
+
+ code_boot = strcmp(mode, "cold_boot");
+ if (code_boot == 0) {
+ wrnP("not support code_boot for check\n");
+ //env_set("reboot_status","reboot_init");
+ //run_command("saveenv", 0);
+ //return -1;
+ }
+
+ //get boot status
+ run_command("amlbootsta -p -s", 0);
+
+ //get forUpgrade_robustOta and check if support robustota
+ robustota = env_get("forUpgrade_robustOta");
+ if ((robustota == NULL) || !strcmp(robustota, "false")) {
+ return -1;
+ }
+
+ //get bootloader index
+ bootloaderindex = env_get("forUpgrade_bootloaderIndex");
+ if (bootloaderindex == NULL) {
+ wrnP("can not get bootloader index, so skip secure check\n");
+ return -1;
+ }
+
+ //get expect index
+ expect_index = env_get("expect_index");
+ if (expect_index == NULL) {
+ wrnP("can not get expect index, so skip secure check\n");
+ return -1;
+ }
+
+ match_flag = strcmp(bootloaderindex, expect_index);
+
+
+ //first reboot, command from recovery, need reboot next
+ if (!strcmp(rebootstatus,"reboot_next")) {
+ wrnP("--secure check reboot_next---\n");
+ //bootloader index, expect == current, no need reboot next
+ if (match_flag == 0) {
+ wrnP("current index is expect, no need reboot next, run ceche recovery\n");
+ if (has_boot_slot == 1) {
+ wrnP("ab mode\n");
+ update_env = env_get("update_env");
+ if (strcmp(update_env, "1") == 0) {
+ printf("ab mode, default all uboot env\n");
+ run_command("env default -a;saveenv;", 0);
+ env_set("update_env","0");
+ }
+ } else {
+ run_recovery_from_cache();
+ return 0;
+ }
+ } else {
+ wrnP("now ready start reboot next\n");
+ if (has_boot_slot == 1) {
+#ifdef CONFIG_MMC_MESON_GX
+ if (mmc != NULL)
+ ret = aml_gpt_valid(mmc);
+#endif
+ if (ret == 0) {
+ wrnP("gpt mode\n");
+ env_set("reboot_status","reboot_finish");
+ run_command("saveenv", 0);
+ run_command("get_rebootmode", 0);
+ run_command("if test ${reboot_mode} = quiescent; then reboot next,quiescent; else reboot next; fi;", 0);
+ } else {
+ write_bootloader_back(bootloaderindex, 0);
+#ifdef CONFIG_FASTBOOT
+ struct misc_virtual_ab_message message;
+ set_mergestatus_cancel(&message);
+#endif
+ if (strcmp(bootloaderindex, "1") == 0) {
+ wrnP("back to slot a\n");
+ run_command("set_active_slot a", 0);
+ } else if (strcmp(bootloaderindex, "2") == 0) {
+ wrnP("back to slot b\n");
+ run_command("set_active_slot b", 0);
+ }
+
+ env_set("update_env","1");
+ env_set("reboot_status","reboot_next");
+ env_set("expect_index","0");
+ run_command("saveenv", 0);
+ run_command("reset", 0);
+ }
+ } else {
+ env_set("reboot_status","reboot_finish");
+ run_command("saveenv", 0);
+ run_command("reboot next", 0);
+ }
+ return 0;
+ }
+ } else if (!strcmp(rebootstatus,"reboot_finish")) {//second reboot, reboot next from uboot
+ wrnP("--secure check reboot_finish---\n");
+ env_set("reboot_status","reboot_end");
+ run_command("saveenv", 0);
+
+ if (match_flag == 0) {
+ wrnP("reboot next succ, bootloader secure check pass......\n");
+ if (has_boot_slot == 1) {
+ printf("ab mode, default all uboot env\n");
+ update_env = env_get("update_env");
+ if (strcmp(update_env, "1") == 0) {
+ printf("ab mode, default all uboot env\n");
+ run_command("env default -a;", 0);
+ env_set("update_env","0");
+
+ if (strcmp(bootloaderindex, "2") == 0) {
+ wrnP("rom always boot as boot0--> boot1\n");
+ wrnP("So if boot1 is ok, write it to boot0\n");
+ run_command("copy_slot_bootable 2 1", 0);
+ }
+ run_command("saveenv", 0);
+ }
+ } else {
+ run_recovery_from_cache();
+ return 0;
+ }
+ } else {
+ //bootloader check failed, run recovery show error
+ wrnP("reboot next fail, bootloader secure check fail(curr:%s, expect:%s)......\n",bootloaderindex, expect_index);
+ env_set("check_result","bootloader_fail");
+ run_command("saveenv", 0);
+ if (has_boot_slot == 1) {
+ wrnP("ab mode\n");
+#ifdef CONFIG_FASTBOOT
+ struct misc_virtual_ab_message message;
+ set_mergestatus_cancel(&message);
+#endif
+ if (strcmp(bootloaderindex, "1") == 0) {
+ wrnP("back to slot a\n");
+ run_command("set_active_slot a", 0);
+ } else if (strcmp(bootloaderindex, "2") == 0) {
+ wrnP("back to slot b\n");
+ run_command("set_active_slot b", 0);
+ }
+
+#ifdef CONFIG_MMC_MESON_GX
+ if (mmc != NULL)
+ ret = aml_gpt_valid(mmc);
+#endif
+
+ if (ret == 0) {
+ wrnP("gpt mode\n");
+ env_set("update_env","0");
+ env_set("reboot_status","reboot_init");
+ run_command("saveenv", 0);
+ } else {
+ write_bootloader_back(bootloaderindex, 0);
+ env_set("update_env","1");
+ env_set("reboot_status","reboot_next");
+ env_set("expect_index","0");
+ run_command("saveenv", 0);
+ run_command("reset", 0);
+ }
+
+ } else {
+ run_recovery_from_flash();
+ return 0;
+ }
+ }
+ } else if (!strcmp(rebootstatus,"reboot_recovery")) {
+ //recovery check failed, run recovery show error
+ wrnP("--secure check reboot_recovery---\n");
+ env_set("reboot_status","reboot_end");
+ run_command("saveenv", 0);
+ run_recovery_from_flash();
+ return 0;
+ } else {
+ env_set("check_result","succ");
+ }
+
+ return 0;
+}
+
+
+U_BOOT_CMD_COMPLETE(
+ amlbootsta, 3, 0, do_get_bootloader_status,
+ "get bootloader status in env",
+ "[-p] print bootloader status\n"
+ "[-s] saveenv after generate bootloader status\n",
+ var_complete
+);
+
+U_BOOT_CMD_COMPLETE(
+ amlsecurecheck, 1, 0, do_secureboot_check,
+ "try bootloader/dtb/recovery secure check",
+ ""
+ "",
+ var_complete
+);
+
+
diff --git a/cmd/amlogic/cmd_avb.c b/cmd/amlogic/cmd_avb.c
index fd9c203..62fd959 100644
--- a/cmd/amlogic/cmd_avb.c
+++ b/cmd/amlogic/cmd_avb.c
@@ -1,7 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2018 Amlogic, Inc
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
+#include <board_variant.h>
#include <common.h>
#include <command.h>
#include <environment.h>
@@ -19,12 +21,31 @@
#endif
#define AVB_USE_TESTKEY
-#define MAX_DTB_SIZE (256 * 1024)
+#define MAX_DTB_SIZE (AML_DTB_IMG_MAX_SZ + 512)
+#define DTB_PARTITION_SIZE 258048
+#define AVB_NUM_SLOT (4)
+#define MAX_AVBKEY_LEN (8 + 1024)
-#ifdef AVB_USE_TESTKEY
-extern const char testkey2048[520];
-extern const int testkey2048_length;
+#define CONFIG_AVB2_KPUB_EMBEDDED
+
+#if defined(CONFIG_AVB2_KPUB_VENDOR_MULTIPLE) && defined(CONFIG_AVB2_KPUB_DEFAULT)
+#pragma message("Warning: both vendor keys and default key are used\n")
#endif
+
+#ifdef CONFIG_AVB2_KPUB_VENDOR_MULTIPLE
+extern const uint8_t *avb2_kpub_vendor[];
+extern const size_t avb2_kpub_vendor_len[];
+extern const size_t avb2_kpub_vendor_num;
+extern const uint8_t *avb2_kpub_vendor_external[];
+extern const size_t avb2_kpub_vendor_external_len[];
+extern const size_t avb2_kpub_vendor_external_num;
+#endif
+
+#ifdef CONFIG_AVB2_KPUB_DEFAULT
+extern const uint8_t avb2_kpub_default[];
+extern const size_t avb2_kpub_default_len;
+#endif /* CONFIG_AVB_KPUB_VENDOR_MULTIPLE */
+
AvbOps avb_ops_;
static AvbIOResult read_from_partition(AvbOps* ops, const char* partition, int64_t offset,
@@ -40,7 +61,7 @@
return AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION;
*out_num_read = 0;
- if (!memcmp(partition, "dtb", strlen("dtb"))) {
+ if (!avb_strcmp(partition, "dt")) {
char *dtb_buf = malloc(MAX_DTB_SIZE);
if (!dtb_buf)
@@ -59,7 +80,7 @@
return AVB_IO_RESULT_OK;
}
} else {
- rc = store_read((unsigned char *)partition, offset, num_bytes, buffer);
+ rc = store_read(partition, offset, num_bytes, buffer);
if (rc) {
printf("Failed to read %zdB from part[%s] at offset %lld\n", num_bytes, partition, offset);
return AVB_IO_RESULT_ERROR_IO;
@@ -82,7 +103,7 @@
if (part_bytes < offset)
return AVB_IO_RESULT_ERROR_RANGE_OUTSIDE_PARTITION;
- if (!memcmp(partition, "dtb", strlen("dtb"))) {
+ if (!avb_strcmp(partition, "dt")) {
if (offset)
return AVB_IO_RESULT_ERROR_IO;
/* rc = store_dtb_rw((void *)buffer, num_bytes, 1); */
@@ -94,7 +115,7 @@
return AVB_IO_RESULT_OK;
}
} else {
- rc = store_write((unsigned char *)partition, offset, num_bytes, (unsigned char *)buffer);
+ rc = store_write(partition, offset, num_bytes, (unsigned char *)buffer);
if (rc) {
printf("Failed to write %zdB from part[%s] at offset %lld\n", num_bytes, partition, offset);
return AVB_IO_RESULT_ERROR_IO;
@@ -111,10 +132,14 @@
int ret;
char part_name[128];
memset(guid_buf, 0, guid_buf_size);
- run_command("get_valid_slot;", 0);
- s1 = env_get("active_slot");
- printf("active_slot is %s\n", s1);
- if (!memcmp(partition, "system", strlen("system"))) {
+
+ s1 = env_get("active_slot");
+ if (!s1) {
+ run_command("get_valid_slot;", 0);
+ s1 = env_get("active_slot");
+ }
+ //printf("active_slot is %s\n", s1);
+ if (!avb_strcmp(partition, "system")) {
if (strcmp(s1, "_a") == 0) {
ret = get_partition_num_by_name("system_a");
sprintf(part_name, "/dev/mmcblk0p%d", ret+1);
@@ -128,7 +153,7 @@
sprintf(part_name, "/dev/mmcblk0p%d", ret+1);
strncpy(guid_buf, part_name, guid_buf_size);
}
- } else if (!memcmp(partition, "vbmeta", strlen("vbmeta")))
+ } else if (!avb_strcmp(partition, "vbmeta"))
strncpy(guid_buf, "/dev/block/vbmeta", guid_buf_size);
return AVB_IO_RESULT_OK;
}
@@ -138,43 +163,73 @@
{
int rc = 0;
- if (!memcmp(partition, "dtb", strlen("dtb"))) {
- *out_size_num_bytes = MAX_DTB_SIZE;
+ if (!avb_strcmp(partition, "dt")) {
+ *out_size_num_bytes = DTB_PARTITION_SIZE;
} else {
/* rc = store_get_partititon_size((unsigned char *)partition, out_size_num_bytes); */
- rc = store_part_size((unsigned char *)partition);
+ rc = store_part_size(partition);
if (1 == rc) {
printf("Failed to get partition[%s] size\n", partition);
return AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION;
}
*out_size_num_bytes = rc;
- *out_size_num_bytes *= 512;
}
return AVB_IO_RESULT_OK;
}
+static inline bool _validate_key(const uint8_t* key1, size_t key1_len,
+ const uint8_t* key2, size_t key2_len)
+{
+ return key1_len == key2_len && avb_safe_memcmp(key1, key2, key1_len) == 0;
+}
+
+/**
+ * AVB custom key should not be supported.
+ */
static AvbIOResult validate_vbmeta_public_key(AvbOps* ops, const uint8_t* public_key_data,
size_t public_key_length, const uint8_t* public_key_metadata, size_t public_key_metadata_length,
bool* out_is_trusted)
{
-#ifdef AVB_USE_TESTKEY
- printf("Verified using testkey\n");
- if (testkey2048_length != public_key_length) {
- *out_is_trusted = false;
- return AVB_IO_RESULT_OK;
+ *out_is_trusted = false;
+
+#ifdef CONFIG_AVB2_KPUB_VENDOR_MULTIPLE
+ if (env_get_yesno("use_external_avb_key") == 1) {
+ for (size_t i = 0; i < avb2_kpub_vendor_external_num && !(*out_is_trusted); i++) {
+ printf("Verifying with vendor external key[%zu]\n", i);
+ if (_validate_key(avb2_kpub_vendor_external[i], avb2_kpub_vendor_external_len[i],
+ public_key_data, public_key_length)) {
+ *out_is_trusted = true;
+ }
+ }
+ } else {
+ for (size_t i = 0; i < avb2_kpub_vendor_num && !(*out_is_trusted); i++) {
+ printf("Verifying with vendor key[%zu]\n", i);
+ if (_validate_key(avb2_kpub_vendor[i], avb2_kpub_vendor_len[i],
+ public_key_data, public_key_length)) {
+ *out_is_trusted = true;
+ }
+ }
}
- if (!avb_safe_memcmp(public_key_data, testkey2048, testkey2048_length))
- *out_is_trusted = true;
- else
- *out_is_trusted = false;
-#else
- unsigned long bl31_addr = get_sharemem_info(GET_SHARE_MEM_INPUT_BASE);
- memcpy((void *)bl31_addr, public_key_data, public_key_length);
- flush_cache(bl31_addr, public_key_length);
- *out_is_trusted = aml_sec_boot_check(AML_D_P_AVB_PUBKEY_VERIFY,
- bl31_addr, public_key_length, 0);
#endif
+
+#ifdef CONFIG_AVB2_KPUB_DEFAULT
+ if (!(*out_is_trusted)) {
+ if (get_board_variant() != BOARD_VARIANT_DEV) {
+ printf("The default key is disabled\n");
+ } else {
+ printf("Verifying with the default key\n");
+ if (_validate_key(avb2_kpub_default, avb2_kpub_default_len,
+ public_key_data, public_key_length)) {
+ *out_is_trusted = true;
+ }
+ }
+ }
+#endif
+
+ if (!(*out_is_trusted))
+ printf("AVB2 key in bootloader does not match with the key in vbmeta\n");
+
return AVB_IO_RESULT_OK;
}
@@ -212,6 +267,12 @@
static AvbIOResult read_is_device_unlocked(AvbOps* ops, bool* out_is_unlocked)
{
+ if (get_board_variant() != BOARD_VARIANT_DEV) {
+ printf("The device is force locked\n");
+ *out_is_unlocked = false;
+ return AVB_IO_RESULT_OK;
+ }
+
#ifdef CONFIG_AML_ANTIROLLBACK
uint32_t lock_state;
char *lock_s;
@@ -288,14 +349,31 @@
int avb_verify(AvbSlotVerifyData** out_data)
{
- const char * const requested_partitions[5] = {"boot", "recovery", "dtb", NULL};
+ const char * requested_partitions_ab[AVB_NUM_SLOT + 1] = {
+ "boot", "dtbo", "vendor_boot", NULL, NULL};
+ const char * requested_partitions[AVB_NUM_SLOT + 1] = {
+ "boot", "dt", "dtbo", NULL, NULL};
AvbSlotVerifyResult result = AVB_SLOT_VERIFY_RESULT_OK;
- char *s1;
- char *ab_suffix;
- run_command("get_valid_slot;", 0);
+ char *s1 = NULL;
+ char *ab_suffix = NULL;
+ uint32_t i = 0;
+
s1 = env_get("active_slot");
- printf("active_slot is %s\n", s1);
- if (strcmp(s1, "normal") == 0) {
+ if (!s1) {
+ run_command("get_valid_slot;", 0);
+ s1 = env_get("active_slot");
+ }
+
+ if (s1 != NULL) {
+ printf("active_slot is %s\n", s1);
+ if (strcmp(s1, "normal") == 0) {
+ ab_suffix = "";
+ } else {
+ ab_suffix = env_get("active_slot");
+ }
+ }
+
+ if (ab_suffix == NULL) {
ab_suffix = "";
} else {
ab_suffix = env_get("active_slot");
@@ -312,7 +390,25 @@
if (is_device_unlocked() || !strcmp(upgradestep, "3"))
flags |= AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR;
- result = avb_slot_verify(&avb_ops_, requested_partitions, ab_suffix,
+ if (!strcmp(ab_suffix, "")) {
+ for (i = 0; i < AVB_NUM_SLOT; i++) {
+ if (requested_partitions[i] == NULL) {
+ requested_partitions[i] = "recovery";
+ break;
+ }
+ }
+ if (i == AVB_NUM_SLOT) {
+ printf("ERROR: failed to find an empty slot for recovery");
+ return AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT;
+ }
+ }
+
+ if (!strcmp(ab_suffix, ""))
+ result = avb_slot_verify(&avb_ops_, requested_partitions, ab_suffix,
+ flags,
+ AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE, out_data);
+ else
+ result = avb_slot_verify(&avb_ops_, requested_partitions_ab, ab_suffix,
flags,
AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE, out_data);
@@ -325,7 +421,7 @@
static int do_avb_verify(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
AvbSlotVerifyResult result = AVB_SLOT_VERIFY_RESULT_OK;
- AvbSlotVerifyData* out_data;
+ AvbSlotVerifyData* out_data = NULL;
uint32_t i = 0;
result = avb_verify(&out_data);
@@ -358,6 +454,9 @@
printf("rpmb lock state: %u\n", lock_state);
#endif
+ }
+
+ if (out_data != NULL) {
avb_slot_verify_data_free(out_data);
}
@@ -386,10 +485,9 @@
}
}
-#if defined(CONFIG_CMD_AVB)
+
U_BOOT_CMD(
avb, 2, 0, do_avb_ops,
"avb",
"\nThis command will trigger related avb operations\n"
);
-#endif
diff --git a/cmd/amlogic/cmd_bcb.c b/cmd/amlogic/cmd_bcb.c
index c9a68b7..7315dda 100644
--- a/cmd/amlogic/cmd_bcb.c
+++ b/cmd/amlogic/cmd_bcb.c
@@ -1,13 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2013 Amlogic, Inc
- *
- * This file is used to run commands from misc partition
- * More detail to check the command "run bcb_cmd" usage
- *
- * cheng.wang@amlogic.com,
- * 2015-04-23 @ Shenzhen
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include <common.h>
#include <command.h>
#include <environment.h>
@@ -30,6 +25,9 @@
#define CMD_WIPE_DATA "wipe_data"
#define CMD_SYSTEM_CRASH "system_crash"
#define CMD_RUN_RECOVERY "boot-recovery"
+#define CMD_RESIZE_DATA "resize2fs_data"
+#define CMD_FOR_RECOVERY "recovery_"
+#define CMD_FASTBOOTD "fastbootd"
struct bootloader_message {
char command[32];
@@ -52,7 +50,7 @@
char *partition = "misc";
memset(clearbuf, 0, size);
- if (store_write((unsigned char *)partition,
+ if (store_write((const char *)partition,
0, size, (unsigned char *)clearbuf) < 0) {
printf("failed to clear %s.\n", partition);
return -1;
@@ -73,6 +71,8 @@
char recovery[RECOVERYBUF_SIZE] = {0};
char miscbuf[MISCBUF_SIZE] = {0};
char clearbuf[COMMANDBUF_SIZE+STATUSBUF_SIZE+RECOVERYBUF_SIZE] = {0};
+ char* RebootMode;
+ char* ActiveSlot;
if (argc != 2) {
return cmd_usage(cmdtp);
@@ -97,16 +97,33 @@
printf("Start to write --wipe_data to %s\n", partition);
memcpy(miscbuf, CMD_RUN_RECOVERY, sizeof(CMD_RUN_RECOVERY));
memcpy(miscbuf+sizeof(command)+sizeof(status), "recovery\n--wipe_data", sizeof("recovery\n--wipe_data"));
- store_write((unsigned char *)partition, 0, sizeof(miscbuf), (unsigned char *)miscbuf);
+ store_write((const char *)partition, 0, sizeof(miscbuf), (unsigned char *)miscbuf);
} else if (!memcmp(command_mark, CMD_SYSTEM_CRASH, strlen(command_mark))) {
printf("Start to write --system_crash to %s\n", partition);
memcpy(miscbuf, CMD_RUN_RECOVERY, sizeof(CMD_RUN_RECOVERY));
memcpy(miscbuf+sizeof(command)+sizeof(status), "recovery\n--system_crash", sizeof("recovery\n--system_crash"));
- store_write((unsigned char *)partition, 0, sizeof(miscbuf), (unsigned char *)miscbuf);
+ store_write((const char *)partition, 0, sizeof(miscbuf), (unsigned char *)miscbuf);
+ } else if (!memcmp(command_mark, CMD_RESIZE_DATA, strlen(command_mark))) {
+ printf("Start to write --resize2fs_data to %s\n", partition);
+ memcpy(miscbuf, CMD_RUN_RECOVERY, sizeof(CMD_RUN_RECOVERY));
+ memcpy(miscbuf+sizeof(command)+sizeof(status), "recovery\n--resize2fs_data", sizeof("recovery\n--resize2fs_data"));
+ store_write((const char *)partition, 0, sizeof(miscbuf), (unsigned char *)miscbuf);
+ } else if (!memcmp(command_mark, CMD_FOR_RECOVERY, strlen(CMD_FOR_RECOVERY))) {
+ memcpy(miscbuf, CMD_RUN_RECOVERY, sizeof(CMD_RUN_RECOVERY));
+ sprintf(recovery, "%s%s", "recovery\n--", command_mark);
+ memcpy(miscbuf+sizeof(command)+sizeof(status), recovery, strlen(recovery));
+ store_write((const char *)partition, 0, sizeof(miscbuf), (unsigned char *)miscbuf);
+ return 0;
+ } else if (!memcmp(command_mark, CMD_FASTBOOTD, strlen(command_mark))) {
+ printf("write cmd to enter fastbootd \n");
+ memcpy(miscbuf, CMD_RUN_RECOVERY, sizeof(CMD_RUN_RECOVERY));
+ memcpy(miscbuf+sizeof(command)+sizeof(status), "recovery\n--fastboot", sizeof("recovery\n--fastboot"));
+ store_write((const char *)partition, 0, sizeof(miscbuf), (unsigned char *)miscbuf);
+ return 0;
}
printf("Start read %s partition datas!\n", partition);
- if (store_read((unsigned char *)partition,
+ if (store_read((const char *)partition,
0, sizeof(miscbuf), (unsigned char *)miscbuf) < 0) {
printf("failed to store read %s.\n", partition);
goto ERR;
@@ -129,6 +146,25 @@
printf("[commannd:%s]\n[status:%s]\n[recovery:%s]\n",
command, status, recovery);
+ run_command("get_rebootmode", 0);
+ RebootMode = env_get("reboot_mode");
+ if (strstr(RebootMode, "quiescent") != NULL) {
+ printf("quiescent mode.\n");
+ run_command("run storeargs", 0);
+ run_command("setenv bootargs ${bootargs} androidboot.quiescent=1;", 0);
+ }
+
+ ActiveSlot = env_get("active_slot");
+ if (!ActiveSlot) {
+ run_command("get_valid_slot", 0);
+ ActiveSlot = env_get("active_slot");
+ }
+ if (ActiveSlot && !strstr(ActiveSlot, "normal")) {
+ printf("ab update mode\n");
+ run_command("setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};",
+ 0);
+ }
+
if (!memcmp(command, CMD_RUN_RECOVERY, strlen(CMD_RUN_RECOVERY))) {
if (run_command("run recovery_from_flash", 0) < 0) {
printf("run_command for cmd:run recovery_from_flash failed.\n");
diff --git a/cmd/amlogic/cmd_bootctl.c b/cmd/amlogic/cmd_bootctl.c
index 184181f..74ff178 100644
--- a/cmd/amlogic/cmd_bootctl.c
+++ b/cmd/amlogic/cmd_bootctl.c
@@ -1,13 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2013 Amlogic, Inc
- *
- * This file is used to run commands from misc partition
- * More detail to check the command "run bcb_cmd" usage
- *
- * cheng.wang@amlogic.com,
- * 2015-04-23 @ Shenzhen
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include <common.h>
#include <command.h>
#include <environment.h>
@@ -20,9 +15,15 @@
#include <asm/arch/io.h>
#include <partition_table.h>
#include <version.h>
-#include <amlogic/storage.h>
+
#ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK
+extern int store_read_ops(
+ unsigned char *partition_name,
+ unsigned char * buf, uint64_t off, uint64_t size);
+extern int store_write_ops(
+ unsigned char *partition_name,
+ unsigned char * buf, uint64_t off, uint64_t size);
#define COMMANDBUF_SIZE 32
#define STATUSBUF_SIZE 32
@@ -183,8 +184,8 @@
char *partition = "misc";
//int i;
printf("Start read %s partition datas!\n", partition);
- if (store_read((unsigned char *)partition,
- 0, MISCBUF_SIZE, (unsigned char *)miscbuf) < 0) {
+ if (store_read((const char *)partition, 0, MISCBUF_SIZE,
+ (unsigned char *)miscbuf) < 0) {
printf("failed to store read %s.\n", partition);
return -1;
}
@@ -208,16 +209,18 @@
memcpy(miscbuf+BOOTINFO_OFFSET, info, SLOTBUF_SIZE);
dump_boot_info(info);
#ifdef CONFIG_AML_MTD
- if (NAND_BOOT_FLAG == device_boot_flag || SPI_NAND_FLAG == device_boot_flag) {
+ enum boot_type_e device_boot_flag = store_get_type();
+ if (BOOT_NAND_NFTL == device_boot_flag || BOOT_NAND_MTD== device_boot_flag ||
+ BOOT_SNAND== device_boot_flag) {
int ret = 0;
- ret = run_command("store erase partition misc", 0);
+ ret = run_command("store erase misc 0 0x4000", 0);
if (ret != 0) {
printf("erase partition misc failed!\n");
return false;
}
}
#endif
- store_write((unsigned char *)partition, 0, MISCBUF_SIZE, (unsigned char *)miscbuf);
+ store_write((const char *)partition, 0, MISCBUF_SIZE, (unsigned char *)miscbuf);
return true;
}
@@ -277,7 +280,8 @@
#ifdef CONFIG_AML_MTD
//check if boot_a/b on nand
- if (device_boot_flag == NAND_BOOT_FLAG) {
+ enum boot_type_e device_boot_flag = store_get_type();
+ if (device_boot_flag == BOOT_NAND_MTD) {
struct mtd_info *nand;
nand = get_mtd_device_nm("boot_a");
if (!IS_ERR(nand)) {
@@ -290,27 +294,38 @@
if (slot == 0) {
if (has_boot_slot == 1) {
- setenv("active_slot","_a");
- setenv("boot_part","boot_a");
- setenv("slot-suffixes","0");
+ env_set("active_slot","_a");
+ env_set("boot_part","boot_a");
+ env_set("recovery_part","recovery_a");
+ env_set("slot-suffixes","0");
}
else {
- setenv("active_slot","normal");
- setenv("boot_part","boot");
+ env_set("active_slot","normal");
+ env_set("boot_part","boot");
+ env_set("recovery_part","recovery");
+ env_set("slot-suffixes","-1");
}
}
else {
if (has_boot_slot == 1) {
- setenv("active_slot","_b");
- setenv("boot_part","boot_b");
- setenv("slot-suffixes","1");
+ env_set("active_slot","_b");
+ env_set("boot_part","boot_b");
+ env_set("recovery_part","recovery_b");
+ env_set("slot-suffixes","1");
}
else {
- setenv("active_slot","normal");
- setenv("boot_part","boot");
+ env_set("active_slot","normal");
+ env_set("boot_part","boot");
+ env_set("recovery_part","recovery");
+ env_set("slot-suffixes","-1");
}
}
+ if (dynamic_partition)
+ env_set("partiton_mode","dynamic");
+ else
+ env_set("partiton_mode","normal");
+
return 0;
}
@@ -346,15 +361,17 @@
}
if (strcmp(argv[1], "a") == 0) {
- setenv("active_slot","_a");
- setenv("boot_part","boot_a");
- setenv("slot-suffixes","0");
+ env_set("active_slot","_a");
+ env_set("boot_part","boot_a");
+ env_set("recovery_part","recovery_a");
+ env_set("slot-suffixes","0");
printf("set active slot a \n");
boot_info_set_active_slot(&info, 0);
} else if (strcmp(argv[1], "b") == 0) {
- setenv("active_slot","_b");
- setenv("boot_part","boot_b");
- setenv("slot-suffixes","1");
+ env_set("active_slot","_b");
+ env_set("boot_part","boot_b");
+ env_set("recovery_part","recovery_b");
+ env_set("slot-suffixes","1");
printf("set active slot b \n");
boot_info_set_active_slot(&info, 1);
} else {
@@ -373,16 +390,16 @@
#ifdef CONFIG_SYSTEM_AS_ROOT
system = CONFIG_SYSTEM_AS_ROOT;
#else
- setenv("system_mode","0");
+ env_set("system_mode","0");
return 0;
#endif
strcpy(system, CONFIG_SYSTEM_AS_ROOT);
printf("CONFIG_SYSTEM_AS_ROOT: %s \n", CONFIG_SYSTEM_AS_ROOT);
if (strcmp(system, "systemroot") == 0) {
- setenv("system_mode","1");
+ env_set("system_mode","1");
}
else
- setenv("system_mode","0");
+ env_set("system_mode","0");
return 0;
@@ -390,7 +407,7 @@
int do_GetAvbMode (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- setenv("avb2","0");
+ env_set("avb2","0");
return 0;
}
diff --git a/cmd/amlogic/cmd_bootctl_avb.c b/cmd/amlogic/cmd_bootctl_avb.c
index b2f2395..c05f53a 100644
--- a/cmd/amlogic/cmd_bootctl_avb.c
+++ b/cmd/amlogic/cmd_bootctl_avb.c
@@ -1,13 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2013 Amlogic, Inc
- *
- * This file is used to run commands from misc partition
- * More detail to check the command "run bcb_cmd" usage
- *
- * cheng.wang@amlogic.com,
- * 2015-04-23 @ Shenzhen
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include <common.h>
#include <command.h>
#include <environment.h>
@@ -19,7 +14,6 @@
#include <libavb.h>
#include <version.h>
#include <amlogic/storage.h>
-#include <asm/arch/secure_apb.h>
#ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK
@@ -27,16 +21,6 @@
#define MISCBUF_SIZE 2080
-#ifdef CONFIG_G_AB_SYSTEM
-/* offset definition of slot x */
-#define SLOT_PRIORITY_OFFSET 0
-#define SLOT_TRIES_REMAINING_OFFSET 8
-#define SLOT_SUCCESSFUL_BOOT_OFFSET 16
-#define SLOT_STICKY_REG_VALID_OFFSET 24
-#define SLOT_MISC_CORRUPTION_OFFSET 25
-#define SLOT_NEXT_BOOT_OFFSET 24
-#define SLOT_CUR_BOOT_OFFSET 28
-#endif
/* Magic for the A/B struct when serialized. */
#define AVB_AB_MAGIC "\0AB0"
@@ -116,56 +100,6 @@
return 0;
}*/
-#ifdef CONFIG_G_AB_SYSTEM
-void boot_info_update(AvbABData *info)
-{
- unsigned int sticky_reg0_val;
- unsigned int sticky_reg1_val;
-
- sticky_reg0_val = readl(P_AO_RTI_STICKY_REG0);
- sticky_reg1_val = readl(P_AO_RTI_STICKY_REG1);
-
- info->slots[0].priority = (sticky_reg0_val >> SLOT_PRIORITY_OFFSET) & 0xff;
- info->slots[0].tries_remaining = (sticky_reg0_val >> SLOT_TRIES_REMAINING_OFFSET) & 0xff;
- info->slots[0].successful_boot = (sticky_reg0_val >> SLOT_SUCCESSFUL_BOOT_OFFSET) & 0xff;
- info->slots[1].priority = (sticky_reg1_val >> SLOT_PRIORITY_OFFSET) & 0xff;
- info->slots[1].tries_remaining = (sticky_reg1_val >> SLOT_TRIES_REMAINING_OFFSET) & 0xff;
- info->slots[1].successful_boot = (sticky_reg1_val >> SLOT_SUCCESSFUL_BOOT_OFFSET) & 0xff;
-}
-
-void boot_info_save_to_reg(AvbABData *info, char *slot)
-{
- unsigned int sticky_reg0_val = 0;
- unsigned int sticky_reg1_val = 0;
- unsigned int cur_slot_index = 0;
- unsigned int next_boot_slot_index = 0;
-
- sticky_reg0_val = ((info->slots[0].priority & 0xff) << SLOT_PRIORITY_OFFSET) |
- ((info->slots[0].tries_remaining & 0xff) << SLOT_TRIES_REMAINING_OFFSET) |
- ((info->slots[0].successful_boot & 0xff) << SLOT_SUCCESSFUL_BOOT_OFFSET);
- sticky_reg1_val = ((info->slots[1].priority & 0xff) << SLOT_PRIORITY_OFFSET) |
- ((info->slots[1].tries_remaining & 0xff) << SLOT_TRIES_REMAINING_OFFSET) |
- ((info->slots[1].successful_boot & 0xff) << SLOT_SUCCESSFUL_BOOT_OFFSET);
-
- /* mark the sticky register is valid */
- sticky_reg0_val |= (1 << SLOT_STICKY_REG_VALID_OFFSET);
- /* set slot_x to cur_slot_index and next_boot_slot_index */
- if (!strcmp(slot, "a")) {
- cur_slot_index = 0;
- next_boot_slot_index = 0;
- }
- else if (!strcmp(slot, "b")) {
- cur_slot_index = 1;
- next_boot_slot_index = 1;
- }
- sticky_reg1_val |= ((cur_slot_index << SLOT_CUR_BOOT_OFFSET) |
- (next_boot_slot_index << SLOT_NEXT_BOOT_OFFSET));
-
- writel(sticky_reg0_val, P_AO_RTI_STICKY_REG0);
- writel(sticky_reg1_val, P_AO_RTI_STICKY_REG1);
-}
-#endif
-
bool boot_info_validate(AvbABData* info)
{
if (memcmp(info->magic, AVB_AB_MAGIC, AVB_AB_MAGIC_LEN) != 0) {
@@ -195,6 +129,7 @@
void dump_boot_info(AvbABData* info)
{
+#if 0
printf("info->magic = %s\n", info->magic);
printf("info->version_major = %d\n", info->version_major);
printf("info->version_minor = %d\n", info->version_minor);
@@ -206,14 +141,13 @@
printf("info->slots[1].successful_boot = %d\n", info->slots[1].successful_boot);
printf("info->crc32 = %d\n", info->crc32);
+#endif
}
-#ifndef CONFIG_G_AB_SYSTEM
static bool slot_is_bootable(AvbABSlotData* slot) {
return slot->priority > 0 &&
(slot->successful_boot || (slot->tries_remaining > 0));
}
-#endif
int get_active_slot(AvbABData* info) {
if (info->slots[0].priority > info->slots[1].priority)
@@ -222,38 +156,7 @@
return 1;
}
-#ifdef CONFIG_G_AB_SYSTEM
-int boot_info_set_active_slot(AvbABData* info, int slot, int switch_flag)
-{
- unsigned int other_slot_number;
- /* Make requested slot top priority, unsuccessful, and with max tries. */
- info->slots[slot].priority = AVB_AB_MAX_PRIORITY;
- info->slots[slot].tries_remaining = AVB_AB_MAX_TRIES_REMAINING;
- info->slots[slot].successful_boot = 0;
-
- /* Ensure other slot doesn't have as high a priority. */
- other_slot_number = 1 - slot;
- if (switch_flag == 0) {
- /* switch good slot to good slot, reduce the priority of the current slot */
- if (info->slots[other_slot_number].priority == AVB_AB_MAX_PRIORITY) {
- info->slots[other_slot_number].priority = AVB_AB_MAX_PRIORITY - 1;
- }
- }
- else {
- /* switch bad slot to good slot, mark the current slot to bad */
- info->slots[other_slot_number].priority = 0;
- info->slots[other_slot_number].tries_remaining = 0;
- info->slots[other_slot_number].successful_boot = 0;
- }
-
-#ifdef BL33_DEBUG_PRINT
- dump_boot_info(info);
-#endif
- return 0;
-}
-
-#else
int boot_info_set_active_slot(AvbABData* info, int slot)
{
unsigned int other_slot_number;
@@ -273,14 +176,13 @@
return 0;
}
-#endif
int boot_info_open_partition(char *miscbuf)
{
char *partition = "misc";
//int i;
printf("Start read %s partition datas!\n", partition);
- if (store_read((unsigned char *)partition,
+ if (store_read((const char *)partition,
0, MISCBUF_SIZE, (unsigned char *)miscbuf) < 0) {
printf("failed to store read %s.\n", partition);
return -1;
@@ -302,19 +204,12 @@
{
char *partition = "misc";
printf("save boot-info \n");
-#ifdef CONFIG_G_AB_SYSTEM
- info->crc32 = avb_crc32((const uint8_t*)info, sizeof(AvbABData) - sizeof(uint32_t));
- memcpy(miscbuf, info, AVB_AB_DATA_SIZE);
-#else
info->crc32 = avb_htobe32(
avb_crc32((const uint8_t*)info, sizeof(AvbABData) - sizeof(uint32_t)));
memcpy(miscbuf+AB_METADATA_MISC_PARTITION_OFFSET, info, AVB_AB_DATA_SIZE);
-#endif
-#ifdef BL33_DEBUG_PRINT
dump_boot_info(info);
-#endif
- store_write((unsigned char *)partition, 0, MISCBUF_SIZE, (unsigned char *)miscbuf);
+ store_write((const char *)partition, 0, MISCBUF_SIZE, (unsigned char *)miscbuf);
return true;
}
@@ -324,47 +219,6 @@
int argc,
char * const argv[])
{
-#ifdef CONFIG_G_AB_SYSTEM
- unsigned int cur_slot_index;
- unsigned int sticky_reg0_val = 0;
- unsigned int sticky_reg1_val = 0;
- unsigned int misc_corruption_flag = 0;
-
- sticky_reg1_val = readl(P_AO_RTI_STICKY_REG1);
- sticky_reg0_val = readl(P_AO_RTI_STICKY_REG0);
- cur_slot_index = (sticky_reg1_val >> SLOT_CUR_BOOT_OFFSET) & 0xf;
- misc_corruption_flag = (sticky_reg0_val >> SLOT_MISC_CORRUPTION_OFFSET) & 0x1;
-
- pr_info("The index of active slot is:0x%x\n", cur_slot_index);
- if (cur_slot_index == 0) {
- env_set("active_slot","_a");
- env_set("boot_part","boot_a");
- env_set("slot-suffixes","a");
- }
- else if (cur_slot_index == 1) {
- env_set("active_slot","_b");
- env_set("boot_part","boot_b");
- env_set("slot-suffixes","b");
- }
- else {
- printf("Invalid slot num\n");
- return -1;
- }
- has_boot_slot = 1;
- has_system_slot = 1;
-
- /* the misc image is damaged, it's should boot from slot a */
- if ((misc_corruption_flag == 1) && (cur_slot_index == 0)) {
- /* reconstruct a default misc image and write to misc partition */
- char miscbuf[MISCBUF_SIZE] = {0};
- AvbABData info;
- pr_info("reconstruct a default misc image\n");
- boot_info_reset(&info);
- boot_info_save_to_reg(&info, "a");
- boot_info_save(&info, miscbuf);
- }
-
-#else
char miscbuf[MISCBUF_SIZE] = {0};
AvbABData info;
int slot;
@@ -389,15 +243,32 @@
bootable_a = slot_is_bootable(&(info.slots[0]));
bootable_b = slot_is_bootable(&(info.slots[1]));
+ if (dynamic_partition)
+ env_set("partiton_mode","dynamic");
+ else
+ env_set("partiton_mode","normal");
+
+ if (vendor_boot_partition) {
+ env_set("vendor_boot_mode","true");
+ printf("set vendor_boot_mode true\n");
+ }
+ else {
+ env_set("vendor_boot_mode","false");
+ printf("set vendor_boot_mode false\n");
+ }
+
if ((slot == 0) && (bootable_a)) {
if (has_boot_slot == 1) {
env_set("active_slot","_a");
env_set("boot_part","boot_a");
+ env_set("recovery_part","recovery_a");
env_set("slot-suffixes","0");
}
else {
env_set("active_slot","normal");
env_set("boot_part","boot");
+ env_set("recovery_part","recovery");
+ env_set("slot-suffixes","-1");
}
return 0;
}
@@ -406,15 +277,17 @@
if (has_boot_slot == 1) {
env_set("active_slot","_b");
env_set("boot_part","boot_b");
+ env_set("recovery_part","recovery_b");
env_set("slot-suffixes","1");
}
else {
env_set("active_slot","normal");
env_set("boot_part","boot");
+ env_set("recovery_part","recovery");
+ env_set("slot-suffixes","-1");
}
return 0;
}
-#endif
return 0;
}
@@ -428,11 +301,7 @@
char miscbuf[MISCBUF_SIZE] = {0};
AvbABData info;
-#ifdef CONFIG_G_AB_SYSTEM
- if (argc != 3) {
-#else
if (argc != 2) {
-#endif
return cmd_usage(cmdtp);
}
@@ -441,17 +310,6 @@
return -1;
}
-#ifdef CONFIG_G_AB_SYSTEM
- unsigned int switch_flag;
- /* get default data from sticky register */
- boot_info_reset(&info);
- boot_info_update(&info);
- switch_flag = (unsigned int)simple_strtoul(argv[2], NULL, 16);
- if ((switch_flag != 0) && (switch_flag != 1)) {
- printf("Invalid flag for switch slot\n");
- return -1;
- }
-#else
boot_info_open_partition(miscbuf);
boot_info_load(&info, miscbuf);
@@ -460,39 +318,26 @@
boot_info_reset(&info);
boot_info_save(&info, miscbuf);
}
-#endif
if (strcmp(argv[1], "a") == 0) {
env_set("active_slot","_a");
- env_set("boot_part","boot_a");
- printf("set active slot a \n");
-#ifdef CONFIG_G_AB_SYSTEM
- env_set("slot-suffixes","a");
- boot_info_set_active_slot(&info, 0, switch_flag);
-#else
env_set("slot-suffixes","0");
+ env_set("boot_part","boot_a");
+ env_set("recovery_part","recovery_a");
+ printf("set active slot a \n");
boot_info_set_active_slot(&info, 0);
-#endif
} else if (strcmp(argv[1], "b") == 0) {
env_set("active_slot","_b");
- env_set("boot_part","boot_b");
- printf("set active slot b \n");
-#ifdef CONFIG_G_AB_SYSTEM
- env_set("slot-suffixes","b");
- boot_info_set_active_slot(&info, 1, switch_flag);
-#else
env_set("slot-suffixes","1");
+ env_set("boot_part","boot_b");
+ env_set("recovery_part","recovery_b");
+ printf("set active slot b \n");
boot_info_set_active_slot(&info, 1);
-#endif
} else {
printf("error input slot\n");
return -1;
}
-#ifdef CONFIG_G_AB_SYSTEM
- /* save new ab data to sticky register */
- boot_info_save_to_reg(&info, argv[1]);
-#endif
boot_info_save(&info, miscbuf);
return 0;
@@ -538,81 +383,6 @@
return 0;
}
-#ifdef CONFIG_G_AB_SYSTEM
-/* write sticky register to misc partitioin */
-int do_SyncAvbData(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char miscbuf[MISCBUF_SIZE] = {0};
- AvbABData info;
-
- /* init ab data */
- boot_info_reset(&info);
- /* copy ab data from sticky register to info struct */
- boot_info_update(&info);
- /* write ab data to misc partition */
- boot_info_save(&info, miscbuf);
- /* clear stick register */
- writel(0x0, P_AO_RTI_STICKY_REG0);
- writel(0x0, P_AO_RTI_STICKY_REG1);
-
- return 0;
-}
-
-U_BOOT_CMD(
- sync_ab_data, 1,0, do_SyncAvbData,
- "sync_ab_data",
- "\nThis command will write the sticky register to misc partitioin\n"
- "So you can execute command: sync_ab_data"
-);
-
-int do_GetSlotState(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned int sticky_reg_val = 0;
- unsigned int result = 0;
- char cur_retry_count_str[8] = {0};
-
- if (argc != 3) {
- return cmd_usage(cmdtp);
- }
-
- if (!strcmp(argv[1], "a")) {
- sticky_reg_val = readl(P_AO_RTI_STICKY_REG0);
- }
-
- else if (!strcmp(argv[1], "b")) {
- sticky_reg_val = readl(P_AO_RTI_STICKY_REG1);
- }
- else {
- return cmd_usage(cmdtp);
- }
-
- if (!strcmp(argv[2], "successful")) {
- result = (sticky_reg_val >> SLOT_SUCCESSFUL_BOOT_OFFSET) & 0xff;
- }
- else if (!strcmp(argv[2], "unbootable")) {
- result = (sticky_reg_val >> SLOT_PRIORITY_OFFSET) & 0xff;
- }
- else if (!strcmp(argv[2], "retry-count")) {
- result = (sticky_reg_val >> SLOT_TRIES_REMAINING_OFFSET) & 0xff;
- /* For command: fastboot getvar slot-retry-count:slot_x */
- snprintf(cur_retry_count_str, sizeof(cur_retry_count_str), "%d", result);
- env_set("cur_retry_count", cur_retry_count_str);
- }
- else {
- return cmd_usage(cmdtp);
- }
-
- printf("slot %s: %s = %d\n", argv[1], argv[2], result);
- return result;
-}
-
-U_BOOT_CMD(
- get_slot_state, 3,0, do_GetSlotState,
- "get_slot_state",
- "\nThis command will get the slot status\n"
- "So you can execute command: get_slot_state [a|b] [successful|unbootable|retry-count]"
-);
-#endif
#endif /* CONFIG_BOOTLOADER_CONTROL_BLOCK */
@@ -624,24 +394,12 @@
"So you can execute command: get_valid_slot"
);
-#ifdef CONFIG_G_AB_SYSTEM
-U_BOOT_CMD(
- set_active_slot, 3, 1, do_SetActiveSlot,
- "set_active_slot",
- "\nThis command will set active slot\n"
- "set_active_slot slot_name switch_flag\n"
- " slot_name: a|b\n"
- " switch_flag: 0 - switch good slot to good slot\n"
- " 1 - switch bad slot to good slot"
-);
-#else
U_BOOT_CMD(
set_active_slot, 2, 1, do_SetActiveSlot,
"set_active_slot",
"\nThis command will set active slot\n"
"So you can execute command: set_active_slot a"
);
-#endif
U_BOOT_CMD(
get_system_as_root_mode, 1, 0, do_GetSystemMode,
diff --git a/cmd/amlogic/cmd_bootctl_vab.c b/cmd/amlogic/cmd_bootctl_vab.c
new file mode 100644
index 0000000..f10ce2a
--- /dev/null
+++ b/cmd/amlogic/cmd_bootctl_vab.c
@@ -0,0 +1,690 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <malloc.h>
+#include <asm/byteorder.h>
+#include <config.h>
+#include <asm/arch/io.h>
+#include <partition_table.h>
+#include <libavb.h>
+#include <version.h>
+#include <amlogic/storage.h>
+#include <fastboot.h>
+
+#ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+// Spaces used by misc partition are as below:
+// 0 - 2K For bootloader_message
+// 2K - 16K Used by Vendor's bootloader (the 2K - 4K range may be optionally used
+// as bootloader_message_ab struct)
+// 16K - 32K Used by uncrypt and recovery to store wipe_package for A/B devices
+// 32K - 64K System space, used for miscellanious AOSP features. See below.
+// Note that these offsets are admitted by bootloader,recovery and uncrypt, so they
+// are not configurable without changing all of them.
+#define BOOTLOADER_MESSAGE_OFFSET_IN_MISC 0
+#define VENDOR_SPACE_OFFSET_IN_MISC 2 * 1024
+#define WIPE_PACKAGE_OFFSET_IN_MISC 16 * 1024
+#define SYSTEM_SPACE_OFFSET_IN_MISC 32 * 1024
+#define SYSTEM_SPACE_SIZE_IN_MISC 32 * 1024
+
+
+#define AB_METADATA_MISC_PARTITION_OFFSET 2048
+
+#define MISCBUF_SIZE 2080
+
+/* Bootloader Message (2-KiB)
+ *
+ * This structure describes the content of a block in flash
+ * that is used for recovery and the bootloader to talk to
+ * each other.
+ *
+ * The command field is updated by linux when it wants to
+ * reboot into recovery or to update radio or bootloader firmware.
+ * It is also updated by the bootloader when firmware update
+ * is complete (to boot into recovery for any final cleanup)
+ *
+ * The status field was used by the bootloader after the completion
+ * of an "update-radio" or "update-hboot" command, which has been
+ * deprecated since Froyo.
+ *
+ * The recovery field is only written by linux and used
+ * for the system to send a message to recovery or the
+ * other way around.
+ *
+ * The stage field is written by packages which restart themselves
+ * multiple times, so that the UI can reflect which invocation of the
+ * package it is. If the value is of the format "#/#" (eg, "1/3"),
+ * the UI will add a simple indicator of that status.
+ *
+ * We used to have slot_suffix field for A/B boot control metadata in
+ * this struct, which gets unintentionally cleared by recovery or
+ * uncrypt. Move it into struct bootloader_message_ab to avoid the
+ * issue.
+ */
+struct bootloader_message {
+ char command[32];
+ char status[32];
+ char recovery[768];
+
+ // The 'recovery' field used to be 1024 bytes. It has only ever
+ // been used to store the recovery command line, so 768 bytes
+ // should be plenty. We carve off the last 256 bytes to store the
+ // stage string (for multistage packages) and possible future
+ // expansion.
+ char stage[32];
+
+ // The 'reserved' field used to be 224 bytes when it was initially
+ // carved off from the 1024-byte recovery field. Bump it up to
+ // 1184-byte so that the entire bootloader_message struct rounds up
+ // to 2048-byte.
+ char reserved[1184];
+};
+
+/**
+ * The A/B-specific bootloader message structure (4-KiB).
+ *
+ * We separate A/B boot control metadata from the regular bootloader
+ * message struct and keep it here. Everything that's A/B-specific
+ * stays after struct bootloader_message, which should be managed by
+ * the A/B-bootloader or boot control HAL.
+ *
+ * The slot_suffix field is used for A/B implementations where the
+ * bootloader does not set the androidboot.ro.boot.slot_suffix kernel
+ * commandline parameter. This is used by fs_mgr to mount /system and
+ * other partitions with the slotselect flag set in fstab. A/B
+ * implementations are free to use all 32 bytes and may store private
+ * data past the first NUL-byte in this field. It is encouraged, but
+ * not mandatory, to use 'struct bootloader_control' described below.
+ *
+ * The update_channel field is used to store the Omaha update channel
+ * if update_engine is compiled with Omaha support.
+ */
+struct bootloader_message_ab {
+ struct bootloader_message message;
+ char slot_suffix[32];
+ char update_channel[128];
+
+ // Round up the entire struct to 4096-byte.
+ char reserved[1888];
+};
+
+#define BOOT_CTRL_MAGIC 0x42414342 /* Bootloader Control AB */
+#define BOOT_CTRL_VERSION 1
+
+typedef struct slot_metadata {
+ // Slot priority with 15 meaning highest priority, 1 lowest
+ // priority and 0 the slot is unbootable.
+ uint8_t priority : 4;
+ // Number of times left attempting to boot this slot.
+ uint8_t tries_remaining : 3;
+ // 1 if this slot has booted successfully, 0 otherwise.
+ uint8_t successful_boot : 1;
+ // 1 if this slot is corrupted from a dm-verity corruption, 0
+ // otherwise.
+ uint8_t verity_corrupted : 1;
+ // Reserved for further use.
+ uint8_t reserved : 7;
+}slot_metadata;
+
+/* Bootloader Control AB
+ *
+ * This struct can be used to manage A/B metadata. It is designed to
+ * be put in the 'slot_suffix' field of the 'bootloader_message'
+ * structure described above. It is encouraged to use the
+ * 'bootloader_control' structure to store the A/B metadata, but not
+ * mandatory.
+ */
+typedef struct bootloader_control {
+ // NUL terminated active slot suffix.
+ char slot_suffix[4];
+ // Bootloader Control AB magic number (see BOOT_CTRL_MAGIC).
+ uint32_t magic;
+ // Version of struct being used (see BOOT_CTRL_VERSION).
+ uint8_t version;
+ // Number of slots being managed.
+ uint8_t nb_slot : 3;
+ // Number of times left attempting to boot recovery.
+ uint8_t recovery_tries_remaining : 3;
+ // Status of any pending snapshot merge of dynamic partitions.
+ uint8_t merge_status : 3;
+ // Ensure 4-bytes alignment for slot_info field.
+ uint8_t reserved0[1];
+ // Per-slot information. Up to 4 slots.
+ struct slot_metadata slot_info[4];
+ // Reserved for further use.
+ uint8_t reserved1[8];
+ // CRC32 of all 28 bytes preceding this field (little endian
+ // format).
+ uint32_t crc32_le;
+}bootloader_control;
+
+#define MISC_VIRTUAL_AB_MESSAGE_VERSION 2
+#define MISC_VIRTUAL_AB_MAGIC_HEADER 0x56740AB0
+
+unsigned int kDefaultBootAttempts = 7;
+
+bool boot_info_validate(bootloader_control* info)
+{
+ if (info->magic != BOOT_CTRL_MAGIC) {
+ printf("Magic 0x%x is incorrect.\n", info->magic);
+ return false;
+ }
+ return true;
+}
+
+void boot_info_reset(bootloader_control* boot_ctrl)
+{
+ int slot;
+ memset(boot_ctrl, '\0', sizeof(bootloader_control));
+ memcpy(boot_ctrl->slot_suffix, "_a", 2);
+ boot_ctrl->magic = BOOT_CTRL_MAGIC;
+ boot_ctrl->version = BOOT_CTRL_VERSION;
+ boot_ctrl->nb_slot = 2;
+
+ for (slot = 0; slot < 4; ++slot) {
+ slot_metadata entry = {};
+
+ if (slot < boot_ctrl->nb_slot) {
+ entry.priority = 7;
+ entry.tries_remaining = kDefaultBootAttempts;
+ entry.successful_boot = 1;
+ } else {
+ entry.priority = 0; // Unbootable
+ entry.tries_remaining = 0;
+ entry.successful_boot = 0;
+ }
+
+ boot_ctrl->slot_info[slot] = entry;
+ }
+ boot_ctrl->recovery_tries_remaining = 0;
+}
+
+void dump_boot_info(bootloader_control* boot_ctrl)
+{
+#if 0
+ int slot;
+ printf("boot_ctrl->slot_suffix = %s\n", boot_ctrl->slot_suffix);
+ printf("boot_ctrl->magic = 0x%x\n", boot_ctrl->magic);
+ printf("boot_ctrl->version = %d\n", boot_ctrl->version);
+ printf("boot_ctrl->nb_slot = %d\n", boot_ctrl->nb_slot);
+ for (slot = 0; slot < 4; ++slot) {
+ printf("boot_ctrl->slot_info[%d].priority = %d\n", slot, boot_ctrl->slot_info[slot].priority);
+ printf("boot_ctrl->slot_info[%d].tries_remaining = %d\n", slot, boot_ctrl->slot_info[slot].tries_remaining);
+ printf("boot_ctrl->slot_info[%d].successful_boot = %d\n", slot, boot_ctrl->slot_info[slot].successful_boot);
+ }
+ printf("boot_ctrl->recovery_tries_remaining = %d\n", boot_ctrl->recovery_tries_remaining);
+#endif
+}
+
+static bool slot_is_bootable(slot_metadata* slot) {
+ return slot->tries_remaining != 0;
+}
+
+int get_active_slot(bootloader_control* info) {
+ if (info->slot_info[0].priority > info->slot_info[1].priority) {
+ return 0;
+ } else if (info->slot_info[0].priority == info->slot_info[1].priority) {
+ if (info->slot_info[0].successful_boot == 1)
+ return 0;
+ else
+ return 1;
+ } else {
+ return 1;
+ }
+}
+
+
+int boot_info_set_active_slot(bootloader_control* bootctrl, int slot)
+{
+ int i;
+ // Set every other slot with a lower priority than the new "active" slot.
+ const unsigned int kActivePriority = 15;
+ const unsigned int kActiveTries = 6;
+ for (i = 0; i < bootctrl->nb_slot; ++i) {
+ if (i != slot) {
+ if (bootctrl->slot_info[i].priority >= kActivePriority)
+ bootctrl->slot_info[i].priority = kActivePriority - 1;
+ }
+ printf("bootctrl->slot_info[%d].priority = %d\n", i, bootctrl->slot_info[i].priority);
+ }
+
+ // Note that setting a slot as active doesn't change the successful bit.
+ // The successful bit will only be changed by setSlotAsUnbootable().
+ bootctrl->slot_info[slot].priority = kActivePriority;
+ bootctrl->slot_info[slot].tries_remaining = kActiveTries;
+
+ printf("bootctrl->slot_info[%d].priority = %d\n", slot, bootctrl->slot_info[slot].priority);
+ printf("bootctrl->slot_info[%d].tries_remaining = %d\n", slot, bootctrl->slot_info[slot].tries_remaining);
+
+ // Setting the current slot as active is a way to revert the operation that
+ // set *another* slot as active at the end of an updater. This is commonly
+ // used to cancel the pending update. We should only reset the verity_corrpted
+ // bit when attempting a new slot, otherwise the verity bit on the current
+ // slot would be flip.
+ if (slot != get_active_slot(bootctrl)) bootctrl->slot_info[slot].verity_corrupted = 0;
+
+ dump_boot_info(bootctrl);
+
+ return 0;
+}
+
+int boot_info_open_partition(char *miscbuf)
+{
+ char *partition = "misc";
+ printf("Start read %s partition datas!\n", partition);
+ if (store_read((const char *)partition,
+ 0, MISCBUF_SIZE, (unsigned char *)miscbuf) < 0) {
+ printf("failed to store read %s.\n", partition);
+ return -1;
+ }
+ return 0;
+}
+
+bool boot_info_load(bootloader_control *out_info, char *miscbuf)
+{
+ memcpy(out_info, miscbuf+AB_METADATA_MISC_PARTITION_OFFSET, sizeof(bootloader_control));
+ dump_boot_info(out_info);
+ return true;
+}
+
+bool boot_info_save(bootloader_control *info, char *miscbuf)
+{
+ char *partition = "misc";
+ printf("save boot-info \n");
+ info->crc32_le = cpu_to_le32(
+ avb_crc32((const uint8_t*)info, sizeof(bootloader_control) - sizeof(uint32_t)));
+
+ memcpy(miscbuf+AB_METADATA_MISC_PARTITION_OFFSET, info, sizeof(bootloader_control));
+ dump_boot_info(info);
+ store_write((const char *)partition, 0, MISCBUF_SIZE, (unsigned char *)miscbuf);
+ return true;
+}
+
+int write_bootloader(int copy, int dstindex) {
+ int iRet = 0;
+ int ret = -1;
+ unsigned char* buffer = NULL;
+
+ buffer = (unsigned char *)malloc(0x2000 * 512);
+ if (!buffer)
+ {
+ printf("ERROR! fail to allocate memory ...\n");
+ goto exit;
+ }
+ memset(buffer, 0, 0x2000 * 512);
+ printf("copy from boot%d to boot%d\n", copy, dstindex);
+ iRet = store_boot_read("bootloader", copy, 0, buffer);
+ if (iRet) {
+ printf("Fail read bootloader from rsv with sz\n");
+ goto exit;
+ }
+ iRet = store_boot_write("bootloader", dstindex, 0, buffer);
+ if (iRet) {
+ printf("Failed to write bootloader\n");
+ goto exit;
+ } else {
+ ret = 0;
+ }
+
+exit:
+ if (buffer)
+ {
+ free(buffer);
+ buffer = NULL;
+ }
+ return ret;
+}
+
+static int do_GetValidSlot(
+ cmd_tbl_t * cmdtp,
+ int flag,
+ int argc,
+ char * const argv[])
+{
+ char miscbuf[MISCBUF_SIZE] = {0};
+ bootloader_control boot_ctrl;
+ int slot;
+ bool bootable_a, bootable_b;
+
+ if (argc != 1) {
+ return cmd_usage(cmdtp);
+ }
+
+ boot_info_open_partition(miscbuf);
+ boot_info_load(&boot_ctrl, miscbuf);
+
+ if (!boot_info_validate(&boot_ctrl)) {
+ printf("boot-info is invalid. Resetting.\n");
+ boot_info_reset(&boot_ctrl);
+ boot_info_save(&boot_ctrl, miscbuf);
+ }
+
+ slot = get_active_slot(&boot_ctrl);
+ printf("active slot = %d\n", slot);
+
+ bootable_a = slot_is_bootable(&(boot_ctrl.slot_info[0]));
+ bootable_b = slot_is_bootable(&(boot_ctrl.slot_info[1]));
+
+ if (dynamic_partition)
+ env_set("partiton_mode","dynamic");
+ else
+ env_set("partiton_mode","normal");
+
+ if (gpt_partition)
+ env_set("gpt_mode","true");
+ else
+ env_set("gpt_mode","false");
+
+ if (vendor_boot_partition) {
+ env_set("vendor_boot_mode","true");
+ printf("set vendor_boot_mode true\n");
+ }
+ else {
+ env_set("vendor_boot_mode","false");
+ printf("set vendor_boot_mode false\n");
+ }
+
+ if (slot == 0) {
+ if (bootable_a) {
+ if (has_boot_slot == 1) {
+ env_set("active_slot","_a");
+ env_set("boot_part","boot_a");
+ env_set("recovery_part","recovery_a");
+ env_set("slot-suffixes","0");
+ }
+ else {
+ env_set("active_slot","normal");
+ env_set("boot_part","boot");
+ env_set("recovery_part","recovery");
+ env_set("slot-suffixes","-1");
+ }
+ return 0;
+ } else if (bootable_b) {
+ write_bootloader(2, 0);
+#ifdef CONFIG_FASTBOOT
+ struct misc_virtual_ab_message message;
+ set_mergestatus_cancel(&message);
+#endif
+ run_command("set_active_slot b", 0);
+ env_set("update_env","1");
+ env_set("reboot_status","reboot_next");
+ env_set("expect_index","0");
+ run_command("saveenv", 0);
+ run_command("reset", 0);
+ } else {
+ run_command("run init_display; run storeargs; run update;", 0);
+ }
+ }
+
+ if (slot == 1) {
+ if (bootable_b) {
+ if (has_boot_slot == 1) {
+ env_set("active_slot","_b");
+ env_set("boot_part","boot_b");
+ env_set("recovery_part","recovery_b");
+ env_set("slot-suffixes","1");
+ }
+ else {
+ env_set("active_slot","normal");
+ env_set("boot_part","boot");
+ env_set("recovery_part","recovery");
+ env_set("slot-suffixes","-1");
+ }
+ return 0;
+ } else if (bootable_a) {
+ write_bootloader(1, 0);
+#ifdef CONFIG_FASTBOOT
+ struct misc_virtual_ab_message message;
+ set_mergestatus_cancel(&message);
+#endif
+ run_command("set_active_slot a", 0);
+ env_set("update_env","1");
+ env_set("reboot_status","reboot_next");
+ env_set("expect_index","0");
+ run_command("saveenv", 0);
+ run_command("reset", 0);
+ } else {
+ run_command("run init_display; run storeargs; run update;", 0);
+ }
+ }
+
+ return 0;
+}
+
+static int do_SetActiveSlot(
+ cmd_tbl_t * cmdtp,
+ int flag,
+ int argc,
+ char * const argv[])
+{
+ char miscbuf[MISCBUF_SIZE] = {0};
+ bootloader_control info;
+
+ if (argc != 2) {
+ return cmd_usage(cmdtp);
+ }
+
+ if (has_boot_slot == 0) {
+ printf("device is not ab mode\n");
+ return -1;
+ }
+
+ boot_info_open_partition(miscbuf);
+ boot_info_load(&info, miscbuf);
+
+ if (!boot_info_validate(&info)) {
+ printf("boot-info is invalid. Resetting.\n");
+ boot_info_reset(&info);
+ boot_info_save(&info, miscbuf);
+ }
+
+ if (strcmp(argv[1], "a") == 0) {
+ env_set("active_slot","_a");
+ env_set("slot-suffixes","0");
+ env_set("boot_part","boot_a");
+ env_set("recovery_part","recovery_a");
+ printf("set active slot a \n");
+ boot_info_set_active_slot(&info, 0);
+ } else if (strcmp(argv[1], "b") == 0) {
+ env_set("active_slot","_b");
+ env_set("slot-suffixes","1");
+ env_set("boot_part","boot_b");
+ env_set("recovery_part","recovery_b");
+ printf("set active slot b \n");
+ boot_info_set_active_slot(&info, 1);
+ } else {
+ printf("error input slot\n");
+ return -1;
+ }
+
+ boot_info_save(&info, miscbuf);
+
+ return 0;
+}
+
+static int do_SetUpdateTries(
+ cmd_tbl_t * cmdtp,
+ int flag,
+ int argc,
+ char * const argv[])
+{
+ char miscbuf[MISCBUF_SIZE] = {0};
+ bootloader_control boot_ctrl;
+ bool bootable_a, bootable_b;
+ int slot;
+
+ boot_info_open_partition(miscbuf);
+ boot_info_load(&boot_ctrl, miscbuf);
+
+ if (!boot_info_validate(&boot_ctrl)) {
+ printf("boot-info is invalid. Resetting\n");
+ boot_info_reset(&boot_ctrl);
+ boot_info_save(&boot_ctrl, miscbuf);
+ }
+
+ slot = get_active_slot(&boot_ctrl);
+ bootable_a = slot_is_bootable(&(boot_ctrl.slot_info[0]));
+ bootable_b = slot_is_bootable(&(boot_ctrl.slot_info[1]));
+
+ if (slot == 0) {
+ if (bootable_a) {
+ if (boot_ctrl.slot_info[0].successful_boot == 0)
+ boot_ctrl.slot_info[0].tries_remaining -= 1;
+ }
+ }
+
+ if (slot == 1) {
+ if (bootable_b) {
+ if (boot_ctrl.slot_info[1].successful_boot == 0)
+ boot_ctrl.slot_info[1].tries_remaining -= 1;
+ }
+ }
+
+ boot_info_save(&boot_ctrl, miscbuf);
+ return 0;
+}
+
+static int do_CopySlot(
+ cmd_tbl_t * cmdtp,
+ int flag,
+ int argc,
+ char * const argv[])
+{
+ char miscbuf[MISCBUF_SIZE] = {0};
+ bootloader_control boot_ctrl;
+ int copy = -1;
+ int dest = -1;
+
+ boot_info_open_partition(miscbuf);
+ boot_info_load(&boot_ctrl, miscbuf);
+
+ if (!boot_info_validate(&boot_ctrl)) {
+ printf("boot-info is invalid. Resetting\n");
+ boot_info_reset(&boot_ctrl);
+ boot_info_save(&boot_ctrl, miscbuf);
+ }
+
+ if (strcmp(argv[1], "1") == 0) {
+ copy = 1;
+ } else if (strcmp(argv[1], "2") == 0) {
+ copy = 2;
+ } else if (strcmp(argv[1], "0") == 0) {
+ copy = 0;
+ }
+
+ if (strcmp(argv[2], "1") == 0) {
+ dest = 1;
+ } else if (strcmp(argv[2], "2") == 0) {
+ dest = 2;
+ } else if (strcmp(argv[2], "0") == 0) {
+ dest = 0;
+ }
+
+ if (copy == 1) {
+ if (boot_ctrl.slot_info[0].successful_boot == 1)
+ write_bootloader(copy, dest);
+ } else if (copy == 2){
+ if (boot_ctrl.slot_info[1].successful_boot == 1) {
+ write_bootloader(copy, dest);
+ } else {
+ env_set("update_env","1");
+ env_set("reboot_status","reboot_next");
+ env_set("expect_index","2");
+ run_command("saveenv", 0);
+ }
+ }
+
+ return 0;
+}
+
+int do_GetSystemMode (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char* system;
+#ifdef CONFIG_SYSTEM_AS_ROOT
+ system = CONFIG_SYSTEM_AS_ROOT;
+ strcpy(system, CONFIG_SYSTEM_AS_ROOT);
+ printf("CONFIG_SYSTEM_AS_ROOT: %s \n", CONFIG_SYSTEM_AS_ROOT);
+ if (strcmp(system, "systemroot") == 0) {
+ env_set("system_mode","1");
+ }
+ else {
+ env_set("system_mode","0");
+ }
+#else
+ env_set("system_mode","0");
+#endif
+
+ return 0;
+}
+
+int do_GetAvbMode (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+#ifdef CONFIG_AVB2
+ char* avbmode;
+ avbmode = CONFIG_AVB2;
+ strcpy(avbmode, CONFIG_AVB2);
+ printf("CONFIG_AVB2: %s \n", CONFIG_AVB2);
+ if (strcmp(avbmode, "avb2") == 0) {
+ env_set("avb2","1");
+ }
+ else {
+ env_set("avb2","0");
+ }
+#else
+ env_set("avb2","0");
+#endif
+
+ return 0;
+}
+
+
+#endif /* CONFIG_BOOTLOADER_CONTROL_BLOCK */
+
+U_BOOT_CMD(
+ get_valid_slot, 2, 0, do_GetValidSlot,
+ "get_valid_slot",
+ "\nThis command will choose valid slot to boot up which saved in misc\n"
+ "partition by mark to decide whether execute command!\n"
+ "So you can execute command: get_valid_slot"
+);
+
+U_BOOT_CMD(
+ set_active_slot, 2, 1, do_SetActiveSlot,
+ "set_active_slot",
+ "\nThis command will set active slot\n"
+ "So you can execute command: set_active_slot a"
+);
+
+U_BOOT_CMD(
+ copy_slot_bootable, 3, 1, do_CopySlot,
+ "copy_slot_bootable",
+ "\nThis command will set active slot\n"
+ "So you can execute command: copy_slot_bootable 2 1"
+);
+
+U_BOOT_CMD(
+ update_tries, 2, 0, do_SetUpdateTries,
+ "update_tries",
+ "\nThis command will change tries_remaining in misc\n"
+ "So you can execute command: update_tries"
+);
+
+U_BOOT_CMD(
+ get_system_as_root_mode, 1, 0, do_GetSystemMode,
+ "get_system_as_root_mode",
+ "\nThis command will get system_as_root_mode\n"
+ "So you can execute command: get_system_as_root_mode"
+);
+
+U_BOOT_CMD(
+ get_avb_mode, 1, 0, do_GetAvbMode,
+ "get_avb_mode",
+ "\nThis command will get avb mode\n"
+ "So you can execute command: get_avb_mode"
+);
+
diff --git a/cmd/amlogic/cmd_cvbs.c b/cmd/amlogic/cmd_cvbs.c
index 259f3fc..b207cd2 100644
--- a/cmd/amlogic/cmd_cvbs.c
+++ b/cmd/amlogic/cmd_cvbs.c
@@ -1,22 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2012
- * Amlogic. Inc. jets.yan@amlogic.com
- *
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -37,12 +21,9 @@
{
if ((argc != 2) && (argc != 3) && (argc != 4) && (argc != 5)) {
printf("cvbs debug command format as:\n"
- " r h/v address\n"
- " w value h/v address\n"
- " dump h/v addr_start addr_end\n"
" enci\n"
" clock\n"
- " set_clkpath 0/1/2/3\n");
+ " clkpath 0/1/2/3\n");
return CMD_RET_FAILURE;
}
@@ -116,12 +97,9 @@
"cvbs init\n"
" init of cvbs\n"
"cvbs debug\n"
- " r h/v address\n"
- " w value h/v address\n"
- " dump h/v addr_start addr_end\n"
" enci\n"
" clock\n"
- " set_clkpath 0/1/2/3\n"
+ " clkpath 0/1/2/3\n"
"cvbs output [FORMAT | bist MODE]\n"
" FORMAT : [576cvbs|480cvbs|ntsc_m|pal_m|pal_n]\n"
" bist mode : [off|1 or colorbar|2 or thinline|3 or dotgrid|0 or fixval]\n"
diff --git a/cmd/amlogic/cmd_d2pll.c b/cmd/amlogic/cmd_d2pll.c
index eb03826..fff2512 100644
--- a/cmd/amlogic/cmd_d2pll.c
+++ b/cmd/amlogic/cmd_d2pll.c
@@ -1,5 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Command d2pll & ddrtest support.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -7,8 +8,8 @@
#include <asm/arch/io.h>
#include <asm/arch/secure_apb.h>
#include <asm/arch/romboot.h>
-#include <asm/arch/watchdog.h>
-#include <asm/arch/cpu_id.h>
+#include <asm/arch/cpu_reset.h>
+#include <amlogic/cpu_id.h>
int do_ddr2pll(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
diff --git a/cmd/amlogic/cmd_ddr_test.c b/cmd/amlogic/cmd_ddr_test.c
index 09dcdb1..5d0901c 100644
--- a/cmd/amlogic/cmd_ddr_test.c
+++ b/cmd/amlogic/cmd_ddr_test.c
@@ -1,5 +1,9 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include <common.h>
-#include <u-boot/sha256.h>
//#include <asm/arch/secure_apb.h>
@@ -14,21 +18,6 @@
//#ifndef char* itoa(intnum,char*str,intradix)
-#define USE_FOR_NEWMAN
-#define USE_FOR_UBOOT_2018
-#ifdef USE_FOR_NEWMAN
-///*
-int setenv(const char *varname, const char *varvalue)
-{
-return 1;
-}
-
-char *getenv(const char *name)
-{
- return NULL;
-}
-//*/
-#endif
#define DWC_AC_PINMUX_TOTAL 28
#define DWC_DFI_PINMUX_TOTAL 26
@@ -69,7 +58,7 @@
read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
read_value=(read_value>>((addr%4)<<3))&0xffff;
return read_value;
-
+
}
static uint32_t ddr_wr_16bit_on_32reg(uint32_t addr,uint32_t value)
{
@@ -82,7 +71,7 @@
*(volatile uint32_t *)(( unsigned long )(addr_t))=write_value;
return write_value;
-
+
}
*/
static uint32_t ddr_rd_8_16bit_on_32reg(uint32_t base_addr,uint32_t size,uint32_t offset_index)
@@ -90,21 +79,21 @@
uint32_t read_value=0;
uint32_t addr_t=0;
uint32_t offset=0;
- if(size==8){
+ if (size == 8) {
offset=((offset_index%4)<<3);
addr_t=(base_addr+((offset_index>>2) << 2));
read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
read_value=(read_value>>offset)&0xff;
-
+
}
- if(size==16){
+ if (size == 16) {
offset=((offset_index%2)<<4);
addr_t=(base_addr+((offset_index>>1) << 2));
read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
read_value=(read_value>>offset)&0xffff;
}
return read_value;
-
+
}
static uint32_t ddr_wr_8_16bit_on_32reg(uint32_t base_addr,uint32_t size,uint32_t offset_index,uint32_t value)
{
@@ -112,13 +101,13 @@
uint32_t write_value=0;
uint32_t addr_t=0;
uint32_t offset=0;
- if(size==8){
+ if (size == 8) {
offset=((offset_index%4)<<3);
addr_t=(base_addr+((offset_index>>2) << 2));
read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
write_value=(value<<offset)|(read_value&(~(0xff<<offset)));
}
- if(size==16){
+ if (size == 16) {
offset=((offset_index%2)<<4);
addr_t=(base_addr+((offset_index>>1) << 2));
read_value= (*(volatile uint32_t *)(( unsigned long )(addr_t)));
@@ -129,8 +118,7 @@
}
typedef struct ddr_set{
unsigned int magic;
- unsigned char fast_boot[4];// 0 fastboot enable 1 window test margin(bit0-3 read bit 4-7 write) 2 auto offset after window test (bit0-3 read bit 4-7 write) 3 auto window test index(bit 7 use for if enable usb download do window test ,bit 6 use for flash)
-// unsigned int rsv_int0;
+ unsigned int rsv_int0;
unsigned char board_id;
//board id reserve,,do not modify
unsigned char version;
@@ -188,9 +176,7 @@
unsigned short training_SequenceCtrl[2];
//system reserve,do not modify
- unsigned char phy_odt_config_rank[2];
- unsigned char rever1;
- unsigned char rever2;
+ unsigned char phy_odt_config_rank[4];
//training odt config ,only use for training
// [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
// [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
@@ -278,23 +264,19 @@
//soc init SOC receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
unsigned short vref_dram_permil;
//soc init DRAM receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
- unsigned short max_core_timmming_frequency;
- //use for limited ddr speed core timmming parameter,for some old dram maybe have no over speed register
+ unsigned short vref_reverse;
+ //system reserve,do not modify
/* align8 */
- unsigned char ac_trace_delay[10];
- unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting;
- unsigned char lpddr4_x8_mode;
+ unsigned char ac_trace_delay[12];
//system reserve,do not modify ,take care ,please follow SI
unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL];
//use for lpddr3 /lpddr4 ca pinmux remap
unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL];
- unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function
- //[1],slt test parameter ,use for force delay line offset
- //system reserve,do not modify
- unsigned short tdqs2dq;//dq_bdlr_org;
- unsigned char dram_data_wr_odt_ohm;
- unsigned char bitTimeControl_2d;
+ unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,[1],slt test parameter ,use for force delay line offset
+ //system reserve,do not modify
+ unsigned short dq_bdlr_org;
+ unsigned char rsv_char1[2];
//system reserve,do not modify
/* align8 */
@@ -311,29 +293,14 @@
//system reserve,do not modify
/* align8 */
- //unsigned long rsv_long0[2];
+ unsigned long rsv_long0[2];
/* v1 end */
-// /*
- unsigned char read_dqs_delay[16];
- unsigned char read_dq_bit_delay[72];
- unsigned short write_dqs_delay[16];
-// */
- unsigned short write_dq_bit_delay[72];
- unsigned short read_dqs_gate_delay[16];
- unsigned char soc_bit_vref[32];
- unsigned char dram_bit_vref[32];
- ///*
- unsigned char rever3;//read_dqs read_dq,write_dqs, write_dq
- unsigned char dfi_mrl;
- unsigned char dfi_hwtmrl;
- unsigned char ARdPtrInitVal;
- unsigned char retraining[16];
+ unsigned char dqs_adjust[16]; //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read
+ /* v2 start */
+ unsigned char dq_bit_delay[72];
//override read bit delay
-
- //extra
-// unsigned short dmc_test_worst_window_tx;
-// unsigned short dmc_test_worst_window_rx;
-// */
+// unsigned short dq_bdlr_org[2];
+// unsigned char dqs_adjust_line[16]; //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 write //rank 0 --lane 0 1 2 3 rank 1--4 5 6 7 read
}ddr_set_t;
ddr_set_t p_ddr_set_t;
@@ -372,7 +339,7 @@
if (str[0] == '-')
k = 1;/*Ê®½øÖƸºÊý*/
else
- k = 0;
+ k = 0;
printf("\nitoa_ddr_test 4\n");
for (j = k;j <= (i-1)/2;j++)
{
@@ -407,7 +374,7 @@
}
} while (sc != 0);
}
-
+
}
*/
int TOLOWER(int ch)
@@ -428,7 +395,7 @@
int isdigit(int ch)
{
return (unsigned int)(ch - '0') < 10u;
-}//ÅжÏ×Ö·ûcÊÇ·ñΪÊý×Ö
+}//ÅжÏ×Ö·ûcÊÇ·ñΪÊý×Ö
unsigned int simple_guess_base(const char *cp)
{
if (cp[0] == '0') {
@@ -445,14 +412,14 @@
{
unsigned int result = 0;
//printf("test sizeof(str_buf)==%d\n",1);
- if(cp == NULL) //jiaxing add 20170616
+ if (cp == NULL) //jiaxing add 20170616
return 0;
if (!base)
base = simple_guess_base(cp);
if (base == 16 && cp[0] == '0' && TOLOWER(cp[1]) == 'x')
cp += 2;
if (base == 10) {
- while ((*cp)== '0')
+ while ((*cp)== '0')
cp++;
}
while (isxdigit(*cp)) {//¼ì²éµ±Ç°cpÊÇ·ñÊǸöÊ®Áù½øÖÆÊýÖµ£¬²»ÊÇÖ±½Ó·µ»Ø0
@@ -466,7 +433,7 @@
if (endp)
*endp = (char *)cp;
return result;
-}
+}
unsigned int env_to_a_num(const char *env_name)
{
char *str_buf = NULL;
@@ -474,7 +441,7 @@
str_buf = (char *)(&buf);
memset(str_buf, 0, sizeof(buf));
printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
- str_buf = getenv(env_name);
+ str_buf = env_get(env_name);
unsigned int a_num = 0;
char *endp;
@@ -494,14 +461,14 @@
str_buf = (char *)(&buf);
memset(str_buf, 0, sizeof(buf));
printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
- str_buf = getenv(env_name);
+ str_buf = env_get(env_name);
printf("str==%s\n",str_buf);
sprintf(buf, "0x%08x", *a_num);
printf( "%s==0x%08x", buf,*a_num);
- setenv(env_name, buf);
+ env_set(env_name, buf);
run_command("save",0);
return 1;
@@ -515,7 +482,7 @@
str_buf = (char *)(&buf);
memset(str_buf, 0, sizeof(buf));
printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
- str_buf = getenv(env_name);
+ str_buf = env_get(env_name);
char * str[48];
char *endp;
@@ -526,7 +493,7 @@
for (i = 0; i < 48; i++) {
str[i] = strsep(&str_buf, ";");
//str[i] = strsep(&str_buf, " ");
- if(str[i] == NULL)
+ if (str[i] == NULL)
break;
str_to_numarry[i] = simple_strtoull_ddr(str[i], &endp, 0);
//printf("str_to_numarry[%d]==%d\n",i,str_to_numarry[i]);
@@ -550,7 +517,7 @@
str_buf = (char *)(&buf);
memset(str_buf, 0, sizeof(buf));
printf("sizeof(str_buf)==%d\n",(unsigned int)(sizeof(buf)));
- str_buf = getenv(env_name);
+ str_buf = env_get(env_name);
//char * str[48];
printf("str==%s\n",str_buf);
@@ -564,7 +531,7 @@
}
//sprintf(str, "%lx", value);
printf( "%s", buf);
- setenv(env_name, buf);
+ env_set(env_name, buf);
run_command("save",0);
//num_arry=(unsigned int *)(&str_to_numarry);
@@ -651,7 +618,7 @@
//#define CONFIG_DDR_CMD_BDL_TUNE
//#define CONFIG_CMD_DDR_TEST
-#ifndef CONFIG_CHIP
+#ifndef CONFIG_CHIP
//#define CONFIG_CHIP CHIP_OLD //CHIP_OLD// //#define CHIP_OLD 0 //#define CHIP_TXLX 1
#define CHIP_OLD 0
#define CHIP_TXLX 1
@@ -670,7 +637,7 @@
#if (CONFIG_CHIP>=CHIP_G12)
#define CONFIG_DDR_PHY P_DDR_PHY_G12
-#else
+#else
//#define CONFIG_CHIP CHIP_OLD//
//#define CONFIG_DDR_PHY P_DDR_PHY_905X//P_DDR_PHY_GX_BABY//P_DDR_PHY_905X// P_DDR_PHY_GX_BABY
//#define CONFIG_DDR_PHY P_DDR_PHY_G12//P_DDR_PHY_DEFAULT// P_DDR_PHY_905X//P_DDR_PHY_GX_BABY//P_DDR_PHY_905X// P_DDR_PHY_GX_BABY
@@ -969,7 +936,7 @@
// at the test period, the whole MMC granted data cycles. 64bits unit.
#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
// at the test period, the granted data cycles for the selected channel and ports.
-#endif
+#endif
#elif (CONFIG_DDR_PHY == P_DDR_PHY_DEFAULT)
@@ -1090,7 +1057,7 @@
// at the test period, the whole MMC granted data cycles. 64bits unit.
#define DMC_MON_ONE_GRANT_CNT (DMC_REG_BASE + (0x2a <<2 ))
// at the test period, the granted data cycles for the selected channel and ports.
-#endif
+#endif
#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
#define DDR0_PUB_PIR (DDR0_PUB_REG_BASE+(0x01<<2))
@@ -1930,7 +1897,7 @@
#define PERIPHS_PIN_MUX_12 (0xff634400 + (0x38 << 2))
#define SEC_PERIPHS_PIN_MUX_12 (0xff634400 + (0x38 << 2))
#define P_PERIPHS_PIN_MUX_12 (volatile uint32_t *)(0xff634400 + (0x38 << 2))
-#endif
+#endif
#define P_PIN_MUX_REG1 P_PERIPHS_PIN_MUX_1// (((volatile unsigned *)(0xda834400 + (0x2d << 2))))
#define P_PIN_MUX_REG2 P_PERIPHS_PIN_MUX_2// (((volatile unsigned *)(0xda834400 + (0x2e << 2))))
#define P_PIN_MUX_REG3 P_PERIPHS_PIN_MUX_3//(((volatile unsigned *)(0xda834400 + (0x2f << 2))))
@@ -2021,10 +1988,10 @@
//#endif
}
-#define DDR_PARAMETER_SOURCE_FROM_DMC_STICKY 1
-#define DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV 2
-#define DDR_PARAMETER_SOURCE_FROM_UBOOT_IDME 3
-#define DDR_PARAMETER_SOURCE_FROM_ORG_STICKY 4
+#define DDR_PARAMETER_SOURCE_FROM_DMC_STICKY 1
+#define DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV 2
+#define DDR_PARAMETER_SOURCE_FROM_UBOOT_IDME 3
+#define DDR_PARAMETER_SOURCE_FROM_ORG_STICKY 4
#define DDR_PARAMETER_READ 1
#define DDR_PARAMETER_WRITE 2
@@ -2032,31 +1999,31 @@
#define DDR_PARAMETER_RIGHT 2
typedef struct ddr_test_struct {
- unsigned int ddr_data_source ;
- unsigned int ddr_data_test_size ;
- unsigned int ddr_address_test_size ;
- unsigned int ddr_test_watchdog_times_s ;
- unsigned int ddr_test_lane_disable ;
+ unsigned int ddr_data_source ;
+ unsigned int ddr_data_test_size ;
+ unsigned int ddr_address_test_size ;
+ unsigned int ddr_test_watchdog_times_s ;
+ unsigned int ddr_test_lane_disable ;
- unsigned int ddr_test_window_flag[8] ;
- unsigned int ddr_test_window_data[100] ;
-} ddr_test_struct_t;
-ddr_test_struct_t *g_ddr_test_struct;
+ unsigned int ddr_test_window_flag[8] ;
+ unsigned int ddr_test_window_data[100] ;
+} ddr_test_struct_t;
+ddr_test_struct_t *g_ddr_test_struct;
unsigned int read_write_window_test_parameter(unsigned int source_index, unsigned int parameter_index ,unsigned int parameter_value,unsigned int read_write_flag )
{
- if(source_index == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
+ if (source_index == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
{
sticky_reg_base_add = (DDR0_PUB_REG_BASE&0xffff0000)+((DMC_STICKY_0)&0xffff);
- if(read_write_flag == DDR_PARAMETER_WRITE)
+ if (read_write_flag == DDR_PARAMETER_WRITE)
wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
- if(read_write_flag == DDR_PARAMETER_READ)
+ if (read_write_flag == DDR_PARAMETER_READ)
parameter_value = rd_reg((sticky_reg_base_add+(parameter_index<<2)));
}
- if(source_index == DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV)
+ if (source_index == DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV)
{
char *pre_env_name = "ddr_test_data_num";
char *env_name = "ddr_test_data_num_0000";
@@ -2069,28 +2036,28 @@
sprintf(env_name,"%s_%04d",pre_env_name,parameter_index);
sprintf(buf, "0x%08x", parameter_value);
- if(read_write_flag == DDR_PARAMETER_WRITE)
- {
- setenv(env_name, buf);
+ if (read_write_flag == DDR_PARAMETER_WRITE)
+ {
+ env_set(env_name, buf);
run_command("save",0);
}
- if(read_write_flag == DDR_PARAMETER_READ)
- {
- temp_s = getenv(env_name);
- if(temp_s)
+ if (read_write_flag == DDR_PARAMETER_READ)
+ {
+ temp_s = env_get(env_name);
+ if (temp_s)
parameter_value = simple_strtoull_ddr(temp_s, &endp, 0);
else
parameter_value = 0;
}
}
- if(source_index == DDR_PARAMETER_SOURCE_FROM_ORG_STICKY)
+ if (source_index == DDR_PARAMETER_SOURCE_FROM_ORG_STICKY)
{
sticky_reg_base_add=(PREG_STICKY_REG0);
- if(read_write_flag==DDR_PARAMETER_WRITE)
+ if (read_write_flag == DDR_PARAMETER_WRITE)
wr_reg((sticky_reg_base_add+(parameter_index<<2)), parameter_value);
- if(read_write_flag==DDR_PARAMETER_READ)
+ if (read_write_flag == DDR_PARAMETER_READ)
parameter_value=rd_reg((sticky_reg_base_add+(parameter_index<<2)));
}
return parameter_value;
@@ -2135,13 +2102,13 @@
if (read_write_flag == DDR_PARAMETER_WRITE)
{
- setenv(env_name, buf);
+ env_set(env_name, buf);
run_command("save",0);
}
- if(read_write_flag == DDR_PARAMETER_READ)
- {
- temp_s = getenv(env_name);
- if(temp_s)
+ if (read_write_flag == DDR_PARAMETER_READ)
+ {
+ temp_s = env_get(env_name);
+ if (temp_s)
parameter_value = simple_strtoull_ddr(temp_s, &endp, 0);
else
parameter_value = 0;
@@ -2191,7 +2158,7 @@
// set timeout
//*P_WATCHDOG_TCNT = msec;
// writel(msec,(unsigned int )P_WATCHDOG_CNTL); //bit0-15
- if(sec*100>0xffff)
+ if (sec*100>0xffff)
*P_WATCHDOG_TCNT=0xffff;
else
*P_WATCHDOG_TCNT=sec*100; //max 655s
@@ -2306,7 +2273,7 @@
//WRITE_CBUS_REG(WATCHDOG_TC, 0xf080000 | 2000);
*P_WATCHDOG_CNTL=(0xf080000 | 2000);
#endif
- while(1);
+ while (1) ;
}
@@ -2321,7 +2288,7 @@
// goto DDR_TUNE_DQS_START;
int i = 0;
printf("\nargc== 0x%08x\n", argc);
- for(i = 0; i<argc; i++)
+ for (i = 0; i<argc; i++)
{
printf("\nargv[%d]=%s\n",i,argv[i]);
}
@@ -2366,23 +2333,23 @@
100 ,
100 ,
};
- if(argc == 1)
+ if (argc == 1)
printf("\nplease read help\n");
- if(argc >= 2)
+ if (argc >= 2)
{
wr_rd_adj_input_src = simple_strtoull_ddr(argv[1], &endp, 10);
- unsigned int i=0;
- if(wr_rd_adj_input_src==WR_RD_ADJ_USE_UART_INPUT)
+ unsigned int i=0;
+ if (wr_rd_adj_input_src == WR_RD_ADJ_USE_UART_INPUT)
{
printf("\ntune ddr lcdlr use uart input\n");
if (argc>24+2)
argc=24+2;
- for(i = 2;i<argc;i++)
+ for (i = 2;i<argc;i++)
{
- if(i<(2+12))
+ if (i<(2+12))
wr_adj_per[i-2]=simple_strtoull_ddr(argv[i], &endp, 10);
else
rd_adj_per[i-14]=simple_strtoull_ddr(argv[i], &endp, 10);
@@ -2390,7 +2357,7 @@
}
// unsigned int = 0, max = 0xff, min = 0x00;
- if(wr_rd_adj_input_src==WR_RD_ADJ_USE_ENV)
+ if (wr_rd_adj_input_src == WR_RD_ADJ_USE_ENV)
{
printf("\ntune ddr lcdlr use uboot env\n");
//char str[24];
@@ -2400,7 +2367,7 @@
int value=0;
//*varname="env_ddrtest";
- s = getenv("env_wr_lcdlr_pr");
+ s = env_get("env_wr_lcdlr_pr");
if (s)
{//i=0;
//while(s_temp)
@@ -2413,7 +2380,7 @@
value = simple_strtoull_ddr(s, &endp, 16);
printf("%d",value);
}
- s = getenv("env_rd_lcdlr_pr");
+ s = env_get("env_rd_lcdlr_pr");
if (s)
{//i=0;
@@ -2427,25 +2394,25 @@
}
//sprintf(str, "%lx", value);
- // setenv("env_ddrtest", str);
+ // env_set("env_ddrtest", str);
//run_command("save",0);
if (argc>24+2)
argc=24+2;
- for(i = 2;i<argc;i++)
+ for (i = 2;i<argc;i++)
{
- if(i<(2+12))
+ if (i<(2+12))
wr_adj_per[i-2]=simple_strtoull_ddr(argv[i], &endp, 16);
else
rd_adj_per[i-14]=simple_strtoull_ddr(argv[i], &endp, 16);
}
}
printf(" int wr_adj_per[12]={\n");
- for(i = 0;i<12;i++)
+ for (i = 0;i<12;i++)
printf("%04d ,\n",wr_adj_per[i]);
printf("};\n");
printf(" int rd_adj_per[12]={\n");
- for(i = 0;i<12;i++)
+ for (i = 0;i<12;i++)
printf("%04d ,\n",rd_adj_per[i]);
printf("};\n");
@@ -2464,17 +2431,17 @@
int lcdlr_w=0,lcdlr_r=0;
unsigned temp_reg=0;
int temp_count=0;
- for( temp_count=0;temp_count<2;temp_count++)
+ for ( temp_count=0;temp_count<2;temp_count++)
{ temp_reg=(unsigned)(DDR0_PUB_ACLCDLR+(temp_count<<2));
lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&ACLCDLR_MAX);
lcdlr_w=lcdlr_w?lcdlr_w:1;
lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
- if(temp_count==1)
+ if (temp_count == 1)
lcdlr_w=lcdlr_w&ACBDLR_MAX;
wr_reg(((uint64_t)(temp_reg)),((lcdlr_w)&ACLCDLR_MAX));
}
#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
- for( temp_count=2;temp_count<6;temp_count++)
+ for ( temp_count=2;temp_count<6;temp_count++)
{ temp_reg=(unsigned)(DDR0_PUB_DX0LCDLR1+(DDR0_PUB_DX1LCDLR1-DDR0_PUB_DX0LCDLR1)*(temp_count-2));
lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&DQLCDLR_MAX);
lcdlr_w=lcdlr_w?lcdlr_w:1;
@@ -2498,18 +2465,18 @@
wr_reg(((uint64_t)(temp_reg)),(((lcdlr_r<<16)|(lcdlr_r<<8)|(lcdlr_w))));
}
#endif
- for( temp_count=6;temp_count<8;temp_count++) {
+ for ( temp_count=6;temp_count<8;temp_count++) {
temp_reg=(unsigned)(DDR1_PUB_ACLCDLR+((temp_count-6)<<2));
lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&ACLCDLR_MAX);
lcdlr_w=lcdlr_w?lcdlr_w:1;
lcdlr_w=(lcdlr_w*(wr_adj_per[temp_count]))/100;
- if(temp_count==7)
+ if (temp_count == 7)
lcdlr_w=lcdlr_w&ACBDLR_MAX;
wr_reg(((uint64_t)(temp_reg)),((lcdlr_w)&ACLCDLR_MAX));
}
#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
- for( temp_count=8;temp_count<12;temp_count++) {
+ for ( temp_count=8;temp_count<12;temp_count++) {
temp_reg=(unsigned)(DDR1_PUB_DX0LCDLR1+(DDR1_PUB_DX1LCDLR1-DDR1_PUB_DX0LCDLR1)*(temp_count-2));
lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&DQLCDLR_MAX);
lcdlr_w=lcdlr_w?lcdlr_w:1;
@@ -2522,7 +2489,7 @@
wr_reg(((uint64_t)(temp_reg+DDR1_PUB_DX0LCDLR4-DDR1_PUB_DX0LCDLR1)),(lcdlr_r));
}
#else
- for( temp_count=8;temp_count<12;temp_count++) {
+ for ( temp_count=8;temp_count<12;temp_count++) {
temp_reg=(unsigned)(DDR1_PUB_DX0LCDLR1+(DDR1_PUB_DX1LCDLR1-DDR1_PUB_DX0LCDLR1)*(temp_count-8));
lcdlr_w=(int)((rd_reg((uint64_t)(temp_reg)))&0xff);
lcdlr_w=lcdlr_w?lcdlr_w:1;
@@ -2532,7 +2499,7 @@
lcdlr_r=(lcdlr_r*(rd_adj_per[temp_count]))/100;
wr_reg(((uint64_t)(temp_reg)),(((lcdlr_r<<16)|(lcdlr_r<<8)|(lcdlr_w))));
}
-#endif
+#endif
#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
wr_reg(DDR0_PUB_PGCR6, (rd_reg(DDR0_PUB_PGCR6))&(~(1<<0)));
@@ -2558,7 +2525,7 @@
U_BOOT_CMD(
ddr_test_tune_dqs_env, 30, 1, do_ddr_fine_tune_lcdlr_env1,
"do_ddr_fine_tune_lcdlr_env arg1 arg2 arg3...",
- "do_ddr_fine_tune_lcdlr_env arg1 arg2 arg3... \n dcache off ? \n"
+ "do_ddr_fine_tune_lcdlr_env arg1 arg2 arg3... \n dcache off ? \n"
);
#endif
@@ -2994,7 +2961,7 @@
}
if ((*(p+i)) !=(start_pattern+pattern_offset*i))
{error_count++;
- printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i),
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p+i), p_convter_int(p + i),
(start_pattern+pattern_offset*i));
}
break;
@@ -7379,14 +7346,14 @@
unsigned int lcdlr_temp_count=0;
env_lcdlr_temp_count="lcdlr_temp_count";
- if(test_temp_value_use_sticky_register)
+ if (test_temp_value_use_sticky_register)
{
lcdlr_temp_count=readl((sticky_reg_base_add+(6<<2)));
}
else
{
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
+ temp_s= env_get(env_lcdlr_temp_count);
+ if (temp_s)
{
lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
}
@@ -7395,7 +7362,7 @@
lcdlr_temp_count=0;
}
}
-
+
//if ( channel_a_en)
{
//writel((0), 0xc8836c00);
@@ -7429,7 +7396,7 @@
printf("\nshould pause ddl pir== 0x%08x,if no pause ddl ,write lcdlr some time may occour error\n", readl(DDR0_PUB_REG_BASE+4));
writel((readl(DDR0_PUB_REG_BASE+4))|(1<<29),(DDR0_PUB_REG_BASE+4));
printf("\n pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
- if( channel_b_en)
+ if ( channel_b_en)
{
printf("\nddr1 should pause ddl pir== 0x%08x,if no pause ddl ,write lcdlr some time may occour error\n", readl(DDR1_PUB_REG_BASE+4));
writel((readl(DDR1_PUB_REG_BASE+4))|(1<<29),(DDR1_PUB_REG_BASE+4));
@@ -7460,7 +7427,7 @@
}
#endif
- if ((test_min_max_flag == 0)||( (test_min_max_flag == 2)))
+ if ((test_min_max_flag == 0) || ( (test_min_max_flag == 2)))
{
while (dq_lcd_bdl_temp_reg_value>0)
{
@@ -7472,13 +7439,13 @@
lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s\n", buf);
- if(test_temp_value_use_sticky_register)
+ if (test_temp_value_use_sticky_register)
{
writel(lcdlr_temp_count,(sticky_reg_base_add+(6<<2)));
}
else
{
- setenv(env_lcdlr_temp_count, buf);
+ env_set(env_lcdlr_temp_count, buf);
run_command("save",0);
}
}
@@ -7518,7 +7485,7 @@
{
dq_lcd_bdl_reg_left_min=dq_lcd_bdl_reg_left ;
}
- }
+ }
else
{
printf("\n left edge skip \n");
@@ -7560,13 +7527,13 @@
lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s\n", buf);
- if(test_temp_value_use_sticky_register)
+ if (test_temp_value_use_sticky_register)
{
writel(lcdlr_temp_count,(sticky_reg_base_add+(6<<2)));
}
else
{
- setenv(env_lcdlr_temp_count, buf);
+ env_set(env_lcdlr_temp_count, buf);
run_command("save",0);
}
@@ -7638,7 +7605,7 @@
dq_lcd_bdl_temp_reg_value=(dq_lcd_bdl_reg_right_min<<16)|dq_lcd_bdl_reg_left_min;
if (!test_lane_step_rdqs_flag)
{
- if(channel_a_en)
+ if (channel_a_en)
{
dq_lcd_bdl_value_wdq_org_a[testing_lane]=dq_lcd_bdl_reg_org;
if (test_min_max_flag != 1)
@@ -8432,14 +8399,14 @@
unsigned int lcdlr_temp_count=0;
env_lcdlr_temp_count="lcdlr_temp_count";
- if(test_temp_value_use_sticky_register)
+ if (test_temp_value_use_sticky_register)
{lcdlr_temp_count=readl((sticky_reg_base_add+(6<<2)));
}
else
{
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
+ temp_s= env_get(env_lcdlr_temp_count);
+ if (temp_s)
{
lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
}
@@ -8498,7 +8465,7 @@
printf("\nshould pause ddl pir== 0x%08x,if no pause ddl ,write lcdlr some time may occour error\n", readl(DDR0_PUB_REG_BASE+4));
writel((readl(DDR0_PUB_REG_BASE+4))|(1<<29),(DDR0_PUB_REG_BASE+4));
printf("\n pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
- if( channel_b_en)
+ if ( channel_b_en)
{ printf("\nddr1 should pause ddl pir== 0x%08x,if no pause ddl ,write lcdlr some time may occour error\n", readl(DDR1_PUB_REG_BASE+4));
writel((readl(DDR1_PUB_REG_BASE+4))|(1<<29),(DDR1_PUB_REG_BASE+4));
printf("\n ddr1 pause ddl pir== 0x%08x\n", readl(DDR1_PUB_REG_BASE+4));
@@ -8537,7 +8504,7 @@
}
#endif
- if ((test_min_max_flag == 0)||( (test_min_max_flag == 2)))
+ if ((test_min_max_flag == 0) || ( (test_min_max_flag == 2)))
{
while (dq_lcd_bdl_temp_reg_value>0)
{
@@ -8549,13 +8516,13 @@
lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s\n", buf);
- if(test_temp_value_use_sticky_register)
+ if (test_temp_value_use_sticky_register)
{
writel(lcdlr_temp_count,(sticky_reg_base_add+(6<<2)));
}
else
{
- setenv(env_lcdlr_temp_count, buf);
+ env_set(env_lcdlr_temp_count, buf);
run_command("save",0);
}
}
@@ -8645,13 +8612,13 @@
lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s\n", buf);
- if(test_temp_value_use_sticky_register)
+ if (test_temp_value_use_sticky_register)
{
writel(lcdlr_temp_count,(sticky_reg_base_add+(6<<2)));
}
else
{
- setenv(env_lcdlr_temp_count, buf);
+ env_set(env_lcdlr_temp_count, buf);
run_command("save",0);
}
}
@@ -8923,14 +8890,14 @@
unsigned int lcdlr_temp_count=0;
env_lcdlr_temp_count="lcdlr_temp_count_a";
unsigned int lcdlr_max=0;
- if(test_temp_value_use_sticky_register)
+ if (test_temp_value_use_sticky_register)
{lcdlr_temp_count=readl((sticky_reg_base_add+(6<<2)));
}
else
{
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
+ temp_s= env_get(env_lcdlr_temp_count);
+ if (temp_s)
{
lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
}
@@ -8989,7 +8956,7 @@
printf("\nshould pause ddl pir== 0x%08x,if no pause ddl ,write lcdlr some time may occour error\n", readl(DDR0_PUB_REG_BASE+4));
writel((readl(DDR0_PUB_REG_BASE+4))|(1<<29),(DDR0_PUB_REG_BASE+4));
printf("\n pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
- if( channel_b_en)
+ if ( channel_b_en)
{ printf("\nddr1 should pause ddl pir== 0x%08x,if no pause ddl ,write lcdlr some time may occour error\n", readl(DDR1_PUB_REG_BASE+4));
writel((readl(DDR1_PUB_REG_BASE+4))|(1<<29),(DDR1_PUB_REG_BASE+4));
printf("\n ddr1 pause ddl pir== 0x%08x\n", readl(DDR1_PUB_REG_BASE+4));
@@ -8997,11 +8964,11 @@
if (test_lane_step>2)
test_lane_step=0;
printf("\ntest_lane_step==0x%08x\n ",test_lane_step);
- if(test_lane_step==0)
+ if (test_lane_step == 0)
{reg_add=DDR0_PUB_ACLCDLR+reg_base_adj;
lcdlr_max=ACLCDLR_MAX;
}
- if(test_lane_step==1)
+ if (test_lane_step == 1)
{reg_add=DDR0_PUB_ACBDLR0+reg_base_adj;
lcdlr_max=ACBDLR_MAX;
}
@@ -9011,17 +8978,17 @@
dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
printf("\nreg_add_0x%08x==0x%08x\n ",reg_add,dq_lcd_bdl_temp_reg_value);
- if(test_lane_step==0)
+ if (test_lane_step == 0)
{dq_lcd_bdl_temp_reg_value=(((readl(reg_add))&ACLCDLR_MAX));
dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
}
- if(test_lane_step==1)
+ if (test_lane_step == 1)
{dq_lcd_bdl_temp_reg_value=(((readl(reg_add))&ACBDLR_MAX));
dq_lcd_bdl_reg_org=dq_lcd_bdl_temp_reg_value;
}
- if ((test_min_max_flag == 0)||( (test_min_max_flag == 2)))
+ if ((test_min_max_flag == 0) || ( (test_min_max_flag == 2)))
{
while (dq_lcd_bdl_temp_reg_value>0)
{
@@ -9033,13 +9000,13 @@
lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s\n", buf);
- if(test_temp_value_use_sticky_register)
+ if (test_temp_value_use_sticky_register)
{
writel(lcdlr_temp_count,(sticky_reg_base_add+(6<<2)));
}
else
{
- setenv(env_lcdlr_temp_count, buf);
+ env_set(env_lcdlr_temp_count, buf);
run_command("save",0);
}
@@ -9111,13 +9078,13 @@
lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s\n", buf);
- if(test_temp_value_use_sticky_register)
+ if (test_temp_value_use_sticky_register)
{
writel(lcdlr_temp_count,(sticky_reg_base_add+(6<<2)));
}
else
{
- setenv(env_lcdlr_temp_count, buf);
+ env_set(env_lcdlr_temp_count, buf);
run_command("save",0);
}
}
@@ -9169,7 +9136,7 @@
dq_lcd_bdl_temp_reg_value=(dq_lcd_bdl_reg_right_min<<16)|dq_lcd_bdl_reg_left_min;
{if(channel_a_en){
- if(test_lane_step==0)
+ if (test_lane_step == 0)
{
dq_lcd_bdl_value_aclcdlr_org_a=dq_lcd_bdl_reg_org;
if (test_min_max_flag != 1)
@@ -9177,7 +9144,7 @@
if (test_min_max_flag != 2)
dq_lcd_bdl_value_aclcdlr_max_a=dq_lcd_bdl_reg_right_min;
}
- if(test_lane_step==1)
+ if (test_lane_step == 1)
{
dq_lcd_bdl_value_bdlr0_org_a=dq_lcd_bdl_reg_org;
if (test_min_max_flag != 1)
@@ -9188,7 +9155,7 @@
}
if (channel_b_en)
{
- if(test_lane_step==0)
+ if (test_lane_step == 0)
{
dq_lcd_bdl_value_aclcdlr_org_b=dq_lcd_bdl_reg_org;
if (test_min_max_flag != 1)
@@ -9196,7 +9163,7 @@
if (test_min_max_flag != 2)
dq_lcd_bdl_value_aclcdlr_max_b=dq_lcd_bdl_reg_right_min;
}
- if(test_lane_step==1)
+ if (test_lane_step == 1)
{
dq_lcd_bdl_value_bdlr0_org_b=dq_lcd_bdl_reg_org;
if (test_min_max_flag != 1)
@@ -9281,7 +9248,7 @@
//argv2[2]=argv[3];
//#include <stdio.h>
// unsigned int wr_adj_per[24] ;
- if(1)
+ if (1)
{
printf("\ntest use uboot env\n");
{
@@ -9297,7 +9264,7 @@
// int value=0;
///varname="env_ddrtest";
- s = getenv("env_wr_lcdlr_pr");
+ s = env_get("env_wr_lcdlr_pr");
if (s)
{//i=0;
//while(s_temp)
@@ -9313,18 +9280,18 @@
//sscanf(s,"d%,",wr_adj_per);
//sprintf(str,"d%",s);
//getc
- // if (strlen(s) > 16)
+ // if (strlen(s) > 16)
{
// sscanf(s, "%08x, %08x, %08x, \n",
// &wr_adj_per[0], &wr_adj_per[1], &wr_adj_per[2]);
- }
+ }
}
}
}
}
// unsigned int = 0, max = 0xff, min = 0x00;
/*
- if(0)
+ if (0)
{
{printf("\ntest use uboot env\n");
{
@@ -9335,7 +9302,7 @@
int value=0;
///varname="env_ddrtest";
- s = getenv("env_wr_lcdlr_pr");
+ s = env_get("env_wr_lcdlr_pr");
if (s)
{//i=0;
//while(s_temp)
@@ -9356,7 +9323,7 @@
value = simple_strtoull_ddr(s, &endp, 16);
printf("%d",value);
}
- s = getenv("env_rd_lcdlr_pr");
+ s = env_get("env_rd_lcdlr_pr");
if (s)
{//i=0;
@@ -9370,7 +9337,7 @@
}
//sprintf(str, "%lx", value);
- // setenv("env_ddrtest", str);
+ // env_set("env_ddrtest", str);
//run_command("save",0);
@@ -9378,9 +9345,9 @@
if (argc>24+2)
argc=24+2;
- for(i = 2;i<argc;i++)
+ for (i = 2;i<argc;i++)
{
- if(i<(2+12)){
+ if (i<(2+12)) {
wr_adj_per[i-2]=simple_strtoull_ddr(argv[i], &endp, 16);
}
else
@@ -9392,13 +9359,13 @@
}
printf(" int wr_adj_per[12]={\n");
- for(i = 0;i<12;i++)
+ for (i = 0;i<12;i++)
{
printf("%04d ,\n",wr_adj_per[i]);
}
printf("};\n");
printf(" int rd_adj_per[12]={\n");
-for(i = 0;i<12;i++)
+for (i = 0;i<12;i++)
{
printf("%04d ,\n",rd_adj_per[i]);
}
@@ -9796,7 +9763,7 @@
while (dq_lcd_bdl_temp_reg_value_wdqd>0)
{
- if(test_min_max)
+ if (test_min_max)
{break;
}
temp_test_error=0;
@@ -10208,10 +10175,10 @@
unsigned int *num_arry_lane1=NULL;
unsigned int *num_arry_lane2=NULL;
unsigned int *num_arry_lane3=NULL;
- char *name_lane0;
- char *name_lane1;
- char *name_lane2;
- char *name_lane3;
+ char *name_lane0;
+ char *name_lane1;
+ char *name_lane2;
+ char *name_lane3;
num_arry = (unsigned int *)(&str_to_numarry);
int i;
char *varname; char *env_lcdlr_temp_count;
@@ -10225,14 +10192,14 @@
name_lane2="ddr_test_data_lane2";
name_lane3="ddr_test_data_lane3";
env_lcdlr_temp_count="lcdlr_temp_count";
- s = getenv(varname);
+ s = env_get(varname);
if (s)
{//i=0;
//while(s_temp)
{
env_to_num(varname,num_arry);//unsigned int *num_arry
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
+ temp_s= env_get(env_lcdlr_temp_count);
+ if (temp_s)
{
lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
}
@@ -10240,7 +10207,7 @@
{lcdlr_temp_count=0;
}
- if(0){
+ if (0) {
env_to_num(name_lane0,num_arry_lane0);//unsigned int *num_arry
env_to_num(name_lane1,num_arry_lane1);//unsigned int *num_arry
env_to_num(name_lane2,num_arry_lane2);//unsigned int *num_arry
@@ -10252,7 +10219,7 @@
printf("str_to_numarry[%d]==%d\n",i,num_arry[i]);
}
//for (lane_step = 0;lane_step< 4;lane_step++)
- if(0)
+ if (0)
{
for (i = 0; i < 8; i++) {
@@ -10275,18 +10242,18 @@
//sscanf(s,"d%,",wr_adj_per);
//sprintf(str,"d%",s);
//getc
- // if (strlen(s) > 16)
+ // if (strlen(s) > 16)
{
// sscanf(s, "%08x, %08x, %08x, \n",
// &wr_adj_per[0], &wr_adj_per[1], &wr_adj_per[2]);
- }
+ }
}
}
else
{
printf("no env set,exit\n");
return 0;}
- s = getenv(varname);//for debug display env should add
+ s = env_get(varname);//for debug display env should add
///*
@@ -10312,18 +10279,18 @@
printf("test_arg_3_freq==%d\n",test_arg_3_freq);
printf("test_arg_4_step_status==%d\n",test_arg_4_step_status);
- if(test_arg_2_step)
+ if (test_arg_2_step)
{
- if(test_arg_3_freq!=global_ddr_clk)
+ if (test_arg_3_freq != global_ddr_clk)
{
printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n",global_ddr_clk,test_arg_3_freq);
sprintf(str,"d2pll %d",test_arg_3_freq);
printf("\nstr=%s\n",str);
run_command(str,0);
- while(1);
+ while (1) ;
}
}
- if(test_arg_2_step==0)
+ if (test_arg_2_step == 0)
{
{
test_arg_0_cmd0=0x22;
@@ -10414,39 +10381,39 @@
printf("DDR0_PUB_DX1GCR0==%x\n",(readl(DDR0_PUB_DX1GCR0)));
printf("DDR0_PUB_DX2GCR0==%x\n",(readl(DDR0_PUB_DX2GCR0)));
printf("DDR0_PUB_DX3GCR0==%x\n",(readl(DDR0_PUB_DX3GCR0)));
- if(((readl(DDR0_PUB_DX0GCR0))&1)==0)
- lane_disable= lane_disable|1;
- if(((readl(DDR0_PUB_DX1GCR0))&1)==0)
- lane_disable= lane_disable|(1<<1);
- if(((readl(DDR0_PUB_DX2GCR0))&1)==0)
- lane_disable= lane_disable|(1<<2);
- if(((readl(DDR0_PUB_DX3GCR0))&1)==0)
- lane_disable= lane_disable|(1<<3);
+ if (((readl(DDR0_PUB_DX0GCR0))&1) == 0)
+ lane_disable= lane_disable|1;
+ if (((readl(DDR0_PUB_DX1GCR0))&1) == 0)
+ lane_disable= lane_disable|(1<<1);
+ if (((readl(DDR0_PUB_DX2GCR0))&1) == 0)
+ lane_disable= lane_disable|(1<<2);
+ if (((readl(DDR0_PUB_DX3GCR0))&1) == 0)
+ lane_disable= lane_disable|(1<<3);
#endif
- if(lane_disable)
+ if (lane_disable)
{if(lane_disable&0x1){
dq_lcd_bdl_value_wdq_status_a[0]=4;
dq_lcd_bdl_value_rdqs_status_a[0]=4;
}
- if(lane_disable&0x2){
+ if (lane_disable&0x2) {
dq_lcd_bdl_value_wdq_status_a[1]=4;
dq_lcd_bdl_value_rdqs_status_a[1]=4;
}
- if(lane_disable&0x4){
+ if (lane_disable&0x4) {
dq_lcd_bdl_value_wdq_status_a[2]=4;
dq_lcd_bdl_value_rdqs_status_a[2]=4;
}
- if(lane_disable&0x8){
+ if (lane_disable&0x8) {
dq_lcd_bdl_value_wdq_status_a[3]=4;
dq_lcd_bdl_value_rdqs_status_a[3]=4;
}
printf("lane_disable==%x\n",lane_disable);
- if(lane_disable&0x10){
+ if (lane_disable&0x10) {
dq_lcd_bdl_value_aclcdlr_status_a=4;
printf("dq_lcd_bdl_value_aclcdlr_status_a==%x\n",dq_lcd_bdl_value_aclcdlr_status_a);
}
- if(lane_disable&0x20){
+ if (lane_disable&0x20) {
dq_lcd_bdl_value_bdlr0_status_a=4;
printf("dq_lcd_bdl_value_bdlr0_status_a==%x\n",dq_lcd_bdl_value_bdlr0_status_a);
@@ -10484,7 +10451,7 @@
}
}
- if(0){
+ if (0) {
for (i = 0; i < 8; i++) {
num_arry_lane0[i]=num_arry[8+i];
}
@@ -10512,7 +10479,7 @@
for (i = 0; i < 48; i++) {
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
@@ -10532,20 +10499,20 @@
}
//sprintf(str, "%lx", value);
printf("%s", str);
- setenv(varname, str);
+ env_set(varname, str);
run_command("save",0);
i=2;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
for (i = 8; i < 48; i++) {
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
- temp_s1= getenv(str_temp1);
- if(temp_s1)
+ temp_s1= env_get(str_temp1);
+ if (temp_s1)
{
num_arry[i]= simple_strtoull_ddr(temp_s1, &endp, 0);
}
@@ -10607,16 +10574,16 @@
lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s", buf);
- setenv(env_lcdlr_temp_count, buf);
+ env_set(env_lcdlr_temp_count, buf);
run_command("save",0);
}
*/
- if((dq_lcd_bdl_value_wdq_status_a[lane_step]==0xffff)
+ if ((dq_lcd_bdl_value_wdq_status_a[lane_step] == 0xffff)
||(dq_lcd_bdl_value_wdq_status_a[lane_step]==0)
||(dq_lcd_bdl_value_wdq_status_a[lane_step]==1)
)
{
- if((dq_lcd_bdl_value_wdq_status_a[lane_step]==0xffff)
+ if ((dq_lcd_bdl_value_wdq_status_a[lane_step] == 0xffff)
||(dq_lcd_bdl_value_wdq_status_a[lane_step]==0))
{ dq_lcd_bdl_value_wdq_status_a[lane_step]=1;
{
@@ -10625,13 +10592,13 @@
i=8+lane_step*8+3;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
lcdlr_temp_count=0;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s", buf);
- setenv(env_lcdlr_temp_count, buf);
+ env_set(env_lcdlr_temp_count, buf);
run_command("save",0);
}
@@ -10648,8 +10615,8 @@
}
else if (dq_lcd_bdl_value_wdq_status_a[lane_step]==1)
{
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
+ temp_s= env_get(env_lcdlr_temp_count);
+ if (temp_s)
{
lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
}
@@ -10668,12 +10635,12 @@
i=8+lane_step*8+1;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
i=8+lane_step*8+3;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
@@ -10681,7 +10648,7 @@
run_command("reset",0);
}
- if((dq_lcd_bdl_value_wdq_status_a[lane_step]==2)||
+ if ((dq_lcd_bdl_value_wdq_status_a[lane_step] == 2) ||
(dq_lcd_bdl_value_wdq_status_a[lane_step]==3))
{
// if((dq_lcd_bdl_value_wdq_min_a[lane_step])==0xffff)
@@ -10691,21 +10658,21 @@
// }
{
- if(dq_lcd_bdl_value_wdq_status_a[lane_step]==2)
+ if (dq_lcd_bdl_value_wdq_status_a[lane_step] == 2)
{ dq_lcd_bdl_value_wdq_status_a[lane_step]=3;
{
num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_wdq_status_a[lane_step];
i=8+lane_step*8+3;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
{
lcdlr_temp_count=0;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s", buf);
- setenv(env_lcdlr_temp_count, buf);
+ env_set(env_lcdlr_temp_count, buf);
run_command("save",0);
}
@@ -10722,8 +10689,8 @@
}
else if (dq_lcd_bdl_value_wdq_status_a[lane_step]==3)
{
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
+ temp_s= env_get(env_lcdlr_temp_count);
+ if (temp_s)
{
lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
}
@@ -10741,12 +10708,12 @@
i=8+lane_step*8+2;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
i=8+lane_step*8+3;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
@@ -10756,12 +10723,12 @@
}
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==0xffff)
+ if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 0xffff)
||(dq_lcd_bdl_value_rdqs_status_a[lane_step]==0)
||(dq_lcd_bdl_value_rdqs_status_a[lane_step]==1)
)
{
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==0xffff)
+ if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 0xffff)
||(dq_lcd_bdl_value_rdqs_status_a[lane_step]==0))
{ dq_lcd_bdl_value_rdqs_status_a[lane_step]=1;
{
@@ -10769,14 +10736,14 @@
i=8+lane_step*8+7;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
{
lcdlr_temp_count=0;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s", buf);
- setenv(env_lcdlr_temp_count, buf);
+ env_set(env_lcdlr_temp_count, buf);
run_command("save",0);
}
@@ -10793,8 +10760,8 @@
}
else if (dq_lcd_bdl_value_rdqs_status_a[lane_step]==1)
{
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
+ temp_s= env_get(env_lcdlr_temp_count);
+ if (temp_s)
{
lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
}
@@ -10812,25 +10779,25 @@
i=8+lane_step*8+5;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
i=8+lane_step*8+7;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
run_command("reset",0);
}
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==2)||
+ if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 2) ||
(dq_lcd_bdl_value_rdqs_status_a[lane_step]==3))
{
{
- if(dq_lcd_bdl_value_rdqs_status_a[lane_step]==2)
- {
+ if (dq_lcd_bdl_value_rdqs_status_a[lane_step] == 2)
+ {
dq_lcd_bdl_value_rdqs_status_a[lane_step]=3;
{
@@ -10838,7 +10805,7 @@
i=8+lane_step*8+7;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
@@ -10846,7 +10813,7 @@
lcdlr_temp_count=0;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s", buf);
- setenv(env_lcdlr_temp_count, buf);
+ env_set(env_lcdlr_temp_count, buf);
run_command("save",0);
}
@@ -10863,8 +10830,8 @@
}
else if (dq_lcd_bdl_value_rdqs_status_a[lane_step]==3)
{
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
+ temp_s= env_get(env_lcdlr_temp_count);
+ if (temp_s)
{
lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
}
@@ -10883,12 +10850,12 @@
i=8+lane_step*8+6;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
i=8+lane_step*8+7;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
run_command("reset",0);
@@ -10897,7 +10864,7 @@
}
/*
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==0xffff)||
+ if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 0xffff) ||
(dq_lcd_bdl_value_rdqs_status_a[lane_step]==0))
{dq_lcd_bdl_value_rdqs_status_a[lane_step]=0;
sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),2);
@@ -10916,7 +10883,7 @@
run_command("reset",0);
}
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==1)||
+ if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 1) ||
(dq_lcd_bdl_value_rdqs_status_a[lane_step]==2))
{dq_lcd_bdl_value_rdqs_status_a[lane_step]=2;
sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),1);
@@ -10934,7 +10901,7 @@
num_to_env(varname,num_arry);
run_command("reset",0);
}
- */
+ */
ddr_test_watchdog_disable(); //s
@@ -10961,12 +10928,12 @@
printf("\ndq_lcd_bdl_value_aclcdlr_status_a %d \n",dq_lcd_bdl_value_aclcdlr_status_a);
lane_step=4;
env_lcdlr_temp_count="lcdlr_temp_count_a";
- if((dq_lcd_bdl_value_aclcdlr_status_a>=0xffff)
+ if ((dq_lcd_bdl_value_aclcdlr_status_a >= 0xffff)
||(dq_lcd_bdl_value_aclcdlr_status_a==0)
||(dq_lcd_bdl_value_aclcdlr_status_a==1)
)
{
- if((dq_lcd_bdl_value_aclcdlr_status_a>=0xffff)
+ if ((dq_lcd_bdl_value_aclcdlr_status_a >= 0xffff)
||(dq_lcd_bdl_value_aclcdlr_status_a==0))
{ dq_lcd_bdl_value_aclcdlr_status_a=1;
{
@@ -10976,14 +10943,14 @@
printf("aclcdlr_status_a==0x%08x\n",num_arry[i]);
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
printf("\n222test lcdlr ac bdlr window lane a...\n");
lcdlr_temp_count=0;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s", buf);
- setenv(env_lcdlr_temp_count, buf);
+ env_set(env_lcdlr_temp_count, buf);
run_command("save",0);
}
@@ -11003,8 +10970,8 @@
}
else if (dq_lcd_bdl_value_aclcdlr_status_a==1)
{
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
+ temp_s= env_get(env_lcdlr_temp_count);
+ if (temp_s)
{
lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
}
@@ -11023,12 +10990,12 @@
i=8+lane_step*8+1;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
i=8+lane_step*8+3;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
@@ -11036,7 +11003,7 @@
run_command("reset",0);
}
- if((dq_lcd_bdl_value_aclcdlr_status_a==2)||
+ if ((dq_lcd_bdl_value_aclcdlr_status_a == 2) ||
(dq_lcd_bdl_value_aclcdlr_status_a==3))
{
// if((dq_lcd_bdl_value_wdq_min_a[lane_step])==0xffff)
@@ -11046,21 +11013,21 @@
// }
{
- if(dq_lcd_bdl_value_aclcdlr_status_a==2)
+ if (dq_lcd_bdl_value_aclcdlr_status_a == 2)
{ dq_lcd_bdl_value_aclcdlr_status_a=3;
{
num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_aclcdlr_status_a;
i=8+lane_step*8+3;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
{
lcdlr_temp_count=0;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s", buf);
- setenv(env_lcdlr_temp_count, buf);
+ env_set(env_lcdlr_temp_count, buf);
run_command("save",0);
}
@@ -11077,8 +11044,8 @@
}
else if (dq_lcd_bdl_value_aclcdlr_status_a==3)
{
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
+ temp_s= env_get(env_lcdlr_temp_count);
+ if (temp_s)
{
lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
}
@@ -11096,12 +11063,12 @@
i=8+lane_step*8+2;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
i=8+lane_step*8+3;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
@@ -11111,12 +11078,12 @@
}
- if((dq_lcd_bdl_value_bdlr0_status_a==0xffff)
+ if ((dq_lcd_bdl_value_bdlr0_status_a == 0xffff)
||(dq_lcd_bdl_value_bdlr0_status_a==0)
||(dq_lcd_bdl_value_bdlr0_status_a==1)
)
{
- if((dq_lcd_bdl_value_bdlr0_status_a==0xffff)
+ if ((dq_lcd_bdl_value_bdlr0_status_a == 0xffff)
||(dq_lcd_bdl_value_bdlr0_status_a==0))
{ dq_lcd_bdl_value_bdlr0_status_a=1;
{
@@ -11124,14 +11091,14 @@
i=8+lane_step*8+7;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
{
lcdlr_temp_count=0;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s", buf);
- setenv(env_lcdlr_temp_count, buf);
+ env_set(env_lcdlr_temp_count, buf);
run_command("save",0);
}
@@ -11148,8 +11115,8 @@
}
else if (dq_lcd_bdl_value_bdlr0_status_a==1)
{
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
+ temp_s= env_get(env_lcdlr_temp_count);
+ if (temp_s)
{
lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
}
@@ -11167,25 +11134,25 @@
i=8+lane_step*8+5;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
i=8+lane_step*8+7;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
run_command("reset",0);
}
- if((dq_lcd_bdl_value_bdlr0_status_a==2)||
+ if ((dq_lcd_bdl_value_bdlr0_status_a == 2) ||
(dq_lcd_bdl_value_bdlr0_status_a==3))
{
{
- if(dq_lcd_bdl_value_bdlr0_status_a==2)
- {
+ if (dq_lcd_bdl_value_bdlr0_status_a == 2)
+ {
dq_lcd_bdl_value_bdlr0_status_a=3;
{
@@ -11193,7 +11160,7 @@
i=8+lane_step*8+7;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
@@ -11201,7 +11168,7 @@
lcdlr_temp_count=0;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s", buf);
- setenv(env_lcdlr_temp_count, buf);
+ env_set(env_lcdlr_temp_count, buf);
run_command("save",0);
}
@@ -11218,8 +11185,8 @@
}
else if (dq_lcd_bdl_value_bdlr0_status_a==3)
{
- temp_s= getenv(env_lcdlr_temp_count);
- if(temp_s)
+ temp_s= env_get(env_lcdlr_temp_count);
+ if (temp_s)
{
lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
}
@@ -11238,12 +11205,12 @@
i=8+lane_step*8+6;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
i=8+lane_step*8+7;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
run_command("reset",0);
@@ -11252,7 +11219,7 @@
}
/*
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==0xffff)||
+ if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 0xffff) ||
(dq_lcd_bdl_value_rdqs_status_a[lane_step]==0))
{dq_lcd_bdl_value_rdqs_status_a[lane_step]=0;
sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),2);
@@ -11271,7 +11238,7 @@
run_command("reset",0);
}
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==1)||
+ if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 1) ||
(dq_lcd_bdl_value_rdqs_status_a[lane_step]==2))
{dq_lcd_bdl_value_rdqs_status_a[lane_step]=2;
sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),1);
@@ -11289,7 +11256,7 @@
num_to_env(varname,num_arry);
run_command("reset",0);
}
- */
+ */
ddr_test_watchdog_disable(); //s
@@ -11473,7 +11440,7 @@
#define DDR3_ODT_20OHM 4
#define DDR3_ODT_30OHM 5
- // lpddr2 drv odt
+ // lpddr2 drv odt
#define LPDDR2_DRV_34OHM 1
#define LPDDR2_DRV_40OHM 2
#define LPDDR2_DRV_48OHM 3
@@ -11482,7 +11449,7 @@
#define LPDDR2_DRV_120OHM 7
#define LPDDR2_ODT_0OHM 0
- // lpddr3 drv odt
+ // lpddr3 drv odt
#define LPDDR3_DRV_34OHM 1
#define LPDDR3_DRV_40OHM 2
#define LPDDR3_DRV_48OHM 3
@@ -11538,7 +11505,7 @@
zqcr = 0;
}
- if(zqcr==0xffffffff)
+ if (zqcr == 0xffffffff)
{
ddr_full_test_enable=1;
zqcr=0;}
@@ -11622,25 +11589,25 @@
soc_dram_drv_odt_use_vlaue = 0;
}
}
- if(soc_dram_drv_odt_use_vlaue)
+ if (soc_dram_drv_odt_use_vlaue)
{if(zqcr)
{printf("zqcr[0x%08x],\n", zqcr);
{
soc_ac_drv=zqcr%100;
- if(soc_ac_drv>100)
+ if (soc_ac_drv>100)
{soc_ac_drv=0;}
- if(soc_ac_drv==0)
+ if (soc_ac_drv == 0)
{soc_ac_drv=1;}
soc_ac_drv=(480/soc_ac_drv)-1;
- if(ddr_type==DDR_TYPE_DDR3)
+ if (ddr_type == DDR_TYPE_DDR3)
{
- if(soc_ac_drv>0xf)
+ if (soc_ac_drv>0xf)
{soc_ac_drv=zq0pr_org&0xf;}
}
- if(ddr_type==DDR_TYPE_DDR4)
+ if (ddr_type == DDR_TYPE_DDR4)
{
- if(soc_ac_drv>0xf)
+ if (soc_ac_drv>0xf)
{soc_ac_drv=(zq0pr_org>>8)&0xf;}
}
}
@@ -11648,22 +11615,22 @@
{
soc_ac_odt=zqcr/100;
- if(soc_ac_odt>240)
+ if (soc_ac_odt>240)
{soc_ac_odt=480;}
- if(soc_ac_odt==0)
+ if (soc_ac_odt == 0)
{soc_ac_odt=1;}
- if(ddr_type==DDR_TYPE_DDR3)
+ if (ddr_type == DDR_TYPE_DDR3)
{
soc_ac_odt=(360/soc_ac_odt)-1;
- if(soc_ac_odt>0xf)
+ if (soc_ac_odt>0xf)
{soc_ac_odt=(zq0pr_org>>4)&0xf;}
}
- if(ddr_type==DDR_TYPE_DDR4)
+ if (ddr_type == DDR_TYPE_DDR4)
{
soc_ac_odt=(480/soc_ac_odt)-1;
- if(soc_ac_odt>0xf)
+ if (soc_ac_odt>0xf)
{soc_ac_odt=(zq0pr_org>>16)&0xf;}
}
}
@@ -11671,16 +11638,16 @@
zqcr=(soc_ac_odt<<16)|(soc_ac_drv<<12)|(soc_ac_drv<<8)|(soc_ac_odt<<4)|(soc_ac_drv);
printf("zqcr[0x%08x],soc_ac_odt [0x%08x],soc_ac_drv [0x%08x]\n", zqcr,soc_ac_odt,soc_ac_drv);
}
- if(zqpr_soc_dram)
+ if (zqpr_soc_dram)
{printf("zqpr_soc_dram[0x%08x],\n", zqpr_soc_dram);
{
soc_data_drv=zqpr_soc_dram%100;
printf("soc_data_drv[%d],\n", soc_data_drv);
- if(soc_data_drv>100)
+ if (soc_data_drv>100)
{soc_data_drv=0;
}
- if(soc_data_drv==0)
+ if (soc_data_drv == 0)
{soc_data_drv=1;
//soc_data_drv_odt_adj_enable=0;
}
@@ -11689,14 +11656,14 @@
}
soc_data_drv=(480/soc_data_drv)-1;
- if(ddr_type==DDR_TYPE_DDR3)
+ if (ddr_type == DDR_TYPE_DDR3)
{
- if(soc_data_drv>0xf)
+ if (soc_data_drv>0xf)
{soc_data_drv=zq1pr_org&0xf;}
}
- if(ddr_type==DDR_TYPE_DDR4)
+ if (ddr_type == DDR_TYPE_DDR4)
{
- if(soc_data_drv>0xf)
+ if (soc_data_drv>0xf)
{soc_data_drv=(zq1pr_org>>8)&0xf;}
}
}
@@ -11705,22 +11672,22 @@
{
soc_data_odt=(zqpr_soc_dram/100)%1000;
printf("soc_data_odt[%d],\n", soc_data_odt);
- if(soc_data_odt>240)
+ if (soc_data_odt>240)
{soc_data_odt=360;}
- if(soc_data_odt==0)
+ if (soc_data_odt == 0)
{soc_data_odt=1;}
- if(ddr_type==DDR_TYPE_DDR3)
+ if (ddr_type == DDR_TYPE_DDR3)
{
soc_data_odt=(360/soc_data_odt)-1;
- if(soc_data_odt>0xf)
+ if (soc_data_odt>0xf)
{soc_data_odt=(zq1pr_org>>4)&0xf;}
}
- if(ddr_type==DDR_TYPE_DDR4)
+ if (ddr_type == DDR_TYPE_DDR4)
{
soc_data_odt=(480/soc_data_odt)-1;
- if(soc_data_odt>0xf)
+ if (soc_data_odt>0xf)
{soc_data_odt=(zq1pr_org>>16)&0xf;}
}
@@ -11732,18 +11699,18 @@
dram_drv=(zqpr_soc_dram/100000)%100;
printf("dram_drv[%d],\n", dram_drv);
- if(dram_drv>100)
+ if (dram_drv>100)
{dram_drv=0;}
- if(dram_drv==0)
+ if (dram_drv == 0)
{
dram_data_drv_adj_enable=0;}
else
{dram_data_drv_adj_enable=1;
}
- if(ddr_type==DDR_TYPE_DDR3)
+ if (ddr_type == DDR_TYPE_DDR3)
{
- if(dram_drv>=40)
+ if (dram_drv >= 40)
{dram_drv=0;}
else
@@ -11752,9 +11719,9 @@
}
- if(ddr_type==DDR_TYPE_DDR4)
+ if (ddr_type == DDR_TYPE_DDR4)
{
- if(dram_drv<48)
+ if (dram_drv<48)
{dram_drv=0;}
else
@@ -11767,9 +11734,9 @@
{
dram_odt=(zqpr_soc_dram/100000)/100;
printf("dram_odt[%d],\n", dram_odt);
- if(dram_odt>240)
+ if (dram_odt>240)
{dram_odt=480;}
- if(dram_odt==0)
+ if (dram_odt == 0)
{
dram_data_odt_adj_enable=0;
}
@@ -11778,9 +11745,9 @@
}
- if(ddr_type==DDR_TYPE_DDR3)
+ if (ddr_type == DDR_TYPE_DDR3)
{
- if(dram_odt>160)
+ if (dram_odt>160)
{dram_odt=0;}
else if (dram_odt>90)
{dram_odt=2;}
@@ -11794,9 +11761,9 @@
{dram_odt=4;}
}
- if(ddr_type==DDR_TYPE_DDR4)
+ if (ddr_type == DDR_TYPE_DDR4)
{
- if(dram_odt>280)
+ if (dram_odt>280)
{dram_odt=0;}
else if (dram_odt>180)
{dram_odt=4;}
@@ -11908,7 +11875,7 @@
dram_odt=(zqpr_soc_dram>>24)&0xf;
printf("setting zqpr_soc_dram [0x%08x],..bit28 enable soc_zqpr , bit 29 enabe dram_drv, bit 30 enabel dram_odt\n", zqpr_soc_dram);
printf("soc_data_drv_odt [0x%08x],dram_drv [0x%08x],dram_odt [0x%08x]\n", soc_data_drv_odt,dram_drv,dram_odt);
- if(ddr_full_test_enable)
+ if (ddr_full_test_enable)
{
pll=(ddr_full_test_enable<<21)|pll;
printf("ddr_full_test_enable %08x,set sticky reg1 bit 21 1\n", ddr_full_test_enable);
@@ -11939,7 +11906,7 @@
// *P_WATCHDOG_RESET = 0;
ddr_test_watchdog_reset_system();
#endif
- while(1);
+ while (1) ;
return 0;
usage:
@@ -12104,16 +12071,16 @@
writel(sticky_cmd, PREG_STICKY_REG1);
uint32_t read_value = 0;
- if(value_size)
+ if (value_size)
{
read_value=rd_reg(G12_DMC_STICKY_0+((cmd_offset/4)<<2));
- if(value_size==1){
+ if (value_size == 1) {
wr_reg((G12_DMC_STICKY_0+((cmd_offset/4)<<2)), ((cmd_value<<((cmd_offset%4)*8))|(read_value&(~(0xff<<((cmd_offset%4)*8))))));
}
- if(value_size==2){
+ if (value_size == 2) {
wr_reg((G12_DMC_STICKY_0+((cmd_offset/4)<<2)), ((cmd_value<<((cmd_offset%4)*8))|(read_value&(~(0xffff<<((cmd_offset%4)*8))))));
}
- if(value_size==4){
+ if (value_size == 4) {
// wr_reg((G12_DMC_STICKY_0+cmd_offset/4), ((cmd_value<<((cmd_offset%4)*8))|(read_value&(~(0xffff<<((cmd_offset%4)*8))))));
wr_reg((G12_DMC_STICKY_0+((cmd_offset/4)<<2)), cmd_value);
}
@@ -12127,11 +12094,11 @@
printf("PREG_STICKY_REG0== [0x%08x]\n", readl(PREG_STICKY_REG0));
- if(reset_enable)
+ if (reset_enable)
{
ddr_test_watchdog_reset_system();
- while(1);
+ while (1) ;
}
return 0;
@@ -13635,7 +13602,7 @@
while (ac_lcdlr_temp>0)
{
- if(test_min_max)
+ if (test_min_max)
{break;
}
temp_test_error=0;
@@ -13719,7 +13686,7 @@
ac_bdlr0_temp=readl(reg_add);
while (ac_bdlr0_temp>0)
{
- if(test_min_max)
+ if (test_min_max)
{break;
}
temp_test_error=0;
@@ -14197,7 +14164,7 @@
while (ac_lcdlr_temp>0)
{
- if(test_min_max)
+ if (test_min_max)
{break;
}
temp_test_error=0;
@@ -17516,7 +17483,7 @@
int do_ddr4_test_phy_vref(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
printf("watchdog_time_s==%d\n",watchdog_time_s);
- if(watchdog_time_s==0)
+ if (watchdog_time_s == 0)
{
watchdog_time_s=50;
printf("test soc_vref re set watchdog_time_s==%d\n",watchdog_time_s);
@@ -17591,33 +17558,33 @@
unsigned int soc_iovref_test_ddr_clk=0;
sprintf(str_temp1,"ddr_soc_iovref_test_ddr_clk");
soc_iovref_test_ddr_clk=env_to_a_num(str_temp1);
- if(soc_iovref_test_ddr_clk==0)
+ if (soc_iovref_test_ddr_clk == 0)
{
soc_iovref_test_ddr_clk=global_ddr_clk;
{
sprintf(str_temp1,"ddr_soc_iovref_test_ddr_clk");
sprintf(str_temp2,"0x%08x",soc_iovref_test_ddr_clk);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
}
- if(soc_iovref_test_ddr_clk!=global_ddr_clk)
+ if (soc_iovref_test_ddr_clk != global_ddr_clk)
{
printf("running ddr freq==%d,but test freq is %d,will reboot use d2pll \n",global_ddr_clk,soc_iovref_test_ddr_clk);
sprintf(str,"d2pll %d",soc_iovref_test_ddr_clk);
printf("\nstr=%s\n",str);
run_command(str,0);
- while(1);
+ while (1) ;
}
unsigned int soc_iovref_test_step=0;
sprintf(str_temp1,"soc_iovref_test_step");
soc_iovref_test_step=env_to_a_num(str_temp1);
- if(soc_iovref_test_step==0)
+ if (soc_iovref_test_step == 0)
iovref_temp_value=0;
{
sprintf(str_temp1,"soc_iovref_test_step");
sprintf(str_temp2,"0x%08x",iovref_temp_value);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
@@ -17888,21 +17855,21 @@
sprintf(str_temp1,"ddr_soc_iovref_org");
ddr_soc_iovref_org=env_to_a_num(str_temp1);
- if(ddr_soc_iovref_org==0)
+ if (ddr_soc_iovref_org == 0)
{
sprintf(str_temp1,"ddr_soc_iovref_org");
sprintf(str_temp2,"0x%08x",iovref_temp_value);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
sprintf(str_temp1,"ddr_soc_iovref_lef");
sprintf(str_temp2,"0x%08x",iovref_temp_value);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
sprintf(str_temp1,"ddr_soc_iovref_rig");
sprintf(str_temp2,"0x%08x",iovref_temp_value);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
sprintf(str_temp1,"ddr_soc_iovref_lef");
@@ -17911,7 +17878,7 @@
soc_iovref_rig=env_to_a_num(str_temp1);
- if(soc_iovref_lef)
+ if (soc_iovref_lef)
{;
}
@@ -17924,15 +17891,15 @@
{
sprintf(str_temp1,"soc_iovref_test_step");
sprintf(str_temp2,"0x%08x",soc_iovref_test_step);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
//break;
}
- if(soc_iovref_test_step==0)
+ if (soc_iovref_test_step == 0)
{//int temp=0;
- if(soc_iovref_lef)
+ if (soc_iovref_lef)
{iovref_temp_value=soc_iovref_lef;
}
while (iovref_temp_value>0x0)
@@ -17947,7 +17914,7 @@
{
sprintf(str_temp1,"ddr_soc_iovref_lef");
sprintf(str_temp2,"0x%08x",iovref_temp_value);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
@@ -18111,7 +18078,7 @@
{
sprintf(str_temp1,"ddr_soc_iovref_lef");
sprintf(str_temp2,"0x%08x",iovref_temp_value);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
@@ -18119,7 +18086,7 @@
soc_iovref_test_step=1;
sprintf(str_temp1,"soc_iovref_test_step");
sprintf(str_temp2,"0x%08x",soc_iovref_test_step);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
run_command("reset",0);
}
@@ -18191,9 +18158,9 @@
iovref_temp_value=((iovref_temp_value)&0xff);
//if(soc_iovref_rig==0)
- if(soc_iovref_test_step==1)
+ if (soc_iovref_test_step == 1)
{
- if(soc_iovref_rig)
+ if (soc_iovref_rig)
{iovref_temp_value=soc_iovref_rig;
}
while (iovref_temp_value<0x3f)
@@ -18207,7 +18174,7 @@
{
sprintf(str_temp1,"ddr_soc_iovref_rig");
sprintf(str_temp2,"0x%08x",iovref_temp_value);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
@@ -18373,7 +18340,7 @@
{
sprintf(str_temp1,"ddr_soc_iovref_rig");
sprintf(str_temp2,"0x%08x",iovref_temp_value);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
@@ -18381,7 +18348,7 @@
soc_iovref_test_step=2;
sprintf(str_temp1,"soc_iovref_test_step");
sprintf(str_temp2,"0x%08x",soc_iovref_test_step);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
//run_command("reset",0);
}
@@ -18458,20 +18425,20 @@
{
sprintf(str_temp1,"ddr_soc_iovref_org");
sprintf(str_temp2,"0x%08x",iovref_org[0]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
{
sprintf(str_temp1,"ddr_soc_iovref_lef");
sprintf(str_temp2,"0x%08x",iovref_lef[0]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
{
sprintf(str_temp1,"ddr_soc_iovref_rig");
sprintf(str_temp2,"0x%08x",iovref_rig[0]);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
@@ -18494,7 +18461,7 @@
printf("watchdog_time_s==%d\n",watchdog_time_s);
- if(watchdog_time_s==0)
+ if (watchdog_time_s == 0)
{
watchdog_time_s=50;
printf("test dram_vref re set watchdog_time_s==%d\n",watchdog_time_s);
@@ -18747,22 +18714,22 @@
unsigned int dram_iovref_test_ddr_clk=0;
sprintf(str_temp1,"ddr_dram_iovref_test_ddr_clk");
dram_iovref_test_ddr_clk=env_to_a_num(str_temp1);
- if(dram_iovref_test_ddr_clk==0)
+ if (dram_iovref_test_ddr_clk == 0)
{dram_iovref_test_ddr_clk=global_ddr_clk;
{
sprintf(str_temp1,"ddr_dram_iovref_test_ddr_clk");
sprintf(str_temp2,"0x%08x",dram_iovref_test_ddr_clk);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
}
- if(dram_iovref_test_ddr_clk!=global_ddr_clk)
+ if (dram_iovref_test_ddr_clk != global_ddr_clk)
{
printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n",global_ddr_clk,dram_iovref_test_ddr_clk);
sprintf(str,"d2pll %d",dram_iovref_test_ddr_clk);
printf("\nstr=%s\n",str);
run_command(str,0);
- while(1);
+ while (1) ;
}
@@ -18770,9 +18737,9 @@
{
sprintf(str_temp1,"ddr_dram_iovref_org");
// sprintf(str_temp2,"0x%08x",iovref_org);
- p_str=getenv(str_temp1);
+ p_str=env_get(str_temp1);
- if(p_str)
+ if (p_str)
{
iovref_org= simple_strtoull_ddr(p_str, &endp, 0);
}
@@ -18780,9 +18747,9 @@
sprintf(str_temp1,"ddr_dram_iovref_lef");
//sprintf(str_temp2,"0x%08x",iovref_lef);
- p_str=getenv(str_temp1);
+ p_str=env_get(str_temp1);
- if(p_str)
+ if (p_str)
{
iovref_lef= simple_strtoull_ddr(p_str, &endp, 0);
}
@@ -18790,26 +18757,26 @@
sprintf(str_temp1,"ddr_dram_iovref_rig");
//sprintf(str_temp2,"0x%08x",iovref_rig);
- p_str=getenv(str_temp1);
+ p_str=env_get(str_temp1);
- if(p_str)
+ if (p_str)
{
iovref_rig= simple_strtoull_ddr(p_str, &endp, 0);
}
sprintf(str_temp1,"ddr_dram_vref_range");
//sprintf(str_temp2,"0x%08x",vref_dram_range);
- p_str=getenv(str_temp1);
+ p_str=env_get(str_temp1);
- if(p_str)
+ if (p_str)
{
vref_dram_range= simple_strtoull_ddr(p_str, &endp, 0);
}
}
- if(vref_dram_range|iovref_rig|iovref_org|iovref_lef)
+ if (vref_dram_range|iovref_rig|iovref_org|iovref_lef)
{
printf("\n\ndram iovref test clk==%d\n",dram_iovref_test_ddr_clk);
iovref_mid=(iovref_lef+iovref_rig)/2;
@@ -19187,25 +19154,25 @@
{
sprintf(str_temp1,"ddr_dram_iovref_org");
sprintf(str_temp2,"0x%08x",iovref_org);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
{
sprintf(str_temp1,"ddr_dram_iovref_lef");
sprintf(str_temp2,"0x%08x",iovref_lef);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
{
sprintf(str_temp1,"ddr_dram_iovref_rig");
sprintf(str_temp2,"0x%08x",iovref_rig);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
{
sprintf(str_temp1,"ddr_dram_vref_range");
sprintf(str_temp2,"0x%08x",vref_dram_range);
- setenv(str_temp1, str_temp2);
+ env_set(str_temp1, str_temp2);
run_command("save",0);
}
}
@@ -19844,21 +19811,21 @@
ddr_pll=ddr_pll&0xfffff;
#if 1// (CONFIG_DDR_PHY == P_DDR_PHY_905X)
//unsigned int ddr_clk = 2*((((24 * ((ddr_pll>>4)&0x1ff))/((ddr_pll>>16)&0x1f))>>((((ddr_pll>>0)&0x3)==3)?(2):(((ddr_pll>>0)&0x3))))/(((ddr_pll>>2)&0x3)+1)); //od1 od
- if(((ddr_pll>>16)&7)==0)
+ if (((ddr_pll>>16)&7) == 0)
od_div=2;
- if(((ddr_pll>>16)&7)==1)
+ if (((ddr_pll>>16)&7) == 1)
od_div=3;
- if(((ddr_pll>>16)&7)==2)
+ if (((ddr_pll>>16)&7) == 2)
od_div=4;
- if(((ddr_pll>>16)&7)==3)
+ if (((ddr_pll>>16)&7) == 3)
od_div=6;
- if(((ddr_pll>>16)&7)==4)
+ if (((ddr_pll>>16)&7) == 4)
od_div=8;
- if(((ddr_pll>>10)&0x1f))
+ if (((ddr_pll>>10)&0x1f))
ddr_clk = 2*((((24 * ((ddr_pll>>0)&0x1ff))/((ddr_pll>>10)&0x1f))>>((((ddr_pll>>19)&0x1)==1)?(2):(1))))/od_div;
#else
@@ -19954,18 +19921,18 @@
#endif
#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
//unsigned int ddr_clk = 2*((((24 * ((ddr_pll>>4)&0x1ff))/((ddr_pll>>16)&0x1f))>>((((ddr_pll>>0)&0x3)==3)?(2):(((ddr_pll>>0)&0x3))))/(((ddr_pll>>2)&0x3)+1));
- if(((ddr_pll>>16)&0x1f))
+ if (((ddr_pll>>16)&0x1f))
ddr_clk = 2*((((24 * ((ddr_pll>>4)&0x1ff))/((ddr_pll>>16)&0x1f))>>((((ddr_pll>>0)&0x3)==3)?(2):(((ddr_pll>>0)&0x3))))>>((((ddr_pll>>2)&0x3)==3)?(2):(((ddr_pll>>2)&0x3))));
#else
- if((ddr_pll>>9)&0x1f)
+ if ((ddr_pll>>9)&0x1f)
ddr_clk = 2*(((24 * (ddr_pll&0x1ff))/((ddr_pll>>9)&0x1f))>>((ddr_pll>>16)&0x3));
#endif
#if (CONFIG_DDR_PHY == P_DDR_PHY_DEFAULT)
- if((ddr_pll>>9)&0x1f)
+ if ((ddr_pll>>9)&0x1f)
ddr_clk = 2*((24 * (ddr_pll&0x1ff))/((ddr_pll>>9)&0x1f))>>((ddr_pll>>16)&0x3);
#endif
@@ -20115,7 +20082,7 @@
#endif
//ddr_pll=ddr_pll_org;
printf("\nddr_pll== %08x\n", ddr_pll);
-#if 0
+#if 0
#else
unsigned int ddr_clk = pll_convert_to_ddr_clk(ddr_pll);
ddr_clk_org=ddr_clk;
@@ -20155,7 +20122,7 @@
//
- p_char_ddr_test_step= getenv("ddr_feq_test_step");
+ p_char_ddr_test_step= env_get("ddr_feq_test_step");
if (p_char_ddr_test_step)
{
printf("%s",p_char_ddr_test_step);
@@ -20164,7 +20131,7 @@
printf("ddr_feq_test_step=%d\n",ddr_feq_test_step);
}
if (ddr_feq_test_step) {
- p_char_freq_org= getenv("ddr_feq_org");
+ p_char_freq_org= env_get("ddr_feq_org");
if (p_char_freq_org)
{
printf("%s",p_char_freq_org);
@@ -20179,7 +20146,7 @@
ddr_clk_org=ddr_clk;
sprintf(char_freq_org,"%04d",ddr_clk);
printf("\nddr_org_freq=%s\n",char_freq_org);
- setenv("ddr_feq_org", char_freq_org);
+ env_set("ddr_feq_org", char_freq_org);
temp_count=(DDR_TEST_MIN_FREQ_LIMITED/12);
while (temp_count<(DDR_TEST_MAX_FREQ/12)) {
@@ -20187,8 +20154,8 @@
// sprintf(freq_table,"%s%04d %01d %01d ",freq_table,(temp_count*12),0,0);
sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))));
printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
- setenv(char_freq_name_table, "0");
- setenv("ddr_feq_test_step", "1");
+ env_set(char_freq_name_table, "0");
+ env_set("ddr_feq_test_step", "1");
temp_count++;
}
temp_count=(DDR_TEST_MIN_FREQ_LIMITED/12);
@@ -20197,8 +20164,8 @@
// sprintf(freq_table,"%s%04d %01d %01d ",freq_table,(temp_count*12),0,0);
sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))));
printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
- setenv(char_freq_name_table, "3");
- setenv("ddr_feq_test_step", "1");
+ env_set(char_freq_name_table, "3");
+ env_set("ddr_feq_test_step", "1");
temp_count++;
}
while (temp_count>((end_freq)/12)) {
@@ -20206,16 +20173,16 @@
// sprintf(freq_table,"%s%04d %01d %01d ",freq_table,(temp_count*12),0,0);
sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))));
printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
- setenv(char_freq_name_table, "3");
- setenv("ddr_feq_test_step", "1");
+ env_set(char_freq_name_table, "3");
+ env_set("ddr_feq_test_step", "1");
temp_count++;
}
- p_char_store_boot= getenv("storeboot");
+ p_char_store_boot= env_get("storeboot");
if (p_char_store_boot)
printf("storeboot %s\n",p_char_store_boot);
sprintf(char_cmd_table,"ddr_test_cmd 0x1c 0x%08x %d %d %d;%s;",ddr_test_size,start_freq,end_freq,test_loops,p_char_store_boot);
- setenv("storeboot", char_cmd_table);
+ env_set("storeboot", char_cmd_table);
run_command("save",0);
@@ -20230,7 +20197,7 @@
sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))));
printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
- p_char_freq_name_table= getenv(char_freq_name_table);
+ p_char_freq_name_table= env_get(char_freq_name_table);
if (p_char_freq_name_table)
{
printf("%s\n",p_char_freq_name_table);
@@ -20255,12 +20222,12 @@
sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count_sub*12))));
printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
// freq_table_test_value[temp_count_sub] =1;
- setenv(char_freq_name_table, "3");
+ env_set(char_freq_name_table, "3");
temp_count_sub++;
}
{
ddr_feq_test_step++;
- setenv("ddr_feq_test_step", "2");
+ env_set("ddr_feq_test_step", "2");
run_command("save",0);
}
@@ -20285,7 +20252,7 @@
sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))));
printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
freq_table_test_value[temp_count] =1;
- setenv(char_freq_name_table, "1");
+ env_set(char_freq_name_table, "1");
run_command("save",0);
temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
@@ -20299,12 +20266,12 @@
if (temp_test_error)
{
freq_table_test_value[temp_count] =1;
- setenv(char_freq_name_table, "1");
+ env_set(char_freq_name_table, "1");
}
else
{
freq_table_test_value[temp_count] =2;
- setenv(char_freq_name_table, "2");
+ env_set(char_freq_name_table, "2");
}
run_command("save",0);
@@ -20325,7 +20292,7 @@
temp_count++;
}
ddr_feq_test_step++;
- setenv("ddr_feq_test_step", "2");
+ env_set("ddr_feq_test_step", "2");
run_command("save",0);
}
@@ -20339,7 +20306,7 @@
sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))));
printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
- p_char_freq_name_table= getenv(char_freq_name_table);
+ p_char_freq_name_table= env_get(char_freq_name_table);
if (p_char_freq_name_table)
{
printf("%s\n",p_char_freq_name_table);
@@ -20355,7 +20322,7 @@
while (temp_count<((DDR_TEST_MAX_FREQ)/12)) {
sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*12))));
- p_char_freq_name_table= getenv(char_freq_name_table);
+ p_char_freq_name_table= env_get(char_freq_name_table);
if (p_char_freq_name_table)
{
// printf("%s\n",p_char_freq_name_table);
@@ -20386,7 +20353,7 @@
//sprintf(str, "%lx", value);
- // setenv("env_ddrtest", str);
+ // env_set("env_ddrtest", str);
//run_command("save",0);
@@ -21211,7 +21178,7 @@
int value=0;
//*varname="env_ddrtest";
- s = getenv("env_wr_lcdlr_pr");
+ s = env_get("env_wr_lcdlr_pr");
if (s)
{//i=0;
//while(s_temp)
@@ -21225,7 +21192,7 @@
value = simple_strtoull_ddr(s, &endp, 16);
printf("%d",value);
}
- s = getenv("env_rd_lcdlr_pr");
+ s = env_get("env_rd_lcdlr_pr");
if (s)
{//i=0;
@@ -21239,7 +21206,7 @@
}
//sprintf(str, "%lx", value);
- // setenv("env_ddrtest", str);
+ // env_set("env_ddrtest", str);
//run_command("save",0);
@@ -22176,253 +22143,6 @@
return 1;
}
#endif
-
-void ddr_memcpy(void *dst, const void *src, uint32_t len)
-{//enable_mmu_el1_s();
-// printf("\nlen==%d,",len);
- //printf(len);
- //serial_puts("\n");
-//uint32_t ddr_test_start_time_us=get_us_time(); // check cost time
- //const char *s = src;
- //char *d = dst;
- len=(len>>3);
- const long long *s = src;
- long long *d = dst;
- while (len)
- {
- // ddr_pld_cache(s) ;
- ///1 times len==33554432 copy time==18192 us 1.2g bandwidth 3688M/S
- // 4times len==33554432 copy time==11844 us 1.2g bandwidth 5666M/S
- // 8times len==33554432 copy time==11844 us 1.2g bandwidth 5666M/S
- *d++ = *s++;
- *d++ = *s++;
- *d++ = *s++;
- *d++ = *s++;
- len=len-4;
- }
-// uint32_t ddr_test_end_time_us=get_us_time(); // check cost time
-// serial_puts("\ncopy time==");
-// serial_put_dec(ddr_test_end_time_us-ddr_test_start_time_us);
-// serial_puts("\n");
-//printf("\ncopy time==%d us,",(ddr_test_end_time_us-ddr_test_start_time_us));
-
-}
-#define PATTERN_MATRIX_X (3+32+16+17) //68*32==2176 ///2.2k -0x880-1 loop
- #define PATTERN_MATRIX_Y (32)
- #define PATTERN_MATRIX_LOOP_SIZE ((PATTERN_MATRIX_X)*(PATTERN_MATRIX_Y)*4)
- unsigned int cpu_ddr_test_init_pattern_generater(unsigned int add_offset ) {
-
- unsigned int pattern_select=0;
- unsigned int pattern_value=0;
- //test_size=(test_size>0x10000)?test_size:0x10000;
- // uint32_t write_addr = start_add;
- uint32_t martix_x_select= 0;
- uint32_t martix_y_select= 0;
- unsigned int pattern_value_temp_16=0;
- {
- // uint32_t test_end_add = start_add+test_size;
- // for((write_addr=start_add);(write_addr<test_end_add);)
- {
- pattern_select=((add_offset)%((PATTERN_MATRIX_Y)*(PATTERN_MATRIX_X)));
- martix_x_select=pattern_select/(PATTERN_MATRIX_Y);
- martix_y_select=pattern_select%(PATTERN_MATRIX_Y);
- //write_addr_nibble_start=((((add_offset/PATTERN_MATRIX_Y)/PATTERN_MATRIX_X))*
- // (((PATTERN_MATRIX_Y)*PATTERN_MATRIX_X)));
- //write_addr_nibble_start=(((add_offset)%PATTERN_MATRIX_Y)%PATTERN_MATRIX_X)
- { if(martix_x_select==0)
- pattern_value=0xaaaa5555; //for 16 bit bus pattern
-
- if(martix_x_select==1)
- pattern_value=0x0000ffff; //for 16 bit bus pattern
-
- if(martix_x_select==2)
- pattern_value=0;
-
- if((martix_x_select>2)&&(martix_x_select<(3+32)))
- {
- pattern_value=1<<(martix_x_select-3);
- }
-
- if((martix_x_select>(2+32))&&(martix_x_select<(3+32+16))) //for 16 bit bus pattern
- {
- pattern_value_temp_16=(1<<(martix_x_select-3-32));
- pattern_value=pattern_value_temp_16|((~pattern_value_temp_16)<<16);
-
- }
- if((martix_x_select>(2+32+16))&&(martix_x_select<(3+32+16+17))) //for dbi bus pattern 17 group
- {
- pattern_value_temp_16=(0x0f0f+0xf0f*(martix_x_select-3-32-16));
- pattern_value=pattern_value_temp_16|((~pattern_value_temp_16)<<16);
-
- }
-
- }
- if(martix_y_select%2)
- pattern_value=~pattern_value;
- }
-
- }
- // serial_puts("\ncpu_test_ddr_debug4");
- return pattern_value;
-}
-void cpu_ddr_test_init_pattern_area(unsigned int test_init_start,unsigned int test_size,unsigned int parttern_frequency_setting ) {
-
-// printf("\n 111");
- if(parttern_frequency_setting==0)
- parttern_frequency_setting=1; //for different frequency pattern
- test_size=(test_size>((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting)))?test_size:((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting));
- //unsigned int test_start=0x1080000;
- unsigned int write_add=test_init_start;
- unsigned int size_loop=0;
- unsigned int size_loop_max=0;
- //unsigned int count=0;
- for(;(size_loop<((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting)));)
- {
- //serial_puts("\ncpu_test_ddr_debug5");
-
- // for( count=0;count<(parttern_frequency_setting);)
- {
- write_add = (uint32_t)(size_loop + test_init_start);
- wr_reg((unsigned long)write_add, cpu_ddr_test_init_pattern_generater((size_loop>>2)/parttern_frequency_setting));
- size_loop=size_loop+4;
- }
- // serial_puts("\ncpu_test_ddr_debug6");
-
- // serial_puts(" ");
- #if 0
- serial_put_hex(size_loop,32);
- serial_puts(" ");
- serial_put_hex(cpu_ddr_test_init_pattern_generater(size_loop>>2),32);
-#endif
-
- }
- size_loop=1;
- size_loop_max=((test_size/(((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting))))+1);
- for(;(size_loop<size_loop_max);)
- {
- // serial_puts("\ncpu_test_ddr_debug41");
- ddr_memcpy((void *)(uint64_t)(test_init_start+((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting))*(size_loop)), (void *)(uint64_t)test_init_start, ((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting)));
-//serial_puts("\ncpu_test_ddr_debug42");
-size_loop++;
- }
-}
-unsigned int cpu_ddr_test(unsigned test_init_start,unsigned int start_add, unsigned int test_size, unsigned int test_data_bit_enable,unsigned int parttern_frequency_setting) {
-//printf("\n 1112");
-
- unsigned int src_add=test_init_start;
- unsigned int pattern_value=0;
- unsigned int size_loop=0;
- unsigned int ddr_test_error=0;
- unsigned int read_add=0;
- unsigned int read_value=0;
- test_size=(test_size>0x2000)?(test_size):(0x2000);
- //cpu_ddr_test_init_pattern_area(test_size);
- uint32_t ddr_test_start_time_us=get_us_time(); // check cost time
- ddr_memcpy((void *)(uint64_t)start_add, (void *)(uint64_t)src_add, test_size);
-uint32_t ddr_test_end_time_us=get_us_time(); // check cost time
- printf("\ncpu_ddr_test_test_copy_bandwidth==%d Mbyte/s\n",(1*test_size*2)/(ddr_test_end_time_us-ddr_test_start_time_us));
-
- for(;size_loop<(test_size);)
- {read_add = (uint32_t)(size_loop + start_add);
- read_value=(rd_reg((unsigned long)read_add));
- pattern_value=( cpu_ddr_test_init_pattern_generater((size_loop>>2)/parttern_frequency_setting));
- if(((test_data_bit_enable)&read_value)!=((test_data_bit_enable)&pattern_value))
- {
- #if 1
- printf("error data enable %08x read_value %08x pattern_value %08x",test_data_bit_enable,read_value,pattern_value);
- #if 0
- serial_puts("\nerror data ");
- serial_put_hex(test_data_bit_enable,32);
- serial_puts(" ");
- serial_put_hex(read_value,32);
- serial_puts(" ");
- serial_put_hex(pattern_value,32);
- serial_puts("\n");
- #endif
- #endif
- ddr_test_error++;
- return ddr_test_error;
- }
- size_loop=size_loop+(1<<2);// use big step will fast test ,but lose accuracy.
- }
- //printf("\n 1114");
- return ddr_test_error;
-}
-
-int do_cpu_ddr_test (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{//ddr_cpu_test 0x1080000 0x10000000 0x2000000 0xffffffff 10 //size do not overlap
- int i=0;
- printf("\nargc== 0x%08x\n", argc);
- for (i = 0;i<argc;i++)
- {
- printf("\nargv[%d]=%s\n",i,argv[i]);
- }
- unsigned int init_start_add=0;
- unsigned int test_add=0;
- unsigned int test_size=0;
- unsigned int test_data_bit_enable=0;
- unsigned int test_loops=0;
- unsigned int test_loop=0;
- unsigned int test_errors=0;
- unsigned int parttern_frequency_setting =1;
- char *endp;
- if (argc == 1)
- printf("\nplease read help\n");
- else
- {
- if (argc >= 2)
- {
- // zq0pr0 = argv[1];
- init_start_add= simple_strtoull_ddr(argv[1], &endp, 0);
- }
-
- if (argc >= 3)
- {
- // zq1pr0 = argv[2];
- test_add= simple_strtoull_ddr(argv[2], &endp, 0);
- }
- if (argc >= 4)
- {
- // zq1pr0 = argv[2];
- test_size= simple_strtoull_ddr(argv[3], &endp, 0);
- }
- if (argc >= 5)
- {
- // zq1pr0 = argv[2];
- test_data_bit_enable= simple_strtoull_ddr(argv[4], &endp, 0);
- }
- if (argc >= 6)
- {
- // zq1pr0 = argv[2];
- test_loops= simple_strtoull_ddr(argv[5], &endp, 0);
- if(test_loops==0)
- test_loops=1;
- }
- if (argc >= 7)
- {
- // zq1pr0 = argv[2];
- parttern_frequency_setting= simple_strtoull_ddr(argv[6], &endp, 0);
- if(parttern_frequency_setting==0)
- parttern_frequency_setting=1;
- }
- }
- uint32_t ddr_test_start_time_us=get_us_time(); // check cost time
- cpu_ddr_test_init_pattern_area(init_start_add,test_size,parttern_frequency_setting);
- for(test_loop=0;test_loop<test_loops;)
- {test_errors=test_errors+cpu_ddr_test(init_start_add,test_add,test_size,test_data_bit_enable,parttern_frequency_setting);
- test_loop++;
- printf("\ncpu_ddr_test_test_times==%d test_errors==%d",test_loop,test_errors);
- }
- uint32_t ddr_test_end_time_us=get_us_time(); // check cost time
- printf("\ncpu_ddr_test_test_and compare_bandwidth==%d Mbyte/s\n",(test_loops*test_size*2)/(ddr_test_end_time_us-ddr_test_start_time_us));
- return test_errors;
-}
-U_BOOT_CMD(
- ddr_cpu_test, 30, 1, do_cpu_ddr_test,
- "ddr_test_cmd cmd arg1 arg2 arg3...",
- "ddr_test_cmd cmd arg1 arg2 arg3... \n dcache off ? \n"
- );
-
int do_ddr_test_write_read (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
///*
@@ -22529,8 +22249,8 @@
do
{
if (write_read == 0)
- {
- if(!no_show_info)
+ {
+ if (!no_show_info)
printf("\nloop:0x%08x:Start writing at 0x%08x - 0x%08x...", loop,start_addr, start_addr + test_size);
for (j=0;j<test_size/4;)
{
@@ -22542,8 +22262,8 @@
}
}
if (write_read == 1)
- {
- if(!no_show_info)
+ {
+ if (!no_show_info)
printf("\nloop:0x%08x:Start reading at 0x%08x - 0x%08x...", loop,start_addr, start_addr + test_size);
for (j=0;j<test_size/4;)
{
@@ -22554,14 +22274,14 @@
j=j+4;
}
if (loop == 1) {
- if(!no_show_info)
+ if (!no_show_info)
printf(" \nloop:0x%08x:Start reading read_pattern[0] 0x%08x, pattern[1] 0x%08x,pattern[2] 0x%08x,pattern[3] 0x%08x",
loop,read_pattern[0], read_pattern[1],read_pattern[2],read_pattern[3]
); }
}
if (write_read == 2)
- {
- if(!no_show_info)
+ {
+ if (!no_show_info)
printf("\nloop:0x%08x:Start copying at 0x%08x - 0x%08x...", loop,start_addr, start_addr + test_size);
for (j=0;j<test_size/4;)
{
@@ -22572,7 +22292,7 @@
j=j+4;
}
}
- if(us_delay_counter)
+ if (us_delay_counter)
{
ddr_udelay(us_delay_counter);
}
@@ -22691,7 +22411,7 @@
unsigned int argc_count=1;
unsigned int para_meter[30]={0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0,};
- while(argc_count<argc)
+ while (argc_count<argc)
{para_meter[argc_count-1]= simple_strtoul(argv[argc_count], &endp, 0);
if (*argv[argc_count] == 0 || *endp != 0) {
para_meter[argc_count-1] = 0;
@@ -22760,7 +22480,7 @@
bdlr_100_max=(bdlr_100_cur>bdlr_100_max)?bdlr_100_cur:bdlr_100_max;
bdlr_100_average=(bdlr_100_cur+bdlr_100_average*count)/(count+1);
count++;
- if(show_count_message)
+ if (show_count_message)
printf("%d\n",bdlr_100_cur);
}while(count<loop);
@@ -22776,15 +22496,6 @@
return 1;
}
-
-typedef struct ddr_sha_s {
- unsigned char sha2[SHA256_SUM_LEN];
- ddr_set_t ddrs;
-} ddr_sha_t;
-
-ddr_sha_t ddr_sha = {{0}};
-ddr_set_t *ddr_set_t_p_arrary = &ddr_sha.ddrs;
-
int do_ddr_display_g12_ddr_information(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@@ -22795,19 +22506,7 @@
for (i = 0;i<argc;i++)
printf("\nargv[%d]=%s\n",i,argv[i]);
- ddr_set_t *ddr_set_t_p=NULL;
- ddr_set_t_p=(ddr_set_t *)(ddr_set_t_p_arrary);
- //ddr_set_t_p= (ddr_set_t *)G12_DMC_STICKY_0;
- //if (sizeof(ddr_set_t)<loop_max)
- printf("\nddr_set_t_p==0x%08x\n",(uint32_t)(uint64_t)(ddr_set_t_p));
- uint32_t loop=0;
- uint32_t loop_max = (4+(0x3f<<2));//((DMC_STICKY_63-DMC_STICKY_0));
- // loop_max=sizeof(ddr_set_t);
- for (loop = 0; loop <loop_max; loop+=4) {
- wr_reg(((uint64_t)(ddr_set_t_p) + loop), rd_reg(G12_DMC_STICKY_0 + loop));
- }
-
{
uint16_t dq_bit_delay[72];
unsigned char t_count=0;
@@ -22819,178 +22518,107 @@
ui_1_32_100step=(1000000*100/(global_ddr_clk*2*32));
{
-
-
// dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(0<<12)|(0x20),p_dev->p_ddrs->dfi_mrl); //DFIMRL
//dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(1<<12)|(0x20),p_dev->p_ddrs->dfi_mrl); //DFIMRL
//dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(2<<12)|(0x20),p_dev->p_ddrs->dfi_mrl); //DFIMRL
//dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(3<<12)|(0x20),p_dev->p_ddrs->dfi_mrl); //DFIMRL
//dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0x20),p_dev->p_ddrs->dfi_mrl); //HwtMRL
- //ddr_set_t_p->dfi_mrl;
- //ddr_set_t_p->dfi_hwtmrl;
- ddr_set_t_p->ARdPtrInitVal=0;
- printf("\n ARdPtrInitVal");
- add_offset=((0<<20)|(0<<16)|(0<<12)|(0x2e));
- delay_org=dwc_ddrphy_apb_rd(add_offset);
- ddr_set_t_p->ARdPtrInitVal=delay_org;
- printf("\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
-
+
printf("\n dfimrl0 dfimrl1 dfimrl2 dfimrl3 HwtMRL");
- add_offset=((0<<20)|(1<<16)|(0<<12)|(0x20));
+ add_offset=((0<<20)|(0<<16)|(0<<12)|(0x20));
delay_org=dwc_ddrphy_apb_rd(add_offset);
- ddr_set_t_p->dfi_mrl=delay_org;
printf("\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
- add_offset=((0<<20)|(1<<16)|(1<<12)|(0x20));
+ add_offset=((0<<20)|(0<<16)|(1<<12)|(0x20));
delay_org=dwc_ddrphy_apb_rd(add_offset);
printf("\n t_count: %04d %04d %08x %08x",1,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
- add_offset=((0<<20)|(1<<16)|(2<<12)|(0x20));
+ add_offset=((0<<20)|(0<<16)|(2<<12)|(0x20));
delay_org=dwc_ddrphy_apb_rd(add_offset);
printf("\n t_count: %04d %04d %08x %08x",2,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
- add_offset=((0<<20)|(1<<16)|(3<<12)|(0x20));
+ add_offset=((0<<20)|(0<<16)|(3<<12)|(0x20));
delay_org=dwc_ddrphy_apb_rd(add_offset);
printf("\n t_count: %04d %04d %08x %08x",3,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
add_offset=((0<<20)|(2<<16)|(0<<12)|(0x20));
delay_org=dwc_ddrphy_apb_rd(add_offset);
-
- ddr_set_t_p->dfi_hwtmrl=delay_org;
printf("\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
}
{
printf("\n count_index delay_value register_add register_value \n ");
printf("\n address delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6 is coarse --step==1UI",ui_1_32_100step);
- for(t_count=0;t_count<10;t_count++)
+ for (t_count=0;t_count<10;t_count++)
{
add_offset=((0<<20)|(0<<16)|(t_count<<12)|(0x80));
dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
delay_org=dq_bit_delay[t_count];
delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
- ddr_set_t_p->ac_trace_delay[t_count]=delay_temp;
printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
}
}
{
printf("\n tdqs delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6-9 is coarse --step==1UI",ui_1_32_100step);
- for(t_count=0;t_count<16;t_count++)
+ for (t_count=0;t_count<16;t_count++)
{
add_offset=((0<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0xd0+(t_count/8)+((t_count%2)<<8)));
dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
delay_org=dq_bit_delay[t_count];
delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
-
- ddr_set_t_p->write_dqs_delay[t_count]=delay_temp;
-
printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
}
}
{
printf("\n rxdqs delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI,no coarse",ui_1_32_100step);
- for(t_count=0;t_count<16;t_count++)
+ for (t_count=0;t_count<16;t_count++)
{
add_offset=((0<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0x8c+(t_count/8)+((t_count%2)<<8)));
dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
delay_org=dq_bit_delay[t_count];
delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
- ddr_set_t_p->read_dqs_delay[t_count]=delay_temp;
printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
}
}
{
printf("\n write dq_bit delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6-8 is coarse --step==1U",ui_1_32_100step);
- for(t_count=0;t_count<72;t_count++)
+ for (t_count=0;t_count<72;t_count++)
{
add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(0xc0+((t_count%9)<<8)+(t_count/36)));
dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
delay_org=dq_bit_delay[t_count];
delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
-
- ddr_set_t_p->write_dq_bit_delay[t_count]=delay_temp;
-
-
printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
}
}
{
printf("\n read dq_bit delay * BDLRx100==%d ps bit0-4 fine tune --step==bdlr step size about 5ps,no coarse",bdlr_100step);
- for(t_count=0;t_count<72;t_count++)
+ for (t_count=0;t_count<72;t_count++)
{
add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(0x68+((t_count%9)<<8)+(t_count/36)));
dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
delay_org=dq_bit_delay[t_count];
delay_temp=((delay_org&0x3f));
-
- ddr_set_t_p->read_dq_bit_delay[t_count]=delay_temp;
printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
}
}
{
printf("\n read dqs gate delay * 1/32UIx100==%d ps bit0-4 fine tune ,bit 6-10 is coarse",ui_1_32_100step);
- for(t_count=0;t_count<16;t_count++)
+ for (t_count=0;t_count<16;t_count++)
{
add_offset=((0<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0x80+(t_count/8)+((t_count%2)<<8)));
dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
delay_org=dq_bit_delay[t_count];
delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
-
- ddr_set_t_p->read_dqs_gate_delay[t_count]=delay_temp;
-
-
printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
}
printf("\n soc vref : lpddr4-- VREF = VDDQ*(0.047 + VrefDAC0[6:0]*0.00367 DDR4 --VREF = VDDQ*(0.510 + VrefDAC0[6:0]*0.00345");
- //((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40),over_ride_value)
- uint32_t vref_t_count=0;
- for(t_count=0;t_count<72;t_count++)
+ //((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40),over_ride_value)
+ for (t_count=0;t_count<72;t_count++)
{
add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(((t_count%36)%9)<<8)|(0x40));
dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
delay_org=dq_bit_delay[t_count];
delay_temp=((delay_org));
-
-if(t_count<35)
-{
- vref_t_count=((((t_count%36)/9)*8)+(t_count%9));
-
- ddr_set_t_p->soc_bit_vref[vref_t_count]=delay_temp;
-}
-
-
printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
}
-
-
-
- printf("\n dram vref : lpddr4-- VREF = VDDQ*(0. + VrefDAC0[6:0]*0. DDR4 --VREF = VDDQ*(0. + VrefDAC0[6:0]*0.");
- add_offset=((0<<20)|(1<<16)|(0<<12)|(0x082));
-delay_temp=dwc_ddrphy_apb_rd(add_offset);
- for(t_count=0;t_count<32;t_count++)
- {
-
-
- ddr_set_t_p->dram_bit_vref[t_count]=delay_temp;
-
-
-
- // printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
- }
- printf("\n t_count: %04d %04d %08x %08x",0,delay_temp,((((add_offset) << 1)+0xfe000000)),delay_temp);
}
-
- // if(over_ride_index ==DMC_TEST_WINDOW_INDEX_RETRAINING)
- { // if (read_write==REGISTER_READ)
- for(t_count=0;t_count<4;t_count++)
- {//p_dev->p_ddrs->tdqs2dq=lpddr4_tdqs2dq;
- //ddr_set_t_p->retraining[0]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(0<<12)|(0xaa)); //PptCtlStatic
- //ddr_set_t_p->retraining[1]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(0<<12)|(0xae)); //PptDqsCntInvTrnTg0 ps0 rank0
- //ddr_set_t_p->retraining[2]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(0<<12)|(0xaf)); //PptDqsCntInvTrnTg0 ps0 rank1
- ddr_set_t_p->retraining[4*t_count+0]=(dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xaa)))&0xff; //PptCtlStatic
- ddr_set_t_p->retraining[4*t_count+1]=(dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xaa)))>>8; //PptCtlStatic
- ddr_set_t_p->retraining[4*t_count+2]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xae)); //PptDqsCntInvTrnTg0 ps0 rank0 lane 0-3
- ddr_set_t_p->retraining[4*t_count+3]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xaf)); //PptDqsCntInvTrnTg0 ps0 rank1 lane 0-3
- }
-
-
- }
}
{
@@ -23007,9 +22635,9 @@
for (count=0;count<(DMC_DRAM_TDPD-DMC_DRAM_TMRD);) {
reg_add_offset=(DMC_DRAM_TMRD+(count));
//ddr_log_serial_puts("\n",p_dev->ddr_gloabl_message.stick_ddr_log_level);
- //ddr_log_serial_put_hex(reg_add_offset,32,p_dev->ddr_gloabl_message.stick_ddr_log_level);
+ //ddr_log_serial_put_hex(reg_add_offset,32,p_dev->ddr_gloabl_message.stick_ddr_log_level);
//ddr_log_serial_puts(": ",p_dev->ddr_gloabl_message.stick_ddr_log_level);
- //ddr_log_serial_put_hex(readl(reg_add_offset),32,p_dev->ddr_gloabl_message.stick_ddr_log_level);
+ //ddr_log_serial_put_hex(readl(reg_add_offset),32,p_dev->ddr_gloabl_message.stick_ddr_log_level);
printf("\n reg_add_offset: %08x %08x %08x ",reg_add_offset,readl(reg_add_offset),reg_add_offset);
count=count+4;
}
@@ -23019,11 +22647,11 @@
for (count=0;count<0x80;) {
reg_add_offset=0x54000+count;//dwc_ddrphy_apb_wr(0x54008,0x1001);
//ddr_log_serial_puts("\n",p_dev->ddr_gloabl_message.stick_ddr_log_level);
- //ddr_log_serial_put_hex(count,32,p_dev->ddr_gloabl_message.stick_ddr_log_level);
+ //ddr_log_serial_put_hex(count,32,p_dev->ddr_gloabl_message.stick_ddr_log_level);
//ddr_log_serial_puts(": ",p_dev->ddr_gloabl_message.stick_ddr_log_level);
reg_value= ((*(volatile uint16_t *)((uint64_t)(((0x54000+(count>>1))) << 1)+0xfe000000))>>(((count)%2)?8:0));//dwc_ddrphy_apb_rd(0x54000+add_offset+1);
reg_value=reg_value&0xff;
- //ddr_log_serial_put_hex(reg_value,32,p_dev->ddr_gloabl_message.stick_ddr_log_level);
+ //ddr_log_serial_put_hex(reg_value,32,p_dev->ddr_gloabl_message.stick_ddr_log_level);
printf("\n reg_add_offset: %08x %08x %08x",reg_add_offset,reg_value,((((0x54000+(count>>1))) << 1)+0xfe000000));
count=count+1;
}
@@ -23037,315 +22665,23 @@
//uint32_t loop = 0;
for (count = 0; count < loop_max; count+=4) {
// ddr_log_serial_puts("\n",p_dev->ddr_gloabl_message.stick_ddr_log_level);
- // ddr_log_serial_put_hex(count,32,p_dev->ddr_gloabl_message.stick_ddr_log_level);
+ // ddr_log_serial_put_hex(count,32,p_dev->ddr_gloabl_message.stick_ddr_log_level);
// ddr_log_serial_puts(": ",p_dev->ddr_gloabl_message.stick_ddr_log_level);
- // ddr_log_serial_put_hex(rd_reg((uint64_t)(p_dev->p_ddrs) + count),32,p_dev->ddr_gloabl_message.stick_ddr_log_level);
+ // ddr_log_serial_put_hex(rd_reg((uint64_t)(p_dev->p_ddrs) + count),32,p_dev->ddr_gloabl_message.stick_ddr_log_level);
// count=count+4;
printf("\n reg_add_offset: %08x %08x %08x",count,rd_reg((uint64_t)(G12_DMC_STICKY_0) + count),((G12_DMC_STICKY_0) + count));
}
}
-
-{
- uint32_t loop_max = 0;
- loop_max=sizeof(ddr_set_t);
- uint32_t count = 0;
- for (count = 0; count < loop_max; ) {
- // ddr_log_serial_puts("\n",p_dev->ddr_gloabl_message.stick_ddr_log_level);
- // ddr_log_serial_put_hex(count,32,p_dev->ddr_gloabl_message.stick_ddr_log_level);
- // ddr_log_serial_puts(": ",p_dev->ddr_gloabl_message.stick_ddr_log_level);
- // ddr_log_serial_put_hex(rd_reg((uint64_t)(p_dev->p_ddrs) + count),32,p_dev->ddr_gloabl_message.stick_ddr_log_level);
- printf("\n%08x %08x",count,rd_reg((uint64_t)(ddr_set_t_p) + count));
- count=count+4;
- //printf("\n reg_add_offset: %08x %08x %08x",count,rd_reg((uint64_t)(G12_DMC_STICKY_0) + count),((G12_DMC_STICKY_0) + count));
- }
- }
// ddr_log_serial_puts("\n",p_dev->ddr_gloabl_message.stick_ddr_log_level);
}
printf("\n ");
- //ddr_set_t *ddr_set_t_p;
- //ddr_set_t_p= (ddr_set_t *)G12_DMC_STICKY_0;
- {
-
- //ddr_set_t_p->ddr_func;
- //system reserve,do not modify
- /* align8 */
-
- //unsigned long rsv_long0[2];
- /* v1 end */
-// /*
-
-
-// ddr_set_t_p->read_dqs_delay[16];
-// ddr_set_t_p->read_dq_bit_delay[72];
-// ddr_set_t_p->write_dqs_delay[16];
-// */
-// ddr_set_t_p->write_dq_bit_delay[72];
-// ddr_set_t_p->read_dqs_gate_delay[16];
-// ddr_set_t_p->soc_bit_vref[32];
-// ddr_set_t_p->dram_bit_vref[32];
- ///*
-// ddr_set_t_p->dq_dqs_delay_flag;//read_dqs read_dq,write_dqs, write_dq
-// ddr_set_t_p->dfi_mrl;
-// ddr_set_t_p->dfi_hwtmrl;
-// ddr_set_t_p->ARdPtrInitVal;
- }
- uint32_t temp_count=0;
+ ddr_set_t *ddr_set_t_p;
+ ddr_set_t_p= (ddr_set_t *)G12_DMC_STICKY_0;
{
-
-
-printf("\n.magic=0x%08x,// %d",ddr_set_t_p->magic,ddr_set_t_p->magic);
-for( temp_count=0;temp_count<4;temp_count++)
-printf("\n.fast_boot[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->fast_boot[temp_count],ddr_set_t_p->fast_boot[temp_count]);
-//printf("\n.rsv_int0=0x%08x,// %d",ddr_set_t_p->rsv_int0,ddr_set_t_p->rsv_int0);
-printf("\n.board_id=0x%08x,// %d",ddr_set_t_p->board_id,ddr_set_t_p->board_id);
-printf("\n.version=0x%08x,// %d",ddr_set_t_p->version,ddr_set_t_p->version);
-printf("\n.DramType=0x%08x,// %d",ddr_set_t_p->DramType,ddr_set_t_p->DramType);
-printf("\n.DisabledDbyte=0x%08x,// %d",ddr_set_t_p->DisabledDbyte,ddr_set_t_p->DisabledDbyte);
-printf("\n.Is2Ttiming=0x%08x,// %d",ddr_set_t_p->Is2Ttiming,ddr_set_t_p->Is2Ttiming);
-printf("\n.HdtCtrl=0x%08x,// %d",ddr_set_t_p->HdtCtrl,ddr_set_t_p->HdtCtrl);
-printf("\n.dram_rank_config=0x%08x,// %d",ddr_set_t_p->dram_rank_config,ddr_set_t_p->dram_rank_config);
-printf("\n.diagnose=0x%08x,// %d",ddr_set_t_p->diagnose,ddr_set_t_p->diagnose);
-printf("\n.imem_load_addr=0x%08x,// %d",ddr_set_t_p->imem_load_addr,ddr_set_t_p->imem_load_addr);
-printf("\n.dmem_load_addr=0x%08x,// %d",ddr_set_t_p->dmem_load_addr,ddr_set_t_p->dmem_load_addr);
-printf("\n.imem_load_size=0x%08x,// %d",ddr_set_t_p->imem_load_size,ddr_set_t_p->imem_load_size);
-printf("\n.dmem_load_size=0x%08x,// %d",ddr_set_t_p->dmem_load_size,ddr_set_t_p->dmem_load_size);
-printf("\n.ddr_base_addr=0x%08x,// %d",ddr_set_t_p->ddr_base_addr,ddr_set_t_p->ddr_base_addr);
-printf("\n.ddr_start_offset=0x%08x,// %d",ddr_set_t_p->ddr_start_offset,ddr_set_t_p->ddr_start_offset);
-printf("\n.dram_cs0_size_MB=0x%08x,// %d",ddr_set_t_p->dram_cs0_size_MB,ddr_set_t_p->dram_cs0_size_MB);
-printf("\n.dram_cs1_size_MB=0x%08x,// %d",ddr_set_t_p->dram_cs1_size_MB,ddr_set_t_p->dram_cs1_size_MB);
-printf("\n.training_SequenceCtrl[0]=0x%08x,// %d",ddr_set_t_p->training_SequenceCtrl[0],ddr_set_t_p->training_SequenceCtrl[0]);
-printf("\n.training_SequenceCtrl[1]=0x%08x,// %d",ddr_set_t_p->training_SequenceCtrl[1],ddr_set_t_p->training_SequenceCtrl[1]);
-printf("\n.phy_odt_config_rank[0]=0x%08x,// %d",ddr_set_t_p->phy_odt_config_rank[0],ddr_set_t_p->phy_odt_config_rank[0]);
-printf("\n.phy_odt_config_rank[1]=0x%08x,// %d",ddr_set_t_p->phy_odt_config_rank[1],ddr_set_t_p->phy_odt_config_rank[1]);
-printf("\n.rever1=0x%08x,// %d",ddr_set_t_p->rever1,ddr_set_t_p->rever1);
-printf("\n.rever2=0x%08x,// %d",ddr_set_t_p->rever2,ddr_set_t_p->rever2);
-// unsigned char phy_odt_config_rank[2];
-// unsigned char ddr_fast_boot_function;
-// unsigned char dqs_offset_value;
-printf("\n.dfi_odt_config=0x%08x,// %d",ddr_set_t_p->dfi_odt_config,ddr_set_t_p->dfi_odt_config);
-printf("\n.DRAMFreq[0]=0x%08x,// %d",ddr_set_t_p->DRAMFreq[0],ddr_set_t_p->DRAMFreq[0]);
-printf("\n.DRAMFreq[1]=0x%08x,// %d",ddr_set_t_p->DRAMFreq[1],ddr_set_t_p->DRAMFreq[1]);
-printf("\n.DRAMFreq[2]=0x%08x,// %d",ddr_set_t_p->DRAMFreq[2],ddr_set_t_p->DRAMFreq[2]);
-printf("\n.DRAMFreq[3]=0x%08x,// %d",ddr_set_t_p->DRAMFreq[3],ddr_set_t_p->DRAMFreq[3]);
-printf("\n.PllBypassEn=0x%08x,// %d",ddr_set_t_p->PllBypassEn,ddr_set_t_p->PllBypassEn);
-printf("\n.ddr_rdbi_wr_enable=0x%08x,// %d",ddr_set_t_p->ddr_rdbi_wr_enable,ddr_set_t_p->ddr_rdbi_wr_enable);
-printf("\n.ddr_rfc_type=0x%08x,// %d",ddr_set_t_p->ddr_rfc_type,ddr_set_t_p->ddr_rfc_type);
-printf("\n.enable_lpddr4x_mode=0x%08x,// %d",ddr_set_t_p->enable_lpddr4x_mode,ddr_set_t_p->enable_lpddr4x_mode);
-printf("\n.pll_ssc_mode=0x%08x,// %d",ddr_set_t_p->pll_ssc_mode,ddr_set_t_p->pll_ssc_mode);
-printf("\n.clk_drv_ohm=0x%08x,// %d",ddr_set_t_p->clk_drv_ohm,ddr_set_t_p->clk_drv_ohm);
-printf("\n.cs_drv_ohm=0x%08x,// %d",ddr_set_t_p->cs_drv_ohm,ddr_set_t_p->cs_drv_ohm);
-printf("\n.ac_drv_ohm=0x%08x,// %d",ddr_set_t_p->ac_drv_ohm,ddr_set_t_p->ac_drv_ohm);
-printf("\n.soc_data_drv_ohm_p=0x%08x,// %d",ddr_set_t_p->soc_data_drv_ohm_p,ddr_set_t_p->soc_data_drv_ohm_p);
-printf("\n.soc_data_drv_ohm_n=0x%08x,// %d",ddr_set_t_p->soc_data_drv_ohm_n,ddr_set_t_p->soc_data_drv_ohm_n);
-printf("\n.soc_data_odt_ohm_p=0x%08x,// %d",ddr_set_t_p->soc_data_odt_ohm_p,ddr_set_t_p->soc_data_odt_ohm_p);
-printf("\n.soc_data_odt_ohm_n=0x%08x,// %d",ddr_set_t_p->soc_data_odt_ohm_n,ddr_set_t_p->soc_data_odt_ohm_n);
-printf("\n.dram_data_drv_ohm=0x%08x,// %d",ddr_set_t_p->dram_data_drv_ohm,ddr_set_t_p->dram_data_drv_ohm);
-printf("\n.dram_data_odt_ohm=0x%08x,// %d",ddr_set_t_p->dram_data_odt_ohm,ddr_set_t_p->dram_data_odt_ohm);
-printf("\n.dram_ac_odt_ohm=0x%08x,// %d",ddr_set_t_p->dram_ac_odt_ohm,ddr_set_t_p->dram_ac_odt_ohm);
-printf("\n.soc_clk_slew_rate=0x%08x,// %d",ddr_set_t_p->soc_clk_slew_rate,ddr_set_t_p->soc_clk_slew_rate);
-printf("\n.soc_cs_slew_rate=0x%08x,// %d",ddr_set_t_p->soc_cs_slew_rate,ddr_set_t_p->soc_cs_slew_rate);
-printf("\n.soc_ac_slew_rate=0x%08x,// %d",ddr_set_t_p->soc_ac_slew_rate,ddr_set_t_p->soc_ac_slew_rate);
-printf("\n.soc_data_slew_rate=0x%08x,// %d",ddr_set_t_p->soc_data_slew_rate,ddr_set_t_p->soc_data_slew_rate);
-printf("\n.vref_output_permil =0x%08x,// %d",ddr_set_t_p->vref_output_permil ,ddr_set_t_p->vref_output_permil );
-printf("\n.vref_receiver_permil =0x%08x,// %d",ddr_set_t_p->vref_receiver_permil ,ddr_set_t_p->vref_receiver_permil );
-printf("\n.vref_dram_permil=0x%08x,// %d",ddr_set_t_p->vref_dram_permil,ddr_set_t_p->vref_dram_permil);
-printf("\n.max_core_timmming_frequency=0x%08x,// %d",ddr_set_t_p->max_core_timmming_frequency,ddr_set_t_p->max_core_timmming_frequency);
-printf("\n.ac_trace_delay[0]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[0],ddr_set_t_p->ac_trace_delay[0]);
-printf("\n.ac_trace_delay[1]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[1],ddr_set_t_p->ac_trace_delay[1]);
-printf("\n.ac_trace_delay[2]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[2],ddr_set_t_p->ac_trace_delay[2]);
-printf("\n.ac_trace_delay[3]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[3],ddr_set_t_p->ac_trace_delay[3]);
-printf("\n.ac_trace_delay[4]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[4],ddr_set_t_p->ac_trace_delay[4]);
-printf("\n.ac_trace_delay[5]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[5],ddr_set_t_p->ac_trace_delay[5]);
-printf("\n.ac_trace_delay[6]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[6],ddr_set_t_p->ac_trace_delay[6]);
-printf("\n.ac_trace_delay[7]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[7],ddr_set_t_p->ac_trace_delay[7]);
-printf("\n.ac_trace_delay[8]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[8],ddr_set_t_p->ac_trace_delay[8]);
-printf("\n.ac_trace_delay[9]=0x%08x,// %d",ddr_set_t_p->ac_trace_delay[9],ddr_set_t_p->ac_trace_delay[9]);
-printf("\n.lpddr4_dram_vout_voltage_1_3_2_5_setting=0x%08x,// %d",ddr_set_t_p->lpddr4_dram_vout_voltage_1_3_2_5_setting,ddr_set_t_p->lpddr4_dram_vout_voltage_1_3_2_5_setting);
-printf("\n.lpddr4_x8_mode=0x%08x,// %d",ddr_set_t_p->lpddr4_x8_mode,ddr_set_t_p->lpddr4_x8_mode);
-printf("\n.ac_pinmux[0]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[0],ddr_set_t_p->ac_pinmux[0]);
-printf("\n.ac_pinmux[1]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[1],ddr_set_t_p->ac_pinmux[1]);
-printf("\n.ac_pinmux[2]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[2],ddr_set_t_p->ac_pinmux[2]);
-printf("\n.ac_pinmux[3]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[3],ddr_set_t_p->ac_pinmux[3]);
-printf("\n.ac_pinmux[4]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[4],ddr_set_t_p->ac_pinmux[4]);
-printf("\n.ac_pinmux[5]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[5],ddr_set_t_p->ac_pinmux[5]);
-printf("\n.ac_pinmux[6]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[6],ddr_set_t_p->ac_pinmux[6]);
-printf("\n.ac_pinmux[7]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[7],ddr_set_t_p->ac_pinmux[7]);
-printf("\n.ac_pinmux[8]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[8],ddr_set_t_p->ac_pinmux[8]);
-printf("\n.ac_pinmux[9]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[9],ddr_set_t_p->ac_pinmux[9]);
-printf("\n.ac_pinmux[10]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[10],ddr_set_t_p->ac_pinmux[10]);
-printf("\n.ac_pinmux[11]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[11],ddr_set_t_p->ac_pinmux[11]);
-printf("\n.ac_pinmux[12]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[12],ddr_set_t_p->ac_pinmux[12]);
-printf("\n.ac_pinmux[13]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[13],ddr_set_t_p->ac_pinmux[13]);
-printf("\n.ac_pinmux[14]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[14],ddr_set_t_p->ac_pinmux[14]);
-printf("\n.ac_pinmux[15]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[15],ddr_set_t_p->ac_pinmux[15]);
-printf("\n.ac_pinmux[16]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[16],ddr_set_t_p->ac_pinmux[16]);
-printf("\n.ac_pinmux[17]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[17],ddr_set_t_p->ac_pinmux[17]);
-printf("\n.ac_pinmux[18]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[18],ddr_set_t_p->ac_pinmux[18]);
-printf("\n.ac_pinmux[19]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[19],ddr_set_t_p->ac_pinmux[19]);
-printf("\n.ac_pinmux[20]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[20],ddr_set_t_p->ac_pinmux[20]);
-printf("\n.ac_pinmux[21]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[21],ddr_set_t_p->ac_pinmux[21]);
-printf("\n.ac_pinmux[22]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[22],ddr_set_t_p->ac_pinmux[22]);
-printf("\n.ac_pinmux[23]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[23],ddr_set_t_p->ac_pinmux[23]);
-printf("\n.ac_pinmux[24]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[24],ddr_set_t_p->ac_pinmux[24]);
-printf("\n.ac_pinmux[25]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[25],ddr_set_t_p->ac_pinmux[25]);
-printf("\n.ac_pinmux[26]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[26],ddr_set_t_p->ac_pinmux[26]);
-printf("\n.ac_pinmux[27]=0x%08x,// %d",ddr_set_t_p->ac_pinmux[27],ddr_set_t_p->ac_pinmux[27]);
-printf("\n.dfi_pinmux[0]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[0],ddr_set_t_p->dfi_pinmux[0]);
-printf("\n.dfi_pinmux[1]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[1],ddr_set_t_p->dfi_pinmux[1]);
-printf("\n.dfi_pinmux[2]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[2],ddr_set_t_p->dfi_pinmux[2]);
-printf("\n.dfi_pinmux[3]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[3],ddr_set_t_p->dfi_pinmux[3]);
-printf("\n.dfi_pinmux[4]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[4],ddr_set_t_p->dfi_pinmux[4]);
-printf("\n.dfi_pinmux[5]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[5],ddr_set_t_p->dfi_pinmux[5]);
-printf("\n.dfi_pinmux[6]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[6],ddr_set_t_p->dfi_pinmux[6]);
-printf("\n.dfi_pinmux[7]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[7],ddr_set_t_p->dfi_pinmux[7]);
-printf("\n.dfi_pinmux[8]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[8],ddr_set_t_p->dfi_pinmux[8]);
-printf("\n.dfi_pinmux[9]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[9],ddr_set_t_p->dfi_pinmux[9]);
-printf("\n.dfi_pinmux[10]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[10],ddr_set_t_p->dfi_pinmux[10]);
-printf("\n.dfi_pinmux[11]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[11],ddr_set_t_p->dfi_pinmux[11]);
-printf("\n.dfi_pinmux[12]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[12],ddr_set_t_p->dfi_pinmux[12]);
-printf("\n.dfi_pinmux[13]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[13],ddr_set_t_p->dfi_pinmux[13]);
-printf("\n.dfi_pinmux[14]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[14],ddr_set_t_p->dfi_pinmux[14]);
-printf("\n.dfi_pinmux[15]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[15],ddr_set_t_p->dfi_pinmux[15]);
-printf("\n.dfi_pinmux[16]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[16],ddr_set_t_p->dfi_pinmux[16]);
-printf("\n.dfi_pinmux[17]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[17],ddr_set_t_p->dfi_pinmux[17]);
-printf("\n.dfi_pinmux[18]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[18],ddr_set_t_p->dfi_pinmux[18]);
-printf("\n.dfi_pinmux[19]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[19],ddr_set_t_p->dfi_pinmux[19]);
-printf("\n.dfi_pinmux[20]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[20],ddr_set_t_p->dfi_pinmux[20]);
-printf("\n.dfi_pinmux[21]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[21],ddr_set_t_p->dfi_pinmux[21]);
-printf("\n.dfi_pinmux[22]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[22],ddr_set_t_p->dfi_pinmux[22]);
-printf("\n.dfi_pinmux[23]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[23],ddr_set_t_p->dfi_pinmux[23]);
-printf("\n.dfi_pinmux[24]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[24],ddr_set_t_p->dfi_pinmux[24]);
-printf("\n.dfi_pinmux[25]=0x%08x,// %d",ddr_set_t_p->dfi_pinmux[25],ddr_set_t_p->dfi_pinmux[25]);
-printf("\n.slt_test_function[0] =0x%08x,// %d",ddr_set_t_p->slt_test_function[0] ,ddr_set_t_p->slt_test_function[0] );
-printf("\n.slt_test_function[1] =0x%08x,// %d",ddr_set_t_p->slt_test_function[1] ,ddr_set_t_p->slt_test_function[1] );
-printf("\n.tdqs2dq=0x%08x,// %d",ddr_set_t_p->tdqs2dq,ddr_set_t_p->tdqs2dq);
-printf("\n.dram_data_wr_odt_ohm=0x%08x,// %d",ddr_set_t_p->dram_data_wr_odt_ohm,ddr_set_t_p->dram_data_wr_odt_ohm);
-printf("\n.bitTimeControl_2d=0x%08x,// %d",ddr_set_t_p->bitTimeControl_2d,ddr_set_t_p->bitTimeControl_2d);
-printf("\n.ddr_dmc_remap[0]=0x%08x,// %d",ddr_set_t_p->ddr_dmc_remap[0],ddr_set_t_p->ddr_dmc_remap[0]);
-printf("\n.ddr_dmc_remap[1]=0x%08x,// %d",ddr_set_t_p->ddr_dmc_remap[1],ddr_set_t_p->ddr_dmc_remap[1]);
-printf("\n.ddr_dmc_remap[2]=0x%08x,// %d",ddr_set_t_p->ddr_dmc_remap[2],ddr_set_t_p->ddr_dmc_remap[2]);
-printf("\n.ddr_dmc_remap[3]=0x%08x,// %d",ddr_set_t_p->ddr_dmc_remap[3],ddr_set_t_p->ddr_dmc_remap[3]);
-printf("\n.ddr_dmc_remap[4]=0x%08x,// %d",ddr_set_t_p->ddr_dmc_remap[4],ddr_set_t_p->ddr_dmc_remap[4]);
-printf("\n.ddr_lpddr34_ca_remap[0]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_ca_remap[0],ddr_set_t_p->ddr_lpddr34_ca_remap[0]);
-printf("\n.ddr_lpddr34_ca_remap[1]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_ca_remap[1],ddr_set_t_p->ddr_lpddr34_ca_remap[1]);
-printf("\n.ddr_lpddr34_ca_remap[2]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_ca_remap[2],ddr_set_t_p->ddr_lpddr34_ca_remap[2]);
-printf("\n.ddr_lpddr34_ca_remap[3]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_ca_remap[3],ddr_set_t_p->ddr_lpddr34_ca_remap[3]);
-printf("\n.ddr_lpddr34_dq_remap[0]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[0],ddr_set_t_p->ddr_lpddr34_dq_remap[0]);
-printf("\n.ddr_lpddr34_dq_remap[1]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[1],ddr_set_t_p->ddr_lpddr34_dq_remap[1]);
-printf("\n.ddr_lpddr34_dq_remap[2]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[2],ddr_set_t_p->ddr_lpddr34_dq_remap[2]);
-printf("\n.ddr_lpddr34_dq_remap[3]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[3],ddr_set_t_p->ddr_lpddr34_dq_remap[3]);
-printf("\n.ddr_lpddr34_dq_remap[4]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[4],ddr_set_t_p->ddr_lpddr34_dq_remap[4]);
-printf("\n.ddr_lpddr34_dq_remap[5]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[5],ddr_set_t_p->ddr_lpddr34_dq_remap[5]);
-printf("\n.ddr_lpddr34_dq_remap[6]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[6],ddr_set_t_p->ddr_lpddr34_dq_remap[6]);
-printf("\n.ddr_lpddr34_dq_remap[7]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[7],ddr_set_t_p->ddr_lpddr34_dq_remap[7]);
-printf("\n.ddr_lpddr34_dq_remap[8]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[8],ddr_set_t_p->ddr_lpddr34_dq_remap[8]);
-printf("\n.ddr_lpddr34_dq_remap[9]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[9],ddr_set_t_p->ddr_lpddr34_dq_remap[9]);
-printf("\n.ddr_lpddr34_dq_remap[10]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[10],ddr_set_t_p->ddr_lpddr34_dq_remap[10]);
-printf("\n.ddr_lpddr34_dq_remap[11]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[11],ddr_set_t_p->ddr_lpddr34_dq_remap[11]);
-printf("\n.ddr_lpddr34_dq_remap[12]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[12],ddr_set_t_p->ddr_lpddr34_dq_remap[12]);
-printf("\n.ddr_lpddr34_dq_remap[13]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[13],ddr_set_t_p->ddr_lpddr34_dq_remap[13]);
-printf("\n.ddr_lpddr34_dq_remap[14]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[14],ddr_set_t_p->ddr_lpddr34_dq_remap[14]);
-printf("\n.ddr_lpddr34_dq_remap[15]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[15],ddr_set_t_p->ddr_lpddr34_dq_remap[15]);
-printf("\n.ddr_lpddr34_dq_remap[16]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[16],ddr_set_t_p->ddr_lpddr34_dq_remap[16]);
-printf("\n.ddr_lpddr34_dq_remap[17]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[17],ddr_set_t_p->ddr_lpddr34_dq_remap[17]);
-printf("\n.ddr_lpddr34_dq_remap[18]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[18],ddr_set_t_p->ddr_lpddr34_dq_remap[18]);
-printf("\n.ddr_lpddr34_dq_remap[19]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[19],ddr_set_t_p->ddr_lpddr34_dq_remap[19]);
-printf("\n.ddr_lpddr34_dq_remap[20]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[20],ddr_set_t_p->ddr_lpddr34_dq_remap[20]);
-printf("\n.ddr_lpddr34_dq_remap[21]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[21],ddr_set_t_p->ddr_lpddr34_dq_remap[21]);
-printf("\n.ddr_lpddr34_dq_remap[22]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[22],ddr_set_t_p->ddr_lpddr34_dq_remap[22]);
-printf("\n.ddr_lpddr34_dq_remap[23]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[23],ddr_set_t_p->ddr_lpddr34_dq_remap[23]);
-printf("\n.ddr_lpddr34_dq_remap[24]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[24],ddr_set_t_p->ddr_lpddr34_dq_remap[24]);
-printf("\n.ddr_lpddr34_dq_remap[25]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[25],ddr_set_t_p->ddr_lpddr34_dq_remap[25]);
-printf("\n.ddr_lpddr34_dq_remap[26]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[26],ddr_set_t_p->ddr_lpddr34_dq_remap[26]);
-printf("\n.ddr_lpddr34_dq_remap[27]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[27],ddr_set_t_p->ddr_lpddr34_dq_remap[27]);
-printf("\n.ddr_lpddr34_dq_remap[28]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[28],ddr_set_t_p->ddr_lpddr34_dq_remap[28]);
-printf("\n.ddr_lpddr34_dq_remap[29]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[29],ddr_set_t_p->ddr_lpddr34_dq_remap[29]);
-printf("\n.ddr_lpddr34_dq_remap[30]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[30],ddr_set_t_p->ddr_lpddr34_dq_remap[30]);
-printf("\n.ddr_lpddr34_dq_remap[31]=0x%08x,// %d",ddr_set_t_p->ddr_lpddr34_dq_remap[31],ddr_set_t_p->ddr_lpddr34_dq_remap[31]);
-printf("\n.dram_rtt_nom_wr_park[0]=0x%08x,// %d",ddr_set_t_p->dram_rtt_nom_wr_park[0],ddr_set_t_p->dram_rtt_nom_wr_park[0]);
-printf("\n.dram_rtt_nom_wr_park[1]=0x%08x,// %d",ddr_set_t_p->dram_rtt_nom_wr_park[1],ddr_set_t_p->dram_rtt_nom_wr_park[1]);
-printf("\n.ddr_func=0x%08x,// %d",ddr_set_t_p->ddr_func,ddr_set_t_p->ddr_func);
-
-/*
-printf("\n.read_dqs_delay[0]=0x%08x,// %d",ddr_set_t_p->read_dqs_delay[0],ddr_set_t_p->read_dqs_delay[0]);
-printf("\n.read_dqs_delay[1]=0x%08x,// %d",ddr_set_t_p->read_dqs_delay[1],ddr_set_t_p->read_dqs_delay[1]);
-printf("\n.read_dqs_delay[2]=0x%08x,// %d",ddr_set_t_p->read_dqs_delay[2],ddr_set_t_p->read_dqs_delay[2]);
-printf("\n.read_dqs_delay[3]=0x%08x,// %d",ddr_set_t_p->read_dqs_delay[3],ddr_set_t_p->read_dqs_delay[3]);
-printf("\n.read_dqs_delay[4]=0x%08x,// %d",ddr_set_t_p->read_dqs_delay[4],ddr_set_t_p->read_dqs_delay[4]);
-printf("\n.read_dqs_delay[5]=0x%08x,// %d",ddr_set_t_p->read_dqs_delay[5],ddr_set_t_p->read_dqs_delay[5]);
-printf("\n.read_dqs_delay[6]=0x%08x,// %d",ddr_set_t_p->read_dqs_delay[6],ddr_set_t_p->read_dqs_delay[6]);
-printf("\n.read_dqs_delay[7]=0x%08x,// %d",ddr_set_t_p->read_dqs_delay[7],ddr_set_t_p->read_dqs_delay[7]);
-printf("\n.read_dqs_delay[8]=0x%08x,// %d",ddr_set_t_p->read_dqs_delay[8],ddr_set_t_p->read_dqs_delay[8]);
-printf("\n.read_dqs_delay[9]=0x%08x,// %d",ddr_set_t_p->read_dqs_delay[9],ddr_set_t_p->read_dqs_delay[9]);
-printf("\n.read_dqs_delay[10]=0x%08x,// %d",ddr_set_t_p->read_dqs_delay[10],ddr_set_t_p->read_dqs_delay[10]);
-printf("\n.read_dqs_delay[11]=0x%08x,// %d",ddr_set_t_p->read_dqs_delay[11],ddr_set_t_p->read_dqs_delay[11]);
-printf("\n.read_dqs_delay[12]=0x%08x,// %d",ddr_set_t_p->read_dqs_delay[12],ddr_set_t_p->read_dqs_delay[12]);
-printf("\n.read_dqs_delay[13]=0x%08x,// %d",ddr_set_t_p->read_dqs_delay[13],ddr_set_t_p->read_dqs_delay[13]);
-printf("\n.read_dqs_delay[14]=0x%08x,// %d",ddr_set_t_p->read_dqs_delay[14],ddr_set_t_p->read_dqs_delay[14]);
-printf("\n.read_dqs_delay[15]=0x%08x,// %d",ddr_set_t_p->read_dqs_delay[15],ddr_set_t_p->read_dqs_delay[15]);
-printf("\n.read_dq_bit_delay[72]=0x%08x,// %d",ddr_set_t_p->read_dq_bit_delay[72],ddr_set_t_p->read_dq_bit_delay[72]);
-printf("\n.write_dqs_delay[16]=0x%08x,// %d",ddr_set_t_p->write_dqs_delay[16],ddr_set_t_p->write_dqs_delay[16]);
-printf("\n.write_dq_bit_delay[72]=0x%08x,// %d",ddr_set_t_p->write_dq_bit_delay[72],ddr_set_t_p->write_dq_bit_delay[72]);
-printf("\n.read_dqs_gate_delay[16]=0x%08x,// %d",ddr_set_t_p->read_dqs_gate_delay[16],ddr_set_t_p->read_dqs_gate_delay[16]);
-printf("\n.soc_bit_vref[32]=0x%08x,// %d",ddr_set_t_p->soc_bit_vref[32],ddr_set_t_p->soc_bit_vref[32]);
-printf("\n.dram_bit_vref[32]=0x%08x,// %d",ddr_set_t_p->dram_bit_vref[32],ddr_set_t_p->dram_bit_vref[32]);
-printf("\n.dq_dqs_delay_flag=0x%08x,// %d",ddr_set_t_p->dq_dqs_delay_flag,ddr_set_t_p->dq_dqs_delay_flag);
-printf("\n.dfi_mrl=0x%08x,// %d",ddr_set_t_p->dfi_mrl,ddr_set_t_p->dfi_mrl);
-printf("\n.dfi_hwtmrl=0x%08x,// %d",ddr_set_t_p->dfi_hwtmrl,ddr_set_t_p->dfi_hwtmrl);
-printf("\n.ARdPtrInitVal=0x%08x,// %d",ddr_set_t_p->ARdPtrInitVal,ddr_set_t_p->ARdPtrInitVal);
-
-
-*/
-
-
-//printf("\n.read_dq_bit_delay[72]=%d,",ddr_set_t_p->read_dq_bit_delay[72]);
-//printf("\n.write_dqs_delay[16]=%d,",ddr_set_t_p->write_dqs_delay[16]);
-//printf("\n.write_dq_bit_delay[72]=%d,",ddr_set_t_p->write_dq_bit_delay[72]);
-//printf("\n.read_dqs_gate_delay[16]=%d,",ddr_set_t_p->read_dqs_gate_delay[16]);
-//printf("\n.soc_bit_vref[32]=%d,",ddr_set_t_p->soc_bit_vref[32]);
-//printf("\n.dram_bit_vref[32]=%d,",ddr_set_t_p->dram_bit_vref[32]);
-//printf("\n.dq_dqs_delay_flag=%d,",ddr_set_t_p->dq_dqs_delay_flag);
-//printf("\n.dfi_mrl=%d,",ddr_set_t_p->dfi_mrl);
-//printf("\n.dfi_hwtmrl=%d,",ddr_set_t_p->dfi_hwtmrl);
-//printf("\n.ARdPtrInitVal=%d,",ddr_set_t_p->ARdPtrInitVal);
-
-for( temp_count=0;temp_count<16;temp_count++)
-printf("\n.read_dqs_delay[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->read_dqs_delay[temp_count],ddr_set_t_p->read_dqs_delay[temp_count]);
-for( temp_count=0;temp_count<72;temp_count++)
-printf("\n.read_dq_bit_delay[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->read_dq_bit_delay[temp_count],ddr_set_t_p->read_dq_bit_delay[temp_count]);
-for( temp_count=0;temp_count<16;temp_count++)
-//printf("\n.write_dqs_delay[%d]=%d,",temp_count,ddr_set_t_p->write_dqs_delay[temp_count]);
-printf("\n.write_dqs_delay[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->write_dqs_delay[temp_count],ddr_set_t_p->write_dqs_delay[temp_count]);
-for( temp_count=0;temp_count<72;temp_count++)
-//printf("\n.write_dq_bit_delay[%d]=%d,",temp_count,ddr_set_t_p->write_dq_bit_delay[temp_count]);
-printf("\n.write_dq_bit_delay[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->write_dq_bit_delay[temp_count],ddr_set_t_p->write_dq_bit_delay[temp_count]);
-for( temp_count=0;temp_count<16;temp_count++)
-//printf("\n.read_dqs_gate_delay[%d]=%d,",temp_count,ddr_set_t_p->read_dqs_gate_delay[temp_count]);
-printf("\n.read_dqs_gate_delay[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->read_dqs_gate_delay[temp_count],ddr_set_t_p->read_dqs_gate_delay[temp_count]);
-for( temp_count=0;temp_count<32;temp_count++)
-//printf("\n.soc_bit_vref[%d]=%d,",temp_count,ddr_set_t_p->soc_bit_vref[temp_count]);
-printf("\n.soc_bit_vref[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->soc_bit_vref[temp_count],ddr_set_t_p->soc_bit_vref[temp_count]);
-for( temp_count=0;temp_count<32;temp_count++)
-//printf("\n.dram_bit_vref[%d]=%d,",temp_count,ddr_set_t_p->dram_bit_vref[temp_count]);
-printf("\n.dram_bit_vref[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->dram_bit_vref[temp_count],ddr_set_t_p->dram_bit_vref[temp_count]);
-
-//ddr_set_t_p->dq_dqs_delay_flag=0xff;
-printf("\n.rever3=0x%08x,// %d",ddr_set_t_p->rever3,ddr_set_t_p->rever3);
-printf("\n.dfi_mrl=0x%08x,// %d",ddr_set_t_p->dfi_mrl,ddr_set_t_p->dfi_mrl);
-printf("\n.dfi_hwtmrl=0x%08x,// %d",ddr_set_t_p->dfi_hwtmrl,ddr_set_t_p->dfi_hwtmrl);
-printf("\n.ARdPtrInitVal=0x%08x,// %d",ddr_set_t_p->ARdPtrInitVal,ddr_set_t_p->ARdPtrInitVal);
-
-for( temp_count=0;temp_count<16;temp_count++)
-//printf("\n.dram_bit_vref[%d]=%d,",temp_count,ddr_set_t_p->dram_bit_vref[temp_count]);
-printf("\n.retraining[%d]=0x%08x,// %d",temp_count,ddr_set_t_p->retraining[temp_count],ddr_set_t_p->retraining[temp_count]);
-
-
-printf("\n");
-/*
printf("\nddr_set_t_p->magic:%08x",ddr_set_t_p->magic);
printf("\nddr_set_t_p->rsv_int0:%08x",ddr_set_t_p->rsv_int0);
printf("\nddr_set_t_p->board_id:%08x",ddr_set_t_p->board_id);
@@ -23397,7 +22733,7 @@
printf("\nddr_set_t_p->vref_output_permil:%08x",ddr_set_t_p->vref_output_permil);
printf("\nddr_set_t_p->vref_receiver_permil:%08x",ddr_set_t_p->vref_receiver_permil);
printf("\nddr_set_t_p->vref_dram_permil:%08x",ddr_set_t_p->vref_dram_permil);
- printf("\nddr_set_t_p->max_core_timmming_frequency:%08x",ddr_set_t_p->max_core_timmming_frequency);
+ printf("\nddr_set_t_p->vref_reverse:%08x",ddr_set_t_p->vref_reverse);
printf("\nddr_set_t_p->ac_trace_delay[0]:%08x",ddr_set_t_p->ac_trace_delay[0]);
printf("\nddr_set_t_p->ac_trace_delay[1]:%08x",ddr_set_t_p->ac_trace_delay[1]);
printf("\nddr_set_t_p->ac_trace_delay[2]:%08x",ddr_set_t_p->ac_trace_delay[2]);
@@ -23408,14 +22744,13 @@
printf("\nddr_set_t_p->ac_trace_delay[7]:%08x",ddr_set_t_p->ac_trace_delay[7]);
printf("\nddr_set_t_p->ac_trace_delay[8]:%08x",ddr_set_t_p->ac_trace_delay[8]);
printf("\nddr_set_t_p->ac_trace_delay[9]:%08x",ddr_set_t_p->ac_trace_delay[9]);
- printf("\nddr_set_t_p->lpddr4_dram_vout_voltage_1_3_2_5_setting:%08x",ddr_set_t_p->lpddr4_dram_vout_voltage_1_3_2_5_setting);
- printf("\nddr_set_t_p->lpddr4_x8_mode:%08x",ddr_set_t_p->lpddr4_x8_mode);
+ printf("\nddr_set_t_p->ac_trace_delay[10]:%08x",ddr_set_t_p->ac_trace_delay[10]);
+ printf("\nddr_set_t_p->ac_trace_delay[11]:%08x",ddr_set_t_p->ac_trace_delay[11]);
//printf("\nddr_set_t_p->ac_pinmux[26]:%08x",ddr_set_t_p->ac_pinmux[26]);
//printf("\nddr_set_t_p->dfi_pinmux[28]:%08x",ddr_set_t_p->dfi_pinmux[28]);
//printf("\nddr_set_t_p->slt_test_function[2]:%08x",ddr_set_t_p->slt_test_function[2]);
printf("\nddr_set_t_p->dq_bdlr_org:%08x",ddr_set_t_p->dq_bdlr_org);
- printf("\nddr_set_t_p->dram_data_wr_odt_ohm:%08x",ddr_set_t_p->dram_data_wr_odt_ohm);
- printf("\nddr_set_t_p->bitTimeControl_2d:%08x",ddr_set_t_p->bitTimeControl_2d);
+ //printf("\nddr_set_t_p->rsv_char1[2]:%08x",ddr_set_t_p->rsv_char1[2]);
printf("\nddr_set_t_p->ddr_dmc_remap[0]:%08x",ddr_set_t_p->ddr_dmc_remap[0]);
printf("\nddr_set_t_p->ddr_dmc_remap[1]:%08x",ddr_set_t_p->ddr_dmc_remap[1]);
printf("\nddr_set_t_p->ddr_dmc_remap[2]:%08x",ddr_set_t_p->ddr_dmc_remap[2]);
@@ -23463,7 +22798,7 @@
//printf("\nddr_set_t_p->rsv_long0[2]:%08x",ddr_set_t_p->rsv_long0[2]);
//printf("\nddr_set_t_p->dqs_adjust[16]:%08x",ddr_set_t_p->dqs_adjust[16]);
//printf("\nddr_set_t_p->dq_bit_delay[72]:%08x",ddr_set_t_p->dq_bit_delay[72]);
-*/
+
}
@@ -23472,280 +22807,6 @@
}
-
-
-int do_ddr_fastboot_config(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-
- int i=0;
- int count=0;
- char *endp;
- unsigned int enable_ddr_fast_boot=0; // 0 pause 1,resume
-
- printf("\nargc== 0x%08x\n", argc);
- for (i = 0;i<argc;i++)
- printf("\nargv[%d]=%s\n",i,argv[i]);
- if (argc == 1)
- printf("\nplease read help\n");
- else if (argc > 1)
- {
- count=0;
- enable_ddr_fast_boot= simple_strtoull_ddr(argv[count+1], &endp, 0);
- if (*argv[count+1] == 0 || *endp != 0)
- {
- enable_ddr_fast_boot = 0;
- }
- // count++;
- }
- if(!enable_ddr_fast_boot)
- return 1;
- ddr_set_t *ddr_set_t_p=NULL;
- ddr_set_t_p=(ddr_set_t *)(ddr_set_t_p_arrary);
- //ddr_set_t_p= (ddr_set_t *)G12_DMC_STICKY_0;
- //if (sizeof(ddr_set_t)<loop_max)
- uint32_t ddr_set_add=0;
- uint32_t ddr_set_size=0;
- ddr_set_add=(uint32_t)(uint64_t)(ddr_set_t_p);
- ddr_set_size=sizeof(ddr_set_t);
- printf("\nddr_set_t_p==0x%08x\n",ddr_set_add);
- uint32_t loop=0;
- uint32_t loop_max = (4+(0x3f<<2));//((DMC_STICKY_63-DMC_STICKY_0));
- // loop_max=sizeof(ddr_set_t);
- for (loop = 0; loop <loop_max; loop+=4) {
- wr_reg(((uint64_t)(ddr_set_t_p) + loop), rd_reg(G12_DMC_STICKY_0 + loop));
- }
-
-
-{
- uint16_t dq_bit_delay[72];
- unsigned char t_count=0;
- uint16_t delay_org=0;
- uint16_t delay_temp=0;
- uint32_t add_offset=0;
- dwc_ddrphy_apb_wr(0xd0000,0x0);
-
-char dmc_test_worst_window_rx=0;
- char dmc_test_worst_window_tx=0;
-
-{
- dwc_ddrphy_apb_wr((0<<20)|(0xd<<16)|(0<<12)|(0x0),0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
-
- dmc_test_worst_window_tx=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(0<<12)|(0x0c2));
- dmc_test_worst_window_rx=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(0<<12)|(0x0c3));
- if(dmc_test_worst_window_tx>30)
- dmc_test_worst_window_tx=30;
- if(dmc_test_worst_window_rx>30)
- dmc_test_worst_window_rx=30;
-// dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(0<<12)|(0x1c2),t4_write_worst_margin_rank1);
-// dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(0<<12)|(0x1c3),t4_read_worst_margin_rank1);
-ddr_set_t_p->fast_boot[1]=(((dmc_test_worst_window_tx/2)<<4))|(((dmc_test_worst_window_rx/2)));
- }
-
-
- {
-
-
-
- // printf("\n ARdPtrInitVal");
- add_offset=((0<<20)|(0<<16)|(0<<12)|(0x2e));
- delay_org=dwc_ddrphy_apb_rd(add_offset);
- ddr_set_t_p->ARdPtrInitVal=delay_org;
- // printf("\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
-
- // printf("\n dfimrl0 dfimrl1 dfimrl2 dfimrl3 HwtMRL");
- add_offset=((0<<20)|(1<<16)|(0<<12)|(0x20));
- delay_org=dwc_ddrphy_apb_rd(add_offset);
- ddr_set_t_p->dfi_mrl=delay_org;
- // printf("\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
- add_offset=((0<<20)|(1<<16)|(1<<12)|(0x20));
- delay_org=dwc_ddrphy_apb_rd(add_offset);
- // printf("\n t_count: %04d %04d %08x %08x",1,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
- add_offset=((0<<20)|(1<<16)|(2<<12)|(0x20));
- delay_org=dwc_ddrphy_apb_rd(add_offset);
- // printf("\n t_count: %04d %04d %08x %08x",2,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
- add_offset=((0<<20)|(1<<16)|(3<<12)|(0x20));
- delay_org=dwc_ddrphy_apb_rd(add_offset);
- // printf("\n t_count: %04d %04d %08x %08x",3,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
- add_offset=((0<<20)|(2<<16)|(0<<12)|(0x20));
- delay_org=dwc_ddrphy_apb_rd(add_offset);
-
- ddr_set_t_p->dfi_hwtmrl=delay_org;
- // printf("\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
- }
- {
- // printf("\n count_index delay_value register_add register_value \n ");
- // printf("\n address delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6 is coarse --step==1UI",ui_1_32_100step);
- for(t_count=0;t_count<10;t_count++)
- {
- add_offset=((0<<20)|(0<<16)|(t_count<<12)|(0x80));
- dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
- delay_org=dq_bit_delay[t_count];
- delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
- ddr_set_t_p->ac_trace_delay[t_count]=delay_temp;
- // printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
- }
- }
- {
- // printf("\n tdqs delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6-9 is coarse --step==1UI",ui_1_32_100step);
- for(t_count=0;t_count<16;t_count++)
- {
- add_offset=((0<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0xd0+(t_count/8)+((t_count%2)<<8)));
- dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
- delay_org=dq_bit_delay[t_count];
- delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
-
- ddr_set_t_p->write_dqs_delay[t_count]=delay_temp;
-
- // printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
- }
- }
- {
- // printf("\n rxdqs delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI,no coarse",ui_1_32_100step);
- for(t_count=0;t_count<16;t_count++)
- {
- add_offset=((0<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0x8c+(t_count/8)+((t_count%2)<<8)));
- dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
- delay_org=dq_bit_delay[t_count];
- delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
- ddr_set_t_p->read_dqs_delay[t_count]=delay_temp;
- // printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
- }
- }
- {
- // printf("\n write dq_bit delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6-8 is coarse --step==1U",ui_1_32_100step);
- for(t_count=0;t_count<72;t_count++)
- {
- add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(0xc0+((t_count%9)<<8)+(t_count/36)));
- dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
- delay_org=dq_bit_delay[t_count];
- delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
-
- ddr_set_t_p->write_dq_bit_delay[t_count]=delay_temp;
-
-
- // printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
- }
- }
- {
- // printf("\n read dq_bit delay * BDLRx100==%d ps bit0-4 fine tune --step==bdlr step size about 5ps,no coarse",bdlr_100step);
- for(t_count=0;t_count<72;t_count++)
- {
- add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(0x68+((t_count%9)<<8)+(t_count/36)));
- dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
- delay_org=dq_bit_delay[t_count];
- delay_temp=((delay_org&0x3f));
-
- ddr_set_t_p->read_dq_bit_delay[t_count]=delay_temp;
- // printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
- }
- }
- {
- // printf("\n read dqs gate delay * 1/32UIx100==%d ps bit0-4 fine tune ,bit 6-10 is coarse",ui_1_32_100step);
- for(t_count=0;t_count<16;t_count++)
- {
- add_offset=((0<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0x80+(t_count/8)+((t_count%2)<<8)));
- dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
- delay_org=dq_bit_delay[t_count];
- delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
-
- ddr_set_t_p->read_dqs_gate_delay[t_count]=delay_temp;
-
-
- // printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
- }
-
- // printf("\n soc vref : lpddr4-- VREF = VDDQ*(0.047 + VrefDAC0[6:0]*0.00367 DDR4 --VREF = VDDQ*(0.510 + VrefDAC0[6:0]*0.00345");
- //((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40),over_ride_value)
- uint32_t vref_t_count=0;
- for(t_count=0;t_count<72;t_count++)
- {
- add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(((t_count%36)%9)<<8)|(0x40));
- dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
- delay_org=dq_bit_delay[t_count];
- delay_temp=((delay_org));
-
-if(t_count<35)
-{
- vref_t_count=((((t_count%36)/9)*8)+(t_count%9));
-
- ddr_set_t_p->soc_bit_vref[vref_t_count]=delay_temp;
-}
-
-
- // printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
- }
-
-
-
-// printf("\n dram vref : lpddr4-- VREF = VDDQ*(0. + VrefDAC0[6:0]*0. DDR4 --VREF = VDDQ*(0. + VrefDAC0[6:0]*0.");
- add_offset=((0<<20)|(1<<16)|(0<<12)|(0x082));
-delay_temp=dwc_ddrphy_apb_rd(add_offset);
- for(t_count=0;t_count<32;t_count++)
- {
-
-
- ddr_set_t_p->dram_bit_vref[t_count]=delay_temp;
-
-
-
- // printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
- }
- // printf("\n t_count: %04d %04d %08x %08x",0,delay_temp,((((add_offset) << 1)+0xfe000000)),delay_temp);
-
- for(t_count=0;t_count<4;t_count++)
- {//p_dev->p_ddrs->tdqs2dq=lpddr4_tdqs2dq;
- //ddr_set_t_p->retraining[0]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(0<<12)|(0xaa)); //PptCtlStatic
- //ddr_set_t_p->retraining[1]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(0<<12)|(0xae)); //PptDqsCntInvTrnTg0 ps0 rank0
- //ddr_set_t_p->retraining[2]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(0<<12)|(0xaf)); //PptDqsCntInvTrnTg0 ps0 rank1
- ddr_set_t_p->retraining[4*t_count+0]=(dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xaa)))&0xff; //PptCtlStatic
- ddr_set_t_p->retraining[4*t_count+1]=(dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xaa)))>>8; //PptCtlStatic
- ddr_set_t_p->retraining[4*t_count+2]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xae)); //PptDqsCntInvTrnTg0 ps0 rank0 lane 0-3
- ddr_set_t_p->retraining[4*t_count+3]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xaf)); //PptDqsCntInvTrnTg0 ps0 rank1 lane 0-3
- }
- }
-}
-
-
-char str[1024]="";
-//store ddr_parameter write 0x77f81cf0 0x300
-// printf("\n ");
-
-
- if(enable_ddr_fast_boot==1)
- ddr_set_t_p->fast_boot[0]=0xff;
-
- if(enable_ddr_fast_boot==2)
- ddr_set_t_p->fast_boot[0]=0;
-
- {
- #ifdef DEBUG_DDR_FASTBOOT_SHA
- printf("&ddr_sha.ddrs : 0x%x\n", (uint32_t)(uint64_t)&ddr_sha.ddrs);
- printf("&ddr_sha.sha2 : 0x%x\n", (uint32_t)(uint64_t)&ddr_sha.sha2);
- printf("ddr_set_add : 0x%x\n", (uint32_t)(uint64_t)ddr_set_add);
- #endif
- sha256_csum_wd((unsigned char *)(uint64_t)ddr_set_add, sizeof(ddr_set_t), ddr_sha.sha2, 0);
- #ifdef DEBUG_DDR_FASTBOOT_SHA
- printf("print sha\n");
- sprintf(str,"md %08x 0x100", (uint32_t)(uint64_t)(ddr_set_add-32));
- run_command(str,0);
- #endif
- #ifdef USE_FOR_UBOOT_2018
- sprintf(str,"store rsv write ddr-parameter 0x%08x 0x%08x ",ddr_set_add-SHA256_SUM_LEN,ddr_set_size+SHA256_SUM_LEN);
- #else
- sprintf(str,"store ddr_parameter write 0x%08x 0x%08x ",ddr_set_add-SHA256_SUM_LEN,ddr_set_size+SHA256_SUM_LEN);
- #endif
- // sprintf(str,"store ddr_parameter write 0x%08x 0x%08x ",ddr_set_add,ddr_set_size);
- // sprintf(str,"store rsv write ddr-parameter 0x%08x 0x%08x ",ddr_set_add,ddr_set_size);
- printf("\nstr=%s\n",str);
-
- run_command(str,0);
- }
-
-
- return 1;
-
-
-}
#else
int do_ddr_display_ddr_information(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
@@ -23798,15 +22859,15 @@
unsigned int ddr_type= pub_dcr&0x7; //0 -lpddr2 | 1- lpddr3 | 2- rev | 3 -ddr3 | 4- ddr4
{
- if (ddr_type==0)
+ if (ddr_type == 0)
printf("\nddr_type==lpddr2\n");
- if (ddr_type==1)
+ if (ddr_type == 1)
printf("\nddr_type==lpddr3\n");
- if (ddr_type==DDR_TYPE_DDR3)
+ if (ddr_type == DDR_TYPE_DDR3)
printf("\nddr_type==ddr3\n");
- if (ddr_type==DDR_TYPE_DDR4)
+ if (ddr_type == DDR_TYPE_DDR4)
printf("\nddr_type==ddr4\n");
- if(ddr_type==DDR_TYPE_DDR3)
+ if (ddr_type == DDR_TYPE_DDR3)
{//soc_zq_odt_div=360;
}
soc_ac_drv3=zq0pr_org&0xf;
@@ -23829,9 +22890,9 @@
reg_value=pub_mr1;
- if((((reg_value>>5)&1)==0))
+ if ((((reg_value>>5)&1) == 0))
{
- if(((reg_value>>1)&1)==0)
+ if (((reg_value>>1)&1) == 0)
{
dram_drv=40;
dram_ddr4_drv=34;
@@ -23843,40 +22904,40 @@
}
}
- if(((reg_value>>8)&7)==0)
+ if (((reg_value>>8)&7) == 0)
{
dram_ddr4_odt=0;
}
- if(((reg_value>>8)&7))
+ if (((reg_value>>8)&7))
{
dram_ddr4_odt=240/(((reg_value>>10)&1)|(((reg_value>>9)&1)<<1)|(((reg_value>>8)&1)<<2));
}
reg_value=(((reg_value>>9)&1)<<2)|(((reg_value>>6)&1)<<1)|(((reg_value>>2)&1)<<0);
- if(reg_value==1)
+ if (reg_value == 1)
{
dram_odt=60;
}
- if(reg_value==2)
+ if (reg_value == 2)
{
dram_odt=120;
}
- if(reg_value==3)
+ if (reg_value == 3)
{
dram_odt=40;
}
- if(reg_value==4)
+ if (reg_value == 4)
{
dram_odt=20;
}
- if(reg_value==5)
+ if (reg_value == 5)
{
dram_odt=30;
- }
+ }
printf("zq0pr_org==%x,zq1pr_org==%x,zq2pr_org==%x,\n",zq0pr_org,zq1pr_org,zq2pr_org);
printf("soc_ac_drv3==%d,soc_ac_odt3==%d,\n",480/(soc_ac_drv3+1),360/(soc_ac_odt3+1));
- printf("soc_data01_drv3==%d,soc_data01_odt3==%d,\n",480/(soc_data01_drv3+1),360/(soc_data01_odt3+1));
- printf("soc_data23_drv3==%d,soc_data23_odt3==%d,\n",480/(soc_data23_drv3+1),360/(soc_data23_odt3+1));
+ printf("soc_data01_drv3==%d,soc_data01_odt3==%d,\n",480/(soc_data01_drv3+1),360/(soc_data01_odt3+1));
+ printf("soc_data23_drv3==%d,soc_data23_odt3==%d,\n",480/(soc_data23_drv3+1),360/(soc_data23_odt3+1));
printf("dram_drv3==%d,dram_odt3==%d,\n\n\n",dram_drv,dram_odt);
printf("soc_ac_drv4_up==%d,soc_ac_drv4_down==%d,soc_ac_odt4==%d,\n",480/(soc_ac_drv4_up+1),480/(soc_ac_drv4_down+1),480/(soc_ac_odt4+1));
@@ -23909,12 +22970,12 @@
///*
unsigned int i=0;
unsigned int rank=0;
- for(rank=0;rank<2;(rank++))
+ for (rank=0;rank<2;(rank++))
{
printf("DDR0_RANK0==%d,\n",rank);
//bl2_print("DDR0_RANK0: 0x", rank, VALUE_HEX, "\n\n");
wr_reg(DDR0_PUB_RANKIDR, ((rank<<0)|((rank<<16))));
- for(i=0;i<4;(i++))
+ for (i=0;i<4;(i++))
{
//change dtcr0 lane reg map
wr_reg(DDR0_PUB_DTCR0,(((rank<<24)|(i<<16)))|((rd_reg(DDR0_PUB_DTCR0))&(~((1<<11)|(0xf<<16)))));//
@@ -23943,7 +23004,7 @@
printf("DDR0_PUB_R_SETTING: %d\n", ((rd_reg((uint64_t)(DDR0_PUB_DX0LCDLR3+i*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))))&0x1ff);
lcdlr_r_setting[rank][i]=((rd_reg((uint64_t)(DDR0_PUB_DX0LCDLR3+i*(DDR0_PUB_DX1LCDLR3-DDR0_PUB_DX0LCDLR3)))));
- printf("DDR0_PUB_VTDR: 0x%x\n", (rd_reg(DDR0_PUB_VTDR)));
+ printf("DDR0_PUB_VTDR: 0x%x\n", (rd_reg(DDR0_PUB_VTDR)));
}
}
wr_reg(DDR0_PUB_RANKIDR, ((0<<0)|((0<<16))));
@@ -23965,11 +23026,11 @@
global_ddr_clk ,(10000*1000/(2*global_ddr_clk))/((rd_reg(DDR0_PUB_ACMDLR0)>>16)&0X1FF),
(1000*100000/(2*global_ddr_clk))/((rd_reg(DDR0_PUB_ACMDLR0)>>16)&0X1FF));
delay_line_100step=(1000*100000/(2*global_ddr_clk))/((rd_reg(DDR0_PUB_ACMDLR0)>>16)&0X1FF);
- for(rank=0;rank<2;(rank++))
+ for (rank=0;rank<2;(rank++))
{
printf("DDR0_RANK0==%d,\n",rank);
- for(i=0;i<4;(i++))
+ for (i=0;i<4;(i++))
{
//dtedr0[rank][i]=(rd_reg(DDR0_PUB_DTEDR0));
//dtedr1[rank][i]=(rd_reg(DDR0_PUB_DTEDR1));
@@ -23984,7 +23045,7 @@
printf("%4d ", ((((dtedr1[rank][i])>>9)&0x1ff)-lcdlr_r_setting[rank][i])*delay_line_100step/100
);
}
- printf("\n");
+ printf("\n");
}
printf("\nend==%d,\n",rank);
#endif
@@ -24000,7 +23061,7 @@
{
//ddr_test_cmd 0x25 1 1 10 10 10 10 10 10 10 10 10 10
-#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
+#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
// if(!argc)
// goto DDR_TUNE_DQS_START;
int i=0;
@@ -24010,7 +23071,7 @@
unsigned int count=0;
unsigned int reg_add=0;
unsigned int reg_value=0;
- unsigned int offset_value[10]={0,0,0,0,0,0,0,0,0,0} ; // ac w clk w lane 0 w r lane 1 w r lane2 w r lane3 w r
+ unsigned int offset_value[10]={0,0,0,0,0,0,0,0,0,0} ; // ac w clk w lane 0 w r lane 1 w r lane2 w r lane3 w r
printf("\nargc== 0x%08x\n", argc);
for (i = 0;i<argc;i++)
printf("\nargv[%d]=%s\n",i,argv[i]);
@@ -24037,9 +23098,9 @@
}
if (argc > 3)
- {
+ {
count=2;
- while(count<(argc-1))
+ while (count<(argc-1))
{
offset_value[count-2]= simple_strtoull_ddr(argv[count+1], &endp, 0);
if (*argv[count+1] == 0 || *endp != 0)
@@ -24053,7 +23114,7 @@
}
printf("resume_ddl=%d,\n",resume_ddl);
- if(offset_id)
+ if (offset_id)
printf("offset right ++%d,\n",offset_id);
else
printf("offset left --%d,\n",offset_id);
@@ -24080,15 +23141,15 @@
//if (vref_lcdlr_offset)
- for (i = 0;i<10;i++)
+ for (i = 0;i<10;i++)
{
- if(i==0)
+ if (i == 0)
reg_add = DDR0_PUB_ACLCDLR;
- if(i==1)
+ if (i == 1)
reg_add = DDR0_PUB_ACBDLR0;
- if(i>1)
+ if (i>1)
{
- if(i%2){
+ if (i%2) {
reg_add = DDR0_PUB_DX0LCDLR3 + ((DDR0_PUB_DX1LCDLR3 - DDR0_PUB_DX0LCDLR3)*((i-2)/2));}
else{
reg_add = DDR0_PUB_DX0LCDLR1 + ((DDR0_PUB_DX1LCDLR3 - DDR0_PUB_DX0LCDLR3)*((i-2)/2));}
@@ -24096,10 +23157,10 @@
printf("\n org reg_add 0x%08x== 0x%08x\n ",(reg_add),
rd_reg(reg_add));
- if(offset_id) //offset +
+ if (offset_id) //offset +
{
wr_reg(reg_add, ( rd_reg(reg_add)+offset_value[i]));
- if(i>1)
+ if (i>1)
{if(i%2){wr_reg((reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3),
( rd_reg((reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3))+offset_value[i]));
}
@@ -24113,7 +23174,7 @@
reg_value=rd_reg(reg_add);
reg_value=( reg_value>offset_value[i])?( reg_value-offset_value[i]):0;
wr_reg(reg_add, reg_value);
- if(i>1)
+ if (i>1)
{if(i%2){wr_reg((reg_add+DDR0_PUB_DX0LCDLR4-DDR0_PUB_DX0LCDLR3),
( reg_value));
}
@@ -24135,7 +23196,7 @@
}
// printf("\n read reg==0x%08x\n ",(readl(reg_add)));
printf("\nend pause ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
- if(resume_ddl){
+ if (resume_ddl) {
writel(((readl(DDR0_PUB_REG_BASE+4))&(~(1<<29))),(DDR0_PUB_REG_BASE+4));
printf("\n resume ddl pir== 0x%08x\n", readl(DDR0_PUB_REG_BASE+4));
}
@@ -24222,8 +23283,8 @@
#define TEST_ARG_BOOT_TIMES_H 7
//BYTE12-15
- #define TEST_ARG_ERROR_FLAG 8 //take 4 byte for kernel test flag
- //#define TEST_ARG_ERROR_FLAG 63*4 //take 4 byte for kernel test flag
+ //#define TEST_ARG_ERROR_FLAG 8 //take 4 byte for kernel test flag
+ #define TEST_ARG_ERROR_FLAG 63*4 //take 4 byte for kernel test flag
//BYTE16-19
//#define TEST_ARG_16_LCDLR_TEMP_COUNT 16
@@ -24329,7 +23390,7 @@
}
printf("test_index_enable==0x%08x\n",test_index_enable);
enable_kernel_test=(test_index_enable>>7)&1;
- if(enable_kernel_test){
+ if (enable_kernel_test) {
printf("enable kernel window test\n");
}
@@ -24416,7 +23477,7 @@
//num_arry=p_num_arry;
for (i = 0; i < 64*4; i++) {
num_arry[i]=ddr_rd_8_16bit_on_32reg(sticky_reg_base_add,8,i);
- if((i==0)||(i==32)||(i==(32+10*3))||(i==(32+10*3+16*3))||(i==(32+10*3+16*3+16*3)))
+ if ((i == 0) || (i == 32) || (i == (32+10*3)) || (i == (32+10*3+16*3)) || (i == (32+10*3+16*3+16*3)))
{
printf("\n numarry[%d]" ,i);
}
@@ -24434,11 +23495,11 @@
#define TEST_ARG_7_DMC_STICKY_MAGIC 7
*/
- uint16_t test_left_max_init_value =32;
- uint16_t test_right_max_init_value =32;
- uint16_t test_boot_times =0;
- uint16_t test_ddr_frequency =0;
- //uint16_t temp_sub_value_a =0;
+ uint16_t test_left_max_init_value =32;
+ uint16_t test_right_max_init_value =32;
+ uint16_t test_boot_times =0;
+ uint16_t test_ddr_frequency =0;
+ //uint16_t temp_sub_value_a =0;
/*
uint16_t test_arg_1_cmd0 =1; //master cmd
uint16_t test_arg_1_cmd1 =0; //min cmd
@@ -24467,7 +23528,7 @@
printf("TEST_ARG_BOOT_TIMES==%d\n",(num_arry[TEST_ARG_BOOT_TIMES_H]<<8)|(num_arry[TEST_ARG_BOOT_TIMES_L]<<0));
test_boot_times=(num_arry[TEST_ARG_BOOT_TIMES_H]<<8)|(num_arry[TEST_ARG_BOOT_TIMES_L]<<0);
test_ddr_frequency=(num_arry[TEST_ARG_FREQ_NIBBLE_H]<<8)|(num_arry[TEST_ARG_FREQ_NIBBLE_L]<<0);
- if((num_arry[TEST_ARG_0_DMC_STICKY_MAGIC]==(DMC_STICKY_UBOOT_WINDOW_MAGIC_1&0xff))&&
+ if ((num_arry[TEST_ARG_0_DMC_STICKY_MAGIC] == (DMC_STICKY_UBOOT_WINDOW_MAGIC_1&0xff)) &&
(num_arry[TEST_ARG_1_CMD0]==(DMC_STICKY_UBOOT_WINDOW_MAGIC_1&0xff)) ) //for check magic number make sume enter test command
{
//num_arry[TEST_ARG_5_BOOT_TIMES]++;
@@ -24477,13 +23538,13 @@
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_BOOT_TIMES_L,num_arry[TEST_ARG_BOOT_TIMES_L]);
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_BOOT_TIMES_H,num_arry[TEST_ARG_BOOT_TIMES_H]);
- if( test_ddr_frequency!=global_ddr_clk) //
+ if ( test_ddr_frequency != global_ddr_clk) //
{
printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n",global_ddr_clk,test_ddr_frequency);
sprintf(str,"d2pll %d",test_ddr_frequency);
printf("\nstr=%s\n",str);
run_command(str,0);
- while(1);
+ while (1) ;
}
}
else
@@ -24498,6 +23559,7 @@
}
printf("test_sticky is not magic nummber,boot times==%d\n",test_boot_times);
+ if (config_register == 1)
{
wr_reg((sticky_reg_base_add+TEST_ARG_CS0_TEST_START_INDEX), cs0_test_start);
wr_reg((sticky_reg_base_add+TEST_ARG_CS0_TEST_SIZE_INDEX), cs0_test_size);
@@ -24511,16 +23573,13 @@
}
num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX]=test_index_enable;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_TEST_INDEX_ENALBE_INDEX,num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX]);
- if(config_register==1)
- {
- num_arry[TEST_ARG_2_STEP]=0;
- ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP,num_arry[TEST_ARG_2_STEP]);
- }
+ num_arry[TEST_ARG_2_STEP]=0;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP,num_arry[TEST_ARG_2_STEP]);
num_arry[TEST_ARG_3_ALL_TOGHTER]=all_toghter_enable;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_3_ALL_TOGHTER,num_arry[TEST_ARG_3_ALL_TOGHTER]);
}
- if(( num_arry[TEST_ARG_2_STEP])==0)
+ if (( num_arry[TEST_ARG_2_STEP]) == 0)
{
{
num_arry[TEST_ARG_0_DMC_STICKY_MAGIC]=DMC_STICKY_UBOOT_WINDOW_MAGIC_1;
@@ -24556,7 +23615,7 @@
//num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_ORG]=0xffff;
test_left_max_init_value=16;
test_right_max_init_value=16;
- if(nibble_step<10)
+ if (nibble_step<10)
{
test_left_max_init_value=32;
test_right_max_init_value=32;
@@ -24570,22 +23629,22 @@
{
if (nibble_step<32)
{
- if(((nibble_mask[0])>>nibble_step)&1)
+ if (((nibble_mask[0])>>nibble_step)&1)
num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4;
}
else if (nibble_step<64)
{
- if(((nibble_mask[1])>>(nibble_step-32))&1)
+ if (((nibble_mask[1])>>(nibble_step-32))&1)
num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4;
}
else if (nibble_step<96)
{
- if(((nibble_mask[2])>>(nibble_step-64))&1)
+ if (((nibble_mask[2])>>(nibble_step-64))&1)
num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4;
}
- if(all_toghter_enable)
+ if (all_toghter_enable)
{
- if((nibble_step==0)||(nibble_step==10)||(nibble_step==(10+16)))
+ if ((nibble_step == 0) || (nibble_step == 10) || (nibble_step == (10+16)))
num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=0;
else
num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4;
@@ -24609,69 +23668,56 @@
}
- if(all_toghter_enable)
- {
- for (nibble_step = 0; nibble_step < 72; nibble_step++)
- {
- if((nibble_step==0)||(nibble_step==10)||(nibble_step==(10+16)))
- {
- // num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=0;
- }
- else
- num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+nibble_step*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4;
- }
- }
-if(config_register==1)
+if (config_register == 1)
{
num_arry[TEST_ARG_2_STEP]=0;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]);
}
-if(( num_arry[TEST_ARG_2_STEP]))
+if (( num_arry[TEST_ARG_2_STEP]))
{
-for(test_index=num_arry[TEST_ARG_2_STEP];test_index<test_index_max ;test_index++ )
+for (test_index=num_arry[TEST_ARG_2_STEP];test_index<test_index_max ;test_index++ )
{
printf("\ntest_index=%d\n",test_index);
- if((((test_index_enable)>>(test_index-1))&1)==0)
+ if ((((test_index_enable)>>(test_index-1))&1) == 0)
{
num_arry[TEST_ARG_2_STEP]=((num_arry[TEST_ARG_2_STEP])+1);//why can not use ++
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]);
continue;
}
{
- if(test_index==DMC_TEST_WINDOW_INDEX_ATXDLY)
+ if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY)
{
nibble_save_offset=0;
nibble_max=10;
- nibble_mask[0]= 0x30;
- if((dram_type==CONFIG_DDR_TYPE_LPDDR3))
+ if ((dram_type == CONFIG_DDR_TYPE_LPDDR3))
{
- nibble_mask[0]= 0x3e3;
+ nibble_mask[0]= 0x3e0;
}
- if((dram_type==CONFIG_DDR_TYPE_LPDDR4))
+ if ((dram_type == CONFIG_DDR_TYPE_LPDDR4))
{
- nibble_mask[0]= 0x273;
- if((channel_mode==CONFIG_DDR0_32BIT_RANK01_CH0))
- nibble_mask[0]= 0x3f3;
+ nibble_mask[0]= 0x210;
+ if ((channel_mode == CONFIG_DDR0_32BIT_RANK01_CH0))
+ nibble_mask[0]= 0x3f0;
}
test_left_max_init_value=64;
test_right_max_init_value=64;
}
- if(test_index==DMC_TEST_WINDOW_INDEX_TXDQSDLY)
+ if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY)
{
nibble_save_offset=10;
nibble_max=16;
- if((cs1_test_size==0))
+ if ((cs1_test_size == 0))
{
nibble_mask[0]= 0xff00;
}
test_left_max_init_value=16;
test_right_max_init_value=16;
}
- if(test_index==DMC_TEST_WINDOW_INDEX_RXCLKDLY)
+ if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY)
{
nibble_save_offset=(10)+(16);
- if((cs1_test_size==0))
+ if ((cs1_test_size == 0))
{
nibble_mask[0]= 0xff00;
}
@@ -24679,11 +23725,11 @@
test_left_max_init_value=16;
test_right_max_init_value=16;
}
- if(test_index==DMC_TEST_WINDOW_INDEX_TXDQDLY)
+ if (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY)
{
nibble_save_offset=0;
nibble_max=72;
- if((cs1_test_size==0))
+ if ((cs1_test_size == 0))
{
nibble_mask[1]= 0xfffffff0;
nibble_mask[2]= 0xffffffff;
@@ -24691,40 +23737,40 @@
test_left_max_init_value=16;
test_right_max_init_value=16;
}
- if(test_index==DMC_TEST_WINDOW_INDEX_RXPBDLY)
+ if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY)
{
nibble_save_offset=0;
nibble_max=72;
- if((cs1_test_size==0))
+ if ((cs1_test_size == 0))
{
nibble_mask[1]= 0xfffffff0;
nibble_mask[2]= 0xffffffff;
}
-
+
test_left_max_init_value=64;
test_right_max_init_value=64;}
- //nibble_max=8;//
+ //nibble_max=8;//
// if(nibble_max>30) can not over sticky register size
// nibble_max=30;
for ((nibble_step=0);(nibble_step<nibble_max);(nibble_step++))
{
if (nibble_step<32)
{
- if(((nibble_mask[0])>>nibble_step)&1)
+ if (((nibble_mask[0])>>nibble_step)&1)
num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4;
}
else if (nibble_step<64)
{
- if(((nibble_mask[1])>>(nibble_step-32))&1)
+ if (((nibble_mask[1])>>(nibble_step-32))&1)
num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4;
}
else if (nibble_step<96)
{
- if(((nibble_mask[2])>>(nibble_step-64))&1)
+ if (((nibble_mask[2])>>(nibble_step-64))&1)
num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+(nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE+LCD_BDLR_STATUS]=4;
}
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
}
}
@@ -24732,24 +23778,24 @@
{
for ((nibble_step=0);(nibble_step<nibble_max);(nibble_step++))
{
- if(num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==4)
+ if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)] == 4)
continue;
printf("nibble_step ==%d\n",nibble_step);
- if(test_index==DMC_TEST_WINDOW_INDEX_TXDQSDLY)
+ if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY)
{
- if(nibble_step%2)
+ if (nibble_step%2)
{
//nibble_save_offset
//num_arry[TEST_ARG_2_STEP]=1;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN),
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN),
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step-1+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]);
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX),
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX),
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step-1+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]);
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step-1+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
//nibble_step++;
continue;
@@ -24757,39 +23803,39 @@
}
test_start_addr=cs0_test_start;
ddr_test_size=cs0_test_size;
- if(test_index==DMC_TEST_WINDOW_INDEX_ATXDLY)
+ if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY)
{
test_start_addr=cs0_test_start;
ddr_test_size=cs0_test_size;
}
- if(test_index==DMC_TEST_WINDOW_INDEX_TXDQSDLY)
+ if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY)
{
- if(nibble_step>7)
+ if (nibble_step>7)
{
test_start_addr=cs1_test_start;
ddr_test_size=cs1_test_size;
}
}
- if(test_index==DMC_TEST_WINDOW_INDEX_RXCLKDLY)
+ if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY)
{
- if(nibble_step>7)
+ if (nibble_step>7)
{
test_start_addr=cs1_test_start;
ddr_test_size=cs1_test_size;
}
}
- if(test_index==DMC_TEST_WINDOW_INDEX_TXDQDLY)
+ if (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY)
{
- if(nibble_step>35)
+ if (nibble_step>35)
{
test_start_addr=cs1_test_start;
ddr_test_size=cs1_test_size;
}
}
- if(test_index==DMC_TEST_WINDOW_INDEX_RXPBDLY)
+ if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY)
{
- if(nibble_step>35)
+ if (nibble_step>35)
{
test_start_addr=cs1_test_start;
ddr_test_size=cs1_test_size;
@@ -24815,54 +23861,27 @@
nibble_mask[2]=((0xffffffff)&(~(1<<(nibble_step-64))));
}
}
- if(all_toghter_enable)
- {
- if(test_index==DMC_TEST_WINDOW_INDEX_ATXDLY)
- {
- nibble_save_offset=0;
- nibble_max=10;
- nibble_mask[0]= 0x30;
- nibble_mask[1]= 0;
- nibble_mask[2]= 0;
- if((dram_type==CONFIG_DDR_TYPE_LPDDR3))
- {
- nibble_mask[0]= 0x3e3;
- }
- if((dram_type==CONFIG_DDR_TYPE_LPDDR4))
- {
- nibble_mask[0]= 0x273;
- if((channel_mode==CONFIG_DDR0_32BIT_RANK01_CH0))
- nibble_mask[0]= 0x3f3;
- }
- }
- else
- {
- nibble_mask[0]= 0;
- nibble_mask[1]= 0;
- nibble_mask[2]= 0;
- }
- }
ddr_test_watchdog_enable(watchdog_time_s); //s
printf("\nenable %ds watchdog \n",watchdog_time_s);
- if((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==0xffff)
+ if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)] == 0xffff)
||(num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==0)
||(num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==1) )
{
printf("\nnibble_step ==%d ", nibble_step);
- if((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==0xffff)
+ if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)] == 0xffff)
||(num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==0))
{
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=1;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
- if(num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]==0)
+ if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)] == 0)
{
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
run_command("reset",0);
}
@@ -24881,33 +23900,28 @@
num_arry[TEST_ARG_ERROR_FLAG]);
}
- sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,nibble_mask[0],nibble_mask[1],nibble_mask[2],DDR_PARAMETER_LEFT,
- num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]);
+ if (all_toghter_enable)
+ sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,0,0,0,DDR_PARAMETER_LEFT,
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]);
+ else
+ sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,nibble_mask[0],nibble_mask[1],nibble_mask[2],DDR_PARAMETER_LEFT,
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]);
printf("\nstr=%s\n",str);
ddr_test_watchdog_clear();
run_command(str,0);
-
temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
- if(all_toghter_enable && cs1_test_size)
- {
- test_start_addr=cs1_test_start;
- ddr_test_size=cs1_test_size;
- temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
- test_start_addr=cs0_test_start;
- ddr_test_size=cs0_test_size;
- }
- if(temp_test_error)
+ if (temp_test_error)
{
run_command("reset",0);
}
else
{
//
- if(!enable_kernel_test)
+ if (!enable_kernel_test)
{
num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_PASS;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- TEST_ARG_ERROR_FLAG,
+ TEST_ARG_ERROR_FLAG,
num_arry[TEST_ARG_ERROR_FLAG]);
run_command("reset",0);
}
@@ -24917,10 +23931,10 @@
printf("\nenable %ds watchdog \n",kernel_watchdog_s);
run_command("run storeboot",0);
}
- /*
+ /*
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
run_command("reset",0);
*/
@@ -24929,38 +23943,38 @@
else if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==1)
{//go on find left edge
- if(num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]==0)
+ if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)] == 0)
{
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
run_command("reset",0);
}
- if((num_arry[TEST_ARG_ERROR_FLAG])==TEST_ARG_ERROR_FLAG_PASS)
+ if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_PASS)
{
{
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
}
{
num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_NULL;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- TEST_ARG_ERROR_FLAG,
+ TEST_ARG_ERROR_FLAG,
num_arry[TEST_ARG_ERROR_FLAG]);
}
run_command("reset",0);
}
- if((num_arry[TEST_ARG_ERROR_FLAG])==TEST_ARG_ERROR_FLAG_FAIL)
+ if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_FAIL)
{
{
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]=
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]-1;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN),
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN),
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]);
}
{
@@ -24971,29 +23985,24 @@
}
sprintf(buf, "0x%08x", ( num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]));
printf( "%s", buf);
-
- sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,nibble_mask[0],nibble_mask[1],nibble_mask[2],DDR_PARAMETER_LEFT,
- ( num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]));
+ if (all_toghter_enable)
+ sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,0,0,0,DDR_PARAMETER_LEFT,
+ ( num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]));
+ else
+ sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,nibble_mask[0],nibble_mask[1],nibble_mask[2],DDR_PARAMETER_LEFT,
+ ( num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MIN)]));
printf("\nstr=%s\n",str);
ddr_test_watchdog_clear();
run_command(str,0);
temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
- if(all_toghter_enable&&cs1_test_size)
- {
- test_start_addr=cs1_test_start;
- ddr_test_size=cs1_test_size;
- temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
- test_start_addr=cs0_test_start;
- ddr_test_size=cs0_test_size;
- }
- if(temp_test_error)
+ if (temp_test_error)
{
run_command("reset",0);
}
else
{
//
- if(!enable_kernel_test)
+ if (!enable_kernel_test)
{
num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_PASS;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
@@ -25007,10 +24016,10 @@
printf("\nenable %ds watchdog \n",kernel_watchdog_s);
run_command("run storeboot",0);
}
- /*
+ /*
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
run_command("reset",0);
*/
@@ -25019,24 +24028,24 @@
}
// run_command("reset",0);
}
-
- if((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==2)||
+
+ if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)] == 2) ||
(num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==3))
{
printf("\nnibble_step ==%d ", nibble_step);
- if((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==2)
+ if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)] == 2)
||(num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==2))
{
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=3;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
- if(num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]==0)
+ if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)] == 0)
{
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=4;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
run_command("reset",0);
}
@@ -25055,27 +24064,19 @@
num_arry[TEST_ARG_ERROR_FLAG]);
}
sprintf(str,"ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d",test_index,nibble_mask[0],nibble_mask[1],nibble_mask[2],DDR_PARAMETER_RIGHT,
- num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]);
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]);
printf("\nstr=%s\n",str);
ddr_test_watchdog_clear();
run_command(str,0);
temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
- if(all_toghter_enable&&cs1_test_size)
- {
- test_start_addr=cs1_test_start;
- ddr_test_size=cs1_test_size;
- temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
- test_start_addr=cs0_test_start;
- ddr_test_size=cs0_test_size;
- }
- if(temp_test_error)
+ if (temp_test_error)
{
run_command("reset",0);
}
else
{
//
- if(!enable_kernel_test)
+ if (!enable_kernel_test)
{
num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_PASS;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
@@ -25089,10 +24090,10 @@
printf("\nenable %ds watchdog \n",kernel_watchdog_s);
run_command("run storeboot",0);
}
- /*
+ /*
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
run_command("reset",0);
*/
@@ -25100,44 +24101,44 @@
}
else if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]==3)
{//go on find left edge
- if(num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]==0)
+ if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)] == 0)
{
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=4;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
run_command("reset",0);
}
- if((num_arry[TEST_ARG_ERROR_FLAG])==TEST_ARG_ERROR_FLAG_PASS)
+ if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_PASS)
{
{
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=4;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
}
{
num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_NULL;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- TEST_ARG_ERROR_FLAG,
+ TEST_ARG_ERROR_FLAG,
num_arry[TEST_ARG_ERROR_FLAG]);
}
run_command("reset",0);
}
- if((num_arry[TEST_ARG_ERROR_FLAG])==TEST_ARG_ERROR_FLAG_FAIL)
+ if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_FAIL)
{
{
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]=
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]-1;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX),
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX),
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]);
}
{
num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_FAIL;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- TEST_ARG_ERROR_FLAG,
+ TEST_ARG_ERROR_FLAG,
num_arry[TEST_ARG_ERROR_FLAG]);
}
sprintf(buf, "0x%08x", ( num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_MAX)]));
@@ -25148,25 +24149,17 @@
ddr_test_watchdog_clear();
run_command(str,0);
temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
- if(all_toghter_enable&&cs1_test_size)
- {
- test_start_addr=cs1_test_start;
- ddr_test_size=cs1_test_size;
- temp_test_error=temp_test_error+ddr_test_s_cross_talk_pattern(ddr_test_size);
- test_start_addr=cs0_test_start;
- ddr_test_size=cs0_test_size;
- }
- if(temp_test_error)
+ if (temp_test_error)
{
run_command("reset",0);
}
else
{
- if(!enable_kernel_test)
+ if (!enable_kernel_test)
{
num_arry[TEST_ARG_ERROR_FLAG]=TEST_ARG_ERROR_FLAG_PASS;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- TEST_ARG_ERROR_FLAG,
+ TEST_ARG_ERROR_FLAG,
num_arry[TEST_ARG_ERROR_FLAG]);
run_command("reset",0);
}
@@ -25177,10 +24170,10 @@
run_command("run storeboot",0);
}
- /*
+ /*
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]=2;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,
- (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS),
num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE+((nibble_step+nibble_save_offset)*TEST_ARG_NIBBLE_WIDTH_BYTE)+LCD_BDLR_STATUS)]);
run_command("reset",0);
*/
@@ -25258,10 +24251,6 @@
char delay_left_margin=0;
char delay_right_margin=0;
- if(all_toghter_enable==1)
- {
- nibble_max=1;
- }
for ( nibble_step=0;nibble_step<nibble_max;nibble_step++)
{
//serial_put_dec_out_align(delay_martix[count].add_index,8);
@@ -25284,7 +24273,7 @@
);
}
}
-
+
// delay_left_margin=((num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_ORG]>num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_MIN])?
// (num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_ORG]-num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_MIN]):0);
// delay_right_margin=((num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_MAX]>num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_ORG])?
@@ -25327,17 +24316,14 @@
}
}
- if(config_register==1)
+ if (config_register == 1)
{
- if(num_arry[TEST_ARG_2_STEP]==0)
+ if (num_arry[TEST_ARG_2_STEP] == 0)
{
num_arry[TEST_ARG_2_STEP]=1;
ddr_wr_8_16bit_on_32reg(sticky_reg_base_add,8,TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]);
}
}
-
- if((enable_kernel_test)&&(num_arry[TEST_ARG_2_STEP]>1))
- run_command("run storeboot",0);
return reg_value;
}
#else
@@ -25455,10 +24441,10 @@
//unsigned int *num_arry_lane1=NULL;
//unsigned int *num_arry_lane2=NULL;
//unsigned int *num_arry_lane3=NULL;
- //char *name_lane0;
- //char *name_lane1;
- //char *name_lane2;
- //char *name_lane3;
+ //char *name_lane0;
+ //char *name_lane1;
+ //char *name_lane2;
+ //char *name_lane3;
num_arry = (unsigned int *)(&str_to_numarry);
int i;
//char *varname; char *env_lcdlr_temp_count;
@@ -25535,7 +24521,7 @@
printf("test_arg_6 lcdlr_temp_count=%d\n",num_arry[6]);
printf("test_arg_7=%d\n",num_arry[7]);
- if((num_arry[7]==DMC_STICKY_MAGIC_1)) //for check magic number make sume enter test command
+ if ((num_arry[7] == DMC_STICKY_MAGIC_1)) //for check magic number make sume enter test command
{boot_times++;
}
@@ -25554,18 +24540,18 @@
writel(num_arry[5],(sticky_reg_base_add+(5<<2)));
//if(test_arg_2_step)
- if(test_arg_2_step)
+ if (test_arg_2_step)
{
- if(test_arg_3_freq!=global_ddr_clk) //
+ if (test_arg_3_freq != global_ddr_clk) //
{
printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n",global_ddr_clk,test_arg_3_freq);
sprintf(str,"d2pll %d",test_arg_3_freq);
printf("\nstr=%s\n",str);
run_command(str,0);
- while(1);
+ while (1) ;
}
}
- if(test_arg_2_step==0)
+ if (test_arg_2_step == 0)
{
{
test_arg_0_cmd0=0x22;
@@ -25658,39 +24644,39 @@
printf("DDR0_PUB_DX1GCR0==%x\n",(readl(DDR0_PUB_DX1GCR0)));
printf("DDR0_PUB_DX2GCR0==%x\n",(readl(DDR0_PUB_DX2GCR0)));
printf("DDR0_PUB_DX3GCR0==%x\n",(readl(DDR0_PUB_DX3GCR0)));
- if(((readl(DDR0_PUB_DX0GCR0))&1)==0)
- lane_disable= lane_disable|1;
- if(((readl(DDR0_PUB_DX1GCR0))&1)==0)
- lane_disable= lane_disable|(1<<1);
- if(((readl(DDR0_PUB_DX2GCR0))&1)==0)
- lane_disable= lane_disable|(1<<2);
- if(((readl(DDR0_PUB_DX3GCR0))&1)==0)
- lane_disable= lane_disable|(1<<3);
+ if (((readl(DDR0_PUB_DX0GCR0))&1) == 0)
+ lane_disable= lane_disable|1;
+ if (((readl(DDR0_PUB_DX1GCR0))&1) == 0)
+ lane_disable= lane_disable|(1<<1);
+ if (((readl(DDR0_PUB_DX2GCR0))&1) == 0)
+ lane_disable= lane_disable|(1<<2);
+ if (((readl(DDR0_PUB_DX3GCR0))&1) == 0)
+ lane_disable= lane_disable|(1<<3);
#endif
- if(lane_disable)
+ if (lane_disable)
{if(lane_disable&0x1){
dq_lcd_bdl_value_wdq_status_a[0]=4;
dq_lcd_bdl_value_rdqs_status_a[0]=4;
}
- if(lane_disable&0x2){
+ if (lane_disable&0x2) {
dq_lcd_bdl_value_wdq_status_a[1]=4;
dq_lcd_bdl_value_rdqs_status_a[1]=4;
}
- if(lane_disable&0x4){
+ if (lane_disable&0x4) {
dq_lcd_bdl_value_wdq_status_a[2]=4;
dq_lcd_bdl_value_rdqs_status_a[2]=4;
}
- if(lane_disable&0x8){
+ if (lane_disable&0x8) {
dq_lcd_bdl_value_wdq_status_a[3]=4;
dq_lcd_bdl_value_rdqs_status_a[3]=4;
}
printf("lane_disable==%x\n",lane_disable);
- if(lane_disable&0x10){
+ if (lane_disable&0x10) {
dq_lcd_bdl_value_aclcdlr_status_a=4;
printf("dq_lcd_bdl_value_aclcdlr_status_a==%x\n",dq_lcd_bdl_value_aclcdlr_status_a);
}
- if(lane_disable&0x20){
+ if (lane_disable&0x20) {
dq_lcd_bdl_value_bdlr0_status_a=4;
printf("dq_lcd_bdl_value_bdlr0_status_a==%x\n",dq_lcd_bdl_value_bdlr0_status_a);
@@ -25738,7 +24724,7 @@
for (i = 0; i < 48; i++) {
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- //setenv(str_temp1, str_temp2);
+ //env_set(str_temp1, str_temp2);
//run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
}
@@ -25759,7 +24745,7 @@
}
//sprintf(str, "%lx", value);
printf("%s", str);
- // setenv(varname, str);
+ // env_set(varname, str);
//run_command("save",0);
for (i = 0; i < 48; i++) {
@@ -25825,16 +24811,16 @@
lcdlr_temp_count=dq_lcd_bdl_temp_reg_value;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s", buf);
- setenv(env_lcdlr_temp_count, buf);
+ env_set(env_lcdlr_temp_count, buf);
run_command("save",0);
}
*/
- if((dq_lcd_bdl_value_wdq_status_a[lane_step]==0xffff)
+ if ((dq_lcd_bdl_value_wdq_status_a[lane_step] == 0xffff)
||(dq_lcd_bdl_value_wdq_status_a[lane_step]==0)
||(dq_lcd_bdl_value_wdq_status_a[lane_step]==1)
)
{
- if((dq_lcd_bdl_value_wdq_status_a[lane_step]==0xffff)
+ if ((dq_lcd_bdl_value_wdq_status_a[lane_step] == 0xffff)
||(dq_lcd_bdl_value_wdq_status_a[lane_step]==0))
{ dq_lcd_bdl_value_wdq_status_a[lane_step]=1;
{
@@ -25843,14 +24829,14 @@
i=8+lane_step*8+3;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
//run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
}
lcdlr_temp_count=0;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s", buf);
- // setenv(env_lcdlr_temp_count, buf);
+ // env_set(env_lcdlr_temp_count, buf);
// run_command("save",0);
writel(num_arry[6],(sticky_reg_base_add+(6<<2)));
}
@@ -25868,7 +24854,7 @@
}
else if (dq_lcd_bdl_value_wdq_status_a[lane_step]==1)
{
- // temp_s= getenv(env_lcdlr_temp_count);
+ // temp_s= env_get(env_lcdlr_temp_count);
// if(temp_s)
// {
// lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
@@ -25890,13 +24876,13 @@
i=8+lane_step*8+1;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
//run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
i=8+lane_step*8+3;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
// run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
}
@@ -25905,7 +24891,7 @@
run_command("reset",0);
}
- if((dq_lcd_bdl_value_wdq_status_a[lane_step]==2)||
+ if ((dq_lcd_bdl_value_wdq_status_a[lane_step] == 2) ||
(dq_lcd_bdl_value_wdq_status_a[lane_step]==3))
{
// if((dq_lcd_bdl_value_wdq_min_a[lane_step])==0xffff)
@@ -25915,14 +24901,14 @@
// }
{
- if(dq_lcd_bdl_value_wdq_status_a[lane_step]==2)
+ if (dq_lcd_bdl_value_wdq_status_a[lane_step] == 2)
{ dq_lcd_bdl_value_wdq_status_a[lane_step]=3;
{
num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_wdq_status_a[lane_step];
i=8+lane_step*8+3;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
//run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
}
@@ -25930,7 +24916,7 @@
lcdlr_temp_count=0;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s", buf);
- // setenv(env_lcdlr_temp_count, buf);
+ // env_set(env_lcdlr_temp_count, buf);
// run_command("save",0);
writel(num_arry[6],(sticky_reg_base_add+(6<<2)));
}
@@ -25948,7 +24934,7 @@
}
else if (dq_lcd_bdl_value_wdq_status_a[lane_step]==3)
{
- // temp_s= getenv(env_lcdlr_temp_count);
+ // temp_s= env_get(env_lcdlr_temp_count);
// if(temp_s)
// {
//
@@ -25969,13 +24955,13 @@
i=8+lane_step*8+2;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
//run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
i=8+lane_step*8+3;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
// run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
}
@@ -25986,12 +24972,12 @@
}
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==0xffff)
+ if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 0xffff)
||(dq_lcd_bdl_value_rdqs_status_a[lane_step]==0)
||(dq_lcd_bdl_value_rdqs_status_a[lane_step]==1)
)
{
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==0xffff)
+ if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 0xffff)
||(dq_lcd_bdl_value_rdqs_status_a[lane_step]==0))
{ dq_lcd_bdl_value_rdqs_status_a[lane_step]=1;
{
@@ -25999,7 +24985,7 @@
i=8+lane_step*8+7;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
//run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
}
@@ -26007,7 +24993,7 @@
lcdlr_temp_count=0;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s", buf);
- // setenv(env_lcdlr_temp_count, buf);
+ // env_set(env_lcdlr_temp_count, buf);
// run_command("save",0);
//i=6;
writel(num_arry[6],(sticky_reg_base_add+(6<<2)));
@@ -26026,12 +25012,12 @@
}
else if (dq_lcd_bdl_value_rdqs_status_a[lane_step]==1)
{
- // temp_s= getenv(env_lcdlr_temp_count);
+ // temp_s= env_get(env_lcdlr_temp_count);
// if(temp_s)
// {
// lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
// }
- lcdlr_temp_count= readl((sticky_reg_base_add+(6<<2)));
+ lcdlr_temp_count= readl((sticky_reg_base_add+(6<<2)));
dq_lcd_bdl_value_rdqs_min_a[lane_step]=lcdlr_temp_count;
dq_lcd_bdl_value_rdqs_status_a[lane_step]=2;
}
@@ -26046,13 +25032,13 @@
i=8+lane_step*8+5;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
//run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
i=8+lane_step*8+7;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
// run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
}
@@ -26060,13 +25046,13 @@
run_command("reset",0);
}
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==2)||
+ if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 2) ||
(dq_lcd_bdl_value_rdqs_status_a[lane_step]==3))
{
{
- if(dq_lcd_bdl_value_rdqs_status_a[lane_step]==2)
- {
+ if (dq_lcd_bdl_value_rdqs_status_a[lane_step] == 2)
+ {
dq_lcd_bdl_value_rdqs_status_a[lane_step]=3;
{
@@ -26074,7 +25060,7 @@
i=8+lane_step*8+7;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
//run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
}
@@ -26083,7 +25069,7 @@
lcdlr_temp_count=0;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s", buf);
- // setenv(env_lcdlr_temp_count, buf);
+ // env_set(env_lcdlr_temp_count, buf);
// run_command("save",0);
writel(num_arry[6],(sticky_reg_base_add+(6<<2)));
}
@@ -26101,12 +25087,12 @@
}
else if (dq_lcd_bdl_value_rdqs_status_a[lane_step]==3)
{
- // temp_s= getenv(env_lcdlr_temp_count);
+ // temp_s= env_get(env_lcdlr_temp_count);
// if(temp_s)
// {
// lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
// }
- lcdlr_temp_count= readl((sticky_reg_base_add+(6<<2)));
+ lcdlr_temp_count= readl((sticky_reg_base_add+(6<<2)));
dq_lcd_bdl_value_rdqs_max_a[lane_step]=lcdlr_temp_count;
dq_lcd_bdl_value_rdqs_status_a[lane_step]=4;
}
@@ -26122,13 +25108,13 @@
i=8+lane_step*8+6;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
//run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
i=8+lane_step*8+7;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
// run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
}
@@ -26138,7 +25124,7 @@
}
/*
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==0xffff)||
+ if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 0xffff) ||
(dq_lcd_bdl_value_rdqs_status_a[lane_step]==0))
{dq_lcd_bdl_value_rdqs_status_a[lane_step]=0;
sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),2);
@@ -26157,7 +25143,7 @@
run_command("reset",0);
}
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==1)||
+ if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 1) ||
(dq_lcd_bdl_value_rdqs_status_a[lane_step]==2))
{dq_lcd_bdl_value_rdqs_status_a[lane_step]=2;
sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),1);
@@ -26175,7 +25161,7 @@
num_to_env(varname,num_arry);
run_command("reset",0);
}
- */
+ */
ddr_test_watchdog_disable(); //s
@@ -26202,12 +25188,12 @@
printf("\ndq_lcd_bdl_value_aclcdlr_status_a %d \n",dq_lcd_bdl_value_aclcdlr_status_a);
lane_step=4;
//env_lcdlr_temp_count="lcdlr_temp_count_a";
- if((dq_lcd_bdl_value_aclcdlr_status_a>=0xffff)
+ if ((dq_lcd_bdl_value_aclcdlr_status_a >= 0xffff)
||(dq_lcd_bdl_value_aclcdlr_status_a==0)
||(dq_lcd_bdl_value_aclcdlr_status_a==1)
)
{
- if((dq_lcd_bdl_value_aclcdlr_status_a>=0xffff)
+ if ((dq_lcd_bdl_value_aclcdlr_status_a >= 0xffff)
||(dq_lcd_bdl_value_aclcdlr_status_a==0))
{ dq_lcd_bdl_value_aclcdlr_status_a=1;
{
@@ -26217,7 +25203,7 @@
printf("aclcdlr_status_a==0x%08x\n",num_arry[i]);
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
//run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
@@ -26226,7 +25212,7 @@
lcdlr_temp_count=0;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s", buf);
- // setenv(env_lcdlr_temp_count, buf);
+ // env_set(env_lcdlr_temp_count, buf);
// run_command("save",0);
writel(num_arry[6],(sticky_reg_base_add+(6<<2)));
}
@@ -26247,7 +25233,7 @@
}
else if (dq_lcd_bdl_value_aclcdlr_status_a==1)
{
- // temp_s= getenv(env_lcdlr_temp_count);
+ // temp_s= env_get(env_lcdlr_temp_count);
// if(temp_s)
// {
//lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
@@ -26268,13 +25254,13 @@
i=8+lane_step*8+1;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
//run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
i=8+lane_step*8+3;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
// run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
}
@@ -26283,7 +25269,7 @@
run_command("reset",0);
}
- if((dq_lcd_bdl_value_aclcdlr_status_a==2)||
+ if ((dq_lcd_bdl_value_aclcdlr_status_a == 2) ||
(dq_lcd_bdl_value_aclcdlr_status_a==3))
{
// if((dq_lcd_bdl_value_wdq_min_a[lane_step])==0xffff)
@@ -26293,14 +25279,14 @@
// }
{
- if(dq_lcd_bdl_value_aclcdlr_status_a==2)
+ if (dq_lcd_bdl_value_aclcdlr_status_a == 2)
{ dq_lcd_bdl_value_aclcdlr_status_a=3;
{
num_arry[8+lane_step*4*2+3]=dq_lcd_bdl_value_aclcdlr_status_a;
i=8+lane_step*8+3;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
//run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
}
@@ -26308,7 +25294,7 @@
lcdlr_temp_count=0;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s", buf);
- // setenv(env_lcdlr_temp_count, buf);
+ // env_set(env_lcdlr_temp_count, buf);
// run_command("save",0);
writel(num_arry[6],(sticky_reg_base_add+(6<<2)));
}
@@ -26326,7 +25312,7 @@
}
else if (dq_lcd_bdl_value_aclcdlr_status_a==3)
{
- // temp_s= getenv(env_lcdlr_temp_count);
+ // temp_s= env_get(env_lcdlr_temp_count);
// if(temp_s)
// {
// lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
@@ -26346,13 +25332,13 @@
i=8+lane_step*8+2;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
//run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
i=8+lane_step*8+3;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
// run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
}
@@ -26363,12 +25349,12 @@
}
- if((dq_lcd_bdl_value_bdlr0_status_a==0xffff)
+ if ((dq_lcd_bdl_value_bdlr0_status_a == 0xffff)
||(dq_lcd_bdl_value_bdlr0_status_a==0)
||(dq_lcd_bdl_value_bdlr0_status_a==1)
)
{
- if((dq_lcd_bdl_value_bdlr0_status_a==0xffff)
+ if ((dq_lcd_bdl_value_bdlr0_status_a == 0xffff)
||(dq_lcd_bdl_value_bdlr0_status_a==0))
{ dq_lcd_bdl_value_bdlr0_status_a=1;
{
@@ -26376,7 +25362,7 @@
i=8+lane_step*8+7;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
//run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
}
@@ -26384,7 +25370,7 @@
lcdlr_temp_count=0;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s", buf);
- // setenv(env_lcdlr_temp_count, buf);
+ // env_set(env_lcdlr_temp_count, buf);
// run_command("save",0);
writel(num_arry[6],(sticky_reg_base_add+(6<<2)));
}
@@ -26402,7 +25388,7 @@
}
else if (dq_lcd_bdl_value_bdlr0_status_a==1)
{
- // temp_s= getenv(env_lcdlr_temp_count);
+ // temp_s= env_get(env_lcdlr_temp_count);
// if(temp_s)
// {
// lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
@@ -26422,13 +25408,13 @@
i=8+lane_step*8+5;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
//run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
i=8+lane_step*8+7;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
// run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
}
@@ -26436,13 +25422,13 @@
run_command("reset",0);
}
- if((dq_lcd_bdl_value_bdlr0_status_a==2)||
+ if ((dq_lcd_bdl_value_bdlr0_status_a == 2) ||
(dq_lcd_bdl_value_bdlr0_status_a==3))
{
{
- if(dq_lcd_bdl_value_bdlr0_status_a==2)
- {
+ if (dq_lcd_bdl_value_bdlr0_status_a == 2)
+ {
dq_lcd_bdl_value_bdlr0_status_a=3;
{
@@ -26450,7 +25436,7 @@
i=8+lane_step*8+7;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
//run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
}
@@ -26459,7 +25445,7 @@
lcdlr_temp_count=0;
sprintf(buf, "0x%08x", lcdlr_temp_count);
printf( "%s", buf);
- // setenv(env_lcdlr_temp_count, buf);
+ // env_set(env_lcdlr_temp_count, buf);
// run_command("save",0);
writel(num_arry[6],(sticky_reg_base_add+(6<<2)));
}
@@ -26477,7 +25463,7 @@
}
else if (dq_lcd_bdl_value_bdlr0_status_a==3)
{
- // temp_s= getenv(env_lcdlr_temp_count);
+ // temp_s= env_get(env_lcdlr_temp_count);
// if(temp_s)
// {
// lcdlr_temp_count= simple_strtoull_ddr(temp_s, &endp, 0);
@@ -26498,13 +25484,13 @@
i=8+lane_step*8+6;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
//run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
i=8+lane_step*8+7;
sprintf(str_temp1,"ddr_test_data_num_%04d",i);
sprintf(str_temp2,"0x%08x",num_arry[i]);
- // setenv(str_temp1, str_temp2);
+ // env_set(str_temp1, str_temp2);
// run_command("save",0);
writel(num_arry[i],(sticky_reg_base_add+(i<<2)));
}
@@ -26514,7 +25500,7 @@
}
/*
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==0xffff)||
+ if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 0xffff) ||
(dq_lcd_bdl_value_rdqs_status_a[lane_step]==0))
{dq_lcd_bdl_value_rdqs_status_a[lane_step]=0;
sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),2);
@@ -26533,7 +25519,7 @@
run_command("reset",0);
}
- if((dq_lcd_bdl_value_rdqs_status_a[lane_step]==1)||
+ if ((dq_lcd_bdl_value_rdqs_status_a[lane_step] == 1) ||
(dq_lcd_bdl_value_rdqs_status_a[lane_step]==2))
{dq_lcd_bdl_value_rdqs_status_a[lane_step]=2;
sprintf(str,"ddr_tune_dqs_step a 0 0x%08x %d %d",ddr_test_size,( lane_step*2+1),1);
@@ -26551,7 +25537,7 @@
num_to_env(varname,num_arry);
run_command("reset",0);
}
- */
+ */
ddr_test_watchdog_disable(); //s
@@ -26690,7 +25676,7 @@
{
char *endp;
unsigned temp_count=0;
- for(;temp_count<argc;temp_count++)
+ for (;temp_count<argc;temp_count++)
{
printf("arg[%d]==%s;\n",argc,argv[temp_count]);
}
@@ -26737,24 +25723,24 @@
reg_add=((data_index>>1)*(DDR0_PUB_DX1LCDLR1-
DDR0_PUB_DX0LCDLR1)
+DDR0_PUB_DX0LCDLR1);
- if((data_index%2)==0)
+ if ((data_index%2) == 0)
{
- if(read_write_flag==DDR_PARAMETER_READ)
+ if (read_write_flag == DDR_PARAMETER_READ)
{
lcdlr_value=((readl(reg_add))&0xff);
}
- if(read_write_flag==DDR_PARAMETER_WRITE)
+ if (read_write_flag == DDR_PARAMETER_WRITE)
{
wr_reg(reg_add, ((readl(reg_add))&0xffffff00)|(lcdlr_value&0xff));
}
}
- if((data_index%2)==1)
+ if ((data_index%2) == 1)
{
- if(read_write_flag==DDR_PARAMETER_READ)
+ if (read_write_flag == DDR_PARAMETER_READ)
{
lcdlr_value=(((readl(reg_add))>>8)&0xff);
}
- if(read_write_flag==DDR_PARAMETER_WRITE)
+ if (read_write_flag == DDR_PARAMETER_WRITE)
{
wr_reg(reg_add, ((readl(reg_add))&0xffff00ff)|((lcdlr_value&0xff)<<8));
}
@@ -26763,25 +25749,25 @@
#else
- if((data_index%2)==0)
+ if ((data_index%2) == 0)
{
reg_add=((data_index>>1)*(DDR0_PUB_DX1LCDLR1-
DDR0_PUB_DX0LCDLR1)
+DDR0_PUB_DX0LCDLR1);
}
- if((data_index%2)==1)
+ if ((data_index%2) == 1)
{
reg_add=((data_index>>1)*(DDR0_PUB_DX1LCDLR1-
DDR0_PUB_DX0LCDLR1)
+DDR0_PUB_DX0LCDLR3);
}
- if(read_write_flag==DDR_PARAMETER_READ)
+ if (read_write_flag == DDR_PARAMETER_READ)
{
lcdlr_value=(((readl(reg_add))>>0)&0x1ff);
}
- if(read_write_flag==DDR_PARAMETER_WRITE)
+ if (read_write_flag == DDR_PARAMETER_WRITE)
{
wr_reg(reg_add, ((lcdlr_value&0x1ff)<<0));
}
@@ -26797,7 +25783,7 @@
return read_value;
-#endif
+#endif
}
unsigned int do_ddr_read_acmdlr(void )
{
@@ -26813,16 +25799,16 @@
{
unsigned reg_add=0;
- if(add_index==0)
+ if (add_index == 0)
reg_add=(DDR0_PUB_ACLCDLR);
- if(add_index==1)
+ if (add_index == 1)
reg_add=(DDR0_PUB_ACBDLR0);
{
- if(read_write_flag==DDR_PARAMETER_READ)
+ if (read_write_flag == DDR_PARAMETER_READ)
{
lcdlr_value=(((readl(reg_add))>>0)&0x1ff);
}
- if(read_write_flag==DDR_PARAMETER_WRITE)
+ if (read_write_flag == DDR_PARAMETER_WRITE)
{
wr_reg(reg_add, ((lcdlr_value&0x1ff)<<0));
}
@@ -26836,7 +25822,7 @@
int do_ddr_uboot_window_use_source_quick_method(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- //setenv bootcmd "ddr_test_cmd 0x31 2 6 20 0 0x100000 0x4000000"
+ //env_set bootcmd "ddr_test_cmd 0x31 2 6 20 0 0x100000 0x4000000"
printf("\nsetenv bootcmd ddr_test_cmd 0x32 2 6 20 0 0x100000 0x4000000 \n");
printf("\nEnter do_ddr_uboot_window_use_source function\n");
printf("\n--- watchdog should >15s\n");
@@ -26888,7 +25874,7 @@
lane_disable= 0;
}
}
- printf("lane_disable==0x%08x\n",lane_disable);
+ printf("lane_disable==0x%08x\n",lane_disable);
if (argc >5) {
ddr_data_test_size = simple_strtoull_ddr(argv[5], &endp, 0);
@@ -26918,11 +25904,11 @@
memset(num_array, 0, sizeof(num_array));
char str[1024]="";
- if(data_source==DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
+ if (data_source == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
ddr_test_data_array_max=64;
- for (temp_count= 0;temp_count < ddr_test_data_array_max; temp_count++)
+ for (temp_count= 0;temp_count < ddr_test_data_array_max; temp_count++)
{
- num_array[temp_count]= read_write_window_test_parameter(data_source,
+ num_array[temp_count]= read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_READ );
printf("read numarry[%d]==%d\n",temp_count,num_array[temp_count]);
}
@@ -26958,7 +25944,7 @@
- if((test_arg_7_magic_number==DMC_STICKY_MAGIC_1)) //for check magic number make sume enter test command
+ if ((test_arg_7_magic_number == DMC_STICKY_MAGIC_1)) //for check magic number make sume enter test command
{
}
else
@@ -26980,26 +25966,26 @@
num_array[6] = test_arg_6_lcdlr_temp_count ;
num_array[7] = test_arg_7_magic_number ;
- for (temp_count= 0;temp_count < 8; temp_count++)
+ for (temp_count= 0;temp_count < 8; temp_count++)
{
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
- if(test_arg_2_step)
+ if (test_arg_2_step)
{
- if(test_arg_3_freq!=global_ddr_clk) //
+ if (test_arg_3_freq != global_ddr_clk) //
{
printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n",global_ddr_clk,test_arg_3_freq);
sprintf(str,"d2pll %d",test_arg_3_freq);
printf("\nstr=%s\n",str);
run_command(str,0);
- while(1);
+ while (1) ;
}
}
- if(test_arg_2_step==0)
+ if (test_arg_2_step == 0)
{
{
test_arg_0_ab_best_lcdlr_value=0;
@@ -27020,9 +26006,9 @@
num_array[7] = test_arg_7_magic_number ;
- for (temp_count= 0;temp_count < 8; temp_count++)
+ for (temp_count= 0;temp_count < 8; temp_count++)
{
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
@@ -27035,9 +26021,9 @@
{
//printf("1temp_count=%d\n",temp_count);
- if((temp_count%4)==0) //org
+ if ((temp_count%4) == 0) //org
{
- if(((temp_count-8)/4)<8)
+ if (((temp_count-8)/4)<8)
{
lcdlr_min=0;
lcdlr_max=(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
@@ -27045,12 +26031,12 @@
//if(lane_step==9)
//lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
}
- else if(((temp_count-8)/4)<10)
+ else if(((temp_count-8)/4)<10)
{
lcdlr_min=0;
lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
//lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
- if(((temp_count-8)/4)==9)
+ if (((temp_count-8)/4) == 9)
lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
}
//printf("2temp_count=%d\n",temp_count);
@@ -27069,9 +26055,9 @@
for (temp_count = 32+8; temp_count < (32+8+8); temp_count++) //add
{
- if((temp_count%4)==0) //org
- {
- if(((temp_count-8)/4)<8)
+ if ((temp_count%4) == 0) //org
+ {
+ if (((temp_count-8)/4)<8)
{
lcdlr_min=0;
lcdlr_max=(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
@@ -27079,12 +26065,12 @@
//if(lane_step==9)
//lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
}
- else if(((temp_count-8)/4)<10)
+ else if(((temp_count-8)/4)<10)
{
lcdlr_min=0;
lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
//lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
- if(((temp_count-8)/4)==9)
+ if (((temp_count-8)/4) == 9)
lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
}
//num_array[temp_count]=0;
@@ -27106,38 +26092,38 @@
printf("DDR0_PUB_DX1GCR0==%x\n",(readl(DDR0_PUB_DX1GCR0)));
printf("DDR0_PUB_DX2GCR0==%x\n",(readl(DDR0_PUB_DX2GCR0)));
printf("DDR0_PUB_DX3GCR0==%x\n",(readl(DDR0_PUB_DX3GCR0)));
- if(((readl(DDR0_PUB_DX0GCR0))&1)==0)
- lane_disable= lane_disable|1;
- if(((readl(DDR0_PUB_DX1GCR0))&1)==0)
- lane_disable= lane_disable|(1<<1);
- if(((readl(DDR0_PUB_DX2GCR0))&1)==0)
- lane_disable= lane_disable|(1<<2);
- if(((readl(DDR0_PUB_DX3GCR0))&1)==0)
- lane_disable= lane_disable|(1<<3);
+ if (((readl(DDR0_PUB_DX0GCR0))&1) == 0)
+ lane_disable= lane_disable|1;
+ if (((readl(DDR0_PUB_DX1GCR0))&1) == 0)
+ lane_disable= lane_disable|(1<<1);
+ if (((readl(DDR0_PUB_DX2GCR0))&1) == 0)
+ lane_disable= lane_disable|(1<<2);
+ if (((readl(DDR0_PUB_DX3GCR0))&1) == 0)
+ lane_disable= lane_disable|(1<<3);
#endif
- if(lane_disable)
+ if (lane_disable)
{if(lane_disable&0x1){
num_array[8+3]=0xffff;
num_array[8+4+3]=0xffff;
}
- if(lane_disable&0x2){
+ if (lane_disable&0x2) {
num_array[8+3+8]=0xffff;
num_array[8+4+3+8]=0xffff;
}
- if(lane_disable&0x4){
+ if (lane_disable&0x4) {
num_array[8+3+8+8]=0xffff;
num_array[8+4+3+8+8]=0xffff;
}
- if(lane_disable&0x8){
+ if (lane_disable&0x8) {
num_array[8+3+8+8+8]=0xffff;
num_array[8+4+3+8+8+8]=0xffff;
}
printf("lane_disable==%x\n",lane_disable);
- if(lane_disable&0x10){
+ if (lane_disable&0x10) {
num_array[8+3+8+8+8+8]=0xffff;
}
- if(lane_disable&0x20){
+ if (lane_disable&0x20) {
num_array[8+4+3+8+8+8+8]=0xffff;
}
@@ -27150,19 +26136,19 @@
for (temp_count= 0; temp_count< 48;temp_count++) {
- num_array[temp_count]= read_write_window_test_parameter(data_source,
+ num_array[temp_count]= read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
}
test_arg_2_step++;
num_array[2]=test_arg_2_step;
- for (temp_count = 1; temp_count < 48; temp_count++)
+ for (temp_count = 1; temp_count < 48; temp_count++)
{
printf("%d %d\n", temp_count,num_array[temp_count]);
}
temp_count=2;
- num_array[temp_count]= read_write_window_test_parameter(data_source,
+ num_array[temp_count]= read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
//for (i = 0; i < 48; i++) {
@@ -27182,14 +26168,14 @@
for ((lane_step=0);(lane_step<10);(lane_step++)) //find need test data step
{
- if((num_array[(lane_step<<2)+3+8]<0x4))
+ if ((num_array[(lane_step<<2)+3+8]<0x4))
{break;
}
}
printf("\nstart test lane_step =%d\n",lane_step);
- if(lane_step<10)
+ if (lane_step<10)
{
- if(lane_step<8)
+ if (lane_step<8)
{
test_watchdog_time_s=watchdog_time_s;
ddr_test_size=ddr_data_test_size;
@@ -27207,7 +26193,7 @@
//lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
}
- if((num_array[8+(lane_step<<2)+3]==0)) //test left edge begin
+ if ((num_array[8+(lane_step<<2)+3] == 0)) //test left edge begin
{
/*
num_array[1] = test_arg_1_test_error_flag ;//1 pass 2 error
@@ -27221,23 +26207,23 @@
// test_arg_0_ab_best_lcdlr_value=(num_array[8+(lane_step<<2)+0]);
// num_array[0]=test_arg_0_ab_best_lcdlr_value;
// temp_count=0;
- // read_write_window_test_parameter(data_source,
+ // read_write_window_test_parameter(data_source,
// temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[5]=(num_array[8+(lane_step<<2)+1]); //edge lcdlr
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- (num_array[8+(lane_step<<2)+1])=(num_array[8+(lane_step<<2)+0]);
+ (num_array[8+(lane_step<<2)+1])=(num_array[8+(lane_step<<2)+0]);
temp_count=8+(lane_step<<2)+1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
@@ -27254,7 +26240,7 @@
ddr_test_watchdog_enable(test_watchdog_time_s); //s
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -27265,75 +26251,75 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_PASS; //pass 2 error 1
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
else if((num_array[8+(lane_step<<2)+3]==1)) //test left edge ongoing -loop
{
- if((num_array[5]+1)>=(num_array[6]))
+ if ((num_array[5]+1) >= (num_array[6]))
{
- if(num_array[1]==DDR_TEST_NULL)
+ if (num_array[1] == DDR_TEST_NULL)
{printf("default value not stable ,or recovery sticky?\n");
}
num_array[8+(lane_step<<2)+3]=2; //update status
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[5]=0; //update edge lcdlr
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[1]==DDR_TEST_FAIL)
+ if (num_array[1] == DDR_TEST_FAIL)
num_array[8+(lane_step<<2)+1]=num_array[6]+1; //update B
- if(num_array[1]==DDR_TEST_PASS)
+ if (num_array[1] == DDR_TEST_PASS)
num_array[8+(lane_step<<2)+1]=num_array[6]; //update B
temp_count=8+(lane_step<<2)+1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
test_arg_6_lcdlr_temp_count=0; //curren_test +B //(A+B)/2
num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
temp_count=1; //update test error flag
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
// test_arg_0_ab_best_lcdlr_value=0;//(num_array[8+(lane_step<<2)+0]);
// num_array[0]=test_arg_0_ab_best_lcdlr_value;
// temp_count=0;
- // read_write_window_test_parameter(data_source,
+ // read_write_window_test_parameter(data_source,
// temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- run_command("reset",0);
- while(1);
+ run_command("reset",0);
+ while (1) ;
}
- else
- {
- if(num_array[1]==DDR_TEST_NULL)
+ else
+ {
+ if (num_array[1] == DDR_TEST_NULL)
{printf("default value not stable ,or recovery sticky?\n");
}
else if(num_array[1]==DDR_TEST_FAIL)
@@ -27344,34 +26330,34 @@
{
num_array[8+(lane_step<<2)+3]=1; //update status
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[5]=num_array[6]; //update edge lcdlr
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1); //curren_test +B //(A+B)/2
num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
// num_array[8+(lane_step<<2)+1]=num_array[8+(lane_step<<2)+1]; //update B
// temp_count=8+(lane_step<<2)+1;
- // read_write_window_test_parameter(data_source,
+ // read_write_window_test_parameter(data_source,
// temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
temp_count=1; //update test error flag
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
ddr_test_watchdog_enable(test_watchdog_time_s); //s
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -27382,23 +26368,23 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_PASS; //pass 2 error 1
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
@@ -27408,29 +26394,29 @@
{
num_array[8+(lane_step<<2)+3]=1; //update status
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[8+(lane_step<<2)+1]=num_array[6]; //update min value
temp_count=8+(lane_step<<2)+1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1); //curren_test +B //(A+B)/2
num_array[6]=test_arg_6_lcdlr_temp_count; // --update curent
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
temp_count=1; //update test error flag
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
ddr_test_watchdog_enable(test_watchdog_time_s); //s
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -27441,23 +26427,23 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_PASS; //pass 2 error 1
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
- while(1);
+ while (1) ;
}
@@ -27481,17 +26467,17 @@
num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[5]=num_array[8+(lane_step<<2)+2];//lcdlr_max; //edge lcdlr
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[8+(lane_step<<2)+2]=num_array[8+(lane_step<<2)+0];//
temp_count=8+(lane_step<<2)+2;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1);
@@ -27507,7 +26493,7 @@
ddr_test_watchdog_enable(test_watchdog_time_s); //s
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -27518,67 +26504,67 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_PASS; //pass 2 error 1
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
else if((num_array[8+(lane_step<<2)+3]==3)) //test right edge ongoing -loop
{
- if((num_array[6]+1)>=(num_array[5]))
+ if ((num_array[6]+1) >= (num_array[5]))
{
- if(num_array[1]==DDR_TEST_NULL)
+ if (num_array[1] == DDR_TEST_NULL)
{printf("default value not stable ,or recovery sticky?\n");
}
num_array[8+(lane_step<<2)+3]=4; //update status
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[5]=0; //update edge lcdlr
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[1]==DDR_TEST_FAIL)
+ if (num_array[1] == DDR_TEST_FAIL)
num_array[8+(lane_step<<2)+2]=num_array[6]-1; //update B
- if(num_array[1]==DDR_TEST_PASS)
+ if (num_array[1] == DDR_TEST_PASS)
num_array[8+(lane_step<<2)+2]=num_array[6]; //update B
temp_count=8+(lane_step<<2)+2;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
test_arg_6_lcdlr_temp_count=0; //curren_test +B //(A+B)/2
num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
temp_count=1; //update test error flag
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- run_command("reset",0);
- while(1);
+ run_command("reset",0);
+ while (1) ;
}
- else
- {
- if(num_array[1]==DDR_TEST_NULL)
+ else
+ {
+ if (num_array[1] == DDR_TEST_NULL)
{printf("default value not stable ,or recovery sticky?\n");
}
else if(num_array[1]==DDR_TEST_FAIL)
@@ -27589,34 +26575,34 @@
{
num_array[8+(lane_step<<2)+3]=3; //update status
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[5]=num_array[6]; //update edge lcdlr
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1); //curren_test +B //(A+B)/2
num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
// num_array[8+(lane_step<<2)+1]=num_array[8+(lane_step<<2)+1]; //update B
// temp_count=8+(lane_step<<2)+1;
- // read_write_window_test_parameter(data_source,
+ // read_write_window_test_parameter(data_source,
// temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
temp_count=1; //update test error flag
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
ddr_test_watchdog_enable(test_watchdog_time_s); //s
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -27627,23 +26613,23 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_PASS; //pass 2 error 1
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
@@ -27653,29 +26639,29 @@
{
num_array[8+(lane_step<<2)+3]=3; //update status
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[8+(lane_step<<2)+2]=num_array[6]; //update max value
temp_count=8+(lane_step<<2)+2;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1); //curren_test +B //(A+B)/2
num_array[6]=test_arg_6_lcdlr_temp_count; // --update curent
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
temp_count=1; //update test error flag
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
ddr_test_watchdog_enable(test_watchdog_time_s); //s
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -27686,23 +26672,23 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_PASS; //pass 2 error 1
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
- while(1);
+ while (1) ;
}
@@ -27713,7 +26699,7 @@
}
}
- if(lane_step>=10) //finish
+ if (lane_step >= 10) //finish
{
ddr_test_watchdog_disable(); //s
printf("close watchdog\n");
@@ -27815,7 +26801,7 @@
temp_count=2;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
return 1;
@@ -27824,7 +26810,7 @@
int do_ddr_uboot_window_use_source(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- //setenv bootcmd "ddr_test_cmd 0x31 2 6 20 0 0x100000 0x4000000"
+ //env_set bootcmd "ddr_test_cmd 0x31 2 6 20 0 0x100000 0x4000000"
printf("\nsetenv bootcmd ddr_test_cmd 0x31 2 6 20 0 0x100000 0x4000000 \n");
printf("\nEnter do_ddr_uboot_window_use_source function\n");
printf("\n--- watchdog should >15s\n");
@@ -27873,7 +26859,7 @@
lane_disable= 0;
}
}
- printf("lane_disable==0x%08x\n",lane_disable);
+ printf("lane_disable==0x%08x\n",lane_disable);
if (argc >5) {
ddr_data_test_size = simple_strtoull_ddr(argv[5], &endp, 0);
@@ -27903,11 +26889,11 @@
memset(num_array, 0, sizeof(num_array));
char str[1024]="";
- if(data_source==DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
+ if (data_source == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
ddr_test_data_array_max=64;
- for (temp_count= 0;temp_count < ddr_test_data_array_max; temp_count++)
+ for (temp_count= 0;temp_count < ddr_test_data_array_max; temp_count++)
{
- num_array[temp_count]= read_write_window_test_parameter(data_source,
+ num_array[temp_count]= read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_READ );
printf("read numarry[%d]==%d\n",temp_count,num_array[temp_count]);
}
@@ -27943,7 +26929,7 @@
- if((test_arg_7_magic_number==DMC_STICKY_MAGIC_1)) //for check magic number make sume enter test command
+ if ((test_arg_7_magic_number == DMC_STICKY_MAGIC_1)) //for check magic number make sume enter test command
{test_arg_5_boottimes++;
}
@@ -27963,26 +26949,26 @@
num_array[6] = test_arg_6_lcdlr_temp_count ;
num_array[7] = test_arg_7_magic_number ;
- for (temp_count= 0;temp_count < 8; temp_count++)
+ for (temp_count= 0;temp_count < 8; temp_count++)
{
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
- if(test_arg_2_step)
+ if (test_arg_2_step)
{
- if(test_arg_3_freq!=global_ddr_clk) //
+ if (test_arg_3_freq != global_ddr_clk) //
{
printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n",global_ddr_clk,test_arg_3_freq);
sprintf(str,"d2pll %d",test_arg_3_freq);
printf("\nstr=%s\n",str);
run_command(str,0);
- while(1);
+ while (1) ;
}
}
- if(test_arg_2_step==0)
+ if (test_arg_2_step == 0)
{
{
test_arg_0_cmd0=0X31;//DDR_TEST_CMD__DDR_SET_UBOOT_KERNEL_WINDOW;
@@ -28000,9 +26986,9 @@
num_array[6] = test_arg_6_lcdlr_temp_count ;
num_array[7] = test_arg_7_magic_number ;
- for (temp_count= 0;temp_count < 8; temp_count++)
+ for (temp_count= 0;temp_count < 8; temp_count++)
{
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
@@ -28014,7 +27000,7 @@
for (temp_count = 8; temp_count < (32+8); temp_count++) //data
{
//printf("1temp_count=%d\n",temp_count);
- if((temp_count%4)==0) //org
+ if ((temp_count%4) == 0) //org
{
//printf("2temp_count=%d\n",temp_count);
//num_array[temp_count]=0;
@@ -28022,16 +27008,16 @@
num_array[temp_count]=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,((temp_count-8)>>2),num_array[temp_count],DDR_PARAMETER_READ);
}
- if((temp_count%4)==1) //min
- {
+ if ((temp_count%4) == 1) //min
+ {
num_array[temp_count]=0;
}
- if((temp_count%4)==2) //max
- {
+ if ((temp_count%4) == 2) //max
+ {
num_array[temp_count]=acmdlr;
}
- if((temp_count%4)==3) //status
- {
+ if ((temp_count%4) == 3) //status
+ {
num_array[temp_count]=0;
}
@@ -28040,25 +27026,25 @@
for (temp_count = 32+8; temp_count < (32+8+8); temp_count++) //add
{
- if((temp_count%4)==0) //org
- {
+ if ((temp_count%4) == 0) //org
+ {
//num_array[temp_count]=0;
//unsigned int do_ddr_read_write_ddr_data_window_lcdlr(unsigned int rank_index,unsigned int data_add_index,unsigned int lcdlr_value,unsigned int read_write_flag ))
num_array[temp_count]=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,((temp_count-8-32)>>2),num_array[temp_count],DDR_PARAMETER_READ);
}
- if((temp_count%4)==1) //min
- {
+ if ((temp_count%4) == 1) //min
+ {
num_array[temp_count]=0;
}
- if((temp_count%4)==2) //max
- {
+ if ((temp_count%4) == 2) //max
+ {
num_array[temp_count]=acmdlr*3;
- if(temp_count==(32+8+4+2))
+ if (temp_count == (32+8+4+2))
num_array[temp_count]=0x3f;//bdlr0 max value
}
- if((temp_count%4)==3) //status
- {
+ if ((temp_count%4) == 3) //status
+ {
num_array[temp_count]=0;
}
@@ -28073,38 +27059,38 @@
printf("DDR0_PUB_DX1GCR0==%x\n",(readl(DDR0_PUB_DX1GCR0)));
printf("DDR0_PUB_DX2GCR0==%x\n",(readl(DDR0_PUB_DX2GCR0)));
printf("DDR0_PUB_DX3GCR0==%x\n",(readl(DDR0_PUB_DX3GCR0)));
- if(((readl(DDR0_PUB_DX0GCR0))&1)==0)
- lane_disable= lane_disable|1;
- if(((readl(DDR0_PUB_DX1GCR0))&1)==0)
- lane_disable= lane_disable|(1<<1);
- if(((readl(DDR0_PUB_DX2GCR0))&1)==0)
- lane_disable= lane_disable|(1<<2);
- if(((readl(DDR0_PUB_DX3GCR0))&1)==0)
- lane_disable= lane_disable|(1<<3);
+ if (((readl(DDR0_PUB_DX0GCR0))&1) == 0)
+ lane_disable= lane_disable|1;
+ if (((readl(DDR0_PUB_DX1GCR0))&1) == 0)
+ lane_disable= lane_disable|(1<<1);
+ if (((readl(DDR0_PUB_DX2GCR0))&1) == 0)
+ lane_disable= lane_disable|(1<<2);
+ if (((readl(DDR0_PUB_DX3GCR0))&1) == 0)
+ lane_disable= lane_disable|(1<<3);
#endif
- if(lane_disable)
+ if (lane_disable)
{if(lane_disable&0x1){
num_array[8+3]=0xffff;
num_array[8+4+3]=0xffff;
}
- if(lane_disable&0x2){
+ if (lane_disable&0x2) {
num_array[8+3+8]=0xffff;
num_array[8+4+3+8]=0xffff;
}
- if(lane_disable&0x4){
+ if (lane_disable&0x4) {
num_array[8+3+8+8]=0xffff;
num_array[8+4+3+8+8]=0xffff;
}
- if(lane_disable&0x8){
+ if (lane_disable&0x8) {
num_array[8+3+8+8+8]=0xffff;
num_array[8+4+3+8+8+8]=0xffff;
}
printf("lane_disable==%x\n",lane_disable);
- if(lane_disable&0x10){
+ if (lane_disable&0x10) {
num_array[8+3+8+8+8+8]=0xffff;
}
- if(lane_disable&0x20){
+ if (lane_disable&0x20) {
num_array[8+4+3+8+8+8+8]=0xffff;
}
@@ -28117,19 +27103,19 @@
for (temp_count= 0; temp_count< 48;temp_count++) {
- num_array[temp_count]= read_write_window_test_parameter(data_source,
+ num_array[temp_count]= read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
}
test_arg_2_step++;
num_array[2]=test_arg_2_step;
- for (temp_count = 1; temp_count < 48; temp_count++)
+ for (temp_count = 1; temp_count < 48; temp_count++)
{
printf("%d %d\n", temp_count,num_array[temp_count]);
}
temp_count=2;
- num_array[temp_count]= read_write_window_test_parameter(data_source,
+ num_array[temp_count]= read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
//for (i = 0; i < 48; i++) {
@@ -28149,14 +27135,14 @@
for ((lane_step=0);(lane_step<10);(lane_step++)) //find need test data step
{
- if((num_array[(lane_step<<2)+3+8]<0x4))
+ if ((num_array[(lane_step<<2)+3+8]<0x4))
{break;
}
}
printf("\nstart test lane_step =%d\n",lane_step);
- if(lane_step<10)
+ if (lane_step<10)
{
- if(lane_step<8)
+ if (lane_step<8)
{
test_watchdog_time_s=watchdog_time_s;
ddr_test_size=ddr_data_test_size;
@@ -28171,22 +27157,22 @@
lcdlr_max=(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
}
- if((num_array[8+(lane_step<<2)+3]==0)) //test left edge begin
+ if ((num_array[8+(lane_step<<2)+3] == 0)) //test left edge begin
{
num_array[8+(lane_step<<2)+3]=1;
test_arg_6_lcdlr_temp_count=lcdlr_min;
num_array[6]=test_arg_6_lcdlr_temp_count;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
ddr_test_watchdog_enable(test_watchdog_time_s); //s
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -28202,7 +27188,7 @@
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
@@ -28211,19 +27197,19 @@
num_array[8+(lane_step<<2)+3]=2; //left finish
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
temp_count=8+(lane_step<<2)+1;
num_array[temp_count]=test_arg_6_lcdlr_temp_count;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
test_arg_6_lcdlr_temp_count=0;
num_array[6]=test_arg_6_lcdlr_temp_count;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
@@ -28238,15 +27224,15 @@
num_array[6]=test_arg_6_lcdlr_temp_count;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
ddr_test_watchdog_enable(test_watchdog_time_s); //s
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -28262,7 +27248,7 @@
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
@@ -28270,19 +27256,19 @@
num_array[8+(lane_step<<2)+3]=2; //left finish
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
temp_count=8+(lane_step<<2)+1;
num_array[temp_count]=test_arg_6_lcdlr_temp_count;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
test_arg_6_lcdlr_temp_count=0;
num_array[6]=test_arg_6_lcdlr_temp_count;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
@@ -28297,15 +27283,15 @@
num_array[6]=test_arg_6_lcdlr_temp_count;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
ddr_test_watchdog_enable(test_watchdog_time_s); //s
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -28321,7 +27307,7 @@
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
@@ -28329,19 +27315,19 @@
num_array[8+(lane_step<<2)+3]=4; //right finish
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
temp_count=8+(lane_step<<2)+2;
num_array[temp_count]=test_arg_6_lcdlr_temp_count;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
test_arg_6_lcdlr_temp_count=0;
num_array[6]=test_arg_6_lcdlr_temp_count;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
@@ -28356,15 +27342,15 @@
num_array[6]=test_arg_6_lcdlr_temp_count;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
ddr_test_watchdog_enable(test_watchdog_time_s); //s
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -28380,7 +27366,7 @@
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
@@ -28388,19 +27374,19 @@
num_array[8+(lane_step<<2)+3]=4; //right finish
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
temp_count=8+(lane_step<<2)+2;
num_array[temp_count]=test_arg_6_lcdlr_temp_count;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
test_arg_6_lcdlr_temp_count=0;
num_array[6]=test_arg_6_lcdlr_temp_count;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
@@ -28410,7 +27396,7 @@
}
}
- if(lane_step>=10) //finish
+ if (lane_step >= 10) //finish
{
ddr_test_watchdog_disable(); //s
printf("close watchdog\n");
@@ -28512,7 +27498,7 @@
temp_count=2;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
return 1;
@@ -28521,7 +27507,7 @@
int do_ddr_uboot_kernel_window_use_source_quick_method(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- //setenv storeboot "ddr_test_cmd 0x33 2 6 20 0 0x100000 0x4000000"
+ //env_set storeboot "ddr_test_cmd 0x33 2 6 20 0 0x100000 0x4000000"
printf("\nsetenv bootcmd ddr_test_cmd 0x33 2 6 20 0 0x100000 0x4000000 \n");
printf("\nEnter do_ddr_uboot_window_use_source function\n");
printf("\n--- watchdog should >15s\n");
@@ -28590,7 +27576,7 @@
lane_disable= 0;
}
}
- printf("lane_disable==0x%08x\n",lane_disable);
+ printf("lane_disable==0x%08x\n",lane_disable);
if (argc >5) {
ddr_data_test_size = simple_strtoull_ddr(argv[5], &endp, 0);
@@ -28636,11 +27622,11 @@
memset(num_array, 0, sizeof(num_array));
char str[1024]="";
- if(data_source==DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
+ if (data_source == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
ddr_test_data_array_max=64;
- for (temp_count= 0;temp_count < ddr_test_data_array_max; temp_count++)
+ for (temp_count= 0;temp_count < ddr_test_data_array_max; temp_count++)
{
- num_array[temp_count]= read_write_window_test_parameter(data_source,
+ num_array[temp_count]= read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_READ );
printf("read numarry[%d]==%d\n",temp_count,num_array[temp_count]);
}
@@ -28676,7 +27662,7 @@
- if((test_arg_7_magic_number==DMC_STICKY_MAGIC_1)) //for check magic number make sume enter test command
+ if ((test_arg_7_magic_number == DMC_STICKY_MAGIC_1)) //for check magic number make sume enter test command
{
}
else
@@ -28698,26 +27684,26 @@
num_array[6] = test_arg_6_lcdlr_temp_count ;
num_array[7] = test_arg_7_magic_number ;
- for (temp_count= 0;temp_count < 8; temp_count++)
+ for (temp_count= 0;temp_count < 8; temp_count++)
{
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
- if(test_arg_2_step)
+ if (test_arg_2_step)
{
- if(test_arg_3_freq!=global_ddr_clk) //
+ if (test_arg_3_freq != global_ddr_clk) //
{
printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n",global_ddr_clk,test_arg_3_freq);
sprintf(str,"d2pll %d",test_arg_3_freq);
printf("\nstr=%s\n",str);
run_command(str,0);
- while(1);
+ while (1) ;
}
}
- if(test_arg_2_step==0)
+ if (test_arg_2_step == 0)
{
{
@@ -28741,13 +27727,13 @@
num_array[7] = test_arg_7_magic_number ;
- for (temp_count= 0;temp_count < 8; temp_count++)
+ for (temp_count= 0;temp_count < 8; temp_count++)
{
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
- // read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ // read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
// DDR_TEST_STATUS_STEP_FLAG_ADD_ORG_STICKY_OFFSET ,test_arg_2_step,DDR_PARAMETER_WRITE);
//for (temp_count = 8; temp_count< 48;temp_count++) {
// num_array[temp_count]=0;
@@ -28757,9 +27743,9 @@
{
//printf("1temp_count=%d\n",temp_count);
- if((temp_count%4)==0) //org
+ if ((temp_count%4) == 0) //org
{
- if(((temp_count-8)/4)<8)
+ if (((temp_count-8)/4)<8)
{
lcdlr_min=0;
lcdlr_max=(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
@@ -28767,12 +27753,12 @@
//if(lane_step==9)
//lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
}
- else if(((temp_count-8)/4)<10)
+ else if(((temp_count-8)/4)<10)
{
lcdlr_min=0;
lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
//lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
- if(((temp_count-8)/4)==9)
+ if (((temp_count-8)/4) == 9)
lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
}
//printf("2temp_count=%d\n",temp_count);
@@ -28791,9 +27777,9 @@
for (temp_count = 32+8; temp_count < (32+8+8); temp_count++) //add
{
- if((temp_count%4)==0) //org
- {
- if(((temp_count-8)/4)<8)
+ if ((temp_count%4) == 0) //org
+ {
+ if (((temp_count-8)/4)<8)
{
lcdlr_min=0;
lcdlr_max=(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
@@ -28801,12 +27787,12 @@
//if(lane_step==9)
//lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
}
- else if(((temp_count-8)/4)<10)
+ else if(((temp_count-8)/4)<10)
{
lcdlr_min=0;
lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
//lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
- if(((temp_count-8)/4)==9)
+ if (((temp_count-8)/4) == 9)
lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
}
//num_array[temp_count]=0;
@@ -28828,38 +27814,38 @@
printf("DDR0_PUB_DX1GCR0==%x\n",(readl(DDR0_PUB_DX1GCR0)));
printf("DDR0_PUB_DX2GCR0==%x\n",(readl(DDR0_PUB_DX2GCR0)));
printf("DDR0_PUB_DX3GCR0==%x\n",(readl(DDR0_PUB_DX3GCR0)));
- if(((readl(DDR0_PUB_DX0GCR0))&1)==0)
- lane_disable= lane_disable|1;
- if(((readl(DDR0_PUB_DX1GCR0))&1)==0)
- lane_disable= lane_disable|(1<<1);
- if(((readl(DDR0_PUB_DX2GCR0))&1)==0)
- lane_disable= lane_disable|(1<<2);
- if(((readl(DDR0_PUB_DX3GCR0))&1)==0)
- lane_disable= lane_disable|(1<<3);
+ if (((readl(DDR0_PUB_DX0GCR0))&1) == 0)
+ lane_disable= lane_disable|1;
+ if (((readl(DDR0_PUB_DX1GCR0))&1) == 0)
+ lane_disable= lane_disable|(1<<1);
+ if (((readl(DDR0_PUB_DX2GCR0))&1) == 0)
+ lane_disable= lane_disable|(1<<2);
+ if (((readl(DDR0_PUB_DX3GCR0))&1) == 0)
+ lane_disable= lane_disable|(1<<3);
#endif
- if(lane_disable)
+ if (lane_disable)
{if(lane_disable&0x1){
num_array[8+3]=0xffff;
num_array[8+4+3]=0xffff;
}
- if(lane_disable&0x2){
+ if (lane_disable&0x2) {
num_array[8+3+8]=0xffff;
num_array[8+4+3+8]=0xffff;
}
- if(lane_disable&0x4){
+ if (lane_disable&0x4) {
num_array[8+3+8+8]=0xffff;
num_array[8+4+3+8+8]=0xffff;
}
- if(lane_disable&0x8){
+ if (lane_disable&0x8) {
num_array[8+3+8+8+8]=0xffff;
num_array[8+4+3+8+8+8]=0xffff;
}
printf("lane_disable==%x\n",lane_disable);
- if(lane_disable&0x10){
+ if (lane_disable&0x10) {
num_array[8+3+8+8+8+8]=0xffff;
}
- if(lane_disable&0x20){
+ if (lane_disable&0x20) {
num_array[8+4+3+8+8+8+8]=0xffff;
}
@@ -28872,21 +27858,21 @@
for (temp_count= 0; temp_count< 48;temp_count++) {
- num_array[temp_count]= read_write_window_test_parameter(data_source,
+ num_array[temp_count]= read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
}
//test_arg_2_step++;
num_array[2]=test_arg_2_step;
- for (temp_count = 1; temp_count < 48; temp_count++)
+ for (temp_count = 1; temp_count < 48; temp_count++)
{
printf("%d %d\n", temp_count,num_array[temp_count]);
}
temp_count=2;
- num_array[temp_count]= read_write_window_test_parameter(data_source,
+ num_array[temp_count]= read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- // read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ // read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
// DDR_TEST_STATUS_STEP_FLAG_ADD_ORG_STICKY_OFFSET ,test_arg_2_step,DDR_PARAMETER_WRITE);
//for (i = 0; i < 48; i++) {
@@ -28906,15 +27892,15 @@
for ((lane_step=0);(lane_step<10);(lane_step++)) //find need test data step
{
- if(test_arg_2_step<DDR_TEST_STATUS_KERNEL_ONGING)
+ if (test_arg_2_step<DDR_TEST_STATUS_KERNEL_ONGING)
{
- if((num_array[(lane_step<<2)+3+8]<(0x4)))
+ if ((num_array[(lane_step<<2)+3+8]<(0x4)))
{break;
}
}
}
- if(test_arg_2_step==DDR_TEST_STATUS_UBOOT_ONGOING)
+ if (test_arg_2_step == DDR_TEST_STATUS_UBOOT_ONGOING)
{if(lane_step>9)
{
test_arg_2_step=DDR_TEST_STATUS_UBOOT_FINISH;
@@ -28922,29 +27908,29 @@
}
}
- if(test_arg_2_step>DDR_TEST_STATUS_UBOOT_FINISH)
+ if (test_arg_2_step>DDR_TEST_STATUS_UBOOT_FINISH)
{
for ((lane_step=0);(lane_step<10);(lane_step++)) //find need test data step
{
{
- if((num_array[(lane_step<<2)+3+8]<(0x4+4)))
+ if ((num_array[(lane_step<<2)+3+8]<(0x4+4)))
{break;
}
}
}
}
- if(test_arg_2_step==DDR_TEST_STATUS_UBOOT_FINISH)//||(test_arg_2_step==DDR_TEST_STATUS_KERNEL_FINISH)
+ if (test_arg_2_step == DDR_TEST_STATUS_UBOOT_FINISH)// || (test_arg_2_step == DDR_TEST_STATUS_KERNEL_FINISH)
{
//test_arg_2_step=DDR_TEST_STATUS_KERNEL_ONGING;
}
else
{
printf("\nstart test lane_step =%d\n",lane_step);
- if(lane_step<10)
+ if (lane_step<10)
{
- if(lane_step<8)
+ if (lane_step<8)
{
test_watchdog_time_s=watchdog_time_s;
ddr_test_size=ddr_data_test_size;
@@ -28964,15 +27950,15 @@
//lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
}
- if(num_array[8+(lane_step<<2)+3]>4) //from kernel
+ if (num_array[8+(lane_step<<2)+3]>4) //from kernel
{
- num_array[1]= read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ num_array[1]= read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_READ);
- // read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ // read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
// DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
- if(((num_array[8+(lane_step<<2)+3]==0))||((num_array[8+(lane_step<<2)+3]==4))) //test left edge begin
+ if (((num_array[8+(lane_step<<2)+3] == 0)) || ((num_array[8+(lane_step<<2)+3] == 4))) //test left edge begin
{
/*
num_array[1] = test_arg_1_test_error_flag ;//1 pass 2 error
@@ -28986,35 +27972,35 @@
// test_arg_0_ab_best_lcdlr_value=(num_array[8+(lane_step<<2)+0]);
// num_array[0]=test_arg_0_ab_best_lcdlr_value;
// temp_count=0;
- // read_write_window_test_parameter(data_source,
+ // read_write_window_test_parameter(data_source,
// temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
- read_write_window_test_flag(data_source,
+ read_write_window_test_flag(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[5]=(num_array[8+(lane_step<<2)+1]); //edge lcdlr
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- (num_array[8+(lane_step<<2)+1])=(num_array[8+(lane_step<<2)+0]);
+ (num_array[8+(lane_step<<2)+1])=(num_array[8+(lane_step<<2)+0]);
temp_count=8+(lane_step<<2)+1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(ddr_test_method==DDR_TEST_METHOD_DIVIDER_2)
+ if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+0])>>1);
else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
test_arg_6_lcdlr_temp_count=((num_array[5])+1);
@@ -29035,7 +28021,7 @@
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
}
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -29051,98 +28037,98 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
- if( num_array[8+(lane_step<<2)+3]>4)
+ if ( num_array[8+(lane_step<<2)+3]>4)
{
ddr_test_watchdog_disable(); //s
run_command("run storeboot",0);
- while(1);
+ while (1) ;
}
else
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_PASS; //pass 2 error 1
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
}
else if((num_array[8+(lane_step<<2)+3]==1)||((num_array[8+(lane_step<<2)+3]==5))) //test left edge begin) //test left edge ongoing -loop
{
- if((num_array[6]+1)>=(num_array[8+(lane_step<<2)+1]))
+ if ((num_array[6]+1) >= (num_array[8+(lane_step<<2)+1]))
{
- if(num_array[1]==DDR_TEST_NULL)
+ if (num_array[1] == DDR_TEST_NULL)
{printf("default value not stable ,or recovery sticky?\n");
}
num_array[8+(lane_step<<2)+3]= num_array[8+(lane_step<<2)+3]+1; //update status
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[5]=0; //update edge lcdlr
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[1]==DDR_TEST_FAIL)
+ if (num_array[1] == DDR_TEST_FAIL)
num_array[8+(lane_step<<2)+1]=num_array[6]+1; //update B
- if(num_array[1]==DDR_TEST_PASS)
+ if (num_array[1] == DDR_TEST_PASS)
num_array[8+(lane_step<<2)+1]=num_array[6]; //update B
temp_count=8+(lane_step<<2)+1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
test_arg_6_lcdlr_temp_count=0; //curren_test +B //(A+B)/2
num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
temp_count=1; //update test error flag
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- // num_array[1]= read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ // num_array[1]= read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
// DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_READ);
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
// test_arg_0_ab_best_lcdlr_value=0;//(num_array[8+(lane_step<<2)+0]);
// num_array[0]=test_arg_0_ab_best_lcdlr_value;
// temp_count=0;
- // read_write_window_test_parameter(data_source,
+ // read_write_window_test_parameter(data_source,
// temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- run_command("reset",0);
- while(1);
+ run_command("reset",0);
+ while (1) ;
}
- else
- {
- if(num_array[1]==DDR_TEST_NULL)
+ else
+ {
+ if (num_array[1] == DDR_TEST_NULL)
{printf("default value not stable ,or recovery sticky?\n");
}
else if(num_array[1]==DDR_TEST_FAIL)
@@ -29153,37 +28139,37 @@
{
// num_array[8+(lane_step<<2)+3]=1; //update status
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[5]=num_array[6]; //update edge lcdlr
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(ddr_test_method==DDR_TEST_METHOD_DIVIDER_2)
+ if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1);
else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
test_arg_6_lcdlr_temp_count=((num_array[5])+1);
// test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1); //curren_test +B //(A+B)/2
num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
// num_array[8+(lane_step<<2)+1]=num_array[8+(lane_step<<2)+1]; //update B
// temp_count=8+(lane_step<<2)+1;
- // read_write_window_test_parameter(data_source,
+ // read_write_window_test_parameter(data_source,
// temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
temp_count=1; //update test error flag
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
@@ -29191,7 +28177,7 @@
ddr_test_watchdog_enable(test_watchdog_time_s); //s
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -29202,40 +28188,40 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
- if( num_array[8+(lane_step<<2)+3]>4)
+ if ( num_array[8+(lane_step<<2)+3]>4)
{
ddr_test_watchdog_disable(); //s
run_command("run storeboot",0);
- while(1);
+ while (1) ;
}
else
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_PASS; //pass 2 error 1
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
@@ -29246,32 +28232,32 @@
{
// num_array[8+(lane_step<<2)+3]=1; //update status
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[8+(lane_step<<2)+1]=num_array[6]; //update min value
temp_count=8+(lane_step<<2)+1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(ddr_test_method==DDR_TEST_METHOD_DIVIDER_2)
+ if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1);
else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
test_arg_6_lcdlr_temp_count=((num_array[5])+1);
// test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1); //curren_test +B //(A+B)/2
num_array[6]=test_arg_6_lcdlr_temp_count; // --update curent
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
temp_count=1; //update test error flag
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
@@ -29279,7 +28265,7 @@
ddr_test_watchdog_enable(test_watchdog_time_s); //s
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -29290,38 +28276,38 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
- if( num_array[8+(lane_step<<2)+3]>4)
+ if ( num_array[8+(lane_step<<2)+3]>4)
{
ddr_test_watchdog_disable(); //s
run_command("run storeboot",0);
- while(1);
+ while (1) ;
}
else
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_PASS; //pass 2 error 1
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
@@ -29345,27 +28331,27 @@
num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
num_array[5]=num_array[8+(lane_step<<2)+2];//lcdlr_max; //edge lcdlr
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[8+(lane_step<<2)+2]=num_array[8+(lane_step<<2)+0];//
temp_count=8+(lane_step<<2)+2;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(ddr_test_method==DDR_TEST_METHOD_DIVIDER_2)
+ if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1);
else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
test_arg_6_lcdlr_temp_count=((num_array[5])-1);
@@ -29382,7 +28368,7 @@
ddr_test_watchdog_enable(test_watchdog_time_s); //s
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -29393,39 +28379,39 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
- if( num_array[8+(lane_step<<2)+3]>4)
+ if ( num_array[8+(lane_step<<2)+3]>4)
{
ddr_test_watchdog_disable(); //s
run_command("run storeboot",0);
- while(1);
+ while (1) ;
}
else
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_PASS; //pass 2 error 1
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
@@ -29433,50 +28419,50 @@
else if((num_array[8+(lane_step<<2)+3]==3)||(num_array[8+(lane_step<<2)+3]==7)) //test right edge ongoing -loop
{
- if((num_array[8+(lane_step<<2)+2]+1)>=(num_array[6]))
+ if ((num_array[8+(lane_step<<2)+2]+1) >= (num_array[6]))
{
- if(num_array[1]==DDR_TEST_NULL)
+ if (num_array[1] == DDR_TEST_NULL)
{printf("default value not stable ,or recovery sticky?\n");
}
num_array[8+(lane_step<<2)+3]= num_array[8+(lane_step<<2)+3]+1; //update status
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[5]=0; //update edge lcdlr
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[1]==DDR_TEST_FAIL)
+ if (num_array[1] == DDR_TEST_FAIL)
num_array[8+(lane_step<<2)+2]=num_array[6]-1; //update B
- if(num_array[1]==DDR_TEST_PASS)
+ if (num_array[1] == DDR_TEST_PASS)
num_array[8+(lane_step<<2)+2]=num_array[6]; //update B
temp_count=8+(lane_step<<2)+2;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
test_arg_6_lcdlr_temp_count=0; //curren_test +B //(A+B)/2
num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
temp_count=1; //update test error flag
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
- run_command("reset",0);
- while(1);
+ run_command("reset",0);
+ while (1) ;
}
- else
- {
- if(num_array[1]==DDR_TEST_NULL)
+ else
+ {
+ if (num_array[1] == DDR_TEST_NULL)
{printf("default value not stable ,or recovery sticky?\n");
}
else if(num_array[1]==DDR_TEST_FAIL)
@@ -29487,37 +28473,37 @@
{
// num_array[8+(lane_step<<2)+3]=3; //update status
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[5]=num_array[6]; //update edge lcdlr
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(ddr_test_method==DDR_TEST_METHOD_DIVIDER_2)
+ if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1);
else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
test_arg_6_lcdlr_temp_count=((num_array[5])-1);
// test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1); //curren_test +B //(A+B)/2
num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
// num_array[8+(lane_step<<2)+1]=num_array[8+(lane_step<<2)+1]; //update B
// temp_count=8+(lane_step<<2)+1;
- // read_write_window_test_parameter(data_source,
+ // read_write_window_test_parameter(data_source,
// temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
temp_count=1; //update test error flag
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
@@ -29525,7 +28511,7 @@
ddr_test_watchdog_enable(test_watchdog_time_s); //s
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -29536,39 +28522,39 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
- if( num_array[8+(lane_step<<2)+3]>4)
+ if ( num_array[8+(lane_step<<2)+3]>4)
{
ddr_test_watchdog_disable(); //s
run_command("run storeboot",0);
- while(1);
+ while (1) ;
}
else
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_PASS; //pass 2 error 1
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
@@ -29579,31 +28565,31 @@
{
// num_array[8+(lane_step<<2)+3]=3; //update status
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[8+(lane_step<<2)+2]=num_array[6]; //update max value
temp_count=8+(lane_step<<2)+2;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(ddr_test_method==DDR_TEST_METHOD_DIVIDER_2)
+ if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1);
else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
test_arg_6_lcdlr_temp_count=((num_array[5])-1);
// test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1); //curren_test +B //(A+B)/2
num_array[6]=test_arg_6_lcdlr_temp_count; // --update curent
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
temp_count=1; //update test error flag
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
@@ -29611,7 +28597,7 @@
ddr_test_watchdog_enable(test_watchdog_time_s); //s
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -29622,37 +28608,37 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
- if( num_array[8+(lane_step<<2)+3]>4)
+ if ( num_array[8+(lane_step<<2)+3]>4)
{
ddr_test_watchdog_disable(); //s
run_command("run storeboot",0);
- while(1);
+ while (1) ;
}
else
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_PASS; //pass 2 error 1
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
@@ -29664,7 +28650,7 @@
}
}
}
- if(lane_step>=10) //finish
+ if (lane_step >= 10) //finish
{
ddr_test_watchdog_disable(); //s
printf("close watchdog\n");
@@ -29761,35 +28747,35 @@
}
- if(test_arg_2_step==DDR_TEST_STATUS_UBOOT_FINISH)//||(test_arg_2_step==DDR_TEST_STATUS_KERNEL_FINISH)
+ if (test_arg_2_step == DDR_TEST_STATUS_UBOOT_FINISH)// || (test_arg_2_step == DDR_TEST_STATUS_KERNEL_FINISH)
{
test_arg_2_step=DDR_TEST_STATUS_KERNEL_ONGING;
num_array[2]=test_arg_2_step;
temp_count=2;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
- while(1);
+ while (1) ;
}
- if(test_arg_2_step==DDR_TEST_STATUS_KERNEL_ONGING)//||(test_arg_2_step==DDR_TEST_STATUS_KERNEL_FINISH)
+ if (test_arg_2_step == DDR_TEST_STATUS_KERNEL_ONGING)// || (test_arg_2_step == DDR_TEST_STATUS_KERNEL_FINISH)
{
test_arg_2_step=DDR_TEST_STATUS_KERNEL_FINISH;
num_array[2]=test_arg_2_step;
temp_count=2;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_STEP_FLAG_ADD_ORG_STICKY_OFFSET ,test_arg_2_step,DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_NULL;
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
{
ddr_test_watchdog_disable(); //s
run_command("run storeboot",0);
- while(1);
+ while (1) ;
}
}
@@ -29808,7 +28794,7 @@
int do_ddr_uboot_kernel_window_use_source_quick_methods(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- //setenv storeboot "ddr_test_cmd 0x34 2 6 20 0 0x100000 0x4000000"
+ //env_set storeboot "ddr_test_cmd 0x34 2 6 20 0 0x100000 0x4000000"
printf("\nsetenv bootcmd ddr_test_cmd 0x34 2 6 20 0 0x100000 0x4000000 \n");
printf("\nEnter do_ddr_uboot_window_use_source function\n");
printf("\n--- watchdog should >15s\n");
@@ -29883,7 +28869,7 @@
lane_disable= 0;
}
}
- printf("lane_disable==0x%08x\n",lane_disable);
+ printf("lane_disable==0x%08x\n",lane_disable);
if (argc >5) {
ddr_data_test_size = simple_strtoull_ddr(argv[5], &endp, 0);
@@ -29938,11 +28924,11 @@
memset(num_array, 0, sizeof(num_array));
char str[1024]="";
- if(data_source==DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
+ if (data_source == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY)
ddr_test_data_array_max=64;
- for (temp_count= 0;temp_count < ddr_test_data_array_max; temp_count++)
+ for (temp_count= 0;temp_count < ddr_test_data_array_max; temp_count++)
{
- num_array[temp_count]= read_write_window_test_parameter(data_source,
+ num_array[temp_count]= read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_READ );
printf("read numarry[%d]==%d\n",temp_count,num_array[temp_count]);
}
@@ -29978,7 +28964,7 @@
- if((test_arg_7_magic_number==DMC_STICKY_MAGIC_1)) //for check magic number make sume enter test command
+ if ((test_arg_7_magic_number == DMC_STICKY_MAGIC_1)) //for check magic number make sume enter test command
{
}
else
@@ -30000,26 +28986,26 @@
num_array[6] = test_arg_6_lcdlr_temp_count ;
num_array[7] = test_arg_7_magic_number ;
- for (temp_count= 0;temp_count < 8; temp_count++)
+ for (temp_count= 0;temp_count < 8; temp_count++)
{
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
- if(test_arg_2_step)
+ if (test_arg_2_step)
{
- if(test_arg_3_freq!=global_ddr_clk) //
+ if (test_arg_3_freq != global_ddr_clk) //
{
printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n",global_ddr_clk,test_arg_3_freq);
sprintf(str,"d2pll %d",test_arg_3_freq);
printf("\nstr=%s\n",str);
run_command(str,0);
- while(1);
+ while (1) ;
}
}
- if(test_arg_2_step==0)
+ if (test_arg_2_step == 0)
{
{
@@ -30043,13 +29029,13 @@
num_array[7] = test_arg_7_magic_number ;
- for (temp_count= 0;temp_count < 8; temp_count++)
+ for (temp_count= 0;temp_count < 8; temp_count++)
{
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
- // read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ // read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
// DDR_TEST_STATUS_STEP_FLAG_ADD_ORG_STICKY_OFFSET ,test_arg_2_step,DDR_PARAMETER_WRITE);
//for (temp_count = 8; temp_count< 48;temp_count++) {
// num_array[temp_count]=0;
@@ -30059,9 +29045,9 @@
{
//printf("1temp_count=%d\n",temp_count);
- if((temp_count%4)==0) //org
+ if ((temp_count%4) == 0) //org
{
- if(((temp_count-8)/4)<8)
+ if (((temp_count-8)/4)<8)
{
lcdlr_min=0;
lcdlr_max=(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
@@ -30069,12 +29055,12 @@
//if(lane_step==9)
//lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
}
- else if(((temp_count-8)/4)<10)
+ else if(((temp_count-8)/4)<10)
{
lcdlr_min=0;
lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
//lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
- if(((temp_count-8)/4)==9)
+ if (((temp_count-8)/4) == 9)
lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
}
//printf("2temp_count=%d\n",temp_count);
@@ -30093,9 +29079,9 @@
for (temp_count = 32+8; temp_count < (32+8+8); temp_count++) //add
{
- if((temp_count%4)==0) //org
- {
- if(((temp_count-8)/4)<8)
+ if ((temp_count%4) == 0) //org
+ {
+ if (((temp_count-8)/4)<8)
{
lcdlr_min=0;
lcdlr_max=(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
@@ -30103,12 +29089,12 @@
//if(lane_step==9)
//lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
}
- else if(((temp_count-8)/4)<10)
+ else if(((temp_count-8)/4)<10)
{
lcdlr_min=0;
lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
//lcdlr_max=4*(do_ddr_read_acmdlr());//(num_array[(lane_step<<2)+2+8]);////3*(do_ddr_read_acmdlr());
- if(((temp_count-8)/4)==9)
+ if (((temp_count-8)/4) == 9)
lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
}
//num_array[temp_count]=0;
@@ -30130,38 +29116,38 @@
printf("DDR0_PUB_DX1GCR0==%x\n",(readl(DDR0_PUB_DX1GCR0)));
printf("DDR0_PUB_DX2GCR0==%x\n",(readl(DDR0_PUB_DX2GCR0)));
printf("DDR0_PUB_DX3GCR0==%x\n",(readl(DDR0_PUB_DX3GCR0)));
- if(((readl(DDR0_PUB_DX0GCR0))&1)==0)
- lane_disable= lane_disable|1;
- if(((readl(DDR0_PUB_DX1GCR0))&1)==0)
- lane_disable= lane_disable|(1<<1);
- if(((readl(DDR0_PUB_DX2GCR0))&1)==0)
- lane_disable= lane_disable|(1<<2);
- if(((readl(DDR0_PUB_DX3GCR0))&1)==0)
- lane_disable= lane_disable|(1<<3);
+ if (((readl(DDR0_PUB_DX0GCR0))&1) == 0)
+ lane_disable= lane_disable|1;
+ if (((readl(DDR0_PUB_DX1GCR0))&1) == 0)
+ lane_disable= lane_disable|(1<<1);
+ if (((readl(DDR0_PUB_DX2GCR0))&1) == 0)
+ lane_disable= lane_disable|(1<<2);
+ if (((readl(DDR0_PUB_DX3GCR0))&1) == 0)
+ lane_disable= lane_disable|(1<<3);
#endif
- if(lane_disable)
+ if (lane_disable)
{if(lane_disable&0x1){
num_array[8+3]=0xffff;
num_array[8+4+3]=0xffff;
}
- if(lane_disable&0x2){
+ if (lane_disable&0x2) {
num_array[8+3+8]=0xffff;
num_array[8+4+3+8]=0xffff;
}
- if(lane_disable&0x4){
+ if (lane_disable&0x4) {
num_array[8+3+8+8]=0xffff;
num_array[8+4+3+8+8]=0xffff;
}
- if(lane_disable&0x8){
+ if (lane_disable&0x8) {
num_array[8+3+8+8+8]=0xffff;
num_array[8+4+3+8+8+8]=0xffff;
}
printf("lane_disable==%x\n",lane_disable);
- if(lane_disable&0x10){
+ if (lane_disable&0x10) {
num_array[8+3+8+8+8+8]=0xffff;
}
- if(lane_disable&0x20){
+ if (lane_disable&0x20) {
num_array[8+4+3+8+8+8+8]=0xffff;
}
@@ -30174,21 +29160,21 @@
for (temp_count= 0; temp_count< 48;temp_count++) {
- num_array[temp_count]= read_write_window_test_parameter(data_source,
+ num_array[temp_count]= read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
}
//test_arg_2_step++;
num_array[2]=test_arg_2_step;
- for (temp_count = 1; temp_count < 48; temp_count++)
+ for (temp_count = 1; temp_count < 48; temp_count++)
{
printf("%d %d\n", temp_count,num_array[temp_count]);
}
temp_count=2;
- num_array[temp_count]= read_write_window_test_parameter(data_source,
+ num_array[temp_count]= read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- // read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ // read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
// DDR_TEST_STATUS_STEP_FLAG_ADD_ORG_STICKY_OFFSET ,test_arg_2_step,DDR_PARAMETER_WRITE);
//for (i = 0; i < 48; i++) {
@@ -30209,21 +29195,21 @@
for ((lane_step=0);(lane_step<10);(lane_step++)) //find need test data step
{
- if(ddr_enable_kernel_window_test_flag==0)
+ if (ddr_enable_kernel_window_test_flag == 0)
{
- if((num_array[(lane_step<<2)+3+8]<(0x4)))
+ if ((num_array[(lane_step<<2)+3+8]<(0x4)))
{break;
}
}
else if(test_arg_2_step<DDR_TEST_STATUS_KERNEL_ONGING)
{
- if((num_array[(lane_step<<2)+3+8]<(0x4)))
+ if ((num_array[(lane_step<<2)+3+8]<(0x4)))
{break;
}
}
}
- if(test_arg_2_step==DDR_TEST_STATUS_UBOOT_ONGOING)
+ if (test_arg_2_step == DDR_TEST_STATUS_UBOOT_ONGOING)
{if(lane_step>9)
{
test_arg_2_step=DDR_TEST_STATUS_UBOOT_FINISH;
@@ -30232,15 +29218,15 @@
}
- if(ddr_enable_kernel_window_test_flag)
+ if (ddr_enable_kernel_window_test_flag)
{
- if(test_arg_2_step>DDR_TEST_STATUS_UBOOT_FINISH)
+ if (test_arg_2_step>DDR_TEST_STATUS_UBOOT_FINISH)
{
for ((lane_step=0);(lane_step<10);(lane_step++)) //find need test data step
{
{
- if((num_array[(lane_step<<2)+3+8]<(0x4+4)))
+ if ((num_array[(lane_step<<2)+3+8]<(0x4+4)))
{break;
}
}
@@ -30248,16 +29234,16 @@
}
}
- if(test_arg_2_step==DDR_TEST_STATUS_UBOOT_FINISH)//||(test_arg_2_step==DDR_TEST_STATUS_KERNEL_FINISH)
+ if (test_arg_2_step == DDR_TEST_STATUS_UBOOT_FINISH)// || (test_arg_2_step == DDR_TEST_STATUS_KERNEL_FINISH)
{
//test_arg_2_step=DDR_TEST_STATUS_KERNEL_ONGING;
}
else
{
printf("\nstart test lane_step =%d\n",lane_step);
- if(lane_step<10)
+ if (lane_step<10)
{
- if(lane_step<8)
+ if (lane_step<8)
{
test_watchdog_time_s=watchdog_time_s;
ddr_test_size=ddr_data_test_size;
@@ -30277,15 +29263,15 @@
//lcdlr_max=0x3f;////3*(do_ddr_read_acmdlr());
}
- if(num_array[8+(lane_step<<2)+3]>4) //from kernel
+ if (num_array[8+(lane_step<<2)+3]>4) //from kernel
{
- num_array[1]= read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ num_array[1]= read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_READ);
- // read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ // read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
// DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
- if(((num_array[8+(lane_step<<2)+3]==0))||((num_array[8+(lane_step<<2)+3]==4))) //test left edge begin
+ if (((num_array[8+(lane_step<<2)+3] == 0)) || ((num_array[8+(lane_step<<2)+3] == 4))) //test left edge begin
{
/*
num_array[1] = test_arg_1_test_error_flag ;//1 pass 2 error
@@ -30299,45 +29285,45 @@
// test_arg_0_orgt_store_lcdlr_value=(num_array[8+(lane_step<<2)+0]);
// num_array[0]=test_arg_0_orgt_store_lcdlr_value;
// temp_count=0;
- // read_write_window_test_parameter(data_source,
+ // read_write_window_test_parameter(data_source,
// temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
+ if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
{
test_arg_0_orgt_store_lcdlr_value=(num_array[8+(lane_step<<2)+1]);
num_array[0]=test_arg_0_orgt_store_lcdlr_value;
temp_count=0;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
- read_write_window_test_flag(data_source,
+ read_write_window_test_flag(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[5]=(num_array[8+(lane_step<<2)+1]); //edge lcdlr
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- (num_array[8+(lane_step<<2)+1])=(num_array[8+(lane_step<<2)+0]);
+ (num_array[8+(lane_step<<2)+1])=(num_array[8+(lane_step<<2)+0]);
temp_count=8+(lane_step<<2)+1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(ddr_test_method==DDR_TEST_METHOD_DIVIDER_2)
+ if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+0])>>1);
else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
test_arg_6_lcdlr_temp_count=((num_array[5])+1);
@@ -30361,32 +29347,32 @@
ddr_test_watchdog_clear();
}
- if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
+ if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
{
ddr_lcdlr_test_offset=test_arg_6_lcdlr_temp_count-num_array[0];//test_arg_0_orgt_store_lcdlr_value;//num_array[8+(lane_step<<2)+1];
do_ddr_read_write_ddr_data_window_lcdlr( rank_index,0,
(num_array[0]+ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
- for ((lane_step_count=1);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=1);(lane_step_count<8);(lane_step_count++))
{
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
(num_array[8+(lane_step_count<<2)+1]+ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
}
- for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
+ for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
{
ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+1]+ddr_lcdlr_test_offset);
- if(lane_step_count==9)
+ if (lane_step_count == 9)
{if (ddr_lcdlr_test_temp_value>0x3f)
ddr_lcdlr_test_temp_value=0x3f;
}
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
}
}
else
{
- if(lane_step<8)
+ if (lane_step<8)
{
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
}
@@ -30407,38 +29393,38 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
- if( num_array[8+(lane_step<<2)+3]>4)
+ if ( num_array[8+(lane_step<<2)+3]>4)
{
ddr_test_watchdog_disable(); //s
run_command("run storeboot",0);
- while(1);
+ while (1) ;
}
else
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
+ if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
{
ddr_lcdlr_test_offset=0;//test_arg_6_lcdlr_temp_count-num_array[8+(lane_step<<2)+1];
- for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
{
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
(num_array[8+(lane_step_count<<2)+0]+ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
}
- for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
+ for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
{
ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+0]+ddr_lcdlr_test_offset);
- if(lane_step_count==9)
+ if (lane_step_count == 9)
{if (ddr_lcdlr_test_temp_value>0x3f)
ddr_lcdlr_test_temp_value=0x3f;
}
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
}
@@ -30446,7 +29432,7 @@
else
{
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
@@ -30454,40 +29440,40 @@
num_array[1]=DDR_TEST_PASS; //pass 2 error 1
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
}
else if((num_array[8+(lane_step<<2)+3]==1)||((num_array[8+(lane_step<<2)+3]==5))) //test left edge begin) //test left edge ongoing -loop
{
- if((num_array[6]+1)>=(num_array[8+(lane_step<<2)+1]))
+ if ((num_array[6]+1) >= (num_array[8+(lane_step<<2)+1]))
{
- if(num_array[1]==DDR_TEST_NULL)
+ if (num_array[1] == DDR_TEST_NULL)
{printf("default value not stable ,or recovery sticky?\n");
}
- if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
+ if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
{
//ddr_lcdlr_test_offset=0;//test_arg_6_lcdlr_temp_count-num_array[8+(lane_step<<2)+1];
- for ((lane_step_count=0);(lane_step_count<10);(lane_step_count++))
+ for ((lane_step_count=0);(lane_step_count<10);(lane_step_count++))
{
num_array[8+(lane_step_count<<2)+3]= num_array[8+(lane_step_count<<2)+3]+1; //update status
lane_step_count=8+(lane_step_count<<2)+3;
- if(num_array[8+(lane_step_count<<2)+3]<9)
- read_write_window_test_parameter(data_source,
+ if (num_array[8+(lane_step_count<<2)+3]<9)
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
@@ -30497,13 +29483,13 @@
{
num_array[8+(lane_step<<2)+3]= num_array[8+(lane_step<<2)+3]+1; //update status
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
num_array[5]=0; //update edge lcdlr
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
// if(num_array[1]==DDR_TEST_FAIL)
@@ -30513,77 +29499,77 @@
// temp_count=8+(lane_step<<2)+1;
- if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
+ if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
{
test_arg_0_orgt_store_lcdlr_value= num_array[0];
- if(num_array[1]==DDR_TEST_FAIL)
+ if (num_array[1] == DDR_TEST_FAIL)
{
ddr_lcdlr_test_offset=num_array[8+(lane_step<<2)+1]+1-test_arg_0_orgt_store_lcdlr_value;
}
- if(num_array[1]==DDR_TEST_PASS)
+ if (num_array[1] == DDR_TEST_PASS)
{
ddr_lcdlr_test_offset=num_array[8+(lane_step<<2)+1]+0-test_arg_0_orgt_store_lcdlr_value;
}
temp_count=8+(lane_step<<2)+2;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- for ((lane_step_count=1);(lane_step_count<10);(lane_step_count++))
+ for ((lane_step_count=1);(lane_step_count<10);(lane_step_count++))
{
ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+2]+ddr_lcdlr_test_offset);
- if(lane_step_count==9)
+ if (lane_step_count == 9)
{
- if((num_array[8+(lane_step_count<<2)+2]+ddr_lcdlr_test_offset)>0x3f)
+ if ((num_array[8+(lane_step_count<<2)+2]+ddr_lcdlr_test_offset)>0x3f)
ddr_lcdlr_test_temp_value=0x3f;
}
- if(num_array[8+(lane_step_count<<2)+3]<9)
- read_write_window_test_parameter(data_source,
+ if (num_array[8+(lane_step_count<<2)+3]<9)
+ read_write_window_test_parameter(data_source,
(8+(lane_step_count<<2)+2) ,ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
}
}
- else
+ else
{
- if(num_array[1]==DDR_TEST_FAIL)
+ if (num_array[1] == DDR_TEST_FAIL)
num_array[8+(lane_step<<2)+1]=num_array[6]+1; //update B
- if(num_array[1]==DDR_TEST_PASS)
+ if (num_array[1] == DDR_TEST_PASS)
num_array[8+(lane_step<<2)+1]=num_array[6]; //update B
temp_count=8+(lane_step<<2)+1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
test_arg_6_lcdlr_temp_count=0; //curren_test +B //(A+B)/2
num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
temp_count=1; //update test error flag
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- // num_array[1]= read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ // num_array[1]= read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
// DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_READ);
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
// test_arg_0_orgt_store_lcdlr_value=0;//(num_array[8+(lane_step<<2)+0]);
// num_array[0]=test_arg_0_orgt_store_lcdlr_value;
// temp_count=0;
- // read_write_window_test_parameter(data_source,
+ // read_write_window_test_parameter(data_source,
// temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- run_command("reset",0);
- while(1);
+ run_command("reset",0);
+ while (1) ;
}
- else
- {
- if(num_array[1]==DDR_TEST_NULL)
+ else
+ {
+ if (num_array[1] == DDR_TEST_NULL)
{printf("default value not stable ,or recovery sticky?\n");
}
else if(num_array[1]==DDR_TEST_FAIL)
@@ -30594,16 +29580,16 @@
{
// num_array[8+(lane_step<<2)+3]=1; //update status
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[5]=num_array[6]; //update edge lcdlr
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(ddr_test_method==DDR_TEST_METHOD_DIVIDER_2)
+ if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1);
else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
test_arg_6_lcdlr_temp_count=((num_array[5])+1);
@@ -30612,21 +29598,21 @@
// test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1); //curren_test +B //(A+B)/2
num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
// num_array[8+(lane_step<<2)+1]=num_array[8+(lane_step<<2)+1]; //update B
// temp_count=8+(lane_step<<2)+1;
- // read_write_window_test_parameter(data_source,
+ // read_write_window_test_parameter(data_source,
// temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
temp_count=1; //update test error flag
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
@@ -30635,26 +29621,26 @@
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
+ if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
{
ddr_lcdlr_test_offset=test_arg_6_lcdlr_temp_count-num_array[0];//tnum_array[8+(lane_step<<2)+1];
do_ddr_read_write_ddr_data_window_lcdlr( rank_index,0,
(num_array[0]+ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
- for ((lane_step_count=1);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=1);(lane_step_count<8);(lane_step_count++))
{
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
(num_array[8+(lane_step_count<<2)+1]+ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
}
- for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
+ for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
{
ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+1]+ddr_lcdlr_test_offset);
- if(lane_step_count==9)
+ if (lane_step_count == 9)
{if (ddr_lcdlr_test_temp_value>0x3f)
ddr_lcdlr_test_temp_value=0x3f;
}
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
}
@@ -30662,7 +29648,7 @@
else
{
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -30674,15 +29660,15 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
- if( num_array[8+(lane_step<<2)+3]>4)
+ if ( num_array[8+(lane_step<<2)+3]>4)
{
ddr_test_watchdog_disable(); //s
run_command("run storeboot",0);
- while(1);
+ while (1) ;
}
else
{
@@ -30690,30 +29676,30 @@
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
+ if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
{
ddr_lcdlr_test_offset=0;//test_arg_6_lcdlr_temp_count-num_array[8+(lane_step<<2)+1];
- for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
{
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
(num_array[8+(lane_step_count<<2)+0]+ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
}
- for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
+ for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
{
ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+0]+ddr_lcdlr_test_offset);
- if(lane_step_count==9)
+ if (lane_step_count == 9)
{if (ddr_lcdlr_test_temp_value>0x3f)
ddr_lcdlr_test_temp_value=0x3f;
}
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
}
}
else
{
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
@@ -30721,18 +29707,18 @@
num_array[1]=DDR_TEST_PASS; //pass 2 error 1
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
@@ -30743,15 +29729,15 @@
{
// num_array[8+(lane_step<<2)+3]=1; //update status
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[8+(lane_step<<2)+1]=num_array[6]; //update min value
temp_count=8+(lane_step<<2)+1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(ddr_test_method==DDR_TEST_METHOD_DIVIDER_2)
+ if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1);
else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
test_arg_6_lcdlr_temp_count=((num_array[5])+1);
@@ -30760,17 +29746,17 @@
// test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+1])>>1); //curren_test +B //(A+B)/2
num_array[6]=test_arg_6_lcdlr_temp_count; // --update curent
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
temp_count=1; //update test error flag
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
@@ -30779,32 +29765,32 @@
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
+ if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
{
ddr_lcdlr_test_offset=test_arg_6_lcdlr_temp_count-num_array[0];//tnum_array[8+(lane_step<<2)+1];
do_ddr_read_write_ddr_data_window_lcdlr( rank_index,0,
(num_array[0]+ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
- for ((lane_step_count=1);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=1);(lane_step_count<8);(lane_step_count++))
{
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
(num_array[8+(lane_step_count<<2)+1]+ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
}
- for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
+ for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
{
ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+1]+ddr_lcdlr_test_offset);
- if(lane_step_count==9)
+ if (lane_step_count == 9)
{if (ddr_lcdlr_test_temp_value>0x3f)
ddr_lcdlr_test_temp_value=0x3f;
}
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
}
}
else
{
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -30815,44 +29801,44 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
- if( num_array[8+(lane_step<<2)+3]>4)
+ if ( num_array[8+(lane_step<<2)+3]>4)
{
ddr_test_watchdog_disable(); //s
run_command("run storeboot",0);
- while(1);
+ while (1) ;
}
else
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
+ if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
{
ddr_lcdlr_test_offset=0;//test_arg_6_lcdlr_temp_count-num_array[8+(lane_step<<2)+1];
- for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
{
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
(num_array[8+(lane_step_count<<2)+0]+ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
}
- for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
+ for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
{
ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+0]+ddr_lcdlr_test_offset);
- if(lane_step_count==9)
+ if (lane_step_count == 9)
{if (ddr_lcdlr_test_temp_value>0x3f)
ddr_lcdlr_test_temp_value=0x3f;
}
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
}
}
else
{
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
@@ -30860,17 +29846,17 @@
num_array[1]=DDR_TEST_PASS; //pass 2 error 1
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
@@ -30892,38 +29878,38 @@
num_array[7] = test_arg_7_magic_number ;
*/
- if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
+ if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
{
test_arg_0_orgt_store_lcdlr_value=(num_array[8+(lane_step<<2)+2]);
num_array[0]=test_arg_0_orgt_store_lcdlr_value;
temp_count=0;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
num_array[5]=num_array[8+(lane_step<<2)+2];//lcdlr_max; //edge lcdlr
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[8+(lane_step<<2)+2]=num_array[8+(lane_step<<2)+0];//
temp_count=8+(lane_step<<2)+2;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(ddr_test_method==DDR_TEST_METHOD_DIVIDER_2)
+ if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1);
else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
test_arg_6_lcdlr_temp_count=((num_array[5])-1);
@@ -30943,32 +29929,32 @@
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
+ if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
{
ddr_lcdlr_test_offset=num_array[0]-test_arg_6_lcdlr_temp_count;
do_ddr_read_write_ddr_data_window_lcdlr( rank_index,0,
(num_array[0]-ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
- for ((lane_step_count=1);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=1);(lane_step_count<8);(lane_step_count++))
{
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
(num_array[8+(lane_step_count<<2)+2]-ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
}
- for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
+ for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
{
ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+2]-ddr_lcdlr_test_offset);
//if(lane_step_count==9)
{if ((num_array[8+(lane_step_count<<2)+2])<(ddr_lcdlr_test_offset))
ddr_lcdlr_test_temp_value=0;
}
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
}
}
else
{
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -30979,62 +29965,62 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
- if( num_array[8+(lane_step<<2)+3]>4)
+ if ( num_array[8+(lane_step<<2)+3]>4)
{
ddr_test_watchdog_disable(); //s
run_command("run storeboot",0);
- while(1);
+ while (1) ;
}
else
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
+ if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
{
ddr_lcdlr_test_offset=0;//num_array[8+(lane_step<<2)+2]-test_arg_6_lcdlr_temp_count;
- for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
{
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
(num_array[8+(lane_step_count<<2)+0]-ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
}
- for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
+ for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
{
ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+0]-ddr_lcdlr_test_offset);
//if(lane_step_count==9)
// {if ((num_array[8+(lane_step_count<<2)+2]<ddr_lcdlr_test_offset)
// ddr_lcdlr_test_temp_value=0;
// }
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
}
}
else
{
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
}
num_array[1]=DDR_TEST_PASS; //pass 2 error 1
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
@@ -31042,23 +30028,23 @@
else if((num_array[8+(lane_step<<2)+3]==3)||(num_array[8+(lane_step<<2)+3]==7)) //test right edge ongoing -loop
{
- if((num_array[8+(lane_step<<2)+2]+1)>=(num_array[6]))
+ if ((num_array[8+(lane_step<<2)+2]+1) >= (num_array[6]))
{
- if(num_array[1]==DDR_TEST_NULL)
+ if (num_array[1] == DDR_TEST_NULL)
{printf("default value not stable ,or recovery sticky?\n");
}
- if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
+ if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
{
//ddr_lcdlr_test_offset=0;//test_arg_6_lcdlr_temp_count-num_array[8+(lane_step<<2)+1];
- for ((lane_step_count=0);(lane_step_count<10);(lane_step_count++))
+ for ((lane_step_count=0);(lane_step_count<10);(lane_step_count++))
{
num_array[8+(lane_step_count<<2)+3]= num_array[8+(lane_step_count<<2)+3]+1; //update status
lane_step_count=8+(lane_step_count<<2)+3;
- if(num_array[8+(lane_step_count<<2)+3]<9)
- read_write_window_test_parameter(data_source,
+ if (num_array[8+(lane_step_count<<2)+3]<9)
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
@@ -31068,13 +30054,13 @@
{
num_array[8+(lane_step<<2)+3]= num_array[8+(lane_step<<2)+3]+1; //update status
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
num_array[5]=0; //update edge lcdlr
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
// if(num_array[1]==DDR_TEST_FAIL)
@@ -31082,45 +30068,45 @@
// if(num_array[1]==DDR_TEST_PASS)
// num_array[8+(lane_step<<2)+2]=num_array[6]; //update B
// temp_count=8+(lane_step<<2)+2;
- // read_write_window_test_parameter(data_source,
+ // read_write_window_test_parameter(data_source,
// temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
+ if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
{
test_arg_0_orgt_store_lcdlr_value= num_array[0];
- if(num_array[1]==DDR_TEST_FAIL)
+ if (num_array[1] == DDR_TEST_FAIL)
{
ddr_lcdlr_test_offset=test_arg_0_orgt_store_lcdlr_value-num_array[8+(lane_step<<2)+2]+1;
}
- if(num_array[1]==DDR_TEST_PASS)
+ if (num_array[1] == DDR_TEST_PASS)
{
ddr_lcdlr_test_offset=test_arg_0_orgt_store_lcdlr_value-num_array[8+(lane_step<<2)+2]+0;
}
temp_count=8+(lane_step<<2)+2;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- for ((lane_step_count=1);(lane_step_count<10);(lane_step_count++))
+ for ((lane_step_count=1);(lane_step_count<10);(lane_step_count++))
{
ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+2]-ddr_lcdlr_test_offset);
- if(num_array[8+(lane_step_count<<2)+2]<ddr_lcdlr_test_offset)
+ if (num_array[8+(lane_step_count<<2)+2]<ddr_lcdlr_test_offset)
ddr_lcdlr_test_temp_value=0;
- if(num_array[8+(lane_step_count<<2)+3]<9)
- read_write_window_test_parameter(data_source,
+ if (num_array[8+(lane_step_count<<2)+3]<9)
+ read_write_window_test_parameter(data_source,
(8+(lane_step_count<<2)+2) ,ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
}
}
- else
+ else
{
- if(num_array[1]==DDR_TEST_FAIL)
+ if (num_array[1] == DDR_TEST_FAIL)
num_array[8+(lane_step<<2)+2]=num_array[6]-1; //update B
- if(num_array[1]==DDR_TEST_PASS)
+ if (num_array[1] == DDR_TEST_PASS)
num_array[8+(lane_step<<2)+2]=num_array[6]; //update B
temp_count=8+(lane_step<<2)+2;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
@@ -31128,25 +30114,25 @@
test_arg_6_lcdlr_temp_count=0; //curren_test +B //(A+B)/2
num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_NULL; //1 //pass 2 error
temp_count=1; //update test error flag
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
- run_command("reset",0);
- while(1);
+ run_command("reset",0);
+ while (1) ;
}
- else
- {
- if(num_array[1]==DDR_TEST_NULL)
+ else
+ {
+ if (num_array[1] == DDR_TEST_NULL)
{printf("default value not stable ,or recovery sticky?\n");
}
else if(num_array[1]==DDR_TEST_FAIL)
@@ -31157,16 +30143,16 @@
{
// num_array[8+(lane_step<<2)+3]=3; //update status
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[5]=num_array[6]; //update edge lcdlr
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(ddr_test_method==DDR_TEST_METHOD_DIVIDER_2)
+ if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1);
else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
test_arg_6_lcdlr_temp_count=((num_array[5])-1);
@@ -31175,21 +30161,21 @@
// test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1); //curren_test +B //(A+B)/2
num_array[6]=test_arg_6_lcdlr_temp_count; //--update curent
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
// num_array[8+(lane_step<<2)+1]=num_array[8+(lane_step<<2)+1]; //update B
// temp_count=8+(lane_step<<2)+1;
- // read_write_window_test_parameter(data_source,
+ // read_write_window_test_parameter(data_source,
// temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
temp_count=1; //update test error flag
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
@@ -31198,32 +30184,32 @@
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
+ if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
{
ddr_lcdlr_test_offset=num_array[0]-test_arg_6_lcdlr_temp_count;
do_ddr_read_write_ddr_data_window_lcdlr( rank_index,0,
(num_array[0]-ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
- for ((lane_step_count=1);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=1);(lane_step_count<8);(lane_step_count++))
{
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
(num_array[8+(lane_step_count<<2)+2]-ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
}
- for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
+ for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
{
ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+2]-ddr_lcdlr_test_offset);
//if(lane_step_count==9)
{if ((num_array[8+(lane_step_count<<2)+2])<(ddr_lcdlr_test_offset))
ddr_lcdlr_test_temp_value=0;
}
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
}
}
else
{
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -31234,62 +30220,62 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
- if( num_array[8+(lane_step<<2)+3]>4)
+ if ( num_array[8+(lane_step<<2)+3]>4)
{
ddr_test_watchdog_disable(); //s
run_command("run storeboot",0);
- while(1);
+ while (1) ;
}
else
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
+ if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
{
ddr_lcdlr_test_offset=0;//num_array[8+(lane_step<<2)+2]-test_arg_6_lcdlr_temp_count;
- for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
{
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
(num_array[8+(lane_step_count<<2)+0]-ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
}
- for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
+ for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
{
ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+0]-ddr_lcdlr_test_offset);
//if(lane_step_count==9)
// {if ((num_array[8+(lane_step_count<<2)+0]<ddr_lcdlr_test_offset)
// ddr_lcdlr_test_temp_value=0;
// }
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
}
}
else
{
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
}
num_array[1]=DDR_TEST_PASS; //pass 2 error 1
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
@@ -31300,15 +30286,15 @@
{
// num_array[8+(lane_step<<2)+3]=3; //update status
temp_count=8+(lane_step<<2)+3;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[8+(lane_step<<2)+2]=num_array[6]; //update max value
temp_count=8+(lane_step<<2)+2;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(ddr_test_method==DDR_TEST_METHOD_DIVIDER_2)
+ if (ddr_test_method == DDR_TEST_METHOD_DIVIDER_2)
test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1);
else if(ddr_test_method==DDR_TEST_METHOD_DECREASE)
test_arg_6_lcdlr_temp_count=((num_array[5])-1);
@@ -31317,16 +30303,16 @@
// test_arg_6_lcdlr_temp_count=((num_array[5]+num_array[8+(lane_step<<2)+2])>>1); //curren_test +B //(A+B)/2
num_array[6]=test_arg_6_lcdlr_temp_count; // --update curent
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_FAIL; //1 //pass 2 error
temp_count=1; //update test error flag
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
@@ -31334,32 +30320,32 @@
ddr_test_watchdog_enable(test_watchdog_time_s); //s
printf("\nenable %ds watchdog \n",test_watchdog_time_s);
ddr_test_watchdog_clear();
- if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
+ if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
{
ddr_lcdlr_test_offset=num_array[0]-test_arg_6_lcdlr_temp_count;
do_ddr_read_write_ddr_data_window_lcdlr( rank_index,0,
(num_array[0]-ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
- for ((lane_step_count=1);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=1);(lane_step_count<8);(lane_step_count++))
{
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
(num_array[8+(lane_step_count<<2)+2]-ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
}
- for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
+ for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
{
ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+2]-ddr_lcdlr_test_offset);
//if(lane_step_count==9)
{if ((num_array[8+(lane_step_count<<2)+2])<(ddr_lcdlr_test_offset))
ddr_lcdlr_test_temp_value=0;
}
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
}
}
else
{
- if(lane_step<8)
+ if (lane_step<8)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
else if(lane_step<10)
test_arg_6_lcdlr_temp_count=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,test_arg_6_lcdlr_temp_count,DDR_PARAMETER_WRITE);
@@ -31370,60 +30356,60 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
- if( num_array[8+(lane_step<<2)+3]>4)
+ if ( num_array[8+(lane_step<<2)+3]>4)
{
ddr_test_watchdog_disable(); //s
run_command("run storeboot",0);
- while(1);
+ while (1) ;
}
else
{
ddr_test_watchdog_clear();
org_lcdlr_value_temp=num_array[8+(lane_step<<2)+0];
- if(ddr_test_method==DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
+ if (ddr_test_method == DDR_TEST_METHOD_DECREASE_ALL_SAMETIME)
{
ddr_lcdlr_test_offset=0;//num_array[8+(lane_step<<2)+2]-test_arg_6_lcdlr_temp_count;
- for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
{
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
(num_array[8+(lane_step_count<<2)+0]-ddr_lcdlr_test_offset),DDR_PARAMETER_WRITE);
}
- for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
+ for ((lane_step_count=8);(lane_step_count<10);(lane_step_count++))
{
ddr_lcdlr_test_temp_value=(num_array[8+(lane_step_count<<2)+0]-ddr_lcdlr_test_offset);
//if(lane_step_count==9)
// {if ((num_array[8+(lane_step_count<<2)+0]<ddr_lcdlr_test_offset)
// ddr_lcdlr_test_temp_value=0;
// }
- if(num_array[8+(lane_step_count<<2)+3]<9)
+ if (num_array[8+(lane_step_count<<2)+3]<9)
do_ddr_read_write_ddr_add_window_lcdlr( rank_index,(lane_step_count-8),
ddr_lcdlr_test_temp_value,DDR_PARAMETER_WRITE);
}
}
else
{
- if(lane_step<8)
+ if (lane_step<8)
org_lcdlr_value_temp=do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
else if(lane_step<10)
org_lcdlr_value_temp=do_ddr_read_write_ddr_add_window_lcdlr( rank_index,lane_step-8,org_lcdlr_value_temp,DDR_PARAMETER_WRITE);
}
num_array[1]=DDR_TEST_PASS; //pass 2 error 1
temp_count=1;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if(num_array[8+(lane_step<<2)+3]>4)
+ if (num_array[8+(lane_step<<2)+3]>4)
{
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
}
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
@@ -31435,7 +30421,7 @@
}
}
}
- if(lane_step>=10) //finish
+ if (lane_step >= 10) //finish
{
ddr_test_watchdog_disable(); //s
printf("close watchdog\n");
@@ -31532,35 +30518,35 @@
}
- if(test_arg_2_step==DDR_TEST_STATUS_UBOOT_FINISH)//||(test_arg_2_step==DDR_TEST_STATUS_KERNEL_FINISH)
+ if (test_arg_2_step == DDR_TEST_STATUS_UBOOT_FINISH)// || (test_arg_2_step == DDR_TEST_STATUS_KERNEL_FINISH)
{
test_arg_2_step=DDR_TEST_STATUS_KERNEL_ONGING;
num_array[2]=test_arg_2_step;
temp_count=2;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
- while(1);
+ while (1) ;
}
- if(test_arg_2_step==DDR_TEST_STATUS_KERNEL_ONGING)//||(test_arg_2_step==DDR_TEST_STATUS_KERNEL_FINISH)
+ if (test_arg_2_step == DDR_TEST_STATUS_KERNEL_ONGING)// || (test_arg_2_step == DDR_TEST_STATUS_KERNEL_FINISH)
{
test_arg_2_step=DDR_TEST_STATUS_KERNEL_FINISH;
num_array[2]=test_arg_2_step;
temp_count=2;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_STEP_FLAG_ADD_ORG_STICKY_OFFSET ,test_arg_2_step,DDR_PARAMETER_WRITE);
num_array[1]=DDR_TEST_NULL;
- read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
+ read_write_window_test_flag(DDR_PARAMETER_SOURCE_FROM_ORG_STICKY,
DDR_TEST_STATUS_PASS_FAIL_ADD_ORG_STICKY_OFFSET ,num_array[1],DDR_PARAMETER_WRITE);
{
ddr_test_watchdog_disable(); //s
run_command("run storeboot",0);
- while(1);
+ while (1) ;
}
}
@@ -31650,7 +30636,7 @@
lane_disable= 0;
}
}
- printf("lane_disable==0x%08x\n",lane_disable);
+ printf("lane_disable==0x%08x\n",lane_disable);
if (argc >5) {
ddr_data_test_size = simple_strtoull_ddr(argv[5], &endp, 0);
@@ -31719,9 +30705,9 @@
ddr_test_data_array_max=10;
- for (temp_count= 0;temp_count < ddr_test_data_array_max; temp_count++)
+ for (temp_count= 0;temp_count < ddr_test_data_array_max; temp_count++)
{
- num_array[temp_count]= read_write_window_test_parameter(data_source,
+ num_array[temp_count]= read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_READ );
printf("read numarry[%d]==%d\n",temp_count,num_array[temp_count]);
}
@@ -31735,7 +30721,7 @@
unsigned int test_arg_5_pass_fail_flag_add_sticky_offset =0; //use for kernel
unsigned int test_arg_6_step_status =0; //uboot test we should read error then done status. 0 no test 1 ongoing 2 this step done fail or pass
- unsigned int test_arg_7_lcdlr_offset =0; //left_lcdlr+right_lcdlr<<16
+ unsigned int test_arg_7_lcdlr_offset =0; //left_lcdlr+right_lcdlr<<16
unsigned int test_arg_7_lcdlr_offset_l =0; //left_lcdlr
unsigned int test_arg_7_lcdlr_offset_r=0; //right_lcdlr
unsigned int delay_step_x100= 0;
@@ -31773,25 +30759,25 @@
- //for (temp_count= 0;temp_count < 8; temp_count++)
+ //for (temp_count= 0;temp_count < 8; temp_count++)
// {
- // read_write_window_test_parameter(data_source,
+ // read_write_window_test_parameter(data_source,
// temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
//}
- if(ddr_test_clear_flag)
+ if (ddr_test_clear_flag)
{ test_arg_6_step_status=0;
num_array[6] = test_arg_6_step_status ;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
printf("\n clear sticky register should reset,then over write ....\n");
run_command("reset",0);
- while(1);
+ while (1) ;
}
- if(test_arg_6_step_status==0)
+ if (test_arg_6_step_status == 0)
{
{
@@ -31812,7 +30798,7 @@
test_arg_5_pass_fail_flag_add_sticky_offset=0;
test_arg_6_step_status=0;
test_arg_7_lcdlr_offset=0;
- if(ddr_test_init_offset)
+ if (ddr_test_init_offset)
{test_arg_7_lcdlr_offset=ddr_test_init_offset;
}
num_array[0] = reg_def_value_data[0] ;
@@ -31826,9 +30812,9 @@
- for (temp_count= 0;temp_count < 8; temp_count++)
+ for (temp_count= 0;temp_count < 8; temp_count++)
{
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
@@ -31847,7 +30833,7 @@
}
}
- if(ddr_test_uboot_kernel_enable_mask&1)
+ if (ddr_test_uboot_kernel_enable_mask&1)
{printf("skip uboot test should init kernel offset value==0x%08x\n",num_array[7]);
}
@@ -31871,7 +30857,7 @@
printf("test_arg_6_step_status=%d\n",num_array[6]);
printf("test_arg_7_lcdlr_offset=%d\n",num_array[7]);
- if(test_arg_6_step_status==4) //uboot finish
+ if (test_arg_6_step_status == 4) //uboot finish
{
ddr_test_watchdog_disable(); //s
printf("close watchdog\n");
@@ -31893,21 +30879,21 @@
}
- if(ddr_test_uboot_kernel_enable_mask&2)
+ if (ddr_test_uboot_kernel_enable_mask&2)
{
- if(ddr_test_uboot_loop)
+ if (ddr_test_uboot_loop)
{
{ test_arg_6_step_status=0;
num_array[6] = test_arg_6_step_status ;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
printf("\n clear sticky register should reset,then over write ....\n");
run_command("reset",0);
- while(1);
+ while (1) ;
}
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
return 1;
@@ -31918,48 +30904,48 @@
//if((test_arg_6_step_status==0)) //0 test left edge begin 1 test left edge ongoing 2//left_finish 3 right edge ongoing 4 right finish //5 kernel left edge ongoing 6 kernel left finish 7 kernel right ongoing
// uboot find from pass to fail offset 0->max
- //kernel find from fail to pass offset from max ->0
- if((test_arg_6_step_status<4)) //// uboot find from pass to fail offset 0->max
+ //kernel find from fail to pass offset from max ->0
+ if ((test_arg_6_step_status<4)) //// uboot find from pass to fail offset 0->max
{
- if((test_arg_6_step_status==0)||(test_arg_6_step_status==2)
+ if ((test_arg_6_step_status == 0) || (test_arg_6_step_status == 2)
||(test_arg_6_step_status==4)||(test_arg_6_step_status==6)
)
{
test_arg_6_step_status=test_arg_6_step_status+1;
num_array[6] = test_arg_6_step_status ;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
- if((test_arg_6_step_status==1)||(test_arg_6_step_status==3)||(test_arg_6_step_status==5)||(test_arg_6_step_status==7))
+ if ((test_arg_6_step_status == 1) || (test_arg_6_step_status == 3) || (test_arg_6_step_status == 5) || (test_arg_6_step_status == 7))
{
- if(test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_PASS) //pass 2 error 1
+ if (test_arg_5_pass_fail_flag_add_sticky_offset == DDR_TEST_PASS) //pass 2 error 1
{
// test_arg_6_step_status=test_arg_6_step_status+1;
test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_NULL;
num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if((test_arg_6_step_status==1)||(test_arg_6_step_status==5))
+ if ((test_arg_6_step_status == 1) || (test_arg_6_step_status == 5))
{
- for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
{
- if((lane_step_count%2)==0)
+ if ((lane_step_count%2) == 0)
{
- if((((num_array[lane_step_count/2])>>0)&0xffff)<=test_arg_7_lcdlr_offset_l)
+ if ((((num_array[lane_step_count/2])>>0)&0xffff) <= test_arg_7_lcdlr_offset_l)
{
test_lcdlr_reach_lcdlr_limited_flag=test_lcdlr_reach_lcdlr_limited_flag+1;
}
}
- if((lane_step_count%2)==1)
+ if ((lane_step_count%2) == 1)
{
- if((((num_array[lane_step_count/2])>>16)&0xffff)<=test_arg_7_lcdlr_offset_l)
+ if ((((num_array[lane_step_count/2])>>16)&0xffff) <= test_arg_7_lcdlr_offset_l)
{
test_lcdlr_reach_lcdlr_limited_flag=test_lcdlr_reach_lcdlr_limited_flag+1;
}
@@ -31971,15 +30957,15 @@
}
- if(test_lcdlr_reach_lcdlr_limited_flag)
+ if (test_lcdlr_reach_lcdlr_limited_flag)
{
- test_arg_6_step_status=test_arg_6_step_status+1;
+ test_arg_6_step_status=test_arg_6_step_status+1;
num_array[6] = test_arg_6_step_status ;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
@@ -31988,18 +30974,18 @@
// test_arg_7_lcdlr_offset_l=(test_arg_7_lcdlr_offset&0xffff);
// test_arg_7_lcdlr_offset_r=((test_arg_7_lcdlr_offset>>16)&0xffff);
- if(((test_arg_6_step_status==1))||(test_arg_6_step_status==5))
+ if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
{
test_arg_7_lcdlr_offset_l=test_arg_7_lcdlr_offset_l-1;
}
else if(((test_arg_6_step_status==3))||(test_arg_6_step_status==7))
{
- test_arg_7_lcdlr_offset_r=test_arg_7_lcdlr_offset_r-1;
+ test_arg_7_lcdlr_offset_r=test_arg_7_lcdlr_offset_r-1;
}
test_arg_7_lcdlr_offset=(test_arg_7_lcdlr_offset_l|(test_arg_7_lcdlr_offset_r<<16));
num_array[7] = test_arg_7_lcdlr_offset ;
temp_count=7;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
@@ -32007,16 +30993,16 @@
test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_NULL;
num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- test_arg_6_step_status=test_arg_6_step_status+1;
+ test_arg_6_step_status=test_arg_6_step_status+1;
num_array[6] = test_arg_6_step_status ;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
@@ -32024,24 +31010,24 @@
// test_arg_7_lcdlr_offset_l=(test_arg_7_lcdlr_offset&0xffff);
// test_arg_7_lcdlr_offset_r=((test_arg_7_lcdlr_offset>>16)&0xffff);
- if(((test_arg_6_step_status==1))||(test_arg_6_step_status==5))
+ if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
{
test_arg_7_lcdlr_offset_l=test_arg_7_lcdlr_offset_l+1;
}
else if(((test_arg_6_step_status==3))||(test_arg_6_step_status==7))
{
- test_arg_7_lcdlr_offset_r=test_arg_7_lcdlr_offset_r+1;
+ test_arg_7_lcdlr_offset_r=test_arg_7_lcdlr_offset_r+1;
}
test_arg_7_lcdlr_offset=(test_arg_7_lcdlr_offset_l|(test_arg_7_lcdlr_offset_r<<16));
num_array[7] = test_arg_7_lcdlr_offset ;
temp_count=7;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL; //pass 2 error 1
num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
ddr_test_watchdog_enable(test_watchdog_time_s); //s
@@ -32051,34 +31037,34 @@
{
- for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
{
printf("\n (num_array[%d]) ==%08x \n",lane_step_count/2,(num_array[lane_step_count/2]));
- if(((test_arg_6_step_status==1))||(test_arg_6_step_status==5))
+ if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
{
- if((lane_step_count%2)==0)
+ if ((lane_step_count%2) == 0)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff)-test_arg_7_lcdlr_offset_l;
- if((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
+ if ((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
{test_lcdlr_temp_value=0;
}
}
- if((lane_step_count%2)==1)
+ if ((lane_step_count%2) == 1)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff)-test_arg_7_lcdlr_offset_l;
- if((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
+ if ((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
{test_lcdlr_temp_value=0;
}
}
}
- if(((test_arg_6_step_status==3))||(test_arg_6_step_status==7))
+ if (((test_arg_6_step_status == 3)) || (test_arg_6_step_status == 7))
{
- if((lane_step_count%2)==0)
+ if ((lane_step_count%2) == 0)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff)+test_arg_7_lcdlr_offset_r;
}
- if((lane_step_count%2)==1)
+ if ((lane_step_count%2) == 1)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff)+test_arg_7_lcdlr_offset_r;
@@ -32097,17 +31083,17 @@
}
//here will dead
- if(test_arg_6_step_status>4)
+ if (test_arg_6_step_status>4)
{
//ddr_test_watchdog_disable(); //s
ddr_test_watchdog_enable(kernel_test_watchdog_time_s); //s
// test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL; //pass 2 error 1
// num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
// temp_count=5;
- // read_write_window_test_parameter(data_source,
+ // read_write_window_test_parameter(data_source,
// temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("run storeboot",0);
- while(1);
+ while (1) ;
} else
{
temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
@@ -32116,7 +31102,7 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
@@ -32126,13 +31112,13 @@
{
//write org value
- for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
{
- if((lane_step_count%2)==0)
+ if ((lane_step_count%2) == 0)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff);
}
- if((lane_step_count%2)==1)
+ if ((lane_step_count%2) == 1)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff);
}
@@ -32148,10 +31134,10 @@
test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_PASS; //pass 2 error 1
num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
- while(1);
+ while (1) ;
@@ -32161,62 +31147,62 @@
}
- if((test_arg_6_step_status==4)||(test_arg_6_step_status==6))
+ if ((test_arg_6_step_status == 4) || (test_arg_6_step_status == 6))
{
test_arg_4_step_flag_add_sticky_offset=DDR_TEST_STATUS_UBOOT_FINISH;
num_array[4] = test_arg_4_step_flag_add_sticky_offset ;
temp_count=4;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL;//DDR_TEST_NULL;
num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
- if((test_arg_6_step_status>=4)) ////kernel find from fail to pass offset from max ->0
+ if ((test_arg_6_step_status >= 4)) ////kernel find from fail to pass offset from max ->0
{
- if((test_arg_6_step_status==0)||(test_arg_6_step_status==2)
+ if ((test_arg_6_step_status == 0) || (test_arg_6_step_status == 2)
||(test_arg_6_step_status==4)||(test_arg_6_step_status==6)
)
{
test_arg_6_step_status=test_arg_6_step_status+1;
num_array[6] = test_arg_6_step_status ;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
- if((test_arg_6_step_status==1)||(test_arg_6_step_status==3)||(test_arg_6_step_status==5)||(test_arg_6_step_status==7))
+ if ((test_arg_6_step_status == 1) || (test_arg_6_step_status == 3) || (test_arg_6_step_status == 5) || (test_arg_6_step_status == 7))
{
- if(test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_PASS) //pass 2 error 1
+ if (test_arg_5_pass_fail_flag_add_sticky_offset == DDR_TEST_PASS) //pass 2 error 1
{
// test_arg_6_step_status=test_arg_6_step_status+1;
test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_NULL;
num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if((test_arg_6_step_status==1)||(test_arg_6_step_status==5))
+ if ((test_arg_6_step_status == 1) || (test_arg_6_step_status == 5))
{
- for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
{
- if((lane_step_count%2)==0)
+ if ((lane_step_count%2) == 0)
{
- if((((num_array[lane_step_count/2])>>0)&0xffff)<=test_arg_7_lcdlr_offset_l)
+ if ((((num_array[lane_step_count/2])>>0)&0xffff) <= test_arg_7_lcdlr_offset_l)
{
test_lcdlr_reach_lcdlr_limited_flag=test_lcdlr_reach_lcdlr_limited_flag+1;
}
}
- if((lane_step_count%2)==1)
+ if ((lane_step_count%2) == 1)
{
- if((((num_array[lane_step_count/2])>>16)&0xffff)<=test_arg_7_lcdlr_offset_l)
+ if ((((num_array[lane_step_count/2])>>16)&0xffff) <= test_arg_7_lcdlr_offset_l)
{
test_lcdlr_reach_lcdlr_limited_flag=test_lcdlr_reach_lcdlr_limited_flag+1;
}
@@ -32230,35 +31216,35 @@
}
// if(test_lcdlr_reach_lcdlr_limited_flag)
{
- test_arg_6_step_status=test_arg_6_step_status+1;
+ test_arg_6_step_status=test_arg_6_step_status+1;
num_array[6] = test_arg_6_step_status ;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
- else if((test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_FAIL)
+ else if((test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_FAIL)
//||(test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_NULL))//pass 2 error 1
)
{
// test_arg_7_lcdlr_offset_l=(test_arg_7_lcdlr_offset&0xffff);
// test_arg_7_lcdlr_offset_r=((test_arg_7_lcdlr_offset>>16)&0xffff);
- if(((test_arg_6_step_status==1))||(test_arg_6_step_status==5))
+ if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
{
test_arg_7_lcdlr_offset_l=test_arg_7_lcdlr_offset_l-1;
}
else if(((test_arg_6_step_status==3))||(test_arg_6_step_status==7))
{
- test_arg_7_lcdlr_offset_r=test_arg_7_lcdlr_offset_r-1;
+ test_arg_7_lcdlr_offset_r=test_arg_7_lcdlr_offset_r-1;
}
test_arg_7_lcdlr_offset=(test_arg_7_lcdlr_offset_l|(test_arg_7_lcdlr_offset_r<<16));
num_array[7] = test_arg_7_lcdlr_offset ;
temp_count=7;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
@@ -32267,7 +31253,7 @@
test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL;
num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
@@ -32282,34 +31268,34 @@
{
- for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
{
printf("\n (num_array[%d]) ==%08x \n",lane_step_count/2,(num_array[lane_step_count/2]));
- if(((test_arg_6_step_status==1))||(test_arg_6_step_status==5))
+ if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
{
- if((lane_step_count%2)==0)
+ if ((lane_step_count%2) == 0)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff)-test_arg_7_lcdlr_offset_l;
- if((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
+ if ((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
{test_lcdlr_temp_value=0;
}
}
- if((lane_step_count%2)==1)
+ if ((lane_step_count%2) == 1)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff)-test_arg_7_lcdlr_offset_l;
- if((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
+ if ((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
{test_lcdlr_temp_value=0;
}
}
}
- if(((test_arg_6_step_status==3))||(test_arg_6_step_status==7))
+ if (((test_arg_6_step_status == 3)) || (test_arg_6_step_status == 7))
{
- if((lane_step_count%2)==0)
+ if ((lane_step_count%2) == 0)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff)+test_arg_7_lcdlr_offset_r;
}
- if((lane_step_count%2)==1)
+ if ((lane_step_count%2) == 1)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff)+test_arg_7_lcdlr_offset_r;
@@ -32328,17 +31314,17 @@
}
//here will dead
- if(test_arg_6_step_status>4)
+ if (test_arg_6_step_status>4)
{
//ddr_test_watchdog_disable(); //s
ddr_test_watchdog_enable(kernel_test_watchdog_time_s); //s
// test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL; //pass 2 error 1
// num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
// temp_count=5;
- // read_write_window_test_parameter(data_source,
+ // read_write_window_test_parameter(data_source,
// temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("run storeboot",0);
- while(1);
+ while (1) ;
} else
{
temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
@@ -32347,43 +31333,43 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
ddr_test_watchdog_clear();
{
//write org value
- for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
{
- if((lane_step_count%2)==0)
+ if ((lane_step_count%2) == 0)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff);
}
- if((lane_step_count%2)==1)
+ if ((lane_step_count%2) == 1)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff);
}
do_ddr_read_write_ddr_data_window_lcdlr( rank_index,lane_step_count,
(test_lcdlr_temp_value),DDR_PARAMETER_WRITE);
- }
+ }
}
test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_PASS; //pass 2 error 1
num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
}
}
- if(test_arg_6_step_status>=8) //finish
+ if (test_arg_6_step_status >= 8) //finish
{
ddr_test_watchdog_disable(); //s
printf("close watchdog\n");
@@ -32404,7 +31390,7 @@
test_arg_4_step_flag_add_sticky_offset=DDR_TEST_STATUS_KERNEL_FINISH;
num_array[4] = test_arg_4_step_flag_add_sticky_offset ;
temp_count=4;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
}
@@ -32414,13 +31400,13 @@
// test_arg_6_step_status=test_arg_6_step_status+1;
num_array[6] = test_arg_6_step_status ;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
ddr_test_watchdog_disable(); //s
// test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL; //pass 2 error 1
run_command("run storeboot",0);
- while(1);
+ while (1) ;
return 1;
}
@@ -32576,7 +31562,7 @@
printf("test_arg_6 lcdlr_temp_count=%d\n",num_arry[6]);
printf("test_arg_7=%d\n",num_arry[7]);
- if((num_arry[7]==DMC_STICKY_MAGIC_1)) //for check magic number make sume enter test command
+ if ((num_arry[7] == DMC_STICKY_MAGIC_1)) //for check magic number make sume enter test command
{boot_times++;
}
@@ -32596,7 +31582,7 @@
- if(test_arg_2_step==0)
+ if (test_arg_2_step == 0)
{
test_arg_0_cmd0=0x28;
@@ -32627,7 +31613,7 @@
ddr_feq_test_step=rd_reg(sticky_reg_base_add+(8<<2));
//
- //p_char_ddr_test_step= getenv("ddr_feq_test_step");
+ //p_char_ddr_test_step= env_get("ddr_feq_test_step");
// if (p_char_ddr_test_step)
{
// printf("%s",p_char_ddr_test_step);
@@ -32636,7 +31622,7 @@
printf("ddr_feq_test_step=%d\n",ddr_feq_test_step);
}
if (ddr_feq_test_step) {
- //p_char_freq_org= getenv("ddr_feq_org");
+ //p_char_freq_org= env_get("ddr_feq_org");
//if (p_char_freq_org)
{
//printf("%s",p_char_freq_org);
@@ -32652,7 +31638,7 @@
ddr_clk_org=ddr_clk;
sprintf(char_freq_org,"%04d",ddr_clk);
printf("\nddr_org_freq=%s\n",char_freq_org);
- //setenv("ddr_feq_org", char_freq_org);
+ //env_set("ddr_feq_org", char_freq_org);
writel(ddr_clk,(sticky_reg_base_add+(9<<2)));
@@ -32662,8 +31648,8 @@
// sprintf(freq_table,"%s%04d %01d %01d ",freq_table,(temp_count*12),0,0);
sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))));
printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
- //setenv(char_freq_name_table, "0");
- //setenv("ddr_feq_test_step", "1");
+ //env_set(char_freq_name_table, "0");
+ //env_set("ddr_feq_test_step", "1");
writel(0,(sticky_reg_base_add+((10+temp_count-(start_freq/24))<<2)));
writel(1,(sticky_reg_base_add+(8<<2)));
temp_count++;
@@ -32674,8 +31660,8 @@
// sprintf(freq_table,"%s%04d %01d %01d ",freq_table,(temp_count*12),0,0);
sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))));
printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
- //setenv(char_freq_name_table, "3");
- //setenv("ddr_feq_test_step", "1");
+ //env_set(char_freq_name_table, "3");
+ //env_set("ddr_feq_test_step", "1");
writel(3,(sticky_reg_base_add+((10+temp_count-(start_freq/24))<<2)));
writel(1,(sticky_reg_base_add+(8<<2)));
temp_count++;
@@ -32685,18 +31671,18 @@
// sprintf(freq_table,"%s%04d %01d %01d ",freq_table,(temp_count*12),0,0);
sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))));
printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
- //setenv(char_freq_name_table, "3");
- //setenv("ddr_feq_test_step", "1");
+ //env_set(char_freq_name_table, "3");
+ //env_set("ddr_feq_test_step", "1");
writel(3,(sticky_reg_base_add+((10+temp_count-(start_freq/24))<<2)));
writel(1,(sticky_reg_base_add+(8<<2)));
temp_count++;
}
- //p_char_store_boot= getenv("storeboot");
+ //p_char_store_boot= env_get("storeboot");
//if (p_char_store_boot)
//printf("storeboot %s\n",p_char_store_boot);
// sprintf(char_cmd_table,"ddr_test_cmd 0x1c 0x%08x %d %d %d;%s;",ddr_test_size,start_freq,end_freq,test_loops,p_char_store_boot);
- // setenv("storeboot", char_cmd_table);
+ // env_set("storeboot", char_cmd_table);
// run_command("save",0);
@@ -32716,7 +31702,7 @@
sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))));
printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
ddr_feq_test_step=rd_reg(sticky_reg_base_add+(8<<2));
- // p_char_freq_name_table= getenv(char_freq_name_table);
+ // p_char_freq_name_table= env_get(char_freq_name_table);
// if (p_char_freq_name_table)
{
// printf("%s\n",p_char_freq_name_table);
@@ -32744,14 +31730,14 @@
sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count_sub*24))));
printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
// freq_table_test_value[temp_count_sub] =1;
- // setenv(char_freq_name_table, "3");
+ // env_set(char_freq_name_table, "3");
writel(3,(sticky_reg_base_add+((10+temp_count_sub-(start_freq/24))<<2)));
temp_count_sub++;
}
{
ddr_feq_test_step++;
- //setenv("ddr_feq_test_step", "2");
+ //env_set("ddr_feq_test_step", "2");
// run_command("save",0);
writel(2,(sticky_reg_base_add+(8<<2)));
@@ -32777,7 +31763,7 @@
sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))));
printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
freq_table_test_value[temp_count] =1;
- // setenv(char_freq_name_table, "1");
+ // env_set(char_freq_name_table, "1");
// run_command("save",0);
writel(1,(sticky_reg_base_add+((10+temp_count-(start_freq/24))<<2)));
@@ -32793,13 +31779,13 @@
if (temp_test_error)
{
freq_table_test_value[temp_count] =1;
- // setenv(char_freq_name_table, "1");
+ // env_set(char_freq_name_table, "1");
writel(1,(sticky_reg_base_add+((10+temp_count-(start_freq/24))<<2)));
}
else
{
freq_table_test_value[temp_count] =2;
- // setenv(char_freq_name_table, "2");
+ // env_set(char_freq_name_table, "2");
writel(2,(sticky_reg_base_add+((10+temp_count-(start_freq/24))<<2)));
}
// run_command("save",0);
@@ -32826,7 +31812,7 @@
temp_count++;
}
ddr_feq_test_step++;
- //setenv("ddr_feq_test_step", "2");
+ //env_set("ddr_feq_test_step", "2");
//run_command("save",0);
writel(2,(sticky_reg_base_add+(8<<2)));
@@ -32841,7 +31827,7 @@
sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))));
printf("\nchar_freq_name_table=%s\n",char_freq_name_table);
- // p_char_freq_name_table= getenv(char_freq_name_table);
+ // p_char_freq_name_table= env_get(char_freq_name_table);
// if (p_char_freq_name_table)
{
// printf("%s\n",p_char_freq_name_table);
@@ -32858,7 +31844,7 @@
while (temp_count<((DDR_TEST_MAX_FREQ)/24)) {
sprintf(char_freq_name_table,"ddr_fre_%04d",(pll_convert_to_ddr_clk(ddr_clk_convert_to_pll(temp_count*24))));
- // p_char_freq_name_table= getenv(char_freq_name_table);
+ // p_char_freq_name_table= env_get(char_freq_name_table);
// if (p_char_freq_name_table)
{
// printf("%s\n",p_char_freq_name_table);
@@ -32888,7 +31874,7 @@
// printf("\nstr=%s\n",str);
//sprintf(str, "%lx", value);
- // setenv("env_ddrtest", str);
+ // env_set("env_ddrtest", str);
//run_command("save",0);
//*/
@@ -32930,7 +31916,7 @@
#define DDR3_ODT_20OHM 4
#define DDR3_ODT_30OHM 5
- // lpddr2 drv odt
+ // lpddr2 drv odt
#define LPDDR2_DRV_34OHM 1
#define LPDDR2_DRV_40OHM 2
#define LPDDR2_DRV_48OHM 3
@@ -32939,7 +31925,7 @@
#define LPDDR2_DRV_120OHM 7
#define LPDDR2_ODT_0OHM 0
- // lpddr3 drv odt
+ // lpddr3 drv odt
#define LPDDR3_DRV_34OHM 1
#define LPDDR3_DRV_40OHM 2
#define LPDDR3_DRV_48OHM 3
@@ -32996,7 +31982,7 @@
zqcr = 0;
}
bist_test_dq_index=0xff;
- if(zqcr==0xffffffff)
+ if (zqcr == 0xffffffff)
{
ddr_full_test_enable=1;
zqcr=0;}
@@ -33085,25 +32071,25 @@
soc_dram_drv_odt_use_vlaue = 0;
}
}
- if(soc_dram_drv_odt_use_vlaue)
+ if (soc_dram_drv_odt_use_vlaue)
{if(zqcr)
{printf("zqcr[0x%08x],\n", zqcr);
{
soc_ac_drv=zqcr%100;
- if(soc_ac_drv>100)
+ if (soc_ac_drv>100)
{soc_ac_drv=0;}
- if(soc_ac_drv==0)
+ if (soc_ac_drv == 0)
{soc_ac_drv=1;}
soc_ac_drv=(480/soc_ac_drv)-1;
- if(ddr_type==DDR_TYPE_DDR3)
+ if (ddr_type == DDR_TYPE_DDR3)
{
- if(soc_ac_drv>0xf)
+ if (soc_ac_drv>0xf)
{soc_ac_drv=zq0pr_org&0xf;}
}
- if(ddr_type==DDR_TYPE_DDR4)
+ if (ddr_type == DDR_TYPE_DDR4)
{
- if(soc_ac_drv>0xf)
+ if (soc_ac_drv>0xf)
{soc_ac_drv=(zq0pr_org>>8)&0xf;}
}
}
@@ -33111,22 +32097,22 @@
{
soc_ac_odt=zqcr/100;
- if(soc_ac_odt>240)
+ if (soc_ac_odt>240)
{soc_ac_odt=480;}
- if(soc_ac_odt==0)
+ if (soc_ac_odt == 0)
{soc_ac_odt=1;}
- if(ddr_type==DDR_TYPE_DDR3)
+ if (ddr_type == DDR_TYPE_DDR3)
{
soc_ac_odt=(360/soc_ac_odt)-1;
- if(soc_ac_odt>0xf)
+ if (soc_ac_odt>0xf)
{soc_ac_odt=(zq0pr_org>>4)&0xf;}
}
- if(ddr_type==DDR_TYPE_DDR4)
+ if (ddr_type == DDR_TYPE_DDR4)
{
soc_ac_odt=(480/soc_ac_odt)-1;
- if(soc_ac_odt>0xf)
+ if (soc_ac_odt>0xf)
{soc_ac_odt=(zq0pr_org>>16)&0xf;}
}
}
@@ -33134,16 +32120,16 @@
zqcr=(soc_ac_odt<<16)|(soc_ac_drv<<12)|(soc_ac_drv<<8)|(soc_ac_odt<<4)|(soc_ac_drv);
printf("zqcr[0x%08x],soc_ac_odt [0x%08x],soc_ac_drv [0x%08x]\n", zqcr,soc_ac_odt,soc_ac_drv);
}
- if(zqpr_soc_dram)
+ if (zqpr_soc_dram)
{printf("zqpr_soc_dram[0x%08x],\n", zqpr_soc_dram);
{
soc_data_drv=zqpr_soc_dram%100;
printf("soc_data_drv[%d],\n", soc_data_drv);
- if(soc_data_drv>100)
+ if (soc_data_drv>100)
{soc_data_drv=0;
}
- if(soc_data_drv==0)
+ if (soc_data_drv == 0)
{soc_data_drv=1;
//soc_data_drv_odt_adj_enable=0;
}
@@ -33152,14 +32138,14 @@
}
soc_data_drv=(480/soc_data_drv)-1;
- if(ddr_type==DDR_TYPE_DDR3)
+ if (ddr_type == DDR_TYPE_DDR3)
{
- if(soc_data_drv>0xf)
+ if (soc_data_drv>0xf)
{soc_data_drv=zq1pr_org&0xf;}
}
- if(ddr_type==DDR_TYPE_DDR4)
+ if (ddr_type == DDR_TYPE_DDR4)
{
- if(soc_data_drv>0xf)
+ if (soc_data_drv>0xf)
{soc_data_drv=(zq1pr_org>>8)&0xf;}
}
}
@@ -33168,22 +32154,22 @@
{
soc_data_odt=(zqpr_soc_dram/100)%1000;
printf("soc_data_odt[%d],\n", soc_data_odt);
- if(soc_data_odt>240)
+ if (soc_data_odt>240)
{soc_data_odt=360;}
- if(soc_data_odt==0)
+ if (soc_data_odt == 0)
{soc_data_odt=1;}
- if(ddr_type==DDR_TYPE_DDR3)
+ if (ddr_type == DDR_TYPE_DDR3)
{
soc_data_odt=(360/soc_data_odt)-1;
- if(soc_data_odt>0xf)
+ if (soc_data_odt>0xf)
{soc_data_odt=(zq1pr_org>>4)&0xf;}
}
- if(ddr_type==DDR_TYPE_DDR4)
+ if (ddr_type == DDR_TYPE_DDR4)
{
soc_data_odt=(480/soc_data_odt)-1;
- if(soc_data_odt>0xf)
+ if (soc_data_odt>0xf)
{soc_data_odt=(zq1pr_org>>16)&0xf;}
}
@@ -33195,18 +32181,18 @@
dram_drv=(zqpr_soc_dram/100000)%100;
printf("dram_drv[%d],\n", dram_drv);
- if(dram_drv>100)
+ if (dram_drv>100)
{dram_drv=0;}
- if(dram_drv==0)
+ if (dram_drv == 0)
{
dram_data_drv_adj_enable=0;}
else
{dram_data_drv_adj_enable=1;
}
- if(ddr_type==DDR_TYPE_DDR3)
+ if (ddr_type == DDR_TYPE_DDR3)
{
- if(dram_drv>=40)
+ if (dram_drv >= 40)
{dram_drv=0;}
else
@@ -33215,9 +32201,9 @@
}
- if(ddr_type==DDR_TYPE_DDR4)
+ if (ddr_type == DDR_TYPE_DDR4)
{
- if(dram_drv<48)
+ if (dram_drv<48)
{dram_drv=0;}
else
@@ -33230,9 +32216,9 @@
{
dram_odt=(zqpr_soc_dram/100000)/100;
printf("dram_odt[%d],\n", dram_odt);
- if(dram_odt>240)
+ if (dram_odt>240)
{dram_odt=480;}
- if(dram_odt==0)
+ if (dram_odt == 0)
{
dram_data_odt_adj_enable=0;
}
@@ -33241,9 +32227,9 @@
}
- if(ddr_type==DDR_TYPE_DDR3)
+ if (ddr_type == DDR_TYPE_DDR3)
{
- if(dram_odt>160)
+ if (dram_odt>160)
{dram_odt=0;}
else if (dram_odt>90)
{dram_odt=2;}
@@ -33257,9 +32243,9 @@
{dram_odt=4;}
}
- if(ddr_type==DDR_TYPE_DDR4)
+ if (ddr_type == DDR_TYPE_DDR4)
{
- if(dram_odt>280)
+ if (dram_odt>280)
{dram_odt=0;}
else if (dram_odt>180)
{dram_odt=4;}
@@ -33373,7 +32359,7 @@
printf("soc_data_drv_odt [0x%08x],dram_drv [0x%08x],dram_odt [0x%08x]\n", soc_data_drv_odt,dram_drv,dram_odt);
pll=pll|(bist_test_dq_index<<12);
- if(ddr_full_test_enable)
+ if (ddr_full_test_enable)
{
pll=(ddr_full_test_enable<<21)|pll;
printf("ddr_full_test_enable %08x,set sticky reg1 bit 21 1\n", ddr_full_test_enable);
@@ -33406,7 +32392,7 @@
// *P_WATCHDOG_RESET = 0;
ddr_test_watchdog_reset_system();
#endif
- while(1);
+ while (1) ;
return 0;
usage:
@@ -33505,16 +32491,16 @@
{
unsigned reg_add=0;
- if(add_index==0)
+ if (add_index == 0)
reg_add=(DDR0_PUB_ACLCDLR);
- if(add_index==1)
+ if (add_index == 1)
reg_add=(DDR0_PUB_ACBDLR0);
{
- if(read_write_flag==DDR_PARAMETER_READ)
+ if (read_write_flag == DDR_PARAMETER_READ)
{
lcdlr_value=(((readl(reg_add))>>0)&0x1ff);
}
- if(read_write_flag==DDR_PARAMETER_WRITE)
+ if (read_write_flag == DDR_PARAMETER_WRITE)
{
wr_reg(reg_add, ((lcdlr_value&0x1ff)<<0));
}
@@ -33535,7 +32521,7 @@
//dwc_ddrphy_apb_wr((0<<20)|(2<<16)|(0<<12)|(0xb0),0);
//dwc_ddrphy_apb_wr(0xd0000,0);
//dwc_ddrphy_apb_wr(0xd0000,1);
-
+
//*(volatile uint32_t *)(int_convter_p(test_addr))=des_pattern(temp_i,2,temp_k,temp_i);
//dwc_ddrphy_apb_wr((ps<<20)|(0<<16)|(instance_num<<12)|(0x80),);
@@ -33545,7 +32531,7 @@
//argv[1],a
//argv[2],test length
//argv[3],test step
-//argv[4],test_mode,direction,0,up; 1,down; 2,down first,up follow;
+//argv[4],test_mode,direction,0,up; 1,down; 2,down first,up follow;
//argv[5],ACx;0-AC0,1-AC1,2-AC2...,9-AC9
#if 0
@@ -33577,23 +32563,23 @@
{
goto usage;
}
- else
+ else
{
ddr_test_size = simple_strtoull_ddr(argv[2], &endp, 16);
if (*argv[2] == 0 || *endp != 0)
{
ddr_test_size = DDR_CORSS_TALK_TEST_SIZE;
- }
+ }
}
- if (argc >3)
+ if (argc >3)
{
test_step = simple_strtoull_ddr(argv[3], &endp, 16);
if (*argv[3] == 0 || *endp != 0)
{
test_step = 1;
- }
+ }
}
- if (argc >4)
+ if (argc >4)
{
test_mode = simple_strtoull_ddr(argv[4], &endp, 16); //²âÊÔ·½Ïò
if (*argv[4] == 0 || *endp != 0)
@@ -33608,7 +32594,7 @@
if (test_mode >2) test_mode = 2;
test_ACx =0;
- if (argc >5)
+ if (argc >5)
{
test_ACx= simple_strtoull_ddr(argv[5], &endp, 16);
@@ -33640,10 +32626,10 @@
while (dq_lcd_bdl_temp_reg_value>0)
{
temp_test_error=0;
- for(temp_count=0;temp_count < test_step;temp_count++)
+ for (temp_count=0;temp_count < test_step;temp_count++)
{
- if(dq_lcd_bdl_temp_reg_value==0) break;
- dq_lcd_bdl_temp_reg_value--;
+ if (dq_lcd_bdl_temp_reg_value == 0) break;
+ dq_lcd_bdl_temp_reg_value--;
};
dq_lcd_bdl_temp_reg_value--;
printf("\n reg_add==0x%08x,right temp==0x%08x\n,value==0x%08x",reg_add,dq_lcd_bdl_temp_reg_value,
@@ -33664,11 +32650,11 @@
printf("\n org==0x%08x,left edge==0x%08x\n ",acbdlr_x_reg_org,dq_lcd_bdl_temp_reg_value);
acbdlr_x_reg_min= (int)dq_lcd_bdl_temp_reg_value;
- printf("acbdlr_x_reg_min==0x%08x\n",acbdlr_x_reg_min);
+ printf("acbdlr_x_reg_min==0x%08x\n",acbdlr_x_reg_min);
dq_lcd_bdl_temp_reg_value=0;
//»Ö¸´Ä¬ÈÏÖµ
- dwc_ddrphy_apb_wr((0<<20)|(0<<16)|(test_ACx<<12)|(0x80),(uint16_t)acbdlr_x_reg_org);
+ dwc_ddrphy_apb_wr((0<<20)|(0<<16)|(test_ACx<<12)|(0x80),(uint16_t)acbdlr_x_reg_org);
}
if ((test_mode == 0) || (test_mode == 2))
@@ -33679,10 +32665,10 @@
while (dq_lcd_bdl_temp_reg_value<ACX_MAX)
{
temp_test_error = 0;
- for(temp_count=0;temp_count < test_step;temp_count++)
+ for (temp_count=0;temp_count < test_step;temp_count++)
{
- if(dq_lcd_bdl_temp_reg_value>=ACX_MAX) break;
- dq_lcd_bdl_temp_reg_value++;
+ if (dq_lcd_bdl_temp_reg_value >= ACX_MAX) break;
+ dq_lcd_bdl_temp_reg_value++;
};
printf("\n reg_add==0x%08x,right temp==0x%08x\n,value==0x%08x",reg_add,dq_lcd_bdl_temp_reg_value,
dq_lcd_bdl_temp_reg_value-acbdlr_x_reg_org);
@@ -33714,8 +32700,8 @@
//ÏÈÍùϲ⣬ÔÙÍùÉϲ⣬²âÊÔ½áÊø£¬´òÓ¡½á¹û
printf("test AC%d window finish\n ",test_ACx);
printf("acbdlr_x_reg_min = 0x%08x\n",acbdlr_x_reg_min);
- printf("acbdlr_x_reg_max = 0x%08x\n",acbdlr_x_reg_max);
- }
+ printf("acbdlr_x_reg_max = 0x%08x\n",acbdlr_x_reg_max);
+ }
}
dwc_ddrphy_apb_wr(0xd0000,1);
return dq_lcd_bdl_temp_reg_value;
@@ -33740,15 +32726,15 @@
//argv[1],a ,no use,reserve,just for flag
//argv[2],rd/wr,0=read,1=write
//argv[3],AC0
-//argv[4],AC1
+//argv[4],AC1
//argv[5],AC2;...,9-AC9
int do_ddr_read_write_acx_g12a(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- unsigned int read_write_flag= 0;
+{
+ unsigned int read_write_flag= 0;
//unsigned int temp_test_error= 0;
unsigned int temp_count= 0;
- //unsigned int temp_reg_value[40];
+ //unsigned int temp_reg_value[40];
uint16_t ACx[10];
char *endp;
@@ -33759,17 +32745,17 @@
{
goto usage;
}
- else
+ else
{
read_write_flag = simple_strtoull_ddr(argv[2], &endp, 16);
if (*argv[2] == 0 || *endp != 0)
{
read_write_flag = 0;
- }
+ }
}
- if ((argc >12) && (read_write_flag == 1))
+ if ((argc >12) && (read_write_flag == 1))
{
- for(temp_count=0;temp_count < 10;temp_count++)
+ for (temp_count=0;temp_count < 10;temp_count++)
{
//read AC0-AC9 to ACx[0-9]
ACx[temp_count] = simple_strtoull_ddr(argv[temp_count+3], &endp, 16);
@@ -33786,21 +32772,21 @@
{
if (read_write_flag == 0)
{
- for(temp_count=0;temp_count < 10;temp_count++)
+ for (temp_count=0;temp_count < 10;temp_count++)
{
ACx[temp_count]=dwc_ddrphy_apb_rd((0<<20)|(0<<16)|(temp_count<<12)|(0x80));
- printf("Read: AC%d[0x%08x]==0x%08x\n",temp_count,(((0<<20)|(0<<16)|(temp_count<<12)|(0x80))<<1) + 0xfe000000,ACx[temp_count]);
+ printf("Read: AC%d[0x%08x]==0x%08x\n",temp_count,(((0<<20)|(0<<16)|(temp_count<<12)|(0x80))<<1) + 0xfe000000,ACx[temp_count]);
};
}
if (read_write_flag == 1)
{
- for(temp_count=0;temp_count < 10;temp_count++)
+ for (temp_count=0;temp_count < 10;temp_count++)
{
dwc_ddrphy_apb_wr(((0<<20)|(0<<16)|(temp_count<<12)|(0x80)),ACx[temp_count]);
- printf("Write: AC%d[0x%08x]==0x%08x\n",temp_count,(((0<<20)|(0<<16)|(temp_count<<12)|(0x80))<<1) + 0xfe000000,dwc_ddrphy_apb_rd((0<<20)|(0<<16)|(temp_count<<12)|(0x80)));
- };
+ printf("Write: AC%d[0x%08x]==0x%08x\n",temp_count,(((0<<20)|(0<<16)|(temp_count<<12)|(0x80))<<1) + 0xfe000000,dwc_ddrphy_apb_rd((0<<20)|(0<<16)|(temp_count<<12)|(0x80)));
+ };
}
dwc_ddrphy_apb_wr(0xd0000,1);
return 0;
@@ -33852,15 +32838,15 @@
}
*/
#if 0
- if ((test_index <= DMC_TEST_WINDOW_INDEX_TXDQDLY) ){
+ if ((test_index <= DMC_TEST_WINDOW_INDEX_TXDQDLY) ) {
result=(32*(((value>>6)&0xf)+((value>>5)&1))+(value&0x1f));
}
if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
- result=(32*(((value>>6)&0xf)+(((value>>5)&1)*1))+(value&0x1f)); //bit 5 change to 1 UI 20180711
- //result=(32*((((value>>5)&1)*1))+(value&0x1f)); //bit 5 change to 1 UI 20180711
+ result=(32*(((value>>6)&0xf)+(((value>>5)&1)*1))+(value&0x1f)); //bit 5 change to 1 UI 20180711
+ //result=(32*((((value>>5)&1)*1))+(value&0x1f)); //bit 5 change to 1 UI 20180711
}
- if ((test_index == DMC_TEST_WINDOW_INDEX_RXENDLY)){
+ if ((test_index == DMC_TEST_WINDOW_INDEX_RXENDLY)) {
result=(32*(((value>>6)&0x1f)+(((value>>5)&1)*1))+(value&0x1f));
}
if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
@@ -33886,7 +32872,7 @@
uint32_t ddr_cacl_phy_over_ride_back_reg(char test_index,uint32_t value )
{
- //#define DMC_TEST_WINDOW_INDEX_ATXDLY
+ //#define DMC_TEST_WINDOW_INDEX_ATXDLY
//#define DMC_TEST_WINDOW_INDEX_TXDQSDLY 2
//#define DMC_TEST_WINDOW_INDEX_RXCLKDLY 3
//#define DMC_TEST_WINDOW_INDEX_TXDQDLY 4
@@ -33913,7 +32899,7 @@
||(test_index==DMC_TEST_WINDOW_INDEX_RXENDLY)) {
//result=((value/32)<<6)+value%64;
result=value%64;
- if ((test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY)||(test_index == DMC_TEST_WINDOW_INDEX_RXENDLY)) { //use for txdqdly register ,because of this register bit 5 is no use jiaxing 20180814
+ if ((test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) || (test_index == DMC_TEST_WINDOW_INDEX_RXENDLY)) { //use for txdqdly register ,because of this register bit 5 is no use jiaxing 20180814
result=((value/32)<<6)+value%32;
}
}
@@ -33924,9 +32910,9 @@
#if 1
result=((value/32)<<6)+value%32;
/*
- if(enable_bit5)
+ if (enable_bit5)
{
- if((result>>6)&1)
+ if ((result>>6)&1)
{result=(result&0xffbf)|(1<<5);
}
}
@@ -33947,12 +32933,12 @@
dwc_ddrphy_apb_wr(0xd0000,0);//mw fe1a0000 0
// reg_base_adj=0xfe000000;
// reg_add=(((0<<20)|(0<<16)|(test_ACx<<12)|(0x80))<<1) + reg_base_adj;
- if(read_write_flag==DDR_PARAMETER_READ)
+ if (read_write_flag == DDR_PARAMETER_READ)
{
lcdlr_value=dwc_ddrphy_apb_rd((0<<20)|(0<<16)|(add_index<<12)|(0x80));
}
- if(read_write_flag==DDR_PARAMETER_WRITE)
+ if (read_write_flag == DDR_PARAMETER_WRITE)
{
dwc_ddrphy_apb_wr(((0<<20)|(0<<16)|(add_index<<12)|(0x80)), lcdlr_value);
@@ -33962,47 +32948,6 @@
return lcdlr_value;
}
-
-void dwc_window_reg_after_training_update_increas_dq(char over_ride_index,uint32_t over_ride_sub_index,uint32_t over_ride_increase_decrease,
- uint32_t step_value)
-{
- uint32_t delay_old_value=0;
- uint32_t delay_reg_value=0;
-
- uint64_t reg_add=0;
- if (!over_ride_index)
- return;
-
-
- if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) {
- reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0xc0+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36)));
- delay_old_value=dwc_ddrphy_apb_rd(reg_add);
- delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
- if(over_ride_increase_decrease==0)
- {
- delay_reg_value=delay_reg_value+step_value;
- if(delay_reg_value>255)
- delay_reg_value=255;
- }
- if(over_ride_increase_decrease!=0)
- {
- if(delay_reg_value>step_value)
- delay_reg_value=delay_reg_value-step_value;
- else
- delay_reg_value=0;
- }
- delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
- dwc_ddrphy_apb_wr(reg_add,delay_reg_value);
- // dwc_ddrphy_apb_wr(reg_add+4,delay_reg_value);
-
- }
-
-printf("reg_add %08x old_value %08x update_to %08x dec %d to %d \n",((unsigned int)(((reg_add) << 1)+0xfe000000)),
- delay_old_value,dwc_ddrphy_apb_rd(reg_add),ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value),
- (unsigned int)ddr_cacl_phy_delay_all_step(over_ride_index, dwc_ddrphy_apb_rd(reg_add)));
-
-}
-
void dwc_window_reg_after_training_update(char over_ride_index,uint32_t over_ride_sub_index,uint32_t over_ride_value)
{
uint32_t delay_old_value=0;
@@ -34094,15 +33039,15 @@
delay_old_value=dwc_ddrphy_apb_rd(reg_add);
//delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, over_ride_value);
delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
- if(over_ride_increase_decrease==0)
+ if (over_ride_increase_decrease == 0)
{
delay_reg_value=delay_reg_value+step_value;
- if(delay_reg_value>95)
+ if (delay_reg_value>95)
delay_reg_value=95;
}
- if(over_ride_increase_decrease!=0)
+ if (over_ride_increase_decrease == 1)
{
- if(delay_reg_value>=step_value)
+ if (delay_reg_value >= step_value)
delay_reg_value=delay_reg_value-step_value;
else
delay_reg_value=0;
@@ -34115,42 +33060,17 @@
delay_old_value=dwc_ddrphy_apb_rd(reg_add);
// dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0xd0+(over_ride_sub_index/4)),delay_reg_value);
// dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0x1d0+(over_ride_sub_index/4)),delay_reg_value);
-
-
-//some case will happen tdqs from 0x1f to 0x0 or 0x0 to 0x1f ,then fast boot write back will happen error ,because
-// fast boot write back will re-calculate coarse UI,then result dq phase fail.
-/*
- if(over_ride_increase_decrease==0)
+ if (over_ride_increase_decrease == 0)
// if(over_ride_value>ddr_cacl_phy_delay_all_step(over_ride_index,delay_old_value))
- {dwc_ddrphy_apb_wr(reg_add,((delay_old_value&0x3f)+step_value)|(delay_old_value&0xffc0));
- if(((delay_old_value&0x3f)+step_value)>0x3f)
+ {dwc_ddrphy_apb_wr(reg_add,((delay_old_value&0x3f)+step_value)|(delay_old_value&0xffc0));
+ if (((delay_old_value&0x3f)+step_value)>0x3f)
dwc_ddrphy_apb_wr(reg_add,0x3f|(delay_old_value&0xffc0));
- }
- else
- {//dwc_ddrphy_apb_wr(reg_add,((delay_old_value&0x3f)-step_value)|(delay_old_value&0xffc0));
- if(((delay_old_value&0x3f)<step_value))
- dwc_ddrphy_apb_wr(reg_add,(delay_old_value&0xffc0));
- else
- dwc_ddrphy_apb_wr(reg_add,((delay_old_value&0x3f)-step_value)|(delay_old_value&0xffc0));
}
-
-*/
-if((over_ride_sub_index%2)==0)
-{
- char temp_test_index=DMC_TEST_WINDOW_INDEX_TXDQDLY;
- char temp_count=0;
- // if(over_ride_increase_decrease==0)
- {
- for ( temp_count=0;temp_count<9;temp_count++)
- {
- dwc_window_reg_after_training_update_increas_dq(temp_test_index
- ,(((over_ride_sub_index)>>1)*9+temp_count), (!over_ride_increase_decrease),step_value) ;
- }
- }
-
- }
-
-
+ else
+ {dwc_ddrphy_apb_wr(reg_add,((delay_old_value&0x3f)-step_value)|(delay_old_value&0xffc0));
+ if (((delay_old_value&0x3f)<step_value))
+ dwc_ddrphy_apb_wr(reg_add,(delay_old_value&0xffc0));
+ }
// dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0x1d0+(over_ride_sub_index/4)),delay_reg_value|(delay_old_value&0xffc0));
// {enable_bit5=(delay_old_value>>5)&1;}
@@ -34160,17 +33080,17 @@
reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0xc0+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36)));
delay_old_value=dwc_ddrphy_apb_rd(reg_add);
delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
- if(over_ride_increase_decrease==0)
+ if (over_ride_increase_decrease == 0)
{
delay_reg_value=delay_reg_value+step_value;
- if(delay_reg_value>255)
+ if (delay_reg_value>255)
delay_reg_value=255;
}
- if(over_ride_increase_decrease!=0)
+ if (over_ride_increase_decrease == 1)
{
- if(delay_reg_value>step_value)
+ if (delay_reg_value>step_value)
delay_reg_value=delay_reg_value-step_value;
- else
+ else
delay_reg_value=0;
}
delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
@@ -34182,17 +33102,17 @@
reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%8)>>1)<<12)|(0x8c+(over_ride_sub_index/8)+((over_ride_sub_index%2)<<8)));
delay_old_value=dwc_ddrphy_apb_rd(reg_add);
delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
- if(over_ride_increase_decrease==0)
+ if (over_ride_increase_decrease == 0)
{
delay_reg_value=delay_reg_value+step_value;
- if(delay_reg_value>95)
+ if (delay_reg_value>95)
delay_reg_value=95;
}
- if(over_ride_increase_decrease!=0)
+ if (over_ride_increase_decrease == 1)
{
- if(delay_reg_value>step_value)
+ if (delay_reg_value>step_value)
delay_reg_value=delay_reg_value-step_value;
- else
+ else
delay_reg_value=0;
}
delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
@@ -34204,17 +33124,17 @@
reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0x68+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36)));
delay_old_value=dwc_ddrphy_apb_rd(reg_add);
delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
- if(over_ride_increase_decrease==0)
+ if (over_ride_increase_decrease == 0)
{
delay_reg_value=delay_reg_value+step_value;
- if(delay_reg_value>63)
+ if (delay_reg_value>63)
delay_reg_value=63;
}
- if(over_ride_increase_decrease!=0)
+ if (over_ride_increase_decrease == 1)
{
- if(delay_reg_value>step_value)
+ if (delay_reg_value>step_value)
delay_reg_value=delay_reg_value-step_value;
- else
+ else
delay_reg_value=0;
}
delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
@@ -34225,17 +33145,17 @@
reg_add=((0<<20)|(1<<16)|((over_ride_sub_index%8)<<12)|(0x80+(over_ride_sub_index/8)));
delay_old_value=dwc_ddrphy_apb_rd(reg_add);
delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
- if(over_ride_increase_decrease==0)
+ if (over_ride_increase_decrease == 0)
// if(over_ride_value>ddr_cacl_phy_delay_all_step(over_ride_index,delay_old_value))
- {
+ {
dwc_ddrphy_apb_wr(reg_add,((delay_old_value&0x3f)+step_value)|(delay_old_value&0xffc0));
- if(((delay_old_value&0x3f)+step_value)>0x3f)
+ if (((delay_old_value&0x3f)+step_value)>0x3f)
dwc_ddrphy_apb_wr(reg_add,0x3f|(delay_old_value&0xffc0));
}
else
{
dwc_ddrphy_apb_wr(reg_add,((delay_old_value&0x3f)-step_value)|(delay_old_value&0xffc0));
- if(((delay_old_value&0x3f)<step_value))
+ if (((delay_old_value&0x3f)<step_value))
dwc_ddrphy_apb_wr(reg_add,(delay_old_value&0xffc0));
}
// delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
@@ -34249,17 +33169,17 @@
reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40));
delay_old_value=dwc_ddrphy_apb_rd(reg_add);
delay_reg_value=delay_old_value;
- if(over_ride_increase_decrease==0)
+ if (over_ride_increase_decrease == 0)
{
delay_reg_value=delay_reg_value+step_value;
- if(delay_reg_value>127)
+ if (delay_reg_value>127)
delay_reg_value=127;
}
- if(over_ride_increase_decrease!=0)
+ if (over_ride_increase_decrease == 1)
{
- if(delay_reg_value>=step_value)
+ if (delay_reg_value >= step_value)
delay_reg_value=delay_reg_value-step_value;
- else
+ else
delay_reg_value=0;
}
//delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
@@ -34295,7 +33215,7 @@
if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
reg_add=((0<<20)|(0<<16)|(over_ride_sub_index<<12)|(0x80));
delay_old_value=dwc_ddrphy_apb_rd(reg_add);
- for( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
+ for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
{
dwc_window_reg_after_training_update_increas_sub(over_ride_index
,((over_ride_sub_index)), over_ride_increase_decrease,1) ;
@@ -34309,17 +33229,17 @@
// dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0xd0+(over_ride_sub_index/4)),delay_reg_value);
// dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%4)<<12)|(0x1d0+(over_ride_sub_index/4)),delay_reg_value);
delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
- if(over_ride_increase_decrease==0)
+ if (over_ride_increase_decrease == 0)
{
delay_reg_value=delay_reg_value+offset_value;
- if(delay_reg_value>96)
+ if (delay_reg_value>96)
delay_reg_value=96;
}
- if(over_ride_increase_decrease==1)
+ if (over_ride_increase_decrease == 1)
{
- if(delay_reg_value>=offset_value)
+ if (delay_reg_value >= offset_value)
delay_reg_value=delay_reg_value-offset_value;
- else
+ else
delay_reg_value=0;
}
delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
@@ -34329,7 +33249,7 @@
// {enable_bit5=(delay_old_value>>5)&1;}
//delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, over_ride_value,enable_bit5);
*/
- for( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
+ for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
{
dwc_window_reg_after_training_update_increas_sub(over_ride_index
,((over_ride_sub_index)), over_ride_increase_decrease,1) ;
@@ -34340,24 +33260,24 @@
delay_old_value=dwc_ddrphy_apb_rd(reg_add);
/*
delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
- if(over_ride_increase_decrease==0)
+ if (over_ride_increase_decrease == 0)
{
delay_reg_value=delay_reg_value+offset_value;
- if(delay_reg_value>96)
+ if (delay_reg_value>96)
delay_reg_value=96;
}
- if(over_ride_increase_decrease==1)
+ if (over_ride_increase_decrease == 1)
{
- if(delay_old_value>=offset_value)
+ if (delay_old_value >= offset_value)
delay_reg_value=delay_reg_value-offset_value;
- else
+ else
delay_reg_value=0;
}
delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
dwc_ddrphy_apb_wr(reg_add,delay_reg_value|(delay_old_value&0xffc0));
dwc_ddrphy_apb_wr(reg_add+4,delay_reg_value|(delay_old_value&0xffc0));
*/
- for( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
+ for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
{
dwc_window_reg_after_training_update_increas_sub(over_ride_index
,((over_ride_sub_index)), over_ride_increase_decrease,1) ;
@@ -34365,30 +33285,30 @@
/*
delay_old_value=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|((over_ride_sub_index%8)<<12)|(0x18c+(over_ride_sub_index/8)));
- if(over_ride_increase_decrease==0)
+ if (over_ride_increase_decrease == 0)
delay_reg_value=delay_old_value+1;
- if(over_ride_increase_decrease==1)
+ if (over_ride_increase_decrease == 1)
delay_reg_value=delay_old_value-1;
dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%8)<<12)|(0x18c+(over_ride_sub_index/8)),delay_reg_value|(delay_old_value&0xffc0));
dwc_ddrphy_apb_wr((0<<20)|(1<<16)|((over_ride_sub_index%8)<<12)|(0x190+(over_ride_sub_index/8)),delay_reg_value|(delay_old_value&0xffc0));
- */
+ */
}
if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) {
reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0xc0+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36)));
delay_old_value=dwc_ddrphy_apb_rd(reg_add);
/*
delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
- if(over_ride_increase_decrease==0)
+ if (over_ride_increase_decrease == 0)
{
delay_reg_value=delay_reg_value+offset_value;
- if(delay_reg_value>96)
+ if (delay_reg_value>96)
delay_reg_value=96;
}
- if(over_ride_increase_decrease==1)
+ if (over_ride_increase_decrease == 1)
{
- if(delay_reg_value>=offset_value)
+ if (delay_reg_value >= offset_value)
delay_reg_value=delay_reg_value-offset_value;
- else
+ else
delay_reg_value=0;
}
//delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index,delay_old_value)+1;
@@ -34398,7 +33318,7 @@
delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
dwc_ddrphy_apb_wr(reg_add,delay_reg_value);
*/
- for( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
+ for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
{
dwc_window_reg_after_training_update_increas_sub(over_ride_index
,((over_ride_sub_index)), over_ride_increase_decrease,1) ;
@@ -34410,23 +33330,23 @@
delay_old_value=dwc_ddrphy_apb_rd(reg_add);
/*
delay_reg_value=delay_old_value;
- if(over_ride_increase_decrease==0)
+ if (over_ride_increase_decrease == 0)
{
delay_reg_value=delay_reg_value+offset_value;
- if(delay_reg_value>96)
+ if (delay_reg_value>96)
delay_reg_value=96;
}
- if(over_ride_increase_decrease==1)
+ if (over_ride_increase_decrease == 1)
{
- if(delay_reg_value>=offset_value)
+ if (delay_reg_value >= offset_value)
delay_reg_value=delay_reg_value-offset_value;
- else
+ else
delay_reg_value=0;
}
delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
dwc_ddrphy_apb_wr(reg_add,delay_reg_value);
*/
- for( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
+ for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
{
dwc_window_reg_after_training_update_increas_sub(over_ride_index
,((over_ride_sub_index)), over_ride_increase_decrease,1) ;
@@ -34434,28 +33354,28 @@
}
if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXENDLY) {
-
+
reg_add=((0<<20)|(1<<16)|((over_ride_sub_index%8)<<12)|(0x80+(over_ride_sub_index/8)));
delay_old_value=dwc_ddrphy_apb_rd(reg_add);
/*
delay_reg_value=ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
- if(over_ride_increase_decrease==0)
+ if (over_ride_increase_decrease == 0)
{
delay_reg_value=delay_reg_value+offset_value;
- if(delay_reg_value>96)
+ if (delay_reg_value>96)
delay_reg_value=96;
}
- if(over_ride_increase_decrease==1)
+ if (over_ride_increase_decrease == 1)
{
- if(delay_reg_value>=offset_value)
+ if (delay_reg_value >= offset_value)
delay_reg_value=delay_reg_value-offset_value;
- else
+ else
delay_reg_value=0;
}
delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
dwc_ddrphy_apb_wr(reg_add,delay_reg_value|(delay_old_value&0xffc0));
*/
- for( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
+ for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
{
dwc_window_reg_after_training_update_increas_sub(over_ride_index
,((over_ride_sub_index)), over_ride_increase_decrease,1) ;
@@ -34464,30 +33384,30 @@
if (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) {
-
+
//dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40),over_ride_value);
//reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(0x68+((over_ride_sub_index%9)<<8)+(over_ride_sub_index/36)));
reg_add=((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40));
delay_old_value=dwc_ddrphy_apb_rd(reg_add);
/*
delay_reg_value=delay_old_value;
- if(over_ride_increase_decrease==0)
+ if (over_ride_increase_decrease == 0)
{
delay_reg_value=delay_reg_value+offset_value;
- if(delay_reg_value>127)
+ if (delay_reg_value>127)
delay_reg_value=127;
}
- if(over_ride_increase_decrease==1)
+ if (over_ride_increase_decrease == 1)
{
- if(delay_reg_value>=offset_value)
+ if (delay_reg_value >= offset_value)
delay_reg_value=delay_reg_value-offset_value;
- else
+ else
delay_reg_value=0;
}
//delay_reg_value=ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
dwc_ddrphy_apb_wr(reg_add,delay_reg_value);
*/
- for( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
+ for ( temp_count_3=0;temp_count_3<offset_value;temp_count_3++)
{
dwc_window_reg_after_training_update_increas_sub(over_ride_index
,((over_ride_sub_index)), over_ride_increase_decrease,1) ;
@@ -34496,21 +33416,21 @@
printf("over_ride_increase_decrease==%d\n",over_ride_increase_decrease);
-if(over_ride_increase_decrease==1)
+if (over_ride_increase_decrease == 1)
{
unsigned int org_cacl_value=(delay_old_value)&0x3f;
printf("org_cacl_value==%d\n",org_cacl_value);
printf("offset_value==%d\n",offset_value);
- if((org_cacl_value&0x3f)<offset_value){
+ if ((org_cacl_value&0x3f)<offset_value) {
char temp_test_index_2=0;
char temp_count_4=0;
char temp_count_2=0;
- if(over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY)
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY)
{
temp_test_index_2=DMC_TEST_WINDOW_INDEX_TXDQDLY;
- if(over_ride_sub_index%2==0){
- for(temp_count_2=0;temp_count_2<9;temp_count_2++)
+ if (over_ride_sub_index%2 == 0) {
+ for (temp_count_2=0;temp_count_2<9;temp_count_2++)
{for(temp_count_4=0;temp_count_4<(offset_value-org_cacl_value);temp_count_4++)
{
dwc_window_reg_after_training_update_increas_sub(temp_test_index_2
@@ -34525,43 +33445,43 @@
(over_ride_index-1):
(over_ride_index+1)), 0) ;
}
-*/
+*/
}
-if(over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY)
+if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY)
{
temp_test_index_2=DMC_TEST_WINDOW_INDEX_RXPBDLY;
-for( temp_count_2=0;temp_count_2<4;temp_count_2++)
- for(temp_count_4=0;temp_count_4<(((offset_value-org_cacl_value)*ui_1_32_100step)/bdlr_100step);temp_count_4++)
+for ( temp_count_2=0;temp_count_2<4;temp_count_2++)
+ for (temp_count_4=0;temp_count_4<(((offset_value-org_cacl_value)*ui_1_32_100step)/bdlr_100step);temp_count_4++)
{
{
dwc_window_reg_after_training_update_increas_sub(temp_test_index_2
,((over_ride_sub_index/2)*9+
temp_count_2+(over_ride_sub_index%2)*4), 0,1) ;
-
+
}
}
}
- if(over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY)
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY)
{
temp_test_index_2=DMC_TEST_WINDOW_INDEX_RXPBDLY;
- for( temp_count_2=0;temp_count_2<4;temp_count_2++)
+ for ( temp_count_2=0;temp_count_2<4;temp_count_2++)
{
- if(temp_count_2==((over_ride_sub_index%9)%4))
+ if (temp_count_2 == ((over_ride_sub_index%9)%4))
temp_count_2++;
-for(temp_count_4=0;temp_count_4<(offset_value-org_cacl_value);temp_count_4++)
+for (temp_count_4=0;temp_count_4<(offset_value-org_cacl_value);temp_count_4++)
dwc_window_reg_after_training_update_increas_sub(temp_test_index_2
,((over_ride_sub_index/9)*9+
temp_count_2+(((over_ride_sub_index%9)>3)?4:0)), 0,1) ;
}
//bdlr_100step (org_cacl_value<offset_value)
- if((((offset_value-org_cacl_value)*bdlr_100step)/ui_1_32_100step))
+ if ((((offset_value-org_cacl_value)*bdlr_100step)/ui_1_32_100step))
{
temp_test_index_2=DMC_TEST_WINDOW_INDEX_RXCLKDLY;
- for(temp_count_4=0;temp_count_4<(((offset_value-org_cacl_value)*bdlr_100step)/ui_1_32_100step);temp_count_4++)
+ for (temp_count_4=0;temp_count_4<(((offset_value-org_cacl_value)*bdlr_100step)/ui_1_32_100step);temp_count_4++)
dwc_window_reg_after_training_update_increas_sub(temp_test_index_2
,(((over_ride_sub_index/9)<<1)+
(((over_ride_sub_index%9)>3)?1:0)
@@ -34584,7 +33504,7 @@
#define DMC_WINDOW_CMD 20180010 //g12_d2pll 1584 0 0 0 0 0x8
//g12_d2pll 1600 5 0 0x10 1
//g12_d2pll 1600 0 0 0 0 0x10 0 1
- //g12_d2pll 1400 0 0 0 0 0 0 0 0 1 1200 1900 test ddr frequency
+ //g12_d2pll 1400 0 0 0 0 0 0 0 0 1 1200 1900 test ddr frequency
//g12_d2pll 1400 0 0 0 0 0 0 0 0 3 1200 1900 test ddr frequency with EE voltage
//g12_d2pll 1600 0 0 0 0 0 0 0 1 //full test
//g12_d2pll 1600 0 0 0 0 0 0 0 1 0 0 0 872 //full test with 872mv EE
@@ -34641,7 +33561,7 @@
unsigned int window_test_stick_cmd_value=0;
#if 0
unsigned int stick_test_cmd_index=0; // 1 override_cmd 2
- unsigned int stick_test_ddr_window_delay_override_enable=0; // bit 0 ac 1 data dqs write 2 data dqs read 3 data bit write 4 data bit read 5//data write vref 6 //data read vref
+ unsigned int stick_test_ddr_window_delay_override_enable=0; // bit 0 ac 1 data dqs write 2 data dqs read 3 data bit write 4 data bit read 5//data write vref 6 //data read vref
unsigned int stick_test_ddr_window_delay_override_index=0;
unsigned int stick_test_ddr_window_delay_override_value=0;
unsigned int stick_test_ddr_window_delay_override_before_after_training_setting=0; //0 before ,1 after training
@@ -34672,7 +33592,7 @@
}
unsigned int argc_count=1;
unsigned int para_meter[30]={0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0,};
- while(argc_count<argc)
+ while (argc_count<argc)
{para_meter[argc_count-1]= simple_strtoul(argv[argc_count], &endp, 0);
if (*argv[argc_count] == 0 || *endp != 0) {
para_meter[argc_count-1] = 0;
@@ -34775,7 +33695,7 @@
wr_reg(PREG_STICKY_REG0,0 | (0xf13 << 20));
#endif
- if(stick_dmc_ddr_window_test_enable)
+ if (stick_dmc_ddr_window_test_enable)
{
wr_reg(PREG_STICKY_REG0,((stick_dmc_ddr_window_test_enable_spec_sub_index&0xff)<<8)|(stick_dmc_ddr_window_test_enable&0xff) | (0xf12<< 20));
}
@@ -34784,7 +33704,7 @@
wr_reg(PREG_STICKY_REG2,(stick_test_ddr_window_delay_override_value&0xffff) |((stick_test_ddr_window_delay_override_index&0xff)<<16)
|((stick_test_ddr_window_delay_override_enable&0x7)<<29)
|((stick_test_ddr_window_delay_override_before_after_training_setting&0x1)<<28));
- if(stick_dmc_ddr_window_test_enable_mask)
+ if (stick_dmc_ddr_window_test_enable_mask)
{
wr_reg(PREG_STICKY_REG3,(stick_dmc_ddr_window_test_enable_mask));
}
@@ -34792,32 +33712,32 @@
{
wr_reg(PREG_STICKY_REG4,(stick_dmc_ddr_window_test_dmc_full_test_enable<<31)|(stick_dmc_ddr_bl2_sweep_frequency_ee_voltage_enable<<29));
}
- if(stick_dmc_ddr_bl2_sweep_frequency_ee_voltage_enable)
+ if (stick_dmc_ddr_bl2_sweep_frequency_ee_voltage_enable)
{
wr_reg(PREG_STICKY_REG5,(stick_dmc_ddr_bl2_sweep_frequency_min<<0)|(stick_dmc_ddr_bl2_sweep_frequency_max<<16));
}
- if(stick_dmc_ddr_bl2_ee_voltage)
+ if (stick_dmc_ddr_bl2_ee_voltage)
{
wr_reg(PREG_STICKY_REG6,(stick_dmc_ddr_bl2_ee_voltage<<0));
}
-#endif
+#endif
argc_count=2;
window_test_stick_cmd_value=para_meter[argc_count-1];
- if((window_test_stick_cmd_value==G12_D2PLL_CMD_OVER_RIDE)||(window_test_stick_cmd_value==G12_D2PLL_CMD_OVER_RIDE_PLUS_FULLTEST))
+ if ((window_test_stick_cmd_value == G12_D2PLL_CMD_OVER_RIDE) || (window_test_stick_cmd_value == G12_D2PLL_CMD_OVER_RIDE_PLUS_FULLTEST))
{
para_meter[3]=(para_meter[3]<<24)|(para_meter[4]<<16)|(para_meter[5]<<0);
para_meter[4]=(para_meter[6]<<24)|(para_meter[7]<<16)|(para_meter[8]<<0);
para_meter[5]=(para_meter[9]<<24)|(para_meter[10]<<16)|(para_meter[11]<<0);
}
- if((window_test_stick_cmd_value==G12_D2PLL_CMD_WINDOW_TEST)||(window_test_stick_cmd_value==G12_D2PLL_CMD_WINDOW_TEST_AND_STICKY_OVERRIDE))
+ if ((window_test_stick_cmd_value == G12_D2PLL_CMD_WINDOW_TEST) || (window_test_stick_cmd_value == G12_D2PLL_CMD_WINDOW_TEST_AND_STICKY_OVERRIDE))
{
//para_meter[8] size 9 stick_dmc_ddr_window_test_no_use_dqs_dq_correction 10 disable_scramble_use_define_pattern 11 stick_dmc_window_test_loop_flag window loop test
- //12 if reinit when test dq 13 pass_to_fail_flag 14 test_dmc_or_cpu
- para_meter[5]=(para_meter[9]<<28)|(para_meter[10]<<24)|(para_meter[11]<<20)|(para_meter[12]<<21)|(para_meter[13]<<22)|(para_meter[14]<<25)|(para_meter[5]<<0);
+ //12 if reinit when test dq
+ para_meter[5]=(para_meter[9]<<28)|(para_meter[10]<<24)|(para_meter[11]<<20)|(para_meter[12]<<21)|(para_meter[5]<<0);
}
- if((window_test_stick_cmd_value==G12_D2PLL_CMD_DDR_EYE_TEST)||(window_test_stick_cmd_value==G12_D2PLL_CMD_DDR_EYE_TEST_AND_STICKY_OVERRIDE))
+ if ((window_test_stick_cmd_value == G12_D2PLL_CMD_DDR_EYE_TEST) || (window_test_stick_cmd_value == G12_D2PLL_CMD_DDR_EYE_TEST_AND_STICKY_OVERRIDE))
{
para_meter[3]=(para_meter[3]<<0)|(para_meter[4]<<8)|(para_meter[5]<<16)|(para_meter[6]<<24);
@@ -34832,13 +33752,13 @@
printf("P_PREG_STICKY_REG [0x%08x] [0x%08x]==[0x%08x]\n", argc_count,(PREG_STICKY_REG0+(argc_count<<2)),rd_reg(PREG_STICKY_REG0+(argc_count<<2)));
argc_count=1;
//while(argc_count<argc)
- while(argc_count<10)
+ while (argc_count<10)
{
wr_reg(PREG_STICKY_REG0+(argc_count<<2),para_meter[argc_count-1]);
printf("P_PREG_STICKY_REG [0x%08x] [0x%08x]==[0x%08x]\n", argc_count,(PREG_STICKY_REG0+(argc_count<<2)),rd_reg(PREG_STICKY_REG0+(argc_count<<2)));
argc_count++;
}
- /*
+ /*
printf("P_PREG_STICKY_REG0 [0x%08x]\n", rd_reg(PREG_STICKY_REG0));
printf("P_PREG_STICKY_REG1 [0x%08x]\n", rd_reg(PREG_STICKY_REG1));
printf("P_PREG_STICKY_REG2 [0x%08x]\n", rd_reg(PREG_STICKY_REG2));
@@ -34886,7 +33806,7 @@
unsigned int argc_count=1;
unsigned int para_meter[30]={0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0, 0,0,0,0,0,};
- while(argc_count<argc)
+ while (argc_count<argc)
{para_meter[argc_count-1]= simple_strtoul(argv[argc_count], &endp, 0);
if (*argv[argc_count] == 0 || *endp != 0) {
para_meter[argc_count-1] = 0;
@@ -34907,10 +33827,10 @@
test_write_loops=test_write_loops?test_write_loops:DMC_TEST_WRITE_LOOP_DEFAULT;
test_read_loops=test_read_loops?test_read_loops:DMC_TEST_READ_LOOP_DEFAULT;
-while((test_write_loops)||(test_read_loops))
+while ((test_write_loops) || (test_read_loops))
{
-if(test_write_loops)
+if (test_write_loops)
ddr_bist_test_error=dmc_ddr_test(dram_base,1,0,0,test_size,1,0)+ddr_bist_test_error;
@@ -34920,15 +33840,15 @@
#ifdef CFG_ENABLE_DDR_DMC_TEST
-if(test_read_loops)
+if (test_read_loops)
ddr_bist_test_error=dmc_ddr_test(dram_base,0,1,1,test_size,1,0)+ddr_bist_test_error;
serial_puts("\ndmc full test result==");
serial_put_dec(ddr_bist_test_error);
serial_puts("\n");
#endif
-if(test_write_loops)
+if (test_write_loops)
test_write_loops--;
-if(test_read_loops)
+if (test_read_loops)
test_read_loops--;
}
@@ -34942,7 +33862,7 @@
dwc_ddrphy_apb_wr(0xd0000,0x0);
{printf("\n write dq_bit delay * 1/32UI");
- for(t_count=0;t_count<72;t_count++)
+ for (t_count=0;t_count<72;t_count++)
{
add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(0xc0+((t_count%9)<<8)+(t_count/36)));
dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
@@ -35046,7 +33966,7 @@
lane_disable= 0;
}
}
- printf("lane_disable==0x%08x\n",lane_disable);
+ printf("lane_disable==0x%08x\n",lane_disable);
if (argc >5) {
ddr_data_test_size = simple_strtoull_ddr(argv[5], &endp, 0);
@@ -35125,9 +34045,9 @@
ddr_test_data_array_max=8;
- for (temp_count= 0;temp_count < ddr_test_data_array_max; temp_count++)
+ for (temp_count= 0;temp_count < ddr_test_data_array_max; temp_count++)
{
- num_array[temp_count]= read_write_window_test_parameter(data_source,
+ num_array[temp_count]= read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_READ );
printf("read numarry[%d]==%d\n",temp_count,num_array[temp_count]);
}
@@ -35141,7 +34061,7 @@
unsigned int test_arg_5_pass_fail_flag_add_sticky_offset =0; //use for kernel
unsigned int test_arg_6_step_status =0; //uboot test we should read error then done status. 0 no test 1 ongoing 2 this step done fail or pass
- unsigned int test_arg_7_lcdlr_offset =0; //left_lcdlr+right_lcdlr<<16
+ unsigned int test_arg_7_lcdlr_offset =0; //left_lcdlr+right_lcdlr<<16
unsigned int test_arg_7_lcdlr_offset_l =0; //left_lcdlr
unsigned int test_arg_7_lcdlr_offset_r=0; //right_lcdlr
unsigned int delay_step_x100= 0;
@@ -35177,25 +34097,25 @@
- //for (temp_count= 0;temp_count < 8; temp_count++)
+ //for (temp_count= 0;temp_count < 8; temp_count++)
// {
- // read_write_window_test_parameter(data_source,
+ // read_write_window_test_parameter(data_source,
// temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
//}
- if(ddr_test_clear_flag)
+ if (ddr_test_clear_flag)
{ test_arg_6_step_status=0;
num_array[6] = test_arg_6_step_status ;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
printf("\n clear sticky register should reset,then over write ....\n");
run_command("reset",0);
- while(1);
+ while (1) ;
}
- if(test_arg_6_step_status==0)
+ if (test_arg_6_step_status == 0)
{
{
@@ -35218,7 +34138,7 @@
test_arg_5_pass_fail_flag_add_sticky_offset=0;
test_arg_6_step_status=0;
test_arg_7_lcdlr_offset=0;
- if(ddr_test_init_offset)
+ if (ddr_test_init_offset)
{test_arg_7_lcdlr_offset=ddr_test_init_offset;
}
//num_array[0] = reg_def_value_data[0] ;
@@ -35232,9 +34152,9 @@
- for (temp_count= 0;temp_count < 8; temp_count++)
+ for (temp_count= 0;temp_count < 8; temp_count++)
{
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
@@ -35255,7 +34175,7 @@
}
}
- if(ddr_test_uboot_kernel_enable_mask&1)
+ if (ddr_test_uboot_kernel_enable_mask&1)
{printf("skip uboot test should init kernel offset value==0x%08x\n",num_array[7]);
}
@@ -35279,7 +34199,7 @@
printf("test_arg_6_step_status=%d\n",num_array[6]);
printf("test_arg_7_lcdlr_offset=%d\n",num_array[7]);
- if(test_arg_6_step_status==4) //uboot finish
+ if (test_arg_6_step_status == 4) //uboot finish
{
ddr_test_watchdog_disable(); //s
printf("close watchdog\n");
@@ -35302,21 +34222,21 @@
}
- if(ddr_test_uboot_kernel_enable_mask&2)
+ if (ddr_test_uboot_kernel_enable_mask&2)
{
- if(ddr_test_uboot_loop)
+ if (ddr_test_uboot_loop)
{
{ test_arg_6_step_status=0;
num_array[6] = test_arg_6_step_status ;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
printf("\n clear sticky register should reset,then over write ....\n");
run_command("reset",0);
- while(1);
+ while (1) ;
}
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
return 1;
@@ -35327,50 +34247,50 @@
//if((test_arg_6_step_status==0)) //0 test left edge begin 1 test left edge ongoing 2//left_finish 3 right edge ongoing 4 right finish //5 kernel left edge ongoing 6 kernel left finish 7 kernel right ongoing
// uboot find from pass to fail offset 0->max
- //kernel find from fail to pass offset from max ->0
- if((test_arg_6_step_status<4)) //// uboot find from pass to fail offset 0->max
+ //kernel find from fail to pass offset from max ->0
+ if ((test_arg_6_step_status<4)) //// uboot find from pass to fail offset 0->max
{
- if((test_arg_6_step_status==0)||(test_arg_6_step_status==2)
+ if ((test_arg_6_step_status == 0) || (test_arg_6_step_status == 2)
||(test_arg_6_step_status==4)||(test_arg_6_step_status==6)
)
{
test_arg_6_step_status=test_arg_6_step_status+1;
num_array[6] = test_arg_6_step_status ;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
- if((test_arg_6_step_status==1)||(test_arg_6_step_status==3)||(test_arg_6_step_status==5)||(test_arg_6_step_status==7))
+ if ((test_arg_6_step_status == 1) || (test_arg_6_step_status == 3) || (test_arg_6_step_status == 5) || (test_arg_6_step_status == 7))
{
- if(test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_PASS) //pass 2 error 1
+ if (test_arg_5_pass_fail_flag_add_sticky_offset == DDR_TEST_PASS) //pass 2 error 1
{
// test_arg_6_step_status=test_arg_6_step_status+1;
test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_NULL;
num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if((test_arg_6_step_status==1)||(test_arg_6_step_status==5))
+ if ((test_arg_6_step_status == 1) || (test_arg_6_step_status == 5))
{
- // for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
+ // for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
{
lane_step_count=6;
//if((lane_step_count%2)==0)
{
- if((((num_array[lane_step_count/2])>>0)&0xffff)<=test_arg_7_lcdlr_offset_l)
+ if ((((num_array[lane_step_count/2])>>0)&0xffff) <= test_arg_7_lcdlr_offset_l)
{
test_lcdlr_reach_lcdlr_limited_flag=test_lcdlr_reach_lcdlr_limited_flag+1;
}
}
/*
- if((lane_step_count%2)==1)
+ if ((lane_step_count%2) == 1)
{
- if((((num_array[lane_step_count/2])>>16)&0xffff)<=test_arg_7_lcdlr_offset_l)
+ if ((((num_array[lane_step_count/2])>>16)&0xffff) <= test_arg_7_lcdlr_offset_l)
{
test_lcdlr_reach_lcdlr_limited_flag=test_lcdlr_reach_lcdlr_limited_flag+1;
}
@@ -35383,15 +34303,15 @@
}
- if(test_lcdlr_reach_lcdlr_limited_flag)
+ if (test_lcdlr_reach_lcdlr_limited_flag)
{
- test_arg_6_step_status=test_arg_6_step_status+1;
+ test_arg_6_step_status=test_arg_6_step_status+1;
num_array[6] = test_arg_6_step_status ;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
@@ -35400,18 +34320,18 @@
// test_arg_7_lcdlr_offset_l=(test_arg_7_lcdlr_offset&0xffff);
// test_arg_7_lcdlr_offset_r=((test_arg_7_lcdlr_offset>>16)&0xffff);
- if(((test_arg_6_step_status==1))||(test_arg_6_step_status==5))
+ if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
{
test_arg_7_lcdlr_offset_l=test_arg_7_lcdlr_offset_l-1;
}
else if(((test_arg_6_step_status==3))||(test_arg_6_step_status==7))
{
- test_arg_7_lcdlr_offset_r=test_arg_7_lcdlr_offset_r-1;
+ test_arg_7_lcdlr_offset_r=test_arg_7_lcdlr_offset_r-1;
}
test_arg_7_lcdlr_offset=(test_arg_7_lcdlr_offset_l|(test_arg_7_lcdlr_offset_r<<16));
num_array[7] = test_arg_7_lcdlr_offset ;
temp_count=7;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
@@ -35419,16 +34339,16 @@
test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_NULL;
num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- test_arg_6_step_status=test_arg_6_step_status+1;
+ test_arg_6_step_status=test_arg_6_step_status+1;
num_array[6] = test_arg_6_step_status ;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
@@ -35436,24 +34356,24 @@
//(test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_NULL)
// test_arg_7_lcdlr_offset_l=(test_arg_7_lcdlr_offset&0xffff);
// test_arg_7_lcdlr_offset_r=((test_arg_7_lcdlr_offset>>16)&0xffff);
- if(((test_arg_6_step_status==1))||(test_arg_6_step_status==5))
+ if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
{
test_arg_7_lcdlr_offset_l=test_arg_7_lcdlr_offset_l+1;
}
else if(((test_arg_6_step_status==3))||(test_arg_6_step_status==7))
{
- test_arg_7_lcdlr_offset_r=test_arg_7_lcdlr_offset_r+1;
+ test_arg_7_lcdlr_offset_r=test_arg_7_lcdlr_offset_r+1;
}
test_arg_7_lcdlr_offset=(test_arg_7_lcdlr_offset_l|(test_arg_7_lcdlr_offset_r<<16));
num_array[7] = test_arg_7_lcdlr_offset ;
temp_count=7;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL; //pass 2 error 1
num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
ddr_test_watchdog_enable(test_watchdog_time_s); //s
@@ -35463,35 +34383,35 @@
{
- // for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
+ // for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
{
lane_step_count=6;
printf("\n (num_array[%d]) ==%08x \n",lane_step_count/2,(num_array[lane_step_count/2]));
- if(((test_arg_6_step_status==1))||(test_arg_6_step_status==5))
+ if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
{
- if((lane_step_count%2)==0)
+ if ((lane_step_count%2) == 0)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff)-test_arg_7_lcdlr_offset_l;
- if((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
+ if ((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
{test_lcdlr_temp_value=0;
}
}
- if((lane_step_count%2)==1)
+ if ((lane_step_count%2) == 1)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff)-test_arg_7_lcdlr_offset_l;
- if((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
+ if ((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
{test_lcdlr_temp_value=0;
}
}
}
- if(((test_arg_6_step_status==3))||(test_arg_6_step_status==7))
+ if (((test_arg_6_step_status == 3)) || (test_arg_6_step_status == 7))
{
- if((lane_step_count%2)==0)
+ if ((lane_step_count%2) == 0)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff)+test_arg_7_lcdlr_offset_r;
}
- if((lane_step_count%2)==1)
+ if ((lane_step_count%2) == 1)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff)+test_arg_7_lcdlr_offset_r;
@@ -35508,7 +34428,7 @@
printf("\nstr=%s\n",str);
run_command(str,0);
// run_command("reset",0);
- while(1);
+ while (1) ;
}
// do_ddr_g12_read_write_ddr_add_window_lcdlr( rank_index,lane_step_count,
@@ -35521,17 +34441,17 @@
}
//here will dead
- if(test_arg_6_step_status>4)
+ if (test_arg_6_step_status>4)
{
//ddr_test_watchdog_disable(); //s
ddr_test_watchdog_enable(kernel_test_watchdog_time_s); //s
// test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL; //pass 2 error 1
// num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
// temp_count=5;
- // read_write_window_test_parameter(data_source,
+ // read_write_window_test_parameter(data_source,
// temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("run storeboot",0);
- while(1);
+ while (1) ;
} else
{
temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
@@ -35540,7 +34460,7 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
@@ -35550,13 +34470,13 @@
{
//write org value
- for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
{
- if((lane_step_count%2)==0)
+ if ((lane_step_count%2) == 0)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff);
}
- if((lane_step_count%2)==1)
+ if ((lane_step_count%2) == 1)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff);
}
@@ -35572,10 +34492,10 @@
test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_PASS; //pass 2 error 1
num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
- while(1);
+ while (1) ;
@@ -35585,62 +34505,62 @@
}
- if((test_arg_6_step_status==4)||(test_arg_6_step_status==6))
+ if ((test_arg_6_step_status == 4) || (test_arg_6_step_status == 6))
{
test_arg_4_step_flag_add_sticky_offset=DDR_TEST_STATUS_UBOOT_FINISH;
num_array[4] = test_arg_4_step_flag_add_sticky_offset ;
temp_count=4;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL;//DDR_TEST_NULL;
num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
- if((test_arg_6_step_status>=4)) ////kernel find from fail to pass offset from max ->0
+ if ((test_arg_6_step_status >= 4)) ////kernel find from fail to pass offset from max ->0
{
- if((test_arg_6_step_status==0)||(test_arg_6_step_status==2)
+ if ((test_arg_6_step_status == 0) || (test_arg_6_step_status == 2)
||(test_arg_6_step_status==4)||(test_arg_6_step_status==6)
)
{
test_arg_6_step_status=test_arg_6_step_status+1;
num_array[6] = test_arg_6_step_status ;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
- if((test_arg_6_step_status==1)||(test_arg_6_step_status==3)||(test_arg_6_step_status==5)||(test_arg_6_step_status==7))
+ if ((test_arg_6_step_status == 1) || (test_arg_6_step_status == 3) || (test_arg_6_step_status == 5) || (test_arg_6_step_status == 7))
{
- if(test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_PASS) //pass 2 error 1
+ if (test_arg_5_pass_fail_flag_add_sticky_offset == DDR_TEST_PASS) //pass 2 error 1
{
// test_arg_6_step_status=test_arg_6_step_status+1;
test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_NULL;
num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
- if((test_arg_6_step_status==1)||(test_arg_6_step_status==5))
+ if ((test_arg_6_step_status == 1) || (test_arg_6_step_status == 5))
{
- for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
{
- if((lane_step_count%2)==0)
+ if ((lane_step_count%2) == 0)
{
- if((((num_array[lane_step_count/2])>>0)&0xffff)<=test_arg_7_lcdlr_offset_l)
+ if ((((num_array[lane_step_count/2])>>0)&0xffff) <= test_arg_7_lcdlr_offset_l)
{
test_lcdlr_reach_lcdlr_limited_flag=test_lcdlr_reach_lcdlr_limited_flag+1;
}
}
- if((lane_step_count%2)==1)
+ if ((lane_step_count%2) == 1)
{
- if((((num_array[lane_step_count/2])>>16)&0xffff)<=test_arg_7_lcdlr_offset_l)
+ if ((((num_array[lane_step_count/2])>>16)&0xffff) <= test_arg_7_lcdlr_offset_l)
{
test_lcdlr_reach_lcdlr_limited_flag=test_lcdlr_reach_lcdlr_limited_flag+1;
}
@@ -35654,35 +34574,35 @@
}
// if(test_lcdlr_reach_lcdlr_limited_flag)
{
- test_arg_6_step_status=test_arg_6_step_status+1;
+ test_arg_6_step_status=test_arg_6_step_status+1;
num_array[6] = test_arg_6_step_status ;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
- else if((test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_FAIL)
+ else if((test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_FAIL)
//||(test_arg_5_pass_fail_flag_add_sticky_offset==DDR_TEST_NULL))//pass 2 error 1
)
{
// test_arg_7_lcdlr_offset_l=(test_arg_7_lcdlr_offset&0xffff);
// test_arg_7_lcdlr_offset_r=((test_arg_7_lcdlr_offset>>16)&0xffff);
- if(((test_arg_6_step_status==1))||(test_arg_6_step_status==5))
+ if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
{
test_arg_7_lcdlr_offset_l=test_arg_7_lcdlr_offset_l-1;
}
else if(((test_arg_6_step_status==3))||(test_arg_6_step_status==7))
{
- test_arg_7_lcdlr_offset_r=test_arg_7_lcdlr_offset_r-1;
+ test_arg_7_lcdlr_offset_r=test_arg_7_lcdlr_offset_r-1;
}
test_arg_7_lcdlr_offset=(test_arg_7_lcdlr_offset_l|(test_arg_7_lcdlr_offset_r<<16));
num_array[7] = test_arg_7_lcdlr_offset ;
temp_count=7;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
@@ -35691,7 +34611,7 @@
test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL;
num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
@@ -35706,34 +34626,34 @@
{
- for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
{
printf("\n (num_array[%d]) ==%08x \n",lane_step_count/2,(num_array[lane_step_count/2]));
- if(((test_arg_6_step_status==1))||(test_arg_6_step_status==5))
+ if (((test_arg_6_step_status == 1)) || (test_arg_6_step_status == 5))
{
- if((lane_step_count%2)==0)
+ if ((lane_step_count%2) == 0)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff)-test_arg_7_lcdlr_offset_l;
- if((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
+ if ((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
{test_lcdlr_temp_value=0;
}
}
- if((lane_step_count%2)==1)
+ if ((lane_step_count%2) == 1)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff)-test_arg_7_lcdlr_offset_l;
- if((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
+ if ((((num_array[lane_step_count/2])>>0)&0xffff)<test_arg_7_lcdlr_offset_l)
{test_lcdlr_temp_value=0;
}
}
}
- if(((test_arg_6_step_status==3))||(test_arg_6_step_status==7))
+ if (((test_arg_6_step_status == 3)) || (test_arg_6_step_status == 7))
{
- if((lane_step_count%2)==0)
+ if ((lane_step_count%2) == 0)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff)+test_arg_7_lcdlr_offset_r;
}
- if((lane_step_count%2)==1)
+ if ((lane_step_count%2) == 1)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff)+test_arg_7_lcdlr_offset_r;
@@ -35752,17 +34672,17 @@
}
//here will dead
- if(test_arg_6_step_status>4)
+ if (test_arg_6_step_status>4)
{
//ddr_test_watchdog_disable(); //s
ddr_test_watchdog_enable(kernel_test_watchdog_time_s); //s
// test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL; //pass 2 error 1
// num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
// temp_count=5;
- // read_write_window_test_parameter(data_source,
+ // read_write_window_test_parameter(data_source,
// temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("run storeboot",0);
- while(1);
+ while (1) ;
} else
{
temp_test_error=ddr_test_s_cross_talk_pattern(ddr_test_size);
@@ -35771,43 +34691,43 @@
if (temp_test_error)
{
run_command("reset",0);
- while(1);
+ while (1) ;
}
else
{
ddr_test_watchdog_clear();
{
//write org value
- for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
+ for ((lane_step_count=0);(lane_step_count<8);(lane_step_count++))
{
- if((lane_step_count%2)==0)
+ if ((lane_step_count%2) == 0)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>0)&0xffff);
}
- if((lane_step_count%2)==1)
+ if ((lane_step_count%2) == 1)
{
test_lcdlr_temp_value=(((num_array[lane_step_count/2])>>16)&0xffff);
}
do_ddr_g12_read_write_ddr_add_window_lcdlr( rank_index,lane_step_count,
(test_lcdlr_temp_value),DDR_PARAMETER_WRITE);
- }
+ }
}
test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_PASS; //pass 2 error 1
num_array[5] = test_arg_5_pass_fail_flag_add_sticky_offset ;
temp_count=5;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
run_command("reset",0);
- while(1);
+ while (1) ;
}
}
}
}
- if(test_arg_6_step_status>=8) //finish
+ if (test_arg_6_step_status >= 8) //finish
{
ddr_test_watchdog_disable(); //s
printf("close watchdog\n");
@@ -35829,7 +34749,7 @@
test_arg_4_step_flag_add_sticky_offset=DDR_TEST_STATUS_KERNEL_FINISH;
num_array[4] = test_arg_4_step_flag_add_sticky_offset ;
temp_count=4;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
}
@@ -35839,16 +34759,16 @@
// test_arg_6_step_status=test_arg_6_step_status+1;
num_array[6] = test_arg_6_step_status ;
temp_count=6;
- read_write_window_test_parameter(data_source,
+ read_write_window_test_parameter(data_source,
temp_count ,num_array[temp_count],DDR_PARAMETER_WRITE);
}
ddr_test_watchdog_disable(); //s
// test_arg_5_pass_fail_flag_add_sticky_offset=DDR_TEST_FAIL; //pass 2 error 1
run_command("run storeboot",0);
- while(1);
+ while (1) ;
return 1;
}
-#endif
+#endif
#if ( CONFIG_DDR_PHY >= P_DDR_PHY_G12)
int do_ddr_g12_override_data(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -35932,7 +34852,7 @@
}
- else {
+ else {
return 1;
}
printf("lcdlr_max %d,\n",lcdlr_max);
@@ -36069,13 +34989,13 @@
}
- else {
+ else {
return 1;
}
printf("lcdlr_max %d,\n",lcdlr_max);
- if(left_right_flag==DDR_PARAMETER_RIGHT)
+ if (left_right_flag == DDR_PARAMETER_RIGHT)
printf("offset right ++ left_right_flag %d,\n",left_right_flag);
- if(left_right_flag==DDR_PARAMETER_LEFT)
+ if (left_right_flag == DDR_PARAMETER_LEFT)
printf("offset left --left_right_flag %d,\n",left_right_flag);
if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
@@ -36127,15 +35047,15 @@
}
}
- // for (count1=0;count1<offset_value;count1++)
+ // for (count1=0;count1<offset_value;count1++)
{
- if(left_right_flag==DDR_PARAMETER_RIGHT)
+ if (left_right_flag == DDR_PARAMETER_RIGHT)
{
dwc_window_reg_after_training_update_increas(test_index,
count,
0,offset_value);
}
- if(left_right_flag==DDR_PARAMETER_LEFT)
+ if (left_right_flag == DDR_PARAMETER_LEFT)
{
dwc_window_reg_after_training_update_increas(test_index,
count,
@@ -36159,19 +35079,17 @@
#endif
-#if 0
+#if 0
U_BOOT_CMD(
ddr_g12_offset_data_lcdlr, 10, 1, do_ddr_g12_offset_data_lcdlr,
"ddr_g12_offset_data_lcdlr 0 1 2 2 3",
"ddr_g12_offset_data_lcdlr rank_index dq_index write_read left/right offset_value \n"
);
#endif
-char CMD_VER[] = "Ver_10";
int do_ddr_test_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
//ddr_test_watchdog_init(4000);
//printf("\nopen watchdog %dms\n",4000);
- printf("\n ddr test cmd version== %s\n", CMD_VER);
printf("\nargc== 0x%08x\n", argc);
int i ;
for (i = 0;i<argc;i++)
@@ -36295,7 +35213,7 @@
{
run_command("dcache off",0);
run_command("dcache on",0);
- printf("\n cache off on");
+ printf("\n cache off on");
switch (ddr_test_cmd)
{case(DDR_TEST_CMD__NONE):
{
@@ -36324,28 +35242,28 @@
printf("\n 0x16 test ee mdlr ddr_test_cmd 0x16 voltage pwm_id loops ");
printf("\n 0x17 d2pll ddr_test_cmd 0x17 clk zq_ac zq_soc_dram soc_vref dram_vref dec_hex zq_vref 0\n \
example ddr_test_cmd 0x17 1200 0x2aa4a 0x2015995d 50 81 1 50 \n \
- or ddr_test_cmd 0x17 1200 0x2aa4a 0x2015995d 0x09 0x20 0 50 \n");
+ or ddr_test_cmd 0x17 1200 0x2aa4a 0x2015995d 0x09 0x20 0 50 \n");
printf("or ddr_test_cmd 0x17 1200 6034 60346034 0 0 0 0 1 \n");
printf("\n 0x18 test data_lane_setup_hold ddr_test_cmd 0x18 a 0 size range start_pin_id end_pin_id ddr_test_cmd 0x18 a 0 0x80000 1 0 96 ");
printf("\n 0x19 test phy vref ddr_test_cmd 0x19 a 0 0x80000 1 seed step vref_all vref_lcdlr_offset test_down_up_step seed_hex_dec \
ddr_test_cmd 0x19 a 0 0x1000000 1 63 1 1 0x8 0 1 ");
printf("\n 0x1a test dram vref ddr_test_cmd 0x1A a 0 0x80000 clear seed step vref_all vref_lcdlr_offset test_down_up_step vref_range seed_hex_dec \
- \n setenv ddr_test_ddr4ram_vref ddr_test_cmd 0x1A a 0 0x0800000 0 0x14 1 0 0x8 0 0 0 ; setenv storeboot run ddr_test_ddr4ram_vref ;save;reset ");
+ \n env_set ddr_test_ddr4ram_vref ddr_test_cmd 0x1A a 0 0x0800000 0 0x14 1 0 0x8 0 0 0 ; env_set storeboot run ddr_test_ddr4ram_vref ;save;reset ");
printf("\n 0x1b test ac vref ddr_test_cmd 0x1B a 0 0x80000 clear seed step vref_all vref_lcdlr_offset seed_hex_dec");
printf("\n 0x1c sweep dram clk use d2pll_env ddr_test_cmd 0x1c test_size start_freq end_freq test_loops ddr_test_cmd 0x1c 0x8000000 800 1500 1");
printf("\n 0x1d test shift clk ddr_test_cmd 0x1d type delay_ms times");
printf("\n 0x1e test write_read ddr_test_cmd 0x1e write_read pattern_id loop start_add test_size");
printf("\n 0x1f test pwm_cmd ddr_test_cmd 0x1f pwmid pwm_low pwm_high");
printf("\n 0x22 test ddr_window use env ddr_test_cmd 0x22 a 0 test_size watchdog_time \
- lane_disable_masrk add_test_size setenv bootcmd ddr_test_cmd 0x22 a 0 0x800000 15 0 0x8000000");
- printf("\n defenv;save;setenv bootcmd ddr_test_cmd 0x22 a 0 0x800000 18 0x0 0x8000000");
- printf("\n setenv env_ddrtest_data_lane 0x22;save;reset");
+ lane_disable_masrk add_test_size env_set bootcmd ddr_test_cmd 0x22 a 0 0x800000 15 0 0x8000000");
+ printf("\n defenv;save;env_set bootcmd ddr_test_cmd 0x22 a 0 0x800000 18 0x0 0x8000000");
+ printf("\n env_set env_ddrtest_data_lane 0x22;save;reset");
printf("\n 0x23 test shift ddr frequency ddr_test_cmd 0x23");
printf("\n 0x24 display ddr_information ddr_test_cmd 0x24");
printf("\n 0x25 offset ddr_lcdlr ddr_test_cmd 0x25");
printf("\n 0x26 set watchdog_value ddr_test_cmd 0x26 30");
printf("\n 0x27 test ddr_window use sticky register ddr_test_cmd 0x27 a 0 test_size watchdog_time \
- lane_disable_masrk add_test_size setenv bootcmd ddr_test_cmd 0x27 a 0 0x800000 15 0 0x8000000");
+ lane_disable_masrk add_test_size env_set bootcmd ddr_test_cmd 0x27 a 0 0x800000 15 0 0x8000000");
printf("\n 0x28 sweep dram clk use d2pll_sticky ddr_test_cmd 0x28 test_size start_freq end_freq test_loops ddr_test_cmd 0x28 0x8000000 800 1500 1");
/*
@@ -36355,31 +35273,31 @@
ddr_tune_aclcdlr_step a 0 0x8000000 1 2 lane0-1 min
ddr_tune_aclcdlr_step a 0 0x8000000 1 1 lane0-1 max
- setenv bootcmd "ddr_test_cmd 0x22 a 0 0x800000 18 0 0x8000000" watchdog_time £¬lane_disable_mask,add_test_size
- setenv env_ddrtest_data_lane 0x22 ÉèÖÃÃüÁʼ±êÖ¾
- save watchdog_time £¬lane_disable_mask,add_test_size
- d2pll 1200
+ env_set bootcmd "ddr_test_cmd 0x22 a 0 0x800000 18 0 0x8000000" watchdog_time £¬lane_disable_mask,add_test_size
+ env_set env_ddrtest_data_lane 0x22 ÉèÖÃÃüÁʼ±êÖ¾
+ save watchdog_time £¬lane_disable_mask,add_test_size
+ d2pll 1200
- setenv ddr_soc_iovref_test_ddr_clk "0x0000000";
- setenv ddr_soc_iovref_lef "0x0000000";
- setenv ddr_soc_iovref_org "0x0";
- setenv ddr_soc_iovref_rig "0x000000 ";
- save
- d2pll 1104
- ddr_test_cmd 0x19 a 0 0x80000 1 70 1 1 0x8 0 1
+ env_set ddr_soc_iovref_test_ddr_clk "0x0000000";
+ env_set ddr_soc_iovref_lef "0x0000000";
+ env_set ddr_soc_iovref_org "0x0";
+ env_set ddr_soc_iovref_rig "0x000000 ";
+ save
+ d2pll 1104
+ ddr_test_cmd 0x19 a 0 0x80000 1 70 1 1 0x8 0 1
- ÖزâÒªµôµç£¬Êý¾Ý´æÔÚstick ¼Ä´æÆ÷ÁË
- setenv ddr_dram_iovref_test_ddr_clk "0x0000000";
- setenv ddr_dram_iovref_lef "0x0000000";
- setenv ddr_dram_iovref_org "0x0";
- setenv ddr_dram_iovref_rig "0x000000 ";
- setenv ddr_test_ddr4ram_vref "ddr_test_cmd 0x1A a 0 0x080000 0 70 0 0 0x08 0 0 1"
- setenv bootcmd "run ddr_test_ddr4ram_vref"
- save
- µôµçÉϵç
- d2pll 1104
+ ÖزâÒªµôµç£¬Êý¾Ý´æÔÚstick ¼Ä´æÆ÷ÁË
+ env_set ddr_dram_iovref_test_ddr_clk "0x0000000";
+ env_set ddr_dram_iovref_lef "0x0000000";
+ env_set ddr_dram_iovref_org "0x0";
+ env_set ddr_dram_iovref_rig "0x000000 ";
+ env_set ddr_test_ddr4ram_vref "ddr_test_cmd 0x1A a 0 0x080000 0 70 0 0 0x08 0 0 1"
+ env_set bootcmd "run ddr_test_ddr4ram_vref"
+ save
+ µôµçÉϵç
+ d2pll 1104
*/
@@ -36566,8 +35484,8 @@
{
// run_command("ddr_test_cmd 0x1A a 0 0x80000 clear seed step vref_all vref_lcdlr_offset test_down_up_step vref_range seed_hex_dec",0);
//ddr_test_cmd 0x1A a 0 0x1000000 0 0 3 0 0x10
- //setenv ddr_test_ddr4ram_vref "ddr_test_cmd 0x1A a 0 0x0800000 0 0x14 0 0 0x8 0 0 0"
- //setenv storeboot "run ddr_test_ddr4ram_vref"
+ //env_set ddr_test_ddr4ram_vref "ddr_test_cmd 0x1A a 0 0x0800000 0 0x14 0 0 0x8 0 0 0"
+ //env_set storeboot "run ddr_test_ddr4ram_vref"
printf("\ntest ddr4 DRAM vref \n");
do_ddr4_test_dram_vref((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
@@ -36668,7 +35586,7 @@
case(DDR_TEST_CMD__DDR4_SWEEP_DRAM_CLK_USE_D2PLL_STICKY):
{
- // run_command("ddr_test_cmd 0x28
+ // run_command("ddr_test_cmd 0x28
printf("\ntest ddr frequency use sticky register\n");
do_ddr4_test_dram_clk_use_sticky((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
@@ -36676,7 +35594,7 @@
break;
case(DDR_TEST_CMD__DDR4_DDR_BIST_TEST_USE_D2PLL_STICKY):
{
- // run_command("ddr_test_cmd 0x29
+ // run_command("ddr_test_cmd 0x29
printf("\ntest ddr bist test use sticky register\n");
do_ddr4_test_bist_test_use_sticky((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
@@ -36734,7 +35652,7 @@
#endif
case(DDR_TEST_CMD__DDR_TUNE_DDR_DATA_WINDOW_STICKY):
{
- // run_command("ddr_test_cmd 0x27
+ // run_command("ddr_test_cmd 0x27
printf("\ntest dqs window use sticky register\n");
do_ddr_test_dqs_window_sticky((cmd_tbl_t * )cmdtp, (int) flag,( int) argc2, (argv2));
@@ -36808,7 +35726,7 @@
printf("\nargc== 0x%08x\n", argc);
printf("\nargc== 0x%08x\n", argc);
int i ;
- for (i = 0;i<argc;i++)
+ for (i = 0;i<argc;i++)
{
printf("\nargv[%d]=%s\n",i,argv[i]);
}
@@ -36825,7 +35743,7 @@
//num_arry = (uint16_t *)(uint64_t )(sticky_reg_base_add);
for (i = 0; i < 32; i++) {
num_arry[i]=ddr_rd_8_16bit_on_32reg(temp_reg_add,8,i);
- if((i==0)||(i==16)){
+ if ((i == 0) || (i == 16)) {
printf("\n numarry[%d]" ,i);
}
printf(" %d ",num_arry[i]);
@@ -36853,9 +35771,9 @@
test_index_enable=((num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX])|((num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX+1])<<8));
all_toghter_enable=(num_arry[TEST_ARG_3_ALL_TOGHTER]);
switch (ddr_test_cmd)
- {
+ {
case(DMC_STICKY_UBOOT_WINDOW_MAGIC_1):
- if(num_arry[1]==DMC_STICKY_UBOOT_WINDOW_MAGIC_1)
+ if (num_arry[1] == DMC_STICKY_UBOOT_WINDOW_MAGIC_1)
{
//argc2=10;
sprintf(str,"ddr_test_cmd 0x27 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x \
@@ -36882,7 +35800,7 @@
"ddr_test_cmd cmd arg1 arg2 arg3...",
"ddr_test_cmd cmd arg1 arg2 arg3... \n dcache off ? \n"
);
-
+
int do_ddr_auto_scan_drv(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
// ddr_type 2 lpddr4 rank_config
@@ -36896,7 +35814,7 @@
char *string_print_flag= " window-loop \n";
global_boot_times=rd_reg(PREG_STICKY_G12A_REG0);
-
+
printf("\nargc== 0x%08x\n", argc);
printf("\nargc== 0x%08x\n", argc);
int i ;
@@ -36963,7 +35881,7 @@
i=52/2;
ddr_frequency=ddr_rd_8_16bit_on_32reg(temp_reg_add,16,i);
//ddr_frequency=global_ddr_clk;
- if(global_boot_times==1)
+ if (global_boot_times == 1)
{
printf("\norg_global_boot_times== %d %s", global_boot_times,string_print_flag);
//printf("\nmax_counter=%d %d %s",max_counter_total,max_counter_total*2,string_print_flag);
@@ -36975,7 +35893,7 @@
printf("\ndram_data_odt_ohm=%d %s",dram_data_odt_ohm,string_print_flag);
printf("\ndram_data_wr_odt_ohm=%d %s",dram_data_wr_odt_ohm,string_print_flag);
}
- unsigned int soc_data_drv_ohm_p_t[]={34,40,48,60};
+ unsigned int soc_data_drv_ohm_p_t[]={34,40,48,60};
// unsigned int soc_data_drv_ohm_n_t[]={34,40,48,60};
unsigned int dram_data_odt_ohm_t_ddr3[]={40,60,120}; //ddr3
@@ -36986,7 +35904,7 @@
unsigned int dram_data_drv_ohm_t_ddr4[]={34,48}; //ddr4
unsigned int dram_data_drv_ohm_t_lpddr4[]={40,48,60}; //lpddr4
- unsigned int soc_data_odt_ohm_p_t[]={40,48,60,80,120};
+ unsigned int soc_data_odt_ohm_p_t[]={40,48,60,80,120};
unsigned int soc_data_odt_ohm_n_t[]={40,48,60,80,120};
unsigned int dram_data_wr_odt_ohm_t_ddr3[]={60,120,0}; //ddr3
@@ -37017,12 +35935,12 @@
unsigned int max_counter_loop_r1=(sizeof(dram_data_drv_ohm_t_ddr3))/(sizeof(dram_data_drv_ohm_t_ddr3[0]));
unsigned int max_counter_loop_r2=(sizeof(soc_data_odt_ohm_p_t))/(sizeof(soc_data_odt_ohm_p_t[0]));
unsigned int max_counter_loop_wr1=1;
- if(ddr_channel_rank_config)
+ if (ddr_channel_rank_config)
{
max_counter_loop_wr1=(sizeof(dram_data_wr_odt_ohm_t_ddr3))/(sizeof(dram_data_wr_odt_ohm_t_ddr3[0]));
}
- //ddr_channel_rank_configCONFIG_DDR0_32BIT_RANK01_CH0
- if(ddr_type==AUTO_SCAN_DDR4)
+ //ddr_channel_rank_configCONFIG_DDR0_32BIT_RANK01_CH0
+ if (ddr_type == AUTO_SCAN_DDR4)
{
p_dram_data_drv_ohm=dram_data_drv_ohm_t_ddr4;
p_dram_data_odt_ohm=dram_data_odt_ohm_t_ddr4;
@@ -37030,12 +35948,12 @@
max_counter_loop_w2=(sizeof(dram_data_odt_ohm_t_ddr4))/(sizeof(dram_data_odt_ohm_t_ddr4[0]));
max_counter_loop_r1=(sizeof(dram_data_drv_ohm_t_ddr4))/(sizeof(dram_data_drv_ohm_t_ddr4[0]));
- if(ddr_channel_rank_config)
+ if (ddr_channel_rank_config)
{
max_counter_loop_wr1=(sizeof(dram_data_wr_odt_ohm_t_ddr4))/(sizeof(dram_data_wr_odt_ohm_t_ddr4[0]));
}
}
- if(ddr_type==AUTO_SCAN_LPDDR4)
+ if (ddr_type == AUTO_SCAN_LPDDR4)
{
p_dram_data_drv_ohm=dram_data_drv_ohm_t_lpddr4;
p_dram_data_odt_ohm=dram_data_odt_ohm_t_lpddr4;
@@ -37045,17 +35963,17 @@
max_counter_loop_r2=(sizeof(soc_data_odt_ohm_n_t))/(sizeof(soc_data_odt_ohm_n_t[0]));
// unsigned int *p_dram_data_wr_odt_ohm=dram_data_wr_odt_ohm_t_lpddr4;
- if(ddr_channel_rank_config)
+ if (ddr_channel_rank_config)
{
max_counter_loop_wr1=1;
}
}
unsigned int max_counter_total=(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2)*max_counter_loop_wr1;
- //add 2 times recover
+ //add 2 times recover
/*
switch (global_boot_times)
- {
+ {
case(1):
{
break;
@@ -37065,11 +35983,11 @@
//each arrary test 2 times ,for maybe 1times will fail,then next time will recovery //jiaxing 20181114
counter_loop=(((global_boot_times-1)/2)%max_counter_total);
dram_data_wr_odt_ohm=0;
- if(max_counter_loop_wr1>1)
+ if (max_counter_loop_wr1>1)
{
dram_data_wr_odt_ohm=p_dram_data_wr_odt_ohm[(counter_loop/(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2))];
}
- if((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2))<(max_counter_loop_w1*max_counter_loop_w2))
+ if ((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2))<(max_counter_loop_w1*max_counter_loop_w2))
{
soc_data_drv_ohm_p=p_soc_data_drv_ohm_p[(((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2)))%max_counter_loop_w1)];
soc_data_drv_ohm_n=soc_data_drv_ohm_p;
@@ -37087,7 +36005,7 @@
dram_data_drv_ohm=p_dram_data_drv_ohm[((((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2)))-(max_counter_loop_w1*max_counter_loop_w2+1))%max_counter_loop_r1)];
soc_data_odt_ohm_p=p_soc_data_odt_ohm_p[((((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2)))-(max_counter_loop_w1*max_counter_loop_w2+1))/max_counter_loop_r1)];
soc_data_odt_ohm_n=0;
- if(ddr_type==CONFIG_DDR_TYPE_LPDDR4)
+ if (ddr_type == CONFIG_DDR_TYPE_LPDDR4)
{
soc_data_odt_ohm_p=0;
soc_data_odt_ohm_n=p_soc_data_odt_ohm_n[((((counter_loop%(max_counter_loop_w1*max_counter_loop_w2+max_counter_loop_r1*max_counter_loop_r2+2)))-(max_counter_loop_w1*max_counter_loop_w2+1))/max_counter_loop_r1)];
@@ -37098,9 +36016,9 @@
ddr_test_watchdog_reset_system();
}
printf("\nglobal_boot_times== %d %s", global_boot_times,string_print_flag);
- if(loop)
+ if (loop)
{
- if(((global_boot_times-1)/2)>max_counter_total)
+ if (((global_boot_times-1)/2)>max_counter_total)
return 1;
}
printf("\nmax_counter=%d %d %s",max_counter_total,max_counter_total*2,string_print_flag);
@@ -37112,42 +36030,42 @@
printf("\ndram_data_odt_ohm=%d %s",dram_data_odt_ohm,string_print_flag);
printf("\ndram_data_wr_odt_ohm=%d %s",dram_data_wr_odt_ohm,string_print_flag);
{
- if(soc_data_drv_ohm_p)
+ if (soc_data_drv_ohm_p)
{
sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 74 %d 2 0 ",
soc_data_drv_ohm_p);
printf("\nstr=%s\n",str);
run_command(str,0);
}
- if(soc_data_drv_ohm_n)
+ if (soc_data_drv_ohm_n)
{
sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 76 %d 2 0 ",
soc_data_drv_ohm_n);
printf("\nstr=%s\n",str);
run_command(str,0);
}
- if(soc_data_odt_ohm_p)
+ if (soc_data_odt_ohm_p)
{
sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 78 %d 2 0 ",
soc_data_odt_ohm_p);
printf("\nstr=%s\n",str);
run_command(str,0);
}
- if(soc_data_odt_ohm_n)
+ if (soc_data_odt_ohm_n)
{
sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 80 %d 2 0 ",
soc_data_odt_ohm_n);
printf("\nstr=%s\n",str);
run_command(str,0);
}
- if(dram_data_drv_ohm)
+ if (dram_data_drv_ohm)
{
sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 82 %d 2 0 ",
dram_data_drv_ohm);
printf("\nstr=%s\n",str);
run_command(str,0);
}
- if(dram_data_odt_ohm)
+ if (dram_data_odt_ohm)
{
sprintf(str,"ddr_test_cmd 0x36 0x20180030 0x1 84 %d 2 0 ",
dram_data_odt_ohm);
@@ -37169,387 +36087,8 @@
return 1;
}
-
-int do_ddr_auto_fastboot_check(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-#define DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT (1<<5)
-#define AUTO_WINDOW_TEST_ENABLE_ITEM ((1<<1)|(1<<2))
-// int i=0;
-// int count=0;
- char *endp;
- //unsigned int enable_ddr_fast_boot=0; // 0 pause 1,resume
- char auto_window_test_enable_item=DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT;
- uint32_t auto_window_test_dq_size=0;
- char pattern_dis_scramble=0;
- if (argc>1)
- {
- auto_window_test_enable_item = simple_strtoull_ddr(argv[1], &endp, 0);
- if (*argv[1] == 0 || *endp != 0)
- auto_window_test_enable_item=DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT;
- }
- if (argc>2)
- {
- auto_window_test_dq_size = simple_strtoull_ddr(argv[2], &endp, 0);
- if (*argv[2] == 0 || *endp != 0)
- auto_window_test_dq_size=0;
- }
- if (argc>3)
- {
- pattern_dis_scramble = simple_strtoull_ddr(argv[3], &endp, 0);
- if (*argv[3] == 0 || *endp != 0)
- pattern_dis_scramble=0;
- }
- char str[1024]="";
- ddr_set_t *ddr_set_t_p=NULL;
- ddr_set_t_p=(ddr_set_t *)(ddr_set_t_p_arrary);
- //ddr_set_t_p= (ddr_set_t *)G12_DMC_STICKY_0;
- //if (sizeof(ddr_set_t)<loop_max)
- uint32_t ddr_set_add=0;
- uint32_t ddr_set_size=0;
- ddr_set_add=(uint32_t)(uint64_t)(ddr_set_t_p);
- ddr_set_size=sizeof(ddr_set_t);
- printf("\nddr_set_t_p==0x%08x\n",ddr_set_add);
- uint32_t loop=0;
- uint32_t loop_max = (4+(0x3f<<2));//((DMC_STICKY_63-DMC_STICKY_0));
- // loop_max=sizeof(ddr_set_t);
- for (loop = 0; loop <loop_max; loop+=4) {
- wr_reg(((uint64_t)(ddr_set_t_p) + loop), rd_reg(G12_DMC_STICKY_0 + loop));
- }
-
-
- // if((ddr_set_t_p->slt_test_function[0])&DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT)
- // if((ddr_set_t_p->fast_boot[0])>=0xfe)
- if((ddr_set_t_p->fast_boot[0]))
- {
- printf("\nuboot enable auto fast boot funciton \n");
- }
-else
- return 1 ;
-
- if((ddr_set_t_p->fast_boot[0])==0xff)
- { printf("\nuboot auto fast boot auto window test is done \n");
- return 1 ;
- }
-
-printf("\n(ddr_set_t_p->fast_boot[0])==0x%08x\n",(ddr_set_t_p->fast_boot[0]));
-{
- uint16_t dq_bit_delay[72];
- unsigned char t_count=0;
- uint16_t delay_org=0;
- uint16_t delay_temp=0;
- uint32_t add_offset=0;
- dwc_ddrphy_apb_wr(0xd0000,0x0);
-
- {
-
-
-
- // printf("\n ARdPtrInitVal");
- add_offset=((0<<20)|(0<<16)|(0<<12)|(0x2e));
- delay_org=dwc_ddrphy_apb_rd(add_offset);
- ddr_set_t_p->ARdPtrInitVal=delay_org;
- // printf("\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
-
- // printf("\n dfimrl0 dfimrl1 dfimrl2 dfimrl3 HwtMRL");
- add_offset=((0<<20)|(1<<16)|(0<<12)|(0x20));
- delay_org=dwc_ddrphy_apb_rd(add_offset);
- ddr_set_t_p->dfi_mrl=delay_org;
- // printf("\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
- add_offset=((0<<20)|(1<<16)|(1<<12)|(0x20));
- delay_org=dwc_ddrphy_apb_rd(add_offset);
- // printf("\n t_count: %04d %04d %08x %08x",1,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
- add_offset=((0<<20)|(1<<16)|(2<<12)|(0x20));
- delay_org=dwc_ddrphy_apb_rd(add_offset);
- // printf("\n t_count: %04d %04d %08x %08x",2,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
- add_offset=((0<<20)|(1<<16)|(3<<12)|(0x20));
- delay_org=dwc_ddrphy_apb_rd(add_offset);
- // printf("\n t_count: %04d %04d %08x %08x",3,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
- add_offset=((0<<20)|(2<<16)|(0<<12)|(0x20));
- delay_org=dwc_ddrphy_apb_rd(add_offset);
-
- ddr_set_t_p->dfi_hwtmrl=delay_org;
- // printf("\n t_count: %04d %04d %08x %08x",0,delay_org,((((add_offset) << 1)+0xfe000000)),delay_org);
- }
- {
- // printf("\n count_index delay_value register_add register_value \n ");
- // printf("\n address delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6 is coarse --step==1UI",ui_1_32_100step);
- for(t_count=0;t_count<10;t_count++)
- {
- add_offset=((0<<20)|(0<<16)|(t_count<<12)|(0x80));
- dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
- delay_org=dq_bit_delay[t_count];
- delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
- ddr_set_t_p->ac_trace_delay[t_count]=delay_temp;
- // printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
- }
- }
- {
- // printf("\n tdqs delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6-9 is coarse --step==1UI",ui_1_32_100step);
- for(t_count=0;t_count<16;t_count++)
- {
- add_offset=((0<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0xd0+(t_count/8)+((t_count%2)<<8)));
- dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
- delay_org=dq_bit_delay[t_count];
- delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
-
- ddr_set_t_p->write_dqs_delay[t_count]=delay_temp;
-
- // printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
- }
- }
- {
- // printf("\n rxdqs delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI,no coarse",ui_1_32_100step);
- for(t_count=0;t_count<16;t_count++)
- {
- add_offset=((0<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0x8c+(t_count/8)+((t_count%2)<<8)));
- dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
- delay_org=dq_bit_delay[t_count];
- delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
- ddr_set_t_p->read_dqs_delay[t_count]=delay_temp;
- // printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
- }
- }
- {
- // printf("\n write dq_bit delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6-8 is coarse --step==1U",ui_1_32_100step);
- for(t_count=0;t_count<72;t_count++)
- {
- add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(0xc0+((t_count%9)<<8)+(t_count/36)));
- dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
- delay_org=dq_bit_delay[t_count];
- delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
-
- ddr_set_t_p->write_dq_bit_delay[t_count]=delay_temp;
-
-
- // printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
- }
- }
- {
- // printf("\n read dq_bit delay * BDLRx100==%d ps bit0-4 fine tune --step==bdlr step size about 5ps,no coarse",bdlr_100step);
- for(t_count=0;t_count<72;t_count++)
- {
- add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(0x68+((t_count%9)<<8)+(t_count/36)));
- dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
- delay_org=dq_bit_delay[t_count];
- delay_temp=((delay_org&0x3f));
-
- ddr_set_t_p->read_dq_bit_delay[t_count]=delay_temp;
- // printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
- }
- }
- {
- // printf("\n read dqs gate delay * 1/32UIx100==%d ps bit0-4 fine tune ,bit 6-10 is coarse",ui_1_32_100step);
- for(t_count=0;t_count<16;t_count++)
- {
- add_offset=((0<<20)|(1<<16)|(((t_count%8)>>1)<<12)|(0x80+(t_count/8)+((t_count%2)<<8)));
- dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
- delay_org=dq_bit_delay[t_count];
- delay_temp=(32*(((delay_org>>6)&0xf)+((delay_org>>5)&1))+(delay_org&0x1f));
-
- ddr_set_t_p->read_dqs_gate_delay[t_count]=delay_temp;
-
-
- // printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
- }
-
- // printf("\n soc vref : lpddr4-- VREF = VDDQ*(0.047 + VrefDAC0[6:0]*0.00367 DDR4 --VREF = VDDQ*(0.510 + VrefDAC0[6:0]*0.00345");
- //((0<<20)|(1<<16)|(((over_ride_sub_index%36)/9)<<12)|(((over_ride_sub_index%36)%9)<<8)|(0x40),over_ride_value)
- uint32_t vref_t_count=0;
- for(t_count=0;t_count<72;t_count++)
- {
- add_offset=((0<<20)|(1<<16)|(((t_count%36)/9)<<12)|(((t_count%36)%9)<<8)|(0x40));
- dq_bit_delay[t_count]=dwc_ddrphy_apb_rd(add_offset);
- delay_org=dq_bit_delay[t_count];
- delay_temp=((delay_org));
-
-if(t_count<35)
-{
- vref_t_count=((((t_count%36)/9)*8)+(t_count%9));
-
- ddr_set_t_p->soc_bit_vref[vref_t_count]=delay_temp;
-}
-
-
- // printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
- }
-
-
-
-// printf("\n dram vref : lpddr4-- VREF = VDDQ*(0. + VrefDAC0[6:0]*0. DDR4 --VREF = VDDQ*(0. + VrefDAC0[6:0]*0.");
- add_offset=((0<<20)|(1<<16)|(0<<12)|(0x082));
-delay_temp=dwc_ddrphy_apb_rd(add_offset);
- for(t_count=0;t_count<32;t_count++)
- {
-
-
- ddr_set_t_p->dram_bit_vref[t_count]=delay_temp;
-
-
-
- // printf("\n t_count: %04d %04d %08x %08x",t_count,delay_temp,((((add_offset) << 1)+0xfe000000)),dq_bit_delay[t_count]);
- }
- // printf("\n t_count: %04d %04d %08x %08x",0,delay_temp,((((add_offset) << 1)+0xfe000000)),delay_temp);
- }
- for(t_count=0;t_count<4;t_count++)
- {//p_dev->p_ddrs->tdqs2dq=lpddr4_tdqs2dq;
- //ddr_set_t_p->retraining[0]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(0<<12)|(0xaa)); //PptCtlStatic
- //ddr_set_t_p->retraining[1]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(0<<12)|(0xae)); //PptDqsCntInvTrnTg0 ps0 rank0
- //ddr_set_t_p->retraining[2]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(0<<12)|(0xaf)); //PptDqsCntInvTrnTg0 ps0 rank1
- ddr_set_t_p->retraining[4*t_count+0]=(dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xaa)))&0xff; //PptCtlStatic
- ddr_set_t_p->retraining[4*t_count+1]=(dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xaa)))>>8; //PptCtlStatic
- ddr_set_t_p->retraining[4*t_count+2]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xae)); //PptDqsCntInvTrnTg0 ps0 rank0 lane 0-3
- ddr_set_t_p->retraining[4*t_count+3]=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(t_count<<12)|(0xaf)); //PptDqsCntInvTrnTg0 ps0 rank1 lane 0-3
- }
-}
-
-
-
-
- if((ddr_set_t_p->fast_boot[0])<0xfe)
- {
- printf("\nuboot auto fast boot auto window test begin \n");
- {
- ddr_set_t_p->fast_boot[0]=0xfe;
- #ifdef DEBUG_DDR_FASTBOOT_SHA
- printf("&ddr_sha.ddrs : 0x%x\n", (uint32_t)(uint64_t)&ddr_sha.ddrs);
- printf("&ddr_sha.sha2 : 0x%x\n", (uint32_t)(uint64_t)&ddr_sha.sha2);
- printf("ddr_set_add : 0x%x\n", (uint32_t)(uint64_t)ddr_set_add);
- #endif
- sha256_csum_wd((unsigned char *)(uint64_t)ddr_set_add, sizeof(ddr_set_t), ddr_sha.sha2, 0);
- #ifdef DEBUG_DDR_FASTBOOT_SHA
- printf("print sha\n");
- sprintf(str,"md %08x 0x100", (uint32_t)(uint64_t)(ddr_set_add-32));
- run_command(str,0);
- #endif
-{
- #ifdef USE_FOR_UBOOT_2018
- sprintf(str,"store rsv write ddr-parameter 0x%08x 0x%08x ",ddr_set_add-SHA256_SUM_LEN,ddr_set_size+SHA256_SUM_LEN);
- #else
- sprintf(str,"store ddr_parameter write 0x%08x 0x%08x ",ddr_set_add-SHA256_SUM_LEN,ddr_set_size+SHA256_SUM_LEN);
- #endif
- // sprintf(str,"store ddr_parameter write 0x%08x 0x%08x ",ddr_set_add,ddr_set_size);
-// sprintf(str,"store rsv write ddr-parameter 0x%08x 0x%08x ",ddr_set_add,ddr_set_size);
-
- printf("\nstr=%s\n",str);
-
- run_command(str,0);
- }
-
- sprintf(str,"g12_d2pll %d 0x11 %d 0 0 0 0 0 0x%08x 0 %d",ddr_set_t_p->DRAMFreq[0],auto_window_test_enable_item,auto_window_test_dq_size,pattern_dis_scramble);
-
- printf("\nstr=%s\n",str);
-
- run_command(str,0);
- }
- return 1 ;
- }
-
- if((ddr_set_t_p->fast_boot[0])==0xfe)
- {
- char dmc_test_worst_window_rx=0;
- char dmc_test_worst_window_tx=0;
-
-{
- dwc_ddrphy_apb_wr((0<<20)|(0xd<<16)|(0<<12)|(0x0),0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
-
- dmc_test_worst_window_tx=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(0<<12)|(0x0c2));
- dmc_test_worst_window_rx=dwc_ddrphy_apb_rd((0<<20)|(1<<16)|(0<<12)|(0x0c3));
- printf("\ndmc_test_worst_window_tx =%d \n",dmc_test_worst_window_tx);
- printf("\ndmc_test_worst_window_rx=%d \n",dmc_test_worst_window_rx);
- if(dmc_test_worst_window_tx>30)
- dmc_test_worst_window_tx=30;
- if(dmc_test_worst_window_rx>30)
- dmc_test_worst_window_rx=30;
-// dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(0<<12)|(0x1c2),t4_write_worst_margin_rank1);
-// dwc_ddrphy_apb_wr((0<<20)|(1<<16)|(0<<12)|(0x1c3),t4_read_worst_margin_rank1);
-ddr_set_t_p->fast_boot[1]=(((dmc_test_worst_window_tx/2)<<4))|(((dmc_test_worst_window_rx/2)));
- }
-
- ddr_set_t_p->fast_boot[0]=0xff;
- { printf("\nuboot auto fast boot auto window test finish \n");
-
- if(ddr_set_t_p->fast_boot[2])
- {
- if((ddr_set_t_p->fast_boot[2])&0x7)
- {
- if(((ddr_set_t_p->fast_boot[2])&0x8))
- sprintf(str,"ddr_g12_offset_data 3 0x0 0 0 1 %d ",(ddr_set_t_p->fast_boot[2])&0x7);
- else
- sprintf(str,"ddr_g12_offset_data 3 0x0 0 0 2 %d ",(ddr_set_t_p->fast_boot[2])&0x7);
-
- printf("\nstr=%s\n",str);
-
- run_command(str,0);
- }
- if((ddr_set_t_p->fast_boot[2])&0x70)
- {
- if(((ddr_set_t_p->fast_boot[2])&0x80))
- sprintf(str,"ddr_g12_offset_data 2 0x0 0 0 1 %d ",((ddr_set_t_p->fast_boot[2])>>4)&0x7);
- else
- sprintf(str,"ddr_g12_offset_data 2 0x0 0 0 2 %d ",((ddr_set_t_p->fast_boot[2])>>4)&0x7);
-
- printf("\nstr=%s\n",str);
-
- run_command(str,0);
- }
-
- sprintf(str,"ddr_fast_boot 1 ");
-
- printf("\nstr=%s\n",str);
-
- run_command(str,0);
-
- }
- else
- {
- #ifdef DEBUG_DDR_FASTBOOT_SHA
- printf("&ddr_sha.ddrs : 0x%x\n", (uint32_t)(uint64_t)&ddr_sha.ddrs);
- printf("&ddr_sha.sha2 : 0x%x\n", (uint32_t)(uint64_t)&ddr_sha.sha2);
- printf("ddr_set_add : 0x%x\n", (uint32_t)(uint64_t)ddr_set_add);
- #endif
- sha256_csum_wd((unsigned char *)(uint64_t)ddr_set_add, sizeof(ddr_set_t), ddr_sha.sha2, 0);
- #ifdef DEBUG_DDR_FASTBOOT_SHA
- printf("print sha\n");
- sprintf(str,"md %08x 0x100", (uint32_t)(uint64_t)(ddr_set_add-32));
- run_command(str,0);
- #endif
-
- {
- #ifdef USE_FOR_UBOOT_2018
- sprintf(str,"store rsv write ddr-parameter 0x%08x 0x%08x ",ddr_set_add-SHA256_SUM_LEN,ddr_set_size+SHA256_SUM_LEN);
- #else
- sprintf(str,"store ddr_parameter write 0x%08x 0x%08x ",ddr_set_add-SHA256_SUM_LEN,ddr_set_size+SHA256_SUM_LEN);
- #endif
- // sprintf(str,"store ddr_parameter write 0x%08x 0x%08x ",ddr_set_add,ddr_set_size);
- // sprintf(str,"store rsv write ddr-parameter 0x%08x 0x%08x ",ddr_set_add,ddr_set_size);
- printf("\nstr=%s\n",str);
-
- run_command(str,0);
- }
- }
- return 1 ;
- }
- }
-
-
-
- return 1;
-
-
-}
U_BOOT_CMD(
ddr_auto_scan_drv, 30, 1, do_ddr_auto_scan_drv,
"ddr_test_cmd cmd arg1 arg2 arg3...",
"ddr_test_cmd cmd arg1 arg2 arg3... \n dcache off ? \n"
);
-U_BOOT_CMD(
- ddr_fast_boot, 30, 1, do_ddr_fastboot_config,
- "ddr_fastboot_config cmd arg1 arg2 arg3...",
- "ddr_fastboot_config cmd arg1 arg2 arg3... \n dcache off ? \n"
- );
-U_BOOT_CMD(
- ddr_auto_fast_boot_check, 30, 1, do_ddr_auto_fastboot_check,
- "ddr_fastboot_config cmd arg1 arg2 arg3...",
- "ddr_fastboot_config cmd arg1 arg2 arg3... \n dcache off ? \n"
- );
-
diff --git a/cmd/amlogic/cmd_ddr_test_g12.c b/cmd/amlogic/cmd_ddr_test_g12.c
new file mode 100644
index 0000000..4d41749
--- /dev/null
+++ b/cmd/amlogic/cmd_ddr_test_g12.c
@@ -0,0 +1,10670 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+
+#define USE_FOR_UBOOT_2018
+//#define USE_FOR_UBOOT_2015
+#define GET_CHIP_ID
+
+#ifdef USE_FOR_UBOOT_2018
+#define DISABLE_ENV
+#define USE_FOR_UBOOT_2018
+#include <amlogic/cpu_id.h>
+#endif
+#ifdef USE_FOR_UBOOT_2015
+#include <asm/cpu_id.h>
+#endif
+
+uint32_t do_read_c2_ddr_bdlr_steps(void);
+
+struct ddr_base_address_table {
+ char soc_family_name[16];
+ unsigned int chip_id;
+ unsigned int preg_sticky_reg0;
+ unsigned int ddr_phy_base_address;
+ unsigned int ddr_pctl_timing_base_address;
+ unsigned int ddr_pctl_timing_end_address;
+ unsigned int ddr_dmc_sticky0;
+ unsigned int sys_watchdog_base_address;
+ unsigned int sys_watchdog_enable_value;
+ unsigned int ddr_pll_base_address;
+ unsigned int ee_timer_base_address;
+ unsigned int ee_pwm_base_address;
+ unsigned int ddr_dmc_apd_address;
+ unsigned int ddr_dmc_asr_address;
+ unsigned int ddr_boot_reason_address;
+ unsigned int ddr_dmc_lpdd4_retraining_address;
+ unsigned int ddr_dmc_refresh_ctrl_address;
+
+ unsigned int ddr_dmc_sticky0_1;
+ unsigned int ddr_phy_base_address_1;
+ unsigned int ddr_pctl_timing_base_address_1;
+ unsigned int ddr_pctl_timing_end_address_1;
+ unsigned int ddr_dmc_apd_address_1;
+ unsigned int ddr_dmc_asr_address_1;
+ unsigned int ddr_dmc_lpdd4_retraining_address_1;
+ unsigned int ddr_dmc_refresh_ctrl_address_1;
+};
+typedef struct ddr_base_address_table ddr_base_address_table_t;
+
+#define MESON_CPU_MAJOR_ID_GXBB 0x1F
+#define MESON_CPU_MAJOR_ID_GXTVBB 0x20
+#define MESON_CPU_MAJOR_ID_GXLBB 0x21
+#define MESON_CPU_MAJOR_ID_GXM 0x22
+#define MESON_CPU_MAJOR_ID_TXL 0x23
+#define MESON_CPU_MAJOR_ID_TXLX 0x24
+#define MESON_CPU_MAJOR_ID_AXG 0x25
+#define MESON_CPU_MAJOR_ID_GXLX 0x26
+#define MESON_CPU_MAJOR_ID_TXHD 0x27
+#define MESON_CPU_MAJOR_ID_G12A 0x28
+#define MESON_CPU_MAJOR_ID_G12B 0x29
+
+#define MESON_CPU_MAJOR_ID_SM1 0x2B
+
+#define MESON_CPU_MAJOR_ID_A1 0x2C
+
+#define MESON_CPU_MAJOR_ID_TL1 0x2E
+#define MESON_CPU_MAJOR_ID_TM2 0x2F
+#define MESON_CPU_MAJOR_ID_C1 0x30
+#define MESON_CPU_MAJOR_ID_SC2 0x32
+#define MESON_CPU_MAJOR_ID_C2 0x33
+#define MESON_CPU_MAJOR_ID_T5 0x34
+#define MESON_CPU_MAJOR_ID_T5D 0x35
+#define MESON_CPU_MAJOR_ID_T7 0x36
+#define MESON_CPU_MAJOR_ID_S4 0x37
+
+#define MESON_CPU_VERSION_LVL_MAJOR 0
+#define MESON_CPU_VERSION_LVL_MINOR 1
+#define MESON_CPU_VERSION_LVL_PACK 2
+#define MESON_CPU_VERSION_LVL_MISC 3
+#define MESON_CPU_VERSION_LVL_MAX MESON_CPU_VERSION_LVL_MISC
+
+#define CHIP_ID_MASK 0xff
+char global_chip_id[12] = { 0 };
+
+#define MESON_CPU_CHIP_ID_SIZE 12 //4 //12byte
+int ddr_get_chip_id(void)
+{
+ int soc_family_id = 0;
+
+ soc_family_id = get_cpu_id().family_id;
+ printf("\nsoc_family_id==0x%08x", soc_family_id);
+
+ unsigned char chipid[16];
+#ifdef GET_CHIP_ID
+ get_chip_id(chipid, 16);
+#endif
+ int count = 0;
+
+ for (count = 0; count < 16; count++) {
+ if (count > 3)
+ global_chip_id[16 - 1 - count] = chipid[count];
+ }
+
+ return soc_family_id;
+}
+
+char CMD_VER[] = "Ver_14";
+ddr_base_address_table_t __ddr_base_address_table[] =
+{
+ //g12a
+ {
+ .soc_family_name = "G12A",
+ .chip_id = MESON_CPU_MAJOR_ID_G12A,
+ .preg_sticky_reg0 = (0xff634400 + (0x070 << 2)), //PREG_STICKY_G12A_REG0
+ .ddr_phy_base_address = 0xfe000000,
+ .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xff638400),
+ .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xff638400),
+ .ddr_dmc_sticky0 = 0xff638800,
+ .sys_watchdog_base_address = ((0x3c34 << 2) + 0xffd00000),
+ .ddr_pll_base_address = ((0x0000 << 2) + 0xff638c00),
+ .ee_timer_base_address = ((0x3c62 << 2) + 0xffd00000),
+ .ee_pwm_base_address = (0xff807000 + (0x001 << 2)),
+ .ddr_dmc_apd_address = ((0x008c << 2) + 0xff638400),
+ .ddr_dmc_asr_address = ((0x008d << 2) + 0xff638400),
+ .ddr_boot_reason_address = (0xff800000 + (0x08f << 2)), //AO_SEC_SD_CFG15
+ .ddr_dmc_lpdd4_retraining_address = ((0x0097 << 2) + 0xff638400),
+ },
+ //g12b
+ {
+ .soc_family_name = "G12B",
+ .chip_id = MESON_CPU_MAJOR_ID_G12B,
+ .preg_sticky_reg0 = (0xff634400 + (0x070 << 2)), //PREG_STICKY_G12A_REG0
+ .ddr_phy_base_address = 0xfe000000,
+ .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xff638400),
+ .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xff638400),
+ .ddr_dmc_sticky0 = 0xff638800,
+ .sys_watchdog_base_address = ((0x3c34 << 2) + 0xffd00000),
+ .ddr_pll_base_address = ((0x0000 << 2) + 0xff638c00),
+ .ee_timer_base_address = ((0x3c62 << 2) + 0xffd00000),
+ .ee_pwm_base_address = (0xff807000 + (0x001 << 2)),
+ .ddr_dmc_apd_address = ((0x008c << 2) + 0xff638400),
+ .ddr_dmc_asr_address = ((0x008d << 2) + 0xff638400),
+ .ddr_boot_reason_address = (0xff800000 + (0x08f << 2)), //AO_SEC_SD_CFG15
+ .ddr_dmc_lpdd4_retraining_address = ((0x0097 << 2) + 0xff638400),
+ },
+ //tl1
+ {
+ .soc_family_name = "TL1",
+ .chip_id = MESON_CPU_MAJOR_ID_TL1,
+ .preg_sticky_reg0 = (0xff634400 + (0x070 << 2)), //PREG_STICKY_G12A_REG0
+ .ddr_phy_base_address = 0xfe000000,
+ .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xff638400),
+ .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xff638400),
+ .ddr_dmc_sticky0 = 0xff638800,
+ .sys_watchdog_base_address = ((0x3c34 << 2) + 0xffd00000),
+ .ddr_pll_base_address = ((0x0000 << 2) + 0xff638c00),
+ .ee_timer_base_address = ((0x3c62 << 2) + 0xffd00000),
+ .ee_pwm_base_address = (0xff807000 + (0x001 << 2)),
+ .ddr_dmc_apd_address = ((0x008c << 2) + 0xff638400),
+ .ddr_dmc_asr_address = ((0x008d << 2) + 0xff638400),
+ .ddr_boot_reason_address = (0xff800000 + (0x08f << 2)), //AO_SEC_SD_CFG15
+ .ddr_dmc_lpdd4_retraining_address = ((0x0097 << 2) + 0xff638400),
+ },
+ //sm1
+ {
+ .soc_family_name = "SM1",
+ .chip_id = MESON_CPU_MAJOR_ID_SM1,
+ .preg_sticky_reg0 = (0xff634400 + (0x070 << 2)), //PREG_STICKY_G12A_REG0
+ .ddr_phy_base_address = 0xfe000000,
+ .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xff638400),
+ .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xff638400),
+ .ddr_dmc_sticky0 = 0xff638800,
+ .sys_watchdog_base_address = ((0x3c34 << 2) + 0xffd00000),
+ .ddr_pll_base_address = ((0x0000 << 2) + 0xff638c00),
+ .ee_timer_base_address = ((0x3c62 << 2) + 0xffd00000),
+ .ee_pwm_base_address = (0xff807000 + (0x001 << 2)),
+ .ddr_dmc_apd_address = ((0x008c << 2) + 0xff638400),
+ .ddr_dmc_asr_address = ((0x008d << 2) + 0xff638400),
+ .ddr_boot_reason_address = (0xff800000 + (0x08f << 2)), //AO_SEC_SD_CFG15
+ .ddr_dmc_lpdd4_retraining_address = ((0x0097 << 2) + 0xff638400),
+ },
+ //tm2
+ {
+ .soc_family_name = "TM2",
+ .chip_id = MESON_CPU_MAJOR_ID_TM2,
+ .preg_sticky_reg0 = (0xff634400 + (0x070 << 2)), //PREG_STICKY_G12A_REG0
+ .ddr_phy_base_address = 0xfe000000,
+ .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xff638400),
+ .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xff638400),
+ .ddr_dmc_sticky0 = 0xff638800,
+ .sys_watchdog_base_address = ((0x3c34 << 2) + 0xffd00000),
+ .ddr_pll_base_address = ((0x0000 << 2) + 0xff638c00),
+ .ee_timer_base_address = ((0x3c62 << 2) + 0xffd00000),
+ .ee_pwm_base_address = (0xff807000 + (0x001 << 2)),
+ .ddr_dmc_apd_address = ((0x008c << 2) + 0xff638400),
+ .ddr_dmc_asr_address = ((0x008d << 2) + 0xff638400),
+ .ddr_boot_reason_address = (0xff800000 + (0x08f << 2)), //AO_SEC_SD_CFG15
+ .ddr_dmc_lpdd4_retraining_address = ((0x0097 << 2) + 0xff638400),
+ },
+ //a1
+ {
+ .soc_family_name = "A1",
+ .chip_id = MESON_CPU_MAJOR_ID_A1,
+ .preg_sticky_reg0 = 0xfffff400, //use sram A1,((0x00b0 << 2) + 0xfe005800),//SYSCTRL_STICKY_REG0
+ .ddr_phy_base_address = 0xfc000000,
+ .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xfd020400),
+ .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xfd020400),
+ .ddr_dmc_sticky0 = 0xfd020800,
+ .ddr_dmc_apd_address = ((0x008c << 2) + 0xfd020400),
+ .ddr_dmc_asr_address = ((0x008d << 2) + 0xfd020400),
+ .sys_watchdog_base_address = 0, //((0x0040 << 2) + 0xfe000000),
+ .sys_watchdog_enable_value = 0x03c401ff,
+ .ddr_boot_reason_address = ((0x00e1 << 2) + 0xfe005800), //SYSCTRL_SEC_STICKY_REG1
+ .ee_timer_base_address = ((0x0041 << 2) + 0xfe005800),
+ },
+ //c1
+ {
+ .soc_family_name = "C1",
+ .chip_id = MESON_CPU_MAJOR_ID_C1,
+ .preg_sticky_reg0 = 0xfffff400, //use sram A1,((0x00b0 << 2) + 0xfe005800),//SYSCTRL_STICKY_REG0
+ .ddr_phy_base_address = 0xfd000000,
+ .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xfe024400),
+ .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xfe024400),
+ .ddr_dmc_sticky0 = ((0x0000 << 2) + 0xfe024800),
+ .ddr_pll_base_address = ((0x0000 << 2) + 0xfe024c00),
+ .ddr_dmc_apd_address = ((0x008c << 2) + 0xfe024400),
+ .ddr_dmc_asr_address = ((0x008d << 2) + 0xfe024400),
+ .sys_watchdog_base_address = 0, //((0x0040 << 2) + 0xfe000000),
+ .sys_watchdog_enable_value = 0x03c401ff,
+ .ddr_boot_reason_address = ((0x00e1 << 2) + 0xfe005800), //SYSCTRL_SEC_STICKY_REG1
+ .ee_timer_base_address = ((0x0041 << 2) + 0xfe005800),
+ },
+ //c2
+ {
+ .soc_family_name = "C2",
+ .chip_id = MESON_CPU_MAJOR_ID_C2,
+ .preg_sticky_reg0 = ((0x0000 << 2) + 0xfe024800), //use sram A1,((0x00b0 << 2) + 0xfe005800),//SYSCTRL_STICKY_REG0
+ .ddr_phy_base_address = 0xfd000000,
+ .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xfe024400),
+ .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xfe024400),
+ .ddr_dmc_sticky0 = ((0x0000 << 2) + 0xfe024800),
+ .ddr_pll_base_address = ((0x0000 << 2) + 0xfe024c00),
+ .ddr_dmc_apd_address = ((0x008c << 2) + 0xfe024400),
+ .ddr_dmc_asr_address = ((0x008d << 2) + 0xfe024400),
+ .sys_watchdog_base_address = 0, //((0x0040 << 2) + 0xfe000000),
+ .sys_watchdog_enable_value = 0x03c401ff,
+ .ddr_boot_reason_address = ((0x00e1 << 2) + 0xfe005800), //SYSCTRL_SEC_STICKY_REG1
+ .ddr_dmc_lpdd4_retraining_address = ((0x0097 << 2) + 0xfe024400),
+ .ddr_dmc_refresh_ctrl_address = ((0x0092 << 2) + 0xfe024400), //DMC_DRAM_REFR_CTRL
+ .ee_timer_base_address = ((0x0041 << 2) + 0xfe005800),
+ },
+ //sc2
+ {
+ .soc_family_name = "SC2",
+ .chip_id = MESON_CPU_MAJOR_ID_SC2,
+ .preg_sticky_reg0 = ((0x0000 << 2) + 0xfe036800), //
+ .ddr_phy_base_address = 0xfc000000,
+ .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xfe036400),
+ .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xfe036400),
+ .ddr_dmc_sticky0 = 0xfe036800,
+ .sys_watchdog_base_address = ((0x3c34 << 2) + 0xffd00000), //sc2 can not find
+ .ddr_pll_base_address = ((0x0000 << 2) + 0xfe036c00),
+ .ee_timer_base_address = ((0x003b << 2) + 0xfe010000), //sc2 can not find
+ .ee_pwm_base_address = ((0x0001 << 2) + 0xfe05e000), //PWMGH_PWM_B
+ .ddr_dmc_apd_address = ((0x008c << 2) + 0xfe036400),
+ .ddr_dmc_asr_address = ((0x008d << 2) + 0xfe036400),
+ //.ddr_boot_reason_address = ((0x00e1 << 2) + 0xfe010000), //SYSCTRL_SEC_STICKY_REG1,20210204,0xfe010384,zhiguang confirm
+ },
+ //T5
+ {
+ .soc_family_name = "T5",
+ .chip_id = MESON_CPU_MAJOR_ID_T5,
+ .preg_sticky_reg0 = ((0x0000 << 2) + 0xff638800),
+ .ddr_phy_base_address = 0xfe000000,
+ .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xff638400),
+ .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xff638400),
+ .ddr_dmc_sticky0 = ((0x0000 << 2) + 0xff638800),
+ .ddr_pll_base_address = ((0x0000 << 2) + 0xff638c00), //AM_DDR_PLL_CNTL0
+ .ddr_boot_reason_address = (0xff800000 + (0x003 << 2)), //#define SEC_AO_RTI_STATUS_REG3
+ //.ddr_dmc_lpdd4_retraining_address = ((0x0097 << 2) + 0xfe024400),
+
+ .sys_watchdog_base_address = 0,
+ .sys_watchdog_enable_value = 0x03c401ff,
+ .ee_timer_base_address = 0xffd0f188, //#define P_EE_TIMER_E (volatile uint32_t *)0xffd0f188
+ .ee_pwm_base_address = ((0x001 << 2) + 0xff807000), //AO_PWM_PWM_B
+ .ddr_dmc_apd_address = ((0x008c << 2) + 0xff638400),
+ .ddr_dmc_asr_address = ((0x008d << 2) + 0xff638400),
+ .ddr_dmc_refresh_ctrl_address = ((0x0092 << 2) + 0xff638400), // DMC_DRAM_REFR_CTRL ((0x0092 << 2) + 0xff638400)
+ },
+ //T5D
+ {
+ .soc_family_name = "T5D",
+ .chip_id = MESON_CPU_MAJOR_ID_T5D,
+ .preg_sticky_reg0 = ((0x0000 << 2) + 0xff638800),
+ .ddr_phy_base_address = 0xfe000000,
+ .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xff638400),
+ .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xff638400),
+ .ddr_dmc_sticky0 = ((0x0000 << 2) + 0xff638800),
+ .ddr_pll_base_address = ((0x0000 << 2) + 0xff638c00), //AM_DDR_PLL_CNTL0
+ .ddr_boot_reason_address = (0xff800000 + (0x003 << 2)), //#define SEC_AO_RTI_STATUS_REG3
+ //.ddr_dmc_lpdd4_retraining_address = ((0x0097 << 2) + 0xfe024400),
+
+ .sys_watchdog_base_address = 0,
+ .sys_watchdog_enable_value = 0x03c401ff,
+ .ee_timer_base_address = 0xffd0f188, //#define P_EE_TIMER_E (volatile uint32_t *)0xffd0f188
+ .ee_pwm_base_address = ((0x001 << 2) + 0xff807000), //AO_PWM_PWM_B
+ .ddr_dmc_apd_address = ((0x008c << 2) + 0xff638400),
+ .ddr_dmc_asr_address = ((0x008d << 2) + 0xff638400),
+ .ddr_dmc_refresh_ctrl_address = ((0x0092 << 2) + 0xff638400), // DMC_DRAM_REFR_CTRL ((0x0092 << 2) + 0xff638400)
+ },
+ //T7
+ {
+ .soc_family_name = "T7",
+ .chip_id = MESON_CPU_MAJOR_ID_T7,
+ .preg_sticky_reg0 = ((0x0000 << 2) + 0xfe036800), //
+ .ddr_phy_base_address = 0xfc000000,
+ .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xfe036400),
+ .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xfe036400),
+ .ddr_dmc_sticky0 = ((0x200 << 2) + 0xfe036000),
+ .sys_watchdog_base_address = ((0x3c34 << 2) + 0xffd00000), //sc2 can not find
+ .ddr_pll_base_address = ((0x0000 << 2) + 0xfe036c00),
+ .ee_timer_base_address = ((0x003b << 2) + 0xfe010000), //sc2 can not find
+ .ee_pwm_base_address = ((0x0001 << 2) + 0xfe05e000), //PWMGH_PWM_B
+ .ddr_dmc_apd_address = ((0x018c << 2) + 0xfe036000),
+ .ddr_dmc_asr_address = ((0x018d << 2) + 0xfe036000),
+ //.ddr_boot_reason_address = ((0x00c1 << 2) + 0xfe010000), //SYSCTRL_SEC_STATUS_REG1,20210204,0xfe010304,zhiguang confirm
+
+ .ddr_dmc_lpdd4_retraining_address = ((0x0197 << 2) + 0xfe036000),
+ .ddr_dmc_refresh_ctrl_address = ((0x0192 << 2) + 0xfe036000),
+
+ .ddr_dmc_sticky0_1 = ((0x200 << 2) + 0xfe034000),
+ .ddr_dmc_refresh_ctrl_address_1 = ((0x0192 << 2) + 0xfe036000),
+ .ddr_phy_base_address_1 = 0xfb000000,
+ .ddr_pctl_timing_base_address_1 = ((0x0000 << 2) + 0xfe034400),
+ .ddr_pctl_timing_end_address_1 = ((0x00bb << 2) + 0xfe034400),
+ .ddr_dmc_apd_address_1 = ((0x018c << 2) + 0xfe034000),
+ .ddr_dmc_asr_address_1 = ((0x018d << 2) + 0xfe034000),
+ .ddr_dmc_lpdd4_retraining_address_1 = ((0x0197 << 2) + 0xfe034000),
+ .ddr_dmc_refresh_ctrl_address_1 = ((0x0192 << 2) + 0xfe034000),
+ },
+ //S4
+ {
+ .soc_family_name = "S4",
+ .chip_id = MESON_CPU_MAJOR_ID_S4,
+ .preg_sticky_reg0 = ((0x0000 << 2) + 0xfe036800),
+ .ddr_phy_base_address = 0xfc000000,
+ .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xfe036400),//DMC_DRAM_TRFC
+ .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xfe036400),//DMC_DRAM_DFI
+ .ddr_dmc_sticky0 = ((0x0000 << 2) + 0xfe036800),
+ .ddr_pll_base_address = ((0x0000 << 2) + 0xfe036c00), //AM_DDR_PLL_CNTL0//
+ //.ddr_boot_reason_address = ((0x00e1 << 2) + 0xfe010000), //SYSCTRL_SEC_STICKY_REG1,20210204,0xfe010384,zhiguang confirm
+ //.ddr_dmc_lpdd4_retraining_address = ((0x0097 << 2) + 0xfe024400),
+
+ .sys_watchdog_base_address = 0,
+ .sys_watchdog_enable_value = 0x03c401ff,
+ .ee_timer_base_address = ((0x003b << 2) + 0xfe010000), //SYSCTRL_TIMERE ((0x003b << 2) + 0xfe010000)
+ .ee_pwm_base_address = ((0x001 << 2) + 0xff807000), //AO_PWM_PWM_B
+ .ddr_dmc_apd_address = ((0x008c << 2) + 0xfe036400),//DMC_DRAM_APD_CTRL
+ .ddr_dmc_asr_address = ((0x008d << 2) + 0xfe036400),//DMC_DRAM_ASR_CTRL
+ .ddr_dmc_refresh_ctrl_address = ((0x0092 << 2) + 0xfe036400), // DMC_DRAM_REFR_CTRL ((0x0092 << 2) + 0xff638400)
+ },
+ // force id use id mask
+ {
+ .soc_family_name = "UKNOWN",
+ .chip_id = CHIP_ID_MASK, //MESON_CPU_MAJOR_ID_G12A,
+ .preg_sticky_reg0 = (0xff634400 + (0x070 << 2)), //PREG_STICKY_G12A_REG0
+ .ddr_phy_base_address = 0xfe000000,
+ .ddr_pctl_timing_base_address = ((0x0000 << 2) + 0xff638400),
+ .ddr_pctl_timing_end_address = ((0x00bb << 2) + 0xff638400),
+ .ddr_dmc_sticky0 = 0xff638800,
+ .sys_watchdog_base_address = ((0x3c34 << 2) + 0xffd00000),
+ .ddr_pll_base_address = ((0x0000 << 2) + 0xff638c00),
+ .ee_timer_base_address = ((0x3c62 << 2) + 0xffd00000),
+ .ee_pwm_base_address = (0xff807000 + (0x001 << 2)),
+ .ddr_dmc_apd_address = ((0x008c << 2) + 0xff638400),
+ .ddr_dmc_asr_address = ((0x008d << 2) + 0xff638400),
+ .ddr_boot_reason_address = (0xff800000 + (0x08f << 2)), //AO_SEC_SD_CFG15
+ .ddr_dmc_lpdd4_retraining_address = ((0x0097 << 2) + 0xff638400),
+ },
+};
+
+ddr_base_address_table_t *p_ddr_base = { 0 };
+unsigned int phy_base_add[2] = { 0, 0, };
+unsigned int ddr_dmc_sticky[2] = { 0, 0, };
+unsigned int ddr_dmc_apd_address[2] = { 0, 0, };
+unsigned int ddr_dmc_asr_address[2] = { 0, 0, };
+unsigned int dmc_retraining_ctrl_address[2] = { 0, 0, };
+unsigned int dmc_ddr_config_channel_id=0;
+//#ifdef CONFIG_ENV_IS_NOWHERE
+#ifdef DISABLE_ENV
+int setenv(const char *varname, const char *varvalue)
+{
+ return 1;
+}
+
+char *getenv(const char *name)
+{
+ return NULL;
+}
+
+#endif
+
+#define DWC_AC_PINMUX_TOTAL 28
+#define DWC_DFI_PINMUX_TOTAL 26
+
+#define DDR_STICKY_MAGIC_NUMBER 0x20180000
+#define DDR_CHIP_ID 0x30
+#define DDR_STICKY_SOURCE_DMC_STICKY 0x1
+#define DDR_STICKY_SOURCE_SRAM 0x2
+
+#define DDR_STICKY_OVERRIDE_CONFIG_MESSAGE_CMD 0x1 //override config
+#define DDR_STICKY_SPECIAL_FUNCTION_CMD 0x2 //special test such as shift some bdlr or parameter or interleave test
+
+#define DDR_INIT_CONFIG_STICKY_MESSAGE_SRAM_ADDRESS 0x00040000
+#define DDR_INIT_CONFIG_GLOBAL_MESSAGE_SRAM_ADDRESS 0x00050000
+#define CONFIG_DDR_TYPE_DDR3 0
+#define CONFIG_DDR_TYPE_DDR4 1
+#define CONFIG_DDR_TYPE_LPDDR4 2
+#define CONFIG_DDR_TYPE_LPDDR3 3
+#define CONFIG_DDR_TYPE_LPDDR2 4
+#define CONFIG_DDR_TYPE_AUTO 0xf
+#define CONFIG_DDR_TYPE_AUTO_LIMIT CONFIG_DDR_TYPE_DDR4
+
+#define CONFIG_DDR0_16BIT_CH0 0x1
+#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4
+#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2
+#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3
+#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5
+#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6
+#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7
+#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8
+#define DDR_PRINT_DISABLE 0
+#define DDR_PRINT_ENABLE 1
+
+typedef struct board_common_setting {
+ unsigned int timming_magic;
+ unsigned short timming_max_valid_configs;
+ unsigned short timming_struct_version;
+ unsigned short timming_struct_org_size;
+ unsigned short timming_struct_real_size;
+ unsigned char fast_boot[4]; // 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test enable
+ unsigned int ddr_func;
+ unsigned char board_id;
+ unsigned char DramType;
+ unsigned char dram_rank_config;
+ unsigned char DisabledDbyte;
+ unsigned int dram_cs0_base_add;
+ unsigned int dram_cs1_base_add;
+ unsigned short dram_cs0_size_MB;
+ unsigned short dram_cs1_size_MB;
+ unsigned char dram_x4x8x16_mode;
+ unsigned char Is2Ttiming;
+ unsigned char log_level;
+ unsigned char ddr_rdbi_wr_enable;
+ unsigned int pll_ssc_mode;
+ unsigned short org_tdqs2dq;
+ unsigned char reserve1_test_function[2];
+ unsigned int ddr_dmc_remap[5];
+ unsigned char ac_pinmux[35];
+ unsigned char ddr_dqs_swap;
+ unsigned char ddr_dq_remap[36];
+ unsigned int ddr_vddee_setting[4]; //add,default-value,default-voltage,step
+}__attribute__ ((packed)) board_common_setting_t;
+
+typedef struct board_SI_setting_ps {
+ unsigned short DRAMFreq;
+ unsigned char PllBypassEn;
+ unsigned char training_SequenceCtrl;
+ unsigned short ddr_odt_config;
+ unsigned char clk_drv_ohm;
+ unsigned char cs_drv_ohm;
+ unsigned char ac_drv_ohm;
+ unsigned char soc_data_drv_ohm_p;
+ unsigned char soc_data_drv_ohm_n;
+ unsigned char soc_data_odt_ohm_p;
+ unsigned char soc_data_odt_ohm_n;
+ unsigned char dram_data_drv_ohm;
+ unsigned char dram_data_odt_ohm;
+ unsigned char dram_data_wr_odt_ohm;
+ unsigned char dram_ac_odt_ohm;
+ unsigned char dram_data_drv_pull_up_calibration_ohm;
+ unsigned char lpddr4_dram_vout_voltage_range_setting;
+ unsigned char reserve2;
+ unsigned short vref_ac_permil; //phy
+ unsigned short vref_soc_data_permil; //soc
+ unsigned short vref_dram_data_permil;
+ unsigned short max_core_timmming_frequency;
+ unsigned short training_phase_parameter[2];
+ unsigned short ac_trace_delay_org[36];
+}__attribute__ ((packed)) board_SI_setting_ps_t;
+
+typedef struct board_phase_setting_ps {
+ unsigned short ac_trace_delay[36];
+ unsigned short write_dqs_delay[8];
+ unsigned short write_dq_bit_delay[72];
+ unsigned short read_dqs_gate_delay[8];
+ unsigned char read_dqs_delay[8];
+ unsigned char read_dq_bit_delay[72];
+ unsigned char soc_bit_vref[44];
+ unsigned char dram_bit_vref[36];
+ unsigned char reserve_training_parameter[16]; //0-7 write dqs offset,8-15 read dqs offset,MSB bit 7 use 0 mean right offset
+ unsigned char soc_bit_vref_dac1[44];
+}__attribute__ ((packed)) board_phase_setting_ps_t;
+
+typedef struct ddr_set_c2 {
+ board_common_setting_t cfg_board_common_setting;
+ board_SI_setting_ps_t cfg_board_SI_setting_ps[2];
+ board_phase_setting_ps_t cfg_ddr_training_delay_ps[2];
+}__attribute__ ((packed)) ddr_set_t_c2;
+
+static uint32_t ddr_rd_8_16bit_on_32reg(uint32_t base_addr, uint32_t size, uint32_t offset_index)
+{
+ uint32_t read_value = 0;
+ uint32_t addr_t = 0;
+ uint32_t offset = 0;
+
+ if (size == 8) {
+ offset = ((offset_index % 4) << 3);
+ addr_t = (base_addr + ((offset_index >> 2) << 2));
+ read_value = (*(volatile uint32_t *)((unsigned long)(addr_t)));
+ read_value = (read_value >> offset) & 0xff;
+ }
+ if (size == 16) {
+ offset = ((offset_index % 2) << 4);
+ addr_t = (base_addr + ((offset_index >> 1) << 2));
+ read_value = (*(volatile uint32_t *)((unsigned long)(addr_t)));
+ read_value = (read_value >> offset) & 0xffff;
+ }
+ return read_value;
+}
+
+static uint32_t ddr_wr_8_16bit_on_32reg(uint32_t base_addr, uint32_t size, uint32_t offset_index, uint32_t value)
+{
+ uint32_t read_value = 0;
+ uint32_t write_value = 0;
+ uint32_t addr_t = 0;
+ uint32_t offset = 0;
+
+ if (size == 8) {
+ offset = ((offset_index % 4) << 3);
+ addr_t = (base_addr + ((offset_index >> 2) << 2));
+ read_value = (*(volatile uint32_t *)((unsigned long)(addr_t)));
+ write_value = (value << offset) | (read_value & (~(0xff << offset)));
+ }
+ if (size == 16) {
+ offset = ((offset_index % 2) << 4);
+ addr_t = (base_addr + ((offset_index >> 1) << 2));
+ read_value = (*(volatile uint32_t *)((unsigned long)(addr_t)));
+ write_value = (value << offset) | (read_value & (~(0xffff << offset)));
+ }
+ *(volatile uint32_t *)((unsigned long)(addr_t)) = write_value;
+ return write_value;
+}
+
+uint32_t ddr_min(uint32_t a, uint32_t b)
+{
+ uint32_t min = a;
+
+ if (a < b)
+ min = a;
+ else
+ min = b;
+ return min;
+}
+
+uint32_t ddr_max(uint32_t a, uint32_t b)
+{
+ uint32_t max = a;
+
+ if (a < b)
+ max = b;
+ else
+ max = a;
+ return max;
+}
+
+typedef struct training_delay_set_ps {
+ unsigned char ac_trace_delay[10];
+ unsigned char ac_trace_delay_rev[2];
+ unsigned char read_dqs_delay[16];
+ unsigned char read_dq_bit_delay[72];
+ unsigned short write_dqs_delay[16];
+ unsigned short write_dq_bit_delay[72];
+ unsigned short read_dqs_gate_delay[16];
+ unsigned char soc_bit_vref[36];
+ unsigned char dram_bit_vref[32];
+ unsigned char rever1; //read_dqs read_dq,write_dqs, write_dq
+ unsigned char dfi_mrl;
+ unsigned char dfi_hwtmrl;
+ unsigned char ARdPtrInitVal;
+ unsigned short csr_vrefinglobal;
+ unsigned short csr_dqsrcvcntrl[4];
+ unsigned short csr_pptdqscntinvtrntg0[4];
+ unsigned short csr_pptdqscntinvtrntg1[4];
+ unsigned short csr_seq0bgpr[9];
+ unsigned short csr_dllgainctl;
+ unsigned short csr_dlllockpara;
+}__attribute__ ((packed)) training_delay_set_ps_t;
+
+typedef struct ddr_phy_common_extra_set {
+ unsigned short csr_pllctrl3;
+ unsigned short csr_pptctlstatic[4];
+ unsigned short csr_trainingincdecdtsmen[4];
+ unsigned short csr_tsmbyte0[4];
+ unsigned short csr_hwtcamode;
+ unsigned short csr_hwtlpcsena;
+ unsigned short csr_hwtlpcsenb;
+ unsigned short csr_acsmctrl13;
+ unsigned short csr_acsmctrl23;
+ unsigned char csr_soc_vref_dac1_dfe[36];
+}__attribute__ ((packed)) ddr_phy_common_extra_set_t;
+
+typedef struct retraining_set {
+ unsigned short csr_pllctrl3;
+ unsigned short csr_pptctlstatic[4];
+ unsigned short csr_trainingincdecdtsmen[4];
+ unsigned short csr_tsmbyte0[4];
+ unsigned short csr_vrefinglobal;
+ unsigned short csr_dqsrcvcntrl[4];
+ unsigned short csr_pptdqscntinvtrntg0[4];
+ unsigned short csr_pptdqscntinvtrntg1[4];
+ unsigned short csr_seq0bgpr[9];
+ unsigned short csr_dllgainctl;
+ unsigned short csr_dlllockpara;
+ unsigned short csr_hwtcamode;
+ unsigned short csr_hwtlpcsena;
+ unsigned short csr_hwtlpcsenb;
+ unsigned short csr_acsmctrl13;
+ unsigned short csr_acsmctrl23;
+ unsigned char csr_soc_vref_dac1_dfe[36];
+}retraining_set_t;
+
+typedef struct ddr_set {
+ unsigned int magic;
+ unsigned char fast_boot[4]; // 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test
+ unsigned int ddr_func;
+ unsigned char board_id;
+ //board id reserve,,do not modify
+ unsigned char version;
+ // firmware reserve version,,do not modify
+ unsigned char DramType;
+ //support DramType should confirm with amlogic
+ //#define CONFIG_DDR_TYPE_DDR3 0
+ //#define CONFIG_DDR_TYPE_DDR4 1
+ //#define CONFIG_DDR_TYPE_LPDDR4 2
+ //#define CONFIG_DDR_TYPE_LPDDR3 3
+ //#define CONFIG_DDR_TYPE_LPDDR2 4
+ unsigned char DisabledDbyte;
+ //use for dram bus 16bit or 32bit,if use 16bit mode ,should disable bit 2,3
+ //bit 0 ---use byte 0 ,1 disable byte 0,
+ //bit 1 ---use byte 1 ,1 disable byte 1,
+ //bit 2 ---use byte 2 ,1 disable byte 2,
+ //bit 3 ---use byte 3 ,1 disable byte 3,
+ unsigned char Is2Ttiming;
+ //ddr3/ddr3 use 2t timing,now only support 2t timming
+ unsigned char HdtCtrl;
+ //training information control,do not modify
+ unsigned char dram_rank_config;
+ //support Dram connection type should confirm with amlogic
+ //#define CONFIG_DDR0_16BIT_CH0 0x1 //dram total bus width 16bit only use cs0
+ //#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 //dram total bus width 16bit use cs0 cs1
+ //#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 //dram total bus width 32bit use cs0
+ //#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 //only for lpddr4,dram total bus width 32bit use chanel a cs0 cs1 chanel b cs0 cs1
+ //#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 //dram total bus width 32bit only use cs0,but high address use 16bit mode
+ //#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 //dram total bus width 32bit use cs0 cs1,but cs1 use 16bit mode ,current phy not support reserve
+ //#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7 //dram total bus width 32bit use cs0 cs1
+ //#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8 //only for lpddr4,dram total bus width 32bit use chanel a cs0 chanel b cs0
+
+ /* rsv_char0. update for diagnose type define */
+ unsigned char diagnose;
+
+ unsigned short soc_data_drv_ohm_ps1;
+ unsigned short dram_data_drv_ohm_ps1;
+ unsigned short soc_data_odt_ohm_ps1;
+ unsigned short dram_data_odt_ohm_ps1;
+ unsigned short dram_data_wr_odt_ohm_ps1;
+ //system reserve,do not modify
+ unsigned short dmem_load_size;
+ //system reserve,do not modify
+ unsigned int ddr_base_addr;
+ //system reserve,do not modify
+ unsigned int ddr_start_offset;
+ //system reserve,do not modify
+
+ unsigned short dram_cs0_size_MB;
+ //config cs0 dram size ,like 1G DRAM ,setting 1024
+ unsigned short dram_cs1_size_MB;
+ //config cs1 dram size,like 512M DRAM ,setting 512
+ /* align8 */
+
+ unsigned short training_SequenceCtrl[2];
+ //system reserve,do not modify
+ unsigned char phy_odt_config_rank[2];
+ //unsigned char rever1;
+ //unsigned char rever2;
+ unsigned short rank1_ca_vref_permil;
+ //training odt config ,only use for training
+ // [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ // [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ unsigned int dfi_odt_config;
+ //normal go status od config,use for normal status
+ //bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity.
+ //bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1.
+ //bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0.
+ //bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1.
+ //bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0.
+ //bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity.
+ //bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0.
+ //bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1.
+ //bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0.
+ //bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1.
+ unsigned short DRAMFreq[4];
+ //config dram frequency,use DRAMFreq[0],ohter reserve
+ unsigned char PllBypassEn;
+ //system reserve,do not modify
+ unsigned char ddr_rdbi_wr_enable;
+ //system reserve,do not modify
+ unsigned char ddr_rfc_type;
+ //config dram rfc type,according dram type,also can use same dram type max config
+ //#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+ //#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+ //#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+ //#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+ //#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+ //#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+ //#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+ //#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+ //#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+ //#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+ //#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+ //#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+ unsigned char enable_lpddr4x_mode;
+ //system reserve,do not modify
+ /* align8 */
+
+ unsigned int pll_ssc_mode;
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ unsigned short clk_drv_ohm;
+ //config soc clk pin signal driver stength ,select 20,30,40,60ohm
+ unsigned short cs_drv_ohm;
+ //config soc cs0 cs1 pin signal driver stength ,select 20,30,40,60ohm
+ unsigned short ac_drv_ohm;
+ //config soc normal address command pin driver stength ,select 20,30,40,60ohm
+ unsigned short soc_data_drv_ohm_p;
+ //config soc data pin pull up driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short soc_data_drv_ohm_n;
+ //config soc data pin pull down driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short soc_data_odt_ohm_p;
+ //config soc data pin odt pull up stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short soc_data_odt_ohm_n;
+ //config soc data pin odt pull down stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short dram_data_drv_ohm;
+ //config dram data pin pull up pull down driver stength,ddr3 select 34,40ohm,ddr4 select 34,48ohm,lpddr4 select 40,48,60,80,120,240ohm
+ unsigned short dram_data_odt_ohm;
+ //config dram data pin odt pull up down stength,ddr3 select 40,60,120ohm,ddr4 select 34,40,48,60,120,240ohm,lpddr4 select 40,48,60,80,120,240ohm
+ unsigned short dram_ac_odt_ohm;
+ //config dram ac pin odt pull up down stength,use for lpddr4, select 40,48,60,80,120,240ohm
+ unsigned short soc_clk_slew_rate;
+ //system reserve,do not modify
+ unsigned short soc_cs_slew_rate;
+ //system reserve,do not modify
+ unsigned short soc_ac_slew_rate;
+ //system reserve,do not modify
+ unsigned short soc_data_slew_rate;
+ //system reserve,do not modify
+ unsigned short vref_output_permil; //phy
+ //setting same with vref_dram_permil
+ unsigned short vref_receiver_permil; //soc
+ //soc init SOC receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
+ unsigned short vref_dram_permil;
+ //soc init DRAM receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
+ unsigned short max_core_timmming_frequency;
+ //use for limited ddr speed core timmming parameter,for some old dram maybe have no over speed register
+ /* align8 */
+
+ unsigned char ac_trace_delay[10];
+ unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting;
+ unsigned char lpddr4_x8_mode;
+ unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function
+ //[1],slt test parameter ,use for force delay line offset
+ //system reserve,do not modify
+ unsigned short tdqs2dq;
+ unsigned char dram_data_wr_odt_ohm;
+ unsigned char bitTimeControl_2d;
+ //system reserve,do not modify
+ /* align8 */
+ unsigned char char_rev1;
+ unsigned char char_rev2;
+ unsigned int ddr_dmc_remap[5];
+ unsigned int dram_rtt_nom_wr_park[2];
+ //system reserve,do not modify
+ /* align8 */
+ unsigned char ddr_lpddr34_ca_remap[4];
+ ////use for lpddr3 /lpddr4 ca training data byte lane remap
+ unsigned char ddr_lpddr34_dq_remap[32];
+ ////use for lpddr3 /lpddr4 ca pinmux remap
+ unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL];
+ //use for lpddr3 /lpddr4 ca pinmux remap
+ unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL];
+ unsigned char char_rev3;
+ unsigned char char_rev4;
+ ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t;
+ training_delay_set_ps_t cfg_ddr_training_delay_ps[2];
+}ddr_set_t;
+
+ddr_set_t p_ddr_set_t;
+
+
+typedef struct ddr_set_t7 {
+ unsigned int magic;
+ unsigned char fast_boot[4]; // 0 fastboot enable 1 window test margin 2 auto offset after window test 3 auto window test
+ //unsigned int rsv_int0;
+ unsigned int ddr_func;
+ unsigned char board_id;
+ //board id reserve,,do not modify
+ unsigned char version;
+ // firmware reserve version,,do not modify
+ unsigned char DramType;
+ //support DramType should confirm with amlogic
+ //#define CONFIG_DDR_TYPE_DDR3 0
+ //#define CONFIG_DDR_TYPE_DDR4 1
+ //#define CONFIG_DDR_TYPE_LPDDR4 2
+ //#define CONFIG_DDR_TYPE_LPDDR3 3
+ //#define CONFIG_DDR_TYPE_LPDDR2 4
+ //#define CONFIG_DDR_TYPE_LPDDR4x 5
+ unsigned char DisabledDbyte[2]; //ch0 and ch1
+ //use for dram bus 16bit or 32bit,if use 16bit mode ,should disable bit 2,3
+ //bit 0 ---cs0 use byte 0 ,1 disable byte 0,
+ //bit 1 ---cs0 use byte 1 ,1 disable byte 1,
+ //bit 2 ---cs0 use byte 2 ,1 disable byte 2,
+ //bit 3 ---cs0 use byte 3 ,1 disable byte 3,
+ //bit 4 ---cs1 use byte 0 ,1 disable byte 0,
+ //bit 5 ---cs1 use byte 1 ,1 disable byte 1,
+ //bit 6 ---cs1 use byte 2 ,1 disable byte 2,
+ //bit 7 ---cs1 use byte 3 ,1 disable byte 3,
+ unsigned char Is2Ttiming;
+ //ddr3/ddr3 use 2t timing,now only support 2t timming
+ unsigned char HdtCtrl;
+ //training information control,do not modify
+ unsigned char dram_rank_config;
+ //support Dram connection type should confirm with amlogic
+ //#define CONFIG_DDR0_16BIT_CH0 0x1 //dram total bus width 16bit only use cs0
+ //#define CONFIG_DDR0_16BIT_RANK01_CH0 0x4 //dram total bus width 16bit use cs0 cs1
+ //#define CONFIG_DDR0_32BIT_RANK0_CH0 0x2 //dram total bus width 32bit use cs0
+ //#define CONFIG_DDR0_32BIT_RANK01_CH01 0x3 //only for lpddr4,dram total bus width 32bit use chanel a cs0 cs1 chanel b cs0 cs1
+ //#define CONFIG_DDR0_32BIT_16BIT_RANK0_CH0 0x5 //dram total bus width 32bit only use cs0,but high address use 16bit mode
+ //#define CONFIG_DDR0_32BIT_16BIT_RANK01_CH0 0x6 //dram total bus width 32bit use cs0 cs1,but cs1 use 16bit mode ,current phy not support reserve
+ //#define CONFIG_DDR0_32BIT_RANK01_CH0 0x7 //dram total bus width 32bit use cs0 cs1
+ //#define CONFIG_DDR0_32BIT_RANK0_CH01 0x8 //only for lpddr4,dram total bus width 32bit use chanel a cs0 chanel b cs0
+
+ /* rsv_char0. update for diagnose type define */
+ //unsigned char diagnose;
+
+ unsigned short soc_data_drv_ohm_ps1;
+ unsigned short dram_data_drv_ohm_ps1;
+ unsigned short soc_data_odt_ohm_ps1;
+ unsigned short dram_data_odt_ohm_ps1;
+ unsigned short dram_data_wr_odt_ohm_ps1;
+#if 0
+ /* imem/dmem define */
+ unsigned int imem_load_addr;
+ //system reserve,do not modify
+ unsigned int dmem_load_addr;
+ //system reserve,do not modify
+ unsigned short imem_load_size;
+#endif
+ //system reserve,do not modify
+ unsigned short soc_data_drv_ohm_ffe; //dmem_load_size;
+ //system reserve,do not modify
+ unsigned int ddr_base_addr;
+ //system reserve,do not modify
+ unsigned int ddr_start_offset;
+ //system reserve,do not modify
+
+ unsigned short dram_ch0_size_MB;
+ //config cs0 dram size ,like 1G DRAM ,setting 1024
+ unsigned short dram_ch1_size_MB;
+ //config cs1 dram size,like 512M DRAM ,setting 512
+ /* align8 */
+
+ unsigned short training_SequenceCtrl[2];
+ //system reserve,do not modify
+ unsigned char phy_odt_config_rank[2];
+ //unsigned char rever1;
+ //unsigned char rever2;
+ unsigned short rank1_ca_vref_permil;
+ //training odt config ,only use for training
+ // [0]Odt pattern for accesses targeting rank 0. [3:0] is used for write ODT [7:4] is used for read ODT
+ // [1]Odt pattern for accesses targeting rank 1. [3:0] is used for write ODT [7:4] is used for read ODT
+ unsigned int dfi_odt_config;
+ //normal go status od config,use for normal status
+ //bit 12. rank1 ODT default. default vulue for ODT[1] pins if theres no read/write activity.
+ //bit 11. rank1 ODT write sel. enable ODT[1] if there's write occur in rank1.
+ //bit 10. rank1 ODT write nsel. enable ODT[1] if theres's write occur in rank0.
+ //bit 9. rank1 odt read sel. enable ODT[1] if there's read occur in rank1.
+ //bit 8. rank1 odt read nsel. enable ODT[1] if there's read occure in rank0.
+ //bit 4. rank0 ODT default. default vulue for ODT[0] pins if theres no read/write activity.
+ //bit 3. rank0 ODT write sel. enable ODT[0] if there's write occur in rank0.
+ //bit 2. rank0 ODT write nsel. enable ODT[0] if theres's write occur in rank1.
+ //bit 1. rank0 odt read sel. enable ODT[0] if there's read occur in rank0.
+ //bit 0. rank0 odt read nsel. enable ODT[0] if there's read occure in rank1.
+ unsigned short DRAMFreq[4];
+ //config dram frequency,use DRAMFreq[0],ohter reserve
+ unsigned char PllBypassEn;
+ //system reserve,do not modify
+ unsigned char ddr_rdbi_wr_enable;
+ //system reserve,do not modify
+ unsigned char ddr_rfc_type;
+ //config dram rfc type,according dram type,also can use same dram type max config
+ //#define DDR_RFC_TYPE_DDR3_512Mbx1 0
+ //#define DDR_RFC_TYPE_DDR3_512Mbx2 1
+ //#define DDR_RFC_TYPE_DDR3_512Mbx4 2
+ //#define DDR_RFC_TYPE_DDR3_512Mbx8 3
+ //#define DDR_RFC_TYPE_DDR3_512Mbx16 4
+ //#define DDR_RFC_TYPE_DDR4_2Gbx1 5
+ //#define DDR_RFC_TYPE_DDR4_2Gbx2 6
+ //#define DDR_RFC_TYPE_DDR4_2Gbx4 7
+ //#define DDR_RFC_TYPE_DDR4_2Gbx8 8
+ //#define DDR_RFC_TYPE_LPDDR4_2Gbx1 9
+ //#define DDR_RFC_TYPE_LPDDR4_3Gbx1 10
+ //#define DDR_RFC_TYPE_LPDDR4_4Gbx1 11
+ unsigned char enable_lpddr4x_mode;
+ //system reserve,do not modify
+ /* align8 */
+
+ unsigned int pll_ssc_mode;
+ //
+ /* pll ssc config:
+ *
+ * pll_ssc_mode = (1<<20) | (1<<8) | ([strength] << 4) | [mode],
+ * ppm = strength * 500
+ * mode: 0=center, 1=up, 2=down
+ *
+ * eg:
+ * 1. config 1000ppm center ss. then mode=0, strength=2
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (2 << 4) | 0,
+ * 2. config 3000ppm down ss. then mode=2, strength=6
+ * .pll_ssc_mode = (1<<20) | (1<<8) | (6 << 4) | 2,
+ */
+ unsigned short clk_drv_ohm;
+ //config soc clk pin signal driver stength ,select 20,30,40,60ohm
+ unsigned short cs_drv_ohm;
+ //config soc cs0 cs1 pin signal driver stength ,select 20,30,40,60ohm
+ unsigned short ac_drv_ohm;
+ //config soc normal address command pin driver stength ,select 20,30,40,60ohm
+ unsigned short soc_data_drv_ohm_p;
+ //config soc data pin pull up driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short soc_data_drv_ohm_n;
+ //config soc data pin pull down driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short soc_data_odt_ohm_p;
+ //config soc data pin odt pull up stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short soc_data_odt_ohm_n;
+ //config soc data pin odt pull down stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned short dram_data_drv_ohm;
+ //config dram data pin pull up pull down driver stength,ddr3 select 34,40ohm,ddr4 select 34,48ohm,lpddr4 select 40,48,60,80,120,240ohm
+ unsigned short dram_data_odt_ohm;
+ //config dram data pin odt pull up down stength,ddr3 select 40,60,120ohm,ddr4 select 34,40,48,60,120,240ohm,lpddr4 select 40,48,60,80,120,240ohm
+ unsigned short dram_ac_odt_ohm;
+ //config dram ac pin odt pull up down stength,use for lpddr4, select 40,48,60,80,120,240ohm
+ unsigned short soc_clk_slew_rate;
+ //system reserve,do not modify
+ unsigned short soc_cs_slew_rate;
+ //system reserve,do not modify
+ unsigned short soc_ac_slew_rate;
+ //system reserve,do not modify
+ unsigned short soc_data_slew_rate;
+ //system reserve,do not modify
+ unsigned short vref_output_permil; //phy
+ //setting same with vref_dram_permil
+ unsigned short vref_receiver_permil; //soc
+ //soc init SOC receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
+ unsigned short vref_dram_permil;
+ //soc init DRAM receiver vref ,config like 500 means 0.5VDDQ,take care ,please follow SI
+ unsigned short max_core_timmming_frequency;
+ //use for limited ddr speed core timmming parameter,for some old dram maybe have no over speed register
+ /* align8 */
+
+ unsigned char ac_trace_delay[10];
+ unsigned char lpddr4_dram_vout_voltage_1_3_2_5_setting;
+ //use for lpddr4 read vout voltage setting 0 --->2/5VDDQ ,1--->1/3VDDQ
+ unsigned char lpddr4_x8_mode;
+ unsigned char slt_test_function[2]; //[0] slt test function enable,bit 0 enable 4 frequency scan,bit 1 enable force delay line offset ,bit 7 enable skip training function
+ //[1],slt test parameter ,use for force delay line offset
+ //system reserve,do not modify
+ unsigned short tdqs2dq;
+ unsigned char dram_data_wr_odt_ohm;
+ unsigned char bitTimeControl_2d;
+ //system reserve,do not modify
+ /* align8 */
+ unsigned char char_rev1;
+ unsigned char training_offset; //char_rev2;
+ unsigned int ddr_dmc_remap[5];
+ unsigned int dram_rtt_nom_wr_park[2];
+ //system reserve,do not modify
+ /* align8 */
+ unsigned char ddr_lpddr34_ca_remap[4];
+ ////use for lpddr3 /lpddr4 ca training data byte lane remap
+ unsigned char ddr_lpddr34_dq_remap[32];
+ ////use for lpddr3 /lpddr4 ca pinmux remap
+ unsigned char ac_pinmux[DWC_AC_PINMUX_TOTAL];
+ //use for lpddr3 /lpddr4 ca pinmux remap
+ unsigned char dfi_pinmux[DWC_DFI_PINMUX_TOTAL];
+ unsigned char char_rev3;
+ unsigned char char_rev4;
+ ddr_phy_common_extra_set_t cfg_ddr_phy_common_extra_set_t;
+ training_delay_set_ps_t cfg_ddr_training_delay_ps[2];
+
+ //override read bit delay
+}ddr_set_t7;
+
+ddr_set_t7 p_ddr_set_t7;
+
+#ifndef _SHA256_H_DDR
+#define _SHA256_H_DDR
+
+#define SHA256_SUM_LEN 32
+#define SHA256_DER_LEN 19
+
+/* Reset watchdog each time we process this many bytes */
+#define CHUNKSZ_SHA256 (64 * 1024)
+
+typedef struct {
+ uint32_t total[2];
+ uint32_t state[8];
+ uint8_t buffer[64];
+} sha256_context_ddr;
+
+const uint8_t sha256_der_prefix_ddr[SHA256_DER_LEN] =
+{
+ 0x30, 0x31, 0x30, 0x0d, 0x06, 0x09, 0x60, 0x86,
+ 0x48, 0x01, 0x65, 0x03, 0x04, 0x02, 0x01, 0x05,
+ 0x00, 0x04, 0x20
+};
+
+/*
+ * 32-bit integer manipulation macros (big endian)
+ */
+#ifndef GET_UINT32_BE
+#define GET_UINT32_BE(n, b, i) { \
+ (n) = ((unsigned long)(b)[(i)] << 24) \
+ | ((unsigned long)(b)[(i) + 1] << 16) \
+ | ((unsigned long)(b)[(i) + 2] << 8) \
+ | ((unsigned long)(b)[(i) + 3]); \
+}
+#endif
+#ifndef PUT_UINT32_BE
+#define PUT_UINT32_BE(n, b, i) { \
+ (b)[(i)] = (unsigned char)((n) >> 24); \
+ (b)[(i) + 1] = (unsigned char)((n) >> 16); \
+ (b)[(i) + 2] = (unsigned char)((n) >> 8); \
+ (b)[(i) + 3] = (unsigned char)((n)); \
+}
+#endif
+
+void sha256_starts_internal(sha256_context_ddr *ctx)
+{
+ ctx->total[0] = 0;
+ ctx->total[1] = 0;
+
+ ctx->state[0] = 0x6A09E667;
+ ctx->state[1] = 0xBB67AE85;
+ ctx->state[2] = 0x3C6EF372;
+ ctx->state[3] = 0xA54FF53A;
+ ctx->state[4] = 0x510E527F;
+ ctx->state[5] = 0x9B05688C;
+ ctx->state[6] = 0x1F83D9AB;
+ ctx->state[7] = 0x5BE0CD19;
+}
+
+static void sha256_process_internal(sha256_context_ddr *ctx, const uint8_t data[64])
+{
+ uint32_t temp1, temp2;
+ uint32_t W[64];
+ uint32_t A, B, C, D, E, F, G, H;
+
+ GET_UINT32_BE(W[0], data, 0);
+ GET_UINT32_BE(W[1], data, 4);
+ GET_UINT32_BE(W[2], data, 8);
+ GET_UINT32_BE(W[3], data, 12);
+ GET_UINT32_BE(W[4], data, 16);
+ GET_UINT32_BE(W[5], data, 20);
+ GET_UINT32_BE(W[6], data, 24);
+ GET_UINT32_BE(W[7], data, 28);
+ GET_UINT32_BE(W[8], data, 32);
+ GET_UINT32_BE(W[9], data, 36);
+ GET_UINT32_BE(W[10], data, 40);
+ GET_UINT32_BE(W[11], data, 44);
+ GET_UINT32_BE(W[12], data, 48);
+ GET_UINT32_BE(W[13], data, 52);
+ GET_UINT32_BE(W[14], data, 56);
+ GET_UINT32_BE(W[15], data, 60);
+
+#define SHR(x, n) ((x & 0xFFFFFFFF) >> n)
+#define ROTR(x, n) (SHR(x, n) | (x << (32 - n)))
+
+#define S0(x) (ROTR(x, 7) ^ ROTR(x, 18) ^ SHR(x, 3))
+#define S1(x) (ROTR(x, 17) ^ ROTR(x, 19) ^ SHR(x, 10))
+
+#define S2(x) (ROTR(x, 2) ^ ROTR(x, 13) ^ ROTR(x, 22))
+#define S3(x) (ROTR(x, 6) ^ ROTR(x, 11) ^ ROTR(x, 25))
+
+#define F0(x, y, z) ((x & y) | (z & (x | y)))
+#define F1(x, y, z) (z ^ (x & (y ^ z)))
+
+#define R(t) \
+ ( \
+ W[t] = S1(W[t - 2]) + W[t - 7] + \
+ S0(W[t - 15]) + W[t - 16] \
+ )
+
+#define P(a, b, c, d, e, f, g, h, x, K) { \
+ temp1 = h + S3(e) + F1(e, f, g) + K + x; \
+ temp2 = S2(a) + F0(a, b, c); \
+ d += temp1; h = temp1 + temp2; \
+}
+
+ A = ctx->state[0];
+ B = ctx->state[1];
+ C = ctx->state[2];
+ D = ctx->state[3];
+ E = ctx->state[4];
+ F = ctx->state[5];
+ G = ctx->state[6];
+ H = ctx->state[7];
+
+ P(A, B, C, D, E, F, G, H, W[0], 0x428A2F98);
+ P(H, A, B, C, D, E, F, G, W[1], 0x71374491);
+ P(G, H, A, B, C, D, E, F, W[2], 0xB5C0FBCF);
+ P(F, G, H, A, B, C, D, E, W[3], 0xE9B5DBA5);
+ P(E, F, G, H, A, B, C, D, W[4], 0x3956C25B);
+ P(D, E, F, G, H, A, B, C, W[5], 0x59F111F1);
+ P(C, D, E, F, G, H, A, B, W[6], 0x923F82A4);
+ P(B, C, D, E, F, G, H, A, W[7], 0xAB1C5ED5);
+ P(A, B, C, D, E, F, G, H, W[8], 0xD807AA98);
+ P(H, A, B, C, D, E, F, G, W[9], 0x12835B01);
+ P(G, H, A, B, C, D, E, F, W[10], 0x243185BE);
+ P(F, G, H, A, B, C, D, E, W[11], 0x550C7DC3);
+ P(E, F, G, H, A, B, C, D, W[12], 0x72BE5D74);
+ P(D, E, F, G, H, A, B, C, W[13], 0x80DEB1FE);
+ P(C, D, E, F, G, H, A, B, W[14], 0x9BDC06A7);
+ P(B, C, D, E, F, G, H, A, W[15], 0xC19BF174);
+ P(A, B, C, D, E, F, G, H, R(16), 0xE49B69C1);
+ P(H, A, B, C, D, E, F, G, R(17), 0xEFBE4786);
+ P(G, H, A, B, C, D, E, F, R(18), 0x0FC19DC6);
+ P(F, G, H, A, B, C, D, E, R(19), 0x240CA1CC);
+ P(E, F, G, H, A, B, C, D, R(20), 0x2DE92C6F);
+ P(D, E, F, G, H, A, B, C, R(21), 0x4A7484AA);
+ P(C, D, E, F, G, H, A, B, R(22), 0x5CB0A9DC);
+ P(B, C, D, E, F, G, H, A, R(23), 0x76F988DA);
+ P(A, B, C, D, E, F, G, H, R(24), 0x983E5152);
+ P(H, A, B, C, D, E, F, G, R(25), 0xA831C66D);
+ P(G, H, A, B, C, D, E, F, R(26), 0xB00327C8);
+ P(F, G, H, A, B, C, D, E, R(27), 0xBF597FC7);
+ P(E, F, G, H, A, B, C, D, R(28), 0xC6E00BF3);
+ P(D, E, F, G, H, A, B, C, R(29), 0xD5A79147);
+ P(C, D, E, F, G, H, A, B, R(30), 0x06CA6351);
+ P(B, C, D, E, F, G, H, A, R(31), 0x14292967);
+ P(A, B, C, D, E, F, G, H, R(32), 0x27B70A85);
+ P(H, A, B, C, D, E, F, G, R(33), 0x2E1B2138);
+ P(G, H, A, B, C, D, E, F, R(34), 0x4D2C6DFC);
+ P(F, G, H, A, B, C, D, E, R(35), 0x53380D13);
+ P(E, F, G, H, A, B, C, D, R(36), 0x650A7354);
+ P(D, E, F, G, H, A, B, C, R(37), 0x766A0ABB);
+ P(C, D, E, F, G, H, A, B, R(38), 0x81C2C92E);
+ P(B, C, D, E, F, G, H, A, R(39), 0x92722C85);
+ P(A, B, C, D, E, F, G, H, R(40), 0xA2BFE8A1);
+ P(H, A, B, C, D, E, F, G, R(41), 0xA81A664B);
+ P(G, H, A, B, C, D, E, F, R(42), 0xC24B8B70);
+ P(F, G, H, A, B, C, D, E, R(43), 0xC76C51A3);
+ P(E, F, G, H, A, B, C, D, R(44), 0xD192E819);
+ P(D, E, F, G, H, A, B, C, R(45), 0xD6990624);
+ P(C, D, E, F, G, H, A, B, R(46), 0xF40E3585);
+ P(B, C, D, E, F, G, H, A, R(47), 0x106AA070);
+ P(A, B, C, D, E, F, G, H, R(48), 0x19A4C116);
+ P(H, A, B, C, D, E, F, G, R(49), 0x1E376C08);
+ P(G, H, A, B, C, D, E, F, R(50), 0x2748774C);
+ P(F, G, H, A, B, C, D, E, R(51), 0x34B0BCB5);
+ P(E, F, G, H, A, B, C, D, R(52), 0x391C0CB3);
+ P(D, E, F, G, H, A, B, C, R(53), 0x4ED8AA4A);
+ P(C, D, E, F, G, H, A, B, R(54), 0x5B9CCA4F);
+ P(B, C, D, E, F, G, H, A, R(55), 0x682E6FF3);
+ P(A, B, C, D, E, F, G, H, R(56), 0x748F82EE);
+ P(H, A, B, C, D, E, F, G, R(57), 0x78A5636F);
+ P(G, H, A, B, C, D, E, F, R(58), 0x84C87814);
+ P(F, G, H, A, B, C, D, E, R(59), 0x8CC70208);
+ P(E, F, G, H, A, B, C, D, R(60), 0x90BEFFFA);
+ P(D, E, F, G, H, A, B, C, R(61), 0xA4506CEB);
+ P(C, D, E, F, G, H, A, B, R(62), 0xBEF9A3F7);
+ P(B, C, D, E, F, G, H, A, R(63), 0xC67178F2);
+
+ ctx->state[0] += A;
+ ctx->state[1] += B;
+ ctx->state[2] += C;
+ ctx->state[3] += D;
+ ctx->state[4] += E;
+ ctx->state[5] += F;
+ ctx->state[6] += G;
+ ctx->state[7] += H;
+}
+
+void sha256_update_internal(sha256_context_ddr *ctx, const uint8_t *input, uint32_t length)
+{
+ uint32_t left, fill;
+
+ if (!length)
+ return;
+
+ left = ctx->total[0] & 0x3F;
+ fill = 64 - left;
+
+ ctx->total[0] += length;
+ ctx->total[0] &= 0xFFFFFFFF;
+
+ if (ctx->total[0] < length)
+ ctx->total[1]++;
+
+ if (left && length >= fill) {
+ memcpy((void *)(ctx->buffer + left), (void *)input, fill);
+ sha256_process_internal(ctx, ctx->buffer);
+ length -= fill;
+ input += fill;
+ left = 0;
+ }
+
+ while (length >= 64) {
+ sha256_process_internal(ctx, input);
+ length -= 64;
+ input += 64;
+ }
+
+ if (length)
+ memcpy((void *)(ctx->buffer + left), (void *)input, length);
+}
+
+static uint8_t sha256_padding[64] =
+{
+ 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
+};
+
+void sha256_finish_internal(sha256_context_ddr *ctx, uint8_t digest[32])
+{
+ uint32_t last, padn;
+ uint32_t high, low;
+ uint8_t msglen[8];
+
+ high = ((ctx->total[0] >> 29)
+ | (ctx->total[1] << 3));
+ low = (ctx->total[0] << 3);
+
+ PUT_UINT32_BE(high, msglen, 0);
+ PUT_UINT32_BE(low, msglen, 4);
+
+ last = ctx->total[0] & 0x3F;
+ padn = (last < 56) ? (56 - last) : (120 - last);
+
+ sha256_update_internal(ctx, sha256_padding, padn);
+ sha256_update_internal(ctx, msglen, 8);
+
+ PUT_UINT32_BE(ctx->state[0], digest, 0);
+ PUT_UINT32_BE(ctx->state[1], digest, 4);
+ PUT_UINT32_BE(ctx->state[2], digest, 8);
+ PUT_UINT32_BE(ctx->state[3], digest, 12);
+ PUT_UINT32_BE(ctx->state[4], digest, 16);
+ PUT_UINT32_BE(ctx->state[5], digest, 20);
+ PUT_UINT32_BE(ctx->state[6], digest, 24);
+ PUT_UINT32_BE(ctx->state[7], digest, 28);
+}
+
+/*
+ * Output = SHA-256( input buffer ). Trigger the watchdog every 'chunk_sz'
+ * bytes of input processed.
+ */
+void sha256_csum_wd_internal(const unsigned char *input, unsigned int ilen,
+ unsigned char *output, unsigned int chunk_sz)
+{
+ sha256_context_ddr ctx;
+
+ sha256_starts_internal(&ctx);
+ sha256_update_internal(&ctx, input, ilen);
+ sha256_finish_internal(&ctx, output);
+}
+#endif
+
+typedef struct ddr_sha_s {
+ unsigned char sha2[SHA256_SUM_LEN];
+ ddr_set_t ddrs;
+ unsigned char sha_chip_id[MESON_CPU_CHIP_ID_SIZE];
+}ddr_sha_t;
+
+ddr_sha_t ddr_sha = { { 0 } };
+ddr_set_t *ddr_set_t_p_arrary = &ddr_sha.ddrs;
+
+typedef struct ddr_sha_s_c2 {
+ unsigned char sha2[SHA256_SUM_LEN];
+ ddr_set_t_c2 ddrs;
+ unsigned char sha_chip_id[MESON_CPU_CHIP_ID_SIZE];
+}ddr_sha_t_c2;
+
+ddr_sha_t_c2 ddr_sha_c2 = { { 0 } };
+ddr_set_t_c2 *ddr_set_t_p_arrary_c2 = &ddr_sha_c2.ddrs;
+ddr_set_t_c2 *ddr_set_t_p = NULL;
+
+int check_base_address(void)
+{
+ ddr_set_t_p = (ddr_set_t_c2 *)(ddr_set_t_p_arrary_c2);
+ unsigned int table_max = (sizeof(__ddr_base_address_table)) / (sizeof(ddr_base_address_table_t));
+ unsigned int table_index = 0;
+ char chip_id = 0;
+ chip_id = ddr_get_chip_id();
+ p_ddr_base = (ddr_base_address_table_t *)(&__ddr_base_address_table);
+
+ printf("\ntable_max=%08x,p_ddr_base_add=%08x,chip_id=%08x", table_max, (unsigned int)(unsigned long)p_ddr_base, chip_id);
+ if (chip_id == 0)
+ chip_id = CHIP_ID_MASK;
+ if (chip_id) {
+ for (table_index = 0; table_index < table_max; table_index++) { //p_ddr_base=(p_ddr_base+1);
+ printf("\ntable_index=%08x,p_ddr_base_add=%08x,(p_ddr_base->chip_id==%08x",
+ table_index, (unsigned int)(unsigned long)p_ddr_base, (p_ddr_base->chip_id));
+ if ((p_ddr_base->chip_id == chip_id) && (chip_id < CHIP_ID_MASK)) {
+ printf("\nfind match chip id=0x%08x ,%s", chip_id, p_ddr_base->soc_family_name);
+ break;
+ } else {
+ printf("\nno find match chip id=0x%08x, ,%s will use default value", chip_id, p_ddr_base->soc_family_name);
+ }
+ p_ddr_base = (p_ddr_base + 1);
+ }
+ }
+
+ int count = 0;
+ for (count = 0; count < 12; count++)
+ ddr_sha.sha_chip_id[count] = global_chip_id[count];
+
+ if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T7))
+ {
+ phy_base_add[0] = p_ddr_base->ddr_phy_base_address;
+ phy_base_add[1] = p_ddr_base->ddr_phy_base_address_1;
+ ddr_dmc_sticky[0] = p_ddr_base->ddr_dmc_sticky0;
+ ddr_dmc_sticky[1] = p_ddr_base->ddr_dmc_sticky0_1;
+ ddr_dmc_apd_address[0] = p_ddr_base->ddr_dmc_apd_address;
+ ddr_dmc_apd_address[1] = p_ddr_base->ddr_dmc_apd_address_1;
+ ddr_dmc_asr_address[0] = p_ddr_base->ddr_dmc_asr_address;
+ ddr_dmc_asr_address[1] = p_ddr_base->ddr_dmc_asr_address_1;
+ dmc_retraining_ctrl_address[0] = p_ddr_base->ddr_dmc_lpdd4_retraining_address;
+ dmc_retraining_ctrl_address[1] = p_ddr_base->ddr_dmc_lpdd4_retraining_address_1;
+ }
+ return (unsigned int)(unsigned long)(p_ddr_base);
+}
+
+void dmc_change_channel(uint32_t ch)
+{
+ dmc_ddr_config_channel_id = ch;
+ //dmc_ddr_config_channel_id=0;
+ p_ddr_base->ddr_phy_base_address = phy_base_add[dmc_ddr_config_channel_id];
+ p_ddr_base->ddr_dmc_sticky0 = ddr_dmc_sticky[dmc_ddr_config_channel_id];
+ p_ddr_base->ddr_dmc_lpdd4_retraining_address=dmc_retraining_ctrl_address[dmc_ddr_config_channel_id];
+ p_ddr_base->ddr_dmc_apd_address=ddr_dmc_apd_address[dmc_ddr_config_channel_id];
+ p_ddr_base->ddr_dmc_asr_address=ddr_dmc_asr_address[dmc_ddr_config_channel_id];
+}
+
+char *itoa_ddr_test(int num, char *str, int radix)
+{
+ printf("\nitoa_ddr_test 1\n");
+ char index[] = "0123456789ABCDEFGHIJKLMNOPQRSTUVWXYZ";
+ unsigned unum;
+ char temp;
+ int i = 0, j, k;
+
+ if (radix == 10 && num < 0) {
+ unum = (unsigned)-num;
+ str[i++] = '-';
+ } else {
+ unum = (unsigned)num;
+ }
+
+ printf("\nitoa_ddr_test 2\n");
+ printf("\nunum=0x%08x\n", unum);
+ printf("\nunum2=0x%08x\n", (unum % (unsigned)radix));
+ printf("\nradix=0x%08x\n", radix);
+ str[0] = index[0];
+ printf("\nitoa_ddr_test 22\n");
+ unum /= radix;
+ printf("\nitoa_ddr_test 23\n");
+ do {
+ str[i++] = index[unum % (unsigned)radix];
+ unum /= radix;
+ } while (unum);
+ printf("\nitoa_ddr_test 3\n");
+ str[i] = '\0';
+
+ if (str[0] == '-')
+ k = 1;
+ else
+ k = 0;
+ printf("\nitoa_ddr_test 4\n");
+ for (j = k; j <= (i - 1) / 2; j++) {
+ temp = str[j];
+ str[j] = str[i - 1 + k - j];
+ str[i - 1 + k - j] = temp;
+ }
+ return str;
+}
+
+int TOLOWER(int ch)
+{
+ if ((unsigned int)(ch - 'A') < 26u)
+ ch += 'a' - 'A';
+ return ch;
+}
+
+int isxdigit(int ch)
+{
+ return (unsigned int)(ch - '0') < 10u
+ || (unsigned int)((ch | 0x20) - 'a') < 6u;
+}
+
+int isdigit(int ch)
+{
+ return (unsigned int)(ch - '0') < 10u;
+}
+
+unsigned int simple_guess_base(const char *cp)
+{
+ if (cp[0] == '0') {
+ if (TOLOWER(cp[1]) == 'x' && isxdigit(cp[2]))
+ return 16;
+ else
+ return 10;
+ } else {
+ return 10;
+ }
+}
+
+unsigned int simple_strtoull_ddr(const char *cp, char **endp, unsigned int base)
+{
+ unsigned int result = 0;
+
+ if (cp == NULL) //jiaxing add 20170616
+ return 0;
+ if (!base)
+ base = simple_guess_base(cp);
+ if (base == 16 && cp[0] == '0' && TOLOWER(cp[1]) == 'x')
+ cp += 2;
+ if (base == 10)
+ while ((*cp) == '0')
+ cp++;
+ while (isxdigit(*cp)) {
+ unsigned int value;
+ value = isdigit(*cp) ? *cp - '0' : TOLOWER(*cp) - 'a' + 10;
+ if (value >= base)
+ break;
+ result = result * base + value;
+ cp++;
+ }
+ if (endp)
+ *endp = (char *)cp;
+ return result;
+}
+
+unsigned int env_to_a_num(const char *env_name)
+{
+ char *str_buf = NULL;
+ char buf[48];
+
+ str_buf = (char *)(&buf);
+ memset(str_buf, 0, sizeof(buf));
+ printf("sizeof(str_buf)==%d\n", (unsigned int)(sizeof(buf)));
+ str_buf = getenv(env_name);
+ unsigned int a_num = 0;
+ char *endp;
+
+ printf("str==%s\n", str_buf);
+
+ a_num = simple_strtoull_ddr(str_buf, &endp, 0);
+ printf("%s==0x%08x\n", str_buf, a_num);
+
+ return a_num;
+}
+
+unsigned int a_num_to_env(const char *env_name, unsigned int *a_num)
+{
+ char *str_buf = NULL;
+ char buf[1024];
+
+ str_buf = (char *)(&buf);
+ memset(str_buf, 0, sizeof(buf));
+ printf("sizeof(str_buf)==%d\n", (unsigned int)(sizeof(buf)));
+ str_buf = getenv(env_name);
+
+ printf("str==%s\n", str_buf);
+
+ sprintf(buf, "0x%08x", *a_num);
+
+ printf("%s==0x%08x", buf, *a_num);
+ setenv(env_name, buf);
+
+ run_command("save", 0);
+ return 1;
+}
+
+unsigned int env_to_num(const char *env_name, unsigned int *num_arry)
+{
+ char *str_buf = NULL;
+ char buf[1024];
+ unsigned int str_to_numarry[48];
+
+ str_buf = (char *)(&buf);
+ memset(str_buf, 0, sizeof(buf));
+ printf("sizeof(str_buf)==%d\n", (unsigned int)(sizeof(buf)));
+ str_buf = getenv(env_name);
+
+ char *str[48];
+ char *endp;
+ int i;
+ for (i = 0; i < 48; i++)
+ str_to_numarry[i] = 0;
+ printf("str==%s\n", str_buf);
+ for (i = 0; i < 48; i++) {
+ str[i] = strsep(&str_buf, ";");
+ if (str[i] == NULL)
+ break;
+ str_to_numarry[i] = simple_strtoull_ddr(str[i], &endp, 0);
+ }
+ for (i = 0; i < 48; i++) {
+ printf("str_to_numarry[%d]==%d\n", i, str_to_numarry[i]);
+ num_arry[i] = str_to_numarry[i];
+ }
+ return 1;
+}
+
+unsigned int num_to_env(const char *env_name, unsigned int *num_arry)
+{
+ char *str_buf = NULL;
+ char buf[1024];
+ int i;
+
+ str_buf = (char *)(&buf);
+ memset(str_buf, 0, sizeof(buf));
+ printf("sizeof(str_buf)==%d\n", (unsigned int)(sizeof(buf)));
+ str_buf = getenv(env_name);
+
+ printf("str==%s\n", str_buf);
+
+
+ sprintf(buf, "0x%08x", num_arry[0]);
+ for (i = 1; i < 48; i++) {
+ sprintf(buf, "%s;0x%08x", buf, num_arry[i]);
+ printf("%d %d\n", i, num_arry[i]);
+ }
+ printf("%s", buf);
+ setenv(env_name, buf);
+
+ run_command("save", 0);
+ return 1;
+}
+
+#define TDATA32F 0xffffffff
+#define TDATA32A 0xaaaaaaaa
+#define TDATA325 0x55555555
+
+#define DMC_STICKY_MAGIC_0 0x12345678
+#define DMC_STICKY_MAGIC_1 0xabcdbead
+#define DMC_STICKY_UBOOT_WINDOW_MAGIC_1 0x22
+#define DMC_STICKY_AUTO_TEST_CMD_INDEX_MAGIC_1 0x33
+
+unsigned int dmc_sticky[64];
+unsigned int sticky_reg_base_add = 0;
+
+unsigned int global_boot_times = 0;
+unsigned int watchdog_time_s = 20;
+unsigned int global_ddr_clk = 1;
+unsigned int bdlr_100step = 0;
+unsigned int ui_1_32_100step = 0;
+unsigned int error_count = 0;
+unsigned int error_outof_count_flag = 0;
+unsigned int copy_test_flag = 0;
+unsigned int training_pattern_flag = 0;
+unsigned int test_start_addr = 0x1080000;
+
+unsigned int dq_lcd_bdl_value_aclcdlr_org_a;
+unsigned int dq_lcd_bdl_value_bdlr0_org_a;
+unsigned int dq_lcd_bdl_value_aclcdlr_min_a;
+unsigned int dq_lcd_bdl_value_bdlr0_min_a;
+unsigned int dq_lcd_bdl_value_aclcdlr_max_a;
+unsigned int dq_lcd_bdl_value_bdlr0_max_a;
+unsigned int dq_lcd_bdl_value_aclcdlr_status_a;
+unsigned int dq_lcd_bdl_value_bdlr0_status_a;
+
+unsigned int dq_lcd_bdl_value_aclcdlr_org_b;
+unsigned int dq_lcd_bdl_value_bdlr0_org_b;
+unsigned int dq_lcd_bdl_value_aclcdlr_min_b;
+unsigned int dq_lcd_bdl_value_bdlr0_min_b;
+unsigned int dq_lcd_bdl_value_aclcdlr_max_b;
+unsigned int dq_lcd_bdl_value_bdlr0_max_b;
+
+unsigned int dq_lcd_bdl_value_wdq_org_a[4];
+unsigned int dq_lcd_bdl_value_rdqs_org_a[4];
+unsigned int dq_lcd_bdl_value_wdq_min_a[4];
+unsigned int dq_lcd_bdl_value_wdq_max_a[4];
+unsigned int dq_lcd_bdl_value_rdqs_min_a[4];
+unsigned int dq_lcd_bdl_value_rdqs_max_a[4];
+unsigned int dq_lcd_bdl_value_wdq_status_a[4];
+unsigned int dq_lcd_bdl_value_rdqs_status_a[4];
+
+unsigned int dq_lcd_bdl_value_wdq_org_b[4];
+unsigned int dq_lcd_bdl_value_rdqs_org_b[4];
+unsigned int dq_lcd_bdl_value_wdq_min_b[4];
+unsigned int dq_lcd_bdl_value_wdq_max_b[4];
+unsigned int dq_lcd_bdl_value_rdqs_min_b[4];
+unsigned int dq_lcd_bdl_value_rdqs_max_b[4];
+unsigned int dq_lcd_bdl_value_wdq_status_b[4];
+unsigned int dq_lcd_bdl_value_rdqs_status_b[4];
+unsigned int acbdlr0_9_reg_org[10];
+unsigned int acbdlr0_9_reg_setup_max[40];
+unsigned int acbdlr0_9_reg_hold_max[40];
+unsigned int acbdlr0_9_reg_setup_time[40];
+unsigned int acbdlr0_9_reg_hold_time[40];
+unsigned int data_bdlr0_5_reg_org[28]; //4//4lane
+unsigned int bdlr0_9_reg_setup_max[24 * 4]; //4//4 lane 96 bdlr
+unsigned int bdlr0_9_reg_hold_max[24 * 4];
+unsigned int bdlr0_9_reg_setup_time[24 * 4];
+unsigned int bdlr0_9_reg_hold_time[24 * 4];
+
+unsigned int pre_fetch_enable = 0;
+
+#define readl(addr) (unsigned int)(*((volatile unsigned int *)((unsigned long)(unsigned int)addr))) //rd_reg(addr)
+#define writel(data, addr) (*((volatile unsigned int *)((unsigned long)(unsigned int)addr))) = (data) //wr_reg(addr, data)
+
+#define wr_reg(addr, data) (*((volatile unsigned int *)((unsigned long)(unsigned int)addr))) = (data) //wr_reg(addr, data)
+#define rd_reg(addr) (unsigned int)(*((volatile unsigned int *)((unsigned long)(unsigned int)addr))) //rd_reg(addr)
+
+#ifndef CONFIG_CHIP
+#define CHIP_OLD 0
+#define CHIP_TXLX 1
+#define CHIP_A113 2
+#define CHIP_G12 3
+#define CONFIG_CHIP CHIP_G12 // CHIP_OLD//
+#endif
+
+#define P_DDR_PHY_DEFAULT 0
+#define P_DDR_PHY_GX_BABY 1
+#define P_DDR_PHY_GX_TV_BABY 2
+#define P_DDR_PHY_905X 3
+
+#define P_DDR_PHY_G12 4
+#define CONFIG_DDR_PHY P_DDR_PHY_G12
+
+#define PATTERN_USE_DDR_DES
+#define USE_64BIT_POINTER
+#ifdef USE_64BIT_POINTER
+#define p_convter_int(a) (unsigned int)(unsigned long)(a)
+#define int_convter_p(a) (unsigned long)(a)
+
+#else
+#define p_convter_int(a) (unsigned int)(a)
+#define int_convter_p(a) (unsigned int)(a)
+#endif
+
+#ifdef PATTERN_USE_DDR_DES
+#define des_pattern(a, b, c, d) (des[a] ^ pattern_ ## b[c][d])
+#define des_inv_pattern(a, b, c, d) (des[a] ^ (~(pattern_ ## b[c][d])))
+#define des_xor_pattern(a, b) (a ^ b)
+#else
+#define des_pattern(a, b, c, d) (des[a] & 0) + pattern_ ## b[c][d]
+#define des_inv_pattern(a, b, c, d) (des[a] & 0) + ~(pattern_ ## b[c][d])
+#define des_xor_pattern(a, b) (a & 0 + b)
+#endif
+
+#define DDR_LCDLR_CK_USE_FAST_PATTERN
+#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
+#define DDR_PREFETCH_CACHE
+#endif
+#ifdef DDR_PREFETCH_CACHE
+#define ddr_pld_cache(P) asm ("prfm PLDL1KEEP, [%0, #376]" ::"r" (P))
+#else
+#define ddr_pld_cache(P)
+#endif
+
+#define DDR_TEST_START_ADDR 0x1080000 // 0x10000000 //CONFIG_SYS_MEMTEST_START
+#define DDR_TEST_SIZE 0x2000000
+
+#if (CONFIG_CHIP >= CHIP_TXLX)
+
+#endif
+
+#define get_us_time() (rd_reg(p_ddr_base->ee_timer_base_address)) // (readl(P_ISA_TIMERE))
+
+#define ACX_MAX 0x80
+
+//OVERRIDE_OPTION
+#define DMC_TEST_WINDOW_INDEX_ATXDLY 1
+#define DMC_TEST_WINDOW_INDEX_TXDQSDLY 2
+#define DMC_TEST_WINDOW_INDEX_RXCLKDLY 3
+#define DMC_TEST_WINDOW_INDEX_TXDQDLY 4
+#define DMC_TEST_WINDOW_INDEX_RXPBDLY 5
+#define DMC_TEST_WINDOW_INDEX_RXENDLY 6
+#define DMC_TEST_WINDOW_INDEX_RXPBDLY_2 7
+#define DMC_TEST_WINDOW_INDEX_DFIMRL 8
+#define DMC_TEST_WINDOW_INDEX_VREF 9
+#define DMC_TEST_WINDOW_INDEX_RETRAINING 10
+#define DMC_TEST_WINDOW_INDEX_EXTERA_COMMON 11
+#define DMC_TEST_WINDOW_INDEX_EXTERA_PS 12
+
+#define DMC_TEST_WINDOW_INDEX_RXCLKDLY_DAC1 12
+#define DMC_TEST_WINDOW_INDEX_RXPBDLY_DAC1 13
+#define DMC_TEST_WINDOW_INDEX_RXPBDLY_2_DAC1 14
+
+#define DMC_TEST_WINDOW_INDEX_EE_VOLTAGE 0x11
+#define DMC_TEST_WINDOW_INDEX_SOC_VREF 0x12
+#define DMC_TEST_WINDOW_INDEX_SOC_VREF_DAC1 0x13
+#define DMC_TEST_WINDOW_INDEX_DRAM_VREF 0x14
+
+#define DMC_TEST_WINDOW_INDEX_DDR3_WRITE_VREF_RANG0 0x21
+#define DMC_TEST_WINDOW_INDEX_DDR3_WRITE_VREF_RANG1 0x22
+#define DMC_TEST_WINDOW_INDEX_DDR3_READ_VREF_RANG0 0x23
+#define DMC_TEST_WINDOW_INDEX_DDR3_READ_VREF_RANG1 0x24
+
+#define DMC_TEST_WINDOW_INDEX_DDR4_WRITE_VREF_RANG0 0x31
+#define DMC_TEST_WINDOW_INDEX_DDR4_WRITE_VREF_RANG1 0x32
+#define DMC_TEST_WINDOW_INDEX_DDR4_READ_VREF_RANG0 0x33
+#define DMC_TEST_WINDOW_INDEX_DDR4_READ_VREF_RANG1 0x34
+
+#define DMC_TEST_WINDOW_INDEX_LPDDR4_WRITE_VREF_RANG0 0x41
+#define DMC_TEST_WINDOW_INDEX_LPDDR4_WRITE_VREF_RANG1 0x42
+#define DMC_TEST_WINDOW_INDEX_LPDDR4_READ_VREF_RANG0 0x43
+#define DMC_TEST_WINDOW_INDEX_LPDDR4_READ_VREF_RANG1 0x44
+
+#define DMC_TEST_WINDOW_INDEX_LPDDR3_WRITE_VREF_RANG0 0x51
+#define DMC_TEST_WINDOW_INDEX_LPDDR3_WRITE_VREF_RANG1 0x52
+#define DMC_TEST_WINDOW_INDEX_LPDDR3_READ_VREF_RANG0 0x53
+#define DMC_TEST_WINDOW_INDEX_LPDDR3_READ_VREF_RANG1 0x54
+
+unsigned int dwc_ddrphy_apb_wr(unsigned int addr, unsigned int dat)
+{
+ *(volatile uint16_t *)(int_convter_p(((addr) << 1) + (p_ddr_base->ddr_phy_base_address))) = ((uint16_t)dat);
+ return 1;
+}
+
+unsigned int dwc_ddrphy_apb_rd(unsigned int addr)
+{
+ return *(volatile uint16_t *)(int_convter_p(((addr) << 1) + (p_ddr_base->ddr_phy_base_address)));
+}
+
+void ddr_udelay(unsigned int us)
+{
+ unsigned int t0 = (rd_reg((p_ddr_base->ee_timer_base_address)));
+
+ while ((rd_reg(((p_ddr_base->ee_timer_base_address)))) - t0 <= us) {
+ }
+}
+
+void ddr_udelay_dummy(volatile unsigned int us)
+{
+ if ((p_ddr_base->ee_timer_base_address)) {
+ ddr_udelay(us);
+ } else {
+ if (us == 0)
+ us = 10000;
+
+ while (us--) {
+ }
+ }
+}
+#define DDR_PARAMETER_SOURCE_FROM_DMC_STICKY 1
+#define DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV 2
+#define DDR_PARAMETER_SOURCE_FROM_UBOOT_IDME 3
+#define DDR_PARAMETER_SOURCE_FROM_ORG_STICKY 4
+
+#define DDR_PARAMETER_READ 1
+#define DDR_PARAMETER_WRITE 2
+#define DDR_PARAMETER_LEFT 1
+#define DDR_PARAMETER_RIGHT 2
+
+#define REGISTER_READ 1
+#define REGISTER_WRITE 0
+
+typedef struct ddr_test_struct {
+ unsigned int ddr_data_source;
+ unsigned int ddr_data_test_size;
+ unsigned int ddr_address_test_size;
+ unsigned int ddr_test_watchdog_times_s;
+ unsigned int ddr_test_lane_disable;
+
+ unsigned int ddr_test_window_flag[8];
+ unsigned int ddr_test_window_data[100];
+}ddr_test_struct_t;
+ddr_test_struct_t *g_ddr_test_struct;
+
+unsigned int read_write_window_test_parameter(unsigned int source_index, unsigned int parameter_index, unsigned int parameter_value, unsigned int read_write_flag)
+{
+ if (source_index == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY) {
+ sticky_reg_base_add = (((p_ddr_base->ddr_dmc_sticky0)) & 0xffff);
+
+ if (read_write_flag == DDR_PARAMETER_WRITE)
+ wr_reg((sticky_reg_base_add + (parameter_index << 2)), parameter_value);
+ if (read_write_flag == DDR_PARAMETER_READ)
+ parameter_value = rd_reg((sticky_reg_base_add + (parameter_index << 2)));
+ }
+
+ if (source_index == DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV) {
+ char *pre_env_name = "ddr_test_data_num";
+ char *env_name = "ddr_test_data_num_0000";
+ char *str_buf = NULL;
+ char *temp_s = NULL;
+ char *endp = NULL;
+ char buf[1024];
+ str_buf = (char *)(&buf);
+ memset(str_buf, 0, sizeof(buf));
+ sprintf(env_name, "%s_%04d", pre_env_name, parameter_index);
+ sprintf(buf, "0x%08x", parameter_value);
+
+ if (read_write_flag == DDR_PARAMETER_WRITE) {
+ setenv(env_name, buf);
+ run_command("save", 0);
+ }
+ if (read_write_flag == DDR_PARAMETER_READ) {
+ temp_s = getenv(env_name);
+ if (temp_s)
+ parameter_value = simple_strtoull_ddr(temp_s, &endp, 0);
+ else
+ parameter_value = 0;
+ }
+ }
+
+ if (source_index == DDR_PARAMETER_SOURCE_FROM_ORG_STICKY) {
+ sticky_reg_base_add = ((p_ddr_base->preg_sticky_reg0));
+
+ if (read_write_flag == DDR_PARAMETER_WRITE)
+ wr_reg((sticky_reg_base_add + (parameter_index << 2)), parameter_value);
+ if (read_write_flag == DDR_PARAMETER_READ)
+ parameter_value = rd_reg((sticky_reg_base_add + (parameter_index << 2)));
+ }
+ return parameter_value;
+}
+
+unsigned int read_write_window_test_flag(unsigned int source_index, unsigned int parameter_index, unsigned int parameter_value, unsigned int read_write_flag)
+{
+ if (source_index == DDR_PARAMETER_SOURCE_FROM_ORG_STICKY) {
+ sticky_reg_base_add = p_ddr_base->preg_sticky_reg0;
+
+ if (read_write_flag == DDR_PARAMETER_WRITE)
+ wr_reg((sticky_reg_base_add + (parameter_index << 2)), parameter_value);
+ if (read_write_flag == DDR_PARAMETER_READ)
+ parameter_value = rd_reg((sticky_reg_base_add + (parameter_index << 2)));
+ }
+
+ if (source_index == DDR_PARAMETER_SOURCE_FROM_DMC_STICKY) {
+ sticky_reg_base_add = (((p_ddr_base->ddr_dmc_sticky0)) & 0xffff);
+
+ if (read_write_flag == DDR_PARAMETER_WRITE)
+ wr_reg((sticky_reg_base_add + (parameter_index << 2)), parameter_value);
+ if (read_write_flag == DDR_PARAMETER_READ)
+ parameter_value = rd_reg((sticky_reg_base_add + (parameter_index << 2)));
+ }
+
+ if (source_index == DDR_PARAMETER_SOURCE_FROM_UBOOT_ENV) {
+ char *pre_env_name = "ddr_test_data_num";
+ char *env_name = "ddr_test_data_num_0000";
+ char *str_buf = NULL;
+ char *temp_s = NULL;
+ char *endp = NULL;
+ char buf[1024];
+ str_buf = (char *)(&buf);
+ memset(str_buf, 0, sizeof(buf));
+ sprintf(env_name, "%s_%04d", pre_env_name, parameter_index);
+ sprintf(buf, "0x%08x", parameter_value);
+
+ if (read_write_flag == DDR_PARAMETER_WRITE) {
+ setenv(env_name, buf);
+ run_command("save", 0);
+ }
+ if (read_write_flag == DDR_PARAMETER_READ) {
+ temp_s = getenv(env_name);
+ if (temp_s)
+ parameter_value = simple_strtoull_ddr(temp_s, &endp, 0);
+ else
+ parameter_value = 0;
+ }
+ }
+
+ return parameter_value;
+}
+
+void ddr_test_watchdog_init(uint32_t msec)
+{
+ // src: 24MHz
+ // div: 24000 for 1ms
+ // reset ao-22 and ee-21
+ *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address) = (1 << 24) | (1 << 25) | (1 << 22) | (1 << 21) | (24000 - 1);
+
+ // set timeout
+ *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address + 8) = msec;
+ *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address + 12) = 0;
+
+ // enable
+ *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address) |= (1 << 18);
+}
+
+void ddr_test_watchdog_clear(void)
+{
+ *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address + 12) = 0;
+}
+
+void ddr_test_watchdog_disable(void)
+{
+ // turn off internal counter and disable
+ *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address) &= ~((1 << 18) | (1 << 25));
+}
+
+void ddr_test_watchdog_enable(uint32_t sec)
+{
+ // src: 24MHz
+ // div: 24000 for 1ms
+ // reset ao-22 and ee-21
+#if (CONFIG_DDR_PHY > P_DDR_PHY_DEFAULT)
+ *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address) = (1 << 24) | (1 << 25) | (1 << 23) | (1 << 21) | (240000 - 1); //10ms
+ if (sec * 100 > 0xffff)
+ *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address + 8) = 0xffff;
+ else
+ *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address + 8) = sec * 100; //max 655s
+ *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address + 12) = 0;
+
+ // enable
+ *(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address) = (*(volatile uint32_t *)(unsigned long)(p_ddr_base->sys_watchdog_base_address)) | (1 << 18);
+#endif
+ printf("\nP_WATCHDOG_ENABLE\n");
+}
+
+void ddr_test_watchdog_reset_system(void)
+{
+ int i;
+
+ if (p_ddr_base->sys_watchdog_enable_value == 0) {
+ p_ddr_base->sys_watchdog_enable_value = 0x3 | (1 << 21) // sys reset en
+ | (1 << 23) // interrupt en
+ | (1 << 24) // clk en
+ | (1 << 25) // clk div en
+ | (1 << 26); // sys reset now
+ }
+ writel(0, (p_ddr_base->sys_watchdog_base_address + 12));
+ while (1) {
+ writel(p_ddr_base->sys_watchdog_enable_value
+ , (p_ddr_base->sys_watchdog_base_address));
+ writel(0, (p_ddr_base->sys_watchdog_base_address + 12));
+ writel((p_ddr_base->sys_watchdog_enable_value) | (1 << 18),
+ (p_ddr_base->sys_watchdog_base_address)); // watchdog en
+ for (i = 0; i < 100; i++)
+ readl((p_ddr_base->sys_watchdog_base_address)); /*Deceive gcc for waiting some cycles */
+ }
+}
+
+static void ddr_write(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ unsigned int i, j, n;
+ unsigned int m_len = m_length;
+
+ p = (unsigned int *)buff;
+
+ while (m_len) {
+ for (j = 0; j < 32; j++) {
+ if (m_len >= 128)
+ n = 32;
+ else
+ n = m_len >> 2;
+
+ for (i = 0; i < n; i++) {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p);
+#endif
+ switch (i) {
+ case 0:
+ case 9:
+ case 14:
+ case 25:
+ case 30:
+ *(p + i) = TDATA32F;
+ break;
+ case 1:
+ case 6:
+ case 8:
+ case 17:
+ case 22:
+ *(p + i) = 0;
+ break;
+ case 16:
+ case 23:
+ case 31:
+ *(p + i) = TDATA32A;
+ break;
+ case 7:
+ case 15:
+ case 24:
+ *(p + i) = TDATA325;
+ break;
+ case 2:
+ case 4:
+ case 10:
+ case 12:
+ case 19:
+ case 21:
+ case 27:
+ case 29:
+ *(p + i) = 1 << j;
+ break;
+ case 3:
+ case 5:
+ case 11:
+ case 13:
+ case 18:
+ case 20:
+ case 26:
+ case 28:
+ *(p + i) = ~(1 << j);
+ break;
+ }
+ }
+
+ if (m_len > 128) {
+ m_len -= 128;
+ p += 32;
+ } else {
+ p += (m_len >> 2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+static void ddr_read(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ unsigned int i, j, n;
+ unsigned int m_len = m_length;
+
+ p = (unsigned int *)buff;
+
+ while (m_len) {
+ for (j = 0; j < 32; j++) {
+ if (m_len >= 128)
+ n = 32;
+ else
+ n = m_len >> 2;
+
+ for (i = 0; i < n; i++) {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p);
+#endif
+ if ((error_outof_count_flag) && (error_count)) {
+ printf("Error data out of count");
+ m_len = 0;
+ break;
+ }
+ switch (i) {
+ case 0:
+ case 9:
+ case 14:
+ case 25:
+ case 30:
+ if (*(p + i) != TDATA32F) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32F);
+ }
+ break;
+ case 1:
+ case 6:
+ case 8:
+ case 17:
+ case 22:
+ if (*(p + i) != 0) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0);
+ }
+ break;
+ case 16:
+ case 23:
+ case 31:
+ if (*(p + i) != TDATA32A) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32A);
+ }
+ break;
+ case 7:
+ case 15:
+ case 24:
+ if (*(p + i) != TDATA325) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA325);
+ }
+ break;
+ case 2:
+ case 4:
+ case 10:
+ case 12:
+ case 19:
+ case 21:
+ case 27:
+ case 29:
+ if (*(p + i) != 1 << j) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 1 << j);
+ }
+ break;
+ case 3:
+ case 5:
+ case 11:
+ case 13:
+ case 18:
+ case 20:
+ case 26:
+ case 28:
+ if (*(p + i) != ~(1 << j)) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~(1 << j));
+ }
+ break;
+ }
+ }
+
+ if (m_len > 128) {
+ m_len -= 128;
+ p += 32;
+ } else {
+ p += (m_len >> 2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+static void ddr_write4(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ unsigned int i, j, n;
+ unsigned int m_len = m_length;
+
+ p = (unsigned int *)buff;
+
+ while (m_len) {
+ for (j = 0; j < 32; j++) {
+ if (m_len >= 128)
+ n = 32;
+ else
+ n = m_len >> 2;
+
+ for (i = 0; i < n; i++) {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p);
+#endif
+ switch (i) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ *(p + i) = 0xff00ff00;
+ break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ *(p + i) = ~0xff00ff00;
+ break;
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ *(p + i) = 0xaa55aa55;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ *(p + i) = ~0xaa55aa55;
+ break;
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+
+ case 24:
+ case 25:
+ case 26:
+ case 27:
+ *(p + i) = 1 << j;
+ break;
+ case 20:
+ case 21:
+ case 22:
+ case 23:
+ case 28:
+ case 29:
+ case 30:
+ case 31:
+ *(p + i) = ~(1 << j);
+ break;
+ }
+ }
+
+ if (m_len > 128) {
+ m_len -= 128;
+ p += 32;
+ } else {
+ p += (m_len >> 2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+static void ddr_read4(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ unsigned int i, j, n;
+ unsigned int m_len = m_length;
+
+ p = (unsigned int *)buff;
+
+ while (m_len) {
+ for (j = 0; j < 32; j++) {
+ if (m_len >= 128)
+ n = 32;
+ else
+ n = m_len >> 2;
+
+ for (i = 0; i < n; i++) {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p);
+#endif
+ if ((error_outof_count_flag) && (error_count)) {
+ printf("Error data out of count");
+ m_len = 0;
+ break;
+ }
+ switch (i) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ if (*(p + i) != 0xff00ff00) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32F);
+ }
+ break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ if (*(p + i) != ~0xff00ff00) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32F);
+ }
+ break;
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ if (*(p + i) != 0xaa55aa55) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32F);
+ }
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ if (*(p + i) != ~0xaa55aa55) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32F);
+ }
+ break;
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+
+ case 24:
+ case 25:
+ case 26:
+ case 27:
+ if (*(p + i) != (1 << j)) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32F);
+ }
+ break;
+ case 20:
+ case 21:
+ case 22:
+ case 23:
+ case 28:
+ case 29:
+ case 30:
+ case 31:
+ if (*(p + i) != ~(1 << j)) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32F);
+ }
+ break;
+ }
+ }
+
+ if (m_len > 128) {
+ m_len -= 128;
+ p += 32;
+ } else {
+ p += (m_len >> 2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+static void ddr_read_full(void *buff, unsigned int m_length, unsigned int start_pattern,
+ unsigned int pattern_offset)
+{
+ unsigned int *p;
+ unsigned int i = 0;
+ unsigned int m_len = m_length & 0xfffffffc;
+
+ p = (unsigned int *)buff;
+ while (m_len) {
+ m_len = m_len - 4;
+
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p + i);
+#endif
+ if ((error_outof_count_flag) && (error_count)) {
+ printf("Error data out of count");
+ m_len = 0;
+ break;
+ }
+ if ((*(p + i)) != (start_pattern + pattern_offset * i)) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i),
+ (start_pattern + pattern_offset * i));
+ }
+ //break;
+ i++;
+ }
+}
+
+static void ddr_write_full(void *buff, unsigned int m_length, unsigned int start_pattern,
+ unsigned int pattern_offset)
+{
+ unsigned int *p;
+ unsigned int i = 0;
+ unsigned int m_len = m_length & 0xfffffffc;
+
+ p = (unsigned int *)buff;
+ while (m_len) {
+ m_len = m_len - 4;
+ *(p + i) = start_pattern + pattern_offset * i;
+ i++;
+ }
+}
+
+static void ddr_test_copy(void *addr_dest, void *addr_src, unsigned int memcpy_size)
+{
+ unsigned int *p_dest;
+ unsigned int *p_src;
+
+ unsigned int m_len = memcpy_size;
+
+ p_dest = (unsigned int *)addr_dest;
+ p_src = (unsigned int *)addr_src;
+ m_len = m_len / 4; //assume it's multiple of 4
+ while (m_len--) {
+ ddr_pld_cache(p_src); //#define ddr_pld_cache(P) asm ("prfm PLDL1KEEP, [%0, #376]"::"r" (P))
+ *p_dest++ = *p_src++;
+ *p_dest++ = *p_src++;
+ *p_dest++ = *p_src++;
+ *p_dest++ = *p_src++;
+ }
+}
+
+int do_ddr_test_copy(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ check_base_address();
+ char *endp = NULL;
+ unsigned long loop = 1;
+ unsigned int print_flag = 1;
+ unsigned int src_addr = DDR_TEST_START_ADDR;
+ unsigned int dec_addr = DDR_TEST_START_ADDR + 0x8000000;
+ unsigned int test_size = DDR_TEST_SIZE;
+
+
+ print_flag = 1;
+
+ printf("\nargc== 0x%08x\n", argc);
+ int i;
+ for (i = 0; i < argc; i++)
+ printf("\nargv[%d]=%s\n", i, argv[i]);
+
+ if (argc == 1) {
+ src_addr = DDR_TEST_START_ADDR;
+ loop = 1;
+ }
+
+ if (argc > 2) {
+ if (*argv[2] == 0 || *endp != 0)
+ src_addr = DDR_TEST_START_ADDR;
+ }
+
+ if (argc > 3) {
+ src_addr = simple_strtoull_ddr(argv[1], &endp, 16);
+ dec_addr = simple_strtoull_ddr(argv[2], &endp, 16);
+ test_size = simple_strtoull_ddr(argv[3], &endp, 16);
+ loop = 1;
+ if (*argv[3] == 0 || *endp != 0)
+ test_size = DDR_TEST_SIZE;
+ }
+ if (test_size < 0x1000)
+ test_size = DDR_TEST_SIZE;
+ if (argc > 4) {
+ loop = simple_strtoull_ddr(argv[4], &endp, 16);
+ if (*argv[4] == 0 || *endp != 0)
+ loop = 1;
+ }
+ if (argc > 5) {
+ print_flag = simple_strtoull_ddr(argv[5], &endp, 16);
+ if (*argv[5] == 0 || *endp != 0)
+ print_flag = 1;
+ }
+
+ unsigned long time_start, time_end, test_loops;
+ test_loops = loop;
+ unsigned long size_count = 0;
+ size_count = loop * test_size;
+ time_start = get_us_time(); //us
+
+ do {
+ ddr_test_copy((void *)(int_convter_p(dec_addr)), (void *)(int_convter_p(src_addr)), test_size);
+ if (print_flag) {
+ printf("\nloop==0x%08x", (unsigned int)loop);
+ printf("\n \n");
+ }
+ } while (--loop);
+ time_end = get_us_time(); //us
+ printf("\ncopy %d times use %dus\n \n", (unsigned int)test_loops, (unsigned int)(time_end - time_start));
+
+ printf("\nddr copy bandwidth==%d MBYTE/S \n \n", (unsigned int)(size_count / (time_end - time_start)));
+ printf("\rEnd ddr test. \n");
+
+ unsigned int m_len = 0, counter = 0;
+ unsigned int *p_dest;
+ p_dest = (void *)(int_convter_p(dec_addr));
+ m_len = test_size / 4; //assume it's multiple of 4
+ counter = (unsigned int)test_loops;
+ size_count = counter * test_size;
+ time_start = get_us_time(); //us
+ do {
+ loop = 1;
+ m_len = test_size / 4;
+ while (m_len--) {
+ ddr_pld_cache(p_dest);
+ *p_dest++ = 0x12345678;
+ *p_dest++ = 0x12345678;
+ *p_dest++ = 0x12345678;
+ *p_dest++ = 0x12345678;
+ }
+ } while (--counter);
+ time_end = get_us_time(); //us
+ printf("\nwrite %d bytes use %dus\n \n", (unsigned int)test_size, (unsigned int)(time_end - time_start));
+
+ printf("\nddr write bandwidth==%d MBYTE/S \n \n", (unsigned int)(size_count / (time_end - time_start)));
+
+ unsigned int *p_src;
+ p_src = (void *)(int_convter_p(src_addr));
+ m_len = test_size / 4; //assume it's multiple of 4
+ unsigned int temp0 = 0;
+ counter = (unsigned int)test_loops;
+ size_count = counter * test_size;
+
+ time_start = get_us_time(); //us
+ do {
+ loop = 1;
+ m_len = test_size / 4;
+ while (m_len--) {
+#ifdef DDR_PREFETCH_CACHE
+ __asm__ __volatile__ ("prfm PLDL1KEEP, [%0, #376]" ::"r" (p_src));
+#endif
+ p_src++;
+ temp0 = (*p_src);
+ m_len--;
+ m_len--;
+ m_len--;
+ m_len--;
+ m_len--;
+ m_len--;
+ m_len--;
+ }
+ } while (--counter);
+ *p_dest++ = temp0;
+ *p_dest++ = *p_src;
+ *p_dest++ = *p_src;
+ *p_dest++ = *p_src;
+ time_end = get_us_time(); //us
+
+ printf("\nread %d Kbytes use %dus\n \n", (unsigned int)(size_count / 1000), (unsigned int)(time_end - time_start));
+ printf("\nddr read bandwidth==%d MBYTE/S \n \n", (unsigned int)(size_count / (time_end - time_start)));
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ ddr_test_copy, 7, 1, do_ddr_test_copy,
+ "ddr_test_copy function",
+ "ddr_test_copy 0x08000000 0x10000000 0x02000000 1 0 ? \n"
+ );
+
+
+#define DDR_PATTERN_LOOP_1 32
+#define DDR_PATTERN_LOOP_2 64
+#define DDR_PATTERN_LOOP_3 96
+
+static void ddr_write_pattern4_cross_talk_p(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ unsigned int i, n;
+ unsigned int m_len = m_length;
+
+ p = (unsigned int *)buff;
+
+ while (m_len) {
+ {
+ if (m_len >= 128 * 4)
+ n = 32 * 4;
+ else
+ n = m_len >> 2;
+
+ for (i = 0; i < n; i++) {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p);
+#endif
+ switch (i) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+ case 24:
+ case 25:
+ case 26:
+ case 27:
+ *(p + i) = TDATA32F;
+ break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ case 20:
+ case 21:
+ case 22:
+ case 23:
+ case 28:
+ case 29:
+ case 30:
+ case 31:
+ *(p + i) = 0;
+ break;
+ case DDR_PATTERN_LOOP_1 + 0:
+ case DDR_PATTERN_LOOP_1 + 1:
+ case DDR_PATTERN_LOOP_1 + 2:
+ case DDR_PATTERN_LOOP_1 + 3:
+ case DDR_PATTERN_LOOP_1 + 8:
+ case DDR_PATTERN_LOOP_1 + 9:
+ case DDR_PATTERN_LOOP_1 + 10:
+ case DDR_PATTERN_LOOP_1 + 11:
+ case DDR_PATTERN_LOOP_1 + 16:
+ case DDR_PATTERN_LOOP_1 + 17:
+ case DDR_PATTERN_LOOP_1 + 18:
+ case DDR_PATTERN_LOOP_1 + 19:
+ case DDR_PATTERN_LOOP_1 + 24:
+ case DDR_PATTERN_LOOP_1 + 25:
+ case DDR_PATTERN_LOOP_1 + 26:
+ case DDR_PATTERN_LOOP_1 + 27:
+ *(p + i) = TDATA32A;
+ break;
+ case DDR_PATTERN_LOOP_1 + 4:
+ case DDR_PATTERN_LOOP_1 + 5:
+ case DDR_PATTERN_LOOP_1 + 6:
+ case DDR_PATTERN_LOOP_1 + 7:
+ case DDR_PATTERN_LOOP_1 + 12:
+ case DDR_PATTERN_LOOP_1 + 13:
+ case DDR_PATTERN_LOOP_1 + 14:
+ case DDR_PATTERN_LOOP_1 + 15:
+ case DDR_PATTERN_LOOP_1 + 20:
+ case DDR_PATTERN_LOOP_1 + 21:
+ case DDR_PATTERN_LOOP_1 + 22:
+ case DDR_PATTERN_LOOP_1 + 23:
+ case DDR_PATTERN_LOOP_1 + 28:
+ case DDR_PATTERN_LOOP_1 + 29:
+ case DDR_PATTERN_LOOP_1 + 30:
+ case DDR_PATTERN_LOOP_1 + 31:
+ *(p + i) = TDATA325;
+ break;
+ case DDR_PATTERN_LOOP_2 + 0:
+ case DDR_PATTERN_LOOP_2 + 1:
+ case DDR_PATTERN_LOOP_2 + 2:
+ case DDR_PATTERN_LOOP_2 + 3:
+ *(p + i) = 0xfe01fe01;
+ break;
+ case DDR_PATTERN_LOOP_2 + 4:
+ case DDR_PATTERN_LOOP_2 + 5:
+ case DDR_PATTERN_LOOP_2 + 6:
+ case DDR_PATTERN_LOOP_2 + 7:
+ *(p + i) = 0xfd02fd02;
+ break;
+ case DDR_PATTERN_LOOP_2 + 8:
+ case DDR_PATTERN_LOOP_2 + 9:
+ case DDR_PATTERN_LOOP_2 + 10:
+ case DDR_PATTERN_LOOP_2 + 11:
+ *(p + i) = 0xfb04fb04;
+ break;
+ case DDR_PATTERN_LOOP_2 + 12:
+ case DDR_PATTERN_LOOP_2 + 13:
+ case DDR_PATTERN_LOOP_2 + 14:
+ case DDR_PATTERN_LOOP_2 + 15:
+ *(p + i) = 0xf708f708;
+ break;
+ case DDR_PATTERN_LOOP_2 + 16:
+ case DDR_PATTERN_LOOP_2 + 17:
+ case DDR_PATTERN_LOOP_2 + 18:
+ case DDR_PATTERN_LOOP_2 + 19:
+ *(p + i) = 0xef10ef10;
+ break;
+ case DDR_PATTERN_LOOP_2 + 20:
+ case DDR_PATTERN_LOOP_2 + 21:
+ case DDR_PATTERN_LOOP_2 + 22:
+ case DDR_PATTERN_LOOP_2 + 23:
+ *(p + i) = 0xdf20df20;
+ break;
+ case DDR_PATTERN_LOOP_2 + 24:
+ case DDR_PATTERN_LOOP_2 + 25:
+ case DDR_PATTERN_LOOP_2 + 26:
+ case DDR_PATTERN_LOOP_2 + 27:
+ *(p + i) = 0xbf40bf40;
+ break;
+ case DDR_PATTERN_LOOP_2 + 28:
+ case DDR_PATTERN_LOOP_2 + 29:
+ case DDR_PATTERN_LOOP_2 + 30:
+ case DDR_PATTERN_LOOP_2 + 31:
+ *(p + i) = 0x7f807f80;
+ break;
+ case DDR_PATTERN_LOOP_3 + 0:
+ case DDR_PATTERN_LOOP_3 + 1:
+ case DDR_PATTERN_LOOP_3 + 2:
+ case DDR_PATTERN_LOOP_3 + 3:
+ *(p + i) = 0x00000100;
+ break;
+ case DDR_PATTERN_LOOP_3 + 4:
+ case DDR_PATTERN_LOOP_3 + 5:
+ case DDR_PATTERN_LOOP_3 + 6:
+ case DDR_PATTERN_LOOP_3 + 7:
+ *(p + i) = 0x00000200;
+ break;
+ case DDR_PATTERN_LOOP_3 + 8:
+ case DDR_PATTERN_LOOP_3 + 9:
+ case DDR_PATTERN_LOOP_3 + 10:
+ case DDR_PATTERN_LOOP_3 + 11:
+ *(p + i) = 0x00000400;
+ break;
+ case DDR_PATTERN_LOOP_3 + 12:
+ case DDR_PATTERN_LOOP_3 + 13:
+ case DDR_PATTERN_LOOP_3 + 14:
+ case DDR_PATTERN_LOOP_3 + 15:
+ *(p + i) = 0x00000800;
+ break;
+ case DDR_PATTERN_LOOP_3 + 16:
+ case DDR_PATTERN_LOOP_3 + 17:
+ case DDR_PATTERN_LOOP_3 + 18:
+ case DDR_PATTERN_LOOP_3 + 19:
+ *(p + i) = 0x00001000;
+ break;
+ case DDR_PATTERN_LOOP_3 + 20:
+ case DDR_PATTERN_LOOP_3 + 21:
+ case DDR_PATTERN_LOOP_3 + 22:
+ case DDR_PATTERN_LOOP_3 + 23:
+ *(p + i) = 0x00002000;
+ break;
+ case DDR_PATTERN_LOOP_3 + 24:
+ case DDR_PATTERN_LOOP_3 + 25:
+ case DDR_PATTERN_LOOP_3 + 26:
+ case DDR_PATTERN_LOOP_3 + 27:
+ *(p + i) = 0x00004000;
+ break;
+ case DDR_PATTERN_LOOP_3 + 28:
+ case DDR_PATTERN_LOOP_3 + 29:
+ case DDR_PATTERN_LOOP_3 + 30:
+ case DDR_PATTERN_LOOP_3 + 31:
+ *(p + i) = 0x00008000;
+ break;
+ }
+ }
+
+ if (m_len > (128 * 4)) {
+ m_len -= (128 * 4);
+ p += 32 * 4;
+ } else {
+ p += (m_len >> 2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+static void ddr_write_pattern4_cross_talk_p2(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ unsigned int i, n;
+ unsigned int m_len = m_length;
+
+ p = (unsigned int *)buff;
+
+ while (m_len) {
+ {
+ if (m_len >= 128 * 4)
+ n = 32 * 4;
+ else
+ n = m_len >> 2;
+
+ for (i = 0; i < n; i++) {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p);
+#endif
+
+ switch (i) {
+ case 0:
+ case DDR_PATTERN_LOOP_1 + 1:
+ case DDR_PATTERN_LOOP_2 + 2:
+ case DDR_PATTERN_LOOP_3 + 3:
+ *(p + i) = 0xfe01fe01;
+ break;
+ case 4:
+ case DDR_PATTERN_LOOP_1 + 5:
+ case DDR_PATTERN_LOOP_2 + 6:
+ case DDR_PATTERN_LOOP_3 + 7:
+ *(p + i) = 0xfd02fd02;
+ break;
+
+ case 8:
+ case DDR_PATTERN_LOOP_1 + 9:
+ case DDR_PATTERN_LOOP_2 + 10:
+ case DDR_PATTERN_LOOP_3 + 11:
+ *(p + i) = 0xfb04fb04;
+ break;
+
+ case 12:
+ case DDR_PATTERN_LOOP_1 + 13:
+ case DDR_PATTERN_LOOP_2 + 14:
+ case DDR_PATTERN_LOOP_3 + 15:
+ *(p + i) = 0xf708f708;
+ break;
+
+ case 16:
+ case DDR_PATTERN_LOOP_1 + 17:
+ case DDR_PATTERN_LOOP_2 + 18:
+ case DDR_PATTERN_LOOP_3 + 19:
+ *(p + i) = 0xef10ef10;
+ break;
+
+ case 20:
+ case DDR_PATTERN_LOOP_1 + 21:
+ case DDR_PATTERN_LOOP_2 + 22:
+ case DDR_PATTERN_LOOP_3 + 23:
+ *(p + i) = 0xdf20df20;
+ break;
+
+ case 24:
+ case DDR_PATTERN_LOOP_1 + 25:
+ case DDR_PATTERN_LOOP_2 + 26:
+ case DDR_PATTERN_LOOP_3 + 27:
+ *(p + i) = 0xbf40bf40;
+ break;
+
+ case 28:
+ case DDR_PATTERN_LOOP_1 + 29:
+ case DDR_PATTERN_LOOP_2 + 30:
+ case DDR_PATTERN_LOOP_3 + 31:
+ *(p + i) = 0x7f807f80;
+ break;
+
+
+ default:
+
+ *(p + i) = 0xff00ff00;
+ break;
+
+ break;
+ }
+ }
+
+ if (m_len > (128 * 4)) {
+ m_len -= (128 * 4);
+ p += 32 * 4;
+ } else {
+ p += (m_len >> 2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+static void ddr_read_pattern4_cross_talk_p(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ unsigned int i, n;
+ unsigned int m_len = m_length;
+
+ p = (unsigned int *)buff;
+
+ while (m_len) {
+ {
+ if (m_len >= 128 * 4)
+ n = 32 * 4;
+ else
+ n = m_len >> 2;
+
+ for (i = 0; i < n; i++) {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p);
+#endif
+ if ((error_outof_count_flag) && (error_count)) {
+ printf("Error data out of count");
+ m_len = 0;
+ break;
+ }
+
+ switch (i) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+ case 24:
+ case 25:
+ case 26:
+ case 27:
+ if (*(p + i) != TDATA32F) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32F);
+ break;
+ }
+ break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ case 20:
+ case 21:
+ case 22:
+ case 23:
+ case 28:
+ case 29:
+ case 30:
+ case 31:
+ if (*(p + i) != 0) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_1 + 0:
+ case DDR_PATTERN_LOOP_1 + 1:
+ case DDR_PATTERN_LOOP_1 + 2:
+ case DDR_PATTERN_LOOP_1 + 3:
+ case DDR_PATTERN_LOOP_1 + 8:
+ case DDR_PATTERN_LOOP_1 + 9:
+ case DDR_PATTERN_LOOP_1 + 10:
+ case DDR_PATTERN_LOOP_1 + 11:
+ case DDR_PATTERN_LOOP_1 + 16:
+ case DDR_PATTERN_LOOP_1 + 17:
+ case DDR_PATTERN_LOOP_1 + 18:
+ case DDR_PATTERN_LOOP_1 + 19:
+ case DDR_PATTERN_LOOP_1 + 24:
+ case DDR_PATTERN_LOOP_1 + 25:
+ case DDR_PATTERN_LOOP_1 + 26:
+ case DDR_PATTERN_LOOP_1 + 27:
+ if (*(p + i) != TDATA32A) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA32A);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_1 + 4:
+ case DDR_PATTERN_LOOP_1 + 5:
+ case DDR_PATTERN_LOOP_1 + 6:
+ case DDR_PATTERN_LOOP_1 + 7:
+ case DDR_PATTERN_LOOP_1 + 12:
+ case DDR_PATTERN_LOOP_1 + 13:
+ case DDR_PATTERN_LOOP_1 + 14:
+ case DDR_PATTERN_LOOP_1 + 15:
+ case DDR_PATTERN_LOOP_1 + 20:
+ case DDR_PATTERN_LOOP_1 + 21:
+ case DDR_PATTERN_LOOP_1 + 22:
+ case DDR_PATTERN_LOOP_1 + 23:
+ case DDR_PATTERN_LOOP_1 + 28:
+ case DDR_PATTERN_LOOP_1 + 29:
+ case DDR_PATTERN_LOOP_1 + 30:
+ case DDR_PATTERN_LOOP_1 + 31:
+ if (*(p + i) != TDATA325) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), TDATA325);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 0:
+ case DDR_PATTERN_LOOP_2 + 1:
+ case DDR_PATTERN_LOOP_2 + 2:
+ case DDR_PATTERN_LOOP_2 + 3:
+ if (*(p + i) != 0xfe01fe01) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xfe01fe01);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 4:
+ case DDR_PATTERN_LOOP_2 + 5:
+ case DDR_PATTERN_LOOP_2 + 6:
+ case DDR_PATTERN_LOOP_2 + 7:
+ if (*(p + i) != 0xfd02fd02) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xfd02fd02);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 8:
+ case DDR_PATTERN_LOOP_2 + 9:
+ case DDR_PATTERN_LOOP_2 + 10:
+ case DDR_PATTERN_LOOP_2 + 11:
+ if (*(p + i) != 0xfb04fb04) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xfb04fb04);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 12:
+ case DDR_PATTERN_LOOP_2 + 13:
+ case DDR_PATTERN_LOOP_2 + 14:
+ case DDR_PATTERN_LOOP_2 + 15:
+ if (*(p + i) != 0xf708f708) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xf708f708);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 16:
+ case DDR_PATTERN_LOOP_2 + 17:
+ case DDR_PATTERN_LOOP_2 + 18:
+ case DDR_PATTERN_LOOP_2 + 19:
+ if (*(p + i) != 0xef10ef10) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xef10ef10);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 20:
+ case DDR_PATTERN_LOOP_2 + 21:
+ case DDR_PATTERN_LOOP_2 + 22:
+ case DDR_PATTERN_LOOP_2 + 23:
+ if (*(p + i) != 0xdf20df20) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xdf20df20);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 24:
+ case DDR_PATTERN_LOOP_2 + 25:
+ case DDR_PATTERN_LOOP_2 + 26:
+ case DDR_PATTERN_LOOP_2 + 27:
+ if (*(p + i) != 0xbf40bf40) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xbf40bf40);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 28:
+ case DDR_PATTERN_LOOP_2 + 29:
+ case DDR_PATTERN_LOOP_2 + 30:
+ case DDR_PATTERN_LOOP_2 + 31:
+ if (*(p + i) != 0x7f807f80) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x7f807f80);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 0:
+ case DDR_PATTERN_LOOP_3 + 1:
+ case DDR_PATTERN_LOOP_3 + 2:
+ case DDR_PATTERN_LOOP_3 + 3:
+ if (*(p + i) != 0x00000100) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00000100);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 4:
+ case DDR_PATTERN_LOOP_3 + 5:
+ case DDR_PATTERN_LOOP_3 + 6:
+ case DDR_PATTERN_LOOP_3 + 7:
+ if (*(p + i) != 0x00000200) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00000200);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 8:
+ case DDR_PATTERN_LOOP_3 + 9:
+ case DDR_PATTERN_LOOP_3 + 10:
+ case DDR_PATTERN_LOOP_3 + 11:
+ if (*(p + i) != 0x00000400) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00000400);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 12:
+ case DDR_PATTERN_LOOP_3 + 13:
+ case DDR_PATTERN_LOOP_3 + 14:
+ case DDR_PATTERN_LOOP_3 + 15:
+ if (*(p + i) != 0x00000800) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00000800);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 16:
+ case DDR_PATTERN_LOOP_3 + 17:
+ case DDR_PATTERN_LOOP_3 + 18:
+ case DDR_PATTERN_LOOP_3 + 19:
+ if (*(p + i) != 0x00001000) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00001000);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 20:
+ case DDR_PATTERN_LOOP_3 + 21:
+ case DDR_PATTERN_LOOP_3 + 22:
+ case DDR_PATTERN_LOOP_3 + 23:
+ if (*(p + i) != 0x00002000) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00002000);
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 24:
+ case DDR_PATTERN_LOOP_3 + 25:
+ case DDR_PATTERN_LOOP_3 + 26:
+ case DDR_PATTERN_LOOP_3 + 27:
+ if (*(p + i) != 0x00004000) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00004000);
+ break;
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 28:
+ case DDR_PATTERN_LOOP_3 + 29:
+ case DDR_PATTERN_LOOP_3 + 30:
+ case DDR_PATTERN_LOOP_3 + 31:
+ if (*(p + i) != 0x00008000) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00008000);
+ break;
+ }
+ break;
+ }
+ }
+
+ if (m_len > 128 * 4) {
+ m_len -= 128 * 4;
+ p += 32 * 4;
+ } else {
+ p += (m_len >> 2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+static void ddr_read_pattern4_cross_talk_p2(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ unsigned int i, n;
+ unsigned int m_len = m_length;
+
+ p = (unsigned int *)buff;
+
+ while (m_len) {
+ {
+ if (m_len >= 128 * 4)
+ n = 32 * 4;
+ else
+ n = m_len >> 2;
+
+ for (i = 0; i < n; i++) {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p);
+#endif
+ if ((error_outof_count_flag) && (error_count)) {
+ printf("Error data out of count");
+ m_len = 0;
+ break;
+ }
+
+ switch (i) {
+ case 0:
+ case DDR_PATTERN_LOOP_1 + 1:
+ case DDR_PATTERN_LOOP_2 + 2:
+ case DDR_PATTERN_LOOP_3 + 3:
+ if (*(p + i) != 0xfe01fe01) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xfe01fe01);
+ break;
+ }
+ break;
+ case 4:
+ case DDR_PATTERN_LOOP_1 + 5:
+ case DDR_PATTERN_LOOP_2 + 6:
+ case DDR_PATTERN_LOOP_3 + 7:
+ if (*(p + i) != 0xfd02fd02) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xfd02fd02);
+ break;
+ }
+ break;
+
+ case 8:
+ case DDR_PATTERN_LOOP_1 + 9:
+ case DDR_PATTERN_LOOP_2 + 10:
+ case DDR_PATTERN_LOOP_3 + 11:
+ if (*(p + i) != 0xfb04fb04) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xfb04fb04);
+ break;
+ }
+ break;
+
+ case 12:
+ case DDR_PATTERN_LOOP_1 + 13:
+ case DDR_PATTERN_LOOP_2 + 14:
+ case DDR_PATTERN_LOOP_3 + 15:
+ if (*(p + i) != 0xf708f708) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xf708f708);
+ break;
+ }
+ break;
+
+ case 16:
+ case DDR_PATTERN_LOOP_1 + 17:
+ case DDR_PATTERN_LOOP_2 + 18:
+ case DDR_PATTERN_LOOP_3 + 19:
+ if (*(p + i) != 0xef10ef10) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xef10ef10);
+ break;
+ }
+ break;
+
+ case 20:
+ case DDR_PATTERN_LOOP_1 + 21:
+ case DDR_PATTERN_LOOP_2 + 22:
+ case DDR_PATTERN_LOOP_3 + 23:
+ if (*(p + i) != 0xdf20df20) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xdf20df20);
+ break;
+ }
+ break;
+
+ case 24:
+ case DDR_PATTERN_LOOP_1 + 25:
+ case DDR_PATTERN_LOOP_2 + 26:
+ case DDR_PATTERN_LOOP_3 + 27:
+ if (*(p + i) != 0xbf40bf40) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xbf40bf40);
+ break;
+ }
+ break;
+ case 28:
+ case DDR_PATTERN_LOOP_1 + 29:
+ case DDR_PATTERN_LOOP_2 + 30:
+ case DDR_PATTERN_LOOP_3 + 31:
+ if (*(p + i) != 0x7f807f80) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x7f807f80);
+ break;
+ }
+ break;
+
+
+ default:
+ if (*(p + i) != 0xff00ff00) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff00ff00);
+ break;
+ }
+ break;
+
+ break;
+ }
+ }
+
+ if (m_len > 128 * 4) {
+ m_len -= 128 * 4;
+ p += 32 * 4;
+ } else {
+ p += (m_len >> 2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+static void ddr_write_pattern4_cross_talk_n(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ unsigned int i, n;
+ unsigned int m_len = m_length;
+
+ p = (unsigned int *)buff;
+
+ while (m_len) {
+ {
+ if (m_len >= 128 * 4)
+ n = 32 * 4;
+ else
+ n = m_len >> 2;
+
+ for (i = 0; i < n; i++) {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p);
+#endif
+ switch (i) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+ case 24:
+ case 25:
+ case 26:
+ case 27:
+ *(p + i) = ~TDATA32F;
+ break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ case 20:
+ case 21:
+ case 22:
+ case 23:
+ case 28:
+ case 29:
+ case 30:
+ case 31:
+ *(p + i) = ~0;
+ break;
+ case DDR_PATTERN_LOOP_1 + 0:
+ case DDR_PATTERN_LOOP_1 + 1:
+ case DDR_PATTERN_LOOP_1 + 2:
+ case DDR_PATTERN_LOOP_1 + 3:
+ case DDR_PATTERN_LOOP_1 + 8:
+ case DDR_PATTERN_LOOP_1 + 9:
+ case DDR_PATTERN_LOOP_1 + 10:
+ case DDR_PATTERN_LOOP_1 + 11:
+ case DDR_PATTERN_LOOP_1 + 16:
+ case DDR_PATTERN_LOOP_1 + 17:
+ case DDR_PATTERN_LOOP_1 + 18:
+ case DDR_PATTERN_LOOP_1 + 19:
+ case DDR_PATTERN_LOOP_1 + 24:
+ case DDR_PATTERN_LOOP_1 + 25:
+ case DDR_PATTERN_LOOP_1 + 26:
+ case DDR_PATTERN_LOOP_1 + 27:
+ *(p + i) = ~TDATA32A;
+ break;
+ case DDR_PATTERN_LOOP_1 + 4:
+ case DDR_PATTERN_LOOP_1 + 5:
+ case DDR_PATTERN_LOOP_1 + 6:
+ case DDR_PATTERN_LOOP_1 + 7:
+ case DDR_PATTERN_LOOP_1 + 12:
+ case DDR_PATTERN_LOOP_1 + 13:
+ case DDR_PATTERN_LOOP_1 + 14:
+ case DDR_PATTERN_LOOP_1 + 15:
+ case DDR_PATTERN_LOOP_1 + 20:
+ case DDR_PATTERN_LOOP_1 + 21:
+ case DDR_PATTERN_LOOP_1 + 22:
+ case DDR_PATTERN_LOOP_1 + 23:
+ case DDR_PATTERN_LOOP_1 + 28:
+ case DDR_PATTERN_LOOP_1 + 29:
+ case DDR_PATTERN_LOOP_1 + 30:
+ case DDR_PATTERN_LOOP_1 + 31:
+ *(p + i) = ~TDATA325;
+ break;
+ case DDR_PATTERN_LOOP_2 + 0:
+ case DDR_PATTERN_LOOP_2 + 1:
+ case DDR_PATTERN_LOOP_2 + 2:
+ case DDR_PATTERN_LOOP_2 + 3:
+ *(p + i) = ~0xfe01fe01;
+ break;
+ case DDR_PATTERN_LOOP_2 + 4:
+ case DDR_PATTERN_LOOP_2 + 5:
+ case DDR_PATTERN_LOOP_2 + 6:
+ case DDR_PATTERN_LOOP_2 + 7:
+ *(p + i) = ~0xfd02fd02;
+ break;
+ case DDR_PATTERN_LOOP_2 + 8:
+ case DDR_PATTERN_LOOP_2 + 9:
+ case DDR_PATTERN_LOOP_2 + 10:
+ case DDR_PATTERN_LOOP_2 + 11:
+ *(p + i) = ~0xfb04fb04;
+ break;
+ case DDR_PATTERN_LOOP_2 + 12:
+ case DDR_PATTERN_LOOP_2 + 13:
+ case DDR_PATTERN_LOOP_2 + 14:
+ case DDR_PATTERN_LOOP_2 + 15:
+ *(p + i) = ~0xf708f708;
+ break;
+ case DDR_PATTERN_LOOP_2 + 16:
+ case DDR_PATTERN_LOOP_2 + 17:
+ case DDR_PATTERN_LOOP_2 + 18:
+ case DDR_PATTERN_LOOP_2 + 19:
+ *(p + i) = ~0xef10ef10;
+ break;
+ case DDR_PATTERN_LOOP_2 + 20:
+ case DDR_PATTERN_LOOP_2 + 21:
+ case DDR_PATTERN_LOOP_2 + 22:
+ case DDR_PATTERN_LOOP_2 + 23:
+ *(p + i) = ~0xdf20df20;
+ break;
+ case DDR_PATTERN_LOOP_2 + 24:
+ case DDR_PATTERN_LOOP_2 + 25:
+ case DDR_PATTERN_LOOP_2 + 26:
+ case DDR_PATTERN_LOOP_2 + 27:
+ *(p + i) = ~0xbf40bf40;
+ break;
+ case DDR_PATTERN_LOOP_2 + 28:
+ case DDR_PATTERN_LOOP_2 + 29:
+ case DDR_PATTERN_LOOP_2 + 30:
+ case DDR_PATTERN_LOOP_2 + 31:
+ *(p + i) = ~0x7f807f80;
+ break;
+ case DDR_PATTERN_LOOP_3 + 0:
+ case DDR_PATTERN_LOOP_3 + 1:
+ case DDR_PATTERN_LOOP_3 + 2:
+ case DDR_PATTERN_LOOP_3 + 3:
+ *(p + i) = ~0x00000100;
+ break;
+ case DDR_PATTERN_LOOP_3 + 4:
+ case DDR_PATTERN_LOOP_3 + 5:
+ case DDR_PATTERN_LOOP_3 + 6:
+ case DDR_PATTERN_LOOP_3 + 7:
+ *(p + i) = ~0x00000200;
+ break;
+ case DDR_PATTERN_LOOP_3 + 8:
+ case DDR_PATTERN_LOOP_3 + 9:
+ case DDR_PATTERN_LOOP_3 + 10:
+ case DDR_PATTERN_LOOP_3 + 11:
+ *(p + i) = ~0x00000400;
+ break;
+ case DDR_PATTERN_LOOP_3 + 12:
+ case DDR_PATTERN_LOOP_3 + 13:
+ case DDR_PATTERN_LOOP_3 + 14:
+ case DDR_PATTERN_LOOP_3 + 15:
+ *(p + i) = ~0x00000800;
+ break;
+ case DDR_PATTERN_LOOP_3 + 16:
+ case DDR_PATTERN_LOOP_3 + 17:
+ case DDR_PATTERN_LOOP_3 + 18:
+ case DDR_PATTERN_LOOP_3 + 19:
+ *(p + i) = ~0x00001000;
+ break;
+ case DDR_PATTERN_LOOP_3 + 20:
+ case DDR_PATTERN_LOOP_3 + 21:
+ case DDR_PATTERN_LOOP_3 + 22:
+ case DDR_PATTERN_LOOP_3 + 23:
+ *(p + i) = ~0x00002000;
+ break;
+ case DDR_PATTERN_LOOP_3 + 24:
+ case DDR_PATTERN_LOOP_3 + 25:
+ case DDR_PATTERN_LOOP_3 + 26:
+ case DDR_PATTERN_LOOP_3 + 27:
+ *(p + i) = ~0x00004000;
+ break;
+ case DDR_PATTERN_LOOP_3 + 28:
+ case DDR_PATTERN_LOOP_3 + 29:
+ case DDR_PATTERN_LOOP_3 + 30:
+ case DDR_PATTERN_LOOP_3 + 31:
+ *(p + i) = ~0x00008000;
+ break;
+ }
+ }
+
+ if (m_len > (128 * 4)) {
+ m_len -= (128 * 4);
+ p += 32 * 4;
+ } else {
+ p += (m_len >> 2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+static void ddr_write_pattern4_cross_talk_n2(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ unsigned int i, n;
+ unsigned int m_len = m_length;
+
+ p = (unsigned int *)buff;
+
+ while (m_len) {
+ {
+ if (m_len >= 128 * 4)
+ n = 32 * 4;
+ else
+ n = m_len >> 2;
+
+ for (i = 0; i < n; i++) {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p);
+#endif
+
+ switch (i) {
+ case 0:
+ case DDR_PATTERN_LOOP_1 + 1:
+ case DDR_PATTERN_LOOP_2 + 2:
+ case DDR_PATTERN_LOOP_3 + 3:
+ *(p + i) = ~0xfe01fe01;
+ break;
+ case 4:
+ case DDR_PATTERN_LOOP_1 + 5:
+ case DDR_PATTERN_LOOP_2 + 6:
+ case DDR_PATTERN_LOOP_3 + 7:
+ *(p + i) = ~0xfd02fd02;
+ break;
+
+ case 8:
+ case DDR_PATTERN_LOOP_1 + 9:
+ case DDR_PATTERN_LOOP_2 + 10:
+ case DDR_PATTERN_LOOP_3 + 11:
+ *(p + i) = ~0xfb04fb04;
+ break;
+
+ case 12:
+ case DDR_PATTERN_LOOP_1 + 13:
+ case DDR_PATTERN_LOOP_2 + 14:
+ case DDR_PATTERN_LOOP_3 + 15:
+ *(p + i) = ~0xf708f708;
+ break;
+
+ case 16:
+ case DDR_PATTERN_LOOP_1 + 17:
+ case DDR_PATTERN_LOOP_2 + 18:
+ case DDR_PATTERN_LOOP_3 + 19:
+ *(p + i) = ~0xef10ef10;
+ break;
+
+ case 20:
+ case DDR_PATTERN_LOOP_1 + 21:
+ case DDR_PATTERN_LOOP_2 + 22:
+ case DDR_PATTERN_LOOP_3 + 23:
+ *(p + i) = ~0xdf20df20;
+ break;
+
+ case 24:
+ case DDR_PATTERN_LOOP_1 + 25:
+ case DDR_PATTERN_LOOP_2 + 26:
+ case DDR_PATTERN_LOOP_3 + 27:
+ *(p + i) = ~0xbf40bf40;
+ break;
+ case 28:
+ case DDR_PATTERN_LOOP_1 + 29:
+ case DDR_PATTERN_LOOP_2 + 30:
+ case DDR_PATTERN_LOOP_3 + 31:
+ *(p + i) = ~0x7f807f80;
+ break;
+
+
+ default:
+
+ *(p + i) = ~0xff00ff00;
+ break;
+
+ break;
+ }
+ }
+
+ if (m_len > (128 * 4)) {
+ m_len -= (128 * 4);
+ p += 32 * 4;
+ } else {
+ p += (m_len >> 2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+static void ddr_read_pattern4_cross_talk_n(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ unsigned int i, n;
+ unsigned int m_len = m_length;
+
+ p = (unsigned int *)buff;
+
+ while (m_len) {
+ {
+ if (m_len >= 128 * 4)
+ n = 32 * 4;
+ else
+ n = m_len >> 2;
+
+ for (i = 0; i < n; i++) {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p);
+#endif
+ if ((error_outof_count_flag) && (error_count)) {
+ printf("Error data out of count");
+ m_len = 0;
+ break;
+ }
+ switch (i) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+ case 24:
+ case 25:
+ case 26:
+ case 27:
+ if (*(p + i) != ~TDATA32F) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~TDATA32F);
+ break;
+ }
+ break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ case 20:
+ case 21:
+ case 22:
+ case 23:
+ case 28:
+ case 29:
+ case 30:
+ case 31:
+ if (*(p + i) != ~0) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0);
+ }
+ break;
+ case DDR_PATTERN_LOOP_1 + 0:
+ case DDR_PATTERN_LOOP_1 + 1:
+ case DDR_PATTERN_LOOP_1 + 2:
+ case DDR_PATTERN_LOOP_1 + 3:
+ case DDR_PATTERN_LOOP_1 + 8:
+ case DDR_PATTERN_LOOP_1 + 9:
+ case DDR_PATTERN_LOOP_1 + 10:
+ case DDR_PATTERN_LOOP_1 + 11:
+ case DDR_PATTERN_LOOP_1 + 16:
+ case DDR_PATTERN_LOOP_1 + 17:
+ case DDR_PATTERN_LOOP_1 + 18:
+ case DDR_PATTERN_LOOP_1 + 19:
+ case DDR_PATTERN_LOOP_1 + 24:
+ case DDR_PATTERN_LOOP_1 + 25:
+ case DDR_PATTERN_LOOP_1 + 26:
+ case DDR_PATTERN_LOOP_1 + 27:
+ if (*(p + i) != ~TDATA32A) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~TDATA32A);
+ }
+ break;
+ case DDR_PATTERN_LOOP_1 + 4:
+ case DDR_PATTERN_LOOP_1 + 5:
+ case DDR_PATTERN_LOOP_1 + 6:
+ case DDR_PATTERN_LOOP_1 + 7:
+ case DDR_PATTERN_LOOP_1 + 12:
+ case DDR_PATTERN_LOOP_1 + 13:
+ case DDR_PATTERN_LOOP_1 + 14:
+ case DDR_PATTERN_LOOP_1 + 15:
+ case DDR_PATTERN_LOOP_1 + 20:
+ case DDR_PATTERN_LOOP_1 + 21:
+ case DDR_PATTERN_LOOP_1 + 22:
+ case DDR_PATTERN_LOOP_1 + 23:
+ case DDR_PATTERN_LOOP_1 + 28:
+ case DDR_PATTERN_LOOP_1 + 29:
+ case DDR_PATTERN_LOOP_1 + 30:
+ case DDR_PATTERN_LOOP_1 + 31:
+ if (*(p + i) != ~TDATA325) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~TDATA325);
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 0:
+ case DDR_PATTERN_LOOP_2 + 1:
+ case DDR_PATTERN_LOOP_2 + 2:
+ case DDR_PATTERN_LOOP_2 + 3:
+ if (*(p + i) != ~0xfe01fe01) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xfe01fe01);
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 4:
+ case DDR_PATTERN_LOOP_2 + 5:
+ case DDR_PATTERN_LOOP_2 + 6:
+ case DDR_PATTERN_LOOP_2 + 7:
+ if (*(p + i) != ~0xfd02fd02) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xfd02fd02);
+ }
+ break;
+
+ case DDR_PATTERN_LOOP_2 + 8:
+ case DDR_PATTERN_LOOP_2 + 9:
+ case DDR_PATTERN_LOOP_2 + 10:
+ case DDR_PATTERN_LOOP_2 + 11:
+ if (*(p + i) != ~0xfb04fb04) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xfb04fb04);
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 12:
+ case DDR_PATTERN_LOOP_2 + 13:
+ case DDR_PATTERN_LOOP_2 + 14:
+ case DDR_PATTERN_LOOP_2 + 15:
+ if (*(p + i) != ~0xf708f708) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xf708f708);
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 16:
+ case DDR_PATTERN_LOOP_2 + 17:
+ case DDR_PATTERN_LOOP_2 + 18:
+ case DDR_PATTERN_LOOP_2 + 19:
+ if (*(p + i) != ~0xef10ef10) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xef10ef10);
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 20:
+ case DDR_PATTERN_LOOP_2 + 21:
+ case DDR_PATTERN_LOOP_2 + 22:
+ case DDR_PATTERN_LOOP_2 + 23:
+ if (*(p + i) != ~0xdf20df20) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xdf20df20);
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 24:
+ case DDR_PATTERN_LOOP_2 + 25:
+ case DDR_PATTERN_LOOP_2 + 26:
+ case DDR_PATTERN_LOOP_2 + 27:
+ if (*(p + i) != ~0xbf40bf40) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xbf40bf40);
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 28:
+ case DDR_PATTERN_LOOP_2 + 29:
+ case DDR_PATTERN_LOOP_2 + 30:
+ case DDR_PATTERN_LOOP_2 + 31:
+ if (*(p + i) != ~0x7f807f80) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x7f807f80);
+ }
+ break;
+ break;
+ case DDR_PATTERN_LOOP_3 + 0:
+ case DDR_PATTERN_LOOP_3 + 1:
+ case DDR_PATTERN_LOOP_3 + 2:
+ case DDR_PATTERN_LOOP_3 + 3:
+ if (*(p + i) != ~0x00000100) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00000100);
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 4:
+ case DDR_PATTERN_LOOP_3 + 5:
+ case DDR_PATTERN_LOOP_3 + 6:
+ case DDR_PATTERN_LOOP_3 + 7:
+ if (*(p + i) != ~0x00000200) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00000200);
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 8:
+ case DDR_PATTERN_LOOP_3 + 9:
+ case DDR_PATTERN_LOOP_3 + 10:
+ case DDR_PATTERN_LOOP_3 + 11:
+ if (*(p + i) != ~0x00000400) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00000400);
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 12:
+ case DDR_PATTERN_LOOP_3 + 13:
+ case DDR_PATTERN_LOOP_3 + 14:
+ case DDR_PATTERN_LOOP_3 + 15:
+ if (*(p + i) != ~0x00000800) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00000800);
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 16:
+ case DDR_PATTERN_LOOP_3 + 17:
+ case DDR_PATTERN_LOOP_3 + 18:
+ case DDR_PATTERN_LOOP_3 + 19:
+ if (*(p + i) != ~0x00001000) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00001000);
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 20:
+ case DDR_PATTERN_LOOP_3 + 21:
+ case DDR_PATTERN_LOOP_3 + 22:
+ case DDR_PATTERN_LOOP_3 + 23:
+ if (*(p + i) != ~0x00002000) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00002000);
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 24:
+ case DDR_PATTERN_LOOP_3 + 25:
+ case DDR_PATTERN_LOOP_3 + 26:
+ case DDR_PATTERN_LOOP_3 + 27:
+ if (*(p + i) != ~0x00004000) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00004000);
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 28:
+ case DDR_PATTERN_LOOP_3 + 29:
+ case DDR_PATTERN_LOOP_3 + 30:
+ case DDR_PATTERN_LOOP_3 + 31:
+ if (*(p + i) != ~0x00008000) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00008000);
+ }
+ break;
+ }
+ }
+
+ if (m_len > 128 * 4) {
+ m_len -= 128 * 4;
+ p += 32 * 4;
+ } else {
+ p += (m_len >> 2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+static void ddr_read_pattern4_cross_talk_n2(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ unsigned int i, n;
+ unsigned int m_len = m_length;
+
+ p = (unsigned int *)buff;
+
+ while (m_len) {
+ {
+ if (m_len >= 128 * 4)
+ n = 32 * 4;
+ else
+ n = m_len >> 2;
+
+ for (i = 0; i < n; i++) {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p);
+#endif
+ if ((error_outof_count_flag) && (error_count)) {
+ printf("Error data out of count");
+ m_len = 0;
+ break;
+ }
+
+ switch (i) {
+ case 0:
+ case DDR_PATTERN_LOOP_1 + 1:
+ case DDR_PATTERN_LOOP_2 + 2:
+ case DDR_PATTERN_LOOP_3 + 3:
+ if (*(p + i) != ~0xfe01fe01) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xfe01fe01);
+ break;
+ }
+ break;
+ case 4:
+ case DDR_PATTERN_LOOP_1 + 5:
+ case DDR_PATTERN_LOOP_2 + 6:
+ case DDR_PATTERN_LOOP_3 + 7:
+ if (*(p + i) != ~0xfd02fd02) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xfd02fd02);
+ break;
+ }
+ break;
+
+ case 8:
+ case DDR_PATTERN_LOOP_1 + 9:
+ case DDR_PATTERN_LOOP_2 + 10:
+ case DDR_PATTERN_LOOP_3 + 11:
+ if (*(p + i) != ~0xfb04fb04) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xfb04fb04);
+ break;
+ }
+ break;
+
+ case 12:
+ case DDR_PATTERN_LOOP_1 + 13:
+ case DDR_PATTERN_LOOP_2 + 14:
+ case DDR_PATTERN_LOOP_3 + 15:
+ if (*(p + i) != ~0xf708f708) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xf708f708);
+ break;
+ }
+ break;
+
+ case 16:
+ case DDR_PATTERN_LOOP_1 + 17:
+ case DDR_PATTERN_LOOP_2 + 18:
+ case DDR_PATTERN_LOOP_3 + 19:
+ if (*(p + i) != ~0xef10ef10) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xef10ef10);
+ break;
+ }
+ break;
+
+ case 20:
+ case DDR_PATTERN_LOOP_1 + 21:
+ case DDR_PATTERN_LOOP_2 + 22:
+ case DDR_PATTERN_LOOP_3 + 23:
+ if (*(p + i) != ~0xdf20df20) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xdf20df20);
+ break;
+ }
+ break;
+
+ case 24:
+ case DDR_PATTERN_LOOP_1 + 25:
+ case DDR_PATTERN_LOOP_2 + 26:
+ case DDR_PATTERN_LOOP_3 + 27:
+ if (*(p + i) != ~0xbf40bf40) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xbf40bf40);
+ break;
+ }
+ break;
+ case 28:
+ case DDR_PATTERN_LOOP_1 + 29:
+ case DDR_PATTERN_LOOP_2 + 30:
+ case DDR_PATTERN_LOOP_3 + 31:
+ if (*(p + i) != ~0x7f807f80) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x7f807f80);
+ break;
+ }
+ break;
+
+
+ default:
+ if (*(p + i) != ~0xff00ff00) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff00ff00);
+ break;
+ }
+ break;
+
+ break;
+ }
+ }
+
+ if (m_len > 128 * 4) {
+ m_len -= 128 * 4;
+ p += 32 * 4;
+ } else {
+ p += (m_len >> 2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+static void ddr_write_pattern4_no_cross_talk(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ unsigned int i, n;
+ unsigned int m_len = m_length;
+
+ p = (unsigned int *)buff;
+
+ while (m_len) {
+ {
+ if (m_len >= 128 * 4)
+ n = 32 * 4;
+ else
+ n = m_len >> 2;
+
+ for (i = 0; i < n; i++) {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p);
+#endif
+ switch (i) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ *(p + i) = 0xff00ff00;
+ break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ *(p + i) = 0xffff0000;
+ break;
+
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ *(p + i) = 0xff000000;
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ *(p + i) = 0xff00ffff;
+ break;
+
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+ *(p + i) = 0xff00ffff;
+ break;
+ case 20:
+ case 21:
+ case 22:
+ case 23:
+ *(p + i) = 0xff0000ff;
+ break;
+ case 24:
+ case 25:
+ case 26:
+ case 27:
+ *(p + i) = 0xffff0000;
+ break;
+
+ case 28:
+ case 29:
+ case 30:
+ case 31:
+ *(p + i) = 0x00ff00ff;
+ break;
+ case DDR_PATTERN_LOOP_1 + 0:
+ case DDR_PATTERN_LOOP_1 + 1:
+ case DDR_PATTERN_LOOP_1 + 2:
+ case DDR_PATTERN_LOOP_1 + 3:
+ *(p + i) = ~0xff00ff00;
+ break;
+ case DDR_PATTERN_LOOP_1 + 4:
+ case DDR_PATTERN_LOOP_1 + 5:
+ case DDR_PATTERN_LOOP_1 + 6:
+ case DDR_PATTERN_LOOP_1 + 7:
+ *(p + i) = ~0xffff0000;
+ break;
+ case DDR_PATTERN_LOOP_1 + 8:
+ case DDR_PATTERN_LOOP_1 + 9:
+ case DDR_PATTERN_LOOP_1 + 10:
+ case DDR_PATTERN_LOOP_1 + 11:
+ *(p + i) = ~0xff000000;
+ break;
+ case DDR_PATTERN_LOOP_1 + 12:
+ case DDR_PATTERN_LOOP_1 + 13:
+ case DDR_PATTERN_LOOP_1 + 14:
+ case DDR_PATTERN_LOOP_1 + 15:
+ *(p + i) = ~0xff00ffff;
+ break;
+ case DDR_PATTERN_LOOP_1 + 16:
+ case DDR_PATTERN_LOOP_1 + 17:
+ case DDR_PATTERN_LOOP_1 + 18:
+ case DDR_PATTERN_LOOP_1 + 19:
+ *(p + i) = ~0xff00ffff;
+ break;
+ case DDR_PATTERN_LOOP_1 + 20:
+ case DDR_PATTERN_LOOP_1 + 21:
+ case DDR_PATTERN_LOOP_1 + 22:
+ case DDR_PATTERN_LOOP_1 + 23:
+ *(p + i) = ~0xff00ffff;
+ break;
+ case DDR_PATTERN_LOOP_1 + 24:
+ case DDR_PATTERN_LOOP_1 + 25:
+ case DDR_PATTERN_LOOP_1 + 26:
+ case DDR_PATTERN_LOOP_1 + 27:
+ *(p + i) = ~0xffff0000;
+ break;
+ case DDR_PATTERN_LOOP_1 + 28:
+ case DDR_PATTERN_LOOP_1 + 29:
+ case DDR_PATTERN_LOOP_1 + 30:
+ case DDR_PATTERN_LOOP_1 + 31:
+ *(p + i) = ~0x00ff00ff;
+ break;
+
+ case DDR_PATTERN_LOOP_2 + 0:
+ case DDR_PATTERN_LOOP_2 + 1:
+ case DDR_PATTERN_LOOP_2 + 2:
+ case DDR_PATTERN_LOOP_2 + 3:
+ *(p + i) = 0x00ff0000;
+ break;
+ case DDR_PATTERN_LOOP_2 + 4:
+ case DDR_PATTERN_LOOP_2 + 5:
+ case DDR_PATTERN_LOOP_2 + 6:
+ case DDR_PATTERN_LOOP_2 + 7:
+ *(p + i) = 0xff000000;
+ break;
+ case DDR_PATTERN_LOOP_2 + 8:
+ case DDR_PATTERN_LOOP_2 + 9:
+ case DDR_PATTERN_LOOP_2 + 10:
+ case DDR_PATTERN_LOOP_2 + 11:
+ *(p + i) = 0x0000ffff;
+ break;
+ case DDR_PATTERN_LOOP_2 + 12:
+ case DDR_PATTERN_LOOP_2 + 13:
+ case DDR_PATTERN_LOOP_2 + 14:
+ case DDR_PATTERN_LOOP_2 + 15:
+ *(p + i) = 0x000000ff;
+ break;
+ case DDR_PATTERN_LOOP_2 + 16:
+ case DDR_PATTERN_LOOP_2 + 17:
+ case DDR_PATTERN_LOOP_2 + 18:
+ case DDR_PATTERN_LOOP_2 + 19:
+ *(p + i) = 0x00ff00ff;
+ break;
+ case DDR_PATTERN_LOOP_2 + 20:
+ case DDR_PATTERN_LOOP_2 + 21:
+ case DDR_PATTERN_LOOP_2 + 22:
+ case DDR_PATTERN_LOOP_2 + 23:
+ *(p + i) = 0xff00ff00;
+ break;
+ case DDR_PATTERN_LOOP_2 + 24:
+ case DDR_PATTERN_LOOP_2 + 25:
+ case DDR_PATTERN_LOOP_2 + 26:
+ case DDR_PATTERN_LOOP_2 + 27:
+ *(p + i) = 0xff00ffff;
+ break;
+ case DDR_PATTERN_LOOP_2 + 28:
+ case DDR_PATTERN_LOOP_2 + 29:
+ case DDR_PATTERN_LOOP_2 + 30:
+ case DDR_PATTERN_LOOP_2 + 31:
+ *(p + i) = 0xff00ff00;
+ break;
+ case DDR_PATTERN_LOOP_3 + 0:
+ case DDR_PATTERN_LOOP_3 + 1:
+ case DDR_PATTERN_LOOP_3 + 2:
+ case DDR_PATTERN_LOOP_3 + 3:
+ *(p + i) = ~0x00ff0000;
+ break;
+ case DDR_PATTERN_LOOP_3 + 4:
+ case DDR_PATTERN_LOOP_3 + 5:
+ case DDR_PATTERN_LOOP_3 + 6:
+ case DDR_PATTERN_LOOP_3 + 7:
+ *(p + i) = ~0xff000000;
+ break;
+ case DDR_PATTERN_LOOP_3 + 8:
+ case DDR_PATTERN_LOOP_3 + 9:
+ case DDR_PATTERN_LOOP_3 + 10:
+ case DDR_PATTERN_LOOP_3 + 11:
+ *(p + i) = ~0x0000ffff;
+ break;
+ case DDR_PATTERN_LOOP_3 + 12:
+ case DDR_PATTERN_LOOP_3 + 13:
+ case DDR_PATTERN_LOOP_3 + 14:
+ case DDR_PATTERN_LOOP_3 + 15:
+ *(p + i) = ~0x000000ff;
+ break;
+ case DDR_PATTERN_LOOP_3 + 16:
+ case DDR_PATTERN_LOOP_3 + 17:
+ case DDR_PATTERN_LOOP_3 + 18:
+ case DDR_PATTERN_LOOP_3 + 19:
+ *(p + i) = ~0x00ff00ff;
+ break;
+ case DDR_PATTERN_LOOP_3 + 20:
+ case DDR_PATTERN_LOOP_3 + 21:
+ case DDR_PATTERN_LOOP_3 + 22:
+ case DDR_PATTERN_LOOP_3 + 23:
+ *(p + i) = ~0xff00ff00;
+ break;
+ case DDR_PATTERN_LOOP_3 + 24:
+ case DDR_PATTERN_LOOP_3 + 25:
+ case DDR_PATTERN_LOOP_3 + 26:
+ case DDR_PATTERN_LOOP_3 + 27:
+ *(p + i) = ~0xff00ffff;
+ break;
+ case DDR_PATTERN_LOOP_3 + 28:
+ case DDR_PATTERN_LOOP_3 + 29:
+ case DDR_PATTERN_LOOP_3 + 30:
+ case DDR_PATTERN_LOOP_3 + 31:
+ *(p + i) = ~0xff00ff00;
+ break;
+ }
+ }
+
+ if (m_len > (128 * 4)) {
+ m_len -= (128 * 4);
+ p += 32 * 4;
+ } else {
+ p += (m_len >> 2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+static void ddr_read_pattern4_no_cross_talk(void *buff, unsigned int m_length)
+{
+ unsigned int *p;
+ unsigned int i, n;
+ unsigned int m_len = m_length;
+
+ p = (unsigned int *)buff;
+ while (m_len) {
+ {
+ if (m_len >= 128 * 4)
+ n = 32 * 4;
+ else
+ n = m_len >> 2;
+
+ for (i = 0; i < n; i++) {
+#ifdef DDR_PREFETCH_CACHE
+ ddr_pld_cache(p);
+#endif
+ if ((error_outof_count_flag) && (error_count)) {
+ printf("Error data out of count");
+ m_len = 0;
+ break;
+ }
+ switch (i) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ if (*(p + i) != 0xff00ff00) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff00ff00);
+ }
+ break;
+ case 4:
+ case 5:
+ case 6:
+ case 7:
+ if (*(p + i) != 0xffff0000) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xffff0000);
+ }
+ break;
+
+ case 8:
+ case 9:
+ case 10:
+ case 11:
+ if (*(p + i) != 0xff000000) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff000000);
+ }
+ break;
+ case 12:
+ case 13:
+ case 14:
+ case 15:
+ if (*(p + i) != 0xff00ffff) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff00ffff);
+ }
+ break;
+
+ case 16:
+ case 17:
+ case 18:
+ case 19:
+ if (*(p + i) != 0xff00ffff) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff00ffff);
+ }
+ break;
+ case 20:
+ case 21:
+ case 22:
+ case 23:
+ if (*(p + i) != 0xff0000ff) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff0000ff);
+ }
+ break;
+ case 24:
+ case 25:
+ case 26:
+ case 27:
+ if (*(p + i) != 0xffff0000) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xffff0000);
+ }
+ break;
+
+ case 28:
+ case 29:
+ case 30:
+ case 31:
+ if (*(p + i) != 0x00ff00ff) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00ff00ff);
+ }
+ break;
+ case DDR_PATTERN_LOOP_1 + 0:
+ case DDR_PATTERN_LOOP_1 + 1:
+ case DDR_PATTERN_LOOP_1 + 2:
+ case DDR_PATTERN_LOOP_1 + 3:
+ if (*(p + i) != ~0xff00ff00) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff00ff00);
+ }
+ break;
+ case DDR_PATTERN_LOOP_1 + 4:
+ case DDR_PATTERN_LOOP_1 + 5:
+ case DDR_PATTERN_LOOP_1 + 6:
+ case DDR_PATTERN_LOOP_1 + 7:
+ if (*(p + i) != ~0xffff0000) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xffff0000);
+ }
+ break;
+ case DDR_PATTERN_LOOP_1 + 8:
+ case DDR_PATTERN_LOOP_1 + 9:
+ case DDR_PATTERN_LOOP_1 + 10:
+ case DDR_PATTERN_LOOP_1 + 11:
+ if (*(p + i) != ~0xff000000) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff000000);
+ }
+ break;
+ case DDR_PATTERN_LOOP_1 + 12:
+ case DDR_PATTERN_LOOP_1 + 13:
+ case DDR_PATTERN_LOOP_1 + 14:
+ case DDR_PATTERN_LOOP_1 + 15:
+ if (*(p + i) != ~0xff00ffff) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff00ffff);
+ }
+ break;
+ case DDR_PATTERN_LOOP_1 + 16:
+ case DDR_PATTERN_LOOP_1 + 17:
+ case DDR_PATTERN_LOOP_1 + 18:
+ case DDR_PATTERN_LOOP_1 + 19:
+ if (*(p + i) != ~0xff00ffff) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff00ffff);
+ }
+ break;
+ case DDR_PATTERN_LOOP_1 + 20:
+ case DDR_PATTERN_LOOP_1 + 21:
+ case DDR_PATTERN_LOOP_1 + 22:
+ case DDR_PATTERN_LOOP_1 + 23:
+ if (*(p + i) != ~0xff00ffff) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff00ffff);
+ }
+ break;
+ case DDR_PATTERN_LOOP_1 + 24:
+ case DDR_PATTERN_LOOP_1 + 25:
+ case DDR_PATTERN_LOOP_1 + 26:
+ case DDR_PATTERN_LOOP_1 + 27:
+ if (*(p + i) != ~0xffff0000) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xffff0000);
+ }
+ break;
+ case DDR_PATTERN_LOOP_1 + 28:
+ case DDR_PATTERN_LOOP_1 + 29:
+ case DDR_PATTERN_LOOP_1 + 30:
+ case DDR_PATTERN_LOOP_1 + 31:
+ if (*(p + i) != ~0x00ff00ff) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00ff00ff);
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 0:
+ case DDR_PATTERN_LOOP_2 + 1:
+ case DDR_PATTERN_LOOP_2 + 2:
+ case DDR_PATTERN_LOOP_2 + 3:
+ if (*(p + i) != 0x00ff0000) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00ff0000);
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 4:
+ case DDR_PATTERN_LOOP_2 + 5:
+ case DDR_PATTERN_LOOP_2 + 6:
+ case DDR_PATTERN_LOOP_2 + 7:
+ if (*(p + i) != 0xff000000) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff000000);
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 8:
+ case DDR_PATTERN_LOOP_2 + 9:
+ case DDR_PATTERN_LOOP_2 + 10:
+ case DDR_PATTERN_LOOP_2 + 11:
+ if (*(p + i) != 0x0000ffff) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x0000ffff);
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 12:
+ case DDR_PATTERN_LOOP_2 + 13:
+ case DDR_PATTERN_LOOP_2 + 14:
+ case DDR_PATTERN_LOOP_2 + 15:
+ if (*(p + i) != 0x000000ff) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x000000ff);
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 16:
+ case DDR_PATTERN_LOOP_2 + 17:
+ case DDR_PATTERN_LOOP_2 + 18:
+ case DDR_PATTERN_LOOP_2 + 19:
+ if (*(p + i) != 0x00ff00ff) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0x00ff00ff);
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 20:
+ case DDR_PATTERN_LOOP_2 + 21:
+ case DDR_PATTERN_LOOP_2 + 22:
+ case DDR_PATTERN_LOOP_2 + 23:
+ if (*(p + i) != 0xff00ff00) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff00ff00);
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 24:
+ case DDR_PATTERN_LOOP_2 + 25:
+ case DDR_PATTERN_LOOP_2 + 26:
+ case DDR_PATTERN_LOOP_2 + 27:
+ if (*(p + i) != 0xff00ffff) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff00ffff);
+ }
+ break;
+ case DDR_PATTERN_LOOP_2 + 28:
+ case DDR_PATTERN_LOOP_2 + 29:
+ case DDR_PATTERN_LOOP_2 + 30:
+ case DDR_PATTERN_LOOP_2 + 31:
+ if (*(p + i) != 0xff00ff00) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), 0xff00ff00);
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 0:
+ case DDR_PATTERN_LOOP_3 + 1:
+ case DDR_PATTERN_LOOP_3 + 2:
+ case DDR_PATTERN_LOOP_3 + 3:
+ if (*(p + i) != ~0x00ff0000) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00ff0000);
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 4:
+ case DDR_PATTERN_LOOP_3 + 5:
+ case DDR_PATTERN_LOOP_3 + 6:
+ case DDR_PATTERN_LOOP_3 + 7:
+ if (*(p + i) != ~0xff000000) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff000000);
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 8:
+ case DDR_PATTERN_LOOP_3 + 9:
+ case DDR_PATTERN_LOOP_3 + 10:
+ case DDR_PATTERN_LOOP_3 + 11:
+ if (*(p + i) != ~0x0000ffff) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x0000ffff);
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 12:
+ case DDR_PATTERN_LOOP_3 + 13:
+ case DDR_PATTERN_LOOP_3 + 14:
+ case DDR_PATTERN_LOOP_3 + 15:
+ if (*(p + i) != ~0x000000ff) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x000000ff);
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 16:
+ case DDR_PATTERN_LOOP_3 + 17:
+ case DDR_PATTERN_LOOP_3 + 18:
+ case DDR_PATTERN_LOOP_3 + 19:
+ if (*(p + i) != ~0x00ff00ff) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0x00ff00ff);
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 20:
+ case DDR_PATTERN_LOOP_3 + 21:
+ case DDR_PATTERN_LOOP_3 + 22:
+ case DDR_PATTERN_LOOP_3 + 23:
+ if (*(p + i) != ~0xff00ff00) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff00ff00);
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 24:
+ case DDR_PATTERN_LOOP_3 + 25:
+ case DDR_PATTERN_LOOP_3 + 26:
+ case DDR_PATTERN_LOOP_3 + 27:
+ if (*(p + i) != ~0xff00ffff) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff00ffff);
+ }
+ break;
+ case DDR_PATTERN_LOOP_3 + 28:
+ case DDR_PATTERN_LOOP_3 + 29:
+ case DDR_PATTERN_LOOP_3 + 30:
+ case DDR_PATTERN_LOOP_3 + 31:
+ if (*(p + i) != ~0xff00ff00) {
+ error_count++;
+ printf("Error data [0x%08x] at offset 0x%08x[0x%08x]\n", *(p + i), p_convter_int(p + i), ~0xff00ff00);
+ }
+ break;
+ }
+ }
+
+ if (m_len > (128 * 4)) {
+ m_len -= (128 * 4);
+ p += 32 * 4;
+ } else {
+ p += (m_len >> 2);
+ m_len = 0;
+ break;
+ }
+ }
+ }
+}
+
+int do_ddr_test(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ char *endp;
+ unsigned int loop = 1;
+ unsigned int lflag = 0;
+ unsigned int start_addr = DDR_TEST_START_ADDR;
+ unsigned int test_size = DDR_TEST_SIZE;
+ unsigned int simple_pattern_flag = 1;
+ unsigned int cross_talk_pattern_flag = 1;
+ unsigned int old_pattern_flag = 1;
+ unsigned int print_flag = 1;
+
+ print_flag = 1;
+ error_outof_count_flag = 0;
+ error_count = 0;
+ printf("\nargc== 0x%08x\n", argc);
+ int i;
+ for (i = 0; i < argc; i++)
+ printf("\nargv[%d]=%s\n", i, argv[i]);
+ if (!argc)
+ goto DDR_TEST_START;
+ if (argc > 1) {
+ if (strcmp(argv[1], "l") == 0) {
+ lflag = 1;
+ } else if (strcmp(argv[1], "h") == 0) {
+ goto usage;
+ } else {
+ loop = simple_strtoull_ddr(argv[1], &endp, 10);
+ if (*argv[1] == 0 || *endp != 0)
+ loop = 1;
+ }
+ }
+ if (argc == 1) {
+ start_addr = DDR_TEST_START_ADDR;
+ loop = 1;
+ }
+ if (argc > 2) {
+ start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
+ if (*argv[2] == 0 || *endp != 0)
+ start_addr = DDR_TEST_START_ADDR;
+ }
+ if (argc > 3) {
+ test_size = simple_strtoull_ddr(argv[3], &endp, 16);
+ if (*argv[3] == 0 || *endp != 0)
+ test_size = DDR_TEST_SIZE;
+ }
+ if (test_size < 0x1000)
+ test_size = DDR_TEST_SIZE;
+
+ old_pattern_flag = 1;
+ simple_pattern_flag = 1;
+ cross_talk_pattern_flag = 1;
+ if (argc == 2) {
+ if ((strcmp(argv[1], "s") == 0)) {
+ simple_pattern_flag = 1;
+ old_pattern_flag = 0;
+ cross_talk_pattern_flag = 0;
+ } else if ((strcmp(argv[1], "c") == 0)) {
+ simple_pattern_flag = 0;
+ old_pattern_flag = 0;
+ cross_talk_pattern_flag = 1;
+ } else if ((strcmp(argv[1], "e") == 0)) {
+ error_outof_count_flag = 1;
+ }
+ }
+ if (argc > 2) {
+ if ((strcmp(argv[1], "n") == 0) || (strcmp(argv[2], "n") == 0))
+ print_flag = 0;
+ if ((strcmp(argv[1], "p") == 0) || (strcmp(argv[2], "p") == 0))
+ copy_test_flag = 1;
+ if ((strcmp(argv[1], "s") == 0) || (strcmp(argv[2], "s") == 0)) {
+ simple_pattern_flag = 1;
+ old_pattern_flag = 0;
+ cross_talk_pattern_flag = 0;
+ } else if ((strcmp(argv[1], "c") == 0) || (strcmp(argv[2], "c") == 0)) {
+ simple_pattern_flag = 0;
+ old_pattern_flag = 0;
+ cross_talk_pattern_flag = 1;
+ } else if ((strcmp(argv[1], "e") == 0) || (strcmp(argv[2], "e") == 0)) {
+ error_outof_count_flag = 1;
+ }
+ }
+ if (argc > 3) {
+ if ((strcmp(argv[1], "p") == 0) || (strcmp(argv[2], "p") == 0) || (strcmp(argv[3], "p") == 0))
+ copy_test_flag = 1;
+ if ((strcmp(argv[1], "n") == 0) || (strcmp(argv[2], "n") == 0) || (strcmp(argv[3], "n") == 0))
+ print_flag = 0;
+ if ((strcmp(argv[1], "s") == 0) || (strcmp(argv[2], "s") == 0) || (strcmp(argv[3], "s") == 0)) {
+ simple_pattern_flag = 1;
+ old_pattern_flag = 0;
+ cross_talk_pattern_flag = 0;
+ }
+ if ((strcmp(argv[1], "c") == 0) || (strcmp(argv[2], "c") == 0) || (strcmp(argv[3], "c") == 0)) {
+ simple_pattern_flag = 0;
+ old_pattern_flag = 0;
+ cross_talk_pattern_flag = 1;
+ }
+ if ((strcmp(argv[1], "e") == 0) || (strcmp(argv[2], "e") == 0) || (strcmp(argv[3], "e") == 0))
+ error_outof_count_flag = 1;
+ }
+
+DDR_TEST_START:
+
+ do {
+ if (lflag)
+ loop = 888;
+
+ if (old_pattern_flag == 1) {
+ {
+ if (print_flag)
+ printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);
+ ddr_write((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\nEnd write. ");
+ printf("\nStart 1st reading... ");
+ }
+ ddr_read((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\nEnd 1st read. ");
+ printf("\nStart 2nd reading... ");
+ }
+ ddr_read((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\nEnd 2nd read. ");
+ printf("\nStart 3rd reading... ");
+ }
+ ddr_read((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag)
+ printf("\nEnd 3rd read. \n");
+
+ if (copy_test_flag) {
+ if (print_flag)
+ printf("\n copy_test_flag = 1,start copy test. \n");
+ ddr_test_copy((void *)(int_convter_p(start_addr + test_size / 2)), (void *)(int_convter_p(start_addr)), test_size / 2);
+ ddr_read((void *)(int_convter_p(start_addr + test_size / 2)), test_size / 2);
+ ddr_read((void *)(int_convter_p(start_addr + test_size / 2)), test_size / 2);
+ }
+ }
+ {
+ if (print_flag) {
+ printf("\nStart *4 normal pattern. ");
+ printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);
+ }
+ ddr_write4((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\nEnd write. ");
+ printf("\nStart 1st reading... ");
+ }
+ ddr_read4((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\nEnd 1st read. ");
+ printf("\nStart 2nd reading... ");
+ }
+ ddr_read4((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\nEnd 2nd read. ");
+ printf("\nStart 3rd reading... ");
+ }
+ ddr_read4((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag)
+ printf("\rEnd 3rd read. \n");
+ if (copy_test_flag) {
+ ddr_test_copy((void *)(int_convter_p(start_addr + test_size / 2)), (void *)(int_convter_p(start_addr)), test_size / 2);
+ ddr_read4((void *)(int_convter_p(start_addr + test_size / 2)), test_size / 2);
+ ddr_read4((void *)(int_convter_p(start_addr + test_size / 2)), test_size / 2);
+ }
+ }
+ }
+
+ if (simple_pattern_flag == 1) {
+ if (print_flag) {
+ printf("\nStart *4 no cross talk pattern. ");
+ printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);
+ }
+ ddr_write_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\rEnd write. ");
+ printf("\rStart 1st reading... ");
+ }
+ ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\rEnd 1st read. ");
+ printf("\rStart 2nd reading... ");
+ }
+ ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\rEnd 2nd read. ");
+ printf("\rStart 3rd reading... ");
+ }
+ ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag)
+ printf("\rEnd 3rd read. \n");
+
+ if (copy_test_flag) {
+ ddr_test_copy((void *)(int_convter_p(start_addr + test_size / 2)), (void *)(int_convter_p(start_addr)), test_size / 2);
+ ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr + test_size / 2)), test_size / 2);
+ ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr + test_size / 2)), test_size / 2);
+ }
+ }
+
+ if (cross_talk_pattern_flag == 1) {
+ if (print_flag) {
+ printf("\nStart *4 cross talk pattern p. ");
+ printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);
+ }
+ ddr_write_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\rEnd write. ");
+ printf("\rStart 1st reading... ");
+ }
+ ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\rEnd 1st read. ");
+ printf("\rStart 2nd reading... ");
+ }
+ ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\rEnd 2nd read. ");
+ printf("\rStart 3rd reading... ");
+ }
+ ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\rEnd 3rd read. \n");
+
+ printf("\nStart *4 cross talk pattern n. ");
+ printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);
+ }
+ ddr_write_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\rEnd write. ");
+ printf("\rStart 1st reading... ");
+ }
+ ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\rEnd 1st read. ");
+ printf("\rStart 2nd reading... ");
+ }
+ ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\rEnd 2nd read. ");
+ printf("\rStart 3rd reading... ");
+ }
+ ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\rEnd 3rd read. \n");
+
+ ///*
+ printf("\nStart *4 cross talk pattern p2. ");
+ printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);
+ }
+ ddr_write_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\rEnd write. ");
+ printf("\rStart 1st reading... ");
+ }
+ ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\rEnd 1st read. ");
+ printf("\rStart 2nd reading... ");
+ }
+ ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\rEnd 2nd read. ");
+ printf("\rStart 3rd reading... ");
+ }
+ ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\rEnd 3rd read. \n");
+
+ printf("\nStart *4 cross talk pattern n2. ");
+ printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + test_size);
+ }
+ ddr_write_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\rEnd write. ");
+ printf("\rStart 1st reading... ");
+ }
+ ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\rEnd 1st read. ");
+ printf("\rStart 2nd reading... ");
+ }
+ ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag) {
+ printf("\rEnd 2nd read. ");
+ printf("\rStart 3rd reading... ");
+ }
+ ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), test_size);
+ if (print_flag)
+ printf("\rEnd 3rd read. \n");
+
+ if (copy_test_flag) {
+ ddr_test_copy((void *)(int_convter_p(start_addr + test_size / 2)), (void *)(int_convter_p(start_addr)), test_size / 2);
+ ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr + test_size / 2)), test_size / 2);
+ ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr + test_size / 2)), test_size / 2);
+ }
+ }
+
+ if (print_flag)
+ printf("\nError count==0x%08x", error_count);
+ } while (--loop);
+
+ printf("\rEnd ddr test. \n");
+
+ return 0;
+
+usage:
+ cmd_usage(cmdtp);
+ return 1;
+}
+
+U_BOOT_CMD(
+ ddrtest, 5, 1, do_ddr_test,
+ "DDR test function",
+ "ddrtest [LOOP] [ADDR].Default address is 0x8d000000\n"
+ );
+
+int do_ddr_special_test(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ char *endp;
+ unsigned int loop = 1;
+ unsigned int lflag = 0;
+ unsigned int start_addr = DDR_TEST_START_ADDR;
+ unsigned int test_addr = DDR_TEST_START_ADDR;
+ unsigned int test_size = DDR_TEST_SIZE;
+ unsigned int write_times = 1;
+ unsigned int read_times = 3;
+
+ unsigned int print_flag = 1;
+
+ print_flag = 1;
+ error_outof_count_flag = 0;
+ error_count = 0;
+ printf("\nargc== 0x%08x\n", argc);
+ int i;
+ for (i = 0; i < argc; i++)
+ printf("\nargv[%d]=%s\n", i, argv[i]);
+
+ if (strcmp(argv[1], "l") == 0) {
+ lflag = 1;
+ } else if (strcmp(argv[1], "h") == 0) {
+ goto usage;
+ } else {
+ loop = simple_strtoull_ddr(argv[1], &endp, 10);
+ if (*argv[1] == 0 || *endp != 0)
+ loop = 1;
+ }
+
+ if (argc == 1) {
+ start_addr = DDR_TEST_START_ADDR;
+ loop = 1;
+ }
+ if (argc > 2) {
+ start_addr = simple_strtoull_ddr(argv[2], &endp, 16);
+ if (*argv[2] == 0 || *endp != 0)
+ start_addr = DDR_TEST_START_ADDR;
+ }
+ if (argc > 3) {
+ test_size = simple_strtoull_ddr(argv[3], &endp, 16);
+ if (*argv[3] == 0 || *endp != 0)
+ test_size = DDR_TEST_SIZE;
+ }
+ if (test_size < 0x1000)
+ test_size = DDR_TEST_SIZE;
+ if (argc > 4) {
+ write_times = simple_strtoull_ddr(argv[4], &endp, 16);
+ if (*argv[4] == 0 || *endp != 0)
+ write_times = 0;
+ }
+ if (argc > 5) {
+ read_times = simple_strtoull_ddr(argv[5], &endp, 16);
+ if (*argv[5] == 0 || *endp != 0)
+ read_times = 0;
+ }
+ unsigned int base_pattern = 1;
+ unsigned int inc_flag = 1;
+ if (argc > 6) {
+ base_pattern = simple_strtoull_ddr(argv[6], &endp, 16);
+ if (*argv[6] == 0 || *endp != 0)
+ base_pattern = 0;
+ }
+ if (argc > 7) {
+ inc_flag = simple_strtoull_ddr(argv[7], &endp, 16);
+ if (*argv[7] == 0 || *endp != 0)
+ inc_flag = 0;
+ }
+
+
+ unsigned int count = 1;
+ unsigned int test_val = 1;
+
+ do {
+ if (lflag)
+ loop = 888;
+
+ if (1) {
+ for (i = 0; i < write_times; ) {
+ i++;
+ printf("\nwrite_times==0x%08x \n", ((unsigned int)i));
+ test_addr = start_addr;
+ test_val = base_pattern;
+ count = (test_size >> 2);
+ do {
+ writel(test_val, (unsigned long)test_addr);
+ test_addr = test_addr + 4;
+ if (inc_flag)
+ test_val = test_val + 1;
+ } while (count--);
+ }
+
+ for (i = 0; i < read_times; ) {
+ i++;
+ printf("\nread_times==0x%08x \n", ((unsigned int)i));
+ test_addr = start_addr;
+ test_val = base_pattern;
+ count = (test_size >> 2);
+
+ do {
+ if (test_val != (readl((unsigned long)test_addr)))
+
+ printf("\nadd==0x%08x,pattern==0x%08x,read==0x%08x \n", ((unsigned int)test_addr), ((unsigned int)test_val), (readl((unsigned int)test_addr)));
+ test_addr = test_addr + 4;
+ if (inc_flag)
+ test_val = test_val + 1;
+ } while (count--);
+ }
+ }
+
+
+
+ if (print_flag)
+ printf("\nError count==0x%08x", error_count);
+ } while (--loop);
+
+ printf("\rEnd ddr test. \n");
+
+ return 0;
+
+usage:
+ cmd_usage(cmdtp);
+ return 1;
+}
+U_BOOT_CMD(
+ ddr_spec_test, 8, 1, do_ddr_special_test,
+ "DDR test function",
+ "ddrtest [LOOP] [ADDR] [size] [write_times] [read times] [pattern] [inc].ddr_spec_test 1 0x1080000 0x200000 1 3 1 1 \n"
+ );
+
+int ddr_test_s_cross_talk_pattern(int ddr_test_size)
+{
+#define TEST_OFFSET 0 //0X40000000
+ unsigned int start_addr = test_start_addr;
+
+ error_outof_count_flag = 1;
+
+ error_count = 0;
+
+#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
+ training_pattern_flag = 0;
+#endif
+ if (training_pattern_flag) {
+#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
+ ddr_test_gx_training_pattern(ddr_test_size);
+#endif
+ if (error_count)
+ return 1;
+ else
+ return 0;
+ } else {
+#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
+ ddr_test_gx_training_pattern(ddr_test_size);
+#endif
+ }
+
+ {
+ printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
+ ddr_write((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\nEnd write. ");
+ printf("\nStart 1st reading... ");
+ ddr_read((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\nEnd 1st read. ");
+ printf("\nStart 2nd reading... ");
+ ddr_read((void *)(int_convter_p(start_addr)), ddr_test_size);
+ if (error_count)
+ return error_count;
+ printf("\nStart writing pattern4 at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
+ ddr_write4((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\nEnd write. ");
+ printf("\nStart 1st reading... ");
+ ddr_read4((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\nEnd 1st read. ");
+ printf("\nStart 2nd reading... ");
+ ddr_read4((void *)(int_convter_p(start_addr)), ddr_test_size);
+
+ if (error_count)
+ return error_count;
+ printf("\nStart *4 no cross talk pattern. ");
+ printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
+ ddr_write_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\nEnd write. ");
+ printf("\nStart 1st reading... ");
+ ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\nEnd 1st read. ");
+ printf("\nStart 2nd reading... ");
+ ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
+ }
+
+ if (error_count)
+ return error_count;
+ {
+ printf("\nStart *4 cross talk pattern p. ");
+ printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
+ ddr_write_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd write. ");
+ printf("\rStart 1st reading... ");
+ ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd 1st read. ");
+ printf("\rStart 2nd reading... ");
+ ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd 2nd read. ");
+
+ if (error_count)
+ return error_count;
+ printf("\nStart *4 cross talk pattern n. ");
+ printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
+ ddr_write_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd write. ");
+ printf("\rStart 1st reading... ");
+ ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd 1st read. ");
+ printf("\rStart 2nd reading... ");
+ ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd 2nd read. ");
+ }
+ if (error_count)
+ return error_count;
+ {
+ printf("\nStart *4 cross talk pattern p2. ");
+ printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
+ ddr_write_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd write. ");
+ printf("\rStart 1st reading... ");
+ ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd 1st read. ");
+ printf("\rStart 2nd reading... ");
+ ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd 2nd read. ");
+
+ if (error_count)
+ return error_count;
+ printf("\nStart *4 cross talk pattern n. ");
+ printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
+ ddr_write_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd write. ");
+ printf("\rStart 1st reading... ");
+ ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd 1st read. ");
+ printf("\rStart 2nd reading... ");
+ ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd 2nd read. ");
+
+ if (copy_test_flag) {
+ if (error_count)
+ return error_count;
+ printf("\n start copy test ... ");
+ ddr_test_copy((void *)(int_convter_p(start_addr + ddr_test_size / 2)), (void *)(int_convter_p(start_addr)), ddr_test_size / 2);
+ ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr + ddr_test_size / 2)), ddr_test_size / 2);
+ ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr + ddr_test_size / 2)), ddr_test_size / 2);
+ }
+ }
+
+ if (error_count)
+ return 1;
+ else
+ return 0;
+}
+
+int ddr_test_s_cross_talk_pattern_quick_retrun(int ddr_test_size)
+{
+ error_outof_count_flag = 1;
+#define TEST_OFFSET 0 //0X40000000
+ unsigned int start_addr = test_start_addr;
+
+ error_outof_count_flag = 1;
+
+ error_count = 0;
+
+#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
+ training_pattern_flag = 0;
+#endif
+ if (training_pattern_flag) {
+#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
+ ddr_test_gx_training_pattern(ddr_test_size);
+#endif
+ if (error_count)
+ return 1;
+ else
+ return 0;
+ } else {
+#if (CONFIG_DDR_PHY == P_DDR_PHY_GX_BABY)
+ ddr_test_gx_training_pattern(ddr_test_size);
+#endif
+ }
+
+ {
+ printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
+ ddr_write((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\nEnd write. ");
+ printf("\nStart 1st reading... ");
+ ddr_read((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\nEnd 1st read. ");
+ printf("\nStart 2nd reading... ");
+ ddr_read((void *)(int_convter_p(start_addr)), ddr_test_size);
+
+ printf("\nStart writing pattern4 at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
+ ddr_write4((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\nEnd write. ");
+ printf("\nStart 1st reading... ");
+ ddr_read4((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\nEnd 1st read. ");
+ printf("\nStart 2nd reading... ");
+ ddr_read4((void *)(int_convter_p(start_addr)), ddr_test_size);
+
+ printf("\nStart *4 no cross talk pattern. ");
+ printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
+ ddr_write_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\nEnd write. ");
+ printf("\nStart 1st reading... ");
+ ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\nEnd 1st read. ");
+ printf("\nStart 2nd reading... ");
+ ddr_read_pattern4_no_cross_talk((void *)(int_convter_p(start_addr)), ddr_test_size);
+ }
+ {
+ printf("\nStart *4 cross talk pattern p. ");
+ printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
+ ddr_write_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd write. ");
+ printf("\rStart 1st reading... ");
+ ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd 1st read. ");
+ printf("\rStart 2nd reading... ");
+ ddr_read_pattern4_cross_talk_p((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd 2nd read. ");
+
+ printf("\nStart *4 cross talk pattern n. ");
+ printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
+ ddr_write_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd write. ");
+ printf("\rStart 1st reading... ");
+ ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd 1st read. ");
+ printf("\rStart 2nd reading... ");
+ ddr_read_pattern4_cross_talk_n((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd 2nd read. ");
+ }
+
+ {
+ printf("\nStart *4 cross talk pattern p2. ");
+ printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
+ ddr_write_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd write. ");
+ printf("\rStart 1st reading... ");
+ ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd 1st read. ");
+ printf("\rStart 2nd reading... ");
+ ddr_read_pattern4_cross_talk_p2((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd 2nd read. ");
+
+ printf("\nStart *4 cross talk pattern n. ");
+ printf("\nStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
+ ddr_write_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd write. ");
+ printf("\rStart 1st reading... ");
+ ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd 1st read. ");
+ printf("\rStart 2nd reading... ");
+ ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd 2nd read. ");
+ if (copy_test_flag) {
+ printf("\n start copy test ... ");
+ ddr_test_copy((void *)(int_convter_p(start_addr + ddr_test_size / 2)), (void *)(int_convter_p(start_addr)), ddr_test_size / 2);
+ ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr + ddr_test_size / 2)), ddr_test_size / 2);
+ ddr_read_pattern4_cross_talk_n2((void *)(int_convter_p(start_addr + ddr_test_size / 2)), ddr_test_size / 2);
+ }
+ }
+
+ if (error_count)
+ return 1;
+ else
+ return 0;
+}
+
+int do_ddr2pll_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+#if (CONFIG_DDR_PHY >= P_DDR_PHY_G12)
+ extern int do_ddr2pll_g12_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[]);
+ do_ddr2pll_g12_cmd(cmdtp, flag, argc, argv);
+ return 1;
+#endif
+}
+
+int do_ddr_uboot_new_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ //ddr_test_cmd 0x36 0x20180030 0x1 cmd_offset cmd_value value_size reset_enable
+#define DDR_STICKY_OVERRIDE_CONFIG_MESSAGE_CMD 0x1 //override config
+#define DDR_STICKY_SPECIAL_FUNCTION_CMD 0x2 //special test such as shift some bdlr or parameter or interleave test
+
+ uint32_t magic_chipid = 0; //rd_reg(P_PREG_STICKY_REG0);
+ uint32_t sticky_cmd = 0; //rd_reg(P_PREG_STICKY_REG1);
+ uint32_t cmd_offset = 0;
+ uint32_t cmd_value = 0;
+ uint32_t reset_enable = 0;
+ uint32_t value_size = 4;
+ char *endp;
+ //bit 0 trigger effect reset.
+ if ((magic_chipid) != ((DDR_STICKY_MAGIC_NUMBER + DDR_CHIP_ID) & 0xffff0000))
+ //magic number not match
+ printf("sticky0 magic not match\n");
+
+ printf("\nargc== 0x%08x\n", argc);
+ int i;
+ for (i = 0; i < argc; i++)
+ printf("\nargv[%d]=%s\n", i, argv[i]);
+
+ if (argc < 2)
+ goto usage;
+
+ magic_chipid = simple_strtoull_ddr(argv[1], &endp, 0);
+ if (*argv[1] == 0 || *endp != 0) {
+ printf("Error: Wrong format parament!\n");
+ return 1;
+ }
+ if (argc > 2) {
+ sticky_cmd = simple_strtoull_ddr(argv[2], &endp, 0);
+ if (*argv[2] == 0 || *endp != 0)
+ sticky_cmd = 0;
+ }
+
+ if (argc > 3) {
+ cmd_offset = simple_strtoull_ddr(argv[3], &endp, 0);
+ if (*argv[3] == 0 || *endp != 0)
+ cmd_offset = 0;
+ }
+ if (argc > 4) {
+ cmd_value = simple_strtoull_ddr(argv[4], &endp, 0);
+ if (*argv[4] == 0 || *endp != 0)
+ cmd_value = 0;
+ }
+ if (argc > 5) {
+ value_size = simple_strtoull_ddr(argv[5], &endp, 0);
+ if (*argv[5] == 0 || *endp != 0)
+ value_size = 4;
+ }
+ if (argc > 6) {
+ reset_enable = simple_strtoull_ddr(argv[6], &endp, 0);
+ if (*argv[6] == 0 || *endp != 0)
+ reset_enable = 0;
+ }
+ printf("cmd_offset[0x%08x}==cmd_value [0x%08x]\n", cmd_offset, cmd_value);
+ writel((magic_chipid & 0xffff0000) | (rd_reg((p_ddr_base->preg_sticky_reg0))), (p_ddr_base->preg_sticky_reg0));
+ writel(sticky_cmd, (p_ddr_base->preg_sticky_reg0 + 4));
+
+ uint32_t read_value = 0;
+ if (value_size) {
+ read_value = rd_reg((p_ddr_base->ddr_dmc_sticky0) + ((cmd_offset / 4) << 2));
+ if (value_size == 1)
+ wr_reg(((p_ddr_base->ddr_dmc_sticky0) + ((cmd_offset / 4) << 2)), ((cmd_value << ((cmd_offset % 4) * 8)) | (read_value & (~(0xff << ((cmd_offset % 4) * 8))))));
+ if (value_size == 2)
+ wr_reg(((p_ddr_base->ddr_dmc_sticky0) + ((cmd_offset / 4) << 2)), ((cmd_value << ((cmd_offset % 4) * 8)) | (read_value & (~(0xffff << ((cmd_offset % 4) * 8))))));
+ if (value_size == 4)
+ wr_reg(((p_ddr_base->ddr_dmc_sticky0) + ((cmd_offset / 4) << 2)), cmd_value);
+
+ printf("DMC_STICKY_0_ offset[0x%08x}== [0x%08x]\n", cmd_offset, readl(((p_ddr_base->ddr_dmc_sticky0) + ((cmd_offset / 4) << 2))));
+ }
+
+ printf("(p_ddr_base->preg_sticky_reg0)== [0x%08x]\n", readl((p_ddr_base->preg_sticky_reg0)));
+
+ if (reset_enable) {
+ ddr_test_watchdog_reset_system();
+
+ while (1) {
+ }
+ }
+ return 0;
+
+usage:
+ cmd_usage(cmdtp);
+
+ return 1;
+}
+
+unsigned int do_test_address_bus(volatile unsigned int *baseAddress, unsigned int nBytes)
+{
+ unsigned int addressMask = (nBytes / sizeof(unsigned int) - 1);
+ unsigned int offset;
+ unsigned int testOffset;
+
+ unsigned int pattern = (unsigned int)0xAAAAAAAA;
+ unsigned int antipattern = (unsigned int)0x55555555;
+
+ unsigned int data1, data2;
+
+ unsigned int ret = 0;
+
+ /*
+ * Write the default pattern at each of the power-of-two offsets.
+ */
+ for (offset = 1; (offset & addressMask) != 0; offset <<= 1)
+ baseAddress[offset] = pattern;
+
+ /*
+ * Check for address bits stuck high.
+ */
+ testOffset = 0;
+ baseAddress[testOffset] = antipattern;
+
+ for (offset = 1; (offset & addressMask) != 0; offset <<= 1) {
+ data1 = baseAddress[offset];
+ data2 = baseAddress[offset];
+ if (data1 != data2) {
+ printf(" memTestAddressBus - read twice different[offset]: 0x%8x-0x%8x\n", data1, data2);
+ ret = 1;
+ }
+ if (data1 != pattern) {
+ printf(" memTestAddressBus - write[0x%8x]: 0x%8x, read[0x%8x]: 0x%8x\n", \
+ offset, pattern, offset, data1);
+ ret = 1;
+ }
+ }
+
+ baseAddress[testOffset] = pattern;
+
+ /*
+ * Check for address bits stuck low or shorted.
+ */
+ for (testOffset = 1; (testOffset & addressMask) != 0; testOffset <<= 1) {
+ baseAddress[testOffset] = antipattern;
+
+ if (baseAddress[0] != pattern) {
+ printf(" memTestAddressBus2 - write baseAddress[0x%8x]: 0x%8x, read baseAddress[0]: 0x%8x\n", \
+ testOffset, antipattern, baseAddress[0]);
+ ret = 1;
+ }
+
+ for (offset = 1; (offset & addressMask) != 0; offset <<= 1) {
+ data1 = baseAddress[offset];
+ if ((data1 != pattern) && (offset != testOffset)) {
+ printf(" memTestAddressBus3 - write baseAddress[0x%8x]: 0x%8x, read baseAddress[0x%8x]: 0x%8x\n", \
+ testOffset, antipattern, testOffset, data1);
+ ret = 1;
+ }
+ }
+
+ baseAddress[testOffset] = pattern;
+ }
+
+ for (offset = 0x1; (offset <= addressMask); offset++) {
+ if (((~offset) <= addressMask)) {
+ baseAddress[offset] = pattern;
+ baseAddress[(~offset)] = antipattern;
+ }
+ }
+
+ for (offset = 0x1; (offset <= addressMask); offset++) {
+ if (((~offset) <= addressMask)) {
+ if (baseAddress[offset] != pattern) {
+ printf(" memTestAddressBus4 - write baseAddress[0x%8x]: 0x%8x, read baseAddress[0x%8x]: 0x%8x\n", \
+ offset, pattern, offset, baseAddress[offset]);
+
+ ret = 1;
+ break;
+ }
+
+ if (baseAddress[(~offset)] != antipattern) {
+ printf(" memTestAddressBus5 - write baseAddress[0x%8x]: 0x%8x, read baseAddress[0x%8x]: 0x%8x\n", \
+ ((~offset)), antipattern, ((~offset)), baseAddress[((~offset))]);
+ ret = 1;
+ break;
+ }
+ }
+ }
+
+ if (ret)
+ return ret;
+
+ for (offset = 0x1; (offset <= addressMask); offset++) {
+ {
+ pattern = ((offset << 2) - offset);
+ baseAddress[offset] = pattern;
+ }
+ }
+
+ for (offset = 0x1; (offset <= addressMask); offset++) {
+ {
+ pattern = ((offset << 2) - offset);
+ if (baseAddress[offset] != pattern) {
+ printf(" memTestAddressBus6 - write baseAddress[0x%8x]: 0x%8x, read baseAddress[0x%8x]: 0x%8x\n", \
+ offset, pattern, offset, baseAddress[offset]);
+ ret = 1;
+ break;
+ }
+ }
+ }
+
+ if (ret)
+ return ret;
+
+ for (offset = 0x1; (offset <= addressMask); offset++) {
+ {
+ pattern = ~((offset << 2) - offset);
+ baseAddress[offset] = pattern;
+ }
+ }
+
+ for (offset = 0x1; (offset <= addressMask); offset++) {
+ {
+ pattern = ~((offset << 2) - offset);
+ if (baseAddress[offset] != pattern) {
+ printf(" memTestAddressBus7 - write baseAddress[0x%8x]: 0x%8x, read baseAddress[0x%8x]: 0x%8x\n", \
+ offset, pattern, offset, baseAddress[offset]);
+ ret = 1;
+ break;
+ }
+ }
+ }
+
+
+ return ret;
+} /* memTestAddressBus() */
+
+int ddr_test_s_add_cross_talk_pattern(int ddr_test_size)
+{
+ unsigned int start_addr = test_start_addr;
+
+ error_outof_count_flag = 1;
+ error_count = 0;
+ printf("\rStart writing at 0x%08x - 0x%08x...", start_addr, start_addr + ddr_test_size);
+ ddr_write((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd write. ");
+ printf("\nStart 1st reading... ");
+ ddr_read((void *)(int_convter_p(start_addr)), ddr_test_size);
+ printf("\rEnd 1st read. ");
+ printf("\rStart 2nd reading... ");
+ ddr_read((void *)(int_convter_p(start_addr)), ddr_test_size);
+ ddr_write_full((void *)(int_convter_p(start_addr)), ddr_test_size, 0x0, 0x3);
+ printf("\rEnd write. ");
+ printf("\rStart 1st reading... ");
+ ddr_read_full((void *)(int_convter_p(start_addr)), ddr_test_size, 0, 3);
+ printf("\rEnd 1st read. ");
+ printf("\rStart 2nd reading... ");
+ ddr_read_full((void *)(int_convter_p(start_addr)), ddr_test_size, 0, 3);
+
+ printf("\rStart writing add pattern ");
+ if (do_test_address_bus((void *)(int_convter_p(start_addr)), ddr_test_size))
+ error_count++;
+
+ if (error_count)
+ return 1;
+ else
+ return 0;
+}
+
+int pll_convert_to_ddr_clk_g12a(unsigned int ddr_pll)
+{
+ unsigned int ddr_clk = 0;
+ unsigned int od_div = 0xfff;
+
+ ddr_pll = ddr_pll & 0xfffff;
+ if (((ddr_pll >> 16) & 7) == 0)
+ od_div = 2;
+ if (((ddr_pll >> 16) & 7) == 1)
+ od_div = 3;
+
+ if (((ddr_pll >> 16) & 7) == 2)
+ od_div = 4;
+
+ if (((ddr_pll >> 16) & 7) == 3)
+ od_div = 6;
+
+ if (((ddr_pll >> 16) & 7) == 4)
+ od_div = 8;
+
+ if (((ddr_pll >> 10) & 0x1f))
+ ddr_clk = 2 * ((((24 * ((ddr_pll >> 0) & 0x1ff)) / ((ddr_pll >> 10) & 0x1f)) >> ((((ddr_pll >> 19) & 0x1) == 1) ? (2) : (1)))) / od_div;
+
+ return ddr_clk;
+}
+
+int ddr_clk_convert_to_pll_g12a(unsigned int ddr_clk, unsigned char pll_bypass_en)
+{
+ uint32_t ddr_pll_vco_ctrl = 0;
+ uint32_t ddr_pll_vco_m = 0;
+ uint32_t ddr_pll_vco_n = 0;
+ uint32_t ddr_pll_vco_ctrl_od = 0;
+ uint32_t ddr_pll_vco_ctrl_od1 = 0;
+
+ ddr_pll_vco_n = 1;
+ if (pll_bypass_en == 0) {
+ if ((ddr_clk >= 4800 / 4)) {
+ ddr_pll_vco_ctrl_od = 1;
+ ddr_pll_vco_ctrl_od1 = 0x2; //0
+ ddr_pll_vco_m = (ddr_clk * 3) / 24; //6
+ } else if ((ddr_clk > 4800 / 6)) {
+ ddr_pll_vco_ctrl_od = 2;
+ ddr_pll_vco_ctrl_od1 = 0x2; //0
+ ddr_pll_vco_m = (ddr_clk * 4) / 24; //8
+ } else if ((ddr_clk > 4800 / 8)) {
+ ddr_pll_vco_ctrl_od = 3;
+ ddr_pll_vco_ctrl_od1 = 0x2; //0
+ ddr_pll_vco_m = (ddr_clk * 6) / 24; //12
+ } else if ((ddr_clk > 4800 / 12)) {
+ ddr_pll_vco_ctrl_od = 4;
+ ddr_pll_vco_ctrl_od1 = 0x2; //0
+ ddr_pll_vco_m = (ddr_clk * 8) / 24; //16
+ } else if ((ddr_clk > 360)) {
+ ddr_pll_vco_ctrl_od = 3;
+ ddr_pll_vco_ctrl_od1 = 0x3; //0
+ ddr_pll_vco_m = (ddr_clk * 12) / 24;
+ } else {
+ ddr_pll_vco_ctrl_od = 4;
+ ddr_pll_vco_ctrl_od1 = 0x3; //0
+ ddr_pll_vco_m = (ddr_clk * 16) / 24;
+ }
+ }
+ if (pll_bypass_en == 1) {
+ ddr_pll_vco_ctrl_od1 = 0x3; //0
+ if ((ddr_clk >= 800)) {
+ ddr_pll_vco_ctrl_od = 0;
+ ddr_pll_vco_m = (ddr_clk * 4) / 24;
+ } else if ((ddr_clk < 4800 / 6)) {
+ ddr_pll_vco_ctrl_od = 1;
+ ddr_pll_vco_m = (ddr_clk * 2 * 3) / 24;
+ } else if ((ddr_clk < 4800 / 8)) {
+ ddr_pll_vco_ctrl_od = 2;
+ ddr_pll_vco_m = (ddr_clk * 2 * 4) / 24;
+ } else if ((ddr_clk < 4800 / 12)) {
+ ddr_pll_vco_ctrl_od = 3;
+ ddr_pll_vco_m = (ddr_clk * 2 * 6) / 24;
+ } else if ((ddr_clk < 4800 / 16)) {
+ ddr_pll_vco_ctrl_od = 4;
+ ddr_pll_vco_m = (ddr_clk * 2 * 8) / 24;
+ }
+ }
+ ddr_pll_vco_ctrl = ddr_pll_vco_m | (ddr_pll_vco_n << 10) | (ddr_pll_vco_ctrl_od << 16) | (ddr_pll_vco_ctrl_od1 << 19);
+ return ddr_pll_vco_ctrl;
+}
+
+int pll_convert_to_ddr_clk(unsigned int ddr_pll)
+{
+ unsigned int ddr_clk = 0;
+
+ ddr_pll = ddr_pll & 0xfffff;
+
+#if (CONFIG_DDR_PHY >= P_DDR_PHY_G12)
+ ddr_clk = pll_convert_to_ddr_clk_g12a(ddr_pll);
+ return ddr_clk;
+#endif
+#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
+ if (((ddr_pll >> 16) & 0x1f))
+
+ ddr_clk = 2 * ((((24 * ((ddr_pll >> 4) & 0x1ff)) / ((ddr_pll >> 16) & 0x1f)) >> ((((ddr_pll >> 0) & 0x3) == 3) ? (2) : (((ddr_pll >> 0) & 0x3)))) >> ((((ddr_pll >> 2) & 0x3) == 3) ? (2) : (((ddr_pll >> 2) & 0x3))));
+
+#else
+ if ((ddr_pll >> 9) & 0x1f)
+ ddr_clk = 2 * (((24 * (ddr_pll & 0x1ff)) / ((ddr_pll >> 9) & 0x1f)) >> ((ddr_pll >> 16) & 0x3));
+
+#endif
+
+#if (CONFIG_DDR_PHY == P_DDR_PHY_DEFAULT)
+ if ((ddr_pll >> 9) & 0x1f)
+ ddr_clk = 2 * ((24 * (ddr_pll & 0x1ff)) / ((ddr_pll >> 9) & 0x1f)) >> ((ddr_pll >> 16) & 0x3);
+#endif
+
+ return ddr_clk;
+}
+
+int ddr_clk_convert_to_pll(unsigned int ddr_clk)
+{
+ unsigned int ddr_pll = 0x10221;
+
+#if (CONFIG_DDR_PHY >= P_DDR_PHY_G12)
+ ddr_pll = ddr_clk_convert_to_pll_g12a(ddr_clk, 0);
+ return ddr_pll;
+#endif
+
+ /* set ddr pll reg */
+ if ((ddr_clk >= 40) && (ddr_clk < 750))
+ ddr_pll = (2 << 16) | (1 << 9) | ((((ddr_clk / 6) * 6) / 12) << 0);
+ else if ((ddr_clk >= 750) && (ddr_clk < 2000))
+ ddr_pll = (1 << 16) | (1 << 9) | ((((ddr_clk / 12) * 12) / 24) << 0);
+
+#if (CONFIG_DDR_PHY == P_DDR_PHY_905X)
+ ddr_pll = 0x00104c5;
+ /* set ddr pll reg */
+ /*
+ * if ((ddr_clk >= 40) && (ddr_clk < 750)) {
+ * // OD N M
+ * ddr_pll= (2 << 2) | (1 << 16) | ((((ddr_clk/6)*6)/12) << 4);
+ * }
+ * else if((ddr_clk >= 750) && (ddr_clk < 2000)) {
+ * // OD N M
+ * ddr_pll= (1 << 2) | (1 << 16) | ((((ddr_clk/12)*12)/24) << 4);
+ * }
+ */
+ if ((ddr_clk < 200))
+ // OD1 OD N M
+ ddr_pll = (2 << 0) | (3 << 2) | (1 << 16) | ((((ddr_clk * 6) / 6) / 3) << 4);
+ else if ((ddr_clk >= 200) && (ddr_clk < 400))
+ // OD1 OD N M
+ ddr_pll = (2 << 0) | (1 << 2) | (1 << 16) | ((((ddr_clk * 6) / 6) / 6) << 4);
+ else if ((ddr_clk >= 400) && (ddr_clk < 800))
+ // OD1 OD N M
+ ddr_pll = (1 << 0) | (1 << 2) | (1 << 16) | ((((ddr_clk * 12) / 12) / 12) << 4);
+ else if ((ddr_clk >= 800) && (ddr_clk < 2000))
+ // OD1 OD N M
+ ddr_pll = (0 << 0) | (1 << 2) | (1 << 16) | ((((ddr_clk * 12) / 12) / 24) << 4);
+
+#endif
+
+#if (CONFIG_DDR_PHY == P_DDR_PHY_DEFAULT)
+ {
+ if ((ddr_clk < 750))
+ // OD N M
+ ddr_pll = (2 << 16) | (1 << 9) | (((ddr_clk / 24) * 2) << 0);
+ else if ((ddr_clk >= 750))
+ // OD N M
+ ddr_pll = (1 << 16) | (1 << 9) | ((ddr_clk / 24) << 0);
+ }
+#endif
+
+ return ddr_pll;
+}
+
+int get_ddr_clk(void)
+{
+ unsigned int ddr_clk = 10;
+ unsigned int ddr_pll = 0;
+
+ if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_G12A)
+ || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_G12B)
+ || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_TL1)
+ || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_SM1)
+ || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_TM2)
+ || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_C1)
+ || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_SC2)
+ || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T7)) {
+ ddr_pll = rd_reg(p_ddr_base->ddr_pll_base_address);
+ ddr_pll = ddr_pll & 0xfffff;
+ ddr_clk = pll_convert_to_ddr_clk_g12a(ddr_pll);
+ } else if (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_A1) {
+ ddr_clk = 768;
+ } else if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_C2) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5D) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_S4)) {
+ uint32_t stick_store_sticky_f0_reg_base_t = (p_ddr_base->ddr_phy_base_address + 0x0128);
+ ddr_clk = rd_reg(stick_store_sticky_f0_reg_base_t);
+ } else {
+ ddr_clk = 10;
+ }
+ return ddr_clk;
+}
+
+void ddr_memcpy(void *dst, const void *src, uint32_t len)
+{
+ len = (len >> 3);
+ const long long *s = src;
+ long long *d = dst;
+#ifdef TEST_L1_CACHE
+ void *bound = (void *)src + 16 * 1024; //debug for test L1 cache ,if only read write small aread
+#endif
+ if (pre_fetch_enable) {
+ while (len) {
+ //for best test efficiency not inclued much more code in the while loop
+ ddr_pld_cache(s);
+ ///1 times len==33554432 copy time==18192 us 1.2g bandwidth 3688M/S
+ // 4times len==33554432 copy time==11844 us 1.2g bandwidth 5666M/S
+ // 8times len==33554432 copy time==11844 us 1.2g bandwidth 5666M/S
+ *d++ = *s++;
+ *d++ = *s++;
+ *d++ = *s++;
+ *d++ = *s++;
+ len = len - 4;
+#ifdef TEST_L1_CACHE
+ if ((void *)s >= bound) {
+ s = src;
+ d = dst;
+ }
+#endif
+ }
+ } else {
+ while (len) { //for best test efficiency not inclued much more code in the while loop
+ ///1 times len==33554432 copy time==18192 us 1.2g bandwidth 3688M/S
+ // 4times len==33554432 copy time==11844 us 1.2g bandwidth 5666M/S
+ // 8times len==33554432 copy time==11844 us 1.2g bandwidth 5666M/S
+ *d++ = *s++;
+ *d++ = *s++;
+ *d++ = *s++;
+ *d++ = *s++;
+ len = len - 4;
+#ifdef TEST_L1_CACHE
+ if ((void *)s >= bound) {
+ s = src;
+ d = dst;
+ }
+#endif
+ }
+ }
+}
+
+#define PATTERN_MATRIX_X (3 + 32 + 16 + 17) //68*32==2176 ///2.2k -0x880-1 loop
+#define PATTERN_MATRIX_Y (32)
+#define PATTERN_MATRIX_LOOP_SIZE ((PATTERN_MATRIX_X)*(PATTERN_MATRIX_Y) * 4)
+
+unsigned int cpu_ddr_test_init_pattern_generater(unsigned int add_offset)
+{
+ unsigned int pattern_select = 0;
+ unsigned int pattern_value = 0;
+ uint32_t martix_x_select = 0;
+ uint32_t martix_y_select = 0;
+ unsigned int pattern_value_temp_16 = 0;
+
+ {
+ {
+ pattern_select = ((add_offset) % ((PATTERN_MATRIX_Y)*(PATTERN_MATRIX_X)));
+ martix_x_select = pattern_select / (PATTERN_MATRIX_Y);
+ martix_y_select = pattern_select % (PATTERN_MATRIX_Y);
+ {
+ if (martix_x_select == 0)
+ pattern_value = 0xaaaa5555; //for 16 bit bus pattern
+
+ if (martix_x_select == 1)
+ pattern_value = 0x0000ffff; //for 16 bit bus pattern
+
+ if (martix_x_select == 2)
+ pattern_value = 0;
+
+ if ((martix_x_select > 2) && (martix_x_select < (3 + 32)))
+ pattern_value = 1 << (martix_x_select - 3);
+ if ((martix_x_select > (2 + 32)) && (martix_x_select < (3 + 32 + 16))) { //for 16 bit bus pattern
+ pattern_value_temp_16 = (1 << (martix_x_select - 3 - 32));
+ pattern_value = pattern_value_temp_16 | ((~pattern_value_temp_16) << 16);
+ }
+ if ((martix_x_select > (2 + 32 + 16)) && (martix_x_select < (3 + 32 + 16 + 17))) { //for dbi bus pattern 17 group
+ pattern_value_temp_16 = (0x0f0f + 0xf0f * (martix_x_select - 3 - 32 - 16));
+ pattern_value = pattern_value_temp_16 | ((~pattern_value_temp_16) << 16);
+ }
+ }
+ if (martix_y_select % 2)
+ pattern_value = ~pattern_value;
+ }
+ }
+ return pattern_value;
+}
+
+void cpu_ddr_test_init_pattern_area(unsigned int test_init_start, unsigned int test_size, unsigned int parttern_frequency_setting)
+{
+ if (parttern_frequency_setting == 0)
+ parttern_frequency_setting = 1; //for different frequency pattern
+ test_size = (test_size > ((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting))) ? test_size : ((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting));
+ unsigned int write_add = test_init_start;
+ unsigned int size_loop = 0;
+ unsigned int size_loop_max = 0;
+ for (; (size_loop < ((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting))); ) {
+ {
+ write_add = (uint32_t)(size_loop + test_init_start);
+ wr_reg((unsigned long)write_add, cpu_ddr_test_init_pattern_generater((size_loop >> 2) / parttern_frequency_setting));
+ size_loop = size_loop + 4;
+ }
+ }
+ size_loop = 1;
+ size_loop_max = ((test_size / (((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting)))) + 1);
+ for (; (size_loop < size_loop_max); ) {
+ ddr_memcpy((void *)(uint64_t)(test_init_start + ((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting)) * (size_loop)), (void *)(uint64_t)test_init_start, ((PATTERN_MATRIX_LOOP_SIZE)*(parttern_frequency_setting)));
+ size_loop++;
+ }
+}
+
+unsigned int cpu_ddr_test(unsigned test_init_start, unsigned int start_add, unsigned int test_size, unsigned int test_data_bit_enable, unsigned int parttern_frequency_setting)
+{
+ unsigned int src_add = test_init_start;
+ unsigned int pattern_value = 0;
+ unsigned int size_loop = 0;
+ unsigned int ddr_test_error = 0;
+ unsigned int read_add = 0;
+ unsigned int read_value = 0;
+
+ test_size = (test_size > 0x2000) ? (test_size) : (0x2000);
+ uint32_t ddr_test_start_time_us = get_us_time(); // check cost time
+ ddr_memcpy((void *)(uint64_t)start_add, (void *)(uint64_t)src_add, test_size);
+ uint32_t ddr_test_end_time_us = get_us_time(); // check cost time
+ printf("\ncpu_ddr_test_test_copy_bandwidth==%d Mbyte/s\n", (1 * test_size * 2) / (ddr_test_end_time_us - ddr_test_start_time_us));
+
+ for (; size_loop < (test_size); ) {
+ read_add = (uint32_t)(size_loop + start_add);
+ read_value = (rd_reg((unsigned long)read_add));
+ pattern_value = (cpu_ddr_test_init_pattern_generater((size_loop >> 2) / parttern_frequency_setting));
+ if (((test_data_bit_enable) & read_value) != ((test_data_bit_enable) & pattern_value)) {
+ printf("error data enable %08x read_value %08x pattern_value %08x", test_data_bit_enable, read_value, pattern_value);
+ ddr_test_error++;
+ return ddr_test_error;
+ }
+ size_loop = size_loop + (1 << 2); // use big step will fast test ,but lose accuracy.
+ }
+ return ddr_test_error;
+}
+
+int do_cpu_ddr_test(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ check_base_address();
+ int i = 0;
+ printf("\nargc== 0x%08x\n", argc);
+ for (i = 0; i < argc; i++)
+ printf("\nargv[%d]=%s\n", i, argv[i]);
+ unsigned int init_start_add = 0;
+ unsigned int test_add = 0;
+ unsigned int test_size = 0;
+ unsigned int test_data_bit_enable = 0;
+ unsigned int test_loops = 0;
+ unsigned int test_loop = 0;
+ unsigned int test_errors = 0;
+ unsigned int parttern_frequency_setting = 1;
+ char *endp;
+ if (argc == 1) {
+ printf("\nplease read help\n");
+ } else {
+ if (argc >= 2)
+ init_start_add = simple_strtoull_ddr(argv[1], &endp, 0);
+
+ if (argc >= 3)
+ test_add = simple_strtoull_ddr(argv[2], &endp, 0);
+ if (argc >= 4)
+ test_size = simple_strtoull_ddr(argv[3], &endp, 0);
+ if (argc >= 5)
+ test_data_bit_enable = simple_strtoull_ddr(argv[4], &endp, 0);
+ if (argc >= 6) {
+ test_loops = simple_strtoull_ddr(argv[5], &endp, 0);
+ if (test_loops == 0)
+ test_loops = 1;
+ }
+ if (argc >= 7) {
+ parttern_frequency_setting = simple_strtoull_ddr(argv[6], &endp, 0);
+ if (parttern_frequency_setting == 0)
+ parttern_frequency_setting = 1;
+ }
+ if (argc >= 8)
+ pre_fetch_enable = simple_strtoull_ddr(argv[7], &endp, 0);
+ }
+ uint32_t ddr_test_start_time_us = get_us_time(); // check cost time
+ cpu_ddr_test_init_pattern_area(init_start_add, test_size, parttern_frequency_setting);
+ for (test_loop = 0; test_loop < test_loops; ) {
+ test_errors = test_errors + cpu_ddr_test(init_start_add, test_add, test_size, test_data_bit_enable, parttern_frequency_setting);
+ test_loop++;
+ printf("\ncpu_ddr_test_test_times==%d test_errors==%d", test_loop, test_errors);
+ }
+ uint32_t ddr_test_end_time_us = get_us_time(); // check cost time
+ printf("\ncpu_ddr_test_test_and compare_bandwidth==%d Mbyte/s\n", (test_loops * test_size * 2) / (ddr_test_end_time_us - ddr_test_start_time_us));
+ return test_errors;
+}
+
+U_BOOT_CMD(
+ ddr_cpu_test, 30, 1, do_cpu_ddr_test,
+ "ddr_test_cmd cmd arg1 arg2 arg3...",
+ "ddr_test_cmd cmd arg1 arg2 arg3... \n dcache off ? \n"
+ );
+
+int do_ddr_test_write_read(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ {
+ printf("\nEnter do_ddr_test_ddr_write_read_current\n");
+ int i = 0;
+ printf("\nargc== 0x%08x\n", argc);
+ for (i = 0; i < argc; i++)
+ printf("\nargv[%d]=%s\n", i, argv[i]);
+
+ char *endp;
+
+ unsigned int pattern_id = 1;
+ unsigned int pattern[4] = { 0 };
+ unsigned int write_read = 0;
+ unsigned int read_pattern[4] = { 0 };
+ unsigned int loop = 1;
+ unsigned int start_addr = DDR_TEST_START_ADDR;
+ unsigned int test_size = DDR_TEST_SIZE;
+ unsigned int copy_offset = DDR_TEST_SIZE;
+ unsigned int no_show_info = 0;
+ unsigned int us_delay_counter = 0;
+
+
+ if (argc == 1) {
+ printf("\nplease read help\n");
+ } else {
+ if (argc >= 2)
+ write_read = simple_strtoull_ddr(argv[1], &endp, 0);
+ if (argc >= 3)
+ pattern_id = simple_strtoull_ddr(argv[2], &endp, 0);
+ if (argc >= 4)
+ loop = simple_strtoull_ddr(argv[3], &endp, 0);
+ if (argc >= 5)
+ start_addr = simple_strtoull_ddr(argv[4], &endp, 0);
+ if (argc >= 6)
+ test_size = simple_strtoull_ddr(argv[5], &endp, 0);
+ if (argc >= 7)
+ no_show_info = simple_strtoull_ddr(argv[6], &endp, 0);
+ if (argc >= 8)
+ us_delay_counter = simple_strtoull_ddr(argv[7], &endp, 0);
+ }
+ printf("\nwrite_read== 0x%08d\n", write_read);
+ printf("\npattern_id== 0x%08d\n", pattern_id);
+ printf("\nloop== 0x%08d\n", loop);
+ printf("\nstart_addr== 0x%08x\n", start_addr);
+ printf("\ntest_size== 0x%08x\n", test_size);
+ printf("\nus_delay_counter== %d\n", us_delay_counter);
+ copy_offset = test_size;
+
+ unsigned int *p;
+ unsigned int j;
+
+ p = (unsigned int *)(int_convter_p(start_addr));
+
+ if (pattern_id == 0) {
+ pattern[0] = 0;
+ pattern[1] = 0;
+ pattern[2] = 0;
+ pattern[3] = 0;
+ }
+ if (pattern_id == 1) {
+ pattern[0] = 0xffffffff;
+ pattern[1] = 0xffffffff;
+ pattern[2] = 0xffffffff;
+ pattern[3] = 0xffffffff;
+ }
+
+ do {
+ if (write_read == 0) {
+ if (!no_show_info)
+ printf("\nloop:0x%08x:Start writing at 0x%08x - 0x%08x...", loop, start_addr, start_addr + test_size);
+ for (j = 0; j < test_size / 4; ) {
+ *(p + j) = (pattern[0]);
+ *(p + j + 1) = (pattern[1]);
+ *(p + j + 2) = (pattern[2]);
+ *(p + j + 3) = (pattern[3]);
+ j = j + 4;
+ }
+ }
+ if (write_read == 1) {
+ if (!no_show_info)
+ printf("\nloop:0x%08x:Start reading at 0x%08x - 0x%08x...", loop, start_addr, start_addr + test_size);
+ for (j = 0; j < test_size / 4; ) {
+ read_pattern[0] = *(p + j);
+ read_pattern[1] = *(p + j + 1);
+ read_pattern[2] = *(p + j + 2);
+ read_pattern[3] = *(p + j + 3);
+ j = j + 4;
+ }
+
+ if (loop == 1) {
+ if (!no_show_info) {
+ printf(" \nloop:0x%08x:Start reading read_pattern[0] 0x%08x, pattern[1] 0x%08x,pattern[2] 0x%08x,pattern[3] 0x%08x",
+ loop, read_pattern[0], read_pattern[1], read_pattern[2], read_pattern[3]
+ );
+ }
+ }
+ }
+ if (write_read == 2) {
+ if (!no_show_info)
+ printf("\nloop:0x%08x:Start copying at 0x%08x - 0x%08x...", loop, start_addr, start_addr + test_size);
+ for (j = 0; j < test_size / 4; ) {
+ *(p + j + copy_offset / 4) = *(p + j);
+ *(p + j + 1 + copy_offset / 4) = *(p + j + 1);
+ *(p + j + 2 + copy_offset / 4) = *(p + j + 2);
+ *(p + j + 3 + copy_offset / 4) = *(p + j + 3);
+ j = j + 4;
+ }
+ }
+ if (us_delay_counter)
+ ddr_udelay(us_delay_counter);
+ } while (loop--);
+
+ printf("\ntest end\n");
+
+ return 1;
+ }
+}
+
+#if (CONFIG_DDR_PHY >= P_DDR_PHY_G12)
+
+#define TEST_MIN_DDR_EE_VOLTAGE 681
+#define TEST_MAX_DDR_EE_VOLTAGE 962
+static int pwm_voltage_table_ee[][2] =
+{
+ { 0x1c0000, 681 },
+ { 0x1b0001, 691 },
+ { 0x1a0002, 701 },
+ { 0x190003, 711 },
+ { 0x180004, 721 },
+ { 0x170005, 731 },
+ { 0x160006, 741 },
+ { 0x150007, 751 },
+ { 0x140008, 761 },
+ { 0x130009, 772 },
+ { 0x12000a, 782 },
+ { 0x11000b, 792 },
+ { 0x10000c, 802 },
+ { 0x0f000d, 812 },
+ { 0x0e000e, 822 },
+ { 0x0d000f, 832 },
+ { 0x0c0010, 842 },
+ { 0x0b0011, 852 },
+ { 0x0a0012, 862 },
+ { 0x090013, 872 },
+ { 0x080014, 882 },
+ { 0x070015, 892 },
+ { 0x060016, 902 },
+ { 0x050017, 912 },
+ { 0x040018, 922 },
+ { 0x030019, 932 },
+ { 0x02001a, 942 },
+ { 0x01001b, 952 },
+ { 0x00001c, 962 }
+};
+uint32_t find_vddee_voltage_index(unsigned int target_voltage)
+{
+ unsigned int to;
+
+ for (to = 0; to < ARRAY_SIZE(pwm_voltage_table_ee); to++) {
+ if (pwm_voltage_table_ee[to][1] >= target_voltage)
+ break;
+ }
+
+ if (to >= ARRAY_SIZE(pwm_voltage_table_ee))
+ to = ARRAY_SIZE(pwm_voltage_table_ee) - 1;
+ return to;
+}
+
+void set_ee_voltage(uint32_t ee_over_ride_voltage)
+{
+ unsigned int to;
+
+ for (to = (ARRAY_SIZE(pwm_voltage_table_ee)); (to > 0); to--) {
+ if ((pwm_voltage_table_ee[to - 1][1] < ee_over_ride_voltage) && (pwm_voltage_table_ee[to][1] >= ee_over_ride_voltage))
+ break;
+ }
+
+ if (ee_over_ride_voltage) {
+ writel(pwm_voltage_table_ee[to][0], (p_ddr_base->ee_pwm_base_address));
+ printf("\nDDR_overide_EE_voltage ==%d mv /n", pwm_voltage_table_ee[to - 1][1]);
+ }
+}
+
+unsigned int read_ee_voltage(void)
+{
+ unsigned int to;
+ unsigned int reg_value = 0;
+
+ reg_value = readl((p_ddr_base->ee_pwm_base_address));
+ to = reg_value & 0xff;
+ return pwm_voltage_table_ee[to][1];
+}
+
+uint32_t get_bdlr_100step(uint32_t ddr_frequency)
+{
+ uint32_t bdlr_100step = 0;
+
+ if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_C2) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5D) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_S4)) {
+ bdlr_100step = do_read_c2_ddr_bdlr_steps();
+ } else {
+ dwc_ddrphy_apb_wr(((((0 << 20) | (2 << 16) | (0 << 12) | (0xe3)))), 0xc00);
+ bdlr_100step = (100000000 / (2 * ddr_frequency)) / ((dwc_ddrphy_apb_rd((((0 << 20) | (2 << 16) | (0 << 12) | (0xe4))))) & 0x3ff);
+ }
+ return bdlr_100step;
+}
+
+int do_ddr_test_pwm_bdlr(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ char *endp;
+
+ printf("\nEnter g12 do_ddr_test_pwm_bdl function\n");
+ int i = 0;
+ printf("\nargc== 0x%08x\n", argc);
+ for (i = 0; i < argc; i++)
+ printf("\nargv[%d]=%s\n", i, argv[i]);
+
+ unsigned int argc_count = 1;
+ unsigned int para_meter[30] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+ while (argc_count < argc) {
+ para_meter[argc_count - 1] = simple_strtoul(argv[argc_count], &endp, 0);
+ if (*argv[argc_count] == 0 || *endp != 0)
+ para_meter[argc_count - 1] = 0;
+ argc_count++;
+ }
+
+ uint32_t loop = para_meter[0];
+ uint32_t voltage_min = para_meter[1];
+ uint32_t voltage_max = para_meter[2];
+ uint32_t show_count_message = para_meter[3];
+
+#define PWM_LOOP_DEFAULT 10 << 0
+#define PWM_VOLTAGE_MIN_DEFAULT TEST_MIN_DDR_EE_VOLTAGE
+#define PWM_VOLTAGE_MAX_DEFAULT TEST_MAX_DDR_EE_VOLTAGE
+
+ loop = loop ? loop : PWM_LOOP_DEFAULT;
+ voltage_min = (voltage_min < PWM_VOLTAGE_MIN_DEFAULT) ? PWM_VOLTAGE_MIN_DEFAULT : voltage_min;
+ voltage_max = (voltage_max > PWM_VOLTAGE_MAX_DEFAULT) ? PWM_VOLTAGE_MAX_DEFAULT : voltage_max;
+ voltage_max = (voltage_max < PWM_VOLTAGE_MIN_DEFAULT) ? PWM_VOLTAGE_MAX_DEFAULT : voltage_max;
+
+ uint16_t bdlr_100_min = 0;
+ uint16_t bdlr_100_average = 0;
+ uint16_t bdlr_100_max = 0;
+ uint16_t bdlr_100_cur = 0;
+ uint32_t count = 1;
+
+ bdlr_100_cur = get_bdlr_100step(global_ddr_clk);
+ bdlr_100_min = bdlr_100_cur;
+ bdlr_100_max = bdlr_100_cur;
+ bdlr_100_average = bdlr_100_cur;
+
+ unsigned int to = 0;
+ unsigned int to_min = 0;
+ unsigned int to_max = (ARRAY_SIZE(pwm_voltage_table_ee)) - 1;
+ printf("\nread org_EE_voltage %d mv \n", read_ee_voltage());
+ to_min = find_vddee_voltage_index(voltage_min);
+ to_max = find_vddee_voltage_index(voltage_max);
+ for (to = (to_max + 1); (to > to_min); to--) {
+ writel(pwm_voltage_table_ee[to - 1][0], (p_ddr_base->ee_pwm_base_address));
+ udelay(1000);
+ bdlr_100_cur = get_bdlr_100step(global_ddr_clk);
+ bdlr_100_min = bdlr_100_cur;
+ bdlr_100_max = bdlr_100_cur;
+ bdlr_100_average = bdlr_100_cur;
+ count = 1;
+
+ do {
+ bdlr_100_cur = (100000000 / (2 * global_ddr_clk)) / ((dwc_ddrphy_apb_rd((((0 << 20) | (2 << 16) | (0 << 12) | (0xe4))))) & 0x3ff);
+ bdlr_100_min = (bdlr_100_cur < bdlr_100_min) ? bdlr_100_cur : bdlr_100_min;
+ bdlr_100_max = (bdlr_100_cur > bdlr_100_max) ? bdlr_100_cur : bdlr_100_max;
+ bdlr_100_average = (bdlr_100_cur + bdlr_100_average * count) / (count + 1);
+ count++;
+ if (show_count_message)
+ printf("%d\n", bdlr_100_cur);
+ } while (count < loop);
+ printf("\nDDR_set EE_voltage %d bdlr_100_average %d bdlr_100_min %d bdlr_100_max %d count %d", pwm_voltage_table_ee[to - 1][1],
+ bdlr_100_average, bdlr_100_min, bdlr_100_max, count);
+ }
+ return 1;
+}
+
+
+int printf_log(char log_level, const char *fmt, ...)
+{
+ if (log_level < 1) {
+ va_list args;
+ va_start(args, fmt);
+ vprintf(fmt, args); //
+ va_end(args);
+ return 0;
+ } else {
+ return 1;
+ }
+}
+
+int do_read_ddr_training_data(char log_level, ddr_set_t *ddr_set_t_p)
+{
+ printf_log(log_level, "\nddr_set_t_p==0x%08x\n", (uint32_t)(uint64_t)(ddr_set_t_p));
+ uint32_t loop = 0;
+ uint32_t loop_max = (4 + (0x3f << 2)); //((DMC_STICKY_63-DMC_STICKY_0));
+ for (loop = 0; loop < loop_max; loop += 4)
+ wr_reg(((uint64_t)(ddr_set_t_p) + loop), rd_reg((p_ddr_base->ddr_dmc_sticky0) + loop));
+
+ for (loop = 0; loop < MESON_CPU_CHIP_ID_SIZE; loop++) //update chip id
+ ddr_sha.sha_chip_id[loop] = global_chip_id[loop];
+ {
+ uint16_t dq_bit_delay[72];
+ unsigned char t_count = 0;
+ uint16_t delay_org = 0;
+ uint16_t delay_temp = 0;
+ uint32_t add_offset = 0;
+ dwc_ddrphy_apb_wr(0xd0000, 0x0);
+ bdlr_100step = get_bdlr_100step(global_ddr_clk);
+ ui_1_32_100step = (1000000 * 100 / (global_ddr_clk * 2 * 32));
+ uint32_t ps = 0;
+ for (ps = 0; ps < 2; ps++) {
+ {
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ARdPtrInitVal = 0;
+ printf_log(log_level, "\n ARdPtrInitVal ps=%d", ps);
+ add_offset = ((ps << 20) | (2 << 16) | (0 << 12) | (0x2e));
+ delay_org = dwc_ddrphy_apb_rd(add_offset);
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ARdPtrInitVal = delay_org;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", 0, delay_org, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), delay_org);
+
+ printf_log(log_level, "\n dfimrl0 dfimrl1 dfimrl2 dfimrl3 HwtMRL ps=%d", ps);
+ add_offset = ((ps << 20) | (1 << 16) | (0 << 12) | (0x20));
+ delay_org = dwc_ddrphy_apb_rd(add_offset);
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_mrl = delay_org;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", 0, delay_org, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), delay_org);
+ add_offset = ((ps << 20) | (1 << 16) | (1 << 12) | (0x20));
+ delay_org = dwc_ddrphy_apb_rd(add_offset);
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", 1, delay_org, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), delay_org);
+ add_offset = ((ps << 20) | (1 << 16) | (2 << 12) | (0x20));
+ delay_org = dwc_ddrphy_apb_rd(add_offset);
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", 2, delay_org, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), delay_org);
+ add_offset = ((ps << 20) | (1 << 16) | (3 << 12) | (0x20));
+ delay_org = dwc_ddrphy_apb_rd(add_offset);
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", 3, delay_org, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), delay_org);
+ add_offset = ((ps << 20) | (2 << 16) | (0 << 12) | (0x20));
+ delay_org = dwc_ddrphy_apb_rd(add_offset);
+
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_hwtmrl = delay_org;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", 0, delay_org, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), delay_org);
+ }
+ {
+ printf_log(log_level, "\n count_index delay_value register_add register_value ps=%d\n ", ps);
+ printf_log(log_level, "\n address delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6 is coarse --step==1UI ps=%d", ui_1_32_100step, ps);
+ for (t_count = 0; t_count < 10; t_count++) {
+ add_offset = ((ps << 20) | (0 << 16) | (t_count << 12) | (0x80));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_org = dq_bit_delay[t_count];
+ delay_temp = (32 * (((delay_org >> 6) & 0xf) + ((delay_org >> 5) & 1)) + (delay_org & 0x1f));
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ac_trace_delay[t_count] = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ }
+ {
+ printf_log(log_level, "\n tdqs delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6-9 is coarse --step==1UI ps=%d", ui_1_32_100step, ps);
+ for (t_count = 0; t_count < 16; t_count++) {
+ add_offset = ((ps << 20) | (1 << 16) | (((t_count % 8) >> 1) << 12) | (0xd0 + (t_count / 8) + ((t_count % 2) << 8)));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_org = dq_bit_delay[t_count];
+ delay_temp = (32 * (((delay_org >> 6) & 0xf) + ((delay_org >> 5) & 1)) + (delay_org & 0x1f));
+
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dqs_delay[t_count] = delay_temp;
+
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ }
+ {
+ printf_log(log_level, "\n rxdqs delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI,no coarse ps=%d", ui_1_32_100step, ps);
+ for (t_count = 0; t_count < 16; t_count++) {
+ add_offset = ((ps << 20) | (1 << 16) | (((t_count % 8) >> 1) << 12) | (0x8c + (t_count / 8) + ((t_count % 2) << 8)));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_org = dq_bit_delay[t_count];
+ delay_temp = (32 * (((delay_org >> 6) & 0xf) + ((delay_org >> 5) & 1)) + (delay_org & 0x1f));
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_delay[t_count] = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ }
+ {
+ printf_log(log_level, "\n write dq_bit delay * 1/32UIx100==%d ps bit0-4 fine tune --step==1/32UI ,bit 6-8 is coarse --step==1U ps=%d", ui_1_32_100step, ps);
+ for (t_count = 0; t_count < 72; t_count++) {
+ add_offset = ((ps << 20) | (1 << 16) | (((t_count % 36) / 9) << 12) | (0xc0 + ((t_count % 9) << 8) + (t_count / 36)));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_org = dq_bit_delay[t_count];
+ delay_temp = (32 * (((delay_org >> 6) & 0xf) + ((delay_org >> 5) & 1)) + (delay_org & 0x1f));
+
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dq_bit_delay[t_count] = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ }
+ {
+ printf_log(log_level, "\n read dq_bit delay * BDLRx100==%d ps bit0-4 fine tune --step==bdlr step size about 5ps,no coarse ps=%d", bdlr_100step, ps);
+ for (t_count = 0; t_count < 72; t_count++) {
+ add_offset = ((0 << 20) | (1 << 16) | (((t_count % 36) / 9) << 12) | (0x68 + ((t_count % 9) << 8) + (t_count / 36)));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_org = dq_bit_delay[t_count];
+ delay_temp = ((delay_org & 0x3f));
+
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dq_bit_delay[t_count] = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ }
+ {
+ printf_log(log_level, "\n read dqs gate delay * 1/32UIx100==%d ps bit0-4 fine tune ,bit 6-10 is coarse ps=%d", ui_1_32_100step, ps);
+ for (t_count = 0; t_count < 16; t_count++) {
+ add_offset = ((ps << 20) | (1 << 16) | (((t_count % 8) >> 1) << 12) | (0x80 + (t_count / 8) + ((t_count % 2) << 8)));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_org = dq_bit_delay[t_count];
+ delay_temp = (32 * (((delay_org >> 6) & 0x1f) + ((delay_org >> 5) & 1)) + (delay_org & 0x1f));
+
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_gate_delay[t_count] = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+
+ printf_log(log_level, "\n soc vref : lpddr4-- VREF = VDDQ*(0.047 + VrefDAC0[6:0]*0.00367 DDR4 --VREF = VDDQ*(0.510 + VrefDAC0[6:0]*0.00345 ps=%d", ps);
+ uint32_t vref_t_count = 0;
+ for (t_count = 0; t_count < 72; t_count++) { //add normal vref0---vrefDac0 for just 1->x transitions
+ add_offset = ((0 << 20) | (1 << 16) | (((t_count % 36) / 9) << 12) | (((t_count % 36) % 9) << 8) | (0x40));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_org = dq_bit_delay[t_count];
+ delay_temp = ((delay_org));
+ if (t_count < 35) {
+ vref_t_count = ((((t_count % 36) / 9) * 8) + (t_count % 9));
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[vref_t_count] = delay_temp;
+ }
+ if ((t_count % 9) == 8) {
+ vref_t_count = 32 + ((((t_count % 36) / 9)));
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[vref_t_count] = delay_temp;
+ }
+
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ printf_log(log_level, "\n soc vref-dfe dac1 0--->x : lpddr4-- VREF = VDDQ*(0.047 + VrefDAC0[6:0]*0.00367 DDR4 --VREF = VDDQ*(0.510 + VrefDAC0[6:0]*0.00345 ps=%d", ps);
+ for (t_count = 0; t_count < 72; t_count++) { //add dfe vref1---vrefDac1 for just 0->x transitions
+ add_offset = ((0 << 20) | (1 << 16) | (((t_count % 36) / 9) << 12) | (((t_count % 36) % 9) << 8) | (0x30));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_org = dq_bit_delay[t_count];
+ delay_temp = ((delay_org));
+ if (t_count < 35) {
+ vref_t_count = ((((t_count % 36) / 9) * 8) + (t_count % 9));
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[vref_t_count] = delay_temp;
+ }
+ if ((t_count % 9) == 8) {
+ vref_t_count = 32 + ((((t_count % 36) / 9)));
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[vref_t_count] = delay_temp;
+ }
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ printf_log(log_level, "\n dram vref : lpddr4-- VREF = VDDQ*(0. + VrefDAC0[6:0]*0. DDR4 --VREF = VDDQ*(0. + VrefDAC0[6:0]*0. ps=%d", ps);
+ add_offset = ((0 << 20) | (1 << 16) | (0 << 12) | (0x082));
+ delay_temp = dwc_ddrphy_apb_rd(add_offset);
+ for (t_count = 0; t_count < 32; t_count++)
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dram_bit_vref[t_count] = delay_temp;
+
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", 0, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), delay_temp);
+ }
+ //add for skip training
+ printf_log(log_level, "\n extra retraining setting. ps=%d", ps);
+ t_count = 0;
+ add_offset = (0 << 20) | (2 << 16) | (0 << 12) | (0xcb);
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_temp = dq_bit_delay[t_count];
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pllctrl3 = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+
+ for (t_count = 0; t_count < 4; t_count++) {
+ add_offset = ((0 << 20) | (1 << 16) | (t_count << 12) | (0xaa));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_temp = dq_bit_delay[t_count];
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pptctlstatic[t_count] = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ for (t_count = 0; t_count < 4; t_count++) {
+ add_offset = ((0 << 20) | (1 << 16) | (t_count << 12) | (0x62));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_temp = dq_bit_delay[t_count];
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_trainingincdecdtsmen[t_count] = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ for (t_count = 0; t_count < 4; t_count++) {
+ add_offset = ((0 << 20) | (1 << 16) | (t_count << 12) | (0x01));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_temp = dq_bit_delay[t_count];
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_tsmbyte0[t_count] = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ for (t_count = 0; t_count < 4; t_count++) {
+ add_offset = ((ps << 20) | (1 << 16) | (t_count << 12) | (0x43));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_temp = dq_bit_delay[t_count];
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dqsrcvcntrl[t_count] = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ for (t_count = 0; t_count < 4; t_count++) {
+ add_offset = ((ps << 20) | (1 << 16) | (t_count << 12) | (0xae));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_temp = dq_bit_delay[t_count];
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg0[t_count] = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ for (t_count = 0; t_count < 4; t_count++) {
+ add_offset = ((ps << 20) | (1 << 16) | (t_count << 12) | (0xaf));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_temp = dq_bit_delay[t_count];
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg1[t_count] = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ {
+ t_count = 0;
+ add_offset = ((ps << 20) | (2 << 16) | (t_count << 12) | (0xb2));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_temp = dq_bit_delay[t_count];
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_vrefinglobal = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ for (t_count = 1; t_count < 9; t_count++) {
+ add_offset = ((ps << 20) | (9 << 16) | (0 << 12) | (0x200) | t_count);
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_temp = dq_bit_delay[t_count];
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_seq0bgpr[t_count] = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ {
+ t_count = 0;
+ add_offset = ((ps << 20) | (2 << 16) | (t_count << 12) | (0x7c));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_temp = dq_bit_delay[t_count];
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dllgainctl = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ {
+ t_count = 0;
+ add_offset = ((ps << 20) | (2 << 16) | (t_count << 12) | (0x7d));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_temp = dq_bit_delay[t_count];
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dlllockpara = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ {
+ t_count = 0;
+ add_offset = ((0 << 20) | (2 << 16) | (t_count << 12) | (0x77));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_temp = dq_bit_delay[t_count];
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtcamode = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ {
+ t_count = 0;
+ add_offset = ((0 << 20) | (2 << 16) | (t_count << 12) | (0x72));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_temp = dq_bit_delay[t_count];
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsena = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ {
+ t_count = 0;
+ add_offset = ((0 << 20) | (2 << 16) | (t_count << 12) | (0x73));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_temp = dq_bit_delay[t_count];
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsenb = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ {
+ t_count = 0;
+ add_offset = ((0 << 20) | (4 << 16) | (t_count << 12) | (0xfd));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_temp = dq_bit_delay[t_count];
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl13 = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ {
+ t_count = 0;
+ add_offset = ((0 << 20) | (4 << 16) | (t_count << 12) | (0xc0));
+ dq_bit_delay[t_count] = dwc_ddrphy_apb_rd(add_offset);
+ delay_temp = dq_bit_delay[t_count];
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl23 = delay_temp;
+ printf_log(log_level, "\n t_count: %04d %04d %08x %08x", t_count, delay_temp, ((((add_offset) << 1) + (p_ddr_base->ddr_phy_base_address))), dq_bit_delay[t_count]);
+ }
+ }
+ }
+ return 1;
+}
+
+int do_ddr_display_g12_ddr_information(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int i = 0;
+ unsigned int ps = 0;
+
+ printf("\nargc== 0x%08x\n", argc);
+ for (i = 0; i < argc; i++)
+ printf("\nargv[%d]=%s\n", i, argv[i]);
+ ddr_set_t *ddr_set_t_p = NULL;
+ ddr_set_t_p = (ddr_set_t *)(ddr_set_t_p_arrary);
+ ddr_set_t7 *ddr_set_t_p_t7 = (ddr_set_t7 *)ddr_set_t_p;
+ do_read_ddr_training_data(0, ddr_set_t_p);
+
+ {
+ uint32_t count = 0;
+ uint32_t reg_add_offset = 0;
+ uint16_t reg_value = 0;
+
+ printf("\n PCTL timming: 0x");
+
+ for (count = 0; count < ((p_ddr_base->ddr_pctl_timing_end_address) - (p_ddr_base->ddr_pctl_timing_base_address)); ) {
+ reg_add_offset = ((p_ddr_base->ddr_pctl_timing_base_address) + (count));
+ printf("\n reg_add_offset: %08x %08x %08x ", reg_add_offset, readl(reg_add_offset), reg_add_offset);
+ count = count + 4;
+ }
+ printf("\n mrs register: ");
+ printf("\n mrs register: base (0x54000<<1)+DDR_PHY_BASE,%08x byte offset\n", (0x54000 << 1) + (p_ddr_base->ddr_phy_base_address));
+ for (count = 0; count < 0x80; ) {
+ reg_add_offset = 0x54000 + count; //dwc_ddrphy_apb_wr(0x54008,0x1001);
+ reg_value = ((*(volatile uint16_t *)((uint64_t)(((0x54000 + (count >> 1))) << 1) + (p_ddr_base->ddr_phy_base_address))) >> (((count) % 2) ? 8 : 0)); //dwc_ddrphy_apb_rd(0x54000+add_offset+1);
+ reg_value = reg_value & 0xff;
+ printf("\n reg_add_offset: %08x %08x %08x", reg_add_offset, reg_value, ((((0x54000 + (count >> 1))) << 1) + (p_ddr_base->ddr_phy_base_address)));
+ count = count + 1;
+ }
+
+ printf("\n sticky register: ");
+ {
+ uint32_t loop_max = 0;
+ loop_max = 64 << 2; //sizeof(ddr_set_t);
+ for (count = 0; count < loop_max; count += 4)
+ printf("\n reg_add_offset: %08x %08x %08x", count, rd_reg((uint64_t)((p_ddr_base->ddr_dmc_sticky0)) + count), (((p_ddr_base->ddr_dmc_sticky0)) + count));
+ }
+
+ {
+ uint32_t loop_max = 0;
+ loop_max = sizeof(ddr_set_t);
+ uint32_t count = 0;
+ for (count = 0; count < loop_max; ) {
+ printf("\n%08x %08x", count, rd_reg((uint64_t)(ddr_set_t_p) + count));
+ count = count + 4;
+ }
+ }
+ }
+
+ printf("\n {");
+
+#define DDR_TIMMING_OFFSET_DDR_SET_T7(X) (unsigned int)(unsigned long)(&(((ddr_set_t7 *)(0))->X))
+////#define DDR_TIMMING_OFFSET_SIZE(X) sizeof(((ddr_set_t7 *)(0))->X)
+#define DDR_TIMMING_OFFSET_DDR_SET(X) (unsigned int)(unsigned long)(&(((ddr_set_t *)(0))->X))
+//#define DDR_TIMMING_OFFSET_SIZE(X) sizeof(((ddr_set_t *)(0))->X)
+ uint32_t temp_count = 0;
+ {
+ printf("\n.magic=0x%08x,// %d,0x%08x", ddr_set_t_p->magic, ddr_set_t_p->magic,DDR_TIMMING_OFFSET_DDR_SET(magic));
+ printf("\n//old fast_boot[%d]=0x%08x,// %d,0x%08x", 0, ddr_set_t_p->fast_boot[0], ddr_set_t_p->fast_boot[0],DDR_TIMMING_OFFSET_DDR_SET(fast_boot[0]));
+ ddr_set_t_p->fast_boot[0] = 0xfd; //add for auto copy to code test
+ for (temp_count = 0; temp_count < 4; temp_count++)
+ printf("\n.fast_boot[%d]=0x%08x,// %d,0x%08x", temp_count, ddr_set_t_p->fast_boot[temp_count], ddr_set_t_p->fast_boot[temp_count],DDR_TIMMING_OFFSET_DDR_SET(fast_boot[temp_count]));
+ printf("\n.board_id=0x%08x,// %d,0x%08x", ddr_set_t_p->board_id, ddr_set_t_p->board_id,DDR_TIMMING_OFFSET_DDR_SET(board_id));
+ printf("\n.version=0x%08x,// %d,0x%08x", ddr_set_t_p->version, ddr_set_t_p->version,DDR_TIMMING_OFFSET_DDR_SET(version));
+ printf("\n.DramType=0x%08x,// %d,0x%08x", ddr_set_t_p->DramType, ddr_set_t_p->DramType,DDR_TIMMING_OFFSET_DDR_SET(DramType));
+ if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T7)) {
+ printf("\n.DisabledDbyte[0]=0x%08x,// %d,0x%08x", ddr_set_t_p_t7->DisabledDbyte[0], ddr_set_t_p_t7->DisabledDbyte[0],DDR_TIMMING_OFFSET_DDR_SET_T7(DisabledDbyte[0]));
+ printf("\n.DisabledDbyte[1]=0x%08x,// %d,0x%08x", ddr_set_t_p_t7->DisabledDbyte[1], ddr_set_t_p_t7->DisabledDbyte[1],DDR_TIMMING_OFFSET_DDR_SET_T7(DisabledDbyte[1]));
+ printf("\n.Is2Ttiming=0x%08x,// %d,0x%08x", ddr_set_t_p_t7->Is2Ttiming, ddr_set_t_p_t7->Is2Ttiming,DDR_TIMMING_OFFSET_DDR_SET_T7(Is2Ttiming));
+ printf("\n.HdtCtrl=0x%08x,// %d,0x%08x", ddr_set_t_p_t7->HdtCtrl, ddr_set_t_p_t7->HdtCtrl,DDR_TIMMING_OFFSET_DDR_SET_T7(HdtCtrl));
+ printf("\n.dram_rank_config=0x%08x,// %d,0x%08x", ddr_set_t_p_t7->dram_rank_config, ddr_set_t_p_t7->dram_rank_config,DDR_TIMMING_OFFSET_DDR_SET_T7(dram_rank_config));
+ } else {
+ printf("\n.DisabledDbyte=0x%08x,// %d,0x%08x", ddr_set_t_p->DisabledDbyte, ddr_set_t_p->DisabledDbyte,DDR_TIMMING_OFFSET_DDR_SET(DisabledDbyte));
+ printf("\n.Is2Ttiming=0x%08x,// %d,0x%08x", ddr_set_t_p->Is2Ttiming, ddr_set_t_p->Is2Ttiming,DDR_TIMMING_OFFSET_DDR_SET(Is2Ttiming));
+ printf("\n.HdtCtrl=0x%08x,// %d,0x%08x", ddr_set_t_p->HdtCtrl, ddr_set_t_p->HdtCtrl,DDR_TIMMING_OFFSET_DDR_SET(HdtCtrl));
+ printf("\n.dram_rank_config=0x%08x,// %d,0x%08x", ddr_set_t_p->dram_rank_config, ddr_set_t_p->dram_rank_config,DDR_TIMMING_OFFSET_DDR_SET(dram_rank_config));
+ printf("\n.diagnose=0x%08x,// %d,0x%08x", ddr_set_t_p->diagnose, ddr_set_t_p->diagnose,DDR_TIMMING_OFFSET_DDR_SET(diagnose));
+ }
+ printf("\n.soc_data_drv_ohm_ps1=0x%08x,// %d,0x%08x", ddr_set_t_p->soc_data_drv_ohm_ps1, ddr_set_t_p->soc_data_drv_ohm_ps1,DDR_TIMMING_OFFSET_DDR_SET(soc_data_drv_ohm_ps1));
+ printf("\n.dram_data_drv_ohm_ps1=0x%08x,// %d,0x%08x", ddr_set_t_p->dram_data_drv_ohm_ps1, ddr_set_t_p->dram_data_drv_ohm_ps1,DDR_TIMMING_OFFSET_DDR_SET(dram_data_drv_ohm_ps1));
+ printf("\n.soc_data_odt_ohm_ps1=0x%08x,// %d,0x%08x", ddr_set_t_p->soc_data_odt_ohm_ps1, ddr_set_t_p->soc_data_odt_ohm_ps1,DDR_TIMMING_OFFSET_DDR_SET(soc_data_odt_ohm_ps1));
+ printf("\n.dram_data_odt_ohm_ps1=0x%08x,// %d,0x%08x", ddr_set_t_p->dram_data_odt_ohm_ps1, ddr_set_t_p->dram_data_odt_ohm_ps1,DDR_TIMMING_OFFSET_DDR_SET(dram_data_odt_ohm_ps1));
+ printf("\n.dram_data_wr_odt_ohm_ps1=0x%08x,// %d,0x%08x", ddr_set_t_p->dram_data_wr_odt_ohm_ps1, ddr_set_t_p->dram_data_wr_odt_ohm_ps1,DDR_TIMMING_OFFSET_DDR_SET(dram_data_wr_odt_ohm_ps1));
+ if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T7)) {
+ printf("\n.soc_data_drv_ohm_ffe=0x%08x,// %d,0x%08x", ddr_set_t_p_t7->soc_data_drv_ohm_ffe, ddr_set_t_p_t7->soc_data_drv_ohm_ffe,DDR_TIMMING_OFFSET_DDR_SET_T7(soc_data_drv_ohm_ffe));
+ printf("\n.ddr_base_addr=0x%08x,// %d,0x%08x", ddr_set_t_p->ddr_base_addr, ddr_set_t_p->ddr_base_addr,DDR_TIMMING_OFFSET_DDR_SET_T7(ddr_base_addr));
+ printf("\n.ddr_start_offset=0x%08x,// %d,0x%08x", ddr_set_t_p->ddr_start_offset, ddr_set_t_p->ddr_start_offset,DDR_TIMMING_OFFSET_DDR_SET_T7(ddr_start_offset));
+ printf("\n.dram_ch0_size_MB=0x%08x,// %d,0x%08x", ddr_set_t_p_t7->dram_ch0_size_MB, ddr_set_t_p_t7->dram_ch0_size_MB,DDR_TIMMING_OFFSET_DDR_SET_T7(dram_ch0_size_MB));
+ printf("\n.dram_ch1_size_MB=0x%08x,// %d,0x%08x", ddr_set_t_p_t7->dram_ch1_size_MB, ddr_set_t_p_t7->dram_ch1_size_MB,DDR_TIMMING_OFFSET_DDR_SET_T7(dram_ch1_size_MB));
+ } else {
+ printf("\n.dmem_load_size=0x%08x,// %d,0x%08x", ddr_set_t_p->dmem_load_size, ddr_set_t_p->dmem_load_size,DDR_TIMMING_OFFSET_DDR_SET(dmem_load_size));
+ printf("\n.ddr_base_addr=0x%08x,// %d,0x%08x", ddr_set_t_p->ddr_base_addr, ddr_set_t_p->ddr_base_addr,DDR_TIMMING_OFFSET_DDR_SET(ddr_base_addr));
+ printf("\n.ddr_start_offset=0x%08x,// %d,0x%08x", ddr_set_t_p->ddr_start_offset, ddr_set_t_p->ddr_start_offset,DDR_TIMMING_OFFSET_DDR_SET(ddr_start_offset));
+ printf("\n.dram_cs0_size_MB=0x%08x,// %d,0x%08x", ddr_set_t_p->dram_cs0_size_MB, ddr_set_t_p->dram_cs0_size_MB,DDR_TIMMING_OFFSET_DDR_SET(dram_cs0_size_MB));
+ printf("\n.dram_cs1_size_MB=0x%08x,// %d,0x%08x", ddr_set_t_p->dram_cs1_size_MB, ddr_set_t_p->dram_cs1_size_MB,DDR_TIMMING_OFFSET_DDR_SET(dram_cs1_size_MB));
+ }
+ printf("\n.training_SequenceCtrl[0]=0x%08x,// %d,0x%08x", ddr_set_t_p->training_SequenceCtrl[0], ddr_set_t_p->training_SequenceCtrl[0],DDR_TIMMING_OFFSET_DDR_SET(training_SequenceCtrl[0]));
+ printf("\n.training_SequenceCtrl[1]=0x%08x,// %d,0x%08x", ddr_set_t_p->training_SequenceCtrl[1], ddr_set_t_p->training_SequenceCtrl[1],DDR_TIMMING_OFFSET_DDR_SET(training_SequenceCtrl[1]));
+ printf("\n.phy_odt_config_rank[0]=0x%08x,// %d,0x%08x", ddr_set_t_p->phy_odt_config_rank[0], ddr_set_t_p->phy_odt_config_rank[0],DDR_TIMMING_OFFSET_DDR_SET(phy_odt_config_rank[0]));
+ printf("\n.phy_odt_config_rank[1]=0x%08x,// %d,0x%08x", ddr_set_t_p->phy_odt_config_rank[1], ddr_set_t_p->phy_odt_config_rank[1],DDR_TIMMING_OFFSET_DDR_SET(phy_odt_config_rank[1]));
+ printf("\n.rank1_ca_vref_permil=0x%08x,// %d,0x%08x", ddr_set_t_p->rank1_ca_vref_permil, ddr_set_t_p->rank1_ca_vref_permil,DDR_TIMMING_OFFSET_DDR_SET(rank1_ca_vref_permil));
+
+ printf("\n.dfi_odt_config=0x%08x,// %d,0x%08x", ddr_set_t_p->dfi_odt_config, ddr_set_t_p->dfi_odt_config,DDR_TIMMING_OFFSET_DDR_SET(dfi_odt_config));
+ printf("\n.DRAMFreq[0]=0x%08x,// %d,0x%08x", ddr_set_t_p->DRAMFreq[0], ddr_set_t_p->DRAMFreq[0],DDR_TIMMING_OFFSET_DDR_SET(DRAMFreq[0]));
+ printf("\n.DRAMFreq[1]=0x%08x,// %d,0x%08x", ddr_set_t_p->DRAMFreq[1], ddr_set_t_p->DRAMFreq[1],DDR_TIMMING_OFFSET_DDR_SET(DRAMFreq[1]));
+ printf("\n.DRAMFreq[2]=0x%08x,// %d,0x%08x", ddr_set_t_p->DRAMFreq[2], ddr_set_t_p->DRAMFreq[2],DDR_TIMMING_OFFSET_DDR_SET(DRAMFreq[2]));
+ printf("\n.DRAMFreq[3]=0x%08x,// %d,0x%08x", ddr_set_t_p->DRAMFreq[3], ddr_set_t_p->DRAMFreq[3],DDR_TIMMING_OFFSET_DDR_SET(DRAMFreq[3]));
+ printf("\n.PllBypassEn=0x%08x,// %d,0x%08x", ddr_set_t_p->PllBypassEn, ddr_set_t_p->PllBypassEn,DDR_TIMMING_OFFSET_DDR_SET(PllBypassEn));
+ printf("\n.ddr_rdbi_wr_enable=0x%08x,// %d,0x%08x", ddr_set_t_p->ddr_rdbi_wr_enable, ddr_set_t_p->ddr_rdbi_wr_enable,DDR_TIMMING_OFFSET_DDR_SET(ddr_rdbi_wr_enable));
+ printf("\n.ddr_rfc_type=0x%08x,// %d,0x%08x", ddr_set_t_p->ddr_rfc_type, ddr_set_t_p->ddr_rfc_type,DDR_TIMMING_OFFSET_DDR_SET(ddr_rfc_type));
+ printf("\n.enable_lpddr4x_mode=0x%08x,// %d,0x%08x", ddr_set_t_p->enable_lpddr4x_mode, ddr_set_t_p->enable_lpddr4x_mode,DDR_TIMMING_OFFSET_DDR_SET(enable_lpddr4x_mode));
+ printf("\n.pll_ssc_mode=0x%08x,// %d,0x%08x", ddr_set_t_p->pll_ssc_mode, ddr_set_t_p->pll_ssc_mode,DDR_TIMMING_OFFSET_DDR_SET(pll_ssc_mode));
+ printf("\n.clk_drv_ohm=0x%08x,// %d,0x%08x", ddr_set_t_p->clk_drv_ohm, ddr_set_t_p->clk_drv_ohm,DDR_TIMMING_OFFSET_DDR_SET(clk_drv_ohm));
+ printf("\n.cs_drv_ohm=0x%08x,// %d,0x%08x", ddr_set_t_p->cs_drv_ohm, ddr_set_t_p->cs_drv_ohm,DDR_TIMMING_OFFSET_DDR_SET(cs_drv_ohm));
+ printf("\n.ac_drv_ohm=0x%08x,// %d,0x%08x", ddr_set_t_p->ac_drv_ohm, ddr_set_t_p->ac_drv_ohm,DDR_TIMMING_OFFSET_DDR_SET(ac_drv_ohm));
+ printf("\n.soc_data_drv_ohm_p=0x%08x,// %d,0x%08x", ddr_set_t_p->soc_data_drv_ohm_p, ddr_set_t_p->soc_data_drv_ohm_p,DDR_TIMMING_OFFSET_DDR_SET(soc_data_drv_ohm_p));
+ printf("\n.soc_data_drv_ohm_n=0x%08x,// %d,0x%08x", ddr_set_t_p->soc_data_drv_ohm_n, ddr_set_t_p->soc_data_drv_ohm_n,DDR_TIMMING_OFFSET_DDR_SET(soc_data_drv_ohm_n));
+ printf("\n.soc_data_odt_ohm_p=0x%08x,// %d,0x%08x", ddr_set_t_p->soc_data_odt_ohm_p, ddr_set_t_p->soc_data_odt_ohm_p,DDR_TIMMING_OFFSET_DDR_SET(soc_data_odt_ohm_p));
+ printf("\n.soc_data_odt_ohm_n=0x%08x,// %d,0x%08x", ddr_set_t_p->soc_data_odt_ohm_n, ddr_set_t_p->soc_data_odt_ohm_n,DDR_TIMMING_OFFSET_DDR_SET(soc_data_odt_ohm_n));
+ printf("\n.dram_data_drv_ohm=0x%08x,// %d,0x%08x", ddr_set_t_p->dram_data_drv_ohm, ddr_set_t_p->dram_data_drv_ohm,DDR_TIMMING_OFFSET_DDR_SET(dram_data_drv_ohm));
+ printf("\n.dram_data_odt_ohm=0x%08x,// %d,0x%08x", ddr_set_t_p->dram_data_odt_ohm, ddr_set_t_p->dram_data_odt_ohm,DDR_TIMMING_OFFSET_DDR_SET(dram_data_drv_ohm));
+ printf("\n.dram_ac_odt_ohm=0x%08x,// %d,0x%08x", ddr_set_t_p->dram_ac_odt_ohm, ddr_set_t_p->dram_ac_odt_ohm,DDR_TIMMING_OFFSET_DDR_SET(dram_ac_odt_ohm));
+ printf("\n.soc_clk_slew_rate=0x%08x,// %d,0x%08x", ddr_set_t_p->soc_clk_slew_rate, ddr_set_t_p->soc_clk_slew_rate,DDR_TIMMING_OFFSET_DDR_SET(soc_clk_slew_rate));
+ printf("\n.soc_cs_slew_rate=0x%08x,// %d,0x%08x", ddr_set_t_p->soc_cs_slew_rate, ddr_set_t_p->soc_cs_slew_rate,DDR_TIMMING_OFFSET_DDR_SET(soc_cs_slew_rate));
+ printf("\n.soc_ac_slew_rate=0x%08x,// %d,0x%08x", ddr_set_t_p->soc_ac_slew_rate, ddr_set_t_p->soc_ac_slew_rate,DDR_TIMMING_OFFSET_DDR_SET(soc_ac_slew_rate));
+ printf("\n.soc_data_slew_rate=0x%08x,// %d,0x%08x", ddr_set_t_p->soc_data_slew_rate, ddr_set_t_p->soc_data_slew_rate,DDR_TIMMING_OFFSET_DDR_SET(soc_data_slew_rate));
+ printf("\n.vref_output_permil =0x%08x,// %d,0x%08x", ddr_set_t_p->vref_output_permil, ddr_set_t_p->vref_output_permil,DDR_TIMMING_OFFSET_DDR_SET(vref_output_permil));
+ printf("\n.vref_receiver_permil =0x%08x,// %d,0x%08x", ddr_set_t_p->vref_receiver_permil, ddr_set_t_p->vref_receiver_permil,DDR_TIMMING_OFFSET_DDR_SET(vref_receiver_permil));
+ printf("\n.vref_dram_permil=0x%08x,// %d,0x%08x", ddr_set_t_p->vref_dram_permil, ddr_set_t_p->vref_dram_permil,DDR_TIMMING_OFFSET_DDR_SET(vref_dram_permil));
+ printf("\n.max_core_timmming_frequency=0x%08x,// %d,0x%08x", ddr_set_t_p->max_core_timmming_frequency, ddr_set_t_p->max_core_timmming_frequency,DDR_TIMMING_OFFSET_DDR_SET(max_core_timmming_frequency));
+ for (temp_count = 0; temp_count < 10; temp_count++)
+ printf("\n.ac_trace_delay[%d]=0x%08x,// %d,0x%08x", temp_count,ddr_set_t_p->ac_trace_delay[temp_count], ddr_set_t_p->ac_trace_delay[temp_count],DDR_TIMMING_OFFSET_DDR_SET(ac_trace_delay[temp_count]));
+ printf("\n.lpddr4_dram_vout_voltage_1_3_2_5_setting=0x%08x,// %d,0x%08x", ddr_set_t_p->lpddr4_dram_vout_voltage_1_3_2_5_setting, ddr_set_t_p->lpddr4_dram_vout_voltage_1_3_2_5_setting,DDR_TIMMING_OFFSET_DDR_SET(lpddr4_dram_vout_voltage_1_3_2_5_setting));
+ printf("\n.lpddr4_x8_mode=0x%08x,// %d,0x%08x", ddr_set_t_p->lpddr4_x8_mode, ddr_set_t_p->lpddr4_x8_mode,DDR_TIMMING_OFFSET_DDR_SET(lpddr4_x8_mode));
+ for (temp_count = 0; temp_count < 28; temp_count++)
+ printf("\n.ac_pinmux[%d]=0x%08x,// %d,0x%08x", temp_count,ddr_set_t_p->ac_pinmux[temp_count], ddr_set_t_p->ac_pinmux[temp_count],DDR_TIMMING_OFFSET_DDR_SET(ac_pinmux[temp_count]));
+ for (temp_count = 0; temp_count < 26; temp_count++)
+ printf("\n.dfi_pinmux[%d]=0x%08x,// %d,0x%08x",temp_count, ddr_set_t_p->dfi_pinmux[temp_count], ddr_set_t_p->dfi_pinmux[temp_count],DDR_TIMMING_OFFSET_DDR_SET(dfi_pinmux[temp_count]));
+
+ printf("\n.slt_test_function[0] =0x%08x,// %d,0x%08x", ddr_set_t_p->slt_test_function[0], ddr_set_t_p->slt_test_function[0],DDR_TIMMING_OFFSET_DDR_SET(slt_test_function[0]));
+ printf("\n.slt_test_function[1] =0x%08x,// %d,0x%08x", ddr_set_t_p->slt_test_function[1], ddr_set_t_p->slt_test_function[1],DDR_TIMMING_OFFSET_DDR_SET(slt_test_function[1]));
+ printf("\n.tdqs2dq=0x%08x,// %d,0x%08x", ddr_set_t_p->tdqs2dq, ddr_set_t_p->tdqs2dq,DDR_TIMMING_OFFSET_DDR_SET(tdqs2dq));
+ printf("\n.dram_data_wr_odt_ohm=0x%08x,// %d,0x%08x", ddr_set_t_p->dram_data_wr_odt_ohm, ddr_set_t_p->dram_data_wr_odt_ohm,DDR_TIMMING_OFFSET_DDR_SET(dram_data_wr_odt_ohm));
+ printf("\n.bitTimeControl_2d=0x%08x,// %d,0x%08x", ddr_set_t_p->bitTimeControl_2d, ddr_set_t_p->bitTimeControl_2d,DDR_TIMMING_OFFSET_DDR_SET(bitTimeControl_2d));
+ if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T7))
+ printf("\n.training_offset=0x%08x,// %d,0x%08x", ddr_set_t_p_t7->training_offset, ddr_set_t_p_t7->training_offset,DDR_TIMMING_OFFSET_DDR_SET_T7(training_offset));
+ for (temp_count = 0; temp_count < 5; temp_count++)
+ printf("\n.ddr_dmc_remap[%d]=0x%08x,// %d,0x%08x",temp_count, ddr_set_t_p->ddr_dmc_remap[temp_count], ddr_set_t_p->ddr_dmc_remap[temp_count],DDR_TIMMING_OFFSET_DDR_SET(ddr_dmc_remap[temp_count]));
+ for (temp_count = 0; temp_count < 4; temp_count++)
+ printf("\n.ddr_lpddr34_ca_remap[%d]=0x%08x,// %d,0x%08x",temp_count ,ddr_set_t_p->ddr_lpddr34_ca_remap[temp_count], ddr_set_t_p->ddr_lpddr34_ca_remap[temp_count],DDR_TIMMING_OFFSET_DDR_SET(ddr_lpddr34_ca_remap[temp_count]));
+ printf("\n.dram_rtt_nom_wr_park[0]=0x%08x,// %d,0x%08x", ddr_set_t_p->dram_rtt_nom_wr_park[0], ddr_set_t_p->dram_rtt_nom_wr_park[0],DDR_TIMMING_OFFSET_DDR_SET(dram_rtt_nom_wr_park[0]));
+ printf("\n.dram_rtt_nom_wr_park[1]=0x%08x,// %d,0x%08x", ddr_set_t_p->dram_rtt_nom_wr_park[1], ddr_set_t_p->dram_rtt_nom_wr_park[1],DDR_TIMMING_OFFSET_DDR_SET(dram_rtt_nom_wr_park[1]));
+ printf("\n.ddr_func=0x%08x,// %d,0x%08x", ddr_set_t_p->ddr_func, ddr_set_t_p->ddr_func,DDR_TIMMING_OFFSET_DDR_SET(ddr_func));
+ for (ps = 0; ps < 2; ps++) {
+ for (temp_count = 0; temp_count < 10; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].ac_trace_delay[%d]=0x%08x,// %d,0x%08x", ps, temp_count,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ac_trace_delay[temp_count],
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ac_trace_delay[temp_count],
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_training_delay_ps[ps].ac_trace_delay[temp_count]));
+
+ for (temp_count = 0; temp_count < 16; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].read_dqs_delay[%d]=0x%08x,// %d,0x%08x", ps, temp_count,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_delay[temp_count],
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_delay[temp_count],
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_training_delay_ps[ps].read_dqs_delay[temp_count]));
+ for (temp_count = 0; temp_count < 72; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].read_dq_bit_delay[%d]=0x%08x,// %d,0x%08x", ps, temp_count,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dq_bit_delay[temp_count],
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dq_bit_delay[temp_count],
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_training_delay_ps[ps].read_dq_bit_delay[temp_count]));
+ for (temp_count = 0; temp_count < 16; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].write_dqs_delay[%d]=0x%08x,// %d,0x%08x", ps, temp_count,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dqs_delay[temp_count],
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dqs_delay[temp_count],
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_training_delay_ps[ps].write_dqs_delay[temp_count]));
+ for (temp_count = 0; temp_count < 72; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].write_dq_bit_delay[%d]=0x%08x,// %d,0x%08x", ps, temp_count,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dq_bit_delay[temp_count],
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dq_bit_delay[temp_count],
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_training_delay_ps[ps].write_dq_bit_delay[temp_count]));
+ for (temp_count = 0; temp_count < 16; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].read_dqs_gate_delay[%d]=0x%08x,// %d,0x%08x", ps, temp_count,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_gate_delay[temp_count],
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_gate_delay[temp_count],
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_training_delay_ps[ps].read_dqs_gate_delay[temp_count]));
+ for (temp_count = 0; temp_count < 36; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].soc_bit_vref[%d]=0x%08x,// %d,0x%08x", ps, temp_count,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[temp_count],
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[temp_count],
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_training_delay_ps[ps].soc_bit_vref[temp_count]));
+ for (temp_count = 0; temp_count < 36; temp_count++)
+ printf("\n.cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[%d]=0x%08x,// %d,0x%08x", temp_count,
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[temp_count],
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[temp_count],
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_phy_common_extra_set_t.csr_soc_vref_dac1_dfe[temp_count]));
+ for (temp_count = 0; temp_count < 32; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].dram_bit_vref[%d]=0x%08x,// %d,0x%08x", ps, temp_count,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dram_bit_vref[temp_count],
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dram_bit_vref[temp_count],
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_training_delay_ps[ps].dram_bit_vref[temp_count]));
+
+ printf("\n.cfg_ddr_training_delay_ps[%d].dfi_mrl=0x%08x,// %d,0x%08x", ps,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_mrl, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_mrl,
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_training_delay_ps[ps].dfi_mrl));
+ printf("\n.cfg_ddr_training_delay_ps[%d].dfi_hwtmrl=0x%08x,// %d,0x%08x", ps,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_hwtmrl, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dfi_hwtmrl,
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_training_delay_ps[ps].dfi_hwtmrl));
+ printf("\n.cfg_ddr_training_delay_ps[%d].ARdPtrInitVal=0x%08x,// %d,0x%08x", ps,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ARdPtrInitVal, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ARdPtrInitVal,
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_training_delay_ps[ps].ARdPtrInitVal));
+
+ printf("\n.cfg_ddr_training_delay_ps[%d].csr_vrefinglobal=0x%08x,// %d,0x%08x", ps,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_vrefinglobal, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_vrefinglobal,
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_training_delay_ps[ps].csr_vrefinglobal));
+ for (temp_count = 0; temp_count < 4; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].csr_dqsrcvcntrl[%d]=0x%08x,// %d,0x%08x", ps, temp_count,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dqsrcvcntrl[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dqsrcvcntrl[temp_count],
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_training_delay_ps[ps].csr_dqsrcvcntrl[temp_count]));
+ for (temp_count = 0; temp_count < 4; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].csr_pptdqscntinvtrntg0[%d]=0x%08x,// %d,0x%08x", ps, temp_count,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg0[temp_count],
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg0[temp_count],
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg0[temp_count]));
+ for (temp_count = 0; temp_count < 4; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].csr_pptdqscntinvtrntg1[%d]=0x%08x,// %d,0x%08x", ps, temp_count,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg1[temp_count],
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg1[temp_count],
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_training_delay_ps[ps].csr_pptdqscntinvtrntg1[temp_count]));
+ for (temp_count = 0; temp_count < 9; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].csr_seq0bgpr[%d]=0x%08x,// %d,0x%08x", ps, temp_count,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_seq0bgpr[temp_count],
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_seq0bgpr[temp_count],
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_training_delay_ps[ps].csr_seq0bgpr[temp_count]));
+ printf("\n.cfg_ddr_training_delay_ps[%d].csr_dllgainctl=0x%08x,// %d,0x%08x", ps,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dllgainctl,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dllgainctl,
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_training_delay_ps[ps].csr_dllgainctl));
+ printf("\n.cfg_ddr_training_delay_ps[%d].csr_dlllockpara=0x%08x,// %d,0x%08x", ps,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dlllockpara,
+ ddr_set_t_p->cfg_ddr_training_delay_ps[ps].csr_dlllockpara,
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_training_delay_ps[ps].csr_dlllockpara));
+ }
+ printf("\n.cfg_ddr_phy_common_extra_set_t.csr_pllctrl3=0x%08x,// %d,0x%08x",
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pllctrl3,
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pllctrl3,
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_phy_common_extra_set_t.csr_pllctrl3));
+ for (temp_count = 0; temp_count < 4; temp_count++)
+ printf("\n.cfg_ddr_phy_common_extra_set_t.csr_pptctlstatic[%d]=0x%08x,// %d,0x%08x", temp_count,
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pptctlstatic[temp_count],
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_pptctlstatic[temp_count],
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_phy_common_extra_set_t.csr_pptctlstatic[temp_count]));
+ for (temp_count = 0; temp_count < 4; temp_count++)
+ printf("\n.cfg_ddr_phy_common_extra_set_t.csr_trainingincdecdtsmen[%d]=0x%08x,// %d,0x%08x", temp_count,
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_trainingincdecdtsmen[temp_count],
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_trainingincdecdtsmen[temp_count],
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_phy_common_extra_set_t.csr_trainingincdecdtsmen[temp_count]));
+ for (temp_count = 0; temp_count < 4; temp_count++)
+ printf("\n.cfg_ddr_phy_common_extra_set_t.csr_tsmbyte0[%d]=0x%08x,// %d,0x%08x", temp_count,
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_tsmbyte0[temp_count],
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_tsmbyte0[temp_count],
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_phy_common_extra_set_t.csr_tsmbyte0[temp_count]));
+
+ printf("\n.cfg_ddr_phy_common_extra_set_t.csr_hwtcamode=0x%08x,// %d,0x%08x",
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtcamode,
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtcamode,
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_phy_common_extra_set_t.csr_hwtcamode));
+ printf("\n.cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsena=0x%08x,// %d,0x%08x",
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsena,
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsena,
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsena));
+ printf("\n.cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsenb=0x%08x,// %d,0x%08x",
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsenb,
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsenb,
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_phy_common_extra_set_t.csr_hwtlpcsenb));
+ printf("\n.cfg_ddr_phy_common_extra_set_t.csr_acsmctrl13=0x%08x,// %d,0x%08x",
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl13,
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl13,
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_phy_common_extra_set_t.csr_acsmctrl13));
+ printf("\n.cfg_ddr_phy_common_extra_set_t.csr_acsmctrl23=0x%08x,// %d,0x%08x",
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl23,
+ ddr_set_t_p->cfg_ddr_phy_common_extra_set_t.csr_acsmctrl23,
+ DDR_TIMMING_OFFSET_DDR_SET(cfg_ddr_phy_common_extra_set_t.csr_acsmctrl23));
+
+ printf("\n},\n");
+ }
+ return 1;
+}
+
+uint32_t ddr_mask_convert_offset(uint32_t mask)
+{
+ uint32_t offset = 0;
+
+ while ((mask & 1)) {
+ offset++;
+ mask = (mask >> 1);
+ }
+ return offset;
+}
+
+uint32_t ddr_cacl_phy_delay_all_step_c2(char test_index, uint32_t value)
+{
+ //value bit0-15 fine value ,bit 16-32 coarse value
+ uint32_t result = 0;
+ uint32_t coarse_value = 0;
+ uint32_t fine_value = 0;
+
+ if (value)
+ coarse_value = (value >> 16);
+ else
+ coarse_value = 0;
+ fine_value = (value & 0xffff);
+ result = (coarse_value * 128 + fine_value);
+ return result;
+}
+
+uint32_t ddr_cacl_phy_over_ride_back_reg_c2(char test_index, uint32_t value)
+{
+ uint32_t result = 0; //bit0-15 fine value ,bit 16-32 coarse value
+
+ if ((test_index == DMC_TEST_WINDOW_INDEX_ATXDLY)) {
+ if (value > (3 * 128 + 127))
+ value = (3 * 128 + 127);
+ result = (value % 128) + ((value / 128) << 16);
+ } else if ((test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) || (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY)) {
+ if (value > (7 * 128 + 127))
+ value = (7 * 128 + 127);
+ result = (value % 128) + ((value / 128) << 16);
+ } else if ((test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) || (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY)) {
+ if (value > (1 * 128 + 127))
+ value = (1 * 128 + 127);
+ result = value;
+ } else if ((test_index == DMC_TEST_WINDOW_INDEX_RXENDLY)) {
+ if (value > (31 * 128 + 127))
+ value = (31 * 128 + 127);
+ result = (value % 128) + ((value / 128) << 16);
+ } else if ((test_index == DMC_TEST_WINDOW_INDEX_SOC_VREF)||
+ (test_index ==DMC_TEST_WINDOW_INDEX_SOC_VREF_DAC1)) {
+ if (value > (63))
+ value = (63);
+ result = value;
+ }
+ return result;
+}
+
+uint32_t ddr_disable_update_delay_line_c2(void)
+{
+ //config phy update use register change and ctrl update req and condition,power on default is or condition
+ //disable ctrl update req
+ return 1;
+}
+
+uint32_t ddr_enable_update_delay_line_c2(void)
+{
+ //config phy update use register change and ctrl update req and condition,power on default is or condition
+ //enable ctrl update req
+ return 1;
+}
+
+uint32_t ddr_phy_training_reg_read_write(ddr_set_t_c2 *p_ddrs, char index,
+ uint32_t sub_index, uint32_t read_write_value, char read_write_enable, char ps)
+{
+ //read_write_value bit0-15 fine value ,bit 16-32 coarse value
+ uint32_t delay_old_value = 0;
+ uint32_t delay_new_value = 0;
+ uint32_t delay_reg_coarse_value = 0;
+ uint32_t delay_reg_fine_value = 0;
+ uint64_t reg_add_coarse = 0;
+ uint32_t reg_add_coarse_bit_mask = 0;
+ uint64_t reg_add_fine = 0;
+ uint32_t reg_add_fine_bit_mask = 0;
+ uint64_t add_base = (p_ddr_base->ddr_phy_base_address);
+ uint32_t reg_offset = 0;
+ uint32_t temp_save = 0;
+
+#define DDR_X32_F0_A800 (0x800)
+#define DDR_X32_F0_A804 (0x804)
+#define DDR_X32_F0_A808 (0x808)
+#define DDR_X32_F0_A810 (0x810)
+#define DDR_X32_F0_A828 (0x828)
+#define DDR_X32_F0_A82C (0x82c)
+#define DDR_X32_F0_A840 (0x840)
+#define DDR_X32_F0_A844 (0x844)
+#define DDR_X32_F0_A850 (0x850)
+#define DDR_X32_F0_A858 (0x858)
+#define DDR_X32_F0_A890 (0x890)
+#define DDR_X32_F0_A8D0 (0x8d0)
+#define DDR_X32_F0_A8F0 (0x8F0)
+#define DDR_X32_F0_A8F8 (0x8F8)
+#define DDR_X32_F0_A8D4 (0x8d4)
+#define DDR_X32_F0_A930 (0x930)
+#define DDR_X32_F0_AC08 (0xc08)
+#define DDR_X32_F0_AC2C (0xc2c)
+#define DDR_X32_F0_AC40 (0xc40)
+#define DDR_X32_F0_AC44 (0xc44)
+#define DDR_X32_F0_AC50 (0xc50)
+#define DDR_X32_F0_AC58 (0xc58)
+#define DDR_X32_F0_ACD0 (0xcd0)
+#define DDR_X32_F0_ACD4 (0xcd4)
+#define DDR_X32_F0_ACF0 (0xcf0)
+#define DDR_X32_F0_ACF8 (0xcf8)
+#define DDR_X32_F0_AD30 (0xD30)
+ reg_offset = ps * (0x1000);
+ if (!index)
+ return read_write_value;
+ //ac group0 then ac group1
+ if (index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
+ if (sub_index < 8) { //ac group 0
+ switch (sub_index) {
+ case 0: //cke0
+ reg_add_coarse = (add_base + DDR_X32_F0_A808 + reg_offset);
+ reg_add_fine = (add_base + DDR_X32_F0_A82C + reg_offset);
+ reg_add_coarse_bit_mask = (~(3 << 4));
+ reg_add_fine_bit_mask = (~(0x7f << 16));
+ break;
+ case 1: //cke1
+ reg_add_coarse = (add_base + DDR_X32_F0_AC08 + reg_offset);
+ reg_add_fine = (add_base + DDR_X32_F0_AC2C + reg_offset);
+ reg_add_coarse_bit_mask = (~(3 << 4));
+ reg_add_fine_bit_mask = (~(0x7f << 16));
+ break;
+ case 2: //cs0
+ reg_add_coarse = (add_base + DDR_X32_F0_A808 + reg_offset);
+ reg_add_fine = (add_base + DDR_X32_F0_A82C + reg_offset);
+ reg_add_coarse_bit_mask = (~(3 << 2));
+ reg_add_fine_bit_mask = (~(0x7f << 8));
+ break;
+ case 3: //cs1
+ reg_add_coarse = (add_base + DDR_X32_F0_AC08 + reg_offset);
+ reg_add_fine = (add_base + DDR_X32_F0_AC2C + reg_offset);
+ reg_add_coarse_bit_mask = (~(3 << 2));
+ reg_add_fine_bit_mask = (~(0x7f << 8));
+ break;
+ case 4: //odt0
+ reg_add_coarse = (add_base + DDR_X32_F0_A808 + reg_offset);
+ reg_add_fine = (add_base + DDR_X32_F0_A82C + reg_offset);
+ reg_add_coarse_bit_mask = (~(3 << 0));
+ reg_add_fine_bit_mask = (~(0x7f << 0));
+ break;
+ case 5: //odt1
+ reg_add_coarse = (add_base + DDR_X32_F0_AC08 + reg_offset);
+ reg_add_fine = (add_base + DDR_X32_F0_AC2C + reg_offset);
+ reg_add_coarse_bit_mask = (~(3 << 0));
+ reg_add_fine_bit_mask = (~(0x7f << 0));
+ break;
+ case 6: //clk
+ reg_add_coarse = (add_base + DDR_X32_F0_A804 + reg_offset);
+ reg_add_fine = (add_base + DDR_X32_F0_A828 + reg_offset);
+ reg_add_coarse_bit_mask = (~(1 << 18));
+ reg_add_fine_bit_mask = (~(0x7f << 8));
+ break;
+ case 7: //this pin use for act pin
+ //reg_add_coarse = 0;
+ //reg_add_fine = 0;
+ reg_add_coarse = (add_base + DDR_X32_F0_A800 + (((36 - 8 - 4 - 2 + 2) / 16) << 2) + reg_offset);
+ reg_add_fine = (add_base + DDR_X32_F0_A810 + (((36 - 8 - 4 - 2 + 2) / 4) << 2) + reg_offset);
+ reg_add_coarse_bit_mask = (~(3 << (((36 - 8 - 4 - 2 + 2) % 16) << 1)));
+ reg_add_fine_bit_mask = (~(0x7f << (((36 - 8 - 4 - 2 + 2) % 4) * 8)));
+
+ break;
+ }
+ } else if (sub_index < (8 + 16)) { ////ac group 1
+ reg_add_coarse = (add_base + DDR_X32_F0_A800 + (((sub_index - 8) / 16) << 2) + reg_offset);
+ reg_add_fine = (add_base + DDR_X32_F0_A810 + (((sub_index - 8) / 4) << 2) + reg_offset);
+ reg_add_coarse_bit_mask = (~(3 << (((sub_index - 8) % 16) << 1)));
+ reg_add_fine_bit_mask = (~(0x7f << (((sub_index - 8) % 4) * 8)));
+ } else if (sub_index < (8 + 16 + 4)) {
+ reg_add_coarse = 0;
+ reg_add_fine = 0;
+ } else if (sub_index < (8 + 16 + 4 + 3 + 2)) {
+ reg_add_coarse = (add_base + DDR_X32_F0_A800 + (((sub_index - 8 - 4) / 16) << 2) + reg_offset);
+ reg_add_fine = (add_base + DDR_X32_F0_A810 + (((sub_index - 8 - 4) / 4) << 2) + reg_offset);
+ reg_add_coarse_bit_mask = (~(3 << (((sub_index - 8 - 4) % 16) << 1)));
+ reg_add_fine_bit_mask = (~(0x7f << (((sub_index - 8 - 4) % 4) * 8)));
+ }
+#if 0
+ else if (sub_index < (8 + 16 + 4 + 3 + 2)) {
+ reg_add_coarse = 0;
+ reg_add_fine = 0;
+ }
+#endif
+ else if (sub_index < (8 + 28)) {
+ reg_add_coarse = (add_base + DDR_X32_F0_A800 + (((sub_index - 8 - 4 - 2 + 2) / 16) << 2) + reg_offset);
+ reg_add_fine = (add_base + DDR_X32_F0_A810 + (((sub_index - 8 - 4 - 2 + 2) / 4) << 2) + reg_offset);
+ reg_add_coarse_bit_mask = (~(3 << (((sub_index - 8 - 4 - 2 + 2) % 16) << 1)));
+ reg_add_fine_bit_mask = (~(0x7f << (((sub_index - 8 - 4 - 2 + 2) % 4) * 8)));
+ } else {
+ reg_add_coarse = 0;
+ reg_add_fine = 0;
+ }
+ } else if (index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
+ reg_add_coarse = (add_base + DDR_X32_F0_A8D4 + (sub_index / 4) * (
+ DDR_X32_F0_ACD4 - DDR_X32_F0_A8D4) + (((sub_index % 4) << 1) << 2) + reg_offset);
+ reg_add_fine = (add_base + DDR_X32_F0_A8F8 + (sub_index / 4) * (
+ DDR_X32_F0_ACF8 - DDR_X32_F0_A8F8) + ((sub_index % 4) << 4) + reg_offset);
+ reg_add_coarse_bit_mask = (~(3 << ((4))));
+ reg_add_fine_bit_mask = (~(0x7f << 8));
+ } else if (index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) {
+ reg_add_coarse = 0;
+ reg_add_fine = (add_base + DDR_X32_F0_A858 + (sub_index / 4) * (
+ DDR_X32_F0_AC58 - DDR_X32_F0_A858) + ((sub_index % 4) << 4) + reg_offset);
+ reg_add_coarse_bit_mask = 0;
+ reg_add_fine_bit_mask = (~(0xff << (8)));
+ }
+ //d0-d7 dm0 d8-d15 dm1...
+ else if (index == DMC_TEST_WINDOW_INDEX_TXDQDLY) {
+ reg_add_coarse = (add_base + DDR_X32_F0_A8D0 + (sub_index / 36) * (DDR_X32_F0_ACD0
+ - DDR_X32_F0_A8D0) + ((((sub_index % 36) / 9) << 1) << 2) + (((((sub_index) % 9) / 8)) << 2) + reg_offset);
+ reg_add_fine = (add_base + DDR_X32_F0_A8F0 + (sub_index / 36) * (DDR_X32_F0_ACF0
+ - DDR_X32_F0_A8F0) + ((((sub_index % 36) / 9)) << 4) + (((((sub_index) % 9)) >> 2) << 2) + reg_offset);
+ reg_add_coarse_bit_mask = (~(7 << (((((sub_index) % 9) % 8) << 2))));
+ reg_add_fine_bit_mask = (~(0x7f << (((((sub_index) % 9) % 4) << 3))));
+ }
+ //d0-d7 dm0 d8-d15 dm1...
+ else if (index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
+ reg_add_coarse = 0;
+ reg_add_fine = (add_base + DDR_X32_F0_A850 + (sub_index / 36) * (DDR_X32_F0_AC50
+ - DDR_X32_F0_A850) + ((((sub_index % 36) / 9)) << 4) + (((sub_index % 9) >> 2) << 2) + reg_offset);
+ reg_add_coarse_bit_mask = 0;
+ reg_add_fine_bit_mask = (~(0xff << (((((sub_index) % 9) % 4) << 3))));
+ } else if (index == DMC_TEST_WINDOW_INDEX_RXENDLY) {
+ reg_add_coarse = (add_base + DDR_X32_F0_A840 + (sub_index / 4) * (DDR_X32_F0_AC40
+ - DDR_X32_F0_A840) + reg_offset);
+ reg_add_fine = (add_base + DDR_X32_F0_A844 + (sub_index / 4) * (DDR_X32_F0_AC44
+ - DDR_X32_F0_A844) + reg_offset);
+ reg_add_coarse_bit_mask = (~(0x1f << ((sub_index << 3))));
+ reg_add_fine_bit_mask = (~(0x7f << ((sub_index << 3))));
+ } else if (index == DMC_TEST_WINDOW_INDEX_SOC_VREF) {
+ if (sub_index < (36)) { //vref dq and dbi
+ reg_add_coarse = 0;
+ reg_add_fine = (add_base + DDR_X32_F0_A890 + (((sub_index / 9) * 4) << 2)
+ + (((sub_index % 9) >> 2) << 2) + reg_offset);
+ reg_add_coarse_bit_mask = 0;
+ reg_add_fine_bit_mask = (~(0x3f << (((((sub_index) % 9) % 4) << 3))));
+ } else if (sub_index < (44)) { //vref dqs and dqsn
+ reg_add_coarse = 0;
+ reg_add_fine = (add_base + DDR_X32_F0_A890 + 8 + ((((sub_index - 36) / 2) * 4) << 2) + reg_offset);
+ reg_add_coarse_bit_mask = 0;
+ reg_add_fine_bit_mask = (~(0x3f << (((((sub_index - 36) % 2)) << 3) + 8)));
+ }
+ } else if (index == DMC_TEST_WINDOW_INDEX_SOC_VREF_DAC1) {
+ if (sub_index < (36)) { //vref dq and dbi
+ reg_add_coarse = 0;
+ reg_add_fine = (add_base + DDR_X32_F0_A890+ 0x100 + (((sub_index / 9) * 4) << 2)
+ + (((sub_index % 9) >> 2) << 2) + reg_offset);
+ reg_add_coarse_bit_mask = 0;
+ reg_add_fine_bit_mask = (~(0x3f << (((((sub_index) % 9) % 4) << 3))));
+ } else if (sub_index < (44)) { //vref dqs and dqsn
+ reg_add_coarse = 0;
+ reg_add_fine = (add_base + DDR_X32_F0_A890 + 0x100+ 8 + ((((sub_index - 36) / 2) * 4) << 2) + reg_offset);
+ reg_add_coarse_bit_mask = 0;
+ reg_add_fine_bit_mask = (~(0x3f << (((((sub_index - 36) % 2)) << 3) + 8)));
+ }
+ } else if (index == DMC_TEST_WINDOW_INDEX_DRAM_VREF) {
+ if (sub_index < (36)) { //DDR_X32_F0_AD30 DDR_X32_F0_A930
+ reg_add_coarse = 0;
+ reg_add_fine = (add_base + DDR_X32_F0_A930 +
+ ((DDR_X32_F0_AD30 - DDR_X32_F0_A930) * sub_index % 2) + reg_offset);
+ reg_add_coarse_bit_mask = 0;
+ reg_add_fine_bit_mask = (~(0xff << 0));
+ }
+ } else if (index == DMC_TEST_WINDOW_INDEX_EXTERA_PS) {
+ if (sub_index == 1) { //DDR_X32_F0_AD30 DDR_X32_F0_A930
+ }
+
+ return read_write_value;
+ }
+
+ {
+ if (reg_add_coarse)
+ delay_reg_coarse_value = (((rd_reg(reg_add_coarse)) & (~reg_add_coarse_bit_mask))
+ >> (ddr_mask_convert_offset(reg_add_coarse_bit_mask)));
+ if (reg_add_fine)
+ delay_reg_fine_value = (((rd_reg(reg_add_fine)) & (~reg_add_fine_bit_mask))
+ >> (ddr_mask_convert_offset(reg_add_fine_bit_mask)));
+
+ delay_old_value = ((delay_reg_coarse_value << 16) | delay_reg_fine_value);
+ delay_old_value = ddr_cacl_phy_delay_all_step_c2(index, delay_old_value);
+ }
+
+ if (read_write_enable == REGISTER_READ) {
+ read_write_value = delay_old_value;
+ } else if (read_write_enable == REGISTER_WRITE) {
+ delay_new_value = read_write_value;
+ delay_new_value = ddr_cacl_phy_over_ride_back_reg_c2(index, delay_new_value);
+ temp_save = rd_reg(p_ddr_base->ddr_dmc_refresh_ctrl_address);
+ wr_reg((p_ddr_base->ddr_dmc_refresh_ctrl_address), 0x21); //take care T5 no set bit //bit 22 dmc to control DFI_CTRLUPD_REQ with zq generation together.
+ ddr_udelay_dummy(1);
+ wr_reg(p_ddr_base->ddr_phy_base_address + 0x2440, 1); //detect should update delay when controller update arrive
+ ddr_udelay_dummy(1);
+ if (reg_add_coarse)
+ wr_reg(reg_add_coarse, ((rd_reg(reg_add_coarse)) & (reg_add_coarse_bit_mask))
+ | ((delay_new_value >> 16) << (ddr_mask_convert_offset(reg_add_coarse_bit_mask))));
+ if (reg_add_fine)
+ wr_reg(reg_add_fine, ((rd_reg(reg_add_fine)) & (reg_add_fine_bit_mask))
+ | ((delay_new_value & 0xffff) << (ddr_mask_convert_offset(reg_add_fine_bit_mask))));
+ ddr_udelay_dummy(1);
+ //wr_reg(p_ddr_base->ddr_phy_base_address + 0x2440, 1); //no need force release ,because maybe have glitch when ddr read/write ,must upadate on the rfc stage
+ //wr_reg(p_ddr_base->ddr_phy_base_address + 0x2440, 2);
+ //ddr_udelay_dummy(1);
+ //wr_reg(p_ddr_base->ddr_phy_base_address + 0x2440, 0);
+ //ddr_udelay_dummy(1);
+ wr_reg((p_ddr_base->ddr_dmc_refresh_ctrl_address), (temp_save & (~((1 << 22) | (1 << 4)))));
+ ddr_udelay_dummy(1);
+ wr_reg((p_ddr_base->ddr_dmc_refresh_ctrl_address), (temp_save & (~((1 << 22)))) | (1 << 4));
+ ddr_udelay_dummy(40); //since we are use 3 refresh time ,so shuld over 4*7.8us make sure a update command send out ,then maybe fail
+ wr_reg((p_ddr_base->ddr_dmc_refresh_ctrl_address), (temp_save & (~((1 << 22)))) | (1 << 4));
+ ddr_udelay_dummy(1);
+ wr_reg((p_ddr_base->ddr_dmc_refresh_ctrl_address), (temp_save));
+ }
+ printf("delay_old_value,%08x,read_write_value,%08x,index,%08x,sub_index,%08x\n", delay_old_value, read_write_value, index, sub_index);
+
+ return read_write_value;
+}
+
+void ddr_read_write_training_value(ddr_set_t_c2 *p_ddrs, char over_ride_index,
+ char read_write, uint32_t ps, void *input, char print)
+{
+ uint16_t t_count = 0;
+ char count_max = 72;
+ uint16_t t_count_value = 0;
+ uint16_t delay_temp = 0;
+ char *input_uint8_p = input;
+ uint16_t *input_uint16_p = input;
+ char p_size = 1;
+ char read_skip = 0;
+
+ for (t_count = 0; t_count < count_max; t_count++) {
+ if ((over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY)
+ || (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY)
+ || (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY)
+ || (over_ride_index == DMC_TEST_WINDOW_INDEX_RXENDLY)
+ || (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY)
+ || (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY)
+ || (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF)
+ || (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF_DAC1)
+ ) {
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
+ p_size = 2;
+ count_max = 36;
+ } else if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
+ p_size = 2;
+ count_max = 8;
+ } else if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
+ p_size = 1;
+ count_max = 72;
+ } else if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXENDLY) {
+ p_size = 2;
+ count_max = 8;
+ } else if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) {
+ p_size = 1;
+ count_max = 8;
+ } else if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) {
+ p_size = 2;
+ count_max = 72;
+ } else if ((over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) ||
+ (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF_DAC1))
+ {
+ p_size = 1;
+ count_max = 44;
+ } else if (over_ride_index == DMC_TEST_WINDOW_INDEX_EXTERA_PS) {
+ p_size = 2;
+ count_max = 8;
+ }
+ if (read_write == REGISTER_READ) {
+ read_skip = 0;
+ if ((ps == 3) && ((over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF)||
+ (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF_DAC1))) {
+ if (t_count > 35)
+ read_skip = 1;
+ else //ro training no vref value
+ if ((t_count % 9) == 8)
+ read_skip = 1;
+ }
+ t_count_value = ddr_phy_training_reg_read_write(p_ddrs,
+ over_ride_index, t_count, t_count_value, read_write, ps);
+ delay_temp = t_count_value;
+ if (read_skip) {
+ } else {
+ if (p_size == 1)
+ (*input_uint8_p) = delay_temp;
+ if (p_size == 2)
+ (*input_uint16_p) = delay_temp;
+ }
+ } else {
+ if (p_size == 1)
+ delay_temp = (*input_uint8_p);
+ if (p_size == 2)
+ delay_temp = (*input_uint16_p);
+ t_count_value = delay_temp;
+ ddr_phy_training_reg_read_write(p_ddrs, over_ride_index, t_count, t_count_value, read_write, ps);
+ }
+ if (p_size == 1)
+ input_uint8_p++;
+ if (p_size == 2)
+ input_uint16_p++;
+
+ if (print == DDR_PRINT_ENABLE) {
+ printf("training_index %d sub_index %d phase %d\n", over_ride_index, t_count, t_count_value);
+ } else { //maybe funciton will be optimize not use the variable
+ }
+ //printf("training_index %d sub_index %d phase %d\n", over_ride_index, t_count, t_count_value);
+ }
+ }
+} /* ddr_read_write_training_value */
+
+void ddr_read_write_training_all_delay_value(ddr_set_t_c2 *p_ddrs, char read_write, char print)
+{
+ uint32_t ps = 0;
+
+ for (ps = 0; ps < 2; ) {
+ ddr_read_write_training_value(p_ddrs, DMC_TEST_WINDOW_INDEX_ATXDLY,
+ read_write, ps, &(p_ddrs->cfg_ddr_training_delay_ps[ps].ac_trace_delay), print);
+ ddr_read_write_training_value(p_ddrs, DMC_TEST_WINDOW_INDEX_TXDQSDLY,
+ read_write, ps, &(p_ddrs->cfg_ddr_training_delay_ps[ps].write_dqs_delay), print);
+ ddr_read_write_training_value(p_ddrs, DMC_TEST_WINDOW_INDEX_RXCLKDLY,
+ read_write, ps, &(p_ddrs->cfg_ddr_training_delay_ps[ps].read_dqs_delay), print);
+ ddr_read_write_training_value(p_ddrs, DMC_TEST_WINDOW_INDEX_TXDQDLY,
+ read_write, ps, &(p_ddrs->cfg_ddr_training_delay_ps[ps].write_dq_bit_delay), print);
+ ddr_read_write_training_value(p_ddrs, DMC_TEST_WINDOW_INDEX_RXPBDLY,
+ read_write, ps, &(p_ddrs->cfg_ddr_training_delay_ps[ps].read_dq_bit_delay), print);
+ ddr_read_write_training_value(p_ddrs, DMC_TEST_WINDOW_INDEX_RXENDLY,
+ read_write, ps, &(p_ddrs->cfg_ddr_training_delay_ps[ps].read_dqs_gate_delay), print);
+ ddr_read_write_training_value(p_ddrs, DMC_TEST_WINDOW_INDEX_SOC_VREF,
+ read_write, ps, &(p_ddrs->cfg_ddr_training_delay_ps[ps].soc_bit_vref), print);
+ ddr_read_write_training_value(p_ddrs, DMC_TEST_WINDOW_INDEX_SOC_VREF_DAC1,
+ read_write, ps, &(p_ddrs->cfg_ddr_training_delay_ps[ps].soc_bit_vref_dac1), print);
+ ddr_read_write_training_value(p_ddrs, DMC_TEST_WINDOW_INDEX_EXTERA_PS,
+ read_write, ps, 0, print);
+ p_ddrs->cfg_ddr_training_delay_ps[ps].dram_bit_vref[0] = ((rd_reg(p_ddr_base->ddr_phy_base_address + 0x3930)) & 0x3f);
+
+ ps = ps + 1;
+ }
+}
+
+uint32_t ddr_get_c2_bdlr_100step_min(void)
+{
+ uint32_t bdlr_100step = 0;
+ uint32_t DRAMFreq = 0;
+ uint32_t stick_store_sticky_f0_reg_base_t = (p_ddr_base->ddr_phy_base_address + 0x0128);
+
+ DRAMFreq = rd_reg(stick_store_sticky_f0_reg_base_t);
+ uint32_t dll_counter = 0;
+ uint32_t dll_counter_max = 0;
+
+ dll_counter = (((rd_reg(p_ddr_base->ddr_phy_base_address + 0x3130))));
+ dll_counter_max = ddr_max((dll_counter & 0xff), ((dll_counter >> 8) & 0xff));
+ dll_counter_max = ddr_max(dll_counter_max, ((dll_counter >> 16) & 0xff));
+ dll_counter_max = ddr_max(dll_counter_max, ((dll_counter >> 24) & 0xff));
+ dll_counter_max = dll_counter_max ? dll_counter_max : 1;
+ bdlr_100step = (100000000 / (2 * (DRAMFreq))) / (dll_counter_max);
+ return bdlr_100step;
+}
+
+uint32_t ddr_get_c2_bdlr_100step_max(void)
+{
+ uint32_t bdlr_100step = 0;
+ uint32_t DRAMFreq = 0;
+ uint32_t stick_store_sticky_f0_reg_base_t = (p_ddr_base->ddr_phy_base_address + 0x0128);
+
+ DRAMFreq = rd_reg(stick_store_sticky_f0_reg_base_t);
+ uint32_t dll_counter = 0;
+ uint32_t dll_counter_min = 0;
+
+ dll_counter = (((rd_reg(p_ddr_base->ddr_phy_base_address + 0x312c))));
+ dll_counter_min = ddr_min((dll_counter & 0xff), ((dll_counter >> 8) & 0xff));
+ dll_counter_min = ddr_min(dll_counter_min, ((dll_counter >> 16) & 0xff));
+ dll_counter_min = ddr_min(dll_counter_min, ((dll_counter >> 24) & 0xff));
+ dll_counter_min = dll_counter_min ? dll_counter_min : 1;
+ bdlr_100step = (100000000 / (2 * (DRAMFreq))) / (dll_counter_min);
+ return bdlr_100step;
+}
+
+uint32_t ddr_get_c2_bdlr_100step(void)
+{
+ uint32_t bdlr_100step = 0;
+ uint32_t DRAMFreq = 0;
+ uint32_t dll_counter = 0;
+ uint32_t stick_store_sticky_f0_reg_base_t = (p_ddr_base->ddr_phy_base_address + 0x0128);
+
+ DRAMFreq = rd_reg(stick_store_sticky_f0_reg_base_t);
+ dll_counter = rd_reg(p_ddr_base->ddr_phy_base_address + 0x3128);
+ dll_counter = (((dll_counter & 0xff) + ((dll_counter >> 8) & 0xff) + ((dll_counter >> 16) & 0xff) + ((dll_counter >> 24) & 0xff)) >> 2);
+ bdlr_100step = (100000000 / (2 * DRAMFreq)) / (dll_counter + 1);
+ return bdlr_100step;
+}
+
+uint32_t ddr_get_c2_bdlr_100step_cur(void)
+{
+ uint32_t bdlr_100step = 0;
+ uint32_t DRAMFreq = 0;
+ uint32_t dll_counter = 0;
+ uint32_t stick_store_sticky_f0_reg_base_t = (p_ddr_base->ddr_phy_base_address + 0x0128);
+
+ DRAMFreq = rd_reg(stick_store_sticky_f0_reg_base_t);
+ dll_counter = rd_reg(p_ddr_base->ddr_phy_base_address + 0x3100);
+ dll_counter = (((dll_counter >> 1) & 0xff));
+ bdlr_100step = (100000000 / (2 * DRAMFreq)) / (dll_counter + 1);
+ // printf("\nrdll_counter=%08x ", rd_reg(p_ddr_base->ddr_phy_base_address + 0x3100));
+ return bdlr_100step;
+}
+
+uint32_t ddr_get_ui_1_128_100step(void)
+{
+ uint32_t DRAMFreq = 0;
+ uint32_t stick_store_sticky_f0_reg_base_t = (p_ddr_base->ddr_phy_base_address + 0x0128);
+
+ DRAMFreq = rd_reg(stick_store_sticky_f0_reg_base_t);
+ return (1000000 * 100 / (2 * 128)) / ((DRAMFreq));
+}
+
+uint32_t do_read_c2_ddr_bdlr_steps(void)
+{
+ uint32_t DRAMFreq = 0;
+
+ DRAMFreq = get_ddr_clk();
+ printf("\nc2_chip_DRAMFreq=%d MHz,100min_bdlr=%d ps,100max_bdlr=%d ps,ave_100_bdlr=%d ps,bdlr_var=%d thousand,cur_100_bdlr=%d ps\n",
+ DRAMFreq, ddr_get_c2_bdlr_100step_min(), ddr_get_c2_bdlr_100step_max(), ddr_get_c2_bdlr_100step(),
+ 2000 * (ddr_get_c2_bdlr_100step_max() - ddr_get_c2_bdlr_100step_min()) / (ddr_get_c2_bdlr_100step_max() + ddr_get_c2_bdlr_100step_min()), ddr_get_c2_bdlr_100step_cur());
+
+ return ddr_get_c2_bdlr_100step();
+}
+
+int do_read_c2_ddr_training_data(char log_level, ddr_set_t_c2 *ddr_set_t_p)
+{
+ uint32_t stick_store_sticky_f0_reg_base_t = (p_ddr_base->ddr_phy_base_address + 0x0128);
+ uint32_t stick_store_sticky_f1_reg_base_t = (p_ddr_base->ddr_phy_base_address + 0x1128);
+
+ printf_log(log_level, "\nddr_set_t_p==0x%08x\n", (uint32_t)(uint64_t)(ddr_set_t_p));
+ uint32_t loop = 0;
+ uint32_t loop_max = (4 + (0x3f << 2)); //((DMC_STICKY_63-DMC_STICKY_0));
+ for (loop = 0; loop < loop_max; loop += 4)
+ wr_reg(((uint64_t)(ddr_set_t_p) + loop), rd_reg((p_ddr_base->ddr_dmc_sticky0) + loop));
+ loop_max = sizeof(board_SI_setting_ps_t);
+ for (loop = 0; loop < loop_max; loop += 4)
+ wr_reg(((uint64_t)(&(ddr_set_t_p->cfg_board_SI_setting_ps[0])) + loop), rd_reg((stick_store_sticky_f0_reg_base_t + loop)));
+ for (loop = 0; loop < loop_max; loop += 4)
+ wr_reg(((uint64_t)(&(ddr_set_t_p->cfg_board_SI_setting_ps[1])) + loop), rd_reg((stick_store_sticky_f1_reg_base_t + loop)));
+ for (loop = 0; loop < MESON_CPU_CHIP_ID_SIZE; loop++) //update chip id
+
+ ddr_sha_c2.sha_chip_id[loop] = global_chip_id[loop];
+ {
+ bdlr_100step = get_bdlr_100step(global_ddr_clk);
+ ui_1_32_100step = (1000000 * 100 / (global_ddr_clk * 2 * 32));
+ ddr_read_write_training_all_delay_value(ddr_set_t_p, REGISTER_READ, ~log_level);
+ }
+ return 1;
+}
+
+int do_ddr_display_c2_ddr_information(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int i = 0;
+ unsigned int ps = 0;
+
+ printf("\nargc== 0x%08x\n", argc);
+ for (i = 0; i < argc; i++)
+ printf("\nargv[%d]=%s\n", i, argv[i]);
+
+ do_read_c2_ddr_training_data(0, ddr_set_t_p);
+
+ {
+ uint32_t count = 0;
+ uint32_t reg_add_offset = 0;
+
+ printf("\n PCTL timming: 0x");
+
+ for (count = 0; count < ((p_ddr_base->ddr_pctl_timing_end_address) - (p_ddr_base->ddr_pctl_timing_base_address)); ) {
+ reg_add_offset = ((p_ddr_base->ddr_pctl_timing_base_address) + (count));
+ printf("\n reg_add_offset: %08x %08x %08x ", reg_add_offset, readl(reg_add_offset), reg_add_offset);
+ count = count + 4;
+ }
+ printf("\n mrs register: ");
+ printf("\n mrs register: base (0x54000<<1)+DDR_PHY_BASE,%08x byte offset\n", (0x54000 << 1) + (p_ddr_base->ddr_phy_base_address));
+
+ printf("\n sticky register: ");
+ {
+ uint32_t loop_max = 0;
+ loop_max = 64 << 2; //sizeof(ddr_set_t);
+ for (count = 0; count < loop_max; count += 4)
+ printf("\n reg_add_offset: %08x %08x %08x", count, rd_reg((uint64_t)((p_ddr_base->ddr_dmc_sticky0)) + count), (((p_ddr_base->ddr_dmc_sticky0)) + count));
+ }
+
+ {
+ uint32_t loop_max = 0;
+ loop_max = sizeof(ddr_set_t_c2);
+ uint32_t count = 0;
+ for (count = 0; count < loop_max; ) {
+ printf("\n%08x %08x", count, rd_reg((uint64_t)(ddr_set_t_p) + count));
+ count = count + 4;
+ }
+ }
+ }
+
+ printf("\n {");
+
+ uint32_t temp_count = 0;
+ {
+ printf("\n//old fast_boot[%d]=0x%08x,// %d", 0, ddr_set_t_p->cfg_board_common_setting.fast_boot[0], ddr_set_t_p->cfg_board_common_setting.fast_boot[0]);
+ ddr_set_t_p->cfg_board_common_setting.fast_boot[0] = 0xfd; //add for auto copy to code test
+ for (temp_count = 0; temp_count < 4; temp_count++)
+ printf("\n.cfg_board_common_setting.fast_boot[%d]=0x%08x,// %d", temp_count, ddr_set_t_p->cfg_board_common_setting.fast_boot[temp_count], ddr_set_t_p->cfg_board_common_setting.fast_boot[temp_count]);
+
+ printf("\n.cfg_board_common_setting.timming_magic=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.timming_magic, ddr_set_t_p->cfg_board_common_setting.timming_magic);
+ printf("\n.cfg_board_common_setting.timming_max_valid_configs=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.timming_max_valid_configs, ddr_set_t_p->cfg_board_common_setting.timming_max_valid_configs);
+ printf("\n.cfg_board_common_setting.timming_struct_version=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.timming_struct_version, ddr_set_t_p->cfg_board_common_setting.timming_struct_version);
+ printf("\n.cfg_board_common_setting.timming_struct_org_size=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.timming_struct_org_size, ddr_set_t_p->cfg_board_common_setting.timming_struct_org_size);
+ printf("\n.cfg_board_common_setting.timming_struct_real_size=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.timming_struct_real_size, ddr_set_t_p->cfg_board_common_setting.timming_struct_real_size);
+ printf("\n.cfg_board_common_setting.ddr_func=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.ddr_func, ddr_set_t_p->cfg_board_common_setting.ddr_func);
+ printf("\n.cfg_board_common_setting.board_id=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.board_id, ddr_set_t_p->cfg_board_common_setting.board_id);
+ printf("\n.cfg_board_common_setting.DramType=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.DramType, ddr_set_t_p->cfg_board_common_setting.DramType);
+ printf("\n.cfg_board_common_setting.dram_rank_config=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.dram_rank_config, ddr_set_t_p->cfg_board_common_setting.dram_rank_config);
+ printf("\n.cfg_board_common_setting.DisabledDbyte=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.DisabledDbyte, ddr_set_t_p->cfg_board_common_setting.DisabledDbyte);
+ printf("\n.cfg_board_common_setting.dram_cs0_base_add=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.dram_cs0_base_add, ddr_set_t_p->cfg_board_common_setting.dram_cs0_base_add);
+ printf("\n.cfg_board_common_setting.dram_cs1_base_add=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.dram_cs1_base_add, ddr_set_t_p->cfg_board_common_setting.dram_cs1_base_add);
+ printf("\n.cfg_board_common_setting.dram_cs0_size_MB=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.dram_cs0_size_MB, ddr_set_t_p->cfg_board_common_setting.dram_cs0_size_MB);
+ printf("\n.cfg_board_common_setting.dram_cs1_size_MB=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.dram_cs1_size_MB, ddr_set_t_p->cfg_board_common_setting.dram_cs1_size_MB);
+ printf("\n.cfg_board_common_setting.dram_x4x8x16_mode=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.dram_x4x8x16_mode, ddr_set_t_p->cfg_board_common_setting.dram_x4x8x16_mode);
+ printf("\n.cfg_board_common_setting.Is2Ttiming=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.Is2Ttiming, ddr_set_t_p->cfg_board_common_setting.Is2Ttiming);
+ printf("\n.cfg_board_common_setting.log_level=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.log_level, ddr_set_t_p->cfg_board_common_setting.log_level);
+ printf("\n.cfg_board_common_setting.ddr_rdbi_wr_enable=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.ddr_rdbi_wr_enable, ddr_set_t_p->cfg_board_common_setting.ddr_rdbi_wr_enable);
+ printf("\n.cfg_board_common_setting.pll_ssc_mode=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.pll_ssc_mode, ddr_set_t_p->cfg_board_common_setting.pll_ssc_mode);
+ printf("\n.cfg_board_common_setting.org_tdqs2dq=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.org_tdqs2dq, ddr_set_t_p->cfg_board_common_setting.org_tdqs2dq);
+ for (temp_count = 0; temp_count < 2; temp_count++)
+ printf("\n.cfg_board_common_setting.reserve1_test_function[%d]=0x%08x,// %d", temp_count, ddr_set_t_p->cfg_board_common_setting.reserve1_test_function[temp_count], ddr_set_t_p->cfg_board_common_setting.reserve1_test_function[temp_count]);
+ for (temp_count = 0; temp_count < 5; temp_count++)
+ printf("\n.cfg_board_common_setting.ddr_dmc_remap[%d]=0x%08x,// %d", temp_count, ddr_set_t_p->cfg_board_common_setting.ddr_dmc_remap[temp_count], ddr_set_t_p->cfg_board_common_setting.ddr_dmc_remap[temp_count]);
+ for (temp_count = 0; temp_count < 35; temp_count++)
+ printf("\n.cfg_board_common_setting.ac_pinmux[%d]=0x%08x,// %d", temp_count, ddr_set_t_p->cfg_board_common_setting.ac_pinmux[temp_count], (uint32_t)ddr_set_t_p->cfg_board_common_setting.ac_pinmux[temp_count]);
+ printf("\n.cfg_board_common_setting.ddr_dqs_swap=0x%08x,// %d", ddr_set_t_p->cfg_board_common_setting.ddr_dqs_swap, ddr_set_t_p->cfg_board_common_setting.ddr_dqs_swap);
+ for (temp_count = 0; temp_count < 36; temp_count++)
+ printf("\n.cfg_board_common_setting.ddr_dq_remap[%d]=0x%08x,// %d", temp_count, ddr_set_t_p->cfg_board_common_setting.ddr_dq_remap[temp_count], (uint32_t)ddr_set_t_p->cfg_board_common_setting.ddr_dq_remap[temp_count]);
+ for (temp_count = 0; temp_count < 4; temp_count++)
+ printf("\n.cfg_board_common_setting.ddr_vddee_setting[%d]=0x%08x,// %d", temp_count, ddr_set_t_p->cfg_board_common_setting.ddr_vddee_setting[temp_count], (uint32_t)ddr_set_t_p->cfg_board_common_setting.ddr_vddee_setting[temp_count]);
+
+
+
+
+ for (ps = 0; ps < 2; ps++) {
+ printf("\n.cfg_board_SI_setting_ps[%d].DRAMFreq=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].DRAMFreq, ddr_set_t_p->cfg_board_SI_setting_ps[ps].DRAMFreq);
+ printf("\n.cfg_board_SI_setting_ps[%d].PllBypassEn=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].PllBypassEn, ddr_set_t_p->cfg_board_SI_setting_ps[ps].PllBypassEn);
+ printf("\n.cfg_board_SI_setting_ps[%d].training_SequenceCtrl=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].training_SequenceCtrl, ddr_set_t_p->cfg_board_SI_setting_ps[ps].training_SequenceCtrl);
+ printf("\n.cfg_board_SI_setting_ps[%d].ddr_odt_config=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].ddr_odt_config, ddr_set_t_p->cfg_board_SI_setting_ps[ps].ddr_odt_config);
+ printf("\n.cfg_board_SI_setting_ps[%d].clk_drv_ohm=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].clk_drv_ohm, ddr_set_t_p->cfg_board_SI_setting_ps[ps].clk_drv_ohm);
+ printf("\n.cfg_board_SI_setting_ps[%d].cs_drv_ohm=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].cs_drv_ohm, ddr_set_t_p->cfg_board_SI_setting_ps[ps].cs_drv_ohm);
+ printf("\n.cfg_board_SI_setting_ps[%d].ac_drv_ohm=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].ac_drv_ohm, ddr_set_t_p->cfg_board_SI_setting_ps[ps].ac_drv_ohm);
+ printf("\n.cfg_board_SI_setting_ps[%d].soc_data_drv_ohm_p=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].soc_data_drv_ohm_p, ddr_set_t_p->cfg_board_SI_setting_ps[ps].soc_data_drv_ohm_p);
+ printf("\n.cfg_board_SI_setting_ps[%d].soc_data_drv_ohm_n=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].soc_data_drv_ohm_n, ddr_set_t_p->cfg_board_SI_setting_ps[ps].soc_data_drv_ohm_n);
+ printf("\n.cfg_board_SI_setting_ps[%d].soc_data_odt_ohm_p=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].soc_data_odt_ohm_p, ddr_set_t_p->cfg_board_SI_setting_ps[ps].soc_data_odt_ohm_p);
+ printf("\n.cfg_board_SI_setting_ps[%d].soc_data_odt_ohm_n=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].soc_data_odt_ohm_n, ddr_set_t_p->cfg_board_SI_setting_ps[ps].soc_data_odt_ohm_n);
+ printf("\n.cfg_board_SI_setting_ps[%d].dram_data_drv_ohm=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_data_drv_ohm, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_data_drv_ohm);
+ printf("\n.cfg_board_SI_setting_ps[%d].dram_data_odt_ohm=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_data_odt_ohm, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_data_odt_ohm);
+ printf("\n.cfg_board_SI_setting_ps[%d].dram_data_wr_odt_ohm=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_data_wr_odt_ohm, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_data_wr_odt_ohm);
+ printf("\n.cfg_board_SI_setting_ps[%d].dram_ac_odt_ohm=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_ac_odt_ohm, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_ac_odt_ohm);
+ printf("\n.cfg_board_SI_setting_ps[%d].dram_data_drv_pull_up_calibration_ohm=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_data_drv_pull_up_calibration_ohm, ddr_set_t_p->cfg_board_SI_setting_ps[ps].dram_data_drv_pull_up_calibration_ohm);
+ printf("\n.cfg_board_SI_setting_ps[%d].lpddr4_dram_vout_voltage_range_setting=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].lpddr4_dram_vout_voltage_range_setting, ddr_set_t_p->cfg_board_SI_setting_ps[ps].lpddr4_dram_vout_voltage_range_setting);
+ printf("\n.cfg_board_SI_setting_ps[%d].reserve2=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].reserve2, ddr_set_t_p->cfg_board_SI_setting_ps[ps].reserve2);
+ printf("\n.cfg_board_SI_setting_ps[%d].vref_ac_permil =0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].vref_ac_permil, ddr_set_t_p->cfg_board_SI_setting_ps[ps].vref_ac_permil);
+ printf("\n.cfg_board_SI_setting_ps[%d].vref_soc_data_permil =0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].vref_soc_data_permil, ddr_set_t_p->cfg_board_SI_setting_ps[ps].vref_soc_data_permil);
+ printf("\n.cfg_board_SI_setting_ps[%d].vref_dram_data_permil=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].vref_dram_data_permil, ddr_set_t_p->cfg_board_SI_setting_ps[ps].vref_dram_data_permil);
+ printf("\n.cfg_board_SI_setting_ps[%d].max_core_timmming_frequency=0x%08x,// %d", ps, ddr_set_t_p->cfg_board_SI_setting_ps[ps].max_core_timmming_frequency, ddr_set_t_p->cfg_board_SI_setting_ps[ps].max_core_timmming_frequency);
+ for (temp_count = 0; temp_count < 2; temp_count++)
+ printf("\n.cfg_board_SI_setting_ps[%d].training_phase_parameter[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_board_SI_setting_ps[ps].training_phase_parameter[temp_count], (uint32_t)ddr_set_t_p->cfg_board_SI_setting_ps[ps].training_phase_parameter[temp_count]);
+ for (temp_count = 0; temp_count < 36; temp_count++)
+ printf("\n.cfg_board_SI_setting_ps[%d].ac_trace_delay_org[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_board_SI_setting_ps[ps].ac_trace_delay_org[temp_count], (uint32_t)ddr_set_t_p->cfg_board_SI_setting_ps[ps].ac_trace_delay_org[temp_count]);
+
+ for (temp_count = 0; temp_count < 36; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].ac_trace_delay[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ac_trace_delay[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].ac_trace_delay[temp_count]);
+ for (temp_count = 0; temp_count < 8; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].write_dqs_delay[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dqs_delay[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dqs_delay[temp_count]);
+ for (temp_count = 0; temp_count < 72; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].write_dq_bit_delay[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dq_bit_delay[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].write_dq_bit_delay[temp_count]);
+ for (temp_count = 0; temp_count < 8; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].read_dqs_gate_delay[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_gate_delay[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_gate_delay[temp_count]);
+ for (temp_count = 0; temp_count < 8; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].read_dqs_delay[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_delay[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dqs_delay[temp_count]);
+ for (temp_count = 0; temp_count < 72; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].read_dq_bit_delay[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dq_bit_delay[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].read_dq_bit_delay[temp_count]);
+ for (temp_count = 0; temp_count < 44; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].soc_bit_vref[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref[temp_count]);
+ for (temp_count = 0; temp_count < 36; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].dram_bit_vref[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dram_bit_vref[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].dram_bit_vref[temp_count]);
+ for (temp_count = 0; temp_count < 16; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].reserve_training_parameter[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].reserve_training_parameter[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].reserve_training_parameter[temp_count]);
+ for (temp_count = 0; temp_count < 44; temp_count++)
+ printf("\n.cfg_ddr_training_delay_ps[%d].soc_bit_vref_dac1[%d]=0x%08x,// %d", ps, temp_count, ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref_dac1[temp_count], ddr_set_t_p->cfg_ddr_training_delay_ps[ps].soc_bit_vref_dac1[temp_count]);
+
+ }
+
+
+ printf("\n},\n");
+ }
+ return 1;
+}
+
+#ifdef USE_FOR_UBOOT_2018
+#include <amlogic/storage.h>
+extern struct storage_t *current;
+
+static int ddr_do_store_ddr_parameter_ops(uint8_t *buffer, uint32_t length)
+{
+ char str[1024] = "";
+
+ if (!current) {
+ sprintf(str, "store init");
+ run_command(str, 0);
+ }
+
+ {
+ printf("\nstore rsv write ddr-parameter 0x%08x 0x%08x\n", (uint32_t)(uint64_t)buffer, length);
+ sprintf(str, "store rsv write ddr-parameter 0x%08x 0x%08x\n", (uint32_t)(uint64_t)buffer, length);
+ run_command(str, 0);
+ }
+
+ return 1;
+}
+#else
+static int ddr_do_store_ddr_parameter_ops(uint8_t *buffer, uint32_t length)
+{
+ extern int store_ddr_parameter_write(uint8_t *buffer, uint32_t length);
+ printf("\nstore ddr_parameter write 0x%08x 0x%08x\n", (uint32_t)(uint64_t)buffer, length);
+ store_ddr_parameter_write((uint8_t *)buffer, length);
+
+
+ return 1;
+}
+#endif
+
+
+int do_ddr_fastboot_config(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ check_base_address();
+ int i = 0;
+ int count = 0;
+ char *endp;
+ unsigned int enable_ddr_fast_boot = 0; // 0 pause 1,resume
+ char *out_sha2;
+
+ printf("\nargc== 0x%08x\n", argc);
+ for (i = 0; i < argc; i++)
+ printf("\nargv[%d]=%s\n", i, argv[i]);
+ if (argc == 1) {
+ printf("\nplease read help\n");
+ } else if (argc > 1) {
+ count = 0;
+ enable_ddr_fast_boot = simple_strtoull_ddr(argv[count + 1], &endp, 0);
+ if (*argv[count + 1] == 0 || *endp != 0)
+ enable_ddr_fast_boot = 0;
+ }
+ if (!enable_ddr_fast_boot)
+ return 1;
+
+ uint32_t dmc_retraining_ctrl = 0;
+ dmc_retraining_ctrl = rd_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address));
+
+ if ((p_ddr_base->ddr_dmc_lpdd4_retraining_address))
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl & (~(1 << 31)));
+ ddr_set_t *ddr_set_t_p = NULL;
+ ddr_set_t_p = (ddr_set_t *)(ddr_set_t_p_arrary);
+ uint32_t ddr_set_add = 0;
+ uint32_t ddr_set_size = 0;
+
+
+ ddr_set_t_c2 *ddr_set_t_p_c2 = NULL;
+ ddr_set_t_p_c2 = (ddr_set_t_c2 *)(ddr_set_t_p_arrary_c2);
+
+ uint32_t write_size = 0;
+
+ if (((p_ddr_base->chip_id >= MESON_CPU_MAJOR_ID_C2) && (p_ddr_base->chip_id <= MESON_CPU_MAJOR_ID_T5D)) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_S4)) {
+ ddr_set_add = (uint32_t)(uint64_t)(ddr_set_t_p_c2);
+ ddr_set_size = sizeof(ddr_set_t_c2);
+ out_sha2 = (char *)ddr_sha_c2.sha2;
+ do_read_c2_ddr_training_data(1, ddr_set_t_p_c2);
+
+ if (enable_ddr_fast_boot == 1)
+ ddr_set_t_p_c2->cfg_board_common_setting.fast_boot[0] = 0xff;
+
+ if (enable_ddr_fast_boot == 2)
+ ddr_set_t_p_c2->cfg_board_common_setting.fast_boot[0] = 0;
+ }
+
+ //do_read_ddr_training_data(1, ddr_set_t_p);
+ if ((p_ddr_base->chip_id >= MESON_CPU_MAJOR_ID_G12A) && (p_ddr_base->chip_id <= MESON_CPU_MAJOR_ID_SC2)) {
+ ddr_set_add = (uint32_t)(uint64_t)(ddr_set_t_p);
+ ddr_set_size = sizeof(ddr_set_t);
+ out_sha2 = (char *)ddr_sha.sha2;
+ dwc_ddrphy_apb_wr(0xd0000, 0x0);
+ do_read_ddr_training_data(1, ddr_set_t_p);
+ char dmc_test_worst_window_rx = 0;
+ char dmc_test_worst_window_tx = 0;
+
+ {
+ dwc_ddrphy_apb_wr((0 << 20) | (0xd << 16) | (0 << 12) | (0x0), 0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+
+ dmc_test_worst_window_tx = dwc_ddrphy_apb_rd((0 << 20) | (1 << 16) | (0 << 12) | (0x0c2));
+ dmc_test_worst_window_rx = dwc_ddrphy_apb_rd((0 << 20) | (1 << 16) | (0 << 12) | (0x0c3));
+ if (dmc_test_worst_window_tx > 30)
+ dmc_test_worst_window_tx = 30;
+ if (dmc_test_worst_window_rx > 30)
+ dmc_test_worst_window_rx = 30;
+ ddr_set_t_p->fast_boot[1] = (((dmc_test_worst_window_tx / 2) << 4)) | (((dmc_test_worst_window_rx / 2)));
+ }
+ if (enable_ddr_fast_boot == 1)
+ ddr_set_t_p->fast_boot[0] = 0xff;
+
+ if (enable_ddr_fast_boot == 2)
+ ddr_set_t_p->fast_boot[0] = 0;
+ }
+ if (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T7) {
+ ddr_set_add = (uint32_t)(uint64_t)(ddr_set_t_p);
+ ddr_set_size = sizeof(ddr_set_t);
+ out_sha2 = (char *)ddr_sha.sha2;
+ dwc_ddrphy_apb_wr(0xd0000, 0x0);
+ do_read_ddr_training_data(1, ddr_set_t_p);
+ char dmc_test_worst_window_rx = 0;
+ char dmc_test_worst_window_tx = 0;
+
+ {
+ dwc_ddrphy_apb_wr((0 << 20) | (0xd << 16) | (0 << 12) | (0x0), 0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+
+ dmc_test_worst_window_tx = dwc_ddrphy_apb_rd((0 << 20) | (1 << 16) | (0 << 12) | (0x0c2));
+ dmc_test_worst_window_rx = dwc_ddrphy_apb_rd((0 << 20) | (1 << 16) | (0 << 12) | (0x0c3));
+ if (dmc_test_worst_window_tx > 30)
+ dmc_test_worst_window_tx = 30;
+ if (dmc_test_worst_window_rx > 30)
+ dmc_test_worst_window_rx = 30;
+ ddr_set_t_p->fast_boot[1] = (((dmc_test_worst_window_tx / 2) << 4)) | (((dmc_test_worst_window_rx / 2)));
+ }
+ if (enable_ddr_fast_boot == 1)
+ ddr_set_t_p->fast_boot[0] = 0xff;
+
+ if (enable_ddr_fast_boot == 2)
+ ddr_set_t_p->fast_boot[0] = 0;
+ }
+
+ write_size = ((ddr_set_size + SHA256_SUM_LEN + MESON_CPU_CHIP_ID_SIZE + 511) / 512) * 512;
+
+ {
+ //printf("&ddr_sha.ddrs : 0x%x\n", (uint32_t)(uint64_t)&ddr_sha.ddrs);
+ printf("&ddr_sha.sha2 : 0x%x\n", (uint32_t)(uint64_t)out_sha2);
+ printf("ddr_set_add : 0x%x sizeof(ddr_set_t):0x%x\n ", (uint32_t)(uint64_t)ddr_set_add, (uint32_t)(uint64_t)ddr_set_size);
+ printf("ddr_set_add_chip_id : 0x%x\n", (uint32_t)(uint64_t)(ddr_set_add + ddr_set_size));
+ sha256_csum_wd_internal((unsigned char *)(uint64_t)ddr_set_add, ddr_set_size, (unsigned char *)out_sha2, 0);
+ printf("print sha\n");
+ ddr_do_store_ddr_parameter_ops((uint8_t *)(unsigned long)(ddr_set_add - SHA256_SUM_LEN), write_size);
+ }
+ return 1;
+}
+#endif
+
+int do_ddr_set_watchdog_value(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ char *endp;
+ int i = 0;
+
+ printf("\nargc== 0x%08x\n", argc);
+ for (i = 0; i < argc; i++)
+ printf("\nargv[%d]=%s\n", i, argv[i]);
+
+ if (argc == 1) {
+ printf("\nplease read help\n");
+ } else if (argc > 1) {
+ {
+ watchdog_time_s = simple_strtoull_ddr(argv[1], &endp, 0);
+ if (*argv[1] == 0 || *endp != 0)
+ watchdog_time_s = 20;
+ }
+ printf("watchdog_time_s==%d\n", watchdog_time_s);
+ }
+
+ return 1;
+}
+
+#define G12_DATA_READ_OFFSET_MAX (0X3F)
+#define G12_DATA_WRITE_OFFSET_MAX (0X3F + 7 * 32)
+
+#define DMC_TEST_WINDOW_INDEX_ATXDLY 1
+#define DMC_TEST_WINDOW_INDEX_TXDQSDLY 2
+#define DMC_TEST_WINDOW_INDEX_RXCLKDLY 3
+#define DMC_TEST_WINDOW_INDEX_TXDQDLY 4
+#define DMC_TEST_WINDOW_INDEX_RXPBDLY 5
+#define DMC_TEST_WINDOW_INDEX_RXENDLY 6
+
+#define DMC_TEST_WINDOW_INDEX_EE_VOLTAGE 0x11
+#define DMC_TEST_WINDOW_INDEX_SOC_VREF 0x12
+#define DMC_TEST_WINDOW_INDEX_DRAM_VREF 0x14
+
+typedef struct training_delay_information {
+ uint16_t ac_delay[10];
+ uint16_t txdqs_delay[16];
+ uint16_t rxdqs_delay[16];
+ uint16_t txdq_delay[72];
+ uint16_t rxdq_delay[72];
+ uint16_t gate_rxdq_delay[72];
+} training_delay_t;
+training_delay_t training_delay_t_p;
+
+uint16_t lcd_bdl_value[72][4]; //org min max status
+#define LCD_BDLR_MIN 0
+#define LCD_BDLR_MAX 1
+#define LCD_BDLR_STATUS 2
+
+//BYTE0-3
+#define TEST_ARG_0_DMC_STICKY_MAGIC 0
+#define TEST_ARG_1_CMD0 1
+#define TEST_ARG_2_STEP 2 // 0 init 1 test ac 2 test tdqs_write
+#define TEST_ARG_3_ALL_TOGHTER 3
+
+//BYTE4-7
+#define TEST_ARG_FREQ_NIBBLE_L 4
+#define TEST_ARG_FREQ_NIBBLE_H 5
+
+//BYTE8-11
+#define TEST_ARG_BOOT_TIMES_L 6
+#define TEST_ARG_BOOT_TIMES_H 7
+
+//BYTE12-15
+#define TEST_ARG_ERROR_FLAG 8 //take 4 byte for kernel test flag
+
+//BYTE16-19
+#define TEST_ARG_CS0_TEST_START_INDEX 12
+#define TEST_ARG_CS0_TEST_SIZE_INDEX 16
+#define TEST_ARG_CS1_TEST_START_INDEX 20
+#define TEST_ARG_CS1_TEST_SIZE_INDEX 24
+
+#define TEST_ARG_WATCHDOG_TIME_SIZE_INDEX 28
+#define TEST_ARG_TEST_INDEX_ENALBE_INDEX 30
+
+#define TEST_ARG_ERROR_FLAG_NULL 0
+#define TEST_ARG_ERROR_FLAG_FAIL 1
+#define TEST_ARG_ERROR_FLAG_PASS 2
+
+#define TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE 32 // 32BYTE
+#define TEST_ARG_NIBBLE_WIDTH_BYTE 3 //3///BYTE
+
+int do_ddr_test_dqs_window_sticky(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ printf("\nEnterddr_test_dqs_window function ddr_test_cmd 0x27 0x1080000 0x800000 0x40000000 0x800000 15 0x6 0 0 0 0 0 0 1/config\n");
+ printf("\nddr_test_cmd 0x27 cs0_test_start cs0_test_size cs1_test_start cs1_test_size ns test_index_enable nibble_mask0 nibble_mask1 nibble_mask2 dram_type channel_mode config_register all_togther--- watchdog should >15s\n");
+ printf("\n ac write_dqs read_dqs can test togther test_index_enable can enable kernel test \n");
+#define DDR_CORSS_TALK_TEST_SIZE 0x20000
+ unsigned int temp_test_error = 0;
+ unsigned int nibble_save_offset = 0;
+ unsigned int nibble_step = 0;
+ unsigned int nibble_max = 16;
+ unsigned int test_index_enable = 0;
+ unsigned int test_index = 0;
+ unsigned int test_index_max = 6;
+ unsigned int reg_value = 0;
+ unsigned int dram_type = 0;
+ unsigned int channel_mode = 0;
+ unsigned int kernel_watchdog_s = 20; //240;
+ unsigned int config_register = 0;
+ unsigned int all_toghter_enable = 0;
+ unsigned int error_flag_reg_add = 0;
+ char *string_print_flag = " uboot-window-loop \n";
+ char *endp;
+ char *buf;
+ buf = "";
+
+ unsigned int cs0_test_start = 0x1080000;
+ unsigned int cs0_test_size = DDR_CORSS_TALK_TEST_SIZE;
+ unsigned int cs1_test_start = 0;
+ unsigned int cs1_test_size = 0;
+ unsigned int enable_kernel_test = 0;
+ if (argc > 1) {
+ cs0_test_start = simple_strtoull_ddr(argv[1], &endp, 16);
+ if (*argv[1] == 0 || *endp != 0)
+ cs0_test_start = 0x1080000;
+ }
+
+ if (argc > 2) {
+ cs0_test_size = simple_strtoull_ddr(argv[2], &endp, 16);
+ if (*argv[2] == 0 || *endp != 0)
+ cs0_test_size = DDR_CORSS_TALK_TEST_SIZE;
+ }
+
+ if (argc > 3) {
+ cs1_test_start = simple_strtoull_ddr(argv[3], &endp, 16);
+ if (*argv[3] == 0 || *endp != 0)
+ cs1_test_start = 0;
+ }
+ if (argc > 4) {
+ cs1_test_size = simple_strtoull_ddr(argv[4], &endp, 16);
+ if (*argv[4] == 0 || *endp != 0)
+ cs1_test_size = 0;
+ }
+
+ unsigned int ddr_test_size = DDR_CORSS_TALK_TEST_SIZE;
+ ddr_test_size = cs0_test_size;
+ if (argc > 5) {
+ watchdog_time_s = simple_strtoull_ddr(argv[5], &endp, 0);
+ if (*argv[5] == 0 || *endp != 0)
+ watchdog_time_s = 20;
+ }
+ printf("watchdog_time_s==%d\n", watchdog_time_s);
+
+ if (argc > 6) {
+ test_index_enable = simple_strtoull_ddr(argv[6], &endp, 0);
+ if (*argv[5] == 0 || *endp != 0)
+ test_index_enable = 0;
+ }
+ printf("test_index_enable==0x%08x\n", test_index_enable);
+ enable_kernel_test = (test_index_enable >> 7) & 1;
+ if (enable_kernel_test)
+ printf("enable kernel window test\n");
+
+ unsigned int nibble_mask[3] = { 0, 0, 0 };
+ if (argc > 7) {
+ nibble_mask[0] = simple_strtoull_ddr(argv[7], &endp, 0);
+ if (*argv[7] == 0 || *endp != 0)
+ nibble_mask[0] = 0;
+ }
+ printf("nibble_mask[0]==0x%08x\n", nibble_mask[0]);
+ if (argc > 8) {
+ nibble_mask[1] = simple_strtoull_ddr(argv[8], &endp, 0);
+ if (*argv[8] == 0 || *endp != 0)
+ nibble_mask[1] = 0;
+ }
+ printf("nibble_mask[1]==0x%08x\n", nibble_mask[1]);
+ if (argc > 9) {
+ nibble_mask[2] = simple_strtoull_ddr(argv[9], &endp, 0);
+ if (*argv[9] == 0 || *endp != 0)
+ nibble_mask[2] = 0;
+ }
+ printf("nibble_mask[2]==0x%08x\n", nibble_mask[2]);
+
+ if (argc > 10) {
+ dram_type = simple_strtoull_ddr(argv[10], &endp, 0);
+ if (*argv[10] == 0 || *endp != 0)
+ dram_type = 0;
+ }
+ if (argc > 11) {
+ channel_mode = simple_strtoull_ddr(argv[11], &endp, 0);
+ if (*argv[11] == 0 || *endp != 0)
+ channel_mode = 0;
+ }
+ if (argc > 12) {
+ config_register = simple_strtoull_ddr(argv[12], &endp, 0);
+ if (*argv[12] == 0 || *endp != 0)
+ config_register = 0;
+ }
+ if (argc > 13) {
+ all_toghter_enable = simple_strtoull_ddr(argv[13], &endp, 0);
+ if (*argv[13] == 0 || *endp != 0)
+ all_toghter_enable = 0;
+ }
+ printf("all_toghter_enable==0x%08x\n", all_toghter_enable);
+
+ if (argc > 14) {
+ error_flag_reg_add = simple_strtoull_ddr(argv[14], &endp, 0);
+ if (*argv[14] == 0 || *endp != 0)
+ error_flag_reg_add = 0;
+ }
+ printf("error_flag_reg_add==0x%08x\n", error_flag_reg_add);
+ printf("\ntest use uboot sticky register\n");
+
+ char str[1024] = "";
+ volatile uint16_t *num_arry = NULL;
+ int i;
+
+ sticky_reg_base_add = (((p_ddr_base->ddr_dmc_sticky0)) & 0xffff);
+ for (i = 0; i < 64 * 4; i++) {
+ num_arry[i] = ddr_rd_8_16bit_on_32reg(sticky_reg_base_add, 8, i);
+ if ((i == 0) || (i == 32) || (i == (32 + 10 * 3)) || (i == (32 + 10 * 3 + 16 * 3)) || (i == (32 + 10 * 3 + 16 * 3 + 16 * 3)))
+ printf("\n numarry[%d]", i);
+ printf(" %d ", num_arry[i]);
+ }
+
+ uint16_t test_left_max_init_value = 32;
+ uint16_t test_right_max_init_value = 32;
+ uint16_t test_boot_times = 0;
+ uint16_t test_ddr_frequency = 0;
+
+ printf("\nTEST_ARG_0_DMC_STICKY_MAGIC==0x%08x\n", num_arry[TEST_ARG_0_DMC_STICKY_MAGIC]);
+ printf("\nTEST_ARG_1_CMD0==0x%08x\n", num_arry[TEST_ARG_1_CMD0]);
+ printf("TEST_ARG_2_STEP==0x%08x\n", num_arry[TEST_ARG_2_STEP]);
+ printf("TEST_ARG_3_ALL_TOGHTER==0x%08x\n", num_arry[TEST_ARG_3_ALL_TOGHTER]);
+ printf("TEST_ARG_FREQ_NIBBLE_L==0x%08x\n", num_arry[TEST_ARG_FREQ_NIBBLE_L]);
+ printf("TEST_ARG_FREQ_NIBBLE_H==0x%08x\n", num_arry[TEST_ARG_FREQ_NIBBLE_H]);
+ printf("TEST_ARG_BOOT_TIMES_L==0x%08x\n", num_arry[TEST_ARG_BOOT_TIMES_L]);
+ printf("TEST_ARG_BOOT_TIMES_H==0x%08x\n", num_arry[TEST_ARG_BOOT_TIMES_H]);
+ printf("TEST_ARG_ERROR_FLAG==0x%08x\n", num_arry[TEST_ARG_ERROR_FLAG]);
+
+ printf("TEST_ARG_FREQ==%dM\n", (num_arry[TEST_ARG_FREQ_NIBBLE_H] << 8) | (num_arry[TEST_ARG_FREQ_NIBBLE_L] << 0));
+ printf("TEST_ARG_BOOT_TIMES==%d\n", (num_arry[TEST_ARG_BOOT_TIMES_H] << 8) | (num_arry[TEST_ARG_BOOT_TIMES_L] << 0));
+ test_boot_times = (num_arry[TEST_ARG_BOOT_TIMES_H] << 8) | (num_arry[TEST_ARG_BOOT_TIMES_L] << 0);
+ test_ddr_frequency = (num_arry[TEST_ARG_FREQ_NIBBLE_H] << 8) | (num_arry[TEST_ARG_FREQ_NIBBLE_L] << 0);
+
+ if ((num_arry[TEST_ARG_0_DMC_STICKY_MAGIC] == (DMC_STICKY_UBOOT_WINDOW_MAGIC_1 & 0xff))
+ && (num_arry[TEST_ARG_1_CMD0] == (DMC_STICKY_UBOOT_WINDOW_MAGIC_1 & 0xff))) { //for check magic number make sume enter test command
+ test_boot_times++;
+ num_arry[TEST_ARG_BOOT_TIMES_L] = test_boot_times & 0xff;
+ num_arry[TEST_ARG_BOOT_TIMES_H] = (test_boot_times >> 8) & 0xff;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_BOOT_TIMES_L, num_arry[TEST_ARG_BOOT_TIMES_L]);
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_BOOT_TIMES_H, num_arry[TEST_ARG_BOOT_TIMES_H]);
+
+ if (test_ddr_frequency != global_ddr_clk) { //
+ printf("running ddr freq==%d,but test freq is%d,will reboot use d2pll \n", global_ddr_clk, test_ddr_frequency);
+ sprintf(str, "d2pll %d", test_ddr_frequency);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+
+ while (1) {
+ }
+ }
+ } else {
+ test_boot_times = 0;
+ num_arry[TEST_ARG_BOOT_TIMES_L] = test_boot_times & 0xff;
+ num_arry[TEST_ARG_BOOT_TIMES_H] = (test_boot_times >> 8) & 0xff;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_BOOT_TIMES_L, num_arry[TEST_ARG_BOOT_TIMES_L]);
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_BOOT_TIMES_H, num_arry[TEST_ARG_BOOT_TIMES_H]);
+ num_arry[TEST_ARG_2_STEP] = 0;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]);
+ }
+ printf("test_sticky is not magic nummber,boot times==%d\n", test_boot_times);
+
+ {
+ wr_reg((sticky_reg_base_add + TEST_ARG_CS0_TEST_START_INDEX), cs0_test_start);
+ wr_reg((sticky_reg_base_add + TEST_ARG_CS0_TEST_SIZE_INDEX), cs0_test_size);
+ wr_reg((sticky_reg_base_add + TEST_ARG_CS1_TEST_START_INDEX), cs1_test_start);
+ wr_reg((sticky_reg_base_add + TEST_ARG_CS1_TEST_SIZE_INDEX), cs1_test_size);
+ {
+ num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX] = watchdog_time_s & 0xff;
+ num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX + 1] = (watchdog_time_s >> 8) & 0xff;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_WATCHDOG_TIME_SIZE_INDEX, num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX]);
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, (TEST_ARG_WATCHDOG_TIME_SIZE_INDEX + 1), num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX + 1]);
+ }
+ num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX] = test_index_enable;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_TEST_INDEX_ENALBE_INDEX, num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX]);
+ if (config_register == 1) {
+ num_arry[TEST_ARG_2_STEP] = 0;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]);
+ }
+ num_arry[TEST_ARG_3_ALL_TOGHTER] = all_toghter_enable;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_3_ALL_TOGHTER, num_arry[TEST_ARG_3_ALL_TOGHTER]);
+ }
+
+ if ((num_arry[TEST_ARG_2_STEP]) == 0) {
+ {
+ num_arry[TEST_ARG_0_DMC_STICKY_MAGIC] = DMC_STICKY_UBOOT_WINDOW_MAGIC_1;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_0_DMC_STICKY_MAGIC, num_arry[TEST_ARG_0_DMC_STICKY_MAGIC]);
+ num_arry[TEST_ARG_1_CMD0] = DMC_STICKY_UBOOT_WINDOW_MAGIC_1;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_1_CMD0, num_arry[TEST_ARG_1_CMD0]);
+ num_arry[TEST_ARG_2_STEP] = 1;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]);
+ {
+ test_boot_times = 0;
+ num_arry[TEST_ARG_BOOT_TIMES_L] = test_boot_times & 0xff;
+ num_arry[TEST_ARG_BOOT_TIMES_H] = (test_boot_times >> 8) & 0xff;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_BOOT_TIMES_L, num_arry[TEST_ARG_BOOT_TIMES_L]);
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_BOOT_TIMES_H, num_arry[TEST_ARG_BOOT_TIMES_H]);
+ }
+ {
+ test_ddr_frequency = global_ddr_clk;
+ num_arry[TEST_ARG_FREQ_NIBBLE_L] = test_ddr_frequency & 0xff;
+ num_arry[TEST_ARG_FREQ_NIBBLE_H] = (test_ddr_frequency >> 8) & 0xff;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_FREQ_NIBBLE_L, num_arry[TEST_ARG_FREQ_NIBBLE_L]);
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_FREQ_NIBBLE_H, num_arry[TEST_ARG_FREQ_NIBBLE_H]);
+ }
+
+ num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_NULL;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_ERROR_FLAG, num_arry[TEST_ARG_ERROR_FLAG]);
+ }
+
+
+ for (nibble_step = 0; nibble_step < 72; nibble_step++) {
+ {
+ test_left_max_init_value = 16;
+ test_right_max_init_value = 16;
+ if (nibble_step < 10) {
+ test_left_max_init_value = 32;
+ test_right_max_init_value = 32;
+ }
+ num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + (nibble_step * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN] = test_left_max_init_value;
+ num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + (nibble_step * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX] = test_right_max_init_value;
+ num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + (nibble_step * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS] = 0; //0
+ }
+
+ {
+ if (nibble_step < 32) {
+ if (((nibble_mask[0]) >> nibble_step) & 1)
+ num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + nibble_step * TEST_ARG_NIBBLE_WIDTH_BYTE + LCD_BDLR_STATUS] = 4;
+ } else if (nibble_step < 64) {
+ if (((nibble_mask[1]) >> (nibble_step - 32)) & 1)
+ num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + nibble_step * TEST_ARG_NIBBLE_WIDTH_BYTE + LCD_BDLR_STATUS] = 4;
+ } else if (nibble_step < 96) {
+ if (((nibble_mask[2]) >> (nibble_step - 64)) & 1)
+ num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + nibble_step * TEST_ARG_NIBBLE_WIDTH_BYTE + LCD_BDLR_STATUS] = 4;
+ }
+ if (all_toghter_enable) {
+ if ((nibble_step == 0) || (nibble_step == 10) || (nibble_step == (10 + 16)))
+ num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + nibble_step * TEST_ARG_NIBBLE_WIDTH_BYTE + LCD_BDLR_STATUS] = 0;
+ else
+ num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + nibble_step * TEST_ARG_NIBBLE_WIDTH_BYTE + LCD_BDLR_STATUS] = 4;
+ }
+ }
+ }
+
+ {
+ for (i = TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE; i < 72 * TEST_ARG_NIBBLE_WIDTH_BYTE; i++)
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, i, num_arry[i]);
+
+ num_arry[TEST_ARG_2_STEP] = 1;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]);
+ }
+ }
+
+ if (all_toghter_enable) {
+ for (nibble_step = 0; nibble_step < 72; nibble_step++) {
+ if ((nibble_step == 0) || (nibble_step == 10) || (nibble_step == (10 + 16))) {
+ } else {
+ num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + nibble_step * TEST_ARG_NIBBLE_WIDTH_BYTE + LCD_BDLR_STATUS] = 4;
+ }
+ }
+ }
+
+ if (config_register == 1) {
+ num_arry[TEST_ARG_2_STEP] = 0;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]);
+ }
+
+ if ((num_arry[TEST_ARG_2_STEP])) {
+ for (test_index = num_arry[TEST_ARG_2_STEP]; test_index < test_index_max; test_index++) {
+ printf("\ntest_index=%d\n", test_index);
+ if ((((test_index_enable) >> (test_index - 1)) & 1) == 0) {
+ num_arry[TEST_ARG_2_STEP] = ((num_arry[TEST_ARG_2_STEP]) + 1); //why can not use ++
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]);
+ continue;
+ }
+ {
+ if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
+ nibble_save_offset = 0;
+ nibble_max = 10;
+ nibble_mask[0] = 0x30;
+ if ((dram_type == CONFIG_DDR_TYPE_LPDDR3))
+ nibble_mask[0] = 0x3e3;
+ if ((dram_type == CONFIG_DDR_TYPE_LPDDR4)) {
+ nibble_mask[0] = 0x273;
+ if ((channel_mode == CONFIG_DDR0_32BIT_RANK01_CH0))
+ nibble_mask[0] = 0x3f3;
+ }
+ test_left_max_init_value = 64;
+ test_right_max_init_value = 64;
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
+ nibble_save_offset = 10;
+ nibble_max = 16;
+ if ((cs1_test_size == 0))
+ nibble_mask[0] = 0xff00;
+ test_left_max_init_value = 16;
+ test_right_max_init_value = 16;
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) {
+ nibble_save_offset = (10) + (16);
+ if ((cs1_test_size == 0))
+ nibble_mask[0] = 0xff00;
+ nibble_max = 16;
+ test_left_max_init_value = 16;
+ test_right_max_init_value = 16;
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) {
+ nibble_save_offset = 0;
+ nibble_max = 72;
+ if ((cs1_test_size == 0)) {
+ nibble_mask[1] = 0xfffffff0;
+ nibble_mask[2] = 0xffffffff;
+ }
+ test_left_max_init_value = 16;
+ test_right_max_init_value = 16;
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
+ nibble_save_offset = 0;
+ nibble_max = 72;
+ if ((cs1_test_size == 0)) {
+ nibble_mask[1] = 0xfffffff0;
+ nibble_mask[2] = 0xffffffff;
+ }
+
+ test_left_max_init_value = 64;
+ test_right_max_init_value = 64;
+ }
+ for ((nibble_step = 0); (nibble_step < nibble_max); (nibble_step++)) {
+ if (nibble_step < 32) {
+ if (((nibble_mask[0]) >> nibble_step) & 1)
+ num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + (nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE + LCD_BDLR_STATUS] = 4;
+ } else if (nibble_step < 64) {
+ if (((nibble_mask[1]) >> (nibble_step - 32)) & 1)
+ num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + (nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE + LCD_BDLR_STATUS] = 4;
+ } else if (nibble_step < 96) {
+ if (((nibble_mask[2]) >> (nibble_step - 64)) & 1)
+ num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + (nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE + LCD_BDLR_STATUS] = 4;
+ }
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS),
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]);
+ }
+ }
+
+ {
+ for ((nibble_step = 0); (nibble_step < nibble_max); (nibble_step++)) {
+ if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 4)
+ continue;
+ printf("nibble_step ==%d\n", nibble_step);
+
+ if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
+ if (nibble_step % 2) {
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN),
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step - 1 + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)]);
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX),
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step - 1 + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)]);
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS),
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step - 1 + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]);
+ continue;
+ }
+ }
+ test_start_addr = cs0_test_start;
+ ddr_test_size = cs0_test_size;
+ if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
+ test_start_addr = cs0_test_start;
+ ddr_test_size = cs0_test_size;
+ }
+
+ if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
+ if (nibble_step > 7) {
+ test_start_addr = cs1_test_start;
+ ddr_test_size = cs1_test_size;
+ }
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) {
+ if (nibble_step > 7) {
+ test_start_addr = cs1_test_start;
+ ddr_test_size = cs1_test_size;
+ }
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) {
+ if (nibble_step > 35) {
+ test_start_addr = cs1_test_start;
+ ddr_test_size = cs1_test_size;
+ }
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
+ if (nibble_step > 35) {
+ test_start_addr = cs1_test_start;
+ ddr_test_size = cs1_test_size;
+ }
+ }
+ {
+ if (nibble_step < 32) {
+ nibble_mask[0] = ((0xffffffff) & (~(1 << nibble_step)));
+ nibble_mask[1] = ((0xffffffff));
+ nibble_mask[2] = ((0xffffffff));
+ } else if (nibble_step < 64) {
+ nibble_mask[0] = ((0xffffffff));
+ nibble_mask[1] = ((0xffffffff) & (~(1 << (nibble_step - 32))));
+ nibble_mask[2] = ((0xffffffff));
+ } else if (nibble_step < 96) {
+ nibble_mask[0] = ((0xffffffff));
+ nibble_mask[1] = ((0xffffffff));
+ nibble_mask[2] = ((0xffffffff) & (~(1 << (nibble_step - 64))));
+ }
+ }
+ if (all_toghter_enable) {
+ if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
+ nibble_save_offset = 0;
+ nibble_max = 10;
+ nibble_mask[0] = 0x30;
+ nibble_mask[1] = 0;
+ nibble_mask[2] = 0;
+ if ((dram_type == CONFIG_DDR_TYPE_LPDDR3))
+ nibble_mask[0] = 0x3e3;
+ if ((dram_type == CONFIG_DDR_TYPE_LPDDR4)) {
+ nibble_mask[0] = 0x273;
+ if ((channel_mode == CONFIG_DDR0_32BIT_RANK01_CH0))
+ nibble_mask[0] = 0x3f3;
+ }
+ } else {
+ nibble_mask[0] = 0;
+ nibble_mask[1] = 0;
+ nibble_mask[2] = 0;
+ }
+ }
+
+ ddr_test_watchdog_enable(watchdog_time_s); //s
+ printf("\nenable %ds watchdog \n", watchdog_time_s);
+ if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 0xffff)
+ || (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 0)
+ || (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 1)) {
+ printf("\nnibble_step ==%d ", nibble_step);
+ if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 0xffff)
+ || (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 0)) {
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] = 1;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS),
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]);
+
+ if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)] == 0) {
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] = 2;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS),
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]);
+ run_command("reset", 0);
+ }
+ {
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)] =
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)] - 1;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN),
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)]);
+ }
+
+ {
+ num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_FAIL;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ TEST_ARG_ERROR_FLAG,
+ num_arry[TEST_ARG_ERROR_FLAG]);
+ }
+
+ sprintf(str, "ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d", test_index, nibble_mask[0], nibble_mask[1], nibble_mask[2], DDR_PARAMETER_LEFT,
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)]);
+ printf("\nstr=%s\n", str);
+ ddr_test_watchdog_clear();
+ run_command(str, 0);
+
+ temp_test_error = ddr_test_s_cross_talk_pattern(ddr_test_size);
+ if (all_toghter_enable && cs1_test_size) {
+ test_start_addr = cs1_test_start;
+ ddr_test_size = cs1_test_size;
+ temp_test_error = temp_test_error + ddr_test_s_cross_talk_pattern(ddr_test_size);
+ test_start_addr = cs0_test_start;
+ ddr_test_size = cs0_test_size;
+ }
+ if (temp_test_error) {
+ run_command("reset", 0);
+ } else {
+ if (!enable_kernel_test) {
+ num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_PASS;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ TEST_ARG_ERROR_FLAG,
+ num_arry[TEST_ARG_ERROR_FLAG]);
+ run_command("reset", 0);
+ } else {
+ ddr_test_watchdog_enable(kernel_watchdog_s); //s
+ printf("\nenable %ds watchdog \n", kernel_watchdog_s);
+ run_command("run storeboot", 0);
+ }
+ }
+ } else if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 1) { //go on find left edge
+ if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)] == 0) {
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] = 2;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS),
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]);
+ run_command("reset", 0);
+ }
+
+ if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_PASS) {
+ {
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] = 2;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS),
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]);
+ }
+ {
+ num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_NULL;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ TEST_ARG_ERROR_FLAG,
+ num_arry[TEST_ARG_ERROR_FLAG]);
+ }
+ run_command("reset", 0);
+ }
+ if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_FAIL) {
+ {
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)] =
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)] - 1;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN),
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)]);
+ }
+ {
+ num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_FAIL;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ TEST_ARG_ERROR_FLAG,
+ num_arry[TEST_ARG_ERROR_FLAG]);
+ }
+ sprintf(buf, "0x%08x", (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)]));
+ printf("%s", buf);
+ sprintf(str, "ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d", test_index, nibble_mask[0], nibble_mask[1], nibble_mask[2], DDR_PARAMETER_LEFT,
+ (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)]));
+ printf("\nstr=%s\n", str);
+ ddr_test_watchdog_clear();
+ run_command(str, 0);
+ temp_test_error = ddr_test_s_cross_talk_pattern(ddr_test_size);
+ if (all_toghter_enable && cs1_test_size) {
+ test_start_addr = cs1_test_start;
+ ddr_test_size = cs1_test_size;
+ temp_test_error = temp_test_error + ddr_test_s_cross_talk_pattern(ddr_test_size);
+ test_start_addr = cs0_test_start;
+ ddr_test_size = cs0_test_size;
+ }
+ if (temp_test_error) {
+ run_command("reset", 0);
+ } else {
+ if (!enable_kernel_test) {
+ num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_PASS;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ TEST_ARG_ERROR_FLAG,
+ num_arry[TEST_ARG_ERROR_FLAG]);
+ run_command("reset", 0);
+ } else {
+ ddr_test_watchdog_enable(kernel_watchdog_s); //s
+ printf("\nenable %ds watchdog \n", kernel_watchdog_s);
+ run_command("run storeboot", 0);
+ }
+ }
+ }
+ }
+ }
+
+ if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 2)
+ || (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 3)) {
+ printf("\nnibble_step ==%d ", nibble_step);
+
+ if ((num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 2)
+ || (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 2)) {
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] = 3;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS),
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]);
+
+ if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)] == 0) {
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] = 4;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS),
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]);
+ run_command("reset", 0);
+ }
+ {
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)] =
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)] - 1;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX),
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)]);
+ }
+
+ {
+ num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_FAIL;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ TEST_ARG_ERROR_FLAG,
+ num_arry[TEST_ARG_ERROR_FLAG]);
+ }
+ sprintf(str, "ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d", test_index, nibble_mask[0], nibble_mask[1], nibble_mask[2], DDR_PARAMETER_RIGHT,
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)]);
+ printf("\nstr=%s\n", str);
+ ddr_test_watchdog_clear();
+ run_command(str, 0);
+ temp_test_error = ddr_test_s_cross_talk_pattern(ddr_test_size);
+ if (all_toghter_enable && cs1_test_size) {
+ test_start_addr = cs1_test_start;
+ ddr_test_size = cs1_test_size;
+ temp_test_error = temp_test_error + ddr_test_s_cross_talk_pattern(ddr_test_size);
+ test_start_addr = cs0_test_start;
+ ddr_test_size = cs0_test_size;
+ }
+ if (temp_test_error) {
+ run_command("reset", 0);
+ } else {
+ if (!enable_kernel_test) {
+ num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_PASS;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ TEST_ARG_ERROR_FLAG,
+ num_arry[TEST_ARG_ERROR_FLAG]);
+ run_command("reset", 0);
+ } else {
+ ddr_test_watchdog_enable(kernel_watchdog_s); //s
+ printf("\nenable %ds watchdog \n", kernel_watchdog_s);
+ run_command("run storeboot", 0);
+ }
+ }
+ } else if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] == 3) { //go on find left edge
+ if (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)] == 0) {
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] = 4;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS),
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]);
+ run_command("reset", 0);
+ }
+
+ if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_PASS) {
+ {
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)] = 4;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS),
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_STATUS)]);
+ }
+ {
+ num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_NULL;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ TEST_ARG_ERROR_FLAG,
+ num_arry[TEST_ARG_ERROR_FLAG]);
+ }
+ run_command("reset", 0);
+ }
+ if ((num_arry[TEST_ARG_ERROR_FLAG]) == TEST_ARG_ERROR_FLAG_FAIL) {
+ {
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)] =
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)] - 1;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ (TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX),
+ num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)]);
+ }
+ {
+ num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_FAIL;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ TEST_ARG_ERROR_FLAG,
+ num_arry[TEST_ARG_ERROR_FLAG]);
+ }
+ sprintf(buf, "0x%08x", (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)]));
+ printf("%s", buf);
+ sprintf(str, "ddr_g12_offset_data %d 0x%08x 0x%08x 0x%08x %d %d", test_index, nibble_mask[0], nibble_mask[1], nibble_mask[2], DDR_PARAMETER_RIGHT,
+ (num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)]));
+ printf("\nstr=%s\n", str);
+ ddr_test_watchdog_clear();
+ run_command(str, 0);
+ temp_test_error = ddr_test_s_cross_talk_pattern(ddr_test_size);
+ if (all_toghter_enable && cs1_test_size) {
+ test_start_addr = cs1_test_start;
+ ddr_test_size = cs1_test_size;
+ temp_test_error = temp_test_error + ddr_test_s_cross_talk_pattern(ddr_test_size);
+ test_start_addr = cs0_test_start;
+ ddr_test_size = cs0_test_size;
+ }
+ if (temp_test_error) {
+ run_command("reset", 0);
+ } else {
+ if (!enable_kernel_test) {
+ num_arry[TEST_ARG_ERROR_FLAG] = TEST_ARG_ERROR_FLAG_PASS;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8,
+ TEST_ARG_ERROR_FLAG,
+ num_arry[TEST_ARG_ERROR_FLAG]);
+ run_command("reset", 0);
+ } else {
+ ddr_test_watchdog_enable(kernel_watchdog_s); //s
+ printf("\nenable %ds watchdog \n", kernel_watchdog_s);
+ run_command("run storeboot", 0);
+ }
+ }
+ }
+ }
+ }
+
+ ddr_test_watchdog_disable(); //s
+ {
+ printf("close watchdog\n");
+ }
+ }
+
+ printf("11num_arry[TEST_ARG_2_STEP]==%d\n", num_arry[TEST_ARG_2_STEP]);
+ num_arry[TEST_ARG_2_STEP] = (num_arry[TEST_ARG_2_STEP]) + 1;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]);
+ printf("22num_arry[TEST_ARG_2_STEP]==%d\n", num_arry[TEST_ARG_2_STEP]);
+
+ ddr_test_watchdog_disable(); //s
+ printf("close watchdog\n");
+ {
+ unsigned int ui_1_32_100step = 0;
+ unsigned int bdlr_100step = 0;
+ ui_1_32_100step = (1000000 * 100 / (global_ddr_clk * 2 * 32));
+ bdlr_100step = get_bdlr_100step(global_ddr_clk);
+
+ printf("\nacmdlr=0x%08x-->dec %d,ddr clk==%d,bdlr_100step=%d ps,ui_1_32_100step=%d ps,\n", 0, 0, global_ddr_clk,
+ bdlr_100step, ui_1_32_100step);
+
+ printf("\n test result index==");
+ printf("%08d", test_index);
+
+ if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
+ printf(" ac window:");
+ printf(" step_size ps==");
+ printf("%08d", ui_1_32_100step);
+ printf("/100 ps ");
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
+ printf(" txdqs window:");
+ printf(" step_size ps==");
+ printf("%08d", ui_1_32_100step);
+ printf("/100 ps ");
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) {
+ printf(" rx_clk_window:");
+ printf(" step_size ps==");
+ printf("%08d", ui_1_32_100step);
+ printf("/100 ps ");
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) {
+ printf(" tx_bit_dq_window:");
+ printf(" step_size ps==");
+ printf("%08d", ui_1_32_100step);
+ printf("/100 ps ");
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
+ printf(" rx_bit_dq_window");
+ printf(" step_size ps==");
+ printf("%08d", bdlr_100step); //480ps
+ printf("/100 ps ");
+ }
+ printf("ddr clk frequency : ");
+ printf("%08d", (global_ddr_clk));
+ printf("Mhz ");
+ printf(string_print_flag);
+ printf("index org min max left right dec vref_range vref_count");
+ printf(string_print_flag);
+
+ char delay_left_margin = 0;
+ char delay_right_margin = 0;
+ if (all_toghter_enable == 1)
+ nibble_max = 1;
+ for (nibble_step = 0; nibble_step < nibble_max; nibble_step++) {
+ printf("%08d", nibble_step);
+ printf(" ");
+ printf("%08d", 0);
+ {
+ printf(" ");
+ printf("%08d", 0 //num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_MIN]
+ );
+ }
+ {
+ printf(" ");
+ printf("%08d", 0 //num_arry[TEST_ARG_NIBBLE_SAVE_OFFSET+nibble_step*TEST_ARG_NIBBLE_WIDTH+LCD_BDLR_MAX]
+ );
+ }
+
+ delay_left_margin = num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MIN)];
+ delay_right_margin = num_arry[(TEST_ARG_NIBBLE_SAVE_OFFSET_BYTE + ((nibble_step + nibble_save_offset) * TEST_ARG_NIBBLE_WIDTH_BYTE) + LCD_BDLR_MAX)];
+ printf(" ");
+ printf("%08d", delay_left_margin);
+
+ printf(" ");
+ printf("%08d", delay_right_margin);
+ printf(" ");
+ printf("%08d", 0);
+ printf(" ");
+ printf("%08d", 0);
+ printf(" 2d-eye"); //p_dev->cur_type
+ printf(" dramtype ");
+ printf("%08d", 0);
+ printf(" ");
+ printf("%08d", (global_ddr_clk));
+ printf(" M bdl ");
+ printf("%08d", bdlr_100step); //480ps
+ printf(" /100 ps ");
+ printf("1/32step== ");
+ printf("%08d", ui_1_32_100step);
+ printf(" /100 ps ");
+ printf(string_print_flag);
+ }
+ }
+ }
+ }
+ }
+
+ if (config_register == 1) {
+ if (num_arry[TEST_ARG_2_STEP] == 0) {
+ num_arry[TEST_ARG_2_STEP] = 1;
+ ddr_wr_8_16bit_on_32reg(sticky_reg_base_add, 8, TEST_ARG_2_STEP, num_arry[TEST_ARG_2_STEP]);
+ }
+ }
+
+ if ((enable_kernel_test) && (num_arry[TEST_ARG_2_STEP] > 1))
+ run_command("run storeboot", 0);
+ return reg_value;
+}
+
+#define ACX_MAX 0x80
+
+#if (CONFIG_DDR_PHY >= P_DDR_PHY_G12)
+#define G12_DATA_READ_OFFSET_MAX (0X3F)
+#define G12_DATA_WRITE_OFFSET_MAX (0X3F + 7 * 32)
+
+#define DMC_TEST_WINDOW_INDEX_ATXDLY 1
+#define DMC_TEST_WINDOW_INDEX_TXDQSDLY 2
+#define DMC_TEST_WINDOW_INDEX_RXCLKDLY 3
+#define DMC_TEST_WINDOW_INDEX_TXDQDLY 4
+#define DMC_TEST_WINDOW_INDEX_RXPBDLY 5
+#define DMC_TEST_WINDOW_INDEX_RXENDLY 6
+
+#define DMC_TEST_WINDOW_INDEX_EE_VOLTAGE 0x11
+#define DMC_TEST_WINDOW_INDEX_SOC_VREF 0x12
+#define DMC_TEST_WINDOW_INDEX_DRAM_VREF 0x14
+
+uint32_t ddr_cacl_phy_delay_all_step(char test_index, uint32_t value)
+{
+ uint32_t result = 0;
+
+ if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY)
+ result = (32 * (((value >> 6) & 1) + ((value >> 5) & 1))) + (value & 0x1f);
+ //use for txdqdly register ,because of this register bit 5 is no use jiaxing 20180814
+ else if ((test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) || (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY))
+ result = (32 * (((value >> 6) & 7))) + (value & 0x3f);
+ else //other register bit5 is effect ,but can not modify coarse delay why ? jiaxing 20180814
+ result = value & 0x3f;
+ if (test_index >= DMC_TEST_WINDOW_INDEX_EE_VOLTAGE)
+ result = value;
+ return result;
+}
+
+uint32_t ddr_cacl_phy_over_ride_back_reg(char test_index, uint32_t value)
+{
+ uint32_t result = 0;
+
+ if ((test_index == DMC_TEST_WINDOW_INDEX_ATXDLY)) {
+ if (value < 64)
+ result = ((value / 32) << 6) + value % 32;
+ else
+ result = (3 << 5) + (value % 32);
+ } else if ((test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY)
+ || (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY)
+ || (test_index == DMC_TEST_WINDOW_INDEX_RXENDLY)) {
+ result = value % 64;
+ if ((test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) || (test_index == DMC_TEST_WINDOW_INDEX_RXENDLY)) //use for txdqdly register ,because of this register bit 5 is no use jiaxing 20180814
+ result = ((value / 32) << 6) + value % 32;
+ } else if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
+ result = value & 0x3f;
+ } else if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
+ result = ((value / 32) << 6) + value % 32;
+ } else if (test_index > DMC_TEST_WINDOW_INDEX_RXPBDLY) {
+ result = value;
+ }
+
+ return result;
+}
+
+unsigned int do_ddr_g12_read_write_ddr_add_window_lcdlr(unsigned int rank_index, unsigned int add_index, unsigned int lcdlr_value, unsigned int read_write_flag)
+{
+ dwc_ddrphy_apb_wr(0xd0000, 0); //mw fe1a0000 0
+ if (read_write_flag == DDR_PARAMETER_READ)
+ lcdlr_value = dwc_ddrphy_apb_rd((0 << 20) | (0 << 16) | (add_index << 12) | (0x80));
+ if (read_write_flag == DDR_PARAMETER_WRITE)
+ dwc_ddrphy_apb_wr(((0 << 20) | (0 << 16) | (add_index << 12) | (0x80)), lcdlr_value);
+
+ printf("rank_index %d add_index %d lcdlr== %d \n", rank_index, add_index, lcdlr_value);
+ return lcdlr_value;
+}
+
+void dwc_window_reg_after_training_update_increas_dq(char over_ride_index, uint32_t over_ride_sub_index, uint32_t over_ride_increase_decrease,
+ uint32_t step_value)
+{
+ uint32_t delay_old_value = 0;
+ uint32_t delay_reg_value = 0;
+
+ uint64_t reg_add = 0;
+
+ if (!over_ride_index)
+ return;
+
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) {
+ reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (0xc0 + ((over_ride_sub_index % 9) << 8) + (over_ride_sub_index / 36)));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+ delay_reg_value = ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
+ if (over_ride_increase_decrease == 0) {
+ delay_reg_value = delay_reg_value + step_value;
+ if (delay_reg_value > 255)
+ delay_reg_value = 255;
+ }
+ if (over_ride_increase_decrease != 0) {
+ if (delay_reg_value > step_value)
+ delay_reg_value = delay_reg_value - step_value;
+ else
+ delay_reg_value = 0;
+ }
+ delay_reg_value = ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
+ dwc_ddrphy_apb_wr(reg_add, delay_reg_value);
+ }
+
+ printf("reg_add %08x old_value %08x update_to %08x dec %d to %d \n", ((unsigned int)(((reg_add) << 1) + (p_ddr_base->ddr_phy_base_address))),
+ delay_old_value, dwc_ddrphy_apb_rd(reg_add), ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value),
+ (unsigned int)ddr_cacl_phy_delay_all_step(over_ride_index, dwc_ddrphy_apb_rd(reg_add)));
+}
+
+void dwc_window_reg_after_training_update(char over_ride_index, uint32_t over_ride_sub_index, uint32_t over_ride_value)
+{
+ uint32_t delay_old_value = 0;
+ uint32_t delay_reg_value = 0;
+ uint64_t reg_add = 0;
+
+ if (!over_ride_index)
+ return;
+ delay_reg_value = ddr_cacl_phy_over_ride_back_reg(over_ride_index, over_ride_value);
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
+ reg_add = ((0 << 20) | (0 << 16) | (over_ride_sub_index << 12) | (0x80));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+ dwc_ddrphy_apb_wr(reg_add, delay_reg_value);
+ }
+
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
+ reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 8) >> 1) << 12) | (0xd0 + (over_ride_sub_index / 8) + ((over_ride_sub_index % 2) << 8)));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+
+ dwc_ddrphy_apb_wr(reg_add, delay_reg_value);
+ }
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) {
+ reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 8) >> 1) << 12) | (0x8c + (over_ride_sub_index / 8) + ((over_ride_sub_index % 2) << 8)));
+ delay_old_value = dwc_ddrphy_apb_rd((0 << 20) | (1 << 16) | (((over_ride_sub_index % 8) >> 1) << 12) | (0x8c + (over_ride_sub_index / 8) + ((over_ride_sub_index % 2) << 8)));
+ dwc_ddrphy_apb_wr(reg_add, delay_reg_value);
+ dwc_ddrphy_apb_wr(reg_add + 4, delay_reg_value);
+ }
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) {
+ reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (0xc0 + ((over_ride_sub_index % 9) << 8) + (over_ride_sub_index / 36)));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+ dwc_ddrphy_apb_wr(reg_add, delay_reg_value);
+ }
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
+ reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (0x68 + ((over_ride_sub_index % 9) << 8) + (over_ride_sub_index / 36)));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+ dwc_ddrphy_apb_wr(reg_add, delay_reg_value);
+ }
+
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXENDLY) {
+ reg_add = ((0 << 20) | (1 << 16) | ((over_ride_sub_index % 8) << 12) | (0x80 + (over_ride_sub_index / 8)));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+ dwc_ddrphy_apb_wr(reg_add, delay_reg_value);
+ }
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF)
+ dwc_ddrphy_apb_wr((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (((over_ride_sub_index % 36) % 9) << 8) | (0x40), over_ride_value);
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF_DAC1)
+ dwc_ddrphy_apb_wr((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (((over_ride_sub_index % 36) % 9) << 8) | (0x30), over_ride_value);
+
+ printf("reg_add %08x old_value %08x update_to %08x dec %d to %d \n", ((unsigned int)(((reg_add) << 1) + (p_ddr_base->ddr_phy_base_address))),
+ delay_old_value, dwc_ddrphy_apb_rd(reg_add), ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value),
+ (unsigned int)ddr_cacl_phy_delay_all_step(over_ride_index, delay_reg_value));
+}
+
+void dwc_window_reg_after_training_update_increas_sub(char over_ride_index, uint32_t over_ride_sub_index, uint32_t over_ride_increase_decrease,
+ uint32_t step_value)
+{
+ uint32_t delay_old_value = 0;
+ uint32_t delay_reg_value = 0;
+
+ uint64_t reg_add = 0;
+
+ if (!over_ride_index)
+ return;
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
+ reg_add = ((0 << 20) | (0 << 16) | (over_ride_sub_index << 12) | (0x80));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+ delay_reg_value = ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
+ if (over_ride_increase_decrease == 0) {
+ delay_reg_value = delay_reg_value + step_value;
+ if (delay_reg_value > 95)
+ delay_reg_value = 95;
+ }
+ if (over_ride_increase_decrease != 0) {
+ if (delay_reg_value >= step_value)
+ delay_reg_value = delay_reg_value - step_value;
+ else
+ delay_reg_value = 0;
+ }
+ delay_reg_value = ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
+ dwc_ddrphy_apb_wr((reg_add), delay_reg_value);
+ }
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
+ reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 8) >> 1) << 12) | (0xd0 + (over_ride_sub_index / 8) + ((over_ride_sub_index % 2) << 8)));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+
+ //some case will happen tdqs from 0x1f to 0x0 or 0x0 to 0x1f ,then fast boot write back will happen error ,because
+ // fast boot write back will re-calculate coarse UI,then result dq phase fail.
+ if ((over_ride_sub_index % 2) == 0) {
+ char temp_test_index = DMC_TEST_WINDOW_INDEX_TXDQDLY;
+ char temp_count = 0;
+ {
+ for (temp_count = 0; temp_count < 9; temp_count++)
+ dwc_window_reg_after_training_update_increas_dq(temp_test_index
+ , (((over_ride_sub_index) >> 1) * 9 + temp_count), (!over_ride_increase_decrease), step_value);
+ }
+ }
+ }
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) {
+ reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (0xc0 + ((over_ride_sub_index % 9) << 8) + (over_ride_sub_index / 36)));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+ delay_reg_value = ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
+ if (over_ride_increase_decrease == 0) {
+ delay_reg_value = delay_reg_value + step_value;
+ if (delay_reg_value > 255)
+ delay_reg_value = 255;
+ }
+ if (over_ride_increase_decrease != 0) {
+ if (delay_reg_value > step_value)
+ delay_reg_value = delay_reg_value - step_value;
+ else
+ delay_reg_value = 0;
+ }
+ delay_reg_value = ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
+ dwc_ddrphy_apb_wr(reg_add, delay_reg_value);
+ }
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) {
+ reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 8) >> 1) << 12) | (0x8c + (over_ride_sub_index / 8) + ((over_ride_sub_index % 2) << 8)));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+ delay_reg_value = ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
+ if (over_ride_increase_decrease == 0) {
+ delay_reg_value = delay_reg_value + step_value;
+ if (delay_reg_value > 95)
+ delay_reg_value = 95;
+ }
+ if (over_ride_increase_decrease != 0) {
+ if (delay_reg_value > step_value)
+ delay_reg_value = delay_reg_value - step_value;
+ else
+ delay_reg_value = 0;
+ }
+ delay_reg_value = ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
+ dwc_ddrphy_apb_wr(reg_add, delay_reg_value);
+ dwc_ddrphy_apb_wr(reg_add + 4, delay_reg_value);
+ }
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
+ reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (0x68 + ((over_ride_sub_index % 9) << 8) + (over_ride_sub_index / 36)));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+ delay_reg_value = ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
+ if (over_ride_increase_decrease == 0) {
+ delay_reg_value = delay_reg_value + step_value;
+ if (delay_reg_value > 63)
+ delay_reg_value = 63;
+ }
+ if (over_ride_increase_decrease != 0) {
+ if (delay_reg_value > step_value)
+ delay_reg_value = delay_reg_value - step_value;
+ else
+ delay_reg_value = 0;
+ }
+ delay_reg_value = ddr_cacl_phy_over_ride_back_reg(over_ride_index, delay_reg_value);
+ dwc_ddrphy_apb_wr(reg_add, delay_reg_value);
+ }
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXENDLY) {
+ reg_add = ((0 << 20) | (1 << 16) | ((over_ride_sub_index % 8) << 12) | (0x80 + (over_ride_sub_index / 8)));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+ delay_reg_value = ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value);
+ if (over_ride_increase_decrease == 0) {
+ dwc_ddrphy_apb_wr(reg_add, ((delay_old_value & 0x3f) + step_value) | (delay_old_value & 0xffc0));
+ if (((delay_old_value & 0x3f) + step_value) > 0x3f)
+ dwc_ddrphy_apb_wr(reg_add, 0x3f | (delay_old_value & 0xffc0));
+ } else {
+ dwc_ddrphy_apb_wr(reg_add, ((delay_old_value & 0x3f) - step_value) | (delay_old_value & 0xffc0));
+ if (((delay_old_value & 0x3f) < step_value))
+ dwc_ddrphy_apb_wr(reg_add, (delay_old_value & 0xffc0));
+ }
+ }
+
+ if ((over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) || (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF_DAC1)) {
+ reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (((over_ride_sub_index % 36) % 9) << 8) | (0x40));
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF_DAC1)
+ reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (((over_ride_sub_index % 36) % 9) << 8) | (0x30));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+ delay_reg_value = delay_old_value;
+ if (over_ride_increase_decrease == 0) {
+ delay_reg_value = delay_reg_value + step_value;
+ if (delay_reg_value > 127)
+ delay_reg_value = 127;
+ }
+ if (over_ride_increase_decrease != 0) {
+ if (delay_reg_value >= step_value)
+ delay_reg_value = delay_reg_value - step_value;
+ else
+ delay_reg_value = 0;
+ }
+ dwc_ddrphy_apb_wr(reg_add, delay_reg_value);
+ }
+ printf("reg_add %08x old_value %08x update_to %08x dec %d to %d \n", ((unsigned int)(((reg_add) << 1) + (p_ddr_base->ddr_phy_base_address))),
+ delay_old_value, dwc_ddrphy_apb_rd(reg_add), ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value),
+ (unsigned int)ddr_cacl_phy_delay_all_step(over_ride_index, dwc_ddrphy_apb_rd(reg_add)));
+}
+
+void dwc_window_reg_after_training_update_increas(char over_ride_index, uint32_t over_ride_sub_index, uint32_t over_ride_increase_decrease,
+ uint32_t offset_value)
+{
+ uint32_t delay_old_value = 0;
+ uint32_t temp_count_3 = 0;
+ uint64_t reg_add = 0;
+
+ if (!over_ride_index)
+ return;
+
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
+ reg_add = ((0 << 20) | (0 << 16) | (over_ride_sub_index << 12) | (0x80));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+ for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++)
+ dwc_window_reg_after_training_update_increas_sub(over_ride_index
+ , ((over_ride_sub_index)), over_ride_increase_decrease, 1);
+ }
+
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
+ reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 8) >> 1) << 12) | (0xd0 + (over_ride_sub_index / 8) + ((over_ride_sub_index % 2) << 8)));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+ for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++)
+ dwc_window_reg_after_training_update_increas_sub(over_ride_index
+ , ((over_ride_sub_index)), over_ride_increase_decrease, 1);
+ }
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) {
+ reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 8) >> 1) << 12) | (0x8c + (over_ride_sub_index / 8) + ((over_ride_sub_index % 2) << 8)));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+ for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++)
+ dwc_window_reg_after_training_update_increas_sub(over_ride_index
+ , ((over_ride_sub_index)), over_ride_increase_decrease, 1);
+ }
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) {
+ reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (0xc0 + ((over_ride_sub_index % 9) << 8) + (over_ride_sub_index / 36)));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+ for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++)
+ dwc_window_reg_after_training_update_increas_sub(over_ride_index
+ , ((over_ride_sub_index)), over_ride_increase_decrease, 1);
+ }
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
+ reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (0x68 + ((over_ride_sub_index % 9) << 8) + (over_ride_sub_index / 36)));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+ for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++)
+ dwc_window_reg_after_training_update_increas_sub(over_ride_index
+ , ((over_ride_sub_index)), over_ride_increase_decrease, 1);
+ }
+
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXENDLY) {
+ reg_add = ((0 << 20) | (1 << 16) | ((over_ride_sub_index % 8) << 12) | (0x80 + (over_ride_sub_index / 8)));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+ for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++)
+ dwc_window_reg_after_training_update_increas_sub(over_ride_index
+ , ((over_ride_sub_index)), over_ride_increase_decrease, 1);
+ }
+
+ if ((over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) || (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF_DAC1)) {
+ reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (((over_ride_sub_index % 36) % 9) << 8) | (0x40));
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF_DAC1)
+ reg_add = ((0 << 20) | (1 << 16) | (((over_ride_sub_index % 36) / 9) << 12) | (((over_ride_sub_index % 36) % 9) << 8) | (0x30));
+ delay_old_value = dwc_ddrphy_apb_rd(reg_add);
+ for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++)
+ dwc_window_reg_after_training_update_increas_sub(over_ride_index
+ , ((over_ride_sub_index)), over_ride_increase_decrease, 1);
+ }
+
+ printf("over_ride_increase_decrease==%d\n", over_ride_increase_decrease);
+
+ if (over_ride_increase_decrease == 1) {
+ unsigned int org_cacl_value = (delay_old_value) & 0x3f;
+ printf("org_cacl_value==%d\n", org_cacl_value);
+ printf("offset_value==%d\n", offset_value);
+ if ((org_cacl_value & 0x3f) < offset_value) {
+ char temp_test_index_2 = 0;
+ char temp_count_4 = 0;
+ char temp_count_2 = 0;
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) {
+ temp_test_index_2 = DMC_TEST_WINDOW_INDEX_RXPBDLY;
+
+ for (temp_count_2 = 0; temp_count_2 < 4; temp_count_2++) {
+ for (temp_count_4 = 0; temp_count_4 < (((offset_value - org_cacl_value) * ui_1_32_100step) / bdlr_100step); temp_count_4++) {
+ dwc_window_reg_after_training_update_increas_sub(temp_test_index_2
+ , ((over_ride_sub_index / 2) * 9 +
+ temp_count_2 + (over_ride_sub_index % 2) * 4), 0, 1);
+ }
+ }
+ }
+
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
+ temp_test_index_2 = DMC_TEST_WINDOW_INDEX_RXPBDLY;
+
+ for (temp_count_2 = 0; temp_count_2 < 4; temp_count_2++) {
+ if (temp_count_2 == ((over_ride_sub_index % 9) % 4))
+ temp_count_2++;
+
+ for (temp_count_4 = 0; temp_count_4 < (offset_value - org_cacl_value); temp_count_4++) {
+ dwc_window_reg_after_training_update_increas_sub(temp_test_index_2
+ , ((over_ride_sub_index / 9) * 9 +
+ temp_count_2 + (((over_ride_sub_index % 9) > 3) ? 4 : 0)), 0, 1);
+ }
+ }
+
+ if ((((offset_value - org_cacl_value) * bdlr_100step) / ui_1_32_100step)) {
+ temp_test_index_2 = DMC_TEST_WINDOW_INDEX_RXCLKDLY;
+
+ for (temp_count_4 = 0; temp_count_4 < (((offset_value - org_cacl_value) * bdlr_100step) / ui_1_32_100step); temp_count_4++) {
+ dwc_window_reg_after_training_update_increas_sub(temp_test_index_2
+ , (((over_ride_sub_index / 9) << 1) +
+ (((over_ride_sub_index % 9) > 3) ? 1 : 0)
+ ), 0, 1);
+ }
+ }
+ }
+ }
+ }
+ printf("reg_add %08x old_value %08x update_to %08x dec %d to %d \n", ((unsigned int)(((reg_add) << 1) + (p_ddr_base->ddr_phy_base_address))),
+ delay_old_value, dwc_ddrphy_apb_rd(reg_add), ddr_cacl_phy_delay_all_step(over_ride_index, delay_old_value),
+ ddr_cacl_phy_delay_all_step(over_ride_index, dwc_ddrphy_apb_rd(reg_add)));
+}
+
+int do_ddr2pll_g12_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ check_base_address();
+#define DMC_WINDOW_CMD 20180010 //g12_d2pll 1584 0 0 0 0 0x8
+#define G12_D2PLL_CMD_DMC_FULL_TEST 0x01
+#define G12_D2PLL_CMD_OVER_RIDE 0x02
+#define G12_D2PLL_CMD_OVER_RIDE_PLUS_FULLTEST 0x03
+#define G12_D2PLL_CMD_OVER_RIDE_TRAINING_HDTL 0x04
+#define G12_D2PLL_CMD_OFFSET 0x06
+#define G12_D2PLL_CMD_WINDOW_TEST 0x11
+#define G12_D2PLL_CMD_WINDOW_TEST_AND_STICKY_OVERRIDE 0x12
+#define G12_D2PLL_CMD_SUSPEND_TEST 0x21
+#define G12_D2PLL_CMD_SWEEP_EE_VOLTAGE_FREQUENCY_TABLE_TEST 0x32
+#define G12_D2PLL_CMD_DDR_EYE_TEST 0x41
+#define G12_D2PLL_CMD_DDR_EYE_TEST_AND_STICKY_OVERRIDE 0x42
+#define G12_D2PLL_CMD_DDR_EYE_TEST_DAC1 0x43
+#define G12_D2PLL_CMD_DDR_EYE_TEST_AND_STICKY_OVERRIDE_DAC1 0x44
+
+#define G12_D2PLL_CMD_DDR_DVFS_TEST 0x51
+
+#define DMC_TEST_WINDOW_INDEX_ATXDLY 1
+#define DMC_TEST_WINDOW_INDEX_TXDQSDLY 2
+#define DMC_TEST_WINDOW_INDEX_RXCLKDLY 3
+#define DMC_TEST_WINDOW_INDEX_TXDQDLY 4
+#define DMC_TEST_WINDOW_INDEX_RXPBDLY 5
+
+#define DMC_TEST_WINDOW_INDEX_EE_VOLTAGE 0x11
+
+ char *endp;
+ unsigned int pll;
+ unsigned int window_test_stick_cmd_value = 0;
+ /* need at least two arguments */
+ if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_C2) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5D) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_S4))
+ do_read_c2_ddr_bdlr_steps();
+ if (argc < 2)
+ goto usage;
+
+ pll = simple_strtoul(argv[1], &endp, 0);
+ if (*argv[1] == 0 || *endp != 0) {
+ printf("Error: Wrong format parament!pll=0x%08x\n", pll);
+ return 1;
+ }
+ unsigned int argc_count = 1;
+ unsigned int para_meter[30] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+ while (argc_count < argc) {
+ para_meter[argc_count - 1] = simple_strtoul(argv[argc_count], &endp, 0);
+ if (*argv[argc_count] == 0 || *endp != 0)
+ para_meter[argc_count - 1] = 0;
+ argc_count++;
+ }
+
+ argc_count = 2;
+ window_test_stick_cmd_value = para_meter[argc_count - 1];
+ if ((window_test_stick_cmd_value == G12_D2PLL_CMD_OVER_RIDE) || (window_test_stick_cmd_value == G12_D2PLL_CMD_OVER_RIDE_PLUS_FULLTEST)) {
+ para_meter[3] = (para_meter[3] << 24) | (para_meter[4] << 16) | (para_meter[5] << 0);
+ para_meter[4] = (para_meter[6] << 24) | (para_meter[7] << 16) | (para_meter[8] << 0);
+ para_meter[5] = (para_meter[9] << 24) | (para_meter[10] << 16) | (para_meter[11] << 0);
+ }
+ if ((window_test_stick_cmd_value == G12_D2PLL_CMD_WINDOW_TEST) || (window_test_stick_cmd_value == G12_D2PLL_CMD_WINDOW_TEST_AND_STICKY_OVERRIDE))
+ para_meter[5] = (para_meter[9] << 28) | (para_meter[10] << 24) | (para_meter[11] << 20) | (para_meter[12] << 21) | (para_meter[13] << 22) | (para_meter[14] << 25) | (para_meter[5] << 0);
+ if ((window_test_stick_cmd_value >= G12_D2PLL_CMD_DDR_EYE_TEST) && (window_test_stick_cmd_value <= G12_D2PLL_CMD_DDR_EYE_TEST_AND_STICKY_OVERRIDE_DAC1)) {
+ para_meter[3] = (para_meter[3] << 0) | (para_meter[4] << 8) | (para_meter[5] << 16) | (para_meter[6] << 24);
+ para_meter[4] = (para_meter[7] << 0) | (para_meter[8] << 8) | (para_meter[9] << 16) | (para_meter[10] << 24);
+ para_meter[5] = para_meter[11]; //(para_meter[11]<<0)|(para_meter[12]<<8)|(para_meter[13]<<16)|(para_meter[14]<<24);
+ para_meter[6] = para_meter[12]; //para_meter[15];
+ para_meter[7] = para_meter[13]; //para_meter[16];
+ para_meter[8] = para_meter[14]; //para_meter[17];
+ }
+ wr_reg((p_ddr_base->preg_sticky_reg0), (rd_reg((p_ddr_base->preg_sticky_reg0)) & 0xffff) | (0xf13 << 20));
+ argc_count = 0;
+ printf("\nP_PREG_STICKY_REG [0x%08x] [0x%08x]==[0x%08x]\n", argc_count, ((p_ddr_base->preg_sticky_reg0) + (argc_count << 2)), rd_reg((p_ddr_base->preg_sticky_reg0) + (argc_count << 2)));
+ argc_count = 1;
+ while (argc_count < 10) {
+ wr_reg((p_ddr_base->preg_sticky_reg0) + (argc_count << 2), para_meter[argc_count - 1]);
+ printf("P_PREG_STICKY_REG [0x%08x] [0x%08x]==[0x%08x]\n", argc_count, ((p_ddr_base->preg_sticky_reg0) + (argc_count << 2)), rd_reg((p_ddr_base->preg_sticky_reg0) + (argc_count << 2)));
+ argc_count++;
+ }
+ dcache_disable();
+ if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_A1) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_C1) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_C2)
+ || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_SC2) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_S4)
+ //|| (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5D)
+ ) {
+ printf("reset...\n");
+ run_command("reset", 0);
+ } else { //G12A/G12B/SM1/TL1/TM2 //(p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T7)
+ printf("reboot...\n"); //reset will enter bl2 panic path,so change to "reboot"
+ run_command("reboot", 0);
+ //ddr_test_watchdog_reset_system();
+ }
+
+ return 0;
+
+usage:
+ cmd_usage(cmdtp);
+ return 1;
+}
+
+U_BOOT_CMD(
+ g12_d2pll, 18, 1, do_ddr2pll_g12_cmd,
+ "g12_d2pll 1300 1 0x10 0",
+ "g12_d2pll clk delay_index delay_value before_after_training_setting\n"
+ );
+
+#endif
+
+#if (CONFIG_DDR_PHY >= P_DDR_PHY_G12)
+
+int do_ddr_g12_override_data(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ check_base_address();
+
+ uint32_t dmc_retraining_ctrl = 0;
+ dmc_retraining_ctrl = rd_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address));
+ unsigned int ddr_dmc_apd_temp_save, ddr_dmc_asr_temp_save;
+ ddr_dmc_apd_temp_save = readl((p_ddr_base->ddr_dmc_apd_address));
+ ddr_dmc_asr_temp_save = readl((p_ddr_base->ddr_dmc_asr_address));
+ printf("\12nm phy read write register should closd apd and asr funciton\n");
+
+#define G12_DATA_READ_OFFSET_MAX (0X3F)
+#define G12_DATA_WRITE_OFFSET_MAX (0X3F + 7 * 32)
+
+#if 1
+ int i = 0;
+ printf("\nargc== 0x%08x\n", argc);
+ for (i = 0; i < argc; i++)
+ printf("\nargv[%d]=%s\n", i, argv[i]);
+ char *endp;
+ //rank_index dq_index write_read left/right offset_value
+ unsigned int test_index = 0; // 1 ac ,0x2, write dqs ,0x4,read dqs,0x8,write dq,0x10 read dq
+ unsigned int dq_index = 0; //0-8 rank0 lane0 ,rank0 9-17 lane1,rank0 18-26 lane2, rank0 27-35 lane3, 36+0-8 rank1 lane0 ,rank1 36+9-17 lane1,rank1 36+18-26 lane2, rank1 36+27-35 lane3
+ unsigned int ovrride_value = 0; //
+
+ unsigned int count = 0;
+ unsigned int lcdlr_max = 0;
+
+ if (argc == 1) {
+ printf("\nplease read help\n");
+ } else if (argc > 4) { //offset_enable=1;
+ {
+ count = 0;
+ test_index = simple_strtoull_ddr(argv[count + 1], &endp, 0);
+ if (*argv[count + 1] == 0 || *endp != 0)
+ test_index = 0;
+ }
+ {
+ count++;
+ dq_index = simple_strtoull_ddr(argv[count + 1], &endp, 0);
+ if (*argv[count + 1] == 0 || *endp != 0)
+ dq_index = 0;
+ }
+
+ {
+ count++;
+ ovrride_value = simple_strtoull_ddr(argv[count + 1], &endp, 0);
+ if (*argv[count + 1] == 0 || *endp != 0)
+ ovrride_value = 0;
+ }
+ } else {
+ return 1;
+ }
+ printf("lcdlr_max %d,\n", lcdlr_max);
+
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl & (~(1 << 31)));
+ writel((0), p_ddr_base->ddr_dmc_apd_address);
+ writel((0), p_ddr_base->ddr_dmc_asr_address);
+ {
+ dwc_window_reg_after_training_update(test_index, dq_index, ovrride_value);
+ }
+
+#endif
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl);
+ writel(ddr_dmc_apd_temp_save, p_ddr_base->ddr_dmc_apd_address);
+ writel(ddr_dmc_asr_temp_save, p_ddr_base->ddr_dmc_asr_address);
+ return 1;
+}
+U_BOOT_CMD(
+ ddr_g12_override_data, 20, 1, do_ddr_g12_override_data,
+ "ddr_g12_override_data 1 0 0 0 1 3",
+ "ddr_g12_override_data test_index dq_index ovrride_value \n"
+ );
+
+void ddr_window_reg_after_training_update_increas_sub_c2(char over_ride_index, uint32_t over_ride_sub_index, uint32_t over_ride_increase_decrease, uint32_t step)
+{
+ uint32_t delay_old_value = 0;
+ uint32_t delay_reg_value = 0;
+ uint32_t ps = 0;
+
+ if (!over_ride_index)
+ return;
+ if (over_ride_index <= DMC_TEST_WINDOW_INDEX_DRAM_VREF) {
+ delay_old_value = ddr_phy_training_reg_read_write(ddr_set_t_p, over_ride_index, over_ride_sub_index, delay_old_value, REGISTER_READ, ps);
+ if (over_ride_increase_decrease == 0)
+ delay_reg_value = delay_old_value + step;
+ if (over_ride_increase_decrease != 0) {
+ if (delay_old_value > step)
+ delay_reg_value = delay_old_value - step;
+ else
+ delay_reg_value = 0;
+ }
+
+ ddr_phy_training_reg_read_write(ddr_set_t_p, over_ride_index, over_ride_sub_index, delay_reg_value, REGISTER_WRITE,
+ ps);
+ }
+}
+
+void dwc_window_reg_after_training_update_increas_c2(char over_ride_index, uint32_t over_ride_sub_index, uint32_t over_ride_increase_decrease,
+ uint32_t offset_value)
+{
+ uint32_t temp_count_3 = 0;
+
+ if (!over_ride_index)
+ return;
+
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
+ for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++)
+ ddr_window_reg_after_training_update_increas_sub_c2(over_ride_index
+ , ((over_ride_sub_index)), over_ride_increase_decrease, 1);
+ }
+
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
+ for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++)
+ ddr_window_reg_after_training_update_increas_sub_c2(over_ride_index
+ , ((over_ride_sub_index)), over_ride_increase_decrease, 1);
+ }
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) {
+ for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++)
+ ddr_window_reg_after_training_update_increas_sub_c2(over_ride_index
+ , ((over_ride_sub_index)), over_ride_increase_decrease, 1);
+ }
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) {
+ for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++)
+ ddr_window_reg_after_training_update_increas_sub_c2(over_ride_index
+ , ((over_ride_sub_index)), over_ride_increase_decrease, 1);
+ }
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
+ for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++)
+ ddr_window_reg_after_training_update_increas_sub_c2(over_ride_index
+ , ((over_ride_sub_index)), over_ride_increase_decrease, 1);
+ }
+
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_RXENDLY) {
+ for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++)
+ ddr_window_reg_after_training_update_increas_sub_c2(over_ride_index
+ , ((over_ride_sub_index)), over_ride_increase_decrease, 1);
+ }
+
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) {
+ for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++)
+ ddr_window_reg_after_training_update_increas_sub_c2(over_ride_index
+ , ((over_ride_sub_index)), over_ride_increase_decrease, 1);
+ }
+ if (over_ride_index == DMC_TEST_WINDOW_INDEX_SOC_VREF_DAC1) {
+ for (temp_count_3 = 0; temp_count_3 < offset_value; temp_count_3++)
+ ddr_window_reg_after_training_update_increas_sub_c2(over_ride_index
+ , ((over_ride_sub_index)), over_ride_increase_decrease, 1);
+ }
+}
+
+int do_ddr_c2_offset_data(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ check_base_address();
+
+ uint32_t dmc_retraining_ctrl = 0;
+ dmc_retraining_ctrl = rd_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address));
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl & (~(1 << 31)));
+ unsigned int ddr_dmc_apd_temp_save, ddr_dmc_asr_temp_save;
+ ddr_dmc_apd_temp_save = readl(p_ddr_base->ddr_dmc_apd_address);
+ ddr_dmc_asr_temp_save = readl(p_ddr_base->ddr_dmc_asr_address);
+#define G12_DATA_READ_OFFSET_MAX (0X3F)
+#define G12_DATA_WRITE_OFFSET_MAX (0X3F + 7 * 32)
+ printf("\12nm phy read write register should closd apd and asr funciton\n");
+ int i = 0;
+
+ printf("\nargc== 0x%08x\n", argc);
+ for (i = 0; i < argc; i++)
+ printf("\nargv[%d]=%s\n", i, argv[i]);
+ char *endp;
+ //rank_index dq_index write_read left/right offset_value
+ unsigned int test_index = 0; // 1 ac ,0x2, write dqs ,0x4,read dqs,0x8,write dq,0x10 read dq
+ unsigned int test_dq_mask_1 = 0; //each bit mask corresspond with dq_index
+ unsigned int test_dq_mask_2 = 0; //each bit mask corresspond with dq_index
+ unsigned int test_dq_mask_3 = 0; //each bit mask corresspond with dq_index
+ unsigned int left_right_flag = 0; // 1 left ,2 right #define DDR_PARAMETER_LEFT 1 #define DDR_PARAMETER_RIGHT 2
+ unsigned int offset_value = 0; //
+ unsigned int count = 0;
+ unsigned int count_max = 0;
+ unsigned int lcdlr_max = 0;
+
+ global_ddr_clk = get_ddr_clk();
+ bdlr_100step = get_bdlr_100step(global_ddr_clk);
+ if (global_ddr_clk)
+ ui_1_32_100step = (1000000 * 100 / (global_ddr_clk * 2 * 32));
+
+ if (argc == 1) {
+ printf("\nplease read aml phy cmd help\n");
+ } else if (argc > 6) { //offset_enable=1;
+ {
+ count = 0;
+ test_index = simple_strtoull_ddr(argv[count + 1], &endp, 0);
+ if (*argv[count + 1] == 0 || *endp != 0)
+ test_index = 0;
+ }
+ {
+ count++;
+ test_dq_mask_1 = simple_strtoull_ddr(argv[count + 1], &endp, 0);
+ if (*argv[count + 1] == 0 || *endp != 0)
+ test_dq_mask_1 = 0;
+ }
+ {
+ count++;
+ test_dq_mask_2 = simple_strtoull_ddr(argv[count + 1], &endp, 0);
+ if (*argv[count + 1] == 0 || *endp != 0)
+ test_dq_mask_2 = 0;
+ }
+ {
+ count++;
+ test_dq_mask_3 = simple_strtoull_ddr(argv[count + 1], &endp, 0);
+ if (*argv[count + 1] == 0 || *endp != 0)
+ test_dq_mask_3 = 0;
+ }
+ {
+ count++;
+ left_right_flag = simple_strtoull_ddr(argv[count + 1], &endp, 0);
+ if (*argv[count + 1] == 0 || *endp != 0)
+ left_right_flag = 0;
+ }
+ {
+ count++;
+ offset_value = simple_strtoull_ddr(argv[count + 1], &endp, 0);
+ if (*argv[count + 1] == 0 || *endp != 0)
+ offset_value = 0;
+ }
+ } else {
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl);
+ return 1;
+ }
+ printf("lcdlr_max %d,\n", lcdlr_max);
+ if (left_right_flag == DDR_PARAMETER_RIGHT)
+ printf("offset right ++ left_right_flag %d,\n", left_right_flag);
+ if (left_right_flag == DDR_PARAMETER_LEFT)
+ printf("offset left --left_right_flag %d,\n", left_right_flag);
+
+ if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
+ count_max = 36;
+ lcdlr_max = 4 * 128 - 1; //0x3ff;
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
+ count_max = 8;
+ lcdlr_max = 4 * 128 - 1; //0x3ff;
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) {
+ count_max = 8;
+ lcdlr_max = 255; //0x3f;
+ }
+
+ if (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) {
+ count_max = 36 * 2;
+ lcdlr_max = 8 * 128 - 1; //0x1ff;
+ }
+
+ if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
+ count_max = 36 * 2;
+ lcdlr_max = 255;
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) {
+ count_max = 36 * 1;
+ lcdlr_max = 0x3f;
+ printf(" soc vref rank0 and rank1 share vref dac\n");
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_SOC_VREF_DAC1) {
+ count_max = 36 * 1;
+ lcdlr_max = 0x3f;
+ printf(" soc vref rank0 and rank1 share vref dac\n");
+ }
+ count = 0;
+ writel((0), p_ddr_base->ddr_dmc_apd_address);
+ writel((0), p_ddr_base->ddr_dmc_asr_address);
+
+ for (; count < count_max; count++) {
+ if ((count < 32)) {
+ if (test_dq_mask_1 & (1 << (count % 32)))
+ continue;
+ }
+
+ if ((count > 31) && (count < 63)) {
+ if (test_dq_mask_2 & (1 << (count % 32)))
+ continue;
+ }
+
+ if ((count > 63)) {
+ if (test_dq_mask_3 & (1 << (count % 32)))
+ continue;
+ }
+ {
+ if (left_right_flag == DDR_PARAMETER_RIGHT) {
+ dwc_window_reg_after_training_update_increas_c2(test_index,
+ count,
+ 0, offset_value);
+ }
+ if (left_right_flag == DDR_PARAMETER_LEFT) {
+ dwc_window_reg_after_training_update_increas_c2(test_index,
+ count,
+ 1, offset_value);
+ }
+ }
+ }
+ writel(ddr_dmc_apd_temp_save, p_ddr_base->ddr_dmc_apd_address);
+ writel(ddr_dmc_asr_temp_save, p_ddr_base->ddr_dmc_asr_address);
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl);
+ return 1;
+}
+
+int do_ddr_g12_offset_data(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ //ddr_g12_offset_data 1 0 0 0 1 3
+ check_base_address();
+
+ if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_C2)
+ || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5)
+ || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5D)
+ || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_S4)) {
+ do_ddr_c2_offset_data(cmdtp, flag, argc, argv);
+ return 1;
+ }
+
+ uint32_t dmc_retraining_ctrl = 0;
+ dmc_retraining_ctrl = rd_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address));
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl & (~(1 << 31)));
+ unsigned int ddr_dmc_apd_temp_save, ddr_dmc_asr_temp_save;
+ ddr_dmc_apd_temp_save = readl(p_ddr_base->ddr_dmc_apd_address);
+ ddr_dmc_asr_temp_save = readl(p_ddr_base->ddr_dmc_asr_address);
+#define G12_DATA_READ_OFFSET_MAX (0X3F)
+#define G12_DATA_WRITE_OFFSET_MAX (0X3F + 7 * 32)
+ printf("\12nm phy read write register should closd apd and asr funciton\n");
+
+ int i = 0;
+ printf("\nargc== 0x%08x\n", argc);
+ for (i = 0; i < argc; i++)
+ printf("\nargv[%d]=%s\n", i, argv[i]);
+ char *endp;
+ //rank_index dq_index write_read left/right offset_value
+ unsigned int test_index = 0; // 1 ac ,0x2, write dqs ,0x4,read dqs,0x8,write dq,0x10 read dq
+ unsigned int test_dq_mask_1 = 0; //each bit mask corresspond with dq_index
+ unsigned int test_dq_mask_2 = 0; //each bit mask corresspond with dq_index
+ unsigned int test_dq_mask_3 = 0; //each bit mask corresspond with dq_index
+ unsigned int left_right_flag = 0; // 1 left ,2 right #define DDR_PARAMETER_LEFT 1 #define DDR_PARAMETER_RIGHT 2
+ unsigned int offset_value = 0; //
+ unsigned int count = 0;
+ unsigned int count_max = 0;
+ unsigned int lcdlr_max = 0;
+
+ global_ddr_clk = get_ddr_clk();
+ bdlr_100step = get_bdlr_100step(global_ddr_clk);
+ if (global_ddr_clk)
+ ui_1_32_100step = (1000000 * 100 / (global_ddr_clk * 2 * 32));
+
+ if (argc == 1) {
+ printf("\nplease read help\n");
+ return 1;
+ } else if (argc > 6) { //offset_enable=1;
+ {
+ count = 0;
+ test_index = simple_strtoull_ddr(argv[count + 1], &endp, 0);
+ if (*argv[count + 1] == 0 || *endp != 0)
+ test_index = 0;
+ }
+ {
+ count++;
+ test_dq_mask_1 = simple_strtoull_ddr(argv[count + 1], &endp, 0);
+ if (*argv[count + 1] == 0 || *endp != 0)
+ test_dq_mask_1 = 0;
+ }
+ {
+ count++;
+ test_dq_mask_2 = simple_strtoull_ddr(argv[count + 1], &endp, 0);
+ if (*argv[count + 1] == 0 || *endp != 0)
+ test_dq_mask_2 = 0;
+ }
+ {
+ count++;
+ test_dq_mask_3 = simple_strtoull_ddr(argv[count + 1], &endp, 0);
+ if (*argv[count + 1] == 0 || *endp != 0)
+ test_dq_mask_3 = 0;
+ }
+ {
+ count++;
+ left_right_flag = simple_strtoull_ddr(argv[count + 1], &endp, 0);
+ if (*argv[count + 1] == 0 || *endp != 0)
+ left_right_flag = 0;
+ }
+ {
+ count++;
+ offset_value = simple_strtoull_ddr(argv[count + 1], &endp, 0);
+ if (*argv[count + 1] == 0 || *endp != 0)
+ offset_value = 0;
+ }
+ } else {
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl);
+ return 1;
+ }
+
+ if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T7)) {
+ writel(ddr_dmc_apd_temp_save, p_ddr_base->ddr_dmc_apd_address);
+ writel(ddr_dmc_asr_temp_save, p_ddr_base->ddr_dmc_asr_address);
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl);
+ count = 0;
+ test_index = simple_strtoull_ddr(argv[count + 1], &endp, 0);
+ if (*argv[count + 1] == 0 || *endp != 0)
+ test_index = 0;
+ if (test_index/100)
+ dmc_ddr_config_channel_id=1;
+ else
+ dmc_ddr_config_channel_id=0;
+ test_index=(test_index%100); //for DDR_PHY 1
+ dmc_change_channel(dmc_ddr_config_channel_id);
+ dmc_retraining_ctrl = rd_reg(p_ddr_base->ddr_dmc_lpdd4_retraining_address);
+ wr_reg(p_ddr_base->ddr_dmc_lpdd4_retraining_address, dmc_retraining_ctrl & (~(1 << 31)));
+ ddr_dmc_apd_temp_save = readl(p_ddr_base->ddr_dmc_apd_address);
+ ddr_dmc_asr_temp_save = readl(p_ddr_base->ddr_dmc_asr_address);
+ }
+
+ printf("lcdlr_max %d,\n", lcdlr_max);
+ if (left_right_flag == DDR_PARAMETER_RIGHT)
+ printf("offset right ++ left_right_flag %d,\n", left_right_flag);
+ if (left_right_flag == DDR_PARAMETER_LEFT)
+ printf("offset left --left_right_flag %d,\n", left_right_flag);
+ if (test_index == DMC_TEST_WINDOW_INDEX_ATXDLY) {
+ count_max = 10;
+ lcdlr_max = 3 * 32; //0x3ff;
+ }
+
+ if (test_index == DMC_TEST_WINDOW_INDEX_TXDQSDLY) {
+ count_max = 16;
+ lcdlr_max = 16 * 32; //0x3ff;
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_RXCLKDLY) {
+ count_max = 16;
+ lcdlr_max = 96; //0x3f;
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_TXDQDLY) {
+ count_max = 36 * 2;
+ lcdlr_max = 8 * 32; //0x1ff;
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_RXPBDLY) {
+ count_max = 36 * 2;
+ lcdlr_max = 0x3f;
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_SOC_VREF) {
+ count_max = 36 * 1;
+ lcdlr_max = 0x3f;
+ printf(" soc vref rank0 and rank1 share vref dac\n");
+ }
+ if (test_index == DMC_TEST_WINDOW_INDEX_SOC_VREF_DAC1) {
+ count_max = 36 * 1;
+ lcdlr_max = 0x3f;
+ printf(" soc vref rank0 and rank1 share vref dac\n");
+ }
+
+ count = 0;
+ writel((0), p_ddr_base->ddr_dmc_apd_address);
+ writel((0), p_ddr_base->ddr_dmc_asr_address);
+
+ for (; count < count_max; count++) {
+ if ((count < 32)) {
+ if (test_dq_mask_1 & (1 << (count % 32)))
+ continue;
+ }
+
+ if ((count > 31) && (count < 63)) {
+ if (test_dq_mask_2 & (1 << (count % 32)))
+ continue;
+ }
+
+ if ((count > 63)) {
+ if (test_dq_mask_3 & (1 << (count % 32)))
+ continue;
+ }
+ {
+ if (left_right_flag == DDR_PARAMETER_RIGHT) {
+ dwc_window_reg_after_training_update_increas(test_index,
+ count,
+ 0, offset_value);
+ }
+ if (left_right_flag == DDR_PARAMETER_LEFT) {
+ dwc_window_reg_after_training_update_increas(test_index,
+ count,
+ 1, offset_value);
+ }
+ }
+ }
+
+ writel(ddr_dmc_apd_temp_save, p_ddr_base->ddr_dmc_apd_address);
+ writel(ddr_dmc_asr_temp_save, p_ddr_base->ddr_dmc_asr_address);
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl);
+
+ if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T7)) {
+ dmc_ddr_config_channel_id=0;
+ dmc_change_channel(dmc_ddr_config_channel_id);
+ }
+ return 1;
+}
+
+U_BOOT_CMD(
+ ddr_g12_offset_data, 20, 1, do_ddr_g12_offset_data,
+ "ddr_g12_offset_data 1 0 0 0 1 3",
+ "ddr_g12_offset_data test_index mask1 mask2 mask3 left/right offset_value \n"
+ );
+
+#endif
+
+int do_ddr_test_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ check_base_address();
+
+ uint32_t dmc_retraining_ctrl = 0;
+ dmc_retraining_ctrl = rd_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address));
+ unsigned int ddr_dmc_apd_temp_save, ddr_dmc_asr_temp_save;
+ ddr_dmc_apd_temp_save = readl(p_ddr_base->ddr_dmc_apd_address);
+ ddr_dmc_asr_temp_save = readl(p_ddr_base->ddr_dmc_asr_address);
+
+ printf("\n ddr test cmd version== %s\n", CMD_VER);
+ printf("\nargc== 0x%08x\n", argc);
+ int i;
+ for (i = 0; i < argc; i++)
+ printf("\nargv[%d]=%s\n", i, argv[i]);
+
+ /* need at least two arguments */
+ if (argc < 2)
+ goto usage;
+ if ((strcmp(argv[1], "h") == 0))
+ goto usage;
+
+ printf("\12nm phy read write register should closd apd and asr funciton\n");
+
+ global_ddr_clk = get_ddr_clk();
+ printf("\nddr_clk== %dMHz\n", global_ddr_clk);
+
+#define DDR_TEST_CMD__NONE 0
+#define DDR_TEST_CMD__DDR_TEST 1
+#define DDR_TEST_CMD__DDR_TUNE_ACLCDLR 2
+#define DDR_TEST_CMD__DDR_TUNE_MAX_CLK 3 //ddr_test_cmd 3 0x8000000 3 1
+#define DDR_TEST_CMD__DDR_TUNE_ZQ 4
+#define DDR_TEST_CMD__DDR_TUNE_VREF 5
+#define DDR_TEST_CMD__DDR_GXTVBB_CROSSTALK 6
+#define DDR_TEST_CMD__DDR_BANDWIDTH_TEST 7
+#define DDR_TEST_CMD__DDR_LCDLR_ENV_TUNE 8
+#define DDR_TEST_CMD__DDR_MODIFY_REG_USE_MASK 9
+#define DDR_TEST_CMD__DDR_DDR_TUNE_AC_CLK 0xa
+
+#define DDR_TEST_CMD__DDR_SETZQ 0x10
+#define DDR_TEST_CMD__DDR_TUNE_DQS 0x11
+#define DDR_TEST_CMD__DDR_SET_TEST_START_ADD 0x12
+#define DDR_TEST_CMD__DDR_TEST_AC_BIT_SETUP_HOLD_MARGIN 0x13
+#define DDR_TEST_CMD__DDR_TEST_DATA_BIT_SETUP_HOLD_MARGIN 0x14
+#define DDR_TEST_CMD__DDR_TEST_AC_LANE_BIT_MARGIN 0x15
+#define DDR_TEST_CMD__DDR_TEST_EE_VOLTAGE_MDLR_STEP 0x16
+#define DDR_TEST_CMD__DDR_TEST_D2PLL_CMD 0x17
+#define DDR_TEST_CMD__DDR_TEST_DATA_LANE_BIT_MARGIN 0x18
+#define DDR_TEST_CMD__DDR4_TUNE_PHY_VREF 0x19
+#define DDR_TEST_CMD__DDR4_TUNE_DRAM_VREF 0x1A
+#define DDR_TEST_CMD__DDR4_TUNE_AC_VREF 0x1b
+#define DDR_TEST_CMD__DDR4_SWEEP_DRAM_CLK_USE_D2PLL 0x1c
+#define DDR_TEST_CMD__DDR4_TEST_SHIFT_DDR_FREQUENCY 0x1d
+#define DDR_TEST_CMD__DDR4_TEST_DATA_WRTIE_READ 0x1e
+#define DDR_TEST_CMD__DDR_TEST_PWM_CMD 0x1f
+#define DDR_TEST_CMD__DDR_TEST_EE_SI 0x20
+#define DDR_TEST_CMD__DDR_TEST_VDDQ_SI 0x21
+#define DDR_TEST_CMD__DDR_TUNE_DDR_DATA_WINDOW_ENV 0x22
+#define DDR_TEST_CMD__DDR4_TEST_SHIFT_DDR_FREQUENCY_TXL 0x23
+#define DDR_TEST_CMD__DISPLAY_DDR_INFORMATION 0x24
+#define DDR_TEST_CMD__OFFSET_LCDLR 0x25
+#define DDR_TEST_CMD__SET_WATCH_DOG_VALUE 0x26
+#define DDR_TEST_CMD__DDR_TUNE_DDR_DATA_WINDOW_STICKY 0x27
+#define DDR_TEST_CMD__DDR4_SWEEP_DRAM_CLK_USE_D2PLL_STICKY 0x28
+#define DDR_TEST_CMD__DDR4_DDR_BIST_TEST_USE_D2PLL_STICKY 0x29
+#define DDR_TEST_CMD__DDR_SET_BIST_TEST_SIZE_STICKY_6 0x30
+#define DDR_TEST_CMD__DDR_SET_UBOOT_STORE_WINDOW 0x31
+#define DDR_TEST_CMD__DDR_SET_UBOOT_STORE_QUICK_WINDOW 0x32
+#define DDR_TEST_CMD__DDR_SET_UBOOT_KERNEL_STORE_QUICK_WINDOW 0x33
+#define DDR_TEST_CMD__DDR_SET_UBOOT_KERNEL_STORE_QUICK_WINDOW_MULTI 0x34
+#define DDR_TEST_CMD__DDR_SET_UBOOT_KERNEL_WINDOW_SAME_CHANGE 0x35
+#define DDR_TEST_CMD__DDR_SET_UBOOT_G12_RECONFIG_CMD 0x36
+#define DDR_TEST_CMD__DISPLAY_G12_DDR_INFORMATION 0x37
+#define DDR_TEST_CMD__DDR_G12_DMC_TEST 0x38
+#define DDR_TEST_CMD__DDR_G12_EE_BDLR_TEST 0x39
+
+ unsigned int ddr_test_cmd = 0;
+ unsigned int arg[30] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, };
+ char *endp;
+ ddr_test_cmd = simple_strtoull_ddr(argv[1], &endp, 0);
+ for (i = 2; i < argc; i++)
+ arg[i - 2] = simple_strtoull_ddr(argv[i], &endp, 0);
+ printf("\nddr_test_cmd== 0x%08x\n", ddr_test_cmd);
+
+ for (i = 0; i < (argc - 2); i++)
+ printf("\narg[%08x]=%08x\n", i, arg[i]);
+
+ int argc2;
+ char *argv2[30];
+
+ argc2 = argc - 1;
+ for (i = 1; i < (argc); i++)
+ argv2[i - 1] = argv[i];
+ {
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl & (~(1 << 31)));
+ writel((0), p_ddr_base->ddr_dmc_apd_address);
+ writel((0), p_ddr_base->ddr_dmc_asr_address);
+ run_command("dcache off", 0);
+ run_command("dcache on", 0);
+ printf("\n cache off on");
+ switch (ddr_test_cmd) {
+ case (DDR_TEST_CMD__NONE):
+ {
+ printf("\n 0x0 help\n");
+ printf("\n 0x1 ddrtest ddr_test_cmd 0x1 start_add test_size loops ");
+ printf("\n 0x2 test aclcdlr ddr_test_cmd 0x2 start_add test_size loops ddr_test_cmd 0x2 a 0 0x8000000 1");
+ printf("\n 0x3 test max_pllclk ddr_test_cmd 0x3 test_size loops add_freq sub_freq ");
+ printf("\n 0x4 test zq ddr_test_cmd 0x4 test_size loops add_freq sub_freq drv_odt_flag ");
+ printf("\n 0x5 test vref ddr_test_cmd 0x5 ");
+ printf("\n 0x6 test gxtvbb_crosstalk ddr_test_cmd 0x6 loops pattern_flag ");
+ printf("\n 0x7 test bandwidth ddr_test_cmd 0x7 size loops port sub_id timer_ms ");
+ printf("\n 0x8 test lcdlr_use_env_uart ddr_test_cmd 0x8 input_src wr_adj_per[] rd_adj_per[][] ");
+ printf("\n 0x9 test_reg_use_mask ddr_test_cmd 0x9 reg_add value mask ");
+ printf("\n 0xa test ac_clk ddr_test_cmd 0xa start_add test_size loops ddr_test_cmd 0xa a 0 0x8000000 1 ");
+ printf("\n 0xb ... ");
+ printf("\n 0xc ... ");
+ printf("\n 0xd ... ");
+ printf("\n 0xe ... ");
+ printf("\n 0xf ... ");
+ printf("\n 0x10 test set zq ddr_test_cmd 0x10 zq0pr0 zq1pr0 zq2pr0 ");
+ printf("\n 0x11 test tune dqs ddr_test_cmd 0x11 a 0 test_size ddr_test_cmd 0x11 a 0 0x80000");
+ printf("\n 0x12 test set start_add ddr_test_cmd 0x12 start_add ");
+ printf("\n 0x13 test ac_bit_setup_hold time ddr_test_cmd 0x13 a 0 size method pin_id ddr_test_cmd 0x13 a 0 0x8000000 0 0xc");
+ printf("\n 0x14 test data_bit_setup_hold time ddr_test_cmd 0x14 a 0 size setup/hold pin_id ddr_test_cmd 0x14 a 0 0x80000 0 3 ");
+ printf("\n 0x15 test ac_lane_setup_hold ddr_test_cmd 0x15 a 0 size ");
+ printf("\n 0x16 test ee mdlr ddr_test_cmd 0x16 voltage pwm_id loops ");
+ printf("\n 0x17 d2pll ddr_test_cmd 0x17 clk zq_ac zq_soc_dram soc_vref dram_vref dec_hex zq_vref 0\n \
+ example ddr_test_cmd 0x17 1200 0x2aa4a 0x2015995d 50 81 1 50 \n \
+ or ddr_test_cmd 0x17 1200 0x2aa4a 0x2015995d 0x09 0x20 0 50 \n");
+ printf("or ddr_test_cmd 0x17 1200 6034 60346034 0 0 0 0 1 \n");
+ printf("\n 0x18 test data_lane_setup_hold ddr_test_cmd 0x18 a 0 size range start_pin_id end_pin_id ddr_test_cmd 0x18 a 0 0x80000 1 0 96 ");
+ printf("\n 0x19 test phy vref ddr_test_cmd 0x19 a 0 0x80000 1 seed step vref_all vref_lcdlr_offset test_down_up_step seed_hex_dec \
+ ddr_test_cmd 0x19 a 0 0x1000000 1 63 1 1 0x8 0 1 ");
+ printf("\n 0x1a test dram vref ddr_test_cmd 0x1A a 0 0x80000 clear seed step vref_all vref_lcdlr_offset test_down_up_step vref_range seed_hex_dec \
+ \n setenv ddr_test_ddr4ram_vref ddr_test_cmd 0x1A a 0 0x0800000 0 0x14 1 0 0x8 0 0 0 ; setenv storeboot run ddr_test_ddr4ram_vref ;save;reset ");
+ printf("\n 0x1b test ac vref ddr_test_cmd 0x1B a 0 0x80000 clear seed step vref_all vref_lcdlr_offset seed_hex_dec");
+ printf("\n 0x1c sweep dram clk use d2pll_env ddr_test_cmd 0x1c test_size start_freq end_freq test_loops ddr_test_cmd 0x1c 0x8000000 800 1500 1");
+ printf("\n 0x1d test shift clk ddr_test_cmd 0x1d type delay_ms times");
+ printf("\n 0x1e test write_read ddr_test_cmd 0x1e write_read pattern_id loop start_add test_size");
+ printf("\n 0x1f test pwm_cmd ddr_test_cmd 0x1f pwmid pwm_low pwm_high");
+ printf("\n 0x22 test ddr_window use env ddr_test_cmd 0x22 a 0 test_size watchdog_time \
+ lane_disable_masrk add_test_size setenv bootcmd ddr_test_cmd 0x22 a 0 0x800000 15 0 0x8000000");
+ printf("\n defenv;save;setenv bootcmd ddr_test_cmd 0x22 a 0 0x800000 18 0x0 0x8000000");
+ printf("\n setenv env_ddrtest_data_lane 0x22;save;reset");
+ printf("\n 0x23 test shift ddr frequency ddr_test_cmd 0x23");
+ printf("\n 0x24 display ddr_information ddr_test_cmd 0x24");
+ printf("\n 0x25 offset ddr_lcdlr ddr_test_cmd 0x25");
+ printf("\n 0x26 set watchdog_value ddr_test_cmd 0x26 30");
+ printf("\n 0x27 test ddr_window use sticky register ddr_test_cmd 0x27 a 0 test_size watchdog_time \
+ lane_disable_masrk add_test_size setenv bootcmd ddr_test_cmd 0x27 a 0 0x800000 15 0 0x8000000");
+ printf("\n 0x28 sweep dram clk use d2pll_sticky ddr_test_cmd 0x28 test_size start_freq end_freq test_loops ddr_test_cmd 0x28 0x8000000 800 1500 1");
+ }
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl);
+ //return 1;
+ break;
+
+
+ case (DDR_TEST_CMD__DDR_TEST):
+ {
+ do_ddr_test((cmd_tbl_t *)cmdtp, (int)flag, (int)argc2, (argv2));
+ break;
+ }
+ case (DDR_TEST_CMD__DDR_TUNE_ACLCDLR):
+ break;
+ case (DDR_TEST_CMD__DDR_DDR_TUNE_AC_CLK):
+ break;
+ case (DDR_TEST_CMD__DDR_TUNE_ZQ):
+ break;
+ case (DDR_TEST_CMD__DDR_GXTVBB_CROSSTALK):
+ break;
+ case (DDR_TEST_CMD__DDR_BANDWIDTH_TEST):
+ break;
+ case (DDR_TEST_CMD__DDR_LCDLR_ENV_TUNE):
+ break;
+ case (DDR_TEST_CMD__DDR_MODIFY_REG_USE_MASK):
+ break;
+ case (DDR_TEST_CMD__DDR_SETZQ):
+ break;
+
+ case (DDR_TEST_CMD__DDR_TUNE_DDR_DATA_WINDOW_STICKY):
+ break;
+ case (DDR_TEST_CMD__DDR4_TEST_DATA_WRTIE_READ):
+ {
+ printf("\ntest ddr write read \n");
+
+ do_ddr_test_write_read((cmd_tbl_t *)cmdtp, (int)flag, (int)argc2, (argv2));
+ }
+ break;
+ case (DDR_TEST_CMD__DDR_SET_UBOOT_G12_RECONFIG_CMD):
+ {
+ printf("\nset do_ddr_uboot_reconfig cmd\n");
+
+ do_ddr_uboot_new_cmd((cmd_tbl_t *)cmdtp, (int)flag, (int)argc2, (argv2));
+ }
+ break;
+
+ case (DDR_TEST_CMD__DISPLAY_G12_DDR_INFORMATION):
+ {
+ printf("\nshow g12 ddr information\n");
+ if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_C2) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T5D) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_S4)) {
+ do_ddr_display_c2_ddr_information((cmd_tbl_t *)cmdtp, (int)flag, (int)argc2, (argv2));
+ } else if ((p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_T7)) {
+ dmc_ddr_config_channel_id=0;
+ dmc_change_channel(dmc_ddr_config_channel_id);
+ do_ddr_display_g12_ddr_information((cmd_tbl_t *)cmdtp, (int)flag, (int)argc2, (argv2));
+ dmc_ddr_config_channel_id=1;
+ dmc_change_channel(dmc_ddr_config_channel_id);
+ do_ddr_display_g12_ddr_information((cmd_tbl_t *)cmdtp, (int)flag, (int)argc2, (argv2));
+ dmc_ddr_config_channel_id=0;
+ dmc_change_channel(dmc_ddr_config_channel_id);
+ } else {
+ do_ddr_display_g12_ddr_information((cmd_tbl_t *)cmdtp, (int)flag, (int)argc2, (argv2));
+ }
+ }
+ break;
+
+ case (DDR_TEST_CMD__DDR_G12_DMC_TEST):
+ break;
+ case (DDR_TEST_CMD__DDR_G12_EE_BDLR_TEST):
+ {
+ printf("\nUboot BDLR test \n");
+
+ do_ddr_test_pwm_bdlr((cmd_tbl_t *)cmdtp, (int)flag, (int)argc2, (argv2));
+ }
+ break;
+ }
+ writel(ddr_dmc_apd_temp_save, p_ddr_base->ddr_dmc_apd_address);
+ writel(ddr_dmc_asr_temp_save, p_ddr_base->ddr_dmc_asr_address);
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl);
+ return 1; //test_start_addr
+ }
+
+usage:
+ cmd_usage(cmdtp);
+ //wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl);
+ return 1;
+}
+
+U_BOOT_CMD(
+ ddr_test_cmd, 30, 1, do_ddr_test_cmd,
+ "ddr_test_cmd cmd arg1 arg2 arg3...",
+ "ddr_test_cmd cmd arg1 arg2 arg3... \n dcache off ? \n"
+ );
+
+int do_ddr_auto_test_window(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ check_base_address();
+ global_boot_times = rd_reg(p_ddr_base->preg_sticky_reg0);
+ printf("\nglobal_boot_times== %d\n", global_boot_times);
+
+ printf("\nargc== 0x%08x\n", argc);
+ printf("\nargc== 0x%08x\n", argc);
+ int i;
+ for (i = 0; i < argc; i++)
+ printf("\nargv[%d]=%s\n", i, argv[i]);
+
+ char str[1024] = "";
+ unsigned int ddr_test_cmd = 0;
+ unsigned int temp_reg_add = 0;
+ unsigned int num_arry[32] = { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 };
+
+ temp_reg_add = (((p_ddr_base->ddr_dmc_sticky0)));
+ for (i = 0; i < 32; i++) {
+ num_arry[i] = ddr_rd_8_16bit_on_32reg(temp_reg_add, 8, i);
+ if ((i == 0) || (i == 16))
+ printf("\n numarry[%d]", i);
+ printf(" %d ", num_arry[i]);
+ }
+
+ ddr_test_cmd = num_arry[0];
+
+ unsigned int cs0_test_start = 0x1080000;
+ unsigned int cs0_test_size = DDR_CORSS_TALK_TEST_SIZE;
+ unsigned int cs1_test_start = 0;
+ unsigned int cs1_test_size = 0;
+ unsigned int watchdog_time_s = 0;
+ unsigned int test_index_enable = 0;
+ unsigned int all_toghter_enable = 0;
+ cs0_test_start = ((num_arry[TEST_ARG_CS0_TEST_START_INDEX]) | ((num_arry[TEST_ARG_CS0_TEST_START_INDEX + 1]) << 8) |
+ ((num_arry[TEST_ARG_CS0_TEST_START_INDEX + 2]) << 16) | ((num_arry[TEST_ARG_CS0_TEST_START_INDEX + 3]) << 24));
+ cs0_test_size = ((num_arry[TEST_ARG_CS0_TEST_SIZE_INDEX]) | ((num_arry[TEST_ARG_CS0_TEST_SIZE_INDEX + 1]) << 8) |
+ ((num_arry[TEST_ARG_CS0_TEST_SIZE_INDEX + 2]) << 16) | ((num_arry[TEST_ARG_CS0_TEST_SIZE_INDEX + 3]) << 24));
+ cs1_test_start = ((num_arry[TEST_ARG_CS1_TEST_START_INDEX]) | ((num_arry[TEST_ARG_CS1_TEST_START_INDEX + 1]) << 8) |
+ ((num_arry[TEST_ARG_CS1_TEST_START_INDEX + 2]) << 16) | ((num_arry[TEST_ARG_CS1_TEST_START_INDEX + 3]) << 24));
+ cs1_test_size = ((num_arry[TEST_ARG_CS1_TEST_SIZE_INDEX]) | ((num_arry[TEST_ARG_CS1_TEST_SIZE_INDEX + 1]) << 8) |
+ ((num_arry[TEST_ARG_CS1_TEST_SIZE_INDEX + 2]) << 16) | ((num_arry[TEST_ARG_CS1_TEST_SIZE_INDEX + 3]) << 24));
+ watchdog_time_s = ((num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX]) | ((num_arry[TEST_ARG_WATCHDOG_TIME_SIZE_INDEX + 1]) << 8));
+ test_index_enable = ((num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX]) | ((num_arry[TEST_ARG_TEST_INDEX_ENALBE_INDEX + 1]) << 8));
+ all_toghter_enable = (num_arry[TEST_ARG_3_ALL_TOGHTER]);
+ switch (ddr_test_cmd) {
+ case (DMC_STICKY_UBOOT_WINDOW_MAGIC_1):
+ if (num_arry[1] == DMC_STICKY_UBOOT_WINDOW_MAGIC_1) {
+ sprintf(str, "ddr_test_cmd 0x27 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x \
+ 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x", cs0_test_start, cs0_test_size, cs1_test_start, cs1_test_size,
+ watchdog_time_s, test_index_enable, 0, 0, 0, 0, 0, 0, all_toghter_enable);
+
+ printf("\nstr=%s\n", str);
+
+ run_command(str, 0);
+ break;
+ }
+ }
+
+ return 1;
+}
+
+U_BOOT_CMD(
+ ddr_auto_test_window, 30, 1, do_ddr_auto_test_window,
+ "ddr_test_cmd cmd arg1 arg2 arg3...",
+ "ddr_test_cmd cmd arg1 arg2 arg3... \n dcache off ? \n"
+ );
+
+int do_ddr_auto_scan_drv(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ check_base_address();
+#define AUTO_SCAN_DDR3 0
+#define AUTO_SCAN_DDR4 1
+#define AUTO_SCAN_LPDDR3 2
+#define AUTO_SCAN_LPDDR4 3
+
+#define AUTO_SCAN_CONFIG_RANK0 0
+#define AUTO_SCAN_CONFIG_RANK01 1
+
+ char *string_print_flag = " window-loop \n";
+ global_boot_times = rd_reg((p_ddr_base->preg_sticky_reg0));
+
+ printf("\nargc== 0x%08x\n", argc);
+ printf("\nargc== 0x%08x\n", argc);
+ int i;
+ for (i = 0; i < argc; i++)
+ printf("\nargv[%d]=%s\n", i, argv[i]);
+
+ unsigned int ddr_type = 0;
+ unsigned int ddr_channel_rank_config = 0;
+ unsigned int loop = 0;
+ char *endp;
+ if (argc > 1) {
+ ddr_type = simple_strtoull_ddr(argv[1], &endp, 0);
+ if (*argv[1] == 0 || *endp != 0)
+ ddr_type = 0;
+ }
+ if (argc > 2) {
+ ddr_channel_rank_config = simple_strtoull_ddr(argv[2], &endp, 0);
+ if (*argv[2] == 0 || *endp != 0)
+ ddr_channel_rank_config = 0;
+ }
+ if (argc > 3) {
+ loop = simple_strtoull_ddr(argv[3], &endp, 0);
+ if (*argv[3] == 0 || *endp != 0)
+ loop = 0;
+ }
+ unsigned int temp_reg_add = 0;
+ {
+ temp_reg_add = (((p_ddr_base->ddr_dmc_sticky0)));
+ }
+
+ char str[1024] = "";
+
+ unsigned int counter_loop = 0;
+ unsigned int ddr_frequency = 0;
+ unsigned int soc_data_drv_ohm_p = 0; //74 //config soc data pin pull up driver stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned int soc_data_drv_ohm_n = 0; //76
+ unsigned int soc_data_odt_ohm_p = 0; //78 //config soc data pin odt pull up stength,select 0,28,30,32,34,37,40,43,48,53,60,68,80,96,120ohm
+ unsigned int soc_data_odt_ohm_n = 0; //80
+ unsigned int dram_data_drv_ohm = 0; //82 //config dram data pin pull up pull down driver stength,ddr3 select 34,40ohm,ddr4 select 34,48ohm,lpddr4 select 40,48,60,80,120,240ohm
+ unsigned int dram_data_odt_ohm = 0; //84 //config dram data pin odt pull up down stength,ddr3 select 40,60,120ohm,ddr4 select 34,40,48,60,120,240ohm,lpddr4 select 40,48,60,80,120,240ohm
+ unsigned int dram_data_wr_odt_ohm = 0; //174 char 1
+ i = 74 / 2;
+ soc_data_drv_ohm_p = ddr_rd_8_16bit_on_32reg(temp_reg_add, 16, i);
+ i = 76 / 2;
+ soc_data_drv_ohm_n = ddr_rd_8_16bit_on_32reg(temp_reg_add, 16, i);
+ i = 78 / 2;
+ soc_data_odt_ohm_p = ddr_rd_8_16bit_on_32reg(temp_reg_add, 16, i);
+ i = 80 / 2;
+ soc_data_odt_ohm_n = ddr_rd_8_16bit_on_32reg(temp_reg_add, 16, i);
+ i = 82 / 2;
+ dram_data_drv_ohm = ddr_rd_8_16bit_on_32reg(temp_reg_add, 16, i);
+ i = 84 / 2;
+ dram_data_odt_ohm = ddr_rd_8_16bit_on_32reg(temp_reg_add, 16, i);
+ i = 174 / 1;
+ dram_data_wr_odt_ohm = ddr_rd_8_16bit_on_32reg(temp_reg_add, 8, i);
+ i = 52 / 2;
+ ddr_frequency = ddr_rd_8_16bit_on_32reg(temp_reg_add, 16, i);
+ if (global_boot_times == 1) {
+ printf("\norg_global_boot_times== %d %s", global_boot_times, string_print_flag);
+ printf("\nsoc_data_drv_ohm_p=%d %s", soc_data_drv_ohm_p, string_print_flag);
+ printf("\nsoc_data_drv_ohm_n=%d %s", soc_data_drv_ohm_n, string_print_flag);
+ printf("\nsoc_data_odt_ohm_p=%d %s", soc_data_odt_ohm_p, string_print_flag);
+ printf("\nsoc_data_odt_ohm_n=%d %s", soc_data_odt_ohm_n, string_print_flag);
+ printf("\ndram_data_drv_ohm=%d %s", dram_data_drv_ohm, string_print_flag);
+ printf("\ndram_data_odt_ohm=%d %s", dram_data_odt_ohm, string_print_flag);
+ printf("\ndram_data_wr_odt_ohm=%d %s", dram_data_wr_odt_ohm, string_print_flag);
+ }
+ unsigned int soc_data_drv_ohm_p_t[] = { 34, 40, 48, 60 };
+
+ unsigned int dram_data_odt_ohm_t_ddr3[] = { 40, 60, 120 }; //ddr3
+ unsigned int dram_data_odt_ohm_t_ddr4[] = { 40, 48, 60, 120 }; //ddr4
+ unsigned int dram_data_odt_ohm_t_lpddr4[] = { 40, 48, 60, 120 }; //lpddr4
+
+ unsigned int dram_data_drv_ohm_t_ddr3[] = { 34, 40 }; //ddr3
+ unsigned int dram_data_drv_ohm_t_ddr4[] = { 34, 48 }; //ddr4
+ unsigned int dram_data_drv_ohm_t_lpddr4[] = { 40, 48, 60 }; //lpddr4
+
+ unsigned int soc_data_odt_ohm_p_t[] = { 40, 48, 60, 80, 120 };
+ unsigned int soc_data_odt_ohm_n_t[] = { 40, 48, 60, 80, 120 };
+
+ unsigned int dram_data_wr_odt_ohm_t_ddr3[] = { 60, 120, 0 }; //ddr3
+ unsigned int dram_data_wr_odt_ohm_t_ddr4[] = { 80, 120, 0 }; //ddr4
+
+ unsigned int *p_soc_data_drv_ohm_p = NULL;
+ unsigned int *p_soc_data_odt_ohm_p = NULL;
+ unsigned int *p_soc_data_odt_ohm_n = NULL;
+
+
+ unsigned int *p_dram_data_drv_ohm = NULL;
+ unsigned int *p_dram_data_odt_ohm = NULL;
+ unsigned int *p_dram_data_wr_odt_ohm = NULL;
+
+ p_soc_data_drv_ohm_p = soc_data_drv_ohm_p_t;
+ p_soc_data_odt_ohm_p = soc_data_odt_ohm_p_t;
+ p_soc_data_odt_ohm_n = soc_data_odt_ohm_n_t;
+
+
+ p_dram_data_drv_ohm = dram_data_drv_ohm_t_ddr3;
+ p_dram_data_odt_ohm = dram_data_odt_ohm_t_ddr3;
+ p_dram_data_wr_odt_ohm = dram_data_wr_odt_ohm_t_ddr3;
+
+ unsigned int max_counter_loop_w1 = (sizeof(soc_data_drv_ohm_p_t)) / (sizeof(soc_data_drv_ohm_p_t[0]));
+ unsigned int max_counter_loop_w2 = (sizeof(dram_data_odt_ohm_t_ddr3)) / (sizeof(dram_data_odt_ohm_t_ddr3[0]));
+ unsigned int max_counter_loop_r1 = (sizeof(dram_data_drv_ohm_t_ddr3)) / (sizeof(dram_data_drv_ohm_t_ddr3[0]));
+ unsigned int max_counter_loop_r2 = (sizeof(soc_data_odt_ohm_p_t)) / (sizeof(soc_data_odt_ohm_p_t[0]));
+ unsigned int max_counter_loop_wr1 = 1;
+ if (ddr_channel_rank_config)
+ max_counter_loop_wr1 = (sizeof(dram_data_wr_odt_ohm_t_ddr3)) / (sizeof(dram_data_wr_odt_ohm_t_ddr3[0]));
+ if (ddr_type == AUTO_SCAN_DDR4) {
+ p_dram_data_drv_ohm = dram_data_drv_ohm_t_ddr4;
+ p_dram_data_odt_ohm = dram_data_odt_ohm_t_ddr4;
+ p_dram_data_wr_odt_ohm = dram_data_wr_odt_ohm_t_ddr4;
+ max_counter_loop_w2 = (sizeof(dram_data_odt_ohm_t_ddr4)) / (sizeof(dram_data_odt_ohm_t_ddr4[0]));
+ max_counter_loop_r1 = (sizeof(dram_data_drv_ohm_t_ddr4)) / (sizeof(dram_data_drv_ohm_t_ddr4[0]));
+
+ if (ddr_channel_rank_config)
+ max_counter_loop_wr1 = (sizeof(dram_data_wr_odt_ohm_t_ddr4)) / (sizeof(dram_data_wr_odt_ohm_t_ddr4[0]));
+ }
+ if (ddr_type == AUTO_SCAN_LPDDR4) {
+ p_dram_data_drv_ohm = dram_data_drv_ohm_t_lpddr4;
+ p_dram_data_odt_ohm = dram_data_odt_ohm_t_lpddr4;
+ max_counter_loop_w2 = (sizeof(dram_data_odt_ohm_t_lpddr4)) / (sizeof(dram_data_odt_ohm_t_lpddr4[0]));
+ max_counter_loop_r1 = (sizeof(dram_data_drv_ohm_t_lpddr4)) / (sizeof(dram_data_drv_ohm_t_lpddr4[0]));
+ max_counter_loop_r2 = (sizeof(soc_data_odt_ohm_n_t)) / (sizeof(soc_data_odt_ohm_n_t[0]));
+
+ if (ddr_channel_rank_config)
+ max_counter_loop_wr1 = 1;
+ }
+
+ unsigned int max_counter_total = (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2) * max_counter_loop_wr1;
+ //add 2 times recover
+ //each arrary test 2 times ,for maybe 1times will fail,then next time will recovery //jiaxing 20181114
+ counter_loop = (((global_boot_times - 1) / 2) % max_counter_total);
+ dram_data_wr_odt_ohm = 0;
+ if (max_counter_loop_wr1 > 1)
+ dram_data_wr_odt_ohm = p_dram_data_wr_odt_ohm[(counter_loop / (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2))];
+ if ((counter_loop % (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2)) < (max_counter_loop_w1 * max_counter_loop_w2)) {
+ soc_data_drv_ohm_p = p_soc_data_drv_ohm_p[(((counter_loop % (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2))) % max_counter_loop_w1)];
+ soc_data_drv_ohm_n = soc_data_drv_ohm_p;
+ dram_data_odt_ohm = p_dram_data_odt_ohm[(((counter_loop % (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2))) / max_counter_loop_w1)];
+ } else if ((counter_loop % (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2)) == ((max_counter_loop_w1 * max_counter_loop_w2) + 0)) {
+ ddr_test_watchdog_reset_system();
+ } else if ((counter_loop % (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2)) < (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2 - 1)) {
+ dram_data_drv_ohm = p_dram_data_drv_ohm[((((counter_loop % (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2))) - (max_counter_loop_w1 * max_counter_loop_w2 + 1)) % max_counter_loop_r1)];
+ soc_data_odt_ohm_p = p_soc_data_odt_ohm_p[((((counter_loop % (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2))) - (max_counter_loop_w1 * max_counter_loop_w2 + 1)) / max_counter_loop_r1)];
+ soc_data_odt_ohm_n = 0;
+ if (ddr_type == CONFIG_DDR_TYPE_LPDDR4) {
+ soc_data_odt_ohm_p = 0;
+ soc_data_odt_ohm_n = p_soc_data_odt_ohm_n[((((counter_loop % (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2))) - (max_counter_loop_w1 * max_counter_loop_w2 + 1)) / max_counter_loop_r1)];
+ }
+ } else if ((counter_loop % (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2)) == (max_counter_loop_w1 * max_counter_loop_w2 + max_counter_loop_r1 * max_counter_loop_r2 + 2 - 1)) {
+ ddr_test_watchdog_reset_system();
+ }
+ printf("\nglobal_boot_times== %d %s", global_boot_times, string_print_flag);
+
+ if (loop) {
+ if (((global_boot_times - 1) / 2) > max_counter_total)
+ return 1;
+ }
+ printf("\nmax_counter=%d %d %s", max_counter_total, max_counter_total * 2, string_print_flag);
+ printf("\nsoc_data_drv_ohm_p=%d %s", soc_data_drv_ohm_p, string_print_flag);
+ printf("\nsoc_data_drv_ohm_n=%d %s", soc_data_drv_ohm_n, string_print_flag);
+ printf("\nsoc_data_odt_ohm_p=%d %s", soc_data_odt_ohm_p, string_print_flag);
+ printf("\nsoc_data_odt_ohm_n=%d %s", soc_data_odt_ohm_n, string_print_flag);
+ printf("\ndram_data_drv_ohm=%d %s", dram_data_drv_ohm, string_print_flag);
+ printf("\ndram_data_odt_ohm=%d %s", dram_data_odt_ohm, string_print_flag);
+ printf("\ndram_data_wr_odt_ohm=%d %s", dram_data_wr_odt_ohm, string_print_flag);
+ {
+ if (soc_data_drv_ohm_p) {
+ sprintf(str, "ddr_test_cmd 0x36 0x20180030 0x1 74 %d 2 0 ",
+ soc_data_drv_ohm_p);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ }
+ if (soc_data_drv_ohm_n) {
+ sprintf(str, "ddr_test_cmd 0x36 0x20180030 0x1 76 %d 2 0 ",
+ soc_data_drv_ohm_n);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ }
+ if (soc_data_odt_ohm_p) {
+ sprintf(str, "ddr_test_cmd 0x36 0x20180030 0x1 78 %d 2 0 ",
+ soc_data_odt_ohm_p);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ }
+ if (soc_data_odt_ohm_n) {
+ sprintf(str, "ddr_test_cmd 0x36 0x20180030 0x1 80 %d 2 0 ",
+ soc_data_odt_ohm_n);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ }
+ if (dram_data_drv_ohm) {
+ sprintf(str, "ddr_test_cmd 0x36 0x20180030 0x1 82 %d 2 0 ",
+ dram_data_drv_ohm);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ }
+ if (dram_data_odt_ohm) {
+ sprintf(str, "ddr_test_cmd 0x36 0x20180030 0x1 84 %d 2 0 ",
+ dram_data_odt_ohm);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ }
+ {
+ sprintf(str, "ddr_test_cmd 0x36 0x20180030 0x1 174 %d 1 0 ",
+ dram_data_wr_odt_ohm);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ }
+
+ sprintf(str, "g12_d2pll %d 0x12 0x6 0 0x0 0 0 0 0x800000 0 1 ", ddr_frequency);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ }
+
+ return 1;
+}
+
+unsigned char temp_sha2[SHA256_SUM_LEN];
+int do_verify_flash_ddr_parameter(char log_level)
+{
+ unsigned count = 0;
+ unsigned error = 0;
+
+ if (((p_ddr_base->chip_id >= MESON_CPU_MAJOR_ID_C2) && (p_ddr_base->chip_id <= MESON_CPU_MAJOR_ID_T5D)) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_S4)) {
+ char temp_buf[((sizeof(ddr_sha_t_c2) + 511) / 512) * 512] = { 0 };
+
+#ifdef USE_FOR_UBOOT_2018
+ extern int store_rsv_read(const char *name, size_t size, void *buf);
+
+ store_rsv_read("ddr-parameter", ((sizeof(ddr_sha_t_c2) + 511) / 512) * 512, (uint8_t *)(temp_buf));
+
+#else
+ extern int store_ddr_parameter_read(uint8_t *buffer, uint32_t length);
+
+ store_ddr_parameter_read((uint8_t *)(temp_buf), ((sizeof(ddr_sha_t_c2) + 511) / 512) * 512);
+#endif
+ char *s = temp_buf;
+ char *d = (char *)(&ddr_sha_c2);
+
+ for (count = 0; count < sizeof(ddr_sha_t_c2); count++) {
+ *d = *s;
+ s++;
+ d++;
+ }
+
+ for (count = 0; count < SHA256_SUM_LEN; count++)
+ ((temp_sha2[count]) = (ddr_sha_c2.sha2[count]));
+
+ sha256_csum_wd_internal((uint8_t *)(&(ddr_sha_c2.ddrs)), sizeof(ddr_set_t_c2), ddr_sha_c2.sha2, 0);
+
+ for (count = 0; count < SHA256_SUM_LEN; count++) {
+ if ((temp_sha2[count]) != (ddr_sha_c2.sha2[count]))
+ error++;
+
+ if (log_level == 0)
+ printf("\nread sha[%08x] %08x,calu %08x", count, (ddr_sha_c2.sha2[count]), (temp_sha2[count]));
+ }
+
+#define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1 << 30)
+ // if ((ddr_sha_c2.ddrs.cfg_board_common_setting.ddr_func) & DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID)
+ {
+ for (count = 0; count < MESON_CPU_CHIP_ID_SIZE; count++) {
+ if ((ddr_sha_c2.sha_chip_id[count]) != (global_chip_id[count]))
+ error++;
+
+ if (log_level == 0)
+ printf("\nglobal_chip_id[%08x] %08x,read %08x", count, (global_chip_id[count]), (ddr_sha_c2.sha_chip_id[count]));
+ }
+ }
+
+ return error;
+ }
+ char temp_buf[((sizeof(ddr_sha_t) + 511) / 512) * 512] = { 0 };
+
+#ifdef USE_FOR_UBOOT_2018
+ extern int store_rsv_read(const char *name, size_t size, void *buf);
+
+ store_rsv_read("ddr-parameter", ((sizeof(ddr_sha_t) + 511) / 512) * 512, (uint8_t *)(temp_buf));
+
+#else
+ extern int store_ddr_parameter_read(uint8_t *buffer, uint32_t length);
+
+ store_ddr_parameter_read((uint8_t *)(temp_buf), ((sizeof(ddr_sha_t) + 511) / 512) * 512);
+#endif
+ char *s = temp_buf;
+ char *d = (char *)(&ddr_sha);
+
+ for (count = 0; count < sizeof(ddr_sha_t); count++) {
+ *d = *s;
+ s++;
+ d++;
+ }
+
+ for (count = 0; count < SHA256_SUM_LEN; count++)
+ ((temp_sha2[count]) = (ddr_sha.sha2[count]));
+
+ sha256_csum_wd_internal((uint8_t *)(&(ddr_sha.ddrs)), sizeof(ddr_set_t), ddr_sha.sha2, 0);
+
+ for (count = 0; count < SHA256_SUM_LEN; count++) {
+ if ((temp_sha2[count]) != (ddr_sha.sha2[count]))
+ error++;
+
+ if (log_level == 0)
+ printf("\nread sha[%08x] %08x,calu %08x", count, (ddr_sha.sha2[count]), (temp_sha2[count]));
+ }
+
+#define DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID (1 << 30)
+
+ if ((ddr_sha.ddrs.ddr_func) & DDR_FUNC_FAST_BOOT_CHECK_CHIP_ID) {
+ for (count = 0; count < MESON_CPU_CHIP_ID_SIZE; count++) {
+ if ((ddr_sha.sha_chip_id[count]) != (global_chip_id[count]))
+ error++;
+
+ if (log_level == 0)
+ printf("\nglobal_chip_id[%08x] %08x,read %08x", count, (global_chip_id[count]), (ddr_sha.sha_chip_id[count]));
+ }
+ }
+ return error;
+} /* do_verify_flash_ddr_parameter */
+
+uint32_t enable_ddr_check_boot_reason = 0;
+uint32_t boot_reason = 0;
+#define HOT_BOOT_MAGIC 0x99887766
+#define HOT_BOOT_STICKY_ADD (p_ddr_base->preg_sticky_reg0 + (6 << 2))
+#define AMLOGIC_COLD_BOOT 0
+int do_ddr_auto_fastboot_check_c2(char auto_window_test_enable_item, uint32_t auto_window_test_dq_size, char pattern_dis_scramble, uint32_t stick_dmc_ddr_window_test_read_vref_offset_value, uint32_t skip_window_test_enable)
+{
+ uint32_t ddr_set_size = 0;
+ uint32_t need_ddr_window_test = 0;
+ char str[1024] = "";
+ int verify_error = 0;
+
+ verify_error = do_verify_flash_ddr_parameter(1);
+
+ if ((verify_error) == 0) {
+ if ((ddr_sha_c2.ddrs.cfg_board_common_setting.fast_boot[0]) == 0xff) {
+ printf("\nuboot auto fast boot check flash data is ok return \n");
+ return 1;
+ }
+ }
+ enable_ddr_check_boot_reason = 0;
+ enable_ddr_check_boot_reason = env_to_a_num("enable_ddr_check_boot_reason");
+ printf("\nenable_ddr_check_boot_reason==%d \n", enable_ddr_check_boot_reason);
+ printf("\nddr_fast_boot_enable_flag==%d \n", env_to_a_num("ddr_fast_boot_enable_flag"));
+ ddr_set_t_c2 *ddr_set_t_p = NULL;
+ ddr_set_t_p = (ddr_set_t_c2 *)(ddr_set_t_p_arrary_c2);
+ uint32_t ddr_set_add = 0;
+
+ ddr_set_add = (uint32_t)(uint64_t)(ddr_set_t_p);
+ ddr_set_size = sizeof(ddr_set_t_c2);
+ printf("\nddr_set_t_p==0x%08x\n", ddr_set_add);
+
+ uint32_t dmc_retraining_ctrl = 0;
+ dmc_retraining_ctrl = rd_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address));
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl & (~(1 << 31)));
+ uint32_t write_size = 0;
+ write_size = ((ddr_set_size + SHA256_SUM_LEN + MESON_CPU_CHIP_ID_SIZE + 511) / 512) * 512;
+ do_read_c2_ddr_training_data(1, ddr_set_t_p);
+
+ if (((ddr_set_t_p->cfg_board_common_setting.fast_boot[3]) & 0xc0) && ((ddr_set_t_p->cfg_board_common_setting.fast_boot[3]) & 0x3f)) {
+ enable_ddr_check_boot_reason = 0;
+
+ if (((ddr_set_t_p->cfg_board_common_setting.fast_boot[0]) > 0) && ((ddr_set_t_p->cfg_board_common_setting.fast_boot[0]) < 0xff)) {
+ (ddr_set_t_p->cfg_board_common_setting.fast_boot[0]) = 0xfe;
+ (verify_error) = 0;
+ }
+ }
+
+ if ((ddr_set_t_p->cfg_board_common_setting.fast_boot[0])) {
+ printf("\nuboot enable auto fast boot funciton \n");
+
+ if ((verify_error)) {
+ printf("\nuboot auto fast boot check verify data happen wrong \n");
+ (ddr_set_t_p->cfg_board_common_setting.fast_boot[0]) = 1;
+ }
+ } else {
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl);
+ return 1;
+ }
+
+ if (enable_ddr_check_boot_reason) {
+ boot_reason = 0; //ddr_set_t_p->boot_reason
+ {
+ if ((((readl(p_ddr_base->ddr_boot_reason_address) >> 0) & 0xf) == AMLOGIC_COLD_BOOT) && ((rd_reg(HOT_BOOT_STICKY_ADD)) == HOT_BOOT_MAGIC))
+ boot_reason = 1;
+
+ if (ddr_set_t_p->cfg_board_common_setting.fast_boot[0] == 0xfe)
+ boot_reason = 2;
+ }
+ printf("\nboot_reason=%08x \n", (boot_reason));
+ printf("\nHOT_BOOT_STICKY_ADD=%08x \n", (rd_reg(HOT_BOOT_STICKY_ADD)));
+ wr_reg(HOT_BOOT_STICKY_ADD, HOT_BOOT_MAGIC);
+ printf("\nHOT_BOOT_STICKY_ADD=%08x \n", (rd_reg(HOT_BOOT_STICKY_ADD)));
+
+ if (boot_reason == 0) {
+ if ((ddr_set_t_p->cfg_board_common_setting.fast_boot[0]) < 0xfe) {
+ need_ddr_window_test = 1;
+ sprintf(str, "setenv initargs ${initargs} need_ddr_window_test=%d", need_ddr_window_test);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ sprintf(str, "setenv bootargs ${bootargs} need_ddr_window_test=%d", need_ddr_window_test);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ } else {
+ sprintf(str, "setenv initargs ${initargs} need_ddr_window_test=%d", need_ddr_window_test);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ sprintf(str, "setenv bootargs ${bootargs} need_ddr_window_test=%d", need_ddr_window_test);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ }
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl);
+ return 1;
+ } else {
+ sprintf(str, "setenv initargs ${initargs} need_ddr_window_test=%d", need_ddr_window_test);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ sprintf(str, "setenv bootargs ${bootargs} need_ddr_window_test=%d", need_ddr_window_test);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ }
+ }
+
+ if ((ddr_set_t_p->cfg_board_common_setting.fast_boot[0]) == 0xff) {
+ printf("\nuboot auto fast boot auto window test is done \n");
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl);
+ return 1;
+ }
+
+ if (skip_window_test_enable) {
+ printf("enable skip window test fast boot mode! \n");
+ ddr_set_t_p->cfg_board_common_setting.fast_boot[0] = 0xfe;
+ }
+ printf("\n(ddr_set_t_p->cfg_board_common_setting.fast_boot[0])==0x%08x\n", (ddr_set_t_p->cfg_board_common_setting.fast_boot[0]));
+
+ if ((ddr_set_t_p->cfg_board_common_setting.fast_boot[0]) < 0xfe) {
+ printf("\nuboot auto fast boot auto window test begin \n");
+ {
+ ddr_set_t_p->cfg_board_common_setting.fast_boot[0] = 0xfd; //0xfd for check unexcept power off status
+ sha256_csum_wd_internal((unsigned char *)(uint64_t)ddr_set_add, sizeof(ddr_set_t_c2), ddr_sha_c2.sha2, 0);
+ write_size = ((ddr_set_size + SHA256_SUM_LEN + MESON_CPU_CHIP_ID_SIZE + 511) / 512) * 512;
+ {
+ ddr_do_store_ddr_parameter_ops((uint8_t *)(unsigned long)(ddr_set_add - SHA256_SUM_LEN), write_size);
+ }
+ sprintf(str, "g12_d2pll %d 0x11 %d 0 0 0 0 %d 0x%08x 0 %d", ddr_set_t_p->cfg_board_SI_setting_ps[0].DRAMFreq, auto_window_test_enable_item, stick_dmc_ddr_window_test_read_vref_offset_value, auto_window_test_dq_size, pattern_dis_scramble);
+ printf("\nstr=%s\n", str);
+
+ run_command(str, 0);
+ }
+ return 1;
+ }
+
+ if ((ddr_set_t_p->cfg_board_common_setting.fast_boot[0]) == 0xfe) {
+#if 0
+ char dmc_test_worst_window_rx = 0;
+ char dmc_test_worst_window_tx = 0;
+
+ {
+ dwc_ddrphy_apb_wr((0 << 20) | (0xd << 16) | (0 << 12) | (0x0), 0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+
+ dmc_test_worst_window_tx = dwc_ddrphy_apb_rd((0 << 20) | (1 << 16) | (0 << 12) | (0x0c2));
+ dmc_test_worst_window_rx = dwc_ddrphy_apb_rd((0 << 20) | (1 << 16) | (0 << 12) | (0x0c3));
+ printf("\ndmc_test_worst_window_tx =%d \n", dmc_test_worst_window_tx);
+ printf("\ndmc_test_worst_window_rx=%d \n", dmc_test_worst_window_rx);
+
+ if (dmc_test_worst_window_tx > 30)
+ dmc_test_worst_window_tx = 30;
+
+ if (dmc_test_worst_window_rx > 30)
+ dmc_test_worst_window_rx = 30;
+ ddr_set_t_p->fast_boot[1] = (((dmc_test_worst_window_tx / 2) << 4)) | (((dmc_test_worst_window_rx / 2)));
+ }
+#endif
+ ddr_set_t_p->cfg_board_common_setting.fast_boot[0] = 0xff;
+ {
+ printf("\nuboot auto fast boot auto window test finish \n");
+
+ if (ddr_set_t_p->cfg_board_common_setting.fast_boot[2]) {
+ if ((ddr_set_t_p->cfg_board_common_setting.fast_boot[2]) & 0x7) {
+ if (((ddr_set_t_p->cfg_board_common_setting.fast_boot[2]) & 0x8))
+ sprintf(str, "ddr_g12_offset_data 3 0x0 0 0 1 %d ", (ddr_set_t_p->cfg_board_common_setting.fast_boot[2]) & 0x7);
+ else
+ sprintf(str, "ddr_g12_offset_data 3 0x0 0 0 2 %d ", (ddr_set_t_p->cfg_board_common_setting.fast_boot[2]) & 0x7);
+ printf("\nstr=%s\n", str);
+
+ run_command(str, 0);
+ }
+
+ if ((ddr_set_t_p->cfg_board_common_setting.fast_boot[2]) & 0x70) {
+ if (((ddr_set_t_p->cfg_board_common_setting.fast_boot[2]) & 0x80))
+ sprintf(str, "ddr_g12_offset_data 2 0x0 0 0 1 %d ", ((ddr_set_t_p->cfg_board_common_setting.fast_boot[2]) >> 4) & 0x7);
+ else
+ sprintf(str, "ddr_g12_offset_data 2 0x0 0 0 2 %d ", ((ddr_set_t_p->cfg_board_common_setting.fast_boot[2]) >> 4) & 0x7);
+ printf("\nstr=%s\n", str);
+
+ run_command(str, 0);
+ }
+ sprintf(str, "ddr_fast_boot 1 ");
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ } else {
+ sha256_csum_wd_internal((unsigned char *)(uint64_t)ddr_set_add, sizeof(ddr_set_t_c2), ddr_sha_c2.sha2, 0);
+ ddr_do_store_ddr_parameter_ops((uint8_t *)(unsigned long)(ddr_set_add - SHA256_SUM_LEN), write_size);
+ }
+
+ if ((enable_ddr_check_boot_reason)) {
+ if (boot_reason) {
+ sprintf(str, "systemoff");
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ }
+ }
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl);
+ return 1;
+ }
+ }
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl);
+ return 1;
+} /* do_ddr_auto_fastboot_check_c2 */
+
+int do_ddr_auto_fastboot_check(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ check_base_address();
+#define DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT (1 << 5)
+#define AUTO_WINDOW_TEST_ENABLE_ITEM ((1 << 1) | (1 << 2))
+ char *endp;
+ char auto_window_test_enable_item = DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT;
+ uint32_t auto_window_test_dq_size = 0;
+ char pattern_dis_scramble = 0;
+ uint32_t stick_dmc_ddr_window_test_read_vref_offset_value = 0;
+ uint32_t ddr_set_size = 0;
+ uint32_t need_ddr_window_test = 0;
+ uint32_t skip_window_test_enable = 0;
+ if (argc > 1) {
+ auto_window_test_enable_item = simple_strtoull_ddr(argv[1], &endp, 0);
+ if (*argv[1] == 0 || *endp != 0)
+ auto_window_test_enable_item = DMC_TEST_SLT_ENABLE_DDR_AUTO_FAST_BOOT;
+ }
+ if (argc > 2) {
+ auto_window_test_dq_size = simple_strtoull_ddr(argv[2], &endp, 0);
+ if (*argv[2] == 0 || *endp != 0)
+ auto_window_test_dq_size = 0;
+ }
+ if (argc > 3) {
+ pattern_dis_scramble = simple_strtoull_ddr(argv[3], &endp, 0);
+ if (*argv[3] == 0 || *endp != 0)
+ pattern_dis_scramble = 0;
+ }
+ if (argc > 4) {
+ stick_dmc_ddr_window_test_read_vref_offset_value = simple_strtoull_ddr(argv[4], &endp, 0);
+ if (*argv[4] == 0 || *endp != 0)
+ stick_dmc_ddr_window_test_read_vref_offset_value = 0;
+ }
+ if (argc > 5) {
+ skip_window_test_enable = simple_strtoull_ddr(argv[5], &endp, 0);
+ if (*argv[5] == 0 || *endp != 0)
+ skip_window_test_enable = 0;
+ }
+ if (((p_ddr_base->chip_id >= MESON_CPU_MAJOR_ID_C2) && (p_ddr_base->chip_id <= MESON_CPU_MAJOR_ID_T5D)) || (p_ddr_base->chip_id == MESON_CPU_MAJOR_ID_S4)) {
+ do_ddr_auto_fastboot_check_c2(auto_window_test_enable_item, auto_window_test_dq_size, pattern_dis_scramble, stick_dmc_ddr_window_test_read_vref_offset_value, skip_window_test_enable);
+ return 1;
+ }
+ char str[1024] = "";
+ int verify_error = 0;
+ verify_error = do_verify_flash_ddr_parameter(1);
+ if ((verify_error) == 0) {
+ if ((ddr_sha.ddrs.fast_boot[0]) == 0xff) {
+ printf("\nuboot auto fast boot check flash data is ok return \n");
+ return 1;
+ }
+ }
+ enable_ddr_check_boot_reason = 0;
+ enable_ddr_check_boot_reason = env_to_a_num("enable_ddr_check_boot_reason");
+ printf("\nenable_ddr_check_boot_reason==%d \n", enable_ddr_check_boot_reason);
+ printf("\nddr_fast_boot_enable_flag==%d \n", env_to_a_num("ddr_fast_boot_enable_flag"));
+ ddr_set_t *ddr_set_t_p = NULL;
+ ddr_set_t_p = (ddr_set_t *)(ddr_set_t_p_arrary);
+ uint32_t ddr_set_add = 0;
+
+ ddr_set_add = (uint32_t)(uint64_t)(ddr_set_t_p);
+ ddr_set_size = sizeof(ddr_set_t);
+ printf("\nddr_set_t_p==0x%08x\n", ddr_set_add);
+
+ uint32_t dmc_retraining_ctrl = 0;
+ dmc_retraining_ctrl = rd_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address));
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl & (~(1 << 31)));
+ uint32_t write_size = 0;
+ write_size = ((ddr_set_size + SHA256_SUM_LEN + MESON_CPU_CHIP_ID_SIZE + 511) / 512) * 512;
+ do_read_ddr_training_data(1, ddr_set_t_p);
+ if (((ddr_set_t_p->fast_boot[3]) & 0xc0) && ((ddr_set_t_p->fast_boot[3]) & 0x3f)) {
+ enable_ddr_check_boot_reason = 0;
+ if (((ddr_set_t_p->fast_boot[0]) > 0) && ((ddr_set_t_p->fast_boot[0]) < 0xff)) {
+ (ddr_set_t_p->fast_boot[0]) = 0xfe;
+ (verify_error) = 0;
+ }
+ }
+ if ((ddr_set_t_p->fast_boot[0])) {
+ printf("\nuboot enable auto fast boot funciton \n");
+ if ((verify_error)) {
+ printf("\nuboot auto fast boot check verify data happen wrong \n");
+ (ddr_set_t_p->fast_boot[0]) = 1;
+ }
+ } else {
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl);
+ return 1;
+ }
+
+ if (enable_ddr_check_boot_reason) {
+ boot_reason = 0; //ddr_set_t_p->boot_reason
+ {
+ if ((((readl(p_ddr_base->ddr_boot_reason_address) >> 12) & 0xf) == AMLOGIC_COLD_BOOT) && ((rd_reg(HOT_BOOT_STICKY_ADD)) == HOT_BOOT_MAGIC))
+ boot_reason = 1;
+ if (ddr_set_t_p->fast_boot[0] == 0xfe)
+ boot_reason = 2;
+ }
+ printf("\nboot_reason=%08x \n", (boot_reason));
+ printf("\nHOT_BOOT_STICKY_ADD=%08x \n", (rd_reg(HOT_BOOT_STICKY_ADD)));
+ wr_reg(HOT_BOOT_STICKY_ADD, HOT_BOOT_MAGIC);
+ printf("\nHOT_BOOT_STICKY_ADD=%08x \n", (rd_reg(HOT_BOOT_STICKY_ADD)));
+
+ if (boot_reason == 0) {
+ if ((ddr_set_t_p->fast_boot[0]) < 0xfe) {
+ need_ddr_window_test = 1;
+ sprintf(str, "setenv initargs ${initargs} need_ddr_window_test=%d", need_ddr_window_test);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ sprintf(str, "setenv bootargs ${bootargs} need_ddr_window_test=%d", need_ddr_window_test);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ } else {
+ sprintf(str, "setenv initargs ${initargs} need_ddr_window_test=%d", need_ddr_window_test);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ sprintf(str, "setenv bootargs ${bootargs} need_ddr_window_test=%d", need_ddr_window_test);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ }
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl);
+ return 1;
+ } else {
+ sprintf(str, "setenv initargs ${initargs} need_ddr_window_test=%d", need_ddr_window_test);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ sprintf(str, "setenv bootargs ${bootargs} need_ddr_window_test=%d", need_ddr_window_test);
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ }
+ }
+ if ((ddr_set_t_p->fast_boot[0]) == 0xff) {
+ printf("\nuboot auto fast boot auto window test is done \n");
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl);
+ return 1;
+ }
+ if (skip_window_test_enable) {
+ printf("enable skip window test fast boot mode! \n");
+ ddr_set_t_p->fast_boot[0] = 0xfe;
+ }
+ printf("\n(ddr_set_t_p->fast_boot[0])==0x%08x\n", (ddr_set_t_p->fast_boot[0]));
+
+ if ((ddr_set_t_p->fast_boot[0]) < 0xfe) {
+ printf("\nuboot auto fast boot auto window test begin \n");
+ {
+ ddr_set_t_p->fast_boot[0] = 0xfd; //0xfd for check unexcept power off status
+ sha256_csum_wd_internal((unsigned char *)(uint64_t)ddr_set_add, sizeof(ddr_set_t), ddr_sha.sha2, 0);
+ write_size = ((ddr_set_size + SHA256_SUM_LEN + MESON_CPU_CHIP_ID_SIZE + 511) / 512) * 512;
+ {
+ ddr_do_store_ddr_parameter_ops((uint8_t *)(unsigned long)(ddr_set_add - SHA256_SUM_LEN), write_size);
+ }
+ sprintf(str, "g12_d2pll %d 0x11 %d 0 0 0 0 %d 0x%08x 0 %d", ddr_set_t_p->DRAMFreq[0], auto_window_test_enable_item, stick_dmc_ddr_window_test_read_vref_offset_value, auto_window_test_dq_size, pattern_dis_scramble);
+ printf("\nstr=%s\n", str);
+
+ run_command(str, 0);
+ }
+ return 1;
+ }
+
+ if ((ddr_set_t_p->fast_boot[0]) == 0xfe) {
+ char dmc_test_worst_window_rx = 0;
+ char dmc_test_worst_window_tx = 0;
+
+ {
+ dwc_ddrphy_apb_wr((0 << 20) | (0xd << 16) | (0 << 12) | (0x0), 0); // DWC_DDRPHYA_APBONLY0_MicroContMuxSel
+
+ dmc_test_worst_window_tx = dwc_ddrphy_apb_rd((0 << 20) | (1 << 16) | (0 << 12) | (0x0c2));
+ dmc_test_worst_window_rx = dwc_ddrphy_apb_rd((0 << 20) | (1 << 16) | (0 << 12) | (0x0c3));
+ printf("\ndmc_test_worst_window_tx =%d \n", dmc_test_worst_window_tx);
+ printf("\ndmc_test_worst_window_rx=%d \n", dmc_test_worst_window_rx);
+ if (dmc_test_worst_window_tx > 30)
+ dmc_test_worst_window_tx = 30;
+ if (dmc_test_worst_window_rx > 30)
+ dmc_test_worst_window_rx = 30;
+ ddr_set_t_p->fast_boot[1] = (((dmc_test_worst_window_tx / 2) << 4)) | (((dmc_test_worst_window_rx / 2)));
+ }
+
+ ddr_set_t_p->fast_boot[0] = 0xff;
+ {
+ printf("\nuboot auto fast boot auto window test finish \n");
+
+ if (ddr_set_t_p->fast_boot[2]) {
+ if ((ddr_set_t_p->fast_boot[2]) & 0x7) {
+ if (((ddr_set_t_p->fast_boot[2]) & 0x8))
+ sprintf(str, "ddr_g12_offset_data 3 0x0 0 0 1 %d ", (ddr_set_t_p->fast_boot[2]) & 0x7);
+ else
+ sprintf(str, "ddr_g12_offset_data 3 0x0 0 0 2 %d ", (ddr_set_t_p->fast_boot[2]) & 0x7);
+
+ printf("\nstr=%s\n", str);
+
+ run_command(str, 0);
+ }
+ if ((ddr_set_t_p->fast_boot[2]) & 0x70) {
+ if (((ddr_set_t_p->fast_boot[2]) & 0x80))
+ sprintf(str, "ddr_g12_offset_data 2 0x0 0 0 1 %d ", ((ddr_set_t_p->fast_boot[2]) >> 4) & 0x7);
+ else
+ sprintf(str, "ddr_g12_offset_data 2 0x0 0 0 2 %d ", ((ddr_set_t_p->fast_boot[2]) >> 4) & 0x7);
+
+ printf("\nstr=%s\n", str);
+
+ run_command(str, 0);
+ }
+
+ sprintf(str, "ddr_fast_boot 1 ");
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ } else {
+ sha256_csum_wd_internal((unsigned char *)(uint64_t)ddr_set_add, sizeof(ddr_set_t), ddr_sha.sha2, 0);
+ ddr_do_store_ddr_parameter_ops((uint8_t *)(unsigned long)(ddr_set_add - SHA256_SUM_LEN), write_size);
+ }
+ if ((enable_ddr_check_boot_reason)) {
+ if (boot_reason) {
+ sprintf(str, "systemoff");
+ printf("\nstr=%s\n", str);
+ run_command(str, 0);
+ }
+ }
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl);
+ return 1;
+ }
+ }
+ wr_reg((p_ddr_base->ddr_dmc_lpdd4_retraining_address), dmc_retraining_ctrl);
+ return 1;
+}
+
+U_BOOT_CMD(
+ ddr_auto_scan_drv, 30, 1, do_ddr_auto_scan_drv,
+ "ddr_test_cmd cmd arg1 arg2 arg3...",
+ "ddr_test_cmd cmd arg1 arg2 arg3... \n dcache off ? \n"
+ );
+
+U_BOOT_CMD(
+ ddr_fast_boot, 30, 1, do_ddr_fastboot_config,
+ "ddr_fastboot_config cmd arg1 arg2 arg3...",
+ "ddr_fastboot_config cmd arg1 arg2 arg3... \n dcache off ? \n"
+ );
+
+U_BOOT_CMD(
+ ddr_auto_fast_boot_check, 30, 1, do_ddr_auto_fastboot_check,
+ "ddr_fastboot_config cmd arg1 arg2 arg3...",
+ "ddr_fastboot_config cmd arg1 arg2 arg3... \n dcache off ? \n"
+ );
diff --git a/cmd/amlogic/cmd_dolbyvision.c b/cmd/amlogic/cmd_dolbyvision.c
new file mode 100644
index 0000000..009cc26
--- /dev/null
+++ b/cmd/amlogic/cmd_dolbyvision.c
@@ -0,0 +1,118 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <malloc.h>
+#include <asm/byteorder.h>
+#include <amlogic/media/dv/dolby_vision.h>
+
+static int do_dolbyvision_process(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ dolby_vision_process();
+ return 1;
+}
+
+static int do_dolbyvision_set(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ apply_stb_core_settings();
+ return 1;
+}
+
+static int do_hdmi_package(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ send_hdmi_pkt();
+ return 1;
+}
+
+static int do_read_reg(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned long tmp_addr = 0;
+
+ tmp_addr = simple_strtoul(argv[1], NULL, 16);
+ dv_read_reg((unsigned int)tmp_addr);
+ printf("addr:%lx, value: %x\n", tmp_addr,
+ dv_read_reg((unsigned int)tmp_addr));
+ return 1;
+}
+
+static int do_write_reg(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned long tmp_addr = 0;
+ unsigned long tmp_value = 0;
+
+ tmp_addr = simple_strtoul(argv[1], NULL, 16);
+ tmp_value = simple_strtoul(argv[2], NULL, 16);
+ dv_write_reg((unsigned int)tmp_addr,(unsigned int)tmp_value);
+ printf("addr:%lx, value: %x\n", tmp_addr,
+ dv_read_reg((unsigned int)tmp_addr));
+ return 1;
+}
+
+static int do_dolbyvision_debug(cmd_tbl_t *cmdtp, int flag, int argc,
+ char *const argv[])
+{
+ int ret = 0;
+ unsigned long value = 0;
+
+ if (argc == 2) {
+ value = simple_strtoul(argv[1], NULL, 16);
+ switch (value) {
+ case 0:
+ dolbyvision_debug(0);
+ break;
+ case 1:
+ dolbyvision_debug(1);
+ break;
+ case 2:
+ dolbyvision_dump_setting();
+ break;
+ default:
+ cmd_usage(cmdtp);
+ break;
+ }
+ } else {
+ return cmd_usage(cmdtp);
+ }
+
+ return ret;
+}
+
+static cmd_tbl_t cmd_dovi_sub[] = {
+ U_BOOT_CMD_MKENT(process, 1, 1, do_dolbyvision_process, "", ""),
+ U_BOOT_CMD_MKENT(pkg, 1, 1, do_hdmi_package, "", ""),
+ U_BOOT_CMD_MKENT(set, 1, 1, do_dolbyvision_set, "", ""),
+ U_BOOT_CMD_MKENT(rv, 2, 1, do_read_reg, "", ""),
+ U_BOOT_CMD_MKENT(wv, 3, 1, do_write_reg, "", ""),
+ U_BOOT_CMD_MKENT(debug, 2, 0, do_dolbyvision_debug, "", ""),
+};
+
+static int do_dolby_vision(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ cmd_tbl_t *c;
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ argc--;
+ argv++;
+
+ c = find_cmd_tbl(argv[0], &cmd_dovi_sub[0], ARRAY_SIZE(cmd_dovi_sub));
+
+ if (c)
+ return c->cmd(cmdtp, flag, argc, argv);
+ else
+ return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(dovi, CONFIG_SYS_MAXARGS, 0, do_dolby_vision,
+ "Dolby_vision sub-system",
+ "set------------ apply core settings \n"
+ "dovi pkg--------------send hdmi pkt\n"
+ "dovi rv---------------Dolby_vision read registers\n"
+ "dovi wv---------------Dolby_vision write registers\n"
+ "dovi debug------------0: disable debug; 1:enable debug; 2: dump setting\n"
+);
diff --git a/cmd/amlogic/cmd_dynamic.c b/cmd/amlogic/cmd_dynamic.c
new file mode 100644
index 0000000..f650cb5
--- /dev/null
+++ b/cmd/amlogic/cmd_dynamic.c
@@ -0,0 +1,673 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <malloc.h>
+#include <asm/byteorder.h>
+#include <config.h>
+#include <asm/arch/io.h>
+#include <emmc_partitions.h>
+#include <partition_table.h>
+#include <version.h>
+#include <amlogic/storage.h>
+
+#ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK
+
+/* Magic signature for LpMetadataGeometry. */
+#define LP_METADATA_GEOMETRY_MAGIC 0x616c4467
+
+/* Space reserved for geometry information. */
+#define LP_METADATA_GEOMETRY_SIZE 4096
+
+#define LP_METADATA_HEADER_SIZE 124
+
+#define SUPERBUF_SIZE 16384
+
+/* Magic signature for LpMetadataHeader. */
+#define LP_METADATA_HEADER_MAGIC 0x414C5030
+
+/* Current metadata version. */
+#define LP_METADATA_MAJOR_VERSION 10
+#define LP_METADATA_MINOR_VERSION_MIN 0
+#define LP_METADATA_MINOR_VERSION_MAX 2
+
+/* Attributes for the LpMetadataPartition::attributes field.
+ *
+ * READONLY - The partition should not be considered writable. When used with
+ * device mapper, the block device will be created as read-only.
+ */
+#define LP_PARTITION_ATTR_NONE 0x0
+#define LP_PARTITION_ATTR_READONLY (1 << 0)
+
+/* This flag is only intended to be used with super_empty.img and super.img on
+ * retrofit devices. On these devices there are A and B super partitions, and
+ * we don't know ahead of time which slot the image will be applied to.
+ *
+ * If set, the partition name needs a slot suffix applied. The slot suffix is
+ * determined by the metadata slot number (0 = _a, 1 = _b).
+ */
+#define LP_PARTITION_ATTR_SLOT_SUFFIXED (1 << 1)
+
+/* Mask that defines all valid attributes. */
+#define LP_PARTITION_ATTRIBUTE_MASK (LP_PARTITION_ATTR_READONLY | LP_PARTITION_ATTR_SLOT_SUFFIXED)
+
+/* Default name of the physical partition that holds logical partition entries.
+ * The layout of this partition will look like:
+ *
+ * +--------------------+
+ * | Disk Geometry |
+ * +--------------------+
+ * | Geometry Backup |
+ * +--------------------+
+ * | Metadata |
+ * +--------------------+
+ * | Backup Metadata |
+ * +--------------------+
+ * | Logical Partitions |
+ * +--------------------+
+ */
+#define LP_METADATA_DEFAULT_PARTITION_NAME "super"
+
+/* Size of a sector is always 512 bytes for compatibility with the Linux kernel. */
+#define LP_SECTOR_SIZE 512
+
+/* Amount of space reserved at the start of every super partition to avoid
+ * creating an accidental boot sector.
+ */
+#define LP_PARTITION_RESERVED_BYTES 4096
+
+/* This structure is stored at block 0 in the first 4096 bytes of the
+ * partition, and again in the following block. It is never modified and
+ * describes how logical partition information can be located.
+ */
+typedef struct LpMetadataGeometry {
+ /* 0: Magic signature (LP_METADATA_GEOMETRY_MAGIC). */
+ uint32_t magic;
+
+ /* 4: Size of the LpMetadataGeometry struct. */
+ uint32_t struct_size;
+
+ /* 8: SHA256 checksum of this struct, with this field set to 0. */
+ uint8_t checksum[32];
+
+ /* 40: Maximum amount of space a single copy of the metadata can use. This
+ * must be a multiple of LP_SECTOR_SIZE.
+ */
+ uint32_t metadata_max_size;
+
+ /* 44: Number of copies of the metadata to keep. For A/B devices, this
+ * will be 2. For an A/B/C device, it would be 3, et cetera. For Non-A/B
+ * it will be 1. A backup copy of each slot is kept, so if this is "2",
+ * there will be four copies total.
+ */
+ uint32_t metadata_slot_count;
+
+ /* 48: Logical block size. This is the minimal alignment for partition and
+ * extent sizes, and it must be a multiple of LP_SECTOR_SIZE. Note that
+ * this must be equal across all LUNs that comprise the super partition,
+ * and thus this field is stored in the geometry, not per-device.
+ */
+ uint32_t logical_block_size;
+} __attribute__((packed)) LpMetadataGeometry;
+
+/* The logical partition metadata has a number of tables; they are described
+ * in the header via the following structure.
+ *
+ * The size of the table can be computed by multiplying entry_size by
+ * num_entries, and the result must not overflow a 32-bit signed integer.
+ */
+typedef struct LpMetadataTableDescriptor {
+ /* 0: Location of the table, relative to end of the metadata header. */
+ uint32_t offset;
+ /* 4: Number of entries in the table. */
+ uint32_t num_entries;
+ /* 8: Size of each entry in the table, in bytes. */
+ uint32_t entry_size;
+} __attribute__((packed)) LpMetadataTableDescriptor;
+
+/* Binary format for the header of the logical partition metadata format.
+ *
+ * The format has three sections. The header must occur first, and the
+ * proceeding tables may be placed in any order after.
+ *
+ * +-----------------------------------------+
+ * | Header data - fixed size |
+ * +-----------------------------------------+
+ * | Partition table - variable size |
+ * +-----------------------------------------+
+ * | Partition table extents - variable size |
+ * +-----------------------------------------+
+ *
+ * The "Header" portion is described by LpMetadataHeader. It will always
+ * precede the other three blocks.
+ *
+ * All fields are stored in little-endian byte order when serialized.
+ *
+ * This struct is versioned; see the |major_version| and |minor_version|
+ * fields.
+ */
+typedef struct LpMetadataHeader {
+ /* 0: Four bytes equal to LP_METADATA_HEADER_MAGIC. */
+ uint32_t magic;
+
+ /* 4: Version number required to read this metadata. If the version is not
+ * equal to the library version, the metadata should be considered
+ * incompatible.
+ */
+ uint16_t major_version;
+
+ /* 6: Minor version. A library supporting newer features should be able to
+ * read metadata with an older minor version. However, an older library
+ * should not support reading metadata if its minor version is higher.
+ */
+ uint16_t minor_version;
+
+ /* 8: The size of this header struct. */
+ uint32_t header_size;
+
+ /* 12: SHA256 checksum of the header, up to |header_size| bytes, computed as
+ * if this field were set to 0.
+ */
+ uint8_t header_checksum[32];
+
+ /* 44: The total size of all tables. This size is contiguous; tables may not
+ * have gaps in between, and they immediately follow the header.
+ */
+ uint32_t tables_size;
+
+ /* 48: SHA256 checksum of all table contents. */
+ uint8_t tables_checksum[32];
+
+ /* 80: Partition table descriptor. */
+ LpMetadataTableDescriptor partitions;
+ /* 92: Extent table descriptor. */
+ LpMetadataTableDescriptor extents;
+ /* 104: Updateable group descriptor. */
+ LpMetadataTableDescriptor groups;
+ /* 116: Block device table. */
+ LpMetadataTableDescriptor block_devices;
+} __attribute__((packed)) LpMetadataHeader;
+
+/* This struct defines a logical partition entry, similar to what would be
+ * present in a GUID Partition Table.
+ */
+typedef struct LpMetadataPartition {
+ /* 0: Name of this partition in ASCII characters. Any unused characters in
+ * the buffer must be set to 0. Characters may only be alphanumeric or _.
+ * The name must include at least one ASCII character, and it must be unique
+ * across all partition names. The length (36) is the same as the maximum
+ * length of a GPT partition name.
+ */
+ char name[36];
+
+ /* 36: Attributes for the partition (see LP_PARTITION_ATTR_* flags above). */
+ uint32_t attributes;
+
+ /* 40: Index of the first extent owned by this partition. The extent will
+ * start at logical sector 0. Gaps between extents are not allowed.
+ */
+ uint32_t first_extent_index;
+
+ /* 44: Number of extents in the partition. Every partition must have at
+ * least one extent.
+ */
+ uint32_t num_extents;
+
+ /* 48: Group this partition belongs to. */
+ uint32_t group_index;
+} __attribute__((packed)) LpMetadataPartition;
+
+/* This extent is a dm-linear target, and the index is an index into the
+ * LinearExtent table.
+ */
+#define LP_TARGET_TYPE_LINEAR 0
+
+/* This extent is a dm-zero target. The index is ignored and must be 0. */
+#define LP_TARGET_TYPE_ZERO 1
+
+/* This struct defines an extent entry in the extent table block. */
+typedef struct LpMetadataExtent {
+ /* 0: Length of this extent, in 512-byte sectors. */
+ uint64_t num_sectors;
+
+ /* 8: Target type for device-mapper (see LP_TARGET_TYPE_* values). */
+ uint32_t target_type;
+
+ /* 12: Contents depends on target_type.
+ *
+ * LINEAR: The sector on the physical partition that this extent maps onto.
+ * ZERO: This field must be 0.
+ */
+ uint64_t target_data;
+
+ /* 20: Contents depends on target_type.
+ *
+ * LINEAR: Must be an index into the block devices table.
+ * ZERO: This field must be 0.
+ */
+ uint32_t target_source;
+} __attribute__((packed)) LpMetadataExtent;
+
+/* This struct defines an entry in the groups table. Each group has a maximum
+ * size, and partitions in a group must not exceed that size. There is always
+ * a "default" group of unlimited size, which is used when not using update
+ * groups or when using overlayfs or fastbootd.
+ */
+typedef struct LpMetadataPartitionGroup {
+ /* 0: Name of this group. Any unused characters must be 0. */
+ char name[36];
+
+ /* 36: Flags (see LP_GROUP_*). */
+ uint32_t flags;
+
+ /* 40: Maximum size in bytes. If 0, the group has no maximum size. */
+ uint64_t maximum_size;
+} __attribute__((packed)) LpMetadataPartitionGroup;
+
+/* This flag is only intended to be used with super_empty.img and super.img on
+ * retrofit devices. If set, the group needs a slot suffix to be interpreted
+ * correctly. The suffix is automatically applied by ReadMetadata().
+ */
+#define LP_GROUP_SLOT_SUFFIXED (1 << 0)
+
+/* This struct defines an entry in the block_devices table. There must be at
+ * least one device, and the first device must represent the partition holding
+ * the super metadata.
+ */
+typedef struct LpMetadataBlockDevice {
+ /* 0: First usable sector for allocating logical partitions. this will be
+ * the first sector after the initial geometry blocks, followed by the
+ * space consumed by metadata_max_size*metadata_slot_count*2.
+ */
+ uint64_t first_logical_sector;
+
+ /* 8: Alignment for defining partitions or partition extents. For example,
+ * an alignment of 1MiB will require that all partitions have a size evenly
+ * divisible by 1MiB, and that the smallest unit the partition can grow by
+ * is 1MiB.
+ *
+ * Alignment is normally determined at runtime when growing or adding
+ * partitions. If for some reason the alignment cannot be determined, then
+ * this predefined alignment in the geometry is used instead. By default
+ * it is set to 1MiB.
+ */
+ uint32_t alignment;
+
+ /* 12: Alignment offset for "stacked" devices. For example, if the "super"
+ * partition itself is not aligned within the parent block device's
+ * partition table, then we adjust for this in deciding where to place
+ * |first_logical_sector|.
+ *
+ * Similar to |alignment|, this will be derived from the operating system.
+ * If it cannot be determined, it is assumed to be 0.
+ */
+ uint32_t alignment_offset;
+
+ /* 16: Block device size, as specified when the metadata was created. This
+ * can be used to verify the geometry against a target device.
+ */
+ uint64_t size;
+
+ /* 24: Partition name in the GPT. Any unused characters must be 0. */
+ char partition_name[36];
+
+ /* 60: Flags (see LP_BLOCK_DEVICE_* flags below). */
+ uint32_t flags;
+} __attribute__((packed)) LpMetadataBlockDevice;
+
+/* This flag is only intended to be used with super_empty.img and super.img on
+ * retrofit devices. On these devices there are A and B super partitions, and
+ * we don't know ahead of time which slot the image will be applied to.
+ *
+ * If set, the block device needs a slot suffix applied before being used with
+ * IPartitionOpener. The slot suffix is determined by the metadata slot number
+ * (0 = _a, 1 = _b).
+ */
+#define LP_BLOCK_DEVICE_SLOT_SUFFIXED (1 << 0)
+
+
+typedef struct PartitionList
+{
+ char name[128];
+ struct PartitionList* next;
+}__attribute__((packed)) PartitionList;
+
+PartitionList* part_list = NULL;
+
+void printlist(void)
+{
+ PartitionList* node = part_list;
+ while (NULL != node)
+ {
+ printf("name: %s\n",node->name);
+ node = node->next;
+ }
+}
+
+int GetPrimaryGeometryOffset(void) {
+ int offset = LP_PARTITION_RESERVED_BYTES;
+ return offset;
+}
+
+int GetBackupGeometryOffset(void) {
+ int offset = GetPrimaryGeometryOffset() + LP_METADATA_GEOMETRY_SIZE;
+ return offset;
+}
+
+int GetPrimaryMetadataOffset(LpMetadataGeometry* geometry, int slot_number) {
+ int offset = LP_PARTITION_RESERVED_BYTES + (LP_METADATA_GEOMETRY_SIZE * 2) +
+ geometry->metadata_max_size * slot_number;
+ //printf("GetPrimaryMetadataOffset : %d\n", offset);
+ return offset;
+}
+
+int GetBackupMetadataOffset(LpMetadataGeometry* geometry, int slot_number) {
+ int start = LP_PARTITION_RESERVED_BYTES + (LP_METADATA_GEOMETRY_SIZE * 2) +
+ geometry->metadata_max_size * geometry->metadata_slot_count;
+ //printf("GetBackupMetadataOffset : %d\n", start + geometry->metadata_max_size * slot_number);
+ return start + geometry->metadata_max_size * slot_number;
+}
+
+int GetTotalMetadataSize(int metadata_max_size, int max_slots) {
+ return LP_PARTITION_RESERVED_BYTES +
+ (LP_METADATA_GEOMETRY_SIZE + metadata_max_size * max_slots) * 2;
+}
+
+int ParseGeometry(const void* buffer, LpMetadataGeometry* geometry) {
+ memcpy(geometry, buffer, sizeof(LpMetadataGeometry));
+
+ // Check the magic signature.
+ if (geometry->magic != LP_METADATA_GEOMETRY_MAGIC) {
+ printf("Logical partition metadata has invalid geometry magic signature\n");
+ return -1;
+ }
+ // Reject if the struct size is larger than what we compiled. This is so we
+ // can compute a checksum with the |struct_size| field rather than using
+ // sizeof.
+ if (geometry->struct_size > sizeof(LpMetadataGeometry)) {
+ printf("Logical partition metadata has unrecognized fields.\n");
+ return -1;
+ }
+
+ // Check that the struct size is equal (this will have to change if we ever
+ // change the struct size in a release).
+ if (geometry->struct_size != sizeof(LpMetadataGeometry)) {
+ printf("Logical partition metadata has invalid struct size.\n");
+ return -1;
+ }
+ if (geometry->metadata_slot_count == 0) {
+ printf("Logical partition metadata has invalid slot count.\n");
+ return -1;
+ }
+ if (geometry->metadata_max_size % LP_SECTOR_SIZE != 0) {
+ printf("Metadata max size is not sector-aligned.\n");
+ return -1;
+ }
+ return 0;
+}
+
+int ReadPrimaryGeometry(char *superbuf, LpMetadataGeometry* geometry) {
+ char buffer[LP_METADATA_GEOMETRY_SIZE];
+ memcpy(buffer, superbuf+LP_PARTITION_RESERVED_BYTES, LP_METADATA_GEOMETRY_SIZE);
+ return ParseGeometry(buffer, geometry);
+}
+
+int ReadBackupGeometry(char *superbuf, LpMetadataGeometry* geometry) {
+ char buffer[LP_METADATA_GEOMETRY_SIZE];
+ memcpy(buffer, superbuf+LP_PARTITION_RESERVED_BYTES+LP_METADATA_GEOMETRY_SIZE, LP_METADATA_GEOMETRY_SIZE);
+ return ParseGeometry(buffer, geometry);
+}
+
+// Read and validate geometry information from a block device that holds
+// logical partitions. If the information is corrupted, this will attempt
+// to read it from a secondary backup location.
+int ReadLogicalPartitionGeometry(char *superbuf, LpMetadataGeometry* geometry) {
+ if (ReadPrimaryGeometry(superbuf, geometry) == 0) {
+ return 0;
+ }
+ return ReadBackupGeometry(superbuf, geometry);
+}
+
+static int ValidateMetadataHeader(LpMetadataHeader* header) {
+ // Do basic validation of key metadata bits.
+ if (header->magic != LP_METADATA_HEADER_MAGIC) {
+ printf("Logical partition metadata has invalid magic value.\n");
+ return -1;
+ }
+ // Check that the version is compatible.
+ if (header->major_version != LP_METADATA_MAJOR_VERSION ||
+ header->minor_version > LP_METADATA_MINOR_VERSION_MAX) {
+ printf("Logical partition metadata has incompatible version.\n");
+ return -1;
+ }
+ /*if (!ValidateTableBounds(header, &header->partitions) ||
+ !ValidateTableBounds(header, &header->extents) ||
+ !ValidateTableBounds(header, &header->groups) ||
+ !ValidateTableBounds(header, &header->block_devices)) {
+ printf("Logical partition metadata has invalid table bounds.\n");
+ return -1;
+ }*/
+ // Check that table entry sizes can accomodate their respective structs. If
+ // table sizes change, these checks will have to be adjusted.
+ if (header->partitions.entry_size != sizeof(LpMetadataPartition)) {
+ printf("Logical partition metadata has invalid partition table entry size.\n");
+ return -1;
+ }
+ if (header->extents.entry_size != sizeof(LpMetadataExtent)) {
+ printf("Logical partition metadata has invalid extent table entry size.\n");
+ return -1;
+ }
+ if (header->groups.entry_size != sizeof(LpMetadataPartitionGroup)) {
+ printf("Logical partition metadata has invalid group table entry size.\n");
+ return -1;
+ }
+ return 0;
+}
+
+
+int ReadMetadataHeader(char *superbuf, LpMetadataHeader* header,
+ LpMetadataGeometry* geometry, int slot_number) {
+ char* buffer = NULL;
+ int cursor = 0;
+ PartitionList* tail = NULL ;
+ PartitionList* node = NULL ;
+ int ishead = 0;
+ int i;
+ int index = 0;
+ char* flag;
+
+ //printf("metaoffset: %d\n", GetPrimaryMetadataOffset(geometry, slot_number));
+
+ memcpy(header, superbuf + GetPrimaryMetadataOffset(geometry, slot_number), sizeof(LpMetadataHeader));
+ if (ValidateMetadataHeader(header) != 0) {
+ return -1;
+ }
+
+ //printf("header table size = %d\n", header->tables_size);
+ buffer = (char*)malloc(header->tables_size);
+ if (buffer == NULL) {
+ printf("Out of memory reading logical partition tables.\n");
+ return -1;
+ }
+
+ index = GetPrimaryMetadataOffset(geometry, slot_number) + sizeof(LpMetadataHeader);
+#ifdef CONFIG_CMD_BOOTCTOL_VAB
+ flag = CONFIG_CMD_BOOTCTOL_VAB;
+ strcpy(flag, CONFIG_CMD_BOOTCTOL_VAB);
+ //printf("CONFIG_CMD_BOOTCTOL_VAB: %s \n", CONFIG_CMD_BOOTCTOL_VAB);
+ if ((strcmp(flag, "1") == 0) && (has_boot_slot == 1)) {
+ index = index + 128;
+ }
+#endif
+
+ memcpy(buffer, superbuf + index, header->tables_size);
+ cursor = index + header->partitions.offset;
+
+ //printf("index: %d\n", index);
+ //printf("cursor: %d\n", cursor);
+
+ // ValidateTableSize ensured that |cursor| is valid for the number of
+ // entries in the table.
+ for (i = 0; i < header->partitions.num_entries; i++) {
+ LpMetadataPartition partition;
+ memcpy(&partition, superbuf + cursor, sizeof(partition));
+ cursor += header->partitions.entry_size;
+
+ //printf("partition name : %s\n", partition.name);
+
+ if (partition.attributes & ~LP_PARTITION_ATTRIBUTE_MASK) {
+ printf("Logical partition has invalid attribute set.\n");
+ if (buffer)
+ free (buffer);
+ return -1;
+ }
+ if (partition.first_extent_index + partition.num_extents < partition.first_extent_index) {
+ printf("Logical partition first_extent_index + num_extents overflowed.\n");
+ if (buffer)
+ free (buffer);
+ return -1;
+ }
+ if (partition.first_extent_index + partition.num_extents > header->extents.num_entries) {
+ printf("Logical partition has invalid extent list.\n");
+ if (buffer)
+ free (buffer);
+ return -1;
+ }
+ if (partition.group_index >= header->groups.num_entries) {
+ printf("Logical partition has invalid group index.\n");
+ if (buffer)
+ free (buffer);
+ return -1;
+ }
+
+ node = malloc(sizeof(PartitionList));
+ strcpy(node->name, partition.name);
+ if (ishead == 0)
+ {
+ part_list = node ;
+ part_list->next = NULL ;
+ tail = node;
+ ishead = -1;
+ }
+ else
+ {
+ tail->next = node;
+ tail = node;
+ }
+ //metadata->partitions.push_back(partition);
+ }
+
+ if (NULL != tail)
+ tail->next = NULL;
+
+ if (buffer)
+ free (buffer);
+
+ return 0;
+}
+
+/*void dump_mem(char * buffer, int count)
+{
+ int i;
+ printf("***********************************************\n");
+ for (i=0; i<count ; i++)
+ {
+ if (i % 16 == 0)
+ printf("\n");
+ printf("%02x ", buffer[i]);
+ }
+ printf("\n");
+ printf("***********************************************\n");
+}*/
+
+
+int do_ReadMetadata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char *partition = "super";
+ char* superbuf;
+ LpMetadataGeometry geometry;
+ LpMetadataHeader metadata_header;
+ char *slot;
+ int slot_number = 0;
+ superbuf = (char*)malloc(SUPERBUF_SIZE);
+ if (superbuf == NULL) {
+ printf("Out of memory reading logical partition tables.\n");
+ goto ERR;
+ }
+
+ if (dynamic_partition) {
+ if (store_read((const char *)partition,
+ 0, SUPERBUF_SIZE, (unsigned char *)superbuf) < 0) {
+ printf("failed to store read %s.\n", partition);
+ goto ERR;
+ }
+
+ //dump_mem(superbuf, SUPERBUF_SIZE);
+
+ if (ReadLogicalPartitionGeometry(superbuf, &geometry) != 0) {
+ goto ERR;
+ }
+
+ if (has_boot_slot == 1) {
+ slot = env_get("slot-suffixes");
+ //printf("slot-suffixes: %s\n", slot);
+ if (strcmp(slot, "0") == 0) {
+ slot_number = 0;
+ } else if (strcmp(slot, "1") == 0) {
+ slot_number = 1;
+ }
+ }
+
+ ReadMetadataHeader(superbuf, &metadata_header, &geometry, slot_number);
+
+ //printlist();
+ }
+
+ if (superbuf)
+ free (superbuf);
+
+ return 0;
+
+ERR:
+ if (superbuf)
+ free (superbuf);
+ return -1;
+
+}
+
+int is_partition_logical(char* parition_name) {
+ run_command("readMetadata", 0);
+ PartitionList* node = part_list;
+ while (NULL != node)
+ {
+ //printf("name: %s\n",node->name);
+ if (strcmp(node->name, parition_name) == 0)
+ return 0;
+ node = node->next;
+ }
+
+ return -1;
+}
+
+#else
+static int do_ReadMetadata(
+ cmd_tbl_t * cmdtp,
+ int flag,
+ int argc,
+ char * const argv[]) {
+ // Do-Nothing!
+ return 0;
+}
+#endif /* CONFIG_BOOTLOADER_CONTROL_BLOCK */
+
+U_BOOT_CMD(
+ readMetadata, 1, 0, do_ReadMetadata,
+ "readMetadata",
+ "\nThis command will read metadata in super \n"
+ "So you can execute command: readMetadata"
+);
+
diff --git a/cmd/amlogic/cmd_factory_boot.c b/cmd/amlogic/cmd_factory_boot.c
deleted file mode 100644
index 266c4a9..0000000
--- a/cmd/amlogic/cmd_factory_boot.c
+++ /dev/null
@@ -1,69 +0,0 @@
-
-/*
- * common/cmd_factory_boot.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <command.h>
-#include <amlogic/flash_ts.h>
-
-#include <asm/arch-g12b/reboot.h>
-#include <asm/arch/secure_apb.h>
-#include <asm/io.h>
-#include <asm/arch/bl31_apis.h>
-#include <asm/arch/watchdog.h>
-
-int set_factory_boot (char * const value)
-{
- int ret = 1;
-
- if(is_flash_inited()) {
- flash_ts_init();
-
- char key[] = "bootloader.command";
- ret = flash_ts_set(key, value);
-
- printf("FTS set:\n%s -> %s\nReturn: %d\n", key, value, ret);
- }
- return ret;
-}
-
-int do_factory_boot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char value[] = "boot-factory";
- return set_factory_boot(value);
-}
-
-int do_not_factory_boot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- char value[] = "";
- return set_factory_boot(value);
-}
-
-U_BOOT_CMD(
- enable_factory_boot, 1, 0, do_factory_boot,
- "Set FTS flag to enable factory boot.",
- "enable_factory_boot\n"
-);
-
-U_BOOT_CMD(
- disable_factory_boot, 1, 0, do_not_factory_boot,
- "Resets FTS flag to disable factory boot.",
- "disable_factory_boot\n"
-);
diff --git a/cmd/amlogic/cmd_factory_provision.c b/cmd/amlogic/cmd_factory_provision.c
new file mode 100644
index 0000000..76c64fd
--- /dev/null
+++ b/cmd/amlogic/cmd_factory_provision.c
@@ -0,0 +1,965 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <fs.h>
+#include <fat.h>
+#include <u-boot/sha256.h>
+#include <emmc_partitions.h>
+#include <stdlib.h>
+#include <mapmem.h>
+#include <amlogic/storage.h>
+
+#define CMD_DEBUG (0)
+#define CMD_LOG_TAG "[FACTORY-PROVISION] "
+
+#if CMD_DEBUG
+#define LOGD(fmt, ...) printf("%s"fmt, CMD_LOG_TAG, ##__VA_ARGS__)
+#else
+#define LOGD(fmt, ...)
+#endif
+
+#define LOGE(fmt, ...) printf("%sERROR: "fmt, CMD_LOG_TAG, ##__VA_ARGS__)
+#define LOGI(fmt, ...) printf("%s"fmt, CMD_LOG_TAG, ##__VA_ARGS__)
+
+#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
+
+#ifndef getenv
+#define getenv env_get
+#endif
+
+#define FUNCID_PROVISION_SET_IV 0xB200E030
+#define FUNCID_PROVISION_ENCRYPT 0xB200E031
+#define FUNCID_PROVISION_GET_TRANSFER_ADDR 0xB2000007
+
+#define SIZE_1K (1024)
+#define SIZE_1M (SIZE_1K * SIZE_1K)
+#define SIZE_TAG (16)
+#define SIZE_IV (16)
+#define SIZE_AES_KEY (16)
+#define SIZE_HMAC_KEY (32)
+#define SIZE_HMAC_DIGEST (32)
+#define SIZE_BLOCK (512)
+
+#define MAX_SIZE_CMD (256)
+#define MAX_SIZE_KEYBOX_NAME (256)
+#define MAX_SIZE_PART_NAME (32)
+#define MAX_SIZE_KEYBOX (SIZE_1K * 16)
+
+#define MAX_CNT_FS_VALUE (256)
+
+#define KEYBOX_HDR_MAGIC (0x6B626F78) //"kbox"
+#define KEYBOX_HDR_MIN_VERSION (5)
+
+#define PROVISION_TYPE_FACTORY (0)
+
+#define ACTION_UNKNOWN (0x00)
+#define ACTION_INIT (0x01)
+#define ACTION_WRITE (0x02)
+#define ACTION_QUERY (0x03)
+#define ACTION_REMOVE (0x04)
+#define ACTION_CLEAR (0x05)
+#define ACTION_LIST (0x06)
+
+#define DEV_NAME "mmc"
+#define DEV_NO (1)
+#define PART_TYPE "user"
+#define PART_NAME_RSV "rsv"
+#define PART_NAME_FTY "factory"
+
+#define CMD_RET_SUCCESS 0x00000000
+#define CMD_RET_KEYBOX_NOT_EXIST 0x00000001
+#define CMD_RET_KEYBOX_TOO_LARGE 0x00000002
+#define CMD_RET_KEYBOX_NAME_TOO_LONG 0x00000003
+#define CMD_RET_KEYBOX_BAD_FORMAT 0x00000004
+#define CMD_RET_DEVICE_NO_SPACE 0x00000011
+#define CMD_RET_DEVICE_NOT_AVAILABLE 0x00000012
+#define CMD_RET_BAD_PARAMETER 0x00000021
+#define CMD_RET_SMC_CALL_FAILED 0x00000031
+#define CMD_RET_UNKNOWN_ERROR 0x0000FFFF
+
+struct keybox_header {
+ uint32_t magic;
+ uint32_t version;
+ uint32_t key_type;
+ uint32_t key_size;
+ uint32_t provision_type;
+ uint32_t ta_uuid[4];
+ uint32_t reserved[4];
+};
+
+struct encryption_context {
+ char iv[SIZE_IV];
+ char tag[SIZE_TAG];
+ char epek[SIZE_AES_KEY];
+ char rsv[64];
+};
+
+struct input_param {
+ uint32_t action;
+ const char *keybox_name;
+ uint32_t keybox_phy_addr;
+ uint32_t keybox_size;
+ uint32_t ret_data_addr;
+};
+
+struct fs_value {
+ int idx;
+ uint32_t value;
+};
+
+static char g_keybox[MAX_SIZE_KEYBOX] = { 0 };
+static char g_fs_data[SIZE_1K] = { 0 };
+static char g_part_name[MAX_SIZE_PART_NAME] = { 0 };
+
+static struct fs_value g_fs_vals_rsv[MAX_CNT_FS_VALUE] = {
+ { 0, 0xEB }, { 1, 0x3C }, { 2, 0x90 }, { 3, 0x6D },
+ { 4, 0x6B }, { 5, 0x66 }, { 6, 0x73 }, { 7, 0x2E },
+ { 8, 0x66 }, { 9, 0x61 }, { 10, 0x74 }, { 12, 0x02 },
+ { 13, 0x10 }, { 14, 0x01 }, { 16, 0x02 }, { 18, 0x02 },
+ { 20, 0x80 }, { 21, 0xF8 }, { 22, 0x10 }, { 24, 0x20 },
+ { 26, 0x40 }, { 36, 0x80 }, { 38, 0x29 }, { 39, 0x13 },
+ { 40, 0x4C }, { 41, 0x98 }, { 42, 0x6A }, { 43, 0x4B },
+ { 44, 0x45 }, { 45, 0x59 }, { 46, 0x42 }, { 47, 0x4F },
+ { 48, 0x58 }, { 49, 0x20 }, { 50, 0x50 }, { 51, 0x41 },
+ { 52, 0x52 }, { 53, 0x54 }, { 54, 0x46 }, { 55, 0x41 },
+ { 56, 0x54 }, { 57, 0x31 }, { 58, 0x32 }, { 59, 0x20 },
+ { 60, 0x20 }, { 61, 0x20 }, { 62, 0x0E }, { 63, 0x1F },
+ { 64, 0xBE }, { 65, 0x5B }, { 66, 0x7C }, { 67, 0xAC },
+ { 68, 0x22 }, { 69, 0xC0 }, { 70, 0x74 }, { 71, 0x0B },
+ { 72, 0x56 }, { 73, 0xB4 }, { 74, 0x0E }, { 75, 0xBB },
+ { 76, 0x07 }, { 78, 0xCD }, { 79, 0x10 }, { 80, 0x5E },
+ { 81, 0xEB }, { 82, 0xF0 }, { 83, 0x32 }, { 84, 0xE4 },
+ { 85, 0xCD }, { 86, 0x16 }, { 87, 0xCD }, { 88, 0x19 },
+ { 89, 0xEB }, { 90, 0xFE }, { 91, 0x54 }, { 92, 0x68 },
+ { 93, 0x69 }, { 94, 0x73 }, { 95, 0x20 }, { 96, 0x69 },
+ { 97, 0x73 }, { 98, 0x20 }, { 99, 0x6E }, { 100, 0x6F },
+ { 101, 0x74 }, { 102, 0x20 }, { 103, 0x61 }, { 104, 0x20 },
+ { 105, 0x62 }, { 106, 0x6F }, { 107, 0x6F }, { 108, 0x74 },
+ { 109, 0x61 }, { 110, 0x62 }, { 111, 0x6C }, { 112, 0x65 },
+ { 113, 0x20 }, { 114, 0x64 }, { 115, 0x69 }, { 116, 0x73 },
+ { 117, 0x6B }, { 118, 0x2E }, { 119, 0x20 }, { 120, 0x20 },
+ { 121, 0x50 }, { 122, 0x6C }, { 123, 0x65 }, { 124, 0x61 },
+ { 125, 0x73 }, { 126, 0x65 }, { 127, 0x20 }, { 128, 0x69 },
+ { 129, 0x6E }, { 130, 0x73 }, { 131, 0x65 }, { 132, 0x72 },
+ { 133, 0x74 }, { 134, 0x20 }, { 135, 0x61 }, { 136, 0x20 },
+ { 137, 0x62 }, { 138, 0x6F }, { 139, 0x6F }, { 140, 0x74 },
+ { 141, 0x61 }, { 142, 0x62 }, { 143, 0x6C }, { 144, 0x65 },
+ { 145, 0x20 }, { 146, 0x66 }, { 147, 0x6C }, { 148, 0x6F },
+ { 149, 0x70 }, { 150, 0x70 }, { 151, 0x79 }, { 152, 0x20 },
+ { 153, 0x61 }, { 154, 0x6E }, { 155, 0x64 }, { 156, 0x0D },
+ { 157, 0x0A }, { 158, 0x70 }, { 159, 0x72 }, { 160, 0x65 },
+ { 161, 0x73 }, { 162, 0x73 }, { 163, 0x20 }, { 164, 0x61 },
+ { 165, 0x6E }, { 166, 0x79 }, { 167, 0x20 }, { 168, 0x6B },
+ { 169, 0x65 }, { 170, 0x79 }, { 171, 0x20 }, { 172, 0x74 },
+ { 173, 0x6F }, { 174, 0x20 }, { 175, 0x74 }, { 176, 0x72 },
+ { 177, 0x79 }, { 178, 0x20 }, { 179, 0x61 }, { 180, 0x67 },
+ { 181, 0x61 }, { 182, 0x69 }, { 183, 0x6E }, { 184, 0x20 },
+ { 185, 0x2E }, { 186, 0x2E }, { 187, 0x2E }, { 188, 0x20 },
+ { 189, 0x0D }, { 190, 0x0A }, { 510, 0x55 }, { 511, 0xAA },
+ { 512, 0xF8 }, { 513, 0xFF }, { 514, 0xFF }, { 8704, 0xF8 },
+ { 8705, 0xFF }, { 8706, 0xFF }, { 16896, 0x4B }, { 16897, 0x45 },
+ { 16898, 0x59 }, { 16899, 0x42 }, { 16900, 0x4F }, { 16901, 0x58 },
+ { 16902, 0x20 }, { 16903, 0x50 }, { 16904, 0x41 }, { 16905, 0x52 },
+ { 16906, 0x54 }, { 16907, 0x08 }, { 16910, 0x1C }, { 16911, 0x78 },
+ { 16912, 0x44 }, { 16913, 0x50 }, { 16914, 0x44 }, { 16915, 0x50 },
+ { 16918, 0x1C }, { 16919, 0x78 }, { 16920, 0x44 }, { 16921, 0x50 },
+ { 0, 0 },
+};
+
+static struct fs_value g_fs_vals_fty[MAX_CNT_FS_VALUE] = {
+ { 0, 0xEB }, { 1, 0x3C }, { 2, 0x90 }, { 3, 0x6D },
+ { 4, 0x6B }, { 5, 0x66 }, { 6, 0x73 }, { 7, 0x2E },
+ { 8, 0x66 }, { 9, 0x61 }, { 10, 0x74 }, { 12, 0x02 },
+ { 13, 0x08 }, { 14, 0x01 }, { 16, 0x02 }, { 18, 0x02 },
+ { 20, 0x40 }, { 21, 0xF8 }, { 22, 0x08 }, { 24, 0x20 },
+ { 26, 0x40 }, { 36, 0x80 }, { 38, 0x29 }, { 39, 0xDE },
+ { 40, 0x62 }, { 41, 0xA6 }, { 42, 0xD0 }, { 43, 0x4B },
+ { 44, 0x45 }, { 45, 0x59 }, { 46, 0x42 }, { 47, 0x4F },
+ { 48, 0x58 }, { 49, 0x20 }, { 50, 0x50 }, { 51, 0x41 },
+ { 52, 0x52 }, { 53, 0x54 }, { 54, 0x46 }, { 55, 0x41 },
+ { 56, 0x54 }, { 57, 0x31 }, { 58, 0x32 }, { 59, 0x20 },
+ { 60, 0x20 }, { 61, 0x20 }, { 62, 0x0E }, { 63, 0x1F },
+ { 64, 0xBE }, { 65, 0x5B }, { 66, 0x7C }, { 67, 0xAC },
+ { 68, 0x22 }, { 69, 0xC0 }, { 70, 0x74 }, { 71, 0x0B },
+ { 72, 0x56 }, { 73, 0xB4 }, { 74, 0x0E }, { 75, 0xBB },
+ { 76, 0x07 }, { 78, 0xCD }, { 79, 0x10 }, { 80, 0x5E },
+ { 81, 0xEB }, { 82, 0xF0 }, { 83, 0x32 }, { 84, 0xE4 },
+ { 85, 0xCD }, { 86, 0x16 }, { 87, 0xCD }, { 88, 0x19 },
+ { 89, 0xEB }, { 90, 0xFE }, { 91, 0x54 }, { 92, 0x68 },
+ { 93, 0x69 }, { 94, 0x73 }, { 95, 0x20 }, { 96, 0x69 },
+ { 97, 0x73 }, { 98, 0x20 }, { 99, 0x6E }, { 100, 0x6F },
+ { 101, 0x74 }, { 102, 0x20 }, { 103, 0x61 }, { 104, 0x20 },
+ { 105, 0x62 }, { 106, 0x6F }, { 107, 0x6F }, { 108, 0x74 },
+ { 109, 0x61 }, { 110, 0x62 }, { 111, 0x6C }, { 112, 0x65 },
+ { 113, 0x20 }, { 114, 0x64 }, { 115, 0x69 }, { 116, 0x73 },
+ { 117, 0x6B }, { 118, 0x2E }, { 119, 0x20 }, { 120, 0x20 },
+ { 121, 0x50 }, { 122, 0x6C }, { 123, 0x65 }, { 124, 0x61 },
+ { 125, 0x73 }, { 126, 0x65 }, { 127, 0x20 }, { 128, 0x69 },
+ { 129, 0x6E }, { 130, 0x73 }, { 131, 0x65 }, { 132, 0x72 },
+ { 133, 0x74 }, { 134, 0x20 }, { 135, 0x61 }, { 136, 0x20 },
+ { 137, 0x62 }, { 138, 0x6F }, { 139, 0x6F }, { 140, 0x74 },
+ { 141, 0x61 }, { 142, 0x62 }, { 143, 0x6C }, { 144, 0x65 },
+ { 145, 0x20 }, { 146, 0x66 }, { 147, 0x6C }, { 148, 0x6F },
+ { 149, 0x70 }, { 150, 0x70 }, { 151, 0x79 }, { 152, 0x20 },
+ { 153, 0x61 }, { 154, 0x6E }, { 155, 0x64 }, { 156, 0x0D },
+ { 157, 0x0A }, { 158, 0x70 }, { 159, 0x72 }, { 160, 0x65 },
+ { 161, 0x73 }, { 162, 0x73 }, { 163, 0x20 }, { 164, 0x61 },
+ { 165, 0x6E }, { 166, 0x79 }, { 167, 0x20 }, { 168, 0x6B },
+ { 169, 0x65 }, { 170, 0x79 }, { 171, 0x20 }, { 172, 0x74 },
+ { 173, 0x6F }, { 174, 0x20 }, { 175, 0x74 }, { 176, 0x72 },
+ { 177, 0x79 }, { 178, 0x20 }, { 179, 0x61 }, { 180, 0x67 },
+ { 181, 0x61 }, { 182, 0x69 }, { 183, 0x6E }, { 184, 0x20 },
+ { 185, 0x2E }, { 186, 0x2E }, { 187, 0x2E }, { 188, 0x20 },
+ { 189, 0x0D }, { 190, 0x0A }, { 510, 0x55 }, { 511, 0xAA },
+ { 512, 0xF8 }, { 513, 0xFF }, { 514, 0xFF }, { 4608, 0xF8 },
+ { 4609, 0xFF }, { 4610, 0xFF }, { 8704, 0x4B }, { 8705, 0x45 },
+ { 8706, 0x59 }, { 8707, 0x42 }, { 8708, 0x4F }, { 8709, 0x58 },
+ { 8710, 0x20 }, { 8711, 0x50 }, { 8712, 0x41 }, { 8713, 0x52 },
+ { 8714, 0x54 }, { 8715, 0x08 }, { 8718, 0x49 }, { 8719, 0xA2 },
+ { 8720, 0x4C }, { 8721, 0x50 }, { 8722, 0x4C }, { 8723, 0x50 },
+ { 8726, 0x49 }, { 8727, 0xA2 }, { 8728, 0x4C }, { 8729, 0x50 },
+ { 0, 0 },
+};
+
+static uint32_t get_transfer_phy_addr(uint32_t *transfer_phy_addr)
+{
+ register uint32_t x0 asm("x0") = FUNCID_PROVISION_GET_TRANSFER_ADDR;
+ register uint32_t x1 asm("x1") = 0;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x0")
+ "smc #0\n"
+ : "=r"(x0), "=r"(x1)
+ : "r"(x0));
+ } while (0);
+
+ if (x0 == 0)
+ *transfer_phy_addr = x1;
+
+ return x0;
+}
+
+static uint32_t set_iv(uint32_t transfer_addr, uint32_t iv_size)
+{
+ register uint32_t x0 asm("x0") = FUNCID_PROVISION_SET_IV;
+ register uint32_t x1 asm("x1") = iv_size;
+ register uint32_t x2 asm("x2") = transfer_addr;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x0")
+ __asmeq("%2", "x1")
+ __asmeq("%3", "x2")
+ "smc #0\n"
+ : "=r"(x0)
+ : "r"(x0), "r"(x1), "r"(x2));
+ } while (0);
+
+ return x0;
+}
+
+static uint32_t encrypt(uint32_t transfer_addr, uint32_t *data_size)
+{
+ register uint32_t x0 asm("x0") = FUNCID_PROVISION_ENCRYPT;
+ register uint32_t x1 asm("x1") = *data_size;
+ register uint32_t x2 asm("x2") = transfer_addr;
+
+ do {
+ asm volatile(
+ __asmeq("%0", "x0")
+ __asmeq("%1", "x1")
+ __asmeq("%2", "x2")
+ __asmeq("%3", "x0")
+ __asmeq("%4", "x1")
+ __asmeq("%5", "x2")
+ "smc #0\n"
+ : "=r"(x0), "=r"(x1), "=r"(x2)
+ : "r"(x0), "r"(x1), "r"(x2));
+ } while (0);
+
+ if (x0 == 0)
+ *data_size = x1;
+
+ return x0;
+}
+
+static void usage(void)
+{
+ printf("factory_provision -- provision keybox\n\n"
+ "Usage:\n"
+ "factory_provision write <keybox_name> <keybox_addr> <keybox_size>\n"
+ " - write keybox to key partition\n\n"
+ "factory_provision query <keybox_name> [ret_data_addr]\n"
+ " - query whether the keybox exists by keybox name\n"
+ " - when keybox exists, return data: keybox_size(4bytes)\n\n"
+ "factory_provision remove <keybox_name>\n"
+ " - remove the keybox by keybox name\n\n");
+}
+
+static void parse_params(int argc, char * const argv[],
+ struct input_param *params)
+{
+ memset(params, 0, sizeof(struct input_param));
+ switch (argc) {
+ case 5:
+ if (!memcmp(argv[1], "write", strlen("write"))) {
+ params->action = ACTION_WRITE;
+ params->keybox_name = argv[2];
+ params->keybox_phy_addr =
+ (uint32_t)simple_strtoul(argv[3], NULL, 0);
+ params->keybox_size =
+ (uint32_t)simple_strtoul(argv[4], NULL, 0);
+ }
+ break;
+ case 4:
+ if (!memcmp(argv[1], "query", strlen("query"))) {
+ params->action = ACTION_QUERY;
+ params->keybox_name = argv[2];
+ params->ret_data_addr =
+ (uint32_t)simple_strtoul(argv[3], NULL, 0);
+ }
+ break;
+ case 3:
+ if (!memcmp(argv[1], "query", strlen("query"))) {
+ params->action = ACTION_QUERY;
+ params->keybox_name = argv[2];
+ if (env_get("loadaddr"))
+ params->ret_data_addr =
+ (uint32_t)simple_strtoul(
+ (char * const)env_get("loadaddr"), NULL, 0);
+ else
+ params->ret_data_addr = CONFIG_SYS_LOAD_ADDR;
+ } else if (!memcmp(argv[1], "remove", strlen("remove"))) {
+ params->action = ACTION_REMOVE;
+ params->keybox_name = argv[2];
+ }
+ break;
+ case 2:
+ if (!memcmp(argv[1], "init", strlen("init")))
+ params->action = ACTION_INIT;
+ else if (!memcmp(argv[1], "clear", strlen("clear")))
+ params->action = ACTION_CLEAR;
+ else if (!memcmp(argv[1], "list", strlen("list")))
+ params->action = ACTION_LIST;
+ break;
+ default:
+ break;
+ }
+}
+
+static int check_params(const struct input_param *params)
+{
+ int ret = CMD_RET_SUCCESS;
+
+ switch (params->action) {
+ case ACTION_INIT:
+ case ACTION_CLEAR:
+ case ACTION_LIST:
+ break;
+ case ACTION_WRITE:
+ if (strlen(params->keybox_name) > MAX_SIZE_KEYBOX_NAME) {
+ LOGE("keybox name is too long, and max length is "
+ "%d\n", MAX_SIZE_KEYBOX_NAME);
+ ret = CMD_RET_KEYBOX_NAME_TOO_LONG;
+ goto exit;
+ }
+ if (params->keybox_size > MAX_SIZE_KEYBOX) {
+ LOGE("keybox size is too large, and max size is %d\n",
+ MAX_SIZE_KEYBOX);
+ ret = CMD_RET_KEYBOX_TOO_LARGE;
+ goto exit;
+ }
+ if (!params->keybox_phy_addr) {
+ LOGE("keybox addr error\n");
+ ret = CMD_RET_BAD_PARAMETER;
+ goto exit;
+ }
+ break;
+ case ACTION_QUERY:
+ case ACTION_REMOVE:
+ if (strlen(params->keybox_name) > MAX_SIZE_KEYBOX_NAME) {
+ LOGE("keybox name is too long, and max length is "
+ "%d\n", MAX_SIZE_KEYBOX_NAME);
+ ret = CMD_RET_KEYBOX_NAME_TOO_LONG;
+ goto exit;
+ }
+ break;
+ default:
+ ret = CMD_RET_BAD_PARAMETER;
+ break;
+ }
+
+exit:
+ return ret;
+}
+
+static int preprocess_keybox(char *keybox, uint32_t size)
+{
+ uint32_t res = 0;
+ struct encryption_context *enc_cxt = (struct encryption_context *)
+ (keybox + sizeof(struct keybox_header));
+ uint32_t epek_size = sizeof(enc_cxt->epek);
+ uint32_t transfer_phy_addr = 0;
+ char *transfer_buf = NULL;
+
+ res = get_transfer_phy_addr(&transfer_phy_addr);
+ if (res) {
+ LOGE("get transfer address failed, "
+ "smc fast call ret = 0x%08X\n", res);
+ return CMD_RET_SMC_CALL_FAILED;
+ }
+
+ transfer_buf = map_sysmem(transfer_phy_addr, 0);
+
+ memcpy(transfer_buf, enc_cxt->iv, sizeof(enc_cxt->iv));
+ res = set_iv(transfer_phy_addr, sizeof(enc_cxt->iv));
+ if (res) {
+ LOGE("set iv failed, smc fast call ret = 0x%08X\n", res);
+ return CMD_RET_SMC_CALL_FAILED;
+ }
+
+ memcpy(transfer_buf, enc_cxt->epek, sizeof(enc_cxt->epek));
+ res = encrypt(transfer_phy_addr, &epek_size);
+ if (res) {
+ LOGE("encrypt epek failed, smc fast call ret = 0x%08X\n", res);
+ return CMD_RET_SMC_CALL_FAILED;
+ }
+ memcpy(enc_cxt->epek, transfer_buf, epek_size);
+
+ unmap_sysmem(transfer_buf);
+
+ return CMD_RET_SUCCESS;
+}
+
+static const char* get_valid_part_name(void)
+{
+ int part_num = get_partition_num_by_name(PART_NAME_FTY);
+
+ memset(g_part_name, 0, sizeof(g_part_name));
+ if (part_num >= 0)
+ strcpy(g_part_name, PART_NAME_FTY);
+ else
+ strcpy(g_part_name, PART_NAME_RSV);
+
+ return g_part_name;
+}
+
+static const struct fs_value* get_fs_values(void)
+{
+ int part_num = get_partition_num_by_name(PART_NAME_FTY);
+
+ if (part_num >= 0)
+ return g_fs_vals_fty;
+ else
+ return g_fs_vals_rsv;
+}
+
+static int make_fat_fs(void)
+{
+ char cmd[MAX_SIZE_CMD] = { 0 };
+ int i = 0;
+ const char *part_name = get_valid_part_name();
+ const struct fs_value *fs_vals = get_fs_values();
+ uint32_t data_phy_addr = (uint32_t)virt_to_phys(g_fs_data);
+ uint32_t offset = 0;
+
+ /* erase partition */
+ sprintf(cmd, "mmc dev %d;amlmmc switch %d %s;amlmmc erase %s;",
+ DEV_NO, DEV_NO, PART_TYPE, part_name);
+ if (run_command(cmd, 0)) {
+ LOGE("command[%s] failed\n", cmd);
+ return CMD_RET_UNKNOWN_ERROR;
+ }
+
+ /* write fat file system */
+ memset(g_fs_data, 0, SIZE_1K);
+ for (i = 0; i < MAX_CNT_FS_VALUE && fs_vals[i].value; i++) {
+ if ((i > 0) && (fs_vals[i].idx / SIZE_1K !=
+ fs_vals[i - 1].idx / SIZE_1K)) {
+ memset(cmd, 0, sizeof(cmd));
+ offset = fs_vals[i - 1].idx / SIZE_1K * SIZE_1K;
+ sprintf(cmd, "amlmmc write %s 0x%08X 0x%X 0x%X;",
+ part_name, data_phy_addr, offset, SIZE_1K);
+ if (run_command(cmd, 0)) {
+ LOGE("command[%s] failed\n", cmd);
+ return CMD_RET_UNKNOWN_ERROR;
+ }
+ }
+ g_fs_data[fs_vals[i].idx % SIZE_1K] = fs_vals[i].value;
+ }
+ memset(cmd, 0, sizeof(cmd));
+ offset = fs_vals[i - 1].idx / SIZE_1K * SIZE_1K;
+ sprintf(cmd, "amlmmc write %s 0x%08X 0x%X 0x%X;",
+ part_name, data_phy_addr, offset, SIZE_1K);
+ if (run_command(cmd, 0)) {
+ LOGE("command[%s] failed\n", cmd);
+ return CMD_RET_UNKNOWN_ERROR;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int dev_writable(void)
+{
+ char cmd[MAX_SIZE_CMD] = { 0 };
+
+ sprintf(cmd, "fatinfo %s 0x%X:0x%X", DEV_NAME, DEV_NO,
+ get_partition_num_by_name((char *)get_valid_part_name()));
+ if (run_command(cmd, 0)) {
+ LOGD("command[%s] failed\n", cmd);
+ return CMD_RET_DEVICE_NOT_AVAILABLE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int dev_write(const char *name, const char *data, uint32_t size)
+{
+ char cmd[MAX_SIZE_CMD] = { 0 };
+
+ sprintf(cmd, "fatwrite %s 0x%X:0x%X 0x%08X %s 0x%X", DEV_NAME, DEV_NO,
+ get_partition_num_by_name((char *)get_valid_part_name()),
+ (uint32_t)virt_to_phys((void *)data), name, size);
+ if (run_command(cmd, 0)) {
+ LOGD("command[%s] failed\n", cmd);
+ return CMD_RET_DEVICE_NOT_AVAILABLE;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int init_partition(void)
+{
+ int ret = CMD_RET_SUCCESS;
+ char dev_part_str[16] = { 0 };
+
+ ret = dev_writable();
+ if (ret) {
+ ret = make_fat_fs();
+ if (ret) {
+ LOGE("make fat file system failed\n");
+ return ret;
+ }
+ ret = dev_writable();
+ if (ret) {
+ LOGE("device not available\n");
+ return ret;
+ }
+ }
+
+ sprintf(dev_part_str, "0x%X:0x%X", DEV_NO,
+ get_partition_num_by_name((char *)get_valid_part_name()));
+ if (fs_set_blk_dev(DEV_NAME, dev_part_str, FS_TYPE_FAT)) {
+ LOGE("set block device failed\n");
+ ret = CMD_RET_UNKNOWN_ERROR;
+ }
+
+ return ret;
+}
+
+void convert_to_uuid_str(const char uuid[16], char uuid_str[40])
+{
+ int i = 0;
+ const char *uuid_ptr = uuid;
+ char *str_ptr = uuid_str;
+
+ for (i = 0; i < 4; i++) {
+ sprintf(str_ptr, "%02x", *uuid_ptr);
+ str_ptr += 2;
+ uuid_ptr++;
+ }
+ *str_ptr++ = '-';
+ for (i = 0; i < 2; i++) {
+ sprintf(str_ptr, "%02x", *uuid_ptr);
+ str_ptr += 2;
+ uuid_ptr++;
+ }
+ *str_ptr++ = '-';
+ for (i = 0; i < 2; i++) {
+ sprintf(str_ptr, "%02x", *uuid_ptr);
+ str_ptr += 2;
+ uuid_ptr++;
+ }
+ *str_ptr++ = '-';
+ for (i = 0; i < 8; i++) {
+ sprintf(str_ptr, "%02x", *uuid_ptr);
+ str_ptr += 2;
+ uuid_ptr++;
+ }
+}
+
+static int check_keybox(const char *keybox, uint32_t size)
+{
+ const struct keybox_header *hdr = (const struct keybox_header *)keybox;
+ uint32_t hdr_cxt_size = sizeof(struct keybox_header)
+ + sizeof(struct encryption_context);
+
+ if (hdr->magic != KEYBOX_HDR_MAGIC) {
+ LOGE("keybox header magic error"
+ "(expected magic: 0x%08X; wrong magic: 0x%08X)\n",
+ KEYBOX_HDR_MAGIC, hdr->magic);
+ return CMD_RET_KEYBOX_BAD_FORMAT;
+ }
+ if (hdr->version < KEYBOX_HDR_MIN_VERSION) {
+ LOGE("keybox header version error"
+ "(min version: %d; wrong version: %d)\n",
+ KEYBOX_HDR_MIN_VERSION, hdr->version);
+ return CMD_RET_KEYBOX_BAD_FORMAT;
+ }
+ if (size > MAX_SIZE_KEYBOX || size <= hdr_cxt_size
+ || hdr->key_size != size - hdr_cxt_size) {
+ LOGE("keybox length error\n");
+ return CMD_RET_KEYBOX_BAD_FORMAT;
+ }
+ if (hdr->provision_type != PROVISION_TYPE_FACTORY) {
+ LOGE("keybox provision type error"
+ "(expected type: %d; wrong type: %d)\n",
+ PROVISION_TYPE_FACTORY, hdr->provision_type);
+ return CMD_RET_KEYBOX_BAD_FORMAT;
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static void calc_sha256(const char *data, uint32_t data_size, char *sha256)
+{
+ sha256_context sha256_cxt;
+
+ sha256_starts(&sha256_cxt);
+ sha256_update(&sha256_cxt, (const uint8_t *)data, (uint32_t)data_size);
+ sha256_finish(&sha256_cxt, (uint8_t *)sha256);
+}
+
+static int verify_written_keybox(const char *keybox_name, const char *keybox,
+ uint32_t keybox_size)
+{
+ char sha256[SHA256_SUM_LEN] = { 0 };
+ char written_sha256[SHA256_SUM_LEN] = { 0 };
+ loff_t act_read = 0;
+
+ calc_sha256(keybox, keybox_size, sha256);
+
+ memset(g_keybox, 0, sizeof(g_keybox));
+ if (fat_read_file(keybox_name, g_keybox, 0, MAX_SIZE_KEYBOX, &act_read))
+ return CMD_RET_UNKNOWN_ERROR;
+ if (keybox_size != act_read)
+ return CMD_RET_UNKNOWN_ERROR;
+
+ calc_sha256(g_keybox, act_read, written_sha256);
+
+ if (memcmp(sha256, written_sha256, SHA256_SUM_LEN))
+ return CMD_RET_UNKNOWN_ERROR;
+
+ return CMD_RET_SUCCESS;
+}
+
+static int append_keybox(const char *keybox_name, const char *keybox,
+ uint32_t keybox_size)
+{
+ int ret = CMD_RET_SUCCESS;
+
+ ret = init_partition();
+ if (ret)
+ return ret;
+
+ ret = dev_write(keybox_name, keybox, keybox_size);
+ if (ret)
+ return ret;
+
+ ret = verify_written_keybox(keybox_name, keybox, keybox_size);
+ if (ret) {
+ LOGE("verify written keybox '%s' failed\n", keybox_name);
+ return ret;
+ }
+
+ LOGI("write keybox '%s' success\n", keybox_name);
+
+ return ret;
+}
+
+static int get_keybox_size(const char *keybox_name, uint32_t *size)
+{
+ loff_t keybox_size = 0;
+
+ if (fat_size(keybox_name, &keybox_size)) {
+ LOGE("get keybox '%s' size failed\n", keybox_name);
+ return CMD_RET_UNKNOWN_ERROR;
+ } else {
+ *size = (uint32_t)keybox_size;
+ LOGI("keybox '%s' size is %d\n", keybox_name, *size);
+ return CMD_RET_SUCCESS;
+ }
+}
+
+static int query_keybox(const char *keybox_name, char *ret_data)
+{
+ int ret = CMD_RET_SUCCESS;
+
+ ret = init_partition();
+ if (ret)
+ return ret;
+
+ if (!fat_exists(keybox_name)) {
+ LOGI("keybox '%s' not exists\n", keybox_name);
+ return CMD_RET_KEYBOX_NOT_EXIST;
+ }
+ else {
+ return get_keybox_size(keybox_name, (uint32_t *)ret_data);
+ }
+}
+
+static int remove_keybox(const char *keybox_name)
+{
+ int ret = init_partition();
+
+ if (ret)
+ return ret;
+
+ if (fs_unlink(keybox_name)) {
+ LOGE("remove '%s' failed\n", keybox_name);
+ return CMD_RET_UNKNOWN_ERROR;
+ }
+
+ LOGI("remove '%s' success\n", keybox_name);
+ return CMD_RET_SUCCESS;
+}
+
+static int remove_all_keyboxes(void)
+{
+ int ret = CMD_RET_SUCCESS;
+ struct fs_dir_stream *dirs = NULL;
+ struct fs_dirent *dent = NULL;
+ char cmd[MAX_SIZE_CMD] = { 0 };
+
+ ret = init_partition();
+ if (ret)
+ return ret;
+
+ if (fat_opendir("/", &dirs)) {
+ LOGE("open '/' failed\n");
+ return CMD_RET_UNKNOWN_ERROR;
+ }
+
+ while (!fat_readdir(dirs, &dent)) {
+ if (dent->type != FS_DT_REG) // not regular file
+ continue;
+
+ sprintf(cmd, "fatrm %s 0x%X:0x%X %s", DEV_NAME, DEV_NO,
+ get_partition_num_by_name(
+ (char *)get_valid_part_name()),
+ dent->name);
+ if (run_command(cmd, 0)) {
+ ret = CMD_RET_UNKNOWN_ERROR;
+ LOGE("remove '%s' failed\n", dent->name);
+ } else {
+ LOGI("remove '%s' success\n", dent->name);
+ }
+ }
+
+ fat_closedir(dirs);
+ return ret;
+}
+
+static int list_all_keyboxes(void)
+{
+ int ret = CMD_RET_SUCCESS;
+ char cmd[MAX_SIZE_CMD] = { 0 };
+
+ ret = init_partition();
+ if (ret)
+ return ret;
+
+ sprintf(cmd, "fatls %s 0x%X:0x%X", DEV_NAME, DEV_NO,
+ get_partition_num_by_name((char *)get_valid_part_name()));
+ if (run_command(cmd, 0)) {
+ LOGE("command[%s] failed\n", cmd);
+ ret = CMD_RET_UNKNOWN_ERROR;
+ }
+
+ return ret;
+}
+
+static int remove_same_type_keybox(uint32_t key_type, const char *uuid)
+{
+ int ret = CMD_RET_SUCCESS;
+ struct fs_dir_stream *dirs = NULL;
+ struct fs_dirent *dent = NULL;
+ struct keybox_header hdr;
+ loff_t act_read = 0;
+ char uuid_str[40] = { 0 };
+
+ ret = init_partition();
+ if (ret)
+ return ret;
+
+ if (fat_opendir("/", &dirs)) {
+ LOGE("open '/' failed\n");
+ return CMD_RET_UNKNOWN_ERROR;
+ }
+
+ convert_to_uuid_str(uuid, uuid_str);
+ while (!fat_readdir(dirs, &dent)) {
+ if (dent->type != FS_DT_REG) // not regular file
+ continue;
+
+ memset(&hdr, 0, sizeof(hdr));
+ if (fat_read_file(dent->name, &hdr, 0, sizeof(hdr), &act_read)
+ || act_read != sizeof(hdr)) {
+ LOGE("read keybox '%s' failed\n", dent->name);
+ ret = CMD_RET_UNKNOWN_ERROR;
+ goto exit;
+ }
+
+ if (!memcmp(uuid, hdr.ta_uuid, sizeof(hdr.ta_uuid)) &&
+ key_type == hdr.key_type) {
+ ret = remove_keybox(dent->name);
+ if (ret != CMD_RET_SUCCESS) {
+ LOGE("remove the same type"
+ "(uuid = %s, key_type = 0x%02X) "
+ "keybox '%s' failed\n",
+ uuid_str, key_type, dent->name);
+ goto exit;
+ }
+ }
+ }
+
+exit:
+ fat_closedir(dirs);
+ return ret;
+}
+
+int is_storage_medium_supported(void)
+{
+ int ret = CMD_RET_SUCCESS;
+ int medium_type = store_get_type();
+ char type_str[64] = { 0 };
+
+ if (medium_type != BOOT_EMMC) {
+ switch (medium_type) {
+ case BOOT_SD:
+ strcpy(type_str, "SD");
+ break;
+ case BOOT_NAND_NFTL:
+ strcpy(type_str, "NAND_NFTL");
+ break;
+ case BOOT_NAND_MTD:
+ strcpy(type_str, "NAND_MTD");
+ break;
+ case BOOT_SNAND:
+ strcpy(type_str, "SNAND");
+ break;
+ case BOOT_SNOR:
+ strcpy(type_str, "SNOR");
+ break;
+ default:
+ strcpy(type_str, "Unknown Storage Medium");
+ break;
+ }
+
+ LOGE("Provision function is not supported on '%s' storage medium", type_str);
+ ret = CMD_RET_DEVICE_NOT_AVAILABLE;
+ }
+
+ return ret;
+}
+
+int cmd_func(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int ret = CMD_RET_SUCCESS;
+ struct input_param params;
+ char *in_kb = NULL;
+ char *ret_data = NULL;
+ const struct keybox_header *hdr = NULL;
+
+ ret = is_storage_medium_supported();
+ if (ret != CMD_RET_SUCCESS)
+ goto exit;
+
+ parse_params(argc, argv, ¶ms);
+
+ ret = check_params(¶ms);
+ if (ret != CMD_RET_SUCCESS)
+ goto exit;
+
+ switch (params.action) {
+ case ACTION_INIT:
+ ret = init_partition();
+ break;
+ case ACTION_WRITE:
+ in_kb = map_sysmem(params.keybox_phy_addr, 0);
+
+ ret = check_keybox(in_kb, params.keybox_size);
+ if (ret != CMD_RET_SUCCESS)
+ goto exit;
+
+ hdr = (const struct keybox_header *)in_kb;
+ ret = remove_same_type_keybox(hdr->key_type,
+ (const char *)hdr->ta_uuid);
+ if (ret != CMD_RET_SUCCESS)
+ goto exit;
+
+ memcpy(g_keybox, in_kb, params.keybox_size);
+
+ ret = preprocess_keybox(g_keybox, params.keybox_size);
+ if (ret != CMD_RET_SUCCESS)
+ goto exit;
+
+ ret = append_keybox(params.keybox_name, g_keybox,
+ params.keybox_size);
+ if (ret != CMD_RET_SUCCESS)
+ goto exit;
+ break;
+ case ACTION_QUERY:
+ ret_data = map_sysmem(params.ret_data_addr, 0);
+ ret = query_keybox(params.keybox_name, ret_data);
+ if (ret != CMD_RET_SUCCESS)
+ goto exit;
+ break;
+ case ACTION_REMOVE:
+ ret = remove_keybox(params.keybox_name);
+ if (ret != CMD_RET_SUCCESS)
+ goto exit;
+ break;
+ case ACTION_CLEAR:
+ ret = remove_all_keyboxes();
+ if (ret != CMD_RET_SUCCESS)
+ goto exit;
+ break;
+ case ACTION_LIST:
+ ret = list_all_keyboxes();
+ if (ret != CMD_RET_SUCCESS)
+ goto exit;
+ break;
+ default:
+ break;
+ }
+
+exit:
+ if (in_kb)
+ unmap_sysmem(in_kb);
+ if (ret_data)
+ unmap_sysmem(ret_data);
+ if (ret == CMD_RET_BAD_PARAMETER)
+ usage();
+ return ret;
+}
+
+/* -------------------------------------------------------------------- */
+U_BOOT_CMD(
+ factory_provision, CONFIG_SYS_MAXARGS, 0, cmd_func,
+ "provision keybox\n",
+ "write <keybox_name> <keybox_addr> <keybox_size>\n"
+ " - write keybox to key partition\n\n"
+ "query <keybox_name> [ret_data_addr]\n"
+ " - query whether the keybox exists by keybox name\n"
+ " - when keybox exists, return data: keybox_size(4bytes)\n\n"
+ "remove <keybox_name>\n"
+ " - remove the keybox by keybox name\n"
+);
diff --git a/cmd/amlogic/cmd_hdmitx.c b/cmd/amlogic/cmd_hdmitx.c
index e1a10fb..c3d72b9 100644
--- a/cmd/amlogic/cmd_hdmitx.c
+++ b/cmd/amlogic/cmd_hdmitx.c
@@ -1,23 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2018
- * Amlogic. Inc.
- *
- * This file is used to prefetch/varify/compare HDCP keys
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -25,40 +8,129 @@
#include <environment.h>
#include <malloc.h>
#include <asm/byteorder.h>
-#include <amlogic/media/vout/hdmitx.h>
+#include <amlogic/media/vout/hdmitx/hdmitx.h>
+#include <amlogic/media/dv/dolby_vision.h>
#ifdef CONFIG_AML_LCD
#include <amlogic/media/vout/lcd/aml_lcd.h>
#endif
+#ifdef CONFIG_AML_LCD
+static unsigned int hdmitx_parse_vout_name(char *name)
+{
+ char *p, *frac_str;
+ unsigned int frac = 0;
+
+ p = strchr(name, ',');
+ if (!p) {
+ frac = 0;
+ } else {
+ frac_str = p + 1;
+ *p = '\0';
+ if (strcmp(frac_str, "frac") == 0)
+ frac = 1;
+ }
+
+ return frac;
+}
+#endif
+
static int do_hpd_detect(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
#ifdef CONFIG_AML_LCD
struct aml_lcd_drv_s *lcd_drv = NULL;
char *mode;
+ unsigned int frac;
#endif
- int st;
+ char* st;
+ char* hdmimode;
+ char* cvbsmode;
+ char* colorattribute;
+ int hpd_st = 0;
+
+ st = env_get("hdmitx_hpd_bypass");
+ if (st && (strcmp((const char *)(uintptr_t)st[0], "1") == 0)) {
+ printf("hdmitx_hpd_bypass detect\n");
+ return 0;
+ }
#ifdef CONFIG_AML_LCD
lcd_drv = aml_lcd_get_driver();
if (lcd_drv) {
if (lcd_drv->lcd_outputmode_check) {
- mode = env_get("outputmode");
- if (lcd_drv->lcd_outputmode_check(mode) == 0)
- return 0;
+ mode = (char *)malloc(64 * sizeof(char));
+ if (!mode) {
+ printf("cmd_hpd: mode malloc falied\n");
+ if (lcd_drv->lcd_outputmode_check(mode, 0) == 0)
+ return 0;
+ } else {
+ memset(mode, 0, sizeof(mode));
+ sprintf(mode, "%s", env_get("outputmode"));
+ frac = hdmitx_parse_vout_name(mode);
+ if (lcd_drv->lcd_outputmode_check(mode, frac) == 0) {
+ free(mode);
+ return 0;
+ }
+ free(mode);
+ }
}
}
#endif
- st = hdmitx_device.HWOp.get_hpd_state();
- printf("hpd_state=%c\n", st ? '1' : '0');
+ hpd_st = hdev->hwop.get_hpd_state();
+ if (!hpd_st) {
+ /* For some TV, they cost extra time to pullup HPD after 5V */
+ ulong hdmitx_hpd_wait_ms = env_get_ulong("hdmitx_hpd_wait_ms", 10, 1000);
+ ulong delay_ms = 0;
- if (st) {
- env_set("outputmode", env_get("hdmimode"));
- } else {
- env_set("outputmode", env_get("cvbsmode"));
+ while (delay_ms < hdmitx_hpd_wait_ms) {
+ if (hdmitx_hpd_wait_ms - delay_ms > 100) {
+ mdelay(100);
+ delay_ms += 100;
+ } else {
+ mdelay(hdmitx_hpd_wait_ms - delay_ms);
+ delay_ms = hdmitx_hpd_wait_ms;
+ }
+ hpd_st = hdev->hwop.get_hpd_state();
+ if (hpd_st) {
+ printf("hpd delay %lu ms\n", delay_ms);
+ break;
+ }
+ }
}
- return st;
+ printf("hpd_state=%d\n", hpd_st);
+
+ /*get hdmi mode and colorattribute from env */
+ hdmimode = env_get("hdmimode");
+ if (hdmimode)
+ printf("do_hpd_detect: hdmimode=%s\n", hdmimode);
+
+
+ colorattribute = env_get("colorattribute");
+ if (colorattribute)
+ printf("do_hpd_detect: colorattribute=%s\n", colorattribute);
+
+ if (hdmimode) {
+ if (strstr(hdmimode, "null")) {
+ env_set("hdmimode", "1080p60hz");
+ //run_command("saveenv", 0);
+ }
+ } else {
+ env_set("hdmimode", "1080p60hz");
+ //run_command("saveenv", 0);
+ }
+ hdmimode = env_get("hdmimode");
+ if (hpd_st) {
+ env_set("outputmode", hdmimode);
+ } else {
+ cvbsmode = env_get("cvbsmode");
+ if (cvbsmode)
+ env_set("outputmode", cvbsmode);
+ env_set("hdmichecksum", "0x00000000");
+ //run_command("saveenv", 0);
+ }
+ return hpd_st;
}
static unsigned char edid_raw_buf[256] = {0};
@@ -90,6 +162,7 @@
unsigned int tmp_addr = 0;
unsigned char edid_addr = 0;
unsigned char st = 0;
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
memset(edid_raw_buf, 0, ARRAY_SIZE(edid_raw_buf));
if (argc < 2)
@@ -101,7 +174,7 @@
edid_addr = tmp_addr;
/* read edid raw data */
/* current only support read 1 byte edid data */
- st = hdmitx_device.HWOp.read_edid(
+ st = hdev->hwop.read_edid(
&edid_raw_buf[edid_addr & 0xf8], edid_addr & 0xf8, 8);
printf("edid[0x%02x]: 0x%02x\n", edid_addr,
edid_raw_buf[edid_addr]);
@@ -117,12 +190,13 @@
{
unsigned char edid_addr = 0xf8; // Fixed Address
unsigned char st = 0;
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
memset(edid_raw_buf, 0, ARRAY_SIZE(edid_raw_buf));
// read edid raw data
// current only support read 1 byte edid data
- st = hdmitx_device.HWOp.read_edid(&edid_raw_buf[edid_addr & 0xf8], edid_addr & 0xf8, 8);
+ st = hdev->hwop.read_edid(&edid_raw_buf[edid_addr & 0xf8], edid_addr & 0xf8, 8);
if (1) // Debug only
dump_edid_raw_8bytes(&edid_raw_buf[edid_addr & 0xf8]);
if (st) {
@@ -198,13 +272,35 @@
return st;
}
+static void save_default_720p(void)
+{
+ env_set("hdmimode", "720p60hz");
+ env_set("outputmode", "720p60hz");
+ env_set("colorattribute", "rgb,8bit");
+}
+
+static void hdmitx_mask_rx_info(struct hdmitx_dev *hdev)
+{
+ if (!hdev || !hdev->para)
+ return;
+
+ if (env_get("colorattribute"))
+ hdmi_parse_attr(hdev->para, env_get("colorattribute"));
+
+ /* when current output color depth is 8bit, mask hdr capability */
+ /* refer to SWPL-44445 for more detail */
+ if (hdev->para->cd == HDMI_COLOR_DEPTH_24B)
+ memset(&hdev->RXCap.hdr_info, 0, sizeof(struct hdr_info));
+}
+
static int do_output(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
if (argc < 1)
return cmd_usage(cmdtp);
if (strcmp(argv[1], "list") == 0)
- hdmitx_device.HWOp.list_support_modes();
+ hdev->hwop.list_support_modes();
else if (strcmp(argv[1], "bist") == 0) {
unsigned int mode = 0;
if (strcmp(argv[2], "off") == 0)
@@ -215,31 +311,49 @@
mode = 3;
else
mode = simple_strtoul(argv[2], NULL, 10);
- hdmitx_device.HWOp.test_bist(mode);
+ hdev->hwop.test_bist(mode);
} else if (strcmp(argv[1], "prbs") == 0) {
- hdmitx_device.para->cs = HDMI_COLOR_FORMAT_RGB;
- hdmitx_device.para->cd = HDMI_COLOR_DEPTH_24B;
- hdmitx_device.vic = HDMI_1920x1080p60_16x9;
- hdmi_tx_set(&hdmitx_device);
- hdmitx_device.HWOp.test_bist(10);
- } else if (strcmp(argv[1], "div40") == 0) {
- hdmitx_device.HWOp.test_bist(11);
+ hdev->para->cs = HDMI_COLOR_FORMAT_RGB;
+ hdev->para->cd = HDMI_COLOR_DEPTH_24B;
+ hdev->vic = HDMI_1920x1080p60_16x9;
+ hdmi_tx_set(hdev);
+ hdev->hwop.test_prbs();
+ } else if (strncmp(argv[1], "div40", 5) == 0) {
+ bool div40 = 0;
+
+ if (argv[1][5] == '1')
+ div40 = 1;
+ hdev->hwop.set_div40(div40);
} else { /* "output" */
- hdmitx_device.vic = hdmi_get_fmt_vic(argv[1]);
- hdmitx_device.para = hdmi_get_fmt_paras(hdmitx_device.vic);
- if (hdmitx_device.vic == HDMI_unkown) {
+ if (!edid_parsing_ok(hdev)) {
+ /* SWPL-34712: if EDID parsing error case, not save env,
+ * only forcely output default mode(480p,RGB,8bit).
+ */
+ printf("edid parsing ng, forcely output 720p, rgb,8bit\n");
+ save_default_720p();
+ hdev->vic = HDMI_1280x720p60_16x9;
+ hdev->para =
+ hdmi_get_fmt_paras(hdev->vic);
+ hdev->para->cs = HDMI_COLOR_FORMAT_RGB;
+ hdev->para->cd = HDMI_COLOR_DEPTH_24B;
+ hdmi_tx_set(hdev);
+ return CMD_RET_SUCCESS;
+ }
+ hdev->vic = hdmi_get_fmt_vic(argv[1]);
+ hdev->para = hdmi_get_fmt_paras(hdev->vic);
+ if (hdev->vic == HDMI_unkown) {
/* Not find VIC */
printf("Not find '%s' mapped VIC\n", argv[1]);
return CMD_RET_FAILURE;
} else
- printf("set hdmitx VIC = %d\n", hdmitx_device.vic);
- if (strstr(argv[1], "hz420") != NULL)
- hdmitx_device.para->cs = HDMI_COLOR_FORMAT_420;
+ printf("set hdmitx VIC = %d\n", hdev->vic);
if (env_get("colorattribute"))
- hdmi_parse_attr(hdmitx_device.para, env_get("colorattribute"));
+ hdmi_parse_attr(hdev->para, env_get("colorattribute"));
+ if (strstr(argv[1], "hz420") != NULL)
+ hdev->para->cs = HDMI_COLOR_FORMAT_420;
/* For RGB444 or YCbCr444 under 6Gbps mode, no deepcolor */
/* Only 4k50/60 has 420 modes */
- switch (hdmitx_device.vic) {
+ switch (hdev->vic) {
case HDMI_3840x2160p50_16x9:
case HDMI_3840x2160p60_16x9:
case HDMI_4096x2160p50_256x135:
@@ -252,61 +366,71 @@
case HDMI_4096x2160p60_256x135_Y420:
case HDMI_3840x2160p50_64x27_Y420:
case HDMI_3840x2160p60_64x27_Y420:
- if ((hdmitx_device.para->cs == HDMI_COLOR_FORMAT_RGB) ||
- (hdmitx_device.para->cs == HDMI_COLOR_FORMAT_444)) {
- if (hdmitx_device.para->cd != HDMI_COLOR_DEPTH_24B) {
+ if ((hdev->para->cs == HDMI_COLOR_FORMAT_RGB) ||
+ (hdev->para->cs == HDMI_COLOR_FORMAT_444)) {
+ if (hdev->para->cd != HDMI_COLOR_DEPTH_24B) {
printf("vic %d cs %d has no cd %d\n",
- hdmitx_device.vic,
- hdmitx_device.para->cs,
- hdmitx_device.para->cd);
- hdmitx_device.para->cd = HDMI_COLOR_DEPTH_24B;
+ hdev->vic,
+ hdev->para->cs,
+ hdev->para->cd);
+ hdev->para->cd = HDMI_COLOR_DEPTH_24B;
printf("set cd as %d\n", HDMI_COLOR_DEPTH_24B);
}
}
- if (hdmitx_device.para->cs == HDMI_COLOR_FORMAT_420)
- hdmitx_device.vic |= HDMITX_VIC420_OFFSET;
+ if (hdev->para->cs == HDMI_COLOR_FORMAT_420)
+ hdev->vic |= HDMITX_VIC420_OFFSET;
break;
default:
- if (hdmitx_device.para->cs == HDMI_COLOR_FORMAT_420) {
- printf("vic %d has no cs %d\n", hdmitx_device.vic,
- hdmitx_device.para->cs);
- hdmitx_device.para->cs = HDMI_COLOR_FORMAT_444;
+ if (hdev->para->cs == HDMI_COLOR_FORMAT_420) {
+ printf("vic %d has no cs %d\n", hdev->vic,
+ hdev->para->cs);
+ hdev->para->cs = HDMI_COLOR_FORMAT_444;
printf("set cs as %d\n", HDMI_COLOR_FORMAT_444);
}
+ /* For VESA modes, should be RGB format */
+ if (hdev->vic >= HDMITX_VESA_OFFSET) {
+ hdev->para->cs = HDMI_COLOR_FORMAT_RGB;
+ hdev->para->cd = HDMI_COLOR_DEPTH_24B;
+ }
break;
- /* For VESA modes, should be RGB format */
- if (hdmitx_device.vic >= HDMITX_VESA_OFFSET)
- hdmitx_device.para->cs = HDMI_COLOR_FORMAT_RGB;
}
- hdmi_tx_set(&hdmitx_device);
+ printf("set hdmitx VIC = %d CS = %d CD = %d\n",
+ hdev->vic, hdev->para->cs, hdev->para->cd);
+ hdmi_tx_set(hdev);
}
return CMD_RET_SUCCESS;
}
static int do_blank(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
+
if (argc < 1)
return cmd_usage(cmdtp);
if (strcmp(argv[1], "1") == 0)
- hdmitx_device.HWOp.output_blank(1);
+ hdev->hwop.output_blank(1);
if (strcmp(argv[1], "0") == 0)
- hdmitx_device.HWOp.output_blank(0);
+ hdev->hwop.output_blank(0);
return CMD_RET_SUCCESS;
}
static int do_off(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
- hdmitx_device.vic = HDMI_unkown;
- hdmitx_device.HWOp.turn_off();
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
+
+ hdev->vic = HDMI_unkown;
+ hdev->hwop.turn_off();
printf("turn off hdmitx\n");
return 1;
}
static int do_dump(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
- hdmitx_device.HWOp.dump_regs();
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
+
+ hdev->hwop.dump_regs();
return 1;
}
@@ -336,7 +460,7 @@
static int do_info(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
- struct hdmitx_dev *hdev = &hdmitx_device;
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
struct hdmi_format_para *para = hdev->para;
printf("%s %d\n", para->ext_name, hdev->vic);
@@ -345,24 +469,33 @@
return 1;
}
-static int do_get_preferred_mode(cmd_tbl_t * cmdtp, int flag, int argc,
- char * const argv[])
+static int xtochar(int num, char* checksum)
{
- struct hdmitx_dev *hdev = &hdmitx_device;
- unsigned int byte_num = 0;
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
+
+ if (((hdev->rawedid[num] >> 4 ) & 0xf) <= 9)
+ checksum[0] = ((hdev->rawedid[num] >> 4 ) & 0xf) + '0';
+ else
+ checksum[0] = ((hdev->rawedid[num] >> 4 ) & 0xf) -10 + 'a';
+
+ if ((hdev->rawedid[num] & 0xf) <= 9)
+ checksum[1] = (hdev->rawedid[num] & 0xf) + '0';
+ else
+ checksum[1] = (hdev->rawedid[num] & 0xf) -10 + 'a';
+
+ return 0;
+}
+
+static void get_parse_edid_data(struct hdmitx_dev *hdev)
+{
unsigned char *edid = hdev->rawedid;
+ unsigned int byte_num = 0;
unsigned char blk_no = 1;
- struct hdmi_format_para *para;
- char pref_mode[64];
- char color_attr[64];
+ char *hdr_priority = env_get("hdr_priority");
- memset(edid, 0, EDID_BLK_SIZE * EDID_BLK_NO);
- memset(pref_mode, 0, sizeof(pref_mode));
- memset(color_attr, 0, sizeof(color_attr));
-
- /* Read complete EDID data sequentially */
+ /* get edid data */
while (byte_num < 128 * blk_no) {
- hdmitx_device.HWOp.read_edid(&edid[byte_num], byte_num & 0x7f, byte_num / 128);
+ hdev->hwop.read_edid(&edid[byte_num], byte_num & 0x7f, byte_num / 128);
if (byte_num == 120) {
blk_no = edid[126] + 1;
if (blk_no > 4)
@@ -371,30 +504,264 @@
byte_num += 8;
}
- if (hdmi_edid_parsing(hdev->rawedid, &hdev->RXCap) == 0) {
+ if (0)
dump_full_edid(hdev->rawedid);
+
+ /* parse edid data */
+ hdmi_edid_parsing(hdev->rawedid, &hdev->RXCap);
+
+ if (!hdr_priority)
+ return;
+ /* if hdr_priority is 2, then mark both dv_info and hdr_info */
+ if (strcmp(hdr_priority, "2") == 0) {
+ memset(&hdev->RXCap.dv_info, 0, sizeof(struct dv_info));
+ memset(&hdev->RXCap.hdr_info, 0, sizeof(struct hdr_info));
+ memset(&hdev->RXCap.hdr10plus_info, 0, sizeof(struct hdr10_plus_info));
+ pr_info("hdr_priority: %s and clear dv/hdr_info\n", hdr_priority);
+ return;
}
+ /* if hdr_priority is 1, then mark dv_info */
+ if (hdr_priority && (strcmp(hdr_priority, "1") == 0)) {
+ memset(&hdev->RXCap.dv_info, 0, sizeof(struct dv_info));
+ pr_info("hdr_priority: %s and clear dv_info\n", hdr_priority);
+ }
+}
+
+/* policy process: to find the output mode/attr/dv_type */
+void scene_process(struct hdmitx_dev *hdev,
+ scene_output_info_t *scene_output_info)
+{
+ hdmi_data_t hdmidata;
+
+ if (!hdev || !scene_output_info)
+ return;
+ /* 1.read dolby vision mode from prop(maybe need to env) */
+ memset(&hdmidata, 0, sizeof(hdmi_data_t));
+ get_hdmi_data(hdev, &hdmidata);
+
+ /* 2. dolby vision scene process */
+ /* only for tv support dv and box enable dv */
+ if (is_dv_preference(hdev)) {
+ dolbyvision_scene_process(&hdmidata, scene_output_info);
+ } else if (is_dolby_enabled()) {
+ /* for enable dolby vision core when
+ * first boot connecting non dv tv
+ * NOTE: let systemcontrol to enable DV core
+ */
+ /* scene_output_info->final_dv_type = DOLBY_VISION_ENABLE; */
+ } else {
+ /* for UI disable dolby vision core and boot keep the status
+ * NOTE: TBD if need to disable DV here
+ */
+ /* scene_output_info->final_dv_type = DOLBY_VISION_DISABLE; */
+ }
+ /* 3.sdr scene process */
+ /* decide final display mode and deepcolor */
+ if (is_dv_preference(hdev)) {
+ /* do nothing
+ * already done above, just sync with sysctrl
+ */
+ } else if (is_hdr_preference(hdev)) {
+ hdr_scene_process(&hdmidata, scene_output_info);
+ } else {
+ sdr_scene_process(&hdmidata, scene_output_info);
+ }
+ /* not find outputmode and use default mode */
+ if (strlen(scene_output_info->final_displaymode) == 0)
+ strcpy(scene_output_info->final_displaymode, DEFAULT_HDMI_MODE);
+ /* not find color space and use default mode */
+ if (!strstr(scene_output_info->final_deepcolor, "bit"))
+ strcpy(scene_output_info->final_deepcolor, DEFAULT_COLOR_FORMAT);
+}
+
+static int do_get_parse_edid(cmd_tbl_t * cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
+ unsigned char *edid = hdev->rawedid;
+ unsigned char *store_checkvalue;
+ memset(edid, 0, EDID_BLK_SIZE * EDID_BLK_NO);
+ unsigned int i;
+ unsigned int checkvalue[4];
+ unsigned int checkvalue1;
+ unsigned int checkvalue2;
+ char checksum[11];
+ unsigned char def_cksum[] = {'0', 'x', '0', '0', '0', '0', '0', '0', '0', '0', '\0'};
+ char *hdmimode;
+ char *colorattribute;
+ char dv_type[2] = {0};
+ scene_output_info_t scene_output_info;
+ struct hdmi_format_para *para = NULL;
+ bool mode_support = false;
+
+ if (!hdev->hwop.get_hpd_state()) {
+ printf("HDMI HPD low, no need parse EDID\n");
+ return 1;
+ }
+ memset(&scene_output_info, 0, sizeof(scene_output_info_t));
+
+ get_parse_edid_data(hdev);
+
+ /* check if the tv has changed or anything wrong */
+ store_checkvalue = (unsigned char*)env_get("hdmichecksum");
+ colorattribute = env_get("colorattribute");
+ hdmimode = env_get("hdmimode");
+
+ if (!store_checkvalue)
+ store_checkvalue = def_cksum;
+
+ printf("read hdmichecksum: %s, hdmimode: %s, colorattribute: %s\n",
+ store_checkvalue, hdmimode, colorattribute);
+
+ for (i = 0; i < 4; i++) {
+ if (('0' <= store_checkvalue[i * 2 + 2]) && (store_checkvalue[i * 2 + 2] <= '9'))
+ checkvalue1 = store_checkvalue[i * 2 + 2] -'0';
+ else
+ checkvalue1 = store_checkvalue[i * 2 + 2] -'W';
+ if (('0' <= store_checkvalue[i * 2 + 3]) && (store_checkvalue[i * 2 + 3] <= '9'))
+ checkvalue2 = store_checkvalue[i * 2 + 3] -'0';
+ else
+ checkvalue2 = store_checkvalue[i * 2 + 3] -'W';
+ checkvalue[i] = checkvalue1 * 16 + checkvalue2;
+ }
+
+ if ((checkvalue[0] != hdev->rawedid[0x7f]) ||
+ (checkvalue[1] != hdev->rawedid[0xff]) ||
+ (checkvalue[2] != hdev->rawedid[0x17f]) ||
+ (checkvalue[3] != hdev->rawedid[0x1ff])) {
+ hdev->RXCap.edid_changed = 1;
+
+ checksum[0] = '0';
+ checksum[1] = 'x';
+ for (i = 0; i < 4; i++)
+ xtochar(0x80 * i + 0x7f, &checksum[2* i + 2]);
+ checksum[10] = '\0';
+ memcpy(hdev->RXCap.checksum, checksum, 10);
+ printf("TV has changed, now crc: %s\n", checksum);
+ } else {
+ memcpy(hdev->RXCap.checksum, store_checkvalue, 10);
+ printf("TV is the same, checksum: %s\n", hdev->RXCap.checksum);
+ }
+
+ /* check current mode+colorattr support or not */
+ para = hdmi_tst_fmt_name(hdmimode, colorattribute);
+ if (hdmitx_edid_check_valid_mode(hdev, para))
+ mode_support = true;
+ else
+ mode_support = false;
+
+ /* two cases need to go with uboot mode select policy:
+ * 1.TV changed
+ * 2.TV not changed, but current mode(set by sysctrl/hwc)
+ * not supportted by uboot (probably means mode select policy or
+ * edid parse between sysctrl and uboot have some gap)
+ * then need to find proper output mode with uboot policy.
+ */
+ if (hdev->RXCap.edid_changed || !mode_support) {
+ /* find proper mode if EDID changed */
+ scene_process(hdev, &scene_output_info);
+ env_set("hdmichecksum", hdev->RXCap.checksum);
+ if (edid_parsing_ok(hdev)) {
+ /* SWPL-34712: if EDID parsing error case, not save env,
+ * only output default mode(480p,RGB,8bit). after
+ * EDID read OK, systemcontrol will recover the hdmi
+ * mode from env, to avoid keep the default hdmi output
+ */
+ env_set("hdmimode", scene_output_info.final_displaymode);
+ env_set("outputmode",
+ scene_output_info.final_displaymode);
+ env_set("colorattribute",
+ scene_output_info.final_deepcolor);
+ /* if change from DV TV to HDR/SDR TV, don't change
+ * DV status to disabled, as DV core need to be enabled.
+ */
+ if ((scene_output_info.final_dv_type !=
+ get_ubootenv_dv_type()) &&
+ (scene_output_info.final_dv_type !=
+ DOLBY_VISION_DISABLE)) {
+ sprintf(dv_type, "%d", scene_output_info.final_dv_type);
+ env_set("dolby_status", dv_type);
+ /* according to the policy of systemcontrol,
+ * if current DV mode is not supported by TV
+ * EDID, DV type maybe changed to one witch
+ * TV support, and need VPP/DV module to
+ * update new DV output mode.
+ */
+ printf("update dv_type: %d\n",
+ scene_output_info.final_dv_type);
+ }
+ } else {
+ save_default_720p();
+ }
+ printf("update outputmode: %s\n", env_get("outputmode"));
+ printf("update colorattribute: %s\n", env_get("colorattribute"));
+ printf("update hdmichecksum: %s\n", env_get("hdmichecksum"));
+ }
+ hdev->vic = hdmi_get_fmt_vic(env_get("outputmode"));
+ hdev->para = hdmi_get_fmt_paras(hdev->vic);
+ hdmitx_mask_rx_info(hdev);
+ return 0;
+}
+static int do_get_preferred_mode(cmd_tbl_t * cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
+
+ unsigned char *edid = hdev->rawedid;
+
+ struct hdmi_format_para *para;
+ char pref_mode[64];
+ char color_attr[64];
+ char *hdmi_read_edid;
+
+ hdmi_read_edid = env_get("hdmi_read_edid");
+ if (hdmi_read_edid && (hdmi_read_edid[0] == '0'))
+ return 0;
+
+ memset(edid, 0, EDID_BLK_SIZE * EDID_BLK_NO);
+ memset(pref_mode, 0, sizeof(pref_mode));
+ memset(color_attr, 0, sizeof(color_attr));
+
+ /* If sink is not detected there is a still a good chance it supports proper modes */
+ /* 720p is chosen as a safe compromise: supported by most sinks and looks good enough */
+ if (!hdev->hwop.get_hpd_state()) {
+ para = hdmi_get_fmt_paras(HDMI_1280x720p60_16x9);
+ snprintf(pref_mode, sizeof(pref_mode), "%s", para->sname);
+ snprintf(color_attr, sizeof(color_attr), "%s", "rgb,8bit");
+ printk("no sink, fallback to %s[%d]\n", para->sname, HDMI_1280x720p60_16x9);
+ goto bypass_edid_read;
+ }
+
+ get_parse_edid_data(hdev);
+
para = hdmi_get_fmt_paras(hdev->RXCap.preferred_mode);
+
if (para) {
- sprintf(pref_mode, "setenv hdmimode %s", para->sname);
+ sprintf(pref_mode, "preferred_mode %s", para->sname);
if (hdev->RXCap.pref_colorspace & (1 << 5))
sprintf(color_attr, "setenv colorattribute %s", "444,8bit");
else if (hdev->RXCap.pref_colorspace & (1 << 4))
sprintf(color_attr, "setenv colorattribute %s", "422,8bit");
else
sprintf(color_attr, "setenv colorattribute %s", "rgb,8bit");
- } else { /* set default mode */
+ } else {
hdev->RXCap.preferred_mode = HDMI_720x480p60_16x9;
para = hdmi_get_fmt_paras(HDMI_720x480p60_16x9);
sprintf(pref_mode, "setenv hdmimode %s", para->sname);
sprintf(color_attr, "setenv colorattribute %s", "444,8bit");
}
- printk("edid preferred_mode is %s[%d]\n", para->sname, hdev->RXCap.preferred_mode);
+ printk("sink preferred_mode is %s[%d]\n", para->sname, hdev->RXCap.preferred_mode);
+bypass_edid_read:
/* save to ENV */
+ /*
run_command(pref_mode, 0);
run_command(color_attr, 0);
run_command("saveenv", 0);
+ */
+ printk("hdr mode is %d\n", hdev->RXCap.hdr_info.hdr_sup_eotf_smpte_st_2084);
+ printk("dv mode is ver:%d len: %x\n", hdev->RXCap.dv_info.ver, hdev->RXCap.dv_info.length);
+ printk("hdr10+ mode is %d\n", hdev->RXCap.hdr10plus_info.application_version);
return 0;
}
@@ -410,6 +777,7 @@
U_BOOT_CMD_MKENT(info, 1, 1, do_info, "", ""),
U_BOOT_CMD_MKENT(get_preferred_mode, 1, 1, do_get_preferred_mode, "", ""),
U_BOOT_CMD_MKENT(reg, 3, 1, do_reg, "", ""),
+ U_BOOT_CMD_MKENT(get_parse_edid, 1, 1, do_get_parse_edid, "", ""),
};
static int do_hdmitx(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
@@ -432,7 +800,7 @@
U_BOOT_CMD(hdmitx, CONFIG_SYS_MAXARGS, 0, do_hdmitx,
"HDMITX sub-system",
- "hdmitx version:20181013\n"
+ "hdmitx version:20200618\n"
"hdmitx hpd\n"
" Detect hdmi rx plug-in\n"
"hdmitx get_preferred_mode\n"
@@ -456,3 +824,10 @@
"hdmitx rx_det\n"
" Auto detect if RX is FBC and set outputmode\n"
);
+
+struct hdr_info *hdmitx_get_rx_hdr_info(void)
+{
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
+
+ return &hdev->RXCap.hdr_info;
+}
diff --git a/cmd/amlogic/cmd_lcd.c b/cmd/amlogic/cmd_lcd.c
index 68e81da..c508a3a 100644
--- a/cmd/amlogic/cmd_lcd.c
+++ b/cmd/amlogic/cmd_lcd.c
@@ -1,138 +1,114 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include <common.h>
#include <command.h>
+#include <malloc.h>
#include <amlogic/media/vout/lcd/aml_lcd.h>
+static unsigned int lcd_parse_vout_name(char *name)
+{
+ char *p, *frac_str;
+ unsigned int frac = 0;
+
+ p = strchr(name, ',');
+ if (!p) {
+ frac = 0;
+ } else {
+ frac_str = p + 1;
+ *p = '\0';
+ if (strcmp(frac_str, "frac") == 0)
+ frac = 1;
+ }
+
+ return frac;
+}
+
static int do_lcd_probe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();;
-
- if (lcd_drv == NULL) {
- printf("no lcd driver\n");
- return 0;
- }
-
- if (lcd_drv->lcd_probe)
- lcd_drv->lcd_probe();
- else
- printf("no lcd probe\n");
+ aml_lcd_driver_probe(0);
return 0;
}
static int do_lcd_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- char *mode;
+ char *mode, *str;
+ unsigned int frac;
- if (lcd_drv == NULL) {
- printf("no lcd driver\n");
- return 0;
+ str = env_get("outputmode");
+ if (!str) {
+ printf("no outputmode\n");
+ return -1;
}
- mode = env_get("outputmode");
- if (lcd_drv->lcd_enable)
- lcd_drv->lcd_enable(mode);
- else
- printf("no lcd enable\n");
+ mode = (char *)malloc(64);
+ if (!mode) {
+ printf("%s: create mode failed\n", __func__);
+ return -1;
+ }
+ memset(mode, 0, 64);
+ sprintf(mode, "%s", str);
+ frac = lcd_parse_vout_name(mode);
+
+ aml_lcd_driver_enable(0, mode, frac);
+
+ free(mode);
return 0;
}
static int do_lcd_disable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
-
- if (lcd_drv == NULL) {
- printf("no lcd driver\n");
- return 0;
- }
-
- if (lcd_drv->lcd_disable)
- lcd_drv->lcd_disable();
- else
- printf("no lcd disable\n");
+ aml_lcd_driver_disable(0);
return 0;
}
static int do_lcd_ss(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- int level;
+ int value, temp;
int ret = 0;
- if (argc == 1) {
+ if (argc == 1)
return -1;
- }
- if (lcd_drv == NULL) {
- printf("no lcd driver\n");
- return 0;
- }
- if (strcmp(argv[1], "set") == 0) {
+ if (strcmp(argv[1], "level") == 0) {
if (argc == 3) {
- level = (int)simple_strtoul(argv[2], NULL, 10);
- if (lcd_drv->lcd_set_ss)
- lcd_drv->lcd_set_ss(level);
- else
- printf("no lcd lcd_set_ss\n");
+ value = (unsigned int)simple_strtoul(argv[2], NULL, 10);
+ value &= 0xff;
+ aml_lcd_driver_set_ss(0, value, 0xff, 0xff);
} else {
ret = -1;
}
- } else if (strcmp(argv[1], "get") == 0) {
- if (lcd_drv->lcd_get_ss)
- printf("lcd_get_ss: %s\n", lcd_drv->lcd_get_ss());
- else
- printf("no lcd_get_ss\n");
- } else {
- ret = -1;
- }
- return ret;
-}
-
-static int do_lcd_bl(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- unsigned int level;
- int ret = 0;
-
- if (argc == 1) {
- return -1;
- }
-
- if (lcd_drv == NULL) {
- printf("no lcd driver\n");
- return 0;
- }
- if (strcmp(argv[1], "on") == 0) {
- if (lcd_drv->bl_power_ctrl)
- lcd_drv->bl_power_ctrl(1);
- else
- printf("no lcd bl_power_ctrl\n");
- } else if (strcmp(argv[1], "off") == 0) {
- if (lcd_drv->bl_power_ctrl)
- lcd_drv->bl_power_ctrl(0);
- else
- printf("no lcd bl_power_ctrl\n");
+ } else if (strcmp(argv[1], "freq") == 0) {
+ if (argc == 3) {
+ value = (unsigned int)simple_strtoul(argv[2], NULL, 10);
+ value &= 0xf;
+ aml_lcd_driver_set_ss(0, 0xff, value, 0xff);
+ } else {
+ ret = -1;
+ }
+ } else if (strcmp(argv[1], "mode") == 0) {
+ if (argc == 3) {
+ value = (unsigned int)simple_strtoul(argv[2], NULL, 10);
+ value &= 0xf;
+ aml_lcd_driver_set_ss(0, 0xff, 0xff, value);
+ } else {
+ ret = -1;
+ }
} else if (strcmp(argv[1], "set") == 0) {
if (argc == 3) {
- level = (unsigned int)simple_strtoul(argv[2], NULL, 10);
- if (lcd_drv->bl_set_level)
- lcd_drv->bl_set_level(level);
- else
- printf("no lcd bl_set_level\n");
+ value = (unsigned int)simple_strtoul(argv[2], NULL, 16);
+ value &= 0xffff;
+ temp = value >> 8;
+ aml_lcd_driver_set_ss(0, (value & 0xff),
+ ((temp >> LCD_CLK_SS_BIT_FREQ) & 0xf),
+ ((temp >> LCD_CLK_SS_BIT_MODE) & 0xf));
} else {
ret = -1;
}
} else if (strcmp(argv[1], "get") == 0) {
- if (lcd_drv->bl_get_level) {
- level = lcd_drv->bl_get_level();
- printf("lcd bl_get_level: %d\n", level);
- } else {
- printf("no lcd bl_get_level\n");
- }
- } else if (strcmp(argv[1], "info") == 0) {
- if (lcd_drv->bl_config_print)
- lcd_drv->bl_config_print();
- else
- printf("no lcd bl_config_print\n");
+ aml_lcd_driver_get_ss(0);
} else {
ret = -1;
}
@@ -141,176 +117,957 @@
static int do_lcd_clk(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
-
- if (lcd_drv == NULL) {
- printf("no lcd driver\n");
- return 0;
- }
-
- if (lcd_drv->lcd_info)
- lcd_drv->lcd_clk();
- else
- printf("no lcd clk\n");
+ aml_lcd_driver_clk_info(0);
return 0;
}
static int do_lcd_info(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
-
- if (lcd_drv == NULL) {
- printf("no lcd driver\n");
- return 0;
- }
-
- if (lcd_drv->lcd_info)
- lcd_drv->lcd_info();
- else
- printf("no lcd info\n");
+ aml_lcd_driver_info(0);
return 0;
}
+#ifdef CONFIG_AML_LCD_TCON
static int do_lcd_tcon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- int ret = 0;
+ struct lcd_drv_s *lcd_drv = lcd_get_driver(0);
+ unsigned int addr, val, len;
+ int ret = 0, i;
- if (argc == 1) {
+ if (argc == 1)
return -1;
- }
- if (lcd_drv == NULL) {
+ if (!lcd_drv) {
printf("no lcd driver\n");
return 0;
}
if (strcmp(argv[1], "reg") == 0) {
- if (lcd_drv->lcd_tcon_reg)
- lcd_drv->lcd_tcon_reg();
+ if (lcd_drv->lcd_tcon_reg_print)
+ lcd_drv->lcd_tcon_reg_print();
else
- printf("no lcd tcon_reg\n");
+ printf("no lcd tcon_reg_print\n");
} else if (strcmp(argv[1], "table") == 0) {
- if (lcd_drv->lcd_tcon_table)
- lcd_drv->lcd_tcon_table();
+ if (lcd_drv->lcd_tcon_table_print)
+ lcd_drv->lcd_tcon_table_print();
else
- printf("no lcd tcon_table\n");
+ printf("no lcd tcon_table_print\n");
+ } else if (strcmp(argv[1], "tw") == 0) {
+ addr = (unsigned int)simple_strtoul(argv[2], NULL, 16);
+ val = (unsigned int)simple_strtoul(argv[3], NULL, 16);
+ if (lcd_drv->lcd_tcon_table_write) {
+ val = lcd_drv->lcd_tcon_table_write(addr, val);
+ printf("write tcon table[0x%04x] = 0x%02x\n",
+ addr, val);
+ } else {
+ printf("no lcd_tcon_table_write\n");
+ }
+ } else if (strcmp(argv[1], "tr") == 0) {
+ addr = (unsigned int)simple_strtoul(argv[2], NULL, 16);
+ if (lcd_drv->lcd_tcon_table_read) {
+ val = lcd_drv->lcd_tcon_table_read(addr);
+ printf("read tcon table[0x%04x] = 0x%02x\n",
+ addr, val);
+ } else {
+ printf("no lcd_tcon_table_write\n");
+ }
+ } else if (strcmp(argv[1], "wb") == 0) {
+ if (lcd_drv->lcd_tcon_reg_write) {
+ addr = (unsigned int)simple_strtoul(argv[2], NULL, 16);
+ val = (unsigned int)simple_strtoul(argv[3], NULL, 16);
+ lcd_drv->lcd_tcon_reg_write(addr, val, 1);
+ printf
+ ("tcon byte write: 0x%04x = 0x%02x, readback 0x%02x\n",
+ addr, val, lcd_drv->lcd_tcon_reg_read(addr, 1));
+ } else {
+ printf("no lcd_tcon_reg_write\n");
+ }
+ } else if (strcmp(argv[1], "rb") == 0) {
+ if (lcd_drv->lcd_tcon_reg_read) {
+ addr = (unsigned int)simple_strtoul(argv[2], NULL, 16);
+ val = lcd_drv->lcd_tcon_reg_read(addr, 1);
+ printf("tcon byte read: 0x%04x = 0x%02x\n", addr, val);
+ } else {
+ printf("no lcd_tcon_reg_read\n");
+ }
+ } else if (strcmp(argv[1], "db") == 0) {
+ if (lcd_drv->lcd_tcon_reg_read) {
+ addr = (unsigned int)simple_strtoul(argv[2], NULL, 16);
+ len = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+ printf("tcon byte reg dump:\n");
+ for (i = 0; i < len; i++) {
+ val = lcd_drv->lcd_tcon_reg_read((addr + i), 1);
+ printf(" 0x%04x = 0x%02x\n", (addr + i), val);
+ }
+ } else {
+ printf("no lcd_tcon_reg_read\n");
+ }
+ } else if (strcmp(argv[1], "w") == 0) {
+ if (lcd_drv->lcd_tcon_reg_write) {
+ addr = (unsigned int)simple_strtoul(argv[2], NULL, 16);
+ val = (unsigned int)simple_strtoul(argv[3], NULL, 16);
+ lcd_drv->lcd_tcon_reg_write(addr, val, 0);
+ printf("tcon write: 0x%04x = 0x%08x, readback 0x%08x\n",
+ addr, val, lcd_drv->lcd_tcon_reg_read(addr, 0));
+ } else {
+ printf("no lcd_tcon_reg_write\n");
+ }
+ } else if (strcmp(argv[1], "r") == 0) {
+ if (lcd_drv->lcd_tcon_reg_read) {
+ addr = (unsigned int)simple_strtoul(argv[2], NULL, 16);
+ val = lcd_drv->lcd_tcon_reg_read(addr, 0);
+ printf("tcon read: 0x%04x = 0x%08x\n", addr, val);
+ } else {
+ printf("no lcd_tcon_reg_read\n");
+ }
+ } else if (strcmp(argv[1], "d") == 0) {
+ if (lcd_drv->lcd_tcon_reg_read) {
+ addr = (unsigned int)simple_strtoul(argv[2], NULL, 16);
+ len = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+ printf("tcon reg dump:\n");
+ for (i = 0; i < len; i++) {
+ val = lcd_drv->lcd_tcon_reg_read((addr + i), 0);
+ printf(" 0x%04x = 0x%08x\n", (addr + i), val);
+ }
+ } else {
+ printf("no lcd_tcon_reg_read\n");
+ }
+ } else if (strcmp(argv[1], "vac") == 0) {
+ if (lcd_drv->lcd_tcon_vac_print)
+ lcd_drv->lcd_tcon_vac_print();
+ else
+ printf("no lcd tcon_vac_print\n");
+ } else if (strcmp(argv[1], "demura") == 0) {
+ if (lcd_drv->lcd_tcon_demura_print)
+ lcd_drv->lcd_tcon_demura_print();
+ else
+ printf("no lcd tcon_demura_print\n");
+ } else if (strcmp(argv[1], "acc") == 0) {
+ if (lcd_drv->lcd_tcon_acc_print)
+ lcd_drv->lcd_tcon_acc_print();
+ else
+ printf("no lcd tcon_acc_print\n");
+ } else if (strcmp(argv[1], "data") == 0) {
+ if (argc == 3) {
+ i = (unsigned char)simple_strtoul(argv[2], NULL, 10);
+ if (lcd_drv->lcd_tcon_data_print)
+ lcd_drv->lcd_tcon_data_print(i);
+ else
+ printf("no lcd tcon_data_print\n");
+ } else {
+ if (lcd_drv->lcd_tcon_data_print)
+ lcd_drv->lcd_tcon_data_print(0xff);
+ else
+ printf("no lcd tcon_data_print\n");
+ }
+ } else if (strcmp(argv[1], "spi") == 0) {
+ if (lcd_drv->lcd_tcon_spi_print)
+ lcd_drv->lcd_tcon_spi_print();
+ else
+ printf("no lcd tcon_spi_print\n");
+ } else {
+ ret = -1;
+ }
+ return ret;
+}
+#endif
+
+static int do_lcd_vbyone(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int ret = 0;
+
+ if (argc == 1)
+ return -1;
+
+ if (strcmp(argv[1], "rst") == 0)
+ aml_lcd_vbyone_rst(0);
+ else if (strcmp(argv[1], "cdr") == 0)
+ aml_lcd_vbyone_cdr(0);
+ else
+ ret = -1;
+
+ return ret;
+}
+
+static int do_lcd_reg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ aml_lcd_driver_reg_info(0);
+ return 0;
+}
+
+static int do_lcd_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int num;
+
+ if (argc == 1)
+ return -1;
+
+ num = (unsigned int)simple_strtoul(argv[1], NULL, 10);
+ aml_lcd_driver_test(0, num);
+ return 0;
+}
+
+static int do_lcd_prbs(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ unsigned int s, prbs_mode_flag;
+
+ if (argc == 1)
+ return -1;
+
+ if (strcmp(argv[1], "vx1") == 0) {
+ if (argc == 3)
+ prbs_mode_flag = LCD_PRBS_MODE_VX1;
+ else
+ return -1;
+ } else if (strcmp(argv[1], "lvds") == 0) {
+ if (argc == 3)
+ prbs_mode_flag = LCD_PRBS_MODE_LVDS;
+ else
+ return -1;
+ } else {
+ prbs_mode_flag = LCD_PRBS_MODE_LVDS | LCD_PRBS_MODE_VX1;
+ }
+
+ s = (unsigned int)simple_strtoul(argv[2], NULL, 10);
+ aml_lcd_driver_prbs(0, s, prbs_mode_flag);
+ return 0;
+}
+
+static int do_lcd_key(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int tmp = 0;
+
+ if (argc == 1)
+ return -1;
+
+ if (strcmp(argv[1], "dump") == 0) {
+ if (argc == 3) {
+ if (strcmp(argv[2], "tcon") == 0)
+ tmp = (1 << 1);
+ else
+ tmp = (1 << 0);
+ } else {
+ tmp = (1 << 0);
+ }
+ aml_lcd_driver_unifykey_dump(0, tmp);
+ }
+ return 0;
+}
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static int do_lcd_ext(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int temp;
+
+ if (argc == 1)
+ return -1;
+
+ if (strcmp(argv[1], "info") == 0) {
+ aml_lcd_driver_ext_info(0);
+ } else if (strcmp(argv[1], "power") == 0) {
+ if (argc < 3)
+ return -1;
+ temp = simple_strtoul(argv[2], NULL, 10);
+ if (temp)
+ aml_lcd_driver_ext_power_on(0);
+ else
+ aml_lcd_driver_ext_power_off(0);
+ }
+
+ return 0;
+}
+#endif
+
+static int do_lcd_bl(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int level;
+ int ret = 0;
+
+ if (argc == 1)
+ return -1;
+
+ if (strcmp(argv[1], "on") == 0) {
+ aml_lcd_driver_bl_on(0);
+ } else if (strcmp(argv[1], "off") == 0) {
+ aml_lcd_driver_bl_off(0);
+ } else if (strcmp(argv[1], "set") == 0) {
+ if (argc == 3) {
+ level = (unsigned int)simple_strtoul(argv[2], NULL, 10);
+ aml_lcd_driver_set_bl_level(0, level);
+ } else {
+ ret = -1;
+ }
+ } else if (strcmp(argv[1], "get") == 0) {
+ level = aml_lcd_driver_get_bl_level(0);
+ printf("lcd2 get_bl_level: %d\n", level);
+ } else if (strcmp(argv[1], "info") == 0) {
+ aml_lcd_driver_bl_config_print(0);
} else {
ret = -1;
}
return ret;
}
-static int do_lcd_reg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_lcd1_probe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
-
- if (lcd_drv == NULL) {
- printf("no lcd driver\n");
- return 0;
- }
-
- if (lcd_drv->lcd_reg)
- lcd_drv->lcd_reg();
- else
- printf("no lcd reg\n");
+ aml_lcd_driver_probe(1);
return 0;
}
-static int do_lcd_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_lcd1_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- unsigned int num;
+ char *mode, *str;
+ unsigned int frac;
- if (argc == 1) {
+ str = env_get("outputmode2");
+ if (!str) {
+ printf("no outputmode2\n");
return -1;
}
- if (lcd_drv == NULL) {
- printf("no lcd driver\n");
- return 0;
- }
- num = (unsigned int)simple_strtoul(argv[1], NULL, 10);
- if (lcd_drv->lcd_test)
- lcd_drv->lcd_test(num);
- else
- printf("no lcd_test\n");
+ mode = (char *)malloc(64);
+ if (!mode) {
+ printf("%s: create mode failed\n", __func__);
+ return -1;
+ }
+ memset(mode, 0, 64);
+ sprintf(mode, "%s", str);
+ frac = lcd_parse_vout_name(mode);
+
+ aml_lcd_driver_enable(1, mode, frac);
+
+ free(mode);
return 0;
}
-static int do_lcd_key(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+static int do_lcd1_disable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- int tmp;
+ aml_lcd_driver_disable(1);
+ return 0;
+}
- if (argc == 1) {
+static int do_lcd1_ss(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int value, temp;
+ int ret = 0;
+
+ if (argc == 1)
return -1;
- }
- if (lcd_drv == NULL) {
- printf("no lcd driver\n");
- return 0;
- }
- if (strcmp(argv[1], "flag") == 0) {
+ if (strcmp(argv[1], "level") == 0) {
if (argc == 3) {
- tmp = (int)simple_strtoul(argv[2], NULL, 10);
- lcd_drv->unifykey_test_flag = tmp;
- if (tmp) {
- printf("enable lcd unifykey test\n");
- printf("Be Careful!! This test will overwrite lcd unifykeys!!\n");
- } else {
- printf("disable lcd unifykey test\n");
+ value = (unsigned int)simple_strtoul(argv[2], NULL, 10);
+ value &= 0xff;
+ aml_lcd_driver_set_ss(1, value, 0xff, 0xff);
+ } else {
+ ret = -1;
+ }
+ } else if (strcmp(argv[1], "freq") == 0) {
+ if (argc == 3) {
+ value = (unsigned int)simple_strtoul(argv[2], NULL, 10);
+ value &= 0xf;
+ aml_lcd_driver_set_ss(1, 0xff, value, 0xff);
+ } else {
+ ret = -1;
+ }
+ } else if (strcmp(argv[1], "mode") == 0) {
+ if (argc == 3) {
+ value = (unsigned int)simple_strtoul(argv[2], NULL, 10);
+ value &= 0xf;
+ aml_lcd_driver_set_ss(1, 0xff, 0xff, value);
+ } else {
+ ret = -1;
+ }
+ } else if (strcmp(argv[1], "set") == 0) {
+ if (argc == 3) {
+ value = (unsigned int)simple_strtoul(argv[2], NULL, 16);
+ value &= 0xffff;
+ temp = value >> 8;
+ aml_lcd_driver_set_ss(1, (value & 0xff),
+ ((temp >> LCD_CLK_SS_BIT_FREQ) & 0xf),
+ ((temp >> LCD_CLK_SS_BIT_MODE) & 0xf));
+ } else {
+ ret = -1;
+ }
+ } else if (strcmp(argv[1], "get") == 0) {
+ aml_lcd_driver_get_ss(1);
+ } else {
+ ret = -1;
+ }
+ return ret;
+}
+
+static int do_lcd1_clk(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ aml_lcd_driver_clk_info(1);
+ return 0;
+}
+
+static int do_lcd1_info(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ aml_lcd_driver_info(1);
+ return 0;
+}
+
+#ifdef CONFIG_AML_LCD_TCON
+static int do_lcd1_tcon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ struct lcd_drv_s *lcd_drv = lcd_get_driver(1);
+ unsigned int addr, val, len;
+ int ret = 0, i;
+
+ if (argc == 1)
+ return -1;
+
+ if (!lcd_drv) {
+ printf("no lcd driver\n");
+ return 0;
+ }
+ if (strcmp(argv[1], "reg") == 0) {
+ if (lcd_drv->lcd_tcon_reg_print)
+ lcd_drv->lcd_tcon_reg_print();
+ else
+ printf("no lcd tcon_reg_print\n");
+ } else if (strcmp(argv[1], "table") == 0) {
+ if (lcd_drv->lcd_tcon_table_print)
+ lcd_drv->lcd_tcon_table_print();
+ else
+ printf("no lcd tcon_table_print\n");
+ } else if (strcmp(argv[1], "tw") == 0) {
+ addr = (unsigned int)simple_strtoul(argv[2], NULL, 16);
+ val = (unsigned int)simple_strtoul(argv[3], NULL, 16);
+ if (lcd_drv->lcd_tcon_table_write) {
+ val = lcd_drv->lcd_tcon_table_write(addr, val);
+ printf("write tcon table[0x%04x] = 0x%02x\n",
+ addr, val);
+ } else {
+ printf("no lcd_tcon_table_write\n");
+ }
+ } else if (strcmp(argv[1], "tr") == 0) {
+ addr = (unsigned int)simple_strtoul(argv[2], NULL, 16);
+ if (lcd_drv->lcd_tcon_table_read) {
+ val = lcd_drv->lcd_tcon_table_read(addr);
+ printf("read tcon table[0x%04x] = 0x%02x\n",
+ addr, val);
+ } else {
+ printf("no lcd_tcon_table_write\n");
+ }
+ } else if (strcmp(argv[1], "wb") == 0) {
+ if (lcd_drv->lcd_tcon_reg_write) {
+ addr = (unsigned int)simple_strtoul(argv[2], NULL, 16);
+ val = (unsigned int)simple_strtoul(argv[3], NULL, 16);
+ lcd_drv->lcd_tcon_reg_write(addr, val, 1);
+ printf
+ ("tcon byte write: 0x%04x = 0x%02x, readback 0x%02x\n",
+ addr, val, lcd_drv->lcd_tcon_reg_read(addr, 1));
+ } else {
+ printf("no lcd_tcon_reg_write\n");
+ }
+ } else if (strcmp(argv[1], "rb") == 0) {
+ if (lcd_drv->lcd_tcon_reg_read) {
+ addr = (unsigned int)simple_strtoul(argv[2], NULL, 16);
+ val = lcd_drv->lcd_tcon_reg_read(addr, 1);
+ printf("tcon byte read: 0x%04x = 0x%02x\n", addr, val);
+ } else {
+ printf("no lcd_tcon_reg_read\n");
+ }
+ } else if (strcmp(argv[1], "db") == 0) {
+ if (lcd_drv->lcd_tcon_reg_read) {
+ addr = (unsigned int)simple_strtoul(argv[2], NULL, 16);
+ len = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+ printf("tcon byte reg dump:\n");
+ for (i = 0; i < len; i++) {
+ val = lcd_drv->lcd_tcon_reg_read((addr + i), 1);
+ printf(" 0x%04x = 0x%02x\n", (addr + i), val);
}
} else {
- return -1;
+ printf("no lcd_tcon_reg_read\n");
}
- } else if (strcmp(argv[1], "test") == 0) {
- if (lcd_drv->unifykey_test)
- lcd_drv->unifykey_test();
+ } else if (strcmp(argv[1], "w") == 0) {
+ if (lcd_drv->lcd_tcon_reg_write) {
+ addr = (unsigned int)simple_strtoul(argv[2], NULL, 16);
+ val = (unsigned int)simple_strtoul(argv[3], NULL, 16);
+ lcd_drv->lcd_tcon_reg_write(addr, val, 0);
+ printf("tcon write: 0x%04x = 0x%08x, readback 0x%08x\n",
+ addr, val, lcd_drv->lcd_tcon_reg_read(addr, 0));
+ } else {
+ printf("no lcd_tcon_reg_write\n");
+ }
+ } else if (strcmp(argv[1], "r") == 0) {
+ if (lcd_drv->lcd_tcon_reg_read) {
+ addr = (unsigned int)simple_strtoul(argv[2], NULL, 16);
+ val = lcd_drv->lcd_tcon_reg_read(addr, 0);
+ printf("tcon read: 0x%04x = 0x%08x\n", addr, val);
+ } else {
+ printf("no lcd_tcon_reg_read\n");
+ }
+ } else if (strcmp(argv[1], "d") == 0) {
+ if (lcd_drv->lcd_tcon_reg_read) {
+ addr = (unsigned int)simple_strtoul(argv[2], NULL, 16);
+ len = (unsigned int)simple_strtoul(argv[3], NULL, 10);
+ printf("tcon reg dump:\n");
+ for (i = 0; i < len; i++) {
+ val = lcd_drv->lcd_tcon_reg_read((addr + i), 0);
+ printf(" 0x%04x = 0x%08x\n", (addr + i), val);
+ }
+ } else {
+ printf("no lcd_tcon_reg_read\n");
+ }
+ } else if (strcmp(argv[1], "vac") == 0) {
+ if (lcd_drv->lcd_tcon_vac_print)
+ lcd_drv->lcd_tcon_vac_print();
else
- printf("no lcd unifykey_test\n");
- } else if (strcmp(argv[1], "tcon") == 0) {
- if (lcd_drv->unifykey_tcon_test)
- lcd_drv->unifykey_tcon_test();
+ printf("no lcd tcon_vac_print\n");
+ } else if (strcmp(argv[1], "demura") == 0) {
+ if (lcd_drv->lcd_tcon_demura_print)
+ lcd_drv->lcd_tcon_demura_print();
else
- printf("no lcd unifykey_dump\n");
- } else if (strcmp(argv[1], "dump") == 0) {
- if (lcd_drv->unifykey_dump)
- lcd_drv->unifykey_dump();
+ printf("no lcd tcon_demura_print\n");
+ } else if (strcmp(argv[1], "acc") == 0) {
+ if (lcd_drv->lcd_tcon_acc_print)
+ lcd_drv->lcd_tcon_acc_print();
else
- printf("no lcd unifykey_dump\n");
+ printf("no lcd tcon_acc_print\n");
+ } else if (strcmp(argv[1], "data") == 0) {
+ if (argc == 3) {
+ i = (unsigned char)simple_strtoul(argv[2], NULL, 10);
+ if (lcd_drv->lcd_tcon_data_print)
+ lcd_drv->lcd_tcon_data_print(i);
+ else
+ printf("no lcd tcon_data_print\n");
+ } else {
+ if (lcd_drv->lcd_tcon_data_print)
+ lcd_drv->lcd_tcon_data_print(0xff);
+ else
+ printf("no lcd tcon_data_print\n");
+ }
+ } else if (strcmp(argv[1], "spi") == 0) {
+ if (lcd_drv->lcd_tcon_spi_print)
+ lcd_drv->lcd_tcon_spi_print();
+ else
+ printf("no lcd tcon_spi_print\n");
+ } else {
+ ret = -1;
+ }
+ return ret;
+}
+#endif
+
+static int do_lcd1_vbyone(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int ret = 0;
+
+ if (argc == 1)
+ return -1;
+
+ if (strcmp(argv[1], "rst") == 0)
+ aml_lcd_vbyone_rst(1);
+ else if (strcmp(argv[1], "cdr") == 0)
+ aml_lcd_vbyone_cdr(1);
+ else
+ ret = -1;
+
+ return ret;
+}
+
+static int do_lcd1_reg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ aml_lcd_driver_reg_info(1);
+ return 0;
+}
+
+static int do_lcd1_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int num;
+
+ if (argc == 1)
+ return -1;
+
+ num = (unsigned int)simple_strtoul(argv[1], NULL, 10);
+ aml_lcd_driver_test(1, num);
+ return 0;
+}
+
+static int do_lcd1_prbs(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int s, prbs_mode_flag;
+
+ if (argc == 1)
+ return -1;
+
+ if (strcmp(argv[1], "vx1") == 0) {
+ if (argc == 3)
+ prbs_mode_flag = LCD_PRBS_MODE_VX1;
+ else
+ return -1;
+ } else if (strcmp(argv[1], "lvds") == 0) {
+ if (argc == 3)
+ prbs_mode_flag = LCD_PRBS_MODE_LVDS;
+ else
+ return -1;
+ } else {
+ prbs_mode_flag = LCD_PRBS_MODE_LVDS | LCD_PRBS_MODE_VX1;
+ }
+
+ s = (unsigned int)simple_strtoul(argv[2], NULL, 10);
+ aml_lcd_driver_prbs(1, s, prbs_mode_flag);
+ return 0;
+}
+
+static int do_lcd1_key(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int tmp = 0;
+
+ if (argc == 1)
+ return -1;
+
+ if (strcmp(argv[1], "dump") == 0) {
+ if (argc == 3) {
+ if (strcmp(argv[2], "tcon") == 0)
+ tmp = (1 << 1);
+ else
+ tmp = (1 << 0);
+ } else {
+ tmp = (1 << 0);
+ }
+ aml_lcd_driver_unifykey_dump(1, tmp);
}
return 0;
}
-static int do_lcd_ext(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+#ifdef CONFIG_AML_LCD_EXTERN
+static int do_lcd1_ext(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
+ unsigned int temp;
- if (lcd_drv == NULL) {
- printf("no lcd driver\n");
- return 0;
+ if (argc == 1)
+ return -1;
+
+ if (strcmp(argv[1], "info") == 0) {
+ aml_lcd_driver_ext_info(1);
+ } else if (strcmp(argv[1], "power") == 0) {
+ if (argc < 3)
+ return -1;
+ temp = simple_strtoul(argv[2], NULL, 10);
+ if (temp)
+ aml_lcd_driver_ext_power_on(1);
+ else
+ aml_lcd_driver_ext_power_off(1);
}
- if (lcd_drv->lcd_extern_info)
- lcd_drv->lcd_extern_info();
- else
- printf("no lcd lcd_extern_info\n");
return 0;
}
+#endif
+
+static int do_lcd1_bl(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int level;
+ int ret = 0;
+
+ if (argc == 1)
+ return -1;
+
+ if (strcmp(argv[1], "on") == 0) {
+ aml_lcd_driver_bl_on(1);
+ } else if (strcmp(argv[1], "off") == 0) {
+ aml_lcd_driver_bl_off(1);
+ } else if (strcmp(argv[1], "set") == 0) {
+ if (argc == 3) {
+ level = (unsigned int)simple_strtoul(argv[2], NULL, 10);
+ aml_lcd_driver_set_bl_level(1, level);
+ } else {
+ ret = -1;
+ }
+ } else if (strcmp(argv[1], "get") == 0) {
+ level = aml_lcd_driver_get_bl_level(1);
+ printf("lcd2 get_bl_level: %d\n", level);
+ } else if (strcmp(argv[1], "info") == 0) {
+ aml_lcd_driver_bl_config_print(1);
+ } else {
+ ret = -1;
+ }
+ return ret;
+}
+
+static int do_lcd2_probe(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ aml_lcd_driver_probe(2);
+ return 0;
+}
+
+static int do_lcd2_enable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char *mode, *str;
+ unsigned int frac;
+
+ str = env_get("outputmode3");
+ if (!str) {
+ printf("no outputmode3\n");
+ return -1;
+ }
+
+ mode = (char *)malloc(64);
+ if (!mode) {
+ printf("%s: create mode failed\n", __func__);
+ return -1;
+ }
+ memset(mode, 0, 64);
+ sprintf(mode, "%s", str);
+ frac = lcd_parse_vout_name(mode);
+
+ aml_lcd_driver_enable(2, mode, frac);
+
+ free(mode);
+ return 0;
+}
+
+static int do_lcd2_disable(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ aml_lcd_driver_disable(2);
+ return 0;
+}
+
+static int do_lcd2_ss(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int value, temp;
+ int ret = 0;
+
+ if (argc == 1)
+ return -1;
+
+ if (strcmp(argv[1], "level") == 0) {
+ if (argc == 3) {
+ value = (unsigned int)simple_strtoul(argv[2], NULL, 10);
+ value &= 0xff;
+ aml_lcd_driver_set_ss(2, value, 0xff, 0xff);
+ } else {
+ ret = -1;
+ }
+ } else if (strcmp(argv[1], "freq") == 0) {
+ if (argc == 3) {
+ value = (unsigned int)simple_strtoul(argv[2], NULL, 10);
+ value &= 0xf;
+ aml_lcd_driver_set_ss(2, 0xff, value, 0xff);
+ } else {
+ ret = -1;
+ }
+ } else if (strcmp(argv[1], "mode") == 0) {
+ if (argc == 3) {
+ value = (unsigned int)simple_strtoul(argv[2], NULL, 10);
+ value &= 0xf;
+ aml_lcd_driver_set_ss(2, 0xff, 0xff, value);
+ } else {
+ ret = -1;
+ }
+ } else if (strcmp(argv[1], "set") == 0) {
+ if (argc == 3) {
+ value = (unsigned int)simple_strtoul(argv[2], NULL, 16);
+ value &= 0xffff;
+ temp = value >> 8;
+ aml_lcd_driver_set_ss(2, (value & 0xff),
+ ((temp >> LCD_CLK_SS_BIT_FREQ) & 0xf),
+ ((temp >> LCD_CLK_SS_BIT_MODE) & 0xf));
+ } else {
+ ret = -1;
+ }
+ } else if (strcmp(argv[1], "get") == 0) {
+ aml_lcd_driver_get_ss(2);
+ } else {
+ ret = -1;
+ }
+ return ret;
+}
+
+static int do_lcd2_clk(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ aml_lcd_driver_clk_info(2);
+ return 0;
+}
+
+static int do_lcd2_info(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ aml_lcd_driver_info(2);
+ return 0;
+}
+
+static int do_lcd2_reg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ aml_lcd_driver_reg_info(2);
+ return 0;
+}
+
+static int do_lcd2_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int num;
+
+ if (argc == 1)
+ return -1;
+
+ num = (unsigned int)simple_strtoul(argv[1], NULL, 10);
+ aml_lcd_driver_test(2, num);
+ return 0;
+}
+
+static int do_lcd2_prbs(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int s, prbs_mode_flag;
+
+ if (argc == 1)
+ return -1;
+
+ if (strcmp(argv[1], "vx1") == 0) {
+ if (argc == 3)
+ prbs_mode_flag = LCD_PRBS_MODE_VX1;
+ else
+ return -1;
+ } else if (strcmp(argv[1], "lvds") == 0) {
+ if (argc == 3)
+ prbs_mode_flag = LCD_PRBS_MODE_LVDS;
+ else
+ return -1;
+ } else {
+ prbs_mode_flag = LCD_PRBS_MODE_LVDS | LCD_PRBS_MODE_VX1;
+ }
+
+ s = (unsigned int)simple_strtoul(argv[2], NULL, 10);
+ aml_lcd_driver_prbs(2, s, prbs_mode_flag);
+ return 0;
+}
+
+static int do_lcd2_key(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int tmp = 0;
+
+ if (argc == 1)
+ return -1;
+
+ if (strcmp(argv[1], "dump") == 0) {
+ if (argc == 3) {
+ if (strcmp(argv[2], "tcon") == 0)
+ tmp = (1 << 1);
+ else
+ tmp = (1 << 0);
+ } else {
+ tmp = (1 << 0);
+ }
+ aml_lcd_driver_unifykey_dump(2, tmp);
+ }
+ return 0;
+}
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static int do_lcd2_ext(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int temp;
+
+ if (argc == 1)
+ return -1;
+
+ if (strcmp(argv[1], "info") == 0) {
+ aml_lcd_driver_ext_info(2);
+ } else if (strcmp(argv[1], "power") == 0) {
+ if (argc < 3)
+ return -1;
+ temp = simple_strtoul(argv[2], NULL, 10);
+ if (temp)
+ aml_lcd_driver_ext_power_on(2);
+ else
+ aml_lcd_driver_ext_power_off(2);
+ }
+
+ return 0;
+}
+#endif
+
+static int do_lcd2_bl(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int level;
+ int ret = 0;
+
+ if (argc == 1)
+ return -1;
+
+ if (strcmp(argv[1], "on") == 0) {
+ aml_lcd_driver_bl_on(2);
+ } else if (strcmp(argv[1], "off") == 0) {
+ aml_lcd_driver_bl_off(2);
+ } else if (strcmp(argv[1], "set") == 0) {
+ if (argc == 3) {
+ level = (unsigned int)simple_strtoul(argv[2], NULL, 10);
+ aml_lcd_driver_set_bl_level(2, level);
+ } else {
+ ret = -1;
+ }
+ } else if (strcmp(argv[1], "get") == 0) {
+ level = aml_lcd_driver_get_bl_level(2);
+ printf("lcd2 get_bl_level: %d\n", level);
+ } else if (strcmp(argv[1], "info") == 0) {
+ aml_lcd_driver_bl_config_print(2);
+ } else {
+ ret = -1;
+ }
+ return ret;
+}
static cmd_tbl_t cmd_lcd_sub[] = {
U_BOOT_CMD_MKENT(probe, 2, 0, do_lcd_probe, "", ""),
U_BOOT_CMD_MKENT(enable, 2, 0, do_lcd_enable, "", ""),
U_BOOT_CMD_MKENT(disable, 2, 0, do_lcd_disable, "", ""),
U_BOOT_CMD_MKENT(ss, 4, 0, do_lcd_ss, "", ""),
- U_BOOT_CMD_MKENT(bl, 4, 0, do_lcd_bl, "", ""),
U_BOOT_CMD_MKENT(clk , 2, 0, do_lcd_clk, "", ""),
U_BOOT_CMD_MKENT(info, 2, 0, do_lcd_info, "", ""),
+#ifdef CONFIG_AML_LCD_TCON
U_BOOT_CMD_MKENT(tcon, 3, 0, do_lcd_tcon, "", ""),
+#endif
+ U_BOOT_CMD_MKENT(vbyone, 3, 0, do_lcd_vbyone, "", ""),
U_BOOT_CMD_MKENT(reg, 2, 0, do_lcd_reg, "", ""),
U_BOOT_CMD_MKENT(test, 3, 0, do_lcd_test, "", ""),
+ U_BOOT_CMD_MKENT(prbs, 2, 0, do_lcd_prbs, "", ""),
U_BOOT_CMD_MKENT(key, 4, 0, do_lcd_key, "", ""),
- U_BOOT_CMD_MKENT(ext, 2, 0, do_lcd_ext, "", ""),
+#ifdef CONFIG_AML_LCD_EXTERN
+ U_BOOT_CMD_MKENT(ext, 4, 0, do_lcd_ext, "", ""),
+#endif
+ U_BOOT_CMD_MKENT(bl, 4, 0, do_lcd_bl, "", ""),
+};
+
+static cmd_tbl_t cmd_lcd1_sub[] = {
+ U_BOOT_CMD_MKENT(probe, 2, 0, do_lcd1_probe, "", ""),
+ U_BOOT_CMD_MKENT(enable, 2, 0, do_lcd1_enable, "", ""),
+ U_BOOT_CMD_MKENT(disable, 2, 0, do_lcd1_disable, "", ""),
+ U_BOOT_CMD_MKENT(ss, 4, 0, do_lcd1_ss, "", ""),
+ U_BOOT_CMD_MKENT(clk , 2, 0, do_lcd1_clk, "", ""),
+ U_BOOT_CMD_MKENT(info, 2, 0, do_lcd1_info, "", ""),
+#ifdef CONFIG_AML_LCD_TCON
+ U_BOOT_CMD_MKENT(tcon, 3, 0, do_lcd1_tcon, "", ""),
+#endif
+ U_BOOT_CMD_MKENT(vbyone, 3, 0, do_lcd1_vbyone, "", ""),
+ U_BOOT_CMD_MKENT(reg, 2, 0, do_lcd1_reg, "", ""),
+ U_BOOT_CMD_MKENT(test, 3, 0, do_lcd1_test, "", ""),
+ U_BOOT_CMD_MKENT(prbs, 2, 0, do_lcd1_prbs, "", ""),
+ U_BOOT_CMD_MKENT(key, 4, 0, do_lcd1_key, "", ""),
+#ifdef CONFIG_AML_LCD_EXTERN
+ U_BOOT_CMD_MKENT(ext, 4, 0, do_lcd1_ext, "", ""),
+#endif
+ U_BOOT_CMD_MKENT(bl, 4, 0, do_lcd1_bl, "", ""),
+};
+
+static cmd_tbl_t cmd_lcd2_sub[] = {
+ U_BOOT_CMD_MKENT(probe, 2, 0, do_lcd2_probe, "", ""),
+ U_BOOT_CMD_MKENT(enable, 2, 0, do_lcd2_enable, "", ""),
+ U_BOOT_CMD_MKENT(disable, 2, 0, do_lcd2_disable, "", ""),
+ U_BOOT_CMD_MKENT(ss, 4, 0, do_lcd2_ss, "", ""),
+ U_BOOT_CMD_MKENT(clk , 2, 0, do_lcd2_clk, "", ""),
+ U_BOOT_CMD_MKENT(info, 2, 0, do_lcd2_info, "", ""),
+ U_BOOT_CMD_MKENT(reg, 2, 0, do_lcd2_reg, "", ""),
+ U_BOOT_CMD_MKENT(test, 3, 0, do_lcd2_test, "", ""),
+ U_BOOT_CMD_MKENT(prbs, 2, 0, do_lcd2_prbs, "", ""),
+ U_BOOT_CMD_MKENT(key, 4, 0, do_lcd2_key, "", ""),
+#ifdef CONFIG_AML_LCD_EXTERN
+ U_BOOT_CMD_MKENT(ext, 4, 0, do_lcd2_ext, "", ""),
+#endif
+ U_BOOT_CMD_MKENT(bl, 4, 0, do_lcd2_bl, "", ""),
};
static int do_lcd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -341,9 +1098,90 @@
"lcd bl - lcd backlight operation\n"
"lcd clk - show lcd pll & clk parameters\n"
"lcd info - show lcd parameters\n"
+#ifdef CONFIG_AML_LCD_TCON
"lcd tcon - show lcd tcon debug\n"
+#endif
+ "lcd vbyone - show lcd vbyone debug\n"
"lcd reg - dump lcd registers\n"
"lcd test - show lcd bist pattern\n"
"lcd key - show lcd unifykey test\n"
+#ifdef CONFIG_AML_LCD_EXTERN
"lcd ext - show lcd extern information\n"
+#endif
+);
+
+static int do_lcd1(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ cmd_tbl_t *c;
+
+ /* Strip off leading 'bmp' command argument */
+ argc--;
+ argv++;
+
+ c = find_cmd_tbl(argv[0], &cmd_lcd1_sub[0], ARRAY_SIZE(cmd_lcd1_sub));
+
+ if (c) {
+ return c->cmd(cmdtp, flag, argc, argv);
+ } else {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+}
+
+U_BOOT_CMD(
+ lcd1, 5, 0, do_lcd1,
+ "lcd1 sub-system",
+ "lcd1 probe - probe lcd parameters\n"
+ "lcd1 enable - enable lcd module\n"
+ "lcd1 disable - disable lcd module\n"
+ "lcd1 ss - lcd pll spread spectrum operation\n"
+ "lcd1 bl - lcd backlight operation\n"
+ "lcd1 clk - show lcd pll & clk parameters\n"
+ "lcd1 info - show lcd parameters\n"
+#ifdef CONFIG_AML_LCD_TCON
+ "lcd1 tcon - show lcd tcon debug\n"
+#endif
+ "lcd1 vbyone - show lcd vbyone debug\n"
+ "lcd1 reg - dump lcd registers\n"
+ "lcd1 test - show lcd bist pattern\n"
+ "lcd1 key - show lcd unifykey test\n"
+#ifdef CONFIG_AML_LCD_EXTERN
+ "lcd1 ext - show lcd extern information\n"
+#endif
+);
+
+static int do_lcd2(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ cmd_tbl_t *c;
+
+ /* Strip off leading 'bmp' command argument */
+ argc--;
+ argv++;
+
+ c = find_cmd_tbl(argv[0], &cmd_lcd2_sub[0], ARRAY_SIZE(cmd_lcd2_sub));
+
+ if (c) {
+ return c->cmd(cmdtp, flag, argc, argv);
+ } else {
+ cmd_usage(cmdtp);
+ return 1;
+ }
+}
+
+U_BOOT_CMD(
+ lcd2, 5, 0, do_lcd2,
+ "lcd2 sub-system",
+ "lcd2 probe - probe lcd parameters\n"
+ "lcd2 enable - enable lcd module\n"
+ "lcd2 disable - disable lcd module\n"
+ "lcd2 ss - lcd pll spread spectrum operation\n"
+ "lcd2 bl - lcd backlight operation\n"
+ "lcd2 clk - show lcd pll & clk parameters\n"
+ "lcd2 info - show lcd parameters\n"
+ "lcd2 reg - dump lcd registers\n"
+ "lcd2 test - show lcd bist pattern\n"
+ "lcd2 key - show lcd unifykey test\n"
+#ifdef CONFIG_AML_LCD_EXTERN
+ "lcd2 ext - show lcd extern information\n"
+#endif
);
diff --git a/cmd/amlogic/cmd_osd.c b/cmd/amlogic/cmd_osd.c
index bba6515..4001c74 100644
--- a/cmd/amlogic/cmd_osd.c
+++ b/cmd/amlogic/cmd_osd.c
@@ -1,3 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include <common.h>
#include <lcd.h>
#include <command.h>
@@ -6,6 +11,7 @@
#include <splash.h>
#include <video_fb.h>
#include <video.h>
+#include <amlogic/fb.h>
int osd_enabled = 0;
/* Graphic Device */
@@ -17,6 +23,7 @@
extern void osd_enable_hw(u32 index, u32 enable);
extern void osd_set_free_scale_enable_hw(u32 index, u32 enable);
extern int osd_rma_test(u32 osd_index);
+extern int get_osd_layer(void);
static int do_osd_open(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -32,10 +39,11 @@
static int do_osd_enable(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
- ulong index = 0;
+ int index = 0;
- index = simple_strtoul(env_get("display_layer"), NULL, 0);
- osd_enable_hw(index, 1);
+ index = get_osd_layer();
+ if (index >= 0)
+ osd_enable_hw(index, 1);
return 0;
}
@@ -43,38 +51,59 @@
static int do_osd_close(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
+
+ uint index = 0;
+
+ index = get_osd_layer();
+
if (gdev == NULL)
return 1;
gdev = NULL;
- osd_enable_hw(0, 0);
- osd_enable_hw(1, 0);
- osd_set_free_scale_enable_hw(0, 0);
- osd_set_free_scale_enable_hw(1, 0);
+ if (index >= VIU2_OSD1) {
+ osd_enable_hw(VIU2_OSD1, 0);
+ } else {
+ osd_enable_hw(OSD1, 0);
+ osd_enable_hw(OSD2, 0);
+ osd_set_free_scale_enable_hw(OSD1, 0);
+ osd_set_free_scale_enable_hw(OSD2, 0);
+ }
+
osd_enabled = 0;
+
return 0;
}
static int do_osd_clear(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
+#ifdef OSD_SCALE_ENABLE
+ uint index = 0;
+ ulong fb_addr;
+ ulong fb_len;
+#endif
if (gdev == NULL) {
printf("Please enable osd device first!\n");
return 1;
}
#ifdef OSD_SCALE_ENABLE
- memset((void *)(long long)(gdev->frameAdrs), 0,
- (gdev->fb_width * gdev->fb_height)*gdev->gdfBytesPP);
-
- flush_cache(gdev->frameAdrs,
- ((gdev->fb_width * gdev->fb_height)*gdev->gdfBytesPP));
+ index = get_osd_layer();
+ if (index < VIU2_OSD1) {
+ fb_addr = (ulong)gdev->frameAdrs;
+ fb_len = CANVAS_ALIGNED(gdev->fb_width * gdev->gdfBytesPP) * gdev->fb_height;
+ } else {
+ fb_addr = (ulong)(gdev->frameAdrs +
+ CANVAS_ALIGNED(gdev->fb_width * gdev->gdfBytesPP) * gdev->fb_height);
+ fb_len = CANVAS_ALIGNED(gdev->winSizeX * gdev->gdfBytesPP) * gdev->winSizeY;
+ }
+ memset((void *)fb_addr, 0, fb_len);
+ flush_cache(fb_addr, fb_len);
#else
- memset((void *)(long long)(gdev->frameAdrs), 0,
- (gdev->winSizeX * gdev->winSizeY)*gdev->gdfBytesPP);
+ fb_len = CANVAS_ALIGNED(gdev->winSizeX * gdev->gdfBytesPP) * gdev->winSizeY;
+ memset((void *)(long long)(gdev->frameAdrs), 0, fb_len);
- flush_cache(gdev->frameAdrs,
- ((gdev->winSizeX * gdev->winSizeY)*gdev->gdfBytesPP));
+ flush_cache(gdev->frameAdrs, fb_len);
#endif
return 0;
}
@@ -151,77 +180,6 @@
return ret;
}
-static int do_osd_setcolor(cmd_tbl_t *cmdtp, int flag, int argc,
- char *const argv[])
-{
- ulong addr = 0;
- int h = 0, w = 0;
- int size = 0;
- int i = 0, j = 0;
- int display_bpp_value = 16; //default 16bpp
- ulong val = 0;
- unsigned int *ptr = NULL;
- uchar *fb, low_value = 0, high_value = 0;
-
- char *str = env_get("fb_addr");
- if (str == NULL) {
- printf("failed to get fb_addr");
- return 1;
- } else {
- addr = simple_strtoul(str, NULL, 16);
- pr_info("osd fb addr: 0x%lx\n", addr);
- }
- fb = (uchar *)(addr);
- str = env_get("fb_height");
- if (str == NULL) {
- printf("failed to get fb_heigh");
- return 1;
- } else {
- h = simple_strtoul(str, NULL, 10);
- }
- pr_info("osd fb_height: %d\n", h);
-
- str = env_get("fb_width");
- if (str == NULL) {
- printf("failed to get fb_width");
- return 1;
- } else {
- w = simple_strtoul(str, NULL, 10);
- }
- pr_info("osd fb_width: %d\n", w);
-
- str = env_get("display_bpp");
- if (str == NULL) {
- printf("failed to get display_bpp");
- return 1;
- } else {
- display_bpp_value = simple_strtoul(str, NULL, 10);
- }
- pr_info("display_bpp_value: %d\n", display_bpp_value);
-
- if (gdev == NULL) {
- printf("do_osd_display, enable osd device first!\n");
- return 1;
- }
- size = ((w * h));
-
- val = simple_strtoul(argv[1], NULL, 16);
- if (display_bpp_value == 16)
- {
- low_value = (val & 0xff);
- high_value = ((val & 0xff00) >> 8);
-
- for (j = 0; j < h; j++) {
- for (i = 0; i < w; i++ ) {
- *(fb++) = low_value;
- *(fb++) = high_value;
- }
- }
- flush_cache((unsigned long)addr, w * h * 16);
- }
- return 0;
-}
-
static int do_osd_set(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
{
@@ -275,7 +233,6 @@
U_BOOT_CMD_MKENT(debug, 2, 0, do_osd_debug, "", ""),
U_BOOT_CMD_MKENT(test, 2, 0, do_osd_test, "", ""),
U_BOOT_CMD_MKENT(display, 5, 0, do_osd_display, "", ""),
- U_BOOT_CMD_MKENT(setcolor, 2, 0, do_osd_setcolor, "", ""),
U_BOOT_CMD_MKENT(set, 7, 0, do_osd_set, "", ""),
U_BOOT_CMD_MKENT(get, 2, 0, do_osd_get, "", ""),
};
@@ -297,7 +254,7 @@
}
U_BOOT_CMD(
- osd, 10, 1, do_osd,
+ osd, 7, 1, do_osd,
"osd sub-system",
"open - open osd device\n"
"osd enable - enable osd device\n"
@@ -306,7 +263,6 @@
"osd debug - debug osd device\n"
"osd test [osdID] - test osd device\n"
"osd display <imageAddr> [x y] - display image\n"
- "osd setcolor <color-rgb-value> - display color bg\n"
"osd set <osdID> <a> <b> <c> <d> - set Hist GoldenData in env\n"
" a for hist_max_min\n"
" b for hist_spl_val\n"
diff --git a/cmd/amlogic/cmd_plltest.c b/cmd/amlogic/cmd_plltest.c
new file mode 100644
index 0000000..f315a36
--- /dev/null
+++ b/cmd/amlogic/cmd_plltest.c
@@ -0,0 +1,447 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/* README */
+/*
+
+Part1: S905X usage
+
+1. sys pll
+
+ test pass print: sys pll test pass!
+ test fail print: sys pll test failed!
+
+ uboot command(select one as needed):
+ 960MHz: plltest sys 0x60000228 0xc4258100 0xb7400000 0x0a59a288 0x0040002d 0x7c700007
+ 1056MHz: plltest sys 0x6000022c 0xc4258100 0xb7400000 0x0a59a288 0x0040002d 0x7c700007
+ 1152MHz: plltest sys 0x60000230 0xc4258100 0xb7400000 0x0a59a288 0x0040002d 0x7c700007
+ 1248MHz: plltest sys 0x60000234 0xc4258100 0xb7400000 0x0a59a288 0x0040002d 0x7c700007
+ 1344MHz: plltest sys 0x60000238 0xc4258100 0xb7400000 0x0a59a288 0x0040002d 0x7c700007
+ 1440MHz: plltest sys 0x6000023c 0xc4258100 0xb7400000 0x0a59a288 0x0040002d 0x7c700007
+ 1536MHz: plltest sys 0x60000240 0xc4258100 0xb7400000 0x0a59a288 0x0040002d 0x7c700007
+ 1632MHz: plltest sys 0x60000244 0xc4258100 0xb7400000 0x0a59a288 0x0040002d 0x7c700007
+ all: plltest sys
+
+2. hdmi pll
+
+ test pass print: hdmi pll test pass!
+ test fail print: hdmi pll test failed!
+
+ uboot command:
+ 5940MHz: plltest hdmi 0x4000027b 0x800cb300 0xc65f30e0 0x0c8e0000 0x001fa729 0x01a31500
+ 5405MHz: plltest hdmi 0x400002e1 0x800cb0e6 0x865f30c4 0x0c8e0000 0x001fa729 0x01a31500
+ 4455MHz: plltest hdmi 0x400002b9 0x800cb280 0x865f30c4 0x0c8e0000 0x001fa729 0x01a31500
+ 4324MHz: plltest hdmi 0x400002b4 0x800cb0b8 0x865f30c4 0x0c8e0000 0x001fa729 0x01a31500
+ 3712MHz: plltest hdmi 0x4000029a 0x800cb2c0 0x865f30c4 0x0c8e0000 0x001fa729 0x01a31500
+ 3450MHz: plltest hdmi 0x4000028f 0x800cb300 0x865f30c4 0x0c8e0000 0x001fa729 0x01a31500
+ 3243MHz: plltest hdmi 0x40000287 0x800cb08a 0x865f30c4 0x0c8e0000 0x001fa729 0x01a31500
+ 2970MHz: plltest hdmi 0x4000027b 0x800cb300 0x865f30c4 0x0c8e0000 0x001fa729 0x01a31500
+ all: plltest hdmi
+
+3. gp0 pll
+
+ test pass print: gp0 pll test pass!
+ test fail print: gp0 pll test failed!
+
+ uboot command:
+ 504MHz: plltest gp0 0xc001022a 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 516MHz: plltest gp0 0xc001022b 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 528MHz: plltest gp0 0xc001022c 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 540MHz: plltest gp0 0xc001022d 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 552MHz: plltest gp0 0xc001022e 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 564MHz: plltest gp0 0xc001022f 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 576MHz: plltest gp0 0xc0010230 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 588MHz: plltest gp0 0xc0010231 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 600MHz: plltest gp0 0xc0010232 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 612MHz: plltest gp0 0xc0010233 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 624MHz: plltest gp0 0xc0010234 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 636MHz: plltest gp0 0xc0010235 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 648MHz: plltest gp0 0xc0010236 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 660MHz: plltest gp0 0xc0010237 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 672MHz: plltest gp0 0xc0010238 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 684MHz: plltest gp0 0xc0010239 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 696MHz: plltest gp0 0xc001023a 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 708MHz: plltest gp0 0xc001023b 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 720MHz: plltest gp0 0xc001023c 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 732MHz: plltest gp0 0xc001023d 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 744MHz: plltest gp0 0xc001023e 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 756MHz: plltest gp0 0xc001023f 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 768MHz: plltest gp0 0xc0010240 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 780MHz: plltest gp0 0xc0010241 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 792MHz: plltest gp0 0xc0010242 0xc084a000 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ all: plltest gp0
+
+
+
+Part2: T968 usage
+
+1. sys pll
+
+ test pass print: sys pll test pass!
+ test fail print: sys pll test failed!
+
+ uboot command:
+ 1152MHz: plltest sys 0x60000230 0x5ac80000 0x8e452015 0x0401d40c 0x00000870
+ 1248MHz: plltest sys 0x60000234 0x5ac80000 0x8e452015 0x0401d40c 0x00000870
+ 1344MHz: plltest sys 0x60000238 0x5ac80000 0x8e452015 0x0401d40c 0x00000870
+ 1440MHz: plltest sys 0x6000023c 0x5ac80000 0x8e452015 0x0401d40c 0x00000870
+ 1536MHz: plltest sys 0x60000240 0x5ac80000 0x8e452015 0x0401d40c 0x00000870
+ 1632MHz: plltest sys 0x60000244 0x5ac80000 0x8e452015 0x0401d40c 0x00000870
+ all: plltest sys
+
+2. hdmi pll
+
+ test pass print: hdmi pll test pass!
+ test fail print: hdmi pll test failed!
+
+ uboot command:
+ 5940MHz: plltest hdmi 0x5800027b 0x000E4300 0x12dc5081 0x801da72c 0x71486980 0x00002e55
+ 4320MHz: plltest hdmi 0x5800025a 0x000E0000 0x0d5c5091 0x801da72c 0x71486980 0x00002e55
+ 3712MHz: plltest hdmi 0x5800024d 0x000E4160 0x0d5c5091 0x801da72c 0x71486980 0x00002e55
+ all: plltest hdmi
+
+3. gp0 pll
+
+ test pass print: gp0 pll test pass!
+ test fail print: gp0 pll test failed!
+
+ uboot command:
+ 504MHz: plltest gp0 0xc001022a 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 516MHz: plltest gp0 0xc001022b 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 528MHz: plltest gp0 0xc001022c 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 540MHz: plltest gp0 0xc001022d 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 552MHz: plltest gp0 0xc001022e 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 564MHz: plltest gp0 0xc001022f 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 576MHz: plltest gp0 0xc0010230 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 588MHz: plltest gp0 0xc0010231 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 600MHz: plltest gp0 0xc0010232 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 612MHz: plltest gp0 0xc0010233 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 624MHz: plltest gp0 0xc0010234 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 636MHz: plltest gp0 0xc0010235 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 648MHz: plltest gp0 0xc0010236 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 660MHz: plltest gp0 0xc0010237 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 672MHz: plltest gp0 0xc0010238 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 684MHz: plltest gp0 0xc0010239 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 696MHz: plltest gp0 0xc001023a 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 708MHz: plltest gp0 0xc001023b 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 720MHz: plltest gp0 0xc001023c 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 732MHz: plltest gp0 0xc001023d 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ all: plltest gp0
+
+
+Part3: T962 usage
+
+1. sys pll
+
+ test pass print: sys pll test pass!
+ test fail print: sys pll test failed!
+
+ uboot command(select one as needed):
+ 960MHz: plltest sys 0x60000228 0xc4258100 0xb7400000 0x0a59a288 0x0040002d 0x7c700007
+ 1056MHz: plltest sys 0x6000022c 0xc4258100 0xb7400000 0x0a59a288 0x0040002d 0x7c700007
+ 1152MHz: plltest sys 0x60000230 0xc4258100 0xb7400000 0x0a59a288 0x0040002d 0x7c700007
+ 1248MHz: plltest sys 0x60000234 0xc4258100 0xb7400000 0x0a59a288 0x0040002d 0x7c700007
+ 1344MHz: plltest sys 0x60000238 0xc4258100 0xb7400000 0x0a59a288 0x0040002d 0x7c700007
+ 1440MHz: plltest sys 0x6000023c 0xc4258100 0xb7400000 0x0a59a288 0x0040002d 0x7c700007
+ 1536MHz: plltest sys 0x60000240 0xc4258100 0xb7400000 0x0a59a288 0x0040002d 0x7c700007
+ 1632MHz: plltest sys 0x60000244 0xc4258100 0xb7400000 0x0a59a288 0x0040002d 0x7c700007
+ all: plltest sys
+
+2. hdmi pll
+
+ test pass print: hdmi pll test pass!
+ test fail print: hdmi pll test failed!
+
+ uboot command:
+ 5940MHz: plltest hdmi 0x400002f7 0x800cb200 0x865f30c4 0x0c8e0000 0x001fa729 0x01a31500
+ 4320MHz: plltest hdmi 0x400002b4 0x800cb000 0x865f30c4 0x0c8e0000 0x001fa729 0x01a31500
+ 3712MHz: plltest hdmi 0x4000029a 0x800cb2c0 0x865f30c4 0x0c8e0000 0x001fa729 0x01a31500
+ 3712MHz: plltest hdmi 0x4000027b 0x800cb300 0x865f30c4 0x0c8e0000 0x001fa729 0x01a31500
+ all: plltest hdmi
+
+3. gp0 pll
+
+ test pass print: gp0 pll test pass!
+ test fail print: gp0 pll test failed!
+
+ uboot command:
+ 504MHz: plltest gp0 0xc001022a 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 516MHz: plltest gp0 0xc001022b 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 528MHz: plltest gp0 0xc001022c 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 540MHz: plltest gp0 0xc001022d 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 552MHz: plltest gp0 0xc001022e 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 564MHz: plltest gp0 0xc001022f 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 576MHz: plltest gp0 0xc0010230 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 588MHz: plltest gp0 0xc0010231 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 600MHz: plltest gp0 0xc0010232 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 612MHz: plltest gp0 0xc0010233 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 624MHz: plltest gp0 0xc0010234 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 636MHz: plltest gp0 0xc0010235 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 648MHz: plltest gp0 0xc0010236 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 660MHz: plltest gp0 0xc0010237 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 672MHz: plltest gp0 0xc0010238 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 684MHz: plltest gp0 0xc0010239 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 696MHz: plltest gp0 0xc001023a 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 708MHz: plltest gp0 0xc001023b 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 720MHz: plltest gp0 0xc001023c 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ 732MHz: plltest gp0 0xc001023d 0xb75020be 0x0a59a288 0xc000004d 0x00078000
+ all: plltest gp0
+
+
+T962: please check Part3
+
+Part4: G12A usage
+
+1. sys pll
+
+ test pass print: sys pll test pass!
+ test fail print: sys pll test failed!
+
+ uboot command(select one as needed):
+ 960MHz: plltest sys 0x380204a0 0x0 0x0 0x48681c00 0x88770290 0x39272000 0x56540000
+ 1056MHz: plltest sys 0x380204b0 0x0 0x0 0x48681c00 0x88770290 0x39272000 0x56540000
+ 1152MHz: plltest sys 0x380204c0 0x0 0x0 0x48681c00 0x88770290 0x39272000 0x56540000
+ 1248MHz: plltest sys 0x380204d0 0x0 0x0 0x48681c00 0x88770290 0x39272000 0x56540000
+ 1344MHz: plltest sys 0x380204e0 0x0 0x0 0x48681c00 0x88770290 0x39272000 0x56540000
+ 1440MHz: plltest sys 0x380204f0 0x0 0x0 0x48681c00 0x88770290 0x39272000 0x56540000
+ 1536MHz: plltest sys 0x38010480 0x0 0x0 0x48681c00 0x88770290 0x39272000 0x56540000
+ 1632MHz: plltest sys 0x38010488 0x0 0x0 0x48681c00 0x88770290 0x39272000 0x56540000
+ all: plltest sys
+
+2. hdmi pll
+
+ test pass print: hdmi pll test pass!
+ test fail print: hdmi pll test failed!
+
+ uboot command:
+ 5405MHz: plltest hdmi 0x3b0004e1 0x00007333 0x00000000 0x0a691c00 0x33771290 0x39270000 0x50540000
+ 4455MHz: plltest hdmi 0x3b0004b9 0x00014000 0x00000000 0x0a691c00 0x33771290 0x39270000 0x50540000
+ 3450MHz: plltest hdmi 0x3b00048f 0x00018000 0x00000000 0x0a691c00 0x33771290 0x39270000 0x50540000
+ 2970MHz: plltest hdmi 0x3b00047b 0x00018000 0x00000000 0x0a691c00 0x33771290 0x39270000 0x50540000
+ all: plltest hdmi
+
+3. gp0 pll
+
+ test pass print: gp0 pll test pass!
+ test fail print: gp0 pll test failed!
+
+ uboot command:
+ 408MHz: plltest gp0 0x38070488 0 0 0x48681c00 0x33771290 0x39272000 0x56540000
+ 600MHz: plltest gp0 0x380704c8 0 0 0x48681c00 0x33771290 0x39272000 0x56540000
+ 696MHz: plltest gp0 0x380704e8 0 0 0x48681c00 0x33771290 0x39272000 0x56540000
+ 792MHz: plltest gp0 0x38060484 0 0 0x48681c00 0x33771290 0x39272000 0x56540000
+ 846MHz: plltest gp0 0x3806048d 0 0 0x48681c00 0x33771290 0x39272000 0x56540000
+ 912MHz: plltest gp0 0x38060498 0 0 0x48681c00 0x33771290 0x39272000 0x56540000
+ all: plltest gp0
+
+4. hifi pll
+
+ test pass print: hifi pll test pass!
+ test fail print: hifi pll test failed!
+
+ uboot command:
+ 1008MHz: plltest hifi 0x380604A8 0 0 0x48681c00 0x33771290 0x39272000 0x56540000
+ 1104MHz: plltest hifi 0x380604B8 0 0 0x48681c00 0x33771290 0x39272000 0x56540000
+ 1200MHz: plltest hifi 0x380604C8 0 0 0x48681c00 0x33771290 0x39272000 0x56540000
+ 1296MHz: plltest hifi 0x380604D8 0 0 0x48681c00 0x33771290 0x39272000 0x56540000
+ 1398MHz: plltest hifi 0x380604E9 0 0 0x48681c00 0x33771290 0x39272000 0x56540000
+ 1494MHz: plltest hifi 0x380604F9 0 0 0x48681c00 0x33771290 0x39272000 0x56540000
+ all: plltest hifi
+
+5. pcie pll
+
+ test pass print: pcie pll test pass!
+ test fail print: pcie pll test failed!
+
+ uboot command:
+ 100MHz: plltest pcie 0x200c04c8 0 0x00001100 0x10058e00 0x000100c0 0x68000048
+ all: plltest pcie
+
+6. ethphy pll
+
+ test pass print: ethphy pll test pass!
+ test fail print: ethphy pll test failed!
+
+ uboot command:
+ 500MHz: plltest ethphy 0x9c0040a 0x927e0000 0xac5f49e5 0x00000000
+ all: plltest ethphy
+
+7. usbphy pll
+
+ test pass print: usbphy pll test pass!
+ test fail print: usbphy pll test failed!
+
+ uboot command:
+ 480MHz: plltest usbphy 0x8000fff 0x34 0x78000 0 0x09400414 0x927E0000 0xac5f69e5 0xfe18
+ all: plltest usbphy
+
+ NOTICE:usbphy pll does not connect clk_msr£¬so here only judge whether is locked
+
+
+
+Part5: A1 usage
+
+1. sys pll
+
+ test pass print: sys pll test pass!
+ test fail print: sys pll test failed!
+
+ uboot command(select one as needed):
+ 768MHz: plltest sys 0x01f18420 0x01800000 0x00001100 0x10022300 0x00300000
+ 888MHz: plltest sys 0x01f18425 0x01800000 0x00001100 0x10022300 0x00300000
+ 960MHz: plltest sys 0x01f18428 0x01800000 0x00001100 0x10022300 0x00300000
+ 1008MHz: plltest sys 0x01f1842A 0x01800000 0x00001100 0x10022300 0x00300000
+ 1152MHz: plltest sys 0x01f18430 0x01800000 0x00001100 0x10022300 0x00300000
+ 1248MHz: plltest sys 0x01f18434 0x01800000 0x00001100 0x10022300 0x00300000
+ 1392MHz: plltest sys 0x01f1843A 0x01800000 0x00001100 0x10022300 0x00300000
+ 1536MHz: plltest sys 0x01f18440 0x01800000 0x00001100 0x10022300 0x00300000
+ all: plltest sys
+
+2. hifi pll
+
+ test pass print: hifi pll test pass!
+ test fail print: hifi pll test failed!
+
+ uboot command:
+ 864MHz: plltest hifi 0x01f18424 0x01800000 0x00001100 0x10022300 0x00300000
+ 960MHz: plltest hifi 0x01f18428 0x01800000 0x00001100 0x10022300 0x00300000
+ 1056MHz: plltest hifi 0x01f1842C 0x01800000 0x00001100 0x10022300 0x00300000
+ 1200MHz: plltest hifi 0x01f18432 0x01800000 0x00001100 0x10022300 0x00300000
+ 1320MHz: plltest hifi 0x01f18437 0x01800000 0x00001100 0x10022300 0x00300000
+ 1536MHz: plltest hifi 0x01f18440 0x01800000 0x00001100 0x10022300 0x00300000
+ all: plltest hifi
+
+3. usbphy pll
+
+ test pass print: usbphy pll test pass!
+ test fail print: usbphy pll test failed!
+
+ uboot command:
+ 480MHz: plltest usbphy 0x09400414 0x927e0000 0xac5f69e5
+ all: plltest usbphy
+
+ NOTICE:usbphy pll does not connect clk_msr£¬so here only judge whether is locked
+
+Part6: C1 usage
+
+1. sys pll
+
+ test pass print: sys pll test pass!
+ test fail print: sys pll test failed!
+
+ uboot command(select one as needed):
+ 768MHz: plltest sys 0x01f18420 0x01800000 0x00001100 0x10022300 0x00300000
+ 888MHz: plltest sys 0x01f18425 0x01800000 0x00001100 0x10022300 0x00300000
+ 960MHz: plltest sys 0x01f18428 0x01800000 0x00001100 0x10022300 0x00300000
+ 1008MHz: plltest sys 0x01f1842A 0x01800000 0x00001100 0x10022300 0x00300000
+ 1152MHz: plltest sys 0x01f18430 0x01800000 0x00001100 0x10022300 0x00300000
+ 1248MHz: plltest sys 0x01f18434 0x01800000 0x00001100 0x10022300 0x00300000
+ 1392MHz: plltest sys 0x01f1843A 0x01800000 0x00001100 0x10022300 0x00300000
+ 1536MHz: plltest sys 0x01f18440 0x01800000 0x00001100 0x10022300 0x00300000
+ all: plltest sys
+
+2. hifi pll
+
+ test pass print: hifi pll test pass!
+ test fail print: hifi pll test failed!
+
+ uboot command:
+ 864MHz: plltest hifi 0x01f18424 0x01800000 0x00001100 0x10022300 0x00300000
+ 960MHz: plltest hifi 0x01f18428 0x01800000 0x00001100 0x10022300 0x00300000
+ 1056MHz: plltest hifi 0x01f1842C 0x01800000 0x00001100 0x10022300 0x00300000
+ 1200MHz: plltest hifi 0x01f18432 0x01800000 0x00001100 0x10022300 0x00300000
+ 1320MHz: plltest hifi 0x01f18437 0x01800000 0x00001100 0x10022300 0x00300000
+ 1536MHz: plltest hifi 0x01f18440 0x01800000 0x00001100 0x10022300 0x00300000
+ all: plltest hifi
+
+3. gp pll
+
+ test pass print: gp pll test pass!
+ test fail print: gp pll test failed!
+
+ uboot command:
+ 864MHz: plltest gp 0x01f18424 0x01800000 0x00001100 0x10022300 0x00300000 0x00088888
+ 960MHz: plltest gp 0x01f18428 0x01800000 0x00001100 0x10022300 0x00300000 0x00088888
+ 1056MHz: plltest gp 0x01f1842C 0x01800000 0x00001100 0x10022300 0x00300000 0x00088888
+ 1200MHz: plltest gp 0x01f18432 0x01800000 0x00001100 0x10022300 0x00300000 0x00088888
+ 1320MHz: plltest gp 0x01f18437 0x01800000 0x00001100 0x10022300 0x00300000 0x00088888
+ 1536MHz: plltest gp 0x01f18440 0x01800000 0x00001100 0x10022300 0x00300000 0x00088888
+ all: plltest gp
+
+4. dds pll
+
+ test pass print: dds pll test pass!
+ test fail print: dds pll test failed!
+
+ uboot command:
+ 32MHz: plltest dds 0x4 0x50041340 0x0 0x0 0x000003e8 0x00000040
+ 50MHz: plltest dds 0x4 0x50041340 0x0 0x0 0x000003e8 0x00000064
+ 60MHz: plltest dds 0x4 0x50041340 0x0 0x0 0x0000052 0x000000A
+ 80MHz: plltest dds 0x4 0x50041340 0x0 0x0 0x00000271 0x00000064
+ 100MHz: plltest dds 0x4 0x50041340 0x0 0x0 0x000005 0x0000001
+ all: plltest dds
+
+5. usbphy pll
+
+ test pass print: usbphy pll test pass!
+ test fail print: usbphy pll test failed!
+
+ uboot command:
+ 480MHz: plltest usbphy 0x09400414 0x927e0000 0xac5f69e5
+ all: plltest usbphy
+
+ NOTICE:usbphy pll does not connect clk_msr£¬so here only judge whether is locked
+
+6. ethphy pll
+
+ test pass print: ethphy pll test pass!
+ test fail print: ethphy pll test failed!
+
+ uboot command:
+ 500MHz: plltest ethphy 0x9c0040a 0x927e0000 0xac5f49e5
+ all: plltest ethphy
+
+
+*/
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/pll.h>
+
+static int do_plltest(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) {
+ if (argc < 2) {
+ return -1;
+ }
+
+ pll_test(argc, argv);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ plltest, CONFIG_SYS_MAXARGS, 1, do_plltest,
+ "test pll",
+ "\n"
+ " - test pll and report result\n\n"
+ "plltest [all/sys/hdmi/gp0/hifi/pcie/ethphy/usbphy] [pll_cntl pll_cntl2 ...]\n\n"
+ "examples:\n"
+ "plltest all - test all plls\n"
+ "plltest sys - test sys pll with all preset freq\n"
+ "plltest sys cntl cntl1 cntl2 ... - test sys pll with params\n"
+ "plltest hdmi - test hdmi pll with all preset freq\n"
+ "plltest hdmi cntl cntl1 cntl2 ... - test hdmi pll with params\n"
+ "plltest gp0 - test gp0 pll with all preset freq\n"
+ "plltest gp0 cntl cntl1 cntl2 ... - test gp0 pll with params\n"
+ "plltest hifi - test hifi pll with all preset freq\n"
+ "plltest hifi cntl cntl1 cntl2 ... - test hifi pll with params\n"
+ "plltest pcie - test pcie pll with all preset freq\n"
+ "plltest pcie cntl cntl1 cntl2 ... - test pcie pll with params\n"
+ "plltest ethphy - test ethphy pll with all preset freq\n"
+ "plltest ethphy cntl cntl1 cntl2 ... - test ethphy pll with params\n"
+ "plltest usbphy - test usbphy pll with all preset freq\n"
+ "plltest usbphy cntl cntl1 cntl2 ... - test usbphy pll with params\n"
+ "plltest dds - test dds pll with all preset freq\n"
+ "plltest dds cntl cntl1 cntl2 ... - test dds pll with params\n"
+);
diff --git a/cmd/amlogic/cmd_power.c b/cmd/amlogic/cmd_power.c
new file mode 100644
index 0000000..c5ad242
--- /dev/null
+++ b/cmd/amlogic/cmd_power.c
@@ -0,0 +1,71 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/pwr_ctrl.h>
+#include <command.h>
+
+#ifndef PM_MAX
+#define PM_MAX 0
+static char* domain_name[];
+#else
+extern char* domain_name[];
+#endif
+extern unsigned long pwr_ctrl_status_psci_smc(unsigned int power_domain);
+
+static int do_powershow(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int i;
+ int ret=0;
+
+ if (argc > 1) {
+ return CMD_RET_USAGE;
+ }
+
+ if (PM_MAX == 0) {
+ printf("Don't support this feature now!\n");
+ return ret;
+ }
+
+ for (i = 0; i < PM_MAX; i++)
+ printf("%s[%d]: %lx\n", domain_name[i],i, pwr_ctrl_status_psci_smc(i));
+
+ return ret;
+}
+
+U_BOOT_CMD(
+ powershow, 1, 1, do_powershow,
+ "show the power domain status , 0: on; 1: off",
+ "\n arg[0]: cmd\n"
+);
+
+static int do_powerset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int domain_id;
+ bool domain_status;
+ int ret=0;
+
+ if (argc <= 1) {
+ printf("plese input power set args: domain ID, domain status!\n");
+ return CMD_RET_USAGE;
+ }
+
+ domain_id = simple_strtoul(argv[1], NULL, 10);
+ domain_status = simple_strtoul(argv[2], NULL, 10);
+ printf("domain_id: %d \n",domain_id);
+ printf("domain_status: %d\n",domain_status);
+
+ pwr_ctrl_psci_smc(domain_id, !domain_status);
+
+ return ret;
+}
+
+U_BOOT_CMD(
+ powerset, 3, 1, do_powerset,
+ "power on/off a certain power domain",
+ "\n arg[0]: cmd\n"
+ "arg[1]: power domain ID \n"
+ "arg[2]: power status to set, 0: on, 1: off\n"
+);
diff --git a/cmd/amlogic/cmd_reboot.c b/cmd/amlogic/cmd_reboot.c
index ef0aa86..eebd76f 100644
--- a/cmd/amlogic/cmd_reboot.c
+++ b/cmd/amlogic/cmd_reboot.c
@@ -1,33 +1,16 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * common/cmd_reboot.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <common.h>
#include <command.h>
-#include <amlogic/flash_ts.h>
#include <asm/arch/reboot.h>
#include <asm/arch/secure_apb.h>
#include <asm/io.h>
#include <asm/arch/bl31_apis.h>
-#include <asm/arch/watchdog.h>
-
+#include <partition_table.h>
+#include <amlogic/storage.h>
/*
run get_rebootmode //set reboot_mode env with current mode
*/
@@ -39,26 +22,6 @@
debug("reboot_mode(0x%x)=0x%x\n", AO_SEC_SD_CFG15, reboot_mode_val);
- if(is_flash_inited()) {
- flash_ts_init();
-
- const char *fts_key = "bootloader.command";
- char fts_value[256] = { 0 };
-
- flash_ts_get(fts_key, fts_value, sizeof(fts_value));
- pr_info("FTS read: bootloader.command -> %s\n", fts_value);
- if (strncmp(fts_value, "boot-recovery", sizeof(fts_value)) == 0) {
-#ifndef CONFIG_G_AB_SYSTEM
- /* Recovery mode support only for non-A/B systems */
- reboot_mode_val = AMLOGIC_FACTORY_RESET_REBOOT;
- printf("overwriting reboot_mode_val to: %d\n", reboot_mode_val);
-#endif
- } else if (strncmp(fts_value, "boot-factory", sizeof(fts_value)) == 0) {
- reboot_mode_val = AMLOGIC_QUIESCENT_REBOOT;
- printf("overwriting reboot_mode_val to: %d\n", reboot_mode_val);
- }
- }
-
switch (reboot_mode_val)
{
case AMLOGIC_COLD_BOOT:
@@ -71,11 +34,6 @@
env_set("reboot_mode","normal");
break;
}
- case AMLOGIC_QUIESCENT_REBOOT:
- {
- env_set("reboot_mode","factory_boot");
- break;
- }
case AMLOGIC_FACTORY_RESET_REBOOT:
{
env_set("reboot_mode","factory_reset");
@@ -111,9 +69,9 @@
env_set("reboot_mode","shutdown_reboot");
break;
}
- case AMLOGIC_CRASH_REBOOT:
+ case AMLOGIC_RESCUEPARTY_REBOOT:
{
- env_set("reboot_mode","crash_dump");
+ env_set("reboot_mode", "rescueparty");
break;
}
case AMLOGIC_KERNEL_PANIC:
@@ -131,6 +89,16 @@
env_set("reboot_mode","rpmbp");
break;
}
+ case AMLOGIC_QUIESCENT_REBOOT:
+ {
+ env_set("reboot_mode","quiescent");
+ break;
+ }
+ case AMLOGIC_RECOVERY_QUIESCENT_REBOOT:
+ {
+ env_set("reboot_mode","recovery_quiescent");
+ break;
+ }
default:
{
env_set("reboot_mode","charging");
@@ -145,13 +113,14 @@
break;
}
case AMLOGIC_BOOTLOADER_REBOOT: {
- env_set("bootdelay","-1");
+ if (dynamic_partition)
+ env_set("reboot_mode","fastboot");
break;
}
}
#endif
-#if !defined(CONFIG_AML_RPMB_DISABLE)
+#if defined(CONFIG_AML_RPMB)
run_command("rpmb_state",0);
#endif
@@ -161,32 +130,39 @@
int do_reboot (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
uint32_t reboot_mode_val = AMLOGIC_NORMAL_BOOT;
- if (argc <= 1)
+ if (argc <= 1) {
printf("reboot use default mode: normal\n");
+ }
else {
printf("reboot mode: %s\n", argv[1]);
char * mode = argv[1];
- if (strcmp(mode, "cold_boot") == 0)
+ if (strcmp(mode, "next") == 0) {
+ store_restore_bootidx();
+ reboot_mode_val = AMLOGIC_COLD_BOOT;
+ } else if (strcmp(mode, "cold_boot") == 0)
reboot_mode_val = AMLOGIC_COLD_BOOT;
else if (strcmp(mode, "normal") == 0)
reboot_mode_val = AMLOGIC_NORMAL_BOOT;
else if (strcmp(mode, "recovery") == 0 || strcmp(mode, "factory_reset") == 0)
reboot_mode_val = AMLOGIC_FACTORY_RESET_REBOOT;
- else if (strcmp(mode, "factory_boot") == 0)
- reboot_mode_val = AMLOGIC_QUIESCENT_REBOOT;
else if (strcmp(mode, "update") == 0)
reboot_mode_val = AMLOGIC_UPDATE_REBOOT;
- else if (strcmp(mode, "fastboot") == 0)
- reboot_mode_val = AMLOGIC_FASTBOOT_REBOOT;
- else if (strcmp(mode, "bootloader") == 0)
+ else if (strcmp(mode, "fastboot") == 0) {
+ if (dynamic_partition) {
+ printf("dynamic partition, enter fastbootd");
+ reboot_mode_val = AMLOGIC_FACTORY_RESET_REBOOT;
+ run_command("bcb fastbootd",0);
+ } else
+ reboot_mode_val = AMLOGIC_FASTBOOT_REBOOT;
+ } else if (strcmp(mode, "bootloader") == 0)
reboot_mode_val = AMLOGIC_BOOTLOADER_REBOOT;
else if (strcmp(mode, "suspend_off") == 0)
reboot_mode_val = AMLOGIC_SUSPEND_REBOOT;
else if (strcmp(mode, "hibernate") == 0)
reboot_mode_val = AMLOGIC_HIBERNATE_REBOOT;
- else if (strcmp(mode, "crash_dump") == 0)
- reboot_mode_val = AMLOGIC_CRASH_REBOOT;
+ else if (strcmp(mode, "rescueparty") == 0)
+ reboot_mode_val = AMLOGIC_RESCUEPARTY_REBOOT;
else if (strcmp(mode, "kernel_panic") == 0)
reboot_mode_val = AMLOGIC_KERNEL_PANIC;
else if (strcmp(mode, "rpmbp") == 0)
@@ -197,9 +173,12 @@
}
}
#ifdef CONFIG_USB_DEVICE_V2
+#if !(defined AML_USB_V2)
*P_RESET1_REGISTER |= (1<<17);
mdelay(200);
#endif
+#endif
+ dcache_disable();
aml_reboot (PSCI_SYS_REBOOT, reboot_mode_val, 0, 0);
return 0;
@@ -244,12 +223,12 @@
" cold_boot\n"
" normal[default]\n"
" factory_reset/recovery\n"
- " factory_boot\n"
" update\n"
" fastboot\n"
" bootloader\n"
" suspend_off\n"
" hibernate\n"
+ " next <ONLY work for SC2>\n"
" crash_dump\n"
);
@@ -270,6 +249,7 @@
return 0;
}
+
U_BOOT_CMD(
systemoff, 2, 1, do_systemoff,
"system off ",
diff --git a/cmd/amlogic/cmd_ringmsr.c b/cmd/amlogic/cmd_ringmsr.c
index 7b41223..c353557 100644
--- a/cmd/amlogic/cmd_ringmsr.c
+++ b/cmd/amlogic/cmd_ringmsr.c
@@ -1,6 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Amlogic clkmsr command
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include <common.h>
#include <command.h>
#include <asm/arch/oscring.h>
diff --git a/cmd/amlogic/cmd_rpmb.c b/cmd/amlogic/cmd_rpmb.c
index 43bacfa..1148085 100644
--- a/cmd/amlogic/cmd_rpmb.c
+++ b/cmd/amlogic/cmd_rpmb.c
@@ -1,71 +1,153 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * common/cmd_rpmb.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <config.h>
#include <common.h>
#include <asm/arch/io.h>
#include <command.h>
#include <malloc.h>
-#include <asm/arch/secure_apb.h>
+#include <tee.h>
+
+#define TEE_ERROR_RPMB_AUTH_KEY_PROGRAMMED 0x7FFFFFFD
+
+#define CMD_RPMB_AUTH_KEY_INIT 0
+#define CMD_RPMB_AUTH_KEY_STATE 1
+
+#define TA_RPMB_UUID { 0x0ab5a718, 0xee63, 0x4115, \
+ { 0xa0, 0xad, 0xef, 0x6e, 0xe9, 0x8f, 0xcb, 0xc7 } }
+
+static int do_rpmb_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int ret = 0;
+ struct udevice *dev;
+ struct tee_open_session_arg open_arg;
+ struct tee_invoke_arg invoke_arg;
+ const struct tee_optee_ta_uuid uuid = TA_RPMB_UUID;
+
+ dev = tee_find_device(NULL, NULL, NULL, NULL);
+ if (!dev) {
+ printf("tee_find_device() failed");
+ return -ENODEV;
+ }
+
+ memset(&open_arg, 0, sizeof(open_arg));
+ tee_optee_ta_uuid_to_octets(open_arg.uuid, &uuid);
+ ret = tee_open_session(dev, &open_arg, 0, NULL);
+ if (ret) {
+ printf("tee_open_session() failed, ret = 0x%x\n", ret);
+ return ret;
+ }
+ if (open_arg.ret) {
+ printf("tee_open_session() failed, ret = 0x%x, ret_origin=0x%x \n",
+ open_arg.ret, open_arg.ret_origin);
+ return open_arg.ret;
+ }
+
+ memset(&invoke_arg, 0, sizeof(invoke_arg));
+ invoke_arg.session = open_arg.session;
+ invoke_arg.func = CMD_RPMB_AUTH_KEY_INIT;
+
+ ret = tee_invoke_func(dev, &invoke_arg, 0, NULL);
+ if (ret) {
+ printf("tee_invoke_func() failed, ret = 0x%x\n", ret);
+ goto exit;
+ }
+ if (invoke_arg.ret == TEE_SUCCESS) {
+ printf("program RPMB auth key success\n");
+ } else if (invoke_arg.ret == TEE_ERROR_RPMB_AUTH_KEY_PROGRAMMED) {
+ printf("RPMB auth key is programmed already\n");
+ } else {
+ printf("tee_invoke_func() failed, ret = 0x%x, origin = %d\n",
+ invoke_arg.ret, invoke_arg.ret_origin);
+ ret = invoke_arg.ret;
+ goto exit;
+ }
+
+exit:
+ tee_close_session(dev, open_arg.session);
+
+ return ret;
+}
+
+U_BOOT_CMD(rpmb_init, CONFIG_SYS_MAXARGS, 0, do_rpmb_init,
+ "RPMB sub-system",
+ "RPMB auth key init\n");
static int do_rpmb_state(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
- int nReturn = __LINE__;
+ int ret = 0;
+ struct udevice *dev;
+ struct tee_open_session_arg open_arg;
+ struct tee_invoke_arg invoke_arg;
+ const struct tee_optee_ta_uuid uuid = TA_RPMB_UUID;
+ struct tee_param param = { .attr = TEE_PARAM_ATTR_TYPE_VALUE_OUTPUT };
-#define AML_RPMB_STATE (((readl(AO_SEC_GP_CFG7))>>22) & 0x01)
-
- char *pARG = env_get("bootargs");
-
- if (pARG)
- {
- //printf("1 bootargs=%s\n",pARG);
-
- char *szBuffer=malloc(strlen(pARG)+64);
- nReturn = __LINE__;
-
- if (szBuffer)
- {
- memset(szBuffer+strlen(pARG),0,64);
- strcpy(szBuffer,pARG);
- char *pFind = strstr(szBuffer,"androidboot.rpmb_state");
- if (!pFind)
- sprintf(szBuffer,"%s androidboot.rpmb_state=%d",pARG,AML_RPMB_STATE);
- else
- pFind[23] = AML_RPMB_STATE ? '1':'0';
-
- //printf("2 bootargs=%s\n",szBuffer);
-
- env_set("rpmb_state",AML_RPMB_STATE?"1":"0"); //need this?
- env_set("bootargs",szBuffer);
- free(szBuffer);
- szBuffer = 0;
-
- nReturn = 0;
- }
- else
- printf("aml log : internal sys error!\n");
-
+ dev = tee_find_device(NULL, NULL, NULL, NULL);
+ if (!dev) {
+ printf("tee_find_device() failed");
+ return -ENODEV;
}
- return nReturn;
+ memset(&open_arg, 0, sizeof(open_arg));
+ tee_optee_ta_uuid_to_octets(open_arg.uuid, &uuid);
+ ret = tee_open_session(dev, &open_arg, 0, NULL);
+ if (ret) {
+ printf("tee_open_session() failed, ret = 0x%x\n", ret);
+ return ret;
+ }
+ if (open_arg.ret) {
+ printf("tee_open_session() failed, ret = 0x%x, ret_origin=0x%x\n",
+ open_arg.ret, open_arg.ret_origin);
+ return open_arg.ret;
+ }
+
+ memset(&invoke_arg, 0, sizeof(invoke_arg));
+ invoke_arg.session = open_arg.session;
+ invoke_arg.func = CMD_RPMB_AUTH_KEY_STATE;
+
+ ret = tee_invoke_func(dev, &invoke_arg, 1, ¶m);
+ if (ret) {
+ printf("tee_invoke_func() failed, ret = 0x%x\n", ret);
+ goto exit;
+ }
+ if (invoke_arg.ret) {
+ printf("tee_invoke_func() failed, ret = 0x%x, origin = %d\n",
+ invoke_arg.ret, invoke_arg.ret_origin);
+ ret = invoke_arg.ret;
+ goto exit;
+ }
+
+ char *parg = env_get("bootargs");
+ if (parg)
+ {
+ char *buff =malloc(strlen(parg) + 64);
+ if (!buff) {
+ ret = -ENOMEM;
+ goto exit;
+ }
+
+ memset(buff + strlen(parg), 0, 64);
+ strcpy(buff, parg);
+ char *find = strstr(buff, "androidboot.rpmb_state");
+ if (!find)
+ sprintf(buff,"%s androidboot.rpmb_state=0x%llx", parg, param.u.value.a);
+ else
+ find[23] = param.u.value.a ? '1':'0';
+
+ //printf("2 bootargs=%s\n",buff);
+
+ env_set("rpmb_state", param.u.value.a?"1":"0"); //need this?
+ env_set("bootargs", buff);
+ free(buff);
+ buff = NULL;
+ }
+
+exit:
+ tee_close_session(dev, open_arg.session);
+
+ return ret;
}
U_BOOT_CMD(rpmb_state, CONFIG_SYS_MAXARGS, 0, do_rpmb_state,
diff --git a/cmd/amlogic/cmd_rsvmem.c b/cmd/amlogic/cmd_rsvmem.c
index 7f3b1e8..db76c28 100644
--- a/cmd/amlogic/cmd_rsvmem.c
+++ b/cmd/amlogic/cmd_rsvmem.c
@@ -1,19 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * common/cmd_rsvmem.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <common.h>
#include <command.h>
@@ -22,6 +10,16 @@
#ifdef CONFIG_CMD_RSVMEM
+#if defined(P_AO_SEC_GP_CFG3)
+#define REG_RSVMEM_SIZE P_AO_SEC_GP_CFG3
+#define REG_RSVMEM_BL32_START P_AO_SEC_GP_CFG4
+#define REG_RSVMEM_BL31_START P_AO_SEC_GP_CFG5
+#elif defined(SYSCTRL_SEC_STATUS_REG15)
+#define REG_RSVMEM_SIZE SYSCTRL_SEC_STATUS_REG15
+#define REG_RSVMEM_BL32_START SYSCTRL_SEC_STATUS_REG16
+#define REG_RSVMEM_BL31_START SYSCTRL_SEC_STATUS_REG17
+#endif
+
//#define RSVMEM_DEBUG_ENABLE
#ifdef RSVMEM_DEBUG_ENABLE
#define rsvmem_dbg(fmt...) printf("[rsvmem] "fmt)
@@ -36,7 +34,9 @@
#define RSVMEM_RESERVED 0
#define RSVMEM_CMA 1
#define BL31_SHARE_MEM_SIZE 0x100000
+#ifndef BL32_SHARE_MEM_SIZE
#define BL32_SHARE_MEM_SIZE 0x400000
+#endif
static int do_rsvmem_check(cmd_tbl_t *cmdtp, int flag, int argc,
char *const argv[])
@@ -54,11 +54,17 @@
unsigned int aarch32 = 0;
rsvmem_dbg("reserved memory check!\n");
- data = readl(P_AO_SEC_GP_CFG3);
- bl31_rsvmem_size = ((data & 0xffff0000) >> 16) << 10;
- bl32_rsvmem_size = (data & 0x0000ffff) << 10;
- bl31_rsvmem_start = readl(P_AO_SEC_GP_CFG5);
- bl32_rsvmem_start = readl(P_AO_SEC_GP_CFG4);
+ data = readl(REG_RSVMEM_SIZE);
+ /* workaround for bl3x size */
+ if ((data >> 16) & 0xf0) {
+ bl31_rsvmem_size = ((data & 0xffff0000) >> 16) << 16;
+ bl32_rsvmem_size = (data & 0x0000ffff) << 16;
+ } else {
+ bl31_rsvmem_size = ((data & 0xffff0000) >> 16) << 10;
+ bl32_rsvmem_size = (data & 0x0000ffff) << 10;
+ }
+ bl31_rsvmem_start = readl(REG_RSVMEM_BL31_START);
+ bl32_rsvmem_start = readl(REG_RSVMEM_BL32_START);
fdtaddr = env_get("fdtaddr");
if (fdtaddr == NULL) {
@@ -231,6 +237,27 @@
}
memset(cmdbuf, 0, sizeof(cmdbuf));
+ sprintf(cmdbuf, "fdt get value ramoops_reg /reserved-memory/ramoops reg;");
+ if (run_command(cmdbuf, 0) == 0) {
+ memset(cmdbuf, 0, sizeof(cmdbuf));
+ if (aarch32)
+ sprintf(cmdbuf, "fdt set /reserved-memory/ramoops reg <0x%x 0x%x>;",
+ ((bl31_rsvmem_start + bl31_rsvmem_size + bl32_rsvmem_size + 0x400000 - 1) / 0x400000)*0x400000,
+ 0x100000);
+ else
+ sprintf(cmdbuf, "fdt set /reserved-memory/ramoops reg <0x0 0x%x 0x0 0x%x>;",
+ ((bl31_rsvmem_start + bl31_rsvmem_size + bl32_rsvmem_size + 0x400000 - 1) / 0x400000)*0x400000,
+ 0x100000);
+
+ rsvmem_dbg("CMD: %s\n", cmdbuf);
+ ret = run_command(cmdbuf, 0);
+ if (ret != 0 ) {
+ rsvmem_err("fdt set /reserved-memory/ramoops reg error.\n");
+ return -3;
+ }
+ }
+
+ memset(cmdbuf, 0, sizeof(cmdbuf));
sprintf(cmdbuf, "fdt get value secmon_clear_range /secmon clear_range;");
if (run_command(cmdbuf, 0) == 0) {
memset(cmdbuf, 0, sizeof(cmdbuf));
@@ -260,11 +287,17 @@
unsigned int bl32_rsvmem_start = 0;
rsvmem_info("reserved memory:\n");
- data = readl(P_AO_SEC_GP_CFG3);
- bl31_rsvmem_size = ((data & 0xffff0000) >> 16) << 10;
- bl32_rsvmem_size = (data & 0x0000ffff) << 10;
- bl31_rsvmem_start = readl(P_AO_SEC_GP_CFG5);
- bl32_rsvmem_start = readl(P_AO_SEC_GP_CFG4);
+ data = readl(REG_RSVMEM_SIZE);
+ /* workaround for bl3x size */
+ if ((data >> 16) & 0xf0) {
+ bl31_rsvmem_size = ((data & 0xffff0000) >> 16) << 16;
+ bl32_rsvmem_size = (data & 0x0000ffff) << 16;
+ } else {
+ bl31_rsvmem_size = ((data & 0xffff0000) >> 16) << 10;
+ bl32_rsvmem_size = (data & 0x0000ffff) << 10;
+ }
+ bl31_rsvmem_start = readl(REG_RSVMEM_BL31_START);
+ bl32_rsvmem_start = readl(REG_RSVMEM_BL32_START);
rsvmem_info("bl31 reserved memory start: 0x%08x\n", bl31_rsvmem_start);
rsvmem_info("bl31 reserved memory size: 0x%08x\n", bl31_rsvmem_size);
diff --git a/cmd/amlogic/cmd_tsensor.c b/cmd/amlogic/cmd_tsensor.c
index 4ca7b41..9f4d2ef 100644
--- a/cmd/amlogic/cmd_tsensor.c
+++ b/cmd/amlogic/cmd_tsensor.c
@@ -1,3 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include <common.h>
#include <command.h>
#include <asm/arch/tsensor.h>
@@ -17,14 +22,11 @@
printf("too little args for temp triming!!\n");
return CMD_RET_USAGE;
}
-
temp_base = simple_strtoul(argv[1], NULL, 10);
printf("set base temperature: %d\n", temp_base);
-
ver = simple_strtoul(argv[2], NULL, 16);
ret = temp_trim_entry(temp_base, ver);
- if (!ret)
- printf("temperature triming error %x\n", ret);
+ printf("temperature triming %x\n", ret);
return ret;
}
@@ -52,21 +54,14 @@
" - [ver]: [decimal]only for New thermal sensor\n"
" BBT: OPS socket board, which can change chips\n"
" online: reference boards witch chip mounted\n"
- " AXG or TXHD:\n"
- " 5 (0101)b: BBT, thermal0\n"
- " 6 (0110)b: BBT, thermal1\n"
- " 7 (0111)b: BBT, thermal01\n"
- " d (1101)b: online, thermal0\n"
- " e (1110)b: online, thermal1\n"
- " f (1111)b: online, thermal01\n"
" G12A or G12B:\n"
" 88 (10001000)b: BBT-SW, thermal1 thermal2, valid thermal cali data\n"
" 89 (10001001)b: BBT-OPS, thermal1 thermal2, valid thermal cali data\n"
- " 8b (10001001)b: SLT, thermal1 thermal2, valid thermal cali data\n"
- " TL1:\n"
- " 8c (10001001)b: BBT-SW, thermal1 ~ 3, valid thermal cali data\n"
- " 8d (10001001)b: BBT-OPS, thermal1 ~ 3, valid thermal cali data\n"
- " 8f (10001001)b: SLT, thermal1 ~ 3, valid thermal cali data\n";
+ " 8b (10001011)b: SLT, thermal1 thermal2, valid thermal cali data\n"
+ " A1:\n"
+ " 84 (10000100)b: BBT-SW, thermal1, valid thermal cali data\n"
+ " 85 (10000101)b: BBT-OPS, thermal1, valid thermal cali data\n"
+ " 87 (10000111)b: SLT, thermal1, valid thermal cali data\n";
U_BOOT_CMD(
temp_triming, 5, 1, do_temp_triming,
diff --git a/cmd/amlogic/cmd_version.c b/cmd/amlogic/cmd_version.c
new file mode 100644
index 0000000..dfab020
--- /dev/null
+++ b/cmd/amlogic/cmd_version.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <version.h>
+#include <linux/compiler.h>
+
+static int do_bootloadr_version(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ char s_version[64];
+ strcpy(s_version, "01.01.");
+ strcat(s_version, U_BOOT_DATE_TIME);
+ printf("s_version: %s\n", s_version);
+ env_set("bootloader_version", s_version);
+ return 0;
+}
+
+U_BOOT_CMD(
+ get_bootloaderversion, 1, 0, do_bootloadr_version,
+ "print bootloader version",
+ ""
+);
diff --git a/cmd/amlogic/cmd_vout.c b/cmd/amlogic/cmd_vout.c
index 1c6d8aa..c1e44f5 100644
--- a/cmd/amlogic/cmd_vout.c
+++ b/cmd/amlogic/cmd_vout.c
@@ -1,22 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2012
- * Amlogic. Inc. jets.yan@amlogic.com
- *
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -29,7 +13,7 @@
#endif
#include <amlogic/media/vout/aml_vout.h>
#ifdef CONFIG_AML_HDMITX
-#include <amlogic/media/vout/hdmitx.h>
+#include <amlogic/media/vout/hdmitx/hdmitx.h>
#endif
#ifdef CONFIG_AML_CVBS
@@ -39,15 +23,37 @@
#include <amlogic/media/vout/lcd/aml_lcd.h>
#endif
+static unsigned int vout_parse_vout_name(char *name)
+{
+ char *p, *frac_str;
+ unsigned int frac = 0;
+
+ p = strchr(name, ',');
+ if (!p) {
+ frac = 0;
+ } else {
+ frac_str = p + 1;
+ *p = '\0';
+ if (strcmp(frac_str, "frac") == 0)
+ frac = 1;
+ }
+
+ return frac;
+}
+
static int do_vout_list(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
{
-#ifdef CONFIG_AML_LCD
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
+#ifdef CONFIG_AML_HDMITX
+ struct hdmitx_dev *hdmitx_device = hdmitx_get_hdev();
#endif
#ifdef CONFIG_AML_HDMITX
- printf("\nvalid hdmi mode:\n");
- hdmitx_device.HWOp.list_support_modes();
+ if (!hdmitx_device) {
+ printf("\nerror: hdmitx device is null\n");
+ } else {
+ printf("\nvalid hdmi mode:\n");
+ hdmitx_device->hwop.list_support_modes();
+ }
#endif
#ifdef CONFIG_AML_CVBS
@@ -57,14 +63,7 @@
#ifdef CONFIG_AML_LCD
printf("\nvalid lcd mode:\n");
- if (lcd_drv) {
- if (lcd_drv->list_support_mode)
- lcd_drv->list_support_mode();
- else
- printf("no lcd list_support_mode\n");
- } else {
- printf("no lcd driver\n");
- }
+ aml_lcd_driver_list_support_mode();
#endif
return CMD_RET_SUCCESS;
@@ -72,58 +71,264 @@
static int do_vout_output(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
+ char *mode;
+ unsigned int frac;
+#if defined(CONFIG_AML_CVBS) || defined(CONFIG_AML_HDMITX) || defined(CONFIG_AML_LCD)
+ unsigned int mux_sel = VIU_MUX_MAX, venc_sel = VIU_MUX_MAX;
+#endif
#ifdef CONFIG_AML_HDMITX
- char mode[64];
+ char str[64];
#endif
#ifdef CONFIG_AML_LCD
- struct aml_lcd_drv_s *lcd_drv = NULL;
+ unsigned int venc_index;
#endif
if (argc != 2)
return CMD_RET_FAILURE;
+ mode = (char *)malloc(64 * sizeof(char));
+ if (!mode) {
+ printf("cmd_vout: mode malloc falied, exit\n");
+ return CMD_RET_FAILURE;
+ }
+ memset(mode, 0, (sizeof(char) * 64));
+ sprintf(mode, "%s", argv[1]);
+ frac = vout_parse_vout_name(mode);
+
#ifdef CONFIG_AML_CVBS
- if (cvbs_outputmode_check(argv[1]) == 0) {
+ mux_sel = cvbs_outputmode_check(mode, frac);
+ venc_sel = mux_sel & 0xf;
+ if (venc_sel == VIU_MUX_ENCI) {
+ vout_viu_mux(VOUT_VIU1_SEL, mux_sel);
#ifdef CONFIG_AML_VPP
vpp_matrix_update(VPP_CM_YUV);
#endif
- if (cvbs_set_vmode(argv[1]) == 0)
+ if (cvbs_set_vmode(mode) == 0) {
+ free(mode);
+ run_command("setenv vout_init enable", 0);
return CMD_RET_SUCCESS;
+ }
}
#endif
#ifdef CONFIG_AML_HDMITX
- if (hdmi_outputmode_check(argv[1]) == 0) {
+ if (frac == 0) { /* remove frac support in outputmode */
+ mux_sel = hdmi_outputmode_check(mode, frac);
+ venc_sel = mux_sel & 0xf;
+ if (venc_sel < VIU_MUX_MAX) {
+ vout_viu_mux(VOUT_VIU1_SEL, mux_sel);
#ifdef CONFIG_AML_VPP
- vpp_matrix_update(VPP_CM_YUV);
+ vpp_matrix_update(VPP_CM_YUV);
#endif
- memset(mode, 0, sizeof(mode));
- sprintf(mode, "hdmitx output %s", argv[1]);
- run_command(mode, 0);
+ /* //remove frac support in outputmode
+ *if (frac)
+ * setenv("frac_rate_policy", "1");
+ *else
+ * setenv("frac_rate_policy", "0");
+ */
+ memset(str, 0, sizeof(str));
+ sprintf(str, "hdmitx output %s", mode);
+ run_command(str, 0);
+ free(mode);
+ run_command("setenv vout_init enable", 0);
+ return CMD_RET_SUCCESS;
+ }
+ }
+#endif
+
+#ifdef CONFIG_AML_LCD
+ mux_sel = aml_lcd_driver_outputmode_check(mode, frac);
+ venc_sel = mux_sel & 0xf;
+ venc_index = (mux_sel >> 4) & 0xf;
+ if (venc_sel == VIU_MUX_ENCL) {
+ vout_viu_mux(VOUT_VIU1_SEL, mux_sel);
+#ifdef CONFIG_AML_VPP
+ vpp_matrix_update(VPP_CM_RGB);
+#endif
+ aml_lcd_driver_enable(venc_index, mode, frac);
+ free(mode);
+ run_command("setenv vout_init enable", 0);
+ return CMD_RET_SUCCESS;
+ }
+#endif
+
+ printf("outputmode[%s] is invalid\n", argv[1]);
+ do { (void)frac; } while(0);
+
+ free(mode);
+ return CMD_RET_FAILURE;
+}
+
+static int do_vout2_list(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+#ifdef CONFIG_AML_HDMITX
+ struct hdmitx_dev *hdmitx_device = hdmitx_get_hdev();
+#endif
+
+#ifdef CONFIG_AML_HDMITX
+ if (!hdmitx_device) {
+ printf("\nerror: hdmitx device is null\n");
+ } else {
+ printf("\nvalid hdmi mode:\n");
+ hdmitx_device->hwop.list_support_modes();
+ }
+#endif
+
+#ifdef CONFIG_AML_CVBS
+ printf("\nvalid cvbs mode:\n");
+ cvbs_show_valid_vmode();
+#endif
+
+#ifdef CONFIG_AML_LCD
+ printf("\nvalid lcd mode:\n");
+ aml_lcd_driver_list_support_mode();
+#endif
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_vout2_output(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ char *mode;
+ unsigned int frac;
+#if defined(CONFIG_AML_CVBS) || defined(CONFIG_AML_HDMITX) || defined(CONFIG_AML_LCD)
+ unsigned int mux_sel = VIU_MUX_MAX, venc_sel = VIU_MUX_MAX;
+#endif
+#ifdef CONFIG_AML_HDMITX20
+ char str[64];
+#endif
+#ifdef CONFIG_AML_LCD
+ unsigned int venc_index;
+#endif
+
+ if (argc != 2)
+ return CMD_RET_FAILURE;
+
+ mode = (char *)malloc(64 * sizeof(char));
+ if (!mode) {
+ printf("cmd_vout: mode malloc falied, exit\n");
+ return CMD_RET_FAILURE;
+ }
+ memset(mode, 0, (sizeof(char) * 64));
+ sprintf(mode, "%s", argv[1]);
+ frac = vout_parse_vout_name(mode);
+
+#ifdef CONFIG_AML_CVBS
+ mux_sel = cvbs_outputmode_check(mode, frac);
+ venc_sel = mux_sel & 0xf;
+ if (venc_sel == VIU_MUX_ENCI) {
+ if (cvbs_set_vmode(mode) == 0) {
+ free(mode);
+ return CMD_RET_SUCCESS;
+ }
+ }
+#endif
+
+#ifdef CONFIG_AML_HDMITX20
+ if (frac == 0) { /* remove frac support in outputmode */
+ mux_sel = hdmi_outputmode_check(mode, frac);
+ venc_sel = mux_sel & 0xf;
+ if (venc_sel < VIU_MUX_MAX) {
+ /* //remove frac support in outputmode
+ *if (frac)
+ * setenv("frac_rate_policy", "1");
+ *else
+ * setenv("frac_rate_policy", "0");
+ */
+ memset(str, 0, sizeof(str));
+ sprintf(str, "hdmitx output %s", mode);
+ run_command(str, 0);
+ free(mode);
+ return CMD_RET_SUCCESS;
+ }
+ }
+#endif
+
+#ifdef CONFIG_AML_LCD
+ mux_sel = aml_lcd_driver_outputmode_check(mode, frac);
+ venc_sel = mux_sel & 0xf;
+ venc_index = (mux_sel >> 4) & 0xf;
+ if (venc_sel == VIU_MUX_ENCL) {
+ aml_lcd_driver_enable(venc_index, mode, frac);
+ free(mode);
+ return CMD_RET_SUCCESS;
+ }
+#endif
+
+ printf("outputmode[%s] is invalid\n", argv[1]);
+ do { (void)frac; } while(0);
+
+ free(mode);
+ return CMD_RET_FAILURE;
+}
+
+static int do_vout2_prepare(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ char *mode;
+ unsigned int frac;
+#if defined(CONFIG_AML_CVBS) || defined(CONFIG_AML_HDMITX) || defined(CONFIG_AML_LCD)
+ unsigned int mux_sel = VIU_MUX_MAX, venc_sel = VIU_MUX_MAX;
+#endif
+#ifdef CONFIG_AML_LCD
+ unsigned int venc_index;
+#endif
+
+ if (argc != 2)
+ return CMD_RET_FAILURE;
+
+ mode = (char *)malloc(64 * sizeof(char));
+ if (!mode) {
+ printf("cmd_vout: mode malloc falied, exit\n");
+ return CMD_RET_FAILURE;
+ }
+ memset(mode, 0, (sizeof(char) * 64));
+ sprintf(mode, "%s", argv[1]);
+ frac = vout_parse_vout_name(mode);
+
+#ifdef CONFIG_AML_CVBS
+ mux_sel = cvbs_outputmode_check(mode, frac);
+ venc_sel = mux_sel & 0xf;
+ if (venc_sel == VIU_MUX_ENCI) {
+ vout_viu_mux(VOUT_VIU2_SEL, mux_sel);
+#ifdef CONFIG_AML_VPP
+ vpp_viu2_matrix_update(VPP_CM_YUV);
+#endif
+ free(mode);
+ return CMD_RET_SUCCESS;
+ }
+#endif
+
+#ifdef CONFIG_AML_HDMITX20
+ mux_sel = hdmi_outputmode_check(mode, frac);
+ venc_sel = mux_sel & 0xf;
+ if (venc_sel < VIU_MUX_MAX) {
+ vout_viu_mux(VOUT_VIU2_SEL, mux_sel);
+#ifdef CONFIG_AML_VPP
+ vpp_viu2_matrix_update(VPP_CM_YUV);
+#endif
+ free(mode);
return CMD_RET_SUCCESS;
}
#endif
#ifdef CONFIG_AML_LCD
- lcd_drv = aml_lcd_get_driver();
- if (lcd_drv) {
- if (lcd_drv->lcd_outputmode_check) {
- if (lcd_drv->lcd_outputmode_check(argv[1]) == 0) {
+ mux_sel = aml_lcd_driver_outputmode_check(mode, frac);
+ venc_sel = mux_sel & 0xf;
+ venc_index = (mux_sel >> 4) & 0xf;
+ if (venc_sel == VIU_MUX_ENCL) {
+ vout_viu_mux(VOUT_VIU2_SEL, mux_sel);
#ifdef CONFIG_AML_VPP
- vpp_matrix_update(VPP_CM_RGB);
+ vpp_viu2_matrix_update(VPP_CM_RGB);
#endif
- if (lcd_drv->lcd_enable) {
- lcd_drv->lcd_enable(argv[1]);
- return CMD_RET_SUCCESS;
- } else
- printf("no lcd enable\n");
- }
- }
- } else {
- printf("no lcd driver\n");
+ aml_lcd_driver_prepare(venc_index, mode, frac);
+ free(mode);
+ return CMD_RET_SUCCESS;
}
#endif
+ do { (void)frac; } while(0);
+
+ free(mode);
return CMD_RET_FAILURE;
}
@@ -165,3 +370,36 @@
" format : perfered output video mode\n"
" info : dump vinfo\n"
);
+
+static cmd_tbl_t cmd_vout2_sub[] = {
+ U_BOOT_CMD_MKENT(list, 1, 1, do_vout2_list, "", ""),
+ U_BOOT_CMD_MKENT(prepare, 3, 1, do_vout2_prepare, "", ""),
+ U_BOOT_CMD_MKENT(output, 3, 1, do_vout2_output, "", ""),
+ U_BOOT_CMD_MKENT(info, 1, 1, do_vout_info, "", ""),
+};
+
+static int do_vout2(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ cmd_tbl_t *c;
+
+ if (argc < 2)
+ return cmd_usage(cmdtp);
+
+ argc--;
+ argv++;
+
+ c = find_cmd_tbl(argv[0], &cmd_vout2_sub[0], ARRAY_SIZE(cmd_vout2_sub));
+
+ if (c)
+ return c->cmd(cmdtp, flag, argc, argv);
+ else
+ return cmd_usage(cmdtp);
+}
+
+U_BOOT_CMD(vout2, CONFIG_SYS_MAXARGS, 1, do_vout2,
+ "VOUT2 sub-system",
+ "vout2 [list | prepare format | output format | info]\n"
+ " list : list for valid video mode names.\n"
+ " format : perfered output video mode\n"
+ " info : dump vinfo\n"
+);
diff --git a/cmd/amlogic/cmd_vpp.c b/cmd/amlogic/cmd_vpp.c
index b3fde37..b9491c0 100644
--- a/cmd/amlogic/cmd_vpp.c
+++ b/cmd/amlogic/cmd_vpp.c
@@ -1,3 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include <common.h>
#include <command.h>
#include <amlogic/media/vpp/vpp.h>
@@ -33,8 +38,34 @@
return CMD_RET_SUCCESS;
}
+static int do_hdr_packet(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+
+ if (argc < 1) {
+ printf("[vpp] hdr packet error !!!\n");
+ return cmd_usage(cmdtp);
+ }
+
+ extern bool check_dolby_vision_on(void);
+ if (!check_dolby_vision_on()) {
+ printf("hdr_packet\n");
+ hdr_tx_pkt_cb();
+ }
+
+ return CMD_RET_SUCCESS;
+}
+
+static int do_vpp_init(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ vpp_init();
+ return CMD_RET_SUCCESS;
+
+}
+
static cmd_tbl_t cmd_vpp_sub[] = {
U_BOOT_CMD_MKENT(pq, 5, 1, do_vpp_pq, "", ""),
+ U_BOOT_CMD_MKENT(hdrpkt, 1, 1, do_hdr_packet, "", ""),
+ U_BOOT_CMD_MKENT(init, 2, 0, do_vpp_init, "", ""),
};
static int do_vpp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -58,4 +89,5 @@
U_BOOT_CMD(vpp, CONFIG_SYS_MAXARGS, 0, do_vpp,
"vpp sub-system",
"osd+video pq value brightness/contrast/saturation/hue parameters\n"
+ "vpp init - init vpp\n"
);
diff --git a/cmd/amlogic/cmd_vpu.c b/cmd/amlogic/cmd_vpu.c
index fec2045..b692c25 100644
--- a/cmd/amlogic/cmd_vpu.c
+++ b/cmd/amlogic/cmd_vpu.c
@@ -1,5 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Amlogic VPU debug function
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
diff --git a/cmd/amlogic/defenv_without.c b/cmd/amlogic/defenv_without.c
index 70e8cc1..90026a7 100644
--- a/cmd/amlogic/defenv_without.c
+++ b/cmd/amlogic/defenv_without.c
@@ -1,15 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file cmd_defenv_without.c
- * \brief use this cmd but not 'env default',
- * to reserve some envs after defaulting envs
- *
- * \version 1.0.0
- * \date 15/09/29
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2015 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include <config.h>
#include <common.h>
#include <command.h>
@@ -80,7 +73,7 @@
}
}
- set_default_env("## defenv_reserve\n", 0);
+ set_default_env("## defenv_reserve ##", 0);
if (sumOfEnvVal)
{
diff --git a/cmd/amlogic/flash_ts.c b/cmd/amlogic/flash_ts.c
deleted file mode 100644
index b72105e..0000000
--- a/cmd/amlogic/flash_ts.c
+++ /dev/null
@@ -1,66 +0,0 @@
-/*
- * Flash-based transactional key-value store
- *
- * Copyright (C) 2010 Google, Inc.
- * Author: Eugene Surovegin <es@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- */
-#include <amlogic/flash_ts.h>
-#include <amlogic/nand_ts.h>
-#include <amlogic/mmc_ts.h>
-
-int flash_ts_set(const char *key, const char *value)
-{
- int res = 0;
-#ifdef CONFIG_NAND_FTS
- res = nand_ts_set(key, value);
-#endif
-
-#ifdef CONFIG_MMC_FTS
- res = mmc_ts_set(key, value);
-#endif
- return res;
-}
-
-void flash_ts_get(const char *key, char *value, unsigned int size)
-{
-#ifdef CONFIG_NAND_FTS
- nand_ts_get(key, value, size);
-#endif
-
-#ifdef CONFIG_MMC_FTS
- mmc_ts_get(key, value, size);
-#endif
-}
-
-int flash_ts_init(void)
-{
- int res = 0;
-#ifdef CONFIG_NAND_FTS
- res = nand_ts_init();
-#endif
-
-#ifdef CONFIG_MMC_FTS
- res = mmc_ts_init();
-#endif
- return res;
-}
-
-int is_flash_inited(void)
-{
-#if defined(CONFIG_NAND_FTS)
- extern bool amlnf_is_inited(void);
- return amlnf_is_inited()
-#endif
-#if defined(CONFIG_MMC_FTS)
- extern bool amlmmc_is_inited(void);
- return amlmmc_is_inited();
-#endif
-}
-
-/* Make sure MTD subsystem is already initialized */
-late_initcall(flash_ts_init);
diff --git a/cmd/amlogic/get_bcb_boot_part.c b/cmd/amlogic/get_bcb_boot_part.c
new file mode 100644
index 0000000..e51e909
--- /dev/null
+++ b/cmd/amlogic/get_bcb_boot_part.c
@@ -0,0 +1,230 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <malloc.h>
+#include <asm/byteorder.h>
+#include <config.h>
+#include <asm/arch/io.h>
+#include <partition_table.h>
+#include <version.h>
+#include <amlogic/store_wrapper.h>
+
+#define COMMANDBUF_SIZE 32
+#define STATUSBUF_SIZE 32
+#define RECOVERYBUF_SIZE 768
+
+#define BOOTINFO_OFFSET 864
+#define SLOTBUF_SIZE 32
+#define BCB_INFO_SZ 1024
+
+#define DbgP(fmt...) //printf("D[BCB]L%d:", __LINE__),printf(fmt)
+#define ErrP(fmt...) printf("E[BCB]L%d:", __LINE__),printf(fmt)
+#define MsgP(fmt...) printf("[BCB]"fmt)
+
+#pragma pack(push, 4)
+struct recovery_message {
+ char command[32];
+ char status[32];
+ char recovery[768];
+
+ // The 'recovery' field used to be 1024 bytes. It has only ever
+ // been used to store the recovery command line, so 768 bytes
+ // should be plenty. We carve off the last 256 bytes to store the
+ // stage string (for multistage packages) and possible future
+ // expansion.
+ char stage[32];
+};
+
+typedef struct BrilloSlotInfo {
+ uint8_t bootable;
+ uint8_t online;
+ uint8_t reserved[2];
+} BrilloSlotInfo;
+
+#define MAX_SLOT_NUM 4
+typedef struct BrilloBootInfo {
+ // Used by fs_mgr. Must be NUL terminated.
+ char bootctrl_suffix[4];
+
+ // Magic for identification - must be 'B', 'C', 'c' (short for
+ // "boot_control copy" implementation).
+ uint8_t magic[3];
+
+ // Version of BrilloBootInfo struct, must be 0 or larger.
+ uint8_t version;
+
+ // Currently active slot.
+ uint8_t active_slot;
+
+ uint8_t attemp_times;
+ uint8_t maxTryTimes;
+ uint8_t numSlots;//slots number, >=2 if support multiple system switch
+
+ // Information about each slot.
+ BrilloSlotInfo slot_info[MAX_SLOT_NUM]; //at last and can extend to any number you need
+
+} BrilloBootInfo;
+
+struct bootloader_control_msg {
+ struct recovery_message recovery;
+ struct BrilloBootInfo bootInfo;
+};
+#pragma pack(pop)
+
+static bool boot_info_validate(BrilloBootInfo* info)
+{
+ if (info->magic[0] != 'B' ||
+ info->magic[1] != 'C' ||
+ info->magic[2] != 'c')
+ return false;
+ if (info->active_slot >= MAX_SLOT_NUM)
+ return false;
+ return true;
+}
+
+static void dump_boot_info(BrilloBootInfo* info)
+{
+ MsgP("info->active_slot = %u\n", info->active_slot);
+ MsgP("info->attemp_times = %u / %u\n", info->attemp_times, info->maxTryTimes);
+ MsgP("info->slot_info[0].bootable = %u\n", info->slot_info[0].bootable);
+ MsgP("info->slot_info[0].online = %u\n", info->slot_info[0].online);
+ MsgP("info->slot_info[1].bootable = %u\n", info->slot_info[1].bootable);
+ MsgP("info->slot_info[1].online = %u\n", info->slot_info[1].online);
+}
+
+/*
+ * code flow:
+ * if recovery_message->command valid, yes then run into upgrade mode
+ * if info->numSlots == 1, then NOT a/b system mode, just set boot_part as 'boot'
+ * if info->numSlots > 1, then IS a/b system mode
+ * if attemp_times >= maxTryTimes; then
+ * try info[active_slot]
+ * else try next slot
+ * */
+static int parse_and_update_bcb(struct bootloader_control_msg* bcb, int* needUpdateMisc)
+{
+ struct recovery_message* recoveryInfo = &(bcb->recovery);
+ BrilloBootInfo* info = &(bcb->bootInfo);
+
+ *needUpdateMisc = 1;
+ DbgP("command:%s, recovery:%s\n", recoveryInfo->command, recoveryInfo->recovery);
+ if (!memcmp(recoveryInfo->command, "boot-recovery", strlen("boot-recovery"))) {
+ MsgP("need boot recovery, maybe upgrading not completed\n");
+ run_command("run storeargs; run update", 0);
+ return 0;
+ }
+
+ if (!boot_info_validate(info)) {
+ MsgP("boot-info is invalid. Resetting.\n");
+ return CMD_RET_FAILURE;
+ }
+ dump_boot_info(info);
+
+ const int numSlots = info->numSlots;
+ if (numSlots < 1) {
+ ErrP("slots num %d invalid\n", numSlots);
+ return CMD_RET_FAILURE;
+ }
+ if (numSlots < 2) {
+ MsgP("slots num %d < 2, so don't support multiple system switch\n", numSlots);
+ env_set("active_slot","normal");
+ env_set("boot_part","boot");
+ *needUpdateMisc = 0;
+ return 0;
+ }
+
+ int slotIndex = info->active_slot;
+ MsgP("active slot = %d \n", slotIndex);
+ BrilloSlotInfo* slotInf = info->slot_info + slotIndex;
+
+ int attemp_times = info->attemp_times;
+ MsgP("attemp_times = %d \n", attemp_times);
+ do {
+ if (slotInf->bootable) {
+ MsgP("current slot %d already bootable, just boot it\n", slotIndex);
+ *needUpdateMisc = 0;
+ break;
+ }
+
+ //current active slot NOT bootable, try until system marked bootable
+ if (attemp_times > info->maxTryTimes) {
+ MsgP("Try next as slot[%d] tried times %d > max %d!!!\n", slotIndex, attemp_times, (int)(info->maxTryTimes));
+ attemp_times = 0;
+ slotIndex += 1;
+ slotIndex = slotIndex < numSlots ? slotIndex : (slotIndex - numSlots);
+ slotInf = info->slot_info + slotIndex;
+ continue;
+ }
+ attemp_times += 1;
+ break;
+ }while(1);
+ info->attemp_times = attemp_times;
+ info->active_slot = slotIndex;
+
+ char bootName[8];
+ const int iPostfix = 4;
+ const int nlen = strlen("bootA");
+ memcpy(bootName, "bootA", nlen + 1);
+ if (slotIndex > 0) bootName[iPostfix] += slotIndex;
+ env_set("active_slot", bootName + iPostfix);//"_a" or "-b"
+ env_set("boot_part", bootName);
+ run_command("setenv dsp_part dsp${active_slot}", 0);
+ memcpy(info->bootctrl_suffix, bootName + iPostfix, iPostfix);
+
+ char* slotSuffix = bootName + iPostfix;//"a" or "b"
+ slotSuffix[0] = slotSuffix[0] - 'A' + '0'; //"0" or "1"
+ env_set("slot-suffixes", slotSuffix);
+ run_command("printenv slot-suffixes boot_part active_slot dsp_part", 0);
+
+ return 0;
+}
+
+static int do_GetValidSlot(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ struct bootloader_control_msg* loadaddr = NULL;
+ const char* bcbPart = argc > 1 ? argv[1] : "misc";
+ if ( argc < 3 ) {//default address is env $loadaddr
+ loadaddr = (struct bootloader_control_msg*)env_get_hex("loadaddr", 0x4000);
+ } else {
+ loadaddr = (struct bootloader_control_msg*)simple_strtoul(argv[2], NULL, 16);
+ }
+ DbgP("bcbPart %s, loadaddr %p\n", bcbPart, loadaddr);
+ int rc = store_logic_read(bcbPart, 0, BCB_INFO_SZ, loadaddr);
+ if (rc) {
+ ErrP("Fail read bcb from part %s\n", bcbPart);
+ return CMD_RET_FAILURE;
+ }
+
+ int needUpdateMisc = 0;
+ rc = parse_and_update_bcb(loadaddr, &needUpdateMisc);
+ if (rc) {
+ ErrP("Fail parse bcb from part %s\n", bcbPart);
+ return CMD_RET_FAILURE;
+ }
+ if (!needUpdateMisc) return CMD_RET_SUCCESS;
+
+ rc = store_erase(bcbPart, 0, 0, 0);//erase whole misc part
+ if (rc) {
+ ErrP("Fail erase bcb from part %s\n", bcbPart);
+ return CMD_RET_FAILURE;
+ }
+ rc = store_logic_write(bcbPart, 0, BCB_INFO_SZ, loadaddr);
+ if (rc) {
+ ErrP("Fail read bcb from part %s\n", bcbPart);
+ return CMD_RET_FAILURE;
+ }
+ return CMD_RET_SUCCESS;
+}
+
+U_BOOT_CMD(
+ get_boot_part, 3, 0, do_GetValidSlot,
+ "get part name to load the bootable part",
+ "\nThis command will get which partititon name should be used for booting\n"
+ " argv: get_boot_part <bcbPartName> <loadaddr>\n" //usage
+);
+
diff --git a/cmd/amlogic/imgread.c b/cmd/amlogic/imgread.c
old mode 100755
new mode 100644
index 934f6ca..84232aa
--- a/cmd/amlogic/imgread.c
+++ b/cmd/amlogic/imgread.c
@@ -1,14 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file cmd_imgread.c
- * \brief command to read the actual size of boot.img/recovery.img and logo.img
- *
- * \version 1.0.0
- * \date 2013/10/29
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2013 Amlogic Inc.. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include <config.h>
#include <common.h>
#include <image.h>
@@ -16,11 +10,15 @@
#include <android_image.h>
#include <asm/arch/bl31_apis.h>
#include <asm/arch/secure_apb.h>
-#include <amlogic/storage.h>
+#include <amlogic/store_wrapper.h>
#include <amlogic/aml_efuse.h>
-#include <zircon/image.h>
+#include <malloc.h>
-typedef struct andr_img_hdr boot_img_hdr;
+#ifndef IS_FEAT_BOOT_VERIFY
+#define IS_FEAT_BOOT_VERIFY() 0
+#endif// #ifndef IS_FEAT_BOOT_VERIFY
+int __attribute__((weak)) store_logic_read(const char *name, loff_t off, size_t size, void *buf)
+{ return store_read(name, off, size, buf);}
#define debugP(fmt...) //printf("[Dbg imgread]L%d:", __LINE__),printf(fmt)
#define errorP(fmt...) printf("Err imgread(L%d):", __LINE__),printf(fmt)
@@ -31,9 +29,6 @@
#define PIC_PRELOAD_SZ (8U<<10) //Total read 4k at first to read the image header
#define RES_OLD_FMT_READ_SZ (8U<<20)
-#define CONFIG_AML_SECURE_BOOT_FOR_GOOGLE 1
-
-#ifndef CONFIG_AML_SECURE_BOOT_FOR_GOOGLE
typedef struct __aml_enc_blk{
unsigned int nOffset;
unsigned int nRawLength;
@@ -82,49 +77,28 @@
#define COMPILE_TYPE_ASSERT(expr, t) typedef char t[(expr) ? 1 : -1]
COMPILE_TYPE_ASSERT(2048 >= sizeof(AmlSecureBootImgHeader), _cc);
-#else /* CONFIG_AML_SECURE_BOOT_FOR_GOOGLE */
-typedef struct {
- uint32_t magic;
- uint32_t version;
- uint32_t flags;
- uint32_t img_version;
- uint32_t img_size;
- uint32_t img_offset;
- uint8_t img_hash[32];
- uint8_t reserved[200];
- uint8_t rsa_sig[256];
-} aml_boot_header_t;
-#endif /* CONFIG_AML_SECURE_BOOT_FOR_GOOGLE */
-static int is_secure_boot_enabled(void)
-{
- const unsigned long cfg10 = readl(AO_SEC_SD_CFG10);
- return ( cfg10 & (0x1<< 4) );
-}
-
-#ifndef CONFIG_AML_SECURE_BOOT_FOR_GOOGLE
static int is_andr_9_image(void* pBuffer)
{
+
int nReturn = 0;
if (!pBuffer)
goto exit;
- struct andr_img_hdr *pAHdr = (struct andr_img_hdr*)(unsigned long)pBuffer;
+ boot_img_hdr_t *pAHdr = (boot_img_hdr_t*)(unsigned long)pBuffer;
- if (pAHdr->kernel_version)
+ if (pAHdr->header_version)
nReturn = 1;
exit:
return nReturn;
+
}
-#endif
static int _aml_get_secure_boot_kernel_size(const void* pLoadaddr, unsigned* pTotalEncKernelSz)
{
- const int isSecure = is_secure_boot_enabled();
-#ifndef CONFIG_AML_SECURE_BOOT_FOR_GOOGLE
const AmlEncryptBootImgInfo* amlEncrypteBootimgInfo = 0;
int rc = 0;
unsigned secureKernelImgSz = 2048;
@@ -174,14 +148,6 @@
*pTotalEncKernelSz = secureKernelImgSz;
return 0;
-#else /* CONFIG_AML_SECURE_BOOT_FOR_GOOGLE */
- if (isSecure) {
- if (pLoadaddr && pTotalEncKernelSz)
- *pTotalEncKernelSz = (((aml_boot_header_t *)pLoadaddr)->img_size);
- }
- return 0;
-
-#endif /* CONFIG_AML_SECURE_BOOT_FOR_GOOGLE */
}
static int do_image_read_dtb_from_knl(const char* partName, unsigned char* loadaddr, uint64_t lflashReadOff)
@@ -190,11 +156,12 @@
unsigned int nFlashLoadLen = 0;
unsigned secureKernelImgSz = 0;
const int preloadSz = 4096;
- boot_img_hdr *hdr_addr = (boot_img_hdr*)loadaddr;
+ int pageSz = 0;
+ boot_img_hdr_t *hdr_addr = (boot_img_hdr_t*)loadaddr;
nFlashLoadLen = preloadSz;//head info is one page size == 2k
debugP("sizeof preloadSz=%u\n", nFlashLoadLen);
- nReturn = store_read(partName, lflashReadOff, nFlashLoadLen, loadaddr);
+ nReturn = store_logic_read(partName, lflashReadOff, nFlashLoadLen, loadaddr);
if (nReturn) {
errorP("Fail to read 0x%xB from part[%s] at offset 0\n", nFlashLoadLen, partName);
return __LINE__;
@@ -205,17 +172,62 @@
return __LINE__;
}
- nReturn = _aml_get_secure_boot_kernel_size(loadaddr, &secureKernelImgSz);
- if (nReturn) {
- errorP("Fail in _aml_get_secure_boot_kernel_size, rc=%d\n", nReturn);
- return __LINE__;
- }
+ if (is_android_r_image((void *) hdr_addr)) {
+ const int preloadSz_r = 0x1000;
+ int rc_r = 0;
+ char *slot_name;
- const int pageSz = hdr_addr->page_size;
- lflashReadOff += pageSz;
- lflashReadOff += ALIGN(hdr_addr->kernel_size, pageSz);
- lflashReadOff += ALIGN(hdr_addr->ramdisk_size, pageSz);
- nFlashLoadLen = ALIGN(hdr_addr->second_size, pageSz);
+ slot_name = env_get("slot-suffixes");
+ if (strcmp(slot_name, "0") == 0) {
+ strcpy((char *)partName, "vendor_boot_a");
+ } else if (strcmp(slot_name, "1") == 0) {
+ strcpy((char *)partName, "vendor_boot_b");
+ }
+ MsgP("partName = %s \n", partName);
+
+ nFlashLoadLen = preloadSz_r;//head info is one page size == 4k
+ debugP("sizeof preloadSz=%u\n", nFlashLoadLen);
+
+ nReturn = store_logic_read(partName,lflashReadOff, nFlashLoadLen, loadaddr);
+ if (nReturn) {
+ errorP("Fail to read 0x%xB from part[%s] at offset 0\n", nFlashLoadLen, partName);
+ return __LINE__;
+ }
+
+ p_vendor_boot_img_hdr_t pVendorIMGHDR = (p_vendor_boot_img_hdr_t)loadaddr;
+
+ rc_r = vendor_boot_image_check_header(pVendorIMGHDR);
+ if (!rc_r) {
+ unsigned long ramdisk_size_r,dtb_size_r;
+ pageSz = pVendorIMGHDR->page_size;
+
+ /* Android R's vendor_boot partition include ramdisk and dtb */
+ ramdisk_size_r = ALIGN(pVendorIMGHDR->vendor_ramdisk_size, pageSz);
+ dtb_size_r = ALIGN(pVendorIMGHDR->dtb_size, pageSz);
+ nFlashLoadLen = dtb_size_r;
+ lflashReadOff = ramdisk_size_r + 0x1000;
+ debugP("ramdisk_size_r 0x%x, totalSz 0x%lx\n", pVendorIMGHDR->vendor_ramdisk_size, ramdisk_size_r);
+ debugP("dtb_size_r 0x%x, totalSz 0x%lx\n", pVendorIMGHDR->dtb_size, dtb_size_r);
+ debugP("lflashReadOff=0x%llx\n", lflashReadOff);
+ debugP("nFlashLoadLen=0x%x\n", nFlashLoadLen);
+ }else {
+ errorP("check vendor_boot header error\n");
+ return __LINE__;
+ }
+
+ } else {
+ nReturn = _aml_get_secure_boot_kernel_size(loadaddr, &secureKernelImgSz);
+ if (nReturn) {
+ errorP("Fail in _aml_get_secure_boot_kernel_size, rc=%d\n", nReturn);
+ return __LINE__;
+ }
+
+ pageSz = hdr_addr->page_size;
+ lflashReadOff += pageSz;
+ lflashReadOff += ALIGN(hdr_addr->kernel_size, pageSz);
+ lflashReadOff += ALIGN(hdr_addr->ramdisk_size, pageSz);
+ nFlashLoadLen = ALIGN(hdr_addr->second_size, pageSz);
+ }
debugP("lflashReadOff=0x%llx, nFlashLoadLen=0x%x\n", lflashReadOff, nFlashLoadLen);
debugP("page sz %u\n", hdr_addr->page_size);
@@ -224,7 +236,7 @@
return __LINE__;
}
unsigned char* secondAddr = (unsigned char*)loadaddr + lflashReadOff;
- nReturn = store_read(partName, lflashReadOff, nFlashLoadLen, secondAddr);
+ nReturn = store_logic_read(partName, lflashReadOff, nFlashLoadLen, secondAddr);
if (nReturn) {
errorP("Fail to read 0x%xB from part[%s] at offset 0x%x\n", nFlashLoadLen, partName, (unsigned int)lflashReadOff);
return __LINE__;
@@ -243,7 +255,7 @@
MsgP("decrypted dtb sz 0x%x\n", nFlashLoadLen);
}
- char* dtDestAddr = (char*)loadaddr;//simple_strtoull(env_get("dtb_mem_addr"), NULL, 0);
+ char* dtDestAddr = (char*)loadaddr;//simple_strtoull(getenv("dtb_mem_addr"), NULL, 0);
memmove(dtDestAddr, secondAddr, nFlashLoadLen);
return nReturn;
@@ -257,7 +269,7 @@
errorP("dtbMaxSz(0x%x) invalid\n", dtbMaxSz);
return -__LINE__;
}
- int iRet = store_rsv_read("dtb", dtbMaxSz/2, loadaddr);
+ int iRet = store_rsv_read("dtb", dtbMaxSz, loadaddr);
if (iRet) {
errorP("Fail read dtb from rsv with sz 0x%x\n", dtbMaxSz);
return -__LINE__;
@@ -278,103 +290,50 @@
//imgread dtb rsv ${dtb_mem_addr}
static int do_image_read_dtb(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- boot_img_hdr *hdr_addr = NULL;
+ int iRet = 0;
const char* const partName = argv[1];
unsigned char* loadaddr = 0;
- int nReturn = __LINE__;
uint64_t lflashReadOff = 0;
- unsigned int nFlashLoadLen = 0;
- unsigned secureKernelImgSz = 0;
- const int preloadSz = 4096;
-
if (2 < argc) {
loadaddr = (unsigned char*)simple_strtoul(argv[2], NULL, 16);
- }
- else{
+ } else{
loadaddr = (unsigned char*)simple_strtoul(env_get("loadaddr"), NULL, 16);
}
- hdr_addr = (boot_img_hdr*)loadaddr;
if (3 < argc) lflashReadOff = simple_strtoull(argv[3], NULL, 0) ;
- nFlashLoadLen = preloadSz;//head info is one page size == 2k
- debugP("sizeof preloadSz=%u\n", nFlashLoadLen);
- nReturn = store_read((unsigned char*)partName, lflashReadOff, nFlashLoadLen, loadaddr);
- if (nReturn) {
- errorP("Fail to read 0x%xB from part[%s] at offset 0\n", nFlashLoadLen, partName);
- return __LINE__;
+ const int fromRsv = !strcmp("_aml_dtb", argv[1]);
+ if ( fromRsv ) {
+ iRet = do_image_read_dtb_from_rsv(loadaddr);
+ } else {
+ iRet = do_image_read_dtb_from_knl(partName, loadaddr, lflashReadOff);
}
- if (IMAGE_FORMAT_ANDROID != genimg_get_format(hdr_addr)) {
- errorP("Fmt unsupported! only support 0x%x\n", IMAGE_FORMAT_ANDROID);
- return __LINE__;
- }
-
- nReturn = _aml_get_secure_boot_kernel_size(loadaddr, &secureKernelImgSz);
- if (nReturn) {
- errorP("Fail in _aml_get_secure_boot_kernel_size, rc=%d\n", nReturn);
- return __LINE__;
- }
-
- const int pageSz = hdr_addr->page_size;
- /*lflashReadOff += secureKernelImgSz ? sizeof(AmlSecureBootImgHeader) : pageSz;*/
- lflashReadOff += pageSz;
- lflashReadOff += ALIGN(hdr_addr->kernel_size, pageSz);
- lflashReadOff += ALIGN(hdr_addr->ramdisk_size, pageSz);
- nFlashLoadLen = ALIGN(hdr_addr->second_size, pageSz);
-
- debugP("lflashReadOff=0x%llx, nFlashLoadLen=0x%x\n", lflashReadOff, nFlashLoadLen);
- debugP("page sz %u\n", hdr_addr->page_size);
- if (!nFlashLoadLen) {
- errorP("NO second part in kernel image\n");
- return __LINE__;
- }
- unsigned char* dtImgAddr = (unsigned char*)loadaddr + lflashReadOff;
- nReturn = store_read((unsigned char*)partName, lflashReadOff, nFlashLoadLen, dtImgAddr);
- if (nReturn) {
- errorP("Fail to read 0x%xB from part[%s] at offset 0x%x\n", nFlashLoadLen, partName, (unsigned int)lflashReadOff);
- return __LINE__;
- }
-
- if (secureKernelImgSz) {
- //because secure boot will use DMA which need disable MMU temp
- //here must update the cache, otherwise nand will fail (eMMC is OK)
- flush_cache((unsigned long)dtImgAddr,(unsigned long)nFlashLoadLen);
-
- nReturn = aml_sec_boot_check(AML_D_P_IMG_DECRYPT,(unsigned long)loadaddr,GXB_IMG_SIZE,GXB_IMG_DEC_DTB);
- if (nReturn) {
- errorP("\n[dtb]aml log : Sig Check is %d\n",nReturn);
- return __LINE__;
- }
- MsgP("Enc dtb sz 0x%x\n", nFlashLoadLen);
- }
-
- char* dtDestAddr = (char*)loadaddr;//simple_strtoull(env_get("dtb_mem_addr"), NULL, 0);
- unsigned long fdtAddr = (unsigned long)dtImgAddr;
+ unsigned long fdtAddr = (unsigned long)loadaddr;
#ifdef CONFIG_MULTI_DTB
extern unsigned long get_multi_dt_entry(unsigned long fdt_addr);
- fdtAddr = get_multi_dt_entry((unsigned long)dtImgAddr);
+ fdtAddr = get_multi_dt_entry((unsigned long)fdtAddr);
if (!fdtAddr) {
- errorP("Fail in fdt chk\n");
+ errorP("Fail in get_multi_dt_entry\n");
return __LINE__;
}
#endif// #ifdef CONFIG_MULTI_DTB
- nReturn = fdt_check_header((char*)fdtAddr);
- if (nReturn) {
+ iRet = fdt_check_header((char*)fdtAddr);
+ if (iRet) {
errorP("Fail in fdt check header\n");
return CMD_RET_FAILURE;
}
const unsigned fdtsz = fdt_totalsize((char*)fdtAddr);
- memmove(dtDestAddr, (char*)fdtAddr, fdtsz);
+ memmove(loadaddr, (char*)fdtAddr, fdtsz);
- return nReturn;
+ return iRet;
}
static int do_image_read_kernel(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
unsigned kernel_size;
unsigned ramdisk_size;
- boot_img_hdr *hdr_addr = NULL;
+ boot_img_hdr_t *hdr_addr = NULL;
int genFmt = 0;
unsigned actualBootImgSz = 0;
unsigned dtbSz = 0;
@@ -383,7 +342,6 @@
int rc = 0;
uint64_t flashReadOff = 0;
unsigned secureKernelImgSz = 0;
- uint32_t offset = 0;
if (2 < argc) {
loadaddr = (unsigned char*)simple_strtoul(argv[2], NULL, 16);
@@ -391,89 +349,201 @@
else{
loadaddr = (unsigned char*)simple_strtoul(env_get("loadaddr"), NULL, 16);
}
-#ifdef CONFIG_AML_SECURE_BOOT_FOR_GOOGLE
- if (is_secure_boot_enabled()) {
- offset = sizeof(aml_boot_header_t);
- }
-#endif /* CONFIG_AML_SECURE_BOOT_FOR_GOOGLE */
-
- hdr_addr = (boot_img_hdr*)(loadaddr + offset);
+ hdr_addr = (boot_img_hdr_t*)loadaddr;
if (3 < argc) flashReadOff = simple_strtoull(argv[3], NULL, 0) ;
- rc = store_read((unsigned char*)partName, flashReadOff, IMG_PRELOAD_SZ, loadaddr);
+ rc = store_logic_read(partName, flashReadOff, IMG_PRELOAD_SZ, loadaddr);
if (rc) {
errorP("Fail to read 0x%xB from part[%s] at offset 0\n", IMG_PRELOAD_SZ, partName);
return __LINE__;
}
flashReadOff += IMG_PRELOAD_SZ;
-#ifdef CONFIG_AML_SECURE_BOOT_FOR_GOOGLE
- if (!is_secure_boot_enabled()) {
-#endif /* CONFIG_AML_SECURE_BOOT_FOR_GOOGLE */
- genFmt = genimg_get_format(hdr_addr);
- if ((IMAGE_FORMAT_ANDROID != genFmt) &&
- (IMAGE_FORMAT_ZIRCON != genFmt)) {
- errorP("Fmt unsupported!genFmt 0x%x != 0x%x or 0x%x\n",
- genFmt, IMAGE_FORMAT_ANDROID, IMAGE_FORMAT_ZIRCON);
- return __LINE__;
- } else {
- MsgP("OK genFmt = %d\n", genFmt);
- }
-#ifdef CONFIG_AML_SECURE_BOOT_FOR_GOOGLE
- }
-#endif /* CONFIG_AML_SECURE_BOOT_FOR_GOOGLE */
+ if (!is_android_r_image((void *) hdr_addr)) {
- //Check if encrypted image
- rc = _aml_get_secure_boot_kernel_size(loadaddr, &secureKernelImgSz);
- if (rc) {
+ extern p_vendor_boot_img_t p_vender_boot_img;
+
+ /*free vendor buffer first*/
+ if (p_vender_boot_img) {
+ free(p_vender_boot_img);
+ p_vender_boot_img = 0;
+ }
+ genFmt = genimg_get_format(hdr_addr);
+ if (IMAGE_FORMAT_ANDROID != genFmt) {
+ errorP("Fmt unsupported!genFmt 0x%x != 0x%x\n", genFmt, IMAGE_FORMAT_ANDROID);
+ return __LINE__;
+ }
+
+ //Check if encrypted image
+ rc = _aml_get_secure_boot_kernel_size(loadaddr, &secureKernelImgSz);
+ if (rc) {
errorP("Fail in _aml_get_secure_boot_kernel_size, rc=%d\n", rc);
return __LINE__;
+ }
+ if (secureKernelImgSz) {
+ actualBootImgSz = secureKernelImgSz;
+ MsgP("secureKernelImgSz=0x%x\n", actualBootImgSz);
+ }
+ else {
+ kernel_size =(hdr_addr->kernel_size + (hdr_addr->page_size-1)+hdr_addr->page_size)&(~(hdr_addr->page_size -1));
+ ramdisk_size =(hdr_addr->ramdisk_size + (hdr_addr->page_size-1))&(~(hdr_addr->page_size -1));
+ dtbSz = hdr_addr->second_size;
+ actualBootImgSz = kernel_size + ramdisk_size + dtbSz;
+ debugP("kernel_size 0x%x, page_size 0x%x, totalSz 0x%x\n", hdr_addr->kernel_size, hdr_addr->page_size, kernel_size);
+ debugP("ramdisk_size 0x%x, totalSz 0x%x\n", hdr_addr->ramdisk_size, ramdisk_size);
+ debugP("dtbSz 0x%x, Total actualBootImgSz 0x%x\n", dtbSz, actualBootImgSz);
+ }
+
+ if (actualBootImgSz > IMG_PRELOAD_SZ) {
+ const unsigned leftSz = actualBootImgSz - IMG_PRELOAD_SZ;
+
+ debugP("Left sz 0x%x\n", leftSz);
+ rc = store_logic_read(partName, flashReadOff, leftSz, loadaddr + IMG_PRELOAD_SZ);
+ if (rc) {
+ errorP("Fail to read 0x%xB from part[%s] at offset 0x%x\n", leftSz, partName, IMG_PRELOAD_SZ);
+ return __LINE__;
+ }
+ }
+ debugP("totalSz=0x%x\n", actualBootImgSz);
+
+ //because secure boot will use DMA which need disable MMU temp
+ //here must update the cache, otherwise nand will fail (eMMC is OK)
+ flush_cache((unsigned long)loadaddr,(unsigned long)actualBootImgSz);
+
+ return 0;
}
- if (secureKernelImgSz)
- {
- actualBootImgSz = secureKernelImgSz + offset;
- MsgP("secureKernelImgSz=0x%x\n", actualBootImgSz);
- } else if (genFmt == IMAGE_FORMAT_ZIRCON) {
- const zbi_header_t *zbi = (zbi_header_t *)hdr_addr;
+ else {
+ extern p_vendor_boot_img_t p_vender_boot_img;
- actualBootImgSz = zbi->length + sizeof(*zbi);
- } else {
- kernel_size =(hdr_addr->kernel_size + (hdr_addr->page_size-1)+hdr_addr->page_size)&(~(hdr_addr->page_size -1));
- ramdisk_size =(hdr_addr->ramdisk_size + (hdr_addr->page_size-1))&(~(hdr_addr->page_size -1));
- dtbSz = hdr_addr->second_size;
- actualBootImgSz = kernel_size + ramdisk_size + dtbSz;
- debugP("kernel_size 0x%x, page_size 0x%x, totalSz 0x%x\n", hdr_addr->kernel_size, hdr_addr->page_size, kernel_size);
- debugP("ramdisk_size 0x%x, totalSz 0x%x\n", hdr_addr->ramdisk_size, ramdisk_size);
- debugP("dtbSz 0x%x, Total actualBootImgSz 0x%x\n", dtbSz, actualBootImgSz);
- }
+ /*free vendor buffer first*/
+ if (p_vender_boot_img) {
+ free(p_vender_boot_img);
+ p_vender_boot_img = 0;
+ }
-#if defined(CONFIG_IMG_SECURE_CHECK_SZ)
- // Check if boot image size is larger than the secure boot size limitation. See doc:
- // https://docs.google.com/document/d/1YrW2yBzCbMrQfBR2n56aUPZPg_0waxveOH-E0NU07OM/edit?usp=sharing
- if (actualBootImgSz > CONFIG_IMG_SECURE_CHECK_SZ) {
- errorP("Boot image size(0x%x) is larger than secure size limit(0x%x)\n", actualBootImgSz, CONFIG_IMG_SECURE_CHECK_SZ);
- return __LINE__;
- }
-#endif //CONFIG_IMG_SECURE_CHECK_SZ
-
- if (actualBootImgSz > IMG_PRELOAD_SZ)
- {
- const unsigned leftSz = actualBootImgSz - IMG_PRELOAD_SZ;
-
- debugP("Left sz 0x%x\n", leftSz);
- rc = store_read((unsigned char*)partName, flashReadOff, leftSz, loadaddr + IMG_PRELOAD_SZ);
- if (rc) {
- errorP("Fail to read 0x%xB from part[%s] at offset 0x%x\n", leftSz, partName, IMG_PRELOAD_SZ);
+ genFmt = genimg_get_format(hdr_addr);
+ if (IMAGE_FORMAT_ANDROID != genFmt) {
+ errorP("Fmt unsupported!genFmt 0x%x != 0x%x\n", genFmt, IMAGE_FORMAT_ANDROID);
return __LINE__;
}
+
+ //Check if encrypted image
+ rc = _aml_get_secure_boot_kernel_size(loadaddr, &secureKernelImgSz);
+ if (rc) {
+ errorP("Fail in _aml_get_secure_boot_kernel_size, rc=%d\n", rc);
+ return __LINE__;
+ }
+ if (secureKernelImgSz) {
+ actualBootImgSz = secureKernelImgSz;
+ MsgP("secureKernelImgSz=0x%x\n", actualBootImgSz);
+ }
+ else {
+ p_boot_img_hdr_v3_t hdr_addr_v3 = NULL;
+ hdr_addr_v3 = (p_boot_img_hdr_v3_t)hdr_addr;
+ kernel_size = ALIGN(hdr_addr_v3->kernel_size,0x1000);
+ ramdisk_size = ALIGN(hdr_addr_v3->ramdisk_size,0x1000);
+ debugP("kernel_size 0x%x, totalSz 0x%x\n", hdr_addr_v3->kernel_size, kernel_size);
+ debugP("ramdisk_size 0x%x, totalSz 0x%x\n", hdr_addr_v3->ramdisk_size, ramdisk_size);
+
+ actualBootImgSz = kernel_size + ramdisk_size + 0x1000;
+
+ if (actualBootImgSz > IMG_PRELOAD_SZ) {
+ const unsigned leftSz = actualBootImgSz - IMG_PRELOAD_SZ;
+
+ debugP("Left sz 0x%x\n", leftSz);
+ rc = store_logic_read(partName, flashReadOff, leftSz,loadaddr + IMG_PRELOAD_SZ);
+ if (rc) {
+ errorP("Fail to read 0x%xB from part[%s] at offset 0x%x\n", leftSz, partName, IMG_PRELOAD_SZ);
+ return __LINE__;
+ }
+ }
+ debugP("totalSz=0x%x\n", actualBootImgSz);
+ /*
+ because secure boot will use DMA which need disable MMU temp
+ here must update the cache, otherwise nand will fail (eMMC is OK)
+ */
+ flush_cache((unsigned long)loadaddr,(unsigned long)actualBootImgSz);
+
+ /*
+ Android R need read vendor_boot partition
+ define Android R variable add suffix xxx_r
+ */
+ char partName_r[32] = {0};
+ int nReturn_r = __LINE__;
+ uint64_t lflashReadOff_r = 0;
+ unsigned int nFlashLoadLen_r = 0;
+ const int preloadSz_r = 0x1000;
+ unsigned char * pBuffPreload = 0;
+ int rc_r = 0;
+ char *slot_name;
+
+ slot_name = env_get("slot-suffixes");
+ if (strcmp(slot_name, "0") == 0) {
+ strcpy((char *)partName_r, "vendor_boot_a");
+ }
+ else if (strcmp(slot_name, "1") == 0) {
+ strcpy((char *)partName_r, "vendor_boot_b");
+ }
+ MsgP("partName_r = %s\n", partName_r);
+
+ nFlashLoadLen_r = preloadSz_r; //head info is one page size == 4k
+ debugP("sizeof preloadSz=%u\n", nFlashLoadLen_r);
+
+ pBuffPreload = malloc(preloadSz_r);
+
+ if (!pBuffPreload) {
+ printf("aml log : system error! Fail to allocate memory for %s!\n",partName_r);
+ return __LINE__;
+ }
+ nReturn_r = store_logic_read(partName_r,lflashReadOff_r, nFlashLoadLen_r, pBuffPreload);
+
+ if (nReturn_r) {
+ errorP("Fail to read 0x%xB from part[%s] at offset 0\n", nFlashLoadLen_r, partName_r);
+ free(pBuffPreload);
+ pBuffPreload = 0;
+ return __LINE__;
+ }
+ p_vendor_boot_img_hdr_t pVendorIMGHDR = (p_vendor_boot_img_hdr_t)pBuffPreload;
+
+ rc_r = vendor_boot_image_check_header(pVendorIMGHDR);
+ if (!rc_r) {
+ unsigned long ramdisk_size_r,dtb_size_r;
+ const int pageSz_r = pVendorIMGHDR->page_size;
+
+ /* Android R's vendor_boot partition include ramdisk and dtb */
+ ramdisk_size_r = ALIGN(pVendorIMGHDR->vendor_ramdisk_size, pageSz_r);
+ dtb_size_r = ALIGN(pVendorIMGHDR->dtb_size, pageSz_r);
+ nFlashLoadLen_r = ramdisk_size_r + dtb_size_r + 0x1000;
+ debugP("ramdisk_size_r 0x%x, totalSz 0x%x\n", pVendorIMGHDR->vendor_ramdisk_size, ramdisk_size_r);
+ debugP("dtb_size_r 0x%x, totalSz 0x%x\n", pVendorIMGHDR->dtb_size, dtb_size_r);
+
+ if (nFlashLoadLen_r > preloadSz_r) {
+ free(pBuffPreload);
+ pBuffPreload=malloc(nFlashLoadLen_r);
+ if (!pBuffPreload)
+ return __LINE__;
+ rc_r = store_logic_read(partName_r, lflashReadOff_r, nFlashLoadLen_r, pBuffPreload);
+ if (rc_r) {
+ errorP("Fail to read 0x%xB from part[%s] at offset 0x%x\n",
+ (unsigned int)nFlashLoadLen_r, partName_r, (unsigned int)lflashReadOff_r);
+ free(pBuffPreload);
+ pBuffPreload = 0;
+ return __LINE__;
+ }
+ }
+
+ debugP("totalSz=0x%x\n", nFlashLoadLen_r);
+ flush_cache((unsigned long)pBuffPreload,nFlashLoadLen_r);
+
+ p_vender_boot_img = (p_vendor_boot_img_t)pBuffPreload;
+ }
+ else {
+ free(pBuffPreload);
+ pBuffPreload=0;
+ }
+ } /*ANDROID R/S*/
}
- debugP("totalSz=0x%x\n", actualBootImgSz);
-
- //because secure boot will use DMA which need disable MMU temp
- //here must update the cache, otherwise nand will fail (eMMC is OK)
- flush_cache((unsigned long)loadaddr,(unsigned long)actualBootImgSz);
-
return 0;
}
@@ -538,7 +608,7 @@
}
pResImgHead = (AmlResImgHead_t*)loadaddr;
- rc = store_read((unsigned char*)partName, flashReadOff, IMG_PRELOAD_SZ, loadaddr);
+ rc = store_logic_read(partName, flashReadOff, IMG_PRELOAD_SZ, loadaddr);
if (rc) {
errorP("Fail to read 0x%xB from part[%s] at offset 0\n", IMG_PRELOAD_SZ, partName);
return __LINE__;
@@ -556,7 +626,7 @@
{
const unsigned leftSz = totalSz - flashReadOff;
- rc = store_read((unsigned char*)partName, flashReadOff, leftSz, loadaddr + (unsigned)flashReadOff);
+ rc = store_logic_read(partName, flashReadOff, leftSz, loadaddr + (unsigned)flashReadOff);
if (rc) {
errorP("Fail to read 0x%xB from part[%s] at offset 0x%x\n", leftSz, partName, IMG_PRELOAD_SZ);
return __LINE__;
@@ -607,107 +677,106 @@
//[imgread pic] logo bootup $loadaddr_misc
static int do_image_read_pic(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- const char* const partName = argv[1];
- unsigned char* loadaddr = 0;
- int rc = 0;
- const AmlResImgHead_t* pResImgHead = NULL;
- //unsigned totalSz = 0;
- uint64_t flashReadOff = 0;
- const unsigned PreloadSz = PIC_PRELOAD_SZ;//preload 8k, 124-1 pic header, If you need pack more than 123 items, fix this
- unsigned itemIndex = 0;
- const AmlResItemHead_t* pItem = NULL;
- const char* picName = argv[2];
+ const char* const partName = argv[1];
+ unsigned char* loadaddr = 0;
+ int rc = 0;
+ const AmlResImgHead_t* pResImgHead = NULL;
+ //unsigned totalSz = 0;
+ uint64_t flashReadOff = 0;
+ const unsigned PreloadSz = PIC_PRELOAD_SZ;//preload 8k, 124-1 pic header, If you need pack more than 123 items, fix this
+ unsigned itemIndex = 0;
+ const AmlResItemHead_t* pItem = NULL;
+ const char* picName = argv[2];
- loadaddr = (unsigned char*)simple_strtoul(argc > 3 ? argv[3] : env_get("loadaddr_misc"), NULL, 16);
+ loadaddr = (unsigned char*)simple_strtoul(argc > 3 ? argv[3] : env_get("loadaddr_misc"), NULL, 16);
- pResImgHead = (AmlResImgHead_t*)loadaddr;
+ pResImgHead = (AmlResImgHead_t*)loadaddr;
- debugP("to read pic (%s)\n", picName);
- rc = store_read((unsigned char*)partName, flashReadOff, PreloadSz, loadaddr);
- if (rc) {
- errorP("Fail to read 0x%xB from part[%s] at offset 0\n", PreloadSz, partName);
- return __LINE__;
- }
- flashReadOff = PreloadSz;
- debugP("end read pic sz %d\n", PreloadSz);
+ debugP("to read pic (%s)\n", picName);
+ rc = store_logic_read(partName, flashReadOff, PreloadSz, loadaddr);
+ if (rc) {
+ errorP("Fail to read 0x%xB from part[%s] at offset 0\n", PreloadSz, partName);
+ return __LINE__;
+ }
+ flashReadOff = PreloadSz;
+ debugP("end read pic sz %d\n", PreloadSz);
- if (img_res_check_log_header(pResImgHead)) {
- errorP("Logo header err.\n");
- return __LINE__;
- }
+ if (img_res_check_log_header(pResImgHead)) {
+ errorP("Logo header err.\n");
+ return __LINE__;
+ }
- //correct bootup for mbox
- while (!strcmp("bootup", picName))
- {
- char* outputmode = env_get("outputmode");
- if (!outputmode)break;//not env outputmode
+ //correct bootup for mbox
+ while (!strcmp("bootup", picName))
+ {
+ char* outputmode = env_get("outputmode");
+ if (!outputmode)break;//not env outputmode
- rc = !strncmp("720", outputmode, 3) || !strncmp("576", outputmode, 3) || !strncmp("480", outputmode, 3);
- if (rc) {
- picName = "bootup_720";
- break;
- }
+ rc = !strncmp("720", outputmode, 3) || !strncmp("576", outputmode, 3) || !strncmp("480", outputmode, 3);
+ if (rc) {
+ picName = "bootup_720";
+ break;
+ }
- picName = "bootup_1080";
- break;
- }
+ picName = "bootup_1080";
+ break;
+ }
- pItem = (AmlResItemHead_t*)(pResImgHead + 1);
- for (itemIndex = 0; itemIndex < pResImgHead->imgItemNum; ++itemIndex, ++pItem)
- {
- if (IH_MAGIC != pItem->magic) {
- errorP("item magic 0x%x != 0x%x\n", pItem->magic, IH_MAGIC);
- return __LINE__;
- }
- if (!strcmp(picName, pItem->name) || !strcmp(argv[2], pItem->name))
- {
- char env_name[IH_NMLEN*2];
- char env_data[IH_NMLEN*2];
- unsigned long picLoadAddr = (unsigned long)loadaddr + (unsigned)pItem->start;
- int itemSz = pItem->size;
- int uncompSz = 0;
+ pItem = (AmlResItemHead_t*)(pResImgHead + 1);
+ for (itemIndex = 0; itemIndex < pResImgHead->imgItemNum; ++itemIndex, ++pItem)
+ {
+ if (IH_MAGIC != pItem->magic) {
+ errorP("item magic 0x%x != 0x%x\n", pItem->magic, IH_MAGIC);
+ return __LINE__;
+ }
+ if (!strcmp(picName, pItem->name) || !strcmp(argv[2], pItem->name))
+ {
+ char env_name[IH_NMLEN*2];
+ char env_data[IH_NMLEN*2];
+ unsigned long picLoadAddr = (unsigned long)loadaddr + (unsigned)pItem->start;
+ int itemSz = pItem->size;
+ int uncompSz = 0;
- if (pItem->start + itemSz > flashReadOff)
- {
- unsigned long rdOff = pItem->start;
- unsigned long rdOffAlign = (rdOff >> 11) << 11;//align 2k page for mtd nand, 512 for emmc
- rc = store_read((unsigned char*)partName, rdOffAlign, itemSz + (rdOff & 0x7ff),
- (unsigned char *)((picLoadAddr>>11)<<11));
- if (rc) {
- errorP("Fail to read pic at offset 0x%x\n", pItem->start);
- return __LINE__;
- }
- debugP("pic sz 0x%x\n", itemSz);
- }
+ if (pItem->start + itemSz > flashReadOff)
+ {
+ unsigned long rdOff = pItem->start;
+ unsigned long rdOffAlign = (rdOff >> 11) << 11;//align 2k page for mtd nand, 512 for emmc
+ rc = store_logic_read(partName, rdOffAlign, itemSz + (rdOff & 0x7ff),(char*)((picLoadAddr>>11)<<11));
+ if (rc) {
+ errorP("Fail to read pic at offset 0x%x\n", pItem->start);
+ return __LINE__;
+ }
+ debugP("pic sz 0x%x\n", itemSz);
+ }
- //uncompress supported format
- unsigned long uncompLoadaddr = picLoadAddr + itemSz + 7;
- uncompLoadaddr &= ~(0x7U);
- rc = imgread_uncomp_pic((unsigned char*)picLoadAddr, itemSz, (unsigned char*)uncompLoadaddr,
- CONFIG_MAX_PIC_LEN, (unsigned long*)&uncompSz);
- if (rc) {
- errorP("Fail in uncomp pic,rc[%d]\n", rc);
- return __LINE__;
- }
- if (uncompSz) {
- itemSz = uncompSz;
- picLoadAddr = uncompLoadaddr;
- }
+ //uncompress supported format
+ unsigned long uncompLoadaddr = picLoadAddr + itemSz + 7;
+ uncompLoadaddr &= ~(0x7U);
+ rc = imgread_uncomp_pic((unsigned char*)picLoadAddr, itemSz, (unsigned char*)uncompLoadaddr,
+ CONFIG_MAX_PIC_LEN, (unsigned long*)&uncompSz);
+ if (rc) {
+ errorP("Fail in uncomp pic,rc[%d]\n", rc);
+ return __LINE__;
+ }
+ if (uncompSz) {
+ itemSz = uncompSz;
+ picLoadAddr = uncompLoadaddr;
+ }
- sprintf(env_name, "%s_offset", argv[2]);//be bootup_offset ,not bootup_720_offset
- sprintf(env_data, "0x%lx", picLoadAddr);
- env_set(env_name, env_data);
+ sprintf(env_name, "%s_offset", argv[2]);//be bootup_offset ,not bootup_720_offset
+ sprintf(env_data, "0x%lx", picLoadAddr);
+ env_set(env_name, env_data);
- sprintf(env_name, "%s_size", argv[2]);
- sprintf(env_data, "0x%x", itemSz);
- env_set(env_name, env_data);
+ sprintf(env_name, "%s_size", argv[2]);
+ sprintf(env_data, "0x%x", itemSz);
+ env_set(env_name, env_data);
- debugP("end read pic[%s]\n", picName);
- return 0;//success
- }
- }
+ debugP("end read pic[%s]\n", picName);
+ return 0;//success
+ }
+ }
- return __LINE__;//fail
+ return __LINE__;//fail
}
static cmd_tbl_t cmd_imgread_sub[] = {
@@ -719,9 +788,15 @@
static int do_image_read(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
+
+#ifdef CONFIG_PXP_EMULATOR
+ printf("\naml log : PXP image all use preload\n");
+ do { (void)cmd_imgread_sub[0]; } while(0);
+ return 0;
+#else
cmd_tbl_t *c;
- /* Strip off leading 'bmp' command argument */
+ /* Strip off leading 'imgread' command argument */
argc--;
argv++;
@@ -733,6 +808,7 @@
cmd_usage(cmdtp);
return 1;
}
+#endif //CONFIG_PXP_EMULATOR
}
U_BOOT_CMD(
@@ -743,7 +819,7 @@
"Read the image from internal flash with actual size", //description
" argv: <imageType> <part_name> <loadaddr> \n" //usage
" - <image_type> Current support is kernel/res(ource).\n"
- "imgread kernel --- Read image in fomart IMAGE_FORMAT_ANDROID or IMAGE_FORMAT_ZIRCON\n"
+ "imgread kernel --- Read image in fomart IMAGE_FORMAT_ANDROID\n"
"imgread dtb --- Read dtb in fomart IMAGE_FORMAT_ANDROID\n"
"imgread res --- Read image packed by 'Amlogic resource packer'\n"
"imgread picture --- Read one picture from Amlogic logo"
@@ -804,3 +880,29 @@
" un pack the logo image, which already loaded at <imgLoadaddr>.\n"
);
+#if defined(CONFIG_CMD_AUTOSCR)
+/*
+ * Keep for now for backward compatibility;
+ * remove later when support for "autoscr" goes away.
+ */
+static int
+do_autoscr (cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ printf ("\n### WARNING ### "
+ "\"autoscr\" is deprecated, use \"source\" instead ###\n\n");
+ if (argc < 2) {
+ printf("too few argc %d for %s\n", argc, argv[0]);
+ return CMD_RET_FAILURE;
+ }
+ env_set("_src_addr", argv[1]);
+ return run_command("echo _src_addr ${_src_addr}; source ${_src_addr}; env delete _src_addr", 0);
+}
+
+U_BOOT_CMD_COMPLETE(
+ autoscr, 2, 0, do_autoscr,
+ "DEPRECATED - use \"source\" command instead",
+ " argv: autoscr script_mem_addr",
+ var_complete
+);
+#endif//#if defined(CONFIG_CMD_AUTOSCR)
+
diff --git a/cmd/amlogic/ini/UnifyKey.c b/cmd/amlogic/ini/UnifyKey.c
new file mode 100644
index 0000000..b953672
--- /dev/null
+++ b/cmd/amlogic/ini/UnifyKey.c
@@ -0,0 +1,482 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "ini_config.h"
+
+#define LOG_TAG "UnifyKey"
+#define LOG_NDEBUG 0
+
+#include "ini_log.h"
+#include "UnifyKey.h"
+#include "ini_size_define.h"
+
+#if (defined (CC_INI_IO_USE_UNIFY_KEY))
+
+#if (!defined (CC_INI_IO_UKEY_USE_OTHER_MODULE))
+
+#if (defined(CC_COMPILE_IN_PC) || defined(CC_COMPILE_IN_ANDROID))
+
+#if (defined CC_COMPILE_IN_PC)
+
+#define CS_KEY_DATA_LIST_DEV_PATH "sys/class/unifykeys/list"
+#define CS_KEY_DATA_NAME_DEV_PATH "sys/class/unifykeys/name"
+
+static char gDevPath[256] = {0};
+static int GetDevPath(char path_buf[]) {
+ int tmp_len = 0;
+ FILE *dev_fp = NULL;
+
+ strcpy(path_buf, "sys/class/unifykeys/");
+ dev_fp = fopen(CS_KEY_DATA_NAME_DEV_PATH, "r");
+ if (dev_fp == NULL) {
+ ALOGE("%s, open %s ERROR(%s)!!\n", __FUNCTION__,
+ CS_KEY_DATA_NAME_DEV_PATH, strerror(errno));
+ return -1;
+ }
+
+ tmp_len = strlen(path_buf);
+ fscanf(dev_fp, "%s", path_buf + tmp_len);
+
+ fclose(dev_fp);
+ dev_fp = NULL;
+
+ return 0;
+}
+
+static const char *GetKeyDataWriteDevPath() {
+ memset((void *)gDevPath, 0, 256);
+ GetDevPath(gDevPath);
+ return gDevPath;
+}
+
+static const char *GetKeyDataReadDevPath() {
+ memset((void *)gDevPath, 0, 256);
+ GetDevPath(gDevPath);
+ return gDevPath;
+}
+
+#else
+
+#define CS_KEY_DATA_LIST_DEV_PATH "/sys/class/unifykeys/list"
+#define CS_KEY_DATA_NAME_DEV_PATH "/sys/class/unifykeys/name"
+
+static const char *GetKeyDataWriteDevPath() {
+ return "/sys/class/unifykeys/write";
+}
+
+static const char *GetKeyDataReadDevPath() {
+ return "/sys/class/unifykeys/read";
+}
+
+#endif //CC_COMPILE_IN_PC
+
+static int checkKeyNameInList(const char *key_name) {
+ FILE *dev_fp = NULL;
+ char *tmp_ptr = NULL;
+ char lineStr[1024];
+
+ dev_fp = fopen(CS_KEY_DATA_LIST_DEV_PATH, "r");
+ if (dev_fp == NULL) {
+ ALOGE("%s, open %s ERROR(%s)!!\n", __FUNCTION__,
+ CS_KEY_DATA_LIST_DEV_PATH, strerror(errno));
+ return -1;
+ }
+
+ while (fgets(lineStr, 1024, dev_fp) != NULL) {
+ tmp_ptr = strstr(lineStr, key_name);
+ if (tmp_ptr != NULL) {
+ break;
+ }
+
+ tmp_ptr = NULL;
+ }
+
+ fclose(dev_fp);
+ dev_fp = NULL;
+
+ if (tmp_ptr == NULL) {
+ return -1;
+ }
+
+ return 0;
+}
+
+int readUKeyData_no_header(const char *key_name, unsigned char data_buf[], int rd_size) {
+ int rd_cnt = 0;
+ FILE *dev_fp = NULL;
+
+ if (checkKeyNameInList(key_name) < 0) {
+ ALOGE("%s, key \"%s\" isn't exist in unifykeys list\n", __FUNCTION__, key_name);
+ return -1;
+ }
+
+ dev_fp = fopen(CS_KEY_DATA_NAME_DEV_PATH, "w");
+ if (dev_fp == NULL) {
+ ALOGE("%s, open %s ERROR(%s)!!\n", __FUNCTION__,
+ CS_KEY_DATA_NAME_DEV_PATH, strerror(errno));
+ return -1;
+ }
+
+ fprintf(dev_fp, "%s", key_name);
+
+ fclose(dev_fp);
+ dev_fp = NULL;
+
+ int mode = 1;
+
+ if (mode == 0) {
+ dev_fp = fopen(GetKeyDataReadDevPath(), "r");
+ if (dev_fp == NULL) {
+ ALOGE("%s, open %s ERROR(%s)!!\n", __FUNCTION__,
+ GetKeyDataReadDevPath(), strerror(errno));
+ return -1;
+ }
+
+ fscanf(dev_fp, "%s", data_buf);
+ rd_cnt = strlen((char *) data_buf);
+ } else {
+ dev_fp = fopen(GetKeyDataReadDevPath(), "rb");
+ if (dev_fp == NULL) {
+ ALOGE("%s, open %s ERROR(%s)!!\n", __FUNCTION__,
+ GetKeyDataReadDevPath(), strerror(errno));
+ return -1;
+ }
+
+ rd_cnt = fread(data_buf, 1, CC_ONE_SECTION_SIZE, dev_fp);
+ }
+
+ fclose(dev_fp);
+ dev_fp = NULL;
+
+ return rd_cnt;
+}
+
+int readUKeyData(const char *key_name, unsigned char data_buf[], int rd_size) {
+ int rd_cnt = 0;
+ FILE *dev_fp = NULL;
+
+ if (checkKeyNameInList(key_name) < 0) {
+ ALOGE("%s, key \"%s\" isn't exist in unifykeys list\n", __FUNCTION__, key_name);
+ return -1;
+ }
+
+ dev_fp = fopen(CS_KEY_DATA_NAME_DEV_PATH, "w");
+ if (dev_fp == NULL) {
+ ALOGE("%s, open %s ERROR(%s)!!\n", __FUNCTION__,
+ CS_KEY_DATA_NAME_DEV_PATH, strerror(errno));
+ return -1;
+ }
+
+ fprintf(dev_fp, "%s", key_name);
+
+ fclose(dev_fp);
+ dev_fp = NULL;
+
+ int mode = 1;
+
+ if (mode == 0) {
+ dev_fp = fopen(GetKeyDataReadDevPath(), "r");
+ if (dev_fp == NULL) {
+ ALOGE("%s, open %s ERROR(%s)!!\n", __FUNCTION__,
+ GetKeyDataReadDevPath(), strerror(errno));
+ return -1;
+ }
+
+ fscanf(dev_fp, "%s", data_buf);
+ rd_cnt = strlen((char *) data_buf);
+ } else {
+ dev_fp = fopen(GetKeyDataReadDevPath(), "rb");
+ if (dev_fp == NULL) {
+ ALOGE("%s, open %s ERROR(%s)!!\n", __FUNCTION__,
+ GetKeyDataReadDevPath(), strerror(errno));
+ return -1;
+ }
+
+ rd_cnt = fread(data_buf, 1, CC_ONE_SECTION_SIZE, dev_fp);
+ }
+
+ fclose(dev_fp);
+ dev_fp = NULL;
+
+ return rd_cnt;
+}
+
+int writeUKeyData(const char *key_name, unsigned char data_buf[], int wr_size) {
+ int wr_cnt = 0;
+ int dev_fd = -1;
+ FILE *dev_fp = NULL;
+
+ if (checkKeyNameInList(key_name) < 0) {
+ ALOGE("%s, key \"%s\" isn't exist in unifykeys list\n", __FUNCTION__, key_name);
+ return -1;
+ }
+
+ dev_fp = fopen(CS_KEY_DATA_NAME_DEV_PATH, "w");
+ if (dev_fp == NULL) {
+ ALOGE("%s, open %s ERROR(%s)!!\n", __FUNCTION__,
+ CS_KEY_DATA_NAME_DEV_PATH, strerror(errno));
+ return -1;
+ }
+
+ fprintf(dev_fp, "%s", key_name);
+
+ fclose(dev_fp);
+ dev_fp = NULL;
+
+ dev_fd = open(GetKeyDataWriteDevPath(), O_WRONLY | O_SYNC | O_CREAT | O_TRUNC, S_IRWXU | S_IRWXG | S_IRWXO);
+
+ if (dev_fd < 0) {
+ ALOGE("%s, open %s ERROR(%s)!!\n", __FUNCTION__,
+ GetKeyDataWriteDevPath(), strerror(errno));
+ return -1;
+ }
+
+ wr_cnt = write(dev_fd, data_buf, wr_size);
+
+ fsync(dev_fd);
+
+ close(dev_fd);
+ dev_fd = -1;
+
+ return wr_cnt;
+}
+
+#elif (defined CC_COMPILE_IN_UBOOT)
+
+#include "model.h"
+
+#define CC_UKEY_RETRY_CNT_MAX (5)
+
+static int checkUnifyKey(const char *key_name) {
+ int ret = 0, key_exist = 0, isSecure = 0;
+ unsigned int key_len = 0;
+ ssize_t key_size = 0;
+
+ // start check the key is exist?
+ ret = key_unify_query_exist(key_name, &key_exist);
+ if (ret) {
+ ALOGE("%s, %s query exist error.\n",__FUNCTION__, key_name);
+ return -1;
+ }
+ if (key_exist == 0) {
+ ALOGE("%s, %s is not exist.\n",__FUNCTION__, key_name);
+ return -1;
+ }
+ // end check the key is exist?
+
+ // start check the key is secure?
+ ret = key_unify_query_secure(key_name, &isSecure);
+ if (ret) {
+ ALOGE("%s, %s query secure error\n",__FUNCTION__, key_name);
+ return -1;
+ }
+ if (isSecure) {
+ ALOGE("%s, %s is secure key\n",__FUNCTION__, key_name);
+ return -1;
+ }
+ // end check the key is secure?
+
+ // start read and check data integrity
+ ret = key_unify_query_size(key_name, &key_size);
+ if (ret) {
+ ALOGE("%s, %s query size error\n",__FUNCTION__, key_name);
+ return -1;
+ }
+ //ALOGD("%s, %s size: %d\n",__FUNCTION__, key_name, (int)key_size);
+
+ key_len = (int)key_size;
+ //ALOGD("%s, %s size: %d\n",__FUNCTION__, key_name, key_len);
+
+ return key_len;
+}
+
+int readUKeyData_no_header(const char *key_name, unsigned char data_buf[], int rd_size) {
+ int ret = 0, key_len = 0;
+
+ key_len = checkUnifyKey(key_name);
+ if (key_len < 0) {
+ return -1;
+ } else if (key_len == 0) {
+ ALOGE("%s, %s size is zero\n",__FUNCTION__, key_name);
+ return -1;
+ } else if (key_len > rd_size) {
+ ALOGE("%s, %s key len is larger than rd size.\n",__FUNCTION__, key_name);
+ return -1;
+ }
+
+ ret = key_unify_read(key_name, data_buf, key_len);
+ if (ret) {
+ ALOGE("%s, %s unify read error\n",__FUNCTION__, key_name);
+ return -1;
+ }
+
+ return key_len;
+}
+
+int readUKeyData(const char *key_name, unsigned char data_buf[], int rd_size) {
+ int i = 0, ret = 0, key_len = 0, retry_cnt = 0, tmp_content_type = 0;
+ unsigned int key_crc = 0, key_crc32 = 0, tmp_len = 0, tmp_crc = 0;
+ struct all_info_header_s *pHeadPtr = NULL;
+
+ key_len = checkUnifyKey(key_name);
+ if (key_len < 0) {
+ return -1;
+ } else if (key_len == 0) {
+ ALOGE("%s, %s size is zero\n",__FUNCTION__, key_name);
+ return -1;
+ } else if (key_len > rd_size) {
+ ALOGE("%s, %s key len is larger than rd size.\n",__FUNCTION__, key_name);
+ return -1;
+ }
+
+unifykey_read:
+ ret = key_unify_read(key_name, data_buf, key_len);
+ if (ret) {
+ ALOGE("%s, %s unify read error\n",__FUNCTION__, key_name);
+ return -1;
+ }
+
+ //judge unfikey data type, default is binary data
+ tmp_content_type = 0;
+ for (i = 0; i < 14; i++) {
+ if (i < 8 || (i > 9 && i < 13)) {
+ if (!isxdigit(data_buf[i])) {
+ break;
+ }
+ } else if (i == 8 || i == 13) {
+ if (data_buf[i] != ',') {
+ break;
+ }
+ } else if (i == 9) {
+ if (data_buf[i] != 'V' && data_buf[i] != 'v') {
+ break;
+ }
+ }
+ }
+
+ if (i == 14) {
+ tmp_content_type = 1;
+ }
+
+ tmp_crc = 0;
+ tmp_len = 0;
+ if (tmp_content_type == 0) {
+ pHeadPtr = (struct all_info_header_s *)(data_buf);
+ tmp_crc = pHeadPtr->crc32;
+ tmp_len = pHeadPtr->data_len;
+ } else {
+ return key_len;
+ }
+
+ if (key_len != tmp_len) {
+ ALOGE("%s, %s data_len %d is not match key_len %d\n",__FUNCTION__,
+ key_name, tmp_len, key_len);
+ if (retry_cnt < CC_UKEY_RETRY_CNT_MAX) {
+ retry_cnt++;
+ goto unifykey_read;
+ } else {
+ ALOGE("%s, %s load unifykey failed\n",__FUNCTION__, key_name);
+ return -1;
+ }
+ }
+
+ key_crc = crc32(0, &data_buf[4], (key_len - 4)); //except crc32
+ key_crc32 = (unsigned int)key_crc;
+ if (key_crc32 != tmp_crc) {
+ ALOGE("%s, %s crc32 0x%08x is not match 0x%08x\n",__FUNCTION__,
+ key_name, tmp_crc, key_crc32);
+ if (retry_cnt < CC_UKEY_RETRY_CNT_MAX) {
+ retry_cnt++;
+ goto unifykey_read;
+ } else {
+ ALOGE("%s, %s load unifykey failed\n",__FUNCTION__, key_name);
+ return -1;
+ }
+ }
+ // end read and check data integrity
+
+ return key_len;
+}
+
+int writeUKeyData(const char *key_name, unsigned char data_buf[], int wr_size) {
+ // if the key is not burn data, the fucntion will return fail
+ // now we disable the unifykey check function.
+/*
+ int key_len = 0;
+
+ key_len = checkUnifyKey(key_name);
+ if (key_len < 0) {
+ return -1;
+ }
+*/
+ if (key_unify_write(key_name, data_buf, wr_size) == 0) {
+ return wr_size;
+ }
+ return -1;
+}
+
+#endif
+
+#endif
+
+#if (defined CC_UBOOT_RW_SIMULATE)
+
+#include "ini_io.h"
+
+unsigned int crc32(unsigned int crc, const unsigned char *ptr, int buf_len) {
+ return CalCRC32(crc, ptr, buf_len);
+}
+
+static unsigned char gTempBuf[0x400000];
+
+int key_unify_write(const char* keyname, const void* keydata, const unsigned datalen) {
+ int tmp_ret = 0;
+
+ tmp_ret = writeUKeyData(keyname, (unsigned char *)keydata, datalen);
+ if (tmp_ret != datalen) {
+ return -1;
+ }
+ return 0;
+}
+
+int key_unify_read(const char* keyname, void* keydata, const unsigned bufLen) {
+ if (readUKeyData(keyname, (unsigned char *)keydata, CC_ONE_SECTION_SIZE) <= 0) {
+ return -1;
+ }
+
+ return 0;
+}
+
+int key_unify_query_size(const char* keyname, ssize_t *keysize) {
+ int rd_size = 0;
+
+ rd_size = readUKeyData(keyname, gTempBuf, CC_ONE_SECTION_SIZE);
+ if (rd_size > 0) {
+ *keysize = rd_size;
+ return 0;
+ }
+
+ return -1;
+}
+
+int key_unify_query_exist(const char* keyname, int *exist) {
+ if (checkKeyNameInList(keyname) < 0) {
+ ALOGE("%s, key \"%s\" isn't exist in unifykeys list\n", __FUNCTION__, keyname);
+ *exist = 0;
+ return -1;
+ }
+
+ *exist = 1;
+ return 0;
+}
+
+int key_unify_query_secure(const char* keyname, int *isSecure) {
+ *isSecure = 0;
+ return 0;
+}
+
+#endif
+
+#endif //CC_INI_IO_UKEY_USE_OTHER_MODULE
diff --git a/cmd/amlogic/ini/UnifyKey.h b/cmd/amlogic/ini/UnifyKey.h
new file mode 100644
index 0000000..1a73542
--- /dev/null
+++ b/cmd/amlogic/ini/UnifyKey.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __UNIFYKEY_H__
+#define __UNIFYKEY_H__
+
+#include "ini_config.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int readUKeyData_no_header(const char *key_name, unsigned char data_buf[], int rd_size);
+int readUKeyData(const char *key_name, unsigned char data_buf[], int rd_size);
+int writeUKeyData(const char *key_name, unsigned char data_buf[], int wr_size);
+
+#if (defined CC_UBOOT_RW_SIMULATE)
+
+unsigned int crc32(unsigned int crc, const unsigned char *ptr, int buf_len);
+int key_unify_write(const char* keyname, const void* keydata, const unsigned datalen);
+int key_unify_read(const char* keyname, void* keydata, const unsigned bufLen);
+int key_unify_query_size(const char* keyname, ssize_t* keysize);
+int key_unify_query_exist(const char* keyname, int *exist);
+int key_unify_query_secure(const char* keyname, int *isSecure);
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__UNIFYKEY_H__
diff --git a/cmd/amlogic/ini/ini_config.h b/cmd/amlogic/ini/ini_config.h
new file mode 100644
index 0000000..4ed4a2d
--- /dev/null
+++ b/cmd/amlogic/ini/ini_config.h
@@ -0,0 +1,42 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __INI_CONFIG_H__
+#define __INI_CONFIG_H__
+
+#if (!defined(CC_COMPILE_IN_PC) && !defined(CC_COMPILE_IN_ANDROID))
+ #define CC_COMPILE_IN_UBOOT
+ #define CC_INI_IO_USE_UNIFY_KEY
+#endif
+
+#if (defined CC_COMPILE_IN_PC)
+ #define CC_UBOOT_RW_SIMULATE
+#endif
+
+#if (defined CC_COMPILE_IN_PC || defined CC_COMPILE_IN_ANDROID)
+ #include <stdio.h>
+ #include <stdlib.h>
+ #include <string.h>
+ #include <ctype.h>
+ #include <errno.h>
+ #include <fcntl.h>
+ #include <unistd.h>
+ #include <sys/stat.h>
+#elif (defined CC_COMPILE_IN_UBOOT)
+ #include <common.h>
+ #include <command.h>
+ #include <environment.h>
+ #include <linux/ctype.h>
+ #include <linux/string.h>
+ #include <malloc.h>
+ #include <amlogic/keyunify.h>
+ #include <ext4fs.h>
+ #include <linux/stat.h>
+ #include <malloc.h>
+ #include <fs.h>
+ #include <emmc_partitions.h>
+#endif
+
+#endif //__INI_CONFIG_H__
diff --git a/cmd/amlogic/ini/ini_core.c b/cmd/amlogic/ini/ini_core.c
new file mode 100644
index 0000000..8d04025
--- /dev/null
+++ b/cmd/amlogic/ini/ini_core.c
@@ -0,0 +1,272 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "ini_config.h"
+#include "ini_core.h"
+#include "ini_size_define.h"
+
+/* Strip whitespace chars off end of given string, in place. Return s. */
+static char* rstrip(char* s) {
+ char* p = s + strlen(s);
+ while (p > s && isspace((unsigned char) (*--p)))
+ *p = '\0';
+ return s;
+}
+
+/* Return pointer to first non-whitespace char in given string. */
+static char* lskip(const char* s) {
+ while (*s && isspace((unsigned char) (*s)))
+ s++;
+ return (char*) s;
+}
+
+/* Return pointer to first char c or ';' comment in given string, or pointer to
+ null at end of string if neither found. ';' must be prefixed by a whitespace
+ character to register as a comment. */
+static char* find_char_or_comment(const char* s, char c) {
+ int was_whitespace = 0;
+ while (*s && *s != c && !(was_whitespace && *s == ';')) {
+ was_whitespace = isspace((unsigned char) (*s));
+ s++;
+ }
+ return (char*) s;
+}
+
+/* Version of strncpy that ensures dest (size bytes) is null-terminated. */
+static char* strncpy0(char* dest, const char* src, size_t size) {
+ strncpy(dest, src, size);
+ dest[size - 1] = '\0';
+ return dest;
+}
+
+#if (defined CC_COMPILE_IN_PC || defined CC_COMPILE_IN_ANDROID)
+/* See documentation in header file. */
+int ini_parse_file(FILE* file,
+ int (*handler)(void*, const char*, const char*, const char*),
+ void* user) {
+ /* Uses a fair bit of stack (use heap instead if you need to) */
+#if INI_USE_STACK
+ char line[INI_MAX_LINE];
+#else
+ char* line;
+#endif
+ char section[MAX_SECTION] = "";
+ char prev_name[MAX_NAME] = "";
+
+ char* start;
+ char* end;
+ char* name;
+ char* value;
+ int lineno = 0;
+ int error = 0;
+
+#if !INI_USE_STACK
+ line = (char*) malloc(INI_MAX_LINE);
+ if (!line) {
+ return -2;
+ }
+#endif
+
+ /* Scan through file line by line */
+ while (fgets(line, INI_MAX_LINE, file) != NULL) {
+ lineno++;
+
+ start = line;
+#if INI_ALLOW_BOM
+ if (lineno == 1 && (unsigned char)start[0] == 0xEF &&
+ (unsigned char)start[1] == 0xBB &&
+ (unsigned char)start[2] == 0xBF) {
+ start += 3;
+ }
+#endif
+ start = lskip(rstrip(start));
+
+ if (*start == ';' || *start == '#') {
+ /* Per Python ConfigParser, allow '#' comments at start of line */
+ }
+ else if (*start == '[') {
+ /* A "[section]" line */
+ end = find_char_or_comment(start + 1, ']');
+ if (*end == ']') {
+ *end = '\0';
+ strncpy0(section, start + 1, sizeof(section));
+ *prev_name = '\0';
+ } else if (!error) {
+ /* No ']' found on section line */
+ error = lineno;
+ }
+ }
+#if INI_ALLOW_MULTILINE
+ else if (*prev_name && *start && (start > line || strstr(start, "=") == NULL)) {
+ /* Non-black line with leading whitespace, treat as continuation
+ of previous name's value (as per Python ConfigParser). */
+ if (!handler(user, section, prev_name, start) && !error)
+ error = lineno;
+ }
+#endif
+ else if (*start && *start != ';') {
+ /* Not a comment, must be a name[=:]value pair */
+ end = find_char_or_comment(start, '=');
+ if (*end != '=') {
+ end = find_char_or_comment(start, ':');
+ }
+ if (*end == '=' || *end == ':') {
+ *end = '\0';
+ name = rstrip(start);
+ value = lskip(end + 1);
+ end = find_char_or_comment(value, '\0');
+ if (*end == ';')
+ *end = '\0';
+ rstrip(value);
+
+ /* Valid name[=:]value pair found, call handler */
+ strncpy0(prev_name, name, sizeof(prev_name));
+ if (!handler(user, section, name, value) && !error)
+ error = lineno;
+ } else if (!error) {
+ /* No '=' or ':' found on name[=:]value line */
+ error = lineno;
+ }
+ }
+ }
+
+#if !INI_USE_STACK
+ free(line);
+#endif
+
+ return error;
+}
+#endif
+
+int ini_parse_mem(const char* buf,
+ int (*handler)(void* user, const char* section, const char* name,
+ const char* value), void* user) {
+ char* bufptr = (char*) buf;
+
+ /* Uses a fair bit of stack (use heap instead if you need to) */
+#if INI_USE_STACK
+ char line[INI_MAX_LINE];
+#else
+ char* line;
+#endif
+ char section[MAX_SECTION] = "";
+ char prev_name[MAX_NAME] = "";
+
+ char* start;
+ char* end;
+ char* name;
+ char* value;
+ int lineno = 0;
+ int error = 0;
+
+#if !INI_USE_STACK
+ line = (char*) malloc(INI_MAX_LINE);
+ if (!line) {
+ return -2;
+ }
+#endif
+
+ while (1) {
+ int ncount = 0;
+ while (*bufptr != '\0') {
+ if (*bufptr == '\r' || *bufptr == '\n')
+ break;
+
+ line[ncount] = *bufptr++;
+ ncount++;
+ }
+ while (*bufptr == '\r' || *bufptr == '\n')
+ bufptr++;
+ line[ncount] = 0;
+
+ if (ncount == 0)
+ break;
+
+ /* Scan through file line by line */
+ //while (fgets(line, INI_MAX_LINE, file) != NULL) {
+ lineno++;
+
+ start = line;
+#if INI_ALLOW_BOM
+ if (lineno == 1 && (unsigned char)start[0] == 0xEF &&
+ (unsigned char)start[1] == 0xBB &&
+ (unsigned char)start[2] == 0xBF) {
+ start += 3;
+ }
+#endif
+ start = lskip(rstrip(start));
+
+ if (*start == ';' || *start == '#') {
+ /* Per Python ConfigParser, allow '#' comments at start of line */
+ }
+ else if (*start == '[') {
+ /* A "[section]" line */
+ end = find_char_or_comment(start + 1, ']');
+ if (*end == ']') {
+ *end = '\0';
+ strncpy0(section, start + 1, sizeof(section));
+ *prev_name = '\0';
+ } else if (!error) {
+ /* No ']' found on section line */
+ error = lineno;
+ }
+ }
+#if INI_ALLOW_MULTILINE
+ else if (*prev_name && *start && (start > line || strstr(start, "=") == NULL)) {
+ /* Non-black line with leading whitespace, treat as continuation
+ of previous name's value (as per Python ConfigParser). */
+ if (!handler(user, section, prev_name, start) && !error)
+ error = lineno;
+ }
+#endif
+ else if (*start && *start != ';') {
+ /* Not a comment, must be a name[=:]value pair */
+ end = find_char_or_comment(start, '=');
+ if (*end != '=') {
+ end = find_char_or_comment(start, ':');
+ }
+ if (*end == '=' || *end == ':') {
+ *end = '\0';
+ name = rstrip(start);
+ value = lskip(end + 1);
+ end = find_char_or_comment(value, '\0');
+ if (*end == ';')
+ *end = '\0';
+ rstrip(value);
+
+ /* Valid name[=:]value pair found, call handler */
+ strncpy0(prev_name, name, sizeof(prev_name));
+ if (!handler(user, section, name, value) && !error)
+ error = lineno;
+ } else if (!error) {
+ /* No '=' or ':' found on name[=:]value line */
+ error = lineno;
+ }
+ }
+ }
+
+#if !INI_USE_STACK
+ free(line);
+#endif
+
+ return error;
+}
+
+#if (defined CC_COMPILE_IN_PC || defined CC_COMPILE_IN_ANDROID)
+/* See documentation in header file. */
+int ini_parse(const char* filename,
+ int (*handler)(void*, const char*, const char*, const char*),
+ void* user) {
+ FILE* file;
+ int error;
+
+ file = fopen(filename, "r");
+ if (!file)
+ return -1;
+ error = ini_parse_file(file, handler, user);
+ fclose(file);
+ return error;
+}
+#endif
diff --git a/cmd/amlogic/ini/ini_core.h b/cmd/amlogic/ini/ini_core.h
new file mode 100644
index 0000000..0fb268a
--- /dev/null
+++ b/cmd/amlogic/ini/ini_core.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __INI_CORE_H__
+#define __INI_CORE_H__
+
+/* Make this header file easier to include in C++ code */
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if (defined CC_COMPILE_IN_PC || defined CC_COMPILE_IN_ANDROID)
+
+#include <stdio.h>
+
+/* Parse given INI-style file. May have [section]s, name=value pairs
+ (whitespace stripped), and comments starting with ';' (semicolon). Section
+ is "" if name=value pair parsed before any section heading. name:value
+ pairs are also supported as a concession to Python's ConfigParser.
+
+ For each name=value pair parsed, call handler function with given user
+ pointer as well as section, name, and value (data only valid for duration
+ of handler call). Handler should return nonzero on success, zero on error.
+
+ Returns 0 on success, line number of first error on parse error (doesn't
+ stop on first error), -1 on file open error, or -2 on memory allocation
+ error (only when INI_USE_STACK is zero).
+ */
+int ini_parse(const char* filename,
+ int (*handler)(void* user, const char* section, const char* name,
+ const char* value), void* user);
+
+/* Same as ini_parse(), but takes a FILE* instead of filename. This doesn't
+ close the file when it's finished -- the caller must do that. */
+int ini_parse_file(FILE* file,
+ int (*handler)(void* user, const char* section, const char* name,
+ const char* value), void* user);
+#endif
+
+int ini_parse_mem(const char* buf,
+ int (*handler)(void* user, const char* section, const char* name,
+ const char* value), void* user);
+
+/* Nonzero to allow multi-line value parsing, in the style of Python's
+ ConfigParser. If allowed, ini_parse() will call the handler with the same
+ name for each subsequent line parsed. */
+#ifndef INI_ALLOW_MULTILINE
+#define INI_ALLOW_MULTILINE 1
+#endif
+
+/* Nonzero to allow a UTF-8 BOM sequence (0xEF 0xBB 0xBF) at the start of
+ the file. See http://code.google.com/p/inih/issues/detail?id=21 */
+#ifndef INI_ALLOW_BOM
+#define INI_ALLOW_BOM 1
+#endif
+
+/* Nonzero to use stack, zero to use heap (malloc/free). */
+#ifndef INI_USE_STACK
+#define INI_USE_STACK 1
+#endif
+
+/* Maximum line length for any line in INI file. */
+#ifndef INI_MAX_LINE
+#define INI_MAX_LINE 10000
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __INI_CORE_H__ */
diff --git a/cmd/amlogic/ini/ini_handler.c b/cmd/amlogic/ini/ini_handler.c
new file mode 100644
index 0000000..ae22e65
--- /dev/null
+++ b/cmd/amlogic/ini/ini_handler.c
@@ -0,0 +1,490 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "ini_config.h"
+
+#define LOG_TAG "ini_handler"
+#define LOG_NDEBUG 0
+
+#include "ini_log.h"
+
+#include "ini_core.h"
+#include "ini_handler.h"
+#include "ini_platform.h"
+
+static void trim(char *str, char ch);
+static void trim_all(char *str);
+static INI_SECTION* getSection(const char* section, INI_HANDLER_DATA *pHandlerData);
+static INI_LINE* getKeyLineAtSec(INI_SECTION* pSec, const char* key);
+static int setKeyValue(void* user, const char* section, const char* name, const char* value, int set_mode);
+static int handler(void* user, const char* section, const char* name, const char* value);
+static INI_LINE* newLine(const char* name, const char* value);
+static INI_SECTION* newSection(const char* section, INI_LINE* pLINE);
+
+#if CC_MEMORY_ALLOC_FREE_TRACE == 1
+static void alloc_mem(const char *fun_name, const char *var_name, void *ptr);
+static void free_mem(const char *fun_name, const char *var_name, void *ptr);
+static void printAllocMemND(const char *fun_name);
+static void printFreeMemND(const char *fun_name);
+static void clearMemND(void);
+#endif
+
+int bin_file_read(const char* filename, unsigned char *file_buf) {
+ int tmp_ret = -1, rd_cnt = 0, file_size = 0;
+ unsigned char *tmp_buf = NULL;
+
+ if (!iniIsFileExist(filename)) {
+ ALOGE("%s, file \"%s\" is not exist!\n", __FUNCTION__, filename);
+ return -1;
+ }
+
+ file_size = iniGetFileSize(filename);
+ if (file_size <= 0) {
+ ALOGE("%s, file \"%s\" size error!\n", __FUNCTION__, filename);
+ return -1;
+ }
+
+ tmp_buf = (unsigned char *) malloc(file_size * 2);
+ if (tmp_buf != NULL) {
+ rd_cnt = iniReadFileToBuffer(filename, 0, file_size, tmp_buf);
+ if (rd_cnt > 0) {
+ if (file_size > CC_MAX_INI_FILE_SIZE) {
+ ALOGE("%s: file \"%s\" size out of support!\n", __FUNCTION__, filename);
+ tmp_ret = -1;
+ } else {
+ memcpy(file_buf, tmp_buf, file_size);
+ tmp_ret = file_size;
+ }
+ }
+
+ free(tmp_buf);
+ tmp_buf = NULL;
+ }
+
+ return tmp_ret;
+}
+
+int ini_file_parse(const char* filename, INI_HANDLER_DATA *pHandlerData) {
+ int tmp_ret = -1, rd_cnt = 0, file_size = 0;
+ unsigned char *tmp_buf = NULL;
+
+ if (!iniIsFileExist(filename)) {
+ ALOGE("%s, file \"%s\" is not exist!\n", __FUNCTION__, filename);
+ return -1;
+ }
+
+ file_size = iniGetFileSize(filename);
+ if (file_size <= 0) {
+ ALOGE("%s, file \"%s\" size error!\n", __FUNCTION__, filename);
+ return -1;
+ }
+
+ tmp_buf = (unsigned char *) malloc(file_size * 2);
+ if (tmp_buf != NULL) {
+ strncpy(pHandlerData->mpFileName, filename, CC_MAX_INI_FILE_NAME_LEN - 1);
+
+ memset((void *)tmp_buf, '\0', (file_size * 2) * sizeof(char));
+ rd_cnt = iniReadFileToBuffer(filename, 0, file_size, tmp_buf);
+ if (rd_cnt > 0) {
+ tmp_ret = ini_mem_parse(tmp_buf, pHandlerData);
+ }
+
+ free(tmp_buf);
+ tmp_buf = NULL;
+ }
+
+ return tmp_ret;
+}
+
+int ini_mem_parse(unsigned char* file_buf, INI_HANDLER_DATA *pHandlerData) {
+ //ALOGD("%s, entering...\n", __FUNCTION__);
+ return ini_parse_mem((char *)file_buf, handler, (void *)pHandlerData);
+}
+
+int ini_set_save_file_name(const char* filename, INI_HANDLER_DATA *pHandlerData) {
+ //ALOGD("%s, entering...\n", __FUNCTION__);
+
+ strncpy(pHandlerData->mpFileName, filename, CC_MAX_INI_FILE_NAME_LEN - 1);
+ return 0;
+}
+
+void ini_free_mem(INI_HANDLER_DATA *pHandlerData) {
+ //ALOGD("%s, entering...\n", __FUNCTION__);
+
+ INI_SECTION* pNextSec = NULL;
+ INI_SECTION* pSec = NULL;
+ for (pSec = pHandlerData->mpFirstSection; pSec != NULL;) {
+ pNextSec = pSec->pNext;
+
+ INI_LINE* pNextLine = NULL;
+ INI_LINE* pLine = NULL;
+ for (pLine = pSec->pLine; pLine != NULL;) {
+ pNextLine = pLine->pNext;
+
+ if (pLine != NULL) {
+#if CC_MEMORY_ALLOC_FREE_TRACE == 1
+ free_mem(__FUNCTION__, "pLine", pLine);
+#endif
+
+ free(pLine);
+ pLine = NULL;
+ }
+
+ pLine = pNextLine;
+ }
+
+ if (pSec != NULL) {
+#if CC_MEMORY_ALLOC_FREE_TRACE == 1
+ free_mem(__FUNCTION__, "pSec", pSec);
+#endif
+
+ free(pSec);
+ pSec = NULL;
+ }
+
+ pSec = pNextSec;
+ }
+
+ pHandlerData->mpFirstSection = NULL;
+ pHandlerData->mpCurSection = NULL;
+
+#if CC_MEMORY_ALLOC_FREE_TRACE == 1
+ printAllocMemND(__FUNCTION__);
+ printFreeMemND(__FUNCTION__);
+ clearMemND();
+#endif
+}
+
+static void trim(char *str, char ch) {
+ char* pStr;
+
+ pStr = str;
+ while (*pStr != '\0') {
+ if (*pStr == ch) {
+ char* pTmp = pStr;
+ while (*pTmp != '\0') {
+ *pTmp = *(pTmp + 1);
+ pTmp++;
+ }
+ } else {
+ pStr++;
+ }
+ }
+}
+
+static void trim_all(char *str) {
+ char* pStr = NULL;
+
+ pStr = strchr(str, '\n');
+ if (pStr != NULL) {
+ *pStr = 0;
+ }
+
+ int Len = strlen(str);
+ if (Len > 0) {
+ if (str[Len - 1] == '\r') {
+ str[Len - 1] = '\0';
+ }
+ }
+
+ pStr = strchr(str, '#');
+ if (pStr != NULL) {
+ *pStr = 0;
+ }
+
+ pStr = strchr(str, ';');
+ if (pStr != NULL) {
+ *pStr = 0;
+ }
+
+ trim(str, ' ');
+ trim(str, '{');
+ trim(str, '\\');
+ trim(str, '}');
+ trim(str, '\"');
+ return;
+}
+
+void ini_print_all(INI_HANDLER_DATA *pHandlerData) {
+ INI_SECTION* pSec = NULL;
+ for (pSec = pHandlerData->mpFirstSection; pSec != NULL; pSec = pSec->pNext) {
+ ALOGD("[%s]\n", pSec->Name);
+ INI_LINE* pLine = NULL;
+ for (pLine = pSec->pLine; pLine != NULL; pLine = pLine->pNext) {
+ ALOGD("%s = %s\n", pLine->Name, pLine->Value);
+ }
+ ALOGD("\n\n\n");
+ }
+}
+
+void ini_list_section(INI_HANDLER_DATA *pHandlerData) {
+ INI_SECTION* pSec = NULL;
+ for (pSec = pHandlerData->mpFirstSection; pSec != NULL; pSec = pSec->pNext) {
+ printf(" %s\n", pSec->Name);
+ }
+}
+
+static INI_SECTION* getSection(const char* section, INI_HANDLER_DATA *pHandlerData) {
+ INI_SECTION* pSec = NULL;
+ for (pSec = pHandlerData->mpFirstSection; pSec != NULL; pSec = pSec->pNext) {
+ if (strncmp(pSec->Name, section, strlen(section)) == 0) {
+ return pSec;
+ }
+ }
+
+ return NULL;
+}
+
+static INI_LINE* getKeyLineAtSec(INI_SECTION* pSec, const char* key) {
+ INI_LINE* pLine = NULL;
+ for (pLine = pSec->pLine; pLine != NULL; pLine = pLine->pNext) {
+ if (strncmp(pLine->Name, key, strlen(key)) == 0) {
+ return pLine;
+ }
+ }
+ return NULL;
+}
+
+const char* ini_get_string(const char* section, const char* key,
+ const char* def_value, INI_HANDLER_DATA *pHandlerData) {
+ INI_SECTION* pSec = getSection(section, pHandlerData);
+ if (pSec == NULL) {
+ //ALOGD("%s, section %s is NULL\n", __FUNCTION__, section);
+ return def_value;
+ }
+
+ INI_LINE* pLine = getKeyLineAtSec(pSec, key);
+ if (pLine == NULL) {
+ //ALOGD("%s, key \"%s\" is NULL\n", __FUNCTION__, key);
+ return def_value;
+ }
+
+ return pLine->Value;
+}
+
+int ini_set_string(const char *section, const char *key, const char *value, INI_HANDLER_DATA *pHandlerData) {
+ setKeyValue(pHandlerData, section, key, value, 1);
+ return 0;
+}
+
+int ini_save_to_file(const char *filename, INI_HANDLER_DATA *pHandlerData) {
+#if (defined CC_COMPILE_IN_PC || defined CC_COMPILE_IN_ANDROID)
+ const char *fname = NULL;
+ FILE *fp = NULL;
+
+ if (filename == NULL) {
+ if (strlen(pHandlerData->mpFileName) == 0) {
+ ALOGE("%s, save file name is NULL!!!\n", __FUNCTION__);
+ return -1;
+ } else {
+ fname = pHandlerData->mpFileName;
+ }
+ } else {
+ fname = filename;
+ }
+
+ if ((fp = fopen (fname, "wb")) == NULL) {
+ ALOGE("%s, Open file \"%s\" ERROR (%s)!!!\n", __FUNCTION__, fname, strerror(errno));
+ return -1;
+ }
+
+ INI_SECTION* pSec = NULL;
+ for (pSec = pHandlerData->mpFirstSection; pSec != NULL; pSec = pSec->pNext) {
+ fprintf(fp, "[%s]\r\n", pSec->Name);
+ INI_LINE* pLine = NULL;
+ for (pLine = pSec->pLine; pLine != NULL; pLine = pLine->pNext) {
+ fprintf(fp, "%s = %s\r\n", pLine->Name, pLine->Value);
+ }
+ }
+
+ fflush(fp);
+ fsync(fileno(fp));
+
+ fclose(fp);
+ fp = NULL;
+
+ return 0;
+#elif (defined CC_COMPILE_IN_UBOOT)
+ return 0;
+#endif
+}
+
+static INI_LINE* newLine(const char* name, const char* value) {
+ INI_LINE* pLine = NULL;
+
+ pLine = (INI_LINE*) malloc(sizeof(INI_LINE));
+ if (pLine != NULL) {
+ pLine->pNext = NULL;
+ strncpy(pLine->Name, name, sizeof(pLine->Name) - 1);
+ pLine->Name[sizeof(pLine->Name) - 1] = '\0';
+ strncpy(pLine->Value, value, sizeof(pLine->Value) - 1);
+ pLine->Value[sizeof(pLine->Value) - 1] = '\0';
+
+#if CC_MEMORY_ALLOC_FREE_TRACE == 1
+ alloc_mem(__FUNCTION__, "pLine", pLine);
+#endif
+ }
+
+ return pLine;
+}
+
+static INI_SECTION* newSection(const char* section, INI_LINE* pLine) {
+ INI_SECTION* pSec = NULL;
+
+ pSec = (INI_SECTION*) malloc(sizeof(INI_SECTION));
+ if (pSec != NULL) {
+ pSec->pLine = pLine;
+ pSec->pNext = NULL;
+ strncpy(pSec->Name, section, sizeof(pSec->Name) - 1);
+ pSec->Name[sizeof(pSec->Name) - 1] = '\0';
+
+#if CC_MEMORY_ALLOC_FREE_TRACE == 1
+ alloc_mem(__FUNCTION__, "pSec", pSec);
+#endif
+ }
+
+ return pSec;
+}
+
+static int setKeyValue(void* user, const char* section, const char* key, const char* value, int set_mode) {
+ INI_LINE* pLine = NULL;
+ INI_SECTION *pSec = NULL;
+ INI_HANDLER_DATA *pHandlerData = (INI_HANDLER_DATA *) user;
+
+ if (section == NULL || key == NULL || value == NULL) {
+ return 1;
+ }
+
+ trim_all((char *) value);
+ if (value[0] == '\0') {
+ return 1;
+ }
+
+ if (strlen(key) > CC_MAX_INI_LINE_NAME_LEN) {
+ ALOGE("key name is too long, limit %d.\n", CC_MAX_INI_LINE_NAME_LEN);
+ return 1;
+ }
+ if (strlen(value) > CC_MAX_INI_FILE_LINE_LEN) {
+ ALOGE("key name is too long, limit %d.\n", CC_MAX_INI_FILE_LINE_LEN);
+ return 1;
+ }
+
+ if (pHandlerData->mpFirstSection == NULL) {
+ pLine = newLine(key, value);
+ pSec = newSection(section, pLine);
+
+ pHandlerData->mpFirstSection = pSec;
+ pHandlerData->mpCurSection = pSec;
+ pSec->pCurLine = pLine;
+ } else {
+ pSec = getSection(section, pHandlerData);
+ if (pSec == NULL) {
+ pLine = newLine(key, value);
+ pSec = newSection(section, pLine);
+
+ pHandlerData->mpCurSection->pNext = pSec;
+ pHandlerData->mpCurSection = pSec;
+ pSec->pCurLine = pLine;
+
+ pSec->pCurLine = pLine;
+ } else {
+ pLine = getKeyLineAtSec(pSec, key);
+ if (pLine == NULL) {
+ pLine = newLine(key, value);
+
+ pSec->pCurLine->pNext = pLine;
+ pSec->pCurLine = pLine;
+ } else {
+ if (set_mode == 1) {
+ strcpy(pLine->Value, value);
+ } else {
+ strcat(pLine->Value, value);
+ }
+ }
+ }
+ }
+
+ return 0;
+}
+
+static int handler(void* user, const char* section, const char* name,
+ const char* value) {
+ //ALOGD("%s, section = %s, name = %s, value = %s\n", __FUNCTION__, section, name, value);
+ setKeyValue(user, section, name, value, 0);
+ return 1;
+}
+
+#if CC_MEMORY_ALLOC_FREE_TRACE == 1
+
+#define CC_MEM_RECORD_CNT (1024)
+
+typedef struct tag_memnd {
+ char fun_name[50];
+ char var_name[50];
+ void *ptr;
+} memnd;
+
+static memnd gMemAllocItems[CC_MEM_RECORD_CNT];
+static int gMemAllocInd = 0;
+
+static memnd gMemFreeItems[CC_MEM_RECORD_CNT];
+static int gMemFreeInd = 0;
+
+static void alloc_mem(const char *fun_name, const char *var_name, void *ptr) {
+ strncpy(gMemAllocItems[gMemAllocInd].fun_name, fun_name,
+ sizeof(gMemAllocItems[gMemAllocInd].fun_name) - 1);
+ gMemAllocItems[gMemAllocInd].fun_name[sizeof(gMemAllocItems[gMemAllocInd].fun_name) - 1]
+ = '\0';
+ strncpy(gMemAllocItems[gMemAllocInd].var_name, var_name,
+ sizeof(gMemAllocItems[gMemAllocInd].var_name) - 1);
+ gMemAllocItems[gMemAllocInd].var_name[sizeof(gMemAllocItems[gMemAllocInd].var_name) - 1]
+ = '\0';
+ gMemAllocItems[gMemAllocInd].ptr = ptr;
+
+ gMemAllocInd += 1;
+}
+
+static void free_mem(const char *fun_name, const char *var_name, void *ptr) {
+ strncpy(gMemFreeItems[gMemFreeInd].fun_name, fun_name,
+ sizeof(gMemFreeItems[gMemFreeInd].fun_name) - 1);
+ gMemFreeItems[gMemFreeInd].fun_name[sizeof(gMemFreeItems[gMemFreeInd].fun_name) - 1]
+ = '\0';
+ strncpy(gMemFreeItems[gMemFreeInd].var_name, var_name,
+ sizeof(gMemFreeItems[gMemFreeInd].var_name) - 1);
+ gMemFreeItems[gMemFreeInd].var_name[sizeof(gMemFreeItems[gMemFreeInd].var_name) - 1]
+ = '\0';
+
+ gMemFreeItems[gMemFreeInd].ptr = ptr;
+
+ gMemFreeInd += 1;
+}
+
+static void printMemND(const char *fun_name, memnd *tmp_nd, int tmp_cnt) {
+#if CC_MEMORY_ALLOC_FREE_TRACE_PRINT_ALL == 1
+ int i = 0;
+
+ ALOGD("fun_name = %s, total_cnt = %d\n", fun_name, tmp_cnt);
+
+ for (i = 0; i < tmp_cnt; i++) {
+ ALOGD("fun_name = %s, var_name = %s, ptr = %p\n", tmp_nd[i].fun_name, tmp_nd[i].var_name, tmp_nd[i].ptr);
+ }
+#endif
+}
+
+static void printFreeMemND(const char *fun_name) {
+ printMemND(__FUNCTION__, gMemFreeItems, gMemFreeInd);
+}
+
+static void printAllocMemND(const char *fun_name) {
+ printMemND(__FUNCTION__, gMemAllocItems, gMemAllocInd);
+}
+
+static void clearMemND(void) {
+ gMemAllocInd = 0;
+ gMemFreeInd = 0;
+ memset((void *)gMemAllocItems, 0, sizeof(memnd) * CC_MEM_RECORD_CNT);
+ memset((void *)gMemFreeItems, 0, sizeof(memnd) * CC_MEM_RECORD_CNT);
+}
+#endif
diff --git a/cmd/amlogic/ini/ini_handler.h b/cmd/amlogic/ini/ini_handler.h
new file mode 100644
index 0000000..0e29331
--- /dev/null
+++ b/cmd/amlogic/ini/ini_handler.h
@@ -0,0 +1,54 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __INI_HANDLER_H__
+#define __INI_HANDLER_H__
+#include "ini_size_define.h"
+
+typedef struct S_INI_LINE {
+ struct S_INI_LINE *pNext;
+ char Name[CC_MAX_INI_LINE_NAME_LEN];
+ char Value[CC_MAX_INI_FILE_LINE_LEN];
+} INI_LINE;
+
+typedef struct S_INI_SECTION {
+ INI_LINE* pLine;
+ INI_LINE* pCurLine;
+ struct S_INI_SECTION *pNext;
+ char Name[CC_MAX_INI_LINE_NAME_LEN];
+} INI_SECTION;
+
+typedef struct S_INI_HANDLER_DATA {
+ INI_SECTION* mpFirstSection;
+ INI_SECTION* mpCurSection;
+ char mpFileName[CC_MAX_INI_FILE_NAME_LEN];
+ void *data;
+} INI_HANDLER_DATA;
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int bin_file_read(const char* filename, unsigned char *file_buf);
+
+int ini_file_parse(const char* filename, INI_HANDLER_DATA *pHandlerData);
+int ini_mem_parse(unsigned char* file_buf, INI_HANDLER_DATA *pHandlerData);
+int ini_set_save_file_name(const char* filename, INI_HANDLER_DATA *pHandlerData);
+void ini_free_mem(INI_HANDLER_DATA *pHandlerData);
+void ini_print_all(INI_HANDLER_DATA *pHandlerData);
+void ini_list_section(INI_HANDLER_DATA *pHandlerData);
+const char* ini_get_string(const char* section, const char* key, const char* def_value, INI_HANDLER_DATA *pHandlerData);
+int ini_set_string(const char *section, const char *key, const char *value, INI_HANDLER_DATA *pHandlerData);
+int ini_save_to_file(const char *filename, INI_HANDLER_DATA *pHandlerData);
+
+#ifdef __cplusplus
+}
+#endif
+
+//for memory malloc & free debug
+//#define CC_MEMORY_ALLOC_FREE_TRACE (1) //remove for it will cause memory issue
+#define CC_MEMORY_ALLOC_FREE_TRACE_PRINT_ALL (0)
+
+#endif //__INI_HANDLER_H__
diff --git a/cmd/amlogic/ini/ini_io.c b/cmd/amlogic/ini/ini_io.c
new file mode 100644
index 0000000..351d019
--- /dev/null
+++ b/cmd/amlogic/ini/ini_io.c
@@ -0,0 +1,493 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "ini_config.h"
+
+#define LOG_TAG "ini_io"
+#define LOG_NDEBUG 0
+
+#include "ini_log.h"
+#include "ini_platform.h"
+#include "ini_io.h"
+
+#if (defined (CC_INI_IO_USE_UNIFY_KEY))
+ #if (!defined (CC_INI_IO_UKEY_USE_OTHER_MODULE))
+ #include "UnifyKey.h"
+
+ #define HanldeReadData readUKeyData
+ #define HandleWriteData writeUKeyData
+ #else
+ #include <tvutils/tvutils.h>
+
+ #define HanldeReadData readUnifyKeyData
+ #define HandleWriteData writeUnifyKeyData
+ #endif
+#endif
+
+static int ReadBinData(const char *item_name, unsigned char data_buf[]) {
+ return readUKeyData_no_header(item_name, data_buf, CC_ONE_SECTION_SIZE);
+}
+
+static int WriteBinData(const char *item_name, int wr_size, unsigned char data_buf[]) {
+ return HandleWriteData(item_name, data_buf, wr_size);
+}
+
+static int ReadIniData(const char *item_name, unsigned char data_buf[]) {
+ return HanldeReadData(item_name, data_buf, CC_ONE_SECTION_SIZE);
+}
+
+static int WriteIniData(const char *item_name, int wr_size, unsigned char data_buf[]) {
+ return HandleWriteData(item_name, data_buf, wr_size);
+}
+
+static int ReadStringData(const char *item_name, int mode, char data_buf[]) {
+ int rd_size = 0, skip_len = 0;
+ unsigned char *tmp_buf = NULL;
+
+ if (data_buf == NULL) {
+ return -1;
+ }
+
+ tmp_buf = (unsigned char *) malloc(CC_MAX_DATA_SIZE);
+ if (tmp_buf == NULL) {
+ ALOGE("%s, malloc buffer memory error!!!\n", __FUNCTION__);
+ return -1;
+ }
+
+ memset((void *)tmp_buf, 0, CC_MAX_DATA_SIZE);
+ rd_size = ReadIniData(item_name, tmp_buf);
+ if (check_string_data_have_header_valid(NULL, (char *)tmp_buf, CC_HEAD_CHKSUM_LEN, CC_VERSION_LEN) < 0) {
+ data_buf[0] = '\0';
+
+ free(tmp_buf);
+ tmp_buf = NULL;
+ return 0;
+ }
+
+ if (mode == 0) {
+ skip_len = CC_HEAD_CHKSUM_LEN + CC_VERSION_LEN;
+ } else {
+ skip_len = 0;
+ }
+
+ strncpy(data_buf, (char *)tmp_buf + skip_len, rd_size - skip_len);
+
+ free(tmp_buf);
+ tmp_buf = NULL;
+
+ return rd_size;
+}
+
+static int SaveStringData(const char *item_name, int mode, char data_buf[]) {
+ int tmp_ret = 0, data_len = 0;
+ unsigned int tmp_crc32 = 0;
+ char *buf_ptr = NULL;
+ char *tmp_buf = NULL;
+ char *tmp_ch_buf = NULL;
+
+ if (data_buf == NULL) {
+ return -1;
+ }
+
+ tmp_buf = (char *) malloc(CC_MAX_DATA_SIZE);
+ if (tmp_buf == NULL) {
+ ALOGE("%s, malloc buffer memory error!!!\n", __FUNCTION__);
+ return -1;
+ }
+
+ tmp_ch_buf = (char *) malloc(CC_MAX_DATA_SIZE);
+ if (tmp_ch_buf == NULL) {
+ free(tmp_buf);
+ tmp_buf = NULL;
+
+ ALOGE("%s, malloc buffer memory error!!!\n", __FUNCTION__);
+ return -1;
+ }
+
+ memset((void *)tmp_buf, 0, CC_MAX_DATA_SIZE);
+
+ if (mode == 0) {
+ strcpy(tmp_ch_buf, "V001,");
+ strcat(tmp_ch_buf, data_buf);
+
+ buf_ptr = tmp_ch_buf;
+ } else {
+ buf_ptr = data_buf;
+ }
+
+ tmp_crc32 = CalCRC32(0, (unsigned char *)buf_ptr, strlen(buf_ptr));
+ sprintf(tmp_buf, "%08x,%s", tmp_crc32, buf_ptr);
+
+ data_len = strlen(tmp_buf) + 1;
+ tmp_ret = WriteIniData(item_name, data_len, (unsigned char *)tmp_buf);
+ if (tmp_ret != data_len) {
+ ALOGE("%s, write data error (0x%08X, 0x%08X)\n", __FUNCTION__, tmp_ret, data_len);
+
+ free(tmp_ch_buf);
+ tmp_ch_buf = NULL;
+
+ free(tmp_buf);
+ tmp_buf = NULL;
+
+ return -1;
+ }
+
+ free(tmp_ch_buf);
+ tmp_ch_buf = NULL;
+
+ free(tmp_buf);
+ tmp_buf = NULL;
+
+ return tmp_ret;
+}
+
+int check_hex_data_no_header_valid(unsigned int* tmp_crc32, int max_len, int buf_len, unsigned char data_buf[]) {
+ unsigned int cal_crc32 = 0;
+
+ if (tmp_crc32 != NULL) {
+ *tmp_crc32 = 0;
+ }
+
+ if (buf_len >= max_len) {
+ ALOGE("%s, buf_len error (0x%x, 0x%x)\n", __FUNCTION__, max_len, buf_len);
+ return -1;
+ }
+ //ALOGD("%s, data len ok(0x%x, 0x%x)\n", __FUNCTION__, data_len, buf_len);
+
+ cal_crc32 = CalCRC32(0, data_buf, buf_len);
+
+ if (tmp_crc32 != NULL) {
+ *tmp_crc32 = cal_crc32;
+ }
+
+ return 0;
+}
+
+int check_hex_data_have_header_valid(unsigned int* tmp_crc32, int max_len, int buf_len, unsigned char data_buf[]) {
+ unsigned int rd_crc32 = 0, cal_crc32 = 0;
+ unsigned short data_len = 0;
+
+ if (tmp_crc32 != NULL) {
+ *tmp_crc32 = 0;
+ }
+
+ memcpy((void *)&data_len, (void *)(data_buf + 4), 2);
+ if (data_len < 4 || data_len >= max_len || data_len != buf_len) {
+ ALOGE("%s, rd data len error (0x%x, 0x%x)\n", __FUNCTION__, data_len, buf_len);
+ return -1;
+ }
+ //ALOGD("%s, data len ok(0x%x, 0x%x)\n", __FUNCTION__, data_len, buf_len);
+
+ memcpy((void *)&rd_crc32, (void *)data_buf, 4);
+ cal_crc32 = CalCRC32(0, (data_buf + 4), data_len - 4);
+
+ if (rd_crc32 != cal_crc32) {
+ ALOGE("%s, data invalid (0x%08X, 0x%08X)\n", __FUNCTION__, rd_crc32, cal_crc32);
+ return -1;
+ }
+
+ if (tmp_crc32 != NULL) {
+ *tmp_crc32 = cal_crc32;
+ }
+
+ //ALOGD("%s, data check ok (0x%08X, 0x%08X)\n", __FUNCTION__, rd_crc32, cal_crc32);
+ return 0;
+}
+
+int check_string_data_have_header_valid(unsigned int* tmp_crc32, char *data_str, int chksum_head_len, int ver_len) {
+ int tmp_len = 0, tmp_ver = 0;
+ char *endp = NULL;
+ unsigned long src_chksum = 0, cal_chksum = 0;
+ char tmp_buf[129] = { 0 };
+
+ if (data_str != NULL) {
+ if (tmp_crc32 != NULL) {
+ *tmp_crc32 = 0;
+ }
+
+ tmp_len = strlen(data_str);
+ if (tmp_len > chksum_head_len + ver_len) {
+ cal_chksum = CalCRC32(0, (unsigned char *)(data_str + chksum_head_len), tmp_len - chksum_head_len);
+ memcpy(tmp_buf, data_str, chksum_head_len);
+ tmp_buf[chksum_head_len] = 0;
+ src_chksum = strtoul(tmp_buf, &endp, 16);
+ if (cal_chksum == src_chksum) {
+ memcpy(tmp_buf, data_str + chksum_head_len, ver_len);
+ if ((tmp_buf[0] == 'v' || tmp_buf[0] == 'V') && isxdigit(tmp_buf[1]) && isxdigit(tmp_buf[2]) && isxdigit(tmp_buf[3])) {
+ tmp_ver = strtoul(tmp_buf + 1, &endp, 16);
+ if (tmp_ver <= 0) {
+ ALOGE("%s, data version error!!!\n", __FUNCTION__);
+ return -1;
+ }
+ } else {
+ ALOGD("%s, data version error!!!\n", __FUNCTION__);
+ return -1;
+ }
+
+ if (tmp_crc32 != NULL) {
+ *tmp_crc32 = cal_chksum;
+ }
+ //ALOGD("%s, data check ok\n", __FUNCTION__);
+ return tmp_ver;
+ } else {
+ ALOGD("%s, cal_chksum = %x\n", __FUNCTION__, (unsigned int)cal_chksum);
+ ALOGD("%s, src_chksum = %x\n", __FUNCTION__, (unsigned int)src_chksum);
+ }
+ }
+
+ ALOGE("%s, data error!!!\n", __FUNCTION__);
+ return -1;
+ }
+
+ ALOGE("%s, data is NULL!!!\n", __FUNCTION__);
+ return -1;
+}
+
+int ReadLCDParam(unsigned char data_buf[]) {
+ int rd_size = 0;
+
+ if (data_buf == NULL) {
+ return -1;
+ }
+
+ rd_size = ReadIniData(CS_LCD_ITEM_NAME, data_buf);
+
+ return rd_size;
+}
+
+int SaveLCDParam(int wr_size, unsigned char data_buf[]) {
+ int tmp_ret = 0;
+
+ if (data_buf == NULL) {
+ return -1;
+ }
+
+ tmp_ret = WriteIniData(CS_LCD_ITEM_NAME, wr_size, data_buf);
+ if (tmp_ret != wr_size) {
+ return -1;
+ }
+
+ return tmp_ret;
+}
+
+int ReadLCDExternParam(unsigned char data_buf[]) {
+ int rd_size = 0;
+
+ if (data_buf == NULL) {
+ return -1;
+ }
+
+ rd_size = ReadIniData(CS_LCD_EXT_ITEM_NAME, data_buf);
+
+ return rd_size;
+}
+
+int SaveLCDExternParam(int wr_size, unsigned char data_buf[]) {
+ int tmp_ret = 0;
+
+ if (data_buf == NULL) {
+ return -1;
+ }
+
+ tmp_ret = WriteIniData(CS_LCD_EXT_ITEM_NAME, wr_size, data_buf);
+ if (tmp_ret != wr_size) {
+ return -1;
+ }
+
+ return tmp_ret;
+}
+
+int ReadBackLightParam(unsigned char data_buf[]) {
+ int rd_size = 0;
+
+ if (data_buf == NULL) {
+ return -1;
+ }
+
+ rd_size = ReadIniData(CS_BACKLIGHT_ITEM_NAME, data_buf);
+
+ return rd_size;
+}
+
+int SaveBackLightParam(int wr_size, unsigned char data_buf[]) {
+ int tmp_ret = 0;
+
+ if (data_buf == NULL) {
+ return -1;
+ }
+
+ tmp_ret = WriteIniData(CS_BACKLIGHT_ITEM_NAME, wr_size, data_buf);
+ if (tmp_ret != wr_size) {
+ return -1;
+ }
+
+ return tmp_ret;
+}
+
+int ReadTconSpiParam(unsigned char data_buf[]) {
+ int rd_size = 0;
+
+ if (data_buf == NULL) {
+ return -1;
+ }
+
+ rd_size = ReadIniData(CS_LCD_TCON_SPI_ITEM_NAME, data_buf);
+
+ return rd_size;
+}
+
+int SaveTconSpiParam(int wr_size, unsigned char data_buf[]) {
+ int tmp_ret = 0;
+
+ if (data_buf == NULL) {
+ return -1;
+ }
+
+ tmp_ret = WriteIniData(CS_LCD_TCON_SPI_ITEM_NAME, wr_size, data_buf);
+ if (tmp_ret != wr_size) {
+ return -1;
+ }
+
+ return tmp_ret;
+}
+
+int ReadTconBinParam(unsigned char data_buf[]) {
+ int rd_size = 0;
+
+ if (data_buf == NULL) {
+ return -1;
+ }
+
+ rd_size = ReadBinData(CS_LCD_TCON_ITEM_NAME, data_buf);
+
+ return rd_size;
+}
+
+int SaveTconBinParam(int wr_size, unsigned char data_buf[]) {
+ int tmp_ret = 0;
+
+ if (data_buf == NULL) {
+ return -1;
+ }
+
+ tmp_ret = WriteBinData(CS_LCD_TCON_ITEM_NAME, wr_size, data_buf);
+ if (tmp_ret != wr_size) {
+ return -1;
+ }
+
+ return tmp_ret;
+}
+
+int ReadPanelIniName(char data_buf[]) {
+ return ReadStringData(CS_PANEL_INI_PATH_ITEM_NAME, 0, data_buf);
+}
+
+int SavePanelIniName(char data_buf[]) {
+ return SaveStringData(CS_PANEL_INI_PATH_ITEM_NAME, 0, data_buf);
+}
+
+int ReadPanelPQPath(char data_buf[]) {
+ return ReadStringData(CS_PANEL_PQ_PATH_ITEM_NAME, 0, data_buf);
+}
+
+int SavePanelPQPath(char data_buf[]) {
+ return SaveStringData(CS_PANEL_PQ_PATH_ITEM_NAME, 0, data_buf);
+}
+
+int ReadPanelAllInfoData(unsigned char data_buf[]) {
+ int rd_size = 0;
+
+ if (data_buf == NULL) {
+ return -1;
+ }
+
+ rd_size = ReadIniData(CS_PANEL_ALL_INFO_ITEM_NAME, data_buf);
+
+ return rd_size;
+}
+
+int SavePanelAllInfoData(int wr_size, unsigned char data_buf[]) {
+ int tmp_ret = 0;
+
+ if (data_buf == NULL) {
+ return -1;
+ }
+
+ tmp_ret = WriteIniData(CS_PANEL_ALL_INFO_ITEM_NAME, wr_size, data_buf);
+ if (tmp_ret != wr_size) {
+ return -1;
+ }
+
+ return tmp_ret;
+}
+
+int ReadPanelAllData(int sec_no, unsigned char data_buf[]) {
+ int rd_size = 0;
+ char tmp_buf[128];
+
+ if (data_buf == NULL) {
+ return -1;
+ }
+
+ sprintf(tmp_buf, "%s_d%d", CS_PANEL_ALL_DATA_ITEM_NAME, sec_no);
+
+ rd_size = ReadIniData(tmp_buf, data_buf);
+
+ return rd_size;
+}
+
+int SavePanelAllData(int sec_no, int wr_size, unsigned char data_buf[]) {
+ int tmp_ret = 0;
+ char tmp_buf[128];
+
+ if (data_buf == NULL) {
+ return -1;
+ }
+
+ sprintf(tmp_buf, "%s_d%d", CS_PANEL_ALL_DATA_ITEM_NAME, sec_no);
+
+ tmp_ret = WriteIniData(tmp_buf, wr_size, data_buf);
+ if (tmp_ret != wr_size) {
+ return -1;
+ }
+
+ return tmp_ret;
+}
+
+void PrintDataBuf(int data_cnt, unsigned char data_buf[]) {
+ int i = 0;
+
+ for (i = 0; i < data_cnt; i++) {
+ ALOGD("%s, data_buf[%d] = 0x%02x\n", __FUNCTION__, i, data_buf[i]);
+ }
+
+ ALOGD("%s, \n\n\n\n", __FUNCTION__);
+}
+
+unsigned int CalCRC32(unsigned int crc, const unsigned char *ptr, int buf_len) {
+ static const unsigned int s_crc32[16] = {
+ 0, 0x1db71064, 0x3b6e20c8, 0x26d930ac, 0x76dc4190, 0x6b6b51f4, 0x4db26158, 0x5005713c,
+ 0xedb88320, 0xf00f9344, 0xd6d6a3e8, 0xcb61b38c, 0x9b64c2b0, 0x86d3d2d4, 0xa00ae278, 0xbdbdf21c };
+
+ unsigned int crcu32 = crc;
+ unsigned char b;
+
+ if (buf_len <= 0) {
+ return 0;
+ }
+
+ if (!ptr) {
+ return 0;
+ }
+
+ crcu32 = ~crcu32;
+ while (buf_len--) {
+ b = *ptr++;
+ crcu32 = (crcu32 >> 4) ^ s_crc32[(crcu32 & 0xF) ^ (b & 0xF)];
+ crcu32 = (crcu32 >> 4) ^ s_crc32[(crcu32 & 0xF) ^ (b >> 4)];
+ }
+
+ return ~crcu32;
+}
diff --git a/cmd/amlogic/ini/ini_io.h b/cmd/amlogic/ini/ini_io.h
new file mode 100644
index 0000000..28cb1e6
--- /dev/null
+++ b/cmd/amlogic/ini/ini_io.h
@@ -0,0 +1,56 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __INI_IO_H__
+#define __INI_IO_H__
+#include "ini_size_define.h"
+
+#define CS_LCD_ITEM_NAME "lcd"
+#define CS_LCD_EXT_ITEM_NAME "lcd_extern"
+#define CS_BACKLIGHT_ITEM_NAME "backlight"
+#define CS_LCD_TCON_ITEM_NAME "lcd_tcon"
+#define CS_LCD_TCON_SPI_ITEM_NAME "lcd_tcon_spi"
+#define CS_PANEL_INI_PATH_ITEM_NAME "panel_ini_path"
+#define CS_PANEL_PQ_PATH_ITEM_NAME "panel_pq_path"
+#define CS_PANEL_ALL_INFO_ITEM_NAME "panel_all_info"
+#define CS_PANEL_ALL_DATA_ITEM_NAME "panel_all"
+
+#define CC_HEAD_CHKSUM_LEN (9)
+#define CC_VERSION_LEN (5)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+int ReadLCDParam(unsigned char data_buf[]);
+int SaveLCDParam(int wr_size, unsigned char data_buf[]);
+int ReadLCDExternParam(unsigned char data_buf[]);
+int SaveLCDExternParam(int wr_size, unsigned char data_buf[]);
+int ReadBackLightParam(unsigned char data_buf[]);
+int SaveBackLightParam(int wr_size, unsigned char data_buf[]);
+int ReadTconSpiParam(unsigned char data_buf[]);
+int SaveTconSpiParam(int wr_size, unsigned char data_buf[]);
+int ReadTconBinParam(unsigned char data_buf[]);
+int SaveTconBinParam(int wr_size, unsigned char data_buf[]);
+int ReadPanelIniName(char data_buf[]);
+int SavePanelIniName(char data_buf[]);
+int ReadPanelPQPath(char data_buf[]);
+int SavePanelPQPath(char data_buf[]);
+int ReadPanelAllInfoData(unsigned char data_buf[]);
+int SavePanelAllInfoData(int wr_size, unsigned char data_buf[]);
+int ReadPanelAllData(int sec_no, unsigned char data_buf[]);
+int SavePanelAllData(int sec_no, int wr_size, unsigned char data_buf[]);
+
+int check_hex_data_no_header_valid(unsigned int* tmp_crc32, int max_len, int buf_len, unsigned char data_buf[]);
+int check_hex_data_have_header_valid(unsigned int* tmp_crc32, int max_len, int buf_len, unsigned char data_buf[]);
+int check_string_data_have_header_valid(unsigned int* tmp_crc32, char *data_str, int chksum_head_len, int ver_len);
+unsigned int CalCRC32(unsigned int crc, const unsigned char *ptr, int buf_len);
+void PrintDataBuf(int data_cnt, unsigned char data_buf[]);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__INI_IO_H__
diff --git a/cmd/amlogic/ini/ini_log.c b/cmd/amlogic/ini/ini_log.c
new file mode 100644
index 0000000..d8495d0
--- /dev/null
+++ b/cmd/amlogic/ini/ini_log.c
@@ -0,0 +1,22 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "ini_config.h"
+
+#include "ini_log.h"
+
+#if (defined CC_COMPILE_IN_PC || defined CC_COMPILE_IN_UBOOT)
+static int gLogLevel = INI_LOG_DEFAULT;
+
+int ini_set_log_level(int log_level) {
+ int tmp_level = gLogLevel;
+ gLogLevel = log_level;
+ return tmp_level;
+}
+
+int ini_get_log_level(void) {
+ return gLogLevel;
+}
+#endif
diff --git a/cmd/amlogic/ini/ini_log.h b/cmd/amlogic/ini/ini_log.h
new file mode 100644
index 0000000..b91f5c6
--- /dev/null
+++ b/cmd/amlogic/ini/ini_log.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef ANDROID_LOG_H
+#define ANDROID_LOG_H
+
+#if (defined CC_COMPILE_IN_ANDROID)
+ #include <utils/Log.h>
+#elif (defined CC_COMPILE_IN_PC)
+ #include <stdio.h>
+ #include <stdarg.h>
+
+ extern int ioctl(int handle, int cmd, void *data);
+#elif (defined CC_COMPILE_IN_UBOOT)
+#endif
+
+#if (defined CC_COMPILE_IN_PC || defined CC_COMPILE_IN_UBOOT)
+
+ #define INI_LOG_UNKNOWN (0)
+ #define INI_LOG_DEFAULT (1)
+ #define INI_LOG_VERBOSE (2)
+ #define INI_LOG_DEBUG (3)
+ #define INI_LOG_INFO (4)
+ #define INI_LOG_WARN (5)
+ #define INI_LOG_ERROR (6)
+ #define INI_LOG_FATAL (7)
+ #define INI_LOG_SILENT (8)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+ int ini_set_log_level(int log_level);
+ int ini_get_log_level(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+ #if LOG_NDEBUG == 1
+ #define ALOGD(...)
+ #define ALOGE(...)
+ #define ALOGI(...)
+ #define ALOGW(...)
+ #else
+
+ #define __ini_log_print(prio, tag, fmt, args...) \
+ if (prio >= ini_get_log_level()) { \
+ if (prio == INI_LOG_DEBUG) { \
+ printf("D/ %s: ", tag); \
+ } else if (prio == INI_LOG_ERROR) { \
+ printf("E/ %s: ", tag); \
+ } else if (prio == INI_LOG_INFO) { \
+ printf("I/ %s: ", tag); \
+ } else if (prio == INI_LOG_WARN) { \
+ printf("W/ %s: ", tag); \
+ } else { \
+ printf("V/ %s: ", tag); \
+ } \
+ printf(fmt, ##args); \
+ printf("\n"); \
+ }
+
+ #define ALOGD(...) __ini_log_print(INI_LOG_DEBUG, LOG_TAG, __VA_ARGS__)
+ #define ALOGE(...) __ini_log_print(INI_LOG_ERROR, LOG_TAG, __VA_ARGS__)
+ #define ALOGI(...) __ini_log_print(INI_LOG_INFO, LOG_TAG, __VA_ARGS__)
+ #define ALOGW(...) __ini_log_print(INI_LOG_WARN, LOG_TAG, __VA_ARGS__)
+ #endif
+#endif
+
+#endif //ANDROID_LOG_H
diff --git a/cmd/amlogic/ini/ini_platform.c b/cmd/amlogic/ini/ini_platform.c
new file mode 100644
index 0000000..7ff9049
--- /dev/null
+++ b/cmd/amlogic/ini/ini_platform.c
@@ -0,0 +1,247 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "ini_config.h"
+
+#define LOG_TAG "ini_platform"
+#define LOG_NDEBUG 0
+
+#include "ini_log.h"
+
+#include "ini_handler.h"
+#include "ini_platform.h"
+#include <partition_table.h>
+
+//c basic lib
+char* plat_strtok_r(char *str, const char *delim, char **saveptr) {
+#if (defined CC_COMPILE_IN_PC || defined CC_COMPILE_IN_ANDROID)
+ return strtok_r(str, delim, saveptr);
+#elif (defined CC_COMPILE_IN_UBOOT)
+ return strtok(str, delim);
+#endif
+}
+
+//File functions
+#if (defined CC_COMPILE_IN_UBOOT)
+static int splitFilePath(const char *file_path, char part_name[], char file_name[], const char *ext_name) {
+ int i = 0;
+ char *tmp_start_ptr = NULL;
+ char *tmp_end_ptr = NULL;
+ char *slot_name;
+
+ if (file_path == NULL) {
+ ALOGE("%s, file_path is NULL!!!\n", __FUNCTION__);
+ return -1;
+ }
+
+ tmp_start_ptr = strchr((char*)file_path,'/');
+ if (tmp_start_ptr != file_path) {
+ ALOGE("%s, we need one abstract file path!!! %s.\n", __FUNCTION__, file_path);
+ return -1;
+ }
+
+ tmp_end_ptr = strchr(tmp_start_ptr + 1,'/');
+ if (tmp_end_ptr == NULL) {
+ ALOGE("%s, there is only partition name in the path!!!\n", __FUNCTION__);
+ return -1;
+ }
+
+ strncpy(part_name, tmp_start_ptr + 1, tmp_end_ptr - tmp_start_ptr - 1);
+ part_name[tmp_end_ptr - tmp_start_ptr - 1] = '\0';
+ //ALOGD("%s, partition name is %s\n", __FUNCTION__, part_name);
+
+ if (has_boot_slot == 1) {
+ slot_name = env_get("slot-suffixes");
+ if (slot_name == NULL) {
+ run_command("get_valid_slot", 0);
+ slot_name = env_get("slot-suffixes");
+ }
+ if (strcmp(slot_name, "0") == 0) {
+ strcat(part_name, "_a");
+ } else if (strcmp(slot_name, "1") == 0) {
+ strcat(part_name, "_b");
+ }
+ //ALOGD("%s, partition name is %s\n", __FUNCTION__, part_name);
+ }
+
+ tmp_start_ptr = tmp_end_ptr;
+
+ i = 0;
+ while (*tmp_end_ptr && i < CC_MAX_INI_FILE_NAME_LEN) {
+ tmp_end_ptr++;
+ i++;
+ }
+ if (i >= CC_MAX_INI_FILE_NAME_LEN) {
+ ALOGE("%s, file path is too long (%d)!!!\n", __FUNCTION__, i);
+ return -1;
+ }
+
+ strncpy(file_name, tmp_start_ptr, i);
+ file_name[i] = '\0';
+ //ALOGD("%s, file name is %s\n", __FUNCTION__, file_name);
+
+ if (ext_name != NULL) {
+ if (strlen(ext_name) > 0) {
+ while (tmp_end_ptr != tmp_start_ptr && *tmp_end_ptr != '.') {
+ tmp_end_ptr--;
+ }
+
+ if (*tmp_end_ptr != '.') {
+ ALOGE("%s, the file path \"%s\" doesn't have ext name!!!\n", __FUNCTION__, file_path);
+ return -1;
+ } else {
+ if (strncmp(tmp_end_ptr + 1, ext_name, 128)) {
+ ALOGE("%s, the ext name of file path \"%s\" not equal to the special ext name \"%s\"!!!\n", __FUNCTION__, file_path, ext_name);
+ return -1;
+ }
+ }
+ }
+ }
+
+ return 0;
+}
+
+#define CS_BLCOK_DEV_INTERFACE "mmc"
+#define CS_BLCOK_DEV_MARJOR_NUM "1"
+
+static int setBlockDevice(const char *part_name) {
+ int part_no = 0;
+ char part_buf[128] = {0};
+ char tmp_buf[128] = {0};
+
+ part_no = get_partition_num_by_name((char *)part_name);
+ //ALOGD("%s, part_no is %d\n", __FUNCTION__, part_no);
+ if (part_no >= 0) {
+ strcpy(part_buf, CS_BLCOK_DEV_MARJOR_NUM);
+ strcat(part_buf, ":");
+
+ sprintf(tmp_buf, "%x", part_no);
+ strcat(part_buf, tmp_buf);
+
+ return fs_set_blk_dev(CS_BLCOK_DEV_INTERFACE, part_buf, FS_TYPE_EXT);
+ }
+
+ return -1;
+}
+#endif
+
+int iniIsFileExist(const char *file_path) {
+#if (defined CC_COMPILE_IN_PC || defined CC_COMPILE_IN_ANDROID)
+ if (access(file_path, 0) < 0) {
+ return 0;
+ }
+
+ return 1;
+#elif (defined CC_COMPILE_IN_UBOOT)
+ char part_name[CC_MAX_INI_FILE_NAME_LEN];
+ char file_name[CC_MAX_INI_FILE_NAME_LEN];
+
+ memset((void *)part_name, 0, CC_MAX_INI_FILE_NAME_LEN);
+ memset((void *)file_name, 0, CC_MAX_INI_FILE_NAME_LEN);
+ if (splitFilePath(file_path, part_name, file_name, NULL) < 0) {
+ return 0;
+ }
+
+ if (setBlockDevice(part_name) < 0) {
+ return 0;
+ }
+
+ return fs_exists(file_name);
+#endif
+}
+
+int iniGetFileSize(const char *file_path) {
+#if (defined CC_COMPILE_IN_PC || defined CC_COMPILE_IN_ANDROID)
+ int file_size = 0;
+ int dev_fd = -1;
+
+ dev_fd = open(file_path, O_RDONLY);
+ if (dev_fd < 0) {
+ ALOGE("%s, open \"%s\" ERROR(%s)!!\n", __FUNCTION__,
+ file_path, strerror(errno));
+ return 0;
+ }
+
+ file_size = lseek(dev_fd, 0L, SEEK_END);
+ lseek(dev_fd, 0L, SEEK_SET);
+
+ return file_size;
+#elif (defined CC_COMPILE_IN_UBOOT)
+ loff_t file_size = 0;
+ char part_name[CC_MAX_INI_FILE_NAME_LEN];
+ char file_name[CC_MAX_INI_FILE_NAME_LEN];
+
+ memset((void *)part_name, 0, CC_MAX_INI_FILE_NAME_LEN);
+ memset((void *)file_name, 0, CC_MAX_INI_FILE_NAME_LEN);
+ if (splitFilePath(file_path, part_name, file_name, NULL) < 0) {
+ return -1;
+ }
+
+ if (setBlockDevice(part_name) < 0) {
+ return -1;
+ }
+
+ if (fs_size(file_name, &file_size)) {
+ return -1;
+ }
+
+ return file_size;
+#endif
+}
+
+int iniReadFileToBuffer(const char *file_path, int offset, int rd_size, unsigned char data_buf[]) {
+#if (defined CC_COMPILE_IN_PC || defined CC_COMPILE_IN_ANDROID)
+ int rd_cnt = 0, file_size = 0;
+ int dev_fd = -1;
+
+ dev_fd = open(file_path, O_RDONLY);
+ if (dev_fd < 0) {
+ ALOGE("%s, open \"%s\" ERROR(%s)!!\n", __FUNCTION__,
+ file_path, strerror(errno));
+ return -1;
+ }
+
+ lseek(dev_fd, offset, SEEK_SET);
+
+ rd_cnt = read(dev_fd, data_buf, rd_size);
+
+ close(dev_fd);
+ dev_fd = -1;
+
+ if (rd_cnt != rd_size) {
+ ALOGE("%s, read file \"%s\" ERROR(%d, %d)!!!!\n", __FUNCTION__,
+ file_path, rd_cnt, file_size);
+ return -1;
+ }
+
+ return rd_cnt;
+#elif (defined CC_COMPILE_IN_UBOOT)
+ int tmp_ret = -1;
+ loff_t rd_cnt = 0;
+ char part_name[CC_MAX_INI_FILE_NAME_LEN];
+ char file_name[CC_MAX_INI_FILE_NAME_LEN];
+
+ memset((void *)part_name, 0, CC_MAX_INI_FILE_NAME_LEN);
+ memset((void *)file_name, 0, CC_MAX_INI_FILE_NAME_LEN);
+ if (splitFilePath(file_path, part_name, file_name, NULL) < 0) {
+ return -1;
+ }
+
+ if (setBlockDevice(part_name) < 0) {
+ return -1;
+ }
+
+ tmp_ret = fs_read(file_name, (unsigned long)data_buf, 0, 0, &rd_cnt);
+ if (tmp_ret < 0) {
+ return -1;
+ }
+
+ flush_dcache_range((unsigned long )data_buf, (unsigned long )data_buf + rd_cnt);
+
+ return rd_cnt;
+#endif
+}
+
+
diff --git a/cmd/amlogic/ini/ini_platform.h b/cmd/amlogic/ini/ini_platform.h
new file mode 100644
index 0000000..9381adf
--- /dev/null
+++ b/cmd/amlogic/ini/ini_platform.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __INI_PLATFORM_H__
+#define __INI_PLATFORM_H__
+
+#if (defined CC_COMPILE_IN_UBOOT)
+#ifndef strtoul
+ #define strtoul simple_strtoul
+#endif
+#ifndef strtol
+ #define strtol simple_strtol
+#endif
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//c basic lib
+char* plat_strtok_r(char *str, const char *delim, char **saveptr);
+
+//File functions
+int iniIsFileExist(const char *file_path);
+int iniGetFileSize(const char *file_path);
+int iniReadFileToBuffer(const char *file_path, int offset, int rd_size, unsigned char data_buf[]);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__INI_PLATFORM_H__
diff --git a/cmd/amlogic/ini/ini_proxy.c b/cmd/amlogic/ini/ini_proxy.c
new file mode 100644
index 0000000..0348d03
--- /dev/null
+++ b/cmd/amlogic/ini/ini_proxy.c
@@ -0,0 +1,133 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "ini_config.h"
+
+#define LOG_TAG "ini_proxy"
+#define LOG_NDEBUG 0
+
+#include "ini_log.h"
+
+#include "ini_handler.h"
+#include "ini_proxy.h"
+
+INI_HANDLER_DATA *gHandlerData = NULL;
+static unsigned char *gBinData = NULL;
+
+void BinFileInit(void) {
+ if (gBinData == NULL) {
+ gBinData = malloc(CC_MAX_INI_FILE_SIZE);
+ if (gBinData != NULL)
+ memset(gBinData, 0, CC_MAX_INI_FILE_SIZE);
+ }
+}
+
+void BinFileUninit(void) {
+ if (gBinData != NULL) {
+ free(gBinData);
+ gBinData = NULL;
+ }
+}
+
+int ReadBinFile(const char* filename) {
+ if (gBinData == NULL) {
+ return -1;
+ }
+ return bin_file_read(filename, gBinData);
+}
+
+int GetBinData(unsigned char* file_buf, unsigned int file_size)
+{
+ if (gBinData == NULL) {
+ return -1;
+ }
+ if (file_buf == NULL) {
+ return -1;
+ }
+ memcpy(file_buf, gBinData, file_size);
+ return 0;
+}
+
+void IniParserInit(void) {
+ if (gHandlerData == NULL) {
+ gHandlerData = (INI_HANDLER_DATA *) malloc(sizeof(INI_HANDLER_DATA));
+ if (gHandlerData != NULL) {
+ memset((void *)gHandlerData, 0, sizeof(INI_HANDLER_DATA));
+ }
+ }
+}
+
+void IniParserUninit(void) {
+ if (gHandlerData != NULL) {
+ IniParserFree();
+ free(gHandlerData);
+ gHandlerData = NULL;
+ }
+}
+
+int IniParseFile(const char* filename) {
+ if (gHandlerData == NULL) {
+ return -1;
+ }
+ return ini_file_parse(filename, gHandlerData);
+}
+
+int IniParseMem(unsigned char* file_buf) {
+ if (gHandlerData == NULL) {
+ return -1;
+ }
+ return ini_mem_parse(file_buf, gHandlerData);
+}
+
+int IniSetSaveFileName(const char* filename) {
+ if (gHandlerData == NULL) {
+ return -1;
+ }
+ return ini_set_save_file_name(filename, gHandlerData);
+}
+
+void IniParserFree(void) {
+ if (gHandlerData == NULL) {
+ return;
+ }
+ return ini_free_mem(gHandlerData);
+}
+
+void IniPrintAll(void) {
+ if (gHandlerData == NULL) {
+ return;
+ }
+ return ini_print_all(gHandlerData);
+}
+
+void IniListSection(void) {
+ if (gHandlerData == NULL) {
+ ALOGE("%s, ini load file error!\n", __FUNCTION__);
+ return;
+ }
+ ini_list_section(gHandlerData);
+}
+
+const char* IniGetString(const char* section, const char* key,
+ const char* def_value) {
+ if (gHandlerData == NULL) {
+ return def_value;
+ }
+ return ini_get_string(section, key, def_value, gHandlerData);
+}
+
+int IniSetString(const char *section, const char *key, const char *value) {
+ if (gHandlerData == NULL) {
+ return -1;
+ }
+ return ini_set_string(section, key, value, gHandlerData);
+}
+
+int IniSaveToFile(const char *filename) {
+ if (gHandlerData == NULL) {
+ return -1;
+ }
+ return ini_save_to_file(filename, gHandlerData);
+}
diff --git a/cmd/amlogic/ini/ini_proxy.h b/cmd/amlogic/ini/ini_proxy.h
new file mode 100644
index 0000000..0f041cf
--- /dev/null
+++ b/cmd/amlogic/ini/ini_proxy.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __INI_PROXY_H__
+#define __INI_PROXY_H__
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void BinFileInit(void);
+void BinFileUninit(void);
+int ReadBinFile(const char* filename);
+int GetBinData(unsigned char* file_buf, unsigned int file_size);
+
+void IniParserInit(void);
+void IniParserUninit(void);
+int IniParseFile(const char* filename);
+int IniParseMem(unsigned char* file_buf);
+int IniSetSaveFileName(const char* filename);
+void IniParserFree(void);
+void IniPrintAll(void);
+void IniListSection(void);
+const char* IniGetString(const char* section, const char* key, const char* def_value);
+int IniSetString(const char *section, const char *key, const char *value);
+int IniSaveToFile(const char *filename);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif //__INI_PROXY_H__
diff --git a/cmd/amlogic/ini/ini_size_define.h b/cmd/amlogic/ini/ini_size_define.h
new file mode 100644
index 0000000..27be83e
--- /dev/null
+++ b/cmd/amlogic/ini/ini_size_define.h
@@ -0,0 +1,48 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __INI_SIZE_H__
+#define __INI_SIZE_H__
+
+#define CC_MAX_TEMP_BUF_SIZE (0x1000)
+#define CC_MAX_PANEL_ALL_DATA_SIZE (0x100000)
+
+#define CC_MAX_INI_FILE_NAME_LEN (512)
+/* 256->5k for large lcd_ext large init_on table */
+#define CC_MAX_INI_FILE_LINE_LEN (5120)
+
+#define CC_MAX_INI_LINE_NAME_LEN (128)
+#define CC_MAX_INI_FILE_SIZE (0x400000)
+
+#define CC_MAX_DATA_SIZE (0x300000)
+#define CC_MAX_TCON_BIN_SIZE (0xf000) /* max:24000 */
+#define CC_MAX_TCON_VAC_SIZE (0x1000)
+#define CC_MAX_TCON_DEMURA_SET_SIZE (0x1000)
+#define CC_MAX_TCON_DEMURA_LUT_SIZE (0x120000)
+#define CC_MAX_TCON_ACC_LUT_SIZE (0x1000)
+#define CC_MAX_TCON_BIN_PATH_SIZE (0x2800)
+#define CC_MAX_TCON_SPI_SIZE (0x610)
+#define CC_ONE_SECTION_SIZE (0x10000)
+
+
+#ifdef CONFIG_INI_MAX_LINE
+#define MAX_LINE CONFIG_INI_MAX_LINE
+#else
+#define MAX_LINE 200
+#endif
+
+#ifdef CONFIG_INI_MAX_SECTION
+#define MAX_SECTION CONFIG_INI_MAX_SECTION
+#else
+#define MAX_SECTION 300
+#endif
+
+#ifdef CONFIG_INI_MAX_NAME
+#define MAX_NAME CONFIG_INI_MAX_NAME
+#else
+#define MAX_NAME 100
+#endif
+
+#endif //__INI_CONFIG_H__
diff --git a/cmd/amlogic/ini/model.c b/cmd/amlogic/ini/model.c
new file mode 100644
index 0000000..b0cb9c7
--- /dev/null
+++ b/cmd/amlogic/ini/model.c
@@ -0,0 +1,2860 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "ini_config.h"
+
+#define LOG_TAG "model"
+#define LOG_NDEBUG 0
+
+#include "ini_log.h"
+
+#include "ini_proxy.h"
+#include "ini_handler.h"
+#include "ini_platform.h"
+#include "ini_io.h"
+#include "model.h"
+#include <partition_table.h>
+
+#define DEFAULT_MODEL_SUM_PATH1 "/odm/etc/tvconfig/model/model_sum.ini"
+#define DEFAULT_MODEL_SUM_PATH2 "/odm_ext/etc/tvconfig/model/model_sum.ini"
+#define AML_START "amlogic_start"
+#define AML_END "amlogic_end"
+
+#define CC_PARAM_CHECK_OK (0)
+#define CC_PARAM_CHECK_ERROR_NEED_UPDATE_PARAM (-1)
+#define CC_PARAM_CHECK_ERROR_NOT_NEED_UPDATE_PARAM (-2)
+
+#ifdef CONFIG_AML_LCD
+#define DEBUG_NORMAL (1 << 0)
+#define DEBUG_LCD (1 << 1)
+#define DEBUG_LCD_EXTERN (1 << 2)
+#define DEBUG_BACKLIGHT (1 << 3)
+#define DEBUG_MISC (1 << 4)
+#define DEBUG_TCON (1 << 5)
+static int model_debug_flag;
+
+static int gLcdDataCnt, gLcdExtDataCnt, gBlDataCnt;
+static int g_lcd_pwr_on_seq_cnt, g_lcd_pwr_off_seq_cnt;
+static int gLcdExtInitOnCnt, gLcdExtInitOffCnt, gLcdExtCmdSize;
+static struct lcd_ext_attr_s *lcd_ext_attr;
+static unsigned int g_lcd_tcon_valid;
+#ifdef CONFIG_AML_LCD_TCON
+static int gLcdTconDataCnt, gLcdTconSpi_cnt;
+static unsigned int g_lcd_tcon_bin_block_cnt;
+static unsigned char *g_lcd_tcon_bin_path_mem;
+
+static int handle_tcon_ext_pmu_data(int index, int flag, unsigned char *buf,
+ unsigned int offset, unsigned int data_len);
+#endif
+#endif
+
+#ifdef CONFIG_AML_LCD
+static int transBufferData(const char *data_str, unsigned int data_buf[]) {
+ int item_ind = 0;
+ char *token = NULL;
+ char *pSave = NULL;
+ char *tmp_buf = NULL;
+
+ if (data_str == NULL)
+ return 0;
+
+ tmp_buf = (char *) malloc(CC_MAX_TEMP_BUF_SIZE);
+ if (tmp_buf == NULL) {
+ ALOGE("%s, malloc buffer memory error!!!\n", __func__);
+ return -1;
+ }
+
+ memset((void *)tmp_buf, 0, CC_MAX_TEMP_BUF_SIZE);
+ strncpy(tmp_buf, data_str, CC_MAX_TEMP_BUF_SIZE - 1);
+ token = plat_strtok_r(tmp_buf, ",", &pSave);
+ while (token != NULL) {
+ data_buf[item_ind] = strtoul(token, NULL, 0);
+ item_ind++;
+ token = plat_strtok_r(NULL, ",", &pSave);
+ }
+
+ free(tmp_buf);
+ tmp_buf = NULL;
+
+ return item_ind;
+}
+
+static int check_param_valid(int mode, int parse_len, unsigned char parse_buf[], int ori_len, unsigned char ori_buf[])
+{
+ unsigned int ori_cal_crc32 = 0, parse_cal_crc32 = 0;
+
+ if (mode == 0) {
+ // start check parse data valid
+ //ALOGD("%s, start check parse data valid\n", __func__);
+ if (check_hex_data_have_header_valid(&parse_cal_crc32, CC_MAX_DATA_SIZE, parse_len, parse_buf) < 0)
+ return CC_PARAM_CHECK_ERROR_NOT_NEED_UPDATE_PARAM;
+
+ // start check flash key data valid
+ //ALOGD("%s, start check flash key data valid\n", __func__);
+ if (check_hex_data_have_header_valid(&ori_cal_crc32, CC_MAX_DATA_SIZE, ori_len, ori_buf) < 0)
+ return CC_PARAM_CHECK_ERROR_NEED_UPDATE_PARAM;
+
+ if (parse_cal_crc32 != ori_cal_crc32) {
+ //ALOGE("%s, parse data not equal flash data(0x%08X, 0x%08X)\n", __func__, parse_cal_crc32, ori_cal_crc32);
+ return CC_PARAM_CHECK_ERROR_NEED_UPDATE_PARAM;
+ }
+ // end check parse data valid
+ } else if (mode == 1) {
+ // start check parse data valid
+ //ALOGD("%s, start check parse data valid\n", __func__);
+ if (check_hex_data_no_header_valid(&parse_cal_crc32, CC_MAX_DATA_SIZE, parse_len, parse_buf) < 0)
+ return CC_PARAM_CHECK_ERROR_NOT_NEED_UPDATE_PARAM;
+
+ // start check flash key data valid
+ //ALOGD("%s, start check flash key data valid\n", __func__);
+ if (check_hex_data_no_header_valid(&ori_cal_crc32, CC_MAX_DATA_SIZE, ori_len, ori_buf) < 0)
+ return CC_PARAM_CHECK_ERROR_NEED_UPDATE_PARAM;
+
+ if (parse_cal_crc32 != ori_cal_crc32) {
+ //ALOGE("%s, parse data not equal flash data(0x%08X, 0x%08X)\n", __func__, parse_cal_crc32, ori_cal_crc32);
+ return CC_PARAM_CHECK_ERROR_NEED_UPDATE_PARAM;
+ }
+ // end check parse data valid
+ } else {
+ // start check parse data valid
+ //ALOGD("%s, start check parse data valid\n", __func__);
+ if (check_string_data_have_header_valid(&parse_cal_crc32, (char *)parse_buf, CC_HEAD_CHKSUM_LEN, CC_VERSION_LEN) < 0)
+ return CC_PARAM_CHECK_ERROR_NOT_NEED_UPDATE_PARAM;
+
+ // start check flash key data valid
+ //ALOGD("%s, start check flash key data valid\n", __func__);
+ if (check_string_data_have_header_valid(&ori_cal_crc32, (char *)ori_buf, CC_HEAD_CHKSUM_LEN, CC_VERSION_LEN) < 0)
+ return CC_PARAM_CHECK_ERROR_NEED_UPDATE_PARAM;
+
+ if (parse_cal_crc32 != ori_cal_crc32) {
+ //ALOGE("%s, parse data not equal flash data(0x%08X, 0x%08X)\n", __func__, parse_cal_crc32, ori_cal_crc32);
+ return CC_PARAM_CHECK_ERROR_NEED_UPDATE_PARAM;
+ }
+ // end check parse data valid
+ }
+
+ //ALOGD("%s, param check ok!\n", __func__);
+ return CC_PARAM_CHECK_OK;
+}
+
+static int handle_integrity_flag(void)
+{
+ const char *ini_value = NULL;
+
+ ini_value = IniGetString("start", "start_tag", "null");
+ if (model_debug_flag & DEBUG_NORMAL)
+ ALOGD("%s, start_tag is (%s)\n", __func__, ini_value);
+ if (strncasecmp(ini_value, AML_START, strlen(AML_START))) {
+ ALOGE("%s, start_tag (%s) is error!!!\n", __func__, ini_value);
+ return -1;
+ }
+
+ ini_value = IniGetString("end", "end_tag", "null");
+ if (model_debug_flag & DEBUG_NORMAL)
+ ALOGD("%s, end_tag is (%s)\n", __func__, ini_value);
+ if (strncasecmp(ini_value, AML_END, strlen(AML_END))) {
+ ALOGE("%s, end_tag (%s) is error!!!\n", __func__, ini_value);
+ return -1;
+ }
+
+ return 0;
+}
+
+void *handle_lcd_ext_buf_get(void)
+{
+ return (void *)lcd_ext_attr;
+}
+
+#ifdef CONFIG_AML_LCD_TCON
+static unsigned int handle_tcon_char_data_size_align(unsigned int size)
+{
+ unsigned int new_size;
+
+ if (size % 4)
+ new_size = (size / 4 + 1) * 4;
+ else
+ new_size = size;
+
+ return new_size;
+}
+
+void *handle_tcon_path_mem_get(unsigned int size)
+{
+ unsigned int data_size = 0;
+
+ if (!g_lcd_tcon_bin_path_mem) {
+ ALOGE("%s, buf is null\n", __func__);
+ return NULL;
+ }
+
+ data_size = g_lcd_tcon_bin_path_mem[4] |
+ (g_lcd_tcon_bin_path_mem[5] << 8) |
+ (g_lcd_tcon_bin_path_mem[6] << 16) |
+ (g_lcd_tcon_bin_path_mem[7] << 24);
+ if (data_size > size) {
+ ALOGE("%s, buf size invalid\n", __func__);
+ return NULL;
+ }
+
+ return g_lcd_tcon_bin_path_mem;
+}
+
+static char *handle_tcon_path_file_name_get(unsigned int index)
+{
+ unsigned int n;
+ char *str;
+
+ if (!g_lcd_tcon_bin_path_mem) {
+ ALOGE("%s, tcon_path buf is null\n", __func__);
+ return NULL;
+ }
+
+ if (index >= g_lcd_tcon_bin_block_cnt) {
+ ALOGE("%s, invalid index %d\n", __func__, index);
+ return NULL;
+ }
+
+ n = 32 + (index * 256) + 4;
+ str = (char *)&g_lcd_tcon_bin_path_mem[n];
+ return str;
+}
+
+static int handle_tcon_path(void)
+{
+ unsigned char *buf;
+ char str[30], env_str[30];
+ const char *ini_value = NULL;
+ unsigned int temp, i, n, version, header, block_cnt, data_size, crc32;
+
+ /* version */
+ ini_value = IniGetString("tcon_Path", "version", "0");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, version is (%s)\n", __func__, ini_value);
+ version = strtoul(ini_value, NULL, 0);
+
+ /* tcon_bin_header */
+ ini_value = IniGetString("tcon_Path", "header", "0");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, header is (%s)\n", __func__, ini_value);
+ header = strtoul(ini_value, NULL, 0);
+ snprintf(str, 30, "%d", header);
+ env_set("model_tcon_bin_header", str);
+
+ /* tcon regs bin */
+ ini_value = IniGetString("tcon_Path", "TCON_BIN_PATH", "null");
+ if (!strcmp(ini_value, "null")) {
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGE("%s, tcon bin load file error!\n", __func__);
+ }
+ env_set("model_tcon", ini_value);
+
+ /* tcon data bin path */
+ g_lcd_tcon_bin_path_mem = (unsigned char *) malloc(CC_MAX_TCON_BIN_PATH_SIZE);
+ if (!g_lcd_tcon_bin_path_mem) {
+ ALOGE("%s, malloc buffer memory error!!!\n", __func__);
+ return -1;
+ }
+ memset(g_lcd_tcon_bin_path_mem, 0, CC_MAX_TCON_BIN_PATH_SIZE);
+ buf = g_lcd_tcon_bin_path_mem;
+
+ /* version */
+ buf[8] = version & 0xff;
+ buf[9] = (version >> 8) & 0xff;
+ buf[10] = (version >> 16) & 0xff;
+ buf[11] = (version >> 24) & 0xff;
+
+ /* data_load_level */
+ ini_value = IniGetString("tcon_Path", "data_load_level", "0");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, data_load_level is (%s)\n", __func__, ini_value);
+ temp = strtoul(ini_value, NULL, 0);
+ buf[12] = temp & 0xff;
+ buf[13] = (temp >> 8) & 0xff;
+ buf[14] = (temp >> 16) & 0xff;
+ buf[15] = (temp >> 24) & 0xff;
+
+ block_cnt = 0;
+ n = 32;
+
+ if (version == 0) {/* tcon data bin: old data format */
+ ini_value = IniGetString("tcon_Path", "TCON_VAC_PATH", "null");
+ if (!strcmp(ini_value, "null")) {
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, no vac ini file\n", __func__);
+ }
+ env_set("model_tcon_vac", ini_value);
+ strncpy((char *)&buf[n + 4], ini_value, 256);
+ n += 256;
+
+ ini_value = IniGetString("tcon_Path", "TCON_DEMURA_SET_PATH", "null");
+ if (!strcmp(ini_value, "null")) {
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, no demura_set file\n", __func__);
+ }
+ env_set("model_tcon_demura_set", ini_value);
+ strncpy((char *)&buf[n + 4], ini_value, 256);
+ n += 256;
+
+ ini_value = IniGetString("tcon_Path", "TCON_DEMURA_LUT_PATH", "null");
+ if (!strcmp(ini_value, "null")) {
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, no demura_lut file\n", __func__);
+ }
+ env_set("model_tcon_demura_lut", ini_value);
+ strncpy((char *)&buf[n + 4], ini_value, 256);
+ n += 256;
+
+ ini_value = IniGetString("tcon_Path", "TCON_ACC_LUT_PATH", "null");
+ if (!strcmp(ini_value, "null")) {
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, no acc_lut file\n", __func__);
+ }
+ env_set("model_tcon_acc_lut", ini_value);
+ strncpy((char *)&buf[n + 4], ini_value, 256);
+
+ /* block cnt */
+ block_cnt = 4;
+ buf[16] = block_cnt & 0xff;
+ buf[17] = (block_cnt >> 8) & 0xff;
+ buf[18] = (block_cnt >> 16) & 0xff;
+ buf[19] = (block_cnt >> 24) & 0xff;
+ } else {/* tcon data bin: new data format */
+ for (i = 0; i < 32; i++) {
+ snprintf(str, 30, "TCON_DATA_%d_BIN_PATH", i);
+ ini_value = IniGetString("tcon_Path", str, "null");
+ if (strcmp(ini_value, "null") == 0)
+ break;
+
+ if (model_debug_flag & DEBUG_TCON) {
+ ALOGD("%s, tcon_path %d is (%s)\n",
+ __func__, i, ini_value);
+ }
+ strncpy((char *)&buf[n + 4], ini_value, 252);
+ block_cnt++;
+ n += 256;
+ }
+
+ /* block cnt */
+ buf[16] = block_cnt & 0xff;
+ buf[17] = (block_cnt >> 8) & 0xff;
+ buf[18] = (block_cnt >> 16) & 0xff;
+ buf[19] = (block_cnt >> 24) & 0xff;
+ }
+
+ /* tcon data bin path */
+ g_lcd_tcon_bin_block_cnt = block_cnt;
+
+ /* data size */
+ data_size = 32 + block_cnt * 256;
+ buf[4] = data_size & 0xff;
+ buf[5] = (data_size >> 8) & 0xff;
+ buf[6] = (data_size >> 16) & 0xff;
+ buf[7] = (data_size >> 24) & 0xff;
+
+ /* data check */
+ crc32 = CalCRC32(0, &buf[4], (data_size - 4));
+ buf[0] = crc32 & 0xff;
+ buf[1] = (crc32 >> 8) & 0xff;
+ buf[2] = (crc32 >> 16) & 0xff;
+ buf[3] = (crc32 >> 24) & 0xff;
+
+ /* pmu bin */
+ for (i = 0; i < 4; i++) {
+ snprintf(str, 30, "TCON_EXT_B%d_BIN_PATH", i);
+ snprintf(env_str, 30, "model_tcon_ext_b%d", i);
+ ini_value = IniGetString("tcon_Path", str, "null");
+ if (!strcmp(ini_value, "null")) {
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, no %s file\n", __func__, str);
+ }
+ env_set(env_str, ini_value);
+ }
+
+ for (i = 0; i < 4; i++) {
+ snprintf(str, 30, "TCON_EXT_B%d_SPI_BIN_PATH", i);
+ snprintf(env_str, 30, "model_tcon_ext_b%d_spi", i);
+ ini_value = IniGetString("tcon_Path", str, "null");
+ if (!strcmp(ini_value, "null")) {
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, no %s file\n", __func__, str);
+ }
+ env_set(env_str, ini_value);
+ }
+
+ return 0;
+}
+#endif
+
+static int handle_lcd_basic(struct lcd_attr_s *p_attr)
+{
+ const char *ini_value = NULL;
+
+ ini_value = IniGetString("lcd_Attr", "model_name", "null");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, model_name is (%s)\n", __func__, ini_value);
+ strncpy(p_attr->basic.model_name, ini_value, CC_LCD_NAME_LEN_MAX - 1);
+ p_attr->basic.model_name[CC_LCD_NAME_LEN_MAX - 1] = '\0';
+
+ ini_value = IniGetString("lcd_Attr", "interface", "null");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, interface is (%s)\n", __func__, ini_value);
+ if (strcmp(ini_value, "LCD_TTL") == 0)
+ p_attr->basic.lcd_type = LCD_TTL;
+ else if (strcmp(ini_value, "LCD_LVDS") == 0)
+ p_attr->basic.lcd_type = LCD_LVDS;
+ else if (strcmp(ini_value, "LCD_VBYONE") == 0)
+ p_attr->basic.lcd_type = LCD_VBYONE;
+ else if (strcmp(ini_value, "LCD_MIPI") == 0)
+ p_attr->basic.lcd_type = LCD_MIPI;
+ else if (strcmp(ini_value, "LCD_MLVDS") == 0)
+ p_attr->basic.lcd_type = LCD_MLVDS;
+ else if (strcmp(ini_value, "LCD_P2P") == 0)
+ p_attr->basic.lcd_type = LCD_P2P;
+ else
+ p_attr->basic.lcd_type = LCD_TYPE_MAX;
+
+ ini_value = IniGetString("lcd_Attr", "lcd_bits", "10");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, lcd_bits is (%s)\n", __func__, ini_value);
+ p_attr->basic.lcd_bits = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "screen_width", "16");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, screen_width is (%s)\n", __func__, ini_value);
+ p_attr->basic.screen_width = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "screen_height", "9");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, screen_height is (%s)\n", __func__, ini_value);
+ p_attr->basic.screen_height = strtoul(ini_value, NULL, 0);
+
+ return 0;
+}
+
+static int handle_lcd_timming(struct lcd_attr_s *p_attr)
+{
+ const char *ini_value = NULL;
+
+ ini_value = IniGetString("lcd_Attr", "h_active", "1920");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, h_active is (%s)\n", __func__, ini_value);
+ p_attr->timming.h_active = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "v_active", "1080");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, v_active is (%s)\n", __func__, ini_value);
+ p_attr->timming.v_active = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "h_period", "2200");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, h_period is (%s)\n", __func__, ini_value);
+ p_attr->timming.h_period = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "v_period", "1125");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, v_period is (%s)\n", __func__, ini_value);
+ p_attr->timming.v_period = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "hsync_width", "44");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, hsync_width is (%s)\n", __func__, ini_value);
+ p_attr->timming.hsync_width = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "hsync_bp", "148");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, hsync_bp is (%s)\n", __func__, ini_value);
+ p_attr->timming.hsync_bp = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "hsync_pol", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, hsync_pol is (%s)\n", __func__, ini_value);
+ p_attr->timming.hsync_pol = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "vsync_width", "5");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, vsync_width is (%s)\n", __func__, ini_value);
+ p_attr->timming.vsync_width = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "vsync_bp", "30");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, vsync_bp is (%s)\n", __func__, ini_value);
+ p_attr->timming.vsync_bp = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "vsync_pol", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, vsync_pol is (%s)\n", __func__, ini_value);
+ p_attr->timming.vsync_pol = strtoul(ini_value, NULL, 0);
+
+ return 0;
+}
+
+static int handle_lcd_customer(struct lcd_attr_s *p_attr)
+{
+ const char *ini_value = NULL;
+
+ ini_value = IniGetString("lcd_Attr", "fr_adjust_type", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, fr_adjust_type is (%s)\n", __func__, ini_value);
+ p_attr->customer.fr_adjust_type = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "ss_level", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, ss_level is (%s)\n", __func__, ini_value);
+ p_attr->customer.ss_level = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "clk_auto_gen", "1");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, clk_auto_gen is (%s)\n", __func__, ini_value);
+ p_attr->customer.clk_auto_gen = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "pixel_clk", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, pixel_clk is (%s)\n", __func__, ini_value);
+ p_attr->customer.pixel_clk = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "h_period_min", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, h_period_min is (%s)\n", __func__, ini_value);
+ p_attr->customer.h_period_min = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "h_period_max", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, h_period_max is (%s)\n", __func__, ini_value);
+ p_attr->customer.h_period_max = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "v_period_min", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, v_period_min is (%s)\n", __func__, ini_value);
+ p_attr->customer.v_period_min = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "v_period_max", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, v_period_max is (%s)\n", __func__, ini_value);
+ p_attr->customer.v_period_max = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "pixel_clk_min", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, pixel_clk_min is (%s)\n", __func__, ini_value);
+ p_attr->customer.pixel_clk_min = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "pixel_clk_max", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, pixel_clk_max is (%s)\n", __func__, ini_value);
+ p_attr->customer.pixel_clk_max = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "vlock_val_0", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, vlock_val_0 is (%s)\n", __func__, ini_value);
+ p_attr->customer.vlock_val_0 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "vlock_val_1", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, vlock_val_1 is (%s)\n", __func__, ini_value);
+ p_attr->customer.vlock_val_1 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "vlock_val_2", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, vlock_val_2 is (%s)\n", __func__, ini_value);
+ p_attr->customer.vlock_val_2 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "vlock_val_3", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, vlock_val_3 is (%s)\n", __func__, ini_value);
+ p_attr->customer.vlock_val_3 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "customer_value_9", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, customer_value_9 is (%s)\n", __func__, ini_value);
+ p_attr->customer.customer_value_9 = strtoul(ini_value, NULL, 0);
+
+ return 0;
+}
+
+static int handle_lcd_interface(struct lcd_attr_s *p_attr)
+{
+ const char *ini_value = NULL;
+
+ ini_value = IniGetString("lcd_Attr", "if_attr_0", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, if_attr_0 is (%s)\n", __func__, ini_value);
+ p_attr->interface.if_attr_0 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "if_attr_1", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, if_attr_1 is (%s)\n", __func__, ini_value);
+ p_attr->interface.if_attr_1 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "if_attr_2", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, if_attr_2 is (%s)\n", __func__, ini_value);
+ p_attr->interface.if_attr_2 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "if_attr_3", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, if_attr_3 is (%s)\n", __func__, ini_value);
+ p_attr->interface.if_attr_3 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "if_attr_4", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, if_attr_4 is (%s)\n", __func__, ini_value);
+ p_attr->interface.if_attr_4 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "if_attr_5", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, if_attr_5 is (%s)\n", __func__, ini_value);
+ p_attr->interface.if_attr_5 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "if_attr_6", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, if_attr_6 is (%s)\n", __func__, ini_value);
+ p_attr->interface.if_attr_6 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "if_attr_7", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, if_attr_7 is (%s)\n", __func__, ini_value);
+ p_attr->interface.if_attr_7 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "if_attr_8", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, if_attr_8 is (%s)\n", __func__, ini_value);
+ p_attr->interface.if_attr_8 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_Attr", "if_attr_9", "0");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, if_attr_9 is (%s)\n", __func__, ini_value);
+ p_attr->interface.if_attr_9 = strtoul(ini_value, NULL, 0);
+
+ return 0;
+}
+
+static int handle_lcd_pwr(struct lcd_attr_s *p_attr)
+{
+ int i = 0, tmp_cnt = 0, tmp_base_ind = 0;
+ const char *ini_value = NULL;
+ unsigned int tmp_buf[1024];
+
+ ini_value = IniGetString("lcd_Attr", "power_on_step", "null");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, power_on_step is (%s)\n", __func__, ini_value);
+ tmp_cnt = transBufferData(ini_value, tmp_buf + 0);
+ g_lcd_pwr_on_seq_cnt = tmp_cnt / CC_LCD_PWR_ITEM_CNT;
+ for (i = 0; i < g_lcd_pwr_on_seq_cnt; i++) {
+ tmp_base_ind = i * CC_LCD_PWR_ITEM_CNT;
+ p_attr->pwr[i].pwr_step_type = tmp_buf[tmp_base_ind + 0];
+ p_attr->pwr[i].pwr_step_index = tmp_buf[tmp_base_ind + 1];
+ p_attr->pwr[i].pwr_step_val = tmp_buf[tmp_base_ind + 2];
+ p_attr->pwr[i].pwr_step_delay = tmp_buf[tmp_base_ind + 3];
+ }
+
+ ini_value = IniGetString("lcd_Attr", "power_off_step", "null");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, power_off_step is (%s)\n", __func__, ini_value);
+ tmp_cnt = transBufferData(ini_value, tmp_buf + tmp_cnt);
+ g_lcd_pwr_off_seq_cnt = tmp_cnt / CC_LCD_PWR_ITEM_CNT;
+ for (i = 0; i < g_lcd_pwr_off_seq_cnt; i++) {
+ tmp_base_ind = (g_lcd_pwr_on_seq_cnt + i)* CC_LCD_PWR_ITEM_CNT;
+ p_attr->pwr[i + g_lcd_pwr_on_seq_cnt].pwr_step_type = tmp_buf[tmp_base_ind + 0];
+ p_attr->pwr[i + g_lcd_pwr_on_seq_cnt].pwr_step_index = tmp_buf[tmp_base_ind + 1];
+ p_attr->pwr[i + g_lcd_pwr_on_seq_cnt].pwr_step_val = tmp_buf[tmp_base_ind + 2];
+ p_attr->pwr[i + g_lcd_pwr_on_seq_cnt].pwr_step_delay = tmp_buf[tmp_base_ind + 3];
+ }
+
+ return 0;
+}
+
+static int handle_lcd_header(struct lcd_attr_s *p_attr)
+{
+ const char *ini_value = NULL;
+
+ gLcdDataCnt = 0;
+ gLcdDataCnt += sizeof(struct lcd_header_s);
+ gLcdDataCnt += sizeof(struct lcd_basic_s);
+ gLcdDataCnt += sizeof(struct lcd_timming_s);
+ gLcdDataCnt += sizeof(struct lcd_customer_s);
+ gLcdDataCnt += sizeof(struct lcd_interface_s);
+
+ gLcdDataCnt += sizeof(struct lcd_pwr_s) * g_lcd_pwr_on_seq_cnt;
+ gLcdDataCnt += sizeof(struct lcd_pwr_s) * g_lcd_pwr_off_seq_cnt;
+
+ p_attr->head.data_len = gLcdDataCnt;
+
+ ini_value = IniGetString("lcd_Attr", "version", "null");
+ if (model_debug_flag & DEBUG_LCD)
+ ALOGD("%s, version is (%s)\n", __func__, ini_value);
+ if (strcmp(ini_value, "null") == 0)
+ p_attr->head.version = 0;
+ else
+ p_attr->head.version = strtoul(ini_value, NULL, 0);
+
+ p_attr->head.rev = 0;
+ p_attr->head.crc32 = CalCRC32(0, (((unsigned char *)p_attr) + 4), gLcdDataCnt - 4);
+
+ return 0;
+}
+
+static int handle_lcd_ext_basic(struct lcd_ext_attr_s *p_attr)
+{
+ const char *ini_value = NULL;
+
+ ini_value = IniGetString("lcd_ext_Attr", "ext_name", "null");
+ if (model_debug_flag & DEBUG_LCD_EXTERN)
+ ALOGD("%s, ext_name is (%s)\n", __func__, ini_value);
+ strncpy(p_attr->basic.ext_name, ini_value, CC_LCD_EXT_NAME_LEN_MAX - 1);
+ p_attr->basic.ext_name[CC_LCD_EXT_NAME_LEN_MAX - 1] = '\0';
+
+ ini_value = IniGetString("lcd_ext_Attr", "ext_index", "0xff");
+ if (model_debug_flag & DEBUG_LCD_EXTERN)
+ ALOGD("%s, ext_index is (%s)\n", __func__, ini_value);
+ p_attr->basic.ext_index = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_ext_Attr", "ext_type", "null");
+ if (model_debug_flag & DEBUG_LCD_EXTERN)
+ ALOGD("%s, ext_type is (%s)\n", __func__, ini_value);
+ if (strcmp(ini_value, "LCD_EXTERN_I2C") == 0)
+ p_attr->basic.ext_type = LCD_EXTERN_I2C;
+ else if (strcmp(ini_value, "LCD_EXTERN_SPI") == 0)
+ p_attr->basic.ext_type = LCD_EXTERN_SPI;
+ else if (strcmp(ini_value, "LCD_EXTERN_MIPI") == 0)
+ p_attr->basic.ext_type = LCD_EXTERN_MIPI;
+ else
+ p_attr->basic.ext_type = LCD_EXTERN_MAX;
+
+ ini_value = IniGetString("lcd_ext_Attr", "ext_status", "0");
+ if (model_debug_flag & DEBUG_LCD_EXTERN)
+ ALOGD("%s, ext_status is (%s)\n", __func__, ini_value);
+ p_attr->basic.ext_status = strtoul(ini_value, NULL, 0);
+
+ return 0;
+}
+
+static int handle_lcd_ext_type(struct lcd_ext_attr_s *p_attr)
+{
+ const char *ini_value = NULL;
+
+ ini_value = IniGetString("lcd_ext_Attr", "value_0", "null");
+ if (model_debug_flag & DEBUG_LCD_EXTERN)
+ ALOGD("%s, value_0 is (%s)\n", __func__, ini_value);
+ p_attr->type.value_0 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_ext_Attr", "value_1", "null");
+ if (model_debug_flag & DEBUG_LCD_EXTERN)
+ ALOGD("%s, value_1 is (%s)\n", __func__, ini_value);
+ p_attr->type.value_1 = strtoul(ini_value, NULL, 0);
+
+ if (p_attr->basic.ext_type == LCD_EXTERN_I2C)
+ p_attr->type.value_2 = LCD_EXTERN_I2C_BUS_INVALID;
+ else {
+ ini_value = IniGetString("lcd_ext_Attr", "value_2", "null");
+ if (model_debug_flag & DEBUG_LCD_EXTERN)
+ ALOGD("%s, value_2 is (%s)\n", __func__, ini_value);
+ p_attr->type.value_2 = strtoul(ini_value, NULL, 0);
+ }
+
+ ini_value = IniGetString("lcd_ext_Attr", "value_3", "null");
+ if (model_debug_flag & DEBUG_LCD_EXTERN)
+ ALOGD("%s, value_3 is (%s)\n", __func__, ini_value);
+ p_attr->type.value_3 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_ext_Attr", "value_4", "null");
+ if (model_debug_flag & DEBUG_LCD_EXTERN)
+ ALOGD("%s, value_4 is (%s)\n", __func__, ini_value);
+ p_attr->type.value_4 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_ext_Attr", "value_5", "null");
+ if (model_debug_flag & DEBUG_LCD_EXTERN)
+ ALOGD("%s, value_5 is (%s)\n", __func__, ini_value);
+ p_attr->type.value_5 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_ext_Attr", "value_6", "null");
+ if (model_debug_flag & DEBUG_LCD_EXTERN)
+ ALOGD("%s, value_6 is (%s)\n", __func__, ini_value);
+ p_attr->type.value_6 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_ext_Attr", "value_7", "null");
+ if (model_debug_flag & DEBUG_LCD_EXTERN)
+ ALOGD("%s, value_7 is (%s)\n", __func__, ini_value);
+ p_attr->type.value_7 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_ext_Attr", "value_8", "null");
+ if (model_debug_flag & DEBUG_LCD_EXTERN)
+ ALOGD("%s, value_8 is (%s)\n", __func__, ini_value);
+ p_attr->type.value_8 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("lcd_ext_Attr", "value_9", "null");
+ if (model_debug_flag & DEBUG_LCD_EXTERN)
+ ALOGD("%s, value_9 is (%s)\n", __func__, ini_value);
+ p_attr->type.value_9 = strtoul(ini_value, NULL, 0);
+
+ if (p_attr->basic.ext_type == LCD_EXTERN_I2C)
+ gLcdExtCmdSize = p_attr->type.value_3;
+ else if (p_attr->basic.ext_type == LCD_EXTERN_SPI)
+ gLcdExtCmdSize = p_attr->type.value_6;
+ else
+ gLcdExtCmdSize = p_attr->type.value_9;
+
+ return 0;
+}
+
+static int handle_lcd_ext_cmd_data(struct lcd_ext_attr_s *p_attr)
+{
+ int i = 0, j = 0, k, tmp_cnt = 0, tmp_off = 0;
+ const char *ini_value = NULL;
+ unsigned int tmp_buf[2048];
+ unsigned char *data_buf = NULL;
+ unsigned int data_size = 0;
+#ifdef CONFIG_AML_LCD_TCON
+ unsigned int n, flag = 0;
+ unsigned int offset = 0, data_len = 0;
+ int ret;
+#endif
+
+ /* orignal data in ini */
+ ini_value = IniGetString("lcd_ext_Attr", "init_on", "null");
+ if (model_debug_flag & DEBUG_LCD_EXTERN)
+ ALOGD("%s, init_on is (%s)\n", __func__, ini_value);
+ tmp_cnt = transBufferData(ini_value, tmp_buf);
+
+ data_buf = (unsigned char *)malloc(LCD_EXTERN_INIT_ON_MAX);
+ if (data_buf == NULL) {
+ ALOGE("%s, malloc buffer memory error!!!\n", __func__);
+ return -1;
+ }
+
+ /* data check and copy */
+ if (tmp_cnt > LCD_EXTERN_INIT_ON_MAX) {
+ ALOGE("%s: invalid init_on data\n", __func__);
+ p_attr->cmd_data[0] = LCD_EXTERN_INIT_END;
+ p_attr->cmd_data[1] = 0;
+ gLcdExtInitOnCnt = 2;
+ } else {
+ if (gLcdExtCmdSize == 0xff) {
+ i = 0;
+ j = 0;
+ while (i < tmp_cnt) {
+ p_attr->cmd_data[j] = tmp_buf[i];
+ if (p_attr->cmd_data[j] == LCD_EXTERN_INIT_END) {
+ p_attr->cmd_data[j + 1] = 0;
+ j += 2;
+ break;
+ }
+ if ((((p_attr->cmd_data[j] >> 4) & 0xf) == 0xb) ||
+ (((p_attr->cmd_data[j] >> 4) & 0xf)
+ == 0xd) ||
+ (((p_attr->cmd_data[j] >> 4) & 0xf)
+ == 0xa)) {
+#ifdef CONFIG_AML_LCD_TCON
+ n = p_attr->cmd_data[j] & 0xf;
+ if (((p_attr->cmd_data[j] >> 4) & 0xf)
+ == 0xa) {
+ flag = 2;
+ data_len = tmp_buf[i + 1];
+ offset = tmp_buf[i + 2];
+ } else if (((p_attr->cmd_data[j] >> 4)
+ & 0xf) == 0xb) {
+ flag = 1;
+ } else if (((p_attr->cmd_data[j] >> 4)
+ & 0xf) == 0xd) {
+ flag = 0;
+ }
+ memset(data_buf, 0, LCD_EXTERN_INIT_ON_MAX);
+ ret = handle_tcon_ext_pmu_data(n, flag,
+ data_buf, offset,
+ data_len);
+ if (ret == 0) {
+ /* bin data size valid */
+ if (data_buf[0]) {
+ data_size = data_buf[0];
+ p_attr->cmd_data[j + 1] = data_size;
+ memcpy(&p_attr->cmd_data[j + 2],
+ &data_buf[1], data_size);
+ } else { /* orignal ini data */
+ data_size = tmp_buf[i + 1];
+ p_attr->cmd_data[j + 1] = data_size;
+ for (k = 0; k < data_size; k++) {
+ p_attr->cmd_data[j + 2 + k] =
+ (unsigned char)tmp_buf[i + 2 + k];
+ }
+ }
+ }
+#endif
+ } else { /* orignal ini data */
+ data_size = tmp_buf[i + 1];
+ p_attr->cmd_data[j + 1] = data_size;
+ for (k = 0; k < data_size; k++) {
+ p_attr->cmd_data[j + 2 + k] =
+ (unsigned char)tmp_buf[i + 2 + k];
+ }
+ }
+ j += data_size + 2;
+ i += tmp_buf[i + 1] + 2; /* raw data */
+ }
+ gLcdExtInitOnCnt = j;
+ } else {
+ for (i = 0; i < tmp_cnt; i++)
+ p_attr->cmd_data[i] = tmp_buf[i];
+ gLcdExtInitOnCnt = tmp_cnt;
+ }
+ }
+
+ tmp_off = gLcdExtInitOnCnt;
+ ini_value = IniGetString("lcd_ext_Attr", "init_off", "null");
+ if (model_debug_flag & DEBUG_LCD_EXTERN)
+ ALOGD("%s, init_off is (%s)\n", __func__, ini_value);
+ tmp_cnt = transBufferData(ini_value, tmp_buf);
+ if (tmp_cnt > LCD_EXTERN_INIT_OFF_MAX) {
+ ALOGE("%s: invalid init_off data\n", __func__);
+ p_attr->cmd_data[tmp_off+0] = LCD_EXTERN_INIT_END;
+ p_attr->cmd_data[tmp_off+1] = 0;
+ gLcdExtInitOnCnt = 2;
+ } else {
+ for (i = 0; i < tmp_cnt; i++)
+ p_attr->cmd_data[tmp_off+i] = tmp_buf[i];
+ gLcdExtInitOffCnt = tmp_cnt;
+ }
+
+ if (model_debug_flag & DEBUG_LCD_EXTERN) {
+ ALOGD("%s, init_on_data:\n", __func__);
+ for (i = 0; i < gLcdExtInitOnCnt; i++) {
+ printf(" [%d] = 0x%02x\n", i, p_attr->cmd_data[i]);
+ }
+
+ ALOGD("%s, init_off_data:\n", __func__);
+ for (i = 0; i < gLcdExtInitOffCnt; i++) {
+ ALOGD(" [%d] = 0x%02x\n", i, p_attr->cmd_data[tmp_off+i]);
+ }
+ }
+
+ free(data_buf);
+ data_buf = NULL;
+ return 0;
+}
+
+static int lcd_ext_data_to_buf(unsigned char tmp_buf[], struct lcd_ext_attr_s *p_attr)
+{
+ int i = 0;
+ int tmp_len = 0, tmp_off = 0;
+
+ tmp_off = 0;
+
+ tmp_len = sizeof(struct lcd_ext_header_s);
+ memcpy((void *)(tmp_buf + tmp_off), (void *)(&p_attr->head), tmp_len);
+ tmp_off += tmp_len;
+
+ tmp_len = sizeof(struct lcd_ext_basic_s);
+ memcpy((void *)(tmp_buf + tmp_off), (void *)(&p_attr->basic), tmp_len);
+ tmp_off += tmp_len;
+
+ tmp_len = sizeof(struct lcd_ext_type_s);
+ memcpy((void *)(tmp_buf + tmp_off), (void *)(&p_attr->type), tmp_len);
+ tmp_off += tmp_len;
+
+ tmp_len = gLcdExtInitOnCnt;
+ for (i = 0; i < gLcdExtInitOnCnt; i++)
+ tmp_buf[tmp_off + i] = p_attr->cmd_data[i];
+ tmp_off += tmp_len;
+
+ for (i = 0; i < gLcdExtInitOffCnt; i++)
+ tmp_buf[tmp_off + i] = p_attr->cmd_data[tmp_len+i];
+
+ return 0;
+}
+
+static int handle_lcd_ext_header(struct lcd_ext_attr_s *p_attr)
+{
+ const char *ini_value = NULL;
+ unsigned char *tmp_buf = NULL;
+
+ tmp_buf = (unsigned char *) malloc(CC_MAX_TEMP_BUF_SIZE);
+ if (tmp_buf == NULL) {
+ ALOGE("%s, malloc buffer memory error!!!\n", __func__);
+ return -1;
+ }
+
+ gLcdExtDataCnt = 0;
+ gLcdExtDataCnt += sizeof(struct lcd_ext_header_s);
+ gLcdExtDataCnt += sizeof(struct lcd_ext_basic_s);
+ gLcdExtDataCnt += sizeof(struct lcd_ext_type_s);
+
+ gLcdExtDataCnt += gLcdExtInitOnCnt;
+ gLcdExtDataCnt += gLcdExtInitOffCnt;
+
+ p_attr->head.data_len = gLcdExtDataCnt;
+
+ ini_value = IniGetString("lcd_ext_Attr", "version", "null");
+ if (model_debug_flag & DEBUG_LCD_EXTERN)
+ ALOGD("%s, version is (%s)\n", __func__, ini_value);
+ if (strcmp(ini_value, "null") == 0)
+ p_attr->head.version = 0;
+ else
+ p_attr->head.version = strtoul(ini_value, NULL, 0);
+
+ p_attr->head.rev = 0;
+
+ memset((void *)tmp_buf, 0, CC_MAX_TEMP_BUF_SIZE);
+ lcd_ext_data_to_buf(tmp_buf, p_attr);
+ p_attr->head.crc32 = CalCRC32(0, (tmp_buf + 4), gLcdExtDataCnt - 4);
+
+ if (model_debug_flag & DEBUG_LCD_EXTERN)
+ ALOGD("%s, gLcdExtDataCnt = %d\n", __func__, gLcdExtDataCnt);
+
+ free(tmp_buf);
+ tmp_buf = NULL;
+
+ return 0;
+}
+
+static int handle_bl_basic(struct bl_attr_s *p_attr)
+{
+ const char *ini_value = NULL;
+
+ ini_value = IniGetString("Backlight_Attr", "bl_name", "null");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_name is (%s)\n", __func__, ini_value);
+ strncpy(p_attr->basic.bl_name, ini_value, CC_BL_NAME_LEN_MAX - 1);
+ p_attr->basic.bl_name[CC_BL_NAME_LEN_MAX - 1] = '\0';
+
+ return 0;
+}
+
+static int handle_bl_level(struct bl_attr_s *p_attr)
+{
+ const char *ini_value = NULL;
+
+ ini_value = IniGetString("Backlight_Attr", "bl_level_uboot", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_level_uboot is (%s)\n", __func__, ini_value);
+ p_attr->level.bl_level_uboot = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "bl_level_kernel", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_level_kernel is (%s)\n", __func__, ini_value);
+ p_attr->level.bl_level_kernel = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "bl_level_max", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_level_max is (%s)\n", __func__, ini_value);
+ p_attr->level.bl_level_max = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "bl_level_min", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_level_min is (%s)\n", __func__, ini_value);
+ p_attr->level.bl_level_min = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "bl_level_mid", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_level_mid is (%s)\n", __func__, ini_value);
+ p_attr->level.bl_level_mid = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "bl_level_mid_mapping", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_level_mid_mapping is (%s)\n", __func__, ini_value);
+ p_attr->level.bl_level_mid_mapping = strtoul(ini_value, NULL, 0);
+
+ return 0;
+}
+
+static int handle_bl_method(struct bl_attr_s *p_attr)
+{
+ const char *ini_value = NULL;
+
+ ini_value = IniGetString("Backlight_Attr", "bl_method", "null");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_method is (%s)\n", __func__, ini_value);
+ if (strcmp(ini_value, "BL_CTRL_GPIO") == 0)
+ p_attr->method.bl_method = BL_CTRL_GPIO;
+ else if (strcmp(ini_value, "BL_CTRL_PWM") == 0)
+ p_attr->method.bl_method = BL_CTRL_PWM;
+ else if (strcmp(ini_value, "BL_CTRL_PWM_COMBO") == 0)
+ p_attr->method.bl_method = BL_CTRL_PWM_COMBO;
+ else if (strcmp(ini_value, "BL_CTRL_LOCAL_DIMING") == 0)
+ p_attr->method.bl_method = BL_CTRL_LOCAL_DIMMING;
+ else if (strcmp(ini_value, "BL_CTRL_LOCAL_DIMMING") == 0)
+ p_attr->method.bl_method = BL_CTRL_LOCAL_DIMMING;
+ else if (strcmp(ini_value, "BL_CTRL_EXTERN") == 0)
+ p_attr->method.bl_method = BL_CTRL_EXTERN;
+ else
+ p_attr->method.bl_method = BL_CTRL_MAX;
+
+ ini_value = IniGetString("Backlight_Attr", "bl_en_gpio", "0xff");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_en_gpio is (%s)\n", __func__, ini_value);
+ p_attr->method.bl_en_gpio = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "bl_en_gpio_on", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_en_gpio_on is (%s)\n", __func__, ini_value);
+ p_attr->method.bl_en_gpio_on = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "bl_en_gpio_off", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_en_gpio_off is (%s)\n", __func__, ini_value);
+ p_attr->method.bl_en_gpio_off = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "bl_on_delay", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_on_delay is (%s)\n", __func__, ini_value);
+ p_attr->method.bl_on_delay = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "bl_off_delay", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_off_delay is (%s)\n", __func__, ini_value);
+ p_attr->method.bl_off_delay = strtoul(ini_value, NULL, 0);
+
+ return 0;
+}
+
+static int getPWMMethod(const char *ini_value, int def_val)
+{
+ if (strcmp(ini_value, "BL_PWM_NEGATIVE") == 0)
+ return BL_PWM_NEGATIVE;
+ else if (strcmp(ini_value, "BL_PWM_POSITIVE") == 0)
+ return BL_PWM_POSITIVE;
+ else
+ return def_val;
+}
+
+static int getPWMPortIndVal(const char *ini_value, int def_val)
+{
+ if (strcmp(ini_value, "BL_PWM_A") == 0)
+ return BL_PWM_A;
+ else if (strcmp(ini_value, "BL_PWM_B") == 0)
+ return BL_PWM_B;
+ else if (strcmp(ini_value, "BL_PWM_C") == 0)
+ return BL_PWM_C;
+ else if (strcmp(ini_value, "BL_PWM_D") == 0)
+ return BL_PWM_D;
+ else if (strcmp(ini_value, "BL_PWM_E") == 0)
+ return BL_PWM_E;
+ else if (strcmp(ini_value, "BL_PWM_F") == 0)
+ return BL_PWM_F;
+ else if (strcmp(ini_value, "BL_PWM_VS") == 0)
+ return BL_PWM_VS;
+ else
+ return def_val;
+}
+
+static int handle_bl_pwm(struct bl_attr_s *p_attr)
+{
+ const char *ini_value = NULL;
+
+ ini_value = IniGetString("Backlight_Attr", "pwm_method", "BL_PWM_POSITIVE");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm_method is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm_method = getPWMMethod(ini_value, BL_PWM_POSITIVE);
+
+ ini_value = IniGetString("Backlight_Attr", "pwm_port", "null");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm_port is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm_port = getPWMPortIndVal(ini_value, BL_PWM_MAX);
+
+ ini_value = IniGetString("Backlight_Attr", "pwm_freq", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm_freq is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm_freq = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "pwm_duty_max", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm_duty_max is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm_duty_max = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "pwm_duty_min", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm_duty_min is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm_duty_min = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "pwm_gpio", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm_gpio is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm_gpio = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "pwm_gpio_off", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm_gpio_off is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm_gpio_off = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "pwm2_method", "BL_PWM_POSITIVE");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm2_method is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm2_method = getPWMMethod(ini_value, BL_PWM_POSITIVE);
+
+ ini_value = IniGetString("Backlight_Attr", "pwm2_port", "null");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm2_port is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm2_port = getPWMPortIndVal(ini_value, BL_PWM_MAX);
+
+ ini_value = IniGetString("Backlight_Attr", "pwm2_freq", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm2_freq is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm2_freq = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "pwm2_duty_max", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm2_duty_max is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm2_duty_max = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "pwm2_duty_min", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm2_duty_min is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm2_duty_min = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "pwm2_gpio", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm2_gpio is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm2_gpio = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "pwm2_gpio_off", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm2_gpio_off is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm2_gpio_off = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "pwm_on_delay", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm_on_delay is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm_on_delay = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "pwm_off_delay", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm_off_delay is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm_off_delay = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "pwm_level_max", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm_level_max is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm_level_max = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "pwm_level_min", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm_level_min is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm_level_min = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "pwm2_level_max", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm2_level_max is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm2_level_max = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "pwm2_level_min", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, pwm2_level_min is (%s)\n", __func__, ini_value);
+ p_attr->pwm.pwm2_level_min = strtoul(ini_value, NULL, 0);
+
+ return 0;
+}
+
+static int handle_bl_ldim(struct bl_attr_s *p_attr)
+{
+ const char *ini_value = NULL;
+
+ ini_value = IniGetString("Backlight_Attr", "bl_ldim_row", "1");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_ldim_row is (%s)\n", __func__, ini_value);
+ p_attr->ldim.ldim_row = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "bl_ldim_col", "1");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_ldim_col is (%s)\n", __func__, ini_value);
+ p_attr->ldim.ldim_col = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "bl_ldim_mode", "null");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_ldim_mode is (%s)\n", __func__, ini_value);
+ if (strcmp(ini_value, "LDIM_LR_SIDE") == 0)
+ p_attr->ldim.ldim_mode = LDIM_MODE_LR_SIDE;
+ else if (strcmp(ini_value, "LDIM_TB_SIDE") == 0)
+ p_attr->ldim.ldim_mode = LDIM_MODE_TB_SIDE;
+ else if (strcmp(ini_value, "LDIM_DIRECT") == 0)
+ p_attr->ldim.ldim_mode = LDIM_MODE_DIRECT;
+ else
+ p_attr->ldim.ldim_mode = LDIM_MODE_TB_SIDE;
+
+ ini_value = IniGetString("Backlight_Attr", "bl_ldim_dev_index", "0xff");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_ldim_dev_index is (%s)\n", __func__, ini_value);
+ p_attr->ldim.ldim_dev_index = strtoul(ini_value, NULL, 0);
+
+ p_attr->ldim.ldim_attr_4 = 0;
+ p_attr->ldim.ldim_attr_5 = 0;
+ p_attr->ldim.ldim_attr_6 = 0;
+ p_attr->ldim.ldim_attr_7 = 0;
+ p_attr->ldim.ldim_attr_8 = 0;
+ p_attr->ldim.ldim_attr_9 = 0;
+
+ return 0;
+}
+
+static int handle_bl_custome(struct bl_attr_s *p_attr)
+{
+ const char *ini_value = NULL;
+
+ ini_value = IniGetString("Backlight_Attr", "bl_custome_val_0", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_custome_val_0 is (%s)\n", __func__, ini_value);
+ p_attr->custome.custome_val_0 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "bl_custome_val_1", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_custome_val_1 is (%s)\n", __func__, ini_value);
+ p_attr->custome.custome_val_1 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "bl_custome_val_2", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_custome_val_2 is (%s)\n", __func__, ini_value);
+ p_attr->custome.custome_val_2 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "bl_custome_val_3", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_custome_val_3 is (%s)\n", __func__, ini_value);
+ p_attr->custome.custome_val_3 = strtoul(ini_value, NULL, 0);
+
+ ini_value = IniGetString("Backlight_Attr", "bl_custome_val_4", "0");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, bl_custome_val_4 is (%s)\n", __func__, ini_value);
+ p_attr->custome.custome_val_4 = strtoul(ini_value, NULL, 0);
+
+ return 0;
+}
+
+static int handle_bl_header(struct bl_attr_s *p_attr)
+{
+ const char *ini_value = NULL;
+
+ ini_value = IniGetString("Backlight_Attr", "version", "null");
+ if (model_debug_flag & DEBUG_BACKLIGHT)
+ ALOGD("%s, version is (%s)\n", __func__, ini_value);
+ if (strcmp(ini_value, "null") == 0)
+ p_attr->head.version = 0;
+ else
+ p_attr->head.version = strtoul(ini_value, NULL, 0);
+
+ gBlDataCnt = 0;
+ gBlDataCnt += sizeof(struct bl_header_s);
+ gBlDataCnt += sizeof(struct bl_basic_s);
+ gBlDataCnt += sizeof(struct bl_level_s);
+ gBlDataCnt += sizeof(struct bl_method_s);
+ gBlDataCnt += sizeof(struct bl_pwm_s);
+ if (p_attr->head.version == 2) {
+ gBlDataCnt += sizeof(struct bl_ldim_s);
+ gBlDataCnt += sizeof(struct bl_custome_s);
+ }
+ p_attr->head.data_len = gBlDataCnt;
+
+ p_attr->head.rev = 0;
+ p_attr->head.crc32 = CalCRC32(0, (((unsigned char *)p_attr) + 4), gBlDataCnt - 4);
+
+ return 0;
+}
+
+static int handle_panel_misc(struct panel_misc_s *p_misc)
+{
+ int tmp_val = 0;
+ const char *ini_value = NULL;
+ char buf[64] = {0};
+
+ ini_value = IniGetString("panel_misc", "panel_misc_version", "null");
+ if (model_debug_flag & DEBUG_MISC)
+ ALOGD("%s, panel_misc_version is (%s)\n", __func__, ini_value);
+ if (strcmp(ini_value, "null") == 0) {
+ strcpy(p_misc->version, "V001");
+ } else {
+ tmp_val = strtol(ini_value, NULL, 0);
+ if (tmp_val < 1)
+ tmp_val = 1;
+
+ sprintf(p_misc->version, "V%03d", tmp_val);
+ }
+
+ ini_value = IniGetString("panel_misc", "outputmode2", "null");
+ if (model_debug_flag & DEBUG_MISC)
+ ALOGD("%s, outputmode2 is (%s)\n", __func__, ini_value);
+ if (strcmp(ini_value, "null") == 0) {
+ ini_value = IniGetString("panel_misc", "outputmode", "null");
+ if (model_debug_flag & DEBUG_MISC)
+ ALOGD("%s, outputmode is (%s)\n", __func__, ini_value);
+ if (strcmp(ini_value, "null")) {
+ strncpy(p_misc->outputmode, ini_value,
+ sizeof(p_misc->outputmode) - 1);
+ p_misc->outputmode[sizeof(p_misc->outputmode) - 1]
+ = '\0';
+ snprintf(buf, 63, "env_set outputmode %s", p_misc->outputmode);
+ run_command(buf, 0);
+ }
+ } else {
+ strncpy(p_misc->outputmode, ini_value, 63);
+ snprintf(buf, 63, "env_set outputmode2 %s", p_misc->outputmode);
+ run_command(buf, 0);
+ }
+
+ ini_value = IniGetString("panel_misc", "panel_reverse", "null");
+ if (model_debug_flag & DEBUG_MISC)
+ ALOGD("%s, panel_reverse is (%s)\n", __func__, ini_value);
+ if (strcmp(ini_value, "null") == 0 || strcmp(ini_value, "0") == 0 ||
+ strcmp(ini_value, "false") == 0 || strcmp(ini_value, "no_rev") == 0) {
+ p_misc->panel_reverse = 0;
+ } else if (strcmp(ini_value, "true") == 0 || strcmp(ini_value, "1") == 0 ||
+ strcmp(ini_value, "have_rev") == 0) {
+ p_misc->panel_reverse = 1;
+ } else {
+ p_misc->panel_reverse = 0;
+ }
+
+ if (p_misc->panel_reverse) {
+ run_command("env_set panel_reverse 1", 0);
+ run_command("env_set osd_reverse all,true", 0);
+ run_command("env_set video_reverse 1", 0);
+ } else {
+ run_command("env_set panel_reverse 0", 0);
+ run_command("env_set osd_reverse n", 0);
+ run_command("env_set video_reverse 0", 0);
+ }
+
+ return 0;
+}
+
+#ifdef CONFIG_AML_LCD_TCON
+static int handle_tcon_spi_v0(unsigned char *buff)
+{
+ const char *ini_value = NULL;
+ char str[30];
+ unsigned int null_cnt = 0, block_cnt = 4;
+ unsigned int temp, i, j, n;
+
+ /* header */
+ /* version */
+ temp = 0;
+ buff[8] = temp & 0xff;
+ buff[9] = (temp >> 8) & 0xff;
+ buff[10] = (temp >> 16) & 0xff;
+ buff[11] = (temp >> 24) & 0xff;
+
+ /* block 0: demura_lut */
+ n = 16;
+ ini_value = IniGetString("tcon_spi_Attr", "demura_lut_offset", "null");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, demura_lut_offset is (%s)\n", __func__, ini_value);
+ if (strcmp(ini_value, "null") == 0) {
+ null_cnt++;
+ goto handle_tcon_spi_v0_block_1;
+ }
+ temp = strtoul(ini_value, NULL, 0);
+ for (i = 0; i < 4; i++)
+ buff[n + i] = (temp >> (i * 8)) & 0xff;
+ n += 4;
+
+ ini_value = IniGetString("tcon_spi_Attr", "demura_lut_size", "null");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, demura_lut_size is (%s)\n", __func__, ini_value);
+ if (strcmp(ini_value, "null") == 0) {
+ null_cnt++;
+ goto handle_tcon_spi_v0_block_1;
+ }
+ temp = strtoul(ini_value, NULL, 0);
+ for (i = 0; i < 4; i++)
+ buff[n + i] = (temp >> (i * 8)) & 0xff;
+ n += 4;
+
+ for (j = 0; j < 6; j++) {
+ sprintf(str, "block0_param_%d", j);
+ ini_value = IniGetString("tcon_spi_Attr", str, "0");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, %s is (%s)\n", __func__, str, ini_value);
+ temp = strtoul(ini_value, NULL, 0);
+ for (i = 0; i < 4; i++)
+ buff[n + i] = (temp >> (i * 8)) & 0xff;
+ n += 4;
+ }
+
+handle_tcon_spi_v0_block_1:
+ /* block 1: p_gamma */
+ ini_value = IniGetString("tcon_spi_Attr", "p_gamma_offset", "null");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, p_gamma_offset is (%s)\n", __func__, ini_value);
+ if (strcmp(ini_value, "null") == 0) {
+ null_cnt++;
+ goto handle_tcon_spi_v0_block_2;
+ }
+ temp = strtoul(ini_value, NULL, 0);
+ for (i = 0; i < 4; i++)
+ buff[n + i] = (temp >> (i * 8)) & 0xff;
+ n += 4;
+
+ ini_value = IniGetString("tcon_spi_Attr", "p_gamma_size", "null");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, p_gamma_size is (%s)\n", __func__, ini_value);
+ if (strcmp(ini_value, "null") == 0) {
+ null_cnt++;
+ goto handle_tcon_spi_v0_block_2;
+ }
+ temp = strtoul(ini_value, NULL, 0);
+ for (i = 0; i < 4; i++)
+ buff[n + i] = (temp >> (i * 8)) & 0xff;
+ n += 4;
+
+ for (j = 0; j < 6; j++) {
+ sprintf(str, "block1_param_%d", j);
+ ini_value = IniGetString("tcon_spi_Attr", str, "0");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, %s is (%s)\n", __func__, str, ini_value);
+ temp = strtoul(ini_value, NULL, 0);
+ for (i = 0; i < 4; i++)
+ buff[n + i] = (temp >> (i * 8)) & 0xff;
+ n += 4;
+ }
+
+handle_tcon_spi_v0_block_2:
+ /* block 2: acc_lut */
+ ini_value = IniGetString("tcon_spi_Attr", "acc_lut_offset", "null");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, acc_lut_offset is (%s)\n", __func__, ini_value);
+ if (strcmp(ini_value, "null") == 0) {
+ null_cnt++;
+ goto handle_tcon_spi_v0_block_3;
+ }
+ temp = strtoul(ini_value, NULL, 0);
+ for (i = 0; i < 4; i++)
+ buff[n + i] = (temp >> (i * 8)) & 0xff;
+ n += 4;
+
+ ini_value = IniGetString("tcon_spi_Attr", "acc_lut_size", "null");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, acc_lut_size is (%s)\n", __func__, ini_value);
+ if (strcmp(ini_value, "null") == 0) {
+ null_cnt++;
+ goto handle_tcon_spi_v0_block_3;
+ }
+ temp = strtoul(ini_value, NULL, 0);
+ for (i = 0; i < 4; i++)
+ buff[n + i] = (temp >> (i * 8)) & 0xff;
+ n += 4;
+
+ for (j = 0; j < 6; j++) {
+ sprintf(str, "block2_param_%d", j);
+ ini_value = IniGetString("tcon_spi_Attr", str, "0");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, %s is (%s)\n", __func__, str, ini_value);
+ temp = strtoul(ini_value, NULL, 0);
+ for (i = 0; i < 4; i++)
+ buff[n + i] = (temp >> (i * 8)) & 0xff;
+ n += 4;
+ }
+
+handle_tcon_spi_v0_block_3:
+ /* block 3: auto_flicker */
+ ini_value = IniGetString("tcon_spi_Attr", "auto_flicker_offset", "null");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, auto_flicker_offset is (%s)\n", __func__, ini_value);
+ if (strcmp(ini_value, "null") == 0) {
+ null_cnt++;
+ goto handle_tcon_spi_v0_next;
+ }
+ temp = strtoul(ini_value, NULL, 0);
+ for (i = 0; i < 4; i++)
+ buff[n + i] = (temp >> (i * 8)) & 0xff;
+ n += 4;
+
+ ini_value = IniGetString("tcon_spi_Attr", "auto_flicker_size", "null");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, auto_flicker_size is (%s)\n", __func__, ini_value);
+ if (strcmp(ini_value, "null") == 0) {
+ null_cnt++;
+ goto handle_tcon_spi_v0_next;
+ }
+ temp = strtoul(ini_value, NULL, 0);
+ for (i = 0; i < 4; i++)
+ buff[n + i] = (temp >> (i * 8)) & 0xff;
+ n += 4;
+
+ for (j = 0; j < 6; j++) {
+ sprintf(str, "block3_param_%d", j);
+ ini_value = IniGetString("tcon_spi_Attr", str, "0");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, %s is (%s)\n", __func__, str, ini_value);
+ temp = strtoul(ini_value, NULL, 0);
+ for (i = 0; i < 4; i++)
+ buff[n + i] = (temp >> (i * 8)) & 0xff;
+ n += 4;
+ }
+
+handle_tcon_spi_v0_next:
+ if (null_cnt >= 4) {
+ block_cnt = 0;
+ gLcdTconSpi_cnt = 0;
+ } else {
+ block_cnt = 4;
+ gLcdTconSpi_cnt = (16 + 32 * block_cnt);
+ }
+
+ /* block cnt */
+ buff[12] = block_cnt & 0xff;
+ buff[13] = (block_cnt >> 8) & 0xff;
+ buff[14] = (block_cnt >> 16) & 0xff;
+ buff[15] = (block_cnt >> 24) & 0xff;
+
+ /* data size */
+ buff[4] = gLcdTconSpi_cnt & 0xff;
+ buff[5] = (gLcdTconSpi_cnt >> 8) & 0xff;
+ buff[6] = (gLcdTconSpi_cnt >> 16) & 0xff;
+ buff[7] = (gLcdTconSpi_cnt >> 24) & 0xff;
+
+ /* crc */
+ temp = CalCRC32(0, (buff + 4), gLcdTconSpi_cnt - 4);
+ buff[0] = temp & 0xff;
+ buff[1] = (temp >> 8) & 0xff;
+ buff[2] = (temp >> 16) & 0xff;
+ buff[3] = (temp >> 24) & 0xff;
+
+ return 0;
+}
+
+static int handle_tcon_spi(unsigned char *buff)
+{
+ unsigned char *p;
+ const char *ini_value = NULL;
+ char str[30];
+ unsigned int data_size, block_cnt, param_cnt;
+ unsigned int temp, i, j, k, n;
+
+ /* header */
+ /* version */
+ ini_value = IniGetString("tcon_spi_Attr", "version", "0");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, version is (%s)\n", __func__, ini_value);
+ temp = strtoul(ini_value, NULL, 0);
+ if (temp == 0) {
+ handle_tcon_spi_v0(buff);
+ return 0;
+ }
+
+ /* new data format */
+ /* version */
+ buff[8] = temp & 0xff;
+ buff[9] = (temp >> 8) & 0xff;
+
+ /* block cnt */
+ ini_value = IniGetString("tcon_spi_Attr", "block_cnt", "0");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, block_cnt is (%s)\n", __func__, ini_value);
+ block_cnt = strtoul(ini_value, NULL, 0);
+ buff[14] = block_cnt & 0xff;
+ buff[15] = (block_cnt >> 8) & 0xff;
+
+ p = &buff[16];
+ n = 0;
+ for (i = 0; i < block_cnt; i++) {
+ snprintf(str, 30, "block%d_data_type", i);
+ ini_value = IniGetString("tcon_spi_Attr", str, "0");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, %s is (%s)\n", __func__, str, ini_value);
+ temp = strtoul(ini_value, NULL, 0);
+ p[n] = temp & 0xff;
+ p[n + 1] = (temp >> 8) & 0xff;
+
+ snprintf(str, 30, "block%d_data_index", i);
+ ini_value = IniGetString("tcon_spi_Attr", str, "0xff");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, %s is (%s)\n", __func__, str, ini_value);
+ temp = strtoul(ini_value, NULL, 0);
+ p[n + 2] = temp & 0xff;
+ p[n + 3] = (temp >> 8) & 0xff;
+
+ snprintf(str, 30, "block%d_data_flag", i);
+ ini_value = IniGetString("tcon_spi_Attr", str, "0xff");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, %s is (%s)\n", __func__, str, ini_value);
+ temp = strtoul(ini_value, NULL, 0);
+ p[n + 4] = temp & 0xff;
+ p[n + 5] = (temp >> 8) & 0xff;
+ p[n + 6] = (temp >> 16) & 0xff;
+ p[n + 7] = (temp >> 24) & 0xff;
+
+ snprintf(str, 30, "block%d_spi_data_offset", i);
+ ini_value = IniGetString("tcon_spi_Attr", str, "0");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, %s is (%s)\n", __func__, str, ini_value);
+ temp = strtoul(ini_value, NULL, 0);
+ p[n + 8] = temp & 0xff;
+ p[n + 9] = (temp >> 8) & 0xff;
+ p[n + 10] = (temp >> 16) & 0xff;
+ p[n + 11] = (temp >> 24) & 0xff;
+
+ snprintf(str, 30, "block%d_spi_data_size", i);
+ ini_value = IniGetString("tcon_spi_Attr", str, "0");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, %s is (%s)\n", __func__, str, ini_value);
+ temp = strtoul(ini_value, NULL, 0);
+ p[n + 12] = temp & 0xff;
+ p[n + 13] = (temp >> 8) & 0xff;
+ p[n + 14] = (temp >> 16) & 0xff;
+ p[n + 15] = (temp >> 24) & 0xff;
+
+ snprintf(str, 30, "block%d_param_cnt", i);
+ ini_value = IniGetString("tcon_spi_Attr", str, "0");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, %s is (%s)\n", __func__, str, ini_value);
+ param_cnt = strtoul(ini_value, NULL, 0);
+ p[n + 16] = param_cnt & 0xff;
+ p[n + 17] = (param_cnt >> 8) & 0xff;
+ p[n + 18] = (param_cnt >> 16) & 0xff;
+ p[n + 19] = (param_cnt >> 24) & 0xff;
+
+ /* conversion parameters */
+ k = n + 20;
+ for (j = 0; j < param_cnt; j++) {
+ snprintf(str, 30, "block%d_param_%d", i, j);
+ ini_value = IniGetString("tcon_spi_Attr", str, "0");
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, %s is (%s)\n", __func__, str, ini_value);
+ temp = strtoul(ini_value, NULL, 0);
+ p[k] = temp & 0xff;
+ p[k + 1] = (temp >> 8) & 0xff;
+ p[k + 2] = (temp >> 16) & 0xff;
+ p[k + 3] = (temp >> 24) & 0xff;
+ k += 4;
+ }
+ n += (20 + param_cnt * 4);
+ }
+
+ /* data size */
+ data_size = 16 + n;
+ buff[4] = data_size & 0xff;
+ buff[5] = (data_size >> 8) & 0xff;
+ buff[6] = (data_size >> 16) & 0xff;
+ buff[7] = (data_size >> 24) & 0xff;
+ gLcdTconSpi_cnt = data_size;
+
+ /* crc */
+ temp = CalCRC32(0, (buff + 4), gLcdTconSpi_cnt - 4);
+ buff[0] = temp & 0xff;
+ buff[1] = (temp >> 8) & 0xff;
+ buff[2] = (temp >> 16) & 0xff;
+ buff[3] = (temp >> 24) & 0xff;
+
+ return 0;
+}
+#endif
+
+static int parse_panel_ini(const char *file_name, struct lcd_attr_s *lcd_attr,
+ struct lcd_ext_attr_s *ext_attr,
+ struct bl_attr_s *bl_attr,
+ struct panel_misc_s *misc_attr,
+ unsigned char *tcon_spi_buf)
+{
+
+ memset((void *)lcd_attr, 0, sizeof(struct lcd_attr_s));
+ memset((void *)bl_attr, 0, sizeof(struct bl_attr_s));
+
+ IniParserInit();
+
+ if (IniParseFile(file_name) < 0) {
+ ALOGE("%s, ini load file error!\n", __func__);
+ IniParserUninit();
+ return -1;
+ }
+
+ // handle integrity flag
+ if (handle_integrity_flag() < 0) {
+ ALOGE("%s, handle_integrity_flag error!\n", __func__);
+ IniParserUninit();
+ return -1;
+ }
+
+ /* handle lcd attr */
+ handle_lcd_basic(lcd_attr);
+ handle_lcd_timming(lcd_attr);
+ handle_lcd_customer(lcd_attr);
+ handle_lcd_interface(lcd_attr);
+ handle_lcd_pwr(lcd_attr);
+ handle_lcd_header(lcd_attr);
+
+ if (((lcd_attr->basic.lcd_type) == LCD_MLVDS) ||
+ ((lcd_attr->basic.lcd_type) == LCD_P2P))
+ g_lcd_tcon_valid = 1;
+ else
+ g_lcd_tcon_valid = 0;
+
+#ifdef CONFIG_AML_LCD_TCON
+ /*should ready tcon path here, for lcd_ext usage */
+ if (g_lcd_tcon_valid)
+ handle_tcon_path();
+#endif
+
+ // handle lcd extern attr
+ handle_lcd_ext_basic(ext_attr);
+ handle_lcd_ext_type(ext_attr);
+ handle_lcd_ext_cmd_data(ext_attr);
+ handle_lcd_ext_header(ext_attr);
+
+ // handle bl attr
+ handle_bl_basic(bl_attr);
+ handle_bl_level(bl_attr);
+ handle_bl_method(bl_attr);
+ handle_bl_pwm(bl_attr);
+ handle_bl_ldim(bl_attr);
+ handle_bl_custome(bl_attr);
+ handle_bl_header(bl_attr);
+
+ handle_panel_misc(misc_attr);
+
+#ifdef CONFIG_AML_LCD_TCON
+ if (g_lcd_tcon_valid)
+ handle_tcon_spi(tcon_spi_buf);
+ else
+ gLcdTconSpi_cnt = 0;
+#endif
+
+ IniParserUninit();
+
+ return 0;
+}
+
+#ifdef CONFIG_AML_LCD_TCON
+static int read_bin_file(const char *file_name, unsigned long int max_buf_len)
+{
+ int size;
+
+ BinFileInit();
+
+ size = ReadBinFile(file_name);
+ if (size < 0) {
+ ALOGE("%s, load bin file error!\n", __func__);
+ BinFileUninit();
+ return 0;
+ }
+
+ if (size > max_buf_len) {
+ ALOGE("%s, bin file size out of support!\n", __func__);
+ BinFileUninit();
+ return 0;
+ }
+
+ return size;
+}
+
+static int read_bin_file_with_header(const char *file_name, unsigned long int max_buf_len)
+{
+ unsigned char buf[16];
+ int bin_size, data_size = 0;
+
+ BinFileInit();
+
+ bin_size = ReadBinFile(file_name);
+ if (bin_size < 64) {
+ ALOGE("%s, load bin file error!\n", __func__);
+ BinFileUninit();
+ return 0;
+ }
+
+ GetBinData(buf, 16);
+ data_size = (buf[8] | (buf[9] << 8) |
+ (buf[10] << 16) | (buf[11] << 24));
+ if ((data_size > bin_size) || (data_size < 64)) {
+ ALOGE("%s, bin file size less than expectation!\n", __func__);
+ BinFileUninit();
+ return 0;
+ }
+ if (data_size > max_buf_len) {
+ ALOGE("%s, bin file size out of support!\n", __func__);
+ BinFileUninit();
+ return 0;
+ }
+
+ return data_size;
+}
+
+static int handle_tcon_bin(void)
+{
+ int tmp_len = 0;
+ unsigned int size = 0;
+ unsigned char *tmp_buf = NULL;
+ unsigned char *tcon_buf = NULL;
+ char *file_name;
+ unsigned int bypass, header, data_crc32, temp_crc32;
+ int tmp;
+
+ tmp = env_get_ulong("model_tcon_bypass", 10, 0xffff);
+ if (tmp != 0xffff) {
+ bypass = tmp;
+ if (bypass) {
+ ALOGI("model_tcon_bypass\n");
+ return 0;
+ }
+ }
+
+ header = env_get_ulong("model_tcon_bin_header", 10, 0);
+
+ file_name = env_get("model_tcon");
+ if (!file_name) {
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s, no model_tcon path\n", __func__);
+ return 0;
+ }
+
+ tmp_buf = (unsigned char *)malloc(CC_MAX_TCON_BIN_SIZE);
+ if (!tmp_buf) {
+ ALOGE("%s, malloc buffer memory error!!!\n", __func__);
+ return -1;
+ }
+
+ // start handle tcon bin name
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s: model_tcon: %s\n", __func__, file_name);
+ if (!iniIsFileExist(file_name)) {
+ ALOGE("%s, file name \"%s\" not exist.\n", __func__, file_name);
+ free(tmp_buf);
+ tmp_buf = NULL;
+ return -1;
+ }
+
+ if (header)
+ size = read_bin_file_with_header(file_name, CC_MAX_TCON_BIN_SIZE);
+ else
+ size = read_bin_file(file_name, CC_MAX_TCON_BIN_SIZE);
+ if (size == 0) {
+ free(tmp_buf);
+ tmp_buf = NULL;
+ return -1;
+ }
+
+ GetBinData(tmp_buf, size);
+ if (header) {
+ data_crc32 = tmp_buf[0] | (tmp_buf[1] << 8) |
+ (tmp_buf[2] << 16) | (tmp_buf[3] << 24);
+ temp_crc32 = CalCRC32(0, &tmp_buf[4], (size - 4));
+ if (data_crc32 != temp_crc32) {
+ free(tmp_buf);
+ tmp_buf = NULL;
+ if (model_debug_flag & DEBUG_TCON) {
+ ALOGE("%s, tcon bin crc error! raw:0x%08x, temp:0x%08x\n",
+ __func__, data_crc32, temp_crc32);
+ } else {
+ ALOGE("%s, tcon bin crc error!!!\n", __func__);
+ }
+ return -1;
+ }
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s: load tcon bin with header\n", __func__);
+ } else {
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s: load tcon bin\n", __func__);
+ }
+
+ gLcdTconDataCnt = size;
+ tcon_buf = (unsigned char *)malloc(size);
+ if (!tcon_buf) {
+ free(tmp_buf);
+ tmp_buf = NULL;
+ ALOGE("%s, malloc buffer memory error!!!\n", __func__);
+ return -1;
+ }
+ memcpy(tcon_buf, tmp_buf, size);
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s: bin_size=0x%x\n", __func__, size);
+
+ BinFileUninit();
+
+ // start handle lcd_tcon param
+ memset((void *)tmp_buf, 0, CC_MAX_TCON_BIN_SIZE);
+ tmp_len = ReadTconBinParam(tmp_buf);
+ //ALOGD("%s, start check lcd_tcon param data (0x%x).\n", __func__, tmp_len);
+ if (check_param_valid(1, gLcdTconDataCnt, tcon_buf, tmp_len, tmp_buf) ==
+ CC_PARAM_CHECK_ERROR_NEED_UPDATE_PARAM) {
+ ALOGD("%s, check tcon bin data error (0x%x), save tcon bin data.\n",
+ __func__, tmp_len);
+ SaveTconBinParam(gLcdTconDataCnt, tcon_buf);
+ }
+ // end handle lcd_tcon param
+
+ free(tmp_buf);
+ tmp_buf = NULL;
+ free(tcon_buf);
+ tcon_buf = NULL;
+
+ return 0;
+}
+
+static int handle_tcon_ext_pmu_data(int index, int flag, unsigned char *buf,
+ unsigned int offset, unsigned int data_len)
+{
+ char *file_name, str[2][30];
+ unsigned int data_size = 0, i, file_find = 0;
+ unsigned char *bin_buf = NULL;
+
+ if (!buf) {
+ ALOGE("%s, buf is null\n", __func__);
+ return -1;
+ }
+ buf[0] = 0; /* init invalid data */
+ i = 0;
+
+ if (index >= 4) {
+ ALOGE("%s, invalid index %d\n", __func__, index);
+ return -1;
+ }
+
+ sprintf(str[0], "model_tcon_ext_b%d_spi", index);
+ sprintf(str[1], "model_tcon_ext_b%d", index);
+ while (i < 2) {
+ file_name = env_get(str[i]);
+ if (file_name == NULL) {
+ if (model_debug_flag & DEBUG_NORMAL)
+ ALOGD("%s: no %s path\n", __func__, str[i]);
+ } else {
+ if (iniIsFileExist(file_name)) {
+ if (model_debug_flag & DEBUG_NORMAL)
+ ALOGD("%s: %s: %s\n", __func__, str[i], file_name);
+ file_find = 1;
+ break;
+ }
+ if (model_debug_flag & DEBUG_NORMAL) {
+ ALOGE("%s: %s: \"%s\" not exist.\n",
+ __func__, str[i], file_name);
+ }
+ }
+ i++;
+ }
+ if (file_find == 0)
+ return -1;
+
+ data_size = read_bin_file(file_name, LCD_EXTERN_INIT_ON_MAX);
+ if (data_size == 0) {
+ ALOGE("%s, %s data_size %d error!\n", __func__, str[i], data_size);
+ return -1;
+ }
+ if (data_size > LCD_EXTERN_INIT_ON_MAX) {
+ ALOGE("%s, %s data_size %d out of support(max %d)!\n",
+ __func__, str[i], data_size, LCD_EXTERN_INIT_ON_MAX);
+ return -1;
+ }
+
+ switch (flag) {
+ case 0:
+ buf[0] = data_size;
+ GetBinData(&buf[1], data_size);
+ break;
+ case 1: /* data with reg addr auto fill */
+ buf[0] = (data_size + 1); /* data size include reg start */
+ buf[1] = 0x00; /* reg start */
+ GetBinData(&buf[2], data_size);
+ break;
+ case 2:
+ if (data_size < (offset + data_len - 1)) {
+ ALOGE("%s, %s suspend size %d out of data_size(%d)!\n",
+ __func__, str[i], (offset + data_len - 1),
+ data_size);
+ return -1;
+ }
+
+ bin_buf = (unsigned char *)malloc(data_size);
+ if (bin_buf == NULL) {
+ ALOGE("%s, malloc buffer memory error!!!\n", __func__);
+ return -1;
+ }
+ buf[0] = data_len;
+ buf[1] = offset;
+ GetBinData(bin_buf, data_size);
+ memcpy(&buf[2], &bin_buf[offset], data_len - 1);
+ free(bin_buf);
+ break;
+ default:
+ break;
+ }
+
+ if (model_debug_flag & DEBUG_LCD_EXTERN) {
+ ALOGD("%s: %s:\n", __func__, str[i]);
+ for (i = 0; i < (buf[0] + 1); i++)
+ printf(" 0x%02x", buf[i]);
+ printf("\n");
+ }
+
+ if (model_debug_flag & DEBUG_NORMAL)
+ ALOGD("%s %s finish\n", __func__, str[i]);
+
+ BinFileUninit();
+
+ return 0;
+}
+
+#define TCON_VAC_SET_PARAM_NUM 3
+#define TCON_VAC_LUT_PARAM_NUM 256
+int handle_tcon_vac(unsigned char *vac_data, unsigned int vac_mem_size)
+{
+ int i, n, tmp_cnt, len;
+ char *file_name;
+ const char *ini_value = NULL;
+ unsigned int tmp_buf[512];
+ unsigned int data_cnt = 0;
+
+ file_name = env_get("model_tcon_vac");
+ if (file_name == NULL) {
+ if (model_debug_flag & DEBUG_NORMAL)
+ ALOGD("%s, no model_tcon_vac path\n", __func__);
+ return -1;
+ }
+
+ if (model_debug_flag & DEBUG_NORMAL)
+ ALOGD("%s: model_tcon_vac: %s\n", __func__, file_name);
+ if (!iniIsFileExist(file_name)) {
+ ALOGE("%s, file name \"%s\" not exist.\n", __func__, file_name);
+ return -1;
+ }
+
+ if ((vac_data == NULL) || (!vac_mem_size)) {
+ ALOGE("%s, buffer memory or data size error!!!\n", __func__);
+ return -1;
+ }
+
+ IniParserInit();
+
+ if (IniParseFile(file_name) < 0) {
+ ALOGE("%s, ini load file error!\n", __func__);
+ IniParserUninit();
+ free(vac_data);
+ vac_data = NULL;
+ return -1;
+ }
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("vac_data addr: 0x%p\n", vac_data);
+
+ n = 8;
+ len = TCON_VAC_SET_PARAM_NUM;
+
+ ini_value = IniGetString("lcd_tcon_vac", "vac_set", "null");
+ tmp_cnt = transBufferData(ini_value, tmp_buf);
+ data_cnt = tmp_cnt;
+
+ if ((tmp_cnt > CC_MAX_TCON_VAC_SIZE) || (tmp_cnt < len)) {
+ ALOGE("%s: invalid vac_set data cnt %d\n", __func__, tmp_cnt);
+ return -1;
+ }
+ if ((data_cnt * 2) > vac_mem_size) {
+ ALOGE("data size %d is out of memory size %d (data_cnt=%d)\n",
+ (data_cnt * 2), vac_mem_size, data_cnt);
+ return -1;
+ }
+ for (i = 0; i < len; i++) {
+ vac_data[n+i*2] = tmp_buf[i] & 0xff;
+ vac_data[n+i*2+1] = (tmp_buf[i] >> 8) & 0xff;
+ if (model_debug_flag & DEBUG_TCON) {
+ ALOGD("vac_set: 0x%02x, 0x%02x; tmp_buf: 0x%04x\n",
+ vac_data[n+i*2], vac_data[n+i*2+1],
+ tmp_buf[i]);
+ }
+ }
+
+ len = TCON_VAC_LUT_PARAM_NUM;
+
+ ini_value = IniGetString("lcd_tcon_vac", "vac_ramt1", "null");
+ tmp_cnt = transBufferData(ini_value, tmp_buf);
+ data_cnt += tmp_cnt;
+ if ((tmp_cnt > CC_MAX_TCON_VAC_SIZE) || (tmp_cnt < len)) {
+ ALOGE("%s: invalid vac_ramt1 data cnt %d\n", __func__, tmp_cnt);
+ return -1;
+ }
+ if ((data_cnt * 2) > vac_mem_size) {
+ ALOGE("data size %d is out of memory size %d (data_cnt=%d)\n",
+ (data_cnt * 2), vac_mem_size, data_cnt);
+ return -1;
+ }
+ n += (TCON_VAC_SET_PARAM_NUM * 2);
+ for (i = 0; i < len; i++) {
+ vac_data[n+i*2] = tmp_buf[i] & 0xff;
+ vac_data[n+i*2+1] = (tmp_buf[i] >> 8) & 0xff;
+ if ((model_debug_flag & DEBUG_TCON) && (i < 30)) {
+ ALOGD("vac_ramt1_data: 0x%02x, 0x%02x; tmp_buf: 0x%04x\n",
+ vac_data[n+i*2], vac_data[n+i*2+1],
+ tmp_buf[i]);
+ }
+ }
+
+ ini_value = IniGetString("lcd_tcon_vac", "vac_ramt2", "null");
+ tmp_cnt = transBufferData(ini_value, tmp_buf);
+ data_cnt += tmp_cnt;
+ if ((tmp_cnt > CC_MAX_TCON_VAC_SIZE) || (tmp_cnt < len)) {
+ ALOGE("%s: invalid vac_ramt2 data cnt %d\n", __func__, tmp_cnt);
+ return -1;
+ }
+ if ((data_cnt * 2) > vac_mem_size) {
+ ALOGE("data size %d is out of memory size %d (data_cnt=%d)\n",
+ (data_cnt * 2), vac_mem_size, data_cnt);
+ return -1;
+ }
+ n += (len * 2);
+ for (i = 0; i < len; i++) {
+ vac_data[n+i*2] = tmp_buf[i] & 0xff;
+ vac_data[n+i*2+1] = (tmp_buf[i] >> 8) & 0xff;
+ if ((model_debug_flag & DEBUG_TCON) && (i < 30)) {
+ ALOGD("vac_ramt2_data: 0x%02x, 0x%02x; tmp_buf: 0x%04x\n",
+ vac_data[n+i*2], vac_data[n+i*2+1],
+ tmp_buf[i]);
+ }
+ }
+
+ ini_value = IniGetString("lcd_tcon_vac", "vac_ramt3_1", "null");
+ tmp_cnt = transBufferData(ini_value, tmp_buf);
+ data_cnt += tmp_cnt;
+ if ((tmp_cnt > CC_MAX_TCON_VAC_SIZE) || (tmp_cnt < len)) {
+ ALOGE("%s: invalid vac_ramt3_1 data cnt %d\n", __func__, tmp_cnt);
+ return -1;
+ }
+ if ((data_cnt * 2) > vac_mem_size) {
+ ALOGE("data size %d is out of memory size %d (data_cnt=%d)\n",
+ (data_cnt * 2), vac_mem_size, data_cnt);
+ return -1;
+ }
+ n += (len * 2);
+ for (i = 0; i < len; i++) {
+ vac_data[n+i*2] = tmp_buf[i] & 0xff;
+ vac_data[n+i*2+1] = (tmp_buf[i] >> 8) & 0xff;
+ if ((model_debug_flag & DEBUG_TCON) && (i < 30)) {
+ ALOGD("vac_ramt3_1_data: 0x%02x, 0x%02x; tmp_buf: 0x%04x\n",
+ vac_data[n+i*2], vac_data[n+i*2+1],
+ tmp_buf[i]);
+ }
+ }
+
+ ini_value = IniGetString("lcd_tcon_vac", "vac_ramt3_2", "null");
+ tmp_cnt = transBufferData(ini_value, tmp_buf);
+ data_cnt += tmp_cnt;
+ if ((tmp_cnt > CC_MAX_TCON_VAC_SIZE) || (tmp_cnt < len)) {
+ ALOGE("%s: invalid vac_ramt3_2 data cnt %d\n", __func__, tmp_cnt);
+ return -1;
+ }
+ if ((data_cnt * 2) > vac_mem_size) {
+ ALOGE("data size %d is out of memory size %d (data_cnt=%d)\n",
+ (data_cnt * 2), vac_mem_size, data_cnt);
+ return -1;
+ }
+ n += (len * 2);
+ for (i = 0; i < len; i++) {
+ vac_data[n+i*2] = tmp_buf[i] & 0xff;
+ vac_data[n+i*2+1] = (tmp_buf[i] >> 8) & 0xff;
+ if ((model_debug_flag & DEBUG_TCON) && (i < 30)) {
+ ALOGD("vac_ramt3_2_data: 0x%02x, 0x%02x; tmp_buf: 0x%04x\n",
+ vac_data[n+i*2], vac_data[n+i*2+1],
+ tmp_buf[i]);
+ }
+ }
+
+ ini_value = IniGetString("lcd_tcon_vac", "vac_ramt3_3", "null");
+ tmp_cnt = transBufferData(ini_value, tmp_buf);
+ data_cnt += tmp_cnt;
+ if ((data_cnt > CC_MAX_TCON_VAC_SIZE) || (tmp_cnt < len)) {
+ ALOGE("%s: invalid vac_ramt3_3 data cnt %d\n", __func__, tmp_cnt);
+ return -1;
+ }if (data_cnt > vac_mem_size) {
+ ALOGE("data size %d is out of memory size %d (data_cnt=%d)\n",
+ (data_cnt * 2), vac_mem_size, data_cnt);
+ return -1;
+ }
+ n += (len * 2);
+ for (i = 0; i < len; i++) {
+ vac_data[n+i*2] = tmp_buf[i] & 0xff;
+ vac_data[n+i*2+1] = (tmp_buf[i] >> 8) & 0xff;
+ if ((model_debug_flag & DEBUG_TCON) && (i < 30)) {
+ ALOGD("vac_ramt3_3_data: 0x%02x, 0x%02x; tmp_buf: 0x%04x\n",
+ vac_data[n+i*2], vac_data[n+i*2+1],
+ tmp_buf[i]);
+ }
+ }
+
+ ini_value = IniGetString("lcd_tcon_vac", "vac_ramt3_4", "null");
+ tmp_cnt = transBufferData(ini_value, tmp_buf);
+ data_cnt += tmp_cnt;
+ if ((tmp_cnt > CC_MAX_TCON_VAC_SIZE) || (tmp_cnt < len)) {
+ ALOGE("%s: invalid vac_ramt3_4 data cnt %d\n", __func__, tmp_cnt);
+ return -1;
+ }
+ if (data_cnt > vac_mem_size) {
+ ALOGE("data size %d is out of memory size %d (data_cnt=%d)\n",
+ (data_cnt * 2), vac_mem_size, data_cnt);
+ return -1;
+ }
+ n += (len * 2);
+ for (i = 0; i < len; i++) {
+ vac_data[n+i*2] = tmp_buf[i] & 0xff;
+ vac_data[n+i*2+1] = (tmp_buf[i] >> 8) & 0xff;
+ if ((model_debug_flag & DEBUG_TCON) && (i < 30)) {
+ ALOGD("vac_ramt3_4_data: 0x%02x, 0x%02x; tmp_buf: 0x%04x\n",
+ vac_data[n+i*2], vac_data[n+i*2+1],
+ tmp_buf[i]);
+ }
+ }
+
+ ini_value = IniGetString("lcd_tcon_vac", "vac_ramt3_5", "null");
+ tmp_cnt = transBufferData(ini_value, tmp_buf);
+ data_cnt += tmp_cnt;
+ if ((tmp_cnt > CC_MAX_TCON_VAC_SIZE) || (tmp_cnt < len)) {
+ ALOGE("%s: invalid vac_ramt3_5 data cnt %d\n", __func__, tmp_cnt);
+ return -1;
+ }if (data_cnt > vac_mem_size) {
+ ALOGE("data size %d is out of memory size %d (data_cnt=%d)\n",
+ (data_cnt * 2), vac_mem_size, data_cnt);
+ return -1;
+ }
+ n += (len * 2);
+ for (i = 0; i < len; i++) {
+ vac_data[n+i*2] = tmp_buf[i] & 0xff;
+ vac_data[n+i*2+1] = (tmp_buf[i] >> 8) & 0xff;
+ if ((model_debug_flag & DEBUG_TCON) && (i < 30)) {
+ ALOGD("vac_ramt3_5_data: 0x%02x, 0x%02x; tmp_buf: 0x%04x\n",
+ vac_data[n+i*2], vac_data[n+i*2+1],
+ tmp_buf[i]);
+ }
+ }
+
+ ini_value = IniGetString("lcd_tcon_vac", "vac_ramt3_6", "null");
+ tmp_cnt = transBufferData(ini_value, tmp_buf);
+ data_cnt += tmp_cnt;
+ if ((tmp_cnt > CC_MAX_TCON_VAC_SIZE) || (tmp_cnt < len)) {
+ ALOGE("%s: invalid vac_ramt3_6 data cnt %d\n", __func__, tmp_cnt);
+ return -1;
+ }
+ if (data_cnt > vac_mem_size) {
+ ALOGE("data size %d is out of memory size %d (data_cnt=%d)\n",
+ (data_cnt * 2), vac_mem_size, data_cnt);
+ return -1;
+ }
+ n += (len * 2);
+ for (i = 0; i < len; i++) {
+ vac_data[n+i*2] = tmp_buf[i] & 0xff;
+ vac_data[n+i*2+1] = (tmp_buf[i] >> 8) & 0xff;
+ if ((model_debug_flag & DEBUG_TCON) && (i < 30)) {
+ ALOGD("vac_ramt3_6_data: 0x%02x, 0x%02x; tmp_buf: 0x%04x\n",
+ vac_data[n+i*2], vac_data[n+i*2+1],
+ tmp_buf[i]);
+ }
+ }
+
+ /*add check data: total_size(4byte) + crc(4byte) +
+ *crc todo
+ */
+ vac_data[0] = data_cnt & 0xff;
+ vac_data[1] = (data_cnt >> 8) & 0xff;
+ vac_data[2] = (data_cnt >> 16) & 0xff;
+ vac_data[3] = (data_cnt >> 24) & 0xff;
+
+ vac_data[4] = model_data_checksum(&vac_data[8], data_cnt);
+ vac_data[5] = model_data_lrc(&vac_data[8], data_cnt);
+ vac_data[6] = 0x55;
+ vac_data[7] = 0xaa;
+
+ if (model_debug_flag & DEBUG_NORMAL)
+ ALOGD("%s finish\n", __func__);
+
+ IniParserUninit();
+ return 0;
+}
+
+int handle_tcon_demura_set(unsigned char *demura_set_data,
+ unsigned int demura_set_size)
+{
+ unsigned long int bin_size;
+ char *file_name;
+ int n;
+
+ file_name = env_get("model_tcon_demura_set");
+ if (file_name == NULL) {
+ if (model_debug_flag & DEBUG_NORMAL)
+ ALOGD("%s, no model_tcon_demura_set path\n", __func__);
+ return -1;
+ }
+
+ if ((demura_set_data == NULL) || (!demura_set_size)) {
+ ALOGE("%s, buffer or size error!!!\n", __func__);
+ return -1;
+ }
+
+ if (model_debug_flag & DEBUG_NORMAL)
+ ALOGD("%s: model_tcon_demura_set: %s\n", __func__, file_name);
+ if (!iniIsFileExist(file_name)) {
+ ALOGE("%s, file name \"%s\" not exist.\n", __func__, file_name);
+ return -1;
+ }
+
+ bin_size = read_bin_file(file_name, CC_MAX_TCON_DEMURA_SET_SIZE);
+ if (!bin_size || (bin_size > demura_set_size)) {
+ ALOGE("%s, bin_size 0x%lx error!(memory_size 0x%x)\n",
+ __func__, bin_size, demura_set_size);
+ return -1;
+ }
+
+ n = 8;
+ GetBinData(&demura_set_data[n], bin_size);
+
+ demura_set_data[0] = bin_size & 0xff;
+ demura_set_data[1] = (bin_size >> 8) & 0xff;
+ demura_set_data[2] = (bin_size >> 16) & 0xff;
+ demura_set_data[3] = (bin_size >> 24) & 0xff;
+
+ demura_set_data[4] = model_data_checksum(&demura_set_data[8], bin_size);
+ demura_set_data[5] = model_data_lrc(&demura_set_data[8], bin_size);
+ demura_set_data[6] = 0x55;
+ demura_set_data[7] = 0xaa;
+
+ if (model_debug_flag & DEBUG_NORMAL)
+ ALOGD("%s finish\n", __func__);
+
+ BinFileUninit();
+
+ return 0;
+}
+
+int handle_tcon_demura_lut(unsigned char *demura_lut_data,
+ unsigned int demura_lut_size)
+{
+ unsigned long int bin_size;
+ char *file_name;
+ int n;
+
+ file_name = env_get("model_tcon_demura_lut");
+ if (file_name == NULL) {
+ if (model_debug_flag & DEBUG_NORMAL)
+ ALOGD("%s, no model_tcon_demura_lut path\n", __func__);
+ return -1;
+ }
+
+ if ((demura_lut_data == NULL) || (!demura_lut_size)) {
+ ALOGE("%s, buffer memory or size error!!!\n", __func__);
+ return -1;
+ }
+
+ if (model_debug_flag & DEBUG_NORMAL)
+ ALOGD("%s: model_tcon_demura_lut: %s\n", __func__, file_name);
+ if (!iniIsFileExist(file_name)) {
+ ALOGE("%s, file name \"%s\" not exist.\n", __func__, file_name);
+ return -1;
+ }
+
+ bin_size = read_bin_file(file_name, CC_MAX_TCON_DEMURA_LUT_SIZE);
+ if (!bin_size || (bin_size > demura_lut_size)) {
+ ALOGE("%s, bin_size 0x%lx error!(memory_size 0x%x)\n",
+ __func__, bin_size, demura_lut_size);
+ return -1;
+ }
+
+ n = 8;
+ GetBinData(&demura_lut_data[n], bin_size);
+
+ demura_lut_data[0] = bin_size & 0xff;
+ demura_lut_data[1] = (bin_size >> 8) & 0xff;
+ demura_lut_data[2] = (bin_size >> 16) & 0xff;
+ demura_lut_data[3] = (bin_size >> 24) & 0xff;
+
+ demura_lut_data[4] = model_data_checksum(&demura_lut_data[8], bin_size);
+ demura_lut_data[5] = model_data_lrc(&demura_lut_data[8], bin_size);
+ demura_lut_data[6] = 0x55;
+ demura_lut_data[7] = 0xaa;
+
+ if (model_debug_flag)
+ ALOGD("%s finish, bin_size = 0x%lx\n", __func__, bin_size);
+
+ BinFileUninit();
+
+ return 0;
+}
+
+int handle_tcon_acc_lut(unsigned char *acc_lut_data, unsigned int acc_lut_size)
+{
+ unsigned long int bin_size;
+ char *file_name;
+ int n;
+
+ file_name = env_get("model_tcon_acc_lut");
+ if (!file_name) {
+ if (model_debug_flag & DEBUG_NORMAL)
+ ALOGD("%s, no model_tcon_acc_lut path\n", __func__);
+ return -1;
+ }
+
+ if ((!acc_lut_data) || (acc_lut_size == 0)) {
+ ALOGE("%s, buffer memory or size error!!!\n", __func__);
+ return -1;
+ }
+
+ if (!iniIsFileExist(file_name)) {
+ ALOGE("%s, model_tcon_acc_lut file name \"%s\" not exist.\n",
+ __func__, file_name);
+ return -1;
+ }
+ if (model_debug_flag & DEBUG_NORMAL)
+ ALOGD("%s: model_tcon_acc_lut: %s\n", __func__, file_name);
+
+ bin_size = read_bin_file(file_name, CC_MAX_TCON_ACC_LUT_SIZE);
+ if (!bin_size || (bin_size > acc_lut_size)) {
+ ALOGE("%s, bin_size 0x%lx error!(memory_size 0x%x)\n",
+ __func__, bin_size, acc_lut_size);
+ return -1;
+ }
+
+ n = 8;
+ GetBinData(&acc_lut_data[n], bin_size);
+
+ acc_lut_data[0] = bin_size & 0xff;
+ acc_lut_data[1] = (bin_size >> 8) & 0xff;
+ acc_lut_data[2] = (bin_size >> 16) & 0xff;
+ acc_lut_data[3] = (bin_size >> 24) & 0xff;
+
+ acc_lut_data[4] = model_data_checksum(&acc_lut_data[8], bin_size);
+ acc_lut_data[5] = model_data_lrc(&acc_lut_data[8], bin_size);
+ acc_lut_data[6] = 0x55;
+ acc_lut_data[7] = 0xaa;
+
+ if (model_debug_flag)
+ ALOGD("%s finish, bin_size = 0x%lx\n", __func__, bin_size);
+
+ BinFileUninit();
+
+ return 0;
+}
+
+int handle_tcon_data_load(unsigned char **buf, unsigned int index)
+{
+ unsigned char *data_buf;
+ unsigned long int bin_size, new_size;
+ unsigned int data_size;
+ unsigned int data_crc32, temp_crc32;
+ char *file_name;
+
+ if (!buf) {
+ ALOGE("%s, buf is null\n", __func__);
+ return -1;
+ }
+
+ file_name = handle_tcon_path_file_name_get(index);
+ if (!file_name)
+ return -1;
+ if (!iniIsFileExist(file_name)) {
+ ALOGE("%s, tcon_data[%d] file name \"%s\" not exist.\n",
+ __func__, index, file_name);
+ return -1;
+ }
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s: tcon_data[%d] file name: %s\n", __func__, index, file_name);
+
+ bin_size = read_bin_file(file_name, CC_MAX_DATA_SIZE);
+ if (bin_size == 0) {
+ ALOGE("%s, bin_size 0x%lx error!\n", __func__, bin_size);
+ return -1;
+ }
+
+ data_buf = buf[index];
+ if (data_buf) { /* already exist for reload */
+ data_size = data_buf[8] |
+ (data_buf[9] << 8) |
+ (data_buf[10] << 16) |
+ (data_buf[11] << 24);
+ if (data_size >= bin_size) {
+ memset(data_buf, 0, data_size);
+ goto handle_tcon_data_load_next;
+ }
+ free(data_buf);
+ buf[index] = NULL;
+ }
+ /* note: all the tcon data buf size must align to 32byte */
+ new_size = handle_tcon_char_data_size_align(bin_size);
+ data_buf = (unsigned char *)malloc(new_size);
+ if (!data_buf) {
+ ALOGE("%s: Not enough memory\n", __func__);
+ return -1;
+ }
+ memset(data_buf, 0, new_size);
+ buf[index] = data_buf;
+
+handle_tcon_data_load_next:
+ GetBinData(data_buf, bin_size);
+ data_size = data_buf[8] |
+ (data_buf[9] << 8) |
+ (data_buf[10] << 16) |
+ (data_buf[11] << 24);
+ if (data_size > bin_size) {
+ ALOGE("%s: data_size 0x%x invalid, bin_size 0x%lx\n",
+ __func__, data_size, bin_size);
+ free(data_buf);
+ buf[index] = NULL;
+ return -1;
+ }
+
+ /* data check */
+ data_crc32 = data_buf[0] |
+ (data_buf[1] << 8) |
+ (data_buf[2] << 16) |
+ (data_buf[3] << 24);
+ temp_crc32 = CalCRC32(0, &data_buf[4], (data_size - 4));
+
+ if (model_debug_flag & DEBUG_TCON) {
+ ALOGD("%s: tcon_data[%d] crc32=0x%08x(0x%02x)\n",
+ __func__, index, temp_crc32, data_crc32);
+ }
+ if (data_crc32 != temp_crc32) {
+ ALOGE("%s: tcon_data[%d] crc32 check error\n", __func__, index);
+ free(data_buf);
+ buf[index] = NULL;
+ return -1;
+ }
+
+ data_buf[47] = '\0'; /* ensure name string ending */
+ if (model_debug_flag & DEBUG_TCON)
+ ALOGD("%s %d finish, bin_size = 0x%lx\n", __func__, index, bin_size);
+
+ BinFileUninit();
+
+ return 0;
+}
+#endif
+
+int handle_panel_ini(void)
+{
+ int tmp_len = 0;
+ unsigned char *tmp_buf = NULL;
+ struct lcd_attr_s lcd_attr;
+ struct bl_attr_s bl_attr;
+ struct panel_misc_s misc_attr;
+ unsigned char *tcon_spi = NULL;
+ char *file_name;
+ int print_flag;
+
+ print_flag = env_get_ulong("model_debug_print", 10, 0xffff);
+ if (print_flag != 0xffff) {
+ model_debug_flag = print_flag;
+ ALOGD("model_debug_flag: %d\n", model_debug_flag);
+ }
+
+ file_name = env_get("model_panel");
+ if (file_name == NULL) {
+ ALOGE("%s, model_panel path error!!!\n", __func__);
+ return -1;
+ }
+
+ tmp_buf = (unsigned char *) malloc(CC_MAX_DATA_SIZE);
+ if (tmp_buf == NULL) {
+ ALOGE("%s, malloc buffer memory error!!!\n", __func__);
+ return -1;
+ }
+
+ if (!lcd_ext_attr) {
+ lcd_ext_attr = (struct lcd_ext_attr_s *) malloc(sizeof(struct lcd_ext_attr_s));
+ if (!lcd_ext_attr) {
+ ALOGE("%s, malloc buffer memory error!!!\n", __func__);
+ goto handle_panel_ini_err1;
+ }
+ }
+
+#ifdef CONFIG_AML_LCD_TCON
+ tcon_spi = (unsigned char *) malloc(CC_MAX_TCON_SPI_SIZE);
+ if (!tcon_spi) {
+ ALOGE("%s, malloc buffer memory error!!!\n", __func__);
+ goto handle_panel_ini_err1;
+ }
+#endif
+
+ memset((void *)&lcd_attr, 0, sizeof(struct lcd_attr_s));
+ memset((void *)lcd_ext_attr, 0, sizeof(struct lcd_ext_attr_s));
+ memset((void *)&bl_attr, 0, sizeof(struct bl_attr_s));
+ memset((void *)&misc_attr, 0, sizeof(struct panel_misc_s));
+#ifdef CONFIG_AML_LCD_TCON
+ memset(tcon_spi, 0, CC_MAX_TCON_SPI_SIZE);
+#endif
+
+ //init misc attr as default
+ strcpy(misc_attr.version, "V001");
+ strcpy(misc_attr.outputmode, "1080p60hz");
+ misc_attr.panel_reverse = 0;
+
+ // start handle panel ini name
+ if (model_debug_flag & DEBUG_NORMAL)
+ ALOGD("%s: model_panel: %s\n", __func__, file_name);
+ if (!iniIsFileExist(file_name)) {
+ ALOGE("%s, file name \"%s\" not exist.\n", __func__, file_name);
+ goto handle_panel_ini_err2;
+ }
+
+ if (parse_panel_ini(file_name, &lcd_attr, lcd_ext_attr, &bl_attr, &misc_attr, tcon_spi) < 0) {
+ ALOGE("%s, parse_panel_ini file name \"%s\" fail.\n",
+ __func__, file_name);
+ goto handle_panel_ini_err2;
+ }
+
+ // start handle lcd param
+ memset((void *)tmp_buf, 0, CC_MAX_DATA_SIZE);
+ tmp_len = ReadLCDParam(tmp_buf);
+ //ALOGD("%s, start check lcd param data (0x%x).\n", __func__, tmp_len);
+ if (check_param_valid(0, gLcdDataCnt, (unsigned char*)&lcd_attr, tmp_len, tmp_buf) == CC_PARAM_CHECK_ERROR_NEED_UPDATE_PARAM) {
+ ALOGD("%s, check lcd param data error (0x%x), save lcd param.\n", __func__, tmp_len);
+ SaveLCDParam(gLcdDataCnt, (unsigned char*)&lcd_attr);
+ }
+ // end handle lcd param
+
+ // start handle lcd extern param
+ memset((void *)tmp_buf, 0, CC_MAX_DATA_SIZE);
+ tmp_len = ReadLCDExternParam(tmp_buf);
+ //ALOGD("%s, start check lcd extern param data (0x%x).\n", __func__, tmp_len);
+ if (check_param_valid(0, gLcdExtDataCnt, (unsigned char*)lcd_ext_attr, tmp_len, tmp_buf) == CC_PARAM_CHECK_ERROR_NEED_UPDATE_PARAM) {
+ ALOGD("%s, check lcd extern param data error (0x%x), save lcd extern param.\n", __func__, tmp_len);
+ SaveLCDExternParam(gLcdExtDataCnt, (unsigned char*)lcd_ext_attr);
+ }
+ // end handle lcd extern param
+
+ // start handle backlight param
+ memset((void *)tmp_buf, 0, CC_MAX_DATA_SIZE);
+ tmp_len = ReadBackLightParam(tmp_buf);
+ //ALOGD("%s, start check backlight param data (0x%x).\n", __func__, tmp_len);
+ if (check_param_valid(0, gBlDataCnt, (unsigned char*)&bl_attr, tmp_len, tmp_buf) == CC_PARAM_CHECK_ERROR_NEED_UPDATE_PARAM) {
+ ALOGD("%s, check backlight param data error (0x%x), save backlight param.\n", __func__, tmp_len);
+ SaveBackLightParam(gBlDataCnt, (unsigned char*)&bl_attr);
+ }
+ // end handle backlight param
+
+#ifdef CONFIG_AML_LCD_TCON
+ // start handle lcd_tcon_spi param
+ if (gLcdTconSpi_cnt) {
+ memset((void *)tmp_buf, 0, CC_MAX_DATA_SIZE);
+ tmp_len = ReadTconSpiParam(tmp_buf);
+ //ALOGD("%s, start check lcd_tcon_spi param data (0x%x).\n", __func__, tmp_len);
+ if (check_param_valid(0, gLcdTconSpi_cnt, tcon_spi, tmp_len, tmp_buf) == CC_PARAM_CHECK_ERROR_NEED_UPDATE_PARAM) {
+ ALOGD("%s, check lcd_tcon_spi param data error (0x%x), save lcd_tcon_spi param.\n", __func__, tmp_len);
+ SaveTconSpiParam(gLcdTconSpi_cnt, tcon_spi);
+ }
+ }
+ // end handle lcd_tcon_spi param
+#endif
+
+ // panel misc don't saving env
+
+ free(tcon_spi);
+ tcon_spi = NULL;
+ free(tmp_buf);
+ tmp_buf = NULL;
+
+#ifdef CONFIG_AML_LCD_TCON
+ if (g_lcd_tcon_valid)
+ handle_tcon_bin();
+#endif
+
+ return 0;
+
+handle_panel_ini_err2:
+ free(tcon_spi);
+ tcon_spi = NULL;
+handle_panel_ini_err1:
+ free(tmp_buf);
+ tmp_buf = NULL;
+
+ return -1;
+}
+
+static void model_list_panel_path(void)
+{
+ char *str;
+
+ str = env_get("model_panel");
+ if (str)
+ printf("current model_panel: %s\n", str);
+}
+#endif
+
+int parse_model_sum(const char *file_name, char *model_name)
+{
+ const char *ini_value = NULL;
+
+ IniParserInit();
+
+ if (IniParseFile(file_name) < 0) {
+ ALOGE("%s, ini load file error!\n", __func__);
+ IniParserUninit();
+ return -1;
+ }
+
+#ifdef CONFIG_AML_LCD
+ ini_value = IniGetString(model_name, "PANELINI_PATH", "null");
+ if (strcmp(ini_value, "null") != 0)
+ env_set("model_panel", ini_value);
+ else
+ ALOGE("%s, invalid PANELINI_PATH!!!\n", __func__);
+#endif
+
+ ini_value = IniGetString(model_name, "EDID_14_FILE_PATH", "null");
+ if (strcmp(ini_value, "null") != 0)
+ env_set("model_edid", ini_value);
+ else
+ ALOGE("%s, invalid EDID_14_FILE_PATH!!!\n", __func__);
+ /*
+ ini_value = IniGetString(model_name, "PQINI_PATH", "null");
+ if (strcmp(ini_value, "null") != 0)
+ env_set("model_pq", ini_value);
+
+ ini_value = IniGetString(model_name, "AMLOGIC_AUDIO_EFFECT_INI_PATH", "null");
+ if (strcmp(ini_value, "null") != 0)
+ env_set("model_audio", ini_value);
+ */
+ IniParserUninit();
+
+ return 0;
+}
+
+const char *get_model_sum_path(void)
+{
+ char *model_path;
+
+ model_path = env_get("model_path");
+ if (model_path == NULL) {
+ if (dynamic_partition) {
+ return DEFAULT_MODEL_SUM_PATH2;
+ } else {
+ return DEFAULT_MODEL_SUM_PATH1;
+ }
+ }
+
+ printf("%s: %s\n", __func__, model_path);
+ return model_path;
+}
+
+int handle_model_list(void)
+{
+ char *model;
+
+ model = env_get("model_name");
+ if (model == NULL) {
+ ALOGE("%s, model_name error!!!\n", __func__);
+ return -1;
+ }
+ printf("current model_name: %s\n", model);
+#ifdef CONFIG_AML_LCD
+ model_list_panel_path();
+#endif
+
+ IniParserInit();
+
+ if (IniParseFile(get_model_sum_path()) < 0) {
+ ALOGE("%s, ini load file error!\n", __func__);
+ IniParserUninit();
+ return -1;
+ }
+
+ printf("model_name list:\n");
+ IniListSection();
+ printf("\n");
+
+ IniParserUninit();
+
+ return 0;
+}
+
+int handle_model_sum(void)
+{
+ char *model;
+ int ret;
+
+ model = env_get("model_name");
+ if (model == NULL) {
+ ALOGE("%s, model_name error!!!\n", __func__);
+ return -1;
+ }
+ ret = parse_model_sum(get_model_sum_path(), model);
+ if (ret < 0)
+ return -1;
+#ifdef CONFIG_AML_LCD
+ ret = handle_panel_ini();
+#endif
+ return ret;
+}
+
diff --git a/cmd/amlogic/ini/model.h b/cmd/amlogic/ini/model.h
new file mode 100644
index 0000000..35ef91a
--- /dev/null
+++ b/cmd/amlogic/ini/model.h
@@ -0,0 +1,336 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __PAEL_INI_H__
+#define __PAEL_INI_H__
+#include "ini_size_define.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+extern int handle_model_list(void);
+extern int handle_model_sum(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#pragma pack (1)
+
+enum lcd_type_e {
+ LCD_TTL = 0,
+ LCD_LVDS,
+ LCD_VBYONE,
+ LCD_MIPI,
+ LCD_MLVDS,
+ LCD_P2P,
+ LCD_TYPE_MAX,
+};
+
+enum bl_ctrl_method_e {
+ BL_CTRL_GPIO = 0,
+ BL_CTRL_PWM,
+ BL_CTRL_PWM_COMBO,
+ BL_CTRL_LOCAL_DIMMING,
+ BL_CTRL_EXTERN,
+ BL_CTRL_MAX,
+};
+
+enum bl_pwm_method_e {
+ BL_PWM_NEGATIVE = 0,
+ BL_PWM_POSITIVE,
+ BL_PWM_METHOD_MAX,
+};
+
+enum bl_pwm_port_e {
+ BL_PWM_A = 0,
+ BL_PWM_B,
+ BL_PWM_C,
+ BL_PWM_D,
+ BL_PWM_E,
+ BL_PWM_F,
+ BL_PWM_VS,
+ BL_PWM_MAX,
+};
+
+enum lcd_ldim_mode_e {
+ LDIM_MODE_LR_SIDE = 0,
+ LDIM_MODE_TB_SIDE,
+ LDIM_MODE_DIRECT,
+ LDIM_MODE_MAX,
+};
+
+enum lcd_extern_type_e {
+ LCD_EXTERN_I2C = 0,
+ LCD_EXTERN_SPI,
+ LCD_EXTERN_MIPI,
+ LCD_EXTERN_MAX,
+};
+#define LCD_EXTERN_I2C_BUS_INVALID 0xff
+
+#define CC_LCD_NAME_LEN_MAX (30)
+
+struct lcd_header_s {
+ unsigned int crc32;
+ unsigned short data_len;
+ unsigned short version;
+ unsigned short rev;
+};
+
+struct lcd_basic_s {
+ char model_name[CC_LCD_NAME_LEN_MAX];
+ unsigned char lcd_type;
+ unsigned char lcd_bits;
+ unsigned short screen_width; /* screen physical width in "mm" unit */
+ unsigned short screen_height; /* screen physical height in "mm" unit */
+};
+
+struct lcd_timming_s {
+ unsigned short h_active; /* Horizontal display area */
+ unsigned short v_active; /* Vertical display area */
+ unsigned short h_period; /* Horizontal total period time */
+ unsigned short v_period; /* Vertical total period time */
+ unsigned short hsync_width;
+ unsigned short hsync_bp;
+ unsigned char hsync_pol;
+ unsigned short vsync_width;
+ unsigned short vsync_bp;
+ unsigned char vsync_pol;
+};
+
+struct lcd_customer_s {
+ unsigned char fr_adjust_type;
+ unsigned char ss_level;
+ unsigned char clk_auto_gen;
+ unsigned int pixel_clk;
+ unsigned short h_period_min;
+ unsigned short h_period_max;
+ unsigned short v_period_min;
+ unsigned short v_period_max;
+ unsigned int pixel_clk_min;
+ unsigned int pixel_clk_max;
+ unsigned char vlock_val_0;
+ unsigned char vlock_val_1;
+ unsigned char vlock_val_2;
+ unsigned char vlock_val_3;
+ unsigned int customer_value_9;
+};
+
+struct lcd_interface_s {
+ unsigned short if_attr_0; //vbyone_attr lane_count
+ unsigned short if_attr_1; //vbyone_attr region_num
+ unsigned short if_attr_2; //vbyone_attr byte_mode
+ unsigned short if_attr_3; //vbyone_attr color_fmt
+ unsigned short if_attr_4; //phy_attr vswing_level
+ unsigned short if_attr_5; //phy_attr preemphasis_level
+ unsigned short if_attr_6; //reversed
+ unsigned short if_attr_7; //reversed
+ unsigned short if_attr_8; //reversed
+ unsigned short if_attr_9; //reversed
+};
+
+#define CC_LCD_PWR_ITEM_CNT (4)
+struct lcd_pwr_s {
+ unsigned char pwr_step_type;
+ unsigned char pwr_step_index;
+ unsigned char pwr_step_val;
+ unsigned short pwr_step_delay;
+};
+
+#define CC_MAX_PWR_SEQ_CNT (50)
+
+struct lcd_attr_s {
+ struct lcd_header_s head;
+ struct lcd_basic_s basic;
+ struct lcd_timming_s timming;
+ struct lcd_customer_s customer;
+ struct lcd_interface_s interface;
+ struct lcd_pwr_s pwr[CC_MAX_PWR_SEQ_CNT];
+};
+
+#define CC_BL_NAME_LEN_MAX (30)
+
+struct bl_header_s {
+ unsigned int crc32;
+ unsigned short data_len;
+ unsigned short version;
+ unsigned short rev;
+};
+
+struct bl_basic_s {
+ char bl_name[CC_BL_NAME_LEN_MAX];
+};
+
+struct bl_level_s {
+ unsigned short bl_level_uboot;
+ unsigned short bl_level_kernel;
+ unsigned short bl_level_max;
+ unsigned short bl_level_min;
+ unsigned short bl_level_mid;
+ unsigned short bl_level_mid_mapping;
+};
+
+struct bl_method_s {
+ unsigned char bl_method;
+ unsigned char bl_en_gpio;
+ unsigned char bl_en_gpio_on;
+ unsigned char bl_en_gpio_off;
+ unsigned short bl_on_delay;
+ unsigned short bl_off_delay;
+};
+
+struct bl_pwm_s {
+ unsigned short pwm_on_delay;
+ unsigned short pwm_off_delay;
+
+ unsigned char pwm_method;
+ unsigned char pwm_port;
+ unsigned int pwm_freq;
+ unsigned char pwm_duty_max;
+ unsigned char pwm_duty_min;
+ unsigned char pwm_gpio;
+ unsigned char pwm_gpio_off;
+
+ unsigned char pwm2_method;
+ unsigned char pwm2_port;
+ unsigned int pwm2_freq;
+ unsigned char pwm2_duty_max;
+ unsigned char pwm2_duty_min;
+ unsigned char pwm2_gpio;
+ unsigned char pwm2_gpio_off;
+
+ unsigned short pwm_level_max;
+ unsigned short pwm_level_min;
+ unsigned short pwm2_level_max;
+ unsigned short pwm2_level_min;
+};
+
+struct bl_ldim_s {
+ unsigned char ldim_row;
+ unsigned char ldim_col;
+ unsigned char ldim_mode;
+ unsigned char ldim_dev_index;
+
+ unsigned short ldim_attr_4;
+ unsigned short ldim_attr_5;
+ unsigned short ldim_attr_6;
+ unsigned short ldim_attr_7;
+ unsigned short ldim_attr_8;
+ unsigned short ldim_attr_9;
+};
+
+struct bl_custome_s {
+ unsigned short custome_val_0;
+ unsigned short custome_val_1;
+ unsigned short custome_val_2;
+ unsigned short custome_val_3;
+ unsigned short custome_val_4;
+};
+
+struct bl_attr_s {
+ struct bl_header_s head;
+ struct bl_basic_s basic;
+ struct bl_level_s level;
+ struct bl_method_s method;
+ struct bl_pwm_s pwm;
+ struct bl_ldim_s ldim; //v2
+ struct bl_custome_s custome; //v2
+};
+
+#define CC_LCD_EXT_NAME_LEN_MAX (30)
+
+struct lcd_ext_header_s {
+ unsigned int crc32;
+ unsigned short data_len;
+ unsigned short version;
+ unsigned short rev;
+};
+
+#define LCD_EXTERN_CMD_SIZE_DYNAMIC 0xff
+#define LCD_EXTERN_INIT_ON_MAX 3000
+#define LCD_EXTERN_INIT_OFF_MAX 100
+
+struct lcd_ext_basic_s {
+ char ext_name[CC_LCD_EXT_NAME_LEN_MAX];
+ unsigned char ext_index; // set it as 0
+ unsigned char ext_type; // LCD_EXTERN_I2C, LCD_EXTERN_SPI, LCD_EXTERN_MIPI
+ unsigned char ext_status; // 1 is okay, 0 is disable
+};
+
+struct lcd_ext_type_s {
+ unsigned char value_0; //i2c_addr //spi_gpio_cs
+ unsigned char value_1; //i2c_second_addr //spi_gpio_clk
+ unsigned char value_2; //i2c_bus //spi_gpio_data
+ unsigned char value_3; //cmd_size //spi_clk_freq[bit 7:0] //unit: hz
+ unsigned char value_4; //spi_clk_freq[bit 15:8]
+ unsigned char value_5; //spi_clk_freq[bit 23:16]
+ unsigned char value_6; //spi_clk_freq[bit 31:24]
+ unsigned char value_7; //spi_clk_pol
+ unsigned char value_8; //cmd_size
+ unsigned char value_9; //reserved for future usage
+};
+
+#define CC_EXT_CMD_MAX_CNT (300)
+
+#define LCD_EXTERN_INIT_CMD 0x00
+#define LCD_EXTERN_INIT_CMD2 0x01 //only for special i2c device
+#define LCD_EXTERN_INIT_NONE 0x10
+#define LCD_EXTERN_INIT_GPIO 0xf0
+#define LCD_EXTERN_INIT_END 0xff
+
+struct lcd_ext_attr_s {
+ struct lcd_ext_header_s head;
+ struct lcd_ext_basic_s basic;
+ struct lcd_ext_type_s type;
+ unsigned char cmd_data[LCD_EXTERN_INIT_ON_MAX+LCD_EXTERN_INIT_OFF_MAX];
+};
+
+struct panel_misc_s {
+ char version[8];
+ char outputmode[64];
+ unsigned char panel_reverse;
+};
+
+struct lcd_tcon_spi_block_s {
+ unsigned short data_type;
+ unsigned short data_index;
+ unsigned int data_flag;
+ unsigned int spi_offset;
+ unsigned int spi_size;
+ unsigned int param_cnt;
+};
+
+#define CC_MAX_SUPPORT_PANEL_CNT (128)
+
+#define CC_MAX_PANEL_ALL_INFO_TAG_SIZE (16)
+#define CS_PANEL_ALL_INFO_TAG_CONTENT "panel_all_info"
+
+struct all_info_header_s {
+ unsigned int crc32;
+ unsigned short data_len;
+ unsigned short version;
+ unsigned char tag[CC_MAX_PANEL_ALL_INFO_TAG_SIZE];
+ unsigned int max_panel_cnt;
+ unsigned int cur_panel_cnt;
+ unsigned int sec_off;
+ unsigned int sec_cnt;
+ unsigned int sec_size;
+ unsigned int sec_len;
+ unsigned int item_head_off;
+ unsigned int item_head_cnt;
+ unsigned int item_head_size;
+ unsigned int item_head_len;
+ unsigned int def_flag;
+ unsigned char rev[12];
+};
+
+#define CC_MAX_PANEL_ALL_ONE_SEC_TAG_SIZE (16)
+#define CC_MAX_PANEL_ALL_ONE_SEC_TAG_CONTENT "panel_all_data0"
+
+unsigned char model_data_checksum(unsigned char *buf, unsigned int len);
+unsigned char model_data_lrc(unsigned char *buf, unsigned int len);
+
+#endif //__PAEL_INI_H__
diff --git a/cmd/amlogic/ini/model_data_check.c b/cmd/amlogic/ini/model_data_check.c
new file mode 100644
index 0000000..ec3a252
--- /dev/null
+++ b/cmd/amlogic/ini/model_data_check.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "model.h"
+
+unsigned char model_data_checksum(unsigned char *buf, unsigned int len)
+{
+ unsigned int temp = 0;
+ unsigned int i;
+
+ if (!buf)
+ return 0;
+ if (len == 0)
+ return 0;
+ for (i = 0; i < len; i++)
+ temp += buf[i];
+
+ return (unsigned char)(temp & 0xff);
+}
+
+unsigned char model_data_lrc(unsigned char *buf, unsigned int len)
+{
+ unsigned char temp = 0;
+ unsigned int i;
+
+ if (!buf)
+ return 0xff;
+ if (len == 0)
+ return 0xff;
+ temp = buf[0];
+ for (i = 1; i < len; i++)
+ temp = temp ^ buf[i];
+
+ return temp;
+}
+
diff --git a/cmd/amlogic/mmc_ts.c b/cmd/amlogic/mmc_ts.c
deleted file mode 100644
index caee322..0000000
--- a/cmd/amlogic/mmc_ts.c
+++ /dev/null
@@ -1,510 +0,0 @@
-/*
- * MMC-based transactional key-value store
- *
- * Copyright (C) 2010 Google, Inc.
- * Author: Bill he <yuegui.he@amlogic.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- */
-#include <amlogic/flash_ts.h>
-#include <amlogic/mmc_ts.h>
-#include <common.h>
-#include <malloc.h>
-#include <mmc.h>
-#include <partition_table.h>
-#include <emmc_partitions.h>
-#include <asm/arch/cpu_sdio.h>
-#include <asm/arch/sd_emmc.h>
-#include <linux/sizes.h>
-#include <amlogic/aml_mmc.h>
-
-#define DRV_DESC "MMC-based key-value storage"
-
-/* Internal state */
-struct mmc_ts_priv {
- struct mutex lock;
- struct mmc *mmc;
- struct partitions *part_info;
-
- /* chunk size, >= sizeof(struct mmc_ts) */
- size_t chunk;
-
- int mmc_read_write_unit;
-
- /* current record offset within mmc partition device */
- loff_t offset;
-
- /* fts partition offset on*/
- u64 mmc_ts_offset;
-
- /* fts partition size */
- u64 mmc_ts_size;
-
- /* mmc dev*/
- int dev;
-
- /* in-memory copy of mmc content */
- struct flash_ts cache;
-
- /* temporary buffers
- * - one backup for failure rollback
- * - another for read-after-write verification
- */
- struct flash_ts cache_tmp_backup;
- struct flash_ts cache_tmp_verify;
-};
-
-static struct mmc_ts_priv *__ts;
-static inline void __mmc_ts_put(struct mmc_ts_priv *ts)
-{
- mutex_unlock(&ts->lock);
-}
-
-static void set_to_default_empty_state(struct mmc_ts_priv *ts)
-{
- ts->offset = ts->part_info->size - ts->chunk;
- ts->cache.version = 0;
- ts->cache.len = 1;
- ts->cache.magic = FLASH_TS_MAGIC;
- ts->cache.data[0] = '\0';
-}
-
-static struct mmc_ts_priv *__mmc_ts_get(void)
-{
- struct mmc_ts_priv *ts = __ts;
-
- if (likely(ts)) {
- mutex_lock(&ts->lock);
- } else {
- printk(KERN_ERR DRV_NAME ": not initialized yet\n");
- }
-
- return ts;
-}
-
-static char *mmc_ts_find(struct mmc_ts_priv *ts, const char *key, size_t key_len)
-{
- char *s = ts->cache.data;
- while (*s) {
- if (!strncmp(s, key, key_len)) {
- if (s[key_len] == '=')
- return s;
- }
-
- s += strlen(s) + 1;
- }
- return NULL;
-}
-
-static inline u32 mmc_ts_check_header(const struct flash_ts *cache)
-{
- if (cache->magic == FLASH_TS_MAGIC &&
- cache->version &&
- cache->len && cache->len <= sizeof(cache->data) &&
- /* check correct null-termination */
- !cache->data[cache->len - 1] &&
- (cache->len == 1 || !cache->data[cache->len - 2])) {
- /* all is good */
- return cache->version;
- }
-
- return 0;
-}
-
-static int mmc_ts_read(int dev, struct mmc_ts_priv *ts, loff_t off, void *buf, size_t size, u64 part_start_offset)
-{
- ulong start_blk;
- struct mmc *mmc = ts->mmc;
- void *addr_byte, *addr = buf, *addr_tmp;
- u64 cnt = 0, sz_byte = 0, n = 0, blk = 0;
- mmc = find_mmc_device(dev);
- if (!mmc) {
- return 1;
- }
- mmc_init(mmc);
-
- /* blk shift : normal is 9 */
- int blk_shift = 0;
- blk_shift = ffs(mmc->read_bl_len) - 1;
-
- /* start blk offset */
- blk = (part_start_offset + off) >> blk_shift;
-
- /* seziof(ts->cache_tmp_verify) = cnt * ts->chunk + sz_byte */
- cnt = size >> blk_shift;
- sz_byte = size - (cnt << blk_shift);
-
- /* read cnt* ts->chunk bytes */
- n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
-
- /* read sz_byte bytes */
- if ((n == cnt) && (sz_byte != 0)) {
- //printf("sz_byte=%#llx bytes\n",sz_byte);
- addr_tmp = malloc(mmc->read_bl_len);
- addr_byte = (void *)(addr+cnt*(mmc->read_bl_len));
- start_blk = blk+cnt;
-
- if (addr_tmp == NULL) {
- printf("mmc read: malloc fail\n");
- free(addr);
- return 1;
- }
-
- if (blk_dread(mmc_get_blk_desc(mmc), start_blk, 1, addr_tmp) != 1) { // read 1 block
- free(addr_tmp);
- printf("mmc read 1 block fail\n");
- return 1;
- }
-
- memcpy(addr_byte, addr_tmp, sz_byte);
- free(addr_tmp);
- }
-
- return 0;
-}
-
-static int mmc_is_blank(const void *buf, size_t size)
-{
- size_t i;
- const unsigned int *data = (const unsigned int *)buf;
- size /= sizeof(data[0]);
-
- for (i = 0; i < size; i++)
- if (data[i] != 0xffffffff)
- return 0;
- return 1;
-}
-
-static int __init mmc_ts_scan(struct mmc_ts_priv *ts, int dev)
-{
- struct mmc *mmc = ts->mmc;
- int res;
- loff_t off = 0;
- struct flash_ts tmp_scan_backup;
- u64 mmc_ts_size = ts->mmc_ts_size;
- u64 part_start_offset = ts->mmc_ts_offset;
- void *scan_addr = (void *) &tmp_scan_backup;
-
- memset(&tmp_scan_backup, 0, sizeof(tmp_scan_backup));
-
- mmc_init(mmc);
-
- do {
- /* read FLASH_TS_MAX_DATA_SIZE data to ts->cache_tmp_verify */
- res = mmc_ts_read(dev, ts, off, scan_addr, sizeof(tmp_scan_backup), part_start_offset);
- if (!res) {
- /* check data struct */
- u32 version = mmc_ts_check_header(scan_addr);
- if (version > 0) {
- if (version > ts->cache.version) {
- memcpy(&ts->cache, scan_addr, sizeof(tmp_scan_backup));
- ts->offset = off;
- }
- break;
- } else if (0 == version && mmc_is_blank(&tmp_scan_backup, sizeof(tmp_scan_backup))) {
- off = (off + ts->mmc->erase_grp_size) & ~(ts->mmc->erase_grp_size - 1);
- } else {
- off += ts->chunk;
- }
-
- } else {
- off += ts->chunk;
- }
-
- } while(off < mmc_ts_size) ;/* while done*/
-
- return res;
-}
-
-
-static int mmc_write(int dev, struct mmc_ts_priv *ts, loff_t off, void *buf, size_t size, u64 part_start_offset)
-{
- ulong start_blk;
- struct mmc *mmc = ts->mmc;
- void *addr_byte, *addr_tmp, *addr, *addr_read;
- u64 cnt = 0, sz_byte = 0, n = 0, blk = 0, res;
- struct flash_ts tmp_write_backup, tmp_read_backup;
-
- /*********init local data struct**************/
- memset(&tmp_write_backup, 0, sizeof(tmp_write_backup));
- memset(&tmp_read_backup, 0, sizeof(tmp_read_backup));
- memcpy(&tmp_write_backup, buf, size);
- addr = (void *) &tmp_write_backup;
- addr_read = (void *) &tmp_read_backup;
- /********************************************/
-
- mmc = find_mmc_device(dev);
- if (!mmc) {
- return 1;
- }
- mmc_init(mmc);
-
- /* blk shift : normal is 9 */
- int blk_shift = 0;
- blk_shift = ffs(mmc->read_bl_len) - 1;
-
- /* start blk offset */
- blk = (part_start_offset + off) >> blk_shift;
-
- /* seziof(ts->cache_tmp_verify) = cnt * ts->chunk + sz_byte */
- cnt = size >> blk_shift;
- sz_byte = size - (cnt << blk_shift);
-
- n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr);
- //write sz_byte bytes
- if ((n == cnt) && (sz_byte != 0)) {
- // printf("sz_byte=%#llx bytes\n",sz_byte);
- addr_tmp = malloc(mmc->write_bl_len);
- addr_byte = (void*)(addr+cnt*(mmc->write_bl_len));
- start_blk = blk+cnt;
-
- if (addr_tmp == NULL) {
- printf("mmc write: malloc fail\n");
- return 1;
- }
-
- if (blk_dread(mmc_get_blk_desc(mmc), start_blk, 1, addr_tmp) != 1) { // read 1 block
- free(addr_tmp);
- printf("mmc read 1 block fail\n");
- return 1;
- }
-
- memcpy(addr_tmp, addr_byte, sz_byte);
- if (blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr) != 1) { // write 1 block
- free(addr_tmp);
- printf("mmc write 1 block fail\n");
- return 1;
- }
- free(addr_tmp);
- }
-
- res = mmc_ts_read(dev, ts, off, addr_read, sizeof(tmp_read_backup), part_start_offset);
-
- if (!res) {
- if (! memcmp(&tmp_write_backup, &tmp_read_backup, size)) {
- memcpy(&ts->cache, &tmp_write_backup, size);
- printk("key write successfull!\n");
- return 0;
- } else {
- printk("%s:%d error!\n", __func__, __LINE__);
- return -1;
- }
-
- } else {
- printk("check key failure!\n");
- printk("%s:%d error!\n", __func__, __LINE__);
- return -2;
- }
-
- return 0;
-}
-
-static int mmc_ts_commit(struct mmc_ts_priv *ts)
-{
- int res;
- int dev = ts->dev;
- u64 part_start_offset = ts->mmc_ts_offset;
-
- res = mmc_write(dev,ts, 0, &ts->cache, sizeof(ts->cache), part_start_offset);
-
- return res;
-}
-
-int mmc_ts_set(const char *key, const char *value)
-{
- int res;
- char *p;
- struct mmc_ts_priv *ts;
- size_t klen = strlen(key);
- size_t vlen = strlen(value);
-
- ts = __mmc_ts_get();
- if (unlikely(!ts))
- return -EINVAL;
- /* save current cache contents so we can restore it on failure */
- memcpy(&ts->cache_tmp_backup, &ts->cache, sizeof(ts->cache_tmp_backup));
-
- p = mmc_ts_find(ts, key, klen);
- if (p) {
- /* we are replacing existing entry,
- * empty value (vlen == 0) removes entry completely.
- */
- size_t cur_len = strlen(p) + 1;
- size_t new_len = vlen ? klen + 1 + vlen + 1 : 0;
-
- if (cur_len != new_len) {
- /* we need to move stuff around */
-
- if ((ts->cache.len - cur_len) + new_len >
- sizeof(ts->cache.data))
- goto no_space;
-
- memmove(p + new_len, p + cur_len,
- ts->cache.len - (p - ts->cache.data + cur_len));
-
- ts->cache.len = (ts->cache.len - cur_len) + new_len;
- } else if (!strcmp(p + klen + 1, value)) {
- /* skip update if new value is the same as the old one */
- res = 0;
- goto out;
- }
-
- if (vlen) {
- p += klen + 1;
- memcpy(p, value, vlen);
- p[vlen] = '\0';
- }
- } else {
- size_t len = klen + 1 + vlen + 1;
-
- /* don't do anything if value is empty */
- if (!vlen) {
- res = 0;
- goto out;
- }
-
- if (ts->cache.len + len > sizeof(ts->cache.data))
- goto no_space;
-
- /* add new entry at the end */
- p = ts->cache.data + ts->cache.len - 1;
- memcpy(p, key, klen);
- p += klen;
- *p++ = '=';
- memcpy(p, value, vlen);
- p += vlen;
- *p++ = '\0';
- *p = '\0';
- ts->cache.len += len;
- }
- ++ts->cache.version;
- res = mmc_ts_commit(ts);
- if (unlikely(res))
- memcpy(&ts->cache, &ts->cache_tmp_backup, sizeof(ts->cache));
-
- goto out;
-
- no_space:
- printk(KERN_WARNING DRV_NAME ": no space left for '%s=%s'\n",
- key, value);
- res = -ENOSPC;
- out:
- __mmc_ts_put(ts);
-
- return res;
-
-}
-
-void mmc_ts_get(const char *key, char *value, unsigned int size)
-{
- const char *p;
- struct mmc_ts_priv *ts;
- size_t klen = strlen(key);
-
- BUG_ON(!size);
-
- *value = '\0';
-
- ts = __mmc_ts_get();
- if (unlikely(!ts))
- return;
-
- p = mmc_ts_find(ts, key, klen);
- if (p)
- strlcpy(value, p + klen + 1, size);
-
- __mmc_ts_put(ts);
-
-}
-
-/* Round-up to the next power-of-2,
- * from "Hacker's Delight" by Henry S. Warren.
- */
-static inline u32 clp2(u32 x)
-{
- --x;
- x |= x >> 1;
- x |= x >> 2;
- x |= x >> 4;
- x |= x >> 8;
- x |= x >> 16;
- return x + 1;
-}
-
-int mmc_ts_init(void)
-{
- int res,dev;
- struct mmc *mmc;
- struct mmc_ts_priv *ts;
- struct partitions *part_info = NULL;
-
- // get dev by name
- dev = find_dev_num_by_partition_name(CONFIG_FLASH_TS_PARTITION);
- if (dev < 0) {
- printf("Cannot find dev.\n");
- return 1;
- }
- mmc = find_mmc_device(dev);
- if (!mmc) {
- return 1;
- }
-
- //init mmc
- mmc_init(mmc);
- //init fts data struct
- ts = malloc(sizeof(*ts));
- if (unlikely(!ts)) {
- res = -ENOMEM;
- printk(KERN_ERR DRV_NAME ": failed to allocate memory\n");
- }
-
- mutex_init(&ts->lock);
- ts->mmc = mmc;
- ts->mmc_read_write_unit = ts->mmc->read_bl_len;
- ts->chunk = clp2((sizeof(struct flash_ts) + ts->mmc->read_bl_len - 1) &
- ~(ts->mmc->read_bl_len - 1));
-
- /* dev*/
- ts->dev = dev;
-
- /* get fts part info*/
- part_info = find_mmc_partition_by_name(CONFIG_FLASH_TS_PARTITION);
- if (part_info == NULL) {
- kfree(ts);
- printf("get partition info failed !!\n");
- return -1;
- }
-
- /* init partiton info to ts data struct*/
- ts->part_info = part_info;
- ts->mmc_ts_offset = ts->part_info->offset;
- ts->mmc_ts_size = ts->part_info->size;
-
- /* default empty state */
- set_to_default_empty_state(ts);
-
- /* scan mmc partition for the most recent record */
- res = mmc_ts_scan(ts, dev);
- if (unlikely(res)) {
- goto out_free;
- }
-
- if (ts->cache.version)
- printk(KERN_INFO DRV_NAME ": v%u loaded from 0x%08llx\n",
- ts->cache.version, ts->offset);
-
- res = misc_register(&mmc_ts_miscdev);
- if (unlikely(res)) {
- goto out_free;
- }
-
- __ts = ts;
-
-out_free:
- kfree(ts);
-
- return 0;
-}
diff --git a/cmd/amlogic/nand_ts.c b/cmd/amlogic/nand_ts.c
deleted file mode 100644
index 0807cef..0000000
--- a/cmd/amlogic/nand_ts.c
+++ /dev/null
@@ -1,562 +0,0 @@
-/*
- * MTD-based transactional key-value store
- *
- * Copyright (C) 2010 Google, Inc.
- * Author: Eugene Surovegin <es@google.com>
- *
- * This software is licensed under the terms of the GNU General Public
- * License version 2, as published by the Free Software Foundation, and
- * may be copied, distributed, and modified under those terms.
- *
- */
-#include <amlogic/flash_ts.h>
-#include <linux/mtd/mtd.h>
-#include <amlogic/nand_ts.h>
-
-#define DRV_DESC "MTD-based key-value storage"
-
-/* Internal state */
-struct nand_ts_priv {
- struct mutex lock;
- struct mtd_info *mtd;
-
- /* chunk size, >= sizeof(struct flash_ts) */
- size_t chunk;
-
- /* current record offset within MTD device */
- loff_t offset;
-
- /* in-memory copy of flash content */
- struct flash_ts cache;
-
- /* temporary buffers
- * - one backup for failure rollback
- * - another for read-after-write verification
- */
- struct flash_ts cache_tmp_backup;
- struct flash_ts cache_tmp_verify;
-};
-
-static struct nand_ts_priv *__ts;
-static int nand_is_blank(const void *buf, size_t size)
-{
- size_t i;
- const unsigned int *data = (const unsigned int *)buf;
- size /= sizeof(data[0]);
-
- for (i = 0; i < size; i++)
- if (data[i] != 0xffffffff)
- return 0;
- return 1;
-}
-
-static void nand_erase_callback(struct erase_info *ctx)
-{
-#ifndef __UBOOT__
- wake_up((wait_queue_head_t*)ctx->priv);
-#endif
-}
-
-static int nand_erase(struct mtd_info *mtd, loff_t off)
-{
- struct erase_info ei = {0};
- int res;
-
- wait_queue_head_t waitq;
- DECLARE_WAITQUEUE(wait, current);
- init_waitqueue_head(&waitq);
-
- ei.mtd = mtd;
- ei.len = mtd->erasesize;
- ei.addr = off;
- ei.callback = nand_erase_callback;
- ei.priv = (unsigned long)&waitq;
-
- /* Yes, this is racy, but safer than just leaving
- * partition writeable all the time.
- */
- mtd->flags |= MTD_WRITEABLE;
-
- res = mtd_erase(mtd, &ei);
- if (!res) {
- set_current_state(TASK_UNINTERRUPTIBLE);
- add_wait_queue(&waitq, &wait);
- if (ei.state != MTD_ERASE_DONE && ei.state != MTD_ERASE_FAILED)
- schedule();
- remove_wait_queue(&waitq, &wait);
- set_current_state(TASK_RUNNING);
-
- res = ei.state == MTD_ERASE_FAILED ? -EIO : 0;
- }
- mtd->flags &= ~MTD_WRITEABLE;
-
- if (unlikely(res))
- printk(KERN_ERR DRV_NAME
- ": nand_erase(0x%08llx) failed, errno %d\n",
- off, res);
- return res;
-}
-
-static int nand_write(struct mtd_info *mtd, loff_t off,
- const void *buf, size_t size)
-{
- int res = 0;
-
- mtd->flags |= MTD_WRITEABLE;
- while (size) {
- size_t retlen;
- res = mtd_write(mtd, off, size, &retlen, buf);
- if (likely(!res)) {
- off += retlen;
- buf += retlen;
- size -= retlen;
- } else {
- printk(KERN_ERR DRV_NAME
- ": nand_write(0x%08llx, %zu) failed, errno %d\n",
- off, size, res);
- break;
- }
- }
- mtd->flags &= ~MTD_WRITEABLE;
-
- return res;
-}
-
-static int nand_read(struct mtd_info *mtd, loff_t off, void *buf, size_t size)
-{
- int res = 0;
- while (size) {
- size_t retlen;
- res = mtd_read(mtd, off, size, &retlen, buf);
- if (!res || res == -EUCLEAN) {
- off += retlen;
- buf += retlen;
- size -= retlen;
- } else {
- printk(KERN_WARNING DRV_NAME
- ": nand_read() failed, errno %d\n", res);
- break;
- }
- }
- return res;
-}
-
-static char *nand_ts_find(struct nand_ts_priv *ts, const char *key,
- size_t key_len)
-{
- char *s = ts->cache.data;
- while (*s) {
- if (!strncmp(s, key, key_len)) {
- if (s[key_len] == '=')
- return s;
- }
-
- s += strlen(s) + 1;
- }
- return NULL;
-}
-
-static inline u32 nand_ts_crc(const struct flash_ts *cache)
-{
- const unsigned char *p;
- u32 crc = 0;
- size_t len;
-
- /* skip magic and crc fields */
- len = cache->len + 2 * sizeof(u32);
- p = (const unsigned char*)&cache->len;
-
- while (len--) {
- int i;
-
- crc ^= *p++;
- for (i = 0; i < 8; i++)
- crc = (crc >> 1) ^ ((crc & 1) ? 0xedb88320 : 0);
- }
- return crc ^ ~0;
-}
-
-static void set_to_default_empty_state(struct nand_ts_priv *ts)
-{
- ts->offset = ts->mtd->size - ts->chunk;
- ts->cache.magic = FLASH_TS_MAGIC;
- ts->cache.version = 0;
- ts->cache.len = 1;
- ts->cache.data[0] = '\0';
- ts->cache.crc = nand_ts_crc(&ts->cache);
-}
-
-/* Verifies cache consistency and locks it */
-static struct nand_ts_priv *__nand_ts_get(void)
-{
- struct nand_ts_priv *ts = __ts;
-
- if (likely(ts)) {
- mutex_lock(&ts->lock);
- if (unlikely(ts->cache.crc != nand_ts_crc(&ts->cache))) {
- printk(KERN_CRIT DRV_NAME
- ": memory corruption detected\n");
- mutex_lock(&ts->lock);
- ts = NULL;
- }
- } else {
- printk(KERN_ERR DRV_NAME ": not initialized yet\n");
- }
-
- return ts;
-}
-
-static inline void __nand_ts_put(struct nand_ts_priv *ts)
-{
- mutex_unlock(&ts->lock);
-}
-
-static int nand_ts_commit(struct nand_ts_priv *ts)
-{
- struct mtd_info *mtd = ts->mtd;
- loff_t off = ts->offset + ts->chunk;
- /* we try to make two passes to handle non-erased blocks
- * this should only matter for the inital pass over the whole device.
- */
- int max_iterations = mtd_div_by_eb(mtd->size, mtd) * 2;
- size_t size = ALIGN(FLASH_TS_HDR_SIZE + ts->cache.len, ts->chunk);
-
- /* fill unused part of data */
- memset(ts->cache.data + ts->cache.len, 0xff,
- sizeof(ts->cache.data) - ts->cache.len);
-
- while (max_iterations--) {
- /* wrap around */
- if (off >= mtd->size)
- off = 0;
-
- /* new block? */
- if (!(off & (mtd->erasesize - 1))) {
- if (mtd_block_isbad(mtd, off)) {
- /* skip this block */
- off += mtd->erasesize;
- continue;
- }
-
- if (unlikely(nand_erase(mtd, off))) {
- /* skip this block */
- off += mtd->erasesize;
- continue;
- }
- }
-
- /* write and read back to veryfy */
- if (nand_write(mtd, off, &ts->cache, size) ||
- nand_read(mtd, off, &ts->cache_tmp_verify, size)) {
- /* hmm, probably unclean block, skip it for now */
- off = (off + mtd->erasesize) & ~(mtd->erasesize - 1);
- continue;
- }
-
- /* compare */
- if (memcmp(&ts->cache, &ts->cache_tmp_verify, size)) {
- printk(KERN_WARNING DRV_NAME
- ": record v%u read mismatch @ 0x%08llx\n",
- ts->cache.version, off);
- /* skip this block for now */
- off = (off + mtd->erasesize) & ~(mtd->erasesize - 1);
- continue;
- }
-
- /* for new block, erase the previous block after write done,
- * it's to speed up nand_ts_scan
- */
- if (!(off & (mtd->erasesize - 1))) {
- loff_t pre_block_base = ts->offset & ~(mtd->erasesize - 1);
- loff_t cur_block_base = off & ~(mtd->erasesize - 1);
- if (cur_block_base != pre_block_base)
- nand_erase(mtd, pre_block_base);
- }
- ts->offset = off;
- printk(KERN_DEBUG DRV_NAME ": record v%u commited @ 0x%08llx\n",
- ts->cache.version, off);
- return 0;
- }
-
- printk(KERN_ERR DRV_NAME ": commit failure\n");
- return -EIO;
-}
-
-int nand_ts_set(const char *key, const char *value)
-{
- struct nand_ts_priv *ts;
- size_t klen = strlen(key);
- size_t vlen = strlen(value);
- int res;
- char *p;
-
- ts = __nand_ts_get();
- if (unlikely(!ts))
- return -EINVAL;
-
- /* save current cache contents so we can restore it on failure */
- memcpy(&ts->cache_tmp_backup, &ts->cache, sizeof(ts->cache_tmp_backup));
-
- p = nand_ts_find(ts, key, klen);
- if (p) {
- /* we are replacing existing entry,
- * empty value (vlen == 0) removes entry completely.
- */
- size_t cur_len = strlen(p) + 1;
- size_t new_len = vlen ? klen + 1 + vlen + 1 : 0;
-
- if (cur_len != new_len) {
- /* we need to move stuff around */
-
- if ((ts->cache.len - cur_len) + new_len >
- sizeof(ts->cache.data))
- goto no_space;
-
- memmove(p + new_len, p + cur_len,
- ts->cache.len - (p - ts->cache.data + cur_len));
-
- ts->cache.len = (ts->cache.len - cur_len) + new_len;
- } else if (!strcmp(p + klen + 1, value)) {
- /* skip update if new value is the same as the old one */
- res = 0;
- goto out;
- }
-
- if (vlen) {
- p += klen + 1;
- memcpy(p, value, vlen);
- p[vlen] = '\0';
- }
- } else {
- size_t len = klen + 1 + vlen + 1;
-
- /* don't do anything if value is empty */
- if (!vlen) {
- res = 0;
- goto out;
- }
-
- if (ts->cache.len + len > sizeof(ts->cache.data))
- goto no_space;
-
- /* add new entry at the end */
- p = ts->cache.data + ts->cache.len - 1;
- memcpy(p, key, klen);
- p += klen;
- *p++ = '=';
- memcpy(p, value, vlen);
- p += vlen;
- *p++ = '\0';
- *p = '\0';
- ts->cache.len += len;
- }
-
- ++ts->cache.version;
- ts->cache.crc = nand_ts_crc(&ts->cache);
- res = nand_ts_commit(ts);
- if (unlikely(res))
- memcpy(&ts->cache, &ts->cache_tmp_backup, sizeof(ts->cache));
- goto out;
-
- no_space:
- printk(KERN_WARNING DRV_NAME ": no space left for '%s=%s'\n",
- key, value);
- res = -ENOSPC;
- out:
- __nand_ts_put(ts);
-
- return res;
-}
-
-void nand_ts_get(const char *key, char *value, unsigned int size)
-{
- size_t klen = strlen(key);
- struct nand_ts_priv *ts;
- const char *p;
-
- BUG_ON(!size);
-
- *value = '\0';
-
- ts = __nand_ts_get();
- if (unlikely(!ts))
- return;
-
- p = nand_ts_find(ts, key, klen);
- if (p)
- strlcpy(value, p + klen + 1, size);
-
- __nand_ts_put(ts);
-}
-
-static inline u32 nand_ts_check_header(const struct flash_ts *cache)
-{
- if (cache->magic == FLASH_TS_MAGIC &&
- cache->version &&
- cache->len && cache->len <= sizeof(cache->data) &&
- cache->crc == nand_ts_crc(cache) &&
- /* check correct null-termination */
- !cache->data[cache->len - 1] &&
- (cache->len == 1 || !cache->data[cache->len - 2])) {
- /* all is good */
- return cache->version;
- }
-
- return 0;
-}
-
-static int __init nand_ts_scan(struct nand_ts_priv *ts)
-{
- struct mtd_info *mtd = ts->mtd;
- int res, good_blocks = 0;
- loff_t off = 0;
-
- do {
- /* new block ? */
- if (!(off & (mtd->erasesize - 1))) {
- if (mtd_block_isbad(mtd, off)) {
- printk(KERN_INFO DRV_NAME
- ": skipping bad block @ 0x%08llx\n",
- off);
- off += mtd->erasesize;
- continue;
- } else
- ++good_blocks;
- }
-
- res = nand_read(mtd, off, &ts->cache_tmp_verify,
- sizeof(ts->cache_tmp_verify));
- if (!res) {
- u32 version =
- nand_ts_check_header(&ts->cache_tmp_verify);
- if (version > ts->cache.version) {
- memcpy(&ts->cache, &ts->cache_tmp_verify,
- sizeof(ts->cache));
- ts->offset = off;
- }
- if (0 == version &&
- nand_is_blank(&ts->cache_tmp_verify,
- sizeof(ts->cache_tmp_verify))) {
- /* skip the whole block if chunk is blank */
- off = (off + mtd->erasesize) & ~(mtd->erasesize - 1);
- } else {
- off += ts->chunk;
- }
- } else {
- off += ts->chunk;
- }
- } while (off < mtd->size);
-
- if (unlikely(!good_blocks)) {
- printk(KERN_ERR DRV_NAME ": no good blocks\n");
- return -ENODEV;
- }
-
- if (unlikely(good_blocks < 2))
- printk(KERN_WARNING DRV_NAME ": less than 2 good blocks,"
- " reliability is not guaranteed\n");
- return 0;
-}
-
-/* Round-up to the next power-of-2,
- * from "Hacker's Delight" by Henry S. Warren.
- */
-static inline u32 clp2(u32 x)
-{
- --x;
- x |= x >> 1;
- x |= x >> 2;
- x |= x >> 4;
- x |= x >> 8;
- x |= x >> 16;
- return x + 1;
-}
-
-int nand_ts_init(void)
-{
- static bool do_init = false;
- if (do_init)
- return 0;
-
- do_init = true;
- struct nand_ts_priv *ts;
- struct mtd_info *mtd;
- int res;
-
- mtd = get_mtd_device_nm(CONFIG_FLASH_TS_PARTITION);
- if (unlikely(IS_ERR(mtd))) {
- printk(KERN_ERR DRV_NAME
- ": mtd partition '" CONFIG_FLASH_TS_PARTITION
- "' not found\n");
- return -ENODEV;
- }
-
- /* we need at least two erase blocks */
- if (unlikely(mtd->size < 2 * mtd->erasesize)) {
- printk(KERN_ERR DRV_NAME ": mtd partition is too small\n");
- res = -ENODEV;
- goto out_put;
- }
-
- /* make sure both page and block sizes are power-of-2
- * (this will make chunk size determination simpler).
- */
- if (unlikely(!is_power_of_2(mtd->writesize) ||
- !is_power_of_2(mtd->erasesize))) {
- res = -ENODEV;
- printk(KERN_ERR DRV_NAME ": unsupported MTD geometry\n");
- goto out_put;
- }
-
- ts = kzalloc(sizeof(*ts), GFP_KERNEL);
- if (unlikely(!ts)) {
- res = -ENOMEM;
- printk(KERN_ERR DRV_NAME ": failed to allocate memory\n");
- goto out_put;
- }
-
- mutex_init(&ts->lock);
- ts->mtd = mtd;
-
- /* determine chunk size so it doesn't cross block boundary,
- * is multiple of page size and there is no wasted space in a block.
- * We assume page and block sizes are power-of-2.
- */
- ts->chunk = clp2((sizeof(struct flash_ts) + mtd->writesize - 1) &
- ~(mtd->writesize - 1));
- if (unlikely(ts->chunk > mtd->erasesize)) {
- res = -ENODEV;
- printk(KERN_ERR DRV_NAME ": MTD block size is too small\n");
- goto out_free;
- }
-
- /* default empty state */
- set_to_default_empty_state(ts);
-
- /* scan flash partition for the most recent record */
- res = nand_ts_scan(ts);
- if (unlikely(res))
- goto out_free;
-
- if (ts->cache.version)
- printk(KERN_INFO DRV_NAME ": v%u loaded from 0x%08llx\n",
- ts->cache.version, ts->offset);
-
- /* "Protect" MTD partition from direct user-space write access */
- mtd->flags &= ~MTD_WRITEABLE;
-
- res = misc_register(&flash_ts_miscdev);
- if (unlikely(res))
- goto out_free;
-
- __ts = ts;
-
- return 0;
-
- out_free:
- kfree(ts);
-
- out_put:
- put_mtd_device(mtd);
- return res;
-}
diff --git a/cmd/amlogic/os_ident.c b/cmd/amlogic/os_ident.c
new file mode 100644
index 0000000..b74b1db
--- /dev/null
+++ b/cmd/amlogic/os_ident.c
@@ -0,0 +1,62 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <image.h>
+#include <android_image.h>
+
+//#define OS_IDENT_DEBUG
+
+#ifdef OS_IDENT_DEBUG
+#define debug_print(...) printf(__VA_ARGS__)
+#else
+#define debug_print(...) ((void)0)
+#endif
+
+static int do_os_ident(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int ret = -1;
+
+ if (argc < 2) {
+ printf("Err! OS hdr addr not specified!\n");
+ return ret;
+ }
+
+ const void *img_addr = (const void *)simple_strtoul(argv[1], NULL, 16);
+ debug_print("os hdr addr: 0x%lx\n", (ulong)img_addr);
+
+ ret = genimg_get_format(img_addr);
+ switch (ret) {
+ case IMAGE_FORMAT_LEGACY:
+ debug_print("IMAGE_FORMAT_LEGACY format\n");
+ env_set("os_type", "rtos");
+ break;
+ case IMAGE_FORMAT_FIT:
+ debug_print("IMAGE_FORMAT_FIT format\n");
+ /* ignore fdt format, it's not an OS */
+ //env_set("os_type", "fdt");
+ break;
+ case IMAGE_FORMAT_ANDROID:
+ debug_print("IMAGE_FORMAT_ANDROID format\n");
+ env_set("os_type", "kernel");
+ break;
+ case IMAGE_FORMAT_INVALID:
+ debug_print("IMAGE_FORMAT_INVALID format\n");
+ env_set("os_type", "invalid");
+ break;
+ default:
+ debug_print("default format\n");
+ break;
+ }
+
+ return ret;
+}
+
+U_BOOT_CMD(
+ os_ident, CONFIG_SYS_MAXARGS, 1, do_os_ident,
+ "identify OS type",
+ "[addr]\n"
+);
diff --git a/cmd/amlogic/storage.c b/cmd/amlogic/storage.c
deleted file mode 100644
index 4e91050..0000000
--- a/cmd/amlogic/storage.c
+++ /dev/null
@@ -1,802 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
-/*
- * Storage interface module
- *
- * Copyright (C) 2018 Amlogic Corporation
- *
- */
-#include <amlogic/storage.h>
-
-#undef pr_info
-#define pr_info printf
-
-#ifdef CONFIG_SPI_FLASH
-extern int spi_nor_pre(void);
-extern int spi_nor_probe(u32 init_flag);
-#endif
-
-#ifdef CONFIG_SPI_NAND
-extern int spi_nand_pre(void);
-extern int spi_nand_probe(u32 init_flag);
-#endif
-
-#ifdef CONFIG_AML_NAND
-extern int amlnf_pre(void);
-extern int amlnf_probe(u32 init_flag);
-#endif
-
-#ifdef CONFIG_MESON_NFC
-extern int nand_pre(void);
-extern int nand_probe(uint32_t init_flag);
-#endif
-
-#ifdef CONFIG_MMC_MESON_GX
-extern int emmc_pre(void);
-extern int emmc_probe(u32 init_flag);
-#endif
-
-static struct storage_t *current;
-static struct device_node_t device_list[] = {
-#if 0
- {BOOT_SD, "sd", sdcard_pre, sdcard_probe},
-#endif
-
-#ifdef CONFIG_MMC_MESON_GX
- {BOOT_EMMC, "emmc", emmc_pre, emmc_probe},
-#endif
-
-#ifdef CONFIG_MESON_NFC
- {BOOT_NAND_MTD, "mtd", nand_pre, nand_probe},
-#endif
-
-#ifdef CONFIG_AML_NAND
- {BOOT_NAND_NFTL, "nftl", amlnf_pre, amlnf_probe},
-#endif
-#ifdef CONFIG_SPI_NAND
- {BOOT_SNAND, "spi-nand", spi_nand_pre, spi_nand_probe},
-#endif
-#if CONFIG_SPI_FLASH
- {BOOT_SNOR, "spi-nor", spi_nor_pre, spi_nor_probe}
-#endif
-};
-
-int store_register(struct storage_t *store_dev)
-{
- if (!store_dev)
- return 1;
- if (!current) {
- INIT_LIST_HEAD(&store_dev->list);
- current = store_dev;
- return 0;
- }
- /**
- * the head node will not be a valid node
- * usually when we use the list, but in storage
- * interface module, we init the device node as
- * a head instead a global list_head pointer,
- * it should be traversaled.
- */
- if (store_dev == current)
- return 0;
- struct storage_t *dev;
-
- if (store_dev->type == current->type)
- return 1;
- list_for_each_entry(dev, ¤t->list, list) {
- if (dev == store_dev)
- return 0;
- else if (dev->type == store_dev->type)
- return 1;
- }
- list_add_tail(&store_dev->list, ¤t->list);
- current = store_dev;
- return 0;
-}
-
-void store_unregister(struct storage_t *store_dev)
-{
- if (store_dev == current) {
- if (list_empty_careful(&store_dev->list)) {
- current = NULL;
- } else {
- current = list_entry((current->list).next,
- struct storage_t, list);
- list_del_init(&store_dev->list);
- }
- } else {
- list_del_init(&store_dev->list);
- }
-}
-
-u8 store_device_valid(enum boot_type_e type)
-{
- struct list_head *entry;
- struct storage_t *dev;
-
- if (!current)
- return 0;
- if (current->type == type)
- return 1;
- list_for_each(entry, ¤t->list) {
- dev = list_entry(entry, struct storage_t, list);
- if (dev->type == type)
- return 1;
- }
- return 0;
-}
-
-int store_init(u32 init_flag)
-{
- int i, ret;
- int record = 0;
-
- for (i = 0; i < ARRAY_SIZE(device_list); i++)
- if (!device_list[i].pre()) {
- ret = device_list[i].probe(init_flag);
- if (!ret)
- record |= device_list[i].index;
- }
-
- return record;
-}
-
-static struct storage_t *store_get_current(void)
-{
- return current;
-}
-
-int store_set_device(enum boot_type_e type)
-{
- struct list_head *entry;
- struct storage_t *dev, *store_dev = store_get_current();
-
- if (!store_dev) {
- pr_info("%s %d no current device\n", __func__, __LINE__);
- return 1;
- }
- if (store_dev->type == type)
- return 0;
- list_for_each(entry, &store_dev->list) {
- dev = list_entry(entry, struct storage_t, list);
- if (dev->type == type) {
- current = dev;
- return 0;
- }
- }
- pr_info("%s %d please confirm the %d device is valid\n",
- __func__, __LINE__, type);
- return 1;
-}
-
-enum boot_type_e store_get_type(void)
-{
- struct storage_t *store = store_get_current();
-
- if (!store) {
- pr_info("%s %d please init storage device first\n",
- __func__, __LINE__);
- return BOOT_NONE;
- }
-
- return store->type;
-}
-
-int store_get_device_info(struct storage_info_t *info)
-{
- struct storage_t *store = store_get_current();
-
- if (!store) {
- pr_info("%s %d please init storage device first\n",
- __func__, __LINE__);
- return 1;
- }
-
- memcpy((char *)info, (char *)&store->info,
- sizeof(struct storage_info_t));
- return 0;
-}
-
-int store_read(const char *name, loff_t off, size_t size, void *buf)
-{
- struct storage_t *store = store_get_current();
-
- if (!store) {
- pr_info("%s %d please init storage device first\n",
- __func__, __LINE__);
- return 1;
- }
- return store->read(name, off, size, buf);
-}
-
-int store_write(const char *name, loff_t off, size_t size, void *buf)
-{
- struct storage_t *store = store_get_current();
-
- if (!store) {
- pr_info("%s %d please init storage device first\n",
- __func__, __LINE__);
- return 1;
- }
- return store->write(name, off, size, buf);
-}
-
-int store_erase(const char *name, loff_t off, size_t size, int scrub)
-{
- struct storage_t *store = store_get_current();
-
- if (!store) {
- pr_info("%s %d please init storage device first\n",
- __func__, __LINE__);
- return 1;
- }
- return store->erase(name, off, size, scrub);
-}
-
-u64 store_part_size(const char *name)
-{
- struct storage_t *store = store_get_current();
-
- if (!store) {
- pr_info("%s %d please init storage device first\n",
- __func__, __LINE__);
- return 1;
- }
- return store->get_part_size(name);
-}
-
-u8 store_boot_copy_num(const char *name)
-{
- struct storage_t *store = store_get_current();
-
- if (!store) {
- pr_info("%s %d please init storage device first\n",
- __func__, __LINE__);
- return 1;
- }
- return store->get_copies(name);
-}
-
-u64 store_boot_copy_size(const char *name)
-{
- struct storage_t *store = store_get_current();
-
- if (!store) {
- pr_info("%s %d please init storage device first\n",
- __func__, __LINE__);
- return 1;
- }
- return store->get_copy_size(name);
-}
-
-int store_boot_read(const char *name, u8 copy, size_t size, void *buf)
-{
- struct storage_t *store = store_get_current();
-
- if (!store) {
- pr_info("%s %d please init storage device first\n",
- __func__, __LINE__);
- return 1;
- }
- return store->boot_read(name, copy, size, buf);
-}
-
-int store_boot_write(const char *name, u8 copy, size_t size, void *buf)
-{
- struct storage_t *store = store_get_current();
-
- if (!store) {
- pr_info("%s %d please init storage device first\n",
- __func__, __LINE__);
- return 1;
- }
- return store->boot_write(name, copy, size, buf);
-}
-
-int store_boot_erase(const char *name, u8 copy)
-{
- struct storage_t *store = store_get_current();
-
- if (!store) {
- pr_info("%s %d please init storage device first\n",
- __func__, __LINE__);
- return 1;
- }
- return store->boot_erase(name, copy);
-}
-
-u32 store_rsv_size(const char *name)
-{
- struct storage_t *store = store_get_current();
-
- if (!store) {
- pr_info("%s %d please init storage device first\n",
- __func__, __LINE__);
- return 1;
- }
- return store->get_rsv_size(name);
-}
-
-int store_rsv_read(const char *name, size_t size, void *buf)
-{
- struct storage_t *store = store_get_current();
-
- if (!store) {
- pr_info("%s %d please init storage device first\n",
- __func__, __LINE__);
- return 1;
- }
- return store->read_rsv(name, size, buf);
-}
-
-int store_rsv_write(const char *name, size_t size, void *buf)
-{
- struct storage_t *store = store_get_current();
-
- if (!store) {
- pr_info("%s %d please init storage device first\n",
- __func__, __LINE__);
- return 1;
- }
- return store->write_rsv(name, size, buf);
-}
-
-int store_rsv_erase(const char *name)
-{
- struct storage_t *store = store_get_current();
-
- if (!store) {
- pr_info("%s %d please init storage device first\n",
- __func__, __LINE__);
- return 1;
- }
- return store->erase_rsv(name);
-}
-
-int store_rsv_protect(const char *name, bool ops)
-{
- struct storage_t *store = store_get_current();
-
- if (!store) {
- pr_info("%s %d please init storage device first\n",
- __func__, __LINE__);
- return 1;
- }
- return store->protect_rsv(name, ops);
-}
-
-static int do_store_init(cmd_tbl_t *cmdtp,
- int flag, int argc, char * const argv[])
-{
- u32 init_flag = 1;
- u8 ret = 0;
-
- if (unlikely(argc != 2 && argc != 3))
- return CMD_RET_USAGE;
-
- if (argc == 3)
- init_flag = simple_strtoul(argv[2], NULL, 10);
-
- /*Returns a nonzero value: device index*/
- if (store_init(init_flag))
- ret = 0;
- else ret = 1;
- return ret;
-}
-
-void store_print_device(struct storage_t *store_dev)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(device_list); i++)
- if (store_dev->type & device_list[i].index)
- pr_info("device type: [%s]\n", device_list[i].type);
- pr_info("name %s\n", store_dev->info.name);
- pr_info("id :");
- for (i = 0; i < ARRAY_SIZE(store_dev->info.id); i++)
- pr_info(" 0x%x", store_dev->info.id[i]);
- pr_info("\n");
- pr_info("read unit %d\n", store_dev->info.read_unit);
- pr_info("write unit %d\n", store_dev->info.write_unit);
- pr_info("erase unit %d\n", store_dev->info.erase_unit);
- pr_info("total size %lld\n", store_dev->info.caps);
- if (store_dev->info.mode)
- pr_info("bootloader in discrete mode : %d\n",
- store_dev->info.mode);
- else
- pr_info("bootloader in compact mode : %d\n",
- store_dev->info.mode);
-}
-
-static int do_store_device(cmd_tbl_t *cmdtp,
- int flag, int argc, char * const argv[])
-{
- if (argc == 2) {
- struct storage_t *store_dev, *dev;
- struct list_head *entry;
-
- store_dev = store_get_current();
- pr_info("current device:\n");
- pr_info("----------------------------------\n");
- store_print_device(store_dev);
- pr_info("----------------------------------\n");
- list_for_each(entry, &store_dev->list) {
- dev = list_entry(entry, struct storage_t, list);
- pr_info("valid device:\n");
- pr_info("----------------------------------\n");
- store_print_device(dev);
- pr_info("----------------------------------\n");
- }
- return 0;
- } else if (argc == 3) {
- char *name = NULL;
- int i = 0, ret = 0;
- name = argv[2];
- for (i = 0; i < ARRAY_SIZE(device_list); i++)
- if (!strcmp(name, device_list[i].type)) {
-
- ret = store_set_device(device_list[i].index);
- if (!ret) {
- pr_info("now current device is: %s\n",
- name);
- return 0;
- }
- }
- pr_info("%s %d no such device: %s\n",
- __func__, __LINE__, name);
- return ret;
- }
- return CMD_RET_USAGE;
-}
-
-#ifdef CONFIG_AML_MTD
-extern int is_mtd_store_boot_area(const char *part_name);
-#endif
-static int do_store_erase(cmd_tbl_t *cmdtp,
- int flag, int argc, char * const argv[])
-{
- struct storage_t *store = store_get_current();
- unsigned long offset;
- size_t size = 0;
- char *name = NULL;
- char *s;
- int scrub_flag = 0;
-
- const char *scrub =
- "Warning: scrub_flag is 1!!!!"
- "scrub operation!!!\n"
- "will erase oob area\n"
- "There is no reliable way to recover them.\n"
- " "
- "are sure of what you are doing!\n"
- "\nReally erase this NAND flash? <y/N>\n";
-
- if (!store) {
- pr_info("%s %d please init your storage device first!\n",
- __func__, __LINE__);
- return CMD_RET_FAILURE;
- }
-
- if (strncmp(argv[1], "scrub", 5) == 0)
- scrub_flag = 1;
-
- if (scrub_flag == 1) {
- puts(scrub);
- if (!confirm_yesno()) {
- printf("erase aborted\n");
- return 1;
- }
- }
-
- /*store erase.chip*/
- s = strchr(argv[1], '.');
- if (s != NULL && strcmp(s, ".chip") == 0) {
- offset = 0;
- } else {
- /*store erase normal, partition name can't NULL*/
- if (unlikely(argc != 5))
- return CMD_RET_USAGE;
-
- size = (size_t)simple_strtoul(argv[argc - 1], NULL, 16);
- offset = simple_strtoul(argv[argc - 2], NULL, 16);
- name = argv[2];
-#ifdef CONFIG_AML_MTD
- if (is_mtd_store_boot_area(name)) {
- pr_info("%s %d please enter normal partition name except tpl area!\n",
- __func__, __LINE__);
- return CMD_RET_FAILURE;
- }
-#endif
- }
- return store->erase(name, offset, size, scrub_flag);
-}
-
-static int do_store_read(cmd_tbl_t *cmdtp,
- int flag, int argc, char * const argv[])
-{
- struct storage_t *store = store_get_current();
- unsigned long offset, addr;
- size_t size;
- char *name = NULL;
-
- if (!store) {
- pr_info("%s %d please init your storage device first!\n",
- __func__, __LINE__);
- return CMD_RET_FAILURE;
- }
-
- if (unlikely(argc != 5 && argc != 6))
- return CMD_RET_USAGE;
-
- addr = simple_strtoul(argv[2], NULL, 16);
- size = (size_t)simple_strtoul(argv[argc - 1], NULL, 16);
- offset = simple_strtoul(argv[argc - 2], NULL, 16);
- if (argc == 6)
- name = argv[3];
-#ifdef CONFIG_AML_MTD
- if (is_mtd_store_boot_area(name)) {
- pr_info("%s %d please enter normal partition name except tpl area!\n",
- __func__, __LINE__);
- return CMD_RET_FAILURE;
- }
-#endif
- return store->read(name, offset, size, (u_char *)addr);
-}
-
-static int do_store_write(cmd_tbl_t *cmdtp,
- int flag, int argc, char * const argv[])
-{
- struct storage_t *store = store_get_current();
- unsigned long offset, addr;
- size_t size;
- char *name = NULL;
-
- if (!store) {
- pr_info("%s %d please init your storage device first!\n",
- __func__, __LINE__);
- return CMD_RET_FAILURE;
- }
-
- if (unlikely(argc != 5 && argc != 6))
- return CMD_RET_USAGE;
-
- addr = simple_strtoul(argv[2], NULL, 16);
- offset = simple_strtoul(argv[argc - 2], NULL, 16);
- size = (size_t)simple_strtoul(argv[argc - 1], NULL, 16);
- if (argc == 6)
- name = argv[3];
-#ifdef CONFIG_AML_MTD
- if (is_mtd_store_boot_area(name)) {
- pr_info("%s %d please enter normal partition name except tpl area!\n",
- __func__, __LINE__);
- return CMD_RET_FAILURE;
- }
-#endif
- return store->write(name, offset, size, (u_char *)addr);
-}
-
-static int do_store_boot_read(cmd_tbl_t *cmdtp,
- int flag, int argc, char * const argv[])
-{
- struct storage_t *store = store_get_current();
- unsigned long addr;
- size_t size;
- u8 cpy;
- char *name;
-
- if (!store) {
- pr_info("%s %d please init your storage device first!\n",
- __func__, __LINE__);
- return CMD_RET_FAILURE;
- }
-
- if (unlikely(argc != 6))
- return CMD_RET_USAGE;
-
- name = argv[2];
- addr = (unsigned long)simple_strtoul(argv[3], NULL, 16);
- cpy = (u8)simple_strtoul(argv[4], NULL, 16);
- size = (size_t)simple_strtoul(argv[5], NULL, 16);
-
- return store->boot_read(name, cpy, size, (u_char *)addr);
-}
-
-static int do_store_boot_write(cmd_tbl_t *cmdtp,
- int flag, int argc, char * const argv[])
-{
- struct storage_t *store = store_get_current();
- unsigned long addr;
- size_t size;
- u8 cpy = BOOT_OPS_ALL;
- char *name;
-
- if (!store) {
- pr_info("%s %d please init your storage device first!\n",
- __func__, __LINE__);
- return CMD_RET_FAILURE;
- }
-
- if (unlikely(argc != 5 && argc != 6))
- return CMD_RET_USAGE;
-
- name = argv[2];
- addr = (unsigned long)simple_strtoul(argv[3], NULL, 16);
- size = (size_t)simple_strtoul(argv[argc - 1], NULL, 16);
- if (argc == 6)
- cpy = (u8)simple_strtoul(argv[4], NULL, 16);
-
- return store->boot_write(name, cpy, size, (u_char *)addr);
-}
-
-static int do_store_boot_erase(cmd_tbl_t *cmdtp,
- int flag, int argc, char * const argv[])
-{
- struct storage_t *store = store_get_current();
- u8 cpy = BOOT_OPS_ALL;
- char *name;
-
- if (!store) {
- pr_info("%s %d please init your storage device first!\n",
- __func__, __LINE__);
- return CMD_RET_FAILURE;
- }
-
- if (unlikely(argc != 3 && argc != 4))
- return CMD_RET_USAGE;
-
- name = argv[2];
- if (argc == 4)
- cpy = (u8)simple_strtoul(argv[3], NULL, 16);
-
- return store->boot_erase(name, cpy);
-}
-
-static int do_store_rsv_ops(cmd_tbl_t *cmdtp,
- int flag, int argc, char * const argv[])
-{
- struct storage_t *store = store_get_current();
- char *name = NULL;
-
- if (!store) {
- pr_info("%s %d please init your storage device first!\n",
- __func__, __LINE__);
- return CMD_RET_FAILURE;
- }
-
- if (!strcmp(argv[2], "erase")) {
- if (argc == 3)
- ;
- else if (argc == 4)
- name = argv[3];
- else
- return CMD_RET_USAGE;
- return store->erase_rsv(name);
- } else if (!strcmp(argv[2], "read") ||
- !strcmp(argv[2], "write")) {
- u8 cmd = strcmp(argv[2], "read") ? 0 : 1;
- unsigned long addr = simple_strtoul(argv[4], NULL, 16);
- size_t size = (size_t)simple_strtoul(argv[5], NULL, 16);
-
- name = argv[3];
- if (unlikely(argc != 6))
- return CMD_RET_USAGE;
- if (cmd)
- return store->read_rsv(name, size, (u_char *)addr);
- else
- return store->write_rsv(name, size, (u_char *)addr);
- } else if (!strcmp(argv[2], "protect")) {
- bool flag = false;
- char *ops;
-
- if (unlikely(argc != 4 && argc != 5))
- return CMD_RET_USAGE;
-
- name = (argc == 4) ? NULL : argv[3];
- ops = argv[argc - 1];
- if (!strcmp(ops, "on"))
- flag = true;
- else if (!strcmp(ops, "off"))
- flag = false;
- return store->protect_rsv(name, flag);
- }
- return CMD_RET_USAGE;
-}
-
-static cmd_tbl_t cmd_store_sub[] = {
- U_BOOT_CMD_MKENT(init, 4, 0, do_store_init, "", ""),
- U_BOOT_CMD_MKENT(device, 4, 0, do_store_device, "", ""),
- U_BOOT_CMD_MKENT(scrub, 5, 0, do_store_erase, "", ""),
- U_BOOT_CMD_MKENT(erase, 5, 0, do_store_erase, "", ""),
- U_BOOT_CMD_MKENT(read, 6, 0, do_store_read, "", ""),
- U_BOOT_CMD_MKENT(write, 7, 0, do_store_write, "", ""),
- U_BOOT_CMD_MKENT(boot_read, 6, 0, do_store_boot_read, "", ""),
- U_BOOT_CMD_MKENT(boot_write, 6, 0, do_store_boot_write, "", ""),
- U_BOOT_CMD_MKENT(boot_erase, 4, 0, do_store_boot_erase, "", ""),
- U_BOOT_CMD_MKENT(rsv, 6, 0, do_store_rsv_ops, "", ""),
-};
-
-static int do_store(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
- cmd_tbl_t *c;
-
- if (argc < 2)
- return CMD_RET_USAGE;
-
- c = find_cmd_tbl(argv[1], cmd_store_sub, ARRAY_SIZE(cmd_store_sub));
- if (c)
- return c->cmd(cmdtp, flag, argc, argv);
-
- return CMD_RET_USAGE;
-}
-
-U_BOOT_CMD(store, CONFIG_SYS_MAXARGS, 1, do_store,
- "STORE sub-system",
- "store init [flag]\n"
- " init storage device\n"
- "store device [name]\n"
- " show or set storage device\n"
- " 'store device' command will list\n"
- " all valid storage device and print.\n"
- " 'store device [name]' will set the\n"
- " [name] device to the current device\n"
- "store read addr [partition name] off size\n"
- " read 'size' bytes from offset 'off'\n"
- " of device/partition 'partition name' to.\n"
- " address 'addr' of memory.\n"
- " if partition name NULL. read start with\n"
- " offset in normal logic area,if tpl area exist\n"
- " read offset at end of tpl area\n"
- "store write addr [partition name] off size\n"
- " write 'size' bytes to offset 'off' of\n"
- " device/partition [partition name] from\n"
- " address 'addr' of memory.\n"
- " if partition name NULL. write start with\n"
- " offset in normal logic area,if tpl area exist\n"
- " write offset at end of tpl area\n"
- "store erase [partition name] off size.\n"
- " erase 'size' bytes from offset 'off'\n"
- " of device/partition [partition name]\n"
- " partition name must't NULL\n"
- "store scrub [partition name] off size.\n"
- " erase 'size' bytes from offset 'off'\n"
- " of device/partition [partition name]\n"
- " includes oob area if the device has.\n"
- " partition name must't NULL\n"
- "store erase.chip\n"
- " erase all nand chip,except bad block\n"
- "store scrub.chip\n"
- " erase all nand chip,include bad block\n"
- "store boot_read [name] addr copy size\n"
- " read 'size' bytes from 'copy'th backup\n"
- " in [name] partition, 'copy' can't be null.\n"
- " [name]:\n"
- " in discrete mode: 'bl2'/'tpl'(fip)\n"
- " in compact mode: 'bootloader'\n"
- "store boot_write [name] addr [copy] size\n"
- " write 'size' bytes to 'copy'th backup\n"
- " in [name] partition from address\n"
- " 'addr' of memory. when the optional 'copy'\n"
- " is null, it will writes to all copies\n"
- " [name]:\n"
- " in discrete mode: 'bl2'/'tpl'(fip)\n"
- " in compact mode: 'bootloader'\n"
- "store boot_erase [name] [copy]\n"
- " erase the [name] info from 'copy'th backup\n"
- " when the optional 'copy' is null, it\n"
- " will erase all copies.\n"
- " [name]:\n"
- " in discrete mode: 'bl2'/'tpl'(fip)\n"
- " in compact mode: 'bootloader'\n"
- "store rsv read name addr size\n"
- " read 'size' bytes 'name' rsv info\n"
- " to address 'addr' of memory\n"
- " 'name' could be key/dtb/env etc...\n"
- "store rsv write name addr size\n"
- " write 'size' bytes 'name' rsv info\n"
- " from address 'addr' of memory\n"
- "store rsv erase [name]\n"
- " erase 'name' rsv info it will erase\n"
- " all rsv info when [name] is null\n"
- "store rsv protect [name] on/off\n"
- " turn on/off the rsv info protection\n"
- " it will operates all when [name] is null\n"
-);
diff --git a/cmd/amlogic/store_wrapper.c b/cmd/amlogic/store_wrapper.c
new file mode 100644
index 0000000..78a5c86
--- /dev/null
+++ b/cmd/amlogic/store_wrapper.c
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <amlogic/storage.h>
+#include <linux/mtd/mtd.h>
+
+#define debugP(fmt...) //printf("Dbg[WRP]L%d:", __LINE__),printf(fmt)
+#define errorP(fmt...) printf("Err[WRP]L%d:", __LINE__),printf(fmt)
+#define wrnP(fmt...) printf("wrn:"fmt)
+#define MsgP(fmt...) printf("[WRP]"fmt)
+
+//change part logic offset to physical address for mtd, not changed if not MTD
+static int mtd_find_phy_off_by_lgc_off(const char* partName, const loff_t logicAddr, loff_t* phyAddr)
+{
+ if (!(BOOT_NAND_MTD == store_get_type() || BOOT_SNAND == store_get_type())) {
+ *phyAddr = logicAddr;
+ return 0;
+ }
+#ifndef CONFIG_CMD_MTD
+ MsgP("Exception, boottype is MTD or snand, BUT CMD_MTD not defined\n");
+#else
+#ifndef CONFIG_USB_GADGET_CRG
+ struct mtd_info * mtdPartInf = NULL;
+ mtdPartInf = get_mtd_device_nm(partName);
+#endif
+ if (IS_ERR(mtdPartInf)) {
+ errorP("device(%s) is err\n", partName);
+ return CMD_RET_FAILURE;
+ }
+ const unsigned eraseSz = mtdPartInf->erasesize;
+ const unsigned offsetInBlk = logicAddr & (eraseSz - 1);
+ loff_t off = 0;
+ int canSpeedUp = 0;
+ static struct {
+ loff_t lastblkPhyOff;
+ loff_t lastblkLgcOff;
+ char partName[64];
+ }_map4SpeedUp = {0};
+ if ( !strcmp(partName, _map4SpeedUp.partName) && logicAddr >= _map4SpeedUp.lastblkLgcOff) {
+ canSpeedUp = 1;
+ } else {
+ _map4SpeedUp.lastblkLgcOff = _map4SpeedUp.lastblkPhyOff = 0;
+ strncpy(_map4SpeedUp.partName, partName, 63);
+ }
+
+ if ( canSpeedUp ) {
+ if ( logicAddr >= _map4SpeedUp.lastblkLgcOff &&
+ logicAddr < _map4SpeedUp.lastblkLgcOff + eraseSz) {
+ *phyAddr = _map4SpeedUp.lastblkPhyOff + offsetInBlk;
+ return 0;
+ }
+ _map4SpeedUp.lastblkPhyOff += eraseSz;
+ _map4SpeedUp.lastblkLgcOff += eraseSz;
+ off = _map4SpeedUp.lastblkPhyOff;
+ }
+ for (; off < mtdPartInf->size; off += eraseSz, _map4SpeedUp.lastblkPhyOff += eraseSz) {
+#ifndef CONFIG_USB_GADGET_CRG
+ if (mtd_block_isbad(mtdPartInf, off)) {
+ MsgP("bad blk at %08llx\n", (unsigned long long)off);
+ } else {
+ if ( logicAddr >= _map4SpeedUp.lastblkLgcOff &&
+ logicAddr < _map4SpeedUp.lastblkLgcOff + eraseSz) {
+ *phyAddr = _map4SpeedUp.lastblkPhyOff + offsetInBlk;
+ return 0;
+ }
+ _map4SpeedUp.lastblkLgcOff += eraseSz;
+ }
+#endif
+ }
+#endif// #ifndef CONFIG_CMD_MTD
+ return __LINE__;
+}
+
+int store_logic_write(const char *name, loff_t off, size_t size, void *buf)
+{
+ loff_t phyAddr = 0;
+ if (mtd_find_phy_off_by_lgc_off(name, off, &phyAddr)) {
+ errorP("Fail find phy addr\n");
+ return -__LINE__;
+ }
+ return store_write(name, phyAddr, size, buf);
+}
+
+int store_logic_read(const char *name, loff_t off, size_t size, void *buf)
+{
+ loff_t phyAddr = 0;
+ if (mtd_find_phy_off_by_lgc_off(name, off, &phyAddr)) {
+ errorP("Fail find phy addr\n");
+ return -__LINE__;
+ }
+ return store_read(name, phyAddr, size, buf);
+}
+
+//get partition logic size
+u64 store_logic_cap(const char* partName)
+{
+ if (!(BOOT_NAND_MTD == store_get_type() || BOOT_SNAND == store_get_type())) {
+ return store_part_size(partName);
+ }
+
+#ifndef CONFIG_CMD_MTD
+ MsgP("Exception, boottype is MTD or snand, BUT CMD_MTD not defined\n");
+ return 0;
+#else
+ //get mtd part logic size (i.e, not including the bad blocks)
+ struct mtd_info * mtdPartInf = NULL;
+ uint64_t partSzLgc = 0;
+ loff_t off = 0;
+
+ mtdPartInf = get_mtd_device_nm(partName);
+ if (IS_ERR(mtdPartInf)) {
+ errorP("device(%s) is err\n", partName);
+ return CMD_RET_FAILURE;
+ }
+ const unsigned eraseSz = mtdPartInf->erasesize;
+ const uint64_t partSzPhy = mtdPartInf->size;
+
+ partSzLgc = partSzPhy;
+ for (; off < partSzPhy; off += eraseSz) {
+ if (mtd_block_isbad(mtdPartInf, off)) {
+ partSzLgc -= eraseSz;
+ }
+ }
+ return partSzLgc;
+#endif// #ifndef CONFIG_CMD_MTD
+}
+
+int store_gpt_ops(size_t sz, void *buf, int isWr)
+{
+ int ret = 0;
+
+ if (!sz || sz >= 0x100000) {
+ errorP("sz 0x%zx to large\n", sz);
+ return -__LINE__;
+ }
+
+ if (isWr)
+ ret = store_gpt_write(buf);
+ else
+ ret = store_gpt_read(buf);
+
+ return ret;
+}
+
diff --git a/cmd/bmp.c b/cmd/bmp.c
index f13db13..44fef6c 100644
--- a/cmd/bmp.c
+++ b/cmd/bmp.c
@@ -63,7 +63,7 @@
bmp = dst;
/* align to 32-bit-aligned-address + 2 */
- bmp = (bmp_image_t *)((((unsigned int)dst + 1) & ~3) + 2);
+ bmp = (bmp_image_t *)((((ulong)dst + 1) & ~3) + 2);
if (gunzip(bmp, CONFIG_SYS_VIDEO_LOGO_MAX_SIZE, (uchar *)addr, &len) != 0) {
free(dst);
@@ -290,6 +290,21 @@
printf("There is no valid bmp file at the given address\n");
return 1;
}
+ /*Logo only supports compression of header files as BI_BITFIELDS && RGB565 BMP format*/
+ u32 bit_count = le32_to_cpu(bmp->header.bit_count);
+ if (bit_count == 16) {
+ u32 compression = le32_to_cpu(bmp->header.compression);
+ if (compression != BI_BITFIELDS) {
+ printf("Error: logo only supports BI_BITFIELDS\n");
+ return 1;
+ } else {
+ u32* colortable = (u32*)(&bmp->color_table);
+ if (colortable[0] != 0xf800 && colortable[1] != 0x7e0 && colortable[2] != 0x1f) {
+ printf("Error: logo only supports RGB565 forma\n");
+ return 1;
+ }
+ }
+ }
#if defined(CONFIG_LCD)
ret = lcd_display_bitmap((ulong)bmp, x, y);
diff --git a/cmd/bootm.c b/cmd/bootm.c
index b887890..16b401e 100644
--- a/cmd/bootm.c
+++ b/cmd/bootm.c
@@ -90,20 +90,33 @@
return ret;
}
-static int is_secure_boot_enabled(void)
+static void recovery_mode_process(void)
{
- const unsigned long cfg10 = readl(AO_SEC_SD_CFG10);
- return ( cfg10 & (0x1<< 4) );
+ char *reboot_mode_s = NULL;
+ char *upgrade_step_s = NULL;
+
+ reboot_mode_s = env_get("reboot_mode");
+ upgrade_step_s = env_get("upgrade_step");
+ if ((!reboot_mode_s) || (!upgrade_step_s))
+ return;
+
+ if ((!strcmp(reboot_mode_s, "recovery")) || (!strcmp(reboot_mode_s, "update"))
+ || (!strcmp(reboot_mode_s, "factory_reset")) || (!strcmp(upgrade_step_s, "3")))
+ {
+ run_command("amlbootsta -p -s",0);
+ }
}
+
/*******************************************************************/
/* bootm - boot application image from image in memory */
/*******************************************************************/
+//temp solution for A1, as A1 secure boot not ready yet...
+#include <amlogic/cpu_id.h>
+//end
int do_bootm(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
{
- ulong img_addr;
- char *avb_s;
int nRet = 0;
#ifdef CONFIG_NEEDS_MANUAL_RELOC
static int relocated = 0;
@@ -136,83 +149,31 @@
if ((*endp != 0) && (*endp != ':') && (*endp != '#'))
return do_bootm_subcommand(cmdtp, flag, argc, argv);
}
+
unsigned int nLoadAddr = GXB_IMG_LOAD_ADDR; //default load address
if (argc > 0)
{
char *endp;
nLoadAddr = simple_strtoul(argv[0], &endp, 16);
- pr_info("aml log : addr = 0x%x\n",nLoadAddr);
+ //printf("aml log : addr = 0x%x\n",nLoadAddr);
}
- const char *is_boot_external_image = env_get("boot_external_image");
- if (is_boot_external_image && !strcmp(is_boot_external_image, "1")) {
- printf("aml log : boot from usb\n");
- nRet = aml_sec_boot_check(AML_D_P_EXT_IMG_DECRYPT_V3, nLoadAddr, GXB_IMG_SIZE, GXB_IMG_DEC_ALL);
- } else {
- printf("aml log : boot from nand or emmc\n");
- nRet = aml_sec_boot_check(AML_D_P_IMG_DECRYPT_V3, nLoadAddr, GXB_IMG_SIZE, GXB_IMG_DEC_ALL);
- pr_info("AML_D_P_IMG_DECRYPT_V3: 0x%x\n", AML_D_P_IMG_DECRYPT_V3);
- pr_info("nLoadAddr: 0x%x\n", nLoadAddr);
- pr_info("GXB_IMG_SIZE: 0x%x\n", GXB_IMG_SIZE);
- pr_info("GXB_IMG_DEC_ALL: 0x%x\n", GXB_IMG_DEC_ALL);
- }
+ nRet = aml_sec_boot_check(AML_D_P_IMG_DECRYPT,nLoadAddr,GXB_IMG_SIZE,GXB_IMG_DEC_ALL);
+
if (nRet)
{
printf("\naml log : Sig Check %d\n",nRet);
-#ifdef CONFIG_G_AB_SYSTEM
- unsigned int sticky_reg0_val;
- unsigned int sticky_reg1_val;
- char *cur_slot;
- printf("\nVerify boot.img failure, watchdog reset and try again\n");
- /* clear successful_boot flag of the current slot when verifying boot.img failure,
- * make sure bl2 check the tries_remaining flag of the current slot after reset
- */
- cur_slot = env_get("active_slot");
- printf("cur_slot: %s\n", cur_slot);
- if (strcmp(cur_slot, "_a") == 0) {
- sticky_reg0_val = readl(P_AO_RTI_STICKY_REG0);
- sticky_reg0_val &= ~(0xff << 16);
- writel(sticky_reg0_val, P_AO_RTI_STICKY_REG0);
- }
- else if (strcmp(cur_slot, "_b") == 0) {
- sticky_reg1_val = readl(P_AO_RTI_STICKY_REG1);
- sticky_reg1_val &= ~(0xff << 16);
- writel(sticky_reg1_val, P_AO_RTI_STICKY_REG1);
- }
-#else
- //don`t return but just deadlock here
- while (1);
-#endif
- }
-#ifdef CONFIG_G_AB_SYSTEM
- /* save ab data to misc */
- run_command("sync_ab_data", 0);
- /* verify image fail, reset and try again */
- if (nRet)
- run_command("reset", 0);
-#endif
- if (is_secure_boot_enabled()) {
- /* Override load address argument to skip secure boot header (512).
- * Only skip if secure boot so normal boot can use plain boot.img
- */
- img_addr = genimg_get_kernel_addr(argc < 1 ? NULL : argv[0]);
- img_addr += 512;
- char argv0_new[12] = {0};
- char *argv_new = (char*)&argv0_new;
- snprintf(argv0_new, sizeof(argv0_new), "%lx", img_addr);
- argc = 1;
- argv = (char**)&argv_new;
+ return nRet;
}
- avb_s = env_get("avb2");
- if (avb_s == NULL) {
#ifdef CONFIG_CMD_BOOTCTOL_AVB
+ char *avb_s = env_get("avb2");
+ if (avb_s == NULL) {
run_command("get_avb_mode;", 0);
avb_s = env_get("avb2");
-#endif
}
- pr_info("avb2: %s\n", avb_s);
+ printf("avb2: %s\n", avb_s);
if (strcmp(avb_s, "1") == 0) {
AvbSlotVerifyData* out_data;
char *bootargs = NULL;
@@ -220,6 +181,7 @@
const char *bootstate_o = "androidboot.verifiedbootstate=orange";
const char *bootstate_g = "androidboot.verifiedbootstate=green";
const char *bootstate = NULL;
+ uint8_t vbmeta_digest[AVB_SHA256_DIGEST_SIZE];
nRet = avb_verify(&out_data);
printf("avb verification: locked = %d, result = %d\n", !is_device_unlocked(), nRet);
if (is_device_unlocked()) {
@@ -253,19 +215,47 @@
if (!bootargs) {
bootargs = "\0";
}
- if (is_device_unlocked())
- bootstate = bootstate_o;
- else
- bootstate = bootstate_g;
- newbootargs = malloc(strlen(bootargs) + strlen(out_data->cmdline) + strlen(bootstate) + 1 + 1 + 1);
- if (!newbootargs) {
- printf("failed to allocate buffer for bootarg\n");
- return -1;
+
+ if (out_data) {
+ keymaster_boot_params boot_params;
+ const int is_dev_unlocked = is_device_unlocked();
+
+ boot_params.device_locked = is_dev_unlocked? 0: 1;
+ if (is_dev_unlocked) {
+ bootstate = bootstate_o;
+ boot_params.verified_boot_state = 2;
+ }
+ else {
+ bootstate = bootstate_g;
+ boot_params.verified_boot_state = 0;
+ }
+ memcpy(boot_params.verified_boot_key, boot_key_hash,
+ sizeof(boot_params.verified_boot_key));
+
+ avb_slot_verify_data_calculate_vbmeta_digest(
+ out_data, AVB_DIGEST_TYPE_SHA256, vbmeta_digest);
+ memcpy(boot_params.verified_boot_hash, vbmeta_digest,
+ sizeof(boot_params.verified_boot_hash));
+
+ if (set_boot_params(&boot_params) < 0) {
+ printf("failed to set boot params.\n");
+ }
+
+ newbootargs = malloc(strlen(bootargs) + strlen(out_data->cmdline) + strlen(bootstate) + 1 + 1 + 1);
+ if (!newbootargs) {
+ printf("failed to allocate buffer for bootarg\n");
+ return -1;
+ }
+ sprintf(newbootargs, "%s %s %s", bootargs, out_data->cmdline, bootstate);
+ env_set("bootargs", newbootargs);
+ free(newbootargs);
+ newbootargs = NULL;
+ avb_slot_verify_data_free(out_data);
}
- sprintf(newbootargs, "%s %s %s", bootargs, out_data->cmdline, bootstate);
- env_set("bootargs", newbootargs);
- avb_slot_verify_data_free(out_data);
}
+#endif//CONFIG_CMD_BOOTCTOL_AVB
+
+ recovery_mode_process();
return do_bootm_states(cmdtp, flag, argc, argv, BOOTM_STATE_START |
BOOTM_STATE_FINDOS | BOOTM_STATE_FINDOTHER |
BOOTM_STATE_LOADOS |
@@ -426,7 +416,7 @@
case IMAGE_FORMAT_FIT:
puts(" FIT image found\n");
- if (fit_check_format(hdr, IMAGE_SIZE_INVAL)) {
+ if (!fit_check_format(hdr)) {
puts("Bad FIT image format!\n");
return 1;
}
@@ -499,7 +489,7 @@
#endif
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
- if (fit_check_format(hdr, IMAGE_SIZE_INVAL))
+ if (!fit_check_format(hdr))
goto next_sector;
printf("FIT Image at %08lX:\n", (ulong)hdr);
@@ -579,7 +569,7 @@
return ret;
}
- if (fit_check_format(imgdata, IMAGE_SIZE_INVAL)) {
+ if (!fit_check_format(imgdata)) {
free(imgdata);
return 0;
}
diff --git a/cmd/clkmsr.c b/cmd/clkmsr.c
new file mode 100644
index 0000000..f2574a2
--- /dev/null
+++ b/cmd/clkmsr.c
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/clock.h>
+
+extern int clk_msr(int index);
+
+static int do_clkmsr(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int index = 0xff;
+
+ if (argc == 2)
+ index = simple_strtoul(argv[1], NULL, 10);
+
+ clk_msr(index);
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ clkmsr, 2, 1, do_clkmsr,
+ "Amlogic measure clock",
+ " - measure PLL clock.\n"
+ "\n"
+ "clkmsr [index]"
+ "\n"
+);
diff --git a/cmd/cmd_dsprun.c b/cmd/cmd_dsprun.c
new file mode 100644
index 0000000..c86f138
--- /dev/null
+++ b/cmd/cmd_dsprun.c
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/bl31_apis.h>
+#include <asm/arch/register.h>
+#include <serial.h>
+
+void dsp_reset(uint32_t id,uint32_t reset_addr)
+{
+ uint32_t StatVectorSel;
+ uint32_t strobe = 1;
+ //address remap
+ printf("start_dsp \n");
+ //*P_DSP_REMAP2 = 0x3000fff0; //replace the highest 12bits 0xfffxxxxx with 0x300xxxxx
+
+ StatVectorSel = (reset_addr!= 0xfffa0000);
+
+ //open the Dreset, Breset, irq_clken
+ if (id == 0) { //dspa
+ init_dsp(id,reset_addr, (0x1 | StatVectorSel<<1 | strobe<<2));
+ udelay(50);
+
+ writel((readl(DSP_CFG0) &( ~(0xffff <<0))) | (0x2018 << 0) | (1<<29), DSP_CFG0);
+ udelay(10);
+
+ writel(readl(DSP_CFG0) | (1<<31), DSP_CFG0); //Dreset deassert
+ udelay(10);
+
+ writel(readl(DSP_CFG0) & ~(1<<31), DSP_CFG0); //Dreset assert
+ udelay(10);
+
+ writel(readl(DSP_CFG0) | (1<<30), DSP_CFG0); //Breset deassert
+ udelay(10);
+
+ writel(readl(DSP_CFG0) & ~(1<<30), DSP_CFG0); //Breset
+ udelay(10);
+ printf("DSP_CFG0 : value_0x%8x \n",readl(DSP_CFG0));
+ } else {
+ init_dsp(id,reset_addr, (0x1 | StatVectorSel<<1 | strobe<<2));
+ udelay(50);
+ writel((readl(DSPB_CFG0) & (~(0xffff <<0))) | (0x2019 << 0) | (1<<29), DSPB_CFG0);
+ udelay(10);
+ writel(readl(DSPB_CFG0) & ~(1<<31), DSPB_CFG0); //Dreset
+ udelay(10);
+ writel(readl(DSPB_CFG0) & ~(1<<30), DSPB_CFG0); //Breset
+ udelay(10);
+ printf("DSPB_CFG0 : value_0x%8x \n",readl(DSPB_CFG0));
+ }
+}
+
+static int do_dsprun(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned long addr;
+ unsigned int dspid;
+ int ret=0;
+ if (argc <= 1) {
+ printf("plese input dsp boot args:id, addrss, clk!\n");
+ return CMD_RET_USAGE;
+ }
+ dspid = simple_strtoul(argv[1], NULL, 16);
+ addr = simple_strtoul(argv[2], NULL, 16);
+ printf("dsp%d boot \n",dspid);
+ printf("dspboot start address:0x%lx\n",addr);
+ dsp_reset(dspid, addr);
+ printf("dsp init over! \n");
+ return ret;
+}
+
+
+U_BOOT_CMD(
+ dsprun, 3, 1, do_dsprun,
+ "load dspboot.bin from ddr address",
+ "arg[0]: cmd\n"
+ "arg[1]: dspid \n"
+ "arg[2]: dspboot.bin load address!"
+);
+
diff --git a/cmd/cmd_dspset.c b/cmd/cmd_dspset.c
new file mode 100644
index 0000000..d801884
--- /dev/null
+++ b/cmd/cmd_dspset.c
@@ -0,0 +1,128 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/bl31_apis.h>
+#include <asm/arch/register.h>
+#include <serial.h>
+
+
+/*
+ * clk_util_set_dsp_clk
+ * freq_sel:
+ * 1:400MHz fclk_5
+ * 2:500MHz fclk_2/2
+ * 4:333MHz fclk_3/2
+ * 5:250Mhz fclk_2/4
+ * 6:200Mhz fclk_5/2
+ * 7:100Mhz fclk_5/4
+ * 8:24Mhz oscin
+ * 10:3Mhz oscin/8
+ * others:400MHz fclk_5
+ */
+
+// --------------------------------------------------
+// clk_util_set_dsp_clk
+// --------------------------------------------------
+void clk_util_set_dsp_clk(uint32_t id, uint32_t freq_sel)
+{
+ uint32_t control;
+ uint32_t clk_sel;
+ uint32_t clk_div;
+ uint32_t addr;
+
+ switch ( id ) {
+ case 0: addr = CLKTREE_DSPA_CLK_CTRL0;break;
+ default : addr = CLKTREE_DSPB_CLK_CTRL0;break;
+ }
+
+ // Make sure not busy from last setting and we currently match the last setting
+
+
+ control = readl(addr);
+ printf("CLKTREE_DSP_CLK_CTRL0 value 0x%x \n",control);
+
+ switch (freq_sel)
+ {
+ case 1 : clk_sel = 3; clk_div =0; printf ("CLK_UTIL:dsp[%d]:fclk5:400MHz\n" ,id); break;
+ case 2 : clk_sel = 1; clk_div =1; printf ("CLK_UTIL:dsp[%d]:fclk2/2:500MHz\n" ,id); break;
+ //case 3 : clk_sel = 1; clk_div =0; printf ("CLK_UTIL:dsp[%d]:fclk/3:667MHz\n" ,id); break;
+ case 4 : clk_sel = 2; clk_div =1; printf ("CLK_UTIL:dsp[%d]:fclk3/2:333MHz\n" ,id); break;
+ case 5 : clk_sel = 1; clk_div =3; printf ("CLK_UTIL:dsp[%d]:fclk2/4:250MHz\n",id); break;
+ case 6 : clk_sel = 3; clk_div =1; printf ("CLK_UTIL:dsp[%d]:fclk5/2:200MHz\n",id); break;
+ case 7 : clk_sel = 3; clk_div =3; printf ("CLK_UTIL:dsp[%d]:fclk5/4:100MHz\n",id); break;
+ case 8 : clk_sel = 0; clk_div =0; printf ("CLK_UTIL:dsp[%d]:oscin:24MHz\n",id); break;
+ case 10 : clk_sel = 0; clk_div =7; printf ("CLK_UTIL:dsp[%d]:oscin/8:3MHz\n",id); break;
+ default : clk_sel = 3; clk_div =0; printf ("CLK_UTIL:dsp[%d]:fclk5:400MHz\n" ,id); break;
+ }
+
+ if (control & (1 << 15)) { //if sync_mux ==1, sel mux 0
+ control = (control & ~( ( 1<<15) | (0x3ff<<0) | (0x7 <<10) ) ) | (1<<13)| (1<<29) | (clk_div<<0) | (clk_sel<<10);
+ } else {
+ control = (control & ~( ( 1<<15) | (0x3ff<<16) | (0x7 <<26) ) ) | (1<<13)| (1<<29) | (clk_div<<16) | (clk_sel<<26) | (1<<15);
+ }
+ printf("CLKTREE_DSP_CLK_CTRL0 value 0x%x \n",control);
+ writel(control,addr);
+ printf("CLKTREE_DSP_CLK_CTRL0 value 0x%x \n",readl(addr));
+
+}
+
+void dsp_clk_init(unsigned int dspid, uint32_t freq_sel) {
+ clk_util_set_dsp_clk(dspid,freq_sel);
+}
+
+void dsp_power_set(unsigned int dspid, uint32_t powerflag) {
+ power_set_dsp(dspid,powerflag);
+}
+
+
+static int do_dspset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int dspid;
+ uint32_t freq_sel;
+ uint32_t powerflag;
+ int ret=0;
+ if (argc <= 1) {
+ printf("plese input dsp boot args:id, addrss, clk!\n");
+ return CMD_RET_USAGE;
+ }
+ dspid = simple_strtoul(argv[1], NULL, 16);
+ freq_sel = simple_strtoul(argv[2], NULL, 16);
+ powerflag = simple_strtoul(argv[3], NULL, 16);
+ printf("dsp%d boot \n",dspid);
+ printf("dsp clk num:%d\n",freq_sel);
+ if (powerflag == 1)
+ printf("power on dsp init \n");
+ else
+ printf("power off dsp init \n");
+
+// writel32(readl(CLKTREE_SYS_CLK_EN0) | (1<<30),CLKTREE_SYS_CLK_EN0);
+// printf("CLKTREE_SYS_CLK_EN0 value 0x%x \n",readl(CLKTREE_SYS_CLK_EN0));
+
+ dsp_clk_init(dspid, freq_sel);
+ udelay(10);
+ dsp_power_set(dspid, powerflag) ;
+ printf("dsp init CLK, power over! \n");
+
+ return ret;
+}
+
+
+U_BOOT_CMD(
+ dspset, 4, 1, do_dspset,
+ "set dsp clk, power domain",
+ "\n arg[0]: cmd\n"
+ "arg[1]: dspid \n"
+ "arg[2]: dsp clk set 1:400M 2:500M 4:333M 5:250M 6:200M 7:100M 8 :24M \n"
+ "arg[3]: power on [1] / power off [0]"
+);
+
+
+
+
diff --git a/cmd/cmd_startdsp.c b/cmd/cmd_startdsp.c
new file mode 100644
index 0000000..81cf174
--- /dev/null
+++ b/cmd/cmd_startdsp.c
@@ -0,0 +1,127 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <asm/arch/cpu.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/timer.h>
+#include <asm/arch/bl31_apis.h>
+
+#include <serial.h>
+
+
+/*
+ * clk_util_set_dsp_clk
+ * freq_sel: 0:800MHz fclk_7
+ * 1:400MHz fclk_5
+ * 2:500MHz fclk_2/2
+ * 4:333MHz fclk_3/2
+ * 5:250Mhz fclk_2/4
+ * 6:200Mhz fclk_5/2
+ * 7:100Mhz fclk_5/4
+ * 8:24Mhz oscin
+ * others:286MHz fclk/7
+ */
+
+void set_dsp_clk(uint32_t id, uint32_t freq_sel)
+{
+ int control;
+ uint32_t clk_sel;
+ uint32_t clk_div;
+ uint32_t addr = 0;
+
+ switch ( id )
+ {
+ case 0 : addr = CLKCTRL_DSPA_CLK_CTRL0; break;
+ case 1 : addr = CLKCTRL_DSPB_CLK_CTRL0; break;
+ default : break;
+ }
+ // Make sure not busy from last setting and we currently match the last setting
+
+ control = readl(addr);
+ printf("control = 0x%x \n", control);
+ printf ("CLKCTRL_DSP_CLK_CTRL0 =%x", readl(addr));
+ printf ("\n");
+
+ switch (freq_sel)
+ {
+ case 0 : clk_sel = 1; clk_div =0; printf ("CLK_UTIL:dsp[]:fclk2p5:800MHz\n") ; break;
+ case 1 : clk_sel = 3; clk_div =0; printf ("CLK_UTIL:dsp[]:fclk5:400MHz\n") ; break;
+ case 2 : clk_sel = 5; clk_div =0; printf ("CLK_UTIL:dsp[]:fclk4:500MHz\n") ; break;
+ case 3 : clk_sel = 2; clk_div =0; printf ("CLK_UTIL:dsp[]:fclk/3:667MHz\n") ; break;
+ case 4 : clk_sel = 2; clk_div =1; printf ("CLK_UTIL:dsp[]:fclk3/2:333MHz\n") ; break;
+ case 5 : clk_sel = 5; clk_div =1; printf ("CLK_UTIL:dsp[]:fclk4/2:250MHz\n") ; break;
+ case 6 : clk_sel = 3; clk_div =1; printf ("CLK_UTIL:dsp[]:fclk5/2:200MHz\n") ; break;
+ case 7 : clk_sel = 3; clk_div =3; printf ("CLK_UTIL:dsp[]:fclk5/4:100MHz\n") ; break;
+ case 8 : clk_sel = 0; clk_div =0; printf ("CLK_UTIL:dsp[]:oscin:24MHz\n") ; break;
+ case 10 : clk_sel = 0; clk_div =7; printf ("CLK_UTIL:dsp[]:oscin/8:3MHz\n") ; break;
+ default : clk_sel = 3; clk_div =0; printf ("CLK_UTIL:dsp[]:fclk5:400MHz\n") ; break;
+ }
+
+ if (control & (1 << 15)) { //if sync_mux ==1, sel mux 0
+ control = (control & ~( ( 1<<15) | (0x3ff<<0) | (0x7 <<10) ) ) | (1<<13)| (1<<29) | (clk_div<<0) | (clk_sel<<10);
+ } else {
+ control = (control & ~( ( 1<<15) | (0x3ff<<16) | (0x7 <<26) ) ) | (1<<13)| (1<<29) | (clk_div<<16) | (clk_sel<<26) | (1<<15);
+ }
+
+ writel(control, addr);
+
+ switch ( id )
+ {
+ case 0 : printf ("CLKCTRL_DSPA_CLK_CTRL0 =%x\n", readl(addr)); break;
+ case 1 : printf ("CLKCTRL_DSPB_CLK_CTRL0 =%x\n", readl(addr)); break;
+ default : break;
+ }
+}
+
+static int do_startdsp(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ uint32_t addr;
+ uint32_t dspid;
+ uint32_t freq_sel;
+ uint32_t cfg0;
+ uint32_t StatVectorSel;
+ uint32_t strobe = 1;
+
+ int ret=0;
+
+ if (argc <= 1) {
+ printf("plese input dsp boot args:id, addrss, clk!\n");
+ return CMD_RET_USAGE;
+ }
+ dspid = simple_strtoul(argv[1], NULL, 16);
+ addr = simple_strtoul(argv[2], NULL, 16);
+ freq_sel = simple_strtoul(argv[3], NULL, 16);
+
+ printf("dsp%d boot \n",dspid);
+ printf("dspboot start address:0x%d\n",addr);
+ printf("dsp clk num:%d\n",freq_sel);
+
+ StatVectorSel = (addr != 0xfffa0000);
+ cfg0 = 0x1 | StatVectorSel << 1 | strobe << 2;
+
+ power_set_dsp(dspid,1);
+ udelay(100);
+ set_dsp_clk(dspid,freq_sel);
+ udelay(100);
+ init_dsp(dspid, addr, cfg0);
+ printf("dsp init over! \n");
+ return ret;
+}
+
+
+U_BOOT_CMD(
+ startdsp, 4, 1, do_startdsp,
+ "load dspboot.bin from address",
+ "\narg[0]: cmd\n"
+ "arg[1]: dspid \n"
+ "arg[2]: dspboot.bin load address!\n"
+ "arg[3]: dsp clk set 0:800M 1:400M 2:500M 4:333M 5:250M 6:200M 7:100M 8 :24M"
+);
+
+
+
+
diff --git a/cmd/disk.c b/cmd/disk.c
index 294fc11..dcc36a6 100644
--- a/cmd/disk.c
+++ b/cmd/disk.c
@@ -110,7 +110,7 @@
/* This cannot be done earlier,
* we need complete FIT image in RAM first */
if (genimg_get_format((void *) addr) == IMAGE_FORMAT_FIT) {
- if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) {
+ if (!fit_check_format(fit_hdr)) {
bootstage_error(BOOTSTAGE_ID_IDE_FIT_READ);
puts("** Bad FIT image format\n");
return 1;
diff --git a/cmd/efuse.c b/cmd/efuse.c
index 148fa1f..753ad68 100644
--- a/cmd/efuse.c
+++ b/cmd/efuse.c
@@ -1,22 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * cmd/efuse.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <config.h>
#include <common.h>
@@ -135,8 +120,8 @@
lAddr1 = simple_strtoul(argv[2], &end, 16);
lAddr2 = get_sharemem_info(GET_SHARE_MEM_INPUT_BASE);
- memcpy((void *)lAddr2, (void *)lAddr1, GXB_EFUSE_PATTERN_SIZE);
- flush_cache(lAddr2, GXB_EFUSE_PATTERN_SIZE);
+ memcpy((void *)lAddr2, (void *)lAddr1, GXB_EFUSE_PATTERN_SIZE<<1);
+ flush_cache(lAddr2, GXB_EFUSE_PATTERN_SIZE<<1);
switch (action) {
case CMD_EFUSE_SECURE_BOOT_SET:
@@ -155,7 +140,7 @@
return -1;
}
- ret = aml_sec_boot_check(nType, lAddr2, GXB_EFUSE_PATTERN_SIZE, 0);
+ ret = aml_sec_boot_check(nType, lAddr2, GXB_EFUSE_PATTERN_SIZE<<1, 0);
if (ret)
printf("aml log : EFUSE pattern programming fail [%d]!\n",
ret);
diff --git a/cmd/fastboot.c b/cmd/fastboot.c
index e98cd9a..2e28875 100644
--- a/cmd/fastboot.c
+++ b/cmd/fastboot.c
@@ -6,6 +6,7 @@
* (C) Copyright 2014 Linaro, Ltd.
* Rob Herring <robh@kernel.org>
*/
+#include <board_variant.h>
#include <common.h>
#include <command.h>
#include <console.h>
@@ -17,6 +18,11 @@
static int do_fastboot_udp(int argc, char *const argv[],
uintptr_t buf_addr, size_t buf_size)
{
+ if (get_board_variant() != BOARD_VARIANT_DEV) {
+ printf("Fastboot is disabled\n");
+ return CMD_RET_FAILURE;
+ }
+
#if CONFIG_IS_ENABLED(UDP_FUNCTION_FASTBOOT)
int err = net_loop(FASTBOOT);
@@ -32,9 +38,18 @@
#endif
}
+#ifdef CONFIG_USB_GADGET_CRG
+extern int phy_num;
+#endif
+
static int do_fastboot_usb(int argc, char *const argv[],
uintptr_t buf_addr, size_t buf_size)
{
+ if (get_board_variant() != BOARD_VARIANT_DEV) {
+ printf("Fastboot is disabled\n");
+ return CMD_RET_FAILURE;
+ }
+
#if CONFIG_IS_ENABLED(USB_FUNCTION_FASTBOOT)
int controller_index;
char *usb_controller;
@@ -51,6 +66,9 @@
return CMD_RET_FAILURE;
}
+#ifdef CONFIG_USB_GADGET_CRG
+ phy_num = controller_index;
+#endif
/* ret = usb_gadget_initialize(controller_index); */
ret = 0;
if (ret) {
@@ -94,6 +112,11 @@
static int do_fastboot(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
{
+ if (get_board_variant() != BOARD_VARIANT_DEV) {
+ printf("Fastboot is disabled\n");
+ return CMD_RET_FAILURE;
+ }
+
uintptr_t buf_addr = (uintptr_t)NULL;
size_t buf_size = 0;
@@ -106,6 +129,8 @@
--argc;
while (*++arg) {
switch (*arg) {
+#if 0
+/*for secure consider ,no permission to download any address and size,use default only*/
case 'l':
if (--argc <= 0)
return CMD_RET_USAGE;
@@ -117,13 +142,15 @@
return CMD_RET_USAGE;
buf_size = simple_strtoul(*++argv, NULL, 16);
goto NXTARG;
-
+#endif
default:
return CMD_RET_USAGE;
}
}
+#if 0
NXTARG:
;
+#endif
}
/* Handle case when USB controller param is just '-' */
diff --git a/cmd/fpga.c b/cmd/fpga.c
index 9093026..88a8e3f 100644
--- a/cmd/fpga.c
+++ b/cmd/fpga.c
@@ -325,7 +325,7 @@
return CMD_RET_FAILURE;
}
- if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) {
+ if (!fit_check_format(fit_hdr)) {
puts("Bad FIT image format\n");
return CMD_RET_FAILURE;
}
diff --git a/cmd/gpio.c b/cmd/gpio.c
index 0110d6a..ecdc453 100644
--- a/cmd/gpio.c
+++ b/cmd/gpio.c
@@ -213,11 +213,11 @@
}
gpio_direction_output(gpio, value);
}
- pr_info("gpio: pin %s (gpio %i) value is ", str_gpio, gpio);
+ printf("gpio: pin %s (gpio %i) value is ", str_gpio, gpio);
if (IS_ERR_VALUE(value))
- pr_err("unknown (ret=%d)\n", value);
+ printf("unknown (ret=%d)\n", value);
else
- pr_info("%d\n", value);
+ printf("%d\n", value);
if (sub_cmd != GPIO_INPUT && !IS_ERR_VALUE(value)) {
int nval = gpio_get_value(gpio);
diff --git a/cmd/gpt.c b/cmd/gpt.c
index 02a65f0..6388703 100644
--- a/cmd/gpt.c
+++ b/cmd/gpt.c
@@ -556,9 +556,6 @@
u8 part_count = 0;
disk_partition_t *partitions = NULL;
- if (!str_part)
- return -1;
-
/* fill partitions */
ret = set_gpt_info(blk_dev_desc, str_part,
&str_disk_guid, &partitions, &part_count);
@@ -590,9 +587,6 @@
u8 part_count = 0;
int ret = 0;
- if (!str_part)
- return -1;
-
/* fill partitions */
ret = set_gpt_info(blk_dev_desc, str_part,
&str_disk_guid, &partitions, &part_count);
@@ -638,6 +632,21 @@
}
#ifdef CONFIG_CMD_GPT_RENAME
+/*
+ * There are 3 malloc() calls in set_gpt_info() and there is no info about which
+ * failed.
+ */
+static void set_gpt_cleanup(char **str_disk_guid,
+ disk_partition_t **partitions)
+{
+#ifdef CONFIG_RANDOM_UUID
+ if (str_disk_guid)
+ free(str_disk_guid);
+#endif
+ if (partitions)
+ free(partitions);
+}
+
static int do_rename_gpt_parts(struct blk_desc *dev_desc, char *subcomm,
char *name1, char *name2)
{
@@ -645,7 +654,7 @@
struct disk_part *curr;
disk_partition_t *new_partitions = NULL;
char disk_guid[UUID_STR_LEN + 1];
- char *partitions_list, *str_disk_guid = NULL;
+ char *partitions_list, *str_disk_guid;
u8 part_count = 0;
int partlistlen, ret, numparts = 0, partnum, i = 1, ctr1 = 0, ctr2 = 0;
@@ -687,8 +696,14 @@
/* set_gpt_info allocates new_partitions and str_disk_guid */
ret = set_gpt_info(dev_desc, partitions_list, &str_disk_guid,
&new_partitions, &part_count);
- if (ret < 0)
- goto out;
+ if (ret < 0) {
+ del_gpt_info();
+ free(partitions_list);
+ if (ret == -ENOMEM)
+ set_gpt_cleanup(&str_disk_guid, &new_partitions);
+ else
+ goto out;
+ }
if (!strcmp(subcomm, "swap")) {
if ((strlen(name1) > PART_NAME_LEN) || (strlen(name2) > PART_NAME_LEN)) {
@@ -750,8 +765,14 @@
* Even though valid pointers are here passed into set_gpt_info(),
* it mallocs again, and there's no way to tell which failed.
*/
- if (ret < 0)
- goto out;
+ if (ret < 0) {
+ del_gpt_info();
+ free(partitions_list);
+ if (ret == -ENOMEM)
+ set_gpt_cleanup(&str_disk_guid, &new_partitions);
+ else
+ goto out;
+ }
debug("Writing new partition table\n");
ret = gpt_restore(dev_desc, disk_guid, new_partitions, numparts);
@@ -773,14 +794,10 @@
}
printf("new partition table with %d partitions is:\n", numparts);
print_gpt_info();
- out:
del_gpt_info();
-#ifdef CONFIG_RANDOM_UUID
- if (str_disk_guid)
- free(str_disk_guid);
-#endif
- if (new_partitions)
- free(new_partitions);
+ out:
+ free(new_partitions);
+ free(str_disk_guid);
free(partitions_list);
return ret;
}
diff --git a/cmd/i2c.c b/cmd/i2c.c
index 09c4ba9..ed14175 100644
--- a/cmd/i2c.c
+++ b/cmd/i2c.c
@@ -1843,6 +1843,69 @@
}
#endif /* defined(CONFIG_SYS_I2C) */
+#if defined(CONFIG_DM_I2C)
+static int do_i2c_boot(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ uint8_t buf[5];
+ const uint8_t buf_sdc[] = {0x53, 0x44, 0x43};
+ const uint8_t buf_usb[] = {0x55, 0x53, 0x42};
+ struct udevice *dev;
+ int ret, i, bus_no;
+
+ /*
+ * The gpio i2c bum is 5 as default.
+ * It depends on the Meson i2c controller number.
+ * It is 5 for the current SoCs, May it be 4 in the future.
+ * If gpio bus number is not 5, run: i2c dev x first.
+ */
+ if (!i2c_get_cur_bus(&dev))
+ bus_no = dev->seq;
+ else {
+ bus_no = 5;
+ printf("Using the default BUS: 5. ");
+ }
+
+ ret = i2c_get_chip_for_busnum(bus_no, 0x52, 1, &dev);
+ if (ret) {
+ printf("Cannot find i2c chip 0: %d\n", ret);
+ return 0;
+ }
+
+ if (argc == 1) {
+ /* read fd/fe/ff */
+ ret = dm_i2c_read(dev, 0xfd, &buf[0], 1);
+ ret = dm_i2c_read(dev, 0xfe, &buf[1], 1);
+ ret = dm_i2c_read(dev, 0xff, &buf[2], 1);
+ if (ret) {
+ printf("HDMI NO POWER or gpio wrong config");
+ return ret;
+ }
+ buf[3] = '\0';
+ printf("Current BOOT is %s\n", buf);
+ } else {
+ if (!strcmp(argv[1], "usb"))
+ strcpy((char *)buf, (const char *)buf_usb);
+ else if (!strcmp(argv[1], "sdc"))
+ strcpy((char *)buf, (const char *)buf_sdc);
+ else {
+ printf("Not support boot\n");
+ return 0;
+ }
+
+ printf("Setting BOOT to %s\n", argv[1]);
+ for (i = 0; i < 3; i++) {
+ ret = dm_i2c_write(dev, 0xfd + i, &buf[i], 1);
+ if (ret)
+ return ret;
+ udelay(1000);/* Waiting for write in*/
+ }
+ }
+
+ return ret;
+}
+#endif
+
/**
* do_i2c_bus_speed() - Handle the "i2c speed" command-line command
* @cmdtp: Command data struct pointer
@@ -1965,6 +2028,7 @@
U_BOOT_CMD_MKENT(read, 5, 1, do_i2c_read, "", ""),
U_BOOT_CMD_MKENT(write, 6, 0, do_i2c_write, "", ""),
#ifdef CONFIG_DM_I2C
+ U_BOOT_CMD_MKENT(boot, 1, 1, do_i2c_boot, "", ""),
U_BOOT_CMD_MKENT(flags, 2, 1, do_i2c_flags, "", ""),
U_BOOT_CMD_MKENT(olen, 2, 1, do_i2c_olen, "", ""),
#endif
@@ -2043,6 +2107,7 @@
"i2c write memaddress chip address[.0, .1, .2] length [-s] - write memory\n"
" to I2C; the -s option selects bulk write in a single transaction\n"
#ifdef CONFIG_DM_I2C
+ "i2c boot [usb/sdc] - show or set current BOOT\n"
"i2c flags chip [flags] - set or get chip flags\n"
"i2c olen chip [offset_length] - set or get chip offset length\n"
#endif
diff --git a/cmd/ini.c b/cmd/ini.c
index 8c28fa6..8b56ed7 100644
--- a/cmd/ini.c
+++ b/cmd/ini.c
@@ -16,24 +16,8 @@
#include <environment.h>
#include <linux/ctype.h>
#include <linux/string.h>
-
-#ifdef CONFIG_INI_MAX_LINE
-#define MAX_LINE CONFIG_INI_MAX_LINE
-#else
-#define MAX_LINE 200
-#endif
-
-#ifdef CONFIG_INI_MAX_SECTION
-#define MAX_SECTION CONFIG_INI_MAX_SECTION
-#else
-#define MAX_SECTION 50
-#endif
-
-#ifdef CONFIG_INI_MAX_NAME
-#define MAX_NAME CONFIG_INI_MAX_NAME
-#else
-#define MAX_NAME 50
-#endif
+#include "amlogic/ini/model.h"
+#include "amlogic/ini/ini_size_define.h"
/* Strip whitespace chars off end of given string, in place. Return s. */
static char *rstrip(char *s)
@@ -89,7 +73,10 @@
end = *mem + *memsize;
newline = 0;
}
- len = min((end - *mem) + newline, num);
+ len = end - *mem + newline;
+ if (len > num)
+ len = num;
+ //len = min(((int)end - (int)(*mem)) + newline, num);
memcpy(str, *mem, len);
if (len < num)
str[len] = '\0';
@@ -249,3 +236,36 @@
"parse an ini file in memory and merge the specified section into the env",
"section [[file-address] file-size]"
);
+
+static int do_ini_model_list(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int ret;
+ if (argc > 1)
+ return CMD_RET_USAGE;
+
+ ret = handle_model_list();
+ return ret;
+}
+
+U_BOOT_CMD(
+ model_list, 4, 0, do_ini_model_list,
+ "list ini model name",
+ " "
+);
+
+static int do_ini_model(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int ret;
+ if (argc > 1)
+ return CMD_RET_USAGE;
+
+ ret = handle_model_sum();
+ return ret;
+}
+
+U_BOOT_CMD(
+ ini_model, 4, 0, do_ini_model,
+ "parse ini file by env model_name",
+ " "
+);
+
diff --git a/cmd/irkey.c b/cmd/irkey.c
new file mode 100644
index 0000000..033c14f
--- /dev/null
+++ b/cmd/irkey.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <dm.h>
+#include <asm/io.h>
+#include <common.h>
+#include <command.h>
+#include <errno.h>
+#include <misc.h>
+
+#define KEY_PARAMS_NUM 10
+#define OTHER_PARAMS_NUM 1
+
+extern uint32_t get_time(void);
+
+static int do_irkey(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ uint32_t key_buf[KEY_PARAMS_NUM];
+ uint32_t time_out = 0;
+ uint32_t time_base = 0;
+ struct udevice *ir_devp;
+ uint32_t key;
+ char *endp;
+ char str[16] = {0};
+ u8 i;
+
+ /*at least set a key*/
+ if (argc < 3)
+ return -EINVAL;
+
+ /*obtain timeout time*/
+ time_out = simple_strtoul(argv[1], &endp, 0);
+ printf("time_out = %d\n",time_out);
+ if (*argv[1] == 0 || *endp != 0)
+ return -EINVAL;
+
+ /*obtain IR keys value which need to detect*/
+ for (i=2; i<argc; i++) {
+ key_buf[i-2] = simple_strtoul(argv[i], &endp, 0);
+ printf("key[%d] = %x\n",i-2, key_buf[i-2]);
+ if (*argv[i] == 0 || *endp != 0)
+ return -EINVAL;
+ }
+
+ if (uclass_get_device_by_name(UCLASS_MISC, "meson-ir", &ir_devp)) {
+ printf("failed to get ir udevice\n");
+ return -EINVAL;
+ }
+
+ time_base = get_time();
+
+ while ((get_time() - time_base) < time_out)
+ {
+ if (misc_read(ir_devp, 0, &key, 1))
+ continue;
+
+ printf("keycode = %x\n",key);
+ for (i=2; i<argc; i++) {
+ if (key == key_buf[i-2]) {
+ snprintf(str, sizeof(str), "0x%x", key);
+ env_set("irkey_value", str);
+ return 0;
+ }
+ }
+ }
+
+ return -EINVAL;
+}
+/*Maxium key arguments: 10*/
+U_BOOT_CMD(
+ irkey, (KEY_PARAMS_NUM + OTHER_PARAMS_NUM + 1), 0, do_irkey,
+ "irkey <timeout> <key1> ...<keyN> - maximum value of N: 10",
+ NULL
+);
diff --git a/cmd/jtag.c b/cmd/jtag.c
new file mode 100644
index 0000000..1eaab6b
--- /dev/null
+++ b/cmd/jtag.c
@@ -0,0 +1,203 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <dm.h>
+#include <misc.h>
+#include <malloc.h>
+#include <asm/arch/bl31_apis.h>
+#include <amlogic/cpu_id.h>
+#include <amlogic/jtag.h>
+#include <linux/ctype.h>
+
+static struct udevice *jtag_devp;
+static int jtagon_id = INVALID_ID;
+
+struct jtag_id_desc {
+ unsigned short id;
+ const char *core_type;
+ const char *jtag_type;
+ const char *alias;
+};
+
+static struct jtag_id_desc jtag_id_data[] = {
+ {JTAG_SELECT_ID(AP, JTAG_A, 0), "ap", "jtag_a", "apao"},
+ {JTAG_SELECT_ID(AP, JTAG_B, 0), "ap", "jtag_b", "apee"},
+ {JTAG_SELECT_ID(AP, SWD_A, 0), "ap", "swd_a", "swd_apao"},
+
+ {JTAG_SELECT_ID(SCP, JTAG_A, 0), "scp", "jtag_a", "scpao"},
+ {JTAG_SELECT_ID(SCP, JTAG_B, 0), "scp", "jtag_b", "scpee"},
+ {JTAG_SELECT_ID(SCP, SWD_A, 0), "scp", "swd_a"},
+
+ {JTAG_SELECT_ID(SP, JTAG_A, 0), "sp", "jtag_a"},
+ {JTAG_SELECT_ID(SP, JTAG_B, 0), "sp", "jtag_b"},
+ {JTAG_SELECT_ID(SP, SWD_A, 0), "sp", "swd_a"},
+
+ {JTAG_SELECT_ID(DSPA, JTAG_A, 0), "dspa", "jtag_a"},
+ {JTAG_SELECT_ID(DSPA, JTAG_B, 0), "dspa", "jtag_b"},
+ {JTAG_SELECT_ID(DSPA, SWD_A, 0), "dspa", "swd_a"},
+
+ {JTAG_SELECT_ID(DSPB, JTAG_A, 0), "dspb", "jtag_a"},
+ {JTAG_SELECT_ID(DSPB, JTAG_B, 0), "dspb", "jtag_b"},
+ {JTAG_SELECT_ID(DSPB, SWD_A, 0), "dspb", "swd_a"},
+
+ {JTAG_SELECT_ID(DIF, JTAG_A, 0), "dif", "jtag_a"},
+ {JTAG_SELECT_ID(DIF, JTAG_B, 0), "dif", "jtag_b"},
+
+ {JTAG_SELECT_ID(AOCPU, JTAG_A, 0), "aocpu", "jtag_a"},
+ {JTAG_SELECT_ID(AOCPU, JTAG_B, 0), "aocpu", "jtag_b"},
+
+ {JTAG_SELECT_ID(AUCPU, JTAG_A, 0), "aucpu", "jtag_a"},
+ {JTAG_SELECT_ID(AUCPU, JTAG_B, 0), "aucpu", "jtag_b"},
+
+ {JTAG_SELECT_ID(SOCBRG, JTAG_A, 0), "socbrg", "jtag_a"},
+ {JTAG_SELECT_ID(SOCBRG, JTAG_B, 0), "socbrg", "jtag_b"},
+};
+
+static int jtag_id_find(const char *core_type, const char *jtag_type)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(jtag_id_data); i++) {
+ if ((!jtag_id_data[i].core_type) || (!jtag_id_data[i].jtag_type))
+ continue;
+ if ((strcmp(core_type, jtag_id_data[i].core_type) == 0) &&
+ (strcmp(jtag_type, jtag_id_data[i].jtag_type) == 0)) {
+ return jtag_id_data[i].id;
+ }
+ }
+
+ return INVALID_ID;
+}
+
+static int jtag_id_find_by_alias(const char *name)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(jtag_id_data); i++) {
+ if (!jtag_id_data[i].alias)
+ continue;
+ if (strcmp(name, jtag_id_data[i].alias) == 0)
+ return jtag_id_data[i].id;
+ }
+
+ return INVALID_ID;
+}
+
+static int jtag_id_get(int argc, char * const* argv)
+{
+ int jtag_id = INVALID_ID;
+ int cluster_type;
+
+ switch (argc) {
+ case 2:
+ jtag_id = jtag_id_find_by_alias(argv[1]);
+ break;
+ case 3:
+ if (isdigit(argv[2][0])) {
+ jtag_id = jtag_id_find_by_alias(argv[1]);
+ if (jtag_id < 0)
+ return jtag_id;
+
+ cluster_type = simple_strtoul(argv[2], NULL, 10);
+ if ((cluster_type & (~CLUSTER_TYPE_MASK)) != 0) {
+ printf("invalid cluster type.\n");
+ return INVALID_ID;
+ }
+ jtag_id = CLUSTER_TYPE_UPDATE(jtag_id, cluster_type);
+ } else {
+ jtag_id = jtag_id_find(argv[1], argv[2]);
+ }
+ break;
+ case 4:
+ jtag_id = jtag_id_find(argv[1], argv[2]);
+ if (jtag_id < 0)
+ return jtag_id;
+
+ cluster_type = simple_strtoul(argv[3], NULL, 10);
+ if ((cluster_type & (~CLUSTER_TYPE_MASK)) != 0) {
+ printf("invalid cluster type.\n");
+ return INVALID_ID;
+ }
+ jtag_id = CLUSTER_TYPE_UPDATE(jtag_id, cluster_type);
+ break;
+ default:
+ printf("invalid argument count!\n");
+ return INVALID_ID;
+ }
+
+ return jtag_id;
+}
+
+int do_jtagon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ int jtag_id;
+ int ret = 0;
+
+ jtag_id = jtag_id_get(argc, argv);
+ if (jtag_id < 0) {
+ printf("can't find jtag id.\n");
+ return -1;
+ }
+
+ ret = uclass_get_device_by_name(UCLASS_MISC, "jtag", &jtag_devp);
+ if (ret) {
+ printf("failed to find jtag node, check device tree.\n");
+ return ret;
+ }
+
+ if (misc_ioctl(jtag_devp, JTAG_SETPINMUX, &jtag_id) < 0) {
+ printf("failed to set jtag pinmux.\n");
+ return -1;
+ }
+
+ if (misc_ioctl(jtag_devp, JTAG_EANBLE, &jtag_id) < 0) {
+ printf("failed to enable jtag.\n");
+ return -1;
+ }
+
+ jtagon_id = jtag_id;
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ jtagon, 4, 1, do_jtagon,
+ "enable jtag",
+ "jtagon <core_type> <jtag_type> [cluster_type]\n"
+ "core_type: [ap | scp | sp | dspa | dspb | dif | aocpu | aucpu | socbrg]\n"
+ "jtag_type: [jtag_a | jtag_b | swd_a | swd_b]\n"
+ "cluster_type: [0 | 1]"
+);
+
+int do_jtagoff(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (jtagon_id == INVALID_ID) {
+ printf("jtag is not enable!\n");
+ return -1;
+ }
+
+ if (misc_ioctl(jtag_devp, JTAG_CLRPINMUX, &jtagon_id) < 0) {
+ printf("failed to clear jtag pinmux.\n");
+ return -1;
+ }
+
+ if (misc_ioctl(jtag_devp, JTAG_DISABLE, &jtagon_id) < 0) {
+ printf("failed to disable jtag\n");
+ return -1;
+ }
+
+ jtagon_id = INVALID_ID;
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ jtagoff, 1, 1, do_jtagoff,
+ "disable jtag",
+ "jtagoff"
+);
diff --git a/cmd/led.c b/cmd/led.c
index fc07ca9..652637f 100644
--- a/cmd/led.c
+++ b/cmd/led.c
@@ -19,6 +19,10 @@
#ifdef CONFIG_LED_BLINK
[LEDST_BLINK] = "blink",
#endif
+#ifdef CONFIG_AML_LED_PWM
+ [LEDST_SET_BRIGHTNESS] = "set_brightness",
+ [LEDST_GET_BRIGHTNESS] = "get_brightness",
+#endif
};
enum led_state_t get_led_cmd(char *var)
@@ -79,13 +83,16 @@
#ifdef CONFIG_LED_BLINK
int freq_ms = 0;
#endif
+#ifdef CONFIG_AML_LED_PWM
+ int brightness = 0;
+#endif
int ret;
/* Validate arguments */
if (argc < 2)
return CMD_RET_USAGE;
led_label = argv[1];
- if (*led_label == 'l')
+ if (!strncmp(led_label, "list", 4))
return list_leds();
cmd = argc > 2 ? get_led_cmd(argv[2]) : LEDST_COUNT;
@@ -96,6 +103,13 @@
freq_ms = simple_strtoul(argv[3], NULL, 10);
}
#endif
+#ifdef CONFIG_AML_LED_PWM
+ if (cmd == LEDST_SET_BRIGHTNESS) {
+ if (argc < 4)
+ return CMD_RET_USAGE;
+ brightness = simple_strtoul(argv[3], NULL, 10);
+ }
+#endif
ret = led_get_by_label(led_label, &dev);
if (ret) {
printf("LED '%s' not found (err=%d)\n", led_label, ret);
@@ -118,6 +132,14 @@
printf("LED '%s': ", led_label);
ret = show_led_state(dev);
break;
+#ifdef CONFIG_AML_LED_PWM
+ case LEDST_SET_BRIGHTNESS:
+ ret = led_set_brightness(dev, brightness);
+ break;
+ case LEDST_GET_BRIGHTNESS:
+ printf("LED '%s' brightness: %d\n",led_label,led_get_brightness(dev));
+ break;
+#endif
}
if (ret < 0) {
printf("LED '%s' operation failed (err=%d)\n", led_label, ret);
@@ -138,5 +160,9 @@
"manage LEDs",
"<led_label> on|off|toggle" BLINK "\tChange LED state\n"
"led [<led_label>\tGet LED state\n"
- "led list\t\tshow a list of LEDs"
+#ifdef CONFIG_AML_LED_PWM
+ "led [<led_label> set_brightness\tSet LED brightness\n"
+ "led [<led_label> get_brightness\tGet LED brightness\n"
+#endif
+ "led list\t\tshow a list of LEDs\n"
);
diff --git a/cmd/mmc.c b/cmd/mmc.c
index 2bad819..13925e4 100644
--- a/cmd/mmc.c
+++ b/cmd/mmc.c
@@ -92,7 +92,6 @@
}
}
}
-
static struct mmc *init_mmc_device(int dev, bool force_init)
{
struct mmc *mmc;
@@ -106,7 +105,6 @@
mmc->has_init = 0;
if (mmc_init(mmc))
return NULL;
-
return mmc;
}
static int do_mmcinfo(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/cmd/mtdparts.c b/cmd/mtdparts.c
index ac0e0d3..5fbf1f9 100644
--- a/cmd/mtdparts.c
+++ b/cmd/mtdparts.c
@@ -130,23 +130,20 @@
#if defined(CONFIG_SYS_MTDPARTS_RUNTIME)
extern void board_mtdparts_default(const char **mtdids, const char **mtdparts);
#endif
+#ifndef CONFIG_AML_MTDPART
static const char *mtdids_default = MTDIDS_DEFAULT;
static const char *mtdparts_default = MTDPARTS_DEFAULT;
+#endif
/* copies of last seen 'mtdids', 'mtdparts' and 'partition' env variables */
#define MTDIDS_MAXLEN 128
#define MTDPARTS_MAXLEN 512
#define PARTITION_MAXLEN 16
-static char last_ids[MTDIDS_MAXLEN + 1];
-static char last_parts[MTDPARTS_MAXLEN + 1];
static char last_partition[PARTITION_MAXLEN + 1];
/* low level jffs2 cache cleaning routine */
extern void jffs2_free_cache(struct part_info *part);
-/* mtdids mapping list, filled by parse_ids() */
-static struct list_head mtdids;
-
/* device/partition list, parse_cmdline() parses into here */
static struct list_head devices;
@@ -157,10 +154,9 @@
u8 use_defaults;
static struct part_info* mtd_part_info(struct mtd_device *dev, unsigned int part_num);
-
-/* command line only routines */
-static struct mtdids* id_find_by_mtd_id(const char *mtd_id, unsigned int mtd_id_len);
-static int device_del(struct mtd_device *dev);
+#ifndef CONFIG_AML_MTDPART
+/* mtdids mapping list, filled by parse_ids() */
+static struct list_head mtdids;
/**
* Parses a string into a number. The number stored at ptr is
@@ -225,7 +221,7 @@
else
sprintf(buf, "%llu", size);
}
-
+#endif
/**
* This routine does global indexing of all partitions. Resulting index for
* current partition is saved in 'mtddevnum'. Current partition name in
@@ -280,7 +276,6 @@
debug("--- current_save ---\n");
- memset(buf, 0, sizeof(buf)/sizeof(buf[0]));
if (current_mtd_dev) {
sprintf(buf, "%s%d,%d", MTD_DEV_TYPE(current_mtd_dev->id->type),
current_mtd_dev->id->num, current_mtd_partnum);
@@ -298,7 +293,7 @@
index_partitions();
}
-
+#ifndef CONFIG_AML_MTDPART
/**
* Produce a mtd_info given a type and num.
*
@@ -322,6 +317,7 @@
return 0;
}
+
/**
* Performs sanity check for supplied flash partition.
* Table of existing MTD flash devices is searched and partition device
@@ -418,6 +414,7 @@
* @param part partition to validate
* @return 0 if partition is valid, 1 otherwise
*/
+
static int part_validate(struct mtdids *id, struct part_info *part)
{
if (part->size == SIZE_REMAINING)
@@ -454,6 +451,7 @@
* @param part partition to delete
* @return 0 on success, 1 otherwise
*/
+static int device_del(struct mtd_device *dev);
static int part_del(struct mtd_device *dev, struct part_info *part)
{
u8 current_save_needed = 0;
@@ -594,7 +592,6 @@
return 0;
}
-
/**
* Parse one partition definition, allocate memory and return pointer to this
* location in retpart.
@@ -713,6 +710,7 @@
*retpart = part;
return 0;
}
+#endif
/**
* Check device number to be within valid range for given device type.
@@ -722,6 +720,7 @@
* @param size a pointer to the size of the mtd device (output)
* @return 0 if device is valid, 1 otherwise
*/
+#ifndef CONFIG_AML_MTDPART
static int mtd_device_validate(u8 type, u8 num, u64 *size)
{
struct mtd_info *mtd = NULL;
@@ -756,6 +755,7 @@
return 0;
}
+#endif
/**
* If provided device exists it's partitions are deleted, device is removed
@@ -764,6 +764,7 @@
* @param dev device to be deleted
* @return 0 on success, 1 otherwise
*/
+#ifndef CONFIG_AML_MTDPART
static int device_del(struct mtd_device *dev)
{
part_delall(&dev->parts);
@@ -787,7 +788,7 @@
index_partitions();
return 0;
}
-
+#endif
/**
* Search global device list and return pointer to the device of type and num
* specified.
@@ -811,6 +812,7 @@
return NULL;
}
+#ifndef CONFIG_AML_MTDPART
/**
* Add specified device to the global device list.
*
@@ -843,6 +845,7 @@
* @param retdev pointer to the allocated device (output)
* @return 0 on success, 1 otherwise
*/
+static struct mtdids* id_find_by_mtd_id(const char *mtd_id, unsigned int mtd_id_len);
static int device_parse(const char *const mtd_dev, const char **ret, struct mtd_device **retdev)
{
struct mtd_device *dev;
@@ -974,6 +977,7 @@
*
* @return 0 on success, 1 otherwise
*/
+static char last_parts[MTDPARTS_MAXLEN + 1];
static int mtd_devices_init(void)
{
last_parts[0] = '\0';
@@ -1002,7 +1006,6 @@
return NULL;
}
-
/**
* Search global mtdids list and find id of a requested mtd_id.
*
@@ -1034,6 +1037,7 @@
return NULL;
}
+#endif
/**
* Parse device id string <dev-id> := 'nand'|'nor'|'onenand'|'spi-nand'<dev-num>,
@@ -1078,7 +1082,7 @@
*ret_id = p;
return 0;
}
-
+#ifndef CONFIG_AML_MTDPART
/**
* Process all devices and generate corresponding mtdparts string describing
* all partitions on all devices.
@@ -1225,7 +1229,7 @@
return ret;
}
-
+#endif
#if defined(CONFIG_CMD_MTDPARTS_SHOW_NET_SIZES)
/**
* Get the net size (w/o bad blocks) of the given partition.
@@ -1249,7 +1253,7 @@
return net_size;
}
#endif
-
+#ifndef CONFIG_AML_MTDPART
static void print_partition_table(void)
{
struct list_head *dentry, *pentry;
@@ -1302,7 +1306,8 @@
if (list_empty(&devices))
printf("no partitions defined\n");
}
-
+#endif
+#ifndef CONFIG_AML_MTDPART
/**
* Format and print out a partition list for each device from global device
* list.
@@ -1339,6 +1344,7 @@
puts(mtdparts_default ? mtdparts_default : "none");
puts("\n");
}
+#endif
/**
* Given partition identifier in form of <dev_type><dev_num>,<part_num> find
@@ -1435,7 +1441,7 @@
return 1;
}
#endif
-
+#ifndef CONFIG_AML_MTDPART
/**
* Find and delete partition. For partition id format see find_dev_and_part().
*
@@ -1467,7 +1473,7 @@
printf("partition %s not found\n", id);
return 1;
}
-
+#endif
#if defined(CONFIG_CMD_MTDPARTS_SPREAD)
/**
* Increase the size of the given partition so that it's net size is at least
@@ -1571,6 +1577,7 @@
* @param buf temporary buffer pointer MTDPARTS_MAXLEN long
* @return mtdparts variable string, NULL if not found
*/
+#ifndef CONFIG_AML_MTDPART
static const char *env_get_mtdparts(char *buf)
{
if (gd->flags & GD_FLG_ENV_READY)
@@ -1636,6 +1643,7 @@
return err;
}
+#endif
/**
* Parse provided string describing mtdids mapping (see file header for mtdids
@@ -1645,6 +1653,8 @@
* @param ids mapping string
* @return 0 on success, 1 otherwise
*/
+#ifndef CONFIG_AML_MTDPART
+static char last_ids[MTDIDS_MAXLEN + 1];
static int parse_mtdids(const char *const ids)
{
const char *p = ids;
@@ -1747,7 +1757,7 @@
return 0;
}
-
+#endif
/**
* Parse and initialize global mtdids mapping and create global
@@ -1755,6 +1765,7 @@
*
* @return 0 on success, 1 otherwise
*/
+#ifndef CONFIG_AML_MTDPART
int mtdparts_init(void)
{
static int initialized = 0;
@@ -1896,7 +1907,7 @@
return 0;
}
-
+#endif
/**
* Return pointer to the partition of a requested number from a requested
* device.
@@ -1993,6 +2004,11 @@
static int do_mtdparts(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
+#ifdef CONFIG_AML_MTDPART
+ if (argc > 1)
+ printf("we are not support cmd mtdparts operates\n");
+ return 0;
+#else
if (argc == 2) {
if (strcmp(argv[1], "default") == 0) {
env_set("mtdids", NULL);
@@ -2104,7 +2120,7 @@
if ((argc == 2) && (strcmp(argv[1], "spread") == 0))
return spread_partitions();
#endif /* CONFIG_CMD_MTDPARTS_SPREAD */
-
+#endif
return CMD_RET_USAGE;
}
diff --git a/cmd/mvebu/Kconfig b/cmd/mvebu/Kconfig
index b809708..ad10a57 100644
--- a/cmd/mvebu/Kconfig
+++ b/cmd/mvebu/Kconfig
@@ -50,4 +50,3 @@
MVEBU "bubt" command if the source file name is omitted
endmenu
-
diff --git a/cmd/nand.c b/cmd/nand.c
index 069da99..22a534d 100644
--- a/cmd/nand.c
+++ b/cmd/nand.c
@@ -928,7 +928,7 @@
#if defined(CONFIG_FIT)
/* This cannot be done earlier, we need complete FIT image in RAM first */
if (genimg_get_format ((void *)addr) == IMAGE_FORMAT_FIT) {
- if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) {
+ if (!fit_check_format (fit_hdr)) {
bootstage_error(BOOTSTAGE_ID_NAND_FIT_READ);
puts ("** Bad FIT image format\n");
return 1;
diff --git a/cmd/net.c b/cmd/net.c
index 89721b8..f9bb817 100644
--- a/cmd/net.c
+++ b/cmd/net.c
@@ -98,6 +98,27 @@
"boot image via network using DHCP/TFTP protocol",
"[loadAddress] [[hostIPaddr:]bootfilename]"
);
+
+static int do_ethloop(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ if (argc != 1)
+ return -1;
+
+ if (net_loop(ETHLOOP) < 0) {
+ printf("loopback test failed\n");
+ return 1;
+ }
+
+ printf("loopback test successfully completed\n");
+ return 0;
+}
+
+U_BOOT_CMD(
+ ethloop, 1, 1, do_ethloop,
+ "ethloop\t- loopback test using ethernet test package\n",
+ ""
+);
#endif
#if defined(CONFIG_CMD_NFS)
@@ -456,4 +477,5 @@
""
);
+
#endif /* CONFIG_CMD_LINK_LOCAL */
diff --git a/cmd/nvedit.c b/cmd/nvedit.c
index de16c72..fed3646 100644
--- a/cmd/nvedit.c
+++ b/cmd/nvedit.c
@@ -51,6 +51,7 @@
!defined(CONFIG_ENV_IS_IN_SPI_FLASH) && \
!defined(CONFIG_ENV_IS_IN_REMOTE) && \
!defined(CONFIG_ENV_IS_IN_UBI) && \
+ !defined(CONFIG_ENV_IS_IN_STORAGE) && \
!defined(CONFIG_ENV_IS_NOWHERE)
# error Define one of CONFIG_ENV_IS_IN_{EEPROM|FLASH|MMC|FAT|EXT4|\
NAND|NVRAM|ONENAND|SATA|SPI_FLASH|REMOTE|UBI} or CONFIG_ENV_IS_NOWHERE
diff --git a/cmd/saradc.c b/cmd/saradc.c
index 63190d9..04fc0c7 100644
--- a/cmd/saradc.c
+++ b/cmd/saradc.c
@@ -1,21 +1,28 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Command for SARADC.
- *
- * Copyright (C) 2012 Amlogic.
- * Elvis Yu <elvis.yu@amlogic.com>
- *
- * Copyright (C) 2018 Amlogic.
- * Xingyu Chen <xingyu.chen@amlogic.com>
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
-
#include <common.h>
#include <command.h>
#include <dm/uclass.h>
-#include <asm/arch/saradc.h>
+#include <amlogic/saradc.h>
#define ENV_SARADC_VALUE "saradc_val"
+struct meson_saradc_mode {
+ unsigned int sample_mode;
+ const char *mode_name;
+};
+
+static const struct meson_saradc_mode mode_table[] = {
+ {ADC_MODE_AVERAGE, "average"}, //default mode
+ {ADC_MODE_AVERAGE, "average"},
+ {ADC_MODE_HIGH_PRECISION, "high precision"},
+ {ADC_MODE_HIGH_RESOLUTION, "high resolution"},
+ {ADC_MODE_DECIM_FILTER, "decim filter"}
+};
+
static const char * const ch7_voltage[] = {
"gnd",
"vdd/4",
@@ -25,13 +32,24 @@
};
static int current_channel = -1;
+static unsigned int current_mode;
static int do_saradc_open(cmd_tbl_t *cmdtp, int flag, int argc,
char * const argv[])
{
+ struct udevice *dev;
int channel;
+ int mode;
+ int ret;
+ char *endp;
+
+ ret = uclass_get_device_by_name(UCLASS_ADC, "adc", &dev);
+ if (ret)
+ return ret;
channel = simple_strtoul(argv[1], NULL, 10);
+ mode = simple_strtoul(argv[2], &endp, 10);
+
if ((channel < 0) || (channel >= MESON_SARADC_CH_MAX))
{
pr_err("No such channel(%d) in SARADC! open failed!\n",
@@ -39,8 +57,24 @@
return -1;
}
+ if ((mode < 0) || (mode >= sizeof(mode_table)/sizeof(mode_table[0])) ||
+ (endp && !mode)) {
+ pr_err("No such mode(%d) in SARADC! open failed!\n", mode);
+ return -1;
+ }
+
+ ret = adc_set_mode(dev, channel, mode_table[mode].sample_mode);
+ if (ret) {
+ pr_err("current platform does not support [%s] mode\n",
+ mode_table[mode].mode_name);
+ return ret;
+ }
+
+ current_mode = mode_table[mode].sample_mode;
current_channel = channel;
+ printf("SARADC mode is %s\n", mode_table[mode].mode_name);
+
return 0;
}
@@ -66,7 +100,8 @@
return -EINVAL;
};
- ret = adc_channel_single_shot("adc", current_channel, &val);
+ ret = adc_channel_single_shot_mode("adc", current_mode,
+ current_channel, &val);
if (ret)
return ret;
@@ -126,7 +161,8 @@
unsigned int val;
int ret;
- ret = adc_channel_single_shot("adc", current_channel, &val);
+ ret = adc_channel_single_shot_mode("adc", current_mode,
+ current_channel, &val);
if (ret)
return ret;
@@ -151,7 +187,7 @@
}
static cmd_tbl_t cmd_saradc_sub[] = {
- U_BOOT_CMD_MKENT(open, 2, 0, do_saradc_open, "", ""),
+ U_BOOT_CMD_MKENT(open, 3, 0, do_saradc_open, "", ""),
U_BOOT_CMD_MKENT(close, 1, 0, do_saradc_close, "", ""),
U_BOOT_CMD_MKENT(getval, 1, 0, do_saradc_getval, "", ""),
U_BOOT_CMD_MKENT(test, 1, 0, do_saradc_test, "", ""),
@@ -178,10 +214,10 @@
U_BOOT_CMD(
saradc, CONFIG_SYS_MAXARGS, 0, do_saradc,
"saradc sub-system",
- "saradc open <channel> - open a SARADC channel\n"
+ "saradc open <channel> <mode> - open a SARADC channel\n\
+ mode: 1:average 2:high precision 3:high resolution 4:decim filter\n"
"saradc close - close the SARADC\n"
"saradc getval - get the value in current channel\n"
"saradc test - test the SARADC by channel-7\n"
- "saradc get_in_range <min> <max> - \
- return 0 if current value in the range of current channel\n"
+ "saradc get_in_range <min> <max> - return 0 if current value in the range of current channel\n"
);
diff --git a/cmd/sf.c b/cmd/sf.c
index 84bb057..aea0022 100644
--- a/cmd/sf.c
+++ b/cmd/sf.c
@@ -316,6 +316,41 @@
return ret == 0 ? 0 : 1;
}
+#ifdef CONFIG_AML_SPIFCV2
+extern int spifc_xip_prepare(void);
+static int do_spi_xip(int argc, char * const argv[])
+{
+ unsigned long addr;
+ char *endp;
+ int ret = 0;
+ int (*xip_entrance)(int, char **);
+
+ if (argc == 2) {
+ addr = simple_strtoul(argv[1], &endp, 16);
+ if (*argv[1] == 0 || *endp != 0)
+ return -1;
+ printf("addr 0x%lu\n", addr);
+ }
+
+ ret = spifc_xip_prepare();
+ if (ret)
+ goto _out;
+
+ if (argc == 2) {
+ xip_entrance = (int (*)(int, char **))(addr);
+ xip_entrance(3, NULL);
+ }
+
+_out:
+ return ret;
+}
+#else
+static int do_spi_xip(int argc, char * const argv[])
+{
+ return -1;
+}
+#endif /* only v2 supprt this. */
+
static int do_spi_flash_erase(int argc, char * const argv[])
{
int ret;
@@ -558,6 +593,9 @@
if (strcmp(cmd, "probe") == 0) {
ret = do_spi_flash_probe(argc, argv);
goto done;
+ } else if (strcmp(cmd, "xip") == 0) {
+ ret = do_spi_xip(argc, argv);
+ goto done;
}
/* The remaining commands require a selected device */
@@ -596,7 +634,7 @@
#endif
U_BOOT_CMD(
- sf, 5, 1, do_spi_flash,
+ sf, 5, 1, do_spi_flash,
"SPI flash sub-system",
"probe [[bus:]cs] [hz] [mode] - init flash device on given SPI bus\n"
" and chip select\n"
@@ -614,5 +652,5 @@
" or to start of mtd `partition'\n"
"sf protect lock/unlock sector len - protect/unprotect 'len' bytes starting\n"
" at address 'sector'\n"
- SF_TEST_HELP
-);
+ "sf xip [addr] - switch to xip and run to addr if addr exsit\n"
+ SF_TEST_HELP);
diff --git a/cmd/source.c b/cmd/source.c
index 897b970..6d98a1c 100644
--- a/cmd/source.c
+++ b/cmd/source.c
@@ -106,7 +106,7 @@
#if defined(CONFIG_FIT)
case IMAGE_FORMAT_FIT:
fit_hdr = buf;
- if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) {
+ if (!fit_check_format (fit_hdr)) {
puts ("Bad FIT image format\n");
return 1;
}
diff --git a/cmd/spi_nand.c b/cmd/spi_nand.c
new file mode 100644
index 0000000..14a432e
--- /dev/null
+++ b/cmd/spi_nand.c
@@ -0,0 +1,86 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <amlogic/storage.h>
+#include <amlogic/aml_mtd.h>
+#include <asm/arch/cpu_config.h>
+
+extern int spi_nand_probe(u32 init_flag);
+static int do_spinand(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ u32 init_flag = 0;
+ int ret = 0;
+ ulong addr;
+ size_t size;
+
+ if (argc != 3 && argc != 4)
+ return CMD_RET_USAGE;
+
+ if (!strcmp(argv[1], "init")) {
+ init_flag = (ulong)simple_strtoul(argv[2], NULL, 16);
+ return spi_nand_probe(init_flag);
+ } else if (!strcmp(argv[1], "update")) {
+ addr = (ulong)simple_strtoul(argv[2], NULL, 16);
+ size = (size_t)simple_strtoul(argv[3], NULL, 16);
+ if (store_device_valid(BOOT_SNAND)) {
+ ret = store_set_device(BOOT_SNAND);
+ if (!ret) {
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER) {
+ ret = store_boot_erase(BOOT_BL2, BOOT_OPS_ALL);
+ if (ret) {
+ pr_info("%s %d erase failed in %s",
+ __func__, __LINE__, BOOT_BL2);
+ return ret;
+ }
+ ret = store_boot_erase(BOOT_TPL, BOOT_OPS_ALL);
+ if (ret) {
+ pr_info("%s %d erase failed in %s",
+ __func__, __LINE__, BOOT_TPL);
+ return ret;
+ }
+ ret = store_boot_write(BOOT_BL2, BOOT_OPS_ALL,
+ size, (void *)addr);
+ if (ret) {
+ pr_info("%s %d write failed in %s",
+ __func__, __LINE__, BOOT_BL2);
+ return ret;
+ }
+ return store_boot_write(BOOT_TPL, BOOT_OPS_ALL,
+ size - BL2_SIZE,
+ (void *)(addr + BL2_SIZE));
+ } else {
+ ret = store_boot_erase(BOOT_LOADER,
+ BOOT_OPS_ALL);
+ if (ret) {
+ pr_info("%s %d erase failed in %s",
+ __func__,
+ __LINE__,
+ BOOT_LOADER);
+ return ret;
+ }
+ return store_boot_write(BOOT_LOADER,
+ BOOT_OPS_ALL,
+ size, (void *)addr);
+ }
+ }
+ } else {
+ pr_info("%s %d no valid spi nand\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ } else {
+ return CMD_RET_USAGE;
+ }
+ return ret;
+}
+
+U_BOOT_CMD(spinand, CONFIG_SYS_MAXARGS, 1, do_spinand,
+ "spinand sub-system",
+ "init [flag]\n"
+ " init spi nand with flag\n"
+ "spinand update addr size\n"
+ " update bootloader in spi nand\n"
+);
diff --git a/cmd/storage.c b/cmd/storage.c
new file mode 100644
index 0000000..917ac42
--- /dev/null
+++ b/cmd/storage.c
@@ -0,0 +1,1686 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <amlogic/storage.h>
+#include <div64.h>
+#include <linux/math64.h>
+#include <amlogic/cpu_id.h>
+#include <amlogic/store_wrapper.h>
+#include <asm/arch/register.h>
+#include <asm/arch/bl31_apis.h>
+#include <amlogic/aml_efuse.h>
+#include <asm/arch/cpu_config.h>
+#include <asm/arch/romboot.h>
+#include <asm/arch/secure_apb.h>
+#include <amlogic/blxx2bl33_param.h>
+#include <amlogic/aml_mtd.h>
+#include <mmc.h>
+
+#undef pr_info
+#define pr_info printf
+
+#ifdef CONFIG_SPI_FLASH
+extern int spi_nor_pre(void);
+extern int spi_nor_probe(u32 init_flag);
+#endif
+
+#ifdef CONFIG_SPI_NAND
+extern int spi_nand_pre(void);
+extern int spi_nand_probe(u32 init_flag);
+#endif
+
+#ifdef CONFIG_MTD_SPI_NAND
+extern int spi_nand_pre(void);
+extern int spi_nand_probe(u32 init_flag);
+#endif
+
+#ifdef CONFIG_AML_NAND
+extern int amlnf_pre(void);
+extern int amlnf_probe(u32 init_flag);
+#endif
+
+#ifdef CONFIG_MESON_NFC
+extern int nand_pre(void);
+extern int nand_probe(uint32_t init_flag);
+#endif
+
+#ifdef CONFIG_MMC_MESON_GX
+extern int emmc_pre(void);
+extern int emmc_probe(u32 init_flag);
+#endif
+
+#ifdef CONFIG_MMC_MESON_GX
+extern int sdcard_pre(void);
+extern int sdcard_probe(u32 init_flag);
+#endif
+/* for info protect, fixme later */
+int info_disprotect = 0;
+
+static struct storage_t *current;
+static struct device_node_t device_list[] = {
+#ifdef CONFIG_MESON_NFC
+ {BOOT_NAND_MTD, "mtd", nand_pre, nand_probe},
+#endif
+#ifdef CONFIG_AML_NAND
+ {BOOT_NAND_NFTL, "nftl", amlnf_pre, amlnf_probe},
+#endif
+#ifdef CONFIG_SPI_NAND
+ /* old drivers will be removed later */
+ {BOOT_SNAND, "spi-nand", spi_nand_pre, spi_nand_probe},
+#endif
+#ifdef CONFIG_MTD_SPI_NAND
+ {BOOT_SNAND, "spi-nand", spi_nand_pre, spi_nand_probe},
+#endif
+#if CONFIG_SPI_FLASH
+ {BOOT_SNOR, "spi-nor", spi_nor_pre, spi_nor_probe},
+#endif
+#if 0
+ {BOOT_SD, "sd", sdcard_pre, sdcard_probe},
+#endif
+
+#ifdef CONFIG_MMC_MESON_GX
+ {BOOT_EMMC, "emmc", emmc_pre, emmc_probe},
+#endif
+
+};
+
+int store_register(struct storage_t *store_dev)
+{
+ if (!store_dev)
+ return 1;
+ if (!current) {
+ INIT_LIST_HEAD(&store_dev->list);
+ current = store_dev;
+ return 0;
+ }
+ /**
+ * the head node will not be a valid node
+ * usually when we use the list, but in storage
+ * interface module, we init the device node as
+ * a head instead a global list_head pointer,
+ * it should be traversaled.
+ */
+ if (store_dev == current)
+ return 0;
+ struct storage_t *dev;
+
+ if (store_dev->type == current->type)
+ return 1;
+ list_for_each_entry(dev, ¤t->list, list) {
+ if (dev == store_dev)
+ return 0;
+ else if (dev->type == store_dev->type)
+ return 1;
+ }
+ list_add_tail(&store_dev->list, ¤t->list);
+ current = store_dev;
+ return 0;
+}
+
+void store_unregister(struct storage_t *store_dev)
+{
+ if (store_dev == current) {
+ if (list_empty_careful(&store_dev->list)) {
+ current = NULL;
+ } else {
+ current = list_entry((current->list).next,
+ struct storage_t, list);
+ list_del_init(&store_dev->list);
+ }
+ } else {
+ list_del_init(&store_dev->list);
+ }
+}
+
+int sheader_need(void)
+{
+ const cpu_id_t cpuid = get_cpu_id();
+ const int familyId = cpuid.family_id;
+
+ return ((MESON_CPU_MAJOR_ID_SC2 == familyId) || (MESON_CPU_MAJOR_ID_T7 == familyId)
+ || (MESON_CPU_MAJOR_ID_S4 == familyId));
+}
+
+unsigned char *ubootdata = NULL;
+void sheader_load(void *addr)
+{
+ ubootdata = addr;
+}
+
+/*
+ * storage header which size is 512B
+ * is bind into the tail of bl2.bin.
+ * @addr: uboot address.
+ */
+static p_payload_info_t parse_uboot_sheader(void *addr)
+{
+ p_payload_info_t pInfo = (p_payload_info_t)(addr + BL2_SIZE);
+
+ if (AML_MAGIC_HDR_L == pInfo->hdr.nMagicL &&
+ AML_MAGIC_HDR_R == pInfo->hdr.nMagicR) {
+ printf("aml log : bootloader blxx mode!\n");
+ return pInfo;
+ }
+ return NULL;
+}
+
+boot_area_entry_t general_boot_part_entry[MAX_BOOT_AREA_ENTRIES] = {
+ {BOOT_BL2, BOOT_AREA_BB1ST, 0, 0},
+ {BOOT_BL2E, BOOT_AREA_BL2E, 0, 0},
+ {BOOT_BL2X, BOOT_AREA_BL2X, 0, 0},
+ {BOOT_DDRFIP, BOOT_AREA_DDRFIP, 0, 0},
+ {BOOT_DEVFIP, BOOT_AREA_DEVFIP, 0, 0},
+};
+
+struct boot_layout general_boot_layout = {.boot_entry = general_boot_part_entry};
+struct storage_startup_parameter g_ssp;
+struct storage_bl *g_storage = NULL;
+
+static void storage_boot_layout_debug_info(
+ struct boot_layout *boot_layout)
+{
+ boot_area_entry_t *boot_entry = boot_layout->boot_entry;
+ int i;
+
+ printf("boot area list: \n");
+ for (i = 0; i < MAX_BOOT_AREA_ENTRIES && boot_entry[i].size; i++) {
+ printf("%10s ", boot_entry[i].name);
+ printf("%10llx ", boot_entry[i].offset);
+ printf("%10llx\n", boot_entry[i].size);
+ }
+}
+
+/* use STORAGE_ROUND_UP, y must be power of 2 */
+#define STORAGE_ROUND_UP_IF_UNALIGN(x, y) ((x) = (((x) + (y) - 1) & (~(y - 1))))
+#define NAND_RSV_OFFSET 1024
+#define ALIGN_SIZE (4096)
+static int storage_boot_layout_rebuild(struct boot_layout *boot_layout,
+ unsigned int bl2e_size,
+ unsigned int bl2x_size)
+{
+ struct storage_startup_parameter *ssp = &g_ssp;
+ boot_area_entry_t *boot_entry = boot_layout->boot_entry;
+ uint64_t align_size, reserved_size = 0;
+ uint8_t i, cal_copy = ssp->boot_bakups;
+
+ align_size = ALIGN_SIZE;
+ if ((ssp->boot_device == BOOT_NAND_NFTL) ||
+ (ssp->boot_device == BOOT_NAND_MTD)) {
+ reserved_size = ssp->sip.nsp.layout_reserve_size;
+ align_size = ((NAND_RSV_OFFSET / cal_copy) * ssp->sip.nsp.page_size);
+ printf("reserved_size:0x%llx 0x%llx\n", reserved_size, align_size);
+ } else if (ssp->boot_device == BOOT_SNAND) {
+ reserved_size = ssp->sip.snasp.layout_reserve_size;
+ align_size = ((NAND_RSV_OFFSET / cal_copy) * ssp->sip.snasp.pagesize);
+ } else if (ssp->boot_device == BOOT_EMMC) {
+ ssp->boot_entry[0].offset = boot_entry[0].offset +=
+ BL2_CORE_BASE_OFFSET_EMMC;
+ cal_copy = 1;
+ }
+ STORAGE_ROUND_UP_IF_UNALIGN(boot_entry[0].size, align_size);
+ ssp->boot_entry[0].size = boot_entry[0].size;
+ printf("ssp->boot_entry[0] offset:0x%x, size:0x%x\n",
+ ssp->boot_entry[0].offset, ssp->boot_entry[0].size);
+ printf("cal_copy:0x%x\n", cal_copy);
+ printf("align_size:0x%llx\n", align_size);
+ printf("reserved_size:0x%llx\n", reserved_size);
+ if ((ssp->boot_device == BOOT_NAND_NFTL) ||
+ (ssp->boot_device == BOOT_NAND_MTD))
+ align_size = ssp->sip.nsp.block_size;
+ else if (ssp->boot_device == BOOT_SNAND)
+ align_size = ssp->sip.snasp.pagesize *
+ ssp->sip.snasp.pages_per_eraseblock;
+ printf("align_size2:%llu\n", align_size);
+
+ boot_entry[BOOT_AREA_BL2E].size = bl2e_size;
+ boot_entry[BOOT_AREA_BL2X].size = bl2x_size;
+
+ for (i = 1; i < MAX_BOOT_AREA_ENTRIES && boot_entry[i - 1].size; i++) {
+ STORAGE_ROUND_UP_IF_UNALIGN(boot_entry[i].size, align_size);
+ boot_entry[i].offset = boot_entry[i-1].offset +
+ boot_entry[i-1].size * cal_copy + reserved_size;
+ reserved_size = 0;
+ ssp->boot_entry[i].size = boot_entry[i].size;
+ ssp->boot_entry[i].offset = boot_entry[i].offset;
+ }
+
+ return 0;
+}
+
+/* use STORAGE_ROUND_UP, y must be power of 2 */
+#define STORAGE_ROUND_UP_IF_UNALIGN(x, y) ((x) = (((x) + (y) - 1) & (~(y - 1))))
+#define NAND_RSV_OFFSET 1024
+#define ALIGN_SIZE (4096)
+static int storage_boot_layout_general_setting(struct boot_layout *boot_layout,
+ int need_build)
+{
+ struct storage_startup_parameter *ssp = &g_ssp;
+ boot_area_entry_t *boot_entry = boot_layout->boot_entry;
+ struct storage_boot_entry *sbentry = ssp->boot_entry;
+ p_payload_info_t pInfo = parse_uboot_sheader(ubootdata);;
+ p_payload_info_hdr_t hdr = &pInfo->hdr;
+ p_payload_info_item_t pItem = pInfo->arrItems;
+ int offPayload = 0, szPayload = 0;
+ unsigned int bl2e_size = 0, bl2x_size = 0;
+ char name[8] = {0};
+ int nIndex = 0;
+
+ if (need_build == BOOT_ID_USB) {
+ for (nIndex = 1, pItem += 1;
+ nIndex < hdr->byItemNum; ++nIndex, ++pItem) {
+ memcpy(name, &pItem->nMagic, sizeof(unsigned int));
+ offPayload = pItem->nOffset;
+ if (nIndex == BOOT_AREA_BL2E)
+ bl2e_size = pItem->nPayLoadSize;
+ if (nIndex == BOOT_AREA_BL2X)
+ bl2x_size = pItem->nPayLoadSize;
+ szPayload = pItem->nPayLoadSize;
+ pr_info("Item[%d]%4s offset 0x%08x sz 0x%x\n",
+ nIndex, name, offPayload, szPayload);
+ }
+ boot_entry[BOOT_AREA_BB1ST].size = ssp->boot_entry[BOOT_AREA_BB1ST].size;
+ boot_entry[BOOT_AREA_DDRFIP].size = ssp->boot_entry[BOOT_AREA_DDRFIP].size;
+ boot_entry[BOOT_AREA_DEVFIP].size = ssp->boot_entry[BOOT_AREA_DEVFIP].size;
+ storage_boot_layout_rebuild(boot_layout, bl2e_size, bl2x_size);
+ } else {
+ /* may be sdcard boot and also have to rebuild layout */
+ if (need_build == BOOT_ID_SDCARD) {
+ bl2e_size = sbentry[BOOT_AREA_BL2E].size;
+ bl2x_size = sbentry[BOOT_AREA_BL2X].size;
+ printf("bl2e_size=%x bl2x_size=%x current->type=%d\n",
+ bl2e_size, bl2x_size, current->type);
+ boot_entry[BOOT_AREA_BB1ST].size =
+ ssp->boot_entry[BOOT_AREA_BB1ST].size;
+ boot_entry[BOOT_AREA_DDRFIP].size =
+ ssp->boot_entry[BOOT_AREA_DDRFIP].size;
+ boot_entry[BOOT_AREA_DEVFIP].size =
+ ssp->boot_entry[BOOT_AREA_DEVFIP].size;
+ storage_boot_layout_rebuild(boot_layout,
+ bl2e_size, bl2x_size);
+ return 0;
+ }
+ /* normal boot */
+ for (nIndex = 0;
+ nIndex < MAX_BOOT_AREA_ENTRIES && sbentry->size;
+ nIndex++, sbentry++) {
+ boot_entry[nIndex].size = sbentry->size;
+ boot_entry[nIndex].offset = sbentry->offset;
+ }
+ }
+
+ return 0;
+}
+
+uint8_t emmc_boot_seqs_tbl[8][2] = {
+ {0, 3}, {0, 2}, {0, 3}, {0, 1},
+ {1, 2}, {1, 1}, {2, 1}, {0, 0}
+ };
+
+static int _get_emmc_boot_seqs(void)
+{
+ uint8_t ebcfg = 0;
+ if (IS_FEAT_DIS_EMMC_USER())
+ ebcfg |= (1<<2);
+ if (IS_FEAT_DIS_EMMC_BOOT_0())
+ ebcfg |= (1<<1);
+ if (IS_FEAT_DIS_EMMC_BOOT_1())
+ ebcfg |= (1<<0);
+
+ return ebcfg;
+}
+
+static int storage_get_emmc_boot_seqs(void)
+{
+ return emmc_boot_seqs_tbl[_get_emmc_boot_seqs()][1];;
+}
+
+static int storage_get_emmc_boot_start(void)
+{
+ return emmc_boot_seqs_tbl[_get_emmc_boot_seqs()][0];;
+}
+
+#define NAND_RSV_BLOCK_NUM 48
+#define NSP_PAGE0_DISABLE 1
+extern unsigned char *ubootdata;
+static int storage_get_and_parse_ssp(int *need_build) // boot_device:
+{
+ struct storage_startup_parameter *ssp = &g_ssp;
+ union storage_independent_parameter *sip;
+ static struct param_e *storage_param_e;
+ int usb_boot = *need_build;
+
+ memset(ssp, 0, sizeof(struct storage_startup_parameter));
+ if (!usb_boot) {
+ storage_param_e = param_of(STORAGE_PARAM_TPYE);
+ if (!storage_param_e)
+ return -1;
+ memcpy(ssp, storage_param_e->data,
+ sizeof(struct storage_startup_parameter));
+ /* may be sdcard boot and also have to rebuild layout */
+ if (ssp->boot_device == BOOT_ID_SDCARD ||
+ ssp->boot_device == BOOT_ID_USB) {
+ /* need change the storage base here */
+ *need_build = ssp->boot_device;
+ }
+ }
+
+ if (*need_build) {
+ sip = &ssp->sip;
+ ssp->boot_device = current->type;
+ switch (ssp->boot_device) {
+ case BOOT_EMMC:
+ ssp->boot_bakups = storage_get_emmc_boot_seqs();
+ break;
+ case BOOT_SNOR:
+ if (IS_FEAT_EN_4BL2_SNOR())
+ ssp->boot_bakups = 4;
+ else if (IS_FEAT_DIS_NBL2_SNOR())
+ ssp->boot_bakups = 1;
+ else
+ ssp->boot_bakups = 2; /* Default 2 backup, consistent with rom */
+ break;
+ case BOOT_SNAND:
+ if (IS_FEAT_EN_8BL2_SNAND())
+ ssp->boot_bakups = 8;
+ if (IS_FEAT_DIS_NBL2_SNAND())
+ ssp->boot_bakups = 1;
+ sip->snasp.pagesize = current->info.write_unit;
+ sip->snasp.pages_per_eraseblock =
+ current->info.erase_unit / current->info.write_unit;
+ sip->snasp.eraseblocks_per_lun =
+ (current->info.caps >> 20) / current->info.erase_unit;
+ sip->snasp.planes_per_lun = 1;
+ sip->snasp.luns_per_target = 1;
+ sip->snasp.ntargets = 1;
+ sip->snasp.layout_reserve_size =
+ NAND_RSV_BLOCK_NUM * current->info.erase_unit;
+ break;
+ case BOOT_NAND_NFTL:
+ case BOOT_NAND_MTD:
+ ssp->boot_bakups = 8;
+ if (IS_FEAT_DIS_8BL2_NAND())
+ ssp->boot_bakups = 4;
+ if (IS_FEAT_DIS_NBL2_NAND())
+ ssp->boot_bakups = 1;
+ sip->nsp.page_size = current->info.write_unit;
+ sip->nsp.block_size = current->info.erase_unit;
+ sip->nsp.pages_per_block =
+ current->info.erase_unit / current->info.write_unit;
+ sip->nsp.layout_reserve_size =
+ NAND_RSV_BLOCK_NUM * sip->nsp.block_size;
+ sip->nsp.page0_disable = NSP_PAGE0_DISABLE;
+ break;
+ default:
+ /* do nothing. */
+ break;
+ }
+
+ }
+
+ /* sanity check */
+
+ printf("boot_device:%d\n", ssp->boot_device);
+ printf("boot_seq:%d\n", ssp->boot_seq);
+ printf("boot_bakups:%d\n", ssp->boot_bakups);
+ printf("rebuid_id :%d\n", *need_build);
+
+ return 0;
+}
+
+int storage_post_init(void)
+{
+ int ret = -1;
+ int need_build = 0;
+
+ ret = storage_get_and_parse_ssp(&need_build);
+ if (ret < 0)
+ return -1;
+ storage_boot_layout_general_setting(&general_boot_layout, need_build);
+ storage_boot_layout_debug_info(&general_boot_layout);
+
+ return ret;
+}
+
+int store_init(u32 init_flag)
+{
+ cpu_id_t cpu_id = get_cpu_id();
+ int i, ret = 0;
+ u8 record = 0;
+
+ /*1. pre scan*/
+ for (i = 0; i < ARRAY_SIZE(device_list); i++) {
+ if (!device_list[i].pre()) {
+ record |= BIT(i);
+ }
+ }
+
+ if (!record) {
+ pr_info("No Valid storage device\n");
+ return record;
+ }
+
+ if ((cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) || (cpu_id.family_id == MESON_CPU_MAJOR_ID_T7)
+ || (cpu_id.family_id == MESON_CPU_MAJOR_ID_S4))
+ storage_post_init();
+
+ /*2. Enter the probe of the valid device*/
+ for (i = 0; i < ARRAY_SIZE(device_list); i++) {
+ if (record & BIT(i)) {
+ ret = device_list[i].probe(init_flag);
+ if (ret)
+ pr_info("the 0x%x storage device probe failed\n",
+ device_list[i].index);
+ }
+ }
+
+ return record;
+}
+
+static struct storage_t *store_get_current(void)
+{
+ return current;
+}
+
+int store_set_device(enum boot_type_e type)
+{
+ struct list_head *entry;
+ struct storage_t *dev, *store_dev = store_get_current();
+
+ if (!store_dev) {
+ pr_info("%s %d no current device\n", __func__, __LINE__);
+ return 1;
+ }
+ if (store_dev->type == type)
+ return 0;
+ list_for_each(entry, &store_dev->list) {
+ dev = list_entry(entry, struct storage_t, list);
+ if (dev->type == type) {
+ current = dev;
+ return 0;
+ }
+ }
+ pr_info("%s %d please confirm the %d device is valid\n",
+ __func__, __LINE__, type);
+ return 1;
+}
+
+enum boot_type_e store_get_type(void)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return BOOT_NONE;
+ }
+
+ return store->type;
+}
+
+int store_get_device_info(struct storage_info_t *info)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return 1;
+ }
+
+ memcpy((char *)info, (char *)&store->info,
+ sizeof(struct storage_info_t));
+ return 0;
+}
+
+int store_get_device_bootloader_mode(void)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return -1;
+ }
+ return store->info.mode;
+}
+
+int store_read(const char *name, loff_t off, size_t size, void *buf)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ return store->read(name, off, size, buf);
+}
+
+int store_write(const char *name, loff_t off, size_t size, void *buf)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ return store->write(name, off, size, buf);
+}
+
+int store_erase(const char *name, loff_t off, size_t size, int scrub)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ return store->erase(name, off, size, scrub);
+}
+
+u64 store_part_size(const char *name)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ return store->get_part_size(name);
+}
+
+u8 store_boot_copy_num(const char *name)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ return store->get_copies(name);
+}
+
+
+#ifndef SYSCTRL_SEC_STATUS_REG2
+static u32 fake_reg = 0;
+#define SYSCTRL_SEC_STATUS_REG2 (&fake_reg)
+#endif
+u8 store_boot_copy_start(void)
+{
+ struct storage_t *store = store_get_current();
+ cpu_id_t cpu_id = get_cpu_id();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return 0;
+ }
+ if (store->type != BOOT_EMMC)
+ return 0;
+ if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2 ||
+ cpu_id.family_id == MESON_CPU_MAJOR_ID_S4)
+ return storage_get_emmc_boot_start();
+ return 0;
+}
+
+u8 store_bootup_bootidx(const char *name)
+{
+ cpu_id_t cpu_id = get_cpu_id();
+ u8 bl2_idx = 0, fip_idx = 0;
+ u32 val = 0;
+
+ if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2 ||
+ cpu_id.family_id == MESON_CPU_MAJOR_ID_S4) {
+ bl2_idx = readl(SYSCTRL_SEC_STATUS_REG2) & 0xF;
+ //TODO: fixme after robust devfip is finished.
+ fip_idx = bl2_idx;
+ } else {
+ /* accroding to the:
+ commit 975b4acbcfa686601999d56843471d98e9c0a2cd
+ storage: robust boot: record bootlog in SEC_AO_SEC_GP_CFG2 [1/2]
+ PD#SWPL-4850
+ ...
+ record the bootup bl2/fip into SEC_AO_SEC_GP_CFG2
+ bit[27-25] bl2
+ bit[24-22] fip
+ */
+ val = readl(SEC_AO_SEC_GP_CFG2);
+ bl2_idx = (val >> 25) & 0x7;
+ fip_idx = (val >> 22) & 0x7;
+ }
+ if (!strncmp(name, "bl2", sizeof("bl2")) ||
+ !strncmp(name, "spl", sizeof("spl")))
+ return bl2_idx;
+ else
+ return fip_idx;
+}
+
+void store_restore_bootidx(void)
+{
+ cpu_id_t cpu_id = get_cpu_id();
+ if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2 ||
+ cpu_id.family_id == MESON_CPU_MAJOR_ID_S4) {
+ extern void aml_set_bootsequence(uint32_t val);
+ aml_set_bootsequence(0x55);
+ }
+ return;
+}
+
+u64 store_boot_copy_size(const char *name)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ return store->get_copy_size(name);
+}
+
+int store_boot_read(const char *name, u8 copy, size_t size, void *buf)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ return store->boot_read(name, copy, size, buf);
+}
+
+int store_boot_write(const char *name, u8 copy, size_t size, void *buf)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ return store->boot_write(name, copy, size, buf);
+}
+
+int store_boot_erase(const char *name, u8 copy)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ return store->boot_erase(name, copy);
+}
+
+int store_gpt_read(void *buf)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ if (!store->gpt_read)
+ return 1;
+ return store->gpt_read(buf);
+}
+
+int store_gpt_write(void *buf)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ if (!store->gpt_write)
+ return 1;
+ return store->gpt_write(buf);
+}
+
+int store_gpt_erase(void)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ if (!store->gpt_erase)
+ return 1;
+ return store->gpt_erase();
+}
+
+u32 store_rsv_size(const char *name)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ return store->get_rsv_size(name);
+}
+
+int store_rsv_read(const char *name, size_t size, void *buf)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ return store->read_rsv(name, size, buf);
+}
+
+int store_rsv_write(const char *name, size_t size, void *buf)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ return store->write_rsv(name, size, buf);
+}
+
+int store_rsv_erase(const char *name)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ return store->erase_rsv(name);
+}
+
+int store_rsv_protect(const char *name, bool ops)
+{
+ struct storage_t *store = store_get_current();
+
+ if (!store) {
+ pr_info("%s %d please init storage device first\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ return store->protect_rsv(name, ops);
+}
+
+static int do_store_init(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ u32 init_flag = 1;
+ u8 ret = 0;
+
+ if (unlikely(argc != 2 && argc != 3))
+ return CMD_RET_USAGE;
+
+ if (argc == 3)
+ init_flag = simple_strtoul(argv[2], NULL, 10);
+
+ /*Returns a nonzero value: device index*/
+ if (store_init(init_flag))
+ ret = 0;
+ else ret = 1;
+ return ret;
+}
+
+void store_print_device(struct storage_t *store_dev)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(device_list); i++)
+ if (store_dev->type & device_list[i].index)
+ pr_info("device type: [%s]\n", device_list[i].type);
+ pr_info("name %s\n", store_dev->info.name);
+ pr_info("id :");
+ for (i = 0; i < ARRAY_SIZE(store_dev->info.id); i++)
+ pr_info(" 0x%x", store_dev->info.id[i]);
+ pr_info("\n");
+ pr_info("read unit %d\n", store_dev->info.read_unit);
+ pr_info("write unit %d\n", store_dev->info.write_unit);
+ pr_info("erase unit %d\n", store_dev->info.erase_unit);
+ pr_info("total size %lld\n", store_dev->info.caps);
+ if (store_dev->info.mode)
+ pr_info("bootloader in discrete mode : %d\n",
+ store_dev->info.mode);
+ else
+ pr_info("bootloader in compact mode : %d\n",
+ store_dev->info.mode);
+}
+
+static int do_store_device(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ if (argc == 2) {
+ struct storage_t *store_dev, *dev;
+ struct list_head *entry;
+
+ store_dev = store_get_current();
+ pr_info("current device:\n");
+ pr_info("----------------------------------\n");
+ store_print_device(store_dev);
+ pr_info("----------------------------------\n");
+ list_for_each(entry, &store_dev->list) {
+ dev = list_entry(entry, struct storage_t, list);
+ pr_info("valid device:\n");
+ pr_info("----------------------------------\n");
+ store_print_device(dev);
+ pr_info("----------------------------------\n");
+ }
+ return 0;
+ } else if (argc == 3) {
+ char *name = NULL;
+ int i = 0, ret = 0;
+ name = argv[2];
+ for (i = 0; i < ARRAY_SIZE(device_list); i++)
+ if (!strcmp(name, device_list[i].type)) {
+
+ ret = store_set_device(device_list[i].index);
+ if (!ret) {
+ pr_info("now current device is: %s\n",
+ name);
+ return 0;
+ }
+ }
+ pr_info("%s %d no such device: %s\n",
+ __func__, __LINE__, name);
+ return ret;
+ }
+ return CMD_RET_USAGE;
+}
+
+static int do_store_partition(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ struct storage_t *store_dev;
+ int i = 0, partitions = 0;
+ int ret = 0;
+ char name[16];
+
+ if (argc > 2)
+ return CMD_RET_USAGE;
+ else {
+ store_dev = store_get_current();
+ if (store_dev->get_part_count)
+ partitions = store_dev->get_part_count();
+ pr_info("%d partitions of device %s:\n",
+ partitions, store_dev->info.name);
+
+ if (store_dev->list_part_name)
+ ret = store_dev->list_part_name(i, name);
+
+ return ret;
+ }
+}
+
+#ifdef CONFIG_AML_MTD
+extern int is_mtd_store_boot_area(const char *part_name);
+#endif
+static int do_store_erase(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ struct storage_t *store = store_get_current();
+ unsigned long offset;
+ size_t size = 0;
+ char *name = NULL;
+ char *s;
+ int scrub_flag = 0, ret;
+ unsigned long time;
+
+ const char *scrub =
+ "Warning: scrub_flag is 1!!!!"
+ "scrub operation!!!\n"
+ "will erase oob area\n"
+ "There is no reliable way to recover them.\n"
+ " "
+ "are sure of what you are doing!\n"
+ "\nReally erase this NAND flash? <y/N>\n";
+
+ if (!store) {
+ pr_info("%s %d please init your storage device first!\n",
+ __func__, __LINE__);
+ return CMD_RET_FAILURE;
+ }
+
+ if (strncmp(argv[1], "scrub", 5) == 0)
+ scrub_flag = 1;
+
+ if (scrub_flag == 1) {
+ puts(scrub);
+ if (!confirm_yesno()) {
+ printf("erase aborted\n");
+ return 1;
+ }
+ }
+
+ /*store erase.chip*/
+ s = strchr(argv[1], '.');
+ if (s != NULL && strcmp(s, ".chip") == 0) {
+ offset = 0;
+ } else {
+ /*store erase normal, partition name can't NULL*/
+ if (unlikely(argc != 5))
+ return CMD_RET_USAGE;
+
+ size = (size_t)simple_strtoul(argv[argc - 1], NULL, 16);
+ offset = simple_strtoul(argv[argc - 2], NULL, 16);
+ name = argv[2];
+#ifdef CONFIG_AML_MTD
+ if (is_mtd_store_boot_area(name)) {
+ pr_info("%s %d please enter normal partition name except tpl area!\n",
+ __func__, __LINE__);
+ return CMD_RET_FAILURE;
+ }
+#endif
+ }
+
+ time = get_timer(0);
+ ret = store->erase(name, offset, size, scrub_flag);
+ time = get_timer(time);
+
+ if (size != 0)
+ printf("%lu bytes ", size);
+
+ printf("erased in %lu ms", time);
+ if ((time > 0) && (size != 0)) {
+ puts(" (");
+ print_size(div_u64(size, time) * 1000, "/s");
+ puts(")");
+ }
+ puts("\n");
+
+ return ret;
+}
+
+static int do_store_read(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ struct storage_t *store = store_get_current();
+ unsigned long offset, addr, time;
+ size_t size;
+ char *name = NULL;
+ int ret;
+
+ if (!store) {
+ pr_info("%s %d please init your storage device first!\n",
+ __func__, __LINE__);
+ return CMD_RET_FAILURE;
+ }
+
+ if (unlikely(argc != 5 && argc != 6))
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[2], NULL, 16);
+ size = (size_t)simple_strtoul(argv[argc - 1], NULL, 16);
+ offset = simple_strtoul(argv[argc - 2], NULL, 16);
+ if (argc == 6)
+ name = argv[3];
+#ifdef CONFIG_AML_MTD
+ if (is_mtd_store_boot_area(name)) {
+ pr_info("%s %d please enter normal partition name except tpl area!\n",
+ __func__, __LINE__);
+ return CMD_RET_FAILURE;
+ }
+#endif
+ time = get_timer(0);
+ ret = store->read(name, offset, size, (u_char *)addr);
+ time = get_timer(time);
+
+ if (size != 0)
+ printf("%lu bytes ", size);
+
+ printf("read in %lu ms", time);
+ if ((time > 0) && (size != 0)) {
+ puts(" (");
+ print_size(div_u64(size, time) * 1000, "/s");
+ puts(")");
+ }
+ puts("\n");
+
+ return ret;
+}
+
+static int name2index(struct boot_layout *boot_layout, const char *img)
+{
+ boot_area_entry_t *boot_entry = NULL;
+ int i;
+
+ boot_entry = boot_layout->boot_entry;
+ for (i = 1; i < MAX_BOOT_AREA_ENTRIES && boot_entry[i].size; i++) {
+ if (!strncmp(img, boot_entry[i].name, strlen(boot_entry[i].name)))
+ return i;
+ }
+
+ return -1;
+}
+
+static int do_store_write_bl2img(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ struct storage_t *store = store_get_current();
+ unsigned long offset, addr;
+ size_t size, size_src;
+ char *name = NULL;
+ int ret = -1, index;
+ struct boot_layout *boot_layout = &general_boot_layout;
+
+ if (!store) {
+ pr_info("%s %d please init your storage device first!\n",
+ __func__, __LINE__);
+ return CMD_RET_FAILURE;
+ }
+
+ addr = simple_strtoul(argv[2], NULL, 16);
+ name = argv[3];
+ size = simple_strtoul(argv[4], NULL, 16);
+
+ index = name2index(&general_boot_layout, name);
+ offset = boot_layout->boot_entry[index].offset;
+ size_src = boot_layout->boot_entry[index].size;
+ printf("[%s] offset:0x%lx, index:%d\n", name, offset, index);
+
+ if (size_src != size)
+ printf("new img size:0x%lx != img src:0x%lx\n", size, size_src);
+
+ ret = store->boot_write(name, offset, size, (u_char *)addr);
+
+ return ret;
+}
+
+int store_write_bl2img(void* addr, const char *name, size_t size)
+{
+ struct storage_t *store = store_get_current();
+ unsigned long offset;
+ size_t size_src;
+ int ret = -1, index;
+ struct boot_layout *boot_layout = &general_boot_layout;
+
+ if (!store) {
+ pr_info("%s %d please init your storage device first!\n",
+ __func__, __LINE__);
+ return CMD_RET_FAILURE;
+ }
+
+ index = name2index(&general_boot_layout, name);
+ offset = boot_layout->boot_entry[index].offset;
+ size_src = boot_layout->boot_entry[index].size;
+ printf("[%s] offset:0x%lx, index:%d\n", name, offset, index);
+
+ if (size_src != size)
+ printf("new img size:0x%zx != img src:0x%zx\n", size, size_src);
+
+ ret = store->boot_write(name, offset, size, (u_char *)addr);
+ if (size != 0)
+ printf("[%s][%d]%lx bytes\n", __func__, __LINE__, size);
+
+ return ret;
+}
+
+static int do_store_write(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ struct storage_t *store = store_get_current();
+ unsigned long offset, addr, time;
+ size_t size;
+ char *name = NULL;
+ int ret;
+
+ if (!store) {
+ pr_info("%s %d please init your storage device first!\n",
+ __func__, __LINE__);
+ return CMD_RET_FAILURE;
+ }
+
+ if (unlikely(argc != 5 && argc != 6))
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[2], NULL, 16);
+ offset = simple_strtoul(argv[argc - 2], NULL, 16);
+ size = (size_t)simple_strtoul(argv[argc - 1], NULL, 16);
+ if (argc == 6)
+ name = argv[3];
+#ifdef CONFIG_AML_MTD
+ if (is_mtd_store_boot_area(name)) {
+ pr_info("%s %d please enter normal partition name except tpl area!\n",
+ __func__, __LINE__);
+ return CMD_RET_FAILURE;
+ }
+#endif
+ time = get_timer(0);
+ ret = store->write(name, offset, size, (u_char *)addr);
+ time = get_timer(time);
+
+ if (size != 0)
+ printf("%lu bytes ", size);
+
+ printf("write in %lu ms", time);
+ if ((time > 0) && (size != 0)) {
+ puts(" (");
+ print_size(div_u64(size, time) * 1000, "/s");
+ puts(")");
+ }
+ puts("\n");
+
+ return ret;
+}
+
+static int do_store_boot_read(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ struct storage_t *store = store_get_current();
+ unsigned long addr;
+ size_t size;
+ u8 cpy;
+ char *name;
+
+ if (!store) {
+ pr_info("%s %d please init your storage device first!\n",
+ __func__, __LINE__);
+ return CMD_RET_FAILURE;
+ }
+
+ if (unlikely(argc != 6))
+ return CMD_RET_USAGE;
+
+ name = argv[2];
+ addr = (unsigned long)simple_strtoul(argv[3], NULL, 16);
+ cpy = (u8)simple_strtoul(argv[4], NULL, 16);
+ size = (size_t)simple_strtoul(argv[5], NULL, 16);
+
+ return store->boot_read(name, cpy, size, (u_char *)addr);
+}
+
+static int bl2x_mode_check_header(p_payload_info_t pInfo)
+{
+ p_payload_info_hdr_t hdr = &pInfo->hdr;
+ const int nItemNum = hdr->byItemNum;
+ p_payload_info_item_t pItem = pInfo->arrItems;
+ u8 i = 0;
+ int sz_payload = 0;
+ uint64_t align_size = 1;
+ struct storage_startup_parameter *ssp = &g_ssp;
+ u8 cal_copy = ssp->boot_bakups;
+
+ printf("\naml log : info parse...\n");
+ printf("\tsztimes : %s\n",hdr->szTimeStamp);
+ printf("\tversion : %d\n",hdr->byVersion);
+ printf("\tItemNum : %d\n",nItemNum);
+ printf("\tSize : %d(0x%x)\n", hdr->nSize, hdr->nSize);
+ if (nItemNum > 8 || nItemNum < 3) {
+ pr_info("illegal nitem num %d\n", nItemNum);
+ return __LINE__;
+ }
+ if (ssp->boot_device == BOOT_NAND_MTD)
+ align_size = ((NAND_RSV_OFFSET / cal_copy) * ssp->sip.nsp.page_size);
+ else if (ssp->boot_device == BOOT_SNAND)
+ align_size = ((NAND_RSV_OFFSET / cal_copy) * ssp->sip.snasp.pagesize);
+
+ sz_payload = pItem->nPayLoadSize;
+ STORAGE_ROUND_UP_IF_UNALIGN(sz_payload, align_size);
+ if (sz_payload > ssp->boot_entry[0].size)
+ return __LINE__;
+ if (ssp->boot_device == BOOT_NAND_MTD)
+ align_size = ssp->sip.nsp.block_size;
+ else if (ssp->boot_device == BOOT_SNAND)
+ align_size = ssp->sip.snasp.pagesize *
+ ssp->sip.snasp.pages_per_eraseblock;
+ ++pItem;
+
+ for (i = 1; i < nItemNum; i++, ++pItem) {
+ sz_payload = pItem->nPayLoadSize;
+ STORAGE_ROUND_UP_IF_UNALIGN(sz_payload, align_size);
+ if (sz_payload > ssp->boot_entry[i].size)
+ return __LINE__;
+ }
+
+ return 0;
+}
+
+static int _store_boot_write(const char *part_name, u8 cpy, size_t size, void *addr)
+{
+ cpu_id_t cpu_id = get_cpu_id();
+ enum boot_type_e medium_type = store_get_type();
+ struct storage_startup_parameter *ssp = &g_ssp;
+
+
+ int ret = 0;
+ struct storage_t *store = store_get_current();
+ int bl2_size = BL2_SIZE;
+ int bl2_cpynum = 0;
+ int tpl_per_size = CONFIG_TPL_SIZE_PER_COPY;
+ int tpl_cpynum = 0;
+ int bootloader_maxsize = 0;
+
+ if (store_get_device_bootloader_mode() != DISCRETE_BOOTLOADER)
+ return store->boot_write(part_name, cpy, size, (u_char *)addr);
+
+ if (BOOT_NAND_MTD == medium_type || BOOT_SNAND == medium_type)
+ tpl_cpynum = CONFIG_NAND_TPL_COPY_NUM;
+ else if (medium_type == BOOT_SNOR)
+ tpl_cpynum = CONFIG_NOR_TPL_COPY_NUM;
+
+ if ((cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) || (cpu_id.family_id == MESON_CPU_MAJOR_ID_T7)
+ || (cpu_id.family_id == MESON_CPU_MAJOR_ID_S4)) {
+ bl2_cpynum = ssp->boot_bakups;
+ } else {
+ bootloader_maxsize = bl2_size + tpl_per_size;
+ bl2_cpynum = CONFIG_BL2_COPY_NUM;
+ if (size > bootloader_maxsize) {
+ pr_info("bootloader sz 0x%lx too large,max sz 0x%x\n",
+ size, bootloader_maxsize);
+ return CMD_RET_FAILURE;
+ }
+ }
+
+ if ((cpy >= tpl_cpynum || cpy >= bl2_cpynum) && (cpy != BOOT_OPS_ALL)) {
+ pr_info("update copy %d invalid, must < min(%d, %d)\n",
+ cpy, tpl_cpynum, bl2_cpynum);
+ return CMD_RET_FAILURE;
+ }
+
+ p_payload_info_t pinfo = parse_uboot_sheader((u8 *)addr);
+
+ if (!pinfo) {
+ ret = store->boot_write("tpl", cpy, size - bl2_size, (u_char *)(addr +bl2_size));
+ if (ret) {
+ pr_info("failed update tpl\n");
+ return CMD_RET_FAILURE;
+ }
+ } else {
+ if (bl2x_mode_check_header(pinfo)) {
+ pr_info("!!!warning bl2xx size is bigger than bl2x layout size\n");
+ pr_info("plase check bl2x,or erase flash and turn off\n");
+ pr_info("then turn on, and update uboot again\n");
+ return CMD_RET_FAILURE;
+ }
+
+ char name[8];
+ int nindex = 0;
+ p_payload_info_hdr_t hdr = &pinfo->hdr;
+ p_payload_info_item_t pitem = pinfo->arrItems;
+ int off_payload = 0;
+ int sz_payload = 0;
+
+ memset(name, 0, 8);
+ for (nindex = 1, pitem +=1; nindex < hdr->byItemNum; ++nindex, ++pitem) {
+ memcpy(name, &pitem->nMagic, sizeof(unsigned int));
+ off_payload = pitem->nOffset;
+ sz_payload = pitem->nPayLoadSize;
+ pr_info("item[%d]%4s offset 0x%08x sz 0x%x\n",
+ nindex, name, off_payload, sz_payload);
+ if (!sz_payload)
+ continue;
+ ret = store->boot_write(general_boot_part_entry[nindex].name, cpy, sz_payload, (u_char *)(addr + off_payload));
+ if (ret) {
+ pr_info("Fail in flash payload %s\n",name);
+ return CMD_RET_FAILURE;
+ }
+ }
+ }
+
+ ret = store->boot_write("bl2", cpy, bl2_size, (u_char *)addr);
+ if (ret) {
+ pr_info("Fail in flash payload bl2\n");
+ return CMD_RET_FAILURE;
+ }
+ return ret;
+
+}
+
+static int do_store_boot_write(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ struct storage_t *store = store_get_current();
+ unsigned long addr;
+ size_t size;
+ u8 cpy = BOOT_OPS_ALL;
+ char *name;
+
+ if (!store) {
+ pr_info("%s %d please init your storage device first!\n",
+ __func__, __LINE__);
+ return CMD_RET_FAILURE;
+ }
+
+ if (unlikely(argc != 5 && argc != 6))
+ return CMD_RET_USAGE;
+
+ name = argv[2];
+ addr = (unsigned long)simple_strtoul(argv[3], NULL, 16);
+ size = (size_t)simple_strtoul(argv[argc - 1], NULL, 16);
+ if (argc == 6)
+ cpy = (u8)simple_strtoul(argv[4], NULL, 16);
+
+ if (strcmp(name, "bootloader") == 0) {
+ return _store_boot_write(name, cpy, size, (u_char *)addr);
+ }
+
+ return store->boot_write(name, cpy, size, (u_char *)addr);
+}
+
+static int do_store_boot_erase(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ struct storage_t *store = store_get_current();
+ u8 cpy = BOOT_OPS_ALL;
+ char *name;
+
+ if (!store) {
+ pr_info("%s %d please init your storage device first!\n",
+ __func__, __LINE__);
+ return CMD_RET_FAILURE;
+ }
+
+ if (unlikely(argc != 3 && argc != 4))
+ return CMD_RET_USAGE;
+
+ name = argv[2];
+ if (argc == 4)
+ cpy = (u8)simple_strtoul(argv[3], NULL, 16);
+
+ return store->boot_erase(name, cpy);
+}
+
+static int do_store_gpt_read(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ struct storage_t *store = store_get_current();
+ unsigned long addr;
+ int ret;
+
+ if (!store) {
+ pr_info("%s %d please init your storage device first!\n",
+ __func__, __LINE__);
+ return CMD_RET_FAILURE;
+ }
+
+ if (unlikely(argc != 3))
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[2], NULL, 16);
+
+ if (store->gpt_read) {
+ ret = store->gpt_read((u_char *)addr);
+ return ret;
+ }
+
+ printf("read gpt is not prepared\n");
+ return CMD_RET_USAGE;
+}
+
+static int do_store_gpt_write(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ struct storage_t *store = store_get_current();
+ unsigned long addr;
+ int ret;
+
+ if (!store) {
+ pr_info("%s %d please init your storage device first!\n",
+ __func__, __LINE__);
+ return CMD_RET_FAILURE;
+ }
+
+ if (unlikely(argc != 3))
+ return CMD_RET_USAGE;
+
+ addr = simple_strtoul(argv[2], NULL, 16);
+
+ if (store->gpt_write) {
+ ret = store->gpt_write((u_char *)addr);
+ return ret;
+ }
+
+ printf("write gpt is not prepared\n");
+ return CMD_RET_USAGE;
+}
+
+static int do_store_gpt_erase(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ struct storage_t *store = store_get_current();
+ int ret;
+
+ if (!store) {
+ pr_info("%s %d please init your storage device first!\n",
+ __func__, __LINE__);
+ return CMD_RET_FAILURE;
+ }
+
+ if (unlikely(argc != 2))
+ return CMD_RET_USAGE;
+
+ if (store->gpt_erase) {
+ ret = store->gpt_erase();
+ return ret;
+ }
+
+ printf("erase gpt is not prepared\n");
+ return CMD_RET_USAGE;
+}
+
+static int do_store_rsv_ops(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ struct storage_t *store = store_get_current();
+ char *name = NULL;
+
+ if (!store) {
+ pr_info("%s %d please init your storage device first!\n",
+ __func__, __LINE__);
+ return CMD_RET_FAILURE;
+ }
+
+ if (!strcmp(argv[2], "erase")) {
+ if (argc == 3)
+ ;
+ else if (argc == 4)
+ name = argv[3];
+ else
+ return CMD_RET_USAGE;
+ return store->erase_rsv(name);
+ } else if (!strcmp(argv[2], "read") ||
+ !strcmp(argv[2], "write")) {
+ u8 cmd = strcmp(argv[2], "read") ? 0 : 1;
+ unsigned long addr = simple_strtoul(argv[4], NULL, 16);
+ size_t size = (size_t)simple_strtoul(argv[5], NULL, 16);
+
+ name = argv[3];
+ if (unlikely(argc != 6))
+ return CMD_RET_USAGE;
+ if (cmd)
+ return store->read_rsv(name, size, (u_char *)addr);
+ else
+ return store->write_rsv(name, size, (u_char *)addr);
+ } else if (!strcmp(argv[2], "protect")) {
+ bool flag = false;
+ char *ops;
+
+ if (unlikely(argc != 4 && argc != 5))
+ return CMD_RET_USAGE;
+
+ name = (argc == 4) ? NULL : argv[3];
+ ops = argv[argc - 1];
+ if (!strcmp(ops, "on"))
+ flag = true;
+ else if (!strcmp(ops, "off"))
+ flag = false;
+ return store->protect_rsv(name, flag);
+ }
+ return CMD_RET_USAGE;
+}
+
+static int do_store_param_ops(cmd_tbl_t *cmdtp,
+ int flag, int argc, char * const argv[])
+{
+ boot_area_entry_t *boot_entry = general_boot_layout.boot_entry;
+ cpu_id_t cpu_id = get_cpu_id();
+ char bufvir[64];
+ int lenvir, i, re;
+ u32 bl2e_size, bl2x_size;
+ char *p = bufvir;
+
+ if ((cpu_id.family_id != MESON_CPU_MAJOR_ID_SC2) &&
+ (cpu_id.family_id != MESON_CPU_MAJOR_ID_S4)) return 0;
+ bl2e_size = boot_entry[BOOT_AREA_BL2E].size;
+ bl2x_size = boot_entry[BOOT_AREA_BL2X].size;
+ lenvir = snprintf(bufvir, sizeof(bufvir), "%s", "mtdbootparts=aml-nand:");
+ p += lenvir;
+ re = sizeof(bufvir) - lenvir;
+ for (i = 0; i < 2; i++) { /* bl2e and bl2x */
+ if (i == 0)
+ lenvir = snprintf(p, re, "%dk(%s),",
+ (int)(bl2e_size / 1024),
+ "bl2e");
+ else
+ lenvir = snprintf(p, re, "%dk(%s),",
+ (int)(bl2x_size / 1024),
+ "bl2x");
+ re -= lenvir;
+ p += lenvir;
+ }
+ p = bufvir;
+ bufvir[strlen(p) - 1] = 0; /* delete the last comma */
+ env_set("mtdbootparts", p);
+
+ return 0;
+}
+
+static cmd_tbl_t cmd_store_sub[] = {
+ U_BOOT_CMD_MKENT(init, 4, 0, do_store_init, "", ""),
+ U_BOOT_CMD_MKENT(device, 4, 0, do_store_device, "", ""),
+ U_BOOT_CMD_MKENT(partition, 3, 0, do_store_partition, "", ""),
+ U_BOOT_CMD_MKENT(scrub, 5, 0, do_store_erase, "", ""),
+ U_BOOT_CMD_MKENT(erase, 5, 0, do_store_erase, "", ""),
+ U_BOOT_CMD_MKENT(read, 6, 0, do_store_read, "", ""),
+ U_BOOT_CMD_MKENT(write, 7, 0, do_store_write, "", ""),
+ U_BOOT_CMD_MKENT(write_gpt, 3, 0, do_store_gpt_write, "", ""),
+ U_BOOT_CMD_MKENT(read_gpt, 3, 0, do_store_gpt_read, "", ""),
+ U_BOOT_CMD_MKENT(erase_gpt, 2, 0, do_store_gpt_erase, "", ""),
+ U_BOOT_CMD_MKENT(write_bl2img, 5, 0, do_store_write_bl2img, "", ""),
+ U_BOOT_CMD_MKENT(boot_read, 6, 0, do_store_boot_read, "", ""),
+ U_BOOT_CMD_MKENT(boot_write, 6, 0, do_store_boot_write, "", ""),
+ U_BOOT_CMD_MKENT(boot_erase, 4, 0, do_store_boot_erase, "", ""),
+ U_BOOT_CMD_MKENT(rsv, 6, 0, do_store_rsv_ops, "", ""),
+ U_BOOT_CMD_MKENT(param, 2, 0, do_store_param_ops, "", ""),
+};
+
+static int do_store(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ cmd_tbl_t *c;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+
+ c = find_cmd_tbl(argv[1], cmd_store_sub, ARRAY_SIZE(cmd_store_sub));
+ if (c)
+ return c->cmd(cmdtp, flag, argc, argv);
+
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(store, CONFIG_SYS_MAXARGS, 1, do_store,
+ "STORE sub-system:",
+ "store init [flag]\n"
+ " init storage device\n"
+ "store device [name]\n"
+ " show or set storage device\n"
+ " 'store device' command will list\n"
+ " all valid storage device and print.\n"
+ " 'store device [name]' will set the\n"
+ " [name] device to the current device\n"
+ "store partition\n"
+ " show partitions of current device\n"
+ "store read addr [partition name] off size\n"
+ " read 'size' bytes from offset 'off'\n"
+ " of device/partition 'partition name' to.\n"
+ " address 'addr' of memory.\n"
+ " if partition name not value. read start with\n"
+ " offset in normal logic area,if tpl area exist\n"
+ " read offset at end of tpl area\n"
+ "store write addr [partition name] off size\n"
+ " write 'size' bytes to offset 'off' of\n"
+ " device/partition [partition name] from\n"
+ " address 'addr' of memory.\n"
+ " if partition name not value. write start with\n"
+ " offset in normal logic area,if tpl area exist\n"
+ " write offset at end of tpl area\n"
+ "store write_gpt addr\n"
+ " write gpt from address 'addr'\n"
+ "store read_gpt addr\n"
+ " read gpt to address 'addr'\n"
+ "store erase_gpt\n"
+ " erase primary and secondary gpt\n"
+ "store erase partition name off size.\n"
+ " erase 'size' bytes from offset 'off'\n"
+ " of device/partition [partition name]\n"
+ " partition name must't NULL\n"
+ "store scrub partition name off size.\n"
+ " erase 'size' bytes from offset 'off'\n"
+ " of device/partition [partition name]\n"
+ " includes oob area if the device has.\n"
+ " partition name must't NULL\n"
+ "store erase.chip\n"
+ " erase all nand chip,except bad block\n"
+ "store scrub.chip\n"
+ " erase all nand chip,include bad block\n"
+ "store boot_read name addr copy size\n"
+ " read 'size' bytes from 'copy'th backup\n"
+ " in name partition, 'copy' can't be null.\n"
+ " name:\n"
+ " in discrete mode: 'bl2'/'tpl'(fip)\n"
+ " in compact mode: 'bootloader'\n"
+ "store boot_write name addr [copy] size\n"
+ " write 'size' bytes to 'copy'th backup\n"
+ " in [name] partition from address\n"
+ " 'addr' of memory. when the optional 'copy'\n"
+ " is null, it will writes to all copies\n"
+ " name:\n"
+ " in discrete mode:\n"
+ " 'bl2/bl2e/bl2x/ddrfip/tpl(fip), only update part\n"
+ " 'bootloader', update whole uboot.bin, in this case\n"
+ " @copy:if used, must < min(tplCpyNum, Bl2CpyNum), update only the specified copy\n"
+ " if not used, update all the copies of bl2 bl2e bl2x ddrfip tpl!\n"
+ " in compact mode: 'bootloader'\n"
+ "store boot_erase name [copy]\n"
+ " erase the name info from 'copy'th backup\n"
+ " when the optional 'copy' not value, it\n"
+ " will erase all copies.\n"
+ " name:\n"
+ " in discrete mode: \n"
+ " 'bl2'/'tpl'(fip): erase bl2/tpl partition\n"
+ " 'bootloader':erase bl2 + tpl partition\n"
+ " in compact mode: 'bootloader'\n"
+ "store rsv read name addr size\n"
+ " read 'size' bytes 'name' rsv info\n"
+ " to address 'addr' of memory\n"
+ " 'name' could be key/dtb/env etc...\n"
+ "store rsv write name addr size\n"
+ " write 'size' bytes 'name' rsv info\n"
+ " from address 'addr' of memory\n"
+ "store rsv erase name\n"
+ " erase 'name' rsv info\n"
+ " name must't null\n"
+ "store rsv protect name on/off\n"
+ " turn on/off the rsv info protection\n"
+ " name must't null\n"
+ "store param\n"
+ " transfer bl2e/x size to kernel in such case like sc2"
+);
diff --git a/cmd/tcpc.c b/cmd/tcpc.c
new file mode 100644
index 0000000..2ef6537
--- /dev/null
+++ b/cmd/tcpc.c
@@ -0,0 +1,25 @@
+#include <common.h>
+#include <command.h>
+#include <usb_tcpc.h>
+
+static int do_tcpc(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ extern char tcpc_started;
+
+ if (argc != 2)
+ return CMD_RET_USAGE;
+
+ if (strncmp(argv[1], "start", 5) == 0) {
+ if (tcpc_started)
+ return 0; /* Already started */
+ printf("starting TCPC...\n");
+ tcpc_init();
+ return 0;
+ }
+
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(tcpc, 2, 0, do_tcpc,
+ "run commands and summarize execution time",
+ "start - start USB-C port controller and PD explicit contract\n");
diff --git a/cmd/ti/Kconfig b/cmd/ti/Kconfig
index 9f61723..efeff0d 100644
--- a/cmd/ti/Kconfig
+++ b/cmd/ti/Kconfig
@@ -8,4 +8,3 @@
verification if supported.
endmenu
-
diff --git a/cmd/usb.c b/cmd/usb.c
index 0ccb1b5..8c3c852 100644
--- a/cmd/usb.c
+++ b/cmd/usb.c
@@ -730,6 +730,22 @@
#endif /* CONFIG_USB_STORAGE */
}
+int do_usb_detect(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ if (argc >= 2) {
+ return usb_aml_detect_operation(argc, argv);
+ }
+ return CMD_RET_USAGE;
+}
+
+U_BOOT_CMD(
+ musb, 5, 1, do_usb_detect,
+ "using for get USB information",
+ "info ----default operation to get dts information\n"
+ "musb disable ----disable USB PHY\n"
+);
+
+
U_BOOT_CMD(
usb, 5, 1, do_usb,
"USB sub-system",
diff --git a/cmd/watchdog.c b/cmd/watchdog.c
index cc79852..317f7d4 100644
--- a/cmd/watchdog.c
+++ b/cmd/watchdog.c
@@ -1,7 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include <common.h>
#include <command.h>
#include <dm.h>
-#include <asm/arch/watchdog.h>
#include <wdt.h>
static int do_watchdog(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
@@ -14,6 +18,7 @@
if (argc != 2)
return CMD_RET_USAGE;
cmd = argv[1];
+
ret = uclass_get_device_by_name(UCLASS_WDT, "watchdog", &watchdog_devp);
if (ret < 0) {
printf("Failed to find watchdog node, check device tree.\n");
@@ -24,6 +29,11 @@
wdt_stop(watchdog_devp);
return CMD_RET_SUCCESS;
}
+
+ if (strcmp(cmd, "ping") == 0) {
+ wdt_reset(watchdog_devp);
+ return CMD_RET_SUCCESS;
+ }
timeout = simple_strtoul(cmd, &endp, 0);
if (endp == cmd)
return CMD_RET_USAGE;
@@ -31,7 +41,8 @@
return CMD_RET_USAGE;
/* enable the watchdog and set timeout */
- wdt_start(watchdog_devp, timeout, 0);
+ wdt_start(watchdog_devp, timeout * 1000, 0);
+ wdt_reset(watchdog_devp);
return CMD_RET_SUCCESS;
}
@@ -41,5 +52,6 @@
"enable or disable watchdog",
"<timeout> - enable watchdog with `timeout' seconds timeout\n"
"watchdog off - disable watchdog\n"
+ "watchdog ping - ping watchdog\n"
);
diff --git a/cmd/ximg.c b/cmd/ximg.c
index 4fd1b26..6880c74 100644
--- a/cmd/ximg.c
+++ b/cmd/ximg.c
@@ -131,7 +131,7 @@
"at %08lx ...\n", uname, addr);
fit_hdr = (const void *)addr;
- if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) {
+ if (!fit_check_format(fit_hdr)) {
puts("Bad FIT image format\n");
return 1;
}
diff --git a/common/Kconfig b/common/Kconfig
index 556d42f..8f43b00 100644
--- a/common/Kconfig
+++ b/common/Kconfig
@@ -185,7 +185,7 @@
config BOOTDELAY
int "delay in seconds before automatically booting"
- default 2
+ default 0
depends on AUTOBOOT
help
Delay before automatically running bootcmd;
@@ -799,4 +799,3 @@
endmenu
source "common/spl/Kconfig"
-
diff --git a/common/Makefile b/common/Makefile
index b81dac8..8bf68bd 100644
--- a/common/Makefile
+++ b/common/Makefile
@@ -12,8 +12,8 @@
obj-$(CONFIG_HUSH_PARSER) += cli_hush.o
obj-$(CONFIG_AUTOBOOT) += autoboot.o
-obj-$(CONFIG_CMD_MMC) += partitions.o
-obj-$(CONFIG_CMD_MMC) += aml_dt.o
+obj-$(CONFIG_AML_STORAGE) += partitions.o
+obj-$(CONFIG_AML_STORAGE) += aml_dt.o
# This option is not just y/n - it can have a numeric value
ifdef CONFIG_BOOT_RETRY_TIME
@@ -111,7 +111,6 @@
obj-y += image.o
obj-$(CONFIG_ANDROID_BOOT_IMAGE) += image-android.o
-obj-$(CONFIG_ZIRCON_BOOT_IMAGE) += image-zircon.o
obj-$(CONFIG_$(SPL_TPL_)OF_LIBFDT) += image-fdt.o
obj-$(CONFIG_$(SPL_TPL_)FIT) += image-fit.o
obj-$(CONFIG_$(SPL_)MULTI_DTB_FIT) += boot_fit.o common_fit.o
@@ -126,10 +125,13 @@
obj-y += eeprom/eeprom_field.o eeprom/eeprom_layout.o
endif
+obj-$(CONFIG_CMD_SHA2) += cmd_sha2.o
+
obj-y += cli.o
obj-$(CONFIG_FSL_DDR_INTERACTIVE) += cli_simple.o cli_readline.o
obj-$(CONFIG_DFU_OVER_USB) += dfu.o
obj-y += command.o
+obj-$(CONFIG_MESON_LEDS_STATE_CONTROL) += cmd_leds_state.o
obj-$(CONFIG_$(SPL_TPL_)LOG) += log.o
obj-$(CONFIG_$(SPL_TPL_)LOG_CONSOLE) += log_console.o
obj-y += s_record.o
@@ -137,3 +139,6 @@
obj-$(CONFIG_$(SPL_TPL_)YMODEM_SUPPORT) += xyzModem.o
obj-$(CONFIG_AVB_VERIFY) += avb_verify.o
+obj-$(CONFIG_MDUMP_COMPRESS) += ramdump.o
+
+obj-y += blxx2bl33_param.o
diff --git a/common/aml_dt.c b/common/aml_dt.c
index 6a03f02..a9726e2 100644
--- a/common/aml_dt.c
+++ b/common/aml_dt.c
@@ -1,3 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include <common.h>
#include <bootm.h>
#include <command.h>
@@ -5,6 +10,7 @@
#include <malloc.h>
#include <asm/arch/io.h>
#include <asm/arch/secure_apb.h>
+#include <partition_table.h>
//#define AML_DT_DEBUG
#ifdef AML_DT_DEBUG
@@ -13,6 +19,333 @@
#define dbg_printf(...) ((void)0)
#endif
+#define AML_MULTI_DTB_API_NEW
+//#define AML_MULTI_DTB_CHECK_CMD //command for multi-dtb test
+
+#ifdef AML_MULTI_DTB_API_NEW
+
+/*for multi-dtb gzip buffer*/
+#define GUNZIP_BUF_SIZE (1<<20) /*1MB is enough?*/
+
+/*magic for multi-dtb*/
+#define MAGIC_GZIP_MASK (0x0000FFFF)
+#define MAGIC_GZIP_ID (0x00008B1F)
+#define IS_GZIP_PACKED(nMagic) (MAGIC_GZIP_ID == (MAGIC_GZIP_MASK & nMagic))
+#define MAGIC_DTB_SGL_ID (0xedfe0dd0)
+#define MAGIC_DTB_MLT_ID (0x5f4c4d41)
+
+/*amlogic multi-dtb version*/
+#define AML_MUL_DTB_VER_1 (1)
+#define AML_MUL_DTB_VER_2 (2)
+
+/*max char for dtb name, fixed to soc_package_board format*/
+#define AML_MAX_DTB_NAME_SIZE (128)
+#define AML_DTB_TOKEN_MAX_COUNT (AML_MAX_DTB_NAME_SIZE>>1)
+
+typedef struct{
+ unsigned int nMagic;
+ unsigned int nVersion;
+ unsigned int nDTBCount;
+}st_dtb_hdr_t,*p_st_dtb_hdr_t;
+
+/*v1,v2 multi-dtb only support max to 3 tokens for each DTB name*/
+#define MULTI_DTB_TOKEN_MAX_COUNT (3)
+#define MULTI_DTB_TOKEN_UNIT_SIZE_V1 (4) //v1 support 4bytes for each token
+#define MULTI_DTB_TOKEN_UNIT_SIZE_V2 (16) //v2 support 16bytes for each token
+
+/*v1 multi-dtb*/
+typedef struct{
+ unsigned char szToken[MULTI_DTB_TOKEN_MAX_COUNT][MULTI_DTB_TOKEN_UNIT_SIZE_V1];
+ int nDTBOffset;
+ int nDTBIMGSize;
+}st_dtb_token_v1_t,*p_st_dtb_token_v1_t;
+
+typedef struct{
+ st_dtb_hdr_t hdr;
+ st_dtb_token_v1_t dtb[1];
+}st_dtb_v1_t,*p_st_dtb_v1_t;
+
+
+/*v2 multi-dtb*/
+typedef struct{
+ unsigned char szToken[MULTI_DTB_TOKEN_MAX_COUNT][MULTI_DTB_TOKEN_UNIT_SIZE_V2];
+ int nDTBOffset;
+ int nDTBIMGSize;
+}st_dtb_token_v2_t,*p_st_dtb_token_v2_t;
+
+typedef struct{
+ st_dtb_hdr_t hdr;
+ st_dtb_token_v2_t dtb[1];
+}st_dtb_v2_t,*p_st_dtb_v2_t;
+
+
+/*to get the valid DTB index with matched DTB name*/
+static int get_dtb_index(const char aml_dt_buf[128],unsigned long fdt_addr)
+{
+ int nReturn = -1;
+
+ if (!aml_dt_buf)
+ goto exit;
+
+ p_st_dtb_hdr_t pDTBHdr = (p_st_dtb_hdr_t)fdt_addr;
+ char sz_aml_dt_msb[10][MULTI_DTB_TOKEN_UNIT_SIZE_V2];
+ memset(sz_aml_dt_msb,0,sizeof(sz_aml_dt_msb));
+
+ /* split aml_dt with token '_', e.g "tm2-revb_t962x3_ab301" */
+ //printf(" aml_dt : %s\n",aml_dt_buf);
+
+ char *tokens[AML_DTB_TOKEN_MAX_COUNT];
+ char sz_temp[AML_MAX_DTB_NAME_SIZE+4];
+ memset(tokens,0,sizeof(tokens));
+ memset(sz_temp,0,sizeof(sz_temp));
+ strncpy(sz_temp,aml_dt_buf,128);
+ int i,j;
+ int nLen = strlen(sz_temp);
+ sz_temp[nLen]='_';
+ sz_temp[nLen+1]='\0';
+ nLen +=1;
+ tokens[0]=sz_temp;
+ for (i = 1; i < sizeof(tokens)/sizeof(tokens[0]); i++)
+ {
+ tokens[i] = strstr(tokens[i-1],"_");
+ if (!tokens[i])
+ break;
+
+ *tokens[i]='\0';
+
+ tokens[i]=tokens[i]+1;
+
+ if (!(*tokens[i]))
+ {
+ tokens[i] = 0;
+ break;
+ }
+ }
+
+ //for (i=0;i<10 && tokens[i];++i)
+ // printf("token-%d:%s\n",i,tokens[i]);
+
+ int nTokenLen = 0;
+
+ switch (pDTBHdr->nVersion)
+ {
+ case AML_MUL_DTB_VER_1:
+ {
+ nTokenLen = MULTI_DTB_TOKEN_UNIT_SIZE_V1;
+ }break;
+ case AML_MUL_DTB_VER_2:
+ {
+ nTokenLen = MULTI_DTB_TOKEN_UNIT_SIZE_V2;
+ }break;
+ default: goto exit; break;
+ }
+
+
+ for (i = 0;i<MULTI_DTB_TOKEN_MAX_COUNT;++i)
+ {
+ if (tokens[i])
+ {
+ char *pbyswap = (char*)sz_aml_dt_msb+(nTokenLen*i);
+ strcpy(pbyswap,tokens[i]);
+ unsigned int nValSwap;
+ for (j = 0;j< nTokenLen;j+=4)
+ {
+ int m;
+ /*swap byte order with unit@4bytes*/
+ nValSwap = *(unsigned int *)(pbyswap+j);
+ for (m=0;m<4;m++)
+ pbyswap[j+m] = (nValSwap >> ((3-m)<<3)) & 0xFF;
+
+ /*replace 0 with 0x20*/
+ for (m=0;m<MULTI_DTB_TOKEN_UNIT_SIZE_V2;++m)
+ if (0 == pbyswap[m])
+ pbyswap[m]=0x20;
+ }
+ }
+ else
+ break;
+ }
+
+ switch (pDTBHdr->nVersion)
+ {
+ case AML_MUL_DTB_VER_1:
+ {
+ p_st_dtb_v1_t pDTB_V1 = (p_st_dtb_v1_t)fdt_addr;
+ for (i=0;i< pDTB_V1->hdr.nDTBCount;++i)
+ {
+ if (!memcmp(pDTB_V1->dtb[i].szToken,sz_aml_dt_msb,
+ MULTI_DTB_TOKEN_MAX_COUNT*nTokenLen))
+ {
+ nReturn = i;
+ break;
+ }
+ }
+
+ }break;
+ case AML_MUL_DTB_VER_2:
+ {
+ p_st_dtb_v2_t pDTB_V2 = (p_st_dtb_v2_t)fdt_addr;
+ for (i=0;i< pDTB_V2->hdr.nDTBCount;++i)
+ {
+ if (!memcmp(pDTB_V2->dtb[i].szToken,sz_aml_dt_msb,
+ MULTI_DTB_TOKEN_MAX_COUNT*nTokenLen))
+ {
+ nReturn = i;
+ break;
+ }
+ }
+
+ }break;
+ default: goto exit; break;
+ }
+
+exit:
+
+ return nReturn;
+
+}
+
+unsigned long __attribute__((unused)) get_multi_dt_entry(unsigned long fdt_addr)
+{
+ unsigned long lReturn = 0; //return buffer for valid DTB;
+ void * gzip_buf = NULL;
+ unsigned long pInputFDT = fdt_addr;
+ p_st_dtb_hdr_t pDTBHdr = (p_st_dtb_hdr_t)pInputFDT;
+ unsigned long unzip_size = GUNZIP_BUF_SIZE;
+
+ printf(" Amlogic Multi-DTB tool\n");
+
+ /* first check the blob header, support GZIP format */
+ if ( IS_GZIP_PACKED(pDTBHdr->nMagic))
+ {
+ printf(" GZIP format, decompress...\n");
+ gzip_buf = malloc(GUNZIP_BUF_SIZE);
+ if (!gzip_buf)
+ {
+ printf(" ERROR! fail to allocate memory for GUNZIP...\n");
+ goto exit;
+ }
+ memset(gzip_buf, 0, GUNZIP_BUF_SIZE);
+ if (gunzip(gzip_buf, GUNZIP_BUF_SIZE, (void *)pInputFDT, &unzip_size) < 0)
+ {
+ printf(" ERROR! GUNZIP process fail...\n");
+ goto exit;
+ }
+ if (unzip_size > GUNZIP_BUF_SIZE)
+ {
+ printf(" ERROR! GUNZIP overflow...\n");
+ goto exit;
+ }
+ //memcpy((void*)fdt_addr,gzip_buf,unzip_size);
+ pInputFDT = (unsigned long)gzip_buf;
+ pDTBHdr = (p_st_dtb_hdr_t)pInputFDT;
+ }
+
+
+ switch (pDTBHdr->nMagic)
+ {
+ case MAGIC_DTB_SGL_ID:
+ {
+ printf(" Single DTB detected\n");
+
+ if (fdt_addr != (unsigned long)pInputFDT) //in case of GZIP single DTB
+ memcpy((void*)fdt_addr,(void*)pInputFDT,unzip_size);
+
+ lReturn = fdt_addr;
+
+ }break;
+ case MAGIC_DTB_MLT_ID:
+ {
+ printf(" Multi DTB detected.\n");
+ printf(" Multi DTB tool version: v%d.\n", pDTBHdr->nVersion);
+ printf(" Support %d DTBS.\n", pDTBHdr->nDTBCount);
+
+
+ /* check and set aml_dt */
+ char aml_dt_buf[AML_MAX_DTB_NAME_SIZE+4];
+ memset(aml_dt_buf, 0, sizeof(aml_dt_buf));
+
+ /* update 2016.07.27, checkhw and setenv everytime,
+ or else aml_dt will set only once if it is reserved */
+ extern int checkhw(char * name);
+#if 1
+ if (checkhw(aml_dt_buf) < 0 || strlen(aml_dt_buf) <= 0)
+ {
+ printf(" Get env aml_dt failed!\n");
+ goto exit;
+ }
+#else
+ char *aml_dt = getenv(AML_DT_UBOOT_ENV);
+ /* if aml_dt not exist or env not ready, get correct dtb by name */
+ if (NULL == aml_dt)
+ checkhw(aml_dt_buf);
+ else
+ memcpy(aml_dt_buf, aml_dt,
+ (strlen(aml_dt)>AML_MAX_DTB_NAME_SIZE?AML_MAX_DTB_NAME_SIZE:(strlen(aml_dt)+1)));
+#endif
+
+ int dtb_match_num = get_dtb_index(aml_dt_buf,(unsigned long)pInputFDT);
+
+ /*check valid dtb index*/
+ if (dtb_match_num < 0 || dtb_match_num >= pDTBHdr->nDTBCount)
+ {
+ printf(" NOT found matched DTB for \"%s\"\n",aml_dt_buf);
+ goto exit;
+ }
+
+ printf(" Found DTB for \"%s\"\n",aml_dt_buf);
+
+ switch (pDTBHdr->nVersion)
+ {
+ case AML_MUL_DTB_VER_1:
+ {
+ p_st_dtb_v1_t pDTB_V1 = (p_st_dtb_v1_t)pInputFDT;
+ lReturn = pDTB_V1->dtb[dtb_match_num].nDTBOffset + pInputFDT;
+
+ //if (pInputFDT != fdt_addr)
+ {
+ memcpy((void*)fdt_addr, (void*)lReturn,pDTB_V1->dtb[dtb_match_num].nDTBIMGSize);
+ lReturn = fdt_addr;
+ }
+
+ }break;
+ case AML_MUL_DTB_VER_2:
+ {
+ p_st_dtb_v2_t pDTB_V2 = (p_st_dtb_v2_t)pInputFDT;
+ lReturn = pDTB_V2->dtb[dtb_match_num].nDTBOffset + pInputFDT;
+
+ //if (pInputFDT != fdt_addr)
+ {
+ memcpy((void*)fdt_addr, (void*)lReturn,pDTB_V2->dtb[dtb_match_num].nDTBIMGSize);
+ lReturn = fdt_addr;
+ }
+
+ }break;
+ default:
+ {
+ printf(" Invalid Multi-DTB Version [%d]!\n",
+ pDTBHdr->nVersion);
+ goto exit;
+ }break;
+ }
+
+ }break;
+ default: goto exit; break;
+ }
+
+exit:
+
+ if (gzip_buf)
+ {
+ free(gzip_buf);
+ gzip_buf = 0;
+ }
+
+ return lReturn;
+}
+
+#else //#ifdef AML_MULTI_DTB_API_NEW
+
#define AML_DT_IND_LENGTH_V1 4 /*fixed*/
#define AML_DT_IND_LENGTH_V2 16 /*fixed*/
@@ -35,7 +368,7 @@
#define IS_GZIP_FORMAT(data) ((data & (0x0000FFFF)) == (0x00008B1F))
#define GUNZIP_BUF_SIZE (0x500000) /* 5MB */
-#define DTB_MAX_SIZE (0x40000) /* 256KB */
+#define DTB_MAX_SIZE (AML_DTB_IMG_MAX_SZ)
//#define readl(addr) (*(volatile unsigned int*)(addr))
extern int checkhw(char * name);
@@ -69,7 +402,6 @@
dbg_printf(" DBG: fdt_addr: 0x%x\n", (unsigned int)fdt_addr);
dbg_printf(" DBG: dt_magic: 0x%x\n", (unsigned int)dt_magic);
- dbg_printf(" DBG: gzip_format: %d\n", gzip_format);
/*printf(" Process device tree. dt magic: %x\n", dt_magic);*/
if (dt_magic == DT_HEADER_MAGIC) {/*normal dtb*/
@@ -86,7 +418,10 @@
printf(" Multi dtb detected\n");
/* check and set aml_dt */
int i = 0;
- char aml_dt_buf[64] = {0};
+ char *aml_dt_buf;
+ aml_dt_buf = (char *)malloc(sizeof(char)*64);
+ printf("Multi dtb malloc aml_dt_buf addr = %p\n", aml_dt_buf);
+ memset(aml_dt_buf, 0, sizeof(aml_dt_buf));
/* update 2016.07.27, checkhw and setenv everytime,
or else aml_dt will set only once if it is reserved */
@@ -101,9 +436,13 @@
memcpy(aml_dt_buf, aml_dt, (strlen(aml_dt)>64?64:(strlen(aml_dt)+1)));
#endif
- unsigned int aml_dt_len = strlen(aml_dt_buf);
+ unsigned int aml_dt_len = aml_dt_buf ? strlen(aml_dt_buf) : 0;
if (aml_dt_len <= 0) {
printf(" Get env aml_dt failed!\n");
+ if (aml_dt_buf)
+ free(aml_dt_buf);
+ if (gzip_buf)
+ free(gzip_buf);
return fdt_addr;
}
@@ -127,12 +466,12 @@
/* split aml_dt to 3 strings */
char *tokens[3] = {NULL, NULL, NULL};
- char *sep_start = aml_dt_buf;
for (i = 0; i < AML_DT_ID_VARI_TOTAL; i++) {
- tokens[i] = strsep(&sep_start, "_");
+ tokens[i] = strsep(&aml_dt_buf, "_");
}
- printf(" aml_dt soc: %s platform: %s variant: %s\n", tokens[0],
- tokens[1], tokens[2]);
+ //if (aml_dt_buf)
+ //free(aml_dt_buf);
+ printf(" aml_dt soc: %s platform: %s variant: %s\n", tokens[0], tokens[1], tokens[2]);
/*match and print result*/
char **dt_info;
@@ -213,7 +552,34 @@
}
else {
printf(" Cannot find legal dtb!\n");
+ if (gzip_buf)
+ free(gzip_buf);
return fdt_addr;
}
+}
+#endif //#ifdef AML_MULTI_DTB_API_NEW
+
+extern int check_valid_dts(unsigned char *buffer);
+#ifdef AML_MULTI_DTB_CHECK_CMD
+static int do_test(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned long loadaddr = 0x1080000;
+
+ if (argc > 1)
+ loadaddr = simple_strtoul(argv[1],NULL,16);
+
+ check_valid_dts((void*)loadaddr);
+
return 0;
}
+
+U_BOOT_CMD(
+ dtb_chk, //command name
+ 2, //maxargs
+ 0, //repeatable
+ do_test, //command function
+ "multi-dtb check command", //description
+ " argv: dtb_chk <dtbLoadaddr> \n" //usage
+ " do dtb check, which already loaded at <dtbLoadaddr>.\n"
+);
+#endif //#ifdef AML_MULTI_DTB_CHECK_CMD
diff --git a/common/autoboot.c b/common/autoboot.c
index 94133ea..4dcfb18 100644
--- a/common/autoboot.c
+++ b/common/autoboot.c
@@ -294,6 +294,11 @@
bootcount_inc();
+#ifdef CONFIG_SILENT_CONSOLE
+ /* disable silent */
+ gd->flags &= ~GD_FLG_SILENT;
+#endif
+
s = env_get("bootdelay");
bootdelay = s ? (int)simple_strtol(s, NULL, 10) : CONFIG_BOOTDELAY;
diff --git a/common/blxx2bl33_param.c b/common/blxx2bl33_param.c
new file mode 100644
index 0000000..0adc679
--- /dev/null
+++ b/common/blxx2bl33_param.c
@@ -0,0 +1,45 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <amlogic/blxx2bl33_param.h>
+
+#define param_end(x) ((x) > (BL2E2BL33_PARAM_END))
+
+struct param_e *next_entry(struct param_e *param_pre)
+{
+ struct param_e *param_next;
+
+ param_next = (struct param_e *)((unsigned long)param_pre + param_pre->len);
+ if (param_end((unsigned long)param_next))
+ return NULL;
+
+ return param_next;
+}
+
+struct param_e *param_of(int type)
+{
+ struct param_e *param;
+
+ param = (struct param_e *)BL2E2BL33_PARAM_START;
+
+#if BLXX2BL33_PARAM_DEBUG
+ {
+ int i = 1;
+ unsigned char *data = (unsigned char *)BL2E2BL33_PARAM_START;
+ for (; i <= 512; i++) {
+ printf("%02x ", data[i-1]);
+ if (i%16 == 0)
+ printf("\n");
+ }
+ }
+#endif
+
+ for (; param && param->type; param = next_entry(param)) {
+ if (param->type == STORAGE_PARAM_TPYE)
+ return param;
+ }
+ printf("ERROR param_of(Type=%d) not found\n", param->type);
+ return NULL;
+}
\ No newline at end of file
diff --git a/common/board_f.c b/common/board_f.c
index b1d7504..59e2ba4 100644
--- a/common/board_f.c
+++ b/common/board_f.c
@@ -725,10 +725,11 @@
#endif
memcpy(gd->new_gd, (char *)gd, sizeof(gd_t));
- pr_info("Relocation Offset is: %08lx\n", gd->reloc_off);
- pr_info("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
+ printf("Relocation Offset is: %08lx\n", gd->reloc_off);
+ printf("Relocating to %08lx, new gd at %08lx, sp at %08lx\n",
gd->relocaddr, (ulong)map_to_sysmem(gd->new_gd),
gd->start_addr_sp);
+
return 0;
}
diff --git a/common/board_r.c b/common/board_r.c
index 9c26055..cbc256d 100644
--- a/common/board_r.c
+++ b/common/board_r.c
@@ -48,6 +48,7 @@
#include <linux/compiler.h>
#include <linux/err.h>
#include <efi_loader.h>
+#include <amlogic/storage.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -326,6 +327,13 @@
}
#endif
+#ifdef CONFIG_AML_STORAGE
+static int initr_storage(void)
+{
+ store_init(0);
+ return 0;
+}
+#else
#if defined(CONFIG_MTD_NOR_FLASH)
static int initr_flash(void)
{
@@ -402,11 +410,12 @@
#ifdef CONFIG_MMC
static int initr_mmc(void)
{
- puts("MMC:\n");
+ puts("MMC: \n");
mmc_initialize(gd->bd);
return 0;
}
#endif
+#endif //end of CONFIG_AML_STORAGE
/*
* Tell if it's OK to load the environment early in boot.
@@ -729,6 +738,12 @@
/* initialize higher level parts of CPU like time base and timers */
cpu_init_r,
#endif
+#ifdef CONFIG_AML_STORAGE
+ initr_storage,
+#else
+#ifdef CONFIG_PPC
+ initr_spi,
+#endif
#ifdef CONFIG_CMD_NAND
initr_nand,
#endif
@@ -738,6 +753,7 @@
#ifdef CONFIG_MMC
initr_mmc,
#endif
+#endif //end of CONFIG_AML_STORAGE
initr_env,
#ifdef CONFIG_SYS_BOOTPARAMS_LEN
initr_malloc_bootparams,
diff --git a/common/bootm.c b/common/bootm.c
index 49be3ef..85532c7 100644
--- a/common/bootm.c
+++ b/common/bootm.c
@@ -5,6 +5,8 @@
*/
#ifndef USE_HOSTCC
+#include <image-android-dt.h>
+#include <dt_table.h>
#include <common.h>
#include <bootstage.h>
#include <bzlib.h>
@@ -18,6 +20,8 @@
#include <lzma/LzmaTypes.h>
#include <lzma/LzmaDec.h>
#include <lzma/LzmaTools.h>
+#include <android_image.h>
+#include <amlogic/storage.h>
#if defined(CONFIG_CMD_USB)
#include <usb.h>
#endif
@@ -29,6 +33,10 @@
#include <bootm.h>
#include <image.h>
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+#include <ext_common.h>
+#endif
+
#ifndef CONFIG_SYS_BOOTM_LEN
/* use 8MByte as default max gunzip size */
#define CONFIG_SYS_BOOTM_LEN 0x800000
@@ -36,6 +44,10 @@
#define IH_INITRD_ARCH IH_ARCH_DEFAULT
+#ifdef CONFIG_MDUMP_COMPRESS
+#include <ramdump.h>
+#endif
+
#ifndef USE_HOSTCC
DECLARE_GLOBAL_DATA_PTR;
@@ -111,6 +123,10 @@
images.os.end = image_get_image_end(os_hdr);
images.os.load = image_get_load(os_hdr);
images.os.arch = image_get_arch(os_hdr);
+ if (images.os.arch == IH_ARCH_ARM) {
+ env_set("initrd_high", "0A000000");
+ env_set("fdt_high", "0A000000");
+ }
break;
#endif
#if IMAGE_ENABLE_FIT
@@ -181,20 +197,6 @@
ep_found = true;
break;
#endif
-#ifdef CONFIG_ZIRCON_BOOT_IMAGE
- case IMAGE_FORMAT_ZIRCON:
- images.os.type = IH_TYPE_KERNEL;
- images.os.comp = zircon_image_get_comp(os_hdr);
- images.os.os = IH_OS_ZIRCON;
-
- images.os.end = zircon_image_get_end(os_hdr);
- images.os.load = zircon_image_get_kload(os_hdr);
- if (images.os.load == 0x10008000)
- images.os.load = 0x1080000;
- images.ep = images.os.load;
- ep_found = true;
- break;
-#endif
default:
puts("ERROR: unknown image format type!\n");
return 1;
@@ -254,6 +256,232 @@
return 0;
}
+/*
+ * load dtb overlay partition to mem
+*/
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+static int read_fdto_partition(void)
+{
+ char cmd[128];
+ void *dtbo_mem_addr = NULL;
+ char dtbo_partition[32];
+ char *s1;
+ struct dt_table_header hdr;
+
+ //run_command("get_valid_slot;", 0);
+ s1 = env_get("active_slot");
+ printf("active_slot is %s\n", s1);
+ if (strcmp(s1, "normal") == 0) {
+ strcpy(dtbo_partition, "dtbo");
+ } else if (strcmp(s1, "_a") == 0) {
+ strcpy(dtbo_partition, "dtbo_a");
+ } else if (strcmp(s1, "_b") == 0) {
+ strcpy(dtbo_partition, "dtbo_b");
+ }
+
+ /*
+ * Though it is really no need to parse the dtimg infos
+ * here, but wasting time to read the whole dtbo image
+ * partition is unacceptable
+ */
+ printf("Start read %s partition datas!\n", dtbo_partition);
+ if (store_read(dtbo_partition, 0,
+ sizeof(struct dt_table_header), &hdr) < 0) {
+ printf("Fail to read header of DTBO partition\n");
+ return -1;
+ }
+
+#ifdef CONFIG_CMD_DTIMG
+ if (!android_dt_check_header((ulong)&hdr)) {
+ printf("DTBO partition header is incorrect\n");
+ return -1;
+ }
+#endif
+
+ dtbo_mem_addr = malloc(fdt32_to_cpu(hdr.total_size));
+ if (!dtbo_mem_addr) {
+ printf("out of memory\n");
+ return -1;
+ } else {
+ if (store_read(dtbo_partition, 0,
+ fdt32_to_cpu(hdr.total_size), dtbo_mem_addr) < 0) {
+ printf("Fail to read DTBO partition\n");
+ free(dtbo_mem_addr);
+ return -1;
+ }
+ else {
+ sprintf(cmd, "0x%p", dtbo_mem_addr);
+ env_set("dtbo_mem_addr",cmd);
+ }
+ }
+
+ return 0;
+}
+#endif
+
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+static int get_fdto_totalsize(u32 *tz)
+{
+#ifdef CONFIG_CMD_DTIMG
+ unsigned long long dtbo_mem_addr = 0x0;
+#endif
+ int ret;
+
+ ret = read_fdto_partition();
+ if (ret != 0)
+ return ret;
+
+#ifdef CONFIG_CMD_DTIMG
+ dtbo_mem_addr = simple_strtoul(env_get("dtbo_mem_addr"), NULL, 16);
+ *tz = android_dt_get_totalsize(dtbo_mem_addr);
+#endif
+ return 0;
+}
+#endif
+
+static void add_boot_args(const char *varname, const int varvalue)
+{
+ // Build cmdline.
+ int ret;
+ char cmdline[/* max= */ 256];
+ ret = snprintf(cmdline, sizeof(cmdline), "%s=%d", varname, varvalue);
+ if (ret < 0 || ret >= sizeof(cmdline)) {
+ puts("Error: build cmdline in add_boot_args failed!\n");
+ return;
+ }
+
+ // Add boot args.
+ char *bootargs = env_get("bootargs");
+ int newbootargs_size = bootargs
+ ? strlen(bootargs) + 1 /* space */ + strlen(cmdline) + 1 /* null */
+ : strlen(cmdline) + 1 /* null */;
+ char *newbootargs = malloc(newbootargs_size);
+ if (!newbootargs) {
+ puts("Error: malloc in add_boot_args failed!\n");
+ return;
+ }
+
+ if (bootargs) {
+ snprintf(newbootargs, newbootargs_size, "%s %s", bootargs, cmdline);
+ } else {
+ snprintf(newbootargs, newbootargs_size, "%s", cmdline);
+ }
+
+ env_set("bootargs", newbootargs);
+ free(newbootargs);
+}
+
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+static int find_dtbo_idx(const int board_id)
+{
+ unsigned long long dtbo_mem_addr = env_get_hex("dtbo_mem_addr", 0x0);
+
+ if (dtbo_mem_addr == 0x0) {
+ printf("No valid dtbo image found\n");
+ return -1;
+ }
+
+#ifdef CONFIG_CMD_DTIMG
+ if (!android_dt_check_header(dtbo_mem_addr)) {
+ printf("Error: DTBO image header is incorrect\n");
+ return -1;
+ }
+#endif
+
+ const struct dt_table_header *hdr;
+ u32 entry_count, entries_offset, entry_size;
+ u32 i;
+
+ hdr = map_sysmem(dtbo_mem_addr, sizeof(*hdr));
+ entry_count = fdt32_to_cpu(hdr->dt_entry_count);
+ entries_offset = fdt32_to_cpu(hdr->dt_entries_offset);
+ entry_size = fdt32_to_cpu(hdr->dt_entry_size);
+
+ unmap_sysmem(hdr);
+
+ printf("Read board id from dtbo...\n");
+ for (i = 0; i < entry_count; ++i) {
+ const ulong e_addr = dtbo_mem_addr + entries_offset + i * entry_size;
+ const struct dt_table_entry *entry;
+
+ entry = map_sysmem(e_addr, sizeof(*entry));
+ int dtbo_board_id = fdt32_to_cpu(entry->id);
+
+ unmap_sysmem(entry);
+
+ if (dtbo_board_id == board_id) {
+ printf("Find dtbo index %d for board id %d\n", i, board_id);
+ return i;
+ }
+ }
+ printf("Can't find dtbo index for board id %d\n", board_id);
+ return -1;
+}
+#endif
+
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+static int do_fdt_overlay(void)
+{
+ unsigned long long dtbo_mem_addr = 0x0;
+ int dtbo_num = 0;
+ int i;
+ char cmd[128];
+ unsigned long long dtbo_start;
+ char *dtbo_idx = NULL;
+ char idx[32];
+
+ if (!env_get("dtbo_mem_addr")) {
+ printf("No valid dtbo image found\n");
+ return -1;
+ }
+
+ dtbo_mem_addr = simple_strtoul(env_get("dtbo_mem_addr"), NULL, 16);
+#ifdef CONFIG_CMD_DTIMG
+ if (!android_dt_check_header(dtbo_mem_addr)) {
+ printf("Error: DTBO image header is incorrect\n");
+ return -1;
+ }
+#endif
+
+ /* android_dt_print_contents(dtbo_mem_addr); */
+ dtbo_num = fdt32_to_cpu((
+ (const struct dt_table_header *)dtbo_mem_addr)->dt_entry_count);
+ printf("find %d dtbos\n", dtbo_num);
+
+ dtbo_idx = env_get("dtbo_idx");
+ if (!dtbo_idx) {
+ printf("No dtbo_idx configured\n");
+ printf("And no dtbos will be applied\n");
+ return -1;
+ }
+ printf("dtbos to be applied: %s\n", dtbo_idx);
+
+ #ifndef CONFIG_CMD_DTIMG
+ printf("Error: No dtimg support found\n");
+ return -1;
+ #endif
+
+ for (i = 0; i < dtbo_num; i++) {
+ memset(idx, 0x00, sizeof(idx));
+ sprintf(idx, "%d", i);
+ if (strstr(dtbo_idx, idx)) {
+ printf("Apply dtbo %d\n", i);
+ sprintf(cmd, "dtimg start 0x%llx %d dtbo_start",
+ dtbo_mem_addr, i);
+ run_command(cmd, 0);
+ dtbo_start = simple_strtoul(
+ env_get("dtbo_start"), NULL, 16);
+
+ sprintf(cmd, "fdt apply 0x%llx", dtbo_start);
+ run_command(cmd, 0);
+ }
+ }
+
+ free((void *)dtbo_mem_addr);
+ return 0;
+}
+#endif
+
/**
* bootm_find_images - wrapper to find and locate various images
* @flag: Ignored Argument
@@ -273,6 +501,9 @@
int bootm_find_images(int flag, int argc, char * const argv[])
{
int ret;
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+ u32 fdto_totalsize = 0;
+#endif
/* find ramdisk */
ret = boot_get_ramdisk(argc, argv, &images, IH_INITRD_ARCH,
@@ -284,13 +515,72 @@
#if IMAGE_ENABLE_OF_LIBFDT
/* find flattened device tree */
+#ifdef CONFIG_DTB_MEM_ADDR
+ unsigned long long dtb_mem_addr = -1;
+ char *ft_addr_bak;
+ ulong ft_len_bak;
+ if (env_get("dtb_mem_addr"))
+ dtb_mem_addr = simple_strtoul(env_get("dtb_mem_addr"), NULL, 16);
+ else
+ dtb_mem_addr = CONFIG_DTB_MEM_ADDR;
+ ft_addr_bak = (char *)images.ft_addr;
+ ft_len_bak = images.ft_len;
+ images.ft_addr = (char *)map_sysmem(dtb_mem_addr, 0);
+ images.ft_len = fdt_get_header(dtb_mem_addr, totalsize);
+#endif /* CONFIG_DTB_MEM_ADDR */
+ printf("load dtb from 0x%lx ......\n", (unsigned long)(images.ft_addr));
+#ifdef CONFIG_MULTI_DTB
+ extern unsigned long get_multi_dt_entry(unsigned long fdt_addr);
+ /* update dtb address, compatible with single dtb and multi dtbs */
+ images.ft_addr = (char*)get_multi_dt_entry((unsigned long)images.ft_addr);
+#endif /* CONFIG_MULTI_DTB */
+
ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, &images,
&images.ft_addr, &images.ft_len);
+#ifdef CONFIG_DTB_MEM_ADDR
+ if (ret) {
+ images.ft_addr = ft_addr_bak;
+ images.ft_len = ft_len_bak;
+
+ printf("load dtb from 0x%lx ......\n",
+ (unsigned long)(images.ft_addr));
+#ifdef CONFIG_MULTI_DTB
+ extern unsigned long get_multi_dt_entry(unsigned long fdt_addr);
+ /* update dtb address, compatible with single dtb and multi dtbs */
+ images.ft_addr = (char*)get_multi_dt_entry((unsigned long)images.ft_addr);
+#endif /* CONFIG_MULTI_DTB */
+ ret = boot_get_fdt(flag, argc, argv, IH_ARCH_DEFAULT, &images,
+ &images.ft_addr, &images.ft_len);
+ }
+#endif /* CONFIG_DTB_MEM_ADDR */
if (ret) {
puts("Could not find a valid device tree\n");
return 1;
}
set_working_fdt_addr(map_to_sysmem(images.ft_addr));
+
+ int board_id = env_get_ulong("board_id", 10, -1);
+ if (board_id >= 0) {
+ // Add board id to sys properties.
+ add_boot_args("androidboot.board_id", board_id);
+ }
+
+#ifdef CONFIG_OF_LIBFDT_OVERLAY
+ if (get_fdto_totalsize(&fdto_totalsize) == 0)
+ fdt_set_totalsize(images.ft_addr, fdt_get_header(images.ft_addr,
+ totalsize) + fdto_totalsize);
+ images.ft_len = fdt_get_header(images.ft_addr, totalsize);
+
+ int dtbo_idx = 0; // Default.
+ int board_dtbo_idx = find_dtbo_idx(board_id);
+ if (board_dtbo_idx >= 0) {
+ dtbo_idx = board_dtbo_idx;
+ }
+
+ add_boot_args("androidboot.dtbo_idx", dtbo_idx);
+ env_set_ulong("dtbo_idx", dtbo_idx);
+ do_fdt_overlay();
+#endif
#endif
#if IMAGE_ENABLE_FIT
@@ -388,9 +678,7 @@
uint unc_len, ulong *load_end)
{
int ret = 0;
- size_t size = 0;
- const char *type_name = genimg_get_type_name(type);
*load_end = load;
print_decomp_msg(comp, type, load == image_start);
@@ -442,7 +730,8 @@
#endif /* CONFIG_LZMA */
#ifdef CONFIG_LZO
case IH_COMP_LZO: {
- size = unc_len;
+ const char *type_name = genimg_get_type_name(type);
+ size_t size = unc_len;
printf(" Uncompressing %s ... ", type_name);
ret = lzop_decompress(image_buf, image_len, load_buf, &size);
image_len = size;
@@ -451,7 +740,7 @@
#endif /* CONFIG_LZO */
#ifdef CONFIG_LZ4
case IH_COMP_LZ4: {
- size = unc_len;
+ size_t size = unc_len;
ret = ulz4fn(image_buf, image_len, load_buf, &size);
image_len = size;
@@ -514,10 +803,6 @@
blob_start, blob_end);
debug("images.os.load = 0x%lx, load_end = 0x%lx\n", load,
load_end);
- if (os.os == IH_OS_ZIRCON) {
- /* no further checking is necessary */
- return 0;
- }
#ifndef CONFIG_ANDROID_BOOT_IMAGE
/* Check what type of image this is. */
if (images->legacy_hdr_valid) {
@@ -684,6 +969,9 @@
if (!ret && (states & BOOTM_STATE_FINDOTHER))
ret = bootm_find_other(cmdtp, flag, argc, argv);
+#ifdef CONFIG_MDUMP_COMPRESS
+ check_ramdump();
+#endif
/* Load the OS */
if (!ret && (states & BOOTM_STATE_LOADOS)) {
@@ -708,26 +996,22 @@
}
}
#endif
-
- if (images->os.os != IH_OS_ZIRCON) {
-#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_LMB)
- if (!ret && (states & BOOTM_STATE_FDT)) {
- boot_fdt_add_mem_rsv_regions(&images->lmb,
- images->ft_addr);
- ret = boot_relocate_fdt(&images->lmb, &images->ft_addr,
- &images->ft_len);
- }
-#endif
-
- /* Check reserved memory region */
-#ifdef CONFIG_CMD_RSVMEM
- ret = run_command("rsvmem check", 0);
- if (ret) {
- puts("rsvmem check failed\n");
- return ret;
- }
-#endif
+#if IMAGE_ENABLE_OF_LIBFDT && defined(CONFIG_LMB)
+ if (!ret && (states & BOOTM_STATE_FDT)) {
+ boot_fdt_add_mem_rsv_regions(&images->lmb, images->ft_addr);
+ ret = boot_relocate_fdt(&images->lmb, &images->ft_addr,
+ &images->ft_len);
}
+#endif
+
+ /* Check reserved memory region */
+#ifdef CONFIG_CMD_RSVMEM
+ ret = run_command("rsvmem check", 0);
+ if (ret) {
+ puts("rsvmem check failed\n");
+ return ret;
+ }
+#endif
/* From now on, we need the OS boot function */
if (ret)
@@ -874,10 +1158,10 @@
char *avb_s;
avb_s = env_get("avb2");
- pr_info("avb2: %s\n", avb_s);
+ printf("avb2: %s\n", avb_s);
if (strcmp(avb_s, "1") != 0) {
#ifdef CONFIG_AML_ANTIROLLBACK
- struct andr_img_hdr **tmp_img_hdr = (struct andr_img_hdr **)&buf;
+ boot_img_hdr_t **tmp_img_hdr = (boot_img_hdr_t **)&buf;
#endif
}
@@ -977,15 +1261,6 @@
break;
#endif
-#ifdef CONFIG_ZIRCON_BOOT_IMAGE
- case IMAGE_FORMAT_ZIRCON:
- printf("## Booting Zircon Image at 0x%08lx ...\n", img_addr);
- buf = map_sysmem(img_addr, 0);
- if (zircon_image_get_kernel(buf, images->verify,
- os_data, os_len))
- return NULL;
- break;
-#endif
default:
printf("Wrong Image Format for %s command\n", cmdtp->name);
bootstage_error(BOOTSTAGE_ID_FIT_KERNEL_INFO);
@@ -1004,8 +1279,7 @@
memmove(to, from, len);
}
-static int bootm_host_load_image(const void *fit, int req_image_type,
- int cfg_noffset)
+static int bootm_host_load_image(const void *fit, int req_image_type)
{
const char *fit_uname_config = NULL;
ulong data, len;
@@ -1017,7 +1291,6 @@
void *load_buf;
int ret;
- fit_uname_config = fdt_get_name(fit, cfg_noffset, NULL);
memset(&images, '\0', sizeof(images));
images.verify = 1;
noffset = fit_image_load(&images, (ulong)fit,
@@ -1062,7 +1335,7 @@
for (i = 0; i < ARRAY_SIZE(image_types); i++) {
int ret;
- ret = bootm_host_load_image(fit, image_types[i], cfg_noffset);
+ ret = bootm_host_load_image(fit, image_types[i]);
if (!err && ret && ret != -ENOENT)
err = ret;
}
diff --git a/common/bootm_os.c b/common/bootm_os.c
index cad4923..28b0687 100644
--- a/common/bootm_os.c
+++ b/common/bootm_os.c
@@ -20,14 +20,18 @@
char *s;
int (*appl)(int, char *const[]);
- /* Don't start if "autostart" is set to "no" */
- s = env_get("autostart");
- if ((s != NULL) && !strcmp(s, "no")) {
- env_set_hex("filesize", images->os.image_len);
- return 0;
+ if (images->os.arch == IH_ARCH_ARM) {
+ jump_to_a32_kernel(images->ep, 0, 0);
+ } else {
+ /* Don't start if "autostart" is set to "no" */
+ s = env_get("autostart");
+ if ((s != NULL) && !strcmp(s, "no")) {
+ env_set_hex("filesize", images->os.image_len);
+ return 0;
+ }
+ appl = (int (*)(int, char * const []))images->ep;
+ appl(argc, argv);
}
- appl = (int (*)(int, char * const []))images->ep;
- appl(argc, argv);
return 0;
}
@@ -497,9 +501,6 @@
#ifdef CONFIG_BOOTM_OPTEE
[IH_OS_TEE] = do_bootm_tee,
#endif
-#ifdef CONFIG_ZIRCON_BOOT_IMAGE
- [IH_OS_ZIRCON] = do_bootm_zircon,
-#endif
};
/* Allow for arch specific config before we boot */
diff --git a/common/cli.c b/common/cli.c
index d0b9826..51b8d5f 100644
--- a/common/cli.c
+++ b/common/cli.c
@@ -211,7 +211,6 @@
}
#endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
-#ifdef CONFIG_CLI_ENABLED
void cli_loop(void)
{
#ifdef CONFIG_HUSH_PARSER
@@ -224,7 +223,6 @@
printf("## U-Boot command line is disabled. Please enable CONFIG_CMDLINE\n");
#endif /*CONFIG_HUSH_PARSER*/
}
-#endif /* CONFIG_CLI_ENABLED */
void cli_init(void)
{
diff --git a/common/cmd_leds_state.c b/common/cmd_leds_state.c
new file mode 100644
index 0000000..0288126
--- /dev/null
+++ b/common/cmd_leds_state.c
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <config.h>
+#include <command.h>
+#include <asm/arch/mailbox.h>
+#include "amlogic/leds_state.h"
+
+int32_t do_leds_state(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ uint32_t data[12];
+ uint32_t rev_data, i, ret;
+
+ if (argc < 2)
+ return CMD_RET_USAGE;
+ for (i = 1; i < argc; i++)
+ data[i-1] = (u32)simple_strtoul(argv[i], NULL, 10);
+ ret = scpi_send_data(AOCPU_REE_CHANNEL, 0xF7, data, 4*(argc-1), &rev_data, 0);
+ if (ret != 0) {
+ printf("communication failed\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+#define BLINK ""
+
+U_BOOT_CMD(
+ leds_state, 12, 1, do_leds_state,
+ "manage amlogic LEDs",
+ "<led_label> on|off|toggle" BLINK "\tChange LED state\n"
+ "led [<led_label>\tGet LED state\n"
+ "led list\t\tshow a list of LEDs\n"
+);
diff --git a/common/cmd_sha2.c b/common/cmd_sha2.c
new file mode 100644
index 0000000..ac99d64
--- /dev/null
+++ b/common/cmd_sha2.c
@@ -0,0 +1,282 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+/*
+ * Functions in this file implement Amlogic SHA2 function
+ *
+ * Author : zhongfu.luo@amlogic.com
+ *
+ * Feature: implement uboot command for SHA2 common usage
+ * command : sha2 addr_in len [addr_out]
+ * addr_in[IN] : DDR address for input buffer
+ * len[IN] : total data size to be processed for SHA2
+ * addr_out[OUT]: user defined output buffer for the SHA2 (if not set then the SHA2 of input will shown only but not stored)
+ *
+ * History: 1. 2017.06.01 function init
+ *
+ *
+*/
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/regs.h>
+#include <u-boot/sha256.h>
+#include <asm/arch-c1/timer.h>
+
+#define DATA_MAX_LEN (1 << 31) //max length of SHA2 is 2 GB
+
+static int do_sha2(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+ int nReturn=CMD_RET_USAGE;
+ ulong addr_in,nLength,addr_out = 0;
+ unsigned char szSHA2[32];
+ unsigned char *pSHA2 = szSHA2;
+ int nSHA2Type = 256;
+ char *endp;
+ int i = 0;
+ unsigned int ntime1,ntime2,ntime;
+
+ /* need at least three arguments */
+ if (argc < 3)
+ goto exit;
+
+ nReturn = __LINE__;
+
+ if ( 0 == *argv[1] )
+ {
+ printf("[addr_in] format error! \n" );
+ goto exit;
+ }
+ addr_in = simple_strtoul(argv[1], &endp, 16);
+ if ( 0 != *endp )
+ {
+ printf("[addr_in] format error! \n" );
+ goto exit;
+ }
+ nReturn = __LINE__;
+
+ if ( 0 == *argv[2])
+ {
+ printf("[Length] format error! \n" );
+ goto exit;
+ }
+ nLength = simple_strtoul(argv[2], &endp, 16);
+ if ( 0 != *endp )
+ {
+ printf("[Length] format error! \n" );
+ goto exit;
+ }
+ if ( !nLength || nLength > DATA_MAX_LEN)
+ {
+ printf("Length range: 0x00000001 ~ 0x%08x Byte! \n", DATA_MAX_LEN );
+ goto exit;
+ }
+
+ nReturn = __LINE__;
+
+
+ if (argc > 3)
+ {
+ if ( 0 == *argv[3] )
+ {
+ printf("[addr_out] format error! \n" );
+ goto exit;
+ }
+ addr_out = simple_strtoul(argv[3], &endp, 16);
+ if ( 0 != *endp )
+ {
+ printf("[addr_out] format error! \n" );
+ goto exit;
+ }
+ pSHA2=(unsigned char *)addr_out;
+ }
+
+ ntime1 = get_time();
+ sha256_csum_wd((unsigned char *)addr_in,(unsigned int)nLength,pSHA2,0);
+ ntime2 = get_time();
+ ntime = ntime2 - ntime1;
+ printf("\n cost time: %d us, bandwidth: %d M/s",ntime, (unsigned int)((float)nLength/1024/ntime*1000000/1024));
+
+ if (argc > 3)
+ printf("\nSHA%d of addr_in: 0x%08x, len: 0x%08x, addr_out: 0x%08x \n", nSHA2Type, (unsigned int)addr_in, (unsigned int)nLength,(unsigned int)addr_out);
+ else
+ printf("\nSHA%d of addr_in: 0x%08x, len: 0x%08x \n", nSHA2Type, (unsigned int)addr_in, (unsigned int)nLength);
+
+
+ for (i=0; i<SHA256_SUM_LEN; i++)
+ printf("%02x%s", pSHA2[i], ((i+1) % 16==0) ? "\n" :" ");
+
+ nReturn = 0;
+
+exit:
+
+ return nReturn;
+}
+
+
+#undef DATA_MAX_LEN
+
+U_BOOT_CMD(
+ sha2, 4, 1, do_sha2,
+ "SHA2 command",
+ "addr_in len [addr_out] \n"
+);
+
+
+
+/*
+ * Feature: implement uboot command for test SHA2 common usage
+ * command : sha2test [writeval] [len]
+ * writeval[IN] : the value of data for test(default is 0x01)
+ * len[IN] : total data size to be processed for SHA2 (default is 128k bytes)
+ *
+ * History: 1. 2017.06.01 function init
+ *
+ *
+*/
+
+//#define CONFIG_AML_SHA2_TEST
+#if defined(CONFIG_AML_SHA2_TEST)
+
+#define writel(val,reg) (*((volatile unsigned *)(reg)))=(val)
+#define readl(reg) (*((volatile unsigned *)(reg)))
+#define TEST_MAX_LEN (10<<20)
+#define TEST_MIN_LEN (64)
+
+static int do_sha2test(cmd_tbl_t *cmdtp, int flag, int argc,
+ char * const argv[])
+{
+
+ int nReturn = __LINE__;
+ unsigned char *pBuffer = 0;
+
+ int i;
+ int nLength = TEST_MAX_LEN;
+ unsigned int byPattern = 1;
+ char *endp;
+ int nSHA2Type = 256;
+ unsigned int ntime1,ntime2,ntime;
+ unsigned char szSHA2[32];
+ int testLength[8]={TEST_MAX_LEN,1024*1024,100*1024,10*1024,1024,512,128,TEST_MIN_LEN};
+ int c=0;
+
+ #ifdef CONFIG_AML_HW_SHA2
+ printf("aml log : Amlogic HW SHA2 \n");
+ #else
+ printf("aml log : Software SHA2 \n");
+ #endif
+
+
+ //pattern
+ if (argc > 1)
+ {
+ if ( 0 == *argv[1] )
+ {
+ printf("[writeval] format error! \n" );
+ goto exit;
+ }
+ byPattern = simple_strtoul(argv[1], &endp, 16);
+ if ( 0 != *endp )
+ {
+ printf("[writeval] format error! \n" );
+ goto exit;
+ }
+ if ( byPattern > 0xff)
+ {
+ printf("writeval range: 0x00 ~ 0xff! \n" );
+ goto exit;
+ }
+
+ }
+
+ nReturn = __LINE__;
+
+ //length
+ if (argc > 2)
+ {
+ if ( 0== *argv[2] )
+ {
+ printf("[Length] format error! \n" );
+ goto exit;
+ }
+ nLength = simple_strtoul(argv[2], &endp, 16);
+ if ( 0 != *endp )
+ {
+ printf("[Length] format error! \n" );
+ goto exit;
+ }
+
+ if ( !nLength || nLength > TEST_MAX_LEN)
+ {
+ printf("Length range: 0x00000001 ~ 0x%08x Byte! \n", TEST_MAX_LEN );
+ goto exit;
+ }
+ }
+
+ nReturn = __LINE__;
+
+ pBuffer=(unsigned char*)malloc(nLength);
+
+ if (!pBuffer)
+ {
+ printf("malloc fail! \n" );
+ goto exit;
+ }
+
+ //set buffer with dedicated pattern
+ memset(pBuffer,byPattern,nLength);
+
+
+ do
+ {
+ ntime1=readl(P_ISA_TIMERE);
+
+ sha256_csum_wd(pBuffer,nLength,szSHA2,0);
+
+ ntime2=readl(P_ISA_TIMERE);
+
+ ntime = ntime2 - ntime1;
+
+ printf("\nSHA%d of value: 0x%02x, len: 0x%08x, time used: %d us, bandwidth: %d kB/s \n",\
+ nSHA2Type, (unsigned int)byPattern, nLength,ntime, (unsigned int)((float)nLength/1024/ntime*1000000));
+
+ //SHA2 dump
+ for (i=0; i<SHA256_SUM_LEN; i++)
+ printf("%02x%s", szSHA2[i], ((i+1) % 16==0) ? "\n" :" ");
+
+ if (argc > 2)
+ break;
+
+ nLength =testLength[++c];
+ }
+ while (nLength > TEST_MIN_LEN) ;
+
+ nReturn = 0;
+
+exit:
+
+ if (pBuffer)
+ {
+ free(pBuffer);
+ pBuffer = 0;
+ }
+
+ return nReturn;
+
+}
+
+#undef writel
+#undef readl
+#undef TEST_MAX_LEN
+#undef TEST_MIN_LEN
+
+U_BOOT_CMD(
+ sha2test, 3, 1, do_sha2test,
+ "test SHA2 fuction",
+ "[writeval] [len] \n"
+);
+
+#endif //#if defined(CONFIG_AML_SHA2_TEST)
diff --git a/common/image-android-dt.c b/common/image-android-dt.c
index c0683ee..d174413 100644
--- a/common/image-android-dt.c
+++ b/common/image-android-dt.c
@@ -28,6 +28,18 @@
return magic == DT_TABLE_MAGIC;
}
+u32 android_dt_get_totalsize(ulong hdr_addr)
+{
+ const struct dt_table_header *hdr;
+ u32 totalsize;
+
+ hdr = map_sysmem(hdr_addr, sizeof(*hdr));
+ totalsize = fdt32_to_cpu(hdr->total_size);
+ unmap_sysmem(hdr);
+
+ return totalsize;
+}
+
/**
* Get the address of FDT (dtb or dtbo) in memory by its index in image.
*
diff --git a/common/image-android.c b/common/image-android.c
index 45c341f..c569651 100644
--- a/common/image-android.c
+++ b/common/image-android.c
@@ -8,65 +8,44 @@
#include <android_image.h>
#include <malloc.h>
#include <errno.h>
-#define KDTB_MAGIC "KDTB"
-#define KDTB_MAGIC_SZ (sizeof(KDTB_MAGIC) - 1)
-
-// The Kernel is packed along with its dtb file
-// The format is [header][kernel][dtb file]
-// This is the header
-typedef struct __attribute__((__packed__)) KDTB_HEADER {
- char magic[KDTB_MAGIC_SZ];
- uint32_t kernel_size;
- uint32_t dtb_size;
-} KDTB_HEADER;
-
-typedef struct KDTB_PARSED {
- unsigned char *kernel_addr;
- uint32_t kernel_size;
- unsigned char *dtb_addr;
- uint32_t dtb_size;
-} KDTB_PARSED;
-
-static int parse_kern_dtb(unsigned char *kern_dtb, unsigned kern_dtb_size,
- KDTB_PARSED *parsed) {
- KDTB_HEADER header;
- memcpy(&header, kern_dtb, sizeof(header));
- if (memcmp(KDTB_MAGIC, header.magic, KDTB_MAGIC_SZ) != 0) {
- return ANDR_BOOT_KDTB_NOT_FOUND;
- }
-
- unsigned expected_kernel_size =
- header.kernel_size + header.dtb_size + sizeof(header);
- if (expected_kernel_size != kern_dtb_size) {
- printf("the expected kern-dtb size is: %u\n", expected_kernel_size);
- printf("the actual kern-dtb size is: %u\n", kern_dtb_size);
- // For now, don't error out on this condition. Seems the
- // hdr->kernel_size value is not used in current code, so there is no
- // way to assert this.
- }
- parsed->kernel_addr = kern_dtb + sizeof(header);
- if ((uintptr_t)parsed->kernel_addr & 0x3) {
- printf("Kernel must be 4 byte aligned\n");
- return ANDR_BOOT_KDTB_INVALID;
- }
- parsed->kernel_size = header.kernel_size;
- parsed->dtb_addr = parsed->kernel_addr + header.kernel_size;
- parsed->dtb_size = header.dtb_size;
-
- return 0;
-}
static const unsigned char lzop_magic[] = {
0x89, 0x4c, 0x5a, 0x4f, 0x00, 0x0d, 0x0a, 0x1a, 0x0a
};
#define ANDROID_IMAGE_DEFAULT_KERNEL_ADDR 0x10008000
+
+#define ANDROIDR_IMAGE_KERNEL_DECOMPRESS_LOAD_ADDR 0x1080000
+
static const unsigned char gzip_magic[] = {
0x1f, 0x8b
};
static char andr_tmp_str[ANDR_BOOT_ARGS_SIZE + 1];
-static ulong android_image_get_kernel_addr(const struct andr_img_hdr *hdr)
+static struct {
+ const unsigned char * szID;
+ int nIDLength;
+ ulong nCompID;
+} arrComp[] = {
+ {lzop_magic,9,IH_COMP_LZO},
+ {gzip_magic,2,IH_COMP_GZIP},
+};
+
+/* android R*/
+static int android_image_get_kernel_v3(const boot_img_hdr_v3_t *hdr, int verify, ulong *os_data, ulong *os_len);
+static int android_image_need_move_v3(ulong *img_addr,const boot_img_hdr_v3_t *hdr);
+static ulong android_image_get_kload_v3(const boot_img_hdr_v3_t *hdr);
+static ulong android_image_get_comp_v3(const boot_img_hdr_v3_t *hdr);
+static ulong android_image_get_end_v3(const boot_img_hdr_v3_t *hdr);
+
+int is_android_r_image(void *img_addr)
+{
+ /* check android version for R/S/etc */
+ p_boot_img_hdr_v3_t pHDR = (p_boot_img_hdr_v3_t)(img_addr);
+ return ((pHDR->header_version >= 3) ? 1 : 0);
+}
+
+static ulong android_image_get_kernel_addr(const boot_img_hdr_t *hdr)
{
/*
* All the Android tools that generate a boot.img use this
@@ -100,9 +79,12 @@
* Return: Zero, os start address and length on success,
* otherwise on failure.
*/
-int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
+int android_image_get_kernel(const boot_img_hdr_t *hdr, int verify,
ulong *os_data, ulong *os_len)
{
+ if (is_android_r_image((void*)hdr))
+ return android_image_get_kernel_v3((void*)hdr,verify,os_data,os_len);
+
u32 kernel_addr = android_image_get_kernel_addr(hdr);
/*
@@ -110,7 +92,6 @@
* sha1 (or anything) so we don't check it. It is not obvious that the
* string is null terminated so we take care of this.
*/
- ulong end;
strncpy(andr_tmp_str, hdr->name, ANDR_BOOT_NAME_SIZE);
andr_tmp_str[ANDR_BOOT_NAME_SIZE] = '\0';
if (strlen(andr_tmp_str))
@@ -145,40 +126,15 @@
env_set("bootargs", newbootargs);
- // Kernel or kernel-dtb file exists at this location.
- void *kernel = (unsigned char *)hdr + hdr->page_size;
-
- KDTB_PARSED parsed = {0};
- int ret = parse_kern_dtb(kernel, hdr->kernel_size, &parsed);
-
- if (ret == ANDR_BOOT_KDTB_INVALID)
- return ret;
-
- if (ret == 0) {
- // kernel-dtb file found.
- printf("found kdtb.\n");
- if (os_data) {
- *os_data = (ulong)parsed.kernel_addr;
- }
- if (os_len)
- *os_len = parsed.kernel_size;
- images.ft_len = parsed.dtb_size;
- images.ft_addr = (char *)parsed.dtb_addr;
-
- end = (ulong)hdr;
- end += hdr->page_size;
- end += ALIGN(hdr->kernel_size, hdr->page_size);
- images.rd_start = end;
- return 0;
- }
if (os_data) {
- *os_data = (ulong)kernel;
+ *os_data = (ulong)hdr;
+ *os_data += hdr->page_size;
}
if (os_len)
*os_len = hdr->kernel_size;
#if defined(CONFIG_ANDROID_BOOT_IMAGE)
- //ulong end;
+ ulong end;
images.ft_len = (ulong)(hdr->second_size);
end = (ulong)hdr;
end += hdr->page_size;
@@ -191,13 +147,21 @@
return 0;
}
-int android_image_check_header(const struct andr_img_hdr *hdr)
+int android_image_check_header(const boot_img_hdr_t *hdr)
{
return memcmp(ANDR_BOOT_MAGIC, hdr->magic, ANDR_BOOT_MAGIC_SIZE);
}
-ulong android_image_get_end(const struct andr_img_hdr *hdr)
+int vendor_boot_image_check_header(const vendor_boot_img_hdr_t * hdr)
{
+ return memcmp(VENDOR_BOOT_MAGIC, hdr->magic, VENDOR_BOOT_MAGIC_SIZE);
+}
+
+ulong android_image_get_end(const boot_img_hdr_t *hdr)
+{
+ if (is_android_r_image((void*)hdr))
+ return android_image_get_end_v3((void*)hdr);
+
ulong end;
/*
* The header takes a full page, the remaining components are aligned
@@ -212,14 +176,20 @@
return end;
}
-ulong android_image_get_kload(const struct andr_img_hdr *hdr)
+ulong android_image_get_kload(const boot_img_hdr_t *hdr)
{
- return android_image_get_kernel_addr(hdr);
+ if (is_android_r_image((void*)hdr))
+ return android_image_get_kload_v3((void*)hdr);
+ else
+ return android_image_get_kernel_addr(hdr);
}
-int android_image_get_ramdisk(const struct andr_img_hdr *hdr,
+int android_image_get_ramdisk(const boot_img_hdr_t *hdr,
ulong *rd_data, ulong *rd_len)
{
+ if (is_android_r_image((void*)hdr))
+ return android_image_get_ramdisk_v3((void*)hdr,rd_data,rd_len);
+
if (!hdr->ramdisk_size) {
*rd_data = *rd_len = 0;
return -1;
@@ -236,9 +206,12 @@
return 0;
}
-int android_image_get_second(const struct andr_img_hdr *hdr,
+int android_image_get_second(const boot_img_hdr_t *hdr,
ulong *second_data, ulong *second_len)
{
+ if (is_android_r_image((void*)hdr))
+ return 0;
+
if (!hdr->second_size) {
*second_data = *second_len = 0;
return -1;
@@ -267,7 +240,7 @@
* returns:
* no returned results
*/
-void android_print_contents(const struct andr_img_hdr *hdr)
+void android_print_contents(const boot_img_hdr_t *hdr)
{
const char * const p = IMAGE_INDENT_STRING;
/* os_version = ver << 11 | lvl */
@@ -293,37 +266,26 @@
}
#endif
-ulong android_image_get_comp(const struct andr_img_hdr *os_hdr)
+ulong android_image_get_comp(const boot_img_hdr_t *os_hdr)
{
+ if (is_android_r_image((void*)os_hdr))
+ return android_image_get_comp_v3((void*)os_hdr);
+
int i;
unsigned char *src = (unsigned char *)os_hdr + os_hdr->page_size;
-
- KDTB_PARSED parsed = {0};
- if (parse_kern_dtb(src, os_hdr->kernel_size, &parsed) == 0) {
- src = parsed.kernel_addr;
+ for (i = 0;i< ARRAY_SIZE(arrComp);++i)
+ {
+ if (!memcmp(arrComp[i].szID,src,arrComp[i].nIDLength))
+ return arrComp[i].nCompID;
}
- unsigned char *begin = src;
-
- /* read magic: 9 first bytes */
- for (i = 0; i < ARRAY_SIZE(lzop_magic); i++) {
- if (*src++ != lzop_magic[i])
- break;
- }
- if (i == ARRAY_SIZE(lzop_magic))
- return IH_COMP_LZO;
-
- src = begin;
- for (i = 0; i < ARRAY_SIZE(gzip_magic); i++) {
- if (*src++ != gzip_magic[i])
- break;
- }
- if (i == ARRAY_SIZE(gzip_magic))
- return IH_COMP_GZIP;
return IH_COMP_NONE;
}
-int android_image_need_move(ulong *img_addr, const struct andr_img_hdr *hdr)
+int android_image_need_move(ulong *img_addr, const boot_img_hdr_t *hdr)
{
+ if (is_android_r_image((void*)hdr))
+ return android_image_need_move_v3(img_addr,(void*)hdr);
+
ulong kernel_load_addr = android_image_get_kload(hdr);
ulong img_start = *img_addr;
ulong val = 0;
@@ -344,7 +306,218 @@
memset(reloc_addr, 0, total_size);
memmove(reloc_addr, hdr, total_size);
*img_addr = (ulong)reloc_addr;
- pr_info("copy done\n");
+ printf("copy done\n");
+ }
+ return 0;
+}
+
+/*Android R boot func*/
+/* definition of vendor_boot partition structure */
+p_vendor_boot_img_t p_vender_boot_img = 0;
+static int android_image_get_kernel_v3(const boot_img_hdr_v3_t *hdr, int verify,
+ ulong *os_data, ulong *os_len)
+{
+ /*
+ * Not all Android tools use the id field for signing the image with
+ * sha1 (or anything) so we don't check it. It is not obvious that the
+ * string is null terminated so we take care of this.
+ */
+ /*check vendor boot image first*/
+ if (!p_vender_boot_img)
+ {
+ if (os_data)
+ *os_data = 0;
+ if (os_len)
+ *os_len = 0;
+ goto exit;
+ }
+
+ p_vendor_boot_img_hdr_t vb_hdr = &p_vender_boot_img->hdr;
+ char boot_name[ANDR_BOOT_NAME_SIZE + 8];
+ memset(boot_name,0,sizeof(boot_name));
+ strncpy(boot_name, (char *)vb_hdr->name, ANDR_BOOT_NAME_SIZE);
+ if (strlen(boot_name))
+ printf("Android's image name: %s\n", boot_name);
+
+ //debug("Kernel load addr 0x%08x size %u KiB\n",
+ // hdr_v3->kernel_addr, DIV_ROUND_UP(hdr->kernel_size, 1024));
+
+ int len = 0;
+#if defined(CONFIG_ANDROID_IMG)
+ ulong end;
+ ulong dtb_size = vb_hdr->dtb_size;
+ ulong dtb_addr = vb_hdr->dtb_addr;
+#endif
+
+ if (*vb_hdr->cmdline) {
+ printf("Kernel command line: %s\n", vb_hdr->cmdline);
+ len += strlen(vb_hdr->cmdline);
+ }
+
+ char *pbootargs = env_get("bootargs");
+ if (pbootargs) {
+ int nlen = strlen(pbootargs) + len + 2;
+ char *pnewbootargs = malloc(nlen);
+ if (pnewbootargs) {
+ memset((void *)pnewbootargs,0,nlen);
+ sprintf(pnewbootargs,"%s %s",pbootargs,vb_hdr->cmdline);
+ env_set("bootargs",pnewbootargs);
+ free(pnewbootargs);
+ pnewbootargs = NULL;
+ }
+ else {
+ puts("Error: malloc in pnewbootargs failed!\n");
+ }
+ }
+ else {
+ puts("Error: add kernel command line in bootargs failed!\n");
+ }
+
+ if (os_data) {
+ *os_data = (ulong)hdr;
+ *os_data += 0x1000; //android R header size
+ }
+ if (os_len)
+ *os_len = hdr->kernel_size;
+
+#if defined(CONFIG_ANDROID_IMG)
+ images.ft_len = dtb_size;
+ end = dtb_addr;
+ images.ft_addr = (char *)end;
+#endif
+
+exit:
+
+ return 0;
+}
+
+
+void aml_u8_printf(void *pBuffer, int nSize)
+{
+ printf("aml log : dump buffer from addr=0x%x\n",(unsigned int)(unsigned long)pBuffer);
+
+ unsigned char *pData = (unsigned char *)pBuffer;
+ int nIndex = 0;
+
+ for (nIndex = 0; nIndex < nSize;++nIndex)
+ {
+ printf("%02x%s",pData[nIndex],
+ (nIndex + 1)%16 ? " ":"\n");
+ }
+
+ printf("\n");
+}
+
+static ulong android_image_get_end_v3(const boot_img_hdr_v3_t *hdr)
+{
+ if (!p_vender_boot_img)
+ return 0;
+
+ /*??*/
+ ulong end;
+ /*
+ * The header takes a full page, the remaining components are aligned
+ * on page boundary
+ */
+
+ end = (ulong)hdr;
+ end += 0x1000;
+ end += ALIGN(hdr->kernel_size, 0x1000);
+ end += ALIGN(hdr->ramdisk_size, 0x1000);
+ return end;
+}
+
+static ulong android_image_get_kload_v3(const boot_img_hdr_v3_t *hdr)
+{
+ if (p_vender_boot_img)
+ return ANDROIDR_IMAGE_KERNEL_DECOMPRESS_LOAD_ADDR;
+ else
+ return 0;
+}
+
+int android_image_get_ramdisk_v3(const boot_img_hdr_v3_t *hdr,
+ ulong *rd_data, ulong *rd_len)
+{
+ /*boot image must contain ramdisk*/
+ if (!hdr->ramdisk_size ||!p_vender_boot_img)
+ {
+ if (rd_data)
+ *rd_data = 0;
+ if (rd_len)
+ *rd_len = 0;
+ return -1;
+ }
+
+ p_vendor_boot_img_hdr_t vb_hdr = &p_vender_boot_img->hdr;
+#ifdef CONFIG_RAMDISK_MEM_ADDR
+ vb_hdr->ramdisk_addr = CONFIG_RAMDISK_MEM_ADDR;
+#endif
+
+ debug("RAM disk load addr 0x%08x size %u KiB\n",
+ vb_hdr->ramdisk_addr, DIV_ROUND_UP(hdr->ramdisk_size, 1024));
+
+ /*ramdisk offset of android R boot image*/
+ int nOffset = (DIV_ROUND_UP(hdr->kernel_size,4096)+1)*4096;
+
+ unsigned char *pRAMdisk = (unsigned char *)(unsigned long)vb_hdr->ramdisk_addr;
+
+ /* copy ramdisk to ramdisk_addr */
+ memmove(pRAMdisk, (char*)(unsigned long)(simple_strtoul(env_get("loadaddr"), NULL, 16) + nOffset),hdr->ramdisk_size);
+ memmove(pRAMdisk + hdr->ramdisk_size, p_vender_boot_img->szData,vb_hdr->vendor_ramdisk_size);
+
+ if (rd_data)
+ *rd_data = vb_hdr->ramdisk_addr;
+
+ if (rd_len)
+ *rd_len = hdr->ramdisk_size + vb_hdr->vendor_ramdisk_size;
+
+ return 0;
+}
+
+static ulong android_image_get_comp_v3(const boot_img_hdr_v3_t *os_hdr)
+{
+ int i;
+ unsigned char *src = (unsigned char *)os_hdr + 0x1000;
+
+ for (i = 0;i< ARRAY_SIZE(arrComp);++i)
+ {
+ if (!memcmp(arrComp[i].szID,src,arrComp[i].nIDLength))
+ return arrComp[i].nCompID;
+ }
+
+ return IH_COMP_NONE;
+}
+
+static int android_image_need_move_v3(ulong *img_addr, const boot_img_hdr_v3_t *hdr)
+{
+ /*
+ Gzip format boot.img need relocate to high address.In order to quickly boot,so change load
+ decompress kernel address,when imgread load kernel at 0x3080000 and load decompress kernel
+ address is 0x1080000 needless to relocate,margin calculation is 32M.
+ */
+ ulong kernel_load_addr = android_image_get_kload_v3(hdr);
+ ulong img_start = *img_addr;
+ ulong val = 0;
+ if (kernel_load_addr > img_start)
+ val = kernel_load_addr - img_start;
+ else
+ val = img_start - kernel_load_addr;
+
+ if (android_image_get_comp_v3(hdr) == IH_COMP_NONE)
+ return 0;
+
+ if (val < 32*1024*1024) {
+ ulong total_size = android_image_get_end_v3(hdr)-(ulong)hdr;
+ void *reloc_addr = malloc(total_size);
+ if (!reloc_addr) {
+ puts("Error: malloc in android_image_need_move failed!\n");
+ return -ENOMEM;
+ }
+ printf("reloc_addr =%lx\n", (ulong)reloc_addr);
+ memset(reloc_addr, 0, total_size);
+ memmove(reloc_addr, hdr, total_size);
+ *img_addr = (ulong)reloc_addr;
+ printf("Copy done\n");
}
return 0;
}
diff --git a/common/image-fdt.c b/common/image-fdt.c
index d5468e9..aaf0f22 100644
--- a/common/image-fdt.c
+++ b/common/image-fdt.c
@@ -241,24 +241,22 @@
#endif
const char *select = NULL;
int ok_no_fdt = 0;
-#ifndef CONFIG_ANDROID_BOOT_IMAGE
+
*of_flat_tree = NULL;
*of_size = 0;
-#endif
+
if (argc > 2)
select = argv[2];
- /* find flattened device tree */
- #ifdef CONFIG_DTB_MEM_ADDR
+
if (!select) {
if (env_get("dtb_mem_addr")) {
- select = simple_strtoul(env_get("dtb_mem_addr"), NULL, 16);
- printf("env select addr: 0x%x\n", select);
+ select = env_get("dtb_mem_addr");
+ printf("env select addr: 0x%s\n", select);
}
else {
- select = 0x01000000;
+ select = "0x01000000";
}
}
- #endif
if (select || genimg_has_config(images)) {
#if CONFIG_IS_ENABLED(FIT)
@@ -287,7 +285,7 @@
} else
#endif
{
- fdt_addr = select; //simple_strtoul(select, NULL, 16);
+ fdt_addr = simple_strtoul(select, NULL, 16);
debug("* fdt: cmdline image address = 0x%08lx\n",
fdt_addr);
}
@@ -365,7 +363,7 @@
*/
#if CONFIG_IS_ENABLED(FIT)
/* check FDT blob vs FIT blob */
- if (!fit_check_format(buf, IMAGE_SIZE_INVAL)) {
+ if (fit_check_format(buf)) {
ulong load, len;
fdt_noffset = boot_get_fdt_fit(images,
@@ -419,39 +417,20 @@
fdt_error("image is not a fdt");
goto error;
}
- /*
+
if (fdt_totalsize(fdt_blob) != fdt_len) {
fdt_error("fdt size != image size");
goto error;
}
- */
} else {
debug("## No Flattened Device Tree\n");
goto no_fdt;
}
} else {
- #if defined(CONFIG_ANDROID_BOOT_IMAGE)
- if (images->ft_len) {
- fdt_blob = (char *)images->ft_addr;
-
- if (fdt_check_header(fdt_blob) != 0) {
- fdt_error("image is not a fdt");
- goto error;
- }
- /*
- if (fdt_totalsize(fdt_blob) != images->ft_len) {
- fdt_error("fdt size != image size");
- goto error;
- }*/
- } else {
- printf("## No Flattened Device Tree\n");
- goto error;
- }
- #else
debug("## No Flattened Device Tree\n");
goto no_fdt;
- #endif
}
+
*of_flat_tree = fdt_blob;
*of_size = fdt_totalsize(fdt_blob);
debug(" of_flat_tree at 0x%08lx size 0x%08lx\n",
diff --git a/common/image-fit.c b/common/image-fit.c
index 7377171..95b5723 100644
--- a/common/image-fit.c
+++ b/common/image-fit.c
@@ -8,14 +8,12 @@
* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
*/
-#define LOG_CATEGORY LOGC_BOOT
-
#ifdef USE_HOSTCC
#include "mkimage.h"
#include <time.h>
-#include <linux/libfdt.h>
#else
#include <linux/compiler.h>
+#include <linux/kconfig.h>
#include <common.h>
#include <errno.h>
#include <mapmem.h>
@@ -26,7 +24,6 @@
#include <image.h>
#include <bootstage.h>
-#include <linux/kconfig.h>
#include <u-boot/crc.h>
#include <u-boot/md5.h>
#include <u-boot/sha1.h>
@@ -169,7 +166,7 @@
int value_len;
char *algo;
const char *padding;
- bool required;
+ int required;
int ret, i;
debug("%s %s node: '%s'\n", p, type,
@@ -180,8 +177,8 @@
return;
}
printf("%s", algo);
- keyname = fdt_getprop(fit, noffset, FIT_KEY_HINT, NULL);
- required = fdt_getprop(fit, noffset, FIT_KEY_REQUIRED, NULL) != (void *)NULL;
+ keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL);
+ required = fdt_getprop(fit, noffset, "required", NULL) != NULL;
if (keyname)
printf(":%s", keyname);
if (required)
@@ -987,8 +984,10 @@
if (external_data) {
debug("External Data\n");
ret = fit_image_get_data_size(fit, noffset, &len);
- *data = fit + offset;
- *size = len;
+ if (!ret) {
+ *data = fit + offset;
+ *size = len;
+ }
} else {
ret = fit_image_get_data(fit, noffset, data, size);
}
@@ -1288,31 +1287,21 @@
*/
int fit_image_verify(const void *fit, int image_noffset)
{
- const char *name = fit_get_name(fit, image_noffset, NULL);
const void *data;
size_t size;
+ int noffset = 0;
char *err_msg = "";
- if (strchr(name, '@')) {
- /*
- * We don't support this since libfdt considers names with the
- * name root but different @ suffix to be equal
- */
- err_msg = "Node name contains @";
- goto err;
- }
/* Get image data and data length */
if (fit_image_get_data_and_size(fit, image_noffset, &data, &size)) {
err_msg = "Can't get image data/size";
- goto err;
+ printf("error!\n%s for '%s' hash node in '%s' image node\n",
+ err_msg, fit_get_name(fit, noffset, NULL),
+ fit_get_name(fit, image_noffset, NULL));
+ return 0;
}
return fit_image_verify_with_data(fit, image_noffset, data, size);
-
-err:
- printf("error!\n%s in '%s' image node\n", err_msg,
- fit_get_name(fit, image_noffset, NULL));
- return 0;
}
/**
@@ -1463,100 +1452,42 @@
}
/**
- * fdt_check_no_at() - Check for nodes whose names contain '@'
+ * fit_check_format - sanity check FIT image format
+ * @fit: pointer to the FIT format image header
*
- * This checks the parent node and all subnodes recursively
+ * fit_check_format() runs a basic sanity FIT image verification.
+ * Routine checks for mandatory properties, nodes, etc.
*
- * @fit: FIT to check
- * @parent: Parent node to check
- * @return 0 if OK, -EADDRNOTAVAIL is a node has a name containing '@'
+ * returns:
+ * 1, on success
+ * 0, on failure
*/
-static int fdt_check_no_at(const void *fit, int parent)
+int fit_check_format(const void *fit)
{
- const char *name;
- int node;
- int ret;
-
- name = fdt_get_name(fit, parent, NULL);
- if (!name || strchr(name, '@'))
- return -EADDRNOTAVAIL;
-
- fdt_for_each_subnode(node, fit, parent) {
- ret = fdt_check_no_at(fit, node);
- if (ret)
- return ret;
- }
-
- return 0;
-}
-
-int fit_check_format(const void *fit, ulong size)
-{
- int ret;
-
- /* A FIT image must be a valid FDT */
- ret = fdt_check_header(fit);
- if (ret) {
- log_debug("Wrong FIT format: not a flattened device tree (err=%d)\n",
- ret);
- return -ENOEXEC;
- }
-
- if (CONFIG_IS_ENABLED(FIT_FULL_CHECK)) {
- /*
- * If we are not given the size, make do with calculating it.
- * This is not as secure, so we should consider a flag to
- * control this.
- */
- if (size == IMAGE_SIZE_INVAL)
- size = fdt_totalsize(fit);
- ret = fdt_check_full(fit, size);
- if (ret)
- ret = -EINVAL;
-
- /*
- * U-Boot stopped using unit addressed in 2017. Since libfdt
- * can match nodes ignoring any unit address, signature
- * verification can see the wrong node if one is inserted with
- * the same name as a valid node but with a unit address
- * attached. Protect against this by disallowing unit addresses.
- */
- if (!ret && CONFIG_IS_ENABLED(FIT_SIGNATURE)) {
- ret = fdt_check_no_at(fit, 0);
-
- if (ret) {
- log_debug("FIT check error %d\n", ret);
- return ret;
- }
- }
- if (ret) {
- log_debug("FIT check error %d\n", ret);
- return ret;
- }
- }
/* mandatory / node 'description' property */
- if (!fdt_getprop(fit, 0, FIT_DESC_PROP, NULL)) {
- log_debug("Wrong FIT format: no description\n");
- return -ENOMSG;
+ if (fdt_getprop(fit, 0, FIT_DESC_PROP, NULL) == NULL) {
+ debug("Wrong FIT format: no description\n");
+ return 0;
}
if (IMAGE_ENABLE_TIMESTAMP) {
/* mandatory / node 'timestamp' property */
- if (!fdt_getprop(fit, 0, FIT_TIMESTAMP_PROP, NULL)) {
- log_debug("Wrong FIT format: no timestamp\n");
- return -ENODATA;
+ if (fdt_getprop(fit, 0, FIT_TIMESTAMP_PROP, NULL) == NULL) {
+ debug("Wrong FIT format: no timestamp\n");
+ return 0;
}
}
/* mandatory subimages parent '/images' node */
if (fdt_path_offset(fit, FIT_IMAGES_PATH) < 0) {
- log_debug("Wrong FIT format: no images parent node\n");
- return -ENOENT;
+ debug("Wrong FIT format: no images parent node\n");
+ return 0;
}
- return 0;
+ return 1;
}
+
/**
* fit_conf_find_compat
* @fit: pointer to the FIT format image header
@@ -1885,13 +1816,10 @@
printf("## Loading %s from FIT Image at %08lx ...\n", prop_name, addr);
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_FORMAT);
- ret = fit_check_format(fit, IMAGE_SIZE_INVAL);
- if (ret) {
- printf("Bad FIT %s image format! (err=%d)\n", prop_name, ret);
- if (CONFIG_IS_ENABLED(FIT_SIGNATURE) && ret == -EADDRNOTAVAIL)
- printf("Signature checking prevents use of unit addresses (@) in nodes\n");
+ if (!fit_check_format(fit)) {
+ printf("Bad FIT %s image format!\n", prop_name);
bootstage_error(bootstage_id + BOOTSTAGE_SUB_FORMAT);
- return ret;
+ return -ENOEXEC;
}
bootstage_mark(bootstage_id + BOOTSTAGE_SUB_FORMAT_OK);
if (fit_uname) {
@@ -1942,7 +1870,7 @@
fit_uname = fit_get_name(fit, noffset, NULL);
}
if (noffset < 0) {
- printf("Could not find subimage node type '%s'\n", prop_name);
+ puts("Could not find subimage node\n");
bootstage_error(bootstage_id + BOOTSTAGE_SUB_SUBNODE);
return -ENOENT;
}
diff --git a/common/image-sig.c b/common/image-sig.c
index b757641..4f6b4ec 100644
--- a/common/image-sig.c
+++ b/common/image-sig.c
@@ -200,7 +200,7 @@
padding_name = RSA_DEFAULT_PADDING_NAME;
memset(info, '\0', sizeof(*info));
- info->keyname = fdt_getprop(fit, noffset, FIT_KEY_HINT, NULL);
+ info->keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL);
info->fit = (void *)fit;
info->node_offset = noffset;
info->name = algo_name;
@@ -311,7 +311,7 @@
const char *required;
int ret;
- required = fdt_getprop(sig_blob, noffset, FIT_KEY_REQUIRED, NULL);
+ required = fdt_getprop(sig_blob, noffset, "required", NULL);
if (!required || strcmp(required, "image"))
continue;
ret = fit_image_verify_sig(fit, image_noffset, data, size,
@@ -330,39 +330,20 @@
return 0;
}
-/**
- * fit_config_check_sig() - Check the signature of a config
- *
- * @fit: FIT to check
- * @noffset: Offset of configuration node (e.g. /configurations/conf-1)
- * @required_keynode: Offset in the control FDT of the required key node,
- * if any. If this is given, then the configuration wil not
- * pass verification unless that key is used. If this is
- * -1 then any signature will do.
- * @conf_noffset: Offset of the configuration subnode being checked (e.g.
- * /configurations/conf-1/kernel)
- * @err_msgp: In the event of an error, this will be pointed to a
- * help error string to display to the user.
- * @return 0 if all verified ok, <0 on error
- */
-static int fit_config_check_sig(const void *fit, int noffset,
- int required_keynode, int conf_noffset,
- char **err_msgp)
+int fit_config_check_sig(const void *fit, int noffset, int required_keynode,
+ char **err_msgp)
{
char * const exc_prop[] = {"data"};
const char *prop, *end, *name;
struct image_sign_info info;
const uint32_t *strings;
- const char *config_name;
uint8_t *fit_value;
int fit_value_len;
- bool found_config;
int max_regions;
int i, prop_len;
char path[200];
int count;
- config_name = fit_get_name(fit, conf_noffset, NULL);
debug("%s: fdt=%p, conf='%s', sig='%s'\n", __func__, gd_fdt_blob(),
fit_get_name(fit, noffset, NULL),
fit_get_name(gd_fdt_blob(), required_keynode, NULL));
@@ -403,20 +384,9 @@
char *node_inc[count];
debug("Hash nodes (%d):\n", count);
- found_config = false;
for (name = prop, i = 0; name < end; name += strlen(name) + 1, i++) {
debug(" '%s'\n", name);
node_inc[i] = (char *)name;
- if (!strncmp(FIT_CONFS_PATH, name, strlen(FIT_CONFS_PATH)) &&
- name[sizeof(FIT_CONFS_PATH) - 1] == '/' &&
- !strcmp(name + sizeof(FIT_CONFS_PATH), config_name)) {
- debug(" (found config node %s)", config_name);
- found_config = true;
- }
- }
- if (!found_config) {
- *err_msgp = "Selected config not in hashed nodes";
- return -1;
}
/*
@@ -484,7 +454,7 @@
if (!strncmp(name, FIT_SIG_NODENAME,
strlen(FIT_SIG_NODENAME))) {
ret = fit_config_check_sig(fit, noffset, sig_offset,
- conf_noffset, &err_msg);
+ &err_msg);
if (ret) {
puts("- ");
} else {
@@ -500,14 +470,13 @@
goto error;
}
- if (verified)
- return 0;
+ return verified ? 0 : -EPERM;
error:
printf(" error!\n%s for '%s' hash node in '%s' config node\n",
err_msg, fit_get_name(fit, noffset, NULL),
fit_get_name(fit, conf_noffset, NULL));
- return -EPERM;
+ return -1;
}
int fit_config_verify_required_sigs(const void *fit, int conf_noffset,
@@ -528,7 +497,7 @@
const char *required;
int ret;
- required = fdt_getprop(sig_blob, noffset, FIT_KEY_REQUIRED, NULL);
+ required = fdt_getprop(sig_blob, noffset, "required", NULL);
if (!required || strcmp(required, "conf"))
continue;
ret = fit_config_verify_sig(fit, conf_noffset, sig_blob,
diff --git a/common/image-zircon.c b/common/image-zircon.c
deleted file mode 100644
index 5a5442a..0000000
--- a/common/image-zircon.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (c) 2018 The Fuchsia Authors
- *
- * SPDX-License-Identifier: GPL-2.0+
- */
-
-#include <common.h>
-#include <image.h>
-#include <zircon/image.h>
-
-void zircon_append_boot_item(zbi_header_t *container, u32 type,
- u32 extra, const void *payload,
- u32 length)
-{
- zbi_header_t *dest = (zbi_header_t *)((uintptr_t)container +
- container->length + sizeof(zbi_header_t));
-
- dest->type = type;
- dest->length = length;
- dest->extra = extra;
- dest->flags = ZBI_FLAG_VERSION;
- dest->reserved0 = 0;
- dest->reserved1 = 0;
- dest->magic = ZBI_ITEM_MAGIC;
- dest->crc32 = ZBI_ITEM_NO_CRC32;
-
- if (length) {
- memcpy(dest + 1, payload, length);
- }
- length = ZBI_ALIGN(length + sizeof(zbi_header_t));
- container->length += length;
-}
-
-int zircon_image_check_header(const void *hdr)
-{
- const zbi_header_t *zbi = hdr;
-
- return (zbi[0].type == ZBI_TYPE_CONTAINER &&
- zbi[0].extra == ZBI_CONTAINER_MAGIC &&
- zbi[0].magic == ZBI_ITEM_MAGIC &&
- zbi[1].type == ZBI_TYPE_KERNEL_ARM64 &&
- zbi[1].magic == ZBI_ITEM_MAGIC) ? 0 : -1;
-}
-
-/*
- * zircon_image_get_kernel() - processes kernel part of Zircon bootdata
- * @bootdata: Pointer to bootdata.
- * @verify: Checksum verification flag. Currently unimplemented.
- * @os_data: Pointer to a ulong variable, will hold os data start
- * address.
- * @os_len: Pointer to a ulong variable, will hold os data length.
- *
- * This function returns the os image's start address and length. Also,
- * it appends the kernel command line to the bootargs env variable.
- *
- * Return: Zero, os start address and length on success,
- * otherwise on failure.
- */
-int zircon_image_get_kernel(const void *hdr, int verify,
- ulong *os_data, ulong *os_len)
-{
- if (zircon_image_check_header(hdr))
- return -1;
-
- const zbi_header_t *zbi = hdr;
-
- *os_data = (ulong)zbi;
- *os_len = zbi->length + sizeof(*zbi);
- return 0;
-}
-
-ulong zircon_image_get_end(const void *hdr)
-{
- const zbi_header_t *zbi = hdr;
-
- return (ulong)hdr + zbi->length + sizeof(*zbi);
-}
-
-ulong zircon_image_get_kload(const void *hdr)
-{
- return 0x1080000;
-}
-
-ulong zircon_image_get_comp(const void *hdr)
-{
- return IH_COMP_NONE;
-}
diff --git a/common/image.c b/common/image.c
index 3e04afc..4c9c4d9 100644
--- a/common/image.c
+++ b/common/image.c
@@ -214,11 +214,18 @@
int image_check_dcrc(const image_header_t *hdr)
{
+
+#ifdef CONFIG_PXP_EMULATOR
+ puts("PXP skip CRC...");
+ return 1;
+#else
ulong data = image_get_data(hdr);
ulong len = image_get_data_size(hdr);
ulong dcrc = crc32_wd(0, (unsigned char *)data, len, CHUNKSZ_CRC32);
return (dcrc == image_get_dcrc(hdr));
+#endif
+
}
/**
@@ -882,10 +889,6 @@
if (android_image_check_header(img_addr) == 0)
return IMAGE_FORMAT_ANDROID;
#endif
-#ifdef CONFIG_ZIRCON_BOOT_IMAGE
- if (zircon_image_check_header(img_addr) == 0)
- return IMAGE_FORMAT_ZIRCON;
-#endif
return IMAGE_FORMAT_INVALID;
}
diff --git a/common/main.c b/common/main.c
index 261d56c..4b265d1 100644
--- a/common/main.c
+++ b/common/main.c
@@ -44,6 +44,11 @@
bootstage_mark_name(BOOTSTAGE_ID_MAIN_LOOP, "main_loop");
+#ifdef CONFIG_MDUMP_COMPRESS
+ extern void ramdump_init(void);
+ ramdump_init();
+#endif
+
if (IS_ENABLED(CONFIG_VERSION_VARIABLE))
env_set("ver", version_string); /* set version variable */
@@ -60,8 +65,6 @@
autoboot_command(s);
-#if defined(CONFIG_CLI_ENABLED)
cli_loop();
-#endif /* CONFIG_CLI_ENABLED */
panic("No CLI available");
}
diff --git a/common/partitions.c b/common/partitions.c
index 500cf07..57e8d4a 100644
--- a/common/partitions.c
+++ b/common/partitions.c
@@ -1,3 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include <common.h>
#include <malloc.h>
#include <linux/err.h>
@@ -5,21 +10,33 @@
#include <linux/libfdt.h>
#include <asm/arch/bl31_apis.h>
#include <amlogic/aml_efuse.h>
+#include <part_efi.h>
+#include <blk.h>
+#include <compiler.h>
+#include <mmc.h>
+#include <emmc_partitions.h>
#ifdef CONFIG_MULTI_DTB
extern unsigned long get_multi_dt_entry(unsigned long fdt_addr);
#endif
+#define GPT_SPACE 0X2000
+
struct partitions_data{
int nr;
struct partitions *parts;
};
struct partitions *part_table = NULL;
-static int parts_total_num;
+int parts_total_num;
int has_boot_slot = 0;
int has_system_slot = 0;
-
+bool dynamic_partition = false;
+bool vendor_boot_partition = false;
+bool is_partition_checked = false;
+#if CONFIG_IS_ENABLED(EFI_PARTITION)
+bool gpt_partition;
+#endif
int get_partitions_table(struct partitions **table)
{
@@ -39,8 +56,6 @@
return part_table;
}
-
-
void free_partitions(void)
{
if (part_table)
@@ -48,6 +63,9 @@
part_table = NULL;
}
+#ifndef IS_FEAT_BOOT_VERIFY
+#define IS_FEAT_BOOT_VERIFY() 0
+#endif// #ifndef IS_FEAT_BOOT_VERIFY
/*
return 0 if dts is valid
@@ -77,7 +95,7 @@
#else
dt_addr = (char *)buffer;
#endif
- printf("start dts,buffer=%p,dt_addr=%p\n", buffer, dt_addr);
+ pr_debug("start dts,buffer=%p,dt_addr=%p\n", buffer, dt_addr);
ret = fdt_check_header(dt_addr);
if ( ret < 0 )
printf("%s: %s\n",__func__,fdt_strerror(ret));
@@ -85,6 +103,90 @@
return ret;
}
+#if CONFIG_IS_ENABLED(EFI_PARTITION)
+int parse_gpt(struct blk_desc *dev_desc, void *buf)
+{
+ gpt_header *gpt_h;
+ gpt_entry *gpt_e;
+ size_t efiname_len, dosname_len;
+ int parts_num = 0;
+ int i, k;
+
+ /* determine start of GPT Header in the buffer */
+ gpt_h = buf + (GPT_PRIMARY_PARTITION_TABLE_LBA *
+ dev_desc->blksz);
+
+ /* determine start of GPT Entries in the buffer */
+ gpt_e = buf + (le64_to_cpu(gpt_h->partition_entry_lba) *
+ dev_desc->blksz);
+
+ parts_num = le32_to_cpu(gpt_h->num_partition_entries);
+ if (parts_num > 0) {
+ part_table = (struct partitions *)
+ malloc(sizeof(struct partitions) * parts_num);
+ if (!part_table) {
+ printf("%s part_table alloc _err\n", __func__);
+ return -1;
+ }
+ memset(part_table, 0, sizeof(struct partitions) * parts_num);
+ parts_total_num = parts_num;
+ }
+
+ dynamic_partition = false;
+ env_set("partition_mode", "normal");
+ vendor_boot_partition = false;
+ env_set("vendor_boot_mode", "false");
+
+ for (i = 0; i < parts_num; i++) {
+ if (!is_pte_valid(&gpt_e[i])) {
+ free(part_table);
+ return -1;
+ }
+
+ part_table[i].offset = le64_to_cpu(gpt_e[i].starting_lba << 9ULL);
+ part_table[i].size = ((le64_to_cpu(gpt_e[i].ending_lba) + 1) -
+ le64_to_cpu(gpt_e[i].starting_lba)) << 9ULL;
+ /* mask flag */
+ part_table[i].mask_flags =
+ (uint32_t)le64_to_cpu(gpt_e[i].attributes.fields.type_guid_specific);
+ /* partition name */
+ efiname_len = sizeof(gpt_e[i].partition_name) / sizeof(efi_char16_t);
+ dosname_len = sizeof(part_table[i].name);
+
+ memset(part_table[i].name, 0, sizeof(part_table[i].name));
+ for (k = 0; k < min(dosname_len, efiname_len); k++)
+ part_table[i].name[k] = (char)gpt_e[i].partition_name[k];
+
+ if (strcmp(part_table[i].name, "boot_a") == 0) {
+ has_boot_slot = 1;
+ printf("set has_boot_slot = 1\n");
+ } else if (strcmp(part_table[i].name, "boot") == 0) {
+ has_boot_slot = 0;
+ printf("set has_boot_slot = 0\n");
+ }
+
+ if (strcmp(part_table[i].name, "system_a") == 0)
+ has_system_slot = 1;
+ else if (strcmp(part_table[i].name, "system") == 0)
+ has_system_slot = 0;
+
+ if (strcmp(part_table[i].name, "super") == 0) {
+ dynamic_partition = true;
+ env_set("partition_mode", "dynamic");
+ printf("enable dynamic_partition\n");
+ }
+
+ if (strncmp(part_table[i].name, "vendor_boot", 11) == 0) {
+ vendor_boot_partition = true;
+ env_set("vendor_boot_mode", "true");
+ printf("enable vendor_boot\n");
+ }
+ }
+ is_partition_checked = false;
+ return 0;
+}
+#endif
+
int get_partition_from_dts(unsigned char *buffer)
{
char *dt_addr;
@@ -97,9 +199,36 @@
const char *umask;
int index;
int ret = -1;
+#if CONFIG_IS_ENABLED(EFI_PARTITION)
+ struct blk_desc *dev_desc;
- if ( buffer == NULL)
+ if (!buffer)
goto _err;
+
+ dev_desc = (struct blk_desc *)malloc(sizeof(struct blk_desc));
+ if (!dev_desc)
+ goto _err;
+
+ dev_desc->blksz = MMC_BLOCK_SIZE;
+ dev_desc->lba = GPT_SPACE;
+
+ if (!is_valid_gpt_buf(dev_desc, buffer)) {
+ if (!parse_gpt(dev_desc, buffer)) {
+ gpt_partition = true;
+ free(dev_desc);
+ return 0;
+ }
+ }
+ free(dev_desc);
+#endif
+
+ ret = check_valid_dts(buffer);
+ printf("%s() %d: ret %d\n",__func__, __LINE__, ret);
+ if ( ret < 0 )
+ {
+ printf("%s() %d: ret %d\n",__func__, __LINE__, ret);
+ goto _err;
+ }
#ifdef CONFIG_MULTI_DTB
dt_addr = (char *)get_multi_dt_entry((unsigned long)buffer);
#else
@@ -119,13 +248,16 @@
{
part_table = (struct partitions *)malloc(sizeof(struct partitions)*(be32_to_cpup((u32*)parts_num)));
if (!part_table) {
- printk("%s part_table alloc _err\n",__func__);
- //kfree(data);
+ printf("%s part_table alloc _err\n", __func__);
return -1;
}
memset(part_table, 0, sizeof(struct partitions)*(be32_to_cpup((u32*)parts_num)));
parts_total_num = be32_to_cpup((u32*)parts_num);
}
+ dynamic_partition = false;
+ env_set("partiton_mode","normal");
+ vendor_boot_partition = false;
+ env_set("vendor_boot_mode","false");
for (index = 0; index < be32_to_cpup((u32*)parts_num); index++)
{
sprintf(propname,"part-%d", index);
@@ -168,7 +300,21 @@
has_system_slot = 1;
else if (strcmp(uname, "system") == 0)
has_system_slot = 0;
+
+ if (strcmp(uname, "super") == 0) {
+ dynamic_partition = true;
+ env_set("partiton_mode","dynamic");
+ printf("enable dynamic_partition\n");
+ }
+
+ if (strncmp(uname, "vendor_boot", 11) == 0) {
+ vendor_boot_partition = true;
+ env_set("vendor_boot_mode","true");
+ printf("enable vendor_boot\n");
+ }
}
+ /*enable mmc_device_init when dtb is update from ddr*/
+ is_partition_checked = false;
return 0;
_err:
diff --git a/common/ramdump.c b/common/ramdump.c
new file mode 100644
index 0000000..e105311
--- /dev/null
+++ b/common/ramdump.c
@@ -0,0 +1,149 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/bl31_apis.h>
+#include <asm/arch/secure_apb.h>
+#include <ramdump.h>
+#include <emmc_partitions.h>
+
+#define DEBUG_RAMDUMP 0
+#define AMLOGIC_KERNEL_PANIC 0x0c
+#define AMLOGIC_WATCHDOG_REBOOT 0x0d
+
+
+unsigned long ramdump_base = 0;
+unsigned long ramdump_size = 0;
+unsigned int get_reboot_mode(void)
+{
+ uint32_t reboot_mode_val = ((readl(AO_SEC_SD_CFG15) >> 12) & 0xf);
+ return reboot_mode_val;
+}
+
+void ramdump_init(void)
+{
+ unsigned int data;
+
+ ramdump_base = readl(P_AO_SEC_GP_CFG12);
+ ramdump_size = readl(P_AO_SEC_GP_CFG13);
+
+ data = readl(PREG_STICKY_REG8);
+ writel(data & ~RAMDUMP_STICKY_DATA_MASK, PREG_STICKY_REG8);
+ printf("%s, add:%lx, size:%lx\n", __func__, ramdump_base, ramdump_size);
+}
+
+/*
+ * NOTE: this is a default impemention for writing compressed ramdump data
+ * to /data/ partition for Android platform. You can read out dumpfile in
+ * path /data/crashdump-1.bin when enter Android for crash analyze.
+ * by default, /data/ partion for android is EXT4 fs.
+ *
+ * TODO:
+ * If you are using different fs or OS on your platform, implement compress
+ * data save command for your fs and OS in your board.c with same function
+ * name "ramdump_save_compress_data".
+ */
+__weak int ramdump_save_compress_data(void)
+{
+ int data_pid;
+ char cmd[128] = {0};
+
+ data_pid = get_partition_num_by_name("data");
+ if (data_pid < 0) {
+ printf("can't find data partition\n");
+ return -1;
+ }
+ sprintf(cmd, "ext4write mmc 1:%x %lx /crashdump-1.bin %lx\n",
+ data_pid, ramdump_base, ramdump_size);
+ printf("CMD:%s\n", cmd);
+ run_command(cmd, 1);
+ return 0;
+}
+
+static void ramdump_env_setup(unsigned long addr, unsigned long size)
+{
+ unsigned int data[10] = {
+ 0x8E9C929F, 0x9E9C9791,
+ 0xD28C9191, 0x97949B8D,
+ 0x888B92, 0xCEBB97,
+ 0x938E9B90, 0x978D8D97,
+ 0xC8009B8A, 0xB99CDB
+ };
+ char *line, *p1, *p2, *o;
+ unsigned char *p;
+ int i;
+
+ p = (unsigned char *)data;
+ for (i = 0; i < 40; i++)
+ p[i] = ~(p[i] - 1);
+
+ /*
+ * TODO: Make sure address for fdt_high and initrd_high
+ * are suitable for all boards
+ *
+ * usually kernel load address is 0x010800000
+ * Make sure:
+ * (kernel image size + ramdisk size) <
+ * (initrd_high - 0x010800000)
+ * dts file size < (fdt_high - initrd_high)
+ */
+ env_set("initrd_high", "0x04400000");
+ env_set("fdt_high", "0x04E00000");
+ line = env_get("bootargs");
+ if (!line)
+ return;
+
+ i = strlen(line);
+ o = malloc(i + 128);
+ if (!o)
+ return;
+
+ memset(o, 0, i + 128);
+ memcpy(o, line, i);
+ line = o + i + 128;
+ p1 = strstr(o, (const char *)p);
+ if (p1) {
+ p2 = strchr(p1, ' ');
+ if (!p2)
+ p2 = p1;
+ memmove(p1, p2, line - p2);
+ }
+ i = strlen(o);
+ p1 = o + i;
+ p1[0] = ' ';
+ sprintf(p1 + 1, "%s=%s ramdump=%lx,%lx",
+ (char *)data, (char *)(data + 6), addr, size);
+ env_set("bootargs", o);
+
+#if DEBUG_RAMDUMP
+ run_command("printenv bootargs", 1);
+#endif
+ free(o);
+}
+
+void check_ramdump(void)
+{
+ unsigned long size = 0;
+ unsigned long addr = 0;
+ char *env;
+ int reboot_mode;
+
+ env = env_get("ramdump_enable");
+ if (env) {
+ printf("%s,%s\n", __func__, env);
+ if (!strcmp(env, "1")) {
+ reboot_mode = get_reboot_mode();
+ if ((reboot_mode == AMLOGIC_WATCHDOG_REBOOT ||
+ reboot_mode == AMLOGIC_KERNEL_PANIC)) {
+ addr = ramdump_base;
+ size = ramdump_size;
+ printf("%s, addr:%lx, size:%lx\n",
+ __func__, addr, size);
+ if (addr && size)
+ ramdump_env_setup(addr, size);
+ }
+ }
+ }
+}
diff --git a/common/spl/Kconfig b/common/spl/Kconfig
index c4580cd..37ecbc6 100644
--- a/common/spl/Kconfig
+++ b/common/spl/Kconfig
@@ -1106,4 +1106,3 @@
endif # SPL
endmenu
-
diff --git a/common/splash_source.c b/common/splash_source.c
index 9467def..62763b9 100644
--- a/common/splash_source.c
+++ b/common/splash_source.c
@@ -329,10 +329,10 @@
if (res < 0)
return res;
- res = fit_check_format(fit_header, IMAGE_SIZE_INVAL);
- if (res) {
+ res = fit_check_format(fit_header);
+ if (!res) {
debug("Could not find valid FIT image\n");
- return res;
+ return -EINVAL;
}
node_offset = fit_image_get_node(fit_header, location->name);
diff --git a/common/update.c b/common/update.c
index 42950ed..f237ea5 100644
--- a/common/update.c
+++ b/common/update.c
@@ -280,7 +280,7 @@
got_update_file:
fit = (void *)addr;
- if (fit_check_format((void *)fit, IMAGE_SIZE_INVAL)) {
+ if (!fit_check_format((void *)fit)) {
printf("Bad FIT format of the update file, aborting "
"auto-update\n");
return 1;
diff --git a/common/usb.c b/common/usb.c
index 23eda6b..17fd486 100644
--- a/common/usb.c
+++ b/common/usb.c
@@ -1036,7 +1036,7 @@
int retry_count = 0;
unsigned short portstatus;
-
+ retry:
/*
* Allocate usb 3.0 device context.
* USB 3.0 (xHCI) protocol tries to allocate device slot
@@ -1052,7 +1052,6 @@
if (err)
return err;
- retry:
err = usb_root_port_reset(dev, parent);
if (err)
@@ -1061,11 +1060,6 @@
dev->devnum = addr;
err = usb_set_address(dev); /* set address */
- if (err < 0) {
- printf("\n 1 USB device not accepting new address " \
- "(error=%lX), port= %d\n", dev->status, parent->portnr);
- err = usb_set_address(dev); /* set address */
- }
if (err < 0) {
err = usb_hub_port_reset(parent, dev->portnr -1, &portstatus);
@@ -1083,11 +1077,11 @@
err = usb_set_address(dev); /* set address */
}
if (err < 0) {
- printf("\n 2 USB device not accepting new address " \
+ debug("\n 2 USB device not accepting new address " \
"(error=%lX)\n", dev->status);
if (retry_count == 0) {
retry_count++;
- printf("retry new usb device\n");
+ debug("retry new usb device\n");
goto retry;
}
return err;
diff --git a/common/usb_hub.c b/common/usb_hub.c
index 24f3085..58af132 100644
--- a/common/usb_hub.c
+++ b/common/usb_hub.c
@@ -271,7 +271,7 @@
int err, tries;
ALLOC_CACHE_ALIGN_BUFFER(struct usb_port_status, portsts, 1);
unsigned short portstatus, portchange;
- int delay = HUB_SHORT_RESET_TIME; /* start with short reset delay */
+ int delay = HUB_LONG_RESET_TIME; /* start with short reset delay */
#if CONFIG_IS_ENABLED(DM_USB)
debug("%s: resetting '%s' port %d...\n", __func__, dev->dev->name,
@@ -397,11 +397,13 @@
}
#ifdef CONFIG_USB_DEVICE_V2
+#if CONFIG_IS_ENABLED(DM_USB)
if (usb_hub_is_root_hub(dev->dev)) {
usb_tuning_port(dev, port);
mdelay(10);
}
#endif
+#endif
#if CONFIG_IS_ENABLED(DM_USB)
struct udevice *child;
diff --git a/configs/g12a_u200_v1_defconfig b/configs/g12a_u200_v1_defconfig
deleted file mode 100644
index 1bb5ffe..0000000
--- a/configs/g12a_u200_v1_defconfig
+++ /dev/null
@@ -1,178 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MESON=y
-CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_MESON_G12A=y
-CONFIG_TARGET_G12A_U200_V1=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_AML_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_MMC_MESON_GX=y
-# CONFIG_AML_GPIO=y
-CONFIG_SYS_PROMPT="g12a_u200_v1# "
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-s905d2-u200"
-CONFIG_BOOTCOMMAND="run storeboot"
-CONFIG_BOOTDELAY=1
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_CPU_CLK=1200
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SPI=y
-CONFIG_CMD_SARADC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ADC=y
-CONFIG_SARADC_MESON=y
-CONFIG_CLK=y
-CONFIG_CLK_MESON=y
-CONFIG_CLK_MESON_G12=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_MESON_G12A=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
-CONFIG_PWM_MESON=y
-CONFIG_ADC_POWER_KEY_CHAN=2
-CONFIG_ADC_POWER_KEY_VAL=0
-CONFIG_WDT=y
-CONFIG_WDT_MESON=y
-CONFIG_CMD_WATCHDOG=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MESON=y
-CONFIG_CMD_I2C=y
-# CONFIG_AML_BL33_COMPRESS_ENABLE=1
-CONFIG_AML_CRYPTO_UBOOT=1
-CONFIG_AML_CUSTOMER_ID=0
-CONFIG_AML_DRIVER=y
-CONFIG_AML_MEDIA=y
-CONFIG_AML_VPU=y
-CONFIG_AML_VPP=y
-CONFIG_AML_CANVAS=y
-CONFIG_AML_OSD=y
-CONFIG_CMD_BMP=y
-CONFIG_AML_VOUT=y
-CONFIG_AML_CVBS=y
-CONFIG_AML_HDMITX=y
-CONFIG_AML_LCD=y
-CONFIG_AML_LCD_TV=y
-CONFIG_AML_LCD_TABLET=y
-CONFIG_AML_LCD_EXTERN=y
-CONFIG_AML_BL_EXTERN=y
-CONFIG_NEED_BL301=y
-CONFIG_NEED_BL32=y
-CONFIG_CMD_RSVMEM=y
-CONFIG_FIP_IMG_SUPPORT=y
-CONFIG_SYS_LONGHELP=y
-CONFIG_CMD_MISC=y
-CONFIG_CMD_ITEST=y
-CONFIG_CMD_CPU_TEMP=1
-CONFIG_CMD_LOADB=y
-# CONFIG_AML_MESON=1
-# CONFIG_AML_MESON_G12A=1
-# CONFIG_AML_MESON_GX=1
-CONFIG_MESON_NFC=y
-CONFIG_AML_SECURE_BOOT_V3=1
-CONFIG_AML_SECURE_UBOOT=1
-CONFIG_AML_SECURITY_KEY=1
-CONFIG_BL2_COPY_NUM=4
-CONFIG_BOOTLOADER_CONTROL_BLOCK=y
-CONFIG_CMD_BOOTCTOL_AVB=y
-CONFIG_BT_WAKEUP=y
-CONFIG_CEC_OSD_NAME="AML_TV"
-CONFIG_CEC_WAKEUP=y
-CONFIG_CMD_SARADC=1
-CONFIG_CMD_VIU_PROBE=1
-CONFIG_CPU_CLK=1200
-CONFIG_DDR4_TIMING_TEST=0
-CONFIG_DDR_FULL_TEST=0
-CONFIG_DDR_LOW_POWER=0
-CONFIG_DDR_PLL_BYPASS=0
-# CONFIG_DDR_SIZE=0
-CONFIG_DDR_USE_EXT_VREF=0
-CONFIG_DDR_ZQ_PD=0
-CONFIG_DISCRETE_BOOTLOADER=y
-CONFIG_DTB_MEM_ADDR=0x1000000
-CONFIG_EFUSE=y
-CONFIG_MDUMP_COMPRESS=1
-# CONFIG_PLATFORM_POWER_INIT=y
-CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN=1
-CONFIG_RANDOM_ETHADDR=1
-CONFIG_SARADC_CH=2
-CONFIG_SD_BURNING_SUPPORT_UI=1
-CONFIG_STORE_COMPATIBLE=1
-CONFIG_SYS_HUSH_PARSER=y
-CONFIG_SYS_NO_FLASH=1
-CONFIG_TPL_COPY_NUM=4
-CONFIG_TPL_PART_NAME="tpl"
-CONFIG_TPL_SIZE_PER_COPY=0x200000
-CONFIG_TXLX_USB=1
-CONFIG_USB_DEVICE_V2=1
-CONFIG_USB=y
-CONFIG_CMD_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_FASTBOOT=y
-CONFIG_CMD_FASTBOOT=y
-CONFIG_FASTBOOT_DWC_PCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DUALSPEED=y
-CONFIG_AML_V2_FACTORY_BURN=y
-CONFIG_USB_BURNING_TOOL=y
-CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
-CONFIG_SD_BURNING_SUPPORT_UI=y
-CONFIG_UNIFY_KEY_MANAGE=y
-CONFIG_SECURE_STORAGE=y
-CONFIG_VCCK_INIT_VOLTAGE=800
-# CONFIG_VDDEE_INIT_VOLTAGE=800
-# CONFIG_VDDEE_SLEEP_VOLTAGE=731
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_MESON=y
-CONFIG_DEBUG_UART_BASE=0xff803000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
-CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_CMD_D2PLL=n
-CONFIG_CMD_DDRTEST=n
-#CONFIG_AML_NAND=y
-CONFIG_DM_MTD=y
-CONFIG_MTD_UBI=y
-#CONFIG_MTD=y
-CONFIG_NAND=y
-CONFIG_MTD_DEVICE=y
-CONFIG_AML_MTD=y
-CONFIG_CMD_MTDPARTS=y
-#CONFIG_AML_MTDPART=y
-CONFIG_AML_STORAGE=y
-CONFIG_AML_PARTITION=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_DM=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_AML_SPICC=y
-CONFIG_PHY=y
-CONFIG_DM_USB=y
-CONFIG_AML_USB2_PHY=y
-CONFIG_AML_USB3_PHY=y
-CONFIG_AML_USB=y
-CONFIG_DM_ETH=y
-#CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_CMD_SF=y
-CONFIG_AML_SPIFC=y
-CONFIG_SPI_FLASH_WINBOND=y
-#CONFIG_SPI_FLASH_MTD=y
-CONFIG_SPI_NAND=y
-CONFIG_AML_TSENSOR=y
-CONFIG_AML_TSENSOR_COOL=y
-CONFIG_CMD_EFUSE=y
-#CONFIG_CMD_DDR_D2PLL=y
-#CONFIG_CMD_DDR_TEST=y
-CONFIG_AML_OSCRING=y
diff --git a/configs/g12b_newman_bx_defconfig b/configs/g12b_newman_bx_defconfig
deleted file mode 100644
index 0584188..0000000
--- a/configs/g12b_newman_bx_defconfig
+++ /dev/null
@@ -1,201 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MESON=y
-CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_MESON_G12B=y
-CONFIG_TARGET_G12B_NEWMAN_BX=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_AML_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_MMC_MESON_GX=y
-# CONFIG_AML_GPIO=y
-CONFIG_SYS_PROMPT="g12b_newman_bx# "
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-t931-newman"
-CONFIG_BOOTCOMMAND="run storeboot"
-CONFIG_BOOTDELAY=-2
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_CPU_CLK=1200
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SPI=n
-CONFIG_CMD_SARADC=n
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ADC=y
-CONFIG_SARADC_MESON=y
-CONFIG_CLK=y
-CONFIG_CLK_MESON=y
-CONFIG_CLK_MESON_G12=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_MESON_G12A=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
-CONFIG_PWM_MESON=y
-CONFIG_ADC_POWER_KEY_CHAN=2
-CONFIG_ADC_POWER_KEY_VAL=0
-CONFIG_WDT=y
-CONFIG_WDT_MESON=y
-CONFIG_CMD_WATCHDOG=n
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MESON=y
-CONFIG_CMD_I2C=n
-# CONFIG_AML_BL33_COMPRESS_ENABLE=1
-CONFIG_AML_CRYPTO_UBOOT=y
-CONFIG_AML_CUSTOMER_ID=0
-CONFIG_AML_DRIVER=y
-CONFIG_AML_MEDIA=y
-CONFIG_AML_VPU=y
-CONFIG_AML_VPP=y
-CONFIG_AML_CANVAS=y
-CONFIG_AML_OSD=y
-CONFIG_CMD_BMP=y
-CONFIG_AML_VOUT=y
-CONFIG_AML_CVBS=n
-CONFIG_AML_HDMITX=n
-CONFIG_AML_LCD=y
-CONFIG_AML_LCD_TV=y
-CONFIG_AML_LCD_TABLET=y
-CONFIG_AML_LCD_EXTERN=y
-CONFIG_AML_BL_EXTERN=y
-CONFIG_NEED_BL301=y
-CONFIG_NEED_BL32=y
-CONFIG_FIP_IMG_SUPPORT=y
-CONFIG_SYS_LONGHELP=y
-CONFIG_CMD_MISC=n
-CONFIG_CMD_ITEST=y
-CONFIG_CMD_CPU_TEMP=y
-CONFIG_CMD_LOADB=n
-# CONFIG_AML_MESON=1
-# CONFIG_AML_MESON_G12A=1
-# CONFIG_AML_MESON_GX=1
-# CONFIG_AML_MTD=y
-# CONFIG_AML_NAND=y
-CONFIG_AML_STORAGE=y
-# CONFIG_AML_PARTITION=y
-CONFIG_AML_SECURE_BOOT_V3=y
-CONFIG_AML_SECURE_UBOOT=y
-CONFIG_AML_SECURITY_KEY=y
-CONFIG_IMG_SECURE_CHECK_SZ=66060288
-CONFIG_ANDROID_IMG=y
-CONFIG_BL2_COPY_NUM=4
-CONFIG_BOOTLOADER_CONTROL_BLOCK=y
-CONFIG_CMD_BOOTCTOL_AVB=y
-CONFIG_BT_WAKEUP=y
-#CONFIG_CEC_OSD_NAME="AML_TV"
-CONFIG_CEC_WAKEUP=n
-CONFIG_CMD_AML_MTEST=1
-CONFIG_CMD_DDR_D2PLL=n
-CONFIG_CMD_DDR_TEST=n
-CONFIG_CMD_VIU_PROBE=1
-CONFIG_CPU_CLK=1200
-CONFIG_DDR4_TIMING_TEST=0
-CONFIG_DDR_FULL_TEST=0
-CONFIG_DDR_LOW_POWER=0
-CONFIG_DDR_PLL_BYPASS=0
-# CONFIG_DDR_SIZE=0
-CONFIG_DDR_USE_EXT_VREF=0
-CONFIG_DDR_ZQ_PD=0
-CONFIG_DISCRETE_BOOTLOADER=y
-CONFIG_EFUSE=y
-CONFIG_MDUMP_COMPRESS=1
-# CONFIG_PLATFORM_POWER_INIT=y
-CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN=y
-CONFIG_RANDOM_ETHADDR=1
-CONFIG_SARADC_CH=2
-CONFIG_STORE_COMPATIBLE=y
-CONFIG_SYS_HUSH_PARSER=y
-CONFIG_SYS_NO_FLASH=y
-CONFIG_TPL_COPY_NUM=4
-CONFIG_TPL_PART_NAME="tpl"
-CONFIG_TPL_SIZE_PER_COPY=0x200000
-CONFIG_TXLX_USB=y
-CONFIG_USB_DEVICE_V2=y
-CONFIG_USB=y
-CONFIG_CMD_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_FASTBOOT=y
-CONFIG_CMD_FASTBOOT=n
-CONFIG_FASTBOOT_DWC_PCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DUALSPEED=y
-CONFIG_UNIFY_KEY_MANAGE=y
-CONFIG_SECURE_STORAGE=y
-CONFIG_VCCK_INIT_VOLTAGE=800
-# CONFIG_VDDEE_INIT_VOLTAGE=800
-# CONFIG_VDDEE_SLEEP_VOLTAGE=731
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_MESON=y
-CONFIG_DEBUG_UART_BASE=0xff803000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
-CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_CMD_D2PLL=n
-CONFIG_CMD_DDRTEST=n
-#CONFIG_MTD_UBI=y
-#CONFIG_MTD=y
-#CONFIG_NAND=y
-#CONFIG_MTD_DEVICE=y
-#CONFIG_CMD_MTDPARTS=y
-#CONFIG_AML_MTDPART=y
-#CONFIG_MTD_PARTITIONS=y
-CONFIG_DM=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_AML_SPICC=y
-CONFIG_PHY=y
-CONFIG_DM_USB=y
-CONFIG_AML_USB2_PHY=y
-CONFIG_AML_USB3_PHY=y
-CONFIG_AML_USB=y
-CONFIG_DM_ETH=y
-#CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_CMD_SF=n
-CONFIG_AML_SPIFC=y
-CONFIG_SPI_FLASH_WINBOND=y
-#CONFIG_SPI_FLASH_MTD=y
-#CONFIG_SPI_NAND=y
-CONFIG_CMD_RSVMEM=n
-CONFIG_CMD_REBOOT=y
-CONFIG_CMD_FACTORY_BOOT=y
-CONFIG_MMC_FTS=y
-CONFIG_AML_TSENSOR=y
-CONFIG_AML_TSENSOR_COOL=y
-CONFIG_AML_OSCRING=y
-#CONFIG_CMD_DDR_D2PLL=y
-CONFIG_CMD_DDR_TEST=y
-CONFIG_NOT_DTS_CONTROL_BL=y
-CONFIG_CMD_BOOTD=n
-CONFIG_CMD_BOOTI=n
-CONFIG_CMD_NET=n
-CONFIG_CMD_ELF=n
-CONFIG_CMD_MEMORY=n
-CONFIG_CMD_CONSOLE=n
-CONFIG_CMD_DM=n
-CONFIG_CMD_EDITENV=n
-CONFIG_CMD_FLASH=n
-CONFIG_CMD_GO=n
-CONFIG_CMD_UNZIP=n
-CONFIG_CMD_XIMG=n
-CONFIG_CMD_LZMADEC=n
-CONFIG_AML_RPMB_DISABLE=y
-CONFIG_CMD_SOURCE=n
-CONFIG_CMD_BOOTEFI=y
-CONFIG_CMD_PXE=n
-CONFIG_CMD_EXT2=n
-CONFIG_CMD_FS_GENERIC=n
-CONFIG_CMD_PART=n
-CONFIG_AML_CMD_OSD=y
-CONFIG_CMD_VOUT=y
-CONFIG_CMD_STORAGE=y
-CONFIG_ANDROID_BOOT_IMAGE=y
-CONFIG_LIBAVB=y
diff --git a/configs/g12b_newman_bx_zircon_defconfig b/configs/g12b_newman_bx_zircon_defconfig
deleted file mode 100644
index d780926..0000000
--- a/configs/g12b_newman_bx_zircon_defconfig
+++ /dev/null
@@ -1,181 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MESON=y
-CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_MESON_G12B=y
-CONFIG_TARGET_G12B_NEWMAN_BX=y
-CONFIG_ZIRCON_BOOT_IMAGE=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_AML_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_MMC_MESON_GX=y
-# CONFIG_AML_GPIO=y
-CONFIG_SYS_PROMPT="g12b_newman_bx# "
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-t931-newman"
-CONFIG_BOOTCOMMAND="run storeboot"
-CONFIG_BOOTDELAY=1
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_CPU_CLK=1200
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SPI=y
-CONFIG_CMD_SARADC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ADC=y
-CONFIG_SARADC_MESON=y
-CONFIG_CLK=y
-CONFIG_CLK_MESON=y
-CONFIG_CLK_MESON_G12=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_MESON_G12A=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
-CONFIG_PWM_MESON=y
-CONFIG_ADC_POWER_KEY_CHAN=2
-CONFIG_ADC_POWER_KEY_VAL=0
-CONFIG_WDT=y
-CONFIG_WDT_MESON=y
-CONFIG_CMD_WATCHDOG=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MESON=y
-CONFIG_CMD_I2C=y
-# CONFIG_AML_BL33_COMPRESS_ENABLE=1
-CONFIG_AML_CRYPTO_UBOOT=y
-CONFIG_AML_CUSTOMER_ID=0
-CONFIG_AML_DRIVER=y
-CONFIG_AML_MEDIA=y
-CONFIG_AML_VPU=y
-CONFIG_AML_VPP=y
-CONFIG_AML_CANVAS=y
-CONFIG_AML_OSD=y
-CONFIG_CMD_BMP=y
-CONFIG_AML_VOUT=y
-CONFIG_AML_CVBS=y
-CONFIG_AML_HDMITX=y
-CONFIG_AML_LCD=y
-CONFIG_AML_LCD_TV=y
-CONFIG_AML_LCD_TABLET=y
-CONFIG_AML_LCD_EXTERN=y
-CONFIG_AML_BL_EXTERN=y
-CONFIG_NEED_BL301=y
-CONFIG_NEED_BL32=y
-CONFIG_FIP_IMG_SUPPORT=y
-CONFIG_SYS_LONGHELP=y
-CONFIG_CMD_MISC=y
-CONFIG_CMD_ITEST=y
-CONFIG_CMD_CPU_TEMP=y
-CONFIG_CMD_LOADB=y
-# CONFIG_AML_MESON=1
-# CONFIG_AML_MESON_G12A=1
-# CONFIG_AML_MESON_GX=1
-# CONFIG_AML_MTD=y
-# CONFIG_AML_NAND=y
-CONFIG_AML_STORAGE=y
-# CONFIG_AML_PARTITION=y
-CONFIG_AML_SECURE_BOOT_V3=y
-CONFIG_AML_SECURE_UBOOT=y
-CONFIG_AML_SECURITY_KEY=y
-CONFIG_IMG_SECURE_CHECK_SZ=66060288
-CONFIG_ANDROID_IMG=y
-CONFIG_BL2_COPY_NUM=4
-CONFIG_BOOTLOADER_CONTROL_BLOCK=y
-# CONFIG_CMD_BOOTCTOL_AVB=y
-CONFIG_BT_WAKEUP=y
-CONFIG_CEC_OSD_NAME="AML_TV"
-CONFIG_CEC_WAKEUP=y
-CONFIG_CMD_AML_MTEST=1
-CONFIG_CMD_DDR_D2PLL=0
-CONFIG_CMD_DDR_TEST=0
-CONFIG_CMD_VIU_PROBE=1
-CONFIG_CPU_CLK=1200
-CONFIG_DDR4_TIMING_TEST=0
-CONFIG_DDR_FULL_TEST=0
-CONFIG_DDR_LOW_POWER=0
-CONFIG_DDR_PLL_BYPASS=0
-# CONFIG_DDR_SIZE=0
-CONFIG_DDR_USE_EXT_VREF=0
-CONFIG_DDR_ZQ_PD=0
-CONFIG_DISCRETE_BOOTLOADER=y
-CONFIG_EFUSE=y
-CONFIG_MDUMP_COMPRESS=1
-# CONFIG_PLATFORM_POWER_INIT=y
-CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN=y
-CONFIG_RANDOM_ETHADDR=1
-CONFIG_SARADC_CH=2
-CONFIG_STORE_COMPATIBLE=y
-CONFIG_SYS_HUSH_PARSER=y
-CONFIG_SYS_NO_FLASH=y
-CONFIG_TPL_COPY_NUM=4
-CONFIG_TPL_PART_NAME="tpl"
-CONFIG_TPL_SIZE_PER_COPY=0x200000
-CONFIG_TXLX_USB=y
-CONFIG_USB_DEVICE_V2=y
-CONFIG_USB=y
-CONFIG_CMD_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_FASTBOOT=y
-CONFIG_CMD_FASTBOOT=y
-CONFIG_FASTBOOT_DWC_PCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DUALSPEED=y
-CONFIG_AML_V2_FACTORY_BURN=y
-CONFIG_USB_BURNING_TOOL=y
-CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
-CONFIG_SD_BURNING_SUPPORT_UI=y
-CONFIG_UNIFY_KEY_MANAGE=y
-CONFIG_SECURE_STORAGE=y
-CONFIG_VCCK_INIT_VOLTAGE=800
-# CONFIG_VDDEE_INIT_VOLTAGE=800
-# CONFIG_VDDEE_SLEEP_VOLTAGE=731
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_MESON=y
-CONFIG_DEBUG_UART_BASE=0xff803000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
-CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_CMD_D2PLL=n
-CONFIG_CMD_DDRTEST=n
-#CONFIG_MTD_UBI=y
-#CONFIG_MTD=y
-#CONFIG_NAND=y
-#CONFIG_MTD_DEVICE=y
-#CONFIG_CMD_MTDPARTS=y
-#CONFIG_AML_MTDPART=y
-#CONFIG_MTD_PARTITIONS=y
-CONFIG_DM=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_AML_SPICC=y
-CONFIG_PHY=y
-CONFIG_DM_USB=y
-CONFIG_AML_USB2_PHY=y
-CONFIG_AML_USB3_PHY=y
-CONFIG_AML_USB=y
-CONFIG_DM_ETH=y
-#CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_CMD_SF=y
-CONFIG_AML_SPIFC=y
-CONFIG_SPI_FLASH_WINBOND=y
-#CONFIG_SPI_FLASH_MTD=y
-#CONFIG_SPI_NAND=y
-CONFIG_CMD_RSVMEM=y
-CONFIG_CMD_REBOOT=y
-CONFIG_CMD_FACTORY_BOOT=y
-CONFIG_MMC_FTS=y
-CONFIG_NOT_DTS_CONTROL_BL=y
-CONFIG_AML_TSENSOR=y
-CONFIG_AML_TSENSOR_COOL=y
-CONFIG_AML_OSCRING=y
-#CONFIG_CMD_DDR_D2PLL=y
-CONFIG_CMD_DDR_TEST=y
diff --git a/configs/g12b_newman_p2_1_defconfig b/configs/g12b_newman_p2_1_defconfig
deleted file mode 100644
index 2037000..0000000
--- a/configs/g12b_newman_p2_1_defconfig
+++ /dev/null
@@ -1,204 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MESON=y
-CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_MESON_G12B=y
-CONFIG_TARGET_G12B_NEWMAN_PX=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_AML_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_MMC_MESON_GX=y
-# CONFIG_AML_GPIO=y
-CONFIG_SYS_PROMPT="g12b_newman_p2_1# "
-CONFIG_G12B_NEWMAN_P2_1=y
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-t931-newman"
-CONFIG_BOOTCOMMAND="run storeboot"
-CONFIG_BOOTDELAY=-2
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_CPU_CLK=1200
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SPI=n
-CONFIG_CMD_SARADC=n
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ADC=y
-CONFIG_SARADC_MESON=y
-CONFIG_CLK=y
-CONFIG_CLK_MESON=y
-CONFIG_CLK_MESON_G12=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_MESON_G12A=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
-CONFIG_PWM_MESON=y
-CONFIG_ADC_POWER_KEY_CHAN=2
-CONFIG_ADC_POWER_KEY_VAL=0
-CONFIG_WDT=y
-CONFIG_WDT_MESON=y
-CONFIG_CMD_WATCHDOG=n
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MESON=y
-CONFIG_CMD_I2C=n
-# CONFIG_AML_BL33_COMPRESS_ENABLE=1
-CONFIG_AML_CRYPTO_UBOOT=y
-CONFIG_AML_CUSTOMER_ID=0
-CONFIG_AML_DRIVER=y
-CONFIG_AML_MEDIA=y
-CONFIG_AML_VPU=y
-CONFIG_AML_VPP=y
-CONFIG_AML_CANVAS=y
-CONFIG_AML_OSD=y
-CONFIG_CMD_BMP=y
-CONFIG_AML_VOUT=y
-CONFIG_AML_CVBS=n
-CONFIG_AML_HDMITX=n
-CONFIG_AML_LCD=y
-CONFIG_AML_LCD_TV=y
-CONFIG_AML_LCD_TABLET=y
-CONFIG_AML_LCD_EXTERN=y
-CONFIG_AML_BL_EXTERN=y
-CONFIG_NEED_BL301=y
-CONFIG_NEED_BL32=y
-CONFIG_FIP_IMG_SUPPORT=y
-CONFIG_SYS_LONGHELP=y
-CONFIG_CMD_MISC=n
-CONFIG_CMD_ITEST=y
-CONFIG_CMD_CPU_TEMP=y
-CONFIG_CMD_LOADB=n
-# CONFIG_AML_MESON=1
-# CONFIG_AML_MESON_G12A=1
-# CONFIG_AML_MESON_GX=1
-# CONFIG_AML_MTD=y
-# CONFIG_AML_NAND=y
-CONFIG_AML_STORAGE=y
-# CONFIG_AML_PARTITION=y
-CONFIG_AML_SECURE_BOOT_V3=y
-CONFIG_AML_SECURE_UBOOT=y
-CONFIG_AML_SECURITY_KEY=y
-CONFIG_IMG_SECURE_CHECK_SZ=66060288
-CONFIG_ANDROID_IMG=y
-CONFIG_BL2_COPY_NUM=4
-CONFIG_BOOTLOADER_CONTROL_BLOCK=y
-# CONFIG_CMD_BOOTCTOL_AVB=y
-CONFIG_BT_WAKEUP=y
-#CONFIG_CEC_OSD_NAME="AML_TV"
-CONFIG_CEC_WAKEUP=n
-CONFIG_CMD_AML_MTEST=1
-CONFIG_CMD_DDR_D2PLL=n
-CONFIG_CMD_DDR_TEST=n
-CONFIG_CMD_VIU_PROBE=1
-CONFIG_CPU_CLK=1200
-CONFIG_DDR4_TIMING_TEST=0
-CONFIG_DDR_FULL_TEST=0
-CONFIG_DDR_LOW_POWER=0
-CONFIG_DDR_PLL_BYPASS=0
-# CONFIG_DDR_SIZE=0
-CONFIG_DDR_USE_EXT_VREF=0
-CONFIG_DDR_ZQ_PD=0
-CONFIG_DISCRETE_BOOTLOADER=y
-CONFIG_EFUSE=y
-CONFIG_MDUMP_COMPRESS=1
-# CONFIG_PLATFORM_POWER_INIT=y
-CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN=y
-CONFIG_RANDOM_ETHADDR=1
-CONFIG_SARADC_CH=2
-CONFIG_STORE_COMPATIBLE=y
-CONFIG_SYS_HUSH_PARSER=y
-CONFIG_SYS_NO_FLASH=y
-CONFIG_TPL_COPY_NUM=4
-CONFIG_TPL_PART_NAME="tpl"
-CONFIG_TPL_SIZE_PER_COPY=0x200000
-CONFIG_TXLX_USB=y
-CONFIG_USB_DEVICE_V2=y
-CONFIG_USB=y
-CONFIG_CMD_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_FASTBOOT=y
-CONFIG_CMD_FASTBOOT=n
-CONFIG_FASTBOOT_DWC_PCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DUALSPEED=y
-CONFIG_AML_V2_FACTORY_BURN=y
-CONFIG_USB_BURNING_TOOL=y
-CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
-CONFIG_SD_BURNING_SUPPORT_UI=y
-CONFIG_UNIFY_KEY_MANAGE=y
-CONFIG_SECURE_STORAGE=y
-CONFIG_VCCK_INIT_VOLTAGE=800
-# CONFIG_VDDEE_INIT_VOLTAGE=800
-# CONFIG_VDDEE_SLEEP_VOLTAGE=731
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_MESON=y
-CONFIG_DEBUG_UART_BASE=0xff803000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
-CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_CMD_D2PLL=n
-CONFIG_CMD_DDRTEST=n
-#CONFIG_MTD_UBI=y
-#CONFIG_MTD=y
-#CONFIG_NAND=y
-#CONFIG_MTD_DEVICE=y
-#CONFIG_CMD_MTDPARTS=y
-#CONFIG_AML_MTDPART=y
-#CONFIG_MTD_PARTITIONS=y
-CONFIG_DM=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_AML_SPICC=y
-CONFIG_PHY=y
-CONFIG_DM_USB=y
-CONFIG_AML_USB2_PHY=y
-CONFIG_AML_USB3_PHY=y
-CONFIG_AML_USB=y
-CONFIG_DM_ETH=y
-#CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_CMD_SF=n
-CONFIG_AML_SPIFC=y
-CONFIG_SPI_FLASH_WINBOND=y
-#CONFIG_SPI_FLASH_MTD=y
-#CONFIG_SPI_NAND=y
-CONFIG_CMD_RSVMEM=n
-CONFIG_CMD_REBOOT=y
-CONFIG_CMD_FACTORY_BOOT=y
-CONFIG_MMC_FTS=y
-CONFIG_NOT_DTS_CONTROL_BL=y
-CONFIG_AML_TSENSOR=y
-CONFIG_AML_TSENSOR_COOL=y
-CONFIG_AML_OSCRING=y
-#CONFIG_CMD_DDR_D2PLL=y
-CONFIG_CMD_DDR_TEST=y
-CONFIG_CMD_BOOTD=n
-CONFIG_CMD_BOOTI=n
-CONFIG_CMD_NET=n
-CONFIG_CMD_ELF=n
-CONFIG_CMD_MEMORY=n
-CONFIG_CMD_CONSOLE=n
-CONFIG_CMD_DM=n
-CONFIG_CMD_EDITENV=n
-CONFIG_CMD_FLASH=n
-CONFIG_CMD_GO=n
-CONFIG_CMD_UNZIP=n
-CONFIG_CMD_XIMG=n
-CONFIG_CMD_LZMADEC=n
-CONFIG_AML_RPMB_DISABLE=y
-CONFIG_CMD_SOURCE=n
-CONFIG_CMD_BOOTEFI=n
-CONFIG_CMD_PXE=n
-CONFIG_CMD_EXT2=n
-CONFIG_CMD_FS_GENERIC=n
-CONFIG_CMD_PART=n
-CONFIG_CMD_OSD=y
-CONFIG_CMD_VOUT=y
-CONFIG_CMD_STORAGE=y
diff --git a/configs/g12b_newman_p2_1_zircon_defconfig b/configs/g12b_newman_p2_1_zircon_defconfig
deleted file mode 100644
index 7a5e358..0000000
--- a/configs/g12b_newman_p2_1_zircon_defconfig
+++ /dev/null
@@ -1,176 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MESON=y
-CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_MESON_G12B=y
-CONFIG_TARGET_G12B_NEWMAN_PX=y
-CONFIG_ZIRCON_BOOT_IMAGE=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_AML_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_MMC_MESON_GX=y
-# CONFIG_AML_GPIO=y
-CONFIG_SYS_PROMPT="g12b_newman_p2_1# "
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-t931-newman"
-CONFIG_BOOTCOMMAND="run storeboot"
-CONFIG_BOOTDELAY=1
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_CPU_CLK=1200
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SPI=y
-CONFIG_CMD_SARADC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ADC=y
-CONFIG_SARADC_MESON=y
-CONFIG_CLK=y
-CONFIG_CLK_MESON=y
-CONFIG_CLK_MESON_G12=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_MESON_G12A=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
-CONFIG_PWM_MESON=y
-CONFIG_ADC_POWER_KEY_CHAN=2
-CONFIG_ADC_POWER_KEY_VAL=0
-CONFIG_WDT=y
-CONFIG_WDT_MESON=y
-CONFIG_CMD_WATCHDOG=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MESON=y
-CONFIG_CMD_I2C=y
-# CONFIG_AML_BL33_COMPRESS_ENABLE=1
-CONFIG_AML_CRYPTO_UBOOT=y
-CONFIG_AML_CUSTOMER_ID=0
-CONFIG_AML_DRIVER=y
-CONFIG_AML_MEDIA=y
-CONFIG_AML_VPU=y
-CONFIG_AML_VPP=y
-CONFIG_AML_CANVAS=y
-CONFIG_AML_OSD=y
-CONFIG_CMD_BMP=y
-CONFIG_AML_VOUT=y
-CONFIG_AML_CVBS=y
-CONFIG_AML_HDMITX=y
-CONFIG_AML_LCD=y
-CONFIG_AML_LCD_TV=y
-CONFIG_AML_LCD_TABLET=y
-CONFIG_AML_LCD_EXTERN=y
-CONFIG_AML_BL_EXTERN=y
-CONFIG_NEED_BL301=y
-CONFIG_NEED_BL32=y
-CONFIG_FIP_IMG_SUPPORT=y
-CONFIG_SYS_LONGHELP=y
-CONFIG_CMD_MISC=y
-CONFIG_CMD_ITEST=y
-CONFIG_CMD_CPU_TEMP=y
-CONFIG_CMD_LOADB=y
-# CONFIG_AML_MESON=1
-# CONFIG_AML_MESON_G12A=1
-# CONFIG_AML_MESON_GX=1
-# CONFIG_AML_MTD=y
-# CONFIG_AML_NAND=y
-CONFIG_AML_STORAGE=y
-# CONFIG_AML_PARTITION=y
-CONFIG_AML_SECURE_BOOT_V3=y
-CONFIG_AML_SECURE_UBOOT=y
-CONFIG_AML_SECURITY_KEY=y
-CONFIG_IMG_SECURE_CHECK_SZ=66060288
-CONFIG_ANDROID_IMG=y
-CONFIG_BL2_COPY_NUM=4
-CONFIG_BOOTLOADER_CONTROL_BLOCK=y
-# CONFIG_CMD_BOOTCTOL_AVB=y
-CONFIG_BT_WAKEUP=y
-CONFIG_CEC_OSD_NAME="AML_TV"
-CONFIG_CEC_WAKEUP=y
-CONFIG_CMD_AML_MTEST=1
-CONFIG_CMD_DDR_D2PLL=0
-CONFIG_CMD_DDR_TEST=0
-CONFIG_CMD_VIU_PROBE=1
-CONFIG_CPU_CLK=1200
-CONFIG_DDR4_TIMING_TEST=0
-CONFIG_DDR_FULL_TEST=0
-CONFIG_DDR_LOW_POWER=0
-CONFIG_DDR_PLL_BYPASS=0
-# CONFIG_DDR_SIZE=0
-CONFIG_DDR_USE_EXT_VREF=0
-CONFIG_DDR_ZQ_PD=0
-CONFIG_DISCRETE_BOOTLOADER=y
-CONFIG_EFUSE=y
-CONFIG_MDUMP_COMPRESS=1
-# CONFIG_PLATFORM_POWER_INIT=y
-CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN=y
-CONFIG_RANDOM_ETHADDR=1
-CONFIG_SARADC_CH=2
-CONFIG_STORE_COMPATIBLE=y
-CONFIG_SYS_HUSH_PARSER=y
-CONFIG_SYS_NO_FLASH=y
-CONFIG_TPL_COPY_NUM=4
-CONFIG_TPL_PART_NAME="tpl"
-CONFIG_TPL_SIZE_PER_COPY=0x200000
-CONFIG_TXLX_USB=y
-CONFIG_USB_DEVICE_V2=y
-CONFIG_USB=y
-CONFIG_CMD_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_FASTBOOT=y
-CONFIG_CMD_FASTBOOT=y
-CONFIG_FASTBOOT_DWC_PCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DUALSPEED=y
-CONFIG_AML_V2_FACTORY_BURN=y
-CONFIG_USB_BURNING_TOOL=y
-CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
-CONFIG_SD_BURNING_SUPPORT_UI=y
-CONFIG_UNIFY_KEY_MANAGE=y
-CONFIG_SECURE_STORAGE=y
-CONFIG_VCCK_INIT_VOLTAGE=800
-# CONFIG_VDDEE_INIT_VOLTAGE=800
-# CONFIG_VDDEE_SLEEP_VOLTAGE=731
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_MESON=y
-CONFIG_DEBUG_UART_BASE=0xff803000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
-CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_CMD_D2PLL=n
-CONFIG_CMD_DDRTEST=n
-#CONFIG_MTD_UBI=y
-#CONFIG_MTD=y
-#CONFIG_NAND=y
-#CONFIG_MTD_DEVICE=y
-#CONFIG_CMD_MTDPARTS=y
-#CONFIG_AML_MTDPART=y
-#CONFIG_MTD_PARTITIONS=y
-CONFIG_DM=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_AML_SPICC=y
-CONFIG_PHY=y
-CONFIG_DM_USB=y
-CONFIG_AML_USB2_PHY=y
-CONFIG_AML_USB3_PHY=y
-CONFIG_AML_USB=y
-CONFIG_DM_ETH=y
-#CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_CMD_SF=y
-CONFIG_AML_SPIFC=y
-CONFIG_SPI_FLASH_WINBOND=y
-#CONFIG_SPI_FLASH_MTD=y
-#CONFIG_SPI_NAND=y
-CONFIG_CMD_RSVMEM=y
-CONFIG_CMD_REBOOT=y
-CONFIG_CMD_FACTORY_BOOT=y
-CONFIG_MMC_FTS=y
-CONFIG_G12B_NEWMAN_P2_1=y
diff --git a/configs/g12b_newman_px_defconfig b/configs/g12b_newman_px_defconfig
deleted file mode 100755
index 348e023..0000000
--- a/configs/g12b_newman_px_defconfig
+++ /dev/null
@@ -1,205 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MESON=y
-CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_MESON_G12B=y
-CONFIG_TARGET_G12B_NEWMAN_PX=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_AML_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_MMC_MESON_GX=y
-# CONFIG_AML_GPIO=y
-CONFIG_SYS_PROMPT="g12b_newman_px# "
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-t931-newman"
-CONFIG_BOOTCOMMAND="run storeboot"
-CONFIG_BOOTDELAY=-2
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_CPU_CLK=1200
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SPI=n
-CONFIG_CMD_SARADC=n
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ADC=y
-CONFIG_SARADC_MESON=y
-CONFIG_CLK=y
-CONFIG_CLK_MESON=y
-CONFIG_CLK_MESON_G12=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_MESON_G12A=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
-CONFIG_PWM_MESON=y
-CONFIG_ADC_POWER_KEY_CHAN=2
-CONFIG_ADC_POWER_KEY_VAL=0
-CONFIG_WDT=y
-CONFIG_WDT_MESON=y
-CONFIG_CMD_WATCHDOG=n
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MESON=y
-CONFIG_CMD_I2C=n
-# CONFIG_AML_BL33_COMPRESS_ENABLE=1
-CONFIG_AML_CRYPTO_UBOOT=y
-CONFIG_AML_CUSTOMER_ID=0
-CONFIG_AML_DRIVER=y
-CONFIG_AML_MEDIA=y
-CONFIG_AML_VPU=y
-CONFIG_AML_VPP=y
-CONFIG_AML_CANVAS=y
-CONFIG_AML_OSD=y
-CONFIG_CMD_BMP=y
-CONFIG_AML_VOUT=y
-CONFIG_AML_CVBS=n
-CONFIG_AML_HDMITX=n
-CONFIG_AML_LCD=y
-CONFIG_AML_LCD_TV=y
-CONFIG_AML_LCD_TABLET=y
-CONFIG_AML_LCD_EXTERN=y
-CONFIG_AML_BL_EXTERN=y
-CONFIG_NEED_BL301=y
-CONFIG_NEED_BL32=y
-CONFIG_FIP_IMG_SUPPORT=y
-CONFIG_SYS_LONGHELP=y
-CONFIG_CMD_MISC=n
-CONFIG_CMD_ITEST=y
-CONFIG_CMD_CPU_TEMP=y
-CONFIG_CMD_LOADB=n
-# CONFIG_AML_MESON=1
-# CONFIG_AML_MESON_G12A=1
-# CONFIG_AML_MESON_GX=1
-# CONFIG_AML_MTD=y
-# CONFIG_AML_NAND=y
-CONFIG_AML_STORAGE=y
-# CONFIG_AML_PARTITION=y
-CONFIG_AML_SECURE_BOOT_V3=y
-CONFIG_AML_SECURE_UBOOT=y
-CONFIG_AML_SECURITY_KEY=y
-CONFIG_IMG_SECURE_CHECK_SZ=66060288
-CONFIG_ANDROID_IMG=y
-CONFIG_BL2_COPY_NUM=4
-CONFIG_BOOTLOADER_CONTROL_BLOCK=y
-CONFIG_CMD_BOOTCTOL_AVB=y
-CONFIG_BT_WAKEUP=y
-#CONFIG_CEC_OSD_NAME="AML_TV"
-CONFIG_CEC_WAKEUP=n
-CONFIG_CMD_AML_MTEST=1
-CONFIG_CMD_DDR_D2PLL=n
-CONFIG_CMD_DDR_TEST=n
-CONFIG_CMD_VIU_PROBE=1
-CONFIG_CPU_CLK=1200
-CONFIG_DDR4_TIMING_TEST=0
-CONFIG_DDR_FULL_TEST=0
-CONFIG_DDR_LOW_POWER=0
-CONFIG_DDR_PLL_BYPASS=0
-# CONFIG_DDR_SIZE=0
-CONFIG_DDR_USE_EXT_VREF=0
-CONFIG_DDR_ZQ_PD=0
-CONFIG_DISCRETE_BOOTLOADER=y
-CONFIG_EFUSE=y
-CONFIG_MDUMP_COMPRESS=1
-# CONFIG_PLATFORM_POWER_INIT=y
-CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN=y
-CONFIG_RANDOM_ETHADDR=1
-CONFIG_SARADC_CH=2
-CONFIG_STORE_COMPATIBLE=y
-CONFIG_SYS_HUSH_PARSER=y
-CONFIG_SYS_NO_FLASH=y
-CONFIG_TPL_COPY_NUM=4
-CONFIG_TPL_PART_NAME="tpl"
-CONFIG_TPL_SIZE_PER_COPY=0x200000
-CONFIG_TXLX_USB=y
-CONFIG_USB_DEVICE_V2=y
-CONFIG_USB=y
-CONFIG_CMD_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_FASTBOOT=y
-CONFIG_CMD_FASTBOOT=n
-CONFIG_FASTBOOT_DWC_PCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DUALSPEED=y
-CONFIG_AML_V2_FACTORY_BURN=y
-CONFIG_USB_BURNING_TOOL=y
-CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
-CONFIG_SD_BURNING_SUPPORT_UI=y
-CONFIG_UNIFY_KEY_MANAGE=y
-CONFIG_SECURE_STORAGE=y
-CONFIG_VCCK_INIT_VOLTAGE=800
-# CONFIG_VDDEE_INIT_VOLTAGE=800
-# CONFIG_VDDEE_SLEEP_VOLTAGE=731
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_MESON=y
-CONFIG_DEBUG_UART_BASE=0xff803000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
-CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_CMD_D2PLL=n
-CONFIG_CMD_DDRTEST=n
-#CONFIG_MTD_UBI=y
-#CONFIG_MTD=y
-#CONFIG_NAND=y
-#CONFIG_MTD_DEVICE=y
-#CONFIG_CMD_MTDPARTS=y
-#CONFIG_AML_MTDPART=y
-#CONFIG_MTD_PARTITIONS=y
-CONFIG_DM=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_AML_SPICC=y
-CONFIG_PHY=y
-CONFIG_DM_USB=y
-CONFIG_AML_USB2_PHY=y
-CONFIG_AML_USB3_PHY=y
-CONFIG_AML_USB=y
-CONFIG_DM_ETH=y
-#CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_CMD_SF=n
-CONFIG_AML_SPIFC=y
-CONFIG_SPI_FLASH_WINBOND=y
-#CONFIG_SPI_FLASH_MTD=y
-#CONFIG_SPI_NAND=y
-CONFIG_CMD_RSVMEM=n
-CONFIG_CMD_REBOOT=y
-CONFIG_CMD_FACTORY_BOOT=y
-CONFIG_MMC_FTS=y
-CONFIG_AML_TSENSOR=y
-CONFIG_AML_TSENSOR_COOL=y
-CONFIG_AML_OSCRING=y
-#CONFIG_CMD_DDR_D2PLL=y
-CONFIG_CMD_DDR_TEST=y
-CONFIG_NOT_DTS_CONTROL_BL=y
-CONFIG_CMD_BOOTD=n
-CONFIG_CMD_BOOTI=n
-CONFIG_CMD_NET=n
-CONFIG_CMD_ELF=n
-CONFIG_CMD_MEMORY=n
-CONFIG_CMD_CONSOLE=n
-CONFIG_CMD_DM=n
-CONFIG_CMD_EDITENV=n
-CONFIG_CMD_FLASH=n
-CONFIG_CMD_GO=n
-CONFIG_CMD_UNZIP=n
-CONFIG_CMD_XIMG=n
-CONFIG_CMD_LZMADEC=n
-CONFIG_AML_RPMB_DISABLE=y
-CONFIG_CMD_SOURCE=n
-CONFIG_CMD_BOOTEFI=y
-CONFIG_CMD_PXE=n
-CONFIG_CMD_EXT2=n
-CONFIG_CMD_FS_GENERIC=n
-CONFIG_CMD_PART=n
-CONFIG_AML_CMD_OSD=y
-CONFIG_CMD_VOUT=y
-CONFIG_CMD_STORAGE=y
-CONFIG_ANDROID_BOOT_IMAGE=y
-CONFIG_LIBAVB=y
diff --git a/configs/g12b_newman_px_zircon_defconfig b/configs/g12b_newman_px_zircon_defconfig
deleted file mode 100644
index 50c2622..0000000
--- a/configs/g12b_newman_px_zircon_defconfig
+++ /dev/null
@@ -1,175 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MESON=y
-CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_MESON_G12B=y
-CONFIG_TARGET_G12B_NEWMAN_PX=y
-CONFIG_ZIRCON_BOOT_IMAGE=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_AML_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_MMC_MESON_GX=y
-# CONFIG_AML_GPIO=y
-CONFIG_SYS_PROMPT="g12b_newman_px# "
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-t931-newman"
-CONFIG_BOOTCOMMAND="run storeboot"
-CONFIG_BOOTDELAY=1
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_CPU_CLK=1200
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SPI=y
-CONFIG_CMD_SARADC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ADC=y
-CONFIG_SARADC_MESON=y
-CONFIG_CLK=y
-CONFIG_CLK_MESON=y
-CONFIG_CLK_MESON_G12=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_MESON_G12A=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
-CONFIG_PWM_MESON=y
-CONFIG_ADC_POWER_KEY_CHAN=2
-CONFIG_ADC_POWER_KEY_VAL=0
-CONFIG_WDT=y
-CONFIG_WDT_MESON=y
-CONFIG_CMD_WATCHDOG=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MESON=y
-CONFIG_CMD_I2C=y
-# CONFIG_AML_BL33_COMPRESS_ENABLE=1
-CONFIG_AML_CRYPTO_UBOOT=y
-CONFIG_AML_CUSTOMER_ID=0
-CONFIG_AML_DRIVER=y
-CONFIG_AML_MEDIA=y
-CONFIG_AML_VPU=y
-CONFIG_AML_VPP=y
-CONFIG_AML_CANVAS=y
-CONFIG_AML_OSD=y
-CONFIG_CMD_BMP=y
-CONFIG_AML_VOUT=y
-CONFIG_AML_CVBS=y
-CONFIG_AML_HDMITX=y
-CONFIG_AML_LCD=y
-CONFIG_AML_LCD_TV=y
-CONFIG_AML_LCD_TABLET=y
-CONFIG_AML_LCD_EXTERN=y
-CONFIG_AML_BL_EXTERN=y
-CONFIG_NEED_BL301=y
-CONFIG_NEED_BL32=y
-CONFIG_FIP_IMG_SUPPORT=y
-CONFIG_SYS_LONGHELP=y
-CONFIG_CMD_MISC=y
-CONFIG_CMD_ITEST=y
-CONFIG_CMD_CPU_TEMP=y
-CONFIG_CMD_LOADB=y
-# CONFIG_AML_MESON=1
-# CONFIG_AML_MESON_G12A=1
-# CONFIG_AML_MESON_GX=1
-# CONFIG_AML_MTD=y
-# CONFIG_AML_NAND=y
-CONFIG_AML_STORAGE=y
-# CONFIG_AML_PARTITION=y
-CONFIG_AML_SECURE_BOOT_V3=y
-CONFIG_AML_SECURE_UBOOT=y
-CONFIG_AML_SECURITY_KEY=y
-CONFIG_IMG_SECURE_CHECK_SZ=66060288
-CONFIG_ANDROID_IMG=y
-CONFIG_BL2_COPY_NUM=4
-CONFIG_BOOTLOADER_CONTROL_BLOCK=y
-# CONFIG_CMD_BOOTCTOL_AVB=y
-CONFIG_BT_WAKEUP=y
-CONFIG_CEC_OSD_NAME="AML_TV"
-CONFIG_CEC_WAKEUP=y
-CONFIG_CMD_AML_MTEST=1
-CONFIG_CMD_DDR_D2PLL=0
-CONFIG_CMD_DDR_TEST=0
-CONFIG_CMD_VIU_PROBE=1
-CONFIG_CPU_CLK=1200
-CONFIG_DDR4_TIMING_TEST=0
-CONFIG_DDR_FULL_TEST=0
-CONFIG_DDR_LOW_POWER=0
-CONFIG_DDR_PLL_BYPASS=0
-# CONFIG_DDR_SIZE=0
-CONFIG_DDR_USE_EXT_VREF=0
-CONFIG_DDR_ZQ_PD=0
-CONFIG_DISCRETE_BOOTLOADER=y
-CONFIG_EFUSE=y
-CONFIG_MDUMP_COMPRESS=1
-# CONFIG_PLATFORM_POWER_INIT=y
-CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN=y
-CONFIG_RANDOM_ETHADDR=1
-CONFIG_SARADC_CH=2
-CONFIG_STORE_COMPATIBLE=y
-CONFIG_SYS_HUSH_PARSER=y
-CONFIG_SYS_NO_FLASH=y
-CONFIG_TPL_COPY_NUM=4
-CONFIG_TPL_PART_NAME="tpl"
-CONFIG_TPL_SIZE_PER_COPY=0x200000
-CONFIG_TXLX_USB=y
-CONFIG_USB_DEVICE_V2=y
-CONFIG_USB=y
-CONFIG_CMD_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_FASTBOOT=y
-CONFIG_CMD_FASTBOOT=y
-CONFIG_FASTBOOT_DWC_PCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DUALSPEED=y
-CONFIG_AML_V2_FACTORY_BURN=y
-CONFIG_USB_BURNING_TOOL=y
-CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
-CONFIG_SD_BURNING_SUPPORT_UI=y
-CONFIG_UNIFY_KEY_MANAGE=y
-CONFIG_SECURE_STORAGE=y
-CONFIG_VCCK_INIT_VOLTAGE=800
-# CONFIG_VDDEE_INIT_VOLTAGE=800
-# CONFIG_VDDEE_SLEEP_VOLTAGE=731
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_MESON=y
-CONFIG_DEBUG_UART_BASE=0xff803000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
-CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_CMD_D2PLL=n
-CONFIG_CMD_DDRTEST=n
-#CONFIG_MTD_UBI=y
-#CONFIG_MTD=y
-#CONFIG_NAND=y
-#CONFIG_MTD_DEVICE=y
-#CONFIG_CMD_MTDPARTS=y
-#CONFIG_AML_MTDPART=y
-#CONFIG_MTD_PARTITIONS=y
-CONFIG_DM=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_AML_SPICC=y
-CONFIG_PHY=y
-CONFIG_DM_USB=y
-CONFIG_AML_USB2_PHY=y
-CONFIG_AML_USB3_PHY=y
-CONFIG_AML_USB=y
-CONFIG_DM_ETH=y
-#CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_CMD_SF=y
-CONFIG_AML_SPIFC=y
-CONFIG_SPI_FLASH_WINBOND=y
-#CONFIG_SPI_FLASH_MTD=y
-#CONFIG_SPI_NAND=y
-CONFIG_CMD_RSVMEM=y
-CONFIG_CMD_REBOOT=y
-CONFIG_CMD_FACTORY_BOOT=y
-CONFIG_MMC_FTS=y
diff --git a/configs/g12b_puddy_px_defconfig b/configs/g12b_puddy_px_defconfig
deleted file mode 100644
index c7383d2..0000000
--- a/configs/g12b_puddy_px_defconfig
+++ /dev/null
@@ -1,201 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MESON=y
-CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_MESON_G12B=y
-CONFIG_TARGET_G12B_PUDDY_PX=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_AML_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_MMC_MESON_GX=y
-# CONFIG_AML_GPIO=y
-CONFIG_SYS_PROMPT="g12b_puddy_px# "
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-t931-puddy"
-CONFIG_BOOTCOMMAND="run storeboot"
-CONFIG_BOOTDELAY=1
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_CPU_CLK=1200
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SPI=n
-CONFIG_CMD_SARADC=n
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ADC=y
-CONFIG_SARADC_MESON=y
-CONFIG_CLK=y
-CONFIG_CLK_MESON=y
-CONFIG_CLK_MESON_G12=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_MESON_G12A=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
-CONFIG_PWM_MESON=y
-CONFIG_ADC_POWER_KEY_CHAN=2
-CONFIG_ADC_POWER_KEY_VAL=0
-CONFIG_WDT=y
-CONFIG_WDT_MESON=y
-CONFIG_CMD_WATCHDOG=n
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MESON=y
-CONFIG_CMD_I2C=n
-# CONFIG_AML_BL33_COMPRESS_ENABLE=1
-CONFIG_AML_CRYPTO_UBOOT=y
-CONFIG_AML_CUSTOMER_ID=0
-CONFIG_AML_DRIVER=y
-CONFIG_AML_MEDIA=y
-CONFIG_AML_VPU=y
-CONFIG_AML_VPP=y
-CONFIG_AML_CANVAS=y
-CONFIG_AML_OSD=y
-CONFIG_CMD_BMP=y
-CONFIG_AML_VOUT=y
-CONFIG_AML_CVBS=n
-CONFIG_AML_HDMITX=n
-CONFIG_AML_LCD=y
-CONFIG_AML_LCD_TV=y
-CONFIG_AML_LCD_TABLET=y
-CONFIG_AML_LCD_EXTERN=y
-CONFIG_AML_BL_EXTERN=y
-CONFIG_NEED_BL301=y
-CONFIG_NEED_BL32=y
-CONFIG_FIP_IMG_SUPPORT=y
-CONFIG_SYS_LONGHELP=y
-CONFIG_CMD_MISC=n
-CONFIG_CMD_ITEST=y
-CONFIG_CMD_CPU_TEMP=y
-CONFIG_CMD_LOADB=n
-# CONFIG_AML_MESON=1
-# CONFIG_AML_MESON_G12A=1
-# CONFIG_AML_MESON_GX=1
-# CONFIG_AML_MTD=y
-# CONFIG_AML_NAND=y
-CONFIG_AML_STORAGE=y
-# CONFIG_AML_PARTITION=y
-CONFIG_AML_SECURE_BOOT_V3=y
-CONFIG_AML_SECURE_UBOOT=y
-CONFIG_AML_SECURITY_KEY=y
-CONFIG_IMG_SECURE_CHECK_SZ=66060288
-CONFIG_ANDROID_IMG=y
-CONFIG_BL2_COPY_NUM=4
-CONFIG_BOOTLOADER_CONTROL_BLOCK=y
-CONFIG_CMD_BOOTCTOL_AVB=y
-CONFIG_BT_WAKEUP=y
-# CONFIG_CEC_OSD_NAME="AML_TV"
-CONFIG_CEC_WAKEUP=n
-CONFIG_CMD_AML_MTEST=1
-CONFIG_CMD_DDR_D2PLL=n
-CONFIG_CMD_DDR_TEST=n
-CONFIG_CMD_VIU_PROBE=1
-CONFIG_CPU_CLK=1200
-CONFIG_DDR4_TIMING_TEST=0
-CONFIG_DDR_FULL_TEST=0
-CONFIG_DDR_LOW_POWER=0
-CONFIG_DDR_PLL_BYPASS=0
-# CONFIG_DDR_SIZE=0
-CONFIG_DDR_USE_EXT_VREF=0
-CONFIG_DDR_ZQ_PD=0
-CONFIG_DISCRETE_BOOTLOADER=y
-CONFIG_EFUSE=y
-CONFIG_MDUMP_COMPRESS=1
-# CONFIG_PLATFORM_POWER_INIT=y
-CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN=y
-CONFIG_RANDOM_ETHADDR=1
-CONFIG_SARADC_CH=2
-CONFIG_STORE_COMPATIBLE=y
-CONFIG_SYS_HUSH_PARSER=y
-CONFIG_SYS_NO_FLASH=y
-CONFIG_TPL_COPY_NUM=4
-CONFIG_TPL_PART_NAME="tpl"
-CONFIG_TPL_SIZE_PER_COPY=0x200000
-CONFIG_TXLX_USB=y
-CONFIG_USB_DEVICE_V2=y
-CONFIG_USB=y
-CONFIG_CMD_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_FASTBOOT=y
-CONFIG_CMD_FASTBOOT=n
-CONFIG_FASTBOOT_DWC_PCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DUALSPEED=y
-CONFIG_UNIFY_KEY_MANAGE=y
-CONFIG_SECURE_STORAGE=y
-CONFIG_VCCK_INIT_VOLTAGE=800
-# CONFIG_VDDEE_INIT_VOLTAGE=800
-# CONFIG_VDDEE_SLEEP_VOLTAGE=731
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_MESON=y
-CONFIG_DEBUG_UART_BASE=0xff803000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
-CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_CMD_D2PLL=n
-CONFIG_CMD_DDRTEST=n
-#CONFIG_MTD_UBI=y
-#CONFIG_MTD=y
-#CONFIG_NAND=y
-#CONFIG_MTD_DEVICE=y
-#CONFIG_CMD_MTDPARTS=y
-#CONFIG_AML_MTDPART=y
-#CONFIG_MTD_PARTITIONS=y
-CONFIG_DM=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_AML_SPICC=y
-CONFIG_PHY=y
-CONFIG_DM_USB=y
-CONFIG_AML_USB2_PHY=y
-CONFIG_AML_USB3_PHY=y
-CONFIG_AML_USB=y
-CONFIG_DM_ETH=y
-#CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_CMD_SF=n
-CONFIG_AML_SPIFC=y
-CONFIG_SPI_FLASH_WINBOND=y
-#CONFIG_SPI_FLASH_MTD=y
-#CONFIG_SPI_NAND=y
-CONFIG_CMD_RSVMEM=n
-CONFIG_CMD_REBOOT=y
-CONFIG_CMD_FACTORY_BOOT=y
-CONFIG_MMC_FTS=y
-CONFIG_NOT_DTS_CONTROL_BL=y
-CONFIG_AML_TSENSOR=y
-CONFIG_AML_TSENSOR_COOL=y
-CONFIG_AML_OSCRING=y
-#CONFIG_CMD_DDR_D2PLL=y
-CONFIG_CMD_DDR_TEST=y
-CONFIG_CMD_BOOTD=n
-CONFIG_CMD_BOOTI=n
-CONFIG_CMD_NET=n
-CONFIG_CMD_ELF=n
-CONFIG_CMD_MEMORY=n
-CONFIG_CMD_CONSOLE=n
-CONFIG_CMD_DM=n
-CONFIG_CMD_EDITENV=n
-CONFIG_CMD_FLASH=n
-CONFIG_CMD_GO=n
-CONFIG_CMD_UNZIP=n
-CONFIG_CMD_XIMG=n
-CONFIG_CMD_LZMADEC=n
-CONFIG_AML_RPMB_DISABLE=y
-CONFIG_CMD_SOURCE=n
-CONFIG_CMD_BOOTEFI=y
-CONFIG_CMD_PXE=n
-CONFIG_CMD_EXT2=n
-CONFIG_CMD_FS_GENERIC=n
-CONFIG_CMD_PART=n
-CONFIG_AML_CMD_OSD=y
-CONFIG_CMD_VOUT=y
-CONFIG_CMD_STORAGE=y
-CONFIG_ANDROID_BOOT_IMAGE=y
-CONFIG_LIBAVB=y
diff --git a/configs/g12b_puddy_px_zircon_defconfig b/configs/g12b_puddy_px_zircon_defconfig
deleted file mode 100644
index 6da90f8..0000000
--- a/configs/g12b_puddy_px_zircon_defconfig
+++ /dev/null
@@ -1,174 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MESON=y
-CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_MESON_G12B=y
-CONFIG_TARGET_G12B_PUDDY_PX=y
-CONFIG_ZIRCON_BOOT_IMAGE=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_AML_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_MMC_MESON_GX=y
-# CONFIG_AML_GPIO=y
-CONFIG_SYS_PROMPT="g12b_puddy_px# "
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-t931-newman"
-CONFIG_BOOTCOMMAND="run storeboot"
-CONFIG_BOOTDELAY=1
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_CPU_CLK=1200
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SPI=y
-CONFIG_CMD_SARADC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ADC=y
-CONFIG_SARADC_MESON=y
-CONFIG_CLK=y
-CONFIG_CLK_MESON=y
-CONFIG_CLK_MESON_G12=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_MESON_G12A=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
-CONFIG_PWM_MESON=y
-CONFIG_ADC_POWER_KEY_CHAN=2
-CONFIG_ADC_POWER_KEY_VAL=0
-CONFIG_WDT=y
-CONFIG_WDT_MESON=y
-CONFIG_CMD_WATCHDOG=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MESON=y
-CONFIG_CMD_I2C=y
-# CONFIG_AML_BL33_COMPRESS_ENABLE=1
-CONFIG_AML_CRYPTO_UBOOT=y
-CONFIG_AML_CUSTOMER_ID=0
-CONFIG_AML_DRIVER=y
-CONFIG_AML_MEDIA=y
-CONFIG_AML_VPU=y
-CONFIG_AML_VPP=y
-CONFIG_AML_CANVAS=y
-CONFIG_AML_OSD=y
-CONFIG_CMD_BMP=y
-CONFIG_AML_VOUT=y
-CONFIG_AML_CVBS=y
-CONFIG_AML_HDMITX=y
-CONFIG_AML_LCD=y
-CONFIG_AML_LCD_TV=y
-CONFIG_AML_LCD_TABLET=y
-CONFIG_AML_LCD_EXTERN=y
-CONFIG_AML_BL_EXTERN=y
-CONFIG_NEED_BL301=y
-CONFIG_NEED_BL32=y
-CONFIG_FIP_IMG_SUPPORT=y
-CONFIG_SYS_LONGHELP=y
-CONFIG_CMD_MISC=y
-CONFIG_CMD_ITEST=y
-CONFIG_CMD_CPU_TEMP=y
-CONFIG_CMD_LOADB=y
-# CONFIG_AML_MESON=1
-# CONFIG_AML_MESON_G12A=1
-# CONFIG_AML_MESON_GX=1
-# CONFIG_AML_MTD=y
-# CONFIG_AML_NAND=y
-CONFIG_AML_STORAGE=y
-# CONFIG_AML_PARTITION=y
-CONFIG_AML_SECURE_BOOT_V3=y
-CONFIG_AML_SECURE_UBOOT=y
-CONFIG_AML_SECURITY_KEY=y
-CONFIG_ANDROID_IMG=y
-CONFIG_BL2_COPY_NUM=4
-CONFIG_BOOTLOADER_CONTROL_BLOCK=y
-# CONFIG_CMD_BOOTCTOL_AVB=y
-CONFIG_BT_WAKEUP=y
-CONFIG_CEC_OSD_NAME="AML_TV"
-CONFIG_CEC_WAKEUP=y
-CONFIG_CMD_AML_MTEST=1
-CONFIG_CMD_DDR_D2PLL=0
-CONFIG_CMD_DDR_TEST=0
-CONFIG_CMD_VIU_PROBE=1
-CONFIG_CPU_CLK=1200
-CONFIG_DDR4_TIMING_TEST=0
-CONFIG_DDR_FULL_TEST=0
-CONFIG_DDR_LOW_POWER=0
-CONFIG_DDR_PLL_BYPASS=0
-# CONFIG_DDR_SIZE=0
-CONFIG_DDR_USE_EXT_VREF=0
-CONFIG_DDR_ZQ_PD=0
-CONFIG_DISCRETE_BOOTLOADER=y
-CONFIG_EFUSE=y
-CONFIG_MDUMP_COMPRESS=1
-# CONFIG_PLATFORM_POWER_INIT=y
-CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN=y
-CONFIG_RANDOM_ETHADDR=1
-CONFIG_SARADC_CH=2
-CONFIG_STORE_COMPATIBLE=y
-CONFIG_SYS_HUSH_PARSER=y
-CONFIG_SYS_NO_FLASH=y
-CONFIG_TPL_COPY_NUM=4
-CONFIG_TPL_PART_NAME="tpl"
-CONFIG_TPL_SIZE_PER_COPY=0x200000
-CONFIG_TXLX_USB=y
-CONFIG_USB_DEVICE_V2=y
-CONFIG_USB=y
-CONFIG_CMD_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_FASTBOOT=y
-CONFIG_CMD_FASTBOOT=y
-CONFIG_FASTBOOT_DWC_PCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DUALSPEED=y
-CONFIG_AML_V2_FACTORY_BURN=y
-CONFIG_USB_BURNING_TOOL=y
-CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
-CONFIG_SD_BURNING_SUPPORT_UI=y
-CONFIG_UNIFY_KEY_MANAGE=y
-CONFIG_SECURE_STORAGE=y
-CONFIG_VCCK_INIT_VOLTAGE=800
-# CONFIG_VDDEE_INIT_VOLTAGE=800
-# CONFIG_VDDEE_SLEEP_VOLTAGE=731
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_MESON=y
-CONFIG_DEBUG_UART_BASE=0xff803000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
-CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_CMD_D2PLL=n
-CONFIG_CMD_DDRTEST=n
-#CONFIG_MTD_UBI=y
-#CONFIG_MTD=y
-#CONFIG_NAND=y
-#CONFIG_MTD_DEVICE=y
-#CONFIG_CMD_MTDPARTS=y
-#CONFIG_AML_MTDPART=y
-#CONFIG_MTD_PARTITIONS=y
-CONFIG_DM=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_AML_SPICC=y
-CONFIG_PHY=y
-CONFIG_DM_USB=y
-CONFIG_AML_USB2_PHY=y
-CONFIG_AML_USB3_PHY=y
-CONFIG_AML_USB=y
-CONFIG_DM_ETH=y
-#CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_CMD_SF=y
-CONFIG_AML_SPIFC=y
-CONFIG_SPI_FLASH_WINBOND=y
-#CONFIG_SPI_FLASH_MTD=y
-#CONFIG_SPI_NAND=y
-CONFIG_CMD_RSVMEM=y
-CONFIG_CMD_REBOOT=y
-CONFIG_CMD_FACTORY_BOOT=y
-CONFIG_MMC_FTS=y
diff --git a/configs/g12b_w400_v1_defconfig b/configs/g12b_w400_v1_defconfig
deleted file mode 100644
index e2db37e..0000000
--- a/configs/g12b_w400_v1_defconfig
+++ /dev/null
@@ -1,179 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MESON=y
-CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_MESON_G12B=y
-CONFIG_TARGET_G12B_W400_V1=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_AML_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_MMC_HS200_SUPPORT=y
-CONFIG_MMC_MESON_GX=y
-# CONFIG_AML_GPIO=y
-CONFIG_SYS_PROMPT="g12b_w400_v1# "
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12b-a311d-w400"
-CONFIG_BOOTCOMMAND="run storeboot"
-CONFIG_BOOTDELAY=1
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_CPU_CLK=1200
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SPI=y
-CONFIG_CMD_SARADC=y
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ADC=y
-CONFIG_SARADC_MESON=y
-CONFIG_CLK=y
-CONFIG_CLK_MESON=y
-CONFIG_CLK_MESON_G12=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_MESON_G12A=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
-CONFIG_PWM_MESON=y
-CONFIG_ADC_POWER_KEY_CHAN=2
-CONFIG_ADC_POWER_KEY_VAL=0
-CONFIG_WDT=y
-CONFIG_WDT_MESON=y
-CONFIG_CMD_WATCHDOG=y
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MESON=y
-CONFIG_CMD_I2C=y
-# CONFIG_AML_BL33_COMPRESS_ENABLE=1
-CONFIG_AML_CRYPTO_UBOOT=1
-CONFIG_AML_CUSTOMER_ID=0
-CONFIG_AML_DRIVER=y
-CONFIG_AML_MEDIA=y
-CONFIG_AML_VPU=y
-CONFIG_AML_VPP=y
-CONFIG_AML_CANVAS=y
-CONFIG_AML_OSD=y
-CONFIG_CMD_BMP=y
-CONFIG_AML_VOUT=y
-CONFIG_AML_CVBS=y
-CONFIG_AML_HDMITX=y
-CONFIG_AML_LCD=y
-CONFIG_AML_LCD_TV=y
-CONFIG_AML_LCD_TABLET=y
-CONFIG_AML_LCD_EXTERN=y
-CONFIG_AML_BL_EXTERN=y
-CONFIG_NEED_BL301=y
-CONFIG_NEED_BL32=y
-CONFIG_FIP_IMG_SUPPORT=1
-CONFIG_SYS_LONGHELP=y
-CONFIG_CMD_MISC=y
-CONFIG_CMD_ITEST=y
-CONFIG_CMD_CPU_TEMP=1
-CONFIG_CMD_LOADB=y
-# CONFIG_AML_MESON=1
-# CONFIG_AML_MESON_G12A=1
-# CONFIG_AML_MESON_GX=1
-CONFIG_MESON_NFC=y
-#CONFIG_AML_MTD=1
-#CONFIG_AML_NAND=y
-CONFIG_AML_STORAGE=y
-CONFIG_AML_PARTITION=y
-CONFIG_AML_SECURE_BOOT_V3=1
-CONFIG_AML_SECURE_UBOOT=1
-CONFIG_AML_SECURITY_KEY=1
-CONFIG_BL2_COPY_NUM=4
-CONFIG_BOOTLOADER_CONTROL_BLOCK=y
-CONFIG_CMD_BOOTCTOL_AVB=y
-CONFIG_BT_WAKEUP=y
-CONFIG_CEC_OSD_NAME="AML_TV"
-CONFIG_CEC_WAKEUP=y
-CONFIG_CMD_SARADC=1
-CONFIG_CMD_VIU_PROBE=1
-CONFIG_CPU_CLK=1200
-CONFIG_DDR4_TIMING_TEST=0
-CONFIG_DDR_FULL_TEST=0
-CONFIG_DDR_LOW_POWER=0
-CONFIG_DDR_PLL_BYPASS=0
-# CONFIG_DDR_SIZE=0
-CONFIG_DDR_USE_EXT_VREF=0
-CONFIG_DDR_ZQ_PD=0
-CONFIG_DISCRETE_BOOTLOADER=y
-CONFIG_DTB_MEM_ADDR=0x1000000
-CONFIG_EFUSE=y
-CONFIG_MDUMP_COMPRESS=1
-# CONFIG_PLATFORM_POWER_INIT=y
-CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN=1
-CONFIG_RANDOM_ETHADDR=1
-CONFIG_SARADC_CH=2
-CONFIG_SD_BURNING_SUPPORT_UI=1
-CONFIG_STORE_COMPATIBLE=1
-CONFIG_SYS_HUSH_PARSER=y
-CONFIG_SYS_NO_FLASH=1
-CONFIG_TPL_COPY_NUM=4
-CONFIG_TPL_PART_NAME="tpl"
-CONFIG_TPL_SIZE_PER_COPY=0x200000
-CONFIG_TXLX_USB=1
-CONFIG_USB_DEVICE_V2=1
-CONFIG_USB=y
-CONFIG_CMD_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_FASTBOOT=y
-CONFIG_CMD_FASTBOOT=y
-CONFIG_FASTBOOT_DWC_PCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DUALSPEED=y
-CONFIG_AML_V2_FACTORY_BURN=y
-CONFIG_USB_BURNING_TOOL=y
-CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE=y
-CONFIG_SD_BURNING_SUPPORT_UI=y
-CONFIG_UNIFY_KEY_MANAGE=y
-CONFIG_SECURE_STORAGE=y
-CONFIG_VCCK_INIT_VOLTAGE=800
-# CONFIG_VDDEE_INIT_VOLTAGE=800
-# CONFIG_VDDEE_SLEEP_VOLTAGE=731
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_MESON=y
-CONFIG_DEBUG_UART_BASE=0xff803000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
-CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_CMD_D2PLL=n
-CONFIG_CMD_DDRTEST=n
-CONFIG_DM_MTD=y
-CONFIG_MTD_UBI=y
-#CONFIG_MTD=y
-CONFIG_NAND=y
-CONFIG_MTD_DEVICE=y
-CONFIG_CMD_MTDPARTS=y
-#CONFIG_AML_MTDPART=y
-CONFIG_MTD_PARTITIONS=y
-CONFIG_DM=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_AML_SPICC=y
-CONFIG_PHY=y
-CONFIG_DM_USB=y
-CONFIG_AML_USB2_PHY=y
-CONFIG_AML_USB3_PHY=y
-CONFIG_AML_USB=y
-CONFIG_DM_ETH=y
-#CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_CMD_SF=y
-CONFIG_AML_SPIFC=y
-CONFIG_SPI_FLASH_WINBOND=y
-#CONFIG_SPI_FLASH_MTD=y
-CONFIG_SPI_NAND=y
-CONFIG_CMD_RSVMEM=y
-CONFIG_AML_TSENSOR=y
-CONFIG_AML_TSENSOR_COOL=y
-CONFIG_AML_OSCRING=y
-CONFIG_CMD_EFUSE=y
-#CONFIG_CMD_DDR_D2PLL=y
-#CONFIG_CMD_DDR_TEST=y
diff --git a/configs/sm1_ac200_v1_defconfig b/configs/sm1_ac200_v1_defconfig
index 89d835d..52e0404 100644
--- a/configs/sm1_ac200_v1_defconfig
+++ b/configs/sm1_ac200_v1_defconfig
@@ -11,7 +11,7 @@
CONFIG_MMC_MESON_GX=y
# CONFIG_AML_GPIO=y
CONFIG_SYS_PROMPT="sm1_ac200_v1# "
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-s905d2-u200"
+CONFIG_DEFAULT_DEVICE_TREE="meson-sm1-s905d3-ac200"
CONFIG_BOOTCOMMAND="run storeboot"
CONFIG_BOOTDELAY=1
CONFIG_OF_BOARD_SETUP=y
diff --git a/configs/sm1_elaine_b1_defconfig b/configs/sm1_elaine_b1_defconfig
deleted file mode 100755
index b88a1fd..0000000
--- a/configs/sm1_elaine_b1_defconfig
+++ /dev/null
@@ -1,206 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MESON=y
-CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_MESON_G12A=y
-CONFIG_TARGET_SM1_ELAINE_B1=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_AML_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_MMC_MESON_GX=y
-# CONFIG_AML_GPIO=y
-CONFIG_SYS_PROMPT="sm1_elaine_b1# "
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-s905d3-elaine-b1"
-CONFIG_BOOTCOMMAND="run storeboot"
-CONFIG_BOOTDELAY=-2
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_CPU_CLK=1200
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SPI=n
-CONFIG_CMD_SARADC=n
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ADC=y
-CONFIG_SARADC_MESON=y
-# CONFIG_CLI_ENABLED is not set
-CONFIG_CLK=y
-CONFIG_CLK_MESON=y
-CONFIG_CLK_MESON_G12=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_MESON_G12A=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
-CONFIG_PWM_MESON=y
-CONFIG_ADC_POWER_KEY_CHAN=2
-CONFIG_ADC_POWER_KEY_VAL=0
-CONFIG_WDT=y
-CONFIG_WDT_MESON=y
-CONFIG_CMD_WATCHDOG=n
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MESON=y
-CONFIG_CMD_I2C=n
-# CONFIG_AML_BL33_COMPRESS_ENABLE=1
-CONFIG_AML_CRYPTO_UBOOT=y
-CONFIG_AML_CUSTOMER_ID=0
-CONFIG_AML_DRIVER=y
-CONFIG_AML_MEDIA=y
-CONFIG_AML_VPU=y
-CONFIG_AML_VPP=y
-CONFIG_AML_CANVAS=y
-CONFIG_AML_OSD=y
-CONFIG_CMD_BMP=y
-CONFIG_AML_VOUT=y
-CONFIG_AML_CVBS=n
-CONFIG_AML_HDMITX=n
-CONFIG_AML_LCD=y
-CONFIG_AML_LCD_TV=y
-CONFIG_AML_LCD_TABLET=y
-CONFIG_AML_LCD_EXTERN=y
-CONFIG_AML_BL_EXTERN=y
-CONFIG_NEED_BL301=y
-CONFIG_NEED_BL32=y
-CONFIG_FIP_IMG_SUPPORT=y
-CONFIG_SYS_LONGHELP=y
-CONFIG_CMD_MISC=n
-CONFIG_CMD_ITEST=y
-CONFIG_CMD_CPU_TEMP=y
-CONFIG_CMD_LOADB=n
-# CONFIG_AML_MESON=1
-# CONFIG_AML_MESON_G12A=1
-# CONFIG_AML_MESON_GX=1
-# CONFIG_AML_MTD=y
-# CONFIG_AML_NAND=y
-CONFIG_AML_STORAGE=y
-# CONFIG_AML_PARTITION=y
-CONFIG_AML_SECURE_BOOT_V3=y
-CONFIG_AML_SECURE_UBOOT=y
-CONFIG_AML_SECURITY_KEY=y
-CONFIG_IMG_SECURE_CHECK_SZ=66060288
-CONFIG_ANDROID_IMG=y
-CONFIG_BL2_COPY_NUM=4
-CONFIG_BOOTLOADER_CONTROL_BLOCK=y
-CONFIG_CMD_BOOTCTOL_AVB=y
-CONFIG_G_AB_SYSTEM=y
-CONFIG_BT_WAKEUP=y
-#CONFIG_CEC_OSD_NAME="AML_TV"
-CONFIG_CEC_WAKEUP=n
-CONFIG_CMD_AML_MTEST=1
-CONFIG_CMD_DDR_D2PLL=n
-CONFIG_CMD_DDR_TEST=n
-CONFIG_CMD_VIU_PROBE=1
-CONFIG_CPU_CLK=1200
-CONFIG_DDR4_TIMING_TEST=0
-CONFIG_DDR_FULL_TEST=0
-CONFIG_DDR_LOW_POWER=0
-CONFIG_DDR_PLL_BYPASS=0
-# CONFIG_DDR_SIZE=0
-CONFIG_DDR_USE_EXT_VREF=0
-CONFIG_DDR_ZQ_PD=0
-CONFIG_DISCRETE_BOOTLOADER=y
-CONFIG_EFUSE=y
-CONFIG_MDUMP_COMPRESS=1
-# CONFIG_PLATFORM_POWER_INIT=y
-CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN=y
-CONFIG_RANDOM_ETHADDR=1
-CONFIG_SARADC_CH=2
-CONFIG_STORE_COMPATIBLE=y
-CONFIG_SYS_HUSH_PARSER=y
-CONFIG_SYS_NO_FLASH=y
-CONFIG_TPL_COPY_NUM=4
-CONFIG_TPL_PART_NAME="tpl"
-CONFIG_TPL_SIZE_PER_COPY=0x200000
-CONFIG_TXLX_USB=y
-CONFIG_USB_DEVICE_V2=y
-CONFIG_USB=y
-CONFIG_CMD_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_FASTBOOT=y
-CONFIG_CMD_FASTBOOT=n
-CONFIG_FASTBOOT_DWC_PCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DUALSPEED=y
-CONFIG_UNIFY_KEY_MANAGE=y
-CONFIG_SECURE_STORAGE=y
-CONFIG_VCCK_INIT_VOLTAGE=800
-# CONFIG_VDDEE_INIT_VOLTAGE=800
-# CONFIG_VDDEE_SLEEP_VOLTAGE=731
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_MESON=y
-CONFIG_DEBUG_UART_BASE=0xff803000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
-CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_CMD_D2PLL=n
-CONFIG_CMD_DDRTEST=n
-#CONFIG_MTD_UBI=y
-#CONFIG_MTD=y
-#CONFIG_NAND=y
-#CONFIG_MTD_DEVICE=y
-#CONFIG_CMD_MTDPARTS=y
-#CONFIG_AML_MTDPART=y
-#CONFIG_MTD_PARTITIONS=y
-CONFIG_DM=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_AML_SPICC=y
-CONFIG_PHY=y
-CONFIG_DM_USB=y
-CONFIG_AML_USB2_PHY=y
-CONFIG_AML_USB3_PHY=y
-CONFIG_AML_USB=y
-CONFIG_DM_ETH=y
-#CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_CMD_SF=n
-CONFIG_AML_SPIFC=y
-CONFIG_SPI_FLASH_WINBOND=y
-#CONFIG_SPI_FLASH_MTD=y
-#CONFIG_SPI_NAND=y
-CONFIG_CMD_RSVMEM=n
-CONFIG_CMD_REBOOT=y
-CONFIG_CMD_FACTORY_BOOT=y
-CONFIG_MMC_FTS=y
-CONFIG_AML_TSENSOR=y
-CONFIG_AML_TSENSOR_COOL=y
-# CONFIG_AML_OSCRING=y
-#CONFIG_CMD_DDR_D2PLL=y
-CONFIG_CMD_DDR_TEST=y
-CONFIG_NOT_DTS_CONTROL_BL=y
-CONFIG_CMD_BOOTD=n
-CONFIG_CMD_BOOTI=n
-CONFIG_CMD_NET=n
-CONFIG_CMD_ELF=n
-CONFIG_CMD_MEMORY=n
-CONFIG_CMD_CONSOLE=n
-CONFIG_CMD_DM=n
-CONFIG_CMD_EDITENV=n
-CONFIG_CMD_FLASH=n
-CONFIG_CMD_GO=n
-CONFIG_CMD_UNZIP=n
-CONFIG_CMD_XIMG=n
-CONFIG_CMD_LZMADEC=n
-CONFIG_AML_RPMB_DISABLE=y
-CONFIG_CMD_SOURCE=n
-CONFIG_CMD_BOOTEFI=y
-CONFIG_CMD_PXE=n
-CONFIG_CMD_EXT2=n
-CONFIG_CMD_FS_GENERIC=n
-CONFIG_CMD_PART=n
-CONFIG_AML_CMD_OSD=y
-CONFIG_CMD_VOUT=y
-CONFIG_CMD_STORAGE=y
-CONFIG_ANDROID_BOOT_IMAGE=y
-CONFIG_LIBAVB=y
-CONFIG_AML_LCD_EXTERN_MIPI_P070ACB=y
-CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y
-CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y
diff --git a/configs/sm1_elaine_bx_defconfig b/configs/sm1_elaine_bx_defconfig
deleted file mode 100755
index 84abe03..0000000
--- a/configs/sm1_elaine_bx_defconfig
+++ /dev/null
@@ -1,206 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MESON=y
-CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_MESON_G12A=y
-CONFIG_TARGET_SM1_ELAINE_BX=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_AML_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_MMC_MESON_GX=y
-# CONFIG_AML_GPIO=y
-CONFIG_SYS_PROMPT="sm1_elaine_bx# "
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-s905d3-elaine-bx"
-CONFIG_BOOTCOMMAND="run storeboot"
-CONFIG_BOOTDELAY=-2
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_CPU_CLK=1200
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SPI=n
-CONFIG_CMD_SARADC=n
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ADC=y
-CONFIG_SARADC_MESON=y
-# CONFIG_CLI_ENABLED is not set
-CONFIG_CLK=y
-CONFIG_CLK_MESON=y
-CONFIG_CLK_MESON_G12=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_MESON_G12A=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
-CONFIG_PWM_MESON=y
-CONFIG_ADC_POWER_KEY_CHAN=2
-CONFIG_ADC_POWER_KEY_VAL=0
-CONFIG_WDT=y
-CONFIG_WDT_MESON=y
-CONFIG_CMD_WATCHDOG=n
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MESON=y
-CONFIG_CMD_I2C=n
-# CONFIG_AML_BL33_COMPRESS_ENABLE=1
-CONFIG_AML_CRYPTO_UBOOT=y
-CONFIG_AML_CUSTOMER_ID=0
-CONFIG_AML_DRIVER=y
-CONFIG_AML_MEDIA=y
-CONFIG_AML_VPU=y
-CONFIG_AML_VPP=y
-CONFIG_AML_CANVAS=y
-CONFIG_AML_OSD=y
-CONFIG_CMD_BMP=y
-CONFIG_AML_VOUT=y
-CONFIG_AML_CVBS=n
-CONFIG_AML_HDMITX=n
-CONFIG_AML_LCD=y
-CONFIG_AML_LCD_TV=y
-CONFIG_AML_LCD_TABLET=y
-CONFIG_AML_LCD_EXTERN=y
-CONFIG_AML_BL_EXTERN=y
-CONFIG_NEED_BL301=y
-CONFIG_NEED_BL32=y
-CONFIG_FIP_IMG_SUPPORT=y
-CONFIG_SYS_LONGHELP=y
-CONFIG_CMD_MISC=n
-CONFIG_CMD_ITEST=y
-CONFIG_CMD_CPU_TEMP=y
-CONFIG_CMD_LOADB=n
-# CONFIG_AML_MESON=1
-# CONFIG_AML_MESON_G12A=1
-# CONFIG_AML_MESON_GX=1
-# CONFIG_AML_MTD=y
-# CONFIG_AML_NAND=y
-CONFIG_AML_STORAGE=y
-# CONFIG_AML_PARTITION=y
-CONFIG_AML_SECURE_BOOT_V3=y
-CONFIG_AML_SECURE_UBOOT=y
-CONFIG_AML_SECURITY_KEY=y
-CONFIG_IMG_SECURE_CHECK_SZ=66060288
-CONFIG_ANDROID_IMG=y
-CONFIG_BL2_COPY_NUM=4
-CONFIG_BOOTLOADER_CONTROL_BLOCK=y
-CONFIG_CMD_BOOTCTOL_AVB=y
-CONFIG_G_AB_SYSTEM=y
-CONFIG_BT_WAKEUP=y
-#CONFIG_CEC_OSD_NAME="AML_TV"
-CONFIG_CEC_WAKEUP=n
-CONFIG_CMD_AML_MTEST=1
-CONFIG_CMD_DDR_D2PLL=n
-CONFIG_CMD_DDR_TEST=n
-CONFIG_CMD_VIU_PROBE=1
-CONFIG_CPU_CLK=1200
-CONFIG_DDR4_TIMING_TEST=0
-CONFIG_DDR_FULL_TEST=0
-CONFIG_DDR_LOW_POWER=0
-CONFIG_DDR_PLL_BYPASS=0
-# CONFIG_DDR_SIZE=0
-CONFIG_DDR_USE_EXT_VREF=0
-CONFIG_DDR_ZQ_PD=0
-CONFIG_DISCRETE_BOOTLOADER=y
-CONFIG_EFUSE=y
-CONFIG_MDUMP_COMPRESS=1
-# CONFIG_PLATFORM_POWER_INIT=y
-CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN=y
-CONFIG_RANDOM_ETHADDR=1
-CONFIG_SARADC_CH=2
-CONFIG_STORE_COMPATIBLE=y
-CONFIG_SYS_HUSH_PARSER=y
-CONFIG_SYS_NO_FLASH=y
-CONFIG_TPL_COPY_NUM=4
-CONFIG_TPL_PART_NAME="tpl"
-CONFIG_TPL_SIZE_PER_COPY=0x200000
-CONFIG_TXLX_USB=y
-CONFIG_USB_DEVICE_V2=y
-CONFIG_USB=y
-CONFIG_CMD_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_FASTBOOT=y
-CONFIG_CMD_FASTBOOT=n
-CONFIG_FASTBOOT_DWC_PCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DUALSPEED=y
-CONFIG_UNIFY_KEY_MANAGE=y
-CONFIG_SECURE_STORAGE=y
-CONFIG_VCCK_INIT_VOLTAGE=800
-# CONFIG_VDDEE_INIT_VOLTAGE=800
-# CONFIG_VDDEE_SLEEP_VOLTAGE=731
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_MESON=y
-CONFIG_DEBUG_UART_BASE=0xff803000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
-CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_CMD_D2PLL=n
-CONFIG_CMD_DDRTEST=n
-#CONFIG_MTD_UBI=y
-#CONFIG_MTD=y
-#CONFIG_NAND=y
-#CONFIG_MTD_DEVICE=y
-#CONFIG_CMD_MTDPARTS=y
-#CONFIG_AML_MTDPART=y
-#CONFIG_MTD_PARTITIONS=y
-CONFIG_DM=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_AML_SPICC=y
-CONFIG_PHY=y
-CONFIG_DM_USB=y
-CONFIG_AML_USB2_PHY=y
-CONFIG_AML_USB3_PHY=y
-CONFIG_AML_USB=y
-CONFIG_DM_ETH=y
-#CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_CMD_SF=n
-CONFIG_AML_SPIFC=y
-CONFIG_SPI_FLASH_WINBOND=y
-#CONFIG_SPI_FLASH_MTD=y
-#CONFIG_SPI_NAND=y
-CONFIG_CMD_RSVMEM=n
-CONFIG_CMD_REBOOT=y
-CONFIG_CMD_FACTORY_BOOT=y
-CONFIG_MMC_FTS=y
-CONFIG_AML_TSENSOR=y
-CONFIG_AML_TSENSOR_COOL=y
-# CONFIG_AML_OSCRING=y
-#CONFIG_CMD_DDR_D2PLL=y
-CONFIG_CMD_DDR_TEST=y
-CONFIG_NOT_DTS_CONTROL_BL=y
-CONFIG_CMD_BOOTD=n
-CONFIG_CMD_BOOTI=n
-CONFIG_CMD_NET=n
-CONFIG_CMD_ELF=n
-CONFIG_CMD_MEMORY=n
-CONFIG_CMD_CONSOLE=n
-CONFIG_CMD_DM=n
-CONFIG_CMD_EDITENV=n
-CONFIG_CMD_FLASH=n
-CONFIG_CMD_GO=n
-CONFIG_CMD_UNZIP=n
-CONFIG_CMD_XIMG=n
-CONFIG_CMD_LZMADEC=n
-CONFIG_AML_RPMB_DISABLE=y
-CONFIG_CMD_SOURCE=n
-CONFIG_CMD_BOOTEFI=y
-CONFIG_CMD_PXE=n
-CONFIG_CMD_EXT2=n
-CONFIG_CMD_FS_GENERIC=n
-CONFIG_CMD_PART=n
-CONFIG_AML_CMD_OSD=y
-CONFIG_CMD_VOUT=y
-CONFIG_CMD_STORAGE=y
-CONFIG_ANDROID_BOOT_IMAGE=y
-CONFIG_LIBAVB=y
-CONFIG_AML_LCD_EXTERN_MIPI_P070ACB=y
-CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y
-CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y
diff --git a/configs/sm1_elaine_p0_defconfig b/configs/sm1_elaine_p0_defconfig
deleted file mode 100755
index 1e11a82..0000000
--- a/configs/sm1_elaine_p0_defconfig
+++ /dev/null
@@ -1,205 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MESON=y
-CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_MESON_G12A=y
-CONFIG_TARGET_SM1_ELAINE_P0=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_AML_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_MMC_MESON_GX=y
-# CONFIG_AML_GPIO=y
-CONFIG_SYS_PROMPT="sm1_elaine_p0# "
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-s905d3-elaine-p0"
-CONFIG_BOOTCOMMAND="run storeboot"
-CONFIG_BOOTDELAY=1
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_CPU_CLK=1200
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SPI=n
-CONFIG_CMD_SARADC=n
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ADC=y
-CONFIG_SARADC_MESON=y
-CONFIG_CLK=y
-CONFIG_CLK_MESON=y
-CONFIG_CLK_MESON_G12=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_MESON_G12A=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
-CONFIG_PWM_MESON=y
-CONFIG_ADC_POWER_KEY_CHAN=2
-CONFIG_ADC_POWER_KEY_VAL=0
-CONFIG_WDT=y
-CONFIG_WDT_MESON=y
-CONFIG_CMD_WATCHDOG=n
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MESON=y
-CONFIG_CMD_I2C=n
-# CONFIG_AML_BL33_COMPRESS_ENABLE=1
-CONFIG_AML_CRYPTO_UBOOT=y
-CONFIG_AML_CUSTOMER_ID=0
-CONFIG_AML_DRIVER=y
-CONFIG_AML_MEDIA=y
-CONFIG_AML_VPU=y
-CONFIG_AML_VPP=y
-CONFIG_AML_CANVAS=y
-CONFIG_AML_OSD=y
-CONFIG_CMD_BMP=y
-CONFIG_AML_VOUT=y
-CONFIG_AML_CVBS=n
-CONFIG_AML_HDMITX=n
-CONFIG_AML_LCD=y
-CONFIG_AML_LCD_TV=y
-CONFIG_AML_LCD_TABLET=y
-CONFIG_AML_LCD_EXTERN=y
-CONFIG_AML_BL_EXTERN=y
-CONFIG_NEED_BL301=y
-CONFIG_NEED_BL32=y
-CONFIG_FIP_IMG_SUPPORT=y
-CONFIG_SYS_LONGHELP=y
-CONFIG_CMD_MISC=n
-CONFIG_CMD_ITEST=y
-CONFIG_CMD_CPU_TEMP=y
-CONFIG_CMD_LOADB=n
-# CONFIG_AML_MESON=1
-# CONFIG_AML_MESON_G12A=1
-# CONFIG_AML_MESON_GX=1
-# CONFIG_AML_MTD=y
-# CONFIG_AML_NAND=y
-CONFIG_AML_STORAGE=y
-# CONFIG_AML_PARTITION=y
-CONFIG_AML_SECURE_BOOT_V3=y
-CONFIG_AML_SECURE_UBOOT=y
-CONFIG_AML_SECURITY_KEY=y
-CONFIG_IMG_SECURE_CHECK_SZ=66060288
-CONFIG_ANDROID_IMG=y
-CONFIG_BL2_COPY_NUM=4
-CONFIG_BOOTLOADER_CONTROL_BLOCK=y
-CONFIG_CMD_BOOTCTOL_AVB=y
-CONFIG_BT_WAKEUP=y
-#CONFIG_CEC_OSD_NAME="AML_TV"
-CONFIG_CEC_WAKEUP=n
-CONFIG_CMD_AML_MTEST=1
-CONFIG_CMD_DDR_D2PLL=n
-CONFIG_CMD_DDR_TEST=n
-CONFIG_CMD_VIU_PROBE=1
-CONFIG_CPU_CLK=1200
-CONFIG_DDR4_TIMING_TEST=0
-CONFIG_DDR_FULL_TEST=0
-CONFIG_DDR_LOW_POWER=0
-CONFIG_DDR_PLL_BYPASS=0
-# CONFIG_DDR_SIZE=0
-CONFIG_DDR_USE_EXT_VREF=0
-CONFIG_DDR_ZQ_PD=0
-CONFIG_DISCRETE_BOOTLOADER=y
-CONFIG_EFUSE=y
-CONFIG_MDUMP_COMPRESS=1
-# CONFIG_PLATFORM_POWER_INIT=y
-CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN=y
-CONFIG_RANDOM_ETHADDR=1
-CONFIG_SARADC_CH=2
-CONFIG_STORE_COMPATIBLE=y
-CONFIG_SYS_HUSH_PARSER=y
-CONFIG_SYS_NO_FLASH=y
-CONFIG_TPL_COPY_NUM=4
-CONFIG_TPL_PART_NAME="tpl"
-CONFIG_TPL_SIZE_PER_COPY=0x200000
-CONFIG_TXLX_USB=y
-CONFIG_USB_DEVICE_V2=y
-CONFIG_USB=y
-CONFIG_CMD_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_FASTBOOT=y
-CONFIG_CMD_FASTBOOT=n
-CONFIG_FASTBOOT_DWC_PCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DUALSPEED=y
-CONFIG_UNIFY_KEY_MANAGE=y
-CONFIG_SECURE_STORAGE=y
-CONFIG_VCCK_INIT_VOLTAGE=800
-# CONFIG_VDDEE_INIT_VOLTAGE=800
-# CONFIG_VDDEE_SLEEP_VOLTAGE=731
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_MESON=y
-CONFIG_DEBUG_UART_BASE=0xff803000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
-CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_CMD_D2PLL=n
-CONFIG_CMD_DDRTEST=n
-#CONFIG_MTD_UBI=y
-#CONFIG_MTD=y
-#CONFIG_NAND=y
-#CONFIG_MTD_DEVICE=y
-#CONFIG_CMD_MTDPARTS=y
-#CONFIG_AML_MTDPART=y
-#CONFIG_MTD_PARTITIONS=y
-CONFIG_DM=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_AML_SPICC=y
-CONFIG_PHY=y
-CONFIG_DM_USB=y
-CONFIG_AML_USB2_PHY=y
-CONFIG_AML_USB3_PHY=y
-CONFIG_AML_USB=y
-CONFIG_DM_ETH=y
-#CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_CMD_SF=n
-CONFIG_AML_SPIFC=y
-CONFIG_SPI_FLASH_WINBOND=y
-#CONFIG_SPI_FLASH_MTD=y
-#CONFIG_SPI_NAND=y
-CONFIG_CMD_RSVMEM=n
-CONFIG_CMD_REBOOT=y
-CONFIG_CMD_FACTORY_BOOT=y
-CONFIG_MMC_FTS=y
-CONFIG_AML_TSENSOR=y
-CONFIG_AML_TSENSOR_COOL=y
-# CONFIG_AML_OSCRING=y
-#CONFIG_CMD_DDR_D2PLL=y
-CONFIG_CMD_DDR_TEST=y
-CONFIG_NOT_DTS_CONTROL_BL=y
-CONFIG_CMD_BOOTD=n
-CONFIG_CMD_BOOTI=n
-CONFIG_CMD_NET=n
-CONFIG_CMD_ELF=n
-CONFIG_CMD_MEMORY=n
-CONFIG_CMD_CONSOLE=n
-CONFIG_CMD_DM=n
-CONFIG_CMD_EDITENV=n
-CONFIG_CMD_FLASH=n
-CONFIG_CMD_GO=n
-CONFIG_CMD_UNZIP=n
-CONFIG_CMD_XIMG=n
-CONFIG_CMD_LZMADEC=n
-CONFIG_AML_RPMB_DISABLE=y
-CONFIG_CMD_SOURCE=n
-CONFIG_CMD_BOOTEFI=y
-CONFIG_CMD_PXE=n
-CONFIG_CMD_EXT2=n
-CONFIG_CMD_FS_GENERIC=n
-CONFIG_CMD_PART=n
-CONFIG_AML_CMD_OSD=y
-CONFIG_CMD_VOUT=y
-CONFIG_CMD_STORAGE=y
-CONFIG_ANDROID_BOOT_IMAGE=y
-CONFIG_LIBAVB=y
-CONFIG_AML_LCD_EXTERN_MIPI_P070ACB=y
-CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y
-CONFIG_LOGLEVEL=6
-CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y
diff --git a/configs/sm1_elaine_p1_defconfig b/configs/sm1_elaine_p1_defconfig
deleted file mode 100755
index 8e26b99..0000000
--- a/configs/sm1_elaine_p1_defconfig
+++ /dev/null
@@ -1,207 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MESON=y
-CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_MESON_G12A=y
-CONFIG_TARGET_SM1_ELAINE_P1=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_AML_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_MMC_MESON_GX=y
-# CONFIG_AML_GPIO=y
-CONFIG_SYS_PROMPT="sm1_elaine_p1# "
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-s905d3-elaine-p1"
-CONFIG_BOOTCOMMAND="run storeboot"
-CONFIG_BOOTDELAY=1
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_CPU_CLK=1200
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SPI=n
-CONFIG_CMD_SARADC=n
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ADC=y
-CONFIG_SARADC_MESON=y
-CONFIG_CLI_ENABLED=y
-CONFIG_CLK=y
-CONFIG_CLK_MESON=y
-CONFIG_CLK_MESON_G12=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_MESON_G12A=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
-CONFIG_PWM_MESON=y
-CONFIG_ADC_POWER_KEY_CHAN=2
-CONFIG_ADC_POWER_KEY_VAL=0
-CONFIG_WDT=y
-CONFIG_WDT_MESON=y
-CONFIG_CMD_WATCHDOG=n
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MESON=y
-CONFIG_CMD_I2C=n
-# CONFIG_AML_BL33_COMPRESS_ENABLE=1
-CONFIG_AML_CRYPTO_UBOOT=y
-CONFIG_AML_CUSTOMER_ID=0
-CONFIG_AML_DRIVER=y
-CONFIG_AML_MEDIA=y
-CONFIG_AML_VPU=y
-CONFIG_AML_VPP=y
-CONFIG_AML_CANVAS=y
-CONFIG_AML_OSD=y
-CONFIG_CMD_BMP=y
-CONFIG_AML_VOUT=y
-CONFIG_AML_CVBS=n
-CONFIG_AML_HDMITX=n
-CONFIG_AML_LCD=y
-CONFIG_AML_LCD_TV=y
-CONFIG_AML_LCD_TABLET=y
-CONFIG_AML_LCD_EXTERN=y
-CONFIG_AML_BL_EXTERN=y
-CONFIG_NEED_BL301=y
-CONFIG_NEED_BL32=y
-CONFIG_FIP_IMG_SUPPORT=y
-CONFIG_SYS_LONGHELP=y
-CONFIG_CMD_MISC=n
-CONFIG_CMD_ITEST=y
-CONFIG_CMD_CPU_TEMP=y
-CONFIG_CMD_LOADB=n
-# CONFIG_AML_MESON=1
-# CONFIG_AML_MESON_G12A=1
-# CONFIG_AML_MESON_GX=1
-# CONFIG_AML_MTD=y
-# CONFIG_AML_NAND=y
-CONFIG_AML_STORAGE=y
-# CONFIG_AML_PARTITION=y
-CONFIG_AML_SECURE_BOOT_V3=y
-CONFIG_AML_SECURE_UBOOT=y
-CONFIG_AML_SECURITY_KEY=y
-CONFIG_IMG_SECURE_CHECK_SZ=66060288
-CONFIG_ANDROID_IMG=y
-CONFIG_BL2_COPY_NUM=4
-CONFIG_BOOTLOADER_CONTROL_BLOCK=y
-CONFIG_CMD_BOOTCTOL_AVB=y
-CONFIG_G_AB_SYSTEM=y
-CONFIG_BT_WAKEUP=y
-#CONFIG_CEC_OSD_NAME="AML_TV"
-CONFIG_CEC_WAKEUP=n
-CONFIG_CMD_AML_MTEST=1
-CONFIG_CMD_DDR_D2PLL=n
-CONFIG_CMD_DDR_TEST=n
-CONFIG_CMD_VIU_PROBE=1
-CONFIG_CPU_CLK=1200
-CONFIG_DDR4_TIMING_TEST=0
-CONFIG_DDR_FULL_TEST=0
-CONFIG_DDR_LOW_POWER=0
-CONFIG_DDR_PLL_BYPASS=0
-# CONFIG_DDR_SIZE=0
-CONFIG_DDR_USE_EXT_VREF=0
-CONFIG_DDR_ZQ_PD=0
-CONFIG_DISCRETE_BOOTLOADER=y
-CONFIG_EFUSE=y
-CONFIG_MDUMP_COMPRESS=1
-# CONFIG_PLATFORM_POWER_INIT=y
-CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN=y
-CONFIG_RANDOM_ETHADDR=1
-CONFIG_SARADC_CH=2
-CONFIG_STORE_COMPATIBLE=y
-CONFIG_SYS_HUSH_PARSER=y
-CONFIG_SYS_NO_FLASH=y
-CONFIG_TPL_COPY_NUM=4
-CONFIG_TPL_PART_NAME="tpl"
-CONFIG_TPL_SIZE_PER_COPY=0x200000
-CONFIG_TXLX_USB=y
-CONFIG_USB_DEVICE_V2=y
-CONFIG_USB=y
-CONFIG_CMD_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_FASTBOOT=y
-CONFIG_CMD_FASTBOOT=n
-CONFIG_FASTBOOT_DWC_PCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DUALSPEED=y
-CONFIG_UNIFY_KEY_MANAGE=y
-CONFIG_SECURE_STORAGE=y
-CONFIG_VCCK_INIT_VOLTAGE=800
-# CONFIG_VDDEE_INIT_VOLTAGE=800
-# CONFIG_VDDEE_SLEEP_VOLTAGE=731
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_MESON=y
-CONFIG_DEBUG_UART_BASE=0xff803000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
-CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_CMD_D2PLL=n
-CONFIG_CMD_DDRTEST=n
-#CONFIG_MTD_UBI=y
-#CONFIG_MTD=y
-#CONFIG_NAND=y
-#CONFIG_MTD_DEVICE=y
-#CONFIG_CMD_MTDPARTS=y
-#CONFIG_AML_MTDPART=y
-#CONFIG_MTD_PARTITIONS=y
-CONFIG_DM=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_AML_SPICC=y
-CONFIG_PHY=y
-CONFIG_DM_USB=y
-CONFIG_AML_USB2_PHY=y
-CONFIG_AML_USB3_PHY=y
-CONFIG_AML_USB=y
-CONFIG_DM_ETH=y
-#CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_CMD_SF=n
-CONFIG_AML_SPIFC=y
-CONFIG_SPI_FLASH_WINBOND=y
-#CONFIG_SPI_FLASH_MTD=y
-#CONFIG_SPI_NAND=y
-CONFIG_CMD_RSVMEM=n
-CONFIG_CMD_REBOOT=y
-CONFIG_CMD_FACTORY_BOOT=y
-CONFIG_MMC_FTS=y
-CONFIG_AML_TSENSOR=y
-CONFIG_AML_TSENSOR_COOL=y
-# CONFIG_AML_OSCRING=y
-#CONFIG_CMD_DDR_D2PLL=y
-CONFIG_CMD_DDR_TEST=y
-CONFIG_NOT_DTS_CONTROL_BL=y
-CONFIG_CMD_BOOTD=n
-CONFIG_CMD_BOOTI=n
-CONFIG_CMD_NET=n
-CONFIG_CMD_ELF=n
-CONFIG_CMD_MEMORY=n
-CONFIG_CMD_CONSOLE=n
-CONFIG_CMD_DM=n
-CONFIG_CMD_EDITENV=n
-CONFIG_CMD_FLASH=n
-CONFIG_CMD_GO=n
-CONFIG_CMD_UNZIP=n
-CONFIG_CMD_XIMG=n
-CONFIG_CMD_LZMADEC=n
-CONFIG_AML_RPMB_DISABLE=y
-CONFIG_CMD_SOURCE=n
-CONFIG_CMD_BOOTEFI=y
-CONFIG_CMD_PXE=n
-CONFIG_CMD_EXT2=n
-CONFIG_CMD_FS_GENERIC=n
-CONFIG_CMD_PART=n
-CONFIG_AML_CMD_OSD=y
-CONFIG_CMD_VOUT=y
-CONFIG_CMD_STORAGE=y
-CONFIG_ANDROID_BOOT_IMAGE=y
-CONFIG_LIBAVB=y
-CONFIG_AML_LCD_EXTERN_MIPI_P070ACB=y
-CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y
-CONFIG_LOGLEVEL=6
-CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y
diff --git a/configs/sm1_elaine_p2_defconfig b/configs/sm1_elaine_p2_defconfig
deleted file mode 100755
index 38b2537..0000000
--- a/configs/sm1_elaine_p2_defconfig
+++ /dev/null
@@ -1,206 +0,0 @@
-CONFIG_ARM=y
-CONFIG_ARCH_MESON=y
-CONFIG_SYS_TEXT_BASE=0x01000000
-CONFIG_MESON_G12A=y
-CONFIG_TARGET_SM1_ELAINE_P2=y
-CONFIG_DM_GPIO=y
-CONFIG_DM_MMC=y
-CONFIG_AML_GPT=y
-CONFIG_CMD_MMC=y
-CONFIG_MMC_MESON_GX=y
-# CONFIG_AML_GPIO=y
-CONFIG_SYS_PROMPT="sm1_elaine_p2# "
-CONFIG_DEFAULT_DEVICE_TREE="meson-g12a-s905d3-elaine-p2"
-CONFIG_BOOTCOMMAND="run storeboot"
-CONFIG_BOOTDELAY=-2
-CONFIG_OF_BOARD_SETUP=y
-CONFIG_CPU_CLK=1200
-# CONFIG_DISPLAY_CPUINFO is not set
-# CONFIG_DISPLAY_BOARDINFO is not set
-# CONFIG_CMD_BDI is not set
-# CONFIG_CMD_IMI is not set
-CONFIG_CMD_GPIO=y
-# CONFIG_CMD_LOADS is not set
-CONFIG_CMD_SPI=n
-CONFIG_CMD_SARADC=n
-# CONFIG_CMD_SETEXPR is not set
-CONFIG_OF_CONTROL=y
-CONFIG_ADC=y
-CONFIG_SARADC_MESON=y
-CONFIG_CLI_ENABLED=y
-CONFIG_CLK=y
-CONFIG_CLK_MESON=y
-CONFIG_CLK_MESON_G12=y
-CONFIG_PINCTRL=y
-CONFIG_PINCONF=y
-CONFIG_PINCTRL_MESON_G12A=y
-CONFIG_DM_REGULATOR=y
-CONFIG_DM_PWM=y
-CONFIG_PWM_MESON=y
-CONFIG_ADC_POWER_KEY_CHAN=2
-CONFIG_ADC_POWER_KEY_VAL=0
-CONFIG_WDT=y
-CONFIG_WDT_MESON=y
-CONFIG_CMD_WATCHDOG=n
-CONFIG_DM_I2C=y
-CONFIG_SYS_I2C_MESON=y
-CONFIG_CMD_I2C=n
-# CONFIG_AML_BL33_COMPRESS_ENABLE=1
-CONFIG_AML_CRYPTO_UBOOT=y
-CONFIG_AML_CUSTOMER_ID=0
-CONFIG_AML_DRIVER=y
-CONFIG_AML_MEDIA=y
-CONFIG_AML_VPU=y
-CONFIG_AML_VPP=y
-CONFIG_AML_CANVAS=y
-CONFIG_AML_OSD=y
-CONFIG_CMD_BMP=y
-CONFIG_AML_VOUT=y
-CONFIG_AML_CVBS=n
-CONFIG_AML_HDMITX=n
-CONFIG_AML_LCD=y
-CONFIG_AML_LCD_TV=y
-CONFIG_AML_LCD_TABLET=y
-CONFIG_AML_LCD_EXTERN=y
-CONFIG_AML_BL_EXTERN=y
-CONFIG_NEED_BL301=y
-CONFIG_NEED_BL32=y
-CONFIG_FIP_IMG_SUPPORT=y
-CONFIG_SYS_LONGHELP=y
-CONFIG_CMD_MISC=n
-CONFIG_CMD_ITEST=y
-CONFIG_CMD_CPU_TEMP=y
-CONFIG_CMD_LOADB=n
-# CONFIG_AML_MESON=1
-# CONFIG_AML_MESON_G12A=1
-# CONFIG_AML_MESON_GX=1
-# CONFIG_AML_MTD=y
-# CONFIG_AML_NAND=y
-CONFIG_AML_STORAGE=y
-# CONFIG_AML_PARTITION=y
-CONFIG_AML_SECURE_BOOT_V3=y
-CONFIG_AML_SECURE_UBOOT=y
-CONFIG_AML_SECURITY_KEY=y
-CONFIG_IMG_SECURE_CHECK_SZ=66060288
-CONFIG_ANDROID_IMG=y
-CONFIG_BL2_COPY_NUM=4
-CONFIG_BOOTLOADER_CONTROL_BLOCK=y
-CONFIG_CMD_BOOTCTOL_AVB=y
-CONFIG_G_AB_SYSTEM=y
-CONFIG_BT_WAKEUP=y
-#CONFIG_CEC_OSD_NAME="AML_TV"
-CONFIG_CEC_WAKEUP=n
-CONFIG_CMD_AML_MTEST=1
-CONFIG_CMD_DDR_D2PLL=n
-CONFIG_CMD_DDR_TEST=n
-CONFIG_CMD_VIU_PROBE=1
-CONFIG_CPU_CLK=1200
-CONFIG_DDR4_TIMING_TEST=0
-CONFIG_DDR_FULL_TEST=0
-CONFIG_DDR_LOW_POWER=0
-CONFIG_DDR_PLL_BYPASS=0
-# CONFIG_DDR_SIZE=0
-CONFIG_DDR_USE_EXT_VREF=0
-CONFIG_DDR_ZQ_PD=0
-CONFIG_DISCRETE_BOOTLOADER=y
-CONFIG_EFUSE=y
-CONFIG_MDUMP_COMPRESS=1
-# CONFIG_PLATFORM_POWER_INIT=y
-CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN=y
-CONFIG_RANDOM_ETHADDR=1
-CONFIG_SARADC_CH=2
-CONFIG_STORE_COMPATIBLE=y
-CONFIG_SYS_HUSH_PARSER=y
-CONFIG_SYS_NO_FLASH=y
-CONFIG_TPL_COPY_NUM=4
-CONFIG_TPL_PART_NAME="tpl"
-CONFIG_TPL_SIZE_PER_COPY=0x200000
-CONFIG_TXLX_USB=y
-CONFIG_USB_DEVICE_V2=y
-CONFIG_USB=y
-CONFIG_CMD_USB=y
-CONFIG_USB_STORAGE=y
-CONFIG_USB_XHCI_HCD=y
-CONFIG_USB_XHCI_DWC3=y
-CONFIG_FASTBOOT=y
-CONFIG_CMD_FASTBOOT=n
-CONFIG_FASTBOOT_DWC_PCD=y
-CONFIG_USB_GADGET=y
-CONFIG_USB_GADGET_DUALSPEED=y
-CONFIG_UNIFY_KEY_MANAGE=y
-CONFIG_SECURE_STORAGE=y
-CONFIG_VCCK_INIT_VOLTAGE=800
-# CONFIG_VDDEE_INIT_VOLTAGE=800
-# CONFIG_VDDEE_SLEEP_VOLTAGE=731
-CONFIG_DEBUG_UART=y
-CONFIG_DEBUG_UART_MESON=y
-CONFIG_DEBUG_UART_BASE=0xff803000
-CONFIG_DEBUG_UART_CLOCK=24000000
-CONFIG_DEBUG_UART_ANNOUNCE=y
-CONFIG_DEBUG_UART_SKIP_INIT=y
-CONFIG_MESON_SERIAL=y
-CONFIG_OF_LIBFDT_OVERLAY=y
-CONFIG_CMD_D2PLL=n
-CONFIG_CMD_DDRTEST=n
-#CONFIG_MTD_UBI=y
-#CONFIG_MTD=y
-#CONFIG_NAND=y
-#CONFIG_MTD_DEVICE=y
-#CONFIG_CMD_MTDPARTS=y
-#CONFIG_AML_MTDPART=y
-#CONFIG_MTD_PARTITIONS=y
-CONFIG_DM=y
-CONFIG_SPI=y
-CONFIG_DM_SPI=y
-CONFIG_AML_SPICC=y
-CONFIG_PHY=y
-CONFIG_DM_USB=y
-CONFIG_AML_USB2_PHY=y
-CONFIG_AML_USB3_PHY=y
-CONFIG_AML_USB=y
-CONFIG_DM_ETH=y
-#CONFIG_SPI_FLASH=y
-CONFIG_DM_SPI_FLASH=y
-CONFIG_CMD_SF=n
-CONFIG_AML_SPIFC=y
-CONFIG_SPI_FLASH_WINBOND=y
-#CONFIG_SPI_FLASH_MTD=y
-#CONFIG_SPI_NAND=y
-CONFIG_CMD_RSVMEM=n
-CONFIG_CMD_REBOOT=y
-CONFIG_CMD_FACTORY_BOOT=y
-CONFIG_MMC_FTS=y
-CONFIG_AML_TSENSOR=y
-CONFIG_AML_TSENSOR_COOL=y
-# CONFIG_AML_OSCRING=y
-#CONFIG_CMD_DDR_D2PLL=y
-CONFIG_CMD_DDR_TEST=y
-CONFIG_NOT_DTS_CONTROL_BL=y
-CONFIG_CMD_BOOTD=n
-CONFIG_CMD_BOOTI=n
-CONFIG_CMD_NET=n
-CONFIG_CMD_ELF=n
-CONFIG_CMD_MEMORY=n
-CONFIG_CMD_CONSOLE=n
-CONFIG_CMD_DM=n
-CONFIG_CMD_EDITENV=n
-CONFIG_CMD_FLASH=n
-CONFIG_CMD_GO=n
-CONFIG_CMD_UNZIP=n
-CONFIG_CMD_XIMG=n
-CONFIG_CMD_LZMADEC=n
-CONFIG_AML_RPMB_DISABLE=y
-CONFIG_CMD_SOURCE=n
-CONFIG_CMD_BOOTEFI=y
-CONFIG_CMD_PXE=n
-CONFIG_CMD_EXT2=n
-CONFIG_CMD_FS_GENERIC=n
-CONFIG_CMD_PART=n
-CONFIG_AML_CMD_OSD=y
-CONFIG_CMD_VOUT=y
-CONFIG_CMD_STORAGE=y
-CONFIG_ANDROID_BOOT_IMAGE=y
-CONFIG_LIBAVB=y
-CONFIG_AML_LCD_EXTERN_MIPI_P070ACB=y
-CONFIG_AML_REMOVE_BOOTLOADER_PARTITION=y
-CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY=y
diff --git a/disk/Kconfig b/disk/Kconfig
index cfe7c08..408df7b 100644
--- a/disk/Kconfig
+++ b/disk/Kconfig
@@ -75,7 +75,6 @@
depends on PARTITIONS
default y if DISTRO_DEFAULTS
default y if TEGRA
- default y if AML_GPT
select LIB_UUID
help
Say Y here if you would like to use device under U-Boot which
@@ -133,7 +132,6 @@
bool "Enable support of GUID for partition type"
depends on PARTITIONS
depends on EFI_PARTITION
- default y if AML_GPT
help
Activate the configuration of GUID type
for EFI partition
@@ -148,8 +146,11 @@
config AML_GPT
bool "Enable AML GPT partition table"
depends on PARTITIONS
+ default y if AML_PARTITION
+ select RANDOM_UUID
+ select EFI_PARTITION
+ select PARTITION_TYPE_GUID
help
"AML_GPT_HELP"
endmenu
-
diff --git a/disk/part_aml.c b/disk/part_aml.c
index 42fc8d4..a456c3a 100644
--- a/disk/part_aml.c
+++ b/disk/part_aml.c
@@ -1,8 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2001
- * Yonghui.yu , Amlogic Inc, yonghui.yu@amlogic.com.
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
diff --git a/disk/part_dos.c b/disk/part_dos.c
index b26a33b..c25c3f0 100644
--- a/disk/part_dos.c
+++ b/disk/part_dos.c
@@ -23,11 +23,6 @@
#define DOS_PART_DEFAULT_SECTOR 512
-/* should this be configurable? It looks like it's not very common at all
- * to use large numbers of partitions
- */
-#define MAX_EXT_PARTS 256
-
/* Convert char[4] in little endian format to the host format integer
*/
static inline unsigned int le32_to_int(unsigned char *le32)
@@ -132,12 +127,6 @@
dos_partition_t *pt;
int i;
- /* set a maximum recursion level */
- if (part_num > MAX_EXT_PARTS) {
- printf("** Nested DOS partitions detected, stopping **\n");
- return;
- }
-
if (blk_dread(dev_desc, ext_part_sector, 1, (ulong *)buffer) != 1) {
printf ("** Can't read partition table on %d:" LBAFU " **\n",
dev_desc->devnum, ext_part_sector);
@@ -203,12 +192,6 @@
int i;
int dos_type;
- /* set a maximum recursion level */
- if (part_num > MAX_EXT_PARTS) {
- printf("** Nested DOS partitions detected, stopping **\n");
- return -1;
- }
-
if (blk_dread(dev_desc, ext_part_sector, 1, (ulong *)buffer) != 1) {
printf ("** Can't read partition table on %d:" LBAFU " **\n",
dev_desc->devnum, ext_part_sector);
diff --git a/disk/part_efi.c b/disk/part_efi.c
index 0fb8e8d..1cb8abe 100644
--- a/disk/part_efi.c
+++ b/disk/part_efi.c
@@ -19,6 +19,7 @@
#include <part_efi.h>
#include <linux/compiler.h>
#include <linux/ctype.h>
+#include <emmc_partitions.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -124,11 +125,13 @@
le64_to_cpu(gpt_h->first_usable_lba), lastlba);
return -1;
}
+#ifndef CONFIG_AML_GPT
if (le64_to_cpu(gpt_h->last_usable_lba) > lastlba) {
printf("GPT: last_usable_lba incorrect: %llX > " LBAF "\n",
le64_to_cpu(gpt_h->last_usable_lba), lastlba);
return -1;
}
+#endif
debug("GPT: first_usable_lba: %llX last_usable_lba: %llX last lba: "
LBAF "\n", le64_to_cpu(gpt_h->first_usable_lba),
@@ -336,8 +339,8 @@
ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, legacymbr, 1, dev_desc->blksz);
/* Read legacy MBR from block 0 and validate it */
- if ((blk_dread(dev_desc, 0, 1, (ulong *)legacymbr) != 1)
- || (is_pmbr_valid(legacymbr) != 1)) {
+ if ((blk_dread(dev_desc, 0, 1, (ulong *)legacymbr) != 1) ||
+ (is_pmbr_valid(legacymbr) != 1)) {
return -1;
}
return 0;
@@ -441,7 +444,6 @@
le64_to_cpu(gpt_h->last_usable_lba);
int i, k;
size_t efiname_len, dosname_len;
-#ifndef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY
#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
char *str_uuid;
unsigned char *bin_uuid;
@@ -450,7 +452,6 @@
char *str_type_guid;
unsigned char *bin_type_guid;
#endif
-#endif
size_t hdr_start = gpt_h->my_lba;
size_t hdr_end = hdr_start + 1;
@@ -495,31 +496,20 @@
gpt_e[i].ending_lba = cpu_to_le64(offset - 1);
#ifdef CONFIG_PARTITION_TYPE_GUID
-#ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY
- memcpy(gpt_e[i].partition_type_guid.b, partitions[i].partition_type_guid.b, sizeof(efi_guid_t));
-#else
str_type_guid = partitions[i].type_guid;
bin_type_guid = gpt_e[i].partition_type_guid.b;
if (strlen(str_type_guid)) {
if (uuid_str_to_bin(str_type_guid, bin_type_guid,
UUID_STR_FORMAT_GUID)) {
-#ifdef CONFIG_AML_GPT
- char str[8] = {"default"};
- strcpy(str_type_guid, str);
- uuid_str_to_bin(str_type_guid, bin_type_guid,
- UUID_STR_FORMAT_GUID);
-#else
printf("Partition no. %d: invalid type guid: %s\n",
i, str_type_guid);
return -1;
-#endif
}
} else {
/* default partition type GUID */
memcpy(bin_type_guid,
&partition_basic_data_guid, 16);
}
-#endif
#else
/* partition type GUID */
memcpy(gpt_e[i].partition_type_guid.b,
@@ -527,10 +517,6 @@
#endif
#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
-#ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY
- memcpy(gpt_e[i].unique_partition_guid.b,
- partitions[i].unique_partition_guid.b, sizeof(efi_guid_t));
-#else
str_uuid = partitions[i].uuid;
bin_uuid = gpt_e[i].unique_partition_guid.b;
@@ -540,19 +526,17 @@
return -1;
}
#endif
-#endif
/* partition attributes */
memset(&gpt_e[i].attributes, 0,
sizeof(gpt_entry_attributes));
-#ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY
- memcpy(&(gpt_e[i].attributes), &(partitions[i].attributes), sizeof(gpt_entry_attributes));
-#else
if (partitions[i].bootable)
gpt_e[i].attributes.fields.legacy_bios_bootable = 1;
-#endif
-
+ #ifdef CONFIG_ARCH_MESON
+ if (partitions[i].type[0])
+ gpt_e[i].attributes.fields.reserved = partitions[i].type[0];
+ #endif /* CONFIG_ARCH_MESON */
/* partition name */
efiname_len = sizeof(gpt_e[i].partition_name)
/ sizeof(efi_char16_t);
@@ -825,6 +809,70 @@
return 0;
}
+int erase_gpt_part_table(struct blk_desc *dev_desc)
+{
+ gpt_header *gpt_h;
+ int size;
+ lbaint_t lba;
+ int cnt;
+
+ printf("come to erase_gpt_part_table \n");
+
+ size = PAD_TO_BLOCKSIZE(sizeof(gpt_header), dev_desc);
+ gpt_h = malloc_cache_aligned(size);
+ if (gpt_h == NULL) {
+ printf("%s: calloc failed!\n", __func__);
+ return -1;
+ }
+ memset(gpt_h, 0, size);
+
+ /* Setup the Protective MBR */
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(legacy_mbr, p_mbr, 1, dev_desc->blksz);
+ if (p_mbr == NULL) {
+ printf("%s: calloc failed!\n", __func__);
+ free(gpt_h);
+ return -1;
+ }
+
+ /* Clear all data in MBR except of backed up boot code */
+ memset((char *)p_mbr + MSDOS_MBR_BOOT_CODE_SIZE, 0, sizeof(*p_mbr) -
+ MSDOS_MBR_BOOT_CODE_SIZE);
+
+ /* Write MBR sector to the MMC device */
+ if (blk_dwrite(dev_desc, 0, 1, p_mbr) != 1) {
+ printf("** Can't write to device %d **\n",
+ dev_desc->devnum);
+ free(gpt_h);
+ return -1;
+ }
+
+ /* write Primary GPT */
+ lba = GPT_PRIMARY_PARTITION_TABLE_LBA;
+ cnt = 1; /* GPT Header (1 block) */
+ printf("%s: erase '%s' (%d blks at 0x" LBAF ")\n",
+ __func__, "Primary GPT Header", cnt, lba);
+ if (blk_dwrite(dev_desc, lba, cnt, gpt_h) != cnt) {
+ printf("%s: failed erase '%s' (%d blks at 0x" LBAF ")\n",
+ __func__, "Primary GPT Header", cnt, lba);
+ free(gpt_h);
+ return 1;
+ }
+
+ lba = cpu_to_le64(dev_desc->lba - 1);
+ cnt = 1; /* GPT Header (1 block) */
+ printf("%s: erase '%s' (%d blks at 0x" LBAF ")\n",
+ __func__, "Backup GPT Header", cnt, lba);
+ if (blk_dwrite(dev_desc, lba, cnt, gpt_h) != cnt) {
+ printf("%s: failed erase '%s' (%d blks at 0x" LBAF ")\n",
+ __func__, "Backup GPT Header", cnt, lba);
+ free(gpt_h);
+ return 1;
+ }
+ gpt_partition = false;
+ free(gpt_h);
+ return 0;
+}
+
int write_mbr_and_gpt_partitions(struct blk_desc *dev_desc, void *buf)
{
gpt_header *gpt_h;
@@ -832,6 +880,12 @@
int gpt_e_blk_cnt;
lbaint_t lba;
int cnt;
+#ifdef CONFIG_AML_GPT
+ int i;
+ u32 calc_crc32;
+ u32 entries_num;
+ bool flag = false;
+#endif
if (is_valid_gpt_buf(dev_desc, buf))
return -1;
@@ -846,7 +900,39 @@
gpt_e_blk_cnt = BLOCK_CNT((le32_to_cpu(gpt_h->num_partition_entries) *
le32_to_cpu(gpt_h->sizeof_partition_entry)),
dev_desc);
+#ifdef CONFIG_AML_GPT
+ entries_num = le32_to_cpu(gpt_h->num_partition_entries);
+ if (le64_to_cpu(gpt_h->last_usable_lba) > dev_desc->lba) {
+ printf("GPT: last_usable_lba incorrect: %llX > " LBAF ", reset it\n",
+ le64_to_cpu(gpt_h->last_usable_lba), dev_desc->lba);
+ gpt_h->alternate_lba = cpu_to_le64(dev_desc->lba - 1);
+ gpt_h->last_usable_lba = cpu_to_le64(dev_desc->lba - 34);
+ flag = true;
+ }
+
+ for (i = 0; i < entries_num; i++) {
+ if (le64_to_cpu(gpt_e[i].ending_lba) > gpt_h->last_usable_lba) {
+ printf("gpt_e[%d].ending_lba: %llX > %llX, reset it\n",
+ i, le64_to_cpu(gpt_e[i].ending_lba), le64_to_cpu(gpt_h->last_usable_lba));
+ gpt_e[i].ending_lba = ((gpt_h->last_usable_lba >> 12) << 12) - 1;
+ printf("gpt_e[%d].ending_lba: %llX \n", i, gpt_e[i].ending_lba);
+ flag = true;
+ }
+ }
+
+ if (flag) {
+ calc_crc32 = efi_crc32((const unsigned char *)gpt_e,
+ entries_num * le32_to_cpu(gpt_h->sizeof_partition_entry));
+ gpt_h->partition_entry_array_crc32 = calc_crc32;
+
+ gpt_h->header_crc32 = 0;
+ calc_crc32 = efi_crc32((const unsigned char *)gpt_h,
+ le32_to_cpu(gpt_h->header_size));
+ gpt_h->header_crc32 = calc_crc32;
+ flag = false;
+ }
+#endif
/* write MBR */
lba = 0; /* MBR is always at 0 */
cnt = 1; /* MBR (1 block) */
@@ -1046,7 +1132,7 @@
blk = le64_to_cpu(pgpt_head->partition_entry_lba);
blk_cnt = BLOCK_CNT(count, dev_desc);
if (blk_dread(dev_desc, blk, (lbaint_t)blk_cnt, pte) != blk_cnt) {
- printf("*** ERROR: Can't read GPT Entries ***\n");
+ printf("*** ERROR: Can't read GPT Entries %lu***\n", blk_cnt);
free(pte);
return NULL;
}
diff --git a/doc/README.arm-relocation b/doc/README.arm-relocation
deleted file mode 100644
index d2a7e81..0000000
--- a/doc/README.arm-relocation
+++ /dev/null
@@ -1,193 +0,0 @@
-To make relocation on arm working, the following changes are done:
-
-At arch level: add linker flag -pie
-
- This causes the linker to generate fixup tables .rel.dyn and .dynsym,
- which must be applied to the relocated image before transferring
- control to it.
-
- These fixups are described in the ARM ELF documentation as type 23
- (program-base-relative) and 2 (symbol-relative)
-
-At cpu level: modify linker file and add a relocation and fixup loop
-
- the linker file must be modified to include the .rel.dyn and .dynsym
- tables in the binary image, and to provide symbols for the relocation
- code to access these tables
-
- The relocation and fixup loop must be executed after executing
- board_init_f at initial location and before executing board_init_r
- at final location.
-
-At board level:
-
- dram_init(): bd pointer is now at this point not accessible, so only
- detect the real dramsize, and store it in gd->ram_size. Bst detected
- with get_ram_size().
-
-TODO: move also dram initialization there on boards where it is possible.
-
- Setup of the the bd_t dram bank info is done in the new function
- dram_init_banksize() called after bd is accessible.
-
-At lib level:
-
- Board.c code is adapted from ppc code
-
-* WARNING ** WARNING ** WARNING ** WARNING ** WARNING ** WARNING ** WARNING *
-
-Boards which are not fixed to support relocation will be REMOVED!
-
------------------------------------------------------------------------------
-
-For boards which boot from spl, it is possible to save one copy
-if CONFIG_SYS_TEXT_BASE == relocation address! This prevents that uboot code
-is copied again in relocate_code().
-
-example for the tx25 board booting from NAND Flash:
-
-a) cpu starts
-b) it copies the first page in nand to internal ram
- (spl code)
-c) end executes this code
-d) this initialize CPU, RAM, ... and copy itself to RAM
- (this bin must fit in one page, so board_init_f()
- don;t fit in it ... )
-e) there it copy u-boot to CONFIG_SYS_NAND_U_BOOT_DST and
- starts this image @ CONFIG_SYS_NAND_U_BOOT_START
-f) u-boot code steps through board_init_f() and calculates
- the relocation address and copy itself to it
-
-If CONFIG_SYS_TEXT_BASE == relocation address, the copying of u-boot
-in f) could be saved.
-
------------------------------------------------------------------------------
-
-TODO
-
-- fill in bd_t infos (check)
-- adapt all boards
-
-- maybe adapt CONFIG_SYS_TEXT_BASE (this must be checked from board maintainers)
- This *must* be done for boards, which boot from NOR flash
-
- on other boards if CONFIG_SYS_TEXT_BASE = relocation baseaddr, this saves
- one copying from u-boot code.
-
-- new function dram_init_banksize() is actual board specific. Maybe
- we make a weak default function in arch/arm/lib/board.c ?
-
------------------------------------------------------------------------------
-
-Relocation with SPL (example for the tx25 booting from NAND Flash):
-
-- cpu copies the first page from NAND to 0xbb000000 (IMX_NFC_BASE)
- and start with code execution on this address.
-
-- The First page contains u-boot code from drivers/mtd/nand/raw/mxc_nand_spl.c
- which inits the dram, cpu registers, reloacte itself to CONFIG_SPL_TEXT_BASE and loads
- the "real" u-boot to CONFIG_SYS_NAND_U_BOOT_DST and starts execution
- @CONFIG_SYS_NAND_U_BOOT_START
-
-- This u-boot does no RAM init, nor CPU register setup. Just look
- where it has to copy and relocate itself to this address. If
- relocate address = CONFIG_SYS_TEXT_BASE (not the same, as the
- CONFIG_SPL_TEXT_BASE from the spl code), then there is no need
- to copy, just go on with bss clear and jump to board_init_r.
-
------------------------------------------------------------------------------
-
-How ELF relocations 23 and 2 work.
-
-TBC
-
--------------------------------------------------------------------------------------
-
-Debugging u-boot in RAM:
-(example on the qong board)
-
------------------
-
-a) start debugger
-
-arm-linux-gdb u-boot
-
-[hs@pollux u-boot]$ arm-linux-gdb u-boot
-GNU gdb Red Hat Linux (6.7-2rh)
-Copyright (C) 2007 Free Software Foundation, Inc.
-License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html>
-This is free software: you are free to change and redistribute it.
-There is NO WARRANTY, to the extent permitted by law. Type "show copying"
-and "show warranty" for details.
-This GDB was configured as "--host=i686-pc-linux-gnu --target=arm-linux".
-The target architecture is set automatically (currently arm)
-..
-(gdb)
-
------------------
-
-b) connect to target
-
-target remote bdi10:2001
-
-(gdb) target remote bdi10:2001
-Remote debugging using bdi10:2001
-0x8ff17f10 in ?? ()
-(gdb)
-
------------------
-
-c) discard symbol-file
-
-(gdb) symbol-file
-Discard symbol table from `/home/hs/celf/u-boot/u-boot'? (y or n) y
-No symbol file now.
-(gdb)
-
------------------
-
-d) load new symbol table:
-
-(gdb) add-symbol-file u-boot 0x8ff08000
-add symbol table from file "u-boot" at
- .text_addr = 0x8ff08000
-(y or n) y
-Reading symbols from /home/hs/celf/u-boot/u-boot...done.
-(gdb) c
-Continuing.
-^C
-Program received signal SIGSTOP, Stopped (signal).
-0x8ff17f18 in serial_getc () at serial_mxc.c:192
-192 while (__REG(UART_PHYS + UTS) & UTS_RXEMPTY);
-(gdb)
-
-add-symbol-file u-boot 0x8ff08000
- ^^^^^^^^^^
- get this address from u-boot bdinfo command
- or get it from gd->relocaddr in gdb
-
- => bdinfo
-rch_number = XXXXXXXXXX
-boot_params = XXXXXXXXXX
-DRAM bank = XXXXXXXXXX
--> start = XXXXXXXXXX
--> size = XXXXXXXXXX
-ethaddr = XXXXXXXXXX
-ip_addr = XXXXXXXXXX
-baudrate = XXXXXXXXXX
-TLB addr = XXXXXXXXXX
-relocaddr = 0x8ff08000
- ^^^^^^^^^^
-reloc off = XXXXXXXXXX
-irq_sp = XXXXXXXXXX
-sp start = XXXXXXXXXX
-FB base = XXXXXXXXXX
-
-or interrupt execution by any means and re-load the symbols at the location
-specified by gd->relocaddr -- this is only valid after board_init_f.
-
-(gdb) set $s = gd->relocaddr
-(gdb) symbol-file
-(gdb) add-symbol-file u-boot $s
-
-Now you can use gdb as usual :-)
diff --git a/drivers/Kconfig b/drivers/Kconfig
index ea17e37..7ec8962 100644
--- a/drivers/Kconfig
+++ b/drivers/Kconfig
@@ -137,4 +137,3 @@
functions in your platform's support code.
endmenu
-
diff --git a/drivers/Makefile b/drivers/Makefile
index 5d526fa..add5dd2 100644
--- a/drivers/Makefile
+++ b/drivers/Makefile
@@ -8,6 +8,7 @@
obj-$(CONFIG_$(SPL_TPL_)INPUT) += input/
obj-$(CONFIG_$(SPL_TPL_)LED) += led/
obj-$(CONFIG_$(SPL_TPL_)MMC_SUPPORT) += mmc/
+obj-$(CONFIG_$(SPL_TPL_)CMD_JTAG) += jtag/
obj-$(CONFIG_$(SPL_TPL_)NAND_SUPPORT) += mtd/nand/raw/
obj-$(CONFIG_$(SPL_TPL_)PCH_SUPPORT) += pch/
obj-$(CONFIG_$(SPL_TPL_)PCI) += pci/
@@ -24,10 +25,13 @@
obj-$(CONFIG_$(SPL_)REMOTEPROC) += remoteproc/
obj-$(CONFIG_$(SPL_TPL_)TPM) += tpm/
obj-$(CONFIG_AML_V2_FACTORY_BURN) += usb/gadget/v2_burning/
+obj-$(CONFIG_AML_V3_FACTORY_BURN) += usb/gadget/v3_burning/
obj-$(CONFIG_AML_NAND) += nand/
obj-$(CONFIG_AML_DRIVER) += amlogic/
obj-$(CONFIG_SPI_NAND) += mtd/nand/spi-nand/
-obj-$(CONFIG_MESON_NFC) += mtd/nand/aml_nand/
+obj-$(CONFIG_MESON_NFC) += mtd/nand/raw/aml_nand/
+obj-$(CONFIG_TYPEC) += usb/typec/
+obj-$(CONFIG_USB_ROLE_SWITCH) += usb/roles/
ifndef CONFIG_TPL_BUILD
ifdef CONFIG_SPL_BUILD
diff --git a/drivers/adc/Kconfig b/drivers/adc/Kconfig
index 2b16d83..d383ab1 100644
--- a/drivers/adc/Kconfig
+++ b/drivers/adc/Kconfig
@@ -30,10 +30,24 @@
- single and multi-channel conversion mode
config SARADC_MESON
- bool "Enable Amlogic Meson SARADC driver"
+ bool
imply REGMAP
+
+config SARADC_MESON_G12A
+ bool "Enable Amlogic Meson-G12A SARADC driver"
+ select SARADC_MESON
help
- This enables driver for Amlogic Meson SARADC.
+ This enables driver for Amlogic Meson-G12A SARADC.
+ It provides:
+ - 8 analog input channels
+ - 1O or 12 bits resolution
+ - Up to 1MSPS of sample rate
+
+config SARADC_MESON_C2
+ bool "Enable Amlogic Meson-C2 SARADC driver"
+ select SARADC_MESON
+ help
+ This enables driver for Amlogic Meson-C2 SARADC.
It provides:
- 8 analog input channels
- 1O or 12 bits resolution
@@ -63,13 +77,3 @@
- core driver to deal with common resources
- child driver to deal with individual ADC resources (declare ADC
device and associated channels, start/stop conversions)
-
-config SARADC_MESON
- bool "Enable MESON SARADC driver"
- depends on ADC
- help
- This enables driver for MESON SARADC.
- It provides:
- - 0~7 analog input channels
- - 10 or 12bit resolution
-
diff --git a/drivers/adc/Makefile b/drivers/adc/Makefile
index c1387f3..dcb5628 100644
--- a/drivers/adc/Makefile
+++ b/drivers/adc/Makefile
@@ -8,5 +8,7 @@
obj-$(CONFIG_ADC_EXYNOS) += exynos-adc.o
obj-$(CONFIG_ADC_SANDBOX) += sandbox.o
obj-$(CONFIG_SARADC_ROCKCHIP) += rockchip-saradc.o
-obj-$(CONFIG_SARADC_MESON) += meson-saradc.o
obj-$(CONFIG_STM32_ADC) += stm32-adc.o stm32-adc-core.o
+obj-$(CONFIG_SARADC_MESON) += meson-saradc.o
+obj-$(CONFIG_SARADC_MESON_C2) += meson-saradc-c2.o
+obj-$(CONFIG_SARADC_MESON_G12A) += meson-saradc-g12a.o
diff --git a/drivers/adc/meson-saradc-c2.c b/drivers/adc/meson-saradc-c2.c
new file mode 100644
index 0000000..88883fe
--- /dev/null
+++ b/drivers/adc/meson-saradc-c2.c
@@ -0,0 +1,166 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <dm.h>
+#include <amlogic/saradc.h>
+#include <asm/io.h>
+
+#define SARADC_C2_DISCARD_DATA_CNT 30
+#define SARADC_C2_SAVE_DATA_CNT 1
+
+#define SARADC_C2_FIFO_RD 0x18
+ #define SARADC_C2_FIFO_RD_CHAN_ID_SHIFT (22)
+ #define SARADC_C2_FIFO_RD_CHAN_ID_MASK GENMASK(24, 22)
+ #define SARADC_C2_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(21, 0)
+
+#define SARADC_C2_REG11 0x2c
+ #define SARADC_C2_REG11_CALIB_FACTOR_MASK GENMASK(18, 12)
+
+#define SARADC_C2_REG13 0x34
+ #define SARADC_C2_REG13_VREF_SEL BIT(19)
+
+#define SARADC_C2_CH0_CTRL1 0x4c
+ #define SARADC_C2_CH0_CTRL1_CHAN_MUX_SEL_MASK GENMASK(23, 21)
+ #define SARADC_C2_CH0_CTRL1_CHAN_MUX_SEL_SHIFT (21)
+ #define SARADC_C2_CH0_CTRL1_AUX_DIFF_EN BIT(17)
+ #define SARADC_C2_CH0_CTRL1_AUX_MODE_SEL BIT(0)
+
+#define SARADC_C2_CH0_CTRL2 0x50
+#define SARADC_C2_CH0_CTRL3 0x54
+
+/*
+ * bit[19] = 0 default; 0=vref_buf, 1=avdd
+ * bit[18] = 0 default; 0=vref_buf, 1=vcm_0p9
+ * bit[17] = 1 default; 1=differential; 0=single-ended
+ * bit[16] = 0 default; 0=vbg, 1=vcm_0p9
+ * bit[0] = 0 default; 0=new continuous mode; 1=normal mode
+ */
+static void meson_c2_enable_decim_filter(struct meson_saradc *priv, int ch,
+ unsigned int mode)
+{
+ int reg_off;
+
+ reg_off = ch * 12;
+ clrsetbits_le32(priv->base + SARADC_C2_CH0_CTRL1 + reg_off,
+ SARADC_C2_CH0_CTRL1_AUX_DIFF_EN, 0);
+
+ if (mode & ADC_CAPACITY_DECIM_FILTER) {
+ clrsetbits_le32(priv->base + SARADC_C2_CH0_CTRL1 + reg_off,
+ SARADC_C2_CH0_CTRL1_AUX_MODE_SEL,
+ 0);
+ } else {
+ clrsetbits_le32(priv->base + SARADC_C2_CH0_CTRL1 + reg_off,
+ SARADC_C2_CH0_CTRL1_AUX_MODE_SEL,
+ SARADC_C2_CH0_CTRL1_AUX_MODE_SEL);
+ }
+
+ writel(SARADC_C2_DISCARD_DATA_CNT, priv->base + SARADC_C2_CH0_CTRL2 + reg_off);
+ writel(SARADC_C2_SAVE_DATA_CNT, priv->base + SARADC_C2_CH0_CTRL3 + reg_off);
+}
+
+static void meson_c2_set_ref_voltage(struct meson_saradc *priv,
+ unsigned int mode)
+{
+ if (mode & ADC_CAPACITY_HIGH_PRECISION_VREF) {
+ if (readl(priv->base + SARADC_C2_REG11) &
+ SARADC_C2_REG11_CALIB_FACTOR_MASK) {
+ clrsetbits_le32(priv->base + SARADC_C2_REG13,
+ SARADC_C2_REG13_VREF_SEL,
+ SARADC_C2_REG13_VREF_SEL);
+ } else {
+ clrsetbits_le32(priv->base + SARADC_C2_REG13,
+ SARADC_C2_REG13_VREF_SEL,
+ 0);
+ pr_notice("calib factor is null,\
+ select the vdda as vref\n");
+ }
+ } else {
+ clrsetbits_le32(priv->base + SARADC_C2_REG13,
+ SARADC_C2_REG13_VREF_SEL,
+ SARADC_C2_REG13_VREF_SEL);
+ }
+}
+
+static void meson_c2_set_ch7_mux(struct meson_saradc *priv, int ch, int mux)
+{
+ clrsetbits_le32(priv->base + SARADC_C2_CH0_CTRL1 + ch * 12,
+ SARADC_C2_CH0_CTRL1_CHAN_MUX_SEL_MASK,
+ (mux & 0x7) << SARADC_C2_CH0_CTRL1_CHAN_MUX_SEL_SHIFT);
+}
+
+static int meson_c2_get_fifo_channel(int val)
+{
+ return (val >> SARADC_C2_FIFO_RD_CHAN_ID_SHIFT) & 0x7;
+}
+
+static int meson_c2_get_fifo_data(struct meson_saradc *priv,
+ struct adc_uclass_platdata *uc_pdata, int val)
+{
+ unsigned int data;
+
+ if (priv->current_mode & ADC_CAPACITY_DECIM_FILTER) {
+ /* return the 22-bit sampling value */
+ data = val & ((1 << SARADC_22BIT) - 1);
+
+ //check whether data is negative
+ if ((data >> (SARADC_22BIT - 1)) == 1)
+ data = data - (1 << SARADC_22BIT);
+ //convert to unsigned int
+ data = (data + (1 << (SARADC_22BIT - 1)));
+ } else {
+ /* return the 10-bit sampling value */
+ data = val & uc_pdata->data_mask;
+ if (priv->data->resolution == SARADC_12BIT)
+ data = data >> 2;
+ }
+
+ return data;
+}
+
+static struct meson_saradc_diff_ops meson_c2_diff_ops = {
+ .enable_decim_filter = meson_c2_enable_decim_filter,
+ .set_ref_voltage = meson_c2_set_ref_voltage,
+ .get_fifo_channel = meson_c2_get_fifo_channel,
+ .set_ch7_mux = meson_c2_set_ch7_mux,
+ .get_fifo_data = meson_c2_get_fifo_data,
+};
+
+struct meson_saradc_data meson_saradc_c2_data = {
+ .has_bl30_integration = true,
+ .self_test_channel = SARADC_CH_SELF_TEST,
+ .num_channels = MESON_SARADC_CH_MAX,
+ .resolution = SARADC_12BIT,
+ .dops = &meson_c2_diff_ops,
+ .capacity = ADC_CAPACITY_AVERAGE |
+ ADC_CAPACITY_HIGH_PRECISION_VREF |
+ ADC_CAPACITY_DECIM_FILTER,
+ /* There are 2 reasons for showing down saradc clock in C2:
+ * 1. To save cost, there is no input buffer before saradc.
+ * The value of inside resister of input source can not be too high.
+ * And resister value which can be tolerant is inversely of
+ * frequency of saradc clock.
+ * 2. The drive capability of channel 7 internal input is too weak.
+ */
+ .clock_rate = 600000,
+};
+
+static const struct udevice_id meson_c2_saradc_ids[] = {
+ {
+ .compatible = "amlogic,meson-c2-saradc",
+ .data = (ulong)&meson_saradc_c2_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(meson_c2_saradc) = {
+ .name = "meson_c2_saradc",
+ .id = UCLASS_ADC,
+ .of_match = meson_c2_saradc_ids,
+ .ops = &meson_saradc_ops,
+ .probe = meson_saradc_probe,
+ .remove = meson_saradc_remove,
+ .ofdata_to_platdata = meson_saradc_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct meson_saradc),
+};
diff --git a/drivers/adc/meson-saradc-g12a.c b/drivers/adc/meson-saradc-g12a.c
new file mode 100644
index 0000000..9667a32
--- /dev/null
+++ b/drivers/adc/meson-saradc-g12a.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <dm.h>
+#include <amlogic/saradc.h>
+#include <asm/io.h>
+
+#define SARADC_REG3 0x0c
+ #define SARADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
+ #define SARADC_REG3_CTRL_CHAN7_MUX_SEL_SHIFT (23)
+
+#define SARADC_FIFO_RD 0x18
+ #define SARADC_FIFO_RD_CHAN_ID_SHIFT (12)
+ #define SARADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
+ #define SARADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
+
+#define SARADC_REG11 0x2c
+ #define SARADC_REG11_VREF_SEL BIT(0)
+ #define SARADC_REG11_EOC BIT(1)
+ #define SARADC_REG11_VREF_EN BIT(5)
+ #define SARADC_REG11_CMV_SEL BIT(6)
+ #define SARADC_REG11_BANDGAP_EN BIT(13)
+ #define SARADC_REG11_TEMP_SEL BIT(21)
+
+#define SARADC_REG13 0x34
+ #define SARADC_REG13_CALIB_FACTOR_MASK GENMASK(13, 8)
+
+static void meson_g12a_extra_init(struct meson_saradc *priv)
+{
+ clrsetbits_le32(priv->base + SARADC_REG11,
+ SARADC_REG11_CMV_SEL |
+ SARADC_REG11_VREF_EN |
+ SARADC_REG11_EOC |
+ SARADC_REG11_BANDGAP_EN,
+ (priv->data->reg11_cmv_sel ?
+ SARADC_REG11_CMV_SEL : 0) |
+ (priv->data->reg11_vref_en ?
+ SARADC_REG11_VREF_EN : 0) |
+ (priv->data->reg11_eoc ?
+ SARADC_REG11_EOC : 0) |
+ SARADC_REG11_BANDGAP_EN);
+
+ /* select channel 6 input from temp sensor to external input */
+ clrsetbits_le32(priv->base + SARADC_REG11, SARADC_REG11_TEMP_SEL, 0);
+}
+
+static void meson_g12a_set_ref_voltage(struct meson_saradc *priv,
+ unsigned int mode)
+{
+ if (mode & ADC_CAPACITY_HIGH_PRECISION_VREF) {
+ if (readl(priv->base + SARADC_REG13) &
+ SARADC_REG13_CALIB_FACTOR_MASK) {
+ /* select the internal voltage as reference voltage */
+ clrsetbits_le32(priv->base + SARADC_REG11,
+ SARADC_REG11_VREF_SEL, 0);
+ } else {
+ /* select the VDDA as reference voltage */
+ clrsetbits_le32(priv->base + SARADC_REG11,
+ SARADC_REG11_VREF_SEL,
+ SARADC_REG11_VREF_SEL);
+
+ pr_notice("calib factor is null,\
+ select the vdda as vref\n");
+ }
+ } else {
+ /* select the VDDA as reference voltage */
+ clrsetbits_le32(priv->base + SARADC_REG11,
+ SARADC_REG11_VREF_SEL,
+ SARADC_REG11_VREF_SEL);
+ }
+
+
+}
+
+static int meson_g12a_get_fifo_channel(int val)
+{
+ return (val >> SARADC_FIFO_RD_CHAN_ID_SHIFT) & 0x7;
+}
+
+static void meson_g12a_set_ch7_mux(struct meson_saradc *priv, int ch, int mux)
+{
+ clrsetbits_le32(priv->base + SARADC_REG3,
+ SARADC_REG3_CTRL_CHAN7_MUX_SEL_MASK,
+ (mux & 0x7) << SARADC_REG3_CTRL_CHAN7_MUX_SEL_SHIFT);
+}
+
+static int meson_g12a_get_fifo_data(struct meson_saradc *priv,
+ struct adc_uclass_platdata *uc_pdata, int val)
+{
+ unsigned int data;
+
+ data = val & uc_pdata->data_mask;
+
+ /* return the 10-bit sampling value */
+ if (priv->data->resolution == SARADC_12BIT)
+ data = data >> 2;
+
+ return data;
+}
+
+static struct meson_saradc_diff_ops meson_g12a_diff_ops = {
+ .extra_init = meson_g12a_extra_init,
+ .set_ref_voltage = meson_g12a_set_ref_voltage,
+ .get_fifo_channel = meson_g12a_get_fifo_channel,
+ .set_ch7_mux = meson_g12a_set_ch7_mux,
+ .get_fifo_data = meson_g12a_get_fifo_data,
+};
+
+struct meson_saradc_data meson_saradc_g12a_data = {
+ .reg3_ring_counter_disable = BIT_HIGH,
+ .reg11_vref_en = BIT_LOW,
+ .reg11_cmv_sel = BIT_LOW,
+ .reg11_eoc = BIT_HIGH,
+ .has_bl30_integration = true,
+ .self_test_channel = SARADC_CH_SELF_TEST,
+ .num_channels = MESON_SARADC_CH_MAX,
+ .resolution = SARADC_12BIT,
+ .dops = &meson_g12a_diff_ops,
+ .capacity = ADC_CAPACITY_AVERAGE |
+ ADC_CAPACITY_HIGH_PRECISION_VREF,
+ .clock_rate = 1200000,
+};
+
+static const struct udevice_id meson_g12a_saradc_ids[] = {
+ {
+ .compatible = "amlogic,meson-g12a-saradc",
+ .data = (ulong)&meson_saradc_g12a_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(meson_g12a_saradc) = {
+ .name = "meson_g12a_saradc",
+ .id = UCLASS_ADC,
+ .of_match = meson_g12a_saradc_ids,
+ .ops = &meson_saradc_ops,
+ .probe = meson_saradc_probe,
+ .remove = meson_saradc_remove,
+ .ofdata_to_platdata = meson_saradc_ofdata_to_platdata,
+ .priv_auto_alloc_size = sizeof(struct meson_saradc),
+};
diff --git a/drivers/adc/meson-saradc.c b/drivers/adc/meson-saradc.c
index 70cd9a3..be24be3 100644
--- a/drivers/adc/meson-saradc.c
+++ b/drivers/adc/meson-saradc.c
@@ -10,175 +10,138 @@
#include <dm.h>
#include <errno.h>
#include <asm/io.h>
-#include <asm/arch/saradc.h>
+#include <amlogic/saradc.h>
+#include <clk.h>
#include <asm/arch/secure_apb.h>
-#define MESON_SAR_ADC_VDDA_VOLTAGE (1800000)
-#define MESON_SAR_ADC_TIMEOUT (100 * 1000)
-#define SAR_ADC_MAX_FIFO_SIZE 16
+#define MESON_SARADC_VDDA_VOLTAGE (1800000)
+#define MESON_SARADC_TIMEOUT (100 * 1000)
+#define SARADC_MAX_FIFO_SIZE 16
-#define SAR_CLK_BASE AO_SAR_CLK
- #define SAR_CLK_DIV_MASK GENMASK(7, 0)
- #define SAR_CLK_DIV_SHIFT (0)
- #define SAR_CLK_GATE BIT(8)
- #define SAR_CLK_MUX_MASK GENMASK(10, 9)
+#define SARADC_REG0 0x00
+ #define SARADC_REG0_BUSY_MASK GENMASK(30, 28)
+ #define SARADC_REG0_DELTA_BUSY BIT(30)
+ #define SARADC_REG0_AVG_BUSY BIT(29)
+ #define SARADC_REG0_SAMPLE_BUSY BIT(28)
+ #define SARADC_REG0_FIFO_FULL BIT(27)
+ #define SARADC_REG0_FIFO_EMPTY BIT(26)
+ #define SARADC_REG0_FIFO_COUNT_SHIFT (21)
+ #define SARADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
+ #define SARADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
+ #define SARADC_REG0_SAMPLING_STOP BIT(14)
+ #define SARADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
+ #define SARADC_REG0_FIFO_CNT_IRQ_SHIFT (4)
+ #define SARADC_REG0_FIFO_IRQ_EN BIT(3)
+ #define SARADC_REG0_SAMPLING_START BIT(2)
+ #define SARADC_REG0_CONTINUOUS_EN BIT(1)
+ #define SARADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
-#define SAR_ADC_REG0 0x00
- #define SAR_ADC_REG0_BUSY_MASK GENMASK(30, 28)
- #define SAR_ADC_REG0_DELTA_BUSY BIT(30)
- #define SAR_ADC_REG0_AVG_BUSY BIT(29)
- #define SAR_ADC_REG0_SAMPLE_BUSY BIT(28)
- #define SAR_ADC_REG0_FIFO_FULL BIT(27)
- #define SAR_ADC_REG0_FIFO_EMPTY BIT(26)
- #define SAR_ADC_REG0_FIFO_COUNT_SHIFT (21)
- #define SAR_ADC_REG0_FIFO_COUNT_MASK GENMASK(25, 21)
- #define SAR_ADC_REG0_CURR_CHAN_ID_MASK GENMASK(18, 16)
- #define SAR_ADC_REG0_SAMPLING_STOP BIT(14)
- #define SAR_ADC_REG0_FIFO_CNT_IRQ_MASK GENMASK(8, 4)
- #define SAR_ADC_REG0_FIFO_CNT_IRQ_SHIFT (4)
- #define SAR_ADC_REG0_FIFO_IRQ_EN BIT(3)
- #define SAR_ADC_REG0_SAMPLING_START BIT(2)
- #define SAR_ADC_REG0_CONTINUOUS_EN BIT(1)
- #define SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE BIT(0)
-
-#define SAR_ADC_CHAN_LIST 0x04
- #define SAR_ADC_CHAN_LIST_MAX_INDEX_SHIFT (24)
- #define SAR_ADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
- #define SAR_ADC_CHAN_LIST_ENTRY_SHIFT(_chan) (_chan * 3)
- #define SAR_ADC_CHAN_LIST_ENTRY_MASK(_chan) \
+#define SARADC_CHAN_LIST 0x04
+ #define SARADC_CHAN_LIST_MAX_INDEX_SHIFT (24)
+ #define SARADC_CHAN_LIST_MAX_INDEX_MASK GENMASK(26, 24)
+ #define SARADC_CHAN_LIST_ENTRY_SHIFT(_chan) (_chan * 3)
+ #define SARADC_CHAN_LIST_ENTRY_MASK(_chan) \
(GENMASK(2, 0) << ((_chan) * 3))
-#define SAR_ADC_AVG_CNTL 0x08
- #define SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
+#define SARADC_AVG_CNTL 0x08
+ #define SARADC_AVG_CNTL_AVG_MODE_SHIFT(_chan) \
(16 + ((_chan) * 2))
- #define SAR_ADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
+ #define SARADC_AVG_CNTL_AVG_MODE_MASK(_chan) \
(GENMASK(17, 16) << ((_chan) * 2))
- #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
+ #define SARADC_AVG_CNTL_NUM_SAMPLES_SHIFT(_chan) \
(0 + ((_chan) * 2))
- #define SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
+ #define SARADC_AVG_CNTL_NUM_SAMPLES_MASK(_chan) \
(GENMASK(1, 0) << ((_chan) * 2))
-#define SAR_ADC_REG3 0x0c
- #define SAR_ADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
- #define SAR_ADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
- #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK GENMASK(25, 23)
- #define SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_SHIFT (23)
- #define SAR_ADC_REG3_ADC_EN BIT(21)
- #define SAR_ADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
- #define SAR_ADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
+#define SARADC_REG3 0x0c
+ #define SARADC_REG3_CTRL_CONT_RING_COUNTER_EN BIT(27)
+ #define SARADC_REG3_CTRL_SAMPLING_CLOCK_PHASE BIT(26)
+ #define SARADC_REG3_ADC_EN BIT(21)
+ #define SARADC_REG3_BLOCK_DLY_SEL_MASK GENMASK(9, 8)
+ #define SARADC_REG3_BLOCK_DLY_MASK GENMASK(7, 0)
-#define SAR_ADC_DELAY 0x10
- #define SAR_ADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
- #define SAR_ADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
- #define SAR_ADC_DELAY_BL30_BUSY BIT(15)
- #define SAR_ADC_DELAY_KERNEL_BUSY BIT(14)
- #define SAR_ADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
- #define SAR_ADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
+#define SARADC_DELAY 0x10
+ #define SARADC_DELAY_INPUT_DLY_SEL_MASK GENMASK(25, 24)
+ #define SARADC_DELAY_INPUT_DLY_CNT_MASK GENMASK(23, 16)
+ #define SARADC_DELAY_BL30_BUSY BIT(15)
+ #define SARADC_DELAY_KERNEL_BUSY BIT(14)
+ #define SARADC_DELAY_SAMPLE_DLY_SEL_MASK GENMASK(9, 8)
+ #define SARADC_DELAY_SAMPLE_DLY_CNT_MASK GENMASK(7, 0)
-#define SAR_ADC_LAST_RD 0x14
+#define SARADC_LAST_RD 0x14
-#define SAR_ADC_FIFO_RD 0x18
- #define SAR_ADC_FIFO_RD_CHAN_ID_SHIFT (12)
- #define SAR_ADC_FIFO_RD_CHAN_ID_MASK GENMASK(14, 12)
- #define SAR_ADC_FIFO_RD_SAMPLE_VALUE_MASK GENMASK(11, 0)
+#define SARADC_FIFO_RD 0x18
-#define SAR_ADC_AUX_SW 0x1c
-#define SAR_ADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
+#define SARADC_AUX_SW 0x1c
+#define SARADC_AUX_SW_MUX_SEL_CHAN_MASK(_chan) \
(GENMASK(10, 8) << (((_chan) - 2) * 3))
-#define SAR_ADC_CHAN_10_SW 0x20
- #define SAR_ADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
- #define SAR_ADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
+#define SARADC_CHAN_10_SW 0x20
+ #define SARADC_CHAN_10_SW_CHAN1_MUX_SEL_MASK GENMASK(25, 23)
+ #define SARADC_CHAN_10_SW_CHAN0_MUX_SEL_MASK GENMASK(9, 7)
-#define SAR_ADC_DETECT_IDLE_SW 0x24
- #define SAR_ADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
- #define SAR_ADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
- #define SAR_ADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
+#define SARADC_DETECT_IDLE_SW 0x24
+ #define SARADC_DETECT_IDLE_SW_DETECT_SW_EN BIT(26)
+ #define SARADC_DETECT_IDLE_SW_DETECT_MUX_MASK GENMASK(25, 23)
+ #define SARADC_DETECT_IDLE_SW_IDLE_MUX_SEL_MASK GENMASK(9, 7)
-#define SAR_ADC_DELTA_10 0x28
+#define SARADC_DELTA_10 0x28
-#define SAR_ADC_REG11 0x2c
- #define SAR_ADC_REG11_VREF_SEL BIT(0)
- #define SAR_ADC_REG11_EOC BIT(1)
- #define SAR_ADC_REG11_VREF_EN BIT(5)
- #define SAR_ADC_REG11_CMV_SEL BIT(6)
- #define SAR_ADC_REG11_BANDGAP_EN BIT(13)
+static int meson_saradc_clk_init(struct udevice *dev)
+{
+ struct meson_saradc *priv = dev_get_priv(dev);
+ int ret;
-#define SAR_ADC_REG13 0x34
- #define SAR_ADC_REG13_CALIB_FACTOR_MASK GENMASK(13, 8)
+ ret = clk_get_by_name(dev, "xtal", &priv->xtal);
+ if (ret) {
+ pr_err("%s: failed to get xtal clk\n", dev->name);
+ return ret;
+ }
-enum MESON_SARADC_AVG_MODE {
- NO_AVERAGING = 0x0,
- MEAN_AVERAGING = 0x1,
- MEDIAN_AVERAGING = 0x2,
-};
+ ret = clk_get_by_name(dev, "adc_mux", &priv->adc_mux);
+ if (ret) {
+ pr_err("%s: failed to get adc_mux clk\n", dev->name);
+ return ret;
+ }
-enum MESON_SARADC_NUM_SAMPLES {
- ONE_SAMPLE = 0x0,
- TWO_SAMPLES = 0x1,
- FOUR_SAMPLES = 0x2,
- EIGHT_SAMPLES = 0x3,
-};
+ ret = clk_get_by_name(dev, "adc_div", &priv->adc_div);
+ if (ret) {
+ pr_err("%s: failed to get adc_div clk\n", dev->name);
+ return ret;
+ }
-enum MESON_SARADC_RESOLUTION {
- SARADC_10BIT = 10,
- SARADC_12BIT = 12,
-};
+ ret = clk_get_by_name(dev, "adc_gate", &priv->adc_gate);
+ if (ret) {
+ pr_err("%s: failed to get adc_gate\n", dev->name);
+ return ret;
+ }
-enum MESON_SARADC_BIT_STATE {
- BIT_LOW = 0,
- BIT_HIGH = 1,
-};
+ ret = clk_set_parent(&priv->adc_mux, &priv->xtal);
+ if (ret) {
+ pr_err("%s: failed to reparent adc clk\n", dev->name);
+ return ret;
+ }
-/*
- * struct meson_saradc_reg_diff - various information relative to registers
- *
- * @reg3_ring_counter_disable: to disable continuous ring counter.
- * gxl and later: 1; others(gxtvbb etc): 0
- * @reg11_vref_en: g12a and later: 0; others(axg etc): 1
- * @reg11_cmv_sel: g12a and later: 0; others(axg etc): 1
- */
-struct meson_saradc_reg_diff {
- bool reg3_ring_counter_disable;
- bool reg11_vref_en;
- bool reg11_cmv_sel;
- bool reg11_eoc;
-};
+ ret = clk_set_rate(&priv->adc_div, priv->data->clock_rate);
+ if (ret) {
+ pr_err("%s: failed to set rate\n", dev->name);
+ return ret;
+ }
-/*
- * struct meson_saradc_data - describe the differences of different platform
- *
- * @has_bl30_integration:
- * @num_channels: the number of adc channels
- * @self_test_channel: channel of self-test
- * @resolution: gxl and later: 12bit; others(gxtvbb etc): 10bit
- * @regs_diff: to describe the differences of the registers
- */
-struct meson_saradc_data {
- bool has_bl30_integration;
- unsigned char self_test_channel;
- unsigned char num_channels;
- unsigned int resolution;
- struct meson_saradc_reg_diff regs_diff;
-};
-
-struct meson_saradc {
- phys_addr_t base;
- int active_channel;
- struct meson_saradc_data *data;
-};
+ return 0;
+}
static void meson_saradc_hw_init(struct meson_saradc *priv)
{
/* create association between logic and physical channel */
- writel(0x03eb1a0c, priv->base + SAR_ADC_AUX_SW);
- writel(0x008c000c, priv->base + SAR_ADC_CHAN_10_SW);
+ writel(0x03eb1a0c, priv->base + SARADC_AUX_SW);
+ writel(0x008c000c, priv->base + SARADC_CHAN_10_SW);
/* disable all channels by default */
- writel(0x00000000, priv->base + SAR_ADC_CHAN_LIST);
+ writel(0x00000000, priv->base + SARADC_CHAN_LIST);
/* delay between two input/samples = (10 + 1) * 1us */
- writel(0x010a000a, priv->base + SAR_ADC_DELAY);
+ writel(0x010a000a, priv->base + SARADC_DELAY);
/*
* BIT[21]: disable the ADC by default
@@ -186,52 +149,38 @@
* BIT[26]: select the sampling clock period: 0:3T, 1:5T
* BIT[27]: disable ring counter
*/
- writel(0x0980000a, priv->base + SAR_ADC_REG3);
+ writel(0x0980000a, priv->base + SARADC_REG3);
/* disable continuous sampling mode */
- clrsetbits_le32(priv->base + SAR_ADC_REG0,
- SAR_ADC_REG0_CONTINUOUS_EN, 0);
-
- /* clock initialization: 1.2M=24M/(0x13 + 1) */
- clrsetbits_le32(SAR_CLK_BASE, SAR_CLK_DIV_MASK,
- 0x13 << SAR_CLK_DIV_SHIFT);
+ clrsetbits_le32(priv->base + SARADC_REG0,
+ SARADC_REG0_CONTINUOUS_EN, 0);
}
static void meson_saradc_hw_enable(struct meson_saradc *priv)
{
- clrsetbits_le32(priv->base + SAR_ADC_REG11,
- SAR_ADC_REG11_CMV_SEL |
- SAR_ADC_REG11_VREF_EN |
- SAR_ADC_REG11_BANDGAP_EN |
- SAR_ADC_REG11_EOC,
- (priv->data->regs_diff.reg11_cmv_sel ?
- SAR_ADC_REG11_CMV_SEL : 0) |
- (priv->data->regs_diff.reg11_vref_en ?
- SAR_ADC_REG11_VREF_EN : 0) |
- (priv->data->regs_diff.reg11_eoc ?
- SAR_ADC_REG11_EOC : 0) |
- SAR_ADC_REG11_BANDGAP_EN);
+ if (priv->data->dops->extra_init)
+ priv->data->dops->extra_init(priv);
- clrsetbits_le32(SAR_CLK_BASE, SAR_CLK_GATE, SAR_CLK_GATE);
+ clk_enable(&priv->adc_gate);
- clrsetbits_le32(priv->base + SAR_ADC_REG0,
- SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE,
- SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE);
+ clrsetbits_le32(priv->base + SARADC_REG0,
+ SARADC_REG0_SAMPLE_ENGINE_ENABLE,
+ SARADC_REG0_SAMPLE_ENGINE_ENABLE);
- clrsetbits_le32(priv->base + SAR_ADC_REG3,
- SAR_ADC_REG3_ADC_EN,
- SAR_ADC_REG3_ADC_EN);
+ clrsetbits_le32(priv->base + SARADC_REG3,
+ SARADC_REG3_ADC_EN,
+ SARADC_REG3_ADC_EN);
}
static void meson_saradc_hw_disable(struct meson_saradc *priv)
{
- clrsetbits_le32(priv->base + SAR_ADC_REG3,
- SAR_ADC_REG3_ADC_EN, 0);
+ clrsetbits_le32(priv->base + SARADC_REG3,
+ SARADC_REG3_ADC_EN, 0);
- clrsetbits_le32(priv->base + SAR_ADC_REG0,
- SAR_ADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
+ clrsetbits_le32(priv->base + SARADC_REG0,
+ SARADC_REG0_SAMPLE_ENGINE_ENABLE, 0);
- clrsetbits_le32(SAR_CLK_BASE, SAR_CLK_GATE, 0);
+ clk_disable(&priv->adc_gate);
}
static inline int meson_saradc_get_race_flag(struct meson_saradc *priv)
@@ -246,22 +195,22 @@
{
do {
udelay(1);
- val = readl(priv->base + SAR_ADC_DELAY);
- } while ((val & SAR_ADC_DELAY_BL30_BUSY) && timeout--);
+ val = readl(priv->base + SARADC_DELAY);
+ } while ((val & SARADC_DELAY_BL30_BUSY) && timeout--);
if (timeout < 0)
return -ETIMEDOUT;
/* prevent BL30 from using the SAR ADC while we are using it */
- clrsetbits_le32(priv->base + SAR_ADC_DELAY,
- SAR_ADC_DELAY_KERNEL_BUSY,
- SAR_ADC_DELAY_KERNEL_BUSY);
+ clrsetbits_le32(priv->base + SARADC_DELAY,
+ SARADC_DELAY_KERNEL_BUSY,
+ SARADC_DELAY_KERNEL_BUSY);
udelay(1);
- val = readl(priv->base + SAR_ADC_DELAY);
- if (val & SAR_ADC_DELAY_BL30_BUSY) {
- clrsetbits_le32(priv->base + SAR_ADC_DELAY,
- SAR_ADC_DELAY_KERNEL_BUSY, 0);
+ val = readl(priv->base + SARADC_DELAY);
+ if (val & SARADC_DELAY_BL30_BUSY) {
+ clrsetbits_le32(priv->base + SARADC_DELAY,
+ SARADC_DELAY_KERNEL_BUSY, 0);
return -ETIMEDOUT;
}
}
@@ -272,20 +221,20 @@
static inline void meson_saradc_put_race_flag(struct meson_saradc *priv)
{
if (priv->data->has_bl30_integration)
- clrsetbits_le32(priv->base + SAR_ADC_DELAY,
- SAR_ADC_DELAY_KERNEL_BUSY, 0);
+ clrsetbits_le32(priv->base + SARADC_DELAY,
+ SARADC_DELAY_KERNEL_BUSY, 0);
}
static inline void meson_saradc_enable_channel(struct meson_saradc *priv,
int ch, int idx)
{
- clrsetbits_le32(priv->base + SAR_ADC_CHAN_LIST,
- SAR_ADC_CHAN_LIST_MAX_INDEX_MASK,
- idx << SAR_ADC_CHAN_LIST_MAX_INDEX_SHIFT);
+ clrsetbits_le32(priv->base + SARADC_CHAN_LIST,
+ SARADC_CHAN_LIST_MAX_INDEX_MASK,
+ idx << SARADC_CHAN_LIST_MAX_INDEX_SHIFT);
- clrsetbits_le32(priv->base + SAR_ADC_CHAN_LIST,
- SAR_ADC_CHAN_LIST_ENTRY_MASK(idx),
- ch << SAR_ADC_CHAN_LIST_ENTRY_SHIFT(idx));
+ clrsetbits_le32(priv->base + SARADC_CHAN_LIST,
+ SARADC_CHAN_LIST_ENTRY_MASK(idx),
+ ch << SARADC_CHAN_LIST_ENTRY_SHIFT(idx));
}
@@ -294,65 +243,59 @@
int i;
for (i = 0; i < 32; i++) {
- if (!((readl(priv->base + SAR_ADC_REG0) >>
- SAR_ADC_REG0_FIFO_COUNT_SHIFT) & 0x1f))
+ if (!((readl(priv->base + SARADC_REG0) >>
+ SARADC_REG0_FIFO_COUNT_SHIFT) & 0x1f))
break;
- readl(priv->base + SAR_ADC_FIFO_RD);
+ readl(priv->base + SARADC_FIFO_RD);
}
}
static inline void meson_saradc_start_sample(struct meson_saradc *priv)
{
- clrsetbits_le32(priv->base + SAR_ADC_REG0,
- SAR_ADC_REG0_SAMPLING_START |
- SAR_ADC_REG0_SAMPLING_STOP,
- SAR_ADC_REG0_SAMPLING_START);
+ clrsetbits_le32(priv->base + SARADC_REG0,
+ SARADC_REG0_SAMPLING_START |
+ SARADC_REG0_SAMPLING_STOP,
+ SARADC_REG0_SAMPLING_START);
+}
+
+static int meson_saradc_check_mode(struct meson_saradc *priv, unsigned int mode)
+{
+ if (mode & ~priv->data->capacity)
+ return -EINVAL;
+
+ return 0;
}
static int meson_saradc_set_mode(struct udevice *dev, int ch, unsigned int mode)
{
+ int ret;
struct meson_saradc *priv = dev_get_priv(dev);
+ ret = meson_saradc_check_mode(priv, mode);
+ if (ret < 0)
+ return ret;
+
if (mode & ADC_CAPACITY_AVERAGE) {
- clrsetbits_le32(priv->base + SAR_ADC_AVG_CNTL,
- SAR_ADC_AVG_CNTL_NUM_SAMPLES_MASK(ch),
- EIGHT_SAMPLES << SAR_ADC_AVG_CNTL_NUM_SAMPLES_SHIFT(ch));
+ clrsetbits_le32(priv->base + SARADC_AVG_CNTL,
+ SARADC_AVG_CNTL_NUM_SAMPLES_MASK(ch),
+ EIGHT_SAMPLES << SARADC_AVG_CNTL_NUM_SAMPLES_SHIFT(ch));
- clrsetbits_le32(priv->base + SAR_ADC_AVG_CNTL,
- SAR_ADC_AVG_CNTL_AVG_MODE_MASK(ch),
- MEDIAN_AVERAGING << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(ch));
+ clrsetbits_le32(priv->base + SARADC_AVG_CNTL,
+ SARADC_AVG_CNTL_AVG_MODE_MASK(ch),
+ MEDIAN_AVERAGING << SARADC_AVG_CNTL_AVG_MODE_SHIFT(ch));
} else {
- clrsetbits_le32(priv->base + SAR_ADC_AVG_CNTL,
- SAR_ADC_AVG_CNTL_AVG_MODE_MASK(ch),
- NO_AVERAGING << SAR_ADC_AVG_CNTL_AVG_MODE_SHIFT(ch));
+ clrsetbits_le32(priv->base + SARADC_AVG_CNTL,
+ SARADC_AVG_CNTL_AVG_MODE_MASK(ch),
+ NO_AVERAGING << SARADC_AVG_CNTL_AVG_MODE_SHIFT(ch));
}
- /*
- * the precision of internal voltage is approximately equal to 10mv,
- * but the VDDA is approximately equal to 36mv(2% x 1800mv).
- */
- if (mode & ADC_CAPACITY_HIGH_PRECISION_VREF) {
- if (readl(priv->base + SAR_ADC_REG13) &
- SAR_ADC_REG13_CALIB_FACTOR_MASK) {
- /* select the internal voltage as reference voltage */
- clrsetbits_le32(priv->base + SAR_ADC_REG11,
- SAR_ADC_REG11_VREF_SEL, 0);
- } else {
- /* select the VDDA as reference voltage */
- clrsetbits_le32(priv->base + SAR_ADC_REG11,
- SAR_ADC_REG11_VREF_SEL,
- SAR_ADC_REG11_VREF_SEL);
+ priv->data->dops->set_ref_voltage(priv, mode);
- pr_notice("%s: calib factor is null, \
- please set it in bl30 first\n",
- dev->name);
- }
- } else {
- /* select the VDDA as reference voltage */
- clrsetbits_le32(priv->base + SAR_ADC_REG11,
- SAR_ADC_REG11_VREF_SEL,
- SAR_ADC_REG11_VREF_SEL);
- }
+ priv->current_mode = mode;
+
+ if (priv->data->dops->enable_decim_filter)
+ priv->data->dops->enable_decim_filter(priv, ch,
+ priv->current_mode);
return 0;
}
@@ -404,11 +347,12 @@
return -EINVAL;
}
- if (readl(priv->base + SAR_ADC_REG0) & SAR_ADC_REG0_BUSY_MASK)
+ if (readl(priv->base + SARADC_REG0) & SARADC_REG0_BUSY_MASK)
return -EBUSY;
- val = readl(priv->base + SAR_ADC_FIFO_RD);
- fifo_ch = (val >> SAR_ADC_FIFO_RD_CHAN_ID_SHIFT) & 0x7;
+ val = readl(priv->base + SARADC_FIFO_RD);
+
+ fifo_ch = priv->data->dops->get_fifo_channel(val);
if (fifo_ch != channel) {
pr_err("%s: channel mismatch: exp[%d] - act[%d]\n",
@@ -416,7 +360,7 @@
return -EINVAL;
}
- *data = val & uc_pdata->data_mask;
+ *data = priv->data->dops->get_fifo_data(priv, uc_pdata, val);
priv->active_channel = -1;
@@ -436,14 +380,12 @@
return -EINVAL;
}
- clrsetbits_le32(priv->base + SAR_ADC_REG3,
- SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_MASK,
- (mux & 0x7) << SAR_ADC_REG3_CTRL_CHAN7_MUX_SEL_SHIFT);
+ priv->data->dops->set_ch7_mux(priv, channel, mux);
return 0;
}
-static const struct adc_ops meson_saradc_ops = {
+const struct adc_ops meson_saradc_ops = {
.set_mode = meson_saradc_set_mode,
.start_channel = meson_saradc_start_channel,
.channel_data = meson_saradc_channel_data,
@@ -451,9 +393,10 @@
.select_input_voltage = meson_saradc_select_input_voltage,
};
-static int meson_saradc_probe(struct udevice *dev)
+int meson_saradc_probe(struct udevice *dev)
{
struct meson_saradc *priv = dev_get_priv(dev);
+ int ret;
priv->base = devfdt_get_addr(dev);
if (priv->base == FDT_ADDR_T_NONE) {
@@ -461,6 +404,10 @@
return -EINVAL;
}
+ ret = meson_saradc_clk_init(dev);
+ if (ret)
+ return ret;
+
priv->active_channel = -1;
meson_saradc_hw_init(priv);
@@ -470,7 +417,7 @@
return 0;
}
-static int meson_saradc_remove(struct udevice *dev)
+int meson_saradc_remove(struct udevice *dev)
{
struct meson_saradc *priv = dev_get_priv(dev);
@@ -479,7 +426,7 @@
return 0;
}
-static int meson_saradc_ofdata_to_platdata(struct udevice *dev)
+int meson_saradc_ofdata_to_platdata(struct udevice *dev)
{
struct adc_uclass_platdata *uc_pdata = dev_get_uclass_platdata(dev);
struct meson_saradc *priv = dev_get_priv(dev);
@@ -488,41 +435,9 @@
uc_pdata->data_mask = (1 << priv->data->resolution) - 1;
uc_pdata->data_format = ADC_DATA_FORMAT_BIN;
- uc_pdata->data_timeout_us = MESON_SAR_ADC_TIMEOUT;
+ uc_pdata->data_timeout_us = MESON_SARADC_TIMEOUT;
uc_pdata->channel_mask = (1 << priv->data->num_channels) - 1;
- uc_pdata->vdd_microvolts = MESON_SAR_ADC_VDDA_VOLTAGE;
+ uc_pdata->vdd_microvolts = MESON_SARADC_VDDA_VOLTAGE;
return 0;
}
-
-static struct meson_saradc_data meson_saradc_g12a_data = {
- .has_bl30_integration = true,
- .self_test_channel = SARADC_CH_SELF_TEST,
- .num_channels = MESON_SARADC_CH_MAX,
- .resolution = SARADC_12BIT,
- .regs_diff = {
- .reg3_ring_counter_disable = BIT_HIGH,
- .reg11_vref_en = BIT_LOW,
- .reg11_cmv_sel = BIT_LOW,
- .reg11_eoc = BIT_HIGH,
- },
-};
-
-static const struct udevice_id meson_saradc_ids[] = {
- {
- .compatible = "amlogic,meson-g12a-saradc",
- .data = (ulong)&meson_saradc_g12a_data,
- },
- { }
-};
-
-U_BOOT_DRIVER(meson_saradc) = {
- .name = "meson_saradc",
- .id = UCLASS_ADC,
- .of_match = meson_saradc_ids,
- .ops = &meson_saradc_ops,
- .probe = meson_saradc_probe,
- .remove = meson_saradc_remove,
- .ofdata_to_platdata = meson_saradc_ofdata_to_platdata,
- .priv_auto_alloc_size = sizeof(struct meson_saradc),
-};
diff --git a/drivers/amlogic/Kconfig b/drivers/amlogic/Kconfig
index 22d06ce..e072397 100644
--- a/drivers/amlogic/Kconfig
+++ b/drivers/amlogic/Kconfig
@@ -11,5 +11,11 @@
source "drivers/amlogic/storagekey/Kconfig"
-endmenu
+source "drivers/amlogic/power/Kconfig"
+source "drivers/amlogic/provision/Kconfig"
+
+source "drivers/amlogic/leds/Kconfig"
+
+source "drivers/amlogic/ir/Kconfig"
+endmenu
diff --git a/drivers/amlogic/Makefile b/drivers/amlogic/Makefile
index ecb0991..f5c87ed 100644
--- a/drivers/amlogic/Makefile
+++ b/drivers/amlogic/Makefile
@@ -5,3 +5,9 @@
obj-$(CONFIG_UNIFY_KEY_MANAGE) += keymanage/
obj-$(CONFIG_SECURE_STORAGE) += storagekey/
+
+obj-$(CONFIG_SECURE_POWER_CONTROL) += power/
+
+obj-$(CONFIG_MESON_LEDS_STATE_CONTROL) += leds/
+
+obj-$(CONFIG_MESON_IR) += ir/
diff --git a/drivers/amlogic/ir/Kconfig b/drivers/amlogic/ir/Kconfig
new file mode 100644
index 0000000..89fe08a
--- /dev/null
+++ b/drivers/amlogic/ir/Kconfig
@@ -0,0 +1,8 @@
+#
+#Amlogic IR Remote control drivers
+#
+config MESON_IR
+ tristate "Amlogic Meson IR remote control support"
+ default n
+ help
+ Say Y here if you want to use the Meson IR remote control.
diff --git a/drivers/amlogic/ir/Makefile b/drivers/amlogic/ir/Makefile
new file mode 100644
index 0000000..53efd9b
--- /dev/null
+++ b/drivers/amlogic/ir/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_MESON_IR) += ir.o regmap.o
+
diff --git a/drivers/amlogic/ir/ir.c b/drivers/amlogic/ir/ir.c
new file mode 100644
index 0000000..fb5d02b
--- /dev/null
+++ b/drivers/amlogic/ir/ir.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <dm.h>
+#include <misc.h>
+#include <errno.h>
+#include <dm/read.h>
+#include "ir.h"
+
+static int meson_ir_read(struct udevice *dev, int offset, void *buf, int size)
+{
+ int code;
+ int idx;
+ struct meson_ir_chip *chip = dev_get_priv(dev);
+
+ if (!buf)
+ return -EINVAL;
+
+ for (idx = 0; idx < chip->nr_contr; idx++) {
+ if (chip->ir_contr[idx].get_framecode) {
+ code = chip->ir_contr[idx].get_framecode(chip);
+ if (code) {
+ *(int *)buf = code;
+ return 0;
+ }
+ }
+ }
+
+ return -EINVAL;
+}
+
+static int meson_ir_probe(struct udevice *dev)
+{
+ int idx;
+ fdt_addr_t addr;
+ fdt_addr_t size;
+ struct meson_ir_chip *chip;
+
+ chip = dev_get_priv(dev);
+
+ chip->protocol = dev_read_u32_default(dev, "protocol", -EINVAL);
+ if (!chip->protocol) {
+ printf("failed to get protocol: %d\n", chip->protocol);
+ return -EINVAL;
+ }
+
+ chip->nr_contr = ENABLE_LEGACY_IR(chip->protocol) ? IR_ID_MAX : LEGACY_IR_ID;
+
+ for (idx = 0; idx < chip->nr_contr; idx++) {
+ addr = devfdt_get_addr_size_index(dev, idx, &size);
+ if (addr == FDT_ADDR_T_NONE) {
+ printf("failed to get address: %d\n", idx);
+ return -EINVAL;
+ }
+ chip->ir_contr[idx].base = (void __iomem *)addr;
+ }
+
+ return meson_ir_register_default_config(chip, chip->protocol);
+}
+
+static const struct misc_ops meson_ir_ops = {
+ .read = meson_ir_read,
+};
+
+static const struct udevice_id meson_ir_ids[] = {
+ { .compatible = "amlogic, aml_remote" },
+ { .compatible = "amlogic, meson-ir" },
+ {}
+};
+
+U_BOOT_DRIVER(meson_ir) = {
+ .name = "meson-ir",
+ .id = UCLASS_MISC,
+ .of_match = meson_ir_ids,
+ .ops = &meson_ir_ops,
+ .probe = meson_ir_probe,
+ .priv_auto_alloc_size = sizeof(struct meson_ir_chip),
+};
diff --git a/drivers/amlogic/ir/ir.h b/drivers/amlogic/ir/ir.h
new file mode 100644
index 0000000..d881a0c
--- /dev/null
+++ b/drivers/amlogic/ir/ir.h
@@ -0,0 +1,59 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <linux/bitops.h>
+#include <linux/io.h>
+
+enum MESON_IR_REG {
+ REG_LDR_ACTIVE = 0x00 << 2,
+ REG_LDR_IDLE = 0x01 << 2,
+ REG_LDR_REPEAT = 0x02 << 2,
+ REG_BIT_0 = 0x03 << 2,
+ REG_REG0 = 0x04 << 2,
+ REG_FRAME = 0x05 << 2,
+ REG_STATUS = 0x06 << 2,
+ REG_REG1 = 0x07 << 2,
+ REG_REG2 = 0x08 << 2,
+ REG_DURATN2 = 0x09 << 2,
+ REG_DURATN3 = 0x0a << 2,
+ REG_FRAME1 = 0x0b << 2,
+ REG_STATUS1 = 0x0c << 2,
+ REG_STATUS2 = 0x0d << 2,
+ REG_REG3 = 0x0e << 2,
+ REG_FRAME_RSV0 = 0x0f << 2,
+ REG_FRAME_RSV1 = 0x10 << 2,
+ REG_FILTE = 0x11 << 2,
+ REG_IRQ_CTL = 0x12 << 2,
+ REG_FIFO_CTL = 0x13 << 2,
+ REG_WIDTH_NEW = 0x14 << 2,
+ REG_REPEAT_DET = 0x15 << 2,
+};
+
+enum IR_CONTR_NUMBER {
+ MULTI_IR_ID = 0,
+ LEGACY_IR_ID,
+ IR_ID_MAX
+};
+
+struct meson_ir_chip;
+struct meson_ir_contr {
+ void __iomem *base;
+ int (*get_framecode)(struct meson_ir_chip *chip);
+};
+
+struct meson_ir_chip {
+ unsigned char nr_contr;
+ int protocol;
+ struct meson_ir_contr ir_contr[IR_ID_MAX];
+};
+
+#define MULTI_IR_TYPE_MASK(type) (type & 0xff) /*8bit*/
+#define LEGACY_IR_TYPE_MASK(type) ((type >> 8) & 0xff) /*8bit*/
+#define ENABLE_LEGACY_IR(type) (LEGACY_IR_TYPE_MASK(type) == 0xff)
+
+#define FRAME_STATUS_VALID BIT(3)
+#define FRAME_STATUS_REPEAT BIT(0)
+
+int meson_ir_register_default_config(struct meson_ir_chip *chip, int type);
diff --git a/drivers/amlogic/ir/regmap.c b/drivers/amlogic/ir/regmap.c
new file mode 100644
index 0000000..460e4ba
--- /dev/null
+++ b/drivers/amlogic/ir/regmap.c
@@ -0,0 +1,310 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <dm.h>
+#include <errno.h>
+#include <dt-bindings/input/meson_rc.h>
+#include "ir.h"
+
+struct meson_ir_reg_map {
+ unsigned int reg;
+ unsigned int val;
+};
+
+struct meson_ir_reg_proto {
+ int protocol;
+ int reg_map_size;
+ const char *name;
+ const struct meson_ir_reg_map *reg_map;
+ int (*get_framecode)(struct meson_ir_chip *chip);
+};
+
+static const struct meson_ir_reg_map regs_legacy_nec[] = {
+ {REG_LDR_ACTIVE, (500 << 16) | (400 << 0)},
+ {REG_LDR_IDLE, (300 << 16) | (200 << 0)},
+ {REG_LDR_REPEAT, (150 << 16) | (80 << 0)},
+ {REG_BIT_0, (72 << 16) | (40 << 0) },
+ {REG_REG0, (7 << 28) | (0xFA0 << 12) | 0x13},
+ {REG_STATUS, (134 << 20) | (90 << 10)},
+ {REG_REG1, 0xbe00}
+};
+
+static const struct meson_ir_reg_map regs_default_nec[] = {
+ {REG_LDR_ACTIVE, (500 << 16) | (400 << 0)},
+ {REG_LDR_IDLE, (300 << 16) | (200 << 0)},
+ {REG_LDR_REPEAT, (150 << 16) | (80 << 0)},
+ {REG_BIT_0, (72 << 16) | (40 << 0)},
+ {REG_REG0, (7 << 28) | (0xFA0 << 12) | 0x13},
+ {REG_STATUS, (134 << 20) | (90 << 10) | (1 << 30)},
+ {REG_REG1, 0x9f00},
+ {REG_REG2, 0x00},
+ {REG_DURATN2, 0x00},
+ {REG_DURATN3, 0x00},
+ {REG_IRQ_CTL, 0xCFA10BB8}
+};
+
+static const struct meson_ir_reg_map regs_default_duokan[] = {
+ {REG_LDR_ACTIVE, ((70 << 16) | (30 << 0))},
+ {REG_LDR_IDLE, ((50 << 16) | (15 << 0))},
+ {REG_LDR_REPEAT, ((30 << 16) | (26 << 0))},
+ {REG_BIT_0, ((66 << 16) | (40 << 0))},
+ {REG_REG0, ((3 << 28) | (0x4e2 << 12) | (0x13))},
+ {REG_STATUS, ((80 << 20) | (66 << 10))},
+ {REG_REG1, 0x9300},
+ {REG_REG2, 0xb90b},
+ {REG_DURATN2, ((97 << 16) | (80 << 0))},
+ {REG_DURATN3, ((120 << 16) | (97 << 0))},
+ {REG_REG3, 5000 << 0}
+};
+
+static const struct meson_ir_reg_map regs_default_xmp_1[] = {
+ {REG_LDR_ACTIVE, 0},
+ {REG_LDR_IDLE, 0},
+ {REG_LDR_REPEAT, 0},
+ {REG_BIT_0, (52 << 16) | (45 << 0)},
+ {REG_REG0, ((7 << 28) | (0x5DC << 12) | (0x13))},
+ {REG_STATUS, (87 << 20) | (80 << 10)},
+ {REG_REG1, 0x9f00},
+ {REG_REG2, 0xa90e},
+ /*n=10,758+137*10=2128us,2128/20= 106*/
+ {REG_DURATN2, (121 << 16) | (114 << 0)},
+ {REG_DURATN3, (7 << 16) | (7 << 0)},
+ {REG_REG3, 0}
+};
+
+static const struct meson_ir_reg_map regs_default_rc5[] = {
+ {REG_LDR_ACTIVE, 0},
+ {REG_LDR_IDLE, 0},
+ {REG_LDR_REPEAT, 0},
+ {REG_BIT_0, 0},
+ {REG_REG0, ((3 << 28) | (0x1644 << 12) | 0x13)},
+ {REG_STATUS, (1 << 30)},
+ {REG_REG1, ((1 << 15) | (13 << 8))},
+ /*bit[0-3]: RC5; bit[8]: MSB first mode; bit[11]: compare frame method*/
+ {REG_REG2, ((1 << 13) | (1 << 11) | (1 << 8) | 0x7)},
+ /*Half bit for RC5 format: 888.89us*/
+ {REG_DURATN2, ((49 << 16) | (40 << 0))},
+ /*RC5 typically 1777.78us for whole bit*/
+ {REG_DURATN3, ((94 << 16) | (83 << 0))},
+ {REG_REG3, 0}
+};
+
+static const struct meson_ir_reg_map regs_default_rc6[] = {
+ {REG_LDR_ACTIVE, (210 << 16) | (125 << 0)},
+ /*rc6 leader 4000us,200* timebase*/
+ {REG_LDR_IDLE, (50 << 16) | (38 << 0)}, /* leader idle 400*/
+ {REG_LDR_REPEAT, (145 << 16) | (125 << 0)}, /* leader repeat*/
+ /* logic '0' or '00' 1500us*/
+ {REG_BIT_0, (51 << 16) | (38 << 0) },
+ {REG_REG0, (7 << 28) | (0xFA0 << 12) | 0x13},
+ /* sys clock boby time.base time = 20 body frame*/
+ {REG_STATUS, (94 << 20) | (82 << 10)},
+ /*20bit:9440 32bit:9f40 36bit:a340 37bit:a440*/
+ {REG_REG1, 0xa440},
+ /*it may get the wrong customer value and key value from register if
+ *the value is set to 0x4,so the register value must set to 0x104
+ */
+ {REG_REG2, 0x2909},
+ {REG_DURATN2, ((28 << 16) | (16 << 0))},
+ {REG_DURATN3, ((51 << 16) | (38 << 0))}
+};
+
+static const struct meson_ir_reg_map regs_default_toshiba[] = {
+ {REG_LDR_ACTIVE, (280 << 16) | (180 << 0)},
+ {REG_LDR_IDLE, (280 << 16) | (180 << 0)},
+ {REG_LDR_REPEAT, (150 << 16) | (60 << 0)},
+ {REG_BIT_0, (72 << 16) | (40 << 0)},
+ {REG_REG0, (7 << 28) | (0xFA0 << 12) | 0x13},
+ {REG_STATUS, (134 << 20) | (90 << 10)},
+ {REG_REG1, 0x9f00},
+ {REG_REG2, 0x05 | (1 << 24) | (23 << 11)},
+ {REG_DURATN2, 0x00},
+ {REG_DURATN3, 0x00,},
+ {REG_REPEAT_DET, (1 << 31) | (0xFA0 << 16) | (10 << 0)},
+ {REG_REG3, 0x2AF8}
+};
+
+static struct meson_ir_reg_map regs_default_rca[] = {
+ {REG_LDR_ACTIVE, (250 << 16) | (160 << 0)},
+ {REG_LDR_IDLE, (250 << 16) | (160 << 0)},
+ {REG_LDR_REPEAT, (250 << 16) | (160 << 0)},
+ {REG_BIT_0, (100 << 16) | (48 << 0)},
+ {REG_REG0, (7 << 28) | (0xFA0 << 12) | 0x13},
+ {REG_STATUS, (150 << 20) | (110 << 10)},
+ {REG_REG1, 0x9700},
+ {REG_REG2, 0x104 | (1 << 24) | (23 << 11)},
+ {REG_DURATN2, 0x00},
+ {REG_REPEAT_DET, (1 << 31) | (0xFA0 << 16) | (10 << 0)},
+ {REG_REG3, 0x1A00},
+ {REG_DURATN3, 0x00}
+};
+
+static int meson_ir_get_framecode(struct meson_ir_chip *chip, unsigned char id)
+{
+ int status;
+
+ status = readl(chip->ir_contr[id].base + REG_STATUS);
+ if (status & FRAME_STATUS_VALID) {
+ if (status & FRAME_STATUS_REPEAT) {
+ readl(chip->ir_contr[id].base + REG_FRAME);
+ return 0;
+ }
+
+ return readl(chip->ir_contr[id].base + REG_FRAME);
+ }
+
+ return 0;
+}
+
+static int meson_legacy_ir_get_framecode_default(struct meson_ir_chip *chip)
+{
+ return meson_ir_get_framecode(chip, LEGACY_IR_ID);
+}
+
+static int meson_multi_ir_get_framecode_default(struct meson_ir_chip *chip)
+{
+ return meson_ir_get_framecode(chip, MULTI_IR_ID);
+}
+
+static const struct meson_ir_reg_proto reg_legacy_nec ={
+ .protocol = REMOTE_TYPE_LEGACY_NEC,
+ .name = "LEGACY_NEC",
+ .reg_map = regs_legacy_nec,
+ .reg_map_size = ARRAY_SIZE(regs_legacy_nec),
+ .get_framecode = meson_legacy_ir_get_framecode_default,
+};
+
+static const struct meson_ir_reg_proto reg_nec ={
+ .protocol = REMOTE_TYPE_NEC,
+ .name = "NEC",
+ .reg_map = regs_default_nec,
+ .reg_map_size = ARRAY_SIZE(regs_default_nec),
+ .get_framecode = meson_multi_ir_get_framecode_default,
+};
+
+static const struct meson_ir_reg_proto reg_duokan ={
+ .protocol = REMOTE_TYPE_DUOKAN,
+ .name = "DUOKAN",
+ .reg_map = regs_default_duokan,
+ .reg_map_size = ARRAY_SIZE(regs_default_duokan),
+ .get_framecode = meson_multi_ir_get_framecode_default,
+};
+
+static const struct meson_ir_reg_proto reg_xmp_1 ={
+ .protocol = REMOTE_TYPE_XMP_1,
+ .name = "XMP_1",
+ .reg_map = regs_default_xmp_1,
+ .reg_map_size = ARRAY_SIZE(regs_default_xmp_1),
+ .get_framecode = meson_multi_ir_get_framecode_default,
+};
+
+static const struct meson_ir_reg_proto reg_rc5 ={
+ .protocol = REMOTE_TYPE_RC5,
+ .name = "RC5",
+ .reg_map = regs_default_rc5,
+ .reg_map_size = ARRAY_SIZE(regs_default_rc5),
+ .get_framecode = meson_multi_ir_get_framecode_default,
+};
+
+static const struct meson_ir_reg_proto reg_rc6 ={
+ .protocol = REMOTE_TYPE_RC6,
+ .name = "RC6",
+ .reg_map = regs_default_rc6,
+ .reg_map_size = ARRAY_SIZE(regs_default_rc6),
+};
+
+static const struct meson_ir_reg_proto reg_toshiba ={
+ .protocol = REMOTE_TYPE_TOSHIBA,
+ .name = "toshiba",
+ .reg_map = regs_default_toshiba,
+ .reg_map_size = ARRAY_SIZE(regs_default_toshiba),
+ .get_framecode = meson_multi_ir_get_framecode_default,
+};
+
+static const struct meson_ir_reg_proto reg_rca ={
+ .protocol = REMOTE_TYPE_RCA,
+ .name = "RCA",
+ .reg_map = regs_default_rca,
+ .reg_map_size = ARRAY_SIZE(regs_default_rca),
+ .get_framecode = meson_multi_ir_get_framecode_default,
+};
+
+static const struct meson_ir_reg_proto *meson_ir_regs_proto[] = {
+ ®_nec,
+ ®_duokan,
+ ®_rc5,
+ ®_rc6,
+ ®_toshiba,
+ ®_rca,
+ ®_xmp_1,
+ ®_legacy_nec,
+ NULL
+};
+
+static int meson_ir_contr_init(struct meson_ir_chip *chip, int type, unsigned char id)
+{
+ const struct meson_ir_reg_proto **reg_proto = meson_ir_regs_proto;
+ const struct meson_ir_reg_map *regmap;
+ int size;
+
+ for (; (*reg_proto) != NULL ; ) {
+ if ((*reg_proto)->protocol == type)
+ break;
+ reg_proto++;
+ }
+
+ if (!(*reg_proto)) {
+ printf("%s: invalid protocol type: %d\n", __func__, type);
+ return -EINVAL;
+ }
+
+ readl(chip->ir_contr[id].base + REG_STATUS);
+ readl(chip->ir_contr[id].base + REG_FRAME);
+
+ /*
+ * reset ir decoder and disable the state machine
+ * of IR decoder.
+ * [15] = 0 ,disable the machine of IR decoder
+ * [0] = 0x01,set to 1 to reset the IR decoder
+ */
+ regmap = (*reg_proto)->reg_map;
+ size = (*reg_proto)->reg_map_size;
+
+ for ( ; size > 0; ) {
+ writel(regmap->val, chip->ir_contr[id].base + regmap->reg);
+ size--;
+ regmap++;
+ }
+
+ /*
+ * when we reinstall remote controller register,
+ * we need reset IR decoder, set 1 to REG_REG1 bit0,
+ * after IR decoder reset, we need to clear the bit0
+ */
+ writel(readl(chip->ir_contr[id].base + REG_REG1) | BIT(0),
+ chip->ir_contr[id].base + REG_REG1);
+ writel(readl(chip->ir_contr[id].base + REG_REG1) & (~BIT(0)),
+ chip->ir_contr[id].base + REG_REG1);
+
+ chip->ir_contr[id].get_framecode = (*reg_proto)->get_framecode;
+
+ return 0;
+}
+
+int meson_ir_register_default_config(struct meson_ir_chip *chip, int type)
+{
+ if (ENABLE_LEGACY_IR(type)) {
+ /*initialize registers for legacy IR controller*/
+ meson_ir_contr_init(chip, LEGACY_IR_TYPE_MASK(type),
+ LEGACY_IR_ID);
+ } else {
+ /*disable legacy IR controller: REG_REG1[15]*/
+ writel(0x0, chip->ir_contr[LEGACY_IR_ID].base + REG_REG1);
+ }
+ /*initialize registers for Multi-format IR controller*/
+ meson_ir_contr_init(chip, MULTI_IR_TYPE_MASK(type), MULTI_IR_ID);
+
+ return 0;
+}
diff --git a/drivers/amlogic/keymanage/Kconfig b/drivers/amlogic/keymanage/Kconfig
index 1269717..0074ef2 100644
--- a/drivers/amlogic/keymanage/Kconfig
+++ b/drivers/amlogic/keymanage/Kconfig
@@ -12,5 +12,9 @@
select SHA256
help
"security key wrapper for APIs bl31"
+ config KEYMAN_PROVISION_KEY
+ bool "Amlogic burn provision key"
+ default y
+ help
+ "provision key wrapper for burn tool"
endif #if UNIFY_KEY_MANAGE
-
diff --git a/drivers/amlogic/keymanage/Makefile b/drivers/amlogic/keymanage/Makefile
index b54587f..08dd44e 100644
--- a/drivers/amlogic/keymanage/Makefile
+++ b/drivers/amlogic/keymanage/Makefile
@@ -28,4 +28,5 @@
aml_key_manage-$(CONFIG_OF_LIBFDT) += km_dts.o
aml_key_manage-$(CONFIG_EFUSE) += km_efuse_key.o
aml_key_manage-$(CONFIG_AML_SECURITY_KEY) += km_secure_key.o
+aml_key_manage-$(CONFIG_KEYMAN_PROVISION_KEY) += km_provision_key.o
diff --git a/drivers/amlogic/keymanage/amlkey_if.h b/drivers/amlogic/keymanage/amlkey_if.h
deleted file mode 100644
index 81f1c7c..0000000
--- a/drivers/amlogic/keymanage/amlkey_if.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * \file amlkey_if.h
- * \brief APIs of secure key for users
- *
- * \version 1.0.0
- * \date 15/07/10
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2015 Amlogic. All Rights Reserved.
- *
- */
-#ifndef __AMLKEY_IF_H__
-#define __AMLKEY_IF_H__
-
-#define AMLKEY_NAME_LEN_MAX (80)
-//1.init
-int32_t amlkey_init(uint8_t *seed, uint32_t len, int encrypt_type);
-
-//2. query if the key already programmed, exsit 1, non 0
-int32_t amlkey_isexsit(const uint8_t * name);
-
-//3. query attr, key must exsit before those functions were called.
- //3.1 whether the prgrammed key is secure, secure 1, non 0
-int32_t amlkey_issecure(const uint8_t * name);
- //3.2 whether the prgrammed key is encrypt, encrypt 1, non 0
-int32_t amlkey_isencrypt(const uint8_t * name);
-
-//4. actual bytes of key value
-ssize_t amlkey_size(const uint8_t *name);
-
-//5. read non-secure key in bytes, return byets readback actully.
-ssize_t amlkey_read(const uint8_t *name, uint8_t *buffer, uint32_t len) ;
-
-//6.write key with attribute in bytes , return byets readback actully
- //attr: bit0: secure/non-secure;
- // bit8: encrypt/non-encrypt
-#define UNIFYKEY_ATTR_SECURE_MASK (1<<0)
-#define UNIFYKEY_ATTR_ENCRYPT_MASK (1<<8)
-ssize_t amlkey_write(const uint8_t *name, uint8_t *buffer, uint32_t len, uint32_t attr);
-
-//7. get the hash value of programmed secure key | 32bytes length, sha256
-int32_t amlkey_hash_4_secure(const uint8_t * name, uint8_t * hash);
-
-#endif// #ifndef __AMLKEY_IF_H__
-
diff --git a/drivers/amlogic/keymanage/key_manage.c b/drivers/amlogic/keymanage/key_manage.c
index 13f595a..bd20ffa 100644
--- a/drivers/amlogic/keymanage/key_manage.c
+++ b/drivers/amlogic/keymanage/key_manage.c
@@ -1,15 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file key_encrypt_decrypt.c
- * \brief encrypt a key before burn to target deive,
- * decrypt a key after read from target device
- *
- * \version 1.0.0
- * \date 15/07/17
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2015 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "key_manage_i.h"
#include <u-boot/sha1.h>
#include <linux/ctype.h>
@@ -534,7 +527,8 @@
else KM_MSG("Err key dataFmt(%s)\n", dataFmt);
}
- return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
+ //return ret ? CMD_RET_FAILURE : CMD_RET_SUCCESS;
+ return CMD_RET_SUCCESS;
}
//argv: 1 2 3
diff --git a/drivers/amlogic/keymanage/key_manage.h b/drivers/amlogic/keymanage/key_manage.h
index b3514b2..511b407 100644
--- a/drivers/amlogic/keymanage/key_manage.h
+++ b/drivers/amlogic/keymanage/key_manage.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __KEY_MANAGE_H__
#define __KEY_MANAGE_H__
@@ -6,6 +11,7 @@
KEY_M_EFUSE_NORMAL,
KEY_M_SECURE_KEY, //secure nandkey/emmckey
KEY_M_NORAML_KEY, //non-secure nandkey/emmckey
+ KEY_M_PROVISION_KEY, //provision key
KEY_M_MAX_DEV,
};
diff --git a/drivers/amlogic/keymanage/key_manage_i.h b/drivers/amlogic/keymanage/key_manage_i.h
index 011f81d..ffa2543 100644
--- a/drivers/amlogic/keymanage/key_manage_i.h
+++ b/drivers/amlogic/keymanage/key_manage_i.h
@@ -1,14 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * \file key_manage_i.h
- * \brief common included files for key manager
- *
- * \version 1.0.0
- * \date 15/06/30
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2015 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#ifndef __KEY_MANAGE_I_H__
#define __KEY_MANAGE_I_H__
@@ -52,5 +46,14 @@
int keymanage_secukey_can_read(const char* keyname);
int keymanage_secukey_read(const char* keyname, void* databuf, unsigned buflen);
+//provision key ops
+int keymanage_provision_init(const char *buf, int len);
+int keymanage_provision_exit(void);
+int keymanage_provision_write(const char *keyname, const void* keydata, unsigned int datalen);
+ssize_t keymanage_provision_size(const char* keyname);
+int keymanage_provision_exist(const char* keyname);
+int keymanage_provision_query_can_read(const char* keyname);
+int keymanage_provision_read(const char *keyname, void* databuf, const unsigned bufSz);
+
#endif//#ifndef __KEY_MANAGE_I_H__
diff --git a/drivers/amlogic/keymanage/key_unify.c b/drivers/amlogic/keymanage/key_unify.c
index b321763..b3cdc93 100644
--- a/drivers/amlogic/keymanage/key_unify.c
+++ b/drivers/amlogic/keymanage/key_unify.c
@@ -1,6 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Unify interfaces for read/write nandkey/emmckey/efuse key
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "key_manage_i.h"
#include <amlogic/keyunify.h>
#include <linux/ctype.h>
@@ -55,12 +57,34 @@
};
#endif//#if defined(CONFIG_EFUSE)
+#if defined(CONFIG_KEYMAN_PROVISION_KEY)
+static KmDevKeyOps _provisionKeyOps = {
+ .pInitFunc = keymanage_provision_init ,
+ .pUninitFunc = keymanage_provision_exit ,
+ .pWriteFunc = keymanage_provision_write ,
+ .pGetSize = keymanage_provision_size ,
+ .pKeyExist = keymanage_provision_exist ,
+ .pKeyCanRead = keymanage_provision_query_can_read ,
+ .pReadFunc = keymanage_provision_read ,
+
+ .can_overwrite = 1 ,
+};
+#endif//#if defined(CONFIG_KEYMAN_PROVISION_KEY)
+
#define _KM_DEV_INDEX_SECUREKEY 0
+#define _KM_DEV_INDEX_PROVISION 1
+#if defined(CONFIG_KEYMAN_PROVISION_KEY)
+#define _KM_DEV_INDEX_EFUSE 2
+#else
#define _KM_DEV_INDEX_EFUSE 1
+#endif//#if defined(CONFIG_KEYMAN_PROVISION_KEY)
static KmDevKeyOps* _km_devKeyOpsArr[] = {
[_KM_DEV_INDEX_SECUREKEY] = &_SecukeyOps,
-#if 1
+#if defined(CONFIG_KEYMAN_PROVISION_KEY)
+ [_KM_DEV_INDEX_PROVISION] = &_provisionKeyOps,
+#endif//#if defined(CONFIG_KEYMAN_PROVISION_KEY)
+#if defined(CONFIG_EFUSE)
[_KM_DEV_INDEX_EFUSE] = &_efuseKeyOps,
#endif//#if defined(CONFIG_EFUSE)
};
@@ -173,6 +197,12 @@
KM_ERR("Seed is 0 err\n");
return __LINE__;
}
+
+ if (amlkey_if_init(dtbLoadaddr)) {
+ KM_ERR("amlkey interface init fail\n");
+ return __LINE__;
+ }
+
for (i=0; i < _KM_DEVCNT; i++)
{
KmDevKeyOps* theDevOps = _km_devKeyOpsArr[i];
@@ -230,6 +260,10 @@
}
break;
+ case KEY_M_PROVISION_KEY:
+ theDevOps = _km_devKeyOpsArr[_KM_DEV_INDEX_PROVISION];
+ break;
+
case KEY_M_UNKNOW_DEV:
default:
KM_ERR("key %s not know device %d\n", keyname, theDevice);
@@ -325,7 +359,6 @@
int key_unify_query_size(const char* keyname, ssize_t* keysize)
{
- int ret = 0;
const KmDevKeyOps* theDevOps = NULL;
theDevOps = _get_km_ops_by_name(keyname);
@@ -334,11 +367,13 @@
return __LINE__;
}
- ret = theDevOps->pKeyCanRead(keyname);
+#if 0
+ int ret = theDevOps->pKeyCanRead(keyname);
if (!ret) {
KM_ERR("key[%s] can't read as it's secure\n", keyname);
return __LINE__;
}
+#endif
*keysize = theDevOps->pGetSize(keyname);
diff --git a/drivers/amlogic/keymanage/km_dts.c b/drivers/amlogic/keymanage/km_dts.c
index 0100188..09f203e 100644
--- a/drivers/amlogic/keymanage/km_dts.c
+++ b/drivers/amlogic/keymanage/km_dts.c
@@ -1,3 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include "key_manage_i.h"
#include <fdt.h>
#include <linux/libfdt.h>
@@ -6,9 +11,10 @@
#define UNIFYKEY_DATAFORMAT_HEXASCII "hexascii"
#define UNIFYKEY_DATAFORMAT_ALLASCII "allascii"
-#define UNIFYKEY_DEVICE_EFUSEKEY "efuse"
-#define UNIFYKEY_DEVICE_NORMAL "normal"
-#define UNIFYKEY_DEVICE_SECURESKEY "secure"
+#define UNIFYKEY_DEVICE_EFUSEKEY "efuse"
+#define UNIFYKEY_DEVICE_NORMAL "normal"
+#define UNIFYKEY_DEVICE_SECURESKEY "secure"
+#define UNIFYKEY_DEVICE_PROVISIONKEY "provision"
#define UNIFYKEY_PERMIT_READ "read"
#define UNIFYKEY_PERMIT_WRITE "write"
@@ -16,6 +22,8 @@
static struct key_info_t unify_key_info={.key_num =0, .key_flag = 0, .efuse_version = -1, .encrypt_type = 0};
static struct key_item_t *unifykey_item=NULL;
+static struct key_item_t* _defProvisonItem =NULL;//keyname start with "KEY_PROVISION_" and device is "provison"
+#define _PROVSION_DEFAULT_KEY_NAME "KEY_PROVISION_XXX"
static int unifykey_item_verify_check(struct key_item_t *key_item)
{
@@ -44,6 +52,10 @@
return pre_item;
}
}
+
+ if (!strncmp(_PROVSION_DEFAULT_KEY_NAME, name, strlen(_PROVSION_DEFAULT_KEY_NAME) - 3)) {
+ return _defProvisonItem;
+ }
return NULL;
}
@@ -215,14 +227,6 @@
strcpy(temp_item->keyType, propdata);
}
-#if 0
- propdata = (char*)fdt_getprop((const void *)dt_addr, nodeoffset, "key-dataformat",NULL);
- if (!propdata) {
- KM_ERR("%s get key-dataformat fail at key_%d\n",item_path, id);
- return __LINE__;
- }
-#endif
-
prop = (struct fdt_property*)fdt_get_property((const void *)dt_addr,nodeoffset,"key-permit",NULL) ;
if (!prop) {
KM_ERR("%s get key-permit fail at key_%d\n",item_path, id);
@@ -280,7 +284,9 @@
int keymanage_dts_parse(const void* dt_addr)
{
int ret = 0;
- int nodeoffset;
+ int child;
+ int nodeoffset, provisionOffset;
+ int unifykeyNum = 0, provisionNum = 0;
char *punifykey_num, *encrypt_type;
if (fdt_check_header(dt_addr)!= 0) {
@@ -302,12 +308,19 @@
}
unify_key_info.key_num = 0;
- punifykey_num = (char*)fdt_getprop((const void *)dt_addr, nodeoffset, "unifykey-num",NULL);
- if (punifykey_num) {
-// printf("unifykey-num config is %x\n",be32_to_cpup((unsigned int*)punifykey_num));
- unify_key_info.key_num = be32_to_cpup((unsigned int*)punifykey_num);
+ fdt_for_each_subnode(child, dt_addr, nodeoffset) {
+ unifykeyNum++;
}
+ provisionOffset = fdt_path_offset(dt_addr, "/provisionkey");
+ if (provisionOffset >= 0) {
+ fdt_for_each_subnode(child, dt_addr, provisionOffset) {
+ provisionNum++;
+ }
+ }
+ unify_key_info.key_num = unifykeyNum + provisionNum;
+ KM_MSG("key_num: %d\n", unify_key_info.key_num);
+
unify_key_info.encrypt_type = -1;
encrypt_type = (char*)fdt_getprop((const void *)dt_addr, nodeoffset, "unifykey-encrypt",NULL);
if (encrypt_type) {
@@ -318,7 +331,7 @@
KM_ERR("unifykey-num is not configured\n");
return __LINE__;
}
- if (unify_key_info.key_num > 32) {
+ if (unify_key_info.key_num > 256) {
KM_ERR("Cfg key_num is %d > 32,pls check!\n", unify_key_info.key_num);
return __LINE__;
}
@@ -330,9 +343,55 @@
unifykey_item = (struct key_item_t*)malloc(keyInfBufLen);
memset(unifykey_item, 0 , keyInfBufLen);
- ret = unifykey_item_create(dt_addr,unify_key_info.key_num);
+ ret = unifykey_item_create(dt_addr,unifykeyNum);
unify_key_info.key_flag = ret ? 0 : 1;
+ if (provisionOffset >= 0)
+ {
+ KM_DBG("dts: in find /provisionkey.\n");
+
+ int defPermits = 0;
+ const struct fdt_property *prop = fdt_get_property(dt_addr, provisionOffset,"key-permit-default",NULL) ;
+ if (prop) {
+ const int propLen = prop->len > 512 ? strnlen(prop->data, 512) : prop->len;
+ if (fdt_stringlist_contains(prop->data, propLen, UNIFYKEY_PERMIT_READ)) {
+ defPermits |= KEY_M_PERMIT_READ;
+ }
+ if (fdt_stringlist_contains(prop->data, propLen, UNIFYKEY_PERMIT_WRITE)) {
+ defPermits |= KEY_M_PERMIT_WRITE;
+ }
+ if (fdt_stringlist_contains(prop->data, propLen, UNIFYKEY_PERMIT_DEL)) {
+ defPermits |= KEY_M_PERMIT_DEL;
+ }
+ }
+
+ int node = 0;
+ int id = unifykeyNum;
+ int szlen = 0;
+ fdt_for_each_subnode(node, dt_addr, provisionOffset) {
+ int len = 0;
+ const char* keyName = fdt_get_name(dt_addr, node, &len);
+ KM_DBG("provisionkey[%s] len %d\n", keyName, len);
+
+ struct key_item_t *pItem= unifykey_item + id;
+
+ szlen = strnlen(keyName, KEY_UNIFY_NAME_LEN - 1);
+ memcpy(pItem->name, keyName, szlen);
+ if (szlen < KEY_UNIFY_NAME_LEN) pItem->name[szlen] = '\0';
+
+ strcpy(pItem->keyType, "raw");
+ pItem->dev = KEY_M_PROVISION_KEY;
+ pItem->permit = defPermits;
+ pItem->id = id++;
+ if (!strcmp(_PROVSION_DEFAULT_KEY_NAME, keyName)) _defProvisonItem = pItem;
+ }
+
+ if ((node < 0) && (node != -FDT_ERR_NOTFOUND)) {
+ KM_ERR("in parse /provisionkey, err(%s)\n", fdt_strerror(node));
+ return __LINE__;
+ }
+ }
+
return ret;
}
diff --git a/drivers/amlogic/keymanage/km_efuse_key.c b/drivers/amlogic/keymanage/km_efuse_key.c
index 955dccc..e7d26be 100644
--- a/drivers/amlogic/keymanage/km_efuse_key.c
+++ b/drivers/amlogic/keymanage/km_efuse_key.c
@@ -1,14 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file km_efuse_key.c
- * \brief efuse key ops for key manage
- *
- * \version 1.0.0
- * \date 15/06/30
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2015 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "key_manage_i.h"
#include <asm/arch/secure_apb.h>
#include <asm/io.h>
diff --git a/drivers/amlogic/keymanage/km_provision_key.c b/drivers/amlogic/keymanage/km_provision_key.c
new file mode 100644
index 0000000..21d60d6
--- /dev/null
+++ b/drivers/amlogic/keymanage/km_provision_key.c
@@ -0,0 +1,85 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "key_manage_i.h"
+#define _CMD_BUF_LEN 512
+static char _cmdBuf[_CMD_BUF_LEN];
+
+int keymanage_provision_init(const char *buf, int len)
+{
+ KM_DBG("f(%s)L%d\n", __func__, __LINE__);
+ return 0;
+}
+
+int keymanage_provision_exit(void)
+{
+ KM_DBG("f(%s)L%d\n", __func__, __LINE__);
+ return 0;
+}
+
+//must be hexdata if stored in efuse
+int keymanage_provision_write(const char *keyname, const void* keydata, unsigned int datalen)
+{
+ KM_DBG("f(%s)L%d\n", __func__, __LINE__);
+
+ snprintf(_cmdBuf, _CMD_BUF_LEN, "factory_provision write %s 0x%p 0x%x", keyname, keydata, datalen);
+ int iRet = run_command(_cmdBuf, 0);
+ KM_MSG("factory provision[%s], query sta=%d\n", keyname, iRet);
+
+ return iRet;
+}
+
+ssize_t keymanage_provision_size(const char* keyname)
+{
+ KM_DBG("f(%s)L%d\n", __func__, __LINE__);
+ uint32_t retBuf[12] = {0};
+ snprintf(_cmdBuf, _CMD_BUF_LEN, "factory_provision query %s 0x%p", keyname, retBuf);
+ int iRet = run_command(_cmdBuf, 0);
+ if (iRet) {
+ KM_MSG("factory provision[%s], query sta=%d\n", keyname, iRet);
+ return 0;
+ }
+
+ return retBuf[0];
+}
+
+int keymanage_provision_exist(const char* keyname)
+{
+ KM_DBG("f(%s)L%d\n", __func__, __LINE__);
+ snprintf(_cmdBuf, _CMD_BUF_LEN, "factory_provision query %s", keyname);
+ int iRet = run_command(_cmdBuf, 0);
+ if (iRet) KM_MSG("factory provision[%s], query sta=%d\n", keyname, iRet);
+
+ return !iRet;
+}
+
+int keymanage_provision_query_can_read(const char* keyname)
+{
+ KM_DBG("f(%s)L%d\n", __func__, __LINE__);
+
+ return 0;//always cannot be read
+}
+
+//read hash instead of actual value
+int keymanage_provision_read(const char *keyname, void* databuf, const unsigned bufSz)
+{
+ KM_DBG("f(%s)L%d\n", __func__, __LINE__);
+ uint32_t retBuf[12] = {0};
+ snprintf(_cmdBuf, _CMD_BUF_LEN, "factory_provision query %s 0x%p", keyname, retBuf);
+ int iRet = run_command(_cmdBuf, 0);
+ if (iRet) {
+ KM_MSG("factory provision[%s], query sta=%d\n", keyname, iRet);
+ return __LINE__;
+ }
+ if (bufSz < 32) {
+ KM_ERR("bufsz %d not enough for sha256sum\n", bufSz);
+ return -__LINE__;
+ }
+
+ KM_MSG("provision read return sha256sum, but not original data\n");
+ memcpy(databuf, retBuf + 1, 32);
+ return 0;//
+}
+
diff --git a/drivers/amlogic/keymanage/km_secure_key.c b/drivers/amlogic/keymanage/km_secure_key.c
index f33652b..f0dbbee 100644
--- a/drivers/amlogic/keymanage/km_secure_key.c
+++ b/drivers/amlogic/keymanage/km_secure_key.c
@@ -1,14 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file km_secure_key.c
- * \brief secure storage key ops for key manage
- *
- * \version 1.0.0
- * \date 15/06/30
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2015 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "key_manage_i.h"
#include <amlogic/amlkey_if.h>
#include <u-boot/sha256.h>
diff --git a/drivers/amlogic/leds/Kconfig b/drivers/amlogic/leds/Kconfig
new file mode 100644
index 0000000..f656741
--- /dev/null
+++ b/drivers/amlogic/leds/Kconfig
@@ -0,0 +1,3 @@
+config MESON_LEDS_STATE_CONTROL
+ bool "Amlogic device LEDS control"
+ default n
diff --git a/drivers/amlogic/leds/Makefile b/drivers/amlogic/leds/Makefile
new file mode 100644
index 0000000..6c2619b
--- /dev/null
+++ b/drivers/amlogic/leds/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_MESON_LEDS_STATE_CONTROL) += leds_state.o
+
diff --git a/drivers/amlogic/leds/leds_state.c b/drivers/amlogic/leds/leds_state.c
new file mode 100644
index 0000000..0cca6ab
--- /dev/null
+++ b/drivers/amlogic/leds/leds_state.c
@@ -0,0 +1,142 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+ /*
+ *
+ * Copyright (C) 2012 Amlogic, Inc.
+ *
+ * Author: jiayi.zhou@amlogic.com
+ *
+ */
+#include <common.h>
+#include <asm/arch/mailbox.h>
+#include "amlogic/leds_state.h"
+
+uint32_t meson_ledstate_set_brightness(uint32_t led_id, uint32_t brightness)
+{
+ int32_t ret;
+ uint32_t data[3];
+
+ if (brightness > LED_FULL) {
+ printf("brightness is not within a reasonable range\n");
+ return -EINVAL;
+ }
+
+ data[0] = led_id;
+ data[1] = LED_STATE_BRIGHTNESS;
+ data[2] = brightness;
+ ret = scpi_send_data(AOCPU_REE_CHANNEL, CMD_LED_INFO, data, sizeof(data), NULL, 0);
+ if ( ret != 0 ) {
+ printf("communication failed\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+uint32_t meson_ledstate_set_breath(uint32_t led_id, uint32_t breath_id)
+{
+ int32_t ret;
+ uint32_t data[3];
+
+ if (breath_id > MAXIMUM_BREATH_ID) {
+ printf("brightness is not within a reasonable range\n");
+ return -EINVAL;
+ }
+
+ data[0] = led_id;
+ data[1] = LED_STATE_BREATH;
+ data[2] = breath_id;
+ ret = scpi_send_data(AOCPU_REE_CHANNEL, CMD_LED_INFO, data, sizeof(data), NULL, 0);
+ if (ret != 0) {
+ printf("communication failed\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/*to do:Five and six parameters are extended parameters*/
+uint32_t meson_ledstate_set_blink_times_on(uint32_t led_id, uint32_t blink_times,
+ uint32_t blink_high, uint32_t blink_low, uint32_t brightness_high, uint32_t brightness_low)
+{
+ int32_t ret;
+ uint32_t data[5];
+
+ if ((blink_times > MAXIMUM_BLINK_NUM) || (blink_high > MAXIMUM_HIGH_MS) ||
+ (blink_low > MAXIMUM_LOW_MS)) {
+ printf("Parameter setting out of range\n");
+ return -EINVAL;
+ }
+
+ brightness_high = brightness_low =0;
+ data[0] = led_id;
+ data[1] = LED_STATE_BLINK_ON;
+ data[2] = blink_times;
+ data[3] = blink_high;
+ data[4] = blink_low;
+ ret = scpi_send_data(AOCPU_REE_CHANNEL, CMD_LED_INFO, data, sizeof(data), NULL, 0);
+ if (ret != 0) {
+ printf("communication failed\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+uint32_t meson_ledstate_set_blink_times_off(uint32_t led_id, uint32_t blink_times,
+ uint32_t blink_high, uint32_t blink_low, uint32_t brightness_high, uint32_t brightness_low)
+{
+ int32_t ret;
+ uint32_t data[5];
+
+ if ((blink_times > MAXIMUM_BLINK_NUM) || (blink_high > MAXIMUM_HIGH_MS) ||
+ (blink_low > MAXIMUM_LOW_MS)) {
+ printf("Parameter setting out of range\n");
+ return -EINVAL;
+ }
+
+ brightness_high = brightness_low =0;
+ data[0] = led_id;
+ data[1] = LED_STATE_BLINK_OFF;
+ data[2] = blink_times;
+ data[3] = blink_high;
+ data[4] = blink_low;
+ ret = scpi_send_data(AOCPU_REE_CHANNEL, CMD_LED_INFO, data, sizeof(data), NULL, 0);
+ if (ret != 0) {
+ printf("communication failed\n");
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/*to do*/
+#if 0
+uint32_t set_led_blink_times_breath(uint32_t led_id,
+ uint32_t blink_times, uint32_t blink_high, uint32_t blink_low )
+{
+ int32_t ret;
+
+ if (blink_times>15 || blink_high%50 != 0 || blink_low%50 != 0) {
+ printf("Parameter setting out of range\n");
+ return -1;
+ }
+
+ uint32_t data[5];
+ data[0]=led_id;
+ data[1]=LED_STATE_BLINK_BREATH;
+ data[2]=blink_times;
+ data[3]=blink_high;
+ data[4]=blink_low ;
+ ret = scpi_send_data(AOCPU_REE_CHANNEL, 0xF7, data, 5*sizeof(data), NULL, 0);
+ if (a != 0) {
+ ptintf("communication failed\n");
+ return -1;
+ }
+
+ return 0;
+}
+#endif
diff --git a/drivers/amlogic/media/Kconfig b/drivers/amlogic/media/Kconfig
index 18203be..9463725 100644
--- a/drivers/amlogic/media/Kconfig
+++ b/drivers/amlogic/media/Kconfig
@@ -4,7 +4,7 @@
Enable support for the Amlogic Media drivers.
config AML_VOUT
- bool "Driver support for video"
+ bool "Driver support for video output"
help
Enable support for amlogic video output
lcd,cvbs...
@@ -19,7 +19,8 @@
help
Enable support for amlogic canvas driver.
+source "drivers/amlogic/media/osd/Kconfig"
+
source "drivers/amlogic/media/common/Kconfig"
source "drivers/amlogic/media/vout/Kconfig"
-
diff --git a/drivers/amlogic/media/canvas/canvas.c b/drivers/amlogic/media/canvas/canvas.c
index 11957dc..e9c5d37 100644
--- a/drivers/amlogic/media/canvas/canvas.c
+++ b/drivers/amlogic/media/canvas/canvas.c
@@ -1,18 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * AMLOGIC Canvas management driver.
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
/* System Headers */
@@ -24,9 +12,7 @@
/* Amlogic Headers */
#include <amlogic/canvas.h>
-#ifdef BL33_DEBUG_PRINT
#define CANVAS_DEBUG_ENABLE
-#endif
#ifdef CANVAS_DEBUG_ENABLE
#define canvas_log(fmt, args...) \
do { \
@@ -36,13 +22,34 @@
#define canvas_log(fmt, args...)
#endif
-#define canvas_reg_read(reg) readl(DMC_REG_BASE + reg)
-#define canvas_reg_write(val, reg) writel(val, (DMC_REG_BASE + reg))
+#ifndef DMC_REG_BASE
+#define DMC_REG_BASE (0xFF638000L)
+#endif
+#define REG_CANVAS_ADDR(reg) (reg + 0L)
#define CANVAS_NUM 256
static canvas_t canvasPool[CANVAS_NUM];
static int canvas_inited = 0;
+static inline u32 canvas_reg_read(u32 reg)
+{
+ u32 val;
+
+ if (reg > 0x10000)
+ val = *(volatile unsigned int *)REG_CANVAS_ADDR(reg);
+ else
+ val = readl(DMC_REG_BASE + reg);
+ return val;
+}
+
+static inline void canvas_reg_write(const u32 val, u32 reg)
+{
+ if (reg > 0x10000)
+ *(volatile unsigned int *)REG_CANVAS_ADDR(reg) = (val);
+ else
+ writel(val, (DMC_REG_BASE + reg));
+}
+
void canvas_init(void)
{
int index = 0;
diff --git a/drivers/amlogic/media/common/Kconfig b/drivers/amlogic/media/common/Kconfig
index 6fd11a3..e4e49f8 100644
--- a/drivers/amlogic/media/common/Kconfig
+++ b/drivers/amlogic/media/common/Kconfig
@@ -1,3 +1,7 @@
+config AML_VPP
+ bool "AML VPP drivers Support"
+ help
+ Enable support for the Amlogic VPp drivers.
+
source "drivers/amlogic/media/common/vpu/Kconfig"
source "drivers/amlogic/media/common/vpp/Kconfig"
-
diff --git a/drivers/amlogic/media/common/vpp/Kconfig b/drivers/amlogic/media/common/vpp/Kconfig
index bda4a2b..8b13789 100644
--- a/drivers/amlogic/media/common/vpp/Kconfig
+++ b/drivers/amlogic/media/common/vpp/Kconfig
@@ -1,5 +1 @@
-config AML_VPP
- bool "AML VPP drivers Support"
- help
- Enable support for the Amlogic VPP drivers.
diff --git a/drivers/amlogic/media/common/vpp/Makefile b/drivers/amlogic/media/common/vpp/Makefile
index 28a8aad..4b75097 100644
--- a/drivers/amlogic/media/common/vpp/Makefile
+++ b/drivers/amlogic/media/common/vpp/Makefile
@@ -1,2 +1,2 @@
obj-$(CONFIG_AML_VPP) += vpp.o
-
+obj-$(CONFIG_AML_VPP) += hdr2.o
diff --git a/drivers/amlogic/media/common/vpp/hdr2.c b/drivers/amlogic/media/common/vpp/hdr2.c
new file mode 100644
index 0000000..9a59c7f
--- /dev/null
+++ b/drivers/amlogic/media/common/vpp/hdr2.c
@@ -0,0 +1,1518 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <amlogic/cpu_id.h>
+#include <malloc.h>
+#include "vpp_reg.h"
+#include "hdr2.h"
+#include <common.h>
+
+#define OO_Y_LUT_BYPASS_VAL 512
+
+int cgain_lut0[65] = {
+ 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400,
+ 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400,
+ 0x4c0, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400,
+ 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x40e,
+ 0x429, 0x444, 0x45f, 0x479, 0x492, 0x4ab, 0x4c3, 0x4db, 0x4f2,
+ 0x509, 0x520, 0x536, 0x54c, 0x561, 0x576, 0x58b, 0x59f, 0x5b3,
+ 0x5c0, 0x5d0, 0x5f2, 0x609, 0x620, 0x636, 0x64c, 0x661, 0x676,
+ 0x68b, 0x69f
+};
+
+int cgain_lut1[65] = {
+ 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400,
+ 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400,
+ 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400,
+ 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400,
+ 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x40e,
+ 0x419, 0x424, 0x43f, 0x449, 0x452, 0x46b, 0x473, 0x48b, 0x492,
+ 0x4a9, 0x4b0, 0x4c6, 0x4dc, 0x4e1, 0x4f6, 0x50b, 0x51f, 0x523,
+ 0x530, 0x540
+};
+
+int cgain_lut_bypass[65] = {
+ 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400,
+ 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400,
+ 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400,
+ 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400,
+ 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400,
+ 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400,
+ 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400, 0x400,
+ 0x400, 0x400
+};
+
+int cgain_lut2[65] = {
+ 0xc00, 0xc00, 0xc00, 0xc00, 0xc00, 0xc00, 0xc00, 0xc00, 0xc00,
+ 0xc00, 0xc00, 0xc0e, 0xc79, 0xcdb, 0xd36, 0xd8b, 0xdda, 0xe25,
+ 0xe6b, 0xead, 0xeec, 0xf28, 0xf61, 0xf98, 0xfcc, 0xfff, 0x102f,
+ 0x105d, 0x108a, 0x10b5, 0x10df, 0x1107, 0x112e, 0x1154, 0x1178, 0x119c,
+ 0x11bf, 0x11e0, 0x1201, 0x1221, 0x1240, 0x125e, 0x127c, 0x1299, 0x12b5,
+ 0x12d1, 0x12ec, 0x1306, 0x1320, 0x1339, 0x1352, 0x136b, 0x1383, 0x139a,
+ 0x13b1, 0x13c7, 0x13de, 0x13f3, 0x1409, 0x141e, 0x1432, 0x1447, 0x145b,
+ 0x146e, 0x1482
+};
+
+int eo_y_lut_hdr[143] = {
+ 132288, 136832, 165440, 181832, 193440, 202088, 210400, 216476, 221882,
+ 227920, 231986, 235648, 239639, 243964, 247193, 249698, 252377, 271330,
+ 285261, 297148, 306377, 314682, 321922, 329204, 334486, 340750, 346085,
+ 350369, 355325, 360734, 363991, 367697, 371896, 376636, 379400, 382389,
+ 385731, 389458, 393410, 395711, 398260, 401078, 404188, 407615, 410492,
+ 412562, 414834, 417322, 420045, 423021, 426127, 427900, 429831, 431934,
+ 434222, 436709, 439410, 442342, 443945, 445668, 447230, 448187, 449224,
+ 450344, 451555, 452864, 454277, 455803, 457449, 458988, 459945, 460977,
+ 462089, 463286, 464576, 465964, 467458, 469066, 470795, 472655, 474655,
+ 475971, 477126, 478368, 479702, 481136, 482676, 484330, 486107, 488015,
+ 490063, 491891, 493071, 494339, 495699, 497159, 498727, 500409, 502262,
+ 504308, 506503, 508381, 509646, 511003, 512460, 512934, 513098, 513279,
+ 513477, 513691, 513923, 514172, 514438, 514720, 515017, 515328, 515650,
+ 515981, 516320, 516662, 517006, 517349, 517689, 518022, 518347, 518662,
+ 518968, 519263, 519549, 519827, 520097, 520363, 520625, 520888, 521155,
+ 521431, 521727, 522054, 522431, 522871, 523371, 523881, 524287
+};
+
+int eo_y_lut_hlg[143] = {
+ 0, 169296, 202068, 221184, 234837, 246442, 253952, 262485, 267605,
+ 273408, 279210, 282794, 286720, 290986, 295253, 297728, 300373, 319488,
+ 333141, 344746, 352256, 360789, 365909, 371712, 377514, 381098, 385024,
+ 389290, 393557, 396032, 398677, 401493, 404480, 407637, 410282, 412032,
+ 413866, 415786, 417792, 419882, 422058, 424320, 426325, 427541, 428800,
+ 430101, 431445, 432832, 434261, 435733, 437248, 438805, 440405, 442048,
+ 443050, 443914, 444800, 445706, 446634, 447584, 448554, 449546, 450560,
+ 451594, 452650, 453728, 454826, 455946, 457088, 458250, 459093, 459696,
+ 460309, 460933, 461568, 462213, 462869, 463536, 464213, 464911, 465640,
+ 466401, 467197, 468028, 468896, 469803, 470750, 471740, 472774, 473854,
+ 474982, 475648, 476264, 476907, 477579, 478281, 479014, 479780, 480580,
+ 481416, 482289, 483201, 484154, 485150, 486190, 487276, 488411, 489597,
+ 490835, 491824, 492500, 493206, 493944, 494714, 495519, 496360, 497238,
+ 498156, 499114, 500115, 501161, 502254, 503396, 504588, 505834, 507135,
+ 508199, 508909, 509651, 510426, 511236, 512081, 512965, 513888, 514852,
+ 515859, 516911, 518010, 519158, 520358, 521611, 522920, 524287
+};
+
+int eo_y_lut_sdr[143] = {
+ 0, 163808, 199044, 219568, 234610, 247036, 255751, 264272, 270593,
+ 277939, 282430, 287163, 292441, 296593, 299792, 303278, 307054, 328697,
+ 344063, 354448, 364052, 372123, 379268, 384835, 391196, 395793, 399793,
+ 404214, 409063, 411973, 414834, 417919, 421229, 424767, 427260, 429261,
+ 431380, 433618, 435975, 438453, 441054, 443072, 444496, 445981, 447530,
+ 449142, 450817, 452556, 454360, 456229, 458163, 459457, 460489, 461555,
+ 462654, 463787, 464953, 466153, 467387, 468655, 469957, 471294, 472665,
+ 474071, 475324, 476062, 476817, 477590, 478381, 479190, 480016, 480861,
+ 481723, 482603, 483502, 484418, 485353, 486306, 487278, 488267, 489276,
+ 490302, 491348, 491966, 492507, 493057, 493618, 494187, 494766, 495354,
+ 495952, 496559, 497176, 497803, 498439, 499084, 499740, 500405, 501079,
+ 501764, 502458, 503161, 503875, 504598, 505332, 506075, 506828, 507590,
+ 508133, 508525, 508921, 509322, 509728, 510140, 510556, 510977, 511404,
+ 511835, 512272, 512713, 513160, 513611, 514068, 514530, 514997, 515469,
+ 515946, 516429, 516916, 517409, 517907, 518410, 518918, 519432, 519950,
+ 520474, 521003, 521537, 522077, 522622, 523172, 523727, 524287
+};
+
+int eo_y_lut_bypass[143] = {
+ 0, 360448, 376832, 385024, 393216, 397312, 401408, 405504, 409600,
+ 411648, 413696, 415744, 417792, 419840, 421888, 423936, 425984, 434176,
+ 442368, 446464, 450560, 454656, 458752, 460800, 462848, 464896, 466944,
+ 468992, 471040, 473088, 475136, 476160, 477184, 478208, 479232, 480256,
+ 481280, 482304, 483328, 484352, 485376, 486400, 487424, 488448, 489472,
+ 490496, 491520, 492032, 492544, 493056, 493568, 494080, 494592, 495104,
+ 495616, 496128, 496640, 497152, 497664, 498176, 498688, 499200, 499712,
+ 500224, 500736, 501248, 501760, 502272, 502784, 503296, 503808, 504320,
+ 504832, 505344, 505856, 506368, 506880, 507392, 507904, 508160, 508416,
+ 508672, 508928, 509184, 509440, 509696, 509952, 510208, 510464, 510720,
+ 510976, 511232, 511488, 511744, 512000, 512256, 512512, 512768, 513024,
+ 513280, 513536, 513792, 514048, 514304, 514560, 514816, 515072, 515328,
+ 515584, 515840, 516096, 516352, 516608, 516864, 517120, 517376, 517632,
+ 517888, 518144, 518400, 518656, 518912, 519168, 519424, 519680, 519936,
+ 520192, 520448, 520704, 520960, 521216, 521472, 521728, 521984, 522240,
+ 522496, 522752, 523008, 523264, 523520, 523776, 524032, 524287
+};
+
+int oe_y_lut_hdr[149] = {0, 3, 5, 8, 12, 19, 28, 41, 60, 67, 74, 80, 85,
+ 96, 105, 113, 120, 134, 146, 157, 167, 184, 200, 214, 227, 250, 270,
+ 288, 304, 332, 357, 380, 400, 435, 465, 492, 517, 559, 595, 628, 656,
+ 706, 749, 787, 820, 850, 878, 903, 927, 949, 970, 989, 1008, 1042, 1073,
+ 1102, 1129, 1154, 1177, 1199, 1219, 1258, 1292, 1324, 1354, 1381, 1407,
+ 1431, 1453, 1495, 1533, 1568, 1600, 1630, 1657, 1683, 1708, 1753, 1794,
+ 1831, 1865, 1897, 1926, 1954, 1980, 2028, 2071, 2110, 2146, 2179, 2210,
+ 2239, 2267, 2317, 2361, 2402, 2440, 2474, 2506, 2536, 2564, 2616, 2662,
+ 2704, 2742, 2778, 2810, 2841, 2870, 2922, 2969, 3011, 3050, 3086, 3119,
+ 3150, 3179, 3231, 3278, 3321, 3360, 3396, 3429, 3459, 3488, 3540, 3587,
+ 3629, 3668, 3703, 3736, 3766, 3795, 3821, 3846, 3870, 3892, 3913, 3934,
+ 3953, 3971, 3989, 4006, 4022, 4038, 4053, 4068, 4082, 4095
+};
+
+int oe_y_lut_hlg[149] = {0, 0, 0, 0, 1, 1, 2, 3, 4, 5, 6, 6, 6, 7, 8, 9,
+ 9, 10, 12, 12, 13, 15, 16, 18, 19, 21, 24, 25, 27, 30, 33, 36, 39,
+ 43, 48, 51, 55, 61, 67, 73, 78, 87, 96, 103, 110, 117, 123, 129, 135,
+ 141, 146, 151, 156, 166, 175, 183, 192, 199, 207, 214, 221, 235, 247,
+ 259, 271, 282, 293, 303, 313, 332, 350, 367, 384, 399, 414, 429, 443,
+ 470, 495, 519, 543, 565, 586, 607, 627, 665, 701, 735, 768, 799, 829,
+ 858, 886, 940, 991, 1039, 1086, 1130, 1173, 1214, 1254, 1330, 1402,
+ 1470, 1536, 1598, 1659, 1717, 1773, 1881, 1982, 2079, 2165, 2243,
+ 2313, 2377, 2436, 2541, 2633, 2714, 2788, 2855, 2916, 2972, 3025,
+ 3119, 3203, 3279, 3347, 3409, 3467, 3520, 3570, 3616, 3660, 3701,
+ 3740, 3778, 3813, 3847, 3879, 3910, 3939, 3968, 3995, 4022, 4047,
+ 4072, 4095
+};
+
+int oe_y_lut_sdr[149] = {0, 1, 1, 2, 2, 3, 5, 7, 9, 10, 11, 12, 12, 13,
+ 15, 16, 16, 18, 20, 21, 22, 24, 26, 28, 30, 33, 35, 38, 40, 44, 47,
+ 50, 53, 59, 63, 67, 71, 78, 85, 90, 95, 105, 113, 121, 127, 134, 140,
+ 146, 151, 156, 161, 166, 170, 179, 187, 195, 202, 209, 215, 222, 228,
+ 239, 250, 260, 270, 279, 287, 296, 304, 319, 334, 347, 360, 372, 384,
+ 395, 406, 426, 445, 464, 481, 497, 513, 528, 542, 569, 595, 619, 642,
+ 664, 684, 704, 724, 760, 794, 826, 857, 886, 914, 940, 966, 1015, 1060,
+ 1103, 1144, 1183, 1220, 1255, 1290, 1355, 1415, 1473, 1527, 1579, 1628,
+ 1676, 1722, 1808, 1889, 1966, 2039, 2108, 2174, 2237, 2298, 2414, 2522,
+ 2624, 2721, 2814, 2902, 2987, 3068, 3147, 3222, 3296, 3367, 3436, 3503,
+ 3569, 3633, 3695, 3756, 3816, 3874, 3931, 3987, 4042, 4095
+};
+
+static int oe_y_lut_bypass[149] = {
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
+ 0, 0, 1, 1, 1, 1, 1, 1, 1, 1, 2, 2, 2, 2, 3, 3, 3, 3, 4, 4, 5,
+ 5, 6, 6, 7, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 18, 20, 22, 24,
+ 26, 28, 30, 32, 36, 40, 44, 48, 52, 56, 60, 64, 72, 80, 88, 96,
+ 104, 112, 120, 128, 144, 160, 176, 192, 208, 224, 240, 256, 288,
+ 320, 352, 384, 416, 448, 480, 512, 576, 640, 704, 768, 832, 896,
+ 960, 1024, 1152, 1280, 1408, 1536, 1664, 1792, 1920, 2048, 2176,
+ 2304, 2432, 2560, 2688, 2816, 2944, 3072, 3200, 3328, 3456, 3584,
+ 3712, 3840, 3968, 4095
+};
+
+int oo_y_lut_hdr_hlg[149] = {
+ 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095,
+ 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095,
+ 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095,
+ 3917, 3776, 3662, 3565, 3410, 3288, 3188, 3104, 2968, 2862, 2775,
+ 2702, 2639, 2584, 2535, 2491, 2452, 2416, 2383, 2352, 2297, 2249,
+ 2207, 2169, 2134, 2103, 2074, 2047, 2000, 1958, 1921, 1888, 1858,
+ 1831, 1806, 1782, 1741, 1705, 1672, 1644, 1617, 1594, 1572, 1552,
+ 1515, 1484, 1456, 1431, 1408, 1387, 1368, 1351, 1319, 1292, 1267,
+ 1245, 1226, 1208, 1191, 1176, 1148, 1124, 1103, 1084, 1067, 1051,
+ 1037, 1023, 1000, 979, 960, 944, 929, 915, 903, 891, 870, 852,
+ 836, 822, 808, 797, 786, 776, 757, 742, 728, 715, 704, 693, 684,
+ 675, 659, 646, 633, 622, 613, 604, 595, 588, 581, 574, 568, 562,
+ 557, 551, 546, 542, 537, 533, 529, 525, 522, 518, 515, 512
+};
+
+int oo_y_lut_hdr_sdr[149] = {
+ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+ 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255, 255,
+ 255, 255, 255, 255, 255, 255
+};
+
+int oo_y_lut_hlg_hdr[149] = {
+ 4, 8, 9, 11, 12, 14, 16, 19, 22, 23, 24, 24, 25, 26, 27, 28, 29,
+ 30, 31, 32, 33, 35, 36, 37, 38, 40, 42, 43, 44, 46, 48, 49, 51,
+ 53, 55, 57, 58, 61, 63, 65, 67, 70, 73, 75, 77, 79, 81, 82, 84,
+ 85, 86, 88, 89, 91, 93, 95, 96, 98, 99, 101, 102, 104, 107, 109,
+ 111, 112, 114, 116, 117, 120, 122, 125, 127, 129, 131, 133, 135,
+ 138, 141, 144, 146, 148, 151, 153, 155, 158, 162, 165, 168, 171,
+ 173, 176, 178, 182, 186, 190, 193, 196, 199, 202, 204, 209, 214,
+ 218, 222, 225, 229, 232, 235, 240, 245, 250, 255, 259, 263, 266,
+ 270, 276, 282, 288, 293, 297, 302, 306, 310, 317, 324, 330, 336,
+ 342, 347, 352, 356, 360, 365, 369, 372, 376, 380, 383, 386, 389,
+ 392, 395, 398, 401, 404, 407, 409
+};
+
+int oo_y_lut_sdr_hdr[149] = {
+ 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
+ 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
+ 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
+ 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
+ 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
+ 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
+ 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
+ 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
+ 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16, 16,
+ 16, 16, 16, 16, 16
+};
+
+int oo_y_lut_hlg_sdr[149] = {
+ 245, 269, 275, 282, 288, 295, 302, 309, 316, 318, 320, 322, 323,
+ 326, 327, 329, 331, 333, 335, 337, 338, 341, 343, 345, 346, 349,
+ 351, 353, 354, 357, 359, 361, 362, 365, 367, 369, 371, 373, 376,
+ 378, 379, 382, 384, 386, 388, 390, 391, 392, 393, 394, 395, 396,
+ 397, 399, 400, 401, 402, 403, 404, 405, 406, 408, 409, 410, 412,
+ 413, 414, 415, 416, 417, 419, 420, 421, 422, 423, 424, 425, 427,
+ 428, 430, 431, 432, 433, 434, 435, 437, 438, 440, 441, 442, 443,
+ 444, 445, 447, 448, 450, 451, 452, 453, 454, 455, 457, 459, 460,
+ 462, 463, 464, 465, 466, 468, 469, 471, 472, 473, 475, 476, 477,
+ 479, 480, 482, 483, 484, 486, 487, 488, 490, 491, 493, 494, 496,
+ 497, 498, 499, 500, 501, 502, 503, 503, 504, 505, 506, 506, 507,
+ 508, 508, 509, 509, 510, 510
+};
+
+int oo_y_lut_sdr_hlg[149] = {
+ 1060, 967, 946, 924, 903, 883, 863, 844, 825, 819, 814, 810, 806,
+ 800, 795, 791, 788, 782, 777, 773, 770, 764, 760, 756, 753,
+ 747, 743, 739, 736, 730, 726, 722, 719, 714, 710, 706, 703,
+ 698, 694, 690, 687, 682, 678, 674, 671, 669, 667, 664, 663,
+ 661, 659, 658, 656, 654, 651, 649, 648, 646, 644, 643, 641,
+ 639, 637, 635, 633, 631, 630, 628, 627, 625, 622, 620, 619,
+ 617, 616, 614, 613, 610, 608, 606, 605, 603, 602, 600, 599,
+ 597, 595, 593, 591, 590, 588, 587, 585, 583, 581, 579, 578,
+ 576, 575, 573, 572, 570, 568, 566, 565, 563, 562, 561, 559,
+ 557, 555, 554, 552, 550, 549, 548, 547, 545, 543, 541, 539,
+ 538, 537, 536, 534, 532, 530, 529, 527, 526, 525, 523, 522,
+ 521, 520, 519, 518, 518, 517, 516, 515, 515, 514, 513, 513,
+ 512, 512, 511, 511
+};
+
+int oo_y_lut_1[149] = {
+ 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095,
+ 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095,
+ 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095,
+ 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095,
+ 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095,
+ 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095,
+ 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095,
+ 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095,
+ 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095,
+ 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095,
+ 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095,
+ 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095,
+ 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095, 4095,
+ 4095, 4095, 4095, 4095, 4095, 4095
+};
+
+static uint out_luma = 5;
+static uint in_luma = 1;/*1 as 100luminance*/
+static uint adp_scal_shift = 10;/*1 as 100luminance*/
+
+int ncl_2020_709[9] = {
+ 2684, -489, -147, -201, 2266, -17, -29, -171, 2248};
+
+int ncl_709_2020[9] = {1285, 674, 89, 142, 1883, 23, 34, 180, 1834};
+
+int rgb2yuvpre[3] = {0, 0, 0};
+int rgb2yuvpos[3] = {64, 512, 512};
+int yuv2rgbpre[3] = {-64, -512, -512};
+int yuv2rgbpos[3] = {0, 0, 0};
+int bypass_pre[3] = {0, 0, 0};
+int bypass_pos[3] = {0, 0, 0};
+
+int yuv2rgbmat[15] = {
+ 1197, 0, 0, 1197, 1851, 0, 1197, 0, 1163, 1197, 2271, 0, 1197, 0, 2011};
+int rgb2ycbcr[15] = {
+ 230, 594, 52, -125, -323, 448, 448, -412, -36, 0, 0, 0, 0, 0, 0};
+int rgb2ycbcr_ncl2020[15] = {
+ 230, 594, 52, -125, -323, 448, 448, -412, -36, 0, 0, 0, 0, 0, 0};
+int rgb2ycbcr_709[15] = {
+ 186, 627, 63, -103, -345, 448, 448, -407, -41, 0, 0, 0, 0, 0, 0};
+int ycbcr2rgb_709[15] = {
+ 1192, 0, 1836, 1192, -217, -546, 1192, 2166, 0, 0, 0, 0, 0, 0, 0};
+int ycbcr2rgb_ncl2020[15] = {
+ 1197, 0, 1726, 1197, -193, -669, 1197, 2202, 0, 0, 0, 0, 0, 0, 0};
+
+static int bypass_coeff[15] = {
+ 1024, 0, 0,
+ 0, 1024, 0,
+ 0, 0, 1024,
+ 0, 0, 0,
+ 0, 0, 0,
+};
+
+/* gamut bypass */
+int gamut_bypass[9] = {2048, 0, 0, 0, 2048, 0, 0, 0, 2048};
+
+void set_hdr_matrix(enum hdr_module_sel module_sel,
+ enum hdr_matrix_sel mtx_sel,
+ struct hdr_proc_mtx_param_s *hdr_mtx_param)
+{
+ unsigned int MATRIXI_COEF00_01 = 0;
+ unsigned int MATRIXI_COEF02_10 = 0;
+ unsigned int MATRIXI_COEF11_12 = 0;
+ unsigned int MATRIXI_COEF20_21 = 0;
+ unsigned int MATRIXI_COEF22 = 0;
+ /*unsigned int MATRIXI_COEF30_31 = 0;*/
+ /*unsigned int MATRIXI_COEF32_40 = 0;*/
+ /*unsigned int MATRIXI_COEF41_42 = 0;*/
+ unsigned int MATRIXI_OFFSET0_1 = 0;
+ unsigned int MATRIXI_OFFSET2 = 0;
+ unsigned int MATRIXI_PRE_OFFSET0_1 = 0;
+ unsigned int MATRIXI_PRE_OFFSET2 = 0;
+ /*unsigned int MATRIXI_CLIP = 0;*/
+ unsigned int MATRIXI_EN_CTRL = 0;
+
+ unsigned int MATRIXO_COEF00_01 = 0;
+ unsigned int MATRIXO_COEF02_10 = 0;
+ unsigned int MATRIXO_COEF11_12 = 0;
+ unsigned int MATRIXO_COEF20_21 = 0;
+ unsigned int MATRIXO_COEF22 = 0;
+ /*unsigned int MATRIXO_COEF30_31 = 0;*/
+ /*unsigned int MATRIXO_COEF32_40 = 0;*/
+ /*unsigned int MATRIXO_COEF41_42 = 0;*/
+ unsigned int MATRIXO_OFFSET0_1 = 0;
+ unsigned int MATRIXO_OFFSET2 = 0;
+ unsigned int MATRIXO_PRE_OFFSET0_1 = 0;
+ unsigned int MATRIXO_PRE_OFFSET2 = 0;
+ /*unsigned int MATRIXO_CLIP = 0;*/
+ unsigned int MATRIXO_EN_CTRL = 0;
+
+ unsigned int CGAIN_OFFT = 0;
+ unsigned int CGAIN_COEF0 = 0;
+ unsigned int CGAIN_COEF1 = 0;
+ unsigned int ADPS_CTRL = 0;
+ unsigned int ADPS_ALPHA0 = 0;
+ unsigned int ADPS_ALPHA1 = 0;
+ unsigned int ADPS_BETA0 = 0;
+ unsigned int ADPS_BETA1 = 0;
+ unsigned int ADPS_BETA2 = 0;
+ unsigned int ADPS_COEF0 = 0;
+ unsigned int ADPS_COEF1 = 0;
+ unsigned int GMUT_CTRL = 0;
+ unsigned int GMUT_COEF0 = 0;
+ unsigned int GMUT_COEF1 = 0;
+ unsigned int GMUT_COEF2 = 0;
+ unsigned int GMUT_COEF3 = 0;
+ unsigned int GMUT_COEF4 = 0;
+
+ unsigned int hdr_ctrl = 0;
+
+ int adpscl_mode = 0;
+
+ int c_gain_lim_coef[3];
+ int gmut_coef[3][3];
+ int gmut_shift;
+ int adpscl_enable[3];
+ int adpscl_alpha[3] = {0, 0, 0};
+ int adpscl_shift[3];
+ int adpscl_ys_coef[3] = {0, 0, 0};
+ int adpscl_beta[3];
+ int adpscl_beta_s[3];
+
+ int i = 0;
+ int mtx[15] = {
+ 1024, 0, 0,
+ 0, 1024, 0,
+ 0, 0, 1024,
+ 0, 0, 0,
+ 0, 0, 0,
+ };
+
+ if (module_sel & VD1_HDR) {
+ MATRIXI_COEF00_01 = VD1_HDR2_MATRIXI_COEF00_01;
+ MATRIXI_COEF00_01 = VD1_HDR2_MATRIXI_COEF00_01;
+ MATRIXI_COEF02_10 = VD1_HDR2_MATRIXI_COEF02_10;
+ MATRIXI_COEF11_12 = VD1_HDR2_MATRIXI_COEF11_12;
+ MATRIXI_COEF20_21 = VD1_HDR2_MATRIXI_COEF20_21;
+ MATRIXI_COEF22 = VD1_HDR2_MATRIXI_COEF22;
+ /*MATRIXI_COEF30_31 = VD1_HDR2_MATRIXI_COEF30_31;*/
+ /*MATRIXI_COEF32_40 = VD1_HDR2_MATRIXI_COEF32_40;*/
+ /*MATRIXI_COEF41_42 = VD1_HDR2_MATRIXI_COEF41_42;*/
+ MATRIXI_OFFSET0_1 = VD1_HDR2_MATRIXI_OFFSET0_1;
+ MATRIXI_OFFSET2 = VD1_HDR2_MATRIXI_OFFSET2;
+ MATRIXI_PRE_OFFSET0_1 = VD1_HDR2_MATRIXI_PRE_OFFSET0_1;
+ MATRIXI_PRE_OFFSET2 = VD1_HDR2_MATRIXI_PRE_OFFSET2;
+ /*MATRIXI_CLIP = VD1_HDR2_MATRIXI_CLIP;*/
+ MATRIXI_EN_CTRL = VD1_HDR2_MATRIXI_EN_CTRL;
+
+ MATRIXO_COEF00_01 = VD1_HDR2_MATRIXO_COEF00_01;
+ MATRIXO_COEF00_01 = VD1_HDR2_MATRIXO_COEF00_01;
+ MATRIXO_COEF02_10 = VD1_HDR2_MATRIXO_COEF02_10;
+ MATRIXO_COEF11_12 = VD1_HDR2_MATRIXO_COEF11_12;
+ MATRIXO_COEF20_21 = VD1_HDR2_MATRIXO_COEF20_21;
+ MATRIXO_COEF22 = VD1_HDR2_MATRIXO_COEF22;
+ /*MATRIXO_COEF30_31 = VD1_HDR2_MATRIXO_COEF30_31;*/
+ /*MATRIXO_COEF32_40 = VD1_HDR2_MATRIXO_COEF32_40;*/
+ /*MATRIXO_COEF41_42 = VD1_HDR2_MATRIXO_COEF41_42;*/
+ MATRIXO_OFFSET0_1 = VD1_HDR2_MATRIXO_OFFSET0_1;
+ MATRIXO_OFFSET2 = VD1_HDR2_MATRIXO_OFFSET2;
+ MATRIXO_PRE_OFFSET0_1 = VD1_HDR2_MATRIXO_PRE_OFFSET0_1;
+ MATRIXO_PRE_OFFSET2 = VD1_HDR2_MATRIXO_PRE_OFFSET2;
+ /*MATRIXO_CLIP = VD1_HDR2_MATRIXO_CLIP;*/
+ MATRIXO_EN_CTRL = VD1_HDR2_MATRIXO_EN_CTRL;
+
+ CGAIN_OFFT = VD1_HDR2_CGAIN_OFFT;
+ CGAIN_COEF0 = VD1_HDR2_CGAIN_COEF0;
+ CGAIN_COEF1 = VD1_HDR2_CGAIN_COEF1;
+ ADPS_CTRL = VD1_HDR2_ADPS_CTRL;
+ ADPS_ALPHA0 = VD1_HDR2_ADPS_ALPHA0;
+ ADPS_ALPHA1 = VD1_HDR2_ADPS_ALPHA1;
+ ADPS_BETA0 = VD1_HDR2_ADPS_BETA0;
+ ADPS_BETA1 = VD1_HDR2_ADPS_BETA1;
+ ADPS_BETA2 = VD1_HDR2_ADPS_BETA2;
+ ADPS_COEF0 = VD1_HDR2_ADPS_COEF0;
+ ADPS_COEF1 = VD1_HDR2_ADPS_COEF1;
+ GMUT_CTRL = VD1_HDR2_GMUT_CTRL;
+ GMUT_COEF0 = VD1_HDR2_GMUT_COEF0;
+ GMUT_COEF1 = VD1_HDR2_GMUT_COEF1;
+ GMUT_COEF2 = VD1_HDR2_GMUT_COEF2;
+ GMUT_COEF3 = VD1_HDR2_GMUT_COEF3;
+ GMUT_COEF4 = VD1_HDR2_GMUT_COEF4;
+
+ hdr_ctrl = VD1_HDR2_CTRL;
+ } else if (module_sel & VD2_HDR) {
+ MATRIXI_COEF00_01 = VD2_HDR2_MATRIXI_COEF00_01;
+ MATRIXI_COEF00_01 = VD2_HDR2_MATRIXI_COEF00_01;
+ MATRIXI_COEF02_10 = VD2_HDR2_MATRIXI_COEF02_10;
+ MATRIXI_COEF11_12 = VD2_HDR2_MATRIXI_COEF11_12;
+ MATRIXI_COEF20_21 = VD2_HDR2_MATRIXI_COEF20_21;
+ MATRIXI_COEF22 = VD2_HDR2_MATRIXI_COEF22;
+ /*MATRIXI_COEF30_31 = VD2_HDR2_MATRIXI_COEF30_31;*/
+ /*MATRIXI_COEF32_40 = VD2_HDR2_MATRIXI_COEF32_40;*/
+ /*MATRIXI_COEF41_42 = VD2_HDR2_MATRIXI_COEF41_42;*/
+ MATRIXI_OFFSET0_1 = VD2_HDR2_MATRIXI_OFFSET0_1;
+ MATRIXI_OFFSET2 = VD2_HDR2_MATRIXI_OFFSET2;
+ MATRIXI_PRE_OFFSET0_1 = VD2_HDR2_MATRIXI_PRE_OFFSET0_1;
+ MATRIXI_PRE_OFFSET2 = VD2_HDR2_MATRIXI_PRE_OFFSET2;
+ /*MATRIXI_CLIP = VD2_HDR2_MATRIXI_CLIP;*/
+ MATRIXI_EN_CTRL = VD2_HDR2_MATRIXI_EN_CTRL;
+
+ MATRIXO_COEF00_01 = VD2_HDR2_MATRIXO_COEF00_01;
+ MATRIXO_COEF00_01 = VD2_HDR2_MATRIXO_COEF00_01;
+ MATRIXO_COEF02_10 = VD2_HDR2_MATRIXO_COEF02_10;
+ MATRIXO_COEF11_12 = VD2_HDR2_MATRIXO_COEF11_12;
+ MATRIXO_COEF20_21 = VD2_HDR2_MATRIXO_COEF20_21;
+ MATRIXO_COEF22 = VD2_HDR2_MATRIXO_COEF22;
+ /*MATRIXO_COEF30_31 = VD2_HDR2_MATRIXO_COEF30_31;*/
+ /*MATRIXO_COEF32_40 = VD2_HDR2_MATRIXO_COEF32_40;*/
+ /*MATRIXO_COEF41_42 = VD2_HDR2_MATRIXO_COEF41_42;*/
+ MATRIXO_OFFSET0_1 = VD2_HDR2_MATRIXO_OFFSET0_1;
+ MATRIXO_OFFSET2 = VD2_HDR2_MATRIXO_OFFSET2;
+ MATRIXO_PRE_OFFSET0_1 = VD2_HDR2_MATRIXO_PRE_OFFSET0_1;
+ MATRIXO_PRE_OFFSET2 = VD2_HDR2_MATRIXO_PRE_OFFSET2;
+ /*MATRIXO_CLIP = VD2_HDR2_MATRIXO_CLIP;*/
+ MATRIXO_EN_CTRL = VD2_HDR2_MATRIXO_EN_CTRL;
+
+ CGAIN_OFFT = VD2_HDR2_CGAIN_OFFT;
+ CGAIN_COEF0 = VD2_HDR2_CGAIN_COEF0;
+ CGAIN_COEF1 = VD2_HDR2_CGAIN_COEF1;
+ ADPS_CTRL = VD2_HDR2_ADPS_CTRL;
+ ADPS_ALPHA0 = VD2_HDR2_ADPS_ALPHA0;
+ ADPS_ALPHA1 = VD2_HDR2_ADPS_ALPHA1;
+ ADPS_BETA0 = VD2_HDR2_ADPS_BETA0;
+ ADPS_BETA1 = VD2_HDR2_ADPS_BETA1;
+ ADPS_BETA2 = VD2_HDR2_ADPS_BETA2;
+ ADPS_COEF0 = VD2_HDR2_ADPS_COEF0;
+ ADPS_COEF1 = VD2_HDR2_ADPS_COEF1;
+ GMUT_CTRL = VD2_HDR2_GMUT_CTRL;
+ GMUT_COEF0 = VD2_HDR2_GMUT_COEF0;
+ GMUT_COEF1 = VD2_HDR2_GMUT_COEF1;
+ GMUT_COEF2 = VD2_HDR2_GMUT_COEF2;
+ GMUT_COEF3 = VD2_HDR2_GMUT_COEF3;
+ GMUT_COEF4 = VD2_HDR2_GMUT_COEF4;
+
+ hdr_ctrl = VD2_HDR2_CTRL;
+ } else if (module_sel & OSD1_HDR) {
+ MATRIXI_COEF00_01 = OSD1_HDR2_MATRIXI_COEF00_01;
+ MATRIXI_COEF00_01 = OSD1_HDR2_MATRIXI_COEF00_01;
+ MATRIXI_COEF02_10 = OSD1_HDR2_MATRIXI_COEF02_10;
+ MATRIXI_COEF11_12 = OSD1_HDR2_MATRIXI_COEF11_12;
+ MATRIXI_COEF20_21 = OSD1_HDR2_MATRIXI_COEF20_21;
+ MATRIXI_COEF22 = OSD1_HDR2_MATRIXI_COEF22;
+ /*MATRIXI_COEF30_31 = OSD1_HDR2_MATRIXI_COEF30_31;*/
+ /*MATRIXI_COEF32_40 = OSD1_HDR2_MATRIXI_COEF32_40;*/
+ /*MATRIXI_COEF41_42 = OSD1_HDR2_MATRIXI_COEF41_42;*/
+ MATRIXI_OFFSET0_1 = OSD1_HDR2_MATRIXI_OFFSET0_1;
+ MATRIXI_OFFSET2 = OSD1_HDR2_MATRIXI_OFFSET2;
+ MATRIXI_PRE_OFFSET0_1 = OSD1_HDR2_MATRIXI_PRE_OFFSET0_1;
+ MATRIXI_PRE_OFFSET2 = OSD1_HDR2_MATRIXI_PRE_OFFSET2;
+ /*MATRIXI_CLIP = OSD1_HDR2_MATRIXI_CLIP;*/
+ MATRIXI_EN_CTRL = OSD1_HDR2_MATRIXI_EN_CTRL;
+
+ MATRIXO_COEF00_01 = OSD1_HDR2_MATRIXO_COEF00_01;
+ MATRIXO_COEF00_01 = OSD1_HDR2_MATRIXO_COEF00_01;
+ MATRIXO_COEF02_10 = OSD1_HDR2_MATRIXO_COEF02_10;
+ MATRIXO_COEF11_12 = OSD1_HDR2_MATRIXO_COEF11_12;
+ MATRIXO_COEF20_21 = OSD1_HDR2_MATRIXO_COEF20_21;
+ MATRIXO_COEF22 = OSD1_HDR2_MATRIXO_COEF22;
+ /*MATRIXO_COEF30_31 = OSD1_HDR2_MATRIXO_COEF30_31;*/
+ /*MATRIXO_COEF32_40 = OSD1_HDR2_MATRIXO_COEF32_40;*/
+ /*MATRIXO_COEF41_42 = OSD1_HDR2_MATRIXO_COEF41_42;*/
+ MATRIXO_OFFSET0_1 = OSD1_HDR2_MATRIXO_OFFSET0_1;
+ MATRIXO_OFFSET2 = OSD1_HDR2_MATRIXO_OFFSET2;
+ MATRIXO_PRE_OFFSET0_1 = OSD1_HDR2_MATRIXO_PRE_OFFSET0_1;
+ MATRIXO_PRE_OFFSET2 = OSD1_HDR2_MATRIXO_PRE_OFFSET2;
+ /*MATRIXO_CLIP = OSD1_HDR2_MATRIXO_CLIP;*/
+ MATRIXO_EN_CTRL = OSD1_HDR2_MATRIXO_EN_CTRL;
+
+ CGAIN_OFFT = OSD1_HDR2_CGAIN_OFFT;
+ CGAIN_COEF0 = OSD1_HDR2_CGAIN_COEF0;
+ CGAIN_COEF1 = OSD1_HDR2_CGAIN_COEF1;
+ ADPS_CTRL = OSD1_HDR2_ADPS_CTRL;
+ ADPS_ALPHA0 = OSD1_HDR2_ADPS_ALPHA0;
+ ADPS_ALPHA1 = OSD1_HDR2_ADPS_ALPHA1;
+ ADPS_BETA0 = OSD1_HDR2_ADPS_BETA0;
+ ADPS_BETA1 = OSD1_HDR2_ADPS_BETA1;
+ ADPS_BETA2 = OSD1_HDR2_ADPS_BETA2;
+ ADPS_COEF0 = OSD1_HDR2_ADPS_COEF0;
+ ADPS_COEF1 = OSD1_HDR2_ADPS_COEF1;
+ GMUT_CTRL = OSD1_HDR2_GMUT_CTRL;
+ GMUT_COEF0 = OSD1_HDR2_GMUT_COEF0;
+ GMUT_COEF1 = OSD1_HDR2_GMUT_COEF1;
+ GMUT_COEF2 = OSD1_HDR2_GMUT_COEF2;
+ GMUT_COEF3 = OSD1_HDR2_GMUT_COEF3;
+ GMUT_COEF4 = OSD1_HDR2_GMUT_COEF4;
+
+ hdr_ctrl = OSD1_HDR2_CTRL;
+ }else if (module_sel & OSD2_HDR) {
+ MATRIXI_COEF00_01 = OSD2_HDR2_MATRIXI_COEF00_01;
+ MATRIXI_COEF00_01 = OSD2_HDR2_MATRIXI_COEF00_01;
+ MATRIXI_COEF02_10 = OSD2_HDR2_MATRIXI_COEF02_10;
+ MATRIXI_COEF11_12 = OSD2_HDR2_MATRIXI_COEF11_12;
+ MATRIXI_COEF20_21 = OSD2_HDR2_MATRIXI_COEF20_21;
+ MATRIXI_COEF22 = OSD2_HDR2_MATRIXI_COEF22;
+ /*MATRIXI_COEF30_31 = OSD2_HDR2_MATRIXI_COEF30_31;*/
+ /*MATRIXI_COEF32_40 = OSD2_HDR2_MATRIXI_COEF32_40;*/
+ /*MATRIXI_COEF41_42 = OSD2_HDR2_MATRIXI_COEF41_42;*/
+ MATRIXI_OFFSET0_1 = OSD2_HDR2_MATRIXI_OFFSET0_1;
+ MATRIXI_OFFSET2 = OSD2_HDR2_MATRIXI_OFFSET2;
+ MATRIXI_PRE_OFFSET0_1 = OSD2_HDR2_MATRIXI_PRE_OFFSET0_1;
+ MATRIXI_PRE_OFFSET2 = OSD2_HDR2_MATRIXI_PRE_OFFSET2;
+ /*MATRIXI_CLIP = OSD2_HDR2_MATRIXI_CLIP;*/
+ MATRIXI_EN_CTRL = OSD2_HDR2_MATRIXI_EN_CTRL;
+
+ MATRIXO_COEF00_01 = OSD2_HDR2_MATRIXO_COEF00_01;
+ MATRIXO_COEF00_01 = OSD2_HDR2_MATRIXO_COEF00_01;
+ MATRIXO_COEF02_10 = OSD2_HDR2_MATRIXO_COEF02_10;
+ MATRIXO_COEF11_12 = OSD2_HDR2_MATRIXO_COEF11_12;
+ MATRIXO_COEF20_21 = OSD2_HDR2_MATRIXO_COEF20_21;
+ MATRIXO_COEF22 = OSD2_HDR2_MATRIXO_COEF22;
+ /*MATRIXO_COEF30_31 = OSD2_HDR2_MATRIXO_COEF30_31;*/
+ /*MATRIXO_COEF32_40 = OSD2_HDR2_MATRIXO_COEF32_40;*/
+ /*MATRIXO_COEF41_42 = OSD2_HDR2_MATRIXO_COEF41_42;*/
+ MATRIXO_OFFSET0_1 = OSD2_HDR2_MATRIXO_OFFSET0_1;
+ MATRIXO_OFFSET2 = OSD2_HDR2_MATRIXO_OFFSET2;
+ MATRIXO_PRE_OFFSET0_1 = OSD2_HDR2_MATRIXO_PRE_OFFSET0_1;
+ MATRIXO_PRE_OFFSET2 = OSD2_HDR2_MATRIXO_PRE_OFFSET2;
+ /*MATRIXO_CLIP = OSD2_HDR2_MATRIXO_CLIP;*/
+ MATRIXO_EN_CTRL = OSD2_HDR2_MATRIXO_EN_CTRL;
+
+ CGAIN_OFFT = OSD2_HDR2_CGAIN_OFFT;
+ CGAIN_COEF0 = OSD2_HDR2_CGAIN_COEF0;
+ CGAIN_COEF1 = OSD2_HDR2_CGAIN_COEF1;
+ ADPS_CTRL = OSD2_HDR2_ADPS_CTRL;
+ ADPS_ALPHA0 = OSD2_HDR2_ADPS_ALPHA0;
+ ADPS_ALPHA1 = OSD2_HDR2_ADPS_ALPHA1;
+ ADPS_BETA0 = OSD2_HDR2_ADPS_BETA0;
+ ADPS_BETA1 = OSD2_HDR2_ADPS_BETA1;
+ ADPS_BETA2 = OSD2_HDR2_ADPS_BETA2;
+ ADPS_COEF0 = OSD2_HDR2_ADPS_COEF0;
+ ADPS_COEF1 = OSD2_HDR2_ADPS_COEF1;
+ GMUT_CTRL = OSD2_HDR2_GMUT_CTRL;
+ GMUT_COEF0 = OSD2_HDR2_GMUT_COEF0;
+ GMUT_COEF1 = OSD2_HDR2_GMUT_COEF1;
+ GMUT_COEF2 = OSD2_HDR2_GMUT_COEF2;
+ GMUT_COEF3 = OSD2_HDR2_GMUT_COEF3;
+ GMUT_COEF4 = OSD2_HDR2_GMUT_COEF4;
+
+ hdr_ctrl = OSD2_HDR2_CTRL;
+ }
+
+ if (!hdr_mtx_param)
+ return;
+ vpp_reg_setb(hdr_ctrl, hdr_mtx_param->mtx_on, 13, 1);
+
+ if (mtx_sel & HDR_IN_MTX) {
+ for (i = 0; i < 15; i++)
+ mtx[i] = hdr_mtx_param->mtx_in[i];
+
+ if (hdr_mtx_param->mtx_only == MTX_ONLY &&
+ !hdr_mtx_param->mtx_on)
+ vpp_reg_write(MATRIXI_EN_CTRL, 1);
+ else
+ vpp_reg_write(MATRIXI_EN_CTRL,
+ hdr_mtx_param->mtx_on);
+ /*yuv in*/
+ vpp_reg_setb(hdr_ctrl, hdr_mtx_param->mtx_on, 4, 1);
+
+ vpp_reg_setb(hdr_ctrl, hdr_mtx_param->mtx_only,
+ 16, 1);
+ vpp_reg_setb(hdr_ctrl, 0, 17, 1);
+ /*mtx in en*/
+ vpp_reg_setb(hdr_ctrl, 1, 14, 1);
+
+ vpp_reg_write(MATRIXI_COEF00_01,
+ (mtx[0 * 3 + 0] << 16) |
+ (mtx[0 * 3 + 1] & 0x1FFF));
+ vpp_reg_write(MATRIXI_COEF02_10,
+ (mtx[0 * 3 + 2] << 16) |
+ (mtx[1 * 3 + 0] & 0x1FFF));
+ vpp_reg_write(MATRIXI_COEF11_12,
+ (mtx[1 * 3 + 1] << 16) |
+ (mtx[1 * 3 + 2] & 0x1FFF));
+ vpp_reg_write(MATRIXI_COEF20_21,
+ (mtx[2 * 3 + 0] << 16) |
+ (mtx[2 * 3 + 1] & 0x1FFF));
+ vpp_reg_write(MATRIXI_COEF22,
+ mtx[2 * 3 + 2]);
+ vpp_reg_write(MATRIXI_OFFSET0_1,
+ (hdr_mtx_param->mtxi_pos_offset[0] << 16) |
+ (hdr_mtx_param->mtxi_pos_offset[1] & 0xFFF));
+ vpp_reg_write(MATRIXI_OFFSET2,
+ hdr_mtx_param->mtxi_pos_offset[2]);
+ vpp_reg_write(MATRIXI_PRE_OFFSET0_1,
+ (hdr_mtx_param->mtxi_pre_offset[0] << 16) |
+ (hdr_mtx_param->mtxi_pre_offset[1] & 0xFFF));
+ vpp_reg_write(MATRIXI_PRE_OFFSET2,
+ hdr_mtx_param->mtxi_pre_offset[2]);
+
+ } else if (mtx_sel & HDR_GAMUT_MTX) {
+ for (i = 0; i < 9; i++)
+ gmut_coef[i / 3][i % 3] =
+ hdr_mtx_param->mtx_gamut[i];
+ /*for g12a/g12b osd blend shift rtl bug*/
+ if ((get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_G12A) &&
+ (hdr_mtx_param->p_sel & HDR_BYPASS) &&
+ (module_sel & (OSD1_HDR | OSD1_HDR)))
+ gmut_shift = 10;
+ else
+ gmut_shift = 11;
+
+ for (i = 0; i < 3; i++)
+ c_gain_lim_coef[i] =
+ hdr_mtx_param->mtx_cgain[i] << 2;
+ /*0, nolinear input, 1, max linear, 2, adpscl mode*/
+ adpscl_mode = 1;
+ for (i = 0; i < 3; i++) {
+ if ((get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_G12A) &&
+ (hdr_mtx_param->p_sel & HDR_BYPASS) &&
+ (module_sel & (OSD1_HDR | OSD2_HDR)))
+ adpscl_enable[i] = 1;
+ else
+ adpscl_enable[i] = 0;
+ if (hdr_mtx_param->p_sel & HDR_SDR)
+ adpscl_alpha[i] =
+ (1 << adp_scal_shift);
+ else if (hdr_mtx_param->p_sel & SDR_HDR)
+ adpscl_alpha[i] =
+ (1 << adp_scal_shift);
+ else if (hdr_mtx_param->p_sel & HDR_BYPASS)
+ adpscl_alpha[i] = 1 *
+ (1 << adp_scal_shift) / in_luma;
+ else if (hdr_mtx_param->p_sel & HLG_SDR) {
+ adpscl_alpha[i] = out_luma *
+ (1 << adp_scal_shift) / in_luma;
+ adpscl_mode = 2;
+ } else if (hdr_mtx_param->p_sel & HLG_HDR)
+ adpscl_alpha[i] = 1 *
+ (1 << adp_scal_shift) / in_luma;
+ else if (hdr_mtx_param->p_sel & SDR_HLG)
+ adpscl_alpha[i] = 10 * in_luma *
+ (1 << adp_scal_shift) / out_luma;
+
+ if (hdr_mtx_param->p_sel & HDR_SDR) {
+ if (i == 0)
+ adpscl_shift[i] = adp_scal_shift;
+ else
+ adpscl_shift[i] = adp_scal_shift - 2;
+ } else {
+ /* shift value keep consistent with kernel */
+ if (i == 1)
+ adpscl_shift[i] = adp_scal_shift - 1;
+ else
+ adpscl_shift[i] = adp_scal_shift;
+ }
+
+ adpscl_ys_coef[i] =
+ 1 << adp_scal_shift;
+ adpscl_beta_s[i] = 0;
+ adpscl_beta[i] = 0;
+ }
+
+ /*gamut mode: 1->gamut before ootf*/
+ /*2->gamut after ootf*/
+ /*other->disable gamut*/
+ vpp_reg_setb(hdr_ctrl, 1, 6, 2);
+
+ vpp_reg_write(GMUT_CTRL, gmut_shift);
+ vpp_reg_write(GMUT_COEF0,
+ (gmut_coef[0][1] & 0xffff) << 16 |
+ (gmut_coef[0][0] & 0xffff));
+ vpp_reg_write(GMUT_COEF1,
+ (gmut_coef[1][0] & 0xffff) << 16 |
+ (gmut_coef[0][2] & 0xffff));
+ vpp_reg_write(GMUT_COEF2,
+ (gmut_coef[1][2] & 0xffff) << 16 |
+ (gmut_coef[1][1] & 0xffff));
+ vpp_reg_write(GMUT_COEF3,
+ (gmut_coef[2][1] & 0xffff) << 16 |
+ (gmut_coef[2][0] & 0xffff));
+ vpp_reg_write(GMUT_COEF4,
+ gmut_coef[2][2] & 0xffff);
+
+ vpp_reg_write(CGAIN_COEF0,
+ c_gain_lim_coef[1] << 16 |
+ c_gain_lim_coef[0]);
+ vpp_reg_write(CGAIN_COEF1, c_gain_lim_coef[2] |
+ 0x1000 << 16);
+
+ vpp_reg_write(ADPS_CTRL, adpscl_enable[2] << 6 |
+ adpscl_enable[1] << 5 |
+ adpscl_enable[0] << 4 |
+ adpscl_mode);
+ vpp_reg_write(ADPS_ALPHA0,
+ adpscl_alpha[1] << 16 | adpscl_alpha[0]);
+ vpp_reg_write(ADPS_ALPHA1, adpscl_shift[0] << 24 |
+ adpscl_shift[1] << 20 |
+ adpscl_shift[2] << 16 |
+ adpscl_alpha[2]);
+ vpp_reg_write(ADPS_BETA0,
+ adpscl_beta_s[0] << 20 | adpscl_beta[0]);
+ vpp_reg_write(ADPS_BETA1,
+ adpscl_beta_s[1] << 20 | adpscl_beta[1]);
+ vpp_reg_write(ADPS_BETA2,
+ adpscl_beta_s[2] << 20 | adpscl_beta[2]);
+ vpp_reg_write(ADPS_COEF0,
+ adpscl_ys_coef[1] << 16 | adpscl_ys_coef[0]);
+ vpp_reg_write(ADPS_COEF1, adpscl_ys_coef[2]);
+
+ } else if (mtx_sel & HDR_OUT_MTX) {
+ for (i = 0; i < 15; i++)
+ mtx[i] = hdr_mtx_param->mtx_out[i];
+ vpp_reg_write(CGAIN_OFFT,
+ (rgb2yuvpos[2] << 16) | rgb2yuvpos[1]);
+ vpp_reg_write(MATRIXO_EN_CTRL, hdr_mtx_param->mtx_on);
+ /*yuv in*/
+ vpp_reg_setb(hdr_ctrl, hdr_mtx_param->mtx_on, 4, 1);
+
+ vpp_reg_setb(hdr_ctrl, hdr_mtx_param->mtx_only,
+ 16, 1);
+ vpp_reg_setb(hdr_ctrl, 0, 17, 1);
+ /*mtx out en*/
+ vpp_reg_setb(hdr_ctrl, 1, 15, 1);
+
+ vpp_reg_write(MATRIXO_COEF00_01,
+ (mtx[0 * 3 + 0] << 16) |
+ (mtx[0 * 3 + 1] & 0x1FFF));
+ vpp_reg_write(MATRIXO_COEF02_10,
+ (mtx[0 * 3 + 2] << 16) |
+ (mtx[1 * 3 + 0] & 0x1FFF));
+ vpp_reg_write(MATRIXO_COEF11_12,
+ (mtx[1 * 3 + 1] << 16) |
+ (mtx[1 * 3 + 2] & 0x1FFF));
+ vpp_reg_write(MATRIXO_COEF20_21,
+ (mtx[2 * 3 + 0] << 16) |
+ (mtx[2 * 3 + 1] & 0x1FFF));
+ vpp_reg_write(MATRIXO_COEF22,
+ mtx[2 * 3 + 2]);
+ vpp_reg_write(MATRIXO_OFFSET0_1,
+ (hdr_mtx_param->mtxo_pos_offset[0] << 16) |
+ (hdr_mtx_param->mtxo_pos_offset[1] & 0xFFF));
+ vpp_reg_write(MATRIXO_OFFSET2,
+ hdr_mtx_param->mtxo_pos_offset[2]);
+ vpp_reg_write(MATRIXO_PRE_OFFSET0_1,
+ (hdr_mtx_param->mtxo_pre_offset[0] << 16) |
+ (hdr_mtx_param->mtxo_pre_offset[1] & 0xFFF));
+ vpp_reg_write(MATRIXO_PRE_OFFSET2,
+ hdr_mtx_param->mtxo_pre_offset[2]);
+ }
+}
+
+void set_eotf_lut(enum hdr_module_sel module_sel,
+ struct hdr_proc_lut_param_s *hdr_lut_param)
+{
+ unsigned int lut[HDR2_EOTF_LUT_SIZE];
+ unsigned int eotf_lut_addr_port = 0;
+ unsigned int eotf_lut_data_port = 0;
+ unsigned int hdr_ctrl = 0;
+ unsigned int i = 0;
+
+ if (module_sel & VD1_HDR) {
+ eotf_lut_addr_port = VD1_EOTF_LUT_ADDR_PORT;
+ eotf_lut_data_port = VD1_EOTF_LUT_DATA_PORT;
+ hdr_ctrl = VD1_HDR2_CTRL;
+ } else if (module_sel & VD2_HDR) {
+ eotf_lut_addr_port = VD2_EOTF_LUT_ADDR_PORT;
+ eotf_lut_data_port = VD2_EOTF_LUT_DATA_PORT;
+ hdr_ctrl = VD2_HDR2_CTRL;
+ } else if (module_sel & OSD1_HDR) {
+ eotf_lut_addr_port = OSD1_EOTF_LUT_ADDR_PORT;
+ eotf_lut_data_port = OSD1_EOTF_LUT_DATA_PORT;
+ hdr_ctrl = OSD1_HDR2_CTRL;
+ } else if (module_sel & OSD2_HDR) {
+ eotf_lut_addr_port = OSD2_EOTF_LUT_ADDR_PORT;
+ eotf_lut_data_port = OSD2_EOTF_LUT_DATA_PORT;
+ hdr_ctrl = OSD2_HDR2_CTRL;
+ }
+
+ for (i = 0; i < HDR2_EOTF_LUT_SIZE; i++)
+ lut[i] = hdr_lut_param->eotf_lut[i];
+
+ vpp_reg_setb(hdr_ctrl, hdr_lut_param->lut_on, 3, 1);
+
+ if (!hdr_lut_param->lut_on)
+ return;
+
+ vpp_reg_write(eotf_lut_addr_port, 0x0);
+ for (i = 0; i < HDR2_EOTF_LUT_SIZE; i++)
+ vpp_reg_write(eotf_lut_data_port, lut[i]);
+}
+
+void set_ootf_lut(enum hdr_module_sel module_sel,
+ struct hdr_proc_lut_param_s *hdr_lut_param)
+{
+ unsigned int lut[HDR2_OOTF_LUT_SIZE];
+ unsigned int ootf_lut_addr_port = 0;
+ unsigned int ootf_lut_data_port = 0;
+ unsigned int hdr_ctrl = 0;
+ unsigned int i = 0;
+
+ if (module_sel & VD1_HDR) {
+ ootf_lut_addr_port = VD1_OGAIN_LUT_ADDR_PORT;
+ ootf_lut_data_port = VD1_OGAIN_LUT_DATA_PORT;
+ hdr_ctrl = VD1_HDR2_CTRL;
+ } else if (module_sel & VD2_HDR) {
+ ootf_lut_addr_port = VD2_OGAIN_LUT_ADDR_PORT;
+ ootf_lut_data_port = VD2_OGAIN_LUT_DATA_PORT;
+ hdr_ctrl = VD2_HDR2_CTRL;
+ } else if (module_sel & OSD1_HDR) {
+ ootf_lut_addr_port = OSD1_OGAIN_LUT_ADDR_PORT;
+ ootf_lut_data_port = OSD1_OGAIN_LUT_DATA_PORT;
+ hdr_ctrl = OSD1_HDR2_CTRL;
+ } else if (module_sel & OSD2_HDR) {
+ ootf_lut_addr_port = OSD2_OGAIN_LUT_ADDR_PORT;
+ ootf_lut_data_port = OSD2_OGAIN_LUT_DATA_PORT;
+ hdr_ctrl = OSD2_HDR2_CTRL;
+ }
+
+ for (i = 0; i < HDR2_OOTF_LUT_SIZE; i++)
+ lut[i] = hdr_lut_param->ogain_lut[i];
+
+ vpp_reg_setb(hdr_ctrl, hdr_lut_param->lut_on, 1, 1);
+
+ if (!hdr_lut_param->lut_on)
+ return;
+
+ vpp_reg_write(ootf_lut_addr_port, 0x0);
+ for (i = 0; i < HDR2_OOTF_LUT_SIZE / 2; i++)
+ vpp_reg_write(ootf_lut_data_port,
+ (lut[i * 2 + 1] << 16) +
+ lut[i * 2]);
+ vpp_reg_write(ootf_lut_data_port, lut[148]);
+}
+
+void set_oetf_lut(enum hdr_module_sel module_sel,
+ struct hdr_proc_lut_param_s *hdr_lut_param)
+{
+ unsigned int lut[HDR2_OETF_LUT_SIZE];
+ unsigned int oetf_lut_addr_port = 0;
+ unsigned int oetf_lut_data_port = 0;
+ unsigned int hdr_ctrl = 0;
+ unsigned int i = 0;
+
+ if (module_sel & VD1_HDR) {
+ oetf_lut_addr_port = VD1_OETF_LUT_ADDR_PORT;
+ oetf_lut_data_port = VD1_OETF_LUT_DATA_PORT;
+ hdr_ctrl = VD1_HDR2_CTRL;
+ } else if (module_sel & VD2_HDR) {
+ oetf_lut_addr_port = VD2_OETF_LUT_ADDR_PORT;
+ oetf_lut_data_port = VD2_OETF_LUT_DATA_PORT;
+ hdr_ctrl = VD2_HDR2_CTRL;
+ } else if (module_sel & OSD1_HDR) {
+ oetf_lut_addr_port = OSD1_OETF_LUT_ADDR_PORT;
+ oetf_lut_data_port = OSD1_OETF_LUT_DATA_PORT;
+ hdr_ctrl = OSD1_HDR2_CTRL;
+ } else if (module_sel & OSD2_HDR) {
+ oetf_lut_addr_port = OSD2_OETF_LUT_ADDR_PORT;
+ oetf_lut_data_port = OSD2_OETF_LUT_DATA_PORT;
+ hdr_ctrl = OSD2_HDR2_CTRL;
+ }
+
+ for (i = 0; i < HDR2_OETF_LUT_SIZE; i++)
+ lut[i] = hdr_lut_param->oetf_lut[i];
+
+ vpp_reg_setb(hdr_ctrl, hdr_lut_param->lut_on, 2, 1);
+
+ if (!hdr_lut_param->lut_on)
+ return;
+
+ vpp_reg_write(oetf_lut_addr_port, 0x0);
+ for (i = 0; i < HDR2_OETF_LUT_SIZE / 2; i++) {
+ if (hdr_lut_param->bitdepth == 10)
+ vpp_reg_write(oetf_lut_data_port,
+ ((lut[i * 2 + 1] >> 2) << 16) +
+ (lut[i * 2] >> 2));
+ else
+ vpp_reg_write(oetf_lut_data_port,
+ (lut[i * 2 + 1] << 16) +
+ lut[i * 2]);
+ }
+ vpp_reg_write(oetf_lut_data_port, lut[148]);
+}
+
+void set_c_gain(enum hdr_module_sel module_sel,
+ struct hdr_proc_lut_param_s *hdr_lut_param)
+{
+ unsigned int lut[HDR2_CGAIN_LUT_SIZE];
+ unsigned int cgain_lut_addr_port = 0;
+ unsigned int cgain_lut_data_port = 0;
+ unsigned int hdr_ctrl = 0;
+ unsigned int i = 0;
+
+ if (module_sel & VD1_HDR) {
+ cgain_lut_addr_port = VD1_CGAIN_LUT_ADDR_PORT;
+ cgain_lut_data_port = VD1_CGAIN_LUT_DATA_PORT;
+ hdr_ctrl = VD1_HDR2_CTRL;
+ } else if (module_sel & VD2_HDR) {
+ cgain_lut_addr_port = VD2_CGAIN_LUT_ADDR_PORT;
+ cgain_lut_data_port = VD2_CGAIN_LUT_DATA_PORT;
+ hdr_ctrl = VD2_HDR2_CTRL;
+ } else if (module_sel & OSD1_HDR) {
+ cgain_lut_addr_port = OSD1_CGAIN_LUT_ADDR_PORT;
+ cgain_lut_data_port = OSD1_CGAIN_LUT_DATA_PORT;
+ hdr_ctrl = OSD1_HDR2_CTRL;
+ } else if (module_sel & OSD2_HDR) {
+ cgain_lut_addr_port = OSD2_CGAIN_LUT_ADDR_PORT;
+ cgain_lut_data_port = OSD2_CGAIN_LUT_DATA_PORT;
+ hdr_ctrl = OSD2_HDR2_CTRL;
+ }
+
+ for (i = 0; i < HDR2_CGAIN_LUT_SIZE; i++)
+ lut[i] = hdr_lut_param->cgain_lut[i];
+
+ /*cgain mode: 0->y domin*/
+ /*cgain mode: 1->rgb domin, use r/g/b max*/
+ vpp_reg_setb(hdr_ctrl, 0, 12, 1);
+ vpp_reg_setb(hdr_ctrl, hdr_lut_param->cgain_en, 0, 1);
+
+ if (!hdr_lut_param->cgain_en)
+ return;
+
+ vpp_reg_write(cgain_lut_addr_port, 0x0);
+ for (i = 0; i < HDR2_CGAIN_LUT_SIZE / 2; i++)
+ vpp_reg_write(cgain_lut_data_port,
+ (lut[i * 2 + 1] << 16) + lut[i * 2]);
+ vpp_reg_write(cgain_lut_data_port, lut[64]);
+}
+
+void clip_func_after_ootf(int mtx_gamut_mode,
+ enum hdr_module_sel module_sel)
+{
+ unsigned int asps_ctrl = 0;
+ int clip_en = 0;
+ int clip_max = 0;
+
+ /* if Dynamic TMO+ enable : clip_en = 1 clip_max = 524288
+ * (hdr_process_select is HDR_SDR or HDR10P_SDR);
+ * else if mtx_gamut_mode = 1 : clip_en = 0/1 clip_max = 524288;
+ * else if mtx_gamut_mode == 2 : clip_en = 1 clip_max = 393216;
+ * else : clip_en = 0 clip_max = 524288;
+ */
+ if (mtx_gamut_mode == 1) {
+ clip_max = 524288 >> 14;
+ } else if (mtx_gamut_mode == 2) {
+ clip_en = 1;
+ clip_max = 393216 >> 14;
+ } else {
+ clip_en = 0;
+ clip_max = 524288 >> 14;
+ }
+
+ if (module_sel & VD1_HDR)
+ asps_ctrl = VD1_HDR2_ADPS_CTRL;
+ else if (module_sel & VD2_HDR)
+ asps_ctrl = VD2_HDR2_ADPS_CTRL;
+ else if (module_sel & OSD1_HDR)
+ asps_ctrl = OSD1_HDR2_ADPS_CTRL;
+ else
+ return;
+
+ vpp_reg_setb(asps_ctrl,
+ clip_en, 7, 1);
+ vpp_reg_setb(asps_ctrl,
+ clip_max, 8, 6);
+}
+
+struct hdr_proc_lut_param_s hdr_lut_param;
+
+void hdr_func(enum hdr_module_sel module_sel,
+ enum hdr_process_sel hdr_process_select)
+{
+ int bit_depth;
+ unsigned int i = 0;
+ struct hdr_proc_mtx_param_s hdr_mtx_param;
+
+ printf("%s: %d, hdr_process_select 0x%x\n",
+ __func__, module_sel, hdr_process_select);
+
+ if (get_cpu_id().family_id != MESON_CPU_MAJOR_ID_T7 &&
+ (module_sel == OSD2_HDR ||
+ module_sel == VD3_HDR))
+ return;
+
+ memset(&hdr_mtx_param, 0, sizeof(struct hdr_proc_mtx_param_s));
+ memset(&hdr_lut_param, 0, sizeof(struct hdr_proc_lut_param_s));
+
+ if (module_sel & (VD1_HDR | VD2_HDR | VD3_HDR | OSD1_HDR | OSD2_HDR)) {
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_S4 ||
+ get_cpu_id().family_id == MESON_CPU_MAJOR_ID_T3)
+ bit_depth = 10;
+ else
+ bit_depth = 12;
+ } else if (module_sel & (VDIN0_HDR | VDIN1_HDR | DI_HDR)) {
+ bit_depth = 10;
+ } else {
+ return;
+ }
+
+ /*lut parameters*/
+ if (hdr_process_select & (HDR_BYPASS | RGB_BYPASS)) {
+ /*for g12a/g12b osd blend shift rtl bug*/
+ if ((get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_G12A) &&
+ (module_sel & (OSD1_HDR | OSD2_HDR | VD1_HDR | VD2_HDR))) {
+ for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) {
+ hdr_lut_param.oetf_lut[i] = oe_y_lut_bypass[i];
+ hdr_lut_param.ogain_lut[i] = OO_Y_LUT_BYPASS_VAL;
+ if (i < HDR2_EOTF_LUT_SIZE)
+ hdr_lut_param.eotf_lut[i] =
+ eo_y_lut_bypass[i];
+ if (i < HDR2_CGAIN_LUT_SIZE)
+ hdr_lut_param.cgain_lut[i] =
+ cgain_lut_bypass[i] - 1;
+ }
+ hdr_lut_param.lut_on = LUT_ON;
+ hdr_lut_param.bitdepth = bit_depth;
+ hdr_lut_param.cgain_en = LUT_ON;
+ } else {
+ for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) {
+ hdr_lut_param.oetf_lut[i] = oe_y_lut_sdr[i];
+ hdr_lut_param.ogain_lut[i] =
+ oo_y_lut_hdr_sdr[i];
+ if (i < HDR2_EOTF_LUT_SIZE)
+ hdr_lut_param.eotf_lut[i] =
+ eo_y_lut_hdr[i];
+ if (i < HDR2_CGAIN_LUT_SIZE)
+ hdr_lut_param.cgain_lut[i] =
+ cgain_lut1[i] - 1;
+ }
+ hdr_lut_param.lut_on = LUT_OFF;
+ hdr_lut_param.bitdepth = bit_depth;
+ hdr_lut_param.cgain_en = LUT_OFF;
+ }
+ } else if (hdr_process_select & HDR_SDR) {
+ for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) {
+ hdr_lut_param.oetf_lut[i] = oe_y_lut_sdr[i];
+ hdr_lut_param.ogain_lut[i] = oo_y_lut_hdr_sdr[i];
+ if (i < HDR2_EOTF_LUT_SIZE)
+ hdr_lut_param.eotf_lut[i] = eo_y_lut_hdr[i];
+ if (i < HDR2_CGAIN_LUT_SIZE)
+ hdr_lut_param.cgain_lut[i] = cgain_lut1[i] - 1;
+ }
+ hdr_lut_param.lut_on = LUT_ON;
+ hdr_lut_param.bitdepth = bit_depth;
+ hdr_lut_param.cgain_en = LUT_ON;
+ } else if (hdr_process_select & SDR_HDR) {
+ for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) {
+ hdr_lut_param.oetf_lut[i] = oe_y_lut_hdr[i];
+ hdr_lut_param.ogain_lut[i] = oo_y_lut_sdr_hdr[i];
+ if (i < HDR2_EOTF_LUT_SIZE)
+ hdr_lut_param.eotf_lut[i] = eo_y_lut_sdr[i];
+ if (i < HDR2_CGAIN_LUT_SIZE)
+ hdr_lut_param.cgain_lut[i] =
+ cgain_lut_bypass[i] - 1;
+ }
+ hdr_lut_param.lut_on = LUT_ON;
+ hdr_lut_param.bitdepth = bit_depth;
+ /*for g12a/g12b osd blend shift rtl bug*/
+ if ((get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_G12A) &&
+ (module_sel & (OSD1_HDR | OSD2_HDR)))
+ hdr_lut_param.cgain_en = LUT_ON;
+ else
+ hdr_lut_param.cgain_en = LUT_OFF;
+ } else if (hdr_process_select & HLG_BYPASS) {
+ for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) {
+ hdr_lut_param.oetf_lut[i] = oe_y_lut_sdr[i];
+ hdr_lut_param.ogain_lut[i] = oo_y_lut_hdr_sdr[i];
+ if (i < HDR2_EOTF_LUT_SIZE)
+ hdr_lut_param.eotf_lut[i] = eo_y_lut_hlg[i];
+ if (i < HDR2_CGAIN_LUT_SIZE)
+ hdr_lut_param.cgain_lut[i] = cgain_lut1[i] - 1;
+ }
+ hdr_lut_param.lut_on = LUT_OFF;
+ hdr_lut_param.bitdepth = bit_depth;
+ hdr_lut_param.cgain_en = LUT_OFF;
+ } else if (hdr_process_select & HLG_SDR) {
+ for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) {
+ hdr_lut_param.oetf_lut[i] = oe_y_lut_sdr[i];
+ hdr_lut_param.ogain_lut[i] = oo_y_lut_hlg_sdr[i];
+ if (i < HDR2_EOTF_LUT_SIZE)
+ hdr_lut_param.eotf_lut[i] = eo_y_lut_hlg[i];
+ if (i < HDR2_CGAIN_LUT_SIZE)
+ hdr_lut_param.cgain_lut[i] = cgain_lut1[i] - 1;
+ }
+ hdr_lut_param.lut_on = LUT_ON;
+ hdr_lut_param.bitdepth = bit_depth;
+ hdr_lut_param.cgain_en = LUT_ON;
+ } else if (hdr_process_select & HLG_HDR) {
+ for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) {
+ hdr_lut_param.oetf_lut[i] = oe_y_lut_hdr[i];
+ hdr_lut_param.ogain_lut[i] = oo_y_lut_hlg_hdr[i];
+ if (i < HDR2_EOTF_LUT_SIZE)
+ hdr_lut_param.eotf_lut[i] = eo_y_lut_hlg[i];
+ if (i < HDR2_CGAIN_LUT_SIZE)
+ hdr_lut_param.cgain_lut[i] = cgain_lut1[i] - 1;
+ }
+ hdr_lut_param.lut_on = LUT_ON;
+ hdr_lut_param.bitdepth = bit_depth;
+ hdr_lut_param.cgain_en = LUT_ON;
+ } else if (hdr_process_select & SDR_HLG) {
+ for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) {
+ hdr_lut_param.oetf_lut[i] = oe_y_lut_hlg[i];
+ hdr_lut_param.ogain_lut[i] = oo_y_lut_sdr_hlg[i];
+ if (i < HDR2_EOTF_LUT_SIZE)
+ hdr_lut_param.eotf_lut[i] = eo_y_lut_sdr[i];
+ if (i < HDR2_CGAIN_LUT_SIZE)
+ hdr_lut_param.cgain_lut[i] =
+ cgain_lut_bypass[i] - 1;
+ }
+ hdr_lut_param.lut_on = LUT_ON;
+ hdr_lut_param.bitdepth = bit_depth;
+ /*for g12a/g12b osd blend shift rtl bug*/
+ if (((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) ||
+ (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B)) &&
+ (module_sel & (OSD1_HDR | OSD2_HDR)))
+ hdr_lut_param.cgain_en = LUT_ON;
+ else
+ hdr_lut_param.cgain_en = LUT_OFF;
+ } else if (hdr_process_select & HDR_OFF) {
+ for (i = 0; i < HDR2_OETF_LUT_SIZE; i++) {
+ hdr_lut_param.oetf_lut[i] = oe_y_lut_sdr[i];
+ hdr_lut_param.ogain_lut[i] =
+ oo_y_lut_hdr_sdr[i];
+ if (i < HDR2_EOTF_LUT_SIZE)
+ hdr_lut_param.eotf_lut[i] =
+ eo_y_lut_hdr[i];
+ if (i < HDR2_CGAIN_LUT_SIZE)
+ hdr_lut_param.cgain_lut[i] =
+ cgain_lut1[i] - 1;
+ }
+ hdr_lut_param.lut_on = LUT_OFF;
+ hdr_lut_param.bitdepth = bit_depth;
+ hdr_lut_param.cgain_en = LUT_OFF;
+ } else {
+ return;
+ }
+ /*mtx parameters*/
+ if (hdr_process_select & (HDR_BYPASS | HLG_BYPASS)) {
+ hdr_mtx_param.mtx_only = HDR_ONLY;
+ hdr_mtx_param.mtx_gamut_mode = 1;
+ /*for g12a/g12b osd blend shift rtl bug*/
+ if (((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) ||
+ (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B &&
+ get_cpu_id().chip_rev == MESON_CPU_CHIP_REVISION_A)) &&
+ (hdr_process_select & HDR_BYPASS) &&
+ (module_sel & (OSD1_HDR | OSD2_HDR | VD1_HDR | VD2_HDR))) {
+ for (i = 0; i < 15; i++) {
+ hdr_mtx_param.mtx_in[i] = bypass_coeff[i];
+ hdr_mtx_param.mtx_cgain[i] = bypass_coeff[i];
+ hdr_mtx_param.mtx_ogain[i] = bypass_coeff[i];
+ if (module_sel & (OSD1_HDR | OSD2_HDR))
+ hdr_mtx_param.mtx_out[i] = rgb2ycbcr_709[i];
+ else
+ hdr_mtx_param.mtx_out[i] = bypass_coeff[i];
+ if (i < 9)
+ hdr_mtx_param.mtx_gamut[i] =
+ bypass_coeff[i];
+ if (i < 3) {
+ hdr_mtx_param.mtxi_pre_offset[i] =
+ bypass_pre[i];
+ hdr_mtx_param.mtxi_pos_offset[i] =
+ bypass_pos[i];
+ if (module_sel & (OSD1_HDR | OSD2_HDR)) {
+ hdr_mtx_param.mtxo_pre_offset[i] =
+ rgb2yuvpre[i];
+ hdr_mtx_param.mtxo_pos_offset[i] =
+ rgb2yuvpos[i];
+ } else {
+ hdr_mtx_param.mtxo_pre_offset[i] =
+ bypass_pre[i];
+ hdr_mtx_param.mtxo_pos_offset[i] =
+ bypass_pos[i];
+ }
+ }
+ }
+ hdr_mtx_param.mtx_on = MTX_ON;
+ hdr_mtx_param.p_sel = HDR_BYPASS;
+ } else if (((get_cpu_id().family_id >=
+ MESON_CPU_MAJOR_ID_SM1) ||
+ (get_cpu_id().family_id ==
+ MESON_CPU_MAJOR_ID_G12B &&
+ get_cpu_id().chip_rev ==
+ MESON_CPU_CHIP_REVISION_B)) &&
+ (module_sel & (OSD1_HDR | OSD1_HDR | VD1_HDR | VD2_HDR))) {
+ for (i = 0; i < 15; i++) {
+ if (module_sel & (OSD1_HDR| OSD2_HDR))
+ hdr_mtx_param.mtx_in[i] = rgb2ycbcr_709[i];
+ else
+ hdr_mtx_param.mtx_in[i] = bypass_coeff[i];
+ hdr_mtx_param.mtx_cgain[i] = bypass_coeff[i];
+ hdr_mtx_param.mtx_ogain[i] = bypass_coeff[i];
+ hdr_mtx_param.mtx_out[i] = bypass_coeff[i];
+ if (i < 9)
+ hdr_mtx_param.mtx_gamut[i] =
+ gamut_bypass[i];
+ if (i < 3) {
+ if (module_sel & (OSD1_HDR | OSD2_HDR)) {
+ hdr_mtx_param.mtxi_pre_offset[i] =
+ rgb2yuvpre[i];
+ hdr_mtx_param.mtxi_pos_offset[i] =
+ rgb2yuvpos[i];
+ } else {
+ hdr_mtx_param.mtxi_pre_offset[i] =
+ bypass_pre[i];
+ hdr_mtx_param.mtxi_pos_offset[i] =
+ bypass_pos[i];
+ }
+ hdr_mtx_param.mtxo_pre_offset[i] =
+ bypass_pre[i];
+ hdr_mtx_param.mtxo_pos_offset[i] =
+ bypass_pos[i];
+ }
+ }
+ if (module_sel & (OSD1_HDR | OSD2_HDR)) {
+ hdr_mtx_param.mtx_on = MTX_OFF;
+ hdr_mtx_param.p_sel = HDR_BYPASS;
+ hdr_mtx_param.mtx_only = MTX_ONLY;
+ } else {
+ hdr_mtx_param.mtx_on = MTX_ON;
+ hdr_mtx_param.p_sel = HDR_BYPASS;
+ hdr_mtx_param.mtx_only = HDR_ONLY;
+ }
+ } else {
+ for (i = 0; i < 15; i++) {
+ hdr_mtx_param.mtx_in[i] = bypass_coeff[i];
+ hdr_mtx_param.mtx_cgain[i] = bypass_coeff[i];
+ hdr_mtx_param.mtx_ogain[i] = bypass_coeff[i];
+ hdr_mtx_param.mtx_out[i] = bypass_coeff[i];
+ if (i < 9)
+ hdr_mtx_param.mtx_gamut[i] =
+ bypass_coeff[i];
+ if (i < 3) {
+ hdr_mtx_param.mtxi_pre_offset[i] =
+ bypass_pre[i];
+ hdr_mtx_param.mtxi_pos_offset[i] =
+ bypass_pre[i];
+ hdr_mtx_param.mtxo_pre_offset[i] =
+ bypass_pre[i];
+ hdr_mtx_param.mtxo_pos_offset[i] =
+ bypass_pos[i];
+ }
+ }
+ hdr_mtx_param.mtx_on = MTX_OFF;
+ hdr_mtx_param.p_sel = HDR_BYPASS;
+ }
+ } else if (hdr_process_select & (HDR_SDR | HLG_SDR)) {
+ hdr_mtx_param.mtx_only = HDR_ONLY;
+ hdr_mtx_param.mtx_gamut_mode = 1;
+ for (i = 0; i < 15; i++) {
+ hdr_mtx_param.mtx_in[i] = ycbcr2rgb_ncl2020[i];
+ hdr_mtx_param.mtx_cgain[i] = rgb2ycbcr_709[i];
+ hdr_mtx_param.mtx_ogain[i] = rgb2ycbcr_ncl2020[i];
+ hdr_mtx_param.mtx_out[i] = rgb2ycbcr_709[i];
+ if (i < 9)
+ hdr_mtx_param.mtx_gamut[i] = ncl_2020_709[i];
+ if (i < 3) {
+ hdr_mtx_param.mtxi_pre_offset[i] =
+ yuv2rgbpre[i];
+ hdr_mtx_param.mtxi_pos_offset[i] =
+ yuv2rgbpos[i];
+ hdr_mtx_param.mtxo_pre_offset[i] =
+ rgb2yuvpre[i];
+ hdr_mtx_param.mtxo_pos_offset[i] =
+ rgb2yuvpos[i];
+ }
+ }
+ hdr_mtx_param.mtx_on = MTX_ON;
+
+ if (hdr_process_select & HDR_SDR)
+ hdr_mtx_param.p_sel = HDR_SDR;
+ else if (hdr_process_select & HLG_SDR)
+ hdr_mtx_param.p_sel = HLG_SDR;
+ } else if (hdr_process_select & SDR_HDR) {
+ hdr_mtx_param.mtx_only = HDR_ONLY;
+ hdr_mtx_param.mtx_gamut_mode = 1;
+ if ((get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_G12A) &&
+ (module_sel & (OSD1_HDR | OSD2_HDR))) {
+ for (i = 0; i < 15; i++) {
+ hdr_mtx_param.mtx_in[i] = bypass_coeff[i];
+ hdr_mtx_param.mtx_cgain[i] =
+ rgb2ycbcr_ncl2020[i];
+ hdr_mtx_param.mtx_ogain[i] = rgb2ycbcr_709[i];
+ hdr_mtx_param.mtx_out[i] = rgb2ycbcr_ncl2020[i];
+ if (i < 9)
+ hdr_mtx_param.mtx_gamut[i] =
+ ncl_709_2020[i];
+ if (i < 3) {
+ hdr_mtx_param.mtxi_pre_offset[i] =
+ bypass_pre[i];
+ hdr_mtx_param.mtxi_pos_offset[i] =
+ bypass_pos[i];
+ hdr_mtx_param.mtxo_pre_offset[i] =
+ rgb2yuvpre[i];
+ hdr_mtx_param.mtxo_pos_offset[i] =
+ rgb2yuvpos[i];
+ }
+ }
+ } else {
+ for (i = 0; i < 15; i++) {
+ hdr_mtx_param.mtx_in[i] = ycbcr2rgb_709[i];
+ hdr_mtx_param.mtx_cgain[i] =
+ rgb2ycbcr_ncl2020[i];
+ hdr_mtx_param.mtx_ogain[i] = rgb2ycbcr_709[i];
+ hdr_mtx_param.mtx_out[i] = rgb2ycbcr_ncl2020[i];
+ if (i < 9)
+ hdr_mtx_param.mtx_gamut[i] =
+ ncl_709_2020[i];
+ if (i < 3) {
+ hdr_mtx_param.mtxi_pre_offset[i] =
+ yuv2rgbpre[i];
+ hdr_mtx_param.mtxi_pos_offset[i] =
+ yuv2rgbpos[i];
+ hdr_mtx_param.mtxo_pre_offset[i] =
+ rgb2yuvpre[i];
+ hdr_mtx_param.mtxo_pos_offset[i] =
+ rgb2yuvpos[i];
+ }
+ }
+ }
+ hdr_mtx_param.mtx_on = MTX_ON;
+ hdr_mtx_param.p_sel = SDR_HDR;
+ } else if (hdr_process_select & HLG_HDR) {
+ hdr_mtx_param.mtx_only = HDR_ONLY;
+ hdr_mtx_param.mtx_gamut_mode = 1;
+ for (i = 0; i < 15; i++) {
+ hdr_mtx_param.mtx_in[i] = ycbcr2rgb_ncl2020[i];
+ hdr_mtx_param.mtx_cgain[i] = bypass_coeff[i];
+ hdr_mtx_param.mtx_ogain[i] = bypass_coeff[i];
+ hdr_mtx_param.mtx_out[i] = rgb2ycbcr_ncl2020[i];
+ if (i < 9)
+ hdr_mtx_param.mtx_gamut[i] = bypass_coeff[i];
+ }
+ hdr_mtx_param.mtx_on = MTX_ON;
+ hdr_mtx_param.p_sel = HLG_HDR;
+ } else if (hdr_process_select & SDR_HLG) {
+ hdr_mtx_param.mtx_only = HDR_ONLY;
+ hdr_mtx_param.mtx_gamut_mode = 1;
+ if ((get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_G12A) &&
+ (module_sel & OSD1_HDR)) {
+ for (i = 0; i < 15; i++) {
+ hdr_mtx_param.mtx_in[i] = bypass_coeff[i];
+ hdr_mtx_param.mtx_cgain[i] =
+ rgb2ycbcr_ncl2020[i];
+ hdr_mtx_param.mtx_ogain[i] = rgb2ycbcr_709[i];
+ hdr_mtx_param.mtx_out[i] = rgb2ycbcr_ncl2020[i];
+ if (i < 9)
+ hdr_mtx_param.mtx_gamut[i] =
+ ncl_709_2020[i];
+ if (i < 3) {
+ hdr_mtx_param.mtxi_pre_offset[i] =
+ bypass_pre[i];
+ hdr_mtx_param.mtxi_pos_offset[i] =
+ bypass_pos[i];
+ hdr_mtx_param.mtxo_pre_offset[i] =
+ rgb2yuvpre[i];
+ hdr_mtx_param.mtxo_pos_offset[i] =
+ rgb2yuvpos[i];
+ }
+ }
+ } else {
+ for (i = 0; i < 15; i++) {
+ hdr_mtx_param.mtx_in[i] = ycbcr2rgb_709[i];
+ hdr_mtx_param.mtx_cgain[i] =
+ rgb2ycbcr_ncl2020[i];
+ hdr_mtx_param.mtx_ogain[i] = rgb2ycbcr_709[i];
+ hdr_mtx_param.mtx_out[i] = rgb2ycbcr_ncl2020[i];
+ if (i < 9)
+ hdr_mtx_param.mtx_gamut[i] =
+ ncl_709_2020[i];
+ if (i < 3) {
+ hdr_mtx_param.mtxi_pre_offset[i] =
+ yuv2rgbpre[i];
+ hdr_mtx_param.mtxi_pos_offset[i] =
+ yuv2rgbpos[i];
+ hdr_mtx_param.mtxo_pre_offset[i] =
+ rgb2yuvpre[i];
+ hdr_mtx_param.mtxo_pos_offset[i] =
+ rgb2yuvpos[i];
+ }
+ }
+ }
+ hdr_mtx_param.mtx_on = MTX_ON;
+ hdr_mtx_param.p_sel = SDR_HLG;
+ } else if (hdr_process_select & HDR_OFF) {
+ hdr_mtx_param.mtx_gamut_mode = 0;
+ for (i = 0; i < 15; i++) {
+ hdr_mtx_param.mtx_in[i] = rgb2ycbcr_709[i];
+ hdr_mtx_param.mtx_cgain[i] = bypass_coeff[i];
+ hdr_mtx_param.mtx_ogain[i] = bypass_coeff[i];
+ hdr_mtx_param.mtx_out[i] = bypass_coeff[i];
+ if (i < 9)
+ hdr_mtx_param.mtx_gamut[i] =
+ bypass_coeff[i];
+ if (i < 3) {
+ hdr_mtx_param.mtxi_pre_offset[i] =
+ rgb2yuvpre[i];
+ hdr_mtx_param.mtxi_pos_offset[i] =
+ rgb2yuvpos[i];
+ hdr_mtx_param.mtxo_pre_offset[i] =
+ bypass_pre[i];
+ hdr_mtx_param.mtxo_pos_offset[i] =
+ bypass_pos[i];
+ }
+ }
+ hdr_mtx_param.mtx_on = MTX_OFF;
+ hdr_mtx_param.p_sel = HDR_BYPASS;
+ hdr_mtx_param.mtx_only = HDR_ONLY;
+ } else if (hdr_process_select & RGB_BYPASS) {
+ hdr_mtx_param.mtx_gamut_mode = 0;
+ if ((get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_G12A)) {
+ /*DV HDR_BYPASS need bypass coeff*/
+ for (i = 0; i < 15; i++) {
+ hdr_mtx_param.mtx_in[i] = bypass_coeff[i];
+ hdr_mtx_param.mtx_cgain[i] = bypass_coeff[i];
+ hdr_mtx_param.mtx_ogain[i] = bypass_coeff[i];
+ hdr_mtx_param.mtx_out[i] = bypass_coeff[i];
+ if (i < 9)
+ hdr_mtx_param.mtx_gamut[i] =
+ bypass_coeff[i];
+ if (i < 3) {
+ hdr_mtx_param.mtxi_pre_offset[i] =
+ bypass_pre[i];
+ hdr_mtx_param.mtxi_pos_offset[i] =
+ bypass_pos[i];
+ hdr_mtx_param.mtxo_pre_offset[i] =
+ bypass_pre[i];
+ hdr_mtx_param.mtxo_pos_offset[i] =
+ bypass_pos[i];
+ }
+ }
+ hdr_mtx_param.mtx_on = MTX_ON;
+ hdr_mtx_param.p_sel = HDR_BYPASS;
+ }
+ }
+
+ set_hdr_matrix(module_sel, HDR_IN_MTX, &hdr_mtx_param);
+
+ set_eotf_lut(module_sel, &hdr_lut_param);
+
+ set_hdr_matrix(module_sel, HDR_GAMUT_MTX, &hdr_mtx_param);
+
+ set_ootf_lut(module_sel, &hdr_lut_param);
+
+ set_oetf_lut(module_sel, &hdr_lut_param);
+
+ set_hdr_matrix(module_sel, HDR_OUT_MTX, &hdr_mtx_param);
+
+ set_c_gain(module_sel, &hdr_lut_param);
+
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_T3)
+ clip_func_after_ootf(hdr_mtx_param.mtx_gamut_mode, module_sel);
+}
diff --git a/drivers/amlogic/media/common/vpp/hdr2.h b/drivers/amlogic/media/common/vpp/hdr2.h
new file mode 100644
index 0000000..f433494
--- /dev/null
+++ b/drivers/amlogic/media/common/vpp/hdr2.h
@@ -0,0 +1,288 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __HDR2_H__
+#define __HDR2_H__
+
+enum hdr_module_sel {
+ VD1_HDR = 0x1,
+ VD2_HDR = 0x2,
+ VD3_HDR = 0x3,
+ OSD1_HDR = 0x4,
+ OSD2_HDR = 0x5,
+ VDIN0_HDR = 0x8,
+ VDIN1_HDR = 0x10,
+ DI_HDR = 0x20,
+ OSD3_HDR = 0x40,
+ HDR_MAX
+};
+
+enum hdr_matrix_sel {
+ HDR_IN_MTX = 0x1,
+ HDR_GAMUT_MTX = 0x2,
+ HDR_OUT_MTX = 0x4,
+ HDR_MTX_MAX
+};
+
+enum hdr_lut_sel {
+ HDR_EOTF_LUT = 0x1,
+ HDR_OOTF_LUT = 0x2,
+ HDR_OETF_LUT = 0x4,
+ HDR_CGAIN_LUT = 0x8,
+ HDR_LUT_MAX
+};
+
+enum hdr_process_sel {
+ HDR_BYPASS = 0x1,
+ HDR_SDR = 0x2,
+ SDR_HDR = 0x4,
+ HLG_BYPASS = 0x8,
+ HLG_SDR = 0x10,
+ HLG_HDR = 0x20,
+ SDR_HLG = 0X40,
+ HDRPLUS_SDR = 0x80,
+ HDR_OFF = 0x100,
+ RGB_BYPASS = 0x200,
+ HDR_p_MAX
+};
+
+#define MTX_ON 1
+#define MTX_OFF 0
+
+#define MTX_ONLY 1
+#define HDR_ONLY 0
+
+#define LUT_ON 1
+#define LUT_OFF 0
+
+#define HDR2_EOTF_LUT_SIZE 143
+#define HDR2_OOTF_LUT_SIZE 149
+#define HDR2_OETF_LUT_SIZE 149
+#define HDR2_CGAIN_LUT_SIZE 65
+
+struct hdr_proc_mtx_param_s {
+ int mtx_only;
+ int mtx_in[15];
+ int mtx_gamut[9];
+ int mtx_gamut_mode;
+ int mtx_cgain[15];
+ int mtx_ogain[15];
+ int mtx_out[15];
+ int mtxi_pre_offset[3];
+ int mtxi_pos_offset[3];
+ int mtxo_pre_offset[3];
+ int mtxo_pos_offset[3];
+ unsigned int mtx_on;
+ enum hdr_process_sel p_sel;
+};
+
+struct hdr_proc_lut_param_s {
+ int eotf_lut[143];
+ int oetf_lut[149];
+ int ogain_lut[149];
+ int cgain_lut[65];
+ unsigned int lut_on;
+ unsigned int bitdepth;
+ unsigned int cgain_en;
+};
+
+void hdr_func(enum hdr_module_sel module_sel,
+ enum hdr_process_sel hdr_process_select);
+
+#ifndef OSD2_HDR2_CTRL
+#define OSD2_HDR2_CTRL 0x5b00
+#endif
+#ifndef OSD2_HDR2_CLK_GATE
+#define OSD2_HDR2_CLK_GATE 0x5b01
+#endif
+#ifndef OSD2_HDR2_MATRIXI_COEF00_01
+#define OSD2_HDR2_MATRIXI_COEF00_01 0x5b02
+#endif
+#ifndef OSD2_HDR2_MATRIXI_COEF02_10
+#define OSD2_HDR2_MATRIXI_COEF02_10 0x5b03
+#endif
+#ifndef OSD2_HDR2_MATRIXI_COEF11_12
+#define OSD2_HDR2_MATRIXI_COEF11_12 0x5b04
+#endif
+#ifndef OSD2_HDR2_MATRIXI_COEF20_21
+#define OSD2_HDR2_MATRIXI_COEF20_21 0x5b05
+#endif
+#ifndef OSD2_HDR2_MATRIXI_COEF22
+#define OSD2_HDR2_MATRIXI_COEF22 0x5b06
+#endif
+#ifndef OSD2_HDR2_MATRIXI_COEF30_31
+#define OSD2_HDR2_MATRIXI_COEF30_31 0x5b07
+#endif
+#ifndef OSD2_HDR2_MATRIXI_COEF32_40
+#define OSD2_HDR2_MATRIXI_COEF32_40 0x5b08
+#endif
+#ifndef OSD2_HDR2_MATRIXI_COEF41_42
+#define OSD2_HDR2_MATRIXI_COEF41_42 0x5b09
+#endif
+#ifndef OSD2_HDR2_MATRIXI_OFFSET0_1
+#define OSD2_HDR2_MATRIXI_OFFSET0_1 0x5b0a
+#endif
+#ifndef OSD2_HDR2_MATRIXI_OFFSET2
+#define OSD2_HDR2_MATRIXI_OFFSET2 0x5b0b
+#endif
+#ifndef OSD2_HDR2_MATRIXI_PRE_OFFSET0_1
+#define OSD2_HDR2_MATRIXI_PRE_OFFSET0_1 0x5b0c
+#endif
+#ifndef OSD2_HDR2_MATRIXI_PRE_OFFSET2
+#define OSD2_HDR2_MATRIXI_PRE_OFFSET2 0x5b0d
+#endif
+#ifndef OSD2_HDR2_MATRIXO_COEF00_01
+#define OSD2_HDR2_MATRIXO_COEF00_01 0x5b0e
+#endif
+#ifndef OSD2_HDR2_MATRIXO_COEF02_10
+#define OSD2_HDR2_MATRIXO_COEF02_10 0x5b0f
+#endif
+#ifndef OSD2_HDR2_MATRIXO_COEF11_12
+#define OSD2_HDR2_MATRIXO_COEF11_12 0x5b10
+#endif
+#ifndef OSD2_HDR2_MATRIXO_COEF20_21
+#define OSD2_HDR2_MATRIXO_COEF20_21 0x5b11
+#endif
+#ifndef OSD2_HDR2_MATRIXO_COEF22
+#define OSD2_HDR2_MATRIXO_COEF22 0x5b12
+#endif
+#ifndef OSD2_HDR2_MATRIXO_COEF30_31
+#define OSD2_HDR2_MATRIXO_COEF30_31 0x5b13
+#endif
+#ifndef OSD2_HDR2_MATRIXO_COEF32_40
+#define OSD2_HDR2_MATRIXO_COEF32_40 0x5b14
+#endif
+#ifndef OSD2_HDR2_MATRIXO_COEF41_42
+#define OSD2_HDR2_MATRIXO_COEF41_42 0x5b15
+#endif
+#ifndef OSD2_HDR2_MATRIXO_OFFSET0_1
+#define OSD2_HDR2_MATRIXO_OFFSET0_1 0x5b16
+#endif
+#ifndef OSD2_HDR2_MATRIXO_OFFSET2
+#define OSD2_HDR2_MATRIXO_OFFSET2 0x5b17
+#endif
+#ifndef OSD2_HDR2_MATRIXO_PRE_OFFSET0_1
+#define OSD2_HDR2_MATRIXO_PRE_OFFSET0_1 0x5b18
+#endif
+#ifndef OSD2_HDR2_MATRIXO_PRE_OFFSET2
+#define OSD2_HDR2_MATRIXO_PRE_OFFSET2 0x5b19
+#endif
+#ifndef OSD2_HDR2_MATRIXI_CLIP
+#define OSD2_HDR2_MATRIXI_CLIP 0x5b1a
+#endif
+#ifndef OSD2_HDR2_MATRIXO_CLIP
+#define OSD2_HDR2_MATRIXO_CLIP 0x5b1b
+#endif
+#ifndef OSD2_HDR2_CGAIN_OFFT
+#define OSD2_HDR2_CGAIN_OFFT 0x5b1c
+#endif
+#ifndef OSD2_HDR2_HIST_RD
+#define OSD2_HDR2_HIST_RD 0x5b1d
+#endif
+#ifndef OSD2_EOTF_LUT_ADDR_PORT
+#define OSD2_EOTF_LUT_ADDR_PORT 0x5b1e
+#endif
+#ifndef OSD2_EOTF_LUT_DATA_PORT
+#define OSD2_EOTF_LUT_DATA_PORT 0x5b1f
+#endif
+#ifndef OSD2_OETF_LUT_ADDR_PORT
+#define OSD2_OETF_LUT_ADDR_PORT 0x5b20
+#endif
+#ifndef OSD2_OETF_LUT_DATA_PORT
+#define OSD2_OETF_LUT_DATA_PORT 0x5b21
+#endif
+#ifndef OSD2_CGAIN_LUT_ADDR_PORT
+#define OSD2_CGAIN_LUT_ADDR_PORT 0x5b22
+#endif
+#ifndef OSD2_CGAIN_LUT_DATA_PORT
+#define OSD2_CGAIN_LUT_DATA_PORT 0x5b23
+#endif
+#ifndef OSD2_HDR2_CGAIN_COEF0
+#define OSD2_HDR2_CGAIN_COEF0 0x5b24
+#endif
+#ifndef OSD2_HDR2_CGAIN_COEF1
+#define OSD2_HDR2_CGAIN_COEF1 0x5b25
+#endif
+#ifndef OSD2_OGAIN_LUT_ADDR_PORT
+#define OSD2_OGAIN_LUT_ADDR_PORT 0x5b26
+#endif
+#ifndef OSD2_OGAIN_LUT_DATA_PORT
+#define OSD2_OGAIN_LUT_DATA_PORT 0x5b27
+#endif
+#ifndef OSD2_HDR2_ADPS_CTRL
+#define OSD2_HDR2_ADPS_CTRL 0x5b28
+#endif
+#ifndef OSD2_HDR2_ADPS_ALPHA0
+#define OSD2_HDR2_ADPS_ALPHA0 0x5b29
+#endif
+#ifndef OSD2_HDR2_ADPS_ALPHA1
+#define OSD2_HDR2_ADPS_ALPHA1 0x5b2a
+#endif
+#ifndef OSD2_HDR2_ADPS_BETA0
+#define OSD2_HDR2_ADPS_BETA0 0x5b2b
+#endif
+#ifndef OSD2_HDR2_ADPS_BETA1
+#define OSD2_HDR2_ADPS_BETA1 0x5b2c
+#endif
+#ifndef OSD2_HDR2_ADPS_BETA2
+#define OSD2_HDR2_ADPS_BETA2 0x5b2d
+#endif
+#ifndef OSD2_HDR2_ADPS_COEF0
+#define OSD2_HDR2_ADPS_COEF0 0x5b2e
+#endif
+#ifndef OSD2_HDR2_ADPS_COEF1
+#define OSD2_HDR2_ADPS_COEF1 0x5b2f
+#endif
+#ifndef OSD2_HDR2_GMUT_CTRL
+#define OSD2_HDR2_GMUT_CTRL 0x5b30
+#endif
+#ifndef OSD2_HDR2_GMUT_COEF0
+#define OSD2_HDR2_GMUT_COEF0 0x5b31
+#endif
+#ifndef OSD2_HDR2_GMUT_COEF1
+#define OSD2_HDR2_GMUT_COEF1 0x5b32
+#endif
+#ifndef OSD2_HDR2_GMUT_COEF2
+#define OSD2_HDR2_GMUT_COEF2 0x5b33
+#endif
+#ifndef OSD2_HDR2_GMUT_COEF3
+#define OSD2_HDR2_GMUT_COEF3 0x5b34
+#endif
+#ifndef OSD2_HDR2_GMUT_COEF4
+#define OSD2_HDR2_GMUT_COEF4 0x5b35
+#endif
+#ifndef OSD2_HDR2_PIPE_CTRL1
+#define OSD2_HDR2_PIPE_CTRL1 0x5b36
+#endif
+#ifndef OSD2_HDR2_PIPE_CTRL2
+#define OSD2_HDR2_PIPE_CTRL2 0x5b37
+#endif
+#ifndef OSD2_HDR2_PIPE_CTRL3
+#define OSD2_HDR2_PIPE_CTRL3 0x5b38
+#endif
+#ifndef OSD2_HDR2_PROC_WIN1
+#define OSD2_HDR2_PROC_WIN1 0x5b39
+#endif
+
+#ifndef OSD2_HDR2_PROC_WIN2
+#define OSD2_HDR2_PROC_WIN2 0x5b3a
+#endif
+#ifndef OSD2_HDR2_MATRIXI_EN_CTRL
+#define OSD2_HDR2_MATRIXI_EN_CTRL 0x5b3b
+#endif
+#ifndef OSD2_HDR2_MATRIXO_EN_CTRL
+#define OSD2_HDR2_MATRIXO_EN_CTRL 0x5b3c
+#endif
+#ifndef OSD2_HDR2_HIST_CTRL
+#define OSD2_HDR2_HIST_CTRL 0x5b3d
+#endif
+#ifndef OSD2_HDR2_HIST_H_START_END
+#define OSD2_HDR2_HIST_H_START_END 0x5b3e
+#endif
+#ifndef OSD2_HDR2_HIST_V_START_END
+#define OSD2_HDR2_HIST_V_START_END 0x5b3f
+#endif
+
+#endif
diff --git a/drivers/amlogic/media/common/vpp/vpp.c b/drivers/amlogic/media/common/vpp/vpp.c
old mode 100755
new mode 100644
index 9522dff..640d8c7
--- a/drivers/amlogic/media/common/vpp/vpp.c
+++ b/drivers/amlogic/media/common/vpp/vpp.c
@@ -1,36 +1,19 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/common/vpp/vpp.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
-#include <asm/arch/cpu_id.h>
+#include <amlogic/cpu_id.h>
#include <config.h>
#include <common.h>
#include <amlogic/media/vpp/vpp.h>
+#include <amlogic/media/vout/hdmitx/hdmi_common.h>
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
#include "vpp_reg.h"
#include "vpp.h"
+#include "hdr2.h"
-#ifdef BL33_DEBUG_PRINT
#define VPP_PR(fmt, args...) printf("vpp: "fmt"", ## args)
-#else
-#define VPP_PR(fmt, args...)
-#endif
static unsigned char vpp_init_flag;
@@ -411,9 +394,9 @@
static int RGB709_to_YUV709l_coeff[MATRIX_5x3_COEF_SIZE] = {
0, 0, 0, /* pre offset */
- 0xbb, 0x275, 0x3f,
- 0x1f99, 0x1ea6, 0x1c2,
- 0x1c2, 0x1e67, 0x1fd7,
+ COEFF_NORM(0.181873), COEFF_NORM(0.611831), COEFF_NORM(0.061765),
+ COEFF_NORM(-0.100251), COEFF_NORM(-0.337249), COEFF_NORM(0.437500),
+ COEFF_NORM(0.437500), COEFF_NORM(-0.397384), COEFF_NORM(-0.040116),
0, 0, 0, /* 10'/11'/12' */
0, 0, 0, /* 20'/21'/22' */
64, 512, 512, /* offset */
@@ -483,6 +466,38 @@
#define FRAC(a) ((((a) >= 0) ? \
((a) & 0x3ff) : ((~(a) + 1) & 0x3ff)) * 10000 / 1024)
+#define INORM 50000
+#ifdef CONFIG_AML_HDMITX20
+static u32 bt2020_primaries[3][2] = {
+ {0.17 * INORM + 0.5, 0.797 * INORM + 0.5}, /* G */
+ {0.131 * INORM + 0.5, 0.046 * INORM + 0.5}, /* B */
+ {0.708 * INORM + 0.5, 0.292 * INORM + 0.5}, /* R */
+};
+
+static u32 bt2020_white_point[2] = {
+ 0.3127 * INORM + 0.5, 0.3290 * INORM + 0.5
+};
+#endif
+
+static int vpp_get_chip_type(void)
+{
+ unsigned int cpu_type;
+
+ cpu_type = get_cpu_id().family_id;
+ return cpu_type;
+}
+
+int is_osd_high_version(void)
+{
+ u32 family_id = get_cpu_id().family_id;
+
+ if (family_id == MESON_CPU_MAJOR_ID_G12A ||
+ family_id == MESON_CPU_MAJOR_ID_G12B ||
+ family_id >= MESON_CPU_MAJOR_ID_SM1)
+ return 1;
+ else
+ return 0;
+}
/* OSD csc defines end */
@@ -492,19 +507,13 @@
vpp_reg_setb(VPP_MATRIX_CTRL, 0xf, 11, 4);
}
-static void vpp_set_matrix_ycbcr2rgb(int vd1_or_vd2_or_post, int mode)
+static void vpp_top_post2_matrix_yuv2rgb(int vpp_top)
{
- //VPP_PR("%s: %d, %d\n", __func__, vd1_or_vd2_or_post, mode);
-
int *m = NULL;
+ /* POST2 matrix: YUV limit -> RGB default is 12bit*/
+ m = YUV709l_to_RGB709_coeff12;
- if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) ||
- (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B) ||
- (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_SM1) ||
- (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TL1)){
- /* POST2 matrix: YUV limit -> RGB default is 12bit*/
- m = YUV709l_to_RGB709_coeff12;
-
+ if (vpp_top == 0) {
/* VPP WRAP POST2 matrix */
vpp_reg_write(VPP_POST2_MATRIX_PRE_OFFSET0_1,
(((m[0] >> 2) & 0xfff) << 16) | ((m[1] >> 2) & 0xfff));
@@ -520,14 +529,65 @@
(((m[9] >> 2) & 0x1fff) << 16) | ((m[10] >> 2) & 0x1fff));
vpp_reg_write(VPP_POST2_MATRIX_COEF22,
(m[11] >> 2) & 0x1fff);
-
vpp_reg_write(VPP_POST2_MATRIX_OFFSET0_1,
(((m[18] >> 2) & 0xfff) << 16) | ((m[19] >> 2) & 0xfff));
vpp_reg_write(VPP_POST2_MATRIX_OFFSET2,
(m[20] >> 2) & 0xfff);
-
vpp_reg_setb(VPP_POST2_MATRIX_EN_CTRL, 1, 0, 1);
+ } else if (vpp_top == 1) {
+ vpp_reg_write(VPP1_MATRIX_PRE_OFFSET0_1,
+ (((m[0] >> 2) & 0xfff) << 16) | ((m[1] >> 2) & 0xfff));
+ vpp_reg_write(VPP1_MATRIX_PRE_OFFSET2,
+ (m[2] >> 2) & 0xfff);
+ vpp_reg_write(VPP1_MATRIX_COEF00_01,
+ (((m[3] >> 2) & 0x1fff) << 16) | ((m[4] >> 2) & 0x1fff));
+ vpp_reg_write(VPP1_MATRIX_COEF02_10,
+ (((m[5] >> 2) & 0x1fff) << 16) | ((m[6] >> 2) & 0x1fff));
+ vpp_reg_write(VPP1_MATRIX_COEF11_12,
+ (((m[7] >> 2) & 0x1fff) << 16) | ((m[8] >> 2) & 0x1fff));
+ vpp_reg_write(VPP1_MATRIX_COEF20_21,
+ (((m[9] >> 2) & 0x1fff) << 16) | ((m[10] >> 2) & 0x1fff));
+ vpp_reg_write(VPP1_MATRIX_COEF22,
+ (m[11] >> 2) & 0x1fff);
+ vpp_reg_write(VPP1_MATRIX_OFFSET0_1,
+ (((m[18] >> 2) & 0xfff) << 16) | ((m[19] >> 2) & 0xfff));
+ vpp_reg_write(VPP1_MATRIX_OFFSET2,
+ (m[20] >> 2) & 0xfff);
+
+ vpp_reg_setb(VPP1_MATRIX_EN_CTRL, 1, 0, 1);
+ } else if (vpp_top == 2) {
+ vpp_reg_write(VPP2_MATRIX_PRE_OFFSET0_1,
+ (((m[0] >> 2) & 0xfff) << 16) | ((m[1] >> 2) & 0xfff));
+ vpp_reg_write(VPP2_MATRIX_PRE_OFFSET2,
+ (m[2] >> 2) & 0xfff);
+ vpp_reg_write(VPP2_MATRIX_COEF00_01,
+ (((m[3] >> 2) & 0x1fff) << 16) | ((m[4] >> 2) & 0x1fff));
+ vpp_reg_write(VPP2_MATRIX_COEF02_10,
+ (((m[5] >> 2) & 0x1fff) << 16) | ((m[6] >> 2) & 0x1fff));
+ vpp_reg_write(VPP2_MATRIX_COEF11_12,
+ (((m[7] >> 2) & 0x1fff) << 16) | ((m[8] >> 2) & 0x1fff));
+ vpp_reg_write(VPP2_MATRIX_COEF20_21,
+ (((m[9] >> 2) & 0x1fff) << 16) | ((m[10] >> 2) & 0x1fff));
+ vpp_reg_write(VPP2_MATRIX_COEF22,
+ (m[11] >> 2) & 0x1fff);
+
+ vpp_reg_write(VPP2_MATRIX_OFFSET0_1,
+ (((m[18] >> 2) & 0xfff) << 16) | ((m[19] >> 2) & 0xfff));
+ vpp_reg_write(VPP2_MATRIX_OFFSET2,
+ (m[20] >> 2) & 0xfff);
+
+ vpp_reg_setb(VPP2_MATRIX_EN_CTRL, 1, 0, 1);
+ }
+
+}
+static void vpp_set_matrix_ycbcr2rgb(int vd1_or_vd2_or_post, int mode)
+{
+ //VPP_PR("%s: %d, %d\n", __func__, vd1_or_vd2_or_post, mode);
+
+ if (is_osd_high_version()) {
+ /* vpp top0 */
+ vpp_top_post2_matrix_yuv2rgb(0);
VPP_PR("g12a/b post2(bit12) matrix: YUV limit -> RGB ..............\n");
return;
}
@@ -618,6 +678,8 @@
int size = 0;
int i;
+ pr_info("set_vpp_matrix m_select = %d on = %d\n",m_select,on);
+
if (m_select == VPP_MATRIX_OSD) {
m = osd_matrix_coeff;
size = MATRIX_5x3_COEF_SIZE;
@@ -872,7 +934,7 @@
for (i = 0; i < 16; i++)
vpp_reg_write(data_port,
g_map[i * 2 + 1]
- | (b_map[i * 2 + 2] << 16));
+ | (g_map[i * 2 + 2] << 16));
for (i = 0; i < 16; i++)
vpp_reg_write(data_port,
b_map[i * 2]
@@ -917,10 +979,7 @@
{
int *m = NULL;
- if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) ||
- (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B) ||
- (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TL1) ||
- (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_SM1)) {
+ if (is_osd_high_version()) {
/* RGB -> 709 limit */
m = RGB709_to_YUV709l_coeff;
@@ -980,10 +1039,7 @@
{
int *m = NULL;
- if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) ||
- (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B) ||
- (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TL1) ||
- (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_SM1)) {
+ if (is_osd_high_version()) {
/* RGB -> 709 limit */
m = RGB709_to_YUV709l_coeff;
@@ -1021,9 +1077,7 @@
{
int *m = NULL;
- if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) ||
- (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B) ||
- (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_SM1)) {
+ if (is_osd_high_version()) {
/* RGB -> 709 limit */
m = RGB709_to_YUV709l_coeff;
@@ -1054,49 +1108,132 @@
}
}
+ /*
+for T7, set osd4 matrix(10bit) RGB2YUV
+ */
+static void set_osd4_rgb2yuv(bool on)
+{
+ int *m = NULL;
+
+ if (is_osd_high_version()) {
+ /* RGB -> 709 limit */
+ m = RGB709_to_YUV709l_coeff;
+
+ /* VPP WRAP OSD3 matrix */
+ vpp_reg_write(VIU_OSD4_MATRIX_PRE_OFFSET0_1,
+ ((m[0] & 0xfff) << 16) | (m[1] & 0xfff));
+ vpp_reg_write(VIU_OSD4_MATRIX_PRE_OFFSET2,
+ m[2] & 0xfff);
+ vpp_reg_write(VIU_OSD4_MATRIX_COEF00_01,
+ ((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff));
+ vpp_reg_write(VIU_OSD4_MATRIX_COEF02_10,
+ ((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff));
+ vpp_reg_write(VIU_OSD4_MATRIX_COEF11_12,
+ ((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff));
+ vpp_reg_write(VIU_OSD4_MATRIX_COEF20_21,
+ ((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff));
+ vpp_reg_write(VIU_OSD4_MATRIX_COEF22,
+ m[11] & 0x1fff);
+
+ vpp_reg_write(VIU_OSD4_MATRIX_OFFSET0_1,
+ ((m[18] & 0xfff) << 16) | (m[19] & 0xfff));
+ vpp_reg_write(VIU_OSD4_MATRIX_OFFSET2,
+ m[20] & 0xfff);
+
+ vpp_reg_setb(VIU_OSD4_MATRIX_EN_CTRL, on, 0, 1);
+
+ VPP_PR("T7 osd4 matrix rgb2yuv..............\n");
+ }
+}
+
+#ifndef AML_T7_DISPLAY
+static void set_viu2_osd_matrix_rgb2yuv(bool on)
+{
+ int *m = RGB709_to_YUV709l_coeff;
+
+ /* RGB -> 709 limit */
+ if (is_osd_high_version()) {
+ /* VPP WRAP OSD3 matrix */
+ vpp_reg_write(VIU2_OSD1_MATRIX_PRE_OFFSET0_1,
+ ((m[0] & 0xfff) << 16) | (m[1] & 0xfff));
+ vpp_reg_write(VIU2_OSD1_MATRIX_PRE_OFFSET2,
+ m[2] & 0xfff);
+ vpp_reg_write(VIU2_OSD1_MATRIX_COEF00_01,
+ ((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff));
+ vpp_reg_write(VIU2_OSD1_MATRIX_COEF02_10,
+ ((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff));
+ vpp_reg_write(VIU2_OSD1_MATRIX_COEF11_12,
+ ((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff));
+ vpp_reg_write(VIU2_OSD1_MATRIX_COEF20_21,
+ ((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff));
+ vpp_reg_write(VIU2_OSD1_MATRIX_COEF22,
+ m[11] & 0x1fff);
+
+ vpp_reg_write(VIU2_OSD1_MATRIX_OFFSET0_1,
+ ((m[18] & 0xfff) << 16) | (m[19] & 0xfff));
+ vpp_reg_write(VIU2_OSD1_MATRIX_OFFSET2,
+ m[20] & 0xfff);
+
+ vpp_reg_setb(VIU2_OSD1_MATRIX_EN_CTRL, on, 0, 1);
+ }
+}
+#endif
+
+static void set_vpp_osd2_rgb2yuv(bool on)
+{
+ int *m = NULL;
+
+ /* RGB -> 709 limit */
+ m = RGB709_to_YUV709l_coeff;
+
+ /* VPP WRAP OSD3 matrix */
+ vpp_reg_write(VPP_OSD2_MATRIX_PRE_OFFSET0_1,
+ ((m[0] & 0xfff) << 16) | (m[1] & 0xfff));
+ vpp_reg_write(VPP_OSD2_MATRIX_PRE_OFFSET2,
+ m[2] & 0xfff);
+ vpp_reg_write(VPP_OSD2_MATRIX_COEF00_01,
+ ((m[3] & 0x1fff) << 16) | (m[4] & 0x1fff));
+ vpp_reg_write(VPP_OSD2_MATRIX_COEF02_10,
+ ((m[5] & 0x1fff) << 16) | (m[6] & 0x1fff));
+ vpp_reg_write(VPP_OSD2_MATRIX_COEF11_12,
+ ((m[7] & 0x1fff) << 16) | (m[8] & 0x1fff));
+ vpp_reg_write(VPP_OSD2_MATRIX_COEF20_21,
+ ((m[9] & 0x1fff) << 16) | (m[10] & 0x1fff));
+ vpp_reg_write(VPP_OSD2_MATRIX_COEF22,
+ m[11] & 0x1fff);
+ vpp_reg_write(VPP_OSD2_MATRIX_OFFSET0_1,
+ ((m[18] & 0xfff) << 16) | (m[19] & 0xfff));
+ vpp_reg_write(VPP_OSD2_MATRIX_OFFSET2,
+ m[20] & 0xfff);
+ vpp_reg_setb(VPP_OSD2_MATRIX_EN_CTRL, on, 0, 1);
+ VPP_PR("vpp osd2 matrix rgb2yuv..............\n");
+}
+
/*
for txlx, set vpp default data path to u10
*/
static void set_vpp_bitdepth(void)
{
- if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) ||
- (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B) ||
- (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TL1) ||
- (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_SM1)) {
+ u32 chip_id = get_cpu_id().family_id;
+
+ if (is_osd_high_version()) {
/*after this step vd1 output data is U12,*/
- vpp_reg_write(DOLBY_PATH_CTRL, 0xf);
- }
-}
+ if (chip_id == MESON_CPU_MAJOR_ID_T7) {
+ /* osd dolby bypass en */
+ vpp_reg_setb(MALI_AFBCD_TOP_CTRL, 1, 14, 1);
+ vpp_reg_setb(MALI_AFBCD_TOP_CTRL, 1, 19, 1);
+ /* osd_din_ext 12bit */
+ vpp_reg_setb(MALI_AFBCD_TOP_CTRL, 0, 15, 1);
+ vpp_reg_setb(MALI_AFBCD_TOP_CTRL, 0, 20, 1);
-static void vpp_set_post_matrix_rgb2ycbcr(int mode)
-{
- /* enable post matrix */
- vpp_reg_setb(VPP_MATRIX_CTRL, 1, 0, 1);
- vpp_reg_setb(VPP_MATRIX_CTRL, 0, 8, 3);
- vpp_reg_setb(VPP_MATRIX_CTRL, 0, 1, 2);
+ vpp_reg_setb(MALI_AFBCD1_TOP_CTRL, 1, 19, 1);
+ vpp_reg_setb(MALI_AFBCD1_TOP_CTRL, 0, 20, 1);
- if (mode == 0) {
- /* RGB -> 709 limit */
- vpp_reg_write(VPP_MATRIX_COEF00_01, 0x00bb0275);
- vpp_reg_write(VPP_MATRIX_COEF02_10, 0x003f1f99);
- vpp_reg_write(VPP_MATRIX_COEF11_12, 0x1ea601c2);
- vpp_reg_write(VPP_MATRIX_COEF20_21, 0x01c21e67);
- vpp_reg_write(VPP_MATRIX_COEF22, 0x00001fd7);
- vpp_reg_write(VPP_MATRIX_OFFSET0_1, 0x00400200);
- vpp_reg_write(VPP_MATRIX_OFFSET2, 0x00000200);
- vpp_reg_write(VPP_MATRIX_PRE_OFFSET0_1, 0x0);
- vpp_reg_write(VPP_MATRIX_PRE_OFFSET2, 0x0);
- } else {
- /* RGB -> 709 full */
- vpp_reg_write(VPP_MATRIX_COEF00_01, 0xda02dc);
- vpp_reg_write(VPP_MATRIX_COEF02_10, 0x4a1f8a);
- vpp_reg_write(VPP_MATRIX_COEF11_12, 0x1e760200);
- vpp_reg_write(VPP_MATRIX_COEF20_21, 0x2001e2f);
- vpp_reg_write(VPP_MATRIX_COEF22, 0x1fd1);
- vpp_reg_write(VPP_MATRIX_OFFSET0_1, 0x200);
- vpp_reg_write(VPP_MATRIX_OFFSET2, 0x200);
- vpp_reg_write(VPP_MATRIX_PRE_OFFSET0_1, 0x0);
- vpp_reg_write(VPP_MATRIX_PRE_OFFSET2, 0x0);
+ vpp_reg_setb(MALI_AFBCD2_TOP_CTRL, 1, 19, 1);
+ vpp_reg_setb(MALI_AFBCD2_TOP_CTRL, 0, 20, 1);
+ } else {
+ vpp_reg_write(DOLBY_PATH_CTRL, 0xf);
+ }
}
}
@@ -1263,70 +1400,134 @@
VPP_PR("%s: successful\n", __func__);
}
-void vpp_enable_lcd_gamma_table(void)
+void vpp_enable_lcd_gamma_table(int index)
{
- vpp_reg_setb(L_GAMMA_CNTL_PORT, 1, GAMMA_EN, 1);
+ unsigned int reg;
+
+ if (get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_T7) {
+ switch (index) {
+ case 1:
+ reg = LCD_GAMMA_CNTL_PORT0 + (0x100 << 2);
+ break;
+ case 2:
+ reg = LCD_GAMMA_CNTL_PORT0 + (0x200 << 2);
+ break;
+ case 0:
+ default:
+ reg = LCD_GAMMA_CNTL_PORT0;
+ break;
+ }
+ } else {
+ reg = L_GAMMA_CNTL_PORT;
+ }
+
+ vpp_reg_setb(reg, 1, GAMMA_EN, 1);
}
-void vpp_disable_lcd_gamma_table(void)
+void vpp_disable_lcd_gamma_table(int index)
{
- vpp_reg_setb(L_GAMMA_CNTL_PORT, 0, GAMMA_EN, 1);
+ unsigned int reg;
+
+ if (get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_T7) {
+ switch (index) {
+ case 1:
+ reg = LCD_GAMMA_CNTL_PORT0 + (0x100 << 2);
+ break;
+ case 2:
+ reg = LCD_GAMMA_CNTL_PORT0 + (0x200 << 2);
+ break;
+ case 0:
+ default:
+ reg = LCD_GAMMA_CNTL_PORT0;
+ break;
+ }
+ } else {
+ reg = L_GAMMA_CNTL_PORT;
+ }
+ vpp_reg_setb(reg, 0, GAMMA_EN, 1);
}
#define GAMMA_RETRY 1000
-static void vpp_set_lcd_gamma_table(u16 *data, u32 rgb_mask)
+static void vpp_set_lcd_gamma_table(int index, u16 *data, u32 rgb_mask)
{
+ unsigned int reg_encl_en, reg_cntl_port, reg_data_port, reg_addr_port;
int i;
int cnt = 0;
- if (!(vpp_reg_read(ENCL_VIDEO_EN) & 0x1))
+ if (get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_T7) {
+ switch (index) {
+ case 1:
+ reg_encl_en = ENCL_VIDEO_EN + (0x600 << 2);
+ reg_cntl_port = LCD_GAMMA_CNTL_PORT0 + (0x100 << 2);
+ reg_data_port = LCD_GAMMA_DATA_PORT0 + (0x100 << 2);
+ reg_addr_port = LCD_GAMMA_ADDR_PORT0 + (0x100 << 2);
+ break;
+ case 2:
+ reg_encl_en = ENCL_VIDEO_EN + (0x800 << 2);
+ reg_cntl_port = LCD_GAMMA_CNTL_PORT0 + (0x200 << 2);
+ reg_data_port = LCD_GAMMA_DATA_PORT0 + (0x200 << 2);
+ reg_addr_port = LCD_GAMMA_ADDR_PORT0 + (0x200 << 2);
+ break;
+ case 0:
+ default:
+ reg_encl_en = ENCL_VIDEO_EN;
+ reg_cntl_port = LCD_GAMMA_CNTL_PORT0;
+ reg_data_port = LCD_GAMMA_DATA_PORT0;
+ reg_addr_port = LCD_GAMMA_ADDR_PORT0;
+ break;
+ }
+ } else {
+ reg_encl_en = ENCL_VIDEO_EN;
+ reg_cntl_port = L_GAMMA_CNTL_PORT;
+ reg_data_port = L_GAMMA_DATA_PORT;
+ reg_addr_port = L_GAMMA_ADDR_PORT;
+ }
+
+ if (!(vpp_reg_read(reg_encl_en) & 0x1))
return;
- while (!(vpp_reg_read(L_GAMMA_CNTL_PORT) & (0x1 << ADR_RDY))) {
+ vpp_reg_setb(reg_cntl_port, 0, GAMMA_EN, 1);
+
+ while (!(vpp_reg_read(reg_cntl_port) & (0x1 << ADR_RDY))) {
udelay(10);
if (cnt++ > GAMMA_RETRY)
break;
}
cnt = 0;
- vpp_reg_write(L_GAMMA_ADDR_PORT, (0x1 << H_AUTO_INC) |
+ vpp_reg_write(reg_addr_port, (0x1 << H_AUTO_INC) |
(0x1 << rgb_mask) |
(0x0 << HADR));
for (i = 0; i < 256; i++) {
- while (!(vpp_reg_read(L_GAMMA_CNTL_PORT) & (0x1 << WR_RDY))) {
+ while (!(vpp_reg_read(reg_cntl_port) & (0x1 << WR_RDY))) {
udelay(10);
if (cnt++ > GAMMA_RETRY)
break;
}
cnt = 0;
- vpp_reg_write(L_GAMMA_DATA_PORT, data[i]);
+ vpp_reg_write(reg_data_port, data[i]);
}
- while (!(vpp_reg_read(L_GAMMA_CNTL_PORT) & (0x1 << ADR_RDY))) {
+ while (!(vpp_reg_read(reg_cntl_port) & (0x1 << ADR_RDY))) {
udelay(10);
if (cnt++ > GAMMA_RETRY)
break;
}
- vpp_reg_write(L_GAMMA_ADDR_PORT, (0x1 << H_AUTO_INC) |
+ vpp_reg_write(reg_addr_port, (0x1 << H_AUTO_INC) |
(0x1 << rgb_mask) |
(0x23 << HADR));
}
-void vpp_init_lcd_gamma_table(void)
+void vpp_init_lcd_gamma_table(int index)
{
VPP_PR("%s\n", __func__);
- vpp_set_lcd_gamma_table(gamma_table_r, H_SEL_R);
- vpp_set_lcd_gamma_table(gamma_table_g, H_SEL_G);
- vpp_set_lcd_gamma_table(gamma_table_b, H_SEL_B);
-}
+ vpp_disable_lcd_gamma_table(index);
-void vpp_set_rgb_gamma_table(unsigned short *r, unsigned short *g, unsigned short *b)
-{
- vpp_set_lcd_gamma_table(r, H_SEL_R);
- vpp_set_lcd_gamma_table(g, H_SEL_G);
- vpp_set_lcd_gamma_table(b, H_SEL_B);
+ vpp_set_lcd_gamma_table(index, gamma_table_r, H_SEL_R);
+ vpp_set_lcd_gamma_table(index, gamma_table_g, H_SEL_G);
+ vpp_set_lcd_gamma_table(index, gamma_table_b, H_SEL_B);
- VPP_PR("%s: successful\n", __func__);
+ vpp_enable_lcd_gamma_table(index);
}
void vpp_matrix_update(int type)
@@ -1348,6 +1549,37 @@
}
}
+void vpp_viu2_matrix_update(int type)
+{
+ if (vpp_init_flag == 0)
+ return;
+
+ if (get_cpu_id().family_id < MESON_CPU_MAJOR_ID_G12A)
+ return;
+
+ VPP_PR("%s: %d\n", __func__, type);
+
+ switch (type) {
+ case VPP_CM_RGB:
+ /* default RGB */
+ #ifndef AML_T7_DISPLAY
+ set_viu2_osd_matrix_rgb2yuv(0);
+ #else
+ /* vpp_top1: yuv2rgb */
+ vpp_top_post2_matrix_yuv2rgb(1);
+ #endif
+ break;
+ case VPP_CM_YUV:
+ /* RGB to 709 limit */
+ #ifndef AML_T7_DISPLAY
+ set_viu2_osd_matrix_rgb2yuv(1);
+ #endif
+ break;
+ default:
+ break;
+ }
+}
+
static void vpp_ofifo_init(void)
{
unsigned int data32;
@@ -1360,10 +1592,93 @@
vpp_reg_write(VPP_HOLD_LINES, data32);
}
+#ifdef CONFIG_AML_HDMITX20
+static void amvecm_cp_hdr_info(struct master_display_info_s *hdr_data)
+{
+ int i, j;
+
+ hdr_data->features =
+ (0 << 30) /*sdr output 709*/
+ | (1 << 29) /*video available*/
+ | (5 << 26) /* unspecified */
+ | (0 << 25) /* limit */
+ | (1 << 24) /* color available */
+ | (9 << 16) /* bt2020 */
+ | (16 << 8) /* bt2020-10 */
+ | (10 << 0); /* bt2020c */
+
+ for (i = 0; i < 3; i++)
+ for (j = 0; j < 2; j++)
+ hdr_data->primaries[i][j] =
+ bt2020_primaries[i][j];
+ hdr_data->white_point[0] = bt2020_white_point[0];
+ hdr_data->white_point[1] = bt2020_white_point[1];
+ /* default luminance */
+ hdr_data->luminance[0] = 1000 * 10000;
+ hdr_data->luminance[1] = 50;
+
+ /* content_light_level */
+ hdr_data->max_content = 0;
+ hdr_data->max_frame_average = 0;
+ hdr_data->luminance[0] = hdr_data->luminance[0] / 10000;
+ hdr_data->present_flag = 1;
+}
+#endif
+
+void hdr_tx_pkt_cb(void)
+{
+ int hdr_policy = 0;
+#ifdef CONFIG_AML_HDMITX20
+ struct master_display_info_s hdr_data;
+ struct hdr_info *hdrinfo = NULL;
+#endif
+ const char *hdr_policy_env = env_get("hdr_policy");
+
+ if (!hdr_policy_env)
+ return;
+
+ hdr_policy = simple_strtoul(hdr_policy_env, NULL, 10);
+#ifdef CONFIG_AML_HDMITX20
+ hdrinfo = hdmitx_get_rx_hdr_info();
+
+ if ((hdrinfo && hdrinfo->hdr_sup_eotf_smpte_st_2084) &&
+ hdr_policy == 0) {
+ hdr_func(OSD1_HDR, SDR_HDR);
+ hdr_func(OSD2_HDR, SDR_HDR);
+ hdr_func(VD1_HDR, SDR_HDR);
+ amvecm_cp_hdr_info(&hdr_data);
+ hdmitx_set_drm_pkt(&hdr_data);
+ }
+#endif
+
+ VPP_PR("hdr_policy = %d\n", hdr_policy);
+#ifdef CONFIG_AML_HDMITX20
+ if (hdrinfo)
+ VPP_PR("Rx hdr_info.hdr_sup_eotf_smpte_st_2084 = %d\n",
+ hdrinfo->hdr_sup_eotf_smpte_st_2084);
+#endif
+}
+
+static bool is_vpp_supported(int chip_id)
+{
+ if ((chip_id == MESON_CPU_MAJOR_ID_A1) ||
+ (chip_id == MESON_CPU_MAJOR_ID_C1) ||
+ (chip_id == MESON_CPU_MAJOR_ID_C2))
+ return false;
+ else
+ return true;
+}
+
void vpp_init(void)
{
- VPP_PR("%s\n", __func__);
+ int chip_id;
+ chip_id = vpp_get_chip_type();
+ VPP_PR("%s, chip_id=%d\n", __func__, chip_id);
+ if (!is_vpp_supported(chip_id)) {
+ VPP_PR("%s, vpp not supported\n", __func__);
+ return;
+ }
vpp_init_flag = 1;
/* init vpu fifo control register */
@@ -1371,36 +1686,25 @@
vpp_set_matrix_default_init();
- if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) {
- /* osd1: rgb->yuv limit,osd2: rgb2yuv limit,osd3: rgb2yuv limit*/
- set_osd1_rgb2yuv(1);
- set_osd2_rgb2yuv(1);
- set_osd3_rgb2yuv(1);
+ if (is_osd_high_version()) {
+ /* >= g12a: osd out is rgb */
+ set_osd1_rgb2yuv(0);
+ set_osd2_rgb2yuv(0);
+ if (chip_id != MESON_CPU_MAJOR_ID_TL1 ||
+ chip_id != MESON_CPU_MAJOR_ID_S4)
+ set_osd3_rgb2yuv(0);
+ if (chip_id != MESON_CPU_MAJOR_ID_T7)
+ set_vpp_osd2_rgb2yuv(1);
+ else
+ set_osd4_rgb2yuv(0);
/* set vpp data path to u12 */
set_vpp_bitdepth();
- } else if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B) {
- /* osd1: rgb->yuv limit,osd2: rgb2yuv limit,osd3: rgb2yuv limit*/
- set_osd1_rgb2yuv(1);
- set_osd2_rgb2yuv(1);
- set_osd3_rgb2yuv(1);
-
- /* set vpp data path to u12 */
- set_vpp_bitdepth();
- } else if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TL1) {
- set_osd1_rgb2yuv(1);
- set_osd2_rgb2yuv(1);
-
- /* set vpp data path to u12 */
- set_vpp_bitdepth();
- } else if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_SM1) {
- /* osd1: rgb->yuv limit,osd2: rgb2yuv limit,osd3: rgb2yuv limit*/
- set_osd1_rgb2yuv(1);
- set_osd2_rgb2yuv(1);
- set_osd3_rgb2yuv(1);
-
- /* set vpp data path to u12 */
- set_vpp_bitdepth();
+ hdr_func(OSD1_HDR, HDR_BYPASS);
+ hdr_func(OSD2_HDR, HDR_BYPASS);
+ hdr_func(OSD3_HDR, HDR_BYPASS);
+ hdr_func(VD1_HDR, HDR_BYPASS);
+ hdr_func(VD2_HDR, HDR_BYPASS);
} else {
/* set dummy data default YUV black */
vpp_reg_write(VPP_DUMMY_DATA1, 0x108080);
diff --git a/drivers/amlogic/media/common/vpp/vpp.h b/drivers/amlogic/media/common/vpp/vpp.h
index 7952ee5..4b619b9 100644
--- a/drivers/amlogic/media/common/vpp/vpp.h
+++ b/drivers/amlogic/media/common/vpp/vpp.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/common/vpp/vpp.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __VPP_H__
#define __VPP_H__
@@ -62,4 +46,92 @@
u16 right_shift;
};
+/* vpp1 post2 matrix */
+#ifndef VPP1_MATRIX_COEF00_01
+#define VPP1_MATRIX_COEF00_01 0x5990
+#endif
+#ifndef VPP1_MATRIX_COEF02_10
+#define VPP1_MATRIX_COEF02_10 0x5991
+#endif
+#ifndef VPP1_MATRIX_COEF11_12
+#define VPP1_MATRIX_COEF11_12 0x5992
+#endif
+#ifndef VPP1_MATRIX_COEF20_21
+#define VPP1_MATRIX_COEF20_21 0x5993
+#endif
+#ifndef VPP1_MATRIX_COEF22
+#define VPP1_MATRIX_COEF22 0x5994
+#endif
+#ifndef VPP1_MATRIX_COEF13_14
+#define VPP1_MATRIX_COEF13_14 0x5995
+#endif
+#ifndef VPP1_MATRIX_COEF23_24
+#define VPP1_MATRIX_COEF23_24 0x5996
+#endif
+#ifndef VPP1_MATRIX_COEF15_25
+#define VPP1_MATRIX_COEF15_25 0x5997
+#endif
+#ifndef VPP1_MATRIX_CLIP
+#define VPP1_MATRIX_CLIP 0x5998
+#endif
+#ifndef VPP1_MATRIX_OFFSET0_1
+#define VPP1_MATRIX_OFFSET0_1 0x5999
+#endif
+#ifndef VPP1_MATRIX_OFFSET2
+#define VPP1_MATRIX_OFFSET2 0x599a
+#endif
+#ifndef VPP1_MATRIX_PRE_OFFSET0_1
+#define VPP1_MATRIX_PRE_OFFSET0_1 0x599b
+#endif
+#ifndef VPP1_MATRIX_PRE_OFFSET2
+#define VPP1_MATRIX_PRE_OFFSET2 0x599c
+#endif
+#ifndef VPP1_MATRIX_EN_CTRL
+#define VPP1_MATRIX_EN_CTRL 0x599d
+#endif
+
+/* vpp2 post2 matrix */
+#ifndef VPP2_MATRIX_COEF00_01
+#define VPP2_MATRIX_COEF00_01 0x59d0
+#endif
+#ifndef VPP2_MATRIX_COEF02_10
+#define VPP2_MATRIX_COEF02_10 0x59d1
+#endif
+#ifndef VPP2_MATRIX_COEF11_12
+#define VPP2_MATRIX_COEF11_12 0x59d2
+#endif
+#ifndef VPP2_MATRIX_COEF20_21
+#define VPP2_MATRIX_COEF20_21 0x59d3
+#endif
+#ifndef VPP2_MATRIX_COEF22
+#define VPP2_MATRIX_COEF22 0x59d4
+#endif
+#ifndef VPP2_MATRIX_COEF13_14
+#define VPP2_MATRIX_COEF13_14 0x59d5
+#endif
+#ifndef VPP2_MATRIX_COEF23_24
+#define VPP2_MATRIX_COEF23_24 0x59d6
+#endif
+#ifndef VPP2_MATRIX_COEF15_25
+#define VPP2_MATRIX_COEF15_25 0x59d7
+#endif
+#ifndef VPP2_MATRIX_CLIP
+#define VPP2_MATRIX_CLIP 0x59d8
+#endif
+#ifndef VPP2_MATRIX_OFFSET0_1
+#define VPP2_MATRIX_OFFSET0_1 0x59d9
+#endif
+#ifndef VPP2_MATRIX_OFFSET2
+#define VPP2_MATRIX_OFFSET2 0x59da
+#endif
+#ifndef VPP2_MATRIX_PRE_OFFSET0_1
+#define VPP2_MATRIX_PRE_OFFSET0_1 0x59db
+#endif
+#ifndef VPP2_MATRIX_PRE_OFFSET2
+#define VPP2_MATRIX_PRE_OFFSET2 0x59dc
+#endif
+#ifndef VPP2_MATRIX_EN_CTRL
+#define VPP2_MATRIX_EN_CTRL 0x59dd
+#endif
+
#endif
diff --git a/drivers/amlogic/media/common/vpp/vpp_reg.h b/drivers/amlogic/media/common/vpp/vpp_reg.h
index 0b86445..f34051d 100644
--- a/drivers/amlogic/media/common/vpp/vpp_reg.h
+++ b/drivers/amlogic/media/common/vpp/vpp_reg.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/vpp/aml_vpu_reg.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __VPP_REG_H__
#define __VPP_REG_H__
@@ -27,11 +11,16 @@
/* ********************************
* register define
* ********************************* */
+#ifndef REG_BASE_VCBUS
+#define REG_BASE_VCBUS (0xFF900000L)
+#endif
/* base & offset */
//#define REG_BASE_VCBUS (0xd0100000L)
#define REG_OFFSET_VCBUS(reg) ((reg) << 2)
/* memory mapping */
-#define REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg))
+#define REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg) + 0L)
+
+#define REG_VPP_ADDR(reg) (reg + 0L)
#ifdef VPP_EOTF_CTL
#define VIU_EOTF_CTL VPP_EOTF_CTL
@@ -209,10 +198,187 @@
#define VPP_WRAP_OSD3_MATRIX_EN_CTRL 0x3dbd
#endif
+#ifndef VIU2_OSD1_MATRIX_COEF00_01
+#define VIU2_OSD1_MATRIX_COEF00_01 0x1e70
+#endif
+#ifndef VIU2_OSD1_MATRIX_COEF02_10
+#define VIU2_OSD1_MATRIX_COEF02_10 0x1e71
+#endif
+#ifndef VIU2_OSD1_MATRIX_COEF11_12
+#define VIU2_OSD1_MATRIX_COEF11_12 0x1e72
+#endif
+#ifndef VIU2_OSD1_MATRIX_COEF20_21
+#define VIU2_OSD1_MATRIX_COEF20_21 0x1e73
+#endif
+#ifndef VIU2_OSD1_MATRIX_COEF22
+#define VIU2_OSD1_MATRIX_COEF22 0x1e74
+#endif
+#ifndef VIU2_OSD1_MATRIX_COEF13_14
+#define VIU2_OSD1_MATRIX_COEF13_14 0x1e75
+#endif
+#ifndef VIU2_OSD1_MATRIX_COEF23_24
+#define VIU2_OSD1_MATRIX_COEF23_24 0x1e76
+#endif
+#ifndef VIU2_OSD1_MATRIX_COEF15_25
+#define VIU2_OSD1_MATRIX_COEF15_25 0x1e77
+#endif
+#ifndef VIU2_OSD1_MATRIX_CLIP
+#define VIU2_OSD1_MATRIX_CLIP 0x1e78
+#endif
+#ifndef VIU2_OSD1_MATRIX_OFFSET0_1
+#define VIU2_OSD1_MATRIX_OFFSET0_1 0x1e79
+#endif
+#ifndef VIU2_OSD1_MATRIX_OFFSET2
+#define VIU2_OSD1_MATRIX_OFFSET2 0x1e7a
+#endif
+#ifndef VIU2_OSD1_MATRIX_PRE_OFFSET0_1
+#define VIU2_OSD1_MATRIX_PRE_OFFSET0_1 0x1e7b
+#endif
+#ifndef VIU2_OSD1_MATRIX_PRE_OFFSET2
+#define VIU2_OSD1_MATRIX_PRE_OFFSET2 0x1e7c
+#endif
+#ifndef VIU2_OSD1_MATRIX_EN_CTRL
+#define VIU2_OSD1_MATRIX_EN_CTRL 0x1e7d
+#endif
+
+#ifndef VPP_OSD2_MATRIX_COEF00_01
+#define VPP_OSD2_MATRIX_COEF00_01 0x3920
+#endif
+
+#ifndef VPP_OSD2_MATRIX_COEF02_10
+#define VPP_OSD2_MATRIX_COEF02_10 0x3921
+#endif
+
+#ifndef VPP_OSD2_MATRIX_COEF11_12
+#define VPP_OSD2_MATRIX_COEF11_12 0x3922
+#endif
+
+#ifndef VPP_OSD2_MATRIX_COEF20_21
+#define VPP_OSD2_MATRIX_COEF20_21 0x3923
+#endif
+
+#ifndef VPP_OSD2_MATRIX_COEF22
+#define VPP_OSD2_MATRIX_COEF22 0x3924
+#endif
+
+#ifndef VPP_OSD2_MATRIX_COEF13_14
+#define VPP_OSD2_MATRIX_COEF13_14 0x3925
+#endif
+
+#ifndef VPP_OSD2_MATRIX_COEF23_24
+#define VPP_OSD2_MATRIX_COEF23_24 0x3926
+#endif
+
+#ifndef VPP_OSD2_MATRIX_COEF15_25
+#define VPP_OSD2_MATRIX_COEF15_25 0x3927
+#endif
+
+#ifndef VPP_OSD2_MATRIX_CLIP
+#define VPP_OSD2_MATRIX_CLIP 0x3928
+#endif
+
+#ifndef VPP_OSD2_MATRIX_OFFSET0_1
+#define VPP_OSD2_MATRIX_OFFSET0_1 0x3929
+#endif
+
+#ifndef VPP_OSD2_MATRIX_OFFSET2
+#define VPP_OSD2_MATRIX_OFFSET2 0x392a
+#endif
+
+#ifndef VPP_OSD2_MATRIX_PRE_OFFSET0_1
+#define VPP_OSD2_MATRIX_PRE_OFFSET0_1 0x392b
+#endif
+
+#ifndef VPP_OSD2_MATRIX_PRE_OFFSET2
+#define VPP_OSD2_MATRIX_PRE_OFFSET2 0x392c
+#endif
+
+#ifndef VPP_OSD2_MATRIX_EN_CTRL
+#define VPP_OSD2_MATRIX_EN_CTRL 0x392d
+#endif
+
+#ifndef VIU_OSD4_MATRIX_COEF00_01
+#define VIU_OSD4_MATRIX_COEF00_01 0x3df0
+#endif
+
+#ifndef VIU_OSD4_MATRIX_COEF02_10
+#define VIU_OSD4_MATRIX_COEF02_10 0x3df1
+#endif
+
+#ifndef VIU_OSD4_MATRIX_COEF11_12
+#define VIU_OSD4_MATRIX_COEF11_12 0x3df2
+#endif
+
+#ifndef VIU_OSD4_MATRIX_COEF20_21
+#define VIU_OSD4_MATRIX_COEF20_21 0x3df3
+#endif
+
+#ifndef VIU_OSD4_MATRIX_COEF22
+#define VIU_OSD4_MATRIX_COEF22 0x3df4
+#endif
+
+#ifndef VIU_OSD4_MATRIX_COEF13_14
+#define VIU_OSD4_MATRIX_COEF13_14 0x3df5
+#endif
+
+#ifndef VIU_OSD4_MATRIX_COEF23_24
+#define VIU_OSD4_MATRIX_COEF23_24 0x3df6
+#endif
+
+#ifndef VIU_OSD4_MATRIX_COEF15_25
+#define VIU_OSD4_MATRIX_COEF15_25 0x3df7
+#endif
+
+#ifndef VIU_OSD4_MATRIX_CLIP
+#define VIU_OSD4_MATRIX_CLIP 0x3df8
+#endif
+
+#ifndef VIU_OSD4_MATRIX_OFFSET0_1
+#define VIU_OSD4_MATRIX_OFFSET0_1 0x3df9
+#endif
+
+#ifndef VIU_OSD4_MATRIX_OFFSET2
+#define VIU_OSD4_MATRIX_OFFSET2 0x3dfa
+#endif
+
+#ifndef VIU_OSD4_MATRIX_PRE_OFFSET0_1
+#define VIU_OSD4_MATRIX_PRE_OFFSET0_1 0x3dfb
+#endif
+
+#ifndef VIU_OSD4_MATRIX_PRE_OFFSET2
+#define VIU_OSD4_MATRIX_PRE_OFFSET2 0x3dfc
+#endif
+
+#ifndef VIU_OSD4_MATRIX_EN_CTRL
+#define VIU_OSD4_MATRIX_EN_CTRL 0x3dfd
+#endif
+
+#ifndef MALI_AFBCD_TOP_CTRL
+#define MALI_AFBCD_TOP_CTRL 0x1a0f
+#endif
+
+#ifndef MALI_AFBCD1_TOP_CTRL
+#define MALI_AFBCD1_TOP_CTRL 0x1a55
+#endif
+
+#ifndef MALI_AFBCD2_TOP_CTRL
+#define MALI_AFBCD2_TOP_CTRL 0x1a56
+#endif
+
#ifndef DOLBY_PATH_CTRL
#define DOLBY_PATH_CTRL 0x1a0c
#endif
+#ifndef LCD_GAMMA_CNTL_PORT0
+#define LCD_GAMMA_CNTL_PORT0 ((0x14b4 << 2) + 0xff000000)
+#endif
+#ifndef LCD_GAMMA_DATA_PORT0
+#define LCD_GAMMA_DATA_PORT0 ((0x14b5 << 2) + 0xff000000)
+#endif
+#ifndef LCD_GAMMA_ADDR_PORT0
+#define LCD_GAMMA_ADDR_PORT0 ((0x14b6 << 2) + 0xff000000)
+#endif
+
//#define GAMMA_CNTL_PORT 0x1400
#define GAMMA_VCOM_POL 7 /* RW */
#define GAMMA_RVS_OUT 6 /* RW */
@@ -239,12 +405,21 @@
static inline unsigned int vpp_reg_read(unsigned int _reg)
{
- return (*(volatile unsigned int *)REG_ADDR_VCBUS(_reg));
+ unsigned int val;
+
+ if (_reg > 0x10000)
+ val = *(volatile unsigned int *)REG_VPP_ADDR(_reg);
+ else
+ val = *(volatile unsigned int *)REG_ADDR_VCBUS(_reg);
+ return val;
};
static inline void vpp_reg_write(unsigned int _reg, unsigned int _value)
{
- *(volatile unsigned int *)REG_ADDR_VCBUS(_reg) = (_value);
+ if (_reg > 0x10000)
+ *(volatile unsigned int *)REG_VPP_ADDR(_reg) = (_value);
+ else
+ *(volatile unsigned int *)REG_ADDR_VCBUS(_reg) = (_value);
};
static inline void vpp_reg_setb(unsigned int _reg, unsigned int _value,
diff --git a/drivers/amlogic/media/common/vpu/Kconfig b/drivers/amlogic/media/common/vpu/Kconfig
index 2afbeed..8575338 100644
--- a/drivers/amlogic/media/common/vpu/Kconfig
+++ b/drivers/amlogic/media/common/vpu/Kconfig
@@ -1,4 +1,4 @@
config AML_VPU
bool "AML VPU drivers Support"
help
- Enable support for the Amlogic VPU drivers.
+ Enable support for the Amlogic VPU drivers.
\ No newline at end of file
diff --git a/drivers/amlogic/media/common/vpu/vpu.c b/drivers/amlogic/media/common/vpu/vpu.c
index 6526510..1aee429 100644
--- a/drivers/amlogic/media/common/vpu/vpu.c
+++ b/drivers/amlogic/media/common/vpu/vpu.c
@@ -1,26 +1,10 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/common/vpu/vpu.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <common.h>
-#include <asm/arch/cpu_id.h>
+#include <amlogic/cpu_id.h>
#include <fdtdec.h>
#include <amlogic/media/vpu/vpu.h>
#include "vpu_reg.h"
@@ -29,7 +13,10 @@
/* v20181009: init version */
/* v20190313: add sm1 support */
-#define VPU_VERION "v20190313"
+/* v20200521: add sc2 support */
+/* v20201118: add t7 support */
+/* v20210114: add s4 support */
+#define VPU_VERION "v20210114"
DECLARE_GLOBAL_DATA_PTR;
@@ -47,16 +34,25 @@
.clk_level_max = CLK_LEVEL_MAX_G12A,
.gp_pll_valid = 0,
+ .vpu_clk_reg = HHI_VPU_CLK_CNTL,
+ .vapb_clk_reg = HHI_VAPBCLK_CNTL,
+ .vid_clk_reg = HHI_VID_CLK_CNTL2,
+
+ .pwrctrl_id_table = NULL,
+
.fclk_div_table = fclk_div_table_g12a,
.vpu_clk_table = vpu_clk_table,
.mem_pd_table = vpu_mem_pd_g12a,
- .hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb,
- .hdmi_iso_table = vpu_hdmi_iso_gxb,
+ .power_table = vpu_pwr_gxb,
+ .iso_table = vpu_iso_gxb,
.reset_table = vpu_reset_g12a,
.module_init_table_cnt = 0,
.module_init_table = NULL,
+
+ .power_on = vpu_power_on,
+ .power_off = vpu_power_off,
};
static struct vpu_data_s vpu_data_g12b = {
@@ -66,16 +62,25 @@
.clk_level_max = CLK_LEVEL_MAX_G12A,
.gp_pll_valid = 0,
+ .vpu_clk_reg = HHI_VPU_CLK_CNTL,
+ .vapb_clk_reg = HHI_VAPBCLK_CNTL,
+ .vid_clk_reg = HHI_VID_CLK_CNTL2,
+
+ .pwrctrl_id_table = NULL,
+
.fclk_div_table = fclk_div_table_g12a,
.vpu_clk_table = vpu_clk_table,
.mem_pd_table = vpu_mem_pd_g12a,
- .hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb,
- .hdmi_iso_table = vpu_hdmi_iso_gxb,
+ .power_table = vpu_pwr_gxb,
+ .iso_table = vpu_iso_gxb,
.reset_table = vpu_reset_g12a,
.module_init_table_cnt = 0,
.module_init_table = NULL,
+
+ .power_on = vpu_power_on,
+ .power_off = vpu_power_off,
};
static struct vpu_data_s vpu_data_tl1 = {
@@ -85,37 +90,55 @@
.clk_level_max = CLK_LEVEL_MAX_G12A,
.gp_pll_valid = 0,
+ .vpu_clk_reg = HHI_VPU_CLK_CNTL,
+ .vapb_clk_reg = HHI_VAPBCLK_CNTL,
+ .vid_clk_reg = HHI_VID_CLK_CNTL2,
+
+ .pwrctrl_id_table = NULL,
+
.fclk_div_table = fclk_div_table_g12a,
.vpu_clk_table = vpu_clk_table,
.mem_pd_table = vpu_mem_pd_tl1,
- .hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb,
- .hdmi_iso_table = vpu_hdmi_iso_gxb,
+ .power_table = vpu_pwr_gxb,
+ .iso_table = vpu_iso_gxb,
.reset_table = vpu_reset_tl1,
.module_init_table_cnt = 0,
.module_init_table = NULL,
+
+ .power_on = vpu_power_on,
+ .power_off = vpu_power_off,
};
-static struct vpu_data_s vpu_data_sm1 = {
+/* static struct vpu_data_s vpu_data_sm1 = {
.chip_type = VPU_CHIP_SM1,
.chip_name = "sm1",
.clk_level_dft = CLK_LEVEL_DFT_G12A,
.clk_level_max = CLK_LEVEL_MAX_G12A,
.gp_pll_valid = 0,
+ .vpu_clk_reg = HHI_VPU_CLK_CNTL,
+ .vapb_clk_reg = HHI_VAPBCLK_CNTL,
+ .vid_clk_reg = HHI_VID_CLK_CNTL2,
+
+ .pwrctrl_id_table = NULL,
+
.fclk_div_table = fclk_div_table_g12a,
.vpu_clk_table = vpu_clk_table,
.mem_pd_table = vpu_mem_pd_tl1,
- .hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb,
- .hdmi_iso_table = vpu_hdmi_iso_sm1,
- .reset_table = vpu_reset_g12a,
+ .power_table = vpu_pwr_gxb,
+ .iso_table = vpu_iso_sm1,
+ .reset_table = vpu_reset_gx,
.module_init_table_cnt = 0,
.module_init_table = NULL,
-};
+ .power_on = vpu_power_on,
+ .power_off = vpu_power_off,
+};
+*/
static struct vpu_data_s vpu_data_tm2 = {
.chip_type = VPU_CHIP_TM2,
@@ -124,21 +147,169 @@
.clk_level_max = CLK_LEVEL_MAX_G12A,
.gp_pll_valid = 0,
+ .vpu_clk_reg = HHI_VPU_CLK_CNTL,
+ .vapb_clk_reg = HHI_VAPBCLK_CNTL,
+ .vid_clk_reg = HHI_VID_CLK_CNTL2,
+
+ .pwrctrl_id_table = NULL,
+
.fclk_div_table = fclk_div_table_g12a,
.vpu_clk_table = vpu_clk_table,
.mem_pd_table = vpu_mem_pd_tm2,
- .hdmi_iso_pre_table = vpu_hdmi_iso_pre_gxb,
- .hdmi_iso_table = vpu_hdmi_iso_sm1,
+ .power_table = vpu_pwr_gxb,
+ .iso_table = vpu_iso_sm1,
.reset_table = vpu_reset_tl1,
.module_init_table_cnt = 0,
.module_init_table = NULL,
+
+ .power_on = vpu_power_on,
+ .power_off = vpu_power_off,
+};
+
+static struct vpu_data_s vpu_data_sc2 = {
+ .chip_type = VPU_CHIP_SC2,
+ .chip_name = "sc2",
+ .clk_level_dft = CLK_LEVEL_DFT_G12A,
+ .clk_level_max = CLK_LEVEL_MAX_G12A,
+ .gp_pll_valid = 0,
+
+ .vpu_clk_reg = CLKCTRL_VPU_CLK_CTRL,
+ .vapb_clk_reg = CLKCTRL_VAPBCLK_CTRL,
+ .vid_clk_reg = CLKCTRL_VID_CLK_CTRL2,
+
+ .pwrctrl_id_table = vpu_pwrctrl_id_table,
+
+ .fclk_div_table = fclk_div_table_g12a,
+ .vpu_clk_table = vpu_clk_table,
+
+ .mem_pd_table = NULL,
+ .power_table = NULL,
+ .iso_table = NULL,
+ .reset_table = NULL,
+
+ .module_init_table_cnt = 0,
+ .module_init_table = NULL,
+
+ .power_on = vpu_power_on_new,
+ .power_off = vpu_power_off_new,
+};
+
+static struct vpu_data_s vpu_data_t5 = {
+ .chip_type = VPU_CHIP_T5,
+ .chip_name = "t5",
+ .clk_level_dft = CLK_LEVEL_DFT_G12A,
+ .clk_level_max = CLK_LEVEL_MAX_G12A,
+ .gp_pll_valid = 0,
+
+ .vpu_clk_reg = HHI_VPU_CLK_CNTL,
+ .vapb_clk_reg = HHI_VAPBCLK_CNTL,
+ .vid_clk_reg = HHI_VID_CLK_CNTL2,
+
+ .pwrctrl_id_table = vpu_pwrctrl_id_table,
+
+ .fclk_div_table = fclk_div_table_g12a,
+ .vpu_clk_table = vpu_clk_table,
+
+ .mem_pd_table = vpu_mem_pd_tm2,
+ .power_table = vpu_pwr_gxb,
+ .iso_table = vpu_iso_sm1,
+ .reset_table = vpu_reset_tl1,
+
+ .module_init_table_cnt = 0,
+ .module_init_table = NULL,
+
+ .power_on = vpu_power_on_new,
+ .power_off = vpu_power_off_new,
+};
+
+static struct vpu_data_s vpu_data_t5d = {
+ .chip_type = VPU_CHIP_T5D,
+ .chip_name = "t5d",
+ .clk_level_dft = CLK_LEVEL_DFT_T5D,
+ .clk_level_max = CLK_LEVEL_MAX_T5D,
+ .gp_pll_valid = 0,
+
+ .vpu_clk_reg = HHI_VPU_CLK_CNTL,
+ .vapb_clk_reg = HHI_VAPBCLK_CNTL,
+ .vid_clk_reg = HHI_VID_CLK_CNTL2,
+
+ .pwrctrl_id_table = vpu_pwrctrl_id_table,
+
+ .fclk_div_table = fclk_div_table_g12a,
+ .vpu_clk_table = vpu_clk_table,
+
+ .mem_pd_table = NULL,
+ .power_table = NULL,
+ .iso_table = NULL,
+ .reset_table = NULL,
+
+ .module_init_table_cnt = 0,
+ .module_init_table = NULL,
+
+ .power_on = vpu_power_on_new,
+ .power_off = vpu_power_off_new,
+};
+
+static struct vpu_data_s vpu_data_t7 = {
+ .chip_type = VPU_CHIP_T7,
+ .chip_name = "t7",
+ .clk_level_dft = CLK_LEVEL_DFT_G12A,
+ .clk_level_max = CLK_LEVEL_MAX_G12A,
+ .gp_pll_valid = 0,
+
+ .vpu_clk_reg = CLKCTRL_VPU_CLK_CTRL,
+ .vapb_clk_reg = CLKCTRL_VAPBCLK_CTRL,
+ .vid_clk_reg = CLKCTRL_VID_CLK0_CTRL2,
+
+ .pwrctrl_id_table = vpu_pwrctrl_id_table_t7,
+
+ .fclk_div_table = fclk_div_table_g12a,
+ .vpu_clk_table = vpu_clk_table,
+
+ .mem_pd_table = NULL,
+ .power_table = NULL,
+ .iso_table = NULL,
+ .reset_table = NULL,
+
+ .module_init_table_cnt = 0,
+ .module_init_table = NULL,
+
+ .power_on = vpu_power_on_new,
+ .power_off = vpu_power_off_new,
+};
+
+static struct vpu_data_s vpu_data_s4 = {
+ .chip_type = VPU_CHIP_S4,
+ .chip_name = "s4",
+ .clk_level_dft = CLK_LEVEL_DFT_G12A,
+ .clk_level_max = CLK_LEVEL_MAX_G12A,
+ .gp_pll_valid = 0,
+
+ .vpu_clk_reg = CLKCTRL_VPU_CLK_CTRL,
+ .vapb_clk_reg = CLKCTRL_VAPBCLK_CTRL,
+ .vid_clk_reg = CLKCTRL_VID_CLK_CTRL2,
+
+ .pwrctrl_id_table = vpu_pwrctrl_id_table,
+
+ .fclk_div_table = fclk_div_table_g12a,
+ .vpu_clk_table = vpu_clk_table,
+
+ .mem_pd_table = NULL,
+ .power_table = NULL,
+ .iso_table = NULL,
+ .reset_table = NULL,
+
+ .module_init_table_cnt = 0,
+ .module_init_table = NULL,
+
+ .power_on = vpu_power_on_new,
+ .power_off = vpu_power_off_new,
};
static void vpu_chip_detect(void)
{
-#if 1
unsigned int cpu_type;
cpu_type = get_cpu_id().family_id;
@@ -152,21 +323,39 @@
case MESON_CPU_MAJOR_ID_TL1:
vpu_conf.data = &vpu_data_tl1;
break;
- case MESON_CPU_MAJOR_ID_SM1:
- vpu_conf.data = &vpu_data_sm1;
- break;
+ //case MESON_CPU_MAJOR_ID_SM1:
+ // vpu_conf.data = &vpu_data_sm1;
+ // break;
case MESON_CPU_MAJOR_ID_TM2:
vpu_conf.data = &vpu_data_tm2;
break;
+ case MESON_CPU_MAJOR_ID_SC2:
+ vpu_conf.data = &vpu_data_sc2;
+ break;
+ case MESON_CPU_MAJOR_ID_T5:
+ vpu_conf.data = &vpu_data_t5;
+ break;
+ case MESON_CPU_MAJOR_ID_T5D:
+ vpu_conf.data = &vpu_data_t5d;
+ break;
+ case MESON_CPU_MAJOR_ID_T7:
+ vpu_conf.data = &vpu_data_t7;
+ break;
+ case MESON_CPU_MAJOR_ID_S4:
+ vpu_conf.data = &vpu_data_s4;
+ break;
default:
- vpu_conf.data = &vpu_data_g12a;
+ //vpu_conf.data = NULL;
+ vpu_conf.data = &vpu_data_s4;
break;
}
-#else
- vpu_conf.data = &vpu_data_g12a;
-#endif
strcpy(vpu_conf.drv_version, VPU_VERION);
+ if (!vpu_conf.data) {
+ VPUERR("invalid chip: 0x%x\n", cpu_type);
+ return;
+ }
+
#ifdef AML_VPU_CLK_LEVEL_DFT
vpu_conf.data->clk_level_dft = AML_VPU_CLK_LEVEL_DFT;
VPUPR("find AML_VPU_CLK_LEVEL_DFT: %d\n", AML_VPU_CLK_LEVEL_DFT);
@@ -174,7 +363,7 @@
#ifdef VPU_DEBUG_PRINT
VPUPR("driver version: %s\n", vpu_conf.drv_version);
- VPUPR("detect chip type: %d\n", vpu_conf.data->chip_type);
+ VPUPR("detect chip type: %d(%s)\n", vpu_conf.data->chip_type, vpu_conf.data->chip_name);
VPUPR("clk_level default: %d(%dHz), max: %d(%dHz)\n",
vpu_conf.data->clk_level_dft,
(vpu_conf.data->vpu_clk_table + vpu_conf.data->clk_level_dft)->freq,
@@ -187,7 +376,7 @@
{
int ret = -1;
- if (vpu_conf.data == NULL) {
+ if (!vpu_conf.data) {
VPUERR("invalid vpu\n");
return -1;
}
@@ -198,6 +387,11 @@
case VPU_CHIP_TL1:
case VPU_CHIP_SM1:
case VPU_CHIP_TM2:
+ case VPU_CHIP_SC2:
+ case VPU_CHIP_T5:
+ case VPU_CHIP_T5D:
+ case VPU_CHIP_T7:
+ case VPU_CHIP_S4:
ret = 0;
break;
default:
@@ -249,7 +443,7 @@
struct fclk_div_s *fclk_div;
unsigned int i, mux, mux_id;
- mux = vpu_hiu_getb(HHI_VPU_CLK_CNTL, 9, 3);
+ mux = vpu_hiu_getb(vpu_conf.data->vpu_clk_reg, 9, 3);
mux_id = mux;
for (i = 0; i < FCLK_DIV_MAX; i++) {
fclk_div = vpu_conf.data->fclk_div_table + i;
@@ -305,7 +499,7 @@
break;
}
- div = vpu_hiu_getb(HHI_VPU_CLK_CNTL, 0, 7) + 1;
+ div = vpu_hiu_getb(vpu_conf.data->vpu_clk_reg, 0, 7) + 1;
clk_freq = ((clk_source * 100 / div) + 99) / 100;
return (unsigned int)clk_freq;
@@ -330,7 +524,7 @@
{
struct vpu_clk_s *clk_table;
unsigned int vpu_clk;
- unsigned int mux, div;
+ unsigned int mux, div, clk_reg, vapb_reg;
int ret = 0;
/* vpu clk */
@@ -349,24 +543,26 @@
vpu_clk = clk_table->freq;
mux = get_vpu_clk_mux(clk_table->mux);
div = clk_table->div;
+ clk_reg = vpu_conf.data->vpu_clk_reg;
+ vapb_reg = vpu_conf.data->vapb_clk_reg;
- vpu_hiu_write(HHI_VPU_CLK_CNTL, ((mux << 9) | (div << 0)));
- vpu_hiu_setb(HHI_VPU_CLK_CNTL, 1, 8, 1);
+ vpu_hiu_write(clk_reg, ((mux << 9) | (div << 0)));
+ vpu_hiu_setb(clk_reg, 1, 8, 1);
/* vapb clk */
if (vpu_clk >= 250000000) {
- vpu_hiu_write(HHI_VAPBCLK_CNTL, (1 << 30) | /* turn on ge2d clock */
+ vpu_hiu_write(vapb_reg, (1 << 30) | /* turn on ge2d clock */
(0 << 9) | /* clk_sel //250Mhz */
(1 << 0)); /* clk_div */
} else {
- vpu_hiu_write(HHI_VAPBCLK_CNTL, (1 << 30) | /* turn on ge2d clock */
+ vpu_hiu_write(vapb_reg, (1 << 30) | /* turn on ge2d clock */
(clk_table->mux << 9) | /* clk_sel */
(div << 0)); /* clk_div */
}
- vpu_hiu_setb(HHI_VAPBCLK_CNTL, 1, 8, 1);
+ vpu_hiu_setb(vapb_reg, 1, 8, 1);
VPUPR("set clk: %uHz, readback: %uHz(0x%x)\n",
- vpu_clk, get_vpu_clk(), (vpu_hiu_read(HHI_VPU_CLK_CNTL)));
+ vpu_clk, get_vpu_clk(), (vpu_hiu_read(clk_reg)));
return ret;
}
@@ -452,9 +648,9 @@
return -1;
ret = get_vpu_config();
- vpu_power_on();
+ if (vpu_conf.data->power_on)
+ vpu_conf.data->power_on();
set_vpu_clk(vpu_conf.clk_level);
- //vpu_power_on();
/* vpu module init off, for power save, and special module init */
vpu_mem_pd_init_off();
@@ -469,36 +665,40 @@
return -1;
VPUPR("vpu remove\n");
- vpu_power_off();
+ if (vpu_conf.data->power_off)
+ vpu_conf.data->power_off();
+
return 0;
}
static void vpu_clk_switch(void)
{
struct vpu_clk_s *clk_table;
- unsigned int mux, div;
+ unsigned int mux, div, clk_reg;
+
+ clk_reg = vpu_conf.data->vpu_clk_reg;
/* step 1: switch to 2nd vpu clk patch */
clk_table = vpu_conf.data->vpu_clk_table + vpu_conf.data->clk_level_dft;
mux = get_vpu_clk_mux(clk_table->mux);
- vpu_hiu_setb(HHI_VPU_CLK_CNTL, mux, 25, 3);
+ vpu_hiu_setb(clk_reg, mux, 25, 3);
div = clk_table->div;
- vpu_hiu_setb(HHI_VPU_CLK_CNTL, div, 16, 7);
- vpu_hiu_setb(HHI_VPU_CLK_CNTL, 1, 24, 1);
- vpu_hiu_setb(HHI_VPU_CLK_CNTL, 1, 31, 1);
+ vpu_hiu_setb(clk_reg, div, 16, 7);
+ vpu_hiu_setb(clk_reg, 1, 24, 1);
+ vpu_hiu_setb(clk_reg, 1, 31, 1);
udelay(10);
/* step 2: adjust 1st vpu clk frequency */
clk_table = vpu_conf.data->vpu_clk_table + vpu_conf.clk_level;
- vpu_hiu_setb(HHI_VPU_CLK_CNTL, 0, 8, 1);
+ vpu_hiu_setb(clk_reg, 0, 8, 1);
mux = get_vpu_clk_mux(clk_table->mux);
- vpu_hiu_setb(HHI_VPU_CLK_CNTL, mux, 9, 3);
+ vpu_hiu_setb(clk_reg, mux, 9, 3);
div = clk_table->div;
- vpu_hiu_setb(HHI_VPU_CLK_CNTL, div, 0, 7);
- vpu_hiu_setb(HHI_VPU_CLK_CNTL, 1, 8, 1);
+ vpu_hiu_setb(clk_reg, div, 0, 7);
+ vpu_hiu_setb(clk_reg, 1, 8, 1);
udelay(20);
/* step 3: switch back to 1st vpu clk patch */
- vpu_hiu_setb(HHI_VPU_CLK_CNTL, 0, 31, 1);
- vpu_hiu_setb(HHI_VPU_CLK_CNTL, 0, 24, 1);
+ vpu_hiu_setb(clk_reg, 0, 31, 1);
+ vpu_hiu_setb(clk_reg, 0, 24, 1);
}
int vpu_clk_change(int level)
@@ -528,7 +728,7 @@
vpu_clk_switch();
VPUPR("set clk: %uHz, readback: %uHz(0x%x)\n",
- vpu_clk, get_vpu_clk(), vpu_hiu_read(HHI_VPU_CLK_CNTL));
+ vpu_clk, get_vpu_clk(), vpu_hiu_read(vpu_conf.data->vpu_clk_reg));
return 0;
}
@@ -539,7 +739,7 @@
VPUPR("clk_level: %u, clk: %uHz, reg: 0x%x\n",
vpu_conf.clk_level, get_vpu_clk(),
- vpu_hiu_read(HHI_VPU_CLK_CNTL));
+ vpu_hiu_read(vpu_conf.data->vpu_clk_reg));
}
void vpu_info_print(void)
@@ -564,10 +764,10 @@
#define VCBUS_REG_CNT_MAX 4
static unsigned int vcbus_reg[VCBUS_REG_CNT_MAX] = {
- 0x1b7f, /* VENC_VDAC_TST_VAL */
- 0x1c30, /* ENCP_DVI_HSO_BEGIN */
- 0x1d00, /* VPP_DUMMY_DATA */
- 0x2730, /* VPU_VPU_PWM_V0 */
+ VENC_VDAC_TST_VAL,
+ ENCP_DVI_HSO_BEGIN,
+ VPP_DUMMY_DATA,
+ VPU_VPU_PWM_V0,
};
void vcbus_test(void)
diff --git a/drivers/amlogic/media/common/vpu/vpu.h b/drivers/amlogic/media/common/vpu/vpu.h
index bd5120e..a2caeb8 100644
--- a/drivers/amlogic/media/common/vpu/vpu.h
+++ b/drivers/amlogic/media/common/vpu/vpu.h
@@ -1,47 +1,50 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/common/vpu/vpu.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __VPU_PARA_H__
#define __VPU_PARA_H__
-
-/* #define VPU_DEBUG_PRINT */
-#ifdef BL33_DEBUG_PRINT
-#define VPUPR(fmt, args...) printf("vpu: "fmt"", ## args)
-#else
-#define VPUPR(fmt, args...)
+#ifdef CONFIG_SECURE_POWER_CONTROL
+#include <asm/arch/pwr_ctrl.h>
#endif
+
+//#define VPU_DEBUG_PRINT
+#define VPUPR(fmt, args...) printf("vpu: "fmt"", ## args)
#define VPUERR(fmt, args...) printf("vpu: error: "fmt"", ## args)
enum vpu_chip_e {
VPU_CHIP_G12A = 0,
VPU_CHIP_G12B, /* 1 */
- VPU_CHIP_TL1, /* 10 */
- VPU_CHIP_SM1, /* 11 */
- VPU_CHIP_TM2, /* 12 */
+ VPU_CHIP_TL1, /* 2 */
+ VPU_CHIP_SM1, /* 3 */
+ VPU_CHIP_TM2, /* 4 */
+ VPU_CHIP_SC2, /* 5 */
+ VPU_CHIP_T5, /* 6 */
+ VPU_CHIP_T5D, /* 7 */
+ VPU_CHIP_T7, /* 8 */
+ VPU_CHIP_S4, /* 9 */
VPU_CHIP_MAX,
};
+#define VPU_PWR_ON 1
+#define VPU_PWR_OFF 0
+#define VPU_PWR_ID_END 0xffff
+#ifndef PM_VPU_HDMI
+#define PM_VPU_HDMI 0xffff
+#endif
+#ifndef PM_VI_CLK1
+#define PM_VI_CLK1 0xffff
+#endif
+#ifndef PM_VI_CLK2
+#define PM_VI_CLK2 0xffff
+#endif
+#define VPU_PWR_ID_MAX 10
+
#define VPU_REG_END 0xffff
#define VPU_MEM_PD_CNT_MAX 10
-#define VPU_HDMI_ISO_CNT_MAX 5
+#define VPU_ISO_CNT_MAX 5
+#define VPU_PWR_CNT_MAX 5
#define VPU_RESET_CNT_MAX 10
struct fclk_div_s {
@@ -75,16 +78,25 @@
unsigned char clk_level_max;
unsigned char gp_pll_valid;
+ unsigned int vpu_clk_reg;
+ unsigned int vapb_clk_reg;
+ unsigned int vid_clk_reg;
+
+ unsigned int *pwrctrl_id_table;
+
struct fclk_div_s *fclk_div_table;
struct vpu_clk_s *vpu_clk_table;
struct vpu_ctrl_s *mem_pd_table;
- struct vpu_ctrl_s *hdmi_iso_pre_table;
- struct vpu_ctrl_s *hdmi_iso_table;
+ struct vpu_ctrl_s *power_table;
+ struct vpu_ctrl_s *iso_table;
struct vpu_reset_s *reset_table;
unsigned int module_init_table_cnt;
struct vpu_ctrl_s *module_init_table;
+
+ void (*power_on)(void);
+ void (*power_off)(void);
};
struct vpu_conf_s {
@@ -109,5 +121,7 @@
extern void vpu_power_on(void);
extern void vpu_power_off(void);
+extern void vpu_power_on_new(void);
+extern void vpu_power_off_new(void);
#endif
diff --git a/drivers/amlogic/media/common/vpu/vpu_ctrl.h b/drivers/amlogic/media/common/vpu/vpu_ctrl.h
index dc6b930..b55b3e1 100644
--- a/drivers/amlogic/media/common/vpu/vpu_ctrl.h
+++ b/drivers/amlogic/media/common/vpu/vpu_ctrl.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/common/vpu/vpu_ctrl.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __VPU_CTRL_H__
#define __VPU_CTRL_H__
@@ -36,6 +20,10 @@
#define CLK_LEVEL_DFT_G12A 7
#define CLK_LEVEL_MAX_G12A 8
+/* T5D */
+/* freq max=400M, default=250M */
+#define CLK_LEVEL_DFT_T5D 3
+#define CLK_LEVEL_MAX_T5D 6
/* vpu clk setting */
enum vpu_mux_e {
@@ -118,48 +106,30 @@
};
/* ******************************************************* */
-/* VPU_HDMI ISO pre: before reset */
+/* VPU_HDMI POWER */
/* ******************************************************* */
-static struct vpu_ctrl_s vpu_hdmi_iso_pre_gxb[] = {
+static struct vpu_ctrl_s vpu_pwr_gxb[] = {
/* reg, val, bit, len */
- {AO_RTI_GEN_PWR_SLEEP0, 1, 8, 1},
+ {AO_RTI_GEN_PWR_SLEEP0, 0, 8, 1},
{VPU_REG_END, 0, 0, 0},
};
/* ******************************************************* */
/* VPU_HDMI ISO */
/* ******************************************************* */
-static struct vpu_ctrl_s vpu_hdmi_iso_gxb[] = {
+static struct vpu_ctrl_s vpu_iso_gxb[] = {
/* reg, val, bit, len */
- {AO_RTI_GEN_PWR_SLEEP0, 1, 9, 1},
+ {AO_RTI_GEN_PWR_SLEEP0, 0, 9, 1},
{VPU_REG_END, 0, 0, 0},
};
-static struct vpu_ctrl_s vpu_hdmi_iso_sm1[] = {
+static struct vpu_ctrl_s vpu_iso_sm1[] = {
/* reg, val, bit, len */
- {AO_RTI_GEN_PWR_ISO0, 1, 8, 1},
+ {AO_RTI_GEN_PWR_ISO0, 0, 8, 1},
{VPU_REG_END, 0, 0, 0},
};
/* ******************************************************* */
-/* VPU module init table */
-/* ******************************************************* */
-#if 0
-static struct vpu_ctrl_s vpu_module_init_txlx[] = {
- /* reg, val, bit, len */
- {DOLBY_TV_CLKGATE_CTRL, 1, 10, 2},
- {DOLBY_TV_CLKGATE_CTRL, 1, 2, 2},
- {DOLBY_TV_CLKGATE_CTRL, 1, 4, 2},
- {DOLBY_CORE2A_CLKGATE_CTRL, 1, 10, 2},
- {DOLBY_CORE2A_CLKGATE_CTRL, 1, 2, 2},
- {DOLBY_CORE2A_CLKGATE_CTRL, 1, 4, 2},
- {DOLBY_CORE3_CLKGATE_CTRL, 0, 1, 1},
- {DOLBY_CORE3_CLKGATE_CTRL, 1, 2, 2},
- {VPU_REG_END, 0, 0, 0},
-};
-#endif
-
-/* ******************************************************* */
/* VPU reset table */
/* ******************************************************* */
static struct vpu_reset_s vpu_reset_g12a[] = {
@@ -181,4 +151,37 @@
{RESET7_LEVEL, (1<<7)},
{VPU_REG_END, 0},
};
+
+/* ******************************************************* */
+/* VPU pwrctrl id table */
+/* ******************************************************* */
+static unsigned int vpu_pwrctrl_id_table[] = {
+ PM_VPU_HDMI,
+ VPU_PWR_ID_END
+};
+
+static unsigned int vpu_pwrctrl_id_table_t7[] = {
+ PM_VPU_HDMI,
+ PM_VI_CLK1,
+ PM_VI_CLK2,
+ VPU_PWR_ID_END
+};
+
+/* ******************************************************* */
+/* VPU module init table */
+/* ******************************************************* */
+#if 0
+static struct vpu_ctrl_s vpu_module_init_txlx[] = {
+ /* reg, val, bit, len */
+ {DOLBY_TV_CLKGATE_CTRL, 1, 10, 2},
+ {DOLBY_TV_CLKGATE_CTRL, 1, 2, 2},
+ {DOLBY_TV_CLKGATE_CTRL, 1, 4, 2},
+ {DOLBY_CORE2A_CLKGATE_CTRL, 1, 10, 2},
+ {DOLBY_CORE2A_CLKGATE_CTRL, 1, 2, 2},
+ {DOLBY_CORE2A_CLKGATE_CTRL, 1, 4, 2},
+ {DOLBY_CORE3_CLKGATE_CTRL, 0, 1, 1},
+ {DOLBY_CORE3_CLKGATE_CTRL, 1, 2, 2},
+ {VPU_REG_END, 0, 0, 0},
+};
+#endif
#endif
diff --git a/drivers/amlogic/media/common/vpu/vpu_dummy_reg.h b/drivers/amlogic/media/common/vpu/vpu_dummy_reg.h
index cd12404..1c16ca2 100644
--- a/drivers/amlogic/media/common/vpu/vpu_dummy_reg.h
+++ b/drivers/amlogic/media/common/vpu/vpu_dummy_reg.h
@@ -1,29 +1,21 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/common/vpu/vpu_reg.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __VPU_DUMMY_REG_H__
#define __VPU_DUMMY_REG_H__
#include <asm/arch/io.h>
#include <asm/arch/secure_apb.h>
+#ifndef REG_BASE_CBUS
+#define REG_BASE_CBUS (0xffd00000L)
+#endif
+
+#ifndef REG_BASE_VCBUS
+#define REG_BASE_VCBUS (0xff900000L)
+#endif
+
#ifndef HHI_GP_PLL_CNTL
#define HHI_GP_PLL_CNTL (0xc1100000 + (0x1010 << 2))
#endif
@@ -51,18 +43,138 @@
#define HHI_VPU_MEM_PD_REG4 (0xff63c000 + (0x4c << 2))
#endif
-#ifndef DOLBY_TV_CLKGATE_CTRL
-#define DOLBY_TV_CLKGATE_CTRL (0x33f1)
+#ifndef VENC_VDAC_TST_VAL
+#define VENC_VDAC_TST_VAL (0x1b7f)
#endif
-#ifndef DOLBY_CORE1_CLKGATE_CTRL
-#define DOLBY_CORE1_CLKGATE_CTRL (0x33f2)
+#ifndef ENCP_DVI_HSO_BEGIN
+#define ENCP_DVI_HSO_BEGIN (0x1c30)
#endif
-#ifndef DOLBY_CORE2A_CLKGATE_CTRL
-#define DOLBY_CORE2A_CLKGATE_CTRL (0x3432)
+#ifndef VPP_DUMMY_DATA
+#define VPP_DUMMY_DATA (0x1d00)
#endif
-#ifndef DOLBY_CORE3_CLKGATE_CTRL
-#define DOLBY_CORE3_CLKGATE_CTRL (0x36f0)
+#ifndef VPU_VPU_PWM_V0
+#define VPU_VPU_PWM_V0 (0x2730)
#endif
+#ifndef HHI_VPU_CLK_CNTL
+#define HHI_VPU_CLK_CNTL (0xc883c000 + (0x6f << 2))
+#endif
+
+#ifndef HHI_VAPBCLK_CNTL
+#define HHI_VAPBCLK_CNTL (0xc883c000 + (0x7d << 2))
+#endif
+
+#ifndef HHI_VID_CLK_CNTL2
+#define HHI_VID_CLK_CNTL2 (0xff63c000 + (0x065 << 2))
+#endif
+
+#ifndef AO_RTI_GEN_PWR_SLEEP0
+#define AO_RTI_GEN_PWR_SLEEP0 (0xff800000 + (0x03a << 2))
+#endif
+
+#ifndef AO_RTI_GEN_PWR_ISO0
+#define AO_RTI_GEN_PWR_ISO0 (0xff800000 + (0x03b << 2))
+#endif
+
+#ifndef HHI_MEM_PD_REG0
+#define HHI_MEM_PD_REG0 (0xff63c000 + (0x040 << 2))
+#endif
+
+#ifndef HHI_VPU_MEM_PD_REG0
+#define HHI_VPU_MEM_PD_REG0 (0xff63c000 + (0x041 << 2))
+#endif
+
+#ifndef HHI_VPU_MEM_PD_REG1
+#define HHI_VPU_MEM_PD_REG1 (0xff63c000 + (0x042 << 2))
+#endif
+
+#ifndef HHI_VPU_MEM_PD_REG2
+#define HHI_VPU_MEM_PD_REG2 (0xff63c000 + (0x04d << 2))
+#endif
+
+#ifndef HHI_VPU_MEM_PD_REG3
+#define HHI_VPU_MEM_PD_REG3 (0xff63c000 + (0x043 << 2))
+#endif
+
+#ifndef HHI_VPU_MEM_PD_REG4
+#define HHI_VPU_MEM_PD_REG4 (0xff63c000 + (0x044 << 2))
+#endif
+
+#ifndef HHI_MEM_PD_REG0
+#define HHI_MEM_PD_REG0 (0xff63c000 + (0x040 << 2))
+#endif
+
+#ifndef RESET0_LEVEL
+#define RESET0_LEVEL (0x0420)
+#endif
+#ifndef RESET1_LEVEL
+#define RESET1_LEVEL (0x0421)
+#endif
+#ifndef RESET2_LEVEL
+#define RESET2_LEVEL (0x0422)
+#endif
+#ifndef RESET4_LEVEL
+#define RESET4_LEVEL (0x0424)
+#endif
+#ifndef RESET7_LEVEL
+#define RESET7_LEVEL (0x0427)
+#endif
+
+/* new mmap */
+#ifndef CLKCTRL_VPU_CLK_CTRL
+#define CLKCTRL_VPU_CLK_CTRL ((0x003a << 2) + 0xfe000000)
+#endif
+
+#ifndef CLKCTRL_VAPBCLK_CTRL
+#define CLKCTRL_VAPBCLK_CTRL ((0x003f << 2) + 0xfe000000)
+#endif
+
+#ifndef CLKCTRL_VID_CLK_CTRL2
+#define CLKCTRL_VID_CLK_CTRL2 ((0x0031 << 2) + 0xfe000000)
+#endif
+
+#ifndef CLKCTRL_VID_CLK0_CTRL2
+#define CLKCTRL_VID_CLK0_CTRL2 ((0x0031 << 2) + 0xfe000000)
+#endif
+
+#ifndef PWRCTRL_PWR_ACK0
+#define PWRCTRL_PWR_ACK0 ((0x0000 << 2) + 0xfe00c000)
+#endif
+
+#ifndef PWRCTRL_PWR_OFF0
+#define PWRCTRL_PWR_OFF0 ((0x0004 << 2) + 0xfe00c000)
+#endif
+
+#ifndef PWRCTRL_ISO_EN0
+#define PWRCTRL_ISO_EN0 ((0x0008 << 2) + 0xfe00c000)
+#endif
+
+#ifndef PWRCTRL_FOCRST0
+#define PWRCTRL_FOCRST0 ((0x000c << 2) + 0xfe00c000)
+#endif
+
+#ifndef PWRCTRL_MEM_PD5
+#define PWRCTRL_MEM_PD5 ((0x0015 << 2) + 0xfe00c000)
+#endif
+
+#ifndef PWRCTRL_MEM_PD6
+#define PWRCTRL_MEM_PD6 ((0x0016 << 2) + 0xfe00c000)
+#endif
+
+#ifndef PWRCTRL_MEM_PD7
+#define PWRCTRL_MEM_PD7 ((0x0017 << 2) + 0xfe00c000)
+#endif
+
+#ifndef PWRCTRL_MEM_PD8
+#define PWRCTRL_MEM_PD8 ((0x0018 << 2) + 0xfe00c000)
+#endif
+
+#ifndef PWRCTRL_MEM_PD9
+#define PWRCTRL_MEM_PD9 ((0x0019 << 2) + 0xfe00c000)
+#endif
+
+#ifndef PWRCTRL_MEM_PD11
+#define PWRCTRL_MEM_PD11 ((0x001b << 2) + 0xfe00c000)
+#endif
#endif
diff --git a/drivers/amlogic/media/common/vpu/vpu_power_init.c b/drivers/amlogic/media/common/vpu/vpu_power_init.c
index ba58e20..5864037 100644
--- a/drivers/amlogic/media/common/vpu/vpu_power_init.c
+++ b/drivers/amlogic/media/common/vpu/vpu_power_init.c
@@ -1,23 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/common/vpu/vpu_power_init.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include <config.h>
#include <linux/kernel.h>
@@ -54,7 +38,7 @@
i++;
}
}
- vpu_hiu_setb(HHI_VID_CLK_CNTL2, 0, 0, 8);
+ vpu_hiu_setb(vpu_conf.data->vid_clk_reg, 0, 0, 8);
/* dmc_arb_config */
vpu_vcbus_write(VPU_RDARB_MODE_L1C1, 0x0); //0x210000
@@ -70,13 +54,13 @@
struct vpu_ctrl_s *ctrl_table;
struct vpu_reset_s *reset_table;
unsigned int _reg, _val, _start, _end, _len, mask;
- int i = 0, j;
+ int i, j;
- /* power on VPU_HDMI ISO */
- ctrl_table = vpu_conf.data->hdmi_iso_pre_table;
+ /* power on VPU_HDMI */
+ ctrl_table = vpu_conf.data->power_table;
if (ctrl_table) {
i = 0;
- while (i < VPU_HDMI_ISO_CNT_MAX) {
+ while (i < VPU_PWR_CNT_MAX) {
if (ctrl_table[i].reg == VPU_REG_END)
break;
_reg = ctrl_table[i].reg;
@@ -91,55 +75,59 @@
/* power up memories */
ctrl_table = vpu_conf.data->mem_pd_table;
- i = 0;
- while (i < VPU_MEM_PD_CNT_MAX) {
- if (ctrl_table[i].reg == VPU_REG_END)
- break;
- _reg = ctrl_table[i].reg;
- _start = ctrl_table[i].bit;
- _end = ctrl_table[i].len + ctrl_table[i].bit;
- for (j = _start; j < _end; j+=2) {
- vpu_hiu_setb(_reg, 0, j, 2);
+ if (ctrl_table) {
+ i = 0;
+ while (i < VPU_MEM_PD_CNT_MAX) {
+ if (ctrl_table[i].reg == VPU_REG_END)
+ break;
+ _reg = ctrl_table[i].reg;
+ _start = ctrl_table[i].bit;
+ _end = ctrl_table[i].len + ctrl_table[i].bit;
+ for (j = _start; j < _end; j+=2) {
+ vpu_hiu_setb(_reg, 0, j, 2);
+ udelay(5);
+ }
+ i++;
+ }
+ for (i = 8; i < 16; i++) {
+ vpu_hiu_setb(HHI_MEM_PD_REG0, 0, i, 1);
udelay(5);
}
- i++;
+ udelay(20);
}
- for (i = 8; i < 16; i++) {
- vpu_hiu_setb(HHI_MEM_PD_REG0, 0, i, 1);
- udelay(5);
- }
- udelay(20);
/* Reset VIU + VENC */
/* Reset VENCI + VENCP + VADC + VENCL */
/* Reset HDMI-APB + HDMI-SYS + HDMI-TX + HDMI-CEC */
reset_table = vpu_conf.data->reset_table;
- i = 0;
- while (i < VPU_RESET_CNT_MAX) {
- if (reset_table[i].reg == VPU_REG_END)
- break;
- _reg = reset_table[i].reg;
- mask = reset_table[i].mask;
- vpu_cbus_clr_mask(_reg, mask);
- i++;
- }
- udelay(5);
- /* release Reset */
- i = 0;
- while (i < VPU_RESET_CNT_MAX) {
- if (reset_table[i].reg == VPU_REG_END)
- break;
- _reg = reset_table[i].reg;
- mask = reset_table[i].mask;
- vpu_cbus_set_mask(_reg, mask);
- i++;
+ if (reset_table) {
+ i = 0;
+ while (i < VPU_RESET_CNT_MAX) {
+ if (reset_table[i].reg == VPU_REG_END)
+ break;
+ _reg = reset_table[i].reg;
+ mask = reset_table[i].mask;
+ vpu_cbus_clr_mask(_reg, mask);
+ i++;
+ }
+ udelay(5);
+ /* release Reset */
+ i = 0;
+ while (i < VPU_RESET_CNT_MAX) {
+ if (reset_table[i].reg == VPU_REG_END)
+ break;
+ _reg = reset_table[i].reg;
+ mask = reset_table[i].mask;
+ vpu_cbus_set_mask(_reg, mask);
+ i++;
+ }
}
/* Remove VPU_HDMI ISO */
- ctrl_table = vpu_conf.data->hdmi_iso_table;
+ ctrl_table = vpu_conf.data->iso_table;
if (ctrl_table) {
i = 0;
- while (i < VPU_HDMI_ISO_CNT_MAX) {
+ while (i < VPU_ISO_CNT_MAX) {
if (ctrl_table[i].reg == VPU_REG_END)
break;
_reg = ctrl_table[i].reg;
@@ -158,53 +146,57 @@
{
struct vpu_ctrl_s *ctrl_table;
unsigned int _reg, _start, _end, _len, _val;
- int i = 0, j;
+ int i, j;
- /* Power down VPU_HDMI */
/* Enable Isolation */
- ctrl_table = vpu_conf.data->hdmi_iso_table;
- while (i < VPU_HDMI_ISO_CNT_MAX) {
- if (ctrl_table[i].reg == VPU_REG_END)
- break;
- _reg = ctrl_table[i].reg;
- _val = ctrl_table[i].val;
- _start = ctrl_table[i].bit;
- _len = ctrl_table[i].len;
- vpu_ao_setb(_reg, _val, _start, _len);
- i++;
- }
- udelay(20);
-
- /* power down memories */
- ctrl_table = vpu_conf.data->mem_pd_table;
- i = 0;
- while (i < VPU_MEM_PD_CNT_MAX) {
- if (ctrl_table[i].reg == VPU_REG_END)
- break;
- _reg = ctrl_table[i].reg;
- _start = ctrl_table[i].bit;
- _end = ctrl_table[i].len + ctrl_table[i].bit;
- for (j = _start; j < _end; j+=2) {
- vpu_hiu_setb(_reg, 0x3, j, 2);
- udelay(5);
- }
- i++;
- }
- for (i = 8; i < 16; i++) {
- vpu_hiu_setb(HHI_MEM_PD_REG0, 0x1, i, 1);
- udelay(5);
- }
- udelay(20);
-
- /* Power down VPU domain */
- ctrl_table = vpu_conf.data->hdmi_iso_pre_table;
+ ctrl_table = vpu_conf.data->iso_table;
if (ctrl_table) {
i = 0;
- while (i < VPU_HDMI_ISO_CNT_MAX) {
+ while (i < VPU_ISO_CNT_MAX) {
if (ctrl_table[i].reg == VPU_REG_END)
break;
_reg = ctrl_table[i].reg;
- _val = ctrl_table[i].val;
+ _val = 1;
+ _start = ctrl_table[i].bit;
+ _len = ctrl_table[i].len;
+ vpu_ao_setb(_reg, _val, _start, _len);
+ i++;
+ }
+ udelay(20);
+ }
+
+ /* power down memories */
+ ctrl_table = vpu_conf.data->mem_pd_table;
+ if (ctrl_table) {
+ i = 0;
+ while (i < VPU_MEM_PD_CNT_MAX) {
+ if (ctrl_table[i].reg == VPU_REG_END)
+ break;
+ _reg = ctrl_table[i].reg;
+ _start = ctrl_table[i].bit;
+ _end = ctrl_table[i].len + ctrl_table[i].bit;
+ for (j = _start; j < _end; j+=2) {
+ vpu_hiu_setb(_reg, 0x3, j, 2);
+ udelay(5);
+ }
+ i++;
+ }
+ for (i = 8; i < 16; i++) {
+ vpu_hiu_setb(HHI_MEM_PD_REG0, 0x1, i, 1);
+ udelay(5);
+ }
+ udelay(20);
+ }
+
+ /* Power down VPU domain */
+ ctrl_table = vpu_conf.data->power_table;
+ if (ctrl_table) {
+ i = 0;
+ while (i < VPU_PWR_CNT_MAX) {
+ if (ctrl_table[i].reg == VPU_REG_END)
+ break;
+ _reg = ctrl_table[i].reg;
+ _val = 1;
_start = ctrl_table[i].bit;
_len = ctrl_table[i].len;
vpu_ao_setb(_reg, _val, _start, _len);
@@ -212,8 +204,61 @@
}
}
- vpu_hiu_setb(HHI_VAPBCLK_CNTL, 0, 8, 1);
- vpu_hiu_setb(HHI_VPU_CLK_CNTL, 0, 8, 1);
+ vpu_hiu_setb(vpu_conf.data->vapb_clk_reg, 0, 8, 1);
+ vpu_hiu_setb(vpu_conf.data->vpu_clk_reg, 0, 8, 1);
VPUPR("%s\n", __func__);
}
+
+void vpu_power_on_new(void)
+{
+#ifdef CONFIG_SECURE_POWER_CONTROL
+ unsigned int pwr_id;
+ int i = 0;
+
+ if (!vpu_conf.data->pwrctrl_id_table)
+ return;
+
+ while (i < VPU_PWR_ID_MAX) {
+ pwr_id = vpu_conf.data->pwrctrl_id_table[i];
+ if (pwr_id == VPU_PWR_ID_END)
+ break;
+#ifdef VPU_DEBUG_PRINT
+ VPUPR("%s: pwr_id=%d\n", __func__, pwr_id);
+#endif
+ pwr_ctrl_psci_smc(pwr_id, 1);
+ i++;
+ }
+ VPUPR("%s\n", __func__);
+#else
+ VPUERR("%s: no CONFIG_SECURE_POWER_CONTROL\n", __func__);
+#endif
+}
+
+void vpu_power_off_new(void)
+{
+#ifdef CONFIG_SECURE_POWER_CONTROL
+ unsigned int pwr_id;
+ int i = 0;
+
+ VPUPR("%s\n", __func__);
+ if (!vpu_conf.data->pwrctrl_id_table)
+ return;
+
+ while (i < VPU_PWR_ID_MAX) {
+ pwr_id = vpu_conf.data->pwrctrl_id_table[i];
+ if (pwr_id == VPU_PWR_ID_END)
+ break;
+#ifdef VPU_DEBUG_PRINT
+ VPUPR("%s: pwr_id=%d\n", __func__, pwr_id);
+#endif
+ pwr_ctrl_psci_smc(pwr_id, 0);
+ i++;
+ }
+#else
+ VPUERR("%s: no CONFIG_SECURE_POWER_CONTROL\n", __func__);
+#endif
+
+ vpu_hiu_setb(vpu_conf.data->vapb_clk_reg, 0, 8, 1);
+ vpu_hiu_setb(vpu_conf.data->vpu_clk_reg, 0, 8, 1);
+}
diff --git a/drivers/amlogic/media/common/vpu/vpu_reg.h b/drivers/amlogic/media/common/vpu/vpu_reg.h
index 2856ac2..af26eb7 100644
--- a/drivers/amlogic/media/common/vpu/vpu_reg.h
+++ b/drivers/amlogic/media/common/vpu/vpu_reg.h
@@ -1,23 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/common/vpu/vpu_reg.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __VPU_REG_H__
#define __VPU_REG_H__
@@ -36,12 +20,52 @@
/* memory mapping */
#define REG_ADDR_AOBUS(reg) (reg + 0L)
#define REG_ADDR_HIU(reg) (reg + 0L)
-#define REG_ADDR_CBUS(reg) (REG_BASE_CBUS + REG_OFFSET_CBUS(reg))
-#define REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg))
+#define REG_ADDR_CBUS(reg) (REG_BASE_CBUS + REG_OFFSET_CBUS(reg) + 0L)
+#define REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg) + 0L)
+
+#define REG_VPU_ADDR(reg) (reg + 0L)
/* ********************************
* register access api
* ********************************* */
+static inline unsigned int vpu_reg_read(unsigned int _reg)
+{
+ unsigned int val = 0;
+
+ val = *(volatile unsigned int *)(REG_VPU_ADDR(_reg));
+
+ return val;
+};
+
+static inline void vpu_reg_write(unsigned int _reg, unsigned int _value)
+{
+ *(volatile unsigned int *)REG_VPU_ADDR(_reg) = (_value);
+};
+
+static inline void vpu_reg_setb(unsigned int _reg, unsigned int _value,
+ unsigned int _start, unsigned int _len)
+{
+ vpu_reg_write(_reg, ((vpu_reg_read(_reg) &
+ ~(((1L << (_len))-1) << (_start))) |
+ (((_value)&((1L<<(_len))-1)) << (_start))));
+}
+
+static inline unsigned int vpu_reg_getb(unsigned int _reg,
+ unsigned int _start, unsigned int _len)
+{
+ return (vpu_reg_read(_reg) >> (_start)) & ((1L << (_len)) - 1);
+}
+
+static inline void vpu_reg_set_mask(unsigned int _reg, unsigned int _mask)
+{
+ vpu_reg_write(_reg, (vpu_reg_read(_reg) | (_mask)));
+}
+
+static inline void vpu_reg_clr_mask(unsigned int _reg, unsigned int _mask)
+{
+ vpu_reg_write(_reg, (vpu_reg_read(_reg) & (~(_mask))));
+}
+
static inline unsigned int vpu_hiu_read(unsigned int _reg)
{
unsigned int val = 0;
@@ -83,13 +107,20 @@
static inline unsigned int vpu_vcbus_read(unsigned int _reg)
{
unsigned int val = 0;
- val = *(volatile unsigned int *)(REG_ADDR_VCBUS(_reg));
+
+ if (_reg > 0x10000)
+ val = vpu_reg_read(_reg);
+ else
+ val = *(volatile unsigned int *)(REG_ADDR_VCBUS(_reg));
return val;
};
static inline void vpu_vcbus_write(unsigned int _reg, unsigned int _value)
{
- *(volatile unsigned int *)REG_ADDR_VCBUS(_reg) = (_value);
+ if (_reg > 0x10000)
+ vpu_reg_write(_reg, _value);
+ else
+ *(volatile unsigned int *)REG_ADDR_VCBUS(_reg) = (_value);
};
static inline void vpu_vcbus_setb(unsigned int _reg, unsigned int _value,
@@ -103,13 +134,20 @@
static inline unsigned int vpu_cbus_read(unsigned int _reg)
{
unsigned int val = 0;
- val = *(volatile unsigned int *)(REG_ADDR_CBUS(_reg));
+
+ if (_reg > 0x10000)
+ val = vpu_reg_read(_reg);
+ else
+ val = *(volatile unsigned int *)(REG_ADDR_CBUS(_reg));
return val;
};
static inline void vpu_cbus_write(unsigned int _reg, unsigned int _value)
{
- *(volatile unsigned int *)REG_ADDR_CBUS(_reg) = (_value);
+ if (_reg > 0x10000)
+ vpu_reg_write(_reg, _value);
+ else
+ *(volatile unsigned int *)REG_ADDR_CBUS(_reg) = (_value);
};
static inline void vpu_cbus_setb(unsigned int _reg, unsigned int _value,
diff --git a/drivers/amlogic/media/osd/Kconfig b/drivers/amlogic/media/osd/Kconfig
index e69de29..2ff2ccf 100644
--- a/drivers/amlogic/media/osd/Kconfig
+++ b/drivers/amlogic/media/osd/Kconfig
@@ -0,0 +1,4 @@
+config AML_DOLBY
+ bool "AML DOLBY driver support"
+ help
+ Enable support for the Amlogic DOLBY driver.
diff --git a/drivers/amlogic/media/osd/Makefile b/drivers/amlogic/media/osd/Makefile
index 54aa832..ea8983e 100644
--- a/drivers/amlogic/media/osd/Makefile
+++ b/drivers/amlogic/media/osd/Makefile
@@ -2,3 +2,4 @@
#
obj-$(CONFIG_AML_OSD) += osd_hw.o osd_fb.o osd_debug.o
+obj-$(CONFIG_AML_DOLBY) += dv/
\ No newline at end of file
diff --git a/drivers/amlogic/media/osd/dv/Makefile b/drivers/amlogic/media/osd/dv/Makefile
new file mode 100644
index 0000000..22fb647
--- /dev/null
+++ b/drivers/amlogic/media/osd/dv/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_AML_DOLBY) += dolby_vision.o
diff --git a/drivers/amlogic/media/osd/dv/dolby_vision.c b/drivers/amlogic/media/osd/dv/dolby_vision.c
new file mode 100644
index 0000000..8c4791f
--- /dev/null
+++ b/drivers/amlogic/media/osd/dv/dolby_vision.c
@@ -0,0 +1,1421 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/io.h>
+#include <asm/arch/secure_apb.h>
+#include <amlogic/media/vout/aml_vmode.h>
+#include <amlogic/storage.h>
+#include <amlogic/media/vout/aml_vout.h>
+#include <amlogic/media/vout/hdmitx/hdmitx_module.h>
+
+#include <amlogic/media/dv/dolby_vision.h>
+#include <amlogic/media/dv/dolby_vision_func.h>
+
+#include <malloc.h>
+#include <config.h>
+#include <mmc.h>
+#include <asm/byteorder.h>
+#include <asm/unaligned.h>
+#include <amlogic/cpu_id.h>
+
+#include "./../vpp.h"
+#include "./../hdr2.h"
+
+#include <asm/arch/io.h>
+//#include <asm/arch/secure_apb.h>
+
+static struct dovi_setting_s dovi_setting;
+static struct dovi_mode_s dovi_mode;
+static unsigned int dolby_vision_mode = DOLBY_VISION_OUTPUT_MODE_BYPASS;
+static unsigned int dolby_vision_ll_policy = DOLBY_VISION_LL_DISABLE;
+static unsigned int dv_ll_output_mode = DOLBY_VISION_OUTPUT_MODE_HDR10;
+static unsigned int dolby_vision_target_min = 50; /* 0.0001 */
+static unsigned int dolby_vision_target_max[3][3] = {
+ { 4000, 1000, 100 }, /* DOVI => DOVI/HDR/SDR */
+ { 1000, 1000, 100 }, /* HDR => DOVI/HDR/SDR */
+ { 600, 1000, 100 }, /* SDR => DOVI/HDR/SDR */
+};
+static unsigned int dolby_vision_target_graphics_max[3] = {
+ 300, 300, 100
+}; /* DOVI/HDR/SDR */
+
+/* 0: video priority 1: graphic priority */
+static unsigned int dv_graphics_priority = 1;
+
+static unsigned int vinfo_width = 1920;
+static unsigned int vinfo_height = 1080;
+static unsigned int vinfo_duration_num = 60;
+static unsigned int vinfo_field_height = 1080;
+static bool dolby_vision_on;
+static char *dolby_status;
+#define COEFF_NORM(a) ((int)((((a) * 2048.0) + 1) / 2))
+#define MATRIX_5x3_COEF_SIZE 24
+
+static int RGB709_to_YUV709l_coeff[MATRIX_5x3_COEF_SIZE] = {
+ 0, 0, 0, /* pre offset */
+ COEFF_NORM(0.181873), COEFF_NORM(0.611831), COEFF_NORM(0.061765),
+ COEFF_NORM(-0.100251), COEFF_NORM(-0.337249), COEFF_NORM(0.437500),
+ COEFF_NORM(0.437500), COEFF_NORM(-0.397384), COEFF_NORM(-0.040116),
+ 0, 0, 0, /* 10'/11'/12' */
+ 0, 0, 0, /* 20'/21'/22' */
+ 64, 512, 512, /* offset */
+ 0, 0, 0 /* mode, right_shift, clip_en */
+};
+static int bypass_coeff[MATRIX_5x3_COEF_SIZE] = {
+ 0, 0, 0, /* pre offset */
+ COEFF_NORM(1.0), COEFF_NORM(0.0), COEFF_NORM(0.0),
+ COEFF_NORM(0.0), COEFF_NORM(1.0), COEFF_NORM(0.0),
+ COEFF_NORM(0.0), COEFF_NORM(0.0), COEFF_NORM(1.0),
+ 0, 0, 0, /* 10'/11'/12' */
+ 0, 0, 0, /* 20'/21'/22' */
+ 0, 0, 0, /* offset */
+ 0, 0, 0 /* mode, right_shift, clip_en */
+};
+static int dvll_RGB_to_YUV709l_coeff[MATRIX_5x3_COEF_SIZE] = {
+ 0, 0, 0, /* pre offset */
+ COEFF_NORM(0.181873), COEFF_NORM(0.611831), COEFF_NORM(0.061765),
+ COEFF_NORM(-0.100251), COEFF_NORM(-0.337249), COEFF_NORM(0.437500),
+ COEFF_NORM(0.437500), COEFF_NORM(-0.397384), COEFF_NORM(-0.040116),
+ 0, 0, 0, /* 10'/11'/12' */
+ 0, 0, 0, /* 20'/21'/22' */
+ 64, 512, 512, /* offset */
+ 0, 0, 0 /* mode, right_shift, clip_en */
+};
+
+static int *cur_osd_mtx = RGB709_to_YUV709l_coeff;
+static int *cur_vd1_mtx = bypass_coeff;
+static unsigned int debug_enable = 0;
+
+static bool tv_mode;
+
+#define MAX_PARAM 8
+
+#ifndef REG_BASE_VCBUS
+#define REG_BASE_VCBUS (0xFF900000L)
+#endif
+#define REG_BASE_VCBUS_SC2 (0xFF000000L)
+
+#define REG_OFFSET_VCBUS(reg) ((reg << 2))
+#define REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg))
+#define REG_ADDR_VCBUS_SC2(reg) (REG_BASE_VCBUS_SC2 + REG_OFFSET_VCBUS(reg))
+#define REG_DV_ADDR(reg) (reg + 0L)
+
+static inline bool is_meson_gxm(void)
+{
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXM)
+ return true;
+ else
+ return false;
+}
+static inline bool is_meson_g12(void)
+{
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A ||
+ get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B ||
+ get_cpu_id().family_id == MESON_CPU_MAJOR_ID_SM1)
+ return true;
+ else
+ return false;
+}
+
+static inline bool is_meson_sc2(void)
+{
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_SC2)
+ return true;
+ else
+ return false;
+}
+
+static inline bool is_meson_box(void)
+{
+ if (is_meson_gxm() || is_meson_g12() || is_meson_sc2())
+ return true;
+ else
+ return false;
+}
+
+static inline bool is_meson_txlx(void)
+{
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TXLX)
+ return true;
+ else
+ return false;
+}
+
+static inline bool is_meson_txlx_tvmode(void)
+{
+ if ((is_meson_txlx()) && (tv_mode == 1))
+ return true;
+ else
+ return false;
+}
+static inline bool is_meson_txlx_stbmode(void)
+{
+ if ((is_meson_txlx()) && (tv_mode == 0))
+ return true;
+ else
+ return false;
+}
+static inline bool is_meson_tm2(void)
+{
+ if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TM2)
+ return true;
+ else
+ return false;
+}
+
+static inline bool is_meson_tm2_tvmode(void)
+{
+ if ((is_meson_tm2()) && (tv_mode == 1))
+ return true;
+ else
+ return false;
+}
+
+static inline bool is_meson_tm2_stbmode(void)
+{
+ if ((is_meson_tm2()) && (tv_mode == 0))
+ return true;
+ else
+ return false;
+}
+
+static inline bool is_meson_tvmode(void)
+{
+ if (is_meson_tm2_tvmode() ||
+ is_meson_txlx_tvmode())
+ return true;
+ else
+ return false;
+}
+static inline u32 READ_VPP_REG(u32 reg)
+{
+ u32 val;
+
+ if (reg > 0x10000)
+ val = *(volatile unsigned int *)REG_DV_ADDR(reg);
+ else {
+ if (is_meson_sc2())
+ val = *(volatile unsigned int *)REG_ADDR_VCBUS_SC2(reg);
+ else
+ val = *(volatile unsigned int *)REG_ADDR_VCBUS(reg);
+ }
+ return val;
+}
+
+static inline void WRITE_VPP_REG(u32 reg,
+ const u32 val)
+{
+ if (reg > 0x10000)
+ *(volatile unsigned int *)REG_DV_ADDR(reg) = (val);
+ else {
+ if (is_meson_sc2())
+ *(volatile unsigned int *)REG_ADDR_VCBUS_SC2(reg) = (val);
+ else
+ *(volatile unsigned int *)REG_ADDR_VCBUS(reg) = (val);
+ }
+}
+
+static inline void WRITE_VPP_REG_BITS(uint32_t reg,
+ const uint32_t value, const uint32_t start, const uint32_t len)
+{
+ WRITE_VPP_REG(reg, ((READ_VPP_REG(reg) &
+ ~(((1L << (len)) - 1) << (start))) |
+ (((value) & ((1L << (len)) - 1)) << (start))));
+}
+
+static inline u32 phyaddr_to_dvaddr(u32 reg) {
+ u32 val;
+
+ if (reg > 0x10000) {
+ if (is_meson_sc2())
+ val = (reg - REG_BASE_VCBUS_SC2) >> 2;
+ else
+ val = (reg - REG_BASE_VCBUS) >> 2;
+ return val;
+ } else {
+ return reg;
+ }
+}
+
+#ifdef CONFIG_AML_DOLBY
+/*check dolby enable status,if status is disabled, not enable dolby
+*/
+int is_dolby_enable(void)
+{
+ if (!dolby_status)
+ dolby_status = env_get("dolby_status");
+
+ printf("dolby_status %s\n", dolby_status);
+ if (!strcmp(dolby_status, DOLBY_VISION_SET_STD) ||
+ !strcmp(dolby_status, DOLBY_VISION_SET_LL_YUV) ||
+ !strcmp(dolby_status, DOLBY_VISION_SET_LL_RGB))
+ return 1;
+ else
+ return 0;
+}
+bool request_ll_mode(void)
+{
+ if (!dolby_status)
+ dolby_status = env_get("dolby_status");
+
+ if (!strcmp(dolby_status, DOLBY_VISION_SET_LL_RGB) ||
+ !strcmp(dolby_status, DOLBY_VISION_SET_LL_YUV)) {
+ printf("request LL mode\n");
+ return true;
+ } else
+ return false;
+}
+bool check_dolby_vision_on(void)
+{
+ if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12A) ||
+ (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_G12B) ||
+ (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_SM1) ||
+ (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TM2) ||
+ (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_SC2)) {
+ if (READ_VPP_REG(DOLBY_CORE3_SWAP_CTRL0) & 0x1)
+ return true;
+ }
+ return false;
+}
+#endif
+
+unsigned int dv_read_reg(unsigned int addr)
+{
+ return READ_VPP_REG(addr);
+}
+
+void dv_write_reg(unsigned int addr, unsigned int value)
+{
+ WRITE_VPP_REG(addr, value);
+}
+/*
+static int check_tv_has_changed(struct hdmitx_dev* hdmitx_device)
+{
+ return hdmitx_device->RXCap.edid_changed;
+}*/
+
+static int check_tv_hpd_status(struct hdmitx_dev* hdmitx_device)
+{
+ return hdmitx_device->hwop.get_hpd_state();
+}
+
+static int check_tv_support_dv(struct hdmitx_dev *hdmitx_device)
+{
+ struct dv_info* dv_info = NULL;
+ int maxTMDSRate = 0;
+ //int preferredMode = hdmitx_device->RXCap.preferred_mode;
+
+ //1.tv not changed, use outputmode from env
+ //2.tv changed,hdmi will choose best mode and update outputmode to env
+ char *outputmode = env_get("outputmode");
+ printf("check_tv_support_dv, outputmode %s\n", outputmode);
+
+ if (!hdmitx_device) {
+ printf("null hdmitx_device\n");
+ return 0;
+ }
+ if (hdmitx_device->RXCap.dv_info.ieeeoui != 0x00d046) {
+ printf("dv_info.ieeeoui %x\n", hdmitx_device->RXCap.dv_info.ieeeoui);
+ return 0;
+ }
+ if (hdmitx_device->RXCap.dv_info.block_flag != CORRECT) {
+ printf("dv_info.block_flag %x\n", hdmitx_device->RXCap.dv_info.block_flag);
+ return 0;
+ }
+
+ dv_info = &hdmitx_device->RXCap.dv_info;
+
+ if (dv_info->ver == 0) {
+ dovi_mode.dv_rgb_444_8bit = 1;
+ if (dv_info->sup_2160p60hz)
+ dovi_mode.sup_2160p60hz = 1;
+ } else if ((dv_info->ver == 1) && (dv_info->length == 0xB)) {
+ dovi_mode.dv_rgb_444_8bit = 1;
+ if (dv_info->low_latency == 0x01)
+ dovi_mode.ll_ycbcr_422_12bit = 1;
+ if (dv_info->sup_2160p60hz)
+ dovi_mode.sup_2160p60hz = 1;
+ } else if ((dv_info->ver == 1) && (dv_info->length == 0xE)) {
+ dovi_mode.dv_rgb_444_8bit = 1;
+ if (dv_info->sup_2160p60hz)
+ dovi_mode.sup_2160p60hz = 1;
+ } else if (dv_info->ver == 2) {
+ dovi_mode.ll_ycbcr_422_12bit = 1;
+ if ((dv_info->Interface != 0x00) && (dv_info->Interface != 0x01))
+ dovi_mode.dv_rgb_444_8bit = 1;
+ if ((dv_info->Interface == 0x01) || (dv_info->Interface == 0x03)) {
+ if (dv_info->sup_10b_12b_444 == 0x1)
+ dovi_mode.ll_rgb_444_10bit = 1;
+ if (dv_info->sup_10b_12b_444 == 0x2)
+ dovi_mode.ll_rgb_444_12bit = 1;
+ }
+ dovi_mode.sup_2160p60hz = 1;
+ }
+
+ //if preferred mode is 4k, make sure it can be truly supported in DV format
+ if (hdmitx_device->RXCap.Max_TMDS_Clock2 != 0) {
+ maxTMDSRate = hdmitx_device->RXCap.Max_TMDS_Clock2 * 5;
+ printf("check_tv_support_dv: maxTMDSRate1 = %d\n", maxTMDSRate);
+ } else {
+ if (hdmitx_device->RXCap.Max_TMDS_Clock1 < 0xf)
+ hdmitx_device->RXCap.Max_TMDS_Clock1 = 0x1e;
+ maxTMDSRate = hdmitx_device->RXCap.Max_TMDS_Clock1 * 5;
+ printf("check_tv_support_dv: maxTMDSRate2 = %d\n", maxTMDSRate);
+ }
+ //return true only if DV can truly be supported for a given mode
+ if (strstr(outputmode, "2160p60hz") || strstr(outputmode, "2160p50hz")) {
+ if ((dovi_mode.sup_2160p60hz) && (maxTMDSRate >= 594)) {
+ //safety check for yuv420 - shudn't be the case
+ if (strstr(outputmode, "2160p60hz420"))
+ env_set("outputmode", "2160p60hz");
+ if (strstr(outputmode, "2160p50hz420"))
+ env_set("outputmode", "2160p50hz");
+ printf("check_tv_support_dv: 4k60 dovi supported\n");
+ return 1;
+ } else {
+ printf("check_tv_support_dv: 4k60 dovi NOT supported\n");
+ return 0;
+ }
+ }
+ return 1;
+}
+
+static int check_tv_support_hdr(struct hdmitx_dev *hdmitx_device)
+{
+ if (!hdmitx_device)
+ return 0;
+ if (hdmitx_device->RXCap.hdr_info.hdr_sup_eotf_smpte_st_2084)
+ return 1;
+ return 0;
+}
+
+#if 0
+/* not needed anymore */
+/*if tv has changed, choose the preferred mode and check if dv support this preferred mode*/
+static int check_tv_dv_mode(struct hdmitx_dev *hdmitx_device)
+{
+
+ if (dovi_mode.dv_rgb_444_8bit) {
+ env_set("colorattribute", "444,8bit");
+ if ((hdmitx_device->RXCap.preferred_mode
+ == HDMI_3840x2160p50_16x9) ||
+ (hdmitx_device->RXCap.preferred_mode
+ == HDMI_3840x2160p60_16x9)) {
+ if ((dovi_mode.sup_2160p60hz) &&
+ (hdmitx_device->RXCap.Max_TMDS_Clock2 * 5 == 600))
+ env_set("outputmode", "2160p60hz");
+ else
+ env_set("outputmode", "1080p60hz");
+ } else if (hdmitx_device->RXCap.preferred_mode
+ == HDMI_1920x1080p60_16x9)
+ env_set("outputmode", "1080p60hz");
+ else if (hdmitx_device->RXCap.preferred_mode
+ == HDMI_1920x1080p50_16x9)
+ env_set("outputmode", "1080p50hz");
+ else if (hdmitx_device->RXCap.preferred_mode
+ == HDMI_1280x720p60_16x9)
+ env_set("outputmode", "720p60hz");
+ else if (hdmitx_device->RXCap.preferred_mode
+ == HDMI_1280x720p50_16x9)
+ env_set("outputmode", "720p50hz");
+ else
+ env_set("outputmode", "1080p60hz");
+ printf("output dv standard mode : mode is : %s attr: %s\n",
+ env_get("outputmode"), env_get("colorattribute"));
+ } else if (dovi_mode.ll_ycbcr_422_12bit) {
+ setenv("colorattribute", "422,12bit");
+ if ((hdmitx_device->RXCap.preferred_mode
+ == HDMI_3840x2160p50_16x9) ||
+ (hdmitx_device->RXCap.preferred_mode
+ == HDMI_3840x2160p60_16x9)) {
+ if ((dovi_mode.sup_2160p60hz) &&
+ (hdmitx_device->RXCap.Max_TMDS_Clock2 * 5 == 600))
+ env_set("outputmode", "2160p60hz");
+ else
+ env_set("outputmode", "1080p60hz");
+ } else if (hdmitx_device->RXCap.preferred_mode
+ == HDMI_1920x1080p60_16x9)
+ env_set("outputmode", "1080p60hz");
+ else if (hdmitx_device->RXCap.preferred_mode
+ == HDMI_1920x1080p50_16x9)
+ env_set("outputmode", "1080p50hz");
+ else if (hdmitx_device->RXCap.preferred_mode
+ == HDMI_1280x720p60_16x9)
+ env_set("outputmode", "720p60hz");
+ else if (hdmitx_device->RXCap.preferred_mode
+ == HDMI_1280x720p50_16x9)
+ env_set("outputmode", "720p50hz");
+ else
+ env_set("outputmode", "1080p60hz");
+ printf("output dv LL 422 mode : mode is : %s attr: %s\n",
+ env_get("outputmode"), env_get("colorattribute"));
+ } else if (dovi_mode.ll_rgb_444_10bit) {
+ env_set("colorattribute", "444,10bit");
+ env_set("outputmode", "1080p60hz");
+ printf("output dv LL 444 mode : mode is : %s attr: %s\n",
+ env_get("outputmode"), env_get("colorattribute"));
+ } else if (dovi_mode.ll_rgb_444_12bit) {
+ env_set("colorattribute", "444,12bit");
+ env_set("outputmode", "1080p60hz");
+ printf("output dv LL 444 mode : mode is : %s attr: %s\n",
+ env_get("outputmode"), env_get("colorattribute"));
+ } else {
+ env_set("colorattribute", "444,8bit");
+ env_set("outputmode", "1080p60hz");
+ }
+ return 0;
+}
+#endif
+
+/*true: attr match with dv_moder*/
+/*false: attr not match with dv_mode*/
+static bool is_attr_match(void)
+{
+ char *attr = env_get("colorattribute");
+
+ /*two case use std mode: */
+ /*1.user not requeset LL mode*/
+ /*2.user request LL mode but sink not support LL mode*/
+ if (dovi_mode.dv_rgb_444_8bit &&
+ (!request_ll_mode() || dovi_mode.ll_ycbcr_422_12bit == 0)) { /*STD*/
+ if (!strstr(attr, "444,8bit")) {
+ printf("expect output DV, but attr is %s\n", attr);
+ return false;
+ }
+ } else if (dovi_mode.ll_ycbcr_422_12bit) { /*LL YUV*/
+ if (!strstr(attr, "422,12bit")) {
+ printf("expect output LL YUV, but attr is %s\n", attr);
+ dovi_setting.dst_format = FORMAT_SDR;
+ return false;
+ }
+ } else if (dovi_mode.ll_rgb_444_10bit) { /*LL RGB*/
+ if (!strstr(attr, "444,10bit")) {
+ printf("expect output LL RGB, but attr is %s\n", attr);
+ dovi_setting.dst_format = FORMAT_SDR;
+ return false;
+ }
+ }
+ return true;
+}
+static int check_tv_support(struct hdmitx_dev *hdmitx_device)
+{
+ if (check_tv_support_dv(hdmitx_device)) {
+ if (is_attr_match()) {
+ dovi_setting.dst_format = FORMAT_DOVI;
+ printf("output dovi mode: mode is : %s attr: %s\n",
+ env_get("outputmode"), env_get("colorattribute"));
+ } else {
+ dovi_setting.dst_format = FORMAT_SDR;
+ printf("attr is not match, change to output SDR\n");
+ }
+ } else if (check_tv_support_hdr(hdmitx_device)) {
+ dovi_setting.dst_format = FORMAT_HDR10;
+ printf("output hdr mode: mode is : %s attr: %s\n",
+ env_get("outputmode"), env_get("colorattribute"));
+ } else {
+ dovi_setting.dst_format = FORMAT_SDR;
+ printf("output sdr mode: mode is : %s attr: %s\n",
+ env_get("outputmode"), env_get("colorattribute"));
+ }
+ return 0;
+}
+
+static void dolby_vision_get_vinfo(struct hdmitx_dev *hdmitx_device)
+{
+ uint32_t width;
+ uint32_t height;
+ uint32_t sync_duration_num;
+ uint32_t field_height;
+ char *mode_name;
+
+ mode_name = env_get("outputmode");
+
+ if (strstr(mode_name, "1080")) {
+ width = 1920;
+ height = 1080;
+ } else if (strstr(mode_name, "2160")) {
+ width = 3840;
+ height = 2160;
+ } else if (strstr(mode_name, "720")) {
+ width = 1280;
+ height = 720;
+ } else if (strstr(mode_name, "576")) {
+ width = 720;
+ height = 576;
+ } else if (strstr(mode_name, "480")) {
+ width = 720;
+ height = 480;
+ } else if (strstr(mode_name, "smpte")) {
+ width = 4096;
+ height = 2160;
+ } else {
+ printf("unkown mode, use default 1080p\n");
+ width = 1920;
+ height = 1080;
+ }
+
+ if (strstr(mode_name, "60hz"))
+ sync_duration_num = 60;
+ else if (strstr(mode_name, "50hz"))
+ sync_duration_num = 50;
+ else if (strstr(mode_name, "30hz"))
+ sync_duration_num = 30;
+ else if (strstr(mode_name, "25hz"))
+ sync_duration_num = 25;
+ else if (strstr(mode_name, "24hz"))
+ sync_duration_num = 24;
+ else
+ sync_duration_num = 60;
+
+ if (strstr(mode_name, "i"))
+ field_height = height/2;
+ else
+ field_height = height;
+
+ vinfo_width = width;
+ vinfo_height = height;
+ vinfo_duration_num = sync_duration_num;
+ vinfo_field_height = field_height;
+
+}
+
+static void dolby_vision_parse(struct hdmitx_dev *hdmitx_device)
+{
+ enum signal_format_e src_format = FORMAT_SDR;
+ enum signal_format_e dst_format = dovi_setting.dst_format;
+ unsigned int graphic_min = 50;
+ unsigned int graphic_max = 100;
+ unsigned int target_max = 100;
+ unsigned int w = 3840;
+ unsigned int h = 2160;
+
+ dolby_vision_get_vinfo(hdmitx_device);
+ dovi_setting.vout_width = vinfo_width;
+ dovi_setting.vout_height= vinfo_height;
+ dovi_setting.g_bitdepth = 8;
+ dovi_setting.g_format = GF_SDR_RGB;
+ dovi_setting.video_width = w << 16;
+ dovi_setting.video_height = h << 16;
+
+ if(dst_format >= 0
+ && dst_format <= 2)
+ graphic_max = dolby_vision_target_graphics_max[dst_format];
+
+ if (dovi_setting.dst_format == FORMAT_DOVI) {
+ memset(&dovi_setting.vsvdb_tbl[0],
+ 0, sizeof(dovi_setting.vsvdb_tbl));
+ memcpy(&dovi_setting.vsvdb_tbl[0],
+ &hdmitx_device->RXCap.dv_info.rawdata[0],
+ hdmitx_device->RXCap.dv_info.length + 1);
+
+ //two case use std mode:
+ //1.user not requeset LL mode
+ //2.user request LL mode but sink not support LL mode
+ if (dovi_mode.dv_rgb_444_8bit &&
+ (!request_ll_mode() || dovi_mode.ll_ycbcr_422_12bit == 0))
+ ;
+ else if (dovi_mode.ll_ycbcr_422_12bit) {
+ dovi_setting.use_ll_flag = 1;
+ dovi_setting.dovi_ll_enable = 1;
+ } else if (dovi_mode.ll_rgb_444_10bit) {
+ dovi_setting.use_ll_flag = 1;
+ dovi_setting.dovi_ll_enable = 1;
+ dovi_setting.ll_rgb_desired= 1;
+ dovi_setting.diagnostic_enable = 1;
+ }
+ } else if (dovi_setting.dst_format == FORMAT_HDR10) {
+ if (hdmitx_device->RXCap.hdr_info.hdr_lum_max) {
+ graphic_max = 50 * (2 ^ (hdmitx_device->RXCap.hdr_info.hdr_lum_max >> 5));
+ graphic_max = graphic_max * 10000
+ * hdmitx_device->RXCap.hdr_info.hdr_lum_min
+ * hdmitx_device->RXCap.hdr_info.hdr_lum_min
+ / (255 * 255 * 100);
+ }
+ } else
+ ;
+
+ if ((src_format >= 0 && src_format <= 2) &&
+ (dst_format >= 0 && dst_format <= 2))
+ target_max = dolby_vision_target_max[src_format][dst_format];
+
+ DV_func.control_path(
+ src_format, dst_format,
+ NULL, 0,
+ NULL, 0,
+ dv_graphics_priority,
+ 12, 0, 0,
+ graphic_min,
+ graphic_max * 10000,
+ dolby_vision_target_min,
+ target_max * 10000, 1,
+ NULL,
+ &dovi_setting);
+}
+
+static bool need_skip_cvm(unsigned int is_graphic) {
+ return false;
+}
+
+static unsigned int mtx_en_mux;
+static void video_effect_bypass(int bypass)
+{
+ WRITE_VPP_REG(VPP_EOTF_CTL, 0);
+ WRITE_VPP_REG(XVYCC_LUT_CTL, 0);
+ WRITE_VPP_REG(XVYCC_INV_LUT_CTL, 0);
+ WRITE_VPP_REG(VPP_VADJ_CTRL, 0);
+ WRITE_VPP_REG(VPP_GAINOFF_CTRL0, 0);
+ WRITE_VPP_REG(VPP_VE_ENABLE_CTRL, 0);
+ WRITE_VPP_REG(XVYCC_VD1_RGB_CTRST, 0);
+}
+static void vpp_set_mtx_en_write(void)
+{
+ int reg_val;
+
+ reg_val = READ_VPP_REG(VPP_MATRIX_CTRL);
+ WRITE_VPP_REG(VPP_MATRIX_CTRL, (reg_val &
+ (~(POST_MTX_EN_MASK |
+ VD2_MTX_EN_MASK |
+ VD1_MTX_EN_MASK |
+ XVY_MTX_EN_MASK |
+ OSD1_MTX_EN_MASK))) |
+ mtx_en_mux);
+}
+
+static void vpp_set_mtx_en_read(void)
+{
+ int reg_value;
+
+ reg_value = READ_VPP_REG(VPP_MATRIX_CTRL);
+ mtx_en_mux = reg_value &
+ (POST_MTX_EN_MASK |
+ VD2_MTX_EN_MASK |
+ VD1_MTX_EN_MASK |
+ XVY_MTX_EN_MASK |
+ OSD1_MTX_EN_MASK);
+}
+
+static int enable_rgb_to_yuv_matrix_for_dvll(
+ int32_t on, uint32_t *coeff_orig, uint32_t bits)
+{
+ int32_t i;
+ uint32_t coeff01, coeff23, coeff45, coeff67, coeff89;
+ uint32_t scale, shift, offset[3];
+ int32_t *coeff = dvll_RGB_to_YUV709l_coeff;
+
+ if ((bits < 10) || (bits > 12))
+ return -1;
+ if (on && !coeff_orig)
+ return -2;
+ if (on) {
+ coeff01 = coeff_orig[0];
+ coeff23 = coeff_orig[1];
+ coeff45 = coeff_orig[2];
+ coeff67 = coeff_orig[3];
+ coeff89 = coeff_orig[4] & 0xffff;
+ scale = (coeff_orig[4] >> 16) & 0x0f;
+ offset[0] = coeff_orig[5];
+ offset[1] = 0; /* coeff_orig[6]; */
+ offset[2] = 0; /* coeff_orig[7]; */
+
+ coeff[0] = coeff[1] = coeff[2] = 0; /* pre offset */
+
+ coeff[5] = (int32_t)((coeff01 & 0xffff) << 16) >> 16;
+ coeff[3] = (int32_t)coeff01 >> 16;
+ coeff[4] = (int32_t)((coeff23 & 0xffff) << 16) >> 16;
+ coeff[8] = (int32_t)coeff23 >> 16;
+ coeff[6] = (int32_t)((coeff45 & 0xffff) << 16) >> 16;
+ coeff[7] = (int32_t)coeff45 >> 16;
+ coeff[11] = (int32_t)((coeff67 & 0xffff) << 16) >> 16;
+ coeff[9] = (int32_t)coeff67 >> 16;
+ coeff[10] = (int32_t)((coeff89 & 0xffff) << 16) >> 16;
+
+ if (scale > 12) {
+ shift = scale - 12;
+ for (i = 3; i < 12; i++)
+ coeff[i] = (coeff[i] + (1 << (shift - 1))) >> shift;
+ } else if (scale < 12) {
+ shift = 12 - scale;
+ for (i = 3; i < 12; i++)
+ coeff[i] <<= shift;
+ }
+
+ /* post offset */
+ coeff[18] = offset[0];
+ coeff[19] = offset[1];
+ coeff[20] = offset[2];
+
+ coeff[5] = ((coeff[3] + coeff[4] + coeff[5]) & 0xfffe)
+ - coeff[3] - coeff[4];
+ coeff[8] = 0 - coeff[6] - coeff[7];
+ coeff[11] = 0 - coeff[9] - coeff[10];
+ coeff[18] -= (0x1000 - coeff[3] - coeff[4] - coeff[5]) >> 1;
+
+ coeff[22] = 2;
+ vpp_set_mtx_en_read();
+ WRITE_VPP_REG(VPP_MATRIX_CTRL, 0);
+ set_vpp_matrix(VPP_MATRIX_OSD,
+ cur_osd_mtx, CSC_OFF);
+ set_vpp_matrix(VPP_MATRIX_VD1,
+ cur_vd1_mtx, CSC_OFF);
+ set_vpp_matrix(VPP_MATRIX_POST,
+ coeff, CSC_ON);
+ vpp_set_mtx_en_write();
+ }
+ return 0;
+}
+
+static int dolby_core2_set(
+ const uint32_t dm_count,
+ const uint32_t lut_count,
+ uint32_t *p_core2_dm_regs,
+ uint32_t *p_core2_lut,
+ int hsize,
+ int vsize,
+ int dolby_enable,
+ int lut_endian)
+{
+ uint32_t count;
+ int i;
+ uint32_t bypass_flag = 0;
+
+ uint32_t g_htotal_add = 0x40;
+ uint32_t g_vtotal_add = 0x80;
+ uint32_t g_vsize_add = 0;
+ uint32_t g_vwidth = 0x18;
+ uint32_t g_hwidth = 0x10;
+ uint32_t g_vpotch;
+ uint32_t g_hpotch = 0x10;
+ u32 addr = 0;
+
+ /* adjust core2 setting to work around*/
+ /* fixing with 1080p24hz and 480p60hz */
+ if ((vinfo_width < 1280) && ((vinfo_height < 720)
+ && (vinfo_field_height < 720)))
+ g_vpotch = 0x60;
+ else if ((vinfo_width == 1280) &&
+ (vinfo_height == 720) &&
+ (vinfo_field_height < 720))
+ g_vpotch = 0x60;
+ else if ((vinfo_width == 1920) &&
+ (vinfo_height == 1080) &&
+ (vinfo_duration_num == 24))
+ g_vpotch = 0x60;
+ else if ((vinfo_width == 1920) &&
+ (vinfo_height == 1080) &&
+ (vinfo_field_height < 1080))
+ g_vpotch = 0x60;
+ else if ((vinfo_width == 1280) && (vinfo_height == 720))
+ g_vpotch = 0x38;
+ else
+ g_vpotch = 0x20;
+ WRITE_VPP_REG(DOLBY_CORE2A_CLKGATE_CTRL, 0);
+
+ WRITE_VPP_REG(DOLBY_CORE2A_SWAP_CTRL0, 0);
+
+ WRITE_VPP_REG(DOLBY_CORE2A_SWAP_CTRL1,
+ ((hsize + g_htotal_add) << 16)
+ | (vsize + g_vtotal_add + g_vsize_add));
+ WRITE_VPP_REG(DOLBY_CORE2A_SWAP_CTRL2,
+ (hsize << 16) | (vsize + g_vsize_add));
+ WRITE_VPP_REG(DOLBY_CORE2A_SWAP_CTRL3,
+ (g_hwidth << 16) | g_vwidth);
+ WRITE_VPP_REG(DOLBY_CORE2A_SWAP_CTRL4,
+ (g_hpotch << 16) | g_vpotch);
+ if (is_meson_txlx_stbmode())
+ WRITE_VPP_REG(DOLBY_CORE2A_SWAP_CTRL5, 0xf8000000);
+ else if (is_meson_g12() || is_meson_tm2_stbmode() || is_meson_sc2())
+ WRITE_VPP_REG(DOLBY_CORE2A_SWAP_CTRL5, 0xa8000000);
+ else
+ WRITE_VPP_REG(DOLBY_CORE2A_SWAP_CTRL5, 0x0);
+
+
+ WRITE_VPP_REG(DOLBY_CORE2A_DMA_CTRL, 0x0);
+ WRITE_VPP_REG(DOLBY_CORE2A_Metadata_Start, 1);
+ if (need_skip_cvm(1))
+ bypass_flag |= 1 << 0;
+ WRITE_VPP_REG(DOLBY_CORE2A_Metadata_Start, 1);
+ WRITE_VPP_REG(DOLBY_CORE2A_CTRL,
+ 2 | bypass_flag);
+ WRITE_VPP_REG(DOLBY_CORE2A_CTRL,
+ 2 | bypass_flag);
+ WRITE_VPP_REG(DOLBY_CORE2A_CTRL, 0);
+ WRITE_VPP_REG(DOLBY_CORE2A_CTRL, 0);
+
+ if (dm_count == 0)
+ count = 24;
+ else
+ count = dm_count;
+
+ addr = phyaddr_to_dvaddr(DOLBY_CORE2A_REG_START);
+ for (i = 0; i < count; i++)
+ WRITE_VPP_REG(addr + 6 + i,
+ p_core2_dm_regs[i]);
+
+ /* core2 metadata program done */
+ WRITE_VPP_REG(DOLBY_CORE2A_Metadata_End, 1);
+
+ if (lut_count == 0)
+ count = 256 * 5;
+ else
+ count = lut_count;
+
+ WRITE_VPP_REG(DOLBY_CORE2A_DMA_CTRL, 0x1401);
+ if (lut_endian)
+ for (i = 0; i < count; i += 4) {
+ WRITE_VPP_REG(DOLBY_CORE2A_DMA_PORT,
+ p_core2_lut[i+3]);
+ WRITE_VPP_REG(DOLBY_CORE2A_DMA_PORT,
+ p_core2_lut[i+2]);
+ WRITE_VPP_REG(DOLBY_CORE2A_DMA_PORT,
+ p_core2_lut[i+1]);
+ WRITE_VPP_REG(DOLBY_CORE2A_DMA_PORT,
+ p_core2_lut[i]);
+ }
+ else
+ for (i = 0; i < count; i++)
+ WRITE_VPP_REG(DOLBY_CORE2A_DMA_PORT,
+ p_core2_lut[i]);
+
+ /* enable core2 */
+ WRITE_VPP_REG(DOLBY_CORE2A_SWAP_CTRL0, dolby_enable << 0);
+
+ if (debug_enable) {
+ printf("core2\n");
+ for (i = 0; i < 24; i++)
+ printf("%08x\n", p_core2_dm_regs[i]);
+
+ printf("core2 swap\n");
+ for (i = DOLBY_CORE2A_CLKGATE_CTRL;
+ i <= DOLBY_CORE2A_DMA_PORT; i+=4)
+ printf("[0x%4x] = 0x%x\n",
+ i, READ_VPP_REG(i));
+
+ addr = phyaddr_to_dvaddr(DOLBY_CORE2A_REG_START);
+ for (i = addr; i <= addr + 5; i++)
+ printf("[0x%4x] = 0x%x\n",
+ i, READ_VPP_REG(i));
+ }
+ return 0;
+}
+
+static int dolby_core3_set(
+ uint32_t dm_count,
+ uint32_t md_count,
+ uint32_t *p_core3_dm_regs,
+ uint32_t *p_core3_md_regs,
+ int hsize,
+ int vsize,
+ int dolby_enable,
+ int scramble_en,
+ u8 pps_state)
+{
+ uint32_t count;
+ int i;
+ int vsize_hold = 0x10;
+ uint32_t diag_mode = 0;
+ uint32_t cur_dv_mode = dolby_vision_mode;
+ uint32_t diag_enable = 0;
+
+ uint32_t htotal_add = 0x140;
+ uint32_t vtotal_add = 0x40;
+ uint32_t vsize_add = 0;
+ u32 addr = 0;
+
+ if (dovi_setting.diagnostic_enable
+ || dovi_setting.dovi_ll_enable)
+ diag_enable = 1;
+
+ if (((cur_dv_mode == DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL)
+ || (cur_dv_mode == DOLBY_VISION_OUTPUT_MODE_IPT))
+ && diag_enable) {
+ cur_dv_mode = dv_ll_output_mode & 0xff;
+
+ if (is_meson_g12() || is_meson_tm2_stbmode() || is_meson_sc2()) {
+ if (dolby_vision_ll_policy == DOLBY_VISION_LL_YUV422)
+ diag_mode = 0x20;
+ else
+ diag_mode = 3;
+ } else
+ diag_mode = 3;
+ }
+ if (is_meson_box() || is_meson_tm2_stbmode()) {
+ if (dovi_setting.dovi_ll_enable &&
+ dovi_setting.diagnostic_enable == 0) {
+ WRITE_VPP_REG_BITS(
+ VPP_DOLBY_CTRL,
+ 3, 6, 2); /* post matrix */
+ WRITE_VPP_REG_BITS(
+ VPP_MATRIX_CTRL,
+ 1, 0, 1); /* post matrix */
+ } else {
+ WRITE_VPP_REG_BITS(
+ VPP_DOLBY_CTRL,
+ 0, 6, 2); /* post matrix */
+ WRITE_VPP_REG_BITS(
+ VPP_MATRIX_CTRL,
+ 0, 0, 1); /* post matrix */
+ }
+ } else if (is_meson_txlx_stbmode()) {
+ WRITE_VPP_REG_BITS(
+ VPP_DOLBY_CTRL,
+ 1, 0, 1); /* skip pps/dither/cm */
+ WRITE_VPP_REG(
+ VPP_DAT_CONV_PARA0, 0x08000800);
+
+ if (dovi_setting.dovi_ll_enable &&
+ dovi_setting.diagnostic_enable == 0) {
+ /*bypass gainoff to vks */
+ /*enable wn tp vks*/
+ WRITE_VPP_REG_BITS(
+ VPP_DOLBY_CTRL, 0, 2, 1);
+ WRITE_VPP_REG_BITS(
+ VPP_DOLBY_CTRL, 1, 1, 1);
+ WRITE_VPP_REG(
+ VPP_DAT_CONV_PARA1, 0x8000800);
+ WRITE_VPP_REG_BITS(
+ VPP_MATRIX_CTRL,
+ 1, 0, 1); /* post matrix */
+ } else {
+ /* bypass wm tp vks*/
+ WRITE_VPP_REG_BITS(
+ VPP_DOLBY_CTRL, 1, 2, 1);
+ WRITE_VPP_REG_BITS(
+ VPP_DOLBY_CTRL, 0, 1, 1);
+ WRITE_VPP_REG(
+ VPP_DAT_CONV_PARA1, 0x20002000);
+ if (is_meson_tvmode())
+ enable_rgb_to_yuv_matrix_for_dvll(
+ 0, NULL, 12);
+ else
+ WRITE_VPP_REG_BITS(
+ VPP_MATRIX_CTRL,
+ 0, 0, 1);
+ }
+ }
+
+ /* flush post matrix table when ll mode on and setting changed */
+ if (dovi_setting.dovi_ll_enable &&
+ (dovi_setting.diagnostic_enable == 0))
+ enable_rgb_to_yuv_matrix_for_dvll(
+ 1, &p_core3_dm_regs[18], 12);
+
+ WRITE_VPP_REG(DOLBY_CORE3_CLKGATE_CTRL, 0);
+ WRITE_VPP_REG(DOLBY_CORE3_SWAP_CTRL1,
+ ((hsize + htotal_add) << 16)
+ | (vsize + vtotal_add + vsize_add + vsize_hold * 2));
+ WRITE_VPP_REG(DOLBY_CORE3_SWAP_CTRL2,
+ (hsize << 16) | (vsize + vsize_add));
+ WRITE_VPP_REG(DOLBY_CORE3_SWAP_CTRL3,
+ (0x80 << 16) | vsize_hold);
+ WRITE_VPP_REG(DOLBY_CORE3_SWAP_CTRL4,
+ (0x04 << 16) | vsize_hold);
+ WRITE_VPP_REG(DOLBY_CORE3_SWAP_CTRL5, 0x0000);
+ if (cur_dv_mode != DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL)
+ WRITE_VPP_REG(DOLBY_CORE3_SWAP_CTRL6, 0);
+ else
+ WRITE_VPP_REG(DOLBY_CORE3_SWAP_CTRL6,
+ 0x10000000); /* swap UV */
+ WRITE_VPP_REG(DOLBY_CORE3_Interrupt_Enable, 7);
+ WRITE_VPP_REG(DOLBY_CORE3_Interrupt_Raw, 4);
+ WRITE_VPP_REG(DOLBY_CORE3_Interrupt_Raw, 2);
+ WRITE_VPP_REG(DOLBY_CORE3_Metadata_Start, 1);
+ /* Control Register, address 0x04 2:0 RW */
+ /* Output_operating mode*/
+ /* 00- IPT 12 bit 444 bypass Dolby Vision output*/
+ /* 01- IPT 12 bit tunnelled over RGB 8 bit 444, dolby vision output*/
+ /* 02- HDR10 output, RGB 10 bit 444 PQ*/
+ /* 03- Deep color SDR, RGB 10 bit 444 Gamma*/
+ /* 04- SDR, RGB 8 bit 444 Gamma*/
+ WRITE_VPP_REG(DOLBY_CORE3_CTRL, cur_dv_mode);
+ WRITE_VPP_REG(DOLBY_CORE3_CTRL, cur_dv_mode);
+ /* for delay */
+
+ if (dm_count == 0)
+ count = 26;
+ else
+ count = dm_count;
+
+ addr = phyaddr_to_dvaddr(DOLBY_CORE3_REG_START);
+ for (i = 0; i < count; i++) {
+ WRITE_VPP_REG(addr + 0x6 + i,
+ p_core3_dm_regs[i]);
+ }
+ /* from addr 0x18 */
+
+ count = md_count;
+ for (i = 0; i < count; i++) {
+ WRITE_VPP_REG(addr + 0x24 + i,
+ p_core3_md_regs[i]);
+ }
+ for (; i < (128+1); i++) {
+ WRITE_VPP_REG(addr + (0x24 + i), 0);
+ }
+
+ /* from addr 0x90 */
+ /* core3 metadata program done */
+ WRITE_VPP_REG(DOLBY_CORE3_Metadata_End, 1);
+
+ WRITE_VPP_REG(DOLBY_CORE3_DIAG_CTRL, diag_mode);
+ /* enable core3 */
+ WRITE_VPP_REG(DOLBY_CORE3_SWAP_CTRL0, (dolby_enable << 0));
+
+ if (debug_enable) {
+ printf("core3\n");
+ for (i = 0; i < 26; i++)
+ printf("%08x\n", p_core3_dm_regs[i]);
+ printf("core3 swap\n");
+ for (i = DOLBY_CORE3_CLKGATE_CTRL;
+ i <= DOLBY_CORE3_OUTPUT_CSC_CRC; i+=4)
+ printf("[0x%4x] = 0x%x\n",
+ i, READ_VPP_REG(i));
+ printf("core3 real reg\n");
+ addr = phyaddr_to_dvaddr(DOLBY_CORE3_REG_START);
+ for (i = addr; i <= (addr + 67); i++)
+ printf("[0x%4x] = 0x%x\n",
+ i, READ_VPP_REG(i));
+
+ printf("core3 metadata, count %d\n",md_count);
+ for (i = 0; i < md_count; i++)
+ printf("%08x\n", p_core3_md_regs[i]);
+ }
+
+ return 0;
+}
+
+int apply_stb_core_settings(void)
+{
+ uint32_t graphics_w = 1920;
+ uint32_t graphics_h = 1080;
+
+ if (!is_dolby_enable())
+ return 0;
+ if (dovi_setting.dst_format == FORMAT_INVALID)
+ return 0;
+
+ printf("apply_stb_core_settings\n");
+ if (dovi_setting.dst_format == FORMAT_DOVI) {
+ if (dovi_setting.dovi_ll_enable) {
+ if (dovi_setting.diagnostic_enable) {
+ dolby_vision_mode = DOLBY_VISION_OUTPUT_MODE_IPT;
+ dolby_vision_ll_policy = DOLBY_VISION_LL_RGB444;
+ } else {
+ dolby_vision_mode = DOLBY_VISION_OUTPUT_MODE_IPT;
+ dolby_vision_ll_policy = DOLBY_VISION_LL_YUV422;
+ }
+ } else
+ dolby_vision_mode = DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL;
+ } else if (dovi_setting.dst_format == FORMAT_HDR10)
+ dolby_vision_mode = DOLBY_VISION_OUTPUT_MODE_HDR10;
+ else
+ dolby_vision_mode = DOLBY_VISION_OUTPUT_MODE_SDR8;
+
+ dolby_core2_set(24, 256 * 5,
+ (uint32_t *)&dovi_setting.dm_reg2,
+ (uint32_t *)&dovi_setting.dm_lut2,
+ graphics_w, graphics_h, 1, 1);
+
+ dolby_core3_set(26, dovi_setting.md_reg3.size,
+ (uint32_t *)&dovi_setting.dm_reg3,
+ dovi_setting.md_reg3.raw_metadata,
+ vinfo_width, vinfo_height, 1, 1, 0);
+ return 0;
+}
+
+static int enable_dolby_vision(void)
+{
+ printf("enable_dolby_vision\n");
+ if (is_meson_g12() || is_meson_tm2_stbmode() || is_meson_sc2()) {
+ hdr_func(OSD1_HDR, RGB_BYPASS);
+ hdr_func(OSD2_HDR, RGB_BYPASS);
+
+ /*enable core3*/
+ WRITE_VPP_REG_BITS(VPP_DOLBY_CTRL, 1, 3, 1);
+
+ /*enable core2*/
+ WRITE_VPP_REG_BITS(DOLBY_PATH_CTRL, 0, 2, 1);
+
+ /* bypass all video effect */
+ video_effect_bypass(1);
+ /* 12->10 before vadj1*/
+ /* 10->12 before post blend */
+ WRITE_VPP_REG(VPP_DAT_CONV_PARA0,
+ 0x20002000);
+ /* 12->10 before vadj2*/
+ /* 10->12 after gainoff */
+ WRITE_VPP_REG(VPP_DAT_CONV_PARA1,
+ 0x20002000);
+
+ WRITE_VPP_REG(VPP_MATRIX_CTRL, 0);
+ WRITE_VPP_REG(VPP_DUMMY_DATA1,0x80200);
+
+ if (((dolby_vision_mode ==
+ DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL)
+ || (dolby_vision_mode ==
+ DOLBY_VISION_OUTPUT_MODE_IPT)) &&
+ (dovi_setting.diagnostic_enable == 0) &&
+ dovi_setting.dovi_ll_enable) {
+ uint32_t *reg = (uint32_t *)&dovi_setting.dm_reg3;
+ /* input u12 -0x800 to s12 */
+ WRITE_VPP_REG(VPP_DAT_CONV_PARA1,
+ 0x8000800);
+ /* bypass vadj */
+ WRITE_VPP_REG(VPP_VADJ_CTRL, 0);
+ /* bypass gainoff */
+ WRITE_VPP_REG(VPP_GAINOFF_CTRL0, 0);
+ /* enable wm tp vks*/
+ /* bypass gainoff to vks */
+ WRITE_VPP_REG_BITS(VPP_DOLBY_CTRL, 1, 1, 2);
+ enable_rgb_to_yuv_matrix_for_dvll(1, ®[18],
+ (dv_ll_output_mode >> 8)& 0xff);
+ } else
+ enable_rgb_to_yuv_matrix_for_dvll(0, NULL, 12);
+
+ dolby_vision_on = true;
+ env_set("dolby_vision_on", "1");
+ run_command("saveenv", 0);
+ printk("Dolby Vision turn on\n");
+ }
+ return 0;
+}
+
+static int prepare_drm_pkt(struct master_display_info_s *data,
+ struct dovi_setting_s *setting, const struct hdmitx_dev *hdmitx_device)
+{
+ struct hdr_10_infoframe_s *p_hdr;
+ p_hdr = &(setting->hdr_info);
+
+ if (!data || !hdmitx_device || !setting)
+ return -1;
+
+ data->features = (1 << 29) | (5 << 26) | (0 << 25) | (1 << 24)
+ | (9 << 16) | (0x10 << 8) | (10 << 0);
+ data->primaries[0][0] =
+ (p_hdr->display_primaries_x_1_MSB << 8)
+ | p_hdr->display_primaries_x_1_LSB;
+ data->primaries[0][1] =
+ (p_hdr->display_primaries_y_1_MSB << 8)
+ | p_hdr->display_primaries_y_1_LSB;
+ data->primaries[1][0] =
+ (p_hdr->display_primaries_x_2_MSB << 8)
+ | p_hdr->display_primaries_x_2_LSB;
+ data->primaries[1][1] =
+ (p_hdr->display_primaries_y_2_MSB << 8)
+ | p_hdr->display_primaries_y_2_LSB;
+ data->primaries[2][0] =
+ (p_hdr->display_primaries_x_0_MSB << 8)
+ | p_hdr->display_primaries_x_0_LSB;
+ data->primaries[2][1] =
+ (p_hdr->display_primaries_y_0_MSB << 8)
+ | p_hdr->display_primaries_y_0_LSB;
+ data->white_point[0] =
+ (p_hdr->white_point_x_MSB << 8)
+ | p_hdr->white_point_x_LSB;
+ data->white_point[1] =
+ (p_hdr->white_point_y_MSB << 8)
+ | p_hdr->white_point_y_LSB;
+ data->luminance[0] =
+ (p_hdr->max_display_mastering_luminance_MSB << 8)
+ | p_hdr->max_display_mastering_luminance_LSB;
+ data->luminance[1] =
+ (p_hdr->min_display_mastering_luminance_MSB << 8)
+ | p_hdr->min_display_mastering_luminance_LSB;
+ data->max_content =
+ (p_hdr->max_content_light_level_MSB << 8)
+ | p_hdr->max_content_light_level_LSB;
+ data->max_frame_average =
+ (p_hdr->max_frame_average_light_level_MSB << 8)
+ | p_hdr->max_frame_average_light_level_LSB;
+ return 0;
+}
+
+static int prepare_vsif_pkt(struct dv_vsif_para *vsif,
+ struct dovi_setting_s *setting, const struct hdmitx_dev *hdmitx_device)
+{
+ if (!vsif || !hdmitx_device || !setting)
+ return -1;
+ vsif->vers.ver2.low_latency = setting->dovi_ll_enable;
+ vsif->vers.ver2.dobly_vision_signal = 1;
+ if (hdmitx_device->RXCap.dv_info.sup_backlight_control
+ && (setting->ext_md.available_level_mask
+ & EXT_MD_AVAIL_LEVEL_2)) {
+ vsif->vers.ver2.backlt_ctrl_MD_present = 1;
+ vsif->vers.ver2.eff_tmax_PQ_hi =
+ setting->ext_md.level_2.target_max_PQ_hi & 0xf;
+ vsif->vers.ver2.eff_tmax_PQ_low =
+ setting->ext_md.level_2.target_max_PQ_lo;
+ } else {
+ vsif->vers.ver2.backlt_ctrl_MD_present = 0;
+ vsif->vers.ver2.eff_tmax_PQ_hi = 0;
+ vsif->vers.ver2.eff_tmax_PQ_low = 0;
+ }
+
+ if (setting->dovi_ll_enable
+ && (setting->ext_md.available_level_mask
+ & EXT_MD_AVAIL_LEVEL_255)) {
+ vsif->vers.ver2.auxiliary_MD_present = 1;
+ vsif->vers.ver2.auxiliary_runmode =
+ setting->ext_md.level_255.dm_run_mode;
+ vsif->vers.ver2.auxiliary_runversion =
+ setting->ext_md.level_255.dm_run_version;
+ vsif->vers.ver2.auxiliary_debug0 =
+ setting->ext_md.level_255.dm_debug0;
+ } else {
+ vsif->vers.ver2.auxiliary_MD_present = 0;
+ vsif->vers.ver2.auxiliary_runmode = 0;
+ vsif->vers.ver2.auxiliary_runversion = 0;
+ vsif->vers.ver2.auxiliary_debug0 = 0;
+ }
+ return 0;
+}
+
+void send_hdmi_pkt(void)
+{
+ struct dv_vsif_para vsif;
+ struct master_display_info_s drmif;
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
+
+ if (!is_dolby_enable())
+ return;
+
+ printf("send_hdmi_pkt %d\n",dovi_setting.dst_format);
+
+ if (dovi_setting.dst_format == FORMAT_DOVI) {
+ memset(&vsif, 0, sizeof(vsif));
+ prepare_vsif_pkt(&vsif, &dovi_setting, hdev);
+
+ if (dovi_setting.dovi_ll_enable)
+ hdmitx_set_vsif_pkt( EOTF_T_LL_MODE,
+ dovi_setting.diagnostic_enable
+ ? RGB_10_12BIT : YUV422_BIT12,
+ &vsif);
+ else
+ hdmitx_set_vsif_pkt(EOTF_T_DOLBYVISION, RGB_8BIT,
+ &vsif);
+ } else if (dovi_setting.dst_format == FORMAT_HDR10) {
+ memset(&drmif, 0, sizeof(drmif));
+ prepare_drm_pkt(&drmif, &dovi_setting, hdev);
+#ifdef CONFIG_AML_HDMITX20
+ hdmitx_set_drm_pkt(&drmif);
+#endif
+ } else
+ return;
+}
+
+/*check hpd status:
+ *1. hdmi connected: set hdr/dv mode based on capability of TV if dv enabled.
+ *2. no hdmi: output sdr if dv enabled.
+ */
+void dolby_vision_process(void)
+{
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
+ if (!check_tv_hpd_status(hdev)) {
+ if (is_dolby_enable()) {
+ dovi_setting.dst_format = FORMAT_SDR;
+ printf("dolby_vision_process: no hpd, dst_format = SDR\n");
+ } else {
+ printf("dolby_vision_process: no tv and dv disabled\n");
+ env_set("dolby_vision_on", "0");
+ run_command("saveenv", 0);
+ return;
+ }
+ } else {
+ if (is_dolby_enable()) {
+ check_tv_support(hdev);
+ printf("dolby_vision_process: hpd: dst_format=%d\n",
+ dovi_setting.dst_format);
+ } else {
+ printf("dolby_vision_process: hpd: dv disabled\n");
+ env_set("dolby_vision_on", "0");
+ run_command("saveenv", 0);
+ return;
+ }
+ }
+ if (dovi_setting.dst_format == FORMAT_INVALID) {
+ printf("dolby_vision_process: dst_format = FORMAT_INVALID\n");
+ return;
+ }
+ dolby_vision_parse(hdev);
+ apply_stb_core_settings();
+ enable_dolby_vision();
+ /*dv send hdmi vsif after hdmi set mode*/
+ /* so we add another cmd to send this hdmi package solely*/
+}
+void dolbyvision_dump_setting() {
+ int i;
+ uint32_t *p;
+ if (!is_dolby_enable()) {
+ printf("dv is disabled\n");
+ return;
+ }
+ printf("core2\n");
+ p = (uint32_t *)&dovi_setting.dm_reg2;
+ for (i = 0; i < 24; i++)
+ printf("%08x\n", p[i]);
+ printf("core2 swap\n");
+ for (i = DOLBY_CORE2A_CLKGATE_CTRL;
+ i <= DOLBY_CORE2A_DMA_PORT; i++)
+ printf("[0x%4x] = 0x%x\n",
+ i, READ_VPP_REG(i));
+ printf("core2 real reg\n");
+ for (i = DOLBY_CORE2A_REG_START;
+ i <= DOLBY_CORE2A_REG_START + 5; i++)
+ printf("[0x%4x] = 0x%x\n",
+ i, READ_VPP_REG(i));
+
+ printf("\ncore2lut\n");
+ p = (uint32_t *)&dovi_setting.dm_lut2.TmLutI;
+ for (i = 0; i < 64; i++)
+ printf("%08x, %08x, %08x, %08x\n",
+ p[i*4+3], p[i*4+2], p[i*4+1], p[i*4]);
+ printf("\n");
+ p = (uint32_t *)&dovi_setting.dm_lut2.TmLutS;
+ for (i = 0; i < 64; i++)
+ printf("%08x, %08x, %08x, %08x\n",
+ p[i*4+3], p[i*4+2], p[i*4+1], p[i*4]);
+ printf("\n");
+ p = (uint32_t *)&dovi_setting.dm_lut2.SmLutI;
+ for (i = 0; i < 64; i++)
+ printf("%08x, %08x, %08x, %08x\n",
+ p[i*4+3], p[i*4+2], p[i*4+1], p[i*4]);
+ printf("\n");
+ p = (uint32_t *)&dovi_setting.dm_lut2.SmLutS;
+ for (i = 0; i < 64; i++)
+ printf("%08x, %08x, %08x, %08x\n",
+ p[i*4+3], p[i*4+2], p[i*4+1], p[i*4]);
+ printf("\n");
+ p = (uint32_t *)&dovi_setting.dm_lut2.G2L;
+ for (i = 0; i < 64; i++)
+ printf("%08x, %08x, %08x, %08x\n",
+ p[i*4+3], p[i*4+2], p[i*4+1], p[i*4]);
+ printf("\n");
+
+ printf("core3\n");
+ p = (uint32_t *)&dovi_setting.dm_reg3;
+ for (i = 0; i < 26; i++)
+ printf("%08x\n", p[i]);
+ printf("core3 swap\n");
+ for (i = DOLBY_CORE3_CLKGATE_CTRL;
+ i <= DOLBY_CORE3_CLKGATE_CTRL + 13; i++)
+ printf("[0x%4x] = 0x%x\n",
+ i, READ_VPP_REG(i));
+ printf("core3 real reg\n");
+ for (i = DOLBY_CORE3_REG_START;
+ i <= DOLBY_CORE3_REG_START + 67; i++)
+ printf("[0x%4x] = 0x%x\n",
+ i, READ_VPP_REG(i));
+
+ if (dolby_vision_mode <= DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL) {
+ printf("\ncore3_meta %d\n", dovi_setting.md_reg3.size);
+ p = dovi_setting.md_reg3.raw_metadata;
+ for (i = 0; i < dovi_setting.md_reg3.size; i++)
+ printf("%08x\n", p[i]);
+ printf("\n");
+ }
+
+}
+void dolbyvision_debug(int enable_debug) {
+ debug_enable = enable_debug;
+}
diff --git a/drivers/amlogic/media/osd/hdr2.h b/drivers/amlogic/media/osd/hdr2.h
new file mode 100644
index 0000000..6e16463
--- /dev/null
+++ b/drivers/amlogic/media/osd/hdr2.h
@@ -0,0 +1,39 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __HDR2_H__
+#define __HDR2_H__
+
+enum hdr_module_sel {
+ VD1_HDR = 0x1,
+ VD2_HDR = 0x2,
+ VD3_HDR = 0x2,
+ OSD1_HDR = 0x4,
+ OSD2_HDR = 0x5,
+ VDIN0_HDR = 0x8,
+ VDIN1_HDR = 0x10,
+ DI_HDR = 0x20,
+ OSD3_HDR = 0x40,
+ HDR_MAX
+};
+
+enum hdr_process_sel {
+ HDR_BYPASS = 0x1,
+ HDR_SDR = 0x2,
+ SDR_HDR = 0x4,
+ HLG_BYPASS = 0x8,
+ HLG_SDR = 0x10,
+ HLG_HDR = 0x20,
+ SDR_HLG = 0X40,
+ HDRPLUS_SDR = 0x80,
+ HDR_OFF = 0x100,
+ RGB_BYPASS = 0x200,
+ HDR_p_MAX
+};
+
+extern void hdr_func(enum hdr_module_sel module_sel,
+ enum hdr_process_sel hdr_process_select);
+
+#endif
diff --git a/drivers/amlogic/media/osd/osd.h b/drivers/amlogic/media/osd/osd.h
index 4f0bbc2..f7f86b1 100644
--- a/drivers/amlogic/media/osd/osd.h
+++ b/drivers/amlogic/media/osd/osd.h
@@ -1,21 +1,7 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/osd/osd.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * Author: Platform-BJ @platform.bj@amlogic.com
- *
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _OSD_H_
#define _OSD_H_
@@ -56,7 +42,7 @@
#define KEYCOLOR_FLAG_ONHOLD 2
#define KEYCOLOR_FLAG_CURRENT 4
-#define HW_OSD_COUNT 2
+#define HW_OSD_COUNT 3
/* OSD block definition */
#define HW_OSD_BLOCK_COUNT 4
#define HW_OSD_BLOCK_REG_COUNT (HW_OSD_BLOCK_COUNT*2)
@@ -86,11 +72,6 @@
#define OSD_MAX_BUF_NUM 3 /* fence relative */
-enum osd_index_e {
- OSD1 = 0,
- OSD2
-};
-
enum osd_enable_e {
DISABLE = 0,
ENABLE
@@ -270,6 +251,8 @@
u32 clone[HW_OSD_COUNT];
u32 bot_type;
u32 osd_ver;
+ u32 shift_line;
+ u32 mif_linear;
};
#endif /* _OSD_H_ */
diff --git a/drivers/amlogic/media/osd/osd_canvas.h b/drivers/amlogic/media/osd/osd_canvas.h
index 97f124e..78371a1 100644
--- a/drivers/amlogic/media/osd/osd_canvas.h
+++ b/drivers/amlogic/media/osd/osd_canvas.h
@@ -1,20 +1,7 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/osd/osd_canvas.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
-*/
-
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _OSD_CANVAS_H_
#define _OSD_CANVAS_H_
@@ -22,7 +9,7 @@
#define OSD1_CANVAS_INDEX 0x40
#define OSD2_CANVAS_INDEX 0x43
#define OSD3_CANVAS_INDEX 0x41
-#define OSD4_CANVAS_INDEX 0x42
+#define OSD4_CANVAS_INDEX 0x47
#define ALLOC_CANVAS_INDEX 0x44
#endif
diff --git a/drivers/amlogic/media/osd/osd_debug.c b/drivers/amlogic/media/osd/osd_debug.c
index e8593f3..ae74e24 100644
--- a/drivers/amlogic/media/osd/osd_debug.c
+++ b/drivers/amlogic/media/osd/osd_debug.c
@@ -1,26 +1,14 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/osd/osd_hw.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
/* System Headers */
#include <config.h>
#include <common.h>
#include <malloc.h>
#include <asm/arch/io.h>
-#include <asm/arch/cpu_id.h>
+#include <amlogic/cpu_id.h>
#include <asm/arch/cpu.h>
/* Local Headers */
@@ -199,6 +187,26 @@
reg = VIU_OSD2_BLK0_CFG_W4;
osd_logi("reg[0x%x]: 0x%08x\n\n", reg, osd_reg_read(reg));
}
+
+#ifdef CONFIG_AML_MESON_G12A
+ /* for viu2_osd */
+ if (!strcmp(env_get("display_layer"), "viu2_osd0")) {
+ reg = VIU2_OSD1_FIFO_CTRL_STAT;
+ osd_logi("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
+ reg = VIU2_OSD1_CTRL_STAT;
+ osd_logi("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
+ reg = VIU2_OSD1_BLK0_CFG_W0;
+ osd_logi("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
+ reg = VIU2_OSD1_BLK0_CFG_W1;
+ osd_logi("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
+ reg = VIU2_OSD1_BLK0_CFG_W2;
+ osd_logi("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
+ reg = VIU2_OSD1_BLK0_CFG_W3;
+ osd_logi("reg[0x%x]: 0x%08x\n", reg, osd_reg_read(reg));
+ reg = VIU2_OSD1_BLK0_CFG_W4;
+ osd_logi("reg[0x%x]: 0x%08x\n\n", reg, osd_reg_read(reg));
+ }
+#endif
}
static void osd_test_colorbar(void)
diff --git a/drivers/amlogic/media/osd/osd_fb.c b/drivers/amlogic/media/osd/osd_fb.c
index 8927edc..8902aef 100644
--- a/drivers/amlogic/media/osd/osd_fb.c
+++ b/drivers/amlogic/media/osd/osd_fb.c
@@ -1,19 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/osd/osd_fb.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
/* System Headers */
#include <common.h>
@@ -21,7 +9,7 @@
#include <stdio_dev.h>
#include <malloc.h>
#include <bmp_layout.h>
-#include <asm/arch/cpu_id.h>
+#include <amlogic/cpu_id.h>
#include <asm/arch/cpu.h>
#include <asm/arch/timer.h>
@@ -178,7 +166,9 @@
}pic_info_t;
static pic_info_t g_pic_info;
static int img_video_init = 0;
-static int fb_index = -1;
+#if defined(CONFIG_AML_MINUI)
+extern int in_fastboot_mode;
+#endif
static void osd_layer_init(GraphicDevice *gdev, int layer)
@@ -198,20 +188,26 @@
const struct color_bit_define_s *color =
&default_color_format_array[gdev->gdfIndex];
-#ifdef OSD_SCALE_ENABLE
- xres = gdev->fb_width;
- yres = gdev->fb_height;
- xres_virtual = gdev->fb_width;
- yres_virtual = gdev->fb_height * 2;
- disp_end_x = gdev->fb_width - 1;
- disp_end_y = gdev->fb_height - 1;
-#else
- xres = gdev->winSizeX;
- yres = gdev->winSizeY;
- xres_virtual = gdev->winSizeX;
- yres_virtual = gdev->winSizeY * 2;
- disp_end_x = gdev->winSizeX - 1;
- disp_end_y = gdev->winSizeY - 1;
+ if (index >= VIU2_OSD1) {
+ xres = gdev->winSizeX;
+ yres = gdev->winSizeY;
+ xres_virtual = gdev->winSizeX;
+ yres_virtual = gdev->winSizeY * 2;
+ disp_end_x = gdev->winSizeX - 1;
+ disp_end_y = gdev->winSizeY - 1;
+ } else {
+ xres = gdev->fb_width;
+ yres = gdev->fb_height;
+ xres_virtual = gdev->fb_width;
+ yres_virtual = gdev->fb_height * 2;
+ disp_end_x = gdev->fb_width - 1;
+ disp_end_y = gdev->fb_height - 1;
+ }
+
+#ifdef AML_OSD_HIGH_VERSION
+ if (index >= VIU2_OSD1)
+ osd_init_hw_viu2();
+ else
#endif
osd_init_hw();
osd_setup_hw(index,
@@ -276,35 +272,73 @@
unsigned long get_fb_addr(void)
{
+ char *dt_addr = NULL;
unsigned long fb_addr = 0;
static int initrd_set = 0;
char str_fb_addr[32];
-#ifdef CONFIG_OF_LIBFDT
- const void *dt_addr = NULL;
char fdt_node[32];
+ int dt_loaded = 0;
+#ifdef CONFIG_OF_LIBFDT
int parent_offset = 0;
char *propdata = NULL;
#endif
fb_addr = env_strtoul("fb_addr", 16);
-
#ifdef CONFIG_OF_LIBFDT
- dt_addr = gd->fdt_blob;
- if ((dt_addr == NULL) || (fdt_check_header(dt_addr) < 0)) {
- osd_logi("check dts: %s, load default fb_addr parameters\n",
- fdt_strerror(fdt_check_header(dt_addr)));
- } else {
- strcpy(fdt_node, "/meson-fb");
- osd_logi("load fb addr from dts:%s\n", fdt_node);
- parent_offset = get_dts_node(dt_addr, fdt_node);
- if (parent_offset < 0) {
- strcpy(fdt_node, "/drm-vpu");
+#if defined(CONFIG_AML_MINUI)
+ if (in_fastboot_mode == 1) {
+ osd_logi("in fastboot mode, load default fb_addr parameters \n");
+ } else
+#endif
+ {
+ dt_addr = (char *) env_get_ulong("dtb_mem_addr", 16, 0x1000000);
+ if (dt_addr == NULL) {
+ osd_logi("dt_addr is null, load default parameters\n");
+ }
+ if (fdt_check_header(dt_addr) < 0) {
+ dt_addr = (char *)gd->fdt_blob;
+ if (fdt_check_header(dt_addr) < 0) {
+ dt_loaded = -1;
+ osd_logi("check dts: %s, load default fb_addr parameters\n",
+ fdt_strerror(fdt_check_header(dt_addr)));
+ }
+ }
+ if (dt_loaded < 0) {
+ osd_logi("check dts: %s, load default fb_addr parameters\n",
+ fdt_strerror(fdt_check_header(dt_addr)));
+ } else {
+ strcpy(fdt_node, "/fb");
osd_logi("load fb addr from dts:%s\n", fdt_node);
parent_offset = get_dts_node(dt_addr, fdt_node);
if (parent_offset < 0) {
- osd_logi("not find node: %s\n",fdt_strerror(parent_offset));
- osd_logi("use default fb_addr parameters\n");
+ if (parent_offset < 0) {
+ strcpy(fdt_node, "/drm-vpu");
+ osd_logi("load fb addr from dts:%s\n", fdt_node);
+ parent_offset = get_dts_node(dt_addr, fdt_node);
+ if (parent_offset < 0) {
+ osd_logi("not find node: %s\n",fdt_strerror(parent_offset));
+ osd_logi("use default fb_addr parameters\n");
+ } else {
+ /* check fb_addr */
+ propdata = (char *)fdt_getprop(dt_addr, parent_offset, "logo_addr", NULL);
+ if (propdata == NULL) {
+ osd_logi("failed to get fb addr for logo\n");
+ osd_logi("use default fb_addr parameters\n");
+ } else {
+ fb_addr = simple_strtoul(propdata, NULL, 16);
+ }
+ }
+ } else {
+ /* check fb_addr */
+ propdata = (char *)fdt_getprop(dt_addr, parent_offset, "logo_addr", NULL);
+ if (propdata == NULL) {
+ osd_logi("failed to get fb addr for logo\n");
+ osd_logi("use default fb_addr parameters\n");
+ } else {
+ fb_addr = simple_strtoul(propdata, NULL, 16);
+ }
+ }
} else {
/* check fb_addr */
propdata = (char *)fdt_getprop(dt_addr, parent_offset, "logo_addr", NULL);
@@ -315,19 +349,11 @@
fb_addr = simple_strtoul(propdata, NULL, 16);
}
}
- } else {
- /* check fb_addr */
- propdata = (char *)fdt_getprop(dt_addr, parent_offset, "logo_addr", NULL);
- if (propdata == NULL) {
- osd_logi("failed to get fb addr for logo\n");
- osd_logi("use default fb_addr parameters\n");
- } else {
- fb_addr = simple_strtoul(propdata, NULL, 16);
- }
}
}
#endif
- if ((!initrd_set) && (get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_AXG)) {
+
+ if ((!initrd_set) && (osd_get_chip_type() >= MESON_CPU_MAJOR_ID_AXG)) {
sprintf(str_fb_addr,"%lx",fb_addr);
env_set("initrd_high", str_fb_addr);
initrd_set = 1;
@@ -340,7 +366,7 @@
static void get_osd_version(void)
{
- u32 family_id = get_cpu_id().family_id;
+ u32 family_id = osd_get_chip_type();
if (family_id == MESON_CPU_MAJOR_ID_AXG)
osd_hw.osd_ver = OSD_SIMPLE;
@@ -350,21 +376,34 @@
osd_hw.osd_ver = OSD_HIGH_ONE;
}
-static int get_osd_layer(void)
+int get_osd_layer(void)
{
char *layer_str;
int osd_index = -1;
- if (fb_index < 0) {
- layer_str = env_get("display_layer");
- if (strcmp(layer_str, "osd0") == 0)
- osd_index = OSD1;
- else if (strcmp(layer_str, "osd1") == 0)
- osd_index = OSD2;
- fb_index = osd_index;
- }
- return fb_index;
+ layer_str = env_get("display_layer");
+ if (strcmp(layer_str, "osd0") == 0)
+ osd_index = OSD1;
+ else if (strcmp(layer_str, "osd1") == 0)
+ osd_index = OSD2;
+ else if (strcmp(layer_str, "viu2_osd0") == 0)
+ osd_index = VIU2_OSD1;
+ else
+ osd_loge("%s, error found\n", __func__);
+
+ return osd_index;
}
+
+static bool is_osd_supported(int chip_id)
+{
+ if ((chip_id == MESON_CPU_MAJOR_ID_A1) ||
+ (chip_id == MESON_CPU_MAJOR_ID_C1) ||
+ (chip_id == MESON_CPU_MAJOR_ID_C2))
+ return false;
+ else
+ return true;
+}
+
static void *osd_hw_init(void)
{
int osd_index = -1;
@@ -394,8 +433,13 @@
return NULL;
}
osd_layer_init(&fb_gdev, OSD2);
- }
- else {
+ } else if (osd_index == VIU2_OSD1) {
+ if (osd_hw.osd_ver == OSD_SIMPLE) {
+ osd_loge("AXG not support viu2 osd0\n");
+ return NULL;
+ }
+ osd_layer_init(&fb_gdev, VIU2_OSD1);
+ } else {
osd_loge("display_layer(%d) invalid\n", osd_index);
return NULL;
}
@@ -411,10 +455,14 @@
u32 fg = 0;
u32 bg = 0;
u32 fb_width = 0;
- u32 fb_height = 0;;
+ u32 fb_height = 0;
+ if (!is_osd_supported(osd_get_chip_type()))
+ return NULL;
get_osd_version();
+#ifdef CONFIG_AML_VOUT
vout_init();
+#endif
fb_addr = get_fb_addr();
switch (display_mode) {
case MIDDLE_MODE:
@@ -566,18 +614,14 @@
uchar *fb;
bmp_image_t *bmp = (bmp_image_t *)bmp_image;
uchar *bmap;
- ushort padded_line;
unsigned long width, height;
-#ifdef OSD_SCALE_ENABLE
- unsigned long pheight = fb_gdev.fb_height;
- unsigned long pwidth = fb_gdev.fb_width;
-#else
- unsigned long pheight = info->width;
- unsigned long pwidth = info->height;
-#endif
+ unsigned long pheight;
+ unsigned long pwidth;
unsigned colors, bpix, bmp_bpix;
- int lcd_line_length = (pwidth * NBITS(info->vl_bpix)) / 8;
+ uint lcd_line_length;
int osd_index = -1;
+ int bmp_line_bytes;
+ int bmp_line_align_offset;
osd_index = get_osd_layer();
if (osd_index < 0) {
@@ -585,6 +629,16 @@
return (-1);
}
+ /* viu1 has scaler, viu2 has no scaler */
+ if (osd_index >= VIU2_OSD1) {
+ pwidth = info->width;
+ pheight = info->height;
+ } else {
+ pheight = fb_gdev.fb_height;
+ pwidth = fb_gdev.fb_width;
+ }
+
+ lcd_line_length = CANVAS_ALIGNED((pwidth * NBITS(info->vl_bpix)) / 8);
if (fb_gdev.mode != FULL_SCREEN_MODE)
if (parse_bmp_info(bmp_image))
return -1;
@@ -649,21 +703,24 @@
* their own ways, so make the converting to be MCC200
* specific.
*/
- padded_line = (width & 0x3) ? ((width & ~0x3) + 4) : (width);
+ bmp_line_bytes = width * bmp_bpix / 8;
+ bmp_line_bytes = (bmp_line_bytes & 0x3) ?
+ ((bmp_line_bytes & ~0x3) + 4) : (bmp_line_bytes);
+
+ bmp_line_align_offset = bmp_line_bytes - width * bmp_bpix / 8;
if ((x + width) > pwidth)
width = pwidth - x;
if ((y + height) > pheight)
height = pheight - y;
- osd_enable_hw(osd_index, 1);
-
bmap = (uchar *)bmp + le32_to_cpu(bmp->header.data_offset);
- fb = (uchar *)(info->vd_base +
+ fb = (uchar *)(osd_hw.fb_gem[osd_index].addr +
(y + height - 1) * lcd_line_length + x * fb_gdev.gdfBytesPP);
- osd_logd("fb=0x%p; bmap=0x%p, width=%ld, height= %ld, lcd_line_length=%d, padded_line=%d, fb_gdev.fb_width=%d, fb_gdev.fb_height=%d \n",
- fb, bmap, width, height, lcd_line_length, padded_line,fb_gdev.fb_width,fb_gdev.fb_height);
+ osd_logd("fb=0x%p; bmap=0x%p, width=%ld, height= %ld, lcd_line_length=%d, bmp_line_bytes=%d, fb_gdev.fb_width=%d, fb_gdev.fb_height=%d \n",
+ fb, bmap, width, height, lcd_line_length, bmp_line_bytes,
+ fb_gdev.fb_width, fb_gdev.fb_height);
if (bmp_bpix == 8) {
/* decode of RLE8 */
@@ -700,7 +757,7 @@
}
*/
}
- buffer_rgb += (padded_line - width);
+ buffer_rgb += bmp_line_align_offset;
fb -= (byte_width * 4 + lcd_line_length);
}
buffer_rgb -= width*height*4;
@@ -713,7 +770,7 @@
*(fb++) = *(bmap++);
*(fb++) = *(bmap++);
}
- bmap += (padded_line - width) * 2;
+ bmap += bmp_line_align_offset;
fb -= (width * 2 + lcd_line_length);
}
break;
@@ -727,7 +784,7 @@
*(fb++) = *(bmap++);
*(fb++) = 0xff;
}
- bmap += (padded_line - width);
+ bmap += bmp_line_align_offset;
fb -= (width * 4 + lcd_line_length);
}
} else {
@@ -738,7 +795,7 @@
*(fb++) = *(bmap++);
*(fb++) = *(bmap++);
}
- bmap += (padded_line - width);
+ bmap += bmp_line_align_offset;
fb -= (width * 3 + lcd_line_length);
}
}
@@ -752,7 +809,7 @@
*(fb++) = *(bmap++);
*(fb++) = *(bmap++);
}
- bmap += (padded_line - width);
+ bmap += bmp_line_align_offset;
fb -= (width * 4 + lcd_line_length);
}
break;
@@ -763,8 +820,8 @@
buffer_rgb = NULL;
ptr_rgb = NULL;
- flush_cache((unsigned long)info->vd_base,
- pheight * pwidth * info->vl_bpix / 8);
+ flush_cache((unsigned long)osd_hw.fb_gem[osd_index].addr,
+ pheight * CANVAS_ALIGNED(pwidth * info->vl_bpix / 8));
return (0);
}
@@ -947,16 +1004,20 @@
osd_logd2("video_scale_bitmap src w=%d, h=%d, dst w=%d, dst h=%d\n",
fb_gdev.fb_width, fb_gdev.fb_height, fb_gdev.winSizeX, fb_gdev.winSizeY);
- layer_str = env_get("display_layer");
vout_get_current_axis(axis);
+ layer_str = env_get("display_layer");
if (strcmp(layer_str, "osd0") == 0)
- osd_index = 0;
+ osd_index = OSD1;
else if (strcmp(layer_str, "osd1") == 0)
- osd_index = 1;
- else {
+ osd_index = OSD2;
+ else if (strcmp(layer_str, "viu2_osd0") == 0) {
+ osd_index = VIU2_OSD1;
+ goto no_scale;
+ } else {
osd_logd2("video_scale_bitmap: invalid display_layer\n");
return (-1);
}
+
#ifdef OSD_SUPERSCALE_ENABLE
if ((fb_gdev.fb_width * 2 != fb_gdev.winSizeX) ||
(fb_gdev.fb_height * 2 != fb_gdev.winSizeY)) {
@@ -972,12 +1033,14 @@
osd_set_window_axis_hw(osd_index, axis[0], axis[1], axis[0] + axis[2] - 1,
axis[1] + axis[3] - 1);
osd_set_free_scale_enable_hw(osd_index, 0x10001);
+
+no_scale:
#ifdef AML_OSD_HIGH_VERSION
disp_data.x_start = axis[0];
disp_data.y_start = axis[1];
disp_data.x_end = axis[0] + axis[2] - 1;
disp_data.y_end = axis[1] + axis[3] - 1;
- if (osd_hw.osd_ver == OSD_HIGH_ONE)
+ if (osd_hw.osd_ver == OSD_HIGH_ONE && osd_index < VIU2_OSD1)
osd_update_blend(&disp_data);
#endif
osd_enable_hw(osd_index, 1);
@@ -1142,11 +1205,12 @@
u32 fg = 0;
u32 bg = 0;
u32 fb_width = 0;
- u32 fb_height = 0;;
+ u32 fb_height = 0;
get_osd_version();
-
+#ifdef CONFIG_AML_VOUT
vout_init();
+#endif
fb_addr = get_fb_addr();
#ifdef OSD_SCALE_ENABLE
fb_width = env_strtoul("fb_width", 10);
@@ -1200,10 +1264,6 @@
return 0;
}
-
-
-
-
static int video_display_osd(u32 osd_index)
{
struct vinfo_s *info = NULL;
@@ -1255,7 +1315,7 @@
void hist_set_golden_data(void)
{
u32 i = 0;
- u32 family_id = get_cpu_id().family_id;
+ u32 family_id = osd_get_chip_type();
char *str = NULL;
char *hist_env_key[12] = {"hist_max_min_osd0","hist_spl_val_osd0","hist_spl_pix_cnt_osd0","hist_cheoma_sum_osd0",
"hist_max_min_osd1","hist_spl_val_osd1","hist_spl_pix_cnt_osd1","hist_cheoma_sum_osd1",
@@ -1295,7 +1355,19 @@
hist_cheoma_sum[OSD1][MESON_CPU_MAJOR_ID_G12A]
= hist_cheoma_sum[OSD2][MESON_CPU_MAJOR_ID_G12A]
= 0xd4ffdc;
-
+ //SC2
+ hist_max_min[OSD1][MESON_CPU_MAJOR_ID_SC2]
+ = hist_max_min[OSD2][MESON_CPU_MAJOR_ID_SC2]
+ = 0xf700;
+ hist_spl_val[OSD1][MESON_CPU_MAJOR_ID_SC2]
+ = hist_spl_val[OSD2][MESON_CPU_MAJOR_ID_SC2]
+ = 0x1e873c00;
+ hist_spl_pix_cnt[OSD1][MESON_CPU_MAJOR_ID_SC2]
+ = hist_spl_pix_cnt[OSD2][MESON_CPU_MAJOR_ID_SC2]
+ = 0x1fa409;
+ hist_cheoma_sum[OSD1][MESON_CPU_MAJOR_ID_SC2]
+ = hist_cheoma_sum[OSD2][MESON_CPU_MAJOR_ID_SC2]
+ = 0xfd20480;
for (i = 0; i < 12; i++) {
str = env_get(hist_env_key[i]);
if (str) {
@@ -1321,8 +1393,9 @@
{
u32 i = osd_index, osd_max = 1;
u32 hist_result[4];
- u32 family_id = get_cpu_id().family_id;
+ u32 family_id = osd_get_chip_type();
+ get_osd_version();
if (osd_hw.osd_ver == OSD_SIMPLE) {
osd_max = 0;
} else if (osd_hw.osd_ver == OSD_HIGH_ONE) {
diff --git a/drivers/amlogic/media/osd/osd_fb.h b/drivers/amlogic/media/osd/osd_fb.h
index 4e950e9..43aafe6 100644
--- a/drivers/amlogic/media/osd/osd_fb.h
+++ b/drivers/amlogic/media/osd/osd_fb.h
@@ -1,23 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/osd/osd_fb.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _OSD_FB_H_
#define _OSD_FB_H_
+int get_osd_layer(void);
void img_mode_set(u32 display_mode);
void img_addr_set(ulong pic_image);
void img_type_set(u32 type);
diff --git a/drivers/amlogic/media/osd/osd_hw.c b/drivers/amlogic/media/osd/osd_hw.c
index 06596ce..7d9b182 100644
--- a/drivers/amlogic/media/osd/osd_hw.c
+++ b/drivers/amlogic/media/osd/osd_hw.c
@@ -1,27 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/osd/osd_hw.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
-*/
-
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
/* System Headers */
#include <config.h>
#include <common.h>
#include <asm/arch/io.h>
-#include <asm/arch/cpu_id.h>
+#include <amlogic/cpu_id.h>
#include <asm/arch/cpu.h>
+#include <asm/arch/timer.h>
/* Local Headers */
#include <amlogic/media/vout/aml_vmode.h>
@@ -31,6 +19,8 @@
#ifdef CONFIG_AML_VOUT
#include <amlogic/media/vout/aml_vout.h>
#endif
+#include <amlogic/fb.h>
+#include <video_fb.h>
/* Local Headers */
#include "osd_canvas.h"
@@ -38,8 +28,9 @@
#include "osd_io.h"
#include "osd_hw.h"
#include "osd_hw_def.h"
-
+#include "osd_fb.h"
#include "vpp.h"
+#include <amlogic/media/dv/dolby_vision.h>
static bool vsync_hit;
static bool osd_vf_need_update;
@@ -64,6 +55,7 @@
static unsigned int osd_h_filter_mode = 1;
static unsigned int osd_v_filter_mode = 1;
+extern GraphicDevice fb_gdev;
static unsigned int osd_filter_coefs_bicubic_sharp[] = {
0x01fa008c, 0x01fa0100, 0xff7f0200, 0xfe7f0300,
@@ -184,17 +176,31 @@
#define OSD_TYPE_TOP_FIELD 0
#define OSD_TYPE_BOT_FIELD 1
+int osd_get_chip_type(void)
+{
+ unsigned int cpu_type;
+
+ cpu_type = get_cpu_id().family_id;
+ return cpu_type;
+}
+
static void osd_vpu_power_on(void)
{
}
-
-static void osd_super_scale_mem_power_on(void)
+#ifndef AML_T7_DISPLAY
+#ifdef AML_OSD_HIGH_VERSION
+static void osd_vpu_power_on_viu2(void)
{
}
+#endif
+#endif
+// static void osd_super_scale_mem_power_on(void)
+// {
+// }
-static void osd_super_scale_mem_power_off(void)
-{
-}
+// static void osd_super_scale_mem_power_off(void)
+// {
+// }
void osd_set_log_level(int level)
{
@@ -235,25 +241,151 @@
#endif
-static inline void osd_update_3d_mode(int enable_osd1, int enable_osd2)
+static inline void osd_update_3d_mode(int enable_osd1, int enable_osd2,
+ int enable_viu2_osd1)
{
if (enable_osd1)
osd1_update_disp_3d_mode();
if (enable_osd2)
osd2_update_disp_3d_mode();
+ if (enable_viu2_osd1)
+ viu2_osd1_update_disp_3d_mode();
+}
+
+#if 1
+static void get_encp_line(int *enc_line, int *active_line_begin)
+{
+ unsigned int reg = 0;
+ unsigned int viu_sel;
+ int osd_index;
+
+ osd_index = get_osd_layer();
+ if (osd_index < VIU2_OSD1)
+ viu_sel = osd_reg_read(VPU_VIU_VENC_MUX_CTRL) & 0x3;
+ else
+ viu_sel = (osd_reg_read(VPU_VIU_VENC_MUX_CTRL) >> 2) & 0x3;
+
+ switch (viu_sel) {
+ case 0:
+ reg = osd_reg_read(ENCL_INFO_READ);
+ *active_line_begin =
+ osd_reg_read(ENCL_VIDEO_VAVON_BLINE);
+
+ break;
+ case 1:
+ reg = osd_reg_read(ENCI_INFO_READ);
+ *active_line_begin =
+ osd_reg_read(ENCI_VFIFO2VD_LINE_TOP_START);
+ break;
+ case 2:
+ reg = osd_reg_read(ENCP_INFO_READ);
+ *active_line_begin =
+ osd_reg_read(ENCP_VIDEO_VAVON_BLINE);
+ break;
+ case 3:
+ reg = osd_reg_read(ENCT_INFO_READ);
+ *active_line_begin =
+ osd_reg_read(ENCT_VIDEO_VAVON_BLINE);
+ break;
+ }
+ *enc_line = (reg >> 16) & 0x1fff;
+ *enc_line -= (*active_line_begin);
}
static inline void wait_vsync_wakeup(void)
{
+ int i = 0;
+ int enc_line = 0;
+ int active_line_begin;
+ int vsync_line = 0;
+ struct vinfo_s *info = NULL;
+ int line_after = 0;
+
+#ifdef CONFIG_AML_VOUT
+ info = vout_get_current_vinfo();
+ vsync_line = info->field_height;
+#endif
+
+ get_encp_line(&enc_line, &active_line_begin);
+
+ /* if current line is always zero */
+ if (enc_line == (0 - active_line_begin)) {
+ _udelay(50);
+ get_encp_line(&line_after, &active_line_begin);
+ if (enc_line == (0 - active_line_begin))
+ goto vsync_hit_flag;
+ }
+
+ while (enc_line < vsync_line) {
+ if (i > 100000) {
+ osd_logi("wait_vsync_wakeup exit\n");
+ break;
+ }
+ i++;
+ get_encp_line(&enc_line, &active_line_begin);
+ }
+
+vsync_hit_flag:
vsync_hit = true;
}
+#else
+
+static int get_encp_line(int *enc_line)
+{
+ int vsync_get = 0;
+ unsigned int reg = 0;
+ int field_status = 0;
+ static int pre_field_status = 0;
+
+ switch (osd_reg_read(VPU_VIU_VENC_MUX_CTRL) & 0x3) {
+ case 0:
+ reg = osd_reg_read(ENCL_INFO_READ);
+ break;
+ case 1:
+ reg = osd_reg_read(ENCI_INFO_READ);
+ break;
+ case 2:
+ reg = osd_reg_read(ENCP_INFO_READ);
+ break;
+ case 3:
+ reg = osd_reg_read(ENCT_INFO_READ);
+ break;
+ }
+ *enc_line = (reg >> 16) & 0x1fff;
+ field_status = (reg >> 29) & 0x7;
+ if (field_status != pre_field_status)
+ vsync_get = 1;
+ pre_field_status = field_status;
+ return vsync_get;
+}
+
+static inline void wait_vsync_wakeup(void)
+{
+ int i = 0;
+ int line = 0;
+ int vsync_get = 0;
+
+ vsync_get = get_encp_line(&line);
+ if ((line > 0) || vsync_get) {
+ while (!vsync_get) {
+ if (i>100000) {
+ osd_logi("wait_vsync_wakeup exit, i=%d\n", i);
+ break;
+ }
+ i++;
+ vsync_get = get_encp_line(&line);
+ }
+ }
+ vsync_hit = true;
+}
+#endif
static inline void walk_through_update_list(void)
{
u32 i, j;
for (i = 0; i < HW_OSD_COUNT; i++) {
j = 0;
- while (osd_hw.updated[i] && j < 32) {
+ while (osd_hw.updated[i] && j < HW_REG_INDEX_MAX) {
if (osd_hw.updated[i] & (1 << j)) {
osd_hw.reg[i][j].update_func();
remove_from_update_list(i, j);
@@ -334,17 +466,18 @@
osd_reg_write(VIU_OSD2_BLK0_CFG_W0, fb1_cfg_w0);
}
/* go through update list */
- walk_through_update_list();
- osd_update_3d_mode(osd_hw.mode_3d[OSD1].enable,
- osd_hw.mode_3d[OSD2].enable);
-
if (!vsync_hit)
wait_vsync_wakeup();
+
+ walk_through_update_list();
+ osd_update_3d_mode(osd_hw.mode_3d[OSD1].enable,
+ osd_hw.mode_3d[OSD2].enable,
+ osd_hw.mode_3d[VIU2_OSD1].enable);
}
void osd_wait_vsync_hw(void)
{
- mdelay(5);
+ //mdelay(16);
vsync_isr();
vsync_hit = false;
}
@@ -525,7 +658,7 @@
struct pandata_s disp_data;
struct pandata_s pan_data;
- if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_M8) {
+ if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_M8) {
if (index == OSD2)
return;
}
@@ -548,33 +681,33 @@
osd_wait_vsync_hw();
}
-
/* the return stride unit is 128bit(16bytes) */
-static u32 line_stride_calc(
- u32 fmt_mode,
- u32 hsize,
- u32 stride_align_32bytes)
+static u32 line_stride_calc(u32 fmt_mode,
+ u32 hsize,
+ u32 stride_align_32bytes)
{
u32 line_stride = 0;
+ u32 line_stride_32bytes;
+ u32 line_stride_64bytes;
switch (fmt_mode) {
- /* 2-bit LUT */
+ /* 2-bit LUT */
case COLOR_INDEX_02_PAL4:
- line_stride = ((hsize<<1)+127)>>7;
+ line_stride = ((hsize << 1) + 127) >> 7;
break;
/* 4-bit LUT */
case COLOR_INDEX_04_PAL16:
- line_stride = ((hsize<<2)+127)>>7;
+ line_stride = ((hsize << 2) + 127) >> 7;
break;
- /* 8-bit LUT */
+ /* 8-bit LUT */
case COLOR_INDEX_08_PAL256:
- line_stride = ((hsize<<3)+127)>>7;
+ line_stride = ((hsize << 3) + 127) >> 7;
break;
- /* 4:2:2, 32-bit per 2 pixels */
+ /* 4:2:2, 32-bit per 2 pixels */
case COLOR_INDEX_YUV_422:
- line_stride = ((((hsize+1)>>1)<<5)+127)>>7;
+ line_stride = ((((hsize + 1) >> 1) << 5) + 127) >> 7;
break;
- /* 16-bit LUT */
+ /* 16-bit LUT */
case COLOR_INDEX_16_655:
case COLOR_INDEX_16_844:
case COLOR_INDEX_16_6442:
@@ -583,42 +716,45 @@
case COLOR_INDEX_16_1555_A:
case COLOR_INDEX_16_4444_A:
case COLOR_INDEX_16_565:
- line_stride = ((hsize<<4)+127)>>7;
+ line_stride = ((hsize << 4) + 127) >> 7;
break;
- /* 32-bit LUT */
+ /* 32-bit LUT */
case COLOR_INDEX_32_BGRA:
case COLOR_INDEX_32_ABGR:
case COLOR_INDEX_32_RGBA:
case COLOR_INDEX_32_ARGB:
- line_stride = ((hsize<<5)+127)>>7;
+ line_stride = ((hsize << 5) + 127) >> 7;
break;
+ /* 24-bit LUT */
case COLOR_INDEX_24_6666_A:
case COLOR_INDEX_24_6666_R:
case COLOR_INDEX_24_8565:
case COLOR_INDEX_24_5658:
case COLOR_INDEX_24_888_B:
case COLOR_INDEX_24_RGB:
- /* 24-bit LUT */
- line_stride = ((hsize<<4)+(hsize<<3)+127)>>7;
+ line_stride = ((hsize << 4) + (hsize << 3) + 127) >> 7;
break;
}
+ line_stride_32bytes = ((line_stride + 1) >> 1) << 1;
+ line_stride_64bytes = ((line_stride + 3) >> 2) << 2;
/* need wr ddr is 32bytes aligned */
if (stride_align_32bytes)
- line_stride = ((line_stride+1)>>1)<<1;
+ line_stride = line_stride_32bytes;
else
- line_stride = line_stride;
+ line_stride = line_stride_64bytes;
return line_stride;
}
+
#ifdef AML_OSD_HIGH_VERSION
/* only one layer */
void osd_setting_default_hwc(u32 index, struct pandata_s *disp_data)
{
u32 width, height;
- u32 blend2_premult_en = 0, din_premult_en = 0;
- u32 blend_din_en = 0x1;
+ u32 blend2_premult_en = 3, din_premult_en = 0;
+ u32 blend_din_en = 0x5;
/* blend_din0 input to blend0 */
- u32 din0_byp_blend = 1;
+ u32 din0_byp_blend = 0;
/* blend1_dout to blend2 */
u32 din2_osd_sel = 0;
/* blend1_din3 input to blend1 */
@@ -627,11 +763,16 @@
u32 postbld_src3_sel = 3, postbld_src4_sel = 0;
u32 postbld_osd1_premult = 0, postbld_osd2_premult = 0;
u32 reg_offset = 2;
+ u32 shift_line = osd_hw.shift_line;
+ if (osd_get_chip_type() > MESON_CPU_MAJOR_ID_TM2)
+ reg_offset = 8;
+ if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_T7)
+ postbld_src3_sel = 4;
if (index == OSD1)
- din_reoder_sel = 1;
+ din_reoder_sel = 0x4441;
else if (index == OSD2)
- din_reoder_sel = 2;
+ din_reoder_sel = 0x4442;
/* depend on din0_premult_en */
postbld_osd1_premult = 0;
/* depend on din_premult_en bit 4 */
@@ -674,7 +815,7 @@
0x0);
width = disp_data->x_end - disp_data->x_start + 1;
- height = disp_data->y_end - disp_data->y_start + 1;
+ height = disp_data->y_end - disp_data->y_start + 1 + shift_line;
/* it is setting for osdx */
osd_reg_write(
VIU_OSD_BLEND_DIN0_SCOPE_H + reg_offset * index,
@@ -682,19 +823,38 @@
disp_data->x_start);
osd_reg_write(
VIU_OSD_BLEND_DIN0_SCOPE_V + reg_offset * index,
- disp_data->y_end << 16 |
- disp_data->y_start);
+ (disp_data->y_end + shift_line) << 16 |
+ (disp_data->y_start + shift_line));
+ if (index == OSD1) {
+ int i;
+
+ for (i = 1; i < 4; i++)
+ osd_reg_write(
+ VIU_OSD_BLEND_DIN0_SCOPE_V + reg_offset * i,
+ 0xffffffff);
+ } else if (index == OSD2) {
+ int i = 0;
+
+ osd_reg_write(
+ VIU_OSD_BLEND_DIN0_SCOPE_V + reg_offset * i,
+ 0xffffffff);
+ for (i = 2; i < 4; i++)
+ osd_reg_write(
+ VIU_OSD_BLEND_DIN0_SCOPE_V + reg_offset * i,
+ 0xffffffff);
+ }
+
osd_reg_write(VIU_OSD_BLEND_BLEND0_SIZE,
height << 16 |
width);
osd_reg_write(VIU_OSD_BLEND_BLEND1_SIZE,
height << 16 |
width);
- osd_reg_set_bits(DOLBY_PATH_CTRL,
- 0x3, 2, 2);
-
osd_reg_write(VPP_OSD1_IN_SIZE,
height << 16 | width);
+ if (!is_dolby_enable())
+ osd_reg_set_bits(DOLBY_PATH_CTRL,
+ 0x3, 2, 2);
/* setting blend scope */
osd_reg_write(VPP_OSD1_BLD_H_SCOPE,
@@ -707,7 +867,28 @@
void osd_update_blend(struct pandata_s *disp_data)
{
u32 width, height;
+ int vmode = -1;
+#ifdef CONFIG_AML_VOUT
+ vmode = vout_get_current_vmode();
+#endif
+ switch (vmode) {
+ /* case VMODE_LCD: */
+ case VMODE_480I:
+ case VMODE_480CVBS:
+ case VMODE_576I:
+ case VMODE_576CVBS:
+ case VMODE_1080I:
+ case VMODE_1080I_50HZ:
+#ifdef CONFIG_AML_VOUT_FRAMERATE_AUTOMATION
+ case VMODE_1080I_59HZ:
+#endif
+ disp_data->y_start /=2;
+ disp_data->y_end /= 2;
+ break;
+ default:
+ break;
+ }
width = disp_data->x_end - disp_data->x_start + 1;
height = disp_data->y_end - disp_data->y_start + 1;
@@ -722,6 +903,54 @@
}
#endif
+static void osd_update_mif_linear_addr(u32 index)
+{
+ u32 line_stride, bpp;
+ u32 fmt_mode = 0;
+ u32 osd_blk1_cfg_w4, osd_blk2_cfg_w4, osd_ctrl_stat;
+
+ switch (index) {
+ case 0:
+ osd_blk1_cfg_w4 = VIU_OSD1_BLK1_CFG_W4;
+ osd_blk2_cfg_w4 = VIU_OSD1_BLK2_CFG_W4;
+ osd_ctrl_stat = VIU_OSD1_CTRL_STAT;
+ break;
+ case 1:
+ osd_blk1_cfg_w4 = VIU_OSD2_BLK1_CFG_W4;
+ osd_blk2_cfg_w4 = VIU_OSD2_BLK2_CFG_W4;
+ osd_ctrl_stat = VIU_OSD2_CTRL_STAT;
+ break;
+ case 2:
+ osd_blk1_cfg_w4 = VIU_OSD3_BLK1_CFG_W4;
+ osd_blk2_cfg_w4 = VIU_OSD3_BLK2_CFG_W4;
+ osd_ctrl_stat = VIU_OSD3_CTRL_STAT;
+ break;
+ default:
+ osd_blk1_cfg_w4 = VIU_OSD1_BLK1_CFG_W4;
+ osd_blk2_cfg_w4 = VIU_OSD1_BLK2_CFG_W4;
+ osd_ctrl_stat = VIU_OSD1_CTRL_STAT;
+ break;
+ }
+ if (osd_hw.color_info[index])
+ fmt_mode =
+ osd_hw.color_info[index]->color_index;
+ bpp = osd_hw.color_info[index]->bpp / 8;
+ /* 64 bytes align */
+ line_stride = line_stride_calc
+ (fmt_mode,
+ osd_hw.fb_gem[index].width / bpp, 0);
+ /* set frame addr, 8G addr, need >> 4*/
+ VSYNCOSD_WR_MPEG_REG(osd_blk1_cfg_w4,
+ osd_hw.fb_gem[index].addr >> 4);
+ /* set line stride */
+ VSYNCOSD_WR_MPEG_REG_BITS(osd_blk2_cfg_w4,
+ line_stride,
+ 0, 12);
+ /* used phyic addr */
+ VSYNCOSD_WR_MPEG_REG_BITS(osd_ctrl_stat,
+ 1, 2, 1);
+}
+
void osd_setup_hw(u32 index,
u32 xoffset,
u32 yoffset,
@@ -743,7 +972,7 @@
u32 w = (color->bpp * xres_virtual + 7) >> 3;
if (osd_hw.osd_ver == OSD_SIMPLE) {
- if (index == OSD2) {
+ if (index >= OSD2) {
osd_loge("AXG not support osd2\n");
return ;
}
@@ -786,14 +1015,7 @@
osd_hw.fb_gem[index].addr = fbmem;
osd_hw.fb_gem[index].width = w;
osd_hw.fb_gem[index].height = yres_virtual;
- osd_logd("osd[%d] canvas.idx =0x%x\n",
- index, osd_hw.fb_gem[index].canvas_idx);
- osd_logd("osd[%d] canvas.addr=0x%x\n",
- index, osd_hw.fb_gem[index].addr);
- osd_logd("osd[%d] canvas.width=%d\n",
- index, osd_hw.fb_gem[index].width);
- osd_logd("osd[%d] canvas.height=%d\n",
- index, osd_hw.fb_gem[index].height);
+
if (osd_hw.osd_ver == OSD_SIMPLE) {
u32 line_stride, fmt_mode, bpp;
@@ -808,16 +1030,43 @@
VIU_OSD1_BLK2_CFG_W4,
line_stride,
0, 12);
- }
+ } else {
+ if (osd_hw.mif_linear) {
+ if (index == VIU2_OSD1)
+ /* for dual logo display */
+ osd_hw.fb_gem[index].addr +=
+ fb_gdev.fb_height * CANVAS_ALIGNED(fb_gdev.fb_width * color->bpp >> 3);
+
+ osd_update_mif_linear_addr(index);
+ }
#ifdef CONFIG_AML_CANVAS
- else {
- canvas_config(osd_hw.fb_gem[index].canvas_idx,
- osd_hw.fb_gem[index].addr,
- osd_hw.fb_gem[index].width,
- osd_hw.fb_gem[index].height,
- CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR);
- }
+ else {
+ if (index < VIU2_OSD1) {
+ canvas_config(osd_hw.fb_gem[index].canvas_idx,
+ osd_hw.fb_gem[index].addr,
+ CANVAS_ALIGNED(osd_hw.fb_gem[index].width),
+ osd_hw.fb_gem[index].height,
+ CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR);
+ } else {
+ /* for dual logo display */
+ osd_hw.fb_gem[index].addr += fb_gdev.fb_height * CANVAS_ALIGNED(fb_gdev.fb_width * color->bpp >> 3);
+ canvas_config(osd_hw.fb_gem[index].canvas_idx,
+ osd_hw.fb_gem[index].addr,
+ CANVAS_ALIGNED(osd_hw.fb_gem[index].width),
+ osd_hw.fb_gem[index].height,
+ CANVAS_ADDR_NOWRAP, CANVAS_BLKMODE_LINEAR);
+ }
+ }
#endif
+ }
+ osd_logd("osd[%d] canvas.idx =0x%x\n",
+ index, osd_hw.fb_gem[index].canvas_idx);
+ osd_logd("osd[%d] canvas.addr=0x%x\n",
+ index, osd_hw.fb_gem[index].addr);
+ osd_logd("osd[%d] canvas.width=%d\n",
+ index, CANVAS_ALIGNED(osd_hw.fb_gem[index].width));
+ osd_logd("osd[%d] canvas.height=%d\n",
+ index, osd_hw.fb_gem[index].height);
}
/* osd blank only control by /sys/class/graphcis/fbx/blank */
#if 0
@@ -843,7 +1092,7 @@
add_to_update_list(index, DISP_GEOMETRY);
add_to_update_list(index, DISP_OSD_REVERSE);
#ifdef AML_OSD_HIGH_VERSION
- if (osd_hw.osd_ver == OSD_HIGH_ONE)
+ if (osd_hw.osd_ver == OSD_HIGH_ONE && index < VIU2_OSD1)
osd_setting_default_hwc(index, &disp_data);
#endif
osd_wait_vsync_hw();
@@ -1277,12 +1526,12 @@
osd_hw.dispdata[index].y_end = osd_hw.dispdata[OSD1].y_start +
g_rotation_width;
} else {
- if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_M8) {
+ if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_M8) {
osd_reg_set_mask(VPU_SW_RESET, 1 << 8);
osd_reg_clr_mask(VPU_SW_RESET, 1 << 8);
}
if (index == OSD1) {
- if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_M8) {
+ if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_M8) {
osd_reg_set_mask(VIU_SW_RESET, 1 << 0);
osd_reg_clr_mask(VIU_SW_RESET, 1 << 0);
}
@@ -1436,8 +1685,32 @@
}
}
+#ifdef AML_T7_DISPLAY
+static void viu2_osd1_update_disp_scale_enable(void)
+{
+
+}
+#else
+static void viu2_osd1_update_disp_scale_enable(void)
+{
+ if (osd_hw.scale[VIU2_OSD1].h_enable)
+ VSYNCOSD_SET_MPEG_REG_MASK(VIU2_OSD1_BLK0_CFG_W0, 3 << 12);
+ else
+ VSYNCOSD_CLR_MPEG_REG_MASK(VIU2_OSD1_BLK0_CFG_W0, 3 << 12);
+ if (osd_hw.scan_mode != SCAN_MODE_INTERLACE) {
+ if (osd_hw.scale[VIU2_OSD1].v_enable)
+ VSYNCOSD_SET_MPEG_REG_MASK(VIU2_OSD1_BLK0_CFG_W0,
+ 1 << 14);
+ else
+ VSYNCOSD_CLR_MPEG_REG_MASK(VIU2_OSD1_BLK0_CFG_W0,
+ 1 << 14);
+ }
+}
+#endif
+
static void osd_super_scale_enable(u32 index)
{
+#ifndef AML_OSD_HIGH_VERSION
u32 data32 = 0x0;
osd_super_scale_mem_power_on();
@@ -1469,16 +1742,19 @@
data32 = ((osd_hw.free_dst_data[index].y_end & 0xfff) |
(osd_hw.free_dst_data[index].y_start & 0xfff) << 16);
VSYNCOSD_WR_MPEG_REG(VPP_OSD_SCO_V_START_END, data32);
+#endif
}
static void osd_super_scale_disable(void)
{
+#ifndef AML_OSD_HIGH_VERSION
/* disable osd scaler path */
VSYNCOSD_WR_MPEG_REG(VPP_OSD_SC_CTRL0, 0);
/* disable osd super scaler */
VSYNCOSD_WR_MPEG_REG(OSDSR_HV_SIZEIN, 0);
VSYNCOSD_WR_MPEG_REG(OSDSR_CTRL_MODE, 0);
osd_super_scale_mem_power_off();
+#endif
}
static void osd1_update_disp_freescale_enable(void)
@@ -1492,6 +1768,7 @@
int hf_bank_len = 4;
int vf_bank_len = 0;
u32 data32 = 0x0;
+ u32 shift_line = osd_hw.shift_line;
osd_logi("osd1_update_disp_freescale_enable\n");
if (osd_hw.scale_workaround)
@@ -1519,7 +1796,7 @@
osd_hw.free_dst_data[OSD1].x_start + 1;
dst_h = osd_hw.free_dst_data[OSD1].y_end -
osd_hw.free_dst_data[OSD1].y_start + 1;
- if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_MG9TV) {
+ if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_MG9TV) {
/* super scaler mode */
if (osd_hw.free_scale_mode[OSD1] & 0x2) {
if (osd_hw.free_scale_enable[OSD1])
@@ -1551,9 +1828,12 @@
bot_ini_phase = 0;
vf_phase_step = (vf_phase_step << 4);
/* config osd scaler in/out hv size */
+ if (shift_line)
+ vsc_ini_rcv_num++;
+
data32 = 0x0;
if (osd_hw.free_scale_enable[OSD1]) {
- data32 = (((src_h - 1) & 0x1fff)
+ data32 = (((src_h - 1 + shift_line) & 0x1fff)
| ((src_w - 1) & 0x1fff) << 16);
VSYNCOSD_WR_MPEG_REG(VPP_OSD_SCI_WH_M1, data32);
data32 = ((osd_hw.free_dst_data[OSD1].x_end & 0xfff) |
@@ -1653,6 +1933,8 @@
int hf_bank_len = 4;
int vf_bank_len = 4;
u32 data32 = 0x0;
+ u32 shift_line = osd_hw.shift_line;
+
if (osd_hw.scale_workaround)
vf_bank_len = 2;
hsc_ini_rcv_num = hf_bank_len;
@@ -1666,7 +1948,7 @@
osd_hw.free_dst_data[OSD2].x_start + 1;
dst_h = osd_hw.free_dst_data[OSD2].y_end -
osd_hw.free_dst_data[OSD2].y_start + 1;
- if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_MG9TV) {
+ if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_MG9TV) {
/* super scaler mode */
if (osd_hw.free_scale_mode[OSD2] & 0x2) {
if (osd_hw.free_scale_enable[OSD2])
@@ -1700,9 +1982,11 @@
bot_ini_phase = 0;
vf_phase_step = (vf_phase_step << 4);
/* config osd scaler in/out hv size */
+ if (shift_line)
+ vsc_ini_rcv_num++;
data32 = 0x0;
if (osd_hw.free_scale_enable[OSD2]) {
- data32 = (((src_h - 1) & 0x1fff)
+ data32 = (((src_h - 1 + shift_line) & 0x1fff)
| ((src_w - 1) & 0x1fff) << 16);
VSYNCOSD_WR_MPEG_REG(VPP_OSD_SCI_WH_M1, data32);
data32 = ((osd_hw.free_dst_data[OSD2].x_end & 0xfff) |
@@ -1791,6 +2075,64 @@
remove_from_update_list(OSD2, OSD_FREESCALE_COEF);
}
+static void viu2_osd1_update_disp_freescale_enable(void)
+{
+ /* do nothing */
+
+ remove_from_update_list(VIU2_OSD1, DISP_FREESCALE_ENABLE);
+}
+
+#ifdef AML_T7_DISPLAY
+static void viu2_osd1_update_coef(void)
+{
+
+}
+#else
+static void viu2_osd1_update_coef(void)
+{
+ int i;
+ bool need_update_coef = false;
+ int hf_coef_wren = 1;
+ int vf_coef_wren = 1;
+ unsigned int *hf_coef, *vf_coef;
+ if (osd_hw.scale_workaround) {
+ if (use_v_filter_mode != 3) {
+ use_v_filter_mode = 3;
+ need_update_coef = true;
+ } else
+ need_update_coef = false;
+ } else {
+ if (use_v_filter_mode != osd_v_filter_mode) {
+ use_v_filter_mode = osd_v_filter_mode;
+ need_update_coef = true;
+ } else
+ need_update_coef = false;
+ }
+ if (need_update_coef) {
+ vf_coef = filter_table[use_v_filter_mode];
+ if (vf_coef_wren) {
+ osd_reg_set_bits(VPP_OSD_SCALE_COEF_IDX, 0x0000, 0, 9);
+ for (i = 0; i < 33; i++)
+ osd_reg_write(VPP_OSD_SCALE_COEF, vf_coef[i]);
+ }
+ }
+ need_update_coef = false;
+ if (use_h_filter_mode != osd_h_filter_mode) {
+ use_h_filter_mode = osd_h_filter_mode;
+ need_update_coef = true;
+ }
+ hf_coef = filter_table[use_h_filter_mode];
+ if (need_update_coef) {
+ if (hf_coef_wren) {
+ osd_reg_set_bits(VPP_OSD_SCALE_COEF_IDX, 0x0100, 0, 9);
+ for (i = 0; i < 33; i++)
+ osd_reg_write(VPP_OSD_SCALE_COEF, hf_coef[i]);
+ }
+ }
+ remove_from_update_list(VIU2_OSD1, OSD_FREESCALE_COEF);
+}
+#endif
+
static void osd1_update_color_mode(void)
{
u32 data32 = 0;
@@ -1802,7 +2144,7 @@
if (!osd_hw.rotate[OSD1].on_off)
data32 |= OSD_DATA_LITTLE_ENDIAN << 15;
data32 |= osd_hw.color_info[OSD1]->hw_colormat << 2;
- if (get_cpu_id().family_id < MESON_CPU_MAJOR_ID_GXTVBB) {
+ if (osd_get_chip_type() < MESON_CPU_MAJOR_ID_GXTVBB) {
if (osd_hw.color_info[OSD1]->color_index
< COLOR_INDEX_YUV_422)
data32 |= 1 << 7; /* yuv enable */
@@ -1825,7 +2167,7 @@
if (!osd_hw.rotate[OSD2].on_off)
data32 |= OSD_DATA_LITTLE_ENDIAN << 15;
data32 |= osd_hw.color_info[OSD2]->hw_colormat << 2;
- if (get_cpu_id().family_id != MESON_CPU_MAJOR_ID_GXTVBB) {
+ if (osd_get_chip_type() != MESON_CPU_MAJOR_ID_GXTVBB) {
if (osd_hw.color_info[OSD2]->color_index
< COLOR_INDEX_YUV_422)
data32 |= 1 << 7; /* yuv enable */
@@ -1837,6 +2179,32 @@
remove_from_update_list(OSD2, OSD_COLOR_MODE);
}
+#ifdef AML_T7_DISPLAY
+static void viu2_osd1_update_color_mode(void)
+{
+
+}
+#else
+static void viu2_osd1_update_color_mode(void)
+{
+ u32 data32 = 0;
+ if (osd_hw.color_info[VIU2_OSD1] != NULL) {
+ data32 = (osd_hw.scan_mode == SCAN_MODE_INTERLACE) ? 2 : 0;
+ data32 |= VSYNCOSD_RD_MPEG_REG(VIU2_OSD1_BLK0_CFG_W0)
+ & 0x30007040;
+ data32 |= osd_hw.fb_gem[VIU2_OSD1].canvas_idx << 16;
+ if (!osd_hw.rotate[VIU2_OSD1].on_off)
+ data32 |= OSD_DATA_LITTLE_ENDIAN << 15;
+ data32 |= osd_hw.color_info[VIU2_OSD1]->hw_colormat << 2;
+
+ /* osd_blk_mode */
+ data32 |= osd_hw.color_info[VIU2_OSD1]->hw_blkmode << 8;
+ VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_BLK0_CFG_W0, data32);
+ }
+ remove_from_update_list(VIU2_OSD1, OSD_COLOR_MODE);
+}
+#endif
+
static void osd1_update_enable(void)
{
u32 video_enable = 0;
@@ -1846,9 +2214,9 @@
if (osd_hw.osd_ver <= OSD_NORMAL)
VSYNCOSD_SET_MPEG_REG_MASK(VPP_MISC,
VPP_OSD1_POSTBLEND | VPP_POSTBLEND_EN);
- VSYNCOSD_SET_MPEG_REG_MASK(VIU_OSD1_CTRL_STAT, 1 << 21);
+ VSYNCOSD_SET_MPEG_REG_MASK(VIU_OSD1_CTRL_STAT, 1 << 0);
} else {
- VSYNCOSD_CLR_MPEG_REG_MASK(VIU_OSD1_CTRL_STAT, 1 << 21);
+ VSYNCOSD_CLR_MPEG_REG_MASK(VIU_OSD1_CTRL_STAT, 1 << 0);
if (osd_hw.osd_ver <= OSD_NORMAL)
VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC,
VPP_OSD1_POSTBLEND);
@@ -1889,36 +2257,37 @@
u32 video_enable = 0;
if (osd_hw.free_scale_mode[OSD2]) {
- if (osd_hw.enable[OSD2] == ENABLE) {
+ if (osd_hw.enable[OSD2] == ENABLE)
+ VSYNCOSD_SET_MPEG_REG_MASK(VIU_OSD2_CTRL_STAT,
+ 1 << 0);
+ else
+ VSYNCOSD_CLR_MPEG_REG_MASK(VIU_OSD2_CTRL_STAT,
+ 1 << 0);
+
+ /* for older chips than g12a:
+ * freescale output always on VPP_OSD1_POSTBLEND
+ * if freescale is enable, VPP_OSD1_POSTBLEND to control OSD1&OSD2
+ * if freescale is disable, VPP_OSD2_POSTBLEND to control OSD2
+ */
+ if (osd_hw.osd_ver <= OSD_NORMAL) {
if (osd_hw.free_scale_enable[OSD2]) {
- if (osd_hw.osd_ver <= OSD_NORMAL)
- VSYNCOSD_SET_MPEG_REG_MASK(VPP_MISC,
- VPP_OSD1_POSTBLEND
- | VPP_POSTBLEND_EN);
- VSYNCOSD_SET_MPEG_REG_MASK(VIU_OSD2_CTRL_STAT,
- 1 << 21);
+ if (osd_hw.enable[OSD2] == ENABLE)
+ VSYNCOSD_SET_MPEG_REG_MASK(VPP_MISC,
+ VPP_OSD1_POSTBLEND
+ | VPP_POSTBLEND_EN);
+ else
+ if (!osd_hw.enable[OSD1])
+ VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC,
+ VPP_OSD1_POSTBLEND);
} else {
- VSYNCOSD_CLR_MPEG_REG_MASK(VIU_OSD2_CTRL_STAT,
- 1 << 21);
-#ifndef CONFIG_FB_OSD2_CURSOR
- /*
- VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC,
- VPP_OSD1_POSTBLEND);
- */
-#endif
- if (osd_hw.osd_ver <= OSD_NORMAL)
- VSYNCOSD_SET_MPEG_REG_MASK(VPP_MISC,
- VPP_OSD2_POSTBLEND
- | VPP_POSTBLEND_EN);
+ if (osd_hw.enable[OSD2] == ENABLE)
+ VSYNCOSD_SET_MPEG_REG_MASK(VPP_MISC,
+ VPP_OSD2_POSTBLEND
+ | VPP_POSTBLEND_EN);
+ else
+ VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC,
+ VPP_OSD2_POSTBLEND);
}
- } else {
- if (osd_hw.enable[OSD1] == ENABLE)
- VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC,
- VPP_OSD2_POSTBLEND);
- else
- VSYNCOSD_CLR_MPEG_REG_MASK(VPP_MISC,
- VPP_OSD1_POSTBLEND
- | VPP_OSD2_POSTBLEND);
}
} else if (osd_hw.osd_ver <= OSD_NORMAL){
video_enable |= VSYNCOSD_RD_MPEG_REG(VPP_MISC)&VPP_VD1_PREBLEND;
@@ -1950,6 +2319,24 @@
remove_from_update_list(OSD2, OSD_ENABLE);
}
+#ifdef AML_T7_DISPLAY
+static void viu2_osd1_update_enable(void)
+{
+
+}
+#else
+static void viu2_osd1_update_enable(void)
+{
+ /* do nothing for VPP2_MISC */
+ if (osd_hw.enable[VIU2_OSD1] == ENABLE)
+ VSYNCOSD_SET_MPEG_REG_MASK(VIU2_OSD1_CTRL_STAT, 1 << 0);
+ else
+ VSYNCOSD_CLR_MPEG_REG_MASK(VIU2_OSD1_CTRL_STAT, 1 << 0);
+
+ remove_from_update_list(VIU2_OSD1, OSD_ENABLE);
+}
+#endif
+
static void osd1_update_disp_osd_reverse(void)
{
if (osd_hw.osd_reverse[OSD1])
@@ -1967,6 +2354,23 @@
VSYNCOSD_CLR_MPEG_REG_MASK(VIU_OSD2_BLK0_CFG_W0, 3 << 28);
remove_from_update_list(OSD2, DISP_OSD_REVERSE);
}
+
+#ifdef AML_T7_DISPLAY
+static void viu2_osd1_update_disp_osd_reverse(void)
+{
+
+}
+#else
+static void viu2_osd1_update_disp_osd_reverse(void)
+{
+ if (osd_hw.osd_reverse[VIU2_OSD1])
+ VSYNCOSD_WR_MPEG_REG_BITS(VIU2_OSD1_BLK0_CFG_W0, 3, 28, 2);
+ else
+ VSYNCOSD_CLR_MPEG_REG_MASK(VIU2_OSD1_BLK0_CFG_W0, 3 << 28);
+ remove_from_update_list(VIU2_OSD1, DISP_OSD_REVERSE);
+}
+#endif
+
static void osd1_update_disp_osd_rotate(void)
{
#if 0
@@ -2006,7 +2410,7 @@
y_start = osd_hw.rotation_pandata[OSD1].y_start;
y_end = osd_hw.rotation_pandata[OSD1].y_end;
y_len_m1 = y_end - y_start;
- if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_M8) {
+ if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_M8) {
osd_set_prot(
x_rev,
y_rev,
@@ -2076,7 +2480,7 @@
y_start = osd_hw.rotation_pandata[OSD2].y_start;
y_end = osd_hw.rotation_pandata[OSD2].y_end;
y_len_m1 = y_end - y_start;
- if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_M8) {
+ if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_M8) {
osd_set_prot(
x_rev,
y_rev,
@@ -2107,6 +2511,12 @@
remove_from_update_list(OSD2, DISP_OSD_ROTATE);
}
+static void viu2_osd1_update_disp_osd_rotate(void)
+{
+ /* do nothing*/
+
+ remove_from_update_list(VIU2_OSD1, DISP_OSD_ROTATE);
+}
static void osd1_update_color_key(void)
{
@@ -2120,6 +2530,19 @@
remove_from_update_list(OSD2, OSD_COLOR_KEY);
}
+#ifdef AML_T7_DISPLAY
+static void viu2_osd1_update_color_key(void)
+{
+
+}
+#else
+static void viu2_osd1_update_color_key(void)
+{
+ VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_TCOLOR_AG0, osd_hw.color_key[VIU2_OSD1]);
+ remove_from_update_list(VIU2_OSD1, OSD_COLOR_KEY);
+}
+#endif
+
static void osd1_update_color_key_enable(void)
{
u32 data32;
@@ -2139,7 +2562,25 @@
VSYNCOSD_WR_MPEG_REG(VIU_OSD2_BLK0_CFG_W0, data32);
remove_from_update_list(OSD2, OSD_COLOR_KEY_ENABLE);
}
-static void osd1_update_gbl_alpha(void)
+
+#ifdef AML_T7_DISPLAY
+static void viu2_osd1_update_color_key_enable(void)
+{
+
+}
+#else
+static void viu2_osd1_update_color_key_enable(void)
+{
+ u32 data32;
+ data32 = VSYNCOSD_RD_MPEG_REG(VIU2_OSD1_BLK0_CFG_W0);
+ data32 &= ~(1 << 6);
+ data32 |= (osd_hw.color_key_enable[VIU2_OSD1] << 6);
+ VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_BLK0_CFG_W0, data32);
+ remove_from_update_list(VIU2_OSD1, OSD_COLOR_KEY_ENABLE);
+}
+#endif
+
+static void osd1_update_gbl_alpha(void)
{
u32 data32;
data32 = VSYNCOSD_RD_MPEG_REG(VIU_OSD1_CTRL_STAT);
@@ -2148,7 +2589,8 @@
VSYNCOSD_WR_MPEG_REG(VIU_OSD1_CTRL_STAT, data32);
remove_from_update_list(OSD1, OSD_GBL_ALPHA);
}
-static void osd2_update_gbl_alpha(void)
+
+static void osd2_update_gbl_alpha(void)
{
u32 data32;
data32 = VSYNCOSD_RD_MPEG_REG(VIU_OSD2_CTRL_STAT);
@@ -2157,7 +2599,25 @@
VSYNCOSD_WR_MPEG_REG(VIU_OSD2_CTRL_STAT, data32);
remove_from_update_list(OSD2, OSD_GBL_ALPHA);
}
-static void osd2_update_order(void)
+
+#ifdef AML_T7_DISPLAY
+static void viu2_osd1_update_gbl_alpha(void)
+{
+
+}
+#else
+static void viu2_osd1_update_gbl_alpha(void)
+{
+ u32 data32;
+ data32 = VSYNCOSD_RD_MPEG_REG(VIU2_OSD1_CTRL_STAT);
+ data32 &= ~(0x1ff << 12);
+ data32 |= osd_hw.gbl_alpha[VIU2_OSD1] << 12;
+ VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_CTRL_STAT, data32);
+ remove_from_update_list(VIU2_OSD1, OSD_GBL_ALPHA);
+}
+#endif
+
+static void osd2_update_order(void)
{
switch (osd_hw.order) {
case OSD_ORDER_01:
@@ -2171,7 +2631,8 @@
}
remove_from_update_list(OSD2, OSD_CHANGE_ORDER);
}
-static void osd1_update_order(void)
+
+static void osd1_update_order(void)
{
switch (osd_hw.order) {
case OSD_ORDER_01:
@@ -2186,6 +2647,13 @@
remove_from_update_list(OSD1, OSD_CHANGE_ORDER);
}
+static void viu2_osd1_update_order(void)
+{
+ /* do nothing */
+
+ remove_from_update_list(VIU2_OSD1, OSD_CHANGE_ORDER);
+}
+
static void osd1_2x_scale_update_geometry(void)
{
u32 data32;
@@ -2250,7 +2718,7 @@
{
u32 data32;
- if (get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_M8) {
+ if (osd_get_chip_type() >= MESON_CPU_MAJOR_ID_M8) {
data32 = (osd_hw.dispdata[OSD1].x_start & 0xfff)
| (osd_hw.dispdata[OSD1].x_end & 0xfff) << 16;
VSYNCOSD_WR_MPEG_REG(VIU_OSD1_BLK0_CFG_W3 , data32);
@@ -2344,8 +2812,10 @@
| ((osd_hw.rotation_pandata[OSD1].y_end
+ osd_hw.pandata[OSD1].y_start) & 0x1fff) << 16;
VSYNCOSD_WR_MPEG_REG(VIU_OSD1_BLK0_CFG_W2, data32);
- if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_M8)
+#ifndef AML_OSD_HIGH_VERSION
+ if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_M8)
VSYNCOSD_WR_MPEG_REG(VPU_PROT1_Y_START_END, data32);
+#endif
} else if (osd_hw.rotate[OSD1].on_off
&& osd_hw.rotate[OSD1].angle > 0) {
/* enable osd rotation */
@@ -2357,8 +2827,10 @@
| ((osd_hw.rotation_pandata[OSD1].y_end
+ osd_hw.pandata[OSD1].y_start) & 0x1fff) << 16;
VSYNCOSD_WR_MPEG_REG(VIU_OSD1_BLK0_CFG_W2, data32);
- if (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_M8)
+#ifndef AML_OSD_HIGH_VERSION
+ if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_M8)
VSYNCOSD_WR_MPEG_REG(VPU_PROT1_Y_START_END, data32);
+#endif
} else {
/* normal mode */
data32 = (osd_hw.pandata[OSD1].x_start & 0x1fff)
@@ -2368,10 +2840,6 @@
| (osd_hw.pandata[OSD1].y_end & 0x1fff) << 16;
VSYNCOSD_WR_MPEG_REG(VIU_OSD1_BLK0_CFG_W2, data32);
}
- data32 = osd_reg_read(VIU_OSD1_CTRL_STAT);
- data32 &= 0xfffffff0;
- data32 |= HW_OSD_BLOCK_ENABLE_0;
- osd_reg_write(VIU_OSD1_CTRL_STAT, data32);
}
static void osd1_update_disp_geometry(void)
@@ -2434,7 +2902,40 @@
}
remove_from_update_list(OSD2, DISP_GEOMETRY);
}
-static void osd1_update_disp_3d_mode(void)
+
+#ifdef AML_T7_DISPLAY
+static void viu2_osd1_update_disp_geometry(void)
+{
+
+}
+#else
+static void viu2_osd1_update_disp_geometry(void)
+{
+ u32 data32;
+ data32 = (osd_hw.dispdata[VIU2_OSD1].x_start & 0xfff)
+ | (osd_hw.dispdata[VIU2_OSD1].x_end & 0xfff) << 16;
+ VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_BLK0_CFG_W3 , data32);
+ if (osd_hw.scan_mode == SCAN_MODE_INTERLACE)
+ data32 = ((osd_hw.dispdata[VIU2_OSD1].y_start >> 1) & 0xfff)
+ | ((((osd_hw.dispdata[VIU2_OSD1].y_end + 1) >> 1) - 1)
+ & 0xfff) << 16;
+ else
+ data32 = (osd_hw.dispdata[VIU2_OSD1].y_start & 0xfff)
+ | (osd_hw.dispdata[VIU2_OSD1].y_end & 0xfff) << 16;
+ VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_BLK0_CFG_W4, data32);
+
+ data32 = (osd_hw.pandata[VIU2_OSD1].x_start & 0x1fff)
+ | (osd_hw.pandata[VIU2_OSD1].x_end & 0x1fff) << 16;
+ VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_BLK0_CFG_W1, data32);
+ data32 = (osd_hw.pandata[VIU2_OSD1].y_start & 0x1fff)
+ | (osd_hw.pandata[VIU2_OSD1].y_end & 0x1fff) << 16;
+ VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_BLK0_CFG_W2, data32);
+
+ remove_from_update_list(VIU2_OSD1, DISP_GEOMETRY);
+}
+#endif
+
+static void osd1_update_disp_3d_mode(void)
{
/*step 1 . set pan data */
u32 data32;
@@ -2465,6 +2966,28 @@
osd_hw.mode_3d[OSD2].left_right ^= 1;
}
+#ifdef AML_T7_DISPLAY
+static void viu2_osd1_update_disp_3d_mode(void)
+{
+
+}
+#else
+static void viu2_osd1_update_disp_3d_mode(void)
+{
+ u32 data32;
+ if (osd_hw.mode_3d[VIU2_OSD1].left_right == OSD_LEFT) {
+ data32 = (osd_hw.mode_3d[VIU2_OSD1].l_start & 0x1fff)
+ | (osd_hw.mode_3d[VIU2_OSD1].l_end & 0x1fff) << 16;
+ VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_BLK0_CFG_W1, data32);
+ } else {
+ data32 = (osd_hw.mode_3d[VIU2_OSD1].r_start & 0x1fff)
+ | (osd_hw.mode_3d[VIU2_OSD1].r_end & 0x1fff) << 16;
+ VSYNCOSD_WR_MPEG_REG(VIU2_OSD1_BLK0_CFG_W1, data32);
+ }
+ osd_hw.mode_3d[VIU2_OSD1].left_right ^= 1;
+}
+#endif
+
void osd_hist_enable(u32 osd_index)
{
if (osd_hw.osd_ver == OSD_HIGH_ONE) {
@@ -2494,10 +3017,142 @@
return 0;
}
+#ifdef AML_T7_DISPLAY
+void osd_init_hw_viu2(void)
+{
+
+}
+#else
+void osd_init_hw_viu2(void)
+{
+ u32 group, idx, data32;
+ char *osd_reverse;
+
+ osd_reverse = env_get("osd_reverse");
+ for (group = 0; group < HW_OSD_COUNT; group++)
+ for (idx = 0; idx < HW_REG_INDEX_MAX; idx++)
+ osd_hw.reg[group][idx].update_func =
+ hw_func_array[group][idx];
+
+ osd_hw.updated[VIU2_OSD1] = 0;
+
+ osd_vpu_power_on_viu2();
+
+ osd_reg_write(VPP2_OFIFO_SIZE, 0x7ff00800);
+
+ /* init osd fifo control register */
+ /* set DDR request priority to be urgent */
+ data32 = 1;
+ /* hold_fifo_lines */
+ data32 |= 4 << 5;
+ /* burst_len_sel: 3=64 */
+ data32 |= 1 << 10;
+ data32 |= 1 << 31;
+
+ /*
+ * bit 23:22, fifo_ctrl
+ * 00 : for 1 word in 1 burst
+ * 01 : for 2 words in 1 burst
+ * 10 : for 4 words in 1 burst
+ * 11 : reserved
+ */
+ data32 |= 2 << 22;
+ /* bit 28:24, fifo_lim */
+ data32 |= 2 << 24;
+ /* fifo_depth_val: 32 or 64 *8 = 256 or 512 */
+ data32 |= 64 << 12;
+
+ osd_reg_write(VIU2_OSD1_FIFO_CTRL_STAT, data32);
+
+ /* disable osd */
+ data32 = 0x0 << 0;
+ data32 |= OSD_GLOBAL_ALPHA_DEF << 12;
+ data32 |= 0x80000000;
+ osd_reg_write(VIU2_OSD1_CTRL_STAT , data32);
+
+ /* set replaced_alpha */
+ data32 = 0x1 << 14;
+ data32 |= 0xff << 6;
+ osd_reg_write(VIU2_OSD1_CTRL_STAT2 , data32);
+ osd_hw.enable[VIU2_OSD1] = DISABLE;
+
+ osd_hw.fb_gem[VIU2_OSD1].canvas_idx = OSD4_CANVAS_INDEX;
+ osd_hw.gbl_alpha[VIU2_OSD1] = OSD_GLOBAL_ALPHA_DEF;
+ osd_hw.color_info[VIU2_OSD1] = NULL;
+ osd_hw.color_key[VIU2_OSD1] = 0xffffffff;
+ osd_hw.scale[VIU2_OSD1].h_enable = osd_hw.scale[VIU2_OSD1].v_enable = 0;
+ osd_hw.mode_3d[VIU2_OSD1].enable = 0;
+ if (osd_reverse != NULL && strcmp(osd_reverse, "all,true") == 0) {
+ osd_hw.osd_reverse[VIU2_OSD1] = 1;
+ } else {
+ osd_hw.osd_reverse[VIU2_OSD1] = 0;
+ }
+ osd_hw.rotation_pandata[VIU2_OSD1].x_start = 0;
+ osd_hw.rotation_pandata[VIU2_OSD1].y_start = 0;
+}
+#endif
+
+static void set_vpp_super_position(void)
+{
+#define PREBLD_SR0_VD1_SCALER (1 << 1)
+#define DNLP_SR1_CM (1 << 3)
+
+ if ((osd_get_chip_type() == MESON_CPU_MAJOR_ID_G12A) ||
+ (osd_get_chip_type() == MESON_CPU_MAJOR_ID_G12B) ||
+ (osd_get_chip_type() == MESON_CPU_MAJOR_ID_SM1))
+ osd_reg_set_mask(VPP_MISC, PREBLD_SR0_VD1_SCALER);
+ else if ((osd_get_chip_type() == MESON_CPU_MAJOR_ID_TL1) ||
+ (osd_get_chip_type() >= MESON_CPU_MAJOR_ID_TM2))
+ osd_reg_set_mask(VPP_MISC, DNLP_SR1_CM);
+}
+
+static void fix_vpu_clk2_default_regs(void)
+{
+#ifdef AML_T7_DISPLAY
+ if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_T7) {
+ /* default: osd byp osd_blend */
+ osd_reg_set_bits(VPP_OSD1_SCALE_CTRL, 0x2, 0, 3);
+ osd_reg_set_bits(VPP_OSD2_SCALE_CTRL, 0x3, 0, 3);
+ osd_reg_set_bits(VPP_OSD3_SCALE_CTRL, 0x3, 0, 3);
+ osd_reg_set_bits(VPP_OSD4_SCALE_CTRL, 0x3, 0, 3);
+
+ /* default: osd byp dolby */
+ osd_reg_set_bits(VPP_VD1_DSC_CTRL, 0x1, 4, 1);
+ osd_reg_set_bits(VPP_VD2_DSC_CTRL, 0x1, 4, 1);
+ osd_reg_set_bits(VPP_VD3_DSC_CTRL, 0x1, 4, 1);
+ osd_reg_set_bits(MALI_AFBCD_TOP_CTRL, 0x1, 14, 1);
+ osd_reg_set_bits(MALI_AFBCD_TOP_CTRL, 0x1, 19, 1);
+ osd_reg_set_bits(MALI_AFBCD1_TOP_CTRL, 0x1, 19, 1);
+ osd_reg_set_bits(MALI_AFBCD1_TOP_CTRL, 0x1, 19, 1);
+
+ /* default: osd 12bit path */
+ osd_reg_set_bits(VPP_VD1_DSC_CTRL, 0x0, 5, 1);
+ osd_reg_set_bits(VPP_VD2_DSC_CTRL, 0x0, 5, 1);
+ osd_reg_set_bits(VPP_VD3_DSC_CTRL, 0x0, 5, 1);
+ osd_reg_set_bits(MALI_AFBCD_TOP_CTRL, 0x0, 15, 1);
+ osd_reg_set_bits(MALI_AFBCD_TOP_CTRL, 0x0, 20, 1);
+ osd_reg_set_bits(MALI_AFBCD1_TOP_CTRL, 0x0, 20, 1);
+ osd_reg_set_bits(MALI_AFBCD1_TOP_CTRL, 0x0, 20, 1);
+
+ /* clean vpp_top 1/2 blend default order */
+ osd_reg_set_bits(VPP1_BLD_CTRL, 0x0, 0, 8);
+ osd_reg_set_bits(VPP2_BLD_CTRL, 0x0, 0, 8);
+
+ /* set vpp_top 1/2 default blend dummy */
+ osd_reg_write(VPP1_BLEND_BLEND_DUMMY_DATA, 0x008080);
+ osd_reg_write(VPP1_BLEND_DUMMY_ALPHA, 0xffffffff);
+ osd_reg_write(VPP2_BLEND_BLEND_DUMMY_DATA, 0x008080);
+ osd_reg_write(VPP2_BLEND_DUMMY_ALPHA, 0xffffffff);
+
+ }
+#endif
+}
+
void osd_init_hw(void)
{
u32 group, idx, data32, data2;
char *osd_reverse;
+ struct vinfo_s *info = NULL;
osd_reverse = env_get("osd_reverse");
for (group = 0; group < HW_OSD_COUNT; group++)
@@ -2507,15 +3162,21 @@
osd_hw.updated[OSD1] = 0;
osd_hw.updated[OSD2] = 0;
+ /* set display output resolution */
+ info = vout_get_current_vinfo();
+ if (info != NULL)
+ osd_reg_write(VPP_POSTBLEND_H_SIZE, info->width);
osd_vpu_power_on();
+ fix_vpu_clk2_default_regs();
/* here we will init default value ,these value only set once . */
if (!logo_loaded) {
/* init vpu fifo control register */
data32 = osd_reg_read(VPP_OFIFO_SIZE);
osd_logi("VPP_OFIFO_SIZE:0x%x\n", data32);
if (osd_hw.osd_ver == OSD_HIGH_ONE) {
- data32 = 0xfff << 20;
+ data32 &= ~((0xfff << 20) | 0x3fff);
+ data32 |= (0xfff << 20);
data32 |= (0xfff + 1);
osd_reg_write(VPP_OFIFO_SIZE, data32);
}
@@ -2523,16 +3184,17 @@
/* init osd fifo control register */
/* set DDR request priority to be urgent */
data32 = 1;
- if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_M6TV)
- || (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_MTVD)) {
+ if ((osd_get_chip_type() == MESON_CPU_MAJOR_ID_M6TV)
+ || (osd_get_chip_type() == MESON_CPU_MAJOR_ID_MTVD)) {
data32 |= 18 << 5; /* hold_fifo_lines */
} else if (osd_hw.osd_ver == OSD_SIMPLE) {
data32 &= ~(0x1f << 5); /* bit[9:5] HOLD_FIFO_LINES */
data32 |= 0x18 << 5;
- } else if (osd_hw.osd_ver == OSD_HIGH_ONE) {
- data32 |= 8 << 5; /* hold_fifo_lines */
} else {
- data32 |= 4 << 5; /* hold_fifo_lines */
+ if (osd_hw.osd_ver == OSD_HIGH_ONE)
+ data32 |= 8 << 5; /* hold_fifo_lines */
+ else
+ data32 |= 4 << 5; /* hold_fifo_lines */
}
/* burst_len_sel: 3=64 */
if (osd_hw.osd_ver == OSD_HIGH_ONE) {
@@ -2541,7 +3203,7 @@
} else
data32 |= 3 << 10;
- if (get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_GXBB) {
+ if (osd_get_chip_type() >= MESON_CPU_MAJOR_ID_GXBB) {
/*
* bit 23:22, fifo_ctrl
* 00 : for 1 word in 1 burst
@@ -2555,8 +3217,8 @@
}
data2 = data32;
/* fifo_depth_val: 32*8=256 */
- if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TXL)
- || (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TXLX))
+ if ((osd_get_chip_type() == MESON_CPU_MAJOR_ID_TXL)
+ || (osd_get_chip_type() == MESON_CPU_MAJOR_ID_TXLX))
data32 |= 64 << 12;
else
data32 |= 32 << 12;
@@ -2569,18 +3231,26 @@
osd_reg_clr_mask(VPP_MISC,
VPP_OSD1_POSTBLEND | VPP_OSD2_POSTBLEND | VPP_VD1_POSTBLEND);
/* just disable osd to avoid booting hang up */
- if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_M6TV)
- || (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_MTVD)) {
- data32 = 0x0 << 0; /* osd_blk_enable */
- } else
- data32 = 0x1 << 0;
+ data32 = 0x0 << 0;
data32 |= OSD_GLOBAL_ALPHA_DEF << 12;
- data32 |= (1 << 21);
osd_reg_write(VIU_OSD1_CTRL_STAT , data32);
osd_reg_write(VIU_OSD2_CTRL_STAT , data32);
+
+ /* set replaced_alpha */
+ data32 = 0x1 << 14;
+ data32 |= 0xff << 6;
+ osd_reg_write(VIU_OSD1_CTRL_STAT2 , data32);
+ osd_reg_write(VIU_OSD2_CTRL_STAT2 , data32);
+ logo_loaded = 1;
}
if (osd_hw.osd_ver <= OSD_NORMAL)
osd_reg_clr_mask(VPP_MISC, VPP_POST_FG_OSD2 | VPP_PRE_FG_OSD2);
+ else if (osd_hw.osd_ver > OSD_NORMAL)
+ set_vpp_super_position();
+
+ if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_S4)
+ osd_reg_clr_mask(VPP_MISC, VPP_WATER_MARK_10BIT);
+
osd_hw.order = OSD_ORDER_01;
osd_hw.enable[OSD2] = osd_hw.enable[OSD1] = DISABLE;
osd_hw.fb_gem[OSD1].canvas_idx = OSD1_CANVAS_INDEX;
@@ -2608,7 +3278,7 @@
osd_hw.rotation_pandata[OSD2].x_start = 0;
osd_hw.rotation_pandata[OSD2].y_start = 0;
osd_hw.antiflicker_mode = 0;
- if (get_cpu_id().family_id >= MESON_CPU_MAJOR_ID_M8) {
+ if (osd_get_chip_type() >= MESON_CPU_MAJOR_ID_M8) {
osd_hw.free_scale_data[OSD1].x_start = 0;
osd_hw.free_scale_data[OSD1].x_end = 0;
osd_hw.free_scale_data[OSD1].y_start = 0;
@@ -2619,10 +3289,10 @@
osd_hw.free_scale_data[OSD2].y_end = 0;
osd_hw.free_scale_mode[OSD1] = 1;
osd_hw.free_scale_mode[OSD2] = 1;
- if ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXM)
- ||(get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TXLX))
+ if ((osd_get_chip_type() == MESON_CPU_MAJOR_ID_GXM)
+ ||(osd_get_chip_type() == MESON_CPU_MAJOR_ID_TXLX))
osd_reg_write(VPP_OSD_SC_DUMMY_DATA, 0x00202000);
- else if (get_cpu_id().family_id ==
+ else if (osd_get_chip_type() ==
MESON_CPU_MAJOR_ID_GXTVBB)
osd_reg_write(VPP_OSD_SC_DUMMY_DATA, 0xff);
else
@@ -2632,7 +3302,14 @@
osd_hw.free_scale_mode[OSD2] = 0;
}
memset(osd_hw.rotate, 0, sizeof(struct osd_rotate_s));
-
+ if ((osd_get_chip_type() == MESON_CPU_MAJOR_ID_G12A) ||
+ ((osd_get_chip_type() == MESON_CPU_MAJOR_ID_G12B) &&
+ (get_cpu_id().chip_rev == MESON_CPU_CHIP_REVISION_A)))
+ osd_hw.shift_line = 1;
+ else
+ osd_hw.shift_line = 0;
+ if (osd_get_chip_type() == MESON_CPU_MAJOR_ID_T7)
+ osd_hw.mif_linear = 1;
return;
}
diff --git a/drivers/amlogic/media/osd/osd_hw.h b/drivers/amlogic/media/osd/osd_hw.h
index e013551..fd49804 100644
--- a/drivers/amlogic/media/osd/osd_hw.h
+++ b/drivers/amlogic/media/osd/osd_hw.h
@@ -1,19 +1,7 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/osd/osd_hw.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _OSD_HW_H_
#define _OSD_HW_H_
@@ -22,7 +10,8 @@
#define REG_OFFSET (0x20)
#define OSD_RELATIVE_BITS 0x33370
-
+extern void osd_init_hw_viu2(void);
+extern int osd_get_chip_type(void);
extern void osd_init_hw(void);
extern void osd_set_color_key_hw(u32 index, u32 bpp, u32 colorkey);
extern void osd_srckey_enable_hw(u32 index, u8 enable);
diff --git a/drivers/amlogic/media/osd/osd_hw_def.h b/drivers/amlogic/media/osd/osd_hw_def.h
index be90347..559ed10 100644
--- a/drivers/amlogic/media/osd/osd_hw_def.h
+++ b/drivers/amlogic/media/osd/osd_hw_def.h
@@ -1,19 +1,7 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/osd/osd_hw_def.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _OSD_HW_DEF_H_
#define _OSD_HW_DEF_H_
@@ -48,6 +36,20 @@
static void osd2_update_disp_scale_enable(void);
static void osd2_update_disp_3d_mode(void);
+static void viu2_osd1_update_color_mode(void);
+static void viu2_osd1_update_enable(void);
+static void viu2_osd1_update_color_key(void);
+static void viu2_osd1_update_color_key_enable(void);
+static void viu2_osd1_update_gbl_alpha(void);
+static void viu2_osd1_update_order(void);
+static void viu2_osd1_update_disp_geometry(void);
+static void viu2_osd1_update_coef(void);
+static void viu2_osd1_update_disp_freescale_enable(void);
+static void viu2_osd1_update_disp_osd_reverse(void);
+static void viu2_osd1_update_disp_osd_rotate(void);
+static void viu2_osd1_update_disp_scale_enable(void);
+static void viu2_osd1_update_disp_3d_mode(void);
+
extern struct hw_para_s osd_hw;
static update_func_t hw_func_array[HW_OSD_COUNT][HW_REG_INDEX_MAX] = {
{
@@ -78,6 +80,20 @@
osd2_update_disp_osd_reverse,
osd2_update_disp_osd_rotate,
},
+ {
+ viu2_osd1_update_color_mode,
+ viu2_osd1_update_enable,
+ viu2_osd1_update_color_key,
+ viu2_osd1_update_color_key_enable,
+ viu2_osd1_update_gbl_alpha,
+ viu2_osd1_update_order,
+ viu2_osd1_update_coef,
+ viu2_osd1_update_disp_geometry,
+ viu2_osd1_update_disp_scale_enable,
+ viu2_osd1_update_disp_freescale_enable,
+ viu2_osd1_update_disp_osd_reverse,
+ viu2_osd1_update_disp_osd_rotate,
+ },
};
#define add_to_update_list(osd_idx, cmd_idx) \
diff --git a/drivers/amlogic/media/osd/osd_io.h b/drivers/amlogic/media/osd/osd_io.h
index 286f16f..31d642a 100644
--- a/drivers/amlogic/media/osd/osd_io.h
+++ b/drivers/amlogic/media/osd/osd_io.h
@@ -1,20 +1,7 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/osd/osd_io.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
-*/
-
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _OSD_IO_H_
#define _OSD_IO_H_
@@ -22,34 +9,141 @@
#include <asm/arch/io.h>
#include <asm/arch/secure_apb.h>
+#ifndef REG_BASE_VCBUS
+#define REG_BASE_VCBUS (0xFF900000L)
+#endif
-#define REG_OFFSET_CBUS(reg) ((reg << 2))
+/* osd super scale */
+#ifndef OSDSR_HV_SIZEIN
+#define OSDSR_HV_SIZEIN VPP_OSDSC_DITHER_CTRL
+#endif
+
+#ifndef OSDSR_CTRL_MODE
+#define OSDSR_CTRL_MODE VPP_OSDSC_DITHER_LUT_1
+#endif
+
+#ifdef OSDSR_ABIC_HCOEF
+#define OSDSR_ABIC_HCOEF VPP_OSDSC_DITHER_LUT_2
+#endif
+
+#ifndef OSDSR_YBIC_HCOEF
+#define OSDSR_YBIC_HCOEF VPP_OSDSC_DITHER_LUT_3
+#endif
+
+#ifndef OSDSR_CBIC_HCOEF
+#define OSDSR_CBIC_HCOEF VPP_OSDSC_DITHER_LUT_4
+#endif
+
+#ifndef OSDSR_ABIC_VCOEF
+#define OSDSR_ABIC_VCOEF VPP_OSDSC_DITHER_LUT_5
+#endif
+
+#ifndef OSDSR_YBIC_VCOEF
+#define OSDSR_YBIC_VCOEF VPP_OSDSC_DITHER_LUT_6
+#endif
+
+#ifndef OSDSR_CBIC_VCOEF
+#define OSDSR_CBIC_VCOEF VPP_OSDSC_DITHER_LUT_7
+#endif
+
+#ifndef OSDSR_VAR_PARA
+#define OSDSR_VAR_PARA VPP_OSDSC_DITHER_LUT_8
+#endif
+
+#ifndef OSDSR_CONST_PARA
+#define OSDSR_CONST_PARA VPP_OSDSC_DITHER_LUT_9
+#endif
+
+#ifndef OSDSR_RKE_EXTWIN
+#define OSDSR_RKE_EXTWIN VPP_OSDSC_DITHER_LUT_10
+#endif
+
+#ifndef OSDSR_UK_GRAD2DDIAG_TH_RATE
+#define OSDSR_UK_GRAD2DDIAG_TH_RATE VPP_OSDSC_DITHER_LUT_11
+#endif
+
+#ifndef OSDSR_UK_GRAD2DDIAG_LIMIT
+#define OSDSR_UK_GRAD2DDIAG_LIMIT VPP_OSDSC_DITHER_LUT_12
+#endif
+
+#ifndef OSDSR_UK_GRAD2DADJA_TH_RATE
+#define OSDSR_UK_GRAD2DADJA_TH_RATE VPP_OSDSC_DITHER_LUT_13
+#endif
+
+#ifndef OSDSR_UK_GRAD2DADJA_LIMIT
+#define OSDSR_UK_GRAD2DADJA_LIMIT VPP_OSDSC_DITHER_LUT_14
+#endif
+
+#ifndef OSDSR_UK_BST_GAIN
+#define OSDSR_UK_BST_GAIN VPP_OSDSC_DITHER_LUT_15
+#endif
+
+#ifndef VPP_OSD1_SCALE_CTRL
+#define VPP_OSD1_SCALE_CTRL 0x1a73
+#endif
+
+#ifndef VPP_OSD2_SCALE_CTRL
+#define VPP_OSD2_SCALE_CTRL 0x1a74
+#endif
+
+#ifndef VPP_OSD3_SCALE_CTRL
+#define VPP_OSD3_SCALE_CTRL 0x1a75
+#endif
+
+#ifndef VPP_OSD4_SCALE_CTRL
+#define VPP_OSD4_SCALE_CTRL 0x1a76
+#endif
+
+#ifndef MALI_AFBCD1_TOP_CTRL
+#define MALI_AFBCD1_TOP_CTRL 0x1a55
+#endif
+
+#ifndef VPP_VD1_DSC_CTRL
+#define VPP_VD1_DSC_CTRL 0x1a83
+#endif
+
+#ifndef VPP_VD2_DSC_CTRL
+#define VPP_VD2_DSC_CTRL 0x1a84
+#endif
+
+#ifndef VPP_VD3_DSC_CTRL
+#define VPP_VD3_DSC_CTRL 0x1a85
+#endif
+
+#ifndef VIU_OSD3_BLK1_CFG_W4
+#define VIU_OSD3_BLK1_CFG_W4 0x3d99
+#endif
+
+#ifndef VIU_OSD3_BLK2_CFG_W4
+#define VIU_OSD3_BLK2_CFG_W4 0x3d9a
+#endif
+
+#ifndef VIU_OSD3_CTRL_STAT
+#define VIU_OSD3_CTRL_STAT 0x3d80
+#endif
+
#define REG_OFFSET_VCBUS(reg) ((reg << 2))
-
-#define REG_ADDR_CBUS(reg) (REG_BASE_CBUS + REG_OFFSET_CBUS(reg))
-#define REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg))
-
-static inline u32 osd_cbus_read(u32 reg)
-{
- return (*(volatile unsigned int *)REG_ADDR_CBUS(reg));
-}
-
-static inline void osd_cbus_write(u32 reg,
- const u32 val)
-{
- *(volatile unsigned int *)REG_ADDR_CBUS(reg) = (val);
-}
-
+#define REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg) + 0L)
+#define REG_OSD_ADDR(reg) (reg + 0L)
static inline u32 osd_reg_read(u32 reg)
{
- return (*(volatile unsigned int *)REG_ADDR_VCBUS(reg));
+ u32 val;
+
+ if (reg > 0x10000)
+ val = *(volatile unsigned int *)REG_OSD_ADDR(reg);
+ else
+ val = *(volatile unsigned int *)REG_ADDR_VCBUS(reg);
+ return val;
}
static inline void osd_reg_write(u32 reg,
const u32 val)
{
- *(volatile unsigned int *)REG_ADDR_VCBUS(reg) = (val);
+ if (reg > 0x10000)
+ *(volatile unsigned int *)REG_OSD_ADDR(reg) = (val);
+ else
+ *(volatile unsigned int *)REG_ADDR_VCBUS(reg) = (val);
}
static inline void osd_reg_set_mask(u32 reg,
diff --git a/drivers/amlogic/media/osd/osd_log.h b/drivers/amlogic/media/osd/osd_log.h
index b0deb20..f3d7169 100644
--- a/drivers/amlogic/media/osd/osd_log.h
+++ b/drivers/amlogic/media/osd/osd_log.h
@@ -1,20 +1,7 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/osd/osd_log.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
-*/
-
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _OSD_LOG_H_
#define _OSD_LOG_H_
@@ -36,12 +23,8 @@
#define osd_logv(fmt, ...) \
printf(OSD_LOG_TAG "%s:%d " fmt, __func__, __LINE__, ##__VA_ARGS__)
-#ifdef BL33_DEBUG_PRINT
#define osd_logi(fmt, ...) \
printf(OSD_LOG_TAG fmt, ##__VA_ARGS__)
-#else
-#define osd_logi(fmt, ...)
-#endif
#define osd_loge(fmt, ...) \
printf(OSD_LOG_TAG "ERR: " fmt, ##__VA_ARGS__)
diff --git a/drivers/amlogic/media/osd/vpp.h b/drivers/amlogic/media/osd/vpp.h
index 0a057a5..829373e 100644
--- a/drivers/amlogic/media/osd/vpp.h
+++ b/drivers/amlogic/media/osd/vpp.h
@@ -1,20 +1,7 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/osd/vpp.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
-*/
-
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _VPP_H_
#define _VPP_H_
@@ -32,4 +19,8 @@
#define VPP_PREBLEND_EN (1 << 6)
#define VPP_POST_FG_OSD2 (1 << 4)
+#define VPP_WATER_MARK_10BIT (1 << 10)
+
+void set_vpp_matrix(int m_select, int *s, int on);
+
#endif
diff --git a/drivers/amlogic/media/vout/Kconfig b/drivers/amlogic/media/vout/Kconfig
index 7d268f6..f39ae9d 100644
--- a/drivers/amlogic/media/vout/Kconfig
+++ b/drivers/amlogic/media/vout/Kconfig
@@ -3,4 +3,3 @@
source "drivers/amlogic/media/vout/hdmitx/Kconfig"
source "drivers/amlogic/media/vout/lcd/Kconfig"
-
diff --git a/drivers/amlogic/media/vout/Makefile b/drivers/amlogic/media/vout/Makefile
index 1369907..1b345cf 100644
--- a/drivers/amlogic/media/vout/Makefile
+++ b/drivers/amlogic/media/vout/Makefile
@@ -4,6 +4,6 @@
obj-$(CONFIG_AML_CVBS) += cvbs/
-obj-$(CONFIG_AML_HDMITX) += hdmitx/
-
obj-$(CONFIG_AML_LCD) += lcd/
+
+obj-$(CONFIG_AML_HDMITX) += hdmitx/
diff --git a/drivers/amlogic/media/vout/cvbs/Kconfig b/drivers/amlogic/media/vout/cvbs/Kconfig
index 3bfce3b..d31a9ef 100644
--- a/drivers/amlogic/media/vout/cvbs/Kconfig
+++ b/drivers/amlogic/media/vout/cvbs/Kconfig
@@ -3,4 +3,3 @@
depends on AML_VOUT
help
Support for cvbs video output
-
diff --git a/drivers/amlogic/media/vout/cvbs/Makefile b/drivers/amlogic/media/vout/cvbs/Makefile
index 3199606..2d21bd6 100644
--- a/drivers/amlogic/media/vout/cvbs/Makefile
+++ b/drivers/amlogic/media/vout/cvbs/Makefile
@@ -1 +1 @@
-obj-$(CONFIG_AML_CVBS) += aml_cvbs.o
\ No newline at end of file
+obj-$(CONFIG_AML_CVBS) += cvbs.o vdac.o
\ No newline at end of file
diff --git a/drivers/amlogic/media/vout/cvbs/aml_cvbs.c b/drivers/amlogic/media/vout/cvbs/aml_cvbs.c
deleted file mode 100644
index f7426c6..0000000
--- a/drivers/amlogic/media/vout/cvbs/aml_cvbs.c
+++ /dev/null
@@ -1,834 +0,0 @@
-/*
- * drivers/display/vout/cvbs.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * Author: jets.yan@amlogic.com
- *
-*/
-#include <common.h>
-#include <asm/arch/io.h>
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/cpu.h>
-#include <asm/arch/cpu_id.h>
-#include "aml_cvbs_regs.h"
-#include "aml_cvbs_config.h"
-
-/*----------------------------------------------------------------------------*/
-// global variables
-enum CVBS_MODE_e
-{
- VMODE_PAL,
- VMODE_NTSC,
- VMODE_PAL_M,
- VMODE_PAL_N,
- VMODE_NTSC_M,
- VMODE_MAX
-};
-
-unsigned int cvbs_mode = VMODE_MAX;
-/*bit[0]: 0=vid_pll, 1=gp0_pll*/
-/*bit[1]: 0=vid2_clk, 1=vid1_clk*/
-/*path 0:vid_pll vid2_clk*/
-/*path 1:gp0_pll vid2_clk*/
-/*path 2:vid_pll vid1_clk*/
-/*path 3:gp0_pll vid1_clk*/
-static unsigned int s_enci_clk_path = 0;
-
-/*----------------------------------------------------------------------------*/
-// interface for registers of soc
-
-#define REG_OFFSET_VCBUS(reg) (((reg) << 2))
-#define REG_OFFSET_CBUS(reg) (((reg) << 2))
-
-/* memory mapping */
-#define REG_ADDR_HIU(reg) (reg + 0L)
-#define REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg))
-#define REG_ADDR_CBUS(reg) (REG_BASE_CBUS + REG_OFFSET_CBUS(reg))
-
-static unsigned int cvbs_get_hiu_logic_addr(unsigned int addr_offset)
-{
- return (REG_BASE_HIU + ((addr_offset&0xff)<<2));
-}
-
-static int cvbs_write_cbus(unsigned int addr_offset, unsigned int value)
-{
- *(volatile unsigned int *)REG_ADDR_CBUS(addr_offset) = (value);
- return 0;
-}
-
-static int cvbs_read_cbus(unsigned int addr_offset)
-{
- unsigned int val = 0;
-
- val = *(volatile unsigned int *)(REG_ADDR_CBUS(addr_offset));
- return val;
-}
-
-static int cvbs_write_hiu(unsigned int addr, unsigned int value)
-{
- *(volatile unsigned int *)REG_ADDR_HIU(addr) = (value);
- return 0;
-}
-
-static int cvbs_read_hiu(unsigned int addr)
-{
- unsigned int val = 0;
-
- val = *(volatile unsigned int *)(REG_ADDR_HIU(addr));
- return val;
-}
-
-static int cvbs_set_hiu_bits(unsigned int addr, unsigned int value, unsigned int start, unsigned int len)
-{
- cvbs_write_hiu(addr, ((cvbs_read_hiu(addr) &
- ~(((1L << (len))-1) << (start))) |
- (((value)&((1L<<(len))-1)) << (start))));
- return 0;
-}
-
-static int cvbs_get_hiu_bits(unsigned int addr, unsigned int start, unsigned int len)
-{
- return (cvbs_read_hiu(addr) >> (start)) & ((1L << (len)) - 1);
-}
-
-static unsigned int cvbs_read_vcbus(unsigned int addr_offset)
-{
- unsigned int val = 0;
-
- val = *(volatile unsigned int *)(REG_ADDR_VCBUS(addr_offset));
- return val;
-}
-
-static int cvbs_write_vcbus(unsigned int addr_offset, unsigned int value)
-{
- *(volatile unsigned int *)REG_ADDR_VCBUS(addr_offset) = (value);
- return 0;
-}
-
-static int cvbs_set_vcbus_bits(unsigned int addr_offset, unsigned int value, unsigned int start, unsigned int len)
-{
- cvbs_write_vcbus(addr_offset, ((cvbs_read_vcbus(addr_offset) &
- ~(((1L << (len))-1) << (start))) |
- (((value)&((1L<<(len))-1)) << (start))));
- return 0;
-}
-#if 0
-static int cvbs_get_vcbus_bits(unsigned int addr_offset, unsigned int start, unsigned int len)
-{
- return (cvbs_read_vcbus(addr_offset) >> (start)) & ((1L << (len)) - 1);}
-#endif
-
-/*----------------------------------------------------------------------------*/
-// interface for cpu id checking
-
-static int check_cpu_type(unsigned int cpu_type)
-{
- return (cvbs_read_cbus(ASSIST_HW_REV)==cpu_type);
-}
-
-static bool inline is_equal_after_meson_cpu(unsigned int id)
-{
- return (get_cpu_id().family_id >= id)?1:0;
-}
-
-static bool inline is_meson_gxl_cpu(void)
-{
- return (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL)?
- 1:0;
-}
-
-static bool inline is_meson_gxlx_cpu(void)
-{
- return (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXLX)?
- 1:0;
-}
-
-static bool inline is_meson_g12a_cpu(void)
-{
- return (get_cpu_id().family_id ==
- MESON_CPU_MAJOR_ID_G12A) ? 1 : 0;
-}
-
-static inline bool is_meson_g12b_cpu(void)
-{
- return (get_cpu_id().family_id ==
- MESON_CPU_MAJOR_ID_G12B) ? 1 : 0;
-}
-
-static bool inline is_meson_txl_cpu(void)
-{
- return (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_TXL)?
- 1:0;
-}
-
-static bool inline is_meson_gxm_cpu(void)
-{
- return (get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXM)?
- 1:0;
-
-}
-static bool inline is_meson_gxl_package_905X(void)
-{
- return ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL) &&
- (get_cpu_id().package_id == MESON_CPU_PACKAGE_ID_905X))?
- 1:0;
-}
-
-static bool inline is_meson_gxl_package_905L(void)
-{
- return ((get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL) &&
- (get_cpu_id().package_id == MESON_CPU_PACKAGE_ID_905L))?
- 1:0;
-}
-
-/*----------------------------------------------------------------------------*/
-// configuration for enci bist
-int cvbs_set_bist(char* bist_mode)
-{
- if (!strcmp(bist_mode, "off"))
- {
- cvbs_write_vcbus(ENCI_VIDEO_MODE_ADV, 0x26);
- cvbs_write_vcbus(ENCI_TST_EN, 0x0);
- } else
- {
- unsigned int mode = 0;
-
- if (!strcmp(bist_mode, "fixval") || !strcmp(bist_mode, "0"))
- mode = 0;
- else if (!strcmp(bist_mode, "colorbar") || !strcmp(bist_mode, "1"))
- mode = 1;
- else if (!strcmp(bist_mode, "thinline") || !strcmp(bist_mode, "2"))
- mode = 2;
- else if (!strcmp(bist_mode, "dotgrid") || !strcmp(bist_mode, "3"))
- mode = 3;
-
- cvbs_write_vcbus(ENCI_VIDEO_MODE_ADV, 0x2);
- cvbs_write_vcbus(ENCI_TST_MDSEL, mode);
- cvbs_write_vcbus(ENCI_TST_CLRBAR_STRT, 0x112);
- cvbs_write_vcbus(ENCI_TST_CLRBAR_WIDTH, 0xb4);
- cvbs_write_vcbus(ENCI_TST_EN, 0x1);
- }
-
- return 0;
-}
-
-/*----------------------------------------------------------------------------*/
-// configuration for vdac pin of the soc.
-// config vdac path:
-// 0 : close
-// 1 : enci
-// 2 : atv
-// 3 : passthrough
-int cvbs_set_vdac(int status)
-{
- switch (status)
- {
- case 0:// close vdac
- cvbs_write_hiu(HHI_VDAC_CNTL0, 0);
- if (is_equal_after_meson_cpu(MESON_CPU_MAJOR_ID_TXL) &&
- !is_meson_gxlx_cpu() && !is_meson_g12a_cpu() &&
- !is_meson_g12b_cpu())
- cvbs_write_hiu(HHI_VDAC_CNTL1, 0);
- else
- cvbs_write_hiu(HHI_VDAC_CNTL1, 8);
- break;
- case 1:// from enci to vdac
- cvbs_set_vcbus_bits(VENC_VDAC_DACSEL0, 0, 5, 1);
- if (is_meson_g12a_cpu())
- cvbs_write_hiu(HHI_VDAC_CNTL0, 0x906001);
- else if (is_meson_g12b_cpu())
- cvbs_write_hiu(HHI_VDAC_CNTL0, 0x8f6001);
- else if (is_equal_after_meson_cpu(MESON_CPU_MAJOR_ID_GXL)) {
- if (is_equal_after_meson_cpu(MESON_CPU_MAJOR_ID_TXL) &&
- !is_meson_gxlx_cpu())
- cvbs_write_hiu(HHI_VDAC_CNTL0, 0x620001);
- else
- cvbs_write_hiu(HHI_VDAC_CNTL0, 0xb0001);
- } else
- cvbs_write_hiu(HHI_VDAC_CNTL0, 1);
-
- if (is_equal_after_meson_cpu(MESON_CPU_MAJOR_ID_TXL) &&
- !is_meson_gxlx_cpu() && !is_meson_g12a_cpu() &&
- !is_meson_g12b_cpu())
- cvbs_write_hiu(HHI_VDAC_CNTL1, 8);
- else
- cvbs_write_hiu(HHI_VDAC_CNTL1, 0);
- break;
- case 2:// from atv to vdac
- cvbs_set_vcbus_bits(VENC_VDAC_DACSEL0, 1, 5, 1);
- cvbs_write_hiu(HHI_VDAC_CNTL0, 1);
- cvbs_write_hiu(HHI_VDAC_CNTL1, 0);
- break;
- case 3:// from cvbs_in passthrough to cvbs_out with vdac disabled
- cvbs_write_hiu(HHI_VDAC_CNTL0, 0x400);
- cvbs_write_hiu(HHI_VDAC_CNTL1, 8);
- break;
- default:
- break;
- }
-
- return 0;
-}
-
-/*----------------------------------------------------------------------------*/
-// interface for debug
-static void cvbs_dump_cvbs_regs(void)
-{
- struct reg_s *p = NULL;
-
- if (VMODE_PAL == cvbs_mode) {
- // 576cvbs
- p = (struct reg_s*)&tvregs_576cvbs_enc[0];
-
- } else if (VMODE_NTSC == cvbs_mode) {
- // 480cvbs
- p = (struct reg_s*)&tvregs_480cvbs_enc[0];
- }
-
- if (NULL == p) {
- printf("it's not in cvbs mode!\n");
- return;
- }
-
- if (MREG_END_MARKER != p->reg)
- printf("cvbs enci registers:\n");
- while (MREG_END_MARKER != p->reg) {
- printf(" vcbus[0x%.2x] = 0x%.4x\n", p->reg, cvbs_read_vcbus(p->reg));
- p ++;
- }
-
- return;
-}
-
-unsigned int cvbs_clk_regs[] = {
- HHI_HDMI_PLL_CNTL0,
- HHI_HDMI_PLL_CNTL1,
- HHI_HDMI_PLL_CNTL2,
- HHI_HDMI_PLL_CNTL3,
- HHI_HDMI_PLL_CNTL4,
- HHI_HDMI_PLL_CNTL5,
- HHI_HDMI_PLL_CNTL6,
- HHI_VID_PLL_CLK_DIV,
- HHI_VIID_CLK_DIV,
- HHI_VIID_CLK_CNTL,
- HHI_VID_CLK_DIV,
- HHI_VID_CLK_CNTL2,
- MREG_END_MARKER
-};
-
-static void cvbs_dump_clock_regs(void)
-{
- unsigned int *p = &cvbs_clk_regs[0];
-
- if (MREG_END_MARKER != *p)
- printf("cvbs clock registers:\n");
- while (MREG_END_MARKER != *p) {
- printf(" hiu[0x%.2x] = 0x%.4x\n", *p, cvbs_read_hiu(*p));
- p ++;
- }
-
- return;
-}
-
-int cvbs_reg_debug(int argc, char* const argv[])
-{
- unsigned int addr, start, end, value;
-
- if (!strcmp(argv[1], "r"))
- {
- if (argc != 4)
- goto fail_cmd;
-
- addr = simple_strtoul(argv[3], NULL, 16);
- if (!strcmp(argv[2], "c"))
- printf("cvbs read cbus[0x%.2x] = 0x%.4x\n", addr, cvbs_read_cbus(addr));
- else if (!strcmp(argv[2], "h"))
- printf("cvbs read hiu[0x%.2x] = 0x%.4x\n", addr, cvbs_read_hiu(cvbs_get_hiu_logic_addr(addr)));
- else if (!strcmp(argv[2], "v"))
- printf("cvbs read vcbus[0x%.2x] = 0x%.4x\n", addr, cvbs_read_vcbus(addr));
- } else if (!strcmp(argv[1], "w")) {
- if (argc != 5)
- goto fail_cmd;
-
- addr = simple_strtoul(argv[4], NULL, 16);
- value = simple_strtoul(argv[2], NULL, 16);
- if (!strcmp(argv[3], "c")) {
- cvbs_write_cbus(addr, value);
- printf("cvbs write cbus[0x%.2x] = 0x%.4x\n", addr, cvbs_read_cbus(addr));
- } else if (!strcmp(argv[3], "h")) {
- cvbs_write_hiu(cvbs_get_hiu_logic_addr(addr), value);
- printf("cvbs write hiu[0x%.2x] = 0x%.4x\n", addr, cvbs_read_hiu(cvbs_get_hiu_logic_addr(addr)));
- } else if (!strcmp(argv[3], "v")) {
- cvbs_write_vcbus(addr, value);
- printf("cvbs write hiu[0x%.2x] = 0x%.4x\n", addr, cvbs_read_vcbus(addr));
- }
- } else if (!strcmp(argv[1], "dump")) {
- unsigned int i = 0;
- unsigned int type = 0xff;
-
- if (argc != 5)
- goto fail_cmd;
-
- if (!strcmp(argv[2], "h"))
- type = BUS_TYPE_CBUS;
- if (!strcmp(argv[2], "h"))
- type = BUS_TYPE_HIU;
- else if (!strcmp(argv[2], "v"))
- type = BUS_TYPE_VCBUS;
-
- if (type == 0xff)
- goto fail_cmd;
-
- start = simple_strtoul(argv[3], NULL, 16);
- end = simple_strtoul(argv[4], NULL, 16);
-
- if (type == BUS_TYPE_CBUS) {
- for (i=start; i<=end; i++)
- printf("cvbs read cbus[0x%.2x] = 0x%.4x\n", i, cvbs_read_cbus(i));
- } if (type == BUS_TYPE_HIU) {
- for (i=start; i<=end; i++)
- printf("cvbs read hiu[0x%.2x] = 0x%.4x\n", i, cvbs_read_hiu(cvbs_get_hiu_logic_addr(i)));
- } else if (type == BUS_TYPE_VCBUS) {
- for (i=start; i<=end; i++)
- printf("cvbs read vcbus[0x%.2x] = 0x%.4x\n", i, cvbs_read_vcbus(i));
- }
- } else if (!strcmp(argv[1], "clock")) {
- if (argc != 2)
- goto fail_cmd;
-
- cvbs_dump_clock_regs();
- } else if (!strcmp(argv[1], "enci")) {
- if (argc != 2)
- goto fail_cmd;
-
- cvbs_dump_cvbs_regs();
- } else if (!strcmp(argv[1], "set_clkpath")) {
- if (argc != 3)
- goto fail_cmd;
- value = simple_strtoul(argv[2], NULL, 0);
- if (check_cpu_type(MESON_CPU_MAJOR_ID_G12A) ||
- check_cpu_type(MESON_CPU_MAJOR_ID_G12B)) {
- if (value == 1 || value == 2 ||
- value == 3 || value == 0) {
- s_enci_clk_path = value;
- printf("path 0:vid_pll vid2_clk\n");
- printf("path 1:gp0_pll vid2_clk\n");
- printf("path 2:vid_pll vid1_clk\n");
- printf("path 3:gp0_pll vid1_clk\n");
- printf("you select path %d\n", s_enci_clk_path);
- } else {
- printf("invalid value, only 0/1/2/3\n");
- printf("bit[0]: 0=vid_pll, 1=gp0_pll\n");
- printf("bit[1]: 0=vid2_clk, 1=vid1_clk\n");
- }
- } else
- printf("only support G12A chip");
- }
-
- return 0;
-
-fail_cmd:
- return 1;
-}
-
-/*----------------------------------------------------------------------------*/
-// configuration for clock
-#define WAIT_FOR_PLL_LOCKED(reg) \
- do { \
- unsigned int pll_lock; \
- unsigned int time_out = 0; \
- do { \
- udelay(20); \
- pll_lock = cvbs_get_hiu_bits(reg, 31, 1); \
- time_out ++; \
- } while ((pll_lock == 0) && (time_out < 10000)); \
- if (pll_lock == 0) \
- printf("[error]: cvbs pll lock failed\n"); \
- } while(0);
-
-static void cvbs_config_hdmipll_gxl(void)
-{
-#if (defined(AML_MESON_GXL))
- printf("%s\n", __func__);
- cvbs_write_hiu(HHI_HDMI_PLL_CNTL, 0x4000027b);
- cvbs_write_hiu(HHI_HDMI_PLL_CNTL1, 0x800cb300);
- cvbs_write_hiu(HHI_HDMI_PLL_CNTL2, 0xa6212844);
- cvbs_write_hiu(HHI_HDMI_PLL_CNTL3, 0x0c4d000c);
- cvbs_write_hiu(HHI_HDMI_PLL_CNTL4, 0x001fa729);
- cvbs_write_hiu(HHI_HDMI_PLL_CNTL5, 0x01a31500);
- cvbs_set_hiu_bits(HHI_HDMI_PLL_CNTL, 0x1, 28, 1);
- cvbs_set_hiu_bits(HHI_HDMI_PLL_CNTL, 0x0, 28, 1);
- WAIT_FOR_PLL_LOCKED(HHI_HDMI_PLL_CNTL);
-#endif
- return;
-}
-
-static void cvbs_config_hdmipll_g12a(void)
-{
- printf("%s\n", __func__);
- cvbs_write_hiu(HHI_HDMI_PLL_CNTL0, 0x1a0504f7);
- cvbs_write_hiu(HHI_HDMI_PLL_CNTL1, 0x00010000);
- cvbs_write_hiu(HHI_HDMI_PLL_CNTL2, 0x00000000);
- cvbs_write_hiu(HHI_HDMI_PLL_CNTL3, 0x6a28dc00);
- cvbs_write_hiu(HHI_HDMI_PLL_CNTL4, 0x65771290);
- cvbs_write_hiu(HHI_HDMI_PLL_CNTL5, 0x39272000);
- cvbs_write_hiu(HHI_HDMI_PLL_CNTL6, 0x56540000);
- cvbs_write_hiu(HHI_HDMI_PLL_CNTL0, 0x3a0504f7);
- udelay(100);
- cvbs_write_hiu(HHI_HDMI_PLL_CNTL0, 0x1a0504f7);
- WAIT_FOR_PLL_LOCKED(HHI_HDMI_PLL_CNTL0);
- return;
-}
-
-static void cvbs_config_gp0pll_g12a(void)
-{
- printf("%s\n", __func__);
- cvbs_write_hiu(HHI_GP0_PLL_CNTL0, 0x180204f7);
- cvbs_write_hiu(HHI_GP0_PLL_CNTL1, 0x00010000);
- cvbs_write_hiu(HHI_GP0_PLL_CNTL2, 0x00000000);
- cvbs_write_hiu(HHI_GP0_PLL_CNTL3, 0x6a28dc00);
- cvbs_write_hiu(HHI_GP0_PLL_CNTL4, 0x65771290);
- cvbs_write_hiu(HHI_GP0_PLL_CNTL5, 0x39272000);
- cvbs_write_hiu(HHI_GP0_PLL_CNTL6, 0x56540000);
- cvbs_write_hiu(HHI_GP0_PLL_CNTL0, 0x380204f7);
- udelay(100);
- cvbs_write_hiu(HHI_GP0_PLL_CNTL0, 0x180204f7);
- WAIT_FOR_PLL_LOCKED(HHI_GP0_PLL_CNTL0);
- return;
-}
-
-static void cvbs_set_vid1_clk(unsigned int src_pll)
-{
- int sel = 0;
-
- printf("%s\n", __func__);
- if (src_pll == 0) { /* hpll */
- /* divider: 1 */
- /* Disable the div output clock */
- cvbs_set_hiu_bits(HHI_VID_PLL_CLK_DIV, 0, 19, 1);
- cvbs_set_hiu_bits(HHI_VID_PLL_CLK_DIV, 0, 15, 1);
-
- cvbs_set_hiu_bits(HHI_VID_PLL_CLK_DIV, 1, 18, 1);
- /* Enable the final output clock */
- cvbs_set_hiu_bits(HHI_VID_PLL_CLK_DIV, 1, 19, 1);
- sel = 0;
- } else { /* gp0_pll */
- sel = 1;
- }
-
- /* xd: 55 */
- /* setup the XD divider value */
- cvbs_set_hiu_bits(HHI_VID_CLK_DIV, (55 - 1), VCLK_XD0, 8);
- //udelay(5);
- /*0x59[16]/0x5f[19]/0x5f[20]*/
- cvbs_set_hiu_bits(HHI_VID_CLK_CNTL, sel, VCLK_CLK_IN_SEL, 3);
- cvbs_set_hiu_bits(HHI_VID_CLK_CNTL, 1, VCLK_EN0, 1);
- //udelay(2);
-
- /* vclk: 27M */
- /* [31:28]=0 enci_clk_sel, select vclk_div1 */
- cvbs_set_hiu_bits(HHI_VID_CLK_DIV, 0, 28, 4);
- cvbs_set_hiu_bits(HHI_VIID_CLK_DIV, 0, 28, 4);
- /* release vclk_div_reset and enable vclk_div */
- cvbs_set_hiu_bits(HHI_VID_CLK_DIV, 1, VCLK_XD_EN, 2);
- //udelay(5);
-
- cvbs_set_hiu_bits(HHI_VID_CLK_CNTL, 1, VCLK_DIV1_EN, 1);
-
- cvbs_set_hiu_bits(HHI_VID_CLK_CNTL, 1, VCLK_SOFT_RST, 1);
- //udelay(10);
- cvbs_set_hiu_bits(HHI_VID_CLK_CNTL, 0, VCLK_SOFT_RST, 1);
- //udelay(5);
-}
-
-static void cvbs_set_vid2_clk(unsigned int src_pll)
-{
- int sel = 0;
-
- printf("%s\n", __func__);
- if (src_pll == 0) { /* hpll */
- /* divider: 1 */
- /* Disable the div output clock */
- cvbs_set_hiu_bits(HHI_VID_PLL_CLK_DIV, 0, 19, 1);
- cvbs_set_hiu_bits(HHI_VID_PLL_CLK_DIV, 0, 15, 1);
-
- cvbs_set_hiu_bits(HHI_VID_PLL_CLK_DIV, 1, 18, 1);
- /* Enable the final output clock */
- cvbs_set_hiu_bits(HHI_VID_PLL_CLK_DIV, 1, 19, 1);
- sel = 0;
- } else { /* gp0_pll */
- sel = 1;
- }
-
- /* xd: 55 */
- /* setup the XD divider value */
- cvbs_set_hiu_bits(HHI_VIID_CLK_DIV, (55 - 1), VCLK2_XD, 8);
- //udelay(5);
- /* Bit[18:16] - v2_cntl_clk_in_sel: vid_pll */
- cvbs_set_hiu_bits(HHI_VIID_CLK_CNTL, sel, VCLK2_CLK_IN_SEL, 3);
- cvbs_set_hiu_bits(HHI_VIID_CLK_CNTL, 1, VCLK2_EN, 1);
- //udelay(2);
-
- /* vclk: 27M */
- /* [31:28]=8 enci_clk_sel, select vclk2_div1 */
- cvbs_set_hiu_bits(HHI_VID_CLK_DIV, 8, 28, 4);
- cvbs_set_hiu_bits(HHI_VIID_CLK_DIV, 8, 28, 4);
- /* release vclk2_div_reset and enable vclk2_div */
- cvbs_set_hiu_bits(HHI_VIID_CLK_DIV, 1, VCLK2_XD_EN, 2);
- //udelay(5);
-
- cvbs_set_hiu_bits(HHI_VIID_CLK_CNTL, 1, VCLK2_DIV1_EN, 1);
- cvbs_set_hiu_bits(HHI_VIID_CLK_CNTL, 1, VCLK2_SOFT_RST, 1);
- //udelay(10);
- cvbs_set_hiu_bits(HHI_VIID_CLK_CNTL, 0, VCLK2_SOFT_RST, 1);
- //udelay(5);
-}
-
-static int cvbs_config_clock(void)
-{
- /* pll output 1485M */
- if (check_cpu_type(MESON_CPU_MAJOR_ID_G12A) ||
- check_cpu_type(MESON_CPU_MAJOR_ID_G12B)) {
- if (s_enci_clk_path & 0x1)
- cvbs_config_gp0pll_g12a();
- else
- cvbs_config_hdmipll_g12a();
- }
- else if (is_equal_after_meson_cpu(MESON_CPU_MAJOR_ID_GXL))
- cvbs_config_hdmipll_gxl();
-
- if (check_cpu_type(MESON_CPU_MAJOR_ID_G12A) ||
- check_cpu_type(MESON_CPU_MAJOR_ID_G12B)) {
- if (s_enci_clk_path & 0x2)
- cvbs_set_vid1_clk(s_enci_clk_path & 0x1);
- else
- cvbs_set_vid2_clk(s_enci_clk_path & 0x1);
- } else {
- cvbs_set_vid2_clk(0);
- }
-
- cvbs_set_hiu_bits(HHI_VID_CLK_CNTL2, 1, 0, 1);
- cvbs_set_hiu_bits(HHI_VID_CLK_CNTL2, 1, 4, 1);
-
- return 0;
-}
-
-/*----------------------------------------------------------------------------*/
-// configuration for enci
-static void cvbs_write_vcbus_array(struct reg_s *s)
-{
- if (s == NULL)
- return ;
-
- while (s && (MREG_END_MARKER != s->reg))
- {
- cvbs_write_vcbus(s->reg, s->val);
- //printf("reg[0x%.2x] = 0x%.4x\n", s->reg, s->val);
- s ++;
- }
- return ;
-}
-
-#ifdef AML_CVBS_PERFORMANCE_COMPATIBILITY_SUPPORT
-
-void cvbs_performance_config(void)
-{
- int actived = AML_CVBS_PERFORMANCE_ACTIVED;
- char buf[32];
-
- sprintf(buf, "setenv cvbs_drv %d", actived);
- run_command(buf, 0);
-
- return ;
-}
-
-static void cvbs_performance_enhancement(int mode)
-{
- unsigned int index = AML_CVBS_PERFORMANCE_ACTIVED;
- unsigned int max = 0;
- unsigned int type = 0;
- const struct reg_s *s = NULL;
-
- if (VMODE_PAL != mode && VMODE_PAL_M != mode && VMODE_PAL_N != mode)
- return;
-
- if (0xff == index)
- return;
-
- if (check_cpu_type(MESON_CPU_MAJOR_ID_M8B)) {
- max = sizeof(tvregs_576cvbs_performance_m8b)
- / sizeof(struct reg_s *);
- index = (index >= max) ? 0 : index;
- s = tvregs_576cvbs_performance_m8b[index];
- type = 1;
- } else if (check_cpu_type(MESON_CPU_MAJOR_ID_M8M2)) {
- max = sizeof(tvregs_576cvbs_performance_m8m2)
- / sizeof(struct reg_s *);
- index = (index >= max) ? 0 : index;
- s = tvregs_576cvbs_performance_m8m2[index];
- type = 2;
- } else if (check_cpu_type(MESON_CPU_MAJOR_ID_M8)) {
- max = sizeof(tvregs_576cvbs_performance_m8)
- / sizeof(struct reg_s *);
- index = (index >= max) ? 0 : index;
- s = tvregs_576cvbs_performance_m8[index];
- type = 3;
- } else if (check_cpu_type(MESON_CPU_MAJOR_ID_GXBB)) {
- max = sizeof(tvregs_576cvbs_performance_gxbb)
- / sizeof(struct reg_s *);
- index = (index >= max) ? 0 : index;
- s = tvregs_576cvbs_performance_gxbb[index];
- type = 4;
- } else if (check_cpu_type(MESON_CPU_MAJOR_ID_GXTVBB)) {
- max = sizeof(tvregs_576cvbs_performance_gxtvbb)
- / sizeof(struct reg_s *);
- index = (index >= max) ? 0 : index;
- s = tvregs_576cvbs_performance_gxtvbb[index];
- type = 5;
- } else if (is_meson_g12a_cpu() || is_meson_g12b_cpu()) {
- max = sizeof(tvregs_576cvbs_performance_g12a)
- / sizeof(struct reg_s *);
- index = (index >= max) ? 0 : index;
- s = tvregs_576cvbs_performance_g12a[index];
- type = 9;
- } else if (is_meson_gxlx_cpu()) {
- max = sizeof(tvregs_576cvbs_performance_905l)
- / sizeof(struct reg_s *);
- index = (index >= max) ? 0 : index;
- s = tvregs_576cvbs_performance_905l[index];
- type = 7;
- } else if (is_equal_after_meson_cpu(MESON_CPU_MAJOR_ID_TXL)) {
- max = sizeof(tvregs_576cvbs_performance_txl)
- / sizeof(struct reg_s *);
- index = (index >= max) ? 0 : index;
- s = tvregs_576cvbs_performance_txl[index];
- type = 8;
- } else if (is_equal_after_meson_cpu(MESON_CPU_MAJOR_ID_GXL)) {
- if (is_meson_gxl_package_905L()) {
- max = sizeof(tvregs_576cvbs_performance_905l)
- / sizeof(struct reg_s *);
- index = (index >= max) ? 0 : index;
- s = tvregs_576cvbs_performance_905l[index];
- type = 7;
- } else {
- max = sizeof(tvregs_576cvbs_performance_905x)
- / sizeof(struct reg_s *);
- index = (index >= max) ? 0 : index;
- s = tvregs_576cvbs_performance_905x[index];
- type = 6;
- }
- }
-
- printf("cvbs performance type = %d, table = %d\n", type, index);
- cvbs_write_vcbus_array((struct reg_s*)s);
-
- return;
-}
-
-#endif
-
-static int cvbs_config_enci(int vmode)
-{
- if (VMODE_PAL == vmode)
- cvbs_write_vcbus_array((struct reg_s*)&tvregs_576cvbs_enc[0]);
- else if (VMODE_NTSC == vmode)
- cvbs_write_vcbus_array((struct reg_s*)&tvregs_480cvbs_enc[0]);
- else if (VMODE_NTSC_M == vmode)
- cvbs_write_vcbus_array((struct reg_s*)&tvregs_480cvbs_enc[0]);
- else if (VMODE_PAL_M == vmode)
- cvbs_write_vcbus_array((struct reg_s*)&tvregs_pal_m_enc[0]);
- else if (VMODE_PAL_N == vmode)
- cvbs_write_vcbus_array((struct reg_s*)&tvregs_pal_n_enc[0]);
-
- cvbs_performance_enhancement(vmode);
-
- return 0;
-}
-
-/*----------------------------------------------------------------------------*/
-// configuration for output
-// output vmode: 576cvbs, 480cvbs
-int cvbs_set_vmode(char* vmode_name)
-{
- if (!strncmp(vmode_name, "576cvbs", strlen("576cvbs"))) {
- cvbs_mode = VMODE_PAL;
- cvbs_config_enci(0);
- cvbs_config_clock();
- cvbs_set_vdac(1);
- return 0;
- } else if (!strncmp(vmode_name, "480cvbs", strlen("480cvbs"))) {
- cvbs_mode = VMODE_NTSC;
- cvbs_config_enci(1);
- cvbs_config_clock();
- cvbs_set_vdac(1);
- return 0;
- } else if (!strncmp(vmode_name, "ntsc_m", strlen("ntsc_m"))) {
- cvbs_mode = VMODE_NTSC_M;
- cvbs_config_enci(VMODE_NTSC_M);
- cvbs_config_clock();
- cvbs_set_vdac(1);
- return 0;
- } else if (!strncmp(vmode_name, "pal_m", strlen("pal_m"))) {
- cvbs_mode = VMODE_PAL_M;
- cvbs_config_enci(VMODE_PAL_M);
- cvbs_config_clock();
- cvbs_set_vdac(1);
- return 0;
- } else if (!strncmp(vmode_name, "pal_n", strlen("pal_n"))) {
- cvbs_mode = VMODE_PAL_N;
- cvbs_config_enci(VMODE_PAL_N);
- cvbs_config_clock();
- cvbs_set_vdac(1);
- return 0;
- } else {
- printf("[%s] is invalid for cvbs.\n", vmode_name);
- return -1;
- }
-
- return 0;
-}
-
-/*----------------------------------------------------------------------------*/
-// check for valid video mode
-int cvbs_outputmode_check(char *vmode_name)
-{
- if ((!strncmp(vmode_name, "576cvbs", strlen("576cvbs"))) ||
- (!strncmp(vmode_name, "480cvbs", strlen("480cvbs"))) ||
- (!strncmp(vmode_name, "ntsc_m", strlen("ntsc_m"))) ||
- (!strncmp(vmode_name, "pal_m", strlen("pal_m"))) ||
- (!strncmp(vmode_name, "pal_n", strlen("pal_n")))) {
- return 0;
- }
-
- printf("cvbs: outputmode[%s] is invalid\n", vmode_name);
- return -1;
-}
-
-/*----------------------------------------------------------------------------*/
-// list for valid video mode
-void cvbs_show_valid_vmode(void)
-{
- printf("576cvbs\n""480cvbs\n""ntsc_m\n""pal_m\n""pal_n\n");
- return;
-}
-
-void cvbs_init(void)
-{
-#ifdef AML_CVBS_PERFORMANCE_COMPATIBILITY_SUPPORT
- cvbs_performance_config();
-#endif
-
- return;
-}
-
diff --git a/drivers/amlogic/media/vout/cvbs/aml_cvbs_config.h b/drivers/amlogic/media/vout/cvbs/aml_cvbs_config.h
deleted file mode 100644
index a5dc225..0000000
--- a/drivers/amlogic/media/vout/cvbs/aml_cvbs_config.h
+++ /dev/null
@@ -1,507 +0,0 @@
-/*
- * drivers/display/vout/aml_cvbs_config.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
-*/
-#include <amlogic/media/vout/aml_cvbs.h>
-#include "aml_cvbs_regs.h"
-
-struct reg_s {
- unsigned int reg;
- unsigned int val;
-};
-
-#define MREG_END_MARKER 0xFFFF
-
-#ifdef AML_CVBS_PERFORMANCE_COMPATIBILITY_SUPPORT
-static const struct reg_s tvregs_576cvbs_china_sarft_m8[] = {
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_576cvbs_china_telecom_m8[] = {
- {ENCI_SYNC_ADJ, 0x8060 },
- {ENCI_VIDEO_SAT, 0xfe },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_576cvbs_china_mobile_m8[] = {
- {ENCI_SYNC_ADJ, 0x8060 },
- {ENCI_VIDEO_SAT, 0xfe },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s *tvregs_576cvbs_performance_m8[] = {
- tvregs_576cvbs_china_sarft_m8,
- tvregs_576cvbs_china_telecom_m8,
- tvregs_576cvbs_china_mobile_m8
-};
-
-static const struct reg_s tvregs_576cvbs_china_sarft_m8m2[] = {
- {ENCI_YC_DELAY, 0x343 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_576cvbs_china_telecom_m8m2[] = {
- {ENCI_YC_DELAY, 0x343 },
- {ENCI_SYNC_ADJ, 0x8080 },
- {ENCI_VIDEO_SAT, 0xfd },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_576cvbs_china_mobile_m8m2[] = {
- {ENCI_YC_DELAY, 0x343 },
- {ENCI_SYNC_ADJ, 0x8080 },
- {ENCI_VIDEO_SAT, 0xfd },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s *tvregs_576cvbs_performance_m8m2[] = {
- tvregs_576cvbs_china_sarft_m8m2,
- tvregs_576cvbs_china_telecom_m8m2,
- tvregs_576cvbs_china_mobile_m8m2
-};
-
-static const struct reg_s tvregs_576cvbs_china_sarft_m8b[] = {
- {ENCI_YC_DELAY, 0x343 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_576cvbs_china_telecom_m8b[] = {
- {ENCI_YC_DELAY, 0x343 },
- {ENCI_SYNC_ADJ, 0x8080 },
- {ENCI_VIDEO_SAT, 0xfd },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_576cvbs_china_mobile_m8b[] = {
- {ENCI_YC_DELAY, 0x343 },
- {ENCI_SYNC_ADJ, 0x8080 },
- {ENCI_VIDEO_SAT, 0xfd },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s *tvregs_576cvbs_performance_m8b[] = {
- tvregs_576cvbs_china_sarft_m8b,
- tvregs_576cvbs_china_telecom_m8b,
- tvregs_576cvbs_china_mobile_m8b
-};
-
-static const struct reg_s tvregs_576cvbs_china_sarft_gxbb[] = {
- {VENC_VDAC_DAC0_GAINCTRL, 0x9 },
- {ENCI_YC_DELAY, 0x343},
- {ENCI_VIDEO_SAT, 0x9 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_576cvbs_china_telecom_gxbb[] = {
- {VENC_VDAC_DAC0_GAINCTRL, 0x9 },
- {ENCI_YC_DELAY, 0x343 },
- {ENCI_SYNC_ADJ, 0x8080 },
- {ENCI_VIDEO_SAT, 0xfd },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_576cvbs_china_mobile_gxbb[] = {
- {VENC_VDAC_DAC0_GAINCTRL, 0x9 },
- {ENCI_YC_DELAY, 0x343 },
- {ENCI_SYNC_ADJ, 0x8080 },
- {ENCI_VIDEO_SAT, 0xfd },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s *tvregs_576cvbs_performance_gxbb[] = {
- tvregs_576cvbs_china_sarft_gxbb,
- tvregs_576cvbs_china_telecom_gxbb,
- tvregs_576cvbs_china_mobile_gxbb
-};
-
-static const struct reg_s tvregs_576cvbs_china_sarft_gxtvbb[] = {
- {ENCI_YC_DELAY, 0x333 },
- {ENCI_VIDEO_SAT, 0xfb },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xff42 },
- {ENCI_SYNC_ADJ, 0x8c00 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_576cvbs_china_telecom_gxtvbb[] = {
- {ENCI_YC_DELAY, 0x333 },
- {ENCI_VIDEO_SAT, 0xfb },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xff42 },
- {ENCI_SYNC_ADJ, 0x8c00 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_576cvbs_china_mobile_gxtvbb[] = {
- {ENCI_YC_DELAY, 0x333 },
- {ENCI_VIDEO_SAT, 0xfb },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xff42 },
- {ENCI_SYNC_ADJ, 0x8c00 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s *tvregs_576cvbs_performance_gxtvbb[] = {
- tvregs_576cvbs_china_sarft_gxtvbb,
- tvregs_576cvbs_china_telecom_gxtvbb,
- tvregs_576cvbs_china_mobile_gxtvbb
-};
-
-static const struct reg_s tvregs_576cvbs_china_sarft_905x[] = {
- {VENC_VDAC_DAC0_GAINCTRL, 0x9 },
- {ENCI_YC_DELAY, 0x343},
- {ENCI_VIDEO_SAT, 0x9 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_576cvbs_china_telecom_905x[] = {
- {VENC_VDAC_DAC0_GAINCTRL, 0x9 },
- {ENCI_YC_DELAY, 0x343 },
- {ENCI_SYNC_ADJ, 0x8080 },
- {ENCI_VIDEO_SAT, 0xfd },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xf752 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_576cvbs_china_mobile_905x[] = {
- {VENC_VDAC_DAC0_GAINCTRL, 0x9 },
- {ENCI_YC_DELAY, 0x343 },
- {ENCI_SYNC_ADJ, 0x8080 },
- {ENCI_VIDEO_SAT, 0xfd },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xf752 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s *tvregs_576cvbs_performance_905x[] = {
- tvregs_576cvbs_china_sarft_905x,
- tvregs_576cvbs_china_telecom_905x,
- tvregs_576cvbs_china_mobile_905x
-};
-
-static const struct reg_s tvregs_576cvbs_china_sarft_905l[] = {
- {VENC_VDAC_DAC0_GAINCTRL, 0x9 },
- {ENCI_YC_DELAY, 0x343 },
- {ENCI_SYNC_ADJ, 0x0 },
- {ENCI_VIDEO_SAT, 0x9 },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_576cvbs_china_telecom_905l[] = {
- {VENC_VDAC_DAC0_GAINCTRL, 0x9 },
- {ENCI_YC_DELAY, 0x333 },
- {ENCI_SYNC_ADJ, 0x8080 },
- {ENCI_VIDEO_SAT, 0xfd },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_576cvbs_china_mobile_905l[] = {
- {VENC_VDAC_DAC0_GAINCTRL, 0x9 },
- {ENCI_YC_DELAY, 0x343 },
- {ENCI_SYNC_ADJ, 0x8080 },
- {ENCI_VIDEO_SAT, 0xfd },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s *tvregs_576cvbs_performance_905l[] = {
- tvregs_576cvbs_china_sarft_905l,
- tvregs_576cvbs_china_telecom_905l,
- tvregs_576cvbs_china_mobile_905l
-};
-
-static const struct reg_s tvregs_576cvbs_china_sarft_txl[] = {
- {ENCI_YC_DELAY, 0x333 },
- {ENCI_VIDEO_SAT, 0xf4 },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 },
- {ENCI_SYNC_ADJ, 0x8c00 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_576cvbs_china_telecom_txl[] = {
- {ENCI_YC_DELAY, 0x333 },
- {ENCI_VIDEO_SAT, 0xf4 },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 },
- {ENCI_SYNC_ADJ, 0x8c00 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_576cvbs_china_mobile_txl[] = {
- {ENCI_YC_DELAY, 0x333 },
- {ENCI_VIDEO_SAT, 0xf4 },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 },
- {ENCI_SYNC_ADJ, 0x8c00 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s *tvregs_576cvbs_performance_txl[] = {
- tvregs_576cvbs_china_sarft_txl,
- tvregs_576cvbs_china_telecom_txl,
- tvregs_576cvbs_china_mobile_txl
-};
-
-static const struct reg_s tvregs_576cvbs_china_sarft_g12a[] = {
- {VENC_VDAC_DAC0_GAINCTRL, 0x9 },
- {ENCI_YC_DELAY, 0x333 },
- {ENCI_SYNC_ADJ, 0x0 },
- {ENCI_VIDEO_SAT, 0x9 },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_576cvbs_china_telecom_g12a[] = {
- {VENC_VDAC_DAC0_GAINCTRL, 0x9 },
- {ENCI_YC_DELAY, 0x333 },
- {ENCI_SYNC_ADJ, 0x8080 },
- {ENCI_VIDEO_SAT, 0xfd },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_576cvbs_china_mobile_g12a[] = {
- {VENC_VDAC_DAC0_GAINCTRL, 0x9 },
- {ENCI_YC_DELAY, 0x333 },
- {ENCI_SYNC_ADJ, 0x8080 },
- {ENCI_VIDEO_SAT, 0xfd },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_576cvbs_china_mobile_g12a_revB[] = {
- {VENC_VDAC_DAC0_GAINCTRL, 0x9 },
- {ENCI_YC_DELAY, 0x546 },
- {ENCI_SYNC_ADJ, 0x8080 },
- {ENCI_VIDEO_SAT, 0x9 },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xf850 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s *tvregs_576cvbs_performance_g12a[] = {
- tvregs_576cvbs_china_sarft_g12a,
- tvregs_576cvbs_china_telecom_g12a,
- tvregs_576cvbs_china_mobile_g12a,
- tvregs_576cvbs_china_mobile_g12a_revB
-};
-
-#endif
-
-static const struct reg_s tvregs_576cvbs_enc[] = {
- {ENCI_CFILT_CTRL, 0x12, },
- {ENCI_CFILT_CTRL2, 0x12, },
- {VENC_DVI_SETTING, 0, },
- {ENCI_VIDEO_MODE, 0, },
- {ENCI_VIDEO_MODE_ADV, 0, },
- {ENCI_SYNC_HSO_BEGIN, 3, },
- {ENCI_SYNC_HSO_END, 129, },
- {ENCI_SYNC_VSO_EVNLN, 0x0003 },
- {ENCI_SYNC_VSO_ODDLN, 0x0104 },
- {ENCI_MACV_MAX_AMP, 0x8107 },
- {VENC_VIDEO_PROG_MODE, 0xff },
- {ENCI_VIDEO_MODE, 0x13 },
- {ENCI_VIDEO_MODE_ADV, 0x26, },
- {ENCI_VIDEO_SCH, 0x28, },
- {ENCI_SYNC_MODE, 0x07, },
- {ENCI_YC_DELAY, 0x333, },
- {ENCI_VFIFO2VD_PIXEL_START, 0x0fb },
- {ENCI_VFIFO2VD_PIXEL_END, 0x069b },
- {ENCI_VFIFO2VD_LINE_TOP_START, 0x0016 },
- {ENCI_VFIFO2VD_LINE_TOP_END, 0x0136 },
- {ENCI_VFIFO2VD_LINE_BOT_START, 0x0017 },
- {ENCI_VFIFO2VD_LINE_BOT_END, 0x0137 },
- {VENC_SYNC_ROUTE, 0, },
- {ENCI_DBG_PX_RST, 0, },
- {VENC_INTCTRL, 0x2, },
- {ENCI_VFIFO2VD_CTL, 0x4e01, },
- {VENC_VDAC_SETTING, 0, },
- {VENC_UPSAMPLE_CTRL0, 0x0061, },
- {VENC_UPSAMPLE_CTRL1, 0x4061, },
- {VENC_UPSAMPLE_CTRL2, 0x5061, },
- {VENC_VDAC_DACSEL0, 0x0000, },
- {VENC_VDAC_DACSEL1, 0x0000, },
- {VENC_VDAC_DACSEL2, 0x0000, },
- {VENC_VDAC_DACSEL3, 0x0000, },
- {VENC_VDAC_DACSEL4, 0x0000, },
- {VENC_VDAC_DACSEL5, 0x0000, },
- {VPU_VIU_VENC_MUX_CTRL, 0x0005, },
- {VENC_VDAC_FIFO_CTRL, 0x2000, },
- {ENCI_DACSEL_0, 0x0011 },
- {ENCI_DACSEL_1, 0x11 },
- {ENCI_VIDEO_EN, 1, },
- {ENCI_VIDEO_SAT, 0x7 },
- {VENC_VDAC_DAC0_FILT_CTRL0, 0x1 },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 },
- {ENCI_MACV_N0, 0x0 },
- {ENCI_VIDEO_CONT, 0x0 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_480cvbs_enc[] = {
- {ENCI_CFILT_CTRL, 0x12, },
- {ENCI_CFILT_CTRL2, 0x12, },
- {VENC_DVI_SETTING, 0, },
- {ENCI_VIDEO_MODE, 0, },
- {ENCI_VIDEO_MODE_ADV, 0, },
- {ENCI_SYNC_HSO_BEGIN, 5, },
- {ENCI_SYNC_HSO_END, 129, },
- {ENCI_SYNC_VSO_EVNLN, 0x0003 },
- {ENCI_SYNC_VSO_ODDLN, 0x0104 },
- {ENCI_MACV_MAX_AMP, 0x810b },
- {VENC_VIDEO_PROG_MODE, 0xf0 },
- {ENCI_VIDEO_MODE, 0x08 },
- {ENCI_VIDEO_MODE_ADV, 0x26, },
- {ENCI_VIDEO_SCH, 0x20, },
- {ENCI_SYNC_MODE, 0x07, },
- {ENCI_YC_DELAY, 0x333, },
- {ENCI_VFIFO2VD_PIXEL_START, 0xe3, },
- {ENCI_VFIFO2VD_PIXEL_END, 0x0683, },
- {ENCI_VFIFO2VD_LINE_TOP_START, 0x12, },
- {ENCI_VFIFO2VD_LINE_TOP_END, 0x102, },
- {ENCI_VFIFO2VD_LINE_BOT_START, 0x13, },
- {ENCI_VFIFO2VD_LINE_BOT_END, 0x103, },
- {VENC_SYNC_ROUTE, 0, },
- {ENCI_DBG_PX_RST, 0, },
- {VENC_INTCTRL, 0x2, },
- {ENCI_VFIFO2VD_CTL, 0x4e01, },
- {VENC_VDAC_SETTING, 0, },
- {VENC_UPSAMPLE_CTRL0, 0x0061, },
- {VENC_UPSAMPLE_CTRL1, 0x4061, },
- {VENC_UPSAMPLE_CTRL2, 0x5061, },
- {VENC_VDAC_DACSEL0, 0x0000, },
- {VENC_VDAC_DACSEL1, 0x0000, },
- {VENC_VDAC_DACSEL2, 0x0000, },
- {VENC_VDAC_DACSEL3, 0x0000, },
- {VENC_VDAC_DACSEL4, 0x0000, },
- {VENC_VDAC_DACSEL5, 0x0000, },
- {VPU_VIU_VENC_MUX_CTRL, 0x0005, },
- {VENC_VDAC_FIFO_CTRL, 0x2000, },
- {ENCI_DACSEL_0, 0x0011 },
- {ENCI_DACSEL_1, 0x11 },
- {ENCI_VIDEO_EN, 1, },
- {ENCI_VIDEO_SAT, 0x12 },
- {VENC_VDAC_DAC0_FILT_CTRL0, 0x1 },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 },
- {ENCI_MACV_N0, 0x0 },
- {ENCI_SYNC_ADJ, 0x9c00 },
- {ENCI_VIDEO_CONT, 0x3 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_pal_m_enc[] = {
- {ENCI_CFILT_CTRL, 0x12, },
- {ENCI_CFILT_CTRL2, 0x12, },
- {VENC_DVI_SETTING, 0, },
- {ENCI_VIDEO_MODE, 0, },
- {ENCI_VIDEO_MODE_ADV, 0, },
- {ENCI_SYNC_HSO_BEGIN, 5, },
- {ENCI_SYNC_HSO_END, 129, },
- {ENCI_SYNC_VSO_EVNLN, 0x0003 },
- {ENCI_SYNC_VSO_ODDLN, 0x0104 },
- {ENCI_MACV_MAX_AMP, 0x810b },
- {VENC_VIDEO_PROG_MODE, 0xf0 },
- {ENCI_VIDEO_MODE, 0x2a },
- {ENCI_VIDEO_MODE_ADV, 0x26, },
- {ENCI_VIDEO_SCH, 0x20, },
- {ENCI_SYNC_MODE, 0x07, },
- {ENCI_YC_DELAY, 0x333, },
- {ENCI_VFIFO2VD_PIXEL_START, 0xe3, },
- {ENCI_VFIFO2VD_PIXEL_END, 0x0683,},
- {ENCI_VFIFO2VD_LINE_TOP_START, 0x12, },
- {ENCI_VFIFO2VD_LINE_TOP_END, 0x102, },
- {ENCI_VFIFO2VD_LINE_BOT_START, 0x13, },
- {ENCI_VFIFO2VD_LINE_BOT_END, 0x103, },
- {VENC_SYNC_ROUTE, 0, },
- {ENCI_DBG_PX_RST, 0, },
- {VENC_INTCTRL, 0x2, },
- {ENCI_VFIFO2VD_CTL, 0x4e01,},
- {VENC_VDAC_SETTING, 0, },
- {VENC_UPSAMPLE_CTRL0, 0x0061,},
- {VENC_UPSAMPLE_CTRL1, 0x4061,},
- {VENC_UPSAMPLE_CTRL2, 0x5061,},
- {VENC_VDAC_DACSEL0, 0x0000,},
- {VENC_VDAC_DACSEL1, 0x0000,},
- {VENC_VDAC_DACSEL2, 0x0000,},
- {VENC_VDAC_DACSEL3, 0x0000,},
- {VENC_VDAC_DACSEL4, 0x0000,},
- {VENC_VDAC_DACSEL5, 0x0000,},
- {VPU_VIU_VENC_MUX_CTRL, 0x0005,},
- {VENC_VDAC_FIFO_CTRL, 0x2000,},
- {ENCI_DACSEL_0, 0x0011 },
- {ENCI_DACSEL_1, 0x11 },
- {ENCI_VIDEO_EN, 1, },
- {ENCI_VIDEO_SAT, 0x12 },
- {VENC_VDAC_DAC0_FILT_CTRL0, 0x1 },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 },
- {ENCI_MACV_N0, 0x0 },
- {ENCI_SYNC_ADJ, 0x9c00 },
- {ENCI_VIDEO_CONT, 0x3 },
- {MREG_END_MARKER, 0 }
-};
-
-static const struct reg_s tvregs_pal_n_enc[] = {
- {ENCI_CFILT_CTRL, 0x12, },
- {ENCI_CFILT_CTRL2, 0x12, },
- {VENC_DVI_SETTING, 0, },
- {ENCI_VIDEO_MODE, 0, },
- {ENCI_VIDEO_MODE_ADV, 0, },
- {ENCI_SYNC_HSO_BEGIN, 3, },
- {ENCI_SYNC_HSO_END, 129, },
- {ENCI_SYNC_VSO_EVNLN, 0x0003 },
- {ENCI_SYNC_VSO_ODDLN, 0x0104 },
- {ENCI_MACV_MAX_AMP, 0x8107 },
- {VENC_VIDEO_PROG_MODE, 0xff },
- {ENCI_VIDEO_MODE, 0x3b },
- {ENCI_VIDEO_MODE_ADV, 0x26, },
- {ENCI_VIDEO_SCH, 0x28, },
- {ENCI_SYNC_MODE, 0x07, },
- {ENCI_YC_DELAY, 0x333, },
- {ENCI_VFIFO2VD_PIXEL_START, 0x0fb },
- {ENCI_VFIFO2VD_PIXEL_END, 0x069b },
- {ENCI_VFIFO2VD_LINE_TOP_START, 0x0016 },
- {ENCI_VFIFO2VD_LINE_TOP_END, 0x0136 },
- {ENCI_VFIFO2VD_LINE_BOT_START, 0x0017 },
- {ENCI_VFIFO2VD_LINE_BOT_END, 0x0137 },
- {VENC_SYNC_ROUTE, 0, },
- {ENCI_DBG_PX_RST, 0, },
- {VENC_INTCTRL, 0x2, },
- {ENCI_VFIFO2VD_CTL, 0x4e01, },
- {VENC_VDAC_SETTING, 0, },
- {VENC_UPSAMPLE_CTRL0, 0x0061, },
- {VENC_UPSAMPLE_CTRL1, 0x4061, },
- {VENC_UPSAMPLE_CTRL2, 0x5061, },
- {VENC_VDAC_DACSEL0, 0x0000, },
- {VENC_VDAC_DACSEL1, 0x0000, },
- {VENC_VDAC_DACSEL2, 0x0000, },
- {VENC_VDAC_DACSEL3, 0x0000, },
- {VENC_VDAC_DACSEL4, 0x0000, },
- {VENC_VDAC_DACSEL5, 0x0000, },
- {VPU_VIU_VENC_MUX_CTRL, 0x0005, },
- {VENC_VDAC_FIFO_CTRL, 0x2000, },
- {ENCI_DACSEL_0, 0x0011 },
- {ENCI_DACSEL_1, 0x11 },
- {ENCI_VIDEO_EN, 1, },
- {ENCI_VIDEO_SAT, 0x7 },
- {VENC_VDAC_DAC0_FILT_CTRL0, 0x1 },
- {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 },
- {ENCI_MACV_N0, 0x0 },
- {ENCI_VIDEO_CONT, 0x0 },
- {MREG_END_MARKER, 0 }
-};
-
diff --git a/drivers/amlogic/media/vout/cvbs/aml_cvbs_regs.h b/drivers/amlogic/media/vout/cvbs/aml_cvbs_regs.h
deleted file mode 100644
index 19f3882..0000000
--- a/drivers/amlogic/media/vout/cvbs/aml_cvbs_regs.h
+++ /dev/null
@@ -1,238 +0,0 @@
-/*
- * drivers/display/vout/aml_cvbs_regs.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
-*/
-
-/*-------------------------------------------------------------------------------*/
-// hiu registers
-
-/*-------------------------------------------------------------------------------*/
-// encoder registers
-#define BUS_TYPE_CBUS 0
-#define BUS_TYPE_HIU 1
-#define BUS_TYPE_VCBUS 2
-#if 0/*defined in secure_apb.h*/
-#define MESON_CPU_MAJOR_ID_M6 0x16
-#define MESON_CPU_MAJOR_ID_M6TV 0x17
-#define MESON_CPU_MAJOR_ID_M6TVL 0x18
-#define MESON_CPU_MAJOR_ID_M8 0x19
-#define MESON_CPU_MAJOR_ID_MTVD 0x1A
-#define MESON_CPU_MAJOR_ID_M8B 0x1B
-#define MESON_CPU_MAJOR_ID_MG9TV 0x1C
-#define MESON_CPU_MAJOR_ID_M8M2 0x1D
-#define MESON_CPU_MAJOR_ID_GXBB 0x1F
-#define MESON_CPU_MAJOR_ID_GXTVBB 0x20
-#define MESON_CPU_MAJOR_ID_GXL 0x21
-#define MESON_CPU_MAJOR_ID_GXM 0x22
-#define MESON_CPU_MAJOR_ID_TXL 0x23
-#define MESON_CPU_MAJOR_ID_TXLX 0x24
-
-#define ASSIST_HW_REV 0x1f53
-#endif
-
-#define DAC0_CLK_SEL 28
-#define DAC1_CLK_SEL 24
-#define DAC2_CLK_SEL 20
-#define VCLK2_XD_RST 17
-#define VCLK2_XD_EN 16
-#define ENCL_CLK_SEL 12
-#define VCLK2_XD 0
-#define VCLK_XD0 0
-#define VCLK_CLK_IN_SEL 16
-#define VCLK_EN0 19
-#define VCLK_XD_EN 16
-#define VCLK_DIV1_EN 0
-#define VCLK_SOFT_RST 15
-
-#define VCLK2_EN 19
-#define VCLK2_CLK_IN_SEL 16
-#define VCLK2_SOFT_RST 15
-#define VCLK2_DIV12_EN 4
-#define VCLK2_DIV6_EN 3
-#define VCLK2_DIV4_EN 2
-#define VCLK2_DIV2_EN 1
-#define VCLK2_DIV1_EN 0
-#if 0/*defined in secure_apb.h*/
-#define ENCI_VIDEO_MODE 0x1b00
-#define ENCI_VIDEO_MODE_ADV 0x1b01
-#define ENCI_VIDEO_FSC_ADJ 0x1b02
-#define ENCI_VIDEO_BRIGHT 0x1b03
-#define ENCI_VIDEO_CONT 0x1b04
-#define ENCI_VIDEO_SAT 0x1b05
-#define ENCI_VIDEO_HUE 0x1b06
-#define ENCI_VIDEO_SCH 0x1b07
-#define ENCI_SYNC_MODE 0x1b08
-#define ENCI_SYNC_CTRL 0x1b09
-#define ENCI_SYNC_HSO_BEGIN 0x1b0a
-#define ENCI_SYNC_HSO_END 0x1b0b
-#define ENCI_SYNC_VSO_EVN 0x1b0c
-#define ENCI_SYNC_VSO_ODD 0x1b0d
-#define ENCI_SYNC_VSO_EVNLN 0x1b0e
-#define ENCI_SYNC_VSO_ODDLN 0x1b0f
-#define ENCI_SYNC_HOFFST 0x1b10
-#define ENCI_SYNC_VOFFST 0x1b11
-#define ENCI_SYNC_ADJ 0x1b12
-#define ENCI_RGB_SETTING 0x1b13
-
-#define ENCI_DE_H_BEGIN 0x1b16
-#define ENCI_DE_H_END 0x1b17
-#define ENCI_DE_V_BEGIN_EVEN 0x1b18
-#define ENCI_DE_V_END_EVEN 0x1b19
-#define ENCI_DE_V_BEGIN_ODD 0x1b1a
-#define ENCI_DE_V_END_ODD 0x1b1b
-#define ENCI_VBI_SETTING 0x1b20
-#define ENCI_VBI_CCDT_EVN 0x1b21
-#define ENCI_VBI_CCDT_ODD 0x1b22
-#define ENCI_VBI_CC525_LN 0x1b23
-#define ENCI_VBI_CC625_LN 0x1b24
-#define ENCI_VBI_WSSDT 0x1b25
-#define ENCI_VBI_WSS_LN 0x1b26
-#define ENCI_VBI_CGMSDT_L 0x1b27
-#define ENCI_VBI_CGMSDT_H 0x1b28
-#define ENCI_VBI_CGMS_LN 0x1b29
-#define ENCI_VBI_TTX_HTIME 0x1b2a
-#define ENCI_VBI_TTX_LN 0x1b2b
-#define ENCI_VBI_TTXDT0 0x1b2c
-#define ENCI_VBI_TTXDT1 0x1b2d
-#define ENCI_VBI_TTXDT2 0x1b2e
-#define ENCI_VBI_TTXDT3 0x1b2f
-#define ENCI_MACV_N0 0x1b30
-#define ENCI_MACV_N1 0x1b31
-#define ENCI_MACV_N2 0x1b32
-#define ENCI_MACV_N3 0x1b33
-#define ENCI_MACV_N4 0x1b34
-#define ENCI_MACV_N5 0x1b35
-#define ENCI_MACV_N6 0x1b36
-#define ENCI_MACV_N7 0x1b37
-#define ENCI_MACV_N8 0x1b38
-#define ENCI_MACV_N9 0x1b39
-#define ENCI_MACV_N10 0x1b3a
-#define ENCI_MACV_N11 0x1b3b
-#define ENCI_MACV_N12 0x1b3c
-#define ENCI_MACV_N13 0x1b3d
-#define ENCI_MACV_N14 0x1b3e
-#define ENCI_MACV_N15 0x1b3f
-#define ENCI_MACV_N16 0x1b40
-#define ENCI_MACV_N17 0x1b41
-#define ENCI_MACV_N18 0x1b42
-#define ENCI_MACV_N19 0x1b43
-#define ENCI_MACV_N20 0x1b44
-#define ENCI_MACV_N21 0x1b45
-#define ENCI_MACV_N22 0x1b46
-
-#define ENCI_DBG_PX_RST 0x1b48
-#define ENCI_DBG_FLDLN_RST 0x1b49
-#define ENCI_DBG_PX_INT 0x1b4a
-#define ENCI_DBG_FLDLN_INT 0x1b4b
-#define ENCI_DBG_MAXPX 0x1b4c
-#define ENCI_DBG_MAXLN 0x1b4d
-#define ENCI_MACV_MAX_AMP 0x1b50
-#define ENCI_MACV_PULSE_LO 0x1b51
-#define ENCI_MACV_PULSE_HI 0x1b52
-#define ENCI_MACV_BKP_MAX 0x1b53
-#define ENCI_CFILT_CTRL 0x1b54
-#define ENCI_CFILT7 0x1b55
-#define ENCI_YC_DELAY 0x1b56
-#define ENCI_VIDEO_EN 0x1b57
-
-#define ENCI_DVI_HSO_BEGIN 0x1c00
-#define ENCI_DVI_HSO_END 0x1c01
-#define ENCI_DVI_VSO_BLINE_EVN 0x1c02
-#define ENCI_DVI_VSO_BLINE_ODD 0x1c03
-#define ENCI_DVI_VSO_ELINE_EVN 0x1c04
-#define ENCI_DVI_VSO_ELINE_ODD 0x1c05
-#define ENCI_DVI_VSO_BEGIN_EVN 0x1c06
-#define ENCI_DVI_VSO_BEGIN_ODD 0x1c07
-#define ENCI_DVI_VSO_END_EVN 0x1c08
-#define ENCI_DVI_VSO_END_ODD 0x1c09
-
-#define ENCI_CFILT_CTRL2 0x1c0a
-#define ENCI_DACSEL_0 0x1c0b
-#define ENCI_DACSEL_1 0x1c0c
-#define ENCI_TST_EN 0x1c10
-#define ENCI_TST_MDSEL 0x1c11
-#define ENCI_TST_Y 0x1c12
-#define ENCI_TST_CB 0x1c13
-#define ENCI_TST_CR 0x1c14
-#define ENCI_TST_CLRBAR_STRT 0x1c15
-#define ENCI_TST_CLRBAR_WIDTH 0x1c16
-#define ENCI_TST_VDCNT_STSET 0x1c17
-
-#define ENCI_VFIFO2VD_CTL 0x1c18
-#define ENCI_VFIFO2VD_PIXEL_START 0x1c19
-#define ENCI_VFIFO2VD_PIXEL_END 0x1c1a
-#define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b
-#define ENCI_VFIFO2VD_LINE_TOP_END 0x1c1c
-#define ENCI_VFIFO2VD_LINE_BOT_START 0x1c1d
-#define ENCI_VFIFO2VD_LINE_BOT_END 0x1c1e
-#define ENCI_VFIFO2VD_CTL2 0x1c1f
-
-#define ENCI_SYNC_LINE_LENGTH 0x1c40
-#define ENCI_SYNC_PIXEL_EN 0x1c41
-#define ENCI_SYNC_TO_LINE_EN 0x1c42
-#define ENCI_SYNC_TO_PIXEL 0x1c43
-
-#define VENC_VDAC_DAC4_FILT_CTRL0 0x1c54
-#define VENC_VDAC_DAC4_FILT_CTRL1 0x1c55
-#define VENC_VDAC_DAC5_FILT_CTRL0 0x1c56
-#define VENC_VDAC_DAC5_FILT_CTRL1 0x1c57
-
-#define VENC_VDAC_DAC0_FILT_CTRL0 0x1c58
-#define VENC_VDAC_DAC0_FILT_CTRL1 0x1c59
-#define VENC_VDAC_DAC1_FILT_CTRL0 0x1c5a
-#define VENC_VDAC_DAC1_FILT_CTRL1 0x1c5b
-#define VENC_VDAC_DAC2_FILT_CTRL0 0x1c5c
-#define VENC_VDAC_DAC2_FILT_CTRL1 0x1c5d
-#define VENC_VDAC_DAC3_FILT_CTRL0 0x1c5e
-#define VENC_VDAC_DAC3_FILT_CTRL1 0x1c5f
-
-
-#define VENC_SYNC_ROUTE 0x1b60
-#define VENC_VIDEO_EXSRC 0x1b61
-#define VENC_DVI_SETTING 0x1b62
-#define VENC_C656_CTRL 0x1b63
-#define VENC_UPSAMPLE_CTRL0 0x1b64
-#define VENC_UPSAMPLE_CTRL1 0x1b65
-#define VENC_UPSAMPLE_CTRL2 0x1b66
-#define VENC_VIDEO_PROG_MODE 0x1b68
-
-#define VENC_INTCTRL 0x1b6e
-#define VENC_INTFLAG 0x1b6f
-
-#define VENC_VDAC_DACSEL0 0x1b78
-#define VENC_VDAC_DACSEL1 0x1b79
-#define VENC_VDAC_DACSEL2 0x1b7a
-#define VENC_VDAC_DACSEL3 0x1b7b
-#define VENC_VDAC_DACSEL4 0x1b7c
-#define VENC_VDAC_DACSEL5 0x1b7d
-#define VENC_VDAC_SETTING 0x1b7e
-#define VENC_VDAC_TST_VAL 0x1b7f
-#define VENC_VDAC_DAC0_GAINCTRL 0x1bf0
-#define VENC_VDAC_DAC0_OFFSET 0x1bf1
-#define VENC_VDAC_DAC1_GAINCTRL 0x1bf2
-#define VENC_VDAC_DAC1_OFFSET 0x1bf3
-#define VENC_VDAC_DAC2_GAINCTRL 0x1bf4
-#define VENC_VDAC_DAC2_OFFSET 0x1bf5
-#define VENC_VDAC_DAC3_GAINCTRL 0x1bf6
-#define VENC_VDAC_DAC3_OFFSET 0x1bf7
-#define VENC_VDAC_DAC4_GAINCTRL 0x1bf8
-#define VENC_VDAC_DAC4_OFFSET 0x1bf9
-#define VENC_VDAC_DAC5_GAINCTRL 0x1bfa
-#define VENC_VDAC_DAC5_OFFSET 0x1bfb
-#define VENC_VDAC_FIFO_CTRL 0x1bfc
-
-#define VPU_VIU_VENC_MUX_CTRL 0x271a
-#endif
-
diff --git a/drivers/amlogic/media/vout/cvbs/cvbs.c b/drivers/amlogic/media/vout/cvbs/cvbs.c
new file mode 100644
index 0000000..3aea0f0
--- /dev/null
+++ b/drivers/amlogic/media/vout/cvbs/cvbs.c
@@ -0,0 +1,778 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <fdtdec.h>
+#include <dm.h>
+#include <asm/arch/cpu.h>
+#include <amlogic/cpu_id.h>
+#include <amlogic/media/vout/aml_vout.h>
+#include <amlogic/media/vout/aml_cvbs.h>
+#include "cvbs_reg.h"
+#include "cvbs_config.h"
+#include "cvbs.h"
+#include "vdac.h"
+
+/*----------------------------------------------------------------------------*/
+static struct cvbs_drv_s cvbs_drv = {
+ .data = NULL,
+};
+
+static struct cvbs_data_s cvbs_data_g12a = {
+ .chip_type = CVBS_CHIP_G12A,
+
+ .reg_vid_pll_clk_div = HHI_VID_PLL_CLK_DIV,
+ .reg_vid_clk_div = HHI_VID_CLK_DIV,
+ .reg_vid_clk_ctrl = HHI_VID_CLK_CNTL,
+ .reg_vid2_clk_div = HHI_VIID_CLK_DIV,
+ .reg_vid2_clk_ctrl = HHI_VIID_CLK_CNTL,
+ .reg_vid_clk_ctrl2 = HHI_VID_CLK_CNTL2,
+
+ .vdac_vref_adj = 0x10,
+ .vdac_gsw = 0x0,
+};
+
+static struct cvbs_data_s cvbs_data_g12b = {
+ .chip_type = CVBS_CHIP_G12B,
+
+ .reg_vid_pll_clk_div = HHI_VID_PLL_CLK_DIV,
+ .reg_vid_clk_div = HHI_VID_CLK_DIV,
+ .reg_vid_clk_ctrl = HHI_VID_CLK_CNTL,
+ .reg_vid2_clk_div = HHI_VIID_CLK_DIV,
+ .reg_vid2_clk_ctrl = HHI_VIID_CLK_CNTL,
+ .reg_vid_clk_ctrl2 = HHI_VID_CLK_CNTL2,
+
+ .vdac_vref_adj = 0xf,
+ .vdac_gsw = 0x0,
+};
+
+static struct cvbs_data_s cvbs_data_sc2 = {
+ .chip_type = CVBS_CHIP_SC2,
+
+ .reg_vid_pll_clk_div = CLKCTRL_VID_PLL_CLK_DIV,
+ .reg_vid_clk_div = CLKCTRL_VID_CLK_DIV,
+ .reg_vid_clk_ctrl = CLKCTRL_VID_CLK_CTRL,
+ .reg_vid2_clk_div = CLKCTRL_VIID_CLK_DIV,
+ .reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK_CTRL,
+ .reg_vid_clk_ctrl2 = CLKCTRL_VID_CLK_CTRL2,
+
+ .vdac_vref_adj = 0x10,
+ .vdac_gsw = 0x0,
+};
+
+static struct cvbs_data_s cvbs_data_s4 = {
+ .chip_type = CVBS_CHIP_S4,
+
+ .reg_vid_pll_clk_div = CLKCTRL_VID_PLL_CLK_DIV,
+ .reg_vid_clk_div = CLKCTRL_VID_CLK_DIV,
+ .reg_vid_clk_ctrl = CLKCTRL_VID_CLK_CTRL,
+ .reg_vid2_clk_div = CLKCTRL_VIID_CLK_DIV,
+ .reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK_CTRL,
+ .reg_vid_clk_ctrl2 = CLKCTRL_VID_CLK_CTRL2,
+
+ .vdac_vref_adj = 0x10,
+ .vdac_gsw = 0x0,
+};
+
+unsigned int cvbs_mode = VMODE_MAX;
+/*bit[0]: 0=vid_pll, 1=gp0_pll*/
+/*bit[1]: 0=vid2_clk, 1=vid1_clk*/
+/*path 0:vid_pll vid2_clk*/
+/*path 1:gp0_pll vid2_clk*/
+/*path 2:vid_pll vid1_clk*/
+/*path 3:gp0_pll vid1_clk*/
+static unsigned int s_enci_clk_path = 0;
+
+/*----------------------------------------------------------------------------*/
+// configuration for enci bist
+int cvbs_set_bist(char* bist_mode)
+{
+ if (!strcmp(bist_mode, "off")) {
+ cvbs_write_vcbus(ENCI_VIDEO_MODE_ADV, 0x26);
+ cvbs_write_vcbus(ENCI_TST_EN, 0x0);
+ } else {
+ unsigned int mode = 0;
+
+ if (!strcmp(bist_mode, "fixval") || !strcmp(bist_mode, "0"))
+ mode = 0;
+ else if (!strcmp(bist_mode, "colorbar") || !strcmp(bist_mode, "1"))
+ mode = 1;
+ else if (!strcmp(bist_mode, "thinline") || !strcmp(bist_mode, "2"))
+ mode = 2;
+ else if (!strcmp(bist_mode, "dotgrid") || !strcmp(bist_mode, "3"))
+ mode = 3;
+
+ cvbs_write_vcbus(ENCI_VIDEO_MODE_ADV, 0x2);
+ cvbs_write_vcbus(ENCI_TST_MDSEL, mode);
+ cvbs_write_vcbus(ENCI_TST_CLRBAR_STRT, 0x112);
+ cvbs_write_vcbus(ENCI_TST_CLRBAR_WIDTH, 0xb4);
+ cvbs_write_vcbus(ENCI_TST_EN, 0x1);
+ }
+
+ return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+int cvbs_set_vdac(int status)
+{
+ switch (status) {
+ case 0:// close vdac
+ if (cvbs_drv.data)
+ vdac_enable(0, VDAC_MODULE_CVBS_OUT);
+ else
+ printf("cvbs ERROR:need run cvbs init.\n");
+ break;
+ case 1:// from enci to vdac
+ cvbs_set_vcbus_bits(VENC_VDAC_DACSEL0, 0, 5, 1);
+ if (cvbs_drv.data) {
+ vdac_ctrl_vref_adj(cvbs_drv.data->vdac_vref_adj);
+ vdac_enable(1, VDAC_MODULE_CVBS_OUT);
+ } else {
+ printf("cvbs ERROR:need run cvbs init.\n");
+ }
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+// interface for debug
+static void cvbs_dump_cvbs_regs(void)
+{
+ struct reg_s *p = NULL;
+
+ if (VMODE_PAL == cvbs_mode) {
+ // 576cvbs
+ p = (struct reg_s*)&tvregs_576cvbs_enc[0];
+
+ } else if (VMODE_NTSC == cvbs_mode) {
+ // 480cvbs
+ p = (struct reg_s*)&tvregs_480cvbs_enc[0];
+ }
+
+ if (NULL == p) {
+ printf("it's not in cvbs mode!\n");
+ return;
+ }
+
+ if (MREG_END_MARKER != p->reg)
+ printf("cvbs enci registers:\n");
+ while (MREG_END_MARKER != p->reg) {
+ printf(" vcbus[0x%.2x] = 0x%.4x\n", p->reg, cvbs_read_vcbus(p->reg));
+ p ++;
+ }
+
+ return;
+}
+
+unsigned int cvbs_clk_regs[] = {
+ HHI_HDMI_PLL_CNTL0,
+ HHI_HDMI_PLL_CNTL1,
+ HHI_HDMI_PLL_CNTL2,
+ HHI_HDMI_PLL_CNTL3,
+ HHI_HDMI_PLL_CNTL4,
+ HHI_HDMI_PLL_CNTL5,
+ HHI_HDMI_PLL_CNTL6,
+ HHI_VID_PLL_CLK_DIV,
+ HHI_VIID_CLK_DIV,
+ HHI_VIID_CLK_CNTL,
+ HHI_VID_CLK_DIV,
+ HHI_VID_CLK_CNTL2,
+ MREG_END_MARKER
+};
+
+static void cvbs_dump_clock_regs(void)
+{
+ unsigned int *p = &cvbs_clk_regs[0];
+
+ if (MREG_END_MARKER != *p)
+ printf("cvbs clock registers:\n");
+ while (MREG_END_MARKER != *p) {
+ printf(" hiu[0x%.2x] = 0x%.4x\n", *p, cvbs_read_hiu(*p));
+ p ++;
+ }
+
+ return;
+}
+
+int cvbs_reg_debug(int argc, char* const argv[])
+{
+ unsigned int value;
+
+ if (!cvbs_drv.data) {
+ printf("cvbs: error: %s: no cvbs data\n", __func__);
+ return -1;
+ }
+
+ if (!strcmp(argv[1], "clock")) {
+ if (argc != 2)
+ goto fail_cmd;
+
+ cvbs_dump_clock_regs();
+ } else if (!strcmp(argv[1], "enci")) {
+ if (argc != 2)
+ goto fail_cmd;
+
+ cvbs_dump_cvbs_regs();
+ } else if (!strcmp(argv[1], "clkpath")) {
+ if (argc != 3)
+ goto fail_cmd;
+ value = simple_strtoul(argv[2], NULL, 0);
+ if ((cvbs_drv.data->chip_type == CVBS_CHIP_G12A) ||
+ (cvbs_drv.data->chip_type == CVBS_CHIP_G12B)) {
+ if (value == 1 || value == 2 ||
+ value == 3 || value == 0) {
+ s_enci_clk_path = value;
+ printf("path 0:vid_pll vid2_clk\n");
+ printf("path 1:gp0_pll vid2_clk\n");
+ printf("path 2:vid_pll vid1_clk\n");
+ printf("path 3:gp0_pll vid1_clk\n");
+ printf("you select path %d\n", s_enci_clk_path);
+ } else {
+ printf("invalid value, only 0/1/2/3\n");
+ printf("bit[0]: 0=vid_pll, 1=gp0_pll\n");
+ printf("bit[1]: 0=vid2_clk, 1=vid1_clk\n");
+ }
+ } else {
+ printf("don't support for current chip\n");
+ }
+ }
+
+ return 0;
+
+fail_cmd:
+ return 1;
+}
+
+/*----------------------------------------------------------------------------*/
+// configuration for clock
+#define WAIT_FOR_PLL_LOCKED(reg) \
+ do { \
+ unsigned int pll_lock; \
+ unsigned int time_out = 0; \
+ do { \
+ udelay(20); \
+ pll_lock = cvbs_get_hiu_bits(reg, 31, 1); \
+ time_out ++; \
+ } while ((pll_lock == 0) && (time_out < 10000)); \
+ if (pll_lock == 0) \
+ printf("[error]: cvbs pll lock failed\n"); \
+ } while(0);
+
+static void cvbs_config_hdmipll_g12a(void)
+{
+ printf("%s\n", __func__);
+ cvbs_write_hiu(HHI_HDMI_PLL_CNTL0, 0x1a0504f7);
+ cvbs_write_hiu(HHI_HDMI_PLL_CNTL1, 0x00010000);
+ cvbs_write_hiu(HHI_HDMI_PLL_CNTL2, 0x00000000);
+ cvbs_write_hiu(HHI_HDMI_PLL_CNTL3, 0x6a28dc00);
+ cvbs_write_hiu(HHI_HDMI_PLL_CNTL4, 0x65771290);
+ cvbs_write_hiu(HHI_HDMI_PLL_CNTL5, 0x39272000);
+ cvbs_write_hiu(HHI_HDMI_PLL_CNTL6, 0x56540000);
+ cvbs_write_hiu(HHI_HDMI_PLL_CNTL0, 0x3a0504f7);
+ udelay(100);
+ cvbs_write_hiu(HHI_HDMI_PLL_CNTL0, 0x1a0504f7);
+ WAIT_FOR_PLL_LOCKED(HHI_HDMI_PLL_CNTL0);
+ return;
+}
+
+static void cvbs_config_gp0pll_g12a(void)
+{
+ printf("%s\n", __func__);
+ cvbs_write_hiu(HHI_GP0_PLL_CNTL0, 0x180204f7);
+ cvbs_write_hiu(HHI_GP0_PLL_CNTL1, 0x00010000);
+ cvbs_write_hiu(HHI_GP0_PLL_CNTL2, 0x00000000);
+ cvbs_write_hiu(HHI_GP0_PLL_CNTL3, 0x6a28dc00);
+ cvbs_write_hiu(HHI_GP0_PLL_CNTL4, 0x65771290);
+ cvbs_write_hiu(HHI_GP0_PLL_CNTL5, 0x39272000);
+ cvbs_write_hiu(HHI_GP0_PLL_CNTL6, 0x56540000);
+ cvbs_write_hiu(HHI_GP0_PLL_CNTL0, 0x380204f7);
+ udelay(100);
+ cvbs_write_hiu(HHI_GP0_PLL_CNTL0, 0x180204f7);
+ WAIT_FOR_PLL_LOCKED(HHI_GP0_PLL_CNTL0);
+ return;
+}
+
+static void cvbs_config_hdmipll_sc2(void)
+{
+ printf("%s\n", __func__);
+ cvbs_write_hiu(ANACTRL_HDMIPLL_CTRL0, 0x3b01047b);
+ cvbs_write_hiu(ANACTRL_HDMIPLL_CTRL1, 0x00018000);
+ cvbs_write_hiu(ANACTRL_HDMIPLL_CTRL2, 0x00000000);
+ cvbs_write_hiu(ANACTRL_HDMIPLL_CTRL3, 0x0a691c00);
+ cvbs_write_hiu(ANACTRL_HDMIPLL_CTRL4, 0x33771290);
+ cvbs_write_hiu(ANACTRL_HDMIPLL_CTRL5, 0x39270000);
+ cvbs_write_hiu(ANACTRL_HDMIPLL_CTRL6, 0x50540000);
+ udelay(100);
+ cvbs_write_hiu(ANACTRL_HDMIPLL_CTRL0, 0x1b01047b);
+ WAIT_FOR_PLL_LOCKED(ANACTRL_HDMIPLL_CTRL0);
+}
+
+static void cvbs_set_vid1_clk(unsigned int src_pll)
+{
+ int sel = 0;
+
+ if (!cvbs_drv.data) {
+ printf("cvbs: error: %s: no cvbs data\n", __func__);
+ return;
+ }
+
+ printf("%s\n", __func__);
+ if (src_pll == 0) { /* hpll */
+ /* divider: 1 */
+ /* Disable the div output clock */
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_pll_clk_div, 0, 19, 1);
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_pll_clk_div, 0, 15, 1);
+
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_pll_clk_div, 1, 18, 1);
+ /* Enable the final output clock */
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_pll_clk_div, 1, 19, 1);
+ sel = 0;
+ } else { /* gp0_pll */
+ sel = 1;
+ }
+
+ /* xd: 55 */
+ /* setup the XD divider value */
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_div, (55 - 1), VCLK_XD0, 8);
+ //udelay(5);
+ /*0x59[16]/0x5f[19]/0x5f[20]*/
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_ctrl, sel, VCLK_CLK_IN_SEL, 3);
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_ctrl, 1, VCLK_EN0, 1);
+ //udelay(2);
+
+ /* vclk: 27M */
+ /* [31:28]=0 enci_clk_sel, select vclk_div1 */
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_div, 0, 28, 4);
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid2_clk_div, 0, 28, 4);
+ /* release vclk_div_reset and enable vclk_div */
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_div, 1, VCLK_XD_EN, 2);
+ //udelay(5);
+
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_ctrl, 1, VCLK_DIV1_EN, 1);
+
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_ctrl, 1, VCLK_SOFT_RST, 1);
+ //udelay(10);
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_ctrl, 0, VCLK_SOFT_RST, 1);
+ //udelay(5);
+}
+
+static void cvbs_set_vid2_clk(unsigned int src_pll)
+{
+ int sel = 0;
+
+ if (!cvbs_drv.data) {
+ printf("cvbs: error: %s: no cvbs data\n", __func__);
+ return;
+ }
+
+ printf("%s\n", __func__);
+ if (src_pll == 0) { /* hpll */
+ /* divider: 1 */
+ /* Disable the div output clock */
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_pll_clk_div, 0, 19, 1);
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_pll_clk_div, 0, 15, 1);
+
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_pll_clk_div, 1, 18, 1);
+ /* Enable the final output clock */
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_pll_clk_div, 1, 19, 1);
+ sel = 0;
+ } else { /* gp0_pll */
+ sel = 1;
+ }
+
+ /* xd: 55 */
+ /* setup the XD divider value */
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid2_clk_div, (55 - 1), VCLK2_XD, 8);
+ //udelay(5);
+ /* Bit[18:16] - v2_cntl_clk_in_sel: vid_pll */
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid2_clk_ctrl, sel, VCLK2_CLK_IN_SEL, 3);
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid2_clk_ctrl, 1, VCLK2_EN, 1);
+ //udelay(2);
+
+ /* vclk: 27M */
+ /* [31:28]=8 enci_clk_sel, select vclk2_div1 */
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_div, 8, 28, 4);
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid2_clk_div, 8, 28, 4);
+ /* release vclk2_div_reset and enable vclk2_div */
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid2_clk_div, 1, VCLK2_XD_EN, 2);
+ //udelay(5);
+
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid2_clk_ctrl, 1, VCLK2_DIV1_EN, 1);
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid2_clk_ctrl, 1, VCLK2_SOFT_RST, 1);
+ //udelay(10);
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid2_clk_ctrl, 0, VCLK2_SOFT_RST, 1);
+ //udelay(5);
+}
+
+static int cvbs_config_clock(void)
+{
+ if (!cvbs_drv.data) {
+ printf("cvbs: error: %s: no cvbs data\n", __func__);
+ return -1;
+ }
+
+ /* pll output 1485M */
+ switch (cvbs_drv.data->chip_type) {
+ case CVBS_CHIP_G12A:
+ case CVBS_CHIP_G12B:
+ if (s_enci_clk_path & 0x1)
+ cvbs_config_gp0pll_g12a();
+ else
+ cvbs_config_hdmipll_g12a();
+ if (s_enci_clk_path & 0x2)
+ cvbs_set_vid1_clk(s_enci_clk_path & 0x1);
+ else
+ cvbs_set_vid2_clk(s_enci_clk_path & 0x1);
+ break;
+ case CVBS_CHIP_SC2:
+ case CVBS_CHIP_S4:
+ cvbs_config_hdmipll_sc2();
+ cvbs_set_vid2_clk(0);
+ break;
+ default:
+ printf("cvbs: %s: invalid chip type\n", __func__);
+ return -1;
+ }
+
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_ctrl2, 1, 0, 1);
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_ctrl2, 1, 4, 1);
+
+ return 0;
+}
+
+static void cvbs_disable_clock(void)
+{
+ if (!cvbs_drv.data) {
+ printf("cvbs: error: %s: no cvbs data\n", __func__);
+ return;
+ }
+
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_ctrl2, 0, 4, 1);
+ cvbs_set_hiu_bits(cvbs_drv.data->reg_vid_clk_ctrl2, 0, 0, 1);
+}
+
+/*----------------------------------------------------------------------------*/
+// configuration for enci
+static void cvbs_performance_enhancement(int mode)
+{
+ const struct reg_s *s = NULL;
+ struct performance_config_s *perfconf = NULL;
+ int i = 0;
+
+ switch (mode) {
+ case VMODE_PAL:
+ perfconf = &cvbs_drv.perf_conf_pal;
+ break;
+ case VMODE_NTSC:
+ case VMODE_NTSC_M:
+ perfconf = &cvbs_drv.perf_conf_ntsc;
+ break;
+ default:
+ break;
+ }
+ if (!perfconf)
+ return;
+
+ if (!perfconf->reg_table) {
+ printf("no performance table\n");
+ return;
+ }
+
+ i = 0;
+ s = perfconf->reg_table;
+ while (i < perfconf->reg_cnt) {
+ cvbs_write_vcbus(s->reg, s->val);
+ //printf("vcbus reg[0x%04x] = 0x%08x\n", s->reg, s->val);
+
+ s++;
+ i++;
+ }
+
+ printf("%s\n", __func__);
+}
+
+static int cvbs_config_enci(int vmode)
+{
+ const struct reg_s *s = NULL;
+
+ switch (vmode) {
+ case VMODE_PAL:
+ s = &tvregs_576cvbs_enc[0];
+ break;
+ case VMODE_NTSC:
+ case VMODE_NTSC_M:
+ s = &tvregs_480cvbs_enc[0];
+ break;
+ case VMODE_PAL_M:
+ s = &tvregs_pal_m_enc[0];
+ break;
+ case VMODE_PAL_N:
+ s = &tvregs_pal_n_enc[0];
+ break;
+ default:
+ break;
+ }
+ if (s == NULL)
+ return -1;
+
+ while ((s->reg != MREG_END_MARKER)) {
+ cvbs_write_vcbus(s->reg, s->val);
+ //printf("reg[0x%.2x] = 0x%.4x\n", s->reg, s->val);
+ s ++;
+ }
+
+ cvbs_performance_enhancement(vmode);
+
+ return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+// configuration for output
+// output vmode: 576cvbs, 480cvbs
+int cvbs_set_vmode(char* vmode_name)
+{
+ if (!strncmp(vmode_name, "576cvbs", strlen("576cvbs"))) {
+ cvbs_mode = VMODE_PAL;
+ cvbs_config_enci(0);
+ cvbs_config_clock();
+ cvbs_set_vdac(1);
+ return 0;
+ } else if (!strncmp(vmode_name, "480cvbs", strlen("480cvbs"))) {
+ cvbs_mode = VMODE_NTSC;
+ cvbs_config_enci(1);
+ cvbs_config_clock();
+ cvbs_set_vdac(1);
+ return 0;
+ } else if (!strncmp(vmode_name, "ntsc_m", strlen("ntsc_m"))) {
+ cvbs_mode = VMODE_NTSC_M;
+ cvbs_config_enci(VMODE_NTSC_M);
+ cvbs_config_clock();
+ cvbs_set_vdac(1);
+ return 0;
+ } else if (!strncmp(vmode_name, "pal_m", strlen("pal_m"))) {
+ cvbs_mode = VMODE_PAL_M;
+ cvbs_config_enci(VMODE_PAL_M);
+ cvbs_config_clock();
+ cvbs_set_vdac(1);
+ return 0;
+ } else if (!strncmp(vmode_name, "pal_n", strlen("pal_n"))) {
+ cvbs_mode = VMODE_PAL_N;
+ cvbs_config_enci(VMODE_PAL_N);
+ cvbs_config_clock();
+ cvbs_set_vdac(1);
+ return 0;
+ } else if (!strncmp(vmode_name, "disable", strlen("disable"))) {
+ cvbs_set_vdac(0);
+ cvbs_write_vcbus(ENCI_VIDEO_EN, 0);
+ cvbs_disable_clock();
+ return 0;
+ } else {
+ printf("[%s] is invalid for cvbs.\n", vmode_name);
+ return -1;
+ }
+
+ return 0;
+}
+
+/*----------------------------------------------------------------------------*/
+#define CVBS_MODE_CNT 5
+static char *cvbs_mode_str[CVBS_MODE_CNT] = {
+ "576cvbs",
+ "480cvbs",
+ "ntsc_m",
+ "pal_m",
+ "pal_n",
+};
+
+/***********************************************
+ * parameters: vmode_name, such as 576cvbs, 480cvbs...
+ * frac, cvbs alway 0. don't support.
+ * return: viu_mux
+ ************************************************/
+unsigned int cvbs_outputmode_check(char *vmode_name, unsigned int frac)
+{
+ unsigned int i;
+
+ if (frac) {
+ printf("cvbs: don't support frac\n");
+ return VIU_MUX_MAX;
+ }
+
+ for (i = 0; i < CVBS_MODE_CNT; i++) {
+ if (!strncmp(vmode_name, cvbs_mode_str[i], strlen(cvbs_mode_str[i])))
+ return VIU_MUX_ENCI;
+ }
+
+ //printf("cvbs: outputmode[%s] is invalid\n", vmode_name);
+ return VIU_MUX_MAX;
+}
+
+// list for valid video mode
+void cvbs_show_valid_vmode(void)
+{
+ unsigned int i;
+
+ for (i = 0; i < CVBS_MODE_CNT; i++)
+ printf("%s\n", cvbs_mode_str[i]);
+}
+
+static char *cvbsout_performance_str[] = {
+ "performance", /* default for pal */
+ "performance_pal",
+ "performance_ntsc",
+};
+
+static void cvbs_get_config(void)
+{
+ const void *dt_blob = NULL;
+ int node;
+ char *propdata;
+ const char *str;
+ struct reg_s *s;
+ unsigned int i, j, temp, cnt;
+ int ret;
+
+ dt_blob = gd->fdt_blob;
+ if (!dt_blob) {
+ printf("cvbs: error: dt_blob is null, load default setting\n");
+ return;
+ }
+
+ ret = fdt_check_header(dt_blob);
+ if (ret < 0) {
+ printf("cvbs: error: check dts: %s, load default setting\n",
+ fdt_strerror(ret));
+ return;
+ }
+
+ node = fdt_path_offset(dt_blob, "/cvbsout");
+ if (node < 0) {
+ printf("not find /cvbsout node: %s\n",
+ fdt_strerror(node));
+ return;
+ }
+
+ /* clk_path */
+ propdata = (char *)fdt_getprop(dt_blob, node, "clk_path", NULL);
+ if (propdata) {
+ s_enci_clk_path = be32_to_cpup((u32*)propdata);
+ printf("cvbs: find clk_path: 0x%x\n", s_enci_clk_path);
+ }
+
+ /* performance */
+ str = cvbsout_performance_str[1];
+ propdata = (char *)fdt_getprop(dt_blob, node, str, NULL);
+ if (!propdata) {
+ str = cvbsout_performance_str[0];
+ propdata = (char *)fdt_getprop(dt_blob, node, str, NULL);
+ if (!propdata)
+ goto cvbs_performance_config_ntsc;
+ }
+ cnt = 0;
+ while (cnt < CVBS_PERFORMANCE_CNT_MAX) {
+ j = 2 * cnt;
+ temp = be32_to_cpup((((u32*)propdata)+j));
+ if (temp == MREG_END_MARKER) /* ending */
+ break;
+ cnt++;
+ }
+ if (cnt >= CVBS_PERFORMANCE_CNT_MAX)
+ cnt = 0;
+ if (cnt > 0) {
+ printf("cvbs: find performance_pal config\n");
+ cvbs_drv.perf_conf_pal.reg_table = malloc(sizeof(struct reg_s) * cnt);
+ if (!cvbs_drv.perf_conf_pal.reg_table) {
+ printf("cvbs: error: failed to alloc %s table\n", str);
+ cnt = 0;
+ }
+ memset(cvbs_drv.perf_conf_pal.reg_table, 0, (sizeof(struct reg_s) * cnt));
+ cvbs_drv.perf_conf_pal.reg_cnt = cnt;
+
+ i = 0;
+ s = cvbs_drv.perf_conf_pal.reg_table;
+ while (i < cvbs_drv.perf_conf_pal.reg_cnt) {
+ j = 2 * i;
+ s->reg = be32_to_cpup((((u32*)propdata)+j));
+ s->val = be32_to_cpup((((u32*)propdata)+j+1));
+ /* printf("%p: 0x%04x = 0x%x\n", s, s->reg, s->val); */
+
+ s++;
+ i++;
+ }
+ }
+
+cvbs_performance_config_ntsc:
+ str = cvbsout_performance_str[2];
+ propdata = (char *)fdt_getprop(dt_blob, node, str, NULL);
+ if (!propdata)
+ return;
+ cnt = 0;
+ while (cnt < CVBS_PERFORMANCE_CNT_MAX) {
+ j = 2 * cnt;
+ temp = be32_to_cpup((((u32*)propdata)+j));
+ if (temp == MREG_END_MARKER) /* ending */
+ break;
+ cnt++;
+ }
+ if (cnt >= CVBS_PERFORMANCE_CNT_MAX)
+ cnt = 0;
+ if (cnt > 0) {
+ printf("cvbs: find performance_ntsc config\n");
+ cvbs_drv.perf_conf_ntsc.reg_table = malloc(sizeof(struct reg_s) * cnt);
+ if (!cvbs_drv.perf_conf_ntsc.reg_table) {
+ printf("cvbs: error: failed to alloc %s table\n", str);
+ cnt = 0;
+ }
+ memset(cvbs_drv.perf_conf_ntsc.reg_table, 0, (sizeof(struct reg_s) * cnt));
+ cvbs_drv.perf_conf_ntsc.reg_cnt = cnt;
+
+ i = 0;
+ s = cvbs_drv.perf_conf_ntsc.reg_table;
+ while (i < cvbs_drv.perf_conf_ntsc.reg_cnt) {
+ j = 2 * i;
+ s->reg = be32_to_cpup((((u32*)propdata)+j));
+ s->val = be32_to_cpup((((u32*)propdata)+j+1));
+ /* printf("%p: 0x%04x = 0x%x\n", s, s->reg, s->val); */
+
+ s++;
+ i++;
+ }
+ }
+}
+
+void vdac_data_config(void)
+{
+ printf("cvbs: cpuid:0x%x\n", get_cpu_id().family_id);
+ switch (get_cpu_id().family_id) {
+ case MESON_CPU_MAJOR_ID_G12A:
+ cvbs_drv.data = &cvbs_data_g12a;
+ break;
+ case MESON_CPU_MAJOR_ID_G12B:
+ cvbs_drv.data = &cvbs_data_g12b;
+ break;
+ case MESON_CPU_MAJOR_ID_SC2:
+ cvbs_drv.data = &cvbs_data_sc2;
+ break;
+ case MESON_CPU_MAJOR_ID_S4:
+ cvbs_drv.data = &cvbs_data_s4;
+ break;
+ default:
+ cvbs_drv.data = &cvbs_data_s4;
+ break;
+ }
+}
+
+void cvbs_init(void)
+{
+ vdac_data_config();
+ vdac_ctrl_config_probe();
+ cvbs_get_config();
+}
+
diff --git a/drivers/amlogic/media/vout/cvbs/cvbs.h b/drivers/amlogic/media/vout/cvbs/cvbs.h
new file mode 100644
index 0000000..1afe724
--- /dev/null
+++ b/drivers/amlogic/media/vout/cvbs/cvbs.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _AML_CVBS_H
+#define _AML_CVBS_H
+
+#define CONFIG_CVBS_PERFORMANCE_COMPATIBILITY_SUPPORT 1
+
+#define CONFIG_CVBS_CHINASARFT 0x0
+#define CONFIG_CVBS_CHINATELECOM 0x1
+#define CONFIG_CVBS_CHINAMOBILE 0x2
+#define CONFIG_CVBS_PERFORMANCE_ACTIVED CONFIG_CVBS_CHINASARFT
+
+#define MREG_END_MARKER 0xFFFF
+
+enum cvbs_chip_e {
+ CVBS_CHIP_G12A = 0,
+ CVBS_CHIP_G12B, /* 1 */
+ CVBS_CHIP_SC2, /* 2 */
+ CVBS_CHIP_S4, /* 3 */
+ CVBS_CHIP_MAX,
+};
+
+enum CVBS_MODE_e {
+ VMODE_PAL,
+ VMODE_NTSC,
+ VMODE_PAL_M,
+ VMODE_PAL_N,
+ VMODE_NTSC_M,
+ VMODE_MAX
+};
+
+struct cvbs_data_s {
+ enum cvbs_chip_e chip_type;
+
+ unsigned int reg_vid_pll_clk_div;
+ unsigned int reg_vid_clk_div;
+ unsigned int reg_vid_clk_ctrl;
+ unsigned int reg_vid2_clk_div;
+ unsigned int reg_vid2_clk_ctrl;
+ unsigned int reg_vid_clk_ctrl2;
+
+ unsigned int vdac_vref_adj;
+ unsigned int vdac_gsw;
+};
+
+struct reg_s {
+ unsigned int reg;
+ unsigned int val;
+};
+
+#define CVBS_PERFORMANCE_CNT_MAX 20
+struct performance_config_s {
+ unsigned int reg_cnt;
+ struct reg_s *reg_table;
+};
+
+struct cvbs_drv_s {
+ struct cvbs_data_s *data;
+ struct performance_config_s perf_conf_pal;
+ struct performance_config_s perf_conf_ntsc;
+};
+
+#endif
diff --git a/drivers/amlogic/media/vout/cvbs/cvbs_config.h b/drivers/amlogic/media/vout/cvbs/cvbs_config.h
new file mode 100644
index 0000000..3b3309c
--- /dev/null
+++ b/drivers/amlogic/media/vout/cvbs/cvbs_config.h
@@ -0,0 +1,206 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "cvbs_reg.h"
+#include "cvbs.h"
+
+static const struct reg_s tvregs_576cvbs_enc[] = {
+ {ENCI_CFILT_CTRL, 0x12, },
+ {ENCI_CFILT_CTRL2, 0x12, },
+ {VENC_DVI_SETTING, 0, },
+ {ENCI_VIDEO_MODE, 0, },
+ {ENCI_VIDEO_MODE_ADV, 0, },
+ {ENCI_SYNC_HSO_BEGIN, 3, },
+ {ENCI_SYNC_HSO_END, 129, },
+ {ENCI_SYNC_VSO_EVNLN, 0x0003 },
+ {ENCI_SYNC_VSO_ODDLN, 0x0104 },
+ {ENCI_MACV_MAX_AMP, 0x8107 },
+ {VENC_VIDEO_PROG_MODE, 0xff },
+ {ENCI_VIDEO_MODE, 0x13 },
+ {ENCI_VIDEO_MODE_ADV, 0x26, },
+ {ENCI_VIDEO_SCH, 0x28, },
+ {ENCI_SYNC_MODE, 0x07, },
+ {ENCI_YC_DELAY, 0x333, },
+ {ENCI_VFIFO2VD_PIXEL_START, 0x0fb },
+ {ENCI_VFIFO2VD_PIXEL_END, 0x069b },
+ {ENCI_VFIFO2VD_LINE_TOP_START, 0x0016 },
+ {ENCI_VFIFO2VD_LINE_TOP_END, 0x0136 },
+ {ENCI_VFIFO2VD_LINE_BOT_START, 0x0017 },
+ {ENCI_VFIFO2VD_LINE_BOT_END, 0x0137 },
+ {VENC_SYNC_ROUTE, 0, },
+ {ENCI_DBG_PX_RST, 0, },
+ {VENC_INTCTRL, 0x2, },
+ {ENCI_VFIFO2VD_CTL, 0x4e01, },
+ {VENC_VDAC_SETTING, 0, },
+ {VENC_UPSAMPLE_CTRL0, 0x0061, },
+ {VENC_UPSAMPLE_CTRL1, 0x4061, },
+ {VENC_UPSAMPLE_CTRL2, 0x5061, },
+ {VENC_VDAC_DACSEL0, 0x0000, },
+ {VENC_VDAC_DACSEL1, 0x0000, },
+ {VENC_VDAC_DACSEL2, 0x0000, },
+ {VENC_VDAC_DACSEL3, 0x0000, },
+ {VENC_VDAC_DACSEL4, 0x0000, },
+ {VENC_VDAC_DACSEL5, 0x0000, },
+ {VENC_VDAC_FIFO_CTRL, 0x2000, },
+ {ENCI_DACSEL_0, 0x0011 },
+ {ENCI_DACSEL_1, 0x11 },
+ {ENCI_VIDEO_EN, 1, },
+ {ENCI_VIDEO_SAT, 0x7 },
+ {VENC_VDAC_DAC0_FILT_CTRL0, 0x1 },
+ {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 },
+ {ENCI_MACV_N0, 0x0 },
+ {ENCI_VIDEO_CONT, 0x0 },
+ {MREG_END_MARKER, 0 }
+};
+
+static const struct reg_s tvregs_480cvbs_enc[] = {
+ {ENCI_CFILT_CTRL, 0x12, },
+ {ENCI_CFILT_CTRL2, 0x12, },
+ {VENC_DVI_SETTING, 0, },
+ {ENCI_VIDEO_MODE, 0, },
+ {ENCI_VIDEO_MODE_ADV, 0, },
+ {ENCI_SYNC_HSO_BEGIN, 5, },
+ {ENCI_SYNC_HSO_END, 129, },
+ {ENCI_SYNC_VSO_EVNLN, 0x0003 },
+ {ENCI_SYNC_VSO_ODDLN, 0x0104 },
+ {ENCI_MACV_MAX_AMP, 0x810b },
+ {VENC_VIDEO_PROG_MODE, 0xf0 },
+ {ENCI_VIDEO_MODE, 0x08 },
+ {ENCI_VIDEO_MODE_ADV, 0x26, },
+ {ENCI_VIDEO_SCH, 0x20, },
+ {ENCI_SYNC_MODE, 0x07, },
+ {ENCI_YC_DELAY, 0x333, },
+ {ENCI_VFIFO2VD_PIXEL_START, 0xe3, },
+ {ENCI_VFIFO2VD_PIXEL_END, 0x0683, },
+ {ENCI_VFIFO2VD_LINE_TOP_START, 0x12, },
+ {ENCI_VFIFO2VD_LINE_TOP_END, 0x102, },
+ {ENCI_VFIFO2VD_LINE_BOT_START, 0x13, },
+ {ENCI_VFIFO2VD_LINE_BOT_END, 0x103, },
+ {VENC_SYNC_ROUTE, 0, },
+ {ENCI_DBG_PX_RST, 0, },
+ {VENC_INTCTRL, 0x2, },
+ {ENCI_VFIFO2VD_CTL, 0x4e01, },
+ {VENC_VDAC_SETTING, 0, },
+ {VENC_UPSAMPLE_CTRL0, 0x0061, },
+ {VENC_UPSAMPLE_CTRL1, 0x4061, },
+ {VENC_UPSAMPLE_CTRL2, 0x5061, },
+ {VENC_VDAC_DACSEL0, 0x0000, },
+ {VENC_VDAC_DACSEL1, 0x0000, },
+ {VENC_VDAC_DACSEL2, 0x0000, },
+ {VENC_VDAC_DACSEL3, 0x0000, },
+ {VENC_VDAC_DACSEL4, 0x0000, },
+ {VENC_VDAC_DACSEL5, 0x0000, },
+ {VENC_VDAC_FIFO_CTRL, 0x2000, },
+ {ENCI_DACSEL_0, 0x0011 },
+ {ENCI_DACSEL_1, 0x11 },
+ {ENCI_VIDEO_EN, 1, },
+ {ENCI_VIDEO_SAT, 0x12 },
+ {VENC_VDAC_DAC0_FILT_CTRL0, 0x1 },
+ {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 },
+ {ENCI_MACV_N0, 0x0 },
+ {ENCI_SYNC_ADJ, 0x9c00 },
+ {ENCI_VIDEO_CONT, 0x3 },
+ {MREG_END_MARKER, 0 }
+};
+
+static const struct reg_s tvregs_pal_m_enc[] = {
+ {ENCI_CFILT_CTRL, 0x12, },
+ {ENCI_CFILT_CTRL2, 0x12, },
+ {VENC_DVI_SETTING, 0, },
+ {ENCI_VIDEO_MODE, 0, },
+ {ENCI_VIDEO_MODE_ADV, 0, },
+ {ENCI_SYNC_HSO_BEGIN, 5, },
+ {ENCI_SYNC_HSO_END, 129, },
+ {ENCI_SYNC_VSO_EVNLN, 0x0003 },
+ {ENCI_SYNC_VSO_ODDLN, 0x0104 },
+ {ENCI_MACV_MAX_AMP, 0x810b },
+ {VENC_VIDEO_PROG_MODE, 0xf0 },
+ {ENCI_VIDEO_MODE, 0x2a },
+ {ENCI_VIDEO_MODE_ADV, 0x26, },
+ {ENCI_VIDEO_SCH, 0x20, },
+ {ENCI_SYNC_MODE, 0x07, },
+ {ENCI_YC_DELAY, 0x333, },
+ {ENCI_VFIFO2VD_PIXEL_START, 0xe3, },
+ {ENCI_VFIFO2VD_PIXEL_END, 0x0683,},
+ {ENCI_VFIFO2VD_LINE_TOP_START, 0x12, },
+ {ENCI_VFIFO2VD_LINE_TOP_END, 0x102, },
+ {ENCI_VFIFO2VD_LINE_BOT_START, 0x13, },
+ {ENCI_VFIFO2VD_LINE_BOT_END, 0x103, },
+ {VENC_SYNC_ROUTE, 0, },
+ {ENCI_DBG_PX_RST, 0, },
+ {VENC_INTCTRL, 0x2, },
+ {ENCI_VFIFO2VD_CTL, 0x4e01,},
+ {VENC_VDAC_SETTING, 0, },
+ {VENC_UPSAMPLE_CTRL0, 0x0061,},
+ {VENC_UPSAMPLE_CTRL1, 0x4061,},
+ {VENC_UPSAMPLE_CTRL2, 0x5061,},
+ {VENC_VDAC_DACSEL0, 0x0000,},
+ {VENC_VDAC_DACSEL1, 0x0000,},
+ {VENC_VDAC_DACSEL2, 0x0000,},
+ {VENC_VDAC_DACSEL3, 0x0000,},
+ {VENC_VDAC_DACSEL4, 0x0000,},
+ {VENC_VDAC_DACSEL5, 0x0000,},
+ {VENC_VDAC_FIFO_CTRL, 0x2000,},
+ {ENCI_DACSEL_0, 0x0011 },
+ {ENCI_DACSEL_1, 0x11 },
+ {ENCI_VIDEO_EN, 1, },
+ {ENCI_VIDEO_SAT, 0x12 },
+ {VENC_VDAC_DAC0_FILT_CTRL0, 0x1 },
+ {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 },
+ {ENCI_MACV_N0, 0x0 },
+ {ENCI_SYNC_ADJ, 0x9c00 },
+ {ENCI_VIDEO_CONT, 0x3 },
+ {MREG_END_MARKER, 0 }
+};
+
+static const struct reg_s tvregs_pal_n_enc[] = {
+ {ENCI_CFILT_CTRL, 0x12, },
+ {ENCI_CFILT_CTRL2, 0x12, },
+ {VENC_DVI_SETTING, 0, },
+ {ENCI_VIDEO_MODE, 0, },
+ {ENCI_VIDEO_MODE_ADV, 0, },
+ {ENCI_SYNC_HSO_BEGIN, 3, },
+ {ENCI_SYNC_HSO_END, 129, },
+ {ENCI_SYNC_VSO_EVNLN, 0x0003 },
+ {ENCI_SYNC_VSO_ODDLN, 0x0104 },
+ {ENCI_MACV_MAX_AMP, 0x8107 },
+ {VENC_VIDEO_PROG_MODE, 0xff },
+ {ENCI_VIDEO_MODE, 0x3b },
+ {ENCI_VIDEO_MODE_ADV, 0x26, },
+ {ENCI_VIDEO_SCH, 0x28, },
+ {ENCI_SYNC_MODE, 0x07, },
+ {ENCI_YC_DELAY, 0x333, },
+ {ENCI_VFIFO2VD_PIXEL_START, 0x0fb },
+ {ENCI_VFIFO2VD_PIXEL_END, 0x069b },
+ {ENCI_VFIFO2VD_LINE_TOP_START, 0x0016 },
+ {ENCI_VFIFO2VD_LINE_TOP_END, 0x0136 },
+ {ENCI_VFIFO2VD_LINE_BOT_START, 0x0017 },
+ {ENCI_VFIFO2VD_LINE_BOT_END, 0x0137 },
+ {VENC_SYNC_ROUTE, 0, },
+ {ENCI_DBG_PX_RST, 0, },
+ {VENC_INTCTRL, 0x2, },
+ {ENCI_VFIFO2VD_CTL, 0x4e01, },
+ {VENC_VDAC_SETTING, 0, },
+ {VENC_UPSAMPLE_CTRL0, 0x0061, },
+ {VENC_UPSAMPLE_CTRL1, 0x4061, },
+ {VENC_UPSAMPLE_CTRL2, 0x5061, },
+ {VENC_VDAC_DACSEL0, 0x0000, },
+ {VENC_VDAC_DACSEL1, 0x0000, },
+ {VENC_VDAC_DACSEL2, 0x0000, },
+ {VENC_VDAC_DACSEL3, 0x0000, },
+ {VENC_VDAC_DACSEL4, 0x0000, },
+ {VENC_VDAC_DACSEL5, 0x0000, },
+ {VENC_VDAC_FIFO_CTRL, 0x2000, },
+ {ENCI_DACSEL_0, 0x0011 },
+ {ENCI_DACSEL_1, 0x11 },
+ {ENCI_VIDEO_EN, 1, },
+ {ENCI_VIDEO_SAT, 0x7 },
+ {VENC_VDAC_DAC0_FILT_CTRL0, 0x1 },
+ {VENC_VDAC_DAC0_FILT_CTRL1, 0xfc48 },
+ {ENCI_MACV_N0, 0x0 },
+ {ENCI_VIDEO_CONT, 0x0 },
+ {MREG_END_MARKER, 0 }
+};
+
diff --git a/drivers/amlogic/media/vout/cvbs/cvbs_dummy_reg.h b/drivers/amlogic/media/vout/cvbs/cvbs_dummy_reg.h
new file mode 100644
index 0000000..434235f
--- /dev/null
+++ b/drivers/amlogic/media/vout/cvbs/cvbs_dummy_reg.h
@@ -0,0 +1,139 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __CVBS_DUMMY_REG_H__
+#define __CVBS_DUMMY_REG_H__
+
+#ifndef REG_BASE_VCBUS
+#define REG_BASE_VCBUS (0xff900000L)
+#endif
+
+#ifndef HHI_VDAC_CNTL0
+#define HHI_VDAC_CNTL0 (0xff63c000 + (0x0bb << 2))
+#endif
+#ifndef HHI_VDAC_CNTL1
+#define HHI_VDAC_CNTL1 (0xff63c000 + (0x0bc << 2))
+#endif
+
+#ifndef ANACTRL_VDAC_CTRL0
+#define ANACTRL_VDAC_CTRL0 ((0x00b0 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_VDAC_CTRL1
+#define ANACTRL_VDAC_CTRL1 ((0x00b1 << 2) + 0xfe008000)
+#endif
+
+#ifndef HHI_GP0_PLL_CNTL0
+#define HHI_GP0_PLL_CNTL0 (0xff63c000 + (0x010 << 2))
+#endif
+#ifndef HHI_GP0_PLL_CNTL1
+#define HHI_GP0_PLL_CNTL1 (0xff63c000 + (0x11 << 2))
+#endif
+#ifndef HHI_GP0_PLL_CNTL2
+#define HHI_GP0_PLL_CNTL2 (0xff63c000 + (0x12 << 2))
+#endif
+#ifndef HHI_GP0_PLL_CNTL3
+#define HHI_GP0_PLL_CNTL3 (0xff63c000 + (0x13 << 2))
+#endif
+#ifndef HHI_GP0_PLL_CNTL4
+#define HHI_GP0_PLL_CNTL4 (0xff63c000 + (0x14 << 2))
+#endif
+#ifndef HHI_GP0_PLL_CNTL5
+#define HHI_GP0_PLL_CNTL5 (0xff63c000 + (0x15 << 2))
+#endif
+#ifndef HHI_GP0_PLL_CNTL6
+#define HHI_GP0_PLL_CNTL6 (0xff63c000 + (0x016 << 2))
+#endif
+
+#ifndef HHI_HDMI_PLL_CNTL
+#define HHI_HDMI_PLL_CNTL (0xff63c000 + (0xc8 << 2))
+#endif
+#ifndef HHI_HDMI_PLL_CNTL0
+#define HHI_HDMI_PLL_CNTL0 (0xff63c000 + (0xc8 << 2))
+#endif
+#ifndef HHI_HDMI_PLL_CNTL1
+#define HHI_HDMI_PLL_CNTL1 (0xff63c000 + (0xc9 << 2))
+#endif
+#ifndef HHI_HDMI_PLL_CNTL2
+#define HHI_HDMI_PLL_CNTL2 (0xff63c000 + (0xca << 2))
+#endif
+#ifndef HHI_HDMI_PLL_CNTL3
+#define HHI_HDMI_PLL_CNTL3 (0xff63c000 + (0xcb << 2))
+#endif
+#ifndef HHI_HDMI_PLL_CNTL4
+#define HHI_HDMI_PLL_CNTL4 (0xff63c000 + (0xcd << 2))
+#endif
+#ifndef HHI_HDMI_PLL_CNTL5
+#define HHI_HDMI_PLL_CNTL5 (0xff63c000 + (0xcd << 2))
+#endif
+#ifndef HHI_HDMI_PLL_CNTL6
+#define HHI_HDMI_PLL_CNTL6 (0xff63c000 + (0xce << 2))
+#endif
+
+#ifndef HHI_VID_PLL_CLK_DIV
+#define HHI_VID_PLL_CLK_DIV (0xff63c000 + (0x068 << 2))
+#endif
+
+#ifndef HHI_VIID_CLK_DIV
+#define HHI_VIID_CLK_DIV (0xff63c000 + (0x04a << 2))
+#endif
+
+#ifndef HHI_VIID_CLK_CNTL
+#define HHI_VIID_CLK_CNTL (0xff63c000 + (0x04b << 2))
+#endif
+
+#ifndef HHI_VID_CLK_DIV
+#define HHI_VID_CLK_DIV (0xff63c000 + (0x059 << 2))
+#endif
+
+#ifndef HHI_VID_CLK_CNTL2
+#define HHI_VID_CLK_CNTL2 (0xff63c000 + (0x065 << 2))
+#endif
+
+#ifndef HHI_VID_CLK_CNTL
+#define HHI_VID_CLK_CNTL (0xff63c000 + (0x05f << 2))
+#endif
+
+#ifndef ANACTRL_HDMIPLL_CTRL0
+#define ANACTRL_HDMIPLL_CTRL0 ((0x0070 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_HDMIPLL_CTRL1
+#define ANACTRL_HDMIPLL_CTRL1 ((0x0071 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_HDMIPLL_CTRL2
+#define ANACTRL_HDMIPLL_CTRL2 ((0x0072 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_HDMIPLL_CTRL3
+#define ANACTRL_HDMIPLL_CTRL3 ((0x0073 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_HDMIPLL_CTRL4
+#define ANACTRL_HDMIPLL_CTRL4 ((0x0074 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_HDMIPLL_CTRL5
+#define ANACTRL_HDMIPLL_CTRL5 ((0x0075 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_HDMIPLL_CTRL6
+#define ANACTRL_HDMIPLL_CTRL6 ((0x0076 << 2) + 0xfe008000)
+#endif
+
+#ifndef CLKCTRL_VID_CLK_CTRL
+#define CLKCTRL_VID_CLK_CTRL ((0x0030 << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_VID_CLK_CTRL2
+#define CLKCTRL_VID_CLK_CTRL2 ((0x0031 << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_VID_CLK_DIV
+#define CLKCTRL_VID_CLK_DIV ((0x0032 << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_VIID_CLK_DIV
+#define CLKCTRL_VIID_CLK_DIV ((0x0033 << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_VIID_CLK_CTRL
+#define CLKCTRL_VIID_CLK_CTRL ((0x0034 << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_VID_PLL_CLK_DIV
+#define CLKCTRL_VID_PLL_CLK_DIV ((0x0039 << 2) + 0xfe000000)
+#endif
+
+#endif
\ No newline at end of file
diff --git a/drivers/amlogic/media/vout/cvbs/cvbs_reg.h b/drivers/amlogic/media/vout/cvbs/cvbs_reg.h
new file mode 100644
index 0000000..c3ee332
--- /dev/null
+++ b/drivers/amlogic/media/vout/cvbs/cvbs_reg.h
@@ -0,0 +1,109 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __CVBS_REG_H__
+#define __CVBS_REG_H__
+#include <asm/arch/io.h>
+#include <asm/arch/secure_apb.h>
+#include "cvbs.h"
+#include "cvbs_dummy_reg.h"
+
+// encoder registers
+#define BUS_TYPE_CBUS 0
+#define BUS_TYPE_HIU 1
+#define BUS_TYPE_VCBUS 2
+
+#define DAC0_CLK_SEL 28
+#define DAC1_CLK_SEL 24
+#define DAC2_CLK_SEL 20
+#define VCLK2_XD_RST 17
+#define VCLK2_XD_EN 16
+#define ENCL_CLK_SEL 12
+#define VCLK2_XD 0
+#define VCLK_XD0 0
+#define VCLK_CLK_IN_SEL 16
+#define VCLK_EN0 19
+#define VCLK_XD_EN 16
+#define VCLK_DIV1_EN 0
+#define VCLK_SOFT_RST 15
+
+#define VCLK2_EN 19
+#define VCLK2_CLK_IN_SEL 16
+#define VCLK2_SOFT_RST 15
+#define VCLK2_DIV12_EN 4
+#define VCLK2_DIV6_EN 3
+#define VCLK2_DIV4_EN 2
+#define VCLK2_DIV2_EN 1
+#define VCLK2_DIV1_EN 0
+
+/* ********************************
+ * register define
+ * ********************************* */
+
+#define CVBS_REG_OFFSET_VCBUS(reg) (((reg) << 2))
+
+#define CVBS_REG_ADDR(reg) (reg + 0L)
+#define CVBS_REG_ADDR_HIU(reg) (reg + 0L)
+#define CVBS_REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + CVBS_REG_OFFSET_VCBUS(reg))
+
+/* ********************************
+ * register access api
+ * ********************************* */
+static inline int cvbs_write_hiu(unsigned int addr, unsigned int value)
+{
+ *(volatile unsigned int *)CVBS_REG_ADDR_HIU(addr) = (value);
+ return 0;
+}
+
+static inline int cvbs_read_hiu(unsigned int addr)
+{
+ unsigned int val = 0;
+
+ val = *(volatile unsigned int *)(CVBS_REG_ADDR_HIU(addr));
+ return val;
+}
+
+static inline int cvbs_set_hiu_bits(unsigned int addr, unsigned int value, unsigned int start, unsigned int len)
+{
+ cvbs_write_hiu(addr, ((cvbs_read_hiu(addr) &
+ ~(((1L << (len))-1) << (start))) |
+ (((value)&((1L<<(len))-1)) << (start))));
+ return 0;
+}
+
+static inline int cvbs_get_hiu_bits(unsigned int addr, unsigned int start, unsigned int len)
+{
+ return (cvbs_read_hiu(addr) >> (start)) & ((1L << (len)) - 1);
+}
+
+static inline unsigned int cvbs_read_vcbus(unsigned int addr_offset)
+{
+ unsigned int val = 0;
+
+ if (addr_offset > 0x10000)
+ val = *(volatile unsigned int *)(CVBS_REG_ADDR(addr_offset));
+ else
+ val = *(volatile unsigned int *)(CVBS_REG_ADDR_VCBUS(addr_offset));
+ return val;
+}
+
+static inline int cvbs_write_vcbus(unsigned int addr_offset, unsigned int value)
+{
+ if (addr_offset > 0x10000)
+ *(volatile unsigned int *)CVBS_REG_ADDR(addr_offset) = (value);
+ else
+ *(volatile unsigned int *)CVBS_REG_ADDR_VCBUS(addr_offset) = (value);
+ return 0;
+}
+
+static inline int cvbs_set_vcbus_bits(unsigned int addr_offset, unsigned int value, unsigned int start, unsigned int len)
+{
+ cvbs_write_vcbus(addr_offset, ((cvbs_read_vcbus(addr_offset) &
+ ~(((1L << (len))-1) << (start))) |
+ (((value)&((1L<<(len))-1)) << (start))));
+ return 0;
+}
+
+#endif
diff --git a/drivers/amlogic/media/vout/cvbs/vdac.c b/drivers/amlogic/media/vout/cvbs/vdac.c
new file mode 100644
index 0000000..e3eb433
--- /dev/null
+++ b/drivers/amlogic/media/vout/cvbs/vdac.c
@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/cpu.h>
+#include <amlogic/cpu_id.h>
+#include "vdac.h"
+#include "cvbs_reg.h"
+
+static struct vdac_data_s *vdac_data;
+static unsigned int pri_flag;
+
+#define REG_ADDR_VDAC(reg) (reg + 0L)
+
+static void vdac_write_reg(unsigned int addr, unsigned int val)
+{
+ *(volatile unsigned int *)REG_ADDR_VDAC(addr) = (val);
+}
+
+static unsigned int vdac_read_reg(unsigned int addr)
+{
+ return *(volatile unsigned int *)(REG_ADDR_VDAC(addr));
+}
+
+static void vdac_set_reg_bits(unsigned int addr, unsigned int val,
+ unsigned int start, unsigned int len)
+{
+ vdac_write_reg(addr, ((vdac_read_reg(addr) &
+ ~(((1L << (len))-1) << (start))) |
+ (((val)&((1L<<(len))-1)) << (start))));
+}
+
+static inline unsigned int vdac_get_reg_bits(unsigned int reg,
+ unsigned int start, unsigned int len)
+{
+ unsigned int val;
+
+ val = ((vdac_read_reg(reg) >> (start)) & ((1L << (len)) - 1));
+
+ return val;
+}
+
+static int vdac_ctrl_config(bool on, unsigned int reg, unsigned int bit)
+{
+ struct meson_vdac_ctrl_s *vdac_ctrl;
+ unsigned int val;
+ int i = 0;
+ int ret = -1;
+
+ if (!vdac_data) {
+ printf("%s: vdac_data is NULL\n", __func__);
+ return ret;
+ }
+
+ if (!vdac_data->vdac_ctrl) {
+ printf("%s: vdac_ctrl is NULL\n", __func__);
+ return ret;
+ }
+
+ vdac_ctrl = vdac_data->vdac_ctrl;
+ while (i < VDAC_CTRL_MAX) {
+ if (vdac_ctrl[i].reg == VDAC_REG_MAX)
+ break;
+ if ((vdac_ctrl[i].reg == reg) && (vdac_ctrl[i].bit == bit)) {
+ if (on)
+ val = vdac_ctrl[i].val;
+ else
+ val = vdac_ctrl[i].val ? 0 : 1;
+ vdac_set_reg_bits(reg, val, bit, vdac_ctrl[i].len);
+ //if (vdac_debug_print) {
+ // printf("vdac: reg=0x%02x set bit%d=%d, readback=0x%08x\n",
+ // reg, bit, val, vdac_hiu_reg_read(reg));
+ //}
+ ret = 0;
+ break;
+ }
+ i++;
+ }
+
+ return ret;
+}
+
+static void vdac_enable_dac_input(unsigned int reg_cntl0)
+{
+ vdac_set_reg_bits(reg_cntl0, 0x2, 0, 3);
+ vdac_set_reg_bits(reg_cntl0, 0x1, 4, 1);
+ vdac_set_reg_bits(reg_cntl0, 0x1, 6, 1);
+ vdac_set_reg_bits(reg_cntl0, 0x3, 13, 3);
+ vdac_set_reg_bits(reg_cntl0, 0x10, 18, 5);
+}
+
+static void vdac_enable_cvbs_out(bool on)
+{
+ unsigned int reg_cntl0;
+ unsigned int reg_cntl1;
+
+ if (!vdac_data) {
+ printf("%s: vdac_data is NULL\n", __func__);
+ return;
+ }
+
+ reg_cntl0 = vdac_data->reg_ctrl0;
+ reg_cntl1 = vdac_data->reg_ctrl1;
+
+ if (on) {
+ if (vdac_data->cpu_id == VDAC_CPU_S4) {
+ vdac_enable_dac_input(reg_cntl0);
+ vdac_ctrl_config(1, reg_cntl1, 7);
+ } else {
+ vdac_set_reg_bits(reg_cntl0, 0x6, 12, 4);
+ vdac_ctrl_config(1, reg_cntl1, 3);
+ vdac_ctrl_config(1, reg_cntl0, 0);
+ vdac_ctrl_config(1, reg_cntl0, 9);
+ }
+ } else {
+ if (vdac_data->cpu_id == VDAC_CPU_S4) {
+ vdac_set_reg_bits(reg_cntl0, 0x0, 4, 1);
+ vdac_ctrl_config(0, reg_cntl1, 7);
+ } else {
+ vdac_ctrl_config(0, reg_cntl0, 9);
+ vdac_ctrl_config(0, reg_cntl0, 0);
+ vdac_ctrl_config(0, reg_cntl1, 3);
+ }
+ }
+}
+
+void vdac_enable(bool on, unsigned int module_sel)
+{
+ if (!vdac_data) {
+ printf("%s: vdac_data is NULL\n", __func__);
+ return;
+ }
+
+ printf("%s: %d, module_sel:0x%x\n", __func__, on, module_sel);
+
+ switch (module_sel) {
+ case VDAC_MODULE_CVBS_OUT:
+ if (on) {
+ pri_flag |= VDAC_MODULE_CVBS_OUT;
+ vdac_enable_cvbs_out(1);
+ } else {
+ pri_flag &= ~VDAC_MODULE_CVBS_OUT;
+ vdac_enable_cvbs_out(0);
+ }
+ break;
+ default:
+ printf("%s:module_sel: 0x%x wrong module index !! ",
+ __func__, module_sel);
+ break;
+ }
+
+ if (vdac_data->cpu_id == VDAC_CPU_S4) {
+ if (!vdac_get_reg_bits(vdac_data->reg_ctrl0, 11, 1))
+ vdac_set_reg_bits(vdac_data->reg_ctrl0, 1, 11, 1);
+ }
+}
+
+int vdac_ctrl_vref_adj(unsigned int value)
+{
+ struct meson_vdac_ctrl_s *vdac_ctrl;
+ unsigned int reg;
+ unsigned int bit = 16;
+ int i = 0;
+ int ret = -1;
+
+ if (!vdac_data) {
+ printf("%s: vdac_data is NULL\n", __func__);
+ return ret;
+ }
+
+ if (!vdac_data->vdac_ctrl) {
+ printf("%s: vdac_ctrl is NULL\n", __func__);
+ return ret;
+ }
+
+ vdac_ctrl = vdac_data->vdac_ctrl;
+ reg = vdac_data->reg_ctrl0;
+ while (i < VDAC_CTRL_MAX) {
+ if (vdac_ctrl[i].reg == VDAC_REG_MAX)
+ break;
+ if ((vdac_ctrl[i].reg == reg) && (vdac_ctrl[i].bit == bit)) {
+ vdac_set_reg_bits(reg, value, bit, vdac_ctrl[i].len);
+ //if (vdac_debug_print) {
+ // printf("vdac: reg=0x%x set bit%d=0x%x, readback=0x%08x\n",
+ // reg, bit, value, vdac_hiu_reg_read(reg));
+ //}
+ ret = 0;
+ break;
+ }
+ i++;
+ }
+
+ return ret;
+}
+
+static struct meson_vdac_ctrl_s vdac_ctrl_enable_g12ab[] = {
+ {HHI_VDAC_CNTL0, 0, 9, 1},
+ {HHI_VDAC_CNTL0, 1, 0, 1},
+ {HHI_VDAC_CNTL0, 0, 16, 5}, /* vref adj */
+ {HHI_VDAC_CNTL1, 0, 0, 3}, /*gsw */
+ {HHI_VDAC_CNTL1, 0, 3, 1},
+ {VDAC_REG_MAX, 0, 0, 0},
+};
+
+static struct meson_vdac_ctrl_s vdac_ctrl_enable_sc2[] = {
+ {ANACTRL_VDAC_CTRL0, 0, 9, 1},
+ {ANACTRL_VDAC_CTRL0, 1, 0, 1},
+ {ANACTRL_VDAC_CTRL0, 0, 16, 5}, /* vref adj */
+ {ANACTRL_VDAC_CTRL1, 0, 0, 3}, /*gsw */
+ {ANACTRL_VDAC_CTRL1, 0, 3, 1},
+ {ANACTRL_VDAC_CTRL1, 0, 7, 1}, /* bandgap */
+ {VDAC_REG_MAX, 0, 0, 0},
+};
+
+static struct meson_vdac_ctrl_s vdac_ctrl_enable_s4[] = {
+ {ANACTRL_VDAC_CTRL0, 0, 9, 1},
+ {ANACTRL_VDAC_CTRL0, 1, 0, 1},
+ {ANACTRL_VDAC_CTRL1, 1, 7, 1}, /* cdac_pwd */
+ {VDAC_REG_MAX, 0, 0, 0},
+};
+
+struct vdac_data_s vdac_data_g12ab = {
+ .cpu_id = VDAC_CPU_G12AB,
+ .reg_ctrl0 = HHI_VDAC_CNTL0,
+ .reg_ctrl1 = HHI_VDAC_CNTL1,
+ .vdac_ctrl = vdac_ctrl_enable_g12ab,
+};
+
+struct vdac_data_s vdac_data_sc2 = {
+ .cpu_id = VDAC_CPU_SC2,
+ .reg_ctrl0 = ANACTRL_VDAC_CTRL0,
+ .reg_ctrl1 = ANACTRL_VDAC_CTRL1,
+ .vdac_ctrl = vdac_ctrl_enable_sc2,
+};
+
+struct vdac_data_s vdac_data_s4 = {
+ .cpu_id = VDAC_CPU_S4,
+ .reg_ctrl0 = ANACTRL_VDAC_CTRL0,
+ .reg_ctrl1 = ANACTRL_VDAC_CTRL1,
+ .vdac_ctrl = vdac_ctrl_enable_s4,
+};
+
+void vdac_ctrl_config_probe(void)
+{
+ pri_flag = 0;
+
+ switch (get_cpu_id().family_id) {
+ case MESON_CPU_MAJOR_ID_G12A:
+ case MESON_CPU_MAJOR_ID_G12B:
+ vdac_data = &vdac_data_g12ab;
+ break;
+ case MESON_CPU_MAJOR_ID_SC2:
+ vdac_data = &vdac_data_sc2;
+ break;
+ case MESON_CPU_MAJOR_ID_S4:
+ vdac_data = &vdac_data_s4;
+ default:
+ vdac_data = &vdac_data_s4;
+ break;
+ }
+
+ return;
+}
diff --git a/drivers/amlogic/media/vout/cvbs/vdac.h b/drivers/amlogic/media/vout/cvbs/vdac.h
new file mode 100644
index 0000000..041d879
--- /dev/null
+++ b/drivers/amlogic/media/vout/cvbs/vdac.h
@@ -0,0 +1,45 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _AML_VDAC_H
+#define _AML_VDAC_H
+
+#define VDAC_MODULE_MASK (0x1f)
+#define VDAC_MODULE_AVOUT_ATV (1 << 0) /*0x1*/
+#define VDAC_MODULE_DTV_DEMOD (1 << 1) /*0x2*/
+#define VDAC_MODULE_AVOUT_AV (1 << 2) /*0x4*/
+#define VDAC_MODULE_CVBS_OUT (1 << 3) /*0x8*/
+#define VDAC_MODULE_AUDIO_OUT (1 << 4) /*0x10*/
+
+#define VDAC_CTRL_MAX 10
+
+#define VDAC_REG_MAX 0xffff
+
+enum vdac_cpu_type {
+ VDAC_CPU_G12AB = 0,
+ VDAC_CPU_SC2 = 1,
+ VDAC_CPU_S4 = 2,
+ VDAC_CPU_MAX,
+};
+
+struct meson_vdac_ctrl_s {
+ unsigned int reg;
+ unsigned int val;
+ unsigned int bit;
+ unsigned int len;
+};
+
+struct vdac_data_s {
+ enum vdac_cpu_type cpu_id;
+ unsigned int reg_ctrl0;
+ unsigned int reg_ctrl1;
+ struct meson_vdac_ctrl_s *vdac_ctrl;
+};
+
+void vdac_enable(bool on, unsigned int module_sel);
+int vdac_ctrl_vref_adj(unsigned int value);
+void vdac_ctrl_config_probe(void);
+
+#endif
diff --git a/drivers/amlogic/media/vout/hdmitx/Kconfig b/drivers/amlogic/media/vout/hdmitx/Kconfig
index 4817412..2250598 100644
--- a/drivers/amlogic/media/vout/hdmitx/Kconfig
+++ b/drivers/amlogic/media/vout/hdmitx/Kconfig
@@ -1,5 +1,11 @@
+menu "AMLOGIC HDMI TX Drivers"
+
config AML_HDMITX
- bool "AML Hdmitx drivers Support"
+ bool "Amlogic HDMITX drivers Support"
+ depends on AML_VOUT
help
HDMITX Output Enable
+source "drivers/amlogic/media/vout/hdmitx/hdmitx20/Kconfig"
+
+endmenu
diff --git a/drivers/amlogic/media/vout/hdmitx/Makefile b/drivers/amlogic/media/vout/hdmitx/Makefile
index 70b1813..53bab1c 100644
--- a/drivers/amlogic/media/vout/hdmitx/Makefile
+++ b/drivers/amlogic/media/vout/hdmitx/Makefile
@@ -1,11 +1,4 @@
-#
-# (C) Copyright 2018
-#
+# SPDX-License-Identifier: GPL-2.0+
-#EXTRA_CFLAGS = -Idrivers/video/include/
-
-obj-y += hdmitx.o
-
-hdmitx-y := hdmitx_set.o hdmitx_tvenc.o enc_clk_config.o hdmi_edid_parsing.o hdmi_parameters.o
-#aml_hdmitx20-$(CONFIG_AML_HDMITX20_HDCP) += hdmitx_hdcp.o
-
+obj-$(CONFIG_AML_HDMITX20) += hdmitx20/
+obj-$(CONFIG_AML_HDMITX20) += sound.o
diff --git a/drivers/amlogic/media/vout/hdmitx/enc_clk_config.c b/drivers/amlogic/media/vout/hdmitx/enc_clk_config.c
deleted file mode 100644
index 646a1f0..0000000
--- a/drivers/amlogic/media/vout/hdmitx/enc_clk_config.c
+++ /dev/null
@@ -1,632 +0,0 @@
-/*
- * driver/amlogic/media/vout/hdmitx/enc_clk_config.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <amlogic/enc_clk_config.h>
-#include <asm/arch/register.h>
-#include <asm/arch/secure_apb.h>
-
-#include "hdmitx_common.h"
-#include <amlogic/media/vout/hdmitx.h>
-
-#define msleep(i) udelay(i*1000)
-
-#define check_clk_config(para)\
- if (para == -1)\
- return;
-
-#define check_div() \
- if (div == -1)\
- return ;\
- switch (div) {\
- case 1:\
- div = 0; break;\
- case 2:\
- div = 1; break;\
- case 4:\
- div = 2; break;\
- case 6:\
- div = 3; break;\
- case 12:\
- div = 4; break;\
- default:\
- break;\
- }
-
-/* viu_channel_sel: 1 or 2*/
-/* viu_type_sel: 0: 0=ENCL, 1=ENCI, 2=ENCP, 3=ENCT.*/
-int set_viu_path(unsigned viu_channel_sel, enum viu_type viu_type_sel)
-{
- if ((viu_channel_sel > 2) || (viu_channel_sel == 0))
- return -1;
- if (viu_channel_sel == 1)
- hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 0, 2);
- else
- /* viu_channel_sel ==2*/
- hd_set_reg_bits(P_VPU_VIU_VENC_MUX_CTRL, viu_type_sel, 2, 2);
- return 0;
-}
-
-static void set_hdmitx_sys_clk(void)
-{
- hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 9, 3);
- hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0, 0, 7);
- hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 1, 8, 1);
-}
-
-
-/* --------------------------------------------------
- * clocks_set_vid_clk_div
- * --------------------------------------------------
- * wire clk_final_en = control[19];
- * wire clk_div1 = control[18];
- * wire [1:0] clk_sel = control[17:16];
- * wire set_preset = control[15];
- * wire [14:0] shift_preset = control[14:0];
- */
-static void set_hpll_od3_clk_div(int div_sel)
-{
- int shift_val = 0;
- int shift_sel = 0;
-
- /* When div 6.25, need to reset vid_pll_div */
- if (div_sel == CLK_UTIL_VID_PLL_DIV_6p25) {
- msleep(1);
- hd_set_reg_bits(P_RESET0_REGISTER, 1, 7, 1);
- }
- /* Disable the output clock */
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 19, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
-
- switch (div_sel) {
- case CLK_UTIL_VID_PLL_DIV_1: shift_val = 0xFFFF; shift_sel = 0; break;
- case CLK_UTIL_VID_PLL_DIV_2: shift_val = 0x0aaa; shift_sel = 0; break;
- case CLK_UTIL_VID_PLL_DIV_3: shift_val = 0x0db6; shift_sel = 0; break;
- case CLK_UTIL_VID_PLL_DIV_3p5: shift_val = 0x36cc; shift_sel = 1; break;
- case CLK_UTIL_VID_PLL_DIV_3p75: shift_val = 0x6666; shift_sel = 2; break;
- case CLK_UTIL_VID_PLL_DIV_4: shift_val = 0x0ccc; shift_sel = 0; break;
- case CLK_UTIL_VID_PLL_DIV_5: shift_val = 0x739c; shift_sel = 2; break;
- case CLK_UTIL_VID_PLL_DIV_6: shift_val = 0x0e38; shift_sel = 0; break;
- case CLK_UTIL_VID_PLL_DIV_6p25: shift_val = 0x0000; shift_sel = 3; break;
- case CLK_UTIL_VID_PLL_DIV_7: shift_val = 0x3c78; shift_sel = 1; break;
- case CLK_UTIL_VID_PLL_DIV_7p5: shift_val = 0x78f0; shift_sel = 2; break;
- case CLK_UTIL_VID_PLL_DIV_12: shift_val = 0x0fc0; shift_sel = 0; break;
- case CLK_UTIL_VID_PLL_DIV_14: shift_val = 0x3f80; shift_sel = 1; break;
- case CLK_UTIL_VID_PLL_DIV_15: shift_val = 0x7f80; shift_sel = 2; break;
- case CLK_UTIL_VID_PLL_DIV_2p5: shift_val = 0x5294; shift_sel = 2; break;
- case CLK_UTIL_VID_PLL_DIV_3p25: shift_val = 0x66cc; shift_sel = 2; break;
- default:
- printk("Error: clocks_set_vid_clk_div: Invalid parameter\n");
- break;
- }
-
- if (shift_val == 0xffff ) { /*if divide by 1*/
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 1, 18, 1);
- } else {
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 18, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 16, 2);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 0, 14);
-
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_sel, 16, 2);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 1, 15, 1);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, shift_val, 0, 14);
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 0, 15, 1);
- }
- /*Enable the final output clock*/
- hd_set_reg_bits(P_HHI_VID_PLL_CLK_DIV, 1, 19, 1);
-}
-
-static void set_vid_clk_div(unsigned div)
-{
- check_clk_config(div);
- if (div == 0)
- div = 1;
- hd_set_reg_bits(P_HHI_VID_CLK_CNTL, 0, 16, 3); /*select vid_pll_clk*/
- hd_set_reg_bits(P_HHI_VID_CLK_DIV, div-1, 0, 8);
- hd_set_reg_bits(P_HHI_VID_CLK_CNTL, 7, 0, 3);
-}
-
-static void set_hdmi_tx_pixel_div(unsigned div)
-{
- check_div();
- hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, div, 16, 4);
- hd_set_reg_bits(P_HHI_VID_CLK_CNTL2, 1, 5, 1); /*enable gate*/
-}
-
-static void set_encp_div(unsigned div)
-{
- check_div();
- hd_set_reg_bits(P_HHI_VID_CLK_DIV, div, 24, 4);
- hd_set_reg_bits(P_HHI_VID_CLK_CNTL2, 1, 2, 1); /*enable gate*/
- hd_set_reg_bits(P_HHI_VID_CLK_CNTL, 1, 19, 1);
-}
-
-static void set_enci_div(unsigned div)
-{
- check_div();
- hd_set_reg_bits(P_HHI_VID_CLK_DIV, div, 28, 4);
- hd_set_reg_bits(P_HHI_VID_CLK_CNTL2, 1, 0, 1); /*enable gate*/
- hd_set_reg_bits(P_HHI_VID_CLK_CNTL, 1, 19, 1);
-}
-
-/* mode hpll_clk_out od1 od2(PHY) od3
- * vid_pll_div vid_clk_div hdmi_tx_pixel_div encp_div enci_div
- */
-/* For colordepth 8bits */
-static struct hw_enc_clk_val_group setting_enc_clk_val_24[] = {
- {
- {
- HDMI_720x480i60_16x9, HDMI_720x576i50_16x9, GROUP_END
- },
- 1, VIU_ENCI, 4324320, 4, 4, 1, CLK_UTIL_VID_PLL_DIV_5, 1, 2, -1, 2
- },
- {
- {
- HDMI_720x576p50_16x9, HDMI_720x480p60_16x9, GROUP_END
- },
- 1, VIU_ENCP, 4324320, 4, 4, 1, CLK_UTIL_VID_PLL_DIV_5, 1, 2, 1, -1
- },
- {
- {
- HDMI_720x576p100_16x9, HDMI_720x480p120_16x9, GROUP_END
- },
- 1, VIU_ENCP, 4324320, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 1, 2, 1, -1
- },
- {
- {
- HDMI_1280x720p50_16x9, HDMI_1280x720p60_16x9, GROUP_END
- },
- 1, VIU_ENCP, 5940000, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 1, 2, 1, -1
- },
- {
- {
- HDMI_1920x1080i60_16x9, HDMI_1920x1080i50_16x9, GROUP_END
- },
- 1, VIU_ENCP, 5940000, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 1, 2, 1, -1
- },
- {
- {
- HDMI_1920x1080i100_16x9, HDMI_1920x1080i120_16x9,
- HDMI_1280x720p100_16x9, HDMI_1280x720p120_16x9,
- GROUP_END
- },
- 1, VIU_ENCP, 5940000, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 1, 2, 1, -1
- },
- {
- {
- HDMI_1920x1080p60_16x9, HDMI_1920x1080p50_16x9, GROUP_END
- },
- 1, VIU_ENCP, 5940000, 2, 2, 2, CLK_UTIL_VID_PLL_DIV_5, 1, 1, 1, -1
- },
- {
- {
- HDMI_1920x1080p30_16x9, HDMI_1920x1080p24_16x9,
- HDMI_1920x1080p25_16x9, GROUP_END
- },
- 1, VIU_ENCP, 5940000, 4, 2, 2, CLK_UTIL_VID_PLL_DIV_5, 1, 1, 1, -1
- },
- {
- {
- HDMI_3840x2160p30_16x9, HDMI_3840x2160p25_16x9,
- HDMI_3840x2160p24_16x9, HDMI_4096x2160p24_256x135,
- HDMI_4096x2160p25_256x135, HDMI_4096x2160p30_256x135,
- HDMI_1920x1080p100_16x9, HDMI_1920x1080p120_16x9,
- GROUP_END
- },
- 1, VIU_ENCP, 5940000, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
- },
- {
- {
- HDMIV_2160x1200p90hz, GROUP_END
- },
- 1, VIU_ENCP, 5371100, 1, 2, 2, CLK_UTIL_VID_PLL_DIV_5, 1, 1, 1, -1
- },
- {
- {
- HDMI_3840x2160p60_16x9, HDMI_3840x2160p50_16x9,
- HDMI_4096x2160p60_256x135, HDMI_4096x2160p50_256x135,
- GROUP_END
- },
- 1, VIU_ENCP, 5940000, 1, 1, 2, CLK_UTIL_VID_PLL_DIV_5, 1, 1, 1, -1
- },
- {
- {
- HDMI_4096x2160p60_256x135_Y420,
- HDMI_4096x2160p50_256x135_Y420,
- HDMI_3840x2160p60_16x9_Y420,
- HDMI_3840x2160p50_16x9_Y420,
- GROUP_END
- },
- 1, VIU_ENCP, 5940000, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 1, 2, 1, -1
- },
- /* pll setting for VESA modes */
- {
- {
- HDMIV_640x480p60hz, /* 4.028G / 16 = 251.75M */
- GROUP_END
- },
- 1, VIU_ENCP, 4028000, 4, 4, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
- },
- {
- {
- HDMIV_800x480p60hz, GROUP_END
- },
- 1, VIU_ENCP, 4761600, 4, 4, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
- },
- {
- {
- HDMIV_800x600p60hz, GROUP_END
- },
- 1, VIU_ENCP, 3200000, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
- },
- {
- {
- HDMIV_852x480p60hz, HDMIV_854x480p60hz, GROUP_END
- },
- 1, VIU_ENCP, 4838400, 4, 4, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
- },
- {
- {
- HDMIV_1024x600p60hz, GROUP_END
- },
- 1, VIU_ENCP, 4115866, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
- },
- {
- {
- HDMIV_1024x768p60hz, GROUP_END
- },
- 1, VIU_ENCP, 5200000, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
- },
- {
- {
- HDMIV_1280x768p60hz, GROUP_END
- },
- 1, VIU_ENCP, 3180000, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
- },
- {
- {
- HDMIV_1280x800p60hz,GROUP_END
- },
- 1, VIU_ENCP, 5680000, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
- },
- {
- {
- HDMIV_1152x864p75hz, HDMIV_1280x960p60hz,
- HDMIV_1280x1024p60hz, HDMIV_1600x900p60hz,
- GROUP_END
- },
- 1, VIU_ENCP, 4320000, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
- },
- {
- {
- HDMIV_1600x1200p60hz, GROUP_END
- },
- 1, VIU_ENCP, 3240000, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
- },
- {
- {
- HDMIV_1360x768p60hz, HDMIV_1366x768p60hz, GROUP_END
- },
- 1, VIU_ENCP, 3420000, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
- },
- {
- {
- HDMIV_1400x1050p60hz, GROUP_END
- },
- 1, VIU_ENCP, 4870000, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
- },
- {
- {
- HDMIV_1440x900p60hz, GROUP_END
- },
- 1, VIU_ENCP, 4260000, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
- },
- {
- {
- HDMIV_1440x2560p60hz, GROUP_END
- },
- 1, VIU_ENCP, 4897000, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
- },
- {
- {
- HDMIV_1440x2560p70hz, GROUP_END
- },
- 1, VIU_ENCP, 5600000, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
- },
- {
- {
- HDMIV_1680x1050p60hz, GROUP_END
- },
- 1, VIU_ENCP, 5850000, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
- },
- {
- {
- HDMIV_1920x1200p60hz, GROUP_END
- },
- 1, VIU_ENCP, 3865000, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
- },
- {
- {
- HDMIV_2560x1600p60hz, GROUP_END
- },
- 1, VIU_ENCP, 3485000, 1, 1, 1, CLK_UTIL_VID_PLL_DIV_5, 2, 1, 1, -1
- },
-};
-
-/* For colordepth 10bits */
-static struct hw_enc_clk_val_group setting_enc_clk_val_30[] = {
- {
- {
- HDMI_720x480i60_16x9, HDMI_720x576i50_16x9, GROUP_END
- },
- 1, VIU_ENCI, 5405400, 4, 4, 1, CLK_UTIL_VID_PLL_DIV_6p25, 1, 2, -1, 2
- },
- {
- {
- HDMI_720x576p50_16x9, HDMI_720x480p60_16x9, GROUP_END
- },
- 1, VIU_ENCP, 5405400, 4, 4, 1, CLK_UTIL_VID_PLL_DIV_6p25, 1, 2, 1, -1
- },
- {
- {
- HDMI_720x576p100_16x9, HDMI_720x480p120_16x9, GROUP_END
- },
- 1, VIU_ENCP, 5405400, 4, 2, 1, CLK_UTIL_VID_PLL_DIV_6p25, 1, 2, 1, -1
- },
- {
- {
- HDMI_1280x720p50_16x9, HDMI_1280x720p60_16x9, GROUP_END
- },
- 1, VIU_ENCP, 3712500, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_6p25, 1, 2, 1, -1
- },
- {
- {
- HDMI_1920x1080i60_16x9, HDMI_1920x1080i50_16x9, GROUP_END
- },
- 1, VIU_ENCP, 3712500, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_6p25, 1, 2, 1, -1
- },
- {
- {
- HDMI_1920x1080i120_16x9, HDMI_1920x1080i100_16x9,
- HDMI_1280x720p100_16x9, HDMI_1280x720p120_16x9, GROUP_END
- },
- 1, VIU_ENCP, 3712500, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_6p25, 1, 2, 1, -1
- },
- {
- {
- HDMI_1920x1080p60_16x9, HDMI_1920x1080p50_16x9, GROUP_END
- },
- 1, VIU_ENCP, 3712500, 1, 2, 2, CLK_UTIL_VID_PLL_DIV_6p25, 1, 1, 1, -1
- },
- {
- {
- HDMI_1920x1080p120_16x9, HDMI_1920x1080p100_16x9, GROUP_END
- },
- 1, VIU_ENCP, 3712500, 1, 1, 1, CLK_UTIL_VID_PLL_DIV_6p25, 1, 2, 2, -1
- },
- {
- {
- HDMI_1920x1080p30_16x9, HDMI_1920x1080p24_16x9,
- HDMI_1920x1080p25_16x9, GROUP_END
- },
- 1, VIU_ENCP, 3712500, 2, 2, 2, CLK_UTIL_VID_PLL_DIV_6p25, 1, 1, 1, -1
- },
- {
- {
- HDMI_4096x2160p60_256x135_Y420, HDMI_4096x2160p50_256x135_Y420,
- HDMI_3840x2160p60_16x9_Y420, HDMI_3840x2160p50_16x9_Y420, GROUP_END
- },
- 1, VIU_ENCP, 3712500, 1, 1, 1, CLK_UTIL_VID_PLL_DIV_6p25, 1, 2, 1, -1
- },
- {
- {
- HDMI_3840x2160p24_16x9, HDMI_3840x2160p25_16x9,
- HDMI_3840x2160p30_16x9, HDMI_4096x2160p24_256x135,
- HDMI_4096x2160p25_256x135, HDMI_4096x2160p30_256x135, GROUP_END
- },
- 1, VIU_ENCP, 3712500, 1, 1, 1, CLK_UTIL_VID_PLL_DIV_6p25, 1, 2, 2, -1
- },
-};
-
-/* For colordepth 12bits */
-static struct hw_enc_clk_val_group setting_enc_clk_val_36[] = {
- {
- {
- HDMI_720x480i60_16x9, HDMI_720x576i50_16x9, GROUP_END
- },
- 1, VIU_ENCI, 3243240, 2, 4, 1, CLK_UTIL_VID_PLL_DIV_7p5, 1, 2, -1, 2
- },
- {
- {
- HDMI_720x576p50_16x9, HDMI_720x480p60_16x9, GROUP_END
- },
- 1, VIU_ENCP, 3243240, 2, 4, 1, CLK_UTIL_VID_PLL_DIV_7p5, 1, 2, 1, -1
- },
- {
- {
- HDMI_720x576p100_16x9, HDMI_720x480p120_16x9, GROUP_END
- },
- 1, VIU_ENCP, 3243240, 2, 2, 1, CLK_UTIL_VID_PLL_DIV_7p5, 1, 2, 1, -1
- },
- {
- {
- HDMI_1280x720p50_16x9, HDMI_1280x720p60_16x9, GROUP_END
- },
- 1, VIU_ENCP, 4455000, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_7p5, 1, 2, 1, -1
- },
- {
- {
- HDMI_1920x1080i60_16x9, HDMI_1920x1080i50_16x9, GROUP_END
- },
- 1, VIU_ENCP, 4455000, 4, 1, 1, CLK_UTIL_VID_PLL_DIV_7p5, 1, 2, 1, -1
- },
- {
- {
- HDMI_1920x1080i120_16x9, HDMI_1920x1080i100_16x9,
- HDMI_1280x720p100_16x9, HDMI_1280x720p120_16x9, GROUP_END
- },
- 1, VIU_ENCP, 4455000, 2, 1, 1, CLK_UTIL_VID_PLL_DIV_7p5, 1, 2, 1, -1
- },
- {
- {
- HDMI_1920x1080p60_16x9, HDMI_1920x1080p50_16x9, GROUP_END
- },
- 1, VIU_ENCP, 4455000, 1, 2, 2, CLK_UTIL_VID_PLL_DIV_7p5, 1, 1, 1, -1
- },
- {
- {
- HDMI_1920x1080p120_16x9, HDMI_1920x1080p100_16x9, GROUP_END
- },
- 1, VIU_ENCP, 4455000, 1, 1, 2, CLK_UTIL_VID_PLL_DIV_3p25, 1, 2, 2, -1
- },
- {
- {
- HDMI_1920x1080p30_16x9, HDMI_1920x1080p24_16x9,
- HDMI_1920x1080p25_16x9, GROUP_END
- },
- 1, VIU_ENCP, 4455000, 2, 2, 2, CLK_UTIL_VID_PLL_DIV_7p5, 1, 1, 1, -1
- },
- {
- {
- HDMI_4096x2160p60_256x135_Y420,
- HDMI_4096x2160p50_256x135_Y420,
- HDMI_3840x2160p60_16x9_Y420,
- HDMI_3840x2160p50_16x9_Y420,
- GROUP_END
- },
- 1, VIU_ENCP, 4455000, 1, 1, 2, CLK_UTIL_VID_PLL_DIV_3p25, 1, 2, 1, -1
- },
- {
- {
- HDMI_3840x2160p24_16x9,
- HDMI_3840x2160p25_16x9,
- HDMI_3840x2160p30_16x9,
- HDMI_4096x2160p24_256x135,
- HDMI_4096x2160p25_256x135,
- HDMI_4096x2160p30_256x135,
- GROUP_END
- },
- 1, VIU_ENCP, 4455000, 1, 1, 2, CLK_UTIL_VID_PLL_DIV_3p25, 1, 2, 2, -1
- },
-};
-
-void hdmitx_set_clk_(struct hdmitx_dev *hdev)
-{
- int i = 0;
- int j = 0;
- struct hw_enc_clk_val_group *p_enc =NULL;
- enum hdmi_vic vic = hdev->vic;
- enum hdmi_color_format cs = hdev->para->cs;
- enum hdmi_color_depth cd = hdev->para->cd;
-
- /* YUV 422 always use 24B mode */
- if (cs == HDMI_COLOR_FORMAT_422)
- cd = HDMI_COLOR_DEPTH_24B;
-
- if (cd == HDMI_COLOR_DEPTH_24B) {
- p_enc = &setting_enc_clk_val_24[0];
- for (j = 0; j < sizeof(setting_enc_clk_val_24)
- / sizeof(struct hw_enc_clk_val_group); j++) {
- for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i]
- != GROUP_END)); i++) {
- if (vic == p_enc[j].group[i])
- goto next;
- }
- }
- if (j == sizeof(setting_enc_clk_val_24)
- / sizeof(struct hw_enc_clk_val_group)) {
- pr_info("Not find VIC = %d for hpll setting\n", vic);
- return;
- }
- } else if (cd == HDMI_COLOR_DEPTH_30B) {
- p_enc = &setting_enc_clk_val_30[0];
- for (j = 0; j < sizeof(setting_enc_clk_val_30)
- / sizeof(struct hw_enc_clk_val_group); j++) {
- for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i]
- != GROUP_END)); i++) {
- if (vic == p_enc[j].group[i])
- goto next;
- }
- }
- if (j == sizeof(setting_enc_clk_val_30) /
- sizeof(struct hw_enc_clk_val_group)) {
- pr_info("Not find VIC = %d for hpll setting\n", vic);
- return;
- }
- } else if (cd == HDMI_COLOR_DEPTH_36B) {
- p_enc = &setting_enc_clk_val_36[0];
- for (j = 0; j < sizeof(setting_enc_clk_val_36)
- / sizeof(struct hw_enc_clk_val_group); j++) {
- for (i = 0; ((i < GROUP_MAX) && (p_enc[j].group[i]
- != GROUP_END)); i++) {
- if (vic == p_enc[j].group[i])
- goto next;
- }
- }
- if (j == sizeof(setting_enc_clk_val_36) /
- sizeof(struct hw_enc_clk_val_group)) {
- pr_info("Not find VIC = %d for hpll setting\n", vic);
- return;
- }
- } else {
- pr_info("not support colordepth 48bits\n");
- return;
- }
-
-next:
- set_viu_path(p_enc[j].viu_path, p_enc[j].viu_type);
- set_hdmitx_sys_clk();
- set_hpll_clk_out(p_enc[j].hpll_clk_out, hdev);
- if (!env_get("sspll_dis"))
- set_hpll_sspll(hdev);
- set_hpll_od1(p_enc[j].od1);
- set_hpll_od2(p_enc[j].od2);
- set_hpll_od3(p_enc[j].od3);
- set_hpll_od3_clk_div(p_enc[j].vid_pll_div);
- printk("j = %d vid_clk_div = %d\n", j, p_enc[j].vid_clk_div);
- set_vid_clk_div(p_enc[j].vid_clk_div);
- set_hdmi_tx_pixel_div(p_enc[j].hdmi_tx_pixel_div);
- set_encp_div(p_enc[j].encp_div);
- set_enci_div(p_enc[j].enci_div);
-}
-
-static int likely_frac_rate_mode(char *m)
-{
- if (strstr(m, "24hz") || strstr(m, "30hz") || strstr(m, "60hz")
- || strstr(m, "120hz") || strstr(m, "240hz"))
- return 1;
- else
- return 0;
-}
-
-void hdmitx_set_clk(struct hdmitx_dev *hdev)
-{
- char *frac_rate_str = NULL;
-
- frac_rate_str = env_get("frac_rate_policy");
- if (frac_rate_str && (frac_rate_str[0] == '0'))
- hdev->frac_rate_policy = 0;
- else if (likely_frac_rate_mode(hdev->para->ext_name))
- hdev->frac_rate_policy = 1;
-
- hdmitx_set_clk_(hdev);
-}
-
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_edid_parsing.c b/drivers/amlogic/media/vout/hdmitx/hdmi_edid_parsing.c
deleted file mode 100644
index 22906cb..0000000
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_edid_parsing.c
+++ /dev/null
@@ -1,496 +0,0 @@
-#include <common.h>
-#include <linux/stddef.h>
-#include <amlogic/media/vout/hdmitx.h>
-
-#define CEA_DATA_BLOCK_COLLECTION_ADDR_1StP 0x04
-#define VIDEO_TAG 0x40
-#define AUDIO_TAG 0x20
-#define VENDOR_TAG 0x60
-#define SPEAKER_TAG 0x80
-
-#define HDMI_EDID_BLOCK_TYPE_RESERVED 0
-#define HDMI_EDID_BLOCK_TYPE_AUDIO 1
-#define HDMI_EDID_BLOCK_TYPE_VIDEO 2
-#define HDMI_EDID_BLOCK_TYPE_VENDER 3
-#define HDMI_EDID_BLOCK_TYPE_SPEAKER 4
-#define HDMI_EDID_BLOCK_TYPE_VESA 5
-#define HDMI_EDID_BLOCK_TYPE_RESERVED2 6
-#define HDMI_EDID_BLOCK_TYPE_EXTENDED_TAG 7
-
-#define EXTENSION_VENDOR_SPECIFIC 0x1
-#define EXTENSION_COLORMETRY_TAG 0x5
-/* DRM stands for "Dynamic Range and Mastering " */
-#define EXTENSION_DRM_TAG 0x6
-/* Video Format Preference Data block */
-#define EXTENSION_VFPDB_TAG 0xd
-#define EXTENSION_Y420_VDB_TAG 0xe
-#define EXTENSION_Y420_CMDB_TAG 0xf
-
-#define EDID_DETAILED_TIMING_DES_BLOCK0_POS 0x36
-#define EDID_DETAILED_TIMING_DES_BLOCK1_POS 0x48
-#define EDID_DETAILED_TIMING_DES_BLOCK2_POS 0x5A
-#define EDID_DETAILED_TIMING_DES_BLOCK3_POS 0x6C
-
-/* EDID Descrptor Tag */
-#define TAG_PRODUCT_SERIAL_NUMBER 0xFF
-#define TAG_ALPHA_DATA_STRING 0xFE
-#define TAG_RANGE_LIMITS 0xFD
-#define TAG_DISPLAY_PRODUCT_NAME_STRING 0xFC /* MONITOR NAME */
-#define TAG_COLOR_POINT_DATA 0xFB
-#define TAG_STANDARD_TIMINGS 0xFA
-#define TAG_DISPLAY_COLOR_MANAGEMENT 0xF9
-#define TAG_CVT_TIMING_CODES 0xF8
-#define TAG_ESTABLISHED_TIMING_III 0xF7
-#define TAG_DUMMY_DES 0x10
-
-/* retrun 1 valid edid */
-static int check_dvi_hdmi_edid_valid(unsigned char *buf)
-{
- unsigned int chksum = 0;
- unsigned int i = 0;
-
- /* check block 0 first 8 bytes */
- if ((buf[0] != 0) && (buf[7] != 0))
- return 0;
- for (i = 1; i < 7; i++) {
- if (buf[i] != 0xff)
- return 0;
- }
-
- /* check block 0 checksum */
- for (chksum = 0, i = 0; i < 0x80; i++)
- chksum += buf[i];
- if ((chksum & 0xff) != 0)
- return 0;
-
- if (buf[0x7e] == 0)/* check Extension flag at block 0 */
- return 1;
- /* check block 1 extension tag */
- else if (!((buf[0x80] == 0x2) || (buf[0x80] == 0xf0)))
- return 0;
-
- /* check block 1 checksum */
- for (chksum = 0, i = 0x80; i < 0x100; i++)
- chksum += buf[i];
- if ((chksum & 0xff) != 0)
- return 0;
-
- /* check block 2 checksum */
- if (buf[0x7e] > 1) {
- for (chksum = 0, i = 0x100; i < 0x180; i++)
- chksum += buf[i];
- if ((chksum & 0xff) != 0)
- return 0;
- }
-
- /* check block 3 checksum */
- if (buf[0x7e] > 2) {
- for (chksum = 0, i = 0x180; i < 0x200; i++)
- chksum += buf[i];
- if ((chksum & 0xff) != 0)
- return 0;
- }
-
- return 1;
-}
-
-static void dump_dtd_info(struct dtd *t)
-{
- return; /* debug only */
- printk("%s[%d]\n", __func__, __LINE__);
-#define PR(a) pr_info("%s %d\n", #a, t->a)
- PR(pixel_clock);
- PR(h_active);
- PR(h_blank);
- PR(v_active);
- PR(v_blank);
- PR(h_sync_offset);
- PR(h_sync);
- PR(v_sync_offset);
- PR(v_sync);
-}
-
-static void Edid_DTD_parsing(struct rx_cap *pRXCap, unsigned char *data)
-{
- struct hdmi_format_para *para = NULL;
- struct dtd *t = &pRXCap->dtd[pRXCap->dtd_idx];
-
- memset(t, 0, sizeof(struct dtd));
- t->pixel_clock = data[0] + (data[1] << 8);
- t->h_active = (((data[4] >> 4) & 0xf) << 8) + data[2];
- t->h_blank = ((data[4] & 0xf) << 8) + data[3];
- t->v_active = (((data[7] >> 4) & 0xf) << 8) + data[5];
- t->v_blank = ((data[7] & 0xf) << 8) + data[6];
- t->h_sync_offset = (((data[11] >> 6) & 0x3) << 8) + data[8];
- t->h_sync = (((data[11] >> 4) & 0x3) << 8) + data[9];
- t->v_sync_offset = (((data[11] >> 2) & 0x3) << 4) +
- ((data[10] >> 4) & 0xf);
- t->v_sync = (((data[11] >> 0) & 0x3) << 4) + ((data[10] >> 0) & 0xf);
-/*
- * Special handling of 1080i60hz, 1080i50hz
- */
- if ((t->pixel_clock == 7425) && (t->h_active == 1920) &&
- (t->v_active == 1080)) {
- t->v_active = t->v_active / 2;
- t->v_blank = t->v_blank / 2;
- }
-/*
- * Special handling of 480i60hz, 576i50hz
- */
- if (((((t->flags) >> 1) & 0x3) == 0) && (t->h_active == 1440)) {
- if (t->pixel_clock == 2700) /* 576i50hz */
- goto next;
- if ((t->pixel_clock - 2700) < 10) /* 480i60hz */
- t->pixel_clock = 2702;
-next:
- t->v_active = t->v_active / 2;
- t->v_blank = t->v_blank / 2;
- }
-/*
- * call hdmi_match_dtd_paras() to check t is matched with VIC
- */
- para = hdmi_match_dtd_paras(t);
- if (para) {
- t->vic = para->vic;
- pRXCap->preferred_mode = pRXCap->dtd[0].vic; /* Select dtd0 */
- if (0) /* debug only */
- pr_info("hdmitx: get dtd%d vic: %d\n",
- pRXCap->dtd_idx, para->vic);
- pRXCap->dtd_idx++;
- } else
- dump_dtd_info(t);
-}
-
-/* parse Sink 4k2k information */
-static void hdmitx_edid_4k2k_parse(struct rx_cap *pRXCap, unsigned char *dat,
- unsigned size)
-{
- if ((size > 4) || (size == 0)) {
- return;
- }
- while (size--) {
- if (*dat == 1)
- pRXCap->VIC[pRXCap->VIC_count] = HDMI_3840x2160p30_16x9;
- else if (*dat == 2)
- pRXCap->VIC[pRXCap->VIC_count] = HDMI_3840x2160p25_16x9;
- else if (*dat == 3)
- pRXCap->VIC[pRXCap->VIC_count] = HDMI_3840x2160p24_16x9;
- else if (*dat == 4)
- pRXCap->VIC[pRXCap->VIC_count] = HDMI_4096x2160p24_256x135;
- else
- ;
- dat++;
- pRXCap->VIC_count++;
- }
-}
-
-static void set_vsdb_dc_420_cap(struct rx_cap *pRXCap,
- unsigned char *edid_offset)
-{
- pRXCap->dc_30bit_420 = !!(edid_offset[6] & (1 << 0));
- pRXCap->dc_36bit_420 = !!(edid_offset[6] & (1 << 1));
- pRXCap->dc_48bit_420 = !!(edid_offset[6] & (1 << 2));
-}
-
-static int Edid_ParsingY420VDBBlock(struct rx_cap *pRXCap,
- unsigned char *buf)
-{
- unsigned char tag = 0, ext_tag = 0, data_end = 0;
- unsigned int pos = 0;
- int i = 0, found = 0;
-
- tag = (buf[pos] >> 5) & 0x7;
- data_end = (buf[pos] & 0x1f)+1;
- pos++;
- ext_tag = buf[pos];
-
- if ((tag != 0x7) || (ext_tag != 0xe))
- goto INVALID_Y420VDB;
-
- pos++;
- while (pos < data_end) {
- if (pRXCap->VIC_count < VIC_MAX_NUM) {
- for (i = 0; i < pRXCap->VIC_count; i++) {
- if (pRXCap->VIC[i] == buf[pos]) {
- pRXCap->VIC[i] =
- HDMITX_VIC420_OFFSET + buf[pos];
- found = 1;
- /* Here we do not break,because
- some EDID may have the same
- repeated VICs
- */
- }
- }
- if (0 == found) {
- pRXCap->VIC[pRXCap->VIC_count] =
- HDMITX_VIC420_OFFSET + buf[pos];
- pRXCap->VIC_count++;
- }
- }
- pos++;
- }
-
- return 0;
-
-INVALID_Y420VDB:
- pr_info("[%s] it's not a valid y420vdb!\n", __func__);
- return -1;
-}
-
-static int Edid_ParsingY420CMDBBlock(struct rx_cap *pRXCap,
- unsigned char *buf)
-{
- /* TODO */
- return 0;
-}
-
-static int Edid_Y420CMDB_PostProcess(struct rx_cap *pRXCap)
-{
- /* TODO */
- return 0;
-}
-
-static int Edid_ParsingVFPDB(struct rx_cap *pRXCap, unsigned char *buf)
-{
- unsigned int len = buf[0] & 0x1f;
- enum hdmi_vic svr = HDMI_unkown;
-
- if (buf[1] != EXTENSION_VFPDB_TAG)
- return 0;
- if (len < 2)
- return 0;
-
- svr = buf[2];
- if (((svr >= 1) && (svr <= 127)) ||
- ((svr >= 193) && (svr <= 253))) {
- pRXCap->flag_vfpdb = 1;
- pRXCap->preferred_mode = svr;
- pr_info("preferred mode 0 srv %d\n", pRXCap->preferred_mode);
- return 1;
- }
- if ((svr >= 129) && (svr <= 144)) {
- pRXCap->flag_vfpdb = 1;
- pRXCap->preferred_mode = pRXCap->dtd[svr - 129].vic;
- pr_info("preferred mode 0 dtd %d\n", pRXCap->preferred_mode);
- return 1;
- }
- return 0;
-}
-
-static int hdmitx_edid_block_parse(struct rx_cap *pRXCap,
- unsigned char *BlockBuf)
-{
- unsigned char offset, End;
- unsigned char count;
- unsigned char tag;
- int i, tmp, idx;
- unsigned char *vfpdb_offset = NULL;
-
- if (BlockBuf[0] != 0x02)
- return -1; /* not a CEA BLOCK. */
- End = BlockBuf[2]; /* CEA description. */
- pRXCap->native_Mode = BlockBuf[3];
- pRXCap->number_of_dtd += BlockBuf[3] & 0xf;
- /* bit 5 (YCBCR 4:4:4) = 1 if sink device supports YCBCR 4:4:4
- * in addition to RGB;
- * bit 4 (YCBCR 4:2:2) = 1 if sink device supports YCBCR 4:2:2
- * in addition to RGB
- */
- pRXCap->pref_colorspace = BlockBuf[3] & 0x30;
-
- pRXCap->native_VIC = 0xff;
-
- for (offset = 4 ; offset < End ; ) {
- tag = BlockBuf[offset] >> 5;
- count = BlockBuf[offset] & 0x1f;
- switch (tag) {
- case HDMI_EDID_BLOCK_TYPE_AUDIO:
- offset++;
- offset += count;
- break;
-
- case HDMI_EDID_BLOCK_TYPE_VIDEO:
- offset++;
- for (i = 0 ; i < count ; i++) {
- unsigned char VIC;
- VIC = BlockBuf[offset + i] & (~0x80);
- pRXCap->VIC[pRXCap->VIC_count] = VIC;
- if (BlockBuf[offset + i] & 0x80)
- pRXCap->native_VIC = VIC;
- pRXCap->VIC_count++;
- }
- offset += count;
- break;
-
- case HDMI_EDID_BLOCK_TYPE_VENDER:
- offset++;
- if ((BlockBuf[offset] == 0x03) &&
- (BlockBuf[offset+1] == 0x0c) &&
- (BlockBuf[offset+2] == 0x00))
- pRXCap->IEEEOUI = 0x000c03;
- else
- goto case_hf;
- pRXCap->ColorDeepSupport =
- (unsigned long)BlockBuf[offset+5];
- pRXCap->Max_TMDS_Clock1 =
- (unsigned long)BlockBuf[offset+6];
- if (count > 7) {
- tmp = BlockBuf[offset+7];
- idx = offset + 8;
- if (tmp & (1<<6))
- idx += 2;
- if (tmp & (1<<7))
- idx += 2;
- if (tmp & (1<<5)) {
- idx += 1;
- /* valid 4k */
- if (BlockBuf[idx] & 0xe0) {
- hdmitx_edid_4k2k_parse(
- pRXCap,
- &BlockBuf[idx + 1],
- BlockBuf[idx] >> 5);
- }
- }
- }
- goto case_next;
-case_hf:
- if ((BlockBuf[offset] == 0xd8) &&
- (BlockBuf[offset+1] == 0x5d) &&
- (BlockBuf[offset+2] == 0xc4))
- pRXCap->HF_IEEEOUI = 0xd85dc4;
- pRXCap->Max_TMDS_Clock2 = BlockBuf[offset+4];
- pRXCap->scdc_present =
- !!(BlockBuf[offset+5] & (1 << 7));
- pRXCap->scdc_rr_capable =
- !!(BlockBuf[offset+5] & (1 << 6));
- pRXCap->lte_340mcsc_scramble =
- !!(BlockBuf[offset+5] & (1 << 3));
- set_vsdb_dc_420_cap(pRXCap,
- &BlockBuf[offset]);
-case_next:
- offset += count; /* ignore the remaind. */
- break;
-
- case HDMI_EDID_BLOCK_TYPE_SPEAKER:
- offset++;
- offset += count;
- break;
-
- case HDMI_EDID_BLOCK_TYPE_VESA:
- offset++;
- offset += count;
- break;
-
- case HDMI_EDID_BLOCK_TYPE_EXTENDED_TAG:
- {
- unsigned char ext_tag = 0;
-
- ext_tag = BlockBuf[offset+1];
- switch (ext_tag) {
- case EXTENSION_VENDOR_SPECIFIC:
- break;
- case EXTENSION_COLORMETRY_TAG:
- pRXCap->colorimetry_data =
- BlockBuf[offset + 2];
- break;
- case EXTENSION_DRM_TAG:
- break;
- case EXTENSION_VFPDB_TAG:
-/* Just record VFPDB offset address, call Edid_ParsingVFPDB() after DTD
- * parsing, in case that
- * SVR >=129 and SVR <=144, Interpret as the Kth DTD in the EDID,
- * where K = SVR – 128 (for K=1 to 16)
- */
- vfpdb_offset = &BlockBuf[offset];
- break;
- case EXTENSION_Y420_VDB_TAG:
- Edid_ParsingY420VDBBlock(pRXCap,
- &BlockBuf[offset]);
- break;
- case EXTENSION_Y420_CMDB_TAG:
- Edid_ParsingY420CMDBBlock(pRXCap,
- &BlockBuf[offset]);
- break;
- default:
- break;
- }
- }
- offset += count+1;
- break;
-
- case HDMI_EDID_BLOCK_TYPE_RESERVED:
- offset++;
- offset += count;
- break;
-
- case HDMI_EDID_BLOCK_TYPE_RESERVED2:
- offset++;
- offset += count;
- break;
-
- default:
- break;
- }
- }
-
- Edid_Y420CMDB_PostProcess(pRXCap);
- idx = BlockBuf[3] & 0xf;
- for (i = 0; i < idx; i++)
- Edid_DTD_parsing(pRXCap, &BlockBuf[BlockBuf[2] + i * 18]);
- if (vfpdb_offset)
- Edid_ParsingVFPDB(pRXCap, vfpdb_offset);
-
- return 0;
-}
-
-/*
- * Parsing RAW EDID data from edid to pRXCap
- */
-unsigned int hdmi_edid_parsing(unsigned char *EDID_buf, struct rx_cap *pRXCap)
-{
- int i;
- int BlockCount = EDID_buf[126] + 1;
- int idx[4];
-
- /* Clear all parsing data */
- memset(pRXCap, 0, sizeof(struct rx_cap));
- pRXCap->IEEEOUI = 0x000c03; /* Default is HDMI device */
-
- /* If edid data corrupted, no parse */
- if (check_dvi_hdmi_edid_valid(EDID_buf) == 0)
- return 0;
-
- idx[0] = EDID_DETAILED_TIMING_DES_BLOCK0_POS;
- idx[1] = EDID_DETAILED_TIMING_DES_BLOCK1_POS;
- idx[2] = EDID_DETAILED_TIMING_DES_BLOCK2_POS;
- idx[3] = EDID_DETAILED_TIMING_DES_BLOCK3_POS;
- for (i = 0; i < 4; i++) {
- if ((EDID_buf[idx[i]]) && (EDID_buf[idx[i] + 1]))
- Edid_DTD_parsing(pRXCap, &EDID_buf[idx[i]]);
- }
-
- if (BlockCount == 1)
- pRXCap->IEEEOUI = 0;
-
- for (i = 1 ; i <= BlockCount ; i++) {
- if (EDID_buf[i*128+0] == 0x2)
- hdmitx_edid_block_parse(pRXCap, &(EDID_buf[i*128]));
- }
-
-/*
- * Because DTDs are not able to represent some Video Formats, which can be
- * represented as SVDs and might be preferred by Sinks, the first DTD in the
- * base EDID data structure and the first SVD in the first CEA Extension can
- * differ. When the first DTD and SVD do not match and the total number of
- * DTDs defining Native Video Formats in the whole EDID is zero, the first
- * SVD shall take precedence.
- */
- if (!pRXCap->flag_vfpdb && (pRXCap->preferred_mode != pRXCap->VIC[0]) &&
- (pRXCap->number_of_dtd == 0)) {
- pr_info("hdmitx: edid: change preferred_mode from %d to %d\n",
- pRXCap->preferred_mode, pRXCap->VIC[0]);
- pRXCap->preferred_mode = pRXCap->VIC[0];
- }
-
- return 1;
-}
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmi_parameters.c b/drivers/amlogic/media/vout/hdmitx/hdmi_parameters.c
deleted file mode 100644
index fb405f1..0000000
--- a/drivers/amlogic/media/vout/hdmitx/hdmi_parameters.c
+++ /dev/null
@@ -1,2158 +0,0 @@
-#include <common.h>
-#include <linux/stddef.h>
-#include <amlogic/media/vout/hdmitx.h>
-
-static struct hdmi_format_para fmt_para_1920x1080p60_16x9 = {
- .vic = HDMI_1920x1080p60_16x9,
- .name = "1920x1080p60hz",
- .sname = "1080p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 148500,
- .timing = {
- .pixel_freq = 148500,
- .h_freq = 67500,
- .v_freq = 60000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1920,
- .h_total = 2200,
- .h_blank = 280,
- .h_front = 88,
- .h_sync = 44,
- .h_back = 148,
- .v_active = 1080,
- .v_total = 1125,
- .v_blank = 45,
- .v_front = 4,
- .v_sync = 5,
- .v_back = 36,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_1920x1080p30_16x9 = {
- .vic = HDMI_1920x1080p30_16x9,
- .name = "1920x1080p30hz",
- .sname = "1080p30hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 74250,
- .timing = {
- .pixel_freq = 74250,
- .h_freq = 67500,
- .v_freq = 30000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1920,
- .h_total = 2200,
- .h_blank = 280,
- .h_front = 88,
- .h_sync = 44,
- .h_back = 148,
- .v_active = 1080,
- .v_total = 1125,
- .v_blank = 45,
- .v_front = 4,
- .v_sync = 5,
- .v_back = 36,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_1920x1080p50_16x9 = {
- .vic = HDMI_1920x1080p50_16x9,
- .name = "1920x1080p50hz",
- .sname = "1080p50hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 148500,
- .timing = {
- .pixel_freq = 148500,
- .h_freq = 56250,
- .v_freq = 50000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1920,
- .h_total = 2640,
- .h_blank = 720,
- .h_front = 528,
- .h_sync = 44,
- .h_back = 148,
- .v_active = 1080,
- .v_total = 1125,
- .v_blank = 45,
- .v_front = 4,
- .v_sync = 5,
- .v_back = 36,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_1920x1080p100_16x9 = {
- .vic = HDMI_1920x1080p100_16x9,
- .name = "1920x1080p100hz",
- .sname = "1080p100hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 297000,
- .timing = {
- .pixel_freq = 297000,
- .h_freq = 112500,
- .v_freq = 100000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1920,
- .h_total = 2640,
- .h_blank = 720,
- .h_front = 528,
- .h_sync = 44,
- .h_back = 148,
- .v_active = 1080,
- .v_total = 1125,
- .v_blank = 45,
- .v_front = 4,
- .v_sync = 5,
- .v_back = 36,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_1920x1080p120_16x9 = {
- .vic = HDMI_1920x1080p120_16x9,
- .name = "1920x1080p120hz",
- .sname = "1080p120hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 297000,
- .timing = {
- .pixel_freq = 297000,
- .h_freq = 135000,
- .v_freq = 120000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1920,
- .h_total = 2200,
- .h_blank = 280,
- .h_front = 88,
- .h_sync = 44,
- .h_back = 148,
- .v_active = 1080,
- .v_total = 1125,
- .v_blank = 45,
- .v_front = 4,
- .v_sync = 5,
- .v_back = 36,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_1920x1080p25_16x9 = {
- .vic = HDMI_1920x1080p25_16x9,
- .name = "1920x1080p25hz",
- .sname = "1080p25hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 148500,
- .timing = {
- .pixel_freq = 148500,
- .h_freq = 56250,
- .v_freq = 50000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1920,
- .h_total = 2640,
- .h_blank = 720,
- .h_front = 528,
- .h_sync = 44,
- .h_back = 148,
- .v_active = 1080,
- .v_total = 1125,
- .v_blank = 45,
- .v_front = 4,
- .v_sync = 5,
- .v_back = 36,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_1920x1080p24_16x9 = {
- .vic = HDMI_1920x1080p24_16x9,
- .name = "1920x1080p24hz",
- .sname = "1080p24hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 74250,
- .timing = {
- .pixel_freq = 74250,
- .h_freq = 27000,
- .v_freq = 24000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1920,
- .h_total = 2750,
- .h_blank = 830,
- .h_front = 638,
- .h_sync = 44,
- .h_back = 148,
- .v_active = 1080,
- .v_total = 1125,
- .v_blank = 45,
- .v_front = 4,
- .v_sync = 5,
- .v_back = 36,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_3840x2160p30_16x9 = {
- .vic = HDMI_3840x2160p30_16x9,
- .name = "3840x2160p30hz",
- .sname = "2160p30hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 297000,
- .timing = {
- .pixel_freq = 297000,
- .h_freq = 67500,
- .v_freq = 30000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 3840,
- .h_total = 4400,
- .h_blank = 560,
- .h_front = 176,
- .h_sync = 88,
- .h_back = 296,
- .v_active = 2160,
- .v_total = 2250,
- .v_blank = 90,
- .v_front = 8,
- .v_sync = 10,
- .v_back = 72,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_3840x2160p60_16x9 = {
- .vic = HDMI_3840x2160p60_16x9,
- .name = "3840x2160p60hz",
- .sname = "2160p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 1,
- .tmds_clk_div40 = 1,
- .tmds_clk = 594000,
- .timing = {
- .pixel_freq = 594000,
- .h_freq = 135000,
- .v_freq = 60000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 3840,
- .h_total = 4400,
- .h_blank = 560,
- .h_front = 176,
- .h_sync = 88,
- .h_back = 296,
- .v_active = 2160,
- .v_total = 2250,
- .v_blank = 90,
- .v_front = 8,
- .v_sync = 10,
- .v_back = 72,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_3840x2160p60_y420_16x9 = {
- .vic = HDMI_3840x2160p60_16x9_Y420,
- .name = "3840x2160p60hz420",
- .sname = "2160p60hz420",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 1,
- .tmds_clk_div40 = 1,
- .tmds_clk = 297000,
- .timing = {
- .pixel_freq = 594000,
- .h_freq = 135000,
- .v_freq = 60000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 3840 / 2,
- .h_total = 4400 / 2,
- .h_blank = 560 / 2,
- .h_front = 176 / 2,
- .h_sync = 88 / 2,
- .h_back = 296 / 2,
- .v_active = 2160,
- .v_total = 2250,
- .v_blank = 90,
- .v_front = 8,
- .v_sync = 10,
- .v_back = 72,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_3840x2160p50_16x9 = {
- .vic = HDMI_3840x2160p50_16x9,
- .name = "3840x2160p50hz",
- .sname = "2160p50hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 1,
- .tmds_clk_div40 = 1,
- .tmds_clk = 594000,
- .timing = {
- .pixel_freq = 594000,
- .h_freq = 112500,
- .v_freq = 50000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 3840,
- .h_total = 5280,
- .h_blank = 1440,
- .h_front = 1056,
- .h_sync = 88,
- .h_back = 296,
- .v_active = 2160,
- .v_total = 2250,
- .v_blank = 90,
- .v_front = 8,
- .v_sync = 10,
- .v_back = 72,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_3840x2160p50_y420_16x9 = {
- .vic = HDMI_3840x2160p50_16x9_Y420,
- .name = "3840x2160p50hz420",
- .sname = "2160p50hz420",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 1,
- .tmds_clk_div40 = 1,
- .tmds_clk = 297000,
- .timing = {
- .pixel_freq = 594000,
- .h_freq = 112500,
- .v_freq = 50000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 3840 / 2,
- .h_total = 5280 / 2,
- .h_blank = 1440 / 2,
- .h_front = 1056 / 2,
- .h_sync = 88 / 2,
- .h_back = 296 / 2,
- .v_active = 2160,
- .v_total = 2250,
- .v_blank = 90,
- .v_front = 8,
- .v_sync = 10,
- .v_back = 72,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_3840x2160p25_16x9 = {
- .vic = HDMI_3840x2160p25_16x9,
- .name = "3840x2160p25hz",
- .sname = "2160p25hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 297000,
- .timing = {
- .pixel_freq = 297000,
- .h_freq = 56250,
- .v_freq = 25000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 3840,
- .h_total = 5280,
- .h_blank = 1440,
- .h_front = 1056,
- .h_sync = 88,
- .h_back = 296,
- .v_active = 2160,
- .v_total = 2250,
- .v_blank = 90,
- .v_front = 8,
- .v_sync = 10,
- .v_back = 72,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_3840x2160p24_16x9 = {
- .vic = HDMI_3840x2160p24_16x9,
- .name = "3840x2160p24hz",
- .sname = "2160p24hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 297000,
- .timing = {
- .pixel_freq = 297000,
- .h_freq = 54000,
- .v_freq = 24000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 3840,
- .h_total = 5500,
- .h_blank = 1660,
- .h_front = 1276,
- .h_sync = 88,
- .h_back = 296,
- .v_active = 2160,
- .v_total = 2250,
- .v_blank = 90,
- .v_front = 8,
- .v_sync = 10,
- .v_back = 72,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_4096x2160p24_256x135 = {
- .vic = HDMI_4096x2160p24_256x135,
- .name = "4096x2160p24hz",
- .sname = "smpte24hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 297000,
- .timing = {
- .pixel_freq = 297000,
- .h_freq = 54000,
- .v_freq = 24000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 4096,
- .h_total = 5500,
- .h_blank = 1404,
- .h_front = 1020,
- .h_sync = 88,
- .h_back = 296,
- .v_active = 2160,
- .v_total = 2250,
- .v_blank = 90,
- .v_front = 8,
- .v_sync = 10,
- .v_back = 72,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_4096x2160p25_256x135 = {
- .vic = HDMI_4096x2160p25_256x135,
- .name = "4096x2160p25hz",
- .sname = "smpte25hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 297000,
- .timing = {
- .pixel_freq = 297000,
- .h_freq = 56250,
- .v_freq = 25000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 4096,
- .h_total = 5280,
- .h_blank = 1184,
- .h_front = 968,
- .h_sync = 88,
- .h_back = 128,
- .v_active = 2160,
- .v_total = 2250,
- .v_blank = 90,
- .v_front = 8,
- .v_sync = 10,
- .v_back = 72,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_4096x2160p30_256x135 = {
- .vic = HDMI_4096x2160p30_256x135,
- .name = "4096x2160p30hz",
- .sname = "smpte30hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 297000,
- .timing = {
- .pixel_freq = 297000,
- .h_freq = 67500,
- .v_freq = 30000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 4096,
- .h_total = 4400,
- .h_blank = 304,
- .h_front = 88,
- .h_sync = 88,
- .h_back = 128,
- .v_active = 2160,
- .v_total = 2250,
- .v_blank = 90,
- .v_front = 8,
- .v_sync = 10,
- .v_back = 72,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_4096x2160p50_256x135 = {
- .vic = HDMI_4096x2160p50_256x135,
- .name = "4096x2160p50hz",
- .sname = "smpte50hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 1,
- .tmds_clk_div40 = 1,
- .tmds_clk = 594000,
- .timing = {
- .pixel_freq = 594000,
- .h_freq = 112500,
- .v_freq = 50000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 4096,
- .h_total = 5280,
- .h_blank = 1184,
- .h_front = 968,
- .h_sync = 88,
- .h_back = 128,
- .v_active = 2160,
- .v_total = 2250,
- .v_blank = 90,
- .v_front = 8,
- .v_sync = 10,
- .v_back = 72,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_4096x2160p50_y420_256x135 = {
- .vic = HDMI_4096x2160p50_256x135_Y420,
- .name = "4096x2160p50hz420",
- .sname = "smpte50hz420",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 1,
- .tmds_clk_div40 = 1,
- .tmds_clk = 297000,
- .timing = {
- .pixel_freq = 594000,
- .h_freq = 112500,
- .v_freq = 50000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 4096 / 2,
- .h_total = 5280 / 2,
- .h_blank = 1184 / 2,
- .h_front = 968 / 2,
- .h_sync = 88 / 2,
- .h_back = 128 / 2,
- .v_active = 2160,
- .v_total = 2250,
- .v_blank = 90,
- .v_front = 8,
- .v_sync = 10,
- .v_back = 72,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_4096x2160p60_256x135 = {
- .vic = HDMI_4096x2160p60_256x135,
- .name = "4096x2160p60hz",
- .sname = "smpte60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 1,
- .tmds_clk_div40 = 1,
- .tmds_clk = 594000,
- .timing = {
- .pixel_freq = 594000,
- .h_freq = 135000,
- .v_freq = 60000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 4096,
- .h_total = 4400,
- .h_blank = 304,
- .h_front = 88,
- .h_sync = 88,
- .h_back = 128,
- .v_active = 2160,
- .v_total = 2250,
- .v_blank = 90,
- .v_front = 8,
- .v_sync = 10,
- .v_back = 72,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_4096x2160p60_y420_256x135 = {
- .vic = HDMI_4096x2160p60_256x135_Y420,
- .name = "4096x2160p60hz420",
- .sname = "smpte60hz420",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 1,
- .tmds_clk_div40 = 1,
- .tmds_clk = 297000,
- .timing = {
- .pixel_freq = 594000,
- .h_freq = 135000,
- .v_freq = 60000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 4096 / 2,
- .h_total = 4400 / 2,
- .h_blank = 304 / 2,
- .h_front = 88 / 2,
- .h_sync = 88 / 2,
- .h_back = 128 / 2,
- .v_active = 2160,
- .v_total = 2250,
- .v_blank = 90,
- .v_front = 8,
- .v_sync = 10,
- .v_back = 72,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_1920x1080i60_16x9 = {
- .vic = HDMI_1920x1080i60_16x9,
- .name = "1920x1080i60hz",
- .sname = "1080i60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 0,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 74250,
- .timing = {
- .pixel_freq = 74250,
- .h_freq = 33750,
- .v_freq = 60000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1920,
- .h_total = 2200,
- .h_blank = 280,
- .h_front = 88,
- .h_sync = 44,
- .h_back = 148,
- .v_active = 1080/2,
- .v_total = 1125,
- .v_blank = 45/2,
- .v_front = 2,
- .v_sync = 5,
- .v_back = 15,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_1920x1080i50_16x9 = {
- .vic = HDMI_1920x1080i50_16x9,
- .name = "1920x1080i50hz",
- .sname = "1080i50hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 0,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 74250,
- .timing = {
- .pixel_freq = 74250,
- .h_freq = 28125,
- .v_freq = 50000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1920,
- .h_total = 2640,
- .h_blank = 720,
- .h_front = 528,
- .h_sync = 44,
- .h_back = 148,
- .v_active = 1080/2,
- .v_total = 1125,
- .v_blank = 45/2,
- .v_front = 2,
- .v_sync = 5,
- .v_back = 15,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_1920x1080i100_16x9 = {
- .vic = HDMI_1920x1080i100_16x9,
- .name = "1920x1080i100hz",
- .sname = "1080i100hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 0,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 148500,
- .timing = {
- .pixel_freq = 148500,
- .h_freq = 56250,
- .v_freq = 100000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1920,
- .h_total = 2640,
- .h_blank = 720,
- .h_front = 528,
- .h_sync = 44,
- .h_back = 148,
- .v_active = 1080/2,
- .v_total = 1125,
- .v_blank = 45/2,
- .v_front = 2,
- .v_sync = 5,
- .v_back = 15,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_1920x1080i120_16x9 = {
- .vic = HDMI_1920x1080i120_16x9,
- .name = "1920x1080i120hz",
- .sname = "1080i120hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 0,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 148500,
- .timing = {
- .pixel_freq = 148500,
- .h_freq = 67500,
- .v_freq = 120000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1920,
- .h_total = 2200,
- .h_blank = 280,
- .h_front = 88,
- .h_sync = 44,
- .h_back = 148,
- .v_active = 1080/2,
- .v_total = 1125,
- .v_blank = 45/2,
- .v_front = 2,
- .v_sync = 5,
- .v_back = 15,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_1280x720p60_16x9 = {
- .vic = HDMI_1280x720p60_16x9,
- .name = "1280x720p60hz",
- .sname = "720p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 74250,
- .timing = {
- .pixel_freq = 74250,
- .h_freq = 45000,
- .v_freq = 60000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1280,
- .h_total = 1650,
- .h_blank = 370,
- .h_front = 110,
- .h_sync = 40,
- .h_back = 220,
- .v_active = 720,
- .v_total = 750,
- .v_blank = 30,
- .v_front = 5,
- .v_sync = 5,
- .v_back = 20,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_1280x720p50_16x9 = {
- .vic = HDMI_1280x720p50_16x9,
- .name = "1280x720p50hz",
- .sname = "720p50hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 74250,
- .timing = {
- .pixel_freq = 74250,
- .h_freq = 37500,
- .v_freq = 50000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1280,
- .h_total = 1980,
- .h_blank = 700,
- .h_front = 440,
- .h_sync = 40,
- .h_back = 220,
- .v_active = 720,
- .v_total = 750,
- .v_blank = 30,
- .v_front = 5,
- .v_sync = 5,
- .v_back = 20,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_1280x720p100_16x9 = {
- .vic = HDMI_1280x720p100_16x9,
- .name = "1280x720p100hz",
- .sname = "720p100hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 148500,
- .timing = {
- .pixel_freq = 148500,
- .h_freq = 75000,
- .v_freq = 100000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1280,
- .h_total = 1980,
- .h_blank = 700,
- .h_front = 440,
- .h_sync = 40,
- .h_back = 220,
- .v_active = 720,
- .v_total = 750,
- .v_blank = 30,
- .v_front = 5,
- .v_sync = 5,
- .v_back = 20,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_1280x720p120_16x9 = {
- .vic = HDMI_1280x720p120_16x9,
- .name = "1280x720p120hz",
- .sname = "720p120hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 148500,
- .timing = {
- .pixel_freq = 148500,
- .h_freq = 90000,
- .v_freq = 120000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1280,
- .h_total = 1650,
- .h_blank = 370,
- .h_front = 110,
- .h_sync = 40,
- .h_back = 220,
- .v_active = 720,
- .v_total = 750,
- .v_blank = 30,
- .v_front = 5,
- .v_sync = 5,
- .v_back = 20,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_720x480p60_16x9 = {
- .vic = HDMI_720x480p60_16x9,
- .name = "720x480p60hz",
- .sname = "480p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 27000,
- .timing = {
- .pixel_freq = 27000,
- .h_freq = 31469,
- .v_freq = 59940,
- .vsync_polarity = 0,
- .hsync_polarity = 0,
- .h_active = 720,
- .h_total = 858,
- .h_blank = 138,
- .h_front = 16,
- .h_sync = 62,
- .h_back = 60,
- .v_active = 480,
- .v_total = 525,
- .v_blank = 45,
- .v_front = 9,
- .v_sync = 6,
- .v_back = 30,
- .v_sync_ln = 7,
- },
-};
-
-static struct hdmi_format_para fmt_para_720x480p120_16x9 = {
- .vic = HDMI_720x480p120_16x9,
- .name = "720x480p120hz",
- .sname = "480p120hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 54000,
- .timing = {
- .pixel_freq = 54000,
- .h_freq = 62937,
- .v_freq = 119880,
- .vsync_polarity = 0,
- .hsync_polarity = 0,
- .h_active = 720,
- .h_total = 858,
- .h_blank = 138,
- .h_front = 16,
- .h_sync = 62,
- .h_back = 60,
- .v_active = 480,
- .v_total = 525,
- .v_blank = 45,
- .v_front = 9,
- .v_sync = 6,
- .v_back = 30,
- .v_sync_ln = 7,
- },
-};
-
-static struct hdmi_format_para fmt_para_720x480i60_16x9 = {
- .vic = HDMI_720x480i60_16x9,
- .name = "720x480i60hz",
- .sname = "480i60hz",
- .pixel_repetition_factor = 1,
- .progress_mode = 0,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 27000,
- .timing = {
- .pixel_freq = 27000,
- .h_freq = 15734,
- .v_freq = 59940,
- .vsync_polarity = 0,
- .hsync_polarity = 0,
- .h_active = 1440,
- .h_total = 1716,
- .h_blank = 276,
- .h_front = 38,
- .h_sync = 124,
- .h_back = 114,
- .v_active = 480/2,
- .v_total = 525,
- .v_blank = 45/2,
- .v_front = 4,
- .v_sync = 3,
- .v_back = 15,
- .v_sync_ln = 4,
- },
-};
-
-static struct hdmi_format_para fmt_para_720x576p50_16x9 = {
- .vic = HDMI_720x576p50_16x9,
- .name = "720x576p50hz",
- .sname = "576p50hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 27000,
- .timing = {
- .pixel_freq = 27000,
- .h_freq = 31250,
- .v_freq = 50000,
- .vsync_polarity = 0,
- .hsync_polarity = 0,
- .h_active = 720,
- .h_total = 864,
- .h_blank = 144,
- .h_front = 12,
- .h_sync = 64,
- .h_back = 68,
- .v_active = 576,
- .v_total = 625,
- .v_blank = 49,
- .v_front = 5,
- .v_sync = 5,
- .v_back = 39,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_720x576p100_16x9 = {
- .vic = HDMI_720x576p100_16x9,
- .name = "720x576p100hz",
- .sname = "576p100hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 54000,
- .timing = {
- .pixel_freq = 54000,
- .h_freq = 62500,
- .v_freq = 100000,
- .vsync_polarity = 0,
- .hsync_polarity = 0,
- .h_active = 720,
- .h_total = 864,
- .h_blank = 144,
- .h_front = 12,
- .h_sync = 64,
- .h_back = 68,
- .v_active = 576,
- .v_total = 625,
- .v_blank = 49,
- .v_front = 5,
- .v_sync = 5,
- .v_back = 39,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_720x576i50_16x9 = {
- .vic = HDMI_720x576i50_16x9,
- .name = "720x576i50hz",
- .sname = "576i50hz",
- .pixel_repetition_factor = 1,
- .progress_mode = 0,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 27000,
- .timing = {
- .pixel_freq = 27000,
- .h_freq = 15625,
- .v_freq = 50000,
- .vsync_polarity = 0,
- .hsync_polarity = 0,
- .h_active = 1440,
- .h_total = 1728,
- .h_blank = 288,
- .h_front = 24,
- .h_sync = 126,
- .h_back = 138,
- .v_active = 576/2,
- .v_total = 625,
- .v_blank = 49/2,
- .v_front = 2,
- .v_sync = 3,
- .v_back = 19,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_non_hdmi_fmt = {
- .vic = HDMI_unkown,
- .name = "invalid",
- .sname = "invalid",
-};
-
-static struct hdmi_format_para fmt_para_vesa_640x480p60_4x3 = {
- .vic = HDMIV_640x480p60hz,
- .name = "640x480p60hz",
- .sname = "640x480p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 25175,
- .timing = {
- .pixel_freq = 25175,
- .h_freq = 26218,
- .v_freq = 59940,
- .vsync_polarity = 0,
- .hsync_polarity = 0,
- .h_active = 640,
- .h_total = 800,
- .h_blank = 160,
- .h_front = 16,
- .h_sync = 96,
- .h_back = 48,
- .v_active = 480,
- .v_total = 525,
- .v_blank = 45,
- .v_front = 10,
- .v_sync = 2,
- .v_back = 33,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_800x480p60_4x3 = {
- .vic = HDMIV_800x480p60hz,
- .name = "800x480p60hz",
- .sname = "800x480p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 29760,
- .timing = {
- .pixel_freq = 29760,
- .h_freq = 30000,
- .v_freq = 60000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 800,
- .h_total = 992,
- .h_blank = 192,
- .h_front = 24,
- .h_sync = 72,
- .h_back = 96,
- .v_active = 480,
- .v_total = 500,
- .v_blank = 20,
- .v_front = 3,
- .v_sync = 7,
- .v_back = 10,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_800x600p60_4x3 = {
- .vic = HDMIV_800x600p60hz,
- .name = "800x600p60hz",
- .sname = "800x600p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 40000,
- .timing = {
- .pixel_freq = 66666,
- .h_freq = 37879,
- .v_freq = 60317,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 800,
- .h_total = 1056,
- .h_blank = 256,
- .h_front = 40,
- .h_sync = 128,
- .h_back = 88,
- .v_active = 600,
- .v_total = 628,
- .v_blank = 28,
- .v_front = 1,
- .v_sync = 4,
- .v_back = 23,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_852x480p60_213x120 = {
- .vic = HDMIV_852x480p60hz,
- .name = "852x480p60hz",
- .sname = "852x480p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 30240,
- .timing = {
- .pixel_freq = 30240,
- .h_freq = 31900,
- .v_freq = 59960,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 852,
- .h_total = 948,
- .h_blank = 96,
- .h_front = 40,
- .h_sync = 16,
- .h_back = 40,
- .v_active = 480,
- .v_total = 532,
- .v_blank = 52,
- .v_front = 10,
- .v_sync = 2,
- .v_back = 40,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_854x480p60_427x240 = {
- .vic = HDMIV_854x480p60hz,
- .name = "854x480p60hz",
- .sname = "854x480p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 30240,
- .timing = {
- .pixel_freq = 30240,
- .h_freq = 31830,
- .v_freq = 59950,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 854,
- .h_total = 950,
- .h_blank = 96,
- .h_front = 40,
- .h_sync = 16,
- .h_back = 40,
- .v_active = 480,
- .v_total = 531,
- .v_blank = 51,
- .v_front = 10,
- .v_sync = 2,
- .v_back = 39,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_1024x600p60_17x10 = {
- .vic = HDMIV_1024x600p60hz,
- .name = "1024x600p60hz",
- .sname = "1024x600p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 50400,
- .timing = {
- .pixel_freq = 50400,
- .h_freq = 38280,
- .v_freq = 60000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1024,
- .h_total = 1344,
- .h_blank = 320,
- .h_front = 24,
- .h_sync = 136,
- .h_back = 160,
- .v_active = 600,
- .v_total = 638,
- .v_blank = 38,
- .v_front = 3,
- .v_sync = 6,
- .v_back = 29,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_1024x768p60_4x3 = {
- .vic = HDMIV_1024x768p60hz,
- .name = "1024x768p60hz",
- .sname = "1024x768p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 79500,
- .timing = {
- .pixel_freq = 79500,
- .h_freq = 48360,
- .v_freq = 60004,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1024,
- .h_total = 1344,
- .h_blank = 320,
- .h_front = 24,
- .h_sync = 136,
- .h_back = 160,
- .v_active = 768,
- .v_total = 806,
- .v_blank = 38,
- .v_front = 3,
- .v_sync = 6,
- .v_back = 29,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_1152x864p75_4x3 = {
- .vic = HDMIV_1152x864p75hz,
- .name = "1152x864p75hz",
- .sname = "1152x864p75hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 108000,
- .timing = {
- .pixel_freq = 108000,
- .h_freq = 67500,
- .v_freq = 75000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1152,
- .h_total = 1600,
- .h_blank = 448,
- .h_front = 64,
- .h_sync = 128,
- .h_back = 256,
- .v_active = 864,
- .v_total = 900,
- .v_blank = 36,
- .v_front = 1,
- .v_sync = 3,
- .v_back = 32,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_1280x600p60_32x15 = {
-#if 0 /* TODO */
- .vic = HDMIV_1280x600p60hz,
- .name = "1280x600p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = ,
- .timing = {
- .pixel_freq = ,
- .h_freq = ,
- .v_freq = 60000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1280,
- .h_total = ,
- .h_blank = ,
- .h_front = ,
- .h_sync = ,
- .h_back = ,
- .v_active = 600,
- .v_total = ,
- .v_blank = ,
- .v_front = ,
- .v_sync = ,
- .v_back = ,
- .v_sync_ln = 1,
- },
-#endif
-};
-
-static struct hdmi_format_para fmt_para_vesa_1280x768p60_5x3 = {
- .vic = HDMIV_1280x768p60hz,
- .name = "1280x768p60hz",
- .sname = "1280x768p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 79500,
- .timing = {
- .pixel_freq = 79500,
- .h_freq = 47776,
- .v_freq = 59870,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1280,
- .h_total = 1664,
- .h_blank = 384,
- .h_front = 64,
- .h_sync = 128,
- .h_back = 192,
- .v_active = 768,
- .v_total = 798,
- .v_blank = 30,
- .v_front = 3,
- .v_sync = 7,
- .v_back = 20,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_1280x800p60_8x5 = {
- .vic = HDMIV_1280x800p60hz,
- .name = "1280x800p60hz",
- .sname = "1280x800p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 83500,
- .timing = {
- .pixel_freq = 83500,
- .h_freq = 49380,
- .v_freq = 59910,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1280,
- .h_total = 1440,
- .h_blank = 160,
- .h_front = 48,
- .h_sync = 32,
- .h_back = 80,
- .v_active = 800,
- .v_total = 823,
- .v_blank = 23,
- .v_front = 3,
- .v_sync = 6,
- .v_back = 14,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_1280x960p60_4x3 = {
- .vic = HDMIV_1280x960p60hz,
- .name = "1280x960p60hz",
- .sname = "1280x960p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 108000,
- .timing = {
- .pixel_freq = 108000,
- .h_freq = 60000,
- .v_freq = 60000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1280,
- .h_total = 1440,
- .h_blank = 520,
- .h_front = 96,
- .h_sync = 112,
- .h_back = 312,
- .v_active = 960,
- .v_total = 1000,
- .v_blank = 40,
- .v_front = 1,
- .v_sync = 3,
- .v_back = 36,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_1280x1024p60_5x4 = {
- .vic = HDMIV_1280x1024p60hz,
- .name = "1280x1024p60hz",
- .sname = "1280x1024p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 108000,
- .timing = {
- .pixel_freq = 108000,
- .h_freq = 64080,
- .v_freq = 60020,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1280,
- .h_total = 1688,
- .h_blank = 408,
- .h_front = 48,
- .h_sync = 112,
- .h_back = 248,
- .v_active = 1024,
- .v_total = 1066,
- .v_blank = 42,
- .v_front = 1,
- .v_sync = 3,
- .v_back = 38,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_1360x768p60_16x9 = {
- .vic = HDMIV_1360x768p60hz,
- .name = "1360x768p60hz",
- .sname = "1360x768p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 855000,
- .timing = {
- .pixel_freq = 855000,
- .h_freq = 47700,
- .v_freq = 60015,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1360,
- .h_total = 1792,
- .h_blank = 432,
- .h_front = 64,
- .h_sync = 112,
- .h_back = 256,
- .v_active = 768,
- .v_total = 795,
- .v_blank = 27,
- .v_front = 3,
- .v_sync = 6,
- .v_back = 18,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_1366x768p60_16x9 = {
- .vic = HDMIV_1366x768p60hz,
- .name = "1366x768p60hz",
- .sname = "1366x768p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 85500,
- .timing = {
- .pixel_freq = 85500,
- .h_freq = 47880,
- .v_freq = 59790,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1366,
- .h_total = 1792,
- .h_blank = 426,
- .h_front = 70,
- .h_sync = 143,
- .h_back = 213,
- .v_active = 768,
- .v_total = 798,
- .v_blank = 30,
- .v_front = 3,
- .v_sync = 3,
- .v_back = 24,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_1400x1050p60_4x3 = {
- .vic = HDMIV_1400x1050p60hz,
- .name = "1400x1050p60hz",
- .sname = "1400x1050p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 121750,
- .timing = {
- .pixel_freq = 121750,
- .h_freq = 65317,
- .v_freq = 59978,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1400,
- .h_total = 1864,
- .h_blank = 464,
- .h_front = 88,
- .h_sync = 144,
- .h_back = 232,
- .v_active = 1050,
- .v_total = 1089,
- .v_blank = 39,
- .v_front = 3,
- .v_sync = 4,
- .v_back = 32,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_1440x900p60_8x5 = {
- .vic = HDMIV_1440x900p60hz,
- .name = "1440x900p60hz",
- .sname = "1440x900p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 106500,
- .timing = {
- .pixel_freq = 106500,
- .h_freq = 56040,
- .v_freq = 59887,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1440,
- .h_total = 1904,
- .h_blank = 464,
- .h_front = 80,
- .h_sync = 152,
- .h_back = 232,
- .v_active = 900,
- .v_total = 934,
- .v_blank = 34,
- .v_front = 3,
- .v_sync = 6,
- .v_back = 25,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_1440x2560p60_9x16 = {
- .vic = HDMIV_1440x2560p60hz,
- .name = "1440x2560p60hz",
- .sname = "1440x2560p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 244850,
- .timing = {
- .pixel_freq = 244850,
- .h_freq = 155760,
- .v_freq = 59999,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1440,
- .h_total = 1572,
- .h_blank = 132,
- .h_front = 64,
- .h_sync = 4,
- .h_back = 64,
- .v_active = 2560,
- .v_total = 2596,
- .v_blank = 36,
- .v_front = 16,
- .v_sync = 4,
- .v_back = 16,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_1440x2560p70_9x16 = {
- .vic = HDMIV_1440x2560p70hz,
- .name = "1440x2560p70hz",
- .sname = "1440x2560p70hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 280000,
- .timing = {
- .pixel_freq = 280000,
- .h_freq = 180320,
- .v_freq = 70100,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1440,
- .h_total = 1550,
- .h_blank = 110,
- .h_front = 68,
- .h_sync = 16,
- .h_back = 26,
- .v_active = 2560,
- .v_total = 2576,
- .v_blank = 16,
- .v_front = 6,
- .v_sync = 6,
- .v_back = 4,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_1600x900p60_16x9 = {
- .vic = HDMIV_1600x900p60hz,
- .name = "1600x900p60hz",
- .sname = "1600x900p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 108000,
- .timing = {
- .pixel_freq = 108000,
- .h_freq = 60000,
- .v_freq = 60000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1600,
- .h_total = 1800,
- .h_blank = 200,
- .h_front = 24,
- .h_sync = 80,
- .h_back = 96,
- .v_active = 900,
- .v_total = 1000,
- .v_blank = 100,
- .v_front = 1,
- .v_sync = 3,
- .v_back = 96,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_1600x1200p60_4x3 = {
- .vic = HDMIV_1600x1200p60hz,
- .name = "1600x1200p60hz",
- .sname = "1600x1200p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 162000,
- .timing = {
- .pixel_freq = 162000,
- .h_freq = 75000,
- .v_freq = 60000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1600,
- .h_total = 2160,
- .h_blank = 560,
- .h_front = 64,
- .h_sync = 192,
- .h_back = 304,
- .v_active = 1200,
- .v_total = 1250,
- .v_blank = 50,
- .v_front = 1,
- .v_sync = 3,
- .v_back = 46,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_1680x1050p60_8x5 = {
- .vic = HDMIV_1680x1050p60hz,
- .name = "1680x1050p60hz",
- .sname = "1680x1050p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 146250,
- .timing = {
- .pixel_freq = 146250,
- .h_freq = 65340,
- .v_freq = 59954,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1680,
- .h_total = 2240,
- .h_blank = 560,
- .h_front = 104,
- .h_sync = 176,
- .h_back = 280,
- .v_active = 1050,
- .v_total = 1089,
- .v_blank = 39,
- .v_front = 3,
- .v_sync = 6,
- .v_back = 30,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_1920x1200p60_8x5 = {
- .vic = HDMIV_1920x1200p60hz,
- .name = "1920x1200p60hz",
- .sname = "1920x1200p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 193250,
- .timing = {
- .pixel_freq = 193250,
- .h_freq = 74700,
- .v_freq = 59885,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1920,
- .h_total = 2592,
- .h_blank = 672,
- .h_front = 136,
- .h_sync = 200,
- .h_back = 336,
- .v_active = 1200,
- .v_total = 1245,
- .v_blank = 45,
- .v_front = 3,
- .v_sync = 6,
- .v_back = 36,
- .v_sync_ln = 1,
- },
-};
-static struct hdmi_format_para fmt_para_vesa_2160x1200p90_9x5 = {
- .vic = HDMIV_2160x1200p90hz,
- .name = "2160x1200p90hz",
- .sname = "2160x1200p90hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 268550,
- .timing = {
- .pixel_freq = 268550,
- .h_freq = 109080,
- .v_freq = 90000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 2160,
- .h_total = 2462,
- .h_blank = 302,
- .h_front = 190,
- .h_sync = 32,
- .h_back = 80,
- .v_active = 1200,
- .v_total = 1212,
- .v_blank = 12,
- .v_front = 6,
- .v_sync = 3,
- .v_back = 3,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_2560x1080p60_64x27 = {
-#if 0 /* TODO */
- .vic = HDMIV_2560x1080p60hz,
- .name = "2560x1080p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 193250,
- .timing = {
- .pixel_freq = 193250,
- .h_freq = 74700,
- .v_freq = 60000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1920,
- .h_total = 2592,
- .h_blank = 672,
- .h_front = 136,
- .h_sync = 200,
- .h_back = 336,
- .v_active = 1200,
- .v_total = 1245,
- .v_blank = 45,
- .v_front = 3,
- .v_sync = 6,
- .v_back = 36,
- .v_sync_ln = 1,
- },
-#endif
-};
-
-static struct hdmi_format_para fmt_para_vesa_2560x1440p60_16x9 = {
-#if 0 /* TODO */
- .vic = HDMIV_2560x1440p60hz,
- .name = "2560x1440p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 193250,
- .timing = {
- .pixel_freq = 193250,
- .h_freq = 74700,
- .v_freq = 60000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1920,
- .h_total = 2592,
- .h_blank = 672,
- .h_front = 136,
- .h_sync = 200,
- .h_back = 336,
- .v_active = 1200,
- .v_total = 1245,
- .v_blank = 45,
- .v_front = 3,
- .v_sync = 6,
- .v_back = 36,
- .v_sync_ln = 1,
- },
-#endif
-};
-
-static struct hdmi_format_para fmt_para_vesa_2560x1600p60_8x5 = {
- .vic = HDMIV_2560x1600p60hz,
- .name = "2560x1600p60hz",
- .sname = "2560x1600p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 348500,
- .timing = {
- .pixel_freq = 348500,
- .h_freq = 99458,
- .v_freq = 59987,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 2560,
- .h_total = 3504,
- .h_blank = 944,
- .h_front = 192,
- .h_sync = 280,
- .h_back = 472,
- .v_active = 1600,
- .v_total = 1658,
- .v_blank = 58,
- .v_front = 3,
- .v_sync = 6,
- .v_back = 49,
- .v_sync_ln = 1,
- },
-};
-
-static struct hdmi_format_para fmt_para_vesa_3440x1440p60_43x18 = {
-#if 0 /* TODO */
- .vic = HDMIV_3440x1440p60hz,
- .name = "3440x1440p60hz",
- .pixel_repetition_factor = 0,
- .progress_mode = 1,
- .scrambler_en = 0,
- .tmds_clk_div40 = 0,
- .tmds_clk = 193250,
- .timing = {
- .pixel_freq = 193250,
- .h_freq = 74700,
- .v_freq = 60000,
- .vsync_polarity = 1,
- .hsync_polarity = 1,
- .h_active = 1920,
- .h_total = 2592,
- .h_blank = 672,
- .h_front = 136,
- .h_sync = 200,
- .h_back = 336,
- .v_active = 1200,
- .v_total = 1245,
- .v_blank = 45,
- .v_front = 3,
- .v_sync = 6,
- .v_back = 36,
- .v_sync_ln = 1,
- },
-#endif
-};
-
-static struct hdmi_format_para *all_fmt_paras[] = {
- &fmt_para_3840x2160p60_y420_16x9,
- &fmt_para_3840x2160p60_16x9,
- &fmt_para_3840x2160p50_y420_16x9,
- &fmt_para_3840x2160p50_16x9,
- &fmt_para_3840x2160p30_16x9,
- &fmt_para_3840x2160p25_16x9,
- &fmt_para_3840x2160p24_16x9,
- &fmt_para_4096x2160p24_256x135,
- &fmt_para_4096x2160p25_256x135,
- &fmt_para_4096x2160p30_256x135,
- &fmt_para_4096x2160p50_y420_256x135,
- &fmt_para_4096x2160p50_256x135,
- &fmt_para_4096x2160p60_y420_256x135,
- &fmt_para_4096x2160p60_256x135,
- &fmt_para_1920x1080p50_16x9,
- &fmt_para_1920x1080p60_16x9,
- &fmt_para_1920x1080p30_16x9,
- &fmt_para_1920x1080p25_16x9,
- &fmt_para_1920x1080p24_16x9,
- &fmt_para_1920x1080p100_16x9,
- &fmt_para_1920x1080p120_16x9,
- &fmt_para_1920x1080i60_16x9,
- &fmt_para_1920x1080i50_16x9,
- &fmt_para_1920x1080i100_16x9,
- &fmt_para_1920x1080i120_16x9,
- &fmt_para_1280x720p60_16x9,
- &fmt_para_1280x720p50_16x9,
- &fmt_para_1280x720p100_16x9,
- &fmt_para_1280x720p120_16x9,
- &fmt_para_720x480p60_16x9,
- &fmt_para_720x480p120_16x9,
- &fmt_para_720x480i60_16x9,
- &fmt_para_720x576p50_16x9,
- &fmt_para_720x576p100_16x9,
- &fmt_para_720x576i50_16x9,
- &fmt_para_vesa_640x480p60_4x3,
- &fmt_para_vesa_800x480p60_4x3,
- &fmt_para_vesa_800x600p60_4x3,
- &fmt_para_vesa_852x480p60_213x120,
- &fmt_para_vesa_854x480p60_427x240,
- &fmt_para_vesa_1024x600p60_17x10,
- &fmt_para_vesa_1024x768p60_4x3,
- &fmt_para_vesa_1152x864p75_4x3,
- &fmt_para_vesa_1280x600p60_32x15,
- &fmt_para_vesa_1280x768p60_5x3,
- &fmt_para_vesa_1280x800p60_8x5,
- &fmt_para_vesa_1280x960p60_4x3,
- &fmt_para_vesa_1280x1024p60_5x4,
- &fmt_para_vesa_1360x768p60_16x9,
- &fmt_para_vesa_1366x768p60_16x9,
- &fmt_para_vesa_1400x1050p60_4x3,
- &fmt_para_vesa_1440x900p60_8x5,
- &fmt_para_vesa_1440x2560p60_9x16,
- &fmt_para_vesa_1440x2560p70_9x16,
- &fmt_para_vesa_1600x900p60_16x9,
- &fmt_para_vesa_1600x1200p60_4x3,
- &fmt_para_vesa_1680x1050p60_8x5,
- &fmt_para_vesa_1920x1200p60_8x5,
- &fmt_para_vesa_2160x1200p90_9x5,
- &fmt_para_vesa_2560x1080p60_64x27,
- &fmt_para_vesa_2560x1440p60_16x9,
- &fmt_para_vesa_2560x1600p60_8x5,
- &fmt_para_vesa_3440x1440p60_43x18,
- &fmt_para_non_hdmi_fmt,
- NULL,
-};
-
-struct hdmi_format_para *hdmi_get_fmt_paras(enum hdmi_vic vic)
-{
- int i;
-
- for (i = 0; all_fmt_paras[i] != NULL; i++) {
- if (vic == all_fmt_paras[i]->vic)
- return all_fmt_paras[i];
- }
- return NULL;
-}
-
-static struct parse_cd parse_cd_[] = {
- {HDMI_COLOR_DEPTH_24B, "8bit",},
- {HDMI_COLOR_DEPTH_30B, "10bit"},
- {HDMI_COLOR_DEPTH_36B, "12bit"},
- {HDMI_COLOR_DEPTH_48B, "16bit"},
-};
-
-static struct parse_cs parse_cs_[] = {
- {HDMI_COLOR_FORMAT_RGB, "rgb",},
- {HDMI_COLOR_FORMAT_444, "444",},
- {HDMI_COLOR_FORMAT_422, "422",},
- {HDMI_COLOR_FORMAT_420, "420",},
-};
-
-static struct parse_cr parse_cr_[] = {
- {HDMI_COLOR_RANGE_LIM, "limit",},
- {HDMI_COLOR_RANGE_FUL, "full",},
-};
-
-/* parse the string from "hdmitx output FORMAT" */
-void hdmi_parse_attr(struct hdmi_format_para *para, char const *name)
-{
- int i;
-
- /* parse color depth */
- for (i = 0; i < sizeof(parse_cd_) / sizeof(struct parse_cd); i++) {
- if (strstr(name, parse_cd_[i].name)) {
- para->cd = parse_cd_[i].cd;
- break;
- }
- }
- /* set default value */
- if (i == sizeof(parse_cd_) / sizeof(struct parse_cd))
- para->cd = HDMI_COLOR_DEPTH_24B;
-
- /* parse color space */
- for (i = 0; i < sizeof(parse_cs_) / sizeof(struct parse_cs); i++) {
- if (strstr(name, parse_cs_[i].name)) {
- para->cs = parse_cs_[i].cs;
- break;
- }
- }
- /* set default value */
- if (i == sizeof(parse_cs_) / sizeof(struct parse_cs))
- para->cs = HDMI_COLOR_FORMAT_444;
-
- /* parse color range */
- for (i = 0; i < sizeof(parse_cr_) / sizeof(struct parse_cr); i++) {
- if (strstr(name, parse_cr_[i].name)) {
- para->cr = parse_cr_[i].cr;
- break;
- }
- }
- /* set default value */
- if (i == sizeof(parse_cr_) / sizeof(struct parse_cr))
- para->cr = HDMI_COLOR_RANGE_FUL;
-}
-
-/*
- * Paramter 'name' can be 1080p60hz, or 1920x1080p60hz
- * or 3840x2160p60hz, 2160p60hz
- * or 3840x2160p60hz420, 2160p60hz420 (Y420 mode)
- */
-enum hdmi_vic hdmi_get_fmt_vic(char const *name)
-{
- int i;
- char *lname;
- enum hdmi_vic vic = HDMI_unkown;
- struct hdmi_format_para *para = NULL;
-
- if (!name)
- return HDMI_unkown;
- for (i = 0; all_fmt_paras[i] != NULL; i++) {
- lname = all_fmt_paras[i]->name;
- if (lname && (strncmp(name, lname, strlen(lname)) == 0)) {
- vic = all_fmt_paras[i]->vic;
- break;
- }
- lname = all_fmt_paras[i]->sname;
- if (lname && (strncmp(name, lname, strlen(lname)) == 0)) {
- vic = all_fmt_paras[i]->vic;
- break;
- }
- }
- if ((vic != HDMI_unkown) && (all_fmt_paras[i] != NULL)) {
- para = all_fmt_paras[i];
- memset(¶->ext_name[0], 0, sizeof(para->ext_name));
- memcpy(¶->ext_name[0], name, strlen(name));
- hdmi_parse_attr(para, name);
- }
- return vic;
-}
-
-struct hdmi_format_para *hdmi_match_dtd_paras(struct dtd *t)
-{
- int i;
-
- if (!t)
- return NULL;
- for (i = 0; all_fmt_paras[i]; i++) {
- if ((abs(all_fmt_paras[i]->timing.pixel_freq / 10
- - t->pixel_clock) <= (t->pixel_clock + 1000) / 1000) &&
- (t->h_active == all_fmt_paras[i]->timing.h_active) &&
- (t->h_blank == all_fmt_paras[i]->timing.h_blank) &&
- (t->v_active == all_fmt_paras[i]->timing.v_active) &&
- (t->v_blank == all_fmt_paras[i]->timing.v_blank) &&
- (t->h_sync_offset == all_fmt_paras[i]->timing.h_front) &&
- (t->h_sync == all_fmt_paras[i]->timing.h_sync) &&
- (t->v_sync_offset == all_fmt_paras[i]->timing.v_front) &&
- (t->v_sync == all_fmt_paras[i]->timing.v_sync)
- )
- return all_fmt_paras[i];
- }
-
- return NULL;
-}
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx20/Kconfig b/drivers/amlogic/media/vout/hdmitx/hdmitx20/Kconfig
new file mode 100644
index 0000000..25302b3
--- /dev/null
+++ b/drivers/amlogic/media/vout/hdmitx/hdmitx20/Kconfig
@@ -0,0 +1,5 @@
+config AML_HDMITX20
+ bool "Amlogic HDMITX20 drivers Support"
+ depends on AML_HDMITX
+ help
+ HDMITX20 Output Enable
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx20/Makefile b/drivers/amlogic/media/vout/hdmitx/hdmitx20/Makefile
new file mode 100644
index 0000000..fb00f4a
--- /dev/null
+++ b/drivers/amlogic/media/vout/hdmitx/hdmitx20/Makefile
@@ -0,0 +1,9 @@
+#
+# (C) Copyright 2020
+#
+
+#EXTRA_CFLAGS = -Idrivers/video/include/
+
+obj-y += hdmitx20.o
+
+hdmitx20-y := hdmitx_drv.o hdmitx_tvenc.o hdmi_edid_parsing.o hdmi_parameters.o hdmi_tx_compliance.o hdmitx_policy.o
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmi_edid_parsing.c b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmi_edid_parsing.c
new file mode 100644
index 0000000..1e7cbbd
--- /dev/null
+++ b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmi_edid_parsing.c
@@ -0,0 +1,1494 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <linux/stddef.h>
+#include <amlogic/media/vout/hdmitx/hdmitx.h>
+
+#define CEA_DATA_BLOCK_COLLECTION_ADDR_1StP 0x04
+#define VIDEO_TAG 0x40
+#define AUDIO_TAG 0x20
+#define VENDOR_TAG 0x60
+#define SPEAKER_TAG 0x80
+
+#define HDMI_EDID_BLOCK_TYPE_RESERVED 0
+#define HDMI_EDID_BLOCK_TYPE_AUDIO 1
+#define HDMI_EDID_BLOCK_TYPE_VIDEO 2
+#define HDMI_EDID_BLOCK_TYPE_VENDER 3
+#define HDMI_EDID_BLOCK_TYPE_SPEAKER 4
+#define HDMI_EDID_BLOCK_TYPE_VESA 5
+#define HDMI_EDID_BLOCK_TYPE_RESERVED2 6
+#define HDMI_EDID_BLOCK_TYPE_EXTENDED_TAG 7
+
+#define EXTENSION_VENDOR_SPECIFIC 0x1
+#define EXTENSION_COLORMETRY_TAG 0x5
+/* DRM stands for "Dynamic Range and Mastering " */
+#define EXTENSION_DRM_STATIC_TAG 0x6
+/* Video Format Preference Data block */
+#define EXTENSION_VFPDB_TAG 0xd
+#define EXTENSION_Y420_VDB_TAG 0xe
+#define EXTENSION_Y420_CMDB_TAG 0xf
+
+#define EDID_DETAILED_TIMING_DES_BLOCK0_POS 0x36
+#define EDID_DETAILED_TIMING_DES_BLOCK1_POS 0x48
+#define EDID_DETAILED_TIMING_DES_BLOCK2_POS 0x5A
+#define EDID_DETAILED_TIMING_DES_BLOCK3_POS 0x6C
+
+/* EDID Descrptor Tag */
+#define TAG_PRODUCT_SERIAL_NUMBER 0xFF
+#define TAG_ALPHA_DATA_STRING 0xFE
+#define TAG_RANGE_LIMITS 0xFD
+#define TAG_DISPLAY_PRODUCT_NAME_STRING 0xFC /* MONITOR NAME */
+#define TAG_COLOR_POINT_DATA 0xFB
+#define TAG_STANDARD_TIMINGS 0xFA
+#define TAG_DISPLAY_COLOR_MANAGEMENT 0xF9
+#define TAG_CVT_TIMING_CODES 0xF8
+#define TAG_ESTABLISHED_TIMING_III 0xF7
+#define TAG_DUMMY_DES 0x10
+
+static struct dispmode_vic dispmode_vic_tab[] = {
+ {"480i60hz_4x3", HDMI_720x480i60_4x3},
+ {"480p60hz_4x3", HDMI_720x480p60_4x3},
+ {"576i50hz_4x3", HDMI_720x576i50_4x3},
+ {"576p50hz_4x3", HDMI_720x576p50_4x3},
+ {"480i60hz", HDMI_720x480i60_16x9},
+ {"480p60hz", HDMI_720x480p60_16x9},
+ {"576i50hz", HDMI_720x576i50_16x9},
+ {"576p50hz", HDMI_720x576p50_16x9},
+ {"720p50hz", HDMI_720p50},
+ {"720p60hz", HDMI_720p60},
+ {"1080i50hz", HDMI_1080i50},
+ {"1080i60hz", HDMI_1080i60},
+ {"1080p50hz", HDMI_1080p50},
+ {"1080p30hz", HDMI_1080p30},
+ {"1080p25hz", HDMI_1080p25},
+ {"1080p24hz", HDMI_1080p24},
+ {"1080p60hz", HDMI_1080p60},
+ {"1080p120hz", HDMI_1080p120},
+ {"2560x1080p50hz", HDMI_2560x1080p50_64x27},
+ {"2560x1080p60hz", HDMI_2560x1080p60_64x27},
+ {"2160p30hz", HDMI_4k2k_30},
+ {"2160p25hz", HDMI_4k2k_25},
+ {"2160p24hz", HDMI_4k2k_24},
+ {"smpte24hz", HDMI_4k2k_smpte_24},
+ {"smpte25hz", HDMI_4096x2160p25_256x135},
+ {"smpte30hz", HDMI_4096x2160p30_256x135},
+ {"smpte50hz420", HDMI_4096x2160p50_256x135_Y420},
+ {"smpte60hz420", HDMI_4096x2160p60_256x135_Y420},
+ {"2160p60hz420", HDMI_3840x2160p60_16x9_Y420},
+ {"2160p50hz420", HDMI_3840x2160p50_16x9_Y420},
+ {"smpte50hz", HDMI_4096x2160p50_256x135},
+ {"smpte60hz", HDMI_4096x2160p60_256x135},
+ {"2160p60hz", HDMI_4k2k_60},
+ {"2160p50hz", HDMI_4k2k_50},
+ {"640x480p60hz", HDMIV_640x480p60hz},
+ {"800x480p60hz", HDMIV_800x480p60hz},
+ {"800x600p60hz", HDMIV_800x600p60hz},
+ {"852x480p60hz", HDMIV_852x480p60hz},
+ {"854x480p60hz", HDMIV_854x480p60hz},
+ {"1024x600p60hz", HDMIV_1024x600p60hz},
+ {"1024x768p60hz", HDMIV_1024x768p60hz},
+ {"1152x864p75hz", HDMIV_1152x864p75hz},
+ {"1280x600p60hz", HDMIV_1280x600p60hz},
+ {"1280x768p60hz", HDMIV_1280x768p60hz},
+ {"1280x800p60hz", HDMIV_1280x800p60hz},
+ {"1280x960p60hz", HDMIV_1280x960p60hz},
+ {"1280x1024p60hz", HDMIV_1280x1024p60hz},
+ {"1280x1024", HDMIV_1280x1024p60hz}, /* alias of "1280x1024p60hz" */
+ {"1360x768p60hz", HDMIV_1360x768p60hz},
+ {"1366x768p60hz", HDMIV_1366x768p60hz},
+ {"1400x1050p60hz", HDMIV_1400x1050p60hz},
+ {"1440x900p60hz", HDMIV_1440x900p60hz},
+ {"1440x2560p60hz", HDMIV_1440x2560p60hz},
+ {"1600x900p60hz", HDMIV_1600x900p60hz},
+ {"1600x1200p60hz", HDMIV_1600x1200p60hz},
+ {"1680x1050p60hz", HDMIV_1680x1050p60hz},
+ {"1920x1200p60hz", HDMIV_1920x1200p60hz},
+ {"2160x1200p90hz", HDMIV_2160x1200p90hz},
+ {"2560x1440p60hz", HDMIV_2560x1440p60hz},
+ {"2560x1600p60hz", HDMIV_2560x1600p60hz},
+ {"3440x1440p60hz", HDMIV_3440x1440p60hz},
+ {"2400x1200p90hz", HDMIV_2400x1200p90hz}
+};
+
+/* check the checksum for each sub block */
+static int _check_edid_blk_chksum(unsigned char *block)
+{
+ unsigned int chksum = 0;
+ unsigned int i = 0;
+
+ for (chksum = 0, i = 0; i < 0x80; i++)
+ chksum += block[i];
+ if ((chksum & 0xff) != 0)
+ return 0;
+ else
+ return 1;
+}
+
+/* check the first edid block */
+static int _check_base_structure(unsigned char *buf)
+{
+ unsigned int i = 0;
+
+ /* check block 0 first 8 bytes */
+ if (buf[0] != 0 && buf[7] != 0)
+ return 0;
+
+ for (i = 1; i < 7; i++) {
+ if (buf[i] != 0xff)
+ return 0;
+ }
+
+ if (_check_edid_blk_chksum(buf) == 0)
+ return 0;
+
+ return 1;
+}
+
+/*
+ * check the EDID validatiy
+ * base structure: header, checksum
+ * extension: the first non-zero byte, checksum
+ */
+
+static int check_dvi_hdmi_edid_valid(unsigned char *buf)
+{
+ int i;
+ int blk_cnt = buf[0x7e] + 1;
+
+ /* limit blk_cnt to EDID_BLK_NO */
+ if (blk_cnt > EDID_BLK_NO)
+ blk_cnt = EDID_BLK_NO;
+
+ /* check block 0 */
+ if (_check_base_structure(&buf[0]) == 0)
+ return 0;
+
+ if (blk_cnt == 1)
+ return 1;
+
+ /* check extension block 1 and more */
+ for (i = 1; i < blk_cnt; i++) {
+ if (buf[i * 0x80] == 0)
+ return 0;
+ if (_check_edid_blk_chksum(&buf[i * 0x80]) == 0)
+ return 0;
+ }
+
+ return 1;
+}
+
+/*
+ * if the EDID is invalid, then set the fallback mode
+ * Resolution & RefreshRate:
+ * 1920x1080p60hz 16:9
+ * 1280x720p60hz 16:9 (default)
+ * 720x480p 16:9
+ * ColorSpace: RGB
+ * ColorDepth: 8bit
+ */
+static void edid_set_fallback_mode(struct rx_cap *prxcap)
+{
+ if (!prxcap)
+ return;
+
+ /* EDID extended blk chk error, set the 720p60, rgb,8bit */
+ prxcap->IEEEOUI = HDMI_IEEEOUI;
+ prxcap->Max_TMDS_Clock1 = 0x1e; /* 150MHZ / 5 */
+ prxcap->native_Mode = 0; /* only RGB */
+ prxcap->dc_y444 = 0; /* only 8bit */
+ prxcap->VIC_count = 0x3;
+ prxcap->VIC[0] = HDMI_1920x1080p60_16x9;
+ prxcap->VIC[1] = HDMI_1280x720p60_16x9;
+ prxcap->VIC[2] = HDMI_720x480p60_16x9;
+ prxcap->native_VIC = HDMI_1280x720p60_16x9;
+}
+
+static void dump_dtd_info(struct dtd *t)
+{
+ return; /* debug only */
+ printk("%s[%d]\n", __func__, __LINE__);
+#define PR(a) pr_info("%s %d\n", #a, t->a)
+ PR(pixel_clock);
+ PR(h_active);
+ PR(h_blank);
+ PR(v_active);
+ PR(v_blank);
+ PR(h_sync_offset);
+ PR(h_sync);
+ PR(v_sync_offset);
+ PR(v_sync);
+}
+
+static void store_cea_idx(struct rx_cap *prxcap, enum hdmi_vic vic)
+{
+ int i;
+ int already = 0;
+
+ if (!prxcap || !vic)
+ return;
+
+ for (i = 0; (i < VIC_MAX_NUM) && (i < prxcap->VIC_count); i++) {
+ if (vic == prxcap->VIC[i]) {
+ already = 1;
+ break;
+ }
+ }
+ if (!already && prxcap->VIC_count < VIC_MAX_NUM - 1) {
+ prxcap->VIC[prxcap->VIC_count] = vic;
+ prxcap->VIC_count++;
+ }
+}
+
+static int Edid_ParsingDRMStaticBlock(struct rx_cap *pRXCap,
+ unsigned char *buf)
+{
+ unsigned char tag = 0, ext_tag = 0, data_end = 0;
+ unsigned int pos = 0;
+
+ tag = (buf[pos] >> 5) & 0x7;
+ data_end = (buf[pos] & 0x1f);
+ memset(pRXCap->hdr_info.rawdata, 0, 7);
+ memcpy(pRXCap->hdr_info.rawdata, buf, data_end + 1);
+ pos++;
+ ext_tag = buf[pos];
+ if ((tag != HDMI_EDID_BLOCK_TYPE_EXTENDED_TAG)
+ || (ext_tag != EXTENSION_DRM_STATIC_TAG))
+ goto INVALID_DRM_STATIC;
+ pos++;
+ pRXCap->hdr_info.hdr_sup_eotf_sdr = !!(buf[pos] & (0x1 << 0));
+ pRXCap->hdr_info.hdr_sup_eotf_hdr = !!(buf[pos] & (0x1 << 1));
+ pRXCap->hdr_info.hdr_sup_eotf_smpte_st_2084 = !!(buf[pos] & (0x1 << 2));
+ pRXCap->hdr_info.hdr_sup_eotf_hlg = !!(buf[pos] & (0x1 << 3));
+ pos++;
+ pRXCap->hdr_info.hdr_sup_SMD_type1 = !!(buf[pos] & (0x1 << 0));
+ pos++;
+ if (data_end == 3)
+ return 0;
+ if (data_end == 4) {
+ pRXCap->hdr_info.hdr_lum_max = buf[pos];
+ return 0;
+ }
+ if (data_end == 5) {
+ pRXCap->hdr_info.hdr_lum_max = buf[pos];
+ pRXCap->hdr_info.hdr_lum_avg = buf[pos + 1];
+ return 0;
+ }
+ if (data_end == 6) {
+ pRXCap->hdr_info.hdr_lum_max = buf[pos];
+ pRXCap->hdr_info.hdr_lum_avg = buf[pos + 1];
+ pRXCap->hdr_info.hdr_lum_min = buf[pos + 2];
+ return 0;
+ }
+ return 0;
+INVALID_DRM_STATIC:
+ printf("[%s] it's not a valid DRM STATIC BLOCK\n", __func__);
+ return -1;
+}
+
+static void Edid_ParsingVendSpec(struct rx_cap *pRXCap,
+ unsigned char *buf)
+{
+ struct dv_info *dv = &pRXCap->dv_info;
+ struct hdr10_plus_info *hdr10_plus = &pRXCap->hdr10plus_info;
+ unsigned char *dat = buf;
+ unsigned char pos = 0;
+ unsigned int ieeeoui = 0;
+ u8 length = 0;
+
+ length = dat[pos] & 0x1f;
+ pos++;
+
+ if (dat[pos] != 1) {
+ printf("hdmitx: edid: parsing fail %s[%d]\n", __func__,
+ __LINE__);
+ return;
+ }
+
+ pos++;
+ ieeeoui = dat[pos++];
+ ieeeoui += dat[pos++] << 8;
+ ieeeoui += dat[pos++] << 16;
+ printf("Edid_ParsingVendSpec:ieeeoui=0x%x,len=%u\n", ieeeoui, length);
+
+ /*HDR10+ use vsvdb*/
+ if (ieeeoui == HDR10_PLUS_IEEE_OUI) {
+ memset(hdr10_plus, 0, sizeof(struct hdr10_plus_info));
+ hdr10_plus->length = length;
+ hdr10_plus->ieeeoui = ieeeoui;
+ hdr10_plus->application_version = dat[pos] & 0x3;
+ pos++;
+ return;
+ }
+
+ if (ieeeoui != DV_IEEE_OUI) {
+ dv->block_flag = ERROR_OUI;
+ return;
+ }
+ /* it is a Dovi block*/
+ memset(dv, 0, sizeof(struct dv_info));
+ dv->block_flag = CORRECT;
+ dv->length = length;
+ memcpy(dv->rawdata, dat, dv->length + 1);
+ dv->ieeeoui = ieeeoui;
+ dv->ver = (dat[pos] >> 5) & 0x7;
+ if ((dv->ver) > 2) {
+ dv->block_flag = ERROR_VER;
+ return;
+ }
+ /* Refer to DV 2.9 Page 27 */
+ if (dv->ver == 0) {
+ if (dv->length == 0x19) {
+ dv->sup_yuv422_12bit = dat[pos] & 0x1;
+ dv->sup_2160p60hz = (dat[pos] >> 1) & 0x1;
+ dv->sup_global_dimming = (dat[pos] >> 2) & 0x1;
+ pos++;
+ dv->Rx =
+ (dat[pos+1] << 4) | (dat[pos] >> 4);
+ dv->Ry =
+ (dat[pos+2] << 4) | (dat[pos] & 0xf);
+ pos += 3;
+ dv->Gx =
+ (dat[pos+1] << 4) | (dat[pos] >> 4);
+ dv->Gy =
+ (dat[pos+2] << 4) | (dat[pos] & 0xf);
+ pos += 3;
+ dv->Bx =
+ (dat[pos+1] << 4) | (dat[pos] >> 4);
+ dv->By =
+ (dat[pos+2] << 4) | (dat[pos] & 0xf);
+ pos += 3;
+ dv->Wx =
+ (dat[pos+1] << 4) | (dat[pos] >> 4);
+ dv->Wy =
+ (dat[pos+2] << 4) | (dat[pos] & 0xf);
+ pos += 3;
+ dv->tminPQ =
+ (dat[pos+1] << 4) | (dat[pos] >> 4);
+ dv->tmaxPQ =
+ (dat[pos+2] << 4) | (dat[pos] & 0xf);
+ pos += 3;
+ dv->dm_major_ver = dat[pos] >> 4;
+ dv->dm_minor_ver = dat[pos] & 0xf;
+ pos++;
+ dv->support_DV_RGB_444_8BIT = 1;
+ printf("v0 VSVDB: len=%d, sup_2160p60hz=%d\n",
+ dv->length, dv->sup_2160p60hz);
+ } else
+ dv->block_flag = ERROR_LENGTH;
+ }
+
+ if (dv->ver == 1) {
+ if (dv->length == 0x0B) {/* Refer to DV 2.9 Page 33 */
+ dv->dm_version = (dat[pos] >> 2) & 0x7;
+ dv->sup_yuv422_12bit = dat[pos] & 0x1;
+ dv->sup_2160p60hz = (dat[pos] >> 1) & 0x1;
+ pos++;
+ dv->sup_global_dimming = dat[pos] & 0x1;
+ dv->tmaxLUM = dat[pos] >> 1;
+ pos++;
+ dv->colorimetry = dat[pos] & 0x1;
+ dv->tminLUM = dat[pos] >> 1;
+ pos++;
+ dv->low_latency = dat[pos] & 0x3;
+ dv->Bx = 0x20 | ((dat[pos] >> 5) & 0x7);
+ dv->By = 0x08 | ((dat[pos] >> 2) & 0x7);
+ pos++;
+ dv->Gx = 0x00 | (dat[pos] >> 1);
+ dv->Ry = 0x40 | ((dat[pos] & 0x1) |
+ ((dat[pos + 1] & 0x1) << 1) |
+ ((dat[pos + 2] & 0x3) << 2));
+ pos++;
+ dv->Gy = 0x80 | (dat[pos] >> 1);
+ pos++;
+ dv->Rx = 0xA0 | (dat[pos] >> 3);
+ pos++;
+ dv->support_DV_RGB_444_8BIT = 1;
+ if (dv->low_latency == 0x01)
+ dv->support_LL_YCbCr_422_12BIT = 1;
+ printf("v1 VSVDB: len=%d, sup_2160p60hz=%d, low_latency=%d\n",
+ dv->length, dv->sup_2160p60hz, dv->low_latency);
+ } else if (dv->length == 0x0E) {
+ dv->dm_version = (dat[pos] >> 2) & 0x7;
+ dv->sup_yuv422_12bit = dat[pos] & 0x1;
+ dv->sup_2160p60hz = (dat[pos] >> 1) & 0x1;
+ pos++;
+ dv->sup_global_dimming = dat[pos] & 0x1;
+ dv->tmaxLUM = dat[pos] >> 1;
+ pos++;
+ dv->colorimetry = dat[pos] & 0x1;
+ dv->tminLUM = dat[pos] >> 1;
+ pos += 2; /* byte8 is reserved as 0 */
+ dv->Rx = dat[pos++];
+ dv->Ry = dat[pos++];
+ dv->Gx = dat[pos++];
+ dv->Gy = dat[pos++];
+ dv->Bx = dat[pos++];
+ dv->By = dat[pos++];
+ dv->support_DV_RGB_444_8BIT = 1;
+ printf("v1 VSVDB: len=%d, sup_2160p60hz=%d\n",
+ dv->length, dv->sup_2160p60hz);
+ } else
+ dv->block_flag = ERROR_LENGTH;
+ }
+ if (dv->ver == 2) {
+ /* v2 VSVDB length could be greater than 0xB
+ * and should not be treated as unrecognized
+ * block. Instead, we should parse it as a regular
+ * v2 VSVDB using just the remaining 11 bytes here
+ */
+ if (dv->length >= 0x0B) {
+ dv->sup_2160p60hz = 0x1;/*default*/
+ dv->dm_version = (dat[pos] >> 2) & 0x7;
+ dv->sup_yuv422_12bit = dat[pos] & 0x1;
+ dv->sup_backlight_control = (dat[pos] >> 1) & 0x1;
+ pos++;
+ dv->sup_global_dimming = (dat[pos] >> 2) & 0x1;
+ dv->backlt_min_luma = dat[pos] & 0x3;
+ dv->tminPQ = dat[pos] >> 3;
+ pos++;
+ dv->Interface = dat[pos] & 0x3;
+ dv->tmaxPQ = dat[pos] >> 3;
+ pos++;
+ dv->sup_10b_12b_444 = ((dat[pos] & 0x1) << 1) |
+ (dat[pos + 1] & 0x1);
+ dv->Gx = 0x00 | (dat[pos] >> 1);
+ pos++;
+ dv->Gy = 0x80 | (dat[pos] >> 1);
+ pos++;
+ dv->Rx = 0xA0 | (dat[pos] >> 3);
+ dv->Bx = 0x20 | (dat[pos] & 0x7);
+ pos++;
+ dv->Ry = 0x40 | (dat[pos] >> 3);
+ dv->By = 0x08 | (dat[pos] & 0x7);
+ pos++;
+ if ((dv->Interface != 0x00) &&
+ (dv->Interface != 0x01))
+ dv->support_DV_RGB_444_8BIT = 1;
+
+ dv->support_LL_YCbCr_422_12BIT = 1;
+ if ((dv->Interface == 0x01) ||
+ (dv->Interface == 0x03)) {
+ if (dv->sup_10b_12b_444 == 0x1)
+ dv->support_LL_RGB_444_10BIT = 1;
+ if (dv->sup_10b_12b_444 == 0x2)
+ dv->support_LL_RGB_444_12BIT = 1;
+ }
+ printf("v2 VSVDB: len=%d, sup_2160p60hz=%d, Interface=%d\n",
+ dv->length, dv->sup_2160p60hz, dv->Interface);
+ } else
+ dv->block_flag = ERROR_LENGTH;
+ }
+
+ if (pos > dv->length + 1)
+ printf("hdmitx: edid: maybe invalid dv%d data\n", dv->ver);
+}
+
+static void Edid_DTD_parsing(struct rx_cap *pRXCap, unsigned char *data)
+{
+ struct hdmi_format_para *para = NULL;
+ struct dtd *t = &pRXCap->dtd[pRXCap->dtd_idx];
+
+ memset(t, 0, sizeof(struct dtd));
+ t->pixel_clock = data[0] + (data[1] << 8);
+ t->h_active = (((data[4] >> 4) & 0xf) << 8) + data[2];
+ t->h_blank = ((data[4] & 0xf) << 8) + data[3];
+ t->v_active = (((data[7] >> 4) & 0xf) << 8) + data[5];
+ t->v_blank = ((data[7] & 0xf) << 8) + data[6];
+ t->h_sync_offset = (((data[11] >> 6) & 0x3) << 8) + data[8];
+ t->h_sync = (((data[11] >> 4) & 0x3) << 8) + data[9];
+ t->v_sync_offset = (((data[11] >> 2) & 0x3) << 4) +
+ ((data[10] >> 4) & 0xf);
+ t->v_sync = (((data[11] >> 0) & 0x3) << 4) + ((data[10] >> 0) & 0xf);
+/*
+ * Special handling of 1080i60hz, 1080i50hz
+ */
+ if ((t->pixel_clock == 7425) && (t->h_active == 1920) &&
+ (t->v_active == 1080)) {
+ t->v_active = t->v_active / 2;
+ t->v_blank = t->v_blank / 2;
+ }
+/*
+ * Special handling of 480i60hz, 576i50hz
+ */
+ if (((((t->flags) >> 1) & 0x3) == 0) && (t->h_active == 1440)) {
+ if (t->pixel_clock == 2700) /* 576i50hz */
+ goto next;
+ if ((t->pixel_clock - 2700) < 10) /* 480i60hz */
+ t->pixel_clock = 2702;
+next:
+ t->v_active = t->v_active / 2;
+ t->v_blank = t->v_blank / 2;
+ }
+/*
+ * call hdmi_match_dtd_paras() to check t is matched with VIC
+ */
+ para = hdmi_match_dtd_paras(t);
+ if (para) {
+ t->vic = para->vic;
+ pRXCap->preferred_mode = pRXCap->dtd[0].vic; /* Select dtd0 */
+ if (0) /* debug only */
+ pr_info("hdmitx: get dtd%d vic: %d\n",
+ pRXCap->dtd_idx, para->vic);
+ pRXCap->dtd_idx++;
+ if (para->vic < HDMITX_VESA_OFFSET)
+ store_cea_idx(pRXCap, para->vic);
+ } else
+ dump_dtd_info(t);
+}
+
+/* parse Sink 4k2k information */
+static void hdmitx_edid_4k2k_parse(struct rx_cap *pRXCap, unsigned char *dat,
+ unsigned size)
+{
+ if ((size > 4) || (size == 0)) {
+ return;
+ }
+ while (size--) {
+ if (*dat == 1)
+ pRXCap->VIC[pRXCap->VIC_count] = HDMI_3840x2160p30_16x9;
+ else if (*dat == 2)
+ pRXCap->VIC[pRXCap->VIC_count] = HDMI_3840x2160p25_16x9;
+ else if (*dat == 3)
+ pRXCap->VIC[pRXCap->VIC_count] = HDMI_3840x2160p24_16x9;
+ else if (*dat == 4)
+ pRXCap->VIC[pRXCap->VIC_count] = HDMI_4096x2160p24_256x135;
+ else
+ ;
+ dat++;
+ pRXCap->VIC_count++;
+ }
+}
+
+static void set_vsdb_dc_cap(struct rx_cap *pRXCap)
+{
+ pRXCap->dc_y444 = !!(pRXCap->ColorDeepSupport & (1 << 3));
+ pRXCap->dc_30bit = !!(pRXCap->ColorDeepSupport & (1 << 4));
+ pRXCap->dc_36bit = !!(pRXCap->ColorDeepSupport & (1 << 5));
+ pRXCap->dc_48bit = !!(pRXCap->ColorDeepSupport & (1 << 6));
+}
+
+static void set_vsdb_dc_420_cap(struct rx_cap *pRXCap,
+ unsigned char *edid_offset)
+{
+ pRXCap->dc_30bit_420 = !!(edid_offset[6] & (1 << 0));
+ pRXCap->dc_36bit_420 = !!(edid_offset[6] & (1 << 1));
+ pRXCap->dc_48bit_420 = !!(edid_offset[6] & (1 << 2));
+}
+
+static bool Y420VicRight(unsigned int vic)
+{
+ bool rtn_val;
+
+ rtn_val = false;
+ if (vic == HDMI_3840x2160p60_64x27 ||
+ vic == HDMI_3840x2160p50_64x27 ||
+ vic == HDMI_4096x2160p60_256x135 ||
+ vic == HDMI_4096x2160p50_256x135 ||
+ vic == HDMI_3840x2160p60_16x9 ||
+ vic == HDMI_3840x2160p50_16x9)
+ rtn_val = true;
+ return rtn_val;
+}
+
+static int Edid_ParsingY420VDBBlock(struct rx_cap *pRXCap,
+ unsigned char *buf)
+{
+ unsigned char tag = 0, ext_tag = 0, data_end = 0;
+ unsigned int pos = 0;
+ int i = 0, found = 0;
+
+ tag = (buf[pos] >> 5) & 0x7;
+ data_end = (buf[pos] & 0x1f)+1;
+ pos++;
+ ext_tag = buf[pos];
+
+ if ((tag != 0x7) || (ext_tag != 0xe))
+ goto INVALID_Y420VDB;
+
+ pRXCap->dc_y420 = 1;
+ pos++;
+ while (pos < data_end) {
+ if (pRXCap->VIC_count < VIC_MAX_NUM) {
+ for (i = 0; i < pRXCap->VIC_count; i++) {
+ if (pRXCap->VIC[i] == buf[pos] &&
+ Y420VicRight(buf[pos])) {
+ pRXCap->VIC[i] =
+ HDMITX_VIC420_OFFSET + buf[pos];
+ found = 1;
+ /* Here we do not break,because
+ some EDID may have the same
+ repeated VICs
+ */
+ }
+ }
+ if (0 == found) {
+ pRXCap->VIC[pRXCap->VIC_count] =
+ HDMITX_VIC420_OFFSET + buf[pos];
+ pRXCap->VIC_count++;
+ }
+ }
+ pos++;
+ }
+
+ return 0;
+
+INVALID_Y420VDB:
+ printf("[%s] it's not a valid y420vdb!\n", __func__);
+ return -1;
+}
+
+static int Edid_ParsingY420CMDBBlock(struct rx_cap *pRXCap,
+ unsigned char *buf)
+{
+ unsigned char tag = 0, ext_tag = 0, length = 0, data_end = 0;
+ unsigned int pos = 0, i = 0;
+
+ tag = (buf[pos] >> 5) & 0x7;
+ length = buf[pos] & 0x1f;
+ data_end = length + 1;
+ pos++;
+ ext_tag = buf[pos];
+
+ if ((tag != 0x7) || (ext_tag != 0xf))
+ goto INVALID_Y420CMDB;
+
+ if (length == 1) {
+ pRXCap->y420_all_vic = 1;
+ return 0;
+ }
+
+ pRXCap->bitmap_length = 0;
+ pRXCap->bitmap_valid = 0;
+ memset(pRXCap->y420cmdb_bitmap, 0x00, Y420CMDB_MAX);
+
+ pos++;
+ if (pos < data_end) {
+ pRXCap->bitmap_length = data_end - pos;
+ pRXCap->bitmap_valid = 1;
+ }
+ while (pos < data_end) {
+ if (i < Y420CMDB_MAX)
+ pRXCap->y420cmdb_bitmap[i] = buf[pos];
+ pos++;
+ i++;
+ }
+
+ return 0;
+
+INVALID_Y420CMDB:
+ printf("[%s] it's not a valid y420cmdb!\n", __func__);
+ return -1;
+}
+
+static int Edid_Y420CMDB_fill_all_vic(struct rx_cap *pRXCap)
+{
+ unsigned int count = pRXCap->VIC_count;
+ unsigned int a, b;
+
+ if (pRXCap->y420_all_vic != 1)
+ return 1;
+
+ a = count/8;
+ a = (a >= Y420CMDB_MAX)?Y420CMDB_MAX:a;
+ b = count%8;
+
+ if (a > 0)
+ memset(&(pRXCap->y420cmdb_bitmap[0]), 0xff, a);
+
+ if ((b != 0) && (a < Y420CMDB_MAX))
+ pRXCap->y420cmdb_bitmap[a] = (1 << b) - 1;
+
+ pRXCap->bitmap_length = (b == 0) ? a : (a + 1);
+ pRXCap->bitmap_valid = (pRXCap->bitmap_length != 0)?1:0;
+
+ return 0;
+}
+
+static int Edid_Y420CMDB_PostProcess(struct rx_cap *pRXCap)
+{
+ unsigned int i = 0, j = 0, valid = 0;
+ unsigned char *p = NULL;
+
+ if (pRXCap->y420_all_vic == 1)
+ Edid_Y420CMDB_fill_all_vic(pRXCap);
+
+ if (pRXCap->bitmap_valid == 0)
+ goto PROCESS_END;
+
+ pRXCap->dc_y420 = 1;
+ for (i = 0; i < pRXCap->bitmap_length; i++) {
+ p = &(pRXCap->y420cmdb_bitmap[i]);
+ for (j = 0; j < 8; j++) {
+ valid = ((*p >> j) & 0x1);
+ if (valid != 0 &&
+ Y420VicRight(pRXCap->VIC[i * 8 + j])) {
+ pRXCap->VIC[pRXCap->VIC_count] =
+ HDMITX_VIC420_OFFSET + pRXCap->VIC[i*8+j];
+ pRXCap->VIC_count++;
+ }
+ }
+ }
+
+PROCESS_END:
+ return 0;
+}
+
+static int Edid_ParsingVFPDB(struct rx_cap *pRXCap, unsigned char *buf)
+{
+ unsigned int len = buf[0] & 0x1f;
+ enum hdmi_vic svr = HDMI_unkown;
+
+ if (buf[1] != EXTENSION_VFPDB_TAG)
+ return 0;
+ if (len < 2)
+ return 0;
+
+ svr = buf[2];
+ if (((svr >= 1) && (svr <= 127)) ||
+ ((svr >= 193) && (svr <= 253))) {
+ pRXCap->flag_vfpdb = 1;
+ pRXCap->preferred_mode = svr;
+ pr_info("preferred mode 0 srv %d\n", pRXCap->preferred_mode);
+ return 1;
+ }
+ if ((svr >= 129) && (svr <= 144)) {
+ pRXCap->flag_vfpdb = 1;
+ pRXCap->preferred_mode = pRXCap->dtd[svr - 129].vic;
+ pr_info("preferred mode 0 dtd %d\n", pRXCap->preferred_mode);
+ return 1;
+ }
+ return 0;
+}
+
+static void hdmitx_edid_parse_hdmi14(struct rx_cap *pRXCap,
+ unsigned char offset,
+ unsigned char *BlockBuf,
+ unsigned char count)
+{
+ int idx = 0, tmp = 0;
+
+ pRXCap->IEEEOUI = HDMI_IEEEOUI;
+ pRXCap->ColorDeepSupport = (count > 5) ? (unsigned long)BlockBuf[offset+5] : 0;
+ printf("HDMI_EDID_BLOCK_TYPE_VENDER: pRXCap->ColorDeepSupport=0x%x\n", pRXCap->ColorDeepSupport);
+ if (count > 5)
+ set_vsdb_dc_cap(pRXCap);
+ pRXCap->Max_TMDS_Clock1 = (count > 6) ? (unsigned long)BlockBuf[offset+6] : 0;
+ if (count > 7) {
+ tmp = BlockBuf[offset+7];
+ idx = offset + 8;
+ if (tmp & (1<<6))
+ idx += 2;
+ if (tmp & (1<<7))
+ idx += 2;
+ if (tmp & (1<<5)) {
+ idx += 1;
+ /* valid 4k */
+ if (BlockBuf[idx] & 0xe0) {
+ hdmitx_edid_4k2k_parse(pRXCap,
+ &BlockBuf[idx + 1], BlockBuf[idx] >> 5);
+ }
+ }
+ }
+}
+
+static void hdmitx_parse_sink_capability(struct rx_cap *pRXCap,
+ unsigned char offset, unsigned char *BlockBuf,
+ unsigned char count)
+{
+ pRXCap->HF_IEEEOUI = 0xd85dc4;
+ pRXCap->Max_TMDS_Clock2 = BlockBuf[offset+4];
+ pRXCap->scdc_present = !!(BlockBuf[offset+5] & (1 << 7));
+ pRXCap->scdc_rr_capable = !!(BlockBuf[offset+5] & (1 << 6));
+ pRXCap->lte_340mcsc_scramble = !!(BlockBuf[offset+5] & (1 << 3));
+ set_vsdb_dc_420_cap(pRXCap, &BlockBuf[offset]);
+}
+
+static int hdmitx_edid_block_parse(struct rx_cap *pRXCap,
+ unsigned char *BlockBuf)
+{
+ unsigned char offset, End;
+ unsigned char count;
+ unsigned char tag;
+ int i, idx;
+ unsigned char *vfpdb_offset = NULL;
+
+ /* CEA-861 implementations are required to use Tag = 0x02
+ * for the CEA Extension Tag and Sources should ignore
+ * Tags that are not understood. but for Samsung LA32D400E1
+ * its extension tag is 0x0 while other bytes normal,
+ * so continue parse as other sources do
+ */
+ if (BlockBuf[0] == 0x0)
+ printf("unkonw Extension Tag detected, continue\n");
+ else if ((BlockBuf[0] != 0x02))
+ return -1; /* not a CEA BLOCK. */
+ End = BlockBuf[2]; /* CEA description. */
+ pRXCap->native_Mode = BlockBuf[1] >= 2 ? BlockBuf[3] : 0;
+ pRXCap->number_of_dtd += BlockBuf[1] >= 2 ? (BlockBuf[3] & 0xf) : 0;
+ /* bit 5 (YCBCR 4:4:4) = 1 if sink device supports YCBCR 4:4:4
+ * in addition to RGB;
+ * bit 4 (YCBCR 4:2:2) = 1 if sink device supports YCBCR 4:2:2
+ * in addition to RGB
+ */
+ pRXCap->pref_colorspace = BlockBuf[3] & 0x30;
+
+ pRXCap->native_VIC = 0xff;
+
+ for (offset = 4 ; offset < End ; ) {
+ tag = BlockBuf[offset] >> 5;
+ count = BlockBuf[offset] & 0x1f;
+ switch (tag) {
+ case HDMI_EDID_BLOCK_TYPE_AUDIO:
+ offset++;
+ offset += count;
+ break;
+
+ case HDMI_EDID_BLOCK_TYPE_VIDEO:
+ offset++;
+ for (i = 0 ; i < count ; i++) {
+ unsigned char VIC;
+ /* 7.5.1 Video Data Block Table 58
+ * and CTA-861-G page101: only 1~64
+ * maybe Native Video Format. and
+ * need to take care hdmi2.1 VIC:
+ * 193~253
+ */
+ VIC = BlockBuf[offset + i];
+ if (VIC >= 129 && VIC <= 192) {
+ VIC &= (~0x80);
+ pRXCap->native_VIC = VIC;
+ }
+ pRXCap->VIC[pRXCap->VIC_count] = VIC;
+ pRXCap->VIC_count++;
+ }
+ offset += count;
+ break;
+
+ case HDMI_EDID_BLOCK_TYPE_VENDER:
+ offset++;
+ if ((BlockBuf[offset] == 0x03) &&
+ (BlockBuf[offset+1] == 0x0c) &&
+ (BlockBuf[offset+2] == 0x00))
+ hdmitx_edid_parse_hdmi14(pRXCap, offset, BlockBuf, count);
+ else if ((BlockBuf[offset] == 0xd8) &&
+ (BlockBuf[offset + 1] == 0x5d) &&
+ (BlockBuf[offset + 2] == 0xc4))
+ hdmitx_parse_sink_capability(pRXCap, offset, BlockBuf, count);
+ offset += count; /* ignore the remaind. */
+ break;
+
+ case HDMI_EDID_BLOCK_TYPE_SPEAKER:
+ offset++;
+ offset += count;
+ break;
+
+ case HDMI_EDID_BLOCK_TYPE_VESA:
+ offset++;
+ offset += count;
+ break;
+
+ case HDMI_EDID_BLOCK_TYPE_EXTENDED_TAG:
+ {
+ unsigned char ext_tag = 0;
+
+ ext_tag = BlockBuf[offset+1];
+ switch (ext_tag) {
+ case EXTENSION_VENDOR_SPECIFIC:
+ Edid_ParsingVendSpec(pRXCap,
+ &BlockBuf[offset]);
+ break;
+ case EXTENSION_COLORMETRY_TAG:
+ pRXCap->colorimetry_data =
+ BlockBuf[offset + 2];
+ break;
+ case EXTENSION_DRM_STATIC_TAG:
+ Edid_ParsingDRMStaticBlock(pRXCap,
+ &BlockBuf[offset]);
+ break;
+ case EXTENSION_VFPDB_TAG:
+/* Just record VFPDB offset address, call Edid_ParsingVFPDB() after DTD
+ * parsing, in case that
+ * SVR >=129 and SVR <=144, Interpret as the Kth DTD in the EDID,
+ * where K = SVR – 128 (for K=1 to 16)
+ */
+ vfpdb_offset = &BlockBuf[offset];
+ break;
+ case EXTENSION_Y420_VDB_TAG:
+ Edid_ParsingY420VDBBlock(pRXCap,
+ &BlockBuf[offset]);
+ break;
+ case EXTENSION_Y420_CMDB_TAG:
+ Edid_ParsingY420CMDBBlock(pRXCap,
+ &BlockBuf[offset]);
+ break;
+ default:
+ break;
+ }
+ }
+ offset += count+1;
+ break;
+
+ case HDMI_EDID_BLOCK_TYPE_RESERVED:
+ offset++;
+ offset += count;
+ break;
+
+ case HDMI_EDID_BLOCK_TYPE_RESERVED2:
+ offset++;
+ offset += count;
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ Edid_Y420CMDB_PostProcess(pRXCap);
+ idx = BlockBuf[3] & 0xf;
+ for (i = 0; i < idx; i++)
+ Edid_DTD_parsing(pRXCap, &BlockBuf[BlockBuf[2] + i * 18]);
+ if (vfpdb_offset)
+ Edid_ParsingVFPDB(pRXCap, vfpdb_offset);
+
+ return 0;
+}
+
+void Edid_MonitorCapable861(struct rx_cap *pRXCap,
+ unsigned char edid_flag)
+{
+ if (edid_flag & 0x20)
+ pRXCap->support_ycbcr444_flag = 1;
+ if (edid_flag & 0x10)
+ pRXCap->support_ycbcr422_flag = 1;
+ printf("Edid_MonitorCapable861: ycbcr444=%d, ycbcr422=%d\n",
+ pRXCap->support_ycbcr444_flag, pRXCap->support_ycbcr422_flag);
+}
+
+static bool is_4k60_supported(struct rx_cap *prxcap)
+{
+ int i = 0;
+
+ if (!prxcap)
+ return false;
+
+ for (i = 0; (i < prxcap->VIC_count) && (i < VIC_MAX_NUM); i++) {
+ if (((prxcap->VIC[i] & 0xff) == HDMI_3840x2160p50_16x9) ||
+ ((prxcap->VIC[i] & 0xff) == HDMI_3840x2160p60_16x9)) {
+ return true;
+ }
+ }
+ return false;
+}
+
+static void check_dv_truly_support(struct rx_cap *prxcap, struct dv_info *dv)
+{
+ unsigned int max_tmds_clk = 0;
+
+ if (!prxcap || !dv)
+ return;
+ if ((dv->ieeeoui == DV_IEEE_OUI) && (dv->ver <= 2)) {
+ /* check max tmds rate to determine if 4k60 DV can truly be
+ * supported.
+ */
+ if (prxcap->Max_TMDS_Clock2) {
+ max_tmds_clk = prxcap->Max_TMDS_Clock2 * 5;
+ } else {
+ /* Default min is 74.25 / 5 */
+ if (prxcap->Max_TMDS_Clock1 < 0xf)
+ prxcap->Max_TMDS_Clock1 = 0x1e;
+ max_tmds_clk = prxcap->Max_TMDS_Clock1 * 5;
+ }
+ if (dv->ver == 0)
+ dv->sup_2160p60hz = dv->sup_2160p60hz &&
+ (max_tmds_clk >= 594);
+
+ if ((dv->ver == 1) && (dv->length == 0xB)) {
+ if (dv->low_latency == 0x00) {
+ /*standard mode */
+ dv->sup_2160p60hz = dv->sup_2160p60hz &&
+ (max_tmds_clk >= 594);
+ } else if (dv->low_latency == 0x01) {
+ /* both standard and LL are supported. 4k60 LL
+ * DV support should/can be determined using
+ * video formats supported inthe E-EDID as flag
+ * sup_2160p60hz might not be set.
+ */
+ if ((dv->sup_2160p60hz ||
+ is_4k60_supported(prxcap)) &&
+ (max_tmds_clk >= 594))
+ dv->sup_2160p60hz = 1;
+ else
+ dv->sup_2160p60hz = 0;
+ }
+ }
+
+ if ((dv->ver == 1) && (dv->length == 0xE))
+ dv->sup_2160p60hz = dv->sup_2160p60hz &&
+ (max_tmds_clk >= 594);
+
+ if (dv->ver == 2) {
+ /* 4k60 DV support should be determined using video
+ * formats supported in the EEDID as flag sup_2160p60hz
+ * is not applicable for VSVDB V2.
+ */
+ if (is_4k60_supported(prxcap) && (max_tmds_clk >= 594))
+ dv->sup_2160p60hz = 1;
+ else
+ dv->sup_2160p60hz = 0;
+ }
+ }
+}
+
+/*
+ * Parsing RAW EDID data from edid to pRXCap
+ */
+unsigned int hdmi_edid_parsing(unsigned char *EDID_buf, struct rx_cap *pRXCap)
+{
+ int i, j;
+ int BlockCount = EDID_buf[126];
+ int idx[4];
+ unsigned char CheckSum;
+ struct dv_info *dv = &pRXCap->dv_info;
+
+ /* Clear all parsing data */
+ memset(pRXCap, 0, sizeof(struct rx_cap));
+ pRXCap->IEEEOUI = 0x00; /* Default is DVI device */
+
+ if (check_dvi_hdmi_edid_valid(EDID_buf) == 0) {
+ edid_set_fallback_mode(pRXCap);
+ printf("set fallback mode\n");
+ return 0;
+ }
+
+ idx[0] = EDID_DETAILED_TIMING_DES_BLOCK0_POS;
+ idx[1] = EDID_DETAILED_TIMING_DES_BLOCK1_POS;
+ idx[2] = EDID_DETAILED_TIMING_DES_BLOCK2_POS;
+ idx[3] = EDID_DETAILED_TIMING_DES_BLOCK3_POS;
+ for (i = 0; i < 4; i++) {
+ if ((EDID_buf[idx[i]]) && (EDID_buf[idx[i] + 1]))
+ Edid_DTD_parsing(pRXCap, &EDID_buf[idx[i]]);
+ }
+
+ if (BlockCount == 0)
+ pRXCap->IEEEOUI = 0;
+
+ for (i = 1; i <= BlockCount; i++) {
+ /* block map block */
+ if (EDID_buf[0x80] == 0xf0)
+ continue;
+ if ((BlockCount > 1) && (i == 1))
+ CheckSum = 0; /* ignore the block1 data */
+ else {
+ for (j = 0, CheckSum = 0 ; j < 128 ; j++) {
+ CheckSum += EDID_buf[i*128 + j];
+ CheckSum &= 0xFF;
+ }
+ if (CheckSum == 0) {
+ Edid_MonitorCapable861(
+ pRXCap,
+ EDID_buf[i * 128 + 3]);
+ }
+ }
+ hdmitx_edid_block_parse(pRXCap, &(EDID_buf[i*128]));
+ }
+ check_dv_truly_support(pRXCap, dv);
+/*
+ * Because DTDs are not able to represent some Video Formats, which can be
+ * represented as SVDs and might be preferred by Sinks, the first DTD in the
+ * base EDID data structure and the first SVD in the first CEA Extension can
+ * differ. When the first DTD and SVD do not match and the total number of
+ * DTDs defining Native Video Formats in the whole EDID is zero, the first
+ * SVD shall take precedence.
+ */
+ if (!pRXCap->flag_vfpdb && (pRXCap->preferred_mode != pRXCap->VIC[0]) &&
+ (pRXCap->number_of_dtd == 0)) {
+ pr_info("hdmitx: edid: change preferred_mode from %d to %d\n",
+ pRXCap->preferred_mode, pRXCap->VIC[0]);
+ pRXCap->preferred_mode = pRXCap->VIC[0];
+ }
+
+ return 1;
+}
+
+int hdmitx_edid_VIC_support(enum hdmi_vic vic)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(dispmode_vic_tab); i++) {
+ if (vic == dispmode_vic_tab[i].VIC)
+ return 1;
+ }
+
+ return 0;
+}
+
+enum hdmi_vic hdmitx_edid_vic_tab_map_vic(const char *disp_mode)
+{
+ enum hdmi_vic vic = HDMI_unkown;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(dispmode_vic_tab); i++) {
+ if (strncmp(disp_mode, dispmode_vic_tab[i].disp_mode,
+ strlen(dispmode_vic_tab[i].disp_mode)) == 0) {
+ vic = dispmode_vic_tab[i].VIC;
+ break;
+ }
+ }
+
+ if (vic == HDMI_unkown)
+ printf("not find mapped vic\n");
+
+ return vic;
+}
+
+const char *hdmitx_edid_vic_tab_map_string(enum hdmi_vic vic)
+{
+ int i;
+ const char *disp_str = NULL;
+
+ for (i = 0; i < ARRAY_SIZE(dispmode_vic_tab); i++) {
+ if (vic == dispmode_vic_tab[i].VIC) {
+ disp_str = dispmode_vic_tab[i].disp_mode;
+ break;
+ }
+ }
+
+ return disp_str;
+}
+
+const char *hdmitx_edid_vic_to_string(enum hdmi_vic vic)
+{
+ int i;
+ const char *disp_str = NULL;
+
+ for (i = 0; i < ARRAY_SIZE(dispmode_vic_tab); i++) {
+ if (vic == dispmode_vic_tab[i].VIC) {
+ disp_str = dispmode_vic_tab[i].disp_mode;
+ break;
+ }
+ }
+
+ return disp_str;
+}
+
+static bool is_rx_support_y420(struct hdmitx_dev *hdev)
+{
+ enum hdmi_vic vic = HDMI_unkown;
+
+ vic = hdmitx_edid_get_VIC(hdev, "2160p60hz420", 0);
+ if (vic != HDMI_unkown)
+ return 1;
+
+ vic = hdmitx_edid_get_VIC(hdev, "2160p50hz420", 0);
+ if (vic != HDMI_unkown)
+ return 1;
+
+ vic = hdmitx_edid_get_VIC(hdev, "smpte60hz420", 0);
+ if (vic != HDMI_unkown)
+ return 1;
+
+ vic = hdmitx_edid_get_VIC(hdev, "smpte50hz420", 0);
+ if (vic != HDMI_unkown)
+ return 1;
+
+ return 0;
+}
+
+static int is_4k_fmt(char *mode)
+{
+ int i;
+ static char const *hdmi4k[] = {
+ "2160p",
+ "smpte",
+ NULL
+ };
+
+ for (i = 0; hdmi4k[i]; i++) {
+ if (strstr(mode, hdmi4k[i]))
+ return 1;
+ }
+ return 0;
+}
+
+/* For some TV's EDID, there maybe exist some information ambiguous.
+ * Such as EDID declears support 2160p60hz(Y444 8bit), but no valid
+ * Max_TMDS_Clock2 to indicate that it can support 5.94G signal.
+ */
+bool hdmitx_edid_check_valid_mode(struct hdmitx_dev *hdev,
+ struct hdmi_format_para *para)
+{
+ bool valid = 0;
+ struct rx_cap *prxcap = NULL;
+ struct dv_info *dv = &hdev->RXCap.dv_info;
+ unsigned int rx_max_tmds_clk = 0;
+ unsigned int calc_tmds_clk = 0;
+ int i = 0;
+ int svd_flag = 0;
+ /* Default max color depth is 24 bit */
+ enum hdmi_color_depth rx_y444_max_dc = HDMI_COLOR_DEPTH_24B;
+ enum hdmi_color_depth rx_y420_max_dc = HDMI_COLOR_DEPTH_24B;
+ enum hdmi_color_depth rx_rgb_max_dc = HDMI_COLOR_DEPTH_24B;
+
+ if (!hdev || !para)
+ return 0;
+ /* if current limits to 1080p, here will check the freshrate and
+ * 4k resolution
+ */
+ if (is_hdmitx_limited_1080p()) {
+ if (is_vic_over_limited_1080p(para->vic)) {
+ printf("over limited vic %d in %s\n", para->vic, __func__);
+ return 0;
+ }
+ }
+
+ if (strcmp(para->sname, "invalid") == 0)
+ return 0;
+ if (!is_support_4k() && is_4k_fmt(para->sname))
+ return false;
+ /* exclude such as: 2160p60hz YCbCr444 10bit */
+ switch (para->vic) {
+ case HDMI_3840x2160p50_16x9:
+ case HDMI_3840x2160p60_16x9:
+ case HDMI_4096x2160p50_256x135:
+ case HDMI_4096x2160p60_256x135:
+ case HDMI_3840x2160p50_64x27:
+ case HDMI_3840x2160p60_64x27:
+ if ((para->cs == HDMI_COLOR_FORMAT_RGB) ||
+ (para->cs == HDMI_COLOR_FORMAT_444))
+ if (para->cd != HDMI_COLOR_DEPTH_24B)
+ return 0;
+ break;
+ default:
+ break;
+ }
+
+ prxcap = &hdev->RXCap;
+
+ /* DVI case, only 8bit */
+ if (prxcap->IEEEOUI != HDMI_IEEEOUI) {
+ if (para->cd != HDMI_COLOR_DEPTH_24B)
+ return 0;
+ }
+
+ /* target mode is not contained at RX SVD */
+ for (i = 0; (i < prxcap->VIC_count) && (i < VIC_MAX_NUM); i++) {
+ if ((para->vic & 0xff) == (prxcap->VIC[i] & 0xff))
+ svd_flag = 1;
+ }
+ if (svd_flag == 0)
+ return 0;
+
+ /* Get RX Max_TMDS_Clock */
+ if (prxcap->Max_TMDS_Clock2) {
+ rx_max_tmds_clk = prxcap->Max_TMDS_Clock2 * 5;
+ } else {
+ /* Default min is 74.25 / 5 */
+ if (prxcap->Max_TMDS_Clock1 < 0xf)
+ prxcap->Max_TMDS_Clock1 = 0x1e;
+ rx_max_tmds_clk = prxcap->Max_TMDS_Clock1 * 5;
+ }
+
+ calc_tmds_clk = para->tmds_clk;
+ if (para->cs == HDMI_COLOR_FORMAT_420)
+ calc_tmds_clk = calc_tmds_clk / 2;
+ if (para->cs != HDMI_COLOR_FORMAT_422) {
+ switch (para->cd) {
+ case HDMI_COLOR_DEPTH_30B:
+ calc_tmds_clk = calc_tmds_clk * 5 / 4;
+ break;
+ case HDMI_COLOR_DEPTH_36B:
+ calc_tmds_clk = calc_tmds_clk * 3 / 2;
+ break;
+ case HDMI_COLOR_DEPTH_48B:
+ calc_tmds_clk = calc_tmds_clk * 2;
+ break;
+ case HDMI_COLOR_DEPTH_24B:
+ default:
+ calc_tmds_clk = calc_tmds_clk * 1;
+ break;
+ }
+ }
+ /* if current status already limited to 1080p, so here also needs to
+ * limit the rx_max_tmds_clk as 150 * 1.5 = 225 to make the valid mode
+ * checking works
+ */
+ if (is_hdmitx_limited_1080p()) {
+ if (rx_max_tmds_clk > 225)
+ rx_max_tmds_clk = 225;
+ }
+ calc_tmds_clk = calc_tmds_clk / 1000;
+ /* printf("RX tmds clk: %d Calc clk: %d\n", */
+ /* rx_max_tmds_clk, calc_tmds_clk); */
+ if (calc_tmds_clk < rx_max_tmds_clk)
+ valid = 1;
+ else
+ return 0;
+
+ if (para->cs == HDMI_COLOR_FORMAT_444) {
+ /* Rx may not support Y444 */
+ if (!(prxcap->native_Mode & (1 << 5)))
+ return 0;
+ if ((prxcap->dc_y444 && prxcap->dc_30bit) ||
+ (dv->sup_10b_12b_444 == 0x1))
+ rx_y444_max_dc = HDMI_COLOR_DEPTH_30B;
+ if ((prxcap->dc_y444 && prxcap->dc_36bit) ||
+ (dv->sup_10b_12b_444 == 0x2))
+ rx_y444_max_dc = HDMI_COLOR_DEPTH_36B;
+ if (para->cd <= rx_y444_max_dc)
+ valid = 1;
+ else
+ valid = 0;
+ return valid;
+ }
+ if (para->cs == HDMI_COLOR_FORMAT_422) {
+ /* Rx may not support Y422 */
+ if (!(prxcap->native_Mode & (1 << 4)))
+ return 0;
+ return 1;
+ }
+ if (para->cs == HDMI_COLOR_FORMAT_RGB) {
+ /* Always assume RX supports RGB444 */
+ if ((prxcap->dc_30bit) || (dv->sup_10b_12b_444 == 0x1))
+ rx_rgb_max_dc = HDMI_COLOR_DEPTH_30B;
+ if ((prxcap->dc_36bit) || (dv->sup_10b_12b_444 == 0x2))
+ rx_rgb_max_dc = HDMI_COLOR_DEPTH_36B;
+ if (para->cd <= rx_rgb_max_dc)
+ valid = 1;
+ else
+ valid = 0;
+ return valid;
+ }
+ if (para->cs == HDMI_COLOR_FORMAT_420) {
+ if (!is_rx_support_y420(hdev))
+ return 0;
+ if (prxcap->dc_30bit_420)
+ rx_y420_max_dc = HDMI_COLOR_DEPTH_30B;
+ if (prxcap->dc_36bit_420)
+ rx_y420_max_dc = HDMI_COLOR_DEPTH_36B;
+ if (para->cd <= rx_y420_max_dc)
+ valid = 1;
+ else
+ valid = 0;
+ return valid;
+ }
+
+ return valid;
+}
+
+bool is_supported_mode_attr(hdmi_data_t *hdmi_data, char *mode_attr)
+{
+ struct hdmi_format_para *para = NULL;
+ struct hdmitx_dev *hdev = NULL;
+
+ if (!hdmi_data || !mode_attr)
+ return false;
+ hdev = container_of(hdmi_data->pRXCap,
+ struct hdmitx_dev, RXCap);
+
+ if (mode_attr[0]) {
+ if (!pre_process_str(mode_attr))
+ return false;
+ para = hdmi_tst_fmt_name(mode_attr, mode_attr);
+ }
+ /* if (para) { */
+ /* printf("sname = %s\n", para->sname); */
+ /* printf("char_clk = %d\n", para->tmds_clk); */
+ /* printf("cd = %d\n", para->cd); */
+ /* printf("cs = %d\n", para->cs); */
+ /* } */
+
+ return hdmitx_edid_check_valid_mode(hdev, para);
+}
+
+bool hdmitx_chk_mode_attr_sup(hdmi_data_t *hdmi_data, char *mode, char *attr)
+{
+ struct hdmi_format_para *para = NULL;
+ struct hdmitx_dev *hdev = NULL;
+
+ if (!hdmi_data || !mode || !attr)
+ return false;
+ hdev = container_of(hdmi_data->pRXCap,
+ struct hdmitx_dev, RXCap);
+
+ if (attr[0]) {
+ if (!pre_process_str(attr))
+ return false;
+ para = hdmi_tst_fmt_name(mode, attr);
+ }
+ /* if (para) { */
+ /* printf("sname = %s\n", para->sname); */
+ /* printf("char_clk = %d\n", para->tmds_clk); */
+ /* printf("cd = %d\n", para->cd); */
+ /* printf("cs = %d\n", para->cs); */
+ /* } */
+
+ return hdmitx_edid_check_valid_mode(hdev, para);
+}
+
+/* force_flag: 0 means check with RX's edid */
+/* 1 means no check wich RX's edid */
+enum hdmi_vic hdmitx_edid_get_VIC(struct hdmitx_dev *hdev,
+ const char *disp_mode, char force_flag)
+{
+ struct rx_cap *prxcap = &hdev->RXCap;
+ int j;
+ enum hdmi_vic vic = hdmitx_edid_vic_tab_map_vic(disp_mode);
+ #if 0
+ struct hdmi_format_para *para = NULL;
+ enum hdmi_vic *vesa_t = &hdev->RXCap.vesa_timing[0];
+ enum hdmi_vic vesa_vic;
+
+ if (vic >= HDMITX_VESA_OFFSET)
+ vesa_vic = vic;
+ else
+ vesa_vic = HDMI_unkown;
+ #endif
+ if (vic != HDMI_unkown) {
+ if (force_flag == 0) {
+ for (j = 0 ; j < prxcap->VIC_count ; j++) {
+ if (prxcap->VIC[j] == vic)
+ break;
+ }
+ if (j >= prxcap->VIC_count)
+ vic = HDMI_unkown;
+ }
+ }
+ #if 0
+ if ((vic == HDMI_unkown) &&
+ (vesa_vic != HDMI_unkown)) {
+ for (j = 0; vesa_t[j] && j < VESA_MAX_TIMING; j++) {
+ para = hdmi_get_fmt_paras(vesa_t[j]);
+ if (para) {
+ if ((para->vic >= HDMITX_VESA_OFFSET) &&
+ (vesa_vic == para->vic)) {
+ vic = para->vic;
+ break;
+ }
+ }
+ }
+ }
+ #endif
+ return vic;
+}
+
+static bool hdmitx_edid_notify_ng(unsigned char *buf)
+{
+ if (!buf)
+ return true;
+
+ return check_dvi_hdmi_edid_valid(buf) == 0;
+}
+
+bool edid_parsing_ok(struct hdmitx_dev *hdev)
+{
+ if (!hdev)
+ return false;
+
+ if (hdmitx_edid_notify_ng(hdev->rawedid))
+ return false;
+ return true;
+}
+
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmi_parameters.c b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmi_parameters.c
new file mode 100644
index 0000000..ac46ec4
--- /dev/null
+++ b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmi_parameters.c
@@ -0,0 +1,2440 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <linux/stddef.h>
+#include <amlogic/media/vout/hdmitx/hdmitx.h>
+
+static struct hdmi_format_para fmt_para_1920x1080p60_16x9 = {
+ .vic = HDMI_1920x1080p60_16x9,
+ .name = "1920x1080p60hz",
+ .sname = "1080p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 148500,
+ .timing = {
+ .pixel_freq = 148500,
+ .h_freq = 67500,
+ .v_freq = 60000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1920,
+ .h_total = 2200,
+ .h_blank = 280,
+ .h_front = 88,
+ .h_sync = 44,
+ .h_back = 148,
+ .v_active = 1080,
+ .v_total = 1125,
+ .v_blank = 45,
+ .v_front = 4,
+ .v_sync = 5,
+ .v_back = 36,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_1920x1080p30_16x9 = {
+ .vic = HDMI_1920x1080p30_16x9,
+ .name = "1920x1080p30hz",
+ .sname = "1080p30hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 74250,
+ .timing = {
+ .pixel_freq = 74250,
+ .h_freq = 67500,
+ .v_freq = 30000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1920,
+ .h_total = 2200,
+ .h_blank = 280,
+ .h_front = 88,
+ .h_sync = 44,
+ .h_back = 148,
+ .v_active = 1080,
+ .v_total = 1125,
+ .v_blank = 45,
+ .v_front = 4,
+ .v_sync = 5,
+ .v_back = 36,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_1920x1080p50_16x9 = {
+ .vic = HDMI_1920x1080p50_16x9,
+ .name = "1920x1080p50hz",
+ .sname = "1080p50hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 148500,
+ .timing = {
+ .pixel_freq = 148500,
+ .h_freq = 56250,
+ .v_freq = 50000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1920,
+ .h_total = 2640,
+ .h_blank = 720,
+ .h_front = 528,
+ .h_sync = 44,
+ .h_back = 148,
+ .v_active = 1080,
+ .v_total = 1125,
+ .v_blank = 45,
+ .v_front = 4,
+ .v_sync = 5,
+ .v_back = 36,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_1920x1080p100_16x9 = {
+ .vic = HDMI_1920x1080p100_16x9,
+ .name = "1920x1080p100hz",
+ .sname = "1080p100hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 297000,
+ .timing = {
+ .pixel_freq = 297000,
+ .h_freq = 112500,
+ .v_freq = 100000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1920,
+ .h_total = 2640,
+ .h_blank = 720,
+ .h_front = 528,
+ .h_sync = 44,
+ .h_back = 148,
+ .v_active = 1080,
+ .v_total = 1125,
+ .v_blank = 45,
+ .v_front = 4,
+ .v_sync = 5,
+ .v_back = 36,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_1920x1080p120_16x9 = {
+ .vic = HDMI_1920x1080p120_16x9,
+ .name = "1920x1080p120hz",
+ .sname = "1080p120hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 297000,
+ .timing = {
+ .pixel_freq = 297000,
+ .h_freq = 135000,
+ .v_freq = 120000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1920,
+ .h_total = 2200,
+ .h_blank = 280,
+ .h_front = 88,
+ .h_sync = 44,
+ .h_back = 148,
+ .v_active = 1080,
+ .v_total = 1125,
+ .v_blank = 45,
+ .v_front = 4,
+ .v_sync = 5,
+ .v_back = 36,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_1920x1080p25_16x9 = {
+ .vic = HDMI_1920x1080p25_16x9,
+ .name = "1920x1080p25hz",
+ .sname = "1080p25hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 148500,
+ .timing = {
+ .pixel_freq = 148500,
+ .h_freq = 56250,
+ .v_freq = 50000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1920,
+ .h_total = 2640,
+ .h_blank = 720,
+ .h_front = 528,
+ .h_sync = 44,
+ .h_back = 148,
+ .v_active = 1080,
+ .v_total = 1125,
+ .v_blank = 45,
+ .v_front = 4,
+ .v_sync = 5,
+ .v_back = 36,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_1920x1080p24_16x9 = {
+ .vic = HDMI_1920x1080p24_16x9,
+ .name = "1920x1080p24hz",
+ .sname = "1080p24hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 74250,
+ .timing = {
+ .pixel_freq = 74250,
+ .h_freq = 27000,
+ .v_freq = 24000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1920,
+ .h_total = 2750,
+ .h_blank = 830,
+ .h_front = 638,
+ .h_sync = 44,
+ .h_back = 148,
+ .v_active = 1080,
+ .v_total = 1125,
+ .v_blank = 45,
+ .v_front = 4,
+ .v_sync = 5,
+ .v_back = 36,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_3840x2160p30_16x9 = {
+ .vic = HDMI_3840x2160p30_16x9,
+ .name = "3840x2160p30hz",
+ .sname = "2160p30hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 297000,
+ .timing = {
+ .pixel_freq = 297000,
+ .h_freq = 67500,
+ .v_freq = 30000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 3840,
+ .h_total = 4400,
+ .h_blank = 560,
+ .h_front = 176,
+ .h_sync = 88,
+ .h_back = 296,
+ .v_active = 2160,
+ .v_total = 2250,
+ .v_blank = 90,
+ .v_front = 8,
+ .v_sync = 10,
+ .v_back = 72,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_3840x2160p60_16x9 = {
+ .vic = HDMI_3840x2160p60_16x9,
+ .name = "3840x2160p60hz",
+ .sname = "2160p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 1,
+ .tmds_clk_div40 = 1,
+ .tmds_clk = 594000,
+ .timing = {
+ .pixel_freq = 594000,
+ .h_freq = 135000,
+ .v_freq = 60000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 3840,
+ .h_total = 4400,
+ .h_blank = 560,
+ .h_front = 176,
+ .h_sync = 88,
+ .h_back = 296,
+ .v_active = 2160,
+ .v_total = 2250,
+ .v_blank = 90,
+ .v_front = 8,
+ .v_sync = 10,
+ .v_back = 72,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_3840x2160p60_y420_16x9 = {
+ .vic = HDMI_3840x2160p60_16x9_Y420,
+ .name = "3840x2160p60hz420",
+ .sname = "2160p60hz420",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 1,
+ .tmds_clk_div40 = 1,
+ .tmds_clk = 594000,
+ .timing = {
+ .pixel_freq = 594000,
+ .h_freq = 135000,
+ .v_freq = 60000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 3840 / 2,
+ .h_total = 4400 / 2,
+ .h_blank = 560 / 2,
+ .h_front = 176 / 2,
+ .h_sync = 88 / 2,
+ .h_back = 296 / 2,
+ .v_active = 2160,
+ .v_total = 2250,
+ .v_blank = 90,
+ .v_front = 8,
+ .v_sync = 10,
+ .v_back = 72,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_3840x2160p50_16x9 = {
+ .vic = HDMI_3840x2160p50_16x9,
+ .name = "3840x2160p50hz",
+ .sname = "2160p50hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 1,
+ .tmds_clk_div40 = 1,
+ .tmds_clk = 594000,
+ .timing = {
+ .pixel_freq = 594000,
+ .h_freq = 112500,
+ .v_freq = 50000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 3840,
+ .h_total = 5280,
+ .h_blank = 1440,
+ .h_front = 1056,
+ .h_sync = 88,
+ .h_back = 296,
+ .v_active = 2160,
+ .v_total = 2250,
+ .v_blank = 90,
+ .v_front = 8,
+ .v_sync = 10,
+ .v_back = 72,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_3840x2160p50_y420_16x9 = {
+ .vic = HDMI_3840x2160p50_16x9_Y420,
+ .name = "3840x2160p50hz420",
+ .sname = "2160p50hz420",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 1,
+ .tmds_clk_div40 = 1,
+ .tmds_clk = 594000,
+ .timing = {
+ .pixel_freq = 594000,
+ .h_freq = 112500,
+ .v_freq = 50000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 3840 / 2,
+ .h_total = 5280 / 2,
+ .h_blank = 1440 / 2,
+ .h_front = 1056 / 2,
+ .h_sync = 88 / 2,
+ .h_back = 296 / 2,
+ .v_active = 2160,
+ .v_total = 2250,
+ .v_blank = 90,
+ .v_front = 8,
+ .v_sync = 10,
+ .v_back = 72,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_3840x2160p25_16x9 = {
+ .vic = HDMI_3840x2160p25_16x9,
+ .name = "3840x2160p25hz",
+ .sname = "2160p25hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 297000,
+ .timing = {
+ .pixel_freq = 297000,
+ .h_freq = 56250,
+ .v_freq = 25000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 3840,
+ .h_total = 5280,
+ .h_blank = 1440,
+ .h_front = 1056,
+ .h_sync = 88,
+ .h_back = 296,
+ .v_active = 2160,
+ .v_total = 2250,
+ .v_blank = 90,
+ .v_front = 8,
+ .v_sync = 10,
+ .v_back = 72,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_3840x2160p24_16x9 = {
+ .vic = HDMI_3840x2160p24_16x9,
+ .name = "3840x2160p24hz",
+ .sname = "2160p24hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 297000,
+ .timing = {
+ .pixel_freq = 297000,
+ .h_freq = 54000,
+ .v_freq = 24000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 3840,
+ .h_total = 5500,
+ .h_blank = 1660,
+ .h_front = 1276,
+ .h_sync = 88,
+ .h_back = 296,
+ .v_active = 2160,
+ .v_total = 2250,
+ .v_blank = 90,
+ .v_front = 8,
+ .v_sync = 10,
+ .v_back = 72,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_4096x2160p24_256x135 = {
+ .vic = HDMI_4096x2160p24_256x135,
+ .name = "4096x2160p24hz",
+ .sname = "smpte24hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 297000,
+ .timing = {
+ .pixel_freq = 297000,
+ .h_freq = 54000,
+ .v_freq = 24000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 4096,
+ .h_total = 5500,
+ .h_blank = 1404,
+ .h_front = 1020,
+ .h_sync = 88,
+ .h_back = 296,
+ .v_active = 2160,
+ .v_total = 2250,
+ .v_blank = 90,
+ .v_front = 8,
+ .v_sync = 10,
+ .v_back = 72,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_4096x2160p25_256x135 = {
+ .vic = HDMI_4096x2160p25_256x135,
+ .name = "4096x2160p25hz",
+ .sname = "smpte25hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 297000,
+ .timing = {
+ .pixel_freq = 297000,
+ .h_freq = 56250,
+ .v_freq = 25000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 4096,
+ .h_total = 5280,
+ .h_blank = 1184,
+ .h_front = 968,
+ .h_sync = 88,
+ .h_back = 128,
+ .v_active = 2160,
+ .v_total = 2250,
+ .v_blank = 90,
+ .v_front = 8,
+ .v_sync = 10,
+ .v_back = 72,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_4096x2160p30_256x135 = {
+ .vic = HDMI_4096x2160p30_256x135,
+ .name = "4096x2160p30hz",
+ .sname = "smpte30hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 297000,
+ .timing = {
+ .pixel_freq = 297000,
+ .h_freq = 67500,
+ .v_freq = 30000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 4096,
+ .h_total = 4400,
+ .h_blank = 304,
+ .h_front = 88,
+ .h_sync = 88,
+ .h_back = 128,
+ .v_active = 2160,
+ .v_total = 2250,
+ .v_blank = 90,
+ .v_front = 8,
+ .v_sync = 10,
+ .v_back = 72,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_4096x2160p50_256x135 = {
+ .vic = HDMI_4096x2160p50_256x135,
+ .name = "4096x2160p50hz",
+ .sname = "smpte50hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 1,
+ .tmds_clk_div40 = 1,
+ .tmds_clk = 594000,
+ .timing = {
+ .pixel_freq = 594000,
+ .h_freq = 112500,
+ .v_freq = 50000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 4096,
+ .h_total = 5280,
+ .h_blank = 1184,
+ .h_front = 968,
+ .h_sync = 88,
+ .h_back = 128,
+ .v_active = 2160,
+ .v_total = 2250,
+ .v_blank = 90,
+ .v_front = 8,
+ .v_sync = 10,
+ .v_back = 72,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_4096x2160p50_y420_256x135 = {
+ .vic = HDMI_4096x2160p50_256x135_Y420,
+ .name = "4096x2160p50hz420",
+ .sname = "smpte50hz420",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 1,
+ .tmds_clk_div40 = 1,
+ .tmds_clk = 594000,
+ .timing = {
+ .pixel_freq = 594000,
+ .h_freq = 112500,
+ .v_freq = 50000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 4096 / 2,
+ .h_total = 5280 / 2,
+ .h_blank = 1184 / 2,
+ .h_front = 968 / 2,
+ .h_sync = 88 / 2,
+ .h_back = 128 / 2,
+ .v_active = 2160,
+ .v_total = 2250,
+ .v_blank = 90,
+ .v_front = 8,
+ .v_sync = 10,
+ .v_back = 72,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_4096x2160p60_256x135 = {
+ .vic = HDMI_4096x2160p60_256x135,
+ .name = "4096x2160p60hz",
+ .sname = "smpte60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 1,
+ .tmds_clk_div40 = 1,
+ .tmds_clk = 594000,
+ .timing = {
+ .pixel_freq = 594000,
+ .h_freq = 135000,
+ .v_freq = 60000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 4096,
+ .h_total = 4400,
+ .h_blank = 304,
+ .h_front = 88,
+ .h_sync = 88,
+ .h_back = 128,
+ .v_active = 2160,
+ .v_total = 2250,
+ .v_blank = 90,
+ .v_front = 8,
+ .v_sync = 10,
+ .v_back = 72,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_4096x2160p60_y420_256x135 = {
+ .vic = HDMI_4096x2160p60_256x135_Y420,
+ .name = "4096x2160p60hz420",
+ .sname = "smpte60hz420",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 1,
+ .tmds_clk_div40 = 1,
+ .tmds_clk = 594000,
+ .timing = {
+ .pixel_freq = 594000,
+ .h_freq = 135000,
+ .v_freq = 60000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 4096 / 2,
+ .h_total = 4400 / 2,
+ .h_blank = 304 / 2,
+ .h_front = 88 / 2,
+ .h_sync = 88 / 2,
+ .h_back = 128 / 2,
+ .v_active = 2160,
+ .v_total = 2250,
+ .v_blank = 90,
+ .v_front = 8,
+ .v_sync = 10,
+ .v_back = 72,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_1920x1080i60_16x9 = {
+ .vic = HDMI_1920x1080i60_16x9,
+ .name = "1920x1080i60hz",
+ .sname = "1080i60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 0,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 74250,
+ .timing = {
+ .pixel_freq = 74250,
+ .h_freq = 33750,
+ .v_freq = 60000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1920,
+ .h_total = 2200,
+ .h_blank = 280,
+ .h_front = 88,
+ .h_sync = 44,
+ .h_back = 148,
+ .v_active = 1080/2,
+ .v_total = 1125,
+ .v_blank = 45/2,
+ .v_front = 2,
+ .v_sync = 5,
+ .v_back = 15,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_1920x1080i50_16x9 = {
+ .vic = HDMI_1920x1080i50_16x9,
+ .name = "1920x1080i50hz",
+ .sname = "1080i50hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 0,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 74250,
+ .timing = {
+ .pixel_freq = 74250,
+ .h_freq = 28125,
+ .v_freq = 50000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1920,
+ .h_total = 2640,
+ .h_blank = 720,
+ .h_front = 528,
+ .h_sync = 44,
+ .h_back = 148,
+ .v_active = 1080/2,
+ .v_total = 1125,
+ .v_blank = 45/2,
+ .v_front = 2,
+ .v_sync = 5,
+ .v_back = 15,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_1920x1080i100_16x9 = {
+ .vic = HDMI_1920x1080i100_16x9,
+ .name = "1920x1080i100hz",
+ .sname = "1080i100hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 0,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 148500,
+ .timing = {
+ .pixel_freq = 148500,
+ .h_freq = 56250,
+ .v_freq = 100000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1920,
+ .h_total = 2640,
+ .h_blank = 720,
+ .h_front = 528,
+ .h_sync = 44,
+ .h_back = 148,
+ .v_active = 1080/2,
+ .v_total = 1125,
+ .v_blank = 45/2,
+ .v_front = 2,
+ .v_sync = 5,
+ .v_back = 15,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_1920x1080i120_16x9 = {
+ .vic = HDMI_1920x1080i120_16x9,
+ .name = "1920x1080i120hz",
+ .sname = "1080i120hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 0,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 148500,
+ .timing = {
+ .pixel_freq = 148500,
+ .h_freq = 67500,
+ .v_freq = 120000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1920,
+ .h_total = 2200,
+ .h_blank = 280,
+ .h_front = 88,
+ .h_sync = 44,
+ .h_back = 148,
+ .v_active = 1080/2,
+ .v_total = 1125,
+ .v_blank = 45/2,
+ .v_front = 2,
+ .v_sync = 5,
+ .v_back = 15,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_1280x720p60_16x9 = {
+ .vic = HDMI_1280x720p60_16x9,
+ .name = "1280x720p60hz",
+ .sname = "720p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 74250,
+ .timing = {
+ .pixel_freq = 74250,
+ .h_freq = 45000,
+ .v_freq = 60000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1280,
+ .h_total = 1650,
+ .h_blank = 370,
+ .h_front = 110,
+ .h_sync = 40,
+ .h_back = 220,
+ .v_active = 720,
+ .v_total = 750,
+ .v_blank = 30,
+ .v_front = 5,
+ .v_sync = 5,
+ .v_back = 20,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_1280x720p50_16x9 = {
+ .vic = HDMI_1280x720p50_16x9,
+ .name = "1280x720p50hz",
+ .sname = "720p50hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 74250,
+ .timing = {
+ .pixel_freq = 74250,
+ .h_freq = 37500,
+ .v_freq = 50000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1280,
+ .h_total = 1980,
+ .h_blank = 700,
+ .h_front = 440,
+ .h_sync = 40,
+ .h_back = 220,
+ .v_active = 720,
+ .v_total = 750,
+ .v_blank = 30,
+ .v_front = 5,
+ .v_sync = 5,
+ .v_back = 20,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_1280x720p100_16x9 = {
+ .vic = HDMI_1280x720p100_16x9,
+ .name = "1280x720p100hz",
+ .sname = "720p100hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 148500,
+ .timing = {
+ .pixel_freq = 148500,
+ .h_freq = 75000,
+ .v_freq = 100000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1280,
+ .h_total = 1980,
+ .h_blank = 700,
+ .h_front = 440,
+ .h_sync = 40,
+ .h_back = 220,
+ .v_active = 720,
+ .v_total = 750,
+ .v_blank = 30,
+ .v_front = 5,
+ .v_sync = 5,
+ .v_back = 20,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_1280x720p120_16x9 = {
+ .vic = HDMI_1280x720p120_16x9,
+ .name = "1280x720p120hz",
+ .sname = "720p120hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 148500,
+ .timing = {
+ .pixel_freq = 148500,
+ .h_freq = 90000,
+ .v_freq = 120000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1280,
+ .h_total = 1650,
+ .h_blank = 370,
+ .h_front = 110,
+ .h_sync = 40,
+ .h_back = 220,
+ .v_active = 720,
+ .v_total = 750,
+ .v_blank = 30,
+ .v_front = 5,
+ .v_sync = 5,
+ .v_back = 20,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_720x480p60_16x9 = {
+ .vic = HDMI_720x480p60_16x9,
+ .name = "720x480p60hz",
+ .sname = "480p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 27000,
+ .timing = {
+ .pixel_freq = 27000,
+ .h_freq = 31469,
+ .v_freq = 59940,
+ .vsync_polarity = 0,
+ .hsync_polarity = 0,
+ .h_active = 720,
+ .h_total = 858,
+ .h_blank = 138,
+ .h_front = 16,
+ .h_sync = 62,
+ .h_back = 60,
+ .v_active = 480,
+ .v_total = 525,
+ .v_blank = 45,
+ .v_front = 9,
+ .v_sync = 6,
+ .v_back = 30,
+ .v_sync_ln = 7,
+ },
+};
+
+static struct hdmi_format_para fmt_para_720x480p60_4x3 = {
+ .vic = HDMI_720x480p60_4x3,
+ .name = "720x480p60hz_4x3",
+ .sname = "480p60hz_4x3",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 27000,
+ .timing = {
+ .pixel_freq = 27000,
+ .h_freq = 31469,
+ .v_freq = 59940,
+ .vsync_polarity = 0,
+ .hsync_polarity = 0,
+ .h_active = 720,
+ .h_total = 858,
+ .h_blank = 138,
+ .h_front = 16,
+ .h_sync = 62,
+ .h_back = 60,
+ .v_active = 480,
+ .v_total = 525,
+ .v_blank = 45,
+ .v_front = 9,
+ .v_sync = 6,
+ .v_back = 30,
+ .v_sync_ln = 7,
+ },
+};
+
+static struct hdmi_format_para fmt_para_720x480p120_16x9 = {
+ .vic = HDMI_720x480p120_16x9,
+ .name = "720x480p120hz",
+ .sname = "480p120hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 54000,
+ .timing = {
+ .pixel_freq = 54000,
+ .h_freq = 62937,
+ .v_freq = 119880,
+ .vsync_polarity = 0,
+ .hsync_polarity = 0,
+ .h_active = 720,
+ .h_total = 858,
+ .h_blank = 138,
+ .h_front = 16,
+ .h_sync = 62,
+ .h_back = 60,
+ .v_active = 480,
+ .v_total = 525,
+ .v_blank = 45,
+ .v_front = 9,
+ .v_sync = 6,
+ .v_back = 30,
+ .v_sync_ln = 7,
+ },
+};
+
+static struct hdmi_format_para fmt_para_720x480i60_16x9 = {
+ .vic = HDMI_720x480i60_16x9,
+ .name = "720x480i60hz",
+ .sname = "480i60hz",
+ .pixel_repetition_factor = 1,
+ .progress_mode = 0,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 27000,
+ .timing = {
+ .pixel_freq = 27000,
+ .h_freq = 15734,
+ .v_freq = 59940,
+ .vsync_polarity = 0,
+ .hsync_polarity = 0,
+ .h_active = 1440,
+ .h_total = 1716,
+ .h_blank = 276,
+ .h_front = 38,
+ .h_sync = 124,
+ .h_back = 114,
+ .v_active = 480/2,
+ .v_total = 525,
+ .v_blank = 45/2,
+ .v_front = 4,
+ .v_sync = 3,
+ .v_back = 15,
+ .v_sync_ln = 4,
+ },
+};
+
+static struct hdmi_format_para fmt_para_720x480i60_4x3 = {
+ .vic = HDMI_720x480i60_4x3,
+ .name = "720x480i60hz_4x3",
+ .sname = "480i60hz_4x3",
+ .pixel_repetition_factor = 1,
+ .progress_mode = 0,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 27000,
+ .timing = {
+ .pixel_freq = 27000,
+ .h_freq = 15734,
+ .v_freq = 59940,
+ .vsync_polarity = 0,
+ .hsync_polarity = 0,
+ .h_active = 1440,
+ .h_total = 1716,
+ .h_blank = 276,
+ .h_front = 38,
+ .h_sync = 124,
+ .h_back = 114,
+ .v_active = 480/2,
+ .v_total = 525,
+ .v_blank = 45/2,
+ .v_front = 4,
+ .v_sync = 3,
+ .v_back = 15,
+ .v_sync_ln = 4,
+ },
+};
+
+static struct hdmi_format_para fmt_para_720x576p50_16x9 = {
+ .vic = HDMI_720x576p50_16x9,
+ .name = "720x576p50hz",
+ .sname = "576p50hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 27000,
+ .timing = {
+ .pixel_freq = 27000,
+ .h_freq = 31250,
+ .v_freq = 50000,
+ .vsync_polarity = 0,
+ .hsync_polarity = 0,
+ .h_active = 720,
+ .h_total = 864,
+ .h_blank = 144,
+ .h_front = 12,
+ .h_sync = 64,
+ .h_back = 68,
+ .v_active = 576,
+ .v_total = 625,
+ .v_blank = 49,
+ .v_front = 5,
+ .v_sync = 5,
+ .v_back = 39,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_720x576p50_4x3 = {
+ .vic = HDMI_720x576p50_4x3,
+ .name = "720x576p50hz_4x3",
+ .sname = "576p50hz_4x3",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 27000,
+ .timing = {
+ .pixel_freq = 27000,
+ .h_freq = 31250,
+ .v_freq = 50000,
+ .vsync_polarity = 0,
+ .hsync_polarity = 0,
+ .h_active = 720,
+ .h_total = 864,
+ .h_blank = 144,
+ .h_front = 12,
+ .h_sync = 64,
+ .h_back = 68,
+ .v_active = 576,
+ .v_total = 625,
+ .v_blank = 49,
+ .v_front = 5,
+ .v_sync = 5,
+ .v_back = 39,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_720x576p100_16x9 = {
+ .vic = HDMI_720x576p100_16x9,
+ .name = "720x576p100hz",
+ .sname = "576p100hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 54000,
+ .timing = {
+ .pixel_freq = 54000,
+ .h_freq = 62500,
+ .v_freq = 100000,
+ .vsync_polarity = 0,
+ .hsync_polarity = 0,
+ .h_active = 720,
+ .h_total = 864,
+ .h_blank = 144,
+ .h_front = 12,
+ .h_sync = 64,
+ .h_back = 68,
+ .v_active = 576,
+ .v_total = 625,
+ .v_blank = 49,
+ .v_front = 5,
+ .v_sync = 5,
+ .v_back = 39,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_720x576i50_16x9 = {
+ .vic = HDMI_720x576i50_16x9,
+ .name = "720x576i50hz",
+ .sname = "576i50hz",
+ .pixel_repetition_factor = 1,
+ .progress_mode = 0,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 27000,
+ .timing = {
+ .pixel_freq = 27000,
+ .h_freq = 15625,
+ .v_freq = 50000,
+ .vsync_polarity = 0,
+ .hsync_polarity = 0,
+ .h_active = 1440,
+ .h_total = 1728,
+ .h_blank = 288,
+ .h_front = 24,
+ .h_sync = 126,
+ .h_back = 138,
+ .v_active = 576/2,
+ .v_total = 625,
+ .v_blank = 49/2,
+ .v_front = 2,
+ .v_sync = 3,
+ .v_back = 19,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_720x576i50_4x3 = {
+ .vic = HDMI_720x576i50_4x3,
+ .name = "720x576i50hz_4x3",
+ .sname = "576i50hz_4x3",
+ .pixel_repetition_factor = 1,
+ .progress_mode = 0,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 27000,
+ .timing = {
+ .pixel_freq = 27000,
+ .h_freq = 15625,
+ .v_freq = 50000,
+ .vsync_polarity = 0,
+ .hsync_polarity = 0,
+ .h_active = 1440,
+ .h_total = 1728,
+ .h_blank = 288,
+ .h_front = 24,
+ .h_sync = 126,
+ .h_back = 138,
+ .v_active = 576/2,
+ .v_total = 625,
+ .v_blank = 49/2,
+ .v_front = 2,
+ .v_sync = 3,
+ .v_back = 19,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_non_hdmi_fmt = {
+ .vic = HDMI_unkown,
+ .name = "invalid",
+ .sname = "invalid",
+};
+
+static struct hdmi_format_para fmt_para_vesa_640x480p60_4x3 = {
+ .vic = HDMIV_640x480p60hz,
+ .name = "640x480p60hz",
+ .sname = "640x480p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 25175,
+ .timing = {
+ .pixel_freq = 25175,
+ .h_freq = 26218,
+ .v_freq = 59940,
+ .vsync_polarity = 0,
+ .hsync_polarity = 0,
+ .h_active = 640,
+ .h_total = 800,
+ .h_blank = 160,
+ .h_front = 16,
+ .h_sync = 96,
+ .h_back = 48,
+ .v_active = 480,
+ .v_total = 525,
+ .v_blank = 45,
+ .v_front = 10,
+ .v_sync = 2,
+ .v_back = 33,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_800x480p60_4x3 = {
+ .vic = HDMIV_800x480p60hz,
+ .name = "800x480p60hz",
+ .sname = "800x480p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 29760,
+ .timing = {
+ .pixel_freq = 29760,
+ .h_freq = 30000,
+ .v_freq = 60000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 800,
+ .h_total = 992,
+ .h_blank = 192,
+ .h_front = 24,
+ .h_sync = 72,
+ .h_back = 96,
+ .v_active = 480,
+ .v_total = 500,
+ .v_blank = 20,
+ .v_front = 3,
+ .v_sync = 7,
+ .v_back = 10,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_800x600p60_4x3 = {
+ .vic = HDMIV_800x600p60hz,
+ .name = "800x600p60hz",
+ .sname = "800x600p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 40000,
+ .timing = {
+ .pixel_freq = 66666,
+ .h_freq = 37879,
+ .v_freq = 60317,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 800,
+ .h_total = 1056,
+ .h_blank = 256,
+ .h_front = 40,
+ .h_sync = 128,
+ .h_back = 88,
+ .v_active = 600,
+ .v_total = 628,
+ .v_blank = 28,
+ .v_front = 1,
+ .v_sync = 4,
+ .v_back = 23,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_852x480p60_213x120 = {
+ .vic = HDMIV_852x480p60hz,
+ .name = "852x480p60hz",
+ .sname = "852x480p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 30240,
+ .timing = {
+ .pixel_freq = 30240,
+ .h_freq = 31900,
+ .v_freq = 59960,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 852,
+ .h_total = 948,
+ .h_blank = 96,
+ .h_front = 40,
+ .h_sync = 16,
+ .h_back = 40,
+ .v_active = 480,
+ .v_total = 532,
+ .v_blank = 52,
+ .v_front = 10,
+ .v_sync = 2,
+ .v_back = 40,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_854x480p60_427x240 = {
+ .vic = HDMIV_854x480p60hz,
+ .name = "854x480p60hz",
+ .sname = "854x480p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 30240,
+ .timing = {
+ .pixel_freq = 30240,
+ .h_freq = 31830,
+ .v_freq = 59950,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 854,
+ .h_total = 950,
+ .h_blank = 96,
+ .h_front = 40,
+ .h_sync = 16,
+ .h_back = 40,
+ .v_active = 480,
+ .v_total = 531,
+ .v_blank = 51,
+ .v_front = 10,
+ .v_sync = 2,
+ .v_back = 39,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_1024x600p60_17x10 = {
+ .vic = HDMIV_1024x600p60hz,
+ .name = "1024x600p60hz",
+ .sname = "1024x600p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 50400,
+ .timing = {
+ .pixel_freq = 50400,
+ .h_freq = 38280,
+ .v_freq = 60000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1024,
+ .h_total = 1344,
+ .h_blank = 320,
+ .h_front = 24,
+ .h_sync = 136,
+ .h_back = 160,
+ .v_active = 600,
+ .v_total = 638,
+ .v_blank = 38,
+ .v_front = 3,
+ .v_sync = 6,
+ .v_back = 29,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_1024x768p60_4x3 = {
+ .vic = HDMIV_1024x768p60hz,
+ .name = "1024x768p60hz",
+ .sname = "1024x768p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 79500,
+ .timing = {
+ .pixel_freq = 79500,
+ .h_freq = 48360,
+ .v_freq = 60004,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1024,
+ .h_total = 1344,
+ .h_blank = 320,
+ .h_front = 24,
+ .h_sync = 136,
+ .h_back = 160,
+ .v_active = 768,
+ .v_total = 806,
+ .v_blank = 38,
+ .v_front = 3,
+ .v_sync = 6,
+ .v_back = 29,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_1152x864p75_4x3 = {
+ .vic = HDMIV_1152x864p75hz,
+ .name = "1152x864p75hz",
+ .sname = "1152x864p75hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 108000,
+ .timing = {
+ .pixel_freq = 108000,
+ .h_freq = 67500,
+ .v_freq = 75000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1152,
+ .h_total = 1600,
+ .h_blank = 448,
+ .h_front = 64,
+ .h_sync = 128,
+ .h_back = 256,
+ .v_active = 864,
+ .v_total = 900,
+ .v_blank = 36,
+ .v_front = 1,
+ .v_sync = 3,
+ .v_back = 32,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_1280x600p60_32x15 = {
+#if 0 /* TODO */
+ .vic = HDMIV_1280x600p60hz,
+ .name = "1280x600p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = ,
+ .timing = {
+ .pixel_freq = ,
+ .h_freq = ,
+ .v_freq = 60000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1280,
+ .h_total = ,
+ .h_blank = ,
+ .h_front = ,
+ .h_sync = ,
+ .h_back = ,
+ .v_active = 600,
+ .v_total = ,
+ .v_blank = ,
+ .v_front = ,
+ .v_sync = ,
+ .v_back = ,
+ .v_sync_ln = 1,
+ },
+#endif
+};
+
+static struct hdmi_format_para fmt_para_vesa_1280x768p60_5x3 = {
+ .vic = HDMIV_1280x768p60hz,
+ .name = "1280x768p60hz",
+ .sname = "1280x768p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 79500,
+ .timing = {
+ .pixel_freq = 79500,
+ .h_freq = 47776,
+ .v_freq = 59870,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1280,
+ .h_total = 1664,
+ .h_blank = 384,
+ .h_front = 64,
+ .h_sync = 128,
+ .h_back = 192,
+ .v_active = 768,
+ .v_total = 798,
+ .v_blank = 30,
+ .v_front = 3,
+ .v_sync = 7,
+ .v_back = 20,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_1280x800p60_8x5 = {
+ .vic = HDMIV_1280x800p60hz,
+ .name = "1280x800p60hz",
+ .sname = "1280x800p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 83500,
+ .timing = {
+ .pixel_freq = 83500,
+ .h_freq = 49380,
+ .v_freq = 59910,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1280,
+ .h_total = 1440,
+ .h_blank = 160,
+ .h_front = 48,
+ .h_sync = 32,
+ .h_back = 80,
+ .v_active = 800,
+ .v_total = 823,
+ .v_blank = 23,
+ .v_front = 3,
+ .v_sync = 6,
+ .v_back = 14,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_1280x960p60_4x3 = {
+ .vic = HDMIV_1280x960p60hz,
+ .name = "1280x960p60hz",
+ .sname = "1280x960p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 108000,
+ .timing = {
+ .pixel_freq = 108000,
+ .h_freq = 60000,
+ .v_freq = 60000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1280,
+ .h_total = 1440,
+ .h_blank = 520,
+ .h_front = 96,
+ .h_sync = 112,
+ .h_back = 312,
+ .v_active = 960,
+ .v_total = 1000,
+ .v_blank = 40,
+ .v_front = 1,
+ .v_sync = 3,
+ .v_back = 36,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_1280x1024p60_5x4 = {
+ .vic = HDMIV_1280x1024p60hz,
+ .name = "1280x1024p60hz",
+ .sname = "1280x1024p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 108000,
+ .timing = {
+ .pixel_freq = 108000,
+ .h_freq = 63981,
+ .v_freq = 60020,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1280,
+ .h_total = 1688,
+ .h_blank = 408,
+ .h_front = 48,
+ .h_sync = 112,
+ .h_back = 248,
+ .v_active = 1024,
+ .v_total = 1066,
+ .v_blank = 42,
+ .v_front = 1,
+ .v_sync = 3,
+ .v_back = 38,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_1360x768p60_16x9 = {
+ .vic = HDMIV_1360x768p60hz,
+ .name = "1360x768p60hz",
+ .sname = "1360x768p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 855000,
+ .timing = {
+ .pixel_freq = 855000,
+ .h_freq = 47700,
+ .v_freq = 60015,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1360,
+ .h_total = 1792,
+ .h_blank = 432,
+ .h_front = 64,
+ .h_sync = 112,
+ .h_back = 256,
+ .v_active = 768,
+ .v_total = 795,
+ .v_blank = 27,
+ .v_front = 3,
+ .v_sync = 6,
+ .v_back = 18,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_1366x768p60_16x9 = {
+ .vic = HDMIV_1366x768p60hz,
+ .name = "1366x768p60hz",
+ .sname = "1366x768p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 85500,
+ .timing = {
+ .pixel_freq = 85500,
+ .h_freq = 47880,
+ .v_freq = 59790,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1366,
+ .h_total = 1792,
+ .h_blank = 426,
+ .h_front = 70,
+ .h_sync = 143,
+ .h_back = 213,
+ .v_active = 768,
+ .v_total = 798,
+ .v_blank = 30,
+ .v_front = 3,
+ .v_sync = 3,
+ .v_back = 24,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_1400x1050p60_4x3 = {
+ .vic = HDMIV_1400x1050p60hz,
+ .name = "1400x1050p60hz",
+ .sname = "1400x1050p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 121750,
+ .timing = {
+ .pixel_freq = 121750,
+ .h_freq = 65317,
+ .v_freq = 59978,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1400,
+ .h_total = 1864,
+ .h_blank = 464,
+ .h_front = 88,
+ .h_sync = 144,
+ .h_back = 232,
+ .v_active = 1050,
+ .v_total = 1089,
+ .v_blank = 39,
+ .v_front = 3,
+ .v_sync = 4,
+ .v_back = 32,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_1440x900p60_8x5 = {
+ .vic = HDMIV_1440x900p60hz,
+ .name = "1440x900p60hz",
+ .sname = "1440x900p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 106500,
+ .timing = {
+ .pixel_freq = 106500,
+ .h_freq = 56040,
+ .v_freq = 59887,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1440,
+ .h_total = 1904,
+ .h_blank = 464,
+ .h_front = 80,
+ .h_sync = 152,
+ .h_back = 232,
+ .v_active = 900,
+ .v_total = 934,
+ .v_blank = 34,
+ .v_front = 3,
+ .v_sync = 6,
+ .v_back = 25,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_1440x2560p60_9x16 = {
+ .vic = HDMIV_1440x2560p60hz,
+ .name = "1440x2560p60hz",
+ .sname = "1440x2560p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 244850,
+ .timing = {
+ .pixel_freq = 244850,
+ .h_freq = 155760,
+ .v_freq = 59999,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1440,
+ .h_total = 1572,
+ .h_blank = 132,
+ .h_front = 64,
+ .h_sync = 4,
+ .h_back = 64,
+ .v_active = 2560,
+ .v_total = 2596,
+ .v_blank = 36,
+ .v_front = 16,
+ .v_sync = 4,
+ .v_back = 16,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_1440x2560p70_9x16 = {
+ .vic = HDMIV_1440x2560p70hz,
+ .name = "1440x2560p70hz",
+ .sname = "1440x2560p70hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 280000,
+ .timing = {
+ .pixel_freq = 280000,
+ .h_freq = 180320,
+ .v_freq = 70100,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1440,
+ .h_total = 1550,
+ .h_blank = 110,
+ .h_front = 68,
+ .h_sync = 16,
+ .h_back = 26,
+ .v_active = 2560,
+ .v_total = 2576,
+ .v_blank = 16,
+ .v_front = 6,
+ .v_sync = 6,
+ .v_back = 4,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_1600x900p60_16x9 = {
+ .vic = HDMIV_1600x900p60hz,
+ .name = "1600x900p60hz",
+ .sname = "1600x900p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 108000,
+ .timing = {
+ .pixel_freq = 108000,
+ .h_freq = 60000,
+ .v_freq = 60000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1600,
+ .h_total = 1800,
+ .h_blank = 200,
+ .h_front = 24,
+ .h_sync = 80,
+ .h_back = 96,
+ .v_active = 900,
+ .v_total = 1000,
+ .v_blank = 100,
+ .v_front = 1,
+ .v_sync = 3,
+ .v_back = 96,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_1600x1200p60_4x3 = {
+ .vic = HDMIV_1600x1200p60hz,
+ .name = "1600x1200p60hz",
+ .sname = "1600x1200p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 162000,
+ .timing = {
+ .pixel_freq = 162000,
+ .h_freq = 75000,
+ .v_freq = 60000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1600,
+ .h_total = 2160,
+ .h_blank = 560,
+ .h_front = 64,
+ .h_sync = 192,
+ .h_back = 304,
+ .v_active = 1200,
+ .v_total = 1250,
+ .v_blank = 50,
+ .v_front = 1,
+ .v_sync = 3,
+ .v_back = 46,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_1680x1050p60_8x5 = {
+ .vic = HDMIV_1680x1050p60hz,
+ .name = "1680x1050p60hz",
+ .sname = "1680x1050p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 146250,
+ .timing = {
+ .pixel_freq = 146250,
+ .h_freq = 65290,
+ .v_freq = 59954,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1680,
+ .h_total = 2240,
+ .h_blank = 560,
+ .h_front = 104,
+ .h_sync = 176,
+ .h_back = 280,
+ .v_active = 1050,
+ .v_total = 1089,
+ .v_blank = 39,
+ .v_front = 3,
+ .v_sync = 6,
+ .v_back = 30,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_1920x1200p60_8x5 = {
+ .vic = HDMIV_1920x1200p60hz,
+ .name = "1920x1200p60hz",
+ .sname = "1920x1200p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 193250,
+ .timing = {
+ .pixel_freq = 193250,
+ .h_freq = 74700,
+ .v_freq = 59885,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1920,
+ .h_total = 2592,
+ .h_blank = 672,
+ .h_front = 136,
+ .h_sync = 200,
+ .h_back = 336,
+ .v_active = 1200,
+ .v_total = 1245,
+ .v_blank = 45,
+ .v_front = 3,
+ .v_sync = 6,
+ .v_back = 36,
+ .v_sync_ln = 1,
+ },
+};
+static struct hdmi_format_para fmt_para_vesa_2160x1200p90_9x5 = {
+ .vic = HDMIV_2160x1200p90hz,
+ .name = "2160x1200p90hz",
+ .sname = "2160x1200p90hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 268550,
+ .timing = {
+ .pixel_freq = 268550,
+ .h_freq = 109080,
+ .v_freq = 90000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 2160,
+ .h_total = 2462,
+ .h_blank = 302,
+ .h_front = 190,
+ .h_sync = 32,
+ .h_back = 80,
+ .v_active = 1200,
+ .v_total = 1212,
+ .v_blank = 12,
+ .v_front = 6,
+ .v_sync = 3,
+ .v_back = 3,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_2560x1080p60_64x27 = {
+#if 0 /* TODO */
+ .vic = HDMIV_2560x1080p60hz,
+ .name = "2560x1080p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 193250,
+ .timing = {
+ .pixel_freq = 193250,
+ .h_freq = 74700,
+ .v_freq = 60000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1920,
+ .h_total = 2592,
+ .h_blank = 672,
+ .h_front = 136,
+ .h_sync = 200,
+ .h_back = 336,
+ .v_active = 1200,
+ .v_total = 1245,
+ .v_blank = 45,
+ .v_front = 3,
+ .v_sync = 6,
+ .v_back = 36,
+ .v_sync_ln = 1,
+ },
+#endif
+};
+
+static struct hdmi_format_para fmt_para_vesa_2560x1440p60_16x9 = {
+#if 0 /* TODO */
+ .vic = HDMIV_2560x1440p60hz,
+ .name = "2560x1440p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 193250,
+ .timing = {
+ .pixel_freq = 193250,
+ .h_freq = 74700,
+ .v_freq = 60000,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 1920,
+ .h_total = 2592,
+ .h_blank = 672,
+ .h_front = 136,
+ .h_sync = 200,
+ .h_back = 336,
+ .v_active = 1200,
+ .v_total = 1245,
+ .v_blank = 45,
+ .v_front = 3,
+ .v_sync = 6,
+ .v_back = 36,
+ .v_sync_ln = 1,
+ },
+#endif
+};
+
+static struct hdmi_format_para fmt_para_vesa_2560x1600p60_8x5 = {
+ .vic = HDMIV_2560x1600p60hz,
+ .name = "2560x1600p60hz",
+ .sname = "2560x1600p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 348500,
+ .timing = {
+ .pixel_freq = 348500,
+ .h_freq = 99458,
+ .v_freq = 59987,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 2560,
+ .h_total = 3504,
+ .h_blank = 944,
+ .h_front = 192,
+ .h_sync = 280,
+ .h_back = 472,
+ .v_active = 1600,
+ .v_total = 1658,
+ .v_blank = 58,
+ .v_front = 3,
+ .v_sync = 6,
+ .v_back = 49,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_3440x1440p60_43x18 = {
+ .vic = HDMIV_3440x1440p60hz,
+ .name = "3440x1440p60hz",
+ .sname = "3440x1440p60hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 319750,
+ .timing = {
+ .pixel_freq = 319750,
+ .h_freq = 88819,
+ .v_freq = 59973,
+ .vsync_polarity = 1, /* +VSync */
+ .hsync_polarity = 1, /* +HSync */
+ .h_active = 3440,
+ .h_total = 3600,
+ .h_blank = 160,
+ .h_front = 48,
+ .h_sync = 32,
+ .h_back = 80,
+ .v_active = 1440,
+ .v_total = 1481,
+ .v_blank = 41,
+ .v_front = 3,
+ .v_sync = 10,
+ .v_back = 28,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para fmt_para_vesa_2400x1200p90_2x1 = {
+ .vic = HDMIV_2400x1200p90hz,
+ .name = "2400x1200p90hz",
+ .sname = "2400x1200p90hz",
+ .pixel_repetition_factor = 0,
+ .progress_mode = 1,
+ .scrambler_en = 0,
+ .tmds_clk_div40 = 0,
+ .tmds_clk = 280000,
+ .timing = {
+ .pixel_freq = 280000,
+ .h_freq = 112812,
+ .v_freq = 90106,
+ .vsync_polarity = 1,
+ .hsync_polarity = 1,
+ .h_active = 2400,
+ .h_total = 2482,
+ .h_blank = 82,
+ .h_front = 20,
+ .h_sync = 30,
+ .h_back = 32,
+ .v_active = 1200,
+ .v_total = 1252,
+ .v_blank = 52,
+ .v_front = 17,
+ .v_sync = 5,
+ .v_back = 30,
+ .v_sync_ln = 1,
+ },
+};
+
+static struct hdmi_format_para *all_fmt_paras[] = {
+ &fmt_para_3840x2160p60_y420_16x9,
+ &fmt_para_3840x2160p60_16x9,
+ &fmt_para_3840x2160p50_y420_16x9,
+ &fmt_para_3840x2160p50_16x9,
+ &fmt_para_3840x2160p30_16x9,
+ &fmt_para_3840x2160p25_16x9,
+ &fmt_para_3840x2160p24_16x9,
+ &fmt_para_4096x2160p24_256x135,
+ &fmt_para_4096x2160p25_256x135,
+ &fmt_para_4096x2160p30_256x135,
+ &fmt_para_4096x2160p50_y420_256x135,
+ &fmt_para_4096x2160p50_256x135,
+ &fmt_para_4096x2160p60_y420_256x135,
+ &fmt_para_4096x2160p60_256x135,
+ &fmt_para_1920x1080p50_16x9,
+ &fmt_para_1920x1080p60_16x9,
+ &fmt_para_1920x1080p30_16x9,
+ &fmt_para_1920x1080p25_16x9,
+ &fmt_para_1920x1080p24_16x9,
+ &fmt_para_1920x1080p100_16x9,
+ &fmt_para_1920x1080p120_16x9,
+ &fmt_para_1920x1080i60_16x9,
+ &fmt_para_1920x1080i50_16x9,
+ &fmt_para_1920x1080i100_16x9,
+ &fmt_para_1920x1080i120_16x9,
+ &fmt_para_1280x720p60_16x9,
+ &fmt_para_1280x720p50_16x9,
+ &fmt_para_1280x720p100_16x9,
+ &fmt_para_1280x720p120_16x9,
+ &fmt_para_720x480p60_16x9,
+ &fmt_para_720x480p120_16x9,
+ &fmt_para_720x480p60_4x3,
+ &fmt_para_720x480i60_16x9,
+ &fmt_para_720x480i60_4x3,
+ &fmt_para_720x576p50_16x9,
+ &fmt_para_720x576p100_16x9,
+ &fmt_para_720x576p50_4x3,
+ &fmt_para_720x576i50_16x9,
+ &fmt_para_720x576i50_4x3,
+ &fmt_para_vesa_640x480p60_4x3,
+ &fmt_para_vesa_800x480p60_4x3,
+ &fmt_para_vesa_800x600p60_4x3,
+ &fmt_para_vesa_852x480p60_213x120,
+ &fmt_para_vesa_854x480p60_427x240,
+ &fmt_para_vesa_1024x600p60_17x10,
+ &fmt_para_vesa_1024x768p60_4x3,
+ &fmt_para_vesa_1152x864p75_4x3,
+ &fmt_para_vesa_1280x600p60_32x15,
+ &fmt_para_vesa_1280x768p60_5x3,
+ &fmt_para_vesa_1280x800p60_8x5,
+ &fmt_para_vesa_1280x960p60_4x3,
+ &fmt_para_vesa_1280x1024p60_5x4,
+ &fmt_para_vesa_1360x768p60_16x9,
+ &fmt_para_vesa_1366x768p60_16x9,
+ &fmt_para_vesa_1400x1050p60_4x3,
+ &fmt_para_vesa_1440x900p60_8x5,
+ &fmt_para_vesa_1440x2560p60_9x16,
+ &fmt_para_vesa_1440x2560p70_9x16,
+ &fmt_para_vesa_1600x900p60_16x9,
+ &fmt_para_vesa_1600x1200p60_4x3,
+ &fmt_para_vesa_1680x1050p60_8x5,
+ &fmt_para_vesa_1920x1200p60_8x5,
+ &fmt_para_vesa_2160x1200p90_9x5,
+ &fmt_para_vesa_2560x1080p60_64x27,
+ &fmt_para_vesa_2560x1440p60_16x9,
+ &fmt_para_vesa_2560x1600p60_8x5,
+ &fmt_para_vesa_3440x1440p60_43x18,
+ &fmt_para_vesa_2400x1200p90_2x1,
+ &fmt_para_non_hdmi_fmt,
+ NULL,
+};
+
+struct hdmi_format_para *hdmi_get_fmt_paras(enum hdmi_vic vic)
+{
+ int i;
+
+ for (i = 0; all_fmt_paras[i] != NULL; i++) {
+ if (vic == all_fmt_paras[i]->vic)
+ return all_fmt_paras[i];
+ }
+ return NULL;
+}
+
+static struct parse_cd parse_cd_[] = {
+ {HDMI_COLOR_DEPTH_24B, "8bit",},
+ {HDMI_COLOR_DEPTH_30B, "10bit"},
+ {HDMI_COLOR_DEPTH_36B, "12bit"},
+ {HDMI_COLOR_DEPTH_48B, "16bit"},
+};
+
+static struct parse_cs parse_cs_[] = {
+ {HDMI_COLOR_FORMAT_RGB, "rgb",},
+ {HDMI_COLOR_FORMAT_444, "444",},
+ {HDMI_COLOR_FORMAT_422, "422",},
+ {HDMI_COLOR_FORMAT_420, "420",},
+};
+
+static struct parse_cr parse_cr_[] = {
+ {HDMI_COLOR_RANGE_LIM, "limit",},
+ {HDMI_COLOR_RANGE_FUL, "full",},
+};
+
+/* parse the string from "hdmitx output FORMAT" */
+void hdmi_parse_attr(struct hdmi_format_para *para, char const *name)
+{
+ int i;
+
+ /* parse color depth */
+ for (i = 0; i < sizeof(parse_cd_) / sizeof(struct parse_cd); i++) {
+ if (strstr(name, parse_cd_[i].name)) {
+ para->cd = parse_cd_[i].cd;
+ break;
+ }
+ }
+ /* set default value */
+ if (i == sizeof(parse_cd_) / sizeof(struct parse_cd))
+ para->cd = HDMI_COLOR_DEPTH_24B;
+
+ /* parse color space */
+ for (i = 0; i < sizeof(parse_cs_) / sizeof(struct parse_cs); i++) {
+ if (strstr(name, parse_cs_[i].name)) {
+ para->cs = parse_cs_[i].cs;
+ break;
+ }
+ }
+ /* set default value */
+ if (i == sizeof(parse_cs_) / sizeof(struct parse_cs))
+ para->cs = HDMI_COLOR_FORMAT_444;
+
+ /* parse color range */
+ for (i = 0; i < sizeof(parse_cr_) / sizeof(struct parse_cr); i++) {
+ if (strstr(name, parse_cr_[i].name)) {
+ para->cr = parse_cr_[i].cr;
+ break;
+ }
+ }
+ /* set default value */
+ if (i == sizeof(parse_cr_) / sizeof(struct parse_cr))
+ para->cr = HDMI_COLOR_RANGE_FUL;
+}
+
+/*
+ * Paramter 'name' can be 1080p60hz, or 1920x1080p60hz
+ * or 3840x2160p60hz, 2160p60hz
+ * or 3840x2160p60hz420, 2160p60hz420 (Y420 mode)
+ */
+enum hdmi_vic hdmi_get_fmt_vic(char const *name)
+{
+ int i;
+ unsigned int name_len;
+ char *lname;
+ enum hdmi_vic vic = HDMI_unkown;
+ struct hdmi_format_para *para = NULL;
+
+ if (!name)
+ return HDMI_unkown;
+ for (i = 0; all_fmt_paras[i] != NULL; i++) {
+ lname = all_fmt_paras[i]->name;
+ if (lname && (strncmp(name, lname, strlen(lname)) == 0)) {
+ vic = all_fmt_paras[i]->vic;
+ break;
+ }
+ lname = all_fmt_paras[i]->sname;
+ if (lname && (strncmp(name, lname, strlen(lname)) == 0)) {
+ vic = all_fmt_paras[i]->vic;
+ break;
+ }
+ }
+ if ((vic != HDMI_unkown) && (all_fmt_paras[i] != NULL)) {
+ para = all_fmt_paras[i];
+ memset(¶->ext_name[0], 0, sizeof(para->ext_name));
+ name_len = strlen(name);
+ if (name_len > sizeof(para->ext_name) - 1)
+ name_len = sizeof(para->ext_name) - 1;
+ memcpy(¶->ext_name[0], name, name_len);
+ hdmi_parse_attr(para, name);
+ }
+ return vic;
+}
+
+struct hdmi_format_para *hdmi_match_dtd_paras(struct dtd *t)
+{
+ int i;
+
+ if (!t)
+ return NULL;
+ for (i = 0; all_fmt_paras[i]; i++) {
+ if ((abs(all_fmt_paras[i]->timing.pixel_freq / 10
+ - t->pixel_clock) <= (t->pixel_clock + 1000) / 1000) &&
+ (t->h_active == all_fmt_paras[i]->timing.h_active) &&
+ (t->h_blank == all_fmt_paras[i]->timing.h_blank) &&
+ (t->v_active == all_fmt_paras[i]->timing.v_active) &&
+ (t->v_blank == all_fmt_paras[i]->timing.v_blank) &&
+ (t->h_sync_offset == all_fmt_paras[i]->timing.h_front) &&
+ (t->h_sync == all_fmt_paras[i]->timing.h_sync) &&
+ (t->v_sync_offset == all_fmt_paras[i]->timing.v_front) &&
+ (t->v_sync == all_fmt_paras[i]->timing.v_sync)
+ )
+ return all_fmt_paras[i];
+ }
+
+ return NULL;
+}
+
+/* 1080i still uses encp, not enci */
+bool hdmimode_is_interlaced(enum hdmi_vic vic)
+{
+ switch (vic) {
+ case HDMI_720x480i60_4x3:
+ case HDMI_720x480i60_16x9:
+ case HDMI_2880x480i60_4x3:
+ case HDMI_2880x480i60_16x9:
+ case HDMI_720x576i50_4x3:
+ case HDMI_720x576i50_16x9:
+ case HDMI_2880x576i50_4x3:
+ case HDMI_2880x576i50_16x9:
+ case HDMI_720x576i100_4x3:
+ case HDMI_720x576i100_16x9:
+ case HDMI_720x480i120_4x3:
+ case HDMI_720x480i120_16x9:
+ case HDMI_720x576i200_4x3:
+ case HDMI_720x576i200_16x9:
+ case HDMI_720x480i240_4x3:
+ case HDMI_720x480i240_16x9:
+ return 1;
+ break;
+ default:
+ return 0;
+ break;
+ }
+}
+
+static struct hdmi_format_para tst_para;
+static inline void copy_para(struct hdmi_format_para *des,
+ struct hdmi_format_para *src)
+{
+ if (!des || !src)
+ return;
+ memcpy(des, src, sizeof(struct hdmi_format_para));
+}
+
+bool pre_process_str(char *name)
+{
+ int i;
+ unsigned int flag = 0;
+ char *color_format[4] = {"444", "422", "420", "rgb"};
+
+ for (i = 0 ; i < 4 ; i++) {
+ if (strstr(name, color_format[i]) != NULL)
+ flag++;
+ }
+ if (flag >= 2)
+ return false;
+ else
+ return true;
+}
+
+struct hdmi_format_para *hdmi_tst_fmt_name(char const *name, char const *attr)
+{
+ int i;
+ char *lname;
+ enum hdmi_vic vic = HDMI_unkown;
+ unsigned int copy_len;
+
+ copy_para(&tst_para, &fmt_para_non_hdmi_fmt);
+ if (!name)
+ return &tst_para;
+
+ for (i = 0; all_fmt_paras[i]; i++) {
+ lname = all_fmt_paras[i]->name;
+ if (lname && (strncmp(name, lname, strlen(lname)) == 0)) {
+ vic = all_fmt_paras[i]->vic;
+ break;
+ }
+ lname = all_fmt_paras[i]->sname;
+ if (lname && (strncmp(name, lname, strlen(lname)) == 0)) {
+ vic = all_fmt_paras[i]->vic;
+ break;
+ }
+ }
+ if ((vic != HDMI_unkown) && (i != sizeof(all_fmt_paras) /
+ sizeof(struct hdmi_format_para *))) {
+ copy_para(&tst_para, all_fmt_paras[i]);
+ memset(&tst_para.ext_name[0], 0, sizeof(tst_para.ext_name));
+ copy_len = strlen(name);
+ if (copy_len >= sizeof(tst_para.ext_name))
+ copy_len = sizeof(tst_para.ext_name) - 1;
+ memcpy(&tst_para.ext_name[0], name, copy_len);
+ hdmi_parse_attr(&tst_para, name);
+ hdmi_parse_attr(&tst_para, attr);
+ } else {
+ copy_para(&tst_para, &fmt_para_non_hdmi_fmt);
+ hdmi_parse_attr(&tst_para, name);
+ hdmi_parse_attr(&tst_para, attr);
+ }
+ if (strstr(name, "420"))
+ tst_para.cs = HDMI_COLOR_FORMAT_420;
+
+ /* only 2160p60/50hz smpte60/50hz have Y420 mode */
+ if (tst_para.cs == HDMI_COLOR_FORMAT_420) {
+ switch ((tst_para.vic) & 0xff) {
+ case HDMI_3840x2160p50_16x9:
+ case HDMI_3840x2160p60_16x9:
+ case HDMI_4096x2160p50_256x135:
+ case HDMI_4096x2160p60_256x135:
+ case HDMI_3840x2160p50_64x27:
+ case HDMI_3840x2160p60_64x27:
+ break;
+ default:
+ copy_para(&tst_para, &fmt_para_non_hdmi_fmt);
+ break;
+ }
+ }
+
+ return &tst_para;
+}
+
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmi_tx_compliance.c b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmi_tx_compliance.c
new file mode 100644
index 0000000..0bc43f5
--- /dev/null
+++ b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmi_tx_compliance.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <amlogic/media/vout/hdmitx/hdmitx.h>
+/* Base Block, Vendor/Product Information, byte[8]~[17] */
+struct edid_venddat_t {
+ unsigned char data[10];
+};
+
+static struct edid_venddat_t vendor_6g[] = {
+ /* SAMSUNG UA55KS7300JXXZ */
+ { {0x4c, 0x2d, 0x3b, 0x0d, 0x00, 0x06, 0x00, 0x01, 0x01, 0x1a} },
+ /* Add new vendor data here */
+};
+
+bool hdmitx_find_vendor(struct hdmitx_dev *hdev)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(vendor_6g); i++) {
+ if (memcmp(&hdev->rawedid[8], vendor_6g[i].data,
+ sizeof(vendor_6g[i].data)) == 0)
+ return true;
+ }
+ return false;
+}
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_drv.c b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_drv.c
new file mode 100644
index 0000000..6586013
--- /dev/null
+++ b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_drv.c
@@ -0,0 +1,3287 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/io.h>
+#include <amlogic/media/vout/aml_vout.h>
+#include <amlogic/media/vout/hdmitx/hdmitx.h>
+#include <amlogic/auge_sound.h>
+#include "hdmitx_drv.h"
+
+#ifdef CONFIG_VENDOR_NAME
+const static char *vend_name = CONFIG_VENDOR_NAME; /* Max 8 bytes */
+#else
+const static char *vend_name = "Amlogic"; /* Max 8 bytes */
+#endif
+
+#ifdef CONFIG_PRODUCT_NAME
+const static char *prod_desc = CONFIG_PRODUCT_NAME; /* Max 16 bytes */
+#else
+const static char *prod_desc = "MBox Meson Ref"; /* Max 16 bytes */
+#endif
+
+static struct hdmitx_dev hdmitx_device;
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct hdmitx_dev *hdmitx_get_hdev(void)
+{
+ return &hdmitx_device;
+}
+
+static void hdmi_tvenc_set(enum hdmi_vic vic);
+extern void _udelay(unsigned int us);
+static void set_tmds_clk_div40(unsigned int div40);
+
+#define HSYNC_POLARITY 1 /*HSYNC polarity: active high*/
+#define VSYNC_POLARITY 1 /*VSYNC polarity: active high*/
+
+/*Pixel format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420.*/
+#define TX_INPUT_COLOR_FORMAT HDMI_COLOR_FORMAT_444
+/*Pixel range: 0=limited; 1=full.*/
+#define TX_INPUT_COLOR_RANGE HDMI_COLOR_RANGE_LIM
+/*Pixel range: 0=limited; 1=full.*/
+#define TX_OUTPUT_COLOR_RANGE HDMI_COLOR_RANGE_LIM
+
+static void hdelay(int us)
+{
+ _udelay(us * 1000);
+}
+
+#define mdelay(i) hdelay(i)
+#define msleep(i) hdelay(i)
+
+static void hdmitx_set_hw(struct hdmitx_dev *hdev);
+static int hdmitx_set_audmode(struct hdmitx_dev *hdev);
+
+/*Internal functions:*/
+static void hdmitx_csc_config (unsigned char input_color_format,
+ unsigned char output_color_format,
+ unsigned char color_depth);
+
+static void dump_regs(void)
+{
+ unsigned int reg_adr;
+ unsigned int reg_val;
+ unsigned int ladr;
+
+ for (reg_adr = 0x0000; reg_adr < 0x0100; reg_adr++) {
+ ladr = PERIPHS_REG_ADDR(0x0) + (reg_adr << 2);
+ reg_val = hd_read_reg(ladr);
+ printk("[0x%08x] = 0x%X\n", hd_get_paddr(ladr), reg_val);
+ }
+ for (reg_adr = 0x0000; reg_adr < 0x0100; reg_adr++) {
+ ladr = HHI_REG_ADDR(0x0) + (reg_adr << 2);
+ reg_val = hd_read_reg(ladr);
+ printk("[0x%08x] = 0x%X\n", hd_get_paddr(ladr), reg_val);
+ }
+ for (reg_adr = 0x0000; reg_adr < 0x0100; reg_adr++) {
+ ladr = ANACTRL_REG_ADDR(0x0) + (reg_adr << 2);
+ reg_val = hd_read_reg(ladr);
+ printk("[0x%08x] = 0x%X\n", hd_get_paddr(ladr), reg_val);
+ }
+#define VPU_REG_ADDR(reg) ((VCBUS_REG_IDX << BASE_REG_OFFSET) + (reg << 2))
+ for (reg_adr = 0x1b00; reg_adr < 0x1c00; reg_adr++) {
+ ladr = VPU_REG_ADDR(reg_adr);
+ reg_val = hd_read_reg(ladr);
+ printk("[0x%08x] = 0x%X\n", hd_get_paddr(ladr), reg_val);
+ }
+ for (reg_adr = 0x1c01; reg_adr < 0x1d00; reg_adr++) {
+ ladr = VPU_REG_ADDR(reg_adr);
+ reg_val = hd_read_reg(ladr);
+ printk("[0x%08x] = 0x%X\n", hd_get_paddr(ladr), reg_val);
+ }
+ for (reg_adr = 0x2700; reg_adr < 0x2780; reg_adr++) {
+ ladr = VPU_REG_ADDR(reg_adr);
+ reg_val = hd_read_reg(ladr);
+ printk("[0x%08x] = 0x%X\n", hd_get_paddr(ladr), reg_val);
+ }
+ for (reg_adr = HDMITX_TOP_SW_RESET; reg_adr < HDMITX_TOP_DONT_TOUCH1 + 1; reg_adr++) {
+ reg_val = hdmitx_rd_reg(reg_adr);
+ printk("TOP[0x%x]: 0x%x\n", reg_adr, reg_val);
+ }
+ for (reg_adr = HDMITX_DWC_DESIGN_ID; reg_adr < HDMITX_DWC_I2CM_SCDC_UPDATE1 + 1; reg_adr++) {
+ if ((reg_adr > (DWC_OFFSET_MASK + 0x5016)) && (reg_adr < (DWC_OFFSET_MASK + 0x7800)))
+ reg_val = 0;//hdmitx_rd_reg(reg_adr);
+ else
+ reg_val = hdmitx_rd_reg(reg_adr);
+ if (reg_val)
+ printk("hdmitx: [0x%x]: 0x%x\n", reg_adr, reg_val);
+ }
+}
+
+static void hdmitx_hw_init(void)
+{
+ static int hw_init_flag;
+
+ if (hw_init_flag)
+ return;
+ else
+ hw_init_flag = 1;
+
+ /* Enable clocks and bring out of reset */
+
+ /* Enable hdmitx_sys_clk */
+ /* .clk0 ( cts_oscin_clk ), */
+ /* .clk1 ( fclk_div4 ), */
+ /* .clk2 ( fclk_div3 ), */
+ /* .clk3 ( fclk_div5 ), */
+ hd_set_reg_bits(P_CLKCTRL_HDMI_CLK_CTRL, 0x0100, 0, 16);
+
+ /* Enable clk81_hdmitx_pclk */
+ hd_set_reg_bits(P_CLKCTRL_SYS_CLK_EN0_REG2, 1, 4, 1);
+
+ /* wire wr_enable = control[3]; */
+ /* wire fifo_enable = control[2]; */
+ /* assign phy_clk_en = control[1]; */
+ /* Enable tmds_clk */
+ /* Bring HDMITX MEM output of power down */
+ hd_set_reg_bits(P_PWRCTRL_MEM_PD11, 0, 8, 8);
+ /* reset HDMITX APB & TX & PHY */
+
+ /* Refer to SC2-system-Registers.docx */
+ hd_write_reg(P_RESETCTRL_RESET0, 1 << 29); /* hdmi_tx */
+ hd_write_reg(P_RESETCTRL_RESET0, 1 << 22); /* hdmitxphy */
+ hd_write_reg(P_RESETCTRL_RESET0, 1 << 19); /* vid_pll_div */
+ hd_write_reg(P_RESETCTRL_RESET0, 1 << 16); /* hdmitx_apb */
+
+ /* Bring out of reset */
+ hdmitx_wr_reg(HDMITX_TOP_SW_RESET, 0);
+ _udelay(200);
+ /* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */
+ hdmitx_wr_reg(HDMITX_TOP_CLK_CNTL, 0x000000ff);
+
+ hdmitx_wr_reg(HDMITX_DWC_MC_LOCKONCLOCK, 0xff);
+
+ hdmitx_wr_reg(HDMITX_DWC_MC_CLKDIS, 0x00);
+ /*disable null package*/
+ hdmitx_wr_reg(HDMITX_TOP_DISABLE_NULL, 0x7);
+}
+
+/*
+ * Note: read 8 Bytes of EDID data every time
+ */
+static int read_edid_8bytes(unsigned char *rx_edid, unsigned char addr,
+ unsigned char blk_no)
+{
+ unsigned int timeout = 0;
+ unsigned int i = 0;
+ /*Program SLAVE/SEGMENT/ADDR*/
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, 0x50);
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_SEGADDR, 0x30);
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_SEGPTR, 1);
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, addr);
+ if (blk_no < 2)
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1 << 2);
+ else
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1 << 3);
+ timeout = 0;
+ while ((!(hdmitx_rd_reg(HDMITX_DWC_IH_I2CM_STAT0) & (1 << 1))) && (timeout < 5)) {
+ mdelay(1);
+ timeout ++;
+ }
+ if (timeout == 5) {
+ printk("ddc timeout\n");
+ return 0;
+ }
+ /* add extra delay time for reading segment block */
+ if (blk_no >= 2)
+ mdelay(1);
+ hdmitx_wr_reg(HDMITX_DWC_IH_I2CM_STAT0, 1 << 1); /*clear INT*/
+ /*Read back 8 bytes*/
+ for (i = 0; i < 8; i ++) {
+ rx_edid[i] = hdmitx_rd_reg(HDMITX_DWC_I2CM_READ_BUFF0 + i);
+ }
+ return 1;
+}
+
+static void ddc_init_(void)
+{
+ static int ddc_init_flag;
+ unsigned int data32 = 0;
+
+ hdmitx_hw_init();
+ if (ddc_init_flag)
+ return;
+ else
+ ddc_init_flag = 1;
+
+ hdmitx_ddc_init();
+
+ data32 = 0;
+ data32 |= (0 << 6); /*[ 6] read_req_mask*/
+ data32 |= (0 << 2); /*[ 2] done_mask*/
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_INT, data32);
+
+ data32 = 0;
+ data32 |= (0 << 6); /*[ 6] nack_mask*/
+ data32 |= (0 << 2); /*[ 2] arbitration_error_mask*/
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_CTLINT, data32);
+
+ data32 = 0;
+ data32 |= (0 << 3); /*[ 3] i2c_fast_mode: 0=standard mode; 1=fast mode.*/
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_DIV, data32);
+
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_HCNT_1, 0);
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_HCNT_0, 0xcf);
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_LCNT_1, 0);
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_LCNT_0, 0xff);
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_HCNT_1, 0);
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_HCNT_0, 0x0f);
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_LCNT_1, 0);
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_LCNT_0, 0x20);
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_SDA_HOLD, 0x08);
+
+ data32 = 0;
+ data32 |= (0 << 5); /*[ 5] updt_rd_vsyncpoll_en*/
+ data32 |= (0 << 4); /*[ 4] read_request_en scdc*/
+ data32 |= (0 << 0); /*[ 0] read_update*/
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_SCDC_UPDATE, data32);
+}
+
+static int hdmitx_read_edid(unsigned char *buf, unsigned char addr,
+ unsigned char blk_no)
+{
+ ddc_init_();
+ return read_edid_8bytes(buf, (addr + blk_no * 128) & 0xff, blk_no);
+}
+
+static void scdc_rd_sink(unsigned char adr, unsigned char *val)
+{
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, 0x54);
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, adr);
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1);
+ _udelay(2000);
+ *val = (unsigned char)hdmitx_rd_reg(HDMITX_DWC_I2CM_DATAI);
+}
+
+static void scdc_wr_sink(unsigned char adr, unsigned char val)
+{
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, 0x54);
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, adr);
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_DATAO, val);
+ hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 0x10);
+ _udelay(2000);
+}
+
+static void scdc_prepare(unsigned int div)
+{
+ unsigned char rx_ver = 0;
+
+ scdc_rd_sink(SINK_VER, &rx_ver);
+ if (rx_ver != 1)
+ scdc_rd_sink(SINK_VER, &rx_ver); /* Recheck */
+ if (0)
+ printf("rx version is %s div=%d\n",
+ (rx_ver == 1) ? "2.0" : "1.4 or below",
+ div ? 40 : 10);
+
+ scdc_wr_sink(SOURCE_VER, 0x1);
+ scdc_wr_sink(SOURCE_VER, 0x1);
+ scdc_wr_sink(TMDS_CFG, div ? 0x3 : 0); /* TMDS 1/40 & Scramble */
+ scdc_wr_sink(TMDS_CFG, div ? 0x3 : 0); /* TMDS 1/40 & Scramble */
+}
+
+static struct hdmi_support_mode gxbb_modes[] = {
+ {HDMI_3840x2160p60_16x9, "2160p60hz", 0},
+ {HDMI_3840x2160p50_16x9, "2160p50hz", 0},
+ {HDMI_3840x2160p30_16x9, "2160p30hz", 0},
+ {HDMI_3840x2160p25_16x9, "2160p25hz", 0},
+ {HDMI_3840x2160p24_16x9, "2160p24hz", 0},
+ {HDMI_4096x2160p60_256x135, "smpte60hz", 0},
+ {HDMI_4096x2160p50_256x135, "smpte50hz", 0},
+ {HDMI_4096x2160p30_256x135, "smpte30hz", 0},
+ {HDMI_4096x2160p25_256x135, "smpte25hz", 0},
+ {HDMI_4096x2160p24_256x135, "smpte24hz", 0},
+ {HDMI_3840x2160p60_16x9, "2160p60hz420", 1},
+ {HDMI_3840x2160p50_16x9, "2160p50hz420", 1},
+ {HDMI_4096x2160p50_256x135, "smpte50hz420", 1},
+ {HDMI_4096x2160p60_256x135, "smpte60hz420", 1},
+ {HDMI_1920x1080p120_16x9, "1080p120hz", 0},
+ {HDMI_1920x1080p60_16x9, "1080p60hz", 0},
+ {HDMI_1920x1080p50_16x9, "1080p50hz", 0},
+ {HDMI_1920x1080p30_16x9, "1080p30hz", 0},
+ {HDMI_1920x1080p25_16x9, "1080p25hz", 0},
+ {HDMI_1920x1080p24_16x9, "1080p24hz", 0},
+ {HDMI_1920x1080i60_16x9, "1080i60hz", 0},
+ {HDMI_1920x1080i50_16x9, "1080i50hz", 0},
+ {HDMI_1280x720p60_16x9, "720p60hz", 0},
+ {HDMI_1280x720p50_16x9, "720p50hz", 0},
+ {HDMI_720x576p50_16x9, "576p50hz", 0},
+ {HDMI_720x480p60_16x9, "480p60hz", 0},
+ {HDMI_720x576i50_16x9, "576i50hz", 0},
+ {HDMI_720x480i60_16x9, "480i60hz", 0},
+ {HDMI_720x576p50_4x3, "576p50hz_4x3", 0},
+ {HDMI_720x480p60_4x3, "480p60hz_4x3", 0},
+ {HDMI_720x576i50_4x3, "576i50hz_4x3", 0},
+ {HDMI_720x480i60_4x3, "480i60hz_4x3", 0},
+ {HDMIV_1440x2560p60hz, "1440x2560p60hz", 0},
+ {HDMIV_3440x1440p60hz, "3440x1440p60hz", 0},
+ {HDMIV_2400x1200p90hz, "2400x1200p90hz", 0},
+ {HDMIV_1280x1024p60hz, "1280x1024p60hz", 0},
+ {HDMIV_1680x1050p60hz, "1680x1050p60hz", 0},
+ {HDMIV_1024x600p60hz, "1024x600p60hz", 0},
+};
+
+static void hdmitx_list_support_modes(void)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++)
+ printf("%s\n", gxbb_modes[i].sname);
+}
+
+ void hdmitx_test_bist(unsigned int mode)
+{
+ switch (mode) {
+ case 1:
+ case 2:
+ case 3:
+ hd_set_reg_bits(P_ENCP_VIDEO_MODE_ADV, 0, 3, 1);
+ hd_write_reg(P_VENC_VIDEO_TST_EN, 1);
+ hd_write_reg(P_VENC_VIDEO_TST_MDSEL, mode);
+ break;
+ case 0:
+ default:
+ hd_set_reg_bits(P_ENCP_VIDEO_MODE_ADV, 1, 3, 1);
+ hd_write_reg(P_VENC_VIDEO_TST_EN, 0);
+ break;
+ }
+}
+
+static void hdmitx_output_blank(unsigned int blank)
+{
+ if (blank == 1)
+ hd_write_reg(P_VPU_HDMI_DATA_OVR,
+ ((1 << 31) | (1 << 29) | (1 << 9)));
+ if (blank == 0)
+ hd_write_reg(P_VPU_HDMI_DATA_OVR, 0);
+}
+
+void hdmitx_set_div40(bool div40)
+{
+ set_tmds_clk_div40(div40);
+}
+
+static void hdmitx_load_dts_config(struct hdmitx_dev *hdev)
+{
+ const void *dt_blob;
+ int node;
+ char *propdata;
+ int ret;
+
+ hdev->limit_res_1080p = 0;
+ dt_blob = gd->fdt_blob;
+ if (dt_blob == NULL) {
+ printf("ERR: hdmitx: dt_blob is null\n");
+ return;
+ }
+
+ ret = fdt_check_header(dt_blob);
+ if (ret < 0) {
+ printf("ERR: hdmitx: check dts: %s\n", fdt_strerror(ret));
+ return;
+ }
+
+ node = fdt_path_offset(dt_blob, "/amhdmitx");
+ if (node < 0) {
+ printf("ERR: hdmitx: not find /amhdmitx node: %s\n", fdt_strerror(node));
+ return;
+ }
+
+ propdata = (char *)fdt_getprop(dt_blob, node, "res_1080p", NULL);
+ if (propdata) {
+ if (!strcmp(propdata, "0"))
+ hdev->limit_res_1080p = 0;
+ else
+ hdev->limit_res_1080p = 1;
+ } else {
+ hdev->limit_res_1080p = 0;
+ }
+ printf("limit_res_1080p: %d\n", hdev->limit_res_1080p);
+}
+
+void hdmitx_init(void)
+{
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
+ char *dongle_mode = NULL;
+
+ dongle_mode = env_get("dongle_mode");
+ if (dongle_mode && (dongle_mode[0] == '1'))
+ hdev->dongle_mode = 1;
+ hdev->hwop.get_hpd_state = hdmitx_get_hpd_state;
+ hdev->hwop.read_edid = hdmitx_read_edid;
+ hdev->hwop.turn_off = hdmitx_turnoff;
+ hdev->hwop.list_support_modes = hdmitx_list_support_modes;
+ hdev->hwop.dump_regs = dump_regs;
+ hdev->hwop.test_bist = hdmitx_test_bist;
+ hdev->hwop.test_prbs = hdmitx_test_prbs;
+ hdev->hwop.set_div40 = hdmitx_set_div40;
+ hdev->hwop.output_blank = hdmitx_output_blank;
+ hdmitx_load_dts_config(hdev);
+}
+
+void hdmi_tx_set(struct hdmitx_dev *hdev)
+{
+ unsigned char checksum[11];
+ char *p_tmp;
+ aml_audio_init(); /* Init audio hw firstly */
+ hdmitx_hw_init();
+ ddc_init_();
+ hdmitx_set_hw(hdev);
+ /* add audio */
+ hdmitx_set_audmode(hdev);
+ //kernel will determine output mode on its own
+ p_tmp = env_get("outputmode");
+ if (NULL != p_tmp)
+ env_set("hdmimode", p_tmp);
+
+ /* null char needed to terminate the string
+ otherwise garbage in checksum logopara */
+ memcpy(checksum, hdev->RXCap.checksum, 10);
+ checksum[10] = '\0';
+ env_set("hdmichecksum", (const char*)checksum);
+ printf("hdmi_tx_set: save mode: %s, attr: %s, hdmichecksum: %s\n",
+ env_get("outputmode"), env_get("colorattribute"), env_get("hdmichecksum"));
+ run_command("saveenv", 0);
+ return;
+
+#if 0
+ hdmi_tx_gate(vic);
+ hdmi_tx_clk(vic);
+ hdmi_tx_misc(vic);
+ hdmi_tx_enc(vic);
+ hdmi_tx_set_vend_spec_infofram(vic);
+ hdmi_tx_phy(vic);
+#endif
+}
+
+/***********************************************
+ * parameters: mode, such as 720p60hz, 1080p50hz...
+ * frac, 1=59.94/29.97hz.
+ * return: viu_mux
+ ************************************************/
+unsigned int hdmi_outputmode_check(char *mode, unsigned int frac)
+{
+ int i, ret = 0xff;
+
+ for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) {
+ if (!strcmp(mode, gxbb_modes[i].sname)) {
+ ret = 0;
+ break;
+ }
+ }
+
+ if (ret) {
+ //printf("hdmitx: outputmode[%s] is invalid\n", mode);
+ return VIU_MUX_MAX;
+ }
+
+ if (frac) {
+ if (hdmitx_likely_frac_rate_mode(mode) == 0) {
+ printf("hdmitx: outputmode[%s] don't support frac\n", mode);
+ return VIU_MUX_MAX;
+ }
+ }
+
+ if ((!strcmp(mode, "480i60hz")) || (!strcmp(mode, "576i50hz")))
+ ret = VIU_MUX_ENCI;
+ else
+ ret = VIU_MUX_ENCP;
+ return ret;
+}
+
+static int hdmitx_set_audmode(struct hdmitx_dev *hdev)
+{
+ int i;
+ unsigned int data32;
+ unsigned int aud_n_para;
+
+ pr_info("hdmtix: set audio\n");
+ hdmitx_set_reg_bits(HDMITX_TOP_CLK_CNTL, 3, 2, 2);
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_PACKET_TX_EN, 1, 0, 1);
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_PACKET_TX_EN, 1, 3, 1);
+#if 0 /* TODO */
+ /* Disable HDMI audio clock input and its I2S input */
+ hd_write_reg(P_AIU_HDMI_CLK_DATA_CTRL, 0);
+
+ /* Enable HDMI I2S input from the selected source */
+ hd_write_reg(P_AIU_HDMI_CLK_DATA_CTRL, 0x22);
+#endif
+ /* I2S Sampler config */
+ data32 = 0;
+/* [ 3] fifo_empty_mask: 0=enable int; 1=mask int. */
+ data32 |= (1 << 3);
+/* [ 2] fifo_full_mask: 0=enable int; 1=mask int. */
+ data32 |= (1 << 2);
+ hdmitx_wr_reg(HDMITX_DWC_AUD_INT, data32);
+
+ data32 = 0;
+/* [ 4] fifo_overrun_mask: 0=enable int; 1=mask int.
+ * Enable it later when audio starts. */
+ data32 |= (1 << 4);
+ hdmitx_wr_reg(HDMITX_DWC_AUD_INT1, data32);
+/* [ 5] 0=select SPDIF; 1=select I2S. */
+ data32 = 0;
+ data32 |= (0 << 7); /* [ 7] sw_audio_fifo_rst */
+ data32 |= (0 << 5);
+ data32 |= (0 << 0); /* [3:0] i2s_in_en: enable it later in test.c */
+/* if enable it now, fifo_overrun will happen, because packet don't get sent
+ * out until initial DE detected. */
+ hdmitx_wr_reg(HDMITX_DWC_AUD_CONF0, data32);
+
+ data32 = 0;
+ data32 |= (0 << 5); /* [7:5] i2s_mode: 0=standard I2S mode */
+ data32 |= (24 << 0); /* [4:0] i2s_width */
+ hdmitx_wr_reg(HDMITX_DWC_AUD_CONF1, data32);
+
+ data32 = 0;
+ data32 |= (0 << 1); /* [ 1] NLPCM */
+ data32 |= (0 << 0); /* [ 0] HBR */
+ hdmitx_wr_reg(HDMITX_DWC_AUD_CONF2, data32);
+
+ /* spdif sampler config */
+ /* [ 2] SPDIF fifo_full_mask: 0=enable int; 1=mask int. */
+ /* [ 3] SPDIF fifo_empty_mask: 0=enable int; 1=mask int. */
+ data32 = 0;
+ data32 |= (1 << 3);
+ data32 |= (1 << 2);
+ hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIFINT, data32);
+ /* [ 4] SPDIF fifo_overrun_mask: 0=enable int; 1=mask int. */
+ data32 = 0;
+ data32 |= (0 << 4);
+ hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIFINT1, data32);
+
+ data32 = 0;
+ data32 |= (0 << 7); /* [ 7] sw_audio_fifo_rst */
+ hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIF0, data32);
+
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AUDICONF0, 0, 0, 4); /* CT */
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AUDICONF0, 1, 4, 3); /* CC */
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AUDICONF1, 0, 0, 3); /* SF */
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AUDICONF1, 0, 4, 2); /* SS */
+ hdmitx_wr_reg(HDMITX_DWC_FC_AUDICONF2, 0x00);
+ hdmitx_wr_reg(HDMITX_DWC_FC_AUDICONF3, 0);
+
+ /* audio packetizer config */
+ hdmitx_wr_reg(HDMITX_DWC_AUD_INPUTCLKFS, 0);
+
+ /* 48kHz 2ch PCM as default */
+ aud_n_para = 6144;
+ switch (hdev->vic) {
+ case HDMI_3840x2160p24_16x9:
+ case HDMI_3840x2160p25_16x9:
+ case HDMI_3840x2160p30_16x9:
+ case HDMI_4096x2160p24_256x135:
+ case HDMI_4096x2160p25_256x135:
+ case HDMI_4096x2160p30_256x135:
+ aud_n_para = 5120;
+ break;
+ case HDMI_3840x2160p50_16x9:
+ case HDMI_3840x2160p60_16x9:
+ case HDMI_3840x2160p50_64x27:
+ case HDMI_3840x2160p60_64x27:
+ if (hdev->para->cs == HDMI_COLOR_FORMAT_420)
+ aud_n_para = 5120;
+ break;
+ default:
+ break;
+ }
+
+ /* ACR packet configuration */
+ data32 = 0;
+ data32 |= (1 << 7); /* [ 7] ncts_atomic_write */
+ data32 |= (0 << 0); /* [3:0] AudN[19:16] */
+ hdmitx_wr_reg(HDMITX_DWC_AUD_N3, data32);
+
+ data32 = 0;
+ data32 |= (0 << 7); /* [7:5] N_shift */
+ data32 |= (0 << 4); /* [ 4] CTS_manual */
+ data32 |= (0 << 0); /* [3:0] manual AudCTS[19:16] */
+ hdmitx_wr_reg(HDMITX_DWC_AUD_CTS3, data32);
+
+ hdmitx_wr_reg(HDMITX_DWC_AUD_CTS2, 0); /* manual AudCTS[15:8] */
+ hdmitx_wr_reg(HDMITX_DWC_AUD_CTS1, 0); /* manual AudCTS[7:0] */
+
+ data32 = 0;
+ data32 |= (1 << 7); /* [ 7] ncts_atomic_write */
+ data32 |= (((aud_n_para>>16)&0xf) << 0); /* [3:0] AudN[19:16] */
+ hdmitx_wr_reg(HDMITX_DWC_AUD_N3, data32);
+ hdmitx_wr_reg(HDMITX_DWC_AUD_N2, (aud_n_para>>8)&0xff); /* AudN[15:8] */
+ hdmitx_wr_reg(HDMITX_DWC_AUD_N1, aud_n_para&0xff); /* AudN[7:0] */
+ for (i = 0; i < 9; i++)
+ hdmitx_wr_reg(HDMITX_DWC_FC_AUDSCHNLS0+i, 0x00);
+ hdmitx_wr_reg(HDMITX_DWC_FC_AUDSV, 0x11);
+ hdmitx_wr_reg(HDMITX_DWC_FC_AUDSCHNLS7, 0x02);
+ hdmitx_wr_reg(HDMITX_DWC_FC_AUDSCHNLS8, 0xd2);
+ hdmitx_wr_reg(HDMITX_DWC_FC_AUDSCHNLS3, 0x00);
+ hdmitx_wr_reg(HDMITX_DWC_FC_AUDSCHNLS5, 0x00);
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AUDSCHNLS7,
+ 0x2, 0, 4); /*CSB 27:24*/
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AUDSCHNLS7, 0x0, 6, 2); /*CSB 31:30*/
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AUDSCHNLS7, 0x0, 4, 2); /*CSB 29:28*/
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AUDSCHNLS8, 0x2, 0, 4); /*CSB 35:32*/
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AUDSCHNLS8, /* CSB 39:36 */
+ 0xd, 4, 4);
+
+ hdmitx_set_reg_bits(HDMITX_DWC_AUD_CONF0, 0, 5, 1);
+ /* reset audio fifo */
+ hdmitx_set_reg_bits(HDMITX_DWC_AUD_CONF0, 1, 7, 1);
+ hdmitx_set_reg_bits(HDMITX_DWC_AUD_CONF0, 0, 7, 1);
+ hdmitx_set_reg_bits(HDMITX_DWC_AUD_SPDIF0, 1, 7, 1);
+ hdmitx_set_reg_bits(HDMITX_DWC_AUD_SPDIF0, 0, 7, 1);
+ hdmitx_wr_reg(HDMITX_DWC_MC_SWRSTZREQ, 0xe7);
+ /* need reset again */
+ hdmitx_set_reg_bits(HDMITX_DWC_AUD_SPDIF0, 1, 7, 1);
+ hdmitx_set_reg_bits(HDMITX_DWC_AUD_SPDIF0, 0, 7, 1);
+ hdmitx_wr_reg(HDMITX_DWC_AUD_N1, hdmitx_rd_reg(HDMITX_DWC_AUD_N1));
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO3, 1, 0, 1);
+ return 0;
+}
+
+/*
+ * set Source Product Description InfoFrame
+ */
+static void hdmitx_set_spdinfo(void)
+{
+ int i;
+
+ if (!(vend_name && prod_desc))
+ return;
+
+ for (i = 0; (i < 8) && vend_name[i]; i++)
+ hdmitx_wr_reg(HDMITX_DWC_FC_SPDVENDORNAME0 + i, vend_name[i]);
+ for (i = 0; (i < 16) && prod_desc[i]; i++)
+ hdmitx_wr_reg(HDMITX_DWC_FC_SDPPRODUCTNAME0 + i, prod_desc[i]);
+ hdmitx_wr_reg(HDMITX_DWC_FC_SPDDEVICEINF, 0x1);
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO0, 1, 4, 1);
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO2, 1, 4, 4);
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_PACKET_TX_EN, 1, 4, 1);
+}
+
+#define NUM_INT_VSYNC INT_VEC_VIU1_VSYNC
+
+static unsigned long modulo(unsigned long a, unsigned long b);
+static signed int to_signed(unsigned int a);
+
+/*Pixel bit width: 4=24-bit; 5=30-bit; 6=36-bit; 7=48-bit.
+ *Pixel format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420.
+ *Pixel range: 0=limited; 1=full.
+ *Pixel format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420.
+ *Pixel range: 0=limited; 1=full.
+ *0:TMDS_CLK_rate=TMDS_Character_rate; 1:TMDS_CLK_rate=TMDS_Character_rate/4,
+ *for TMDS_Character_rate>340Mcsc.
+ */
+static void config_hdmi20_tx (struct hdmitx_dev* hdev, enum hdmi_vic vic,
+ struct hdmi_format_para *para,
+ unsigned char color_depth, unsigned char input_color_format,
+ unsigned char input_color_range, unsigned char output_color_format,
+ unsigned char output_color_range)
+{
+ struct hdmi_cea_timing *t = ¶->timing;
+ unsigned long data32;
+ unsigned char vid_map;
+ unsigned char csc_en;
+ unsigned char default_phase = 0;
+ unsigned char tmp = 0;
+
+#define GET_TIMING(name) (t->name)
+
+ hdmitx_hw_init();
+ data32 = 0;
+ data32 |= (1 << 12);
+ data32 |= (0 << 8);
+ data32 |= (0 << 0);
+ hdmitx_wr_reg(HDMITX_TOP_BIST_CNTL, data32);
+
+ /* Configure video */
+
+ /*Configure video sampler*/
+ vid_map = ( input_color_format == HDMI_COLOR_FORMAT_RGB )? ((color_depth == HDMI_COLOR_DEPTH_24B)? 0x01 :
+ (color_depth == HDMI_COLOR_DEPTH_30B)? 0x03 :
+ (color_depth == HDMI_COLOR_DEPTH_36B)? 0x05 :
+ 0x07) :
+ ((input_color_format == HDMI_COLOR_FORMAT_444) ||
+ (input_color_format == HDMI_COLOR_FORMAT_420))? ((color_depth == HDMI_COLOR_DEPTH_24B)? 0x09 :
+ (color_depth == HDMI_COLOR_DEPTH_30B)? 0x0b :
+ (color_depth == HDMI_COLOR_DEPTH_36B)? 0x0d :
+ 0x0f) :
+ ((color_depth == HDMI_COLOR_DEPTH_24B)? 0x16 :
+ (color_depth == HDMI_COLOR_DEPTH_30B)? 0x14 :
+ 0x12);
+
+ data32 = 0;
+ data32 |= (0 << 7);
+ data32 |= (vid_map << 0);
+ hdmitx_wr_reg(HDMITX_DWC_TX_INVID0, data32);
+
+ data32 = 0;
+ data32 |= (0 << 2);
+ data32 |= (0 << 1);
+ data32 |= (0 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_TX_INSTUFFING, data32);
+ hdmitx_wr_reg(HDMITX_DWC_TX_GYDATA0, 0x00);
+ hdmitx_wr_reg(HDMITX_DWC_TX_GYDATA1, 0x00);
+ hdmitx_wr_reg(HDMITX_DWC_TX_RCRDATA0, 0x00);
+ hdmitx_wr_reg(HDMITX_DWC_TX_RCRDATA1, 0x00);
+ hdmitx_wr_reg(HDMITX_DWC_TX_BCBDATA0, 0x00);
+ hdmitx_wr_reg(HDMITX_DWC_TX_BCBDATA1, 0x00);
+
+ /* Configure Color Space Converter */
+
+ csc_en = (input_color_format != output_color_format) ? 1 : 0;
+
+ data32 = 0;
+ data32 |= (csc_en << 0);
+ hdmitx_wr_reg(HDMITX_DWC_MC_FLOWCTRL, data32);
+
+ data32 = 0;
+ data32 |= ((((input_color_format ==HDMI_COLOR_FORMAT_422) &&
+ (output_color_format!=HDMI_COLOR_FORMAT_422))? 2 : 0 ) << 4); /*[5:4] intmode*/
+ data32 |= ((((input_color_format !=HDMI_COLOR_FORMAT_422) &&
+ (output_color_format==HDMI_COLOR_FORMAT_422))? 2 : 0 ) << 0); /*[1:0] decmode*/
+ hdmitx_wr_reg(HDMITX_DWC_CSC_CFG, data32);
+
+ hdmitx_csc_config(input_color_format, output_color_format, color_depth);
+
+ /* Configure video packetizer */
+
+ /* Video Packet color depth and pixel repetition */
+ data32 = 0;
+ data32 |= (((output_color_format==HDMI_COLOR_FORMAT_422)?
+ HDMI_COLOR_DEPTH_24B : color_depth) << 4); /*[7:4] color_depth*/
+ data32 |= (0 << 0);
+ if ((data32 & 0xf0) == 0x40 )
+ data32 &= ~(0xf << 4);
+ hdmitx_wr_reg(HDMITX_DWC_VP_PR_CD, data32);
+ if (output_color_format == HDMI_COLOR_FORMAT_422) {
+ switch (color_depth) {
+ case HDMI_COLOR_DEPTH_24B:
+ tmp = 4;
+ break;
+ default:
+ tmp = 0;
+ break;
+ }
+ hdmitx_set_reg_bits(HDMITX_DWC_VP_PR_CD, tmp, 4, 4);
+ }
+
+ /* Video Packet Stuffing */
+ data32 = 0;
+ data32 |= (default_phase << 5);
+ data32 |= (0 << 2);
+ data32 |= (0 << 1);
+ data32 |= (0 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_VP_STUFF, data32);
+
+ /* Video Packet YCC color remapping */
+ data32 = 0;
+ hdmitx_wr_reg(HDMITX_DWC_VP_REMAP, data32);
+ if (output_color_format == HDMI_COLOR_FORMAT_422) {
+ switch (color_depth) {
+ case HDMI_COLOR_DEPTH_36B:
+ tmp = 2;
+ break;
+ case HDMI_COLOR_DEPTH_30B:
+ tmp = 1;
+ break;
+ case HDMI_COLOR_DEPTH_24B:
+ tmp = 0;
+ break;
+ }
+ }
+ hdmitx_set_reg_bits(HDMITX_DWC_VP_REMAP, tmp, 0, 2); /*[1:0] ycc422_size*/
+
+ /* Video Packet configuration */
+ data32 = 0;
+ data32 |= ((((output_color_format != HDMI_COLOR_FORMAT_422) &&
+ (color_depth == HDMI_COLOR_DEPTH_24B))? 1 : 0) << 6); /*[ 6] bypass_en*/
+ data32 |= ((((output_color_format == HDMI_COLOR_FORMAT_422) ||
+ (color_depth == HDMI_COLOR_DEPTH_24B))? 0 : 1) << 5); /*[ 5] pp_en*/
+ data32 |= (0 << 4); /*[ 4] pr_en*/
+ data32 |= (((output_color_format == HDMI_COLOR_FORMAT_422)? 1 : 0) << 3); /*[ 3] ycc422_en*/
+ data32 |= (1 << 2); /*[ 2] pr_bypass_select*/
+ data32 |= (((output_color_format == HDMI_COLOR_FORMAT_422)? 1 :
+ (color_depth == HDMI_COLOR_DEPTH_24B)? 2 : 0) << 0);
+ /*[1:0] output_selector: 0=pixel packing; 1=YCC422 remap; 2/3=8-bit bypass*/
+ hdmitx_wr_reg(HDMITX_DWC_VP_CONF, data32);
+
+ data32 = 0;
+ data32 |= (1 << 7);
+ data32 |= (1 << 6);
+ data32 |= (1 << 5);
+ data32 |= (1 << 4);
+ data32 |= (1 << 3);
+ data32 |= (1 << 2);
+ data32 |= (1 << 1);
+ data32 |= (1 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_VP_MASK, data32);
+
+ /* Configure audio */
+ /* I2S Sampler config */
+
+ data32 = 0;
+ data32 |= (1 << 3);
+ data32 |= (1 << 2);
+ hdmitx_wr_reg(HDMITX_DWC_AUD_INT, data32);
+
+ data32 = 0;
+ data32 |= (1 << 4);
+ hdmitx_wr_reg(HDMITX_DWC_AUD_INT1, data32);
+
+ hdmitx_wr_reg(HDMITX_DWC_FC_MULTISTREAM_CTRL, 0);
+
+/* if enable it now, fifo_overrun will happen, because packet don't get
+ * sent out until initial DE detected.
+ */
+ data32 = 0;
+ data32 |= (0 << 7);
+ data32 |= (1 << 5);
+ data32 |= (0 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_AUD_CONF0, data32);
+
+ data32 = 0;
+ data32 |= (0 << 5);
+ data32 |= (24 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_AUD_CONF1, data32);
+
+ data32 = 0;
+ data32 |= (0 << 1);
+ data32 |= (0 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_AUD_CONF2, data32);
+
+ /* spdif sampler config */
+
+ data32 = 0;
+ data32 |= (1 << 3);
+ data32 |= (1 << 2);
+ hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIFINT, data32);
+
+ data32 = 0;
+ data32 |= (0 << 4);
+ hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIFINT1, data32);
+
+ data32 = 0;
+ data32 |= (0 << 7);
+ hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIF0, data32);
+
+ data32 = 0;
+ data32 |= (0 << 7);
+ data32 |= (0 << 6);
+ data32 |= (24 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIF1, data32);
+
+ /* Frame Composer configuration */
+
+ /* Video definitions, as per output video(for packet gen/schedulling) */
+
+ data32 = 0;
+ data32 |= (1 << 7);
+ data32 |= (GET_TIMING(vsync_polarity) << 6);
+ data32 |= (GET_TIMING(hsync_polarity) << 5);
+ data32 |= (1 << 4);
+ data32 |= (1 << 3);
+ data32 |= (!(para->progress_mode) << 1);
+ data32 |= (!(para->progress_mode) << 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_INVIDCONF, data32);
+ if (!hdev->RXCap.IEEEOUI) /* DVI devices */
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_INVIDCONF, 0, 3, 1);
+
+ data32 = GET_TIMING(h_active)&0xff;
+ hdmitx_wr_reg(HDMITX_DWC_FC_INHACTV0, data32);
+ data32 = (GET_TIMING(h_active)>>8) & 0x3f;
+ hdmitx_wr_reg(HDMITX_DWC_FC_INHACTV1, data32);
+
+ data32 = GET_TIMING(h_blank) & 0xff;
+ hdmitx_wr_reg(HDMITX_DWC_FC_INHBLANK0, data32);
+ data32 = (GET_TIMING(h_blank)>>8)&0x1f;
+ hdmitx_wr_reg(HDMITX_DWC_FC_INHBLANK1, data32);
+
+ data32 = GET_TIMING(v_active)&0xff;
+ hdmitx_wr_reg(HDMITX_DWC_FC_INVACTV0, data32);
+ data32 = (GET_TIMING(v_active)>>8)&0x1f;
+ hdmitx_wr_reg(HDMITX_DWC_FC_INVACTV1, data32);
+
+ data32 = GET_TIMING(v_blank)&0xff;
+ hdmitx_wr_reg(HDMITX_DWC_FC_INVBLANK, data32);
+
+ data32 = GET_TIMING(h_front)&0xff;
+ hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINDELAY0, data32);
+ data32 = (GET_TIMING(h_front)>>8)&0x1f;
+ hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINDELAY1, data32);
+
+ data32 = GET_TIMING(h_sync)&0xff;
+ hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINWIDTH0, data32);
+ data32 = (GET_TIMING(h_sync)>>8)&0x3;
+ hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINWIDTH1, data32);
+
+ data32 = GET_TIMING(v_front)&0xff;
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSYNCINDELAY, data32);
+
+ data32 = GET_TIMING(v_sync)&0x3f;
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSYNCINWIDTH, data32);
+
+ /* control period duration (typ 12 tmds periods) */
+ hdmitx_wr_reg(HDMITX_DWC_FC_CTRLDUR, 12);
+ /* extended control period duration (typ 32 tmds periods) */
+ hdmitx_wr_reg(HDMITX_DWC_FC_EXCTRLDUR, 32);
+ /* max interval betwen extended control period duration (typ 50) */
+ hdmitx_wr_reg(HDMITX_DWC_FC_EXCTRLSPAC, 1);
+ /* preamble filler */
+ hdmitx_wr_reg(HDMITX_DWC_FC_CH0PREAM, 0x0b);
+ hdmitx_wr_reg(HDMITX_DWC_FC_CH1PREAM, 0x16);
+ hdmitx_wr_reg(HDMITX_DWC_FC_CH2PREAM, 0x21);
+
+ /* write GCP packet configuration */
+ data32 = 0;
+ data32 |= (default_phase << 2);
+ data32 |= (0 << 1);
+ data32 |= (1 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_GCP, data32);
+
+ /* write AVI Infoframe packet configuration */
+
+ data32 = 0;
+ data32 |= (((output_color_format>>2)&0x1) << 7);
+ data32 |= (1 << 6);
+ data32 |= (0x2 << 4);
+ data32 |= (0 << 2);
+ data32 |= (0x2 << 0); /* FIXED YCBCR 444 */
+ hdmitx_wr_reg(HDMITX_DWC_FC_AVICONF0, data32);
+ switch (output_color_format) {
+ case HDMI_COLOR_FORMAT_RGB:
+ tmp = 0;
+ break;
+ case HDMI_COLOR_FORMAT_422:
+ tmp = 1;
+ break;
+ case HDMI_COLOR_FORMAT_420:
+ tmp = 3;
+ break;
+ case HDMI_COLOR_FORMAT_444:
+ default:
+ tmp = 2;
+ break;
+ }
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF0, tmp, 0, 2);
+
+ hdmitx_wr_reg(HDMITX_DWC_FC_AVICONF1, 0x8);
+ hdmitx_wr_reg(HDMITX_DWC_FC_AVICONF2, 0);
+
+ /* set Aspect Ratio in AVIInfo */
+ switch (para->vic) {
+ case HDMI_640x480p60_4x3:
+ case HDMI_720x480p60_4x3:
+ case HDMI_720x480i60_4x3:
+ case HDMI_720x240p60_4x3:
+ case HDMI_2880x480i60_4x3:
+ case HDMI_2880x240p60_4x3:
+ case HDMI_1440x480p60_4x3:
+ case HDMI_720x576p50_4x3:
+ case HDMI_720x576i50_4x3:
+ case HDMI_720x288p_4x3:
+ case HDMI_2880x576i50_4x3:
+ case HDMI_2880x288p50_4x3:
+ case HDMI_1440x576p_4x3:
+ case HDMI_2880x480p60_4x3:
+ case HDMI_2880x576p50_4x3:
+ case HDMI_720x576p100_4x3:
+ case HDMI_720x576i100_4x3:
+ case HDMI_720x480p120_4x3:
+ case HDMI_720x480i120_4x3:
+ case HDMI_720x576p200_4x3:
+ case HDMI_720x576i200_4x3:
+ case HDMI_720x480p240_4x3:
+ case HDMI_720x480i240_4x3:
+ /* Picture Aspect Ratio M1/M0 4:3 */
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 0x1, 4, 2);
+ break;
+ default:
+ /* Picture Aspect Ratio M1/M0 16:9 */
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 0x2, 4, 2);
+ break;
+ }
+ /* Active Format Aspect Ratio R3~R0 Same as picture aspect ratio */
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 0x8, 0, 4);
+
+ /* set Colorimetry in AVIInfo */
+ switch (para->vic) {
+ case HDMI_640x480p60_4x3:
+ case HDMI_720x480p60_4x3:
+ case HDMI_720x480p60_16x9:
+ case HDMI_720x480i60_4x3:
+ case HDMI_720x480i60_16x9:
+ case HDMI_720x240p60_4x3:
+ case HDMI_720x240p60_16x9:
+ case HDMI_2880x480i60_4x3:
+ case HDMI_2880x480i60_16x9:
+ case HDMI_2880x240p60_4x3:
+ case HDMI_2880x240p60_16x9:
+ case HDMI_1440x480p60_4x3:
+ case HDMI_1440x480p60_16x9:
+ case HDMI_720x576p50_4x3:
+ case HDMI_720x576p50_16x9:
+ case HDMI_720x576i50_4x3:
+ case HDMI_720x576i50_16x9:
+ case HDMI_720x288p_4x3:
+ case HDMI_720x288p_16x9:
+ case HDMI_2880x576i50_4x3:
+ case HDMI_2880x576i50_16x9:
+ case HDMI_2880x288p50_4x3:
+ case HDMI_2880x288p50_16x9:
+ case HDMI_1440x576p_4x3:
+ case HDMI_1440x576p_16x9:
+ case HDMI_2880x480p60_4x3:
+ case HDMI_2880x480p60_16x9:
+ case HDMI_2880x576p50_4x3:
+ case HDMI_2880x576p50_16x9:
+ case HDMI_720x576p100_4x3:
+ case HDMI_720x576p100_16x9:
+ case HDMI_720x576i100_4x3:
+ case HDMI_720x576i100_16x9:
+ case HDMI_720x480p120_4x3:
+ case HDMI_720x480p120_16x9:
+ case HDMI_720x480i120_4x3:
+ case HDMI_720x480i120_16x9:
+ case HDMI_720x576p200_4x3:
+ case HDMI_720x576p200_16x9:
+ case HDMI_720x576i200_4x3:
+ case HDMI_720x576i200_16x9:
+ case HDMI_720x480p240_4x3:
+ case HDMI_720x480p240_16x9:
+ case HDMI_720x480i240_4x3:
+ case HDMI_720x480i240_16x9:
+ /* C1C0 601 , now is 709*/
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 1, 6, 2);
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF2, 0, 4, 3);
+ break;
+ default:
+ /* C1C0 709 */
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 2, 6, 2);
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF2, 0, 4, 3);
+ break;
+ }
+
+ data32 = 0;
+ data32 |= (((output_color_range == HDMI_COLOR_RANGE_FUL)?1:0) << 2); /*[3:2] YQ*/
+ data32 |= (0 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_AVICONF3, data32);
+
+ if (para->vic >= HDMITX_VESA_OFFSET)
+ hdmitx_wr_reg(HDMITX_DWC_FC_AVIVID, 0);
+ else
+ hdmitx_wr_reg(HDMITX_DWC_FC_AVIVID, para->vic);
+
+/* the audio setting bellow are only used for I2S audio IEC60958-3 frame
+ * insertion
+ */
+
+ /* packet queue priority (auto mode) */
+ hdmitx_wr_reg(HDMITX_DWC_FC_CTRLQHIGH, 15);
+ hdmitx_wr_reg(HDMITX_DWC_FC_CTRLQLOW, 3);
+
+ /* packet scheduller configuration for SPD, VSD, ISRC1/2, ACP. */
+ data32 = 0;
+ data32 |= (0 << 4);
+ data32 |= (0 << 3);
+ data32 |= (0 << 2);
+ data32 |= (0 << 1);
+ data32 |= (0 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO0, data32);
+ hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO1, 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO2, 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_DATMAN, 0);
+ hdmitx_set_spdinfo();
+
+ /* packet scheduller configuration for AVI, GCP, AUDI, ACR. */
+ data32 = 0;
+ data32 |= (0 << 5);
+ data32 |= (0 << 4);
+ data32 |= (0 << 3);
+ data32 |= (1 << 2);
+ data32 |= (1 << 1);
+ data32 |= (0 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO3, data32);
+ hdmitx_wr_reg(HDMITX_DWC_FC_RDRB0, 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_RDRB1, 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_RDRB2, 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_RDRB3, 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_RDRB4, 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_RDRB5, 0);
+ /* AVI info usb RDRB mode and place in line 10*/
+ hdmitx_wr_reg(HDMITX_DWC_FC_RDRB6, 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_RDRB7, 0x1a);
+ hdmitx_wr_reg(HDMITX_DWC_FC_RDRB8, 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_RDRB9, 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_RDRB10, 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_RDRB11, 0);
+
+ /* Packet transmission enable */
+ data32 = 0;
+ data32 |= (0 << 6);
+ data32 |= (0 << 5);
+ data32 |= (0 << 4);
+ data32 |= (1 << 3);
+ data32 |= (1 << 2);
+ data32 |= (1 << 1);
+ data32 |= (1 << 0);
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_PACKET_TX_EN, data32, 0, 4);
+
+ /* For 3D video */
+ data32 = 0;
+ data32 |= (0 << 1);
+ data32 |= (0 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_ACTSPC_HDLR_CFG, data32);
+
+ data32 = GET_TIMING(v_active)&0xff;
+ hdmitx_wr_reg(HDMITX_DWC_FC_INVACT_2D_0, data32);
+ data32 = (GET_TIMING(v_active)>>8)&0xf;
+ hdmitx_wr_reg(HDMITX_DWC_FC_INVACT_2D_1, data32);
+
+ /* Do not enable these interrupt below, we can check them at RX side. */
+ data32 = 0;
+ data32 |= (1 << 7);
+ data32 |= (1 << 6);
+ data32 |= (1 << 5);
+ data32 |= (1 << 2);
+ data32 |= (1 << 1);
+ data32 |= (1 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_MASK0, data32);
+
+ data32 = 0;
+ data32 |= (1 << 7);
+ data32 |= (1 << 6);
+ data32 |= (1 << 5);
+ data32 |= (1 << 4);
+ data32 |= (1 << 3);
+ data32 |= (1 << 1);
+ data32 |= (1 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_MASK1, data32);
+
+ data32 = 0;
+ data32 |= (1 << 1);
+ data32 |= (1 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_MASK2, data32);
+
+ /* Pixel repetition ratio the input and output video */
+ data32 = 0;
+ data32 |= ((para->pixel_repetition_factor+1) << 4);
+ data32 |= (para->pixel_repetition_factor << 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_PRCONF, data32);
+
+ /* Configure HDCP */
+ data32 = 0;
+ data32 |= (0 << 7);
+ data32 |= (0 << 6);
+ data32 |= (0 << 4);
+ data32 |= (0 << 3);
+ data32 |= (0 << 2);
+ data32 |= (0 << 1);
+ data32 |= (1 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_A_APIINTMSK, data32);
+
+ data32 = 0;
+ data32 |= (0 << 5);
+ data32 |= (1 << 4);
+ data32 |= (1 << 3);
+ data32 |= (1 << 1);
+ hdmitx_wr_reg(HDMITX_DWC_A_VIDPOLCFG, data32);
+
+ hdmitx_wr_reg(HDMITX_DWC_A_OESSWCFG, 0x40);
+ hdmitx_hdcp_init();
+
+ /* Interrupts */
+ /* Clear interrupts */
+ hdmitx_wr_reg(HDMITX_DWC_IH_FC_STAT0, 0xff);
+ hdmitx_wr_reg(HDMITX_DWC_IH_FC_STAT1, 0xff);
+ hdmitx_wr_reg(HDMITX_DWC_IH_FC_STAT2, 0xff);
+ hdmitx_wr_reg(HDMITX_DWC_IH_AS_STAT0, 0xff);
+ hdmitx_wr_reg(HDMITX_DWC_IH_PHY_STAT0, 0xff);
+ hdmitx_wr_reg(HDMITX_DWC_IH_I2CM_STAT0, 0xff);
+ hdmitx_wr_reg(HDMITX_DWC_IH_CEC_STAT0, 0xff);
+ hdmitx_wr_reg(HDMITX_DWC_IH_VP_STAT0, 0xff);
+ hdmitx_wr_reg(HDMITX_DWC_IH_I2CMPHY_STAT0, 0xff);
+ hdmitx_wr_reg(HDMITX_DWC_A_APIINTCLR, 0xff);
+ hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_STAT, 0xff);
+
+ hdmitx_wr_reg(HDMITX_TOP_INTR_STAT_CLR, 0x0000001f);
+
+ /* Selectively enable/mute interrupt sources */
+ data32 = 0;
+ data32 |= (1 << 7);
+ data32 |= (1 << 6);
+ data32 |= (1 << 5);
+ data32 |= (1 << 4);
+ data32 |= (1 << 3);
+ data32 |= (1 << 2);
+ data32 |= (1 << 1);
+ data32 |= (1 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_FC_STAT0, data32);
+
+ data32 = 0;
+ data32 |= (1 << 7);
+ data32 |= (1 << 6);
+ data32 |= (1 << 5);
+ data32 |= (1 << 4);
+ data32 |= (1 << 3);
+ data32 |= (1 << 2);
+ data32 |= (1 << 1);
+ data32 |= (1 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_FC_STAT1, data32);
+
+ data32 = 0;
+ data32 |= (1 << 1);
+ data32 |= (1 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_FC_STAT2, data32);
+
+ data32 = 0;
+ data32 |= (0 << 4);
+ data32 |= (0 << 3);
+ data32 |= (1 << 2);
+ data32 |= (1 << 1);
+ data32 |= (1 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_AS_STAT0, data32);
+
+ hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_PHY_STAT0, 0x3f);
+
+ data32 = 0;
+ data32 |= (0 << 2);
+ data32 |= (1 << 1);
+ data32 |= (0 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_I2CM_STAT0, data32);
+
+ data32 = 0;
+ data32 |= (0 << 6);
+ data32 |= (0 << 5);
+ data32 |= (0 << 4);
+ data32 |= (0 << 3);
+ data32 |= (0 << 2);
+ data32 |= (0 << 1);
+ data32 |= (0 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_CEC_STAT0, data32);
+
+ hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_VP_STAT0, 0xff);
+
+ hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_I2CMPHY_STAT0, 0x03);
+
+ data32 = 0;
+ data32 |= (0 << 1);
+ data32 |= (0 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_IH_MUTE, data32);
+
+ data32 = 0;
+ data32 |= (1 << 4);
+ data32 |= (1 << 3);
+ data32 |= (1 << 2);
+ data32 |= (1 << 1);
+ data32 |= (1 << 0);
+ hdmitx_wr_reg(HDMITX_TOP_INTR_MASKN, data32);
+
+ /* Reset pulse */
+ hdmitx_rd_check_reg(HDMITX_DWC_MC_LOCKONCLOCK, 0xff, 0x9f);
+
+ hdmitx_wr_reg(HDMITX_DWC_MC_SWRSTZREQ, 0);
+ mdelay(10);
+
+ data32 = 0;
+ data32 |= (1 << 7);
+ data32 |= (1 << 6);
+ data32 |= (1 << 4);
+ data32 |= (1 << 3);
+ data32 |= (1 << 2);
+ data32 |= (0 << 1);
+ data32 |= (1 << 0);
+ hdmitx_wr_reg(HDMITX_DWC_MC_SWRSTZREQ, data32);
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSYNCINWIDTH,
+ hdmitx_rd_reg(HDMITX_DWC_FC_VSYNCINWIDTH));
+} /* config_hdmi20_tx */
+
+/* Set TV encoder for HDMI */
+static void hdmitx_enc(enum hdmi_vic vic)
+{
+ set_vmode_enc_hw(vic);
+ hdmi_tvenc_set(vic);
+ return;
+}
+
+static void hdmitx_set_pll(struct hdmitx_dev *hdev)
+{
+ hdmitx_set_clk(hdev);
+}
+
+/*
+ * mode: 1 means Progressive; 0 means interlaced
+ */
+static void enc_vpu_bridge_reset(int mode)
+{
+ unsigned int wr_clk = 0;
+
+ wr_clk = (hd_read_reg(P_VPU_HDMI_SETTING) & 0xf00) >> 8;
+ if (mode) {
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 0, 2); /*[ 0] src_sel_enci: Disable ENCP output to HDMI*/
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 8, 4); /*[ 0] src_sel_enci: Disable ENCP output to HDMI*/
+ mdelay(1);
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, wr_clk, 8, 4);
+ mdelay(1);
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 2, 0, 2); /*[ 0] src_sel_enci: Enable ENCP output to HDMI*/
+ } else {
+ hd_write_reg(P_ENCI_VIDEO_EN, 0);
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 0, 2); /*[ 0] src_sel_enci: Disable ENCI output to HDMI*/
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 8, 4); /*[ 0] src_sel_enci: Disable ENCP output to HDMI*/
+ mdelay(1);
+ hd_write_reg(P_ENCI_VIDEO_EN, 1);
+ mdelay(1);
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, wr_clk, 8, 4);
+ mdelay(1);
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 0, 2); /*[ 0] src_sel_enci: Enable ENCI output to HDMI*/
+ }
+}
+
+static void hdmi_tvenc1080i_set(enum hdmi_vic vic)
+{
+ unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2;
+ unsigned long TOTAL_PIXELS = 0, PIXEL_REPEAT_HDMI = 0,
+ PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 0;
+ unsigned FRONT_PORCH = 88, HSYNC_PIXELS = 0, ACTIVE_LINES = 0,
+ INTERLACE_MODE = 0, TOTAL_LINES = 0, SOF_LINES = 0,
+ VSYNC_LINES = 0;
+ unsigned LINES_F0 = 0, LINES_F1 = 563, BACK_PORCH = 0;
+
+ unsigned long total_pixels_venc = 0;
+ unsigned long active_pixels_venc = 0;
+ unsigned long front_porch_venc = 0;
+ unsigned long hsync_pixels_venc = 0;
+
+ unsigned long de_h_begin = 0, de_h_end = 0;
+ unsigned long de_v_begin_even = 0, de_v_end_even = 0,
+ de_v_begin_odd = 0, de_v_end_odd = 0;
+ unsigned long hs_begin = 0, hs_end = 0;
+ unsigned long vs_adjust = 0;
+ unsigned long vs_bline_evn = 0, vs_eline_evn = 0,
+ vs_bline_odd = 0, vs_eline_odd = 0;
+ unsigned long vso_begin_evn = 0, vso_begin_odd = 0;
+
+ if ((vic == HDMI_1920x1080i60_16x9) ||
+ (vic == HDMI_1920x1080i120_16x9)) {
+ INTERLACE_MODE = 1;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (1080/(1+INTERLACE_MODE));
+ LINES_F0 = 562;
+ LINES_F1 = 563;
+ FRONT_PORCH = 88;
+ HSYNC_PIXELS = 44;
+ BACK_PORCH = 148;
+ VSYNC_LINES = 5;
+ SOF_LINES = 15;
+ } else if ((vic == HDMI_1920x1080i50_16x9) ||
+ (vic == HDMI_1920x1080i100_16x9)) {
+ INTERLACE_MODE = 1;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (1080/(1+INTERLACE_MODE));
+ LINES_F0 = 562;
+ LINES_F1 = 563;
+ FRONT_PORCH = 528;
+ HSYNC_PIXELS = 44;
+ BACK_PORCH = 148;
+ VSYNC_LINES = 5;
+ SOF_LINES = 15;
+ }
+ TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS);
+ TOTAL_LINES = (LINES_F0+(LINES_F1*INTERLACE_MODE));
+
+ total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
+ (1+PIXEL_REPEAT_VENC);
+ active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
+ (1+PIXEL_REPEAT_VENC);
+ front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) *
+ (1+PIXEL_REPEAT_VENC);
+ hsync_pixels_venc =
+ (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) * (1+PIXEL_REPEAT_VENC);
+
+ hd_write_reg(P_ENCP_VIDEO_MODE, hd_read_reg(P_ENCP_VIDEO_MODE)|(1<<14));
+
+ /* Program DE timing */
+ de_h_begin = modulo(hd_read_reg(P_ENCP_VIDEO_HAVON_BEGIN) +
+ VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc);
+ de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc);
+ hd_write_reg(P_ENCP_DE_H_BEGIN, de_h_begin);
+ hd_write_reg(P_ENCP_DE_H_END, de_h_end);
+ /* Program DE timing for even field */
+ de_v_begin_even = hd_read_reg(P_ENCP_VIDEO_VAVON_BLINE);
+ de_v_end_even = de_v_begin_even + ACTIVE_LINES;
+ hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even);
+ hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even);
+ /* Program DE timing for odd field if needed */
+ if (INTERLACE_MODE) {
+ de_v_begin_odd = to_signed((
+ hd_read_reg(P_ENCP_VIDEO_OFLD_VOAV_OFST) & 0xf0)>>4)
+ + de_v_begin_even + (TOTAL_LINES-1)/2;
+ de_v_end_odd = de_v_begin_odd + ACTIVE_LINES;
+ hd_write_reg(P_ENCP_DE_V_BEGIN_ODD, de_v_begin_odd);/* 583 */
+ hd_write_reg(P_ENCP_DE_V_END_ODD, de_v_end_odd); /* 1123 */
+ }
+
+ /* Program Hsync timing */
+ if (de_h_end + front_porch_venc >= total_pixels_venc) {
+ hs_begin = de_h_end + front_porch_venc - total_pixels_venc;
+ vs_adjust = 1;
+ } else {
+ hs_begin = de_h_end + front_porch_venc;
+ vs_adjust = 0;
+ }
+ hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc);
+ hd_write_reg(P_ENCP_DVI_HSO_BEGIN, hs_begin);
+ hd_write_reg(P_ENCP_DVI_HSO_END, hs_end);
+
+ /* Program Vsync timing for even field */
+ if (de_v_begin_even >= SOF_LINES + VSYNC_LINES + (1-vs_adjust))
+ vs_bline_evn = de_v_begin_even - SOF_LINES - VSYNC_LINES
+ - (1-vs_adjust);
+ else
+ vs_bline_evn = TOTAL_LINES + de_v_begin_even - SOF_LINES
+ - VSYNC_LINES - (1-vs_adjust);
+
+ vs_eline_evn = modulo(vs_bline_evn + VSYNC_LINES, TOTAL_LINES);
+ hd_write_reg(P_ENCP_DVI_VSO_BLINE_EVN, vs_bline_evn); /* 0 */
+ hd_write_reg(P_ENCP_DVI_VSO_ELINE_EVN, vs_eline_evn); /* 5 */
+ vso_begin_evn = hs_begin; /* 2 */
+ hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn); /* 2 */
+ hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn); /* 2 */
+ /* Program Vsync timing for odd field if needed */
+ if (INTERLACE_MODE) {
+ vs_bline_odd = de_v_begin_odd-1 - SOF_LINES - VSYNC_LINES;
+ vs_eline_odd = de_v_begin_odd-1 - SOF_LINES;
+ vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1),
+ total_pixels_venc);
+ hd_write_reg(P_ENCP_DVI_VSO_BLINE_ODD, vs_bline_odd);
+ hd_write_reg(P_ENCP_DVI_VSO_ELINE_ODD, vs_eline_odd);
+ hd_write_reg(P_ENCP_DVI_VSO_BEGIN_ODD, vso_begin_odd);
+ hd_write_reg(P_ENCP_DVI_VSO_END_ODD, vso_begin_odd);
+ }
+
+ hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
+ (0 << 1) |
+ (HSYNC_POLARITY << 2) |
+ (VSYNC_POLARITY << 3) |
+ (0 << 4) |
+ (4 << 5) |
+ (0 << 8) |
+ (0 << 12)
+ );
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
+
+}
+
+static bool is_hdmi4k_420(enum hdmi_vic vic)
+{
+ if ((vic & HDMITX_VIC420_OFFSET) == HDMITX_VIC420_OFFSET)
+ return 1;
+ return 0;
+}
+
+static void hdmi_tvenc4k2k_set(enum hdmi_vic vic)
+{
+ unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2;
+ unsigned long TOTAL_PIXELS = 4400, PIXEL_REPEAT_HDMI = 0,
+ PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 3840;
+ unsigned FRONT_PORCH = 1020, HSYNC_PIXELS = 0, ACTIVE_LINES = 2160,
+ INTERLACE_MODE = 0, TOTAL_LINES = 0, SOF_LINES = 0,
+ VSYNC_LINES = 0;
+ unsigned LINES_F0 = 2250, LINES_F1 = 2250, BACK_PORCH = 0;
+
+ unsigned long total_pixels_venc = 0;
+ unsigned long active_pixels_venc = 0;
+ unsigned long front_porch_venc = 0;
+ unsigned long hsync_pixels_venc = 0;
+
+ unsigned long de_h_begin = 0, de_h_end = 0;
+ unsigned long de_v_begin_even = 0, de_v_end_even = 0;
+ unsigned long hs_begin = 0, hs_end = 0;
+ unsigned long vs_adjust = 0;
+ unsigned long vs_adjust_420 = 0;
+ unsigned long vs_bline_evn = 0, vs_eline_evn = 0;
+ unsigned long vso_begin_evn = 0;
+
+/* Due to 444->420 line buffer latency, the active line output from
+ * 444->420 conversion will be delayed by 1 line. So for 420 mode,
+ * we need to delay Vsync by 1 line as well, to meet the timing
+ */
+ if (is_hdmi4k_420(vic))
+ vs_adjust_420 = 1;
+
+ switch (vic) {
+ case HDMI_3840x2160p30_16x9:
+ case HDMI_3840x2160p60_16x9:
+ case HDMI_3840x2160p60_16x9_Y420:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (3840*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (2160/(1+INTERLACE_MODE));
+ LINES_F0 = 2250;
+ LINES_F1 = 2250;
+ FRONT_PORCH = 176;
+ HSYNC_PIXELS = 88;
+ BACK_PORCH = 296;
+ VSYNC_LINES = 10;
+ SOF_LINES = 72 + 1;
+ break;
+ case HDMI_3840x2160p25_16x9:
+ case HDMI_3840x2160p50_16x9:
+ case HDMI_3840x2160p50_16x9_Y420:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (3840*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (2160/(1+INTERLACE_MODE));
+ LINES_F0 = 2250;
+ LINES_F1 = 2250;
+ FRONT_PORCH = 1056;
+ HSYNC_PIXELS = 88;
+ BACK_PORCH = 296;
+ VSYNC_LINES = 10;
+ SOF_LINES = 72 + 1;
+ break;
+ case HDMI_3840x2160p24_16x9:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (3840*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (2160/(1+INTERLACE_MODE));
+ LINES_F0 = 2250;
+ LINES_F1 = 2250;
+ FRONT_PORCH = 1276;
+ HSYNC_PIXELS = 88;
+ BACK_PORCH = 296;
+ VSYNC_LINES = 10;
+ SOF_LINES = 72 + 1;
+ break;
+ case HDMI_4096x2160p24_256x135:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (4096*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (2160/(1+INTERLACE_MODE));
+ LINES_F0 = 2250;
+ LINES_F1 = 2250;
+ FRONT_PORCH = 1020;
+ HSYNC_PIXELS = 88;
+ BACK_PORCH = 296;
+ VSYNC_LINES = 10;
+ SOF_LINES = 72 + 1;
+ break;
+ case HDMI_4096x2160p25_256x135:
+ case HDMI_4096x2160p50_256x135:
+ case HDMI_4096x2160p50_256x135_Y420:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (4096*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (2160/(1+INTERLACE_MODE));
+ LINES_F0 = 2250;
+ LINES_F1 = 2250;
+ FRONT_PORCH = 968;
+ HSYNC_PIXELS = 88;
+ BACK_PORCH = 128;
+ VSYNC_LINES = 10;
+ SOF_LINES = 72;
+ break;
+ case HDMI_4096x2160p30_256x135:
+ case HDMI_4096x2160p60_256x135:
+ case HDMI_4096x2160p60_256x135_Y420:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (4096*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (2160/(1+INTERLACE_MODE));
+ LINES_F0 = 2250;
+ LINES_F1 = 2250;
+ FRONT_PORCH = 88;
+ HSYNC_PIXELS = 88;
+ BACK_PORCH = 128;
+ VSYNC_LINES = 10;
+ SOF_LINES = 72;
+ break;
+ default:
+ printk("hdmitx20: no setting for VIC = %d\n", vic);
+ break;
+ }
+
+ TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS);
+ TOTAL_LINES = (LINES_F0+(LINES_F1*INTERLACE_MODE));
+
+ total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
+ (1+PIXEL_REPEAT_VENC);
+ active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
+ (1+PIXEL_REPEAT_VENC);
+ front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) *
+ (1+PIXEL_REPEAT_VENC);
+ hsync_pixels_venc = (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
+ (1+PIXEL_REPEAT_VENC);
+
+ de_h_begin = modulo(hd_read_reg(P_ENCP_VIDEO_HAVON_BEGIN) +
+ VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc);
+ de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc);
+ hd_write_reg(P_ENCP_DE_H_BEGIN, de_h_begin);
+ hd_write_reg(P_ENCP_DE_H_END, de_h_end);
+ /* Program DE timing for even field */
+ de_v_begin_even = hd_read_reg(P_ENCP_VIDEO_VAVON_BLINE);
+ de_v_end_even = modulo(de_v_begin_even + ACTIVE_LINES, TOTAL_LINES);
+ hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even);
+ hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even);
+
+ /* Program Hsync timing */
+ if (de_h_end + front_porch_venc >= total_pixels_venc) {
+ hs_begin = de_h_end + front_porch_venc - total_pixels_venc;
+ vs_adjust = 1;
+ } else {
+ hs_begin = de_h_end + front_porch_venc;
+ vs_adjust = 1;
+ }
+ hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc);
+ hd_write_reg(P_ENCP_DVI_HSO_BEGIN, hs_begin);
+ hd_write_reg(P_ENCP_DVI_HSO_END, hs_end);
+
+ /* Program Vsync timing for even field */
+ if (de_v_begin_even + vs_adjust_420 >=
+ SOF_LINES + VSYNC_LINES + (1 - vs_adjust))
+ vs_bline_evn = de_v_begin_even + vs_adjust_420 - SOF_LINES -
+ VSYNC_LINES - (1 - vs_adjust);
+ else
+ vs_bline_evn = TOTAL_LINES + de_v_begin_even + vs_adjust_420 -
+ SOF_LINES - VSYNC_LINES - (1 - vs_adjust);
+ vs_eline_evn = modulo(vs_bline_evn + VSYNC_LINES, TOTAL_LINES);
+ hd_write_reg(P_ENCP_DVI_VSO_BLINE_EVN, vs_bline_evn);
+ hd_write_reg(P_ENCP_DVI_VSO_ELINE_EVN, vs_eline_evn);
+ vso_begin_evn = hs_begin;
+ hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn);
+ hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn);
+ hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
+ (0 << 1) |
+ (HSYNC_POLARITY << 2) |
+ (VSYNC_POLARITY << 3) |
+ (0 << 4) |
+ (4 << 5) |
+ (0 << 8) |
+ (0 << 12)
+ );
+ if (is_hdmi4k_420(vic)) {
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 8, 1);
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 20, 1);
+ }
+
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
+}
+
+static void hdmi_tvenc480i_set(enum hdmi_vic vic)
+{
+ unsigned long VFIFO2VD_TO_HDMI_LATENCY = 1;
+ unsigned long TOTAL_PIXELS = 0, PIXEL_REPEAT_HDMI = 0,
+ PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 0;
+ unsigned FRONT_PORCH = 38, HSYNC_PIXELS = 124, ACTIVE_LINES = 0,
+ INTERLACE_MODE = 0, VSYNC_LINES = 0;
+ unsigned LINES_F0 = 262, LINES_F1 = 263, BACK_PORCH = 114,
+ EOF_LINES = 2;
+
+ unsigned long total_pixels_venc = 0;
+ unsigned long active_pixels_venc = 0;
+ unsigned long front_porch_venc = 0;
+ unsigned long hsync_pixels_venc = 0;
+
+ unsigned long de_h_begin = 0, de_h_end = 0;
+ unsigned long de_v_begin_even = 0, de_v_end_even = 0,
+ de_v_begin_odd = 0, de_v_end_odd = 0;
+ unsigned long hs_begin = 0, hs_end = 0;
+ unsigned long vs_adjust = 0;
+ unsigned long vs_bline_evn = 0, vs_eline_evn = 0,
+ vs_bline_odd = 0, vs_eline_odd = 0;
+ unsigned long vso_begin_evn = 0, vso_begin_odd = 0;
+
+ /* hd_set_reg_bits(P_HHI_GCLK_OTHER, 1, 8, 1); TODO */
+ switch (vic) {
+ case HDMI_720x480i60_4x3:
+ case HDMI_720x480i60_16x9:
+ case HDMI_720x480i120_4x3:
+ case HDMI_720x480i120_16x9:
+ case HDMI_720x480i240_4x3:
+ case HDMI_720x480i240_16x9:
+ INTERLACE_MODE = 1;
+ PIXEL_REPEAT_VENC = 1;
+ PIXEL_REPEAT_HDMI = 1;
+ ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (480/(1+INTERLACE_MODE));
+ LINES_F0 = 262;
+ LINES_F1 = 263;
+ FRONT_PORCH = 38;
+ HSYNC_PIXELS = 124;
+ BACK_PORCH = 114;
+ EOF_LINES = 4;
+ VSYNC_LINES = 3;
+ break;
+ case HDMI_720x576i50_4x3:
+ case HDMI_720x576i50_16x9:
+ case HDMI_720x576i100_4x3:
+ case HDMI_720x576i100_16x9:
+ case HDMI_720x576i200_4x3:
+ case HDMI_720x576i200_16x9:
+ INTERLACE_MODE = 1;
+ PIXEL_REPEAT_VENC = 1;
+ PIXEL_REPEAT_HDMI = 1;
+ ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (576/(1+INTERLACE_MODE));
+ LINES_F0 = 312;
+ LINES_F1 = 313;
+ FRONT_PORCH = 24;
+ HSYNC_PIXELS = 126;
+ BACK_PORCH = 138;
+ EOF_LINES = 2;
+ VSYNC_LINES = 3;
+ break;
+ default:
+ break;
+ }
+
+ TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS);
+
+ total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
+ (1+PIXEL_REPEAT_VENC); /* 1716 / 2 * 2 = 1716 */
+ active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
+ (1+PIXEL_REPEAT_VENC);
+ front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) *
+ (1+PIXEL_REPEAT_VENC); /* 38 / 2 * 2 = 38 */
+ hsync_pixels_venc = (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
+ (1+PIXEL_REPEAT_VENC); /* 124 / 2 * 2 = 124 */
+
+ de_h_begin = modulo(hd_read_reg(P_ENCI_VFIFO2VD_PIXEL_START) +
+ VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc);
+ de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc);
+ hd_write_reg(P_ENCI_DE_H_BEGIN, de_h_begin); /* 235 */
+ hd_write_reg(P_ENCI_DE_H_END, de_h_end); /* 1675 */
+
+ de_v_begin_even = hd_read_reg(P_ENCI_VFIFO2VD_LINE_TOP_START);
+ de_v_end_even = de_v_begin_even + ACTIVE_LINES;
+ de_v_begin_odd = hd_read_reg(P_ENCI_VFIFO2VD_LINE_BOT_START);
+ de_v_end_odd = de_v_begin_odd + ACTIVE_LINES;
+ hd_write_reg(P_ENCI_DE_V_BEGIN_EVEN, de_v_begin_even);
+ hd_write_reg(P_ENCI_DE_V_END_EVEN, de_v_end_even);
+ hd_write_reg(P_ENCI_DE_V_BEGIN_ODD, de_v_begin_odd);
+ hd_write_reg(P_ENCI_DE_V_END_ODD, de_v_end_odd);
+
+ /* Program Hsync timing */
+ if (de_h_end + front_porch_venc >= total_pixels_venc) {
+ hs_begin = de_h_end + front_porch_venc - total_pixels_venc;
+ vs_adjust = 1;
+ } else {
+ hs_begin = de_h_end + front_porch_venc;
+ vs_adjust = 0;
+ }
+ hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc);
+ hd_write_reg(P_ENCI_DVI_HSO_BEGIN, hs_begin); /* 1713 */
+ hd_write_reg(P_ENCI_DVI_HSO_END, hs_end); /* 121 */
+
+ /* Program Vsync timing for even field */
+ if (de_v_end_odd-1 + EOF_LINES + vs_adjust >= LINES_F1) {
+ vs_bline_evn = de_v_end_odd-1 + EOF_LINES + vs_adjust
+ - LINES_F1;
+ vs_eline_evn = vs_bline_evn + VSYNC_LINES;
+ hd_write_reg(P_ENCI_DVI_VSO_BLINE_EVN, vs_bline_evn);
+ /* vso_bline_evn_reg_wr_cnt ++; */
+ hd_write_reg(P_ENCI_DVI_VSO_ELINE_EVN, vs_eline_evn);
+ /* vso_eline_evn_reg_wr_cnt ++; */
+ hd_write_reg(P_ENCI_DVI_VSO_BEGIN_EVN, hs_begin);
+ hd_write_reg(P_ENCI_DVI_VSO_END_EVN, hs_begin);
+ } else {
+ vs_bline_odd = de_v_end_odd-1 + EOF_LINES + vs_adjust;
+ hd_write_reg(P_ENCI_DVI_VSO_BLINE_ODD, vs_bline_odd);
+ /* vso_bline_odd_reg_wr_cnt ++; */
+ hd_write_reg(P_ENCI_DVI_VSO_BEGIN_ODD, hs_begin);
+ if (vs_bline_odd + VSYNC_LINES >= LINES_F1) {
+ vs_eline_evn = vs_bline_odd + VSYNC_LINES - LINES_F1;
+ hd_write_reg(P_ENCI_DVI_VSO_ELINE_EVN, vs_eline_evn);
+ /* vso_eline_evn_reg_wr_cnt ++; */
+ hd_write_reg(P_ENCI_DVI_VSO_END_EVN, hs_begin);
+ } else {
+ vs_eline_odd = vs_bline_odd + VSYNC_LINES;
+ hd_write_reg(P_ENCI_DVI_VSO_ELINE_ODD, vs_eline_odd);
+ /* vso_eline_odd_reg_wr_cnt ++; */
+ hd_write_reg(P_ENCI_DVI_VSO_END_ODD, hs_begin);
+ }
+ }
+ /* Program Vsync timing for odd field */
+ if (de_v_end_even-1 + EOF_LINES + 1 >= LINES_F0) {
+ vs_bline_odd = de_v_end_even-1 + EOF_LINES + 1 - LINES_F0;
+ vs_eline_odd = vs_bline_odd + VSYNC_LINES;
+ hd_write_reg(P_ENCI_DVI_VSO_BLINE_ODD, vs_bline_odd);
+ /* vso_bline_odd_reg_wr_cnt ++; */
+ hd_write_reg(P_ENCI_DVI_VSO_ELINE_ODD, vs_eline_odd);
+ /* vso_eline_odd_reg_wr_cnt ++; */
+ vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1),
+ total_pixels_venc);
+ hd_write_reg(P_ENCI_DVI_VSO_BEGIN_ODD, vso_begin_odd);
+ hd_write_reg(P_ENCI_DVI_VSO_END_ODD, vso_begin_odd);
+ } else {
+ vs_bline_evn = de_v_end_even-1 + EOF_LINES + 1;
+ hd_write_reg(P_ENCI_DVI_VSO_BLINE_EVN, vs_bline_evn); /* 261 */
+ /* vso_bline_evn_reg_wr_cnt ++; */
+ vso_begin_evn = modulo(hs_begin + (total_pixels_venc>>1),
+ total_pixels_venc);
+ hd_write_reg(P_ENCI_DVI_VSO_BEGIN_EVN, vso_begin_evn);
+ if (vs_bline_evn + VSYNC_LINES >= LINES_F0) {
+ vs_eline_odd = vs_bline_evn + VSYNC_LINES - LINES_F0;
+ hd_write_reg(P_ENCI_DVI_VSO_ELINE_ODD, vs_eline_odd);
+ /* vso_eline_odd_reg_wr_cnt ++; */
+ hd_write_reg(P_ENCI_DVI_VSO_END_ODD, vso_begin_evn);
+ } else {
+ vs_eline_evn = vs_bline_evn + VSYNC_LINES;
+ hd_write_reg(P_ENCI_DVI_VSO_ELINE_EVN, vs_eline_evn);
+ /* vso_eline_evn_reg_wr_cnt ++; */
+ hd_write_reg(P_ENCI_DVI_VSO_END_EVN, vso_begin_evn);
+ }
+ }
+
+ hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
+ (0 << 1) |
+ (0 << 2) |
+ (0 << 3) |
+ (0 << 4) |
+ (4 << 5) |
+ (1 << 8) |
+ (1 << 12)
+ );
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 0, 1);
+}
+
+static void hdmi_tvenc_set_def(enum hdmi_vic vic)
+{
+ unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2;
+ unsigned long TOTAL_PIXELS = 0, PIXEL_REPEAT_HDMI = 0,
+ PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 0;
+ unsigned FRONT_PORCH = 0, HSYNC_PIXELS = 0, ACTIVE_LINES = 0,
+ INTERLACE_MODE = 0, TOTAL_LINES = 0, SOF_LINES = 0,
+ VSYNC_LINES = 0;
+ unsigned LINES_F0 = 0, LINES_F1 = 0, BACK_PORCH = 0;
+
+ unsigned long total_pixels_venc = 0;
+ unsigned long active_pixels_venc = 0;
+ unsigned long front_porch_venc = 0;
+ unsigned long hsync_pixels_venc = 0;
+
+ unsigned long de_h_begin = 0, de_h_end = 0;
+ unsigned long de_v_begin_even = 0, de_v_end_even = 0;
+ unsigned long hs_begin = 0, hs_end = 0;
+ unsigned long vs_adjust = 0;
+ unsigned long vs_bline_evn = 0, vs_eline_evn = 0;
+ unsigned long vso_begin_evn = 0;
+
+
+ switch (vic) {
+ case HDMI_720x480p60_16x9:
+ case HDMI_720x480p120_16x9:
+ case HDMI_720x480p60_4x3:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (480/(1+INTERLACE_MODE));
+ LINES_F0 = 525;
+ LINES_F1 = 525;
+ FRONT_PORCH = 16;
+ HSYNC_PIXELS = 62;
+ BACK_PORCH = 60;
+ VSYNC_LINES = 6;
+ SOF_LINES = 30;
+ break;
+ case HDMI_720x576p50_16x9:
+ case HDMI_720x576p100_16x9:
+ case HDMI_720x576p50_4x3:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (576/(1+INTERLACE_MODE));
+ LINES_F0 = 625;
+ LINES_F1 = 625;
+ FRONT_PORCH = 12;
+ HSYNC_PIXELS = 64;
+ BACK_PORCH = 68;
+ VSYNC_LINES = 5;
+ SOF_LINES = 39;
+ break;
+ case HDMI_1280x720p60_16x9:
+ case HDMI_1280x720p120_16x9:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (720/(1+INTERLACE_MODE));
+ LINES_F0 = 750;
+ LINES_F1 = 750;
+ FRONT_PORCH = 110;
+ HSYNC_PIXELS = 40;
+ BACK_PORCH = 220;
+ VSYNC_LINES = 5;
+ SOF_LINES = 20;
+ break;
+ case HDMI_1280x720p50_16x9:
+ case HDMI_1280x720p100_16x9:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (720/(1+INTERLACE_MODE));
+ LINES_F0 = 750;
+ LINES_F1 = 750;
+ FRONT_PORCH = 440;
+ HSYNC_PIXELS = 40;
+ BACK_PORCH = 220;
+ VSYNC_LINES = 5;
+ SOF_LINES = 20;
+ break;
+ case HDMI_1920x1080p50_16x9:
+ case HDMI_1920x1080p25_16x9:
+ case HDMI_1920x1080p100_16x9:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (1080/(1+INTERLACE_MODE));
+ LINES_F0 = 1125;
+ LINES_F1 = 1125;
+ FRONT_PORCH = 528;
+ HSYNC_PIXELS = 44;
+ BACK_PORCH = 148;
+ VSYNC_LINES = 5;
+ SOF_LINES = 36;
+ break;
+ case HDMI_1920x1080p24_16x9:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (1080/(1+INTERLACE_MODE));
+ LINES_F0 = 1125;
+ LINES_F1 = 1125;
+ FRONT_PORCH = 638;
+ HSYNC_PIXELS = 44;
+ BACK_PORCH = 148;
+ VSYNC_LINES = 5;
+ SOF_LINES = 36;
+ break;
+ case HDMI_1920x1080p60_16x9:
+ case HDMI_1920x1080p30_16x9:
+ case HDMI_1920x1080p120_16x9:
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI));
+ ACTIVE_LINES = (1080/(1+INTERLACE_MODE));
+ LINES_F0 = 1125;
+ LINES_F1 = 1125;
+ FRONT_PORCH = 88;
+ HSYNC_PIXELS = 44;
+ BACK_PORCH = 148;
+ VSYNC_LINES = 5;
+ SOF_LINES = 36;
+ break;
+ default:
+ break;
+ }
+
+ TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS);
+ TOTAL_LINES = (LINES_F0+(LINES_F1*INTERLACE_MODE));
+
+ total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
+ (1+PIXEL_REPEAT_VENC);
+ active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
+ (1+PIXEL_REPEAT_VENC);
+ front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) *
+ (1+PIXEL_REPEAT_VENC);
+ hsync_pixels_venc = (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
+ (1+PIXEL_REPEAT_VENC);
+
+ hd_write_reg(P_ENCP_VIDEO_MODE, hd_read_reg(P_ENCP_VIDEO_MODE)|(1<<14));
+ /* Program DE timing */
+ de_h_begin = modulo(hd_read_reg(P_ENCP_VIDEO_HAVON_BEGIN) +
+ VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc);
+ de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc);
+ hd_write_reg(P_ENCP_DE_H_BEGIN, de_h_begin); /* 220 */
+ hd_write_reg(P_ENCP_DE_H_END, de_h_end); /* 1660 */
+ /* Program DE timing for even field */
+ de_v_begin_even = hd_read_reg(P_ENCP_VIDEO_VAVON_BLINE);
+ de_v_end_even = de_v_begin_even + ACTIVE_LINES;
+ hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even);
+ hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even); /* 522 */
+
+ /* Program Hsync timing */
+ if (de_h_end + front_porch_venc >= total_pixels_venc) {
+ hs_begin = de_h_end + front_porch_venc - total_pixels_venc;
+ vs_adjust = 1;
+ } else {
+ hs_begin = de_h_end + front_porch_venc;
+ vs_adjust = 0;
+ }
+ hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc);
+ hd_write_reg(P_ENCP_DVI_HSO_BEGIN, hs_begin);
+ hd_write_reg(P_ENCP_DVI_HSO_END, hs_end);
+
+ /* Program Vsync timing for even field */
+ if (de_v_begin_even >= SOF_LINES + VSYNC_LINES + (1-vs_adjust))
+ vs_bline_evn = de_v_begin_even - SOF_LINES - VSYNC_LINES -
+ (1-vs_adjust);
+ else
+ vs_bline_evn = TOTAL_LINES + de_v_begin_even - SOF_LINES -
+ VSYNC_LINES - (1-vs_adjust);
+ vs_eline_evn = modulo(vs_bline_evn + VSYNC_LINES, TOTAL_LINES);
+ hd_write_reg(P_ENCP_DVI_VSO_BLINE_EVN, vs_bline_evn); /* 5 */
+ hd_write_reg(P_ENCP_DVI_VSO_ELINE_EVN, vs_eline_evn); /* 11 */
+ vso_begin_evn = hs_begin; /* 1692 */
+ hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn); /* 1692 */
+ hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn); /* 1692 */
+
+ switch (vic) {
+ case HDMI_720x480i60_16x9:
+ case HDMI_720x576i50_16x9:
+ case HDMI_720x480i60_4x3:
+ case HDMI_720x576i50_4x3:
+ hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
+ (0 << 1) |
+ (0 << 2) |
+ (0 << 3) |
+ (0 << 4) |
+ (4 << 5) |
+ (1 << 8) |
+ (1 << 12)
+ );
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 0, 1);
+ break;
+ case HDMI_1920x1080i60_16x9:
+ case HDMI_1920x1080i50_16x9:
+ hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
+ (0 << 1) |
+ (HSYNC_POLARITY << 2) |
+ (VSYNC_POLARITY << 3) |
+ (0 << 4) |
+ (((TX_INPUT_COLOR_FORMAT == 0) ? 1 : 0) << 5) |
+ (0 << 8) |
+ (0 << 12)
+ );
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
+ break;
+ case HDMI_3840x2160p30_16x9:
+ case HDMI_3840x2160p25_16x9:
+ case HDMI_3840x2160p24_16x9:
+ case HDMI_4096x2160p24_256x135:
+ case HDMI_4096x2160p25_256x135:
+ case HDMI_4096x2160p30_256x135:
+ case HDMI_4096x2160p50_256x135:
+ case HDMI_4096x2160p60_256x135:
+ case HDMI_3840x2160p50_16x9:
+ case HDMI_3840x2160p60_16x9:
+ hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
+ (0 << 1) |
+ (HSYNC_POLARITY << 2) |
+ (VSYNC_POLARITY << 3) |
+ (0 << 4) |
+ (4 << 5) |
+ (0 << 8) |
+ (0 << 12)
+ );
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
+ break;
+ case HDMI_720x480p60_16x9:
+ case HDMI_720x576p50_16x9:
+ case HDMI_720x480p60_4x3:
+ case HDMI_720x576p50_4x3:
+ case HDMI_720x480p120_16x9:
+ case HDMI_720x576p100_16x9:
+ hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
+ (0 << 1) |
+ (0 << 2) |
+ (0 << 3) |
+ (0 << 4) |
+ (4 << 5) |
+ (0 << 8) |
+ (0 << 12)
+ );
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
+ break;
+ case HDMI_1280x720p60_16x9:
+ case HDMI_1280x720p50_16x9:
+ case HDMI_1280x720p100_16x9:
+ case HDMI_1280x720p120_16x9:
+ hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
+ (0 << 1) |
+ (HSYNC_POLARITY << 2) |
+ (VSYNC_POLARITY << 3) |
+ (0 << 4) |
+ (4 << 5) |
+ (0 << 8) |
+ (0 << 12)
+ );
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
+ break;
+ default:
+ hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
+ (0 << 1) | /* [ 1] src_sel_encp */
+ (HSYNC_POLARITY << 2) |
+ (VSYNC_POLARITY << 3) |
+ (0 << 4) |
+ (4 << 5) |
+ (0 << 8) |
+ (0 << 12)
+ );
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
+ }
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
+}
+
+static void hdmi_tvenc_vesa_set(enum hdmi_vic vic)
+{
+ unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2;
+ unsigned long TOTAL_PIXELS = 0, PIXEL_REPEAT_HDMI = 0,
+ PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 0;
+ unsigned FRONT_PORCH = 0, HSYNC_PIXELS = 0, ACTIVE_LINES = 0,
+ INTERLACE_MODE = 0, TOTAL_LINES = 0, SOF_LINES = 0,
+ VSYNC_LINES = 0;
+ unsigned LINES_F0 = 0, LINES_F1 = 0, BACK_PORCH = 0;
+
+ unsigned long total_pixels_venc = 0;
+ unsigned long active_pixels_venc = 0;
+ unsigned long front_porch_venc = 0;
+ unsigned long hsync_pixels_venc = 0;
+
+ unsigned long de_h_begin = 0, de_h_end = 0;
+ unsigned long de_v_begin_even = 0, de_v_end_even = 0;
+ unsigned long hs_begin = 0, hs_end = 0;
+ unsigned long vs_adjust = 0;
+ unsigned long vs_bline_evn = 0, vs_eline_evn = 0;
+ unsigned long vso_begin_evn = 0;
+ struct hdmi_format_para *vpara = NULL;
+ struct hdmi_cea_timing *vtiming = NULL;
+
+ vpara = hdmi_get_fmt_paras(vic);
+ if (vpara == NULL) {
+ printf("hdmitx: don't find Paras for VESA %d\n", vic);
+ return;
+ } else
+ vtiming = &vpara->timing;
+
+ INTERLACE_MODE = 0;
+ PIXEL_REPEAT_VENC = 0;
+ PIXEL_REPEAT_HDMI = 0;
+ ACTIVE_PIXELS = vtiming->h_active;
+ ACTIVE_LINES = vtiming->v_active;
+ LINES_F0 = vtiming->v_total;
+ LINES_F1 = vtiming->v_total;
+ FRONT_PORCH = vtiming->h_front;
+ HSYNC_PIXELS = vtiming->h_sync;
+ BACK_PORCH = vtiming->h_back;
+ VSYNC_LINES = vtiming->v_sync;
+ SOF_LINES = vtiming->v_back;
+
+ TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS);
+ TOTAL_LINES = (LINES_F0+(LINES_F1*INTERLACE_MODE));
+
+ total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
+ (1+PIXEL_REPEAT_VENC);
+ active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
+ (1+PIXEL_REPEAT_VENC);
+ front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) *
+ (1+PIXEL_REPEAT_VENC);
+ hsync_pixels_venc = (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
+ (1+PIXEL_REPEAT_VENC);
+
+ hd_write_reg(P_ENCP_VIDEO_MODE, hd_read_reg(P_ENCP_VIDEO_MODE)|(1<<14));
+ /* Program DE timing */
+ de_h_begin = modulo(hd_read_reg(P_ENCP_VIDEO_HAVON_BEGIN) +
+ VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc);
+ de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc);
+ hd_write_reg(P_ENCP_DE_H_BEGIN, de_h_begin); /* 220 */
+ hd_write_reg(P_ENCP_DE_H_END, de_h_end); /* 1660 */
+ /* Program DE timing for even field */
+ de_v_begin_even = hd_read_reg(P_ENCP_VIDEO_VAVON_BLINE);
+ de_v_end_even = de_v_begin_even + ACTIVE_LINES;
+ hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even);
+ hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even); /* 522 */
+
+ /* Program Hsync timing */
+ if (de_h_end + front_porch_venc >= total_pixels_venc) {
+ hs_begin = de_h_end + front_porch_venc - total_pixels_venc;
+ vs_adjust = 1;
+ } else {
+ hs_begin = de_h_end + front_porch_venc;
+ vs_adjust = 0;
+ }
+ hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc);
+ hd_write_reg(P_ENCP_DVI_HSO_BEGIN, hs_begin);
+ hd_write_reg(P_ENCP_DVI_HSO_END, hs_end);
+
+ /* Program Vsync timing for even field */
+ if (de_v_begin_even >= SOF_LINES + VSYNC_LINES + (1-vs_adjust))
+ vs_bline_evn = de_v_begin_even - SOF_LINES - VSYNC_LINES -
+ (1-vs_adjust);
+ else
+ vs_bline_evn = TOTAL_LINES + de_v_begin_even - SOF_LINES -
+ VSYNC_LINES - (1-vs_adjust);
+ vs_eline_evn = modulo(vs_bline_evn + VSYNC_LINES, TOTAL_LINES);
+ hd_write_reg(P_ENCP_DVI_VSO_BLINE_EVN, vs_bline_evn); /* 5 */
+ hd_write_reg(P_ENCP_DVI_VSO_ELINE_EVN, vs_eline_evn); /* 11 */
+ vso_begin_evn = hs_begin; /* 1692 */
+ hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn); /* 1692 */
+ hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn); /* 1692 */
+
+ switch (vic) {
+ case HDMIV_640x480p60hz:
+ hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
+ (0 << 1) |
+ (0 << 2) |
+ (0 << 3) |
+ (0 << 4) |
+ (4 << 5) |
+ (0 << 8) |
+ (0 << 12)
+ );
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
+ break;
+ default:
+ hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
+ (0 << 1) | /* [ 1] src_sel_encp */
+ (HSYNC_POLARITY << 2) |
+ (VSYNC_POLARITY << 3) |
+ (0 << 4) |
+ (4 << 5) |
+ (0 << 8) |
+ (0 << 12)
+ );
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
+ }
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
+}
+
+static void hdmi_tvenc_set(enum hdmi_vic vic)
+{
+ if ((vic & HDMITX_VESA_OFFSET) == HDMITX_VESA_OFFSET) {
+ /* VESA modes setting */
+ hdmi_tvenc_vesa_set(vic);
+ return;
+ }
+
+ switch (vic) {
+ case HDMI_720x480i60_16x9:
+ case HDMI_720x576i50_16x9:
+ case HDMI_720x480i60_4x3:
+ case HDMI_720x576i50_4x3:
+ hdmi_tvenc480i_set(vic);
+ break;
+ case HDMI_1920x1080i60_16x9:
+ case HDMI_1920x1080i50_16x9:
+ case HDMI_1920x1080i100_16x9:
+ case HDMI_1920x1080i120_16x9:
+ hdmi_tvenc1080i_set(vic);
+ break;
+ case HDMI_3840x2160p30_16x9:
+ case HDMI_3840x2160p25_16x9:
+ case HDMI_3840x2160p24_16x9:
+ case HDMI_4096x2160p24_256x135:
+ case HDMI_4096x2160p25_256x135:
+ case HDMI_4096x2160p30_256x135:
+ case HDMI_4096x2160p50_256x135:
+ case HDMI_4096x2160p60_256x135:
+ case HDMI_3840x2160p50_16x9:
+ case HDMI_3840x2160p60_16x9:
+ case HDMI_4096x2160p50_256x135_Y420:
+ case HDMI_4096x2160p60_256x135_Y420:
+ case HDMI_3840x2160p50_16x9_Y420:
+ case HDMI_3840x2160p60_16x9_Y420:
+ hdmi_tvenc4k2k_set(vic);
+ break;
+ default:
+ hdmi_tvenc_set_def(vic);
+ break;
+ }
+
+ switch (vic) {
+ case HDMI_720x480i60_16x9:
+ case HDMI_720x576i50_16x9:
+ case HDMI_720x480i60_4x3:
+ case HDMI_720x576i50_4x3:
+ /* Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/
+ hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /* [ 0] src_sel_enci*/
+ (0 << 1) | /* [ 1] src_sel_encp*/
+ (0 << 2) | /* [ 2] inv_hsync. 1=Invert Hsync polarity.*/
+ (0 << 3) | /* [ 3] inv_vsync. 1=Invert Vsync polarity.*/
+ (0 << 4) | /* [ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/
+ (4 << 5) | /* [ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/
+ /* 0=output CrYCb(BRG);*/
+ /* 1=output YCbCr(RGB);*/
+ /* 2=output YCrCb(RBG);*/
+ /* 3=output CbCrY(GBR);*/
+ /* 4=output CbYCr(GRB);*/
+ /* 5=output CrCbY(BGR);*/
+ /* 6,7=Rsrv.*/
+ (1 << 8) | /* [11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/
+ (1 <<12) /* [15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/
+ );
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 0, 1); // [ 0] src_sel_enci: Enable ENCI output to HDMI*/
+ break;
+ case HDMI_1920x1080i60_16x9:
+ case HDMI_1920x1080i50_16x9:
+ case HDMI_1920x1080i100_16x9:
+ case HDMI_1920x1080i120_16x9:
+ /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/
+ hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/
+ (0 << 1) | /*[ 1] src_sel_encp*/
+ (HSYNC_POLARITY << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/
+ (VSYNC_POLARITY << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/
+ (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/
+ (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/
+ /* 0=output CrYCb(BRG);*/
+ /* 1=output YCbCr(RGB);*/
+ /* 2=output YCrCb(RBG);*/
+ /* 3=output CbCrY(GBR);*/
+ /* 4=output CbYCr(GRB);*/
+ /* 5=output CrCbY(BGR);*/
+ /* 6,7=Rsrv.*/
+ (0 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/
+ (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/
+ );
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/
+ break;
+ case HDMI_3840x2160p30_16x9:
+ case HDMI_3840x2160p25_16x9:
+ case HDMI_3840x2160p24_16x9:
+ case HDMI_4096x2160p24_256x135:
+ case HDMI_4096x2160p25_256x135:
+ case HDMI_4096x2160p30_256x135:
+ case HDMI_4096x2160p50_256x135:
+ case HDMI_4096x2160p60_256x135:
+ case HDMI_3840x2160p50_16x9:
+ case HDMI_3840x2160p60_16x9:
+ hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/
+ (0 << 1) | /*[ 1] src_sel_encp*/
+ (HSYNC_POLARITY << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/
+ (VSYNC_POLARITY << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/
+ (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/
+ (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/
+ /* 0=output CrYCb(BRG);*/
+ /* 1=output YCbCr(RGB);*/
+ /* 2=output YCrCb(RBG);*/
+ /* 3=output CbCrY(GBR);*/
+ /* 4=output CbYCr(GRB);*/
+ /* 5=output CrCbY(BGR);*/
+ /* 6,7=Rsrv.*/
+ (0 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/
+ (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/
+ );
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/
+ break;
+ case HDMI_720x480p60_16x9:
+ case HDMI_720x576p50_16x9:
+ case HDMI_720x480p60_4x3:
+ case HDMI_720x576p50_4x3:
+ case HDMI_720x480p120_16x9:
+ case HDMI_720x576p100_16x9:
+ /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/
+ hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/
+ (0 << 1) | /*[ 1] src_sel_encp*/
+ (0 << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/
+ (0 << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/
+ (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/
+ (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/
+ /* 0=output CrYCb(BRG);*/
+ /* 1=output YCbCr(RGB);*/
+ /* 2=output YCrCb(RBG);*/
+ /* 3=output CbCrY(GBR);*/
+ /* 4=output CbYCr(GRB);*/
+ /* 5=output CrCbY(BGR);*/
+ /* 6,7=Rsrv.*/
+ (0 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/
+ (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/
+ );
+ /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/
+ break;
+ case HDMI_1280x720p60_16x9:
+ case HDMI_1280x720p50_16x9:
+ case HDMI_1280x720p100_16x9:
+ case HDMI_1280x720p120_16x9:
+ /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/
+ hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/
+ (0 << 1) | /*[ 1] src_sel_encp*/
+ (HSYNC_POLARITY << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/
+ (VSYNC_POLARITY << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/
+ (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/
+ (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/
+ /* 0=output CrYCb(BRG);*/
+ /* 1=output YCbCr(RGB);*/
+ /* 2=output YCrCb(RBG);*/
+ /* 3=output CbCrY(GBR);*/
+ /* 4=output CbYCr(GRB);*/
+ /* 5=output CrCbY(BGR);*/
+ /* 6,7=Rsrv.*/
+ (0 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/
+ (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/
+ );
+ /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/
+ break;
+ default:
+ /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/
+ hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/
+ (0 << 1) | /*[ 1] src_sel_encp*/
+ (HSYNC_POLARITY << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/
+ (VSYNC_POLARITY << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/
+ (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/
+ (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/
+ /* 0=output CrYCb(BRG);*/
+ /* 1=output YCbCr(RGB);*/
+ /* 2=output YCrCb(RBG);*/
+ /* 3=output CbCrY(GBR);*/
+ /* 4=output CbYCr(GRB);*/
+ /* 5=output CrCbY(BGR);*/
+ /* 6,7=Rsrv.*/
+ (0 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/
+ (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/
+ );
+ if (is_hdmi4k_420(vic)) {
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 8, 1);
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 20, 1);
+ }
+ /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/
+ }
+}
+
+static void hdmitx_set_dith(struct hdmitx_dev* hdev)
+{
+ unsigned int hs_flag = 0;
+
+ switch (hdev->para->cd) {
+ case HDMI_COLOR_DEPTH_30B:
+ case HDMI_COLOR_DEPTH_36B:
+ case HDMI_COLOR_DEPTH_48B:
+ /* 12-10 dithering on */
+ hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 0, 4, 1);
+ hs_flag = (hd_read_reg(P_VPU_HDMI_SETTING) >> 2) & 0x3;
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 2, 2);
+ /* 12-10 rounding off */
+ hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 0, 10, 1);
+ /* 10-8 dithering off (2x2 old dither) */
+ hd_set_reg_bits(P_VPU_HDMI_DITH_CNTL, 0, 4, 1);
+ /* set hsync/vsync */
+ hd_set_reg_bits(P_VPU_HDMI_DITH_CNTL, hs_flag, 2, 2);
+ break;
+ default:
+ /* 12-10 dithering off */
+ hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 0, 4, 1);
+ /* 12-10 rounding on */
+ hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 1, 10, 1);
+ /* 10-8 dithering on (2x2 old dither) */
+ hd_set_reg_bits(P_VPU_HDMI_DITH_CNTL, 1, 4, 1);
+ /* set hsync/vsync as default 0 */
+ hd_set_reg_bits(P_VPU_HDMI_DITH_CNTL, 0, 2, 2);
+ break;
+ }
+}
+
+static void set_tmds_clk_div40(unsigned int div40)
+{
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
+
+ if (div40 == 1) {
+ hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_01, 0); /*[25:16] tmds_clk_pttn[19:10] [ 9: 0] tmds_clk_pttn[ 9: 0]*/
+ hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_23, 0x03ff03ff); /*[25:16] tmds_clk_pttn[39:30] [ 9: 0] tmds_clk_pttn[29:20]*/
+ } else {
+ hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_01, 0x001f001f);
+ hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_23, 0x001f001f);
+ }
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_SCRAMBLER_CTRL, (div40 == 1) ? 1 : 0, 0, 1);
+
+ hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1); /*0xc*/
+ msleep(2);
+ hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2); /*0xc*/
+ if (hdev->RXCap.scdc_present)
+ scdc_prepare((div40 == 1) ? 1:0);
+}
+
+static void hdmitx_set_vsi_pkt(enum hdmi_vic vic)
+{
+ /* convert to HDMI_VIC */
+ if (vic == HDMI_3840x2160p30_16x9)
+ vic = 1;
+ else if (vic == HDMI_3840x2160p25_16x9)
+ vic = 2;
+ else if (vic == HDMI_3840x2160p24_16x9)
+ vic = 3;
+ else
+ vic = 4;
+
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID0, 0x03);
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID1, 0x0c);
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID2, 0x00);
+ hdmitx_wr_reg(HDMITX_DWC_FC_AVIVID, 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD0, 0x20);
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD1, vic);
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDSIZE, 5);
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO0, 1, 3, 1);
+ hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO1, 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO2, 0x10);
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_PACKET_TX_EN, 1, 4, 1);
+}
+
+static void hdmitx_set_packet(int type, unsigned char *DB, unsigned char *HB)
+{
+ unsigned int i;
+
+ switch (type) {
+ case HDMI_PACKET_VEND:
+ if ((!DB) || (!HB)) {
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO0, 0, 3, 1);
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDSIZE, 0x0);
+ return;
+ }
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID0, DB[0]);
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID1, DB[1]);
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID2, DB[2]);
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD0, DB[3]);
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDSIZE, HB[2]);
+ if (DB[3] == 0x20) { /* set HDMI VIC */
+ hdmitx_wr_reg(HDMITX_DWC_FC_AVIVID, 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD1, DB[4]);
+ }
+ if (HB[2] == 0x1b) {/*set dolby vsif data information*/
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD1, DB[4]);
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD2, DB[5]);
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD3, DB[6]);
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD4, DB[7]);
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD5, DB[8]);
+ }
+
+ /*set hdr 10+ vsif data information*/
+ if ((DB[0] == 0x8b) && (DB[1] == 0x84) && (DB[2] == 0x90)) {
+ for (i = 0; i < 23; i++)
+ hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD1 + i,
+ DB[4 + i]);
+ }
+
+ /* Enable VSI packet */
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO0, 1, 3, 1);
+ hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO1, 0);
+ hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO2, 0x10);
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_PACKET_TX_EN, 1, 4, 1);
+ break;
+ case HDMI_PACKET_DRM:
+ if ((!DB) || (!HB)) {
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO3, 0, 6, 1);
+ hdmitx_set_reg_bits(
+ HDMITX_DWC_FC_PACKET_TX_EN, 0, 7, 1);
+ return;
+ }
+ /* Ignore HB[0] */
+ hdmitx_wr_reg(HDMITX_DWC_FC_DRM_HB01, HB[1]);
+ hdmitx_wr_reg(HDMITX_DWC_FC_DRM_HB02, HB[2]);
+ for (i = 0; i < 26; i++)
+ hdmitx_wr_reg(HDMITX_DWC_FC_DRM_PB00 + i, DB[i]);
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO3, 1, 6, 1);
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_PACKET_TX_EN, 1, 7, 1);
+ break;
+ default:
+ break;
+ }
+}
+
+static int hdmitx_cntl_config(struct hdmitx_dev *hdev, unsigned int cmd,
+ unsigned int argv)
+{
+ int ret = 0;
+
+ switch (cmd) {
+ case CONF_AVI_BT2020:
+ if (argv == SET_AVI_BT2020) {
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 3, 6, 2);
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF2, 6, 4, 3);
+ }
+ if (argv == CLR_AVI_BT2020) {/*bt709*/
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 2, 6, 2);
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF2, 0, 4, 3);
+ }
+ break;
+ case CONF_AVI_RGBYCC_INDIC:
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF0, argv, 0, 2);
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF0, 0, 7, 1);
+ break;
+ case CONF_AVI_Q01:
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF2, argv, 2, 2);
+ break;
+ case CONF_AVI_YQ01:
+ hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF3, argv, 2, 2);
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+
+#define GET_LOW8BIT(a) ((a) & 0xff)
+#define GET_HIGH8BIT(a) (((a) >> 8) & 0xff)
+void hdmitx_set_drm_pkt(struct master_display_info_s *data)
+{
+ struct hdmitx_dev *hdev = &hdmitx_device;
+ unsigned char DRM_HB[3] = {0x87, 0x1, 26};
+ unsigned char DRM_DB[26] = {0x0};
+ unsigned int hdr_transfer_feature = 0;
+ unsigned int hdr_color_feature = 0;
+ unsigned int hdr_mode = 0;
+ /*
+ *hdr_color_feature: bit 23-16: color_primaries
+ * 1:bt709 0x9:bt2020
+ *hdr_transfer_feature: bit 15-8: transfer_characteristic
+ * 1:bt709 0xe:bt2020-10 0x10:smpte-st-2084 0x12:hlg(todo)
+ */
+ if (NULL == data) {
+ return;
+ }
+ hdr_transfer_feature = (data->features >> 8) & 0xff;
+ hdr_color_feature = (data->features >> 16) & 0xff;
+ DRM_DB[1] = 0x0;
+ DRM_DB[2] = GET_LOW8BIT(data->primaries[0][0]);
+ DRM_DB[3] = GET_HIGH8BIT(data->primaries[0][0]);
+ DRM_DB[4] = GET_LOW8BIT(data->primaries[0][1]);
+ DRM_DB[5] = GET_HIGH8BIT(data->primaries[0][1]);
+ DRM_DB[6] = GET_LOW8BIT(data->primaries[1][0]);
+ DRM_DB[7] = GET_HIGH8BIT(data->primaries[1][0]);
+ DRM_DB[8] = GET_LOW8BIT(data->primaries[1][1]);
+ DRM_DB[9] = GET_HIGH8BIT(data->primaries[1][1]);
+ DRM_DB[10] = GET_LOW8BIT(data->primaries[2][0]);
+ DRM_DB[11] = GET_HIGH8BIT(data->primaries[2][0]);
+ DRM_DB[12] = GET_LOW8BIT(data->primaries[2][1]);
+ DRM_DB[13] = GET_HIGH8BIT(data->primaries[2][1]);
+ DRM_DB[14] = GET_LOW8BIT(data->white_point[0]);
+ DRM_DB[15] = GET_HIGH8BIT(data->white_point[0]);
+ DRM_DB[16] = GET_LOW8BIT(data->white_point[1]);
+ DRM_DB[17] = GET_HIGH8BIT(data->white_point[1]);
+ DRM_DB[18] = GET_LOW8BIT(data->luminance[0]);
+ DRM_DB[19] = GET_HIGH8BIT(data->luminance[0]);
+ DRM_DB[20] = GET_LOW8BIT(data->luminance[1]);
+ DRM_DB[21] = GET_HIGH8BIT(data->luminance[1]);
+ DRM_DB[22] = GET_LOW8BIT(data->max_content);
+ DRM_DB[23] = GET_HIGH8BIT(data->max_content);
+ DRM_DB[24] = GET_LOW8BIT(data->max_frame_average);
+ DRM_DB[25] = GET_HIGH8BIT(data->max_frame_average);
+
+
+ /* SMPTE ST 2084 and (BT2020 or NON_STANDARD) */
+ if (hdr_transfer_feature == T_SMPTE_ST_2084 &&
+ hdr_color_feature == C_BT2020)
+ hdr_mode = 1;
+ else if (hdr_transfer_feature == T_SMPTE_ST_2084 &&
+ hdr_color_feature != C_BT2020)
+ hdr_mode = 2;
+
+ /*HLG and BT2020*/
+ if (hdr_color_feature == C_BT2020 &&
+ (hdr_transfer_feature == T_BT2020_10 ||
+ hdr_transfer_feature == T_HLG))
+ hdr_mode = 3;
+
+ switch (hdr_mode) {
+ case 1:
+ /*standard HDR*/
+ DRM_DB[0] = 0x02; /* SMPTE ST 2084 */
+ hdmitx_set_packet(HDMI_PACKET_DRM, DRM_DB, DRM_HB);
+ hdmitx_cntl_config(hdev, CONF_AVI_BT2020, SET_AVI_BT2020);
+ break;
+ case 2:
+ /*non standard*/
+ DRM_DB[0] = 0x02; /* no standard SMPTE ST 2084 */
+ hdmitx_set_packet(HDMI_PACKET_DRM, DRM_DB, DRM_HB);
+ hdmitx_cntl_config(hdev, CONF_AVI_BT2020, CLR_AVI_BT2020);
+ break;
+ case 3:
+ /*HLG*/
+ DRM_DB[0] = 0x03;/* HLG is 0x03 */
+ hdmitx_set_packet(HDMI_PACKET_DRM, DRM_DB, DRM_HB);
+ hdmitx_cntl_config(hdev, CONF_AVI_BT2020, SET_AVI_BT2020);
+ break;
+ case 0:
+ default:
+ /*other case*/
+ hdmitx_set_packet(HDMI_PACKET_DRM, NULL, NULL);
+ hdmitx_cntl_config(hdev, CONF_AVI_BT2020, CLR_AVI_BT2020);
+ break;
+ }
+}
+
+void hdmitx_set_vsif_pkt(enum eotf_type type,
+ enum mode_type tunnel_mode, struct dv_vsif_para *data)
+{
+ struct hdmitx_dev *hdev = &hdmitx_device;
+ struct dv_vsif_para para = {0};
+ unsigned char VEN_HB[3] = {0x81, 0x01};
+ unsigned char VEN_DB1[24] = {0x00};
+ unsigned char VEN_DB2[27] = {0x00};
+ unsigned char len = 0;
+ unsigned int vic = hdev->vic;
+ unsigned int hdmi_vic_4k_flag = 0;
+
+ if ((hdev->RXCap.dv_info.ieeeoui != DV_IEEE_OUI))
+ return;
+
+ hdev->hdmi_current_eotf_type = type;
+ hdev->hdmi_current_tunnel_mode = tunnel_mode;
+ /*ver0 and ver1_15 and ver1_12bit with ll= 0 use hdmi 1.4b VSIF*/
+ if ((hdev->RXCap.dv_info.ver == 0) || ((hdev->RXCap.dv_info.ver == 1)
+ && (hdev->RXCap.dv_info.length == 0xE))
+ || ((hdev->RXCap.dv_info.ver == 1)
+ && (hdev->RXCap.dv_info.length == 0xB)
+ && (hdev->RXCap.dv_info.low_latency == 0))) {
+ if ((vic == HDMI_3840x2160p30_16x9) ||
+ (vic == HDMI_3840x2160p25_16x9) ||
+ (vic == HDMI_3840x2160p24_16x9) ||
+ (vic == HDMI_4096x2160p24_256x135))
+ hdmi_vic_4k_flag = 1;
+
+ switch (type) {
+ case EOTF_T_DOLBYVISION:
+ len = 0x18;
+ break;
+ case EOTF_T_HDR10:
+ case EOTF_T_SDR:
+ case EOTF_T_NULL:
+ default:
+ len = 0x05;
+ break;
+ }
+
+ VEN_HB[2] = len;
+ VEN_DB1[0] = 0x03;
+ VEN_DB1[1] = 0x0c;
+ VEN_DB1[2] = 0x00;
+ VEN_DB1[3] = 0x00;
+
+ if (hdmi_vic_4k_flag) {
+ VEN_DB1[3] = 0x20;
+ if (vic == HDMI_3840x2160p30_16x9)
+ VEN_DB1[4] = 0x1;
+ else if (vic == HDMI_3840x2160p25_16x9)
+ VEN_DB1[4] = 0x2;
+ else if (vic == HDMI_3840x2160p24_16x9)
+ VEN_DB1[4] = 0x3;
+ else/*vic == HDMI_4096x2160p24_256x135*/
+ VEN_DB1[4] = 0x4;
+ }
+ if (type == EOTF_T_DOLBYVISION) {
+ hdmitx_set_packet(HDMI_PACKET_VEND, VEN_DB1, VEN_HB);
+ hdmitx_cntl_config(hdev, CONF_AVI_BT2020,
+ CLR_AVI_BT2020);/*BT709*/
+ if (tunnel_mode == RGB_8BIT) {
+ hdmitx_cntl_config(hdev,CONF_AVI_RGBYCC_INDIC,
+ HDMI_COLOR_FORMAT_RGB);
+ hdmitx_cntl_config(hdev, CONF_AVI_Q01,
+ RGB_RANGE_FUL);
+ } else {
+ hdmitx_cntl_config(hdev, CONF_AVI_RGBYCC_INDIC,
+ HDMI_COLOR_FORMAT_422);
+ hdmitx_cntl_config(hdev, CONF_AVI_YQ01,
+ YCC_RANGE_FUL);
+ }
+ } else {
+ if (hdmi_vic_4k_flag)
+ hdmitx_set_packet(HDMI_PACKET_VEND, VEN_DB1, VEN_HB);
+ else
+ hdmitx_set_packet(HDMI_PACKET_VEND, NULL, NULL);
+ hdmitx_cntl_config(hdev, CONF_AVI_RGBYCC_INDIC,
+ hdev->para->cs);
+ hdmitx_cntl_config(hdev, CONF_AVI_Q01, RGB_RANGE_LIM);
+ hdmitx_cntl_config(hdev, CONF_AVI_YQ01,
+ YCC_RANGE_LIM);
+ hdmitx_cntl_config(hdev, CONF_AVI_BT2020,
+ CLR_AVI_BT2020);/*BT709*/
+ }
+
+ }
+ /*ver1_12 with low_latency = 1 and ver2 use Dolby VSIF*/
+ if ((hdev->RXCap.dv_info.ver == 2) || ((hdev->RXCap.dv_info.ver == 1)
+ && (hdev->RXCap.dv_info.length == 0xB)
+ && (hdev->RXCap.dv_info.low_latency == 1))
+ || (type == EOTF_T_LL_MODE)) {
+
+ if (data == NULL)
+ data = ¶
+ /*4k vsif package */
+ if ((vic == HDMI_3840x2160p30_16x9) ||
+ (vic == HDMI_3840x2160p25_16x9) ||
+ (vic == HDMI_3840x2160p24_16x9) ||
+ (vic == HDMI_4096x2160p24_256x135))
+ hdmi_vic_4k_flag = 1;
+
+ switch (type) {
+ case EOTF_T_DOLBYVISION:
+ case EOTF_T_LL_MODE:
+ len = 0x1b;
+ break;
+ case EOTF_T_HDR10:
+ case EOTF_T_SDR:
+ case EOTF_T_NULL:
+ default:
+ len = 0x5;
+ break;
+ }
+ VEN_HB[2] = len;
+ VEN_DB2[0] = 0x46;
+ VEN_DB2[1] = 0xd0;
+ VEN_DB2[2] = 0x00;
+ VEN_DB2[3] = (data->vers.ver2.low_latency) |
+ (data->vers.ver2.dobly_vision_signal << 1);
+ VEN_DB2[4] = (data->vers.ver2.eff_tmax_PQ_hi)
+ | (data->vers.ver2.auxiliary_MD_present << 6)
+ | (data->vers.ver2.backlt_ctrl_MD_present << 7);
+ VEN_DB2[5] = data->vers.ver2.eff_tmax_PQ_low;
+ VEN_DB2[6] = data->vers.ver2.auxiliary_runmode;
+ VEN_DB2[7] = data->vers.ver2.auxiliary_runversion;
+ VEN_DB2[8] = data->vers.ver2.auxiliary_debug0;
+
+ /*Dolby Vision standard case*/
+ if (type == EOTF_T_DOLBYVISION) {
+ hdmitx_set_packet(HDMI_PACKET_VEND, VEN_DB2, VEN_HB);
+ hdmitx_cntl_config(hdev, CONF_AVI_BT2020,
+ CLR_AVI_BT2020);/*BT709*/
+ if (tunnel_mode == RGB_8BIT) {/*RGB444*/
+ hdmitx_cntl_config(hdev, CONF_AVI_RGBYCC_INDIC,
+ HDMI_COLOR_FORMAT_RGB);
+ hdmitx_cntl_config(hdev, CONF_AVI_Q01,
+ RGB_RANGE_FUL);
+ } else {/*YUV422*/
+ hdmitx_cntl_config(hdev, CONF_AVI_RGBYCC_INDIC,
+ HDMI_COLOR_FORMAT_422);
+ hdmitx_cntl_config(hdev, CONF_AVI_YQ01,
+ YCC_RANGE_FUL);
+ }
+ }
+ /*Dolby Vision low-latency case*/
+ else if (type == EOTF_T_LL_MODE) {
+ hdmitx_set_packet(HDMI_PACKET_VEND, VEN_DB2, VEN_HB);
+ if (hdev->RXCap.colorimetry_data & 0xe0)
+ /*if RX support BT2020, then output BT2020*/
+ hdmitx_cntl_config(hdev, CONF_AVI_BT2020,
+ SET_AVI_BT2020);/*BT2020*/
+ else
+ hdmitx_cntl_config(hdev, CONF_AVI_BT2020,
+ CLR_AVI_BT2020);/*BT709*/
+ if (tunnel_mode == RGB_10_12BIT) {/*10/12bit RGB444*/
+ hdmitx_cntl_config(hdev, CONF_AVI_RGBYCC_INDIC,
+ HDMI_COLOR_FORMAT_RGB);
+ hdmitx_cntl_config(hdev, CONF_AVI_Q01,
+ RGB_RANGE_LIM);
+ } else if (tunnel_mode == YUV444_10_12BIT) {
+ /*10/12bit YUV444*/
+ hdmitx_cntl_config(hdev,
+ CONF_AVI_RGBYCC_INDIC,
+ HDMI_COLOR_FORMAT_444);
+ hdmitx_cntl_config(hdev, CONF_AVI_YQ01,
+ YCC_RANGE_LIM);
+ } else {/*YUV422*/
+ hdmitx_cntl_config(hdev,
+ CONF_AVI_RGBYCC_INDIC,
+ HDMI_COLOR_FORMAT_422);
+ hdmitx_cntl_config(hdev, CONF_AVI_YQ01,
+ YCC_RANGE_LIM);
+ }
+ }
+ /*SDR case*/
+ else {
+ if (hdmi_vic_4k_flag) {
+ VEN_DB1[0] = 0x03;
+ VEN_DB1[1] = 0x0c;
+ VEN_DB1[2] = 0x00;
+ hdmitx_set_packet(HDMI_PACKET_VEND,
+ VEN_DB2, VEN_HB);
+ } else
+ hdmitx_set_packet(HDMI_PACKET_VEND,
+ NULL, NULL);
+ hdmitx_cntl_config(hdev,
+ CONF_AVI_RGBYCC_INDIC, hdev->para->cs);
+ hdmitx_cntl_config(hdev,
+ CONF_AVI_Q01, RGB_RANGE_LIM);
+ hdmitx_cntl_config(hdev,
+ CONF_AVI_YQ01, YCC_RANGE_LIM);
+ hdmitx_cntl_config(hdev, CONF_AVI_BT2020,
+ CLR_AVI_BT2020);/*BT709*/
+ }
+ }
+}
+
+void hdmitx_set_hdr10plus_pkt(unsigned int flag,
+ struct hdr10plus_para *data)
+{
+ struct hdmitx_dev *hdev = &hdmitx_device;
+ unsigned char VEN_HB[3] = {0x81, 0x01, 0x1b};
+ unsigned char VEN_DB[27] = {0x00};
+
+ if ((!data) || (!flag)) {
+ hdmitx_set_packet(HDMI_PACKET_VEND, NULL, NULL);
+ hdmitx_cntl_config(hdev, CONF_AVI_BT2020,
+ CLR_AVI_BT2020);
+ return;
+ }
+
+ VEN_DB[0] = 0x8b;
+ VEN_DB[1] = 0x84;
+ VEN_DB[2] = 0x90;
+
+ VEN_DB[3] = ((data->application_version & 0x3) << 6) |
+ ((data->targeted_max_lum & 0x1f) << 1);
+ VEN_DB[4] = data->average_maxrgb;
+ VEN_DB[5] = data->distribution_values[0];
+ VEN_DB[6] = data->distribution_values[1];
+ VEN_DB[7] = data->distribution_values[2];
+ VEN_DB[8] = data->distribution_values[3];
+ VEN_DB[9] = data->distribution_values[4];
+ VEN_DB[10] = data->distribution_values[5];
+ VEN_DB[11] = data->distribution_values[6];
+ VEN_DB[12] = data->distribution_values[7];
+ VEN_DB[13] = data->distribution_values[8];
+ VEN_DB[14] = ((data->num_bezier_curve_anchors & 0xf) << 4) |
+ ((data->knee_point_x >> 6) & 0xf);
+ VEN_DB[15] = ((data->knee_point_x & 0x3f) << 2) |
+ ((data->knee_point_y >> 8) & 0x3);
+ VEN_DB[16] = data->knee_point_y & 0xff;
+ VEN_DB[17] = data->bezier_curve_anchors[0];
+ VEN_DB[18] = data->bezier_curve_anchors[1];
+ VEN_DB[19] = data->bezier_curve_anchors[2];
+ VEN_DB[20] = data->bezier_curve_anchors[3];
+ VEN_DB[21] = data->bezier_curve_anchors[4];
+ VEN_DB[22] = data->bezier_curve_anchors[5];
+ VEN_DB[23] = data->bezier_curve_anchors[6];
+ VEN_DB[24] = data->bezier_curve_anchors[7];
+ VEN_DB[25] = data->bezier_curve_anchors[8];
+ VEN_DB[26] = ((data->graphics_overlay_flag & 0x1) << 7)|
+ ((data->no_delay_flag & 0x1) << 6);
+
+ hdmitx_set_packet(HDMI_PACKET_VEND, VEN_DB, VEN_HB);
+ hdmitx_cntl_config(hdev, CONF_AVI_BT2020,
+ SET_AVI_BT2020);
+
+}
+/* record HDMITX current format */
+/* ISA_DEBUG_REG0 0x2600
+ * bit[11]: Y420
+ * bit[10:8]: HDMI VIC
+ * bit[7:0]: CEA VIC
+ */
+static void save_hdmitx_format(enum hdmi_vic vic, int y420)
+{
+ unsigned int data32;
+
+ data32 = vic & 0xff;
+ data32 |= (hdmitx_rd_reg(HDMITX_DWC_FC_VSDPAYLOAD1) & 0x7) << 8;
+ data32 |= (!!y420) << 11;
+ hd_write_reg(P_SYSCTRL_DEBUG_REG0, data32);
+}
+
+static void hdmitx_set_phy(struct hdmitx_dev *hdev)
+{
+ if (!hdev)
+ return;
+
+ switch (hdev->vic) {
+ case HDMI_3840x2160p50_16x9:
+ case HDMI_3840x2160p60_16x9:
+ case HDMI_4096x2160p50_256x135:
+ case HDMI_4096x2160p60_256x135:
+ if ((hdev->para->cs == HDMI_COLOR_FORMAT_420)
+ && (hdev->para->cd == HDMI_COLOR_DEPTH_24B))
+ hdmitx_set_phypara(HDMI_PHYPARA_3G);
+ else
+ hdmitx_set_phypara(HDMI_PHYPARA_6G);
+ break;
+ case HDMI_3840x2160p50_16x9_Y420:
+ case HDMI_3840x2160p60_16x9_Y420:
+ case HDMI_4096x2160p50_256x135_Y420:
+ case HDMI_4096x2160p60_256x135_Y420:
+ if (hdev->para->cd == HDMI_COLOR_DEPTH_24B)
+ hdmitx_set_phypara(HDMI_PHYPARA_3G);
+ else
+ hdmitx_set_phypara(HDMI_PHYPARA_4p5G);
+ break;
+ case HDMI_3840x2160p24_16x9:
+ case HDMI_3840x2160p24_64x27:
+ case HDMI_3840x2160p25_16x9:
+ case HDMI_3840x2160p25_64x27:
+ case HDMI_3840x2160p30_16x9:
+ case HDMI_3840x2160p30_64x27:
+ case HDMI_4096x2160p24_256x135:
+ case HDMI_4096x2160p25_256x135:
+ case HDMI_4096x2160p30_256x135:
+ if ((hdev->para->cs == HDMI_COLOR_FORMAT_422)
+ || (hdev->para->cd == HDMI_COLOR_DEPTH_24B))
+ hdmitx_set_phypara(HDMI_PHYPARA_3G);
+ else
+ hdmitx_set_phypara(HDMI_PHYPARA_4p5G);
+ break;
+ case HDMI_1920x1080p60_16x9:
+ case HDMI_1920x1080p50_16x9:
+ case HDMI_1920x1080i100_16x9:
+ case HDMI_1920x1080i120_16x9:
+ case HDMI_1280x720p100_16x9:
+ case HDMI_1280x720p120_16x9:
+ hdmitx_set_phypara(HDMI_PHYPARA_DEF);
+ break;
+ default:
+ hdmitx_set_phypara(HDMI_PHYPARA_270M);
+ break;
+ }
+ debug("hdmitx phy setting done\n");
+}
+
+static void hdmitx_set_scdc(struct hdmitx_dev *hdev)
+{
+ switch (hdev->vic) {
+ case HDMI_3840x2160p50_16x9:
+ case HDMI_3840x2160p60_16x9:
+ case HDMI_4096x2160p50_256x135:
+ case HDMI_4096x2160p60_256x135:
+ if ((hdev->para->cs == HDMI_COLOR_FORMAT_420)
+ && (hdev->para->cd == HDMI_COLOR_DEPTH_24B))
+ set_tmds_clk_div40(0);
+ else
+ set_tmds_clk_div40(1);
+ break;
+ case HDMI_3840x2160p50_16x9_Y420:
+ case HDMI_3840x2160p60_16x9_Y420:
+ case HDMI_4096x2160p50_256x135_Y420:
+ case HDMI_4096x2160p60_256x135_Y420:
+ if ((hdev->para->cs == HDMI_COLOR_FORMAT_420)
+ && (hdev->para->cd == HDMI_COLOR_DEPTH_24B))
+ set_tmds_clk_div40(0);
+ else
+ set_tmds_clk_div40(1);
+ break;
+ case HDMI_3840x2160p24_16x9:
+ case HDMI_3840x2160p24_64x27:
+ case HDMI_4096x2160p24_256x135:
+ case HDMI_3840x2160p25_16x9:
+ case HDMI_3840x2160p25_64x27:
+ case HDMI_4096x2160p25_256x135:
+ case HDMI_3840x2160p30_16x9:
+ case HDMI_3840x2160p30_64x27:
+ case HDMI_4096x2160p30_256x135:
+ case HDMI_1920x1080p100_16x9:
+ case HDMI_1920x1080p120_16x9:
+ if ((hdev->para->cs == HDMI_COLOR_FORMAT_422)
+ || (hdev->para->cd == HDMI_COLOR_DEPTH_24B))
+ set_tmds_clk_div40(0);
+ else
+ set_tmds_clk_div40(1);
+ break;
+ default:
+ set_tmds_clk_div40(0);
+ break;
+ }
+}
+
+static void hdmitx_set_hw(struct hdmitx_dev* hdev)
+{
+ struct hdmi_format_para *para = NULL;
+
+ para = hdmi_get_fmt_paras(hdev->vic);
+ if (para == NULL) {
+ printk("error at %s[%d]\n", __func__, __LINE__);
+ return;
+ }
+ hdmitx_set_scdc(hdev);
+ hdmitx_set_pll(hdev);
+ hdmitx_enc(hdev->vic);
+ hdmitx_set_dith(hdev);
+ hdmitx_set_phy(hdev);
+
+ /* --------------------------------------------------------*/
+ /* Set up HDMI*/
+ /* --------------------------------------------------------*/
+ config_hdmi20_tx(hdev, hdev->vic, para, /*pixel_repeat*/
+ hdev->para->cd, /*Pixel bit width: 4=24-bit; 5=30-bit; 6=36-bit; 7=48-bit.*/
+ TX_INPUT_COLOR_FORMAT, /*input_color_format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420.*/
+ TX_INPUT_COLOR_RANGE, /*input_color_range: 0=limited; 1=full.*/
+ hdev->para->cs, /*output_color_format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420.*/
+ TX_OUTPUT_COLOR_RANGE /*output_color_range: 0=limited; 1=full.*/
+ );
+
+ /* switch HDMI_VIC for 2160p30/25/24hz */
+ switch (hdev->vic) {
+ case HDMI_3840x2160p24_16x9:
+ case HDMI_3840x2160p25_16x9:
+ case HDMI_3840x2160p30_16x9:
+ case HDMI_4096x2160p24_256x135:
+ hdmitx_set_vsi_pkt(hdev->vic);
+ break;
+ default:
+ break;
+ }
+
+ /* Using ISA_DEBUG_REG0 to record HDMITX current format */
+ save_hdmitx_format(hdev->vic, (hdev->para->cs == HDMI_COLOR_FORMAT_420));
+
+ hd_write_reg(P_VPU_HDMI_FMT_CTRL,
+ (((TX_INPUT_COLOR_FORMAT==HDMI_COLOR_FORMAT_420)?2:0) << 0) |
+ /*[ 1: 0] hdmi_vid_fmt. 0=444; 1=convert to 422; 2=convert to 420.*/
+ (2 << 2) | /*[ 3: 2] chroma_dnsmp. 0=use pixel 0; 1=use pixel 1; 2=use average.*/
+ (0 << 4) | /*[ 4] dith_en. 1=enable dithering before HDMI TX input.*/
+ (0 << 5) | /*[ 5] hdmi_dith_md: random noise selector.*/
+ (0 << 6)); /*[ 9: 6] hdmi_dith10_cntl.*/
+ if (hdev->para->cs == HDMI_COLOR_FORMAT_420) {
+ hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 2, 0, 2);
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 4, 4);
+ hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 8, 1);
+ }
+ switch (hdev->vic) {
+ case HDMI_720x480i60_16x9:
+ case HDMI_720x576i50_16x9:
+ case HDMI_720x480i60_4x3:
+ case HDMI_720x576i50_4x3:
+ enc_vpu_bridge_reset(0);
+ break;
+ default:
+ enc_vpu_bridge_reset(1);
+ break;
+ }
+ hd_write_reg(P_ENCP_VIDEO_EN, 1); /* enable it finially */
+}
+
+/*Use this self-made function rather than %,
+ *because % appears to produce wrong
+ *value for divisor which are not 2's exponential.
+ */
+static unsigned long modulo(unsigned long a, unsigned long b)
+{
+ if (a >= b) {
+ return(a-b);
+ } else {
+ return(a);
+ }
+}
+
+static signed int to_signed(unsigned int a)
+{
+ if (a <= 7) {
+ return(a);
+ } else {
+ return(a-16);
+ }
+}
+
+static void hdmitx_csc_config (unsigned char input_color_format,
+ unsigned char output_color_format,
+ unsigned char color_depth)
+{
+ unsigned char conv_en;
+ unsigned long csc_coeff_a1, csc_coeff_a2, csc_coeff_a3, csc_coeff_a4;
+ unsigned long csc_coeff_b1, csc_coeff_b2, csc_coeff_b3, csc_coeff_b4;
+ unsigned long csc_coeff_c1, csc_coeff_c2, csc_coeff_c3, csc_coeff_c4;
+ unsigned char csc_scale;
+ unsigned long data32;
+
+ conv_en = (((input_color_format == HDMI_COLOR_FORMAT_RGB) ||
+ (output_color_format == HDMI_COLOR_FORMAT_RGB)) &&
+ ( input_color_format != output_color_format))? 1 : 0;
+
+ if (conv_en) {
+ if (output_color_format == HDMI_COLOR_FORMAT_RGB) {
+ csc_coeff_a1 = 0x2000;
+ csc_coeff_a2 = 0x6926;
+ csc_coeff_a3 = 0x74fd;
+ csc_coeff_a4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x010e :
+ (color_depth==HDMI_COLOR_DEPTH_30B)? 0x043b :
+ (color_depth==HDMI_COLOR_DEPTH_36B)? 0x10ee :
+ (color_depth==HDMI_COLOR_DEPTH_48B)? 0x10ee : 0x010e;
+ csc_coeff_b1 = 0x2000;
+ csc_coeff_b2 = 0x2cdd;
+ csc_coeff_b3 = 0x0000;
+ csc_coeff_b4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x7e9a :
+ (color_depth==HDMI_COLOR_DEPTH_30B)? 0x7a65 :
+ (color_depth==HDMI_COLOR_DEPTH_36B)? 0x6992 :
+ (color_depth==HDMI_COLOR_DEPTH_48B)? 0x6992 : 0x7e9a;
+ csc_coeff_c1 = 0x2000;
+ csc_coeff_c2 = 0x0000;
+ csc_coeff_c3 = 0x38b4;
+ csc_coeff_c4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x7e3b :
+ (color_depth==HDMI_COLOR_DEPTH_30B)? 0x78ea :
+ (color_depth==HDMI_COLOR_DEPTH_36B)? 0x63a6 :
+ (color_depth==HDMI_COLOR_DEPTH_48B)? 0x63a6 : 0x7e3b;
+ csc_scale = 1;
+ } else { /*input_color_format == HDMI_COLOR_FORMAT_RGB*/
+ csc_coeff_a1 = 0x2591;
+ csc_coeff_a2 = 0x1322;
+ csc_coeff_a3 = 0x074b;
+ csc_coeff_a4 = 0x0000;
+ csc_coeff_b1 = 0x6535;
+ csc_coeff_b2 = 0x2000;
+ csc_coeff_b3 = 0x7acc;
+ csc_coeff_b4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x0200 :
+ (color_depth==HDMI_COLOR_DEPTH_30B)? 0x0800 :
+ (color_depth==HDMI_COLOR_DEPTH_36B)? 0x2000 :
+ (color_depth==HDMI_COLOR_DEPTH_48B)? 0x2000 : 0x0200;
+ csc_coeff_c1 = 0x6acd;
+ csc_coeff_c2 = 0x7534;
+ csc_coeff_c3 = 0x2000;
+ csc_coeff_c4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x0200 :
+ (color_depth==HDMI_COLOR_DEPTH_30B)? 0x0800 :
+ (color_depth==HDMI_COLOR_DEPTH_36B)? 0x2000 :
+ (color_depth==HDMI_COLOR_DEPTH_48B)? 0x2000 : 0x0200;
+ csc_scale = 0;
+ }
+ } else {
+ csc_coeff_a1 = 0x2000;
+ csc_coeff_a2 = 0x0000;
+ csc_coeff_a3 = 0x0000;
+ csc_coeff_a4 = 0x0000;
+ csc_coeff_b1 = 0x0000;
+ csc_coeff_b2 = 0x2000;
+ csc_coeff_b3 = 0x0000;
+ csc_coeff_b4 = 0x0000;
+ csc_coeff_c1 = 0x0000;
+ csc_coeff_c2 = 0x0000;
+ csc_coeff_c3 = 0x2000;
+ csc_coeff_c4 = 0x0000;
+ csc_scale = 1;
+ }
+
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A1_MSB, (csc_coeff_a1>>8)&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A1_LSB, csc_coeff_a1&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A2_MSB, (csc_coeff_a2>>8)&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A2_LSB, csc_coeff_a2&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A3_MSB, (csc_coeff_a3>>8)&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A3_LSB, csc_coeff_a3&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A4_MSB, (csc_coeff_a4>>8)&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A4_LSB, csc_coeff_a4&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B1_MSB, (csc_coeff_b1>>8)&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B1_LSB, csc_coeff_b1&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B2_MSB, (csc_coeff_b2>>8)&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B2_LSB, csc_coeff_b2&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B3_MSB, (csc_coeff_b3>>8)&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B3_LSB, csc_coeff_b3&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B4_MSB, (csc_coeff_b4>>8)&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B4_LSB, csc_coeff_b4&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C1_MSB, (csc_coeff_c1>>8)&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C1_LSB, csc_coeff_c1&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C2_MSB, (csc_coeff_c2>>8)&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C2_LSB, csc_coeff_c2&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C3_MSB, (csc_coeff_c3>>8)&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C3_LSB, csc_coeff_c3&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C4_MSB, (csc_coeff_c4>>8)&0xff);
+ hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C4_LSB, csc_coeff_c4&0xff);
+
+ data32 = 0;
+ data32 |= (color_depth << 4); /* [7:4] csc_color_depth*/
+ data32 |= (csc_scale << 0); /* [1:0] cscscale*/
+ hdmitx_wr_reg(HDMITX_DWC_CSC_SCALE, data32);
+
+ /* set csc in video path */
+ hdmitx_wr_reg(HDMITX_DWC_MC_FLOWCTRL, (conv_en == 1) ? 0x1 : 0x0);
+} /* hdmitx_csc_config */
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_drv.h b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_drv.h
new file mode 100644
index 0000000..7708a9e
--- /dev/null
+++ b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_drv.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __HDMITX_DRV_H__
+#define __HDMITX_DRV_H__
+
+#include <amlogic/media/vout/hdmitx/hdmitx.h>
+void set_vmode_enc_hw(enum hdmi_vic vic);
+
+#endif
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_policy.c b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_policy.c
new file mode 100755
index 0000000..2e33833
--- /dev/null
+++ b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_policy.c
@@ -0,0 +1,1144 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <malloc.h>
+#include <asm/byteorder.h>
+#include <amlogic/media/vout/hdmitx/hdmitx.h>
+#include <amlogic/media/dv/dolby_vision.h>
+#include <asm/arch/cpu.h>
+#include <amlogic/cpu_id.h>
+
+#define DV_MODE_720P50HZ "720p50hz"
+#define DV_MODE_720P "720p60hz"
+#define DV_MODE_1080P24HZ "1080p24hz"
+#define DV_MODE_1080P50HZ "1080p50hz"
+#define DV_MODE_1080P "1080p60hz"
+#define DV_MODE_4K2K24HZ "2160p24hz"
+#define DV_MODE_4K2K25HZ "2160p25hz"
+#define DV_MODE_4K2K30HZ "2160p30hz"
+#define DV_MODE_4K2K50HZ "2160p50hz"
+#define DV_MODE_4K2K60HZ "2160p60hz"
+#define DV_MODE_LIST_SIZE 10
+
+#define MODE_480I "480i60hz"
+#define MODE_480P "480p60hz"
+#define MODE_480CVBS "480cvbs"
+#define MODE_576I "576i50hz"
+#define MODE_576P "576p50hz"
+#define MODE_576CVBS "576cvbs"
+#define MODE_720P50HZ "720p50hz"
+#define MODE_720P "720p60hz"
+#define MODE_768P "768p60hz"
+#define MODE_1080P24HZ "1080p24hz"
+#define MODE_1080P25HZ "1080p25hz"
+#define MODE_1080P30HZ "1080p30hz"
+#define MODE_1080I50HZ "1080i50hz"
+#define MODE_1080P50HZ "1080p50hz"
+#define MODE_1080I "1080i60hz"
+#define MODE_1080P "1080p60hz"
+#define MODE_4K2K24HZ "2160p24hz"
+#define MODE_4K2K25HZ "2160p25hz"
+#define MODE_4K2K30HZ "2160p30hz"
+#define MODE_4K2K50HZ "2160p50hz"
+#define MODE_4K2K60HZ "2160p60hz"
+#define MODE_4K2KSMPTE "smpte24hz"
+#define MODE_4K2KSMPTE30HZ "smpte30hz"
+#define MODE_4K2KSMPTE50HZ "smpte50hz"
+#define MODE_4K2KSMPTE60HZ "smpte60hz"
+#define MODE_PANEL "panel"
+#define MODE_PAL_M "pal_m"
+#define MODE_PAL_N "pal_n"
+#define MODE_NTSC_M "ntsc_m"
+
+#define COLOR_YCBCR444_12BIT "444,12bit"
+#define COLOR_YCBCR444_10BIT "444,10bit"
+#define COLOR_YCBCR444_8BIT "444,8bit"
+#define COLOR_YCBCR422_12BIT "422,12bit"
+#define COLOR_YCBCR422_10BIT "422,10bit"
+#define COLOR_YCBCR422_8BIT "422,8bit"
+#define COLOR_YCBCR420_12BIT "420,12bit"
+#define COLOR_YCBCR420_10BIT "420,10bit"
+#define COLOR_YCBCR420_8BIT "420,8bit"
+#define COLOR_RGB_12BIT "rgb,12bit"
+#define COLOR_RGB_10BIT "rgb,10bit"
+#define COLOR_RGB_8BIT "rgb,8bit"
+
+static const char *DISPLAY_MODE_LIST[] = {
+ MODE_480I,
+ MODE_480P,
+ /* MODE_480CVBS, */
+ MODE_576I,
+ MODE_576P,
+ /* MODE_576CVBS, */
+ MODE_720P,
+ MODE_720P50HZ,
+ MODE_1080P24HZ,
+ MODE_1080P25HZ,
+ MODE_1080P30HZ,
+ MODE_1080I50HZ,
+ MODE_1080P50HZ,
+ MODE_1080I,
+ MODE_1080P,
+ MODE_4K2K24HZ,
+ MODE_4K2K25HZ,
+ MODE_4K2K30HZ,
+ MODE_4K2K50HZ,
+ MODE_4K2K60HZ,
+ MODE_4K2KSMPTE,
+ MODE_4K2KSMPTE30HZ,
+ MODE_4K2KSMPTE50HZ,
+ MODE_4K2KSMPTE60HZ
+ /* MODE_768P, */
+ /* MODE_PANEL, */
+ /* MODE_PAL_M, */
+ /* MODE_PAL_N, */
+ /* MODE_NTSC_M, */
+};
+
+/* for check hdr 4k support or not */
+static const char * const MODE_4K_LIST[] = {
+ MODE_4K2K60HZ,
+ MODE_4K2K50HZ,
+};
+
+/* for check hdr non-4k support or not
+ * interface mode is lower priority as some android
+ * version may removed interlace mode.
+ * descending order
+ */
+static const char * const MODE_NON4K_LIST[] = {
+ MODE_1080P,
+ MODE_1080P50HZ,
+ MODE_720P,
+ MODE_720P50HZ,
+ MODE_576P,
+ MODE_480P,
+ MODE_1080I,
+ MODE_1080I50HZ,
+ MODE_576I,
+ MODE_480I,
+};
+
+/* ascending order */
+static const char *MODE_RESOLUTION_FIRST[] = {
+ MODE_480I,
+ MODE_576I,
+ MODE_1080I50HZ,
+ MODE_1080I,
+ MODE_480P,
+ MODE_576P,
+ MODE_720P50HZ,
+ MODE_720P,
+ MODE_1080P50HZ,
+ MODE_1080P,
+ MODE_4K2K24HZ,
+ MODE_4K2K25HZ,
+ MODE_4K2K30HZ,
+ MODE_4K2K50HZ,
+ MODE_4K2K60HZ
+};
+
+/* ascending order */
+static const char *MODE_FRAMERATE_FIRST[] = {
+ MODE_480I,
+ MODE_576I,
+ MODE_1080I50HZ,
+ MODE_1080I,
+ MODE_480P,
+ MODE_576P,
+ MODE_720P50HZ,
+ MODE_720P,
+ MODE_4K2K24HZ,
+ MODE_4K2K25HZ,
+ MODE_4K2K30HZ,
+ MODE_1080P50HZ,
+ MODE_1080P,
+ MODE_4K2K50HZ,
+ MODE_4K2K60HZ
+};
+
+/* this is prior selected list for sdr of
+ * 4k2k50hz, 4k2k60hz smpte50hz, smpte60hz
+ * for user change resolution case in sysctl.
+ * descending order
+ */
+static const char *COLOR_ATTRIBUTE_LIST1[] = {
+ COLOR_YCBCR420_10BIT,
+ COLOR_YCBCR422_12BIT,
+ COLOR_YCBCR420_8BIT,
+ COLOR_YCBCR444_8BIT,
+ COLOR_RGB_8BIT
+};
+
+/* this is prior selected list for hdr and sdr of
+ * non 4k50/60hz display mode.
+ * under HDR priority && auto best is off, it may
+ * change from TV_A (1080p60hz 444,10bit HDR) to
+ * TV_B witch support 1080p60hz 444,8bit maximum.
+ * should keep mode(1080p60hz) witch user selected,
+ * and 8bit depth(sdr) is kept in select list for
+ * safety of conner case.
+ * i.e. if HDR cs/cd is not supported, may select
+ * 8bit mode.
+ * also for user change resolution case in sysctl.
+ * descending order
+ */
+static const char *COLOR_ATTRIBUTE_LIST2[] = {
+ COLOR_YCBCR422_12BIT,
+ COLOR_YCBCR444_10BIT,
+ COLOR_RGB_10BIT,
+ COLOR_YCBCR444_8BIT,
+ COLOR_RGB_8BIT
+};
+
+/* this is prior selected list for sdr of
+ * non 4k50/60hz display mode
+ * descending order
+ */
+static const char *SDR_NON4K_COLOR_ATTRIBUTE_LIST[] = {
+ COLOR_YCBCR444_8BIT,
+ COLOR_RGB_8BIT,
+ COLOR_YCBCR422_12BIT,
+ COLOR_YCBCR444_10BIT,
+ COLOR_RGB_10BIT,
+};
+
+/* this is prior selected list of Low Power Mode
+ * 4k2k50hz, 4k2k60hz smpte50hz, smpte60hz
+ */
+static const char *COLOR_ATTRIBUTE_LIST3[] = {
+ COLOR_YCBCR420_8BIT,
+ COLOR_YCBCR420_10BIT,
+ COLOR_YCBCR422_8BIT,
+ COLOR_YCBCR422_10BIT,
+ COLOR_YCBCR444_8BIT,
+ COLOR_RGB_8BIT,
+ COLOR_YCBCR420_12BIT,
+ COLOR_YCBCR422_12BIT
+};
+
+/* this is prior selected list of
+ * Low Power Mode other display mode
+ */
+static const char *COLOR_ATTRIBUTE_LIST4[] = {
+ COLOR_YCBCR444_8BIT,
+ COLOR_YCBCR422_8BIT,
+ COLOR_RGB_8BIT,
+ COLOR_YCBCR422_10BIT,
+ COLOR_YCBCR422_12BIT,
+};
+
+/* this is prior selected list of HDR non 4k50/60 colorspace
+ * descending order
+ */
+static const char * const HDR_NON4K_COLOR_ATTRIBUTE_LIST[] = {
+ COLOR_YCBCR422_12BIT,
+ COLOR_YCBCR444_10BIT,
+ COLOR_RGB_10BIT,
+ COLOR_YCBCR444_12BIT,
+ COLOR_RGB_12BIT,
+};
+
+/* this is prior selected list of HDR 4k colorspace(2160p60hz/2160p50hz)
+ * descending order
+ */
+static const char * const HDR_4K_COLOR_ATTRIBUTE_LIST[] = {
+ COLOR_YCBCR420_10BIT,
+ COLOR_YCBCR422_12BIT,
+};
+
+/* support format lists */
+static const char *disp_mode_t[] = {
+ "480i60hz", /* 16:9 */
+ "576i50hz",
+ "480p60hz",
+ "576p50hz",
+ "720p60hz",
+ "1080i60hz",
+ "1080p60hz",
+ "1080p120hz",
+ "720p50hz",
+ "1080i50hz",
+ "1080p30hz",
+ "1080p50hz",
+ "1080p25hz",
+ "1080p24hz",
+ "2560x1080p50hz",
+ "2560x1080p60hz",
+ "2160p30hz",
+ "2160p25hz",
+ "2160p24hz",
+ "smpte24hz",
+ "smpte25hz",
+ "smpte30hz",
+ "smpte50hz",
+ "smpte60hz",
+ "2160p50hz",
+ "2160p60hz",
+ /* VESA modes */
+ "640x480p60hz",
+ "800x480p60hz",
+ "800x600p60hz",
+ "852x480p60hz",
+ "854x480p60hz",
+ "1024x600p60hz",
+ "1024x768p60hz",
+ "1152x864p75hz",
+ "1280x600p60hz",
+ "1280x768p60hz",
+ "1280x800p60hz",
+ "1280x960p60hz",
+ "1280x1024p60hz",
+ "1360x768p60hz",
+ "1366x768p60hz",
+ "1400x1050p60hz",
+ "1440x900p60hz",
+ "1440x2560p60hz",
+ "1600x900p60hz",
+ "1600x1200p60hz",
+ "1680x1050p60hz",
+ "1920x1200p60hz",
+ "2160x1200p90hz",
+ "2560x1440p60hz",
+ "2560x1600p60hz",
+ "3440x1440p60hz",
+ "2400x1200p90hz",
+ NULL
+};
+
+static bool is_best_outputmode(void)
+{
+ char *is_bestmode = env_get("is.bestmode");
+
+ return !is_bestmode || (strcmp(is_bestmode, "true") == 0);
+}
+
+static bool is_framerate_priority(void)
+{
+ char *framerate_priority = env_get("framerate_priority");
+
+ return !framerate_priority || (strcmp(framerate_priority, "true") == 0);
+}
+
+/* import from kernel */
+static inline bool package_id_is(unsigned int id)
+{
+ return get_cpu_id().package_id == id;
+}
+
+static inline bool is_meson_gxl_cpu(void)
+{
+ return get_cpu_id().family_id == MESON_CPU_MAJOR_ID_GXL;
+}
+
+static inline bool is_meson_gxl_package_805X(void)
+{
+ return is_meson_gxl_cpu() && package_id_is(0x30);
+}
+
+static inline bool is_meson_gxl_package_805Y(void)
+{
+ return is_meson_gxl_cpu() && package_id_is(0xb0);
+}
+
+/* below items has feature limited, may need extra judgement */
+bool is_hdmitx_limited_1080p(void)
+{
+ struct hdmitx_dev *hdev = hdmitx_get_hdev();
+
+ if (is_meson_gxl_package_805X())
+ return true;
+ else if (is_meson_gxl_package_805Y())
+ return true;
+ else if (hdev->limit_res_1080p == 1)
+ return true;
+ else
+ return false;
+}
+
+bool is_support_4k(void)
+{
+ if (is_hdmitx_limited_1080p())
+ return false;
+ return true;
+}
+
+static bool is_support_deepcolor(void)
+{
+ return true;
+}
+
+static bool is_low_powermode(void)
+{
+ return false;
+}
+
+static int is_4k50_fmt(char *mode)
+{
+ int i;
+ static char const *hdmi4k50[] = {
+ "2160p50hz",
+ "2160p60hz",
+ "smpte50hz",
+ "smpte60hz",
+ NULL
+ };
+
+ for (i = 0; hdmi4k50[i]; i++) {
+ if (strcmp(hdmi4k50[i], mode) == 0)
+ return 1;
+ }
+ return 0;
+}
+
+static int get_hdr_priority(void)
+{
+ char *hdr_priority = env_get("hdr_priority");
+ hdr_priority_e value = DOLBY_VISION_PRIORITY;
+
+ if (hdr_priority) {
+ if (strcmp(hdr_priority, "2") == 0)
+ value = SDR_PRIORITY;
+ else if (strcmp(hdr_priority, "1") == 0)
+ value = HDR10_PRIORITY;
+ else
+ value = DOLBY_VISION_PRIORITY;
+ } else {
+ value = DOLBY_VISION_PRIORITY;
+ }
+
+ return (int)value;
+}
+
+bool is_tv_support_hdr(struct hdmitx_dev *hdev)
+{
+ struct hdr_info *hdr;
+ struct hdr10_plus_info *hdr10p;
+
+ if (!hdev)
+ return false;
+ hdr = &hdev->RXCap.hdr_info;
+ hdr10p = &hdev->RXCap.hdr10plus_info;
+ if (hdr->hdr_sup_eotf_smpte_st_2084 || hdr->hdr_sup_eotf_hlg)
+ return true;
+ if (hdr10p->ieeeoui == HDR10_PLUS_IEEE_OUI &&
+ hdr10p->application_version != 0xFF)
+ return true;
+ return false;
+}
+
+static bool is_over_60hz(struct hdmi_format_para *para)
+{
+ if (!para)
+ return 1;
+
+ if (para->timing.v_freq > 60000)
+ return 1;
+
+ return 0;
+}
+
+/* check the resolution is over 1920x1080 or not */
+static bool is_over_1080p(struct hdmi_format_para *para)
+{
+ if (!para)
+ return 1;
+
+ if (para->timing.h_active > 1920 || para->timing.v_active > 1080)
+ return 1;
+
+ return 0;
+}
+
+/* test current vic is over 150MHz or not */
+static bool is_over_pixel_150mhz(struct hdmi_format_para *para)
+{
+ if (!para)
+ return 1;
+
+ if (para->timing.pixel_freq > 150000)
+ return 1;
+
+ return 0;
+}
+
+bool is_vic_over_limited_1080p(enum hdmi_vic vic)
+{
+ struct hdmi_format_para *para = hdmi_get_fmt_paras(vic);
+
+ /* if the vic equals to HDMI_unkown or VESA,
+ * then treate it as over limited
+ */
+ if (vic == HDMI_unkown || vic >= HDMITX_VESA_OFFSET)
+ return 1;
+
+ if (is_over_1080p(para) || is_over_60hz(para) ||
+ is_over_pixel_150mhz(para)) {
+ pr_err("over limited vic: %d\n", vic);
+ return 1;
+ }
+ return 0;
+}
+
+bool is_tv_support_dv(struct hdmitx_dev *hdev)
+{
+ /*todo*/
+ struct dv_info *dv;
+
+ if (!hdev)
+ return false;
+ dv = &(hdev->RXCap.dv_info);
+
+ if ((dv->ieeeoui != DV_IEEE_OUI) || (dv->block_flag != CORRECT))
+ return false;
+ return true;
+}
+
+bool is_dv_preference(struct hdmitx_dev *hdev)
+{
+ int hdr_priority = get_hdr_priority();
+
+ if (!hdev)
+ return false;
+ if (is_dolby_enabled() &&
+ hdr_priority == DOLBY_VISION_PRIORITY &&
+ is_tv_support_dv(hdev))
+ return true;
+ else
+ return false;
+}
+
+bool is_hdr_preference(struct hdmitx_dev *hdev)
+{
+ int hdr_priority = get_hdr_priority();
+
+ if (!hdev)
+ return false;
+ if ((hdr_priority == DOLBY_VISION_PRIORITY ||
+ hdr_priority == HDR10_PRIORITY) &&
+ is_tv_support_hdr(hdev))
+ return true;
+ else
+ return false;
+}
+
+int get_ubootenv_dv_type(void)
+{
+ char *dolby_status = NULL;
+
+ dolby_status = env_get("dolby_status");
+
+ if (!dolby_status) {
+ printf("no ubootenv dolby_status\n");
+ return DOLBY_VISION_DISABLE;
+ }
+ if (!strcmp(dolby_status, DOLBY_VISION_SET_STD))
+ return DOLBY_VISION_STD_ENABLE;
+ else if (!strcmp(dolby_status, DOLBY_VISION_SET_LL_YUV))
+ return DOLBY_VISION_LL_YUV;
+ else if (!strcmp(dolby_status, DOLBY_VISION_SET_LL_RGB))
+ return DOLBY_VISION_LL_RGB;
+ else
+ return DOLBY_VISION_DISABLE;
+}
+
+bool is_dolby_enabled(void)
+{
+ if (get_ubootenv_dv_type() != DOLBY_VISION_DISABLE)
+ return true;
+ else
+ return false;
+}
+
+static int resolve_resolution_value(const char *mode, int flag)
+{
+ bool validmode = false;
+ int i;
+
+ if (!mode)
+ return -1;
+
+ if (strlen(mode) != 0) {
+ for (i = 0; i < ARRAY_SIZE(DISPLAY_MODE_LIST); i++) {
+ if (strcmp(mode, DISPLAY_MODE_LIST[i]) == 0) {
+ validmode = true;
+ break;
+ }
+ }
+ }
+ if (!validmode) {
+ printf("the resolveResolution mode [%s] is not valid\n", mode);
+ return -1;
+ }
+
+ if (is_framerate_priority() && flag == FRAMERATE_PRIORITY) {
+ for (i = 0; i < ARRAY_SIZE(MODE_FRAMERATE_FIRST); i++) {
+ if (strcmp(mode, MODE_FRAMERATE_FIRST[i]) == 0)
+ return i;
+ }
+ } else {
+ for (i = 0; i < ARRAY_SIZE(MODE_RESOLUTION_FIRST); i++) {
+ if (strcmp(mode, MODE_RESOLUTION_FIRST[i]) == 0)
+ return i;
+ }
+ }
+
+ return -1;
+}
+
+/* need update DV CAP */
+static int update_dv_type(hdmi_data_t *hdmi_data)
+{
+ /* 1.read dolby vision mode from prop(env) */
+ int type;
+ struct dv_info *dv = NULL;
+
+ if (!hdmi_data)
+ return DOLBY_VISION_DISABLE;
+
+ type = hdmi_data->ubootenv_dv_type;
+ dv = &(hdmi_data->pRXCap->dv_info);
+
+ /* 2.check tv support or not */
+ if ((type == 1) && (dv->support_DV_RGB_444_8BIT == 1)) {
+ return DOLBY_VISION_STD_ENABLE;
+ } else if ((type == 2) && (dv->support_LL_YCbCr_422_12BIT == 1)) {
+ return DOLBY_VISION_LL_YUV;
+ } else if ((type == 3) &&
+ ((dv->support_LL_RGB_444_10BIT == 1) ||
+ (dv->support_LL_RGB_444_12BIT == 1))) {
+ return DOLBY_VISION_LL_RGB;
+ } else if (type == 0) {
+ return DOLBY_VISION_DISABLE;
+ }
+
+ /* 3.dolby vision best policy:
+ * STD->LL_YUV->LL_RGB for netflix request
+ * LL_YUV->STD->LL_RGB for dolby vision request
+ */
+ printf("NOTE: DV type is changed!\n");
+ if ((dv->support_DV_RGB_444_8BIT == 1) ||
+ (dv->support_LL_YCbCr_422_12BIT == 1)) {
+ if (dv->support_DV_RGB_444_8BIT == 1)
+ return DOLBY_VISION_STD_ENABLE;
+ else if (dv->support_LL_YCbCr_422_12BIT == 1)
+ return DOLBY_VISION_LL_YUV;
+ } else if ((dv->support_LL_RGB_444_10BIT == 1) ||
+ (dv->support_LL_RGB_444_12BIT == 1)) {
+ return DOLBY_VISION_LL_RGB;
+ }
+
+ return DOLBY_VISION_DISABLE;
+}
+
+static void update_dv_attr(hdmi_data_t *hdmi_data, char *dv_attr)
+{
+ int dv_type;
+ struct dv_info *dv = NULL;
+ if (!hdmi_data || !dv_attr)
+ return;
+
+ dv_type = hdmi_data->ubootenv_dv_type;
+ dv = &(hdmi_data->pRXCap->dv_info);
+
+ switch (dv_type) {
+ case DOLBY_VISION_STD_ENABLE:
+ strcpy(dv_attr, "444,8bit");
+ break;
+ case DOLBY_VISION_LL_YUV:
+ strcpy(dv_attr, "422,12bit");
+ break;
+ case DOLBY_VISION_LL_RGB:
+ if (dv->support_LL_RGB_444_12BIT == 1)
+ strcpy(dv_attr, "444,12bit");
+ else if (dv->support_LL_RGB_444_10BIT == 1)
+ strcpy(dv_attr, "444,10bit");
+
+ break;
+ default:
+ strcpy(dv_attr, "444,8bit");
+ break;
+ }
+
+ printf("dv_type :%d dv_attr:%s", dv_type, dv_attr);
+}
+
+static void update_dv_displaymode(hdmi_data_t *hdmi_data,
+ char *final_displaymode)
+{
+ char dv_displaymode[MODE_LEN] = {0};
+ char cur_outputmode[MODE_LEN] = {0};
+ int dv_type;
+ struct dv_info *dv = NULL;
+
+ if (!hdmi_data || !final_displaymode)
+ return;
+ dv_type = hdmi_data->ubootenv_dv_type;
+ strcpy(cur_outputmode, hdmi_data->ubootenv_hdmimode);
+ dv = &(hdmi_data->pRXCap->dv_info);
+ if (dv->sup_2160p60hz == 1)
+ strcpy(dv_displaymode, DV_MODE_4K2K60HZ);
+ else
+ strcpy(dv_displaymode, DV_MODE_4K2K30HZ);
+ if (is_best_outputmode()) {
+ if (!strcmp(dv_displaymode, DV_MODE_4K2K60HZ)) {
+ if (dv_type == DOLBY_VISION_LL_RGB)
+ strcpy(final_displaymode, DV_MODE_1080P);
+ else
+ strcpy(final_displaymode, DV_MODE_4K2K60HZ);
+ } else {
+ if (!strcmp(dv_displaymode, DV_MODE_4K2K30HZ) ||
+ !strcmp(dv_displaymode, DV_MODE_4K2K25HZ) ||
+ !strcmp(dv_displaymode, DV_MODE_4K2K24HZ))
+ strcpy(final_displaymode, DV_MODE_1080P);
+ else
+ strcpy(final_displaymode, dv_displaymode);
+ }
+ } else {
+ /* if current disp_mode is outside of maximum dv disp_mode */
+ if ((resolve_resolution_value(cur_outputmode, RESOLUTION_PRIORITY) >
+ resolve_resolution_value(dv_displaymode, RESOLUTION_PRIORITY)) ||
+ (strstr(cur_outputmode, "smpte") != NULL) ||
+ (strstr(cur_outputmode, "i") != NULL))
+ strcpy(final_displaymode, dv_displaymode);
+ else
+ strcpy(final_displaymode, cur_outputmode);
+ }
+
+ printf("final_displaymode:%s, cur_outputmode:%s, dv_displaymode:%s",
+ final_displaymode, cur_outputmode, dv_displaymode);
+}
+
+/* for some non-std TV, it declare 4k while MAX_TMDS_CLK
+ * not match 4K format, so filter out mode list by
+ * check if basic color space/depth is supported
+ * or not under this resolution
+ * note that disp_mode should not contain colorspace, such as 420
+ */
+static bool hdmi_sink_disp_mode_sup(struct input_hdmi_data *hdmi_data, char *disp_mode)
+{
+ if (!hdmi_data || !disp_mode)
+ return false;
+
+ if (is_4k50_fmt(disp_mode)) {
+ if (hdmitx_chk_mode_attr_sup(hdmi_data, disp_mode, "420,8bit"))
+ return true;
+ if (hdmitx_chk_mode_attr_sup(hdmi_data, disp_mode, "rgb,8bit"))
+ return true;
+ if (hdmitx_chk_mode_attr_sup(hdmi_data, disp_mode, "444,8bit"))
+ return true;
+ if (hdmitx_chk_mode_attr_sup(hdmi_data, disp_mode, "422,12bit"))
+ return true;
+ } else {
+ if (hdmitx_chk_mode_attr_sup(hdmi_data, disp_mode, "rgb,8bit"))
+ return true;
+ if (hdmitx_chk_mode_attr_sup(hdmi_data, disp_mode, "444,8bit"))
+ return true;
+ if (hdmitx_chk_mode_attr_sup(hdmi_data, disp_mode, "422,12bit"))
+ return true;
+ }
+ return false;
+}
+
+/* get the highest hdmi mode by edid */
+static void get_highest_hdmimode(hdmi_data_t *hdmi_data, char *mode)
+{
+ char value[MODE_LEN] = {0};
+ char mode_tmp[MODE_LEN];
+ int i;
+
+ if (!hdmi_data || !mode)
+ return;
+
+ strcpy(value, DEFAULT_HDMI_MODE);
+
+ for (i = 0; disp_mode_t[i]; i++) {
+ memset(mode_tmp, 0, sizeof(mode_tmp));
+ strncpy(mode_tmp, disp_mode_t[i], MODE_LEN - 1);
+ if (!hdmi_sink_disp_mode_sup(hdmi_data, mode_tmp))
+ continue;
+ if (resolve_resolution_value(mode_tmp, FRAMERATE_PRIORITY) >
+ resolve_resolution_value(value, FRAMERATE_PRIORITY)) {
+ memset(value, 0, MODE_LEN);
+ strcpy(value, mode_tmp);
+ }
+ }
+
+ strcpy(mode, value);
+ printf("set HDMI to highest edid mode: %s\n", mode);
+}
+
+/* check if the edid support current hdmi mode */
+static void filter_hdmimode(hdmi_data_t *hdmi_data, char *mode)
+{
+ if (!hdmi_data || !mode)
+ return;
+
+ if (hdmi_sink_disp_mode_sup(hdmi_data, mode)) {
+ strcpy(mode, hdmi_data->ubootenv_hdmimode);
+ } else {
+ /* old mode is not support in this TV,
+ * so switch to best mode.
+ */
+ get_highest_hdmimode(hdmi_data, mode);
+ }
+}
+
+static void get_hdmi_outputmode(hdmi_data_t *hdmi_data, char *mode)
+{
+ struct hdmitx_dev *hdev = NULL;
+
+ if (!hdmi_data || !mode)
+ return;
+
+ hdev = container_of(hdmi_data->pRXCap,
+ struct hdmitx_dev, RXCap);
+
+ /* Fall back to 480p if EDID can't be parsed */
+ if (!edid_parsing_ok(hdev)) {
+ strcpy(mode, DEFAULT_HDMI_MODE);
+ printf("EDID parsing error detected\n");
+ return;
+ }
+
+ if (is_best_outputmode())
+ get_highest_hdmimode(hdmi_data, mode);
+ else
+ filter_hdmimode(hdmi_data, mode);
+}
+
+static void get_best_color_attr(hdmi_data_t *hdmi_data,
+ const char *outputmode, char *colorattribute)
+{
+ int length = 0;
+ const char **color_list = NULL;
+ char temp_mode[MODE_LEN] = {0};
+ int i;
+ struct hdmitx_dev *hdev = NULL;
+
+ if (!hdmi_data || !outputmode || !colorattribute)
+ return;
+
+ hdev = container_of(hdmi_data->pRXCap,
+ struct hdmitx_dev, RXCap);
+
+ /* filter some color value options, aimed at some modes. */
+ if (!strcmp(outputmode, MODE_4K2K60HZ) ||
+ !strcmp(outputmode, MODE_4K2K50HZ) ||
+ !strcmp(outputmode, MODE_4K2KSMPTE60HZ) ||
+ !strcmp(outputmode, MODE_4K2KSMPTE50HZ)) {
+ if (is_low_powermode()) {
+ color_list = COLOR_ATTRIBUTE_LIST3;
+ length = ARRAY_SIZE(COLOR_ATTRIBUTE_LIST3);
+ } else {
+ color_list = COLOR_ATTRIBUTE_LIST1;
+ length = ARRAY_SIZE(COLOR_ATTRIBUTE_LIST1);
+ }
+ } else {
+ if (is_low_powermode()) {
+ color_list = COLOR_ATTRIBUTE_LIST4;
+ length = ARRAY_SIZE(COLOR_ATTRIBUTE_LIST4);
+ } else if (is_hdr_preference(hdev)) {
+ /* hdr non 4k50/60hz color format priority table */
+ color_list = COLOR_ATTRIBUTE_LIST2;
+ length = ARRAY_SIZE(COLOR_ATTRIBUTE_LIST2);
+ } else {
+ /* sdr non 4k50/60hz color format priority table */
+ color_list = SDR_NON4K_COLOR_ATTRIBUTE_LIST;
+ length = ARRAY_SIZE(SDR_NON4K_COLOR_ATTRIBUTE_LIST);
+ }
+ }
+
+ for (i = 0; i < length; i++) {
+ strcpy(temp_mode, outputmode);
+ strcat(temp_mode, color_list[i]);
+ if (is_supported_mode_attr(hdmi_data, temp_mode)) {
+ printf("support current mode:[%s], deep color:[%s]\n",
+ outputmode, color_list[i]);
+ strcpy(colorattribute, color_list[i]);
+ break;
+ }
+ }
+}
+
+static void get_hdmi_colorattribute(hdmi_data_t *hdmi_data,
+ const char *outputmode, char *colorattribute)
+{
+ char temp_mode[MODE_LEN] = {0};
+
+ if (!hdmi_data || !outputmode || !colorattribute)
+ return;
+ /* if dc_cap is null, use default color format */
+ /* should never encounter this case */
+ if (false) {
+ if (!strcmp(outputmode, MODE_4K2K60HZ) ||
+ !strcmp(outputmode, MODE_4K2K50HZ) ||
+ !strcmp(outputmode, MODE_4K2KSMPTE60HZ) ||
+ !strcmp(outputmode, MODE_4K2KSMPTE50HZ)) {
+ strcpy(colorattribute, DEFAULT_COLOR_FORMAT_4K);
+ } else {
+ strcpy(colorattribute, DEFAULT_COLOR_FORMAT);
+ }
+
+ printf("Do not find sink color list, use default color attribute:%s\n",
+ colorattribute);
+ return;
+ }
+
+ /* if bestpolicy is disabled, use ubootenv.var.colorattribute */
+ if (!is_best_outputmode()) {
+ strcpy(temp_mode, hdmi_data->ubootenv_hdmimode);
+ strcat(temp_mode, hdmi_data->ubootenv_colorattribute);
+ if (is_supported_mode_attr(hdmi_data, temp_mode))
+ strcpy(colorattribute,
+ hdmi_data->ubootenv_colorattribute);
+ else
+ get_best_color_attr(hdmi_data, outputmode,
+ colorattribute);
+ } else {
+ get_best_color_attr(hdmi_data, outputmode, colorattribute);
+ }
+
+ /* if colorAttr is null above steps,
+ * will defines a initial value
+ */
+ if (!strstr(colorattribute, "bit"))
+ strcpy(colorattribute, DEFAULT_COLOR_FORMAT);
+}
+
+static void update_hdmi_deepcolor(hdmi_data_t *hdmi_data,
+ const char *outputmode, char *colorattribute)
+{
+ if (!hdmi_data || !outputmode || !colorattribute)
+ return;
+ if (is_support_deepcolor())
+ get_hdmi_colorattribute(hdmi_data, outputmode, colorattribute);
+ else
+ strcpy(colorattribute, "default");
+
+ printf("colorattribute = %s\n", colorattribute);
+}
+
+void dolbyvision_scene_process(hdmi_data_t *hdmi_data,
+ scene_output_info_t *output_info)
+{
+ int dv_type = DOLBY_VISION_DISABLE;
+
+ if (!hdmi_data || !output_info)
+ return;
+ /* 1.update dolby vision output type */
+ dv_type = update_dv_type(hdmi_data);
+ output_info->final_dv_type = dv_type;
+ printf("dv final_type:%d\n", output_info->final_dv_type);
+
+ /* update param */
+ hdmi_data->ubootenv_dv_type = dv_type;
+ /* 2. update dolby vision output output mode and colorspace */
+ /* 2.1 update dolby vision deepcolor */
+ update_dv_attr(hdmi_data, output_info->final_deepcolor);
+ printf("dv final_deepcolor:%s\n", output_info->final_deepcolor);
+
+ /* 2.2 update dolby vision output mode */
+ update_dv_displaymode(hdmi_data, output_info->final_displaymode);
+ printf("dv final_displaymode:%s", output_info->final_displaymode);
+}
+
+/* check 4k50/4k60 hdr support or not */
+static bool is_support_4k60hdr(struct input_hdmi_data *hdmi_data,
+ scene_output_info_t *output_info)
+{
+ int colorList_length = 0;
+ int resolutionList_length = 0;
+ int i = 0;
+ int j = 0;
+ char temp_mode[MODE_LEN] = {0};
+
+ if (!hdmi_data || !output_info)
+ return false;
+
+ colorList_length = ARRAY_SIZE(HDR_4K_COLOR_ATTRIBUTE_LIST);
+ resolutionList_length = ARRAY_SIZE(MODE_4K_LIST);
+
+ for (i = 0; i < colorList_length; i++) {
+ for (j = 0; j < resolutionList_length; j++) {
+ memset(temp_mode, 0, sizeof(temp_mode));
+ strncpy(temp_mode, MODE_4K_LIST[j], MODE_LEN - 1);
+ if (strlen(temp_mode) + strlen(HDR_4K_COLOR_ATTRIBUTE_LIST[i]) <
+ MODE_LEN)
+ strcat(temp_mode, HDR_4K_COLOR_ATTRIBUTE_LIST[i]);
+ if (is_supported_mode_attr(hdmi_data, temp_mode)) {
+ printf("%s mode:[%s], deep color:[%s]\n",
+ __func__, MODE_4K_LIST[j], HDR_4K_COLOR_ATTRIBUTE_LIST[i]);
+ strcpy(output_info->final_deepcolor,
+ HDR_4K_COLOR_ATTRIBUTE_LIST[i]);
+ strcpy(output_info->final_displaymode,
+ MODE_4K_LIST[j]);
+ return true;
+ }
+ }
+ }
+ printf("%s 4k50/60hz hdr not support\n", __func__);
+ return false;
+}
+
+/* check non 4k hdr support or not */
+static bool is_support_non4k_hdr(struct input_hdmi_data *hdmi_data,
+ scene_output_info_t *output_info)
+{
+ int colorList_length = 0;
+ int resolutionList_length = 0;
+ int i = 0;
+ int j = 0;
+ char temp_mode[MODE_LEN] = {0};
+
+ if (!hdmi_data || !output_info)
+ return false;
+
+ colorList_length = ARRAY_SIZE(HDR_NON4K_COLOR_ATTRIBUTE_LIST);
+ resolutionList_length = ARRAY_SIZE(MODE_NON4K_LIST);
+
+ for (i = 0; i < colorList_length; i++) {
+ for (j = 0; j < resolutionList_length; j++) {
+ memset(temp_mode, 0, sizeof(temp_mode));
+ strncpy(temp_mode, MODE_NON4K_LIST[j], MODE_LEN - 1);
+ if (strlen(temp_mode) + strlen(HDR_NON4K_COLOR_ATTRIBUTE_LIST[i]) <
+ MODE_LEN)
+ strcat(temp_mode, HDR_NON4K_COLOR_ATTRIBUTE_LIST[i]);
+ if (is_supported_mode_attr(hdmi_data, temp_mode)) {
+ printf("%s mode:[%s], deep color:[%s]\n",
+ __func__, MODE_NON4K_LIST[j],
+ HDR_NON4K_COLOR_ATTRIBUTE_LIST[i]);
+ strcpy(output_info->final_deepcolor,
+ HDR_NON4K_COLOR_ATTRIBUTE_LIST[i]);
+ strcpy(output_info->final_displaymode,
+ MODE_NON4K_LIST[j]);
+ return true;
+ }
+ }
+ }
+
+ printf("%s non 4k hdr not support\n", __func__);
+ return false;
+}
+
+static bool find_hdr_prefer_mode(struct input_hdmi_data *hdmi_data,
+ scene_output_info_t *output_info)
+{
+ bool find = false;
+
+ if (!hdmi_data || !output_info)
+ return find;
+
+ /* if box can support 4k case
+ * find prefer 4k50/60hz hdr resolution and color format based on edid
+ */
+ if (is_support_4k())
+ find = is_support_4k60hdr(hdmi_data, output_info);
+
+ /* 1.not find 4k hdr mode case 2. box not support 4k case
+ * find prefer non 4k hdr resolution and color format based on edid
+ */
+ if (!find)
+ find = is_support_non4k_hdr(hdmi_data, output_info);
+
+ return find;
+}
+
+void hdr_scene_process(struct input_hdmi_data *hdmi_data,
+ scene_output_info_t *output_info)
+{
+ bool find = false;
+ char colorattribute[MODE_LEN] = {0};
+
+ if (!hdmi_data || !output_info)
+ return;
+
+ if (is_best_outputmode()) {
+ find = find_hdr_prefer_mode(hdmi_data, output_info);
+ if (!find)
+ printf("%s not find hdr support mode\n", __func__);
+ } else {
+ /* 1.check current displaymode + colorattribute support or not */
+ if (hdmitx_chk_mode_attr_sup(hdmi_data, hdmi_data->ubootenv_hdmimode,
+ hdmi_data->ubootenv_colorattribute)) {
+ strcpy(output_info->final_displaymode, hdmi_data->ubootenv_hdmimode);
+ strcpy(output_info->final_deepcolor, hdmi_data->ubootenv_colorattribute);
+ } else if (hdmi_sink_disp_mode_sup(hdmi_data, hdmi_data->ubootenv_hdmimode)) {
+ /* 2.check cur_displaymode support or not
+ * if support, find best color format for this mode.
+ */
+ get_best_color_attr(hdmi_data, hdmi_data->ubootenv_hdmimode,
+ colorattribute);
+ strcpy(output_info->final_displaymode, hdmi_data->ubootenv_hdmimode);
+ strcpy(output_info->final_deepcolor, colorattribute);
+ } else {
+ /* 3.find best hdr prefer mode */
+ find = find_hdr_prefer_mode(hdmi_data, output_info);
+ if (!find)
+ printf("%s not find hdr support mode2\n", __func__);
+ }
+ }
+}
+
+/* SDR scene policy process */
+void sdr_scene_process(struct input_hdmi_data *hdmi_data, struct scene_output_info *output_info)
+{
+ char outputmode[MODE_LEN] = {0};
+ char colorattribute[MODE_LEN] = {0};
+
+ if (!hdmi_data || !output_info)
+ return;
+ /* 1.choose resolution, frame rate */
+ get_hdmi_outputmode(hdmi_data, outputmode);
+ if (strlen(outputmode) == 0)
+ strcpy(outputmode, DEFAULT_HDMI_MODE);
+ strcpy(output_info->final_displaymode, outputmode);
+
+ /* 2.choose color format, bit-depth */
+ update_hdmi_deepcolor(hdmi_data, outputmode, colorattribute);
+ strcpy(output_info->final_deepcolor, colorattribute);
+ printf("sdr final_displaymode:%s, final_deepcolor:%s\n",
+ output_info->final_displaymode, output_info->final_deepcolor);
+}
+
+void get_hdmi_data(struct hdmitx_dev *hdev, hdmi_data_t *data)
+{
+ char *hdmimode;
+ char *colorattribute;
+
+ if (!hdev || !data)
+ return;
+
+ hdmimode = env_get("hdmimode");
+ colorattribute = env_get("colorattribute");
+
+ if (!hdmimode)
+ hdmimode = DEFAULT_HDMIMODE_ENV;
+ if (!colorattribute)
+ colorattribute = DEFAULT_COLORATTRIBUTE_ENV;
+ strcpy(data->ubootenv_hdmimode, hdmimode);
+ strcpy(data->ubootenv_colorattribute, colorattribute);
+ data->ubootenv_dv_type = get_ubootenv_dv_type();
+ data->hdr_priority = get_hdr_priority();
+ #if 0
+ data->isbestpolicy = is_best_outputmode();
+ data->isSupport4K30Hz = is_support_4k30hz();
+ data->isSupport4K = is_support_4k();
+ data->isDeepColor = is_support_deepcolor();
+ data->isLowPowerMode = is_low_powermode();
+ data->isframeratepriority = is_framerate_priority();
+ #endif
+ data->pRXCap = &hdev->RXCap;
+ /* memcpy(&(data->prxcap), &(hdev->RXCap), sizeof(hdev->RXCap)); */
+ printf("ubootenv dv_type: %d, hdr_priority: %d\n",
+ data->ubootenv_dv_type,
+ data->hdr_priority);
+ printf("ubootenv best_output: %d, framerate_priority: %d\n",
+ is_best_outputmode(),
+ is_framerate_priority());
+}
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_tvenc.c b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_tvenc.c
new file mode 100644
index 0000000..d334881
--- /dev/null
+++ b/drivers/amlogic/media/vout/hdmitx/hdmitx20/hdmitx_tvenc.c
@@ -0,0 +1,1400 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <amlogic/media/vout/hdmitx/hdmitx.h>
+#include "hdmitx_drv.h"
+
+#define MREG_END_MARKER 0xFFFF
+
+static const struct reg_s tvregs_720p[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+
+ {P_VENC_DVI_SETTING, 0x2029},
+ {P_ENCP_VIDEO_MODE, 0x4040},
+ {P_ENCP_VIDEO_MODE_ADV, 0x0018},
+ {P_ENCP_VIDEO_YFP1_HTIME, 648},
+ {P_ENCP_VIDEO_YFP2_HTIME, 3207},
+ {P_ENCP_VIDEO_MAX_PXCNT, 1649},
+ {P_ENCP_VIDEO_HSPULS_BEGIN, 80},
+ {P_ENCP_VIDEO_HSPULS_END, 240},
+ {P_ENCP_VIDEO_HSPULS_SWITCH, 80},
+ {P_ENCP_VIDEO_VSPULS_BEGIN, 688},
+ {P_ENCP_VIDEO_VSPULS_END, 3248},
+ {P_ENCP_VIDEO_VSPULS_BLINE, 4},
+ {P_ENCP_VIDEO_VSPULS_ELINE, 8},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 260},
+ {P_ENCP_VIDEO_HAVON_END, 1539},
+ {P_ENCP_VIDEO_VAVON_BLINE, 29},
+ {P_ENCP_VIDEO_VAVON_ELINE, 749},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0},
+ {P_ENCP_VIDEO_HSO_END, 168},
+ {P_ENCP_VIDEO_VSO_BEGIN, 168},
+ {P_ENCP_VIDEO_VSO_END, 256},
+ {P_ENCP_VIDEO_VSO_BLINE, 0},
+ {P_ENCP_VIDEO_VSO_ELINE, 5},
+ {P_ENCP_VIDEO_MAX_LNCNT, 749},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_720p_50hz[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_VENC_DVI_SETTING, 0x202d},
+ {P_ENCP_VIDEO_MAX_PXCNT, 1979},
+ {P_ENCP_VIDEO_MAX_LNCNT, 749},
+ {P_ENCP_VIDEO_HSPULS_BEGIN, 80},
+ {P_ENCP_VIDEO_HSPULS_END, 240},
+ {P_ENCP_VIDEO_HSPULS_SWITCH, 80},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 260},
+ {P_ENCP_VIDEO_HAVON_END, 1539},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0},
+ {P_ENCP_VIDEO_HSO_END, 40},
+ {P_ENCP_VIDEO_VSPULS_BEGIN, 688},
+ {P_ENCP_VIDEO_VSPULS_END, 3248},
+ {P_ENCP_VIDEO_VSPULS_BLINE, 4},
+ {P_ENCP_VIDEO_VSPULS_ELINE, 8},
+ {P_ENCP_VIDEO_VAVON_BLINE, 25},
+ {P_ENCP_VIDEO_VAVON_ELINE, 744},
+ {P_ENCP_VIDEO_VSO_BEGIN, 30},
+ {P_ENCP_VIDEO_VSO_END, 50},
+ {P_ENCP_VIDEO_VSO_BLINE, 0},
+ {P_ENCP_VIDEO_VSO_ELINE, 5},
+ {P_ENCP_VIDEO_YFP1_HTIME, 648},
+ {P_ENCP_VIDEO_YFP2_HTIME, 3207},
+ {P_VENC_VIDEO_PROG_MODE, 0x100},
+ {P_ENCP_VIDEO_MODE, 0x4040},
+ {P_ENCP_VIDEO_MODE_ADV, 0x0018},
+ {P_ENCP_VIDEO_SYNC_MODE, 0x407},
+ {P_ENCP_VIDEO_YC_DLY, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_480i[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_ENCI_CFILT_CTRL, 0x12},
+ {P_ENCI_CFILT_CTRL2, 0x12},
+ {P_VENC_DVI_SETTING, 0},
+ {P_ENCI_VIDEO_MODE, 0},
+ {P_ENCI_VIDEO_MODE_ADV, 0},
+ {P_ENCI_SYNC_HSO_BEGIN, 5},
+ {P_ENCI_SYNC_HSO_END, 129},
+ {P_ENCI_SYNC_VSO_EVNLN, 0x0003},
+ {P_ENCI_SYNC_VSO_ODDLN, 0x0104},
+ {P_ENCI_MACV_MAX_AMP, 0x810b},
+ {P_VENC_VIDEO_PROG_MODE, 0xf0},
+ {P_ENCI_VIDEO_MODE, 0x08},
+ {P_ENCI_VIDEO_MODE_ADV, 0x26},
+ {P_ENCI_VIDEO_SCH, 0x20},
+ {P_ENCI_SYNC_MODE, 0x07},
+ {P_ENCI_DBG_PX_RST, 0},
+ {P_ENCI_VFIFO2VD_CTL, 0x4e01},
+ {P_ENCI_VFIFO2VD_PIXEL_START, 0xf3,},
+ {P_ENCI_VFIFO2VD_PIXEL_END, 0x0693,},
+ {P_ENCI_VFIFO2VD_LINE_TOP_START, 0x12,},
+ {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,},
+ {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,},
+ {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,},
+ {P_ENCI_VIDEO_EN, 1},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_480p[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_ENCP_VIDEO_FILT_CTRL, 0x2052},
+ {P_VENC_DVI_SETTING, 0x21},
+ {P_ENCP_VIDEO_MODE, 0x4000},
+ {P_ENCP_VIDEO_MODE_ADV, 8},
+ {P_ENCP_VIDEO_YFP1_HTIME, 244},
+ {P_ENCP_VIDEO_YFP2_HTIME, 1630},
+ {P_ENCP_VIDEO_MAX_PXCNT, 857},
+ {P_ENCP_VIDEO_MAX_LNCNT, 524},
+ {P_ENCP_VIDEO_HSPULS_BEGIN, 0x22},
+ {P_ENCP_VIDEO_HSPULS_END, 0xa0},
+ {P_ENCP_VIDEO_HSPULS_SWITCH, 88},
+ {P_ENCP_VIDEO_VSPULS_BEGIN, 0},
+ {P_ENCP_VIDEO_VSPULS_END, 1589},
+ {P_ENCP_VIDEO_VSPULS_BLINE, 0},
+ {P_ENCP_VIDEO_VSPULS_ELINE, 5},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 122},
+ {P_ENCP_VIDEO_HAVON_END, 841},
+ {P_ENCP_VIDEO_VAVON_BLINE, 36},
+ {P_ENCP_VIDEO_VAVON_ELINE, 515},
+ {P_ENCP_VIDEO_SYNC_MODE, 0x07},
+ {P_VENC_VIDEO_PROG_MODE, 0x0},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0},
+ {P_ENCP_VIDEO_HSO_END, 62},
+ {P_ENCP_VIDEO_VSO_BEGIN, 30},
+ {P_ENCP_VIDEO_VSO_END, 50},
+ {P_ENCP_VIDEO_VSO_BLINE, 0},
+ {P_ENCP_VIDEO_VSO_ELINE, 6},
+ {P_ENCP_VIDEO_SY_VAL, 8},
+ {P_ENCP_VIDEO_SY2_VAL, 0x1d8},
+ {P_ENCP_DACSEL_0, 0x3102},
+ {P_ENCP_DACSEL_1, 0x0054},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_576i[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_VENC_DVI_SETTING, 0},
+ {P_ENCI_VIDEO_MODE, 0},
+ {P_ENCI_VIDEO_MODE_ADV, 0},
+ {P_ENCI_SYNC_HSO_BEGIN, 3},
+ {P_ENCI_SYNC_HSO_END, 129},
+ {P_ENCI_SYNC_VSO_EVNLN, 0x0003},
+ {P_ENCI_SYNC_VSO_ODDLN, 0x0104},
+ {P_ENCI_MACV_MAX_AMP, 0x8107},
+ {P_VENC_VIDEO_PROG_MODE, 0xff},
+ {P_ENCI_VIDEO_MODE, 0x13},
+ {P_ENCI_VIDEO_MODE_ADV, 0x26},
+ {P_ENCI_VIDEO_SCH, 0x28},
+ {P_ENCI_SYNC_MODE, 0x07},
+ {P_ENCI_YC_DELAY, 0x333},
+ {P_ENCI_VFIFO2VD_PIXEL_START, 0x010b},
+ {P_ENCI_VFIFO2VD_PIXEL_END, 0x06ab},
+ {P_ENCI_VFIFO2VD_LINE_TOP_START, 0x0016},
+ {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136},
+ {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017},
+ {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137},
+ {P_ENCI_DBG_PX_RST, 0},
+ {P_ENCI_VFIFO2VD_CTL, 0x4e01},
+ {P_ENCI_VFIFO2VD_PIXEL_START, 0x010b},
+ {P_ENCI_VFIFO2VD_PIXEL_END, 0x06ab},
+ {P_ENCI_VFIFO2VD_LINE_TOP_START, 0x0016},
+ {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136},
+ {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017},
+ {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137},
+ {P_ENCI_VIDEO_EN, 1},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_576p[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_ENCP_VIDEO_FILT_CTRL, 0x52},
+ {P_VENC_DVI_SETTING, 0x21},
+ {P_ENCP_VIDEO_MODE, 0x4000},
+ {P_ENCP_VIDEO_MODE_ADV, 8},
+ {P_ENCP_VIDEO_YFP1_HTIME, 235},
+ {P_ENCP_VIDEO_YFP2_HTIME, 1674},
+ {P_ENCP_VIDEO_MAX_PXCNT, 863},
+ {P_ENCP_VIDEO_MAX_LNCNT, 624},
+ {P_ENCP_VIDEO_HSPULS_BEGIN, 0},
+ {P_ENCP_VIDEO_HSPULS_END, 0x80},
+ {P_ENCP_VIDEO_HSPULS_SWITCH, 88},
+ {P_ENCP_VIDEO_VSPULS_BEGIN, 0},
+ {P_ENCP_VIDEO_VSPULS_END, 1599},
+ {P_ENCP_VIDEO_VSPULS_BLINE, 0},
+ {P_ENCP_VIDEO_VSPULS_ELINE, 4},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 132},
+ {P_ENCP_VIDEO_HAVON_END, 851},
+ {P_ENCP_VIDEO_VAVON_BLINE, 44},
+ {P_ENCP_VIDEO_VAVON_ELINE, 619},
+ {P_ENCP_VIDEO_SYNC_MODE, 0x07},
+ {P_VENC_VIDEO_PROG_MODE, 0x0},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0},
+ {P_ENCP_VIDEO_HSO_END, 64},
+ {P_ENCP_VIDEO_VSO_BEGIN, 30},
+ {P_ENCP_VIDEO_VSO_END, 50},
+ {P_ENCP_VIDEO_VSO_BLINE, 0},
+ {P_ENCP_VIDEO_VSO_BLINE, 5},
+ {P_ENCP_VIDEO_SY_VAL, 8},
+ {P_ENCP_VIDEO_SY2_VAL, 0x1d8},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_1080i[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_VENC_DVI_SETTING, 0x2029},
+ {P_ENCP_VIDEO_MAX_PXCNT, 2199},
+ {P_ENCP_VIDEO_MAX_LNCNT, 1124},
+ {P_ENCP_VIDEO_HSPULS_BEGIN, 88},
+ {P_ENCP_VIDEO_HSPULS_END, 264},
+ {P_ENCP_VIDEO_HSPULS_SWITCH, 88},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 192},
+ {P_ENCP_VIDEO_HAVON_END, 2111},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0},
+ {P_ENCP_VIDEO_HSO_END, 44},
+ {P_ENCP_VIDEO_EQPULS_BEGIN, 2288},
+ {P_ENCP_VIDEO_EQPULS_END, 2464},
+ {P_ENCP_VIDEO_VSPULS_BEGIN, 440},
+ {P_ENCP_VIDEO_VSPULS_END, 2200},
+ {P_ENCP_VIDEO_VSPULS_BLINE, 0},
+ {P_ENCP_VIDEO_VSPULS_ELINE, 4},
+ {P_ENCP_VIDEO_EQPULS_BLINE, 0},
+ {P_ENCP_VIDEO_EQPULS_ELINE, 4},
+ {P_ENCP_VIDEO_VAVON_BLINE, 20},
+ {P_ENCP_VIDEO_VAVON_ELINE, 559},
+ {P_ENCP_VIDEO_VSO_BEGIN, 30},
+ {P_ENCP_VIDEO_VSO_END, 50},
+ {P_ENCP_VIDEO_VSO_BLINE, 0},
+ {P_ENCP_VIDEO_VSO_ELINE, 5},
+ {P_ENCP_VIDEO_YFP1_HTIME, 516},
+ {P_ENCP_VIDEO_YFP2_HTIME, 4355},
+ {P_VENC_VIDEO_PROG_MODE, 0x100},
+ {P_ENCP_VIDEO_OFLD_VOAV_OFST, 0x11},
+ {P_ENCP_VIDEO_MODE, 0x5ffc},
+ {P_ENCP_VIDEO_MODE_ADV, 0x0018},
+ {P_ENCP_VIDEO_SYNC_MODE, 0x207},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_1080i_50hz[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_VENC_DVI_SETTING, 0x202d},
+ {P_ENCP_VIDEO_MAX_PXCNT, 2639},
+ {P_ENCP_VIDEO_MAX_LNCNT, 1124},
+ {P_ENCP_VIDEO_HSPULS_BEGIN, 88},
+ {P_ENCP_VIDEO_HSPULS_END, 264},
+ {P_ENCP_VIDEO_HSPULS_SWITCH, 88},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 192},
+ {P_ENCP_VIDEO_HAVON_END, 2111},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0},
+ {P_ENCP_VIDEO_HSO_END, 44},
+ {P_ENCP_VIDEO_VSPULS_BEGIN, 440},
+ {P_ENCP_VIDEO_VSPULS_END, 2200},
+ {P_ENCP_VIDEO_VSPULS_BLINE, 0},
+ {P_ENCP_VIDEO_VSPULS_ELINE, 4},
+ {P_ENCP_VIDEO_VAVON_BLINE, 20},
+ {P_ENCP_VIDEO_VAVON_ELINE, 559},
+ {P_ENCP_VIDEO_VSO_BEGIN, 30},
+ {P_ENCP_VIDEO_VSO_END, 50},
+ {P_ENCP_VIDEO_VSO_BLINE, 0},
+ {P_ENCP_VIDEO_VSO_ELINE, 5},
+ {P_ENCP_VIDEO_YFP1_HTIME, 526},
+ {P_ENCP_VIDEO_YFP2_HTIME, 4365},
+ {P_VENC_VIDEO_PROG_MODE, 0x100},
+ {P_ENCP_VIDEO_OFLD_VOAV_OFST, 0x11},
+ {P_ENCP_VIDEO_MODE, 0x5ffc},
+ {P_ENCP_VIDEO_MODE_ADV, 0x0018},
+ {P_ENCP_VIDEO_SYNC_MODE, 0x7},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_1080p[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_ENCP_VIDEO_FILT_CTRL, 0x1052},
+ {P_VENC_DVI_SETTING, 0x0001},
+ {P_ENCP_VIDEO_MODE, 0x4040},
+ {P_ENCP_VIDEO_MODE_ADV, 0x0018},
+ {P_ENCP_VIDEO_YFP1_HTIME, 140},
+ {P_ENCP_VIDEO_YFP2_HTIME, 2060},
+ {P_ENCP_VIDEO_MAX_PXCNT, 2199},
+ {P_ENCP_VIDEO_HSPULS_BEGIN, 2156},
+ {P_ENCP_VIDEO_HSPULS_END, 44},
+ {P_ENCP_VIDEO_HSPULS_SWITCH, 44},
+ {P_ENCP_VIDEO_VSPULS_BEGIN, 140},
+ {P_ENCP_VIDEO_VSPULS_END, 2059},
+ {P_ENCP_VIDEO_VSPULS_BLINE, 0},
+ {P_ENCP_VIDEO_VSPULS_ELINE, 4},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 148},
+ {P_ENCP_VIDEO_HAVON_END, 2067},
+ {P_ENCP_VIDEO_VAVON_BLINE, 42},
+ {P_ENCP_VIDEO_VAVON_ELINE, 1121},
+ {P_ENCP_VIDEO_HSO_BEGIN, 44},
+ {P_ENCP_VIDEO_HSO_END, 2156},
+ {P_ENCP_VIDEO_VSO_BEGIN, 2100},
+ {P_ENCP_VIDEO_VSO_END, 2164},
+ {P_ENCP_VIDEO_VSO_BLINE, 0},
+ {P_ENCP_VIDEO_VSO_ELINE, 5},
+ {P_ENCP_VIDEO_MAX_LNCNT, 1124},
+ {P_VENC_VIDEO_PROG_MODE, 0x100},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_1080p_50hz[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_VENC_DVI_SETTING, 0x000d},
+ {P_ENCP_VIDEO_MAX_PXCNT, 2639},
+ {P_ENCP_VIDEO_MAX_LNCNT, 1124},
+ {P_ENCP_VIDEO_HSPULS_BEGIN, 44},
+ {P_ENCP_VIDEO_HSPULS_END, 132},
+ {P_ENCP_VIDEO_HSPULS_SWITCH, 44},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 271},
+ {P_ENCP_VIDEO_HAVON_END, 2190},
+ {P_ENCP_VIDEO_HSO_BEGIN, 79},
+ {P_ENCP_VIDEO_HSO_END, 123},
+ {P_ENCP_VIDEO_VSPULS_BEGIN, 220},
+ {P_ENCP_VIDEO_VSPULS_END, 2140},
+ {P_ENCP_VIDEO_VSPULS_BLINE, 0},
+ {P_ENCP_VIDEO_VSPULS_ELINE, 4},
+ {P_ENCP_VIDEO_EQPULS_BLINE, 0},
+ {P_ENCP_VIDEO_EQPULS_ELINE, 4},
+ {P_ENCP_VIDEO_VAVON_BLINE, 41},
+ {P_ENCP_VIDEO_VAVON_ELINE, 1120},
+ {P_ENCP_VIDEO_VSO_BEGIN, 79},
+ {P_ENCP_VIDEO_VSO_END, 79},
+ {P_ENCP_VIDEO_VSO_BLINE, 0},
+ {P_ENCP_VIDEO_VSO_ELINE, 5},
+ {P_ENCP_VIDEO_YFP1_HTIME, 271},
+ {P_ENCP_VIDEO_YFP2_HTIME, 2190},
+ {P_VENC_VIDEO_PROG_MODE, 0x100},
+ {P_ENCP_VIDEO_MODE, 0x4040},
+ {P_ENCP_VIDEO_MODE_ADV, 0x0018},
+ {P_ENCP_VIDEO_SYNC_MODE, 0x7},
+ {P_ENCP_VIDEO_YC_DLY, 0},
+ {P_ENCP_VIDEO_RGB_CTRL, 2},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_1080p_24hz[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_ENCP_VIDEO_FILT_CTRL, 0x1052},
+ {P_VENC_DVI_SETTING, 0x000d},
+ {P_ENCP_VIDEO_MAX_PXCNT, 2749},
+ {P_ENCP_VIDEO_MAX_LNCNT, 1124},
+ {P_ENCP_VIDEO_HSPULS_BEGIN, 44},
+ {P_ENCP_VIDEO_HSPULS_END, 132},
+ {P_ENCP_VIDEO_HSPULS_SWITCH, 44},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 271},
+ {P_ENCP_VIDEO_HAVON_END, 2190},
+ {P_ENCP_VIDEO_HSO_BEGIN, 79},
+ {P_ENCP_VIDEO_HSO_END, 123},
+ {P_ENCP_VIDEO_VSPULS_BEGIN, 220},
+ {P_ENCP_VIDEO_VSPULS_END, 2140},
+ {P_ENCP_VIDEO_VSPULS_BLINE, 0},
+ {P_ENCP_VIDEO_VSPULS_ELINE, 4},
+ {P_ENCP_VIDEO_EQPULS_BLINE, 0},
+ {P_ENCP_VIDEO_EQPULS_ELINE, 4},
+ {P_ENCP_VIDEO_VAVON_BLINE, 41},
+ {P_ENCP_VIDEO_VAVON_ELINE, 1120},
+ {P_ENCP_VIDEO_VSO_BEGIN, 79},
+ {P_ENCP_VIDEO_VSO_END, 79},
+ {P_ENCP_VIDEO_VSO_BLINE, 0},
+ {P_ENCP_VIDEO_VSO_ELINE, 5},
+ {P_ENCP_VIDEO_YFP1_HTIME, 271},
+ {P_ENCP_VIDEO_YFP2_HTIME, 2190},
+ {P_VENC_VIDEO_PROG_MODE, 0x100},
+ {P_ENCP_VIDEO_MODE, 0x4040},
+ {P_ENCP_VIDEO_MODE_ADV, 0x0018},
+ {P_ENCP_VIDEO_SYNC_MODE, 0x7},
+ {P_ENCP_VIDEO_YC_DLY, 0},
+ {P_ENCP_VIDEO_RGB_CTRL, 2},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_4k2k_30hz[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_ENCP_VIDEO_MODE, 0x4040},
+ {P_ENCP_VIDEO_MODE_ADV, 0x0008},
+ {P_ENCP_VIDEO_YFP1_HTIME, 140},
+ {P_ENCP_VIDEO_YFP2_HTIME, 140+3840},
+ {P_ENCP_VIDEO_MAX_PXCNT, 3840+560-1},
+ {P_ENCP_VIDEO_HSPULS_BEGIN, 2156+1920},
+ {P_ENCP_VIDEO_HSPULS_END, 44},
+ {P_ENCP_VIDEO_HSPULS_SWITCH, 44},
+ {P_ENCP_VIDEO_VSPULS_BEGIN, 140},
+ {P_ENCP_VIDEO_VSPULS_END, 2059+1920},
+ {P_ENCP_VIDEO_VSPULS_BLINE, 0},
+ {P_ENCP_VIDEO_VSPULS_ELINE, 4},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 148},
+ {P_ENCP_VIDEO_HAVON_END, 3987},
+ {P_ENCP_VIDEO_VAVON_BLINE, 89},
+ {P_ENCP_VIDEO_VAVON_ELINE, 2248},
+ {P_ENCP_VIDEO_HSO_BEGIN, 44},
+ {P_ENCP_VIDEO_HSO_END, 2156+1920},
+ {P_ENCP_VIDEO_VSO_BEGIN, 2100+1920},
+ {P_ENCP_VIDEO_VSO_END, 2164+1920},
+ {P_ENCP_VIDEO_VSO_BLINE, 51},
+ {P_ENCP_VIDEO_VSO_ELINE, 53},
+ {P_ENCP_VIDEO_MAX_LNCNT, 2249},
+ {P_ENCP_VIDEO_FILT_CTRL, 0x1000},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_4k2k_25hz[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_ENCP_VIDEO_MODE, 0x4040},
+ {P_ENCP_VIDEO_MODE_ADV, 0x0008},
+ {P_ENCP_VIDEO_YFP1_HTIME, 140},
+ {P_ENCP_VIDEO_YFP2_HTIME, 140+3840},
+ {P_ENCP_VIDEO_MAX_PXCNT, 3840+1440-1},
+ {P_ENCP_VIDEO_HSPULS_BEGIN, 2156+1920},
+ {P_ENCP_VIDEO_HSPULS_END, 44},
+ {P_ENCP_VIDEO_HSPULS_SWITCH, 44},
+ {P_ENCP_VIDEO_VSPULS_BEGIN, 140},
+ {P_ENCP_VIDEO_VSPULS_END, 2059+1920},
+ {P_ENCP_VIDEO_VSPULS_BLINE, 0},
+ {P_ENCP_VIDEO_VSPULS_ELINE, 4},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 148},
+ {P_ENCP_VIDEO_HAVON_END, 3987},
+ {P_ENCP_VIDEO_VAVON_BLINE, 89},
+ {P_ENCP_VIDEO_VAVON_ELINE, 2248},
+ {P_ENCP_VIDEO_HSO_BEGIN, 44},
+ {P_ENCP_VIDEO_HSO_END, 2156+1920},
+ {P_ENCP_VIDEO_VSO_BEGIN, 2100+1920},
+ {P_ENCP_VIDEO_VSO_END, 2164+1920},
+ {P_ENCP_VIDEO_VSO_BLINE, 51},
+ {P_ENCP_VIDEO_VSO_ELINE, 53},
+ {P_ENCP_VIDEO_MAX_LNCNT, 2249},
+ {P_ENCP_VIDEO_FILT_CTRL, 0x1000},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_4k2k_24hz[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_ENCP_VIDEO_MODE, 0x4040},
+ {P_ENCP_VIDEO_MODE_ADV, 0x0008},
+ {P_ENCP_VIDEO_YFP1_HTIME, 140},
+ {P_ENCP_VIDEO_YFP2_HTIME, 140+3840},
+ {P_ENCP_VIDEO_MAX_PXCNT, 3840+1660-1},
+ {P_ENCP_VIDEO_HSPULS_BEGIN, 2156+1920},
+ {P_ENCP_VIDEO_HSPULS_END, 44},
+ {P_ENCP_VIDEO_HSPULS_SWITCH, 44},
+ {P_ENCP_VIDEO_VSPULS_BEGIN, 140},
+ {P_ENCP_VIDEO_VSPULS_END, 2059+1920},
+ {P_ENCP_VIDEO_VSPULS_BLINE, 0},
+ {P_ENCP_VIDEO_VSPULS_ELINE, 4},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 148},
+ {P_ENCP_VIDEO_HAVON_END, 3987},
+ {P_ENCP_VIDEO_VAVON_BLINE, 89},
+ {P_ENCP_VIDEO_VAVON_ELINE, 2248},
+ {P_ENCP_VIDEO_HSO_BEGIN, 44},
+ {P_ENCP_VIDEO_HSO_END, 2156+1920},
+ {P_ENCP_VIDEO_VSO_BEGIN, 2100+1920},
+ {P_ENCP_VIDEO_VSO_END, 2164+1920},
+ {P_ENCP_VIDEO_VSO_BLINE, 51},
+ {P_ENCP_VIDEO_VSO_ELINE, 53},
+ {P_ENCP_VIDEO_MAX_LNCNT, 2249},
+ {P_ENCP_VIDEO_FILT_CTRL, 0x1000},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_4k2k_smpte[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_ENCP_VIDEO_MODE, 0x4040},
+ {P_ENCP_VIDEO_MODE_ADV, 0x0008},
+ {P_ENCP_VIDEO_YFP1_HTIME, 140},
+ {P_ENCP_VIDEO_YFP2_HTIME, 140+3840+256},
+ {P_ENCP_VIDEO_MAX_PXCNT, 4096+1404-1},
+ {P_ENCP_VIDEO_HSPULS_BEGIN, 2156+1920},
+ {P_ENCP_VIDEO_HSPULS_END, 44},
+ {P_ENCP_VIDEO_HSPULS_SWITCH, 44},
+ {P_ENCP_VIDEO_VSPULS_BEGIN, 140},
+ {P_ENCP_VIDEO_VSPULS_END, 2059+1920},
+ {P_ENCP_VIDEO_VSPULS_BLINE, 0},
+ {P_ENCP_VIDEO_VSPULS_ELINE, 4},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 148},
+ {P_ENCP_VIDEO_HAVON_END, 3987+256},
+ {P_ENCP_VIDEO_VAVON_BLINE, 89},
+ {P_ENCP_VIDEO_VAVON_ELINE, 2248},
+ {P_ENCP_VIDEO_HSO_BEGIN, 44},
+ {P_ENCP_VIDEO_HSO_END, 2156+1920+256},
+ {P_ENCP_VIDEO_VSO_BEGIN, 2100+1920+256},
+ {P_ENCP_VIDEO_VSO_END, 2164+1920+256},
+ {P_ENCP_VIDEO_VSO_BLINE, 51},
+ {P_ENCP_VIDEO_VSO_ELINE, 53},
+ {P_ENCP_VIDEO_MAX_LNCNT, 2249},
+ {P_ENCP_VIDEO_FILT_CTRL, 0x1000},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_4k2k_smpte_25hz[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x149F,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x8C9,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0xD8,},
+ {P_ENCP_VIDEO_HAVON_END, 0x10D7,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x52,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x8C1,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x58,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0xA,},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_4k2k_smpte_30hz[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x112F,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x8C9,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0xD8,},
+ {P_ENCP_VIDEO_HAVON_END, 0x10D7,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x52,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x8C1,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x58,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0xA,},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_4k2k_smpte_50hz[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x149F,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x8C9,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0xD8,},
+ {P_ENCP_VIDEO_HAVON_END, 0x10D7,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x52,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x8C1,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x58,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0xA,},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_4k2k_smpte_60hz[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x112F,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x8C9,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0xD8,},
+ {P_ENCP_VIDEO_HAVON_END, 0x10D7,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x52,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x8C1,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x58,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0xA,},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_2560x1080p50hz[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_VENC_DVI_SETTING, 0x000d},
+ {P_ENCP_VIDEO_MAX_PXCNT, 3299},
+ {P_ENCP_VIDEO_MAX_LNCNT, 1124},
+ {P_ENCP_VIDEO_HSPULS_BEGIN, 44},
+ {P_ENCP_VIDEO_HSPULS_END, 132},
+ {P_ENCP_VIDEO_HSPULS_SWITCH, 44},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 192},
+ {P_ENCP_VIDEO_HAVON_END, 2751},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0},
+ {P_ENCP_VIDEO_HSO_END, 44},
+ {P_ENCP_VIDEO_VSPULS_BEGIN, 220},
+ {P_ENCP_VIDEO_VSPULS_END, 2140},
+ {P_ENCP_VIDEO_VSPULS_BLINE, 0},
+ {P_ENCP_VIDEO_VSPULS_ELINE, 4},
+ {P_ENCP_VIDEO_EQPULS_BLINE, 0},
+ {P_ENCP_VIDEO_EQPULS_ELINE, 4},
+ {P_ENCP_VIDEO_VAVON_BLINE, 41},
+ {P_ENCP_VIDEO_VAVON_ELINE, 1120},
+ {P_ENCP_VIDEO_VSO_BEGIN, 79},
+ {P_ENCP_VIDEO_VSO_END, 79},
+ {P_ENCP_VIDEO_VSO_BLINE, 0},
+ {P_ENCP_VIDEO_VSO_ELINE, 5},
+ {P_ENCP_VIDEO_YFP1_HTIME, 271},
+ {P_ENCP_VIDEO_YFP2_HTIME, 2190},
+ {P_VENC_VIDEO_PROG_MODE, 0x100},
+ {P_ENCP_VIDEO_MODE, 0x4040},
+ {P_ENCP_VIDEO_MODE_ADV, 0x0018},
+ {P_ENCP_VIDEO_SYNC_MODE, 0x7},
+ {P_ENCP_VIDEO_YC_DLY, 0},
+ {P_ENCP_VIDEO_RGB_CTRL, 2},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_2560x1080p60hz[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_VENC_DVI_SETTING, 0x000d},
+ {P_ENCP_VIDEO_MAX_PXCNT, 2999},
+ {P_ENCP_VIDEO_MAX_LNCNT, 1099},
+ {P_ENCP_VIDEO_HSPULS_BEGIN, 44},
+ {P_ENCP_VIDEO_HSPULS_END, 132},
+ {P_ENCP_VIDEO_HSPULS_SWITCH, 44},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 192},
+ {P_ENCP_VIDEO_HAVON_END, 2751},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0},
+ {P_ENCP_VIDEO_HSO_END, 44},
+ {P_ENCP_VIDEO_VSPULS_BEGIN, 220},
+ {P_ENCP_VIDEO_VSPULS_END, 2140},
+ {P_ENCP_VIDEO_VSPULS_BLINE, 0},
+ {P_ENCP_VIDEO_VSPULS_ELINE, 4},
+ {P_ENCP_VIDEO_EQPULS_BLINE, 0},
+ {P_ENCP_VIDEO_EQPULS_ELINE, 4},
+ {P_ENCP_VIDEO_VAVON_BLINE, 16},
+ {P_ENCP_VIDEO_VAVON_ELINE, 1095},
+ {P_ENCP_VIDEO_VSO_BEGIN, 79},
+ {P_ENCP_VIDEO_VSO_END, 79},
+ {P_ENCP_VIDEO_VSO_BLINE, 0},
+ {P_ENCP_VIDEO_VSO_ELINE, 5},
+ {P_ENCP_VIDEO_YFP1_HTIME, 271},
+ {P_ENCP_VIDEO_YFP2_HTIME, 2190},
+ {P_VENC_VIDEO_PROG_MODE, 0x100},
+ {P_ENCP_VIDEO_MODE, 0x4040},
+ {P_ENCP_VIDEO_MODE_ADV, 0x0018},
+ {P_ENCP_VIDEO_SYNC_MODE, 0x7},
+ {P_ENCP_VIDEO_YC_DLY, 0},
+ {P_ENCP_VIDEO_RGB_CTRL, 2},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_vesa_640x480p60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x31F,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x20C,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x90,},
+ {P_ENCP_VIDEO_HAVON_END, 0x30F,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x23,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x202,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x60,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x2,},
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_800x600p60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x41F,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x273,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0xD8,},
+ {P_ENCP_VIDEO_HAVON_END, 0x3F7,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x1B,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x272,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x80,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x4,},
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_800x480p60hz[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+ {P_VENC_VDAC_SETTING, 0xff},
+ {P_ENCP_VIDEO_MODE, 0x4040},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x3DF},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x1F3},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0xA8},
+ {P_ENCP_VIDEO_HAVON_END, 0x3C7},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x11},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x1F0},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0},
+ {P_ENCP_VIDEO_HSO_END, 0x48},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E},
+ {P_ENCP_VIDEO_VSO_END, 0x32},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x7},
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_vesa_852x480p60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x3B3,},/*947//htotal-1*/
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x213,},/*531//vtotal-1*/
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x38,},/*56//hblank-hfront*/
+ {P_ENCP_VIDEO_HAVON_END, 0x38B,},/*907//htotal-hfront-1*/
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x2A,},/*42//vblank-vfront*/
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x209,},/*521//vtotal-vfront-1*/
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x10,},/*16/hor sync time*/
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x2,},/*2//ver sync time*/
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_854x480p60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x3B5,},/*949//htotal-1*/
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x212,},/*530//vtotal-1*/
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x38,},/*56//hblank-hfront*/
+ {P_ENCP_VIDEO_HAVON_END, 0x38D,},/*909//htotal-hfront-1*/
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x29,},/*41//vblank-vfront*/
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x208,},/*520//vtotal-vfront-1*/
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x10,},/*16//hor sync time*/
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x2,},/*2//ver sync time*/
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_1024x600p60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x53F,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x27D,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x128,},
+ {P_ENCP_VIDEO_HAVON_END, 0x527,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x23,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x27A,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x88,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x6,},
+
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_1024x768p60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x53F,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x325,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x128,},
+ {P_ENCP_VIDEO_HAVON_END, 0x527,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x23,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x322,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x88,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x6,},
+
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_1152x864p75hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x63F,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x383,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x180,},
+ {P_ENCP_VIDEO_HAVON_END, 0x5FF,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x23,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x382,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x80,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x3,},
+
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_1280x600p60hz[] = {
+#if 0
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+ {P_VENC_VDAC_SETTING, 0xff,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x59F,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x336,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x70,},
+ {P_ENCP_VIDEO_HAVON_END, 0x56F,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x14,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x333,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x20,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x6,},
+
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0}
+#endif
+};
+
+static const struct reg_s tvregs_vesa_1280x768p60hz[] = {
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+ {P_VENC_VDAC_SETTING, 0xff,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x67F,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x31D,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x140,},
+ {P_ENCP_VIDEO_HAVON_END, 0x63F,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x1B,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x31A,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x80,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x7,},
+
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_1280x800p60hz[] = {
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+ {P_VENC_VDAC_SETTING, 0xff,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x59F,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x336,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x70,},
+ {P_ENCP_VIDEO_HAVON_END, 0x56F,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x14,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x333,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x20,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x6,},
+
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_1280x960p60hz[] = {
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+ {P_VENC_VDAC_SETTING, 0xff,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x707,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x3E7,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x1A8,},
+ {P_ENCP_VIDEO_HAVON_END, 0x6A7,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x27,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x3E6,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x70,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x3,},
+
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_1280x1024p60hz[] = {
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+ {P_VENC_VDAC_SETTING, 0xff,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x697,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x429,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x168,},
+ {P_ENCP_VIDEO_HAVON_END, 0x667,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x29,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x428,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x70,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x3,},
+
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_1360x768p60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x6FF,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x31A,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x170,},
+ {P_ENCP_VIDEO_HAVON_END, 0x6BF,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x18,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x317,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x70,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x6,},
+
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_1366x768p60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x6FF,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x31D,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x164,},
+ {P_ENCP_VIDEO_HAVON_END, 0x6B9,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x1B,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x31A,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x8F,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x3,},
+
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_1400x1050p60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x747,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x440,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x178,},
+ {P_ENCP_VIDEO_HAVON_END, 0x6EF,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x24,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x43D,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x90,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x4,},
+
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_1440x900p60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x76F,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x3A5,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x180,},
+ {P_ENCP_VIDEO_HAVON_END, 0x71F,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x1F,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x3A2,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x98,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x6,},
+
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_1440x2560p60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x623,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0xA23,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x44,},
+ {P_ENCP_VIDEO_HAVON_END, 0x5E3,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x14,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0xA13,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x4,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x4,},
+
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_1600x900p60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x707,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x3E7,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0xB0,},
+ {P_ENCP_VIDEO_HAVON_END, 0x6EF,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x63,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x3E6,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x50,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x3,},
+
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_1600x1200p60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x86F,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x4E1,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x1F0,},
+ {P_ENCP_VIDEO_HAVON_END, 0x82F,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x31,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x4E0,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0xC0,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x3,},
+
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_1680x1050p60hz[] = {
+ {P_VENC_VDAC_SETTING, 0xff,},
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x8BF,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x440,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x1C8,},
+ {P_ENCP_VIDEO_HAVON_END, 0x857,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x24,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x43D,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0xB0,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x6,},
+
+ {P_ENCI_VIDEO_EN, 0,},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_1920x1200p60hz[] = {
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+ {P_VENC_VDAC_SETTING, 0xff,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0xA1F,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x4DC,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x218,},
+ {P_ENCP_VIDEO_HAVON_END, 0x997,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x2A,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x4D9,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0xC8,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x6,},
+
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_2160x1200p90hz[] = {
+ {P_ENCP_VIDEO_EN, 0},
+ {P_ENCI_VIDEO_EN, 0},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x99D,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x4BB,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x70,},
+ {P_ENCP_VIDEO_HAVON_END, 0x8DF,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x6,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x4B5,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x20,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x3,},
+
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0},
+};
+
+static const struct reg_s tvregs_vesa_2560x1600p60hz[] = {
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+ {P_VENC_VDAC_SETTING, 0xff,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0xDAF,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x679,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x2F0,},
+ {P_ENCP_VIDEO_HAVON_END, 0xCEF,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x37,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x676,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x118,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x6,},
+
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_3440x1440p60hz[] = {
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+ {P_VENC_VDAC_SETTING, 0xff,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0xE0F,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x5C8,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x70,},
+ {P_ENCP_VIDEO_HAVON_END, 0xDDF,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x26,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x5C5,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x20,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0xA,},
+
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0}
+};
+
+static const struct reg_s tvregs_vesa_2400x1200p90hz[] = {
+ {P_ENCP_VIDEO_EN, 0,},
+ {P_ENCI_VIDEO_EN, 0,},
+ {P_VENC_VDAC_SETTING, 0xff,},
+
+ {P_ENCP_VIDEO_MODE, 0x4040,},
+ {P_ENCP_VIDEO_MODE_ADV, 0x18,},
+ {P_ENCP_VIDEO_MAX_PXCNT, 0x9B1,},
+ {P_ENCP_VIDEO_MAX_LNCNT, 0x4E3,},
+ {P_ENCP_VIDEO_HAVON_BEGIN, 0x3E,},
+ {P_ENCP_VIDEO_HAVON_END, 0x99D,},
+ {P_ENCP_VIDEO_VAVON_BLINE, 0x23,},
+ {P_ENCP_VIDEO_VAVON_ELINE, 0x4D2,},
+ {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
+ {P_ENCP_VIDEO_HSO_END, 0x1E,},
+ {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
+ {P_ENCP_VIDEO_VSO_END, 0x32,},
+ {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
+ {P_ENCP_VIDEO_VSO_ELINE, 0x5,},
+
+ {P_ENCI_VIDEO_EN, 0},
+ {MREG_END_MARKER, 0}
+};
+
+struct vic_tvregs_set {
+ enum hdmi_vic vic;
+ const struct reg_s *reg_setting;
+};
+
+/* Using HDMI VIC as index */
+static struct vic_tvregs_set tvregsTab[] = {
+ {HDMI_720x480i60_16x9, tvregs_480i},
+ {HDMI_720x480i60_4x3, tvregs_480i},
+ {HDMI_2880x480i60_16x9, tvregs_480i},
+ {HDMI_720x480p60_16x9, tvregs_480p},
+ {HDMI_720x480p60_4x3, tvregs_480p},
+ {HDMI_2880x240p60_16x9, tvregs_480p},
+ {HDMI_720x576i50_16x9, tvregs_576i},
+ {HDMI_720x576i50_4x3, tvregs_576i},
+ {HDMI_2880x576i50_16x9, tvregs_576i},
+ {HDMI_720x576p50_16x9, tvregs_576p},
+ {HDMI_720x576p50_4x3, tvregs_576p},
+ {HDMI_2880x576p50_16x9, tvregs_576p},
+ {HDMI_1280x720p60_16x9, tvregs_720p},
+ {HDMI_1920x1080i60_16x9, tvregs_1080i},
+ {HDMI_1920x1080p60_16x9, tvregs_1080p},
+ {HDMI_1920x1080p120_16x9, tvregs_1080p},
+ {HDMI_1280x720p50_16x9, tvregs_720p_50hz},
+ {HDMI_1920x1080i50_16x9, tvregs_1080i_50hz},
+ {HDMI_1920x1080p50_16x9, tvregs_1080p_50hz},
+ {HDMI_1920x1080p25_16x9, tvregs_1080p_50hz},
+ {HDMI_1920x1080p30_16x9, tvregs_1080p},
+ {HDMI_1920x1080p24_16x9, tvregs_1080p_24hz},
+ {HDMI_3840x2160p30_16x9, tvregs_4k2k_30hz},
+ {HDMI_3840x2160p25_16x9, tvregs_4k2k_25hz},
+ {HDMI_3840x2160p24_16x9, tvregs_4k2k_24hz},
+ {HDMI_4096x2160p24_256x135, tvregs_4k2k_smpte},
+ {HDMI_4096x2160p25_256x135, tvregs_4k2k_smpte_25hz},
+ {HDMI_4096x2160p30_256x135, tvregs_4k2k_smpte_30hz},
+ {HDMI_4096x2160p50_256x135, tvregs_4k2k_smpte_50hz},
+ {HDMI_4096x2160p60_256x135, tvregs_4k2k_smpte_60hz},
+ {HDMI_4096x2160p60_256x135_Y420, tvregs_4k2k_smpte_60hz},
+ {HDMI_4096x2160p50_256x135_Y420, tvregs_4k2k_smpte_50hz},
+ {HDMI_3840x2160p60_16x9, tvregs_4k2k_30hz},
+ {HDMI_3840x2160p50_16x9, tvregs_4k2k_25hz},
+ {HDMI_3840x2160p60_16x9_Y420, tvregs_4k2k_30hz},
+ {HDMI_3840x2160p50_16x9_Y420, tvregs_4k2k_25hz},
+ {HDMI_2560x1080p50_64x27, tvregs_2560x1080p50hz},
+ {HDMI_2560x1080p60_64x27, tvregs_2560x1080p60hz},
+ {HDMIV_640x480p60hz, tvregs_vesa_640x480p60hz},
+ {HDMIV_800x480p60hz, tvregs_vesa_800x480p60hz},
+ {HDMIV_800x600p60hz, tvregs_vesa_800x600p60hz},
+ {HDMIV_852x480p60hz, tvregs_vesa_852x480p60hz},
+ {HDMIV_854x480p60hz, tvregs_vesa_854x480p60hz},
+ {HDMIV_1024x600p60hz, tvregs_vesa_1024x600p60hz},
+ {HDMIV_1024x768p60hz, tvregs_vesa_1024x768p60hz},
+ {HDMIV_1152x864p75hz, tvregs_vesa_1152x864p75hz},
+ {HDMIV_1280x600p60hz, tvregs_vesa_1280x600p60hz},
+ {HDMIV_1280x768p60hz, tvregs_vesa_1280x768p60hz},
+ {HDMIV_1280x800p60hz, tvregs_vesa_1280x800p60hz},
+ {HDMIV_1280x960p60hz, tvregs_vesa_1280x960p60hz},
+ {HDMIV_1280x1024p60hz, tvregs_vesa_1280x1024p60hz},
+ {HDMIV_1360x768p60hz, tvregs_vesa_1360x768p60hz},
+ {HDMIV_1366x768p60hz, tvregs_vesa_1366x768p60hz},
+ {HDMIV_1400x1050p60hz, tvregs_vesa_1400x1050p60hz},
+ {HDMIV_1440x900p60hz, tvregs_vesa_1440x900p60hz},
+ {HDMIV_1440x2560p60hz, tvregs_vesa_1440x2560p60hz},
+ {HDMIV_1600x900p60hz, tvregs_vesa_1600x900p60hz},
+ {HDMIV_1600x1200p60hz, tvregs_vesa_1600x1200p60hz},
+ {HDMIV_1680x1050p60hz, tvregs_vesa_1680x1050p60hz},
+ {HDMIV_1920x1200p60hz, tvregs_vesa_1920x1200p60hz},
+ {HDMIV_2160x1200p90hz, tvregs_vesa_2160x1200p90hz},
+ {HDMIV_2560x1600p60hz, tvregs_vesa_2560x1600p60hz},
+ {HDMIV_3440x1440p60hz, tvregs_vesa_3440x1440p60hz},
+ {HDMIV_2400x1200p90hz, tvregs_vesa_2400x1200p90hz},
+};
+
+static inline void setreg(const struct reg_s *r)
+{
+ hd_write_reg(r->reg, r->val);
+ /* printk("[0x%x] = 0x%x\n", r->reg, r->val); */
+}
+
+static const struct reg_s *tvregs_setting_mode(enum hdmi_vic vic)
+{
+ int i = 0;
+ for (i = 0; i < ARRAY_SIZE(tvregsTab); i++) {
+ if (vic == tvregsTab[i].vic)
+ return tvregsTab[i].reg_setting;
+ }
+ return NULL;
+}
+
+void set_vmode_enc_hw(enum hdmi_vic vic)
+{
+ const struct reg_s *s = tvregs_setting_mode(vic);
+
+ if (s) {
+ pr_info("hdmitx: set enc for VIC: %d\n", vic);
+ while (s->reg != MREG_END_MARKER)
+ setreg(s++);
+ } else
+ printf("hdmitx: not find VIC: %d\n", vic);
+}
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx21/hdmi_edid_parsing.c b/drivers/amlogic/media/vout/hdmitx/hdmitx21/hdmi_edid_parsing.c
new file mode 100644
index 0000000..34a949d
--- /dev/null
+++ b/drivers/amlogic/media/vout/hdmitx/hdmitx21/hdmi_edid_parsing.c
@@ -0,0 +1,1283 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <linux/stddef.h>
+#include <amlogic/media/vout/hdmitx21/hdmitx.h>
+#include "hdmitx_drv.h"
+
+#define CEA_DATA_BLOCK_COLLECTION_ADDR_1StP 0x04
+#define VIDEO_TAG 0x40
+#define AUDIO_TAG 0x20
+#define VENDOR_TAG 0x60
+#define SPEAKER_TAG 0x80
+
+#define HDMI_EDID_BLOCK_TYPE_RESERVED 0
+#define HDMI_EDID_BLOCK_TYPE_AUDIO 1
+#define HDMI_EDID_BLOCK_TYPE_VIDEO 2
+#define HDMI_EDID_BLOCK_TYPE_VENDER 3
+#define HDMI_EDID_BLOCK_TYPE_SPEAKER 4
+#define HDMI_EDID_BLOCK_TYPE_VESA 5
+#define HDMI_EDID_BLOCK_TYPE_RESERVED2 6
+#define HDMI_EDID_BLOCK_TYPE_EXTENDED_TAG 7
+
+#define EXTENSION_VENDOR_SPECIFIC 0x1
+#define EXTENSION_COLORMETRY_TAG 0x5
+/* DRM stands for "Dynamic Range and Mastering " */
+#define EXTENSION_DRM_STATIC_TAG 0x6
+/* Video Format Preference Data block */
+#define EXTENSION_VFPDB_TAG 0xd
+#define EXTENSION_Y420_VDB_TAG 0xe
+#define EXTENSION_Y420_CMDB_TAG 0xf
+
+#define EDID_DETAILED_TIMING_DES_BLOCK0_POS 0x36
+#define EDID_DETAILED_TIMING_DES_BLOCK1_POS 0x48
+#define EDID_DETAILED_TIMING_DES_BLOCK2_POS 0x5A
+#define EDID_DETAILED_TIMING_DES_BLOCK3_POS 0x6C
+
+/* EDID Descrptor Tag */
+#define TAG_PRODUCT_SERIAL_NUMBER 0xFF
+#define TAG_ALPHA_DATA_STRING 0xFE
+#define TAG_RANGE_LIMITS 0xFD
+#define TAG_DISPLAY_PRODUCT_NAME_STRING 0xFC /* MONITOR NAME */
+#define TAG_COLOR_POINT_DATA 0xFB
+#define TAG_STANDARD_TIMINGS 0xFA
+#define TAG_DISPLAY_COLOR_MANAGEMENT 0xF9
+#define TAG_CVT_TIMING_CODES 0xF8
+#define TAG_ESTABLISHED_TIMING_III 0xF7
+#define TAG_DUMMY_DES 0x10
+
+static int edid_parsingdrmstaticblock(struct rx_cap *prxcap,
+ unsigned char *buf)
+{
+ unsigned char tag = 0, ext_tag = 0, data_end = 0;
+ unsigned int pos = 0;
+
+ tag = (buf[pos] >> 5) & 0x7;
+ data_end = (buf[pos] & 0x1f);
+ memset(prxcap->hdr_info.rawdata, 0, 7);
+ memcpy(prxcap->hdr_info.rawdata, buf, data_end + 1);
+ pos++;
+ ext_tag = buf[pos];
+ if (tag != HDMI_EDID_BLOCK_TYPE_EXTENDED_TAG || ext_tag != EXTENSION_DRM_STATIC_TAG)
+ goto INVALID_DRM_STATIC;
+ pos++;
+ prxcap->hdr_info.hdr_sup_eotf_sdr = !!(buf[pos] & (0x1 << 0));
+ prxcap->hdr_info.hdr_sup_eotf_hdr = !!(buf[pos] & (0x1 << 1));
+ prxcap->hdr_info.hdr_sup_eotf_smpte_st_2084 = !!(buf[pos] & (0x1 << 2));
+ prxcap->hdr_info.hdr_sup_eotf_hlg = !!(buf[pos] & (0x1 << 3));
+ pos++;
+ prxcap->hdr_info.hdr_sup_SMD_type1 = !!(buf[pos] & (0x1 << 0));
+ pos++;
+ if (data_end == 3)
+ return 0;
+ if (data_end == 4) {
+ prxcap->hdr_info.hdr_lum_max = buf[pos];
+ return 0;
+ }
+ if (data_end == 5) {
+ prxcap->hdr_info.hdr_lum_max = buf[pos];
+ prxcap->hdr_info.hdr_lum_avg = buf[pos + 1];
+ return 0;
+ }
+ if (data_end == 6) {
+ prxcap->hdr_info.hdr_lum_max = buf[pos];
+ prxcap->hdr_info.hdr_lum_avg = buf[pos + 1];
+ prxcap->hdr_info.hdr_lum_min = buf[pos + 2];
+ return 0;
+ }
+ return 0;
+INVALID_DRM_STATIC:
+ printf("[%s] it's not a valid DRM STATIC BLOCK\n", __func__);
+ return -1;
+}
+
+static void edid_parsingvendspec(struct rx_cap *prxcap,
+ unsigned char *buf)
+{
+ struct dv_info *dv = &prxcap->dv_info;
+ struct hdr10_plus_info *hdr10_plus = &prxcap->hdr10plus_info;
+ unsigned char *dat = buf;
+ unsigned char pos = 0;
+ unsigned int ieeeoui = 0;
+ u8 length = 0;
+
+ length = dat[pos] & 0x1f;
+ pos++;
+
+ if (dat[pos] != 1) {
+ printf("hdmitx: edid: parsing fail %s[%d]\n", __func__,
+ __LINE__);
+ return;
+ }
+
+ pos++;
+ ieeeoui = dat[pos++];
+ ieeeoui += dat[pos++] << 8;
+ ieeeoui += dat[pos++] << 16;
+ printf("%s:ieeeoui=0x%x,len=%u\n", __func__, ieeeoui, length);
+
+ /*HDR10+ use vsvdb*/
+ if (ieeeoui == HDR10_PLUS_IEEE_OUI) {
+ memset(hdr10_plus, 0, sizeof(struct hdr10_plus_info));
+ hdr10_plus->length = length;
+ hdr10_plus->ieeeoui = ieeeoui;
+ hdr10_plus->application_version = dat[pos] & 0x3;
+ pos++;
+ return;
+ }
+
+ if (ieeeoui == DV_IEEE_OUI) {
+ /* it is a Dovi block*/
+ memset(dv, 0, sizeof(struct dv_info));
+ dv->block_flag = CORRECT;
+ dv->length = length;
+ memcpy(dv->rawdata, dat, dv->length + 1);
+ dv->ieeeoui = ieeeoui;
+ dv->ver = (dat[pos] >> 5) & 0x7;
+ if (dv->ver > 2) {
+ dv->block_flag = ERROR_VER;
+ return;
+ }
+ /* Refer to DV 2.9 Page 27 */
+ if (dv->ver == 0) {
+ if (dv->length == 0x19) {
+ dv->sup_yuv422_12bit = dat[pos] & 0x1;
+ dv->sup_2160p60hz = (dat[pos] >> 1) & 0x1;
+ dv->sup_global_dimming = (dat[pos] >> 2) & 0x1;
+ pos++;
+ dv->Rx = (dat[pos + 1] << 4) | (dat[pos] >> 4);
+ dv->Ry = (dat[pos + 2] << 4) | (dat[pos] & 0xf);
+ pos += 3;
+ dv->Gx = (dat[pos + 1] << 4) | (dat[pos] >> 4);
+ dv->Gy = (dat[pos + 2] << 4) | (dat[pos] & 0xf);
+ pos += 3;
+ dv->Bx = (dat[pos + 1] << 4) | (dat[pos] >> 4);
+ dv->By = (dat[pos + 2] << 4) | (dat[pos] & 0xf);
+ pos += 3;
+ dv->Wx = (dat[pos + 1] << 4) | (dat[pos] >> 4);
+ dv->Wy = (dat[pos + 2] << 4) | (dat[pos] & 0xf);
+ pos += 3;
+ dv->tminPQ = (dat[pos + 1] << 4) | (dat[pos] >> 4);
+ dv->tmaxPQ = (dat[pos + 2] << 4) | (dat[pos] & 0xf);
+ pos += 3;
+ dv->dm_major_ver = dat[pos] >> 4;
+ dv->dm_minor_ver = dat[pos] & 0xf;
+ pos++;
+ dv->support_DV_RGB_444_8BIT = 1;
+ printf("v0 VSVDB: len=%d, sup_2160p60hz=%d\n",
+ dv->length, dv->sup_2160p60hz);
+ } else {
+ dv->block_flag = ERROR_LENGTH;
+ }
+ }
+
+ if (dv->ver == 1) {
+ if (dv->length == 0x0B) {/* Refer to DV 2.9 Page 33 */
+ dv->dm_version = (dat[pos] >> 2) & 0x7;
+ dv->sup_yuv422_12bit = dat[pos] & 0x1;
+ dv->sup_2160p60hz = (dat[pos] >> 1) & 0x1;
+ pos++;
+ dv->sup_global_dimming = dat[pos] & 0x1;
+ dv->tmaxLUM = dat[pos] >> 1;
+ pos++;
+ dv->colorimetry = dat[pos] & 0x1;
+ dv->tminLUM = dat[pos] >> 1;
+ pos++;
+ dv->low_latency = dat[pos] & 0x3;
+ dv->Bx = 0x20 | ((dat[pos] >> 5) & 0x7);
+ dv->By = 0x08 | ((dat[pos] >> 2) & 0x7);
+ pos++;
+ dv->Gx = 0x00 | (dat[pos] >> 1);
+ dv->Ry = 0x40 | ((dat[pos] & 0x1) |
+ ((dat[pos + 1] & 0x1) << 1) |
+ ((dat[pos + 2] & 0x3) << 2));
+ pos++;
+ dv->Gy = 0x80 | (dat[pos] >> 1);
+ pos++;
+ dv->Rx = 0xA0 | (dat[pos] >> 3);
+ pos++;
+ dv->support_DV_RGB_444_8BIT = 1;
+ if (dv->low_latency == 0x01)
+ dv->support_LL_YCbCr_422_12BIT = 1;
+ printf("v1 VSVDB: len=%d, sup_2160p60hz=%d, low_latency=%d\n",
+ dv->length, dv->sup_2160p60hz, dv->low_latency);
+ } else if (dv->length == 0x0E) {
+ dv->dm_version = (dat[pos] >> 2) & 0x7;
+ dv->sup_yuv422_12bit = dat[pos] & 0x1;
+ dv->sup_2160p60hz = (dat[pos] >> 1) & 0x1;
+ pos++;
+ dv->sup_global_dimming = dat[pos] & 0x1;
+ dv->tmaxLUM = dat[pos] >> 1;
+ pos++;
+ dv->colorimetry = dat[pos] & 0x1;
+ dv->tminLUM = dat[pos] >> 1;
+ pos += 2; /* byte8 is reserved as 0 */
+ dv->Rx = dat[pos++];
+ dv->Ry = dat[pos++];
+ dv->Gx = dat[pos++];
+ dv->Gy = dat[pos++];
+ dv->Bx = dat[pos++];
+ dv->By = dat[pos++];
+ dv->support_DV_RGB_444_8BIT = 1;
+ printf("v1 VSVDB: len=%d, sup_2160p60hz=%d\n",
+ dv->length, dv->sup_2160p60hz);
+ } else {
+ dv->block_flag = ERROR_LENGTH;
+ }
+ }
+ if (dv->ver == 2) {
+ /* v2 VSVDB length could be greater than 0xB
+ * and should not be treated as unrecognized
+ * block. Instead, we should parse it as a regular
+ * v2 VSVDB using just the remaining 11 bytes here
+ */
+ if (dv->length >= 0x0B) {
+ dv->sup_2160p60hz = 0x1;/*default*/
+ dv->dm_version = (dat[pos] >> 2) & 0x7;
+ dv->sup_yuv422_12bit = dat[pos] & 0x1;
+ dv->sup_backlight_control = (dat[pos] >> 1) & 0x1;
+ pos++;
+ dv->sup_global_dimming = (dat[pos] >> 2) & 0x1;
+ dv->backlt_min_luma = dat[pos] & 0x3;
+ dv->tminPQ = dat[pos] >> 3;
+ pos++;
+ dv->Interface = dat[pos] & 0x3;
+ dv->tmaxPQ = dat[pos] >> 3;
+ pos++;
+ dv->sup_10b_12b_444 = ((dat[pos] & 0x1) << 1) |
+ (dat[pos + 1] & 0x1);
+ dv->Gx = 0x00 | (dat[pos] >> 1);
+ pos++;
+ dv->Gy = 0x80 | (dat[pos] >> 1);
+ pos++;
+ dv->Rx = 0xA0 | (dat[pos] >> 3);
+ dv->Bx = 0x20 | (dat[pos] & 0x7);
+ pos++;
+ dv->Ry = 0x40 | (dat[pos] >> 3);
+ dv->By = 0x08 | (dat[pos] & 0x7);
+ pos++;
+ if (dv->Interface != 0x00 && dv->Interface != 0x01)
+ dv->support_DV_RGB_444_8BIT = 1;
+
+ dv->support_LL_YCbCr_422_12BIT = 1;
+ if (dv->Interface == 0x01 || dv->Interface == 0x03) {
+ if (dv->sup_10b_12b_444 == 0x1)
+ dv->support_LL_RGB_444_10BIT = 1;
+ if (dv->sup_10b_12b_444 == 0x2)
+ dv->support_LL_RGB_444_12BIT = 1;
+ }
+ printf("v2 VSVDB: len=%d, sup_2160p60hz=%d, Interface=%d\n",
+ dv->length, dv->sup_2160p60hz, dv->Interface);
+ } else {
+ dv->block_flag = ERROR_LENGTH;
+ }
+ }
+
+ if (pos > dv->length + 1)
+ printf("hdmitx: edid: maybe invalid dv%d data\n", dv->ver);
+ return;
+ }
+ /* future: other new VSVDB add here: */
+}
+
+static void edid_dtd_parsing(struct rx_cap *prxcap, unsigned char *data)
+{
+ struct hdmi_format_para *para = NULL;
+ struct dtd *t = &prxcap->dtd[prxcap->dtd_idx];
+
+ memset(t, 0, sizeof(struct dtd));
+ t->pixel_clock = data[0] + (data[1] << 8);
+ t->h_active = (((data[4] >> 4) & 0xf) << 8) + data[2];
+ t->h_blank = ((data[4] & 0xf) << 8) + data[3];
+ t->v_active = (((data[7] >> 4) & 0xf) << 8) + data[5];
+ t->v_blank = ((data[7] & 0xf) << 8) + data[6];
+ t->h_sync_offset = (((data[11] >> 6) & 0x3) << 8) + data[8];
+ t->h_sync = (((data[11] >> 4) & 0x3) << 8) + data[9];
+ t->v_sync_offset = (((data[11] >> 2) & 0x3) << 4) +
+ ((data[10] >> 4) & 0xf);
+ t->v_sync = (((data[11] >> 0) & 0x3) << 4) + ((data[10] >> 0) & 0xf);
+/*
+ * Special handling of 1080i60hz, 1080i50hz
+ */
+ if (t->pixel_clock == 7425 && t->h_active == 1920 &&
+ t->v_active == 1080) {
+ t->v_active = t->v_active / 2;
+ t->v_blank = t->v_blank / 2;
+ }
+/*
+ * Special handling of 480i60hz, 576i50hz
+ */
+ if ((((t->flags >> 1) & 0x3) == 0) && t->h_active == 1440) {
+ if (t->pixel_clock == 2700) /* 576i50hz */
+ goto next;
+ if ((t->pixel_clock - 2700) < 10) /* 480i60hz */
+ t->pixel_clock = 2702;
+next:
+ t->v_active = t->v_active / 2;
+ t->v_blank = t->v_blank / 2;
+ }
+/*
+ * call hdmitx21_match_dtd_paras() to check t is matched with VIC
+ */
+ para = hdmitx21_match_dtd_paras(t);
+ if (para) {
+ t->vic = para->timing.vic;
+ prxcap->preferred_mode = prxcap->dtd[0].vic; /* Select dtd0 */
+ if (0) /* debug only */
+ pr_info("hdmitx: get dtd%d vic: %d\n",
+ prxcap->dtd_idx, para->timing.vic);
+ prxcap->dtd_idx++;
+ }
+}
+
+/* parse Sink 4k2k information */
+static void hdmitx_edid_4k2k_parse(struct rx_cap *prxcap, unsigned char *dat,
+ unsigned int size)
+{
+ if (size > 4 || size == 0)
+ return;
+
+ while (size--) {
+ if (*dat == 1)
+ prxcap->VIC[prxcap->VIC_count] = HDMI_95_3840x2160p30_16x9;
+ else if (*dat == 2)
+ prxcap->VIC[prxcap->VIC_count] = HDMI_94_3840x2160p25_16x9;
+ else if (*dat == 3)
+ prxcap->VIC[prxcap->VIC_count] = HDMI_93_3840x2160p24_16x9;
+ else if (*dat == 4)
+ prxcap->VIC[prxcap->VIC_count] = HDMI_98_4096x2160p24_256x135;
+ else
+ ;
+ dat++;
+ prxcap->VIC_count++;
+ }
+}
+
+static void set_vsdb_dc_cap(struct rx_cap *prxcap)
+{
+ prxcap->dc_y444 = !!(prxcap->ColorDeepSupport & (1 << 3));
+ prxcap->dc_30bit = !!(prxcap->ColorDeepSupport & (1 << 4));
+ prxcap->dc_36bit = !!(prxcap->ColorDeepSupport & (1 << 5));
+ prxcap->dc_48bit = !!(prxcap->ColorDeepSupport & (1 << 6));
+}
+
+static void set_vsdb_dc_420_cap(struct rx_cap *prxcap,
+ unsigned char *edid_offset)
+{
+ prxcap->dc_30bit_420 = !!(edid_offset[6] & (1 << 0));
+ prxcap->dc_36bit_420 = !!(edid_offset[6] & (1 << 1));
+ prxcap->dc_48bit_420 = !!(edid_offset[6] & (1 << 2));
+}
+
+static bool y420vicright(unsigned int vic)
+{
+ bool rtn_val;
+
+ rtn_val = false;
+ if (vic == HDMI_107_3840x2160p60_64x27 ||
+ vic == HDMI_106_3840x2160p50_64x27 ||
+ vic == HDMI_102_4096x2160p60_256x135 ||
+ vic == HDMI_101_4096x2160p50_256x135 ||
+ vic == HDMI_97_3840x2160p60_16x9 ||
+ vic == HDMI_96_3840x2160p50_16x9)
+ rtn_val = true;
+ return rtn_val;
+}
+
+static int edid_parsingy420vdbblock(struct rx_cap *prxcap,
+ unsigned char *buf)
+{
+ unsigned char tag = 0, ext_tag = 0, data_end = 0;
+ unsigned int pos = 0;
+ int i = 0, found = 0;
+
+ tag = (buf[pos] >> 5) & 0x7;
+ data_end = (buf[pos] & 0x1f) + 1;
+ pos++;
+ ext_tag = buf[pos];
+
+ if (tag != 0x7 || ext_tag != 0xe)
+ goto INVALID_Y420VDB;
+
+ prxcap->dc_y420 = 1;
+ pos++;
+ while (pos < data_end) {
+ if (prxcap->VIC_count < VIC_MAX_NUM) {
+ for (i = 0; i < prxcap->VIC_count; i++) {
+ if (prxcap->VIC[i] == buf[pos] &&
+ y420vicright(buf[pos])) {
+ prxcap->VIC[i] = buf[pos];
+ // TODO HDMITX_VIC420_OFFSET + buf[pos];
+ found = 1;
+ /* Here we do not break,because
+ * some EDID may have the same
+ * repeated VICs
+ */
+ }
+ }
+ if (found == 0) {
+ prxcap->VIC[prxcap->VIC_count] = buf[pos];
+ // TODO HDMITX_VIC420_OFFSET + buf[pos];
+ prxcap->VIC_count++;
+ }
+ }
+ pos++;
+ }
+
+ return 0;
+
+INVALID_Y420VDB:
+ printf("[%s] it's not a valid y420vdb!\n", __func__);
+ return -1;
+}
+
+static int edid_parsingy420cmdbblock(struct rx_cap *prxcap,
+ unsigned char *buf)
+{
+ unsigned char tag = 0, ext_tag = 0, length = 0, data_end = 0;
+ unsigned int pos = 0, i = 0;
+
+ tag = (buf[pos] >> 5) & 0x7;
+ length = buf[pos] & 0x1f;
+ data_end = length + 1;
+ pos++;
+ ext_tag = buf[pos];
+
+ if (tag != 0x7 || ext_tag != 0xf)
+ goto INVALID_Y420CMDB;
+
+ if (length == 1) {
+ prxcap->y420_all_vic = 1;
+ return 0;
+ }
+
+ prxcap->bitmap_length = 0;
+ prxcap->bitmap_valid = 0;
+ memset(prxcap->y420cmdb_bitmap, 0x00, Y420CMDB_MAX);
+
+ pos++;
+ if (pos < data_end) {
+ prxcap->bitmap_length = data_end - pos;
+ prxcap->bitmap_valid = 1;
+ }
+ while (pos < data_end) {
+ if (i < Y420CMDB_MAX)
+ prxcap->y420cmdb_bitmap[i] = buf[pos];
+ pos++;
+ i++;
+ }
+
+ return 0;
+
+INVALID_Y420CMDB:
+ printf("[%s] it's not a valid y420cmdb!\n", __func__);
+ return -1;
+}
+
+static int edid_y420cmbd_fill_all_vic(struct rx_cap *prxcap)
+{
+ unsigned int count = prxcap->VIC_count;
+ unsigned int a, b;
+
+ if (prxcap->y420_all_vic != 1)
+ return 1;
+
+ a = count / 8;
+ a = (a >= Y420CMDB_MAX) ? Y420CMDB_MAX : a;
+ b = count % 8;
+
+ if (a > 0)
+ memset(&prxcap->y420cmdb_bitmap[0], 0xff, a);
+
+ if (b != 0 && a < Y420CMDB_MAX)
+ prxcap->y420cmdb_bitmap[a] = (1 << b) - 1;
+
+ prxcap->bitmap_length = (b == 0) ? a : (a + 1);
+ prxcap->bitmap_valid = (prxcap->bitmap_length != 0) ? 1 : 0;
+
+ return 0;
+}
+
+static int edid_y420cmdb_postprocess(struct rx_cap *prxcap)
+{
+ unsigned int i = 0, j = 0, valid = 0;
+ unsigned char *p = NULL;
+
+ if (prxcap->y420_all_vic == 1)
+ edid_y420cmbd_fill_all_vic(prxcap);
+
+ if (prxcap->bitmap_valid == 0)
+ goto PROCESS_END;
+
+ prxcap->dc_y420 = 1;
+ for (i = 0; i < prxcap->bitmap_length; i++) {
+ p = &prxcap->y420cmdb_bitmap[i];
+ for (j = 0; j < 8; j++) {
+ valid = ((*p >> j) & 0x1);
+ if (valid != 0 &&
+ y420vicright(prxcap->VIC[i * 8 + j])) {
+ prxcap->VIC[prxcap->VIC_count] = prxcap->VIC[i * 8 + j];
+ // TODO HDMITX_VIC420_OFFSET + prxcap->VIC[i*8+j];
+ prxcap->VIC_count++;
+ }
+ }
+ }
+
+PROCESS_END:
+ return 0;
+}
+
+static int edid_parsingvfpdb(struct rx_cap *prxcap, unsigned char *buf)
+{
+ unsigned int len = buf[0] & 0x1f;
+ enum hdmi_vic svr = HDMI_UNKNOWN;
+
+ if (buf[1] != EXTENSION_VFPDB_TAG)
+ return 0;
+ if (len < 2)
+ return 0;
+
+ svr = buf[2];
+ if ((svr >= 1 && svr <= 127) ||
+ (svr >= 193 && svr <= 253)) {
+ prxcap->flag_vfpdb = 1;
+ prxcap->preferred_mode = svr;
+ pr_info("preferred mode 0 srv %d\n", prxcap->preferred_mode);
+ return 1;
+ }
+ if (svr >= 129 && svr <= 144) {
+ prxcap->flag_vfpdb = 1;
+ prxcap->preferred_mode = prxcap->dtd[svr - 129].vic;
+ pr_info("preferred mode 0 dtd %d\n", prxcap->preferred_mode);
+ return 1;
+ }
+ return 0;
+}
+
+static int hdmitx_edid_block_parse(struct rx_cap *prxcap,
+ unsigned char *blockbuf)
+{
+ unsigned char offset, end;
+ unsigned char count;
+ unsigned char tag;
+ int i, tmp, idx;
+ unsigned char *vfpdb_offset = NULL;
+
+ /* CEA-861 implementations are required to use Tag = 0x02
+ * for the CEA Extension Tag and Sources should ignore
+ * Tags that are not understood. but for Samsung LA32D400E1
+ * its extension tag is 0x0 while other bytes normal,
+ * so continue parse as other sources do
+ */
+ if (blockbuf[0] == 0x0)
+ printf("unkonw Extension Tag detected, continue\n");
+ else if (blockbuf[0] != 0x02)
+ return -1; /* not a CEA BLOCK. */
+ end = blockbuf[2]; /* CEA description. */
+ prxcap->native_Mode = blockbuf[3];
+ prxcap->number_of_dtd += blockbuf[3] & 0xf;
+ /* bit 5 (YCBCR 4:4:4) = 1 if sink device supports YCBCR 4:4:4
+ * in addition to RGB;
+ * bit 4 (YCBCR 4:2:2) = 1 if sink device supports YCBCR 4:2:2
+ * in addition to RGB
+ */
+ prxcap->pref_colorspace = blockbuf[3] & 0x30;
+
+ prxcap->native_VIC = 0xff;
+
+ for (offset = 4 ; offset < end ; ) {
+ tag = blockbuf[offset] >> 5;
+ count = blockbuf[offset] & 0x1f;
+ switch (tag) {
+ case HDMI_EDID_BLOCK_TYPE_AUDIO:
+ offset++;
+ offset += count;
+ break;
+
+ case HDMI_EDID_BLOCK_TYPE_VIDEO:
+ offset++;
+ for (i = 0 ; i < count ; i++) {
+ unsigned char VIC;
+ /* 7.5.1 Video Data Block Table 58
+ * and CTA-861-G page101: only 1~64
+ * maybe Native Video Format. and
+ * need to take care hdmi2.1 VIC:
+ * 193~253
+ */
+ VIC = blockbuf[offset + i];
+ if (VIC >= 129 && VIC <= 192) {
+ VIC &= (~0x80);
+ prxcap->native_VIC = VIC;
+ }
+ prxcap->VIC[prxcap->VIC_count] = VIC;
+ prxcap->VIC_count++;
+ }
+ offset += count;
+ break;
+
+ case HDMI_EDID_BLOCK_TYPE_VENDER:
+ offset++;
+ if (blockbuf[offset] == 0x03 &&
+ blockbuf[offset + 1] == 0x0c &&
+ blockbuf[offset + 2] == 0x00)
+ prxcap->IEEEOUI = 0x000c03;
+ else
+ goto case_hf;
+ prxcap->ColorDeepSupport = (unsigned long)blockbuf[offset + 5];
+ printf("HDMI_EDID_BLOCK_TYPE_VENDER: prxcap->ColorDeepSupport=0x%x\n",
+ prxcap->ColorDeepSupport);
+ set_vsdb_dc_cap(prxcap);
+ prxcap->Max_TMDS_Clock1 = (unsigned long)blockbuf[offset + 6];
+ if (count > 7) {
+ tmp = blockbuf[offset + 7];
+ idx = offset + 8;
+ if (tmp & (1 << 6))
+ idx += 2;
+ if (tmp & (1 << 7))
+ idx += 2;
+ if (tmp & (1 << 5)) {
+ idx += 1;
+ /* valid 4k */
+ if (blockbuf[idx] & 0xe0) {
+ hdmitx_edid_4k2k_parse(prxcap,
+ &blockbuf[idx + 1],
+ blockbuf[idx] >> 5);
+ }
+ }
+ }
+ goto case_next;
+case_hf:
+ if (blockbuf[offset] == 0xd8 &&
+ blockbuf[offset + 1] == 0x5d &&
+ blockbuf[offset + 2] == 0xc4)
+ prxcap->HF_IEEEOUI = 0xd85dc4;
+ prxcap->Max_TMDS_Clock2 = blockbuf[offset + 4];
+ prxcap->scdc_present =
+ !!(blockbuf[offset + 5] & (1 << 7));
+ prxcap->scdc_rr_capable =
+ !!(blockbuf[offset + 5] & (1 << 6));
+ prxcap->lte_340mcsc_scramble =
+ !!(blockbuf[offset + 5] & (1 << 3));
+ set_vsdb_dc_420_cap(prxcap,
+ &blockbuf[offset]);
+case_next:
+ offset += count; /* ignore the remaind. */
+ break;
+
+ case HDMI_EDID_BLOCK_TYPE_SPEAKER:
+ offset++;
+ offset += count;
+ break;
+
+ case HDMI_EDID_BLOCK_TYPE_VESA:
+ offset++;
+ offset += count;
+ break;
+
+ case HDMI_EDID_BLOCK_TYPE_EXTENDED_TAG:
+ {
+ unsigned char ext_tag = 0;
+
+ ext_tag = blockbuf[offset + 1];
+ switch (ext_tag) {
+ case EXTENSION_VENDOR_SPECIFIC:
+ edid_parsingvendspec(prxcap, &blockbuf[offset]);
+ break;
+ case EXTENSION_COLORMETRY_TAG:
+ prxcap->colorimetry_data = blockbuf[offset + 2];
+ break;
+ case EXTENSION_DRM_STATIC_TAG:
+ edid_parsingdrmstaticblock(prxcap, &blockbuf[offset]);
+ break;
+ case EXTENSION_VFPDB_TAG:
+/* Just record VFPDB offset address, call edid_parsingvfpdb() after DTD
+ * parsing, in case that
+ * SVR >=129 and SVR <=144, Interpret as the Kth DTD in the EDID,
+ * where K = SVR – 128 (for K=1 to 16)
+ */
+ vfpdb_offset = &blockbuf[offset];
+ break;
+ case EXTENSION_Y420_VDB_TAG:
+ edid_parsingy420vdbblock(prxcap, &blockbuf[offset]);
+ break;
+ case EXTENSION_Y420_CMDB_TAG:
+ edid_parsingy420cmdbblock(prxcap, &blockbuf[offset]);
+ break;
+ default:
+ break;
+ }
+ }
+ offset += count + 1;
+ break;
+
+ case HDMI_EDID_BLOCK_TYPE_RESERVED:
+ offset++;
+ offset += count;
+ break;
+
+ case HDMI_EDID_BLOCK_TYPE_RESERVED2:
+ offset++;
+ offset += count;
+ break;
+
+ default:
+ break;
+ }
+ }
+
+ edid_y420cmdb_postprocess(prxcap);
+ idx = blockbuf[3] & 0xf;
+ for (i = 0; i < idx; i++)
+ edid_dtd_parsing(prxcap, &blockbuf[blockbuf[2] + i * 18]);
+ if (vfpdb_offset)
+ edid_parsingvfpdb(prxcap, vfpdb_offset);
+
+ return 0;
+}
+
+void edid_montorcapable861(struct rx_cap *prxcap,
+ unsigned char edid_flag)
+{
+ if (edid_flag & 0x20)
+ prxcap->support_ycbcr444_flag = 1;
+ if (edid_flag & 0x10)
+ prxcap->support_ycbcr422_flag = 1;
+ printf("%s: ycbcr444=%d, ycbcr422=%d\n", __func__,
+ prxcap->support_ycbcr444_flag, prxcap->support_ycbcr422_flag);
+}
+
+static bool is_4k60_supported(struct rx_cap *prxcap)
+{
+ int i = 0;
+
+ if (!prxcap)
+ return false;
+
+ for (i = 0; (i < prxcap->VIC_count) && (i < VIC_MAX_NUM); i++) {
+ if (((prxcap->VIC[i] & 0xff) == HDMI_96_3840x2160p50_16x9) ||
+ ((prxcap->VIC[i] & 0xff) == HDMI_97_3840x2160p60_16x9)) {
+ return true;
+ }
+ }
+ return false;
+}
+
+static void check_dv_truly_support(struct rx_cap *prxcap, struct dv_info *dv)
+{
+ unsigned int max_tmds_clk = 0;
+
+ if (!prxcap || !dv)
+ return;
+ if (dv->ieeeoui == DV_IEEE_OUI && dv->ver <= 2) {
+ /* check max tmds rate to determine if 4k60 DV can truly be
+ * supported.
+ */
+ if (prxcap->Max_TMDS_Clock2) {
+ max_tmds_clk = prxcap->Max_TMDS_Clock2 * 5;
+ } else {
+ /* Default min is 74.25 / 5 */
+ if (prxcap->Max_TMDS_Clock1 < 0xf)
+ prxcap->Max_TMDS_Clock1 = 0x1e;
+ max_tmds_clk = prxcap->Max_TMDS_Clock1 * 5;
+ }
+ if (dv->ver == 0)
+ dv->sup_2160p60hz = dv->sup_2160p60hz &&
+ (max_tmds_clk >= 594);
+
+ if (dv->ver == 1 && dv->length == 0xB) {
+ if (dv->low_latency == 0x00) {
+ /*standard mode */
+ dv->sup_2160p60hz = dv->sup_2160p60hz &&
+ (max_tmds_clk >= 594);
+ } else if (dv->low_latency == 0x01) {
+ /* both standard and LL are supported. 4k60 LL
+ * DV support should/can be determined using
+ * video formats supported inthe E-EDID as flag
+ * sup_2160p60hz might not be set.
+ */
+ if ((dv->sup_2160p60hz || is_4k60_supported(prxcap)) &&
+ max_tmds_clk >= 594)
+ dv->sup_2160p60hz = 1;
+ else
+ dv->sup_2160p60hz = 0;
+ }
+ }
+
+ if (dv->ver == 1 && dv->length == 0xE)
+ dv->sup_2160p60hz = dv->sup_2160p60hz &&
+ (max_tmds_clk >= 594);
+
+ if (dv->ver == 2) {
+ /* 4k60 DV support should be determined using video
+ * formats supported in the EEDID as flag sup_2160p60hz
+ * is not applicable for VSVDB V2.
+ */
+ if (is_4k60_supported(prxcap) && max_tmds_clk >= 594)
+ dv->sup_2160p60hz = 1;
+ else
+ dv->sup_2160p60hz = 0;
+ }
+ }
+}
+
+/*
+ * Parsing RAW EDID data from edid to prxcap
+ */
+unsigned int hdmi_edid_parsing(unsigned char *edid_buf, struct rx_cap *prxcap)
+{
+ int i, j;
+ int blockcount = edid_buf[126];
+ int idx[4];
+ unsigned char CheckSum;
+ struct dv_info *dv = &prxcap->dv_info;
+
+ /* Clear all parsing data */
+ memset(prxcap, 0, sizeof(struct rx_cap));
+ prxcap->IEEEOUI = 0x000c03; /* Default is HDMI device */
+
+ /* If edid data corrupted, no parse */
+ /*
+ * if (check_dvi_hdmi_edid_valid(edid_buf) == 0)
+ * return 0;
+ */
+
+ idx[0] = EDID_DETAILED_TIMING_DES_BLOCK0_POS;
+ idx[1] = EDID_DETAILED_TIMING_DES_BLOCK1_POS;
+ idx[2] = EDID_DETAILED_TIMING_DES_BLOCK2_POS;
+ idx[3] = EDID_DETAILED_TIMING_DES_BLOCK3_POS;
+ for (i = 0; i < 4; i++) {
+ if ((edid_buf[idx[i]]) && (edid_buf[idx[i] + 1]))
+ edid_dtd_parsing(prxcap, &edid_buf[idx[i]]);
+ }
+
+ if (blockcount == 0)
+ prxcap->IEEEOUI = 0;
+
+ for (i = 1; i <= blockcount; i++) {
+ if (blockcount > 1 && i == 1) {
+ CheckSum = 0; /* ignore the block1 data */
+ } else {
+ for (j = 0, CheckSum = 0 ; j < 128 ; j++) {
+ CheckSum += edid_buf[i * 128 + j];
+ CheckSum &= 0xFF;
+ }
+ if (CheckSum == 0)
+ edid_montorcapable861(prxcap, edid_buf[i * 128 + 3]);
+ }
+ hdmitx_edid_block_parse(prxcap, &edid_buf[i * 128]);
+ }
+ check_dv_truly_support(prxcap, dv);
+/*
+ * Because DTDs are not able to represent some Video Formats, which can be
+ * represented as SVDs and might be preferred by Sinks, the first DTD in the
+ * base EDID data structure and the first SVD in the first CEA Extension can
+ * differ. When the first DTD and SVD do not match and the total number of
+ * DTDs defining Native Video Formats in the whole EDID is zero, the first
+ * SVD shall take precedence.
+ */
+ if (!prxcap->flag_vfpdb && prxcap->preferred_mode != prxcap->VIC[0] &&
+ prxcap->number_of_dtd == 0) {
+ pr_info("hdmitx: edid: change preferred_mode from %d to %d\n",
+ prxcap->preferred_mode, prxcap->VIC[0]);
+ prxcap->preferred_mode = prxcap->VIC[0];
+ }
+
+ return 1;
+}
+
+int hdmitx_edid_VIC_support(enum hdmi_vic vic)
+{
+ int i;
+ int size = hdmitx21_timing_size();
+ const struct hdmi_timing *t = hdmitx21_get_timing_para0();
+
+ for (i = 0; i < size; i++) {
+ if (vic == t->vic)
+ return 1;
+ t++;
+ }
+
+ return 0;
+}
+
+enum hdmi_vic hdmitx_edid_vic_tab_map_vic(const char *disp_mode)
+{
+ int i;
+ enum hdmi_vic vic = HDMI_UNKNOWN;
+ int size = hdmitx21_timing_size();
+ const struct hdmi_timing *t = hdmitx21_get_timing_para0();
+
+ for (i = 0; i < size; i++) {
+ if (t->sname && strncmp(disp_mode, t->sname, strlen(t->sname)) == 0) {
+ vic = t->vic;
+ break;
+ }
+ if (strncmp(disp_mode, t->name, strlen(t->name)) == 0) {
+ vic = t->vic;
+ break;
+ }
+ t++;
+ }
+
+ if (vic == HDMI_UNKNOWN)
+ printf("not find mapped vic\n");
+
+ return vic;
+}
+
+const char *hdmitx_edid_vic_tab_map_string(enum hdmi_vic vic)
+{
+ int i;
+ const char *disp_str = NULL;
+ int size = get_hdmitx_timing_size();
+ const struct hdmi_timing *t = get_hdmitx_timing_para0();
+
+ for (i = 0; i < size; i++) {
+ if (vic == t->vic) {
+ disp_str = t->sname;
+ if (!disp_str)
+ disp_str = t->name;
+ break;
+ }
+ t++;
+ }
+
+ return disp_str;
+}
+
+const char *hdmitx_edid_vic_to_string(enum hdmi_vic vic)
+{
+ return hdmitx_edid_vic_tab_map_string(vic);
+}
+
+static bool is_rx_support_y420(struct hdmitx_dev *hdev)
+{
+ enum hdmi_vic vic = HDMI_UNKNOWN;
+
+ vic = hdmitx_edid_get_VIC(hdev, "2160p60hz420", 0);
+ if (vic != HDMI_UNKNOWN)
+ return 1;
+
+ vic = hdmitx_edid_get_VIC(hdev, "2160p50hz420", 0);
+ if (vic != HDMI_UNKNOWN)
+ return 1;
+
+ vic = hdmitx_edid_get_VIC(hdev, "smpte60hz420", 0);
+ if (vic != HDMI_UNKNOWN)
+ return 1;
+
+ vic = hdmitx_edid_get_VIC(hdev, "smpte50hz420", 0);
+ if (vic != HDMI_UNKNOWN)
+ return 1;
+
+ return 0;
+}
+
+static int is_4k_fmt(char *mode)
+{
+ int i;
+ static char const *hdmi4k[] = {
+ "2160p",
+ "smpte",
+ NULL
+ };
+
+ for (i = 0; hdmi4k[i]; i++) {
+ if (strstr(mode, hdmi4k[i]))
+ return 1;
+ }
+ return 0;
+}
+
+/* For some TV's EDID, there maybe exist some information ambiguous.
+ * Such as EDID declears support 2160p60hz(Y444 8bit), but no valid
+ * Max_TMDS_Clock2 to indicate that it can support 5.94G signal.
+ */
+bool hdmitx_edid_check_valid_mode(struct hdmitx_dev *hdev,
+ struct hdmi_format_para *para)
+{
+ bool valid = 0;
+ struct rx_cap *prxcap = NULL;
+ struct dv_info *dv = &hdev->RXCap.dv_info;
+ unsigned int rx_max_tmds_clk = 0;
+ unsigned int calc_tmds_clk = 0;
+ int i = 0;
+ int svd_flag = 0;
+ /* Default max color depth is 24 bit */
+ enum hdmi_color_depth rx_y444_max_dc = COLORDEPTH_24B;
+ enum hdmi_color_depth rx_y420_max_dc = COLORDEPTH_24B;
+ enum hdmi_color_depth rx_rgb_max_dc = COLORDEPTH_24B;
+
+ if (!hdev || !para)
+ return 0;
+
+ if (strcmp(para->sname, "invalid") == 0)
+ return 0;
+ if (!is_support_4k() && is_4k_fmt(para->sname))
+ return false;
+ /* exclude such as: 2160p60hz YCbCr444 10bit */
+ switch (para->timing.vic) {
+ case HDMI_96_3840x2160p50_16x9:
+ case HDMI_97_3840x2160p60_16x9:
+ case HDMI_101_4096x2160p50_256x135:
+ case HDMI_102_4096x2160p60_256x135:
+ case HDMI_106_3840x2160p50_64x27:
+ case HDMI_107_3840x2160p60_64x27:
+ if (para->cs == HDMI_COLORSPACE_RGB ||
+ para->cs == HDMI_COLORSPACE_YUV444)
+ if (para->cd != COLORDEPTH_24B)
+ return 0;
+ break;
+ default:
+ break;
+ }
+
+ prxcap = &hdev->RXCap;
+
+ /* DVI case, only 8bit */
+ if (prxcap->IEEEOUI != HDMI_IEEEOUI) {
+ if (para->cd != COLORDEPTH_24B)
+ return 0;
+ }
+
+ /* target mode is not contained at RX SVD */
+ for (i = 0; (i < prxcap->VIC_count) && (i < VIC_MAX_NUM); i++) {
+ if ((para->timing.vic & 0xff) == (prxcap->VIC[i] & 0xff))
+ svd_flag = 1;
+ }
+ if (svd_flag == 0)
+ return 0;
+
+ /* Get RX Max_TMDS_Clock */
+ if (prxcap->Max_TMDS_Clock2) {
+ rx_max_tmds_clk = prxcap->Max_TMDS_Clock2 * 5;
+ } else {
+ /* Default min is 74.25 / 5 */
+ if (prxcap->Max_TMDS_Clock1 < 0xf)
+ prxcap->Max_TMDS_Clock1 = 0x1e;
+ rx_max_tmds_clk = prxcap->Max_TMDS_Clock1 * 5;
+ }
+
+ calc_tmds_clk = para->tmds_clk / 1000;
+ /* printf("RX tmds clk: %d Calc clk: %d\n", */
+ /* rx_max_tmds_clk, calc_tmds_clk); */
+ if (calc_tmds_clk < rx_max_tmds_clk)
+ valid = 1;
+ else
+ return 0;
+
+ if (para->cs == HDMI_COLORSPACE_YUV444) {
+ /* Rx may not support Y444 */
+ if (!(prxcap->native_Mode & (1 << 5)))
+ return 0;
+ if ((prxcap->dc_y444 && prxcap->dc_30bit) ||
+ dv->sup_10b_12b_444 == 0x1)
+ rx_y444_max_dc = COLORDEPTH_30B;
+ if ((prxcap->dc_y444 && prxcap->dc_36bit) ||
+ dv->sup_10b_12b_444 == 0x2)
+ rx_y444_max_dc = COLORDEPTH_36B;
+ if (para->cd <= rx_y444_max_dc)
+ valid = 1;
+ else
+ valid = 0;
+ return valid;
+ }
+ if (para->cs == HDMI_COLORSPACE_YUV422) {
+ /* Rx may not support Y422 */
+ if (!(prxcap->native_Mode & (1 << 4)))
+ return 0;
+ return 1;
+ }
+ if (para->cs == HDMI_COLORSPACE_RGB) {
+ /* Always assume RX supports RGB444 */
+ if (prxcap->dc_30bit || dv->sup_10b_12b_444 == 0x1)
+ rx_rgb_max_dc = COLORDEPTH_30B;
+ if (prxcap->dc_36bit || dv->sup_10b_12b_444 == 0x2)
+ rx_rgb_max_dc = COLORDEPTH_36B;
+ if (para->cd <= rx_rgb_max_dc)
+ valid = 1;
+ else
+ valid = 0;
+ return valid;
+ }
+ if (para->cs == HDMI_COLORSPACE_YUV420) {
+ if (!is_rx_support_y420(hdev))
+ return 0;
+ if (prxcap->dc_30bit_420)
+ rx_y420_max_dc = COLORDEPTH_30B;
+ if (prxcap->dc_36bit_420)
+ rx_y420_max_dc = COLORDEPTH_36B;
+ if (para->cd <= rx_y420_max_dc)
+ valid = 1;
+ else
+ valid = 0;
+ return valid;
+ }
+
+ return valid;
+}
+
+static bool pre_process_str(char *name)
+{
+ int i;
+ unsigned int flag = 0;
+ char *color_format[4] = {"444", "422", "420", "rgb"};
+
+ for (i = 0 ; i < 4 ; i++) {
+ if (strstr(name, color_format[i]))
+ flag++;
+ }
+ if (flag >= 2)
+ return false;
+ else
+ return true;
+}
+
+bool is_supported_mode_attr(hdmi_data_t *hdmi_data, char *mode_attr)
+{
+ struct hdmi_format_para *para = NULL;
+ struct hdmitx_dev *hdev = NULL;
+
+ if (!hdmi_data || !mode_attr)
+ return false;
+ hdev = container_of(hdmi_data->prxcap,
+ struct hdmitx_dev, RXCap);
+
+ if (mode_attr[0]) {
+ if (!pre_process_str(mode_attr))
+ return false;
+ para = hdmitx21_tst_fmt_name(mode_attr, mode_attr);
+ }
+ /* if (para) { */
+ /* printf("sname = %s\n", para->sname); */
+ /* printf("char_clk = %d\n", para->tmds_clk); */
+ /* printf("cd = %d\n", para->cd); */
+ /* printf("cs = %d\n", para->cs); */
+ /* } */
+
+ return hdmitx_edid_check_valid_mode(hdev, para);
+}
+
+bool hdmitx_chk_mode_attr_sup(hdmi_data_t *hdmi_data, char *mode, char *attr)
+{
+ struct hdmi_format_para *para = NULL;
+ struct hdmitx_dev *hdev = NULL;
+
+ if (!hdmi_data || !mode || !attr)
+ return false;
+ hdev = container_of(hdmi_data->prxcap,
+ struct hdmitx_dev, RXCap);
+
+ if (attr[0]) {
+ if (!pre_process_str(attr))
+ return false;
+ para = hdmitx21_tst_fmt_name(mode, attr);
+ }
+ /* if (para) { */
+ /* printf("sname = %s\n", para->sname); */
+ /* printf("char_clk = %d\n", para->tmds_clk); */
+ /* printf("cd = %d\n", para->cd); */
+ /* printf("cs = %d\n", para->cs); */
+ /* } */
+
+ return hdmitx_edid_check_valid_mode(hdev, para);
+}
+
+/* force_flag: 0 means check with RX's edid */
+/* 1 means no check wich RX's edid */
+enum hdmi_vic hdmitx_edid_get_VIC(struct hdmitx_dev *hdev,
+ const char *disp_mode, char force_flag)
+{
+ struct rx_cap *prxcap = &hdev->RXCap;
+ int j;
+ enum hdmi_vic vic = hdmitx_edid_vic_tab_map_vic(disp_mode);
+
+ if (vic != HDMI_UNKNOWN) {
+ if (force_flag == 0) {
+ for (j = 0 ; j < prxcap->VIC_count ; j++) {
+ if (prxcap->VIC[j] == vic)
+ break;
+ }
+ if (j >= prxcap->VIC_count)
+ vic = HDMI_UNKNOWN;
+ }
+ }
+ return vic;
+}
+
+#define EDID_MAX_BLOCK 4
+static bool hdmitx_check_edid_all_zeros(unsigned char *buf)
+{
+ unsigned int i = 0, j = 0;
+ unsigned int chksum = 0;
+
+ for (j = 0; j < EDID_MAX_BLOCK; j++) {
+ chksum = 0;
+ for (i = 0; i < 128; i++)
+ chksum += buf[i + j * 128];
+ if (chksum != 0)
+ return false;
+ }
+ return true;
+}
+
+static bool hdmitx_edid_header_invalid(unsigned char *buf)
+{
+ bool base_blk_invalid = false;
+ bool ext_blk_invalid = false;
+ bool ret = false;
+ int i = 0;
+
+ if (buf[0] != 0 || buf[7] != 0) {
+ base_blk_invalid = true;
+ } else {
+ for (i = 1; i < 7; i++) {
+ if (buf[i] != 0xff) {
+ base_blk_invalid = true;
+ break;
+ }
+ }
+ }
+ /* judge header strickly, only if both header invalid */
+ if (buf[0x7e] > 0) {
+ if (buf[0x80] != 0x2 && buf[0x80] != 0xf0)
+ ext_blk_invalid = true;
+ ret = base_blk_invalid && ext_blk_invalid;
+ } else {
+ ret = base_blk_invalid;
+ }
+
+ return ret;
+}
+
+static bool hdmitx_edid_notify_ng(unsigned char *buf)
+{
+ if (!buf)
+ return true;
+ /* notify EDID NG to systemcontrol */
+ if (hdmitx_check_edid_all_zeros(buf)) {
+ printf("ERR: edid all zero\n");
+ return true;
+ } else if ((buf[0x7e] > 3) &&
+ hdmitx_edid_header_invalid(buf)) {
+ printf("ERR: edid header invalid\n");
+ return true;
+ }
+ /* may extend NG case here */
+
+ return false;
+}
+
+bool edid_parsing_ok(struct hdmitx_dev *hdev)
+{
+ if (!hdev)
+ return false;
+
+ if (hdmitx_edid_notify_ng(hdev->rawedid))
+ return false;
+ return true;
+}
+
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx_common.h b/drivers/amlogic/media/vout/hdmitx/hdmitx_common.h
deleted file mode 100644
index d041a3c..0000000
--- a/drivers/amlogic/media/vout/hdmitx/hdmitx_common.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * driver/amlogic/media/vout/hdmitx/hdmitx_common.h
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#ifndef __HDMITX_COMMON_H__
-#define __HDMITX_COMMON_H__
-
-#include <common.h>
-#include <amlogic/media/vout/hdmitx.h>
-
-#define CLK_UTIL_VID_PLL_DIV_1 0
-#define CLK_UTIL_VID_PLL_DIV_2 1
-#define CLK_UTIL_VID_PLL_DIV_3 2
-#define CLK_UTIL_VID_PLL_DIV_3p5 3
-#define CLK_UTIL_VID_PLL_DIV_3p75 4
-#define CLK_UTIL_VID_PLL_DIV_4 5
-#define CLK_UTIL_VID_PLL_DIV_5 6
-#define CLK_UTIL_VID_PLL_DIV_6 7
-#define CLK_UTIL_VID_PLL_DIV_6p25 8
-#define CLK_UTIL_VID_PLL_DIV_7 9
-#define CLK_UTIL_VID_PLL_DIV_7p5 10
-#define CLK_UTIL_VID_PLL_DIV_12 11
-#define CLK_UTIL_VID_PLL_DIV_14 12
-#define CLK_UTIL_VID_PLL_DIV_15 13
-#define CLK_UTIL_VID_PLL_DIV_2p5 14
-#define CLK_UTIL_VID_PLL_DIV_3p25 15
-
-enum viu_type {
- VIU_ENCL = 0,
- VIU_ENCI,
- VIU_ENCP,
- VIU_ENCT,
-};
-
-typedef struct{
- enum hdmi_vic vic;
- unsigned viu_path;
- enum viu_type viu_type;
- unsigned hpll_clk_out;
- unsigned od1;
- unsigned od2;
- unsigned od3;
- unsigned vid_pll_div;
- unsigned vid_clk_div;
- unsigned hdmi_tx_pixel_div;
- unsigned encp_div;
- unsigned enci_div;
-}hw_enc_clk_val_t;
-
-#define GROUP_MAX 10
-#define GROUP_END -1
-struct hw_enc_clk_val_group {
- enum hdmi_vic group[GROUP_MAX];
- unsigned viu_path;
- enum viu_type viu_type;
- unsigned hpll_clk_out;
- unsigned od1;
- unsigned od2;
- unsigned od3;
- unsigned vid_pll_div;
- unsigned vid_clk_div;
- unsigned hdmi_tx_pixel_div;
- unsigned encp_div;
- unsigned enci_div;
-};
-
-struct reg_t {
- volatile unsigned int* reg;
- unsigned int val;
-};
-
-extern void hdmitx_set_clk(struct hdmitx_dev *hdev);
-extern void set_hdmitx_clk_420(void);
-extern void set_vmode_enc_hw(enum hdmi_vic vic);
-
-#endif
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx_hdcp.c b/drivers/amlogic/media/vout/hdmitx/hdmitx_hdcp.c
deleted file mode 100644
index c64c121..0000000
--- a/drivers/amlogic/media/vout/hdmitx/hdmitx_hdcp.c
+++ /dev/null
@@ -1,85 +0,0 @@
-
-/*
- * arch/arm/cpu/armv8/txl/hdmitx20/hdmitx_hdcp.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <asm/arch/io.h>
-#include <common.h>
-#include "hdmi_tx_reg.h"
-
-// if the following bits are 0, then access HDMI IP Port will cause system hungup
-#define GATE_NUM 2
-
-static struct Hdmi_Gate_s{
- unsigned short cbus_addr;
- unsigned char gate_bit;
-}hdmi_gate[GATE_NUM] = { {HHI_HDMI_CLK_CNTL, 8},
- {HHI_GCLK_MPEG2 , 4},
- };
-
-// In order to prevent system hangup, add check_cts_hdmi_sys_clk_status() to check
-static void check_cts_hdmi_sys_clk_status(void)
-{
- int i;
-
- for (i = 0; i < GATE_NUM; i++) {
- if (!(READ_CBUS_REG(hdmi_gate[i].cbus_addr) & (1<<hdmi_gate[i].gate_bit))) {
-// printf("HDMI Gate Clock is off, turn on now\n");
- WRITE_CBUS_REG_BITS(hdmi_gate[i].cbus_addr, 1, hdmi_gate[i].gate_bit, 1);
- }
- }
-}
-
-unsigned long hdmi_hdcp_rd_reg(unsigned long addr)
-{
- unsigned long data;
- check_cts_hdmi_sys_clk_status();
- WRITE_APB_REG(HDMI_ADDR_PORT, addr);
- WRITE_APB_REG(HDMI_ADDR_PORT, addr);
-
- data = READ_APB_REG(HDMI_DATA_PORT);
-
- return (data);
-}
-
-void hdmi_hdcp_wr_reg(unsigned long addr, unsigned long data)
-{
- check_cts_hdmi_sys_clk_status();
- WRITE_APB_REG(HDMI_ADDR_PORT, addr);
- WRITE_APB_REG(HDMI_ADDR_PORT, addr);
-
- WRITE_APB_REG(HDMI_DATA_PORT, data);
-}
-
-#define TX_HDCP_KSV_OFFSET 0x540
-#define TX_HDCP_KSV_SIZE 5
-// Must be done by system init
-// In kenrel hdmi driver, it will get AKSV value
-// If equals to 0, then kernel won't enable HDCP
-extern int hdmi_hdcp_clear_ksv_ram(void);
-int hdmi_hdcp_clear_ksv_ram(void)
-{
- int i;
- for (i = 0; i < TX_HDCP_KSV_SIZE; i++) {
- hdmi_hdcp_wr_reg(TX_HDCP_KSV_OFFSET + i, 0x00);
- }
- printf("clr h-ram\n");
- return 0;
-}
-
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx_reg.h b/drivers/amlogic/media/vout/hdmitx/hdmitx_reg.h
deleted file mode 100644
index 49324f1..0000000
--- a/drivers/amlogic/media/vout/hdmitx/hdmitx_reg.h
+++ /dev/null
@@ -1,1013 +0,0 @@
-/*
- * driver/amlogic/media/vout/hdmitx/hdmitx_reg.h
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#ifndef _HDMI_TX_REG_H
-#define _HDMI_TX_REG_H
-
-/* TOP-level wrapper registers addresses */
-/* bit24: 1 means secure access */
-/* bit28: 1 means DWC, 0 means TOP */
-#define SEC_OFFSET (0x1UL << 24)
-#define TOP_OFFSET_MASK (0x0UL << 24)
-#define TOP_SEC_OFFSET_MASK ((TOP_OFFSET_MASK) | (SEC_OFFSET))
-#define DWC_OFFSET_MASK (0x10UL << 24)
-#define DWC_SEC_OFFSET_MASK ((DWC_OFFSET_MASK) | (SEC_OFFSET))
-
-/* Bit 7 RW Reserved. Default 1. */
-/* Bit 6 RW Reserved. Default 1. */
-/* Bit 5 RW Reserved. Default 1. */
-/* Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
- * Default 1.
- * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
- * 0=Release from reset. Default 1.
- * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
- * Default 1.
- * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset;
- * 0=Release from reset. Default 1.
- * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset;
- * 0=Release from reset. Default 1.
- */
-#define HDMITX_TOP_SW_RESET (TOP_OFFSET_MASK + 0x000)
-
-/* Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0. */
-/* Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0. */
-/* Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0. */
-/* Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0. */
-/* Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0. */
-/* Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. */
-/* Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0. */
-/* Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0. */
-/* Bit 1 RW tmds_clk_en: 1=enable tmds_clk; 0=disable. Default 0. */
-/* Bit 0 RW pixel_clk_en: 1=enable pixel_clk; 0=disable. Default 0. */
-#define HDMITX_TOP_CLK_CNTL (TOP_OFFSET_MASK + 0x001)
-
-/* Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024. Default 0. */
-/* Bit 15:12 RW hpd_glitch_width: filter out glitch <= N. Default 0. */
-#define HDMITX_TOP_HPD_FILTER (TOP_OFFSET_MASK + 0x002)
-
-/* intr_maskn: MASK_N, one bit per interrupt source.
- * 1=Enable interrupt source; 0=Disable interrupt source. Default 0.
- * [ 4] hdcp22_rndnum_err
- * [ 3] nonce_rfrsh_rise
- * [ 2] hpd_fall_intr
- * [ 1] hpd_rise_intr
- * [ 0] core_intr
- */
-#define HDMITX_TOP_INTR_MASKN (TOP_OFFSET_MASK + 0x003)
-
-/* Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt
- * bit, read back the interrupt status. */
-/* Bit 31 R IP interrupt status */
-/* Bit 2 RW hpd_fall */
-/* Bit 1 RW hpd_rise */
-/* Bit 0 RW IP interrupt */
-#define HDMITX_TOP_INTR_STAT (TOP_OFFSET_MASK + 0x004)
-
-/* [4] hdcp22_rndnum_err */
-/* [3] nonce_rfrsh_rise */
-/* [2] hpd_fall */
-/* [1] hpd_rise */
-/* [0] core_intr_rise */
-#define HDMITX_TOP_INTR_STAT_CLR (TOP_OFFSET_MASK + 0x005)
-
-/* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data;
- * 3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0.
- * Bit 11: 9 RW shift_pttn_repeat: 0=New pattern every clk cycle; 1=New pattern
- * every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0.
- * Bit 8 RW shift_pttn_en: 1= Eanble shift pattern generator; 0=Disable.
- * Default 0.
- * Bit 4: 3 RW prbs_pttn_mode: 0=PRBS11; 1=PRBS15; 2=PRBS7; 3=PRBS31. Default 0.
- * Bit 2: 1 RW prbs_pttn_width: 0=idle; 1=output 8-bit pattern;
- * 2=Output 1-bit pattern; 3=output 10-bit pattern. Default 0.
- * Bit 0 RW prbs_pttn_en: 1=Enable PRBS generator; 0=Disable. Default 0.
- */
-#define HDMITX_TOP_BIST_CNTL (TOP_OFFSET_MASK + 0x006)
-
-/* Bit 29:20 RW shift_pttn_data[59:50]. Default 0. */
-/* Bit 19:10 RW shift_pttn_data[69:60]. Default 0. */
-/* Bit 9: 0 RW shift_pttn_data[79:70]. Default 0. */
-#define HDMITX_TOP_SHIFT_PTTN_012 (TOP_OFFSET_MASK + 0x007)
-
-/* Bit 29:20 RW shift_pttn_data[29:20]. Default 0. */
-/* Bit 19:10 RW shift_pttn_data[39:30]. Default 0. */
-/* Bit 9: 0 RW shift_pttn_data[49:40]. Default 0. */
-#define HDMITX_TOP_SHIFT_PTTN_345 (TOP_OFFSET_MASK + 0x008)
-
-/* Bit 19:10 RW shift_pttn_data[ 9: 0]. Default 0. */
-/* Bit 9: 0 RW shift_pttn_data[19:10]. Default 0. */
-#define HDMITX_TOP_SHIFT_PTTN_67 (TOP_OFFSET_MASK + 0x009)
-
-/* Bit 25:16 RW tmds_clk_pttn[19:10]. Default 0. */
-/* Bit 9: 0 RW tmds_clk_pttn[ 9: 0]. Default 0. */
-#define HDMITX_TOP_TMDS_CLK_PTTN_01 (TOP_OFFSET_MASK + 0x00A)
-
-/* Bit 25:16 RW tmds_clk_pttn[39:30]. Default 0. */
-/* Bit 9: 0 RW tmds_clk_pttn[29:20]. Default 0. */
-#define HDMITX_TOP_TMDS_CLK_PTTN_23 (TOP_OFFSET_MASK + 0x00B)
-
-/* Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern,
- * used when TMDS CLK rate = TMDS character rate /4. Default 0.
- * Bit 0 R Reserved. Default 0.
- */
-/* [ 1] shift_tmds_clk_pttn */
-/* [ 0] load_tmds_clk_pttn */
-#define HDMITX_TOP_TMDS_CLK_PTTN_CNTL (TOP_OFFSET_MASK + 0x00C)
-
-/* Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM
- * failure, write 1 to clear the failure flag. Default 0.
- */
-#define HDMITX_TOP_REVOCMEM_STAT (TOP_OFFSET_MASK + 0x00D)
-
-/* Bit 0 R filtered HPD status. */
-#define HDMITX_TOP_STAT0 (TOP_OFFSET_MASK + 0x00E)
-#define HDMITX_TOP_SKP_CNTL_STAT (TOP_SEC_OFFSET_MASK + 0x010)
-#define HDMITX_TOP_NONCE_0 (TOP_SEC_OFFSET_MASK + 0x011)
-#define HDMITX_TOP_NONCE_1 (TOP_SEC_OFFSET_MASK + 0x012)
-#define HDMITX_TOP_NONCE_2 (TOP_SEC_OFFSET_MASK + 0x013)
-#define HDMITX_TOP_NONCE_3 (TOP_SEC_OFFSET_MASK + 0x014)
-#define HDMITX_TOP_PKF_0 (TOP_SEC_OFFSET_MASK + 0x015)
-#define HDMITX_TOP_PKF_1 (TOP_SEC_OFFSET_MASK + 0x016)
-#define HDMITX_TOP_PKF_2 (TOP_SEC_OFFSET_MASK + 0x017)
-#define HDMITX_TOP_PKF_3 (TOP_SEC_OFFSET_MASK + 0x018)
-#define HDMITX_TOP_DUK_0 (TOP_SEC_OFFSET_MASK + 0x019)
-#define HDMITX_TOP_DUK_1 (TOP_SEC_OFFSET_MASK + 0x01A)
-#define HDMITX_TOP_DUK_2 (TOP_SEC_OFFSET_MASK + 0x01B)
-#define HDMITX_TOP_DUK_3 (TOP_SEC_OFFSET_MASK + 0x01C)
-/* [26:24] infilter_ddc_intern_clk_divide */
-/* [23:16] infilter_ddc_sample_clk_divide */
-/* [10: 8] infilter_cec_intern_clk_divide */
-/* [ 7: 0] infilter_cec_sample_clk_divide */
-#define HDMITX_TOP_INFILTER (TOP_OFFSET_MASK + 0x01D)
-#define HDMITX_TOP_NSEC_SCRATCH (TOP_OFFSET_MASK + 0x01E)
-#define HDMITX_TOP_SEC_SCRATCH (TOP_SEC_OFFSET_MASK + 0x01F)
-#define HDMITX_TOP_EMP_CNTL0 (TOP_OFFSET_MASK + 0x020)
-#define HDMITX_TOP_EMP_CNTL1 (TOP_OFFSET_MASK + 0x021)
-#define HDMITX_TOP_EMP_MEMADDR_START (TOP_OFFSET_MASK + 0x022)
-#define HDMITX_TOP_EMP_STAT0 (TOP_OFFSET_MASK + 0x023)
-#define HDMITX_TOP_EMP_STAT1 (TOP_OFFSET_MASK + 0x024)
-#define HDMITX_TOP_AXI_ASYNC_CNTL0 (TOP_OFFSET_MASK + 0x025)
-#define HDMITX_TOP_AXI_ASYNC_CNTL1 (TOP_OFFSET_MASK + 0x026)
-#define HDMITX_TOP_AXI_ASYNC_STAT0 (TOP_OFFSET_MASK + 0x027)
-#define HDMITX_TOP_I2C_BUSY_CNT_MAX (TOP_OFFSET_MASK + 0x028)
-#define HDMITX_TOP_I2C_BUSY_CNT_STAT (TOP_OFFSET_MASK + 0x029)
-#define HDMITX_TOP_HDCP22_BSOD (TOP_OFFSET_MASK + 0x02A)
-#define HDMITX_TOP_DDC_CNTL (TOP_OFFSET_MASK + 0x02B)
-#define HDMITX_TOP_REVOCMEM_ADDR_S (TOP_OFFSET_MASK + 0x2000)
-#define HDMITX_TOP_REVOCMEM_ADDR_E (TOP_OFFSET_MASK + 0x365E)
-
-#define HDMITX_TOP_DONT_TOUCH0 (TOP_OFFSET_MASK + 0x0FE)
-#define HDMITX_TOP_DONT_TOUCH1 (TOP_OFFSET_MASK + 0x0FF)
-
-/* DWC_HDMI_TX Controller registers addresses */
-
-/* Identification Registers */
-#define HDMITX_DWC_DESIGN_ID (DWC_OFFSET_MASK + 0x0000)
-#define HDMITX_DWC_REVISION_ID (DWC_OFFSET_MASK + 0x0001)
-#define HDMITX_DWC_PRODUCT_ID0 (DWC_OFFSET_MASK + 0x0002)
-#define HDMITX_DWC_PRODUCT_ID1 (DWC_OFFSET_MASK + 0x0003)
-#define HDMITX_DWC_CONFIG0_ID (DWC_OFFSET_MASK + 0x0004)
-#define HDMITX_DWC_CONFIG1_ID (DWC_OFFSET_MASK + 0x0005)
-#define HDMITX_DWC_CONFIG2_ID (DWC_OFFSET_MASK + 0x0006)
-#define HDMITX_DWC_CONFIG3_ID (DWC_OFFSET_MASK + 0x0007)
-
-/* Interrupt Registers */
-#define HDMITX_DWC_IH_FC_STAT0 (DWC_OFFSET_MASK + 0x0100)
-#define HDMITX_DWC_IH_FC_STAT1 (DWC_OFFSET_MASK + 0x0101)
-#define HDMITX_DWC_IH_FC_STAT2 (DWC_OFFSET_MASK + 0x0102)
-#define HDMITX_DWC_IH_AS_STAT0 (DWC_OFFSET_MASK + 0x0103)
-#define HDMITX_DWC_IH_PHY_STAT0 (DWC_OFFSET_MASK + 0x0104)
-#define HDMITX_DWC_IH_I2CM_STAT0 (DWC_OFFSET_MASK + 0x0105)
-#define HDMITX_DWC_IH_CEC_STAT0 (DWC_OFFSET_MASK + 0x0106)
-#define HDMITX_DWC_IH_VP_STAT0 (DWC_OFFSET_MASK + 0x0107)
-#define HDMITX_DWC_IH_I2CMPHY_STAT0 (DWC_OFFSET_MASK + 0x0108)
-#define HDMITX_DWC_IH_DECODE (DWC_OFFSET_MASK + 0x0170)
-/* [ 7] mute_AUDI */
-/* [ 6] mute_ACP */
-/* [ 5] mute_HBR */
-/* [ 4] mute_MAS */
-/* [ 3] mute_NVBI */
-/* [ 2] mute_AUDS */
-/* [ 1] mute_ACR */
-/* [ 0] mute_NULL */
-#define HDMITX_DWC_IH_MUTE_FC_STAT0 (DWC_OFFSET_MASK + 0x0180)
-/* [ 7] mute_GMD */
-/* [ 6] mute_ISRC1 */
-/* [ 5] mute_ISRC2 */
-/* [ 4] mute_VSD */
-/* [ 3] mute_SPD */
-/* [ 2] mute_AMP */
-/* [ 1] mute_AVI */
-/* [ 0] mute_GCP */
-#define HDMITX_DWC_IH_MUTE_FC_STAT1 (DWC_OFFSET_MASK + 0x0181)
-/* [ 1] mute_LowPriority_fifo_full */
-/* [ 0] mute_HighPriority_fifo_full */
-#define HDMITX_DWC_IH_MUTE_FC_STAT2 (DWC_OFFSET_MASK + 0x0182)
-/* [ 4] mute_aud_fifo_underrun */
-/* [ 3] mute_aud_fifo_overrun */
-/* [ 2] mute_aud_fifo_empty_thr. oififoemptythr tied to 0. */
-/* [ 1] mute_aud_fifo_empty */
-/* [ 0] mute_aud_fifo_full */
-#define HDMITX_DWC_IH_MUTE_AS_STAT0 (DWC_OFFSET_MASK + 0x0183)
-#define HDMITX_DWC_IH_MUTE_PHY_STAT0 (DWC_OFFSET_MASK + 0x0184)
-/* [ 2] mute_scdc_readreq */
-/* [ 1] mute_edid_i2c_master_done */
-/* [ 0] mute_edid_i2c_master_error */
-#define HDMITX_DWC_IH_MUTE_I2CM_STAT0 (DWC_OFFSET_MASK + 0x0185)
-/* [ 6] cec_wakeup */
-/* [ 5] cec_error_follower */
-/* [ 4] cec_error_initiator */
-/* [ 3] cec_arb_lost */
-/* [ 2] cec_nack */
-/* [ 1] cec_eom */
-/* [ 0] cec_done */
-#define HDMITX_DWC_IH_MUTE_CEC_STAT0 (DWC_OFFSET_MASK + 0x0186)
-#define HDMITX_DWC_IH_MUTE_VP_STAT0 (DWC_OFFSET_MASK + 0x0187)
-#define HDMITX_DWC_IH_MUTE_I2CMPHY_STAT0 (DWC_OFFSET_MASK + 0x0188)
-/* [ 1] mute_wakeup_interrupt */
-/* [ 0] mute_all_interrupt */
-#define HDMITX_DWC_IH_MUTE (DWC_OFFSET_MASK + 0x01FF)
-
-/* Video Sampler Registers */
-/* [ 7] internal_de_generator */
-/* [4:0] video_mapping */
-#define HDMITX_DWC_TX_INVID0 (DWC_OFFSET_MASK + 0x0200)
-/* [ 2] bcbdata_stuffing */
-/* [ 1] rcrdata_stuffing */
-/* [ 0] gydata_stuffing */
-#define HDMITX_DWC_TX_INSTUFFING (DWC_OFFSET_MASK + 0x0201)
-#define HDMITX_DWC_TX_GYDATA0 (DWC_OFFSET_MASK + 0x0202)
-#define HDMITX_DWC_TX_GYDATA1 (DWC_OFFSET_MASK + 0x0203)
-#define HDMITX_DWC_TX_RCRDATA0 (DWC_OFFSET_MASK + 0x0204)
-#define HDMITX_DWC_TX_RCRDATA1 (DWC_OFFSET_MASK + 0x0205)
-#define HDMITX_DWC_TX_BCBDATA0 (DWC_OFFSET_MASK + 0x0206)
-#define HDMITX_DWC_TX_BCBDATA1 (DWC_OFFSET_MASK + 0x0207)
-
-/* Video Packetizer Registers */
-#define HDMITX_DWC_VP_STATUS (DWC_OFFSET_MASK + 0x0800)
-/* [3:0] desired_pr_factor */
-#define HDMITX_DWC_VP_PR_CD (DWC_OFFSET_MASK + 0x0801)
-/* [ 5] default_phase */
-/* [ 2] ycc422_stuffing */
-/* [ 1] pp_stuffing */
-/* [ 0] pr_stuffing */
-#define HDMITX_DWC_VP_STUFF (DWC_OFFSET_MASK + 0x0802)
-#define HDMITX_DWC_VP_REMAP (DWC_OFFSET_MASK + 0x0803)
-#define HDMITX_DWC_VP_CONF (DWC_OFFSET_MASK + 0x0804)
-/* [ 7] mask_int_full_prpt */
-/* [ 6] mask_int_empty_prpt */
-/* [ 5] mask_int_full_ppack */
-/* [ 4] mask_int_empty_ppack */
-/* [ 3] mask_int_full_remap */
-/* [ 2] mask_int_empty_remap */
-/* [ 1] mask_int_full_byp */
-/* [ 0] mask_int_empty_byp */
-#define HDMITX_DWC_VP_MASK (DWC_OFFSET_MASK + 0x0807)
-
-/* Frmae Composer Registers */
-/* [ 7] HDCP_keepout */
-/* [ 6] vs_in_pol: 0=active low; 1=active high. */
-/* [ 5] hs_in_pol: 0=active low; 1=active high. */
-/* [ 4] de_in_pol: 0=active low; 1=active high. */
-/* [ 3] dvi_modez: 0=dvi; 1=hdmi. */
-/* [ 1] r_v_blank_in_osc */
-/* [ 0] in_I_P: 0=progressive; 1=interlaced. */
-#define HDMITX_DWC_FC_INVIDCONF (DWC_OFFSET_MASK + 0x1000)
-/* [7:0] H_in_active[7:0] */
-#define HDMITX_DWC_FC_INHACTV0 (DWC_OFFSET_MASK + 0x1001)
-/* [5:0] H_in_active[13:8] */
-#define HDMITX_DWC_FC_INHACTV1 (DWC_OFFSET_MASK + 0x1002)
-/* [7:0] H_in_blank[7:0] */
-#define HDMITX_DWC_FC_INHBLANK0 (DWC_OFFSET_MASK + 0x1003)
-/* [4:0] H_in_blank[12:8] */
-#define HDMITX_DWC_FC_INHBLANK1 (DWC_OFFSET_MASK + 0x1004)
-/* [7:0] V_in_active[7:0] */
-#define HDMITX_DWC_FC_INVACTV0 (DWC_OFFSET_MASK + 0x1005)
-/* [4:0] V_in_active[12:8] */
-#define HDMITX_DWC_FC_INVACTV1 (DWC_OFFSET_MASK + 0x1006)
-/* [7:0] V_in_blank */
-#define HDMITX_DWC_FC_INVBLANK (DWC_OFFSET_MASK + 0x1007)
-/* [7:0] H_in_delay[7:0] */
-#define HDMITX_DWC_FC_HSYNCINDELAY0 (DWC_OFFSET_MASK + 0x1008)
-/* [4:0] H_in_delay[12:8] */
-#define HDMITX_DWC_FC_HSYNCINDELAY1 (DWC_OFFSET_MASK + 0x1009)
-/* [7:0] H_in_width[7:0] */
-#define HDMITX_DWC_FC_HSYNCINWIDTH0 (DWC_OFFSET_MASK + 0x100A)
-/* [1:0] H_in_width[9:8] */
-#define HDMITX_DWC_FC_HSYNCINWIDTH1 (DWC_OFFSET_MASK + 0x100B)
-/* [7:0] V_in_delay */
-#define HDMITX_DWC_FC_VSYNCINDELAY (DWC_OFFSET_MASK + 0x100C)
-/* [5:0] V_in_width */
-#define HDMITX_DWC_FC_VSYNCINWIDTH (DWC_OFFSET_MASK + 0x100D)
-#define HDMITX_DWC_FC_INFREQ0 (DWC_OFFSET_MASK + 0x100E)
-#define HDMITX_DWC_FC_INFREQ1 (DWC_OFFSET_MASK + 0x100F)
-#define HDMITX_DWC_FC_INFREQ2 (DWC_OFFSET_MASK + 0x1010)
-#define HDMITX_DWC_FC_CTRLDUR (DWC_OFFSET_MASK + 0x1011)
-#define HDMITX_DWC_FC_EXCTRLDUR (DWC_OFFSET_MASK + 0x1012)
-#define HDMITX_DWC_FC_EXCTRLSPAC (DWC_OFFSET_MASK + 0x1013)
-#define HDMITX_DWC_FC_CH0PREAM (DWC_OFFSET_MASK + 0x1014)
-#define HDMITX_DWC_FC_CH1PREAM (DWC_OFFSET_MASK + 0x1015)
-#define HDMITX_DWC_FC_CH2PREAM (DWC_OFFSET_MASK + 0x1016)
-/* [3:2] YQ */
-/* [1:0] CN */
-#define HDMITX_DWC_FC_AVICONF3 (DWC_OFFSET_MASK + 0x1017)
-/* [ 2] default_phase */
-/* [ 1] set_avmute */
-/* [ 0] clear_avmute */
-#define HDMITX_DWC_FC_GCP (DWC_OFFSET_MASK + 0x1018)
-/* [ 7] rgb_ycc_indication[2] */
-/* [ 6] active_format_present */
-/* [5:4] scan_information */
-/* [3:2] bar_information */
-/* [1:0] rgb_ycc_indication[1:0] */
-#define HDMITX_DWC_FC_AVICONF0 (DWC_OFFSET_MASK + 0x1019)
-/* [7:6] colorimetry */
-/* [5:4] picture_aspect_ratio */
-/* [3:0] active_aspect_ratio */
-#define HDMITX_DWC_FC_AVICONF1 (DWC_OFFSET_MASK + 0x101A)
-/* [ 7] IT_content */
-/* [6:4] extended_colorimetry */
-/* [3:2] quantization_range */
-/* [1:0] non_uniform_picture_scaling */
-#define HDMITX_DWC_FC_AVICONF2 (DWC_OFFSET_MASK + 0x101B)
-#define HDMITX_DWC_FC_AVIVID (DWC_OFFSET_MASK + 0x101C)
-#define HDMITX_DWC_FC_AVIETB0 (DWC_OFFSET_MASK + 0x101D)
-#define HDMITX_DWC_FC_AVIETB1 (DWC_OFFSET_MASK + 0x101E)
-#define HDMITX_DWC_FC_AVISBB0 (DWC_OFFSET_MASK + 0x101F)
-#define HDMITX_DWC_FC_AVISBB1 (DWC_OFFSET_MASK + 0x1020)
-#define HDMITX_DWC_FC_AVIELB0 (DWC_OFFSET_MASK + 0x1021)
-#define HDMITX_DWC_FC_AVIELB1 (DWC_OFFSET_MASK + 0x1022)
-#define HDMITX_DWC_FC_AVISRB0 (DWC_OFFSET_MASK + 0x1023)
-#define HDMITX_DWC_FC_AVISRB1 (DWC_OFFSET_MASK + 0x1024)
-/* [3:0] CT: coding type */
-#define HDMITX_DWC_FC_AUDICONF0 (DWC_OFFSET_MASK + 0x1025)
-/* [5:4] SS: sampling size */
-/* [2:0] SF: sampling frequency */
-#define HDMITX_DWC_FC_AUDICONF1 (DWC_OFFSET_MASK + 0x1026)
-/* CA: channel allocation */
-#define HDMITX_DWC_FC_AUDICONF2 (DWC_OFFSET_MASK + 0x1027)
-/* [6:5] LFEPBL: LFE playback info */
-/* [ 4] DM_INH: down mix enable */
-/* [3:0] LSv: Level shift value */
-#define HDMITX_DWC_FC_AUDICONF3 (DWC_OFFSET_MASK + 0x1028)
-#define HDMITX_DWC_FC_VSDIEEEID0 (DWC_OFFSET_MASK + 0x1029)
-#define HDMITX_DWC_FC_VSDSIZE (DWC_OFFSET_MASK + 0x102A)
-#define HDMITX_DWC_FC_VSDIEEEID1 (DWC_OFFSET_MASK + 0x1030)
-#define HDMITX_DWC_FC_VSDIEEEID2 (DWC_OFFSET_MASK + 0x1031)
-#define HDMITX_DWC_FC_VSDPAYLOAD0 (DWC_OFFSET_MASK + 0x1032)
-#define HDMITX_DWC_FC_VSDPAYLOAD1 (DWC_OFFSET_MASK + 0x1033)
-#define HDMITX_DWC_FC_VSDPAYLOAD2 (DWC_OFFSET_MASK + 0x1034)
-#define HDMITX_DWC_FC_VSDPAYLOAD3 (DWC_OFFSET_MASK + 0x1035)
-#define HDMITX_DWC_FC_VSDPAYLOAD4 (DWC_OFFSET_MASK + 0x1036)
-#define HDMITX_DWC_FC_VSDPAYLOAD5 (DWC_OFFSET_MASK + 0x1037)
-#define HDMITX_DWC_FC_VSDPAYLOAD6 (DWC_OFFSET_MASK + 0x1038)
-#define HDMITX_DWC_FC_VSDPAYLOAD7 (DWC_OFFSET_MASK + 0x1039)
-#define HDMITX_DWC_FC_VSDPAYLOAD8 (DWC_OFFSET_MASK + 0x103A)
-#define HDMITX_DWC_FC_VSDPAYLOAD9 (DWC_OFFSET_MASK + 0x103B)
-#define HDMITX_DWC_FC_VSDPAYLOAD10 (DWC_OFFSET_MASK + 0x103C)
-#define HDMITX_DWC_FC_VSDPAYLOAD11 (DWC_OFFSET_MASK + 0x103D)
-#define HDMITX_DWC_FC_VSDPAYLOAD12 (DWC_OFFSET_MASK + 0x103E)
-#define HDMITX_DWC_FC_VSDPAYLOAD13 (DWC_OFFSET_MASK + 0x103F)
-#define HDMITX_DWC_FC_VSDPAYLOAD14 (DWC_OFFSET_MASK + 0x1040)
-#define HDMITX_DWC_FC_VSDPAYLOAD15 (DWC_OFFSET_MASK + 0x1041)
-#define HDMITX_DWC_FC_VSDPAYLOAD16 (DWC_OFFSET_MASK + 0x1042)
-#define HDMITX_DWC_FC_VSDPAYLOAD17 (DWC_OFFSET_MASK + 0x1043)
-#define HDMITX_DWC_FC_VSDPAYLOAD18 (DWC_OFFSET_MASK + 0x1044)
-#define HDMITX_DWC_FC_VSDPAYLOAD19 (DWC_OFFSET_MASK + 0x1045)
-#define HDMITX_DWC_FC_VSDPAYLOAD20 (DWC_OFFSET_MASK + 0x1046)
-#define HDMITX_DWC_FC_VSDPAYLOAD21 (DWC_OFFSET_MASK + 0x1047)
-#define HDMITX_DWC_FC_VSDPAYLOAD22 (DWC_OFFSET_MASK + 0x1048)
-#define HDMITX_DWC_FC_VSDPAYLOAD23 (DWC_OFFSET_MASK + 0x1049)
-#define HDMITX_DWC_FC_SPDVENDORNAME0 (DWC_OFFSET_MASK + 0x104A)
-#define HDMITX_DWC_FC_SPDVENDORNAME1 (DWC_OFFSET_MASK + 0x104B)
-#define HDMITX_DWC_FC_SPDVENDORNAME2 (DWC_OFFSET_MASK + 0x104C)
-#define HDMITX_DWC_FC_SPDVENDORNAME3 (DWC_OFFSET_MASK + 0x104D)
-#define HDMITX_DWC_FC_SPDVENDORNAME4 (DWC_OFFSET_MASK + 0x104E)
-#define HDMITX_DWC_FC_SPDVENDORNAME5 (DWC_OFFSET_MASK + 0x104F)
-#define HDMITX_DWC_FC_SPDVENDORNAME6 (DWC_OFFSET_MASK + 0x1050)
-#define HDMITX_DWC_FC_SPDVENDORNAME7 (DWC_OFFSET_MASK + 0x1051)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME0 (DWC_OFFSET_MASK + 0x1052)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME1 (DWC_OFFSET_MASK + 0x1053)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME2 (DWC_OFFSET_MASK + 0x1054)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME3 (DWC_OFFSET_MASK + 0x1055)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME4 (DWC_OFFSET_MASK + 0x1056)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME5 (DWC_OFFSET_MASK + 0x1057)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME6 (DWC_OFFSET_MASK + 0x1058)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME7 (DWC_OFFSET_MASK + 0x1059)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME8 (DWC_OFFSET_MASK + 0x105A)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME9 (DWC_OFFSET_MASK + 0x105B)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME10 (DWC_OFFSET_MASK + 0x105C)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME11 (DWC_OFFSET_MASK + 0x105D)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME12 (DWC_OFFSET_MASK + 0x105E)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME13 (DWC_OFFSET_MASK + 0x105F)
-#define HDMITX_DWC_FC_SDPPRODUCTNAME14 (DWC_OFFSET_MASK + 0x1060)
-#define HDMITX_DWC_FC_SPDPRODUCTNAME15 (DWC_OFFSET_MASK + 0x1061)
-#define HDMITX_DWC_FC_SPDDEVICEINF (DWC_OFFSET_MASK + 0x1062)
-/* [7:4] aud_packet_sampflat */
-/* [ 0] aud_packet_layout */
-#define HDMITX_DWC_FC_AUDSCONF (DWC_OFFSET_MASK + 0x1063)
-#define HDMITX_DWC_FC_AUDSSTAT (DWC_OFFSET_MASK + 0x1064)
-/* [ 7] V3r */
-/* [ 6] V2r */
-/* [ 5] V1r */
-/* [ 4] V0r */
-/* [ 3] V3l */
-/* [ 2] V2l */
-/* [ 1] V1l */
-/* [ 0] V0l */
-#define HDMITX_DWC_FC_AUDSV (DWC_OFFSET_MASK + 0x1065)
-#define HDMITX_DWC_FC_AUDSU (DWC_OFFSET_MASK + 0x1066)
-#define HDMITX_DWC_FC_AUDSCHNLS0 (DWC_OFFSET_MASK + 0x1067)
-#define HDMITX_DWC_FC_AUDSCHNLS1 (DWC_OFFSET_MASK + 0x1068)
-#define HDMITX_DWC_FC_AUDSCHNLS2 (DWC_OFFSET_MASK + 0x1069)
-#define HDMITX_DWC_FC_AUDSCHNLS3 (DWC_OFFSET_MASK + 0x106A)
-#define HDMITX_DWC_FC_AUDSCHNLS4 (DWC_OFFSET_MASK + 0x106B)
-#define HDMITX_DWC_FC_AUDSCHNLS5 (DWC_OFFSET_MASK + 0x106C)
-#define HDMITX_DWC_FC_AUDSCHNLS6 (DWC_OFFSET_MASK + 0x106D)
-#define HDMITX_DWC_FC_AUDSCHNLS7 (DWC_OFFSET_MASK + 0x106E)
-#define HDMITX_DWC_FC_AUDSCHNLS8 (DWC_OFFSET_MASK + 0x106F)
-#define HDMITX_DWC_FC_DATACH0FILL (DWC_OFFSET_MASK + 0x1070)
-#define HDMITX_DWC_FC_DATACH1FILL (DWC_OFFSET_MASK + 0x1071)
-#define HDMITX_DWC_FC_DATACH2FILL (DWC_OFFSET_MASK + 0x1072)
-#define HDMITX_DWC_FC_CTRLQHIGH (DWC_OFFSET_MASK + 0x1073)
-#define HDMITX_DWC_FC_CTRLQLOW (DWC_OFFSET_MASK + 0x1074)
-#define HDMITX_DWC_FC_ACP0 (DWC_OFFSET_MASK + 0x1075)
-#define HDMITX_DWC_FC_ACP16 (DWC_OFFSET_MASK + 0x1082)
-#define HDMITX_DWC_FC_ACP15 (DWC_OFFSET_MASK + 0x1083)
-#define HDMITX_DWC_FC_ACP14 (DWC_OFFSET_MASK + 0x1084)
-#define HDMITX_DWC_FC_ACP13 (DWC_OFFSET_MASK + 0x1085)
-#define HDMITX_DWC_FC_ACP12 (DWC_OFFSET_MASK + 0x1086)
-#define HDMITX_DWC_FC_ACP11 (DWC_OFFSET_MASK + 0x1087)
-#define HDMITX_DWC_FC_ACP10 (DWC_OFFSET_MASK + 0x1088)
-#define HDMITX_DWC_FC_ACP9 (DWC_OFFSET_MASK + 0x1089)
-#define HDMITX_DWC_FC_ACP8 (DWC_OFFSET_MASK + 0x108A)
-#define HDMITX_DWC_FC_ACP7 (DWC_OFFSET_MASK + 0x108B)
-#define HDMITX_DWC_FC_ACP6 (DWC_OFFSET_MASK + 0x108C)
-#define HDMITX_DWC_FC_ACP5 (DWC_OFFSET_MASK + 0x108D)
-#define HDMITX_DWC_FC_ACP4 (DWC_OFFSET_MASK + 0x108E)
-#define HDMITX_DWC_FC_ACP3 (DWC_OFFSET_MASK + 0x108F)
-#define HDMITX_DWC_FC_ACP2 (DWC_OFFSET_MASK + 0x1090)
-#define HDMITX_DWC_FC_ACP1 (DWC_OFFSET_MASK + 0x1091)
-#define HDMITX_DWC_FC_ISCR1_0 (DWC_OFFSET_MASK + 0x1092)
-#define HDMITX_DWC_FC_ISCR1_16 (DWC_OFFSET_MASK + 0x1093)
-#define HDMITX_DWC_FC_ISCR1_15 (DWC_OFFSET_MASK + 0x1094)
-#define HDMITX_DWC_FC_ISCR1_14 (DWC_OFFSET_MASK + 0x1095)
-#define HDMITX_DWC_FC_ISCR1_13 (DWC_OFFSET_MASK + 0x1096)
-#define HDMITX_DWC_FC_ISCR1_12 (DWC_OFFSET_MASK + 0x1097)
-#define HDMITX_DWC_FC_ISCR1_11 (DWC_OFFSET_MASK + 0x1098)
-#define HDMITX_DWC_FC_ISCR1_10 (DWC_OFFSET_MASK + 0x1099)
-#define HDMITX_DWC_FC_ISCR1_9 (DWC_OFFSET_MASK + 0x109A)
-#define HDMITX_DWC_FC_ISCR1_8 (DWC_OFFSET_MASK + 0x109B)
-#define HDMITX_DWC_FC_ISCR1_7 (DWC_OFFSET_MASK + 0x109C)
-#define HDMITX_DWC_FC_ISCR1_6 (DWC_OFFSET_MASK + 0x109D)
-#define HDMITX_DWC_FC_ISCR1_5 (DWC_OFFSET_MASK + 0x109E)
-#define HDMITX_DWC_FC_ISCR1_4 (DWC_OFFSET_MASK + 0x109F)
-#define HDMITX_DWC_FC_ISCR1_3 (DWC_OFFSET_MASK + 0x10A0)
-#define HDMITX_DWC_FC_ISCR1_2 (DWC_OFFSET_MASK + 0x10A1)
-#define HDMITX_DWC_FC_ISCR1_1 (DWC_OFFSET_MASK + 0x10A2)
-#define HDMITX_DWC_FC_ISCR0_15 (DWC_OFFSET_MASK + 0x10A3)
-#define HDMITX_DWC_FC_ISCR0_14 (DWC_OFFSET_MASK + 0x10A4)
-#define HDMITX_DWC_FC_ISCR0_13 (DWC_OFFSET_MASK + 0x10A5)
-#define HDMITX_DWC_FC_ISCR0_12 (DWC_OFFSET_MASK + 0x10A6)
-#define HDMITX_DWC_FC_ISCR0_11 (DWC_OFFSET_MASK + 0x10A7)
-#define HDMITX_DWC_FC_ISCR0_10 (DWC_OFFSET_MASK + 0x10A8)
-#define HDMITX_DWC_FC_ISCR0_9 (DWC_OFFSET_MASK + 0x10A9)
-#define HDMITX_DWC_FC_ISCR0_8 (DWC_OFFSET_MASK + 0x10AA)
-#define HDMITX_DWC_FC_ISCR0_7 (DWC_OFFSET_MASK + 0x10AB)
-#define HDMITX_DWC_FC_ISCR0_6 (DWC_OFFSET_MASK + 0x10AC)
-#define HDMITX_DWC_FC_ISCR0_5 (DWC_OFFSET_MASK + 0x10AD)
-#define HDMITX_DWC_FC_ISCR0_4 (DWC_OFFSET_MASK + 0x10AE)
-#define HDMITX_DWC_FC_ISCR0_3 (DWC_OFFSET_MASK + 0x10AF)
-#define HDMITX_DWC_FC_ISCR0_2 (DWC_OFFSET_MASK + 0x10B0)
-#define HDMITX_DWC_FC_ISCR0_1 (DWC_OFFSET_MASK + 0x10B1)
-#define HDMITX_DWC_FC_ISCR0_0 (DWC_OFFSET_MASK + 0x10B2)
-/* [ 4] spd_auto */
-/* [ 3] vsd_auto */
-/* [ 2] isrc2_auto */
-/* [ 1] isrc1_auto */
-/* [ 0] acp_auto */
-#define HDMITX_DWC_FC_DATAUTO0 (DWC_OFFSET_MASK + 0x10B3)
-#define HDMITX_DWC_FC_DATAUTO1 (DWC_OFFSET_MASK + 0x10B4)
-#define HDMITX_DWC_FC_DATAUTO2 (DWC_OFFSET_MASK + 0x10B5)
-#define HDMITX_DWC_FC_DATMAN (DWC_OFFSET_MASK + 0x10B6)
-/* [ 5] nvbi_auto: insert on Vsync */
-/* [ 4] amp_auto: insert on Vsync */
-/* [ 3] avi_auto: insert on Vsync */
-/* [ 2] gcp_auto: insert on Vsync */
-/* [ 1] audi_auto: insert on Vsync */
-/* [ 0] acr_auto: insert on CTS update. Assert this bit later to avoid
- * inital packets with false CTS value
- */
-#define HDMITX_DWC_FC_DATAUTO3 (DWC_OFFSET_MASK + 0x10B7)
-#define HDMITX_DWC_FC_RDRB0 (DWC_OFFSET_MASK + 0x10B8)
-#define HDMITX_DWC_FC_RDRB1 (DWC_OFFSET_MASK + 0x10B9)
-#define HDMITX_DWC_FC_RDRB2 (DWC_OFFSET_MASK + 0x10BA)
-#define HDMITX_DWC_FC_RDRB3 (DWC_OFFSET_MASK + 0x10BB)
-#define HDMITX_DWC_FC_RDRB4 (DWC_OFFSET_MASK + 0x10BC)
-#define HDMITX_DWC_FC_RDRB5 (DWC_OFFSET_MASK + 0x10BD)
-#define HDMITX_DWC_FC_RDRB6 (DWC_OFFSET_MASK + 0x10BE)
-#define HDMITX_DWC_FC_RDRB7 (DWC_OFFSET_MASK + 0x10BF)
-#define HDMITX_DWC_FC_RDRB8 (DWC_OFFSET_MASK + 0x10C0)
-#define HDMITX_DWC_FC_RDRB9 (DWC_OFFSET_MASK + 0x10C1)
-#define HDMITX_DWC_FC_RDRB10 (DWC_OFFSET_MASK + 0x10C2)
-#define HDMITX_DWC_FC_RDRB11 (DWC_OFFSET_MASK + 0x10C3)
-/* [ 7] AUDI_int_mask */
-/* [ 6] ACP_int_mask */
-/* [ 5] HBR_int_mask */
-/* [ 2] AUDS_int_mask */
-/* [ 1] ACR_int_mask */
-/* [ 0] NULL_int_mask */
-#define HDMITX_DWC_FC_MASK0 (DWC_OFFSET_MASK + 0x10D2)
-/* [ 7] GMD_int_mask */
-/* [ 6] ISRC1_int_mask */
-/* [ 5] ISRC2_int_mask */
-/* [ 4] VSD_int_mask */
-/* [ 3] SPD_int_mask */
-/* [ 1] AVI_int_mask */
-/* [ 0] GCP_int_mask */
-#define HDMITX_DWC_FC_MASK1 (DWC_OFFSET_MASK + 0x10D6)
-/* [ 1] LowPriority_fifo_full */
-/* [ 0] HighPriority_fifo_full */
-#define HDMITX_DWC_FC_MASK2 (DWC_OFFSET_MASK + 0x10DA)
-/* [7:4] incoming_pr_factor */
-/* [3:0] output_pr_factor */
-#define HDMITX_DWC_FC_PRCONF (DWC_OFFSET_MASK + 0x10E0)
-/* [ 4] scrambler_ucp_line */
-/* [ 0] scrambler_en. Only update this bit once we've sent SCDC message*/
-#define HDMITX_DWC_FC_SCRAMBLER_CTRL (DWC_OFFSET_MASK + 0x10E1)
-#define HDMITX_DWC_FC_MULTISTREAM_CTRL (DWC_OFFSET_MASK + 0x10E2)
-/* [ 6] nvbi_tx_en */
-/* [ 5] amp_tx_en */
-/* [ 4] aut_tx_en */
-/* [ 3] audi_tx_en */
-/* [ 2] avi_tx_en */
-/* [ 1] gcp_tx_en */
-/* [ 0] acr_tx_en */
-#define HDMITX_DWC_FC_PACKET_TX_EN (DWC_OFFSET_MASK + 0x10E3)
-/* [ 1] actspc_hdlr_tgl */
-/* [ 0] actspc_hdlr_en */
-#define HDMITX_DWC_FC_ACTSPC_HDLR_CFG (DWC_OFFSET_MASK + 0x10E8)
-#define HDMITX_DWC_FC_INVACT_2D_0 (DWC_OFFSET_MASK + 0x10E9)
-/* [3:0] fc_invact_2d_0[11:8] */
-/* [7:0] fc_invact_2d_0[7:0] */
-#define HDMITX_DWC_FC_INVACT_2D_1 (DWC_OFFSET_MASK + 0x10EA)
-
-#define HDMITX_DWC_FC_GMD_STAT (DWC_OFFSET_MASK + 0x1100)
-#define HDMITX_DWC_FC_GMD_EN (DWC_OFFSET_MASK + 0x1101)
-#define HDMITX_DWC_FC_GMD_UP (DWC_OFFSET_MASK + 0x1102)
-#define HDMITX_DWC_FC_GMD_CONF (DWC_OFFSET_MASK + 0x1103)
-#define HDMITX_DWC_FC_GMD_HB (DWC_OFFSET_MASK + 0x1104)
-#define HDMITX_DWC_FC_GMD_PB0 (DWC_OFFSET_MASK + 0x1105)
-#define HDMITX_DWC_FC_GMD_PB1 (DWC_OFFSET_MASK + 0x1106)
-#define HDMITX_DWC_FC_GMD_PB2 (DWC_OFFSET_MASK + 0x1107)
-#define HDMITX_DWC_FC_GMD_PB3 (DWC_OFFSET_MASK + 0x1108)
-#define HDMITX_DWC_FC_GMD_PB4 (DWC_OFFSET_MASK + 0x1109)
-#define HDMITX_DWC_FC_GMD_PB5 (DWC_OFFSET_MASK + 0x110A)
-#define HDMITX_DWC_FC_GMD_PB6 (DWC_OFFSET_MASK + 0x110B)
-#define HDMITX_DWC_FC_GMD_PB7 (DWC_OFFSET_MASK + 0x110C)
-#define HDMITX_DWC_FC_GMD_PB8 (DWC_OFFSET_MASK + 0x110D)
-#define HDMITX_DWC_FC_GMD_PB9 (DWC_OFFSET_MASK + 0x110E)
-#define HDMITX_DWC_FC_GMD_PB10 (DWC_OFFSET_MASK + 0x110F)
-#define HDMITX_DWC_FC_GMD_PB11 (DWC_OFFSET_MASK + 0x1110)
-#define HDMITX_DWC_FC_GMD_PB12 (DWC_OFFSET_MASK + 0x1111)
-#define HDMITX_DWC_FC_GMD_PB13 (DWC_OFFSET_MASK + 0x1112)
-#define HDMITX_DWC_FC_GMD_PB14 (DWC_OFFSET_MASK + 0x1113)
-#define HDMITX_DWC_FC_GMD_PB15 (DWC_OFFSET_MASK + 0x1114)
-#define HDMITX_DWC_FC_GMD_PB16 (DWC_OFFSET_MASK + 0x1115)
-#define HDMITX_DWC_FC_GMD_PB17 (DWC_OFFSET_MASK + 0x1116)
-#define HDMITX_DWC_FC_GMD_PB18 (DWC_OFFSET_MASK + 0x1117)
-#define HDMITX_DWC_FC_GMD_PB19 (DWC_OFFSET_MASK + 0x1118)
-#define HDMITX_DWC_FC_GMD_PB20 (DWC_OFFSET_MASK + 0x1119)
-#define HDMITX_DWC_FC_GMD_PB21 (DWC_OFFSET_MASK + 0x111A)
-#define HDMITX_DWC_FC_GMD_PB22 (DWC_OFFSET_MASK + 0x111B)
-#define HDMITX_DWC_FC_GMD_PB23 (DWC_OFFSET_MASK + 0x111C)
-#define HDMITX_DWC_FC_GMD_PB24 (DWC_OFFSET_MASK + 0x111D)
-#define HDMITX_DWC_FC_GMD_PB25 (DWC_OFFSET_MASK + 0x111E)
-#define HDMITX_DWC_FC_GMD_PB26 (DWC_OFFSET_MASK + 0x111F)
-#define HDMITX_DWC_FC_GMD_PB27 (DWC_OFFSET_MASK + 0x1120)
-
-/* Audio Metadata Packet Registers */
-#define HDMITX_DWC_FC_AMP_HB01 (DWC_OFFSET_MASK + 0x1128)
-#define HDMITX_DWC_FC_AMP_HB02 (DWC_OFFSET_MASK + 0x1129)
-#define HDMITX_DWC_FC_AMP_PB00 (DWC_OFFSET_MASK + 0x112A)
-#define HDMITX_DWC_FC_AMP_PB01 (DWC_OFFSET_MASK + 0x112B)
-#define HDMITX_DWC_FC_AMP_PB02 (DWC_OFFSET_MASK + 0x112C)
-#define HDMITX_DWC_FC_AMP_PB03 (DWC_OFFSET_MASK + 0x112D)
-#define HDMITX_DWC_FC_AMP_PB04 (DWC_OFFSET_MASK + 0x112E)
-#define HDMITX_DWC_FC_AMP_PB05 (DWC_OFFSET_MASK + 0x112F)
-#define HDMITX_DWC_FC_AMP_PB06 (DWC_OFFSET_MASK + 0x1130)
-#define HDMITX_DWC_FC_AMP_PB07 (DWC_OFFSET_MASK + 0x1131)
-#define HDMITX_DWC_FC_AMP_PB08 (DWC_OFFSET_MASK + 0x1132)
-#define HDMITX_DWC_FC_AMP_PB09 (DWC_OFFSET_MASK + 0x1133)
-#define HDMITX_DWC_FC_AMP_PB10 (DWC_OFFSET_MASK + 0x1134)
-#define HDMITX_DWC_FC_AMP_PB11 (DWC_OFFSET_MASK + 0x1135)
-#define HDMITX_DWC_FC_AMP_PB12 (DWC_OFFSET_MASK + 0x1136)
-#define HDMITX_DWC_FC_AMP_PB13 (DWC_OFFSET_MASK + 0x1137)
-#define HDMITX_DWC_FC_AMP_PB14 (DWC_OFFSET_MASK + 0x1138)
-#define HDMITX_DWC_FC_AMP_PB15 (DWC_OFFSET_MASK + 0x1139)
-#define HDMITX_DWC_FC_AMP_PB16 (DWC_OFFSET_MASK + 0x113A)
-#define HDMITX_DWC_FC_AMP_PB17 (DWC_OFFSET_MASK + 0x113B)
-#define HDMITX_DWC_FC_AMP_PB18 (DWC_OFFSET_MASK + 0x113C)
-#define HDMITX_DWC_FC_AMP_PB19 (DWC_OFFSET_MASK + 0x113D)
-#define HDMITX_DWC_FC_AMP_PB20 (DWC_OFFSET_MASK + 0x113E)
-#define HDMITX_DWC_FC_AMP_PB21 (DWC_OFFSET_MASK + 0x113F)
-#define HDMITX_DWC_FC_AMP_PB22 (DWC_OFFSET_MASK + 0x1140)
-#define HDMITX_DWC_FC_AMP_PB23 (DWC_OFFSET_MASK + 0x1141)
-#define HDMITX_DWC_FC_AMP_PB24 (DWC_OFFSET_MASK + 0x1142)
-#define HDMITX_DWC_FC_AMP_PB25 (DWC_OFFSET_MASK + 0x1143)
-#define HDMITX_DWC_FC_AMP_PB26 (DWC_OFFSET_MASK + 0x1144)
-#define HDMITX_DWC_FC_AMP_PB27 (DWC_OFFSET_MASK + 0x1145)
-
-/* NTSC VBI Packet Registers */
-#define HDMITX_DWC_FC_NVBI_HB01 (DWC_OFFSET_MASK + 0x1148)
-#define HDMITX_DWC_FC_NVBI_HB02 (DWC_OFFSET_MASK + 0x1149)
-#define HDMITX_DWC_FC_NVBI_PB01 (DWC_OFFSET_MASK + 0x114A)
-#define HDMITX_DWC_FC_NVBI_PB02 (DWC_OFFSET_MASK + 0x114B)
-#define HDMITX_DWC_FC_NVBI_PB03 (DWC_OFFSET_MASK + 0x114C)
-#define HDMITX_DWC_FC_NVBI_PB04 (DWC_OFFSET_MASK + 0x114D)
-#define HDMITX_DWC_FC_NVBI_PB05 (DWC_OFFSET_MASK + 0x114E)
-#define HDMITX_DWC_FC_NVBI_PB06 (DWC_OFFSET_MASK + 0x114F)
-#define HDMITX_DWC_FC_NVBI_PB07 (DWC_OFFSET_MASK + 0x1150)
-#define HDMITX_DWC_FC_NVBI_PB08 (DWC_OFFSET_MASK + 0x1151)
-#define HDMITX_DWC_FC_NVBI_PB09 (DWC_OFFSET_MASK + 0x1152)
-#define HDMITX_DWC_FC_NVBI_PB10 (DWC_OFFSET_MASK + 0x1153)
-#define HDMITX_DWC_FC_NVBI_PB11 (DWC_OFFSET_MASK + 0x1154)
-#define HDMITX_DWC_FC_NVBI_PB12 (DWC_OFFSET_MASK + 0x1155)
-#define HDMITX_DWC_FC_NVBI_PB13 (DWC_OFFSET_MASK + 0x1156)
-#define HDMITX_DWC_FC_NVBI_PB14 (DWC_OFFSET_MASK + 0x1157)
-#define HDMITX_DWC_FC_NVBI_PB15 (DWC_OFFSET_MASK + 0x1158)
-#define HDMITX_DWC_FC_NVBI_PB16 (DWC_OFFSET_MASK + 0x1159)
-#define HDMITX_DWC_FC_NVBI_PB17 (DWC_OFFSET_MASK + 0x115A)
-#define HDMITX_DWC_FC_NVBI_PB18 (DWC_OFFSET_MASK + 0x115B)
-#define HDMITX_DWC_FC_NVBI_PB19 (DWC_OFFSET_MASK + 0x115C)
-#define HDMITX_DWC_FC_NVBI_PB20 (DWC_OFFSET_MASK + 0x115D)
-#define HDMITX_DWC_FC_NVBI_PB21 (DWC_OFFSET_MASK + 0x115E)
-#define HDMITX_DWC_FC_NVBI_PB22 (DWC_OFFSET_MASK + 0x115F)
-#define HDMITX_DWC_FC_NVBI_PB23 (DWC_OFFSET_MASK + 0x1160)
-#define HDMITX_DWC_FC_NVBI_PB24 (DWC_OFFSET_MASK + 0x1161)
-#define HDMITX_DWC_FC_NVBI_PB25 (DWC_OFFSET_MASK + 0x1162)
-#define HDMITX_DWC_FC_NVBI_PB26 (DWC_OFFSET_MASK + 0x1163)
-#define HDMITX_DWC_FC_NVBI_PB27 (DWC_OFFSET_MASK + 0x1164)
-
-#define HDMITX_DWC_FC_DBGFORCE (DWC_OFFSET_MASK + 0x1200)
-#define HDMITX_DWC_FC_DBGAUD0CH0 (DWC_OFFSET_MASK + 0x1201)
-#define HDMITX_DWC_FC_DBGAUD1CH0 (DWC_OFFSET_MASK + 0x1202)
-#define HDMITX_DWC_FC_DBGAUD2CH0 (DWC_OFFSET_MASK + 0x1203)
-#define HDMITX_DWC_FC_DBGAUD0CH1 (DWC_OFFSET_MASK + 0x1204)
-#define HDMITX_DWC_FC_DBGAUD1CH1 (DWC_OFFSET_MASK + 0x1205)
-#define HDMITX_DWC_FC_DBGAUD2CH1 (DWC_OFFSET_MASK + 0x1206)
-#define HDMITX_DWC_FC_DBGAUD0CH2 (DWC_OFFSET_MASK + 0x1207)
-#define HDMITX_DWC_FC_DBGAUD1CH2 (DWC_OFFSET_MASK + 0x1208)
-#define HDMITX_DWC_FC_DBGAUD2CH2 (DWC_OFFSET_MASK + 0x1209)
-#define HDMITX_DWC_FC_DBGAUD0CH3 (DWC_OFFSET_MASK + 0x120A)
-#define HDMITX_DWC_FC_DBGAUD1CH3 (DWC_OFFSET_MASK + 0x120B)
-#define HDMITX_DWC_FC_DBGAUD2CH3 (DWC_OFFSET_MASK + 0x120C)
-#define HDMITX_DWC_FC_DBGAUD0CH4 (DWC_OFFSET_MASK + 0x120D)
-#define HDMITX_DWC_FC_DBGAUD1CH4 (DWC_OFFSET_MASK + 0x120E)
-#define HDMITX_DWC_FC_DBGAUD2CH4 (DWC_OFFSET_MASK + 0x120F)
-#define HDMITX_DWC_FC_DBGAUD0CH5 (DWC_OFFSET_MASK + 0x1210)
-#define HDMITX_DWC_FC_DBGAUD1CH5 (DWC_OFFSET_MASK + 0x1211)
-#define HDMITX_DWC_FC_DBGAUD2CH5 (DWC_OFFSET_MASK + 0x1212)
-#define HDMITX_DWC_FC_DBGAUD0CH6 (DWC_OFFSET_MASK + 0x1213)
-#define HDMITX_DWC_FC_DBGAUD1CH6 (DWC_OFFSET_MASK + 0x1214)
-#define HDMITX_DWC_FC_DBGAUD2CH6 (DWC_OFFSET_MASK + 0x1215)
-#define HDMITX_DWC_FC_DBGAUD0CH7 (DWC_OFFSET_MASK + 0x1216)
-#define HDMITX_DWC_FC_DBGAUD1CH7 (DWC_OFFSET_MASK + 0x1217)
-#define HDMITX_DWC_FC_DBGAUD2CH7 (DWC_OFFSET_MASK + 0x1218)
-#define HDMITX_DWC_FC_DBGTMDS0 (DWC_OFFSET_MASK + 0x1219)
-#define HDMITX_DWC_FC_DBGTMDS1 (DWC_OFFSET_MASK + 0x121A)
-#define HDMITX_DWC_FC_DBGTMDS2 (DWC_OFFSET_MASK + 0x121B)
-
-/* HDMI Source PHY Registers */
-#define HDMITX_DWC_PHY_CONF0 (DWC_OFFSET_MASK + 0x3000)
-#define HDMITX_DWC_PHY_TST0 (DWC_OFFSET_MASK + 0x3001)
-#define HDMITX_DWC_PHY_TST1 (DWC_OFFSET_MASK + 0x3002)
-#define HDMITX_DWC_PHY_TST2 (DWC_OFFSET_MASK + 0x3003)
-#define HDMITX_DWC_PHY_STAT0 (DWC_OFFSET_MASK + 0x3004)
-#define HDMITX_DWC_PHY_INT0 (DWC_OFFSET_MASK + 0x3005)
-#define HDMITX_DWC_PHY_MASK0 (DWC_OFFSET_MASK + 0x3006)
-#define HDMITX_DWC_PHY_POL0 (DWC_OFFSET_MASK + 0x3007)
-
-/* I2C Master PHY Registers */
-#define HDMITX_DWC_I2CM_PHY_SLAVE (DWC_OFFSET_MASK + 0x3020)
-#define HDMITX_DWC_I2CM_PHY_ADDRESS (DWC_OFFSET_MASK + 0x3021)
-#define HDMITX_DWC_I2CM_PHY_DATAO_1 (DWC_OFFSET_MASK + 0x3022)
-#define HDMITX_DWC_I2CM_PHY_DATAO_0 (DWC_OFFSET_MASK + 0x3023)
-#define HDMITX_DWC_I2CM_PHY_DATAI_1 (DWC_OFFSET_MASK + 0x3024)
-#define HDMITX_DWC_I2CM_PHY_DATAI_0 (DWC_OFFSET_MASK + 0x3025)
-#define HDMITX_DWC_I2CM_PHY_OPERATION (DWC_OFFSET_MASK + 0x3026)
-#define HDMITX_DWC_I2CM_PHY_INT (DWC_OFFSET_MASK + 0x3027)
-#define HDMITX_DWC_I2CM_PHY_CTLINT (DWC_OFFSET_MASK + 0x3028)
-#define HDMITX_DWC_I2CM_PHY_DIV (DWC_OFFSET_MASK + 0x3029)
-#define HDMITX_DWC_I2CM_PHY_SOFTRSTZ (DWC_OFFSET_MASK + 0x302A)
-#define HDMITX_DWC_I2CM_PHY_SS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x302B)
-#define HDMITX_DWC_I2CM_PHY_SS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x302C)
-#define HDMITX_DWC_I2CM_PHY_SS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x302D)
-#define HDMITX_DWC_I2CM_PHY_SS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x302E)
-#define HDMITX_DWC_I2CM_PHY_FS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x302F)
-#define HDMITX_DWC_I2CM_PHY_FS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x3030)
-#define HDMITX_DWC_I2CM_PHY_FS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x3031)
-#define HDMITX_DWC_I2CM_PHY_FS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x3032)
-#define HDMITX_DWC_I2CM_PHY_SDA_HOLD (DWC_OFFSET_MASK + 0x3033)
-
-/* Audio Sampler Registers */
-
- /* [ 7] sw_audio_fifo_rst */
- /* [ 5] 0=select SPDIF; 1=select I2S. */
- /* [3:0] i2s_in_en: enable it later in test.c */
-
-#define HDMITX_DWC_AUD_CONF0 (DWC_OFFSET_MASK + 0x3100)
-/* [4:0] i2s_width */
-/* [7:5] i2s_mode: 0=standard I2S mode */
-#define HDMITX_DWC_AUD_CONF1 (DWC_OFFSET_MASK + 0x3101)
-/* [ 3] fifo_empty_mask: 0=enable int; 1=mask int. */
-/* [ 2] fifo_full_mask: 0=enable int; 1=mask int. */
-#define HDMITX_DWC_AUD_INT (DWC_OFFSET_MASK + 0x3102)
- /* [ 1] NLPCM */
-#define HDMITX_DWC_AUD_CONF2 (DWC_OFFSET_MASK + 0x3103)
-
-/* [ 4] fifo_overrun_mask: 0=enable int; 1=mask int.
- * Enable it later when audio starts.
- */
-#define HDMITX_DWC_AUD_INT1 (DWC_OFFSET_MASK + 0x3104)
-
-#define HDMITX_DWC_AUD_N1 (DWC_OFFSET_MASK + 0x3200)
-#define HDMITX_DWC_AUD_N2 (DWC_OFFSET_MASK + 0x3201)
-#define HDMITX_DWC_AUD_N3 (DWC_OFFSET_MASK + 0x3202)
-#define HDMITX_DWC_AUD_CTS1 (DWC_OFFSET_MASK + 0x3203)
-#define HDMITX_DWC_AUD_CTS2 (DWC_OFFSET_MASK + 0x3204)
-#define HDMITX_DWC_AUD_CTS3 (DWC_OFFSET_MASK + 0x3205)
-#define HDMITX_DWC_AUD_INPUTCLKFS (DWC_OFFSET_MASK + 0x3206)
-/* [ 7] sw_audio_fifo_rst */
-#define HDMITX_DWC_AUD_SPDIF0 (DWC_OFFSET_MASK + 0x3300)
-/* [4:0] spdif_width */
-/* [ 7] setnlpcm */
-#define HDMITX_DWC_AUD_SPDIF1 (DWC_OFFSET_MASK + 0x3301)
-/* [ 3] SPDIF fifo_empty_mask: 0=enable int; 1=mask int. */
-/* [ 2] SPDIF fifo_full_mask: 0=enable int; 1=mask int. */
-#define HDMITX_DWC_AUD_SPDIFINT (DWC_OFFSET_MASK + 0x3302)
-/* [ 4] SPDIF fifo_overrun_mask: 0=enable int; 1=mask int. */
-#define HDMITX_DWC_AUD_SPDIFINT1 (DWC_OFFSET_MASK + 0x3303)
-
-/* Generic Parallel Audio Interface Registers (DWC_OFFSET_MASK + 0x3500) */
-/* Audio DMA Registers (DWC_OFFSET_MASK + 0x3600) */
-
-/* Main Controller Registers */
-/* [ 6] hdcpclk_disable */
-/* [ 5] cecclk_disable */
-/* [ 4] cscclk_disable */
-/* [ 3] audclk_disable */
-/* [ 2] prepclk_disable */
-/* [ 1] tmdsclk_disable */
-/* [ 0] pixelclk_disable */
-#define HDMITX_DWC_MC_CLKDIS (DWC_OFFSET_MASK + 0x4001)
-/*
- * [ 7] gpaswrst_req: 0=generate reset pulse; 1=no reset.
- * [ 6] cecswrst_req: 0=generate reset pulse; 1=no reset.
- * [ 4] spdifswrst_req: 0=generate reset pulse; 1=no reset.
- * [ 3] i2sswrst_req: 0=generate reset pulse; 1=no reset.
- * [ 2] prepswrst_req: 0=generate reset pulse; 1=no reset.
- * [ 1] tmdsswrst_req: 0=generate reset pulse; 1=no reset.
- * [ 0] pixelswrst_req: 0=generate reset pulse; 1=no reset.
- */
-#define HDMITX_DWC_MC_SWRSTZREQ (DWC_OFFSET_MASK + 0x4002)
-#define HDMITX_DWC_MC_OPCTRL (DWC_OFFSET_MASK + 0x4003)
-/* [ 0] CSC enable */
-#define HDMITX_DWC_MC_FLOWCTRL (DWC_OFFSET_MASK + 0x4004)
-#define HDMITX_DWC_MC_PHYRSTZ (DWC_OFFSET_MASK + 0x4005)
-#define HDMITX_DWC_MC_LOCKONCLOCK (DWC_OFFSET_MASK + 0x4006)
-
-/* Color Space Converter Registers */
-/* [ 7] csc_limit */
-#define HDMITX_DWC_CSC_CFG (DWC_OFFSET_MASK + 0x4100)
-#define HDMITX_DWC_CSC_SCALE (DWC_OFFSET_MASK + 0x4101)
-#define HDMITX_DWC_CSC_COEF_A1_MSB (DWC_OFFSET_MASK + 0x4102)
-#define HDMITX_DWC_CSC_COEF_A1_LSB (DWC_OFFSET_MASK + 0x4103)
-#define HDMITX_DWC_CSC_COEF_A2_MSB (DWC_OFFSET_MASK + 0x4104)
-#define HDMITX_DWC_CSC_COEF_A2_LSB (DWC_OFFSET_MASK + 0x4105)
-#define HDMITX_DWC_CSC_COEF_A3_MSB (DWC_OFFSET_MASK + 0x4106)
-#define HDMITX_DWC_CSC_COEF_A3_LSB (DWC_OFFSET_MASK + 0x4107)
-#define HDMITX_DWC_CSC_COEF_A4_MSB (DWC_OFFSET_MASK + 0x4108)
-#define HDMITX_DWC_CSC_COEF_A4_LSB (DWC_OFFSET_MASK + 0x4109)
-#define HDMITX_DWC_CSC_COEF_B1_MSB (DWC_OFFSET_MASK + 0x410A)
-#define HDMITX_DWC_CSC_COEF_B1_LSB (DWC_OFFSET_MASK + 0x410B)
-#define HDMITX_DWC_CSC_COEF_B2_MSB (DWC_OFFSET_MASK + 0x410C)
-#define HDMITX_DWC_CSC_COEF_B2_LSB (DWC_OFFSET_MASK + 0x410D)
-#define HDMITX_DWC_CSC_COEF_B3_MSB (DWC_OFFSET_MASK + 0x410E)
-#define HDMITX_DWC_CSC_COEF_B3_LSB (DWC_OFFSET_MASK + 0x410F)
-#define HDMITX_DWC_CSC_COEF_B4_MSB (DWC_OFFSET_MASK + 0x4110)
-#define HDMITX_DWC_CSC_COEF_B4_LSB (DWC_OFFSET_MASK + 0x4111)
-#define HDMITX_DWC_CSC_COEF_C1_MSB (DWC_OFFSET_MASK + 0x4112)
-#define HDMITX_DWC_CSC_COEF_C1_LSB (DWC_OFFSET_MASK + 0x4113)
-#define HDMITX_DWC_CSC_COEF_C2_MSB (DWC_OFFSET_MASK + 0x4114)
-#define HDMITX_DWC_CSC_COEF_C2_LSB (DWC_OFFSET_MASK + 0x4115)
-#define HDMITX_DWC_CSC_COEF_C3_MSB (DWC_OFFSET_MASK + 0x4116)
-#define HDMITX_DWC_CSC_COEF_C3_LSB (DWC_OFFSET_MASK + 0x4117)
-#define HDMITX_DWC_CSC_COEF_C4_MSB (DWC_OFFSET_MASK + 0x4118)
-#define HDMITX_DWC_CSC_COEF_C4_LSB (DWC_OFFSET_MASK + 0x4119)
-#define HDMITX_DWC_CSC_LIMIT_UP_MSB (DWC_OFFSET_MASK + 0x411A)
-#define HDMITX_DWC_CSC_LIMIT_UP_LSB (DWC_OFFSET_MASK + 0x411B)
-#define HDMITX_DWC_CSC_LIMIT_DN_MSB (DWC_OFFSET_MASK + 0x411C)
-#define HDMITX_DWC_CSC_LIMIT_DN_LSB (DWC_OFFSET_MASK + 0x411D)
-
-/* HDCP Encryption Engine Registers */
-#define HDMITX_DWC_A_HDCPCFG0 (DWC_SEC_OFFSET_MASK + 0x5000)
-/* [ 4] hdcp_lock */
-/* [ 3] dissha1check */
-/* [ 2] ph2upshiftenc */
-/* [ 1] encryptiondisable */
-/* [ 0] swresetn. Write 0 to activate, self-clear to 1. */
-#define HDMITX_DWC_A_HDCPCFG1 (DWC_SEC_OFFSET_MASK + 0x5001)
-#define HDMITX_DWC_A_HDCPOBS0 (DWC_OFFSET_MASK + 0x5002)
-#define HDMITX_DWC_A_HDCPOBS1 (DWC_OFFSET_MASK + 0x5003)
-#define HDMITX_DWC_A_HDCPOBS2 (DWC_OFFSET_MASK + 0x5004)
-#define HDMITX_DWC_A_HDCPOBS3 (DWC_OFFSET_MASK + 0x5005)
-#define HDMITX_DWC_A_APIINTCLR (DWC_OFFSET_MASK + 0x5006)
-#define HDMITX_DWC_A_APIINTSTAT (DWC_OFFSET_MASK + 0x5007)
-/* [ 7] hdcp_engaged_int_mask */
-/* [ 6] hdcp_failed_int_mask */
-/* [ 4] i2c_nack_int_mask */
-/* [ 3] lost_arbitration_int_mask */
-/* [ 2] keepout_error_int_mask */
-/* [ 1] ksv_sha1_calc_int_mask */
-/* [ 0] ksv_access_int_mask */
-#define HDMITX_DWC_A_APIINTMSK (DWC_OFFSET_MASK + 0x5008)
-/* [6:5] unencryptconf */
-/* [ 4] dataenpol */
-/* [ 3] vsyncpol */
-/* [ 1] hsyncpol */
-#define HDMITX_DWC_A_VIDPOLCFG (DWC_OFFSET_MASK + 0x5009)
-#define HDMITX_DWC_A_OESSWCFG (DWC_OFFSET_MASK + 0x500A)
-#define HDMITX_DWC_A_COREVERLSB (DWC_OFFSET_MASK + 0x5014)
-#define HDMITX_DWC_A_COREVERMSB (DWC_OFFSET_MASK + 0x5015)
-/* [ 3] sha1_fail */
-/* [ 2] ksv_ctrl_update */
-/* [ 1] Rsvd for read-only ksv_mem_access */
-/* [ 0] ksv_mem_request */
-#define HDMITX_DWC_A_KSVMEMCTRL (DWC_OFFSET_MASK + 0x5016)
-#define HDMITX_DWC_HDCP_BSTATUS_0 (TOP_OFFSET_MASK + 0x2000)
-#define HDMITX_DWC_HDCP_BSTATUS_1 (TOP_OFFSET_MASK + 0x2001)
-#define HDMITX_DWC_HDCP_M0_0 (TOP_OFFSET_MASK + 0x2002)
-#define HDMITX_DWC_HDCP_M0_1 (TOP_OFFSET_MASK + 0x2003)
-#define HDMITX_DWC_HDCP_M0_2 (TOP_OFFSET_MASK + 0x2004)
-#define HDMITX_DWC_HDCP_M0_3 (TOP_OFFSET_MASK + 0x2005)
-#define HDMITX_DWC_HDCP_M0_4 (TOP_OFFSET_MASK + 0x2006)
-#define HDMITX_DWC_HDCP_M0_5 (TOP_OFFSET_MASK + 0x2007)
-#define HDMITX_DWC_HDCP_M0_6 (TOP_OFFSET_MASK + 0x2008)
-#define HDMITX_DWC_HDCP_M0_7 (TOP_OFFSET_MASK + 0x2009)
-#define HDMITX_DWC_HDCP_KSV (TOP_OFFSET_MASK + 0x200A)
-#define HDMITX_DWC_HDCP_VH (TOP_OFFSET_MASK + 0x2285)
-#define HDMITX_DWC_HDCP_REVOC_SIZE_0 (TOP_OFFSET_MASK + 0x2299)
-#define HDMITX_DWC_HDCP_REVOC_SIZE_1 (TOP_OFFSET_MASK + 0x229A)
-#define HDMITX_DWC_HDCP_REVOC_LIST (TOP_OFFSET_MASK + 0x229B)
-#define HDMITX_DWC_HDCP_REVOC_LIST_END (TOP_OFFSET_MASK + 0x365E)
-
-
-/* HDCP BKSV Registers */
-#define HDMITX_DWC_HDCPREG_BKSV0 (DWC_OFFSET_MASK + 0x7800)
-#define HDMITX_DWC_HDCPREG_BKSV1 (DWC_OFFSET_MASK + 0x7801)
-#define HDMITX_DWC_HDCPREG_BKSV2 (DWC_OFFSET_MASK + 0x7802)
-#define HDMITX_DWC_HDCPREG_BKSV3 (DWC_OFFSET_MASK + 0x7803)
-#define HDMITX_DWC_HDCPREG_BKSV4 (DWC_OFFSET_MASK + 0x7804)
-
-/* HDCP AN Registers */
-#define HDMITX_DWC_HDCPREG_ANCONF (DWC_OFFSET_MASK + 0x7805)
-#define HDMITX_DWC_HDCPREG_AN0 (DWC_OFFSET_MASK + 0x7806)
-#define HDMITX_DWC_HDCPREG_AN1 (DWC_OFFSET_MASK + 0x7807)
-#define HDMITX_DWC_HDCPREG_AN2 (DWC_OFFSET_MASK + 0x7808)
-#define HDMITX_DWC_HDCPREG_AN3 (DWC_OFFSET_MASK + 0x7809)
-#define HDMITX_DWC_HDCPREG_AN4 (DWC_OFFSET_MASK + 0x780A)
-#define HDMITX_DWC_HDCPREG_AN5 (DWC_OFFSET_MASK + 0x780B)
-#define HDMITX_DWC_HDCPREG_AN6 (DWC_OFFSET_MASK + 0x780C)
-#define HDMITX_DWC_HDCPREG_AN7 (DWC_OFFSET_MASK + 0x780D)
-#define HDMITX_DWC_HDCPREG_RMLCTL (DWC_OFFSET_MASK + 0x780E)
-
-/* Encrypted DPK Embedded Storage Registers */
-#define HDMITX_DWC_HDCPREG_RMLSTS (DWC_OFFSET_MASK + 0x780F)
-#define HDMITX_DWC_HDCPREG_SEED0 (DWC_SEC_OFFSET_MASK + 0x7810)
-#define HDMITX_DWC_HDCPREG_SEED1 (DWC_SEC_OFFSET_MASK + 0x7811)
-#define HDMITX_DWC_HDCPREG_DPK0 (DWC_SEC_OFFSET_MASK + 0x7812)
-#define HDMITX_DWC_HDCPREG_DPK1 (DWC_SEC_OFFSET_MASK + 0x7813)
-#define HDMITX_DWC_HDCPREG_DPK2 (DWC_SEC_OFFSET_MASK + 0x7814)
-#define HDMITX_DWC_HDCPREG_DPK3 (DWC_SEC_OFFSET_MASK + 0x7815)
-#define HDMITX_DWC_HDCPREG_DPK4 (DWC_SEC_OFFSET_MASK + 0x7816)
-#define HDMITX_DWC_HDCPREG_DPK5 (DWC_SEC_OFFSET_MASK + 0x7817)
-#define HDMITX_DWC_HDCPREG_DPK6 (DWC_SEC_OFFSET_MASK + 0x7818)
-
-/* HDCP22 Registers */
-#define HDMITX_DWC_HDCP22REG_ID (DWC_OFFSET_MASK + 0x7900)
-#define HDMITX_DWC_HDCP22REG_CTRL (DWC_SEC_OFFSET_MASK + 0x7904)
-#define HDMITX_DWC_HDCP22REG_CTRL1 (DWC_OFFSET_MASK + 0x7905)
-#define HDMITX_DWC_HDCP22REG_STS (DWC_OFFSET_MASK + 0x7908)
-#define HDMITX_DWC_HDCP22REG_MASK (DWC_OFFSET_MASK + 0x790C)
-#define HDMITX_DWC_HDCP22REG_STAT (DWC_OFFSET_MASK + 0x790D)
-#define HDMITX_DWC_HDCP22REG_MUTE (DWC_OFFSET_MASK + 0x790E)
-
-
-/* ********** CEC related ********** */
-
-/* CEC 2.0 Engine Registers */
-#define HDMITX_DWC_CEC_CTRL (DWC_OFFSET_MASK + 0x7D00)
-#define HDMITX_DWC_CEC_INTR_MASK (DWC_OFFSET_MASK + 0x7D02)
-#define HDMITX_DWC_CEC_LADD_LOW (DWC_OFFSET_MASK + 0x7D05)
-#define HDMITX_DWC_CEC_LADD_HIGH (DWC_OFFSET_MASK + 0x7D06)
-#define HDMITX_DWC_CEC_TX_CNT (DWC_OFFSET_MASK + 0x7D07)
-#define HDMITX_DWC_CEC_RX_CNT (DWC_OFFSET_MASK + 0x7D08)
-#define HDMITX_DWC_CEC_TX_DATA00 (DWC_OFFSET_MASK + 0x7D10)
-#define HDMITX_DWC_CEC_TX_DATA01 (DWC_OFFSET_MASK + 0x7D11)
-#define HDMITX_DWC_CEC_TX_DATA02 (DWC_OFFSET_MASK + 0x7D12)
-#define HDMITX_DWC_CEC_TX_DATA03 (DWC_OFFSET_MASK + 0x7D13)
-#define HDMITX_DWC_CEC_TX_DATA04 (DWC_OFFSET_MASK + 0x7D14)
-#define HDMITX_DWC_CEC_TX_DATA05 (DWC_OFFSET_MASK + 0x7D15)
-#define HDMITX_DWC_CEC_TX_DATA06 (DWC_OFFSET_MASK + 0x7D16)
-#define HDMITX_DWC_CEC_TX_DATA07 (DWC_OFFSET_MASK + 0x7D17)
-#define HDMITX_DWC_CEC_TX_DATA08 (DWC_OFFSET_MASK + 0x7D18)
-#define HDMITX_DWC_CEC_TX_DATA09 (DWC_OFFSET_MASK + 0x7D19)
-#define HDMITX_DWC_CEC_TX_DATA10 (DWC_OFFSET_MASK + 0x7D1A)
-#define HDMITX_DWC_CEC_TX_DATA11 (DWC_OFFSET_MASK + 0x7D1B)
-#define HDMITX_DWC_CEC_TX_DATA12 (DWC_OFFSET_MASK + 0x7D1C)
-#define HDMITX_DWC_CEC_TX_DATA13 (DWC_OFFSET_MASK + 0x7D1D)
-#define HDMITX_DWC_CEC_TX_DATA14 (DWC_OFFSET_MASK + 0x7D1E)
-#define HDMITX_DWC_CEC_TX_DATA15 (DWC_OFFSET_MASK + 0x7D1F)
-#define HDMITX_DWC_CEC_RX_DATA00 (DWC_OFFSET_MASK + 0x7D20)
-#define HDMITX_DWC_CEC_RX_DATA01 (DWC_OFFSET_MASK + 0x7D21)
-#define HDMITX_DWC_CEC_RX_DATA02 (DWC_OFFSET_MASK + 0x7D22)
-#define HDMITX_DWC_CEC_RX_DATA03 (DWC_OFFSET_MASK + 0x7D23)
-#define HDMITX_DWC_CEC_RX_DATA04 (DWC_OFFSET_MASK + 0x7D24)
-#define HDMITX_DWC_CEC_RX_DATA05 (DWC_OFFSET_MASK + 0x7D25)
-#define HDMITX_DWC_CEC_RX_DATA06 (DWC_OFFSET_MASK + 0x7D26)
-#define HDMITX_DWC_CEC_RX_DATA07 (DWC_OFFSET_MASK + 0x7D27)
-#define HDMITX_DWC_CEC_RX_DATA08 (DWC_OFFSET_MASK + 0x7D28)
-#define HDMITX_DWC_CEC_RX_DATA09 (DWC_OFFSET_MASK + 0x7D29)
-#define HDMITX_DWC_CEC_RX_DATA10 (DWC_OFFSET_MASK + 0x7D2A)
-#define HDMITX_DWC_CEC_RX_DATA11 (DWC_OFFSET_MASK + 0x7D2B)
-#define HDMITX_DWC_CEC_RX_DATA12 (DWC_OFFSET_MASK + 0x7D2C)
-#define HDMITX_DWC_CEC_RX_DATA13 (DWC_OFFSET_MASK + 0x7D2D)
-#define HDMITX_DWC_CEC_RX_DATA14 (DWC_OFFSET_MASK + 0x7D2E)
-#define HDMITX_DWC_CEC_RX_DATA15 (DWC_OFFSET_MASK + 0x7D2F)
-#define HDMITX_DWC_CEC_LOCK_BUF (DWC_OFFSET_MASK + 0x7D30)
-#define HDMITX_DWC_CEC_WAKEUPCTRL (DWC_OFFSET_MASK + 0x7D31)
-
-/* I2C Master Registers(E-DDC/SCDC) */
-#define HDMITX_DWC_I2CM_SLAVE (DWC_OFFSET_MASK + 0x7E00)
-#define HDMITX_DWC_I2CM_ADDRESS (DWC_OFFSET_MASK + 0x7E01)
-#define HDMITX_DWC_I2CM_DATAO (DWC_OFFSET_MASK + 0x7E02)
-#define HDMITX_DWC_I2CM_DATAI (DWC_OFFSET_MASK + 0x7E03)
-#define HDMITX_DWC_I2CM_OPERATION (DWC_OFFSET_MASK + 0x7E04)
-/* [ 2] done_mask */
-/* [ 6] read_req_mask */
-#define HDMITX_DWC_I2CM_INT (DWC_OFFSET_MASK + 0x7E05)
-/* [ 6] nack_mask */
-/* [ 2] arbitration_error_mask */
-#define HDMITX_DWC_I2CM_CTLINT (DWC_OFFSET_MASK + 0x7E06)
-/* [ 3] i2c_fast_mode: 0=standard mode; 1=fast mode. */
-#define HDMITX_DWC_I2CM_DIV (DWC_OFFSET_MASK + 0x7E07)
-#define HDMITX_DWC_I2CM_SEGADDR (DWC_OFFSET_MASK + 0x7E08)
-#define HDMITX_DWC_I2CM_SOFTRSTZ (DWC_OFFSET_MASK + 0x7E09)
-#define HDMITX_DWC_I2CM_SEGPTR (DWC_OFFSET_MASK + 0x7E0A)
-/* I2CM_SS_SCL_HCNT = RndUp(min_ss_scl_htime*Freq(sfrclkInMHz)/1000) */
-/* I2CM_SS_SCL_LCNT = RndUp(min_ss_scl_ltime*Freq(sfrclkInMHz)/1000) */
-/* I2CM_FS_SCL_HCNT = RndUp(min_fs_scl_htime*Freq(sfrclkInMHz)/1000) */
-/* I2CM_FS_SCL_LCNT = RndUp(min_fs_scl_ltime*Freq(sfrclkInMHz)/1000) */
-/* Where Freq(sfrclkInMHz)=24; */
-#define HDMITX_DWC_I2CM_SS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x7E0B)
-#define HDMITX_DWC_I2CM_SS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x7E0C)
-#define HDMITX_DWC_I2CM_SS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x7E0D)
-#define HDMITX_DWC_I2CM_SS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x7E0E)
-#define HDMITX_DWC_I2CM_FS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x7E0F)
-#define HDMITX_DWC_I2CM_FS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x7E10)
-#define HDMITX_DWC_I2CM_FS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x7E11)
-#define HDMITX_DWC_I2CM_FS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x7E12)
-#define HDMITX_DWC_I2CM_SDA_HOLD (DWC_OFFSET_MASK + 0x7E13)
-/* [ 5] updt_rd_vsyncpoll_en */
-/* [ 4] read_request_en */
-/* [ 0] read_update */
-#define HDMITX_DWC_I2CM_SCDC_UPDATE (DWC_OFFSET_MASK + 0x7E14)
-#define HDMITX_DWC_I2CM_READ_BUFF0 (DWC_OFFSET_MASK + 0x7E20)
-#define HDMITX_DWC_I2CM_READ_BUFF1 (DWC_OFFSET_MASK + 0x7E21)
-#define HDMITX_DWC_I2CM_READ_BUFF2 (DWC_OFFSET_MASK + 0x7E22)
-#define HDMITX_DWC_I2CM_READ_BUFF3 (DWC_OFFSET_MASK + 0x7E23)
-#define HDMITX_DWC_I2CM_READ_BUFF4 (DWC_OFFSET_MASK + 0x7E24)
-#define HDMITX_DWC_I2CM_READ_BUFF5 (DWC_OFFSET_MASK + 0x7E25)
-#define HDMITX_DWC_I2CM_READ_BUFF6 (DWC_OFFSET_MASK + 0x7E26)
-#define HDMITX_DWC_I2CM_READ_BUFF7 (DWC_OFFSET_MASK + 0x7E27)
-#define HDMITX_DWC_I2CM_SCDC_UPDATE0 (DWC_OFFSET_MASK + 0x7E30)
-#define HDMITX_DWC_I2CM_SCDC_UPDATE1 (DWC_OFFSET_MASK + 0x7E31)
-
-#endif /* __HDMI_TX_REG_H_ */
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx_set.c b/drivers/amlogic/media/vout/hdmitx/hdmitx_set.c
deleted file mode 100644
index 1cf3dfd..0000000
--- a/drivers/amlogic/media/vout/hdmitx/hdmitx_set.c
+++ /dev/null
@@ -1,2427 +0,0 @@
-/*
- * driver/amlogic/media/vout/hdmitx/hdmitx_set.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <common.h>
-#include <asm/io.h>
-#include <asm/arch/secure_apb.h>
-
-#include <amlogic/media/vout/hdmitx.h>
-#include "hdmitx_reg.h"
-#include "hdmitx_common.h"
-
-const static char *vend_name = "Amlogic"; /* Max 8 bytes */
-const static char *prod_desc = "MBox Meson Ref"; /* Max 16 bytes */
-
-struct hdmitx_dev hdmitx_device;
-
-static void hdmi_tvenc_set(enum hdmi_vic vic);
-extern void _udelay(unsigned int us);
-static void set_tmds_clk_div40(unsigned int div40);
-
-#define HSYNC_POLARITY 1 /*HSYNC polarity: active high*/
-#define VSYNC_POLARITY 1 /*VSYNC polarity: active high*/
-
-/*Pixel format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420.*/
-#define TX_INPUT_COLOR_FORMAT HDMI_COLOR_FORMAT_444
-/*Pixel range: 0=limited; 1=full.*/
-#define TX_INPUT_COLOR_RANGE HDMI_COLOR_RANGE_LIM
-/*Pixel range: 0=limited; 1=full.*/
-#define TX_OUTPUT_COLOR_RANGE HDMI_COLOR_RANGE_LIM
-
-static void hdelay(int us)
-{
- _udelay(us * 1000);
-}
-
-#define mdelay(i) hdelay(i)
-#define msleep(i) hdelay(i)
-
-static void hdmitx_set_hw(struct hdmitx_dev *hdev);
-
-/*Internal functions:*/
-static void hdmitx_csc_config (unsigned char input_color_format,
- unsigned char output_color_format,
- unsigned char color_depth);
-
-static void dump_regs(void)
-{
- unsigned int reg_adr;
-
- for (reg_adr = 0x0; reg_adr < 0x100; reg_adr ++)
- printk("[0x%08lx] = 0x%lx\n", REG_BASE_HIU + (reg_adr << 2),
- hd_read_reg((volatile unsigned int *)(REG_BASE_HIU + (reg_adr << 2))));
-
- for (reg_adr = 0x1b00; reg_adr < (0x1b00 + 0x200); reg_adr ++)
- printk("[0x%08lx] = 0x%lx\n", REG_BASE_VCBUS + (reg_adr << 2),
- hd_read_reg((volatile unsigned int *)(REG_BASE_VCBUS + (reg_adr << 2))));
-
- for (reg_adr = 0x2700; reg_adr < (0x2700 + 0x100); reg_adr ++)
- printk("[0x%08lx] = 0x%lx\n", REG_BASE_VCBUS + (reg_adr << 2),
- hd_read_reg((volatile unsigned int *)(REG_BASE_VCBUS + (reg_adr << 2))));
-
- for (reg_adr = HDMITX_TOP_SW_RESET; reg_adr <
- HDMITX_TOP_DDC_CNTL; reg_adr ++)
- printk("[0x%08x] = 0x%X\n", reg_adr,
- hdmitx_rd_reg(reg_adr));
-
- for (reg_adr = HDMITX_DWC_DESIGN_ID; reg_adr <
- HDMITX_DWC_A_COREVERMSB; reg_adr ++)
- printk("[0x%08x] = 0x%X\n", reg_adr,
- hdmitx_rd_reg(reg_adr));
-
- for (reg_adr = HDMITX_DWC_HDCPREG_BKSV0; reg_adr <
- HDMITX_DWC_I2CM_SCDC_UPDATE1; reg_adr ++)
- printk("[0x%08x] = 0x%X\n", reg_adr,
- hdmitx_rd_reg(reg_adr));
-
-}
-
-static void hdmitx_hw_init(void)
-{
- static int hw_init_flag;
-
- if (hw_init_flag)
- return;
- else
- hw_init_flag = 1;
-
- /* Enable clocks and bring out of reset */
-
- /* Enable hdmitx_sys_clk */
- /* .clk0 ( cts_oscin_clk ), */
- /* .clk1 ( fclk_div4 ), */
- /* .clk2 ( fclk_div3 ), */
- /* .clk3 ( fclk_div5 ), */
- hd_set_reg_bits(P_HHI_HDMI_CLK_CNTL, 0x0100, 0, 16);
-
- /* Enable clk81_hdmitx_pclk */
- hd_set_reg_bits(P_HHI_GCLK_MPEG2, 1, 4, 1);
-
- /* wire wr_enable = control[3]; */
- /* wire fifo_enable = control[2]; */
- /* assign phy_clk_en = control[1]; */
- /* Enable tmds_clk */
- /* Bring HDMITX MEM output of power down */
- hd_set_reg_bits(P_HHI_MEM_PD_REG0, 0, 8, 8);
- /* reset HDMITX APB & TX & PHY */
-
- hd_set_reg_bits(P_RESET0_REGISTER, 1, 19, 1);
- hd_set_reg_bits(P_RESET2_REGISTER, 1, 15, 1);
- hd_set_reg_bits(P_RESET2_REGISTER, 1, 2, 1);
-
- /* Enable APB3 fail on error */
- hdmitx_enable_apb3();
-
- /* Bring out of reset */
- hdmitx_wr_reg(HDMITX_TOP_SW_RESET, 0);
- _udelay(200);
- /* Enable internal pixclk, tmds_clk, spdif_clk, i2s_clk, cecclk */
- hdmitx_wr_reg(HDMITX_TOP_CLK_CNTL, 0x000000ff);
-
- hdmitx_wr_reg(HDMITX_DWC_MC_LOCKONCLOCK, 0xff);
-
- hdmitx_wr_reg(HDMITX_DWC_MC_CLKDIS, 0x00);
-}
-
-/*
- * Note: read 8 Bytes of EDID data every time
- */
-static int read_edid_8bytes(unsigned char *rx_edid, unsigned char addr)
-{
- unsigned int timeout = 0;
- unsigned int i = 0;
- /*Program SLAVE/SEGMENT/ADDR*/
- hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, 0x50);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_SEGADDR, 0x30);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_SEGPTR, 0);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, addr & 0xff);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1 << 3);
- timeout = 0;
- while ((!(hdmitx_rd_reg(HDMITX_DWC_IH_I2CM_STAT0) & (1 << 1))) && (timeout < 3)) {
- mdelay(2);
- timeout ++;
- }
- if (timeout == 3) {
- printk("ddc timeout\n");
- return 0;
- }
- hdmitx_wr_reg(HDMITX_DWC_IH_I2CM_STAT0, 1 << 1); /*clear INT*/
- /*Read back 8 bytes*/
- for (i = 0; i < 8; i ++) {
- rx_edid[i] = hdmitx_rd_reg(HDMITX_DWC_I2CM_READ_BUFF0 + i);
- }
- return 1;
-}
-
-static void ddc_init(void)
-{
- static int ddc_init_flag;
- unsigned int data32 = 0;
-
-
- if (ddc_init_flag)
- return;
- else
- ddc_init_flag = 1;
-
- ddc_pinmux_init();
-
- data32 = 0;
- data32 |= (0 << 6); /*[ 6] read_req_mask*/
- data32 |= (0 << 2); /*[ 2] done_mask*/
- hdmitx_wr_reg(HDMITX_DWC_I2CM_INT, data32);
-
- data32 = 0;
- data32 |= (0 << 6); /*[ 6] nack_mask*/
- data32 |= (0 << 2); /*[ 2] arbitration_error_mask*/
- hdmitx_wr_reg(HDMITX_DWC_I2CM_CTLINT, data32);
-
- data32 = 0;
- data32 |= (0 << 3); /*[ 3] i2c_fast_mode: 0=standard mode; 1=fast mode.*/
- hdmitx_wr_reg(HDMITX_DWC_I2CM_DIV, data32);
-
- hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_HCNT_1, 0);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_HCNT_0, 0xcf);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_LCNT_1, 0);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_SS_SCL_LCNT_0, 0xff);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_HCNT_1, 0);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_HCNT_0, 0x0f);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_LCNT_1, 0);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_FS_SCL_LCNT_0, 0x20);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_SDA_HOLD, 0x08);
-
- data32 = 0;
- data32 |= (0 << 5); /*[ 5] updt_rd_vsyncpoll_en*/
- data32 |= (0 << 4); /*[ 4] read_request_en scdc*/
- data32 |= (0 << 0); /*[ 0] read_update*/
- hdmitx_wr_reg(HDMITX_DWC_I2CM_SCDC_UPDATE, data32);
-}
-
-static int hdmitx_read_edid(unsigned char *buf, unsigned char addr, unsigned char size)
-{
- ddc_init();
- if ((addr + size) > 256)
- return 0;
- return read_edid_8bytes(buf, addr);
-}
-
-static void scdc_rd_sink(unsigned char adr, unsigned char *val)
-{
- hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, 0x54);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, adr);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 1);
- _udelay(2000);
- *val = (unsigned char)hdmitx_rd_reg(HDMITX_DWC_I2CM_DATAI);
-}
-
-static void scdc_wr_sink(unsigned char adr, unsigned char val)
-{
- hdmitx_wr_reg(HDMITX_DWC_I2CM_SLAVE, 0x54);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_ADDRESS, adr);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_DATAO, val);
- hdmitx_wr_reg(HDMITX_DWC_I2CM_OPERATION, 0x10);
- _udelay(2000);
-}
-
-static void scdc_prepare(unsigned int div)
-{
- unsigned char rx_ver = 0;
-
- scdc_rd_sink(SINK_VER, &rx_ver);
- if (rx_ver != 1)
- scdc_rd_sink(SINK_VER, &rx_ver); /* Recheck */
- printf("rx version is %s div=%d\n",
- (rx_ver == 1) ? "2.0" : "1.4 or below",
- div ? 40 : 10);
-
- scdc_wr_sink(SOURCE_VER, 0x1);
- scdc_wr_sink(SOURCE_VER, 0x1);
- scdc_wr_sink(TMDS_CFG, div ? 0x3 : 0); /* TMDS 1/40 & Scramble */
- scdc_wr_sink(TMDS_CFG, div ? 0x3 : 0); /* TMDS 1/40 & Scramble */
-}
-
-static struct hdmi_support_mode gxbb_modes[] = {
- {HDMI_3840x2160p60_16x9, "2160p60hz", 0},
- {HDMI_3840x2160p50_16x9, "2160p50hz", 0},
- {HDMI_3840x2160p30_16x9, "2160p30hz", 0},
- {HDMI_3840x2160p25_16x9, "2160p25hz", 0},
- {HDMI_3840x2160p24_16x9, "2160p24hz", 0},
- {HDMI_4096x2160p60_256x135, "smpte60hz", 0},
- {HDMI_4096x2160p50_256x135, "smpte50hz", 0},
- {HDMI_4096x2160p30_256x135, "smpte30hz", 0},
- {HDMI_4096x2160p25_256x135, "smpte25hz", 0},
- {HDMI_4096x2160p24_256x135, "smpte24hz", 0},
- {HDMI_3840x2160p60_16x9, "2160p60hz420", 1},
- {HDMI_3840x2160p50_16x9, "2160p50hz420", 1},
- {HDMI_4096x2160p50_256x135, "smpte50hz420", 1},
- {HDMI_4096x2160p60_256x135, "smpte60hz420", 1},
- {HDMI_1920x1080p60_16x9, "1080p60hz", 0},
- {HDMI_1920x1080p50_16x9, "1080p50hz", 0},
- {HDMI_1920x1080p30_16x9, "1080p30hz", 0},
- {HDMI_1920x1080p25_16x9, "1080p25hz", 0},
- {HDMI_1920x1080p24_16x9, "1080p24hz", 0},
- {HDMI_1920x1080i60_16x9, "1080i60hz", 0},
- {HDMI_1920x1080i50_16x9, "1080i50hz", 0},
- {HDMI_1280x720p60_16x9, "720p60hz", 0},
- {HDMI_1280x720p50_16x9, "720p50hz", 0},
- {HDMI_720x576p50_16x9, "576p50hz", 0},
- {HDMI_720x480p60_16x9, "480p60hz", 0},
- {HDMI_720x576i50_16x9, "576i50hz", 0},
- {HDMI_720x480i60_16x9, "480i60hz", 0},
-};
-
-static void hdmitx_list_support_modes(void)
-{
- int i;
-
- for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++)
- printf("%s\n", gxbb_modes[i].sname);
-}
-
-static void hdmitx_test_bist(unsigned int mode)
-{
- switch (mode) {
- case 0:
- hd_set_reg_bits(P_ENCP_VIDEO_MODE_ADV, 1, 3, 1);
- hd_write_reg(P_VENC_VIDEO_TST_EN, 0);
- break;
- case 1:
- case 2:
- case 3:
- hd_set_reg_bits(P_ENCP_VIDEO_MODE_ADV, 0, 3, 1);
- hd_write_reg(P_VENC_VIDEO_TST_EN, 1);
- hd_write_reg(P_VENC_VIDEO_TST_MDSEL, mode);
- break;
- case 10:
- hdmitx_prbs();
- break;
- case 11:
- set_tmds_clk_div40(1);
- break;
- default:
- pr_info("hdmitx commands have no this parameter\n");
- break;
- }
-}
-
-static void hdmitx_output_blank(unsigned int blank)
-{
- if (blank == 1)
- hd_write_reg(P_VPU_HDMI_DATA_OVR,
- ((1 << 31) | (1 << 29) | (1 << 9)));
- if (blank == 0)
- hd_write_reg(P_VPU_HDMI_DATA_OVR, 0);
-}
-
-void hdmi_tx_init(void)
-{
- hdmitx_device.HWOp.get_hpd_state = hdmitx_get_hpd_state;
- hdmitx_device.HWOp.read_edid = hdmitx_read_edid;
- hdmitx_device.HWOp.turn_off = hdmitx_turnoff;
- hdmitx_device.HWOp.list_support_modes = hdmitx_list_support_modes;
- hdmitx_device.HWOp.dump_regs = dump_regs;
- hdmitx_device.HWOp.test_bist = hdmitx_test_bist;
- hdmitx_device.HWOp.output_blank = hdmitx_output_blank;
-}
-
-void hdmi_tx_set(struct hdmitx_dev *hdev)
-{
- hdmitx_hw_init();
- ddc_init();
- hdmitx_set_hw(hdev);
- return;
-
-#if 0
- hdmi_tx_gate(vic);
- hdmi_tx_clk(vic);
- hdmi_tx_misc(vic);
- hdmi_tx_enc(vic);
- hdmi_tx_set_vend_spec_infofram(vic);
- hdmi_tx_phy(vic);
-#endif
-}
-
-int hdmi_outputmode_check(char *mode)
-{
- int i, ret = -1;
-
- for (i = 0; i < ARRAY_SIZE(gxbb_modes); i++) {
- if (!strcmp(mode, gxbb_modes[i].sname)) {
- ret = 0;
- break;
- }
- }
-
- if (ret)
- printf("hdmitx: outputmode[%s] is invalid\n", mode);
- return ret;
-}
-
-#define __asmeq(x, y) ".ifnc " x "," y " ; .err ; .endif\n\t"
-static void hdcp14_init(void)
-{
- register long x0 asm("x0") = 0x82000012;
- asm volatile(
- __asmeq("%0", "x0")
- "smc #0\n"
- : : "r"(x0)
- );
-}
-
-/*
- * set Source Product Description InfoFrame
- */
-static void hdmitx_set_spdinfo(void)
-{
- int i;
-
- if (!(vend_name && prod_desc))
- return;
-
- for (i = 0; (i < 8) && vend_name[i]; i++)
- hdmitx_wr_reg(HDMITX_DWC_FC_SPDVENDORNAME0 + i, vend_name[i]);
- for (i = 0; (i < 16) && prod_desc[i]; i++)
- hdmitx_wr_reg(HDMITX_DWC_FC_SDPPRODUCTNAME0 + i, prod_desc[i]);
- hdmitx_wr_reg(HDMITX_DWC_FC_SPDDEVICEINF, 0x1);
- hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO0, 1, 4, 1);
- hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO2, 1, 4, 4);
- hdmitx_set_reg_bits(HDMITX_DWC_FC_PACKET_TX_EN, 1, 4, 1);
-}
-
-#define NUM_INT_VSYNC INT_VEC_VIU1_VSYNC
-
-static unsigned long modulo(unsigned long a, unsigned long b);
-static signed int to_signed(unsigned int a);
-
-/*Pixel bit width: 4=24-bit; 5=30-bit; 6=36-bit; 7=48-bit.
- *Pixel format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420.
- *Pixel range: 0=limited; 1=full.
- *Pixel format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420.
- *Pixel range: 0=limited; 1=full.
- *0:TMDS_CLK_rate=TMDS_Character_rate; 1:TMDS_CLK_rate=TMDS_Character_rate/4,
- *for TMDS_Character_rate>340Mcsc.
- */
-static void config_hdmi20_tx ( enum hdmi_vic vic, struct hdmi_format_para *para,
- unsigned char color_depth, unsigned char input_color_format,
- unsigned char input_color_range, unsigned char output_color_format,
- unsigned char output_color_range)
-{
- struct hdmi_cea_timing *t = ¶->timing;
- unsigned long data32;
- unsigned char vid_map;
- unsigned char csc_en;
- unsigned char default_phase = 0;
- unsigned char tmp = 0;
-
-#define GET_TIMING(name) (t->name)
-
- hdmitx_hw_init();
-
- data32 = 0;
- data32 |= (1 << 12);
- data32 |= (0 << 8);
- data32 |= (0 << 0);
- hdmitx_wr_reg(HDMITX_TOP_BIST_CNTL, data32);
-
- /* Configure video */
-
- /*Configure video sampler*/
- vid_map = ( input_color_format == HDMI_COLOR_FORMAT_RGB )? ((color_depth == HDMI_COLOR_DEPTH_24B)? 0x01 :
- (color_depth == HDMI_COLOR_DEPTH_30B)? 0x03 :
- (color_depth == HDMI_COLOR_DEPTH_36B)? 0x05 :
- 0x07) :
- ((input_color_format == HDMI_COLOR_FORMAT_444) ||
- (input_color_format == HDMI_COLOR_FORMAT_420))? ((color_depth == HDMI_COLOR_DEPTH_24B)? 0x09 :
- (color_depth == HDMI_COLOR_DEPTH_30B)? 0x0b :
- (color_depth == HDMI_COLOR_DEPTH_36B)? 0x0d :
- 0x0f) :
- ((color_depth == HDMI_COLOR_DEPTH_24B)? 0x16 :
- (color_depth == HDMI_COLOR_DEPTH_30B)? 0x14 :
- 0x12);
-
- data32 = 0;
- data32 |= (0 << 7);
- data32 |= (vid_map << 0);
- hdmitx_wr_reg(HDMITX_DWC_TX_INVID0, data32);
-
- data32 = 0;
- data32 |= (0 << 2);
- data32 |= (0 << 1);
- data32 |= (0 << 0);
- hdmitx_wr_reg(HDMITX_DWC_TX_INSTUFFING, data32);
- hdmitx_wr_reg(HDMITX_DWC_TX_GYDATA0, 0x00);
- hdmitx_wr_reg(HDMITX_DWC_TX_GYDATA1, 0x00);
- hdmitx_wr_reg(HDMITX_DWC_TX_RCRDATA0, 0x00);
- hdmitx_wr_reg(HDMITX_DWC_TX_RCRDATA1, 0x00);
- hdmitx_wr_reg(HDMITX_DWC_TX_BCBDATA0, 0x00);
- hdmitx_wr_reg(HDMITX_DWC_TX_BCBDATA1, 0x00);
-
- /* Configure Color Space Converter */
-
- csc_en = (input_color_format != output_color_format) ? 1 : 0;
-
- data32 = 0;
- data32 |= (csc_en << 0);
- hdmitx_wr_reg(HDMITX_DWC_MC_FLOWCTRL, data32);
-
- data32 = 0;
- data32 |= ((((input_color_format ==HDMI_COLOR_FORMAT_422) &&
- (output_color_format!=HDMI_COLOR_FORMAT_422))? 2 : 0 ) << 4); /*[5:4] intmode*/
- data32 |= ((((input_color_format !=HDMI_COLOR_FORMAT_422) &&
- (output_color_format==HDMI_COLOR_FORMAT_422))? 2 : 0 ) << 0); /*[1:0] decmode*/
- hdmitx_wr_reg(HDMITX_DWC_CSC_CFG, data32);
-
- hdmitx_csc_config(input_color_format, output_color_format, color_depth);
-
- /* Configure video packetizer */
-
- /* Video Packet color depth and pixel repetition */
- data32 = 0;
- data32 |= (((output_color_format==HDMI_COLOR_FORMAT_422)?
- HDMI_COLOR_DEPTH_24B : color_depth) << 4); /*[7:4] color_depth*/
- data32 |= (0 << 0);
- if ((data32 & 0xf0) == 0x40 )
- data32 &= ~(0xf << 4);
- hdmitx_wr_reg(HDMITX_DWC_VP_PR_CD, data32);
- if (output_color_format == HDMI_COLOR_FORMAT_422) {
- switch (color_depth) {
- case HDMI_COLOR_DEPTH_24B:
- tmp = 4;
- break;
- default:
- tmp = 0;
- break;
- }
- hdmitx_set_reg_bits(HDMITX_DWC_VP_PR_CD, tmp, 4, 4);
- }
-
- /* Video Packet Stuffing */
- data32 = 0;
- data32 |= (default_phase << 5);
- data32 |= (0 << 2);
- data32 |= (0 << 1);
- data32 |= (0 << 0);
- hdmitx_wr_reg(HDMITX_DWC_VP_STUFF, data32);
-
- /* Video Packet YCC color remapping */
- data32 = 0;
- hdmitx_wr_reg(HDMITX_DWC_VP_REMAP, data32);
- if (output_color_format == HDMI_COLOR_FORMAT_422) {
- switch (color_depth) {
- case HDMI_COLOR_DEPTH_36B:
- tmp = 2;
- break;
- case HDMI_COLOR_DEPTH_30B:
- tmp = 1;
- break;
- case HDMI_COLOR_DEPTH_24B:
- tmp = 0;
- break;
- }
- }
- hdmitx_set_reg_bits(HDMITX_DWC_VP_REMAP, tmp, 0, 2); /*[1:0] ycc422_size*/
-
- /* Video Packet configuration */
- data32 = 0;
- data32 |= ((((output_color_format != HDMI_COLOR_FORMAT_422) &&
- (color_depth == HDMI_COLOR_DEPTH_24B))? 1 : 0) << 6); /*[ 6] bypass_en*/
- data32 |= ((((output_color_format == HDMI_COLOR_FORMAT_422) ||
- (color_depth == HDMI_COLOR_DEPTH_24B))? 0 : 1) << 5); /*[ 5] pp_en*/
- data32 |= (0 << 4); /*[ 4] pr_en*/
- data32 |= (((output_color_format == HDMI_COLOR_FORMAT_422)? 1 : 0) << 3); /*[ 3] ycc422_en*/
- data32 |= (1 << 2); /*[ 2] pr_bypass_select*/
- data32 |= (((output_color_format == HDMI_COLOR_FORMAT_422)? 1 :
- (color_depth == HDMI_COLOR_DEPTH_24B)? 2 : 0) << 0);
- /*[1:0] output_selector: 0=pixel packing; 1=YCC422 remap; 2/3=8-bit bypass*/
- hdmitx_wr_reg(HDMITX_DWC_VP_CONF, data32);
-
- data32 = 0;
- data32 |= (1 << 7);
- data32 |= (1 << 6);
- data32 |= (1 << 5);
- data32 |= (1 << 4);
- data32 |= (1 << 3);
- data32 |= (1 << 2);
- data32 |= (1 << 1);
- data32 |= (1 << 0);
- hdmitx_wr_reg(HDMITX_DWC_VP_MASK, data32);
-
- /* Configure audio */
- /* I2S Sampler config */
-
- data32 = 0;
- data32 |= (1 << 3);
- data32 |= (1 << 2);
- hdmitx_wr_reg(HDMITX_DWC_AUD_INT, data32);
-
- data32 = 0;
- data32 |= (1 << 4);
- hdmitx_wr_reg(HDMITX_DWC_AUD_INT1, data32);
-
- hdmitx_wr_reg(HDMITX_DWC_FC_MULTISTREAM_CTRL, 0);
-
-/* if enable it now, fifo_overrun will happen, because packet don't get
- * sent out until initial DE detected.
- */
- data32 = 0;
- data32 |= (0 << 7);
- data32 |= (1 << 5);
- data32 |= (0 << 0);
- hdmitx_wr_reg(HDMITX_DWC_AUD_CONF0, data32);
-
- data32 = 0;
- data32 |= (0 << 5);
- data32 |= (24 << 0);
- hdmitx_wr_reg(HDMITX_DWC_AUD_CONF1, data32);
-
- data32 = 0;
- data32 |= (0 << 1);
- data32 |= (0 << 0);
- hdmitx_wr_reg(HDMITX_DWC_AUD_CONF2, data32);
-
- /* spdif sampler config */
-
- data32 = 0;
- data32 |= (1 << 3);
- data32 |= (1 << 2);
- hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIFINT, data32);
-
- data32 = 0;
- data32 |= (0 << 4);
- hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIFINT1, data32);
-
- data32 = 0;
- data32 |= (0 << 7);
- hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIF0, data32);
-
- data32 = 0;
- data32 |= (0 << 7);
- data32 |= (0 << 6);
- data32 |= (24 << 0);
- hdmitx_wr_reg(HDMITX_DWC_AUD_SPDIF1, data32);
-
- /* Frame Composer configuration */
-
- /* Video definitions, as per output video(for packet gen/schedulling) */
-
- data32 = 0;
- data32 |= (1 << 7);
- data32 |= (GET_TIMING(vsync_polarity) << 6);
- data32 |= (GET_TIMING(hsync_polarity) << 5);
- data32 |= (1 << 4);
- data32 |= (1 << 3);
- data32 |= (!(para->progress_mode) << 1);
- data32 |= (!(para->progress_mode) << 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_INVIDCONF, data32);
-
- data32 = GET_TIMING(h_active)&0xff;
- hdmitx_wr_reg(HDMITX_DWC_FC_INHACTV0, data32);
- data32 = (GET_TIMING(h_active)>>8) & 0x3f;
- hdmitx_wr_reg(HDMITX_DWC_FC_INHACTV1, data32);
-
- data32 = GET_TIMING(h_blank) & 0xff;
- hdmitx_wr_reg(HDMITX_DWC_FC_INHBLANK0, data32);
- data32 = (GET_TIMING(h_blank)>>8)&0x1f;
- hdmitx_wr_reg(HDMITX_DWC_FC_INHBLANK1, data32);
-
- data32 = GET_TIMING(v_active)&0xff;
- hdmitx_wr_reg(HDMITX_DWC_FC_INVACTV0, data32);
- data32 = (GET_TIMING(v_active)>>8)&0x1f;
- hdmitx_wr_reg(HDMITX_DWC_FC_INVACTV1, data32);
-
- data32 = GET_TIMING(v_blank)&0xff;
- hdmitx_wr_reg(HDMITX_DWC_FC_INVBLANK, data32);
-
- data32 = GET_TIMING(h_front)&0xff;
- hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINDELAY0, data32);
- data32 = (GET_TIMING(h_front)>>8)&0x1f;
- hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINDELAY1, data32);
-
- data32 = GET_TIMING(h_sync)&0xff;
- hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINWIDTH0, data32);
- data32 = (GET_TIMING(h_sync)>>8)&0x3;
- hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINWIDTH1, data32);
-
- data32 = GET_TIMING(v_front)&0xff;
- hdmitx_wr_reg(HDMITX_DWC_FC_VSYNCINDELAY, data32);
-
- data32 = GET_TIMING(v_sync)&0x3f;
- hdmitx_wr_reg(HDMITX_DWC_FC_VSYNCINWIDTH, data32);
-
- /* control period duration (typ 12 tmds periods) */
- hdmitx_wr_reg(HDMITX_DWC_FC_CTRLDUR, 12);
- /* extended control period duration (typ 32 tmds periods) */
- hdmitx_wr_reg(HDMITX_DWC_FC_EXCTRLDUR, 32);
- /* max interval betwen extended control period duration (typ 50) */
- hdmitx_wr_reg(HDMITX_DWC_FC_EXCTRLSPAC, 1);
- /* preamble filler */
- hdmitx_wr_reg(HDMITX_DWC_FC_CH0PREAM, 0x0b);
- hdmitx_wr_reg(HDMITX_DWC_FC_CH1PREAM, 0x16);
- hdmitx_wr_reg(HDMITX_DWC_FC_CH2PREAM, 0x21);
-
- /* write GCP packet configuration */
- data32 = 0;
- data32 |= (default_phase << 2);
- data32 |= (0 << 1);
- data32 |= (1 << 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_GCP, data32);
-
- /* write AVI Infoframe packet configuration */
-
- data32 = 0;
- data32 |= (((output_color_format>>2)&0x1) << 7);
- data32 |= (1 << 6);
- data32 |= (0 << 4);
- data32 |= (0 << 2);
- data32 |= (0x2 << 0); /* FIXED YCBCR 444 */
- hdmitx_wr_reg(HDMITX_DWC_FC_AVICONF0, data32);
- switch (output_color_format) {
- case HDMI_COLOR_FORMAT_RGB:
- tmp = 0;
- break;
- case HDMI_COLOR_FORMAT_422:
- tmp = 1;
- break;
- case HDMI_COLOR_FORMAT_420:
- tmp = 3;
- break;
- case HDMI_COLOR_FORMAT_444:
- default:
- tmp = 2;
- break;
- }
- hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF0, tmp, 0, 2);
-
- hdmitx_wr_reg(HDMITX_DWC_FC_AVICONF1, 0x8);
- hdmitx_wr_reg(HDMITX_DWC_FC_AVICONF2, 0);
-
- /* set Aspect Ratio in AVIInfo */
- switch (para->vic) {
- case HDMI_640x480p60_4x3:
- case HDMI_720x480p60_4x3:
- case HDMI_720x480i60_4x3:
- case HDMI_720x240p60_4x3:
- case HDMI_2880x480i60_4x3:
- case HDMI_2880x240p60_4x3:
- case HDMI_1440x480p60_4x3:
- case HDMI_720x576p50_4x3:
- case HDMI_720x576i50_4x3:
- case HDMI_720x288p_4x3:
- case HDMI_2880x576i50_4x3:
- case HDMI_2880x288p50_4x3:
- case HDMI_1440x576p_4x3:
- case HDMI_2880x480p60_4x3:
- case HDMI_2880x576p50_4x3:
- case HDMI_720x576p100_4x3:
- case HDMI_720x576i100_4x3:
- case HDMI_720x480p120_4x3:
- case HDMI_720x480i120_4x3:
- case HDMI_720x576p200_4x3:
- case HDMI_720x576i200_4x3:
- case HDMI_720x480p240_4x3:
- case HDMI_720x480i240_4x3:
- /* Picture Aspect Ratio M1/M0 4:3 */
- hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 0x1, 4, 2);
- break;
- default:
- /* Picture Aspect Ratio M1/M0 16:9 */
- hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 0x2, 4, 2);
- break;
- }
- /* Active Format Aspect Ratio R3~R0 Same as picture aspect ratio */
- hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 0x8, 0, 4);
-
- /* set Colorimetry in AVIInfo */
- switch (para->vic) {
- case HDMI_640x480p60_4x3:
- case HDMI_720x480p60_4x3:
- case HDMI_720x480p60_16x9:
- case HDMI_720x480i60_4x3:
- case HDMI_720x480i60_16x9:
- case HDMI_720x240p60_4x3:
- case HDMI_720x240p60_16x9:
- case HDMI_2880x480i60_4x3:
- case HDMI_2880x480i60_16x9:
- case HDMI_2880x240p60_4x3:
- case HDMI_2880x240p60_16x9:
- case HDMI_1440x480p60_4x3:
- case HDMI_1440x480p60_16x9:
- case HDMI_720x576p50_4x3:
- case HDMI_720x576p50_16x9:
- case HDMI_720x576i50_4x3:
- case HDMI_720x576i50_16x9:
- case HDMI_720x288p_4x3:
- case HDMI_720x288p_16x9:
- case HDMI_2880x576i50_4x3:
- case HDMI_2880x576i50_16x9:
- case HDMI_2880x288p50_4x3:
- case HDMI_2880x288p50_16x9:
- case HDMI_1440x576p_4x3:
- case HDMI_1440x576p_16x9:
- case HDMI_2880x480p60_4x3:
- case HDMI_2880x480p60_16x9:
- case HDMI_2880x576p50_4x3:
- case HDMI_2880x576p50_16x9:
- case HDMI_720x576p100_4x3:
- case HDMI_720x576p100_16x9:
- case HDMI_720x576i100_4x3:
- case HDMI_720x576i100_16x9:
- case HDMI_720x480p120_4x3:
- case HDMI_720x480p120_16x9:
- case HDMI_720x480i120_4x3:
- case HDMI_720x480i120_16x9:
- case HDMI_720x576p200_4x3:
- case HDMI_720x576p200_16x9:
- case HDMI_720x576i200_4x3:
- case HDMI_720x576i200_16x9:
- case HDMI_720x480p240_4x3:
- case HDMI_720x480p240_16x9:
- case HDMI_720x480i240_4x3:
- case HDMI_720x480i240_16x9:
- /* C1C0 601 , now is 709*/
- hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 1, 6, 2);
- hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF2, 0, 4, 3);
- break;
- default:
- /* C1C0 709 */
- hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF1, 2, 6, 2);
- hdmitx_set_reg_bits(HDMITX_DWC_FC_AVICONF2, 0, 4, 3);
- break;
- }
-
- data32 = 0;
- data32 |= (((output_color_range == HDMI_COLOR_RANGE_FUL)?1:0) << 2); /*[3:2] YQ*/
- data32 |= (0 << 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_AVICONF3, data32);
-
- hdmitx_wr_reg(HDMITX_DWC_FC_AVIVID, para->vic);
-
-/* the audio setting bellow are only used for I2S audio IEC60958-3 frame
- * insertion
- */
-
- /* packet queue priority (auto mode) */
- hdmitx_wr_reg(HDMITX_DWC_FC_CTRLQHIGH, 15);
- hdmitx_wr_reg(HDMITX_DWC_FC_CTRLQLOW, 3);
-
- /* packet scheduller configuration for SPD, VSD, ISRC1/2, ACP. */
- data32 = 0;
- data32 |= (0 << 4);
- data32 |= (0 << 3);
- data32 |= (0 << 2);
- data32 |= (0 << 1);
- data32 |= (0 << 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO0, data32);
- hdmitx_set_spdinfo();
- hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO1, 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO2, 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_DATMAN, 0);
-
- /* packet scheduller configuration for AVI, GCP, AUDI, ACR. */
- data32 = 0;
- data32 |= (0 << 5);
- data32 |= (0 << 4);
- data32 |= (0 << 3);
- data32 |= (1 << 2);
- data32 |= (1 << 1);
- data32 |= (0 << 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO3, data32);
- hdmitx_wr_reg(HDMITX_DWC_FC_RDRB0, 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_RDRB1, 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_RDRB2, 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_RDRB3, 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_RDRB4, 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_RDRB5, 0);
- /* AVI info usb RDRB mode and place in line 10*/
- hdmitx_wr_reg(HDMITX_DWC_FC_RDRB6, 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_RDRB7, 0x1a);
- hdmitx_wr_reg(HDMITX_DWC_FC_RDRB8, 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_RDRB9, 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_RDRB10, 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_RDRB11, 0);
-
- /* Packet transmission enable */
- data32 = 0;
- data32 |= (0 << 6);
- data32 |= (0 << 5);
- data32 |= (0 << 4);
- data32 |= (1 << 3);
- data32 |= (1 << 2);
- data32 |= (1 << 1);
- data32 |= (1 << 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_PACKET_TX_EN, data32);
-
- /* For 3D video */
- data32 = 0;
- data32 |= (0 << 1);
- data32 |= (0 << 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_ACTSPC_HDLR_CFG, data32);
-
- data32 = GET_TIMING(v_active)&0xff;
- hdmitx_wr_reg(HDMITX_DWC_FC_INVACT_2D_0, data32);
- data32 = (GET_TIMING(v_active)>>8)&0xf;
- hdmitx_wr_reg(HDMITX_DWC_FC_INVACT_2D_1, data32);
-
- /* Do not enable these interrupt below, we can check them at RX side. */
- data32 = 0;
- data32 |= (1 << 7);
- data32 |= (1 << 6);
- data32 |= (1 << 5);
- data32 |= (1 << 2);
- data32 |= (1 << 1);
- data32 |= (1 << 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_MASK0, data32);
-
- data32 = 0;
- data32 |= (1 << 7);
- data32 |= (1 << 6);
- data32 |= (1 << 5);
- data32 |= (1 << 4);
- data32 |= (1 << 3);
- data32 |= (1 << 1);
- data32 |= (1 << 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_MASK1, data32);
-
- data32 = 0;
- data32 |= (1 << 1);
- data32 |= (1 << 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_MASK2, data32);
-
- /* Pixel repetition ratio the input and output video */
- data32 = 0;
- data32 |= ((para->pixel_repetition_factor+1) << 4);
- data32 |= (para->pixel_repetition_factor << 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_PRCONF, data32);
-
- /* Configure HDCP */
- data32 = 0;
- data32 |= (0 << 7);
- data32 |= (0 << 6);
- data32 |= (0 << 4);
- data32 |= (0 << 3);
- data32 |= (0 << 2);
- data32 |= (0 << 1);
- data32 |= (1 << 0);
- hdmitx_wr_reg(HDMITX_DWC_A_APIINTMSK, data32);
-
- data32 = 0;
- data32 |= (0 << 5);
- data32 |= (1 << 4);
- data32 |= (1 << 3);
- data32 |= (1 << 1);
- hdmitx_wr_reg(HDMITX_DWC_A_VIDPOLCFG, data32);
-
- hdmitx_wr_reg(HDMITX_DWC_A_OESSWCFG, 0x40);
-
- hdcp14_init();
-
- /* Interrupts */
- /* Clear interrupts */
- hdmitx_wr_reg(HDMITX_DWC_IH_FC_STAT0, 0xff);
- hdmitx_wr_reg(HDMITX_DWC_IH_FC_STAT1, 0xff);
- hdmitx_wr_reg(HDMITX_DWC_IH_FC_STAT2, 0xff);
- hdmitx_wr_reg(HDMITX_DWC_IH_AS_STAT0, 0xff);
- hdmitx_wr_reg(HDMITX_DWC_IH_PHY_STAT0, 0xff);
- hdmitx_wr_reg(HDMITX_DWC_IH_I2CM_STAT0, 0xff);
- hdmitx_wr_reg(HDMITX_DWC_IH_CEC_STAT0, 0xff);
- hdmitx_wr_reg(HDMITX_DWC_IH_VP_STAT0, 0xff);
- hdmitx_wr_reg(HDMITX_DWC_IH_I2CMPHY_STAT0, 0xff);
- hdmitx_wr_reg(HDMITX_DWC_A_APIINTCLR, 0xff);
- hdmitx_wr_reg(HDMITX_DWC_HDCP22REG_STAT, 0xff);
-
- hdmitx_wr_reg(HDMITX_TOP_INTR_STAT_CLR, 0x0000001f);
-
- /* Selectively enable/mute interrupt sources */
- data32 = 0;
- data32 |= (1 << 7);
- data32 |= (1 << 6);
- data32 |= (1 << 5);
- data32 |= (1 << 4);
- data32 |= (1 << 3);
- data32 |= (1 << 2);
- data32 |= (1 << 1);
- data32 |= (1 << 0);
- hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_FC_STAT0, data32);
-
- data32 = 0;
- data32 |= (1 << 7);
- data32 |= (1 << 6);
- data32 |= (1 << 5);
- data32 |= (1 << 4);
- data32 |= (1 << 3);
- data32 |= (1 << 2);
- data32 |= (1 << 1);
- data32 |= (1 << 0);
- hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_FC_STAT1, data32);
-
- data32 = 0;
- data32 |= (1 << 1);
- data32 |= (1 << 0);
- hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_FC_STAT2, data32);
-
- data32 = 0;
- data32 |= (0 << 4);
- data32 |= (0 << 3);
- data32 |= (1 << 2);
- data32 |= (1 << 1);
- data32 |= (1 << 0);
- hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_AS_STAT0, data32);
-
- hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_PHY_STAT0, 0x3f);
-
- data32 = 0;
- data32 |= (0 << 2);
- data32 |= (1 << 1);
- data32 |= (0 << 0);
- hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_I2CM_STAT0, data32);
-
- data32 = 0;
- data32 |= (0 << 6);
- data32 |= (0 << 5);
- data32 |= (0 << 4);
- data32 |= (0 << 3);
- data32 |= (0 << 2);
- data32 |= (0 << 1);
- data32 |= (0 << 0);
- hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_CEC_STAT0, data32);
-
- hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_VP_STAT0, 0xff);
-
- hdmitx_wr_reg(HDMITX_DWC_IH_MUTE_I2CMPHY_STAT0, 0x03);
-
- data32 = 0;
- data32 |= (0 << 1);
- data32 |= (0 << 0);
- hdmitx_wr_reg(HDMITX_DWC_IH_MUTE, data32);
-
- data32 = 0;
- data32 |= (1 << 4);
- data32 |= (1 << 3);
- data32 |= (1 << 2);
- data32 |= (1 << 1);
- data32 |= (1 << 0);
- hdmitx_wr_reg(HDMITX_TOP_INTR_MASKN, data32);
-
- /* Reset pulse */
- hdmitx_rd_check_reg(HDMITX_DWC_MC_LOCKONCLOCK, 0xff, 0x9f);
-
- hd_write_reg(P_ENCP_VIDEO_EN, 0);
- hdmitx_wr_reg(HDMITX_DWC_MC_CLKDIS, 0xdf);
-
- hdmitx_wr_reg(HDMITX_DWC_MC_SWRSTZREQ, 0);
- mdelay(10);
-
- data32 = 0;
- data32 |= (1 << 7);
- data32 |= (1 << 6);
- data32 |= (1 << 4);
- data32 |= (1 << 3);
- data32 |= (1 << 2);
- data32 |= (0 << 1);
- data32 |= (1 << 0);
- hdmitx_wr_reg(HDMITX_DWC_MC_SWRSTZREQ, data32);
- hdmitx_wr_reg(HDMITX_DWC_FC_VSYNCINWIDTH,
- hdmitx_rd_reg(HDMITX_DWC_FC_VSYNCINWIDTH));
-
- hdmitx_wr_reg(HDMITX_DWC_MC_CLKDIS, 0);
- hd_write_reg(P_ENCP_VIDEO_EN, 0xff);
-} /* config_hdmi20_tx */
-
-/* Set TV encoder for HDMI */
-static void hdmitx_enc(enum hdmi_vic vic)
-{
- set_vmode_enc_hw(vic);
- hdmi_tvenc_set(vic);
- return;
-}
-
-static void hdmitx_set_pll(struct hdmitx_dev *hdev)
-{
- hdmitx_set_clk(hdev);
-}
-
-/*
- * mode: 1 means Progressive; 0 means interlaced
- */
-static void enc_vpu_bridge_reset(int mode)
-{
- unsigned int wr_clk = 0;
-
- printk("%s[%d]\n", __func__, __LINE__);
- wr_clk = (hd_read_reg(P_VPU_HDMI_SETTING) & 0xf00) >> 8;
- if (mode) {
- hd_write_reg(P_ENCP_VIDEO_EN, 0);
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 0, 2); /*[ 0] src_sel_enci: Disable ENCP output to HDMI*/
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 8, 4); /*[ 0] src_sel_enci: Disable ENCP output to HDMI*/
- mdelay(1);
- hd_write_reg(P_ENCP_VIDEO_EN, 1);
- mdelay(1);
- hd_set_reg_bits(P_VPU_HDMI_SETTING, wr_clk, 8, 4);
- mdelay(1);
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 2, 0, 2); /*[ 0] src_sel_enci: Enable ENCP output to HDMI*/
- } else {
- hd_write_reg(P_ENCI_VIDEO_EN, 0);
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 0, 2); /*[ 0] src_sel_enci: Disable ENCI output to HDMI*/
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 8, 4); /*[ 0] src_sel_enci: Disable ENCP output to HDMI*/
- mdelay(1);
- hd_write_reg(P_ENCI_VIDEO_EN, 1);
- mdelay(1);
- hd_set_reg_bits(P_VPU_HDMI_SETTING, wr_clk, 8, 4);
- mdelay(1);
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 0, 2); /*[ 0] src_sel_enci: Enable ENCI output to HDMI*/
- }
-}
-
-static void hdmi_tvenc1080i_set(enum hdmi_vic vic)
-{
- unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2;
- unsigned long TOTAL_PIXELS = 0, PIXEL_REPEAT_HDMI = 0,
- PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 0;
- unsigned FRONT_PORCH = 88, HSYNC_PIXELS = 0, ACTIVE_LINES = 0,
- INTERLACE_MODE = 0, TOTAL_LINES = 0, SOF_LINES = 0,
- VSYNC_LINES = 0;
- unsigned LINES_F0 = 0, LINES_F1 = 563, BACK_PORCH = 0;
-
- unsigned long total_pixels_venc = 0;
- unsigned long active_pixels_venc = 0;
- unsigned long front_porch_venc = 0;
- unsigned long hsync_pixels_venc = 0;
-
- unsigned long de_h_begin = 0, de_h_end = 0;
- unsigned long de_v_begin_even = 0, de_v_end_even = 0,
- de_v_begin_odd = 0, de_v_end_odd = 0;
- unsigned long hs_begin = 0, hs_end = 0;
- unsigned long vs_adjust = 0;
- unsigned long vs_bline_evn = 0, vs_eline_evn = 0,
- vs_bline_odd = 0, vs_eline_odd = 0;
- unsigned long vso_begin_evn = 0, vso_begin_odd = 0;
-
- if ((vic == HDMI_1920x1080i60_16x9) ||
- (vic == HDMI_1920x1080i120_16x9)) {
- INTERLACE_MODE = 1;
- PIXEL_REPEAT_VENC = 1;
- PIXEL_REPEAT_HDMI = 0;
- ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI));
- ACTIVE_LINES = (1080/(1+INTERLACE_MODE));
- LINES_F0 = 562;
- LINES_F1 = 563;
- FRONT_PORCH = 88;
- HSYNC_PIXELS = 44;
- BACK_PORCH = 148;
- VSYNC_LINES = 5;
- SOF_LINES = 15;
- } else if ((vic == HDMI_1920x1080i50_16x9) ||
- (vic == HDMI_1920x1080i100_16x9)) {
- INTERLACE_MODE = 1;
- PIXEL_REPEAT_VENC = 1;
- PIXEL_REPEAT_HDMI = 0;
- ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI));
- ACTIVE_LINES = (1080/(1+INTERLACE_MODE));
- LINES_F0 = 562;
- LINES_F1 = 563;
- FRONT_PORCH = 528;
- HSYNC_PIXELS = 44;
- BACK_PORCH = 148;
- VSYNC_LINES = 5;
- SOF_LINES = 15;
- }
- TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS);
- TOTAL_LINES = (LINES_F0+(LINES_F1*INTERLACE_MODE));
-
- total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
- (1+PIXEL_REPEAT_VENC);
- active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
- (1+PIXEL_REPEAT_VENC);
- front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) *
- (1+PIXEL_REPEAT_VENC);
- hsync_pixels_venc =
- (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) * (1+PIXEL_REPEAT_VENC);
-
- hd_write_reg(P_ENCP_VIDEO_MODE, hd_read_reg(P_ENCP_VIDEO_MODE)|(1<<14));
-
- /* Program DE timing */
- de_h_begin = modulo(hd_read_reg(P_ENCP_VIDEO_HAVON_BEGIN) +
- VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc);
- de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc);
- hd_write_reg(P_ENCP_DE_H_BEGIN, de_h_begin);
- hd_write_reg(P_ENCP_DE_H_END, de_h_end);
- /* Program DE timing for even field */
- de_v_begin_even = hd_read_reg(P_ENCP_VIDEO_VAVON_BLINE);
- de_v_end_even = de_v_begin_even + ACTIVE_LINES;
- hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even);
- hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even);
- /* Program DE timing for odd field if needed */
- if (INTERLACE_MODE) {
- de_v_begin_odd = to_signed((
- hd_read_reg(P_ENCP_VIDEO_OFLD_VOAV_OFST) & 0xf0)>>4)
- + de_v_begin_even + (TOTAL_LINES-1)/2;
- de_v_end_odd = de_v_begin_odd + ACTIVE_LINES;
- hd_write_reg(P_ENCP_DE_V_BEGIN_ODD, de_v_begin_odd);/* 583 */
- hd_write_reg(P_ENCP_DE_V_END_ODD, de_v_end_odd); /* 1123 */
- }
-
- /* Program Hsync timing */
- if (de_h_end + front_porch_venc >= total_pixels_venc) {
- hs_begin = de_h_end + front_porch_venc - total_pixels_venc;
- vs_adjust = 1;
- } else {
- hs_begin = de_h_end + front_porch_venc;
- vs_adjust = 0;
- }
- hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc);
- hd_write_reg(P_ENCP_DVI_HSO_BEGIN, hs_begin);
- hd_write_reg(P_ENCP_DVI_HSO_END, hs_end);
-
- /* Program Vsync timing for even field */
- if (de_v_begin_even >= SOF_LINES + VSYNC_LINES + (1-vs_adjust))
- vs_bline_evn = de_v_begin_even - SOF_LINES - VSYNC_LINES
- - (1-vs_adjust);
- else
- vs_bline_evn = TOTAL_LINES + de_v_begin_even - SOF_LINES
- - VSYNC_LINES - (1-vs_adjust);
-
- vs_eline_evn = modulo(vs_bline_evn + VSYNC_LINES, TOTAL_LINES);
- hd_write_reg(P_ENCP_DVI_VSO_BLINE_EVN, vs_bline_evn); /* 0 */
- hd_write_reg(P_ENCP_DVI_VSO_ELINE_EVN, vs_eline_evn); /* 5 */
- vso_begin_evn = hs_begin; /* 2 */
- hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn); /* 2 */
- hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn); /* 2 */
- /* Program Vsync timing for odd field if needed */
- if (INTERLACE_MODE) {
- vs_bline_odd = de_v_begin_odd-1 - SOF_LINES - VSYNC_LINES;
- vs_eline_odd = de_v_begin_odd-1 - SOF_LINES;
- vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1),
- total_pixels_venc);
- hd_write_reg(P_ENCP_DVI_VSO_BLINE_ODD, vs_bline_odd);
- hd_write_reg(P_ENCP_DVI_VSO_ELINE_ODD, vs_eline_odd);
- hd_write_reg(P_ENCP_DVI_VSO_BEGIN_ODD, vso_begin_odd);
- hd_write_reg(P_ENCP_DVI_VSO_END_ODD, vso_begin_odd);
- }
-
- hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
- (0 << 1) |
- (HSYNC_POLARITY << 2) |
- (VSYNC_POLARITY << 3) |
- (0 << 4) |
- (4 << 5) |
- (0 << 8) |
- (0 << 12)
- );
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
-
-}
-
-static void hdmi_tvenc4k2k_set(enum hdmi_vic vic)
-{
- unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2;
- unsigned long TOTAL_PIXELS = 4400, PIXEL_REPEAT_HDMI = 0,
- PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 3840;
- unsigned FRONT_PORCH = 1020, HSYNC_PIXELS = 0, ACTIVE_LINES = 2160,
- INTERLACE_MODE = 0, TOTAL_LINES = 0, SOF_LINES = 0,
- VSYNC_LINES = 0;
- unsigned LINES_F0 = 2250, LINES_F1 = 2250, BACK_PORCH = 0;
-
- unsigned long total_pixels_venc = 0;
- unsigned long active_pixels_venc = 0;
- unsigned long front_porch_venc = 0;
- unsigned long hsync_pixels_venc = 0;
-
- unsigned long de_h_begin = 0, de_h_end = 0;
- unsigned long de_v_begin_even = 0, de_v_end_even = 0,
- de_v_begin_odd = 0, de_v_end_odd = 0;
- unsigned long hs_begin = 0, hs_end = 0;
- unsigned long vs_adjust = 0;
- unsigned long vs_bline_evn = 0, vs_eline_evn = 0, vs_bline_odd = 0,
- vs_eline_odd = 0;
- unsigned long vso_begin_evn = 0, vso_begin_odd = 0;
-
- switch (vic) {
- case HDMI_3840x2160p30_16x9:
- case HDMI_3840x2160p60_16x9:
- case HDMI_3840x2160p60_16x9_Y420:
- INTERLACE_MODE = 0;
- PIXEL_REPEAT_VENC = 0;
- PIXEL_REPEAT_HDMI = 0;
- ACTIVE_PIXELS = (3840*(1+PIXEL_REPEAT_HDMI));
- ACTIVE_LINES = (2160/(1+INTERLACE_MODE));
- LINES_F0 = 2250;
- LINES_F1 = 2250;
- FRONT_PORCH = 176;
- HSYNC_PIXELS = 88;
- BACK_PORCH = 296;
- VSYNC_LINES = 10;
- SOF_LINES = 72 + 1;
- break;
- case HDMI_3840x2160p25_16x9:
- case HDMI_3840x2160p50_16x9:
- case HDMI_3840x2160p50_16x9_Y420:
- INTERLACE_MODE = 0;
- PIXEL_REPEAT_VENC = 0;
- PIXEL_REPEAT_HDMI = 0;
- ACTIVE_PIXELS = (3840*(1+PIXEL_REPEAT_HDMI));
- ACTIVE_LINES = (2160/(1+INTERLACE_MODE));
- LINES_F0 = 2250;
- LINES_F1 = 2250;
- FRONT_PORCH = 1056;
- HSYNC_PIXELS = 88;
- BACK_PORCH = 296;
- VSYNC_LINES = 10;
- SOF_LINES = 72 + 1;
- break;
- case HDMI_3840x2160p24_16x9:
- INTERLACE_MODE = 0;
- PIXEL_REPEAT_VENC = 0;
- PIXEL_REPEAT_HDMI = 0;
- ACTIVE_PIXELS = (3840*(1+PIXEL_REPEAT_HDMI));
- ACTIVE_LINES = (2160/(1+INTERLACE_MODE));
- LINES_F0 = 2250;
- LINES_F1 = 2250;
- FRONT_PORCH = 1276;
- HSYNC_PIXELS = 88;
- BACK_PORCH = 296;
- VSYNC_LINES = 10;
- SOF_LINES = 72 + 1;
- break;
- case HDMI_4096x2160p24_256x135:
- INTERLACE_MODE = 0;
- PIXEL_REPEAT_VENC = 0;
- PIXEL_REPEAT_HDMI = 0;
- ACTIVE_PIXELS = (4096*(1+PIXEL_REPEAT_HDMI));
- ACTIVE_LINES = (2160/(1+INTERLACE_MODE));
- LINES_F0 = 2250;
- LINES_F1 = 2250;
- FRONT_PORCH = 1020;
- HSYNC_PIXELS = 88;
- BACK_PORCH = 296;
- VSYNC_LINES = 10;
- SOF_LINES = 72 + 1;
- break;
- case HDMI_4096x2160p25_256x135:
- case HDMI_4096x2160p50_256x135:
- case HDMI_4096x2160p50_256x135_Y420:
- INTERLACE_MODE = 0;
- PIXEL_REPEAT_VENC = 0;
- PIXEL_REPEAT_HDMI = 0;
- ACTIVE_PIXELS = (4096*(1+PIXEL_REPEAT_HDMI));
- ACTIVE_LINES = (2160/(1+INTERLACE_MODE));
- LINES_F0 = 2250;
- LINES_F1 = 2250;
- FRONT_PORCH = 968;
- HSYNC_PIXELS = 88;
- BACK_PORCH = 128;
- VSYNC_LINES = 10;
- SOF_LINES = 72;
- break;
- case HDMI_4096x2160p30_256x135:
- case HDMI_4096x2160p60_256x135:
- case HDMI_4096x2160p60_256x135_Y420:
- INTERLACE_MODE = 0;
- PIXEL_REPEAT_VENC = 0;
- PIXEL_REPEAT_HDMI = 0;
- ACTIVE_PIXELS = (4096*(1+PIXEL_REPEAT_HDMI));
- ACTIVE_LINES = (2160/(1+INTERLACE_MODE));
- LINES_F0 = 2250;
- LINES_F1 = 2250;
- FRONT_PORCH = 88;
- HSYNC_PIXELS = 88;
- BACK_PORCH = 128;
- VSYNC_LINES = 10;
- SOF_LINES = 72;
- break;
- default:
- printk("hdmitx20: no setting for VIC = %d\n", vic);
- break;
- }
-
- TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS);
- TOTAL_LINES = (LINES_F0+(LINES_F1*INTERLACE_MODE));
-
- total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
- (1+PIXEL_REPEAT_VENC);
- active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
- (1+PIXEL_REPEAT_VENC);
- front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) *
- (1+PIXEL_REPEAT_VENC);
- hsync_pixels_venc = (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
- (1+PIXEL_REPEAT_VENC);
-
- de_h_begin = modulo(hd_read_reg(P_ENCP_VIDEO_HAVON_BEGIN) +
- VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc);
- de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc);
- hd_write_reg(P_ENCP_DE_H_BEGIN, de_h_begin);
- hd_write_reg(P_ENCP_DE_H_END, de_h_end);
- /* Program DE timing for even field */
- de_v_begin_even = hd_read_reg(P_ENCP_VIDEO_VAVON_BLINE);
- de_v_end_even = modulo(de_v_begin_even + ACTIVE_LINES, TOTAL_LINES);
- hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even);
- hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even);
- /* Program DE timing for odd field if needed */
- if (INTERLACE_MODE) {
- de_v_begin_odd = to_signed(
- (hd_read_reg(P_ENCP_VIDEO_OFLD_VOAV_OFST) & 0xf0)>>4)
- + de_v_begin_even + (TOTAL_LINES-1)/2;
- de_v_end_odd = modulo(de_v_begin_odd + ACTIVE_LINES,
- TOTAL_LINES);
- hd_write_reg(P_ENCP_DE_V_BEGIN_ODD, de_v_begin_odd);
- hd_write_reg(P_ENCP_DE_V_END_ODD, de_v_end_odd);
- }
-
- /* Program Hsync timing */
- if (de_h_end + front_porch_venc >= total_pixels_venc) {
- hs_begin = de_h_end + front_porch_venc - total_pixels_venc;
- vs_adjust = 1;
- } else {
- hs_begin = de_h_end + front_porch_venc;
- vs_adjust = 1;
- }
- hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc);
- hd_write_reg(P_ENCP_DVI_HSO_BEGIN, hs_begin);
- hd_write_reg(P_ENCP_DVI_HSO_END, hs_end);
-
- /* Program Vsync timing for even field */
- if (de_v_begin_even >= SOF_LINES + VSYNC_LINES + (1-vs_adjust))
- vs_bline_evn = de_v_begin_even - SOF_LINES - VSYNC_LINES
- - (1-vs_adjust);
- else
- vs_bline_evn = TOTAL_LINES + de_v_begin_even - SOF_LINES
- - VSYNC_LINES - (1-vs_adjust);
- vs_eline_evn = modulo(vs_bline_evn + VSYNC_LINES, TOTAL_LINES);
- hd_write_reg(P_ENCP_DVI_VSO_BLINE_EVN, vs_bline_evn);
- hd_write_reg(P_ENCP_DVI_VSO_ELINE_EVN, vs_eline_evn);
- vso_begin_evn = hs_begin;
- hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn);
- hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn);
- /* Program Vsync timing for odd field if needed */
- if (INTERLACE_MODE) {
- vs_bline_odd = de_v_begin_odd-1 - SOF_LINES - VSYNC_LINES;
- vs_eline_odd = de_v_begin_odd-1 - SOF_LINES;
- vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1),
- total_pixels_venc);
- hd_write_reg(P_ENCP_DVI_VSO_BLINE_ODD, vs_bline_odd);
- hd_write_reg(P_ENCP_DVI_VSO_ELINE_ODD, vs_eline_odd);
- hd_write_reg(P_ENCP_DVI_VSO_BEGIN_ODD, vso_begin_odd);
- hd_write_reg(P_ENCP_DVI_VSO_END_ODD, vso_begin_odd);
- }
- hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
- (0 << 1) |
- (HSYNC_POLARITY << 2) |
- (VSYNC_POLARITY << 3) |
- (0 << 4) |
- (4 << 5) |
- (0 << 8) |
- (0 << 12)
- );
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
- hd_write_reg(P_ENCP_VIDEO_EN, 1);
-}
-
-static void hdmi_tvenc480i_set(enum hdmi_vic vic)
-{
- unsigned long VFIFO2VD_TO_HDMI_LATENCY = 1;
- unsigned long TOTAL_PIXELS = 0, PIXEL_REPEAT_HDMI = 0,
- PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 0;
- unsigned FRONT_PORCH = 38, HSYNC_PIXELS = 124, ACTIVE_LINES = 0,
- INTERLACE_MODE = 0, VSYNC_LINES = 0;
- unsigned LINES_F0 = 262, LINES_F1 = 263, BACK_PORCH = 114,
- EOF_LINES = 2;
-
- unsigned long total_pixels_venc = 0;
- unsigned long active_pixels_venc = 0;
- unsigned long front_porch_venc = 0;
- unsigned long hsync_pixels_venc = 0;
-
- unsigned long de_h_begin = 0, de_h_end = 0;
- unsigned long de_v_begin_even = 0, de_v_end_even = 0,
- de_v_begin_odd = 0, de_v_end_odd = 0;
- unsigned long hs_begin = 0, hs_end = 0;
- unsigned long vs_adjust = 0;
- unsigned long vs_bline_evn = 0, vs_eline_evn = 0,
- vs_bline_odd = 0, vs_eline_odd = 0;
- unsigned long vso_begin_evn = 0, vso_begin_odd = 0;
-
- hd_set_reg_bits(P_HHI_GCLK_OTHER, 1, 8, 1);
- switch (vic) {
- case HDMI_720x480i60_16x9:
- INTERLACE_MODE = 1;
- PIXEL_REPEAT_VENC = 1;
- PIXEL_REPEAT_HDMI = 1;
- ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI));
- ACTIVE_LINES = (480/(1+INTERLACE_MODE));
- LINES_F0 = 262;
- LINES_F1 = 263;
- FRONT_PORCH = 38;
- HSYNC_PIXELS = 124;
- BACK_PORCH = 114;
- EOF_LINES = 4;
- VSYNC_LINES = 3;
- break;
- case HDMI_720x576i50_16x9:
- INTERLACE_MODE = 1;
- PIXEL_REPEAT_VENC = 1;
- PIXEL_REPEAT_HDMI = 1;
- ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI));
- ACTIVE_LINES = (576/(1+INTERLACE_MODE));
- LINES_F0 = 312;
- LINES_F1 = 313;
- FRONT_PORCH = 24;
- HSYNC_PIXELS = 126;
- BACK_PORCH = 138;
- EOF_LINES = 2;
- VSYNC_LINES = 3;
- break;
- default:
- break;
- }
-
- TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS);
-
- total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
- (1+PIXEL_REPEAT_VENC); /* 1716 / 2 * 2 = 1716 */
- active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
- (1+PIXEL_REPEAT_VENC);
- front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) *
- (1+PIXEL_REPEAT_VENC); /* 38 / 2 * 2 = 38 */
- hsync_pixels_venc = (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
- (1+PIXEL_REPEAT_VENC); /* 124 / 2 * 2 = 124 */
-
- de_h_begin = modulo(hd_read_reg(P_ENCI_VFIFO2VD_PIXEL_START) +
- VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc);
- de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc);
- hd_write_reg(P_ENCI_DE_H_BEGIN, de_h_begin); /* 235 */
- hd_write_reg(P_ENCI_DE_H_END, de_h_end); /* 1675 */
-
- de_v_begin_even = hd_read_reg(P_ENCI_VFIFO2VD_LINE_TOP_START);
- de_v_end_even = de_v_begin_even + ACTIVE_LINES;
- de_v_begin_odd = hd_read_reg(P_ENCI_VFIFO2VD_LINE_BOT_START);
- de_v_end_odd = de_v_begin_odd + ACTIVE_LINES;
- hd_write_reg(P_ENCI_DE_V_BEGIN_EVEN, de_v_begin_even);
- hd_write_reg(P_ENCI_DE_V_END_EVEN, de_v_end_even);
- hd_write_reg(P_ENCI_DE_V_BEGIN_ODD, de_v_begin_odd);
- hd_write_reg(P_ENCI_DE_V_END_ODD, de_v_end_odd);
-
- /* Program Hsync timing */
- if (de_h_end + front_porch_venc >= total_pixels_venc) {
- hs_begin = de_h_end + front_porch_venc - total_pixels_venc;
- vs_adjust = 1;
- } else {
- hs_begin = de_h_end + front_porch_venc;
- vs_adjust = 0;
- }
- hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc);
- hd_write_reg(P_ENCI_DVI_HSO_BEGIN, hs_begin); /* 1713 */
- hd_write_reg(P_ENCI_DVI_HSO_END, hs_end); /* 121 */
-
- /* Program Vsync timing for even field */
- if (de_v_end_odd-1 + EOF_LINES + vs_adjust >= LINES_F1) {
- vs_bline_evn = de_v_end_odd-1 + EOF_LINES + vs_adjust
- - LINES_F1;
- vs_eline_evn = vs_bline_evn + VSYNC_LINES;
- hd_write_reg(P_ENCI_DVI_VSO_BLINE_EVN, vs_bline_evn);
- /* vso_bline_evn_reg_wr_cnt ++; */
- hd_write_reg(P_ENCI_DVI_VSO_ELINE_EVN, vs_eline_evn);
- /* vso_eline_evn_reg_wr_cnt ++; */
- hd_write_reg(P_ENCI_DVI_VSO_BEGIN_EVN, hs_begin);
- hd_write_reg(P_ENCI_DVI_VSO_END_EVN, hs_begin);
- } else {
- vs_bline_odd = de_v_end_odd-1 + EOF_LINES + vs_adjust;
- hd_write_reg(P_ENCI_DVI_VSO_BLINE_ODD, vs_bline_odd);
- /* vso_bline_odd_reg_wr_cnt ++; */
- hd_write_reg(P_ENCI_DVI_VSO_BEGIN_ODD, hs_begin);
- if (vs_bline_odd + VSYNC_LINES >= LINES_F1) {
- vs_eline_evn = vs_bline_odd + VSYNC_LINES - LINES_F1;
- hd_write_reg(P_ENCI_DVI_VSO_ELINE_EVN, vs_eline_evn);
- /* vso_eline_evn_reg_wr_cnt ++; */
- hd_write_reg(P_ENCI_DVI_VSO_END_EVN, hs_begin);
- } else {
- vs_eline_odd = vs_bline_odd + VSYNC_LINES;
- hd_write_reg(P_ENCI_DVI_VSO_ELINE_ODD, vs_eline_odd);
- /* vso_eline_odd_reg_wr_cnt ++; */
- hd_write_reg(P_ENCI_DVI_VSO_END_ODD, hs_begin);
- }
- }
- /* Program Vsync timing for odd field */
- if (de_v_end_even-1 + EOF_LINES + 1 >= LINES_F0) {
- vs_bline_odd = de_v_end_even-1 + EOF_LINES + 1 - LINES_F0;
- vs_eline_odd = vs_bline_odd + VSYNC_LINES;
- hd_write_reg(P_ENCI_DVI_VSO_BLINE_ODD, vs_bline_odd);
- /* vso_bline_odd_reg_wr_cnt ++; */
- hd_write_reg(P_ENCI_DVI_VSO_ELINE_ODD, vs_eline_odd);
- /* vso_eline_odd_reg_wr_cnt ++; */
- vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1),
- total_pixels_venc);
- hd_write_reg(P_ENCI_DVI_VSO_BEGIN_ODD, vso_begin_odd);
- hd_write_reg(P_ENCI_DVI_VSO_END_ODD, vso_begin_odd);
- } else {
- vs_bline_evn = de_v_end_even-1 + EOF_LINES + 1;
- hd_write_reg(P_ENCI_DVI_VSO_BLINE_EVN, vs_bline_evn); /* 261 */
- /* vso_bline_evn_reg_wr_cnt ++; */
- vso_begin_evn = modulo(hs_begin + (total_pixels_venc>>1),
- total_pixels_venc);
- hd_write_reg(P_ENCI_DVI_VSO_BEGIN_EVN, vso_begin_evn);
- if (vs_bline_evn + VSYNC_LINES >= LINES_F0) {
- vs_eline_odd = vs_bline_evn + VSYNC_LINES - LINES_F0;
- hd_write_reg(P_ENCI_DVI_VSO_ELINE_ODD, vs_eline_odd);
- /* vso_eline_odd_reg_wr_cnt ++; */
- hd_write_reg(P_ENCI_DVI_VSO_END_ODD, vso_begin_evn);
- } else {
- vs_eline_evn = vs_bline_evn + VSYNC_LINES;
- hd_write_reg(P_ENCI_DVI_VSO_ELINE_EVN, vs_eline_evn);
- /* vso_eline_evn_reg_wr_cnt ++; */
- hd_write_reg(P_ENCI_DVI_VSO_END_EVN, vso_begin_evn);
- }
- }
-
- hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
- (0 << 1) |
- (0 << 2) |
- (0 << 3) |
- (0 << 4) |
- (4 << 5) |
- (1 << 8) |
- (1 << 12)
- );
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 0, 1);
-}
-
-static void hdmi_tvenc_set_def(enum hdmi_vic vic)
-{
- unsigned long VFIFO2VD_TO_HDMI_LATENCY = 2;
- unsigned long TOTAL_PIXELS = 0, PIXEL_REPEAT_HDMI = 0,
- PIXEL_REPEAT_VENC = 0, ACTIVE_PIXELS = 0;
- unsigned FRONT_PORCH = 0, HSYNC_PIXELS = 0, ACTIVE_LINES = 0,
- INTERLACE_MODE = 0, TOTAL_LINES = 0, SOF_LINES = 0,
- VSYNC_LINES = 0;
- unsigned LINES_F0 = 0, LINES_F1 = 0, BACK_PORCH = 0;
-
- unsigned long total_pixels_venc = 0;
- unsigned long active_pixels_venc = 0;
- unsigned long front_porch_venc = 0;
- unsigned long hsync_pixels_venc = 0;
-
- unsigned long de_h_begin = 0, de_h_end = 0;
- unsigned long de_v_begin_even = 0, de_v_end_even = 0,
- de_v_begin_odd = 0, de_v_end_odd = 0;
- unsigned long hs_begin = 0, hs_end = 0;
- unsigned long vs_adjust = 0;
- unsigned long vs_bline_evn = 0, vs_eline_evn = 0,
- vs_bline_odd = 0, vs_eline_odd = 0;
- unsigned long vso_begin_evn = 0, vso_begin_odd = 0;
-
- switch (vic) {
- case HDMI_720x480p60_16x9:
- case HDMI_720x480p120_16x9:
- INTERLACE_MODE = 0;
- PIXEL_REPEAT_VENC = 1;
- PIXEL_REPEAT_HDMI = 0;
- ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI));
- ACTIVE_LINES = (480/(1+INTERLACE_MODE));
- LINES_F0 = 525;
- LINES_F1 = 525;
- FRONT_PORCH = 16;
- HSYNC_PIXELS = 62;
- BACK_PORCH = 60;
- VSYNC_LINES = 6;
- SOF_LINES = 30;
- break;
- case HDMI_720x576p50_16x9:
- case HDMI_720x576p100_16x9:
- INTERLACE_MODE = 0;
- PIXEL_REPEAT_VENC = 1;
- PIXEL_REPEAT_HDMI = 0;
- ACTIVE_PIXELS = (720*(1+PIXEL_REPEAT_HDMI));
- ACTIVE_LINES = (576/(1+INTERLACE_MODE));
- LINES_F0 = 625;
- LINES_F1 = 625;
- FRONT_PORCH = 12;
- HSYNC_PIXELS = 64;
- BACK_PORCH = 68;
- VSYNC_LINES = 5;
- SOF_LINES = 39;
- break;
- case HDMI_1280x720p60_16x9:
- case HDMI_1280x720p120_16x9:
- INTERLACE_MODE = 0;
- PIXEL_REPEAT_VENC = 1;
- PIXEL_REPEAT_HDMI = 0;
- ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI));
- ACTIVE_LINES = (720/(1+INTERLACE_MODE));
- LINES_F0 = 750;
- LINES_F1 = 750;
- FRONT_PORCH = 110;
- HSYNC_PIXELS = 40;
- BACK_PORCH = 220;
- VSYNC_LINES = 5;
- SOF_LINES = 20;
- break;
- case HDMI_1280x720p50_16x9:
- case HDMI_1280x720p100_16x9:
- INTERLACE_MODE = 0;
- PIXEL_REPEAT_VENC = 1;
- PIXEL_REPEAT_HDMI = 0;
- ACTIVE_PIXELS = (1280*(1+PIXEL_REPEAT_HDMI));
- ACTIVE_LINES = (720/(1+INTERLACE_MODE));
- LINES_F0 = 750;
- LINES_F1 = 750;
- FRONT_PORCH = 440;
- HSYNC_PIXELS = 40;
- BACK_PORCH = 220;
- VSYNC_LINES = 5;
- SOF_LINES = 20;
- break;
- case HDMI_1920x1080p50_16x9:
- case HDMI_1920x1080p25_16x9:
- case HDMI_1920x1080p100_16x9:
- INTERLACE_MODE = 0;
- PIXEL_REPEAT_VENC = 0;
- PIXEL_REPEAT_HDMI = 0;
- ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI));
- ACTIVE_LINES = (1080/(1+INTERLACE_MODE));
- LINES_F0 = 1125;
- LINES_F1 = 1125;
- FRONT_PORCH = 528;
- HSYNC_PIXELS = 44;
- BACK_PORCH = 148;
- VSYNC_LINES = 5;
- SOF_LINES = 36;
- break;
- case HDMI_1920x1080p24_16x9:
- INTERLACE_MODE = 0;
- PIXEL_REPEAT_VENC = 0;
- PIXEL_REPEAT_HDMI = 0;
- ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI));
- ACTIVE_LINES = (1080/(1+INTERLACE_MODE));
- LINES_F0 = 1125;
- LINES_F1 = 1125;
- FRONT_PORCH = 638;
- HSYNC_PIXELS = 44;
- BACK_PORCH = 148;
- VSYNC_LINES = 5;
- SOF_LINES = 36;
- break;
- case HDMI_1920x1080p60_16x9:
- case HDMI_1920x1080p30_16x9:
- case HDMI_1920x1080p120_16x9:
- INTERLACE_MODE = 0;
- PIXEL_REPEAT_VENC = 0;
- PIXEL_REPEAT_HDMI = 0;
- ACTIVE_PIXELS = (1920*(1+PIXEL_REPEAT_HDMI));
- ACTIVE_LINES = (1080/(1+INTERLACE_MODE));
- LINES_F0 = 1125;
- LINES_F1 = 1125;
- FRONT_PORCH = 88;
- HSYNC_PIXELS = 44;
- BACK_PORCH = 148;
- VSYNC_LINES = 5;
- SOF_LINES = 36;
- break;
- default:
- break;
- }
-
- TOTAL_PIXELS = (FRONT_PORCH+HSYNC_PIXELS+BACK_PORCH+ACTIVE_PIXELS);
- TOTAL_LINES = (LINES_F0+(LINES_F1*INTERLACE_MODE));
-
- total_pixels_venc = (TOTAL_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
- (1+PIXEL_REPEAT_VENC);
- active_pixels_venc = (ACTIVE_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
- (1+PIXEL_REPEAT_VENC);
- front_porch_venc = (FRONT_PORCH / (1+PIXEL_REPEAT_HDMI)) *
- (1+PIXEL_REPEAT_VENC);
- hsync_pixels_venc = (HSYNC_PIXELS / (1+PIXEL_REPEAT_HDMI)) *
- (1+PIXEL_REPEAT_VENC);
-
- hd_write_reg(P_ENCP_VIDEO_MODE, hd_read_reg(P_ENCP_VIDEO_MODE)|(1<<14));
- /* Program DE timing */
- de_h_begin = modulo(hd_read_reg(P_ENCP_VIDEO_HAVON_BEGIN) +
- VFIFO2VD_TO_HDMI_LATENCY, total_pixels_venc);
- de_h_end = modulo(de_h_begin + active_pixels_venc, total_pixels_venc);
- hd_write_reg(P_ENCP_DE_H_BEGIN, de_h_begin); /* 220 */
- hd_write_reg(P_ENCP_DE_H_END, de_h_end); /* 1660 */
- /* Program DE timing for even field */
- de_v_begin_even = hd_read_reg(P_ENCP_VIDEO_VAVON_BLINE);
- de_v_end_even = de_v_begin_even + ACTIVE_LINES;
- hd_write_reg(P_ENCP_DE_V_BEGIN_EVEN, de_v_begin_even);
- hd_write_reg(P_ENCP_DE_V_END_EVEN, de_v_end_even); /* 522 */
- /* Program DE timing for odd field if needed */
- if (INTERLACE_MODE) {
- de_v_begin_odd = to_signed(
- (hd_read_reg(P_ENCP_VIDEO_OFLD_VOAV_OFST)
- & 0xf0)>>4) + de_v_begin_even + (TOTAL_LINES-1)/2;
- de_v_end_odd = de_v_begin_odd + ACTIVE_LINES;
- hd_write_reg(P_ENCP_DE_V_BEGIN_ODD, de_v_begin_odd);
- hd_write_reg(P_ENCP_DE_V_END_ODD, de_v_end_odd);
- }
-
- /* Program Hsync timing */
- if (de_h_end + front_porch_venc >= total_pixels_venc) {
- hs_begin = de_h_end + front_porch_venc - total_pixels_venc;
- vs_adjust = 1;
- } else {
- hs_begin = de_h_end + front_porch_venc;
- vs_adjust = 0;
- }
- hs_end = modulo(hs_begin + hsync_pixels_venc, total_pixels_venc);
- hd_write_reg(P_ENCP_DVI_HSO_BEGIN, hs_begin);
- hd_write_reg(P_ENCP_DVI_HSO_END, hs_end);
-
- /* Program Vsync timing for even field */
- if (de_v_begin_even >= SOF_LINES + VSYNC_LINES + (1-vs_adjust))
- vs_bline_evn = de_v_begin_even - SOF_LINES - VSYNC_LINES -
- (1-vs_adjust);
- else
- vs_bline_evn = TOTAL_LINES + de_v_begin_even - SOF_LINES -
- VSYNC_LINES - (1-vs_adjust);
- vs_eline_evn = modulo(vs_bline_evn + VSYNC_LINES, TOTAL_LINES);
- hd_write_reg(P_ENCP_DVI_VSO_BLINE_EVN, vs_bline_evn); /* 5 */
- hd_write_reg(P_ENCP_DVI_VSO_ELINE_EVN, vs_eline_evn); /* 11 */
- vso_begin_evn = hs_begin; /* 1692 */
- hd_write_reg(P_ENCP_DVI_VSO_BEGIN_EVN, vso_begin_evn); /* 1692 */
- hd_write_reg(P_ENCP_DVI_VSO_END_EVN, vso_begin_evn); /* 1692 */
- /* Program Vsync timing for odd field if needed */
- if (INTERLACE_MODE) {
- vs_bline_odd = de_v_begin_odd-1 - SOF_LINES - VSYNC_LINES;
- vs_eline_odd = de_v_begin_odd-1 - SOF_LINES;
- vso_begin_odd = modulo(hs_begin + (total_pixels_venc>>1),
- total_pixels_venc);
- hd_write_reg(P_ENCP_DVI_VSO_BLINE_ODD, vs_bline_odd);
- hd_write_reg(P_ENCP_DVI_VSO_ELINE_ODD, vs_eline_odd);
- hd_write_reg(P_ENCP_DVI_VSO_BEGIN_ODD, vso_begin_odd);
- hd_write_reg(P_ENCP_DVI_VSO_END_ODD, vso_begin_odd);
- }
- switch (vic) {
- case HDMI_720x480i60_16x9:
- case HDMI_720x576i50_16x9:
- hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
- (0 << 1) |
- (0 << 2) |
- (0 << 3) |
- (0 << 4) |
- (4 << 5) |
- (1 << 8) |
- (1 << 12)
- );
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 0, 1);
- break;
- case HDMI_1920x1080i60_16x9:
- case HDMI_1920x1080i50_16x9:
- hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
- (0 << 1) |
- (HSYNC_POLARITY << 2) |
- (VSYNC_POLARITY << 3) |
- (0 << 4) |
- (((TX_INPUT_COLOR_FORMAT == 0) ? 1 : 0) << 5) |
- (1 << 8) |
- (0 << 12)
- );
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
- break;
- case HDMI_3840x2160p30_16x9:
- case HDMI_3840x2160p25_16x9:
- case HDMI_3840x2160p24_16x9:
- case HDMI_4096x2160p24_256x135:
- case HDMI_4096x2160p25_256x135:
- case HDMI_4096x2160p30_256x135:
- case HDMI_4096x2160p50_256x135:
- case HDMI_4096x2160p60_256x135:
- case HDMI_3840x2160p50_16x9:
- case HDMI_3840x2160p60_16x9:
- hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
- (0 << 1) |
- (HSYNC_POLARITY << 2) |
- (VSYNC_POLARITY << 3) |
- (0 << 4) |
- (4 << 5) |
- (0 << 8) |
- (0 << 12)
- );
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
- hd_write_reg(P_ENCP_VIDEO_EN, 1); /* Enable VENC */
- break;
- case HDMI_720x480p60_16x9:
- case HDMI_720x576p50_16x9:
- case HDMI_720x480p120_16x9:
- case HDMI_720x576p100_16x9:
- hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
- (0 << 1) |
- (0 << 2) |
- (0 << 3) |
- (0 << 4) |
- (4 << 5) |
- (1 << 8) |
- (0 << 12)
- );
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
- break;
- case HDMI_1280x720p60_16x9:
- case HDMI_1280x720p50_16x9:
- case HDMI_1280x720p100_16x9:
- case HDMI_1280x720p120_16x9:
- hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
- (0 << 1) |
- (HSYNC_POLARITY << 2) |
- (VSYNC_POLARITY << 3) |
- (0 << 4) |
- (4 << 5) |
- (1 << 8) |
- (0 << 12)
- );
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
- break;
- default:
- hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) |
- (0 << 1) | /* [ 1] src_sel_encp */
- (HSYNC_POLARITY << 2) |
- (VSYNC_POLARITY << 3) |
- (0 << 4) |
- (4 << 5) |
- (0 << 8) |
- (0 << 12)
- );
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
- }
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1);
-}
-
-static void hdmi_tvenc_set(enum hdmi_vic vic)
-{
- switch (vic) {
- case HDMI_720x480i60_16x9:
- case HDMI_720x576i50_16x9:
- hdmi_tvenc480i_set(vic);
- break;
- case HDMI_1920x1080i60_16x9:
- case HDMI_1920x1080i50_16x9:
- case HDMI_1920x1080i100_16x9:
- case HDMI_1920x1080i120_16x9:
- hdmi_tvenc1080i_set(vic);
- break;
- case HDMI_3840x2160p30_16x9:
- case HDMI_3840x2160p25_16x9:
- case HDMI_3840x2160p24_16x9:
- case HDMI_4096x2160p24_256x135:
- case HDMI_4096x2160p25_256x135:
- case HDMI_4096x2160p30_256x135:
- case HDMI_4096x2160p50_256x135:
- case HDMI_4096x2160p60_256x135:
- case HDMI_3840x2160p50_16x9:
- case HDMI_3840x2160p60_16x9:
- case HDMI_4096x2160p50_256x135_Y420:
- case HDMI_4096x2160p60_256x135_Y420:
- case HDMI_3840x2160p50_16x9_Y420:
- case HDMI_3840x2160p60_16x9_Y420:
- hdmi_tvenc4k2k_set(vic);
- break;
- default:
- hdmi_tvenc_set_def(vic);
- break;
- }
-
- switch (vic) {
- case HDMI_720x480i60_16x9:
- case HDMI_720x576i50_16x9:
- /* Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/
- hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /* [ 0] src_sel_enci*/
- (0 << 1) | /* [ 1] src_sel_encp*/
- (0 << 2) | /* [ 2] inv_hsync. 1=Invert Hsync polarity.*/
- (0 << 3) | /* [ 3] inv_vsync. 1=Invert Vsync polarity.*/
- (0 << 4) | /* [ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/
- (4 << 5) | /* [ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/
- /* 0=output CrYCb(BRG);*/
- /* 1=output YCbCr(RGB);*/
- /* 2=output YCrCb(RBG);*/
- /* 3=output CbCrY(GBR);*/
- /* 4=output CbYCr(GRB);*/
- /* 5=output CrCbY(BGR);*/
- /* 6,7=Rsrv.*/
- (1 << 8) | /* [11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/
- (1 <<12) /* [15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/
- );
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 0, 1); // [ 0] src_sel_enci: Enable ENCI output to HDMI*/
- break;
- case HDMI_1920x1080i60_16x9:
- case HDMI_1920x1080i50_16x9:
- case HDMI_1920x1080i100_16x9:
- case HDMI_1920x1080i120_16x9:
- /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/
- hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/
- (0 << 1) | /*[ 1] src_sel_encp*/
- (HSYNC_POLARITY << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/
- (VSYNC_POLARITY << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/
- (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/
- (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/
- /* 0=output CrYCb(BRG);*/
- /* 1=output YCbCr(RGB);*/
- /* 2=output YCrCb(RBG);*/
- /* 3=output CbCrY(GBR);*/
- /* 4=output CbYCr(GRB);*/
- /* 5=output CrCbY(BGR);*/
- /* 6,7=Rsrv.*/
- (1 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/
- (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/
- );
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/
- break;
- case HDMI_3840x2160p30_16x9:
- case HDMI_3840x2160p25_16x9:
- case HDMI_3840x2160p24_16x9:
- case HDMI_4096x2160p24_256x135:
- case HDMI_4096x2160p25_256x135:
- case HDMI_4096x2160p30_256x135:
- case HDMI_4096x2160p50_256x135:
- case HDMI_4096x2160p60_256x135:
- case HDMI_3840x2160p50_16x9:
- case HDMI_3840x2160p60_16x9:
- hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/
- (0 << 1) | /*[ 1] src_sel_encp*/
- (HSYNC_POLARITY << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/
- (VSYNC_POLARITY << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/
- (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/
- (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/
- /* 0=output CrYCb(BRG);*/
- /* 1=output YCbCr(RGB);*/
- /* 2=output YCrCb(RBG);*/
- /* 3=output CbCrY(GBR);*/
- /* 4=output CbYCr(GRB);*/
- /* 5=output CrCbY(BGR);*/
- /* 6,7=Rsrv.*/
- (0 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/
- (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/
- );
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/
- hd_write_reg(P_ENCP_VIDEO_EN, 1); /*Enable VENC*/
- break;
- case HDMI_720x480p60_16x9:
- case HDMI_720x576p50_16x9:
- case HDMI_720x480p120_16x9:
- case HDMI_720x576p100_16x9:
- /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/
- hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/
- (0 << 1) | /*[ 1] src_sel_encp*/
- (0 << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/
- (0 << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/
- (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/
- (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/
- /* 0=output CrYCb(BRG);*/
- /* 1=output YCbCr(RGB);*/
- /* 2=output YCrCb(RBG);*/
- /* 3=output CbCrY(GBR);*/
- /* 4=output CbYCr(GRB);*/
- /* 5=output CrCbY(BGR);*/
- /* 6,7=Rsrv.*/
- (1 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/
- (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/
- );
- /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/
- break;
- case HDMI_1280x720p60_16x9:
- case HDMI_1280x720p50_16x9:
- case HDMI_1280x720p100_16x9:
- case HDMI_1280x720p120_16x9:
- /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/
- hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/
- (0 << 1) | /*[ 1] src_sel_encp*/
- (HSYNC_POLARITY << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/
- (VSYNC_POLARITY << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/
- (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/
- (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/
- /* 0=output CrYCb(BRG);*/
- /* 1=output YCbCr(RGB);*/
- /* 2=output YCrCb(RBG);*/
- /* 3=output CbCrY(GBR);*/
- /* 4=output CbYCr(GRB);*/
- /* 5=output CrCbY(BGR);*/
- /* 6,7=Rsrv.*/
- (1 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/
- (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/
- );
- /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/
- break;
- default:
- /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/
- hd_write_reg(P_VPU_HDMI_SETTING, (0 << 0) | /*[ 0] src_sel_enci*/
- (0 << 1) | /*[ 1] src_sel_encp*/
- (HSYNC_POLARITY << 2) | /*[ 2] inv_hsync. 1=Invert Hsync polarity.*/
- (VSYNC_POLARITY << 3) | /*[ 3] inv_vsync. 1=Invert Vsync polarity.*/
- (0 << 4) | /*[ 4] inv_dvi_clk. 1=Invert clock to external DVI, (clock invertion exists at internal HDMI).*/
- (4 << 5) | /*[ 7: 5] data_comp_map. Input data is CrYCb(BRG), map the output data to desired format:*/
- /* 0=output CrYCb(BRG);*/
- /* 1=output YCbCr(RGB);*/
- /* 2=output YCrCb(RBG);*/
- /* 3=output CbCrY(GBR);*/
- /* 4=output CbYCr(GRB);*/
- /* 5=output CrCbY(BGR);*/
- /* 6,7=Rsrv.*/
- (0 << 8) | /*[11: 8] wr_rate. 0=A write every clk1; 1=A write every 2 clk1; ...; 15=A write every 16 clk1.*/
- (0 <<12) /*[15:12] rd_rate. 0=A read every clk2; 1=A read every 2 clk2; ...; 15=A read every 16 clk2.*/
- );
- /*Annie 01Sep2011: Register VENC_DVI_SETTING and VENC_DVI_SETTING_MORE are no long valid, use VPU_HDMI_SETTING instead.*/
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 1, 1); /*[ 1] src_sel_encp: Enable ENCP output to HDMI*/
- }
-}
-
-static void mode420_half_horizontal_para(void)
-{
- unsigned int hactive = 0;
- unsigned int hblank = 0;
- unsigned int hfront = 0;
- unsigned int hsync = 0;
-
- printk("%s[%d]\n", __func__, __LINE__);
- hactive = hdmitx_rd_reg(HDMITX_DWC_FC_INHACTV0);
- hactive += (hdmitx_rd_reg(HDMITX_DWC_FC_INHACTV1) & 0x3f) << 8;
- hblank = hdmitx_rd_reg(HDMITX_DWC_FC_INHBLANK0);
- hblank += (hdmitx_rd_reg(HDMITX_DWC_FC_INHBLANK1) & 0x1f) << 8;
- hfront = hdmitx_rd_reg(HDMITX_DWC_FC_HSYNCINDELAY0);
- hfront += (hdmitx_rd_reg(HDMITX_DWC_FC_HSYNCINDELAY1) & 0x1f) << 8;
- hsync = hdmitx_rd_reg(HDMITX_DWC_FC_HSYNCINWIDTH0);
- hsync += (hdmitx_rd_reg(HDMITX_DWC_FC_HSYNCINWIDTH1) & 0x3) << 8;
-
- hactive = hactive / 2;
- hblank = hblank / 2;
- hfront = hfront / 2;
- hsync = hsync / 2;
-
- hdmitx_wr_reg(HDMITX_DWC_FC_INHACTV0, (hactive & 0xff));
- hdmitx_wr_reg(HDMITX_DWC_FC_INHACTV1, ((hactive >> 8) & 0x3f));
- hdmitx_wr_reg(HDMITX_DWC_FC_INHBLANK0, (hblank & 0xff));
- hdmitx_wr_reg(HDMITX_DWC_FC_INHBLANK1, ((hblank >> 8) & 0x1f));
- hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINDELAY0, (hfront & 0xff));
- hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINDELAY1, ((hfront >> 8) & 0x1f));
- hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINWIDTH0, (hsync & 0xff));
- hdmitx_wr_reg(HDMITX_DWC_FC_HSYNCINWIDTH1, ((hsync >> 8) & 0x3));
-}
-
-static void set_tmds_clk_div40(unsigned int div40)
-{
- if (div40 == 1) {
- hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_01, 0); /*[25:16] tmds_clk_pttn[19:10] [ 9: 0] tmds_clk_pttn[ 9: 0]*/
- hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_23, 0x03ff03ff); /*[25:16] tmds_clk_pttn[39:30] [ 9: 0] tmds_clk_pttn[29:20]*/
- } else {
- hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_01, 0x001f001f);
- hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_23, 0x001f001f);
- }
- hdmitx_set_reg_bits(HDMITX_DWC_FC_SCRAMBLER_CTRL, (div40 == 1) ? 1 : 0, 0, 1);
-
- hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x1); /*0xc*/
- msleep(2);
- hdmitx_wr_reg(HDMITX_TOP_TMDS_CLK_PTTN_CNTL, 0x2); /*0xc*/
- scdc_prepare((div40 == 1) ? 1:0);
-}
-
-static void hdmitx_set_vsi_pkt(enum hdmi_vic vic)
-{
- /* convert to HDMI_VIC */
- if (vic == HDMI_3840x2160p30_16x9)
- vic = 1;
- else if (vic == HDMI_3840x2160p25_16x9)
- vic = 2;
- else if (vic == HDMI_3840x2160p24_16x9)
- vic = 3;
- else
- vic = 4;
-
- hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID0, 0x03);
- hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID1, 0x0c);
- hdmitx_wr_reg(HDMITX_DWC_FC_VSDIEEEID2, 0x00);
- hdmitx_wr_reg(HDMITX_DWC_FC_AVIVID, 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD0, 0x20);
- hdmitx_wr_reg(HDMITX_DWC_FC_VSDPAYLOAD1, vic);
- hdmitx_wr_reg(HDMITX_DWC_FC_VSDSIZE, 5);
- hdmitx_set_reg_bits(HDMITX_DWC_FC_DATAUTO0, 1, 3, 1);
- hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO1, 0);
- hdmitx_wr_reg(HDMITX_DWC_FC_DATAUTO2, 0x10);
- hdmitx_set_reg_bits(HDMITX_DWC_FC_PACKET_TX_EN, 1, 4, 1);
-}
-
-/* record HDMITX current format */
-/* ISA_DEBUG_REG0 0x2600
- * bit[11]: Y420
- * bit[10:8]: HDMI VIC
- * bit[7:0]: CEA VIC
- */
-static void save_hdmitx_format(enum hdmi_vic vic, int y420)
-{
- unsigned int data32;
-
- data32 = vic & 0xff;
- data32 |= (hdmitx_rd_reg(HDMITX_DWC_FC_VSDPAYLOAD1) & 0x7) << 8;
- data32 |= (!!y420) << 11;
- hd_write_reg(P_ISA_DEBUG_REG0, data32);
-}
-
-static void hdmitx_set_vdac(unsigned int enable)
-{
- if (0 == enable)
- {
- hd_write_reg(P_HHI_VDAC_CNTL0, 0);
- hd_write_reg(P_HHI_VDAC_CNTL1, 8);
- }
- else if (1 == enable)
- {
- hd_write_reg(P_HHI_VDAC_CNTL0, 1);
- hd_write_reg(P_HHI_VDAC_CNTL1, 0);
- }
-
- return ;
-}
-
-static void hdmitx_set_hw(struct hdmitx_dev* hdev)
-{
- struct hdmi_format_para *para = NULL;
-
- para = hdmi_get_fmt_paras(hdev->vic);
- if (para == NULL) {
- printk("error at %s[%d]\n", __func__, __LINE__);
- return;
- }
- hdmitx_set_pll(hdev);
- hdmitx_set_phy(hdev);
- hdmitx_enc(hdev->vic);
- hdmitx_set_vdac(0);
-
- /* --------------------------------------------------------*/
- /* Set up HDMI*/
- /* --------------------------------------------------------*/
- config_hdmi20_tx(hdev->vic, para, /*pixel_repeat*/
- hdev->para->cd, /*Pixel bit width: 4=24-bit; 5=30-bit; 6=36-bit; 7=48-bit.*/
- TX_INPUT_COLOR_FORMAT, /*input_color_format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420.*/
- TX_INPUT_COLOR_RANGE, /*input_color_range: 0=limited; 1=full.*/
- hdev->para->cs, /*output_color_format: 0=RGB444; 1=YCbCr422; 2=YCbCr444; 3=YCbCr420.*/
- TX_OUTPUT_COLOR_RANGE /*output_color_range: 0=limited; 1=full.*/
- );
-
- /* switch HDMI_VIC for 2160p30/25/24hz */
- switch (hdev->vic) {
- case HDMI_3840x2160p24_16x9:
- case HDMI_3840x2160p25_16x9:
- case HDMI_3840x2160p30_16x9:
- case HDMI_4096x2160p24_256x135:
- hdmitx_set_vsi_pkt(hdev->vic);
- break;
- default:
- break;
- }
-
- /* Using ISA_DEBUG_REG0 to record HDMITX current format */
- save_hdmitx_format(hdev->vic, (hdev->para->cs == HDMI_COLOR_FORMAT_420));
-
- hd_write_reg(P_VPU_HDMI_FMT_CTRL,
- (((TX_INPUT_COLOR_FORMAT==HDMI_COLOR_FORMAT_420)?2:0) << 0) |
- /*[ 1: 0] hdmi_vid_fmt. 0=444; 1=convert to 422; 2=convert to 420.*/
- (2 << 2) | /*[ 3: 2] chroma_dnsmp. 0=use pixel 0; 1=use pixel 1; 2=use average.*/
- (0 << 4) | /*[ 4] dith_en. 1=enable dithering before HDMI TX input.*/
- (0 << 5) | /*[ 5] hdmi_dith_md: random noise selector.*/
- (0 << 6)); /*[ 9: 6] hdmi_dith10_cntl.*/
- if (hdev->para->cs == HDMI_COLOR_FORMAT_420) {
- hd_set_reg_bits(P_VPU_HDMI_FMT_CTRL, 2, 0, 2);
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 0, 4, 4);
- hd_set_reg_bits(P_VPU_HDMI_SETTING, 1, 8, 1);
- }
- switch (hdev->vic) {
- case HDMI_720x480i60_16x9:
- case HDMI_720x576i50_16x9:
- enc_vpu_bridge_reset(0);
- break;
- default:
- enc_vpu_bridge_reset(1);
- break;
- }
-
- if (hdev->para->cs == HDMI_COLOR_FORMAT_420)
- mode420_half_horizontal_para();
-
- switch (hdev->vic) {
- case HDMI_3840x2160p50_16x9:
- case HDMI_3840x2160p60_16x9:
- case HDMI_4096x2160p50_256x135:
- case HDMI_4096x2160p60_256x135:
- if ((hdev->para->cs == HDMI_COLOR_FORMAT_420)
- && (hdev->para->cd == HDMI_COLOR_DEPTH_24B))
- set_tmds_clk_div40(0);
- else
- set_tmds_clk_div40(1);
- break;
- case HDMI_3840x2160p50_16x9_Y420:
- case HDMI_3840x2160p60_16x9_Y420:
- case HDMI_4096x2160p50_256x135_Y420:
- case HDMI_4096x2160p60_256x135_Y420:
- if ((hdev->para->cs == HDMI_COLOR_FORMAT_420)
- && (hdev->para->cd == HDMI_COLOR_DEPTH_24B))
- set_tmds_clk_div40(0);
- else
- set_tmds_clk_div40(1);
- break;
- case HDMI_3840x2160p24_16x9:
- case HDMI_3840x2160p24_64x27:
- case HDMI_4096x2160p24_256x135:
- case HDMI_3840x2160p25_16x9:
- case HDMI_3840x2160p25_64x27:
- case HDMI_4096x2160p25_256x135:
- case HDMI_3840x2160p30_16x9:
- case HDMI_3840x2160p30_64x27:
- case HDMI_4096x2160p30_256x135:
- case HDMI_1920x1080p100_16x9:
- case HDMI_1920x1080p120_16x9:
- if ((hdev->para->cs == HDMI_COLOR_FORMAT_422)
- || (hdev->para->cd == HDMI_COLOR_DEPTH_24B))
- set_tmds_clk_div40(0);
- else
- set_tmds_clk_div40(1);
- break;
- default:
- set_tmds_clk_div40(0);
- break;
- }
- hdmitx_set_reg_bits(HDMITX_DWC_FC_INVIDCONF, 0, 3, 1);
- msleep(1);
- hdmitx_set_reg_bits(HDMITX_DWC_FC_INVIDCONF, 1, 3, 1);
-}
-
-/*Use this self-made function rather than %,
- *because % appears to produce wrong
- *value for divisor which are not 2's exponential.
- */
-static unsigned long modulo(unsigned long a, unsigned long b)
-{
- if (a >= b) {
- return(a-b);
- } else {
- return(a);
- }
-}
-
-static signed int to_signed(unsigned int a)
-{
- if (a <= 7) {
- return(a);
- } else {
- return(a-16);
- }
-}
-
-/*TODO*/
-static void hdmitx_csc_config (unsigned char input_color_format,
- unsigned char output_color_format,
- unsigned char color_depth)
-{
- unsigned char conv_en;
- unsigned long csc_coeff_a1, csc_coeff_a2, csc_coeff_a3, csc_coeff_a4;
- unsigned long csc_coeff_b1, csc_coeff_b2, csc_coeff_b3, csc_coeff_b4;
- unsigned long csc_coeff_c1, csc_coeff_c2, csc_coeff_c3, csc_coeff_c4;
- unsigned char csc_scale;
- unsigned long data32;
-
- conv_en = (((input_color_format == HDMI_COLOR_FORMAT_RGB) ||
- (output_color_format == HDMI_COLOR_FORMAT_RGB)) &&
- ( input_color_format != output_color_format))? 1 : 0;
-
- if (conv_en) {
- if (output_color_format == HDMI_COLOR_FORMAT_RGB) {
- csc_coeff_a1 = 0x2000;
- csc_coeff_a2 = 0x6926;
- csc_coeff_a3 = 0x74fd;
- csc_coeff_a4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x010e :
- (color_depth==HDMI_COLOR_DEPTH_30B)? 0x043b :
- (color_depth==HDMI_COLOR_DEPTH_36B)? 0x10ee :
- (color_depth==HDMI_COLOR_DEPTH_48B)? 0x10ee : 0x010e;
- csc_coeff_b1 = 0x2000;
- csc_coeff_b2 = 0x2cdd;
- csc_coeff_b3 = 0x0000;
- csc_coeff_b4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x7e9a :
- (color_depth==HDMI_COLOR_DEPTH_30B)? 0x7a65 :
- (color_depth==HDMI_COLOR_DEPTH_36B)? 0x6992 :
- (color_depth==HDMI_COLOR_DEPTH_48B)? 0x6992 : 0x7e9a;
- csc_coeff_c1 = 0x2000;
- csc_coeff_c2 = 0x0000;
- csc_coeff_c3 = 0x38b4;
- csc_coeff_c4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x7e3b :
- (color_depth==HDMI_COLOR_DEPTH_30B)? 0x78ea :
- (color_depth==HDMI_COLOR_DEPTH_36B)? 0x63a6 :
- (color_depth==HDMI_COLOR_DEPTH_48B)? 0x63a6 : 0x7e3b;
- csc_scale = 1;
- } else { /*input_color_format == HDMI_COLOR_FORMAT_RGB*/
- csc_coeff_a1 = 0x2591;
- csc_coeff_a2 = 0x1322;
- csc_coeff_a3 = 0x074b;
- csc_coeff_a4 = 0x0000;
- csc_coeff_b1 = 0x6535;
- csc_coeff_b2 = 0x2000;
- csc_coeff_b3 = 0x7acc;
- csc_coeff_b4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x0200 :
- (color_depth==HDMI_COLOR_DEPTH_30B)? 0x0800 :
- (color_depth==HDMI_COLOR_DEPTH_36B)? 0x2000 :
- (color_depth==HDMI_COLOR_DEPTH_48B)? 0x2000 : 0x0200;
- csc_coeff_c1 = 0x6acd;
- csc_coeff_c2 = 0x7534;
- csc_coeff_c3 = 0x2000;
- csc_coeff_c4 = (color_depth==HDMI_COLOR_DEPTH_24B)? 0x0200 :
- (color_depth==HDMI_COLOR_DEPTH_30B)? 0x0800 :
- (color_depth==HDMI_COLOR_DEPTH_36B)? 0x2000 :
- (color_depth==HDMI_COLOR_DEPTH_48B)? 0x2000 : 0x0200;
- csc_scale = 0;
- }
- } else {
- csc_coeff_a1 = 0x2000;
- csc_coeff_a2 = 0x0000;
- csc_coeff_a3 = 0x0000;
- csc_coeff_a4 = 0x0000;
- csc_coeff_b1 = 0x0000;
- csc_coeff_b2 = 0x2000;
- csc_coeff_b3 = 0x0000;
- csc_coeff_b4 = 0x0000;
- csc_coeff_c1 = 0x0000;
- csc_coeff_c2 = 0x0000;
- csc_coeff_c3 = 0x2000;
- csc_coeff_c4 = 0x0000;
- csc_scale = 1;
- }
-
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A1_MSB, (csc_coeff_a1>>8)&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A1_LSB, csc_coeff_a1&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A2_MSB, (csc_coeff_a2>>8)&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A2_LSB, csc_coeff_a2&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A3_MSB, (csc_coeff_a3>>8)&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A3_LSB, csc_coeff_a3&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A4_MSB, (csc_coeff_a4>>8)&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_A4_LSB, csc_coeff_a4&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B1_MSB, (csc_coeff_b1>>8)&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B1_LSB, csc_coeff_b1&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B2_MSB, (csc_coeff_b2>>8)&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B2_LSB, csc_coeff_b2&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B3_MSB, (csc_coeff_b3>>8)&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B3_LSB, csc_coeff_b3&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B4_MSB, (csc_coeff_b4>>8)&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_B4_LSB, csc_coeff_b4&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C1_MSB, (csc_coeff_c1>>8)&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C1_LSB, csc_coeff_c1&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C2_MSB, (csc_coeff_c2>>8)&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C2_LSB, csc_coeff_c2&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C3_MSB, (csc_coeff_c3>>8)&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C3_LSB, csc_coeff_c3&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C4_MSB, (csc_coeff_c4>>8)&0xff);
- hdmitx_wr_reg(HDMITX_DWC_CSC_COEF_C4_LSB, csc_coeff_c4&0xff);
-
- data32 = 0;
- data32 |= (color_depth << 4); /* [7:4] csc_color_depth*/
- data32 |= (csc_scale << 0); /* [1:0] cscscale*/
- hdmitx_wr_reg(HDMITX_DWC_CSC_SCALE, data32);
-} /* hdmitx_csc_config */
diff --git a/drivers/amlogic/media/vout/hdmitx/hdmitx_tvenc.c b/drivers/amlogic/media/vout/hdmitx/hdmitx_tvenc.c
deleted file mode 100644
index 06ca302..0000000
--- a/drivers/amlogic/media/vout/hdmitx/hdmitx_tvenc.c
+++ /dev/null
@@ -1,675 +0,0 @@
-/*
- * driver/amlogic/media/vout/hdmitx/hdmitx_tvenc.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#include <asm/arch/register.h>
-#include <asm/arch/secure_apb.h>
-
-#include "hdmitx_common.h"
-
-#define MREG_END_MARKER (volatile unsigned int *)0xFFFF
-
-static const struct reg_t tvregs_720p[] = {
- {P_ENCP_VIDEO_EN, 0},
- {P_ENCI_VIDEO_EN, 0},
-
- {P_VENC_DVI_SETTING, 0x2029},
- {P_ENCP_VIDEO_MODE, 0x4040},
- {P_ENCP_VIDEO_MODE_ADV, 0x0019},
- {P_ENCP_VIDEO_YFP1_HTIME, 648},
- {P_ENCP_VIDEO_YFP2_HTIME, 3207},
- {P_ENCP_VIDEO_MAX_PXCNT, 3299},
- {P_ENCP_VIDEO_HSPULS_BEGIN, 80},
- {P_ENCP_VIDEO_HSPULS_END, 240},
- {P_ENCP_VIDEO_HSPULS_SWITCH, 80},
- {P_ENCP_VIDEO_VSPULS_BEGIN, 688},
- {P_ENCP_VIDEO_VSPULS_END, 3248},
- {P_ENCP_VIDEO_VSPULS_BLINE, 4},
- {P_ENCP_VIDEO_VSPULS_ELINE, 8},
- {P_ENCP_VIDEO_HAVON_BEGIN, 648},
- {P_ENCP_VIDEO_HAVON_END, 3207},
- {P_ENCP_VIDEO_VAVON_BLINE, 29},
- {P_ENCP_VIDEO_VAVON_ELINE, 748},
- {P_ENCP_VIDEO_HSO_BEGIN, 256},
- {P_ENCP_VIDEO_HSO_END, 168},
- {P_ENCP_VIDEO_VSO_BEGIN, 168},
- {P_ENCP_VIDEO_VSO_END, 256},
- {P_ENCP_VIDEO_VSO_BLINE, 0},
- {P_ENCP_VIDEO_VSO_ELINE, 5},
- {P_ENCP_VIDEO_MAX_LNCNT, 749},
- {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
- {P_ENCP_VIDEO_EN, 1},
- {P_ENCI_VIDEO_EN, 0},
- {MREG_END_MARKER, 0},
-};
-
-static const struct reg_t tvregs_720p_50hz[] = {
- {P_ENCP_VIDEO_EN, 0},
- {P_ENCI_VIDEO_EN, 0},
- {P_VENC_DVI_SETTING, 0x202d},
- {P_ENCP_VIDEO_MAX_PXCNT, 3959},
- {P_ENCP_VIDEO_MAX_LNCNT, 749},
- {P_ENCP_VIDEO_HSPULS_BEGIN, 80},
- {P_ENCP_VIDEO_HSPULS_END, 240},
- {P_ENCP_VIDEO_HSPULS_SWITCH, 80},
- {P_ENCP_VIDEO_HAVON_BEGIN, 648},
- {P_ENCP_VIDEO_HAVON_END, 3207},
- {P_ENCP_VIDEO_HSO_BEGIN, 128},
- {P_ENCP_VIDEO_HSO_END, 208},
- {P_ENCP_VIDEO_VSPULS_BEGIN, 688},
- {P_ENCP_VIDEO_VSPULS_END, 3248},
- {P_ENCP_VIDEO_VSPULS_BLINE, 4},
- {P_ENCP_VIDEO_VSPULS_ELINE, 8},
- {P_ENCP_VIDEO_VAVON_BLINE, 29},
- {P_ENCP_VIDEO_VAVON_ELINE, 748},
- {P_ENCP_VIDEO_VSO_BEGIN, 128},
- {P_ENCP_VIDEO_VSO_END, 128},
- {P_ENCP_VIDEO_VSO_BLINE, 0},
- {P_ENCP_VIDEO_VSO_ELINE, 5},
- {P_ENCP_VIDEO_YFP1_HTIME, 648},
- {P_ENCP_VIDEO_YFP2_HTIME, 3207},
- {P_VENC_VIDEO_PROG_MODE, 0x100},
- {P_ENCP_VIDEO_MODE, 0x4040},
- {P_ENCP_VIDEO_MODE_ADV, 0x0019},
- {P_ENCP_VIDEO_SYNC_MODE, 0x407},
- {P_ENCP_VIDEO_YC_DLY, 0},
- {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
- {P_ENCP_VIDEO_EN, 1},
- {P_ENCI_VIDEO_EN, 0},
- {MREG_END_MARKER, 0},
-};
-
-static const struct reg_t tvregs_480i[] = {
- {P_ENCP_VIDEO_EN, 0},
- {P_ENCI_VIDEO_EN, 0},
- {P_ENCI_CFILT_CTRL, 0x12},
- {P_ENCI_CFILT_CTRL2, 0x12},
- {P_VENC_DVI_SETTING, 0},
- {P_ENCI_VIDEO_MODE, 0},
- {P_ENCI_VIDEO_MODE_ADV, 0},
- {P_ENCI_SYNC_HSO_BEGIN, 5},
- {P_ENCI_SYNC_HSO_END, 129},
- {P_ENCI_SYNC_VSO_EVNLN, 0x0003},
- {P_ENCI_SYNC_VSO_ODDLN, 0x0104},
- {P_ENCI_MACV_MAX_AMP, 0x810b},
- {P_VENC_VIDEO_PROG_MODE, 0xf0},
- {P_ENCI_VIDEO_MODE, 0x08},
- {P_ENCI_VIDEO_MODE_ADV, 0x26},
- {P_ENCI_VIDEO_SCH, 0x20},
- {P_ENCI_SYNC_MODE, 0x07},
- {P_ENCI_DBG_PX_RST, 0},
- {P_ENCI_VFIFO2VD_CTL, 0x4e01},
- {P_ENCI_VFIFO2VD_PIXEL_START, 0xf3,},
- {P_ENCI_VFIFO2VD_PIXEL_END, 0x0693,},
- {P_ENCI_VFIFO2VD_LINE_TOP_START, 0x12,},
- {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x102,},
- {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x13,},
- {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x103,},
- {P_VPU_VIU_VENC_MUX_CTRL, 0x5},
- {P_ENCP_VIDEO_EN, 0},
- {P_ENCI_VIDEO_EN, 1},
- {MREG_END_MARKER, 0},
-};
-
-static const struct reg_t tvregs_480p[] = {
- {P_ENCP_VIDEO_EN, 0},
- {P_ENCI_VIDEO_EN, 0},
- {P_ENCP_VIDEO_FILT_CTRL, 0x2052},
- {P_VENC_DVI_SETTING, 0x21},
- {P_ENCP_VIDEO_MODE, 0x4000},
- {P_ENCP_VIDEO_MODE_ADV, 9},
- {P_ENCP_VIDEO_YFP1_HTIME, 244},
- {P_ENCP_VIDEO_YFP2_HTIME, 1630},
- {P_ENCP_VIDEO_MAX_PXCNT, 1715},
- {P_ENCP_VIDEO_MAX_LNCNT, 524},
- {P_ENCP_VIDEO_HSPULS_BEGIN, 0x22},
- {P_ENCP_VIDEO_HSPULS_END, 0xa0},
- {P_ENCP_VIDEO_HSPULS_SWITCH, 88},
- {P_ENCP_VIDEO_VSPULS_BEGIN, 0},
- {P_ENCP_VIDEO_VSPULS_END, 1589},
- {P_ENCP_VIDEO_VSPULS_BLINE, 0},
- {P_ENCP_VIDEO_VSPULS_ELINE, 5},
- {P_ENCP_VIDEO_HAVON_BEGIN, 249},
- {P_ENCP_VIDEO_HAVON_END, 1689},
- {P_ENCP_VIDEO_VAVON_BLINE, 42},
- {P_ENCP_VIDEO_VAVON_ELINE, 521},
- {P_ENCP_VIDEO_SYNC_MODE, 0x07},
- {P_VENC_VIDEO_PROG_MODE, 0x0},
- {P_ENCP_VIDEO_HSO_BEGIN, 0x3},
- {P_ENCP_VIDEO_HSO_END, 0x5},
- {P_ENCP_VIDEO_VSO_BEGIN, 0x3},
- {P_ENCP_VIDEO_VSO_END, 0x5},
- {P_ENCP_VIDEO_VSO_BLINE, 0},
- {P_ENCP_VIDEO_SY_VAL, 8},
- {P_ENCP_VIDEO_SY2_VAL, 0x1d8},
- {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
- {P_ENCI_VIDEO_EN, 0},
- {P_ENCP_VIDEO_EN, 1},
- {MREG_END_MARKER, 0},
-};
-
-static const struct reg_t tvregs_576i[] = {
- {P_ENCP_VIDEO_EN, 0},
- {P_ENCI_VIDEO_EN, 0},
- {P_VENC_DVI_SETTING, 0},
- {P_ENCI_VIDEO_MODE, 0},
- {P_ENCI_VIDEO_MODE_ADV, 0},
- {P_ENCI_SYNC_HSO_BEGIN, 3},
- {P_ENCI_SYNC_HSO_END, 129},
- {P_ENCI_SYNC_VSO_EVNLN, 0x0003},
- {P_ENCI_SYNC_VSO_ODDLN, 0x0104},
- {P_ENCI_MACV_MAX_AMP, 0x8107},
- {P_VENC_VIDEO_PROG_MODE, 0xff},
- {P_ENCI_VIDEO_MODE, 0x13},
- {P_ENCI_VIDEO_MODE_ADV, 0x26},
- {P_ENCI_VIDEO_SCH, 0x28},
- {P_ENCI_SYNC_MODE, 0x07},
- {P_ENCI_YC_DELAY, 0x333},
- {P_ENCI_VFIFO2VD_PIXEL_START, 0x010b},
- {P_ENCI_VFIFO2VD_PIXEL_END, 0x06ab},
- {P_ENCI_VFIFO2VD_LINE_TOP_START, 0x0016},
- {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136},
- {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017},
- {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137},
- {P_ENCI_DBG_PX_RST, 0},
- {P_ENCI_VFIFO2VD_CTL, 0x4e01},
- {P_ENCI_VFIFO2VD_PIXEL_START, 0x010b},
- {P_ENCI_VFIFO2VD_PIXEL_END, 0x06ab},
- {P_ENCI_VFIFO2VD_LINE_TOP_START, 0x0016},
- {P_ENCI_VFIFO2VD_LINE_TOP_END, 0x0136},
- {P_ENCI_VFIFO2VD_LINE_BOT_START, 0x0017},
- {P_ENCI_VFIFO2VD_LINE_BOT_END, 0x0137},
- {P_VPU_VIU_VENC_MUX_CTRL, 0x5},
- {P_ENCP_VIDEO_EN, 0},
- {P_ENCI_VIDEO_EN, 1},
- {MREG_END_MARKER, 0},
-};
-
-static const struct reg_t tvregs_576p[] = {
- {P_ENCP_VIDEO_EN, 0},
- {P_ENCI_VIDEO_EN, 0},
- {P_ENCP_VIDEO_FILT_CTRL, 0x52},
- {P_VENC_DVI_SETTING, 0x21},
- {P_ENCP_VIDEO_MODE, 0x4000},
- {P_ENCP_VIDEO_MODE_ADV, 9},
- {P_ENCP_VIDEO_YFP1_HTIME, 235},
- {P_ENCP_VIDEO_YFP2_HTIME, 1674},
- {P_ENCP_VIDEO_MAX_PXCNT, 1727},
- {P_ENCP_VIDEO_MAX_LNCNT, 624},
- {P_ENCP_VIDEO_HSPULS_BEGIN, 0},
- {P_ENCP_VIDEO_HSPULS_END, 0x80},
- {P_ENCP_VIDEO_HSPULS_SWITCH, 88},
- {P_ENCP_VIDEO_VSPULS_BEGIN, 0},
- {P_ENCP_VIDEO_VSPULS_END, 1599},
- {P_ENCP_VIDEO_VSPULS_BLINE, 0},
- {P_ENCP_VIDEO_VSPULS_ELINE, 4},
- {P_ENCP_VIDEO_HAVON_BEGIN, 235},
- {P_ENCP_VIDEO_HAVON_END, 1674},
- {P_ENCP_VIDEO_VAVON_BLINE, 44},
- {P_ENCP_VIDEO_VAVON_ELINE, 619},
- {P_ENCP_VIDEO_SYNC_MODE, 0x07},
- {P_VENC_VIDEO_PROG_MODE, 0x0},
- {P_ENCP_VIDEO_HSO_BEGIN, 0x80},
- {P_ENCP_VIDEO_HSO_END, 0x0},
- {P_ENCP_VIDEO_VSO_BEGIN, 0x0},
- {P_ENCP_VIDEO_VSO_END, 0x5},
- {P_ENCP_VIDEO_VSO_BLINE, 0},
- {P_ENCP_VIDEO_SY_VAL, 8},
- {P_ENCP_VIDEO_SY2_VAL, 0x1d8},
- {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
- {P_ENCI_VIDEO_EN, 0},
- {P_ENCP_VIDEO_EN, 1},
- {MREG_END_MARKER, 0},
-};
-
-static const struct reg_t tvregs_1080i[] = {
- {P_ENCP_VIDEO_EN, 0},
- {P_ENCI_VIDEO_EN, 0},
- {P_VENC_DVI_SETTING, 0x2029},
- {P_ENCP_VIDEO_MAX_PXCNT, 4399},
- {P_ENCP_VIDEO_MAX_LNCNT, 1124},
- {P_ENCP_VIDEO_HSPULS_BEGIN, 88},
- {P_ENCP_VIDEO_HSPULS_END, 264},
- {P_ENCP_VIDEO_HSPULS_SWITCH, 88},
- {P_ENCP_VIDEO_HAVON_BEGIN, 516},
- {P_ENCP_VIDEO_HAVON_END, 4355},
- {P_ENCP_VIDEO_HSO_BEGIN, 264},
- {P_ENCP_VIDEO_HSO_END, 176},
- {P_ENCP_VIDEO_EQPULS_BEGIN, 2288},
- {P_ENCP_VIDEO_EQPULS_END, 2464},
- {P_ENCP_VIDEO_VSPULS_BEGIN, 440},
- {P_ENCP_VIDEO_VSPULS_END, 2200},
- {P_ENCP_VIDEO_VSPULS_BLINE, 0},
- {P_ENCP_VIDEO_VSPULS_ELINE, 4},
- {P_ENCP_VIDEO_EQPULS_BLINE, 0},
- {P_ENCP_VIDEO_EQPULS_ELINE, 4},
- {P_ENCP_VIDEO_VAVON_BLINE, 20},
- {P_ENCP_VIDEO_VAVON_ELINE, 559},
- {P_ENCP_VIDEO_VSO_BEGIN, 88},
- {P_ENCP_VIDEO_VSO_END, 88},
- {P_ENCP_VIDEO_VSO_BLINE, 0},
- {P_ENCP_VIDEO_VSO_ELINE, 5},
- {P_ENCP_VIDEO_YFP1_HTIME, 516},
- {P_ENCP_VIDEO_YFP2_HTIME, 4355},
- {P_VENC_VIDEO_PROG_MODE, 0x100},
- {P_ENCP_VIDEO_OFLD_VOAV_OFST, 0x11},
- {P_ENCP_VIDEO_MODE, 0x5ffc},
- {P_ENCP_VIDEO_MODE_ADV, 0x0019},
- {P_ENCP_VIDEO_SYNC_MODE, 0x207},
- {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
- {P_ENCI_VIDEO_EN, 0},
- {P_ENCP_VIDEO_EN, 1},
- {MREG_END_MARKER, 0},
-};
-
-static const struct reg_t tvregs_1080i_50hz[] = {
- {P_ENCP_VIDEO_EN, 0},
- {P_ENCI_VIDEO_EN, 0},
- {P_VENC_DVI_SETTING, 0x202d},
- {P_ENCP_VIDEO_MAX_PXCNT, 5279},
- {P_ENCP_VIDEO_MAX_LNCNT, 1124},
- {P_ENCP_VIDEO_HSPULS_BEGIN, 88},
- {P_ENCP_VIDEO_HSPULS_END, 264},
- {P_ENCP_VIDEO_HSPULS_SWITCH, 88},
- {P_ENCP_VIDEO_HAVON_BEGIN, 526},
- {P_ENCP_VIDEO_HAVON_END, 4365},
- {P_ENCP_VIDEO_HSO_BEGIN, 142},
- {P_ENCP_VIDEO_HSO_END, 230},
- {P_ENCP_VIDEO_VSPULS_BEGIN, 440},
- {P_ENCP_VIDEO_VSPULS_END, 2200},
- {P_ENCP_VIDEO_VSPULS_BLINE, 0},
- {P_ENCP_VIDEO_VSPULS_ELINE, 4},
- {P_ENCP_VIDEO_VAVON_BLINE, 20},
- {P_ENCP_VIDEO_VAVON_ELINE, 559},
- {P_ENCP_VIDEO_VSO_BEGIN, 142},
- {P_ENCP_VIDEO_VSO_END, 142},
- {P_ENCP_VIDEO_VSO_BLINE, 0},
- {P_ENCP_VIDEO_VSO_ELINE, 5},
- {P_ENCP_VIDEO_YFP1_HTIME, 526},
- {P_ENCP_VIDEO_YFP2_HTIME, 4365},
- {P_VENC_VIDEO_PROG_MODE, 0x100},
- {P_ENCP_VIDEO_OFLD_VOAV_OFST, 0x11},
- {P_ENCP_VIDEO_MODE, 0x5ffc},
- {P_ENCP_VIDEO_MODE_ADV, 0x0019},
- {P_ENCP_VIDEO_SYNC_MODE, 0x7},
- {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
- {P_ENCI_VIDEO_EN, 0},
- {P_ENCP_VIDEO_EN, 1},
- {MREG_END_MARKER, 0},
-};
-
-static const struct reg_t tvregs_1080p[] = {
- {P_ENCP_VIDEO_EN, 0},
- {P_ENCI_VIDEO_EN, 0},
- {P_ENCP_VIDEO_FILT_CTRL, 0x1052},
- {P_VENC_DVI_SETTING, 0x0001},
- {P_ENCP_VIDEO_MODE, 0x4040},
- {P_ENCP_VIDEO_MODE_ADV, 0x0018},
- {P_ENCP_VIDEO_YFP1_HTIME, 140},
- {P_ENCP_VIDEO_YFP2_HTIME, 2060},
- {P_ENCP_VIDEO_MAX_PXCNT, 2199},
- {P_ENCP_VIDEO_HSPULS_BEGIN, 2156},
- {P_ENCP_VIDEO_HSPULS_END, 44},
- {P_ENCP_VIDEO_HSPULS_SWITCH, 44},
- {P_ENCP_VIDEO_VSPULS_BEGIN, 140},
- {P_ENCP_VIDEO_VSPULS_END, 2059},
- {P_ENCP_VIDEO_VSPULS_BLINE, 0},
- {P_ENCP_VIDEO_VSPULS_ELINE, 4},
- {P_ENCP_VIDEO_HAVON_BEGIN, 148},
- {P_ENCP_VIDEO_HAVON_END, 2067},
- {P_ENCP_VIDEO_VAVON_BLINE, 41},
- {P_ENCP_VIDEO_VAVON_ELINE, 1120},
- {P_ENCP_VIDEO_HSO_BEGIN, 44},
- {P_ENCP_VIDEO_HSO_END, 2156},
- {P_ENCP_VIDEO_VSO_BEGIN, 2100},
- {P_ENCP_VIDEO_VSO_END, 2164},
- {P_ENCP_VIDEO_VSO_BLINE, 0},
- {P_ENCP_VIDEO_VSO_ELINE, 5},
- {P_ENCP_VIDEO_MAX_LNCNT, 1124},
- {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
- {P_VENC_VIDEO_PROG_MODE, 0x100},
- {P_ENCI_VIDEO_EN, 0},
- {P_ENCP_VIDEO_EN, 1},
- {MREG_END_MARKER, 0},
-};
-
-static const struct reg_t tvregs_1080p_50hz[] = {
- {P_ENCP_VIDEO_EN, 0},
- {P_ENCI_VIDEO_EN, 0},
- {P_VENC_DVI_SETTING, 0x000d},
- {P_ENCP_VIDEO_MAX_PXCNT, 2639},
- {P_ENCP_VIDEO_MAX_LNCNT, 1124},
- {P_ENCP_VIDEO_HSPULS_BEGIN, 44},
- {P_ENCP_VIDEO_HSPULS_END, 132},
- {P_ENCP_VIDEO_HSPULS_SWITCH, 44},
- {P_ENCP_VIDEO_HAVON_BEGIN, 271},
- {P_ENCP_VIDEO_HAVON_END, 2190},
- {P_ENCP_VIDEO_HSO_BEGIN, 79},
- {P_ENCP_VIDEO_HSO_END, 123},
- {P_ENCP_VIDEO_VSPULS_BEGIN, 220},
- {P_ENCP_VIDEO_VSPULS_END, 2140},
- {P_ENCP_VIDEO_VSPULS_BLINE, 0},
- {P_ENCP_VIDEO_VSPULS_ELINE, 4},
- {P_ENCP_VIDEO_EQPULS_BLINE, 0},
- {P_ENCP_VIDEO_EQPULS_ELINE, 4},
- {P_ENCP_VIDEO_VAVON_BLINE, 41},
- {P_ENCP_VIDEO_VAVON_ELINE, 1120},
- {P_ENCP_VIDEO_VSO_BEGIN, 79},
- {P_ENCP_VIDEO_VSO_END, 79},
- {P_ENCP_VIDEO_VSO_BLINE, 0},
- {P_ENCP_VIDEO_VSO_ELINE, 5},
- {P_ENCP_VIDEO_YFP1_HTIME, 271},
- {P_ENCP_VIDEO_YFP2_HTIME, 2190},
- {P_VENC_VIDEO_PROG_MODE, 0x100},
- {P_ENCP_VIDEO_MODE, 0x4040},
- {P_ENCP_VIDEO_MODE_ADV, 0x0018},
- {P_ENCP_VIDEO_SYNC_MODE, 0x7},
- {P_ENCP_VIDEO_YC_DLY, 0},
- {P_ENCP_VIDEO_RGB_CTRL, 2},
- {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
- {P_ENCI_VIDEO_EN, 0},
- {P_ENCP_VIDEO_EN, 1},
- {MREG_END_MARKER, 0},
-};
-
-static const struct reg_t tvregs_1080p_24hz[] = {
- {P_ENCP_VIDEO_EN, 0},
- {P_ENCI_VIDEO_EN, 0},
- {P_ENCP_VIDEO_FILT_CTRL, 0x1052},
- {P_VENC_DVI_SETTING, 0x000d},
- {P_ENCP_VIDEO_MAX_PXCNT, 2749},
- {P_ENCP_VIDEO_MAX_LNCNT, 1124},
- {P_ENCP_VIDEO_HSPULS_BEGIN, 44},
- {P_ENCP_VIDEO_HSPULS_END, 132},
- {P_ENCP_VIDEO_HSPULS_SWITCH, 44},
- {P_ENCP_VIDEO_HAVON_BEGIN, 271},
- {P_ENCP_VIDEO_HAVON_END, 2190},
- {P_ENCP_VIDEO_HSO_BEGIN, 79},
- {P_ENCP_VIDEO_HSO_END, 123},
- {P_ENCP_VIDEO_VSPULS_BEGIN, 220},
- {P_ENCP_VIDEO_VSPULS_END, 2140},
- {P_ENCP_VIDEO_VSPULS_BLINE, 0},
- {P_ENCP_VIDEO_VSPULS_ELINE, 4},
- {P_ENCP_VIDEO_EQPULS_BLINE, 0},
- {P_ENCP_VIDEO_EQPULS_ELINE, 4},
- {P_ENCP_VIDEO_VAVON_BLINE, 41},
- {P_ENCP_VIDEO_VAVON_ELINE, 1120},
- {P_ENCP_VIDEO_VSO_BEGIN, 79},
- {P_ENCP_VIDEO_VSO_END, 79},
- {P_ENCP_VIDEO_VSO_BLINE, 0},
- {P_ENCP_VIDEO_VSO_ELINE, 5},
- {P_ENCP_VIDEO_YFP1_HTIME, 271},
- {P_ENCP_VIDEO_YFP2_HTIME, 2190},
- {P_VENC_VIDEO_PROG_MODE, 0x100},
- {P_ENCP_VIDEO_MODE, 0x4040},
- {P_ENCP_VIDEO_MODE_ADV, 0x0018},
- {P_ENCP_VIDEO_SYNC_MODE, 0x7},
- {P_ENCP_VIDEO_YC_DLY, 0},
- {P_ENCP_VIDEO_RGB_CTRL, 2},
- {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
- {P_ENCI_VIDEO_EN, 0},
- {P_ENCP_VIDEO_EN, 1},
- {MREG_END_MARKER, 0},
-};
-
-static const struct reg_t tvregs_4k2k_30hz[] = {
- {P_ENCP_VIDEO_EN, 0},
- {P_ENCI_VIDEO_EN, 0},
- {P_ENCP_VIDEO_MODE, 0x4040},
- {P_ENCP_VIDEO_MODE_ADV, 0x0008},
- {P_ENCP_VIDEO_YFP1_HTIME, 140},
- {P_ENCP_VIDEO_YFP2_HTIME, 140+3840},
- {P_ENCP_VIDEO_MAX_PXCNT, 3840+560-1},
- {P_ENCP_VIDEO_HSPULS_BEGIN, 2156+1920},
- {P_ENCP_VIDEO_HSPULS_END, 44},
- {P_ENCP_VIDEO_HSPULS_SWITCH, 44},
- {P_ENCP_VIDEO_VSPULS_BEGIN, 140},
- {P_ENCP_VIDEO_VSPULS_END, 2059+1920},
- {P_ENCP_VIDEO_VSPULS_BLINE, 0},
- {P_ENCP_VIDEO_VSPULS_ELINE, 4},
- {P_ENCP_VIDEO_HAVON_BEGIN, 148},
- {P_ENCP_VIDEO_HAVON_END, 3987},
- {P_ENCP_VIDEO_VAVON_BLINE, 89},
- {P_ENCP_VIDEO_VAVON_ELINE, 2248},
- {P_ENCP_VIDEO_HSO_BEGIN, 44},
- {P_ENCP_VIDEO_HSO_END, 2156+1920},
- {P_ENCP_VIDEO_VSO_BEGIN, 2100+1920},
- {P_ENCP_VIDEO_VSO_END, 2164+1920},
- {P_ENCP_VIDEO_VSO_BLINE, 51},
- {P_ENCP_VIDEO_VSO_ELINE, 53},
- {P_ENCP_VIDEO_MAX_LNCNT, 2249},
- {P_ENCP_VIDEO_FILT_CTRL, 0x1000},
- {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
- {P_ENCP_VIDEO_EN, 1},
- {P_ENCI_VIDEO_EN, 0},
- {MREG_END_MARKER, 0},
-};
-
-static const struct reg_t tvregs_4k2k_25hz[] = {
- {P_ENCP_VIDEO_EN, 0},
- {P_ENCI_VIDEO_EN, 0},
- {P_ENCP_VIDEO_MODE, 0x4040},
- {P_ENCP_VIDEO_MODE_ADV, 0x0008},
- {P_ENCP_VIDEO_YFP1_HTIME, 140},
- {P_ENCP_VIDEO_YFP2_HTIME, 140+3840},
- {P_ENCP_VIDEO_MAX_PXCNT, 3840+1440-1},
- {P_ENCP_VIDEO_HSPULS_BEGIN, 2156+1920},
- {P_ENCP_VIDEO_HSPULS_END, 44},
- {P_ENCP_VIDEO_HSPULS_SWITCH, 44},
- {P_ENCP_VIDEO_VSPULS_BEGIN, 140},
- {P_ENCP_VIDEO_VSPULS_END, 2059+1920},
- {P_ENCP_VIDEO_VSPULS_BLINE, 0},
- {P_ENCP_VIDEO_VSPULS_ELINE, 4},
- {P_ENCP_VIDEO_HAVON_BEGIN, 148},
- {P_ENCP_VIDEO_HAVON_END, 3987},
- {P_ENCP_VIDEO_VAVON_BLINE, 89},
- {P_ENCP_VIDEO_VAVON_ELINE, 2248},
- {P_ENCP_VIDEO_HSO_BEGIN, 44},
- {P_ENCP_VIDEO_HSO_END, 2156+1920},
- {P_ENCP_VIDEO_VSO_BEGIN, 2100+1920},
- {P_ENCP_VIDEO_VSO_END, 2164+1920},
- {P_ENCP_VIDEO_VSO_BLINE, 51},
- {P_ENCP_VIDEO_VSO_ELINE, 53},
- {P_ENCP_VIDEO_MAX_LNCNT, 2249},
- {P_ENCP_VIDEO_FILT_CTRL, 0x1000},
- {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
- {P_ENCP_VIDEO_EN, 1},
- {P_ENCI_VIDEO_EN, 0},
- {MREG_END_MARKER, 0},
-};
-
-static const struct reg_t tvregs_4k2k_24hz[] = {
- {P_ENCP_VIDEO_EN, 0},
- {P_ENCI_VIDEO_EN, 0},
- {P_ENCP_VIDEO_MODE, 0x4040},
- {P_ENCP_VIDEO_MODE_ADV, 0x0008},
- {P_ENCP_VIDEO_YFP1_HTIME, 140},
- {P_ENCP_VIDEO_YFP2_HTIME, 140+3840},
- {P_ENCP_VIDEO_MAX_PXCNT, 3840+1660-1},
- {P_ENCP_VIDEO_HSPULS_BEGIN, 2156+1920},
- {P_ENCP_VIDEO_HSPULS_END, 44},
- {P_ENCP_VIDEO_HSPULS_SWITCH, 44},
- {P_ENCP_VIDEO_VSPULS_BEGIN, 140},
- {P_ENCP_VIDEO_VSPULS_END, 2059+1920},
- {P_ENCP_VIDEO_VSPULS_BLINE, 0},
- {P_ENCP_VIDEO_VSPULS_ELINE, 4},
- {P_ENCP_VIDEO_HAVON_BEGIN, 148},
- {P_ENCP_VIDEO_HAVON_END, 3987},
- {P_ENCP_VIDEO_VAVON_BLINE, 89},
- {P_ENCP_VIDEO_VAVON_ELINE, 2248},
- {P_ENCP_VIDEO_HSO_BEGIN, 44},
- {P_ENCP_VIDEO_HSO_END, 2156+1920},
- {P_ENCP_VIDEO_VSO_BEGIN, 2100+1920},
- {P_ENCP_VIDEO_VSO_END, 2164+1920},
- {P_ENCP_VIDEO_VSO_BLINE, 51},
- {P_ENCP_VIDEO_VSO_ELINE, 53},
- {P_ENCP_VIDEO_MAX_LNCNT, 2249},
- {P_ENCP_VIDEO_FILT_CTRL, 0x1000},
- {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
- {P_ENCP_VIDEO_EN, 1},
- {P_ENCI_VIDEO_EN, 0},
- {MREG_END_MARKER, 0},
-};
-
-static const struct reg_t tvregs_4k2k_smpte[] = {
- {P_ENCP_VIDEO_EN, 0},
- {P_ENCI_VIDEO_EN, 0},
- {P_ENCP_VIDEO_MODE, 0x4040},
- {P_ENCP_VIDEO_MODE_ADV, 0x0008},
- {P_ENCP_VIDEO_YFP1_HTIME, 140},
- {P_ENCP_VIDEO_YFP2_HTIME, 140+3840+256},
- {P_ENCP_VIDEO_MAX_PXCNT, 4096+1404-1},
- {P_ENCP_VIDEO_HSPULS_BEGIN, 2156+1920},
- {P_ENCP_VIDEO_HSPULS_END, 44},
- {P_ENCP_VIDEO_HSPULS_SWITCH, 44},
- {P_ENCP_VIDEO_VSPULS_BEGIN, 140},
- {P_ENCP_VIDEO_VSPULS_END, 2059+1920},
- {P_ENCP_VIDEO_VSPULS_BLINE, 0},
- {P_ENCP_VIDEO_VSPULS_ELINE, 4},
- {P_ENCP_VIDEO_HAVON_BEGIN, 148},
- {P_ENCP_VIDEO_HAVON_END, 3987+256},
- {P_ENCP_VIDEO_VAVON_BLINE, 89},
- {P_ENCP_VIDEO_VAVON_ELINE, 2248},
- {P_ENCP_VIDEO_HSO_BEGIN, 44},
- {P_ENCP_VIDEO_HSO_END, 2156+1920+256},
- {P_ENCP_VIDEO_VSO_BEGIN, 2100+1920+256},
- {P_ENCP_VIDEO_VSO_END, 2164+1920+256},
- {P_ENCP_VIDEO_VSO_BLINE, 51},
- {P_ENCP_VIDEO_VSO_ELINE, 53},
- {P_ENCP_VIDEO_MAX_LNCNT, 2249},
- {P_ENCP_VIDEO_FILT_CTRL, 0x1000},
- {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
- {P_ENCP_VIDEO_EN, 1},
- {P_ENCI_VIDEO_EN, 0},
- {MREG_END_MARKER, 0},
-};
-
-static const struct reg_t tvregs_4k2k_smpte_25hz[] = {
- {P_ENCP_VIDEO_EN, 0},
- {P_ENCI_VIDEO_EN, 0},
- {P_ENCP_VIDEO_MODE, 0x4040,},
- {P_ENCP_VIDEO_MODE_ADV, 0x18,},
- {P_ENCP_VIDEO_MAX_PXCNT, 0x149F,},
- {P_ENCP_VIDEO_MAX_LNCNT, 0x8C9,},
- {P_ENCP_VIDEO_HAVON_BEGIN, 0xD8,},
- {P_ENCP_VIDEO_HAVON_END, 0x10D7,},
- {P_ENCP_VIDEO_VAVON_BLINE, 0x52,},
- {P_ENCP_VIDEO_VAVON_ELINE, 0x8C1,},
- {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
- {P_ENCP_VIDEO_HSO_END, 0x58,},
- {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
- {P_ENCP_VIDEO_VSO_END, 0x32,},
- {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
- {P_ENCP_VIDEO_VSO_ELINE, 0xA,},
- {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
- {P_ENCP_VIDEO_EN, 1},
- {P_ENCI_VIDEO_EN, 0},
- {MREG_END_MARKER, 0},
-};
-
-static const struct reg_t tvregs_4k2k_smpte_30hz[] = {
- {P_ENCP_VIDEO_EN, 0},
- {P_ENCI_VIDEO_EN, 0},
- {P_ENCP_VIDEO_MODE, 0x4040,},
- {P_ENCP_VIDEO_MODE_ADV, 0x18,},
- {P_ENCP_VIDEO_MAX_PXCNT, 0x112F,},
- {P_ENCP_VIDEO_MAX_LNCNT, 0x8C9,},
- {P_ENCP_VIDEO_HAVON_BEGIN, 0xD8,},
- {P_ENCP_VIDEO_HAVON_END, 0x10D7,},
- {P_ENCP_VIDEO_VAVON_BLINE, 0x52,},
- {P_ENCP_VIDEO_VAVON_ELINE, 0x8C1,},
- {P_ENCP_VIDEO_HSO_BEGIN, 0x0,},
- {P_ENCP_VIDEO_HSO_END, 0x58,},
- {P_ENCP_VIDEO_VSO_BEGIN, 0x1E,},
- {P_ENCP_VIDEO_VSO_END, 0x32,},
- {P_ENCP_VIDEO_VSO_BLINE, 0x0,},
- {P_ENCP_VIDEO_VSO_ELINE, 0xA,},
- {P_VPU_VIU_VENC_MUX_CTRL, 0xA},
- {P_ENCP_VIDEO_EN, 1},
- {P_ENCI_VIDEO_EN, 0},
- {MREG_END_MARKER, 0},
-};
-
-struct vic_tvregs_set {
- enum hdmi_vic vic;
- const struct reg_t *reg_setting;
-};
-
-/* Using HDMI vic as index */
-static struct vic_tvregs_set tvregsTab[] = {
- {HDMI_720x480i60_16x9, tvregs_480i},
- {HDMI_2880x480i60_16x9, tvregs_480i},
- {HDMI_720x480p60_16x9, tvregs_480p},
- {HDMI_2880x240p60_16x9, tvregs_480p},
- {HDMI_720x576i50_16x9, tvregs_576i},
- {HDMI_2880x576i50_16x9, tvregs_576i},
- {HDMI_720x576p50_16x9, tvregs_576p},
- {HDMI_2880x576p50_16x9, tvregs_576p},
- {HDMI_1280x720p60_16x9, tvregs_720p},
- {HDMI_1920x1080i60_16x9, tvregs_1080i},
- {HDMI_1920x1080p60_16x9, tvregs_1080p},
- {HDMI_1920x1080p30_16x9, tvregs_1080p},
- {HDMI_1280x720p50_16x9, tvregs_720p_50hz},
- {HDMI_1920x1080i50_16x9, tvregs_1080i_50hz},
- {HDMI_1920x1080p50_16x9, tvregs_1080p_50hz},
- {HDMI_1920x1080p25_16x9, tvregs_1080p_50hz},
- {HDMI_1920x1080p24_16x9, tvregs_1080p_24hz},
- {HDMI_3840x2160p30_16x9, tvregs_4k2k_30hz},
- {HDMI_3840x2160p25_16x9, tvregs_4k2k_25hz},
- {HDMI_3840x2160p24_16x9, tvregs_4k2k_24hz},
- {HDMI_4096x2160p24_256x135, tvregs_4k2k_smpte},
- {HDMI_4096x2160p25_256x135, tvregs_4k2k_smpte_25hz},
- {HDMI_4096x2160p30_256x135, tvregs_4k2k_smpte_30hz},
- {HDMI_4096x2160p50_256x135, tvregs_4k2k_smpte_25hz},
- {HDMI_4096x2160p60_256x135, tvregs_4k2k_smpte_30hz},
- {HDMI_4096x2160p50_256x135_Y420, tvregs_4k2k_smpte_25hz},
- {HDMI_4096x2160p60_256x135_Y420, tvregs_4k2k_smpte_30hz},
- {HDMI_3840x2160p60_16x9, tvregs_4k2k_30hz},
- {HDMI_3840x2160p50_16x9, tvregs_4k2k_25hz},
- {HDMI_3840x2160p60_16x9_Y420, tvregs_4k2k_30hz},
- {HDMI_3840x2160p50_16x9_Y420, tvregs_4k2k_25hz},
-};
-
-static inline void setreg(const struct reg_t *r)
-{
- hd_write_reg(r->reg, r->val);
- /* printk("[0x%x] = 0x%x\n", r->reg, r->val); */
-}
-
-static const struct reg_t *tvregs_setting_mode(enum hdmi_vic vic)
-{
- int i = 0;
- for (i = 0; i < ARRAY_SIZE(tvregsTab); i++) {
- if (vic == tvregsTab[i].vic)
- return tvregsTab[i].reg_setting;
- }
- return NULL;
-}
-
-void set_vmode_enc_hw(enum hdmi_vic vic)
-{
- const struct reg_t *s = tvregs_setting_mode(vic);
-
- if (s) {
- pr_info("hdmitx: set enc for VIC: %d\n", vic);
- while (MREG_END_MARKER != s->reg)
- setreg(s++);
- } else
- pr_info("hdmitx: not find VIC: %d\n", vic);
-}
diff --git a/drivers/amlogic/media/vout/hdmitx/sound.c b/drivers/amlogic/media/vout/hdmitx/sound.c
new file mode 100644
index 0000000..e03dde9
--- /dev/null
+++ b/drivers/amlogic/media/vout/hdmitx/sound.c
@@ -0,0 +1,185 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <asm/arch/io.h>
+#include <asm/arch/register.h>
+#include <common.h>
+#include <amlogic/auge_sound.h>
+#include <asm/arch/cpu.h>
+#include <amlogic/cpu_id.h>
+
+struct aiu_958_channel_status {
+ unsigned short chstat0_l;
+ unsigned short chstat1_l;
+ unsigned short chstat0_r;
+ unsigned short chstat1_r;
+};
+
+static int audiobus_read(unsigned long reg, unsigned int *val)
+{
+ *val = readl(reg);
+ return 0;
+}
+
+static void hhi_write(unsigned long reg, unsigned int val)
+{
+ writel(val, reg);
+}
+
+static void audiobus_write(unsigned long reg, unsigned int val)
+{
+ writel(val, reg);
+}
+
+static int audiobus_update_bits(unsigned int reg, unsigned int mask,
+ unsigned int value)
+{
+ bool change;
+ unsigned int old, new;
+
+ audiobus_read(reg, &old);
+
+ new = (old & ~mask) | (value & mask);
+ change = old != new;
+ if (change)
+ audiobus_write(reg, new);
+
+ return change;
+}
+
+static void aml_set_audio_spdif_clk(void)
+{
+ /*mpll0: 25m*/
+ hhi_write(ANACTRL_MPLL_CTRL0, 0x543);
+ hhi_write(ANACTRL_MPLL_CTRL1, 0xC5101856);
+ hhi_write(ANACTRL_MPLL_CTRL2, 0x40000033);
+
+ /* audio clk gate */
+ audiobus_write(EE_AUDIO_CLK_GATE_EN0,
+ 1 << 17 /* spdifout */
+ | 1 << 9 /* frddra */
+ | 1 << 0 /* ddr_arb */);
+
+ /*SPDIFOUT_CTRL clk:6m*/
+ audiobus_write(EE_AUDIO_CLK_SPDIFOUT_CTRL,
+ 1 << 31 /* enable */
+ | 0 << 24 /* mpll0 */
+ | 3 << 0 /* dividor */);
+}
+
+static void aml_spdif_fifo_ctrl(void)
+{
+ /* reg mute val */
+ audiobus_write(EE_AUDIO_SPDIFOUT_MUTE_VAL, 0x0);
+
+ /* mask lane0 L/R, lsb first, insert data from 31bits */
+ audiobus_update_bits(EE_AUDIO_SPDIFOUT_CTRL0,
+ 0x1<<22 | 0x1<<21 | 0x1 << 20 | 0x1 << 19 | 0xffff << 0,
+ 0x1<<22 | 0x1<<21 | 0x0 << 20 | 0x0 << 19 | 0x3 << 0);
+
+ /* split 64bits ddr data to 2 sample */
+ /* msb position of data */
+ /* frddr_A */
+ audiobus_update_bits(EE_AUDIO_SPDIFOUT_CTRL1,
+ 0x3 << 24 | 0x1f << 8 | 0x7 << 4,
+ 0 << 24 | (32 - 1) << 8 | 3 << 4);
+
+ audiobus_write(EE_AUDIO_SPDIFOUT_SWAP, 0x1 << 4);
+}
+
+static void spdifout_set_pcm_chsts(struct aiu_958_channel_status *set)
+{
+ if (!set) {
+ printf("%s(), error set NULL point\n", __func__);
+ return;
+ }
+
+ audiobus_write(EE_AUDIO_SPDIFOUT_CHSTS0,
+ set->chstat1_l << 16 | set->chstat0_l);
+ audiobus_write(EE_AUDIO_SPDIFOUT_CHSTS6,
+ set->chstat1_r << 16 | set->chstat0_r);
+}
+
+void frddr_init_without_mngr(void)
+{
+ unsigned int start_addr, end_addr, int_addr;
+ static int buf[256];
+
+ memset(buf, 0x0, sizeof(buf));
+ start_addr = virt_to_phys(buf);
+ end_addr = start_addr + sizeof(buf) - 1;
+ int_addr = sizeof(buf) / 64;
+
+ audiobus_write(EE_AUDIO_ARB_CTRL0, 0x800000ff);
+
+ audiobus_write(EE_AUDIO_FRDDR_A_START_ADDR, start_addr);
+
+ audiobus_write(EE_AUDIO_FRDDR_A_INIT_ADDR, start_addr);
+
+ audiobus_write(EE_AUDIO_FRDDR_A_FINISH_ADDR, end_addr);
+
+ audiobus_write(EE_AUDIO_FRDDR_A_INT_ADDR, int_addr);
+
+ audiobus_write(EE_AUDIO_FRDDR_A_CTRL1,
+ (0x40 - 1) << 24 | (0x20 - 1) << 16 | 2 << 8 | 0 << 0);
+
+ audiobus_write(EE_AUDIO_FRDDR_A_CTRL0,
+ 1 << 31
+ | 0 << 24
+ | 4 << 16
+ );
+
+ /* src0 enable, src0 select spdifout */
+ audiobus_write(EE_AUDIO_FRDDR_A_CTRL2, 1 << 4 | 3 << 0);
+}
+
+static void aml_spdif_enable(void)
+{
+ /* reset */
+ audiobus_update_bits(EE_AUDIO_SPDIFOUT_CTRL0, 3 << 28, 0);
+ audiobus_update_bits(EE_AUDIO_SPDIFOUT_CTRL0, 1 << 29, 1 << 29);
+ audiobus_update_bits(EE_AUDIO_SPDIFOUT_CTRL0, 1 << 28, 1 << 28);
+ /* enable */
+ audiobus_update_bits(EE_AUDIO_SPDIFOUT_CTRL0, 1 << 31, 1 << 31);
+
+ /* tohdmitx enable */
+ audiobus_write(EE_AUDIO_TOHDMITX_CTRL0,
+ 1 << 3 /* spdif_clk_cap_inv */
+ | 0 << 2 /* spdif_clk_inv */
+ | 0 << 1 /* spdif_out */
+ | 0 << 0 /* spdif_clk */
+ );
+ audiobus_update_bits(EE_AUDIO_TOHDMITX_CTRL0,
+ 0x1 << 30, 0x1 << 30);
+
+ audiobus_update_bits(EE_AUDIO_TOHDMITX_CTRL0,
+ 0x1 << 31, 0x1 << 31);
+}
+
+static void aml_spdif_play(void)
+{
+ struct aiu_958_channel_status chstat;
+
+ chstat.chstat0_l = 0x0100;
+ chstat.chstat0_r = 0x0100;
+ chstat.chstat1_l = 0X200;
+ chstat.chstat1_r = 0X200;
+
+ aml_spdif_fifo_ctrl();
+ spdifout_set_pcm_chsts(&chstat);
+ frddr_init_without_mngr();
+ aml_spdif_enable();
+}
+
+int aml_audio_init(void)
+{
+ printf("%s\n", __func__);
+
+ aml_set_audio_spdif_clk();
+ aml_spdif_play();
+
+ return 0;
+}
+
diff --git a/drivers/amlogic/media/vout/lcd/Kconfig b/drivers/amlogic/media/vout/lcd/Kconfig
index 2357e7f..7893e92 100644
--- a/drivers/amlogic/media/vout/lcd/Kconfig
+++ b/drivers/amlogic/media/vout/lcd/Kconfig
@@ -1,21 +1,15 @@
+menu "AMLOGIC LCD Drivers"
+
config AML_LCD
bool "lcd output for video"
depends on AML_VOUT
help
Support for lcd video output
-config NOT_DTS_CONTROL_BL
- bool "Not use dts to control backlight"
- default n
- help
- Not use dts to control backlight
-
-if AML_LCD
source "drivers/amlogic/media/vout/lcd/lcd_tv/Kconfig"
source "drivers/amlogic/media/vout/lcd/lcd_tablet/Kconfig"
source "drivers/amlogic/media/vout/lcd/lcd_extern/Kconfig"
-source "drivers/amlogic/media/vout/lcd/bl_ldim/Kconfig"
-source "drivers/amlogic/media/vout/lcd/bl_extern/Kconfig"
-endif
+source "drivers/amlogic/media/vout/lcd/backlight/Kconfig"
+endmenu
diff --git a/drivers/amlogic/media/vout/lcd/Makefile b/drivers/amlogic/media/vout/lcd/Makefile
index 05fb9fb..0d63b52 100644
--- a/drivers/amlogic/media/vout/lcd/Makefile
+++ b/drivers/amlogic/media/vout/lcd/Makefile
@@ -1,7 +1,9 @@
-obj-$(CONFIG_AML_LCD) += lcd_vout.o lcd_common.o lcd_clk_config.o \
- lcd_bl.o lcd_unifykey.o lcd_debug.o lcd_tcon.o
+obj-$(CONFIG_AML_LCD) += lcd_vout.o lcd_common.o lcd_gpio.o \
+ lcd_clk_config.o lcd_phy_config.o lcd_debug.o \
+ lcd_unifykey.o lcd_i2c_dev.o lcd_venc.o lcd_init_test.o lcd_vbyone.o
+
+obj-$(CONFIG_AML_LCD_TCON) += lcd_tcon.o lcd_tcon_hw.o lcd_tcon_spi.o
obj-$(CONFIG_AML_LCD_TV) += lcd_tv/
obj-$(CONFIG_AML_LCD_TABLET) += lcd_tablet/
-obj-$(CONFIG_AML_LCD_EXTERN) += lcd_extern/
-obj-$(CONFIG_AML_BL_LOCAL_DIMMING) += bl_ldim/
-obj-$(CONFIG_AML_BL_EXTERN) += bl_extern/
+#obj-$(CONFIG_AML_LCD_EXTERN) += lcd_extern/
+obj-$(CONFIG_AML_LCD_BACKLIGHT) += backlight/
diff --git a/drivers/amlogic/media/vout/lcd/backlight/Kconfig b/drivers/amlogic/media/vout/lcd/backlight/Kconfig
new file mode 100644
index 0000000..c33b7fc
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/Kconfig
@@ -0,0 +1,13 @@
+menu "AMLOGIC LCD Drivers"
+
+config AML_LCD_BACKLIGHT
+ bool "backlight control for lcd"
+ depends on AML_LCD
+ help
+ Support for lcd backlight control
+
+
+source "drivers/amlogic/media/vout/lcd/backlight/bl_ldim/Kconfig"
+source "drivers/amlogic/media/vout/lcd/backlight/bl_extern/Kconfig"
+
+endmenu
diff --git a/drivers/amlogic/media/vout/lcd/backlight/Makefile b/drivers/amlogic/media/vout/lcd/backlight/Makefile
new file mode 100644
index 0000000..e1c7a98
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/Makefile
@@ -0,0 +1,4 @@
+obj-$(CONFIG_AML_LCD_BACKLIGHT) += lcd_bl.o bl_pwm.o
+
+#obj-$(CONFIG_AML_BL_LOCAL_DIMMING) += bl_ldim/
+#obj-$(CONFIG_AML_BL_EXTERN) += bl_extern/
diff --git a/drivers/amlogic/media/vout/lcd/backlight/bl_extern/Kconfig b/drivers/amlogic/media/vout/lcd/backlight/bl_extern/Kconfig
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/bl_extern/Kconfig
@@ -0,0 +1 @@
+
diff --git a/drivers/amlogic/media/vout/lcd/backlight/bl_extern/Makefile b/drivers/amlogic/media/vout/lcd/backlight/bl_extern/Makefile
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/bl_extern/Makefile
@@ -0,0 +1 @@
+
diff --git a/drivers/amlogic/media/vout/lcd/backlight/bl_extern/bl_extern.c b/drivers/amlogic/media/vout/lcd/backlight/bl_extern/bl_extern.c
new file mode 100644
index 0000000..1879aac
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/bl_extern/bl_extern.c
@@ -0,0 +1,650 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/gpio.h>
+#include <fdtdec.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+#include <amlogic/media/vout/lcd/lcd_i2c_dev.h>
+#include <amlogic/media/vout/lcd/bl_extern.h>
+#include "bl_extern.h"
+#include "../lcd_common.h"
+
+static unsigned int bl_extern_status;
+static unsigned int bl_extern_level;
+
+static struct aml_bl_extern_driver_s bl_extern_driver;
+
+static int bl_extern_set_level(unsigned int level)
+{
+ struct lcd_drv_s *lcd_drv = lcd_get_driver();
+ struct aml_bl_extern_driver_s *bl_extern = aml_bl_extern_get_driver();
+ unsigned int level_max, level_min;
+ unsigned int dim_max, dim_min;
+
+ if (lcd_drv == NULL)
+ return -1;
+
+ bl_extern_level = level;
+ if (bl_extern_status == 0)
+ return 0;
+
+ level_max = lcd_drv->bl_config->level_max;
+ level_min = lcd_drv->bl_config->level_min;
+ dim_max = bl_extern->config->dim_max;
+ dim_min = bl_extern->config->dim_min;
+ level = dim_min - ((level - level_min) * (dim_min - dim_max)) /
+ (level_max - level_min);
+
+ if (bl_extern_driver.device_bri_update)
+ bl_extern_driver.device_bri_update(level);
+
+ return 0;
+}
+
+static int bl_extern_power_on(void)
+{
+ int ret = 0;
+
+ BLEX("%s\n", __func__);
+
+ if (bl_extern_driver.device_power_on) {
+ bl_extern_driver.device_power_on();
+ bl_extern_status = 1;
+ }
+
+ /* restore bl level */
+ if (bl_extern_level > 0)
+ bl_extern_set_level(bl_extern_level);
+
+ return ret;
+}
+static int bl_extern_power_off(void)
+{
+ int ret = 0;
+
+ BLEX("%s\n", __func__);
+
+ bl_extern_status = 0;
+ if (bl_extern_driver.device_power_off)
+ bl_extern_driver.device_power_off();
+
+ return ret;
+}
+
+static struct aml_bl_extern_driver_s bl_extern_driver = {
+ .power_on = bl_extern_power_on,
+ .power_off = bl_extern_power_off,
+ .set_level = bl_extern_set_level,
+ .config_print = NULL,
+ .device_power_on = NULL,
+ .device_power_off = NULL,
+ .device_bri_update = NULL,
+ .config = NULL,
+};
+
+struct aml_bl_extern_driver_s *aml_bl_extern_get_driver(void)
+{
+ return &bl_extern_driver;
+}
+
+static void bl_extern_init_table_dynamic_size_print(
+ struct bl_extern_config_s *econf, int flag)
+{
+ int i, j, max_len;
+ unsigned char cmd_size;
+ unsigned char *table;
+
+ if (flag) {
+ printf("power on:\n");
+ table = econf->init_on;
+ max_len = econf->init_on_cnt;
+ } else {
+ printf("power off:\n");
+ table = econf->init_off;
+ max_len = econf->init_off_cnt;
+ }
+ if (table == NULL) {
+ BLEXERR("init_table %d is NULL\n", flag);
+ return;
+ }
+
+ i = 0;
+ while ((i + 1) < max_len) {
+ if (table[i] == LCD_EXT_CMD_TYPE_END) {
+ printf(" 0x%02x,%d,\n", table[i], table[i+1]);
+ break;
+ }
+ cmd_size = table[i+1];
+ printf(" 0x%02x,%d,", table[i], cmd_size);
+ if (cmd_size == 0)
+ goto init_table_dynamic_print_next;
+ if (i + 2 + cmd_size > max_len) {
+ printf("cmd_size out of support\n");
+ break;
+ }
+
+ if (table[i] == LCD_EXT_CMD_TYPE_DELAY) {
+ for (j = 0; j < cmd_size; j++)
+ printf("%d,", table[i+2+j]);
+ } else if (table[i] == LCD_EXT_CMD_TYPE_CMD) {
+ for (j = 0; j < cmd_size; j++)
+ printf("0x%02x,", table[i+2+j]);
+ } else if (table[i] == LCD_EXT_CMD_TYPE_CMD_DELAY) {
+ for (j = 0; j < (cmd_size - 1); j++)
+ printf("0x%02x,", table[i+2+j]);
+ printf("%d,", table[i+cmd_size+1]);
+ } else {
+ for (j = 0; j < cmd_size; j++)
+ printf("0x%02x,", table[i+2+j]);
+ }
+init_table_dynamic_print_next:
+ printf("\n");
+ i += (cmd_size + 2);
+ }
+}
+
+static void bl_extern_init_table_fixed_size_print(
+ struct bl_extern_config_s *econf, int flag)
+{
+ int i, j, max_len;
+ unsigned char cmd_size;
+ unsigned char *table;
+
+ cmd_size = econf->cmd_size;
+ if (flag) {
+ printf("power on:\n");
+ table = econf->init_on;
+ max_len = econf->init_on_cnt;
+ } else {
+ printf("power off:\n");
+ table = econf->init_off;
+ max_len = econf->init_off_cnt;
+ }
+ if (table == NULL) {
+ BLEXERR("init_table %d is NULL\n", flag);
+ return;
+ }
+
+ i = 0;
+ while ((i + cmd_size) <= max_len) {
+ printf(" ");
+ for (j = 0; j < cmd_size; j++)
+ printf("0x%02x,", table[i+j]);
+ printf("\n");
+
+ if (table[i] == LCD_EXT_CMD_TYPE_END)
+ break;
+ i += cmd_size;
+ }
+}
+
+static void bl_extern_config_print(void)
+{
+ struct aml_bl_extern_driver_s *bl_extern = aml_bl_extern_get_driver();
+
+ BLEX("%s:\n", __func__);
+ printf("index: %d\n"
+ "name: %s\n",
+ bl_extern->config->index,
+ bl_extern->config->name);
+ switch (bl_extern->config->type) {
+ case BL_EXTERN_I2C:
+ printf("type: i2c(%d)\n"
+ "i2c_addr: 0x%02x\n"
+ "i2c_bus: %d\n"
+ "dim_min: %d\n"
+ "dim_max: %d\n",
+ bl_extern->config->type,
+ bl_extern->config->i2c_addr,
+ bl_extern->config->i2c_bus,
+ bl_extern->config->dim_min,
+ bl_extern->config->dim_max);
+ if (bl_extern->config->cmd_size == 0)
+ break;
+ printf("init_loaded = %d\n"
+ "cmd_size = %d\n"
+ "init_on_cnt = %d\n"
+ "init_off_cnt = %d\n",
+ bl_extern->config->init_loaded,
+ bl_extern->config->cmd_size,
+ bl_extern->config->init_on_cnt,
+ bl_extern->config->init_off_cnt);
+ if (bl_extern->config->cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC) {
+ bl_extern_init_table_dynamic_size_print(bl_extern->config, 1);
+ bl_extern_init_table_dynamic_size_print(bl_extern->config, 0);
+ } else {
+ bl_extern_init_table_fixed_size_print(bl_extern->config, 1);
+ bl_extern_init_table_fixed_size_print(bl_extern->config, 0);
+ }
+ break;
+ case BL_EXTERN_SPI:
+ printf("type: spi(%d)\n"
+ "dim_min: %d\n"
+ "dim_max: %d\n",
+ bl_extern->config->type,
+ bl_extern->config->dim_min,
+ bl_extern->config->dim_max);
+ if (bl_extern->config->cmd_size == 0)
+ break;
+ printf("init_loaded = %d\n"
+ "cmd_size = %d\n"
+ "init_on_cnt = %d\n"
+ "init_off_cnt = %d\n",
+ bl_extern->config->init_loaded,
+ bl_extern->config->cmd_size,
+ bl_extern->config->init_on_cnt,
+ bl_extern->config->init_off_cnt);
+ if (bl_extern->config->cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC) {
+ bl_extern_init_table_dynamic_size_print(bl_extern->config, 1);
+ bl_extern_init_table_dynamic_size_print(bl_extern->config, 0);
+ } else {
+ bl_extern_init_table_fixed_size_print(bl_extern->config, 1);
+ bl_extern_init_table_fixed_size_print(bl_extern->config, 0);
+ }
+ break;
+ case BL_EXTERN_MIPI:
+ printf("type: mipi(%d)\n"
+ "dim_min: %d\n"
+ "dim_max: %d\n",
+ bl_extern->config->type,
+ bl_extern->config->dim_min,
+ bl_extern->config->dim_max);
+ break;
+ default:
+ break;
+ }
+}
+
+#ifdef CONFIG_OF_LIBFDT
+static unsigned char bl_extern_get_i2c_bus_str(const char *str)
+{
+ unsigned char i2c_bus;
+
+ if (strncmp(str, "i2c_bus_ao", 10) == 0)
+ i2c_bus = BL_EXTERN_I2C_BUS_4;
+ else if (strncmp(str, "i2c_bus_a", 9) == 0)
+ i2c_bus = BL_EXTERN_I2C_BUS_0;
+ else if (strncmp(str, "i2c_bus_b", 9) == 0)
+ i2c_bus = BL_EXTERN_I2C_BUS_1;
+ else if (strncmp(str, "i2c_bus_c", 9) == 0)
+ i2c_bus = BL_EXTERN_I2C_BUS_2;
+ else if (strncmp(str, "i2c_bus_d", 9) == 0)
+ i2c_bus = BL_EXTERN_I2C_BUS_3;
+ else if (strncmp(str, "i2c_bus_0", 9) == 0)
+ i2c_bus = BL_EXTERN_I2C_BUS_0;
+ else if (strncmp(str, "i2c_bus_1", 9) == 0)
+ i2c_bus = BL_EXTERN_I2C_BUS_1;
+ else if (strncmp(str, "i2c_bus_2", 9) == 0)
+ i2c_bus = BL_EXTERN_I2C_BUS_2;
+ else if (strncmp(str, "i2c_bus_3", 9) == 0)
+ i2c_bus = BL_EXTERN_I2C_BUS_3;
+ else if (strncmp(str, "i2c_bus_4", 9) == 0)
+ i2c_bus = BL_EXTERN_I2C_BUS_4;
+ else {
+ i2c_bus = BL_EXTERN_I2C_BUS_MAX;
+ BLEXERR("invalid i2c_bus: %s\n", str);
+ }
+
+ return i2c_bus;
+}
+
+static int bl_extern_init_table_dynamic_size_load_dts
+ (char *dtaddr, int nodeoffset, struct bl_extern_config_s *extconf,
+ int flag)
+{
+ unsigned char cmd_size, type;
+ int i = 0, j, max_len;
+ unsigned char *table;
+ char propname[20];
+ char *propdata;
+
+ if (flag) {
+ table = extconf->init_on;
+ max_len = BL_EXTERN_INIT_ON_MAX;
+ sprintf(propname, "init_on");
+ } else {
+ table = extconf->init_off;
+ max_len = BL_EXTERN_INIT_OFF_MAX;
+ sprintf(propname, "init_off");
+ }
+ if (table == NULL) {
+ BLEX("%s init_table is null\n", propname);
+ return 0;
+ }
+
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset, propname, NULL);
+ if (propdata == NULL) {
+ BLEXERR("%s: get %s failed\n", extconf->name, propname);
+ table[0] = LCD_EXT_CMD_TYPE_END;
+ table[1] = 0;
+ return -1;
+ }
+
+ while ((i + 1) < max_len) {
+ table[i] =
+ (unsigned char)(be32_to_cpup((((u32 *)propdata) + i)));
+ table[i + 1] =
+ (unsigned char)(be32_to_cpup((((u32 *)propdata) + i + 1)));
+ type = table[i];
+ cmd_size = table[i + 1];
+ if (type == LCD_EXT_CMD_TYPE_END)
+ break;
+ if (cmd_size == 0)
+ goto init_table_dynamic_dts_next;
+ if ((i + 2 + cmd_size) > max_len) {
+ BLEXERR("%s: %s cmd_size out of support\n",
+ extconf->name, propname);
+ table[i] = LCD_EXT_CMD_TYPE_END;
+ table[i + 1] = 0;
+ return -1;
+ }
+ for (j = 0; j < cmd_size; j++)
+ table[i + 2 + j] =
+ (unsigned char)(be32_to_cpup((((u32 *)propdata) + i + 2 + j)));
+
+init_table_dynamic_dts_next:
+ i += (cmd_size + 2);
+ }
+ if (flag)
+ extconf->init_on_cnt = i + 2;
+ else
+ extconf->init_off_cnt = i + 2;
+
+ return 0;
+}
+
+static int bl_extern_init_table_fixed_size_load_dts
+ (char *dtaddr, int nodeoffset, struct bl_extern_config_s *extconf,
+ int flag)
+{
+ unsigned char cmd_size;
+ int i = 0, j, max_len;
+ unsigned char *table;
+ char propname[20];
+ char *propdata;
+
+ cmd_size = extconf->cmd_size;
+ if (flag) {
+ table = extconf->init_on;
+ max_len = BL_EXTERN_INIT_ON_MAX;
+ sprintf(propname, "init_on");
+ } else {
+ table = extconf->init_off;
+ max_len = BL_EXTERN_INIT_OFF_MAX;
+ sprintf(propname, "init_off");
+ }
+ if (table == NULL) {
+ BLEX("%s init_table is null\n", propname);
+ return 0;
+ }
+
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset, propname, NULL);
+ if (propdata == NULL) {
+ BLEXERR("%s: get %s failed\n", extconf->name, propname);
+ table[0] = LCD_EXT_CMD_TYPE_END;
+ table[1] = 0;
+ return -1;
+ }
+
+ while (i < max_len) {
+ if ((i + cmd_size) > max_len) {
+ BLEXERR("%s: %s cmd_size out of support\n",
+ extconf->name, propname);
+ table[i] = LCD_EXT_CMD_TYPE_END;
+ return -1;
+ }
+ for (j = 0; j < cmd_size; j++)
+ table[i + j] =
+ (unsigned char)(be32_to_cpup((((u32 *)propdata) + i + j)));
+
+ if (table[i] == LCD_EXT_CMD_TYPE_END)
+ break;
+
+ i += cmd_size;
+ }
+ if (flag)
+ extconf->init_on_cnt = i + cmd_size;
+ else
+ extconf->init_off_cnt = i + cmd_size;
+
+ return 0;
+}
+
+static int bl_extern_config_from_dts(char *dtaddr, int index)
+{
+ int ret = 0;
+ int parent_offset, child_offset;
+ char propname[30];
+ char *propdata;
+ struct aml_bl_extern_driver_s *bl_extern = aml_bl_extern_get_driver();
+ unsigned char bl_ext_i2c_bus = BL_EXTERN_I2C_BUS_MAX;
+
+ parent_offset = fdt_path_offset(dtaddr, "/bl_extern");
+ if (parent_offset < 0) {
+ BLEXERR("bl: not find /backlight node %s\n",
+ fdt_strerror(parent_offset));
+ return -1;
+ }
+ propdata = (char *)fdt_getprop(dtaddr, parent_offset, "status", NULL);
+ if (propdata == NULL) {
+ BLEXERR("bl: not find status, default to disabled\n");
+ return -1;
+ } else {
+ if (strncmp(propdata, "okay", 2)) {
+ BLEX("bl: status disabled\n");
+ return -1;
+ }
+ }
+
+ propdata = (char *)fdt_getprop(dtaddr, parent_offset, "i2c_bus", NULL);
+ if (propdata == NULL)
+ bl_ext_i2c_bus = BL_EXTERN_I2C_BUS_MAX;
+ else
+ bl_ext_i2c_bus = bl_extern_get_i2c_bus_str(propdata);
+
+ sprintf(propname,"/bl_extern/extern_%d", index);
+ child_offset = fdt_path_offset(dtaddr, propname);
+ if (child_offset < 0) {
+ BLEXERR("bl: not find %s node: %s\n", propname,
+ fdt_strerror(child_offset));
+ return -1;
+ }
+ propdata = (char *)fdt_getprop(dtaddr, child_offset, "index", NULL);
+ if (propdata == NULL) {
+ BLEXERR("get index failed, exit\n");
+ return -1;
+ } else {
+ if (be32_to_cpup((u32*)propdata) != index) {
+ BLEXERR("index not match, exit\n");
+ return -1;
+ } else {
+ bl_extern->config->index = be32_to_cpup((u32*)propdata);
+ }
+ }
+ propdata = (char *)fdt_getprop(dtaddr, child_offset,
+ "extern_name", NULL);
+ if (propdata == NULL) {
+ BLEXERR("failed to get extern_name\n");
+ sprintf(bl_extern->config->name, "extern_%d", index);
+ } else {
+ strcpy(bl_extern->config->name, propdata);
+ }
+ propdata = (char *)fdt_getprop(dtaddr, child_offset, "type", NULL);
+ if (propdata == NULL) {
+ bl_extern->config->type = BL_EXTERN_MAX;
+ BLEXERR("get type failed, exit\n");
+ return -1;
+ } else {
+ bl_extern->config->type = be32_to_cpup((u32*)propdata);
+ }
+ propdata = (char *)fdt_getprop(dtaddr, child_offset,
+ "dim_max_min", NULL);
+ if (propdata == NULL) {
+ BLEXERR("failed to get bl_level_attr\n");
+ } else {
+ bl_extern->config->dim_max = be32_to_cpup((u32 *)propdata);
+ bl_extern->config->dim_min =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ }
+
+ switch (bl_extern->config->type) {
+ case BL_EXTERN_I2C:
+ propdata = (char *)fdt_getprop(dtaddr, child_offset,
+ "i2c_address", NULL);
+ if (propdata == NULL) {
+ BLEXERR("get %s i2c_address failed, exit\n",
+ bl_extern->config->name);
+ bl_extern->config->i2c_addr = 0xff;
+ return -1;
+ } else {
+ bl_extern->config->i2c_addr =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
+ }
+ /* compatible for kernel3.14 */
+ if (bl_ext_i2c_bus == BL_EXTERN_I2C_BUS_MAX) {
+ propdata = (char *)fdt_getprop(dtaddr, child_offset,
+ "i2c_bus", NULL);
+ if (propdata == NULL) {
+ BLEXERR("get %s i2c_bus failed, exit\n",
+ bl_extern->config->name);
+ bl_extern->config->i2c_bus = BL_EXTERN_I2C_BUS_MAX;
+ return -1;
+ } else {
+ bl_extern->config->i2c_bus =
+ bl_extern_get_i2c_bus_str(propdata);
+ }
+ } else {
+ bl_extern->config->i2c_bus = bl_ext_i2c_bus;
+ }
+ if (lcd_debug_print_flag)
+ aml_lcd_i2c_bus_print(bl_extern->config->i2c_bus);
+
+ propdata = (char *)fdt_getprop(dtaddr, child_offset,
+ "cmd_size", NULL);
+ if (propdata == NULL) {
+ BLEX("%s: no cmd_size\n", bl_extern->config->name);
+ bl_extern->config->cmd_size = 0;
+ } else {
+ bl_extern->config->cmd_size =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
+ }
+ if (lcd_debug_print_flag)
+ BLEX("%s: cmd_size=%d\n", bl_extern->config->name,
+ bl_extern->config->cmd_size);
+ if (bl_extern->config->cmd_size == 0)
+ break;
+
+ if (bl_extern->config->cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC) {
+ ret = bl_extern_init_table_dynamic_size_load_dts(
+ dtaddr, child_offset, bl_extern->config, 1);
+ if (ret)
+ break;
+ ret = bl_extern_init_table_dynamic_size_load_dts(
+ dtaddr, child_offset, bl_extern->config, 0);
+ } else {
+ ret = bl_extern_init_table_fixed_size_load_dts(
+ dtaddr, child_offset, bl_extern->config, 1);
+ if (ret)
+ break;
+ ret = bl_extern_init_table_fixed_size_load_dts(
+ dtaddr, child_offset, bl_extern->config, 0);
+ }
+ if (ret == 0)
+ bl_extern->config->init_loaded = 1;
+ break;
+ case BL_EXTERN_SPI:
+ propdata = (char *)fdt_getprop(dtaddr, child_offset,
+ "cmd_size", NULL);
+ if (propdata == NULL) {
+ BLEX("%s: no cmd_size\n", bl_extern->config->name);
+ bl_extern->config->cmd_size = 0;
+ } else {
+ bl_extern->config->cmd_size =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
+ }
+ if (lcd_debug_print_flag)
+ BLEX("%s: cmd_size=%d\n", bl_extern->config->name,
+ bl_extern->config->cmd_size);
+ if (bl_extern->config->cmd_size == 0)
+ break;
+
+ if (bl_extern->config->cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC) {
+ ret = bl_extern_init_table_dynamic_size_load_dts(
+ dtaddr, child_offset, bl_extern->config, 1);
+ if (ret)
+ break;
+ ret = bl_extern_init_table_dynamic_size_load_dts(
+ dtaddr, child_offset, bl_extern->config, 0);
+ } else {
+ ret = bl_extern_init_table_fixed_size_load_dts(
+ dtaddr, child_offset, bl_extern->config, 1);
+ if (ret)
+ break;
+ ret = bl_extern_init_table_fixed_size_load_dts(
+ dtaddr, child_offset, bl_extern->config, 0);
+ }
+ if (ret == 0)
+ bl_extern->config->init_loaded = 1;
+ break;
+ case BL_EXTERN_MIPI:
+ break;
+ default:
+ break;
+ }
+
+ return ret;
+}
+#endif
+
+static int bl_extern_add_driver(void)
+{
+ int ret = 0;
+ struct bl_extern_config_s *extconf = bl_extern_driver.config;
+
+ if (strcmp(extconf->name, "i2c_lp8556") == 0) {
+#ifdef CONFIG_AML_BL_EXTERN_I2C_LP8556
+ ret = i2c_lp8556_probe();
+#endif
+ } else if (strcmp(extconf->name, "mipi_lt070me05") == 0) {
+#ifdef CONFIG_AML_BL_EXTERN_MIPI_IT070ME05
+ ret = mipi_lt070me05_probe();
+#endif
+ } else {
+ BLEXERR("invalid device name: %s\n", extconf->name);
+ ret = -1;
+ }
+
+ if (ret) {
+ BLEXERR("add device driver failed %s(%d)\n",
+ extconf->name, extconf->index);
+ } else {
+ BLEX("add device driver %s(%d)\n",
+ extconf->name, extconf->index);
+ }
+
+ return ret;
+}
+
+int bl_extern_device_load(char *dtaddr, int index)
+{
+ int ret = 0;
+
+ bl_extern_status = 0;
+ bl_extern_level = 0;
+ bl_extern_driver.config = &bl_extern_config_dtf;
+ if (dtaddr) {
+ if (lcd_debug_print_flag)
+ BLEX("load bl_extern_config from dts\n");
+ bl_extern_config_from_dts(dtaddr, index);
+ }
+ bl_extern_add_driver();
+ bl_extern_driver.config_print = bl_extern_config_print;
+ BLEX("%s OK\n", __func__);
+
+ return ret;
+}
+
diff --git a/drivers/amlogic/media/vout/lcd/backlight/bl_extern/bl_extern.h b/drivers/amlogic/media/vout/lcd/backlight/bl_extern/bl_extern.h
new file mode 100644
index 0000000..fab1afb
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/bl_extern/bl_extern.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _BL_EXTERN_H_
+#define _BL_EXTERN_H_
+#include <amlogic/media/vout/lcd/bl_extern.h>
+
+#define BLEX(fmt, args...) printf("bl extern: "fmt"", ## args)
+#define BLEXERR(fmt, args...) printf("bl extern: error: "fmt"", ## args)
+#define BL_EXTERN_DRIVER "bl_extern"
+
+#ifdef CONFIG_SYS_I2C_AML
+extern struct i2c_platform g_aml_i2c_plat;
+#endif
+
+#ifdef CONFIG_AML_BL_EXTERN_I2C_LP8556
+extern int i2c_lp8556_probe(void);
+#endif
+
+#ifdef CONFIG_AML_BL_EXTERN_MIPI_IT070ME05
+extern int mipi_lt070me05_probe(void);
+#endif
+
+
+#endif
+
diff --git a/drivers/amlogic/media/vout/lcd/backlight/bl_extern/i2c_lp8556.c b/drivers/amlogic/media/vout/lcd/backlight/bl_extern/i2c_lp8556.c
new file mode 100644
index 0000000..98448f9
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/bl_extern/i2c_lp8556.c
@@ -0,0 +1,275 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/gpio.h>
+#include <fdtdec.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+#include <amlogic/media/vout/lcd/bl_extern.h>
+#include <amlogic/media/vout/lcd/lcd_i2c_dev.h>
+#include "bl_extern.h"
+#include "../lcd_common.h"
+#include "../lcd_reg.h"
+
+#define BL_EXTERN_NAME "i2c_lp8556"
+#define BL_EXTERN_TYPE BL_EXTERN_I2C
+#define BL_EXTERN_I2C_ADDR (0x58 >> 1) //7bit address
+
+//#define BL_EXT_I2C_PORT_INIT /* no need init i2c port default */
+
+#define BL_EXTERN_CMD_SIZE LCD_EXT_CMD_SIZE_DYNAMIC
+static unsigned char init_on_table[] = {
+ 0xc0, 2, 0xa2, 0x20,
+ 0xc0, 2, 0xa5, 0x54,
+ 0xc0, 2, 0x00, 0xff,
+ 0xc0, 2, 0x01, 0x05,
+ 0xc0, 2, 0xa2, 0x20,
+ 0xc0, 2, 0xa5, 0x54,
+ 0xc0, 2, 0xa1, 0xb7,
+ 0xc0, 2, 0xa0, 0xff,
+ 0xc0, 2, 0x00, 0x80,
+ 0xff, 0, /*ending*/
+};
+
+static unsigned char init_off_table[] = {
+ 0xff, 0, /*ending*/
+};
+
+static int bl_extern_power_cmd_dynamic_size(unsigned char *table, int flag)
+{
+ struct aml_bl_extern_get_driver *bl_extern = aml_bl_extern_get_driver();
+ int i = 0, j = 0, max_len = 0, step = 0;
+ unsigned char type, cmd_size;
+ int delay_ms, ret = 0;
+
+ if (flag)
+ max_len = bl_extern->config->init_on_cnt;
+ else
+ max_len = bl_extern->config->init_off_cnt;
+
+ while ((i + 1) < max_len) {
+ type = table[i];
+ if (type == LCD_EXT_CMD_TYPE_END)
+ break;
+ if (lcd_debug_print_flag) {
+ BLEX("%s: step %d: type=0x%02x, cmd_size=%d\n",
+ __func__, step, type, table[i + 1]);
+ }
+ cmd_size = table[i+1];
+ if (cmd_size == 0)
+ goto power_cmd_dynamic_next;
+ if ((i + 2 + cmd_size) > max_len)
+ break;
+
+ if (type == LCD_EXT_CMD_TYPE_NONE) {
+ /* do nothing */
+ } else if (type == LCD_EXT_CMD_TYPE_DELAY) {
+ delay_ms = 0;
+ for (j = 0; j < cmd_size; j++)
+ delay_ms += table[i + 2 + j];
+ if (delay_ms > 0)
+ mdelay(delay_ms);
+ } else if (type == LCD_EXT_CMD_TYPE_CMD) {
+ ret =
+ lcd_extern_i2c_write(bl_extern->config->i2c_bus,
+ bl_extern->config->i2c_addr,
+ &table[i + 2], cmd_size);
+ } else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
+ ret =
+ lcd_extern_i2c_write(bl_extern->config->i2c_bus,
+ bl_extern->config->i2c_addr,
+ &table[i + 2], (cmd_size - 1));
+ if (table[i+1+cmd_size] > 0)
+ mdelay(table[i + 1 + cmd_size]);
+ } else {
+ BLEXERR("%s: %s(%d): type 0x%02x invalid\n",
+ __func__, bl_extern->config->name,
+ bl_extern->config->index, type);
+ }
+power_cmd_dynamic_next:
+ i += (cmd_size + 2);
+ step++;
+ }
+
+ return ret;
+}
+
+static int bl_extern_power_cmd_fixed_size(unsigned char *table, int flag)
+{
+ struct aml_bl_extern_get_driver *bl_extern = aml_bl_extern_get_driver();
+ int i = 0, j, max_len, step = 0;
+ unsigned char type, cmd_size;
+ int delay_ms, ret = 0;
+
+ cmd_size = bl_extern->config->cmd_size;
+ if (cmd_size < 2) {
+ BLEXERR("%s: invalid cmd_size %d\n", __func__, cmd_size);
+ return -1;
+ }
+
+ if (flag)
+ max_len = bl_extern->config->init_on_cnt;
+ else
+ max_len = bl_extern->config->init_off_cnt;
+
+ while ((i + cmd_size) <= max_len) {
+ type = table[i];
+ if (type == LCD_EXT_CMD_TYPE_END)
+ break;
+ if (lcd_debug_print_flag) {
+ BLEX("%s: step %d: type=0x%02x, cmd_size=%d\n",
+ __func__, step, type, cmd_size);
+ }
+ if (type == LCD_EXT_CMD_TYPE_NONE) {
+ /* do nothing */
+ } else if (type == LCD_EXT_CMD_TYPE_DELAY) {
+ delay_ms = 0;
+ for (j = 0; j < (cmd_size - 1); j++)
+ delay_ms += table[i+1+j];
+ if (delay_ms > 0)
+ mdelay(delay_ms);
+ } else if (type == LCD_EXT_CMD_TYPE_CMD) {
+ ret =
+ lcd_extern_i2c_write(bl_extern->config->i2c_bus,
+ bl_extern->config->i2c_addr,
+ &table[i + 1], (cmd_size - 1));
+ } else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
+ ret =
+ lcd_extern_i2c_write(bl_extern->config->i2c_bus,
+ bl_extern->config->i2c_addr,
+ &table[i + 1], (cmd_size - 2));
+ if (table[i + cmd_size - 1] > 0)
+ mdelay(table[i + cmd_size - 1]);
+ } else {
+ BLEXERR("%s: %s(%d): type 0x%02x is invalid\n",
+ __func__, bl_extern->config->name,
+ bl_extern->config->index, type);
+ }
+ i += cmd_size;
+ step++;
+ }
+
+ return ret;
+}
+
+static int i2c_lp8556_power_ctrl(int flag)
+{
+ struct aml_bl_extern_driver_s *bl_extern = aml_bl_extern_get_driver();
+ unsigned char *table;
+ unsigned char cmd_size;
+ int ret = 0;
+
+ /* step 1: power prepare */
+#ifdef BL_EXT_I2C_PORT_INIT
+ aml_bl_extern_i2c_bus_change(bl_extern->config->i2c_bus);
+#endif
+
+ /* step 2: power cmd */
+ cmd_size = bl_extern->config->cmd_size;
+ if (flag)
+ table = bl_extern->config->init_on;
+ else
+ table = bl_extern->config->init_off;
+ if (cmd_size < 1) {
+ BLEXERR("%s: cmd_size %d is invalid\n", __func__, cmd_size);
+ ret = -1;
+ goto power_ctrl_next;
+ }
+ if (table == NULL) {
+ BLEXERR("%s: init_table %d is NULL\n", __func__, flag);
+ ret = -1;
+ goto power_ctrl_next;
+ }
+ if (cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC)
+ ret = bl_extern_power_cmd_dynamic_size(table, flag);
+ else
+ ret = bl_extern_power_cmd_fixed_size(table, flag);
+
+power_ctrl_next:
+ /* step 3: power finish */
+#ifdef BL_EXT_I2C_PORT_INIT
+ aml_bl_extern_i2c_bus_recovery();
+#endif
+
+ BLEX("%s: %s(%d): %d\n", __func__, bl_extern->config->name,
+ bl_extern->config->index, flag);
+ return ret;
+}
+
+static int i2c_lp8556_power_on(void)
+{
+ int ret;
+
+ ret = i2c_lp8556_power_ctrl(1);
+
+ return ret;
+}
+
+static int i2c_lp8556_power_off(void)
+{
+ return 0;
+}
+
+static int i2c_lp8556_set_level(unsigned int level)
+{
+ struct aml_bl_extern_get_driver *bl_extern = aml_bl_extern_get_driver();
+ unsigned char t_data[5];
+ int ret = 0;
+
+ if (bl_extern->config->dim_max > 255) {
+ t_data[0] = 0x10;
+ t_data[1] = level & 0xff;
+ t_data[2] = 0x11;
+ t_data[3] = (level >> 8) & 0xf;
+ ret = aml_lcd_extern_i2c_write(bl_extern->config->i2c_bus,
+ bl_extern->config->i2c_addr,
+ t_data, 4);
+ } else {
+ tData[0] = 0x0;
+ tData[1] = level & 0xff;
+ ret = aml_lcd_extern_i2c_write(bl_extern->config->i2c_bus,
+ bl_extern->config->i2c_addr,
+ t_data, 2);
+ }
+
+ return ret;
+}
+
+static int i2c_lp8556_update(void)
+{
+ struct aml_bl_extern_get_driver *bl_extern = aml_bl_extern_get_driver();
+
+ if (bl_extern == NULL) {
+ BLEXERR("%s driver is null\n", BL_EXTERN_NAME);
+ return -1;
+ }
+
+ bl_extern->device_power_on = i2c_lp8556_power_on;
+ bl_extern->device_power_off = i2c_lp8556_power_off;
+ bl_extern->device_bri_update = i2c_lp8556_set_level;
+
+ bl_extern->config->cmd_size = BL_EXTERN_CMD_SIZE;
+ if (!bl_extern->config->init_loaded) {
+ bl_extern->config->init_on = init_on_table;
+ bl_extern->config->init_on_cnt = sizeof(init_on_table);
+ bl_extern->config->init_off = init_off_table;
+ bl_extern->config->init_off_cnt = sizeof(init_off_table);
+ }
+
+ return 0;
+}
+
+int i2c_lp8556_probe(void)
+{
+ int ret = 0;
+
+ ret = i2c_lp8556_update();
+ if (lcd_debug_print_flag)
+ BLEX("%s: %d\n", __func__, ret);
+
+ return ret;
+}
+
diff --git a/drivers/amlogic/media/vout/lcd/backlight/bl_extern/mipi_lt070me05.c b/drivers/amlogic/media/vout/lcd/backlight/bl_extern/mipi_lt070me05.c
new file mode 100644
index 0000000..f6dcae6
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/bl_extern/mipi_lt070me05.c
@@ -0,0 +1,74 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/gpio.h>
+#include <fdtdec.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+#include <amlogic/media/vout/lcd/bl_extern.h>
+#include "bl_extern.h"
+#include "../lcd_common.h"
+
+
+#define BL_EXTERN_NAME "mipi_lt070me05"
+#define BL_EXTERN_TYPE BL_EXTERN_MIPI
+
+static int mipi_lt070me05_power_on(void)
+{
+ return 0;
+}
+
+static int mipi_lt070me05_power_off(void)
+{
+ return 0;
+}
+
+/******************** mipi command ********************
+ *format: data_type, num, data....
+ *special: data_type=0xff, num<0xff means delay ms, num=0xff means ending.
+ */
+static int mipi_lt070me05_set_level(unsigned int level)
+{
+ unsigned char payload[] = {0x15, 2, 0x51, 0xe6, 0xff, 0xff};
+
+ level &= 0xff;
+
+ payload[3] = level;
+#ifdef CONFIG_AML_LCD_TABLET
+ dsi_write_cmd(&payload[0]);
+#endif
+
+ return 0;
+}
+
+static int mipi_lt070me05_update(void)
+{
+ struct bl_extern_driver_s *bl_extern = bl_extern_get_driver();
+
+ if (bl_extern == NULL) {
+ BLEXERR("%s driver is null\n", BL_EXTERN_NAME);
+ return -1;
+ }
+
+ bl_extern->device_power_on = mipi_lt070me05_power_on;
+ bl_extern->device_power_off = mipi_lt070me05_power_off;
+ bl_extern->device_bri_update = mipi_lt070me05_set_level;
+
+ return 0;
+}
+
+int mipi_lt070me05_probe(void)
+{
+ int ret = 0;
+
+ ret = mipi_lt070me05_update();
+
+ BLEX("%s: %d\n", __func__, ret);
+
+ return ret;
+}
+
+
diff --git a/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/Kconfig b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/Kconfig
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/Kconfig
@@ -0,0 +1 @@
+
diff --git a/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/Makefile b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/Makefile
new file mode 100644
index 0000000..8b13789
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/Makefile
@@ -0,0 +1 @@
+
diff --git a/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/global.c b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/global.c
new file mode 100644
index 0000000..7d6db18
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/global.c
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/gpio.h>
+#include <fdtdec.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+#include <amlogic/media/vout/lcd/bl_ldim.h>
+#include "../lcd_reg.h"
+#include "../lcd_common.h"
+#include "ldim_drv.h"
+#include "ldim_dev_drv.h"
+
+static int global_on_flag;
+
+static int global_hw_init_on(void)
+{
+ struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
+
+ ldim_set_duty_pwm(&ldim_drv->ldev_conf->ldim_pwm_config);
+ ldim_set_duty_pwm(&ldim_drv->ldev_conf->analog_pwm_config);
+
+ ldim_drv->pinmux_ctrl(1);
+ mdelay(2);
+ ldim_set_gpio(ldim_drv->ldev_conf->en_gpio,
+ ldim_drv->ldev_conf->en_gpio_on);
+ mdelay(20);
+
+ return 0;
+}
+
+static int global_hw_init_off(void)
+{
+ struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
+
+ ldim_drv->pinmux_ctrl(0);
+ ldim_set_gpio(ldim_drv->ldev_conf->en_gpio,
+ ldim_drv->ldev_conf->en_gpio_off);
+
+ return 0;
+}
+
+static unsigned int global_get_value(unsigned int level)
+{
+ struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
+
+ unsigned int val;
+ unsigned int dim_max, dim_min;
+
+ dim_max = ldim_drv->ldev_conf->dim_max;
+ dim_min = ldim_drv->ldev_conf->dim_min;
+
+ val = dim_min + ((level * (dim_max - dim_min)) / LD_DATA_MAX);
+
+ return val;
+}
+
+static int global_smr(unsigned short *buf, unsigned char len)
+{
+ struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
+ unsigned short val;
+
+ val = global_get_value(buf[0]);
+ ldim_drv->ldev_conf->ldim_pwm_config.pwm_duty = val;
+
+ if (global_on_flag == 0) {
+ if (lcd_debug_print_flag)
+ LDIMPR("%s: on_flag=%d\n", __func__, global_on_flag);
+ return 0;
+ }
+
+ if (len != 1) {
+ LDIMERR("%s: data len %d invalid\n", __func__, len);
+ return -1;
+ }
+
+ ldim_set_duty_pwm(&ldim_drv->ldev_conf->ldim_pwm_config);
+
+ return 0;
+}
+
+static void global_dim_range_update(void)
+{
+ struct ldim_driver_s *ldim_drv = ldim_get_driver();
+ struct ldim_dev_config_s *ldim_dev;
+
+ ldim_dev = ldim_drv->ldev_conf;
+ ldim_dev->dim_max = ldim_dev->ldim_pwm_config.pwm_duty_max;
+ ldim_dev->dim_min = ldim_dev->ldim_pwm_config.pwm_duty_min;
+}
+
+static int global_power_on(void)
+{
+ global_hw_init_on();
+ global_on_flag = 1;
+
+ LDIMPR("%s: ok\n", __func__);
+ return 0;
+}
+
+static int global_power_off(void)
+{
+ global_on_flag = 0;
+ global_hw_init_off();
+
+ LDIMPR("%s: ok\n", __func__);
+ return 0;
+}
+
+static int global_ldim_driver_update(struct aml_ldim_driver_s *ldim_drv)
+{
+ struct ldim_dev_config_s *ldim_dev = ldim_drv->ldev_conf;
+
+ ldim_dev->ldim_pwm_config.pwm_duty_max = ldim_dev->dim_max;
+ ldim_dev->ldim_pwm_config.pwm_duty_min = ldim_dev->dim_min;
+ ldim_dev->dim_range_update = global_dim_range_update;
+
+ ldim_drv->device_power_on = global_power_on;
+ ldim_drv->device_power_off = global_power_off;
+ ldim_drv->device_bri_update = global_smr;
+
+ return 0;
+}
+
+int ldim_dev_global_probe(struct aml_ldim_driver_s *ldim_drv)
+{
+ global_on_flag = 0;
+ global_ldim_driver_update(ldim_drv);
+
+ return 0;
+}
+
+int ldim_dev_global_remove(struct aml_ldim_driver_s *ldim_drv)
+{
+ return 0;
+}
+
diff --git a/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/iw7027.c b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/iw7027.c
new file mode 100644
index 0000000..1d38641
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/iw7027.c
@@ -0,0 +1,434 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/arch/gpio.h>
+#include <fdtdec.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+#include <amlogic/media/vout/lcd/bl_ldim.h>
+#include "../lcd_reg.h"
+#include "../lcd_common.h"
+#include "ldim_drv.h"
+#include "ldim_dev_drv.h"
+
+#define NORMAL_MSG (0<<7)
+#define BROADCAST_MSG (1<<7)
+#define BLOCK_DATA (0<<6)
+#define SINGLE_DATA (1<<6)
+#define IW7027_DEV_ADDR 1
+
+static int iw7027_on_flag;
+
+struct iw7027 {
+ int cs_hold_delay;
+ int cs_clk_delay;
+ unsigned char cmd_size;
+ unsigned char *init_data;
+ unsigned int init_data_cnt;
+ struct spi_slave *spi;
+};
+static struct iw7027 *bl_iw7027;
+
+static unsigned char *val_brightness;
+
+#if 0
+static unsigned char iw7027_init_data[LDIM_INIT_ON_SIZE] = {
+ 0xc0, 0x23, 0x03,
+ 0xc0, 0x24, 0xff,
+ 0xc0, 0x25, 0x00,
+ 0xc0, 0x26, 0x00,
+ 0xc0, 0x27, 0x60,
+ 0xc0, 0x29, 0x00,
+ 0xc0, 0x2a, 0x00,
+ 0xc0, 0x2b, 0x00,
+ 0xc0, 0x2c, 0x73,
+ 0xc0, 0x2d, 0x37,
+ 0xc0, 0x31, 0x93,
+ 0xc0, 0x32, 0x0f,
+ 0xc0, 0x33, 0xff,
+ 0xc0, 0x34, 0xc8,
+ 0xc0, 0x35, 0xbf,
+ 0xff, 0x00, 0x00,
+};
+#endif
+
+//iw7027 register write
+static int iw7027_wreg(struct spi_slave *spi, unsigned char addr, unsigned char val)
+{
+ unsigned char tbuf[3];
+ int ret;
+
+ if (lcd_debug_print_flag)
+ LDIMPR("%s: 0x%02x = 0x%02x\n", __func__, addr, val);
+
+ tbuf[0] = NORMAL_MSG | SINGLE_DATA | IW7027_DEV_ADDR;
+ tbuf[1] = addr & 0x7f;
+ tbuf[2] = val;
+ ret = ldim_spi_write(spi, tbuf, 3);
+
+ return ret;
+}
+
+//iw7027 register read
+static int iw7027_rreg(struct spi_slave *spi, unsigned char addr,
+ unsigned char *val)
+{
+ unsigned char tbuf[4], rbuf[4], temp;
+ int ret;
+
+ /*set read flag*/
+ temp = (addr >= 0x80) ? 0x80 : 0x0;
+ iw7027_wreg(spi, 0x78, temp);
+
+ tbuf[0] = NORMAL_MSG | SINGLE_DATA | IW7027_DEV_ADDR;
+ tbuf[1] = addr | 0x80;
+ tbuf[2] = 0;
+ ret = ldim_spi_read(spi, tbuf, 3, rbuf, 1);
+ *val = rbuf[3];
+
+ return ret;
+}
+
+//iw7027 block write
+static int iw7027_wregs(struct spi_slave *spi, unsigned char addr,
+ unsigned char *val, int len)
+{
+ unsigned char tbuf[30];
+ int ret, i;
+
+ if (lcd_debug_print_flag) {
+ LDIMPR("%s: ", __func__);
+ for (i = 0; i < len; i++)
+ printf("0x%02x ", val[i]);
+ printf("\n");
+ }
+
+ tbuf[0] = NORMAL_MSG | BLOCK_DATA | IW7027_DEV_ADDR;
+ tbuf[1] = len;
+ tbuf[2] = addr & 0x7f;
+ memcpy(&tbuf[3], val, len);
+ ret = ldim_spi_write(spi, tbuf, (len + 3));
+
+ return ret;
+}
+
+static int ldim_power_cmd_dynamic_size(void)
+{
+ unsigned char *table;
+ int i = 0, j, step = 0, max_len = 0;
+ unsigned char type, cmd_size;
+ int delay_ms, ret = 0;
+
+ table = bl_iw7027->init_data;
+ max_len = bl_iw7027->init_data_cnt;
+
+ while ((i + 1) < max_len) {
+ type = table[i];
+ if (type == LCD_EXT_CMD_TYPE_END)
+ break;
+ if (lcd_debug_print_flag) {
+ LDIMPR("%s: step %d: type=0x%02x, cmd_size=%d\n",
+ __func__, step, type, table[i+1]);
+ }
+ cmd_size = table[i+1];
+ if (cmd_size == 0)
+ goto power_cmd_dynamic_next;
+ if ((i + 2 + cmd_size) > max_len)
+ break;
+
+ if (type == LCD_EXT_CMD_TYPE_NONE) {
+ /* do nothing */
+ } else if (type == LCD_EXT_CMD_TYPE_DELAY) {
+ delay_ms = 0;
+ for (j = 0; j < cmd_size; j++)
+ delay_ms += table[i+2+j];
+ if (delay_ms > 0)
+ mdelay(delay_ms);
+ } else if (type == LCD_EXT_CMD_TYPE_CMD) {
+ ret = iw7027_wreg(bl_iw7027->spi,
+ table[i+2], table[i+3]);
+ udelay(1);
+ } else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
+ ret = iw7027_wreg(bl_iw7027->spi,
+ table[i+2], table[i+3]);
+ udelay(1);
+ if (table[i+4] > 0)
+ mdelay(table[i+4]);
+ } else {
+ LDIMERR("%s: type 0x%02x invalid\n", __func__, type);
+ }
+power_cmd_dynamic_next:
+ i += (cmd_size + 2);
+ step++;
+ }
+
+ return ret;
+}
+
+static int ldim_power_cmd_fixed_size(void)
+{
+ unsigned char *table;
+ int i = 0, j, step = 0, max_len = 0;
+ unsigned char type, cmd_size;
+ int delay_ms, ret = 0;
+
+ cmd_size = bl_iw7027->cmd_size;
+ if (cmd_size < 2) {
+ LDIMERR("%s: invalid cmd_size %d\n", __func__, cmd_size);
+ return -1;
+ }
+
+ table = bl_iw7027->init_data;
+ max_len = bl_iw7027->init_data_cnt;
+
+ while ((i + cmd_size) <= max_len) {
+ type = table[i];
+ if (type == LCD_EXT_CMD_TYPE_END)
+ break;
+ if (lcd_debug_print_flag) {
+ LDIMPR("%s: step %d: type=0x%02x, cmd_size=%d\n",
+ __func__, step, type, cmd_size);
+ }
+ if (type == LCD_EXT_CMD_TYPE_NONE) {
+ /* do nothing */
+ } else if (type == LCD_EXT_CMD_TYPE_DELAY) {
+ delay_ms = 0;
+ for (j = 0; j < (cmd_size - 1); j++)
+ delay_ms += table[i+1+j];
+ if (delay_ms > 0)
+ mdelay(delay_ms);
+ } else if (type == LCD_EXT_CMD_TYPE_CMD) {
+ ret = iw7027_wreg(bl_iw7027->spi,
+ table[i+1], table[i+2]);
+ udelay(1);
+ } else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
+ ret = iw7027_wreg(bl_iw7027->spi,
+ table[i+1], table[i+2]);
+ udelay(1);
+ if (table[i+3] > 0)
+ mdelay(table[i+3]);
+ } else {
+ LDIMERR("%s: type 0x%02x invalid\n", __func__, type);
+ }
+ i += cmd_size;
+ step++;
+ }
+
+ return ret;
+}
+
+static int iw7027_power_on_init(void)
+{
+ unsigned char cmd_size;
+ int ret = 0;
+
+ cmd_size = bl_iw7027->cmd_size;
+ if (cmd_size < 2) {
+ LDIMERR("%s: invalid cmd_size %d\n", __func__, cmd_size);
+ return -1;
+ }
+ if (cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC)
+ ret = ldim_power_cmd_dynamic_size();
+ else
+ ret = ldim_power_cmd_fixed_size();
+
+ return ret;
+}
+
+static int iw7027_hw_init_on(void)
+{
+ int i;
+ unsigned char reg_duty_chk = 0 , reg_chk = 0;
+ struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
+
+ /* step 1: system power_on */
+ LDIMPR("%s: iw7027 system power_on\n", __func__);
+ ldim_set_gpio(ldim_drv->ldev_conf->en_gpio,
+ ldim_drv->ldev_conf->en_gpio_on);
+ ldim_set_duty_pwm(&ldim_drv->ldev_conf->ldim_pwm_config);
+ ldim_set_duty_pwm(&ldim_drv->ldev_conf->analog_pwm_config);
+
+ /* step 2: delay for internal logic stable */
+ mdelay(10);
+
+ /* step 3: SPI communication check */
+ LDIMPR("%s: SPI Communication Check\n", __func__);
+ for (i = 0; i <= 10; i++) {
+ iw7027_wreg(bl_iw7027->spi, 0x00, 0x06);
+ iw7027_rreg(bl_iw7027->spi, 0x00, ®_chk);
+ if (reg_chk == 0x06)
+ break;
+ if (i == 10) {
+ LDIMERR("%s: SPI communication check error\n",
+ __func__);
+ }
+ }
+
+ /* step 4: configure initial registers */
+ LDIMPR("%s: Write initial control registers\n", __func__);
+ iw7027_power_on_init();
+
+ /* step 5: supply stable vsync */
+ LDIMPR("%s: open Vsync\n", __func__);
+ ldim_drv->pinmux_ctrl(1);
+
+ /* step 6: delay for system clock and light bar PSU stable */
+ mdelay(550);
+
+ /* step 7: start calibration */
+ LDIMPR("%s: start calibration\n", __func__);
+ iw7027_wreg(bl_iw7027->spi, 0x00, 0x07);
+ mdelay(200);
+
+ /* step 8: calibration done or not */
+ i = 0;
+ while (i++ < 1000) {
+ iw7027_rreg(bl_iw7027->spi, 0xb3, ®_duty_chk);
+ /*VDAC statue reg :FB1=[0x5] FB2=[0x50]*/
+ /*The current platform using FB1*/
+ if ((reg_duty_chk & 0xf) == 0x05)
+ break;
+ mdelay(1);
+ }
+ LDIMPR("%s: calibration done: [%d] = %x\n", __func__, i, reg_duty_chk);
+
+ return 0;
+}
+
+static int iw7027_hw_init_off(void)
+{
+ struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
+
+ ldim_drv->pinmux_ctrl(0);
+ ldim_set_gpio(ldim_drv->ldev_conf->en_gpio,
+ ldim_drv->ldev_conf->en_gpio_off);
+
+ return 0;
+}
+
+static unsigned int dim_max, dim_min;
+static unsigned int iw7027_get_value(unsigned int level)
+{
+ unsigned int val;
+
+ val = dim_min + ((level * (dim_max - dim_min)) / LD_DATA_MAX);
+
+ return val;
+}
+
+static int iw7027_smr(unsigned short *buf, unsigned char len)
+{
+ unsigned int i, temp;
+ unsigned short num;
+ struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
+
+ if (iw7027_on_flag == 0) {
+ LDIMPR("%s: on_flag=%d\n", __func__, iw7027_on_flag);
+ return 0;
+ }
+ num = ldim_drv->ldev_conf->bl_regnum;
+ if (len != num) {
+ LDIMERR("%s: data len %d invalid\n", __func__, len);
+ return -1;
+ }
+ if (val_brightness == NULL) {
+ LDIMERR("%s: val_brightness is null\n", __func__);
+ return -1;
+ }
+
+ dim_max = ldim_drv->ldev_conf->dim_max;
+ dim_min = ldim_drv->ldev_conf->dim_min;
+
+ for (i = 0; i < num; i++) {
+ temp = iw7027_get_value(buf[i]);
+ val_brightness[2*i] = (temp >> 8) & 0xf;
+ val_brightness[2*i+1] = temp & 0xff;
+ }
+
+ iw7027_wregs(bl_iw7027->spi, 0x40, val_brightness, (num * 2));
+
+ return 0;
+}
+
+static int iw7027_power_on(void)
+{
+ iw7027_hw_init_on();
+ iw7027_on_flag = 1;
+
+ LDIMPR("%s: ok\n", __func__);
+ return 0;
+}
+
+static int iw7027_power_off(void)
+{
+ iw7027_on_flag = 0;
+ iw7027_hw_init_off();
+
+ LDIMPR("%s: ok\n", __func__);
+ return 0;
+}
+
+static int iw7027_ldim_driver_update(struct aml_ldim_driver_s *ldim_drv)
+{
+ ldim_drv->device_power_on = iw7027_power_on;
+ ldim_drv->device_power_off = iw7027_power_off;
+ ldim_drv->device_bri_update = iw7027_smr;
+ return 0;
+}
+
+int ldim_dev_iw7027_probe(struct aml_ldim_driver_s *ldim_drv)
+{
+ if (ldim_drv->spi_info->spi == NULL) {
+ LDIMERR("%s: spi is null\n", __func__);
+ return -1;
+ }
+
+ bl_iw7027 = (struct iw7027 *)malloc(sizeof(struct iw7027));
+ if (bl_iw7027 == NULL) {
+ LDIMERR("iw7027 malloc error\n");
+ return -1;
+ }
+ memset(bl_iw7027, 0, sizeof(struct iw7027));
+
+ iw7027_on_flag = 0;
+
+ bl_iw7027->spi = ldim_drv->spi_info->spi;
+ bl_iw7027->cs_hold_delay = ldim_drv->ldev_conf->cs_hold_delay;
+ bl_iw7027->cs_clk_delay = ldim_drv->ldev_conf->cs_clk_delay;
+ bl_iw7027->cmd_size = ldim_drv->ldev_conf->cmd_size;
+ bl_iw7027->init_data = ldim_drv->ldev_conf->init_on;
+ bl_iw7027->init_data_cnt = ldim_drv->ldev_conf->init_on_cnt;
+
+ val_brightness = (unsigned char *)malloc(
+ ldim_drv->ldev_conf->bl_regnum * 2 * sizeof(unsigned char));
+ if (val_brightness == NULL) {
+ LDIMERR("malloc val_brightness failed\n");
+ free(bl_iw7027);
+ return -1;
+ }
+
+ iw7027_ldim_driver_update(ldim_drv);
+
+ printf("%s: ok\n", __func__);
+
+ return 0;
+}
+
+int ldim_dev_iw7027_remove(struct aml_ldim_driver_s *ldim_drv)
+{
+ if (val_brightness) {
+ free(val_brightness);
+ val_brightness = NULL;
+ }
+
+ if (bl_iw7027) {
+ free(bl_iw7027);
+ bl_iw7027 = NULL;
+ }
+ return 0;
+}
+
diff --git a/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ldim_dev_drv.c b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ldim_dev_drv.c
new file mode 100644
index 0000000..14abcd1
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ldim_dev_drv.c
@@ -0,0 +1,1297 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/arch/gpio.h>
+#include <fdtdec.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+#include <amlogic/media/vout/lcd/bl_ldim.h>
+#include "../lcd_reg.h"
+#include "../lcd_common.h"
+#include "ldim_drv.h"
+#include "ldim_dev_drv.h"
+
+static struct ldim_dev_config_s *ldim_dev_config;
+static int ldim_dev_probe_flag;
+
+struct ldim_spi_dev_info_s ldim_spi_info = {
+ .modalias = "ldim_dev",
+ .spi_name = "none",
+ .mode = SPI_MODE_0,
+ .max_speed_hz = 1000000, /* 1MHz */
+ .bus_num = 0, /* SPI bus No. */
+ .chip_select = 0, /* the device index on the spi bus */
+ .wordlen = 8,
+ .spi = NULL,
+};
+
+void ldim_set_gpio(int index, int value)
+{
+ int gpio;
+ char *str;
+
+ if (index >= BL_GPIO_NUM_MAX) {
+ LDIMERR("%s: invalid index %d\n", __func__, index);
+ return;
+ }
+ str = ldim_dev_config->gpio_name[index];
+ gpio = aml_lcd_gpio_name_map_num(str);
+ switch (value) {
+ case LCD_GPIO_OUTPUT_LOW:
+ case LCD_GPIO_OUTPUT_HIGH:
+ aml_lcd_gpio_set(gpio, value);
+ break;
+ case LCD_GPIO_INPUT:
+ default:
+ value = LCD_GPIO_INPUT;
+ aml_lcd_gpio_set(gpio, value);
+ break;
+ }
+ if (lcd_debug_print_flag)
+ LDIMPR("set gpio %s[%d] value: %d\n", str, index, value);
+}
+
+unsigned int ldim_get_gpio(int index)
+{
+ int gpio;
+ char *str;
+ unsigned int value;
+
+ if (index >= BL_GPIO_NUM_MAX) {
+ LDIMERR("%s: invalid index %d\n", __func__, index);
+ return -1;
+ str = ldim_dev_config->gpio_name[index];
+ gpio = aml_lcd_gpio_name_map_num(str);
+ value = aml_lcd_gpio_input_get(gpio);
+ return value;
+}
+/* *************************************** */
+
+static unsigned int pwm_reg[6] = {
+ PWM_PWM_A,
+ PWM_PWM_B,
+ PWM_PWM_C,
+ PWM_PWM_D,
+ PWM_PWM_E,
+ PWM_PWM_F,
+};
+
+void ldim_set_duty_pwm(struct bl_pwm_config_s *bl_pwm)
+{
+ unsigned int pwm_hi = 0, pwm_lo = 0;
+ unsigned int port = bl_pwm->pwm_port;
+ unsigned int vs[4], ve[4], sw, n, i;
+
+ if (bl_pwm->pwm_port >= BL_PWM_MAX)
+ return;
+
+ bl_pwm->pwm_level = bl_pwm->pwm_cnt * bl_pwm->pwm_duty / 100;
+
+ if (lcd_debug_print_flag) {
+ LDIMPR("pwm port %d: duty=%d%%, duty_max=%d, duty_min=%d\n",
+ bl_pwm->pwm_port, bl_pwm->pwm_duty,
+ bl_pwm->pwm_duty_max, bl_pwm->pwm_duty_min);
+ }
+
+ switch (bl_pwm->pwm_method) {
+ case BL_PWM_POSITIVE:
+ pwm_hi = bl_pwm->pwm_level;
+ pwm_lo = bl_pwm->pwm_cnt - bl_pwm->pwm_level;
+ break;
+ case BL_PWM_NEGATIVE:
+ pwm_lo = bl_pwm->pwm_level;
+ pwm_hi = bl_pwm->pwm_cnt - bl_pwm->pwm_level;
+ break;
+ default:
+ LDIMERR("port %d: invalid pwm_method %d\n",
+ port, bl_pwm->pwm_method);
+ break;
+ }
+ if (lcd_debug_print_flag) {
+ LDIMPR("port %d: pwm_cnt=%d, pwm_hi=%d, pwm_lo=%d\n",
+ port, bl_pwm->pwm_cnt, pwm_hi, pwm_lo);
+ }
+
+ switch (port) {
+ case BL_PWM_A:
+ case BL_PWM_B:
+ case BL_PWM_C:
+ case BL_PWM_D:
+ case BL_PWM_E:
+ case BL_PWM_F:
+ lcd_cbus_write(pwm_reg[port], (pwm_hi << 16) | pwm_lo);
+ break;
+ case BL_PWM_VS:
+ memset(vs, 0xffff, sizeof(unsigned int) * 4);
+ memset(ve, 0xffff, sizeof(unsigned int) * 4);
+ n = bl_pwm->pwm_freq;
+ sw = (bl_pwm->pwm_cnt * 10 / n + 5) / 10;
+ pwm_hi = (pwm_hi * 10 / n + 5) / 10;
+ pwm_hi = (pwm_hi > 1) ? pwm_hi : 1;
+ if (lcd_debug_print_flag)
+ LDIMPR("n=%d, sw=%d, pwm_high=%d\n", n, sw, pwm_hi);
+ for (i = 0; i < n; i++) {
+ vs[i] = 1 + (sw * i);
+ ve[i] = vs[i] + pwm_hi - 1;
+ if (lcd_debug_print_flag)
+ LDIMPR("vs[%d]=%d, ve[%d]=%d\n", i, vs[i], i, ve[i]);
+ }
+ lcd_vcbus_write(VPU_VPU_PWM_V0, (ve[0] << 16) | (vs[0]));
+ lcd_vcbus_write(VPU_VPU_PWM_V1, (ve[1] << 16) | (vs[1]));
+ lcd_vcbus_write(VPU_VPU_PWM_V2, (ve[2] << 16) | (vs[2]));
+ lcd_vcbus_write(VPU_VPU_PWM_V3, (ve[3] << 16) | (vs[3]));
+ break;
+ default:
+ break;
+ }
+}
+
+static int ldim_set_pinmux_pwm(int status, struct bl_pwm_config_s *bl_pwm)
+{
+ int i;
+
+ if (lcd_debug_print_flag)
+ LDIMPR("%s: %d\n", __func__, status);
+
+ if (status) {
+ bl_pwm_ctrl(bl_pwm, 1);
+ /* set pinmux */
+ bl_pwm->pinmux_flag = 1;
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (bl_pwm->pinmux_clr[i][0] == LCD_PINMUX_END)
+ break;
+ lcd_pinmux_clr_mask(bl_pwm->pinmux_clr[i][0],
+ bl_pwm->pinmux_clr[i][1]);
+ if (lcd_debug_print_flag) {
+ LDIMPR("%s: port=%d, pinmux_clr=%d,0x%08x\n",
+ __func__, bl_pwm->pwm_port,
+ bl_pwm->pinmux_clr[i][0],
+ bl_pwm->pinmux_clr[i][1]);
+ }
+ i++;
+ }
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (bl_pwm->pinmux_set[i][0] == LCD_PINMUX_END)
+ break;
+ lcd_pinmux_set_mask(bl_pwm->pinmux_set[i][0],
+ bl_pwm->pinmux_set[i][1]);
+ if (lcd_debug_print_flag) {
+ LDIMPR("%s: port=%d, pinmux_set=%d,0x%08x\n",
+ __func__, bl_pwm->pwm_port,
+ bl_pwm->pinmux_set[i][0],
+ bl_pwm->pinmux_set[i][1]);
+ }
+ i++;
+ }
+ } else {
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (bl_pwm->pinmux_set[i][0] == LCD_PINMUX_END)
+ break;
+ lcd_pinmux_clr_mask(bl_pwm->pinmux_set[i][0],
+ bl_pwm->pinmux_set[i][1]);
+ if (lcd_debug_print_flag) {
+ LDIMPR("%s: port=%d, pinmux_clr=%d,0x%08x\n",
+ __func__, bl_pwm->pwm_port,
+ bl_pwm->pinmux_set[i][0],
+ bl_pwm->pinmux_set[i][1]);
+ }
+ i++;
+ }
+ bl_pwm->pinmux_flag = 0;
+
+ bl_pwm_ctrl(bl_pwm, 0);
+ }
+
+ return 0;
+}
+
+static int ldim_pwm_pinmux_ctrl(int status)
+{
+ if (ldim_dev_config->ldim_pwm_config.pwm_port >= BL_PWM_MAX)
+ return 0;
+
+ if (lcd_debug_print_flag)
+ LDIMPR("%s: %d\n", __func__, status);
+
+ ldim_set_pinmux_pwm(status, &ldim_dev_config->ldim_pwm_config);
+ if (ldim_dev_config->analog_pwm_config.pwm_port < BL_PWM_VS)
+ ldim_set_pinmux_pwm(status,
+ &ldim_dev_config->analog_pwm_config);
+
+ return 0;
+}
+
+static void aml_ldim_dev_init_table_dynamic_size_print
+ (struct ldim_dev_config_s *ldconf, int flag)
+{
+ int i, j, max_len;
+ unsigned char cmd_size;
+ unsigned char *table;
+
+ if (flag) {
+ printf("power on:\n");
+ table = ldconf->init_on;
+ max_len = ldconf->init_on_cnt;
+ } else {
+ printf("power off:\n");
+ table = ldconf->init_off;
+ max_len = ldconf->init_off_cnt;
+ }
+ if (table == NULL) {
+ LDIMERR("init_table %d is NULL\n", flag);
+ return;
+ }
+
+ i = 0;
+ while ((i + 1) < max_len) {
+ if (table[i] == LCD_EXT_CMD_TYPE_END) {
+ printf(" 0x%02x,%d,\n", table[i], table[i+1]);
+ break;
+ }
+ cmd_size = table[i+1];
+ printf(" 0x%02x,%d,", table[i], cmd_size);
+ if (cmd_size == 0)
+ goto init_table_dynamic_print_next;
+ if (i + 2 + cmd_size > max_len) {
+ printf("cmd_size out of support\n");
+ break;
+ }
+
+ if (table[i] == LCD_EXT_CMD_TYPE_DELAY) {
+ for (j = 0; j < cmd_size; j++)
+ printf("%d,", table[i+2+j]);
+ } else if (table[i] == LCD_EXT_CMD_TYPE_CMD) {
+ for (j = 0; j < cmd_size; j++)
+ printf("0x%02x,", table[i+2+j]);
+ } else if (table[i] == LCD_EXT_CMD_TYPE_CMD_DELAY) {
+ for (j = 0; j < (cmd_size - 1); j++)
+ printf("0x%02x,", table[i+2+j]);
+ printf("%d,", table[i+cmd_size+1]);
+ } else {
+ for (j = 0; j < cmd_size; j++)
+ printf("0x%02x,", table[i+2+j]);
+ }
+init_table_dynamic_print_next:
+ printf("\n");
+ i += (cmd_size + 2);
+ }
+}
+
+static void ldim_dev_init_table_fixed_size_print(
+ struct ldim_dev_config_s *ldconf, int flag)
+{
+ int i, j, max_len;
+ unsigned char cmd_size;
+ unsigned char *table;
+
+ cmd_size = ldconf->cmd_size;
+ if (flag) {
+ printf("power on:\n");
+ table = ldconf->init_on;
+ max_len = ldconf->init_on_cnt;
+ } else {
+ printf("power off:\n");
+ table = ldconf->init_off;
+ max_len = ldconf->init_off_cnt;
+ }
+ if (table == NULL) {
+ LDIMERR("init_table %d is NULL\n", flag);
+ return;
+ }
+
+ i = 0;
+ while ((i + cmd_size) <= max_len) {
+ printf(" ");
+ for (j = 0; j < cmd_size; j++)
+ printf("0x%02x,", table[i+j]);
+ printf("\n");
+
+ if (table[i] == LCD_EXT_CMD_TYPE_END)
+ break;
+ i += cmd_size;
+ }
+}
+
+static void ldim_device_config_print(void)
+{
+ struct bl_pwm_config_s *bl_pwm;
+
+ if (ldim_dev_config == NULL) {
+ LDIMERR("%s: ldim_dev_config is null\n", __func__);
+ return;
+ }
+
+ printf("\ndev_name = %s\n"
+ "en_gpio = %d\n"
+ "en_gpio_on = %d\n"
+ "en_gpio_off = %d\n"
+ "dim_max = 0x%03x\n"
+ "dim_min = 0x%03x\n"
+ "region_num = %d\n\n"
+ "device_count = %d\n\n",
+ ldim_dev_config->name,
+ ldim_dev_config->en_gpio,
+ ldim_dev_config->en_gpio_on,
+ ldim_dev_config->en_gpio_off,
+ ldim_dev_config->dim_min,
+ ldim_dev_config->dim_max,
+ ldim_dev_config->bl_regnum,
+ ldim_dev_config->device_count);
+
+ switch (ldim_dev_config->type) {
+ case LDIM_DEV_TYPE_SPI:
+ printf("spi_pointer = 0x%p\n"
+ "spi_modalias = %s\n"
+ "spi_mode = %d\n"
+ "spi_max_speed_hz = %d\n"
+ "spi_bus_num = %d\n"
+ "spi_chip_select = %d\n"
+ "cs_hold_delay = %d\n"
+ "cs_clk_delay = %d\n"
+ "write_check = %d\n\n",
+ ldim_spi_info.spi,
+ ldim_spi_info.modalias,
+ ldim_spi_info.mode,
+ ldim_spi_info.max_speed_hz,
+ ldim_spi_info.bus_num,
+ ldim_spi_info.chip_select,
+ ldim_dev_config->cs_hold_delay,
+ ldim_dev_config->cs_clk_delay,
+ ldim_dev_config->write_check);
+ break;
+ case LDIM_DEV_TYPE_I2C:
+ break;
+ case LDIM_DEV_TYPE_NORMAL:
+ default:
+ break;
+ }
+
+ bl_pwm = &ldim_dev_config->ldim_pwm_config;
+ if (bl_pwm->pwm_port < BL_PWM_MAX) {
+ printf("ldim_pwm_port = %d\n"
+ "ldim_pwm_pol = %d\n"
+ "ldim_pwm_freq = %d\n"
+ "ldim_pwm_duty = %d%%\n"
+ "ldim_pwm_pinmux_flag = %d\n\n",
+ bl_pwm->pwm_port, bl_pwm->pwm_method,
+ bl_pwm->pwm_freq, bl_pwm->pwm_duty,
+ bl_pwm->pinmux_flag);
+ }
+
+ bl_pwm = &ldim_dev_config->analog_pwm_config;
+ if (bl_pwm->pwm_port < BL_PWM_VS) {
+ printf("analog_pwm_port = %d\n"
+ "analog_pwm_pol = %d\n"
+ "analog_pwm_freq = %d\n"
+ "analog_pwm_duty = %d%%\n"
+ "analog_pwm_duty_max = %d%%\n"
+ "analog_pwm_duty_min = %d%%\n"
+ "analog_pwm_pinmux_flag = %d\n\n",
+ bl_pwm->pwm_port, bl_pwm->pwm_method,
+ bl_pwm->pwm_freq, bl_pwm->pwm_duty,
+ bl_pwm->pwm_duty_max, bl_pwm->pwm_duty_min,
+ bl_pwm->pinmux_flag);
+ }
+
+ if (ldim_dev_config->cmd_size > 0) {
+ printf("init_loaded = %d\n"
+ "cmd_size = %d\n"
+ "init_on_cnt = %d\n"
+ "init_off_cnt = %d\n",
+ ldim_dev_config->init_loaded,
+ ldim_dev_config->cmd_size,
+ ldim_dev_config->init_on_cnt,
+ ldim_dev_config->init_off_cnt);
+ if (ldim_dev_config->cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC) {
+ ldim_dev_init_table_dynamic_size_print(ldim_dev_config, 1);
+ ldim_dev_init_table_dynamic_size_print(ldim_dev_config, 0);
+ } else {
+ ldim_dev_init_table_fixed_size_print(ldim_dev_config, 1);
+ ldim_dev_init_table_fixed_size_print(ldim_dev_config, 0);
+ }
+ }
+}
+
+#define LDIM_PINMUX_MAX 4
+static char *ldim_pinmux_str[LDIM_PINMUX_MAX] = {
+ "ldim_pwm_pin", /* 0 */
+ "ldim_pwm_vs_pin", /* 1 */
+ "analog_pwm_pin", /* 2 */
+ "none",
+};
+
+#ifdef CONFIG_OF_LIBFDT
+static int ldim_pinmux_load_from_dts
+ (char *dt_addr,
+ struct ldim_dev_config_s *ldev_conf,
+ const char *str, struct bl_pwm_config_s *bl_pwm)
+{
+ int parent_offset;
+ char *propname, *propdata;
+ int i, temp, len = 0;
+ int ret = 0;
+
+ /* get pinmux */
+ propname = (char *)malloc(30);
+ if (!propname) {
+ LDIMERR("%s: propname malloc failed\n", __func__);
+ return -1;
+ }
+ memset(propname, 0, 30);
+ sprintf(propname, "/pinmux/%s", str);
+ parent_offset = fdt_path_offset(dt_addr, propname);
+ if (parent_offset < 0) {
+ LDIMERR("not find ldim_pwm_pin node\n");
+ bl_pwm->pinmux_set[0][0] = LCD_PINMUX_END;
+ bl_pwm->pinmux_set[0][1] = 0x0;
+ bl_pwm->pinmux_clr[0][0] = LCD_PINMUX_END;
+ bl_pwm->pinmux_clr[0][1] = 0x0;
+ free(propname);
+ return -1;
+ }
+ free(propname);
+
+ propdata = (char *)fdt_getprop(dt_addr, parent_offset,
+ "amlogic,setmask", &len);
+ if (!propdata) {
+ LDIMERR("failed to get amlogic,setmask\n");
+ bl_pwm->pinmux_set[0][0] = LCD_PINMUX_END;
+ bl_pwm->pinmux_set[0][1] = 0x0;
+ } else {
+ temp = len / 8;
+ for (i = 0; i < temp; i++) {
+ bl_pwm->pinmux_set[i][0] =
+ be32_to_cpup((((u32 *)propdata) + 2 * i));
+ bl_pwm->pinmux_set[i][1] =
+ be32_to_cpup((((u32 *)propdata) + 2 * i + 1));
+ }
+ if (temp < (LCD_PINMUX_NUM - 1)) {
+ bl_pwm->pinmux_set[temp][0] = LCD_PINMUX_END;
+ bl_pwm->pinmux_set[temp][1] = 0x0;
+ }
+ }
+
+ propdata = (char *)fdt_getprop(dt_addr, parent_offset,
+ "amlogic,clrmask", &len);
+ if (!propdata) {
+ LDIMERR("failed to get amlogic,clrmask\n");
+ bl_pwm->pinmux_clr[0][0] = LCD_PINMUX_END;
+ bl_pwm->pinmux_clr[0][1] = 0x0;
+ } else {
+ temp = len / 8;
+ for (i = 0; i < temp; i++) {
+ bl_pwm->pinmux_clr[i][0] =
+ be32_to_cpup((((u32 *)propdata) + 2 * i));
+ bl_pwm->pinmux_clr[i][1] =
+ be32_to_cpup((((u32 *)propdata) + 2 * i + 1));
+ }
+ if (temp < (LCD_PINMUX_NUM - 1)) {
+ bl_pwm->pinmux_clr[temp][0] = LCD_PINMUX_END;
+ bl_pwm->pinmux_clr[temp][1] = 0x0;
+ }
+ }
+ if (lcd_debug_print_flag) {
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (bl_pwm->pinmux_set[i][0] == LCD_PINMUX_END)
+ break;
+ LDIMPR("%s set: %d, 0x%08x\n",
+ str,
+ bl_pwm->pinmux_set[i][0],
+ bl_pwm->pinmux_set[i][1]);
+ i++;
+ }
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (bl_pwm->pinmux_clr[i][0] == LCD_PINMUX_END)
+ break;
+ LDIMPR("%s clr: %d, 0x%08x\n",
+ str,
+ bl_pwm->pinmux_clr[i][0],
+ bl_pwm->pinmux_clr[i][1]);
+ i++;
+ }
+ }
+
+ return ret;
+}
+#endif
+
+static int ldim_pinmux_load_from_bsp(struct ldim_dev_config_s *ldev_conf,
+ const char *str,
+ struct bl_pwm_config_s *bl_pwm)
+{
+ unsigned int i, j;
+ int set_cnt = 0, clr_cnt = 0;
+ struct lcd_pinmux_ctrl_s *ldim_pinmux = ldev_conf->ldim_pinmux;
+
+ for (i = 0; i < LDIM_PINMUX_MAX; i++) {
+ if (strncmp(ldim_pinmux->name, "invalid", 7) == 0)
+ break;
+ if (strncmp(ldim_pinmux->name, str, strlen(str)) == 0) {
+ for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
+ if (ldim_pinmux->pinmux_set[j][0] ==
+ LCD_PINMUX_END)
+ break;
+ bl_pwm->pinmux_set[j][0] =
+ ldim_pinmux->pinmux_set[j][0];
+ bl_pwm->pinmux_set[j][1] =
+ ldim_pinmux->pinmux_set[j][1];
+ set_cnt++;
+ }
+ for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
+ if (ldim_pinmux->pinmux_clr[j][0] ==
+ LCD_PINMUX_END)
+ break;
+ bl_pwm->pinmux_clr[j][0] =
+ ldim_pinmux->pinmux_clr[j][0];
+ bl_pwm->pinmux_clr[j][1] =
+ ldim_pinmux->pinmux_clr[j][1];
+ clr_cnt++;
+ }
+ break;
+ }
+ ldim_pinmux++;
+ }
+ if (set_cnt < LCD_PINMUX_NUM) {
+ bl_pwm->pinmux_set[set_cnt][0] = LCD_PINMUX_END;
+ bl_pwm->pinmux_set[set_cnt][1] = 0x0;
+ }
+ if (clr_cnt < LCD_PINMUX_NUM) {
+ bl_pwm->pinmux_clr[clr_cnt][0] = LCD_PINMUX_END;
+ bl_pwm->pinmux_clr[clr_cnt][1] = 0x0;
+ }
+
+ if (lcd_debug_print_flag) {
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (bl_pwm->pinmux_set[i][0] == LCD_PINMUX_END)
+ break;
+ LDIMPR("%s set: %d, 0x%08x\n",
+ str,
+ bl_pwm->pinmux_set[i][0],
+ bl_pwm->pinmux_set[i][1]);
+ i++;
+ }
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (bl_pwm->pinmux_clr[i][0] == LCD_PINMUX_END)
+ break;
+ LDIMPR("%s clr: %d, 0x%08x\n",
+ str,
+ bl_pwm->pinmux_clr[i][0],
+ bl_pwm->pinmux_clr[i][1]);
+ i++;
+ }
+ }
+
+ return 0;
+}
+
+static int ldim_pinmux_load(char *dt_addr, struct aml_ldim_driver_s *ldim_drv)
+{
+ struct bl_pwm_config_s *bl_pwm;
+ char *str;
+ int ret = 0;
+
+ if (ldim_drv->ldev_conf->ldim_pwm_config.pwm_port >= BL_PWM_MAX)
+ return 0;
+
+ /* ldim_pwm */
+ bl_pwm = &ldim_drv->ldev_conf->ldim_pwm_config;
+ if (bl_pwm->pwm_port == BL_PWM_VS)
+ str = ldim_pinmux_str[1];
+ else
+ str = ldim_pinmux_str[0];
+ switch (ldim_drv->ldev_conf->pinctrl_ver) {
+ case 0:
+ ret = ldim_pinmux_load_from_dts(dt_addr, ldim_drv->ldev_conf,
+ str, bl_pwm);
+ break;
+ default:
+ ret = ldim_pinmux_load_from_bsp(ldim_drv->ldev_conf,
+ str, bl_pwm);
+ break;
+ }
+ if (ret)
+ return ret;
+
+ /* analog_pwm */
+ bl_pwm = &ldim_drv->ldev_conf->analog_pwm_config;
+ if (bl_pwm->pwm_port >= BL_PWM_MAX)
+ return 0;
+ str = ldim_pinmux_str[2];
+ switch (ldim_drv->ldev_conf->pinctrl_ver) {
+ case 0:
+ ret = ldim_pinmux_load_from_dts(dt_addr, ldim_drv->ldev_conf,
+ str, bl_pwm);
+ break;
+ default:
+ ret = ldim_pinmux_load_from_bsp(ldim_drv->ldev_conf,
+ str, bl_pwm);
+ break;
+ }
+
+ return ret;
+}
+
+#ifdef CONFIG_OF_LIBFDT
+int aml_ldim_dev_init_table_dynamic_size_load_dts(char *dtaddr, int nodeoffset,
+ struct ldim_dev_config_s
+ *ldconf, int flag)
+{
+ unsigned char cmd_size, type;
+ int i = 0, j, max_len;
+ unsigned char *table;
+ char *propname, *propdata;
+
+ propname = (char *)malloc(30);
+ if (!propname) {
+ LDIMERR("%s: propname malloc failed\n", __func__);
+ return -1;
+ }
+ memset(propname, 0, 30);
+
+ if (flag) {
+ table = ldconf->init_on;
+ max_len = LDIM_INIT_ON_MAX;
+ sprintf(propname, "init_on");
+ } else {
+ table = ldconf->init_off;
+ max_len = LDIM_INIT_OFF_MAX;
+ sprintf(propname, "init_off");
+ }
+ if (table == NULL) {
+ LDIMERR("%s init_table is null\n", propname);
+ goto init_table_dynamic_dts_ok;
+ }
+
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset, propname, NULL);
+ if (propdata == NULL) {
+ LDIMERR("%s: get %s failed\n", ldconf->name, propname);
+ table[0] = LCD_EXT_CMD_TYPE_END;
+ table[1] = 0;
+ goto init_table_dynamic_dts_failed;
+ }
+
+ while ((i + 1) < max_len) {
+ table[i] =
+ (unsigned char)(be32_to_cpup((((u32 *)propdata) + i)));
+ table[i + 1] =
+ (unsigned char)(be32_to_cpup((((u32 *)propdata) + i + 1)));
+ type = table[i];
+ cmd_size = table[i + 1];
+ if (type == LCD_EXT_CMD_TYPE_END)
+ break;
+ if (cmd_size == 0)
+ goto init_table_dynamic_dts_next;
+ if ((i + 2 + cmd_size) > max_len) {
+ LDIMERR("%s: %s cmd_size out of support\n",
+ ldconf->name, propname);
+ table[i] = LCD_EXT_CMD_TYPE_END;
+ table[i + 1] = 0;
+ goto init_table_dynamic_dts_failed;
+ }
+ for (j = 0; j < cmd_size; j++)
+ table[i + 2 + j] =
+ (unsigned char)(be32_to_cpup((((u32 *)propdata) + i + 2 + j)));
+
+init_table_dynamic_dts_next:
+ i += (cmd_size + 2);
+ }
+ if (flag)
+ ldconf->init_on_cnt = i + 2;
+ else
+ ldconf->init_off_cnt = i + 2;
+
+init_table_dynamic_dts_ok:
+ free(propname);
+ return 0;
+
+init_table_dynamic_dts_failed:
+ free(propname);
+ return -1;
+}
+
+int ldim_dev_init_table_fixed_size_load_dts(char *dtaddr, int nodeoffset,
+ struct ldim_dev_config_s *ldconf,
+ int flag)
+{
+ unsigned char cmd_size;
+ int i = 0, j, max_len;
+ unsigned char *table;
+ char *propname, *propdata;
+
+ propname = (char *)malloc(30);
+ if (!propname) {
+ LDIMERR("%s: propname malloc failed\n", __func__);
+ return -1;
+ }
+ memset(propname, 0, 30);
+
+ cmd_size = ldconf->cmd_size;
+ if (flag) {
+ table = ldconf->init_on;
+ max_len = LDIM_INIT_ON_MAX;
+ sprintf(propname, "init_on");
+ } else {
+ table = ldconf->init_off;
+ max_len = LDIM_INIT_OFF_MAX;
+ sprintf(propname, "init_off");
+ }
+ if (table == NULL) {
+ LDIMPR("%s init_table is null\n", propname);
+ goto init_table_fixed_dts_ok;
+ }
+
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset, propname, NULL);
+ if (propdata == NULL) {
+ LDIMERR("%s: get %s failed\n", ldconf->name, propname);
+ table[0] = LCD_EXT_CMD_TYPE_END;
+ table[1] = 0;
+ return -1;
+ }
+
+ while (i < max_len) {
+ if ((i + cmd_size) > max_len) {
+ LDIMERR("%s: %s cmd_size out of support\n", ldconf->name, propname);
+ table[i] = LCD_EXT_CMD_TYPE_END;
+ goto init_table_fixed_dts_failed;
+ }
+ for (j = 0; j < cmd_size; j++)
+ table[i+j] =
+ (unsigned char)(be32_to_cpup((((u32 *)propdata) + i + j)));
+
+ if (table[i] == LCD_EXT_CMD_TYPE_END)
+ break;
+
+ i += cmd_size;
+ }
+ if (flag)
+ ldconf->init_on_cnt = i + cmd_size;
+ else
+ ldconf->init_off_cnt = i + cmd_size;
+
+init_table_fixed_dts_ok:
+ free(propname);
+ return 0;
+
+init_table_fixed_dts_failed:
+ free(propname);
+ return -1;
+}
+
+int ldim_dev_get_config_from_dts(char *dt_addr, int index)
+{
+ int parent_offset, child_offset;
+ char *propname, *propdata;
+ char *p;
+ const char *str;
+ int temp;
+ struct bl_pwm_config_s *bl_pwm;
+ struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
+ int i, j;
+ int ret = 0;
+
+ strcpy(ldim_dev_config->name, "ldim_dev");
+ memset(ldim_dev_config->init_on, 0, LDIM_INIT_ON_MAX);
+ memset(ldim_dev_config->init_off, 0, LDIM_INIT_OFF_MAX);
+ ldim_dev_config->init_on[0] = 0xff;
+ ldim_dev_config->init_off[0] = 0xff;
+
+ if (dt_addr == NULL) {
+ LDIMERR("%s: dt_addr is NULL\n", __func__);
+ return -1;
+ }
+
+ parent_offset = fdt_path_offset(dt_addr, "/local_dimming_device");
+ if (parent_offset < 0) {
+ parent_offset = fdt_path_offset(dt_addr, "/local_diming_device");
+ if (parent_offset < 0) {
+ LDIMERR("not find /local_dimming_device node: %s\n",
+ fdt_strerror(parent_offset));
+ return -1;
+ }
+ }
+ propdata = (char *)fdt_getprop(dt_addr, parent_offset, "status", NULL);
+ if (propdata == NULL) {
+ LDIMERR("not find local_dimming_device status, default to disabled\n");
+ return -1;
+ } else {
+ if (strncmp(propdata, "okay", 2)) {
+ LDIMPR("local_dimming_device status disabled\n");
+ return -1;
+ }
+ }
+
+ /* init gpio */
+ i = 0;
+ propdata = (char *)fdt_getprop(dt_addr, parent_offset,
+ "ldim_dev_gpio_names", NULL);
+ if (propdata == NULL) {
+ LDIMERR("failed to get ldim_dev_gpio_names\n");
+ } else {
+ p = propdata;
+ while (i < BL_GPIO_NUM_MAX) {
+ if (i > 0)
+ p += strlen(p) + 1;
+ str = p;
+ if (strlen(str) == 0)
+ break;
+ strcpy(ldim_dev_config->gpio_name[i], str);
+ if (lcd_debug_print_flag)
+ LDIMPR("i=%d, gpio=%s\n", i,
+ ldim_dev_config->gpio_name[i]);
+ i++;
+ }
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(ldim_dev_config->gpio_name[j], "invalid");
+
+ /* get device config */
+ propname = (char *)malloc(30);
+ if (!propname) {
+ LDIMERR("%s: propname malloc failed\n", __func__);
+ return -1;
+ }
+ memset(propname, 0, 30);
+ sprintf(propname,"/local_dimming_device/ldim_dev_%d", index);
+ child_offset = fdt_path_offset(dt_addr, propname);
+ if (child_offset < 0) {
+ sprintf(propname,"/local_diming_device/ldim_dev_%d", index);
+ child_offset = fdt_path_offset(dt_addr, propname);
+ if (child_offset < 0) {
+ LDIMERR("not find %s node: %s\n",
+ propname, fdt_strerror(child_offset));
+ free(propname);
+ return -1;
+ }
+ }
+ free(propname);
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset, "ldim_dev_name", NULL);
+ if (propdata == NULL)
+ LDIMERR("failed to get ldim_dev_name\n");
+ else
+ strcpy(ldim_dev_config->name, propdata);
+ LDIMPR("get config: %s(%d)\n", ldim_dev_config->name, index);
+
+ /* ldim pwm */
+ bl_pwm = &ldim_dev_config->ldim_pwm_config;
+ propdata = (char *)fdt_getprop(dt_addr, child_offset, "ldim_pwm_port", NULL);
+ if (propdata == NULL) {
+ LDIMERR("failed to get ldim_pwm_port\n");
+ bl_pwm->pwm_port = BL_PWM_MAX;
+ } else {
+ bl_pwm->pwm_port = bl_pwm_str_to_pwm(propdata);
+ LDIMPR("ldim_pwm_port: %s(%u)\n", propdata, bl_pwm->pwm_port);
+ }
+ if (bl_pwm->pwm_port < BL_PWM_MAX) {
+ propdata = (char *)fdt_getprop(dt_addr, child_offset, "ldim_pwm_attr", NULL);
+ if (propdata == NULL) {
+ LDIMERR("failed to get ldim_pwm_attr\n");
+ bl_pwm->pwm_method = BL_PWM_POSITIVE;
+ if (bl_pwm->pwm_port == BL_PWM_VS)
+ bl_pwm->pwm_freq = 1;
+ else
+ bl_pwm->pwm_freq = 60;
+ bl_pwm->pwm_duty = 50;
+ } else {
+ bl_pwm->pwm_method = be32_to_cpup((u32 *)propdata);
+ bl_pwm->pwm_freq =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ bl_pwm->pwm_duty =
+ be32_to_cpup((((u32 *)propdata) + 2));
+ }
+ if (bl_pwm->pwm_port == BL_PWM_VS) {
+ if (bl_pwm->pwm_freq > 4) {
+ LDIMERR("pwm_vs wrong freq %d\n",
+ bl_pwm->pwm_freq);
+ bl_pwm->pwm_freq = BL_FREQ_VS_DEFAULT;
+ }
+ } else {
+ if (bl_pwm->pwm_freq > XTAL_HALF_FREQ_HZ)
+ bl_pwm->pwm_freq = XTAL_HALF_FREQ_HZ;
+ }
+ LDIMPR
+ ("get ldim_pwm pol = %d, freq = %d, default duty = %d%%\n",
+ bl_pwm->pwm_method, bl_pwm->pwm_freq,
+ bl_pwm->pwm_duty);
+ }
+
+ /* analog pwm */
+ bl_pwm = &ldim_dev_config->analog_pwm_config;
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "analog_pwm_port", NULL);
+ if (!propdata)
+ bl_pwm->pwm_port = BL_PWM_MAX;
+ else
+ bl_pwm->pwm_port = bl_pwm_str_to_pwm(propdata);
+ if (bl_pwm->pwm_port < BL_PWM_MAX) {
+ LDIMPR("find analog_pwm_port: %s(%u)\n",
+ propdata, bl_pwm->pwm_port);
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "analog_pwm_attr", NULL);
+ if (!propdata) {
+ LDIMERR("failed to get analog_pwm_attr\n");
+ bl_pwm->pwm_method = BL_PWM_POSITIVE;
+ if (bl_pwm->pwm_port == BL_PWM_VS)
+ bl_pwm->pwm_freq = 1;
+ else
+ bl_pwm->pwm_freq = 60;
+ bl_pwm->pwm_duty_max = 100;
+ bl_pwm->pwm_duty_min = 20;
+ bl_pwm->pwm_duty = 50;
+ } else {
+ bl_pwm->pwm_method = be32_to_cpup((u32 *)propdata);
+ bl_pwm->pwm_freq =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ bl_pwm->pwm_duty_max =
+ be32_to_cpup((((u32 *)propdata) + 2));
+ bl_pwm->pwm_duty_min =
+ be32_to_cpup((((u32 *)propdata) + 3));
+ bl_pwm->pwm_duty =
+ be32_to_cpup((((u32 *)propdata) + 4));
+ }
+ if (bl_pwm->pwm_freq > XTAL_HALF_FREQ_HZ)
+ bl_pwm->pwm_freq = XTAL_HALF_FREQ_HZ;
+ LDIMPR("get analog_pwm pol = %d, freq = %d, duty_max = %d%%, duty_min = %d%%, default duty = %d%%\n",
+ bl_pwm->pwm_method, bl_pwm->pwm_freq,
+ bl_pwm->pwm_duty_max, bl_pwm->pwm_duty_min,
+ bl_pwm->pwm_duty);
+ }
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "en_gpio_on_off", NULL);
+ if (!propdata) {
+ LDIMERR("failed to get en_gpio_on_off\n");
+ } else {
+ ldim_dev_config->en_gpio = be32_to_cpup((u32 *)propdata);
+ ldim_dev_config->en_gpio_on =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ ldim_dev_config->en_gpio_off =
+ be32_to_cpup((((u32 *)propdata) + 2));
+ }
+ if (lcd_debug_print_flag) {
+ LDIMPR("en_gpio=%s(%d), en_gpio_on=%d, en_gpio_off=%d\n",
+ ldim_dev_config->gpio_name[ldim_dev_config->en_gpio],
+ ldim_dev_config->en_gpio, ldim_dev_config->en_gpio_on,
+ ldim_dev_config->en_gpio_off);
+ }
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset, "dim_max_min", NULL);
+ if (!propdata) {
+ LDIMERR("failed to get dim_max_min\n");
+ } else {
+ ldim_dev_config->dim_max = be32_to_cpup((u32 *)propdata);
+ ldim_dev_config->dim_min =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ }
+ if (lcd_debug_print_flag) {
+ LDIMPR("dim_max=0x%03x, dim_min=0x%03x\n",
+ ldim_dev_config->dim_max, ldim_dev_config->dim_min);
+ }
+
+ temp = ldim_drv->ldim_conf->row * ldim_drv->ldim_conf->col;
+ ldim_dev_config->bl_regnum = (unsigned short)temp;
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset, "type", NULL);
+ if (!propdata) {
+ LDIMERR("failed to get type\n");
+ } else {
+ ldim_dev_config->type = be32_to_cpup((u32 *)propdata);
+ LDIMPR("type: %d\n", ldim_dev_config->type);
+ }
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "device_count", NULL);
+ if (!propdata)
+ LDIMERR("failed to get device_count\n");
+ else
+ ldim_dev_config->device_count = be32_to_cpup((u32 *)propdata);
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "ldim_pwm_pinmux_sel", NULL);
+ if (!propdata) {
+ strcpy(ldim_dev_config->pinmux_name, "invalid");
+ } else {
+ LDIMPR("find custome ldim_pwm_pinmux_sel: %s\n", propdata);
+ strcpy(ldim_dev_config->pinmux_name, propdata);
+ }
+
+ if (ldim_dev_config->type >= LDIM_DEV_TYPE_MAX) {
+ LDIMERR("type num is out of support\n");
+ return -1;
+ }
+
+ switch (ldim_dev_config->type) {
+ case LDIM_DEV_TYPE_SPI:
+ ldim_drv->spi_info = &ldim_spi_info;
+ /* get spi config */
+ ldim_spi_info.bus_num = 0; /* fix value */
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "spi_chip_select", NULL);
+ if (!propdata)
+ LDIMERR("failed to get spi_chip_select\n");
+ else
+ ldim_spi_info.chip_select =
+ be32_to_cpup((u32 *)propdata);
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "spi_max_frequency", NULL);
+ if (!propdata)
+ LDIMERR("failed to get spi_max_frequency\n");
+ else
+ ldim_spi_info.max_speed_hz =
+ be32_to_cpup((u32 *)propdata);
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "spi_mode", NULL);
+ if (!propdata)
+ LDIMERR("failed to get spi_mode\n");
+ else
+ ldim_spi_info.mode = be32_to_cpup((u32 *)propdata);
+
+ if (lcd_debug_print_flag) {
+ LDIMPR("spi bus_num=%d, chip_select=%d",
+ ldim_spi_info.bus_num,
+ ldim_spi_info.chip_select);
+ LDIMPR("max_frequency=%d, mode=%d\n",
+ ldim_spi_info.max_speed_hz,
+ ldim_spi_info.mode);
+ }
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "spi_cs_delay", NULL);
+ if (!propdata) {
+ LDIMERR("failed to get spi_cs_delay\n");
+ } else {
+ ldim_dev_config->cs_hold_delay =
+ be32_to_cpup((u32 *)propdata);
+ ldim_dev_config->cs_clk_delay =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ }
+ if (lcd_debug_print_flag) {
+ LDIMPR("cs_hold_delay=%dus, cs_clk_delay=%dus\n",
+ ldim_dev_config->cs_hold_delay,
+ ldim_dev_config->cs_clk_delay);
+ }
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "spi_write_check", NULL);
+ if (!propdata)
+ LDIMERR("failed to get spi_write_check\n");
+ else
+ ldim_dev_config->write_check =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
+ if (lcd_debug_print_flag)
+ LDIMPR("write_check=%d\n", ldim_dev_config->write_check);
+
+ /* get init_cmd */
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "cmd_size", NULL);
+ if (propdata == NULL) {
+ LDIMPR("no cmd_size\n");
+ ldim_dev_config->cmd_size = 0;
+ } else {
+ temp = be32_to_cpup((u32*)propdata);
+ ldim_dev_config->cmd_size = (unsigned char)temp;
+ }
+ if (lcd_debug_print_flag)
+ LDIMPR("cmd_size=%d\n", ldim_dev_config->cmd_size);
+ if (ldim_dev_config->cmd_size == 0)
+ break;
+
+ if (ldim_dev_config->cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC) {
+ ret = ldim_dev_init_table_dynamic_size_load_dts(
+ dt_addr, child_offset, ldim_dev_config, 1);
+ if (ret)
+ break;
+ ret = ldim_dev_init_table_dynamic_size_load_dts(
+ dt_addr, child_offset, ldim_dev_config, 0);
+ } else {
+ ret = ldim_dev_init_table_fixed_size_load_dts(
+ dt_addr, child_offset, ldim_dev_config, 1);
+ if (ret)
+ break;
+ ret = ldim_dev_init_table_fixed_size_load_dts(
+ dt_addr, child_offset, ldim_dev_config, 0);
+ }
+ if (ret == 0)
+ ldim_dev_config->init_loaded = 1;
+ break;
+ case LDIM_DEV_TYPE_I2C:
+ break;
+ case LDIM_DEV_TYPE_NORMAL:
+ default:
+ break;
+ }
+
+ /* pinmux */
+ /* new kernel dts pinctrl detect */
+ propdata = (char *)fdt_getprop(dt_addr, parent_offset,
+ "pinctrl_version", NULL);
+ if (propdata)
+ ldim_dev_config->pinctrl_ver =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
+ LDIMPR("pinctrl_version: %d\n", ldim_dev_config->pinctrl_ver);
+
+ ret = aml_ldim_pinmux_load(dt_addr, ldim_drv);
+
+ return ret;
+}
+#endif
+
+static int ldim_dev_add_driver(struct aml_ldim_driver_s *ldim_drv)
+{
+ struct ldim_dev_config_s *ldev_conf = ldim_drv->ldev_conf;
+ int index = ldim_drv->dev_index;
+ int ret = 0;
+
+ switch (ldev_conf->type) {
+ case LDIM_DEV_TYPE_SPI:
+ ret = ldim_spi_driver_add(ldim_drv);
+ break;
+ case LDIM_DEV_TYPE_I2C:
+ break;
+ case LDIM_DEV_TYPE_NORMAL:
+ default:
+ break;
+ }
+ if (ret)
+ return -1;
+
+ ret = -1;
+ if (strcmp(ldev_conf->name, "iw7019") == 0) {
+#ifdef CONFIG_AML_LOCAL_DIMMING_IW7019
+ ret = ldim_dev_iw7019_probe(ldim_drv);
+#endif
+ } else if (strcmp(ldev_conf->name, "iw7027") == 0) {
+#ifdef CONFIG_AML_LOCAL_DIMMING_IW7027
+ ret = ldim_dev_iw7027_probe(ldim_drv);
+#endif
+ } else if (strcmp(ldev_conf->name, "iw7027_he") == 0) {
+#ifdef CONFIG_AML_LOCAL_DIMMING_IW7027_HE
+ ret = ldim_dev_iw7027_he_probe(ldim_drv);
+#endif
+ } else if (strcmp(ldev_conf->name, "iw7038") == 0) {
+#ifdef CONFIG_AML_LOCAL_DIMMING_IW7038
+ ret = ldim_dev_iw7038_probe(ldim_drv);
+#endif
+ } else if (strcmp(ldev_conf->name, "ob3350") == 0) {
+#ifdef CONFIG_AML_LOCAL_DIMMING_OB3350
+ ret = ldim_dev_ob3350_probe(ldim_drv);
+#endif
+ } else if (strcmp(ldev_conf->name, "global") == 0) {
+#ifdef CONFIG_AML_LOCAL_DIMMING_GLOBAL
+ ret = ldim_dev_global_probe(ldim_drv);
+#endif
+ } else {
+ LDIMERR("invalid device name: %s\n", ldev_conf->name);
+ ret = -1;
+ }
+
+ if (ret) {
+ LDIMERR("add device driver failed: %s(%d)\n",
+ ldev_conf->name, index);
+ } else {
+ ldim_dev_probe_flag = 1;
+ LDIMPR("add device driver: %s(%d)\n", ldev_conf->name, index);
+ }
+
+ return ret;
+}
+
+static int ldim_dev_remove_driver(struct aml_ldim_driver_s *ldim_drv)
+{
+ struct ldim_dev_config_s *ldev_conf = ldim_drv->ldev_conf;
+ int index = ldim_drv->dev_index;
+ int ret = -1;
+
+ if (ldim_dev_probe_flag == 0)
+ return 0;
+
+ if (strcmp(ldev_conf->name, "iw7019") == 0) {
+#ifdef CONFIG_AML_LOCAL_DIMMING_IW7019
+ ret = ldim_dev_iw7019_remove(ldim_drv);
+#endif
+ } else if (strcmp(ldev_conf->name, "iw7027") == 0) {
+#ifdef CONFIG_AML_LOCAL_DIMMING_IW7027
+ ret = ldim_dev_iw7027_remove(ldim_drv);
+#endif
+ } else if (strcmp(ldev_conf->name, "iw7027_he") == 0) {
+#ifdef CONFIG_AML_LOCAL_DIMMING_IW7027_HE
+ ret = ldim_dev_iw7027_he_remove(ldim_drv);
+#endif
+ } else if (strcmp(ldev_conf->name, "iw7038") == 0) {
+#ifdef CONFIG_AML_LOCAL_DIMMING_IW7038
+ ret = ldim_dev_iw7038_probe(ldim_drv);
+#endif
+ } else if (strcmp(ldev_conf->name, "ob3350") == 0) {
+#ifdef CONFIG_AML_LOCAL_DIMMING_OB3350
+ ret = ldim_dev_ob3350_remove(ldim_drv);
+#endif
+ } else if (strcmp(ldev_conf->name, "global") == 0) {
+#ifdef CONFIG_AML_LOCAL_DIMMING_GLOBAL
+ ret = ldim_dev_global_remove(ldim_drv);
+#endif
+ } else {
+ LDIMERR("invalid device name: %s\n", ldev_conf->name);
+ ret = -1;
+ }
+
+ if (ret) {
+ LDIMERR("remove device driver failed: %s(%d)\n",
+ ldev_conf->name, index);
+ } else {
+ LDIMPR("remove device driver: %s(%d)\n", ldev_conf->name, index);
+ }
+
+ return ret;
+}
+
+int aml_ldim_device_probe(char *dt_addr)
+{
+ struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
+ int ret = 0;
+
+ if (lcd_debug_print_flag)
+ LDIMPR("%s\n", __func__);
+
+ ldim_dev_probe_flag = 0;
+
+ /* get configs */
+ ldim_dev_config = &ldim_config_dft;
+ ldim_drv->ldev_conf = ldim_dev_config;
+ ldim_drv->pinmux_ctrl = ldim_pwm_pinmux_ctrl;
+ ldim_drv->device_config_print = ldim_device_config_print;
+
+#ifdef CONFIG_OF_LIBFDT
+ ret = ldim_dev_get_config_from_dts(dt_addr, ldim_drv->dev_index);
+ if (ret)
+ return -1;
+#endif
+
+ /* add device driver */
+ ret = ldim_dev_add_driver(ldim_drv);
+
+ return ret;
+}
+
+int aml_ldim_device_remove(void)
+{
+ struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
+ int ret = 0;
+
+ ldim_dev_remove_driver(ldim_drv);
+
+ return ret;
+}
+
diff --git a/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ldim_dev_drv.h b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ldim_dev_drv.h
new file mode 100644
index 0000000..bb1be7d
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ldim_dev_drv.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __LDIM_DEV_DRV_H
+#define __LDIM_DEV_DRV_H
+#include <spi.h>
+#include <amlogic/media/vout/lcd/bl_ldim.h>
+
+void ldim_set_gpio(int index, int value);
+unsigned int ldim_get_gpio(int index);
+void ldim_set_duty_pwm(struct bl_pwm_config_s *bl);
+
+extern int ldim_spi_write(struct spi_slave *spi, unsigned char *tbuf, int tlen);
+extern int ldim_spi_read(struct spi_slave *spi, unsigned char *tbuf, int tlen,
+ unsigned char *rbuf, int rlen);
+extern int ldim_spi_driver_add(struct aml_ldim_driver_s *ldim_drv);
+extern int ldim_spi_driver_remove(struct aml_ldim_driver_s *ldim_drv);
+
+/* ldim device probe function */
+#ifdef CONFIG_AML_LOCAL_DIMMING_IW7019
+int ldim_dev_iw7019_probe(struct aml_ldim_driver_s *ldim_drv);
+int ldim_dev_iw7019_remove(struct aml_ldim_driver_s *ldim_drv);
+#endif
+
+#ifdef CONFIG_AML_LOCAL_DIMMING_IW7027
+extern int ldim_dev_iw7027_probe(struct aml_ldim_driver_s *ldim_drv);
+extern int ldim_dev_iw7027_remove(struct aml_ldim_driver_s *ldim_drv);
+#endif
+
+#ifdef CONFIG_AML_LOCAL_DIMMING_IW7027_HE
+int ldim_dev_iw7027_he_probe(struct aml_ldim_driver_s *ldim_drv);
+int ldim_dev_iw7027_he_remove(struct aml_ldim_driver_s *ldim_drv);
+#endif
+
+#ifdef CONFIG_AML_LOCAL_DIMMING_IW7038
+int ldim_dev_iw7038_probe(struct aml_ldim_driver_s *ldim_drv);
+int ldim_dev_iw7038_remove(struct aml_ldim_driver_s *ldim_drv);
+#endif
+
+#ifdef CONFIG_AML_LOCAL_DIMMING_OB3350
+extern int ldim_dev_ob3350_probe(struct aml_ldim_driver_s *ldim_drv);
+extern int ldim_dev_ob3350_remove(struct aml_ldim_driver_s *ldim_drv);
+#endif
+
+#ifdef CONFIG_AML_LOCAL_DIMMING_GLOBAL
+int ldim_dev_global_probe(struct aml_ldim_driver_s *ldim_drv);
+int ldim_dev_global_remove(struct aml_ldim_driver_s *ldim_drv);
+#endif
+
+#endif
diff --git a/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ldim_drv.c b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ldim_drv.c
new file mode 100644
index 0000000..f3a7f95
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ldim_drv.c
@@ -0,0 +1,238 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/gpio.h>
+#include <fdtdec.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+#include <amlogic/media/vout/lcd/bl_ldim.h>
+#include "../lcd_reg.h"
+#include "../lcd_common.h"
+#include "ldim_drv.h"
+
+#define LD_DATA_MIN 10
+#define LDIM_BRI_LEVEL_MAX 0xfff
+#define LDIM_BRI_LEVEL_MIN 0x7f
+static unsigned int ldim_blk_row = 1;
+static unsigned int ldim_blk_col = 8;
+static struct aml_ldim_driver_s ldim_driver;
+
+static int ldim_on_flag;
+static int ldim_level;
+static int ldim_set_level(unsigned int level);
+
+static struct ldim_config_s ldim_config = {
+ .row = 1,
+ .col = 1,
+};
+
+static int ldim_power_on(void)
+{
+ if (ldim_driver.device_power_on)
+ ldim_driver.device_power_on();
+ else
+ LDIMERR("%s: device_power_on is null\n", __func__);
+ ldim_on_flag = 1;
+
+ if (ldim_level > 0)
+ ldim_set_level(ldim_level);
+
+ return 0;
+}
+static int ldim_power_off(void)
+{
+ ldim_on_flag = 0;
+ if (ldim_driver.device_power_off)
+ ldim_driver.device_power_off();
+ else
+ LDIMERR("%s: device_power_off is null\n", __func__);
+
+ return 0;
+}
+
+static void ldim_brightness_update(unsigned int level)
+{
+ unsigned int size;
+ unsigned int i;
+
+ size = ldim_blk_row * ldim_blk_col;
+ for (i = 0; i < size; i++)
+ ldim_driver.ldim_matrix_buf[i] = (unsigned short)level;
+
+ if (ldim_driver.device_bri_update)
+ ldim_driver.device_bri_update(ldim_driver.ldim_matrix_buf, size);
+ else
+ LDIMPR("%s: device_bri_update is null\n", __func__);
+}
+
+static int ldim_set_level(unsigned int level)
+{
+ int ret = 0;
+ struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
+ unsigned int level_max, level_min;
+
+ ldim_level = level;
+ if (ldim_on_flag == 0)
+ return 0;
+
+ level_max = lcd_drv->bl_config->level_max;
+ level_min = lcd_drv->bl_config->level_min;
+
+ level = ((level - level_min) * (LD_DATA_MAX - LD_DATA_MIN)) /
+ (level_max - level_min) + LD_DATA_MIN;
+ level &= 0xfff;
+
+ ldim_brightness_update(level);
+ return ret;
+}
+
+static void ldim_config_print(void)
+{
+ LDIMPR("%s:\n", __func__);
+ printf("valid_flag = %d\n"
+ "dev_index = %d\n"
+ "ldim_blk_row = %d\n"
+ "ldim_blk_col = %d\n"
+ "ldim_on_flag = %d\n",
+ ldim_driver.valid_flag,
+ ldim_driver.dev_index,
+ ldim_blk_row,
+ ldim_blk_col,
+ ldim_on_flag);
+ if (ldim_driver.device_config_print)
+ ldim_driver.device_config_print();
+}
+
+static struct aml_ldim_driver_s ldim_driver = {
+ .valid_flag = 0, /* default invalid, active when bl_ctrl_method=ldim */
+ .dev_index = 0,
+ .ldim_conf = &ldim_config,
+ .ldev_conf = NULL,
+ .ldim_matrix_buf = NULL,
+ .power_on = ldim_power_on,
+ .power_off = ldim_power_off,
+ .set_level = ldim_set_level,
+ .config_print = ldim_config_print,
+ .pinmux_ctrl = NULL,
+ .device_config_print = NULL,
+ .device_power_on = NULL,
+ .device_power_off = NULL,
+ .device_bri_update = NULL,
+};
+
+struct aml_ldim_driver_s *aml_ldim_get_driver(void)
+{
+ return &ldim_driver;
+}
+
+#ifdef CONFIG_OF_LIBFDT
+int ldim_config_load_from_dts(char *dt_addr, int child_offset)
+{
+ char *propdata;
+
+ if (child_offset < 0) {
+ LDIMERR("not find backlight node %s\n", fdt_strerror(child_offset));
+ return -1;
+ }
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset, "bl_ldim_region_row_col", NULL);
+ if (propdata == NULL) {
+ LDIMERR("failed to get bl_ldim_region_row_col\n");
+ ldim_blk_row = 1;
+ ldim_blk_col = 1;
+ } else {
+ ldim_blk_row = be32_to_cpup((u32*)propdata);
+ ldim_blk_col = be32_to_cpup((((u32*)propdata)+1));
+ ldim_config.row = ldim_blk_row;
+ ldim_config.col = ldim_blk_col;
+ }
+ LDIMPR("get region row = %d, col = %d\n", ldim_blk_row, ldim_blk_col);
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset, "ldim_dev_index", NULL);
+ if (propdata == NULL) {
+ LDIMERR("failed to get ldim_dev_index\n");
+ ldim_driver.dev_index = 0xff;
+ } else {
+ ldim_driver.dev_index = be32_to_cpup((u32*)propdata);
+ }
+ LDIMPR("get dev_index = %d\n", ldim_driver.dev_index);
+
+ return 0;
+}
+#endif
+
+int ldim_config_load_from_unifykey(unsigned char *para)
+{
+ unsigned char *p;
+
+ if (para == NULL) {
+ LDIMERR("backlight unifykey buf is NULL\n");
+ return -1;
+ }
+
+ p = para;
+
+ /* ldim: 24byte */
+ /* get bl_ldim_region_row_col 4byte*/
+ ldim_blk_row = *(p + LCD_UKEY_BL_LDIM_ROW);
+ ldim_blk_col = *(p + LCD_UKEY_BL_LDIM_COL);
+ ldim_config.row = ldim_blk_row;
+ ldim_config.col = ldim_blk_col;
+ LDIMPR("get region row = %d, col = %d\n",
+ ldim_blk_row, ldim_blk_col);
+
+ /* get ldim_dev_index 1byte*/
+ ldim_driver.dev_index = *(p + LCD_UKEY_BL_LDIM_DEV_INDEX);
+ LDIMPR("get dev_index = %d\n", ldim_driver.dev_index);
+
+ return 0;
+}
+
+int aml_ldim_probe(char *dt_addr, int flag)
+{
+ unsigned int size;
+ int ret = -1;
+
+ ldim_on_flag = 0;
+ ldim_level = 0;
+
+ switch (flag) {
+ case 0: /* dts */
+ case 2: /* unifykey */
+#ifdef CONFIG_OF_LIBFDT
+ if (dt_addr) {
+ if (lcd_debug_print_flag)
+ LDIMPR("load ldim_dev_config from dts\n");
+ ret = aml_ldim_device_probe(dt_addr);
+ }
+#endif
+ break;
+ case 1: /* bsp */
+ LDIMPR("%s: not support bsp config\n", __func__);
+ break;
+ default:
+ break;
+ }
+
+ if (ret) {
+ LDIMERR("%s failed\n", __func__);
+ return ret;
+ }
+
+ size = ldim_blk_row * ldim_blk_col;
+ ldim_driver.ldim_matrix_buf = (unsigned short *)malloc(sizeof(unsigned short) * size);
+ if (ldim_driver.ldim_matrix_buf == NULL) {
+ LDIMERR("ldim_matrix_buf malloc error\n");
+ return -1;
+ }
+
+ ldim_driver.valid_flag = 1;
+
+ LDIMPR("%s is ok\n", __func__);
+
+ return ret;
+}
+
diff --git a/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ldim_drv.h b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ldim_drv.h
new file mode 100644
index 0000000..7de2b4e
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ldim_drv.h
@@ -0,0 +1,25 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AML_LDIM_DRV_H__
+#define __AML_LDIM_DRV_H__
+#include <asm/arch/io.h>
+#include <amlogic/media/vout/lcd/lcd_vout.h>
+
+#define LDIMPR(fmt, args...) printf("ldim: "fmt"", ## args)
+#define LDIMERR(fmt, args...) printf("ldim: error: "fmt"", ## args)
+
+#define LD_DATA_DEPTH 12
+#define LD_DATA_MAX 0xfff
+
+void bl_pwm_ctrl(struct bl_pwm_config_s *bl_pwm, int status);
+#ifdef CONFIG_OF_LIBFDT
+enum bl_pwm_port_e bl_pwm_str_to_pwm(const char *str);
+#endif
+
+/* ldim device probe function */
+int aml_ldim_device_probe(char *dt_addr);
+
+#endif
diff --git a/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ldim_spi.c b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ldim_spi.c
new file mode 100644
index 0000000..5cdf9c6
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ldim_spi.c
@@ -0,0 +1,147 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <spi.h>
+#include <asm/arch/gpio.h>
+#include <fdtdec.h>
+#include <amlogic/media/vout/lcd/bl_ldim.h>
+#include "../lcd_common.h"
+#include "ldim_drv.h"
+#include "ldim_dev_drv.h"
+
+#ifdef CONFIG_DM_SPI
+
+static unsigned int cs_hold_delay;
+static unsigned int cs_clk_delay;
+
+int ldim_spi_write(struct spi_slave *spi, unsigned char *tbuf, int tlen)
+{
+ int ret, size;
+
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ LDIMERR("%s: request spi bus failed\n", __func__);
+ goto wreg_end;
+ }
+
+ if (cs_hold_delay)
+ udelay(cs_hold_delay);
+ spi_cs_activate(spi);
+ if (cs_clk_delay)
+ udelay(cs_clk_delay);
+ size = tlen * 8;
+ ret = spi_xfer(spi, size, tbuf, NULL, 0);
+ if (cs_clk_delay)
+ udelay(cs_clk_delay);
+ spi_cs_deactivate(spi);
+
+wreg_end:
+ spi_release_bus(spi);
+ return ret;
+}
+
+int ldim_spi_read(struct spi_slave *spi, unsigned char *tbuf, int tlen,
+ unsigned char *rbuf, int rlen)
+{
+ int ret, size;
+
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ LDIMERR("%s: request spi bus failed\n", __func__);
+ goto rreg_end;
+ }
+
+ if (cs_hold_delay)
+ udelay(cs_hold_delay);
+ spi_cs_activate(spi);
+ if (cs_clk_delay)
+ udelay(cs_clk_delay);
+ size = (tlen + rlen) * 8;
+ ret = spi_xfer(spi, size, tbuf, rbuf, 0);
+ if (ret)
+ goto rreg_end;
+ if (cs_clk_delay)
+ udelay(cs_clk_delay);
+ spi_cs_deactivate(spi);
+
+rreg_end:
+ spi_release_bus(spi);
+ return ret;
+}
+
+int ldim_spi_driver_add(struct aml_ldim_driver_s *ldim_drv)
+{
+ struct udevice *dev;
+ int ret;
+
+ if (ldim_drv->spi_info == NULL) {
+ LDIMERR("%s: spi_info is null\n", __func__);
+ return -1;
+ }
+
+ /* register spi */
+ snprintf(ldim_drv->spi_info->spi_name, LDIM_SPI_NAME_MAX,
+ "generic_%d:%d",
+ ldim_drv->spi_info->bus_num,
+ ldim_drv->spi_info->chip_select);
+ ret = spi_get_bus_and_cs(ldim_drv->spi_info->bus_num,
+ ldim_drv->spi_info->chip_select,
+ ldim_drv->spi_info->max_speed_hz,
+ ldim_drv->spi_info->mode,
+ "spi_generic_drv",
+ ldim_drv->spi_info->spi_name,
+ &dev, &ldim_drv->spi_info->spi);
+ if (ret) {
+ LDIMERR("%s: register spi driver failed\n", __func__);
+ return -1;
+ }
+ ldim_drv->spi_info->spi->wordlen = ldim_drv->spi_info->wordlen;
+ cs_hold_delay = ldim_drv->ldev_conf->cs_hold_delay;
+ cs_clk_delay = ldim_drv->ldev_conf->cs_clk_delay;
+
+ spi_cs_deactivate(ldim_drv->spi_info->spi);
+
+ return 0;
+}
+
+int ldim_spi_driver_remove(struct aml_ldim_driver_s *ldim_drv)
+{
+ if (ldim_drv->spi_info)
+ ldim_drv->spi_info->spi = NULL;
+
+ return 0;
+}
+
+#else
+int ldim_spi_write(struct spi_slave *spi, unsigned char *tbuf, int tlen)
+{
+ LDIMERR("%s: no AML_SPICC support\n", __func__);
+
+ return -1;
+}
+
+int ldim_spi_read(struct spi_slave *spi, unsigned char *tbuf, int tlen,
+ unsigned char *rbuf, int rlen)
+{
+ LDIMERR("%s: no AML_SPICC support\n", __func__);
+
+ return -1;
+}
+
+int ldim_spi_driver_add(struct aml_ldim_driver_s *ldim_drv)
+{
+ LDIMERR("%s: no AML_SPICC support\n", __func__);
+
+ return -1;
+}
+
+int ldim_spi_driver_remove(struct aml_ldim_driver_s *ldim_drv)
+{
+ return 0;
+}
+#endif
+
diff --git a/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ob3350.c b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ob3350.c
new file mode 100644
index 0000000..3e7012f
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/bl_ldim/ob3350.c
@@ -0,0 +1,140 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/gpio.h>
+#include <fdtdec.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+#include <amlogic/media/vout/lcd/bl_ldim.h>
+#include "../lcd_reg.h"
+#include "../lcd_common.h"
+#include "ldim_drv.h"
+#include "ldim_dev_drv.h"
+
+static int ob3350_on_flag;
+
+static int ob3350_hw_init_on(void)
+{
+ struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
+
+ ldim_set_duty_pwm(&ldim_drv->ldev_conf->ldim_pwm_config);
+ ldim_set_duty_pwm(&ldim_drv->ldev_conf->analog_pwm_config);
+
+ ldim_set_gpio(ldim_drv->ldev_conf->en_gpio,
+ ldim_drv->ldev_conf->en_gpio_on);
+ mdelay(2);
+ ldim_drv->pinmux_ctrl(1);
+ mdelay(20);
+
+ return 0;
+}
+
+static int ob3350_hw_init_off(void)
+{
+ struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
+
+ ldim_drv->pinmux_ctrl(0);
+ ldim_set_gpio(ldim_drv->ldev_conf->en_gpio,
+ ldim_drv->ldev_conf->en_gpio_off);
+
+ return 0;
+}
+
+static unsigned int ob3350_get_value(unsigned int level)
+{
+ struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
+
+ unsigned int val;
+ unsigned int dim_max, dim_min;
+
+ dim_max = ldim_drv->ldev_conf->dim_max;
+ dim_min = ldim_drv->ldev_conf->dim_min;
+
+ val = dim_min + ((level * (dim_max - dim_min)) / LD_DATA_MAX);
+
+ return val;
+}
+
+static int ob3350_smr(unsigned short *buf, unsigned char len)
+{
+ struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
+ unsigned short val;
+
+ val = ob3350_get_value(buf[0]);
+ ldim_drv->ldev_conf->ldim_pwm_config.pwm_duty = val;
+
+ if (ob3350_on_flag == 0) {
+ if (lcd_debug_print_flag)
+ LDIMPR("%s: on_flag=%d\n", __func__, ob3350_on_flag);
+ return 0;
+ }
+
+ if (len != 1) {
+ LDIMERR("%s: data len %d invalid\n", __func__, len);
+ return -1;
+ }
+
+ ldim_set_duty_pwm(&ldim_drv->ldev_conf->ldim_pwm_config);
+
+ return 0;
+}
+
+static void ob3350_dim_range_update(void)
+{
+ struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
+ struct ldim_dev_config_s *ldim_dev;
+
+ ldim_dev = ldim_drv->ldev_conf;
+ ldim_dev->dim_max = ldim_dev->ldim_pwm_config.pwm_duty_max;
+ ldim_dev->dim_min = ldim_dev->ldim_pwm_config.pwm_duty_min;
+}
+
+static int ob3350_power_on(void)
+{
+ ob3350_hw_init_on();
+ ob3350_on_flag = 1;
+
+ LDIMPR("%s: ok\n", __func__);
+ return 0;
+}
+
+static int ob3350_power_off(void)
+{
+ ob3350_on_flag = 0;
+ ob3350_hw_init_off();
+
+ LDIMPR("%s: ok\n", __func__);
+ return 0;
+}
+
+static int ob3350_ldim_driver_update(struct aml_ldim_driver_s *ldim_drv)
+{
+ struct ldim_dev_config_s *ldim_dev = ldim_drv->ldev_conf;
+
+ ldim_dev->ldim_pwm_config.pwm_duty_max = ldim_dev->dim_max;
+ ldim_dev->ldim_pwm_config.pwm_duty_min = ldim_dev->dim_min;
+ ldim_dev->dim_range_update = ob3350_dim_range_update;
+
+ ldim_drv->device_power_on = ob3350_power_on;
+ ldim_drv->device_power_off = ob3350_power_off;
+ ldim_drv->device_bri_update = ob3350_smr;
+
+ return 0;
+}
+
+int ldim_dev_ob3350_probe(struct aml_ldim_driver_s *ldim_drv)
+{
+ ob3350_on_flag = 0;
+ ob3350_ldim_driver_update(ldim_drv);
+
+ return 0;
+}
+
+int ldim_dev_ob3350_remove(struct aml_ldim_driver_s *ldim_drv)
+{
+ return 0;
+}
+
diff --git a/drivers/amlogic/media/vout/lcd/backlight/bl_pwm.c b/drivers/amlogic/media/vout/lcd/backlight/bl_pwm.c
new file mode 100644
index 0000000..3476805
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/bl_pwm.c
@@ -0,0 +1,589 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+#include "lcd_bl.h"
+#include "../lcd_reg.h"
+#include "../lcd_common.h"
+
+#define PWM_REG_MAX 0xffffffff
+
+struct bl_pwm_clkctrl_s {
+ unsigned int reg;
+ unsigned int bit_div;
+ unsigned int bit_sel;
+ unsigned int bit_en;
+};
+
+struct bl_pwm_misc_s {
+ unsigned int reg;
+ unsigned int bit_pre_div;
+ unsigned int bit_clk_sel;
+ unsigned int bit_clk_en;
+ unsigned int bit_pwm_en;
+ unsigned int val_pwm_en;
+};
+
+struct bl_pwm_ctrl_config_s {
+ struct bl_pwm_clkctrl_s *pwm_clk;
+ struct bl_pwm_misc_s *pwm_misc;
+ unsigned int *pwm_reg;
+ unsigned int pwm_cnt;
+ struct bl_pwm_clkctrl_s *pwm_ao_clk;
+ struct bl_pwm_misc_s *pwm_ao_misc;
+ unsigned int *pwm_ao_reg;
+ unsigned int pwm_ao_cnt;
+};
+
+static struct bl_pwm_ctrl_config_s *bl_pwm_ctrl_conf;
+
+static struct bl_pwm_misc_s pwm_misc_dft[] = {
+ /* pwm_reg, pre_div, clk_sel, clk_en, pwm_en, val_en*/
+ {PWM_MISC_REG_AB, 8, 4, 15, 0, 3,},
+ {PWM_MISC_REG_AB, 16, 6, 23, 0, 3,},
+ {PWM_MISC_REG_CD, 8, 4, 15, 0, 3,},
+ {PWM_MISC_REG_CD, 16, 6, 23, 0, 3,},
+ {PWM_MISC_REG_EF, 8, 4, 15, 0, 3,},
+ {PWM_MISC_REG_EF, 16, 6, 23, 0, 3,},
+ {PWM_REG_MAX, 0, 0, 0, 0, 0,}
+};
+
+static unsigned int pwm_reg_dft[] = {
+ PWM_PWM_A,
+ PWM_PWM_B,
+ PWM_PWM_C,
+ PWM_PWM_D,
+ PWM_PWM_E,
+ PWM_PWM_F,
+ PWM_REG_MAX
+};
+
+static struct bl_pwm_misc_s pwm_ao_misc_dft[] = {
+ /* pwm_reg, pre_div, clk_sel, clk_en, pwm_en, val_en*/
+ {AO_PWM_MISC_REG_AB, 8, 4, 15, 0, 3,},
+ {AO_PWM_MISC_REG_AB, 16, 6, 23, 0, 3,},
+ {PWM_REG_MAX, 0, 0, 0, 0, 0,}
+};
+
+static unsigned int pwm_ao_reg_dft[] = {
+ AO_PWM_PWM_A,
+ AO_PWM_PWM_B,
+ PWM_REG_MAX
+};
+
+static struct bl_pwm_clkctrl_s pwm_clk_ctrl_t7[] = {
+ /* pwm_reg, bit_div, bit_sel, bit_en*/
+ {CLKCTRL_PWM_CLK_AB_CTRL, 0, 9, 8},
+ {CLKCTRL_PWM_CLK_AB_CTRL, 16, 25, 24},
+ {CLKCTRL_PWM_CLK_CD_CTRL, 0, 9, 8},
+ {CLKCTRL_PWM_CLK_CD_CTRL, 16, 25, 24},
+ {CLKCTRL_PWM_CLK_EF_CTRL, 0, 9, 8},
+ {CLKCTRL_PWM_CLK_EF_CTRL, 16, 25, 24},
+ {PWM_REG_MAX, 0, 0, 0}
+};
+
+static struct bl_pwm_misc_s pwm_misc_t7[] = {
+ /* pwm_reg, pre_div, clk_sel, clk_en, pwm_en, val_en*/
+ {PWMAB_MISC_REG_AB, 8, 4, 15, 0, 1,},
+ {PWMAB_MISC_REG_AB, 16, 6, 23, 1, 1,},
+ {PWMCD_MISC_REG_AB, 8, 4, 15, 0, 1,},
+ {PWMCD_MISC_REG_AB, 16, 6, 23, 1, 1,},
+ {PWMEF_MISC_REG_AB, 8, 4, 15, 0, 1,},
+ {PWMEF_MISC_REG_AB, 16, 6, 23, 1, 1,},
+ {PWM_REG_MAX, 0, 0, 0, 0, 0,}
+};
+
+static unsigned int pwm_reg_t7[] = {
+ PWMAB_PWM_A,
+ PWMAB_PWM_B,
+ PWMCD_PWM_A,
+ PWMCD_PWM_B,
+ PWMEF_PWM_A,
+ PWMEF_PWM_B,
+ PWM_REG_MAX
+};
+
+static struct bl_pwm_clkctrl_s pwm_ao_clk_ctrl_t7[] = {
+ /* pwm_reg, bit_div, bit_sel, bit_en*/
+ {CLKCTRL_PWM_CLK_AO_AB_CTRL, 0, 9, 8},
+ {CLKCTRL_PWM_CLK_AO_AB_CTRL, 16, 25, 24},
+ {CLKCTRL_PWM_CLK_AO_CD_CTRL, 0, 9, 8},
+ {CLKCTRL_PWM_CLK_AO_CD_CTRL, 16, 25, 24},
+ {CLKCTRL_PWM_CLK_AO_EF_CTRL, 0, 9, 8},
+ {CLKCTRL_PWM_CLK_AO_EF_CTRL, 16, 25, 24},
+ {CLKCTRL_PWM_CLK_AO_GH_CTRL, 0, 9, 8},
+ {CLKCTRL_PWM_CLK_AO_GH_CTRL, 16, 25, 24},
+ {PWM_REG_MAX, 0, 0, 0}
+};
+
+static struct bl_pwm_misc_s pwm_ao_misc_t7[] = {
+ /* pwm_reg, pre_div, clk_sel, clk_en, pwm_en, val_en*/
+ {PWM_AO_AB_MISC_REG_AB, 8, 4, 15, 0, 1,},
+ {PWM_AO_AB_MISC_REG_AB, 16, 6, 23, 1, 1,},
+ {PWM_AO_CD_MISC_REG_AB, 8, 4, 15, 0, 1,},
+ {PWM_AO_CD_MISC_REG_AB, 16, 6, 23, 1, 1,},
+ {PWM_AO_EF_MISC_REG_AB, 8, 4, 15, 0, 1,},
+ {PWM_AO_EF_MISC_REG_AB, 16, 6, 23, 1, 1,},
+ {PWM_AO_GH_MISC_REG_AB, 8, 4, 15, 0, 1,},
+ {PWM_AO_GH_MISC_REG_AB, 16, 6, 23, 1, 1,},
+ {PWM_REG_MAX, 0, 0, 0, 0, 0,}
+};
+
+static unsigned int pwm_ao_reg_t7[] = {
+ PWM_AO_AB_PWM_A,
+ PWM_AO_AB_PWM_B,
+ PWM_AO_CD_PWM_A,
+ PWM_AO_CD_PWM_B,
+ PWM_AO_EF_PWM_A,
+ PWM_AO_EF_PWM_B,
+ PWM_AO_GH_PWM_A,
+ PWM_AO_GH_PWM_B,
+ PWM_REG_MAX
+};
+
+static struct bl_pwm_ctrl_config_s bl_pwm_ctrl_conf_dft = {
+ .pwm_clk = NULL,
+ .pwm_misc = pwm_misc_dft,
+ .pwm_reg = pwm_reg_dft,
+ .pwm_cnt = 6,
+ .pwm_ao_clk = NULL,
+ .pwm_ao_misc = pwm_ao_misc_dft,
+ .pwm_ao_reg = pwm_ao_reg_dft,
+ .pwm_ao_cnt = 2,
+};
+
+static struct bl_pwm_ctrl_config_s bl_pwm_ctrl_conf_t7 = {
+ .pwm_clk = pwm_clk_ctrl_t7,
+ .pwm_misc = pwm_misc_t7,
+ .pwm_reg = pwm_reg_t7,
+ .pwm_cnt = 6,
+ .pwm_ao_clk = pwm_ao_clk_ctrl_t7,
+ .pwm_ao_misc = pwm_ao_misc_t7,
+ .pwm_ao_reg = pwm_ao_reg_t7,
+ .pwm_ao_cnt = 8,
+};
+
+static char *bl_pwm_name[] = {
+ "PWM_A",
+ "PWM_B",
+ "PWM_C",
+ "PWM_D",
+ "PWM_E",
+ "PWM_F"
+};
+
+static char *bl_pwm_ao_name[] = {
+ "PWM_AO_A",
+ "PWM_AO_B",
+ "PWM_AO_C",
+ "PWM_AO_D",
+ "PWM_AO_E",
+ "PWM_AO_F",
+ "PWM_AO_G",
+ "PWM_AO_H"
+};
+
+static char bl_pwm_vs_name[] = {"PWM_VS"};
+static char bl_pwm_invalid_name[] = {"invalid"};
+
+enum bl_pwm_port_e bl_pwm_str_to_num(const char *str)
+{
+ enum bl_pwm_port_e pwm_port = BL_PWM_MAX;
+ int i, cnt;
+
+ if (!bl_pwm_ctrl_conf)
+ return BL_PWM_MAX;
+
+ cnt = bl_pwm_ctrl_conf->pwm_cnt;
+ if (cnt > ARRAY_SIZE(bl_pwm_name))
+ cnt = ARRAY_SIZE(bl_pwm_name);
+ for (i = 0; i < cnt; i++) {
+ if (strcmp(str, bl_pwm_name[i]) == 0) {
+ pwm_port = i + BL_PWM_A;
+ return pwm_port;
+ }
+ }
+
+ cnt = bl_pwm_ctrl_conf->pwm_ao_cnt;
+ if (cnt > ARRAY_SIZE(bl_pwm_ao_name))
+ cnt = ARRAY_SIZE(bl_pwm_ao_name);
+ for (i = 0; i < cnt; i++) {
+ if (strcmp(str, bl_pwm_ao_name[i]) == 0) {
+ pwm_port = i + BL_PWM_AO_A;
+ return pwm_port;
+ }
+ }
+
+ if (strcmp(str, bl_pwm_vs_name) == 0) {
+ pwm_port = BL_PWM_VS;
+ return pwm_port;
+ }
+
+ return BL_PWM_MAX;
+}
+
+char *bl_pwm_num_to_str(unsigned int num)
+{
+ unsigned int temp, cnt;
+
+ if (num < BL_PWM_AO_A) {
+ temp = num - BL_PWM_A;
+ cnt = ARRAY_SIZE(bl_pwm_name);
+ if (temp >= cnt)
+ return bl_pwm_invalid_name;
+ return bl_pwm_name[temp];
+ } else if (num < BL_PWM_VS) {
+ temp = num - BL_PWM_AO_A;
+ cnt = ARRAY_SIZE(bl_pwm_ao_name);
+ if (temp >= cnt)
+ return bl_pwm_invalid_name;
+ return bl_pwm_ao_name[temp];
+ } else if (num == BL_PWM_VS) {
+ return bl_pwm_vs_name;
+ }
+
+ return bl_pwm_invalid_name;
+}
+
+void bl_pwm_set_duty(struct bl_pwm_config_s *bl_pwm)
+{
+ unsigned int *pwm_reg;
+ int port;
+
+ if (!bl_pwm_ctrl_conf)
+ return;
+
+ switch (bl_pwm->pwm_port) {
+ case BL_PWM_A:
+ case BL_PWM_B:
+ case BL_PWM_C:
+ case BL_PWM_D:
+ case BL_PWM_E:
+ case BL_PWM_F:
+ port = bl_pwm->pwm_port - BL_PWM_A;
+ if (port >= bl_pwm_ctrl_conf->pwm_cnt) {
+ BLERR("invalid pwm_port 0x%x\n", bl_pwm->pwm_port);
+ return;
+ }
+ pwm_reg = bl_pwm_ctrl_conf->pwm_reg;
+ break;
+ case BL_PWM_AO_A:
+ case BL_PWM_AO_B:
+ case BL_PWM_AO_C:
+ case BL_PWM_AO_D:
+ case BL_PWM_AO_E:
+ case BL_PWM_AO_F:
+ case BL_PWM_AO_G:
+ case BL_PWM_AO_H:
+ port = bl_pwm->pwm_port - BL_PWM_AO_A;
+ if (port >= bl_pwm_ctrl_conf->pwm_ao_cnt) {
+ BLERR("invalid pwm_port 0x%x\n", bl_pwm->pwm_port);
+ return;
+ }
+ pwm_reg = bl_pwm_ctrl_conf->pwm_ao_reg;
+ break;
+ default:
+ return;
+ }
+
+ lcd_cbus_write(pwm_reg[port], (bl_pwm->pwm_hi << 16) | bl_pwm->pwm_lo);
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLPR("pwm_reg=0x%08x\n", lcd_cbus_read(pwm_reg[port]));
+}
+
+static void bl_set_pwm(struct aml_bl_drv_s *bdrv, struct bl_pwm_config_s *bl_pwm)
+{
+ unsigned int port = bl_pwm->pwm_port;
+ unsigned int vs[4], ve[4], sw, n, i, pol = 0;
+
+ if (bdrv->state > 0)
+ bl_set_pwm_gpio_check(bdrv, bl_pwm);
+
+ switch (bl_pwm->pwm_method) {
+ case BL_PWM_POSITIVE:
+ bl_pwm->pwm_hi = bl_pwm->pwm_level;
+ bl_pwm->pwm_lo = bl_pwm->pwm_cnt - bl_pwm->pwm_level;
+ pol = 0;
+ break;
+ case BL_PWM_NEGATIVE:
+ bl_pwm->pwm_lo = bl_pwm->pwm_level;
+ bl_pwm->pwm_hi = bl_pwm->pwm_cnt - bl_pwm->pwm_level;
+ pol = 1;
+ break;
+ default:
+ BLERR("port %d: invalid pwm_method %d\n",
+ port, bl_pwm->pwm_method);
+ break;
+ }
+
+ switch (port) {
+ case BL_PWM_VS:
+ bl_pwm->pwm_hi = bl_pwm->pwm_level;
+ memset(vs, 0xff, sizeof(unsigned int) * 4);
+ memset(ve, 0xff, sizeof(unsigned int) * 4);
+ n = bl_pwm->pwm_freq;
+ sw = (bl_pwm->pwm_cnt * 10 / n + 5) / 10;
+ bl_pwm->pwm_hi = (bl_pwm->pwm_hi * 10 / n + 5) / 10;
+ bl_pwm->pwm_hi = (bl_pwm->pwm_hi > 1) ? bl_pwm->pwm_hi : 1;
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLPR("n=%d, sw=%d, pwm_high=%d\n", n, sw, bl_pwm->pwm_hi);
+ for (i = 0; i < n; i++) {
+ vs[i] = 1 + (sw * i);
+ ve[i] = vs[i] + bl_pwm->pwm_hi - 1;
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLPR("vs[%d]=%d, ve[%d]=%d\n", i, vs[i], i, ve[i]);
+ }
+ lcd_vcbus_write(VPU_VPU_PWM_V0, (pol << 31) | (ve[0] << 16) | (vs[0]));
+ lcd_vcbus_write(VPU_VPU_PWM_V1, (ve[1] << 16) | (vs[1]));
+ lcd_vcbus_write(VPU_VPU_PWM_V2, (ve[2] << 16) | (vs[2]));
+ lcd_vcbus_write(VPU_VPU_PWM_V3, (ve[3] << 16) | (vs[3]));
+ break;
+ default:
+ bl_pwm_set_duty(bl_pwm);
+ break;
+ }
+}
+
+static unsigned int bl_level_mapping(struct bl_config_s *bconf, unsigned int level)
+{
+ unsigned int mid = bconf->level_mid;
+ unsigned int mid_map =bconf->level_mid_mapping;
+ unsigned int max = bconf->level_max;
+ unsigned int min = bconf->level_min;
+
+ if (mid == mid_map)
+ return level;
+
+ level = level > max ? max : level;
+ if ((level >= mid) && (level <= max))
+ level = (((level - mid) * (max - mid_map)) / (max - mid)) + mid_map;
+ else if ((level >= min) && (level < mid))
+ level = (((level - min) * (mid_map - min)) / (mid - min)) + min;
+ else
+ level = 0;
+
+ return level;
+}
+
+void bl_pwm_set_level(struct aml_bl_drv_s *bdrv,
+ struct bl_pwm_config_s *bl_pwm, unsigned int level)
+{
+ unsigned int min = bl_pwm->level_min;
+ unsigned int max = bl_pwm->level_max;
+ unsigned int pwm_max = bl_pwm->pwm_max;
+ unsigned int pwm_min = bl_pwm->pwm_min;
+
+ level = bl_level_mapping(&bdrv->config, level);
+ max = bl_level_mapping(&bdrv->config, max);
+ min = bl_level_mapping(&bdrv->config, min);
+ if ((max <= min) || (level < min))
+ bl_pwm->pwm_level = pwm_min;
+ else
+ bl_pwm->pwm_level =
+ (pwm_max - pwm_min) * (level - min) / (max - min) + pwm_min;
+
+ if (bl_pwm->pwm_duty_max > 100)
+ bl_pwm->pwm_duty = bl_pwm->pwm_level * 255 / bl_pwm->pwm_cnt;
+ else
+ bl_pwm->pwm_duty =
+ ((bl_pwm->pwm_level * 1000 / bl_pwm->pwm_cnt) + 5) / 10;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ BLPR("port 0x%x: level=%d, level_max=%d, level_min=%d, pwm_max=%d, pwm_min=%d, pwm_level=%d, duty=%d%%\n",
+ bl_pwm->pwm_port, level, max, min,
+ pwm_max, pwm_min, bl_pwm->pwm_level,
+ bl_pwm->pwm_duty);
+ }
+
+ bl_set_pwm(bdrv, bl_pwm);
+}
+
+void bl_pwm_en(struct bl_pwm_config_s *bl_pwm, int flag)
+{
+ struct bl_pwm_clkctrl_s *pwm_clk;
+ struct bl_pwm_misc_s *pwm_misc;
+ unsigned int port, pre_div;
+
+ if (!bl_pwm_ctrl_conf)
+ return;
+
+ pre_div = bl_pwm->pwm_pre_div;
+ switch (bl_pwm->pwm_port) {
+ case BL_PWM_A:
+ case BL_PWM_B:
+ case BL_PWM_C:
+ case BL_PWM_D:
+ case BL_PWM_E:
+ case BL_PWM_F:
+ port = bl_pwm->pwm_port - BL_PWM_A;
+ if (port >= bl_pwm_ctrl_conf->pwm_cnt) {
+ BLERR("invalid pwm_port 0x%x\n", bl_pwm->pwm_port);
+ return;
+ }
+ pwm_clk = bl_pwm_ctrl_conf->pwm_clk;
+ pwm_misc = bl_pwm_ctrl_conf->pwm_misc;
+ break;
+ case BL_PWM_AO_A:
+ case BL_PWM_AO_B:
+ case BL_PWM_AO_C:
+ case BL_PWM_AO_D:
+ case BL_PWM_AO_E:
+ case BL_PWM_AO_F:
+ case BL_PWM_AO_G:
+ case BL_PWM_AO_H:
+ port = bl_pwm->pwm_port - BL_PWM_AO_A;
+ if (port >= bl_pwm_ctrl_conf->pwm_ao_cnt) {
+ BLERR("invalid pwm_port 0x%x\n", bl_pwm->pwm_port);
+ return;
+ }
+ pwm_clk = bl_pwm_ctrl_conf->pwm_ao_clk;
+ pwm_misc = bl_pwm_ctrl_conf->pwm_ao_misc;
+ break;
+ default:
+ return;
+ }
+
+ if (flag) {
+ if (pwm_clk) {
+ lcd_cbus_setb(pwm_clk[port].reg, 0, pwm_clk[port].bit_div, 2);
+ lcd_cbus_setb(pwm_clk[port].reg, 0, pwm_clk[port].bit_sel, 8);
+ lcd_cbus_setb(pwm_clk[port].reg, 1, pwm_clk[port].bit_en, 1);
+ }
+ lcd_cbus_setb(pwm_misc[port].reg, pre_div, pwm_misc[port].bit_pre_div, 7);
+ /* pwm clk_sel */
+ lcd_cbus_setb(pwm_misc[port].reg, 0, pwm_misc[port].bit_clk_sel, 2);
+ /* pwm clk_en */
+ lcd_cbus_setb(pwm_misc[port].reg, 1, pwm_misc[port].bit_clk_en, 1);
+ /* pwm enable */
+ lcd_cbus_setb(pwm_misc[port].reg, pwm_misc[port].val_pwm_en,
+ pwm_misc[port].bit_pwm_en, 2);
+ } else {
+ /* pwm clk_disable */
+ lcd_cbus_setb(pwm_misc[port].reg, 0, pwm_misc[port].bit_clk_en, 1);
+ if (pwm_clk)
+ lcd_cbus_setb(pwm_clk[port].reg, 0, pwm_clk[port].bit_en, 1);
+ }
+}
+
+void bl_pwm_config_init(struct bl_pwm_config_s *bl_pwm)
+{
+ unsigned int freq, pre_div, cnt;
+ int i;
+
+ if (!bl_pwm) {
+ BLERR("%s: bl_pwm is NULL\n", __func__);
+ return;
+ }
+ if (bl_pwm->pwm_port >= BL_PWM_MAX)
+ return;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ BLPR("%s pwm_port 0x%x: freq = %u\n",
+ __func__, bl_pwm->pwm_port, bl_pwm->pwm_freq);
+ }
+ freq = bl_pwm->pwm_freq;
+ switch (bl_pwm->pwm_port) {
+ case BL_PWM_VS:
+ cnt = lcd_vcbus_read(ENCL_VIDEO_MAX_LNCNT) + 1;
+ bl_pwm->pwm_cnt = cnt;
+ bl_pwm->pwm_pre_div = 0;
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLPR("pwm_cnt = %u\n", bl_pwm->pwm_cnt);
+ break;
+ default:
+ for (i = 0; i < 0x7f; i++) {
+ pre_div = i;
+ cnt = XTAL_FREQ_HZ / (freq * (pre_div + 1)) - 2;
+ if (cnt <= 0xffff) /* 16bit */
+ break;
+ }
+ bl_pwm->pwm_cnt = cnt;
+ bl_pwm->pwm_pre_div = pre_div;
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLPR("pwm_cnt = %u, pwm_pre_div = %u\n", cnt, pre_div);
+ break;
+ }
+
+ if (bl_pwm->pwm_duty_max > 100) {
+ bl_pwm->pwm_max = (bl_pwm->pwm_cnt * bl_pwm->pwm_duty_max / 255);
+ bl_pwm->pwm_min = (bl_pwm->pwm_cnt * bl_pwm->pwm_duty_min / 255);
+ } else {
+ bl_pwm->pwm_max = (bl_pwm->pwm_cnt * bl_pwm->pwm_duty_max / 100);
+ bl_pwm->pwm_min = (bl_pwm->pwm_cnt * bl_pwm->pwm_duty_min / 100);
+ }
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLPR("pwm_max = %u, pwm_min = %u\n",
+ bl_pwm->pwm_max, bl_pwm->pwm_min);
+}
+
+void bl_pwm_reg_print(struct bl_pwm_config_s *bl_pwm)
+{
+ unsigned int *pwm_reg;
+ int port;
+
+ if (!bl_pwm_ctrl_conf)
+ return;
+
+ switch (bl_pwm->pwm_port) {
+ case BL_PWM_A:
+ case BL_PWM_B:
+ case BL_PWM_C:
+ case BL_PWM_D:
+ case BL_PWM_E:
+ case BL_PWM_F:
+ port = bl_pwm->pwm_port - BL_PWM_A;
+ if (port >= bl_pwm_ctrl_conf->pwm_cnt) {
+ BLERR("invalid pwm_port 0x%x\n", bl_pwm->pwm_port);
+ return;
+ }
+ pwm_reg = bl_pwm_ctrl_conf->pwm_reg;
+ break;
+ case BL_PWM_AO_A:
+ case BL_PWM_AO_B:
+ case BL_PWM_AO_C:
+ case BL_PWM_AO_D:
+ case BL_PWM_AO_E:
+ case BL_PWM_AO_F:
+ case BL_PWM_AO_G:
+ case BL_PWM_AO_H:
+ port = bl_pwm->pwm_port - BL_PWM_AO_A;
+ if (port >= bl_pwm_ctrl_conf->pwm_ao_cnt) {
+ BLERR("invalid pwm_port 0x%x\n", bl_pwm->pwm_port);
+ return;
+ }
+ pwm_reg = bl_pwm_ctrl_conf->pwm_ao_reg;
+ break;
+ default:
+ return;
+ }
+
+ BLPR("pwm_reg = 0x%08x\n", lcd_cbus_read(pwm_reg[port]));
+}
+
+int aml_bl_pwm_reg_config_init(struct aml_lcd_data_s *pdata)
+{
+ switch (pdata->chip_type) {
+ case LCD_CHIP_G12A:
+ case LCD_CHIP_G12B:
+ case LCD_CHIP_SM1:
+ case LCD_CHIP_TL1:
+ case LCD_CHIP_TM2:
+ case LCD_CHIP_T5:
+ case LCD_CHIP_T5D:
+ bl_pwm_ctrl_conf = &bl_pwm_ctrl_conf_dft;
+ break;
+ case LCD_CHIP_T7:
+ bl_pwm_ctrl_conf = &bl_pwm_ctrl_conf_t7;
+ break;
+ default:
+ bl_pwm_ctrl_conf = NULL;
+ break;
+ }
+
+ return 0;
+}
diff --git a/drivers/amlogic/media/vout/lcd/backlight/lcd_bl.c b/drivers/amlogic/media/vout/lcd/backlight/lcd_bl.c
new file mode 100644
index 0000000..6c6ffa8
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/lcd_bl.c
@@ -0,0 +1,2434 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <fdtdec.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+#ifdef CONFIG_AML_LOCAL_DIMMING
+#include <amlogic/media/vout/lcd/bl_ldim.h>
+#endif
+#ifdef CONFIG_AML_BL_EXTERN
+#include <amlogic/media/vout/lcd/bl_extern.h>
+#endif
+#include "lcd_bl.h"
+#include "../lcd_reg.h"
+#include "../lcd_common.h"
+#include "../lcd_unifykey.h"
+
+static int bl_index_lut[LCD_MAX_DRV];
+static struct aml_bl_drv_s *bl_driver[LCD_MAX_DRV];
+
+struct aml_bl_drv_s *aml_bl_get_driver(int index)
+{
+ if (index >= LCD_MAX_DRV)
+ return NULL;
+ if (!bl_driver[index])
+ return NULL;
+ if (bl_driver[index]->config.method >= BL_CTRL_MAX)
+ return NULL;
+
+ return bl_driver[index];
+}
+
+static struct bl_config_s *bl_check_valid(struct aml_bl_drv_s *bdrv)
+{
+ struct bl_config_s *bconf;
+ unsigned int bconf_flag = 1;
+#ifdef CONFIG_AML_BL_EXTERN
+ struct aml_bl_extern_driver_s *bl_ext;
+#endif
+#ifdef CONFIG_AML_LOCAL_DIMMING
+ struct ldim_driver_s *ldim_drv;
+#endif
+
+ if (!bdrv)
+ return NULL;
+
+ bconf = &bdrv->config;
+ switch (bconf->method) {
+ case BL_CTRL_PWM:
+ if (!bconf->bl_pwm) {
+ BLERR("no bl_pwm struct\n");
+ bconf_flag = 0;
+ }
+ break;
+ case BL_CTRL_PWM_COMBO:
+ if (!bconf->bl_pwm_combo0) {
+ BLERR("no bl_pwm_combo_0 struct\n");
+ bconf_flag = 0;
+ }
+ if (!bconf->bl_pwm_combo1) {
+ BLERR("no bl_pwm_combo_1 struct\n");
+ bconf_flag = 0;
+ }
+ break;
+ case BL_CTRL_GPIO:
+ break;
+#ifdef CONFIG_AML_LOCAL_DIMMING
+ case BL_CTRL_LOCAL_DIMMING:
+ ldim_drv = ldim_get_driver();
+ if (!ldim_drv) {
+ BLERR("no ldim driver\n");
+ bconf = NULL;
+ }
+ break;
+#endif
+#ifdef CONFIG_AML_BL_EXTERN
+ case BL_CTRL_EXTERN:
+ bl_ext = aml_bl_extern_get_driver();
+ if (!bl_ext) {
+ BLERR("no bl_extern driver\n");
+ bconf_flag = 0;
+ }
+ break;
+#endif
+ default:
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLPR("invalid control_method: %d\n", bconf->method);
+ bconf_flag = 0;
+ break;
+ }
+
+ if (!bconf_flag)
+ bconf = NULL;
+
+ return bconf;
+}
+
+static void bl_pwm_pinmux_gpio_set(struct aml_bl_drv_s *bdrv, int pwm_index, int gpio_level)
+{
+ struct bl_config_s *bconf;
+ struct bl_pwm_config_s *bl_pwm = NULL;
+ int gpio;
+ char *str;
+ int i;
+
+ bconf = bl_check_valid(bdrv);
+ if (!bconf)
+ return;
+
+ switch (bconf->method) {
+ case BL_CTRL_PWM:
+ bl_pwm = bconf->bl_pwm;
+ break;
+ case BL_CTRL_PWM_COMBO:
+ if (pwm_index == 0)
+ bl_pwm = bconf->bl_pwm_combo0;
+ else
+ bl_pwm = bconf->bl_pwm_combo1;
+ break;
+ default:
+ BLERR("%s: invalid method %d\n", __func__, bconf->method);
+ break;
+ }
+ if (!bl_pwm)
+ return;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ BLPR("%s: pwm_port=0x%x, pinmux_flag=%d\n",
+ __func__, bl_pwm->pwm_port, bl_pwm->pinmux_flag);
+ }
+ if (bl_pwm->pinmux_flag > 0) {
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (bl_pwm->pinmux_set[i][0] == LCD_PINMUX_END)
+ break;
+ lcd_pinmux_clr_mask(bl_pwm->pinmux_set[i][0],
+ bl_pwm->pinmux_set[i][1]);
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ BLPR("%s: port=0x%x, pinmux_clr=%d,0x%08x\n",
+ __func__, bl_pwm->pwm_port,
+ bl_pwm->pinmux_set[i][0], bl_pwm->pinmux_set[i][1]);
+ }
+ i++;
+ }
+ bl_pwm->pinmux_flag = 0;
+ }
+ /* set gpio */
+ if (bl_pwm->pwm_gpio >= BL_GPIO_NUM_MAX) {
+ gpio = LCD_GPIO_MAX;
+ } else {
+ str = bconf->gpio_name[bl_pwm->pwm_gpio];
+ gpio = lcd_gpio_name_map_num(str);
+ }
+ if (gpio < LCD_GPIO_MAX)
+ lcd_gpio_set(gpio, gpio_level);
+}
+
+static void bl_pwm_pinmux_gpio_clr(struct aml_bl_drv_s *bdrv, unsigned int pwm_index)
+{
+ struct bl_config_s *bconf;
+ struct bl_pwm_config_s *bl_pwm = NULL;
+ int i;
+
+ bconf = bl_check_valid(bdrv);
+ if (!bconf)
+ return;
+
+ switch (bconf->method) {
+ case BL_CTRL_PWM:
+ bl_pwm = bconf->bl_pwm;
+ break;
+ case BL_CTRL_PWM_COMBO:
+ if (pwm_index == 0)
+ bl_pwm = bconf->bl_pwm_combo0;
+ else
+ bl_pwm = bconf->bl_pwm_combo1;
+ break;
+ default:
+ BLERR("%s: invalid method %d\n", __func__, bconf->method);
+ break;
+ }
+ if (!bl_pwm)
+ return;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ BLPR("%s: pwm_port=0x%x, pinmux_flag=%d\n",
+ __func__, bl_pwm->pwm_port, bl_pwm->pinmux_flag);
+ }
+ if (bl_pwm->pinmux_flag > 0)
+ return;
+
+ /* set pinmux */
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (bl_pwm->pinmux_set[i][0] == LCD_PINMUX_END)
+ break;
+ lcd_pinmux_set_mask(bl_pwm->pinmux_set[i][0],
+ bl_pwm->pinmux_set[i][1]);
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ BLPR("%s: port=0x%x, pinmux_set=%d,0x%08x\n",
+ __func__, bl_pwm->pwm_port,
+ bl_pwm->pinmux_set[i][0], bl_pwm->pinmux_set[i][1]);
+ }
+ i++;
+ }
+ bl_pwm->pinmux_flag = 1;
+}
+
+void bl_set_pwm_gpio_check(struct aml_bl_drv_s *bdrv, struct bl_pwm_config_s *bl_pwm)
+{
+ unsigned int pwm_index, gpio_level;
+
+ pwm_index = bl_pwm->index;
+
+ /* pwm duty 100% or 0% special control */
+ if (bl_pwm->pwm_duty_max > 100) {
+ if (bl_pwm->pwm_duty == 0 || bl_pwm->pwm_duty == 255) {
+ switch (bl_pwm->pwm_method) {
+ case BL_PWM_POSITIVE:
+ if (bl_pwm->pwm_duty == 0)
+ gpio_level = 0;
+ else
+ gpio_level = 1;
+ break;
+ case BL_PWM_NEGATIVE:
+ if (bl_pwm->pwm_duty == 0)
+ gpio_level = 1;
+ else
+ gpio_level = 0;
+ break;
+ default:
+ BLERR("%s: port=0x%x: invalid pwm_method %d\n",
+ __func__, bl_pwm->pwm_port,
+ bl_pwm->pwm_method);
+ gpio_level = 0;
+ break;
+ }
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ BLPR("%s: pwm port=0x%x, duty=%d%%, switch to gpio %d\n",
+ __func__, bl_pwm->pwm_port,
+ bl_pwm->pwm_duty * 100 / 255, gpio_level);
+ }
+ bl_pwm_pinmux_gpio_set(bdrv, pwm_index, gpio_level);
+ } else {
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ BLPR("%s: pwm_port=0x%x set as pwm\n",
+ __func__, bl_pwm->pwm_port);
+ }
+ bl_pwm_pinmux_gpio_clr(bdrv, pwm_index);
+ }
+ } else {
+ if (bl_pwm->pwm_duty == 0 || bl_pwm->pwm_duty == 100) {
+ switch (bl_pwm->pwm_method) {
+ case BL_PWM_POSITIVE:
+ if (bl_pwm->pwm_duty == 0)
+ gpio_level = 0;
+ else
+ gpio_level = 1;
+ break;
+ case BL_PWM_NEGATIVE:
+ if (bl_pwm->pwm_duty == 0)
+ gpio_level = 1;
+ else
+ gpio_level = 0;
+ break;
+ default:
+ BLERR("%s: port=0x%x: invalid pwm_method %d\n",
+ __func__, bl_pwm->pwm_port, bl_pwm->pwm_method);
+ gpio_level = 0;
+ break;
+ }
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ BLPR("%s: pwm port=0x%x, duty=%d%%, switch to gpio %d\n",
+ __func__, bl_pwm->pwm_port, bl_pwm->pwm_duty,
+ gpio_level);
+ }
+ bl_pwm_pinmux_gpio_set(bdrv, pwm_index, gpio_level);
+ } else {
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ BLPR("%s: pwm_port=0x%x set as pwm\n",
+ __func__, bl_pwm->pwm_port);
+ }
+ bl_pwm_pinmux_gpio_clr(bdrv, pwm_index);
+ }
+ }
+}
+
+static void bl_pwm_pinmux_ctrl(struct aml_bl_drv_s *bdrv, int status)
+{
+ struct bl_config_s *bconf = &bdrv->config;
+ int gpio;
+ char *str;
+ int i;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLPR("%s: %d\n", __func__, status);
+ if (status) {
+ /* set pinmux */
+ switch (bconf->method) {
+ case BL_CTRL_PWM:
+ bl_set_pwm_gpio_check(bdrv, bconf->bl_pwm);
+ break;
+ case BL_CTRL_PWM_COMBO:
+ bl_set_pwm_gpio_check(bdrv, bconf->bl_pwm_combo0);
+ bl_set_pwm_gpio_check(bdrv, bconf->bl_pwm_combo1);
+ break;
+ default:
+ break;
+ }
+ } else {
+ switch (bconf->method) {
+ case BL_CTRL_PWM:
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (bconf->bl_pwm->pinmux_set[i][0] == LCD_PINMUX_END)
+ break;
+ lcd_pinmux_clr_mask(bconf->bl_pwm->pinmux_set[i][0],
+ bconf->bl_pwm->pinmux_set[i][1]);
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ BLPR("%s: port=0x%x, pinmux_clr=%d,0x%08x\n",
+ __func__, bconf->bl_pwm->pwm_port,
+ bconf->bl_pwm->pinmux_set[i][0],
+ bconf->bl_pwm->pinmux_set[i][1]);
+ }
+ i++;
+ }
+ bconf->bl_pwm->pinmux_flag = 0;
+
+ if (bconf->bl_pwm->pwm_gpio >= BL_GPIO_NUM_MAX) {
+ gpio = LCD_GPIO_MAX;
+ } else {
+ str = bconf->gpio_name[bconf->bl_pwm->pwm_gpio];
+ gpio = lcd_gpio_name_map_num(str);
+ }
+ if (gpio < LCD_GPIO_MAX)
+ lcd_gpio_set(gpio, bconf->bl_pwm->pwm_gpio_off);
+ break;
+ case BL_CTRL_PWM_COMBO:
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (bconf->bl_pwm_combo0->pinmux_set[i][0] == LCD_PINMUX_END)
+ break;
+ lcd_pinmux_clr_mask(bconf->bl_pwm_combo0->pinmux_set[i][0],
+ bconf->bl_pwm_combo0->pinmux_set[i][1]);
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ BLPR("%s: port=0x%x, pinmux_clr=%d,0x%08x\n",
+ __func__, bconf->bl_pwm_combo0->pwm_port,
+ bconf->bl_pwm_combo0->pinmux_set[i][0],
+ bconf->bl_pwm_combo0->pinmux_set[i][1]);
+ }
+ i++;
+ }
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (bconf->bl_pwm_combo1->pinmux_set[i][0] == LCD_PINMUX_END)
+ break;
+ lcd_pinmux_clr_mask(bconf->bl_pwm_combo1->pinmux_set[i][0],
+ bconf->bl_pwm_combo1->pinmux_set[i][1]);
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ BLPR("%s: port=0x%x, pinmux_clr=%d,0x%08x\n",
+ __func__, bconf->bl_pwm_combo1->pwm_port,
+ bconf->bl_pwm_combo1->pinmux_set[i][0],
+ bconf->bl_pwm_combo1->pinmux_set[i][1]);
+ }
+ i++;
+ }
+ bconf->bl_pwm_combo0->pinmux_flag = 0;
+ bconf->bl_pwm_combo1->pinmux_flag = 0;
+
+ if (bconf->bl_pwm_combo0->pwm_gpio >= BL_GPIO_NUM_MAX) {
+ gpio = LCD_GPIO_MAX;
+ } else {
+ str = bconf->gpio_name[bconf->bl_pwm_combo0->pwm_gpio];
+ gpio = lcd_gpio_name_map_num(str);
+ }
+ if (gpio < LCD_GPIO_MAX)
+ lcd_gpio_set(gpio, bconf->bl_pwm_combo0->pwm_gpio_off);
+ if (bconf->bl_pwm_combo1->pwm_gpio >= BL_GPIO_NUM_MAX) {
+ gpio = LCD_GPIO_MAX;
+ } else {
+ str = bconf->gpio_name[bconf->bl_pwm_combo1->pwm_gpio];
+ gpio = lcd_gpio_name_map_num(str);
+ }
+ if (gpio < LCD_GPIO_MAX)
+ lcd_gpio_set(gpio, bconf->bl_pwm_combo1->pwm_gpio_off);
+ break;
+ default:
+ break;
+ }
+ }
+}
+
+static void bl_pwm_config_update(struct bl_config_s *bconf)
+{
+#ifdef CONFIG_AML_LOCAL_DIMMING
+ struct ldim_driver_s *ldim_drv;
+#endif
+
+ if (!bconf) {
+ BLERR("bconf is null\n");
+ return;
+ }
+
+ switch (bconf->method) {
+ case BL_CTRL_PWM:
+ bl_pwm_config_init(bconf->bl_pwm);
+ break;
+ case BL_CTRL_PWM_COMBO:
+ bl_pwm_config_init(bconf->bl_pwm_combo0);
+ bl_pwm_config_init(bconf->bl_pwm_combo1);
+ break;
+#ifdef CONFIG_AML_LOCAL_DIMMING
+ case BL_CTRL_LOCAL_DIMMING:
+ ldim_drv = ldim_get_driver();
+ if (!ldim_drv) {
+ BLERR("ldim_drv is null\n");
+ break;
+ }
+ if (ldim_drv->ldev_conf) {
+ BLERR("ldim_config is null\n");
+ break;
+ }
+ if (ldim_drv->ldev_conf->ldim_pwm_config.pwm_port >= BL_PWM_MAX)
+ break;
+ bl_pwm_config_init(&ldim_drv->ldev_conf->ldim_pwm_config);
+ if (ldim_drv->ldev_conf->analog_pwm_config.pwm_port < BL_PWM_VS)
+ bl_pwm_config_init(&ldim_drv->ldev_conf->analog_pwm_config);
+ break;
+#endif
+ default:
+ break;
+ }
+}
+
+static void bl_set_level(struct aml_bl_drv_s *bdrv, unsigned int level)
+{
+ struct bl_config_s *bconf;
+ struct bl_pwm_config_s *pwm0, *pwm1;
+#ifdef CONFIG_AML_BL_EXTERN
+ struct aml_bl_extern_driver_s *bl_ext;
+#endif
+#ifdef CONFIG_AML_LOCAL_DIMMING
+ struct ldim_driver_s *ldim_drv;
+#endif
+
+ bconf = bl_check_valid(bdrv);
+ if (!bconf)
+ return;
+
+ BLPR("set level: %u, last level: %u\n", level, bdrv->level);
+ /* level range check */
+ level = (level > bconf->level_max ? bconf->level_max :
+ (level < bconf->level_min ? bconf->level_min : level));
+ bdrv->level = level;
+
+ switch (bconf->method) {
+ case BL_CTRL_GPIO:
+ break;
+ case BL_CTRL_PWM:
+ bl_pwm_set_level(bdrv, bconf->bl_pwm, level);
+ break;
+ case BL_CTRL_PWM_COMBO:
+ pwm0 = bconf->bl_pwm_combo0;
+ pwm1 = bconf->bl_pwm_combo1;
+
+ if (level >= pwm0->level_max) {
+ bl_pwm_set_level(bdrv, pwm0, pwm0->level_max);
+ } else if ((level > pwm0->level_min) &&
+ (level < pwm0->level_max)) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLPR("pwm0 region, level=%u\n", level);
+ bl_pwm_set_level(bdrv, pwm0, level);
+ } else {
+ bl_pwm_set_level(bdrv, pwm0, pwm0->level_min);
+ }
+
+ if (level >= pwm1->level_max) {
+ bl_pwm_set_level(bdrv, pwm1, pwm1->level_max);
+ } else if ((level > pwm1->level_min) &&
+ (level < pwm1->level_max)) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLPR("pwm1 region, level=%u\n", level);
+ bl_pwm_set_level(bdrv, pwm1, level);
+ } else {
+ bl_pwm_set_level(bdrv, pwm1, pwm1->level_min);
+ }
+ break;
+#ifdef CONFIG_AML_LOCAL_DIMMING
+ case BL_CTRL_LOCAL_DIMMING:
+ ldim_drv = ldim_get_driver();
+ if (ldim_drv->set_level)
+ ldim_drv->set_level(level);
+ else
+ BLERR("ldim set_level is null\n");
+ break;
+#endif
+#ifdef CONFIG_AML_BL_EXTERN
+ case BL_CTRL_EXTERN:
+ bl_ext = aml_bl_extern_get_driver();
+ if (bl_ext->set_level)
+ bl_ext->set_level(level);
+ else
+ BLERR("bl_extern set_level is null\n");
+ break;
+#endif
+ default:
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLERR("wrong backlight control method\n");
+ break;
+ }
+}
+
+static void bl_power_en_ctrl(struct bl_config_s *bconf, int status)
+{
+ int gpio;
+ char *str;
+
+ if (bconf->en_gpio >= BL_GPIO_NUM_MAX) {
+ gpio = LCD_GPIO_MAX;
+ } else {
+ str = bconf->gpio_name[bconf->en_gpio];
+ gpio = lcd_gpio_name_map_num(str);
+ }
+ if (status) {
+ if (gpio < LCD_GPIO_MAX)
+ lcd_gpio_set(gpio, bconf->en_gpio_on);
+ } else {
+ if (gpio < LCD_GPIO_MAX)
+ lcd_gpio_set(gpio, bconf->en_gpio_off);
+ }
+}
+
+static void bl_power_ctrl(struct aml_bl_drv_s *bdrv, int status)
+{
+ int gpio, value;
+ struct bl_config_s *bconf;
+#ifdef CONFIG_AML_BL_EXTERN
+ struct aml_bl_extern_driver_s *bl_ext;
+#endif
+#ifdef CONFIG_AML_LOCAL_DIMMING
+ struct ldim_driver_s *ldim_drv;
+#endif
+
+ bconf = bl_check_valid(bdrv);
+ if (!bconf)
+ return;
+
+ gpio = bconf->en_gpio;
+ value = status ? bconf->en_gpio_on : bconf->en_gpio_off;
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLPR("status=%d gpio=%d value=%d\n", status, gpio, value);
+
+ if (status) {
+ /* bl_off_policy */
+ if (bdrv->bl_off_policy != BL_OFF_POLICY_NONE) {
+ BLPR("bl_off_policy=%d for bl_off\n", bdrv->bl_off_policy);
+ return;
+ }
+
+ bdrv->state = 1;
+ /* check if factory test */
+ if (bdrv->factory_bl_on_delay >= 0) {
+ BLPR("%s: factory test power_on_delay!\n", __func__);
+ if (bdrv->factory_bl_on_delay > 0)
+ mdelay(bdrv->factory_bl_on_delay);
+ } else {
+ if (bconf->power_on_delay > 0)
+ mdelay(bconf->power_on_delay);
+ }
+
+ switch (bconf->method) {
+ case BL_CTRL_GPIO:
+ bl_power_en_ctrl(bconf, 1);
+ break;
+ case BL_CTRL_PWM:
+ if (bconf->en_sequence_reverse) {
+ /* step 1: power on enable */
+ bl_power_en_ctrl(bconf, 1);
+ if (bconf->pwm_on_delay > 0)
+ mdelay(bconf->pwm_on_delay);
+ /* step 2: power on pwm */
+ bl_pwm_en(bconf->bl_pwm, 1);
+ bl_pwm_pinmux_ctrl(bdrv, 1);
+ } else {
+ /* step 1: power on pwm */
+ bl_pwm_en(bconf->bl_pwm, 1);
+ bl_pwm_pinmux_ctrl(bdrv, 1);
+ if (bconf->pwm_on_delay > 0)
+ mdelay(bconf->pwm_on_delay);
+ /* step 2: power on enable */
+ bl_power_en_ctrl(bconf, 1);
+ }
+ break;
+ case BL_CTRL_PWM_COMBO:
+ if (bconf->en_sequence_reverse) {
+ /* step 1: power on enable */
+ bl_power_en_ctrl(bconf, 1);
+ if (bconf->pwm_on_delay > 0)
+ mdelay(bconf->pwm_on_delay);
+ /* step 2: power on pwm_combo */
+ bl_pwm_en(bconf->bl_pwm_combo0, 1);
+ bl_pwm_en(bconf->bl_pwm_combo1, 1);
+ bl_pwm_pinmux_ctrl(bdrv, 1);
+ } else {
+ /* step 1: power on pwm_combo */
+ bl_pwm_en(bconf->bl_pwm_combo0, 1);
+ bl_pwm_en(bconf->bl_pwm_combo1, 1);
+ bl_pwm_pinmux_ctrl(bdrv, 1);
+ if (bconf->pwm_on_delay > 0)
+ mdelay(bconf->pwm_on_delay);
+ /* step 2: power on enable */
+ bl_power_en_ctrl(bconf, 1);
+ }
+ break;
+#ifdef CONFIG_AML_LOCAL_DIMMING
+ case BL_CTRL_LOCAL_DIMMING:
+ ldim_drv = ldim_get_driver();
+ if (bconf->en_sequence_reverse) {
+ /* step 1: power on enable */
+ bl_power_en_ctrl(bconf, 1);
+ /* step 2: power on ldim */
+ if (ldim_drv->power_on)
+ ldim_drv->power_on();
+ else
+ BLERR("ldim power on is null\n");
+ } else {
+ /* step 1: power on ldim */
+ if (ldim_drv->power_on)
+ ldim_drv->power_on();
+ else
+ BLERR("ldim power on is null\n");
+ /* step 2: power on enable */
+ bl_power_en_ctrl(bconf, 1);
+ }
+ break;
+#endif
+#ifdef CONFIG_AML_BL_EXTERN
+ case BL_CTRL_EXTERN:
+ bl_ext = aml_bl_extern_get_driver();
+ if (bconf->en_sequence_reverse) {
+ /* step 1: power on enable */
+ bl_power_en_ctrl(bconf, 1);
+ /* step 2: power on bl_extern */
+ if (bl_ext->power_on)
+ bl_ext->power_on();
+ else
+ BLERR("bl_extern power on is null\n");
+ } else {
+ /* step 1: power on bl_extern */
+ if (bl_ext->power_on)
+ bl_ext->power_on();
+ else
+ BLERR("bl_extern power on is null\n");
+ /* step 2: power on enable */
+ bl_power_en_ctrl(bconf, 1);
+ }
+ break;
+#endif
+ default:
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLERR("wrong backlight control method\n");
+ break;
+ }
+ } else {
+ bdrv->state = 0;
+ switch (bconf->method) {
+ case BL_CTRL_GPIO:
+ bl_power_en_ctrl(bconf, 0);
+ break;
+ case BL_CTRL_PWM:
+ if (bconf->en_sequence_reverse == 1) {
+ /* step 1: power off pwm */
+ bl_pwm_pinmux_ctrl(bdrv, 0);
+ bl_pwm_en(bconf->bl_pwm, 0);
+ if (bconf->pwm_off_delay > 0)
+ mdelay(bconf->pwm_off_delay);
+ /* step 2: power off enable */
+ bl_power_en_ctrl(bconf, 0);
+ } else {
+ /* step 1: power off enable */
+ bl_power_en_ctrl(bconf, 0);
+ /* step 2: power off pwm */
+ if (bconf->pwm_off_delay > 0)
+ mdelay(bconf->pwm_off_delay);
+ bl_pwm_pinmux_ctrl(bdrv, 0);
+ bl_pwm_en(bconf->bl_pwm, 0);
+ }
+ break;
+ case BL_CTRL_PWM_COMBO:
+ if (bconf->en_sequence_reverse == 1) {
+ /* step 1: power off pwm_combo */
+ bl_pwm_pinmux_ctrl(bdrv, 0);
+ bl_pwm_en(bconf->bl_pwm_combo0, 0);
+ bl_pwm_en(bconf->bl_pwm_combo1, 0);
+ if (bconf->pwm_off_delay > 0)
+ mdelay(bconf->pwm_off_delay);
+ /* step 2: power off enable */
+ bl_power_en_ctrl(bconf, 0);
+ } else {
+ /* step 1: power off enable */
+ bl_power_en_ctrl(bconf, 0);
+ /* step 2: power off pwm_combo */
+ if (bconf->pwm_off_delay > 0)
+ mdelay(bconf->pwm_off_delay);
+ bl_pwm_pinmux_ctrl(bdrv, 0);
+ bl_pwm_en(bconf->bl_pwm_combo0, 0);
+ bl_pwm_en(bconf->bl_pwm_combo1, 0);
+ }
+ break;
+#ifdef CONFIG_AML_LOCAL_DIMMING
+ case BL_CTRL_LOCAL_DIMMING:
+ ldim_drv = ldim_get_driver();
+ if (bconf->en_sequence_reverse == 1) {
+ /* step 1: power off ldim */
+ if (ldim_drv->power_off)
+ ldim_drv->power_off();
+ else
+ BLERR("ldim power off is null\n");
+ /* step 2: power off enable */
+ bl_power_en_ctrl(bconf, 0);
+ } else {
+ /* step 1: power off enable */
+ bl_power_en_ctrl(bconf, 0);
+ /* step 2: power off ldim */
+ if (ldim_drv->power_off)
+ ldim_drv->power_off();
+ else
+ BLERR("ldim power off is null\n");
+ }
+ break;
+#endif
+#ifdef CONFIG_AML_BL_EXTERN
+ case BL_CTRL_EXTERN:
+ bl_ext = aml_bl_extern_get_driver();
+ if (bconf->en_sequence_reverse == 1) {
+ /* step 1: power off bl_extern */
+ if (bl_ext->power_off)
+ bl_ext->power_off();
+ else
+ BLERR("bl_extern: power off is null\n");
+ /* step 2: power off enable */
+ bl_power_en_ctrl(bconf, 0);
+ } else {
+ /* step 1: power off enable */
+ bl_power_en_ctrl(bconf, 0);
+ /* step 2: power off bl_extern */
+ if (bl_ext->power_off)
+ bl_ext->power_off();
+ else
+ BLERR("bl_extern: power off is null\n");
+ }
+ break;
+#endif
+ default:
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLERR("wrong backlight control method\n");
+ break;
+ }
+ if (bconf->power_off_delay > 0)
+ mdelay(bconf->power_off_delay);
+ }
+ BLPR("%s: %d\n", __func__, status);
+}
+
+static void bl_power_init_off(struct aml_bl_drv_s *bdrv)
+{
+ struct bl_config_s *bconf;
+
+ bconf = bl_check_valid(bdrv);
+ if (!bconf)
+ return;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ BLPR("[%d]: init_off: gpio=%d value=%d\n",
+ bdrv->index,
+ bconf->en_gpio, bconf->en_gpio_off);
+ }
+
+ bdrv->state = 0;
+ switch (bconf->method) {
+ case BL_CTRL_PWM:
+ case BL_CTRL_PWM_COMBO:
+ bl_power_en_ctrl(bconf, 0);
+ bl_pwm_pinmux_ctrl(bdrv, 0);
+ break;
+ default:
+ bl_power_en_ctrl(bconf, 0);
+ break;
+ }
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLPR("%s finish\n", __func__);
+}
+
+static void bl_config_print(struct aml_bl_drv_s *bdrv)
+{
+ struct bl_config_s *bconf = &bdrv->config;
+ struct bl_pwm_config_s *bl_pwm;
+#ifdef CONFIG_AML_LOCAL_DIMMING
+ struct ldim_driver_s *ldim_drv = ldim_get_driver();
+#endif
+#ifdef CONFIG_AML_BL_EXTERN
+ struct aml_bl_extern_driver_s *bl_extern = aml_bl_extern_get_driver();
+#endif
+
+ BLPR("drv_index: %d\n", bdrv->index);
+ BLPR("key_valid: %d\n", bdrv->key_valid);
+ BLPR("state : 0x%x\n", bdrv->state);
+ BLPR("bl_off_policy: %d\n", bdrv->bl_off_policy);
+
+ BLPR("name: %s\n", bconf->name);
+ BLPR("method: %d\n", bconf->method);
+
+ BLPR("level_default = %d\n", bconf->level_default);
+ BLPR("level_min = %d\n", bconf->level_min);
+ BLPR("level_max = %d\n", bconf->level_max);
+ BLPR("level_mid = %d\n", bconf->level_mid);
+ BLPR("level_mid_mapping = %d\n", bconf->level_mid_mapping);
+
+ BLPR("en_gpio = %s(%d)\n",
+ bconf->gpio_name[bconf->en_gpio], bconf->en_gpio);
+ BLPR("en_gpio_on = %d\n", bconf->en_gpio_on);
+ BLPR("en_gpio_off = %d\n", bconf->en_gpio_off);
+ /* check if factory test */
+ if (bdrv->factory_bl_on_delay >= 0)
+ BLPR("factory test power_on_delay = %d\n", bdrv->factory_bl_on_delay);
+ else
+ BLPR("power_on_delay = %d\n", bconf->power_on_delay);
+ BLPR("power_off_delay = %d\n\n", bconf->power_off_delay);
+ switch (bconf->method) {
+ case BL_CTRL_PWM:
+ if (bconf->bl_pwm) {
+ bl_pwm = bconf->bl_pwm;
+ BLPR("pwm_index = %d\n", bl_pwm->index);
+ BLPR("pwm_method = %d\n", bl_pwm->pwm_method);
+ BLPR("pwm_port = 0x%x\n", bl_pwm->pwm_port);
+ if (bl_pwm->pwm_port == BL_PWM_VS) {
+ BLPR("pwm_freq = %d x vfreq\n", bl_pwm->pwm_freq);
+ BLPR("pwm_cnt = %u\n", bl_pwm->pwm_cnt);
+ if (bl_pwm->pwm_duty_max > 100) {
+ BLPR("pwm_duty = %d%%(%d)\n",
+ bl_pwm->pwm_duty * 100 / 255, bl_pwm->pwm_duty);
+ } else {
+ BLPR("pwm_duty = %d%%(%d)\n",
+ bl_pwm->pwm_duty, bl_pwm->pwm_duty);
+ }
+
+ BLPR("pwm_reg0 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V0));
+ BLPR("pwm_reg1 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V1));
+ BLPR("pwm_reg2 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V2));
+ BLPR("pwm_reg3 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V3));
+ } else {
+ BLPR("pwm_freq = %uHz\n", bl_pwm->pwm_freq);
+ BLPR("pwm_cnt = %u\n", bl_pwm->pwm_cnt);
+ BLPR("pwm_pre_div = %u\n", bl_pwm->pwm_pre_div);
+ if (bl_pwm->pwm_duty_max > 100) {
+ BLPR("pwm_duty = %d%%(%d)\n",
+ bl_pwm->pwm_duty * 100 / 255, bl_pwm->pwm_duty);
+ } else {
+ BLPR("pwm_duty = %d%%(%d)\n",
+ bl_pwm->pwm_duty, bl_pwm->pwm_duty);
+ }
+
+ bl_pwm_reg_print(bl_pwm);
+ }
+ BLPR("pwm_duty_max = %d\n", bl_pwm->pwm_duty_max);
+ BLPR("pwm_duty_min = %d\n", bl_pwm->pwm_duty_min);
+ BLPR("pwm_gpio = %s(%d)\n",
+ bconf->gpio_name[bl_pwm->pwm_gpio], bl_pwm->pwm_gpio);
+ BLPR("pwm_gpio_off = %d\n", bl_pwm->pwm_gpio_off);
+ }
+ BLPR("pwm_on_delay = %d\n", bconf->pwm_on_delay);
+ BLPR("pwm_off_delay = %d\n", bconf->pwm_off_delay);
+ BLPR("en_sequence_reverse = %d\n", bconf->en_sequence_reverse);
+ break;
+ case BL_CTRL_PWM_COMBO:
+ if (bconf->bl_pwm_combo0) {
+ bl_pwm = bconf->bl_pwm_combo0;
+ BLPR("pwm_combo0_index = %d\n", bl_pwm->index);
+ BLPR("pwm_combo0_method = %d\n", bl_pwm->pwm_method);
+ BLPR("pwm_combo0_port = 0x%x\n", bl_pwm->pwm_port);
+ if (bl_pwm->pwm_port == BL_PWM_VS) {
+ BLPR("pwm_combo0_freq = %d x vfreq\n", bl_pwm->pwm_freq);
+ BLPR("pwm_combo0_cnt = %u\n", bl_pwm->pwm_cnt);
+ if (bl_pwm->pwm_duty_max > 100)
+ BLPR("pwm_combo0_duty = %d%%(%d)\n",
+ bl_pwm->pwm_duty * 100 / 255, bl_pwm->pwm_duty);
+ else
+ BLPR("pwm_combo0_duty = %d%%(%d)\n",
+ bl_pwm->pwm_duty, bl_pwm->pwm_duty);
+
+ BLPR("pwm_combo0_reg0 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V0));
+ BLPR("pwm_combo0_reg1 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V1));
+ BLPR("pwm_combo0_reg2 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V2));
+ BLPR("pwm_combo0_reg3 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V3));
+ } else {
+ BLPR("pwm_combo0_freq = %uHz\n", bl_pwm->pwm_freq);
+ BLPR("pwm_combo0_cnt = %u\n", bl_pwm->pwm_cnt);
+ BLPR("pwm_combo0_pre_div = %u\n", bl_pwm->pwm_pre_div);
+ if (bl_pwm->pwm_duty_max > 100)
+ BLPR("pwm_combo0_duty = %d%%(%d)\n",
+ bl_pwm->pwm_duty * 100 / 255, bl_pwm->pwm_duty);
+ else
+ BLPR("pwm_combo0_duty = %d%%(%d)\n",
+ bl_pwm->pwm_duty, bl_pwm->pwm_duty);
+
+ bl_pwm_reg_print(bl_pwm);
+ }
+ BLPR("pwm_combo0_duty_max = %d\n", bl_pwm->pwm_duty_max);
+ BLPR("pwm_combo0_duty_min = %d\n", bl_pwm->pwm_duty_min);
+ BLPR("pwm_combo0_gpio = %s(%d)\n",
+ bconf->gpio_name[bl_pwm->pwm_gpio], bl_pwm->pwm_gpio);
+ BLPR("pwm_combo0_gpio_off = %d\n", bl_pwm->pwm_gpio_off);
+ }
+ if (bconf->bl_pwm_combo1) {
+ bl_pwm = bconf->bl_pwm_combo1;
+ BLPR("pwm_combo1_index = %d\n", bl_pwm->index);
+ BLPR("pwm_combo1_method = %d\n", bl_pwm->pwm_method);
+ BLPR("pwm_combo1_port = 0x%x\n", bl_pwm->pwm_port);
+ if (bl_pwm->pwm_port == BL_PWM_VS) {
+ BLPR("pwm_combo1_freq = %d x vfreq\n", bl_pwm->pwm_freq);
+ BLPR("pwm_combo1_cnt = %u\n", bl_pwm->pwm_cnt);
+ if (bl_pwm->pwm_duty_max > 100) {
+ BLPR("bl:pwm_combo1_duty = %d%% %d\n",
+ bl_pwm->pwm_duty * 100 / 255, bl_pwm->pwm_duty);
+ } else {
+ BLPR("bl:pwm_combo1_duty = %d%% %d\n",
+ bl_pwm->pwm_duty, bl_pwm->pwm_duty);
+ }
+
+ BLPR("pwm_combo1_reg0 = 0x%08x\n",
+ lcd_vcbus_read(VPU_VPU_PWM_V0));
+ BLPR("pwm_combo1_reg1 = 0x%08x\n",
+ lcd_vcbus_read(VPU_VPU_PWM_V1));
+ BLPR("pwm_combo1_reg2 = 0x%08x\n",
+ lcd_vcbus_read(VPU_VPU_PWM_V2));
+ BLPR("pwm_combo1_reg3 = 0x%08x\n",
+ lcd_vcbus_read(VPU_VPU_PWM_V3));
+ } else {
+ BLPR("pwm_combo1_freq = %uHz\n",
+ bl_pwm->pwm_freq);
+ BLPR("pwm_combo1_cnt = %u\n",
+ bl_pwm->pwm_cnt);
+ BLPR("pwm_combo1_pre_div = %u\n",
+ bl_pwm->pwm_pre_div);
+ if (bl_pwm->pwm_duty_max > 100) {
+ BLPR("pwm_combo1_duty = %d%%(%d)\n",
+ bl_pwm->pwm_duty * 100 / 255, bl_pwm->pwm_duty);
+ } else {
+ BLPR("pwm_combo1_duty = %d%%(%d)\n",
+ bl_pwm->pwm_duty, bl_pwm->pwm_duty);
+ }
+
+ bl_pwm_reg_print(bl_pwm);
+ }
+ BLPR("pwm_combo1_duty_max = %d\n", bl_pwm->pwm_duty_max);
+ BLPR("pwm_combo1_duty_min = %d\n", bl_pwm->pwm_duty_min);
+ BLPR("pwm_combo1_gpio = %s(%d)\n",
+ bconf->gpio_name[bl_pwm->pwm_gpio], bl_pwm->pwm_gpio);
+ BLPR("pwm_combo1_gpio_off = %d\n", bl_pwm->pwm_gpio_off);
+ }
+ BLPR("pwm_on_delay = %d\n", bconf->pwm_on_delay);
+ BLPR("pwm_off_delay = %d\n", bconf->pwm_off_delay);
+ BLPR("en_sequence_reverse = %d\n", bconf->en_sequence_reverse);
+ break;
+#ifdef CONFIG_AML_LOCAL_DIMMING
+ case BL_CTRL_LOCAL_DIMMING:
+ if (!ldim_drv) {
+ BLPR("invalid local dimming driver\n");
+ break;
+ }
+ if (ldim_drv->config_print)
+ ldim_drv->config_print();
+ break;
+#endif
+#ifdef CONFIG_AML_BL_EXTERN
+ case BL_CTRL_EXTERN:
+ if (!bl_extern) {
+ BLPR("invalid bl extern driver\n");
+ break;
+ }
+ if (bl_extern->config_print)
+ bl_extern->config_print();
+ break;
+#endif
+
+ default:
+ BLPR("invalid backlight control method\n");
+ break;
+ }
+}
+
+#ifdef CONFIG_OF_LIBFDT
+static int bl_config_load_from_dts(char *dt_addr, struct aml_bl_drv_s *bdrv)
+{
+ int parent_offset, child_offset;
+ char sname[20], propname[30];
+ char *propdata;
+ char *p;
+ const char *str;
+ struct bl_config_s *bconf = &bdrv->config;
+ struct bl_pwm_config_s *bl_pwm;
+ struct bl_pwm_config_s *pwm_combo0, *pwm_combo1;
+
+ if (bdrv->index == 0)
+ sprintf(sname, "/backlight");
+ else
+ sprintf(sname, "/backlight%d", bdrv->index);
+
+ bconf->method = BL_CTRL_MAX; /* default */
+ parent_offset = fdt_path_offset(dt_addr, "sname");
+ if (parent_offset < 0) {
+ BLPR("not find %s node %s\n",
+ sname,
+ fdt_strerror(parent_offset));
+ return -1;
+ }
+ propdata = (char *)fdt_getprop(dt_addr, parent_offset, "status", NULL);
+ if (!propdata) {
+ BLPR("not find status, default to disabled\n");
+ return -1;
+ } else {
+ if (strncmp(propdata, "okay", 2)) {
+ BLPR("status disabled\n");
+ return -1;
+ }
+ }
+
+ sprintf(propname,"%s/backlight_%d", sname, bconf->index);
+ child_offset = fdt_path_offset(dt_addr, propname);
+ if (child_offset < 0) {
+ BLERR("not find %s node: %s\n", propname, fdt_strerror(child_offset));
+ return -1;
+ }
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset, "bl_name", NULL);
+ if (!propdata) {
+ BLERR("failed to get bl_name\n");
+ sprintf(bconf->name, "backlight_%d", bconf->index);
+ } else {
+ strcpy(bconf->name, propdata);
+ }
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "bl_level_default_uboot_kernel", NULL);
+ if (!propdata) {
+ BLERR("failed to get bl_level_default_uboot_kernel\n");
+ bconf->level_default = BL_LEVEL_DEFAULT;
+ } else {
+ bconf->level_default = be32_to_cpup((u32*)propdata);
+ }
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "bl_level_attr", NULL);
+ if (!propdata) {
+ BLERR("failed to get bl_level_attr\n");
+ bconf->level_max = BL_LEVEL_MAX;
+ bconf->level_min = BL_LEVEL_MIN;
+ bconf->level_mid = BL_LEVEL_MID;
+ bconf->level_mid_mapping = BL_LEVEL_MID_MAPPED;
+ } else {
+ bconf->level_max = be32_to_cpup((u32 *)propdata);
+ bconf->level_min = be32_to_cpup((((u32 *)propdata) + 1));
+ bconf->level_mid = be32_to_cpup((((u32 *)propdata) + 2));
+ bconf->level_mid_mapping =
+ be32_to_cpup((((u32 *)propdata) + 3));
+ }
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "bl_ctrl_method", NULL);
+ if (!propdata) {
+ BLERR("failed to get bl_ctrl_method\n");
+ bconf->method = BL_CTRL_MAX;
+ return -1;
+ } else {
+ bconf->method = be32_to_cpup((u32 *)propdata);
+ }
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "bl_power_attr", NULL);
+ if (!propdata) {
+ BLERR("failed to get bl_power_attr\n");
+ bconf->en_gpio = BL_GPIO_NUM_MAX;
+ bconf->en_gpio_on = LCD_GPIO_OUTPUT_HIGH;
+ bconf->en_gpio_off = LCD_GPIO_OUTPUT_LOW;
+ bconf->power_on_delay = 100;
+ bconf->power_off_delay = 30;
+ } else {
+ bconf->en_gpio = be32_to_cpup((u32 *)propdata);
+ bconf->en_gpio_on = be32_to_cpup((((u32 *)propdata) + 1));
+ bconf->en_gpio_off = be32_to_cpup((((u32 *)propdata) + 2));
+ bconf->power_on_delay = be32_to_cpup((((u32 *)propdata) + 3));
+ bconf->power_off_delay = be32_to_cpup((((u32 *)propdata) + 4));
+ }
+
+ switch (bconf->method) {
+ case BL_CTRL_PWM:
+ if (!bconf->bl_pwm) {
+ bconf->bl_pwm = (struct bl_pwm_config_s *)
+ malloc(sizeof(struct bl_pwm_config_s));
+ if (!bconf->bl_pwm) {
+ BLERR("bl_pwm malloc error\n");
+ return -1;
+ }
+ }
+ bl_pwm = bconf->bl_pwm;
+ memset(bl_pwm, 0, sizeof(struct bl_pwm_config_s));
+ bl_pwm->index = 0;
+
+ bl_pwm->level_max = bconf->level_max;
+ bl_pwm->level_min = bconf->level_min;
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "bl_pwm_port", NULL);
+ if (!propdata) {
+ BLERR("failed to get bl_pwm_port\n");
+ bl_pwm->pwm_port = BL_PWM_MAX;
+ } else {
+ bl_pwm->pwm_port = bl_pwm_str_to_num(propdata);
+ }
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "bl_pwm_attr", NULL);
+ if (!propdata) {
+ BLERR("failed to get bl_pwm_attr\n");
+ bl_pwm->pwm_method = BL_PWM_POSITIVE;
+ if (bl_pwm->pwm_port == BL_PWM_VS)
+ bl_pwm->pwm_freq = BL_FREQ_VS_DEFAULT;
+ else
+ bl_pwm->pwm_freq = BL_FREQ_DEFAULT;
+ bl_pwm->pwm_duty_max = 80;
+ bl_pwm->pwm_duty_min = 20;
+ } else {
+ bl_pwm->pwm_method = be32_to_cpup((u32 *)propdata);
+ bl_pwm->pwm_freq =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ bl_pwm->pwm_duty_max =
+ be32_to_cpup((((u32 *)propdata) + 2));
+ bl_pwm->pwm_duty_min =
+ be32_to_cpup((((u32 *)propdata) + 3));
+ }
+ if (bl_pwm->pwm_port == BL_PWM_VS) {
+ if (bl_pwm->pwm_freq > 4) {
+ BLERR("bl_pwm_vs wrong freq %d\n",
+ bl_pwm->pwm_freq);
+ bl_pwm->pwm_freq = BL_FREQ_VS_DEFAULT;
+ }
+ } else {
+ if (bl_pwm->pwm_freq > XTAL_HALF_FREQ_HZ)
+ bl_pwm->pwm_freq = XTAL_HALF_FREQ_HZ;
+ }
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "bl_pwm_power", NULL);
+ if (!propdata) {
+ BLERR("failed to get bl_pwm_power\n");
+ bl_pwm->pwm_gpio = BL_GPIO_NUM_MAX;
+ bl_pwm->pwm_gpio_off = LCD_GPIO_OUTPUT_LOW;
+ bconf->pwm_on_delay = 10;
+ bconf->pwm_off_delay = 10;
+ } else {
+ bl_pwm->pwm_gpio = be32_to_cpup((u32 *)propdata);
+ bl_pwm->pwm_gpio_off =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ bconf->pwm_on_delay =
+ be32_to_cpup((((u32 *)propdata) + 2));
+ bconf->pwm_off_delay =
+ be32_to_cpup((((u32 *)propdata) + 3));
+ }
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "bl_pwm_en_sequence_reverse",
+ NULL);
+ if (!propdata) {
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "en_sequence_reverse",
+ NULL);
+ if (!propdata) {
+ bconf->en_sequence_reverse = 0;
+ } else {
+ bconf->en_sequence_reverse =
+ be32_to_cpup((u32 *)propdata);
+ BLPR("find en_sequence_reverse: %d\n",
+ bconf->en_sequence_reverse);
+ }
+ } else {
+ bconf->en_sequence_reverse = be32_to_cpup((u32 *)propdata);
+ BLPR("find en_sequence_reverse: %d\n",
+ bconf->en_sequence_reverse);
+ }
+
+ bl_pwm->pwm_duty = bl_pwm->pwm_duty_min;
+ /* bl_pwm_config_init(bl_pwm); */
+ break;
+ case BL_CTRL_PWM_COMBO:
+ if (!bconf->bl_pwm_combo0) {
+ bconf->bl_pwm_combo0 = (struct bl_pwm_config_s *)
+ malloc(sizeof(struct bl_pwm_config_s));
+ if (!bconf->bl_pwm_combo0) {
+ BLERR("bl_pwm_combo0 malloc error\n");
+ return -1;
+ }
+ }
+ if (!bconf->bl_pwm_combo1) {
+ bconf->bl_pwm_combo1 = (struct bl_pwm_config_s *)
+ malloc(sizeof(struct bl_pwm_config_s));
+ if (!bconf->bl_pwm_combo1) {
+ free(bconf->bl_pwm_combo0);
+ BLERR("bl_pwm_combo1 struct malloc error\n");
+ return -1;
+ }
+ }
+ pwm_combo0 = bconf->bl_pwm_combo0;
+ pwm_combo1 = bconf->bl_pwm_combo1;
+ memset(pwm_combo0, 0, sizeof(struct bl_pwm_config_s));
+ memset(pwm_combo1, 0, sizeof(struct bl_pwm_config_s));
+ pwm_combo0->index = 0;
+ pwm_combo1->index = 1;
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "bl_pwm_combo_level_mapping",
+ NULL);
+ if (!propdata) {
+ BLERR("failed to get bl_pwm_combo_level_mapping\n");
+ pwm_combo0->level_max = BL_LEVEL_MAX;
+ pwm_combo0->level_min = BL_LEVEL_MID;
+ pwm_combo1->level_max = BL_LEVEL_MID;
+ pwm_combo1->level_min = BL_LEVEL_MIN;
+ } else {
+ pwm_combo0->level_max = be32_to_cpup((u32 *)propdata);
+ pwm_combo0->level_min =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ pwm_combo1->level_max =
+ be32_to_cpup((((u32 *)propdata) + 2));
+ pwm_combo1->level_min =
+ be32_to_cpup((((u32 *)propdata) + 3));
+ }
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "bl_pwm_combo_port", NULL);
+ if (!propdata) {
+ BLERR("failed to get bl_pwm_combo_port\n");
+ pwm_combo0->pwm_port = BL_PWM_MAX;
+ pwm_combo1->pwm_port = BL_PWM_MAX;
+ } else {
+ p = propdata;
+ str = p;
+ pwm_combo0->pwm_port = bl_pwm_str_to_num(str);
+ p += strlen(p) + 1;
+ str = p;
+ pwm_combo1->pwm_port = bl_pwm_str_to_num(str);
+ }
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "bl_pwm_combo_attr", NULL);
+ if (!propdata) {
+ BLERR("failed to get bl_pwm_combo_attr\n");
+ pwm_combo0->pwm_method = BL_PWM_POSITIVE;
+ if (pwm_combo0->pwm_port == BL_PWM_VS)
+ pwm_combo0->pwm_freq = BL_FREQ_VS_DEFAULT;
+ else
+ pwm_combo0->pwm_freq = BL_FREQ_DEFAULT;
+ pwm_combo0->pwm_duty_max = 80;
+ pwm_combo0->pwm_duty_min = 20;
+ pwm_combo1->pwm_method = BL_PWM_POSITIVE;
+ if (pwm_combo1->pwm_port == BL_PWM_VS)
+ pwm_combo1->pwm_freq = BL_FREQ_VS_DEFAULT;
+ else
+ pwm_combo1->pwm_freq = BL_FREQ_DEFAULT;
+ pwm_combo1->pwm_duty_max = 80;
+ pwm_combo1->pwm_duty_min = 20;
+ } else {
+ pwm_combo0->pwm_method = be32_to_cpup((u32 *)propdata);
+ pwm_combo0->pwm_freq =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ pwm_combo0->pwm_duty_max =
+ be32_to_cpup((((u32 *)propdata) + 2));
+ pwm_combo0->pwm_duty_min =
+ be32_to_cpup((((u32 *)propdata) + 3));
+ pwm_combo1->pwm_method =
+ be32_to_cpup((((u32 *)propdata) + 4));
+ pwm_combo1->pwm_freq =
+ be32_to_cpup((((u32 *)propdata) + 5));
+ pwm_combo1->pwm_duty_max =
+ be32_to_cpup((((u32 *)propdata) + 6));
+ pwm_combo1->pwm_duty_min =
+ be32_to_cpup((((u32 *)propdata) + 7));
+ }
+ if (pwm_combo0->pwm_port == BL_PWM_VS) {
+ if (pwm_combo0->pwm_freq > 4) {
+ BLERR("bl_pwm_vs wrong freq %d\n",
+ pwm_combo0->pwm_freq);
+ pwm_combo0->pwm_freq = BL_FREQ_VS_DEFAULT;
+ }
+ } else {
+ if (pwm_combo0->pwm_freq > XTAL_HALF_FREQ_HZ)
+ pwm_combo0->pwm_freq = XTAL_HALF_FREQ_HZ;
+ }
+ if (pwm_combo1->pwm_port == BL_PWM_VS) {
+ if (pwm_combo1->pwm_freq > 4) {
+ BLERR("bl_pwm_vs wrong freq %d\n",
+ pwm_combo1->pwm_freq);
+ pwm_combo1->pwm_freq = BL_FREQ_VS_DEFAULT;
+ }
+ } else {
+ if (pwm_combo1->pwm_freq > XTAL_HALF_FREQ_HZ)
+ pwm_combo1->pwm_freq = XTAL_HALF_FREQ_HZ;
+ }
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "bl_pwm_combo_power", NULL);
+ if (!propdata) {
+ BLERR("failed to get bl_pwm_combo_power\n");
+ pwm_combo0->pwm_gpio = BL_GPIO_NUM_MAX;
+ pwm_combo0->pwm_gpio_off = LCD_GPIO_INPUT;
+ pwm_combo1->pwm_gpio = BL_GPIO_NUM_MAX;
+ pwm_combo1->pwm_gpio_off = LCD_GPIO_INPUT;
+ bconf->pwm_on_delay = 10;
+ bconf->pwm_off_delay = 10;
+ } else {
+ pwm_combo0->pwm_gpio =
+ be32_to_cpup((u32 *)propdata);
+ pwm_combo0->pwm_gpio_off =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ pwm_combo1->pwm_gpio =
+ be32_to_cpup((((u32 *)propdata) + 2));
+ pwm_combo1->pwm_gpio_off =
+ be32_to_cpup((((u32 *)propdata) + 3));
+ bconf->pwm_on_delay =
+ be32_to_cpup((((u32 *)propdata) + 4));
+ bconf->pwm_off_delay =
+ be32_to_cpup((((u32 *)propdata) + 5));
+ }
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "bl_pwm_en_sequence_reverse",
+ NULL);
+ if (!propdata) {
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "en_sequence_reverse",
+ NULL);
+ if (!propdata) {
+ bconf->en_sequence_reverse = 0;
+ } else {
+ bconf->en_sequence_reverse =
+ be32_to_cpup((u32 *)propdata);
+ BLPR("find en_sequence_reverse: %d\n",
+ bconf->en_sequence_reverse);
+ }
+ } else {
+ bconf->en_sequence_reverse =
+ be32_to_cpup((u32 *)propdata);
+ }
+
+ pwm_combo0->pwm_duty = pwm_combo0->pwm_duty_min;
+ pwm_combo1->pwm_duty = pwm_combo1->pwm_duty_min;
+ /* bl_pwm_config_init(pwm_combo0);
+ bl_pwm_config_init(pwm_combo1); */
+ break;
+#ifdef CONFIG_AML_LOCAL_DIMMING
+ case BL_CTRL_LOCAL_DIMMING:
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "en_sequence_reverse", NULL);
+ if (!propdata) {
+ bconf->en_sequence_reverse = 0;
+ } else {
+ bconf->en_sequence_reverse = be32_to_cpup((u32 *)propdata);
+ BLPR("find en_sequence_reverse: %d\n", bconf->en_sequence_reverse);
+ }
+
+ ldim_config_load_from_dts(dt_addr, child_offset);
+ ldim_probe(dt_addr, 0);
+ break;
+#endif
+#ifdef CONFIG_AML_BL_EXTERN
+ case BL_CTRL_EXTERN:
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "en_sequence_reverse", NULL);
+ if (!propdata) {
+ bconf->en_sequence_reverse = 0;
+ } else {
+ bconf->en_sequence_reverse = be32_to_cpup((u32 *)propdata);
+ BLPR("find en_sequence_reverse: %d\n", bconf->en_sequence_reverse);
+ }
+
+ /* get bl_extern_index from dts */
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "bl_extern_index", NULL);
+ if (!propdata) {
+ BLERR("failed to get bl_extern_index\n");
+ } else {
+ bconf->bl_extern_index = be32_to_cpup((u32 *)propdata);
+ BLPR("get bl_extern_index = %d\n", bconf->bl_extern_index);
+ }
+ bl_extern_device_load(dt_addr, bconf->bl_extern_index);
+ break;
+#endif
+
+ default:
+ break;
+ }
+
+ return 0;
+}
+#endif
+
+static int bl_config_load_from_unifykey(char *dt_addr, struct aml_bl_drv_s *bdrv)
+{
+ unsigned char *para;
+ int key_len, len;
+ unsigned char *p;
+ const char *str;
+ char sname[20];
+ struct lcd_unifykey_header_s bl_header;
+ struct bl_config_s *bconf = &bdrv->config;
+ struct bl_pwm_config_s *bl_pwm;
+ struct bl_pwm_config_s *pwm_combo0, *pwm_combo1;
+ int ret;
+
+ key_len = LCD_UKEY_BL_SIZE;
+ para = (unsigned char *)malloc(sizeof(unsigned char) * key_len);
+ if (!para) {
+ BLERR("%s: Not enough memory\n", __func__);
+ return -1;
+ }
+ memset(para, 0, (sizeof(unsigned char) * key_len));
+
+ if (bdrv->index == 0)
+ sprintf(sname, "/backlight");
+ else
+ sprintf(sname, "/backlight%d", bdrv->index);
+ ret = lcd_unifykey_get(sname, para, &key_len);
+ if (ret) {
+ free(para);
+ return -1;
+ }
+
+ /* step 1: check header */
+ len = LCD_UKEY_HEAD_SIZE;
+ ret = lcd_unifykey_len_check(key_len, len);
+ if (ret) {
+ BLERR("unifykey header length is incorrect\n");
+ free(para);
+ return -1;
+ }
+
+ lcd_unifykey_header_check(para, &bl_header);
+ BLPR("unifykey version: 0x%04x\n", bl_header.version);
+ switch (bl_header.version) {
+ case 2:
+ len = 10 + 30 + 12 + 8 + 32 + 10;
+ break;
+ default:
+ len = 10 + 30 + 12 + 8 + 32;
+ break;
+ }
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ BLPR("unifykey header:\n");
+ BLPR("crc32 = 0x%08x\n", bl_header.crc32);
+ BLPR("data_len = %d\n", bl_header.data_len);
+ BLPR("reserved = 0x%04x\n", bl_header.reserved);
+ }
+
+ /* step 2: check backlight parameters */
+ ret = lcd_unifykey_len_check(key_len, len);
+ if (ret) {
+ BLERR("unifykey length is incorrect\n");
+ free(para);
+ return -1;
+ }
+
+ /* basic: 30byte */
+ p = para;
+ str = (const char *)(p + LCD_UKEY_HEAD_SIZE);
+ strncpy(bconf->name, str, sizeof(bconf->name) - 1);
+ bconf->name[sizeof(bconf->name) - 1] = '\0';
+
+ /* level: 12byte */
+ bconf->level_default = (*(p + LCD_UKEY_BL_LEVEL_UBOOT) |
+ ((*(p + LCD_UKEY_BL_LEVEL_UBOOT + 1)) << 8));
+ bconf->level_max = (*(p + LCD_UKEY_BL_LEVEL_MAX) |
+ ((*(p + LCD_UKEY_BL_LEVEL_MAX + 1)) << 8));
+ bconf->level_min = (*(p + LCD_UKEY_BL_LEVEL_MIN) |
+ ((*(p + LCD_UKEY_BL_LEVEL_MIN + 1)) << 8));
+ bconf->level_mid = (*(p + LCD_UKEY_BL_LEVEL_MID) |
+ ((*(p + LCD_UKEY_BL_LEVEL_MID + 1)) << 8));
+ bconf->level_mid_mapping = (*(p + LCD_UKEY_BL_LEVEL_MID_MAP) |
+ ((*(p + LCD_UKEY_BL_LEVEL_MID_MAP + 1)) << 8));
+
+ /* method: 8byte */
+ bconf->method = *(p + LCD_UKEY_BL_METHOD);
+ bconf->en_gpio = *(p + LCD_UKEY_BL_EN_GPIO);
+ bconf->en_gpio_on = *(p + LCD_UKEY_BL_EN_GPIO_ON);
+ bconf->en_gpio_off = *(p + LCD_UKEY_BL_EN_GPIO_OFF);
+ bconf->power_on_delay = (*(p + LCD_UKEY_BL_ON_DELAY) |
+ ((*(p + LCD_UKEY_BL_ON_DELAY + 1)) << 8));
+ bconf->power_off_delay = (*(p + LCD_UKEY_BL_OFF_DELAY) |
+ ((*(p + LCD_UKEY_BL_OFF_DELAY + 1)) << 8));
+
+ /* pwm: 32byte */
+ switch (bconf->method) {
+ case BL_CTRL_PWM:
+ bconf->bl_pwm = (struct bl_pwm_config_s *)
+ malloc(sizeof(struct bl_pwm_config_s));
+ if (!bconf->bl_pwm) {
+ BLERR("bl_pwm struct malloc error\n");
+ free(para);
+ return -1;
+ }
+ bl_pwm = bconf->bl_pwm;
+ bl_pwm->index = 0;
+
+ bl_pwm->level_max = bconf->level_max;
+ bl_pwm->level_min = bconf->level_min;
+
+ bconf->pwm_on_delay = (*(p + LCD_UKEY_BL_PWM_ON_DELAY) |
+ ((*(p + LCD_UKEY_BL_PWM_ON_DELAY + 1)) << 8));
+ bconf->pwm_off_delay = (*(p + LCD_UKEY_BL_PWM_OFF_DELAY) |
+ ((*(p + LCD_UKEY_BL_PWM_OFF_DELAY + 1)) << 8));
+ bl_pwm->pwm_method = *(p + LCD_UKEY_BL_PWM_METHOD);
+ bl_pwm->pwm_port = *(p + LCD_UKEY_BL_PWM_PORT);
+ bl_pwm->pwm_freq = (*(p + LCD_UKEY_BL_PWM_FREQ) |
+ ((*(p + LCD_UKEY_BL_PWM_FREQ + 1)) << 8) |
+ ((*(p + LCD_UKEY_BL_PWM_FREQ + 2)) << 8) |
+ ((*(p + LCD_UKEY_BL_PWM_FREQ + 3)) << 8));
+ if (bl_pwm->pwm_port == BL_PWM_VS) {
+ if (bl_pwm->pwm_freq > 4) {
+ BLERR("bl_pwm_vs wrong freq %d\n", bl_pwm->pwm_freq);
+ bl_pwm->pwm_freq = BL_FREQ_VS_DEFAULT;
+ }
+ } else {
+ if (bl_pwm->pwm_freq > XTAL_HALF_FREQ_HZ)
+ bl_pwm->pwm_freq = XTAL_HALF_FREQ_HZ;
+ }
+ bl_pwm->pwm_duty_max = *(p + LCD_UKEY_BL_PWM_DUTY_MAX);
+ bl_pwm->pwm_duty_min = *(p + LCD_UKEY_BL_PWM_DUTY_MIN);
+ bl_pwm->pwm_gpio = *(p + LCD_UKEY_BL_PWM_GPIO);
+ bl_pwm->pwm_gpio_off = *(p + LCD_UKEY_BL_PWM_GPIO_OFF);
+
+ if (bl_header.version == 2)
+ bconf->en_sequence_reverse =
+ (*(p + LCD_UKEY_BL_CUST_VAL_0) |
+ ((*(p + LCD_UKEY_BL_CUST_VAL_0 + 1)) << 8));
+ else
+ bconf->en_sequence_reverse = 0;
+
+ bl_pwm->pwm_duty = bl_pwm->pwm_duty_min;
+ /* bl_pwm_config_init(bl_pwm); */
+ break;
+ case BL_CTRL_PWM_COMBO:
+ bconf->bl_pwm_combo0 = (struct bl_pwm_config_s *)
+ malloc(sizeof(struct bl_pwm_config_s));
+ if (!bconf->bl_pwm_combo0) {
+ BLERR("bl_pwm_combo0 struct malloc error\n");
+ free(para);
+ return -1;
+ }
+ bconf->bl_pwm_combo1 = (struct bl_pwm_config_s *)
+ malloc(sizeof(struct bl_pwm_config_s));
+ if (!bconf->bl_pwm_combo1) {
+ BLERR("bl_pwm_combo1 struct malloc error\n");
+ free(para);
+ return -1;
+ }
+ pwm_combo0 = bconf->bl_pwm_combo0;
+ pwm_combo1 = bconf->bl_pwm_combo1;
+ pwm_combo0->index = 0;
+ pwm_combo1->index = 1;
+
+ bconf->pwm_on_delay = (*(p + LCD_UKEY_BL_PWM_ON_DELAY) |
+ ((*(p + LCD_UKEY_BL_PWM_ON_DELAY + 1)) << 8));
+ bconf->pwm_off_delay = (*(p + LCD_UKEY_BL_PWM_OFF_DELAY) |
+ ((*(p + LCD_UKEY_BL_PWM_OFF_DELAY + 1)) << 8));
+ pwm_combo0->pwm_method = *(p + LCD_UKEY_BL_PWM_METHOD);
+ pwm_combo0->pwm_port = *(p + LCD_UKEY_BL_PWM_PORT);
+ pwm_combo0->pwm_freq = (*(p + LCD_UKEY_BL_PWM_FREQ) |
+ ((*(p + LCD_UKEY_BL_PWM_FREQ + 1)) << 8) |
+ ((*(p + LCD_UKEY_BL_PWM_FREQ + 2)) << 8) |
+ ((*(p + LCD_UKEY_BL_PWM_FREQ + 3)) << 8));
+ if (pwm_combo0->pwm_port == BL_PWM_VS) {
+ if (pwm_combo0->pwm_freq > 4) {
+ BLERR("bl_pwm_vs wrong freq %d\n",
+ pwm_combo0->pwm_freq);
+ pwm_combo0->pwm_freq = BL_FREQ_VS_DEFAULT;
+ }
+ } else {
+ if (pwm_combo0->pwm_freq > XTAL_HALF_FREQ_HZ)
+ pwm_combo0->pwm_freq = XTAL_HALF_FREQ_HZ;
+ }
+ pwm_combo0->pwm_duty_max = *(p + LCD_UKEY_BL_PWM_DUTY_MAX);
+ pwm_combo0->pwm_duty_min = *(p + LCD_UKEY_BL_PWM_DUTY_MIN);
+ pwm_combo0->pwm_gpio = *(p + LCD_UKEY_BL_PWM_GPIO);
+ pwm_combo0->pwm_gpio_off = *(p + LCD_UKEY_BL_PWM_GPIO_OFF);
+ pwm_combo1->pwm_method = *(p + LCD_UKEY_BL_PWM2_METHOD);
+ pwm_combo1->pwm_port = *(p + LCD_UKEY_BL_PWM2_PORT);
+ pwm_combo1->pwm_freq = (*(p + LCD_UKEY_BL_PWM2_FREQ) |
+ ((*(p + LCD_UKEY_BL_PWM2_FREQ + 1)) << 8) |
+ ((*(p + LCD_UKEY_BL_PWM2_FREQ + 2)) << 8) |
+ ((*(p + LCD_UKEY_BL_PWM2_FREQ + 3)) << 8));
+ if (pwm_combo1->pwm_port == BL_PWM_VS) {
+ if (pwm_combo1->pwm_freq > 4) {
+ BLERR("bl_pwm_vs wrong freq %d\n",
+ pwm_combo1->pwm_freq);
+ pwm_combo1->pwm_freq = BL_FREQ_VS_DEFAULT;
+ }
+ } else {
+ if (pwm_combo1->pwm_freq > XTAL_HALF_FREQ_HZ)
+ pwm_combo1->pwm_freq = XTAL_HALF_FREQ_HZ;
+ }
+ pwm_combo1->pwm_duty_max = *(p + LCD_UKEY_BL_PWM2_DUTY_MAX);
+ pwm_combo1->pwm_duty_min = *(p + LCD_UKEY_BL_PWM2_DUTY_MIN);
+ pwm_combo1->pwm_gpio = *(p + LCD_UKEY_BL_PWM2_GPIO);
+ pwm_combo1->pwm_gpio_off = *(p + LCD_UKEY_BL_PWM2_GPIO_OFF);
+
+ pwm_combo0->level_max = (*(p + LCD_UKEY_BL_PWM_LEVEL_MAX) |
+ ((*(p + LCD_UKEY_BL_PWM_LEVEL_MAX + 1)) << 8));
+ pwm_combo0->level_min = (*(p + LCD_UKEY_BL_PWM_LEVEL_MIN) |
+ ((*(p + LCD_UKEY_BL_PWM_LEVEL_MIN + 1)) << 8));
+ pwm_combo1->level_max = (*(p + LCD_UKEY_BL_PWM2_LEVEL_MAX) |
+ ((*(p + LCD_UKEY_BL_PWM2_LEVEL_MAX + 1)) << 8));
+ pwm_combo1->level_min = (*(p + LCD_UKEY_BL_PWM2_LEVEL_MIN) |
+ ((*(p + LCD_UKEY_BL_PWM2_LEVEL_MIN + 1)) << 8));
+
+ if (bl_header.version == 2)
+ bconf->en_sequence_reverse = (*(p + LCD_UKEY_BL_CUST_VAL_0) |
+ ((*(p + LCD_UKEY_BL_CUST_VAL_0 + 1)) << 8));
+ else
+ bconf->en_sequence_reverse = 0;
+
+ pwm_combo0->pwm_duty = pwm_combo0->pwm_duty_min;
+ pwm_combo1->pwm_duty = pwm_combo1->pwm_duty_min;
+ /* bl_pwm_config_init(pwm_combo0);
+ bl_pwm_config_init(pwm_combo1); */
+ break;
+#ifdef CONFIG_AML_LOCAL_DIMMING
+ case BL_CTRL_LOCAL_DIMMING:
+ if (bl_header.version == 2) {
+ ldim_config_load_from_unifykey(para);
+ } else {
+ BLERR("not support ldim for unifykey version: %d\n",
+ bl_header.version);
+ }
+ ldim_probe(dt_addr, 2);
+ break;
+#endif
+ default:
+ break;
+ }
+
+ free(para);
+ return 0;
+}
+
+static int bl_config_load_from_bsp(struct aml_bl_drv_s *bdrv)
+{
+ struct ext_lcd_config_s *ext_lcd = NULL;
+ char *panel_type, sname[20];
+ unsigned int i = 0, j, done;
+ char *str;
+ struct bl_config_s *bconf = &bdrv->config;
+ struct bl_pwm_config_s *bl_pwm;
+ struct bl_pwm_config_s *pwm_combo0, *pwm_combo1;
+ char (*bl_gpio)[LCD_CPU_GPIO_NAME_MAX];
+
+ if (!bdrv->data)
+ return -1;
+
+ if (bdrv->index == 0)
+ sprintf(sname, "panel_type");
+ else
+ sprintf(sname, "panel%d_type", bdrv->index);
+ panel_type = env_get(sname);
+ if (!panel_type) {
+ BLERR("no %s\n", sname);
+ return -1;
+ }
+
+ if (!bdrv->data->dft_conf[bdrv->index]) {
+ BLERR("no dft_conf\n");
+ return -1;
+ }
+
+ ext_lcd = bdrv->data->dft_conf[bdrv->index]->ext_lcd;
+ if (!ext_lcd) {
+ BLERR("%s: ext_lcd is NULL\n", __func__);
+ return -1;
+ }
+
+ done = 0;
+ for (i = 0; i < LCD_NUM_MAX; i++) {
+ if (strcmp(ext_lcd->panel_type, panel_type) == 0) {
+ done = 1;
+ break;
+ }
+ if (strcmp(ext_lcd->panel_type, "invalid") == 0)
+ break;
+ ext_lcd++;
+ }
+ if (done == 0) {
+ BLERR("can't find %s\n ", panel_type);
+ return -1;
+ }
+
+ strncpy(bconf->name, panel_type, sizeof(bconf->name) - 1);
+ bconf->name[sizeof(bconf->name) - 1] = '\0';
+
+ bconf->level_default = ext_lcd->level_default;
+ bconf->level_min = ext_lcd->level_min;
+ bconf->level_max = ext_lcd->level_max;
+ bconf->level_mid = ext_lcd->level_mid;
+ bconf->level_mid_mapping = ext_lcd->level_mid_mapping;
+
+ bconf->method = ext_lcd->bl_method;
+
+ if (ext_lcd->bl_en_gpio >= BL_GPIO_NUM_MAX)
+ bconf->en_gpio = LCD_GPIO_MAX;
+ else
+ bconf->en_gpio = ext_lcd->bl_en_gpio;
+ bconf->en_gpio_on = ext_lcd->bl_en_gpio_on;
+ bconf->en_gpio_off = ext_lcd->bl_en_gpio_off;
+ bconf->power_on_delay = ext_lcd->bl_power_on_delay;
+ bconf->power_off_delay = ext_lcd->bl_power_off_delay;
+
+ switch (bconf->method) {
+ case BL_CTRL_PWM:
+ bl_pwm = (struct bl_pwm_config_s *)malloc(sizeof(struct bl_pwm_config_s));
+ if (!bl_pwm) {
+ BLERR("bl_pwm struct malloc error\n");
+ return -1;
+ }
+ bconf->bl_pwm = bl_pwm;
+ bl_pwm->index = 0;
+
+ bl_pwm->level_max = bconf->level_max;
+ bl_pwm->level_min = bconf->level_min;
+
+ bl_pwm->pwm_method = ext_lcd->pwm_method;
+ bl_pwm->pwm_port = ext_lcd->pwm_port;
+ bl_pwm->pwm_freq = ext_lcd->pwm_freq;
+ bl_pwm->pwm_duty_max = ext_lcd->pwm_duty_max;
+ bl_pwm->pwm_duty_min = ext_lcd->pwm_duty_min;
+
+ bl_pwm->pwm_gpio = ext_lcd->pwm_gpio;
+ bl_pwm->pwm_gpio_off = ext_lcd->pwm_gpio_off;
+ bconf->pwm_on_delay = ext_lcd->pwm_on_delay;
+ bconf->pwm_off_delay = ext_lcd->pwm_off_delay;
+
+ bl_pwm->pwm_duty = bl_pwm->pwm_duty_min;
+ /* bl_pwm_config_init(bl_pwm); */
+ break;
+ case BL_CTRL_PWM_COMBO:
+ bconf->bl_pwm_combo0 = (struct bl_pwm_config_s *)
+ malloc(sizeof(struct bl_pwm_config_s));
+ if (!bconf->bl_pwm_combo0) {
+ BLERR("bl_pwm_combo0 struct malloc error\n");
+ return -1;
+ }
+ bconf->bl_pwm_combo1 = (struct bl_pwm_config_s *)
+ malloc(sizeof(struct bl_pwm_config_s));
+ if (!bconf->bl_pwm_combo1) {
+ BLERR("bl_pwm_combo1 struct malloc error\n");
+ return -1;
+ }
+ pwm_combo0 = bconf->bl_pwm_combo0;
+ pwm_combo1 = bconf->bl_pwm_combo1;
+ pwm_combo0->index = 0;
+ pwm_combo1->index = 1;
+
+ pwm_combo0->level_max = ext_lcd->pwm_level_max;
+ pwm_combo0->level_min = ext_lcd->pwm_level_min;
+ pwm_combo1->level_max = ext_lcd->pwm2_level_max;
+ pwm_combo1->level_min = ext_lcd->pwm2_level_min;
+
+ pwm_combo0->pwm_method = ext_lcd->pwm_method;
+ pwm_combo0->pwm_port = ext_lcd->pwm_port;
+ pwm_combo0->pwm_freq = ext_lcd->pwm_freq;
+ pwm_combo0->pwm_duty_max = ext_lcd->pwm_duty_max;
+ pwm_combo0->pwm_duty_min = ext_lcd->pwm_duty_min;
+ if (ext_lcd->pwm_gpio >= BL_GPIO_NUM_MAX) {
+ pwm_combo0->pwm_gpio = LCD_GPIO_MAX;
+ } else {
+ str = bconf->gpio_name[ext_lcd->pwm_gpio];
+ pwm_combo0->pwm_gpio = lcd_gpio_name_map_num(str);
+ }
+ pwm_combo0->pwm_gpio_off = ext_lcd->pwm_gpio_off;
+ pwm_combo1->pwm_method = ext_lcd->pwm2_method;
+ pwm_combo1->pwm_port = ext_lcd->pwm2_port;
+ pwm_combo1->pwm_freq = ext_lcd->pwm2_freq;
+ pwm_combo1->pwm_duty_max = ext_lcd->pwm2_duty_max;
+ pwm_combo1->pwm_duty_min = ext_lcd->pwm2_duty_min;
+ if (ext_lcd->pwm2_gpio >= BL_GPIO_NUM_MAX) {
+ pwm_combo1->pwm_gpio = LCD_GPIO_MAX;
+ } else {
+ str = bconf->gpio_name[ext_lcd->pwm2_gpio];
+ pwm_combo1->pwm_gpio = lcd_gpio_name_map_num(str);
+ }
+ pwm_combo1->pwm_gpio_off = ext_lcd->pwm2_gpio_off;
+ bconf->pwm_on_delay = ext_lcd->pwm_on_delay;
+ bconf->pwm_off_delay = ext_lcd->pwm_off_delay;
+
+ pwm_combo0->pwm_duty = pwm_combo0->pwm_duty_min;
+ pwm_combo1->pwm_duty = pwm_combo1->pwm_duty_min;
+ /* bl_pwm_config_init(pwm_combo0);
+ bl_pwm_config_init(pwm_combo1); */
+ break;
+#ifdef CONFIG_AML_LOCAL_DIMMING
+ case BL_CTRL_LOCAL_DIMMING:
+ ldim_probe(NULL, 1);
+ break;
+#endif
+#ifdef CONFIG_AML_BL_EXTERN
+ case BL_CTRL_EXTERN:
+ bl_extern_device_load(NULL, bconf->bl_extern_index);
+ break;
+#endif
+ default:
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLPR("invalid backlight control method\n");
+ break;
+ }
+
+ i = 0;
+ bl_gpio = bdrv->data->dft_conf[bdrv->index]->bl_gpio;
+ if (!bl_gpio) {
+ LCDERR("%s: bl_gpio is null\n", __func__);
+ return -1;
+ }
+ while (i < BL_GPIO_NUM_MAX) {
+ if (strcmp(bl_gpio[i], "invalid") == 0)
+ break;
+ strcpy(bconf->gpio_name[i], bl_gpio[i]);
+ i++;
+ }
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bconf->gpio_name[j], "invalid");
+
+ return 0;
+}
+
+static const char *bl_pinmux_str[] = {
+ "bl_pwm_on_pin", /* 0 */
+ "bl_pwm_vs_on_pin", /* 1 */
+ "bl_pwm_combo_0_on_pin", /* 2 */
+ "bl_pwm_combo_1_on_pin", /* 3 */
+ "bl_pwm_combo_0_vs_on_pin", /* 4 */
+ "bl_pwm_combo_1_vs_on_pin", /* 5 */
+};
+
+static int bl_pinmux_load_from_bsp(struct aml_bl_drv_s *bdrv)
+{
+ struct bl_config_s *bconf = &bdrv->config;
+ char propname[50];
+ struct lcd_pinmux_ctrl_s *pinmux;
+ unsigned int i, j;
+ int pinmux_index = 0, set_cnt = 0, clr_cnt = 0;
+ struct bl_pwm_config_s *bl_pwm;
+ struct bl_pwm_config_s *pwm_combo0, *pwm_combo1;
+
+ if (!bdrv->data)
+ return -1;
+ if (!bdrv->data->dft_conf[bdrv->index]) {
+ BLERR("%s: dft_conf is NULL\n", __func__);
+ return -1;
+ }
+ bconf->bl_pinmux = bdrv->data->dft_conf[bdrv->index]->bl_pinmux;
+ if (!bconf->bl_pinmux) {
+ BLERR("%s: bl_pinmux is NULL\n", __func__);
+ return -1;
+ }
+
+ switch (bconf->method) {
+ case BL_CTRL_PWM:
+ bl_pwm = bconf->bl_pwm;
+ if (bl_pwm->pwm_port == BL_PWM_VS)
+ pinmux_index = 1;
+ else
+ pinmux_index = 0;
+ sprintf(propname,"%s", bl_pinmux_str[pinmux_index]);
+ pinmux = bconf->bl_pinmux;
+ for (i = 0; i < LCD_PINMX_MAX; i++) {
+ if (!pinmux)
+ break;
+ if (!pinmux->name)
+ break;
+ if (strncmp(pinmux->name, "invalid", 7) == 0)
+ break;
+ if (strncmp(pinmux->name, propname, strlen(propname)) == 0) {
+ for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
+ if (pinmux->pinmux_set[j][0] ==
+ LCD_PINMUX_END)
+ break;
+ bl_pwm->pinmux_set[j][0] =
+ pinmux->pinmux_set[j][0];
+ bl_pwm->pinmux_set[j][1] =
+ pinmux->pinmux_set[j][1];
+ set_cnt++;
+ }
+ for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
+ if (pinmux->pinmux_clr[j][0] ==
+ LCD_PINMUX_END)
+ break;
+ bl_pwm->pinmux_clr[j][0] =
+ pinmux->pinmux_clr[j][0];
+ bl_pwm->pinmux_clr[j][1] =
+ pinmux->pinmux_clr[j][1];
+ clr_cnt++;
+ }
+ break;
+ }
+ pinmux++;
+ }
+ if (set_cnt < LCD_PINMUX_NUM) {
+ bl_pwm->pinmux_set[set_cnt][0] = LCD_PINMUX_END;
+ bl_pwm->pinmux_set[set_cnt][1] = 0x0;
+ }
+ if (clr_cnt < LCD_PINMUX_NUM) {
+ bl_pwm->pinmux_clr[clr_cnt][0] = LCD_PINMUX_END;
+ bl_pwm->pinmux_clr[clr_cnt][1] = 0x0;
+ }
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (bl_pwm->pinmux_set[i][0] == LCD_PINMUX_END)
+ break;
+ BLPR("bl_pinmux set: %d, 0x%08x\n",
+ bl_pwm->pinmux_set[i][0],
+ bl_pwm->pinmux_set[i][1]);
+ i++;
+ }
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (bl_pwm->pinmux_clr[i][0] == LCD_PINMUX_END)
+ break;
+ BLPR("bl_pinmux clr: %d, 0x%08x\n",
+ bl_pwm->pinmux_clr[i][0],
+ bl_pwm->pinmux_clr[i][1]);
+ i++;
+ }
+ }
+ break;
+ case BL_CTRL_PWM_COMBO:
+ pwm_combo0 = bconf->bl_pwm_combo0;
+ pwm_combo1 = bconf->bl_pwm_combo1;
+ if (pwm_combo0->pwm_port == BL_PWM_VS)
+ sprintf(propname, "%s", bl_pinmux_str[4]);
+ else
+ sprintf(propname, "%s", bl_pinmux_str[2]);
+
+ pinmux = bconf->bl_pinmux;
+ for (i = 0; i < LCD_PINMX_MAX; i++) {
+ if (!pinmux)
+ break;
+ if (!pinmux->name)
+ break;
+ if (strncmp(pinmux->name, "invalid", 7) == 0)
+ break;
+ if (strncmp(pinmux->name, propname,
+ strlen(propname)) == 0) {
+ for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
+ if (pinmux->pinmux_set[j][0] ==
+ LCD_PINMUX_END)
+ break;
+ pwm_combo0->pinmux_set[j][0] =
+ pinmux->pinmux_set[j][0];
+ pwm_combo0->pinmux_set[j][1] =
+ pinmux->pinmux_set[j][1];
+ set_cnt++;
+ }
+ for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
+ if (pinmux->pinmux_clr[j][0] ==
+ LCD_PINMUX_END)
+ break;
+ pwm_combo0->pinmux_clr[j][0] =
+ pinmux->pinmux_clr[j][0];
+ pwm_combo0->pinmux_clr[j][1] =
+ pinmux->pinmux_clr[j][1];
+ clr_cnt++;
+ }
+ break;
+ }
+ pinmux++;
+ }
+ if (set_cnt < LCD_PINMUX_NUM) {
+ pwm_combo0->pinmux_set[set_cnt][0] = LCD_PINMUX_END;
+ pwm_combo0->pinmux_set[set_cnt][1] = 0x0;
+ }
+ if (clr_cnt < LCD_PINMUX_NUM) {
+ pwm_combo0->pinmux_clr[clr_cnt][0] = LCD_PINMUX_END;
+ pwm_combo0->pinmux_clr[clr_cnt][1] = 0x0;
+ }
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (pwm_combo0->pinmux_set[i][0] ==
+ LCD_PINMUX_END)
+ break;
+ BLPR("pwm_combo0 pinmux_set: %d, 0x%08x\n",
+ pwm_combo0->pinmux_set[i][0],
+ pwm_combo0->pinmux_set[i][1]);
+ i++;
+ }
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (pwm_combo0->pinmux_clr[i][0] ==
+ LCD_PINMUX_END)
+ break;
+ BLPR("pwm_combo0 pinmux_clr: %d, 0x%08x\n",
+ pwm_combo0->pinmux_clr[i][0],
+ pwm_combo0->pinmux_clr[i][1]);
+ i++;
+ }
+ }
+
+ if (pwm_combo1->pwm_port == BL_PWM_VS)
+ sprintf(propname, "%s", bl_pinmux_str[5]);
+ else
+ sprintf(propname, "%s", bl_pinmux_str[3]);
+
+ pinmux = bconf->bl_pinmux;
+ set_cnt = 0;
+ clr_cnt = 0;
+ for (i = 0; i < LCD_PINMX_MAX; i++) {
+ if (!pinmux)
+ break;
+ if (!pinmux->name)
+ break;
+ if (strncmp(pinmux->name, "invalid", 7) == 0)
+ break;
+ if (strncmp(pinmux->name, propname,
+ strlen(propname)) == 0) {
+ for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
+ if (pinmux->pinmux_set[j][0] ==
+ LCD_PINMUX_END)
+ break;
+ pwm_combo1->pinmux_set[j][0] =
+ pinmux->pinmux_set[j][0];
+ pwm_combo1->pinmux_set[j][1] =
+ pinmux->pinmux_set[j][1];
+ set_cnt++;
+ }
+ for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
+ if (pinmux->pinmux_clr[j][0] ==
+ LCD_PINMUX_END)
+ break;
+ pwm_combo1->pinmux_clr[j][0] =
+ pinmux->pinmux_clr[j][0];
+ pwm_combo1->pinmux_clr[j][1] =
+ pinmux->pinmux_clr[j][1];
+ clr_cnt++;
+ }
+ break;
+ }
+ pinmux++;
+ }
+ if (set_cnt < LCD_PINMUX_NUM) {
+ pwm_combo1->pinmux_set[set_cnt][0] = LCD_PINMUX_END;
+ pwm_combo1->pinmux_set[set_cnt][1] = 0x0;
+ }
+ if (clr_cnt < LCD_PINMUX_NUM) {
+ pwm_combo1->pinmux_clr[clr_cnt][0] = LCD_PINMUX_END;
+ pwm_combo1->pinmux_clr[clr_cnt][1] = 0x0;
+ }
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (pwm_combo1->pinmux_set[i][0] == LCD_PINMUX_END)
+ break;
+ BLPR("pwm_combo1 pinmux_set: %d, 0x%08x\n",
+ pwm_combo1->pinmux_set[i][0],
+ pwm_combo1->pinmux_set[i][1]);
+ i++;
+ }
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (pwm_combo1->pinmux_clr[i][0] == LCD_PINMUX_END)
+ break;
+ BLPR("pwm_combo1 pinmux_clr: %d, 0x%08x\n",
+ pwm_combo1->pinmux_clr[i][0],
+ pwm_combo1->pinmux_clr[i][1]);
+ i++;
+ }
+ }
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
+
+static int bl_config_load(char *dt_addr, int load_id, struct aml_bl_drv_s *bdrv)
+{
+ char *bl_off_policy_str, str[30];
+ unsigned int temp;
+ int ret;
+
+ bdrv->state = 0;
+
+ /* load bl config */
+ if (load_id & 0x1) { /* dts */
+ if (load_id & 0x10) { /* unifykey */
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLPR("[%d]: load config from unifykey\n", bdrv->index);
+ ret = bl_config_load_from_unifykey(dt_addr, bdrv);
+ } else { /* dts */
+#ifdef CONFIG_OF_LIBFDT
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLPR("[%d]: load config from dts\n", bdrv->index);
+ if (bdrv->config.index == 0xff) {
+ bdrv->config.method = BL_CTRL_MAX;
+ BLPR("[%d]: no backlight exist\n", bdrv->index);
+ return -1;
+ }
+ ret = bl_config_load_from_dts(dt_addr, bdrv);
+#endif
+ }
+ } else { /* bsp */
+ if (load_id & 0x10) { /* unifykey */
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLPR("[%d]: load config from unifykey\n", bdrv->index);
+ ret = bl_config_load_from_unifykey(dt_addr, bdrv);
+ } else { /* bsp */
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLPR("[%d]: load config from bsp\n", bdrv->index);
+ ret = bl_config_load_from_bsp(bdrv);
+ }
+ }
+ if (ret) {
+ bdrv->config.method = BL_CTRL_MAX;
+ BLPR("[%d]: invalid backlight config\n", bdrv->index);
+ return -1;
+ }
+ bl_pinmux_load_from_bsp(bdrv);
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ bl_config_print(bdrv);
+ } else {
+ BLPR("[%d]: name: %s, method: %d\n",
+ bdrv->index, bdrv->config.name, bdrv->config.method);
+ }
+
+ /* get bl_off_policy */
+ bdrv->bl_off_policy = BL_OFF_POLICY_NONE;
+ if (bdrv->index == 0)
+ sprintf(str, "bl_off");
+ else
+ sprintf(str, "bl%d_off", bdrv->index);
+ bl_off_policy_str = env_get(str);
+ if (bl_off_policy_str) {
+ if (strncmp(bl_off_policy_str, "none", 2) == 0)
+ bdrv->bl_off_policy = BL_OFF_POLICY_NONE;
+ else if (strncmp(bl_off_policy_str, "always", 2) == 0)
+ bdrv->bl_off_policy = BL_OFF_POLICY_ALWAYS;
+ else if (strncmp(bl_off_policy_str, "once", 2) == 0)
+ bdrv->bl_off_policy = BL_OFF_POLICY_ONCE;
+ BLPR("[%d]: bl_off_policy: %s\n", bdrv->index, bl_off_policy_str);
+ }
+
+ /* get bl_level */
+ if (bdrv->index == 0)
+ sprintf(str, "bl_level");
+ else
+ sprintf(str, "bl%d_level", bdrv->index);
+ temp = env_get_ulong(str, 10, 0xffff);
+ if (temp != 0xffff) {
+ bdrv->config.level_default = temp;
+ BLPR("[%d]: bl_level: %d\n", bdrv->index, bdrv->config.level_default);
+ }
+
+ /* get factory_bl_on_delay */
+ if (bdrv->index == 0)
+ sprintf(str, "factory_bl_on_delay");
+ else
+ sprintf(str, "factory_bl%d_on_delay", bdrv->index);
+ temp = env_get_ulong(str, 10, 0xffff);
+ if (temp != 0xffff) {
+ bdrv->config.level_default = temp;
+ BLPR("[%d]: bl_level: %d\n", bdrv->index, bdrv->config.level_default);
+ }
+
+ return 0;
+}
+
+static int lcd_bl_init_load_from_dts(char *dtaddr, struct aml_bl_drv_s *bdrv)
+{
+#ifdef CONFIG_OF_LIBFDT
+ int parent_offset;
+ char *propdata, *p, snode[15];
+ const char *str;
+ int i, j;
+ int ret = 0;
+
+ if (bdrv->index == 0)
+ sprintf(snode, "/backlight");
+ else
+ sprintf(snode, "/backlight%d", bdrv->index);
+
+ /* check key_valid */
+ parent_offset = fdt_path_offset(dtaddr, snode);
+ if (parent_offset < 0) {
+ BLERR("not find %s node: %s\n", snode, fdt_strerror(parent_offset));
+ return -1;
+ }
+ propdata = (char *)fdt_getprop(dtaddr, parent_offset, "key_valid", NULL);
+ if (!propdata) {
+ BLERR("failed to get key_valid\n");
+ bdrv->key_valid = 0;
+ } else {
+ bdrv->key_valid = be32_to_cpup((u32*)propdata);
+ }
+
+ propdata = (char *)fdt_getprop(dtaddr, parent_offset, "status", NULL);
+ if (!propdata) {
+ BLPR("failed to get status, default to disabled\n");
+ return -1;
+ } else {
+ if (strncmp(propdata, "okay", 2)) {
+ BLPR("status disabled\n");
+ return -1;
+ }
+ }
+
+ /* gpio */
+ i = 0;
+ propdata = (char *)fdt_getprop(dtaddr, parent_offset, "bl_gpio_names", NULL);
+ if (!propdata) {
+ BLERR("failed to get bl_gpio_names\n");
+ } else {
+ p = propdata;
+ while (i < BL_GPIO_NUM_MAX) {
+ if (i > 0)
+ p += strlen(p) + 1;
+ str = p;
+ if (strlen(str) == 0)
+ break;
+ strcpy(bdrv->config.gpio_name[i], str);
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLPR("i=%d, gpio=%s\n", i, bdrv->config.gpio_name[i]);
+ i++;
+ }
+ }
+
+ for (j = i; j < BL_GPIO_NUM_MAX; j++)
+ strcpy(bdrv->config.gpio_name[j], "invalid");
+
+ return ret;
+#elif
+ return -1;
+#endif
+}
+
+static int lcd_bl_init_load_from_bsp(struct aml_bl_drv_s *bdrv)
+{
+ return 0;
+}
+
+int aml_bl_probe(char *dtaddr, int load_id)
+{
+ struct aml_lcd_data_s *pdata = aml_lcd_get_data();
+ struct aml_bl_drv_s *bdrv;
+ int load_id_bl;
+ int i, ret;
+
+ if (!pdata) {
+ BLERR("%s: pdata is NULL\n", __func__);
+ return -1;
+ }
+
+ aml_bl_pwm_reg_config_init(pdata);
+
+ load_id_bl = load_id;
+ for (i = 0; i < LCD_MAX_DRV; i++) {
+ if (bl_index_lut[i] >= BL_INDEX_INVALID)
+ continue;
+
+ if (!bl_driver[i]) {
+ bl_driver[i] = (struct aml_bl_drv_s *)
+ malloc(sizeof(struct aml_bl_drv_s));
+ if (!bl_driver[i]) {
+ BLERR("%s: Not enough memory\n", __func__);
+ return -1;
+ }
+ }
+ bdrv = bl_driver[i];
+ memset(bdrv, 0, sizeof(struct aml_bl_drv_s));
+ bdrv->index = i;
+ bdrv->data = pdata;
+
+ /* default config */
+ bdrv->config.index = bl_index_lut[i];
+ bdrv->config.method = BL_CTRL_MAX;
+ bdrv->config.en_gpio = 0xff;
+ bdrv->config.extern_index = 0xff;
+ bdrv->factory_bl_on_delay = -1;
+
+ if (load_id_bl & 0x1) {
+ ret = lcd_bl_init_load_from_dts(dtaddr, bdrv);
+ if (ret) {
+ load_id_bl = 0x0;
+ ret = lcd_bl_init_load_from_bsp(bdrv);
+ if (ret) {
+ free(bl_driver[i]);
+ bl_driver[i] = NULL;
+ return -1;
+ }
+ }
+ } else {
+ ret = lcd_bl_init_load_from_bsp(bdrv);
+ if (ret) {
+ free(bl_driver[i]);
+ bl_driver[i] = NULL;
+ return -1;
+ }
+ }
+ if (bdrv->key_valid)
+ load_id_bl |= 0x10;
+
+ /* load bl config */
+ bl_config_load(dtaddr, load_id_bl, bdrv);
+ bl_power_init_off(bdrv);
+ }
+
+ return 0;
+}
+
+int aml_bl_remove(void)
+{
+ int i = 0;
+
+ for (i = 0; i < LCD_MAX_DRV; i++) {
+ if (bl_driver[i])
+ free(bl_driver[i]);
+ bl_driver[i] = NULL;
+ }
+
+ return 0;
+}
+
+int aml_bl_index_add(int drv_index, int conf_index)
+{
+ if (drv_index >= LCD_MAX_DRV) {
+ BLERR("%s: invalid drv_index: %d\n", __func__, drv_index);
+ return -1;
+ }
+
+ bl_index_lut[drv_index] = conf_index;
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL) {
+ BLPR("%s: drv_index %d, config index: %d\n",
+ __func__, drv_index, conf_index);
+ }
+ return 0;
+}
+
+int aml_bl_index_remove(int drv_index)
+{
+ if (drv_index >= LCD_MAX_DRV) {
+ BLERR("%s: invalid drv_index: %d\n", __func__, drv_index);
+ return -1;
+ }
+
+ bl_index_lut[drv_index] = BL_INDEX_INVALID;
+ if (lcd_debug_print_flag & LCD_DBG_PR_BL_NORMAL)
+ BLPR("%s: drv_index %d\n", __func__, drv_index);
+
+ return 0;
+}
+
+int aml_bl_init(void)
+{
+ int i;
+
+ for (i = 0; i < LCD_MAX_DRV; i++) {
+ if (bl_driver[i])
+ free(bl_driver[i]);
+ bl_driver[i] = NULL;
+ bl_index_lut[i] = BL_INDEX_INVALID;
+ }
+
+ return 0;
+}
+
+void aml_bl_driver_enable(int index)
+{
+ struct aml_bl_drv_s *bdrv;
+
+ bdrv = aml_bl_get_driver(index);
+ if (!bdrv)
+ return;
+
+ bl_pwm_config_update(&bdrv->config);
+ bl_set_level(bdrv, bdrv->config.level_default);
+ bl_power_ctrl(bdrv, 1);
+}
+
+void aml_bl_driver_disable(int index)
+{
+ struct aml_bl_drv_s *bdrv;
+
+ bdrv = aml_bl_get_driver(index);
+ if (!bdrv)
+ return;
+
+ bl_power_ctrl(bdrv, 0);
+}
+
+void aml_bl_set_level(int index, unsigned int level)
+{
+ struct aml_bl_drv_s *bdrv;
+
+ bdrv = aml_bl_get_driver(index);
+ if (!bdrv)
+ return;
+
+ bl_set_level(bdrv, level);
+}
+
+unsigned int aml_bl_get_level(int index)
+{
+ struct aml_bl_drv_s *bdrv;
+
+ bdrv = aml_bl_get_driver(index);
+ if (!bdrv)
+ return 0;
+
+ return bdrv->level;
+}
+
+void aml_bl_config_print(int index)
+{
+ struct aml_bl_drv_s *bdrv;
+
+ bdrv = aml_bl_get_driver(index);
+ if (!bdrv)
+ return;
+
+ bl_config_print(bdrv);
+}
diff --git a/drivers/amlogic/media/vout/lcd/backlight/lcd_bl.h b/drivers/amlogic/media/vout/lcd/backlight/lcd_bl.h
new file mode 100644
index 0000000..9da4691
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/backlight/lcd_bl.h
@@ -0,0 +1,28 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _AML_LCD_BL_H
+#define _AML_LCD_BL_H
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+
+void bl_set_pwm_gpio_check(struct aml_bl_drv_s *bdrv, struct bl_pwm_config_s *bl_pwm);
+
+enum bl_pwm_port_e bl_pwm_str_to_num(const char *str);
+char *bl_pwm_num_to_str(unsigned int num);
+void bl_pwm_set_duty(struct bl_pwm_config_s *bl_pwm);
+void bl_pwm_set_level(struct aml_bl_drv_s *bdrv,
+ struct bl_pwm_config_s *bl_pwm, unsigned int level);
+void bl_pwm_en(struct bl_pwm_config_s *bl_pwm, int flag);
+void bl_pwm_config_init(struct bl_pwm_config_s *bl_pwm);
+void bl_pwm_reg_print(struct bl_pwm_config_s *bl_pwm);
+
+#ifdef CONFIG_AML_LOCAL_DIMMING
+int ldim_config_load_from_dts(char *dt_addr, int child_offset);
+int ldim_config_load_from_unifykey(unsigned char *para);
+int ldim_config_load(char *dt_addr);
+#endif
+
+#endif
+
diff --git a/drivers/amlogic/media/vout/lcd/bl_extern/Kconfig b/drivers/amlogic/media/vout/lcd/bl_extern/Kconfig
deleted file mode 100644
index f5dc86d..0000000
--- a/drivers/amlogic/media/vout/lcd/bl_extern/Kconfig
+++ /dev/null
@@ -1,15 +0,0 @@
-config AML_BL_EXTERN
- bool "bl_extern driver for lcd"
- help
- Support for lcd bl_extern controlling
-
-config AML_BL_EXTERN_I2C_LP8556
- bool "bl_extern LP8556 driver for lcd"
- help
- Support for lcd bl_extern LP8556 controlling
-
-config AML_BL_EXTERN_MIPI_IT070ME05
- bool "bl_extern MIPI_IT070ME05 driver for lcd"
- help
- Support for lcd bl_extern MIPI_IT070ME05 controlling
-
diff --git a/drivers/amlogic/media/vout/lcd/bl_extern/Makefile b/drivers/amlogic/media/vout/lcd/bl_extern/Makefile
deleted file mode 100644
index 3bc7c6b..0000000
--- a/drivers/amlogic/media/vout/lcd/bl_extern/Makefile
+++ /dev/null
@@ -1,5 +0,0 @@
-
-obj-$(CONFIG_AML_BL_EXTERN) += bl_extern.o bl_extern_i2c_dev.o
-obj-$(CONFIG_AML_BL_EXTERN_I2C_LP8556) += i2c_lp8556.o
-obj-$(CONFIG_AML_BL_EXTERN_MIPI_IT070ME05) += mipi_lt070me05.o
-
diff --git a/drivers/amlogic/media/vout/lcd/bl_extern/bl_extern.c b/drivers/amlogic/media/vout/lcd/bl_extern/bl_extern.c
deleted file mode 100644
index 2d5332e..0000000
--- a/drivers/amlogic/media/vout/lcd/bl_extern/bl_extern.c
+++ /dev/null
@@ -1,628 +0,0 @@
-/*
- * drivers/amlogic/media/vout/lcd/bl_extern/bl_extern.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/arch/gpio.h>
-#include <fdtdec.h>
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#include <amlogic/media/vout/lcd/bl_extern.h>
-#include "bl_extern.h"
-#include "../lcd_common.h"
-
-static unsigned int bl_extern_status;
-static unsigned int bl_extern_level;
-
-static struct aml_bl_extern_driver_s bl_extern_driver;
-
-static int bl_extern_set_level(unsigned int level)
-{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- struct aml_bl_extern_driver_s *bl_extern = aml_bl_extern_get_driver();
- unsigned int level_max, level_min;
- unsigned int dim_max, dim_min;
-
- if (lcd_drv == NULL)
- return -1;
-
- bl_extern_level = level;
- if (bl_extern_status == 0)
- return 0;
-
- level_max = lcd_drv->bl_config->level_max;
- level_min = lcd_drv->bl_config->level_min;
- dim_max = bl_extern->config->dim_max;
- dim_min = bl_extern->config->dim_min;
- level = dim_min - ((level - level_min) * (dim_min - dim_max)) /
- (level_max - level_min);
-
- if (bl_extern_driver.device_bri_update)
- bl_extern_driver.device_bri_update(level);
-
- return 0;
-}
-
-static int bl_extern_power_on(void)
-{
- int ret = 0;
-
- BLEXT("%s\n", __func__);
-
- if (bl_extern_driver.device_power_on) {
- bl_extern_driver.device_power_on();
- bl_extern_status = 1;
- }
-
- /* restore bl level */
- if (bl_extern_level > 0)
- bl_extern_set_level(bl_extern_level);
-
- return ret;
-}
-static int bl_extern_power_off(void)
-{
- int ret = 0;
-
- BLEXT("%s\n", __func__);
-
- bl_extern_status = 0;
- if (bl_extern_driver.device_power_off)
- bl_extern_driver.device_power_off();
-
- return ret;
-}
-
-static struct aml_bl_extern_driver_s bl_extern_driver = {
- .power_on = bl_extern_power_on,
- .power_off = bl_extern_power_off,
- .set_level = bl_extern_set_level,
- .config_print = NULL,
- .device_power_on = NULL,
- .device_power_off = NULL,
- .device_bri_update = NULL,
- .config = NULL,
-};
-
-struct aml_bl_extern_driver_s *aml_bl_extern_get_driver(void)
-{
- return &bl_extern_driver;
-}
-
-static void bl_extern_init_table_dynamic_size_print(
- struct bl_extern_config_s *econf, int flag)
-{
- int i, j, max_len;
- unsigned char cmd_size;
- unsigned char *table;
-
- if (flag) {
- printf("power on:\n");
- table = econf->init_on;
- max_len = econf->init_on_cnt;
- } else {
- printf("power off:\n");
- table = econf->init_off;
- max_len = econf->init_off_cnt;
- }
- if (table == NULL) {
- BLEXTERR("init_table %d is NULL\n", flag);
- return;
- }
-
- i = 0;
- while ((i + 1) < max_len) {
- if (table[i] == LCD_EXT_CMD_TYPE_END) {
- printf(" 0x%02x,%d,\n", table[i], table[i+1]);
- break;
- }
- cmd_size = table[i+1];
- printf(" 0x%02x,%d,", table[i], cmd_size);
- if (cmd_size == 0)
- goto init_table_dynamic_print_next;
- if (i + 2 + cmd_size > max_len) {
- printf("cmd_size out of support\n");
- break;
- }
-
- if (table[i] == LCD_EXT_CMD_TYPE_DELAY) {
- for (j = 0; j < cmd_size; j++)
- printf("%d,", table[i+2+j]);
- } else if (table[i] == LCD_EXT_CMD_TYPE_CMD) {
- for (j = 0; j < cmd_size; j++)
- printf("0x%02x,", table[i+2+j]);
- } else if (table[i] == LCD_EXT_CMD_TYPE_CMD_DELAY) {
- for (j = 0; j < (cmd_size - 1); j++)
- printf("0x%02x,", table[i+2+j]);
- printf("%d,", table[i+cmd_size+1]);
- } else {
- for (j = 0; j < cmd_size; j++)
- printf("0x%02x,", table[i+2+j]);
- }
-init_table_dynamic_print_next:
- printf("\n");
- i += (cmd_size + 2);
- }
-}
-
-static void bl_extern_init_table_fixed_size_print(
- struct bl_extern_config_s *econf, int flag)
-{
- int i, j, max_len;
- unsigned char cmd_size;
- unsigned char *table;
-
- cmd_size = econf->cmd_size;
- if (flag) {
- printf("power on:\n");
- table = econf->init_on;
- max_len = econf->init_on_cnt;
- } else {
- printf("power off:\n");
- table = econf->init_off;
- max_len = econf->init_off_cnt;
- }
- if (table == NULL) {
- BLEXTERR("init_table %d is NULL\n", flag);
- return;
- }
-
- i = 0;
- while ((i + cmd_size) <= max_len) {
- printf(" ");
- for (j = 0; j < cmd_size; j++)
- printf("0x%02x,", table[i+j]);
- printf("\n");
-
- if (table[i] == LCD_EXT_CMD_TYPE_END)
- break;
- i += cmd_size;
- }
-}
-
-static void bl_extern_config_print(void)
-{
- struct aml_bl_extern_driver_s *bl_extern = aml_bl_extern_get_driver();
-
- BLEXT("%s:\n", __func__);
- printf("index: %d\n"
- "name: %s\n"
- "dim_min: %d\n"
- "dim_max: %d\n",
- bl_extern->config->index,
- bl_extern->config->name,
- bl_extern->config->dim_min,
- bl_extern->config->dim_max);
- switch (bl_extern->config->type) {
- case BL_EXTERN_I2C:
- printf("type: i2c(%d)\n"
- "i2c_addr: 0x%02x\n"
- "i2c_bus: %d\n",
- bl_extern->config->type,
- bl_extern->config->i2c_addr,
- bl_extern->config->i2c_bus);
- if (bl_extern->config->cmd_size == 0)
- break;
- printf("init_loaded = %d\n"
- "cmd_size = %d\n"
- "init_on_cnt = %d\n"
- "init_off_cnt = %d\n",
- bl_extern->config->init_loaded,
- bl_extern->config->cmd_size,
- bl_extern->config->init_on_cnt,
- bl_extern->config->init_off_cnt);
- if (bl_extern->config->cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC) {
- bl_extern_init_table_dynamic_size_print(bl_extern->config, 1);
- bl_extern_init_table_dynamic_size_print(bl_extern->config, 0);
- } else {
- bl_extern_init_table_fixed_size_print(bl_extern->config, 1);
- bl_extern_init_table_fixed_size_print(bl_extern->config, 0);
- }
- break;
- case BL_EXTERN_SPI:
- printf("type: spi(%d)\n",
- bl_extern->config->type);
- if (bl_extern->config->cmd_size == 0)
- break;
- printf("init_loaded = %d\n"
- "cmd_size = %d\n"
- "init_on_cnt = %d\n"
- "init_off_cnt = %d\n",
- bl_extern->config->init_loaded,
- bl_extern->config->cmd_size,
- bl_extern->config->init_on_cnt,
- bl_extern->config->init_off_cnt);
- if (bl_extern->config->cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC) {
- bl_extern_init_table_dynamic_size_print(bl_extern->config, 1);
- bl_extern_init_table_dynamic_size_print(bl_extern->config, 0);
- } else {
- bl_extern_init_table_fixed_size_print(bl_extern->config, 1);
- bl_extern_init_table_fixed_size_print(bl_extern->config, 0);
- }
- break;
- case BL_EXTERN_MIPI:
- printf("type: mipi(%d)\n",
- bl_extern->config->type);
- break;
- default:
- break;
- }
-}
-
-static unsigned char bl_extern_get_i2c_bus_str(const char *str)
-{
- unsigned char i2c_bus;
-
- if (strncmp(str, "i2c_bus_ao", 10) == 0)
- i2c_bus = BL_EXTERN_I2C_BUS_4;
- else if (strncmp(str, "i2c_bus_a", 9) == 0)
- i2c_bus = BL_EXTERN_I2C_BUS_0;
- else if (strncmp(str, "i2c_bus_b", 9) == 0)
- i2c_bus = BL_EXTERN_I2C_BUS_1;
- else if (strncmp(str, "i2c_bus_c", 9) == 0)
- i2c_bus = BL_EXTERN_I2C_BUS_2;
- else if (strncmp(str, "i2c_bus_d", 9) == 0)
- i2c_bus = BL_EXTERN_I2C_BUS_3;
- else if (strncmp(str, "i2c_bus_0", 9) == 0)
- i2c_bus = BL_EXTERN_I2C_BUS_0;
- else if (strncmp(str, "i2c_bus_1", 9) == 0)
- i2c_bus = BL_EXTERN_I2C_BUS_1;
- else if (strncmp(str, "i2c_bus_2", 9) == 0)
- i2c_bus = BL_EXTERN_I2C_BUS_2;
- else if (strncmp(str, "i2c_bus_3", 9) == 0)
- i2c_bus = BL_EXTERN_I2C_BUS_3;
- else if (strncmp(str, "i2c_bus_4", 9) == 0)
- i2c_bus = BL_EXTERN_I2C_BUS_4;
- else {
- i2c_bus = BL_EXTERN_I2C_BUS_MAX;
- BLEXTERR("invalid i2c_bus: %s\n", str);
- }
-
- return i2c_bus;
-}
-
-static int bl_extern_init_table_dynamic_size_load_dts(const void *dt_blob,
- int nodeoffset, struct bl_extern_config_s *extconf, int flag)
-{
- unsigned char cmd_size, type;
- int i = 0, j, max_len;
- unsigned char *table;
- char propname[20];
- char *propdata;
-
- if (flag) {
- table = extconf->init_on;
- max_len = BL_EXTERN_INIT_ON_MAX;
- sprintf(propname, "init_on");
- } else {
- table = extconf->init_off;
- max_len = BL_EXTERN_INIT_OFF_MAX;
- sprintf(propname, "init_off");
- }
- if (table == NULL) {
- BLEXT("%s init_table is null\n", propname);
- return 0;
- }
-
- propdata = (char *)fdt_getprop(dt_blob, nodeoffset, propname, NULL);
- if (propdata == NULL) {
- BLEXTERR("%s: get %s failed\n", extconf->name, propname);
- table[0] = LCD_EXT_CMD_TYPE_END;
- table[1] = 0;
- return -1;
- }
-
- while ((i + 1) < max_len) {
- table[i] = (unsigned char)(be32_to_cpup((((u32*)propdata)+i)));
- table[i+1] = (unsigned char)(be32_to_cpup((((u32*)propdata)+i+1)));
- type = table[i];
- cmd_size = table[i+1];
- if (type == LCD_EXT_CMD_TYPE_END)
- break;
- if (cmd_size == 0)
- goto init_table_dynamic_dts_next;
- if ((i + 2 + cmd_size) > max_len) {
- BLEXTERR("%s: %s cmd_size out of support\n", extconf->name, propname);
- table[i] = LCD_EXT_CMD_TYPE_END;
- table[i+1] = 0;
- return -1;
- }
- for (j = 0; j < cmd_size; j++)
- table[i+2+j] = (unsigned char)(be32_to_cpup((((u32*)propdata)+i+2+j)));
-
-init_table_dynamic_dts_next:
- i += (cmd_size + 2);
- }
- if (flag)
- extconf->init_on_cnt = i + 2;
- else
- extconf->init_off_cnt = i + 2;
-
- return 0;
-}
-
-static int bl_extern_init_table_fixed_size_load_dts(const void *dt_blob,
- int nodeoffset, struct bl_extern_config_s *extconf, int flag)
-{
- unsigned char cmd_size;
- int i = 0, j, max_len;
- unsigned char *table;
- char propname[20];
- char *propdata;
-
- cmd_size = extconf->cmd_size;
- if (flag) {
- table = extconf->init_on;
- max_len = BL_EXTERN_INIT_ON_MAX;
- sprintf(propname, "init_on");
- } else {
- table = extconf->init_off;
- max_len = BL_EXTERN_INIT_OFF_MAX;
- sprintf(propname, "init_off");
- }
- if (table == NULL) {
- BLEXT("%s init_table is null\n", propname);
- return 0;
- }
-
- propdata = (char *)fdt_getprop(dt_blob, nodeoffset, propname, NULL);
- if (propdata == NULL) {
- BLEXTERR("%s: get %s failed\n", extconf->name, propname);
- table[0] = LCD_EXT_CMD_TYPE_END;
- table[1] = 0;
- return -1;
- }
-
- while (i < max_len) {
- if ((i + cmd_size) > max_len) {
- BLEXTERR("%s: %s cmd_size out of support\n", extconf->name, propname);
- table[i] = LCD_EXT_CMD_TYPE_END;
- return -1;
- }
- for (j = 0; j < cmd_size; j++)
- table[i+j] = (unsigned char)(be32_to_cpup((((u32*)propdata)+i+j)));
-
- if (table[i] == LCD_EXT_CMD_TYPE_END)
- break;
-
- i += cmd_size;
- }
- if (flag)
- extconf->init_on_cnt = i + cmd_size;
- else
- extconf->init_off_cnt = i + cmd_size;
-
- return 0;
-}
-
-static int bl_extern_config_from_dts(const void *dt_blob, int index)
-{
- int ret = 0;
- int parent_offset, child_offset;
- char propname[30];
- char *propdata;
- struct aml_bl_extern_driver_s *bl_extern = aml_bl_extern_get_driver();
- unsigned char bl_ext_i2c_bus = BL_EXTERN_I2C_BUS_MAX;
-
- parent_offset = fdt_path_offset(dt_blob, "/bl_extern");
- if (parent_offset < 0) {
- BLEXTERR("bl: not find /backlight node %s\n", fdt_strerror(parent_offset));
- return -1;
- }
- propdata = (char *)fdt_getprop(dt_blob, parent_offset, "status", NULL);
- if (propdata == NULL) {
- BLEXTERR("bl: not find status, default to disabled\n");
- return -1;
- } else {
- if (strncmp(propdata, "okay", 2)) {
- BLEXT("bl: status disabled\n");
- return -1;
- }
- }
-
- propdata = (char *)fdt_getprop(dt_blob, parent_offset, "i2c_bus", NULL);
- if (propdata == NULL)
- bl_ext_i2c_bus = BL_EXTERN_I2C_BUS_MAX;
- else
- bl_ext_i2c_bus = bl_extern_get_i2c_bus_str(propdata);
-
- sprintf(propname,"/bl_extern/extern_%d", index);
- child_offset = fdt_path_offset(dt_blob, propname);
- if (child_offset < 0) {
- BLEXTERR("bl: not find %s node: %s\n", propname, fdt_strerror(child_offset));
- return -1;
- }
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "index", NULL);
- if (propdata == NULL) {
- BLEXTERR("get index failed, exit\n");
- return -1;
- } else {
- if (be32_to_cpup((u32*)propdata) != index) {
- BLEXTERR("index not match, exit\n");
- return -1;
- } else {
- bl_extern->config->index = be32_to_cpup((u32*)propdata);
- }
- }
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "extern_name", NULL);
- if (propdata == NULL) {
- BLEXTERR("failed to get extern_name\n");
- sprintf(bl_extern->config->name, "extern_%d", index);
- } else {
- strcpy(bl_extern->config->name, propdata);
- }
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "type", NULL);
- if (propdata == NULL) {
- bl_extern->config->type = BL_EXTERN_MAX;
- BLEXTERR("get type failed, exit\n");
- return -1;
- } else {
- bl_extern->config->type = be32_to_cpup((u32*)propdata);
- }
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "dim_max_min", NULL);
- if (propdata == NULL) {
- BLEXTERR("failed to get bl_level_attr\n");
- } else {
- bl_extern->config->dim_max = be32_to_cpup((u32*)propdata);
- bl_extern->config->dim_min = be32_to_cpup((((u32*)propdata)+1));
- }
-
- switch (bl_extern->config->type) {
- case BL_EXTERN_I2C:
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "i2c_address", NULL);
- if (propdata == NULL) {
- BLEXTERR("get %s i2c_address failed, exit\n", bl_extern->config->name);
- bl_extern->config->i2c_addr = 0xff;
- return -1;
- } else {
- bl_extern->config->i2c_addr = (unsigned char)(be32_to_cpup((u32*)propdata));
- }
- if (bl_ext_i2c_bus == BL_EXTERN_I2C_BUS_MAX) { /* compatible for kernel3.14 */
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "i2c_bus", NULL);
- if (propdata == NULL) {
- BLEXTERR("get %s i2c_bus failed, exit\n", bl_extern->config->name);
- bl_extern->config->i2c_bus = BL_EXTERN_I2C_BUS_MAX;
- return -1;
- } else {
- bl_extern->config->i2c_bus = bl_extern_get_i2c_bus_str(propdata);
- }
- } else {
- bl_extern->config->i2c_bus = bl_ext_i2c_bus;
- }
- if (lcd_debug_print_flag)
- bl_extern_i2c_bus_print(bl_extern->config->i2c_bus);
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "cmd_size", NULL);
- if (propdata == NULL) {
- BLEXT("%s: no cmd_size\n", bl_extern->config->name);
- bl_extern->config->cmd_size = 0;
- } else {
- bl_extern->config->cmd_size = (unsigned char)(be32_to_cpup((u32*)propdata));
- }
- if (lcd_debug_print_flag)
- BLEXT("%s: cmd_size=%d\n", bl_extern->config->name, bl_extern->config->cmd_size);
- if (bl_extern->config->cmd_size == 0)
- break;
-
- if (bl_extern->config->cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC) {
- ret = bl_extern_init_table_dynamic_size_load_dts(
- dt_blob, child_offset, bl_extern->config, 1);
- if (ret)
- break;
- ret = bl_extern_init_table_dynamic_size_load_dts(
- dt_blob, child_offset, bl_extern->config, 0);
- } else {
- ret = bl_extern_init_table_fixed_size_load_dts(
- dt_blob, child_offset, bl_extern->config, 1);
- if (ret)
- break;
- ret = bl_extern_init_table_fixed_size_load_dts(
- dt_blob, child_offset, bl_extern->config, 0);
- }
- if (ret == 0)
- bl_extern->config->init_loaded = 1;
- break;
- case BL_EXTERN_SPI:
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "cmd_size", NULL);
- if (propdata == NULL) {
- BLEXT("%s: no cmd_size\n", bl_extern->config->name);
- bl_extern->config->cmd_size = 0;
- } else {
- bl_extern->config->cmd_size = (unsigned char)(be32_to_cpup((u32*)propdata));
- }
- if (lcd_debug_print_flag)
- BLEXT("%s: cmd_size=%d\n", bl_extern->config->name, bl_extern->config->cmd_size);
- if (bl_extern->config->cmd_size == 0)
- break;
-
- if (bl_extern->config->cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC) {
- ret = bl_extern_init_table_dynamic_size_load_dts(
- dt_blob, child_offset, bl_extern->config, 1);
- if (ret)
- break;
- ret = bl_extern_init_table_dynamic_size_load_dts(
- dt_blob, child_offset, bl_extern->config, 0);
- } else {
- ret = bl_extern_init_table_fixed_size_load_dts(
- dt_blob, child_offset, bl_extern->config, 1);
- if (ret)
- break;
- ret = bl_extern_init_table_fixed_size_load_dts(
- dt_blob, child_offset, bl_extern->config, 0);
- }
- if (ret == 0)
- bl_extern->config->init_loaded = 1;
- break;
- case BL_EXTERN_MIPI:
- break;
- default:
- break;
- }
-
- return ret;
-}
-
-static int bl_extern_add_driver(void)
-{
- int ret = 0;
- struct bl_extern_config_s *extconf = bl_extern_driver.config;
-
- if (strcmp(extconf->name, "i2c_lp8556") == 0) {
-#ifdef CONFIG_AML_BL_EXTERN_I2C_LP8556
- ret = i2c_lp8556_probe();
-#endif
- } else if (strcmp(extconf->name, "mipi_lt070me05") == 0) {
-#ifdef CONFIG_AML_BL_EXTERN_MIPI_IT070ME05
- ret = mipi_lt070me05_probe();
-#endif
- } else {
- BLEXTERR("invalid device name: %s\n", extconf->name);
- ret = -1;
- }
-
- if (ret) {
- BLEXTERR("add device driver failed %s(%d)\n",
- extconf->name, extconf->index);
- } else {
- BLEXT("add device driver %s(%d)\n",
- extconf->name, extconf->index);
- }
-
- return ret;
-}
-
-int aml_bl_extern_device_load(const void *dt_blob, int index)
-{
- int ret = 0;
-
- bl_extern_status = 0;
- bl_extern_level = 0;
- bl_extern_driver.config = &bl_extern_config_dtf;
- if (dt_blob) {
- if (lcd_debug_print_flag)
- BLEXT("load bl_extern_config from dts\n");
- bl_extern_config_from_dts(dt_blob, index);
- }
- bl_extern_add_driver();
- bl_extern_driver.config_print = bl_extern_config_print;
- BLEXT("%s OK\n", __func__);
-
- return ret;
-}
-
diff --git a/drivers/amlogic/media/vout/lcd/bl_extern/bl_extern.h b/drivers/amlogic/media/vout/lcd/bl_extern/bl_extern.h
deleted file mode 100644
index 289c701..0000000
--- a/drivers/amlogic/media/vout/lcd/bl_extern/bl_extern.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * drivers/amlogic/media/vout/lcd/bl_extern/bl_extern.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#ifndef _BL_EXTERN_H_
-#define _BL_EXTERN_H_
-#include <amlogic/media/vout/lcd/bl_extern.h>
-
-#define BLEXT(fmt, args...) printf("bl extern: "fmt"", ## args)
-#define BLEXTERR(fmt, args...) printf("bl extern: error: "fmt"", ## args)
-#define BL_EXTERN_DRIVER "bl_extern"
-
-extern void bl_extern_i2c_bus_print(unsigned char i2c_bus);
-extern int bl_extern_i2c_write(unsigned char i2c_bus, unsigned i2c_addr,
- unsigned char *buff, unsigned len);
-extern int bl_extern_i2c_read(unsigned char i2c_bus, unsigned i2c_addr,
- unsigned char *buff, unsigned int len);
-
-#ifdef CONFIG_AML_BL_EXTERN_I2C_LP8556
-extern int i2c_lp8556_probe(void);
-#endif
-
-#ifdef CONFIG_AML_BL_EXTERN_MIPI_IT070ME05
-extern int mipi_lt070me05_probe(void);
-#endif
-
-
-#endif
-
diff --git a/drivers/amlogic/media/vout/lcd/bl_extern/bl_extern_i2c_dev.c b/drivers/amlogic/media/vout/lcd/bl_extern/bl_extern_i2c_dev.c
deleted file mode 100644
index 73a70bc..0000000
--- a/drivers/amlogic/media/vout/lcd/bl_extern/bl_extern_i2c_dev.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * drivers/amlogic/media/vout/lcd/bl_extern/bl_extern_i2c_dev.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/arch/gpio.h>
-#include <fdtdec.h>
-#include <i2c.h>
-#include <dm.h>
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#include <amlogic/media/vout/lcd/bl_extern.h>
-#include "bl_extern.h"
-#include "../lcd_common.h"
-
-struct aml_bl_extern_i2c_match_s {
- unsigned char bus_id;
- unsigned char bus_sys;
- char *bus_str;
-};
-
-static struct aml_bl_extern_i2c_match_s bl_extern_i2c_match_table[] = {
- {BL_EXTERN_I2C_BUS_0, LCD_EXT_I2C_BUS_0, "i2c_0/a"},
- {BL_EXTERN_I2C_BUS_1, LCD_EXT_I2C_BUS_1, "i2c_1/b"},
- {BL_EXTERN_I2C_BUS_2, LCD_EXT_I2C_BUS_2, "i2c_2/c"},
- {BL_EXTERN_I2C_BUS_3, LCD_EXT_I2C_BUS_3, "i2c_3/d"},
- {BL_EXTERN_I2C_BUS_4, LCD_EXT_I2C_BUS_4, "i2c_4/ao"},
- {BL_EXTERN_I2C_BUS_MAX, LCD_EXT_I2C_BUS_MAX, "i2c_invalid"},
-};
-
-void bl_extern_i2c_bus_print(unsigned char i2c_bus)
-{
- int i, temp = ARRAY_SIZE(bl_extern_i2c_match_table) - 1;
-
- for (i = 0; i < ARRAY_SIZE(bl_extern_i2c_match_table); i++) {
- if (bl_extern_i2c_match_table[i].bus_id == i2c_bus) {
- temp = i;
- break;
- }
- }
-
- BLEXT("i2c_bus = %s(%d)\n",
- bl_extern_i2c_match_table[temp].bus_str, temp);
-}
-
-static unsigned char bl_extern_i2c_bus_get_sys(unsigned char i2c_bus)
-{
- int i, ret = LCD_EXT_I2C_BUS_MAX;
-
- for (i = 0; i < ARRAY_SIZE(bl_extern_i2c_match_table); i++) {
- if (bl_extern_i2c_match_table[i].bus_id == i2c_bus) {
- ret = bl_extern_i2c_match_table[i].bus_sys;
- break;
- }
- }
-
- if (lcd_debug_print_flag)
- BLEXT("%s: %d->%d\n", __func__, i2c_bus, ret);
- return ret;
-}
-
-int bl_extern_i2c_write(unsigned char i2c_bus, unsigned i2c_addr,
- unsigned char *buff, unsigned len)
-{
- unsigned char sys_i2c_bus;
- struct udevice *i2c_dev;
- int i, ret = 0;
-
- sys_i2c_bus = bl_extern_i2c_bus_get_sys(i2c_bus);
- ret = i2c_get_chip_for_busnum(sys_i2c_bus, i2c_addr, 1, &i2c_dev);
- if (ret) {
- BLEXTERR("no sys_i2c_bus %d find\n", sys_i2c_bus);
- return ret;
- }
-
- if (lcd_debug_print_flag) {
- printf("%s:", __func__);
- for (i = 0; i < len; i++)
- printf(" 0x%02x", buff[i]);
- printf(" [addr 0x%02x]\n", i2c_addr);
- }
-
- ret = dm_i2c_write(i2c_dev, i2c_addr, buff, len);
- if (ret) {
- BLEXTERR("i2c write failed [addr 0x%02x]\n", i2c_addr);
- return ret;
- }
-
- return 0;
-}
-
-int bl_extern_i2c_read(unsigned char i2c_bus, unsigned i2c_addr,
- unsigned char *buff, unsigned int len)
-{
- unsigned char sys_i2c_bus;
- struct udevice *i2c_dev;
- int ret = 0;
-
- sys_i2c_bus = bl_extern_i2c_bus_get_sys(i2c_bus);
- ret = i2c_get_chip_for_busnum(sys_i2c_bus, i2c_addr, 1, &i2c_dev);
- if (ret) {
- BLEXTERR("no sys_i2c_bus %d find\n", sys_i2c_bus);
- return ret;
- }
-
- ret = dm_i2c_write(i2c_dev, i2c_addr, buff, 1);
- if (ret) {
- BLEXTERR("i2c write failed [addr 0x%02x]\n", i2c_addr);
- return ret;
- }
- ret = dm_i2c_read(i2c_dev, i2c_addr, buff, len);
- if (ret) {
- BLEXTERR("i2c read failed [addr 0x%02x]\n", i2c_addr);
- return ret;
- }
-
- return 0;
-}
diff --git a/drivers/amlogic/media/vout/lcd/bl_extern/i2c_lp8556.c b/drivers/amlogic/media/vout/lcd/bl_extern/i2c_lp8556.c
deleted file mode 100644
index b6f4ba7..0000000
--- a/drivers/amlogic/media/vout/lcd/bl_extern/i2c_lp8556.c
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * drivers/amlogic/media/vout/lcd/bl_extern/i2c_lp8556.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/arch/gpio.h>
-#include <fdtdec.h>
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#include <amlogic/media/vout/lcd/bl_extern.h>
-#include "bl_extern.h"
-#include "../lcd_common.h"
-#include "../lcd_reg.h"
-
-#define BL_EXTERN_NAME "i2c_lp8556"
-#define BL_EXTERN_TYPE BL_EXTERN_I2C
-#define BL_EXTERN_I2C_ADDR (0x58 >> 1) //7bit address
-
-//#define BL_EXT_I2C_PORT_INIT /* no need init i2c port default */
-
-#define BL_EXTERN_CMD_SIZE LCD_EXT_CMD_SIZE_DYNAMIC
-static unsigned char init_on_table[] = {
- 0xc0, 2, 0xa2, 0x20,
- 0xc0, 2, 0xa5, 0x54,
- 0xc0, 2, 0x00, 0xff,
- 0xc0, 2, 0x01, 0x05,
- 0xc0, 2, 0xa2, 0x20,
- 0xc0, 2, 0xa5, 0x54,
- 0xc0, 2, 0xa1, 0xb7,
- 0xc0, 2, 0xa0, 0xff,
- 0xc0, 2, 0x00, 0x80,
- 0xff, 0, /*ending*/
-};
-
-static unsigned char init_off_table[] = {
- 0xff, 0, /*ending*/
-};
-
-static int bl_extern_power_cmd_dynamic_size(unsigned char *table, int flag)
-{
- int i = 0, j = 0, max_len = 0, step = 0;
- unsigned char type, cmd_size;
- int delay_ms, ret = 0;
-
- if (flag)
- max_len = ext_config->init_on_cnt;
- else
- max_len = ext_config->init_off_cnt;
-
- while ((i + 1) < max_len) {
- type = table[i];
- if (type == LCD_EXT_CMD_TYPE_END)
- break;
- if (lcd_debug_print_flag) {
- EXTPR("%s: step %d: type=0x%02x, cmd_size=%d\n",
- __func__, step, type, table[i+1]);
- }
- cmd_size = table[i+1];
- if (cmd_size == 0)
- goto power_cmd_dynamic_next;
- if ((i + 2 + cmd_size) > max_len)
- break;
-
- if (type == LCD_EXT_CMD_TYPE_NONE) {
- /* do nothing */
- } else if (type == LCD_EXT_CMD_TYPE_DELAY) {
- delay_ms = 0;
- for (j = 0; j < cmd_size; j++)
- delay_ms += table[i+2+j];
- if (delay_ms > 0)
- mdelay(delay_ms);
- } else if (type == LCD_EXT_CMD_TYPE_CMD) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
- ext_config->i2c_addr, &table[i+2], cmd_size);
- } else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
- ext_config->i2c_addr, &table[i+2], (cmd_size-1));
- if (table[i+1+cmd_size] > 0)
- mdelay(table[i+1+cmd_size]);
- } else {
- EXTERR("%s: %s(%d): type 0x%02x invalid\n",
- __func__, ext_config->name, ext_config->index, type);
- }
-power_cmd_dynamic_next:
- i += (cmd_size + 2);
- step++;
- }
-
- return ret;
-}
-
-static int bl_extern_power_cmd_fixed_size(unsigned char *table, int flag)
-{
- int i = 0, j, max_len, step = 0;
- unsigned char type, cmd_size;
- int delay_ms, ret = 0;
-
- cmd_size = ext_config->cmd_size;
- if (cmd_size < 2) {
- EXTERR("%s: invalid cmd_size %d\n", __func__, cmd_size);
- return -1;
- }
-
- if (flag)
- max_len = ext_config->init_on_cnt;
- else
- max_len = ext_config->init_off_cnt;
-
- while ((i + cmd_size) <= max_len) {
- type = table[i];
- if (type == LCD_EXT_CMD_TYPE_END)
- break;
- if (lcd_debug_print_flag) {
- EXTPR("%s: step %d: type=0x%02x, cmd_size=%d\n",
- __func__, step, type, cmd_size);
- }
- if (type == LCD_EXT_CMD_TYPE_NONE) {
- /* do nothing */
- } else if (type == LCD_EXT_CMD_TYPE_DELAY) {
- delay_ms = 0;
- for (j = 0; j < (cmd_size - 1); j++)
- delay_ms += table[i+1+j];
- if (delay_ms > 0)
- mdelay(delay_ms);
- } else if (type == LCD_EXT_CMD_TYPE_CMD) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
- ext_config->i2c_addr,
- &table[i+1], (cmd_size-1));
- } else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
- ext_config->i2c_addr,
- &table[i+1], (cmd_size-2));
- if (table[i+cmd_size-1] > 0)
- mdelay(table[i+cmd_size-1]);
- } else {
- EXTERR("%s: %s(%d): type 0x%02x is invalid\n",
- __func__, ext_config->name, ext_config->index, type);
- }
- i += cmd_size;
- step++;
- }
-
- return ret;
-}
-
-static int i2c_lp8556_power_ctrl(int flag)
-{
- struct aml_bl_extern_driver_s *bl_extern = aml_bl_extern_get_driver();
- unsigned char *table;
- unsigned char cmd_size;
- int ret = 0;
-
- /* step 1: power prepare */
-#ifdef BL_EXT_I2C_PORT_INIT
- aml_bl_extern_i2c_bus_change(bl_extern->config->i2c_bus);
-#endif
-
- /* step 2: power cmd */
- cmd_size = ext_config->cmd_size;
- if (flag)
- table = ext_config->init_on;
- else
- table = ext_config->init_off;
- if (cmd_size < 1) {
- BLEXTERR("%s: cmd_size %d is invalid\n", __func__, cmd_size);
- ret = -1;
- goto power_ctrl_next;
- }
- if (table == NULL) {
- BLEXTERR("%s: init_table %d is NULL\n", __func__, flag);
- ret = -1;
- goto power_ctrl_next;
- }
- if (cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC)
- ret = bl_extern_power_cmd_dynamic_size(table, flag);
- else
- ret = bl_extern_power_cmd_fixed_size(table, flag);
-
-power_ctrl_next:
- /* step 3: power finish */
-#ifdef BL_EXT_I2C_PORT_INIT
- aml_bl_extern_i2c_bus_recovery();
-#endif
-
- BLEXT("%s: %s(%d): %d\n", __func__, bl_extern->config->name,
- bl_extern->config->index, flag);
- return ret;
-}
-
-static int i2c_lp8556_power_on(void)
-{
- int ret;
-
- ret = i2c_lp8556_power_ctrl(1);
-
- return ret;
-}
-
-static int i2c_lp8556_power_off(void)
-{
- return 0;
-}
-
-static int i2c_lp8556_set_level(unsigned int level)
-{
- struct aml_bl_extern_driver_s *bl_extern = aml_bl_extern_get_driver();
- unsigned char tData[3];
- int ret = 0;
-
- level &= 0xff;
-
- tData[0] = 0x0;
- tData[1] = level;
- ret = bl_extern_i2c_write(bl_extern->config->i2c_bus,
- bl_extern->config->i2c_addr, tData, 2);
-
- return ret;
-}
-
-static int i2c_lp8556_update(void)
-{
- struct aml_bl_extern_driver_s *bl_extern = aml_bl_extern_get_driver();
-
- if (bl_extern == NULL) {
- BLEXTERR("%s driver is null\n", BL_EXTERN_NAME);
- return -1;
- }
-
- bl_extern->device_power_on = i2c_lp8556_power_on;
- bl_extern->device_power_off = i2c_lp8556_power_off;
- bl_extern->device_bri_update = i2c_lp8556_set_level;
-
- bl_extern->config->cmd_size = BL_EXTERN_CMD_SIZE;
- bl_extern->config->init_on = init_on_table;
- bl_extern->config->init_on_cnt = sizeof(init_on_table);
- bl_extern->config->init_off = init_off_table;
- bl_extern->config->init_off_cnt = sizeof(init_off_table);
-
- return 0;
-}
-
-int i2c_lp8556_probe(void)
-{
- int ret = 0;
-
- ret = i2c_lp8556_update();
- if (lcd_debug_print_flag)
- BLEXT("%s: %d\n", __func__, ret);
-
- return ret;
-}
-
diff --git a/drivers/amlogic/media/vout/lcd/bl_extern/mipi_lt070me05.c b/drivers/amlogic/media/vout/lcd/bl_extern/mipi_lt070me05.c
deleted file mode 100644
index adcd32f..0000000
--- a/drivers/amlogic/media/vout/lcd/bl_extern/mipi_lt070me05.c
+++ /dev/null
@@ -1,89 +0,0 @@
-/*
- * drivers/amlogic/media/vout/lcd/lcd_extern/mipi_lt070me05.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/arch/gpio.h>
-#include <fdtdec.h>
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#include <amlogic/media/vout/lcd/bl_extern.h>
-#include "bl_extern.h"
-#include "../lcd_common.h"
-
-
-#define BL_EXTERN_NAME "mipi_lt070me05"
-#define BL_EXTERN_TYPE BL_EXTERN_MIPI
-
-static int mipi_lt070me05_power_on(void)
-{
- return 0;
-}
-
-static int mipi_lt070me05_power_off(void)
-{
- return 0;
-}
-
-/******************** mipi command ********************
- *format: data_type, num, data....
- *special: data_type=0xff, num<0xff means delay ms, num=0xff means ending.
- */
-static int mipi_lt070me05_set_level(unsigned int level)
-{
- unsigned char payload[] = {0x15, 2, 0x51, 0xe6, 0xff, 0xff};
-
- level &= 0xff;
-
- payload[3] = level;
-#ifdef CONFIG_AML_LCD_TABLET
- dsi_write_cmd(&payload[0]);
-#endif
-
- return 0;
-}
-
-static int mipi_lt070me05_update(void)
-{
- struct aml_bl_extern_driver_s *bl_extern = aml_bl_extern_get_driver();
-
- if (bl_extern == NULL) {
- BLEXTERR("%s driver is null\n", BL_EXTERN_NAME);
- return -1;
- }
-
- bl_extern->device_power_on = mipi_lt070me05_power_on;
- bl_extern->device_power_off = mipi_lt070me05_power_off;
- bl_extern->device_bri_update = mipi_lt070me05_set_level;
-
- return 0;
-}
-
-int mipi_lt070me05_probe(void)
-{
- int ret = 0;
-
- ret = mipi_lt070me05_update();
-
- BLEXT("%s: %d\n", __func__, ret);
-
- return ret;
-}
-
-
diff --git a/drivers/amlogic/media/vout/lcd/bl_ldim/Kconfig b/drivers/amlogic/media/vout/lcd/bl_ldim/Kconfig
deleted file mode 100644
index 377a3d0..0000000
--- a/drivers/amlogic/media/vout/lcd/bl_ldim/Kconfig
+++ /dev/null
@@ -1,21 +0,0 @@
-config AML_BL_LOCAL_DIMMING
- bool "bl_local_dimming driver for lcd"
- help
- Support for lcd bl_local_dimming controlling
-
-config AML_LOCAL_DIMMING_GLOBAL
- bool "bl ldim global dimming driver for lcd"
- help
- Support for lcd bl ldim global dimming controlling
-
-config AML_LOCAL_DIMMING_OB3350
- bool "bl ldim OB3350 driver for lcd"
- help
- Support for lcd bl ldim OB3350 controlling
-
-config AML_LOCAL_DIMMING_IW7027
- bool "bl ldim IW7027 driver for lcd"
- help
- Support for lcd bl ldim IW7027 controlling
-
-
diff --git a/drivers/amlogic/media/vout/lcd/bl_ldim/Makefile b/drivers/amlogic/media/vout/lcd/bl_ldim/Makefile
deleted file mode 100644
index 4492171..0000000
--- a/drivers/amlogic/media/vout/lcd/bl_ldim/Makefile
+++ /dev/null
@@ -1,4 +0,0 @@
-obj-$(CONFIG_AML_LOCAL_DIMMING) += ldim_drv.o ldim_dev_drv.o ldim_spi.o
-obj-$(CONFIG_AML_LOCAL_DIMMING_GLOBAL) += global.o
-obj-$(CONFIG_AML_LOCAL_DIMMING_OB3350) += ob3350.o
-obj-$(CONFIG_AML_LOCAL_DIMMING_IW7027) += iw7027.o
\ No newline at end of file
diff --git a/drivers/amlogic/media/vout/lcd/bl_ldim/global.c b/drivers/amlogic/media/vout/lcd/bl_ldim/global.c
deleted file mode 100644
index 9bdda4c..0000000
--- a/drivers/amlogic/media/vout/lcd/bl_ldim/global.c
+++ /dev/null
@@ -1,139 +0,0 @@
-/*
- * drivers/amlogic/media/vout/lcd/bl_ldim/global_bl.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/arch/gpio.h>
-#include <fdtdec.h>
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#include <amlogic/media/vout/lcd/bl_ldim.h>
-#include "../lcd_reg.h"
-#include "../lcd_common.h"
-#include "ldim_drv.h"
-#include "ldim_dev_drv.h"
-
-static int global_on_flag;
-
-static int global_hw_init_on(void)
-{
- struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
-
- ldim_drv->pinmux_ctrl(1);
- mdelay(2);
- ldim_gpio_set(ldim_drv->ldev_conf->en_gpio, ldim_drv->ldev_conf->en_gpio_on);
- mdelay(20);
-
- return 0;
-}
-
-static int global_hw_init_off(void)
-{
- struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
-
- ldim_drv->pinmux_ctrl(0);
- ldim_gpio_set(ldim_drv->ldev_conf->en_gpio, ldim_drv->ldev_conf->en_gpio_off);
-
- return 0;
-}
-
-static unsigned int global_get_value(unsigned int level)
-{
- struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
-
- unsigned int val;
- unsigned int dim_max, dim_min;
-
- dim_max = ldim_drv->ldev_conf->dim_max;
- dim_min = ldim_drv->ldev_conf->dim_min;
-
- val = dim_min + ((level * (dim_max - dim_min)) / LD_DATA_MAX);
-
- return val;
-}
-
-static int global_smr(unsigned short *buf, unsigned char len)
-{
- struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
- unsigned short val;
-
- val = global_get_value(buf[0]);
- ldim_drv->ldev_conf->pwm_config.pwm_duty = val;
-
- if (global_on_flag == 0) {
- if (lcd_debug_print_flag)
- LDIMPR("%s: on_flag=%d\n", __func__, global_on_flag);
- return 0;
- }
-
- if (len != 1) {
- LDIMERR("%s: data len %d invalid\n", __func__, len);
- return -1;
- }
-
- ldim_set_duty_pwm(&(ldim_drv->ldev_conf->pwm_config));
-
- return 0;
-}
-
-static int global_power_on(void)
-{
- struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
-
- global_hw_init_on();
- global_on_flag = 1;
-
- /* init brightness level */
- ldim_set_duty_pwm(&(ldim_drv->ldev_conf->pwm_config));
-
- LDIMPR("%s: ok\n", __func__);
- return 0;
-}
-
-static int global_power_off(void)
-{
- global_on_flag = 0;
- global_hw_init_off();
-
- LDIMPR("%s: ok\n", __func__);
- return 0;
-}
-
-static int global_ldim_driver_update(struct aml_ldim_driver_s *ldim_drv)
-{
- ldim_drv->device_power_on = global_power_on;
- ldim_drv->device_power_off = global_power_off;
- ldim_drv->device_bri_update = global_smr;
-
- return 0;
-}
-
-int ldim_dev_global_probe(struct aml_ldim_driver_s *ldim_drv)
-{
- global_on_flag = 0;
- global_ldim_driver_update(ldim_drv);
-
- return 0;
-}
-
-int ldim_dev_global_remove(struct aml_ldim_driver_s *ldim_drv)
-{
- return 0;
-}
-
diff --git a/drivers/amlogic/media/vout/lcd/bl_ldim/iw7027.c b/drivers/amlogic/media/vout/lcd/bl_ldim/iw7027.c
deleted file mode 100644
index bebf351..0000000
--- a/drivers/amlogic/media/vout/lcd/bl_ldim/iw7027.c
+++ /dev/null
@@ -1,446 +0,0 @@
-/*
- * drivers/amlogic/media/vout/lcd/bl_ldim/iw7027.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <spi.h>
-#include <asm/arch/gpio.h>
-#include <fdtdec.h>
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#include <amlogic/media/vout/lcd/bl_ldim.h>
-#include "../lcd_reg.h"
-#include "../lcd_common.h"
-#include "ldim_drv.h"
-#include "ldim_dev_drv.h"
-
-#define NORMAL_MSG (0<<7)
-#define BROADCAST_MSG (1<<7)
-#define BLOCK_DATA (0<<6)
-#define SINGLE_DATA (1<<6)
-#define IW7027_DEV_ADDR 1
-
-static int iw7027_on_flag;
-
-struct iw7027 {
- int cs_hold_delay;
- int cs_clk_delay;
- unsigned char cmd_size;
- unsigned char *init_data;
- unsigned int init_data_cnt;
- struct spi_slave *spi;
-};
-static struct iw7027 *bl_iw7027;
-
-static unsigned char *val_brightness;
-
-#if 0
-static unsigned char iw7027_init_data[LDIM_INIT_ON_SIZE] = {
- 0xc0, 0x23, 0x03,
- 0xc0, 0x24, 0xff,
- 0xc0, 0x25, 0x00,
- 0xc0, 0x26, 0x00,
- 0xc0, 0x27, 0x60,
- 0xc0, 0x29, 0x00,
- 0xc0, 0x2a, 0x00,
- 0xc0, 0x2b, 0x00,
- 0xc0, 0x2c, 0x73,
- 0xc0, 0x2d, 0x37,
- 0xc0, 0x31, 0x93,
- 0xc0, 0x32, 0x0f,
- 0xc0, 0x33, 0xff,
- 0xc0, 0x34, 0xc8,
- 0xc0, 0x35, 0xbf,
- 0xff, 0x00, 0x00,
-};
-#endif
-
-//iw7027 register write
-static int iw7027_wreg(struct spi_slave *spi, unsigned char addr, unsigned char val)
-{
- unsigned char tbuf[3];
- int ret;
-
- if (lcd_debug_print_flag)
- LDIMPR("%s: 0x%02x = 0x%02x\n", __func__, addr, val);
-
- tbuf[0] = NORMAL_MSG | SINGLE_DATA | IW7027_DEV_ADDR;
- tbuf[1] = addr & 0x7f;
- tbuf[2] = val;
- ret = ldim_spi_write(spi, tbuf, 3);
-
- return ret;
-}
-
-//iw7027 register read
-static int iw7027_rreg(struct spi_slave *spi, unsigned char addr,
- unsigned char *val)
-{
- unsigned char tbuf[4], rbuf[4], temp;
- int ret;
-
- /*set read flag*/
- temp = (addr >= 0x80) ? 0x80 : 0x0;
- iw7027_wreg(spi, 0x78, temp);
-
- tbuf[0] = NORMAL_MSG | SINGLE_DATA | IW7027_DEV_ADDR;
- tbuf[1] = addr | 0x80;
- tbuf[2] = 0;
- ret = ldim_spi_read(spi, tbuf, 3, rbuf, 1);
- *val = rbuf[3];
-
- return ret;
-}
-
-//iw7027 block write
-static int iw7027_wregs(struct spi_slave *spi, unsigned char addr,
- unsigned char *val, int len)
-{
- unsigned char tbuf[30];
- int ret, i;
-
- if (lcd_debug_print_flag) {
- LDIMPR("%s: ", __func__);
- for (i = 0; i < len; i++)
- printf("0x%02x ", val[i]);
- printf("\n");
- }
-
- tbuf[0] = NORMAL_MSG | BLOCK_DATA | IW7027_DEV_ADDR;
- tbuf[1] = len;
- tbuf[2] = addr & 0x7f;
- memcpy(&tbuf[3], val, len);
- ret = ldim_spi_write(spi, tbuf, (len + 3));
-
- return ret;
-}
-
-static int ldim_power_cmd_dynamic_size(void)
-{
- unsigned char *table;
- int i = 0, j, step = 0, max_len = 0;
- unsigned char type, cmd_size;
- int delay_ms, ret = 0;
-
- table = bl_iw7027->init_data;
- max_len = bl_iw7027->init_data_cnt;
-
- while ((i + 1) < max_len) {
- type = table[i];
- if (type == LCD_EXT_CMD_TYPE_END)
- break;
- if (lcd_debug_print_flag) {
- LDIMPR("%s: step %d: type=0x%02x, cmd_size=%d\n",
- __func__, step, type, table[i+1]);
- }
- cmd_size = table[i+1];
- if (cmd_size == 0)
- goto power_cmd_dynamic_next;
- if ((i + 2 + cmd_size) > max_len)
- break;
-
- if (type == LCD_EXT_CMD_TYPE_NONE) {
- /* do nothing */
- } else if (type == LCD_EXT_CMD_TYPE_DELAY) {
- delay_ms = 0;
- for (j = 0; j < cmd_size; j++)
- delay_ms += table[i+2+j];
- if (delay_ms > 0)
- mdelay(delay_ms);
- } else if (type == LCD_EXT_CMD_TYPE_CMD) {
- ret = iw7027_wreg(bl_iw7027->spi,
- table[i+2], table[i+3]);
- udelay(1);
- } else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
- ret = iw7027_wreg(bl_iw7027->spi,
- table[i+2], table[i+3]);
- udelay(1);
- if (table[i+4] > 0)
- mdelay(table[i+4]);
- } else {
- LDIMERR("%s: type 0x%02x invalid\n", __func__, type);
- }
-power_cmd_dynamic_next:
- i += (cmd_size + 2);
- step++;
- }
-
- return ret;
-}
-
-static int ldim_power_cmd_fixed_size(void)
-{
- unsigned char *table;
- int i = 0, j, step = 0, max_len = 0;
- unsigned char type, cmd_size;
- int delay_ms, ret = 0;
-
- cmd_size = bl_iw7027->cmd_size;
- if (cmd_size < 2) {
- LDIMERR("%s: invalid cmd_size %d\n", __func__, cmd_size);
- return -1;
- }
-
- table = bl_iw7027->init_data;
- max_len = bl_iw7027->init_data_cnt;
-
- while ((i + cmd_size) <= max_len) {
- type = table[i];
- if (type == LCD_EXT_CMD_TYPE_END)
- break;
- if (lcd_debug_print_flag) {
- LDIMPR("%s: step %d: type=0x%02x, cmd_size=%d\n",
- __func__, step, type, cmd_size);
- }
- if (type == LCD_EXT_CMD_TYPE_NONE) {
- /* do nothing */
- } else if (type == LCD_EXT_CMD_TYPE_DELAY) {
- delay_ms = 0;
- for (j = 0; j < (cmd_size - 1); j++)
- delay_ms += table[i+1+j];
- if (delay_ms > 0)
- mdelay(delay_ms);
- } else if (type == LCD_EXT_CMD_TYPE_CMD) {
- ret = iw7027_wreg(bl_iw7027->spi,
- table[i+1], table[i+2]);
- udelay(1);
- } else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
- ret = iw7027_wreg(bl_iw7027->spi,
- table[i+1], table[i+2]);
- udelay(1);
- if (table[i+3] > 0)
- mdelay(table[i+3]);
- } else {
- LDIMERR("%s: type 0x%02x invalid\n", __func__, type);
- }
- i += cmd_size;
- step++;
- }
-
- return ret;
-}
-
-static int iw7027_power_on_init(void)
-{
- unsigned char cmd_size;
- int ret = 0;
-
- cmd_size = bl_iw7027->cmd_size;
- if (cmd_size < 2) {
- LDIMERR("%s: invalid cmd_size %d\n", __func__, cmd_size);
- return -1;
- }
- if (cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC)
- ret = ldim_power_cmd_dynamic_size();
- else
- ret = ldim_power_cmd_fixed_size();
-
- return ret;
-}
-
-static int iw7027_hw_init_on(void)
-{
- int i;
- unsigned char reg_duty_chk = 0 , reg_chk = 0;
- struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
-
- /* step 1: system power_on */
- LDIMPR("%s: iw7027 system power_on\n", __func__);
- ldim_gpio_set(ldim_drv->ldev_conf->en_gpio, ldim_drv->ldev_conf->en_gpio_on);
- ldim_set_duty_pwm(&(ldim_drv->ldev_conf->pwm_config));
-
- /* step 2: delay for internal logic stable */
- mdelay(10);
-
- /* step 3: SPI communication check */
- LDIMPR("%s: SPI Communication Check\n", __func__);
- for (i = 0; i <= 10; i++) {
- iw7027_wreg(bl_iw7027->spi, 0x00, 0x06);
- iw7027_rreg(bl_iw7027->spi, 0x00, ®_chk);
- if (reg_chk == 0x06)
- break;
- if (i == 10) {
- LDIMERR("%s: SPI communication check error\n",
- __func__);
- }
- }
-
- /* step 4: configure initial registers */
- LDIMPR("%s: Write initial control registers\n", __func__);
- iw7027_power_on_init();
-
- /* step 5: supply stable vsync */
- LDIMPR("%s: open Vsync\n", __func__);
- ldim_drv->pinmux_ctrl(1);
-
- /* step 6: delay for system clock and light bar PSU stable */
- mdelay(550);
-
- /* step 7: start calibration */
- LDIMPR("%s: start calibration\n", __func__);
- iw7027_wreg(bl_iw7027->spi, 0x00, 0x07);
- mdelay(200);
-
- /* step 8: calibration done or not */
- i = 0;
- while (i++ < 1000) {
- iw7027_rreg(bl_iw7027->spi, 0xb3, ®_duty_chk);
- /*VDAC statue reg :FB1=[0x5] FB2=[0x50]*/
- /*The current platform using FB1*/
- if ((reg_duty_chk & 0xf) == 0x05)
- break;
- mdelay(1);
- }
- LDIMPR("%s: calibration done: [%d] = %x\n", __func__, i, reg_duty_chk);
-
- return 0;
-}
-
-static int iw7027_hw_init_off(void)
-{
- struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
-
- ldim_drv->pinmux_ctrl(0);
- ldim_gpio_set(ldim_drv->ldev_conf->en_gpio, ldim_drv->ldev_conf->en_gpio_off);
-
- return 0;
-}
-
-static unsigned int dim_max, dim_min;
-static unsigned int iw7027_get_value(unsigned int level)
-{
- unsigned int val;
-
- val = dim_min + ((level * (dim_max - dim_min)) / LD_DATA_MAX);
-
- return val;
-}
-
-static int iw7027_smr(unsigned short *buf, unsigned char len)
-{
- unsigned int i, temp;
- unsigned short num;
- struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
-
- if (iw7027_on_flag == 0) {
- LDIMPR("%s: on_flag=%d\n", __func__, iw7027_on_flag);
- return 0;
- }
- num = ldim_drv->ldev_conf->bl_regnum;
- if (len != num) {
- LDIMERR("%s: data len %d invalid\n", __func__, len);
- return -1;
- }
- if (val_brightness == NULL) {
- LDIMERR("%s: val_brightness is null\n", __func__);
- return -1;
- }
-
- dim_max = ldim_drv->ldev_conf->dim_max;
- dim_min = ldim_drv->ldev_conf->dim_min;
-
- for (i = 0; i < num; i++) {
- temp = iw7027_get_value(buf[i]);
- val_brightness[2*i] = (temp >> 8) & 0xf;
- val_brightness[2*i+1] = temp & 0xff;
- }
-
- iw7027_wregs(bl_iw7027->spi, 0x40, val_brightness, (num * 2));
-
- return 0;
-}
-
-static int iw7027_power_on(void)
-{
- iw7027_hw_init_on();
- iw7027_on_flag = 1;
-
- LDIMPR("%s: ok\n", __func__);
- return 0;
-}
-
-static int iw7027_power_off(void)
-{
- iw7027_on_flag = 0;
- iw7027_hw_init_off();
-
- LDIMPR("%s: ok\n", __func__);
- return 0;
-}
-
-static int iw7027_ldim_driver_update(struct aml_ldim_driver_s *ldim_drv)
-{
- ldim_drv->device_power_on = iw7027_power_on;
- ldim_drv->device_power_off = iw7027_power_off;
- ldim_drv->device_bri_update = iw7027_smr;
- return 0;
-}
-
-int ldim_dev_iw7027_probe(struct aml_ldim_driver_s *ldim_drv)
-{
- if (ldim_drv->spi_info->spi == NULL) {
- LDIMERR("%s: spi is null\n", __func__);
- return -1;
- }
-
- bl_iw7027 = (struct iw7027 *)malloc(sizeof(struct iw7027));
- if (bl_iw7027 == NULL) {
- LDIMERR("iw7027 malloc error\n");
- return -1;
- }
- memset(bl_iw7027, 0, sizeof(struct iw7027));
-
- iw7027_on_flag = 0;
-
- bl_iw7027->spi = ldim_drv->spi_info->spi;
- bl_iw7027->cs_hold_delay = ldim_drv->ldev_conf->cs_hold_delay;
- bl_iw7027->cs_clk_delay = ldim_drv->ldev_conf->cs_clk_delay;
- bl_iw7027->cmd_size = ldim_drv->ldev_conf->cmd_size;
- bl_iw7027->init_data = ldim_drv->ldev_conf->init_on;
- bl_iw7027->init_data_cnt = ldim_drv->ldev_conf->init_on_cnt;
-
- val_brightness = (unsigned char *)malloc(
- ldim_drv->ldev_conf->bl_regnum * 2 * sizeof(unsigned char));
- if (val_brightness == NULL) {
- LDIMERR("malloc val_brightness failed\n");
- free(bl_iw7027);
- return -1;
- }
-
- iw7027_ldim_driver_update(ldim_drv);
-
- printf("%s: ok\n", __func__);
-
- return 0;
-}
-
-int ldim_dev_iw7027_remove(struct aml_ldim_driver_s *ldim_drv)
-{
- if (val_brightness) {
- free(val_brightness);
- val_brightness = NULL;
- }
-
- if (bl_iw7027) {
- free(bl_iw7027);
- bl_iw7027 = NULL;
- }
- return 0;
-}
-
diff --git a/drivers/amlogic/media/vout/lcd/bl_ldim/ldim_dev_drv.c b/drivers/amlogic/media/vout/lcd/bl_ldim/ldim_dev_drv.c
deleted file mode 100644
index c9ba60a..0000000
--- a/drivers/amlogic/media/vout/lcd/bl_ldim/ldim_dev_drv.c
+++ /dev/null
@@ -1,1070 +0,0 @@
-/*
- * drivers/amlogic/media/vout/lcd/bl_ldim/iw7019.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <spi.h>
-#include <asm/arch/gpio.h>
-#include <fdtdec.h>
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#include <amlogic/media/vout/lcd/bl_ldim.h>
-#include "../lcd_reg.h"
-#include "../lcd_common.h"
-#include "ldim_drv.h"
-#include "ldim_dev_drv.h"
-
-static struct ldim_dev_config_s *ldim_dev_config;
-static int ldim_dev_probe_flag;
-
-struct ldim_spi_dev_info_s ldim_spi_info = {
- .modalias = "ldim_dev",
- .spi_name = "none",
- .mode = SPI_MODE_0,
- .max_speed_hz = 1000000, /* 1MHz */
- .bus_num = 0, /* SPI bus No. */
- .chip_select = 0, /* the device index on the spi bus */
- .wordlen = 8,
- .spi = NULL,
-};
-
-/* ***************************************
- * ldim gpio
- * *************************************** */
-static struct lcd_cpu_gpio_s ldim_gpio[BL_GPIO_NUM_MAX] = {
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
-};
-
-static int ldim_gpio_probe(const char *name, int index)
-{
- if (name == NULL) {
- LDIMERR("bl: %s: gpio name is null\n", __func__);
- return -1;
- }
- if (index >= BL_GPIO_NUM_MAX) {
- LDIMERR("bl: %s: invalid gpio: %d\n", __func__, index);
- return -1;
- }
- if (ldim_gpio[index].probe_flag == 1) {
- if (lcd_debug_print_flag) {
- LDIMPR("bl: gpio %s(%d) is already probed\n",
- ldim_gpio[index].name, index);
- }
- return 0;
- }
-
- if (lcd_debug_print_flag)
- LDIMPR("bl: probe gpio: %s(%d)\n", name, index);
- strcpy(ldim_gpio[index].name, name);
- /* init gpio flag */
- ldim_gpio[index].probe_flag = 1;
- ldim_gpio[index].register_flag = 0;
-
- return 0;
-}
-
-static int ldim_gpio_request(int index)
-{
- int ret = 0;
-
- if (index >= BL_GPIO_NUM_MAX) {
- LDIMERR("bl: %s: invalid gpio: %d\n", __func__, index);
- return -1;
- }
- if (ldim_gpio[index].probe_flag == 0) {
- LDIMERR("bl: gpio %d is not probed\n", index);
- return -1;
- }
- if (ldim_gpio[index].register_flag == 1) {
- if (lcd_debug_print_flag) {
- LDIMPR("bl: gpio %s(%d) is already registered\n",
- ldim_gpio[index].name, index);
- }
- return 0;
- }
-
- ret = dm_gpio_lookup_name(ldim_gpio[index].name, &ldim_gpio[index].gpio);
- if (ret) {
- LDIMERR("bl: lookup gpio: wrong name %s\n", ldim_gpio[index].name);
- return -1;
- }
-
- ret = dm_gpio_request(&ldim_gpio[index].gpio, "aml_lcd_bl");
- if (ret) {
- LDIMERR("bl: request gpio %s(%d) failed\n", ldim_gpio[index].name, index);
- return -1;
- }
-
- if (lcd_debug_print_flag)
- LDIMPR("bl: request gpio: %s(%d)\n", ldim_gpio[index].name, index);
- ldim_gpio[index].register_flag = 1;
-
- return 0;
-}
-
-int ldim_gpio_set(int index, int value)
-{
- int ret = 0;
-
- if (index >= BL_GPIO_NUM_MAX) {
- LDIMERR("bl: %s: invalid gpio: %d\n", __func__, index);
- return -1;
- }
- if (ldim_gpio[index].register_flag == 0) {
- ret = ldim_gpio_request(index);
- if (ret)
- return -1;
- }
-
- switch (value) {
- case LCD_GPIO_OUTPUT_LOW:
- ret = dm_gpio_set_dir_flags(&ldim_gpio[index].gpio, GPIOD_IS_OUT);
- if (ret) {
- LDIMERR("bl: set gpio %s(%d) direction failed\n",
- ldim_gpio[index].name, index);
- return ret;
- }
- dm_gpio_set_value(&ldim_gpio[index].gpio, 0);
- break;
- case LCD_GPIO_OUTPUT_HIGH:
- ret = dm_gpio_set_dir_flags(&ldim_gpio[index].gpio, GPIOD_IS_OUT);
- if (ret) {
- LDIMERR("bl: set gpio %s(%d) direction failed\n",
- ldim_gpio[index].name, index);
- return ret;
- }
- dm_gpio_set_value(&ldim_gpio[index].gpio, 1);
- break;
- case LCD_GPIO_INPUT:
- default:
- ret = dm_gpio_set_dir_flags(&ldim_gpio[index].gpio, GPIOD_IS_IN);
- if (ret) {
- LDIMERR("bl: set gpio %s(%d) direction failed\n",
- ldim_gpio[index].name, index);
- return ret;
- }
- break;
- }
- if (lcd_debug_print_flag) {
- LDIMPR("bl: gpio: %s(%d), value: %d\n",
- ldim_gpio[index].name, index, value);
- }
-
- return 0;
-}
-
-unsigned int ldim_gpio_input_get(int index)
-{
- int ret;
- unsigned int value;
-
- if (index >= BL_GPIO_NUM_MAX) {
- LDIMERR("%s: invalid gpio: %d\n", __func__, index);
- return 0;
- }
- if (ldim_gpio[index].register_flag == 0) {
- ret = ldim_gpio_request(index);
- if (ret)
- return 0;
- }
-
- value = dm_gpio_get_value(&ldim_gpio[index].gpio);
-
- return value;
-}
-/* *************************************** */
-
-static unsigned int pwm_reg[6] = {
- PWM_PWM_A,
- PWM_PWM_B,
- PWM_PWM_C,
- PWM_PWM_D,
- PWM_PWM_E,
- PWM_PWM_F,
-};
-
-void ldim_set_duty_pwm(struct bl_pwm_config_s *bl_pwm)
-{
- unsigned int pwm_hi = 0, pwm_lo = 0;
- unsigned int port = bl_pwm->pwm_port;
- unsigned int vs[4], ve[4], sw, n, i;
-
- bl_pwm->pwm_level = bl_pwm->pwm_cnt * bl_pwm->pwm_duty / 100;
-
- LDIMPR("pwm port %d: duty=%d%%, duty_max=%d, duty_min=%d\n",
- bl_pwm->pwm_port, bl_pwm->pwm_duty,
- bl_pwm->pwm_duty_max, bl_pwm->pwm_duty_min);
-
- switch (bl_pwm->pwm_method) {
- case BL_PWM_POSITIVE:
- pwm_hi = bl_pwm->pwm_level;
- pwm_lo = bl_pwm->pwm_cnt - bl_pwm->pwm_level;
- break;
- case BL_PWM_NEGATIVE:
- pwm_lo = bl_pwm->pwm_level;
- pwm_hi = bl_pwm->pwm_cnt - bl_pwm->pwm_level;
- break;
- default:
- LDIMERR("port %d: invalid pwm_method %d\n",
- port, bl_pwm->pwm_method);
- break;
- }
- LDIMPR("port %d: pwm_cnt=%d, pwm_hi=%d, pwm_lo=%d\n",
- port, bl_pwm->pwm_cnt, pwm_hi, pwm_lo);
-
- switch (port) {
- case BL_PWM_A:
- case BL_PWM_B:
- case BL_PWM_C:
- case BL_PWM_D:
- case BL_PWM_E:
- case BL_PWM_F:
- lcd_cbus_write(pwm_reg[port], (pwm_hi << 16) | pwm_lo);
- break;
- case BL_PWM_VS:
- memset(vs, 0xffff, sizeof(unsigned int) * 4);
- memset(ve, 0xffff, sizeof(unsigned int) * 4);
- n = bl_pwm->pwm_freq;
- sw = (bl_pwm->pwm_cnt * 10 / n + 5) / 10;
- pwm_hi = (pwm_hi * 10 / n + 5) / 10;
- pwm_hi = (pwm_hi > 1) ? pwm_hi : 1;
- if (lcd_debug_print_flag)
- LDIMPR("n=%d, sw=%d, pwm_high=%d\n", n, sw, pwm_hi);
- for (i = 0; i < n; i++) {
- vs[i] = 1 + (sw * i);
- ve[i] = vs[i] + pwm_hi - 1;
- if (lcd_debug_print_flag)
- LDIMPR("vs[%d]=%d, ve[%d]=%d\n", i, vs[i], i, ve[i]);
- }
- lcd_vcbus_write(VPU_VPU_PWM_V0, (ve[0] << 16) | (vs[0]));
- lcd_vcbus_write(VPU_VPU_PWM_V1, (ve[1] << 16) | (vs[1]));
- lcd_vcbus_write(VPU_VPU_PWM_V2, (ve[2] << 16) | (vs[2]));
- lcd_vcbus_write(VPU_VPU_PWM_V3, (ve[3] << 16) | (vs[3]));
- break;
- default:
- break;
- }
-}
-
-/* set ldim pwm_vs */
-static int ldim_pwm_pinmux_ctrl(int status)
-{
- struct bl_pwm_config_s *ld_pwm = &ldim_dev_config->pwm_config;
- int i;
-
- if (ld_pwm->pwm_port >= BL_PWM_MAX)
- return 0;
-
- if (lcd_debug_print_flag)
- LDIMPR("%s: %d\n", __func__, status);
-
- if (status) {
- bl_pwm_ctrl(ld_pwm, 1);
- /* set pinmux */
- ld_pwm->pinmux_flag = 1;
- i = 0;
- while (i < LCD_PINMUX_NUM) {
- if (ld_pwm->pinmux_clr[i][0] == LCD_PINMUX_END)
- break;
- lcd_pinmux_clr_mask(ld_pwm->pinmux_clr[i][0],
- ld_pwm->pinmux_clr[i][1]);
- if (lcd_debug_print_flag) {
- LDIMPR("%s: port=%d, pinmux_clr=%d,0x%08x\n",
- __func__, ld_pwm->pwm_port,
- ld_pwm->pinmux_clr[i][0],
- ld_pwm->pinmux_clr[i][1]);
- }
- i++;
- }
- i = 0;
- while (i < LCD_PINMUX_NUM) {
- if (ld_pwm->pinmux_set[i][0] == LCD_PINMUX_END)
- break;
- lcd_pinmux_set_mask(ld_pwm->pinmux_set[i][0],
- ld_pwm->pinmux_set[i][1]);
- if (lcd_debug_print_flag) {
- LDIMPR("%s: port=%d, pinmux_set=%d,0x%08x\n",
- __func__, ld_pwm->pwm_port,
- ld_pwm->pinmux_set[i][0],
- ld_pwm->pinmux_set[i][1]);
- }
- i++;
- }
- } else {
- i = 0;
- while (i < LCD_PINMUX_NUM) {
- if (ld_pwm->pinmux_set[i][0] == LCD_PINMUX_END)
- break;
- lcd_pinmux_clr_mask(ld_pwm->pinmux_set[i][0],
- ld_pwm->pinmux_set[i][1]);
- if (lcd_debug_print_flag) {
- LDIMPR("%s: port=%d, pinmux_clr=%d,0x%08x\n",
- __func__, ld_pwm->pwm_port,
- ld_pwm->pinmux_set[i][0],
- ld_pwm->pinmux_set[i][1]);
- }
- i++;
- }
- ld_pwm->pinmux_flag = 0;
-
- bl_pwm_ctrl(ld_pwm, 0);
- }
-
- return 0;
-}
-
-static void ldim_dev_init_table_dynamic_size_print(
- struct ldim_dev_config_s *ldconf, int flag)
-{
- int i, j, max_len;
- unsigned char cmd_size;
- unsigned char *table;
-
- if (flag) {
- printf("power on:\n");
- table = ldconf->init_on;
- max_len = ldconf->init_on_cnt;
- } else {
- printf("power off:\n");
- table = ldconf->init_off;
- max_len = ldconf->init_off_cnt;
- }
- if (table == NULL) {
- LDIMERR("init_table %d is NULL\n", flag);
- return;
- }
-
- i = 0;
- while ((i + 1) < max_len) {
- if (table[i] == LCD_EXT_CMD_TYPE_END) {
- printf(" 0x%02x,%d,\n", table[i], table[i+1]);
- break;
- }
- cmd_size = table[i+1];
- printf(" 0x%02x,%d,", table[i], cmd_size);
- if (cmd_size == 0)
- goto init_table_dynamic_print_next;
- if (i + 2 + cmd_size > max_len) {
- printf("cmd_size out of support\n");
- break;
- }
-
- if (table[i] == LCD_EXT_CMD_TYPE_DELAY) {
- for (j = 0; j < cmd_size; j++)
- printf("%d,", table[i+2+j]);
- } else if (table[i] == LCD_EXT_CMD_TYPE_CMD) {
- for (j = 0; j < cmd_size; j++)
- printf("0x%02x,", table[i+2+j]);
- } else if (table[i] == LCD_EXT_CMD_TYPE_CMD_DELAY) {
- for (j = 0; j < (cmd_size - 1); j++)
- printf("0x%02x,", table[i+2+j]);
- printf("%d,", table[i+cmd_size+1]);
- } else {
- for (j = 0; j < cmd_size; j++)
- printf("0x%02x,", table[i+2+j]);
- }
-init_table_dynamic_print_next:
- printf("\n");
- i += (cmd_size + 2);
- }
-}
-
-static void ldim_dev_init_table_fixed_size_print(
- struct ldim_dev_config_s *ldconf, int flag)
-{
- int i, j, max_len;
- unsigned char cmd_size;
- unsigned char *table;
-
- cmd_size = ldconf->cmd_size;
- if (flag) {
- printf("power on:\n");
- table = ldconf->init_on;
- max_len = ldconf->init_on_cnt;
- } else {
- printf("power off:\n");
- table = ldconf->init_off;
- max_len = ldconf->init_off_cnt;
- }
- if (table == NULL) {
- LDIMERR("init_table %d is NULL\n", flag);
- return;
- }
-
- i = 0;
- while ((i + cmd_size) <= max_len) {
- printf(" ");
- for (j = 0; j < cmd_size; j++)
- printf("0x%02x,", table[i+j]);
- printf("\n");
-
- if (table[i] == LCD_EXT_CMD_TYPE_END)
- break;
- i += cmd_size;
- }
-}
-
-static void ldim_device_config_print(void)
-{
- struct bl_pwm_config_s *ld_pwm;
-
- if (ldim_dev_config == NULL) {
- LDIMERR("%s: ldim_dev_config is null\n", __func__);
- return;
- }
- ld_pwm = &ldim_dev_config->pwm_config;
-
- printf("dev_name = %s\n"
- "en_gpio = %d\n"
- "en_gpio_on = %d\n"
- "en_gpio_off = %d\n"
- "dim_max = 0x%03x\n"
- "dim_min = 0x%03x\n"
- "region_num = %d\n",
- ldim_dev_config->name,
- ldim_dev_config->en_gpio,
- ldim_dev_config->en_gpio_on,
- ldim_dev_config->en_gpio_off,
- ldim_dev_config->dim_min,
- ldim_dev_config->dim_max,
- ldim_dev_config->bl_regnum);
-
- switch (ldim_dev_config->type) {
- case LDIM_DEV_TYPE_SPI:
- printf("spi_pointer = 0x%p\n"
- "spi_modalias = %s\n"
- "spi_mode = %d\n"
- "spi_max_speed_hz = %d\n"
- "spi_bus_num = %d\n"
- "spi_chip_select = %d\n"
- "cs_hold_delay = %d\n"
- "cs_clk_delay = %d\n"
- "write_check = %d\n",
- ldim_spi_info.spi,
- ldim_spi_info.modalias,
- ldim_spi_info.mode,
- ldim_spi_info.max_speed_hz,
- ldim_spi_info.bus_num,
- ldim_spi_info.chip_select,
- ldim_dev_config->cs_hold_delay,
- ldim_dev_config->cs_clk_delay,
- ldim_dev_config->write_check);
- break;
- case LDIM_DEV_TYPE_I2C:
- break;
- case LDIM_DEV_TYPE_NORMAL:
- default:
- break;
- }
- if (ld_pwm->pwm_port < BL_PWM_MAX) {
- printf("pwm_port = %d\n"
- "pwm_pol = %d\n"
- "pwm_freq = %d\n"
- "pwm_duty = %d%%\n"
- "pinmux_flag = %d\n",
- ld_pwm->pwm_port, ld_pwm->pwm_method,
- ld_pwm->pwm_freq, ld_pwm->pwm_duty,
- ld_pwm->pinmux_flag);
- }
-
- if (ldim_dev_config->cmd_size > 0) {
- printf("init_loaded = %d\n"
- "cmd_size = %d\n"
- "init_on_cnt = %d\n"
- "init_off_cnt = %d\n",
- ldim_dev_config->init_loaded,
- ldim_dev_config->cmd_size,
- ldim_dev_config->init_on_cnt,
- ldim_dev_config->init_off_cnt);
- if (ldim_dev_config->cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC) {
- ldim_dev_init_table_dynamic_size_print(ldim_dev_config, 1);
- ldim_dev_init_table_dynamic_size_print(ldim_dev_config, 0);
- } else {
- ldim_dev_init_table_fixed_size_print(ldim_dev_config, 1);
- ldim_dev_init_table_fixed_size_print(ldim_dev_config, 0);
- }
- }
-}
-
-static int ldim_pinmux_load_from_bsp(struct ldim_dev_config_s *ldev_conf)
-{
- char propname[50] = "ldim_pwm_vs_pin";
- unsigned int i, j;
- int set_cnt = 0, clr_cnt = 0;
- struct bl_pwm_config_s *ld_pwm = &ldev_conf->pwm_config;
-
- for (i = 0; i < 2; i++) {
- if (strncmp(ldev_conf->ldim_pinmux->name, "invalid", 7) == 0)
- break;
- if (strncmp(ldev_conf->ldim_pinmux->name, propname, strlen(propname)) == 0) {
- for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
- if (ldev_conf->ldim_pinmux->pinmux_set[j][0] == LCD_PINMUX_END)
- break;
- ld_pwm->pinmux_set[j][0] = ldev_conf->ldim_pinmux->pinmux_set[j][0];
- ld_pwm->pinmux_set[j][1] = ldev_conf->ldim_pinmux->pinmux_set[j][1];
- set_cnt++;
- }
- for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
- if (ldev_conf->ldim_pinmux->pinmux_clr[j][0] == LCD_PINMUX_END)
- break;
- ld_pwm->pinmux_clr[j][0] = ldev_conf->ldim_pinmux->pinmux_clr[j][0];
- ld_pwm->pinmux_clr[j][1] = ldev_conf->ldim_pinmux->pinmux_clr[j][1];
- clr_cnt++;
- }
- break;
- }
- ldev_conf->ldim_pinmux++;
- }
- if (set_cnt < LCD_PINMUX_NUM) {
- ld_pwm->pinmux_set[set_cnt][0] = LCD_PINMUX_END;
- ld_pwm->pinmux_set[set_cnt][1] = 0x0;
- }
- if (clr_cnt < LCD_PINMUX_NUM) {
- ld_pwm->pinmux_clr[clr_cnt][0] = LCD_PINMUX_END;
- ld_pwm->pinmux_clr[clr_cnt][1] = 0x0;
- }
-
- if (lcd_debug_print_flag) {
- i = 0;
- while (i < LCD_PINMUX_NUM) {
- if (ld_pwm->pinmux_set[i][0] == LCD_PINMUX_END)
- break;
- LDIMPR("ldim_pinmux set: %d, 0x%08x\n",
- ld_pwm->pinmux_set[i][0], ld_pwm->pinmux_set[i][1]);
- i++;
- }
- i = 0;
- while (i < LCD_PINMUX_NUM) {
- if (ld_pwm->pinmux_clr[i][0] == LCD_PINMUX_END)
- break;
- LDIMPR("ldim_pinmux clr: %d, 0x%08x\n",
- ld_pwm->pinmux_clr[i][0], ld_pwm->pinmux_clr[i][1]);
- i++;
- }
- }
-
- return 0;
-}
-
-static int ldim_dev_init_table_dynamic_size_load_dts(const void *dt_blob,
- int nodeoffset, struct ldim_dev_config_s *ldconf, int flag)
-{
- unsigned char cmd_size, type;
- int i = 0, j, max_len;
- unsigned char *table;
- char propname[20];
- char *propdata;
-
- if (flag) {
- table = ldconf->init_on;
- max_len = LDIM_INIT_ON_MAX;
- sprintf(propname, "init_on");
- } else {
- table = ldconf->init_off;
- max_len = LDIM_INIT_OFF_MAX;
- sprintf(propname, "init_off");
- }
- if (table == NULL) {
- LDIMERR("%s init_table is null\n", propname);
- return 0;
- }
-
- propdata = (char *)fdt_getprop(dt_blob, nodeoffset, propname, NULL);
- if (propdata == NULL) {
- LDIMERR("%s: get %s failed\n", ldconf->name, propname);
- table[0] = LCD_EXT_CMD_TYPE_END;
- table[1] = 0;
- return -1;
- }
-
- while ((i + 1) < max_len) {
- table[i] = (unsigned char)(be32_to_cpup((((u32*)propdata)+i)));
- table[i+1] = (unsigned char)(be32_to_cpup((((u32*)propdata)+i+1)));
- type = table[i];
- cmd_size = table[i+1];
- if (type == LCD_EXT_CMD_TYPE_END)
- break;
- if (cmd_size == 0)
- goto init_table_dynamic_dts_next;
- if ((i + 2 + cmd_size) > max_len) {
- LDIMERR("%s: %s cmd_size out of support\n", ldconf->name, propname);
- table[i] = LCD_EXT_CMD_TYPE_END;
- table[i+1] = 0;
- return -1;
- }
- for (j = 0; j < cmd_size; j++)
- table[i+2+j] = (unsigned char)(be32_to_cpup((((u32*)propdata)+i+2+j)));
-
-init_table_dynamic_dts_next:
- i += (cmd_size + 2);
- }
- if (flag)
- ldconf->init_on_cnt = i + 2;
- else
- ldconf->init_off_cnt = i + 2;
-
- return 0;
-}
-
-static int ldim_dev_init_table_fixed_size_load_dts(const void *dt_blob,
- int nodeoffset, struct ldim_dev_config_s *ldconf, int flag)
-{
- unsigned char cmd_size;
- int i = 0, j, max_len;
- unsigned char *table;
- char propname[20];
- char *propdata;
-
- cmd_size = ldconf->cmd_size;
- if (flag) {
- table = ldconf->init_on;
- max_len = LDIM_INIT_ON_MAX;
- sprintf(propname, "init_on");
- } else {
- table = ldconf->init_off;
- max_len = LDIM_INIT_OFF_MAX;
- sprintf(propname, "init_off");
- }
- if (table == NULL) {
- LDIMPR("%s init_table is null\n", propname);
- return 0;
- }
-
- propdata = (char *)fdt_getprop(dt_blob, nodeoffset, propname, NULL);
- if (propdata == NULL) {
- LDIMERR("%s: get %s failed\n", ldconf->name, propname);
- table[0] = LCD_EXT_CMD_TYPE_END;
- table[1] = 0;
- return -1;
- }
-
- while (i < max_len) {
- if ((i + cmd_size) > max_len) {
- LDIMERR("%s: %s cmd_size out of support\n", ldconf->name, propname);
- table[i] = LCD_EXT_CMD_TYPE_END;
- return -1;
- }
- for (j = 0; j < cmd_size; j++)
- table[i+j] = (unsigned char)(be32_to_cpup((((u32*)propdata)+i+j)));
-
- if (table[i] == LCD_EXT_CMD_TYPE_END)
- break;
-
- i += cmd_size;
- }
- if (flag)
- ldconf->init_on_cnt = i + cmd_size;
- else
- ldconf->init_off_cnt = i + cmd_size;
-
- return 0;
-}
-
-static int ldim_dev_get_config_from_dts(char *dt_addr, int index)
-{
- int parent_offset, child_offset;
- char propname[30];
- char *propdata;
- char *p;
- const char *str;
- int temp;
- struct bl_pwm_config_s *ld_pwm = &ldim_dev_config->pwm_config;
- struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
- int i, j;
- int ret = 0;
-
- strcpy(ldim_dev_config->name, "ldim_dev");
- memset(ldim_dev_config->init_on, 0, LDIM_INIT_ON_MAX);
- memset(ldim_dev_config->init_off, 0, LDIM_INIT_OFF_MAX);
- ldim_dev_config->init_on[0] = 0xff;
- ldim_dev_config->init_off[0] = 0xff;
-
- if (dt_addr == NULL) {
- LDIMERR("%s: dt_addr is NULL\n", __func__);
- return -1;
- }
-
- parent_offset = fdt_path_offset(dt_addr, "/local_dimming_device");
- if (parent_offset < 0) {
- parent_offset = fdt_path_offset(dt_addr, "/local_diming_device");
- if (parent_offset < 0) {
- LDIMERR("not find /local_dimming_device node: %s\n",
- fdt_strerror(parent_offset));
- return -1;
- }
- }
- propdata = (char *)fdt_getprop(dt_addr, parent_offset, "status", NULL);
- if (propdata == NULL) {
- LDIMERR("not find local_dimming_device status, default to disabled\n");
- return -1;
- } else {
- if (strncmp(propdata, "okay", 2)) {
- LDIMPR("local_dimming_device status disabled\n");
- return -1;
- }
- }
-
- /* init gpio */
- i = 0;
- propdata = (char *)fdt_getprop(dt_addr, parent_offset, "ldim_dev_gpio_names", NULL);
- if (propdata == NULL) {
- LDIMERR("failed to get ldim_dev_gpio_names\n");
- } else {
- p = propdata;
- while (i < BL_GPIO_NUM_MAX) {
- if (i > 0)
- p += strlen(p) + 1;
- str = p;
- if (strlen(str) == 0)
- break;
- ldim_gpio_probe(str, i);
- i++;
- }
- }
-
- /* get device config */
- sprintf(propname,"/local_dimming_device/ldim_dev_%d", index);
- child_offset = fdt_path_offset(dt_addr, propname);
- if (child_offset < 0) {
- sprintf(propname,"/local_diming_device/ldim_dev_%d", index);
- child_offset = fdt_path_offset(dt_addr, propname);
- if (child_offset < 0) {
- LDIMERR("not find %s node: %s\n",
- propname, fdt_strerror(child_offset));
- return -1;
- }
- }
-
- propdata = (char *)fdt_getprop(dt_addr, child_offset, "ldim_dev_name", NULL);
- if (propdata == NULL)
- LDIMERR("failed to get ldim_dev_name\n");
- else
- strcpy(ldim_dev_config->name, propdata);
- LDIMPR("get config: %s(%d)\n", ldim_dev_config->name, index);
-
- propdata = (char *)fdt_getprop(dt_addr, child_offset, "ldim_pwm_port", NULL);
- if (propdata == NULL) {
- LDIMERR("failed to get ldim_pwm_port\n");
- ld_pwm->pwm_port = BL_PWM_MAX;
- } else {
- ld_pwm->pwm_port = bl_pwm_str_to_pwm(propdata);
- }
- LDIMPR("pwm_port: %s(%u)\n", propdata, ld_pwm->pwm_port);
- if (ld_pwm->pwm_port < BL_PWM_MAX) {
- propdata = (char *)fdt_getprop(dt_addr, child_offset, "ldim_pwm_attr", NULL);
- if (propdata == NULL) {
- LDIMERR("failed to get ldim_pwm_attr\n");
- ld_pwm->pwm_method = BL_PWM_POSITIVE;
- if (ld_pwm->pwm_port == BL_PWM_VS)
- ld_pwm->pwm_freq = 1;
- else
- ld_pwm->pwm_freq = 60;
- ld_pwm->pwm_duty = 50;
- } else {
- ld_pwm->pwm_method = be32_to_cpup((u32*)propdata);
- ld_pwm->pwm_freq = be32_to_cpup((((u32*)propdata)+1));
- ld_pwm->pwm_duty = be32_to_cpup((((u32*)propdata)+2));
- }
- if (ld_pwm->pwm_port == BL_PWM_VS) {
- if (ld_pwm->pwm_freq > 4) {
- LDIMERR("pwm_vs wrong freq %d\n", ld_pwm->pwm_freq);
- ld_pwm->pwm_freq = BL_FREQ_VS_DEFAULT;
- }
- } else {
- if (ld_pwm->pwm_freq > XTAL_HALF_FREQ_HZ)
- ld_pwm->pwm_freq = XTAL_HALF_FREQ_HZ;
- }
- LDIMPR("get pwm pol = %d, freq = %d, duty = %d%%\n",
- ld_pwm->pwm_method, ld_pwm->pwm_freq, ld_pwm->pwm_duty);
- }
-
- propdata = (char *)fdt_getprop(dt_addr, child_offset, "en_gpio_on_off", NULL);
- if (propdata == NULL) {
- LDIMERR("failed to get en_gpio_on_off\n");
- } else {
- ldim_dev_config->en_gpio = be32_to_cpup((u32*)propdata);
- ldim_dev_config->en_gpio_on = be32_to_cpup((((u32*)propdata)+1));
- ldim_dev_config->en_gpio_off = be32_to_cpup((((u32*)propdata)+2));
- }
- if (lcd_debug_print_flag) {
- LDIMPR("en_gpio=%s(%d), en_gpio_on=%d, en_gpio_off=%d\n",
- ldim_dev_config->gpio_name[ldim_dev_config->en_gpio],
- ldim_dev_config->en_gpio, ldim_dev_config->en_gpio_on,
- ldim_dev_config->en_gpio_off);
- }
-
- propdata = (char *)fdt_getprop(dt_addr, child_offset, "dim_max_min", NULL);
- if (propdata == NULL) {
- LDIMERR("failed to get dim_max_min\n");
- } else {
- ldim_dev_config->dim_max = be32_to_cpup((u32*)propdata);
- ldim_dev_config->dim_min = be32_to_cpup((((u32*)propdata)+1));
- }
- if (lcd_debug_print_flag) {
- LDIMPR("dim_max=0x%03x, dim_min=0x%03x\n",
- ldim_dev_config->dim_max, ldim_dev_config->dim_min);
- }
-
- temp = ldim_drv->ldim_conf->row * ldim_drv->ldim_conf->col;
- ldim_dev_config->bl_regnum = (unsigned short)temp;
-
- propdata = (char *)fdt_getprop(dt_addr, child_offset, "type", NULL);
- if (propdata == NULL)
- LDIMERR("failed to get type\n");
- else {
- ldim_dev_config->type = be32_to_cpup((u32*)propdata);
- LDIMPR("type: %d\n", ldim_dev_config->type);
- }
-
- propdata = (char *)fdt_getprop(dt_addr, child_offset, "ldim_pwm_pinmux_sel", NULL);
- if (propdata == NULL)
- LDIMERR("failed to get ldim_pwm_name\n");
- else
- strcpy(ldim_dev_config->pinmux_name, propdata);
- LDIMPR("ldim_pwm_pinmux_sel: %s\n", ldim_dev_config->pinmux_name);
-
- if (ldim_dev_config->type >= LDIM_DEV_TYPE_MAX) {
- LDIMERR("type num is out of support\n");
- return -1;
- }
-
- switch (ldim_dev_config->type) {
- case LDIM_DEV_TYPE_SPI:
- ldim_drv->spi_info = &ldim_spi_info;
- /* get spi config */
- /*
- propdata = (char *)fdt_getprop(dt_addr, parent_offset, "spi_bus_num", NULL);
- if (propdata == NULL)
- LDIMERR("failed to get spi_bus_num\n");
- else
- ldim_spi_info.bus_num = be32_to_cpup((u32*)propdata);
- */
- ldim_spi_info.bus_num = 0; /* fix value */
- propdata = (char *)fdt_getprop(dt_addr, child_offset, "spi_chip_select", NULL);
- if (propdata == NULL)
- LDIMERR("failed to get spi_chip_select\n");
- else
- ldim_spi_info.chip_select = be32_to_cpup((u32*)propdata);
-
- propdata = (char *)fdt_getprop(dt_addr, child_offset, "spi_max_frequency", NULL);
- if (propdata == NULL)
- LDIMERR("failed to get spi_max_frequency\n");
- else
- ldim_spi_info.max_speed_hz = be32_to_cpup((u32*)propdata);
-
- propdata = (char *)fdt_getprop(dt_addr, child_offset, "spi_mode", NULL);
- if (propdata == NULL)
- LDIMERR("failed to get spi_mode\n");
- else
- ldim_spi_info.mode = be32_to_cpup((u32*)propdata);
-
- if (lcd_debug_print_flag) {
- LDIMPR("spi bus_num=%d, chip_select=%d, max_frequency=%d, mode=%d\n",
- ldim_spi_info.bus_num, ldim_spi_info.chip_select,
- ldim_spi_info.max_speed_hz, ldim_spi_info.mode);
- }
-
- propdata = (char *)fdt_getprop(dt_addr, child_offset, "spi_cs_delay", NULL);
- if (propdata == NULL) {
- LDIMERR("failed to get spi_cs_delay\n");
- } else {
- ldim_dev_config->cs_hold_delay = be32_to_cpup((u32*)propdata);
- ldim_dev_config->cs_clk_delay = be32_to_cpup((((u32*)propdata)+1));
- }
- if (lcd_debug_print_flag) {
- LDIMPR("cs_hold_delay=%dus, cs_clk_delay=%dus\n",
- ldim_dev_config->cs_hold_delay, ldim_dev_config->cs_clk_delay);
- }
-
- propdata = (char *)fdt_getprop(dt_addr, child_offset, "spi_write_check", NULL);
- if (propdata == NULL)
- LDIMERR("failed to get spi_write_check\n");
- else
- ldim_dev_config->write_check = (unsigned char)(be32_to_cpup((u32*)propdata));
- if (lcd_debug_print_flag)
- LDIMPR("write_check=%d\n", ldim_dev_config->write_check);
-
- /* get init_cmd */
- propdata = (char *)fdt_getprop(dt_addr, child_offset, "cmd_size", NULL);
- if (propdata == NULL) {
- LDIMPR("no cmd_size\n");
- ldim_dev_config->cmd_size = 0;
- } else {
- temp = be32_to_cpup((u32*)propdata);
- ldim_dev_config->cmd_size = (unsigned char)temp;
- }
- if (lcd_debug_print_flag)
- LDIMPR("cmd_size=%d\n", ldim_dev_config->cmd_size);
- if (ldim_dev_config->cmd_size == 0)
- break;
-
- if (ldim_dev_config->cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC) {
- ret = ldim_dev_init_table_dynamic_size_load_dts(
- dt_addr, child_offset, ldim_dev_config, 1);
- if (ret)
- break;
- ret = ldim_dev_init_table_dynamic_size_load_dts(
- dt_addr, child_offset, ldim_dev_config, 0);
- } else {
- ret = ldim_dev_init_table_fixed_size_load_dts(
- dt_addr, child_offset, ldim_dev_config, 1);
- if (ret)
- break;
- ret = ldim_dev_init_table_fixed_size_load_dts(
- dt_addr, child_offset, ldim_dev_config, 0);
- }
- if (ret == 0)
- ldim_dev_config->init_loaded = 1;
- break;
- case LDIM_DEV_TYPE_I2C:
- break;
- case LDIM_DEV_TYPE_NORMAL:
- default:
- break;
- }
-
- /* pinmux */
- ret = ldim_pinmux_load_from_bsp(ldim_drv->ldev_conf);
-
- return ret;
-}
-
-static int ldim_dev_add_driver(struct aml_ldim_driver_s *ldim_drv)
-{
- struct ldim_dev_config_s *ldev_conf = ldim_drv->ldev_conf;
- int index = ldim_drv->dev_index;
- int ret = -1;
-
- switch (ldev_conf->type) {
- case LDIM_DEV_TYPE_SPI:
- ret = ldim_spi_driver_add(ldim_drv);
- break;
- case LDIM_DEV_TYPE_I2C:
- break;
- case LDIM_DEV_TYPE_NORMAL:
- default:
- break;
- }
- if (ret)
- return -1;
-
- ret = -1;
- if (strcmp(ldev_conf->name, "global") == 0) {
-#ifdef CONFIG_AML_LOCAL_DIMMING_GLOBAL
- ret = ldim_dev_global_probe(ldim_drv);
-#endif
- } else if (strcmp(ldev_conf->name, "iw7027") == 0) {
-#ifdef CONFIG_AML_LOCAL_DIMMING_IW7027
- ret = ldim_dev_iw7027_probe(ldim_drv);
-#endif
- } else if (strcmp(ldev_conf->name, "ob3350") == 0) {
-#ifdef CONFIG_AML_LOCAL_DIMMING_OB3350
- ret = ldim_dev_ob3350_probe(ldim_drv);
-#endif
- } else {
- LDIMERR("invalid device name: %s\n", ldev_conf->name);
- }
-
- if (ret) {
- LDIMERR("add device driver failed: %s(%d)\n",
- ldev_conf->name, index);
- } else {
- ldim_dev_probe_flag = 1;
- LDIMPR("add device driver: %s(%d)\n", ldev_conf->name, index);
- }
-
- return ret;
-}
-
-static int ldim_dev_remove_driver(struct aml_ldim_driver_s *ldim_drv)
-{
- struct ldim_dev_config_s *ldev_conf = ldim_drv->ldev_conf;
- int index = ldim_drv->dev_index;
- int ret = -1;
-
- if (ldim_dev_probe_flag == 0)
- return 0;
-
- if (strcmp(ldev_conf->name, "global") == 0) {
-#ifdef CONFIG_AML_LOCAL_DIMMING_GLOBAL
- ret = ldim_dev_global_remove(ldim_drv);
-#endif
- } else if (strcmp(ldev_conf->name, "iw7027") == 0) {
-#ifdef CONFIG_AML_LOCAL_DIMMING_IW7027
- ret = ldim_dev_iw7027_remove(ldim_drv);
-#endif
- } else if (strcmp(ldev_conf->name, "ob3350") == 0) {
-#ifdef CONFIG_AML_LOCAL_DIMMING_OB3350
- ret = ldim_dev_ob3350_remove(ldim_drv);
-#endif
- } else {
- LDIMERR("invalid device name: %s\n", ldev_conf->name);
- ret = -1;
- }
-
- if (ret) {
- LDIMERR("remove device driver failed: %s(%d)\n",
- ldev_conf->name, index);
- } else {
- LDIMPR("remove device driver: %s(%d)\n", ldev_conf->name, index);
- }
-
- return ret;
-}
-
-int aml_ldim_device_probe(char *dt_addr)
-{
- struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
- int ret = 0;
-
- if (lcd_debug_print_flag)
- LDIMPR("%s\n", __func__);
-
- ldim_dev_probe_flag = 0;
-
- /* get configs */
- ldim_dev_config = &ldim_config_dft;
- ldim_drv->ldev_conf = ldim_dev_config;
- ldim_drv->pinmux_ctrl = ldim_pwm_pinmux_ctrl;
- ldim_drv->device_config_print = ldim_device_config_print;
-
- ret = ldim_dev_get_config_from_dts(dt_addr, ldim_drv->dev_index);
- if (ret)
- return -1;
-
- /* add device driver */
- ret = ldim_dev_add_driver(ldim_drv);
-
- return ret;
-}
-
-int aml_ldim_device_remove(void)
-{
- struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
- int ret = 0;
-
- ldim_dev_remove_driver(ldim_drv);
-
- return ret;
-}
-
diff --git a/drivers/amlogic/media/vout/lcd/bl_ldim/ldim_dev_drv.h b/drivers/amlogic/media/vout/lcd/bl_ldim/ldim_dev_drv.h
deleted file mode 100644
index 13c9562..0000000
--- a/drivers/amlogic/media/vout/lcd/bl_ldim/ldim_dev_drv.h
+++ /dev/null
@@ -1,53 +0,0 @@
-
-/*
- * drivers/amlogic/media/vout/lcd/bl_ldim/ldim_dev_drv.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#ifndef __LDIM_DEV_DRV_H
-#define __LDIM_DEV_DRV_H
-#include <spi.h>
-#include <amlogic/media/vout/lcd/bl_ldim.h>
-
-extern void ldim_gpio_set(int index, int value);
-extern unsigned int ldim_gpio_input_get(int index);
-extern void ldim_set_duty_pwm(struct bl_pwm_config_s *bl);
-
-extern int ldim_spi_write(struct spi_slave *spi, unsigned char *tbuf, int tlen);
-extern int ldim_spi_read(struct spi_slave *spi, unsigned char *tbuf, int tlen,
- unsigned char *rbuf, int rlen);
-extern int ldim_spi_driver_add(struct aml_ldim_driver_s *ldim_drv);
-extern int ldim_spi_driver_remove(struct aml_ldim_driver_s *ldim_drv);
-
-/* ldim device probe function */
-#ifdef CONFIG_AML_LOCAL_DIMMING_GLOBAL
-extern int ldim_dev_global_probe(struct aml_ldim_driver_s *ldim_drv);
-extern int ldim_dev_global_remove(struct aml_ldim_driver_s *ldim_drv);
-#endif
-
-#ifdef CONFIG_AML_LOCAL_DIMMING_IW7027
-extern int ldim_dev_iw7027_probe(struct aml_ldim_driver_s *ldim_drv);
-extern int ldim_dev_iw7027_remove(struct aml_ldim_driver_s *ldim_drv);
-#endif
-
-#ifdef CONFIG_AML_LOCAL_DIMMING_OB3350
-extern int ldim_dev_ob3350_probe(struct aml_ldim_driver_s *ldim_drv);
-extern int ldim_dev_ob3350_remove(struct aml_ldim_driver_s *ldim_drv);
-#endif
-
-#endif
diff --git a/drivers/amlogic/media/vout/lcd/bl_ldim/ldim_drv.c b/drivers/amlogic/media/vout/lcd/bl_ldim/ldim_drv.c
deleted file mode 100644
index 76ac282..0000000
--- a/drivers/amlogic/media/vout/lcd/bl_ldim/ldim_drv.c
+++ /dev/null
@@ -1,248 +0,0 @@
-/*
- * drivers/amlogic/media/vout/lcd/bl_ldim/ldim_drv.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/arch/gpio.h>
-#include <fdtdec.h>
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#include <amlogic/media/vout/lcd/bl_ldim.h>
-#include "../lcd_reg.h"
-#include "../lcd_common.h"
-#include "ldim_drv.h"
-
-#define LD_DATA_MIN 10
-#define LDIM_BRI_LEVEL_MAX 0xfff
-#define LDIM_BRI_LEVEL_MIN 0x7f
-static unsigned int ldim_blk_row = 1;
-static unsigned int ldim_blk_col = 8;
-static struct aml_ldim_driver_s ldim_driver;
-
-static int ldim_on_flag;
-static int ldim_level;
-static int ldim_set_level(unsigned int level);
-
-static struct ldim_config_s ldim_config = {
- .row = 1,
- .col = 1,
-};
-
-static int ldim_power_on(void)
-{
- if (ldim_driver.device_power_on)
- ldim_driver.device_power_on();
- else
- LDIMERR("%s: device_power_on is null\n", __func__);
- ldim_on_flag = 1;
-
- if (ldim_level > 0)
- ldim_set_level(ldim_level);
-
- return 0;
-}
-static int ldim_power_off(void)
-{
- ldim_on_flag = 0;
- if (ldim_driver.device_power_off)
- ldim_driver.device_power_off();
- else
- LDIMERR("%s: device_power_off is null\n", __func__);
-
- return 0;
-}
-
-static void ldim_brightness_update(unsigned int level)
-{
- unsigned int size;
- unsigned int i;
-
- size = ldim_blk_row * ldim_blk_col;
- for (i = 0; i < size; i++)
- ldim_driver.ldim_matrix_buf[i] = (unsigned short)level;
-
- if (ldim_driver.device_bri_update)
- ldim_driver.device_bri_update(ldim_driver.ldim_matrix_buf, size);
- else
- LDIMPR("%s: device_bri_update is null\n", __func__);
-}
-
-static int ldim_set_level(unsigned int level)
-{
- int ret = 0;
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- unsigned int level_max, level_min;
-
- ldim_level = level;
- if (ldim_on_flag == 0)
- return 0;
-
- level_max = lcd_drv->bl_config->level_max;
- level_min = lcd_drv->bl_config->level_min;
-
- level = ((level - level_min) * (LD_DATA_MAX - LD_DATA_MIN)) /
- (level_max - level_min) + LD_DATA_MIN;
- level &= 0xfff;
- ldim_brightness_update(level);
-
- return ret;
-}
-
-static void ldim_config_print(void)
-{
- LDIMPR("%s:\n", __func__);
- printf("valid_flag = %d\n"
- "dev_index = %d\n"
- "ldim_blk_row = %d\n"
- "ldim_blk_col = %d\n"
- "ldim_on_flag = %d\n",
- ldim_driver.valid_flag,
- ldim_driver.dev_index,
- ldim_blk_row,
- ldim_blk_col,
- ldim_on_flag);
- if (ldim_driver.device_config_print)
- ldim_driver.device_config_print();
-}
-
-static struct aml_ldim_driver_s ldim_driver = {
- .valid_flag = 0, /* default invalid, active when bl_ctrl_method=ldim */
- .dev_index = 0,
- .ldim_conf = &ldim_config,
- .ldev_conf = NULL,
- .ldim_matrix_buf = NULL,
- .power_on = ldim_power_on,
- .power_off = ldim_power_off,
- .set_level = ldim_set_level,
- .config_print = ldim_config_print,
- .pinmux_ctrl = NULL,
- .device_config_print = NULL,
- .device_power_on = NULL,
- .device_power_off = NULL,
- .device_bri_update = NULL,
-};
-
-struct aml_ldim_driver_s *aml_ldim_get_driver(void)
-{
- return &ldim_driver;
-}
-
-int ldim_config_load_from_dts(char *dt_addr, int child_offset)
-{
- char *propdata;
-
- if (child_offset < 0) {
- LDIMERR("not find backlight node %s\n", fdt_strerror(child_offset));
- return -1;
- }
-
- propdata = (char *)fdt_getprop(dt_addr, child_offset, "bl_ldim_region_row_col", NULL);
- if (propdata == NULL) {
- LDIMERR("failed to get bl_ldim_region_row_col\n");
- ldim_blk_row = 1;
- ldim_blk_col = 1;
- } else {
- ldim_blk_row = be32_to_cpup((u32*)propdata);
- ldim_blk_col = be32_to_cpup((((u32*)propdata)+1));
- ldim_config.row = ldim_blk_row;
- ldim_config.col = ldim_blk_col;
- }
- LDIMPR("get region row = %d, col = %d\n", ldim_blk_row, ldim_blk_col);
-
- propdata = (char *)fdt_getprop(dt_addr, child_offset, "ldim_dev_index", NULL);
- if (propdata == NULL) {
- LDIMERR("failed to get ldim_dev_index\n");
- ldim_driver.dev_index = 0xff;
- } else {
- ldim_driver.dev_index = be32_to_cpup((u32*)propdata);
- }
- LDIMPR("get dev_index = %d\n", ldim_driver.dev_index);
-
- return 0;
-}
-
-int ldim_config_load_from_unifykey(unsigned char *para)
-{
- unsigned char *p;
-
- if (para == NULL) {
- LDIMERR("backlight unifykey buf is NULL\n");
- return -1;
- }
-
- p = para;
-
- /* ldim: 24byte */
- /* get bl_ldim_region_row_col 4byte*/
- ldim_blk_row = *(p + LCD_UKEY_BL_LDIM_ROW);
- ldim_blk_col = *(p + LCD_UKEY_BL_LDIM_COL);
- ldim_config.row = ldim_blk_row;
- ldim_config.col = ldim_blk_col;
- LDIMPR("get region row = %d, col = %d\n", ldim_blk_row, ldim_blk_col);
-
- /* get ldim_dev_index 1byte*/
- ldim_driver.dev_index = *(p + LCD_UKEY_BL_LDIM_DEV_INDEX);
- LDIMPR("get dev_index = %d\n", ldim_driver.dev_index);
-
- return 0;
-}
-
-int aml_ldim_probe(char *dt_addr, int flag)
-{
- unsigned int size;
- int ret = -1;
-
- ldim_on_flag = 0;
- ldim_level = 0;
-
- switch (flag) {
- case 0: /* dts */
- case 2: /* unifykey */
- if (dt_addr) {
- if (lcd_debug_print_flag)
- LDIMPR("load ldim_dev_config from dts\n");
- ret = aml_ldim_device_probe(dt_addr);
- }
- break;
- case 1: /* bsp */
- LDIMPR("%s: not support bsp config\n", __func__);
- break;
- default:
- break;
- }
-
- if (ret) {
- LDIMERR("%s failed\n", __func__);
- return ret;
- }
-
- size = ldim_blk_row * ldim_blk_col;
- ldim_driver.ldim_matrix_buf = (unsigned short *)malloc(sizeof(unsigned short) * size);
- if (ldim_driver.ldim_matrix_buf == NULL) {
- LDIMERR("ldim_matrix_buf malloc error\n");
- return -1;
- }
-
- ldim_driver.valid_flag = 1;
-
- LDIMPR("%s is ok\n", __func__);
-
- return ret;
-}
-
diff --git a/drivers/amlogic/media/vout/lcd/bl_ldim/ldim_drv.h b/drivers/amlogic/media/vout/lcd/bl_ldim/ldim_drv.h
deleted file mode 100644
index ea040b1..0000000
--- a/drivers/amlogic/media/vout/lcd/bl_ldim/ldim_drv.h
+++ /dev/null
@@ -1,39 +0,0 @@
-
-/*
- * drivers/amlogic/media/vout/lcd/bl_ldim/ldim_drv.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#ifndef __AML_LDIM_DRV_H__
-#define __AML_LDIM_DRV_H__
-#include <asm/arch/io.h>
-#include <amlogic/media/vout/lcd/lcd_vout.h>
-
-#define LDIMPR(fmt, args...) printf("ldim: "fmt"", ## args)
-#define LDIMERR(fmt, args...) printf("ldim: error: "fmt"", ## args)
-
-#define LD_DATA_DEPTH 12
-#define LD_DATA_MAX 0xfff
-
-extern void bl_pwm_ctrl(struct bl_pwm_config_s *bl_pwm, int status);
-extern enum bl_pwm_port_e bl_pwm_str_to_pwm(const char *str);
-
-/* ldim device probe function */
-extern int aml_ldim_device_probe(char *dt_addr);
-
-#endif
diff --git a/drivers/amlogic/media/vout/lcd/bl_ldim/ldim_spi.c b/drivers/amlogic/media/vout/lcd/bl_ldim/ldim_spi.c
deleted file mode 100644
index 8a304a8..0000000
--- a/drivers/amlogic/media/vout/lcd/bl_ldim/ldim_spi.c
+++ /dev/null
@@ -1,162 +0,0 @@
-/*
- * drivers/amlogic/media/vout/lcd/bl_ldim/ldim_spi.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <spi.h>
-#include <asm/arch/gpio.h>
-#include <fdtdec.h>
-#include <amlogic/media/vout/lcd/bl_ldim.h>
-#include "../lcd_common.h"
-#include "ldim_drv.h"
-#include "ldim_dev_drv.h"
-
-#ifdef CONFIG_DM_SPI
-
-static unsigned int cs_hold_delay;
-static unsigned int cs_clk_delay;
-
-int ldim_spi_write(struct spi_slave *spi, unsigned char *tbuf, int tlen)
-{
- int ret, size;
-
- ret = spi_claim_bus(spi);
- if (ret) {
- LDIMERR("%s: request spi bus failed\n", __func__);
- goto wreg_end;
- }
-
- if (cs_hold_delay)
- udelay(cs_hold_delay);
- spi_cs_activate(spi);
- if (cs_clk_delay)
- udelay(cs_clk_delay);
- size = tlen * 8;
- ret = spi_xfer(spi, size, tbuf, NULL, 0);
- if (cs_clk_delay)
- udelay(cs_clk_delay);
- spi_cs_deactivate(spi);
-
-wreg_end:
- spi_release_bus(spi);
- return ret;
-}
-
-int ldim_spi_read(struct spi_slave *spi, unsigned char *tbuf, int tlen,
- unsigned char *rbuf, int rlen)
-{
- int ret, size;
-
- ret = spi_claim_bus(spi);
- if (ret) {
- LDIMERR("%s: request spi bus failed\n", __func__);
- goto rreg_end;
- }
-
- if (cs_hold_delay)
- udelay(cs_hold_delay);
- spi_cs_activate(spi);
- if (cs_clk_delay)
- udelay(cs_clk_delay);
- size = (tlen + rlen) * 8;
- ret = spi_xfer(spi, size, tbuf, rbuf, 0);
- if (ret)
- goto rreg_end;
- if (cs_clk_delay)
- udelay(cs_clk_delay);
- spi_cs_deactivate(spi);
-
-rreg_end:
- spi_release_bus(spi);
- return ret;
-}
-
-int ldim_spi_driver_add(struct aml_ldim_driver_s *ldim_drv)
-{
- struct udevice *dev;
- int ret;
-
- if (ldim_drv->spi_info == NULL) {
- LDIMERR("%s: spi_info is null\n", __func__);
- return -1;
- }
-
- /* register spi */
- snprintf(ldim_drv->spi_info->spi_name, LDIM_SPI_NAME_MAX,
- "generic_%d:%d",
- ldim_drv->spi_info->bus_num,
- ldim_drv->spi_info->chip_select);
- ret = spi_get_bus_and_cs(ldim_drv->spi_info->bus_num,
- ldim_drv->spi_info->chip_select,
- ldim_drv->spi_info->max_speed_hz,
- ldim_drv->spi_info->mode,
- "spi_generic_drv",
- ldim_drv->spi_info->spi_name,
- &dev, &ldim_drv->spi_info->spi);
- if (ret) {
- LDIMERR("%s: register spi driver failed\n", __func__);
- return -1;
- }
- ldim_drv->spi_info->spi->wordlen = ldim_drv->spi_info->wordlen;
- cs_hold_delay = ldim_drv->ldev_conf->cs_hold_delay;
- cs_clk_delay = ldim_drv->ldev_conf->cs_clk_delay;
-
- spi_cs_deactivate(ldim_drv->spi_info->spi);
-
- return 0;
-}
-
-int ldim_spi_driver_remove(struct aml_ldim_driver_s *ldim_drv)
-{
- if (ldim_drv->spi_info)
- ldim_drv->spi_info->spi = NULL;
-
- return 0;
-}
-
-#else
-int ldim_spi_write(struct spi_slave *spi, unsigned char *tbuf, int tlen)
-{
- LDIMERR("%s: no AML_SPICC support\n", __func__);
-
- return -1;
-}
-
-int ldim_spi_read(struct spi_slave *spi, unsigned char *tbuf, int tlen,
- unsigned char *rbuf, int rlen)
-{
- LDIMERR("%s: no AML_SPICC support\n", __func__);
-
- return -1;
-}
-
-int ldim_spi_driver_add(struct aml_ldim_driver_s *ldim_drv)
-{
- LDIMERR("%s: no AML_SPICC support\n", __func__);
-
- return -1;
-}
-
-int ldim_spi_driver_remove(struct aml_ldim_driver_s *ldim_drv)
-{
- return 0;
-}
-#endif
-
diff --git a/drivers/amlogic/media/vout/lcd/bl_ldim/ob3350.c b/drivers/amlogic/media/vout/lcd/bl_ldim/ob3350.c
deleted file mode 100644
index 53a12ef..0000000
--- a/drivers/amlogic/media/vout/lcd/bl_ldim/ob3350.c
+++ /dev/null
@@ -1,138 +0,0 @@
-/*
- * drivers/amlogic/media/vout/lcd/bl_ldim/ob3350_bl.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/arch/gpio.h>
-#include <fdtdec.h>
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#include <amlogic/media/vout/lcd/bl_ldim.h>
-#include "../lcd_reg.h"
-#include "../lcd_common.h"
-#include "ldim_drv.h"
-#include "ldim_dev_drv.h"
-
-static int ob3350_on_flag;
-
-static int ob3350_hw_init_on(void)
-{
- struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
-
- ldim_gpio_set(ldim_drv->ldev_conf->en_gpio, ldim_drv->ldev_conf->en_gpio_on);
- mdelay(2);
- ldim_drv->pinmux_ctrl(1);
- mdelay(20);
-
- return 0;
-}
-
-static int ob3350_hw_init_off(void)
-{
- struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
-
- ldim_drv->pinmux_ctrl(0);
- ldim_gpio_set(ldim_drv->ldev_conf->en_gpio, ldim_drv->ldev_conf->en_gpio_off);
-
- return 0;
-}
-
-static unsigned int ob3350_get_value(unsigned int level)
-{
- struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
-
- unsigned int val;
- unsigned int dim_max, dim_min;
-
- dim_max = ldim_drv->ldev_conf->dim_max;
- dim_min = ldim_drv->ldev_conf->dim_min;
-
- val = dim_min + ((level * (dim_max - dim_min)) / LD_DATA_MAX);
-
- return val;
-}
-
-static int ob3350_smr(unsigned short *buf, unsigned char len)
-{
- struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
- unsigned short val;
-
- val = ob3350_get_value(buf[0]);
- ldim_drv->ldev_conf->pwm_config.pwm_duty = val;
-
- if (ob3350_on_flag == 0) {
- if (lcd_debug_print_flag)
- LDIMPR("%s: on_flag=%d\n", __func__, ob3350_on_flag);
- return 0;
- }
-
- if (len != 1) {
- LDIMERR("%s: data len %d invalid\n", __func__, len);
- return -1;
- }
-
- ldim_set_duty_pwm(&(ldim_drv->ldev_conf->pwm_config));
-
- return 0;
-}
-
-static int ob3350_power_on(void)
-{
- struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
-
- ob3350_hw_init_on();
- ob3350_on_flag = 1;
- /* init brightness level */
- ldim_set_duty_pwm(&(ldim_drv->ldev_conf->pwm_config));
-
- LDIMPR("%s: ok\n", __func__);
- return 0;
-}
-
-static int ob3350_power_off(void)
-{
- ob3350_on_flag = 0;
- ob3350_hw_init_off();
-
- LDIMPR("%s: ok\n", __func__);
- return 0;
-}
-
-static int ob3350_ldim_driver_update(struct aml_ldim_driver_s *ldim_drv)
-{
- ldim_drv->device_power_on = ob3350_power_on;
- ldim_drv->device_power_off = ob3350_power_off;
- ldim_drv->device_bri_update = ob3350_smr;
-
- return 0;
-}
-
-int ldim_dev_ob3350_probe(struct aml_ldim_driver_s *ldim_drv)
-{
- ob3350_on_flag = 0;
- ob3350_ldim_driver_update(ldim_drv);
-
- return 0;
-}
-
-int ldim_dev_ob3350_remove(struct aml_ldim_driver_s *ldim_drv)
-{
- return 0;
-}
-
diff --git a/drivers/amlogic/media/vout/lcd/edp_tx_reg.h b/drivers/amlogic/media/vout/lcd/edp_tx_reg.h
new file mode 100644
index 0000000..068a855
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/edp_tx_reg.h
@@ -0,0 +1,183 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef EDP_TX_REG_H
+#define EDP_TX_REG_H
+
+#define EDP_TX_LINK_BW_SET 0x0000
+#define EDP_TX_LINK_COUNT_SET 0x0004
+#define EDP_TX_ENHANCED_FRAME_EN 0x0008
+#define EDP_TX_TRAINING_PATTERN_SET 0x000c
+#define EDP_TX_LINK_QUAL_PATTERN_SET 0x0010
+#define EDP_TX_SCRAMBLING_DISABLE 0x0014
+#define EDP_TX_DOWNSPREAD_CTRL 0x0018
+#define EDP_TX_ALTERNATE_SCRAMBLER_RESET 0x001c
+#define EDP_TX_PANEL_SELF_REFRESH 0x0020
+
+#define EDP_TX_TRANSMITTER_OUTPUT_ENABLE 0x0080
+#define EDP_TX_MAIN_STREAM_ENABLE 0x0084
+#define EDP_TX_SECONDARY_STREAM_ENABLE 0x0088
+#define EDP_TX_FORCE_SCRAMBLER_RESET 0x00c0
+#define EDP_TX_USER_CONTROL_STATUS 0x00c4
+
+#define EDP_TX_CORE_CAPBILITIES 0x00f8
+#define EDP_TX_CORE_ID 0x00fc
+
+#define EDP_TX_AUX_COMMAND 0x0100
+#define EDP_TX_AUX_WRITE_FIFO 0x0104
+#define EDP_TX_AUX_ADDRESS 0x0108
+#define EDP_TX_AUX_CLOCK_DIVIDER 0x010c
+#define EDP_TX_AUX_STATE 0x0130
+#define EDP_TX_AUX_REPLY_DATA 0x0134
+#define EDP_TX_AUX_REPLY_CODE 0x0138
+#define EDP_TX_AUX_REPLY_COUNT 0x013c
+#define EDP_TX_AUX_INTERRUPT_STATUS 0x0140
+#define EDP_TX_AUX_INTERRUPT_MASK 0x0144
+#define EDP_TX_AUX_REPLY_DATA_COUNT 0x0148
+#define EDP_TX_AUX_TRANSFER_STATUS 0x014c
+#define EDP_TX_AUX_REPLY_CLOCK_WIDTH 0x0150
+
+#define EDP_TX_MAIN_STREAM_HTOTAL 0x0180
+#define EDP_TX_MAIN_STREAM_VTOTAL 0x0184
+#define EDP_TX_MAIN_STREAM_POLARITY 0x0188
+#define EDP_TX_MAIN_STREAM_HSWIDTH 0x018c
+#define EDP_TX_MAIN_STREAM_VSWIDTH 0x0190
+#define EDP_TX_MAIN_STREAM_HRES 0x0194
+#define EDP_TX_MAIN_STREAM_VRES 0x0198
+#define EDP_TX_MAIN_STREAM_HSTART 0x019c
+#define EDP_TX_MAIN_STREAM_VSTART 0x01a0
+#define EDP_TX_MAIN_STREAM_MISC0 0x01a4
+#define EDP_TX_MAIN_STREAM_MISC1 0x01a8
+#define EDP_TX_MAIN_STREAM_M_VID 0x01ac
+#define EDP_TX_MAIN_STREAM_TRANSFER_UNIT_SIZE 0x01b0
+#define EDP_TX_MAIN_STREAM_N_VID 0x01b4
+#define EDP_TX_MAIN_STREAM_USER_PIXEL_WIDTH 0x01b8
+#define EDP_TX_MAIN_STREAM_DATA_COUNT_PER_LANE 0x01bc
+#define EDP_TX_MAIN_STREAM_INTERLACED 0x01c0
+#define EDP_TX_MAIN_STREAM_USER_SYNC_POLARITY 0x01c4
+
+#define EDP_TX_PHY_RESET 0x0200
+#define EDP_TX_PHY_PRE_EMPHASIS_LANE_0 0x0210
+#define EDP_TX_PHY_PRE_EMPHASIS_LANE_1 0x0214
+#define EDP_TX_PHY_PRE_EMPHASIS_LANE_2 0x0218
+#define EDP_TX_PHY_PRE_EMPHASIS_LANE_3 0x021c
+#define EDP_TX_PHY_VOLTAGE_DIFF_LANE_0 0x0220
+#define EDP_TX_PHY_VOLTAGE_DIFF_LANE_1 0x0224
+#define EDP_TX_PHY_VOLTAGE_DIFF_LANE_2 0x0228
+#define EDP_TX_PHY_VOLTAGE_DIFF_LANE_3 0x022c
+#define EDP_TX_PHY_TRANSMIT_PRBS7 0x0230
+#define EDP_TX_PHY_POWER_DOWN 0x0238
+#define EDP_TX_PHY_POST_EMPHASIS_LANE_0 0x0240
+#define EDP_TX_PHY_POST_EMPHASIS_LANE_1 0x0244
+#define EDP_TX_PHY_POST_EMPHASIS_LANE_2 0x024c
+#define EDP_TX_PHY_POST_EMPHASIS_LANE_3 0x024c
+#define EDP_TX_PHY_STATUS 0x0280
+
+#define EDP_TX_HDCP_ENABLE 0x0400
+#define EDP_TX_HDCP_KM_LOWER 0x0410
+#define EDP_TX_HDCP_KM_UPPER 0x0414
+#define EDP_TX_HDCP_AN_LOWER 0x0418
+#define EDP_TX_HDCP_AN_UPPER 0x041c
+#define EDP_TX_HDCP_AUTO_AN_VALUE_LOWER 0x0420
+#define EDP_TX_HDCP_AUTO_AN_VALUE_UPPER 0x0424
+#define EDP_TX_HDCP_STATUS 0x0428
+
+
+//***************************************************************************************************//
+//******note: below address are not eDP Tx core register's, but eDP sink device DPCD register's******//
+//***************************************************************************************************//
+//AUX offset address
+//DPCD information
+//***************************************************************************************************//
+#define EDP_DPCD_REVISION 0x0000
+#define EDP_DPCD_MAX_LINK_RATE 0x0001
+#define EDP_DPCD_MAX_LANE_COUNT 0x0002
+#define EDP_DPCD_MAX_DOWNSPREAD 0x0003
+#define EDP_DPCD_NUM_RX_PORTS 0x0004
+#define EDP_DPCD_DOWNSTREAM_PORTS_PRESENT 0x0005
+#define EDP_DPCD_MAIN_LINK_CODING 0x0006
+#define EDP_DPCD_NUM_DOWNSTREAM_PORTS 0x0007
+#define EDP_DPCD_RX_PORT0_CAPS_0 0x0008
+#define EDP_DPCD_RX_PORT0_CAPS_1 0x0009
+#define EDP_DPCD_RX_PORT1_CAPS_0 0x000A
+#define EDP_DPCD_RX_PORT1_CAPS_1 0x000B
+#define EDP_DPCD_I2C_SPEED_CAP 0x000C //v1.2?
+#define EDP_DPCD_CONFIGURATION_CAP 0x000D //v1.2?
+#define EDP_DPCD_TRAINING_AUX_RD_INTERVAL 0x000E //v1.2?
+#define EDP_DPCD_MUTI_STREAM_TRANSPORT_CAP 0x0021 //v1.2
+#define EDP_DPCD_PSR_SUPPORT 0x0070 //v1.2?
+#define EDP_DPCD_PSR_CAPS 0x0071 //v1.2?
+#define EDP_DPCD_DOWNSTREAM_PORT_CAPS 0x0080 // Downstream Port 0 - 15 Capabilities
+
+#define EDP_DPCD_LINK_BANDWIDTH_SET 0x0100
+#define EDP_DPCD_LANE_COUNT_SET 0x0101
+#define EDP_DPCD_TRAINING_PATTERN_SET 0x0102
+#define EDP_DPCD_TRAINING_LANE0_SET 0x0103
+#define EDP_DPCD_TRAINING_LANE1_SET 0x0104
+#define EDP_DPCD_TRAINING_LANE2_SET 0x0105
+#define EDP_DPCD_TRAINING_LANE3_SET 0x0106
+#define EDP_DPCD_DOWNSPREAD_CONTROL 0x0107
+#define EDP_DPCD_MAIN_LINK_CODING_SET 0x0108
+#define EDP_DPCD_CONFIGURATION_SET 0x010A
+
+#define EDP_DPCD_SINK_COUNT 0x0200
+#define EDP_DPCD_DEVICE_SERVICE_IRQ 0x0201
+#define EDP_DPCD_STATUS_LANE_0_1 0x0202
+#define EDP_DPCD_STATUS_LANE_2_3 0x0203
+#define EDP_DPCD_LANE_ALIGNMENT_STATUS_UPDATED 0x0204
+#define EDP_DPCD_SINK_STATUS 0x0205
+#define EDP_DPCD_ADJUST_REQUEST_LANE_0_1 0x0206
+#define EDP_DPCD_ADJUST_REQUEST_LANE_2_3 0x0207
+#define EDP_DPCD_TRAINING_SCORE_LANE_0 0x0208
+#define EDP_DPCD_TRAINING_SCORE_LANE_1 0x0209
+#define EDP_DPCD_TRAINING_SCORE_LANE_2 0x020A
+#define EDP_DPCD_TRAINING_SCORE_LANE_3 0x020B
+
+#define EDP_DPCD_SYMBOL_ERROR_COUNT_LANE_0 0x0210
+#define EDP_DPCD_SYMBOL_ERROR_COUNT_LANE_1 0x0212
+#define EDP_DPCD_SYMBOL_ERROR_COUNT_LANE_2 0x0214
+#define EDP_DPCD_SYMBOL_ERROR_COUNT_LANE_3 0x0216
+
+#define EDP_DPCD_TEST_REQUEST 0x0218
+#define EDP_DPCD_TEST_LINK_RATE 0x0219
+#define EDP_DPCD_TEST_LANE_COUNT 0x0220
+#define EDP_DPCD_TEST_PATTERN 0x0221
+#define EDP_DPCD_TEST_RESPONSE 0x0260
+#define EDP_DPCD_TEST_EDID_CHECKSUM 0x0261
+
+// Source Device-Specific Field 0x0303 - 0x003FF : Reserved for vendor-specific usage
+#define EDP_DPCD_SOURCE_IEEE_OUI_0 0x0300 // Source IEEE OUI 7:0
+#define EDP_DPCD_SOURCE_IEEE_OUI_1 0x0301 // Source IEEE OUI 15:8
+#define EDP_DPCD_SOURCE_IEEE_OUI_2 0x0302 // Source IEEE OUI 23:16
+
+// Sink Device-Specific Field 0x0403 - 0x004FF : Reserved for vendor-specific usage
+#define EDP_DPCD_SINK_IEEE_OUT_0 0x0400 // Sink IEEE OUI 7:0
+#define EDP_DPCD_SINK_IEEE_OUT_1 0x0401 // Sink IEEE OUI 15:8
+#define EDP_DPCD_SINK_IEEE_OUT_2 0x0402 // Sink IEEE OUI 23:16
+
+// Branch Device-Specific Field 0x0503 - 0x005FF : Reserved for vendor-specific usage
+#define EDP_DPCD_BRANCH_DEVICE_IEEE_OUI_0 0x0500 // Branch Device IEEE OUI 7:0
+#define EDP_DPCD_BRANCH_DEVICE_IEEE_OUI_1 0x0501 // Branch Device IEEE OUI 15:8
+#define EDP_DPCD_BRANCH_DEVICE_IEEE_OUI_2 0x0502 // Branch Device IEEE OUI 23:16
+#define EDP_DPCD_SET_POWER 0x0600 // Set Power
+
+//HDCP field in DPCD
+#define EDP_DPCD_HDCP_BKSV 0x68000
+#define EDP_DPCD_HDCP_ROPRIME 0x68005
+#define EDP_DPCD_HDCP_AKSV 0x68007
+#define EDP_DPCD_HDCP_AN 0x6800c
+#define EDP_DPCD_HDCP_VPRIME_H1 0x68014
+#define EDP_DPCD_HDCP_VPRIME_H2 0x68018
+#define EDP_DPCD_HDCP_VPRIME_H3 0x6801c
+#define EDP_DPCD_HDCP_VPRIME_H4 0x68020
+#define EDP_DPCD_HDCP_VPRIME_H5 0x68024
+#define EDP_DPCD_HDCP_BCAPS 0x68028
+#define EDP_DPCD_HDCP_BSTATUS 0x68029
+#define EDP_DPCD_HDCP_BINFO 0x6802a
+#define EDP_DPCD_HDCP_KSVFIFO 0x6802c
+#define EDP_DPCD_HDCP_RESERVED 0x6803b
+#define EDP_DPCD_HDCP_DEBUG 0x680c0
+
+#endif
\ No newline at end of file
diff --git a/drivers/amlogic/media/vout/lcd/lcd_bl.c b/drivers/amlogic/media/vout/lcd/lcd_bl.c
deleted file mode 100644
index c9cf3ba..0000000
--- a/drivers/amlogic/media/vout/lcd/lcd_bl.c
+++ /dev/null
@@ -1,2287 +0,0 @@
-/*
- * drivers/amlogic/media/vout/lcd/lcd_bl.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <dm.h>
-#include <asm/gpio.h>
-#include <fdtdec.h>
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#ifdef CONFIG_AML_LOCAL_DIMMING
-#include <amlogic/media/vout/lcd/bl_ldim.h>
-#endif
-#ifdef CONFIG_AML_BL_EXTERN
-#include <amlogic/media/vout/lcd/bl_extern.h>
-#endif
-#include "lcd_reg.h"
-#include "lcd_common.h"
-
-static unsigned int bl_off_policy;
-static unsigned int bl_status;
-
-static struct bl_config_s *bl_check_valid(void)
-{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- struct bl_config_s *bconf;
-#ifdef CONFIG_AML_BL_EXTERN
- struct aml_bl_extern_driver_s *bl_ext;
-#endif
-#ifdef CONFIG_AML_LOCAL_DIMMING
- struct aml_ldim_driver_s *ldim_drv;
-#endif
-
- bconf = lcd_drv->bl_config;
- switch (bconf->method) {
- case BL_CTRL_PWM:
- if (bconf->bl_pwm == NULL) {
- LCDERR("bl: no bl_pwm struct\n");
- bconf = NULL;
- }
- break;
- case BL_CTRL_PWM_COMBO:
- if (bconf->bl_pwm_combo0 == NULL) {
- LCDERR("bl: no bl_pwm_combo_0 struct\n");
- bconf = NULL;
- }
- if (bconf->bl_pwm_combo1 == NULL) {
- LCDERR("bl: no bl_pwm_combo_1 struct\n");
- bconf = NULL;
- }
- break;
- case BL_CTRL_GPIO:
- break;
-#ifdef CONFIG_AML_LOCAL_DIMMING
- case BL_CTRL_LOCAL_DIMMING:
- ldim_drv = aml_ldim_get_driver();
- if (ldim_drv == NULL) {
- LCDERR("bl: no ldim driver\n");
- bconf = NULL;
- }
- break;
-#endif
-#ifdef CONFIG_AML_BL_EXTERN
- case BL_CTRL_EXTERN:
- bl_ext = aml_bl_extern_get_driver();
- if (bl_ext == NULL) {
- LCDERR("bl: no bl_extern driver\n");
- bconf = NULL;
- }
- break;
-#endif
- default:
- if (lcd_debug_print_flag)
- LCDPR("bl: invalid control_method: %d\n", bconf->method);
- bconf = NULL;
- break;
- }
- return bconf;
-}
-
-/* ***************************************
- * bl gpio
- * *************************************** */
-static struct lcd_cpu_gpio_s bl_gpio[BL_GPIO_NUM_MAX] = {
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
-};
-
-static void bl_gpio_info_print(void)
-{
- int i;
-
- LCDPR("bl: gpio_info:\n");
- for (i = 0; i < BL_GPIO_NUM_MAX; i++) {
- if (strcmp(bl_gpio[i].name, "invalid") == 0)
- break;
- if (bl_gpio[i].probe_flag == 1) {
- printf("%d: %s, register=%d\n",
- i, bl_gpio[i].name, bl_gpio[i].register_flag);
- }
- }
- printf("\n");
-}
-
-static int bl_gpio_probe(const char *name, int index)
-{
- if (name == NULL) {
- LCDERR("bl: %s: gpio name is null\n", __func__);
- return -1;
- }
- if (index >= BL_GPIO_NUM_MAX) {
- LCDERR("bl: %s: invalid gpio: %d\n", __func__, index);
- return -1;
- }
- if (bl_gpio[index].probe_flag == 1) {
- if (lcd_debug_print_flag) {
- LCDPR("bl: gpio %s(%d) is already probed\n",
- bl_gpio[index].name, index);
- }
- return 0;
- }
-
- if (lcd_debug_print_flag)
- LCDPR("bl: probe gpio: %s(%d)\n", name, index);
- strcpy(bl_gpio[index].name, name);
- /* init gpio flag */
- bl_gpio[index].probe_flag = 1;
- bl_gpio[index].register_flag = 0;
-
- return 0;
-}
-
-static int bl_gpio_request(int index)
-{
- int ret = 0;
-
- if (index >= BL_GPIO_NUM_MAX) {
- LCDERR("bl: %s: invalid gpio: %d\n", __func__, index);
- return -1;
- }
- if (bl_gpio[index].probe_flag == 0) {
- LCDERR("bl: gpio %d is not probed\n", index);
- return -1;
- }
- if (bl_gpio[index].register_flag == 1) {
- if (lcd_debug_print_flag) {
- LCDPR("bl: gpio %s(%d) is already registered\n",
- bl_gpio[index].name, index);
- }
- return 0;
- }
-
- ret = dm_gpio_lookup_name(bl_gpio[index].name, &bl_gpio[index].gpio);
- if (ret) {
- LCDERR("bl: lookup gpio: wrong name %s\n", bl_gpio[index].name);
- return -1;
- }
-
- ret = dm_gpio_request(&bl_gpio[index].gpio, "aml_lcd_bl");
- if (ret) {
- LCDERR("bl: request gpio %s(%d) failed\n", bl_gpio[index].name, index);
- return -1;
- }
-
- if (lcd_debug_print_flag)
- LCDPR("bl: request gpio: %s(%d)\n", bl_gpio[index].name, index);
- bl_gpio[index].register_flag = 1;
-
- return 0;
-}
-
-static int bl_gpio_set(int index, int value)
-{
- int ret = 0;
-
- if (index >= BL_GPIO_NUM_MAX) {
- LCDERR("bl: %s: invalid gpio: %d\n", __func__, index);
- return -1;
- }
- if (bl_gpio[index].register_flag == 0) {
- ret = bl_gpio_request(index);
- if (ret)
- return -1;
- }
-
- switch (value) {
- case LCD_GPIO_OUTPUT_LOW:
- ret = dm_gpio_set_dir_flags(&bl_gpio[index].gpio, GPIOD_IS_OUT);
- if (ret) {
- LCDERR("bl: set gpio %s(%d) direction failed\n",
- bl_gpio[index].name, index);
- return ret;
- }
- dm_gpio_set_value(&bl_gpio[index].gpio, 0);
- break;
- case LCD_GPIO_OUTPUT_HIGH:
- ret = dm_gpio_set_dir_flags(&bl_gpio[index].gpio, GPIOD_IS_OUT);
- if (ret) {
- LCDERR("bl: set gpio %s(%d) direction failed\n",
- bl_gpio[index].name, index);
- return ret;
- }
- dm_gpio_set_value(&bl_gpio[index].gpio, 1);
- break;
- case LCD_GPIO_INPUT:
- default:
- ret = dm_gpio_set_dir_flags(&bl_gpio[index].gpio, GPIOD_IS_IN);
- if (ret) {
- LCDERR("bl: set gpio %s(%d) direction failed\n",
- bl_gpio[index].name, index);
- return ret;
- }
- break;
- }
- if (lcd_debug_print_flag) {
- LCDPR("bl: gpio: %s(%d), value: %d\n",
- bl_gpio[index].name, index, value);
- }
-
- return 0;
-}
-/* *************************************** */
-
-static void bl_pwm_pinmux_clr_gpio_set(struct bl_pwm_config_s *bl_pwm, int gpio_level)
-{
- int i = 0;
-
- if (bl_pwm == NULL)
- return;
-
- if (lcd_debug_print_flag) {
- LCDPR("bl: %s: pwm_port=%d, pinmux_flag=%d\n",
- __func__, bl_pwm->pwm_port, bl_pwm->pinmux_flag);
- }
- if (bl_pwm->pinmux_flag > 0) {
- while (i < LCD_PINMUX_NUM) {
- if (bl_pwm->pinmux_set[i][0] == LCD_PINMUX_END)
- break;
- lcd_pinmux_clr_mask(bl_pwm->pinmux_set[i][0],
- bl_pwm->pinmux_set[i][1]);
- if (lcd_debug_print_flag) {
- LCDPR("bl: %s: port=%d, pinmux_clr=%d,0x%08x\n",
- __func__, bl_pwm->pwm_port,
- bl_pwm->pinmux_set[i][0], bl_pwm->pinmux_set[i][1]);
- }
- i++;
- }
- bl_pwm->pinmux_flag = 0;
- }
- /* set gpio */
- if (bl_pwm->pwm_gpio < BL_GPIO_NUM_MAX)
- bl_gpio_set(bl_pwm->pwm_gpio, gpio_level);
-}
-
-static void bl_pwm_pinmux_set_gpio_clr(struct bl_pwm_config_s *bl_pwm)
-{
- int i = 0;
-
- if (bl_pwm == NULL)
- return;
-
- if (lcd_debug_print_flag) {
- LCDPR("bl: %s: pwm_port=%d, pinmux_flag=%d\n",
- __func__, bl_pwm->pwm_port, bl_pwm->pinmux_flag);
- }
- if (bl_pwm->pinmux_flag > 0)
- return;
-
- /* set pinmux */
- while (i < LCD_PINMUX_NUM) {
- if (bl_pwm->pinmux_set[i][0] == LCD_PINMUX_END)
- break;
- lcd_pinmux_set_mask(bl_pwm->pinmux_set[i][0],
- bl_pwm->pinmux_set[i][1]);
- if (lcd_debug_print_flag) {
- LCDPR("bl: %s: port=%d, pinmux_set=%d,0x%08x\n",
- __func__, bl_pwm->pwm_port,
- bl_pwm->pinmux_set[i][0], bl_pwm->pinmux_set[i][1]);
- }
- i++;
- }
- bl_pwm->pinmux_flag = 1;
-}
-
-static void bl_set_pwm_gpio_check(struct bl_pwm_config_s *bl_pwm)
-{
- unsigned int gpio_level;
-
- /* pwm duty 100% or 0% special control */
- if (bl_pwm->pwm_duty_max > 100) {
- if ((bl_pwm->pwm_duty == 0) || (bl_pwm->pwm_duty == 255)) {
- switch (bl_pwm->pwm_method) {
- case BL_PWM_POSITIVE:
- if (bl_pwm->pwm_duty == 0)
- gpio_level = 0;
- else
- gpio_level = 1;
- break;
- case BL_PWM_NEGATIVE:
- if (bl_pwm->pwm_duty == 0)
- gpio_level = 1;
- else
- gpio_level = 0;
- break;
- default:
- LCDERR("bl: %s: port=%d: invalid pwm_method %d\n",
- __func__, bl_pwm->pwm_port, bl_pwm->pwm_method);
- gpio_level = 0;
- break;
- }
- if (lcd_debug_print_flag) {
- LCDPR("bl: %s: pwm port=%d, duty=%d%%, switch to gpio %d\n",
- __func__, bl_pwm->pwm_port, bl_pwm->pwm_duty*100/255, gpio_level);
- }
- bl_pwm_pinmux_clr_gpio_set(bl_pwm, gpio_level);
- } else {
- if (lcd_debug_print_flag) {
- LCDPR("bl: %s: pwm_port=%d set as pwm\n",
- __func__, bl_pwm->pwm_port);
- }
- bl_pwm_pinmux_set_gpio_clr(bl_pwm);
- }
- } else {
- if ((bl_pwm->pwm_duty == 0) || (bl_pwm->pwm_duty == 100)) {
- switch (bl_pwm->pwm_method) {
- case BL_PWM_POSITIVE:
- if (bl_pwm->pwm_duty == 0)
- gpio_level = 0;
- else
- gpio_level = 1;
- break;
- case BL_PWM_NEGATIVE:
- if (bl_pwm->pwm_duty == 0)
- gpio_level = 1;
- else
- gpio_level = 0;
- break;
- default:
- LCDERR("bl: %s: port=%d: invalid pwm_method %d\n",
- __func__, bl_pwm->pwm_port, bl_pwm->pwm_method);
- gpio_level = 0;
- break;
- }
- if (lcd_debug_print_flag) {
- LCDPR("bl: %s: pwm port=%d, duty=%d%%, switch to gpio %d\n",
- __func__, bl_pwm->pwm_port, bl_pwm->pwm_duty, gpio_level);
- }
- bl_pwm_pinmux_clr_gpio_set(bl_pwm, gpio_level);
- } else {
- if (lcd_debug_print_flag) {
- LCDPR("bl: %s: pwm_port=%d set as pwm\n",
- __func__, bl_pwm->pwm_port);
- }
- bl_pwm_pinmux_set_gpio_clr(bl_pwm);
- }
- }
-}
-
-static void bl_pwm_pinmux_ctrl(struct bl_config_s *bconf, int status)
-{
- int i;
-
- if (lcd_debug_print_flag)
- LCDPR("bl: %s: %d\n", __func__, status);
- if (status) {
- /* set pinmux */
- switch (bconf->method) {
- case BL_CTRL_PWM:
- bl_set_pwm_gpio_check(bconf->bl_pwm);
- break;
- case BL_CTRL_PWM_COMBO:
- bl_set_pwm_gpio_check(bconf->bl_pwm_combo0);
- bl_set_pwm_gpio_check(bconf->bl_pwm_combo1);
- break;
- default:
- break;
- }
- } else {
- switch (bconf->method) {
- case BL_CTRL_PWM:
- i = 0;
- while (i < LCD_PINMUX_NUM) {
- if (bconf->bl_pwm->pinmux_set[i][0] == LCD_PINMUX_END)
- break;
- lcd_pinmux_clr_mask(bconf->bl_pwm->pinmux_set[i][0],
- bconf->bl_pwm->pinmux_set[i][1]);
- if (lcd_debug_print_flag) {
- LCDPR("bl: %s: port=%d, pinmux_clr=%d,0x%08x\n",
- __func__, bconf->bl_pwm->pwm_port,
- bconf->bl_pwm->pinmux_set[i][0],
- bconf->bl_pwm->pinmux_set[i][1]);
- }
- i++;
- }
- bconf->bl_pwm->pinmux_flag = 0;
-
- if (bconf->bl_pwm->pwm_gpio < BL_GPIO_NUM_MAX)
- bl_gpio_set(bconf->bl_pwm->pwm_gpio, bconf->bl_pwm->pwm_gpio_off);
- break;
- case BL_CTRL_PWM_COMBO:
- i = 0;
- while (i < LCD_PINMUX_NUM) {
- if (bconf->bl_pwm_combo0->pinmux_set[i][0] == LCD_PINMUX_END)
- break;
- lcd_pinmux_clr_mask(bconf->bl_pwm_combo0->pinmux_set[i][0],
- bconf->bl_pwm_combo0->pinmux_set[i][1]);
- if (lcd_debug_print_flag) {
- LCDPR("bl: %s: port=%d, pinmux_clr=%d,0x%08x\n",
- __func__, bconf->bl_pwm_combo0->pwm_port,
- bconf->bl_pwm_combo0->pinmux_set[i][0],
- bconf->bl_pwm_combo0->pinmux_set[i][1]);
- }
- i++;
- }
- i = 0;
- while (i < LCD_PINMUX_NUM) {
- if (bconf->bl_pwm_combo1->pinmux_set[i][0] == LCD_PINMUX_END)
- break;
- lcd_pinmux_clr_mask(bconf->bl_pwm_combo1->pinmux_set[i][0],
- bconf->bl_pwm_combo1->pinmux_set[i][1]);
- if (lcd_debug_print_flag) {
- LCDPR("bl: %s: port=%d, pinmux_clr=%d,0x%08x\n",
- __func__, bconf->bl_pwm_combo1->pwm_port,
- bconf->bl_pwm_combo1->pinmux_set[i][0],
- bconf->bl_pwm_combo1->pinmux_set[i][1]);
- }
- i++;
- }
- bconf->bl_pwm_combo0->pinmux_flag = 0;
- bconf->bl_pwm_combo1->pinmux_flag = 0;
-
- if (bconf->bl_pwm_combo0->pwm_gpio < BL_GPIO_NUM_MAX) {
- bl_gpio_set(bconf->bl_pwm_combo0->pwm_gpio,
- bconf->bl_pwm_combo0->pwm_gpio_off);
- }
- if (bconf->bl_pwm_combo1->pwm_gpio < BL_GPIO_NUM_MAX) {
- bl_gpio_set(bconf->bl_pwm_combo1->pwm_gpio,
- bconf->bl_pwm_combo1->pwm_gpio_off);
- }
- break;
- default:
- break;
- }
- }
-}
-
-static unsigned int pwm_misc[6][5] = {
- /* pwm_reg, pre_div, clk_sel, clk_en, pwm_en*/
- {PWM_MISC_REG_AB, 8, 4, 15, 0,},
- {PWM_MISC_REG_AB, 16, 6, 23, 0,},
- {PWM_MISC_REG_CD, 8, 4, 15, 0,},
- {PWM_MISC_REG_CD, 16, 6, 23, 0,},
- {PWM_MISC_REG_EF, 8, 4, 15, 0,},
- {PWM_MISC_REG_EF, 16, 6, 23, 0,},
-};
-
-static unsigned int pwm_reg[6] = {
- PWM_PWM_A,
- PWM_PWM_B,
- PWM_PWM_C,
- PWM_PWM_D,
- PWM_PWM_E,
- PWM_PWM_F,
-};
-
-static void bl_pwm_config_init(struct bl_pwm_config_s *bl_pwm)
-{
- unsigned int freq, pre_div, cnt;
- int i;
-
- if (bl_pwm == NULL) {
- LCDERR("bl: %s: bl_pwm is NULL\n", __func__);
- return;
- }
- if (bl_pwm->pwm_port >= BL_PWM_MAX)
- return;
-
- if (lcd_debug_print_flag) {
- LCDPR("bl: %s pwm_port %d: freq = %u\n",
- __func__, bl_pwm->pwm_port, bl_pwm->pwm_freq);
- }
- freq = bl_pwm->pwm_freq;
- switch (bl_pwm->pwm_port) {
- case BL_PWM_VS:
- cnt = lcd_vcbus_read(ENCL_VIDEO_MAX_LNCNT) + 1;
- bl_pwm->pwm_cnt = cnt;
- bl_pwm->pwm_pre_div = 0;
- if (lcd_debug_print_flag)
- LCDPR("bl: pwm_cnt = %u\n", bl_pwm->pwm_cnt);
- break;
- default:
- for (i = 0; i < 0x7f; i++) {
- pre_div = i;
- cnt = XTAL_FREQ_HZ / (freq * (pre_div + 1)) - 2;
- if (cnt <= 0xffff) /* 16bit */
- break;
- }
- bl_pwm->pwm_cnt = cnt;
- bl_pwm->pwm_pre_div = pre_div;
- if (lcd_debug_print_flag)
- LCDPR("bl: pwm_cnt = %u, pwm_pre_div = %u\n", cnt, pre_div);
- break;
- }
-
- if (bl_pwm->pwm_duty_max > 100) {
- bl_pwm->pwm_max = (bl_pwm->pwm_cnt * bl_pwm->pwm_duty_max / 255);
- bl_pwm->pwm_min = (bl_pwm->pwm_cnt * bl_pwm->pwm_duty_min / 255);
- } else {
- bl_pwm->pwm_max = (bl_pwm->pwm_cnt * bl_pwm->pwm_duty_max / 100);
- bl_pwm->pwm_min = (bl_pwm->pwm_cnt * bl_pwm->pwm_duty_min / 100);
- }
- if (lcd_debug_print_flag)
- LCDPR("bl: pwm_max = %u, pwm_min = %u\n", bl_pwm->pwm_max, bl_pwm->pwm_min);
-}
-
-void bl_pwm_config_update(struct bl_config_s *bconf)
-{
-#ifdef CONFIG_AML_LOCAL_DIMMING
- struct aml_ldim_driver_s *ldim_drv;
-#endif
-
- if (bconf == NULL) {
- LCDERR("bl: bconf is null\n");
- return;
- }
-
- switch (bconf->method) {
- case BL_CTRL_PWM:
- bl_pwm_config_init(bconf->bl_pwm);
- break;
- case BL_CTRL_PWM_COMBO:
- bl_pwm_config_init(bconf->bl_pwm_combo0);
- bl_pwm_config_init(bconf->bl_pwm_combo1);
- break;
-#ifdef CONFIG_AML_LOCAL_DIMMING
- case BL_CTRL_LOCAL_DIMMING:
- ldim_drv = aml_ldim_get_driver();
- if (ldim_drv) {
- if (ldim_drv->ldev_conf)
- bl_pwm_config_init(&ldim_drv->ldev_conf->pwm_config);
- else
- LCDERR("bl: ldim_config is null\n");
- } else {
- LCDERR("bl: ldim_drv is null\n");
- }
- break;
-#endif
- default:
- break;
- }
-}
-
-static unsigned int bl_level_mapping(unsigned int level)
-{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- unsigned int mid = lcd_drv->bl_config->level_mid;
- unsigned int mid_map =lcd_drv->bl_config->level_mid_mapping;
- unsigned int max = lcd_drv->bl_config->level_max;
- unsigned int min = lcd_drv->bl_config->level_min;
-
- if (mid == mid_map)
- return level;
-
- level = level > max ? max : level;
- if ((level >= mid) && (level <= max))
- level = (((level - mid) * (max - mid_map)) / (max - mid)) + mid_map;
- else if ((level >= min) && (level < mid))
- level = (((level - min) * (mid_map - min)) / (mid - min)) + min;
- else
- level = 0;
-
- return level;
-}
-
-static void bl_set_pwm(struct bl_pwm_config_s *bl_pwm)
-{
- unsigned int pwm_hi = 0, pwm_lo = 0;
- unsigned int port = bl_pwm->pwm_port;
- unsigned int vs[4], ve[4], sw, n, i, pol = 0;
-
- if (bl_status > 0)
- bl_set_pwm_gpio_check(bl_pwm);
-
- switch (bl_pwm->pwm_method) {
- case BL_PWM_POSITIVE:
- pwm_hi = bl_pwm->pwm_level;
- pwm_lo = bl_pwm->pwm_cnt - bl_pwm->pwm_level;
- pol = 0;
- break;
- case BL_PWM_NEGATIVE:
- pwm_lo = bl_pwm->pwm_level;
- pwm_hi = bl_pwm->pwm_cnt - bl_pwm->pwm_level;
- pol = 1;
- break;
- default:
- LCDERR("bl: port %d: invalid pwm_method %d\n", port, bl_pwm->pwm_method);
- break;
- }
-
- switch (port) {
- case BL_PWM_A:
- case BL_PWM_B:
- case BL_PWM_C:
- case BL_PWM_D:
- case BL_PWM_E:
- case BL_PWM_F:
- lcd_cbus_write(pwm_reg[port], (pwm_hi << 16) | pwm_lo);
- if (lcd_debug_print_flag)
- LCDPR("bl: pwm_reg=0x%08x\n", lcd_cbus_read(pwm_reg[port]));
- break;
- case BL_PWM_VS:
- pwm_hi = bl_pwm->pwm_level;
- memset(vs, 0xffff, sizeof(unsigned int) * 4);
- memset(ve, 0xffff, sizeof(unsigned int) * 4);
- n = bl_pwm->pwm_freq;
- sw = (bl_pwm->pwm_cnt * 10 / n + 5) / 10;
- pwm_hi = (pwm_hi * 10 / n + 5) / 10;
- pwm_hi = (pwm_hi > 1) ? pwm_hi : 1;
- if (lcd_debug_print_flag)
- LCDPR("bl: n=%d, sw=%d, pwm_high=%d\n", n, sw, pwm_hi);
- for (i = 0; i < n; i++) {
- vs[i] = 1 + (sw * i);
- ve[i] = vs[i] + pwm_hi - 1;
- if (lcd_debug_print_flag) {
- LCDPR("bl: vs[%d]=%d, ve[%d]=%d\n",
- i, vs[i], i, ve[i]);
- }
- }
- lcd_vcbus_write(VPU_VPU_PWM_V0, (pol << 31) |
- (ve[0] << 16) | (vs[0]));
- lcd_vcbus_write(VPU_VPU_PWM_V1, (ve[1] << 16) | (vs[1]));
- lcd_vcbus_write(VPU_VPU_PWM_V2, (ve[2] << 16) | (vs[2]));
- lcd_vcbus_write(VPU_VPU_PWM_V3, (ve[3] << 16) | (vs[3]));
- break;
- default:
- break;
- }
-}
-
-static void bl_set_level_pwm(struct bl_pwm_config_s *bl_pwm, unsigned int level)
-{
- unsigned int min = bl_pwm->level_min;
- unsigned int max = bl_pwm->level_max;
- unsigned int pwm_max = bl_pwm->pwm_max;
- unsigned int pwm_min = bl_pwm->pwm_min;
-
- level = bl_level_mapping(level);
- max = bl_level_mapping(max);
- min = bl_level_mapping(min);
- if ((max <= min) || (level < min))
- bl_pwm->pwm_level = pwm_min;
- else
- bl_pwm->pwm_level = (pwm_max - pwm_min) * (level - min) / (max - min) + pwm_min;
-
- if (bl_pwm->pwm_duty_max > 100)
- bl_pwm->pwm_duty = bl_pwm->pwm_level * 255 / bl_pwm->pwm_cnt;
- else
- bl_pwm->pwm_duty = ((bl_pwm->pwm_level * 1000 / bl_pwm->pwm_cnt) + 5) / 10;
-
- if (lcd_debug_print_flag) {
- LCDPR("bl: port %d: level=%d, level_max=%d, level_min=%d\n",
- bl_pwm->pwm_port, level, max, min);
- LCDPR("bl: port %d: pwm_max=%d, pwm_min=%d, pwm_level=%d, duty=%d%%\n",
- bl_pwm->pwm_port, pwm_max, pwm_min, bl_pwm->pwm_level, bl_pwm->pwm_duty);
- }
-
- bl_set_pwm(bl_pwm);
-}
-
-void bl_set_level(unsigned int level)
-{
- unsigned int temp = 0;
- struct bl_config_s *bconf;
- struct bl_pwm_config_s *pwm0, *pwm1;
-#ifdef CONFIG_AML_BL_EXTERN
- struct aml_bl_extern_driver_s *bl_ext;
-#endif
-#ifdef CONFIG_AML_LOCAL_DIMMING
- struct aml_ldim_driver_s *ldim_drv;
-#endif
-
- bconf = bl_check_valid();
- if (bconf == NULL)
- return;
-
- LCDPR("bl: set level: %u, last level: %u\n", level, bconf->level);
- /* level range check */
- level = (level > bconf->level_max ? bconf->level_max :
- (level < bconf->level_min ? bconf->level_min : level));
- bconf->level = level;
-
- switch (bconf->method) {
- case BL_CTRL_GPIO:
- break;
- case BL_CTRL_PWM:
- bl_set_level_pwm(bconf->bl_pwm, level);
- break;
- case BL_CTRL_PWM_COMBO:
- pwm0 = bconf->bl_pwm_combo0;
- pwm1 = bconf->bl_pwm_combo1;
- if ((level >= pwm0->level_min) && (level <= pwm0->level_max)) {
- temp = (pwm0->level_min > pwm1->level_min) ? pwm1->level_max : pwm1->level_min;
- if (lcd_debug_print_flag)
- LCDPR("bl: pwm0 region, level=%u, pwm1_level=%u\n", level, temp);
- bl_set_level_pwm(pwm0, level);
- bl_set_level_pwm(pwm1, temp);
- } else if ((level >= pwm1->level_min) && (level <= pwm1->level_max)) {
- temp = (pwm1->level_min > pwm0->level_min) ? pwm0->level_max : pwm0->level_min;
- if (lcd_debug_print_flag)
- LCDPR("bl: pwm1 region, level=%u, pwm0_level=%u\n", level, temp);
- bl_set_level_pwm(pwm0, temp);
- bl_set_level_pwm(pwm1, level);
- }
- break;
-#ifdef CONFIG_AML_LOCAL_DIMMING
- case BL_CTRL_LOCAL_DIMMING:
- ldim_drv = aml_ldim_get_driver();
- if (ldim_drv->set_level)
- ldim_drv->set_level(level);
- else
- LCDERR("bl: ldim set_level is null\n");
- break;
-#endif
-#ifdef CONFIG_AML_BL_EXTERN
- case BL_CTRL_EXTERN:
- bl_ext = aml_bl_extern_get_driver();
- if (bl_ext->set_level)
- bl_ext->set_level(level);
- else
- LCDERR("bl: bl_extern set_level is null\n");
- break;
-#endif
- default:
- if (lcd_debug_print_flag)
- LCDERR("bl: wrong backlight control method\n");
- break;
- }
-}
-
-unsigned int bl_get_level(void)
-{
- struct bl_config_s *bconf;
-
- bconf = bl_check_valid();
- if (bconf == NULL)
- return 0;
-
- return bconf->level;
-}
-
-void bl_pwm_ctrl(struct bl_pwm_config_s *bl_pwm, int status)
-{
- int port, pre_div;
-
- port = bl_pwm->pwm_port;
- pre_div = bl_pwm->pwm_pre_div;
- if (status) {
- /* enable pwm */
- switch (port) {
- case BL_PWM_A:
- case BL_PWM_B:
- case BL_PWM_C:
- case BL_PWM_D:
- case BL_PWM_E:
- case BL_PWM_F:
- /* pwm clk_div */
- lcd_cbus_setb(pwm_misc[port][0], pre_div, pwm_misc[port][1], 7);
- /* pwm clk_sel */
- lcd_cbus_setb(pwm_misc[port][0], 0, pwm_misc[port][2], 2);
- /* pwm clk_en */
- lcd_cbus_setb(pwm_misc[port][0], 1, pwm_misc[port][3], 1);
- /* pwm enable */
- lcd_cbus_setb(pwm_misc[port][0], 0x3, pwm_misc[port][4], 2);
- break;
- default:
- break;
- }
- } else {
- /* disable pwm */
- switch (port) {
- case BL_PWM_A:
- case BL_PWM_B:
- case BL_PWM_C:
- case BL_PWM_D:
- case BL_PWM_E:
- case BL_PWM_F:
- /* pwm clk_disable */
- lcd_cbus_setb(pwm_misc[port][0], 0, pwm_misc[port][3], 1);
- break;
- default:
- break;
- }
- }
-}
-
-static void bl_power_en_ctrl(struct bl_config_s *bconf, int status)
-{
- int val;
-
- if (status)
- val = bconf->en_gpio_on;
- else
- val = bconf->en_gpio_off;
- if (bconf->en_gpio < BL_GPIO_NUM_MAX)
- bl_gpio_set(bconf->en_gpio, val);
-}
-
-void bl_power_ctrl(int status)
-{
- int gpio, value;
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- struct bl_config_s *bconf;
-#ifdef CONFIG_AML_BL_EXTERN
- struct aml_bl_extern_driver_s *bl_ext;
-#endif
-#ifdef CONFIG_AML_LOCAL_DIMMING
- struct aml_ldim_driver_s *ldim_drv;
-#endif
-
- bconf = bl_check_valid();
- if (bconf == NULL)
- return;
-
- gpio = bconf->en_gpio;
- value = status ? bconf->en_gpio_on : bconf->en_gpio_off;
- if (lcd_debug_print_flag)
- LCDPR("bl: status=%d gpio=%d value=%d\n", status, gpio, value);
-
- if (status) {
- /* bl_off_policy */
- if (bl_off_policy != BL_OFF_POLICY_NONE) {
- LCDPR("bl_off_policy=%d for bl_off\n", bl_off_policy);
- return;
- }
-
- bl_status = 1;
- /* check if factory test */
- if (lcd_drv->factory_bl_power_on_delay >= 0) {
- LCDPR("bl: %s: factory test power_on_delay!\n", __func__);
- if (lcd_drv->factory_bl_power_on_delay > 0)
- mdelay(lcd_drv->factory_bl_power_on_delay);
- } else {
- if (bconf->power_on_delay > 0)
- mdelay(bconf->power_on_delay);
- }
-
- switch (bconf->method) {
- case BL_CTRL_GPIO:
- bl_power_en_ctrl(bconf, 1);
- break;
- case BL_CTRL_PWM:
- if (bconf->en_sequence_reverse) {
- /* step 1: power on enable */
- bl_power_en_ctrl(bconf, 1);
- if (bconf->pwm_on_delay > 0)
- mdelay(bconf->pwm_on_delay);
- /* step 2: power on pwm */
- bl_pwm_ctrl(bconf->bl_pwm, 1);
- bl_pwm_pinmux_ctrl(bconf, 1);
- } else {
- /* step 1: power on pwm */
- bl_pwm_ctrl(bconf->bl_pwm, 1);
- bl_pwm_pinmux_ctrl(bconf, 1);
- if (bconf->pwm_on_delay > 0)
- mdelay(bconf->pwm_on_delay);
- /* step 2: power on enable */
- bl_power_en_ctrl(bconf, 1);
- }
- break;
- case BL_CTRL_PWM_COMBO:
- if (bconf->en_sequence_reverse) {
- /* step 1: power on enable */
- bl_power_en_ctrl(bconf, 1);
- if (bconf->pwm_on_delay > 0)
- mdelay(bconf->pwm_on_delay);
- /* step 2: power on pwm_combo */
- bl_pwm_ctrl(bconf->bl_pwm_combo0, 1);
- bl_pwm_ctrl(bconf->bl_pwm_combo1, 1);
- bl_pwm_pinmux_ctrl(bconf, 1);
- } else {
- /* step 1: power on pwm_combo */
- bl_pwm_ctrl(bconf->bl_pwm_combo0, 1);
- bl_pwm_ctrl(bconf->bl_pwm_combo1, 1);
- bl_pwm_pinmux_ctrl(bconf, 1);
- if (bconf->pwm_on_delay > 0)
- mdelay(bconf->pwm_on_delay);
- /* step 2: power on enable */
- bl_power_en_ctrl(bconf, 1);
- }
- break;
-#ifdef CONFIG_AML_LOCAL_DIMMING
- case BL_CTRL_LOCAL_DIMMING:
- ldim_drv = aml_ldim_get_driver();
- if (bconf->en_sequence_reverse) {
- /* step 1: power on enable */
- bl_power_en_ctrl(bconf, 1);
- /* step 2: power on ldim */
- if (ldim_drv->power_on)
- ldim_drv->power_on();
- else
- LCDERR("bl: ldim power on is null\n");
- } else {
- /* step 1: power on ldim */
- if (ldim_drv->power_on)
- ldim_drv->power_on();
- else
- LCDERR("bl: ldim power on is null\n");
- /* step 2: power on enable */
- bl_power_en_ctrl(bconf, 1);
- }
- break;
-#endif
-#ifdef CONFIG_AML_BL_EXTERN
- case BL_CTRL_EXTERN:
- bl_ext = aml_bl_extern_get_driver();
- if (bconf->en_sequence_reverse) {
- /* step 1: power on enable */
- bl_power_en_ctrl(bconf, 1);
- /* step 2: power on bl_extern */
- if (bl_ext->power_on)
- bl_ext->power_on();
- else
- LCDERR("bl: bl_extern power on is null\n");
- } else {
- /* step 1: power on bl_extern */
- if (bl_ext->power_on)
- bl_ext->power_on();
- else
- LCDERR("bl: bl_extern power on is null\n");
- /* step 2: power on enable */
- bl_power_en_ctrl(bconf, 1);
- }
- break;
-#endif
- default:
- if (lcd_debug_print_flag)
- LCDERR("bl: wrong backlight control method\n");
- break;
- }
- } else {
- bl_status = 0;
- switch (bconf->method) {
- case BL_CTRL_GPIO:
- bl_power_en_ctrl(bconf, 0);
- break;
- case BL_CTRL_PWM:
- if (bconf->en_sequence_reverse) {
- /* step 1: power off pwm */
- bl_pwm_ctrl(bconf->bl_pwm, 0);
- bl_pwm_pinmux_ctrl(bconf, 0);
- if (bconf->pwm_off_delay > 0)
- mdelay(bconf->pwm_off_delay);
- /* step 2: power off enable */
- bl_power_en_ctrl(bconf, 0);
- } else {
- /* step 1: power off enable */
- bl_power_en_ctrl(bconf, 0);
- /* step 2: power off pwm */
- if (bconf->pwm_off_delay > 0)
- mdelay(bconf->pwm_off_delay);
- bl_pwm_ctrl(bconf->bl_pwm, 0);
- bl_pwm_pinmux_ctrl(bconf, 0);
- }
- break;
- case BL_CTRL_PWM_COMBO:
- if (bconf->en_sequence_reverse) {
- /* step 1: power off pwm_combo */
- bl_pwm_ctrl(bconf->bl_pwm_combo0, 0);
- bl_pwm_ctrl(bconf->bl_pwm_combo1, 0);
- bl_pwm_pinmux_ctrl(bconf, 0);
- if (bconf->pwm_off_delay > 0)
- mdelay(bconf->pwm_off_delay);
- /* step 2: power off enable */
- bl_power_en_ctrl(bconf, 0);
- } else {
- /* step 1: power off enable */
- bl_power_en_ctrl(bconf, 0);
- /* step 2: power off pwm_combo */
- if (bconf->pwm_off_delay > 0)
- mdelay(bconf->pwm_off_delay);
- bl_pwm_ctrl(bconf->bl_pwm_combo0, 0);
- bl_pwm_ctrl(bconf->bl_pwm_combo1, 0);
- bl_pwm_pinmux_ctrl(bconf, 0);
- }
- break;
-#ifdef CONFIG_AML_LOCAL_DIMMING
- case BL_CTRL_LOCAL_DIMMING:
- ldim_drv = aml_ldim_get_driver();
- if (bconf->en_sequence_reverse) {
- /* step 1: power off ldim */
- if (ldim_drv->power_off)
- ldim_drv->power_off();
- else
- LCDERR("bl: ldim power off is null\n");
- /* step 2: power off enable */
- bl_power_en_ctrl(bconf, 0);
- } else {
- /* step 1: power off enable */
- bl_power_en_ctrl(bconf, 0);
- /* step 2: power off ldim */
- if (ldim_drv->power_off)
- ldim_drv->power_off();
- else
- LCDERR("bl: ldim power off is null\n");
- }
- break;
-#endif
-#ifdef CONFIG_AML_BL_EXTERN
- case BL_CTRL_EXTERN:
- bl_ext = aml_bl_extern_get_driver();
- if (bconf->en_sequence_reverse) {
- /* step 1: power off bl_extern */
- if (bl_ext->power_off)
- bl_ext->power_off();
- else
- LCDERR("bl: bl_extern: power off is null\n");
- /* step 2: power off enable */
- bl_power_en_ctrl(bconf, 0);
- } else {
- /* step 1: power off enable */
- bl_power_en_ctrl(bconf, 0);
- /* step 2: power off bl_extern */
- if (bl_ext->power_off)
- bl_ext->power_off();
- else
- LCDERR("bl: bl_extern: power off is null\n");
- }
- break;
-#endif
- default:
- if (lcd_debug_print_flag)
- LCDERR("bl: wrong backlight control method\n");
- break;
- }
- if (bconf->power_off_delay > 0)
- mdelay(bconf->power_off_delay);
- }
- LCDPR("bl: %s: %d\n", __func__, status);
-}
-
-static char *bl_pwm_name[] = {
- "PWM_A",
- "PWM_B",
- "PWM_C",
- "PWM_D",
- "PWM_E",
- "PWM_F",
- "PWM_VS",
-};
-
-enum bl_pwm_port_e bl_pwm_str_to_pwm(const char *str)
-{
- enum bl_pwm_port_e pwm_port = BL_PWM_MAX;
- int i;
-
- for (i = 0; i < ARRAY_SIZE(bl_pwm_name); i++) {
- if (strcmp(str, bl_pwm_name[i]) == 0) {
- pwm_port = i;
- break;
- }
- }
-
- return pwm_port;
-}
-
-static void bl_pinmux_print(struct bl_config_s *bconf)
-{
- struct bl_pwm_config_s *bl_pwm;
- int i;
-
- switch (bconf->method) {
- case BL_CTRL_PWM:
- bl_pwm = bconf->bl_pwm;
- i = 0;
- while (i < LCD_PINMUX_NUM) {
- if (bl_pwm->pinmux_set[i][0] == LCD_PINMUX_END)
- break;
- LCDPR("bl: bl_pinmux set: %d, 0x%08x\n",
- bl_pwm->pinmux_set[i][0], bl_pwm->pinmux_set[i][1]);
- i++;
- }
- i = 0;
- while (i < LCD_PINMUX_NUM) {
- if (bl_pwm->pinmux_clr[i][0] == LCD_PINMUX_END)
- break;
- LCDPR("bl: bl_pinmux clr: %d, 0x%08x\n",
- bl_pwm->pinmux_clr[i][0], bl_pwm->pinmux_clr[i][1]);
- i++;
- }
- break;
- case BL_CTRL_PWM_COMBO:
- bl_pwm = bconf->bl_pwm_combo0;
- i = 0;
- while (i < LCD_PINMUX_NUM) {
- if (bl_pwm->pinmux_set[i][0] == LCD_PINMUX_END)
- break;
- LCDPR("bl: pwm_combo0 pinmux_set: %d, 0x%08x\n",
- bl_pwm->pinmux_set[i][0], bl_pwm->pinmux_set[i][1]);
- i++;
- }
- i = 0;
- while (i < LCD_PINMUX_NUM) {
- if (bl_pwm->pinmux_clr[i][0] == LCD_PINMUX_END)
- break;
- LCDPR("bl: pwm_combo0 pinmux_clr: %d, 0x%08x\n",
- bl_pwm->pinmux_clr[i][0], bl_pwm->pinmux_clr[i][1]);
- i++;
- }
-
- bl_pwm = bconf->bl_pwm_combo1;
- i = 0;
- while (i < LCD_PINMUX_NUM) {
- if (bl_pwm->pinmux_set[i][0] == LCD_PINMUX_END)
- break;
- LCDPR("bl: pwm_combo1 pinmux_set: %d, 0x%08x\n",
- bl_pwm->pinmux_set[i][0], bl_pwm->pinmux_set[i][1]);
- i++;
- }
- i = 0;
- while (i < LCD_PINMUX_NUM) {
- if (bl_pwm->pinmux_clr[i][0] == LCD_PINMUX_END)
- break;
- LCDPR("bl: pwm_combo1 pinmux_clr: %d, 0x%08x\n",
- bl_pwm->pinmux_clr[i][0], bl_pwm->pinmux_clr[i][1]);
- i++;
- }
- break;
- default:
- break;
- }
-}
-
-void bl_config_print(void)
-{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- struct bl_config_s *bconf;
- struct bl_pwm_config_s *bl_pwm;
-#ifdef CONFIG_AML_LOCAL_DIMMING
- struct aml_ldim_driver_s *ldim_drv = aml_ldim_get_driver();
-#endif
-#ifdef CONFIG_AML_BL_EXTERN
- struct aml_bl_extern_driver_s *bl_extern = aml_bl_extern_get_driver();
-#endif
-
- bconf = lcd_drv->bl_config;
- LCDPR("bl: name: %s\n", bconf->name);
- LCDPR("bl: method: %d\n", bconf->method);
-
- LCDPR("bl: level_default = %d\n", bconf->level_default);
- LCDPR("bl: level_min = %d\n", bconf->level_min);
- LCDPR("bl: level_max = %d\n", bconf->level_max);
- LCDPR("bl: level_mid = %d\n", bconf->level_mid);
- LCDPR("bl: level_mid_mapping = %d\n", bconf->level_mid_mapping);
-
- LCDPR("bl: en_gpio = %d\n", bconf->en_gpio);
- LCDPR("bl: en_gpio_on = %d\n", bconf->en_gpio_on);
- LCDPR("bl: en_gpio_off = %d\n", bconf->en_gpio_off);
- /* check if factory test */
- if (lcd_drv->factory_bl_power_on_delay >= 0)
- LCDPR("bl: factory test power_on_delay = %d\n", bconf->power_on_delay);
- else
- LCDPR("bl: power_on_delay = %d\n", bconf->power_on_delay);
- LCDPR("bl: power_off_delay = %d\n", bconf->power_off_delay);
- bl_gpio_info_print();
-
- switch (bconf->method) {
- case BL_CTRL_PWM:
- if (bconf->bl_pwm) {
- bl_pwm = bconf->bl_pwm;
- LCDPR("bl: pwm_index = %d\n", bl_pwm->index);
- LCDPR("bl: pwm_method = %d\n", bl_pwm->pwm_method);
- LCDPR("bl: pwm_port = %d\n", bl_pwm->pwm_port);
- if (bl_pwm->pwm_port == BL_PWM_VS) {
- LCDPR("bl: pwm_freq = %d x vfreq\n", bl_pwm->pwm_freq);
- LCDPR("bl: pwm_cnt = %u\n", bl_pwm->pwm_cnt);
- if (bl_pwm->pwm_duty_max > 100)
- LCDPR("bl: pwm_duty = %d%%(%d)\n", bl_pwm->pwm_duty * 100 / 255, bl_pwm->pwm_duty);
- else
- LCDPR("bl: pwm_duty = %d%%(%d)\n", bl_pwm->pwm_duty, bl_pwm->pwm_duty);
-
- LCDPR("bl: pwm_reg0 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V0));
- LCDPR("bl: pwm_reg1 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V1));
- LCDPR("bl: pwm_reg2 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V2));
- LCDPR("bl: pwm_reg3 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V3));
- } else {
- LCDPR("bl: pwm_freq = %uHz\n", bl_pwm->pwm_freq);
- LCDPR("bl: pwm_cnt = %u\n", bl_pwm->pwm_cnt);
- LCDPR("bl: pwm_pre_div = %u\n", bl_pwm->pwm_pre_div);
- if (bl_pwm->pwm_duty_max > 100)
- LCDPR("bl: pwm_duty = %d%%(%d)\n", bl_pwm->pwm_duty * 100 / 255, bl_pwm->pwm_duty);
- else
- LCDPR("bl: pwm_duty = %d%%(%d)\n", bl_pwm->pwm_duty, bl_pwm->pwm_duty);
-
- LCDPR("bl: pwm_reg = 0x%08x\n", lcd_cbus_read(pwm_reg[bl_pwm->pwm_port]));
- }
- LCDPR("bl: pwm_duty_max = %d\n", bl_pwm->pwm_duty_max);
- LCDPR("bl: pwm_duty_min = %d\n", bl_pwm->pwm_duty_min);
- LCDPR("bl: pwm_gpio = %d\n", bl_pwm->pwm_gpio);
- LCDPR("bl: pwm_gpio_off = %d\n", bl_pwm->pwm_gpio_off);
- }
- LCDPR("bl: pwm_on_delay = %d\n", bconf->pwm_on_delay);
- LCDPR("bl: pwm_off_delay = %d\n", bconf->pwm_off_delay);
- LCDPR("bl: en_sequence_reverse = %d\n", bconf->en_sequence_reverse);
- bl_pinmux_print(bconf);
- break;
- case BL_CTRL_PWM_COMBO:
- if (bconf->bl_pwm_combo0) {
- bl_pwm = bconf->bl_pwm_combo0;
- LCDPR("bl: pwm_combo0_index = %d\n", bl_pwm->index);
- LCDPR("bl: pwm_combo0_method = %d\n", bl_pwm->pwm_method);
- LCDPR("bl: pwm_combo0_port = %d\n", bl_pwm->pwm_port);
- if (bl_pwm->pwm_port == BL_PWM_VS) {
- LCDPR("bl: pwm_combo0_freq = %d x vfreq\n", bl_pwm->pwm_freq);
- LCDPR("bl: pwm_combo0_cnt = %u\n", bl_pwm->pwm_cnt);
- if (bl_pwm->pwm_duty_max > 100)
- LCDPR("bl: pwm_combo0_duty = %d%%(%d)\n", bl_pwm->pwm_duty * 100 / 255, bl_pwm->pwm_duty);
- else
- LCDPR("bl: pwm_combo0_duty = %d%%(%d)\n", bl_pwm->pwm_duty, bl_pwm->pwm_duty);
-
- LCDPR("bl: pwm_combo0_reg0 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V0));
- LCDPR("bl: pwm_combo0_reg1 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V1));
- LCDPR("bl: pwm_combo0_reg2 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V2));
- LCDPR("bl: pwm_combo0_reg3 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V3));
- } else {
- LCDPR("bl: pwm_combo0_freq = %uHz\n", bl_pwm->pwm_freq);
- LCDPR("bl: pwm_combo0_cnt = %u\n", bl_pwm->pwm_cnt);
- LCDPR("bl: pwm_combo0_pre_div = %u\n", bl_pwm->pwm_pre_div);
- if (bl_pwm->pwm_duty_max > 100)
- LCDPR("bl: pwm_combo0_duty = %d%%(%d)\n", bl_pwm->pwm_duty * 100 / 255, bl_pwm->pwm_duty);
- else
- LCDPR("bl: pwm_combo0_duty = %d%%(%d)\n", bl_pwm->pwm_duty, bl_pwm->pwm_duty);
-
- LCDPR("bl: pwm_combo0_reg = 0x%08x\n", lcd_cbus_read(pwm_reg[bl_pwm->pwm_port]));
- }
- LCDPR("bl: pwm_combo0_duty_max = %d\n", bl_pwm->pwm_duty_max);
- LCDPR("bl: pwm_combo0_duty_min = %d\n", bl_pwm->pwm_duty_min);
- LCDPR("bl: pwm_combo0_gpio = %d\n", bl_pwm->pwm_gpio);
- LCDPR("bl: pwm_combo0_gpio_off = %d\n", bl_pwm->pwm_gpio_off);
- }
- if (bconf->bl_pwm_combo1) {
- bl_pwm = bconf->bl_pwm_combo1;
- LCDPR("bl: pwm_combo1_index = %d\n", bl_pwm->index);
- LCDPR("bl: pwm_combo1_method = %d\n", bl_pwm->pwm_method);
- LCDPR("bl: pwm_combo1_port = %d\n", bl_pwm->pwm_port);
- if (bl_pwm->pwm_port == BL_PWM_VS) {
- LCDPR("bl: pwm_combo1_freq = %d x vfreq\n", bl_pwm->pwm_freq);
- LCDPR("bl: pwm_combo1_cnt = %u\n", bl_pwm->pwm_cnt);
- if (bl_pwm->pwm_duty_max > 100)
- LCDPR("bl: pwm_combo1_duty = %d%%(%d)\n", bl_pwm->pwm_duty * 100 / 255, bl_pwm->pwm_duty);
- else
- LCDPR("bl: pwm_combo1_duty = %d%%(%d)\n", bl_pwm->pwm_duty, bl_pwm->pwm_duty);
-
- LCDPR("bl: pwm_combo1_reg0 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V0));
- LCDPR("bl: pwm_combo1_reg1 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V1));
- LCDPR("bl: pwm_combo1_reg2 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V2));
- LCDPR("bl: pwm_combo1_reg3 = 0x%08x\n", lcd_vcbus_read(VPU_VPU_PWM_V3));
- } else {
- LCDPR("bl: pwm_combo1_freq = %uHz\n", bl_pwm->pwm_freq);
- LCDPR("bl: pwm_combo1_cnt = %u\n", bl_pwm->pwm_cnt);
- LCDPR("bl: pwm_combo1_pre_div = %u\n", bl_pwm->pwm_pre_div);
- if (bl_pwm->pwm_duty_max > 100)
- LCDPR("bl: pwm_combo1_duty = %d%%(%d)\n", bl_pwm->pwm_duty * 100 / 255, bl_pwm->pwm_duty);
- else
- LCDPR("bl: pwm_combo1_duty = %d%%(%d)\n", bl_pwm->pwm_duty, bl_pwm->pwm_duty);
-
- LCDPR("bl: pwm_combo1_reg = 0x%08x\n", lcd_cbus_read(pwm_reg[bl_pwm->pwm_port]));
- }
- LCDPR("bl: pwm_combo1_duty_max = %d\n", bl_pwm->pwm_duty_max);
- LCDPR("bl: pwm_combo1_duty_min = %d\n", bl_pwm->pwm_duty_min);
- LCDPR("bl: pwm_combo1_gpio = %d\n", bl_pwm->pwm_gpio);
- LCDPR("bl: pwm_combo1_gpio_off = %d\n", bl_pwm->pwm_gpio_off);
- }
- LCDPR("bl: pwm_on_delay = %d\n", bconf->pwm_on_delay);
- LCDPR("bl: pwm_off_delay = %d\n", bconf->pwm_off_delay);
- LCDPR("bl: en_sequence_reverse = %d\n", bconf->en_sequence_reverse);
- bl_pinmux_print(bconf);
- break;
-#ifdef CONFIG_AML_LOCAL_DIMMING
- case BL_CTRL_LOCAL_DIMMING:
- if (ldim_drv) {
- if (ldim_drv->config_print)
- ldim_drv->config_print();
- } else {
- LCDPR("bl: invalid local dimming driver\n");
- }
- break;
-#endif
-#ifdef CONFIG_AML_BL_EXTERN
- case BL_CTRL_EXTERN:
- if (bl_extern) {
- if (bl_extern->config_print)
- bl_extern->config_print();
- } else {
- LCDPR("bl: invalid bl extern driver\n");
- }
- break;
-#endif
-
- default:
- LCDPR("bl: invalid backlight control method\n");
- break;
- }
-}
-
-static int bl_config_load_from_dts(const void *dt_blob, unsigned int index, struct bl_config_s *bconf)
-{
- int parent_offset, child_offset;
- char propname[30];
- char *propdata;
- char *p;
- const char *str;
- struct bl_pwm_config_s *bl_pwm;
- struct bl_pwm_config_s *pwm_combo0, *pwm_combo1;
-
- bconf->method = BL_CTRL_MAX; /* default */
- parent_offset = fdt_path_offset(dt_blob, "/backlight");
- if (parent_offset < 0) {
- LCDPR("bl: not find /backlight node %s\n", fdt_strerror(parent_offset));
- return -1;
- }
- propdata = (char *)fdt_getprop(dt_blob, parent_offset, "status", NULL);
- if (propdata == NULL) {
- LCDPR("bl: not find status, default to disabled\n");
- return -1;
- } else {
- if (strncmp(propdata, "okay", 2)) {
- LCDPR("bl: status disabled\n");
- return -1;
- }
- }
-
- sprintf(propname,"/backlight/backlight_%d", index);
- child_offset = fdt_path_offset(dt_blob, propname);
- if (child_offset < 0) {
- LCDERR("bl: not find %s node: %s\n", propname, fdt_strerror(child_offset));
- return -1;
- }
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "bl_name", NULL);
- if (propdata == NULL) {
- LCDERR("bl: failed to get bl_name\n");
- sprintf(bconf->name, "backlight_%d", index);
- } else {
- strcpy(bconf->name, propdata);
- }
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "bl_level_default_uboot_kernel", NULL);
- if (propdata == NULL) {
- LCDERR("bl: failed to get bl_level_default_uboot_kernel\n");
- bconf->level_default = BL_LEVEL_DEFAULT;
- } else {
- bconf->level_default = be32_to_cpup((u32*)propdata);
- }
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "bl_level_attr", NULL);
- if (propdata == NULL) {
- LCDERR("bl: failed to get bl_level_attr\n");
- bconf->level_max = BL_LEVEL_MAX;
- bconf->level_min = BL_LEVEL_MIN;
- bconf->level_mid = BL_LEVEL_MID;
- bconf->level_mid_mapping = BL_LEVEL_MID_MAPPED;
- } else {
- bconf->level_max = be32_to_cpup((u32*)propdata);
- bconf->level_min = be32_to_cpup((((u32*)propdata)+1));
- bconf->level_mid = be32_to_cpup((((u32*)propdata)+2));
- bconf->level_mid_mapping = be32_to_cpup((((u32*)propdata)+3));
- }
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "bl_ctrl_method", NULL);
- if (propdata == NULL) {
- LCDERR("bl: failed to get bl_ctrl_method\n");
- bconf->method = BL_CTRL_MAX;
- return -1;
- } else {
- bconf->method = be32_to_cpup((u32*)propdata);
- }
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "bl_power_attr", NULL);
- if (propdata == NULL) {
- LCDERR("bl: failed to get bl_power_attr\n");
- bconf->en_gpio = BL_GPIO_NUM_MAX;
- bconf->en_gpio_on = LCD_GPIO_OUTPUT_HIGH;
- bconf->en_gpio_off = LCD_GPIO_OUTPUT_LOW;
- bconf->power_on_delay = 100;
- bconf->power_off_delay = 30;
- } else {
- bconf->en_gpio = be32_to_cpup((u32*)propdata);
- bconf->en_gpio_on = be32_to_cpup((((u32*)propdata)+1));
- bconf->en_gpio_off = be32_to_cpup((((u32*)propdata)+2));
- bconf->power_on_delay = be32_to_cpup((((u32*)propdata)+3));
- bconf->power_off_delay = be32_to_cpup((((u32*)propdata)+4));
- }
-
- switch (bconf->method) {
- case BL_CTRL_PWM:
- bconf->bl_pwm = (struct bl_pwm_config_s *)malloc(sizeof(struct bl_pwm_config_s));
- if (bconf->bl_pwm == NULL) {
- LCDERR("bl: bl_pwm struct malloc error\n");
- return -1;
- }
- bl_pwm = bconf->bl_pwm;
- bl_pwm->index = 0;
-
- bl_pwm->level_max = bconf->level_max;
- bl_pwm->level_min = bconf->level_min;
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "bl_pwm_port", NULL);
- if (propdata == NULL) {
- LCDERR("bl: failed to get bl_pwm_port\n");
- bl_pwm->pwm_port = BL_PWM_MAX;
- } else {
- bl_pwm->pwm_port = bl_pwm_str_to_pwm(propdata);
- }
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "bl_pwm_attr", NULL);
- if (propdata == NULL) {
- LCDERR("bl: failed to get bl_pwm_attr\n");
- bl_pwm->pwm_method = BL_PWM_POSITIVE;
- if (bl_pwm->pwm_port == BL_PWM_VS)
- bl_pwm->pwm_freq = BL_FREQ_VS_DEFAULT;
- else
- bl_pwm->pwm_freq = BL_FREQ_DEFAULT;
- bl_pwm->pwm_duty_max = 80;
- bl_pwm->pwm_duty_min = 20;
- } else {
- bl_pwm->pwm_method = be32_to_cpup((u32*)propdata);
- bl_pwm->pwm_freq = be32_to_cpup((((u32*)propdata)+1));
- bl_pwm->pwm_duty_max = be32_to_cpup((((u32*)propdata)+2));
- bl_pwm->pwm_duty_min = be32_to_cpup((((u32*)propdata)+3));
- }
- if (bl_pwm->pwm_port == BL_PWM_VS) {
- if (bl_pwm->pwm_freq > 4) {
- LCDERR("bl: bl_pwm_vs wrong freq %d\n", bl_pwm->pwm_freq);
- bl_pwm->pwm_freq = BL_FREQ_VS_DEFAULT;
- }
- } else {
- if (bl_pwm->pwm_freq > XTAL_HALF_FREQ_HZ)
- bl_pwm->pwm_freq = XTAL_HALF_FREQ_HZ;
- }
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "bl_pwm_power", NULL);
- if (propdata == NULL) {
- LCDERR("bl: failed to get bl_pwm_power\n");
- bl_pwm->pwm_gpio = BL_GPIO_NUM_MAX;
- bl_pwm->pwm_gpio_off = LCD_GPIO_OUTPUT_LOW;
- bconf->pwm_on_delay = 10;
- bconf->pwm_off_delay = 10;
- } else {
- bl_pwm->pwm_gpio = be32_to_cpup((u32*)propdata);
- bl_pwm->pwm_gpio_off = be32_to_cpup((((u32*)propdata)+1));
- bconf->pwm_on_delay = be32_to_cpup((((u32*)propdata)+2));
- bconf->pwm_off_delay = be32_to_cpup((((u32*)propdata)+3));
- }
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "bl_pwm_en_sequence_reverse", NULL);
- if (propdata == NULL) {
- LCDPR("bl: don't find bl_pwm_en_sequence_reverse\n");
- bconf->en_sequence_reverse = 0;
- } else {
- bconf->en_sequence_reverse = be32_to_cpup((u32*)propdata);
- }
-
- bl_pwm->pwm_duty = bl_pwm->pwm_duty_min;
- /* bl_pwm_config_init(bl_pwm); */
- break;
- case BL_CTRL_PWM_COMBO:
- bconf->bl_pwm_combo0 = (struct bl_pwm_config_s *)malloc(sizeof(struct bl_pwm_config_s));
- if (bconf->bl_pwm_combo0 == NULL) {
- LCDERR("bl: bl_pwm_combo0 struct malloc error\n");
- return -1;
- }
- bconf->bl_pwm_combo1 = (struct bl_pwm_config_s *)malloc(sizeof(struct bl_pwm_config_s));
- if (bconf->bl_pwm_combo1 == NULL) {
- LCDERR("bl: bl_pwm_combo1 struct malloc error\n");
- return -1;
- }
- pwm_combo0 = bconf->bl_pwm_combo0;
- pwm_combo1 = bconf->bl_pwm_combo1;
- pwm_combo0->index = 0;
- pwm_combo1->index = 1;
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "bl_pwm_combo_level_mapping", NULL);
- if (propdata == NULL) {
- LCDERR("bl: failed to get bl_pwm_combo_level_mapping\n");
- pwm_combo0->level_max = BL_LEVEL_MAX;
- pwm_combo0->level_min = BL_LEVEL_MID;
- pwm_combo1->level_max = BL_LEVEL_MID;
- pwm_combo1->level_min = BL_LEVEL_MIN;
- } else {
- pwm_combo0->level_max = be32_to_cpup((u32*)propdata);
- pwm_combo0->level_min = be32_to_cpup((((u32*)propdata)+1));
- pwm_combo1->level_max = be32_to_cpup((((u32*)propdata)+2));
- pwm_combo1->level_min = be32_to_cpup((((u32*)propdata)+3));
- }
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "bl_pwm_combo_port", NULL);
- if (propdata == NULL) {
- LCDERR("bl: failed to get bl_pwm_combo_port\n");
- pwm_combo0->pwm_port = BL_PWM_MAX;
- pwm_combo1->pwm_port = BL_PWM_MAX;
- } else {
- p = propdata;
- str = p;
- pwm_combo0->pwm_port = bl_pwm_str_to_pwm(str);
- p += strlen(p) + 1;
- str = p;
- pwm_combo1->pwm_port = bl_pwm_str_to_pwm(str);
- }
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "bl_pwm_combo_attr", NULL);
- if (propdata == NULL) {
- LCDERR("bl: failed to get bl_pwm_combo_attr\n");
- pwm_combo0->pwm_method = BL_PWM_POSITIVE;
- if (pwm_combo0->pwm_port == BL_PWM_VS)
- pwm_combo0->pwm_freq = BL_FREQ_VS_DEFAULT;
- else
- pwm_combo0->pwm_freq = BL_FREQ_DEFAULT;
- pwm_combo0->pwm_duty_max = 80;
- pwm_combo0->pwm_duty_min = 20;
- pwm_combo1->pwm_method = BL_PWM_POSITIVE;
- if (pwm_combo1->pwm_port == BL_PWM_VS)
- pwm_combo1->pwm_freq = BL_FREQ_VS_DEFAULT;
- else
- pwm_combo1->pwm_freq = BL_FREQ_DEFAULT;
- pwm_combo1->pwm_duty_max = 80;
- pwm_combo1->pwm_duty_min = 20;
- } else {
- pwm_combo0->pwm_method = be32_to_cpup((u32*)propdata);
- pwm_combo0->pwm_freq = be32_to_cpup((((u32*)propdata)+1));
- pwm_combo0->pwm_duty_max = be32_to_cpup((((u32*)propdata)+2));
- pwm_combo0->pwm_duty_min = be32_to_cpup((((u32*)propdata)+3));
- pwm_combo1->pwm_method = be32_to_cpup((((u32*)propdata)+4));
- pwm_combo1->pwm_freq = be32_to_cpup((((u32*)propdata)+5));
- pwm_combo1->pwm_duty_max = be32_to_cpup((((u32*)propdata)+6));
- pwm_combo1->pwm_duty_min = be32_to_cpup((((u32*)propdata)+7));
- }
- if (pwm_combo0->pwm_port == BL_PWM_VS) {
- if (pwm_combo0->pwm_freq > 4) {
- LCDERR("bl: bl_pwm_vs wrong freq %d\n", pwm_combo0->pwm_freq);
- pwm_combo0->pwm_freq = BL_FREQ_VS_DEFAULT;
- }
- } else {
- if (pwm_combo0->pwm_freq > XTAL_HALF_FREQ_HZ)
- pwm_combo0->pwm_freq = XTAL_HALF_FREQ_HZ;
- }
- if (pwm_combo1->pwm_port == BL_PWM_VS) {
- if (pwm_combo1->pwm_freq > 4) {
- LCDERR("bl: bl_pwm_vs wrong freq %d\n", pwm_combo1->pwm_freq);
- pwm_combo1->pwm_freq = BL_FREQ_VS_DEFAULT;
- }
- } else {
- if (pwm_combo1->pwm_freq > XTAL_HALF_FREQ_HZ)
- pwm_combo1->pwm_freq = XTAL_HALF_FREQ_HZ;
- }
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "bl_pwm_combo_power", NULL);
- if (propdata == NULL) {
- LCDERR("bl: failed to get bl_pwm_combo_power\n");
- pwm_combo0->pwm_gpio = BL_GPIO_NUM_MAX;
- pwm_combo0->pwm_gpio_off = LCD_GPIO_INPUT;
- pwm_combo1->pwm_gpio = BL_GPIO_NUM_MAX;
- pwm_combo1->pwm_gpio_off = LCD_GPIO_INPUT;
- bconf->pwm_on_delay = 10;
- bconf->pwm_off_delay = 10;
- } else {
- pwm_combo0->pwm_gpio = be32_to_cpup((u32*)propdata);
- pwm_combo0->pwm_gpio_off = be32_to_cpup((((u32*)propdata)+1));
- pwm_combo1->pwm_gpio = be32_to_cpup((((u32*)propdata)+2));
- pwm_combo1->pwm_gpio_off = be32_to_cpup((((u32*)propdata)+3));
- bconf->pwm_on_delay = be32_to_cpup((((u32*)propdata)+4));
- bconf->pwm_off_delay = be32_to_cpup((((u32*)propdata)+5));
- }
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "bl_pwm_en_sequence_reverse", NULL);
- if (propdata == NULL) {
- LCDPR("bl: don't find bl_pwm_en_sequence_reverse\n");
- bconf->en_sequence_reverse = 0;
- } else {
- bconf->en_sequence_reverse = be32_to_cpup((u32*)propdata);
- }
-
- pwm_combo0->pwm_duty = pwm_combo0->pwm_duty_min;
- pwm_combo1->pwm_duty = pwm_combo1->pwm_duty_min;
- /* bl_pwm_config_init(pwm_combo0);
- bl_pwm_config_init(pwm_combo1); */
- break;
-#ifdef CONFIG_AML_LOCAL_DIMMING
- case BL_CTRL_LOCAL_DIMMING:
- ldim_config_load_from_dts(dt_blob, child_offset);
- aml_ldim_probe(dt_blob, 0);
- break;
-#endif
-#ifdef CONFIG_AML_BL_EXTERN
- case BL_CTRL_EXTERN:
- /* get bl_extern_index from dts */
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "bl_extern_index", NULL);
- if (propdata == NULL) {
- LCDERR("bl: failed to get bl_extern_index\n");
- } else {
- bconf->bl_extern_index = be32_to_cpup((u32*)propdata);
- LCDPR("get bl_extern_index = %d\n", bconf->bl_extern_index);
- }
- aml_bl_extern_device_load(dt_blob, bconf->bl_extern_index);
- break;
-#endif
-
- default:
- break;
- }
-
- return 0;
-}
-
-static int bl_config_load_from_bsp(struct bl_config_s *bconf)
-{
- struct ext_lcd_config_s *ext_lcd = NULL;
- char *panel_type = env_get("panel_type");
- unsigned int i = 0;
- struct bl_pwm_config_s *bl_pwm;
- struct bl_pwm_config_s *pwm_combo0, *pwm_combo1;
-
- if (panel_type == NULL) {
- LCDERR("bl: no panel_type, use default backlight config\n");
- return -1;
- }
- for (i = 0; i < LCD_NUM_MAX; i++) {
- ext_lcd = &ext_lcd_config[i];
- if (strcmp(ext_lcd->panel_type, panel_type) == 0)
- break;
- }
- if (i >= LCD_NUM_MAX) {
- LCDERR("bl: can't find %s, use default backlight config\n ", panel_type);
- return -1;
- }
-
- strcpy(bconf->name, panel_type);
- bconf->level_default = ext_lcd->level_default;
- bconf->level_min = ext_lcd->level_min;
- bconf->level_max = ext_lcd->level_max;
- bconf->level_mid = ext_lcd->level_mid;
- bconf->level_mid_mapping = ext_lcd->level_mid_mapping;
-
- bconf->method = ext_lcd->bl_method;
-
- if (ext_lcd->bl_en_gpio >= BL_GPIO_NUM_MAX)
- bconf->en_gpio = LCD_GPIO_MAX;
- else
- bconf->en_gpio = ext_lcd->bl_en_gpio;
- bconf->en_gpio_on = ext_lcd->bl_en_gpio_on;
- bconf->en_gpio_off = ext_lcd->bl_en_gpio_off;
- bconf->power_on_delay = ext_lcd->bl_power_on_delay;
- bconf->power_off_delay = ext_lcd->bl_power_off_delay;
-
- switch (bconf->method) {
- case BL_CTRL_PWM:
- bconf->bl_pwm = (struct bl_pwm_config_s *)malloc(sizeof(struct bl_pwm_config_s));
- if (bconf->bl_pwm == NULL) {
- LCDERR("bl: bl_pwm struct malloc error\n");
- return -1;
- }
- bl_pwm = bconf->bl_pwm;
- bl_pwm->index = 0;
-
- bl_pwm->level_max = bconf->level_max;
- bl_pwm->level_min = bconf->level_min;
-
- bl_pwm->pwm_method = ext_lcd->pwm_method;
- bl_pwm->pwm_port = ext_lcd->pwm_port;
- bl_pwm->pwm_freq = ext_lcd->pwm_freq;
- bl_pwm->pwm_duty_max = ext_lcd->pwm_duty_max;
- bl_pwm->pwm_duty_min = ext_lcd->pwm_duty_min;
-
- bl_pwm->pwm_gpio = ext_lcd->pwm_gpio;
- bl_pwm->pwm_gpio_off = ext_lcd->pwm_gpio_off;
- bconf->pwm_on_delay = ext_lcd->pwm_on_delay;
- bconf->pwm_off_delay = ext_lcd->pwm_off_delay;
-
- bl_pwm->pwm_duty = bl_pwm->pwm_duty_min;
- /* bl_pwm_config_init(bl_pwm); */
- break;
- case BL_CTRL_PWM_COMBO:
- bconf->bl_pwm_combo0 = (struct bl_pwm_config_s *)malloc(sizeof(struct bl_pwm_config_s));
- if (bconf->bl_pwm_combo0 == NULL) {
- LCDERR("bl: bl_pwm_combo0 struct malloc error\n");
- return -1;
- }
- bconf->bl_pwm_combo1 = (struct bl_pwm_config_s *)malloc(sizeof(struct bl_pwm_config_s));
- if (bconf->bl_pwm_combo1 == NULL) {
- LCDERR("bl: bl_pwm_combo1 struct malloc error\n");
- return -1;
- }
- pwm_combo0 = bconf->bl_pwm_combo0;
- pwm_combo1 = bconf->bl_pwm_combo1;
- pwm_combo0->index = 0;
- pwm_combo1->index = 1;
-
- pwm_combo0->level_max = ext_lcd->pwm_level_max;
- pwm_combo0->level_min = ext_lcd->pwm_level_min;
- pwm_combo1->level_max = ext_lcd->pwm2_level_max;
- pwm_combo1->level_min = ext_lcd->pwm2_level_min;
-
- pwm_combo0->pwm_method = ext_lcd->pwm_method;
- pwm_combo0->pwm_port = ext_lcd->pwm_port;
- pwm_combo0->pwm_freq = ext_lcd->pwm_freq;
- pwm_combo0->pwm_duty_max = ext_lcd->pwm_duty_max;
- pwm_combo0->pwm_duty_min = ext_lcd->pwm_duty_min;
- pwm_combo0->pwm_gpio = ext_lcd->pwm_gpio;
- pwm_combo0->pwm_gpio_off = ext_lcd->pwm_gpio_off;
- pwm_combo1->pwm_method = ext_lcd->pwm2_method;
- pwm_combo1->pwm_port = ext_lcd->pwm2_port;
- pwm_combo1->pwm_freq = ext_lcd->pwm2_freq;
- pwm_combo1->pwm_duty_max = ext_lcd->pwm2_duty_max;
- pwm_combo1->pwm_duty_min = ext_lcd->pwm2_duty_min;
- pwm_combo1->pwm_gpio = ext_lcd->pwm2_gpio;
- pwm_combo1->pwm_gpio_off = ext_lcd->pwm2_gpio_off;
- bconf->pwm_on_delay = ext_lcd->pwm_on_delay;
- bconf->pwm_off_delay = ext_lcd->pwm_off_delay;
-
- pwm_combo0->pwm_duty = pwm_combo0->pwm_duty_min;
- pwm_combo1->pwm_duty = pwm_combo1->pwm_duty_min;
- /* bl_pwm_config_init(pwm_combo0);
- bl_pwm_config_init(pwm_combo1); */
- break;
-#ifdef CONFIG_AML_LOCAL_DIMMING
- case BL_CTRL_LOCAL_DIMMING:
- aml_ldim_probe(NULL, 1);
- break;
-#endif
-#ifdef CONFIG_AML_BL_EXTERN
- case BL_CTRL_EXTERN:
- aml_bl_extern_device_load(NULL, bconf->bl_extern_index);
- break;
-#endif
- default:
- if (lcd_debug_print_flag)
- LCDPR("bl: invalid backlight control method\n");
- break;
- }
-
- return 0;
-}
-
-static int bl_config_load_from_unifykey(const void *dt_blob, struct bl_config_s *bconf)
-{
- unsigned char *para;
- int key_len, len;
- unsigned char *p;
- const char *str;
- struct aml_lcd_unifykey_header_s bl_header;
- struct bl_pwm_config_s *bl_pwm;
- struct bl_pwm_config_s *pwm_combo0, *pwm_combo1;
- int ret;
-
- para = (unsigned char *)malloc(sizeof(unsigned char) * LCD_UKEY_BL_SIZE);
- if (!para) {
- LCDERR("bl: %s: Not enough memory\n", __func__);
- return -1;
- }
-
- key_len = LCD_UKEY_BL_SIZE;
- memset(para, 0, (sizeof(unsigned char) * key_len));
- ret = aml_lcd_unifykey_get("backlight", para, &key_len);
- if (ret) {
- free(para);
- return -1;
- }
-
- /* step 1: check header */
- len = LCD_UKEY_HEAD_SIZE;
- ret = aml_lcd_unifykey_len_check(key_len, len);
- if (ret) {
- LCDERR("unifykey header length is incorrect\n");
- free(para);
- return -1;
- }
-
- aml_lcd_unifykey_header_check(para, &bl_header);
- LCDPR("bl: unifykey version: 0x%04x\n", bl_header.version);
- switch (bl_header.version) {
- case 2:
- len = 10 + 30 + 12 + 8 + 32 + 10;
- break;
- default:
- len = 10 + 30 + 12 + 8 + 32;
- break;
- }
- if (lcd_debug_print_flag) {
- LCDPR("bl: unifykey header:\n");
- LCDPR("bl: crc32 = 0x%08x\n", bl_header.crc32);
- LCDPR("bl: data_len = %d\n", bl_header.data_len);
- LCDPR("bl: reserved = 0x%04x\n", bl_header.reserved);
- }
-
- /* step 2: check backlight parameters */
- ret = aml_lcd_unifykey_len_check(key_len, len);
- if (ret) {
- LCDERR("bl: unifykey length is incorrect\n");
- free(para);
- return -1;
- }
-
- /* basic: 30byte */
- p = para;
- *(p + LCD_UKEY_BL_NAME - 1) = '\0'; /* ensure string ending */
- str = (const char *)(p + LCD_UKEY_HEAD_SIZE);
- strcpy(bconf->name, str);
-
- /* level: 12byte */
- bconf->level_default = (*(p + LCD_UKEY_BL_LEVEL_UBOOT) |
- ((*(p + LCD_UKEY_BL_LEVEL_UBOOT + 1)) << 8));
- bconf->level_max = (*(p + LCD_UKEY_BL_LEVEL_MAX) |
- ((*(p + LCD_UKEY_BL_LEVEL_MAX + 1)) << 8));
- bconf->level_min = (*(p + LCD_UKEY_BL_LEVEL_MIN) |
- ((*(p + LCD_UKEY_BL_LEVEL_MIN + 1)) << 8));
- bconf->level_mid = (*(p + LCD_UKEY_BL_LEVEL_MID) |
- ((*(p + LCD_UKEY_BL_LEVEL_MID + 1)) << 8));
- bconf->level_mid_mapping = (*(p + LCD_UKEY_BL_LEVEL_MID_MAP) |
- ((*(p + LCD_UKEY_BL_LEVEL_MID_MAP + 1)) << 8));
-
- /* method: 8byte */
- bconf->method = *(p + LCD_UKEY_BL_METHOD);
- bconf->en_gpio = *(p + LCD_UKEY_BL_EN_GPIO);
- bconf->en_gpio_on = *(p + LCD_UKEY_BL_EN_GPIO_ON);
- bconf->en_gpio_off = *(p + LCD_UKEY_BL_EN_GPIO_OFF);
- bconf->power_on_delay = (*(p + LCD_UKEY_BL_ON_DELAY) |
- ((*(p + LCD_UKEY_BL_ON_DELAY + 1)) << 8));
- bconf->power_off_delay = (*(p + LCD_UKEY_BL_OFF_DELAY) |
- ((*(p + LCD_UKEY_BL_OFF_DELAY + 1)) << 8));
-
- /* pwm: 32byte */
- switch (bconf->method) {
- case BL_CTRL_PWM:
- bconf->bl_pwm = (struct bl_pwm_config_s *)malloc(sizeof(struct bl_pwm_config_s));
- if (bconf->bl_pwm == NULL) {
- LCDERR("bl: bl_pwm struct malloc error\n");
- free(para);
- return -1;
- }
- bl_pwm = bconf->bl_pwm;
- bl_pwm->index = 0;
-
- bl_pwm->level_max = bconf->level_max;
- bl_pwm->level_min = bconf->level_min;
-
- bconf->pwm_on_delay = (*(p + LCD_UKEY_BL_PWM_ON_DELAY) |
- ((*(p + LCD_UKEY_BL_PWM_ON_DELAY + 1)) << 8));
- bconf->pwm_off_delay = (*(p + LCD_UKEY_BL_PWM_OFF_DELAY) |
- ((*(p + LCD_UKEY_BL_PWM_OFF_DELAY + 1)) << 8));
- bl_pwm->pwm_method = *(p + LCD_UKEY_BL_PWM_METHOD);
- bl_pwm->pwm_port = *(p + LCD_UKEY_BL_PWM_PORT);
- bl_pwm->pwm_freq = (*(p + LCD_UKEY_BL_PWM_FREQ) |
- ((*(p + LCD_UKEY_BL_PWM_FREQ + 1)) << 8) |
- ((*(p + LCD_UKEY_BL_PWM_FREQ + 2)) << 8) |
- ((*(p + LCD_UKEY_BL_PWM_FREQ + 3)) << 8));
- if (bl_pwm->pwm_port == BL_PWM_VS) {
- if (bl_pwm->pwm_freq > 4) {
- LCDERR("bl: bl_pwm_vs wrong freq %d\n", bl_pwm->pwm_freq);
- bl_pwm->pwm_freq = BL_FREQ_VS_DEFAULT;
- }
- } else {
- if (bl_pwm->pwm_freq > XTAL_HALF_FREQ_HZ)
- bl_pwm->pwm_freq = XTAL_HALF_FREQ_HZ;
- }
- bl_pwm->pwm_duty_max = *(p + LCD_UKEY_BL_PWM_DUTY_MAX);
- bl_pwm->pwm_duty_min = *(p + LCD_UKEY_BL_PWM_DUTY_MIN);
- bl_pwm->pwm_gpio = *(p + LCD_UKEY_BL_PWM_GPIO);
- bl_pwm->pwm_gpio_off = *(p + LCD_UKEY_BL_PWM_GPIO_OFF);
-
- if (bl_header.version == 2)
- bconf->en_sequence_reverse =
- (*(p + LCD_UKEY_BL_CUST_VAL_0) |
- ((*(p + LCD_UKEY_BL_CUST_VAL_0 + 1)) << 8));
- else
- bconf->en_sequence_reverse = 0;
-
- bl_pwm->pwm_duty = bl_pwm->pwm_duty_min;
- /* bl_pwm_config_init(bl_pwm); */
- break;
- case BL_CTRL_PWM_COMBO:
- bconf->bl_pwm_combo0 = (struct bl_pwm_config_s *)malloc(sizeof(struct bl_pwm_config_s));
- if (bconf->bl_pwm_combo0 == NULL) {
- LCDERR("bl: bl_pwm_combo0 struct malloc error\n");
- free(para);
- return -1;
- }
- bconf->bl_pwm_combo1 = (struct bl_pwm_config_s *)malloc(sizeof(struct bl_pwm_config_s));
- if (bconf->bl_pwm_combo1 == NULL) {
- LCDERR("bl: bl_pwm_combo1 struct malloc error\n");
- free(para);
- return -1;
- }
- pwm_combo0 = bconf->bl_pwm_combo0;
- pwm_combo1 = bconf->bl_pwm_combo1;
- pwm_combo0->index = 0;
- pwm_combo1->index = 1;
-
- bconf->pwm_on_delay = (*(p + LCD_UKEY_BL_PWM_ON_DELAY) |
- ((*(p + LCD_UKEY_BL_PWM_ON_DELAY + 1)) << 8));
- bconf->pwm_off_delay = (*(p + LCD_UKEY_BL_PWM_OFF_DELAY) |
- ((*(p + LCD_UKEY_BL_PWM_OFF_DELAY + 1)) << 8));
- pwm_combo0->pwm_method = *(p + LCD_UKEY_BL_PWM_METHOD);
- pwm_combo0->pwm_port = *(p + LCD_UKEY_BL_PWM_PORT);
- pwm_combo0->pwm_freq = (*(p + LCD_UKEY_BL_PWM_FREQ) |
- ((*(p + LCD_UKEY_BL_PWM_FREQ + 1)) << 8) |
- ((*(p + LCD_UKEY_BL_PWM_FREQ + 2)) << 8) |
- ((*(p + LCD_UKEY_BL_PWM_FREQ + 3)) << 8));
- if (pwm_combo0->pwm_port == BL_PWM_VS) {
- if (pwm_combo0->pwm_freq > 4) {
- LCDERR("bl: bl_pwm_vs wrong freq %d\n", pwm_combo0->pwm_freq);
- pwm_combo0->pwm_freq = BL_FREQ_VS_DEFAULT;
- }
- } else {
- if (pwm_combo0->pwm_freq > XTAL_HALF_FREQ_HZ)
- pwm_combo0->pwm_freq = XTAL_HALF_FREQ_HZ;
- }
- pwm_combo0->pwm_duty_max = *(p + LCD_UKEY_BL_PWM_DUTY_MAX);
- pwm_combo0->pwm_duty_min = *(p + LCD_UKEY_BL_PWM_DUTY_MIN);
- pwm_combo0->pwm_gpio = *(p + LCD_UKEY_BL_PWM_GPIO);
- pwm_combo0->pwm_gpio_off = *(p + LCD_UKEY_BL_PWM_GPIO_OFF);
- pwm_combo1->pwm_method = *(p + LCD_UKEY_BL_PWM2_METHOD);
- pwm_combo1->pwm_port = *(p + LCD_UKEY_BL_PWM2_PORT);
- pwm_combo1->pwm_freq = (*(p + LCD_UKEY_BL_PWM2_FREQ) |
- ((*(p + LCD_UKEY_BL_PWM2_FREQ + 1)) << 8) |
- ((*(p + LCD_UKEY_BL_PWM2_FREQ + 2)) << 8) |
- ((*(p + LCD_UKEY_BL_PWM2_FREQ + 3)) << 8));
- if (pwm_combo1->pwm_port == BL_PWM_VS) {
- if (pwm_combo1->pwm_freq > 4) {
- LCDERR("bl: bl_pwm_vs wrong freq %d\n", pwm_combo1->pwm_freq);
- pwm_combo1->pwm_freq = BL_FREQ_VS_DEFAULT;
- }
- } else {
- if (pwm_combo1->pwm_freq > XTAL_HALF_FREQ_HZ)
- pwm_combo1->pwm_freq = XTAL_HALF_FREQ_HZ;
- }
- pwm_combo1->pwm_duty_max = *(p + LCD_UKEY_BL_PWM2_DUTY_MAX);
- pwm_combo1->pwm_duty_min = *(p + LCD_UKEY_BL_PWM2_DUTY_MIN);
- pwm_combo1->pwm_gpio = *(p + LCD_UKEY_BL_PWM2_GPIO);
- pwm_combo1->pwm_gpio_off = *(p + LCD_UKEY_BL_PWM2_GPIO_OFF);
-
- pwm_combo0->level_max = (*(p + LCD_UKEY_BL_PWM_LEVEL_MAX) |
- ((*(p + LCD_UKEY_BL_PWM_LEVEL_MAX + 1)) << 8));
- pwm_combo0->level_min = (*(p + LCD_UKEY_BL_PWM_LEVEL_MIN) |
- ((*(p + LCD_UKEY_BL_PWM_LEVEL_MIN + 1)) << 8));
- pwm_combo1->level_max = (*(p + LCD_UKEY_BL_PWM2_LEVEL_MAX) |
- ((*(p + LCD_UKEY_BL_PWM2_LEVEL_MAX + 1)) << 8));
- pwm_combo1->level_min = (*(p + LCD_UKEY_BL_PWM2_LEVEL_MIN) |
- ((*(p + LCD_UKEY_BL_PWM2_LEVEL_MIN + 1)) << 8));
-
- if (bl_header.version == 2)
- bconf->en_sequence_reverse = (*(p + LCD_UKEY_BL_CUST_VAL_0) |
- ((*(p + LCD_UKEY_BL_CUST_VAL_0 + 1)) << 8));
- else
- bconf->en_sequence_reverse = 0;
-
- pwm_combo0->pwm_duty = pwm_combo0->pwm_duty_min;
- pwm_combo1->pwm_duty = pwm_combo1->pwm_duty_min;
- /* bl_pwm_config_init(pwm_combo0);
- bl_pwm_config_init(pwm_combo1); */
- break;
-#ifdef CONFIG_AML_LOCAL_DIMMING
- case BL_CTRL_LOCAL_DIMMING:
- if (bl_header.version == 2) {
- ldim_config_load_from_unifykey(para);
- } else {
- LCDERR("bl: not support ldim for unifykey version: %d\n",
- bl_header.version);
- }
- aml_ldim_probe(dt_blob, 2);
- break;
-#endif
- default:
- break;
- }
-
- free(para);
- return 0;
-}
-
-static const char *bl_pinmux_str[] = {
- "bl_pwm_on_pin", /* 0 */
- "bl_pwm_vs_on_pin", /* 1 */
- "bl_pwm_combo_0_on_pin", /* 2 */
- "bl_pwm_combo_1_on_pin", /* 3 */
- "bl_pwm_combo_0_vs_on_pin", /* 4 */
- "bl_pwm_combo_1_vs_on_pin", /* 5 */
-};
-
-static int bl_pinmux_load_from_bsp(struct bl_config_s *bconf)
-{
- char propname[50];
- struct lcd_pinmux_ctrl_s *pinmux;
- unsigned int i, j;
- int pinmux_index = 0, set_cnt = 0, clr_cnt = 0;
- struct bl_pwm_config_s *bl_pwm;
- struct bl_pwm_config_s *pwm_combo0, *pwm_combo1;
-
- if (lcd_debug_print_flag)
- LCDPR("bl: %s\n", __func__);
- if (bconf->bl_pinmux == NULL) {
- LCDERR("bl: %s: bl_pinmux is NULL for lcd.c\n", __func__);
- return -1;
- }
-
- switch (bconf->method) {
- case BL_CTRL_PWM:
- bl_pwm = bconf->bl_pwm;
- if (bl_pwm->pwm_port == BL_PWM_VS)
- pinmux_index = 1;
- else
- pinmux_index = 0;
- sprintf(propname,"%s", bl_pinmux_str[pinmux_index]);
- pinmux = bconf->bl_pinmux;
- for (i = 0; i < LCD_PINMX_MAX; i++) {
- if (strncmp(pinmux->name, "invalid", 7) == 0)
- break;
- if (strncmp(pinmux->name, propname, strlen(propname)) == 0) {
- for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
- if (pinmux->pinmux_set[j][0] == LCD_PINMUX_END)
- break;
- bl_pwm->pinmux_set[j][0] = pinmux->pinmux_set[j][0];
- bl_pwm->pinmux_set[j][1] = pinmux->pinmux_set[j][1];
- set_cnt++;
- }
- for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
- if (pinmux->pinmux_clr[j][0] == LCD_PINMUX_END)
- break;
- bl_pwm->pinmux_clr[j][0] = pinmux->pinmux_clr[j][0];
- bl_pwm->pinmux_clr[j][1] = pinmux->pinmux_clr[j][1];
- clr_cnt++;
- }
- break;
- }
- pinmux++;
- }
- if (set_cnt < LCD_PINMUX_NUM) {
- bl_pwm->pinmux_set[set_cnt][0] = LCD_PINMUX_END;
- bl_pwm->pinmux_set[set_cnt][1] = 0x0;
- }
- if (clr_cnt < LCD_PINMUX_NUM) {
- bl_pwm->pinmux_clr[clr_cnt][0] = LCD_PINMUX_END;
- bl_pwm->pinmux_clr[clr_cnt][1] = 0x0;
- }
- break;
- case BL_CTRL_PWM_COMBO:
- pwm_combo0 = bconf->bl_pwm_combo0;
- pwm_combo1 = bconf->bl_pwm_combo1;
- if (pwm_combo0->pwm_port == BL_PWM_VS)
- sprintf(propname,"%s", bl_pinmux_str[4]);
- else
- sprintf(propname,"%s", bl_pinmux_str[2]);
-
- pinmux = bconf->bl_pinmux;
- for (i = 0; i < LCD_PINMX_MAX; i++) {
- if (strncmp(pinmux->name, "invalid", 7) == 0)
- break;
- if (strncmp(pinmux->name, propname, strlen(propname)) == 0) {
- for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
- if (pinmux->pinmux_set[j][0] == LCD_PINMUX_END)
- break;
- pwm_combo0->pinmux_set[j][0] = pinmux->pinmux_set[j][0];
- pwm_combo0->pinmux_set[j][1] = pinmux->pinmux_set[j][1];
- set_cnt++;
- }
- for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
- if (pinmux->pinmux_clr[j][0] == LCD_PINMUX_END)
- break;
- pwm_combo0->pinmux_clr[j][0] = pinmux->pinmux_clr[j][0];
- pwm_combo0->pinmux_clr[j][1] = pinmux->pinmux_clr[j][1];
- clr_cnt++;
- }
- break;
- }
- pinmux++;
- }
- if (set_cnt < LCD_PINMUX_NUM) {
- pwm_combo0->pinmux_set[set_cnt][0] = LCD_PINMUX_END;
- pwm_combo0->pinmux_set[set_cnt][1] = 0x0;
- }
- if (clr_cnt < LCD_PINMUX_NUM) {
- pwm_combo0->pinmux_clr[clr_cnt][0] = LCD_PINMUX_END;
- pwm_combo0->pinmux_clr[clr_cnt][1] = 0x0;
- }
-
- if (pwm_combo1->pwm_port == BL_PWM_VS)
- sprintf(propname,"%s", bl_pinmux_str[5]);
- else
- sprintf(propname,"%s", bl_pinmux_str[3]);
-
- pinmux = bconf->bl_pinmux;
- set_cnt = 0;
- clr_cnt = 0;
- for (i = 0; i < LCD_PINMX_MAX; i++) {
- if (strncmp(pinmux->name, "invalid", 7) == 0)
- break;
- if (strncmp(pinmux->name, propname, strlen(propname)) == 0) {
- for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
- if (pinmux->pinmux_set[j][0] == LCD_PINMUX_END)
- break;
- pwm_combo1->pinmux_set[j][0] = pinmux->pinmux_set[j][0];
- pwm_combo1->pinmux_set[j][1] = pinmux->pinmux_set[j][1];
- set_cnt++;
- }
- for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
- if (pinmux->pinmux_clr[j][0] == LCD_PINMUX_END)
- break;
- pwm_combo1->pinmux_clr[j][0] = pinmux->pinmux_clr[j][0];
- pwm_combo1->pinmux_clr[j][1] = pinmux->pinmux_clr[j][1];
- clr_cnt++;
- }
- break;
- }
- pinmux++;
- }
- if (set_cnt < LCD_PINMUX_NUM) {
- pwm_combo1->pinmux_set[set_cnt][0] = LCD_PINMUX_END;
- pwm_combo1->pinmux_set[set_cnt][1] = 0x0;
- }
- if (clr_cnt < LCD_PINMUX_NUM) {
- pwm_combo1->pinmux_clr[clr_cnt][0] = LCD_PINMUX_END;
- pwm_combo1->pinmux_clr[clr_cnt][1] = 0x0;
- }
- break;
- default:
- break;
- }
-
- if (lcd_debug_print_flag)
- bl_pinmux_print(bconf);
-
- return 0;
-}
-
-static int bl_init_load_from_dts(const void *dt_blob, struct bl_config_s *bconf)
-{
- int parent_offset;
- char *propdata;
- char *p;
- const char *str;
- int i, ret = 0;
-
- parent_offset = fdt_path_offset(dt_blob, "/backlight");
- if (parent_offset < 0) {
- LCDPR("bl: not find /backlight node %s\n", fdt_strerror(parent_offset));
- return -1;
- }
- propdata = (char *)fdt_getprop(dt_blob, parent_offset, "status", NULL);
- if (propdata == NULL) {
- LCDPR("bl: not find status, default to disabled\n");
- return -1;
- } else {
- if (strncmp(propdata, "okay", 2)) {
- LCDPR("bl: status disabled\n");
- return -1;
- }
- }
-
- /* gpio */
- i = 0;
- propdata = (char *)fdt_getprop(dt_blob, parent_offset, "bl_gpio_names", NULL);
- if (propdata == NULL) {
- LCDERR("bl: failed to get bl_gpio_names\n");
- } else {
- p = propdata;
- while (i < BL_GPIO_NUM_MAX) {
- if (i > 0)
- p += strlen(p) + 1;
- str = p;
- if (strlen(str) == 0)
- break;
- bl_gpio_probe(str, i);
- i++;
- }
- }
-
- /* pinmux */
- ret = bl_pinmux_load_from_bsp(bconf);
-
- return ret;
-}
-
-static int bl_init_load_from_bsp(struct bl_config_s *bconf)
-{
- int i, ret = 0;
-
- /* gpio */
- i = 0;
- while (i < BL_GPIO_NUM_MAX) {
- if (strcmp(bconf->gpio_name[i], "invalid") == 0)
- break;
- bl_gpio_probe(bconf->gpio_name[i], i);
- i++;
- }
-
- /* pinmux */
- ret = bl_pinmux_load_from_bsp(bconf);
-
- return ret;
-}
-
-int bl_config_load(const void *dt_blob, int load_id)
-{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- unsigned int index;
- char *bl_off_policy_str;
- char *bl_level_str;
- int ret;
-
- bl_status = 0;
-
- /* load bl config */
- if (load_id & 0x1) { /* dts */
- if (load_id & 0x10) { /* unifykey */
- if (lcd_debug_print_flag)
- LCDPR("bl: load bl_config from unifykey\n");
- ret = bl_config_load_from_unifykey(dt_blob, lcd_drv->bl_config);
- } else { /* dts */
- if (lcd_debug_print_flag)
- LCDPR("bl: load bl_config from dts\n");
- index = lcd_drv->lcd_config->backlight_index;
- if (index == 0xff) {
- lcd_drv->bl_config->method = BL_CTRL_MAX;
- LCDPR("bl: no backlight exist\n");
- return -1;
- }
- ret = bl_config_load_from_dts(dt_blob, index, lcd_drv->bl_config);
- }
- if (ret == 0)
- bl_init_load_from_dts(dt_blob, lcd_drv->bl_config);
- } else { /* bsp */
- if (load_id & 0x10) { /* unifykey */
- if (lcd_debug_print_flag)
- LCDPR("bl: load bl_config from unifykey\n");
- ret = bl_config_load_from_unifykey(dt_blob, lcd_drv->bl_config);
- } else { /* bsp */
- if (lcd_debug_print_flag)
- LCDPR("bl: load bl_config from bsp\n");
- ret = bl_config_load_from_bsp(lcd_drv->bl_config);
- }
- if (ret == 0)
- bl_init_load_from_bsp(lcd_drv->bl_config);
- }
- if (ret) {
- lcd_drv->bl_config->method = BL_CTRL_MAX;
- LCDPR("bl: invalid backlight config\n");
- return -1;
- }
- if (lcd_debug_print_flag) {
- bl_config_print();
- } else {
- LCDPR("bl: name: %s, method: %d\n",
- lcd_drv->bl_config->name,
- lcd_drv->bl_config->method);
- }
-
- /* get bl_off_policy */
- bl_off_policy = BL_OFF_POLICY_NONE;
- bl_off_policy_str = env_get("bl_off");
- if (bl_off_policy_str) {
- if (strncmp(bl_off_policy_str, "none", 2) == 0)
- bl_off_policy = BL_OFF_POLICY_NONE;
- else if (strncmp(bl_off_policy_str, "always", 2) == 0)
- bl_off_policy = BL_OFF_POLICY_ALWAYS;
- else if (strncmp(bl_off_policy_str, "once", 2) == 0)
- bl_off_policy = BL_OFF_POLICY_ONCE;
- LCDPR("bl: bl_off_policy: %s\n", bl_off_policy_str);
- }
-
- /* get bl_level */
- bl_level_str = env_get("bl_level");
- if (bl_level_str != NULL) {
- lcd_drv->bl_config->level_default = (int)simple_strtoul(bl_level_str, NULL, 10);
- LCDPR("bl: bl_level: %d\n", lcd_drv->bl_config->level_default);
- }
-
- return 0;
-}
-
diff --git a/drivers/amlogic/media/vout/lcd/lcd_clk_config.c b/drivers/amlogic/media/vout/lcd/lcd_clk_config.c
index 17b285a..34b45b3 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_clk_config.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_clk_config.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_clk_config.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -26,41 +11,78 @@
#include "lcd_clk_config.h"
#include "lcd_clk_ctrl.h"
-static struct lcd_clk_config_s clk_conf = { /* unit: kHz */
- /* IN-OUT parameters */
- .fin = FIN_FREQ,
- .fout = 0,
-
- /* pll parameters */
- .pll_mode = 0, /* txl */
- .pll_od_fb = 0,
- .pll_m = 0,
- .pll_n = 0,
- .pll_od1_sel = 0,
- .pll_od2_sel = 0,
- .pll_od3_sel = 0,
- .pll_pi_div_sel = 0, /* for tcon */
- .pll_level = 0,
- .ss_level = 0,
- .div_sel = 0,
- .xd = 0,
- .pll_fout = 0,
-
- /* clk path node parameters */
- .div_sel_max = 0,
- .xd_max = 0,
-
- .data = NULL,
-};
-
-struct lcd_clk_config_s *get_lcd_clk_config(void)
+struct lcd_clk_config_s *get_lcd_clk_config(struct aml_lcd_drv_s *pdrv)
{
- return &clk_conf;
+ struct lcd_clk_config_s *cconf;
+
+ if (!pdrv->clk_conf) {
+ LCDERR("[%d]: %s: lcd clk_config is null\n", pdrv->index, __func__);
+ return NULL;
+ }
+ cconf = (struct lcd_clk_config_s *)pdrv->clk_conf;
+ if (!cconf->data) {
+ LCDERR("[%d]: %s: lcd clk config data is null\n",
+ pdrv->index, __func__);
+ return NULL;
+ }
+
+ return cconf;
}
/* **********************************
* lcd controller operation
* ********************************** */
+static unsigned int error_abs(unsigned int a, unsigned int b)
+{
+ if (a >= b)
+ return (a - b);
+ else
+ return (b - a);
+}
+
+#define PLL_CLK_CHECK_MAX 2 /* MHz */
+static int lcd_clk_msr_check(int msr_id, unsigned int freq)
+{
+ unsigned int encl_clk_msr;
+
+ if (msr_id == -1)
+ return 0;
+
+ encl_clk_msr = clk_util_clk_msr(msr_id);
+ if (error_abs(freq, encl_clk_msr) >= PLL_CLK_CHECK_MAX) {
+ LCDERR("%s[%d]: msr_id, expected:%d, msr:%d\n",
+ __func__, msr_id, freq, encl_clk_msr);
+ return -1;
+ }
+
+ return 0;
+}
+
+static int lcd_pll_ss_level_generate(unsigned int *data,
+ unsigned int level, unsigned int step)
+{
+ unsigned int max = 10, val;
+ unsigned int i, j, temp, min;
+
+ if (!data)
+ return -1;
+
+ val = level * 1000;
+ min = 0;
+ for (i = 1; i <= max; i++) { //dep_sel
+ for (j = 1; j <= max; j++) { //str_m
+ temp = error_abs((i * j * step), val);
+ if (min > temp) {
+ min = temp;
+ data[0] = i;
+ data[1] = j;
+ }
+ }
+ }
+
+ return 0;
+}
+
static int lcd_pll_wait_lock(unsigned int reg, unsigned int lock_bit)
{
unsigned int pll_lock;
@@ -69,13 +91,14 @@
do {
udelay(50);
- pll_lock = lcd_hiu_getb(reg, lock_bit, 1);
+ pll_lock = lcd_ana_getb(reg, lock_bit, 1);
wait_loop--;
} while ((pll_lock == 0) && (wait_loop > 0));
if (pll_lock == 0)
ret = -1;
LCDPR("%s: pll_lock=%d, wait_loop=%d\n",
- __func__, pll_lock, (PLL_WAIT_LOCK_CNT - wait_loop));
+ __func__, pll_lock, (PLL_WAIT_LOCK_CNT - wait_loop));
+
return ret;
}
@@ -98,7 +121,7 @@
}
do {
udelay(50);
- pll_lock = lcd_hiu_getb(pll_ctrl, 31, 1);
+ pll_lock = lcd_ana_getb(pll_ctrl, 31, 1);
wait_loop--;
} while ((pll_lock != 1) && (wait_loop > 0));
@@ -106,11 +129,11 @@
goto pll_lock_end_g12a;
} else {
LCDPR("path: %d, pll try 1, lock: %d\n", path, pll_lock);
- lcd_hiu_setb(pll_ctrl3, 1, 31, 1);
+ lcd_ana_setb(pll_ctrl3, 1, 31, 1);
wait_loop = PLL_WAIT_LOCK_CNT_G12A;
do {
udelay(50);
- pll_lock = lcd_hiu_getb(pll_ctrl, 31, 1);
+ pll_lock = lcd_ana_getb(pll_ctrl, 31, 1);
wait_loop--;
} while ((pll_lock != 1) && (wait_loop > 0));
}
@@ -119,11 +142,11 @@
goto pll_lock_end_g12a;
} else {
LCDPR("path: %d, pll try 2, lock: %d\n", path, pll_lock);
- lcd_hiu_write(pll_ctrl6, 0x55540000);
+ lcd_ana_write(pll_ctrl6, 0x55540000);
wait_loop = PLL_WAIT_LOCK_CNT_G12A;
do {
udelay(50);
- pll_lock = lcd_hiu_getb(pll_ctrl, 31, 1);
+ pll_lock = lcd_ana_getb(pll_ctrl, 31, 1);
wait_loop--;
} while ((pll_lock != 1) && (wait_loop > 0));
}
@@ -137,20 +160,25 @@
return ret;
}
-static void lcd_set_gp0_pll_g12a(struct lcd_clk_config_s *cConf)
+static void lcd_set_gp0_pll_g12a(struct aml_lcd_drv_s *pdrv)
{
+ struct lcd_clk_config_s *cconf;
unsigned int pll_ctrl, pll_ctrl1, pll_ctrl3, pll_ctrl4, pll_ctrl6;
- int ret;
+ int ret, cnt = 0;
- if (lcd_debug_print_flag == 2)
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
LCDPR("%s\n", __func__);
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
pll_ctrl = ((1 << LCD_PLL_EN_GP0_G12A) |
- (cConf->pll_n << LCD_PLL_N_GP0_G12A) |
- (cConf->pll_m << LCD_PLL_M_GP0_G12A) |
- (cConf->pll_od1_sel << LCD_PLL_OD_GP0_G12A));
- pll_ctrl1 = (cConf->pll_frac << 0);
- if (cConf->pll_frac) {
+ (cconf->pll_n << LCD_PLL_N_GP0_G12A) |
+ (cconf->pll_m << LCD_PLL_M_GP0_G12A) |
+ (cconf->pll_od1_sel << LCD_PLL_OD_GP0_G12A));
+ pll_ctrl1 = (cconf->pll_frac << 0);
+ if (cconf->pll_frac) {
pll_ctrl |= (1 << 27);
pll_ctrl3 = 0x6a285c00;
pll_ctrl4 = 0x65771290;
@@ -161,39 +189,48 @@
pll_ctrl6 = 0x56540000;
}
- lcd_hiu_write(HHI_GP0_PLL_CNTL0, pll_ctrl);
- lcd_hiu_write(HHI_GP0_PLL_CNTL1, pll_ctrl1);
- lcd_hiu_write(HHI_GP0_PLL_CNTL2, 0x00);
- lcd_hiu_write(HHI_GP0_PLL_CNTL3, pll_ctrl3);
- lcd_hiu_write(HHI_GP0_PLL_CNTL4, pll_ctrl4);
- lcd_hiu_write(HHI_GP0_PLL_CNTL5, 0x39272000);
- lcd_hiu_write(HHI_GP0_PLL_CNTL6, pll_ctrl6);
- lcd_hiu_setb(HHI_GP0_PLL_CNTL0, 1, LCD_PLL_RST_GP0_G12A, 1);
+set_gp0_pll_retry_g12a:
+ lcd_ana_write(HHI_GP0_PLL_CNTL0, pll_ctrl);
+ lcd_ana_write(HHI_GP0_PLL_CNTL1, pll_ctrl1);
+ lcd_ana_write(HHI_GP0_PLL_CNTL2, 0x00);
+ lcd_ana_write(HHI_GP0_PLL_CNTL3, pll_ctrl3);
+ lcd_ana_write(HHI_GP0_PLL_CNTL4, pll_ctrl4);
+ lcd_ana_write(HHI_GP0_PLL_CNTL5, 0x39272000);
+ lcd_ana_write(HHI_GP0_PLL_CNTL6, pll_ctrl6);
+ lcd_ana_setb(HHI_GP0_PLL_CNTL0, 1, LCD_PLL_RST_GP0_G12A, 1);
udelay(100);
- lcd_hiu_setb(HHI_GP0_PLL_CNTL0, 0, LCD_PLL_RST_GP0_G12A, 1);
+ lcd_ana_setb(HHI_GP0_PLL_CNTL0, 0, LCD_PLL_RST_GP0_G12A, 1);
ret = lcd_pll_wait_lock_g12a(1);
- if (ret)
+ if (ret) {
+ if (cnt++ < PLL_RETRY_MAX)
+ goto set_gp0_pll_retry_g12a;
LCDERR("gp0_pll lock failed\n");
+ }
}
-static void lcd_set_hpll_g12a(struct lcd_clk_config_s *cConf)
+static void lcd_set_hpll_g12a(struct aml_lcd_drv_s *pdrv)
{
+ struct lcd_clk_config_s *cconf;
unsigned int pll_ctrl, pll_ctrl1, pll_ctrl3, pll_ctrl4, pll_ctrl6;
- int ret;
+ int ret, cnt = 0;
- if (lcd_debug_print_flag == 2)
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
LCDPR("%s\n", __func__);
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
pll_ctrl = ((1 << LCD_PLL_EN_HPLL_G12A) |
(1 << 25) | /* clk out gate */
- (cConf->pll_n << LCD_PLL_N_HPLL_G12A) |
- (cConf->pll_m << LCD_PLL_M_HPLL_G12A) |
- (cConf->pll_od1_sel << LCD_PLL_OD1_HPLL_G12A) |
- (cConf->pll_od2_sel << LCD_PLL_OD2_HPLL_G12A) |
- (cConf->pll_od3_sel << LCD_PLL_OD3_HPLL_G12A));
- pll_ctrl1 = (cConf->pll_frac << 0);
- if (cConf->pll_frac) {
+ (cconf->pll_n << LCD_PLL_N_HPLL_G12A) |
+ (cconf->pll_m << LCD_PLL_M_HPLL_G12A) |
+ (cconf->pll_od1_sel << LCD_PLL_OD1_HPLL_G12A) |
+ (cconf->pll_od2_sel << LCD_PLL_OD2_HPLL_G12A) |
+ (cconf->pll_od3_sel << LCD_PLL_OD3_HPLL_G12A));
+ pll_ctrl1 = (cconf->pll_frac << 0);
+ if (cconf->pll_frac) {
pll_ctrl |= (1 << 27);
pll_ctrl3 = 0x6a285c00;
pll_ctrl4 = 0x65771290;
@@ -204,36 +241,45 @@
pll_ctrl6 = 0x56540000;
}
- lcd_hiu_write(HHI_HDMI_PLL_CNTL0, pll_ctrl);
- lcd_hiu_write(HHI_HDMI_PLL_CNTL1, pll_ctrl1);
- lcd_hiu_write(HHI_HDMI_PLL_CNTL2, 0x00);
- lcd_hiu_write(HHI_HDMI_PLL_CNTL3, pll_ctrl3);
- lcd_hiu_write(HHI_HDMI_PLL_CNTL4, pll_ctrl4);
- lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x39272000);
- lcd_hiu_write(HHI_HDMI_PLL_CNTL6, pll_ctrl6);
- lcd_hiu_setb(HHI_HDMI_PLL_CNTL0, 1, LCD_PLL_RST_HPLL_G12A, 1);
+set_hpll_pll_retry_g12a:
+ lcd_ana_write(HHI_HDMI_PLL_CNTL0, pll_ctrl);
+ lcd_ana_write(HHI_HDMI_PLL_CNTL1, pll_ctrl1);
+ lcd_ana_write(HHI_HDMI_PLL_CNTL2, 0x00);
+ lcd_ana_write(HHI_HDMI_PLL_CNTL3, pll_ctrl3);
+ lcd_ana_write(HHI_HDMI_PLL_CNTL4, pll_ctrl4);
+ lcd_ana_write(HHI_HDMI_PLL_CNTL5, 0x39272000);
+ lcd_ana_write(HHI_HDMI_PLL_CNTL6, pll_ctrl6);
+ lcd_ana_setb(HHI_HDMI_PLL_CNTL0, 1, LCD_PLL_RST_HPLL_G12A, 1);
udelay(100);
- lcd_hiu_setb(HHI_HDMI_PLL_CNTL0, 0, LCD_PLL_RST_HPLL_G12A, 1);
+ lcd_ana_setb(HHI_HDMI_PLL_CNTL0, 0, LCD_PLL_RST_HPLL_G12A, 1);
ret = lcd_pll_wait_lock_g12a(0);
- if (ret)
+ if (ret) {
+ if (cnt++ < PLL_RETRY_MAX)
+ goto set_hpll_pll_retry_g12a;
LCDERR("hpll lock failed\n");
+ }
}
-static void lcd_set_gp0_pll_g12b(struct lcd_clk_config_s *cConf)
+static void lcd_set_gp0_pll_g12b(struct aml_lcd_drv_s *pdrv)
{
+ struct lcd_clk_config_s *cconf;
unsigned int pll_ctrl, pll_ctrl1, pll_ctrl3, pll_ctrl4, pll_ctrl6;
- int ret;
+ int ret, cnt = 0;
- if (lcd_debug_print_flag == 2)
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
LCDPR("%s\n", __func__);
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
pll_ctrl = ((1 << LCD_PLL_EN_GP0_G12A) |
- (cConf->pll_n << LCD_PLL_N_GP0_G12A) |
- (cConf->pll_m << LCD_PLL_M_GP0_G12A) |
- (cConf->pll_od1_sel << LCD_PLL_OD_GP0_G12A));
- pll_ctrl1 = (cConf->pll_frac << 0);
- if (cConf->pll_frac) {
+ (cconf->pll_n << LCD_PLL_N_GP0_G12A) |
+ (cconf->pll_m << LCD_PLL_M_GP0_G12A) |
+ (cconf->pll_od1_sel << LCD_PLL_OD_GP0_G12A));
+ pll_ctrl1 = (cconf->pll_frac << 0);
+ if (cconf->pll_frac) {
pll_ctrl |= (1 << 27);
pll_ctrl3 = 0x6a285c00;
pll_ctrl4 = 0x65771290;
@@ -244,39 +290,48 @@
pll_ctrl6 = 0x56540000;
}
- lcd_hiu_write(HHI_GP0_PLL_CNTL0, pll_ctrl);
- lcd_hiu_write(HHI_GP0_PLL_CNTL1, pll_ctrl1);
- lcd_hiu_write(HHI_GP0_PLL_CNTL2, 0x00);
- lcd_hiu_write(HHI_GP0_PLL_CNTL3, pll_ctrl3);
- lcd_hiu_write(HHI_GP0_PLL_CNTL4, pll_ctrl4);
- lcd_hiu_write(HHI_GP0_PLL_CNTL5, 0x39272000);
- lcd_hiu_write(HHI_GP0_PLL_CNTL6, pll_ctrl6);
- lcd_hiu_setb(HHI_GP0_PLL_CNTL0, 1, LCD_PLL_RST_GP0_G12A, 1);
+set_gp0_pll_retry_g12b:
+ lcd_ana_write(HHI_GP0_PLL_CNTL0, pll_ctrl);
+ lcd_ana_write(HHI_GP0_PLL_CNTL1, pll_ctrl1);
+ lcd_ana_write(HHI_GP0_PLL_CNTL2, 0x00);
+ lcd_ana_write(HHI_GP0_PLL_CNTL3, pll_ctrl3);
+ lcd_ana_write(HHI_GP0_PLL_CNTL4, pll_ctrl4);
+ lcd_ana_write(HHI_GP0_PLL_CNTL5, 0x39272000);
+ lcd_ana_write(HHI_GP0_PLL_CNTL6, pll_ctrl6);
+ lcd_ana_setb(HHI_GP0_PLL_CNTL0, 1, LCD_PLL_RST_GP0_G12A, 1);
udelay(100);
- lcd_hiu_setb(HHI_GP0_PLL_CNTL0, 0, LCD_PLL_RST_GP0_G12A, 1);
+ lcd_ana_setb(HHI_GP0_PLL_CNTL0, 0, LCD_PLL_RST_GP0_G12A, 1);
ret = lcd_pll_wait_lock(HHI_GP0_PLL_CNTL0, LCD_PLL_LOCK_GP0_G12A);
- if (ret)
+ if (ret) {
+ if (cnt++ < PLL_RETRY_MAX)
+ goto set_gp0_pll_retry_g12b;
LCDERR("gp0_pll lock failed\n");
+ }
}
-static void lcd_set_hpll_g12b(struct lcd_clk_config_s *cConf)
+static void lcd_set_hpll_g12b(struct aml_lcd_drv_s *pdrv)
{
+ struct lcd_clk_config_s *cconf;
unsigned int pll_ctrl, pll_ctrl1, pll_ctrl3, pll_ctrl4, pll_ctrl6;
- int ret;
+ int ret, cnt = 0;
- if (lcd_debug_print_flag == 2)
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
LCDPR("%s\n", __func__);
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
pll_ctrl = ((1 << LCD_PLL_EN_HPLL_G12A) |
(1 << 25) | /* clk out gate */
- (cConf->pll_n << LCD_PLL_N_HPLL_G12A) |
- (cConf->pll_m << LCD_PLL_M_HPLL_G12A) |
- (cConf->pll_od1_sel << LCD_PLL_OD1_HPLL_G12A) |
- (cConf->pll_od2_sel << LCD_PLL_OD2_HPLL_G12A) |
- (cConf->pll_od3_sel << LCD_PLL_OD3_HPLL_G12A));
- pll_ctrl1 = (cConf->pll_frac << 0);
- if (cConf->pll_frac) {
+ (cconf->pll_n << LCD_PLL_N_HPLL_G12A) |
+ (cconf->pll_m << LCD_PLL_M_HPLL_G12A) |
+ (cconf->pll_od1_sel << LCD_PLL_OD1_HPLL_G12A) |
+ (cconf->pll_od2_sel << LCD_PLL_OD2_HPLL_G12A) |
+ (cconf->pll_od3_sel << LCD_PLL_OD3_HPLL_G12A));
+ pll_ctrl1 = (cconf->pll_frac << 0);
+ if (cconf->pll_frac) {
pll_ctrl |= (1 << 27);
pll_ctrl3 = 0x6a285c00;
pll_ctrl4 = 0x65771290;
@@ -287,40 +342,697 @@
pll_ctrl6 = 0x56540000;
}
- lcd_hiu_write(HHI_HDMI_PLL_CNTL0, pll_ctrl);
- lcd_hiu_write(HHI_HDMI_PLL_CNTL1, pll_ctrl1);
- lcd_hiu_write(HHI_HDMI_PLL_CNTL2, 0x00);
- lcd_hiu_write(HHI_HDMI_PLL_CNTL3, pll_ctrl3);
- lcd_hiu_write(HHI_HDMI_PLL_CNTL4, pll_ctrl4);
- lcd_hiu_write(HHI_HDMI_PLL_CNTL5, 0x39272000);
- lcd_hiu_write(HHI_HDMI_PLL_CNTL6, pll_ctrl6);
- lcd_hiu_setb(HHI_HDMI_PLL_CNTL0, 1, LCD_PLL_RST_HPLL_G12A, 1);
+set_hpll_pll_retry_g12b:
+ lcd_ana_write(HHI_HDMI_PLL_CNTL0, pll_ctrl);
+ lcd_ana_write(HHI_HDMI_PLL_CNTL1, pll_ctrl1);
+ lcd_ana_write(HHI_HDMI_PLL_CNTL2, 0x00);
+ lcd_ana_write(HHI_HDMI_PLL_CNTL3, pll_ctrl3);
+ lcd_ana_write(HHI_HDMI_PLL_CNTL4, pll_ctrl4);
+ lcd_ana_write(HHI_HDMI_PLL_CNTL5, 0x39272000);
+ lcd_ana_write(HHI_HDMI_PLL_CNTL6, pll_ctrl6);
+ lcd_ana_setb(HHI_HDMI_PLL_CNTL0, 1, LCD_PLL_RST_HPLL_G12A, 1);
udelay(100);
- lcd_hiu_setb(HHI_HDMI_PLL_CNTL0, 0, LCD_PLL_RST_HPLL_G12A, 1);
+ lcd_ana_setb(HHI_HDMI_PLL_CNTL0, 0, LCD_PLL_RST_HPLL_G12A, 1);
ret = lcd_pll_wait_lock(HHI_HDMI_PLL_CNTL0, LCD_PLL_LOCK_HPLL_G12A);
- if (ret)
+ if (ret) {
+ if (cnt++ < PLL_RETRY_MAX)
+ goto set_hpll_pll_retry_g12b;
LCDERR("hpll lock failed\n");
+ }
}
-static void lcd_set_vid_pll_div(struct lcd_clk_config_s *cConf)
+static void lcd_set_pll_ss_level_tl1(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+ unsigned int level, pll_ctrl2;
+ unsigned int dep_sel, str_m;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ level = cconf->ss_level;
+ pll_ctrl2 = lcd_ana_read(HHI_TCON_PLL_CNTL2);
+ pll_ctrl2 &= ~((1 << 15) | (0xf << 16) | (0xf << 28));
+
+ if (level > 0) {
+ dep_sel = pll_ss_reg_tl1[level][0];
+ str_m = pll_ss_reg_tl1[level][1];
+ dep_sel = (dep_sel > 10) ? 10 : dep_sel;
+ str_m = (str_m > 10) ? 10 : str_m;
+ pll_ctrl2 |= ((1 << 15) | (dep_sel << 28) | (str_m << 16));
+ }
+ lcd_ana_write(HHI_TCON_PLL_CNTL2, pll_ctrl2);
+
+ LCDPR("set pll spread spectrum: %s\n", lcd_ss_level_table_tl1[level]);
+}
+
+static void lcd_set_pll_ss_advance_tl1(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+ unsigned int pll_ctrl2;
+ unsigned int freq, mode;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ freq = cconf->ss_freq;
+ mode = cconf->ss_mode;
+ pll_ctrl2 = lcd_ana_read(HHI_TCON_PLL_CNTL2);
+ pll_ctrl2 &= ~(0x7 << 24); /* ss_freq */
+ pll_ctrl2 |= (freq << 24);
+ pll_ctrl2 &= ~(0x3 << 22); /* ss_mode */
+ pll_ctrl2 |= (mode << 22);
+ lcd_ana_write(HHI_TCON_PLL_CNTL2, pll_ctrl2);
+
+ LCDPR("set pll spread spectrum: freq=%d, mode=%d\n", freq, mode);
+}
+
+static void lcd_set_pll_tl1(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+ unsigned int pll_ctrl, pll_ctrl1;
+ unsigned int tcon_div_sel;
+ int ret, cnt = 0;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
+ LCDPR("%s\n", __func__);
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ tcon_div_sel = cconf->pll_tcon_div_sel;
+ pll_ctrl = ((0x3 << 17) | /* gate ctrl */
+ (tcon_div[tcon_div_sel][2] << 16) |
+ (cconf->pll_n << LCD_PLL_N_TL1) |
+ (cconf->pll_m << LCD_PLL_M_TL1) |
+ (cconf->pll_od3_sel << LCD_PLL_OD3_TL1) |
+ (cconf->pll_od2_sel << LCD_PLL_OD2_TL1) |
+ (cconf->pll_od1_sel << LCD_PLL_OD1_TL1));
+ pll_ctrl1 = (1 << 28) |
+ (tcon_div[tcon_div_sel][0] << 22) |
+ (tcon_div[tcon_div_sel][1] << 21) |
+ ((1 << 20) | /* sdm_en */
+ (cconf->pll_frac << 0));
+
+set_pll_retry_tl1:
+ lcd_ana_write(HHI_TCON_PLL_CNTL0, pll_ctrl);
+ udelay(10);
+ lcd_ana_setb(HHI_TCON_PLL_CNTL0, 1, LCD_PLL_RST_TL1, 1);
+ udelay(10);
+ lcd_ana_setb(HHI_TCON_PLL_CNTL0, 1, LCD_PLL_EN_TL1, 1);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL1, pll_ctrl1);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL2, 0x0000110c);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL3, 0x10051400);
+ udelay(10);
+ lcd_ana_setb(HHI_TCON_PLL_CNTL4, 0x0100c0, 0, 24);
+ udelay(10);
+ lcd_ana_setb(HHI_TCON_PLL_CNTL4, 0x8300c0, 0, 24);
+ udelay(10);
+ lcd_ana_setb(HHI_TCON_PLL_CNTL0, 1, 26, 1);
+ udelay(10);
+ lcd_ana_setb(HHI_TCON_PLL_CNTL0, 0, LCD_PLL_RST_TL1, 1);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL2, 0x0000300c);
+
+ ret = lcd_pll_wait_lock(HHI_TCON_PLL_CNTL0, LCD_PLL_LOCK_TL1);
+ if (ret) {
+ if (cnt++ < PLL_RETRY_MAX)
+ goto set_pll_retry_tl1;
+ LCDERR("hpll lock failed\n");
+ } else {
+ udelay(100);
+ lcd_ana_setb(HHI_TCON_PLL_CNTL2, 1, 5, 1);
+ }
+
+ if (cconf->ss_level > 0) {
+ lcd_set_pll_ss_level_tl1(pdrv);
+ lcd_set_pll_ss_advance_tl1(pdrv);
+ }
+}
+
+static void lcd_set_pll_ss_level_t7(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+ unsigned int pll_ctrl2, offset;
+ unsigned int level, dep_sel, str_m;
+ unsigned int data[2] = {0, 0};
+ int ret;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ level = cconf->ss_level;
+ offset = cconf->pll_offset;
+ pll_ctrl2 = lcd_ana_read(ANACTRL_TCON_PLL0_CNTL2 + offset);
+ pll_ctrl2 &= ~((1 << 15) | (0xf << 16) | (0xf << 28));
+
+ if (level > 0) {
+ ret = lcd_pll_ss_level_generate(data, level, 500);
+ if (ret == 0) {
+ dep_sel = data[0];
+ str_m = data[1];
+ dep_sel = (dep_sel > 10) ? 10 : dep_sel;
+ str_m = (str_m > 10) ? 10 : str_m;
+ pll_ctrl2 |= ((1 << 15) | (dep_sel << 28) | (str_m << 16));
+ }
+ }
+
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL2 + offset, pll_ctrl2);
+
+ if (level > 0) {
+ LCDPR("[%d]: set pll spread spectrum: %dppm\n",
+ pdrv->index, (level * 1000));
+ } else {
+ LCDPR("[%d]: set pll spread spectrum: disable\n", pdrv->index);
+ }
+}
+
+static void lcd_set_pll_ss_advance_t7(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+ unsigned int pll_ctrl2, offset;
+ unsigned int freq, mode;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ freq = cconf->ss_freq;
+ mode = cconf->ss_mode;
+ offset = cconf->pll_offset;
+ pll_ctrl2 = lcd_ana_read(HHI_TCON_PLL_CNTL2 + offset);
+ pll_ctrl2 &= ~(0x7 << 24); /* ss_freq */
+ pll_ctrl2 |= (freq << 24);
+ pll_ctrl2 &= ~(0x3 << 22); /* ss_mode */
+ pll_ctrl2 |= (mode << 22);
+ lcd_ana_write(HHI_TCON_PLL_CNTL2 + offset, pll_ctrl2);
+
+ LCDPR("[%d]: set pll spread spectrum: freq=%d, mode=%d\n",
+ pdrv->index, freq, mode);
+}
+
+static void lcd_set_pll_t7(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+ unsigned int pll_ctrl, pll_ctrl1, pll_stts, offset;
+ unsigned int tcon_div_sel;
+ int ret, cnt = 0;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ tcon_div_sel = cconf->pll_tcon_div_sel;
+ pll_ctrl = ((0x3 << 17) | /* gate ctrl */
+ (tcon_div[tcon_div_sel][2] << 16) |
+ (cconf->pll_n << LCD_PLL_N_TL1) |
+ (cconf->pll_m << LCD_PLL_M_TL1) |
+ (cconf->pll_od3_sel << LCD_PLL_OD3_T7) |
+ (cconf->pll_od2_sel << LCD_PLL_OD2_T7) |
+ (cconf->pll_od1_sel << LCD_PLL_OD1_T7));
+ pll_ctrl1 = (1 << 28) |
+ (tcon_div[tcon_div_sel][0] << 22) |
+ (tcon_div[tcon_div_sel][1] << 21) |
+ ((1 << 20) | /* sdm_en */
+ (cconf->pll_frac << 0));
+
+ offset = cconf->pll_offset;
+ switch (cconf->pll_id) {
+ case 1:
+ pll_stts = ANACTRL_TCON_PLL1_STS;
+ break;
+ case 2:
+ pll_stts = ANACTRL_TCON_PLL2_STS;
+ break;
+ case 0:
+ default:
+ pll_stts = ANACTRL_TCON_PLL0_STS;
+ break;
+ }
+
+set_pll_retry_t7:
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL0 + offset, pll_ctrl);
+ udelay(10);
+ lcd_ana_setb(ANACTRL_TCON_PLL0_CNTL0 + offset, 1, LCD_PLL_RST_TL1, 1);
+ udelay(10);
+ lcd_ana_setb(ANACTRL_TCON_PLL0_CNTL0 + offset, 1, LCD_PLL_EN_TL1, 1);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL1 + offset, pll_ctrl1);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL2 + offset, 0x0000110c);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL3 + offset, 0x10051400);
+ udelay(10);
+ lcd_ana_setb(ANACTRL_TCON_PLL0_CNTL4 + offset, 0x0100c0, 0, 24);
+ udelay(10);
+ lcd_ana_setb(ANACTRL_TCON_PLL0_CNTL4 + offset, 0x8300c0, 0, 24);
+ udelay(10);
+ lcd_ana_setb(ANACTRL_TCON_PLL0_CNTL0 + offset, 1, 26, 1);
+ udelay(10);
+ lcd_ana_setb(ANACTRL_TCON_PLL0_CNTL0 + offset, 0, LCD_PLL_RST_TL1, 1);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL2 + offset, 0x0000300c);
+
+ ret = lcd_pll_wait_lock(pll_stts, LCD_PLL_LOCK_T7);
+ if (ret) {
+ if (cnt++ < PLL_RETRY_MAX)
+ goto set_pll_retry_t7;
+ LCDERR("[%d]: pll lock failed\n", pdrv->index);
+ } else {
+ udelay(100);
+ lcd_ana_setb(ANACTRL_TCON_PLL0_CNTL2 + offset, 1, 5, 1);
+ }
+
+ if (cconf->ss_level > 0) {
+ lcd_set_pll_ss_level_t7(pdrv);
+ lcd_set_pll_ss_advance_t7(pdrv);
+ }
+}
+
+static void lcd_prbs_set_pll_vx1_tl1(struct aml_lcd_drv_s *pdrv)
+{
+ int cnt = 0, ret;
+
+lcd_prbs_retry_pll_vx1_tl1:
+ lcd_ana_write(HHI_TCON_PLL_CNTL0, 0x000f04f7);
+ udelay(10);
+ lcd_ana_setb(HHI_TCON_PLL_CNTL0, 1, LCD_PLL_RST_TL1, 1);
+ udelay(10);
+ lcd_ana_setb(HHI_TCON_PLL_CNTL0, 1, LCD_PLL_EN_TL1, 1);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL1, 0x10110000);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL2, 0x00001108);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL3, 0x10051400);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL4, 0x010100c0);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL4, 0x038300c0);
+ udelay(10);
+ lcd_ana_setb(HHI_TCON_PLL_CNTL0, 1, 26, 1);
+ udelay(10);
+ lcd_ana_setb(HHI_TCON_PLL_CNTL0, 0, LCD_PLL_RST_TL1, 1);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL2, 0x00003008);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL2, 0x00003028);
+ udelay(10);
+
+ ret = lcd_pll_wait_lock(HHI_TCON_PLL_CNTL0, LCD_PLL_LOCK_TL1);
+ if (ret) {
+ if (cnt++ < PLL_RETRY_MAX)
+ goto lcd_prbs_retry_pll_vx1_tl1;
+ LCDERR("pll lock failed\n");
+ }
+
+ /* pll_div */
+ lcd_clk_setb(HHI_VIID_CLK_CNTL, 0, VCLK2_EN, 1);
+ udelay(5);
+
+ /* Disable the div output clock */
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 19, 1);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 15, 1);
+
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 18, 1);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 16, 2);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 15, 1);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 0, 14);
+
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 2, 16, 2);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 1, 15, 1);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0x739c, 0, 15);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 15, 1);
+
+ /* Enable the final output clock */
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 1, 19, 1);
+}
+
+static void lcd_prbs_set_pll_lvds_tl1(struct aml_lcd_drv_s *pdrv)
+{
+ int cnt = 0, ret;
+
+lcd_prbs_retry_pll_lvds_tl1:
+ lcd_ana_write(HHI_TCON_PLL_CNTL0, 0x008e049f);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL0, 0x208e049f);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL0, 0x3006049f);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL1, 0x10000000);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL2, 0x00001102);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL3, 0x10051400);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL4, 0x010100c0);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL4, 0x038300c0);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL0, 0x348e049f);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL0, 0x148e049f);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL2, 0x00003002);
+ udelay(10);
+ lcd_ana_write(HHI_TCON_PLL_CNTL2, 0x00003022);
+ udelay(10);
+
+ ret = lcd_pll_wait_lock(HHI_TCON_PLL_CNTL0, LCD_PLL_LOCK_TL1);
+ if (ret) {
+ if (cnt++ < PLL_RETRY_MAX)
+ goto lcd_prbs_retry_pll_lvds_tl1;
+ LCDERR("pll lock failed\n");
+ }
+
+ /* pll_div */
+ lcd_clk_setb(HHI_VIID_CLK_CNTL, 0, VCLK2_EN, 1);
+ udelay(5);
+
+ /* Disable the div output clock */
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 19, 1);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 15, 1);
+
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 18, 1);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 16, 2);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 15, 1);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 0, 14);
+
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 1, 16, 2);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 1, 15, 1);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0x3c78, 0, 15);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 15, 1);
+
+ /* Enable the final output clock */
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 1, 19, 1);
+}
+
+void lcd_prbs_config_clk_tl1(struct aml_lcd_drv_s *pdrv, unsigned int lcd_prbs_mode)
+{
+ if (lcd_prbs_mode == LCD_PRBS_MODE_VX1) {
+ lcd_prbs_set_pll_vx1_tl1(pdrv);
+ } else if (lcd_prbs_mode == LCD_PRBS_MODE_LVDS) {
+ lcd_prbs_set_pll_lvds_tl1(pdrv);
+ } else {
+ LCDERR("%s: unsupport lcd_prbs_mode %d\n",
+ __func__, lcd_prbs_mode);
+ return;
+ }
+
+ lcd_clk_setb(HHI_VIID_CLK_DIV, 0, VCLK2_XD, 8);
+ udelay(5);
+
+ /* select vid_pll_clk */
+ lcd_clk_setb(HHI_VIID_CLK_CNTL, 0, VCLK2_CLK_IN_SEL, 3);
+ lcd_clk_setb(HHI_VIID_CLK_CNTL, 1, VCLK2_EN, 1);
+ udelay(5);
+
+ /* [15:12] encl_clk_sel, select vclk2_div1 */
+ lcd_clk_setb(HHI_VIID_CLK_DIV, 8, ENCL_CLK_SEL, 4);
+ /* release vclk2_div_reset and enable vclk2_div */
+ lcd_clk_setb(HHI_VIID_CLK_DIV, 1, VCLK2_XD_EN, 2);
+ udelay(5);
+
+ lcd_clk_setb(HHI_VIID_CLK_CNTL, 1, VCLK2_DIV1_EN, 1);
+ lcd_clk_setb(HHI_VIID_CLK_CNTL, 1, VCLK2_SOFT_RST, 1);
+ udelay(10);
+ lcd_clk_setb(HHI_VIID_CLK_CNTL, 0, VCLK2_SOFT_RST, 1);
+ udelay(5);
+
+ /* enable CTS_ENCL clk gate */
+ lcd_clk_setb(HHI_VID_CLK_CNTL2, 1, ENCL_GATE_VCLK, 1);
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s ok\n", __func__);
+}
+
+static void lcd_prbs_set_pll_vx1_t7(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+ unsigned int pll_stts, offset;
+ unsigned int reg_vid_pll_div, reg_vid2_clk_ctrl;
+ int cnt = 0, ret;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ offset = cconf->pll_offset;
+ switch (cconf->pll_id) {
+ case 1:
+ pll_stts = ANACTRL_TCON_PLL1_STS;
+ reg_vid_pll_div = COMBO_DPHY_VID_PLL1_DIV;
+ reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK1_CTRL;
+ break;
+ case 2:
+ pll_stts = ANACTRL_TCON_PLL2_STS;
+ reg_vid_pll_div = COMBO_DPHY_VID_PLL2_DIV;
+ reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK2_CTRL;
+ break;
+ case 0:
+ default:
+ pll_stts = ANACTRL_TCON_PLL0_STS;
+ reg_vid_pll_div = COMBO_DPHY_VID_PLL0_DIV;
+ reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK0_CTRL;
+ break;
+ }
+
+lcd_prbs_retry_pll_vx1_t7:
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL0 + offset, 0x000f04f7);
+ udelay(10);
+ lcd_ana_setb(ANACTRL_TCON_PLL0_CNTL0 + offset, 1, LCD_PLL_RST_TL1, 1);
+ udelay(10);
+ lcd_ana_setb(ANACTRL_TCON_PLL0_CNTL0 + offset, 1, LCD_PLL_EN_TL1, 1);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL1 + offset, 0x10110000);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL2 + offset, 0x00001108);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL3 + offset, 0x10051400);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL4 + offset, 0x010100c0);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL4 + offset, 0x038300c0);
+ udelay(10);
+ lcd_ana_setb(ANACTRL_TCON_PLL0_CNTL0 + offset, 1, 26, 1);
+ udelay(10);
+ lcd_ana_setb(ANACTRL_TCON_PLL0_CNTL0 + offset, 0, LCD_PLL_RST_TL1, 1);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL2 + offset, 0x00003008);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL2 + offset, 0x00003028);
+ udelay(10);
+
+ ret = lcd_pll_wait_lock(pll_stts, LCD_PLL_LOCK_T7);
+ if (ret) {
+ if (cnt++ < PLL_RETRY_MAX)
+ goto lcd_prbs_retry_pll_vx1_t7;
+ LCDERR("[%d]: pll lock failed\n", pdrv->index);
+ }
+
+ /* pll_div */
+ lcd_clk_setb(reg_vid2_clk_ctrl, 0, VCLK2_EN, 1);
+ udelay(5);
+
+ /* Disable the div output clock */
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 19, 1);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 15, 1);
+
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 18, 1);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 16, 2);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 15, 1);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 0, 14);
+
+ lcd_combo_dphy_setb(reg_vid_pll_div, 2, 16, 2);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 1, 15, 1);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0x739c, 0, 15);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 15, 1);
+
+ /* Enable the final output clock */
+ lcd_combo_dphy_setb(reg_vid_pll_div, 1, 19, 1);
+}
+
+static void lcd_prbs_set_pll_lvds_t7(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+ unsigned int pll_stts, offset;
+ unsigned int reg_vid_pll_div, reg_vid2_clk_ctrl;
+ int cnt = 0, ret;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ offset = cconf->pll_offset;
+ switch (cconf->pll_id) {
+ case 1:
+ pll_stts = ANACTRL_TCON_PLL1_STS;
+ reg_vid_pll_div = COMBO_DPHY_VID_PLL1_DIV;
+ reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK1_CTRL;
+ break;
+ case 2:
+ pll_stts = ANACTRL_TCON_PLL2_STS;
+ reg_vid_pll_div = COMBO_DPHY_VID_PLL2_DIV;
+ reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK2_CTRL;
+ break;
+ case 0:
+ default:
+ pll_stts = ANACTRL_TCON_PLL0_STS;
+ reg_vid_pll_div = COMBO_DPHY_VID_PLL0_DIV;
+ reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK0_CTRL;
+ break;
+ }
+
+lcd_prbs_retry_pll_lvds_t7:
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL0 + offset, 0x008e049f);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL0 + offset, 0x208e049f);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL0 + offset, 0x3006049f);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL1 + offset, 0x10000000);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL2 + offset, 0x00001102);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL3 + offset, 0x10051400);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL4 + offset, 0x010100c0);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL4 + offset, 0x038300c0);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL0 + offset, 0x348e049f);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL0 + offset, 0x148e049f);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL2 + offset, 0x00003002);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL0_CNTL2 + offset, 0x00003022);
+ udelay(10);
+
+ ret = lcd_pll_wait_lock(pll_stts, LCD_PLL_LOCK_T7);
+ if (ret) {
+ if (cnt++ < PLL_RETRY_MAX)
+ goto lcd_prbs_retry_pll_lvds_t7;
+ LCDERR("[%d]: pll lock failed\n", pdrv->index);
+ }
+
+ /* pll_div */
+ lcd_clk_setb(reg_vid2_clk_ctrl, 0, VCLK2_EN, 1);
+ udelay(5);
+
+ /* Disable the div output clock */
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 19, 1);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 15, 1);
+
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 18, 1);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 16, 2);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 15, 1);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 0, 14);
+
+ lcd_combo_dphy_setb(reg_vid_pll_div, 1, 16, 2);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 1, 15, 1);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0x3c78, 0, 15);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 15, 1);
+
+ /* Enable the final output clock */
+ lcd_combo_dphy_setb(reg_vid_pll_div, 1, 19, 1);
+}
+
+static void lcd_prbs_config_clk_t7(struct aml_lcd_drv_s *pdrv,
+ unsigned int lcd_prbs_mode)
+{
+ struct lcd_clk_config_s *cconf;
+ unsigned int reg_vid2_clk_div, reg_vid2_clk_ctrl, reg_vid_clk_ctrl2;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ switch (cconf->pll_id) {
+ case 1:
+ reg_vid2_clk_div = CLKCTRL_VIID_CLK1_DIV;
+ reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK1_CTRL;
+ reg_vid_clk_ctrl2 = CLKCTRL_VID_CLK1_CTRL2;
+ break;
+ case 2:
+ reg_vid2_clk_div = CLKCTRL_VIID_CLK2_DIV;
+ reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK2_CTRL;
+ reg_vid_clk_ctrl2 = CLKCTRL_VID_CLK2_CTRL2;
+ break;
+ case 0:
+ default:
+ reg_vid2_clk_div = CLKCTRL_VIID_CLK0_DIV;
+ reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK0_CTRL;
+ reg_vid_clk_ctrl2 = CLKCTRL_VID_CLK0_CTRL2;
+ break;
+ }
+
+ if (lcd_prbs_mode == LCD_PRBS_MODE_VX1) {
+ lcd_prbs_set_pll_vx1_t7(pdrv);
+ } else if (lcd_prbs_mode == LCD_PRBS_MODE_LVDS) {
+ lcd_prbs_set_pll_lvds_t7(pdrv);
+ } else {
+ LCDERR("[%d]: %s: unsupport lcd_prbs_mode %d\n",
+ pdrv->index, __func__, lcd_prbs_mode);
+ return;
+ }
+
+ lcd_clk_setb(reg_vid2_clk_div, 0, VCLK2_XD, 8);
+ udelay(5);
+
+ /* select vid_pll_clk */
+ lcd_clk_setb(reg_vid2_clk_ctrl, 0, VCLK2_CLK_IN_SEL, 3);
+ lcd_clk_setb(reg_vid2_clk_ctrl, 1, VCLK2_EN, 1);
+ udelay(5);
+
+ /* [15:12] encl_clk_sel, select vclk2_div1 */
+ lcd_clk_setb(reg_vid2_clk_div, 8, ENCL_CLK_SEL, 4);
+ /* release vclk2_div_reset and enable vclk2_div */
+ lcd_clk_setb(reg_vid2_clk_div, 1, VCLK2_XD_EN, 2);
+ udelay(5);
+
+ lcd_clk_setb(reg_vid2_clk_ctrl, 1, VCLK2_DIV1_EN, 1);
+ lcd_clk_setb(reg_vid2_clk_ctrl, 1, VCLK2_SOFT_RST, 1);
+ udelay(10);
+ lcd_clk_setb(reg_vid2_clk_ctrl, 0, VCLK2_SOFT_RST, 1);
+ udelay(5);
+
+ /* enable CTS_ENCL clk gate */
+ lcd_clk_setb(reg_vid_clk_ctrl2, 1, ENCL_GATE_VCLK, 1);
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s ok\n", pdrv->index, __func__);
+}
+
+static void lcd_set_vid_pll_div(struct lcd_clk_config_s *cconf)
{
unsigned int shift_val, shift_sel;
int i;
- if (lcd_debug_print_flag == 2)
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
LCDPR("%s\n", __func__);
- lcd_hiu_setb(HHI_VIID_CLK_CNTL, 0, VCLK2_EN, 1);
+ lcd_clk_setb(HHI_VIID_CLK_CNTL, 0, VCLK2_EN, 1);
udelay(5);
/* Disable the div output clock */
- lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, 0, 19, 1);
- lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, 0, 15, 1);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 19, 1);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 15, 1);
i = 0;
while (lcd_clk_div_table[i][0] != CLK_DIV_SEL_MAX) {
- if (cConf->div_sel == lcd_clk_div_table[i][0])
+ if (cconf->div_sel == lcd_clk_div_table[i][0])
break;
i++;
}
@@ -330,68 +1042,359 @@
shift_sel = lcd_clk_div_table[i][2];
if (shift_val == 0xffff) { /* if divide by 1 */
- lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, 1, 18, 1);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 1, 18, 1);
} else {
- lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, 0, 18, 1);
- lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, 0, 16, 2);
- lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, 0, 15, 1);
- lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, 0, 0, 14);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 18, 1);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 16, 2);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 15, 1);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 0, 14);
- lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, shift_sel, 16, 2);
- lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, 1, 15, 1);
- lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, shift_val, 0, 14);
- lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, 0, 15, 1);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, shift_sel, 16, 2);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 1, 15, 1);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, shift_val, 0, 15);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 0, 15, 1);
}
/* Enable the final output clock */
- lcd_hiu_setb(HHI_VID_PLL_CLK_DIV, 1, 19, 1);
+ lcd_ana_setb(HHI_VID_PLL_CLK_DIV, 1, 19, 1);
}
-static void lcd_set_vclk_crt(int lcd_type, struct lcd_clk_config_s *cConf)
+static void lcd_set_phy_dig_div_t7(struct aml_lcd_drv_s *pdrv)
{
- if (lcd_debug_print_flag == 2)
- LCDPR("%s\n", __func__);
+ struct lcd_clk_config_s *cconf;
+ unsigned int reg_edp_clk_div, reg_dphy_tx_ctrl1;
+ unsigned int port_sel, bit_div_en, bit_div0, bit_div1, bit_rst;
- /* setup the XD divider value */
- lcd_hiu_setb(HHI_VIID_CLK_DIV, (cConf->xd-1), VCLK2_XD, 8);
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ reg_edp_clk_div = COMBO_DPHY_EDP_PIXEL_CLK_DIV;
+ switch (cconf->pll_id) {
+ case 1:
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL1;
+ port_sel = 1;
+ bit_div_en = 25;
+ bit_div0 = 8;
+ bit_div1 = 12;
+ bit_rst = 20;
+ break;
+ case 2:
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL1;
+ port_sel = 2;
+ bit_div_en = 26;
+ bit_div0 = 0;
+ bit_div1 = 4;
+ bit_rst = 7;
+ break;
+ case 0:
+ default:
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1;
+ port_sel = 0;
+ bit_div_en = 24;
+ bit_div0 = 0;
+ bit_div1 = 4;
+ bit_rst = 19;
+ break;
+ }
+
+ lcd_reset_setb(RESETCTRL_RESET1_MASK, 0, bit_rst, 1);
+ lcd_reset_setb(RESETCTRL_RESET1_LEVEL, 0, bit_rst, 1);
+ udelay(1);
+ lcd_reset_setb(RESETCTRL_RESET1_LEVEL, 1, bit_rst, 1);
+ udelay(10);
+
+ // Enable dphy clock
+ lcd_combo_dphy_setb(reg_dphy_tx_ctrl1, 1, 0, 1);
+
+ switch (pdrv->config.basic.lcd_type) {
+ case LCD_EDP:
+ if (port_sel == 2) {
+ LCDERR("[%d]: %s: invalid port: %d\n",
+ pdrv->index, __func__, port_sel);
+ return;
+ }
+ // Disable edp_div clock
+ lcd_combo_dphy_setb(reg_edp_clk_div, 0, bit_div_en, 1);
+ lcd_combo_dphy_setb(reg_edp_clk_div, cconf->edp_div0, bit_div0, 4);
+ lcd_combo_dphy_setb(reg_edp_clk_div, cconf->edp_div1, bit_div1, 4);
+ // Enable edp_div clock
+ lcd_combo_dphy_setb(reg_edp_clk_div, 1, bit_div_en, 1);
+ // sel edp_div clock
+ lcd_combo_dphy_setb(reg_dphy_tx_ctrl1, 1, 4, 1);
+ break;
+ case LCD_MIPI:
+ case LCD_VBYONE:
+ if (port_sel == 2) {
+ LCDERR("[%d]: %s: invalid port: %d\n",
+ pdrv->index, __func__, port_sel);
+ return;
+ }
+ // sel pll clock
+ lcd_combo_dphy_setb(reg_dphy_tx_ctrl1, 0, 4, 1);
+ break;
+ default:
+ // sel pll clock
+ lcd_combo_dphy_setb(reg_dphy_tx_ctrl1, 0, 4, 1);
+ break;
+ }
+
+ // sel tcon_pll clock
+ lcd_combo_dphy_setb(reg_dphy_tx_ctrl1, 0, 5, 1);
+}
+
+static void lcd_set_vid_pll_div_t7(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+ unsigned int reg_vid_pll_div, reg_vid2_clk_ctrl;
+ unsigned int shift_val, shift_sel;
+ int i;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ switch (cconf->pll_id) {
+ case 1:
+ reg_vid_pll_div = COMBO_DPHY_VID_PLL1_DIV;
+ reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK1_CTRL;
+ break;
+ case 2:
+ reg_vid_pll_div = COMBO_DPHY_VID_PLL2_DIV;
+ reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK2_CTRL;
+ break;
+ case 0:
+ default:
+ reg_vid_pll_div = COMBO_DPHY_VID_PLL0_DIV;
+ reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK0_CTRL;
+ break;
+ }
+
+ lcd_clk_setb(reg_vid2_clk_ctrl, 0, VCLK2_EN, 1);
udelay(5);
+ /* Disable the div output clock */
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 19, 1);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 15, 1);
+
+ i = 0;
+ while (lcd_clk_div_table[i][0] != CLK_DIV_SEL_MAX) {
+ if (cconf->div_sel == lcd_clk_div_table[i][0])
+ break;
+ i++;
+ }
+ if (lcd_clk_div_table[i][0] == CLK_DIV_SEL_MAX)
+ LCDERR("[%d]: invalid clk divider\n", pdrv->index);
+ shift_val = lcd_clk_div_table[i][1];
+ shift_sel = lcd_clk_div_table[i][2];
+
+ if (shift_val == 0xffff) { /* if divide by 1 */
+ lcd_combo_dphy_setb(reg_vid_pll_div, 1, 18, 1);
+ } else {
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 18, 1);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 16, 2);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 15, 1);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 0, 14);
+
+ lcd_combo_dphy_setb(reg_vid_pll_div, shift_sel, 16, 2);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 1, 15, 1);
+ lcd_combo_dphy_setb(reg_vid_pll_div, shift_val, 0, 15);
+ lcd_combo_dphy_setb(reg_vid_pll_div, 0, 15, 1);
+ }
+ /* Enable the final output clock */
+ lcd_combo_dphy_setb(reg_vid_pll_div, 1, 19, 1);
+}
+
+static void lcd_set_vclk_crt(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
+ LCDPR("%s\n", __func__);
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+#ifdef CONFIG_AML_LCD_PXP
+ /* setup the XD divider value */
+ lcd_clk_setb(HHI_VIID_CLK_DIV, cconf->xd, VCLK2_XD, 8);
+ udelay(5);
/* select vid_pll_clk */
- lcd_hiu_setb(HHI_VIID_CLK_CNTL, cConf->data->vclk_sel,
+ lcd_clk_setb(HHI_VIID_CLK_CNTL, 7, VCLK2_CLK_IN_SEL, 3);
+#else
+ /* setup the XD divider value */
+ lcd_clk_setb(HHI_VIID_CLK_DIV, (cconf->xd - 1), VCLK2_XD, 8);
+ udelay(5);
+ /* select vid_pll_clk */
+ lcd_clk_setb(HHI_VIID_CLK_CNTL, cconf->data->vclk_sel,
VCLK2_CLK_IN_SEL, 3);
- lcd_hiu_setb(HHI_VIID_CLK_CNTL, 1, VCLK2_EN, 1);
+#endif
+ lcd_clk_setb(HHI_VIID_CLK_CNTL, 1, VCLK2_EN, 1);
udelay(2);
/* [15:12] encl_clk_sel, select vclk2_div1 */
- lcd_hiu_setb(HHI_VIID_CLK_DIV, 8, ENCL_CLK_SEL, 4);
+ lcd_clk_setb(HHI_VIID_CLK_DIV, 8, ENCL_CLK_SEL, 4);
/* release vclk2_div_reset and enable vclk2_div */
- lcd_hiu_setb(HHI_VIID_CLK_DIV, 1, VCLK2_XD_EN, 2);
+ lcd_clk_setb(HHI_VIID_CLK_DIV, 1, VCLK2_XD_EN, 2);
udelay(5);
- lcd_hiu_setb(HHI_VIID_CLK_CNTL, 1, VCLK2_DIV1_EN, 1);
- lcd_hiu_setb(HHI_VIID_CLK_CNTL, 1, VCLK2_SOFT_RST, 1);
+ lcd_clk_setb(HHI_VIID_CLK_CNTL, 1, VCLK2_DIV1_EN, 1);
+ lcd_clk_setb(HHI_VIID_CLK_CNTL, 1, VCLK2_SOFT_RST, 1);
udelay(10);
- lcd_hiu_setb(HHI_VIID_CLK_CNTL, 0, VCLK2_SOFT_RST, 1);
+ lcd_clk_setb(HHI_VIID_CLK_CNTL, 0, VCLK2_SOFT_RST, 1);
udelay(5);
/* enable CTS_ENCL clk gate */
- lcd_hiu_setb(HHI_VID_CLK_CNTL2, 1, ENCL_GATE_VCLK, 1);
+ lcd_clk_setb(HHI_VID_CLK_CNTL2, 1, ENCL_GATE_VCLK, 1);
+}
+
+static void lcd_set_vclk_crt_t7(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+ unsigned int reg_vid2_clk_div, reg_vid2_clk_ctrl, reg_vid_clk_ctrl2;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ switch (cconf->pll_id) {
+ case 1:
+ reg_vid2_clk_div = CLKCTRL_VIID_CLK1_DIV;
+ reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK1_CTRL;
+ reg_vid_clk_ctrl2 = CLKCTRL_VID_CLK1_CTRL2;
+ break;
+ case 2:
+ reg_vid2_clk_div = CLKCTRL_VIID_CLK2_DIV;
+ reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK2_CTRL;
+ reg_vid_clk_ctrl2 = CLKCTRL_VID_CLK2_CTRL2;
+ break;
+ case 0:
+ default:
+ reg_vid2_clk_div = CLKCTRL_VIID_CLK0_DIV;
+ reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK0_CTRL;
+ reg_vid_clk_ctrl2 = CLKCTRL_VID_CLK0_CTRL2;
+ break;
+ }
+
+ lcd_clk_write(reg_vid_clk_ctrl2, 0);
+ lcd_clk_write(reg_vid2_clk_ctrl, 0);
+ lcd_clk_write(reg_vid2_clk_div, 0);
+ udelay(5);
+
+#ifdef CONFIG_AML_LCD_PXP
+ /* setup the XD divider value */
+ lcd_clk_setb(reg_vid2_clk_div, cconf->xd, VCLK2_XD, 8);
+ udelay(5);
+ /* select vid_pll_clk */
+ lcd_clk_setb(reg_vid2_clk_ctrl, 7, VCLK2_CLK_IN_SEL, 3);
+#else
+ /* setup the XD divider value */
+ lcd_clk_setb(reg_vid2_clk_div, (cconf->xd - 1), VCLK2_XD, 8);
+ udelay(5);
+ /* select vid_pll_clk */
+ lcd_clk_setb(reg_vid2_clk_ctrl, cconf->data->vclk_sel,
+ VCLK2_CLK_IN_SEL, 3);
+#endif
+ lcd_clk_setb(reg_vid2_clk_ctrl, 1, VCLK2_EN, 1);
+ udelay(2);
+
+ /* [15:12] encl_clk_sel, select vclk2_div1 */
+ lcd_clk_setb(reg_vid2_clk_div, 8, ENCL_CLK_SEL, 4);
+ /* release vclk2_div_reset and enable vclk2_div */
+ lcd_clk_setb(reg_vid2_clk_div, 1, VCLK2_XD_EN, 2);
+ udelay(5);
+
+ lcd_clk_setb(reg_vid2_clk_ctrl, 1, VCLK2_DIV1_EN, 1);
+ lcd_clk_setb(reg_vid2_clk_ctrl, 1, VCLK2_SOFT_RST, 1);
+ udelay(10);
+ lcd_clk_setb(reg_vid2_clk_ctrl, 0, VCLK2_SOFT_RST, 1);
+ udelay(5);
+
+ /* enable CTS_ENCL clk gate */
+ lcd_clk_setb(reg_vid_clk_ctrl2, 1, ENCL_GATE_VCLK, 1);
}
static void lcd_set_dsi_meas_clk(void)
{
- lcd_hiu_setb(HHI_VDIN_MEAS_CLK_CNTL, 0, 21, 3);
- lcd_hiu_setb(HHI_VDIN_MEAS_CLK_CNTL, 0, 12, 7);
- lcd_hiu_setb(HHI_VDIN_MEAS_CLK_CNTL, 1, 20, 1);
+ lcd_clk_setb(HHI_VDIN_MEAS_CLK_CNTL, 0, 21, 3);
+ lcd_clk_setb(HHI_VDIN_MEAS_CLK_CNTL, 0, 12, 7);
+ lcd_clk_setb(HHI_VDIN_MEAS_CLK_CNTL, 1, 20, 1);
}
static void lcd_set_dsi_phy_clk(int sel)
{
- if (lcd_debug_print_flag == 2)
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
LCDPR("%s\n", __func__);
- lcd_hiu_setb(HHI_MIPIDSI_PHY_CLK_CNTL, sel, 12, 3);
- lcd_hiu_setb(HHI_MIPIDSI_PHY_CLK_CNTL, 1, 8, 1);
- lcd_hiu_setb(HHI_MIPIDSI_PHY_CLK_CNTL, 0, 0, 7);
+ lcd_ana_setb(HHI_MIPIDSI_PHY_CLK_CNTL, sel, 12, 3);
+ lcd_ana_setb(HHI_MIPIDSI_PHY_CLK_CNTL, 1, 8, 1);
+ lcd_ana_setb(HHI_MIPIDSI_PHY_CLK_CNTL, 0, 0, 7);
+}
+
+static void lcd_set_dsi_meas_clk_t7(int index)
+{
+ if (index) {
+ lcd_clk_setb(CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL, 7, 12, 7);
+ lcd_clk_setb(CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL, 0, 21, 3);
+ lcd_clk_setb(CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL, 1, 20, 1);
+ } else {
+ lcd_clk_setb(CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL, 7, 0, 7);
+ lcd_clk_setb(CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL, 0, 9, 3);
+ lcd_clk_setb(CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL, 1, 8, 1);
+ }
+}
+
+static void lcd_set_dsi_phy_clk_t7(int index)
+{
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
+ LCDPR("[%d]: %s\n", index, __func__);
+ if (index) {
+ lcd_clk_setb(CLKCTRL_MIPIDSI_PHY_CLK_CTRL, 0, 16, 7);
+ lcd_clk_setb(CLKCTRL_MIPIDSI_PHY_CLK_CTRL, 0, 25, 3);
+ lcd_clk_setb(CLKCTRL_MIPIDSI_PHY_CLK_CTRL, 1, 24, 1);
+ } else {
+ lcd_clk_setb(CLKCTRL_MIPIDSI_PHY_CLK_CTRL, 0, 0, 7);
+ lcd_clk_setb(CLKCTRL_MIPIDSI_PHY_CLK_CTRL, 0, 12, 3);
+ lcd_clk_setb(CLKCTRL_MIPIDSI_PHY_CLK_CTRL, 1, 8, 1);
+ }
+}
+
+static void lcd_set_tcon_clk_tl1(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_config_s *pconf = &pdrv->config;
+ unsigned int val;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
+
+ switch (pconf->basic.lcd_type) {
+ case LCD_MLVDS:
+ val = pconf->control.mlvds_cfg.clk_phase & 0xfff;
+ lcd_ana_setb(HHI_TCON_PLL_CNTL1, (val & 0xf), 24, 4);
+ lcd_ana_setb(HHI_TCON_PLL_CNTL4, ((val >> 4) & 0xf), 28, 4);
+ lcd_ana_setb(HHI_TCON_PLL_CNTL4, ((val >> 8) & 0xf), 24, 4);
+
+ /* tcon_clk */
+ if (pconf->timing.lcd_clk >= 100000000) /* 25M */
+ lcd_clk_write(HHI_TCON_CLK_CNTL,
+ (1 << 7) | (1 << 6) | (0xf << 0));
+ else /* 12.5M */
+ lcd_clk_write(HHI_TCON_CLK_CNTL,
+ (1 << 7) | (1 << 6) | (0x1f << 0));
+ break;
+ case LCD_P2P:
+ /* tcon_clk 50M */
+ lcd_clk_write(HHI_TCON_CLK_CNTL,
+ (1 << 7) | (1 << 6) | (7 << 0));
+ break;
+ default:
+ break;
+ }
}
/* ****************************************************
@@ -491,6 +1494,12 @@
else
clk_ret = clk * 5 / 2;
break;
+ case CLK_DIV_SEL_4p67:
+ if (dir == CLK_DIV_I2O)
+ clk_ret = clk * 3 / 14;
+ else
+ clk_ret = clk * 14 / 3;
+ break;
default:
clk_ret = clk;
LCDERR("clk_div_sel: Invalid parameter\n");
@@ -500,10 +1509,34 @@
return clk_ret;
}
-static int check_pll_txl(struct lcd_clk_config_s *cConf,
- unsigned int pll_fout)
+static unsigned int clk_vid_pll_div_get(unsigned int clk_div)
{
- struct lcd_clk_data_s *data = cConf->data;
+ unsigned int div_sel;
+
+ /* div * 100 */
+ switch (clk_div) {
+ case 375:
+ div_sel = CLK_DIV_SEL_3p75;
+ break;
+ case 750:
+ div_sel = CLK_DIV_SEL_7p5;
+ break;
+ case 1500:
+ div_sel = CLK_DIV_SEL_15;
+ break;
+ case 500:
+ div_sel = CLK_DIV_SEL_5;
+ break;
+ default:
+ div_sel = CLK_DIV_SEL_MAX;
+ break;
+ }
+ return div_sel;
+}
+
+static int check_pll_3od(struct lcd_clk_config_s *cconf, unsigned int pll_fout)
+{
+ struct lcd_clk_data_s *data = cconf->data;
unsigned int m, n;
unsigned int od1_sel, od2_sel, od3_sel, od1, od2, od3;
unsigned int pll_fod2_in, pll_fod3_in, pll_fvco;
@@ -528,27 +1561,36 @@
(pll_fvco > data->pll_vco_fmax)) {
continue;
}
- cConf->pll_od1_sel = od1_sel - 1;
- cConf->pll_od2_sel = od2_sel - 1;
- cConf->pll_od3_sel = od3_sel - 1;
- cConf->pll_fout = pll_fout;
- if (lcd_debug_print_flag == 2) {
+ cconf->pll_od1_sel = od1_sel - 1;
+ cconf->pll_od2_sel = od2_sel - 1;
+ cconf->pll_od3_sel = od3_sel - 1;
+ cconf->pll_fout = pll_fout;
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
LCDPR("od1=%d, od2=%d, od3=%d\n",
(od1_sel - 1), (od2_sel - 1),
(od3_sel - 1));
LCDPR("pll_fvco=%d\n", pll_fvco);
}
- cConf->pll_fvco = pll_fvco;
+ cconf->pll_fvco = pll_fvco;
n = 1;
- od_fb = cConf->pll_od_fb;
+ od_fb = cconf->pll_od_fb;
pll_fvco = pll_fvco / od_fb_table[od_fb];
- m = pll_fvco / cConf->fin;
- pll_frac = (pll_fvco % cConf->fin) *
- data->pll_frac_range / cConf->fin;
- cConf->pll_m = m;
- cConf->pll_n = n;
- cConf->pll_frac = pll_frac;
- if (lcd_debug_print_flag == 2) {
+ m = pll_fvco / cconf->fin;
+ pll_frac = (pll_fvco % cconf->fin) *
+ data->pll_frac_range / cconf->fin;
+ if (cconf->pll_mode & LCD_PLL_MODE_FRAC_SHIFT) {
+ if ((pll_frac == (data->pll_frac_range >> 1)) ||
+ (pll_frac == (data->pll_frac_range >> 2))) {
+ pll_frac |= 0x66;
+ cconf->pll_frac_half_shift = 1;
+ } else {
+ cconf->pll_frac_half_shift = 0;
+ }
+ }
+ cconf->pll_m = m;
+ cconf->pll_n = n;
+ cconf->pll_frac = pll_frac;
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
LCDPR("m=%d, n=%d, frac=0x%x\n",
m, n, pll_frac);
}
@@ -560,97 +1602,9 @@
return done;
}
-static void lcd_pll_frac_generate_txl(struct lcd_config_s *pconf)
+static int check_pll_1od(struct lcd_clk_config_s *cconf, unsigned int pll_fout)
{
- unsigned int pll_fout;
- unsigned int clk_div_in, clk_div_out, clk_div_sel;
- unsigned int od1, od2, od3, pll_fvco;
- unsigned int m, n, od_fb, frac, offset, temp;
- struct lcd_clk_config_s *cConf = get_lcd_clk_config();
-
- cConf->fout = pconf->lcd_timing.lcd_clk / 1000; /* kHz */
- clk_div_sel = cConf->div_sel;
- od1 = od_table[cConf->pll_od1_sel];
- od2 = od_table[cConf->pll_od2_sel];
- od3 = od_table[cConf->pll_od3_sel];
- m = cConf->pll_m;
- n = cConf->pll_n;
-
- if (lcd_debug_print_flag == 2) {
- LCDPR("m=%d, n=%d, od1=%d, od2=%d, od3=%d\n",
- m, n, cConf->pll_od1_sel, cConf->pll_od2_sel,
- cConf->pll_od3_sel);
- LCDPR("clk_div_sel=%s(index %d), xd=%d\n",
- lcd_clk_div_sel_table[clk_div_sel],
- clk_div_sel, cConf->xd);
- }
- if (cConf->fout > cConf->data->xd_out_fmax) {
- LCDERR("%s: wrong lcd_clk value %dkHz\n",
- __func__, cConf->fout);
- return;
- }
- if (lcd_debug_print_flag == 2)
- LCDPR("%s pclk=%d\n", __func__, cConf->fout);
-
- clk_div_out = cConf->fout * cConf->xd;
- if (clk_div_out > cConf->data->div_out_fmax) {
- LCDERR("%s: wrong clk_div_out value %dkHz\n",
- __func__, clk_div_out);
- return;
- }
-
- clk_div_in =
- clk_vid_pll_div_calc(clk_div_out, clk_div_sel, CLK_DIV_O2I);
- if (clk_div_in > cConf->data->div_in_fmax) {
- LCDERR("%s: wrong clk_div_in value %dkHz\n",
- __func__, clk_div_in);
- return;
- }
-
- pll_fout = clk_div_in;
- if ((pll_fout > cConf->data->pll_out_fmax) ||
- (pll_fout < cConf->data->pll_out_fmin)) {
- LCDERR("%s: wrong pll_fout value %dkHz\n", __func__, pll_fout);
- return;
- }
- if (lcd_debug_print_flag == 2)
- LCDPR("%s pll_fout=%d\n", __func__, pll_fout);
-
- pll_fvco = pll_fout * od1 * od2 * od3;
- if ((pll_fvco < cConf->data->pll_vco_fmin) ||
- (pll_fvco > cConf->data->pll_vco_fmax)) {
- LCDERR("%s: wrong pll_fvco value %dkHz\n", __func__, pll_fvco);
- return;
- }
- if (lcd_debug_print_flag == 2)
- LCDPR("%s pll_fvco=%d\n", __func__, pll_fvco);
-
- cConf->pll_fvco = pll_fvco;
- od_fb = cConf->pll_od_fb;
- pll_fvco = pll_fvco / od_fb_table[od_fb];
- temp = cConf->fin * m / n;
- if (pll_fvco >= temp) {
- temp = pll_fvco - temp;
- offset = 0;
- } else {
- temp = temp - pll_fvco;
- offset = 1;
- }
- if (temp >= (2 * cConf->fin)) {
- LCDERR("%s: pll changing %dkHz is too much\n",
- __func__, temp);
- return;
- }
- frac = temp * cConf->data->pll_frac_range * n / cConf->fin;
- cConf->pll_frac = frac | (offset << 11);
- if (lcd_debug_print_flag)
- LCDPR("lcd_pll_frac_generate: frac=0x%x\n", frac);
-}
-
-static int check_pll_axg(struct lcd_clk_config_s *cConf,
- unsigned int pll_fout)
-{
- struct lcd_clk_data_s *data = cConf->data;
+ struct lcd_clk_data_s *data = cconf->data;
unsigned int m, n, od_sel, od;
unsigned int pll_fvco;
unsigned int od_fb = 0, pll_frac;
@@ -667,21 +1621,21 @@
(pll_fvco > data->pll_vco_fmax)) {
continue;
}
- cConf->pll_od1_sel = od_sel - 1;
- cConf->pll_fout = pll_fout;
- if (lcd_debug_print_flag == 2)
+ cconf->pll_od1_sel = od_sel - 1;
+ cconf->pll_fout = pll_fout;
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
LCDPR("od_sel=%d, pll_fvco=%d\n", (od_sel - 1), pll_fvco);
- cConf->pll_fvco = pll_fvco;
+ cconf->pll_fvco = pll_fvco;
n = 1;
- od_fb = cConf->pll_od_fb;
+ od_fb = cconf->pll_od_fb;
pll_fvco = pll_fvco / od_fb_table[od_fb];
- m = pll_fvco / cConf->fin;
- pll_frac = (pll_fvco % cConf->fin) * data->pll_frac_range / cConf->fin;
- cConf->pll_m = m;
- cConf->pll_n = n;
- cConf->pll_frac = pll_frac;
- if (lcd_debug_print_flag == 2)
+ m = pll_fvco / cconf->fin;
+ pll_frac = (pll_fvco % cconf->fin) * data->pll_frac_range / cconf->fin;
+ cconf->pll_m = m;
+ cconf->pll_n = n;
+ cconf->pll_frac = pll_frac;
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
LCDPR("pll_m=%d, pll_n=%d, pll_frac=0x%x\n", m, n, pll_frac);
done = 1;
break;
@@ -689,122 +1643,544 @@
return done;
}
-static void lcd_clk_generate_axg(struct lcd_config_s *pconf)
+static int check_vco(struct lcd_clk_config_s *cconf, unsigned int pll_fvco)
{
- unsigned int pll_fout;
- unsigned int xd;
- unsigned int dsi_bit_rate_max = 0, dsi_bit_rate_min = 0;
- unsigned int tmp;
- struct lcd_clk_config_s *cConf = get_lcd_clk_config();
- int done;
+ struct lcd_clk_data_s *data = cconf->data;
+ unsigned int m, n;
+ unsigned int od_fb = 0, pll_frac;
+ int done = 0;
- done = 0;
- cConf->fout = pconf->lcd_timing.lcd_clk / 1000; /* kHz */
- cConf->err_fmin = MAX_ERROR;
-
- if (cConf->fout > cConf->data->xd_out_fmax) {
- LCDERR("%s: wrong lcd_clk value %dkHz\n",
- __func__, cConf->fout);
- goto generate_clk_done_axg;
+ if (pll_fvco < data->pll_vco_fmin ||
+ pll_fvco > data->pll_vco_fmax) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
+ LCDPR("pll_fvco %d is out of range\n", pll_fvco);
+ return done;
}
- switch (pconf->lcd_basic.lcd_type) {
- case LCD_MIPI:
- cConf->xd_max = CRT_VID_DIV_MAX;
- tmp = pconf->lcd_control.mipi_config->bit_rate_max;
- dsi_bit_rate_max = tmp * 1000; /* change to kHz */
- dsi_bit_rate_min = dsi_bit_rate_max - cConf->fout;
+ cconf->pll_fvco = pll_fvco;
+ n = 1;
+ od_fb = cconf->pll_od_fb;
+ pll_fvco = pll_fvco / od_fb_table[od_fb];
+ m = pll_fvco / cconf->fin;
+ pll_frac = (pll_fvco % cconf->fin) * data->pll_frac_range / cconf->fin;
+ cconf->pll_m = m;
+ cconf->pll_n = n;
+ cconf->pll_frac = pll_frac;
+ if (cconf->pll_mode & LCD_PLL_MODE_FRAC_SHIFT) {
+ if (pll_frac == (data->pll_frac_range >> 1) ||
+ pll_frac == (data->pll_frac_range >> 2)) {
+ pll_frac |= 0x66;
+ cconf->pll_frac_half_shift = 1;
+ } else {
+ cconf->pll_frac_half_shift = 0;
+ }
+ }
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
+ LCDPR("m=%d, n=%d, frac=0x%x, pll_fvco=%d\n",
+ m, n, pll_frac, pll_fvco);
+ }
+ done = 1;
- for (xd = 1; xd <= cConf->xd_max; xd++) {
- pll_fout = cConf->fout * xd;
+ return done;
+}
+
+#define PLL_FVCO_ERR_MAX 2 /* kHz */
+static int check_od(struct lcd_clk_config_s *cconf, unsigned int pll_fout)
+{
+ struct lcd_clk_data_s *data = cconf->data;
+ unsigned int od1_sel, od2_sel, od3_sel, od1, od2, od3;
+ unsigned int pll_fod2_in, pll_fod3_in, pll_fvco;
+ int done = 0;
+
+ if (pll_fout > data->pll_out_fmax ||
+ pll_fout < data->pll_out_fmin) {
+ return done;
+ }
+
+ for (od3_sel = data->pll_od_sel_max; od3_sel > 0; od3_sel--) {
+ od3 = od_table[od3_sel - 1];
+ pll_fod3_in = pll_fout * od3;
+ for (od2_sel = od3_sel; od2_sel > 0; od2_sel--) {
+ od2 = od_table[od2_sel - 1];
+ pll_fod2_in = pll_fod3_in * od2;
+ for (od1_sel = od2_sel; od1_sel > 0; od1_sel--) {
+ od1 = od_table[od1_sel - 1];
+ pll_fvco = pll_fod2_in * od1;
+ if (pll_fvco < data->pll_vco_fmin ||
+ pll_fvco > data->pll_vco_fmax) {
+ continue;
+ }
+ if (error_abs(pll_fvco, cconf->pll_fvco) <
+ PLL_FVCO_ERR_MAX) {
+ cconf->pll_od1_sel = od1_sel - 1;
+ cconf->pll_od2_sel = od2_sel - 1;
+ cconf->pll_od3_sel = od3_sel - 1;
+ cconf->pll_fout = pll_fout;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
+ LCDPR
+ ("od1=%d, od2=%d, od3=%d\n",
+ (od1_sel - 1), (od2_sel - 1),
+ (od3_sel - 1));
+ }
+ done = 1;
+ break;
+ }
+ }
+ }
+ }
+ return done;
+}
+
+static int edp_div_check(struct lcd_clk_config_s *cconf, unsigned int bit_rate)
+{
+ unsigned int edp_div0, edp_div1, tmp_div, tmp;
+
+ for (edp_div0 = 0; edp_div0 < 15; edp_div0++) {
+ for (edp_div1 = 0; edp_div1 < 10; edp_div1++) {
+ tmp_div = edp_div0_table[edp_div0] *
+ edp_div1_table[edp_div1];
+ tmp = bit_rate / tmp_div;
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
+ LCDPR("fout=%d, _clk=%d, tmp_div=%d, edp_div0=%d, edp_div1=%d\n",
+ cconf->fout, tmp, tmp_div,
+ edp_div0, edp_div1);
+ }
+ tmp = error_abs(tmp, cconf->fout);
+ if (cconf->err_fmin > tmp) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
+ LCDPR("err=%d, edp_div0=%d, edp_div1=%d\n",
+ tmp, edp_div0, edp_div1);
+ }
+ cconf->err_fmin = tmp;
+ cconf->edp_div0 = edp_div0;
+ cconf->edp_div1 = edp_div1;
+ }
+ }
+ }
+
+ return 0;
+}
+
+static void lcd_clk_generate_tl1(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+ struct lcd_config_s *pconf = &pdrv->config;
+ unsigned int pll_fout, pll_fvco, bit_rate;
+ unsigned int clk_div_in, clk_div_out;
+ unsigned int clk_div_sel, xd, tcon_div_sel = 0, phy_div = 1;
+ unsigned int od1, od2, od3;
+ unsigned int dsi_bit_rate_max = 0, dsi_bit_rate_min = 0, tmp;
+ unsigned int tmp_div;
+ int done;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ done = 0;
+ cconf->fout = pconf->timing.lcd_clk / 1000; /* kHz */
+ cconf->err_fmin = MAX_ERROR;
+
+ if (cconf->fout > cconf->data->xd_out_fmax) {
+ LCDERR("%s: wrong lcd_clk value %dkHz\n",
+ __func__, cconf->fout);
+ goto generate_clk_done_tl1;
+ }
+
+ bit_rate = pconf->timing.bit_rate / 1000;
+
+ cconf->pll_mode = pconf->timing.clk_auto;
+
+ switch (pconf->basic.lcd_type) {
+ case LCD_TTL:
+ clk_div_sel = CLK_DIV_SEL_1;
+ cconf->xd_max = CRT_VID_DIV_MAX;
+ for (xd = 1; xd <= cconf->xd_max; xd++) {
+ clk_div_out = cconf->fout * xd;
+ if (clk_div_out > cconf->data->div_out_fmax)
+ continue;
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
+ LCDPR("fout=%d, xd=%d, clk_div_out=%d\n",
+ cconf->fout, xd, clk_div_out);
+ }
+ clk_div_in =
+ clk_vid_pll_div_calc(clk_div_out, clk_div_sel,
+ CLK_DIV_O2I);
+ if (clk_div_in > cconf->data->div_in_fmax)
+ continue;
+ cconf->xd = xd;
+ cconf->div_sel = clk_div_sel;
+ pll_fout = clk_div_in;
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
+ LCDPR("clk_div_sel=%s(index %d), pll_fout=%d\n",
+ lcd_clk_div_sel_table[clk_div_sel],
+ clk_div_sel, pll_fout);
+ }
+ done = check_pll_3od(cconf, pll_fout);
+ if (done)
+ goto generate_clk_done_tl1;
+ }
+ break;
+ case LCD_LVDS:
+ clk_div_sel = CLK_DIV_SEL_7;
+ xd = 1;
+ clk_div_out = cconf->fout * xd;
+ if (clk_div_out > cconf->data->div_out_fmax)
+ goto generate_clk_done_tl1;
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
+ LCDPR("fout=%d, xd=%d, clk_div_out=%d\n",
+ cconf->fout, xd, clk_div_out);
+ }
+ clk_div_in = clk_vid_pll_div_calc(clk_div_out,
+ clk_div_sel, CLK_DIV_O2I);
+ if (clk_div_in > cconf->data->div_in_fmax)
+ goto generate_clk_done_tl1;
+ cconf->xd = xd;
+ cconf->div_sel = clk_div_sel;
+ pll_fout = clk_div_in;
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
+ LCDPR("clk_div_sel=%s(index %d), pll_fout=%d\n",
+ lcd_clk_div_sel_table[clk_div_sel],
+ clk_div_sel, pll_fout);
+ }
+ done = check_pll_3od(cconf, pll_fout);
+ if (done == 0)
+ goto generate_clk_done_tl1;
+ done = 0;
+ if (pconf->control.lvds_cfg.dual_port)
+ phy_div = 2;
+ else
+ phy_div = 1;
+ od1 = od_table[cconf->pll_od1_sel];
+ od2 = od_table[cconf->pll_od2_sel];
+ od3 = od_table[cconf->pll_od3_sel];
+ for (tcon_div_sel = 0; tcon_div_sel < 5; tcon_div_sel++) {
+ if (tcon_div_table[tcon_div_sel] ==
+ phy_div * od1 * od2 * od3) {
+ cconf->pll_tcon_div_sel = tcon_div_sel;
+ done = 1;
+ break;
+ }
+ }
+ break;
+ case LCD_VBYONE:
+ cconf->div_sel_max = CLK_DIV_SEL_MAX;
+ cconf->xd_max = CRT_VID_DIV_MAX;
+ pll_fout = bit_rate;
+ clk_div_in = pll_fout;
+ if (clk_div_in > cconf->data->div_in_fmax)
+ goto generate_clk_done_tl1;
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
+ LCDPR("pll_fout=%d\n", pll_fout);
+ if ((clk_div_in / cconf->fout) > 15)
+ cconf->xd = 4;
+ else
+ cconf->xd = 1;
+ clk_div_out = cconf->fout * cconf->xd;
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
+ LCDPR("clk_div_in=%d, fout=%d, xd=%d, clk_div_out=%d\n",
+ clk_div_in, cconf->fout,
+ cconf->xd, clk_div_out);
+ }
+ if (clk_div_out > cconf->data->div_out_fmax)
+ goto generate_clk_done_tl1;
+ clk_div_sel =
+ clk_vid_pll_div_get(clk_div_in * 100 / clk_div_out);
+ if (clk_div_sel == CLK_DIV_SEL_MAX) {
+ clk_div_sel = CLK_DIV_SEL_1;
+ cconf->xd *= clk_div_in / clk_div_out;
+ } else {
+ cconf->div_sel = clk_div_sel;
+ }
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
+ LCDPR("clk_div_sel=%s(index %d), xd=%d\n",
+ lcd_clk_div_sel_table[clk_div_sel],
+ cconf->div_sel, cconf->xd);
+ }
+ done = check_pll_3od(cconf, pll_fout);
+ if (done == 0)
+ goto generate_clk_done_tl1;
+ done = 0;
+ od1 = od_table[cconf->pll_od1_sel];
+ od2 = od_table[cconf->pll_od2_sel];
+ od3 = od_table[cconf->pll_od3_sel];
+ for (tcon_div_sel = 0; tcon_div_sel < 5; tcon_div_sel++) {
+ if (tcon_div_table[tcon_div_sel] == od1 * od2 * od3) {
+ cconf->pll_tcon_div_sel = tcon_div_sel;
+ done = 1;
+ break;
+ }
+ }
+ break;
+ case LCD_MLVDS:
+ /* must go through div4 for clk phase */
+ for (tcon_div_sel = 3; tcon_div_sel < 5; tcon_div_sel++) {
+ pll_fvco = bit_rate * tcon_div_table[tcon_div_sel];
+ done = check_vco(cconf, pll_fvco);
+ if (done == 0)
+ continue;
+ cconf->xd_max = CRT_VID_DIV_MAX;
+ for (xd = 1; xd <= cconf->xd_max; xd++) {
+ clk_div_out = cconf->fout * xd;
+ if (clk_div_out > cconf->data->div_out_fmax)
+ continue;
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
+ LCDPR("fout=%d, xd=%d, clk_div_out=%d\n",
+ cconf->fout, xd, clk_div_out);
+ }
+ for (clk_div_sel = CLK_DIV_SEL_1;
+ clk_div_sel < CLK_DIV_SEL_MAX;
+ clk_div_sel++) {
+ clk_div_in =
+ clk_vid_pll_div_calc(clk_div_out,
+ clk_div_sel,
+ CLK_DIV_O2I);
+ if (clk_div_in > cconf->data->div_in_fmax)
+ continue;
+ cconf->xd = xd;
+ cconf->div_sel = clk_div_sel;
+ cconf->pll_tcon_div_sel = tcon_div_sel;
+ pll_fout = clk_div_in;
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
+ LCDPR("clk_div_sel=%s(%d)\n",
+ lcd_clk_div_sel_table[clk_div_sel],
+ clk_div_sel);
+ LCDPR("pll_fout=%d, tcon_div_sel=%d\n",
+ pll_fout, tcon_div_sel);
+ }
+ done = check_od(cconf, pll_fout);
+ if (done)
+ goto generate_clk_done_tl1;
+ }
+ }
+ }
+ break;
+ case LCD_P2P:
+ for (tcon_div_sel = 0; tcon_div_sel < 5; tcon_div_sel++) {
+ pll_fvco = bit_rate * tcon_div_table[tcon_div_sel];
+ done = check_vco(cconf, pll_fvco);
+ if (done == 0)
+ continue;
+ cconf->xd_max = CRT_VID_DIV_MAX;
+ for (xd = 1; xd <= cconf->xd_max; xd++) {
+ clk_div_out = cconf->fout * xd;
+ if (clk_div_out > cconf->data->div_out_fmax)
+ continue;
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
+ LCDPR("fout=%d, xd=%d, clk_div_out=%d\n",
+ cconf->fout, xd, clk_div_out);
+ }
+ for (clk_div_sel = CLK_DIV_SEL_1;
+ clk_div_sel < CLK_DIV_SEL_MAX;
+ clk_div_sel++) {
+ clk_div_in =
+ clk_vid_pll_div_calc(clk_div_out,
+ clk_div_sel,
+ CLK_DIV_O2I);
+ if (clk_div_in > cconf->data->div_in_fmax)
+ continue;
+ cconf->xd = xd;
+ cconf->div_sel = clk_div_sel;
+ cconf->pll_tcon_div_sel = tcon_div_sel;
+ pll_fout = clk_div_in;
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
+ LCDPR("clk_div_sel=%s(%d)\n",
+ lcd_clk_div_sel_table[clk_div_sel],
+ clk_div_sel);
+ LCDPR("pll_fout=%d, tcon_div_sel=%d\n",
+ pll_fout, tcon_div_sel);
+ }
+ done = check_od(cconf, pll_fout);
+ if (done)
+ goto generate_clk_done_tl1;
+ }
+ }
+ }
+ break;
+ case LCD_MIPI:
+ cconf->xd_max = CRT_VID_DIV_MAX;
+ tmp = pconf->control.mipi_cfg.bit_rate_max;
+ dsi_bit_rate_max = tmp * 1000; /* change to kHz */
+ dsi_bit_rate_min = dsi_bit_rate_max - cconf->fout;
+
+ clk_div_sel = CLK_DIV_SEL_1;
+ for (xd = 1; xd <= cconf->xd_max; xd++) {
+ pll_fout = cconf->fout * xd;
if ((pll_fout > dsi_bit_rate_max) ||
- (pll_fout < dsi_bit_rate_min)) {
+ (pll_fout < dsi_bit_rate_min)) {
continue;
}
- if (lcd_debug_print_flag == 2)
- LCDPR("fout=%d, xd=%d\n", cConf->fout, xd);
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
+ LCDPR("fout=%d, xd=%d\n", cconf->fout, xd);
- pconf->lcd_control.mipi_config->bit_rate = pll_fout * 1000;
- pconf->lcd_control.mipi_config->clk_factor = xd;
- cConf->xd = xd;
- done = check_pll_axg(cConf, pll_fout);
+ pconf->timing.bit_rate = pll_fout * 1000;
+ pconf->control.mipi_cfg.clk_factor = xd;
+ cconf->xd = xd;
+ cconf->div_sel = clk_div_sel;
+ cconf->pll_tcon_div_sel = 2;
+ done = check_pll_3od(cconf, pll_fout);
if (done)
- goto generate_clk_done_axg;
+ goto generate_clk_done_tl1;
+ }
+ break;
+ case LCD_EDP:
+ switch (pconf->control.edp_cfg.link_rate) {
+ case 0: /* 1.62G */
+ cconf->pll_n = 1;
+ cconf->pll_m = 135;
+ cconf->pll_frac = 0x0;
+ cconf->pll_fvco = 3240000;
+ cconf->pll_fout = 1620000;
+ bit_rate = 1620000;
+ break;
+ case 1: /* 2.7G */
+ default:
+ cconf->pll_n = 1;
+ cconf->pll_m = 225;
+ cconf->pll_frac = 0x0;
+ cconf->pll_fvco = 5400000;
+ cconf->pll_fout = 2700000;
+ bit_rate = 2700000;
+ break;
+ }
+ cconf->pll_od1_sel = 1;
+ cconf->pll_od2_sel = 0;
+ cconf->pll_od3_sel = 0;
+ cconf->pll_frac_half_shift = 0;
+ cconf->div_sel = CLK_DIV_SEL_1;
+ cconf->xd = 1;
+ cconf->err_fmin = 10000; /* 10M basic error */
+ for (tcon_div_sel = 0; tcon_div_sel < 5; tcon_div_sel++) {
+ if (tcon_div_table[tcon_div_sel] != cconf->pll_fvco / bit_rate)
+ continue;
+ cconf->pll_tcon_div_sel = tcon_div_sel;
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
+ LCDPR("bit_rate=%d, tcon_div=%d\n",
+ bit_rate, tcon_div_table[tcon_div_sel]);
+ }
+ if (edp_div_check(cconf, bit_rate) == 0)
+ done = 1;
+ }
+ if (done == 0)
+ break;
+ tmp_div = edp_div0_table[cconf->edp_div0] * edp_div1_table[cconf->edp_div1];
+ cconf->fout = bit_rate / tmp_div;
+ pconf->timing.lcd_clk = cconf->fout * 1000; /* Hz */
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
+ LCDPR("final fout=%d, tmp_div=%d, edp_div0=%d, edp_div1=%d\n",
+ cconf->fout, tmp_div, cconf->edp_div0, cconf->edp_div1);
}
break;
default:
break;
}
-generate_clk_done_axg:
+generate_clk_done_tl1:
if (done) {
- pconf->lcd_timing.pll_ctrl =
- (cConf->pll_od1_sel << PLL_CTRL_OD1) |
- (cConf->pll_n << PLL_CTRL_N) |
- (cConf->pll_m << PLL_CTRL_M);
- pconf->lcd_timing.div_ctrl =
- (CLK_DIV_SEL_1 << DIV_CTRL_DIV_SEL) |
- (cConf->xd << DIV_CTRL_XD);
- pconf->lcd_timing.clk_ctrl = (cConf->pll_frac << CLK_CTRL_FRAC);
+ pconf->timing.pll_ctrl =
+ (cconf->pll_od1_sel << PLL_CTRL_OD1) |
+ (cconf->pll_od2_sel << PLL_CTRL_OD2) |
+ (cconf->pll_od3_sel << PLL_CTRL_OD3) |
+ (cconf->pll_n << PLL_CTRL_N) |
+ (cconf->pll_m << PLL_CTRL_M);
+ pconf->timing.div_ctrl =
+ (cconf->div_sel << DIV_CTRL_DIV_SEL) |
+ (cconf->xd << DIV_CTRL_XD);
+ pconf->timing.clk_ctrl =
+ (cconf->pll_frac << CLK_CTRL_FRAC) |
+ (cconf->pll_frac_half_shift << CLK_CTRL_FRAC_SHIFT);
+ cconf->done = 1;
} else {
- pconf->lcd_timing.pll_ctrl =
+ pconf->timing.pll_ctrl =
(1 << PLL_CTRL_OD1) |
+ (1 << PLL_CTRL_OD2) |
+ (1 << PLL_CTRL_OD3) |
(1 << PLL_CTRL_N) |
(50 << PLL_CTRL_M);
- pconf->lcd_timing.div_ctrl =
+ pconf->timing.div_ctrl =
(CLK_DIV_SEL_1 << DIV_CTRL_DIV_SEL) |
(7 << DIV_CTRL_XD);
- pconf->lcd_timing.clk_ctrl = (0 << CLK_CTRL_FRAC);
- LCDERR("Out of clock range, reset to default setting!\n");
+ pconf->timing.clk_ctrl = (0 << CLK_CTRL_FRAC);
+ cconf->done = 0;
+ LCDERR("[%d]: %s: Out of clock range\n", pdrv->index, __func__);
}
}
-static void lcd_pll_frac_generate_axg(struct lcd_config_s *pconf)
+static void lcd_pll_frac_generate_dft(struct aml_lcd_drv_s *pdrv)
{
+ struct lcd_clk_config_s *cconf;
+ struct lcd_config_s *pconf = &pdrv->config;
unsigned int pll_fout;
- unsigned int od, pll_fvco;
- unsigned int m, n, od_fb, frac, offset, temp;
- struct lcd_clk_config_s *cConf = get_lcd_clk_config();
+ unsigned int clk_div_in, clk_div_out, clk_div_sel;
+ unsigned int od1, od2, od3, pll_fvco;
+ unsigned int m, n, od_fb, frac_range, frac, offset, temp;
- cConf->fout = pconf->lcd_timing.lcd_clk / 1000; /* kHz */
- od = od_table[cConf->pll_od1_sel];
- m = cConf->pll_m;
- n = cConf->pll_n;
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
- if (lcd_debug_print_flag == 2) {
- LCDPR("m=%d, n=%d, od=%d, xd=%d\n",
- m, n, cConf->pll_od1_sel, cConf->xd);
+ cconf->fout = pconf->timing.lcd_clk / 1000; /* kHz */
+ clk_div_sel = cconf->div_sel;
+ od1 = od_table[cconf->pll_od1_sel];
+ od2 = od_table[cconf->pll_od2_sel];
+ od3 = od_table[cconf->pll_od3_sel];
+ m = cconf->pll_m;
+ n = cconf->pll_n;
+ od_fb = cconf->pll_od_fb;
+ frac_range = cconf->data->pll_frac_range;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
+ LCDPR("m=%d, n=%d, od1=%d, od2=%d, od3=%d\n",
+ m, n, cconf->pll_od1_sel, cconf->pll_od2_sel,
+ cconf->pll_od3_sel);
+ LCDPR("clk_div_sel=%s(index %d), xd=%d\n",
+ lcd_clk_div_sel_table[clk_div_sel],
+ clk_div_sel, cconf->xd);
}
- if (cConf->fout > cConf->data->xd_out_fmax) {
+ if (cconf->fout > cconf->data->xd_out_fmax) {
LCDERR("%s: wrong lcd_clk value %dkHz\n",
- __func__, cConf->fout);
+ __func__, cconf->fout);
return;
}
- if (lcd_debug_print_flag == 2)
- LCDPR("%s pclk=%d\n", __func__, cConf->fout);
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
+ LCDPR("%s pclk=%d\n", __func__, cconf->fout);
- pll_fout = cConf->fout * cConf->xd;
- if ((pll_fout > cConf->data->pll_out_fmax) ||
- (pll_fout < cConf->data->pll_out_fmin)) {
+ clk_div_out = cconf->fout * cconf->xd;
+ if (clk_div_out > cconf->data->div_out_fmax) {
+ LCDERR("%s: wrong clk_div_out value %dkHz\n",
+ __func__, clk_div_out);
+ return;
+ }
+
+ clk_div_in = clk_vid_pll_div_calc(clk_div_out, clk_div_sel, CLK_DIV_O2I);
+ if (clk_div_in > cconf->data->div_in_fmax) {
+ LCDERR("%s: wrong clk_div_in value %dkHz\n",
+ __func__, clk_div_in);
+ return;
+ }
+
+ pll_fout = clk_div_in;
+ if ((pll_fout > cconf->data->pll_out_fmax) ||
+ (pll_fout < cconf->data->pll_out_fmin)) {
LCDERR("%s: wrong pll_fout value %dkHz\n", __func__, pll_fout);
return;
}
- if (lcd_debug_print_flag == 2)
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
LCDPR("%s pll_fout=%d\n", __func__, pll_fout);
- pll_fvco = pll_fout * od;
- if ((pll_fvco < cConf->data->pll_vco_fmin) ||
- (pll_fvco > cConf->data->pll_vco_fmax)) {
+ pll_fvco = pll_fout * od1 * od2 * od3;
+ if ((pll_fvco < cconf->data->pll_vco_fmin) ||
+ (pll_fvco > cconf->data->pll_vco_fmax)) {
LCDERR("%s: wrong pll_fvco value %dkHz\n", __func__, pll_fvco);
return;
}
- if (lcd_debug_print_flag == 2)
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
LCDPR("%s pll_fvco=%d\n", __func__, pll_fvco);
- cConf->pll_fvco = pll_fvco;
- od_fb = cConf->pll_od_fb;
+ cconf->pll_fvco = pll_fvco;
pll_fvco = pll_fvco / od_fb_table[od_fb];
- temp = cConf->fin * m / n;
+ temp = cconf->fin * m / n;
if (pll_fvco >= temp) {
temp = pll_fvco - temp;
offset = 0;
@@ -812,57 +2188,69 @@
temp = temp - pll_fvco;
offset = 1;
}
- if (temp >= (2 * cConf->fin)) {
+ if (temp >= (2 * cconf->fin)) {
LCDERR("%s: pll changing %dkHz is too much\n",
__func__, temp);
return;
}
- frac = temp * cConf->data->pll_frac_range * n / cConf->fin;
- cConf->pll_frac = frac | (offset << 11);
- if (lcd_debug_print_flag)
- LCDPR("lcd_pll_frac_generate: frac=0x%x\n", frac);
+ frac = temp * frac_range * n / cconf->fin;
+ if (cconf->pll_mode & LCD_PLL_MODE_FRAC_SHIFT) {
+ if (frac == (frac_range >> 1) ||
+ frac == (frac_range >> 2)) {
+ frac |= 0x66;
+ cconf->pll_frac_half_shift = 1;
+ } else {
+ cconf->pll_frac_half_shift = 0;
+ }
+ }
+ cconf->pll_frac = frac | (offset << cconf->data->pll_frac_sign_bit);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: lcd_pll_frac_generate: frac=0x%x\n", pdrv->index, frac);
}
-static void lcd_clk_generate_hpll_g12a(struct lcd_config_s *pconf)
+static void lcd_clk_generate_g12a(struct aml_lcd_drv_s *pdrv)
{
+ struct lcd_clk_config_s *cconf;
+ struct lcd_config_s *pconf = &pdrv->config;
unsigned int pll_fout;
- unsigned int clk_div_sel, xd;
+ unsigned int xd;
unsigned int dsi_bit_rate_max = 0, dsi_bit_rate_min = 0;
unsigned int tmp;
- struct lcd_clk_config_s *cConf = get_lcd_clk_config();
- int done;
+ int done = 0;
- done = 0;
- cConf->fout = pconf->lcd_timing.lcd_clk / 1000; /* kHz */
- cConf->err_fmin = MAX_ERROR;
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
- if (cConf->fout > cConf->data->xd_out_fmax) {
+ cconf->fout = pconf->timing.lcd_clk / 1000; /* kHz */
+ cconf->err_fmin = MAX_ERROR;
+
+ if (cconf->fout > cconf->data->xd_out_fmax) {
LCDERR("%s: wrong lcd_clk value %dkHz\n",
- __func__, cConf->fout);
+ __func__, cconf->fout);
+ goto generate_clk_done_g12a;
}
- switch (pconf->lcd_basic.lcd_type) {
+ switch (pconf->basic.lcd_type) {
case LCD_MIPI:
- cConf->xd_max = CRT_VID_DIV_MAX;
- tmp = pconf->lcd_control.mipi_config->bit_rate_max;
+ cconf->xd_max = CRT_VID_DIV_MAX;
+ tmp = pconf->control.mipi_cfg.bit_rate_max;
dsi_bit_rate_max = tmp * 1000; /* change to kHz */
- dsi_bit_rate_min = dsi_bit_rate_max - cConf->fout;
+ dsi_bit_rate_min = dsi_bit_rate_max - cconf->fout;
- clk_div_sel = CLK_DIV_SEL_1;
- for (xd = 1; xd <= cConf->xd_max; xd++) {
- pll_fout = cConf->fout * xd;
- if ((pll_fout > dsi_bit_rate_max) ||
- (pll_fout < dsi_bit_rate_min)) {
+ for (xd = 1; xd <= cconf->xd_max; xd++) {
+ pll_fout = cconf->fout * xd;
+ if (pll_fout > dsi_bit_rate_max ||
+ pll_fout < dsi_bit_rate_min) {
continue;
}
- if (lcd_debug_print_flag == 2)
- LCDPR("fout=%d, xd=%d\n", cConf->fout, xd);
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
+ LCDPR("fout=%d, xd=%d\n", cconf->fout, xd);
- pconf->lcd_control.mipi_config->bit_rate = pll_fout * 1000;
- pconf->lcd_control.mipi_config->clk_factor = xd;
- cConf->xd = xd;
- cConf->div_sel = clk_div_sel;
- done = check_pll_txl(cConf, pll_fout);
+ pconf->timing.bit_rate = pll_fout * 1000;
+ pconf->control.mipi_cfg.clk_factor = xd;
+ cconf->xd = xd;
+ done = check_pll_1od(cconf, pll_fout);
if (done)
goto generate_clk_done_g12a;
}
@@ -873,28 +2261,176 @@
generate_clk_done_g12a:
if (done) {
- pconf->lcd_timing.pll_ctrl =
- (cConf->pll_od1_sel << PLL_CTRL_OD1) |
- (cConf->pll_od2_sel << PLL_CTRL_OD2) |
- (cConf->pll_od3_sel << PLL_CTRL_OD3) |
- (cConf->pll_n << PLL_CTRL_N) |
- (cConf->pll_m << PLL_CTRL_M);
- pconf->lcd_timing.div_ctrl =
- (cConf->div_sel << DIV_CTRL_DIV_SEL) |
- (cConf->xd << DIV_CTRL_XD);
- pconf->lcd_timing.clk_ctrl = (cConf->pll_frac << CLK_CTRL_FRAC);
+ pconf->timing.pll_ctrl =
+ (cconf->pll_od1_sel << PLL_CTRL_OD1) |
+ (cconf->pll_n << PLL_CTRL_N) |
+ (cconf->pll_m << PLL_CTRL_M);
+ pconf->timing.div_ctrl =
+ (CLK_DIV_SEL_1 << DIV_CTRL_DIV_SEL) |
+ (cconf->xd << DIV_CTRL_XD);
+ pconf->timing.clk_ctrl = (cconf->pll_frac << CLK_CTRL_FRAC);
+ cconf->done = 1;
} else {
- pconf->lcd_timing.pll_ctrl =
+ pconf->timing.pll_ctrl =
+ (1 << PLL_CTRL_OD1) |
+ (1 << PLL_CTRL_N) |
+ (50 << PLL_CTRL_M);
+ pconf->timing.div_ctrl =
+ (CLK_DIV_SEL_1 << DIV_CTRL_DIV_SEL) |
+ (7 << DIV_CTRL_XD);
+ pconf->timing.clk_ctrl = (0 << CLK_CTRL_FRAC);
+ cconf->done = 0;
+ LCDERR("Out of clock range\n");
+ }
+}
+
+static void lcd_pll_frac_generate_g12a(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+ struct lcd_config_s *pconf = &pdrv->config;
+ unsigned int pll_fout;
+ unsigned int od, pll_fvco;
+ unsigned int m, n, od_fb, frac, offset, temp;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ cconf->fout = pconf->timing.lcd_clk / 1000; /* kHz */
+ od = od_table[cconf->pll_od1_sel];
+ m = cconf->pll_m;
+ n = cconf->pll_n;
+ od_fb = cconf->pll_od_fb;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
+ LCDPR("m=%d, n=%d, od=%d, xd=%d\n",
+ m, n, cconf->pll_od1_sel, cconf->xd);
+ }
+ if (cconf->fout > cconf->data->xd_out_fmax) {
+ LCDERR("%s: wrong lcd_clk value %dkHz\n",
+ __func__, cconf->fout);
+ return;
+ }
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
+ LCDPR("%s pclk=%d\n", __func__, cconf->fout);
+
+ pll_fout = cconf->fout * cconf->xd;
+ if ((pll_fout > cconf->data->pll_out_fmax) ||
+ (pll_fout < cconf->data->pll_out_fmin)) {
+ LCDERR("%s: wrong pll_fout value %dkHz\n", __func__, pll_fout);
+ return;
+ }
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
+ LCDPR("%s pll_fout=%d\n", __func__, pll_fout);
+
+ pll_fvco = pll_fout * od;
+ if ((pll_fvco < cconf->data->pll_vco_fmin) ||
+ (pll_fvco > cconf->data->pll_vco_fmax)) {
+ LCDERR("%s: wrong pll_fvco value %dkHz\n", __func__, pll_fvco);
+ return;
+ }
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
+ LCDPR("%s pll_fvco=%d\n", __func__, pll_fvco);
+
+ cconf->pll_fvco = pll_fvco;
+ pll_fvco = pll_fvco / od_fb_table[od_fb];
+ temp = cconf->fin * m / n;
+ if (pll_fvco >= temp) {
+ temp = pll_fvco - temp;
+ offset = 0;
+ } else {
+ temp = temp - pll_fvco;
+ offset = 1;
+ }
+ if (temp >= (2 * cconf->fin)) {
+ LCDERR("%s: pll changing %dkHz is too much\n",
+ __func__, temp);
+ return;
+ }
+ frac = temp * cconf->data->pll_frac_range * n / cconf->fin;
+ cconf->pll_frac = frac | (offset << 11);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("lcd_pll_frac_generate: frac=0x%x\n", frac);
+}
+
+static void lcd_clk_generate_hpll_g12a(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+ struct lcd_config_s *pconf = &pdrv->config;
+ unsigned int pll_fout;
+ unsigned int clk_div_sel, xd;
+ unsigned int dsi_bit_rate_max = 0, dsi_bit_rate_min = 0;
+ unsigned int tmp;
+ int done = 0;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ cconf->fout = pconf->timing.lcd_clk / 1000; /* kHz */
+ cconf->err_fmin = MAX_ERROR;
+
+ if (cconf->fout > cconf->data->xd_out_fmax) {
+ LCDERR("%s: wrong lcd_clk value %dkHz\n",
+ __func__, cconf->fout);
+ }
+
+ switch (pconf->basic.lcd_type) {
+ case LCD_MIPI:
+ cconf->xd_max = CRT_VID_DIV_MAX;
+ tmp = pconf->control.mipi_cfg.bit_rate_max;
+ dsi_bit_rate_max = tmp * 1000; /* change to kHz */
+ dsi_bit_rate_min = dsi_bit_rate_max - cconf->fout;
+
+ clk_div_sel = CLK_DIV_SEL_1;
+ for (xd = 1; xd <= cconf->xd_max; xd++) {
+ pll_fout = cconf->fout * xd;
+ if ((pll_fout > dsi_bit_rate_max) ||
+ (pll_fout < dsi_bit_rate_min)) {
+ continue;
+ }
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK)
+ LCDPR("fout=%d, xd=%d\n", cconf->fout, xd);
+
+ pconf->timing.bit_rate = pll_fout * 1000;
+ pconf->control.mipi_cfg.clk_factor = xd;
+ cconf->xd = xd;
+ cconf->div_sel = clk_div_sel;
+ done = check_pll_3od(cconf, pll_fout);
+ if (done)
+ goto generate_clk_done_hpll_g12a;
+ }
+ break;
+ default:
+ break;
+ }
+
+generate_clk_done_hpll_g12a:
+ if (done) {
+ pconf->timing.pll_ctrl =
+ (cconf->pll_od1_sel << PLL_CTRL_OD1) |
+ (cconf->pll_od2_sel << PLL_CTRL_OD2) |
+ (cconf->pll_od3_sel << PLL_CTRL_OD3) |
+ (cconf->pll_n << PLL_CTRL_N) |
+ (cconf->pll_m << PLL_CTRL_M);
+ pconf->timing.div_ctrl =
+ (cconf->div_sel << DIV_CTRL_DIV_SEL) |
+ (cconf->xd << DIV_CTRL_XD);
+ pconf->timing.clk_ctrl = (cconf->pll_frac << CLK_CTRL_FRAC);
+ cconf->done = 1;
+ } else {
+ pconf->timing.pll_ctrl =
(1 << PLL_CTRL_OD1) |
(1 << PLL_CTRL_OD2) |
(1 << PLL_CTRL_OD3) |
(1 << PLL_CTRL_N) |
(50 << PLL_CTRL_M);
- pconf->lcd_timing.div_ctrl =
+ pconf->timing.div_ctrl =
(CLK_DIV_SEL_1 << DIV_CTRL_DIV_SEL) |
(7 << DIV_CTRL_XD);
- pconf->lcd_timing.clk_ctrl = (0 << CLK_CTRL_FRAC);
- LCDERR("Out of clock range, reset to default setting\n");
+ pconf->timing.clk_ctrl = (0 << CLK_CTRL_FRAC);
+ cconf->done = 0;
+ LCDERR("Out of clock range\n");
}
}
@@ -902,40 +2438,226 @@
* lcd clk match function
* ****************************************************
*/
-static void lcd_clk_set_g12a_path0(struct lcd_config_s *pconf)
+static void lcd_clk_set_g12a_path0(struct aml_lcd_drv_s *pdrv)
{
- lcd_set_hpll_g12a(&clk_conf);
- lcd_set_vid_pll_div(&clk_conf);
+ struct lcd_clk_config_s *cconf;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ lcd_set_hpll_g12a(pdrv);
+ lcd_set_vid_pll_div(cconf);
lcd_set_dsi_meas_clk();
lcd_set_dsi_phy_clk(0);
}
-static void lcd_clk_set_g12a_path1(struct lcd_config_s *pconf)
+static void lcd_clk_set_g12a_path1(struct aml_lcd_drv_s *pdrv)
{
- lcd_set_gp0_pll_g12a(&clk_conf);
+ struct lcd_clk_config_s *cconf;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ lcd_set_gp0_pll_g12a(pdrv);
lcd_set_dsi_meas_clk();
lcd_set_dsi_phy_clk(1);
}
-static void lcd_clk_set_g12b_path0(struct lcd_config_s *pconf)
+static void lcd_clk_set_g12b_path0(struct aml_lcd_drv_s *pdrv)
{
- lcd_set_hpll_g12b(&clk_conf);
- lcd_set_vid_pll_div(&clk_conf);
+ struct lcd_clk_config_s *cconf;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ lcd_set_hpll_g12b(pdrv);
+ lcd_set_vid_pll_div(cconf);
lcd_set_dsi_meas_clk();
lcd_set_dsi_phy_clk(0);
}
-static void lcd_clk_set_g12b_path1(struct lcd_config_s *pconf)
+static void lcd_clk_set_g12b_path1(struct aml_lcd_drv_s *pdrv)
{
- lcd_set_gp0_pll_g12b(&clk_conf);
+ struct lcd_clk_config_s *cconf;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ lcd_set_gp0_pll_g12b(pdrv);
lcd_set_dsi_meas_clk();
lcd_set_dsi_phy_clk(1);
}
-static void lcd_clk_config_init_print_axg(void)
+static void lcd_clk_set_tl1(struct aml_lcd_drv_s *pdrv)
{
- struct lcd_clk_data_s *data = clk_conf.data;
+ struct lcd_clk_config_s *cconf;
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ lcd_set_tcon_clk_tl1(pdrv);
+ lcd_set_pll_tl1(pdrv);
+ lcd_set_vid_pll_div(cconf);
+}
+
+static void lcd_clk_set_t7(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+
+#ifdef CONFIG_AML_LCD_PXP
+ return;
+#endif
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ lcd_set_pll_t7(pdrv);
+ lcd_set_phy_dig_div_t7(pdrv);
+ lcd_set_vid_pll_div_t7(pdrv);
+
+ if (pdrv->config.basic.lcd_type == LCD_MIPI) {
+ lcd_set_dsi_meas_clk_t7(pdrv->index);
+ lcd_set_dsi_phy_clk_t7(pdrv->index);
+ }
+}
+
+static void lcd_clk_disable_dft(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+ struct lcd_clk_ctrl_s *table;
+ int i = 0;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ lcd_clk_setb(HHI_VID_CLK_CNTL2, 0, ENCL_GATE_VCLK, 1);
+
+ /* close vclk2_div gate: 0x104b[4:0] */
+ lcd_clk_setb(HHI_VIID_CLK_CNTL, 0, 0, 5);
+ lcd_clk_setb(HHI_VIID_CLK_CNTL, 0, VCLK2_EN, 1);
+
+ if (!cconf->data->pll_ctrl_table)
+ return;
+ table = cconf->data->pll_ctrl_table;
+ while (i < LCD_CLK_CTRL_CNT_MAX) {
+ if (table[i].flag == LCD_CLK_CTRL_END)
+ break;
+ if (table[i].flag == LCD_CLK_CTRL_EN)
+ lcd_ana_setb(table[i].reg, 0, table[i].bit, table[i].len);
+ else if (table[i].flag == LCD_CLK_CTRL_RST)
+ lcd_ana_setb(table[i].reg, 1, table[i].bit, table[i].len);
+ i++;
+ }
+}
+
+static void lcd_clk_disable_t7(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+ struct lcd_clk_ctrl_s *table;
+ unsigned int reg_vid_clk_ctrl2, reg_vid2_clk_ctrl, offset;
+ int i = 0;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ switch (cconf->pll_id) {
+ case 1:
+ reg_vid_clk_ctrl2 = CLKCTRL_VID_CLK1_CTRL2;
+ reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK1_CTRL;
+ break;
+ case 2:
+ reg_vid_clk_ctrl2 = CLKCTRL_VID_CLK2_CTRL2;
+ reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK2_CTRL;
+ break;
+ case 0:
+ default:
+ reg_vid_clk_ctrl2 = CLKCTRL_VID_CLK0_CTRL2;
+ reg_vid2_clk_ctrl = CLKCTRL_VIID_CLK0_CTRL;
+ break;
+ }
+ offset = cconf->pll_offset;
+
+ lcd_clk_setb(reg_vid_clk_ctrl2, 0, ENCL_GATE_VCLK, 1);
+
+ /* close vclk2_div gate: [4:0] */
+ lcd_clk_setb(reg_vid2_clk_ctrl, 0, 0, 5);
+ lcd_clk_setb(reg_vid2_clk_ctrl, 0, VCLK2_EN, 1);
+
+ if (!cconf->data->pll_ctrl_table)
+ return;
+ table = cconf->data->pll_ctrl_table;
+ while (i < LCD_CLK_CTRL_CNT_MAX) {
+ if (table[i].flag == LCD_CLK_CTRL_END)
+ break;
+ if (table[i].flag == LCD_CLK_CTRL_EN)
+ lcd_ana_setb(table[i].reg + offset, 0, table[i].bit, table[i].len);
+ else if (table[i].flag == LCD_CLK_CTRL_RST)
+ lcd_ana_setb(table[i].reg + offset, 1, table[i].bit, table[i].len);
+ i++;
+ }
+}
+
+static void lcd_clk_config_init_print_dft(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+ struct lcd_clk_data_s *data;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ data = cconf->data;
+ LCDPR("[%d]: lcd clk config data init:\n"
+ "pll_m_max: %d\n"
+ "pll_m_min: %d\n"
+ "pll_n_max: %d\n"
+ "pll_n_min: %d\n"
+ "pll_od_fb: %d\n"
+ "pll_frac_range: %d\n"
+ "pll_od_sel_max: %d\n"
+ "pll_ref_fmax: %d\n"
+ "pll_ref_fmin: %d\n"
+ "pll_vco_fmax: %d\n"
+ "pll_vco_fmin: %d\n"
+ "pll_out_fmax: %d\n"
+ "pll_out_fmin: %d\n"
+ "div_in_fmax: %d\n"
+ "div_out_fmax: %d\n"
+ "xd_out_fmax: %d\n"
+ "ss_level_max: %d\n"
+ "ss_freq_max: %d\n"
+ "ss_mode_max: %d\n\n",
+ pdrv->index,
+ data->pll_m_max, data->pll_m_min,
+ data->pll_n_max, data->pll_n_min,
+ data->pll_od_fb, data->pll_frac_range,
+ data->pll_od_sel_max,
+ data->pll_ref_fmax, data->pll_ref_fmin,
+ data->pll_vco_fmax, data->pll_vco_fmin,
+ data->pll_out_fmax, data->pll_out_fmin,
+ data->div_in_fmax, data->div_out_fmax,
+ data->xd_out_fmax, data->ss_level_max,
+ data->ss_freq_max, data->ss_mode_max);
+}
+
+static void lcd_clk_config_init_print_g12a(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+ struct lcd_clk_data_s *data;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ data = cconf->data;
LCDPR("lcd clk config data init:\n"
"vclk_sel: %d\n"
"pll_m_max: %d\n"
@@ -951,8 +2673,7 @@
"pll_vco_fmin: %d\n"
"pll_out_fmax: %d\n"
"pll_out_fmin: %d\n"
- "xd_out_fmax: %d\n"
- "ss_level_max: %d\n\n",
+ "xd_out_fmax: %d\n\n",
data->vclk_sel,
data->pll_m_max, data->pll_m_min,
data->pll_n_max, data->pll_n_min,
@@ -961,74 +2682,64 @@
data->pll_ref_fmax, data->pll_ref_fmin,
data->pll_vco_fmax, data->pll_vco_fmin,
data->pll_out_fmax, data->pll_out_fmin,
- data->xd_out_fmax, data->ss_level_max);
+ data->xd_out_fmax);
}
-#if 0
-static void lcd_clk_config_init_print_dft(void)
+static void lcd_clk_config_print_dft(struct aml_lcd_drv_s *pdrv)
{
- struct lcd_clk_data_s *data = clk_conf.data;
+ struct lcd_clk_config_s *cconf;
- LCDPR("lcd clk config:\n"
- "pll_m_max: %d\n"
- "pll_m_min: %d\n"
- "pll_n_max: %d\n"
- "pll_n_min: %d\n"
- "pll_od_fb: %d\n"
- "pll_frac_range: %d\n"
- "pll_od_sel_max: %d\n"
- "pll_ref_fmax: %d\n"
- "pll_ref_fmin: %d\n"
- "pll_vco_fmax: %d\n"
- "pll_vco_fmin: %d\n"
- "pll_out_fmax: %d\n"
- "pll_out_fmin: %d\n"
- "div_in_fmax: %d\n"
- "div_out_fmax: %d\n"
- "xd_out_fmax: %d\n"
- "ss_level_max: %d\n\n",
- data->pll_m_max, data->pll_m_min,
- data->pll_n_max, data->pll_n_min,
- data->pll_od_fb, data->pll_frac_range,
- data->pll_od_sel_max,
- data->pll_ref_fmax, data->pll_ref_fmin,
- data->pll_vco_fmax, data->pll_vco_fmin,
- data->pll_out_fmax, data->pll_out_fmin,
- data->div_in_fmax, data->div_out_fmax,
- data->xd_out_fmax, data->ss_level_max);
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ LCDPR("[%d]: lcd clk config:\n"
+ "pll_id: %d\n"
+ "pll_offset: 0x%x\n"
+ "pll_mode: %d\n"
+ "pll_m: %d\n"
+ "pll_n: %d\n"
+ "pll_frac: 0x%03x\n"
+ "pll_frac_half_shift: %d\n"
+ "pll_fvco: %dkHz\n"
+ "pll_od1: %d\n"
+ "pll_od2: %d\n"
+ "pll_od3: %d\n"
+ "pll_tcon_div_sel: %d\n"
+ "pll_out: %dkHz\n"
+ "edp_div0: %d\n"
+ "edp_div1: %d\n"
+ "div_sel: %s(index %d)\n"
+ "xd: %d\n"
+ "fout: %dkHz\n"
+ "ss_level: %d\n"
+ "ss_freq: %d\n"
+ "ss_mode: %d\n\n",
+ pdrv->index,
+ cconf->pll_id, cconf->pll_offset,
+ cconf->pll_mode, cconf->pll_m, cconf->pll_n,
+ cconf->pll_frac, cconf->pll_frac_half_shift,
+ cconf->pll_fvco,
+ cconf->pll_od1_sel, cconf->pll_od2_sel,
+ cconf->pll_od3_sel, cconf->pll_tcon_div_sel,
+ cconf->pll_fout,
+ cconf->edp_div0, cconf->edp_div1,
+ lcd_clk_div_sel_table[cconf->div_sel],
+ cconf->div_sel, cconf->xd,
+ cconf->fout, cconf->ss_level,
+ cconf->ss_freq, cconf->ss_mode);
}
-static void lcd_clk_config_print_dft(void)
-{
- LCDPR("lcd clk config:\n"
- "pll_mode: %d\n"
- "pll_m: %d\n"
- "pll_n: %d\n"
- "pll_frac: 0x%03x\n"
- "pll_fvco: %dkHz\n"
- "pll_od1: %d\n"
- "pll_od2: %d\n"
- "pll_od3: %d\n"
- "pll_pi_div_sel: %d\n"
- "pll_out: %dkHz\n"
- "div_sel: %s(index %d)\n"
- "xd: %d\n"
- "fout: %dkHz\n"
- "ss_level: %d\n\n",
- clk_conf.pll_mode, clk_conf.pll_m, clk_conf.pll_n,
- clk_conf.pll_frac, clk_conf.pll_fvco,
- clk_conf.pll_od1_sel, clk_conf.pll_od2_sel,
- clk_conf.pll_od3_sel, clk_conf.pll_pi_div_sel,
- clk_conf.pll_fout,
- lcd_clk_div_sel_table[clk_conf.div_sel],
- clk_conf.div_sel, clk_conf.xd,
- clk_conf.fout, clk_conf.ss_level);
-}
-#endif
-static void lcd_clk_config_print_g12a(void)
+static void lcd_clk_config_print_g12a(struct aml_lcd_drv_s *pdrv)
{
- if (clk_conf.data->vclk_sel) {
+ struct lcd_clk_config_s *cconf;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ if (cconf->data->vclk_sel) {
LCDPR("lcd clk config:\n"
"vclk_sel %d\n"
"pll_m: %d\n"
@@ -1038,13 +2749,12 @@
"pll_od: %d\n"
"pll_out: %dkHz\n"
"xd: %d\n"
- "fout: %dkHz\n"
- "ss_level: %d\n\n",
- clk_conf.data->vclk_sel,
- clk_conf.pll_m, clk_conf.pll_n,
- clk_conf.pll_frac, clk_conf.pll_fvco,
- clk_conf.pll_od1_sel, clk_conf.pll_fout,
- clk_conf.xd, clk_conf.fout, clk_conf.ss_level);
+ "fout: %dkHz\n\n",
+ cconf->data->vclk_sel,
+ cconf->pll_m, cconf->pll_n,
+ cconf->pll_frac, cconf->pll_fvco,
+ cconf->pll_od1_sel, cconf->pll_fout,
+ cconf->xd, cconf->fout);
} else {
LCDPR("lcd clk config:\n"
"vclk_sel %d\n"
@@ -1058,16 +2768,15 @@
"pll_out: %dkHz\n"
"div_sel: %s(index %d)\n"
"xd: %d\n"
- "fout: %dkHz\n"
- "ss_level: %d\n\n",
- clk_conf.data->vclk_sel,
- clk_conf.pll_m, clk_conf.pll_n,
- clk_conf.pll_frac, clk_conf.pll_fvco,
- clk_conf.pll_od1_sel, clk_conf.pll_od2_sel,
- clk_conf.pll_od3_sel, clk_conf.pll_fout,
- lcd_clk_div_sel_table[clk_conf.div_sel],
- clk_conf.div_sel, clk_conf.xd,
- clk_conf.fout, clk_conf.ss_level);
+ "fout: %dkHz\n\n",
+ cconf->data->vclk_sel,
+ cconf->pll_m, cconf->pll_n,
+ cconf->pll_frac, cconf->pll_fvco,
+ cconf->pll_od1_sel, cconf->pll_od2_sel,
+ cconf->pll_od3_sel, cconf->pll_fout,
+ lcd_clk_div_sel_table[cconf->div_sel],
+ cconf->div_sel, cconf->xd,
+ cconf->fout);
}
}
@@ -1075,150 +2784,197 @@
* lcd clk function api
* ****************************************************
*/
-void lcd_clk_generate_parameter(struct lcd_config_s *pconf)
+void lcd_clk_generate_parameter(struct aml_lcd_drv_s *pdrv)
{
+ struct lcd_clk_config_s *cconf;
+ struct lcd_config_s *pconf = &pdrv->config;
unsigned int ss_level;
+ unsigned int ss_freq;
+ unsigned int ss_mode;
- if (clk_conf.data == NULL) {
- LCDERR("%s: clk config data is null\n", __func__);
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ if (cconf->data->clk_generate_parameter)
+ cconf->data->clk_generate_parameter(pdrv);
+
+ ss_level = pconf->timing.ss_level & 0xff;
+ cconf->ss_level = (ss_level >= cconf->data->ss_level_max) ? 0 : ss_level;
+ ss_freq = (pconf->timing.ss_level >> 8) & 0xf;
+ cconf->ss_freq = (ss_freq >= cconf->data->ss_freq_max) ? 0 : ss_freq;
+ ss_mode = (pconf->timing.ss_level >> 12) & 0xf;
+ cconf->ss_mode = (ss_mode >= cconf->data->ss_mode_max) ? 0 : ss_mode;
+}
+
+void lcd_get_ss(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_clk_config_s *cconf;
+ unsigned int temp;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ if (cconf->data->ss_level_max == 0) {
+ printf("lcd spread spectrum is invalid\n");
return;
}
- if (clk_conf.data->clk_generate_parameter)
- clk_conf.data->clk_generate_parameter(pconf);
-
- ss_level = pconf->lcd_timing.ss_level;
- clk_conf.ss_level = (ss_level >= clk_conf.data->ss_level_max) ?
- 0 : ss_level;
+ temp = (cconf->ss_level >= cconf->data->ss_level_max) ? 0 : cconf->ss_level;
+ if (cconf->data->ss_level_table)
+ printf("ss_level: %s\n", cconf->data->ss_level_table[temp]);
+ temp = (cconf->ss_freq >= cconf->data->ss_freq_max) ? 0 : cconf->ss_freq;
+ if (cconf->data->ss_freq_table)
+ printf("ss_freq: %s\n", cconf->data->ss_freq_table[temp]);
+ temp = (cconf->ss_mode >= cconf->data->ss_mode_max) ? 0 : cconf->ss_mode;
+ if (cconf->data->ss_mode_table)
+ printf("ss_mode: %s\n", cconf->data->ss_mode_table[temp]);
}
-static char lcd_ss_invalid_str[10] = {'i', 'n', 'v', 'a', 'l', 'i', 'd', '\0',};
-char *lcd_get_spread_spectrum(void)
+int lcd_set_ss(struct aml_lcd_drv_s *pdrv, unsigned int level,
+ unsigned int freq, unsigned int mode)
{
- char *ss_str = lcd_ss_invalid_str;
- unsigned int level;
+ struct lcd_clk_config_s *cconf;
- level = clk_conf.ss_level;
- if (clk_conf.data) {
- level = (level >= clk_conf.data->ss_level_max) ? 0 : level;
- if (clk_conf.data->pll_ss_table)
- ss_str = clk_conf.data->pll_ss_table[level];
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return -1;
+
+ if (level < 0xff) {
+ if (level >= cconf->data->ss_level_max) {
+ LCDERR("%s: ss_level %d is out of support (max %d)\n",
+ __func__, level, (cconf->data->ss_level_max - 1));
+ return -1;
+ }
+ }
+ if (freq < 0xff) {
+ if (freq >= cconf->data->ss_freq_max) {
+ LCDERR("%s: ss_freq %d is out of support (max %d)\n",
+ __func__, freq, (cconf->data->ss_freq_max - 1));
+ return -1;
+ }
+ }
+ if (mode < 0xff) {
+ if (mode >= cconf->data->ss_mode_max) {
+ LCDERR("%s: ss_mode %d is out of support (max %d)\n",
+ __func__, mode, (cconf->data->ss_mode_max - 1));
+ return -1;
+ }
}
- return ss_str;
-}
-
-void lcd_set_spread_spectrum(unsigned int ss_level)
-{
- if (clk_conf.data == NULL) {
- LCDERR("%s: clk config data is null\n", __func__);
- return;
+ if (cconf->data->set_ss_level) {
+ if (level < 0xff) {
+ cconf->ss_level = level;
+ cconf->data->set_ss_level(pdrv);
+ }
}
- clk_conf.ss_level = (ss_level >= clk_conf.data->ss_level_max) ?
- 0 : ss_level;
- if (clk_conf.data->set_spread_spectrum)
- clk_conf.data->set_spread_spectrum(clk_conf.ss_level);
+ if (cconf->data->set_ss_advance) {
+ if (freq == 0xff && mode == 0xff)
+ goto lcd_set_ss_end;
+ if (freq < 0xff)
+ cconf->ss_freq = freq;
+ if (mode < 0xff)
+ cconf->ss_mode = mode;
+ cconf->data->set_ss_advance(pdrv);
+ }
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
+lcd_set_ss_end:
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
+ return 0;
}
/* for frame rate change */
-void lcd_clk_update(struct lcd_config_s *pconf)
+void lcd_update_clk(struct aml_lcd_drv_s *pdrv)
{
+ struct lcd_clk_config_s *cconf;
struct lcd_clk_ctrl_s *table;
+ unsigned int offset;
int i = 0;
- if (clk_conf.data == NULL) {
- LCDERR("%s: clk config data is null\n", __func__);
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
return;
- }
- if (clk_conf.data->pll_frac_generate)
- clk_conf.data->pll_frac_generate(pconf);
- if (clk_conf.data->pll_ctrl_table == NULL)
+ if (cconf->data->pll_frac_generate)
+ cconf->data->pll_frac_generate(pdrv);
+
+ offset = cconf->pll_offset;
+
+ if (!cconf->data->pll_ctrl_table)
return;
- table = clk_conf.data->pll_ctrl_table;
+ table = cconf->data->pll_ctrl_table;
while (i < LCD_CLK_CTRL_CNT_MAX) {
if (table[i].flag == LCD_CLK_CTRL_END)
break;
if (table[i].flag == LCD_CLK_CTRL_FRAC) {
- lcd_hiu_setb(table[i].reg, clk_conf.pll_frac,
- table[i].bit, table[i].len);
+ lcd_ana_setb(table[i].reg + offset, cconf->pll_frac,
+ table[i].bit, table[i].len);
}
i++;
}
- LCDPR("%s\n", __func__);
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
}
/* for timing change */
-void lcd_clk_set(struct lcd_config_s *pconf)
+void lcd_set_clk(struct aml_lcd_drv_s *pdrv)
{
- if (clk_conf.data == NULL) {
- LCDERR("%s: clk config data is null\n", __func__);
- return;
- }
- if (clk_conf.data->clk_set)
- clk_conf.data->clk_set(pconf);
+ struct lcd_clk_config_s *cconf;
+ int cnt = 0;
- lcd_set_vclk_crt(pconf->lcd_basic.lcd_type, &clk_conf);
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+lcd_set_clk_retry:
+ if (cconf->data->clk_set)
+ cconf->data->clk_set(pdrv);
+ if (cconf->data->vclk_crt_set)
+ cconf->data->vclk_crt_set(pdrv);
+#ifdef CONFIG_AML_LCD_PXP
+ return;
+#endif
mdelay(10);
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
-}
-
-void lcd_clk_disable(void)
-{
- struct lcd_clk_ctrl_s *table;
- int i = 0;
-
- lcd_hiu_setb(HHI_VID_CLK_CNTL2, 0, ENCL_GATE_VCLK, 1);
-
- /* close vclk2_div gate: 0x104b[4:0] */
- lcd_hiu_setb(HHI_VIID_CLK_CNTL, 0, 0, 5);
- lcd_hiu_setb(HHI_VIID_CLK_CNTL, 0, VCLK2_EN, 1);
-
- if (clk_conf.data == NULL)
- return;
- if (clk_conf.data->pll_ctrl_table == NULL)
- return;
- table = clk_conf.data->pll_ctrl_table;
- while (i < LCD_CLK_CTRL_CNT_MAX) {
- if (table[i].flag == LCD_CLK_CTRL_END)
+ while (lcd_clk_msr_check(cconf->data->enc_clk_msr_id, (cconf->fout / 1000))) {
+ if (cnt++ >= 10) {
+ LCDERR("[%d]: %s timeout\n", pdrv->index, __func__);
break;
- if (table[i].flag == LCD_CLK_CTRL_EN) {
- lcd_hiu_setb(table[i].reg, 0,
- table[i].bit, table[i].len);
}
- i++;
+ goto lcd_set_clk_retry;
}
- LCDPR("%s\n", __func__);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
}
-static void lcd_clk_config_init_print(void)
+void lcd_disable_clk(struct aml_lcd_drv_s *pdrv)
{
- if (clk_conf.data == NULL) {
- LCDERR("%s: clk config data is null\n", __func__);
- return;
- }
+ struct lcd_clk_config_s *cconf;
- if (clk_conf.data->clk_config_init_print)
- clk_conf.data->clk_config_init_print();
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ if (cconf->data->clk_disable)
+ cconf->data->clk_disable(pdrv);
+
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
}
-void lcd_clk_config_print(void)
+void lcd_clk_config_print(struct aml_lcd_drv_s *pdrv)
{
- if (clk_conf.data == NULL) {
- LCDERR("%s: clk config data is null\n", __func__);
- return;
- }
+ struct lcd_clk_config_s *cconf;
- if (clk_conf.data->clk_config_print)
- clk_conf.data->clk_config_print();
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return;
+
+ if (cconf->data->clk_config_print)
+ cconf->data->clk_config_print(pdrv);
}
/* ****************************************************
@@ -1226,16 +2982,16 @@
* ****************************************************
*/
static struct lcd_clk_data_s lcd_clk_data_g12a_path0 = {
- .ss_level_max = SS_LEVEL_MAX_HPLL_G12A,
.pll_od_fb = PLL_OD_FB_HPLL_G12A,
- .pll_m_max = PLL_M_MAX_G12A,
- .pll_m_min = PLL_M_MIN_G12A,
- .pll_n_max = PLL_N_MAX_G12A,
- .pll_n_min = PLL_N_MIN_G12A,
+ .pll_m_max = PLL_M_MAX,
+ .pll_m_min = PLL_M_MIN,
+ .pll_n_max = PLL_N_MAX,
+ .pll_n_min = PLL_N_MIN,
.pll_frac_range = PLL_FRAC_RANGE_HPLL_G12A,
+ .pll_frac_sign_bit = PLL_FRAC_SIGN_BIT_HPLL_G12A,
.pll_od_sel_max = PLL_OD_SEL_MAX_HPLL_G12A,
- .pll_ref_fmax = PLL_FREF_MAX_G12A,
- .pll_ref_fmin = PLL_FREF_MIN_G12A,
+ .pll_ref_fmax = PLL_FREF_MAX,
+ .pll_ref_fmin = PLL_FREF_MIN,
.pll_vco_fmax = PLL_VCO_MAX_HPLL_G12A,
.pll_vco_fmin = PLL_VCO_MIN_HPLL_G12A,
.pll_out_fmax = CRT_VID_CLK_IN_MAX_G12A,
@@ -1246,28 +3002,39 @@
.clk_path_valid = 1,
.vclk_sel = 0,
+ .enc_clk_msr_id = 9,
.pll_ctrl_table = pll_ctrl_table_g12a_path0,
- .pll_ss_table = NULL,
+
+ .ss_level_max = 0,
+ .ss_freq_max = 0,
+ .ss_mode_max = 0,
+ .ss_level_table = NULL,
+ .ss_freq_table = NULL,
+ .ss_mode_table = NULL,
.clk_generate_parameter = lcd_clk_generate_hpll_g12a,
- .pll_frac_generate = lcd_pll_frac_generate_txl,
- .set_spread_spectrum = NULL,
+ .pll_frac_generate = lcd_pll_frac_generate_dft,
+ .set_ss_level = NULL,
+ .set_ss_advance = NULL,
.clk_set = lcd_clk_set_g12a_path0,
- .clk_config_init_print = lcd_clk_config_init_print_axg,
+ .vclk_crt_set = lcd_set_vclk_crt,
+ .clk_disable = lcd_clk_disable_dft,
+ .clk_config_init_print = lcd_clk_config_init_print_g12a,
.clk_config_print = lcd_clk_config_print_g12a,
+ .prbs_clk_config = NULL,
};
static struct lcd_clk_data_s lcd_clk_data_g12a_path1 = {
- .ss_level_max = SS_LEVEL_MAX_GP0_G12A,
.pll_od_fb = PLL_OD_FB_GP0_G12A,
- .pll_m_max = PLL_M_MAX_G12A,
- .pll_m_min = PLL_M_MIN_G12A,
- .pll_n_max = PLL_N_MAX_G12A,
- .pll_n_min = PLL_N_MIN_G12A,
+ .pll_m_max = PLL_M_MAX,
+ .pll_m_min = PLL_M_MIN,
+ .pll_n_max = PLL_N_MAX,
+ .pll_n_min = PLL_N_MIN,
.pll_frac_range = PLL_FRAC_RANGE_GP0_G12A,
+ .pll_frac_sign_bit = PLL_FRAC_SIGN_BIT_GP0_G12A,
.pll_od_sel_max = PLL_OD_SEL_MAX_GP0_G12A,
- .pll_ref_fmax = PLL_FREF_MAX_G12A,
- .pll_ref_fmin = PLL_FREF_MIN_G12A,
+ .pll_ref_fmax = PLL_FREF_MAX,
+ .pll_ref_fmin = PLL_FREF_MIN,
.pll_vco_fmax = PLL_VCO_MAX_GP0_G12A,
.pll_vco_fmin = PLL_VCO_MIN_GP0_G12A,
.pll_out_fmax = CRT_VID_CLK_IN_MAX_G12A,
@@ -1278,28 +3045,39 @@
.clk_path_valid = 1,
.vclk_sel = 1,
+ .enc_clk_msr_id = 9,
.pll_ctrl_table = pll_ctrl_table_g12a_path1,
- .pll_ss_table = NULL,
- .clk_generate_parameter = lcd_clk_generate_axg,
- .pll_frac_generate = lcd_pll_frac_generate_axg,
- .set_spread_spectrum = NULL,
+ .ss_level_max = 0,
+ .ss_freq_max = 0,
+ .ss_mode_max = 0,
+ .ss_level_table = NULL,
+ .ss_freq_table = NULL,
+ .ss_mode_table = NULL,
+
+ .clk_generate_parameter = lcd_clk_generate_g12a,
+ .pll_frac_generate = lcd_pll_frac_generate_g12a,
+ .set_ss_level = NULL,
+ .set_ss_advance = NULL,
.clk_set = lcd_clk_set_g12a_path1,
- .clk_config_init_print = lcd_clk_config_init_print_axg,
+ .vclk_crt_set = lcd_set_vclk_crt,
+ .clk_disable = lcd_clk_disable_dft,
+ .clk_config_init_print = lcd_clk_config_init_print_g12a,
.clk_config_print = lcd_clk_config_print_g12a,
+ .prbs_clk_config = NULL,
};
static struct lcd_clk_data_s lcd_clk_data_g12b_path0 = {
- .ss_level_max = SS_LEVEL_MAX_HPLL_G12A,
.pll_od_fb = PLL_OD_FB_HPLL_G12A,
- .pll_m_max = PLL_M_MAX_G12A,
- .pll_m_min = PLL_M_MIN_G12A,
- .pll_n_max = PLL_N_MAX_G12A,
- .pll_n_min = PLL_N_MIN_G12A,
+ .pll_m_max = PLL_M_MAX,
+ .pll_m_min = PLL_M_MIN,
+ .pll_n_max = PLL_N_MAX,
+ .pll_n_min = PLL_N_MIN,
.pll_frac_range = PLL_FRAC_RANGE_HPLL_G12A,
+ .pll_frac_sign_bit = PLL_FRAC_SIGN_BIT_HPLL_G12A,
.pll_od_sel_max = PLL_OD_SEL_MAX_HPLL_G12A,
- .pll_ref_fmax = PLL_FREF_MAX_G12A,
- .pll_ref_fmin = PLL_FREF_MIN_G12A,
+ .pll_ref_fmax = PLL_FREF_MAX,
+ .pll_ref_fmin = PLL_FREF_MIN,
.pll_vco_fmax = PLL_VCO_MAX_HPLL_G12A,
.pll_vco_fmin = PLL_VCO_MIN_HPLL_G12A,
.pll_out_fmax = CRT_VID_CLK_IN_MAX_G12A,
@@ -1310,28 +3088,39 @@
.clk_path_valid = 1,
.vclk_sel = 0,
+ .enc_clk_msr_id = 9,
.pll_ctrl_table = pll_ctrl_table_g12a_path0,
- .pll_ss_table = NULL,
+
+ .ss_level_max = 0,
+ .ss_freq_max = 0,
+ .ss_mode_max = 0,
+ .ss_level_table = NULL,
+ .ss_freq_table = NULL,
+ .ss_mode_table = NULL,
.clk_generate_parameter = lcd_clk_generate_hpll_g12a,
- .pll_frac_generate = lcd_pll_frac_generate_txl,
- .set_spread_spectrum = NULL,
+ .pll_frac_generate = lcd_pll_frac_generate_dft,
+ .set_ss_level = NULL,
+ .set_ss_advance = NULL,
.clk_set = lcd_clk_set_g12b_path0,
- .clk_config_init_print = lcd_clk_config_init_print_axg,
+ .vclk_crt_set = lcd_set_vclk_crt,
+ .clk_disable = lcd_clk_disable_dft,
+ .clk_config_init_print = lcd_clk_config_init_print_g12a,
.clk_config_print = lcd_clk_config_print_g12a,
+ .prbs_clk_config = NULL,
};
static struct lcd_clk_data_s lcd_clk_data_g12b_path1 = {
- .ss_level_max = SS_LEVEL_MAX_GP0_G12A,
.pll_od_fb = PLL_OD_FB_GP0_G12A,
- .pll_m_max = PLL_M_MAX_G12A,
- .pll_m_min = PLL_M_MIN_G12A,
- .pll_n_max = PLL_N_MAX_G12A,
- .pll_n_min = PLL_N_MIN_G12A,
+ .pll_m_max = PLL_M_MAX,
+ .pll_m_min = PLL_M_MIN,
+ .pll_n_max = PLL_N_MAX,
+ .pll_n_min = PLL_N_MIN,
.pll_frac_range = PLL_FRAC_RANGE_GP0_G12A,
+ .pll_frac_sign_bit = PLL_FRAC_SIGN_BIT_GP0_G12A,
.pll_od_sel_max = PLL_OD_SEL_MAX_GP0_G12A,
- .pll_ref_fmax = PLL_FREF_MAX_G12A,
- .pll_ref_fmin = PLL_FREF_MIN_G12A,
+ .pll_ref_fmax = PLL_FREF_MAX,
+ .pll_ref_fmin = PLL_FREF_MIN,
.pll_vco_fmax = PLL_VCO_MAX_GP0_G12A,
.pll_vco_fmin = PLL_VCO_MIN_GP0_G12A,
.pll_out_fmax = CRT_VID_CLK_IN_MAX_G12A,
@@ -1342,47 +3131,279 @@
.clk_path_valid = 1,
.vclk_sel = 1,
+ .enc_clk_msr_id = 9,
.pll_ctrl_table = pll_ctrl_table_g12a_path1,
- .pll_ss_table = NULL,
- .clk_generate_parameter = lcd_clk_generate_axg,
- .pll_frac_generate = lcd_pll_frac_generate_axg,
- .set_spread_spectrum = NULL,
+ .ss_level_max = 0,
+ .ss_freq_max = 0,
+ .ss_mode_max = 0,
+ .ss_level_table = NULL,
+ .ss_freq_table = NULL,
+ .ss_mode_table = NULL,
+
+ .clk_generate_parameter = lcd_clk_generate_g12a,
+ .pll_frac_generate = lcd_pll_frac_generate_g12a,
+ .set_ss_level = NULL,
+ .set_ss_advance = NULL,
.clk_set = lcd_clk_set_g12b_path1,
- .clk_config_init_print = lcd_clk_config_init_print_axg,
+ .vclk_crt_set = lcd_set_vclk_crt,
+ .clk_disable = lcd_clk_disable_dft,
+ .clk_config_init_print = lcd_clk_config_init_print_g12a,
.clk_config_print = lcd_clk_config_print_g12a,
+ .prbs_clk_config = NULL,
};
-static void lcd_clk_config_chip_init(struct lcd_clk_config_s *cConf)
-{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
+static struct lcd_clk_data_s lcd_clk_data_tl1 = {
+ .pll_od_fb = PLL_OD_FB_TL1,
+ .pll_m_max = PLL_M_MAX,
+ .pll_m_min = PLL_M_MIN,
+ .pll_n_max = PLL_N_MAX,
+ .pll_n_min = PLL_N_MIN,
+ .pll_frac_range = PLL_FRAC_RANGE_TL1,
+ .pll_frac_sign_bit = PLL_FRAC_SIGN_BIT_TL1,
+ .pll_od_sel_max = PLL_OD_SEL_MAX_TL1,
+ .pll_ref_fmax = PLL_FREF_MAX,
+ .pll_ref_fmin = PLL_FREF_MIN,
+ .pll_vco_fmax = PLL_VCO_MAX_TL1,
+ .pll_vco_fmin = PLL_VCO_MIN_TL1,
+ .pll_out_fmax = CLK_DIV_IN_MAX_TL1,
+ .pll_out_fmin = PLL_VCO_MIN_TL1 / 16,
+ .div_in_fmax = CLK_DIV_IN_MAX_TL1,
+ .div_out_fmax = CRT_VID_CLK_IN_MAX_TL1,
+ .xd_out_fmax = ENCL_CLK_IN_MAX_TL1,
- switch (lcd_drv->chip_type) {
+ .clk_path_valid = 0,
+ .vclk_sel = 0,
+ .enc_clk_msr_id = 9,
+ .pll_ctrl_table = pll_ctrl_table_tl1,
+
+ .ss_level_max = sizeof(lcd_ss_level_table_tl1) / sizeof(char *),
+ .ss_freq_max = sizeof(lcd_ss_freq_table_tl1) / sizeof(char *),
+ .ss_mode_max = sizeof(lcd_ss_mode_table_tl1) / sizeof(char *),
+ .ss_level_table = lcd_ss_level_table_tl1,
+ .ss_freq_table = lcd_ss_freq_table_tl1,
+ .ss_mode_table = lcd_ss_mode_table_tl1,
+
+ .clk_generate_parameter = lcd_clk_generate_tl1,
+ .pll_frac_generate = lcd_pll_frac_generate_dft,
+ .set_ss_level = lcd_set_pll_ss_level_tl1,
+ .set_ss_advance = lcd_set_pll_ss_advance_tl1,
+ .clk_set = lcd_clk_set_tl1,
+ .vclk_crt_set = lcd_set_vclk_crt,
+ .clk_disable = lcd_clk_disable_dft,
+ .clk_config_init_print = lcd_clk_config_init_print_dft,
+ .clk_config_print = lcd_clk_config_print_dft,
+ .prbs_clk_config = lcd_prbs_config_clk_tl1,
+};
+
+static struct lcd_clk_data_s lcd_clk_data_tm2 = {
+ .pll_od_fb = PLL_OD_FB_TL1,
+ .pll_m_max = PLL_M_MAX,
+ .pll_m_min = PLL_M_MIN,
+ .pll_n_max = PLL_N_MAX,
+ .pll_n_min = PLL_N_MIN,
+ .pll_frac_range = PLL_FRAC_RANGE_TL1,
+ .pll_frac_sign_bit = PLL_FRAC_SIGN_BIT_TL1,
+ .pll_od_sel_max = PLL_OD_SEL_MAX_TL1,
+ .pll_ref_fmax = PLL_FREF_MAX,
+ .pll_ref_fmin = PLL_FREF_MIN,
+ .pll_vco_fmax = PLL_VCO_MAX_TM2,
+ .pll_vco_fmin = PLL_VCO_MIN_TM2,
+ .pll_out_fmax = CLK_DIV_IN_MAX_TL1,
+ .pll_out_fmin = PLL_VCO_MIN_TL1 / 16,
+ .div_in_fmax = CLK_DIV_IN_MAX_TL1,
+ .div_out_fmax = CRT_VID_CLK_IN_MAX_TL1,
+ .xd_out_fmax = ENCL_CLK_IN_MAX_TL1,
+
+ .clk_path_valid = 0,
+ .vclk_sel = 0,
+ .enc_clk_msr_id = 9,
+ .pll_ctrl_table = pll_ctrl_table_tl1,
+
+ .ss_level_max = sizeof(lcd_ss_level_table_tl1) / sizeof(char *),
+ .ss_freq_max = sizeof(lcd_ss_freq_table_tl1) / sizeof(char *),
+ .ss_mode_max = sizeof(lcd_ss_mode_table_tl1) / sizeof(char *),
+ .ss_level_table = lcd_ss_level_table_tl1,
+ .ss_freq_table = lcd_ss_freq_table_tl1,
+ .ss_mode_table = lcd_ss_mode_table_tl1,
+
+ .clk_generate_parameter = lcd_clk_generate_tl1,
+ .pll_frac_generate = lcd_pll_frac_generate_dft,
+ .set_ss_level = lcd_set_pll_ss_level_tl1,
+ .set_ss_advance = lcd_set_pll_ss_advance_tl1,
+ .clk_set = lcd_clk_set_tl1,
+ .vclk_crt_set = lcd_set_vclk_crt,
+ .clk_disable = lcd_clk_disable_dft,
+ .clk_config_init_print = lcd_clk_config_init_print_dft,
+ .clk_config_print = lcd_clk_config_print_dft,
+ .prbs_clk_config = lcd_prbs_config_clk_tl1,
+};
+
+static struct lcd_clk_data_s lcd_clk_data_t5d = {
+ .pll_od_fb = PLL_OD_FB_TL1,
+ .pll_m_max = PLL_M_MAX,
+ .pll_m_min = PLL_M_MIN,
+ .pll_n_max = PLL_N_MAX,
+ .pll_n_min = PLL_N_MIN,
+ .pll_frac_range = PLL_FRAC_RANGE_TL1,
+ .pll_frac_sign_bit = PLL_FRAC_SIGN_BIT_TL1,
+ .pll_od_sel_max = PLL_OD_SEL_MAX_TL1,
+ .pll_ref_fmax = PLL_FREF_MAX,
+ .pll_ref_fmin = PLL_FREF_MIN,
+ .pll_vco_fmax = PLL_VCO_MAX_TM2,
+ .pll_vco_fmin = PLL_VCO_MIN_TM2,
+ .pll_out_fmax = CLK_DIV_IN_MAX_T5D,
+ .pll_out_fmin = PLL_VCO_MIN_TL1 / 16,
+ .div_in_fmax = CLK_DIV_IN_MAX_T5D,
+ .div_out_fmax = CRT_VID_CLK_IN_MAX_T5D,
+ .xd_out_fmax = ENCL_CLK_IN_MAX_T5D,
+
+ .clk_path_valid = 0,
+ .vclk_sel = 0,
+ .enc_clk_msr_id = 9,
+ .pll_ctrl_table = pll_ctrl_table_tl1,
+
+ .ss_level_max = sizeof(lcd_ss_level_table_tl1) / sizeof(char *),
+ .ss_freq_max = sizeof(lcd_ss_freq_table_tl1) / sizeof(char *),
+ .ss_mode_max = sizeof(lcd_ss_mode_table_tl1) / sizeof(char *),
+ .ss_level_table = lcd_ss_level_table_tl1,
+ .ss_freq_table = lcd_ss_freq_table_tl1,
+ .ss_mode_table = lcd_ss_mode_table_tl1,
+
+ .clk_generate_parameter = lcd_clk_generate_tl1,
+ .pll_frac_generate = lcd_pll_frac_generate_dft,
+ .set_ss_level = lcd_set_pll_ss_level_tl1,
+ .set_ss_advance = lcd_set_pll_ss_advance_tl1,
+ .clk_set = lcd_clk_set_tl1,
+ .vclk_crt_set = lcd_set_vclk_crt,
+ .clk_disable = lcd_clk_disable_dft,
+ .clk_config_init_print = lcd_clk_config_init_print_dft,
+ .clk_config_print = lcd_clk_config_print_dft,
+ .prbs_clk_config = lcd_prbs_config_clk_tl1,
+};
+
+static struct lcd_clk_data_s lcd_clk_data_t7 = {
+ .pll_od_fb = PLL_OD_FB_TL1,
+ .pll_m_max = PLL_M_MAX,
+ .pll_m_min = PLL_M_MIN,
+ .pll_n_max = PLL_N_MAX,
+ .pll_n_min = PLL_N_MIN,
+ .pll_frac_range = PLL_FRAC_RANGE_TL1,
+ .pll_frac_sign_bit = PLL_FRAC_SIGN_BIT_TL1,
+ .pll_od_sel_max = PLL_OD_SEL_MAX_TL1,
+ .pll_ref_fmax = PLL_FREF_MAX,
+ .pll_ref_fmin = PLL_FREF_MIN,
+ .pll_vco_fmax = PLL_VCO_MAX_TM2,
+ .pll_vco_fmin = PLL_VCO_MIN_TM2,
+ .pll_out_fmax = CLK_DIV_IN_MAX_TL1,
+ .pll_out_fmin = PLL_VCO_MIN_TL1 / 16,
+ .div_in_fmax = CLK_DIV_IN_MAX_TL1,
+ .div_out_fmax = CRT_VID_CLK_IN_MAX_TL1,
+ .xd_out_fmax = ENCL_CLK_IN_MAX_TL1,
+
+ .clk_path_valid = 0,
+ .vclk_sel = 0,
+ .enc_clk_msr_id = 222,
+ .pll_ctrl_table = pll_ctrl_table_t7,
+
+ .ss_level_max = sizeof(lcd_ss_level_table_tl1) / sizeof(char *),
+ .ss_freq_max = sizeof(lcd_ss_freq_table_tl1) / sizeof(char *),
+ .ss_mode_max = sizeof(lcd_ss_mode_table_tl1) / sizeof(char *),
+ .ss_level_table = lcd_ss_level_table_tl1,
+ .ss_freq_table = lcd_ss_freq_table_tl1,
+ .ss_mode_table = lcd_ss_mode_table_tl1,
+
+ .clk_generate_parameter = lcd_clk_generate_tl1,
+ .pll_frac_generate = lcd_pll_frac_generate_dft,
+ .set_ss_level = lcd_set_pll_ss_level_t7,
+ .set_ss_advance = lcd_set_pll_ss_advance_tl1,
+ .clk_set = lcd_clk_set_t7,
+ .vclk_crt_set = lcd_set_vclk_crt_t7,
+ .clk_disable = lcd_clk_disable_t7,
+ .clk_config_init_print = lcd_clk_config_init_print_dft,
+ .clk_config_print = lcd_clk_config_print_dft,
+ .prbs_clk_config = lcd_prbs_config_clk_t7,
+};
+
+static void lcd_clk_config_chip_init(struct aml_lcd_drv_s *pdrv,
+ struct lcd_clk_config_s *cconf)
+{
+ cconf->pll_id = 0;
+ cconf->pll_offset = 0;
+ cconf->fin = FIN_FREQ;
+ switch (pdrv->data->chip_type) {
case LCD_CHIP_G12A:
case LCD_CHIP_SM1:
- if (lcd_drv->lcd_config->lcd_clk_path)
- cConf->data = &lcd_clk_data_g12a_path1;
+ if (pdrv->clk_path)
+ cconf->data = &lcd_clk_data_g12a_path1;
else
- cConf->data = &lcd_clk_data_g12a_path0;
+ cconf->data = &lcd_clk_data_g12a_path0;
break;
case LCD_CHIP_G12B:
- if (lcd_drv->lcd_config->lcd_clk_path)
- cConf->data = &lcd_clk_data_g12b_path1;
+ if (pdrv->clk_path)
+ cconf->data = &lcd_clk_data_g12b_path1;
else
- cConf->data = &lcd_clk_data_g12b_path0;
+ cconf->data = &lcd_clk_data_g12b_path0;
+ break;
+ case LCD_CHIP_TL1:
+ cconf->data = &lcd_clk_data_tl1;
+ break;
+ case LCD_CHIP_TM2:
+ case LCD_CHIP_T5:
+ cconf->data = &lcd_clk_data_tm2;
+ break;
+ case LCD_CHIP_T5D:
+ cconf->data = &lcd_clk_data_t5d;
+ break;
+ case LCD_CHIP_T7:
+ cconf->data = &lcd_clk_data_t7;
+ switch (pdrv->index) {
+ case 1:
+ cconf->data->enc_clk_msr_id = 221;
+ cconf->pll_id = 1;
+ cconf->pll_offset = (0x5 << 2);
+ break;
+ case 2:
+ cconf->data->enc_clk_msr_id = 220;
+ cconf->pll_id = 2;
+ cconf->pll_offset = (0xa << 2);
+ break;
+ case 0:
+ default:
+ cconf->data->enc_clk_msr_id = 222;
+ cconf->pll_id = 0;
+ cconf->pll_offset = 0;
+ break;
+ }
+ cconf->data->enc_clk_msr_id = -1;
break;
default:
- LCDPR("%s invalid chip type\n", __func__);
- break;
+ LCDPR("%s: invalid chip type\n", __func__);
+ return;
}
- if (cConf->data)
- cConf->pll_od_fb = cConf->data->pll_od_fb;
- if (lcd_debug_print_flag > 0)
- lcd_clk_config_init_print();
+ cconf->pll_od_fb = cconf->data->pll_od_fb;
+ if (lcd_debug_print_flag & LCD_DBG_PR_CLK) {
+ if (cconf->data->clk_config_init_print)
+ cconf->data->clk_config_init_print(pdrv);
+ }
}
-void lcd_clk_config_probe(void)
+void lcd_clk_config_probe(struct aml_lcd_drv_s *pdrv)
{
- lcd_clk_config_chip_init(&clk_conf);
+ struct lcd_clk_config_s *cconf;
+
+ if (!pdrv->clk_conf) {
+ cconf = (struct lcd_clk_config_s *)malloc(sizeof(struct lcd_clk_config_s));
+ if (!cconf) {
+ LCDERR("[%d]: %s: Not enough memory\n", pdrv->index, __func__);
+ return;
+ }
+ pdrv->clk_conf = (void *)cconf;
+ } else {
+ cconf = (struct lcd_clk_config_s *)pdrv->clk_conf;
+ }
+ memset(cconf, 0, sizeof(struct lcd_clk_config_s));
+
+ lcd_clk_config_chip_init(pdrv, cconf);
}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_clk_config.h b/drivers/amlogic/media/vout/lcd/lcd_clk_config.h
index d1d76d0..c50357f 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_clk_config.h
+++ b/drivers/amlogic/media/vout/lcd/lcd_clk_config.h
@@ -1,21 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/vout/lcd/lcd_clk_config.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef _LCD_CLK_CONFIG_H
@@ -27,6 +12,11 @@
/* **********************************
* clk config
* ********************************** */
+#define LCD_PLL_MODE_DEFAULT BIT(0)
+#define LCD_PLL_MODE_SPECIAL_CNTL BIT(1)
+#define LCD_PLL_MODE_FRAC_SHIFT BIT(2)
+
+#define PLL_RETRY_MAX 20
#define LCD_CLK_CTRL_EN 0
#define LCD_CLK_CTRL_RST 1
#define LCD_CLK_CTRL_FRAC 2
@@ -43,13 +33,13 @@
struct lcd_clk_data_s {
/* clk path node parameters */
- unsigned int ss_level_max;
unsigned int pll_od_fb;
unsigned int pll_m_max;
unsigned int pll_m_min;
unsigned int pll_n_max;
unsigned int pll_n_min;
unsigned int pll_frac_range;
+ unsigned int pll_frac_sign_bit;
unsigned int pll_od_sel_max;
unsigned int pll_ref_fmax;
unsigned int pll_ref_fmin;
@@ -63,15 +53,26 @@
unsigned char clk_path_valid;
unsigned char vclk_sel;
+ int enc_clk_msr_id;
struct lcd_clk_ctrl_s *pll_ctrl_table;
- char **pll_ss_table;
- void (*clk_generate_parameter)(struct lcd_config_s *pconf);
- void (*pll_frac_generate)(struct lcd_config_s *pconf);
- void (*set_spread_spectrum)(unsigned int ss_level);
- void (*clk_set)(struct lcd_config_s *pconf);
- void (*clk_config_init_print)(void);
- void (*clk_config_print)(void);
+ unsigned int ss_level_max;
+ unsigned int ss_freq_max;
+ unsigned int ss_mode_max;
+ char **ss_level_table;
+ char **ss_freq_table;
+ char **ss_mode_table;
+
+ void (*clk_generate_parameter)(struct aml_lcd_drv_s *pdrv);
+ void (*pll_frac_generate)(struct aml_lcd_drv_s *pdrv);
+ void (*set_ss_level)(struct aml_lcd_drv_s *pdrv);
+ void (*set_ss_advance)(struct aml_lcd_drv_s *pdrv);
+ void (*clk_set)(struct aml_lcd_drv_s *pdrv);
+ void (*vclk_crt_set)(struct aml_lcd_drv_s *pdrv);
+ void (*clk_disable)(struct aml_lcd_drv_s *pdrv);
+ void (*clk_config_init_print)(struct aml_lcd_drv_s *pdrv);
+ void (*clk_config_print)(struct aml_lcd_drv_s *pdrv);
+ void (*prbs_clk_config)(struct aml_lcd_drv_s *pdrv, unsigned int lcd_prbs_mode);
};
struct lcd_clk_config_s { /* unit: kHz */
@@ -80,6 +81,8 @@
unsigned int fout;
/* pll parameters */
+ unsigned int pll_id;
+ unsigned int pll_offset;
unsigned int pll_mode; /* txl */
unsigned int pll_od_fb;
unsigned int pll_m;
@@ -88,32 +91,39 @@
unsigned int pll_od1_sel;
unsigned int pll_od2_sel;
unsigned int pll_od3_sel;
- unsigned int pll_pi_div_sel; /* for tcon */
+ unsigned int pll_tcon_div_sel;
unsigned int pll_level;
unsigned int pll_frac;
+ unsigned int pll_frac_half_shift;
unsigned int pll_fout;
unsigned int ss_level;
+ unsigned int ss_freq;
+ unsigned int ss_mode;
+ unsigned int edp_div0;
+ unsigned int edp_div1;
unsigned int div_sel;
unsigned int xd;
unsigned int div_sel_max;
unsigned int xd_max;
unsigned int err_fmin;
+ unsigned int done;
struct lcd_clk_data_s *data;
};
-
/* ******** api ******** */
-extern struct lcd_clk_config_s *get_lcd_clk_config(void);
-extern void lcd_clk_config_print(void);
+struct lcd_clk_config_s *get_lcd_clk_config(struct aml_lcd_drv_s *pdrv);
-extern char *lcd_get_spread_spectrum(void);
-extern void lcd_set_spread_spectrum(unsigned int ss_level);
-extern void lcd_clk_update(struct lcd_config_s *pconf);
-extern void lcd_clk_set(struct lcd_config_s *pconf);
-extern void lcd_clk_disable(void);
+void lcd_clk_config_print(struct aml_lcd_drv_s *pdrv);
-extern void lcd_clk_generate_parameter(struct lcd_config_s *pconf);
-extern void lcd_clk_config_probe(void);
+void lcd_get_ss(struct aml_lcd_drv_s *pdrv);
+int lcd_set_ss(struct aml_lcd_drv_s *pdrv, unsigned int level,
+ unsigned int freq, unsigned int mode);
+void lcd_update_clk(struct aml_lcd_drv_s *pdrv);
+void lcd_set_clk(struct aml_lcd_drv_s *pdrv);
+void lcd_disable_clk(struct aml_lcd_drv_s *pdrv);
+
+void lcd_clk_generate_parameter(struct aml_lcd_drv_s *pdrv);
+void lcd_clk_config_probe(struct aml_lcd_drv_s *pdrv);
#endif
diff --git a/drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h b/drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h
index b8971bc..53f8dad 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h
+++ b/drivers/amlogic/media/vout/lcd/lcd_clk_ctrl.h
@@ -1,21 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/vout/lcd/aml_lcd_clk_ctrl.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef _LCD_CLK_CONFIG_CTRL_H
@@ -24,6 +9,17 @@
#include "lcd_reg.h"
#include "lcd_clk_config.h"
+/* **********************************
+ * COMMON
+ * **********************************
+ */
+#define PLL_M_MIN 2
+#define PLL_M_MAX 511
+#define PLL_N_MIN 1
+#define PLL_N_MAX 1
+#define PLL_FREF_MIN (5 * 1000)
+#define PLL_FREF_MAX (25 * 1000)
+
/* G12A */
/* ******** register bit ******** */
/* PLL_CNTL bit: GP0 */
@@ -37,6 +33,7 @@
/* ******** frequency limit (unit: kHz) ******** */
#define PLL_OD_FB_GP0_G12A 0
#define PLL_FRAC_RANGE_GP0_G12A (1 << 17)
+#define PLL_FRAC_SIGN_BIT_GP0_G12A 18
#define PLL_OD_SEL_MAX_GP0_G12A 5
#define PLL_VCO_MIN_GP0_G12A (3000 * 1000)
#define PLL_VCO_MAX_GP0_G12A (6000 * 1000)
@@ -55,20 +52,68 @@
/* ******** frequency limit (unit: kHz) ******** */
#define PLL_OD_FB_HPLL_G12A 0
#define PLL_FRAC_RANGE_HPLL_G12A (1 << 17)
+#define PLL_FRAC_SIGN_BIT_HPLL_G12A 18
#define PLL_OD_SEL_MAX_HPLL_G12A 3
#define PLL_VCO_MIN_HPLL_G12A (3000 * 1000)
#define PLL_VCO_MAX_HPLL_G12A (6000 * 1000)
/* video */
-#define PLL_M_MIN_G12A 2
-#define PLL_M_MAX_G12A 511
-#define PLL_N_MIN_G12A 1
-#define PLL_N_MAX_G12A 1
-#define PLL_FREF_MIN_G12A (5 * 1000)
-#define PLL_FREF_MAX_G12A (25 * 1000)
#define CRT_VID_CLK_IN_MAX_G12A (6000 * 1000)
#define ENCL_CLK_IN_MAX_G12A (200 * 1000)
+/* **********************************
+ * TL1
+ * **********************************
+ */
+/* ******** register bit ******** */
+/* PLL_CNTL 0x20 */
+#define LCD_PLL_LOCK_TL1 31
+#define LCD_PLL_EN_TL1 28
+#define LCD_PLL_RST_TL1 29
+#define LCD_PLL_N_TL1 10
+#define LCD_PLL_M_TL1 0
+
+#define LCD_PLL_OD3_TL1 19
+#define LCD_PLL_OD2_TL1 23
+#define LCD_PLL_OD1_TL1 21
+
+/* ******** frequency limit (unit: kHz) ******** */
+#define PLL_OD_FB_TL1 0
+#define PLL_FRAC_RANGE_TL1 (1 << 17)
+#define PLL_FRAC_SIGN_BIT_TL1 18
+#define PLL_OD_SEL_MAX_TL1 3
+#define PLL_VCO_MIN_TL1 (3384 * 1000)
+#define PLL_VCO_MAX_TL1 (6024 * 1000)
+
+/* video */
+#define CLK_DIV_IN_MAX_TL1 (3100 * 1000)
+#define CRT_VID_CLK_IN_MAX_TL1 (3100 * 1000)
+#define ENCL_CLK_IN_MAX_TL1 (750 * 1000)
+
+/* **********************************
+ * TM2
+ * **********************************
+ */
+#define PLL_VCO_MIN_TM2 (3000 * 1000)
+#define PLL_VCO_MAX_TM2 (6000 * 1000)
+
+/* **********************************
+ * T5D
+ * **********************************
+ */
+/* video */
+#define CLK_DIV_IN_MAX_T5D (3100 * 1000)
+#define CRT_VID_CLK_IN_MAX_T5D (3100 * 1000)
+#define ENCL_CLK_IN_MAX_T5D (400 * 1000)
+
+/* **********************************
+ * T7
+ * **********************************
+ */
+#define LCD_PLL_OD3_T7 23
+#define LCD_PLL_OD2_T7 21
+#define LCD_PLL_OD1_T7 19
+#define LCD_PLL_LOCK_T7 31
/* **********************************
* Spread Spectrum
@@ -76,27 +121,125 @@
*/
#define LCD_SS_STEP_BASE 500 /* ppm */
-#define SS_LEVEL_MAX_GP0_G12A 0
-#define SS_LEVEL_MAX_HPLL_G12A 0
+static char *lcd_ss_level_table_tl1[] = {
+ "0, disable",
+ "1, 2000ppm",
+ "2, 4000ppm",
+ "3, 6000ppm",
+ "4, 8000ppm",
+ "5, 10000ppm",
+ "6, 12000ppm",
+ "7, 14000ppm",
+ "8, 16000ppm",
+ "9, 18000ppm",
+ "10, 20000ppm",
+ "11, 22000ppm",
+ "12, 24000ppm",
+ "13, 25000ppm",
+ "14, 28000ppm",
+ "15, 30000ppm",
+ "16, 32000ppm",
+ "17, 33000ppm",
+ "18, 36000ppm",
+ "19, 38500ppm",
+ "20, 40000ppm",
+ "21, 42000ppm",
+ "22, 44000ppm",
+ "23, 45000ppm",
+ "24, 48000ppm",
+ "25, 50000ppm",
+ "26, 50000ppm",
+ "27, 54000ppm",
+ "28, 55000ppm",
+ "29, 55000ppm",
+ "30, 60000ppm",
+};
+
+static char *lcd_ss_freq_table_tl1[] = {
+ "0, 29.5KHz",
+ "1, 31.5KHz",
+ "2, 50KHz",
+ "3, 75KHz",
+ "4, 100KHz",
+ "5, 150KHz",
+ "6, 200KHz",
+};
+
+static char *lcd_ss_mode_table_tl1[] = {
+ "0, center ss",
+ "1, up ss",
+ "2, down ss",
+};
+
+static unsigned int pll_ss_reg_tl1[][2] = {
+ /* dep_sel, str_m */
+ { 0, 0}, /* 0: disable */
+ { 4, 1}, /* 1: +/-0.1% */
+ { 4, 2}, /* 2: +/-0.2% */
+ { 4, 3}, /* 3: +/-0.3% */
+ { 4, 4}, /* 4: +/-0.4% */
+ { 4, 5}, /* 5: +/-0.5% */
+ { 4, 6}, /* 6: +/-0.6% */
+ { 4, 7}, /* 7: +/-0.7% */
+ { 4, 8}, /* 8: +/-0.8% */
+ { 4, 9}, /* 9: +/-0.9% */
+ { 4, 10}, /* 10: +/-1.0% */
+ { 11, 4}, /* 11: +/-1.1% */
+ { 12, 4}, /* 12: +/-1.2% */
+ { 10, 5}, /* 13: +/-1.25% */
+ { 8, 7}, /* 14: +/-1.4% */
+ { 6, 10}, /* 15: +/-1.5% */
+ { 8, 8}, /* 16: +/-1.6% */
+ { 11, 6}, /* 17: +/-1.65% */
+ { 8, 9}, /* 18: +/-1.8% */
+ { 11, 7}, /* 19: +/-1.925% */
+ { 10, 8}, /* 20: +/-2.0% */
+ { 12, 7}, /* 21: +/-2.1% */
+ { 11, 8}, /* 22: +/-2.2% */
+ { 9, 10}, /* 23: +/-2.25% */
+ { 12, 8}, /* 24: +/-2.4% */
+ { 10, 10}, /* 25: +/-2.5% */
+ { 10, 10}, /* 26: +/-2.5% */
+ { 12, 9}, /* 27: +/-2.7% */
+ { 11, 10}, /* 28: +/-2.75% */
+ { 11, 10}, /* 29: +/-2.75% */
+ { 12, 10}, /* 30: +/-3.0% */
+};
/* **********************************
* pll control
* **********************************
*/
-static struct lcd_clk_ctrl_s pll_ctrl_table_g12a_path0[] = {
+struct lcd_clk_ctrl_s pll_ctrl_table_g12a_path0[] = {
/* flag reg bit len*/
{LCD_CLK_CTRL_EN, HHI_HDMI_PLL_CNTL0, LCD_PLL_EN_HPLL_G12A, 1},
{LCD_CLK_CTRL_FRAC, HHI_HDMI_PLL_CNTL1, 0, 19},
{LCD_CLK_CTRL_END, LCD_CLK_REG_END, 0, 0},
};
-static struct lcd_clk_ctrl_s pll_ctrl_table_g12a_path1[] = {
+struct lcd_clk_ctrl_s pll_ctrl_table_g12a_path1[] = {
/* flag reg bit len*/
{LCD_CLK_CTRL_EN, HHI_GP0_PLL_CNTL0, LCD_PLL_EN_GP0_G12A, 1},
{LCD_CLK_CTRL_FRAC, HHI_GP0_PLL_CNTL1, 0, 19},
{LCD_CLK_CTRL_END, LCD_CLK_REG_END, 0, 0},
};
+struct lcd_clk_ctrl_s pll_ctrl_table_tl1[] = {
+ /* flag reg bit len*/
+ {LCD_CLK_CTRL_EN, HHI_TCON_PLL_CNTL0, LCD_PLL_EN_TL1, 1},
+ {LCD_CLK_CTRL_RST, HHI_TCON_PLL_CNTL0, LCD_PLL_RST_TL1, 1},
+ {LCD_CLK_CTRL_FRAC, HHI_TCON_PLL_CNTL1, 0, 17},
+ {LCD_CLK_CTRL_END, LCD_CLK_REG_END, 0, 0},
+};
+
+struct lcd_clk_ctrl_s pll_ctrl_table_t7[] = {
+ /* flag reg bit len*/
+ {LCD_CLK_CTRL_EN, ANACTRL_TCON_PLL0_CNTL0, LCD_PLL_EN_TL1, 1},
+ {LCD_CLK_CTRL_RST, ANACTRL_TCON_PLL0_CNTL0, LCD_PLL_RST_TL1, 1},
+ {LCD_CLK_CTRL_FRAC, ANACTRL_TCON_PLL0_CNTL1, 0, 17},
+ {LCD_CLK_CTRL_END, LCD_CLK_REG_END, 0, 0},
+};
+
/* **********************************
* pll & clk parameter
* ********************************** */
@@ -111,11 +254,28 @@
/* divider */
#define CRT_VID_DIV_MAX 255
+#define DIV_PRE_SEL_MAX 6
+#define EDP_DIV0_SEL_MAX 15
+#define EDP_DIV1_SEL_MAX 8
+
static const unsigned int od_fb_table[2] = {1, 2};
-
static const unsigned int od_table[6] = {1, 2, 4, 8, 16, 32};
+static const unsigned int tcon_div_table[5] = {1, 2, 4, 8, 16};
+static unsigned int tcon_div[5][3] = {
+ /* div_mux, div2/4_sel, div4_bypass */
+ {1, 0, 1}, /* div1 */
+ {0, 0, 1}, /* div2 */
+ {0, 1, 1}, /* div4 */
+ {0, 0, 0}, /* div8 */
+ {0, 1, 0}, /* div16 */
+};
-/* static const unsigned int pi_div_table[2] = {2, 4}; */
+static unsigned int edp_div0_table[15] = {
+ 1, 2, 3, 4, 5, 7, 8, 9, 11, 13, 17, 19, 23, 29, 31
+};
+static unsigned int edp_div1_table[10] = {
+ 1, 2, 3, 4, 5, 6, 7, 8, 9, 13
+};
static char *lcd_clk_div_sel_table[] = {
"1",
@@ -133,6 +293,7 @@
"14",
"15",
"2.5",
+ "4.67",
"invalid",
};
@@ -155,6 +316,7 @@
CLK_DIV_SEL_14, /* 12 */
CLK_DIV_SEL_15, /* 13 */
CLK_DIV_SEL_2p5, /* 14 */
+ CLK_DIV_SEL_4p67, /* 15 */
CLK_DIV_SEL_MAX,
};
@@ -175,6 +337,7 @@
{CLK_DIV_SEL_14, 0x3f80, 1,},
{CLK_DIV_SEL_15, 0x7f80, 2,},
{CLK_DIV_SEL_2p5, 0x5294, 2,},
+ {CLK_DIV_SEL_4p67, 0x0ccc, 1,},
{CLK_DIV_SEL_MAX, 0xffff, 0,},
};
diff --git a/drivers/amlogic/media/vout/lcd/lcd_common.c b/drivers/amlogic/media/vout/lcd/lcd_common.c
index 8750d91..4566a3d 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_common.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_common.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_common.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -37,6 +22,8 @@
{"vbyone", LCD_VBYONE},
{"mipi", LCD_MIPI},
{"minilvds", LCD_MLVDS},
+ {"p2p", LCD_P2P},
+ {"edp", LCD_EDP},
{"invalid", LCD_TYPE_MAX},
};
@@ -90,342 +77,164 @@
return lcd_mode_table[mode];
}
-/* ***************************************
- * lcd gpio
- * *************************************** */
-static struct lcd_cpu_gpio_s lcd_gpio[LCD_CPU_GPIO_NUM_MAX] = {
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
-};
-
-void lcd_cpu_gpio_info_print(void)
+static void lcd_config_load_print(struct aml_lcd_drv_s *pdrv)
{
- int i;
+ struct lcd_config_s *pconf = &pdrv->config;
+ union lcd_ctrl_config_u *pctrl;
- LCDPR("cpu gpio info:\n");
- for (i = 0; i < LCD_CPU_GPIO_NUM_MAX; i++) {
- if (strcmp(lcd_gpio[i].name, "invalid") == 0)
- break;
- if (lcd_gpio[i].probe_flag == 1) {
- printf("%d: %s, register=%d\n",
- i, lcd_gpio[i].name, lcd_gpio[i].register_flag);
+ LCDPR("[%d]: %s, %s, %dbit, %dx%d\n",
+ pdrv->index,
+ pconf->basic.model_name,
+ lcd_type_type_to_str(pconf->basic.lcd_type),
+ pconf->basic.lcd_bits,
+ pconf->basic.h_active, pconf->basic.v_active);
+
+ if ((lcd_debug_print_flag & LCD_DBG_PR_NORMAL) == 0)
+ return;
+
+ LCDPR("h_period = %d\n", pconf->basic.h_period);
+ LCDPR("v_period = %d\n", pconf->basic.v_period);
+
+ LCDPR("h_period_min = %d\n", pconf->basic.h_period_min);
+ LCDPR("h_period_max = %d\n", pconf->basic.h_period_max);
+ LCDPR("v_period_min = %d\n", pconf->basic.v_period_min);
+ LCDPR("v_period_max = %d\n", pconf->basic.v_period_max);
+ LCDPR("pclk_min = %d\n", pconf->basic.lcd_clk_min);
+ LCDPR("pclk_max = %d\n", pconf->basic.lcd_clk_max);
+
+ LCDPR("hsync_width = %d\n", pconf->timing.hsync_width);
+ LCDPR("hsync_bp = %d\n", pconf->timing.hsync_bp);
+ LCDPR("hsync_pol = %d\n", pconf->timing.hsync_pol);
+ LCDPR("vsync_width = %d\n", pconf->timing.vsync_width);
+ LCDPR("vsync_bp = %d\n", pconf->timing.vsync_bp);
+ LCDPR("vsync_pol = %d\n", pconf->timing.vsync_pol);
+
+ LCDPR("fr_adjust_type = %d\n", pconf->timing.fr_adjust_type);
+ LCDPR("ss_level = %d\n", pconf->timing.ss_level);
+ LCDPR("clk_auto = %d\n", pconf->timing.clk_auto);
+ LCDPR("pixel_clk = %d\n", pconf->timing.lcd_clk);
+
+ pctrl = &pconf->control;
+ if (pconf->basic.lcd_type == LCD_TTL) {
+ LCDPR("clk_pol = %d\n", pctrl->ttl_cfg.clk_pol);
+ LCDPR("sync_valid = %d\n", pctrl->ttl_cfg.sync_valid);
+ LCDPR("swap_ctrl = %d\n", pctrl->ttl_cfg.swap_ctrl);
+ } else if (pconf->basic.lcd_type == LCD_LVDS) {
+ LCDPR("lvds_repack = %d\n", pctrl->lvds_cfg.lvds_repack);
+ LCDPR("pn_swap = %d\n", pctrl->lvds_cfg.pn_swap);
+ LCDPR("dual_port = %d\n", pctrl->lvds_cfg.dual_port);
+ LCDPR("port_swap = %d\n", pctrl->lvds_cfg.port_swap);
+ LCDPR("lane_reverse = %d\n", pctrl->lvds_cfg.lane_reverse);
+ LCDPR("phy_vswing = 0x%x\n", pctrl->lvds_cfg.phy_vswing);
+ LCDPR("phy_preem = 0x%x\n", pctrl->lvds_cfg.phy_preem);
+ } else if (pconf->basic.lcd_type == LCD_VBYONE) {
+ LCDPR("lane_count = %d\n", pctrl->vbyone_cfg.lane_count);
+ LCDPR("byte_mode = %d\n", pctrl->vbyone_cfg.byte_mode);
+ LCDPR("region_num = %d\n", pctrl->vbyone_cfg.region_num);
+ LCDPR("color_fmt = %d\n", pctrl->vbyone_cfg.color_fmt);
+ LCDPR("phy_vswing = 0x%x\n", pctrl->vbyone_cfg.phy_vswing);
+ LCDPR("phy_preem = 0x%x\n", pctrl->vbyone_cfg.phy_preem);
+ } else if (pconf->basic.lcd_type == LCD_MLVDS) {
+ LCDPR("channel_num = %d\n", pctrl->mlvds_cfg.channel_num);
+ LCDPR("channel_sel0 = %d\n", pctrl->mlvds_cfg.channel_sel0);
+ LCDPR("channel_sel1 = %d\n", pctrl->mlvds_cfg.channel_sel1);
+ LCDPR("clk_phase = %d\n", pctrl->mlvds_cfg.clk_phase);
+ LCDPR("phy_vswing = 0x%x\n", pctrl->mlvds_cfg.phy_vswing);
+ LCDPR("phy_preem = 0x%x\n", pctrl->mlvds_cfg.phy_preem);
+ } else if (pconf->basic.lcd_type == LCD_P2P) {
+ LCDPR("p2p_type = %d\n", pctrl->p2p_cfg.p2p_type);
+ LCDPR("lane_num = %d\n", pctrl->p2p_cfg.lane_num);
+ LCDPR("channel_sel0 = %d\n", pctrl->p2p_cfg.channel_sel0);
+ LCDPR("channel_sel1 = %d\n", pctrl->p2p_cfg.channel_sel1);
+ LCDPR("phy_vswing = 0x%x\n", pctrl->p2p_cfg.phy_vswing);
+ LCDPR("phy_preem = 0x%x\n", pctrl->p2p_cfg.phy_preem);
+ } else if (pconf->basic.lcd_type == LCD_MIPI) {
+ if (pctrl->mipi_cfg.check_en) {
+ LCDPR("check_reg = 0x%02x\n",
+ pctrl->mipi_cfg.check_reg);
+ LCDPR("check_cnt = %d\n",
+ pctrl->mipi_cfg.check_cnt);
}
- }
- printf("\n");
-}
+ LCDPR("lane_num = %d\n", pctrl->mipi_cfg.lane_num);
+ LCDPR("bit_rate_max = %d\n", pctrl->mipi_cfg.bit_rate_max);
+ LCDPR("pclk_lanebyteclk_factor = %d\n", pctrl->mipi_cfg.factor_numerator);
+ LCDPR("operation_mode_init = %d\n", pctrl->mipi_cfg.operation_mode_init);
+ LCDPR("operation_mode_disp = %d\n", pctrl->mipi_cfg.operation_mode_display);
+ LCDPR("video_mode_type = %d\n", pctrl->mipi_cfg.video_mode_type);
+ LCDPR("clk_always_hs = %d\n", pctrl->mipi_cfg.clk_always_hs);
+ LCDPR("phy_switch = %d\n", pctrl->mipi_cfg.phy_switch);
+ LCDPR("extern_init = %d\n", pctrl->mipi_cfg.extern_init);
+ } else if (pconf->basic.lcd_type == LCD_EDP) {
+ LCDPR("max_lane_count = %d\n", pctrl->edp_cfg.max_lane_count);
+ LCDPR("max_link_rate = %d\n", pctrl->edp_cfg.max_link_rate);
+ LCDPR("training_mode = %d\n", pctrl->edp_cfg.training_mode);
+ LCDPR("dpcd_caps_en = %d\n", pctrl->edp_cfg.dpcd_caps_en);
+ LCDPR("sync_clk_mode = %d\n", pctrl->edp_cfg.sync_clk_mode);
-int lcd_gpio_probe(const char *name, int index)
-{
- if (name == NULL) {
- LCDERR("%s: gpio name is null\n", __func__);
- return -1;
- }
- if (index >= LCD_CPU_GPIO_NUM_MAX) {
- LCDERR("%s: invalid gpio: %d\n", __func__, index);
- return -1;
- }
- if (lcd_gpio[index].probe_flag == 1) {
- if (lcd_debug_print_flag) {
- LCDPR("gpio %s(%d) is already probed\n",
- lcd_gpio[index].name, index);
- }
- return 0;
- }
+ LCDPR("lane_count = %d\n", pctrl->edp_cfg.lane_count);
+ LCDPR("link_rate = %d\n", pctrl->edp_cfg.link_rate);
+ LCDPR("bit_rate = %d\n", pctrl->edp_cfg.bit_rate);
+ LCDPR("training_settings = %d\n", pctrl->edp_cfg.training_settings);
+ LCDPR("main_stream_enable = %d\n", pctrl->edp_cfg.main_stream_enable);
- if (lcd_debug_print_flag)
- LCDPR("probe gpio: %s(%d)\n", name, index);
- strcpy(lcd_gpio[index].name, name);
- /* init gpio flag */
- lcd_gpio[index].probe_flag = 1;
- lcd_gpio[index].register_flag = 0;
-
- return 0;
-}
-
-static int lcd_gpio_request(int index)
-{
- int ret = 0;
-
- if (index >= LCD_CPU_GPIO_NUM_MAX) {
- LCDERR("%s: invalid gpio: %d\n", __func__, index);
- return -1;
- }
- if (lcd_gpio[index].probe_flag == 0) {
- LCDERR("gpio %d is not probed\n", index);
- return -1;
- }
- if (lcd_gpio[index].register_flag == 1) {
- if (lcd_debug_print_flag) {
- LCDPR("gpio %s(%d) is already registered\n",
- lcd_gpio[index].name, index);
- }
- return 0;
- }
-
- ret = dm_gpio_lookup_name(lcd_gpio[index].name, &lcd_gpio[index].gpio);
- if (ret) {
- LCDERR("lookup gpio: wrong name %s\n", lcd_gpio[index].name);
- return -1;
- }
-
- ret = dm_gpio_request(&lcd_gpio[index].gpio, "aml_lcd");
- if (ret) {
- LCDERR("request gpio %s(%d) failed\n", lcd_gpio[index].name, index);
- return -1;
- }
-
- if (lcd_debug_print_flag)
- LCDPR("request gpio: %s(%d)\n", lcd_gpio[index].name, index);
- lcd_gpio[index].register_flag = 1;
-
- return 0;
-}
-
-int lcd_gpio_set(int index, int value)
-{
- int ret = 0;
-
- if (index >= LCD_CPU_GPIO_NUM_MAX) {
- LCDERR("%s: invalid gpio: %d\n", __func__, index);
- return -1;
- }
- if (lcd_gpio[index].register_flag == 0) {
- ret = lcd_gpio_request(index);
- if (ret)
- return -1;
- }
-
- switch (value) {
- case LCD_GPIO_OUTPUT_LOW:
- ret = dm_gpio_set_dir_flags(&lcd_gpio[index].gpio, GPIOD_IS_OUT);
- if (ret) {
- LCDERR("set gpio %s(%d) direction failed\n",
- lcd_gpio[index].name, index);
- return ret;
- }
- dm_gpio_set_value(&lcd_gpio[index].gpio, 0);
- break;
- case LCD_GPIO_OUTPUT_HIGH:
- ret = dm_gpio_set_dir_flags(&lcd_gpio[index].gpio, GPIOD_IS_OUT);
- if (ret) {
- LCDERR("set gpio %s(%d) direction failed\n",
- lcd_gpio[index].name, index);
- return ret;
- }
- dm_gpio_set_value(&lcd_gpio[index].gpio, 1);
- break;
- case LCD_GPIO_INPUT:
- default:
- ret = dm_gpio_set_dir_flags(&lcd_gpio[index].gpio, GPIOD_IS_IN);
- if (ret) {
- LCDERR("set gpio %s(%d) direction failed\n",
- lcd_gpio[index].name, index);
- return ret;
- }
- break;
- }
- if (lcd_debug_print_flag) {
- LCDPR("gpio: %s(%d), value: %d\n",
- lcd_gpio[index].name, index, value);
- }
-
- return 0;
-}
-
-unsigned int lcd_gpio_input_get(int index)
-{
- int ret;
- unsigned int value;
-
- if (index >= LCD_CPU_GPIO_NUM_MAX) {
- LCDERR("%s: invalid gpio: %d\n", __func__, index);
- return 0;
- }
- if (lcd_gpio[index].register_flag == 0) {
- ret = lcd_gpio_request(index);
- if (ret)
- return 0;
- }
-
- value = dm_gpio_get_value(&lcd_gpio[index].gpio);
-
- return value;
-}
-/* *************************************** */
-
-unsigned int lcd_lvds_channel_on_value(struct lcd_config_s *pconf)
-{
- unsigned int channel_on = 0;
-
- if (pconf->lcd_control.lvds_config->dual_port == 0) {
- if (pconf->lcd_control.lvds_config->lane_reverse == 0) {
- switch (pconf->lcd_basic.lcd_bits) {
- case 6:
- channel_on = 0xf;
- break;
- case 8:
- channel_on = 0x1f;
- break;
- case 10:
- default:
- channel_on = 0x3f;
- break;
- }
- } else {
- switch (pconf->lcd_basic.lcd_bits) {
- case 6:
- channel_on = 0x3c;
- break;
- case 8:
- channel_on = 0x3e;
- break;
- case 10:
- default:
- channel_on = 0x3f;
- break;
- }
- }
- if (pconf->lcd_control.lvds_config->port_swap == 1)
- channel_on = (channel_on << 6); /* use channel B */
- } else {
- if (pconf->lcd_control.lvds_config->lane_reverse == 0) {
- switch (pconf->lcd_basic.lcd_bits) {
- case 6:
- channel_on = 0x3cf;
- break;
- case 8:
- channel_on = 0x7df;
- break;
- case 10:
- default:
- channel_on = 0xfff;
- break;
- }
- } else {
- switch (pconf->lcd_basic.lcd_bits) {
- case 6:
- channel_on = 0xf3c;
- break;
- case 8:
- channel_on = 0xfbe;
- break;
- case 10:
- default:
- channel_on = 0xfff;
- break;
- }
- }
- }
- return channel_on;
-}
-
-void lcd_pinmux_set(int status)
-{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- struct lcd_config_s *pconf;
- int i;
-
- if (lcd_debug_print_flag)
- LCDPR("%s: %d\n", __func__, status);
-
- pconf = lcd_drv->lcd_config;
- if (status) {
- i = 0;
- while (i < LCD_PINMUX_NUM) {
- if (pconf->pinmux_clr[i][0] == LCD_PINMUX_END)
- break;
- if (lcd_debug_print_flag) {
- LCDPR("pinmux_clr: %d, 0x%08x\n",
- pconf->pinmux_clr[i][0],
- pconf->pinmux_clr[i][1]);
- }
- lcd_pinmux_clr_mask(pconf->pinmux_clr[i][0],
- pconf->pinmux_clr[i][1]);
- i++;
- }
- i = 0;
- while (i < LCD_PINMUX_NUM) {
- if (pconf->pinmux_set[i][0] == LCD_PINMUX_END)
- break;
- if (lcd_debug_print_flag) {
- LCDPR("pinmux_set: %d, 0x%08x\n",
- pconf->pinmux_set[i][0],
- pconf->pinmux_set[i][1]);
- }
- lcd_pinmux_set_mask(pconf->pinmux_set[i][0],
- pconf->pinmux_set[i][1]);
- i++;
- }
- } else {
- i = 0;
- while (i < LCD_PINMUX_NUM) {
- if (pconf->pinmux_set[i][0] == LCD_PINMUX_END)
- break;
- if (lcd_debug_print_flag) {
- LCDPR("pinmux_clr: %d, 0x%08x\n",
- pconf->pinmux_set[i][0],
- pconf->pinmux_set[i][1]);
- }
- lcd_pinmux_clr_mask(pconf->pinmux_set[i][0],
- pconf->pinmux_set[i][1]);
- i++;
- }
+ LCDPR("phy_vswing = 0x%x\n", pctrl->edp_cfg.phy_vswing);
+ LCDPR("phy_preem = 0x%x\n", pctrl->edp_cfg.phy_preem);
}
}
-int lcd_power_load_from_dts(struct lcd_config_s *pconf, const void *dt_blob, int child_offset)
+static int lcd_power_load_from_dts(struct aml_lcd_drv_s *pdrv,
+ char *dt_addr, int child_offset)
{
+ struct lcd_power_step_s *pstep;
char *propdata;
unsigned int i, j, temp;
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "power_on_step", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get power_on_step\n");
+ pstep = pdrv->config.power.power_on_step;
+ propdata = (char *)fdt_getprop(dt_addr, child_offset, "power_on_step", NULL);
+ if (!propdata) {
+ LCDERR("[%d]: failed to get power_on_step\n", pdrv->index);
return 0;
} else {
i = 0;
while (i < LCD_PWR_STEP_MAX) {
j = 4 * i;
- temp = be32_to_cpup((((u32*)propdata)+j));
- pconf->lcd_power->power_on_step[i].type = temp;
+ temp = be32_to_cpup((((u32*)propdata) + j));
+ pstep[i].type = temp;
if (temp == 0xff)
break;
- temp = be32_to_cpup((((u32*)propdata)+j+1));
- pconf->lcd_power->power_on_step[i].index = temp;
- temp = be32_to_cpup((((u32*)propdata)+j+2));
- pconf->lcd_power->power_on_step[i].value = temp;
- temp = be32_to_cpup((((u32*)propdata)+j+3));
- pconf->lcd_power->power_on_step[i].delay = temp;
+ temp = be32_to_cpup((((u32*)propdata) + j + 1));
+ pstep[i].index = temp;
+ temp = be32_to_cpup((((u32*)propdata) + j + 2));
+ pstep[i].value = temp;
+ temp = be32_to_cpup((((u32*)propdata) + j + 3));
+ pstep[i].delay = temp;
+ if (pstep[i].type == LCD_POWER_TYPE_CLK_SS) {
+ temp = pstep[i].value;
+ pdrv->config.timing.ss_level |= temp << 8;
+ }
i++;
}
}
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "power_off_step", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get power_off_step\n");
+ pstep = pdrv->config.power.power_off_step;
+ propdata = (char *)fdt_getprop(dt_addr, child_offset, "power_off_step", NULL);
+ if (!propdata) {
+ LCDERR("[%d]: failed to get power_off_step\n", pdrv->index);
return 0;
} else {
i = 0;
while (i < LCD_PWR_STEP_MAX) {
j = 4 * i;
- temp = be32_to_cpup((((u32*)propdata)+j));
- pconf->lcd_power->power_off_step[i].type = temp;
+ temp = be32_to_cpup((((u32*)propdata) + j));
+ pstep[i].type = temp;
if (temp == 0xff)
break;
- temp = be32_to_cpup((((u32*)propdata)+j+1));
- pconf->lcd_power->power_off_step[i].index = temp;
- temp = be32_to_cpup((((u32*)propdata)+j+2));
- pconf->lcd_power->power_off_step[i].value = temp;
- temp = be32_to_cpup((((u32*)propdata)+j+3));
- pconf->lcd_power->power_off_step[i].delay = temp;
+ temp = be32_to_cpup((((u32*)propdata) + j + 1));
+ pstep[i].index = temp;
+ temp = be32_to_cpup((((u32*)propdata) + j + 2));
+ pstep[i].value = temp;
+ temp = be32_to_cpup((((u32*)propdata) + j + 3));
+ pstep[i].delay = temp;
i++;
}
}
@@ -433,79 +242,80 @@
return 0;
}
-int lcd_power_load_from_unifykey(struct lcd_config_s *pconf,
- unsigned char *buf, int key_len, int len)
+static int lcd_power_load_from_unifykey(struct aml_lcd_drv_s *pdrv,
+ unsigned char *buf, int key_len, int len)
{
- int i, j;
+ struct lcd_power_step_s *pstep;
+ int i, j, temp;
unsigned char *p;
int ret = 0;
/* power: (5byte * n) */
+ pstep = pdrv->config.power.power_on_step;
p = buf + len;
- if (lcd_debug_print_flag)
- LCDPR("power_on step:\n");
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: power_on step:\n", pdrv->index);
i = 0;
while (i < LCD_PWR_STEP_MAX) {
len += 5;
- ret = aml_lcd_unifykey_len_check(key_len, len);
+ ret = lcd_unifykey_len_check(key_len, len);
if (ret) {
- pconf->lcd_power->power_on_step[i].type = 0xff;
- pconf->lcd_power->power_on_step[i].index = 0;
- pconf->lcd_power->power_on_step[i].value = 0;
- pconf->lcd_power->power_on_step[i].delay = 0;
+ pstep[i].type = 0xff;
+ pstep[i].index = 0;
+ pstep[i].value = 0;
+ pstep[i].delay = 0;
LCDERR("unifykey power_on length is incorrect\n");
return -1;
}
- pconf->lcd_power->power_on_step[i].type = *(p + LCD_UKEY_PWR_TYPE + 5*i);
- pconf->lcd_power->power_on_step[i].index = *(p + LCD_UKEY_PWR_INDEX + 5*i);
- pconf->lcd_power->power_on_step[i].value = *(p + LCD_UKEY_PWR_VAL + 5*i);
- pconf->lcd_power->power_on_step[i].delay =
- (*(p + LCD_UKEY_PWR_DELAY + 5*i) |
- ((*(p + LCD_UKEY_PWR_DELAY + 5*i + 1)) << 8));
+ pstep[i].type = *(p + LCD_UKEY_PWR_TYPE + 5 * i);
+ pstep[i].index = *(p + LCD_UKEY_PWR_INDEX + 5 * i);
+ pstep[i].value = *(p + LCD_UKEY_PWR_VAL + 5 * i);
+ pstep[i].delay = (*(p + LCD_UKEY_PWR_DELAY + 5 * i) |
+ ((*(p + LCD_UKEY_PWR_DELAY + 5 * i + 1)) << 8));
- if (lcd_debug_print_flag) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
LCDPR("step %d: type=%d, index=%d, value=%d, delay=%d\n",
- i, pconf->lcd_power->power_on_step[i].type,
- pconf->lcd_power->power_on_step[i].index,
- pconf->lcd_power->power_on_step[i].value,
- pconf->lcd_power->power_on_step[i].delay);
+ i, pstep[i].type, pstep[i].index,
+ pstep[i].value, pstep[i].delay);
}
- if (pconf->lcd_power->power_on_step[i].type >= LCD_POWER_TYPE_MAX)
+ if (pstep[i].type >= LCD_POWER_TYPE_MAX)
break;
+ if (pstep[i].type == LCD_POWER_TYPE_CLK_SS) {
+ temp = pstep[i].value;
+ pdrv->config.timing.ss_level |= temp << 8;
+ }
i++;
}
- if (lcd_debug_print_flag)
- LCDPR("power_off step:\n");
- p += (5*(i + 1));
+ pstep = pdrv->config.power.power_off_step;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: power_off step:\n", pdrv->index);
+ p += (5 * (i + 1));
j = 0;
while (j < LCD_PWR_STEP_MAX) {
len += 5;
- ret = aml_lcd_unifykey_len_check(key_len, len);
+ ret = lcd_unifykey_len_check(key_len, len);
if (ret) {
- pconf->lcd_power->power_off_step[j].type = 0xff;
- pconf->lcd_power->power_off_step[j].index = 0;
- pconf->lcd_power->power_off_step[j].value = 0;
- pconf->lcd_power->power_off_step[j].delay = 0;
+ pstep[j].type = 0xff;
+ pstep[j].index = 0;
+ pstep[j].value = 0;
+ pstep[j].delay = 0;
LCDERR("unifykey power_off length is incorrect\n");
return -1;
}
- pconf->lcd_power->power_off_step[j].type = *(p + LCD_UKEY_PWR_TYPE + 5*j);
- pconf->lcd_power->power_off_step[j].index = *(p + LCD_UKEY_PWR_INDEX + 5*j);
- pconf->lcd_power->power_off_step[j].value = *(p + LCD_UKEY_PWR_VAL + 5*j);
- pconf->lcd_power->power_off_step[j].delay =
- (*(p + LCD_UKEY_PWR_DELAY + 5*j) |
- ((*(p + LCD_UKEY_PWR_DELAY + 5*j + 1)) << 8));
+ pstep[j].type = *(p + LCD_UKEY_PWR_TYPE + 5 * j);
+ pstep[j].index = *(p + LCD_UKEY_PWR_INDEX + 5 * j);
+ pstep[j].value = *(p + LCD_UKEY_PWR_VAL + 5 * j);
+ pstep[j].delay = (*(p + LCD_UKEY_PWR_DELAY + 5 * j) |
+ ((*(p + LCD_UKEY_PWR_DELAY + 5 * j + 1)) << 8));
- if (lcd_debug_print_flag) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
LCDPR("step %d: type=%d, index=%d, value=%d, delay=%d\n",
- j, pconf->lcd_power->power_off_step[j].type,
- pconf->lcd_power->power_off_step[j].index,
- pconf->lcd_power->power_off_step[j].value,
- pconf->lcd_power->power_off_step[j].delay);
+ j, pstep[j].type, pstep[j].index,
+ pstep[j].value, pstep[j].delay);
}
- if (pconf->lcd_power->power_off_step[j].type >= LCD_POWER_TYPE_MAX)
+ if (pstep[j].type >= LCD_POWER_TYPE_MAX)
break;
j++;
@@ -522,209 +332,202 @@
"lcd_ttl_de_hvsync_on_pin", /* 4 */
};
-static int lcd_pinmux_load_from_bsp(struct lcd_config_s *pconf)
+static int lcd_pinmux_load_ttl(struct lcd_pinmux_ctrl_s *pinmux, struct lcd_config_s *pconf)
{
- char propname[50];
- struct lcd_pinmux_ctrl_s *pinmux;
- unsigned int i, j;
+ char propname[30];
int pinmux_index = 0, set_cnt = 0, clr_cnt = 0;
+ unsigned int i, j;
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
-
- if (pconf->lcd_pinmux == NULL) {
- LCDERR("%s: lcd_pinmux is NULL for lcd.c\n", __func__);
- return -1;
+ /* data */
+ if (pconf->basic.lcd_bits == 6)
+ pinmux_index = 0;
+ else
+ pinmux_index = 1;
+ sprintf(propname, "%s", lcd_ttl_pinmux_str[pinmux_index]);
+ for (i = 0; i < LCD_PINMX_MAX; i++) {
+ if (!pinmux)
+ break;
+ if (!pinmux->name)
+ break;
+ if (strncmp(pinmux->name, "invalid", 7) == 0)
+ break;
+ if (strncmp(pinmux->name, propname,
+ strlen(propname)) == 0) {
+ for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
+ if (pinmux->pinmux_set[j][0] == LCD_PINMUX_END)
+ break;
+ pconf->pinmux_set[j][0] = pinmux->pinmux_set[j][0];
+ pconf->pinmux_set[j][1] = pinmux->pinmux_set[j][1];
+ set_cnt++;
+ }
+ for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
+ if (pinmux->pinmux_clr[j][0] == LCD_PINMUX_END)
+ break;
+ pconf->pinmux_clr[j][0] = pinmux->pinmux_clr[j][0];
+ pconf->pinmux_clr[j][1] = pinmux->pinmux_clr[j][1];
+ clr_cnt++;
+ }
+ break;
+ }
+ pinmux++;
}
- switch (pconf->lcd_basic.lcd_type) {
- case LCD_TTL:
- /* data */
- if (pconf->lcd_basic.lcd_bits == 6)
- pinmux_index = 0;
- else
- pinmux_index = 1;
- sprintf(propname, "%s", lcd_ttl_pinmux_str[pinmux_index]);
- pinmux = pconf->lcd_pinmux;
- for (i = 0; i < LCD_PINMX_MAX; i++) {
- pinmux += i;
- if (strncmp(pinmux->name, "invalid", 7) == 0)
- break;
- if (strncmp(pinmux->name, propname, strlen(propname)) == 0) {
- for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
- if (pinmux->pinmux_set[j][0] == LCD_PINMUX_END)
- break;
- pconf->pinmux_set[j][0] = pinmux->pinmux_set[j][0];
- pconf->pinmux_set[j][1] = pinmux->pinmux_set[j][1];
- set_cnt++;
- }
- for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
- if (pinmux->pinmux_clr[j][0] == LCD_PINMUX_END)
- break;
- pconf->pinmux_clr[j][0] = pinmux->pinmux_clr[j][0];
- pconf->pinmux_clr[j][1] = pinmux->pinmux_clr[j][1];
- clr_cnt++;
- }
- break;
- }
- }
-
- /* sync */
- switch (pconf->lcd_control.ttl_config->sync_valid) {
- case 0x1: /* hvsync */
- pinmux_index = 3;
- break;
- case 0x2: /* de */
- pinmux_index = 2;
- break;
- case 0x3: /* de + hvsync */
- default:
- pinmux_index = 4;
- break;
- }
- sprintf(propname, "%s", lcd_ttl_pinmux_str[pinmux_index]);
- pinmux = pconf->lcd_pinmux;
- for (i = 0; i < LCD_PINMX_MAX; i++) {
- pinmux += i;
- if (strncmp(pinmux->name, "invalid", 7) == 0)
- break;
- if (strncmp(pinmux->name, propname, strlen(propname)) == 0) {
- for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
- if (pinmux->pinmux_set[j][0] == LCD_PINMUX_END)
- break;
- pconf->pinmux_set[j+set_cnt][0] = pinmux->pinmux_set[j][0];
- pconf->pinmux_set[j+set_cnt][1] = pinmux->pinmux_set[j][1];
- set_cnt++;
- }
- for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
- if (pinmux->pinmux_clr[j][0] == LCD_PINMUX_END)
- break;
- pconf->pinmux_clr[j+clr_cnt][0] = pinmux->pinmux_clr[j][0];
- pconf->pinmux_clr[j+clr_cnt][1] = pinmux->pinmux_clr[j][1];
- clr_cnt++;
- }
- break;
- }
- }
-
- if (set_cnt < LCD_PINMUX_NUM) {
- pconf->pinmux_set[set_cnt][0] = LCD_PINMUX_END;
- pconf->pinmux_set[set_cnt][1] = 0x0;
- }
- if (clr_cnt < LCD_PINMUX_NUM) {
- pconf->pinmux_clr[clr_cnt][0] = LCD_PINMUX_END;
- pconf->pinmux_clr[clr_cnt][1] = 0x0;
- }
+ /* sync */
+ switch (pconf->control.ttl_cfg.sync_valid) {
+ case 0x1: /* hvsync */
+ pinmux_index = 3;
break;
- case LCD_LVDS:
- pconf->pinmux_set[0][0] = LCD_PINMUX_END;
- pconf->pinmux_set[0][1] = 0x0;
- pconf->pinmux_clr[0][0] = LCD_PINMUX_END;
- pconf->pinmux_clr[0][1] = 0x0;
+ case 0x2: /* de */
+ pinmux_index = 2;
break;
- case LCD_MLVDS:
- sprintf(propname, "lcd_minilvds_pin");
- pinmux = pconf->lcd_pinmux;
- for (i = 0; i < LCD_PINMX_MAX; i++) {
- pinmux += i;
- if (strncmp(pinmux->name, "invalid", 7) == 0)
- break;
- if (strncmp(pinmux->name, propname, strlen(propname)) == 0) {
- for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
- if (pinmux->pinmux_set[j][0] == LCD_PINMUX_END)
- break;
- pconf->pinmux_set[j][0] = pinmux->pinmux_set[j][0];
- pconf->pinmux_set[j][1] = pinmux->pinmux_set[j][1];
- set_cnt++;
- }
- for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
- if (pinmux->pinmux_clr[j][0] == LCD_PINMUX_END)
- break;
- pconf->pinmux_clr[j][0] = pinmux->pinmux_clr[j][0];
- pconf->pinmux_clr[j][1] = pinmux->pinmux_clr[j][1];
- clr_cnt++;
- }
- break;
- }
- }
- if (set_cnt < LCD_PINMUX_NUM) {
- pconf->pinmux_set[set_cnt][0] = LCD_PINMUX_END;
- pconf->pinmux_set[set_cnt][1] = 0x0;
- }
- if (clr_cnt < LCD_PINMUX_NUM) {
- pconf->pinmux_clr[clr_cnt][0] = LCD_PINMUX_END;
- pconf->pinmux_clr[clr_cnt][1] = 0x0;
- }
- break;
- case LCD_VBYONE:
- sprintf(propname, "lcd_vbyone_pin");
- pinmux = pconf->lcd_pinmux;
- for (i = 0; i < LCD_PINMX_MAX; i++) {
- pinmux += i;
- if (strncmp(pinmux->name, "invalid", 7) == 0)
- break;
- if (strncmp(pinmux->name, propname, strlen(propname)) == 0) {
- for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
- if (pinmux->pinmux_set[j][0] == LCD_PINMUX_END)
- break;
- pconf->pinmux_set[j][0] = pinmux->pinmux_set[j][0];
- pconf->pinmux_set[j][1] = pinmux->pinmux_set[j][1];
- set_cnt++;
- }
- for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
- if (pinmux->pinmux_clr[j][0] == LCD_PINMUX_END)
- break;
- pconf->pinmux_clr[j][0] = pinmux->pinmux_clr[j][0];
- pconf->pinmux_clr[j][1] = pinmux->pinmux_clr[j][1];
- clr_cnt++;
- }
- break;
- }
- }
- if (set_cnt < LCD_PINMUX_NUM) {
- pconf->pinmux_set[set_cnt][0] = LCD_PINMUX_END;
- pconf->pinmux_set[set_cnt][1] = 0x0;
- }
- if (clr_cnt < LCD_PINMUX_NUM) {
- pconf->pinmux_clr[clr_cnt][0] = LCD_PINMUX_END;
- pconf->pinmux_clr[clr_cnt][1] = 0x0;
- }
- break;
- case LCD_MIPI:
- pconf->pinmux_set[0][0] = LCD_PINMUX_END;
- pconf->pinmux_set[0][1] = 0x0;
- pconf->pinmux_clr[0][0] = LCD_PINMUX_END;
- pconf->pinmux_clr[0][1] = 0x0;
- break;
+ case 0x3: /* de + hvsync */
default:
- LCDERR("%s: invalid lcd type\n", __func__);
+ pinmux_index = 4;
break;
}
+ sprintf(propname, "%s", lcd_ttl_pinmux_str[pinmux_index]);
+ for (i = 0; i < LCD_PINMX_MAX; i++) {
+ if (!pinmux)
+ break;
+ if (!pinmux->name)
+ break;
+ if (strncmp(pinmux->name, "invalid", 7) == 0)
+ break;
+ if (strncmp(pinmux->name, propname, strlen(propname)) == 0) {
+ for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
+ if (pinmux->pinmux_set[j][0] == LCD_PINMUX_END)
+ break;
+ pconf->pinmux_set[j][0] = pinmux->pinmux_set[j][0];
+ pconf->pinmux_set[j][1] = pinmux->pinmux_set[j][1];
+ set_cnt++;
+ }
+ for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
+ if (pinmux->pinmux_clr[j][0] == LCD_PINMUX_END)
+ break;
+ pconf->pinmux_clr[j][0] = pinmux->pinmux_clr[j][0];
+ pconf->pinmux_clr[j][1] = pinmux->pinmux_clr[j][1];
+ clr_cnt++;
+ }
+ break;
+ }
+ pinmux++;
+ }
+
+ if (set_cnt < LCD_PINMUX_NUM) {
+ pconf->pinmux_set[set_cnt][0] = LCD_PINMUX_END;
+ pconf->pinmux_set[set_cnt][1] = 0x0;
+ }
+ if (clr_cnt < LCD_PINMUX_NUM) {
+ pconf->pinmux_clr[clr_cnt][0] = LCD_PINMUX_END;
+ pconf->pinmux_clr[clr_cnt][1] = 0x0;
+ }
return 0;
}
-int lcd_pinmux_load_config(const void *dt_blob, struct lcd_config_s *pconf)
+static int lcd_pinmux_load_config(struct aml_lcd_drv_s *pdrv)
{
- int i;
+ struct lcd_pinmux_ctrl_s *pinmux;
+ struct lcd_config_s *pconf = &pdrv->config;
+ char propname[30];
+ int set_cnt = 0, clr_cnt = 0;
+ unsigned int i, j;
+ int ret = 0;
- lcd_pinmux_load_from_bsp(pconf);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
- if (lcd_debug_print_flag) {
+ if (!pdrv->data->dft_conf[pdrv->index]) {
+ LCDERR("[%d]: %s: dft_conf is NULL\n", pdrv->index, __func__);
+ return -1;
+ }
+ pinmux = pdrv->data->dft_conf[pdrv->index]->lcd_pinmux;
+ if (!pinmux) {
+ LCDERR("[%d]: %s: lcd_pinmux is NULL\n", pdrv->index, __func__);
+ return -1;
+ }
+
+ if (pconf->basic.lcd_type == LCD_TTL) {
+ ret = lcd_pinmux_load_ttl(pinmux, pconf);
+ if (ret)
+ return -1;
+ goto lcd_pinmux_load_config_next;
+ }
+
+ switch (pconf->basic.lcd_type) {
+ case LCD_VBYONE:
+ sprintf(propname, "lcd_vbyone_pin");
+ break;
+ case LCD_MLVDS:
+ sprintf(propname, "lcd_minilvds_pin");
+ break;
+ case LCD_P2P:
+ if (pconf->control.p2p_cfg.p2p_type == P2P_USIT)
+ sprintf(propname, "lcd_p2p_usit_pin");
+ else
+ sprintf(propname, "lcd_p2p_pin");
+ break;
+ case LCD_EDP:
+ sprintf(propname, "lcd_edp_pin");
+ break;
+ default:
+ pconf->pinmux_set[0][0] = LCD_PINMUX_END;
+ pconf->pinmux_set[0][1] = 0x0;
+ pconf->pinmux_clr[0][0] = LCD_PINMUX_END;
+ pconf->pinmux_clr[0][1] = 0x0;
+ return 0;
+ }
+ for (i = 0; i < LCD_PINMX_MAX; i++) {
+ if (!pinmux->name)
+ break;
+ if (strncmp(pinmux->name, "invalid", 7) == 0)
+ break;
+ if (strncmp(pinmux->name, propname, strlen(propname)) == 0) {
+ for (j = 0; j < LCD_PINMUX_NUM; j++) {
+ if (pinmux->pinmux_set[j][0] == LCD_PINMUX_END)
+ break;
+ pconf->pinmux_set[j][0] = pinmux->pinmux_set[j][0];
+ pconf->pinmux_set[j][1] = pinmux->pinmux_set[j][1];
+ set_cnt++;
+ }
+ for (j = 0; j < LCD_PINMUX_NUM; j++) {
+ if (pinmux->pinmux_clr[j][0] == LCD_PINMUX_END)
+ break;
+ pconf->pinmux_clr[j][0] = pinmux->pinmux_clr[j][0];
+ pconf->pinmux_clr[j][1] = pinmux->pinmux_clr[j][1];
+ clr_cnt++;
+ }
+ break;
+ }
+ pinmux++;
+ }
+ if (set_cnt < LCD_PINMUX_NUM) {
+ pconf->pinmux_set[set_cnt][0] = LCD_PINMUX_END;
+ pconf->pinmux_set[set_cnt][1] = 0x0;
+ }
+ if (clr_cnt < LCD_PINMUX_NUM) {
+ pconf->pinmux_clr[clr_cnt][0] = LCD_PINMUX_END;
+ pconf->pinmux_clr[clr_cnt][1] = 0x0;
+ }
+
+lcd_pinmux_load_config_next:
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
i = 0;
while (i < LCD_PINMUX_NUM) {
- if (pconf->pinmux_set[i][0] == LCD_PINMUX_END)
+ if (pdrv->config.pinmux_set[i][0] == LCD_PINMUX_END)
break;
LCDPR("pinmux_set: %d, 0x%08x\n",
- pconf->pinmux_set[i][0], pconf->pinmux_set[i][1]);
+ pdrv->config.pinmux_set[i][0],
+ pdrv->config.pinmux_set[i][1]);
i++;
}
i = 0;
while (i < LCD_PINMUX_NUM) {
- if (pconf->pinmux_clr[i][0] == LCD_PINMUX_END)
+ if (pdrv->config.pinmux_clr[i][0] == LCD_PINMUX_END)
break;
LCDPR("pinmux_clr: %d, 0x%08x\n",
- pconf->pinmux_clr[i][0], pconf->pinmux_clr[i][1]);
+ pdrv->config.pinmux_clr[i][0],
+ pdrv->config.pinmux_clr[i][1]);
i++;
}
}
@@ -732,6 +535,1331 @@
return 0;
}
+static int lcd_config_load_from_dts(char *dt_addr, struct aml_lcd_drv_s *pdrv)
+{
+#ifdef CONFIG_OF_LIBFDT
+ struct lcd_config_s *pconf = &pdrv->config;
+ union lcd_ctrl_config_u *pctrl;
+ int parent_offset;
+ int child_offset;
+ char parent_str[10], type_str[20], propname[30];
+ char *propdata;
+ unsigned int temp;
+ int len;
+
+ LCDPR("config load from dts\n");
+
+ if (pdrv->index == 0) {
+ sprintf(parent_str, "/lcd");
+ sprintf(type_str, "panel_type");
+ } else {
+ sprintf(parent_str, "/lcd%d", pdrv->index);
+ sprintf(type_str, "panel%d_type", pdrv->index);
+ }
+ parent_offset = fdt_path_offset(dt_addr, parent_str);
+ if (parent_offset < 0) {
+ LCDERR("not find %s node: %s\n",
+ parent_str, fdt_strerror(parent_offset));
+ return -1;
+ }
+
+ /* check panel_type */
+ char *panel_type = env_get(type_str);
+ if (!panel_type) {
+ LCDERR("[%d]: no %s\n", pdrv->index, type_str);
+ return -1;
+ }
+ LCDPR("[%d]: use %s=%s\n", pdrv->index, type_str, panel_type);
+
+ snprintf(propname, 30, "%s/%s", parent_str, panel_type);
+ child_offset = fdt_path_offset(dt_addr, propname);
+ if (child_offset < 0) {
+ LCDERR("[%d]: not find %s node: %s\n",
+ pdrv->index, propname, fdt_strerror(child_offset));
+ return -1;
+ }
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "model_name", NULL);
+ if (!propdata) {
+ LCDERR("[%d]: failed to get model_name\n", pdrv->index);
+ strncpy(pconf->basic.model_name, panel_type,
+ sizeof(pconf->basic.model_name) - 1);
+ } else {
+ strncpy(pconf->basic.model_name, propdata,
+ sizeof(pconf->basic.model_name) - 1);
+ }
+ pconf->basic.model_name[sizeof(pconf->basic.model_name) - 1] = '\0';
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "interface", NULL);
+ if (!propdata) {
+ LCDERR("[%d]: failed to get interface\n", pdrv->index);
+ return -1;
+ }
+ pconf->basic.lcd_type = lcd_type_str_to_type(propdata);
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "basic_setting", NULL);
+ if (!propdata) {
+ LCDERR("[%d]: failed to get basic_setting\n", pdrv->index);
+ return -1;
+ }
+ pconf->basic.h_active = be32_to_cpup((u32 *)propdata);
+ pconf->basic.v_active = be32_to_cpup((((u32 *)propdata) + 1));
+ pconf->basic.h_period = be32_to_cpup((((u32 *)propdata) + 2));
+ pconf->basic.v_period = be32_to_cpup((((u32 *)propdata) + 3));
+ pconf->basic.lcd_bits = be32_to_cpup((((u32 *)propdata) + 4));
+ pconf->basic.screen_width = be32_to_cpup((((u32 *)propdata) + 5));
+ pconf->basic.screen_height = be32_to_cpup((((u32 *)propdata) + 6));
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "range_setting", NULL);
+ if (!propdata) {
+ pconf->basic.h_period_min = pconf->basic.h_period;
+ pconf->basic.h_period_max = pconf->basic.h_period;
+ pconf->basic.v_period_min = pconf->basic.v_period;
+ pconf->basic.v_period_max = pconf->basic.v_period;
+ pconf->basic.lcd_clk_min = 0;
+ pconf->basic.lcd_clk_max = 0;
+ } else {
+ pconf->basic.h_period_min = be32_to_cpup((u32 *)propdata);
+ pconf->basic.h_period_max =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ pconf->basic.v_period_min =
+ be32_to_cpup((((u32 *)propdata) + 2));
+ pconf->basic.v_period_max =
+ be32_to_cpup((((u32 *)propdata) + 3));
+ pconf->basic.lcd_clk_min =
+ be32_to_cpup((((u32 *)propdata) + 4));
+ pconf->basic.lcd_clk_max =
+ be32_to_cpup((((u32 *)propdata) + 5));
+ }
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "lcd_timing", NULL);
+ if (!propdata) {
+ LCDERR("[%d]: failed to get lcd_timing\n", pdrv->index);
+ return -1;
+ }
+ pconf->timing.hsync_width =
+ (unsigned short)(be32_to_cpup((u32 *)propdata));
+ pconf->timing.hsync_bp =
+ (unsigned short)(be32_to_cpup((((u32 *)propdata) + 1)));
+ pconf->timing.hsync_pol =
+ (unsigned short)(be32_to_cpup((((u32 *)propdata) + 2)));
+ pconf->timing.vsync_width =
+ (unsigned short)(be32_to_cpup((((u32 *)propdata) + 3)));
+ pconf->timing.vsync_bp =
+ (unsigned short)(be32_to_cpup((((u32 *)propdata) + 4)));
+ pconf->timing.vsync_pol =
+ (unsigned short)(be32_to_cpup((((u32 *)propdata) + 5)));
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset, "clk_attr", NULL);
+ if (!propdata) {
+ LCDERR("[%d]: failed to get clk_attr\n", pdrv->index);
+ pconf->timing.fr_adjust_type = 0xff;
+ pconf->timing.ss_level = 0;
+ pconf->timing.clk_auto = 1;
+ pconf->timing.lcd_clk = 60;
+ } else {
+ pconf->timing.fr_adjust_type =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
+ pconf->timing.ss_level =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ pconf->timing.clk_auto =
+ (unsigned char)(be32_to_cpup((((u32 *)propdata) + 2)));
+ temp = be32_to_cpup((((u32 *)propdata) + 3));
+ if (temp > 0) {
+ pconf->timing.lcd_clk = temp;
+ } else {
+ pconf->timing.lcd_clk = 60;
+ LCDPR("[%d]: lcd_clk is 0, default to 60Hz\n", pdrv->index);
+ }
+ }
+
+ pctrl = &pconf->control;
+ switch (pconf->basic.lcd_type) {
+ case LCD_TTL:
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "ttl_attr", NULL);
+ if (!propdata) {
+ LCDERR("[%d]: failed to get ttl_attr\n", pdrv->index);
+ return -1;
+ }
+ pctrl->ttl_cfg.clk_pol = be32_to_cpup((u32 *)propdata);
+ pctrl->ttl_cfg.sync_valid =
+ (((be32_to_cpup((((u32 *)propdata) + 1))) << 1) |
+ ((be32_to_cpup((((u32 *)propdata) + 2))) << 0));
+ pctrl->ttl_cfg.swap_ctrl =
+ (((be32_to_cpup((((u32 *)propdata) + 3))) << 1) |
+ ((be32_to_cpup((((u32 *)propdata) + 4))) << 0));
+ break;
+ case LCD_LVDS:
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "lvds_attr", &len);
+ if (!propdata) {
+ LCDERR("[%d]: failed to get lvds_attr\n", pdrv->index);
+ return -1;
+ }
+ len = len / 4;
+ if (len == 5) {
+ pctrl->lvds_cfg.lvds_repack =
+ be32_to_cpup((u32 *)propdata);
+ pctrl->lvds_cfg.dual_port =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ pctrl->lvds_cfg.pn_swap =
+ be32_to_cpup((((u32 *)propdata) + 2));
+ pctrl->lvds_cfg.port_swap =
+ be32_to_cpup((((u32 *)propdata) + 3));
+ pctrl->lvds_cfg.lane_reverse =
+ be32_to_cpup((((u32 *)propdata) + 4));
+ } else if (len == 4) {
+ pctrl->lvds_cfg.lvds_repack =
+ be32_to_cpup((u32 *)propdata);
+ pctrl->lvds_cfg.dual_port =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ pctrl->lvds_cfg.pn_swap =
+ be32_to_cpup((((u32 *)propdata) + 2));
+ pctrl->lvds_cfg.port_swap =
+ be32_to_cpup((((u32 *)propdata) + 3));
+ pctrl->lvds_cfg.lane_reverse = 0;
+ } else {
+ LCDERR("[%d]: invalid lvds_attr parameters cnt: %d\n",
+ pdrv->index, len);
+ return -1;
+ }
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "phy_attr", &len);
+ if (!propdata) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: failed to get phy_attr\n", pdrv->index);
+ pctrl->lvds_cfg.phy_vswing = LVDS_PHY_VSWING_DFT;
+ pctrl->lvds_cfg.phy_preem = LVDS_PHY_PREEM_DFT;
+ } else {
+ pctrl->lvds_cfg.phy_vswing =
+ be32_to_cpup((u32 *)propdata);
+ pctrl->lvds_cfg.phy_preem =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("[%d]: set phy vswing=0x%x, preem=0x%x\n",
+ pdrv->index,
+ pctrl->lvds_cfg.phy_vswing,
+ pctrl->lvds_cfg.phy_preem);
+ }
+ }
+ break;
+ case LCD_VBYONE:
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "vbyone_attr", NULL);
+ if (!propdata) {
+ LCDERR("[%d]: failed to get vbyone_attr\n", pdrv->index);
+ return -1;
+ }
+ pctrl->vbyone_cfg.lane_count =
+ be32_to_cpup((u32 *)propdata);
+ pctrl->vbyone_cfg.region_num =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ pctrl->vbyone_cfg.byte_mode =
+ be32_to_cpup((((u32 *)propdata) + 2));
+ pctrl->vbyone_cfg.color_fmt =
+ be32_to_cpup((((u32 *)propdata) + 3));
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "phy_attr", NULL);
+ if (!propdata) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: failed to get phy_attr\n", pdrv->index);
+ pctrl->vbyone_cfg.phy_vswing = VX1_PHY_VSWING_DFT;
+ pctrl->vbyone_cfg.phy_preem = VX1_PHY_PREEM_DFT;
+ } else {
+ pctrl->vbyone_cfg.phy_vswing =
+ be32_to_cpup((u32 *)propdata);
+ pctrl->vbyone_cfg.phy_preem =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("set phy vswing=0x%x, preem=0x%x\n",
+ pctrl->vbyone_cfg.phy_vswing,
+ pctrl->vbyone_cfg.phy_preem);
+ }
+ }
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "vbyone_ctrl_flag", NULL);
+ if (!propdata) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: failed to get vbyone_ctrl_flag\n", pdrv->index);
+ pctrl->vbyone_cfg.ctrl_flag = 0;
+ pctrl->vbyone_cfg.power_on_reset_delay = VX1_PWR_ON_RESET_DLY_DFT;
+ pctrl->vbyone_cfg.hpd_data_delay = VX1_HPD_DATA_DELAY_DFT;
+ pctrl->vbyone_cfg.cdr_training_hold = VX1_CDR_TRAINING_HOLD_DFT;
+ } else {
+ pctrl->vbyone_cfg.ctrl_flag = be32_to_cpup((u32 *)propdata);
+ LCDPR("vbyone ctrl_flag=0x%x\n", pctrl->vbyone_cfg.ctrl_flag);
+ }
+ if (pctrl->vbyone_cfg.ctrl_flag & 0x7) {
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "vbyone_ctrl_timing", NULL);
+ if (!propdata) {
+ LCDPR("[%d]: failed to get vbyone_ctrl_timing\n", pdrv->index);
+ pctrl->vbyone_cfg.power_on_reset_delay =
+ VX1_PWR_ON_RESET_DLY_DFT;
+ pctrl->vbyone_cfg.hpd_data_delay =
+ VX1_HPD_DATA_DELAY_DFT;
+ pctrl->vbyone_cfg.cdr_training_hold =
+ VX1_CDR_TRAINING_HOLD_DFT;
+ } else {
+ pctrl->vbyone_cfg.power_on_reset_delay =
+ be32_to_cpup((u32 *)propdata);
+ pctrl->vbyone_cfg.hpd_data_delay =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ pctrl->vbyone_cfg.cdr_training_hold =
+ be32_to_cpup((((u32 *)propdata) + 2));
+ }
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("[%d]: power_on_reset_delay: %d\n",
+ pdrv->index,
+ pctrl->vbyone_cfg.power_on_reset_delay);
+ LCDPR("[%d]: hpd_data_delay: %d\n",
+ pdrv->index,
+ pctrl->vbyone_cfg.hpd_data_delay);
+ LCDPR("[%d]: cdr_training_hold: %d\n",
+ pdrv->index,
+ pctrl->vbyone_cfg.cdr_training_hold);
+ }
+ }
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "hw_filter", NULL);
+ if (!propdata) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: failed to get hw_filter\n", pdrv->index);
+ pctrl->vbyone_cfg.hw_filter_time = 0;
+ pctrl->vbyone_cfg.hw_filter_cnt = 0;
+ } else {
+ pctrl->vbyone_cfg.hw_filter_time =
+ be32_to_cpup((u32 *)propdata);
+ pctrl->vbyone_cfg.hw_filter_cnt =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("[%d]: vbyone hw_filter=0x%x 0x%x\n",
+ pdrv->index,
+ pctrl->vbyone_cfg.hw_filter_time,
+ pctrl->vbyone_cfg.hw_filter_cnt);
+ }
+ }
+ break;
+ case LCD_MLVDS:
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "minilvds_attr", &len);
+ if (!propdata) {
+ LCDERR("[%d]: failed to get minilvds_attr\n", pdrv->index);
+ return -1;
+ }
+ pctrl->mlvds_cfg.channel_num =
+ be32_to_cpup((u32 *)propdata);
+ pctrl->mlvds_cfg.channel_sel0 =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ pctrl->mlvds_cfg.channel_sel1 =
+ be32_to_cpup((((u32 *)propdata) + 2));
+ pctrl->mlvds_cfg.clk_phase =
+ be32_to_cpup((((u32 *)propdata) + 3));
+ pctrl->mlvds_cfg.pn_swap =
+ be32_to_cpup((((u32 *)propdata) + 4));
+ pctrl->mlvds_cfg.bit_swap =
+ be32_to_cpup((((u32 *)propdata) + 5));
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "phy_attr", &len);
+ if (!propdata) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: failed to get phy_attr\n", pdrv->index);
+ pctrl->mlvds_cfg.phy_vswing = LVDS_PHY_VSWING_DFT;
+ pctrl->mlvds_cfg.phy_preem = LVDS_PHY_PREEM_DFT;
+ } else {
+ pctrl->mlvds_cfg.phy_vswing =
+ be32_to_cpup((u32 *)propdata);
+ pctrl->mlvds_cfg.phy_preem =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("[%d]: set phy vswing=0x%x, preem=0x%x\n",
+ pdrv->index,
+ pctrl->mlvds_cfg.phy_vswing,
+ pctrl->mlvds_cfg.phy_preem);
+ }
+ }
+ break;
+ case LCD_P2P:
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "p2p_attr", NULL);
+ if (!propdata) {
+ LCDERR("[%d]: failed to get p2p_attr\n", pdrv->index);
+ return -1;
+ }
+ pctrl->p2p_cfg.p2p_type =
+ be32_to_cpup((u32 *)propdata);
+ pctrl->p2p_cfg.lane_num =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ pctrl->p2p_cfg.channel_sel0 =
+ be32_to_cpup((((u32 *)propdata) + 2));
+ pctrl->p2p_cfg.channel_sel1 =
+ be32_to_cpup((((u32 *)propdata) + 3));
+ pctrl->p2p_cfg.pn_swap =
+ be32_to_cpup((((u32 *)propdata) + 4));
+ pctrl->p2p_cfg.bit_swap =
+ be32_to_cpup((((u32 *)propdata) + 5));
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "phy_attr", NULL);
+ if (!propdata) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: failed to get phy_attr\n", pdrv->index);
+ pctrl->p2p_cfg.phy_vswing = 0x5;
+ pctrl->p2p_cfg.phy_preem = 0x1;
+ } else {
+ pctrl->p2p_cfg.phy_vswing = be32_to_cpup((u32 *)propdata);
+ pctrl->p2p_cfg.phy_preem =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("[%d]: set phy vswing=0x%x, preem=0x%x\n",
+ pdrv->index,
+ pctrl->p2p_cfg.phy_vswing,
+ pctrl->p2p_cfg.phy_preem);
+ }
+ }
+ break;
+ case LCD_MIPI:
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "mipi_attr", NULL);
+ if (!propdata) {
+ LCDERR("[%d]: failed to get mipi_attr\n", pdrv->index);
+ return -1;
+ }
+ pctrl->mipi_cfg.lane_num =
+ be32_to_cpup((u32 *)propdata);
+ pctrl->mipi_cfg.bit_rate_max =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ pctrl->mipi_cfg.factor_numerator =
+ be32_to_cpup((((u32 *)propdata) + 2));
+ pctrl->mipi_cfg.factor_denominator = 100;
+ pctrl->mipi_cfg.operation_mode_init =
+ be32_to_cpup((((u32 *)propdata) + 3));
+ pctrl->mipi_cfg.operation_mode_display =
+ be32_to_cpup((((u32 *)propdata) + 4));
+ pctrl->mipi_cfg.video_mode_type =
+ be32_to_cpup((((u32 *)propdata) + 5));
+ pctrl->mipi_cfg.clk_always_hs =
+ be32_to_cpup((((u32 *)propdata) + 6));
+ pctrl->mipi_cfg.phy_switch =
+ be32_to_cpup((((u32 *)propdata) + 7));
+
+ pctrl->mipi_cfg.check_en = 0;
+ pctrl->mipi_cfg.check_reg = 0xff;
+ pctrl->mipi_cfg.check_cnt = 0;
+#ifdef CONFIG_AML_LCD_TABLET
+ lcd_mipi_dsi_init_table_detect(dt_addr, child_offset,
+ &pctrl->mipi_cfg, 1);
+ lcd_mipi_dsi_init_table_detect(dt_addr, child_offset,
+ &pctrl->mipi_cfg, 0);
+#endif
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "extern_init", NULL);
+ if (!propdata) {
+ LCDERR("[%d]: failed to get extern_init\n", pdrv->index);
+ } else {
+ pctrl->mipi_cfg.extern_init =
+ be32_to_cpup((u32 *)propdata);
+ }
+#ifdef CONFIG_AML_LCD_TABLET
+ mipi_dsi_config_init(pconf);
+#endif
+ break;
+ case LCD_EDP:
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "edp_attr", NULL);
+ if (!propdata) {
+ LCDERR("[%d]: failed to get edp_attr\n", pdrv->index);
+ return -1;
+ }
+ pctrl->edp_cfg.max_lane_count =
+ (unsigned char)be32_to_cpup((u32 *)propdata);
+ pctrl->edp_cfg.max_link_rate =
+ (unsigned char)be32_to_cpup((((u32 *)propdata) + 1));
+ pctrl->edp_cfg.training_mode =
+ (unsigned char)be32_to_cpup((((u32 *)propdata) + 2));
+ pctrl->edp_cfg.dpcd_caps_en =
+ (unsigned char)be32_to_cpup((((u32 *)propdata) + 3));
+ pctrl->edp_cfg.sync_clk_mode =
+ (unsigned char)be32_to_cpup((((u32 *)propdata) + 4));
+ pctrl->edp_cfg.scramb_mode =
+ (unsigned char)be32_to_cpup((((u32 *)propdata) + 5));
+ pctrl->edp_cfg.enhanced_framing_en =
+ (unsigned char)be32_to_cpup((((u32 *)propdata) + 6));
+ pctrl->edp_cfg.edid_en =
+ (unsigned char)be32_to_cpup((((u32 *)propdata) + 7));
+
+ pctrl->edp_cfg.lane_count = pctrl->edp_cfg.max_lane_count;
+ pctrl->edp_cfg.link_rate = pctrl->edp_cfg.max_link_rate;
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "phy_attr", NULL);
+ if (!propdata) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: failed to get phy_attr\n", pdrv->index);
+ pctrl->edp_cfg.phy_vswing = 0x5;
+ pctrl->edp_cfg.phy_preem = 0x1;
+ } else {
+ pctrl->edp_cfg.phy_vswing = be32_to_cpup((u32 *)propdata);
+ pctrl->edp_cfg.phy_preem = be32_to_cpup((((u32 *)propdata) + 1));
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("[%d]: set phy vswing=0x%x, preem=0x%x\n",
+ pdrv->index,
+ pctrl->edp_cfg.phy_vswing,
+ pctrl->edp_cfg.phy_preem);
+ }
+ }
+ break;
+ default:
+ LCDERR("invalid lcd type\n");
+ break;
+ }
+
+ /* check power_step */
+ lcd_power_load_from_dts(pdrv, dt_addr, child_offset);
+
+ propdata = (char *)fdt_getprop(dt_addr, child_offset,
+ "backlight_index", NULL);
+ if (!propdata) {
+ LCDERR("[%d]: failed to get backlight_index\n", pdrv->index);
+ pconf->backlight_index = 0xff;
+ } else {
+ pconf->backlight_index = be32_to_cpup((u32 *)propdata);
+#ifdef CONFIG_AML_LCD_BACKLIGHT
+ aml_bl_index_add(pdrv->index, pconf->backlight_index);
+#endif
+ }
+#endif
+
+ return 0;
+}
+
+static int lcd_config_load_from_unifykey(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_config_s *pconf = &pdrv->config;
+ union lcd_ctrl_config_u *pctrl;
+ struct lcd_unifykey_header_s lcd_header;
+ unsigned char *para;
+ char key_str[10];
+ int key_len, len;
+ unsigned char *p;
+ const char *str;
+ unsigned int temp;
+ int ret;
+
+ LCDPR("config load from unifykey\n");
+
+ key_len = LCD_UKEY_LCD_SIZE;
+ para = (unsigned char *)malloc(sizeof(unsigned char) * key_len);
+ if (!para) {
+ LCDERR("[%d]: %s: Not enough memory\n", pdrv->index, __func__);
+ return -1;
+ }
+ memset(para, 0, (sizeof(unsigned char) * key_len));
+
+ if (pdrv->index == 0)
+ sprintf(key_str, "lcd");
+ else
+ sprintf(key_str, "lcd%d", pdrv->index);
+ ret = lcd_unifykey_get(key_str, para, &key_len);
+ if (ret) {
+ free(para);
+ return -1;
+ }
+
+ /* step 1: check header */
+ len = LCD_UKEY_HEAD_SIZE;
+ ret = lcd_unifykey_len_check(key_len, len);
+ if (ret) {
+ LCDERR("[%d]: unifykey header length is incorrect\n", pdrv->index);
+ free(para);
+ return -1;
+ }
+
+ lcd_unifykey_header_check(para, &lcd_header);
+ LCDPR("[%d]: unifykey version: 0x%04x\n", pdrv->index, lcd_header.version);
+ switch (lcd_header.version) {
+ case 2:
+ len = LCD_UKEY_DATA_LEN_V2; /*10+36+18+31+20+44+10*/
+ break;
+ default:
+ len = LCD_UKEY_DATA_LEN_V1; /*10+36+18+31+20*/
+ break;
+ }
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("unifykey header:\n");
+ LCDPR("crc32 = 0x%08x\n", lcd_header.crc32);
+ LCDPR("data_len = %d\n", lcd_header.data_len);
+ LCDPR("reserved = 0x%04x\n", lcd_header.reserved);
+ }
+
+ /* step 2: check lcd parameters */
+ ret = lcd_unifykey_len_check(key_len, len);
+ if (ret) {
+ LCDERR("[%d]: unifykey parameters length is incorrect\n", pdrv->index);
+ free(para);
+ return -1;
+ }
+
+ /* basic: 36byte */
+ p = para;
+ str = (const char *)(p + LCD_UKEY_HEAD_SIZE);
+ strncpy(pconf->basic.model_name, str,
+ sizeof(pconf->basic.model_name) - 1);
+ pconf->basic.model_name[sizeof(pconf->basic.model_name) - 1] = '\0';
+ pconf->basic.lcd_type = *(p + LCD_UKEY_INTERFACE);
+ pconf->basic.lcd_bits = *(p + LCD_UKEY_LCD_BITS);
+ pconf->basic.screen_width = (*(p + LCD_UKEY_SCREEN_WIDTH) |
+ ((*(p + LCD_UKEY_SCREEN_WIDTH + 1)) << 8));
+ pconf->basic.screen_height = (*(p + LCD_UKEY_SCREEN_HEIGHT) |
+ ((*(p + LCD_UKEY_SCREEN_HEIGHT + 1)) << 8));
+
+ /* timing: 18byte */
+ pconf->basic.h_active = (*(p + LCD_UKEY_H_ACTIVE) |
+ ((*(p + LCD_UKEY_H_ACTIVE + 1)) << 8));
+ pconf->basic.v_active = (*(p + LCD_UKEY_V_ACTIVE)) |
+ ((*(p + LCD_UKEY_V_ACTIVE + 1)) << 8);
+ pconf->basic.h_period = (*(p + LCD_UKEY_H_PERIOD)) |
+ ((*(p + LCD_UKEY_H_PERIOD + 1)) << 8);
+ pconf->basic.v_period = (*(p + LCD_UKEY_V_PERIOD)) |
+ ((*(p + LCD_UKEY_V_PERIOD + 1)) << 8);
+ pconf->timing.hsync_width = (*(p + LCD_UKEY_HS_WIDTH) |
+ ((*(p + LCD_UKEY_HS_WIDTH + 1)) << 8));
+ pconf->timing.hsync_bp = (*(p + LCD_UKEY_HS_BP) |
+ ((*(p + LCD_UKEY_HS_BP + 1)) << 8));
+ pconf->timing.hsync_pol = *(p + LCD_UKEY_HS_POL);
+ pconf->timing.vsync_width = (*(p + LCD_UKEY_VS_WIDTH) |
+ ((*(p + LCD_UKEY_VS_WIDTH + 1)) << 8));
+ pconf->timing.vsync_bp = (*(p + LCD_UKEY_VS_BP) |
+ ((*(p + LCD_UKEY_VS_BP + 1)) << 8));
+ pconf->timing.vsync_pol = *(p + LCD_UKEY_VS_POL);
+
+ /* customer: 31byte */
+ pconf->timing.fr_adjust_type = *(p + LCD_UKEY_FR_ADJ_TYPE);
+ pconf->timing.ss_level = *(p + LCD_UKEY_SS_LEVEL);
+ pconf->timing.clk_auto = *(p + LCD_UKEY_CLK_AUTO_GEN);
+ pconf->timing.lcd_clk = (*(p + LCD_UKEY_PCLK) |
+ ((*(p + LCD_UKEY_PCLK + 1)) << 8) |
+ ((*(p + LCD_UKEY_PCLK + 2)) << 16) |
+ ((*(p + LCD_UKEY_PCLK + 3)) << 24));
+ if (pconf->timing.lcd_clk == 0) {
+ pconf->timing.lcd_clk = 60;
+ LCDERR("[%d]: lcd_clk is 0, default to 60Hz\n", pdrv->index);
+ }
+ pconf->basic.h_period_min = (*(p + LCD_UKEY_H_PERIOD_MIN) |
+ ((*(p + LCD_UKEY_H_PERIOD_MIN + 1)) << 8));
+ pconf->basic.h_period_max = (*(p + LCD_UKEY_H_PERIOD_MAX) |
+ ((*(p + LCD_UKEY_H_PERIOD_MAX + 1)) << 8));
+ pconf->basic.v_period_min = (*(p + LCD_UKEY_V_PERIOD_MIN) |
+ ((*(p + LCD_UKEY_V_PERIOD_MIN + 1)) << 8));
+ pconf->basic.v_period_max = (*(p + LCD_UKEY_V_PERIOD_MAX) |
+ ((*(p + LCD_UKEY_V_PERIOD_MAX + 1)) << 8));
+ pconf->basic.lcd_clk_min = (*(p + LCD_UKEY_PCLK_MIN) |
+ ((*(p + LCD_UKEY_PCLK_MIN + 1)) << 8) |
+ ((*(p + LCD_UKEY_PCLK_MIN + 2)) << 16) |
+ ((*(p + LCD_UKEY_PCLK_MIN + 3)) << 24));
+ pconf->basic.lcd_clk_max = (*(p + LCD_UKEY_PCLK_MAX) |
+ ((*(p + LCD_UKEY_PCLK_MAX + 1)) << 8) |
+ ((*(p + LCD_UKEY_PCLK_MAX + 2)) << 16) |
+ ((*(p + LCD_UKEY_PCLK_MAX + 3)) << 24));
+
+ pctrl = &pconf->control;
+ /* interface: 20byte */
+ switch (pconf->basic.lcd_type) {
+ case LCD_TTL:
+ pctrl->ttl_cfg.clk_pol =
+ (*(p + LCD_UKEY_IF_ATTR_0) |
+ ((*(p + LCD_UKEY_IF_ATTR_0 + 1)) << 8)) & 0x1;
+ temp = (*(p + LCD_UKEY_IF_ATTR_1) |
+ ((*(p + LCD_UKEY_IF_ATTR_1 + 1)) << 8)) & 0x1; /* de_valid */
+ pctrl->ttl_cfg.sync_valid = (temp << 1);
+ temp = (*(p + LCD_UKEY_IF_ATTR_2) |
+ ((*(p + LCD_UKEY_IF_ATTR_2 + 1)) << 8)) & 0x1; /* hvsync_valid */
+ pctrl->ttl_cfg.sync_valid |= (temp << 0);
+ temp = (*(p + LCD_UKEY_IF_ATTR_3) |
+ ((*(p + LCD_UKEY_IF_ATTR_3 + 1)) << 8)) & 0x1; /* rb_swap */
+ pctrl->ttl_cfg.swap_ctrl = (temp << 1);
+ temp = (*(p + LCD_UKEY_IF_ATTR_4) |
+ ((*(p + LCD_UKEY_IF_ATTR_4 + 1)) << 8)) & 0x1; /* bit_swap */
+ pctrl->ttl_cfg.swap_ctrl |= (temp << 0);
+ break;
+ case LCD_LVDS:
+ pctrl->lvds_cfg.lvds_repack =
+ *(p + LCD_UKEY_IF_ATTR_0) |
+ ((*(p + LCD_UKEY_IF_ATTR_0 + 1)) << 8);
+ pctrl->lvds_cfg.dual_port =
+ *(p + LCD_UKEY_IF_ATTR_1) |
+ ((*(p + LCD_UKEY_IF_ATTR_1 + 1)) << 8);
+ pctrl->lvds_cfg.pn_swap =
+ *(p + LCD_UKEY_IF_ATTR_2) |
+ ((*(p + LCD_UKEY_IF_ATTR_2 + 1)) << 8);
+ pctrl->lvds_cfg.port_swap =
+ *(p + LCD_UKEY_IF_ATTR_3) |
+ ((*(p + LCD_UKEY_IF_ATTR_3 + 1)) << 8);
+ if (lcd_header.version == 1) {
+ pctrl->lvds_cfg.phy_vswing =
+ *(p + LCD_UKEY_IF_ATTR_4) |
+ ((*(p + LCD_UKEY_IF_ATTR_4 + 1)) << 8);
+ pctrl->lvds_cfg.phy_preem =
+ *(p + LCD_UKEY_IF_ATTR_5) |
+ ((*(p + LCD_UKEY_IF_ATTR_5 + 1)) << 8);
+ pctrl->lvds_cfg.lane_reverse =
+ *(p + LCD_UKEY_IF_ATTR_8) |
+ ((*(p + LCD_UKEY_IF_ATTR_8 + 1)) << 8);
+ } else {
+ pctrl->lvds_cfg.lane_reverse =
+ *(p + LCD_UKEY_IF_ATTR_4) |
+ ((*(p + LCD_UKEY_IF_ATTR_4 + 1)) << 8);
+
+ pctrl->lvds_cfg.phy_vswing = *(p + LCD_UKEY_PHY_ATTR_0);
+ pctrl->lvds_cfg.phy_preem = *(p + LCD_UKEY_PHY_ATTR_1);
+ }
+ break;
+ case LCD_VBYONE:
+ pctrl->vbyone_cfg.lane_count =
+ *(p + LCD_UKEY_IF_ATTR_0) |
+ ((*(p + LCD_UKEY_IF_ATTR_0 + 1)) << 8);
+ pctrl->vbyone_cfg.region_num =
+ *(p + LCD_UKEY_IF_ATTR_1) |
+ ((*(p + LCD_UKEY_IF_ATTR_1 + 1)) << 8);
+ pctrl->vbyone_cfg.byte_mode =
+ *(p + LCD_UKEY_IF_ATTR_2) |
+ ((*(p + LCD_UKEY_IF_ATTR_2 + 1)) << 8);
+ pctrl->vbyone_cfg.color_fmt =
+ *(p + LCD_UKEY_IF_ATTR_3) |
+ ((*(p + LCD_UKEY_IF_ATTR_3 + 1)) << 8);
+ if (lcd_header.version == 1) {
+ pctrl->vbyone_cfg.phy_vswing =
+ *(p + LCD_UKEY_IF_ATTR_4) |
+ ((*(p + LCD_UKEY_IF_ATTR_4 + 1)) << 8);
+ pctrl->vbyone_cfg.phy_preem =
+ *(p + LCD_UKEY_IF_ATTR_5) |
+ ((*(p + LCD_UKEY_IF_ATTR_5 + 1)) << 8);
+ pctrl->vbyone_cfg.hw_filter_time =
+ *(p + LCD_UKEY_IF_ATTR_8) |
+ ((*(p + LCD_UKEY_IF_ATTR_8 + 1)) << 8);
+ pctrl->vbyone_cfg.hw_filter_cnt =
+ *(p + LCD_UKEY_IF_ATTR_9) |
+ ((*(p + LCD_UKEY_IF_ATTR_9 + 1)) << 8);
+
+ pctrl->vbyone_cfg.ctrl_flag = 0;
+ pctrl->vbyone_cfg.power_on_reset_delay = VX1_PWR_ON_RESET_DLY_DFT;
+ pctrl->vbyone_cfg.hpd_data_delay = VX1_HPD_DATA_DELAY_DFT;
+ pctrl->vbyone_cfg.cdr_training_hold = VX1_CDR_TRAINING_HOLD_DFT;
+ } else {
+ pctrl->vbyone_cfg.ctrl_flag =
+ *(p + LCD_UKEY_CTRL_FLAG) |
+ ((*(p + LCD_UKEY_CTRL_FLAG + 1)) << 8) |
+ ((*(p + LCD_UKEY_CTRL_FLAG + 2)) << 16) |
+ ((*(p + LCD_UKEY_CTRL_FLAG + 3)) << 24);
+ pctrl->vbyone_cfg.power_on_reset_delay =
+ *(p + LCD_UKEY_CTRL_ATTR_0) |
+ ((*(p + LCD_UKEY_CTRL_ATTR_0 + 1)) << 8);
+ pctrl->vbyone_cfg.hpd_data_delay =
+ *(p + LCD_UKEY_CTRL_ATTR_1) |
+ ((*(p + LCD_UKEY_CTRL_ATTR_1 + 1)) << 8);
+ pctrl->vbyone_cfg.cdr_training_hold =
+ *(p + LCD_UKEY_CTRL_ATTR_2) |
+ ((*(p + LCD_UKEY_CTRL_ATTR_2 + 1)) << 8);
+
+ pctrl->vbyone_cfg.phy_vswing = *(p + LCD_UKEY_PHY_ATTR_0);
+ pctrl->vbyone_cfg.phy_preem = *(p + LCD_UKEY_PHY_ATTR_1);
+ }
+ break;
+ case LCD_MLVDS:
+ pctrl->mlvds_cfg.channel_num =
+ *(p + LCD_UKEY_IF_ATTR_0) |
+ ((*(p + LCD_UKEY_IF_ATTR_0 + 1)) << 8);
+ pctrl->mlvds_cfg.channel_sel0 =
+ *(p + LCD_UKEY_IF_ATTR_1) |
+ ((*(p + LCD_UKEY_IF_ATTR_1 + 1)) << 8) |
+ ((*(p + LCD_UKEY_IF_ATTR_2)) << 16) |
+ ((*(p + LCD_UKEY_IF_ATTR_2 + 1)) << 24);
+ pctrl->mlvds_cfg.channel_sel1 =
+ *(p + LCD_UKEY_IF_ATTR_3) |
+ ((*(p + LCD_UKEY_IF_ATTR_3 + 1)) << 8) |
+ ((*(p + LCD_UKEY_IF_ATTR_4)) << 16) |
+ ((*(p + LCD_UKEY_IF_ATTR_4 + 1)) << 24);
+ pctrl->mlvds_cfg.clk_phase =
+ *(p + LCD_UKEY_IF_ATTR_5) |
+ ((*(p + LCD_UKEY_IF_ATTR_5 + 1)) << 8);
+ pctrl->mlvds_cfg.pn_swap =
+ *(p + LCD_UKEY_IF_ATTR_6) |
+ ((*(p + LCD_UKEY_IF_ATTR_6 + 1)) << 8);
+ pctrl->mlvds_cfg.bit_swap =
+ *(p + LCD_UKEY_IF_ATTR_7) |
+ ((*(p + LCD_UKEY_IF_ATTR_7 + 1)) << 8);
+ if (lcd_header.version == 1) {
+ pctrl->mlvds_cfg.phy_vswing =
+ *(p + LCD_UKEY_IF_ATTR_8) |
+ ((*(p + LCD_UKEY_IF_ATTR_8 + 1)) << 8);
+ pctrl->mlvds_cfg.phy_preem =
+ *(p + LCD_UKEY_IF_ATTR_9) |
+ ((*(p + LCD_UKEY_IF_ATTR_9 + 1)) << 8);
+ } else {
+ pctrl->mlvds_cfg.phy_vswing = *(p + LCD_UKEY_PHY_ATTR_0);
+ pctrl->mlvds_cfg.phy_preem = *(p + LCD_UKEY_PHY_ATTR_1);
+ }
+ break;
+ case LCD_P2P:
+ pctrl->p2p_cfg.p2p_type =
+ *(p + LCD_UKEY_IF_ATTR_0) |
+ ((*(p + LCD_UKEY_IF_ATTR_0 + 1)) << 8);
+ pctrl->p2p_cfg.lane_num =
+ *(p + LCD_UKEY_IF_ATTR_1) |
+ ((*(p + LCD_UKEY_IF_ATTR_1 + 1)) << 8);
+ pctrl->p2p_cfg.channel_sel0 =
+ *(p + LCD_UKEY_IF_ATTR_2) |
+ ((*(p + LCD_UKEY_IF_ATTR_2 + 1)) << 8) |
+ (*(p + LCD_UKEY_IF_ATTR_3) << 16) |
+ ((*(p + LCD_UKEY_IF_ATTR_3 + 1)) << 24);
+ pctrl->p2p_cfg.channel_sel1 =
+ *(p + LCD_UKEY_IF_ATTR_4) |
+ ((*(p + LCD_UKEY_IF_ATTR_4 + 1)) << 8) |
+ (*(p + LCD_UKEY_IF_ATTR_5) << 16) |
+ ((*(p + LCD_UKEY_IF_ATTR_5 + 1)) << 24);
+ pctrl->p2p_cfg.pn_swap =
+ *(p + LCD_UKEY_IF_ATTR_6) |
+ ((*(p + LCD_UKEY_IF_ATTR_6 + 1)) << 8);
+ pctrl->p2p_cfg.bit_swap =
+ *(p + LCD_UKEY_IF_ATTR_7) |
+ ((*(p + LCD_UKEY_IF_ATTR_7 + 1)) << 8);
+ pctrl->p2p_cfg.phy_vswing =
+ *(p + LCD_UKEY_IF_ATTR_8) |
+ ((*(p + LCD_UKEY_IF_ATTR_8 + 1)) << 8);
+ pctrl->p2p_cfg.phy_preem =
+ *(p + LCD_UKEY_IF_ATTR_9) |
+ ((*(p + LCD_UKEY_IF_ATTR_9 + 1)) << 8);
+ break;
+ default:
+ LCDERR("[%d]: unsupport lcd_type: %d\n",
+ pdrv->index, pconf->basic.lcd_type);
+ break;
+ }
+
+ /* step 3: check power sequence */
+ ret = lcd_power_load_from_unifykey(pdrv, para, key_len, len);
+ if (ret < 0) {
+ free(para);
+ return -1;
+ }
+#ifdef CONFIG_AML_LCD_BACKLIGHT
+ aml_bl_index_add(pdrv->index, 0);
+#endif
+
+ free(para);
+ return 0;
+}
+
+static int lcd_config_load_from_bsp(struct aml_lcd_drv_s *pdrv)
+{
+ struct ext_lcd_config_s *ext_lcd;
+ struct lcd_config_s *pconf = &pdrv->config;
+ union lcd_ctrl_config_u *pctrl;
+ struct lcd_power_step_s *power_step;
+ char *panel_type, str[15];
+ unsigned int i, done;
+ unsigned int temp;
+
+ LCDPR("config load from bsp\n");
+
+ if (pdrv->index >= LCD_MAX_DRV) {
+ LCDERR("[%d]: invalid drv index %d\n", pdrv->index, pdrv->index);
+ return -1;
+ }
+
+ if (pdrv->index == 0)
+ sprintf(str, "panel_type");
+ else
+ sprintf(str, "panel%d_type", pdrv->index);
+ panel_type = env_get(str);
+ if (!panel_type) {
+ LCDERR("[%d]: no %s exist\n", pdrv->index, str);
+ return -1;
+ }
+
+ if (!pdrv->data->dft_conf[pdrv->index]) {
+ LCDERR("[%d]: %s: dft_conf is NULL\n", pdrv->index, __func__);
+ return -1;
+ }
+ ext_lcd = pdrv->data->dft_conf[pdrv->index]->ext_lcd;
+ if (!ext_lcd) {
+ LCDERR("[%d]: %s: ext_lcd is NULL\n", pdrv->index, __func__);
+ return -1;
+ }
+ done = 0;
+ for (i = 0 ; i < LCD_NUM_MAX ; i++) {
+ if (strcmp(ext_lcd->panel_type, panel_type) == 0) {
+ done = 1;
+ break;
+ }
+ if (strcmp(ext_lcd->panel_type, "invalid") == 0)
+ break;
+ ext_lcd++;
+ }
+ if (done == 0) {
+ LCDERR("[%d]: can't find %s\n ", pdrv->index, panel_type);
+ return -1;
+ }
+ LCDPR("[%d]: use default %s=%s\n", pdrv->index, str, panel_type);
+
+ strncpy(pconf->basic.model_name, panel_type,
+ sizeof(pconf->basic.model_name) - 1);
+ pconf->basic.model_name[sizeof(pconf->basic.model_name) - 1] = '\0';
+
+ pconf->basic.lcd_type = ext_lcd->lcd_type;
+ pconf->basic.lcd_bits = ext_lcd->lcd_bits;
+
+ pconf->basic.h_active = ext_lcd->h_active;
+ pconf->basic.v_active = ext_lcd->v_active;
+ pconf->basic.h_period = ext_lcd->h_period;
+ pconf->basic.v_period = ext_lcd->v_period;
+
+ pconf->basic.h_period_min = pconf->basic.h_period;
+ pconf->basic.h_period_max = pconf->basic.h_period;
+ pconf->basic.v_period_min = pconf->basic.v_period;
+ pconf->basic.v_period_max = pconf->basic.v_period;
+ pconf->basic.lcd_clk_min = 0;
+ pconf->basic.lcd_clk_max = 0;
+
+ pconf->timing.hsync_width = ext_lcd->hsync_width;
+ pconf->timing.hsync_bp = ext_lcd->hsync_bp;
+ pconf->timing.hsync_pol = ext_lcd->hsync_pol;
+ pconf->timing.vsync_width = ext_lcd->vsync_width;
+ pconf->timing.vsync_bp = ext_lcd->vsync_bp;
+ pconf->timing.vsync_pol = ext_lcd->vsync_pol;
+
+ /* fr_adjust_type */
+ temp = ext_lcd->customer_val_0;
+ if (temp == Rsv_val)
+ pconf->timing.fr_adjust_type = 0;
+ else
+ pconf->timing.fr_adjust_type = (unsigned char)temp;
+ /* ss_level */
+ temp = ext_lcd->customer_val_1;
+ if (temp == Rsv_val)
+ pconf->timing.ss_level = 0;
+ else
+ pconf->timing.ss_level = temp;
+ /* clk_auto_generate */
+ temp = ext_lcd->customer_val_2;
+ if (temp == Rsv_val)
+ pconf->timing.clk_auto = 1;
+ else
+ pconf->timing.clk_auto = (unsigned char)temp;
+ /* lcd_clk */
+ temp = ext_lcd->customer_val_3;
+ if (temp == Rsv_val)
+ pconf->timing.lcd_clk = 60;
+ else
+ pconf->timing.lcd_clk = temp;
+
+ pctrl = &pconf->control;
+ switch (pconf->basic.lcd_type) {
+ case LCD_TTL:
+ pctrl->ttl_cfg.clk_pol = ext_lcd->lcd_spc_val0;
+ pctrl->ttl_cfg.sync_valid = (ext_lcd->lcd_spc_val1 << 1) |
+ (ext_lcd->lcd_spc_val2 << 0);
+ pctrl->ttl_cfg.swap_ctrl = (ext_lcd->lcd_spc_val3 << 1) |
+ (ext_lcd->lcd_spc_val4 << 0);
+ break;
+ case LCD_LVDS:
+ pctrl->lvds_cfg.lvds_repack = ext_lcd->lcd_spc_val0;
+ pctrl->lvds_cfg.dual_port = ext_lcd->lcd_spc_val1;
+ pctrl->lvds_cfg.pn_swap = ext_lcd->lcd_spc_val2;
+ pctrl->lvds_cfg.port_swap = ext_lcd->lcd_spc_val3;
+ pctrl->lvds_cfg.lane_reverse = ext_lcd->lcd_spc_val4;
+ pctrl->lvds_cfg.phy_vswing = ext_lcd->lcd_spc_val5;
+ pctrl->lvds_cfg.phy_preem = ext_lcd->lcd_spc_val6;
+ pctrl->lvds_cfg.phy_clk_vswing = ext_lcd->lcd_spc_val7;
+ pctrl->lvds_cfg.phy_clk_preem = ext_lcd->lcd_spc_val8;
+ break;
+ case LCD_VBYONE:
+ pctrl->vbyone_cfg.lane_count = ext_lcd->lcd_spc_val0;
+ pctrl->vbyone_cfg.region_num = ext_lcd->lcd_spc_val1;
+ pctrl->vbyone_cfg.byte_mode = ext_lcd->lcd_spc_val2;
+ pctrl->vbyone_cfg.color_fmt = ext_lcd->lcd_spc_val3;
+ pctrl->vbyone_cfg.phy_vswing = ext_lcd->lcd_spc_val4;
+ pctrl->vbyone_cfg.phy_preem = ext_lcd->lcd_spc_val5;
+ if (ext_lcd->lcd_spc_val8 == Rsv_val ||
+ ext_lcd->lcd_spc_val9 == Rsv_val) {
+ pctrl->vbyone_cfg.hw_filter_time = 0;
+ pctrl->vbyone_cfg.hw_filter_cnt = 0;
+ } else {
+ pctrl->vbyone_cfg.hw_filter_time =
+ ext_lcd->lcd_spc_val8;
+ pctrl->vbyone_cfg.hw_filter_cnt =
+ ext_lcd->lcd_spc_val9;
+ }
+
+ pctrl->vbyone_cfg.ctrl_flag = 0;
+ pctrl->vbyone_cfg.power_on_reset_delay =
+ VX1_PWR_ON_RESET_DLY_DFT;
+ pctrl->vbyone_cfg.hpd_data_delay =
+ VX1_HPD_DATA_DELAY_DFT;
+ pctrl->vbyone_cfg.cdr_training_hold =
+ VX1_CDR_TRAINING_HOLD_DFT;
+ break;
+ case LCD_MLVDS:
+ pctrl->mlvds_cfg.channel_num = ext_lcd->lcd_spc_val0;
+ pctrl->mlvds_cfg.channel_sel0 = ext_lcd->lcd_spc_val1;
+ pctrl->mlvds_cfg.channel_sel1 = ext_lcd->lcd_spc_val2;
+ pctrl->mlvds_cfg.clk_phase = ext_lcd->lcd_spc_val3;
+ pctrl->mlvds_cfg.pn_swap = ext_lcd->lcd_spc_val4;
+ pctrl->mlvds_cfg.bit_swap = ext_lcd->lcd_spc_val5;
+ pctrl->mlvds_cfg.phy_vswing = ext_lcd->lcd_spc_val6;
+ pctrl->mlvds_cfg.phy_preem = ext_lcd->lcd_spc_val7;
+ break;
+ case LCD_P2P:
+ pctrl->p2p_cfg.p2p_type = ext_lcd->lcd_spc_val0;
+ pctrl->p2p_cfg.lane_num = ext_lcd->lcd_spc_val1;
+ pctrl->p2p_cfg.channel_sel0 = ext_lcd->lcd_spc_val2;
+ pctrl->p2p_cfg.channel_sel1 = ext_lcd->lcd_spc_val3;
+ pctrl->p2p_cfg.pn_swap = ext_lcd->lcd_spc_val4;
+ pctrl->p2p_cfg.bit_swap = ext_lcd->lcd_spc_val5;
+ pctrl->p2p_cfg.phy_vswing = ext_lcd->lcd_spc_val6;
+ pctrl->p2p_cfg.phy_preem = ext_lcd->lcd_spc_val7;
+ break;
+ case LCD_MIPI:
+ pctrl->mipi_cfg.lane_num = ext_lcd->lcd_spc_val0;
+ pctrl->mipi_cfg.bit_rate_max = ext_lcd->lcd_spc_val1;
+ pctrl->mipi_cfg.factor_numerator = ext_lcd->lcd_spc_val2;
+ pctrl->mipi_cfg.operation_mode_init = ext_lcd->lcd_spc_val3;
+ pctrl->mipi_cfg.operation_mode_display = ext_lcd->lcd_spc_val4;
+ pctrl->mipi_cfg.video_mode_type = ext_lcd->lcd_spc_val5;
+ pctrl->mipi_cfg.clk_always_hs = ext_lcd->lcd_spc_val6;
+ pctrl->mipi_cfg.phy_switch = ext_lcd->lcd_spc_val7;
+ pctrl->mipi_cfg.factor_denominator = 100;
+
+ pctrl->mipi_cfg.check_en = 0;
+ pctrl->mipi_cfg.check_reg = 0xff;
+ pctrl->mipi_cfg.check_cnt = 0;
+#ifdef CONFIG_AML_LCD_TABLET
+ lcd_mipi_dsi_init_table_check_bsp(&pctrl->mipi_cfg, 1);
+ lcd_mipi_dsi_init_table_check_bsp(&pctrl->mipi_cfg, 0);
+#endif
+
+ if (ext_lcd->lcd_spc_val9 == Rsv_val)
+ pctrl->mipi_cfg.extern_init = 0xff;
+ else
+ pctrl->mipi_cfg.extern_init = ext_lcd->lcd_spc_val9;
+#ifdef CONFIG_AML_LCD_TABLET
+ mipi_dsi_config_init(pconf);
+#endif
+ break;
+ case LCD_EDP:
+ pctrl->edp_cfg.max_lane_count = ext_lcd->lcd_spc_val0;
+ pctrl->edp_cfg.max_link_rate = ext_lcd->lcd_spc_val1;
+ pctrl->edp_cfg.training_mode = ext_lcd->lcd_spc_val2;
+ pctrl->edp_cfg.dpcd_caps_en = ext_lcd->lcd_spc_val3;
+ pctrl->edp_cfg.sync_clk_mode = ext_lcd->lcd_spc_val4;
+ pctrl->edp_cfg.scramb_mode = ext_lcd->lcd_spc_val5;
+ pctrl->edp_cfg.enhanced_framing_en = ext_lcd->lcd_spc_val6;
+ pctrl->edp_cfg.edid_en = ext_lcd->lcd_spc_val7;
+ pctrl->edp_cfg.pn_swap = 0;
+ pctrl->edp_cfg.phy_vswing = ext_lcd->lcd_spc_val8;
+ pctrl->edp_cfg.phy_preem = ext_lcd->lcd_spc_val9;
+
+ pctrl->edp_cfg.lane_count = pctrl->edp_cfg.max_lane_count;
+ pctrl->edp_cfg.link_rate = pctrl->edp_cfg.max_link_rate;
+ break;
+ default:
+ break;
+ }
+
+ i = 0;
+ while (i < LCD_PWR_STEP_MAX) {
+ power_step = &ext_lcd->power_on_step[i];
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("power_on: step %d: type=%d, index=%d, value=%d, delay=%d\n",
+ i, power_step->type, power_step->index,
+ power_step->value, power_step->delay);
+ }
+ pconf->power.power_on_step[i].type = power_step->type;
+ pconf->power.power_on_step[i].index = power_step->index;
+ pconf->power.power_on_step[i].value = power_step->value;
+ pconf->power.power_on_step[i].delay = power_step->delay;
+ if (power_step->type >= LCD_POWER_TYPE_MAX)
+ break;
+ i++;
+ }
+
+ i = 0;
+ while (i < LCD_PWR_STEP_MAX) {
+ power_step = &ext_lcd->power_off_step[i];
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("power_off: step %d: type=%d, index=%d, value=%d, delay=%d\n",
+ i, power_step->type, power_step->index,
+ power_step->value, power_step->delay);
+ }
+ pconf->power.power_off_step[i].type = power_step->type;
+ pconf->power.power_off_step[i].index = power_step->index;
+ pconf->power.power_off_step[i].value = power_step->value;
+ pconf->power.power_off_step[i].delay = power_step->delay;
+ if (power_step->type >= LCD_POWER_TYPE_MAX)
+ break;
+ i++;
+ }
+#ifdef CONFIG_AML_LCD_BACKLIGHT
+ aml_bl_index_add(pdrv->index, 0);
+#endif
+
+ return 0;
+}
+
+int lcd_get_config(char *dt_addr, int load_id, struct aml_lcd_drv_s *pdrv)
+{
+ int ret;
+
+ if (load_id & 0x10)
+ ret = lcd_config_load_from_unifykey(pdrv);
+ else if (load_id & 0x1)
+ ret = lcd_config_load_from_dts(dt_addr, pdrv);
+ else
+ ret = lcd_config_load_from_bsp(pdrv);
+ if (ret)
+ return -1;
+
+ lcd_config_load_print(pdrv);
+ lcd_pinmux_load_config(pdrv);
+
+#ifdef CONFIG_AML_LCD_TCON
+ lcd_tcon_probe(dt_addr, pdrv, load_id);
+#endif
+
+ return 0;
+}
+
+static unsigned int vbyone_lane_num[] = {
+ 1,
+ 2,
+ 4,
+ 8,
+ 8,
+};
+
+#define VBYONE_BIT_RATE_MAX 3100 //MHz
+#define VBYONE_BIT_RATE_MIN 600
+void lcd_vbyone_config_set(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_config_s *pconf = &pdrv->config;
+ unsigned int band_width, bit_rate, pclk, phy_div;
+ unsigned int byte_mode, lane_count, minlane;
+ unsigned int temp, i;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
+
+ //auto calculate bandwidth, clock
+ lane_count = pconf->control.vbyone_cfg.lane_count;
+ byte_mode = pconf->control.vbyone_cfg.byte_mode;
+ /* byte_mode * byte2bit * 8/10_encoding * pclk =
+ byte_mode * 8 * 10 / 8 * pclk */
+ pclk = pconf->timing.lcd_clk / 1000; /* kHz */
+ band_width = byte_mode * 10 * pclk;
+
+ temp = VBYONE_BIT_RATE_MAX * 1000;
+ temp = (band_width + temp - 1) / temp;
+ for (i = 0; i < 4; i++) {
+ if (temp <= vbyone_lane_num[i])
+ break;
+ }
+ minlane = vbyone_lane_num[i];
+ if (lane_count < minlane) {
+ LCDERR("vbyone lane_num(%d) is less than min(%d)\n",
+ lane_count, minlane);
+ lane_count = minlane;
+ pconf->control.vbyone_cfg.lane_count = lane_count;
+ LCDPR("change to min lane_num %d\n", minlane);
+ }
+
+ bit_rate = band_width / lane_count;
+ phy_div = lane_count / lane_count;
+ if (phy_div == 8) {
+ phy_div /= 2;
+ bit_rate /= 2;
+ }
+ if (bit_rate > (VBYONE_BIT_RATE_MAX * 1000)) {
+ LCDERR("vbyone bit rate(%dKHz) is out of max(%dKHz)\n",
+ bit_rate, (VBYONE_BIT_RATE_MAX * 1000));
+ }
+ if (bit_rate < (VBYONE_BIT_RATE_MIN * 1000)) {
+ LCDERR("vbyone bit rate(%dKHz) is out of min(%dKHz)\n",
+ bit_rate, (VBYONE_BIT_RATE_MIN * 1000));
+ }
+ bit_rate = bit_rate * 1000; /* Hz */
+
+ pconf->control.vbyone_cfg.phy_div = phy_div;
+ pconf->timing.bit_rate = bit_rate;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("lane_count=%u, bit_rate = %uMHz, pclk=%u.%03uMhz\n",
+ lane_count, (bit_rate / 1000000),
+ (pclk / 1000), (pclk % 1000));
+ }
+}
+
+void lcd_mlvds_config_set(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_config_s *pconf = &pdrv->config;
+ unsigned int bit_rate, pclk;
+ unsigned int lcd_bits, channel_num;
+ unsigned int channel_sel0, channel_sel1, pi_clk_sel = 0;
+ unsigned int i, temp;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
+
+ lcd_bits = pconf->basic.lcd_bits;
+ channel_num = pconf->control.mlvds_cfg.channel_num;
+ pclk = pconf->timing.lcd_clk / 1000;
+ bit_rate = lcd_bits * 3 * pclk / channel_num;
+
+ pconf->timing.bit_rate = bit_rate * 1000;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("channel_num=%u, bit_rate=%u.%03uMHz, pclk=%u.%03uMhz\n",
+ channel_num, (bit_rate / 1000), (bit_rate % 1000),
+ (pclk / 1000), (pclk % 1000));
+ }
+
+ /* pi_clk select */
+ channel_sel0 = pconf->control.mlvds_cfg.channel_sel0;
+ channel_sel1 = pconf->control.mlvds_cfg.channel_sel1;
+ /* mlvds channel: //tx 12 channels
+ * 0: clk_a
+ * 1: d0_a
+ * 2: d1_a
+ * 3: d2_a
+ * 4: d3_a
+ * 5: d4_a
+ * 6: clk_b
+ * 7: d0_b
+ * 8: d1_b
+ * 9: d2_b
+ * 10: d3_b
+ * 11: d4_b
+ */
+ for (i = 0; i < 8; i++) {
+ temp = (channel_sel0 >> (i * 4)) & 0xf;
+ if (temp == 0 || temp == 6)
+ pi_clk_sel |= (1 << i);
+ }
+ for (i = 0; i < 4; i++) {
+ temp = (channel_sel1 >> (i * 4)) & 0xf;
+ if (temp == 0 || temp == 6)
+ pi_clk_sel |= (1 << (i + 8));
+ }
+
+ pconf->control.mlvds_cfg.pi_clk_sel = pi_clk_sel;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("channel_sel0=0x%08x, channel_sel1=0x%08x, pi_clk_sel=0x%03x\n",
+ channel_sel0, channel_sel1, pi_clk_sel);
+ }
+}
+
+void lcd_p2p_config_set(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_config_s *pconf = &pdrv->config;
+ unsigned int bit_rate, pclk;
+ unsigned int lcd_bits, lane_num;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
+
+ lcd_bits = pconf->basic.lcd_bits;
+ lane_num = pconf->control.p2p_cfg.lane_num;
+ pclk = pconf->timing.lcd_clk / 1000;
+ switch (pconf->control.p2p_cfg.p2p_type) {
+ case P2P_CEDS:
+ if (pclk >= 600000)
+ bit_rate = pclk * 3 * lcd_bits / lane_num;
+ else
+ bit_rate = pclk * (3 * lcd_bits + 4) / lane_num;
+ break;
+ case P2P_CHPI: /* 8/10 coding */
+ bit_rate = (pclk * 3 * lcd_bits * 10 / 8) / lane_num;
+ break;
+ default:
+ bit_rate = pclk * 3 * lcd_bits / lane_num;
+ break;
+ }
+
+ pconf->timing.bit_rate = bit_rate * 1000;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("lane_num=%u, bit_rate=%u.%03uMHz, pclk=%u.%03uMhz\n",
+ lane_num, (bit_rate / 1000), (bit_rate % 1000),
+ (pclk / 1000), (pclk % 1000));
+ }
+}
+
+void lcd_mipi_dsi_config_set(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_config_s *pconf = &pdrv->config;
+ unsigned int pclk, bit_rate;
+ unsigned int bit_rate_max, bit_rate_min, pll_out_fmin = 0;
+ struct dsi_config_s *dconf = &pconf->control.mipi_cfg;
+ struct lcd_clk_config_s *cconf;
+ unsigned int temp, n;
+
+ dconf = &pconf->control.mipi_cfg;
+
+ /* unit in kHz for calculation */
+ cconf = get_lcd_clk_config(pdrv);
+ if (cconf && cconf->data)
+ pll_out_fmin = cconf->data->pll_out_fmin;
+ pclk = pconf->timing.lcd_clk / 1000;
+
+ /* bit rate max */
+ if (dconf->bit_rate_max == 0) { /* auto calculate */
+ if ((dconf->operation_mode_display == OPERATION_VIDEO_MODE) &&
+ (dconf->video_mode_type != BURST_MODE)) {
+ temp = pclk * 4 * dconf->data_bits;
+ bit_rate = temp / dconf->lane_num;
+ } else {
+ temp = pclk * 3 * dconf->data_bits;
+ bit_rate = temp / dconf->lane_num;
+ }
+ n = 0;
+ bit_rate_min = 0;
+ bit_rate_max = 0;
+ while ((bit_rate_min < pll_out_fmin) && (n < 100)) {
+ bit_rate_max = bit_rate + (pclk / 2) + (n * pclk);
+ bit_rate_min = bit_rate_max - pclk;
+ n++;
+ }
+ dconf->bit_rate_max = bit_rate_max / 1000; /* unit: MHz*/
+ if (dconf->bit_rate_max > MIPI_BIT_RATE_MAX)
+ dconf->bit_rate_max = MIPI_BIT_RATE_MAX;
+
+ LCDPR("mipi dsi bit_rate max=%dMHz\n", dconf->bit_rate_max);
+ } else { /* user define */
+ if (dconf->bit_rate_max < pll_out_fmin / 1000) {
+ LCDERR("invalid mipi-dsi bit_rate %dMHz (min=%dMHz)\n",
+ dconf->bit_rate_max, (pll_out_fmin / 1000));
+ }
+ if (dconf->bit_rate_max > MIPI_BIT_RATE_MAX) {
+ LCDPR("[warning]: invalid mipi-dsi bit_rate_max %dMHz (max=%dMHz)\n",
+ dconf->bit_rate_max, MIPI_BIT_RATE_MAX);
+ }
+ }
+}
+
+void lcd_edp_config_set(struct aml_lcd_drv_s *pdrv)
+{
+ //todo
+}
+
void lcd_timing_init_config(struct lcd_config_s *pconf)
{
unsigned short h_period, v_period, h_active, v_active;
@@ -740,7 +1868,7 @@
unsigned short hstart, hend, vstart, vend;
unsigned short h_delay;
- switch (pconf->lcd_basic.lcd_type) {
+ switch (pconf->basic.lcd_type) {
case LCD_TTL:
h_delay = TTL_DELAY;
break;
@@ -748,171 +1876,149 @@
h_delay = 0;
break;
}
- h_period = pconf->lcd_basic.h_period;
- v_period = pconf->lcd_basic.v_period;
- h_active = pconf->lcd_basic.h_active;
- v_active = pconf->lcd_basic.v_active;
- hsync_bp = pconf->lcd_timing.hsync_bp;
- hsync_width = pconf->lcd_timing.hsync_width;
- vsync_bp = pconf->lcd_timing.vsync_bp;
- vsync_width = pconf->lcd_timing.vsync_width;
+ h_period = pconf->basic.h_period;
+ v_period = pconf->basic.v_period;
+ h_active = pconf->basic.h_active;
+ v_active = pconf->basic.v_active;
+ hsync_bp = pconf->timing.hsync_bp;
+ hsync_width = pconf->timing.hsync_width;
+ vsync_bp = pconf->timing.vsync_bp;
+ vsync_width = pconf->timing.vsync_width;
- de_hstart = h_period - h_active - 1;
- de_vstart = v_period - v_active;
+ de_hstart = hsync_bp + hsync_width;
+ de_vstart = vsync_bp + vsync_width;
- pconf->lcd_timing.video_on_pixel = de_hstart - h_delay;
- pconf->lcd_timing.video_on_line = de_vstart;
+ pconf->timing.video_on_pixel = de_hstart - h_delay;
+ pconf->timing.video_on_line = de_vstart;
- pconf->lcd_timing.de_hs_addr = de_hstart;
- pconf->lcd_timing.de_he_addr = de_hstart + h_active;
- pconf->lcd_timing.de_vs_addr = de_vstart;
- pconf->lcd_timing.de_ve_addr = de_vstart + v_active - 1;
+ pconf->timing.de_hs_addr = de_hstart;
+ pconf->timing.de_he_addr = de_hstart + h_active;
+ pconf->timing.de_vs_addr = de_vstart;
+ pconf->timing.de_ve_addr = de_vstart + v_active - 1;
hstart = (de_hstart + h_period - hsync_bp - hsync_width) % h_period;
hend = (de_hstart + h_period - hsync_bp) % h_period;
- pconf->lcd_timing.hs_hs_addr = hstart;
- pconf->lcd_timing.hs_he_addr = hend;
- pconf->lcd_timing.hs_vs_addr = 0;
- pconf->lcd_timing.hs_ve_addr = v_period - 1;
+ pconf->timing.hs_hs_addr = hstart;
+ pconf->timing.hs_he_addr = hend;
+ pconf->timing.hs_vs_addr = 0;
+ pconf->timing.hs_ve_addr = v_period - 1;
- pconf->lcd_timing.vs_hs_addr = (hstart + h_period) % h_period;
- pconf->lcd_timing.vs_he_addr = pconf->lcd_timing.vs_hs_addr;
+ pconf->timing.vs_hs_addr = (hstart + h_period) % h_period;
+ pconf->timing.vs_he_addr = pconf->timing.vs_hs_addr;
vstart = (de_vstart + v_period - vsync_bp - vsync_width) % v_period;
vend = (de_vstart + v_period - vsync_bp) % v_period;
- pconf->lcd_timing.vs_vs_addr = vstart;
- pconf->lcd_timing.vs_ve_addr = vend;
+ pconf->timing.vs_vs_addr = vstart;
+ pconf->timing.vs_ve_addr = vend;
- if (lcd_debug_print_flag) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
LCDPR("hs_hs_addr=%d, hs_he_addr=%d, hs_vs_addr=%d, hs_ve_addr=%d\n",
- pconf->lcd_timing.hs_hs_addr, pconf->lcd_timing.hs_he_addr,
- pconf->lcd_timing.hs_vs_addr, pconf->lcd_timing.hs_ve_addr);
+ pconf->timing.hs_hs_addr, pconf->timing.hs_he_addr,
+ pconf->timing.hs_vs_addr, pconf->timing.hs_ve_addr);
LCDPR("vs_hs_addr=%d, vs_he_addr=%d, vs_vs_addr=%d, vs_ve_addr=%d\n",
- pconf->lcd_timing.vs_hs_addr, pconf->lcd_timing.vs_he_addr,
- pconf->lcd_timing.vs_vs_addr, pconf->lcd_timing.vs_ve_addr);
+ pconf->timing.vs_hs_addr, pconf->timing.vs_he_addr,
+ pconf->timing.vs_vs_addr, pconf->timing.vs_ve_addr);
}
}
int lcd_vmode_change(struct lcd_config_s *pconf)
{
- unsigned char type = pconf->lcd_timing.fr_adjust_type;
+ unsigned char type = pconf->timing.fr_adjust_type;
/* use default value to avoid offset */
- unsigned int pclk = pconf->lcd_timing.lcd_clk_dft;
- unsigned int h_period = pconf->lcd_timing.h_period_dft;
- unsigned int v_period = pconf->lcd_timing.v_period_dft;
- unsigned int pclk_min = pconf->lcd_basic.lcd_clk_min;
- unsigned int pclk_max = pconf->lcd_basic.lcd_clk_max;
- unsigned int duration_num = pconf->lcd_timing.sync_duration_num;
- unsigned int duration_den = pconf->lcd_timing.sync_duration_den;
+ unsigned int pclk = pconf->timing.lcd_clk_dft;
+ unsigned int h_period = pconf->timing.h_period_dft;
+ unsigned int v_period = pconf->timing.v_period_dft;
+ unsigned int pclk_min = pconf->basic.lcd_clk_min;
+ unsigned int pclk_max = pconf->basic.lcd_clk_max;
+ unsigned int duration_num = pconf->timing.sync_duration_num;
+ unsigned int duration_den = pconf->timing.sync_duration_den;
char str[100];
int len = 0;
- pconf->lcd_timing.clk_change = 0; /* clear clk flag */
+ pconf->timing.clk_change = 0; /* clear clk flag */
switch (type) {
case 0: /* pixel clk adjust */
pclk = (h_period * v_period) / duration_den * duration_num;
- if (pconf->lcd_timing.lcd_clk != pclk)
- pconf->lcd_timing.clk_change = LCD_CLK_PLL_CHANGE;
+ if (pconf->timing.lcd_clk != pclk)
+ pconf->timing.clk_change = LCD_CLK_PLL_CHANGE;
break;
case 1: /* htotal adjust */
- h_period = ((pclk / v_period) * duration_den * 100) /
- duration_num;
+ h_period = ((pclk / v_period) * duration_den * 100) / duration_num;
h_period = (h_period + 99) / 100; /* round off */
- if (pconf->lcd_basic.h_period != h_period) {
+ if (pconf->basic.h_period != h_period) {
/* check clk frac update */
- pclk = (h_period * v_period) / duration_den *
- duration_num;
- if (pconf->lcd_timing.lcd_clk != pclk) {
- pconf->lcd_timing.clk_change =
- LCD_CLK_FRAC_UPDATE;
- }
+ pclk = (h_period * v_period) / duration_den * duration_num;
+ if (pconf->timing.lcd_clk != pclk)
+ pconf->timing.clk_change = LCD_CLK_FRAC_UPDATE;
}
break;
case 2: /* vtotal adjust */
- v_period = ((pclk / h_period) * duration_den * 100) /
- duration_num;
+ v_period = ((pclk / h_period) * duration_den * 100) / duration_num;
v_period = (v_period + 99) / 100; /* round off */
- if (pconf->lcd_basic.v_period != v_period) {
+ if (pconf->basic.v_period != v_period) {
/* check clk frac update */
- pclk = (h_period * v_period) / duration_den *
- duration_num;
- if (pconf->lcd_timing.lcd_clk != pclk) {
- pconf->lcd_timing.clk_change =
- LCD_CLK_FRAC_UPDATE;
- }
+ pclk = (h_period * v_period) / duration_den * duration_num;
+ if (pconf->timing.lcd_clk != pclk)
+ pconf->timing.clk_change = LCD_CLK_FRAC_UPDATE;
}
break;
case 3: /* free adjust, use min/max range to calculate */
- v_period = ((pclk / h_period) * duration_den * 100) /
- duration_num;
+ v_period = ((pclk / h_period) * duration_den * 100) / duration_num;
v_period = (v_period + 99) / 100; /* round off */
- if (v_period > pconf->lcd_basic.v_period_max) {
- v_period = pconf->lcd_basic.v_period_max;
- h_period = ((pclk / v_period) * duration_den * 100) /
- duration_num;
+ if (v_period > pconf->basic.v_period_max) {
+ v_period = pconf->basic.v_period_max;
+ h_period = ((pclk / v_period) * duration_den * 100) / duration_num;
h_period = (h_period + 99) / 100; /* round off */
- if (h_period > pconf->lcd_basic.h_period_max) {
- h_period = pconf->lcd_basic.h_period_max;
- pclk = (h_period * v_period) / duration_den *
- duration_num;
- if (pconf->lcd_timing.lcd_clk != pclk) {
+ if (h_period > pconf->basic.h_period_max) {
+ h_period = pconf->basic.h_period_max;
+ pclk = (h_period * v_period) / duration_den * duration_num;
+ if (pconf->timing.lcd_clk != pclk) {
if (pclk > pclk_max) {
pclk = pclk_max;
LCDERR("invalid vmode\n");
return -1;
}
- pconf->lcd_timing.clk_change =
- LCD_CLK_PLL_CHANGE;
+ pconf->timing.clk_change = LCD_CLK_PLL_CHANGE;
}
}
- } else if (v_period < pconf->lcd_basic.v_period_min) {
- v_period = pconf->lcd_basic.v_period_min;
- h_period = ((pclk / v_period) * duration_den * 100) /
- duration_num;
+ } else if (v_period < pconf->basic.v_period_min) {
+ v_period = pconf->basic.v_period_min;
+ h_period = ((pclk / v_period) * duration_den * 100) / duration_num;
h_period = (h_period + 99) / 100; /* round off */
- if (h_period < pconf->lcd_basic.h_period_min) {
- h_period = pconf->lcd_basic.h_period_min;
- pclk = (h_period * v_period) / duration_den *
- duration_num;
- if (pconf->lcd_timing.lcd_clk != pclk) {
+ if (h_period < pconf->basic.h_period_min) {
+ h_period = pconf->basic.h_period_min;
+ pclk = (h_period * v_period) / duration_den * duration_num;
+ if (pconf->timing.lcd_clk != pclk) {
if (pclk < pclk_min) {
pclk = pclk_min;
LCDERR("invalid vmode\n");
return -1;
}
- pconf->lcd_timing.clk_change =
- LCD_CLK_PLL_CHANGE;
+ pconf->timing.clk_change = LCD_CLK_PLL_CHANGE;
}
}
}
/* check clk frac update */
- if ((pconf->lcd_timing.clk_change & LCD_CLK_PLL_CHANGE) == 0) {
- pclk = (h_period * v_period) / duration_den *
- duration_num;
- if (pconf->lcd_timing.lcd_clk != pclk) {
- pconf->lcd_timing.clk_change =
- LCD_CLK_FRAC_UPDATE;
- }
+ if ((pconf->timing.clk_change & LCD_CLK_PLL_CHANGE) == 0) {
+ pclk = (h_period * v_period) / duration_den * duration_num;
+ if (pconf->timing.lcd_clk != pclk)
+ pconf->timing.clk_change = LCD_CLK_FRAC_UPDATE;
}
break;
case 4: /* hdmi mode */
if ((duration_num / duration_den) == 59) {
/* pixel clk adjust */
pclk = (h_period * v_period) / duration_den * duration_num;
- if (pconf->lcd_timing.lcd_clk != pclk)
- pconf->lcd_timing.clk_change = LCD_CLK_PLL_CHANGE;
+ if (pconf->timing.lcd_clk != pclk)
+ pconf->timing.clk_change = LCD_CLK_PLL_CHANGE;
} else {
/* htotal adjust */
- h_period = ((pclk / v_period) * duration_den * 100) /
- duration_num;
+ h_period = ((pclk / v_period) * duration_den * 100) / duration_num;
h_period = (h_period + 99) / 100; /* round off */
- if (pconf->lcd_basic.h_period != h_period) {
+ if (pconf->basic.h_period != h_period) {
/* check clk frac update */
- pclk = (h_period * v_period) / duration_den *
- duration_num;
- if (pconf->lcd_timing.lcd_clk != pclk) {
- pconf->lcd_timing.clk_change =
- LCD_CLK_FRAC_UPDATE;
- }
+ pclk = (h_period * v_period) / duration_den * duration_num;
+ if (pconf->timing.lcd_clk != pclk)
+ pconf->timing.clk_change = LCD_CLK_FRAC_UPDATE;
}
}
break;
@@ -921,30 +2027,30 @@
return 0;
}
- if (pconf->lcd_basic.v_period != v_period) {
+ if (pconf->basic.v_period != v_period) {
len += sprintf(str+len, "v_period %u->%u",
- pconf->lcd_basic.v_period, v_period);
+ pconf->basic.v_period, v_period);
/* update v_period */
- pconf->lcd_basic.v_period = v_period;
+ pconf->basic.v_period = v_period;
}
- if (pconf->lcd_basic.h_period != h_period) {
+ if (pconf->basic.h_period != h_period) {
if (len > 0)
len += sprintf(str+len, ", ");
len += sprintf(str+len, "h_period %u->%u",
- pconf->lcd_basic.h_period, h_period);
+ pconf->basic.h_period, h_period);
/* update h_period */
- pconf->lcd_basic.h_period = h_period;
+ pconf->basic.h_period = h_period;
}
- if (pconf->lcd_timing.lcd_clk != pclk) {
+ if (pconf->timing.lcd_clk != pclk) {
if (len > 0)
len += sprintf(str+len, ", ");
len += sprintf(str+len, "pclk %u.%03uMHz->%u.%03uMHz",
- (pconf->lcd_timing.lcd_clk / 1000000),
- ((pconf->lcd_timing.lcd_clk / 1000) % 1000),
+ (pconf->timing.lcd_clk / 1000000),
+ ((pconf->timing.lcd_clk / 1000) % 1000),
(pclk / 1000000), ((pclk / 1000) % 1000));
- pconf->lcd_timing.lcd_clk = pclk;
+ pconf->timing.lcd_clk = pclk;
}
- if (lcd_debug_print_flag) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
if (len > 0)
LCDPR("%s: %s\n", __func__, str);
}
@@ -952,3 +2058,56 @@
return 0;
}
+void lcd_pinmux_set(struct aml_lcd_drv_s *pdrv, int status)
+{
+ struct lcd_config_s *pconf;
+ int i;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s: %d\n", pdrv->index, __func__, status);
+
+ pconf = &pdrv->config;
+ if (status) {
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (pconf->pinmux_clr[i][0] == LCD_PINMUX_END)
+ break;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("pinmux_clr: %d, 0x%08x\n",
+ pconf->pinmux_clr[i][0],
+ pconf->pinmux_clr[i][1]);
+ }
+ lcd_pinmux_clr_mask(pconf->pinmux_clr[i][0],
+ pconf->pinmux_clr[i][1]);
+ i++;
+ }
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (pconf->pinmux_set[i][0] == LCD_PINMUX_END)
+ break;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("pinmux_set: %d, 0x%08x\n",
+ pconf->pinmux_set[i][0],
+ pconf->pinmux_set[i][1]);
+ }
+ lcd_pinmux_set_mask(pconf->pinmux_set[i][0],
+ pconf->pinmux_set[i][1]);
+ i++;
+ }
+ } else {
+ i = 0;
+ while (i < LCD_PINMUX_NUM) {
+ if (pconf->pinmux_set[i][0] == LCD_PINMUX_END)
+ break;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("pinmux_clr: %d, 0x%08x\n",
+ pconf->pinmux_set[i][0],
+ pconf->pinmux_set[i][1]);
+ }
+ lcd_pinmux_clr_mask(pconf->pinmux_set[i][0],
+ pconf->pinmux_set[i][1]);
+ i++;
+ }
+ }
+}
+
diff --git a/drivers/amlogic/media/vout/lcd/lcd_common.h b/drivers/amlogic/media/vout/lcd/lcd_common.h
index 2f828da..cbf2a27 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_common.h
+++ b/drivers/amlogic/media/vout/lcd/lcd_common.h
@@ -1,21 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * driver/amlogic/media/vout/lcd/lcd_common.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef _AML_LCD_COMMON_H
@@ -25,117 +10,101 @@
#include "lcd_unifykey.h"
/* 20181106: init version */
-#define LCD_DRV_VERSION "20181106"
+/* 20201211: support t5/t5d/t7 */
+/* 20210222: support multi driver index */
+#define LCD_DRV_VERSION "20210222"
-#define VPP_OUT_SATURATE (1 << 0)
+extern unsigned int lcd_debug_test;
+extern unsigned long clk_util_clk_msr(unsigned long clk_mux);
-/* -------------------------- */
-/* lvsd phy parameters define */
-/* -------------------------- */
-#define LVDS_PHY_CNTL1_G9TV 0x606cca80
-#define LVDS_PHY_CNTL2_G9TV 0x0000006c
-#define LVDS_PHY_CNTL3_G9TV 0x00000800
+void mdelay(unsigned long n);
-#define LVDS_PHY_CNTL1_TXHD 0x6c60ca80
-#define LVDS_PHY_CNTL2_TXHD 0x00000070
-#define LVDS_PHY_CNTL3_TXHD 0x03ff0c00
-/* -------------------------- */
-
-/* -------------------------- */
-/* vbyone phy parameters define */
-/* -------------------------- */
-#define VX1_PHY_CNTL1_G9TV 0x6e0ec900
-#define VX1_PHY_CNTL1_G9TV_PULLUP 0x6e0f4d00
-#define VX1_PHY_CNTL2_G9TV 0x0000007c
-#define VX1_PHY_CNTL3_G9TV 0x00ff0800
-/* -------------------------- */
-
-/* -------------------------- */
-/* minilvds phy parameters define */
-/* -------------------------- */
-#define MLVDS_PHY_CNTL1_TXHD 0x6c60ca80
-#define MLVDS_PHY_CNTL2_TXHD 0x00000070
-#define MLVDS_PHY_CNTL3_TXHD 0x03ff0c00
-/* -------------------------- */
-
-/* ******** MIPI_DSI_PHY ******** */
-/* bit[15:11] */
-#define MIPI_PHY_LANE_BIT 11
-#define MIPI_PHY_LANE_WIDTH 5
-
-/* MIPI-DSI */
-#define DSI_LANE_0 (1 << 4)
-#define DSI_LANE_1 (1 << 3)
-#define DSI_LANE_CLK (1 << 2)
-#define DSI_LANE_2 (1 << 1)
-#define DSI_LANE_3 (1 << 0)
-#define DSI_LANE_COUNT_1 (DSI_LANE_CLK | DSI_LANE_0)
-#define DSI_LANE_COUNT_2 (DSI_LANE_CLK | DSI_LANE_0 | DSI_LANE_1)
-#define DSI_LANE_COUNT_3 (DSI_LANE_CLK | DSI_LANE_0 |\
- DSI_LANE_1 | DSI_LANE_2)
-#define DSI_LANE_COUNT_4 (DSI_LANE_CLK | DSI_LANE_0 |\
- DSI_LANE_1 | DSI_LANE_2 | DSI_LANE_3)
-/* -------------------------- */
-
-extern void mdelay(unsigned long n);
-extern unsigned int lcd_debug_load_flag;
+void lcd_display_init_test(struct aml_lcd_drv_s *pdrv);
+void lcd_display_init_reg_dump(struct aml_lcd_drv_s *pdrv);
/* lcd common */
-extern int lcd_type_str_to_type(const char *str);
-extern char *lcd_type_type_to_str(int type);
-extern int lcd_mode_str_to_mode(const char *str);
-extern char *lcd_mode_mode_to_str(int mode);
+int lcd_type_str_to_type(const char *str);
+char *lcd_type_type_to_str(int type);
+int lcd_mode_str_to_mode(const char *str);
+char *lcd_mode_mode_to_str(int mode);
-extern void lcd_pinmux_set(int status);
+int lcd_get_config(char *dt_addr, int load_id, struct aml_lcd_drv_s *pdrv);
+void lcd_timing_init_config(struct lcd_config_s *pconf);
+int lcd_vmode_change(struct lcd_config_s *pconf);
+void lcd_pinmux_set(struct aml_lcd_drv_s *pdrv, int status);
+void lcd_vbyone_config_set(struct aml_lcd_drv_s *pdrv);
+void lcd_mipi_dsi_config_set(struct aml_lcd_drv_s *pdrv);
+void lcd_edp_config_set(struct aml_lcd_drv_s *pdrv);
-extern unsigned int lcd_lvds_channel_on_value(struct lcd_config_s *pconf);
-extern int lcd_power_load_from_dts(struct lcd_config_s *pconf,
- const void *dt_blob, int child_offset);
-extern int lcd_power_load_from_unifykey(struct lcd_config_s *pconf,
- unsigned char *buf, int key_len, int len);
-extern int lcd_pinmux_load_config(const void *dt_blob, struct lcd_config_s *pconf);
-extern void lcd_timing_init_config(struct lcd_config_s *pconf);
-extern int lcd_vmode_change(struct lcd_config_s *pconf);
+void lcd_set_venc(struct aml_lcd_drv_s *pdrv);
+
+/* lcd phy */
+void lcd_phy_tcon_chpi_bbc_init_tl1(struct lcd_config_s *pconf);
+void lcd_phy_set(struct aml_lcd_drv_s *pdrv, int status);
+int lcd_phy_probe(struct aml_lcd_drv_s *pdrv);
+int lcd_phy_config_init(struct aml_lcd_data_s *pdata);
+
+/*lcd vbyone*/
+void lcd_vbyone_sw_reset(struct aml_lcd_drv_s *pdrv);
+void lcd_vbyone_wait_timing_stable(struct aml_lcd_drv_s *pdrv);
+void lcd_vbyone_cdr_training_hold(struct aml_lcd_drv_s *pdrv, int flag);
+void lcd_vbyone_wait_hpd(struct aml_lcd_drv_s *pdrv);
+void lcd_vbyone_wait_stable(struct aml_lcd_drv_s *pdrv);
+void lcd_vbyone_hw_filter(struct aml_lcd_drv_s *pdrv, int flag);
/* lcd tcon */
-extern void lcd_tcon_reg_table_print(void);
-extern void lcd_tcon_reg_readback_print(void);
-extern void lcd_tcon_info_print(void);
-extern int lcd_tcon_enable(struct lcd_config_s *pconf);
-extern void lcd_tcon_disable(void);
-extern int lcd_tcon_probe(const void *dt_blob, struct aml_lcd_drv_s *lcd_drv, int load_id);
+#ifdef CONFIG_AML_LCD_TCON
+void lcd_tcon_info_print(void);
+int lcd_tcon_enable(struct aml_lcd_drv_s *pdrv);
+void lcd_tcon_disable(struct aml_lcd_drv_s *pdrv);
+int lcd_tcon_probe(char *dt_addr, struct aml_lcd_drv_s *pdrv, int load_id);
+#endif
/* lcd gpio */
-extern void lcd_cpu_gpio_info_print(void);
-extern int lcd_gpio_probe(const char *name, int index);
-extern int lcd_gpio_set(int gpio, int value);
-extern unsigned int lcd_gpio_input_get(int gpio);
+int lcd_gpio_name_map_num(const char *name);
+int lcd_gpio_set(int gpio, int value);
+unsigned int lcd_gpio_input_get(int gpio);
/* lcd debug */
-extern void lcd_debug_test(unsigned int num);
-extern void lcd_mute_setting(unsigned char flag);
-extern void lcd_info_print(void);
-extern void lcd_reg_print(void);
-extern void lcd_debug_probe(struct aml_lcd_drv_s *lcd_drv);
+void aml_lcd_debug_test(struct aml_lcd_drv_s *pdrv, unsigned int num);
+void lcd_mute_setting(struct aml_lcd_drv_s *pdrv, unsigned char flag);
+void lcd_info_print(struct aml_lcd_drv_s *pdrv);
+void lcd_reg_print(struct aml_lcd_drv_s *pdrv);
+void lcd_vbyone_rst(struct aml_lcd_drv_s *pdrv);
+void lcd_vbyone_cdr(struct aml_lcd_drv_s *pdrv);
+void lcd_debug_probe(struct aml_lcd_drv_s *pdrv);
+int lcd_prbs_test(struct aml_lcd_drv_s *pdrv, unsigned int s, unsigned int mode_flag);
/* lcd driver */
-extern int get_lcd_tv_config(const void *dt_blob, int load_id);
-extern int get_lcd_tablet_config(const void *dt_blob, int load_id);
-
-extern void lcd_wait_vsync(void);
+#ifdef CONFIG_AML_LCD_TV
+int lcd_mode_tv_init(struct aml_lcd_drv_s *pdrv);
+#endif
+#ifdef CONFIG_AML_LCD_TABLET
+int lcd_mode_tablet_init(struct aml_lcd_drv_s *pdrv);
+int lcd_mipi_dsi_init_table_detect(char *dt_addr, int child_offset,
+ struct dsi_config_s *dconf, int flag);
+int lcd_mipi_dsi_init_table_check_bsp(struct dsi_config_s *dconf, int flag);
+void mipi_dsi_print_info(struct lcd_config_s *pconf);
+void mipi_dsi_config_init(struct lcd_config_s *pconf);
+void mipi_dsi_link_off(struct aml_lcd_drv_s *pdrv);
+void mipi_dsi_tx_ctrl(struct aml_lcd_drv_s *pdrv, int flag);
+void dptx_dpcd_dump(struct aml_lcd_drv_s *pdrv);
+void edp_tx_ctrl(struct aml_lcd_drv_s *pdrv, int flag);
+#endif
+void lcd_wait_vsync(struct aml_lcd_drv_s *pdrv);
/* aml_bl driver */
-extern void bl_config_print(void);
-extern void bl_pwm_config_update(struct bl_config_s *bconf);
-extern void bl_set_level(unsigned int level);
-extern unsigned int bl_get_level(void);
-extern void bl_power_ctrl(int status);
-extern int bl_config_load(const void *dt_blob, int load_id);
-#ifdef CONFIG_AML_LOCAL_DIMMING
-extern int ldim_config_load_from_dts(const void *dt_blob, int child_offset);
-extern int ldim_config_load_from_unifykey(unsigned char *para);
-extern int ldim_config_load(const void *dt_blob);
-#endif
+int aml_bl_probe(char *dtaddr, int load_id);
+int aml_bl_remove(void);
+int aml_bl_index_add(int drv_index, int conf_index);
+int aml_bl_index_remove(int drv_index);
+int aml_bl_init(void);
+void aml_bl_driver_enable(int index);
+void aml_bl_driver_disable(int index);
+void aml_bl_set_level(int index, unsigned int level);
+unsigned int aml_bl_get_level(int index);
+void aml_bl_config_print(int index);
+int aml_bl_pwm_reg_config_init(struct aml_lcd_data_s *pdata);
#endif
diff --git a/drivers/amlogic/media/vout/lcd/lcd_debug.c b/drivers/amlogic/media/vout/lcd/lcd_debug.c
index 15972bf..9830ff9 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_debug.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_debug.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_debug.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -28,26 +13,23 @@
#endif
#include "lcd_debug.h"
-static struct lcd_debug_info_reg_s *lcd_debug_info_reg;
-static struct lcd_debug_info_if_s *lcd_debug_info_if;
-
static void lcd_timing_info_print(struct lcd_config_s * pconf)
{
unsigned int hs_width, hs_bp, hs_pol, h_period;
unsigned int vs_width, vs_bp, vs_pol, v_period;
unsigned int video_on_pixel, video_on_line;
- video_on_pixel = pconf->lcd_timing.video_on_pixel;
- video_on_line = pconf->lcd_timing.video_on_line;
- h_period = pconf->lcd_basic.h_period;
- v_period = pconf->lcd_basic.v_period;
+ video_on_pixel = pconf->timing.video_on_pixel;
+ video_on_line = pconf->timing.video_on_line;
+ h_period = pconf->basic.h_period;
+ v_period = pconf->basic.v_period;
- hs_width = pconf->lcd_timing.hsync_width;
- hs_bp = pconf->lcd_timing.hsync_bp;
- hs_pol = pconf->lcd_timing.hsync_pol;
- vs_width = pconf->lcd_timing.vsync_width;
- vs_bp = pconf->lcd_timing.vsync_bp;
- vs_pol = pconf->lcd_timing.vsync_pol;
+ hs_width = pconf->timing.hsync_width;
+ hs_bp = pconf->timing.hsync_bp;
+ hs_pol = pconf->timing.hsync_pol;
+ vs_width = pconf->timing.vsync_width;
+ vs_bp = pconf->timing.vsync_bp;
+ vs_pol = pconf->timing.vsync_pol;
printf("h_period %d\n"
"v_period %d\n"
@@ -68,28 +50,43 @@
"v_period_max %d\n"
"pclk_min %d\n"
"pclk_max %d\n\n",
- pconf->lcd_basic.h_period_min, pconf->lcd_basic.h_period_max,
- pconf->lcd_basic.v_period_min, pconf->lcd_basic.v_period_max,
- pconf->lcd_basic.lcd_clk_min, pconf->lcd_basic.lcd_clk_max);
+ pconf->basic.h_period_min, pconf->basic.h_period_max,
+ pconf->basic.v_period_min, pconf->basic.v_period_max,
+ pconf->basic.lcd_clk_min, pconf->basic.lcd_clk_max);
}
-static void lcd_power_info_print(struct aml_lcd_drv_s *lcd_drv, int status)
+static void lcd_gpio_info_print(struct aml_lcd_drv_s *pdrv)
{
- int i;
+ struct lcd_power_ctrl_s *lcd_power;
+ int i = 0;
+
+ lcd_power = &pdrv->config.power;
+ printf("\ncpu_gpio:\n");
+ while (i < LCD_CPU_GPIO_NUM_MAX) {
+ if (strcmp(lcd_power->cpu_gpio[i], "invalid") == 0)
+ break;
+ printf("%d: gpio name=%s\n", i, lcd_power->cpu_gpio[i]);
+ i++;
+ }
+}
+
+static void lcd_power_info_print(struct aml_lcd_drv_s *pdrv, int status)
+{
struct lcd_power_step_s *power_step;
+ int i;
if (status) {
/* check if factory test */
- if (lcd_drv->factory_lcd_power_on_step) {
+ if (pdrv->factory_lcd_power_on_step) {
printf("factory test power on step:\n");
- power_step = lcd_drv->factory_lcd_power_on_step;
+ power_step = pdrv->factory_lcd_power_on_step;
} else {
printf("power on step:\n");
- power_step = &lcd_drv->lcd_config->lcd_power->power_on_step[0];
+ power_step = &pdrv->config.power.power_on_step[0];
}
} else {
printf("power off step:\n");
- power_step = &lcd_drv->lcd_config->lcd_power->power_off_step[0];
+ power_step = &pdrv->config.power.power_off_step[0];
}
i = 0;
@@ -99,6 +96,8 @@
switch (power_step->type) {
case LCD_POWER_TYPE_CPU:
case LCD_POWER_TYPE_PMU:
+ case LCD_POWER_TYPE_WAIT_GPIO:
+ case LCD_POWER_TYPE_CLK_SS:
printf("%d: type=%d, index=%d, value=%d, delay=%d\n",
i, power_step->type, power_step->index,
power_step->value, power_step->delay);
@@ -154,18 +153,14 @@
"port_swap %u\n"
"lane_reverse %u\n"
"phy_vswing 0x%x\n"
- "phy_preem 0x%x\n"
- "phy_clk_vswing 0x%x\n"
- "phy_clk_preem 0x%x\n\n",
- pconf->lcd_control.lvds_config->lvds_repack,
- pconf->lcd_control.lvds_config->dual_port,
- pconf->lcd_control.lvds_config->pn_swap,
- pconf->lcd_control.lvds_config->port_swap,
- pconf->lcd_control.lvds_config->lane_reverse,
- pconf->lcd_control.lvds_config->phy_vswing,
- pconf->lcd_control.lvds_config->phy_preem,
- pconf->lcd_control.lvds_config->phy_clk_vswing,
- pconf->lcd_control.lvds_config->phy_clk_preem);
+ "phy_preem 0x%x\n\n",
+ pconf->control.lvds_cfg.lvds_repack,
+ pconf->control.lvds_cfg.dual_port,
+ pconf->control.lvds_cfg.pn_swap,
+ pconf->control.lvds_cfg.port_swap,
+ pconf->control.lvds_cfg.lane_reverse,
+ pconf->control.lvds_cfg.phy_vswing,
+ pconf->control.lvds_cfg.phy_preem);
}
static void lcd_info_print_vbyone(struct lcd_config_s *pconf)
@@ -173,50 +168,38 @@
printf("lane_count %u\n"
"region_num %u\n"
"byte_mode %u\n"
+ "bit_rate %uHz\n"
"phy_vswing 0x%x\n"
"phy_preemphasis 0x%x\n"
+ "hw_filter_time 0x%x\n"
+ "hw_filter_cnt 0x%x\n"
"ctrl_flag 0x%x\n\n",
- pconf->lcd_control.vbyone_config->lane_count,
- pconf->lcd_control.vbyone_config->region_num,
- pconf->lcd_control.vbyone_config->byte_mode,
- pconf->lcd_control.vbyone_config->phy_vswing,
- pconf->lcd_control.vbyone_config->phy_preem,
- pconf->lcd_control.vbyone_config->ctrl_flag);
- if (pconf->lcd_control.vbyone_config->ctrl_flag & 0x1) {
+ pconf->control.vbyone_cfg.lane_count,
+ pconf->control.vbyone_cfg.region_num,
+ pconf->control.vbyone_cfg.byte_mode,
+ pconf->timing.bit_rate,
+ pconf->control.vbyone_cfg.phy_vswing,
+ pconf->control.vbyone_cfg.phy_preem,
+ pconf->control.vbyone_cfg.hw_filter_time,
+ pconf->control.vbyone_cfg.hw_filter_cnt,
+ pconf->control.vbyone_cfg.ctrl_flag);
+ if (pconf->control.vbyone_cfg.ctrl_flag & 0x1) {
printf("power_on_reset_en %u\n"
"power_on_reset_delay %ums\n\n",
- (pconf->lcd_control.vbyone_config->ctrl_flag & 0x1),
- pconf->lcd_control.vbyone_config->power_on_reset_delay);
+ (pconf->control.vbyone_cfg.ctrl_flag & 0x1),
+ pconf->control.vbyone_cfg.power_on_reset_delay);
}
- if (pconf->lcd_control.vbyone_config->ctrl_flag & 0x2) {
+ if (pconf->control.vbyone_cfg.ctrl_flag & 0x2) {
printf("hpd_data_delay_en %u\n"
"hpd_data_delay %ums\n\n",
- ((pconf->lcd_control.vbyone_config->ctrl_flag >> 1) & 0x1),
- pconf->lcd_control.vbyone_config->hpd_data_delay);
+ ((pconf->control.vbyone_cfg.ctrl_flag >> 1) & 0x1),
+ pconf->control.vbyone_cfg.hpd_data_delay);
}
- if (pconf->lcd_control.vbyone_config->ctrl_flag & 0x4) {
+ if (pconf->control.vbyone_cfg.ctrl_flag & 0x4) {
printf("cdr_training_hold_en %u\n"
"cdr_training_hold %ums\n\n",
- ((pconf->lcd_control.vbyone_config->ctrl_flag >> 2) & 0x1),
- pconf->lcd_control.vbyone_config->cdr_training_hold);
- }
- if (pconf->lcd_control.vbyone_config->vx1_sw_filter_en) {
- printf("vx1_sw_filter_en %u\n"
- "vx1_sw_filter_time %u\n"
- "vx1_sw_filter_cnt %u\n"
- "vx1_sw_filter_retry_cnt %u\n"
- "vx1_sw_filter_retry_delay %u\n"
- "vx1_sw_cdr_detect_time %u\n"
- "vx1_sw_cdr_detect_cnt %u\n"
- "vx1_sw_cdr_timeout_cnt %u\n\n",
- pconf->lcd_control.vbyone_config->vx1_sw_filter_en,
- pconf->lcd_control.vbyone_config->vx1_sw_filter_time,
- pconf->lcd_control.vbyone_config->vx1_sw_filter_cnt,
- pconf->lcd_control.vbyone_config->vx1_sw_filter_retry_cnt,
- pconf->lcd_control.vbyone_config->vx1_sw_filter_retry_delay,
- pconf->lcd_control.vbyone_config->vx1_sw_cdr_detect_time,
- pconf->lcd_control.vbyone_config->vx1_sw_cdr_detect_cnt,
- pconf->lcd_control.vbyone_config->vx1_sw_cdr_timeout_cnt);
+ ((pconf->control.vbyone_cfg.ctrl_flag >> 2) & 0x1),
+ pconf->control.vbyone_cfg.cdr_training_hold);
}
lcd_pinmux_info_print(pconf);
}
@@ -224,15 +207,15 @@
static void lcd_info_print_ttl(struct lcd_config_s *pconf)
{
printf("clk_pol %u\n"
- "hvsync_valid %u\n"
"DE_valid %u\n"
- "bit_swap %u\n"
- "rb_swap %u\n\n",
- pconf->lcd_control.ttl_config->clk_pol,
- (pconf->lcd_control.ttl_config->sync_valid >> 0) & 1,
- (pconf->lcd_control.ttl_config->sync_valid >> 1) & 1,
- (pconf->lcd_control.ttl_config->swap_ctrl >> 0) & 1,
- (pconf->lcd_control.ttl_config->swap_ctrl >> 1) & 1);
+ "hvsync_valid %u\n"
+ "rb_swap %u\n"
+ "bit_swap %u\n\n",
+ pconf->control.ttl_cfg.clk_pol,
+ (pconf->control.ttl_cfg.sync_valid >> 1) & 1,
+ (pconf->control.ttl_cfg.sync_valid >> 0) & 1,
+ (pconf->control.ttl_cfg.swap_ctrl >> 1) & 1,
+ (pconf->control.ttl_cfg.swap_ctrl >> 0) & 1);
lcd_pinmux_info_print(pconf);
}
@@ -243,33 +226,88 @@
#endif
}
+static void lcd_info_print_edp(struct lcd_config_s *pconf)
+{
+ printf("max_lane_count %u\n"
+ "max_link_rate %u\n"
+ "training_mode %u\n"
+ "dpcd_caps_en %u\n"
+ "sync_clk_mode %u\n"
+ "lane_count %u\n"
+ "link_rate %u\n"
+ "bit_rate %u\n"
+ "training_settings %u\n"
+ "main_stream_enable %u\n"
+ "phy_vswing 0x%x\n"
+ "phy_preem 0x%x\n\n",
+ pconf->control.edp_cfg.max_lane_count,
+ pconf->control.edp_cfg.max_link_rate,
+ pconf->control.edp_cfg.training_mode,
+ pconf->control.edp_cfg.dpcd_caps_en,
+ pconf->control.edp_cfg.sync_clk_mode,
+ pconf->control.edp_cfg.lane_count,
+ pconf->control.edp_cfg.link_rate,
+ pconf->timing.bit_rate,
+ pconf->control.edp_cfg.training_settings,
+ pconf->control.edp_cfg.main_stream_enable,
+ pconf->control.edp_cfg.phy_vswing,
+ pconf->control.edp_cfg.phy_preem);
+ lcd_pinmux_info_print(pconf);
+}
+
+#ifdef CONFIG_AML_LCD_TCON
static void lcd_info_print_mlvds(struct lcd_config_s *pconf)
{
printf("channel_num %d\n"
- "channel_sel1 0x%08x\n"
+ "channel_sel0 0x%08x\n"
"channel_sel1 0x%08x\n"
"clk_phase 0x%04x\n"
"pn_swap %u\n"
"bit_swap %u\n"
"phy_vswing 0x%x\n"
"phy_preem 0x%x\n"
- "bit_rate %dHz\n"
+ "bit_rate %uHz\n"
"pi_clk_sel 0x%03x\n\n",
- pconf->lcd_control.mlvds_config->channel_num,
- pconf->lcd_control.mlvds_config->channel_sel0,
- pconf->lcd_control.mlvds_config->channel_sel1,
- pconf->lcd_control.mlvds_config->clk_phase,
- pconf->lcd_control.mlvds_config->pn_swap,
- pconf->lcd_control.mlvds_config->bit_swap,
- pconf->lcd_control.mlvds_config->phy_vswing,
- pconf->lcd_control.mlvds_config->phy_preem,
- pconf->lcd_control.mlvds_config->bit_rate,
- pconf->lcd_control.mlvds_config->pi_clk_sel);
+ pconf->control.mlvds_cfg.channel_num,
+ pconf->control.mlvds_cfg.channel_sel0,
+ pconf->control.mlvds_cfg.channel_sel1,
+ pconf->control.mlvds_cfg.clk_phase,
+ pconf->control.mlvds_cfg.pn_swap,
+ pconf->control.mlvds_cfg.bit_swap,
+ pconf->control.mlvds_cfg.phy_vswing,
+ pconf->control.mlvds_cfg.phy_preem,
+ pconf->timing.bit_rate,
+ pconf->control.mlvds_cfg.pi_clk_sel);
lcd_tcon_info_print();
lcd_pinmux_info_print(pconf);
}
-static void lcd_reg_print_ttl(void)
+static void lcd_info_print_p2p(struct lcd_config_s *pconf)
+{
+ printf("p2p_type 0x%x\n"
+ "lane_num %d\n"
+ "channel_sel0 0x%08x\n"
+ "channel_sel1 0x%08x\n"
+ "pn_swap %u\n"
+ "bit_swap %u\n"
+ "bit_rate %uHz\n"
+ "phy_vswing 0x%x\n"
+ "phy_preem 0x%x\n\n",
+ pconf->control.p2p_cfg.p2p_type,
+ pconf->control.p2p_cfg.lane_num,
+ pconf->control.p2p_cfg.channel_sel0,
+ pconf->control.p2p_cfg.channel_sel1,
+ pconf->control.p2p_cfg.pn_swap,
+ pconf->control.p2p_cfg.bit_swap,
+ pconf->timing.bit_rate,
+ pconf->control.p2p_cfg.phy_vswing,
+ pconf->control.p2p_cfg.phy_preem);
+ lcd_tcon_info_print();
+ lcd_pinmux_info_print(pconf);
+}
+#endif
+
+static void lcd_reg_print_ttl(struct aml_lcd_drv_s *pdrv)
{
unsigned int reg;
@@ -315,188 +353,485 @@
reg, lcd_vcbus_read(reg));
}
-static void lcd_reg_print_lvds(void)
+static void lcd_reg_print_lvds(struct aml_lcd_drv_s *pdrv)
{
- unsigned int reg;
+ unsigned int reg, offset;
+
+ offset = pdrv->data->offset_venc_if[pdrv->index];
printf("\nlvds registers:\n");
- reg = LVDS_PACK_CNTL_ADDR;
+ reg = LVDS_PACK_CNTL_ADDR + offset;
printf("LVDS_PACK_CNTL [0x%04x] = 0x%08x\n",
- reg, lcd_vcbus_read(reg));
- reg = LVDS_GEN_CNTL;
+ reg, lcd_vcbus_read(reg));
+ reg = LVDS_GEN_CNTL + offset;
printf("LVDS_GEN_CNTL [0x%04x] = 0x%08x\n",
- reg, lcd_vcbus_read(reg));
- reg = LCD_PORT_SWAP;
- printf("LCD_PORT_SWAP [0x%04x] = 0x%08x\n",
- reg, lcd_vcbus_read(reg));
- reg = HHI_LVDS_TX_PHY_CNTL0;
- printf("LVDS_PHY_CNTL0 [0x%04x] = 0x%08x\n",
- reg, lcd_hiu_read(reg));
- reg = HHI_LVDS_TX_PHY_CNTL1;
- printf("LVDS_PHY_CNTL1 [0x%04x] = 0x%08x\n",
- reg, lcd_hiu_read(reg));
+ reg, lcd_vcbus_read(reg));
+
+ reg = P2P_CH_SWAP0 + offset;
+ printf("P2P_CH_SWAP0 [0x%04x] = 0x%08x\n",
+ reg, lcd_vcbus_read(reg));
+ reg = P2P_CH_SWAP1 + offset;
+ printf("P2P_CH_SWAP1 [0x%04x] = 0x%08x\n",
+ reg, lcd_vcbus_read(reg));
}
-static void lcd_reg_print_vbyone(void)
+static void lcd_reg_print_vbyone(struct aml_lcd_drv_s *pdrv)
{
- unsigned int reg;
+ unsigned int reg, offset;
+
+ offset = pdrv->data->offset_venc_if[pdrv->index];
printf("\nvbyone registers:\n");
- reg = VBO_STATUS_L;
+ reg = VBO_STATUS_L + offset;
printf("VX1_STATUS [0x%04x] = 0x%08x\n",
- reg, lcd_vcbus_read(reg));
- reg = VBO_FSM_HOLDER_L;
+ reg, lcd_vcbus_read(reg));
+ reg = VBO_FSM_HOLDER_L + offset;
printf("VX1_FSM_HOLDER_L [0x%04x] = 0x%08x\n",
- reg, lcd_vcbus_read(reg));
- reg = VBO_FSM_HOLDER_H;
+ reg, lcd_vcbus_read(reg));
+ reg = VBO_FSM_HOLDER_H + offset;
printf("VX1_FSM_HOLDER_H [0x%04x] = 0x%08x\n",
- reg, lcd_vcbus_read(reg));
- reg = VBO_INTR_STATE_CTRL;
+ reg, lcd_vcbus_read(reg));
+ reg = VBO_INTR_STATE_CTRL + offset;
printf("VX1_INTR_STATE_CTRL [0x%04x] = 0x%08x\n",
- reg, lcd_vcbus_read(reg));
- reg = VBO_INTR_UNMASK;
+ reg, lcd_vcbus_read(reg));
+ reg = VBO_INTR_UNMASK + offset;
printf("VX1_INTR_UNMASK [0x%04x] = 0x%08x\n",
- reg, lcd_vcbus_read(reg));
- reg = VBO_INTR_STATE;
+ reg, lcd_vcbus_read(reg));
+ reg = VBO_INTR_STATE + offset;
printf("VX1_INTR_STATE [0x%04x] = 0x%08x\n",
- reg, lcd_vcbus_read(reg));
- reg = VBO_INSGN_CTRL;
+ reg, lcd_vcbus_read(reg));
+ reg = VBO_INSGN_CTRL + offset;
printf("VBO_INSGN_CTRL [0x%04x] = 0x%08x\n",
- reg, lcd_vcbus_read(reg));
- reg = HHI_LVDS_TX_PHY_CNTL0;
- printf("VX1_PHY_CNTL0 [0x%04x] = 0x%08x\n",
- reg, lcd_hiu_read(reg));
+ reg, lcd_vcbus_read(reg));
}
-static void lcd_reg_print_mlvds(void)
+#ifdef CONFIG_AML_LCD_TCON
+static void lcd_reg_print_tcon(struct aml_lcd_drv_s *pdrv)
{
unsigned int reg;
- lcd_reg_print_lvds();
-
printf("\ntcon clk registers:\n");
reg = HHI_TCON_CLK_CNTL;
printf("HHI_TCON_CLK_CNTL [0x%08x] = 0x%08x\n",
- reg, lcd_hiu_read(reg));
+ reg, lcd_clk_read(reg));
reg = HHI_HPLL_CNTL6;
printf("HHI_HPLL_CNTL6 [0x%08x] = 0x%08x\n",
- reg, lcd_hiu_read(reg));
+ reg, lcd_clk_read(reg));
reg = HHI_DIF_TCON_CNTL0;
printf("HHI_DIF_TCON_CNTL0 [0x%08x] = 0x%08x\n",
- reg, lcd_hiu_read(reg));
+ reg, lcd_clk_read(reg));
reg = HHI_DIF_TCON_CNTL1;
printf("HHI_DIF_TCON_CNTL1 [0x%08x] = 0x%08x\n",
- reg, lcd_hiu_read(reg));
+ reg, lcd_clk_read(reg));
reg = HHI_DIF_TCON_CNTL2;
printf("HHI_DIF_TCON_CNTL2 [0x%08x] = 0x%08x\n",
- reg, lcd_hiu_read(reg));
+ reg, lcd_clk_read(reg));
printf("\ntcon top registers:\n");
reg = TCON_TOP_CTRL;
printf("TCON_TOP_CTRL [0x%04x] = 0x%08x\n",
- reg, lcd_tcon_read(reg));
+ reg, lcd_tcon_read(reg));
reg = TCON_OUT_CH_SEL0;
printf("TCON_OUT_CH_SEL0 [0x%04x] = 0x%08x\n",
- reg, lcd_tcon_read(reg));
+ reg, lcd_tcon_read(reg));
reg = TCON_OUT_CH_SEL1;
printf("TCON_OUT_CH_SEL1 [0x%04x] = 0x%08x\n",
- reg, lcd_tcon_read(reg));
+ reg, lcd_tcon_read(reg));
reg = TCON_STATUS0;
printf("TCON_STATUS0 [0x%04x] = 0x%08x\n",
- reg, lcd_tcon_read(reg));
+ reg, lcd_tcon_read(reg));
reg = TCON_PLLLOCK_CNTL;
printf("TCON_PLLLOCK_CNTL [0x%04x] = 0x%08x\n",
- reg, lcd_tcon_read(reg));
+ reg, lcd_tcon_read(reg));
reg = TCON_RST_CTRL;
printf("TCON_RST_CTRL [0x%04x] = 0x%08x\n",
- reg, lcd_tcon_read(reg));
+ reg, lcd_tcon_read(reg));
reg = TCON_CLK_CTRL;
printf("TCON_CLK_CTRL [0x%04x] = 0x%08x\n",
- reg, lcd_tcon_read(reg));
+ reg, lcd_tcon_read(reg));
reg = TCON_STATUS1;
printf("TCON_STATUS1 [0x%04x] = 0x%08x\n",
- reg, lcd_tcon_read(reg));
+ reg, lcd_tcon_read(reg));
+
+ reg = LVDS_CH_SWAP0;
+ printf("LVDS_CH_SWAP0 [0x%04x] = 0x%08x\n",
+ reg, lcd_vcbus_read(reg));
+ reg = LVDS_CH_SWAP1;
+ printf("LVDS_CH_SWAP1 [0x%04x] = 0x%08x\n",
+ reg, lcd_vcbus_read(reg));
+ reg = LVDS_CH_SWAP2;
+ printf("LVDS_CH_SWAP2 [0x%04x] = 0x%08x\n",
+ reg, lcd_vcbus_read(reg));
}
-static void lcd_reg_print_mipi(void)
+static void lcd_reg_print_tcon_tl1(struct aml_lcd_drv_s *pdrv)
{
unsigned int reg;
+ printf("\ntcon registers:\n");
+ reg = HHI_TCON_CLK_CNTL;
+ printf("HHI_TCON_CLK_CNTL [0x%08x] = 0x%08x\n",
+ reg, lcd_clk_read(reg));
+ reg = TCON_TOP_CTRL;
+ printf("TCON_TOP_CTRL [0x%04x] = 0x%08x\n",
+ reg, lcd_tcon_read(reg));
+ reg = TCON_RGB_IN_MUX;
+ printf("TCON_RGB_IN_MUX [0x%04x] = 0x%08x\n",
+ reg, lcd_tcon_read(reg));
+ reg = TCON_OUT_CH_SEL0;
+ printf("TCON_OUT_CH_SEL0 [0x%04x] = 0x%08x\n",
+ reg, lcd_tcon_read(reg));
+ reg = TCON_OUT_CH_SEL1;
+ printf("TCON_OUT_CH_SEL1 [0x%04x] = 0x%08x\n",
+ reg, lcd_tcon_read(reg));
+ reg = TCON_STATUS0;
+ printf("TCON_STATUS0 [0x%04x] = 0x%08x\n",
+ reg, lcd_tcon_read(reg));
+ reg = TCON_PLLLOCK_CNTL;
+ printf("TCON_PLLLOCK_CNTL [0x%04x] = 0x%08x\n",
+ reg, lcd_tcon_read(reg));
+ reg = TCON_RST_CTRL;
+ printf("TCON_RST_CTRL [0x%04x] = 0x%08x\n",
+ reg, lcd_tcon_read(reg));
+ reg = TCON_AXI_OFST0;
+ printf("TCON_AXI_OFST0 [0x%04x] = 0x%08x\n",
+ reg, lcd_tcon_read(reg));
+ reg = TCON_AXI_OFST1;
+ printf("TCON_AXI_OFST1 [0x%04x] = 0x%08x\n",
+ reg, lcd_tcon_read(reg));
+ reg = TCON_AXI_OFST2;
+ printf("TCON_AXI_OFST2 [0x%04x] = 0x%08x\n",
+ reg, lcd_tcon_read(reg));
+ reg = TCON_CLK_CTRL;
+ printf("TCON_CLK_CTRL [0x%04x] = 0x%08x\n",
+ reg, lcd_tcon_read(reg));
+ reg = TCON_STATUS1;
+ printf("TCON_STATUS1 [0x%04x] = 0x%08x\n",
+ reg, lcd_tcon_read(reg));
+ reg = TCON_DDRIF_CTRL1;
+ printf("TCON_DDRIF_CTRL1 [0x%04x] = 0x%08x\n",
+ reg, lcd_tcon_read(reg));
+ reg = TCON_DDRIF_CTRL2;
+ printf("TCON_DDRIF_CTRL2 [0x%04x] = 0x%08x\n",
+ reg, lcd_tcon_read(reg));
+}
+#endif
+
+static void lcd_reg_print_mipi(struct aml_lcd_drv_s *pdrv)
+{
+ unsigned int reg;
+ int index = pdrv->index;
+
printf("\nmipi_dsi registers:\n");
reg = MIPI_DSI_TOP_CNTL;
printf("MIPI_DSI_TOP_CNTL [0x%04x] = 0x%08x\n",
- reg, dsi_host_read(reg));
+ reg, dsi_host_read(index, reg));
reg = MIPI_DSI_TOP_CLK_CNTL;
printf("MIPI_DSI_TOP_CLK_CNTL [0x%04x] = 0x%08x\n",
- reg, dsi_host_read(reg));
+ reg, dsi_host_read(index, reg));
reg = MIPI_DSI_DWC_PWR_UP_OS;
printf("MIPI_DSI_DWC_PWR_UP_OS [0x%04x] = 0x%08x\n",
- reg, dsi_host_read(reg));
+ reg, dsi_host_read(index, reg));
reg = MIPI_DSI_DWC_PCKHDL_CFG_OS;
printf("MIPI_DSI_DWC_PCKHDL_CFG_OS [0x%04x] = 0x%08x\n",
- reg, dsi_host_read(reg));
+ reg, dsi_host_read(index, reg));
reg = MIPI_DSI_DWC_LPCLK_CTRL_OS;
printf("MIPI_DSI_DWC_LPCLK_CTRL_OS [0x%04x] = 0x%08x\n",
- reg, dsi_host_read(reg));
+ reg, dsi_host_read(index, reg));
reg = MIPI_DSI_DWC_CMD_MODE_CFG_OS;
printf("MIPI_DSI_DWC_CMD_MODE_CFG_OS [0x%04x] = 0x%08x\n",
- reg, dsi_host_read(reg));
+ reg, dsi_host_read(index, reg));
reg = MIPI_DSI_DWC_VID_MODE_CFG_OS;
printf("MIPI_DSI_DWC_VID_MODE_CFG_OS [0x%04x] = 0x%08x\n",
- reg, dsi_host_read(reg));
+ reg, dsi_host_read(index, reg));
reg = MIPI_DSI_DWC_MODE_CFG_OS;
printf("MIPI_DSI_DWC_MODE_CFG_OS [0x%04x] = 0x%08x\n",
- reg, dsi_host_read(reg));
+ reg, dsi_host_read(index, reg));
reg = MIPI_DSI_DWC_PHY_STATUS_OS;
printf("MIPI_DSI_DWC_PHY_STATUS_OS [0x%04x] = 0x%08x\n",
- reg, dsi_host_read(reg));
+ reg, dsi_host_read(index, reg));
reg = MIPI_DSI_DWC_INT_ST0_OS;
printf("MIPI_DSI_DWC_INT_ST0_OS [0x%04x] = 0x%08x\n",
- reg, dsi_host_read(reg));
+ reg, dsi_host_read(index, reg));
reg = MIPI_DSI_DWC_INT_ST1_OS;
printf("MIPI_DSI_DWC_INT_ST1_OS [0x%04x] = 0x%08x\n",
- reg, dsi_host_read(reg));
+ reg, dsi_host_read(index, reg));
reg = MIPI_DSI_TOP_STAT;
printf("MIPI_DSI_TOP_STAT [0x%04x] = 0x%08x\n",
- reg, dsi_host_read(reg));
+ reg, dsi_host_read(index, reg));
reg = MIPI_DSI_TOP_INTR_CNTL_STAT;
printf("MIPI_DSI_TOP_INTR_CNTL_STAT [0x%04x] = 0x%08x\n",
- reg, dsi_host_read(reg));
+ reg, dsi_host_read(index, reg));
reg = MIPI_DSI_TOP_MEM_PD;
printf("MIPI_DSI_TOP_MEM_PD [0x%04x] = 0x%08x\n",
- reg, dsi_host_read(reg));
+ reg, dsi_host_read(index, reg));
}
-static void lcd_reg_print_phy_analog(void)
+static void lcd_reg_print_edp(struct aml_lcd_drv_s *pdrv)
+{
+ unsigned int reg;
+ int index = pdrv->index;
+
+ if (index > 1) {
+ LCDERR("%s: invalid drv_index %d\n", __func__, index);
+ return;
+ }
+
+ printf("\nedp registers:\n");
+ reg = EDP_TX_LINK_BW_SET;
+ printf("EDP_TX_LINK_BW_SET [0x%04x] = 0x%08x\n",
+ reg, dptx_reg_read(index, reg));
+ reg = EDP_TX_LINK_COUNT_SET;
+ printf("EDP_TX_LINK_COUNT_SET [0x%04x] = 0x%08x\n",
+ reg, dptx_reg_read(index, reg));
+ reg = EDP_TX_TRAINING_PATTERN_SET;
+ printf("EDP_TX_TRAINING_PATTERN_SET [0x%04x] = 0x%08x\n",
+ reg, dptx_reg_read(index, reg));
+ reg = EDP_TX_SCRAMBLING_DISABLE;
+ printf("EDP_TX_SCRAMBLING_DISABLE [0x%04x] = 0x%08x\n",
+ reg, dptx_reg_read(index, reg));
+ reg = EDP_TX_SCRAMBLING_DISABLE;
+ printf("EDP_TX_SCRAMBLING_DISABLE [0x%04x] = 0x%08x\n",
+ reg, dptx_reg_read(index, reg));
+ reg = EDP_TX_TRANSMITTER_OUTPUT_ENABLE;
+ printf("EDP_TX_TRANSMITTER_OUTPUT_ENABLE [0x%04x] = 0x%08x\n",
+ reg, dptx_reg_read(index, reg));
+ reg = EDP_TX_MAIN_STREAM_ENABLE;
+ printf("EDP_TX_MAIN_STREAM_ENABLE [0x%04x] = 0x%08x\n",
+ reg, dptx_reg_read(index, reg));
+ reg = EDP_TX_PHY_RESET;
+ printf("EDP_TX_PHY_RESET [0x%04x] = 0x%08x\n",
+ reg, dptx_reg_read(index, reg));
+ reg = EDP_TX_PHY_STATUS;
+ printf("EDP_TX_PHY_STATUS [0x%04x] = 0x%08x\n",
+ reg, dptx_reg_read(index, reg));
+ reg = EDP_TX_AUX_COMMAND;
+ printf("EDP_TX_AUX_COMMAND [0x%04x] = 0x%08x\n",
+ reg, dptx_reg_read(index, reg));
+ reg = EDP_TX_AUX_ADDRESS;
+ printf("EDP_TX_AUX_ADDRESS [0x%04x] = 0x%08x\n",
+ reg, dptx_reg_read(index, reg));
+ reg = EDP_TX_AUX_STATE;
+ printf("EDP_TX_AUX_STATE [0x%04x] = 0x%08x\n",
+ reg, dptx_reg_read(index, reg));
+ reg = EDP_TX_AUX_REPLY_CODE;
+ printf("EDP_TX_AUX_REPLY_CODE [0x%04x] = 0x%08x\n",
+ reg, dptx_reg_read(index, reg));
+ reg = EDP_TX_AUX_REPLY_COUNT;
+ printf("EDP_TX_AUX_REPLY_COUNT [0x%04x] = 0x%08x\n",
+ reg, dptx_reg_read(index, reg));
+ reg = EDP_TX_AUX_REPLY_DATA_COUNT;
+ printf("EDP_TX_AUX_REPLY_DATA_COUNT [0x%04x] = 0x%08x\n",
+ reg, dptx_reg_read(index, reg));
+ reg = EDP_TX_AUX_TRANSFER_STATUS;
+ printf("EDP_TX_AUX_TRANSFER_STATUS [0x%04x] = 0x%08x\n",
+ reg, dptx_reg_read(index, reg));
+
+ dptx_dpcd_dump(pdrv);
+}
+
+static void lcd_reg_print_serializer(void)
+{
+ unsigned int reg;
+
+ reg = HHI_LVDS_TX_PHY_CNTL0;
+ printf("HHI_LVDS_TX_PHY_CNTL0 [0x%08x] = 0x%08x\n",
+ reg, lcd_clk_read(reg));
+ reg = HHI_LVDS_TX_PHY_CNTL1;
+ printf("HHI_LVDS_TX_PHY_CNTL1 [0x%08x] = 0x%08x\n",
+ reg, lcd_clk_read(reg));
+}
+
+static void lcd_reg_print_phy_analog(struct aml_lcd_drv_s *pdrv)
{
unsigned int reg;
printf("\nphy analog registers:\n");
+ lcd_reg_print_serializer();
+
reg = HHI_DIF_CSI_PHY_CNTL1;
printf("PHY_CNTL1 [0x%08x] = 0x%08x\n",
- reg, lcd_hiu_read(reg));
+ reg, lcd_clk_read(reg));
reg = HHI_DIF_CSI_PHY_CNTL2;
printf("PHY_CNTL2 [0x%08x] = 0x%08x\n",
- reg, lcd_hiu_read(reg));
+ reg, lcd_clk_read(reg));
reg = HHI_DIF_CSI_PHY_CNTL3;
printf("PHY_CNTL3 [0x%08x] = 0x%08x\n",
- reg, lcd_hiu_read(reg));
+ reg, lcd_clk_read(reg));
}
-static void lcd_reg_print_mipi_phy_analog(void)
+static void lcd_reg_print_phy_analog_tl1(struct aml_lcd_drv_s *pdrv)
{
unsigned int reg;
printf("\nphy analog registers:\n");
+ lcd_reg_print_serializer();
+
+ reg = HHI_DIF_CSI_PHY_CNTL1;
+ printf("PHY_CNTL1 [0x%08x] = 0x%08x\n",
+ reg, lcd_clk_read(reg));
+ reg = HHI_DIF_CSI_PHY_CNTL2;
+ printf("PHY_CNTL2 [0x%08x] = 0x%08x\n",
+ reg, lcd_clk_read(reg));
+ reg = HHI_DIF_CSI_PHY_CNTL3;
+ printf("PHY_CNTL3 [0x%08x] = 0x%08x\n",
+ reg, lcd_clk_read(reg));
+ reg = HHI_DIF_CSI_PHY_CNTL4;
+ printf("PHY_CNTL4 [0x%08x] = 0x%08x\n",
+ reg, lcd_clk_read(reg));
+ reg = HHI_DIF_CSI_PHY_CNTL6;
+ printf("PHY_CNTL6 [0x%08x] = 0x%08x\n",
+ reg, lcd_clk_read(reg));
+ reg = HHI_DIF_CSI_PHY_CNTL7;
+ printf("PHY_CNTL7 [0x%08x] = 0x%08x\n",
+ reg, lcd_clk_read(reg));
+ reg = HHI_DIF_CSI_PHY_CNTL8;
+ printf("PHY_CNTL8 [0x%08x] = 0x%08x\n",
+ reg, lcd_clk_read(reg));
+ reg = HHI_DIF_CSI_PHY_CNTL9;
+ printf("PHY_CNTL9 [0x%08x] = 0x%08x\n",
+ reg, lcd_clk_read(reg));
+ reg = HHI_DIF_CSI_PHY_CNTL10;
+ printf("PHY_CNTL10 [0x%08x] = 0x%08x\n",
+ reg, lcd_clk_read(reg));
+ reg = HHI_DIF_CSI_PHY_CNTL11;
+ printf("PHY_CNTL11 [0x%08x] = 0x%08x\n",
+ reg, lcd_clk_read(reg));
+ reg = HHI_DIF_CSI_PHY_CNTL12;
+ printf("PHY_CNTL12 [0x%08x] = 0x%08x\n",
+ reg, lcd_clk_read(reg));
+ reg = HHI_DIF_CSI_PHY_CNTL13;
+ printf("PHY_CNTL13 [0x%08x] = 0x%08x\n",
+ reg, lcd_clk_read(reg));
+ reg = HHI_DIF_CSI_PHY_CNTL14;
+ printf("PHY_CNTL14 [0x%08x] = 0x%08x\n",
+ reg, lcd_clk_read(reg));
+ reg = HHI_DIF_CSI_PHY_CNTL15;
+ printf("PHY_CNTL15 [0x%08x] = 0x%08x\n",
+ reg, lcd_clk_read(reg));
+ reg = HHI_DIF_CSI_PHY_CNTL16;
+ printf("PHY_CNTL16 [0x%08x] = 0x%08x\n",
+ reg, lcd_clk_read(reg));
+}
+
+static void lcd_reg_print_dphy_t7(struct aml_lcd_drv_s *pdrv)
+{
+ unsigned int reg0, reg1;
+
+ switch (pdrv->index) {
+ case 1:
+ reg0 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL0;
+ reg1 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL1;
+ break;
+ case 2:
+ reg0 = COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL0;
+ reg1 = COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL1;
+ break;
+ case 0:
+ default:
+ reg0 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0;
+ reg1 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1;
+ break;
+ }
+
+ printf("COMBO_DPHY_CNTL0 [0x%08x] = 0x%08x\n",
+ COMBO_DPHY_CNTL0, lcd_combo_dphy_read(COMBO_DPHY_CNTL0));
+ printf("COMBO_DPHY_CNTL1 [0x%08x] = 0x%08x\n",
+ COMBO_DPHY_CNTL1, lcd_combo_dphy_read(COMBO_DPHY_CNTL1));
+ printf("COMBO_DPHY_EDP_LVDS_TX_PHY%d_CNTL0 [0x%08x] = 0x%08x\n",
+ pdrv->index, reg0, lcd_combo_dphy_read(reg0));
+ printf("COMBO_DPHY_EDP_LVDS_TX_PHY%d_CNTL1 [0x%08x] = 0x%08x\n",
+ pdrv->index, reg1, lcd_combo_dphy_read(reg1));
+}
+
+static void lcd_reg_print_phy_analog_t7(struct aml_lcd_drv_s *pdrv)
+{
+ unsigned int reg;
+
+ printf("\nphy analog registers:\n");
+ lcd_reg_print_dphy_t7(pdrv);
+
+ reg = ANACTRL_DIF_PHY_CNTL1;
+ printf("PHY_CNTL1 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL2;
+ printf("PHY_CNTL2 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL3;
+ printf("PHY_CNTL3 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL4;
+ printf("PHY_CNTL4 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL5;
+ printf("PHY_CNTL5 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL6;
+ printf("PHY_CNTL6 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL7;
+ printf("PHY_CNTL7 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL8;
+ printf("PHY_CNTL8 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL9;
+ printf("PHY_CNTL9 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL10;
+ printf("PHY_CNTL10 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL11;
+ printf("PHY_CNTL11 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL12;
+ printf("PHY_CNTL12 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL13;
+ printf("PHY_CNTL13 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL14;
+ printf("PHY_CNTL14 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL15;
+ printf("PHY_CNTL15 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL16;
+ printf("PHY_CNTL16 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL17;
+ printf("PHY_CNTL17 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL18;
+ printf("PHY_CNTL18 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL19;
+ printf("PHY_CNTL19 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL20;
+ printf("PHY_CNTL20 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+ reg = ANACTRL_DIF_PHY_CNTL21;
+ printf("PHY_CNTL21 [0x%08x] = 0x%08x\n",
+ reg, lcd_ana_read(reg));
+}
+
+static void lcd_reg_print_mipi_phy_analog(struct aml_lcd_drv_s *pdrv)
+{
+ unsigned int reg;
+#ifdef CONFIG_AML_LCD_PXP
+ return;
+#endif
+ printf("\nphy analog registers:\n");
reg = HHI_MIPI_CNTL0;
printf("PHY_CNTL1 [0x%08x] = 0x%08x\n",
- reg, lcd_hiu_read(reg));
+ reg, lcd_clk_read(reg));
reg = HHI_MIPI_CNTL1;
printf("PHY_CNTL2 [0x%08x] = 0x%08x\n",
- reg, lcd_hiu_read(reg));
+ reg, lcd_clk_read(reg));
reg = HHI_MIPI_CNTL2;
printf("PHY_CNTL3 [0x%08x] = 0x%08x\n",
- reg, lcd_hiu_read(reg));
+ reg, lcd_clk_read(reg));
}
#define TV_LCD_ENC_TST_NUM_MAX 9
@@ -529,158 +864,562 @@
* lcd debug function api
* **********************************
*/
-void lcd_debug_test(unsigned int num)
+void aml_lcd_debug_test(struct aml_lcd_drv_s *pdrv, unsigned int num)
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- unsigned int start, width;
+ unsigned int start, width, offset;
- start = lcd_drv->lcd_config->lcd_timing.video_on_pixel;
- width = lcd_drv->lcd_config->lcd_basic.h_active / 9;
+ offset = pdrv->data->offset_venc[pdrv->index];
+
+ start = pdrv->config.timing.video_on_pixel;
+ width = pdrv->config.basic.h_active / 9;
num = (num >= TV_LCD_ENC_TST_NUM_MAX) ? 0 : num;
- lcd_wait_vsync();
- lcd_vcbus_write(ENCL_VIDEO_RGBIN_CTRL, lcd_enc_tst[num][6]);
- lcd_vcbus_write(ENCL_TST_MDSEL, lcd_enc_tst[num][0]);
- lcd_vcbus_write(ENCL_TST_Y, lcd_enc_tst[num][1]);
- lcd_vcbus_write(ENCL_TST_CB, lcd_enc_tst[num][2]);
- lcd_vcbus_write(ENCL_TST_CR, lcd_enc_tst[num][3]);
- lcd_vcbus_write(ENCL_TST_CLRBAR_STRT, start);
- lcd_vcbus_write(ENCL_TST_CLRBAR_WIDTH, width);
- lcd_vcbus_write(ENCL_TST_EN, lcd_enc_tst[num][4]);
- lcd_vcbus_setb(ENCL_VIDEO_MODE_ADV, lcd_enc_tst[num][5], 3, 1);
+ lcd_wait_vsync(pdrv);
+ lcd_vcbus_write(ENCL_VIDEO_RGBIN_CTRL + offset, lcd_enc_tst[num][6]);
+ lcd_vcbus_write(ENCL_TST_MDSEL + offset, lcd_enc_tst[num][0]);
+ lcd_vcbus_write(ENCL_TST_Y + offset, lcd_enc_tst[num][1]);
+ lcd_vcbus_write(ENCL_TST_CB + offset, lcd_enc_tst[num][2]);
+ lcd_vcbus_write(ENCL_TST_CR + offset, lcd_enc_tst[num][3]);
+ lcd_vcbus_write(ENCL_TST_CLRBAR_STRT + offset, start);
+ lcd_vcbus_write(ENCL_TST_CLRBAR_WIDTH + offset, width);
+ lcd_vcbus_write(ENCL_TST_EN + offset, lcd_enc_tst[num][4]);
+ lcd_vcbus_setb(ENCL_VIDEO_MODE_ADV + offset, lcd_enc_tst[num][5], 3, 1);
if (num > 0) {
- LCDPR("show test pattern: %s\n", lcd_enc_tst_str[num]);
+ LCDPR("[%d]: lcd show test pattern: %s\n",
+ pdrv->index, lcd_enc_tst_str[num]);
} else {
- LCDPR("disable test pattern\n");
+ LCDPR("[%d]: lcd disable test pattern\n", pdrv->index);
}
}
-void lcd_mute_setting(unsigned char flag)
+void lcd_mute_setting(struct aml_lcd_drv_s *pdrv, unsigned char flag)
{
- lcd_wait_vsync();
+ unsigned int offset;
+
+ offset = pdrv->data->offset_venc[pdrv->index];
+
+ lcd_wait_vsync(pdrv);
if (flag) {
- lcd_vcbus_write(ENCL_VIDEO_RGBIN_CTRL, 3);
- lcd_vcbus_write(ENCL_TST_MDSEL, 0);
- lcd_vcbus_write(ENCL_TST_Y, 0);
- lcd_vcbus_write(ENCL_TST_CB, 0);
- lcd_vcbus_write(ENCL_TST_CR, 0);
- lcd_vcbus_write(ENCL_TST_EN, 1);
- lcd_vcbus_setb(ENCL_VIDEO_MODE_ADV, 0, 3, 1);
- LCDPR("set mute\n");
+ lcd_vcbus_write(ENCL_VIDEO_RGBIN_CTRL + offset, 3);
+ lcd_vcbus_write(ENCL_TST_MDSEL + offset, 0);
+ lcd_vcbus_write(ENCL_TST_Y + offset, 0);
+ lcd_vcbus_write(ENCL_TST_CB + offset, 0);
+ lcd_vcbus_write(ENCL_TST_CR + offset, 0);
+ lcd_vcbus_write(ENCL_TST_EN + offset, 1);
+ lcd_vcbus_setb(ENCL_VIDEO_MODE_ADV + offset, 0, 3, 1);
+ LCDPR("[%d]: set lcd mute\n", pdrv->index);
} else {
- lcd_vcbus_setb(ENCL_VIDEO_MODE_ADV, 1, 3, 1);
- lcd_vcbus_write(ENCL_TST_EN, 0);
- LCDPR("clear mute\n");
+ lcd_vcbus_setb(ENCL_VIDEO_MODE_ADV + offset, 1, 3, 1);
+ lcd_vcbus_write(ENCL_TST_EN + offset, 0);
+ LCDPR("[%d]: clear lcd mute\n", pdrv->index);
}
}
-void lcd_info_print(void)
+#define CLK_CHK_MAX 2 /*MHz*/
+static unsigned int lcd_prbs_performed, lcd_prbs_err;
+static unsigned long lcd_encl_clk_check_std = 121;
+static unsigned long lcd_fifo_clk_check_std = 42;
+
+static unsigned long lcd_abs(unsigned long a, unsigned long b)
+{
+ unsigned long val;
+
+ if (a >= b)
+ val = a - b;
+ else
+ val = b - a;
+
+ return val;
+}
+
+static int lcd_prbs_clk_check(unsigned long encl_clk, int encl_msr_id,
+ unsigned long fifo_clk, int fifo_msr_id,
+ unsigned int cnt)
+{
+ unsigned long clk_check, temp;
+
+ if (encl_msr_id == -1)
+ goto lcd_prbs_clk_check_next;
+ clk_check = clk_util_clk_msr(encl_msr_id);
+ if (clk_check != encl_clk) {
+ temp = lcd_abs(clk_check, encl_clk);
+ if (temp >= CLK_CHK_MAX) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_TEST) {
+ LCDERR("encl clkmsr error %ld, cnt: %d\n",
+ clk_check, cnt);
+ }
+ return -1;
+ }
+ }
+
+lcd_prbs_clk_check_next:
+ if (encl_msr_id == -1)
+ return 0;
+ clk_check = clk_util_clk_msr(fifo_msr_id);
+ if (clk_check != fifo_clk) {
+ temp = lcd_abs(clk_check, fifo_clk);
+ if (temp >= CLK_CHK_MAX) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_TEST) {
+ LCDERR("fifo clkmsr error %ld, cnt:%d\n",
+ clk_check, cnt);
+ }
+ return -1;
+ }
+ }
+
+ return 0;
+}
+
+static int lcd_prbs_test_tl1(struct aml_lcd_drv_s *pdrv, unsigned int s, unsigned int mode_flag)
+{
+ struct lcd_clk_config_s *cconf;
+ unsigned int reg_phy_tx_ctrl0, reg_phy_tx_ctrl1;
+ int encl_msr_id, fifo_msr_id;
+ unsigned int lcd_prbs_mode;
+ unsigned int val1, val2, timeout;
+ unsigned int cnt = 0;
+ unsigned int clk_err_cnt = 0;
+ int i, j, ret;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return -1;
+
+ reg_phy_tx_ctrl0 = HHI_LVDS_TX_PHY_CNTL0;
+ reg_phy_tx_ctrl1 = HHI_LVDS_TX_PHY_CNTL1;
+ encl_msr_id = 9;
+ fifo_msr_id = 129;
+
+ s = (s == 0) ? 1 : ((s > 1800) ? 1800 : s);
+ timeout = s * 200;
+ for (i = 0; i < LCD_PRBS_MODE_MAX; i++) {
+ if ((mode_flag & (1 << i)) == 0)
+ continue;
+
+ lcd_ana_write(reg_phy_tx_ctrl0, 0);
+ lcd_ana_write(reg_phy_tx_ctrl1, 0);
+
+ cnt = 0;
+ clk_err_cnt = 0;
+ lcd_prbs_mode = (1 << i);
+ LCDPR("lcd_prbs_mode: %d\n", lcd_prbs_mode);
+ if (lcd_prbs_mode == LCD_PRBS_MODE_LVDS) {
+ lcd_encl_clk_check_std = 136;
+ lcd_fifo_clk_check_std = 48;
+ } else if (lcd_prbs_mode == LCD_PRBS_MODE_VX1) {
+ lcd_encl_clk_check_std = 594;
+ lcd_fifo_clk_check_std = 297;
+ }
+ if (cconf->data->prbs_clk_config) {
+ cconf->data->prbs_clk_config(pdrv, lcd_prbs_mode);
+ } else {
+ LCDERR("%s: prbs_clk_config is null\n", __func__);
+ goto lcd_prbs_test_end;
+ }
+ mdelay(20);
+
+ lcd_ana_write(reg_phy_tx_ctrl0, 0x000000c0);
+ lcd_ana_setb(reg_phy_tx_ctrl0, 0xfff, 16, 12);
+ lcd_ana_setb(reg_phy_tx_ctrl0, 1, 2, 1);
+ lcd_ana_write(reg_phy_tx_ctrl1, 0x41000000);
+ lcd_ana_setb(reg_phy_tx_ctrl1, 1, 31, 1);
+
+ lcd_ana_write(reg_phy_tx_ctrl0, 0xfff20c4);
+ lcd_ana_setb(reg_phy_tx_ctrl0, 1, 12, 1);
+ val1 = lcd_ana_getb(reg_phy_tx_ctrl1, 12, 12);
+
+ while (cnt++ < timeout) {
+ mdelay(5);
+ ret = 1;
+ for (j = 0; j < 5; j++) {
+ val2 = lcd_ana_getb(reg_phy_tx_ctrl1, 12, 12);
+ if (val2 != val1) {
+ ret = 0;
+ break;
+ }
+ }
+ if (ret) {
+ LCDERR("prbs check error 1, val:0x%03x, cnt:%d\n",
+ val2, cnt);
+ goto lcd_prbs_test_err;
+ }
+ val1 = val2;
+ if (lcd_ana_getb(reg_phy_tx_ctrl1, 0, 12)) {
+ LCDERR("prbs check error 2, cnt:%d\n", cnt);
+ goto lcd_prbs_test_err;
+ }
+ if (lcd_prbs_clk_check(lcd_encl_clk_check_std, encl_msr_id,
+ lcd_fifo_clk_check_std, fifo_msr_id,
+ cnt))
+ clk_err_cnt++;
+ else
+ clk_err_cnt = 0;
+ if (clk_err_cnt >= 10) {
+ LCDERR("prbs check error 3(clkmsr), cnt:%d\n",
+ cnt);
+ goto lcd_prbs_test_err;
+ }
+ }
+
+ lcd_ana_write(reg_phy_tx_ctrl0, 0);
+ lcd_ana_write(reg_phy_tx_ctrl1, 0);
+
+ if (lcd_prbs_mode == LCD_PRBS_MODE_LVDS) {
+ lcd_prbs_performed |= LCD_PRBS_MODE_LVDS;
+ lcd_prbs_err &= ~(LCD_PRBS_MODE_LVDS);
+ LCDPR("lvds prbs check ok\n");
+ } else if (lcd_prbs_mode == LCD_PRBS_MODE_VX1) {
+ lcd_prbs_performed |= LCD_PRBS_MODE_VX1;
+ lcd_prbs_err &= ~(LCD_PRBS_MODE_VX1);
+ LCDPR("vx1 prbs check ok\n");
+ } else {
+ LCDPR("prbs check: unsupport mode\n");
+ }
+ continue;
+
+lcd_prbs_test_err:
+ if (lcd_prbs_mode == LCD_PRBS_MODE_LVDS) {
+ lcd_prbs_performed |= LCD_PRBS_MODE_LVDS;
+ lcd_prbs_err |= LCD_PRBS_MODE_LVDS;
+ } else if (lcd_prbs_mode == LCD_PRBS_MODE_VX1) {
+ lcd_prbs_performed |= LCD_PRBS_MODE_VX1;
+ lcd_prbs_err |= LCD_PRBS_MODE_VX1;
+ }
+ }
+
+lcd_prbs_test_end:
+ lcd_ana_setb(reg_phy_tx_ctrl0, 0, 12, 2);
+
+ printf("\n[lcd prbs result]:\n");
+ printf(" lvds prbs performed: %d, error: %d\n"
+ " vx1 prbs performed: %d, error: %d\n",
+ (lcd_prbs_performed & LCD_PRBS_MODE_LVDS) ? 1 : 0,
+ (lcd_prbs_err & LCD_PRBS_MODE_LVDS) ? 1 : 0,
+ (lcd_prbs_performed & LCD_PRBS_MODE_VX1) ? 1 : 0,
+ (lcd_prbs_err & LCD_PRBS_MODE_VX1) ? 1 : 0);
+
+ return 0;
+}
+
+static int lcd_prbs_test_t7(struct aml_lcd_drv_s *pdrv, unsigned int s, unsigned int mode_flag)
+{
+ struct lcd_clk_config_s *cconf;
+ unsigned int reg_phy_tx_ctrl0, reg_phy_tx_ctrl1, reg_ctrl_out, bit_width;
+ int encl_msr_id, fifo_msr_id;
+ unsigned int lcd_prbs_mode;
+ unsigned int val1, val2, timeout;
+ unsigned int cnt = 0;
+ unsigned int clk_err_cnt = 0;
+ int i, j, ret;
+
+ cconf = get_lcd_clk_config(pdrv);
+ if (!cconf)
+ return -1;
+
+ switch (pdrv->index) {
+ case 0:
+ reg_phy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0;
+ reg_phy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1;
+ reg_ctrl_out = COMBO_DPHY_RO_EDP_LVDS_TX_PHY0_CNTL1;
+ bit_width = 8;
+ break;
+ case 1:
+ reg_phy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL0;
+ reg_phy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL1;
+ reg_ctrl_out = COMBO_DPHY_RO_EDP_LVDS_TX_PHY1_CNTL1;
+ bit_width = 8;
+ break;
+ case 2:
+ reg_phy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL0;
+ reg_phy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL1;
+ reg_ctrl_out = COMBO_DPHY_RO_EDP_LVDS_TX_PHY2_CNTL1;
+ bit_width = 10;
+ break;
+ default:
+ LCDERR("[%d]: %s: invalid drv_index\n",
+ pdrv->index, __func__);
+ return -1;
+ }
+ encl_msr_id = cconf->data->enc_clk_msr_id;
+ fifo_msr_id = -1;
+
+ s = (s == 0) ? 1 : ((s > 1800) ? 1800 : s);
+ timeout = s * 200;
+ for (i = 0; i < LCD_PRBS_MODE_MAX; i++) {
+ if ((mode_flag & (1 << i)) == 0)
+ continue;
+
+ lcd_combo_dphy_write(reg_phy_tx_ctrl0, 0);
+ lcd_combo_dphy_write(reg_phy_tx_ctrl1, 0);
+
+ cnt = 0;
+ clk_err_cnt = 0;
+ lcd_prbs_mode = (1 << i);
+ LCDPR("[%d]: lcd_prbs_mode: %d\n", pdrv->index, lcd_prbs_mode);
+ if (lcd_prbs_mode == LCD_PRBS_MODE_LVDS) {
+ lcd_encl_clk_check_std = 136;
+ lcd_fifo_clk_check_std = 48;
+ } else if (lcd_prbs_mode == LCD_PRBS_MODE_VX1) {
+ lcd_encl_clk_check_std = 594;
+ lcd_fifo_clk_check_std = 297;
+ }
+ if (!cconf->data->prbs_clk_config) {
+ LCDERR("[%d]: %s: prbs_clk_config is null\n",
+ pdrv->index, __func__);
+ goto lcd_prbs_test_t7_end;
+
+ }
+ cconf->data->prbs_clk_config(pdrv, lcd_prbs_mode);
+ mdelay(20);
+
+ /* set fifo_clk_sel: div 10 */
+ lcd_combo_dphy_write(reg_phy_tx_ctrl0, (3 << 5));
+ /* set cntl_ser_en: 8-channel to 1 */
+ lcd_combo_dphy_setb(reg_phy_tx_ctrl0, 0x3ff, 16, 10);
+ /* decoupling fifo enable, gated clock enable */
+ lcd_combo_dphy_write(reg_phy_tx_ctrl1, (1 << 6) | (1 << 0));
+ /* decoupling fifo write enable after fifo enable */
+ lcd_combo_dphy_setb(reg_phy_tx_ctrl1, 1, 7, 1);
+ /* prbs_err en */
+ lcd_combo_dphy_setb(reg_phy_tx_ctrl0, 1, 12, 1);
+
+ while (cnt++ < timeout) {
+ val1 = lcd_combo_dphy_getb(reg_ctrl_out, bit_width, bit_width);
+ mdelay(5);
+ ret = 1;
+ for (j = 0; j < 10; j++) {
+ val2 = lcd_combo_dphy_getb(reg_ctrl_out, bit_width, bit_width);
+ if (val2 != val1) {
+ ret = 0;
+ break;
+ }
+ }
+ if (ret) {
+ LCDERR("[%d]: prbs check error 1, val:0x%03x, cnt:%d\n",
+ pdrv->index, val2, cnt);
+ goto lcd_prbs_test_t7_err;
+ }
+ if (lcd_combo_dphy_getb(reg_ctrl_out, 0, bit_width)) {
+ LCDERR("[%d]: prbs check error 2, cnt:%d\n",
+ pdrv->index, cnt);
+ goto lcd_prbs_test_t7_err;
+ }
+ if (lcd_prbs_clk_check(lcd_encl_clk_check_std, encl_msr_id,
+ lcd_fifo_clk_check_std, fifo_msr_id,
+ cnt))
+ clk_err_cnt++;
+ else
+ clk_err_cnt = 0;
+ if (clk_err_cnt >= 10) {
+ LCDERR("[%d]: prbs check error 3(clkmsr), cnt:%d\n",
+ pdrv->index, cnt);
+ goto lcd_prbs_test_t7_err;
+ }
+ }
+
+ lcd_combo_dphy_write(reg_phy_tx_ctrl0, 0);
+ lcd_combo_dphy_write(reg_phy_tx_ctrl1, 0);
+
+ if (lcd_prbs_mode == LCD_PRBS_MODE_LVDS) {
+ lcd_prbs_performed |= LCD_PRBS_MODE_LVDS;
+ lcd_prbs_err &= ~(LCD_PRBS_MODE_LVDS);
+ LCDPR("[%d]: lvds prbs check ok\n", pdrv->index);
+ } else if (lcd_prbs_mode == LCD_PRBS_MODE_VX1) {
+ lcd_prbs_performed |= LCD_PRBS_MODE_VX1;
+ lcd_prbs_err &= ~(LCD_PRBS_MODE_VX1);
+ LCDPR("[%d]: vx1 prbs check ok\n", pdrv->index);
+ } else {
+ LCDPR("[%d]: prbs check: unsupport mode\n", pdrv->index);
+ }
+ continue;
+
+lcd_prbs_test_t7_err:
+ if (lcd_prbs_mode == LCD_PRBS_MODE_LVDS) {
+ lcd_prbs_performed |= LCD_PRBS_MODE_LVDS;
+ lcd_prbs_err |= LCD_PRBS_MODE_LVDS;
+ } else if (lcd_prbs_mode == LCD_PRBS_MODE_VX1) {
+ lcd_prbs_performed |= LCD_PRBS_MODE_VX1;
+ lcd_prbs_err |= LCD_PRBS_MODE_VX1;
+ }
+ }
+
+lcd_prbs_test_t7_end:
+ lcd_combo_dphy_setb(reg_phy_tx_ctrl0, 0, 12, 2);
+
+ printf("\n[[%d]: lcd prbs result]:\n", pdrv->index);
+ printf(" lvds prbs performed: %d, error: %d\n"
+ " vx1 prbs performed: %d, error: %d\n",
+ (lcd_prbs_performed & LCD_PRBS_MODE_LVDS) ? 1 : 0,
+ (lcd_prbs_err & LCD_PRBS_MODE_LVDS) ? 1 : 0,
+ (lcd_prbs_performed & LCD_PRBS_MODE_VX1) ? 1 : 0,
+ (lcd_prbs_err & LCD_PRBS_MODE_VX1) ? 1 : 0);
+
+ return 0;
+}
+
+int lcd_prbs_test(struct aml_lcd_drv_s *pdrv, unsigned int s, unsigned int mode_flag)
+{
+ struct lcd_debug_info_reg_s *info_reg;
+ int ret = -1;
+
+ info_reg = (struct lcd_debug_info_reg_s *)pdrv->debug_info_reg;
+ if (info_reg && info_reg->prbs_test)
+ ret = info_reg->prbs_test(pdrv, s, mode_flag);
+ else
+ LCDERR("[%d]: %s: don't support prbs test\n", pdrv->index, __func__);
+
+ return ret;
+}
+
+void lcd_info_print(struct aml_lcd_drv_s *pdrv)
{
unsigned int lcd_clk;
unsigned int sync_duration;
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
struct lcd_config_s *pconf;
+ struct lcd_debug_info_if_s *info_if;
- pconf = lcd_drv->lcd_config;
- LCDPR("driver version: %s\n", lcd_drv->version);
- LCDPR("key_valid: %d\n", pconf->lcd_key_valid);
+ pconf = &pdrv->config;
+ LCDPR("[%d]: lcd driver version: %s\n", pdrv->index, LCD_DRV_VERSION);
+ LCDPR("key_valid: %d\n", pdrv->key_valid);
LCDPR("mode: %s, status: %d\n",
- lcd_mode_mode_to_str(pconf->lcd_mode),
- lcd_drv->lcd_status);
+ lcd_mode_mode_to_str(pdrv->mode), pdrv->status);
- lcd_clk = (pconf->lcd_timing.lcd_clk / 1000);
- sync_duration = pconf->lcd_timing.sync_duration_num;
- sync_duration = (sync_duration * 10 / pconf->lcd_timing.sync_duration_den);
- LCDPR("%s, %s %ubit, %ux%u@%u.%uHz\n"
+ lcd_clk = (pconf->timing.lcd_clk / 1000);
+ sync_duration = pconf->timing.sync_duration_num;
+ sync_duration = (sync_duration * 100 / pconf->timing.sync_duration_den);
+ LCDPR("%s, %s %ubit, %ux%u@%u.%02uHz\n"
"fr_adj_type %d\n"
"lcd_clk %u.%03uMHz\n"
"ss_level %u\n\n",
- pconf->lcd_basic.model_name,
- lcd_type_type_to_str(pconf->lcd_basic.lcd_type),
- pconf->lcd_basic.lcd_bits,
- pconf->lcd_basic.h_active, pconf->lcd_basic.v_active,
- (sync_duration / 10), (sync_duration % 10),
- pconf->lcd_timing.fr_adjust_type,
+ pconf->basic.model_name,
+ lcd_type_type_to_str(pconf->basic.lcd_type),
+ pconf->basic.lcd_bits,
+ pconf->basic.h_active, pconf->basic.v_active,
+ (sync_duration / 100), (sync_duration % 100),
+ pconf->timing.fr_adjust_type,
(lcd_clk / 1000), (lcd_clk % 1000),
- pconf->lcd_timing.ss_level);
+ pconf->timing.ss_level);
lcd_timing_info_print(pconf);
- if (lcd_debug_info_if) {
- if (lcd_debug_info_if->interface_print)
- lcd_debug_info_if->interface_print(pconf);
+ info_if = (struct lcd_debug_info_if_s *)pdrv->debug_info_if;
+ if (info_if) {
+ if (info_if->interface_print)
+ info_if->interface_print(pconf);
else
LCDERR("%s: interface_print is null\n", __func__);
} else {
LCDERR("%s: lcd_debug_info_if is null\n", __func__);
}
- lcd_power_info_print(lcd_drv, 1);
- lcd_power_info_print(lcd_drv, 0);
- lcd_cpu_gpio_info_print();
+ lcd_power_info_print(pdrv, 1);
+ lcd_power_info_print(pdrv, 0);
+
+ lcd_gpio_info_print(pdrv);
}
-void lcd_reg_print(void)
+void lcd_reg_print(struct aml_lcd_drv_s *pdrv)
{
- int i = 0;
+ struct lcd_debug_info_reg_s *info_reg;
+ struct lcd_debug_info_if_s *info_if;
unsigned int *table;
+ int i = 0;
- if (lcd_debug_info_reg) {
- if (lcd_debug_info_reg->reg_clk_table) {
- table = lcd_debug_info_reg->reg_clk_table;
- while (i < LCD_DEBUG_REG_CNT_MAX) {
- if (table[i] == LCD_DEBUG_REG_END)
- break;
- printf("hiu [0x%08x] = 0x%08x\n",
- table[i], lcd_hiu_read(table[i]));
- i++;
- }
- } else {
- LCDERR("%s: reg_clk_table is null\n", __func__);
- }
+ info_reg = (struct lcd_debug_info_reg_s *)pdrv->debug_info_reg;
+ info_if = (struct lcd_debug_info_if_s *)pdrv->debug_info_if;
- if (lcd_debug_info_reg->reg_encl_table) {
- printf("\nencl regs:\n");
- table = lcd_debug_info_reg->reg_encl_table;
- i = 0;
- while (i < LCD_DEBUG_REG_CNT_MAX) {
- if (table[i] == LCD_DEBUG_REG_END)
- break;
- printf("vcbus [0x%04x] = 0x%08x\n",
- table[i], lcd_vcbus_read(table[i]));
- i++;
- }
- } else {
- LCDERR("%s: reg_encl_table is null\n", __func__);
- }
-
- if (lcd_debug_info_reg->reg_pinmux_table) {
- printf("\npinmux regs:\n");
- table = lcd_debug_info_reg->reg_pinmux_table;
- i = 0;
- while (i < LCD_DEBUG_REG_CNT_MAX) {
- if (table[i] == LCD_DEBUG_REG_END)
- break;
- printf("PERIPHS_PIN_MUX [0x%08x] = 0x%08x\n",
- table[i], lcd_periphs_read(table[i]));
- i++;
- }
- }
- } else {
+ if (!info_reg) {
LCDERR("%s: lcd_debug_info_reg is null\n", __func__);
+ goto lcd_reg_print_next;
+ }
+ LCDPR("[%d]: lcd regs:\n", pdrv->index);
+ if (info_reg->reg_pll_table) {
+ table = info_reg->reg_pll_table;
+ i = 0;
+ while (i < LCD_DEBUG_REG_CNT_MAX) {
+ if (table[i] == LCD_DEBUG_REG_END)
+ break;
+ printf("pll [0x%08x] = 0x%08x\n",
+ table[i], lcd_ana_read(table[i]));
+ i++;
+ }
+ }
+ if (info_reg->reg_clk_table) {
+ table = info_reg->reg_clk_table;
+ i = 0;
+ while (i < LCD_DEBUG_REG_CNT_MAX) {
+ if (table[i] == LCD_DEBUG_REG_END)
+ break;
+ printf("clk [0x%08x] = 0x%08x\n",
+ table[i], lcd_clk_read(table[i]));
+ i++;
+ }
}
- if (lcd_debug_info_if) {
- if (lcd_debug_info_if->reg_dump_interface)
- lcd_debug_info_if->reg_dump_interface();
- else
- LCDERR("%s: reg_dump_interface is null\n", __func__);
+ if (info_reg->reg_encl_table) {
+ printf("\nencl regs:\n");
+ table = info_reg->reg_encl_table;
+ i = 0;
+ while (i < LCD_DEBUG_REG_CNT_MAX) {
+ if (table[i] == LCD_DEBUG_REG_END)
+ break;
+ printf("vcbus [0x%04x] = 0x%08x\n",
+ table[i], lcd_vcbus_read(table[i]));
+ i++;
+ }
+ }
- if (lcd_debug_info_if->reg_dump_phy)
- lcd_debug_info_if->reg_dump_phy();
- } else {
+ if (info_reg->reg_pinmux_table) {
+ printf("\npinmux regs:\n");
+ table = info_reg->reg_pinmux_table;
+ i = 0;
+ while (i < LCD_DEBUG_REG_CNT_MAX) {
+ if (table[i] == LCD_DEBUG_REG_END)
+ break;
+ printf("PERIPHS_PIN_MUX [0x%08x] = 0x%08x\n",
+ table[i], lcd_periphs_read(table[i]));
+ i++;
+ }
+ }
+
+lcd_reg_print_next:
+ if (!info_if) {
LCDERR("%s: lcd_debug_info_if is null\n", __func__);
+ return;
}
+ if (info_if->reg_dump_interface)
+ info_if->reg_dump_interface(pdrv);
+
+ if (info_if->reg_dump_phy)
+ info_if->reg_dump_phy(pdrv);
+}
+
+void lcd_vbyone_rst(struct aml_lcd_drv_s *pdrv)
+{
+ unsigned int offset;
+
+ offset = pdrv->data->offset_venc_if[pdrv->index];
+
+ /* realease PHY */
+ if (lcd_vcbus_read(VBO_INSGN_CTRL + offset) & 0x1) {
+ LCDPR("[%d]: clr force lockn input\n", pdrv->index);
+ lcd_vcbus_setb(VBO_INSGN_CTRL + offset, 0, 0, 1);
+ }
+ lcd_vbyone_sw_reset(pdrv);
+ LCDPR("[%d]: vbyone reset\n", pdrv->index);
+}
+
+void lcd_vbyone_cdr(struct aml_lcd_drv_s *pdrv)
+{
+ unsigned int offset;
+
+ offset = pdrv->data->offset_venc_if[pdrv->index];
+
+ /*[5:0]: vx1 fsm status*/
+ lcd_vcbus_setb(VBO_INSGN_CTRL + offset, 7, 0, 4);
+ mdelay(100);
+ LCDPR("[%d]: vbyone fsm status: 0x%08x\n",
+ pdrv->index, lcd_vcbus_read(VBO_STATUS_L + offset));
}
/* **********************************
@@ -689,15 +1428,51 @@
*/
/* chip_type data */
static struct lcd_debug_info_reg_s lcd_debug_info_reg_g12a_clk_path0 = {
+ .reg_pll_table = NULL,
.reg_clk_table = lcd_reg_dump_clk_hpll_g12a,
.reg_encl_table = lcd_reg_dump_encl_dft,
.reg_pinmux_table = NULL,
+ .prbs_test = NULL,
};
static struct lcd_debug_info_reg_s lcd_debug_info_reg_g12a_clk_path1 = {
+ .reg_pll_table = NULL,
.reg_clk_table = lcd_reg_dump_clk_gp0_g12a,
.reg_encl_table = lcd_reg_dump_encl_dft,
.reg_pinmux_table = NULL,
+ .prbs_test = NULL,
+};
+
+static struct lcd_debug_info_reg_s lcd_debug_info_reg_tl1 = {
+ .reg_pll_table = NULL,
+ .reg_clk_table = lcd_reg_dump_clk_tl1,
+ .reg_encl_table = lcd_reg_dump_encl_tl1,
+ .reg_pinmux_table = lcd_reg_dump_pinmux_tl1,
+ .prbs_test = lcd_prbs_test_tl1,
+};
+
+static struct lcd_debug_info_reg_s lcd_debug_info_reg_t7_0 = {
+ .reg_pll_table = lcd_reg_dump_pll_t7_0,
+ .reg_clk_table = lcd_reg_dump_clk_t7_0,
+ .reg_encl_table = lcd_reg_dump_encl_t7_0,
+ .reg_pinmux_table = lcd_reg_dump_pinmux_t7,
+ .prbs_test = lcd_prbs_test_t7,
+};
+
+static struct lcd_debug_info_reg_s lcd_debug_info_reg_t7_1 = {
+ .reg_pll_table = lcd_reg_dump_pll_t7_1,
+ .reg_clk_table = lcd_reg_dump_clk_t7_1,
+ .reg_encl_table = lcd_reg_dump_encl_t7_1,
+ .reg_pinmux_table = lcd_reg_dump_pinmux_t7,
+ .prbs_test = lcd_prbs_test_t7,
+};
+
+static struct lcd_debug_info_reg_s lcd_debug_info_reg_t7_2 = {
+ .reg_pll_table = lcd_reg_dump_pll_t7_2,
+ .reg_clk_table = lcd_reg_dump_clk_t7_2,
+ .reg_encl_table = lcd_reg_dump_encl_t7_2,
+ .reg_pinmux_table = lcd_reg_dump_pinmux_t7,
+ .prbs_test = lcd_prbs_test_t7,
};
/* interface data */
@@ -725,23 +1500,76 @@
.reg_dump_phy = lcd_reg_print_mipi_phy_analog,
};
+static struct lcd_debug_info_if_s lcd_debug_info_if_edp = {
+ .interface_print = lcd_info_print_edp,
+ .reg_dump_interface = lcd_reg_print_edp,
+ .reg_dump_phy = lcd_reg_print_phy_analog_t7,
+};
+
+#ifdef CONFIG_AML_LCD_TCON
static struct lcd_debug_info_if_s lcd_debug_info_if_mlvds = {
.interface_print = lcd_info_print_mlvds,
- .reg_dump_interface = lcd_reg_print_mlvds,
+ .reg_dump_interface = lcd_reg_print_tcon,
.reg_dump_phy = lcd_reg_print_phy_analog,
};
-void lcd_debug_probe(struct aml_lcd_drv_s *lcd_drv)
+static struct lcd_debug_info_if_s lcd_debug_info_if_p2p = {
+ .interface_print = lcd_info_print_p2p,
+ .reg_dump_interface = lcd_reg_print_tcon_tl1,
+ .reg_dump_phy = lcd_reg_print_phy_analog,
+};
+#endif
+
+void lcd_debug_probe(struct aml_lcd_drv_s *pdrv)
{
- int lcd_type;
+ struct lcd_debug_info_reg_s *lcd_debug_info_reg = NULL;
+ struct lcd_debug_info_if_s *lcd_debug_info_if = NULL;
- lcd_type = lcd_drv->lcd_config->lcd_basic.lcd_type;
-
- switch (lcd_drv->chip_type) {
+ switch (pdrv->data->chip_type) {
+ case LCD_CHIP_T7:
+ switch (pdrv->index) {
+ case 1:
+ lcd_debug_info_reg = &lcd_debug_info_reg_t7_1;
+ break;
+ case 2:
+ lcd_debug_info_reg = &lcd_debug_info_reg_t7_2;
+ break;
+ case 0:
+ default:
+ lcd_debug_info_reg = &lcd_debug_info_reg_t7_0;
+ break;
+ }
+ lcd_debug_info_if_lvds.reg_dump_phy =
+ lcd_reg_print_phy_analog_t7;
+ lcd_debug_info_if_vbyone.reg_dump_phy =
+ lcd_reg_print_phy_analog_t7;
+ lcd_debug_info_if_mipi.reg_dump_phy =
+ lcd_reg_print_phy_analog_t7;
+ break;
+ case LCD_CHIP_TL1:
+ case LCD_CHIP_TM2:
+ case LCD_CHIP_T5:
+ case LCD_CHIP_T5D:
+ lcd_debug_info_reg = &lcd_debug_info_reg_tl1;
+ lcd_debug_info_if_lvds.reg_dump_phy =
+ lcd_reg_print_phy_analog_tl1;
+ lcd_debug_info_if_mipi.reg_dump_phy =
+ lcd_reg_print_phy_analog_tl1;
+#ifdef CONFIG_AML_LCD_TCON
+ lcd_debug_info_if_mlvds.reg_dump_interface =
+ lcd_reg_print_tcon_tl1;
+ lcd_debug_info_if_mlvds.reg_dump_phy =
+ lcd_reg_print_phy_analog_tl1;
+ lcd_debug_info_if_p2p.reg_dump_interface =
+ lcd_reg_print_tcon_tl1;
+ lcd_debug_info_if_p2p.reg_dump_phy =
+ lcd_reg_print_phy_analog_tl1;
+#endif
+ break;
case LCD_CHIP_G12A:
case LCD_CHIP_G12B:
case LCD_CHIP_SM1:
- if (lcd_drv->lcd_config->lcd_clk_path)
+ if (pdrv->clk_path)
lcd_debug_info_reg = &lcd_debug_info_reg_g12a_clk_path1;
else
lcd_debug_info_reg = &lcd_debug_info_reg_g12a_clk_path0;
@@ -751,7 +1579,7 @@
break;
}
- switch (lcd_type) {
+ switch (pdrv->config.basic.lcd_type) {
case LCD_TTL:
lcd_debug_info_if = &lcd_debug_info_if_ttl;
break;
@@ -764,11 +1592,22 @@
case LCD_MIPI:
lcd_debug_info_if = &lcd_debug_info_if_mipi;
break;
+ case LCD_EDP:
+ lcd_debug_info_if = &lcd_debug_info_if_edp;
+ break;
+#ifdef CONFIG_AML_LCD_TCON
case LCD_MLVDS:
lcd_debug_info_if = &lcd_debug_info_if_mlvds;
break;
+ case LCD_P2P:
+ lcd_debug_info_if = &lcd_debug_info_if_p2p;
+ break;
+#endif
default:
lcd_debug_info_if = NULL;
break;
}
+
+ pdrv->debug_info_reg = (void *)lcd_debug_info_reg;
+ pdrv->debug_info_if = (void *)lcd_debug_info_if;
}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_debug.h b/drivers/amlogic/media/vout/lcd/lcd_debug.h
index b1e058f..9326061 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_debug.h
+++ b/drivers/amlogic/media/vout/lcd/lcd_debug.h
@@ -1,40 +1,28 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * driver/amlogic/media/vout/lcd/lcd_debug.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef _AML_LCD_DEBUG_H
#define _AML_LCD_DEBUG_H
+#include <amlogic/media/vout/lcd/lcd_vout.h>
#include "lcd_reg.h"
#define LCD_DEBUG_REG_CNT_MAX 30
#define LCD_DEBUG_REG_END 0xffffffff
struct lcd_debug_info_reg_s {
+ unsigned int *reg_pll_table;
unsigned int *reg_clk_table;
unsigned int *reg_encl_table;
unsigned int *reg_pinmux_table;
+ int (*prbs_test)(struct aml_lcd_drv_s *pdrv, unsigned int s, unsigned int mode_flag);
};
struct lcd_debug_info_if_s {
void (*interface_print)(struct lcd_config_s *pconf);
- void (*reg_dump_interface)(void);
- void (*reg_dump_phy)(void);
+ void (*reg_dump_interface)(struct aml_lcd_drv_s *pdrv);
+ void (*reg_dump_phy)(struct aml_lcd_drv_s *pdrv);
};
static unsigned int lcd_reg_dump_clk_gp0_g12a[] = {
@@ -49,7 +37,7 @@
HHI_VIID_CLK_CNTL,
HHI_VID_CLK_CNTL2,
HHI_MIPIDSI_PHY_CLK_CNTL,
- LCD_DEBUG_REG_END,
+ LCD_DEBUG_REG_END
};
static unsigned int lcd_reg_dump_clk_hpll_g12a[] = {
@@ -65,7 +53,71 @@
HHI_VIID_CLK_CNTL,
HHI_VID_CLK_CNTL2,
HHI_MIPIDSI_PHY_CLK_CNTL,
- LCD_DEBUG_REG_END,
+ LCD_DEBUG_REG_END
+};
+
+static unsigned int lcd_reg_dump_clk_tl1[] = {
+ HHI_TCON_PLL_CNTL0,
+ HHI_TCON_PLL_CNTL1,
+ HHI_TCON_PLL_CNTL2,
+ HHI_TCON_PLL_CNTL3,
+ HHI_TCON_PLL_CNTL4,
+ HHI_VID_PLL_CLK_DIV,
+ HHI_VIID_CLK_DIV,
+ HHI_VIID_CLK_CNTL,
+ HHI_VID_CLK_CNTL2,
+ LCD_DEBUG_REG_END
+};
+
+static unsigned int lcd_reg_dump_pll_t7_0[] = {
+ ANACTRL_TCON_PLL0_CNTL0,
+ ANACTRL_TCON_PLL0_CNTL1,
+ ANACTRL_TCON_PLL0_CNTL2,
+ ANACTRL_TCON_PLL0_CNTL3,
+ ANACTRL_TCON_PLL0_CNTL4,
+ ANACTRL_TCON_PLL0_STS,
+ LCD_DEBUG_REG_END
+};
+
+static unsigned int lcd_reg_dump_pll_t7_1[] = {
+ ANACTRL_TCON_PLL1_CNTL0,
+ ANACTRL_TCON_PLL1_CNTL1,
+ ANACTRL_TCON_PLL1_CNTL2,
+ ANACTRL_TCON_PLL1_CNTL3,
+ ANACTRL_TCON_PLL1_CNTL4,
+ ANACTRL_TCON_PLL1_STS,
+ LCD_DEBUG_REG_END
+};
+
+static unsigned int lcd_reg_dump_pll_t7_2[] = {
+ ANACTRL_TCON_PLL2_CNTL0,
+ ANACTRL_TCON_PLL2_CNTL1,
+ ANACTRL_TCON_PLL2_CNTL2,
+ ANACTRL_TCON_PLL2_CNTL3,
+ ANACTRL_TCON_PLL2_CNTL4,
+ ANACTRL_TCON_PLL2_STS,
+ LCD_DEBUG_REG_END
+};
+
+static unsigned int lcd_reg_dump_clk_t7_0[] = {
+ CLKCTRL_VIID_CLK0_DIV,
+ CLKCTRL_VIID_CLK0_CTRL,
+ CLKCTRL_VID_CLK0_CTRL2,
+ LCD_DEBUG_REG_END
+};
+
+static unsigned int lcd_reg_dump_clk_t7_1[] = {
+ CLKCTRL_VIID_CLK1_DIV,
+ CLKCTRL_VIID_CLK1_CTRL,
+ CLKCTRL_VID_CLK1_CTRL2,
+ LCD_DEBUG_REG_END
+};
+
+static unsigned int lcd_reg_dump_clk_t7_2[] = {
+ CLKCTRL_VIID_CLK2_DIV,
+ CLKCTRL_VIID_CLK2_CTRL,
+ CLKCTRL_VID_CLK2_CTRL2,
+ LCD_DEBUG_REG_END
};
static unsigned int lcd_reg_dump_encl_dft[] = {
@@ -91,7 +143,137 @@
L_RGB_COEFF_ADDR,
L_POL_CNTL_ADDR,
L_DITH_CNTL_ADDR,
- LCD_DEBUG_REG_END,
+ LCD_DEBUG_REG_END
+};
+
+static unsigned int lcd_reg_dump_encl_tl1[] = {
+ VPU_VIU_VENC_MUX_CTRL,
+ ENCL_VIDEO_EN,
+ ENCL_VIDEO_MODE,
+ ENCL_VIDEO_MODE_ADV,
+ ENCL_VIDEO_MAX_PXCNT,
+ ENCL_VIDEO_MAX_LNCNT,
+ ENCL_VIDEO_HAVON_BEGIN,
+ ENCL_VIDEO_HAVON_END,
+ ENCL_VIDEO_VAVON_BLINE,
+ ENCL_VIDEO_VAVON_ELINE,
+ ENCL_VIDEO_HSO_BEGIN,
+ ENCL_VIDEO_HSO_END,
+ ENCL_VIDEO_VSO_BEGIN,
+ ENCL_VIDEO_VSO_END,
+ ENCL_VIDEO_VSO_BLINE,
+ ENCL_VIDEO_VSO_ELINE,
+ ENCL_VIDEO_RGBIN_CTRL,
+ ENCL_INBUF_CNTL0,
+ ENCL_INBUF_CNTL1,
+ L_GAMMA_CNTL_PORT,
+ L_RGB_BASE_ADDR,
+ L_RGB_COEFF_ADDR,
+ L_POL_CNTL_ADDR,
+ L_DITH_CNTL_ADDR,
+ LCD_DEBUG_REG_END
+};
+
+static unsigned int lcd_reg_dump_encl_t7_0[] = {
+ VPU_VIU_VENC_MUX_CTRL,
+ ENCL_VIDEO_EN,
+ ENCL_VIDEO_MODE,
+ ENCL_VIDEO_MODE_ADV,
+ ENCL_VIDEO_MAX_PXCNT,
+ ENCL_VIDEO_MAX_LNCNT,
+ ENCL_VIDEO_HAVON_BEGIN,
+ ENCL_VIDEO_HAVON_END,
+ ENCL_VIDEO_VAVON_BLINE,
+ ENCL_VIDEO_VAVON_ELINE,
+ ENCL_VIDEO_HSO_BEGIN,
+ ENCL_VIDEO_HSO_END,
+ ENCL_VIDEO_VSO_BEGIN,
+ ENCL_VIDEO_VSO_END,
+ ENCL_VIDEO_VSO_BLINE,
+ ENCL_VIDEO_VSO_ELINE,
+ ENCL_VIDEO_RGBIN_CTRL,
+ ENCL_INBUF_CNTL0,
+ ENCL_INBUF_CNTL1,
+ VPU_DISP_VIU0_CTRL,
+ VPU_VENC_CTRL,
+ LCD_GAMMA_CNTL_PORT0,
+ LCD_RGB_BASE_ADDR,
+ LCD_RGB_COEFF_ADDR,
+ LCD_POL_CNTL_ADDR,
+ LCD_DITH_CNTL_ADDR,
+ LCD_DEBUG_REG_END
+};
+
+static unsigned int lcd_reg_dump_encl_t7_1[] = {
+ VPU_VIU_VENC_MUX_CTRL,
+ ENCL_VIDEO_EN + (0x600 << 2),
+ ENCL_VIDEO_MODE + (0x600 << 2),
+ ENCL_VIDEO_MODE_ADV + (0x600 << 2),
+ ENCL_VIDEO_MAX_PXCNT + (0x600 << 2),
+ ENCL_VIDEO_MAX_LNCNT + (0x600 << 2),
+ ENCL_VIDEO_HAVON_BEGIN + (0x600 << 2),
+ ENCL_VIDEO_HAVON_END + (0x600 << 2),
+ ENCL_VIDEO_VAVON_BLINE + (0x600 << 2),
+ ENCL_VIDEO_VAVON_ELINE + (0x600 << 2),
+ ENCL_VIDEO_HSO_BEGIN + (0x600 << 2),
+ ENCL_VIDEO_HSO_END + (0x600 << 2),
+ ENCL_VIDEO_VSO_BEGIN + (0x600 << 2),
+ ENCL_VIDEO_VSO_END + (0x600 << 2),
+ ENCL_VIDEO_VSO_BLINE + (0x600 << 2),
+ ENCL_VIDEO_VSO_ELINE + (0x600 << 2),
+ ENCL_VIDEO_RGBIN_CTRL + (0x600 << 2),
+ ENCL_INBUF_CNTL0 + (0x600 << 2),
+ ENCL_INBUF_CNTL1 + (0x600 << 2),
+ VPU_DISP_VIU1_CTRL,
+ VPU_VENC_CTRL + (0x600 << 2),
+ LCD_GAMMA_CNTL_PORT0 + (0x100 << 2),
+ LCD_RGB_BASE_ADDR + (0x100 << 2),
+ LCD_RGB_COEFF_ADDR + (0x100 << 2),
+ LCD_POL_CNTL_ADDR + (0x100 << 2),
+ LCD_DITH_CNTL_ADDR + (0x100 << 2),
+ LCD_DEBUG_REG_END
+};
+
+static unsigned int lcd_reg_dump_encl_t7_2[] = {
+ VPU_VIU_VENC_MUX_CTRL,
+ ENCL_VIDEO_EN + (0x800 << 2),
+ ENCL_VIDEO_MODE + (0x800 << 2),
+ ENCL_VIDEO_MODE_ADV + (0x800 << 2),
+ ENCL_VIDEO_MAX_PXCNT + (0x800 << 2),
+ ENCL_VIDEO_MAX_LNCNT + (0x800 << 2),
+ ENCL_VIDEO_HAVON_BEGIN + (0x800 << 2),
+ ENCL_VIDEO_HAVON_END + (0x800 << 2),
+ ENCL_VIDEO_VAVON_BLINE + (0x800 << 2),
+ ENCL_VIDEO_VAVON_ELINE + (0x800 << 2),
+ ENCL_VIDEO_HSO_BEGIN + (0x800 << 2),
+ ENCL_VIDEO_HSO_END + (0x800 << 2),
+ ENCL_VIDEO_VSO_BEGIN + (0x800 << 2),
+ ENCL_VIDEO_VSO_END + (0x800 << 2),
+ ENCL_VIDEO_VSO_BLINE + (0x800 << 2),
+ ENCL_VIDEO_VSO_ELINE + (0x800 << 2),
+ ENCL_VIDEO_RGBIN_CTRL + (0x800 << 2),
+ ENCL_INBUF_CNTL0 + (0x800 << 2),
+ ENCL_INBUF_CNTL1 + (0x800 << 2),
+ VPU_DISP_VIU2_CTRL,
+ VPU_VENC_CTRL + (0x800 << 2),
+ LCD_GAMMA_CNTL_PORT0 + (0x200 << 2),
+ LCD_RGB_BASE_ADDR + (0x200 << 2),
+ LCD_RGB_COEFF_ADDR + (0x200 << 2),
+ LCD_POL_CNTL_ADDR + (0x200 << 2),
+ LCD_DITH_CNTL_ADDR + (0x200 << 2),
+ LCD_DEBUG_REG_END
+};
+
+static unsigned int lcd_reg_dump_pinmux_tl1[] = {
+ PERIPHS_PIN_MUX_7,
+ PERIPHS_PIN_MUX_8,
+ PERIPHS_PIN_MUX_9,
+ LCD_DEBUG_REG_END
+};
+
+static unsigned int lcd_reg_dump_pinmux_t7[] = {
+ PADCTRL_PIN_MUX_REGK,
+ LCD_DEBUG_REG_END
};
#endif
diff --git a/drivers/amlogic/media/vout/lcd/lcd_dummy_reg.h b/drivers/amlogic/media/vout/lcd/lcd_dummy_reg.h
index f974c5d..0f6cdf6 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_dummy_reg.h
+++ b/drivers/amlogic/media/vout/lcd/lcd_dummy_reg.h
@@ -1,5 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
-/******* dummy register *********/
#ifndef MIPI_DSI_REGISTER
#define REG_BASE_DSI_HOST (0xFFD00000L)
@@ -173,6 +176,339 @@
#define HHI_LVDS_TX_PHY_CNTL1 (0xff63c000 + (0xdf << 2))
#endif
+#ifndef HHI_DIF_CSI_PHY_CNTL10
+#define HHI_DIF_CSI_PHY_CNTL10 (0xff63c000 + (0x8e << 2))
+#endif
+#ifndef HHI_DIF_CSI_PHY_CNTL11
+#define HHI_DIF_CSI_PHY_CNTL11 (0xff63c000 + (0x8f << 2))
+#endif
+#ifndef HHI_DIF_CSI_PHY_CNTL12
+#define HHI_DIF_CSI_PHY_CNTL12 (0xff63c000 + (0x90 << 2))
+#endif
+#ifndef HHI_DIF_CSI_PHY_CNTL13
+#define HHI_DIF_CSI_PHY_CNTL13 (0xff63c000 + (0x91 << 2))
+#endif
+#ifndef HHI_DIF_CSI_PHY_CNTL14
+#define HHI_DIF_CSI_PHY_CNTL14 (0xff63c000 + (0x92 << 2))
+#endif
+#ifndef HHI_DIF_CSI_PHY_CNTL15
+#define HHI_DIF_CSI_PHY_CNTL15 (0xff63c000 + (0x93 << 2))
+#endif
+#ifndef HHI_DIF_CSI_PHY_CNTL16
+#define HHI_DIF_CSI_PHY_CNTL16 (0xff63c000 + (0xde << 2))
+#endif
+#ifndef HHI_DIF_CSI_PHY_CNTL6
+#define HHI_DIF_CSI_PHY_CNTL6 (0xff63c000 + (0xea << 2))
+#endif
+#ifndef HHI_DIF_CSI_PHY_CNTL7
+#define HHI_DIF_CSI_PHY_CNTL7 (0xff63c000 + (0xeb << 2))
+#endif
+#ifndef HHI_DIF_CSI_PHY_CNTL8
+#define HHI_DIF_CSI_PHY_CNTL8 (0xff63c000 + (0xec << 2))
+#endif
+#ifndef HHI_DIF_CSI_PHY_CNTL9
+#define HHI_DIF_CSI_PHY_CNTL9 (0xff63c000 + (0xed << 2))
+#endif
+
+#ifndef HHI_TCON_PLL_CNTL0
+#define HHI_TCON_PLL_CNTL0 (0xff63c000 + (0x020 << 2))
+#endif
+#ifndef HHI_TCON_PLL_CNTL1
+#define HHI_TCON_PLL_CNTL1 (0xff63c000 + (0x021 << 2))
+#endif
+#ifndef HHI_TCON_PLL_CNTL2
+#define HHI_TCON_PLL_CNTL2 (0xff63c000 + (0x022 << 2))
+#endif
+#ifndef HHI_TCON_PLL_CNTL3
+#define HHI_TCON_PLL_CNTL3 (0xff63c000 + (0x023 << 2))
+#endif
+#ifndef HHI_TCON_PLL_CNTL4
+#define HHI_TCON_PLL_CNTL4 (0xff63c000 + (0x0df << 2))
+#endif
+
+#ifndef ANACTRL_TCON_PLL0_CNTL0
+#define ANACTRL_TCON_PLL0_CNTL0 ((0x00e0 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_TCON_PLL0_CNTL1
+#define ANACTRL_TCON_PLL0_CNTL1 ((0x00e1 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_TCON_PLL0_CNTL2
+#define ANACTRL_TCON_PLL0_CNTL2 ((0x00e2 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_TCON_PLL0_CNTL3
+#define ANACTRL_TCON_PLL0_CNTL3 ((0x00e3 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_TCON_PLL0_CNTL4
+#define ANACTRL_TCON_PLL0_CNTL4 ((0x00e4 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_TCON_PLL1_CNTL0
+#define ANACTRL_TCON_PLL1_CNTL0 ((0x00e5 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_TCON_PLL1_CNTL1
+#define ANACTRL_TCON_PLL1_CNTL1 ((0x00e6 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_TCON_PLL1_CNTL2
+#define ANACTRL_TCON_PLL1_CNTL2 ((0x00e7 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_TCON_PLL1_CNTL3
+#define ANACTRL_TCON_PLL1_CNTL3 ((0x00e8 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_TCON_PLL1_CNTL4
+#define ANACTRL_TCON_PLL1_CNTL4 ((0x00e9 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_TCON_PLL2_CNTL0
+#define ANACTRL_TCON_PLL2_CNTL0 ((0x00ea << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_TCON_PLL2_CNTL1
+#define ANACTRL_TCON_PLL2_CNTL1 ((0x00eb << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_TCON_PLL2_CNTL2
+#define ANACTRL_TCON_PLL2_CNTL2 ((0x00ec << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_TCON_PLL2_CNTL3
+#define ANACTRL_TCON_PLL2_CNTL3 ((0x00ed << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_TCON_PLL2_CNTL4
+#define ANACTRL_TCON_PLL2_CNTL4 ((0x00ee << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_TCON_PLL0_STS
+#define ANACTRL_TCON_PLL0_STS ((0x00ef << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_TCON_PLL1_STS
+#define ANACTRL_TCON_PLL1_STS ((0x00f0 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_TCON_PLL2_STS
+#define ANACTRL_TCON_PLL2_STS ((0x00f1 << 2) + 0xfe008000)
+#endif
+
+#ifndef COMBO_DPHY_CNTL0
+#define COMBO_DPHY_CNTL0 ((0x0000 << 2) + 0xfe018000)
+#endif
+#ifndef COMBO_DPHY_CNTL1
+#define COMBO_DPHY_CNTL1 ((0x0001 << 2) + 0xfe018000)
+#endif
+#ifndef COMBO_DPHY_VID_PLL0_DIV
+#define COMBO_DPHY_VID_PLL0_DIV ((0x0002 << 2) + 0xfe018000)
+#endif
+#ifndef COMBO_DPHY_VID_PLL1_DIV
+#define COMBO_DPHY_VID_PLL1_DIV ((0x0003 << 2) + 0xfe018000)
+#endif
+#ifndef COMBO_DPHY_VID_PLL2_DIV
+#define COMBO_DPHY_VID_PLL2_DIV ((0x0004 << 2) + 0xfe018000)
+#endif
+#ifndef COMBO_DPHY_EDP_PIXEL_CLK_DIV
+#define COMBO_DPHY_EDP_PIXEL_CLK_DIV ((0x0005 << 2) + 0xfe018000)
+#endif
+#ifndef COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0
+#define COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0 ((0x0006 << 2) + 0xfe018000)
+#endif
+#ifndef COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL0
+#define COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL0 ((0x0007 << 2) + 0xfe018000)
+#endif
+#ifndef COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL0
+#define COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL0 ((0x0008 << 2) + 0xfe018000)
+#endif
+#ifndef COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1
+#define COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1 ((0x0009 << 2) + 0xfe018000)
+#endif
+#ifndef COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL1
+#define COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL1 ((0x000a << 2) + 0xfe018000)
+#endif
+#ifndef COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL1
+#define COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL1 ((0x000b << 2) + 0xfe018000)
+#endif
+#ifndef COMBO_DPHY_RO_EDP_LVDS_TX_PHY0_CNTL1
+#define COMBO_DPHY_RO_EDP_LVDS_TX_PHY0_CNTL1 ((0x0000 << 2) + 0xfe018000)
+#endif
+#ifndef COMBO_DPHY_RO_EDP_LVDS_TX_PHY1_CNTL1
+#define COMBO_DPHY_RO_EDP_LVDS_TX_PHY1_CNTL1 ((0x0011 << 2) + 0xfe018000)
+#endif
+#ifndef COMBO_DPHY_RO_EDP_LVDS_TX_PHY2_CNTL1
+#define COMBO_DPHY_RO_EDP_LVDS_TX_PHY2_CNTL1 ((0x0012 << 2) + 0xfe018000)
+#endif
+
+#ifndef ANACTRL_DIF_PHY_CNTL1
+#define ANACTRL_DIF_PHY_CNTL1 ((0x00c8 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL2
+#define ANACTRL_DIF_PHY_CNTL2 ((0x00c9 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL3
+#define ANACTRL_DIF_PHY_CNTL3 ((0x00ca << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL4
+#define ANACTRL_DIF_PHY_CNTL4 ((0x00cb << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL5
+#define ANACTRL_DIF_PHY_CNTL5 ((0x00cc << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL6
+#define ANACTRL_DIF_PHY_CNTL6 ((0x00cd << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL7
+#define ANACTRL_DIF_PHY_CNTL7 ((0x00ce << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL8
+#define ANACTRL_DIF_PHY_CNTL8 ((0x00cf << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL9
+#define ANACTRL_DIF_PHY_CNTL9 ((0x00d0 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL10
+#define ANACTRL_DIF_PHY_CNTL10 ((0x00d1 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL11
+#define ANACTRL_DIF_PHY_CNTL11 ((0x00d2 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL12
+#define ANACTRL_DIF_PHY_CNTL12 ((0x00d3 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL13
+#define ANACTRL_DIF_PHY_CNTL13 ((0x00d4 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL14
+#define ANACTRL_DIF_PHY_CNTL14 ((0x00d5 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL15
+#define ANACTRL_DIF_PHY_CNTL15 ((0x00d6 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL16
+#define ANACTRL_DIF_PHY_CNTL16 ((0x00d7 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL17
+#define ANACTRL_DIF_PHY_CNTL17 ((0x00d8 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL18
+#define ANACTRL_DIF_PHY_CNTL18 ((0x00d9 << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL19
+#define ANACTRL_DIF_PHY_CNTL19 ((0x00da << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL20
+#define ANACTRL_DIF_PHY_CNTL20 ((0x00db << 2) + 0xfe008000)
+#endif
+#ifndef ANACTRL_DIF_PHY_CNTL21
+#define ANACTRL_DIF_PHY_CNTL21 ((0x00dc << 2) + 0xfe008000)
+#endif
+
+#ifndef CLKCTRL_VIID_CLK0_DIV
+#define CLKCTRL_VIID_CLK0_DIV ((0x0033 << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_VIID_CLK0_CTRL
+#define CLKCTRL_VIID_CLK0_CTRL ((0x0034 << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_VID_CLK0_CTRL2
+#define CLKCTRL_VID_CLK0_CTRL2 ((0x0031 << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_VIID_CLK1_DIV
+#define CLKCTRL_VIID_CLK1_DIV ((0x0076 << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_VIID_CLK1_CTRL
+#define CLKCTRL_VIID_CLK1_CTRL ((0x0077 << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_VID_CLK1_CTRL2
+#define CLKCTRL_VID_CLK1_CTRL2 ((0x0074 << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_VIID_CLK2_DIV
+#define CLKCTRL_VIID_CLK2_DIV ((0x007b << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_VIID_CLK2_CTRL
+#define CLKCTRL_VIID_CLK2_CTRL ((0x007c << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_VID_CLK2_CTRL2
+#define CLKCTRL_VID_CLK2_CTRL2 ((0x0079 << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_VID_PLL_CLK0_DIV
+#define CLKCTRL_VID_PLL_CLK0_DIV ((0x0039 << 2) + 0xfe000000)
+#endif
+
+#ifndef CLKCTRL_MIPIDSI_PHY_CLK_CTRL
+#define CLKCTRL_MIPIDSI_PHY_CLK_CTRL ((0x0041 << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL
+#define CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL ((0x0080 << 2) + 0xfe000000)
+#endif
+
+#ifndef ENCL_VIDEO_H_PRE_DE_END
+#define ENCL_VIDEO_H_PRE_DE_END 0x1ccf
+#endif
+#ifndef ENCL_VIDEO_H_PRE_DE_BEGIN
+#define ENCL_VIDEO_H_PRE_DE_BEGIN 0x1cd0
+#endif
+#ifndef ENCL_VIDEO_V_PRE_DE_ELINE
+#define ENCL_VIDEO_V_PRE_DE_ELINE 0x1cd1
+#endif
+#ifndef ENCL_VIDEO_V_PRE_DE_BLINE
+#define ENCL_VIDEO_V_PRE_DE_BLINE 0x1cd2
+#endif
+#ifndef ENCL_INBUF_CNTL0
+#define ENCL_INBUF_CNTL0 0x1cd3
+#endif
+#ifndef ENCL_INBUF_CNTL1
+#define ENCL_INBUF_CNTL1 0x1cd4
+#endif
+#ifndef ENCL_INBUF_CNT
+#define ENCL_INBUF_CNT 0x1cd5
+#endif
+
+#ifndef VPU_VENC_CTRL
+#define VPU_VENC_CTRL ((0x1cef << 2) + 0xff000000)
+#endif
+#ifndef VPU_DISP_VIU0_CTRL
+#define VPU_DISP_VIU0_CTRL ((0x2786 << 2) + 0xff000000)
+#endif
+#ifndef VPU_DISP_VIU1_CTRL
+#define VPU_DISP_VIU1_CTRL ((0x2787 << 2) + 0xff000000)
+#endif
+#ifndef VPU_DISP_VIU2_CTRL
+#define VPU_DISP_VIU2_CTRL ((0x2788 << 2) + 0xff000000)
+#endif
+
+#ifndef VPU_VENCI_STAT
+#define VPU_VENCI_STAT ((0x1ceb << 2) + 0xff000000)
+#endif
+#ifndef VPU_VENCP_STAT
+#define VPU_VENCP_STAT ((0x1cec << 2) + 0xff000000)
+#endif
+#ifndef VPU_VENCL_STAT
+#define VPU_VENCL_STAT ((0x1ced << 2) + 0xff000000)
+#endif
+
+#ifndef LCD_RGB_BASE_ADDR
+#define LCD_RGB_BASE_ADDR ((0x14a5 << 2) + 0xff000000)
+#endif
+#ifndef LCD_RGB_COEFF_ADDR
+#define LCD_RGB_COEFF_ADDR ((0x14a6 << 2) + 0xff000000)
+#endif
+#ifndef LCD_POL_CNTL_ADDR
+#define LCD_POL_CNTL_ADDR ((0x14a7 << 2) + 0xff000000)
+#endif
+#ifndef LCD_DITH_CNTL_ADDR
+#define LCD_DITH_CNTL_ADDR ((0x14a8 << 2) + 0xff000000)
+#endif
+
+#ifndef VBO_INFILTER_CTRL
+#define VBO_INFILTER_CTRL 0x14f9
+#endif
+#ifndef VBO_INFILTER_TICK_PERIOD_L
+#define VBO_INFILTER_TICK_PERIOD_L 0x14f9
+#endif
+#ifndef VBO_INFILTER_TICK_PERIOD_H
+#define VBO_INFILTER_TICK_PERIOD_H 0x1477
+#endif
+
+#ifndef LCD_GAMMA_CNTL_PORT0
+#define LCD_GAMMA_CNTL_PORT0 ((0x14b4 << 2) + 0xff000000)
+#endif
+#ifndef LCD_GAMMA_DATA_PORT0
+#define LCD_GAMMA_DATA_PORT0 ((0x14b5 << 2) + 0xff000000)
+#endif
+#ifndef LCD_GAMMA_ADDR_PORT0
+#define LCD_GAMMA_ADDR_PORT0 ((0x14b6 << 2) + 0xff000000)
+#endif
+
+#define TCON_CORE_FLAG_LIC2 (0xff630000L + (0x00e << 2))
+
#ifndef REG_TCON_APB_BASE
#define REG_TCON_APB_BASE (0xFF600000L)
#define TCON_CORE_REG_START 0x0000
@@ -194,15 +530,64 @@
#define TCON_DDRIF_CTRL2 0x1011
#define TCON_INTR_MASKN 0x1022
#define TCON_INTR 0x1023 /* read only */
+#endif
+#ifndef TCON_AXI_OFST
+#define TCON_AXI_OFST 0x100c
+#endif
+#ifndef TCON_AXI_OFST0
#define TCON_AXI_OFST0 0x200c
+#endif
+#ifndef TCON_STATUS2
#define TCON_STATUS2 0x2012
+#endif
+#ifndef TCON_AXI_OFST1
#define TCON_AXI_OFST1 0x2013
+#endif
+#ifndef TCON_AXI_OFST2
#define TCON_AXI_OFST2 0x2014
+#endif
+#ifndef TCON_GPO_CTRL0
#define TCON_GPO_CTRL0 0x2015
+#endif
+#ifndef TCON_GPO_CTRL1
#define TCON_GPO_CTRL1 0x2016
+#endif
+#ifndef TCON_GPO_CTRL2
#define TCON_GPO_CTRL2 0x2017
#endif
+#ifndef TCON_INTR_WR
+#define TCON_INTR_WR 0x2020
+#endif
+#ifndef TCON_INTR_CLR
+#define TCON_INTR_CLR 0x2021
+#endif
+#ifndef TCON_INTR_MASKN
+#define TCON_INTR_MASKN 0x2022
+#endif
+#ifndef TCON_INTR_RO
+#define TCON_INTR_RO 0x2023
+#endif
+
+#ifndef P2P_CH_SWAP0
+#define P2P_CH_SWAP0 0x4200
+#endif
+#ifndef P2P_CH_SWAP1
+#define P2P_CH_SWAP1 0x4201
+#endif
+#ifndef P2P_BIT_REV
+#define P2P_BIT_REV ((0x1950 << 2) + 0xff000000)
+#endif
+
+#ifndef LVDS_CH_SWAP0
+#define LVDS_CH_SWAP0 0x14e1
+#endif
+#ifndef LVDS_CH_SWAP1
+#define LVDS_CH_SWAP1 0x14e2
+#endif
+#ifndef LVDS_CH_SWAP2
+#define LVDS_CH_SWAP2 0x14e3
+#endif
#ifndef HHI_DIF_TCON_CNTL0
#define HHI_DIF_TCON_CNTL0 (0xff63c000 + (0x3c << 2))
@@ -227,3 +612,361 @@
#define PWM_MISC_REG_EF ((0x6402 << 2) + 0xffd00000)
#endif
+#ifndef REG_BASE_CBUS
+#define REG_BASE_CBUS 0x1
+#endif
+
+#ifndef REG_BASE_VCBUS
+#define REG_BASE_VCBUS 0x2
+#endif
+
+#ifndef REG_BASE_DSI_HOST
+#define REG_BASE_DSI_HOST 0x3
+#endif
+
+#ifndef MIPI_DSI_BASE
+#define MIPI_DSI_BASE 0xfe074000L
+#endif
+#ifndef MIPI_DSI_B_BASE
+#define MIPI_DSI_B_BASE 0xfe072000L
+#endif
+#ifndef MIPI_DSI_PHY_BASE
+#define MIPI_DSI_PHY_BASE 0xfe014000L
+#endif
+#ifndef MIPI_DSI_B_PHY_BASE
+#define MIPI_DSI_B_PHY_BASE 0xfe016000L
+#endif
+#ifndef EDPTX0_BASE
+#define EDPTX0_BASE 0xfe0b0000L
+#endif
+#ifndef EDPTX1_BASE
+#define EDPTX1_BASE 0xfe0b2000L
+#endif
+
+#ifndef HHI_GP0_PLL_CNTL2
+#define HHI_GP0_PLL_CNTL2 0x4
+#endif
+
+#ifndef HHI_GP0_PLL_CNTL3
+#define HHI_GP0_PLL_CNTL3 0x4
+#endif
+
+#ifndef HHI_GP0_PLL_CNTL4
+#define HHI_GP0_PLL_CNTL4 0x4
+#endif
+
+#ifndef HHI_GP0_PLL_CNTL5
+#define HHI_GP0_PLL_CNTL5 0x4
+#endif
+
+#ifndef HHI_VIID_CLK_CNTL
+#define HHI_VIID_CLK_CNTL 0x4
+#endif
+
+#ifndef HHI_VIID_CLK_DIV
+#define HHI_VIID_CLK_DIV 0x4
+#endif
+
+#ifndef HHI_VID_PLL_CLK_DIV
+#define HHI_VID_PLL_CLK_DIV 0x4
+#endif
+
+#ifndef HHI_VID_CLK_CNTL2
+#define HHI_VID_CLK_CNTL2 0x4
+#endif
+
+#ifndef HHI_MIPI_CNTL0
+#define HHI_MIPI_CNTL0 0x4
+#endif
+
+#ifndef HHI_MIPI_CNTL1
+#define HHI_MIPI_CNTL1 0x4
+#endif
+
+#ifndef HHI_MIPI_CNTL2
+#define HHI_MIPI_CNTL2 0x4
+#endif
+
+#ifndef HHI_VDIN_MEAS_CLK_CNTL
+#define HHI_VDIN_MEAS_CLK_CNTL 0x4
+#endif
+
+#ifndef PWM_MISC_REG_AB
+#define PWM_MISC_REG_AB 0x6c02
+#endif
+
+#ifndef PWM_MISC_REG_CD
+#define PWM_MISC_REG_CD 0x6802
+#endif
+
+#ifndef PWM_MISC_REG_EF
+#define PWM_MISC_REG_EF 0x6402
+#endif
+
+#ifndef PWM_PWM_A
+#define PWM_PWM_A 0x6c00
+#endif
+
+#ifndef PWM_PWM_B
+#define PWM_PWM_B 0x6c01
+#endif
+
+#ifndef PWM_PWM_C
+#define PWM_PWM_C 0x6800
+#endif
+
+#ifndef PWM_PWM_D
+#define PWM_PWM_D 0x6801
+#endif
+
+#ifndef PWM_PWM_E
+#define PWM_PWM_E 0x6400
+#endif
+
+#ifndef PWM_PWM_F
+#define PWM_PWM_F 0x6401
+#endif
+
+#ifndef AO_PWM_PWM_A
+#define AO_PWM_PWM_A (0xff807000 + (0x000 << 2))
+#endif
+#ifndef AO_PWM_PWM_B
+#define AO_PWM_PWM_B (0xff807000 + (0x001 << 2))
+#endif
+#ifndef AO_PWM_MISC_REG_AB
+#define AO_PWM_MISC_REG_AB (0xff807000 + (0x002 << 2))
+#endif
+
+#ifndef PWMAB_PWM_A
+#define PWMAB_PWM_A ((0x0000 << 2) + 0xfe058000)
+#endif
+#ifndef PWMAB_PWM_B
+#define PWMAB_PWM_B ((0x0001 << 2) + 0xfe058000)
+#endif
+#ifndef PWMAB_MISC_REG_AB
+#define PWMAB_MISC_REG_AB ((0x0002 << 2) + 0xfe058000)
+#endif
+#ifndef PWMCD_PWM_A
+#define PWMCD_PWM_A ((0x0000 << 2) + 0xfe05a000)
+#endif
+#ifndef PWMCD_PWM_B
+#define PWMCD_PWM_B ((0x0001 << 2) + 0xfe05a000)
+#endif
+#ifndef PWMCD_MISC_REG_AB
+#define PWMCD_MISC_REG_AB ((0x0002 << 2) + 0xfe05a000)
+#endif
+#ifndef PWMEF_PWM_A
+#define PWMEF_PWM_A ((0x0000 << 2) + 0xfe05c000)
+#endif
+#ifndef PWMEF_PWM_B
+#define PWMEF_PWM_B ((0x0001 << 2) + 0xfe05c000)
+#endif
+#ifndef PWMEF_MISC_REG_AB
+#define PWMEF_MISC_REG_AB ((0x0002 << 2) + 0xfe05c000)
+#endif
+
+#ifndef PWM_AO_AB_PWM_A
+#define PWM_AO_AB_PWM_A ((0x0000 << 2) + 0xfe05e000)
+#endif
+#ifndef PWM_AO_AB_PWM_B
+#define PWM_AO_AB_PWM_B ((0x0001 << 2) + 0xfe05e000)
+#endif
+#ifndef PWM_AO_AB_MISC_REG_AB
+#define PWM_AO_AB_MISC_REG_AB ((0x0002 << 2) + 0xfe05e000)
+#endif
+#ifndef PWM_AO_CD_PWM_A
+#define PWM_AO_CD_PWM_A ((0x0000 << 2) + 0xfe060000)
+#endif
+#ifndef PWM_AO_CD_PWM_B
+#define PWM_AO_CD_PWM_B ((0x0001 << 2) + 0xfe060000)
+#endif
+#ifndef PWM_AO_CD_MISC_REG_AB
+#define PWM_AO_CD_MISC_REG_AB ((0x0002 << 2) + 0xfe060000)
+#endif
+#ifndef PWM_AO_EF_PWM_A
+#define PWM_AO_EF_PWM_A ((0x0000 << 2) + 0xfe030000)
+#endif
+#ifndef PWM_AO_EF_PWM_B
+#define PWM_AO_EF_PWM_B ((0x0001 << 2) + 0xfe030000)
+#endif
+#ifndef PWM_AO_EF_MISC_REG_AB
+#define PWM_AO_EF_MISC_REG_AB ((0x0002 << 2) + 0xfe030000)
+#endif
+#ifndef PWM_AO_GH_PWM_A
+#define PWM_AO_GH_PWM_A ((0x0000 << 2) + 0xfe032000)
+#endif
+#ifndef PWM_AO_GH_PWM_B
+#define PWM_AO_GH_PWM_B ((0x0001 << 2) + 0xfe032000)
+#endif
+#ifndef PWM_AO_GH_MISC_REG_AB
+#define PWM_AO_GH_MISC_REG_AB ((0x0002 << 2) + 0xfe032000)
+#endif
+#ifndef CLKCTRL_PWM_CLK_AB_CTRL
+#define CLKCTRL_PWM_CLK_AB_CTRL ((0x0060 << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_PWM_CLK_CD_CTRL
+#define CLKCTRL_PWM_CLK_CD_CTRL ((0x0061 << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_PWM_CLK_EF_CTRL
+#define CLKCTRL_PWM_CLK_EF_CTRL ((0x0062 << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_PWM_CLK_AO_AB_CTRL
+#define CLKCTRL_PWM_CLK_AO_AB_CTRL ((0x0068 << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_PWM_CLK_AO_CD_CTRL
+#define CLKCTRL_PWM_CLK_AO_CD_CTRL ((0x0069 << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_PWM_CLK_AO_EF_CTRL
+#define CLKCTRL_PWM_CLK_AO_EF_CTRL ((0x006a << 2) + 0xfe000000)
+#endif
+#ifndef CLKCTRL_PWM_CLK_AO_GH_CTRL
+#define CLKCTRL_PWM_CLK_AO_GH_CTRL ((0x006b << 2) + 0xfe000000)
+#endif
+
+#ifndef PERIPHS_PIN_MUX_0
+#define PERIPHS_PIN_MUX_0 PADCTRL_PIN_MUX_REG0
+#endif
+
+#ifndef PERIPHS_PIN_MUX_7
+#define PERIPHS_PIN_MUX_7 0x5
+#endif
+
+#ifndef PERIPHS_PIN_MUX_8
+#define PERIPHS_PIN_MUX_8 0x5
+#endif
+
+#ifndef PERIPHS_PIN_MUX_9
+#define PERIPHS_PIN_MUX_9 0x5
+#endif
+
+#ifndef PADCTRL_PIN_MUX_REG0
+#define PADCTRL_PIN_MUX_REG0 ((0x0000 << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REG1
+#define PADCTRL_PIN_MUX_REG1 ((0x0001 << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REG2
+#define PADCTRL_PIN_MUX_REG2 ((0x0002 << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REG3
+#define PADCTRL_PIN_MUX_REG3 ((0x0003 << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REG4
+#define PADCTRL_PIN_MUX_REG4 ((0x0004 << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REG5
+#define PADCTRL_PIN_MUX_REG5 ((0x0005 << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REG6
+#define PADCTRL_PIN_MUX_REG6 ((0x0006 << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REG7
+#define PADCTRL_PIN_MUX_REG7 ((0x0007 << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REG8
+#define PADCTRL_PIN_MUX_REG8 ((0x0008 << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REG9
+#define PADCTRL_PIN_MUX_REG9 ((0x0009 << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REGA
+#define PADCTRL_PIN_MUX_REGA ((0x000a << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REGB
+#define PADCTRL_PIN_MUX_REGB ((0x000b << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REGC
+#define PADCTRL_PIN_MUX_REGC ((0x000c << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REGD
+#define PADCTRL_PIN_MUX_REGD ((0x000d << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REGE
+#define PADCTRL_PIN_MUX_REGE ((0x000e << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REGF
+#define PADCTRL_PIN_MUX_REGF ((0x000f << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REGG
+#define PADCTRL_PIN_MUX_REGG ((0x0010 << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REGH
+#define PADCTRL_PIN_MUX_REGH ((0x0011 << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REGI
+#define PADCTRL_PIN_MUX_REGI ((0x0012 << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REGJ
+#define PADCTRL_PIN_MUX_REGJ ((0x0013 << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REGK
+#define PADCTRL_PIN_MUX_REGK ((0x0014 << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REGL
+#define PADCTRL_PIN_MUX_REGL ((0x0015 << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REGM
+#define PADCTRL_PIN_MUX_REGM ((0x0016 << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REGN
+#define PADCTRL_PIN_MUX_REGN ((0x0017 << 2) + 0xfe004000)
+#endif
+#ifndef PADCTRL_PIN_MUX_REGO
+#define PADCTRL_PIN_MUX_REGO ((0x0018 << 2) + 0xfe004000)
+#endif
+
+#ifndef RESETCTRL_RESET0_LEVEL
+#define RESETCTRL_RESET0_LEVEL ((0x0010 << 2) + 0xfe002000)
+#endif
+#ifndef RESETCTRL_RESET1_LEVEL
+#define RESETCTRL_RESET1_LEVEL ((0x0011 << 2) + 0xfe002000)
+#endif
+#ifndef RESETCTRL_RESET2_LEVEL
+#define RESETCTRL_RESET2_LEVEL ((0x0012 << 2) + 0xfe002000)
+#endif
+#ifndef RESETCTRL_RESET3_LEVEL
+#define RESETCTRL_RESET3_LEVEL ((0x0013 << 2) + 0xfe002000)
+#endif
+#ifndef RESETCTRL_RESET4_LEVEL
+#define RESETCTRL_RESET4_LEVEL ((0x0014 << 2) + 0xfe002000)
+#endif
+#ifndef RESETCTRL_RESET5_LEVEL
+#define RESETCTRL_RESET5_LEVEL ((0x0015 << 2) + 0xfe002000)
+#endif
+#ifndef RESETCTRL_RESET6_LEVEL
+#define RESETCTRL_RESET6_LEVEL ((0x0016 << 2) + 0xfe002000)
+#endif
+#ifndef RESETCTRL_RESET0_MASK
+#define RESETCTRL_RESET0_MASK ((0x0020 << 2) + 0xfe002000)
+#endif
+#ifndef RESETCTRL_RESET1_MASK
+#define RESETCTRL_RESET1_MASK ((0x0021 << 2) + 0xfe002000)
+#endif
+#ifndef RESETCTRL_RESET2_MASK
+#define RESETCTRL_RESET2_MASK ((0x0022 << 2) + 0xfe002000)
+#endif
+#ifndef RESETCTRL_RESET3_MASK
+#define RESETCTRL_RESET3_MASK ((0x0023 << 2) + 0xfe002000)
+#endif
+#ifndef RESETCTRL_RESET4_MASK
+#define RESETCTRL_RESET4_MASK ((0x0024 << 2) + 0xfe002000)
+#endif
+#ifndef RESETCTRL_RESET5_MASK
+#define RESETCTRL_RESET5_MASK ((0x0025 << 2) + 0xfe002000)
+#endif
+#ifndef RESETCTRL_RESET6_MASK
+#define RESETCTRL_RESET6_MASK ((0x0026 << 2) + 0xfe002000)
+#endif
+
+#ifndef PM_MIPI_DSI0
+#define PM_MIPI_DSI0 0xff
+#endif
+#ifndef PM_MIPI_DSI1
+#define PM_MIPI_DSI1 0xff
+#endif
+#ifndef PM_EDP0
+#define PM_EDP0 0xff
+#endif
+#ifndef PM_EDP1
+#define PM_EDP1 0xff
+#endif
diff --git a/drivers/amlogic/media/vout/lcd/lcd_extern/Kconfig b/drivers/amlogic/media/vout/lcd/lcd_extern/Kconfig
index d7ffeaa..8b13789 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_extern/Kconfig
+++ b/drivers/amlogic/media/vout/lcd/lcd_extern/Kconfig
@@ -1,45 +1 @@
-config AML_LCD_EXTERN
- bool "lcd_extern driver for lcd"
- help
- Support for lcd extern driver controlling
-
-config AML_LCD_EXTERN_I2C_T5800Q
- bool "lcd_extern I2C_T5800Q driver for lcd"
- help
- Support for lcd extern I2C_T5800Q controlling
-
-config AML_LCD_EXTERN_I2C_DLPC3439
- bool "lcd_extern I2C_DLPC3439 driver for lcd"
- help
- Support for lcd extern I2C_DLPC3439 controlling
-
-config AML_LCD_EXTERN_I2C_RT6947
- bool "lcd_extern I2C_RT6947 driver for lcd"
- help
- Support for lcd extern I2C_RT6947 controlling
-
-config AML_LCD_EXTERN_SPI_LD070WS2
- bool "lcd_extern SPI_LD070WS2 driver for lcd"
- help
- Support for lcd extern SPI_LD070WS2 controlling
-
-config AML_LCD_EXTERN_MIPI_TV070WSM
- bool "lcd_extern MIPI_TV070WSM driver for lcd"
- help
- Support for lcd extern MIPI_TV070WSM controlling
-
-config AML_LCD_EXTERN_MIPI_P070ACB
- bool "lcd_extern MIPI_P070ACB driver for lcd"
- help
- Support for lcd extern MIPI_P070ACB controlling
-
-config AML_LCD_EXTERN_MIPI_ST7701
- bool "lcd_extern MIPI_ST7701 driver for lcd"
- help
- Support for lcd extern MIPI_ST7701 controlling
-
-config AML_LCD_EXTERN_MIPI_TL050FHV02CT
- bool "lcd_extern MIPI_TL050FHV02CT driver for lcd"
- help
- Support for lcd extern MIPI_TL050FHV02CT controlling
diff --git a/drivers/amlogic/media/vout/lcd/lcd_extern/Makefile b/drivers/amlogic/media/vout/lcd/lcd_extern/Makefile
index a801ee3..8b13789 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_extern/Makefile
+++ b/drivers/amlogic/media/vout/lcd/lcd_extern/Makefile
@@ -1,9 +1 @@
-obj-$(CONFIG_AML_LCD_EXTERN) += lcd_extern.o ext_i2c_dev.o ext_default.o mipi_default.o
-obj-$(CONFIG_AML_LCD_EXTERN_I2C_T5800Q) += i2c_T5800Q.o
-obj-$(CONFIG_AML_LCD_EXTERN_I2C_DLPC3439) += i2c_DLPC3439.o
-obj-$(CONFIG_AML_LCD_EXTERN_I2C_RT6947) += i2c_RT6947.o
-obj-$(CONFIG_AML_LCD_EXTERN_SPI_LD070WS2) += spi_LD070WS2.o
-obj-$(CONFIG_AML_LCD_EXTERN_MIPI_TV070WSM) += mipi_TV070WSM.o
-obj-$(CONFIG_AML_LCD_EXTERN_MIPI_P070ACB) += mipi_P070ACB.o
-obj-$(CONFIG_AML_LCD_EXTERN_MIPI_ST7701) += mipi_ST7701.o
-obj-$(CONFIG_AML_LCD_EXTERN_MIPI_TL050FHV02CT) += mipi_TL050FHV02CT.o
+
diff --git a/drivers/amlogic/media/vout/lcd/lcd_extern/ext_default.c b/drivers/amlogic/media/vout/lcd/lcd_extern/ext_default.c
index 3305d04..af6e732 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_extern/ext_default.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_extern/ext_default.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_extern/ext_default.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -31,25 +16,27 @@
#define LCD_EXTERN_NAME "ext_default"
static struct lcd_extern_config_s *ext_config;
-static unsigned char spi_gpio_cs = 0xff;
-static unsigned char spi_gpio_clk = 0xff;
-static unsigned char spi_gpio_data = 0xff;
+
+static unsigned char check_state[4] = {0, 0, 0, 0};
+static unsigned char check_flag;
+static unsigned char check_offset;
+static unsigned char check_len;
static void set_lcd_csb(unsigned int v)
{
- lcd_ext_gpio_set(spi_gpio_cs, v);
+ lcd_ext_gpio_set(ext_config->spi_gpio_cs, v);
udelay(ext_config->spi_delay_us);
}
static void set_lcd_scl(unsigned int v)
{
- lcd_ext_gpio_set(spi_gpio_clk, v);
+ lcd_ext_gpio_set(ext_config->spi_gpio_clk, v);
udelay(ext_config->spi_delay_us);
}
static void set_lcd_sda(unsigned int v)
{
- lcd_ext_gpio_set(spi_gpio_data, v);
+ lcd_ext_gpio_set(ext_config->spi_gpio_data, v);
udelay(ext_config->spi_delay_us);
}
@@ -82,6 +69,15 @@
}
}
+static int lcd_extern_spi_read(unsigned char reg, unsigned char *buf)
+{
+ EXTERR("%s: %s(%d): extern_type %d is not support\n",
+ __func__, ext_config->name,
+ ext_config->index, ext_config->type);
+
+ return -1;
+}
+
static int lcd_extern_spi_write(unsigned char *buf, int len)
{
int i;
@@ -108,21 +104,173 @@
{
int ret = 0;
+ if (!buf) {
+ EXTERR("%s: buf is null\n", __func__);
+ return -1;
+ }
+
+ switch (ext_config->type) {
+ case LCD_EXTERN_I2C:
+ buf[0] = reg;
+ ret = aml_lcd_i2c_read(ext_config->i2c_bus,
+ ext_config->i2c_addr, buf, 1);
+ break;
+ case LCD_EXTERN_SPI:
+ ret = lcd_extern_spi_read(reg, buf);
+ break;
+ default:
+ EXTERR("%s: %s(%d): extern_type %d is not support\n",
+ __func__, ext_config->name,
+ ext_config->index, ext_config->type);
+ ret = -1;
+ break;
+ }
+ if (ret)
+ EXTERR("%s: failed\n", __func__);
+
return ret;
}
-static int lcd_extern_reg_write(unsigned char reg, unsigned char value)
+static int lcd_extern_reg_write(unsigned char *buf, unsigned int len)
{
int ret = 0;
+ if (!buf) {
+ EXTERR("%s: buf is null\n", __func__);
+ return -1;
+ }
+
+ if (!len) {
+ EXTERR("%s: invalid len\n", __func__);
+ return -1;
+ }
+
+ switch (ext_config->type) {
+ case LCD_EXTERN_I2C:
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
+ ext_config->i2c_addr, buf, len);
+ break;
+ case LCD_EXTERN_SPI:
+ ret = lcd_extern_spi_write(buf, len);
+ break;
+ default:
+ EXTERR("%s: %s(%d): extern_type %d is not support\n",
+ __func__, ext_config->name,
+ ext_config->index, ext_config->type);
+ ret = -1;
+ break;
+ }
+ if (ret)
+ EXTERR("%s: failed\n", __func__);
+
return ret;
}
+static void lcd_extern_init_reg_check(unsigned char i2c_bus,
+ unsigned char i2c_addr,
+ unsigned char type,
+ unsigned char *raw_table,
+ unsigned char data_len)
+{
+ unsigned char *chk_table, *chk_buf, *raw_buf;
+ unsigned char index;
+ unsigned char temp_flag = check_flag;
+ int ret = 0;
+
+ /* if not need to check return */
+ if (check_flag == 0)
+ return;
+
+ index = type & 0x0f;
+ if (index >= 4 || data_len < 1 || !raw_table)
+ goto parameter_err0;
+ check_state[index] = 0;
+ check_flag = 0;
+ chk_table = malloc(data_len * sizeof(unsigned char));
+ if (!chk_table)
+ goto parameter_err0;
+ memset(chk_table, 0, data_len);
+ if (((type & 0xf0) == LCD_EXT_CMD_TYPE_CMD) ||
+ ((type & 0xf0) == LCD_EXT_CMD_TYPE_CMD_BIN)) {
+ if (data_len < 2)
+ goto parameter_err1;
+ chk_table[0] = raw_table[0];
+ data_len--;
+ raw_table++;
+ }
+ ret = aml_lcd_i2c_read(i2c_bus, i2c_addr, chk_table, data_len);
+ if (!check_len || check_len > data_len)
+ check_len = data_len;
+ if (check_offset > data_len)
+ check_offset = 0;
+ if ((ret) || (check_offset + check_len) > data_len)
+ goto parameter_err1;
+ chk_buf = chk_table + check_offset;
+ raw_buf = raw_table + check_offset;
+ ret = memcmp(chk_buf, raw_buf, check_len);
+ if (ret == 0)
+ check_state[index] = temp_flag;
+ if (lcd_debug_print_flag)
+ EXTERR("%s: ret : %d\n", __func__, ret);
+ free(chk_table);
+ return;
+parameter_err1:
+ free(chk_table);
+parameter_err0:
+ EXTERR("%s: error parameters\n", __func__);
+}
+
+static void lcd_extern_init_reg_check2(unsigned char i2c_bus,
+ unsigned char i2c_addr,
+ unsigned char type,
+ unsigned char *raw_table,
+ unsigned char data_len)
+{
+ unsigned char *chk_table, *chk_buf, *raw_buf;
+ unsigned char index;
+ unsigned char temp_flag = check_flag;
+ int ret = 0;
+
+ /* if not need to check return */
+ if (check_flag == 0)
+ return;
+
+ index = type & 0x0f;
+ if (index >= 4 || data_len < 1 || !raw_table)
+ goto parameter_err0;
+ check_state[index] = 0;
+ check_flag = 0;
+ chk_table = malloc(data_len * sizeof(unsigned char));
+ if (!chk_table)
+ goto parameter_err0;
+ memset(chk_table, 0, data_len);
+ ret = aml_lcd_i2c_read(i2c_bus, i2c_addr, chk_table,
+ check_offset + data_len);
+ if (!check_len || check_len > data_len)
+ check_len = data_len;
+ if (ret)
+ goto parameter_err1;
+ chk_buf = chk_table + check_offset;
+ raw_buf = raw_table + 1;
+ ret = memcmp(chk_buf, raw_buf, check_len);
+ if (ret == 0)
+ check_state[index] = temp_flag;
+ if (lcd_debug_print_flag)
+ EXTPR("%s: ret : %d\n", __func__, ret);
+ free(chk_table);
+ return;
+parameter_err1:
+ free(chk_table);
+parameter_err0:
+ EXTERR("%s: error parameters\n", __func__);
+}
+
static int lcd_extern_power_cmd_dynamic_size(unsigned char *table, int flag)
{
int i = 0, j = 0, max_len = 0, step = 0;
- unsigned char type, cmd_size;
+ unsigned char type, size, i2c_bus, i2c_addr;
int delay_ms, ret = 0;
+ i2c_bus = ext_config->i2c_bus;
if (flag)
max_len = ext_config->table_init_on_cnt;
@@ -133,121 +281,253 @@
case LCD_EXTERN_I2C:
while ((i + 1) < max_len) {
type = table[i];
+ size = table[i + 1];
if (type == LCD_EXT_CMD_TYPE_END)
break;
if (lcd_debug_print_flag) {
- EXTPR("%s: step %d: type=0x%02x, cmd_size=%d\n",
- __func__, step, type, table[i+1]);
+ EXTPR("%s: step %d: type=0x%02x, size=%d\n",
+ __func__, step, type, size);
}
- cmd_size = table[i+1];
- if (cmd_size == 0)
+ if (size == 0)
goto power_cmd_dynamic_i2c_next;
- if ((i + 2 + cmd_size) > max_len)
+ if ((i + 2 + size) > max_len)
break;
if (type == LCD_EXT_CMD_TYPE_NONE) {
/* do nothing */
} else if (type == LCD_EXT_CMD_TYPE_GPIO) {
- if (cmd_size < 2) {
- EXTERR("step %d: invalid cmd_size %d for GPIO\n",
- step, cmd_size);
+ if (size < 2) {
+ EXTERR
+ ("step %d: invalid size %d for GPIO\n",
+ step, size);
goto power_cmd_dynamic_i2c_next;
}
- lcd_ext_gpio_set(table[i+2], table[i+3]);
- if (cmd_size > 2) {
- if (table[i+4] > 0)
- mdelay(table[i+4]);
+ lcd_ext_gpio_set(table[i + 2], table[i + 3]);
+ if (size > 2) {
+ if (table[i + 4] > 0)
+ mdelay(table[i + 4]);
}
} else if (type == LCD_EXT_CMD_TYPE_DELAY) {
delay_ms = 0;
- for (j = 0; j < cmd_size; j++)
- delay_ms += table[i+2+j];
+ for (j = 0; j < size; j++)
+ delay_ms += table[i + 2 + j];
if (delay_ms > 0)
mdelay(delay_ms);
- } else if (type == LCD_EXT_CMD_TYPE_CMD) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
- ext_config->i2c_addr,
- &table[i+2], cmd_size);
- } else if (type == LCD_EXT_CMD_TYPE_CMD2) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
- ext_config->i2c_addr2,
- &table[i+2], cmd_size);
+ } else if (type == LCD_EXT_CMD_TYPE_CHECK) {
+ if (size == 1) {
+ check_flag = table[i + 2];
+ check_offset = 0;
+ check_len = 0;
+ } else if (size == 3) {
+ check_flag = table[i + 2];
+ check_offset = table[i + 3];
+ check_len = table[i + 4];
+ } else {
+ check_flag = 0;
+ }
+ } else if ((type == LCD_EXT_CMD_TYPE_CMD) ||
+ (type == LCD_EXT_CMD_TYPE_CMD_BIN) ||
+ (type == LCD_EXT_CMD_TYPE_CMD_BIN_DATA)) {
+ i2c_addr = ext_config->i2c_addr;
+ lcd_extern_init_reg_check(i2c_bus,
+ i2c_addr,
+ type,
+ &table[i + 2],
+ size);
+ if (check_state[0] == 1)
+ goto power_cmd_dynamic_i2c_next;
+ ret = aml_lcd_i2c_write(i2c_bus,
+ i2c_addr,
+ &table[i + 2],
+ size);
+ } else if (type == LCD_EXT_CMD_TYPE_CMD_BIN2) {
+ i2c_addr = ext_config->i2c_addr;
+ lcd_extern_init_reg_check2(i2c_bus,
+ i2c_addr,
+ type,
+ &table[i + 2],
+ size);
+ if (check_state[0] == 1)
+ goto power_cmd_dynamic_i2c_next;
+ ret = aml_lcd_i2c_write(i2c_bus,
+ i2c_addr,
+ &table[i + 2],
+ size);
+ } else if ((type == LCD_EXT_CMD_TYPE_CMD2) ||
+ (type == LCD_EXT_CMD_TYPE_CMD2_BIN) ||
+ (type == LCD_EXT_CMD_TYPE_CMD2_BIN_DATA)) {
+ i2c_addr = ext_config->i2c_addr2;
+ lcd_extern_init_reg_check(i2c_bus,
+ i2c_addr,
+ type,
+ &table[i + 2],
+ size);
+ if (check_state[1] == 1)
+ goto power_cmd_dynamic_i2c_next;
+ ret = aml_lcd_i2c_write(i2c_bus,
+ i2c_addr,
+ &table[i + 2],
+ size);
+ } else if (type == LCD_EXT_CMD_TYPE_CMD2_BIN2) {
+ i2c_addr = ext_config->i2c_addr2;
+ lcd_extern_init_reg_check2(i2c_bus,
+ i2c_addr,
+ type,
+ &table[i + 2],
+ size);
+ if (check_state[1] == 1)
+ goto power_cmd_dynamic_i2c_next;
+ ret = aml_lcd_i2c_write(i2c_bus,
+ i2c_addr,
+ &table[i + 2],
+ size);
+ } else if ((type == LCD_EXT_CMD_TYPE_CMD3) ||
+ (type == LCD_EXT_CMD_TYPE_CMD3_BIN) ||
+ (type == LCD_EXT_CMD_TYPE_CMD3_BIN_DATA)) {
+ i2c_addr = ext_config->i2c_addr3;
+ lcd_extern_init_reg_check(i2c_bus,
+ i2c_addr,
+ type,
+ &table[i + 2],
+ size);
+ if (check_state[2] == 1)
+ goto power_cmd_dynamic_i2c_next;
+ ret = aml_lcd_i2c_write(i2c_bus,
+ i2c_addr,
+ &table[i + 2],
+ size);
+ } else if (type == LCD_EXT_CMD_TYPE_CMD3_BIN2) {
+ i2c_addr = ext_config->i2c_addr3;
+ lcd_extern_init_reg_check2(i2c_bus,
+ i2c_addr,
+ type,
+ &table[i + 2],
+ size);
+ if (check_state[2] == 1)
+ goto power_cmd_dynamic_i2c_next;
+ ret = aml_lcd_i2c_write(i2c_bus,
+ i2c_addr,
+ &table[i + 2],
+ size);
+ } else if ((type == LCD_EXT_CMD_TYPE_CMD4) ||
+ (type == LCD_EXT_CMD_TYPE_CMD4_BIN) ||
+ (type == LCD_EXT_CMD_TYPE_CMD4_BIN_DATA)) {
+ i2c_addr = ext_config->i2c_addr4;
+ lcd_extern_init_reg_check(i2c_bus,
+ i2c_addr,
+ type,
+ &table[i + 2],
+ size);
+ if (check_state[3] == 1)
+ goto power_cmd_dynamic_i2c_next;
+ ret = aml_lcd_i2c_write(i2c_bus,
+ i2c_addr,
+ &table[i + 2],
+ size);
+ } else if (type == LCD_EXT_CMD_TYPE_CMD4_BIN2) {
+ i2c_addr = ext_config->i2c_addr4;
+ lcd_extern_init_reg_check2(i2c_bus,
+ i2c_addr,
+ type,
+ &table[i + 2],
+ size);
+ if (check_state[3] == 1)
+ goto power_cmd_dynamic_i2c_next;
+ ret = aml_lcd_i2c_write(i2c_bus,
+ i2c_addr,
+ &table[i + 2],
+ size);
} else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
- ext_config->i2c_addr,
- &table[i+2], (cmd_size-1));
- if (table[i+1+cmd_size] > 0)
- mdelay(table[i+1+cmd_size]);
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
+ ext_config->i2c_addr,
+ &table[i + 2], (size - 1));
+ if (table[i + 1 + size] > 0)
+ mdelay(table[i + 1 + size]);
} else if (type == LCD_EXT_CMD_TYPE_CMD2_DELAY) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
- ext_config->i2c_addr2,
- &table[i+2], (cmd_size - 1));
- if (table[i+1+cmd_size] > 0)
- mdelay(table[i+1+cmd_size]);
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
+ ext_config->i2c_addr2,
+ &table[i + 2], (size - 1));
+ if (table[i + 1 + size] > 0)
+ mdelay(table[i + 1 + size]);
+ } else if (type == LCD_EXT_CMD_TYPE_CMD3_DELAY) {
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
+ ext_config->i2c_addr3,
+ &table[i + 2], (size - 1));
+ if (table[i + 1 + size] > 0)
+ mdelay(table[i + 1 + size]);
+ } else if (type == LCD_EXT_CMD_TYPE_CMD4_DELAY) {
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
+ ext_config->i2c_addr4,
+ &table[i + 2], (size - 1));
+ if (table[i + 1 + size] > 0)
+ mdelay(table[i + 1 + size]);
} else {
EXTERR("%s: %s(%d): type 0x%02x invalid\n",
- __func__, ext_config->name,
- ext_config->index, type);
+ __func__, ext_config->name,
+ ext_config->index, type);
}
power_cmd_dynamic_i2c_next:
- i += (cmd_size + 2);
+ i += (size + 2);
step++;
}
break;
case LCD_EXTERN_SPI:
while ((i + 1) < max_len) {
type = table[i];
+ size = table[i + 1];
if (type == LCD_EXT_CMD_TYPE_END)
break;
if (lcd_debug_print_flag) {
- EXTPR("%s: step %d: type=0x%02x, cmd_size=%d\n",
- __func__, step, type, table[i+1]);
+ EXTPR("%s: step %d: type=0x%02x, size=%d\n",
+ __func__, step, type, size);
}
- cmd_size = table[i+1];
- if (cmd_size == 0)
+ if (size == 0)
goto power_cmd_dynamic_spi_next;
- if ((i + 2 + cmd_size) > max_len)
+ if ((i + 2 + size) > max_len)
break;
if (type == LCD_EXT_CMD_TYPE_NONE) {
/* do nothing */
} else if (type == LCD_EXT_CMD_TYPE_GPIO) {
- if (cmd_size < 2) {
- EXTERR("step %d: invalid cmd_size %d for GPIO\n",
- step, cmd_size);
+ if (size < 2) {
+ EXTERR
+ ("step %d: invalid size %d for GPIO\n",
+ step, size);
goto power_cmd_dynamic_spi_next;
}
- lcd_ext_gpio_set(table[i+2], table[i+3]);
- if (cmd_size > 2) {
- if (table[i+4] > 0)
- mdelay(table[i+4]);
+ lcd_ext_gpio_set(table[i + 2], table[i + 3]);
+ if (size > 2) {
+ if (table[i + 4] > 0)
+ mdelay(table[i + 4]);
}
} else if (type == LCD_EXT_CMD_TYPE_DELAY) {
delay_ms = 0;
- for (j = 0; j < cmd_size; j++)
- delay_ms += table[i+2+j];
+ for (j = 0; j < size; j++)
+ delay_ms += table[i + 2 + j];
if (delay_ms > 0)
mdelay(delay_ms);
- } else if (type == LCD_EXT_CMD_TYPE_CMD) {
- ret = lcd_extern_spi_write(&table[i+2], cmd_size);
+ } else if ((type == LCD_EXT_CMD_TYPE_CMD) ||
+ (type == LCD_EXT_CMD_TYPE_CMD_BIN)) {
+ ret = lcd_extern_spi_write(&table[i + 2], size);
} else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
- ret = lcd_extern_spi_write(&table[i+2], (cmd_size-1));
- if (table[i+1+cmd_size] > 0)
- mdelay(table[i+1+cmd_size]);
+ ret = lcd_extern_spi_write(&table[i + 2],
+ (size - 1));
+ if (table[i + 1 + size] > 0)
+ mdelay(table[i + 1 + size]);
} else {
EXTERR("%s: %s(%d): type 0x%02x invalid\n",
- __func__, ext_config->name,
- ext_config->index, type);
+ __func__, ext_config->name,
+ ext_config->index, type);
}
power_cmd_dynamic_spi_next:
- i += (cmd_size + 2);
+ i += (size + 2);
step++;
}
break;
default:
EXTERR("%s: %s(%d): extern_type %d is not support\n",
- __func__, ext_config->name,
- ext_config->index, ext_config->type);
+ __func__, ext_config->name,
+ ext_config->index, ext_config->type);
break;
}
@@ -295,26 +575,58 @@
delay_ms += table[i+1+j];
if (delay_ms > 0)
mdelay(delay_ms);
- } else if (type == LCD_EXT_CMD_TYPE_CMD) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
+ } else if ((type == LCD_EXT_CMD_TYPE_CMD) ||
+ (type == LCD_EXT_CMD_TYPE_CMD_BIN) ||
+ (type == LCD_EXT_CMD_TYPE_CMD_BIN_DATA)) {
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
ext_config->i2c_addr,
&table[i+1], (cmd_size-1));
- } else if (type == LCD_EXT_CMD_TYPE_CMD2) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
- ext_config->i2c_addr2,
+ } else if ((type == LCD_EXT_CMD_TYPE_CMD2) ||
+ (type == LCD_EXT_CMD_TYPE_CMD2_BIN) ||
+ (type == LCD_EXT_CMD_TYPE_CMD2_BIN_DATA)) {
+ ret = aml_lcd_i2c_write
+ (ext_config->i2c_bus,
+ ext_config->i2c_addr2,
+ &table[i + 1], (cmd_size - 1));
+ } else if ((type == LCD_EXT_CMD_TYPE_CMD3) ||
+ (type == LCD_EXT_CMD_TYPE_CMD3_BIN) ||
+ (type == LCD_EXT_CMD_TYPE_CMD3_BIN_DATA)) {
+ ret = aml_lcd_i2c_write
+ (ext_config->i2c_bus,
+ ext_config->i2c_addr3,
+ &table[i + 1], (cmd_size - 1));
+ } else if ((type == LCD_EXT_CMD_TYPE_CMD4) ||
+ (type == LCD_EXT_CMD_TYPE_CMD4_BIN) ||
+ (type == LCD_EXT_CMD_TYPE_CMD4_BIN_DATA)) {
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
+ ext_config->i2c_addr4,
&table[i+1], (cmd_size-1));
} else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
ext_config->i2c_addr,
&table[i+1], (cmd_size-2));
if (table[i+cmd_size-1] > 0)
mdelay(table[i+cmd_size-1]);
} else if (type == LCD_EXT_CMD_TYPE_CMD2_DELAY) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
- ext_config->i2c_addr2,
- &table[i+1], (cmd_size-2));
- if (table[i+cmd_size-1] > 0)
- mdelay(table[i+cmd_size-1]);
+ ret = aml_lcd_i2c_write
+ (ext_config->i2c_bus,
+ ext_config->i2c_addr2,
+ &table[i + 1], (cmd_size - 2));
+ if (table[i + cmd_size - 1] > 0)
+ mdelay(table[i + cmd_size - 1]);
+ } else if (type == LCD_EXT_CMD_TYPE_CMD3_DELAY) {
+ ret = aml_lcd_i2c_write
+ (ext_config->i2c_bus,
+ ext_config->i2c_addr3,
+ &table[i + 1], (cmd_size - 2));
+ if (table[i + cmd_size - 1] > 0)
+ mdelay(table[i + cmd_size - 1]);
+ } else if (type == LCD_EXT_CMD_TYPE_CMD4_DELAY) {
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
+ ext_config->i2c_addr4,
+ &table[i + 1], (cmd_size - 2));
+ if (table[i + cmd_size - 1] > 0)
+ mdelay(table[i + cmd_size - 1]);
} else {
EXTERR("%s: %s(%d): type 0x%02x invalid\n",
__func__, ext_config->name,
@@ -347,7 +659,8 @@
delay_ms += table[i+1+j];
if (delay_ms > 0)
mdelay(delay_ms);
- } else if (type == LCD_EXT_CMD_TYPE_CMD) {
+ } else if ((type == LCD_EXT_CMD_TYPE_CMD) ||
+ (type == LCD_EXT_CMD_TYPE_CMD_BIN)) {
ret = lcd_extern_spi_write(&table[i+1], (cmd_size-1));
} else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
ret = lcd_extern_spi_write(&table[i+1], (cmd_size-2));
@@ -378,7 +691,6 @@
int cmd_size;
int ret = 0;
- /* step 1: power prepare */
if (ext_config->type == LCD_EXTERN_SPI)
spi_gpio_init();
@@ -423,7 +735,7 @@
{
int ret;
- lcd_extern_pinmux_set(1);
+ lcd_extern_pinmux_set(ext_config, 1);
ret = lcd_extern_power_ctrl(1);
return ret;
}
@@ -433,12 +745,12 @@
int ret;
ret = lcd_extern_power_ctrl(0);
- lcd_extern_pinmux_set(0);
+ lcd_extern_pinmux_set(ext_config, 0);
return ret;
}
-static int lcd_extern_driver_update(struct aml_lcd_extern_driver_s *ext_drv)
+static int lcd_extern_driver_update(struct lcd_extern_driver_s *ext_drv)
{
if (ext_drv == NULL) {
EXTERR("%s driver is null\n", LCD_EXTERN_NAME);
@@ -449,10 +761,6 @@
return -1;
}
- spi_gpio_cs = ext_drv->common->spi_gpio_cs;
- spi_gpio_clk = ext_drv->common->spi_gpio_clk;
- spi_gpio_data = ext_drv->common->spi_gpio_data;
-
if (ext_drv->config->type == LCD_EXTERN_SPI)
ext_drv->config->spi_delay_us = 1000 / ext_drv->config->spi_clk_freq;
@@ -464,7 +772,7 @@
return 0;
}
-int lcd_extern_default_probe(struct aml_lcd_extern_driver_s *ext_drv)
+int lcd_extern_default_probe(struct lcd_extern_driver_s *ext_drv)
{
int ret = 0;
diff --git a/drivers/amlogic/media/vout/lcd/lcd_extern/ext_i2c_dev.c b/drivers/amlogic/media/vout/lcd/lcd_extern/ext_i2c_dev.c
deleted file mode 100644
index f2b4623..0000000
--- a/drivers/amlogic/media/vout/lcd/lcd_extern/ext_i2c_dev.c
+++ /dev/null
@@ -1,134 +0,0 @@
-/*
- * drivers/amlogic/media/vout/lcd/lcd_extern/ext_i2c_dev.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <asm/arch/gpio.h>
-#include <fdtdec.h>
-#include <i2c.h>
-#include <dm.h>
-#include <amlogic/media/vout/lcd/aml_lcd.h>
-#include <amlogic/media/vout/lcd/lcd_extern.h>
-#include "lcd_extern.h"
-#include "../lcd_common.h"
-
-struct aml_lcd_extern_i2c_match_s {
- unsigned char bus_id;
- unsigned char bus_sys;
- char *bus_str;
-};
-
-static struct aml_lcd_extern_i2c_match_s lcd_extern_i2c_match_table[] = {
- {LCD_EXTERN_I2C_BUS_0, LCD_EXT_I2C_BUS_0, "i2c_0/a"},
- {LCD_EXTERN_I2C_BUS_1, LCD_EXT_I2C_BUS_1, "i2c_1/b"},
- {LCD_EXTERN_I2C_BUS_2, LCD_EXT_I2C_BUS_2, "i2c_2/c"},
- {LCD_EXTERN_I2C_BUS_3, LCD_EXT_I2C_BUS_3, "i2c_3/d"},
- {LCD_EXTERN_I2C_BUS_4, LCD_EXT_I2C_BUS_4, "i2c_4/ao"},
- {LCD_EXTERN_I2C_BUS_MAX, LCD_EXT_I2C_BUS_MAX, "i2c_invalid"},
-};
-
-void lcd_extern_i2c_bus_print(unsigned char i2c_bus)
-{
- int i, temp = ARRAY_SIZE(lcd_extern_i2c_match_table) - 1;
-
- for (i = 0; i < ARRAY_SIZE(lcd_extern_i2c_match_table); i++) {
- if (lcd_extern_i2c_match_table[i].bus_id == i2c_bus) {
- temp = i;
- break;
- }
- }
-
- EXTPR("i2c_bus = %s(%d)\n",
- lcd_extern_i2c_match_table[temp].bus_str, temp);
-}
-
-unsigned char lcd_extern_i2c_bus_get_sys(unsigned char i2c_bus)
-{
- int i, ret = LCD_EXT_I2C_BUS_MAX;
-
- for (i = 0; i < ARRAY_SIZE(lcd_extern_i2c_match_table); i++) {
- if (lcd_extern_i2c_match_table[i].bus_id == i2c_bus) {
- ret = lcd_extern_i2c_match_table[i].bus_sys;
- break;
- }
- }
-
- if (lcd_debug_print_flag)
- EXTPR("%s: %d->%d\n", __func__, i2c_bus, ret);
- return ret;
-}
-
-int lcd_extern_i2c_write(unsigned char i2c_bus, unsigned i2c_addr,
- unsigned char *buff, unsigned len)
-{
- unsigned char sys_i2c_bus;
- struct udevice *i2c_dev;
- int i, ret = 0;
-
- sys_i2c_bus = lcd_extern_i2c_bus_get_sys(i2c_bus);
- ret = i2c_get_chip_for_busnum(sys_i2c_bus, i2c_addr, 1, &i2c_dev);
- if (ret) {
- EXTERR("no sys_i2c_bus %d find\n", sys_i2c_bus);
- return ret;
- }
-
- if (lcd_debug_print_flag) {
- printf("%s:", __func__);
- for (i = 0; i < len; i++)
- printf(" 0x%02x", buff[i]);
- printf(" [addr 0x%02x]\n", i2c_addr);
- }
-
- ret = dm_i2c_write(i2c_dev, i2c_addr, buff, len);
- if (ret) {
- EXTERR("i2c write failed [addr 0x%02x]\n", i2c_addr);
- return ret;
- }
-
- return 0;
-}
-
-int lcd_extern_i2c_read(unsigned char i2c_bus, unsigned i2c_addr,
- unsigned char *buff, unsigned int len)
-{
- unsigned char sys_i2c_bus;
- struct udevice *i2c_dev;
- int ret = 0;
-
- sys_i2c_bus = lcd_extern_i2c_bus_get_sys(i2c_bus);
- ret = i2c_get_chip_for_busnum(sys_i2c_bus, i2c_addr, 1, &i2c_dev);
- if (ret) {
- EXTERR("no sys_i2c_bus %d find\n", sys_i2c_bus);
- return ret;
- }
-
- ret = dm_i2c_write(i2c_dev, i2c_addr, buff, 1);
- if (ret) {
- EXTERR("i2c write failed [addr 0x%02x]\n", i2c_addr);
- return ret;
- }
- ret = dm_i2c_read(i2c_dev, i2c_addr, buff, len);
- if (ret) {
- EXTERR("i2c read failed [addr 0x%02x]\n", i2c_addr);
- return ret;
- }
-
- return 0;
-}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_extern/i2c_ANX6862_7911.c b/drivers/amlogic/media/vout/lcd/lcd_extern/i2c_ANX6862_7911.c
index a8334ae..d1f5583 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_extern/i2c_ANX6862_7911.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_extern/i2c_ANX6862_7911.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_extern/i2c_ANX6862_7911.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -123,7 +108,7 @@
EXTPR("%s: step %d: type=0x%02x, cmd_size=%d\n",
__func__, step, type, table[i+1]);
}
- ret = lcd_extern_i2c_write(i2c_bus, i2c_addr,
+ ret = aml_lcd_i2c_write(i2c_bus, i2c_addr,
&table[i+2], cmd_size);
delay_bypass = 0;
} else if (type == LCD_EXT_CMD_TYPE_DELAY) {
@@ -193,7 +178,7 @@
EXTPR("%s: step %d: type=0x%02x, cmd_size=%d\n",
__func__, step, type, cmd_size);
}
- ret = lcd_extern_i2c_write(i2c_bus, i2c_addr,
+ ret = aml_lcd_i2c_write(i2c_bus, i2c_addr,
&table[i+1], (cmd_size-1));
delay_bypass = 0;
} else if (type == LCD_EXT_CMD_TYPE_DELAY) {
@@ -354,7 +339,7 @@
}
memset(chk_table, 0, cnt);
- ret = lcd_extern_i2c_read(i2c_bus, i2c_addr, chk_table, cnt);
+ ret = aml_lcd_i2c_read(i2c_bus, i2c_addr, chk_table, cnt);
if (ret) {
EXTERR("%s: i2c read error\n", __func__);
return -1;
@@ -372,7 +357,7 @@
{
int ret = 0;
- lcd_extern_pinmux_set(1);
+ lcd_extern_pinmux_set(ext_config, 1);
/* check voltage is init or not */
/* step1: ANX6862 */
@@ -382,7 +367,7 @@
/* init voltage */
lcd_extern_power_cmd(0);
/* NVM write */
- lcd_extern_i2c_write(ext_config->i2c_bus, ext_config->i2c_addr,
+ aml_lcd_i2c_write(ext_config->i2c_bus, ext_config->i2c_addr,
ANX6862_NVM_wr, 2);
}
@@ -393,7 +378,7 @@
/* init voltage */
lcd_extern_power_cmd(1);
/* NVM write */
- lcd_extern_i2c_write(ext_config->i2c_bus, ext_config->i2c_addr2,
+ aml_lcd_i2c_write(ext_config->i2c_bus, ext_config->i2c_addr2,
ANX7911_NVM_wr, 2);
}
@@ -403,7 +388,7 @@
static int lcd_extern_power_off(void)
{
- lcd_extern_pinmux_set(0);
+ lcd_extern_pinmux_set(ext_config, 0);
return 0;
}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_extern/i2c_DLPC3439.c b/drivers/amlogic/media/vout/lcd/lcd_extern/i2c_DLPC3439.c
index 7aded95..f8c963b 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_extern/i2c_DLPC3439.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_extern/i2c_DLPC3439.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_extern/i2c_DLPC3439.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -55,13 +40,13 @@
{
int ret = 0;
- lcd_extern_pinmux_set(1);
+ lcd_extern_pinmux_set(ext_config, 1);
- lcd_extern_i2c_write(ext_config->i2c_bus, ext_config->i2c_addr, data_1, 9);
- lcd_extern_i2c_write(ext_config->i2c_bus, ext_config->i2c_addr, data_2, 5);
- lcd_extern_i2c_write(ext_config->i2c_bus, ext_config->i2c_addr, data_3, 5);
- lcd_extern_i2c_write(ext_config->i2c_bus, ext_config->i2c_addr, data_4, 2);
- lcd_extern_i2c_write(ext_config->i2c_bus, ext_config->i2c_addr, data_5, 2);
+ aml_lcd_i2c_write(ext_config->i2c_bus, ext_config->i2c_addr, data_1, 9);
+ aml_lcd_i2c_write(ext_config->i2c_bus, ext_config->i2c_addr, data_2, 5);
+ aml_lcd_i2c_write(ext_config->i2c_bus, ext_config->i2c_addr, data_3, 5);
+ aml_lcd_i2c_write(ext_config->i2c_bus, ext_config->i2c_addr, data_4, 2);
+ aml_lcd_i2c_write(ext_config->i2c_bus, ext_config->i2c_addr, data_5, 2);
EXTPR("%s\n", __func__);
return ret;
@@ -71,7 +56,7 @@
{
int ret = 0;
- lcd_extern_pinmux_set(0);
+ lcd_extern_pinmux_set(ext_config, 0);
return ret;
}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_extern/i2c_RT6947.c b/drivers/amlogic/media/vout/lcd/lcd_extern/i2c_RT6947.c
index 18f96a2..ed4b206 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_extern/i2c_RT6947.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_extern/i2c_RT6947.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_extern/i2c_RT6947.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -98,19 +83,21 @@
delay_ms += table[i+2+j];
if (delay_ms > 0)
mdelay(delay_ms);
- } else if (type == LCD_EXT_CMD_TYPE_CMD) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
+ } else if ((type == LCD_EXT_CMD_TYPE_CMD) ||
+ (type == LCD_EXT_CMD_TYPE_CMD_BIN)) {
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
ext_config->i2c_addr, &table[i+2], cmd_size);
- } else if (type == LCD_EXT_CMD_TYPE_CMD2) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
+ } else if ((type == LCD_EXT_CMD_TYPE_CMD2) ||
+ (type == LCD_EXT_CMD_TYPE_CMD2_BIN)) {
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
ext_config->i2c_addr2, &table[i+2], cmd_size);
} else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
ext_config->i2c_addr, &table[i+2], (cmd_size-1));
if (table[i+1+cmd_size] > 0)
mdelay(table[i+1+cmd_size]);
} else if (type == LCD_EXT_CMD_TYPE_CMD2_DELAY) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
ext_config->i2c_addr2, &table[i+2], (cmd_size-1));
if (table[i+1+cmd_size] > 0)
mdelay(table[i+1+cmd_size]);
@@ -162,19 +149,21 @@
delay_ms += table[i+1+j];
if (delay_ms > 0)
mdelay(delay_ms);
- } else if (type == LCD_EXT_CMD_TYPE_CMD) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
+ } else if ((type == LCD_EXT_CMD_TYPE_CMD) ||
+ (type == LCD_EXT_CMD_TYPE_CMD_BIN)) {
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
ext_config->i2c_addr, &table[i+1], (cmd_size-1));
- } else if (type == LCD_EXT_CMD_TYPE_CMD2) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
+ } else if ((type == LCD_EXT_CMD_TYPE_CMD2) ||
+ (type == LCD_EXT_CMD_TYPE_CMD2_BIN)) {
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
ext_config->i2c_addr2, &table[i+1], (cmd_size-1));
} else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
ext_config->i2c_addr, &table[i+1], (cmd_size-2));
if (table[i+cmd_size-1] > 0)
mdelay(table[i+cmd_size-1]);
} else if (type == LCD_EXT_CMD_TYPE_CMD2_DELAY) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
ext_config->i2c_addr2, &table[i+1], (cmd_size-2));
if (table[i+cmd_size-1] > 0)
mdelay(table[i+cmd_size-1]);
@@ -225,7 +214,7 @@
}
memset(chk_table, 0, len);
- ret = lcd_extern_i2c_read(ext_config->i2c_bus, ext_config->i2c_addr, chk_table, len);
+ ret = aml_lcd_i2c_read(ext_config->i2c_bus, ext_config->i2c_addr, chk_table, len);
if (ret == 0) {
for (i = 0; i < len; i++) {
if (chk_table[i] != ext_config->table_init_on[i+3])
@@ -244,7 +233,7 @@
int len;
#endif
- lcd_extern_pinmux_set(1);
+ lcd_extern_pinmux_set(ext_config, 1);
#ifdef GAMMA_EEPROM_WRITE
len = ext_config->table_init_on[1] - 2;
@@ -255,10 +244,10 @@
lcd_extern_power_cmd(ext_config->table_init_on);
/* enable mtp */
len = sizeof(mtp_en) / sizeof(unsigned char);
- lcd_extern_i2c_write(ext_config->i2c_bus, ext_config->i2c_addr, mtp_en, len);
+ aml_lcd_i2c_write(ext_config->i2c_bus, ext_config->i2c_addr, mtp_en, len);
/* write eeprom */
len = sizeof(eeprom_wr) / sizeof(unsigned char);
- lcd_extern_i2c_write(ext_config->i2c_bus, ext_config->i2c_addr, eeprom_wr, len);
+ aml_lcd_i2c_write(ext_config->i2c_bus, ext_config->i2c_addr, eeprom_wr, len);
}
#else
lcd_extern_power_cmd(ext_config->table_init_on);
@@ -272,7 +261,7 @@
{
int ret = 0;
- lcd_extern_pinmux_set(0);
+ lcd_extern_pinmux_set(ext_config, 0);
return ret;
}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_extern/i2c_T5800Q.c b/drivers/amlogic/media/vout/lcd/lcd_extern/i2c_T5800Q.c
index 58f775b..4d957dd 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_extern/i2c_T5800Q.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_extern/i2c_T5800Q.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_extern/i2c_T5800Q.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -60,7 +45,7 @@
return ret;
}
-static int lcd_extern_reg_write(unsigned char reg, unsigned char value)
+static int lcd_extern_reg_write(unsigned char *buf, unsigned int len)
{
int ret = 0;
@@ -112,10 +97,10 @@
if (delay_ms > 0)
mdelay(delay_ms);
} else if (type == LCD_EXT_CMD_TYPE_CMD) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
ext_config->i2c_addr, &table[i+2], cmd_size);
} else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
ext_config->i2c_addr, &table[i+2], (cmd_size-1));
if (table[i+1+cmd_size] > 0)
mdelay(table[i+1+cmd_size]);
@@ -171,11 +156,11 @@
if (delay_ms > 0)
mdelay(delay_ms);
} else if (type == LCD_EXT_CMD_TYPE_CMD) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
ext_config->i2c_addr,
&table[i+1], (cmd_size-1));
} else if (type == LCD_EXT_CMD_TYPE_CMD_DELAY) {
- ret = lcd_extern_i2c_write(ext_config->i2c_bus,
+ ret = aml_lcd_i2c_write(ext_config->i2c_bus,
ext_config->i2c_addr,
&table[i+1], (cmd_size-2));
if (table[i+cmd_size-1] > 0)
@@ -195,7 +180,7 @@
{
unsigned char *table;
unsigned char cmd_size;
- int ret = -1;
+ int ret = 0;
cmd_size = ext_config->cmd_size;
if (flag)
@@ -204,10 +189,12 @@
table = ext_config->table_init_off;
if (cmd_size < 1) {
EXTERR("%s: cmd_size %d is invalid\n", __func__, cmd_size);
+ ret = -1;
goto power_ctrl_next;
}
if (table == NULL) {
EXTERR("%s: init_table %d is NULL\n", __func__, flag);
+ ret = -1;
goto power_ctrl_next;
}
if (cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC)
@@ -230,7 +217,7 @@
{
int ret;
- lcd_extern_pinmux_set(1);
+ lcd_extern_pinmux_set(ext_config, 1);
ret = lcd_extern_power_ctrl(1);
return ret;
}
@@ -240,7 +227,7 @@
int ret;
ret = lcd_extern_power_ctrl(0);
- lcd_extern_pinmux_set(0);
+ lcd_extern_pinmux_set(ext_config, 0);
return ret;
}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_extern/lcd_extern.c b/drivers/amlogic/media/vout/lcd/lcd_extern/lcd_extern.c
index acfba98..e10bc3d 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_extern/lcd_extern.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_extern/lcd_extern.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_extern/lcd_extern.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -29,23 +14,37 @@
#include "../lcd_common.h"
#include "../lcd_reg.h"
+static char *dt_addr;
+static int lcd_extern_drv_cnt;
+static int lcd_extern_index_lut[EXTERN_MUL_MAX];
+static struct lcd_extern_common_s *ext_common;
+static struct lcd_extern_driver_s *lcd_ext_driver[EXTERN_MUL_MAX];
-static const void *ext_dt_blob = NULL;
+struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX];
+struct lcd_extern_common_s ext_common_dft;
-static struct aml_lcd_extern_driver_s *lcd_ext_driver;
-
-struct aml_lcd_extern_driver_s *aml_lcd_extern_get_driver(void)
+struct lcd_extern_driver_s *lcd_extern_get_driver(int index)
{
- if (lcd_ext_driver == NULL)
- EXTERR("invalid driver\n");
- return lcd_ext_driver;
+ int i = 0;
+
+ if (index >= LCD_EXTERN_INDEX_INVALID)
+ return NULL;
+
+ for (i = 0; i < lcd_extern_drv_cnt; i++) {
+ if (lcd_ext_driver[i] &&
+ lcd_ext_driver[i]->config->index == index)
+ return lcd_ext_driver[i];
+ }
+
+ EXTERR("invalid driver index: %d\n", index);
+ return NULL;
}
static void lcd_extern_init_table_dynamic_size_print(
struct lcd_extern_config_s *econf, int flag)
{
int i, j, max_len;
- unsigned char cmd_size;
+ unsigned char type, size;
unsigned char *table;
if (flag) {
@@ -66,81 +65,91 @@
case LCD_EXTERN_I2C:
case LCD_EXTERN_SPI:
while ((i + 1) < max_len) {
- if (table[i] == LCD_EXT_CMD_TYPE_END) {
- printf(" 0x%02x,%d,\n", table[i], table[i+1]);
+ type = table[i];
+ size = table[i + 1];
+ if (type == LCD_EXT_CMD_TYPE_END) {
+ printf(" 0x%02x,%d,\n", type, size);
break;
}
- cmd_size = table[i+1];
- printf(" 0x%02x,%d,", table[i], cmd_size);
- if (cmd_size == 0)
+ printf(" 0x%02x,%d,", type, size);
+ if (size == 0)
goto init_table_dynamic_print_i2c_spi_next;
- if (i + 2 + cmd_size > max_len) {
- printf("cmd_size out of support\n");
+ if (i + 2 + size > max_len) {
+ printf("size out of support\n");
break;
}
- if ((table[i] == LCD_EXT_CMD_TYPE_GPIO) ||
- (table[i] == LCD_EXT_CMD_TYPE_DELAY)) {
- for (j = 0; j < cmd_size; j++)
+ if (type == LCD_EXT_CMD_TYPE_GPIO ||
+ type == LCD_EXT_CMD_TYPE_DELAY) {
+ for (j = 0; j < size; j++)
printf("%d,", table[i+2+j]);
- } else if ((table[i] == LCD_EXT_CMD_TYPE_CMD) ||
- (table[i] == LCD_EXT_CMD_TYPE_CMD2)) {
- for (j = 0; j < cmd_size; j++)
+ } else if ((type == LCD_EXT_CMD_TYPE_CMD) ||
+ (type == LCD_EXT_CMD_TYPE_CMD2) ||
+ (type == LCD_EXT_CMD_TYPE_CMD3) ||
+ (type == LCD_EXT_CMD_TYPE_CMD4) ||
+ (type == LCD_EXT_CMD_TYPE_CMD_BIN) ||
+ (type == LCD_EXT_CMD_TYPE_CMD2_BIN) ||
+ (type == LCD_EXT_CMD_TYPE_CMD3_BIN) ||
+ (type == LCD_EXT_CMD_TYPE_CMD4_BIN) ||
+ (type == LCD_EXT_CMD_TYPE_CMD_BIN_DATA) ||
+ (type == LCD_EXT_CMD_TYPE_CMD2_BIN_DATA) ||
+ (type == LCD_EXT_CMD_TYPE_CMD3_BIN_DATA) ||
+ (type == LCD_EXT_CMD_TYPE_CMD4_BIN_DATA)) {
+ for (j = 0; j < size; j++)
+ printf("0x%02x,", table[i + 2 + j]);
+ } else if ((type == LCD_EXT_CMD_TYPE_CMD_DELAY) ||
+ (type == LCD_EXT_CMD_TYPE_CMD2_DELAY)) {
+ for (j = 0; j < (size - 1); j++)
printf("0x%02x,", table[i+2+j]);
- } else if ((table[i] == LCD_EXT_CMD_TYPE_CMD_DELAY) ||
- (table[i] == LCD_EXT_CMD_TYPE_CMD2_DELAY)) {
- for (j = 0; j < (cmd_size - 1); j++)
- printf("0x%02x,", table[i+2+j]);
- printf("%d,", table[i+cmd_size+1]);
+ printf("%d,", table[i + size + 1]);
} else {
- for (j = 0; j < cmd_size; j++)
+ for (j = 0; j < size; j++)
printf("0x%02x,", table[i+2+j]);
}
init_table_dynamic_print_i2c_spi_next:
printf("\n");
- i += (cmd_size + 2);
+ i += (size + 2);
}
break;
case LCD_EXTERN_MIPI:
while ((i + 1) < max_len) {
- cmd_size = table[i+1];
- if (table[i] == LCD_EXT_CMD_TYPE_END) {
- if (cmd_size == 0xff) {
- printf(" 0x%02x,0x%02x,\n",
- table[i], table[i+1]);
+ type = table[i];
+ size = table[i + 1];
+ if (type == LCD_EXT_CMD_TYPE_END) {
+ if (size == 0xff) {
+ printf("0x%02x,0x%02x,\n", type, size);
break;
}
- if (cmd_size == 0) {
- printf(" 0x%02x,%d,\n",
- table[i], table[i+1]);
+ if (size == 0) {
+ printf("0x%02x,%d,\n", type, size);
break;
}
- cmd_size = 0;
+ size = 0;
}
- printf(" 0x%02x,%d,", table[i], table[i+1]);
- if (cmd_size == 0)
+ printf("0x%02x,%d,", type, table[i + 1]);
+ if (size == 0)
goto init_table_dynamic_print_mipi_next;
- if (i + 2 + cmd_size > max_len) {
- printf("cmd_size out of support\n");
+ if (i + 2 + size > max_len) {
+ printf("size out of support\n");
break;
}
- if ((table[i] == LCD_EXT_CMD_TYPE_GPIO) ||
- (table[i] == LCD_EXT_CMD_TYPE_DELAY)) {
- for (j = 0; j < cmd_size; j++)
+ if (type == LCD_EXT_CMD_TYPE_GPIO ||
+ type == LCD_EXT_CMD_TYPE_DELAY) {
+ for (j = 0; j < size; j++)
printf("%d,", table[i+2+j]);
- } else if ((table[i] & 0xf) == 0x0) {
+ } else if ((type & 0xf) == 0x0) {
printf(" init_%s wrong data_type: 0x%02x\n",
- flag ? "on" : "off", table[i]);
+ flag ? "on" : "off", type);
break;
} else {
- for (j = 0; j < cmd_size; j++)
+ for (j = 0; j < size; j++)
printf("0x%02x,", table[i+2+j]);
}
init_table_dynamic_print_mipi_next:
printf("\n");
- i += (cmd_size + 2);
+ i += (size + 2);
}
break;
default:
@@ -183,17 +192,11 @@
}
}
-static void lcd_extern_info_print(void)
+static void lcd_extern_info_print(struct lcd_extern_config_s *econf)
{
- struct lcd_extern_config_s *econf;
struct lcd_extern_common_s *ecommon;
- if (lcd_ext_driver == NULL) {
- EXTERR("no lcd_extern driver\n");
- return;
- }
- econf = lcd_ext_driver->config;
- ecommon = lcd_ext_driver->common;
+ ecommon = ext_common;
LCDPR("lcd_extern info:\n");
printf("name: %s\n"
@@ -207,14 +210,21 @@
case LCD_EXTERN_I2C:
printf("i2c_addr: 0x%02x\n"
"i2c_addr2: 0x%02x\n"
+ "i2c_addr3: 0x%02x\n"
+ "i2c_addr4: 0x%02x\n"
"i2c_bus: %d\n"
- "i2c_gpio_sck: %d\n"
- "i2c_gpio_sda: %d\n"
+ "i2c_sck_gpio: %d\n"
+ "i2c_sck_gpio_off: %d\n"
+ "i2c_sda_gpio: %d\n"
+ "i2c_sda_gpio_off: %d\n"
"table_loaded: %d\n",
econf->i2c_addr, econf->i2c_addr2,
+ econf->i2c_addr3, econf->i2c_addr4,
ecommon->i2c_bus,
- ecommon->i2c_gpio_sck,
- ecommon->i2c_gpio_sda,
+ ecommon->i2c_sck_gpio,
+ ecommon->i2c_sck_gpio_off,
+ ecommon->i2c_sda_gpio,
+ ecommon->i2c_sda_gpio_off,
econf->table_init_loaded);
if (econf->cmd_size == 0)
break;
@@ -241,8 +251,8 @@
"spi_clk_freq: %d\n"
"spi_clk_pol: %d\n"
"table_loaded: %d\n",
- ecommon->spi_gpio_cs,
- ecommon->spi_gpio_clk, ecommon->spi_gpio_data,
+ econf->spi_gpio_cs,
+ econf->spi_gpio_clk, econf->spi_gpio_data,
econf->spi_clk_freq, econf->spi_clk_pol,
econf->table_init_loaded);
if (econf->cmd_size == 0)
@@ -283,164 +293,39 @@
}
}
-/* ***************************************
- * lcd_extern gpio
- * *************************************** */
-static struct lcd_cpu_gpio_s lcd_ext_gpio[LCD_EXTERN_GPIO_NUM_MAX] = {
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
- {.name = "invalid", .probe_flag = 0, .register_flag = 0,},
-};
-
-static int lcd_ext_gpio_probe(const char *name, unsigned char index)
+int lcd_extern_gpio_get(unsigned char index)
{
- if (name == NULL) {
- LCDERR("bl: %s: gpio name is null\n", __func__);
- return -1;
+ int gpio;
+ char *str;
+#if 0
+ if (!lcd_ext_driver) {
+ EXTERR("no lcd_extern driver\n");
+ return LCD_GPIO_MAX;
}
- if (index >= LCD_EXTERN_GPIO_NUM_MAX) {
- LCDERR("bl: %s: invalid gpio: %d\n", __func__, index);
- return -1;
- }
- if (lcd_ext_gpio[index].probe_flag == 1) {
- if (lcd_debug_print_flag) {
- LCDPR("bl: gpio %s(%d) is already probed\n",
- lcd_ext_gpio[index].name, index);
- }
- return 0;
- }
-
- if (lcd_debug_print_flag)
- LCDPR("bl: probe gpio: %s(%d)\n", name, index);
- strcpy(lcd_ext_gpio[index].name, name);
- /* init gpio flag */
- lcd_ext_gpio[index].probe_flag = 1;
- lcd_ext_gpio[index].register_flag = 0;
-
- return 0;
-}
-
-static int lcd_ext_gpio_request(unsigned char index)
-{
- int ret = 0;
+#endif
if (index >= LCD_EXTERN_GPIO_NUM_MAX) {
- LCDERR("bl: %s: invalid gpio: %d\n", __func__, index);
- return -1;
+ return LCD_GPIO_MAX;
}
- if (lcd_ext_gpio[index].probe_flag == 0) {
- LCDERR("bl: gpio %d is not probed\n", index);
- return -1;
- }
- if (lcd_ext_gpio[index].register_flag == 1) {
- if (lcd_debug_print_flag) {
- LCDPR("bl: gpio %s(%d) is already registered\n",
- lcd_ext_gpio[index].name, index);
- }
- return 0;
- }
-
- ret = dm_gpio_lookup_name(lcd_ext_gpio[index].name, &lcd_ext_gpio[index].gpio);
- if (ret) {
- LCDERR("bl: lookup gpio: wrong name %s\n", lcd_ext_gpio[index].name);
- return -1;
- }
-
- ret = dm_gpio_request(&lcd_ext_gpio[index].gpio, "aml_lcd_bl");
- if (ret) {
- LCDERR("bl: request gpio %s(%d) failed\n", lcd_ext_gpio[index].name, index);
- return -1;
- }
-
- if (lcd_debug_print_flag)
- LCDPR("bl: request gpio: %s(%d)\n", lcd_ext_gpio[index].name, index);
- lcd_ext_gpio[index].register_flag = 1;
-
- return 0;
+ str = ext_common->gpio_name[index];
+ gpio = lcd_gpio_name_map_num(str);
+ return gpio;
}
int lcd_ext_gpio_set(unsigned char index, int value)
{
- int ret = 0;
-
- if (index >= LCD_EXTERN_GPIO_NUM_MAX) {
- LCDERR("bl: %s: invalid gpio: %d\n", __func__, index);
- return -1;
- }
- if (lcd_ext_gpio[index].register_flag == 0) {
- ret = lcd_ext_gpio_request(index);
- if (ret)
- return -1;
- }
-
- switch (value) {
- case LCD_GPIO_OUTPUT_LOW:
- ret = dm_gpio_set_dir_flags(&lcd_ext_gpio[index].gpio, GPIOD_IS_OUT);
- if (ret) {
- LCDERR("bl: set gpio %s(%d) direction failed\n",
- lcd_ext_gpio[index].name, index);
- return ret;
- }
- dm_gpio_set_value(&lcd_ext_gpio[index].gpio, 0);
- break;
- case LCD_GPIO_OUTPUT_HIGH:
- ret = dm_gpio_set_dir_flags(&lcd_ext_gpio[index].gpio, GPIOD_IS_OUT);
- if (ret) {
- LCDERR("bl: set gpio %s(%d) direction failed\n",
- lcd_ext_gpio[index].name, index);
- return ret;
- }
- dm_gpio_set_value(&lcd_ext_gpio[index].gpio, 1);
- break;
- case LCD_GPIO_INPUT:
- default:
- ret = dm_gpio_set_dir_flags(&lcd_ext_gpio[index].gpio, GPIOD_IS_IN);
- if (ret) {
- LCDERR("bl: set gpio %s(%d) direction failed\n",
- lcd_ext_gpio[index].name, index);
- return ret;
- }
- break;
- }
- if (lcd_debug_print_flag) {
- LCDPR("bl: gpio: %s(%d), value: %d\n",
- lcd_ext_gpio[index].name, index, value);
- }
-
- return 0;
-}
-
-unsigned int lcd_ext_gpio_input_get(unsigned char index)
-{
+ int gpio;
int ret;
- unsigned int value;
- if (index >= LCD_EXTERN_GPIO_NUM_MAX) {
- LCDERR("%s: invalid gpio: %d\n", __func__, index);
- return 0;
- }
- if (lcd_ext_gpio[index].register_flag == 0) {
- ret = lcd_ext_gpio_request(index);
- if (ret)
- return 0;
- }
-
- value = dm_gpio_get_value(&lcd_ext_gpio[index].gpio);
-
- return value;
+ gpio = lcd_extern_gpio_get(index);
+ ret = lcd_gpio_set(gpio, value);
+ return ret;
}
-/* *************************************** */
-void lcd_extern_pinmux_set(int status)
+void lcd_extern_pinmux_set(struct lcd_extern_config_s *extconf, int status)
{
int i;
- struct lcd_extern_common_s *extcommon = lcd_ext_driver->common;
-
- if (extcommon->pinmux_valid == 0)
- return;
+ struct lcd_extern_common_s *extcommon = ext_common;
if (lcd_debug_print_flag)
EXTPR("%s: %d\n", __func__, status);
@@ -487,37 +372,20 @@
i++;
}
/* set gpio */
- switch (lcd_ext_driver->config->type) {
- case LCD_EXTERN_I2C:
- if (extcommon->i2c_gpio_sck < LCD_EXTERN_GPIO_NUM_MAX) {
- lcd_ext_gpio_set(extcommon->i2c_gpio_sck,
- extcommon->pinmux_gpio_off);
- }
- if (extcommon->i2c_gpio_sda < LCD_EXTERN_GPIO_NUM_MAX) {
- lcd_ext_gpio_set(extcommon->i2c_gpio_sda,
- extcommon->pinmux_gpio_off);
- }
- break;
- case LCD_EXTERN_SPI:
- if (extcommon->spi_gpio_cs < LCD_EXTERN_GPIO_NUM_MAX) {
- lcd_ext_gpio_set(extcommon->spi_gpio_cs,
- extcommon->pinmux_gpio_off);
- }
- if (extcommon->spi_gpio_clk < LCD_EXTERN_GPIO_NUM_MAX) {
- lcd_ext_gpio_set(extcommon->spi_gpio_clk,
- extcommon->pinmux_gpio_off);
- }
- if (extcommon->spi_gpio_data < LCD_EXTERN_GPIO_NUM_MAX) {
- lcd_ext_gpio_set(extcommon->spi_gpio_data,
- extcommon->pinmux_gpio_off);
- }
- break;
- default:
- break;
+ if (extconf->type == LCD_EXTERN_I2C) {
+ if (extcommon->i2c_sck_gpio < LCD_EXTERN_GPIO_NUM_MAX)
+ lcd_ext_gpio_set
+ (extcommon->i2c_sck_gpio,
+ extcommon->i2c_sck_gpio_off);
+ if (extcommon->i2c_sda_gpio < LCD_EXTERN_GPIO_NUM_MAX)
+ lcd_ext_gpio_set
+ (extcommon->i2c_sda_gpio,
+ extcommon->i2c_sda_gpio_off);
}
}
}
+#ifdef CONFIG_OF_LIBFDT
static unsigned char lcd_extern_get_i2c_bus_str(const char *str)
{
unsigned char i2c_bus;
@@ -554,7 +422,7 @@
{
char *propdata;
- propdata = (char *)fdt_getprop(ext_dt_blob, nodeoffset, propname, NULL);
+ propdata = (char *)fdt_getprop(dt_addr, nodeoffset, propname, NULL);
return propdata;
}
@@ -565,13 +433,13 @@
char *propdata;
sprintf(chlid_node, "/lcd_extern/extern_%d", index);
- nodeoffset = fdt_path_offset(ext_dt_blob, chlid_node);
+ nodeoffset = fdt_path_offset(dt_addr, chlid_node);
if (nodeoffset < 0) {
EXTERR("dts: not find node %s\n", chlid_node);
return nodeoffset;
}
- propdata = (char *)fdt_getprop(ext_dt_blob, nodeoffset, "index", NULL);
+ propdata = (char *)fdt_getprop(dt_addr, nodeoffset, "index", NULL);
if (propdata == NULL) {
EXTERR("get index failed, exit\n");
return -1;
@@ -584,89 +452,45 @@
return nodeoffset;
}
-static int lcd_extern_pinmux_load_from_bsp(struct lcd_extern_common_s *extcommon)
-{
- struct lcd_pinmux_ctrl_s *pinmux;
- unsigned int i, j;
- int set_cnt = 0, clr_cnt = 0;
-
- if (lcd_debug_print_flag)
- EXTPR("%s\n", __func__);
-
- extcommon->pinmux_valid = 0;
- if (extcommon->lcd_ext_pinmux == NULL) {
- if (lcd_debug_print_flag)
- LCDPR("%s: lcd_ext_pinmux is NULL for lcd.c\n", __func__);
- return -1;
- }
-
- pinmux = extcommon->lcd_ext_pinmux;
- for (i = 0; i < LCD_PINMX_MAX; i++) {
- pinmux += i;
- if (strcmp(pinmux->name, "invalid") == 0)
- break;
- if (strcmp(pinmux->name, "extern_on") == 0) {
- for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
- if (pinmux->pinmux_set[j][0] == LCD_PINMUX_END)
- break;
- extcommon->pinmux_set[j][0] = pinmux->pinmux_set[j][0];
- extcommon->pinmux_set[j][1] = pinmux->pinmux_set[j][1];
- set_cnt++;
- }
- for (j = 0; j < LCD_PINMUX_NUM; j++ ) {
- if (pinmux->pinmux_clr[j][0] == LCD_PINMUX_END)
- break;
- extcommon->pinmux_clr[j][0] = pinmux->pinmux_clr[j][0];
- extcommon->pinmux_clr[j][1] = pinmux->pinmux_clr[j][1];
- clr_cnt++;
- }
- if (set_cnt < LCD_PINMUX_NUM) {
- extcommon->pinmux_set[set_cnt][0] = LCD_PINMUX_END;
- extcommon->pinmux_set[set_cnt][1] = 0x0;
- }
- if (clr_cnt < LCD_PINMUX_NUM) {
- extcommon->pinmux_clr[clr_cnt][0] = LCD_PINMUX_END;
- extcommon->pinmux_clr[clr_cnt][1] = 0x0;
- }
- extcommon->pinmux_valid = 1;
- break;
- }
- }
-
- return 0;
-}
-
-static int lcd_extern_get_init_dts(const void *dt_blob, struct lcd_extern_common_s *extcommon)
+static int lcd_extern_get_init_dts(char *dtaddr,
+ struct lcd_extern_common_s *extcommon)
{
int parent_offset;
char *propdata, *p;
const char *str;
+ char propname[30];
+ int lcd_ext_pinctrl_ver = 0;
+ int temp, len = 0;
int i;
- parent_offset = fdt_path_offset(dt_blob, "/lcd_extern");
+ parent_offset = fdt_path_offset(dtaddr, "/lcd_extern");
if (parent_offset < 0) {
- EXTERR("not find /lcd_extern node: %s\n", fdt_strerror(parent_offset));
+ EXTERR("not find /lcd_extern node: %s\n",
+ fdt_strerror(parent_offset));
return -1;
}
- propdata = (char *)fdt_getprop(dt_blob, parent_offset, "key_valid", NULL);
- if (propdata == NULL) {
+ propdata = (char *)fdt_getprop(dtaddr, parent_offset,
+ "key_valid", NULL);
+ if (!propdata) {
if (lcd_debug_print_flag)
EXTPR("failed to get key_valid\n");
extcommon->lcd_ext_key_valid = 0;
} else {
- extcommon->lcd_ext_key_valid = (unsigned char)(be32_to_cpup((u32*)propdata));
+ extcommon->lcd_ext_key_valid =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
}
- propdata = (char *)fdt_getprop(dt_blob, parent_offset, "i2c_bus", NULL);
- if (propdata == NULL)
+ propdata = (char *)fdt_getprop(dtaddr, parent_offset, "i2c_bus", NULL);
+ if (!propdata)
extcommon->i2c_bus = LCD_EXTERN_I2C_BUS_MAX;
else
extcommon->i2c_bus = lcd_extern_get_i2c_bus_str(propdata);
i = 0;
- propdata = (char *)fdt_getprop(dt_blob, parent_offset, "extern_gpio_names", NULL);
- if (propdata == NULL) {
+ propdata = (char *)fdt_getprop(dtaddr, parent_offset,
+ "extern_gpio_names", NULL);
+ if (!propdata) {
if (lcd_debug_print_flag)
EXTPR("failed to get extern_gpio_names\n");
} else {
@@ -677,55 +501,119 @@
str = p;
if (strlen(str) == 0)
break;
- lcd_ext_gpio_probe(str, i);
+ strcpy(extcommon->gpio_name[i], str);
+ if (lcd_debug_print_flag)
+ EXTPR("i=%d, gpio=%s\n", i,
+ extcommon->gpio_name[i]);
i++;
}
}
+ if (i < LCD_EXTERN_GPIO_NUM_MAX)
+ strcpy(extcommon->gpio_name[i], "invalid");
- propdata = (char *)fdt_getprop(dt_blob, parent_offset, "i2c_gpio", NULL);
- if (propdata == NULL) {
- extcommon->i2c_gpio_sck = LCD_EXT_GPIO_INVALID;
- extcommon->i2c_gpio_sda = LCD_EXT_GPIO_INVALID;
+ propdata = (char *)fdt_getprop(dtaddr, parent_offset,
+ "i2c_gpio_off", NULL);
+ if (!propdata) {
+ extcommon->i2c_sck_gpio = LCD_EXT_GPIO_INVALID;
+ extcommon->i2c_sck_gpio_off = 2;
+ extcommon->i2c_sda_gpio = LCD_EXT_GPIO_INVALID;
+ extcommon->i2c_sda_gpio_off = 2;
} else {
- extcommon->i2c_gpio_sck = (unsigned char)be32_to_cpup((u32*)propdata);
- extcommon->i2c_gpio_sda = (unsigned char)be32_to_cpup((((u32*)propdata)+1));
+ extcommon->i2c_sck_gpio =
+ be32_to_cpup((u32 *)propdata);
+ extcommon->i2c_sck_gpio_off =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ extcommon->i2c_sda_gpio =
+ be32_to_cpup((((u32 *)propdata) + 2));
+ extcommon->i2c_sda_gpio_off =
+ be32_to_cpup((((u32 *)propdata) + 3));
}
- propdata = (char *)fdt_getprop(dt_blob, parent_offset, "spi_gpio", NULL);
- if (propdata == NULL) {
- extcommon->spi_gpio_cs = LCD_EXT_GPIO_INVALID;
- extcommon->spi_gpio_clk = LCD_EXT_GPIO_INVALID;
- extcommon->spi_gpio_data = LCD_EXT_GPIO_INVALID;
+ /* pinmux version*/
+ /* new kernel dts pinctrl detect */
+ propdata = (char *)fdt_getprop(dtaddr, parent_offset,
+ "pinctrl_version", NULL);
+ if (propdata) {
+ lcd_ext_pinctrl_ver =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
+ EXTPR("pinctrl_version: %d\n", lcd_ext_pinctrl_ver);
+ }
+ if (lcd_ext_pinctrl_ver) /*use lcd.c config, not read dts*/
+ return 0;
+
+ /* get pinmux */
+ propdata = (char *)fdt_getprop(dtaddr, parent_offset,
+ "pinctrl_names_uboot", NULL);
+ if (!propdata)
+ return 0;
+
+ sprintf(propname, "/pinmux/%s", propdata);
+ EXTPR("find pinctrl_names_uboot: %s\n", propname);
+ parent_offset = fdt_path_offset(dt_addr, propname);
+ if (parent_offset < 0) {
+ EXTPR("no pinmux extern_pins\n");
+ extcommon->pinmux_set[0][0] = LCD_PINMUX_END;
+ extcommon->pinmux_set[0][1] = 0x0;
+ extcommon->pinmux_clr[0][0] = LCD_PINMUX_END;
+ extcommon->pinmux_clr[0][1] = 0x0;
+ return -1;
+ }
+ propdata = (char *)fdt_getprop(dt_addr, parent_offset,
+ "amlogic,setmask", &len);
+ if (!propdata) {
+ EXTERR("failed to get amlogic,setmask\n");
+ extcommon->pinmux_set[0][0] = LCD_PINMUX_END;
+ extcommon->pinmux_set[0][1] = 0x0;
} else {
- extcommon->spi_gpio_cs = (unsigned char)be32_to_cpup((u32*)propdata);
- extcommon->spi_gpio_clk = (unsigned char)be32_to_cpup((((u32*)propdata)+1));
- extcommon->spi_gpio_data = (unsigned char)be32_to_cpup((((u32*)propdata)+2));
+ temp = len / 8;
+ for (i = 0; i < temp; i++) {
+ extcommon->pinmux_set[i][0] =
+ be32_to_cpup((((u32 *)propdata) + 2 * i));
+ extcommon->pinmux_set[i][1] =
+ be32_to_cpup((((u32 *)propdata) + 2 * i + 1));
+ }
+ if (temp < (LCD_PINMUX_NUM - 1)) {
+ extcommon->pinmux_set[temp][0] = LCD_PINMUX_END;
+ extcommon->pinmux_set[temp][1] = 0x0;
+ }
}
- propdata = (char *)fdt_getprop(dt_blob, parent_offset, "pinmux_gpio_off", NULL);
- if (propdata == NULL)
- extcommon->pinmux_gpio_off = 2;
- else
- extcommon->pinmux_gpio_off = be32_to_cpup((u32*)propdata);
-
- lcd_extern_pinmux_load_from_bsp(extcommon);
+ propdata = (char *)fdt_getprop(dt_addr, parent_offset,
+ "amlogic,clrmask", &len);
+ if (!propdata) {
+ EXTERR("failed to get amlogic,clrmask\n");
+ extcommon->pinmux_clr[0][0] = LCD_PINMUX_END;
+ extcommon->pinmux_clr[0][1] = 0x0;
+ } else {
+ temp = len / 8;
+ for (i = 0; i < temp; i++) {
+ extcommon->pinmux_clr[i][0] =
+ be32_to_cpup((((u32 *)propdata) + 2 * i));
+ extcommon->pinmux_clr[i][1] =
+ be32_to_cpup((((u32 *)propdata) + 2 * i + 1));
+ }
+ if (temp < (LCD_PINMUX_NUM - 1)) {
+ extcommon->pinmux_clr[temp][0] = LCD_PINMUX_END;
+ extcommon->pinmux_clr[temp][1] = 0x0;
+ }
+ }
if (lcd_debug_print_flag) {
i = 0;
while (i < LCD_PINMUX_NUM) {
if (extcommon->pinmux_set[i][0] == LCD_PINMUX_END)
break;
- EXTPR("pinmux_set: %d, 0x%08x\n",
- extcommon->pinmux_set[i][0],
- extcommon->pinmux_set[i][1]);
+ EXTPR("pinmux set: %d, 0x%08x\n",
+ extcommon->pinmux_set[i][0],
+ extcommon->pinmux_set[i][1]);
i++;
}
i = 0;
while (i < LCD_PINMUX_NUM) {
if (extcommon->pinmux_clr[i][0] == LCD_PINMUX_END)
break;
- EXTPR("pinmux_clr: %d, 0x%08x\n",
- extcommon->pinmux_clr[i][0],
- extcommon->pinmux_clr[i][1]);
+ EXTPR("pinmux clr: %d, 0x%08x\n",
+ extcommon->pinmux_clr[i][0],
+ extcommon->pinmux_clr[i][1]);
i++;
}
}
@@ -733,8 +621,10 @@
return 0;
}
-static int lcd_extern_init_table_dynamic_size_load_dts(const void *dt_blob,
- int nodeoffset, struct lcd_extern_config_s *extconf, int flag)
+static int lcd_extern_init_table_dynamic_size_load_dts(char *dtaddr,
+ int nodeoffset,
+ struct lcd_extern_config_s *extconf,
+ int flag)
{
unsigned char cmd_size, type;
int i = 0, j, max_len;
@@ -756,7 +646,7 @@
return 0;
}
- propdata = (char *)fdt_getprop(dt_blob, nodeoffset, propname, NULL);
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset, propname, NULL);
if (propdata == NULL) {
EXTERR("%s: get %s failed\n", extconf->name, propname);
table[0] = LCD_EXT_CMD_TYPE_END;
@@ -830,8 +720,10 @@
return 0;
}
-static int lcd_extern_init_table_fixed_size_load_dts(const void *dt_blob,
- int nodeoffset, struct lcd_extern_config_s *extconf, int flag)
+static int lcd_extern_init_table_fixed_size_load_dts(char *dtaddr,
+ int nodeoffset,
+ struct lcd_extern_config_s *extconf,
+ int flag)
{
unsigned char cmd_size;
int i = 0, j, max_len;
@@ -854,8 +746,8 @@
return 0;
}
- propdata = (char *)fdt_getprop(dt_blob, nodeoffset, propname, NULL);
- if (propdata == NULL) {
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset, propname, NULL);
+ if (!propdata) {
EXTERR("%s: get %s failed\n", extconf->name, propname);
table[0] = LCD_EXT_CMD_TYPE_END;
table[1] = 0;
@@ -864,12 +756,14 @@
while (i < max_len) {
if ((i + cmd_size) > max_len) {
- EXTERR("%s: %s cmd_size out of support\n", extconf->name, propname);
+ EXTERR("%s: %s cmd_size out of support\n",
+ extconf->name, propname);
table[i] = LCD_EXT_CMD_TYPE_END;
return -1;
}
for (j = 0; j < cmd_size; j++)
- table[i+j] = (unsigned char)(be32_to_cpup((((u32*)propdata)+i+j)));
+ table[i + j] =
+ (unsigned char)(be32_to_cpup((((u32 *)propdata) + i + j)));
if (table[i] == LCD_EXT_CMD_TYPE_END)
break;
@@ -884,9 +778,9 @@
return 0;
}
-static int lcd_extern_get_config_dts(const void *dt_blob, int index,
- struct lcd_extern_config_s *extconf,
- struct lcd_extern_common_s *extcommon)
+static int lcd_extern_get_config_dts(char *dtaddr, int index,
+ struct lcd_extern_config_s *extconf,
+ struct lcd_extern_common_s *extcommon)
{
int nodeoffset;
char *propdata;
@@ -898,7 +792,7 @@
if (nodeoffset < 0)
return -1;
- propdata = (char *)fdt_getprop(dt_blob, nodeoffset, "index", NULL);
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset, "index", NULL);
if (propdata == NULL) {
extconf->index = LCD_EXTERN_INDEX_INVALID;
EXTERR("get index failed, exit\n");
@@ -909,7 +803,7 @@
if (lcd_debug_print_flag)
EXTPR("index = %d\n", extconf->index);
- propdata = (char *)fdt_getprop(dt_blob, nodeoffset, "extern_name", NULL);
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset, "extern_name", NULL);
if (propdata == NULL) {
str = "invalid_name";
strcpy(extconf->name, str);
@@ -919,7 +813,7 @@
strcpy(extconf->name, propdata);
}
- propdata = (char *)fdt_getprop(dt_blob, nodeoffset, "status", NULL);
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset, "status", NULL);
if (propdata == NULL) {
EXTERR("get status failed, default to disabled\n");
extconf->status = 0;
@@ -932,166 +826,260 @@
if (lcd_debug_print_flag)
EXTPR("%s: status = %d\n", extconf->name, extconf->status);
- propdata = (char *)fdt_getprop(dt_blob, nodeoffset, "type", NULL);
- if (propdata == NULL) {
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset, "type", NULL);
+ if (!propdata) {
extconf->type = LCD_EXTERN_MAX;
EXTERR("get type failed, exit\n");
return -1;
- } else {
- extconf->type = be32_to_cpup((u32*)propdata);
}
+ extconf->type = be32_to_cpup((u32 *)propdata);
+
if (lcd_debug_print_flag)
EXTPR("%s: type = %d\n", extconf->name, extconf->type);
switch (extconf->type) {
case LCD_EXTERN_I2C:
- propdata = (char *)fdt_getprop(dt_blob, nodeoffset, "i2c_address", NULL);
- if (propdata == NULL) {
- EXTERR("%s: get i2c_address failed, exit\n", extconf->name);
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset,
+ "i2c_address", NULL);
+ if (!propdata) {
+ EXTERR("%s: get i2c_address failed, exit\n",
+ extconf->name);
extconf->i2c_addr = 0xff;
return -1;
- } else {
- extconf->i2c_addr = (unsigned char)(be32_to_cpup((u32*)propdata));
}
+ extconf->i2c_addr =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
+
if (lcd_debug_print_flag)
- EXTPR("%s: i2c_address=0x%02x\n", extconf->name, extconf->i2c_addr);
- propdata = (char *)fdt_getprop(dt_blob, nodeoffset, "i2c_address2", NULL);
- if (propdata == NULL) {
- propdata = (char *)fdt_getprop(dt_blob, nodeoffset, "i2c_second_address", NULL);
- if (propdata == NULL) {
+ EXTPR("%s: i2c_address=0x%02x\n",
+ extconf->name, extconf->i2c_addr);
+
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset,
+ "i2c_address2", NULL);
+ if (!propdata) {
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset,
+ "i2c_second_address",
+ NULL);
+ if (!propdata) {
if (lcd_debug_print_flag)
- EXTPR("%s no i2c_address2 exist\n", extconf->name);
+ EXTPR("%s no i2c_address2 exist\n",
+ extconf->name);
extconf->i2c_addr2 = 0xff;
} else {
- extconf->i2c_addr2 = (unsigned char)(be32_to_cpup((u32*)propdata));
+ extconf->i2c_addr2 =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
}
} else {
- extconf->i2c_addr2 = (unsigned char)(be32_to_cpup((u32*)propdata));
+ extconf->i2c_addr2 =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
}
if (lcd_debug_print_flag)
- EXTPR("%s: i2c_address2=0x%02x\n", extconf->name, extconf->i2c_addr2);
+ EXTPR("%s: i2c_address2=0x%02x\n",
+ extconf->name, extconf->i2c_addr2);
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset,
+ "i2c_address3", NULL);
+ if (!propdata) {
+ if (lcd_debug_print_flag)
+ EXTPR("%s no i2c_address3 exist\n",
+ extconf->name);
+ extconf->i2c_addr3 = 0xff;
+ } else {
+ extconf->i2c_addr3 =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
+ }
+ if (lcd_debug_print_flag)
+ EXTPR("%s: i2c_address3=0x%02x\n", extconf->name,
+ extconf->i2c_addr3);
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset,
+ "i2c_address4", NULL);
+ if (!propdata) {
+ if (lcd_debug_print_flag)
+ EXTPR("%s no i2c_address4 exist\n",
+ extconf->name);
+ extconf->i2c_addr4 = 0xff;
+ } else {
+ extconf->i2c_addr4 =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
+ }
+ if (lcd_debug_print_flag)
+ EXTPR("%s: i2c_address4=0x%02x\n", extconf->name,
+ extconf->i2c_addr4);
+ /* compatible for kernel3.14 */
+ if (extcommon->i2c_bus == LCD_EXTERN_I2C_BUS_MAX) {
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset,
+ "i2c_bus", NULL);
+ if (!propdata) {
+ EXTERR("%s: get i2c_bus failed, exit\n",
+ extconf->name);
+ extcommon->i2c_bus = LCD_EXTERN_I2C_BUS_MAX;
+ return -1;
+ }
+ extcommon->i2c_bus =
+ lcd_extern_get_i2c_bus_str(propdata);
+ }
extconf->i2c_bus = extcommon->i2c_bus;
if (lcd_debug_print_flag)
- lcd_extern_i2c_bus_print(extconf->i2c_bus);
- if ((extcommon->i2c_gpio_sck < LCD_EXTERN_GPIO_NUM_MAX) &&
- (extcommon->i2c_gpio_sda < LCD_EXTERN_GPIO_NUM_MAX)) {
- EXTPR("%s: find spi_gpio config: sck=%d, sda=%d\n",
- extconf->name,
- extcommon->i2c_gpio_sck, extcommon->i2c_gpio_sda);
- }
+ aml_lcd_i2c_bus_print(extconf->i2c_bus);
+ if (extcommon->i2c_sck_gpio < LCD_EXTERN_GPIO_NUM_MAX ||
+ extcommon->i2c_sda_gpio < LCD_EXTERN_GPIO_NUM_MAX)
+ EXTPR("%s: find i2c_gpio_off config\n", extconf->name);
- propdata = (char *)fdt_getprop(dt_blob, nodeoffset, "cmd_size", NULL);
- if (propdata == NULL) {
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset,
+ "cmd_size", NULL);
+ if (!propdata) {
EXTPR("%s: no cmd_size\n", extconf->name);
extconf->cmd_size = 0;
} else {
- extconf->cmd_size = (unsigned char)(be32_to_cpup((u32*)propdata));
+ extconf->cmd_size =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
}
if (lcd_debug_print_flag)
- EXTPR("%s: cmd_size=%d\n", extconf->name, extconf->cmd_size);
+ EXTPR("%s: cmd_size=%d\n", extconf->name,
+ extconf->cmd_size);
if (extconf->cmd_size == 0)
break;
if (extconf->cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC) {
ret = lcd_extern_init_table_dynamic_size_load_dts(
- dt_blob, nodeoffset, extconf, 1);
+ dtaddr, nodeoffset, extconf, 1);
if (ret)
break;
ret = lcd_extern_init_table_dynamic_size_load_dts(
- dt_blob, nodeoffset, extconf, 0);
+ dtaddr, nodeoffset, extconf, 0);
} else {
ret = lcd_extern_init_table_fixed_size_load_dts(
- dt_blob, nodeoffset, extconf, 1);
+ dtaddr, nodeoffset, extconf, 1);
if (ret)
break;
ret = lcd_extern_init_table_fixed_size_load_dts(
- dt_blob, nodeoffset, extconf, 0);
+ dtaddr, nodeoffset, extconf, 0);
}
if (ret == 0)
extconf->table_init_loaded = 1;
break;
case LCD_EXTERN_SPI:
- if ((extcommon->spi_gpio_cs < LCD_EXTERN_GPIO_NUM_MAX) &&
- (extcommon->spi_gpio_clk < LCD_EXTERN_GPIO_NUM_MAX) &&
- (extcommon->spi_gpio_data < LCD_EXTERN_GPIO_NUM_MAX)) {
- EXTPR("%s: find spi_gpio config: cs=%d, clk=%d, data=%d\n",
- extconf->name, extcommon->spi_gpio_cs,
- extcommon->spi_gpio_clk, extcommon->spi_gpio_data);
- } else {
- EXTERR("%s: get spi_gpio failed\n", extconf->name);
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset,
+ "gpio_spi_cs", NULL);
+ if (!propdata) {
+ EXTERR("%s: get gpio_spi_cs failed, exit\n",
+ extconf->name);
+ extconf->spi_gpio_cs = LCD_EXT_GPIO_INVALID;
+ return -1;
}
+ extconf->spi_gpio_cs =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
- propdata = (char *)fdt_getprop(dt_blob, nodeoffset, "spi_clk_freq", NULL);
- if (propdata == NULL) {
- EXTERR("%s: get spi_clk_freq failed, default to %dKHz\n",
- extconf->name, LCD_EXT_SPI_CLK_FREQ_DFT);
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset,
+ "gpio_spi_clk", NULL);
+ if (!propdata) {
+ EXTERR("%s: get gpio_spi_clk failed, exit\n",
+ extconf->name);
+ extconf->spi_gpio_clk = LCD_EXT_GPIO_INVALID;
+ return -1;
+ }
+ extconf->spi_gpio_clk =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
+
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset,
+ "gpio_spi_data", NULL);
+ if (!propdata) {
+ EXTERR("%s: get gpio_spi_data failed, exit\n",
+ extconf->name);
+ extconf->spi_gpio_data = LCD_EXT_GPIO_INVALID;
+ return -1;
+ }
+ extconf->spi_gpio_data =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
+
+ if (lcd_debug_print_flag) {
+ EXTPR("%s: gpio_spi cs=%d, clk=%d, data=%d\n",
+ extconf->name, extconf->spi_gpio_cs,
+ extconf->spi_gpio_clk, extconf->spi_gpio_data);
+ }
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset,
+ "spi_clk_freq", NULL);
+ if (!propdata) {
+ EXTERR
+ ("%s: get spi_clk_freq failed, default to %dKHz\n",
+ extconf->name, LCD_EXT_SPI_CLK_FREQ_DFT);
extconf->spi_clk_freq = LCD_EXT_SPI_CLK_FREQ_DFT;
} else {
- extconf->spi_clk_freq = be32_to_cpup((u32*)propdata);
+ extconf->spi_clk_freq =
+ be32_to_cpup((u32 *)propdata);
}
- propdata = (char *)fdt_getprop(dt_blob, nodeoffset, "spi_clk_pol", NULL);
- if (propdata == NULL) {
- EXTERR("%s: get spi_clk_pol failed, default to 1\n", extconf->name);
+
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset,
+ "spi_clk_pol", NULL);
+ if (!propdata) {
+ EXTERR("%s: get spi_clk_pol failed, default to 1\n",
+ extconf->name);
extconf->spi_clk_pol = 1;
} else {
- extconf->spi_clk_pol = (unsigned char)(be32_to_cpup((u32*)propdata));
+ extconf->spi_clk_pol =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
}
if (lcd_debug_print_flag) {
EXTPR("%s: spi clk=%dKHz, clk_pol=%d\n",
- extconf->name, extconf->spi_clk_freq, extconf->spi_clk_pol);
+ extconf->name, extconf->spi_clk_freq,
+ extconf->spi_clk_pol);
}
-
- propdata = (char *)fdt_getprop(dt_blob, nodeoffset, "cmd_size", NULL);
- if (propdata == NULL) {
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset,
+ "cmd_size", NULL);
+ if (!propdata) {
EXTPR("%s: no cmd_size\n", extconf->name);
extconf->cmd_size = 0;
} else {
- extconf->cmd_size = (unsigned char)(be32_to_cpup((u32*)propdata));
+ extconf->cmd_size =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
}
if (lcd_debug_print_flag)
- EXTPR("%s: cmd_size=%d\n", extconf->name, extconf->cmd_size);
+ EXTPR("%s: cmd_size=%d\n", extconf->name,
+ extconf->cmd_size);
if (extconf->cmd_size == 0)
break;
if (extconf->cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC) {
ret = lcd_extern_init_table_dynamic_size_load_dts(
- dt_blob, nodeoffset, extconf, 1);
+ dtaddr, nodeoffset, extconf, 1);
if (ret)
break;
ret = lcd_extern_init_table_dynamic_size_load_dts(
- dt_blob, nodeoffset, extconf, 0);
+ dtaddr, nodeoffset, extconf, 0);
} else {
ret = lcd_extern_init_table_fixed_size_load_dts(
- dt_blob, nodeoffset, extconf, 1);
+ dtaddr, nodeoffset, extconf, 1);
if (ret)
break;
ret = lcd_extern_init_table_fixed_size_load_dts(
- dt_blob, nodeoffset, extconf, 0);
+ dtaddr, nodeoffset, extconf, 0);
}
if (ret == 0)
extconf->table_init_loaded = 1;
break;
case LCD_EXTERN_MIPI:
- propdata = (char *)fdt_getprop(dt_blob, nodeoffset, "cmd_size", NULL);
- if (propdata == NULL) {
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset,
+ "cmd_size", NULL);
+ if (!propdata) {
EXTPR("%s: no cmd_size\n", extconf->name);
extconf->cmd_size = 0;
} else {
- extconf->cmd_size = (unsigned char)(be32_to_cpup((u32*)propdata));
+ extconf->cmd_size =
+ (unsigned char)(be32_to_cpup((u32 *)propdata));
}
if (lcd_debug_print_flag)
- EXTPR("%s: cmd_size=%d\n", extconf->name, extconf->cmd_size);
+ EXTPR("%s: cmd_size=%d\n", extconf->name,
+ extconf->cmd_size);
if (extconf->cmd_size == 0)
break;
if (extconf->cmd_size == LCD_EXT_CMD_SIZE_DYNAMIC) {
ret = lcd_extern_init_table_dynamic_size_load_dts(
- dt_blob, nodeoffset, extconf, 1);
+ dtaddr, nodeoffset, extconf, 1);
if (ret)
break;
ret = lcd_extern_init_table_dynamic_size_load_dts(
- dt_blob, nodeoffset, extconf, 0);
+ dtaddr, nodeoffset, extconf, 0);
if (ret == 0)
extconf->table_init_loaded = 1;
}
@@ -1102,6 +1090,7 @@
return 0;
}
+#endif
static int lcd_extern_init_table_dynamic_size_load_unifykey(
struct lcd_extern_config_s *extconf, unsigned char *p,
@@ -1134,9 +1123,10 @@
while ((i + 1) < max_len) {
/* type */
len += 1;
- ret = aml_lcd_unifykey_len_check(key_len, len);
+ ret = lcd_unifykey_len_check(key_len, len);
if (ret) {
- EXTERR("%s: get %s failed\n", extconf->name, propname);
+ EXTERR("%s: get %s type failed\n",
+ extconf->name, propname);
table[i] = LCD_EXT_CMD_TYPE_END;
table[i+1] = 0;
return -1;
@@ -1144,9 +1134,10 @@
table[i] = *(buf + LCD_UKEY_EXT_INIT + i);
/* cmd_size */
len += 1;
- ret = aml_lcd_unifykey_len_check(key_len, len);
+ ret = lcd_unifykey_len_check(key_len, len);
if (ret) {
- EXTERR("%s: get %s failed\n", extconf->name, propname);
+ EXTERR("%s: get %s cmd_size failed\n",
+ extconf->name, propname);
table[i] = LCD_EXT_CMD_TYPE_END;
table[i+1] = 0;
return -1;
@@ -1159,7 +1150,8 @@
if (cmd_size == 0)
goto init_table_dynamic_i2c_spi_ukey_next;
if ((i + 2 + cmd_size) > max_len) {
- EXTERR("%s: %s cmd_size out of support\n", extconf->name, propname);
+ EXTERR("%s: %s cmd_size out of support\n",
+ extconf->name, propname);
table[i] = LCD_EXT_CMD_TYPE_END;
table[i+1] = 0;
return -1;
@@ -1167,15 +1159,17 @@
/* data */
len += cmd_size;
- ret = aml_lcd_unifykey_len_check(key_len, len);
+ ret = lcd_unifykey_len_check(key_len, len);
if (ret) {
- EXTERR("%s: get %s failed\n", extconf->name, propname);
+ EXTERR("%s: get %s data failed\n",
+ extconf->name, propname);
table[i] = LCD_EXT_CMD_TYPE_END;
table[i+1] = 0;
return -1;
}
for (j = 0; j < cmd_size; j++)
- table[i+2+j] = *(buf + LCD_UKEY_EXT_INIT + i + 2 + j);
+ table[i + 2 + j] =
+ *(buf + LCD_UKEY_EXT_INIT + i + 2 + j);
init_table_dynamic_i2c_spi_ukey_next:
i += (cmd_size + 2);
@@ -1189,9 +1183,10 @@
while ((i + 1) < max_len) { /* type & cmd_size detect */
/* type */
len += 1;
- ret = aml_lcd_unifykey_len_check(key_len, len);
+ ret = lcd_unifykey_len_check(key_len, len);
if (ret) {
- EXTERR("%s: get %s failed\n", extconf->name, propname);
+ EXTERR("%s: get type %s failed\n",
+ extconf->name, propname);
table[i] = LCD_EXT_CMD_TYPE_END;
table[i+1] = 0;
return -1;
@@ -1199,9 +1194,10 @@
table[i] = *(buf + LCD_UKEY_EXT_INIT + i);
/* type */
len += 1;
- ret = aml_lcd_unifykey_len_check(key_len, len);
+ ret = lcd_unifykey_len_check(key_len, len);
if (ret) {
- EXTERR("%s: get %s failed\n", extconf->name, propname);
+ EXTERR("%s: get type %s failed\n",
+ extconf->name, propname);
table[i] = LCD_EXT_CMD_TYPE_END;
table[i+1] = 0;
return -1;
@@ -1224,7 +1220,7 @@
}
len += cmd_size;
- ret = aml_lcd_unifykey_len_check(key_len, len);
+ ret = lcd_unifykey_len_check(key_len, len);
if (ret) {
EXTERR("%s: get %s failed\n", extconf->name, propname);
table[i] = LCD_EXT_CMD_TYPE_END;
@@ -1282,7 +1278,7 @@
return -1;
}
len += cmd_size;
- ret = aml_lcd_unifykey_len_check(key_len, len);
+ ret = lcd_unifykey_len_check(key_len, len);
if (ret) {
EXTERR("%s: get %s failed\n", extconf->name, propname);
table[i] = LCD_EXT_CMD_TYPE_END;
@@ -1312,7 +1308,7 @@
unsigned char *para, *p;
int key_len, len;
const char *str;
- struct aml_lcd_unifykey_header_s ext_header;
+ struct lcd_unifykey_header_s ext_header;
int ret;
extconf->table_init_loaded = 0;
@@ -1323,7 +1319,7 @@
}
key_len = LCD_UKEY_LCD_EXT_SIZE;
memset(para, 0, (sizeof(unsigned char) * key_len));
- ret = aml_lcd_unifykey_get("lcd_extern", para, &key_len);
+ ret = lcd_unifykey_get("lcd_extern", para, &key_len);
if (ret) {
free(para);
return -1;
@@ -1331,7 +1327,7 @@
/* check lcd_extern unifykey length */
len = 10 + 33 + 10;
- ret = aml_lcd_unifykey_len_check(key_len, len);
+ ret = lcd_unifykey_len_check(key_len, len);
if (ret) {
EXTERR("unifykey length is not correct\n");
free(para);
@@ -1339,7 +1335,7 @@
}
/* header: 10byte */
- aml_lcd_unifykey_header_check(para, &ext_header);
+ lcd_unifykey_header_check(para, &ext_header);
if (lcd_debug_print_flag) {
EXTPR("unifykey header:\n");
EXTPR("crc32 = 0x%08x\n", ext_header.crc32);
@@ -1350,9 +1346,9 @@
/* basic: 33byte */
p = para;
- *(p + LCD_UKEY_EXT_NAME - 1) = '\0'; /* ensure string ending */
str = (const char *)(p + LCD_UKEY_HEAD_SIZE);
- strcpy(extconf->name, str);
+ strncpy(extconf->name, str, sizeof(extconf->name) - 1);
+ extconf->name[sizeof(extconf->name) - 1] = '\0';
extconf->index = *(p + LCD_UKEY_EXT_INDEX);
extconf->type = *(p + LCD_UKEY_EXT_TYPE);
extconf->status = *(p + LCD_UKEY_EXT_STATUS);
@@ -1366,21 +1362,35 @@
/* type: 10byte */
switch (extconf->type) {
case LCD_EXTERN_I2C:
- extconf->i2c_addr = *(p + LCD_UKEY_EXT_TYPE_VAL_0);
- extconf->i2c_addr2 = *(p + LCD_UKEY_EXT_TYPE_VAL_1);
+ if (*(p + LCD_UKEY_EXT_TYPE_VAL_0))
+ extconf->i2c_addr = *(p + LCD_UKEY_EXT_TYPE_VAL_0);
+ else
+ extconf->i2c_addr = LCD_EXT_I2C_ADDR_INVALID;
+ if (*(p + LCD_UKEY_EXT_TYPE_VAL_1))
+ extconf->i2c_addr2 = *(p + LCD_UKEY_EXT_TYPE_VAL_1);
+ else
+ extconf->i2c_addr2 = LCD_EXT_I2C_ADDR_INVALID;
+ if (*(p + LCD_UKEY_EXT_TYPE_VAL_4))
+ extconf->i2c_addr3 = *(p + LCD_UKEY_EXT_TYPE_VAL_4);
+ else
+ extconf->i2c_addr3 = LCD_EXT_I2C_ADDR_INVALID;
+ if (*(p + LCD_UKEY_EXT_TYPE_VAL_5))
+ extconf->i2c_addr4 = *(p + LCD_UKEY_EXT_TYPE_VAL_5);
+ else
+ extconf->i2c_addr4 = LCD_EXT_I2C_ADDR_INVALID;
+ /* compatible for kernel3.14 */
+ if (extcommon->i2c_bus == LCD_EXTERN_I2C_BUS_MAX)
+ extcommon->i2c_bus = *(p + LCD_UKEY_EXT_TYPE_VAL_2);
extconf->i2c_bus = extcommon->i2c_bus;
if (lcd_debug_print_flag)
- lcd_extern_i2c_bus_print(extconf->i2c_bus);
- if ((extcommon->i2c_gpio_sck < LCD_EXTERN_GPIO_NUM_MAX) &&
- (extcommon->i2c_gpio_sda < LCD_EXTERN_GPIO_NUM_MAX)) {
- EXTPR("%s: find spi_gpio config: sck=%d, sda=%d\n",
- extconf->name,
- extcommon->i2c_gpio_sck, extcommon->i2c_gpio_sda);
- }
+ aml_lcd_i2c_bus_print(extconf->i2c_bus);
+ if (extcommon->i2c_sck_gpio < LCD_EXTERN_GPIO_NUM_MAX ||
+ extcommon->i2c_sda_gpio < LCD_EXTERN_GPIO_NUM_MAX)
+ EXTPR("find i2c_gpio_off config\n");
extconf->cmd_size = *(p + LCD_UKEY_EXT_TYPE_VAL_3);
if (lcd_debug_print_flag) {
EXTPR("%s: cmd_size = %d\n",
- extconf->name, extconf->cmd_size);
+ extconf->name, extconf->cmd_size);
}
/* init */
@@ -1405,15 +1415,9 @@
extconf->table_init_loaded = 1;
break;
case LCD_EXTERN_SPI:
- if ((extcommon->spi_gpio_cs < LCD_EXTERN_GPIO_NUM_MAX) &&
- (extcommon->spi_gpio_clk < LCD_EXTERN_GPIO_NUM_MAX) &&
- (extcommon->spi_gpio_data < LCD_EXTERN_GPIO_NUM_MAX)) {
- EXTPR("%s: find spi_gpio config: cs=%d, clk=%d, data=%d\n",
- extconf->name, extcommon->spi_gpio_cs,
- extcommon->spi_gpio_clk, extcommon->spi_gpio_data);
- } else {
- EXTERR("%s: get spi_gpio failed\n", extconf->name);
- }
+ extconf->spi_gpio_cs = *(p + LCD_UKEY_EXT_TYPE_VAL_0);
+ extconf->spi_gpio_clk = *(p + LCD_UKEY_EXT_TYPE_VAL_1);
+ extconf->spi_gpio_data = *(p + LCD_UKEY_EXT_TYPE_VAL_2);
extconf->spi_clk_freq = (*(p + LCD_UKEY_EXT_TYPE_VAL_3) |
((*(p + LCD_UKEY_EXT_TYPE_VAL_4)) << 8));
extconf->spi_clk_pol = *(p + LCD_UKEY_EXT_TYPE_VAL_5);
@@ -1472,22 +1476,7 @@
return 0;
}
-static int lcd_extern_get_init_default(const void *dt_blob,
- struct lcd_extern_common_s *extcommon)
-{
- int i = 0;
-
- while (i < LCD_EXTERN_GPIO_NUM_MAX) {
- if (strcmp(extcommon->gpio_name[i], "invalid") == 0)
- break;
- lcd_ext_gpio_probe(extcommon->gpio_name[i], i);
- i++;
- }
-
- return 0;
-}
-
-static int lcd_extern_add_i2c(struct aml_lcd_extern_driver_s *ext_drv)
+static int lcd_extern_add_i2c(struct lcd_extern_driver_s *ext_drv)
{
int ret = -1;
@@ -1502,6 +1491,10 @@
#ifdef CONFIG_AML_LCD_EXTERN_I2C_T5800Q
ret = lcd_extern_i2c_T5800Q_probe(ext_drv);
#endif
+ } else if (strcmp(ext_drv->config->name, "i2c_anx6345") == 0) {
+#ifdef CONFIG_AML_LCD_EXTERN_I2C_ANX6345
+ ret = lcd_extern_i2c_anx6345_probe(ext_drv);
+#endif
} else if (strcmp(ext_drv->config->name, "i2c_DLPC3439") == 0) {
#ifdef CONFIG_AML_LCD_EXTERN_I2C_DLPC3439
ret = lcd_extern_i2c_DLPC3439_probe(ext_drv);
@@ -1514,6 +1507,10 @@
#ifdef CONFIG_AML_LCD_EXTERN_I2C_ANX6862_7911
ret = lcd_extern_i2c_ANX6862_7911_probe(ext_drv);
#endif
+ } else if (strcmp(ext_drv->config->name, "i2c_CS602") == 0) {
+#ifdef CONFIG_AML_LCD_EXTERN_I2C_CS602
+ ret = lcd_extern_i2c_CS602_probe(ext_drv);
+#endif
} else {
EXTERR("invalid driver name: %s\n", ext_drv->config->name);
}
@@ -1521,7 +1518,7 @@
return ret;
}
-static int lcd_extern_add_spi(struct aml_lcd_extern_driver_s *ext_drv)
+static int lcd_extern_add_spi(struct lcd_extern_driver_s *ext_drv)
{
int ret = -1;
@@ -1543,7 +1540,7 @@
return ret;
}
-static int lcd_extern_add_mipi(struct aml_lcd_extern_driver_s *ext_drv)
+static int lcd_extern_add_mipi(struct lcd_extern_driver_s *ext_drv)
{
int ret = -1;
@@ -1555,18 +1552,26 @@
} else {
ret = lcd_extern_mipi_default_probe(ext_drv);
}
+ } else if (strcmp(ext_drv->config->name, "mipi_N070ICN") == 0) {
+#ifdef CONFIG_AML_LCD_EXTERN_MIPI_N070ICN
+ ret = lcd_extern_mipi_N070ICN_probe(ext_drv);
+#endif
+ } else if (strcmp(ext_drv->config->name, "mipi_KD080D13") == 0) {
+#ifdef CONFIG_AML_LCD_EXTERN_MIPI_KD080D13
+ ret = lcd_extern_mipi_KD080D13_probe(ext_drv);
+#endif
} else if (strcmp(ext_drv->config->name, "mipi_TV070WSM") == 0) {
#ifdef CONFIG_AML_LCD_EXTERN_MIPI_TV070WSM
ret = lcd_extern_mipi_TV070WSM_probe(ext_drv);
#endif
- } else if (strcmp(ext_drv->config->name, "mipi_P070ACB") == 0) {
-#ifdef CONFIG_AML_LCD_EXTERN_MIPI_P070ACB
- ret = lcd_extern_mipi_p070acb_probe(ext_drv);
-#endif
} else if (strcmp(ext_drv->config->name, "mipi_ST7701") == 0) {
#ifdef CONFIG_AML_LCD_EXTERN_MIPI_ST7701
ret = lcd_extern_mipi_st7701_probe(ext_drv);
#endif
+ } else if (strcmp(ext_drv->config->name, "mipi_P070ACB") == 0) {
+#ifdef CONFIG_AML_LCD_EXTERN_MIPI_P070ACB
+ ret = lcd_extern_mipi_p070acb_probe(ext_drv);
+#endif
} else if (strcmp(ext_drv->config->name, "mipi_TL050FHV02CT") == 0) {
#ifdef CONFIG_AML_LCD_EXTERN_MIPI_TL050FHV02CT
ret = lcd_extern_mipi_tl050fhv02ct_probe(ext_drv);
@@ -1578,28 +1583,28 @@
return ret;
}
-static int lcd_extern_add_driver(struct lcd_extern_config_s *extconf,
- struct lcd_extern_common_s *extcommon)
+static int lcd_extern_add_driver(int drv_index,
+ struct lcd_extern_config_s *extconf,
+ struct lcd_extern_common_s *extcommon)
{
- struct aml_lcd_extern_driver_s *ext_drv;
+ struct lcd_extern_driver_s *ext_drv;
int ret = -1;
if (extconf->status == 0) {
EXTERR("%s(%d) is disabled\n", extconf->name, extconf->index);
return -1;
}
- lcd_ext_driver = (struct aml_lcd_extern_driver_s *)malloc(
- sizeof(struct aml_lcd_extern_driver_s));
- if (lcd_ext_driver == NULL) {
+ lcd_ext_driver[drv_index] = (struct lcd_extern_driver_s *)
+ malloc(sizeof(struct lcd_extern_driver_s));
+ if (!lcd_ext_driver[drv_index]) {
EXTERR("failed to alloc driver %s[%d], not enough memory\n",
extconf->name, extconf->index);
return -1;
}
/* fill config parameters */
- ext_drv = lcd_ext_driver;
+ ext_drv = lcd_ext_driver[drv_index];
ext_drv->config = extconf;
- ext_drv->common = extcommon;
ext_drv->info_print = lcd_extern_info_print;
ext_drv->reg_read = NULL;
ext_drv->reg_write = NULL;
@@ -1624,45 +1629,37 @@
}
if (ret) {
EXTERR("add driver failed\n");
- free(lcd_ext_driver);
- lcd_ext_driver = NULL;
+ free(lcd_ext_driver[drv_index]);
+ lcd_ext_driver[drv_index] = NULL;
return -1;
}
-#ifdef BL33_DEBUG_PRINT
- EXTPR("add driver %s(%d)\n", ext_drv->config->name, ext_drv->config->index);
-#endif
+ EXTPR("add driver %s(%d)\n", ext_drv->config->name,
+ drv_index);
return ret;
}
-static int lcd_extern_add_driver_default(int index,
- struct lcd_extern_config_s *extconf,
+static int lcd_extern_add_driver_default
+ (int drv_index, struct lcd_extern_config_s *extconf,
struct lcd_extern_common_s *extcommon)
{
- int drv_index = extconf->index;
int ret = -1;
- struct aml_lcd_extern_driver_s *ext_drv;
-
- if (index != drv_index) {
- EXTERR("index %d err, default config index %d\n", index, drv_index);
- return -1;
- }
+ struct lcd_extern_driver_s *ext_drv;
if (extconf->status == 0) {
EXTERR("%s(%d) is disabled\n", extconf->name, drv_index);
return -1;
}
- lcd_ext_driver = (struct aml_lcd_extern_driver_s *)malloc(
- sizeof(struct aml_lcd_extern_driver_s));
- if (lcd_ext_driver == NULL) {
- EXTERR("failed to alloc driver %d, not enough memory\n", index);
+ lcd_ext_driver[drv_index] = (struct lcd_extern_driver_s *)malloc
+ (sizeof(struct lcd_extern_driver_s));
+ if (!lcd_ext_driver[drv_index]) {
+ EXTERR("failed to alloc driver %d\n", drv_index);
return -1;
}
- ext_drv = lcd_ext_driver;
+ ext_drv = lcd_ext_driver[drv_index];
ext_drv->config = extconf;
- ext_drv->common = extcommon;
ext_drv->config->table_init_loaded = 1;
ext_drv->info_print = lcd_extern_info_print;
ext_drv->reg_read = NULL;
@@ -1673,152 +1670,235 @@
/* add ext_default driver */
if (strcmp(ext_drv->config->name, "ext_default") == 0) {
ret = lcd_extern_default_probe(ext_drv);
- } else if ((strcmp(ext_drv->config->name, "mipi_default") == 0) ||
- (strcmp(ext_drv->config->name, "ext_default") == 0)) {
+ goto add_driver_default_end;
+ }
+ if ((strcmp(ext_drv->config->name, "mipi_default") == 0) ||
+ (strcmp(ext_drv->config->name, "ext_default") == 0)) {
ret = lcd_extern_mipi_default_probe(ext_drv);
- } else if (strcmp(ext_drv->config->name, "i2c_T5800Q") == 0) {
+ goto add_driver_default_end;
+ }
#ifdef CONFIG_AML_LCD_EXTERN_I2C_T5800Q
+ if (strcmp(ext_drv->config->name, "i2c_T5800Q") == 0) {
ret = lcd_extern_i2c_T5800Q_probe(ext_drv);
+ goto add_driver_default_end;
+ }
#endif
- } else if (strcmp(ext_drv->config->name, "i2c_DLPC3439") == 0) {
+#ifdef CONFIG_AML_LCD_EXTERN_I2C_ANX6345
+ if (strcmp(ext_drv->config->name, "i2c_anx6345") == 0) {
+ ret = lcd_extern_i2c_anx6345_probe(ext_drv);
+ goto add_driver_default_end;
+ }
+#endif
#ifdef CONFIG_AML_LCD_EXTERN_I2C_DLPC3439
+ if (strcmp(ext_drv->config->name, "i2c_DLPC3439") == 0) {
ret = lcd_extern_i2c_DLPC3439_probe(ext_drv);
+ goto add_driver_default_end;
+ }
#endif
- } else if (strcmp(ext_drv->config->name, "i2c_RT6947") == 0) {
#ifdef CONFIG_AML_LCD_EXTERN_I2C_RT6947
+ if (strcmp(ext_drv->config->name, "i2c_RT6947") == 0) {
ret = lcd_extern_i2c_RT6947_probe(ext_drv);
+ goto add_driver_default_end;
+ }
#endif
- } else if (strcmp(ext_drv->config->name, "i2c_ANX6862_7911") == 0) {
#ifdef CONFIG_AML_LCD_EXTERN_I2C_ANX6862_7911
+ if (strcmp(ext_drv->config->name, "i2c_ANX6862_7911") == 0) {
ret = lcd_extern_i2c_ANX6862_7911_probe(ext_drv);
+ goto add_driver_default_end;
+ }
#endif
- } else if (strcmp(ext_drv->config->name, "spi_LD070WS2") == 0) {
+#ifdef CONFIG_AML_LCD_EXTERN_I2C_CS602
+ if (strcmp(ext_drv->config->name, "i2c_CS602") == 0) {
+ ret = lcd_extern_i2c_CS602_probe(ext_drv);
+ goto add_driver_default_end;
+ }
+#endif
#ifdef CONFIG_AML_LCD_EXTERN_SPI_LD070WS2
+ if (strcmp(ext_drv->config->name, "spi_LD070WS2") == 0) {
ret = lcd_extern_spi_LD070WS2_probe(ext_drv);
+ goto add_driver_default_end;
+ }
#endif
- } else if (strcmp(ext_drv->config->name, "mipi_TV070WSM") == 0) {
+#ifdef CONFIG_AML_LCD_EXTERN_MIPI_N070ICN
+ if (strcmp(ext_drv->config->name, "mipi_N070ICN") == 0) {
+ ret = lcd_extern_mipi_N070ICN_probe(ext_drv);
+ goto add_driver_default_end;
+ }
+#endif
+#ifdef CONFIG_AML_LCD_EXTERN_MIPI_KD080D13
+ if (strcmp(ext_drv->config->name, "mipi_KD080D13") == 0) {
+ ret = lcd_extern_mipi_KD080D13_probe(ext_drv);
+ goto add_driver_default_end;
+ }
+#endif
#ifdef CONFIG_AML_LCD_EXTERN_MIPI_TV070WSM
+ if (strcmp(ext_drv->config->name, "mipi_TV070WSM") == 0) {
ret = lcd_extern_mipi_TV070WSM_probe(ext_drv);
+ goto add_driver_default_end;
+ }
#endif
- } else if (strcmp(ext_drv->config->name, "mipi_P070ACB") == 0) {
-#ifdef CONFIG_AML_LCD_EXTERN_MIPI_P070ACB
- ret = lcd_extern_mipi_p070acb_probe(ext_drv);
-#endif
- } else if (strcmp(ext_drv->config->name, "mipi_ST7701") == 0) {
#ifdef CONFIG_AML_LCD_EXTERN_MIPI_ST7701
+ if (strcmp(ext_drv->config->name, "mipi_ST7701") == 0) {
ret = lcd_extern_mipi_st7701_probe(ext_drv);
+ goto add_driver_default_end;
+ }
#endif
- } else if (strcmp(ext_drv->config->name, "mipi_TL050FHV02CT") == 0) {
+#ifdef CONFIG_AML_LCD_EXTERN_MIPI_P070ACB
+ if (strcmp(ext_drv->config->name, "mipi_P070ACB") == 0) {
+ ret = lcd_extern_mipi_p070acb_probe(ext_drv);
+ goto add_driver_default_end;
+ }
+#endif
#ifdef CONFIG_AML_LCD_EXTERN_MIPI_TL050FHV02CT
+ if (strcmp(ext_drv->config->name, "mipi_TL050FHV02CT") == 0) {
ret = lcd_extern_mipi_tl050fhv02ct_probe(ext_drv);
+ goto add_driver_default_end;
+ }
#endif
- } else {
- EXTERR("invalid driver name: %s\n", ext_drv->config->name);
- }
+add_driver_default_end:
if (ret) {
- EXTERR("add default driver failed: %s(%d)\n", ext_drv->config->name, index);
- free(lcd_ext_driver);
- lcd_ext_driver = NULL;
- return -1;
+ EXTERR("add driver failed\n");
+ free(lcd_ext_driver[drv_index]);
+ lcd_ext_driver[drv_index] = NULL;
+ return ret;
}
- EXTPR("add default driver: %s(%d)\n", ext_drv->config->name, index);
+ EXTPR("add default driver: %s(%d)\n",
+ ext_drv->config->name, drv_index);
+
return ret;
}
-int aml_lcd_extern_probe(const void *dt_blob, int index)
+int lcd_extern_probe(char *dtaddr, int index)
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
+ struct aml_lcd_drv_s *lcd_drv = lcd_get_driver(0);
struct lcd_extern_config_s *ext_config;
- struct lcd_extern_common_s *ext_common;
- int ret, load_id = 0;
+ int ret, i, load_id = 0;
- if (index >= LCD_EXTERN_INDEX_INVALID) {
+ if (index >= LCD_EXTERN_NUM_MAX) {
EXTERR("invalid index, %s exit\n", __func__);
return -1;
}
- ext_dt_blob = NULL;
- ext_common = &ext_common_dft;
- ext_config = &ext_config_dtf;
-
- /* check dts config */
- if (dt_blob)
- ext_dt_blob = dt_blob;
- ret = fdt_check_header(ext_dt_blob);
- if (ret) {
- EXTERR("check dts: %s, use default parameters\n",
- fdt_strerror(ret));
- } else {
- load_id = 1;
+ if (lcd_extern_drv_cnt >= EXTERN_MUL_MAX) {
+ EXTERR("ext_drv_cnt(%d) is much than max(%d)\n",
+ lcd_extern_drv_cnt, EXTERN_MUL_MAX);
+ return -1;
}
- if (lcd_debug_load_flag)
+ dt_addr = NULL;
+
+ for (i = 0; i < lcd_extern_drv_cnt; i++) {
+ if (lcd_extern_index_lut[i] == index)
+ return 0;
+ }
+
+ lcd_extern_index_lut[lcd_extern_drv_cnt] = index;
+
+ /* check dts config */
+#ifdef CONFIG_OF_LIBFDT
+ if (dtaddr) {
+ dt_addr = dtaddr;
+ if (fdt_check_header(dt_addr) < 0) {
+ EXTERR("check dts: %s, use default parameters\n",
+ fdt_strerror(fdt_check_header(dt_addr)));
+ } else {
+ load_id = 1;
+ }
+ }
+#endif
+
+ if (lcd_debug_test)
load_id = 0;
switch (load_id) {
case 1: /* dts */
+ ext_config = &ext_config_dtf[0];
ext_config->table_init_on_cnt = 0;
ext_config->table_init_off_cnt = 0;
ext_config->table_init_loaded = 0;
- lcd_extern_get_init_dts(ext_dt_blob, ext_common);
- if (lcd_drv->unifykey_test_flag) {
- ext_common->lcd_ext_key_valid = 1;
- LCDPR("force lcd_ext_key_valid to 1\n");
- }
+ lcd_extern_get_init_dts(dtaddr, ext_common);
/* check unifykey config */
if (ext_common->lcd_ext_key_valid) {
- ret = aml_lcd_unifykey_check("lcd_extern");
+ ret = lcd_unifykey_check("lcd_extern");
if (ret == 0) {
EXTPR("load config from unifykey\n");
- ret = lcd_extern_get_config_unifykey(index,
- ext_config, ext_common);
+ ret = lcd_extern_get_config_unifykey
+ (lcd_extern_drv_cnt, ext_config,
+ ext_common);
}
} else {
-#ifdef BL33_DEBUG_PRINT
EXTPR("load config from dts\n");
-#endif
- ret = lcd_extern_get_config_dts(ext_dt_blob, index,
- ext_config, ext_common);
+ ret = lcd_extern_get_config_dts(dtaddr, index,
+ ext_config, ext_common);
}
if (ret == 0)
- ret = lcd_extern_add_driver(ext_config, ext_common);
+ ret = lcd_extern_add_driver(lcd_extern_drv_cnt,
+ ext_config, ext_common);
break;
default: /* default */
+ if (index >= ext_common_dft.lcd_ext_num) {
+ EXTERR("invalid index %d, %s exit\n", index, __func__);
+ return -1;
+ }
+ ext_config = &ext_config_dtf[index];
ext_config->table_init_loaded = 0;
ext_config->i2c_bus = ext_common->i2c_bus;
- lcd_extern_get_init_default(ext_dt_blob, ext_common);
- if (lcd_drv->unifykey_test_flag) {
- ext_common->lcd_ext_key_valid = 1;
- LCDPR("force lcd_ext_key_valid to 1\n");
- }
if (ext_common->lcd_ext_key_valid) {
- ret = aml_lcd_unifykey_check("lcd_extern");
+ ret = lcd_unifykey_check("lcd_extern");
if (ret == 0) {
EXTPR("load config from unifykey\n");
- ret = lcd_extern_get_config_unifykey(index,
- ext_config, ext_common);
+ ret = lcd_extern_get_config_unifykey
+ (lcd_extern_drv_cnt,
+ ext_config, ext_common);
if (ret == 0)
- ret = lcd_extern_add_driver(ext_config, ext_common);
+ ret = lcd_extern_add_driver
+ (lcd_extern_drv_cnt, ext_config,
+ ext_common);
}
} else {
EXTPR("load config from bsp\n");
- ret = lcd_extern_add_driver_default(index, ext_config, ext_common);
+ ret = lcd_extern_add_driver_default
+ (lcd_extern_drv_cnt, ext_config, ext_common);
}
break;
}
- EXTPR("%s %s\n", __func__, (ret ? "failed" : "ok"));
+ if (ret) {
+ EXTERR("%s: add driver failed\n", __func__);
+ return -1;
+ }
+
+ EXTPR("%s: index(%d->%d) ok\n", __func__, index, lcd_extern_drv_cnt);
+ lcd_extern_drv_cnt++;
return ret;
}
-int aml_lcd_extern_remove(void)
+int lcd_extern_remove(void)
{
- if (lcd_ext_driver)
- free(lcd_ext_driver);
- lcd_ext_driver = NULL;
+ int i = 0;
+
+ for (i = 0; i < lcd_extern_drv_cnt; i++) {
+ if (lcd_ext_driver[i])
+ free(lcd_ext_driver[i]);
+ lcd_ext_driver[i] = NULL;
+ }
+
return 0;
}
+int lcd_extern_init(void)
+{
+ int i;
+
+ for (i = 0; i < EXTERN_MUL_MAX; i++) {
+ if (lcd_ext_driver[i])
+ free(lcd_ext_driver[i]);
+ lcd_ext_driver[i] = NULL;
+ lcd_extern_index_lut[i] = LCD_EXTERN_INDEX_INVALID;
+ }
+
+ return 0;
+}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_extern/lcd_extern.h b/drivers/amlogic/media/vout/lcd/lcd_extern/lcd_extern.h
index 5a310ea..8b9d7a1 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_extern/lcd_extern.h
+++ b/drivers/amlogic/media/vout/lcd/lcd_extern/lcd_extern.h
@@ -1,26 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/vout/lcd/lcd_extern/lcd_extern.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef _LCD_EXTERN_H_
#define _LCD_EXTERN_H_
#include <amlogic/media/vout/lcd/lcd_extern.h>
+#include <amlogic/media/vout/lcd/lcd_i2c_dev.h>
#define EXTPR(fmt, args...) printf("lcd extern: "fmt"", ## args)
#define EXTERR(fmt, args...) printf("lcd extern: error: "fmt"", ## args)
@@ -32,53 +18,65 @@
unsigned mux;
};
+#ifdef CONFIG_SYS_I2C_AML
+extern struct i2c_platform g_aml_i2c_plat;
+#endif
extern void udelay(unsigned long usec);
extern void mdelay(unsigned long msec);
-extern void lcd_extern_i2c_bus_print(unsigned char i2c_bus);
-extern int lcd_extern_i2c_write(unsigned char i2c_bus, unsigned i2c_addr,
- unsigned char *buff, unsigned len);
-extern int lcd_extern_i2c_read(unsigned char i2c_bus, unsigned i2c_addr,
- unsigned char *buff, unsigned int len);
-
-extern char *lcd_extern_get_dts_prop(int nodeoffset, char *propname);
-extern int lcd_extern_get_dts_child(int index);
+#ifdef CONFIG_OF_LIBFDT
+char *aml_lcd_extern_get_dts_prop(int nodeoffset, char *propname);
+int aml_lcd_extern_get_dts_child(int index);
+#endif
extern int lcd_ext_gpio_set(unsigned char index, int value);
extern unsigned int lcd_ext_gpio_input_get(unsigned char index);
-extern void lcd_extern_pinmux_set(int status);
+void lcd_extern_pinmux_set(struct lcd_extern_config_s *extconf, int status);
-extern int lcd_extern_default_probe(struct aml_lcd_extern_driver_s *ext_drv);
-extern int lcd_extern_mipi_default_probe(struct aml_lcd_extern_driver_s *ext_drv);
+int lcd_extern_default_probe(struct lcd_extern_driver_s *ext_drv);
+int lcd_extern_mipi_default_probe(struct lcd_extern_driver_s *ext_drv);
#ifdef CONFIG_AML_LCD_EXTERN_I2C_T5800Q
-extern int lcd_extern_i2c_T5800Q_probe(struct aml_lcd_extern_driver_s *ext_drv);
+int lcd_extern_i2c_T5800Q_probe(struct lcd_extern_driver_s *ext_drv);
+#endif
+#ifdef CONFIG_AML_LCD_EXTERN_I2C_ANX6345
+int lcd_extern_i2c_anx6345_probe(struct lcd_extern_driver_s *ext_drv);
#endif
#ifdef CONFIG_AML_LCD_EXTERN_I2C_DLPC3439
-extern int lcd_extern_i2c_DLPC3439_probe(struct aml_lcd_extern_driver_s *ext_drv);
+int lcd_extern_i2c_DLPC3439_probe(struct lcd_extern_driver_s *ext_drv);
#endif
#ifdef CONFIG_AML_LCD_EXTERN_I2C_RT6947
-extern int lcd_extern_i2c_RT6947_probe(struct aml_lcd_extern_driver_s *ext_drv);
+int lcd_extern_i2c_RT6947_probe(struct lcd_extern_driver_s *ext_drv);
+#endif
+#ifdef CONFIG_AML_LCD_EXTERN_I2C_CS602
+int lcd_extern_i2c_CS602_probe(struct lcd_extern_driver_s *ext_drv);
#endif
#ifdef CONFIG_AML_LCD_EXTERN_I2C_ANX6862_7911
-extern int lcd_extern_i2c_ANX6862_7911_probe(struct aml_lcd_extern_driver_s *ext_drv);
+int lcd_extern_i2c_ANX6862_7911_probe(struct lcd_extern_driver_s *ext_drv);
#endif
#ifdef CONFIG_AML_LCD_EXTERN_SPI_LD070WS2
-extern int lcd_extern_spi_LD070WS2_probe(struct aml_lcd_extern_driver_s *ext_drv);
+int lcd_extern_spi_LD070WS2_probe(struct lcd_extern_driver_s *ext_drv);
#endif
#ifdef CONFIG_AML_LCD_EXTERN_MIPI_TV070WSM
-extern int lcd_extern_mipi_TV070WSM_probe(struct aml_lcd_extern_driver_s *ext_drv);
+int lcd_extern_mipi_TV070WSM_probe(struct lcd_extern_driver_s *ext_drv);
+#endif
+#ifdef CONFIG_AML_LCD_EXTERN_MIPI_KD080D13
+int lcd_extern_mipi_KD080D13_probe(struct lcd_extern_driver_s *ext_drv);
+#endif
+#ifdef CONFIG_AML_LCD_EXTERN_MIPI_TV070WSM
+int aml_lcd_extern_mipi_TV070WSM_probe(struct lcd_extern_driver_s *ext_drv);
+#endif
+
+#ifdef CONFIG_AML_LCD_EXTERN_MIPI_ST7701
+int lcd_extern_mipi_st7701_probe(struct lcd_extern_driver_s *ext_drv);
#endif
#ifdef CONFIG_AML_LCD_EXTERN_MIPI_P070ACB
-extern int lcd_extern_mipi_p070acb_probe(struct aml_lcd_extern_driver_s *ext_drv);
-#endif
-#ifdef CONFIG_AML_LCD_EXTERN_MIPI_ST7701
-extern int lcd_extern_mipi_st7701_probe(struct aml_lcd_extern_driver_s *ext_drv);
+int lcd_extern_mipi_p070acb_probe(struct lcd_extern_driver_s *ext_drv);
#endif
#ifdef CONFIG_AML_LCD_EXTERN_MIPI_TL050FHV02CT
-extern int lcd_extern_mipi_tl050fhv02ct_probe(struct aml_lcd_extern_driver_s *ext_drv);
+int lcd_extern_mipi_tl050fhv02ct_probe(struct lcd_extern_driver_s *ext_drv);
#endif
#endif
diff --git a/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_P070ACB.c b/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_P070ACB.c
index bad54e3..067efed 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_P070ACB.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_P070ACB.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_extern/mipi_P070ACB.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
diff --git a/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_ST7701.c b/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_ST7701.c
index 107fed3..417e498 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_ST7701.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_ST7701.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_extern/mipi_ST7701.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
diff --git a/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_TL050FHV02CT.c b/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_TL050FHV02CT.c
index db138d3..870ee55 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_TL050FHV02CT.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_TL050FHV02CT.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_extern/mipi_TL050FHV02CT.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
diff --git a/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_TV070WSM.c b/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_TV070WSM.c
index 4e41b8d..79a141c 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_TV070WSM.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_TV070WSM.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_extern/mipi_TV070WSM.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
diff --git a/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_default.c b/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_default.c
index 18d4b7f..38e8230 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_default.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_extern/mipi_default.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_extern/mipi_default_drv.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -59,7 +44,7 @@
0xff, 0, /* ending */
};
-static int lcd_extern_driver_update(struct aml_lcd_extern_driver_s *ext_drv)
+static int lcd_extern_driver_update(struct lcd_extern_driver_s *ext_drv)
{
if (ext_drv == NULL) {
EXTERR("%s driver is null\n", LCD_EXTERN_NAME);
@@ -78,7 +63,7 @@
return 0;
}
-int lcd_extern_mipi_default_probe(struct aml_lcd_extern_driver_s *ext_drv)
+int lcd_extern_mipi_default_probe(struct lcd_extern_driver_s *ext_drv)
{
int ret = 0;
diff --git a/drivers/amlogic/media/vout/lcd/lcd_extern/spi_LD070WS2.c b/drivers/amlogic/media/vout/lcd/lcd_extern/spi_LD070WS2.c
index 05c6432..a19e886 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_extern/spi_LD070WS2.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_extern/spi_LD070WS2.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_extern/spi_LD070WS2.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
diff --git a/drivers/amlogic/media/vout/lcd/lcd_gpio.c b/drivers/amlogic/media/vout/lcd/lcd_gpio.c
new file mode 100644
index 0000000..a7ca5ed
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/lcd_gpio.c
@@ -0,0 +1,80 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <errno.h>
+#include <dm.h>
+#include <asm/gpio.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+#include "lcd_reg.h"
+#include "lcd_common.h"
+
+int lcd_gpio_name_map_num(const char *name)
+{
+ int gpio;
+#if defined(CONFIG_DM_GPIO)
+ int ret;
+#endif
+
+#if defined(CONFIG_DM_GPIO)
+ ret = gpio_lookup_name(name, NULL, NULL, (unsigned int *)&gpio);
+ if (ret) {
+ LCDERR("gpio: wrong name %s\n", name);
+ return LCD_GPIO_MAX;
+ }
+#else
+ /* turn the gpio name into a gpio number */
+ gpio = simple_strtoul(name, NULL, 10);
+ if (gpio < 0) {
+ LCDERR("gpio: wrong name %s\n", name);
+ return LCD_GPIO_MAX;
+ }
+#endif
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("gpio: %s, %d\n", name, gpio);
+ return gpio;
+}
+
+int lcd_gpio_set(int gpio, int value)
+{
+ int ret = 0;
+
+ if (gpio >= LCD_GPIO_MAX)
+ return -1;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("gpio: %d, value: %d\n", gpio, value);
+ /* grab the pin before we tweak it */
+ ret = gpio_request(gpio, "aml_lcd_gpio");
+ if (ret && ret != -EBUSY) {
+ LCDERR("gpio: requesting pin %u failed\n", gpio);
+ return -1;
+ }
+
+ /* finally, let's do it: set direction and exec command */
+ switch (value) {
+ case LCD_GPIO_OUTPUT_LOW:
+ case LCD_GPIO_OUTPUT_HIGH:
+ ret = gpio_direction_output(gpio, value);
+ break;
+ case LCD_GPIO_INPUT:
+ default:
+ ret = gpio_direction_input(gpio);
+ break;
+ }
+
+ return 0;
+}
+
+unsigned int lcd_gpio_input_get(int gpio)
+{
+ unsigned int value;
+
+ if (gpio >= LCD_GPIO_MAX)
+ return 0;
+ gpio_direction_input(gpio);
+ value = gpio_get_value(gpio);
+ return value;
+}
+
diff --git a/drivers/amlogic/media/vout/lcd/lcd_i2c_dev.c b/drivers/amlogic/media/vout/lcd/lcd_i2c_dev.c
new file mode 100644
index 0000000..5c11f04
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/lcd_i2c_dev.c
@@ -0,0 +1,126 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/gpio.h>
+#include <fdtdec.h>
+#include <i2c.h>
+#include <dm.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+#include <amlogic/media/vout/lcd/lcd_i2c_dev.h>
+#include "lcd_common.h"
+
+#define LCDI2C_PR(fmt, args...) printf("lcd_i2c: "fmt"", ## args)
+#define LCDI2C_ERR(fmt, args...) printf("lcd_i2c: error: "fmt"", ## args)
+
+struct lcd_i2c_match_s {
+ unsigned char bus_id;
+ char *bus_str;
+};
+
+static struct lcd_i2c_match_s lcd_i2c_match_table[] = {
+ {LCD_EXT_I2C_BUS_0, "i2c_0/a"},
+ {LCD_EXT_I2C_BUS_1, "i2c_1/b"},
+ {LCD_EXT_I2C_BUS_2, "i2c_2/c"},
+ {LCD_EXT_I2C_BUS_3, "i2c_3/d"},
+ {LCD_EXT_I2C_BUS_4, "i2c_4/ao"},
+ {LCD_EXT_I2C_BUS_MAX, "i2c_invalid"},
+};
+
+void aml_lcd_i2c_bus_print(unsigned char i2c_bus)
+{
+ int i, temp = ARRAY_SIZE(lcd_i2c_match_table) - 1;
+
+ for (i = 0; i < ARRAY_SIZE(lcd_i2c_match_table); i++) {
+ if (lcd_i2c_match_table[i].bus_id == i2c_bus) {
+ temp = i;
+ break;
+ }
+ }
+
+ LCDI2C_PR("i2c_bus = %s(%d)\n", lcd_i2c_match_table[temp].bus_str, temp);
+}
+
+int aml_lcd_i2c_write(unsigned char i2c_bus, unsigned int i2c_addr,
+ unsigned char *buff, unsigned int len)
+{
+ unsigned char aml_i2c_bus;
+ struct udevice *i2c_dev;
+ int i, ret = 0;
+ unsigned char data = 0;
+
+ aml_i2c_bus = i2c_bus;
+ ret = i2c_get_chip_for_busnum(aml_i2c_bus, i2c_addr, 1, &i2c_dev);
+ if (ret) {
+ LCDI2C_ERR("no sys aml_i2c_bus %d find\n", aml_i2c_bus);
+ return ret;
+ }
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ printf("%s:", __func__);
+ for (i = 0; i < len; i++)
+ printf(" 0x%02x", buff[i]);
+ printf(" [addr 0x%02x]\n", i2c_addr);
+ }
+
+ if (len < 1) {
+ LCDI2C_ERR("invailed len %d\n", len);
+ return -1;
+ }
+ if (len == 1)
+ ret = dm_i2c_write(i2c_dev, buff[0], &data, len);
+ else if (len > 1)
+ ret = dm_i2c_write(i2c_dev, buff[0], &buff[1], len - 1);
+
+ if (ret) {
+ LCDI2C_ERR("i2c write failed [addr 0x%02x]\n", i2c_addr);
+ return ret;
+ }
+
+ return 0;
+}
+
+int aml_lcd_i2c_read(unsigned char i2c_bus, unsigned int i2c_addr,
+ unsigned char *buff, unsigned int len)
+{
+ unsigned char aml_i2c_bus;
+ struct udevice *i2c_dev;
+ int ret = 0, i;
+
+ aml_i2c_bus = i2c_bus;
+ ret = i2c_get_chip_for_busnum(aml_i2c_bus, i2c_addr, 1, &i2c_dev);
+ if (ret) {
+ LCDI2C_ERR("no sys aml_i2c_bus %d find\n", aml_i2c_bus);
+ return ret;
+ }
+
+#if 0
+ ret = i2c_write(i2c_dev, buff[0], &buff[1], 1);
+ if (ret) {
+ LCDI2C_ERR("i2c write failed [addr 0x%02x]\n", i2c_addr);
+ return ret;
+ }
+#endif
+ if (len < 1) {
+ LCDI2C_ERR("invalied len %d\n", len);
+ return -1;
+ }
+
+ ret = dm_i2c_read(i2c_dev, buff[0], buff, len);
+ if (ret) {
+ LCDI2C_ERR("i2c read failed [addr 0x%02x]\n", i2c_addr);
+ return ret;
+ }
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ printf("%s:", __func__);
+ for (i = 0; i < len; i++)
+ printf(" 0x%02x", buff[i]);
+ printf(" [addr 0x%02x]\n", i2c_addr);
+ }
+
+ return 0;
+}
+
diff --git a/drivers/amlogic/media/vout/lcd/lcd_init_test.c b/drivers/amlogic/media/vout/lcd/lcd_init_test.c
new file mode 100644
index 0000000..08f85b9
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/lcd_init_test.c
@@ -0,0 +1,2642 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <linux/kernel.h>
+#ifdef CONFIG_SECURE_POWER_CONTROL
+#include <asm/arch/pwr_ctrl.h>
+#endif
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+#include "lcd_reg.h"
+#include "lcd_common.h"
+
+/*******************************************************************************
+ * vpu/display init
+ ******************************************************************************/
+static unsigned int pll_table[] = {0x0, 0x5, 0xa};
+static unsigned int venc_table[] = {0x0, 0x600, 0x800};
+static unsigned int venc_if_table[] = {0x0, 0x500, 0x600};
+static unsigned int venc_data_table[] = {0x0, 0x100, 0x200};
+#define EDP_AUX_RETRY_CNT 5
+#define EDP_AUX_TIMEOUT 1000
+#define EDP_AUX_INTERVAL 200
+static int dptx_aux_write(int index, unsigned int addr, unsigned int len, unsigned char *buf)
+{
+ unsigned int data, i, state;
+ int retry_cnt = 0, timeout = 0;
+
+aux_write_retry:
+ do {
+ state = dptx_reg_read(index, EDP_TX_AUX_STATE);
+ } while (state & (1 << 1));
+
+ dptx_reg_write(index, EDP_TX_AUX_ADDRESS, addr);
+ for (i = 0; i < len; i++)
+ dptx_reg_write(index, EDP_TX_AUX_WRITE_FIFO, buf[i]);
+
+ dptx_reg_write(index, EDP_TX_AUX_COMMAND, (0x800 | ((len - 1) & 0xf)));
+
+ while (timeout++ < EDP_AUX_TIMEOUT) {
+ udelay(EDP_AUX_INTERVAL);
+ data = dptx_reg_read(index, EDP_TX_AUX_TRANSFER_STATUS);
+ if (data & (1 << 0)) {
+ state = dptx_reg_read(index, EDP_TX_AUX_REPLY_CODE);
+ if (state == 0)
+ return 0;
+ if (state == 1) {
+ LCDPR("edp aux write addr 0x%x NACK!\n", addr);
+ return -1;
+ }
+ if (state == 2)
+ LCDPR(" edp aux write addr 0x%x Defer!\n", addr);
+ break;
+ }
+
+ if (data & (1 << 3)) {
+ LCDPR(" edp aux write addr 0x%x Error!\n", addr);
+ break;
+ }
+ }
+
+ if (retry_cnt++ < EDP_AUX_RETRY_CNT) {
+ udelay(EDP_AUX_INTERVAL);
+ LCDPR("edp aux write addr 0x%x timeout, retry %d\n", addr, retry_cnt);
+ goto aux_write_retry;
+ }
+
+ LCDPR("edp aux write addr 0x%x failed\n", addr);
+ return -1;
+}
+#if 0
+static int dptx_aux_read(int index, unsigned int addr, unsigned int len, unsigned char *buf)
+{
+ unsigned int data, i, state;
+ int retry_cnt = 0, timeout = 0;
+
+aux_read_retry:
+ do {
+ state = dptx_reg_read(index, EDP_TX_AUX_STATE);
+ } while (state & (1 << 1));
+
+ dptx_reg_write(index, EDP_TX_AUX_ADDRESS, addr);
+ dptx_reg_write(index, EDP_TX_AUX_COMMAND, (0x900 | ((len - 1) & 0xf)));
+
+ while (timeout++ < EDP_AUX_TIMEOUT) {
+ udelay(EDP_AUX_INTERVAL);
+ data = dptx_reg_read(index, EDP_TX_AUX_TRANSFER_STATUS);
+ if (data & (1 << 0)) {
+ state = dptx_reg_read(index, EDP_TX_AUX_REPLY_CODE);
+ if (state == 0)
+ goto aux_read_succeed;
+ if (state == 1) {
+ LCDPR("edp aux read addr 0x%x NACK!\n", addr);
+ return -1;
+ }
+ if (state == 2)
+ LCDPR(" edp aux read addr 0x%x Defer!\n", addr);
+ break;
+ }
+
+ if (data & (1 << 3)) {
+ LCDPR(" edp aux read addr 0x%x Error!\n", addr);
+ break;
+ }
+ }
+
+ if (retry_cnt++ < EDP_AUX_RETRY_CNT) {
+ udelay(EDP_AUX_INTERVAL);
+ LCDPR(" edp aux read addr 0x%x timeout, retry %d\n", addr, retry_cnt);
+ goto aux_read_retry;
+ }
+
+ LCDPR("edp aux read addr 0x%x failed\n", addr);
+ return -1;
+
+aux_read_succeed:
+ for (i = 0; i < len; i++)
+ buf[i] = (unsigned char)(dptx_reg_read(index, EDP_TX_AUX_REPLY_DATA));
+
+ return 0;
+}
+#endif
+
+static void dptx_link_fast_training(int index)
+{
+ unsigned char p_data = 0;
+ int ret;
+
+ LCDPR("..... Sending edp training pattern 1 .....\n");
+ dptx_reg_write(index, EDP_TX_SCRAMBLING_DISABLE ,0x1); // disable scrambling
+ dptx_reg_write(index, EDP_TX_TRAINING_PATTERN_SET, 0x1); // set training pattern 1
+
+ p_data = 0x21;
+ ret = dptx_aux_write(index, 0x102, 1, &p_data); // set pattern 1 in the RX
+ if (ret) {
+ LCDPR("..... edp training pattern 1 failed.....\n");
+ //return;
+ }
+
+ udelay(10);
+
+ LCDPR("..... Sending training pattern 2 .....\n");
+ dptx_reg_write(index, EDP_TX_TRAINING_PATTERN_SET, 0x2);
+ p_data = 0x22;
+ ret = dptx_aux_write(index, 0x102, 1, &p_data); // set pattern 2 in the RX
+ if (ret) {
+ LCDPR("..... edp training pattern 2 failed.....\n");
+ //return;
+ }
+
+ udelay(10);
+
+ LCDPR("..... Sending training pattern 3 .....\n");
+ dptx_reg_write(index, EDP_TX_TRAINING_PATTERN_SET, 0x3);
+ p_data = 0x23;
+ ret = dptx_aux_write(index, 0x102, 1, &p_data); // set pattern 3 in the RX
+ if (ret) {
+ LCDPR("..... edp training pattern 3 failed.....\n");
+ //return;
+ }
+
+ udelay(10);
+
+ p_data = 0x20;
+ ret = dptx_aux_write(index, 0x102, 1, &p_data); // pattern off
+ if (ret) {
+ LCDPR("..... edp training pattern off failed.....\n");
+ //return;
+ }
+
+ // disable the training pattern
+ dptx_reg_write(index, EDP_TX_TRAINING_PATTERN_SET, 0x0);
+}
+
+static void dptx_set_msa(int index)
+{
+ unsigned int hactive = 1920;
+ unsigned int vactive = 1080;
+ unsigned int htotal = 2200;
+ unsigned int vtotal = 1120;
+ unsigned int hsw = 44;
+ unsigned int hbp = 148;
+ unsigned int vsw = 5;
+ unsigned int vbp = 30;
+ //unsigned int pclk = 147840000;
+
+ //unsigned int lane_count = 2;
+ unsigned int data_per_lane;
+ unsigned int misc0_data;
+ unsigned int m_vid = 147840; //pclk/1000
+ unsigned int n_vid = 270000; //162000, 270000, 540000
+
+ unsigned int ppc = 1;// 1 pix per clock pix0 only
+ unsigned int cfmt = 0;// RGB
+ unsigned int bpc = 8;// bits per color
+
+ data_per_lane = ((hactive * bpc * 3) + 15) / 16 - 1;
+
+ //bit[0] sync mode (1=sync 0=async)
+ misc0_data = (cfmt << 1) | (1 << 0);
+ misc0_data |= (0x1 << 5); //6bit:0x0, 8bit:0x1, 10bit:0x2, 12bit:0x3
+
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_HTOTAL, htotal);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_VTOTAL, vtotal);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_POLARITY, (0 << 1) | (0 << 0));
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_HSWIDTH, hsw);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_VSWIDTH, vsw);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_HRES, hactive);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_VRES, vactive);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_HSTART, (hsw + hbp));
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_VSTART, (vsw + vbp));
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_MISC0, misc0_data);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_MISC1, 0x00000000);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_M_VID, m_vid); //unit: 1kHz
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_N_VID, n_vid); //unit: 10kHz
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_TRANSFER_UNIT_SIZE, 32);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_DATA_COUNT_PER_LANE, data_per_lane);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_USER_PIXEL_WIDTH, ppc);
+
+ LCDPR(" edp%d MSA done\n", index);
+}
+
+static void dptx_reset(int index)
+{
+ unsigned int data32, bit;
+
+ if (index == 0)
+ bit = 17;
+ else
+ bit = 18;
+
+ // Level reset mail
+ data32 = readl(RESETCTRL_RESET1_MASK);
+ data32 &= (~(0x1 << bit));
+ writel(data32, RESETCTRL_RESET1_MASK);
+ data32 = readl(RESETCTRL_RESET1_LEVEL);
+ data32 &= (~(0x1 << bit));
+ writel(data32, RESETCTRL_RESET1_LEVEL);
+ udelay(1);
+ data32 |= (0x1 << bit);
+ writel(data32, RESETCTRL_RESET1_LEVEL);
+
+ // Set clock-divider for EDP-APB
+ dptx_reg_write(index, EDP_TX_AUX_CLOCK_DIVIDER, 24); // Set Aux channel clk-div: 24MHz
+}
+
+static void dptx_phy_reset(int index)
+{
+ unsigned int data32, bit;
+
+ if (index == 0)
+ bit = 19;
+ else
+ bit = 20;
+
+ // Level reset mail
+ data32 = readl(RESETCTRL_RESET1_MASK);
+ data32 &= (~(0x1 << bit));
+ writel(data32, RESETCTRL_RESET1_MASK);
+ data32 = readl(RESETCTRL_RESET1_LEVEL);
+ data32 &= (~(0x1 << bit));
+ writel(data32, RESETCTRL_RESET1_LEVEL);
+ udelay(1);
+ data32 |= (0x1 << bit);
+ writel(data32, RESETCTRL_RESET1_LEVEL);
+}
+
+static void dptx_init(int index)
+{
+ unsigned int data32, pinmux_bit;
+ unsigned int reg_dphy_tx_ctrl0, reg_dphy_tx_ctrl1;
+
+ switch (index) {
+ case 0:
+ reg_dphy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0;
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1;
+ break;
+ case 1:
+ reg_dphy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL0;
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL1;
+ break;
+ default:
+ return;
+ }
+
+ // Select Data-in
+ //data32 = readl(COMBO_DPHY_CNTL0);
+ //data32 &= (~((0x1 << 0) | (0x1 << 1)));
+ //data32 |= ((0x0 << 0) | (0x1 << 1)); //reg_phy0_din_sel_edp
+ //writel(data32, COMBO_DPHY_CNTL0);
+
+ data32 = (0x1 | (0x1 << 4) | (0x0 << 5) | (0x1 << 6) | (0x1 << 7));
+ writel(data32, reg_dphy_tx_ctrl1);
+ data32 = ((0x4 << 5) | (0x1f << 16));
+ writel(data32, reg_dphy_tx_ctrl0); //select clkdiv20 , datachan-sel
+ data32 = readl(reg_dphy_tx_ctrl0);
+ data32 &= ~(0x1 << 2); //no pn sawp
+ writel(data32, reg_dphy_tx_ctrl0);
+ // Mux pads in combo-phy -- Lanes 0 through 4
+ //data32 = readl(COMBO_DPHY_CNTL1);
+ //data32 &= (~(0x3 | (0x3 << 2) | (0x3 << 4) | (0x3 << 6) | (0x3 << 8)));
+ //data32 |= (0x1 | (0x1 << 2) | (0x1 << 4) | (0x1 << 6) | (0x1 << 8));
+ //writel(data32, COMBO_DPHY_CNTL1); // Select EDP in combo-phy
+
+ //Hot-plug GPIOY_10
+ if (index == 0)
+ pinmux_bit = 8;
+ else
+ pinmux_bit = 12;
+ data32 = readl(PADCTRL_PIN_MUX_REGK);
+ data32 &= (~(0xf << pinmux_bit));
+ data32 |= (0x4 << pinmux_bit);
+ writel(data32, PADCTRL_PIN_MUX_REGK);
+
+ // Set clock-divider for EDP-APB
+ dptx_reg_write(index, EDP_TX_AUX_CLOCK_DIVIDER, 24); // Set Aux channel clk-div: 24MHz
+}
+
+static void dptx_set_phy_clk(int index, uint16_t lnkclk_x100)
+{
+ dptx_phy_reset(index);
+ dptx_reset(index);
+}
+
+static void dptx_set_pixclk_divN(int index, uint32_t N)
+{
+ unsigned int data32;
+ unsigned int sel0; // 1,2,3,4,5,7,8,9,11,13,17,19,23,29,31
+ unsigned int sel1; // 1,2,3,4,5,6,7,8,9,13
+ unsigned int bit_clk_en, bit_div_sel0, bit_div_sel1, reg_vid_pll_div;
+
+ if (index == 0) {
+ bit_clk_en = 24;
+ bit_div_sel0 = 0;
+ bit_div_sel1 = 4;
+ reg_vid_pll_div = COMBO_DPHY_VID_PLL0_DIV;
+ } else {
+ bit_clk_en = 25;
+ bit_div_sel0 = 8;
+ bit_div_sel1 = 12;
+ reg_vid_pll_div = COMBO_DPHY_VID_PLL1_DIV;
+ }
+
+ switch (N) {
+ case 10:
+ sel0 = 4;
+ sel1 = 1;
+ break;
+ case 13:
+ sel0 = 9;
+ sel1 = 0;
+ break;
+ case 18:
+ sel0 = 2;
+ sel1 = 5;
+ break;
+ case 64:
+ sel0 = 6;
+ sel1 = 7;
+ break;
+ default:
+ sel0 = 2;
+ sel1 = 1;
+ break;
+ }
+
+ // Disable edp_div clock
+ //Wr(COMBO_DPHY_EDP_PIXEL_CLK_DIV, 0x0); // Note this register is shared with edp1 so need to set specific bits
+ data32 = readl(COMBO_DPHY_EDP_PIXEL_CLK_DIV);
+ data32 &= (~(0x1 << bit_clk_en));
+ writel(data32, COMBO_DPHY_EDP_PIXEL_CLK_DIV);
+
+ // Disable hdmi clk_div clock output + bypass
+ writel((0x0 << 19) | (0x1 << 18), reg_vid_pll_div);
+
+ // Set EDP clock divider
+ data32 = readl(COMBO_DPHY_EDP_PIXEL_CLK_DIV);
+ data32 &= (~((0xf << bit_div_sel0) | (0xf << bit_div_sel1)));
+ data32 |= ((sel0 << bit_div_sel0) | (sel1 << bit_div_sel1));
+ writel(data32, COMBO_DPHY_EDP_PIXEL_CLK_DIV);
+
+ // Enable hdmi clk_div clock output + bypass
+ writel((0x1 << 19) | (0x1 << 18), reg_vid_pll_div);
+
+ // Enable edp_div clock
+ data32 = readl(COMBO_DPHY_EDP_PIXEL_CLK_DIV);
+ data32 |= (0x1 << bit_clk_en);
+ writel(data32, COMBO_DPHY_EDP_PIXEL_CLK_DIV);
+
+ dptx_reset(index); // Reset controller : IP is sync reset, may not have been reset if
+ // first time video clock
+}
+
+static int dptx_wait_phy_ready(int index)
+{
+ unsigned int data = 0;
+ unsigned int done = 100;
+
+ do {
+ data = dptx_reg_read(index, EDP_TX_PHY_STATUS);
+ if (done < 20) {
+ LCDPR("dptx%d wait phy ready: reg_val=0x%x, wait_count=%u\n",
+ index, data, (100 - done));
+ }
+ done--;
+ udelay(100);
+ }while(((data & 0x7f) != 0x7f) && (done > 0));
+
+ if ((data & 0x7f) == 0x7f)
+ return 0;
+
+ LCDPR(" edp%d tx phy error!\n", index);
+ return -1;
+}
+
+static void edp_power_init(int index)
+{
+#ifdef CONFIG_SECURE_POWER_CONTROL
+//#define PM_EDP0 48
+//#define PM_EDP1 49
+//#define PM_MIPI_DSI1 50
+//#define PM_MIPI_DSI0 41
+ if (index == 0)
+ pwr_ctrl_psci_smc(PM_EDP0, 1);
+ else
+ pwr_ctrl_psci_smc(PM_EDP1, 1);
+#endif
+ LCDPR(" edp power domain on\n");
+}
+
+#define EDP_HPD_TIMEOUT 1000
+static void edp_tx_init(int index)
+{
+ unsigned int hpd_state = 0;
+ unsigned char edptx_auxdata[2];
+ unsigned int offset;
+ int ret, i;
+
+ offset = (venc_table[index] << 2);
+
+ edp_power_init(index);
+
+ dptx_reset(index);
+ dptx_init(index); // initialize aux-channel clk_div
+
+ dptx_set_phy_clk(index, 270); // 2.7GHz link
+ dptx_set_pixclk_divN(index, 18);
+
+ dptx_reset(index);
+ mdelay(10);
+
+ LCDPR(" edp tx reset done, start host\n");
+ writel(0, ENCL_VIDEO_EN + offset);
+
+ // Enable the transmitter
+ //dptx_reg_write(index, EDP_TX_TRANSMITTER_OUTPUT_ENABLE, 0x1);
+ dptx_reg_write(index, EDP_TX_PHY_RESET, 0); // remove the reset on the PHY
+ dptx_wait_phy_ready(index);
+ mdelay(10);
+ dptx_reg_write(index, EDP_TX_TRANSMITTER_OUTPUT_ENABLE, 0x1);
+
+ i = 0;
+ while (i++ < EDP_HPD_TIMEOUT) {
+ hpd_state = dptx_reg_read(index, EDP_TX_AUX_STATE) & 0x1;
+ if (hpd_state)
+ break;
+ mdelay(2);
+ }
+ LCDPR("HPD state: %d, i=%d\n", hpd_state, i);
+
+ // Program Link-rate and Lane_count
+ dptx_reg_write(index, EDP_TX_LINK_BW_SET, 0x0a); // Link-rate
+ dptx_reg_write(index, EDP_TX_LINK_COUNT_SET, 0x02); // Number of Lanes
+
+ // Program Lane count
+ LCDPR("edp set lane bw & count\n");
+ edptx_auxdata[0] = 0x0a; // 2.7GHz
+ edptx_auxdata[1] = 2;
+ ret = dptx_aux_write(index, 0x100, 2, edptx_auxdata);
+ if (ret) {
+ LCDPR("..... edp set lane bw & count failed.....\n");
+ //return;
+ }
+
+ // Power up link
+ LCDPR("edp power up link\n");
+ edptx_auxdata[0] = 0x1;
+ ret = dptx_aux_write(index, 0x600, 1, edptx_auxdata);
+ if (ret) {
+ LCDPR("..... edp power up link failed.....\n");
+ //return;
+ }
+
+ // Fast Link train
+ dptx_link_fast_training(index);
+ //dptx_dpcd_dump();
+
+ dptx_set_msa(index);
+ writel(1, ENCL_VIDEO_EN + offset);
+
+ LCDPR("edp enabling the main stream video\n");
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_ENABLE, 0x1); // Enable main-link
+
+ LCDPR(" edp%d tx finish\n", index);
+}
+
+void lcd_init_pre_edp(int index)
+{
+ unsigned int data32, offset = (pll_table[index] << 2);
+ unsigned int reg_stts, vid2_clk_ctrl, vid2_clk_div, vid2_clk_ctrl2;
+ unsigned int vid_pll_div;
+ unsigned int bit_dphy_rst, bit_dphy_din_sel, bit_dphy_lane_sel, lane_sel_val;
+ int cnt = 0, i;
+
+ switch (index) {
+ case 0:
+ reg_stts = ANACTRL_TCON_PLL0_STS;
+ vid2_clk_ctrl = CLKCTRL_VIID_CLK0_CTRL;
+ vid2_clk_div = CLKCTRL_VIID_CLK0_DIV;
+ vid2_clk_ctrl2 = CLKCTRL_VID_CLK0_CTRL2;
+ vid_pll_div = COMBO_DPHY_VID_PLL0_DIV;
+ bit_dphy_rst = 19;
+ bit_dphy_din_sel = 0;
+ bit_dphy_lane_sel = 0;
+ lane_sel_val = 0x155;
+ break;
+ case 1:
+ reg_stts = ANACTRL_TCON_PLL1_STS;
+ vid2_clk_ctrl = CLKCTRL_VIID_CLK1_CTRL;
+ vid2_clk_div = CLKCTRL_VIID_CLK1_DIV;
+ vid2_clk_ctrl2 = CLKCTRL_VID_CLK1_CTRL2;
+ vid_pll_div = COMBO_DPHY_VID_PLL1_DIV;
+ bit_dphy_rst = 20;
+ bit_dphy_din_sel = 2;
+ bit_dphy_lane_sel = 16;
+ lane_sel_val = 0x155;
+ break;
+ default:
+ LCDERR("%s: invalid index %d\n", __func__, index);
+ return;
+ }
+
+ //1.config pll
+set_pll_retry_edp:
+ writel(0x000f04e1, ANACTRL_TCON_PLL0_CNTL0 + offset);
+ udelay(10);
+ writel(0x200f04e1, ANACTRL_TCON_PLL0_CNTL0 + offset);
+ udelay(10);
+ writel(0x300f04e1, ANACTRL_TCON_PLL0_CNTL0 + offset);
+ udelay(10);
+ writel(0x10000000, ANACTRL_TCON_PLL0_CNTL1 + offset);
+ udelay(10);
+ writel(0x0000110c, ANACTRL_TCON_PLL0_CNTL2 + offset);
+ udelay(10);
+ writel(0x10051400, ANACTRL_TCON_PLL0_CNTL3 + offset);
+ udelay(10);
+ writel(0x000100c0, ANACTRL_TCON_PLL0_CNTL4 + offset);
+ udelay(10);
+ writel(0x008300c0, ANACTRL_TCON_PLL0_CNTL4 + offset);
+ udelay(10);
+ writel(0x340f04e1, ANACTRL_TCON_PLL0_CNTL0 + offset);
+ udelay(10);
+ writel(0x140f04e1, ANACTRL_TCON_PLL0_CNTL0 + offset);
+ udelay(10);
+ writel(0x0000300c, ANACTRL_TCON_PLL0_CNTL2 + offset);
+ udelay(100);
+ i = 0;
+ while (i++ < 200) {
+ udelay(50);
+ if (readl(reg_stts) & 0x80000000)
+ break;
+ }
+ if (!(readl(reg_stts) & 0x80000000)) {
+ if (cnt++ < 20)
+ goto set_pll_retry_edp;
+ else
+ LCDPR(" pll lock failed!!!\n");
+ }
+
+ //2.config divider
+ data32 = readl(vid2_clk_ctrl);
+ //cntrl_clk_en0 disable
+ data32 &= ~(1 << 19);
+ writel(data32, vid2_clk_ctrl);
+ /* Disable the div output clock */
+ data32 = readl(vid_pll_div);
+ //clk_final_en disable ?
+ data32 &= ~(1 << 19);
+ writel(data32, vid_pll_div);
+ //set_preset disable ?
+ data32 &= ~(1 << 15);
+ writel(data32, vid_pll_div);
+
+ data32 = readl(vid_pll_div); //used COMBO not VID
+ data32 |= (1 << 18);
+ writel(data32, vid_pll_div);
+ data32 |= (1 << 19);
+ writel(data32, vid_pll_div);
+
+ //3.config vclk
+ writel(0x00000000, vid2_clk_div);
+ udelay(5);
+ writel(0x00080000, vid2_clk_ctrl);
+ udelay(5);
+ writel(0x00008000, vid2_clk_div);
+ writel(0x00018000, vid2_clk_div);
+ udelay(5);
+ writel(0x00080001, vid2_clk_ctrl);
+ writel(0x00088001, vid2_clk_ctrl);
+ udelay(10);
+ writel(0x00080001, vid2_clk_ctrl);
+ udelay(5);
+ writel(0x00000008, vid2_clk_ctrl2);
+
+ //4. config phy clk
+ //done by edp init
+
+ //5. reset phy
+ data32 = readl(RESETCTRL_RESET1_MASK);
+ data32 &= ~(0x1 << bit_dphy_rst);
+ writel(data32, RESETCTRL_RESET1_MASK);
+ data32 = readl(RESETCTRL_RESET1_LEVEL);
+ data32 &= ~(0x1 << bit_dphy_rst);
+ writel(data32, RESETCTRL_RESET1_LEVEL);
+ udelay(1);
+ data32 |= (0x1 << bit_dphy_rst);
+ writel(data32, RESETCTRL_RESET1_LEVEL);
+ udelay(10);
+
+ data32 = readl(COMBO_DPHY_CNTL0);
+ data32 &= ~(0x3 << bit_dphy_din_sel);
+ data32 |= (0x2 << bit_dphy_din_sel);
+ writel(data32, COMBO_DPHY_CNTL0);
+ data32 = readl(COMBO_DPHY_CNTL1);
+ data32 &= ~(0x3ff << bit_dphy_lane_sel);
+ data32 |= (lane_sel_val << bit_dphy_lane_sel);
+ writel(data32, COMBO_DPHY_CNTL1);
+
+ //6. config phy
+ switch (index) {
+ case 1:
+ writel(0x46770038, ANACTRL_DIF_PHY_CNTL10);
+ writel(0x0000ffff, ANACTRL_DIF_PHY_CNTL11);
+ writel(0x16530028, ANACTRL_DIF_PHY_CNTL12);
+ writel(0x16530028, ANACTRL_DIF_PHY_CNTL13);
+ writel(0x16530028, ANACTRL_DIF_PHY_CNTL14);
+ writel(0x16530028, ANACTRL_DIF_PHY_CNTL15);
+ break;
+ case 0:
+ default:
+ writel(0x46770038, ANACTRL_DIF_PHY_CNTL1);
+ writel(0x0000ffff, ANACTRL_DIF_PHY_CNTL2);
+ writel(0x16530028, ANACTRL_DIF_PHY_CNTL3);
+ writel(0x16530028, ANACTRL_DIF_PHY_CNTL4);
+ writel(0x16530028, ANACTRL_DIF_PHY_CNTL5);
+ writel(0x16530028, ANACTRL_DIF_PHY_CNTL6);
+ break;
+ }
+ writel(0x00406253, ANACTRL_DIF_PHY_CNTL19);
+ writel(0x0, ANACTRL_DIF_PHY_CNTL20);
+ writel(0x0, ANACTRL_DIF_PHY_CNTL21);
+
+ LCDPR(" lcd init pre\n");
+}
+
+static void lcd_venc_set_edp(int index)
+{
+ unsigned int hactive = 1920;
+ unsigned int vactive = 1080;
+ unsigned int htotal = 2200;
+ unsigned int vtotal = 1120;
+ unsigned int hsw = 44;
+ unsigned int hbp = 148;
+ unsigned int vsw = 5;
+ unsigned int vbp = 30;
+ //unsigned int pclk = 147840000;
+ unsigned int data32, offset;
+
+ offset = (venc_table[index] << 2);
+ lcd_vcbus_write(ENCL_VIDEO_EN + offset, 0);
+
+ lcd_vcbus_write(ENCL_VIDEO_MODE + offset, 0x8000);/*bit[15] shadown en*/
+ lcd_vcbus_write(ENCL_VIDEO_MODE_ADV + offset, 0x0418); /* Sampling rate: 1 */
+
+ lcd_vcbus_write(ENCL_VIDEO_FILT_CTRL + offset, 0x1000); /* bypass filter */
+ lcd_vcbus_write(ENCL_VIDEO_MAX_PXCNT + offset, htotal - 1);
+ lcd_vcbus_write(ENCL_VIDEO_MAX_LNCNT + offset, vtotal - 1);
+ lcd_vcbus_write(ENCL_VIDEO_HAVON_BEGIN + offset, hsw + hbp);
+ lcd_vcbus_write(ENCL_VIDEO_HAVON_END + offset, hactive - 1 + hsw + hbp);
+ lcd_vcbus_write(ENCL_VIDEO_VAVON_BLINE + offset, vsw + vbp);
+ lcd_vcbus_write(ENCL_VIDEO_VAVON_ELINE + offset, vactive - 1 + vsw + vbp);
+
+ lcd_vcbus_write(ENCL_VIDEO_HSO_BEGIN + offset, 0);
+ lcd_vcbus_write(ENCL_VIDEO_HSO_END + offset, hsw);
+ lcd_vcbus_write(ENCL_VIDEO_VSO_BEGIN + offset, 0);
+ lcd_vcbus_write(ENCL_VIDEO_VSO_END + offset, 0);
+ lcd_vcbus_write(ENCL_VIDEO_VSO_BLINE + offset, 0);
+ lcd_vcbus_write(ENCL_VIDEO_VSO_ELINE + offset, vsw);
+ lcd_vcbus_write(ENCL_VIDEO_RGBIN_CTRL + offset, 3); //yuv: 1, rgb: 3
+
+ lcd_vcbus_write(ENCL_INBUF_CNTL1 + offset, (5 << 13) | (hactive - 1));
+ lcd_vcbus_write(ENCL_INBUF_CNTL0 + offset, 0x200);
+#if 0
+ /* default colorbar pattern */
+ lcd_vcbus_write(1, ENCL_TST_MDSEL + offset);
+ lcd_vcbus_write(0x200, ENCL_TST_Y + offset);
+ lcd_vcbus_write(0x200, ENCL_TST_CB + offset);
+ lcd_vcbus_write(0x200, ENCL_TST_CR + offset);
+ lcd_vcbus_write(hsw + hbp, ENCL_TST_CLRBAR_STRT + offset);
+ lcd_vcbus_write(240, ENCL_TST_CLRBAR_WIDTH + offset);
+ lcd_vcbus_write(1, ENCL_TST_EN + offset);
+ //lcd_vcbus_write(0x0410, ENCL_VIDEO_MODE_ADV + offset);
+#endif
+ lcd_vcbus_write(ENCL_VIDEO_EN + offset, 1);
+
+ //select venc to edp
+ data32 = (0 << 31) | (0 << 30) | (0 << 29) | (1 << 28);
+ switch (index) {
+ case 0:
+ lcd_vcbus_write(VPU_DISP_VIU0_CTRL, data32);
+ break;
+ case 1:
+ lcd_vcbus_write(VPU_DISP_VIU1_CTRL, data32);
+ break;
+ default:
+ break;
+ }
+
+ //config venc_tcon
+ offset = (venc_data_table[index] << 2);
+ lcd_vcbus_write(LCD_RGB_BASE_ADDR + offset, 0x0);
+ lcd_vcbus_write(LCD_RGB_COEFF_ADDR + offset, 0x400);
+ lcd_vcbus_write(LCD_POL_CNTL_ADDR + offset, (1 << 0));
+
+ /* DE signal */
+ offset = (venc_if_table[index] << 2);
+ lcd_vcbus_write(DE_HS_ADDR + offset, hsw + hbp);
+ lcd_vcbus_write(DE_HE_ADDR + offset, hsw + hbp + hactive);
+ lcd_vcbus_write(DE_VS_ADDR + offset, vsw + vbp);
+ lcd_vcbus_write(DE_VE_ADDR + offset, vsw + vbp + vactive - 1);
+
+ /* Hsync signal */
+ lcd_vcbus_write(HSYNC_HS_ADDR + offset, 0);
+ lcd_vcbus_write(HSYNC_HE_ADDR + offset, hsw);
+ lcd_vcbus_write(HSYNC_VS_ADDR + offset, 0);
+ lcd_vcbus_write(HSYNC_VE_ADDR + offset, vtotal - 1);
+
+ /* Vsync signal */
+ lcd_vcbus_write(VSYNC_HS_ADDR + offset, 0);
+ lcd_vcbus_write(VSYNC_HE_ADDR + offset, 0);
+ lcd_vcbus_write(VSYNC_VS_ADDR + offset, 0);
+ lcd_vcbus_write(VSYNC_VE_ADDR + offset, vsw);
+
+ //select encl
+ offset = (venc_table[index] << 2);
+ lcd_vcbus_write(VPU_VENC_CTRL + offset, 2);
+
+ LCDPR(" lcd venc init\n");
+}
+
+static void mipi_dsi_power_init(int index)
+{
+#ifdef CONFIG_SECURE_POWER_CONTROL
+//#define PM_EDP0 48
+//#define PM_EDP1 49
+//#define PM_MIPI_DSI1 50
+//#define PM_MIPI_DSI0 41
+ if (index == 0)
+ pwr_ctrl_psci_smc(PM_MIPI_DSI0, 1);
+ else
+ pwr_ctrl_psci_smc(PM_MIPI_DSI1, 1);
+#endif
+ LCDPR(" mipi-dsi power domain on\n");
+}
+
+static void mipi_dsi_reset(int index)
+{
+ unsigned int data32, bit_host_reset, bit_phy_reset;
+
+ if (index == 0) {
+ bit_host_reset = 29;
+ bit_phy_reset = 30;
+ } else {
+ bit_host_reset = 31;
+ bit_phy_reset = 28;
+ }
+
+ data32 = readl(RESETCTRL_RESET1_MASK);
+ data32 &= ~((0x1 << bit_host_reset) | (1 << bit_phy_reset));
+ writel(data32, RESETCTRL_RESET1_MASK);
+ data32 = readl(RESETCTRL_RESET1_LEVEL);
+ data32 &= ~((0x1 << bit_host_reset) | (1 << bit_phy_reset));
+ writel(data32, RESETCTRL_RESET1_LEVEL);
+ udelay(1);
+ data32 |= ((0x1 << bit_host_reset) | (1 << bit_phy_reset));
+ writel(data32, RESETCTRL_RESET1_LEVEL);
+}
+
+static void mipi_dsi_tx_init(struct aml_lcd_drv_s *pdrv)
+{
+ mipi_dsi_reset(pdrv->index);
+
+ pdrv->config.timing.bit_rate = 283500000; //378000000;
+ pdrv->config.control.mipi_cfg.clk_factor = 6;//8;
+ mipi_dsi_tx_ctrl(pdrv, 1);
+}
+
+#define MIPI_DSI_1G_TEST 0
+static void lcd_init_pre_mipi_dsi(int index)
+{
+ unsigned int data32, offset = (pll_table[index] << 2);
+ unsigned int reg_stts, vid2_clk_ctrl, vid2_clk_div, vid2_clk_ctrl2;
+ unsigned int vid_pll_div;
+ unsigned int bit_dphy_rst, bit_dphy_lane_sel, lane_sel_val;
+ unsigned int bit_dsi_phy_clk_div, bit_dsi_phy_clk_en, bit_dsi_phy_clk_sel;
+ unsigned int bit_dsi_meas_clk_div, bit_dsi_meas_clk_en, bit_dsi_meas_clk_sel;
+ int cnt = 0, i;
+
+ switch (index) {
+ case 0:
+ reg_stts = ANACTRL_TCON_PLL0_STS;
+ vid2_clk_ctrl = CLKCTRL_VIID_CLK0_CTRL;
+ vid2_clk_div = CLKCTRL_VIID_CLK0_DIV;
+ vid2_clk_ctrl2 = CLKCTRL_VID_CLK0_CTRL2;
+ vid_pll_div = COMBO_DPHY_VID_PLL0_DIV;
+ bit_dphy_rst = 19;
+ bit_dphy_lane_sel = 0;
+ lane_sel_val = 0x0;
+ bit_dsi_phy_clk_div = 0;
+ bit_dsi_phy_clk_en = 8;
+ bit_dsi_phy_clk_sel = 12;
+ bit_dsi_meas_clk_div = 0;
+ bit_dsi_meas_clk_en = 8;
+ bit_dsi_meas_clk_sel = 9;
+ break;
+ case 1:
+ reg_stts = ANACTRL_TCON_PLL1_STS;
+ vid2_clk_ctrl = CLKCTRL_VIID_CLK1_CTRL;
+ vid2_clk_div = CLKCTRL_VIID_CLK1_DIV;
+ vid2_clk_ctrl2 = CLKCTRL_VID_CLK1_CTRL2;
+ vid_pll_div = COMBO_DPHY_VID_PLL1_DIV;
+ bit_dphy_rst = 20;
+ bit_dphy_lane_sel = 16;
+ lane_sel_val = 0x0;
+ bit_dsi_phy_clk_div = 16;
+ bit_dsi_phy_clk_en = 24;
+ bit_dsi_phy_clk_sel = 25;
+ bit_dsi_meas_clk_div = 12;
+ bit_dsi_meas_clk_en = 20;
+ bit_dsi_meas_clk_sel = 21;
+ break;
+ default:
+ LCDERR("%s: invalid index %d\n", __func__, index);
+ return;
+ }
+
+#if (MIPI_DSI_1G_TEST == 1)
+ /*1.config pll: 3984M*/
+set_pll_retry_mipi:
+ writel(0x002f04a6, ANACTRL_TCON_PLL0_CNTL0 + offset);
+ udelay(10);
+ writel(0x202f04a6, ANACTRL_TCON_PLL0_CNTL0 + offset);
+ udelay(10);
+ writel(0x302f04a6, ANACTRL_TCON_PLL0_CNTL0 + offset);
+ udelay(10);
+ writel(0x10000000, ANACTRL_TCON_PLL0_CNTL1 + offset);
+ udelay(10);
+ writel(0x0000110c, ANACTRL_TCON_PLL0_CNTL2 + offset);
+ udelay(10);
+ writel(0x10051400, ANACTRL_TCON_PLL0_CNTL3 + offset);
+ udelay(10);
+ writel(0x000100c0, ANACTRL_TCON_PLL0_CNTL4 + offset);
+ udelay(10);
+ writel(0x008300c0, ANACTRL_TCON_PLL0_CNTL4 + offset);
+ udelay(10);
+ writel(0x342f04a6, ANACTRL_TCON_PLL0_CNTL0 + offset);
+ udelay(10);
+ writel(0x142f04a6, ANACTRL_TCON_PLL0_CNTL0 + offset);
+ udelay(10);
+ writel(0x0000300c, ANACTRL_TCON_PLL0_CNTL2 + offset);
+ udelay(100);
+ i = 0;
+ while (i++ < 200) {
+ udelay(50);
+ if (readl(reg_stts) & 0x80000000)
+ break;
+ }
+ if (!(readl(reg_stts) & 0x80000000)) {
+ if (cnt++ < 20)
+ goto set_pll_retry_mipi;
+ else
+ LCDPR(" pll lock failed!!!\n");
+ }
+
+#else
+ //1.config pll
+set_pll_retry_mipi:
+ writel(0x00b704bd, ANACTRL_TCON_PLL0_CNTL0 + offset);
+ udelay(10);
+ writel(0x20b704bd, ANACTRL_TCON_PLL0_CNTL0 + offset);
+ udelay(10);
+ writel(0x30b704bd, ANACTRL_TCON_PLL0_CNTL0 + offset);
+ udelay(10);
+ writel(0x10000000, ANACTRL_TCON_PLL0_CNTL1 + offset);
+ udelay(10);
+ writel(0x0000110c, ANACTRL_TCON_PLL0_CNTL2 + offset);
+ udelay(10);
+ writel(0x10051400, ANACTRL_TCON_PLL0_CNTL3 + offset);
+ udelay(10);
+ writel(0x000100c0, ANACTRL_TCON_PLL0_CNTL4 + offset);
+ udelay(10);
+ writel(0x008300c0, ANACTRL_TCON_PLL0_CNTL4 + offset);
+ udelay(10);
+ writel(0x34b704bd, ANACTRL_TCON_PLL0_CNTL0 + offset);
+ udelay(10);
+ writel(0x14b704bd, ANACTRL_TCON_PLL0_CNTL0 + offset);
+ udelay(10);
+ writel(0x0000300c, ANACTRL_TCON_PLL0_CNTL2 + offset);
+ udelay(100);
+ i = 0;
+ while (i++ < 200) {
+ udelay(50);
+ if (readl(reg_stts) & 0x80000000)
+ break;
+ }
+ if (!(readl(reg_stts) & 0x80000000)) {
+ if (cnt++ < 20)
+ goto set_pll_retry_mipi;
+ else
+ LCDPR(" pll lock failed!!!\n");
+ }
+#endif
+ //2.config divider
+ data32 = readl(vid2_clk_ctrl);
+ //cntrl_clk_en0 disable
+ data32 &= ~(1 << 19);
+ writel(data32, vid2_clk_ctrl);
+ /* Disable the div output clock */
+ data32 = readl(vid_pll_div);
+ //clk_final_en disable ?
+ data32 &= ~(1 << 19);
+ writel(data32, vid_pll_div);
+ //set_preset disable ?
+ data32 &= ~(1 << 15);
+ writel(data32, vid_pll_div);
+
+ data32 = readl(vid_pll_div); //used COMBO not VID
+ data32 |= (1 << 18);
+ writel(data32, vid_pll_div);
+ data32 |= (1 << 19);
+ writel(data32, vid_pll_div);
+
+ //3.config vclk
+ writel(0x00000000, vid2_clk_div);
+ writel(0x00000005, vid2_clk_div);
+ udelay(5);
+ writel(0x00080000, vid2_clk_ctrl);
+ udelay(5);
+ writel(0x00008005, vid2_clk_div);
+ writel(0x00018005, vid2_clk_div);
+ udelay(5);
+ writel(0x00080001, vid2_clk_ctrl);
+ writel(0x00088001, vid2_clk_ctrl);
+ udelay(10);
+ writel(0x00080001, vid2_clk_ctrl);
+ udelay(5);
+ writel(0x00000008, vid2_clk_ctrl2);
+
+ //mipi-dsi phy clk
+ data32 = readl(CLKCTRL_MIPIDSI_PHY_CLK_CTRL);
+ data32 &= ~((0x7 << bit_dsi_phy_clk_sel) |
+ (0x1 << bit_dsi_phy_clk_en) |
+ (0x7f << bit_dsi_phy_clk_div));
+ data32 |= ((0x0 << bit_dsi_phy_clk_sel) |
+ (0x1 << bit_dsi_phy_clk_en) |
+ (0x0 << bit_dsi_phy_clk_div));
+ writel(data32, CLKCTRL_MIPIDSI_PHY_CLK_CTRL);
+ //mipi-dsi meas clk
+ data32 = readl(CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL);
+ data32 &= ~((0x7 << bit_dsi_meas_clk_sel) |
+ (0x1 << bit_dsi_meas_clk_en) |
+ (0x7f << bit_dsi_meas_clk_div));
+ data32 |= ((0x0 << bit_dsi_meas_clk_sel) |
+ (0x1 << bit_dsi_meas_clk_en) |
+ (0x7 << bit_dsi_meas_clk_div));
+ writel(data32, CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL);
+ writel(data32, CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL);
+
+ //4. reset phy
+ data32 = readl(RESETCTRL_RESET1_MASK);
+ data32 &= ~(0x1 << bit_dphy_rst);
+ writel(data32, RESETCTRL_RESET1_MASK);
+ data32 = readl(RESETCTRL_RESET1_LEVEL);
+ data32 &= ~(0x1 << bit_dphy_rst);
+ writel(data32, RESETCTRL_RESET1_LEVEL);
+ udelay(1);
+ data32 |= (0x1 << bit_dphy_rst);
+ writel(data32, RESETCTRL_RESET1_LEVEL);
+ udelay(10);
+
+ //5.select mipi-dsi
+ data32 = readl(COMBO_DPHY_CNTL1);
+ data32 &= ~(0x3ff << bit_dphy_lane_sel);
+ data32 |= (lane_sel_val << bit_dphy_lane_sel);
+ writel(data32, COMBO_DPHY_CNTL1);
+ //writel(0x0, COMBO_DPHY_CNTL1);
+
+ //6. config phy
+ switch (index) {
+ case 1:
+ writel(0x022a0028, ANACTRL_DIF_PHY_CNTL10);
+ writel(0x0000ffcf, ANACTRL_DIF_PHY_CNTL11);
+ writel(0x022a0028, ANACTRL_DIF_PHY_CNTL12);
+ writel(0x822a0028, ANACTRL_DIF_PHY_CNTL13);
+ writel(0x022a0028, ANACTRL_DIF_PHY_CNTL14);
+ writel(0x022a0028, ANACTRL_DIF_PHY_CNTL15);
+ break;
+ case 0:
+ default:
+ writel(0x022a0028, ANACTRL_DIF_PHY_CNTL1);
+ writel(0x0000ffcf, ANACTRL_DIF_PHY_CNTL2);
+ writel(0x022a0028, ANACTRL_DIF_PHY_CNTL3);
+ writel(0x822a0028, ANACTRL_DIF_PHY_CNTL4);
+ writel(0x022a0028, ANACTRL_DIF_PHY_CNTL5);
+ writel(0x022a0028, ANACTRL_DIF_PHY_CNTL6);
+ break;
+ }
+ writel(0x1e406253, ANACTRL_DIF_PHY_CNTL19);
+ writel(0xffff0000, ANACTRL_DIF_PHY_CNTL20);
+ writel(0x0, ANACTRL_DIF_PHY_CNTL21);
+
+ LCDPR(" lcd init pre\n");
+}
+
+static void lcd_venc_set_mipi_dsi(int index)
+{
+ unsigned int hactive = 1024;
+ unsigned int vactive = 600;
+ unsigned int htotal = 1250;
+ unsigned int vtotal = 630;
+ unsigned int hsw = 80;
+ unsigned int hbp = 100;
+ unsigned int vsw = 5;
+ unsigned int vbp = 20;
+ //unsigned int pclk = 147840000;
+ unsigned int data32, offset;
+
+ offset = (venc_table[index] << 2);
+ writel(0, ENCL_VIDEO_EN + offset);
+
+ writel(0x8000, ENCL_VIDEO_MODE + offset);/*bit[15] shadown en*/
+ writel(0x0418, ENCL_VIDEO_MODE_ADV + offset); /* Sampling rate: 1 */
+
+ writel(0x1000, ENCL_VIDEO_FILT_CTRL + offset); /* bypass filter */
+ writel(htotal - 1, ENCL_VIDEO_MAX_PXCNT + offset);
+ writel(vtotal - 1, ENCL_VIDEO_MAX_LNCNT + offset);
+ writel(hsw + hbp, ENCL_VIDEO_HAVON_BEGIN + offset);
+ writel(hactive - 1 + hsw + hbp, ENCL_VIDEO_HAVON_END + offset);
+ writel(vsw + vbp, ENCL_VIDEO_VAVON_BLINE + offset);
+ writel(vactive - 1 + vsw + vbp, ENCL_VIDEO_VAVON_ELINE + offset);
+
+ writel(0, ENCL_VIDEO_HSO_BEGIN + offset);
+ writel(hsw, ENCL_VIDEO_HSO_END + offset);
+ writel(0, ENCL_VIDEO_VSO_BEGIN + offset);
+ writel(0, ENCL_VIDEO_VSO_END + offset);
+ writel(0, ENCL_VIDEO_VSO_BLINE + offset);
+ writel(vsw, ENCL_VIDEO_VSO_ELINE + offset);
+ writel(3, ENCL_VIDEO_RGBIN_CTRL + offset); //yuv: 1, rgb: 3
+
+ writel((5 << 13) | (hactive - 1), ENCL_INBUF_CNTL1 + offset);
+ writel(0x200, ENCL_INBUF_CNTL0 + offset);
+
+ /* default colorbar pattern */
+ writel(1, ENCL_TST_MDSEL + offset);
+ writel(0x200, ENCL_TST_Y + offset);
+ writel(0x200, ENCL_TST_CB + offset);
+ writel(0x200, ENCL_TST_CR + offset);
+ writel(hsw + hbp, ENCL_TST_CLRBAR_STRT + offset);
+ writel(240, ENCL_TST_CLRBAR_WIDTH + offset);
+ writel(0, ENCL_TST_EN + offset);
+ //writel(0x0410, ENCL_VIDEO_MODE_ADV);
+
+ writel(1, ENCL_VIDEO_EN + offset);
+
+ //select venc to mipi-dsi
+ data32 = (0 << 31) | (0 << 30) | (0 << 29) | (1 << 28);
+ switch (index) {
+ case 0:
+ writel(data32, VPU_DISP_VIU0_CTRL);
+ break;
+ case 1:
+ writel(data32, VPU_DISP_VIU1_CTRL);
+ break;
+ default:
+ break;
+ }
+
+ //config venc_tcon
+ offset = (venc_data_table[index] << 2);
+ writel(0x0, LCD_RGB_BASE_ADDR + offset);
+ writel(0x400, LCD_RGB_COEFF_ADDR + offset);
+ //writel((1 << 0), LCD_POL_CNTL_ADDR);
+
+ /* DE signal */
+ offset = (venc_if_table[index] << 2);
+ writel(hsw + hbp, DE_HS_ADDR + offset);
+ writel(hsw + hbp + hactive, DE_HE_ADDR + offset);
+ writel(vsw + vbp, DE_VS_ADDR + offset);
+ writel(vsw + vbp + vactive - 1, DE_VE_ADDR + offset);
+
+ /* Hsync signal */
+ writel(0, HSYNC_HS_ADDR + offset);
+ writel(hsw, HSYNC_HE_ADDR + offset);
+ writel(0, HSYNC_VS_ADDR + offset);
+ writel(vtotal - 1, HSYNC_VE_ADDR + offset);
+
+ /* Vsync signal */
+ writel(0, VSYNC_HS_ADDR + offset);
+ writel(0, VSYNC_HE_ADDR + offset);
+ writel(0, VSYNC_VS_ADDR + offset);
+ writel(vsw, VSYNC_VE_ADDR + offset);
+
+ //select encl
+ offset = (venc_table[index] << 2);
+ writel(2, VPU_VENC_CTRL + offset);
+
+ LCDPR(" lcd venc init\n");
+}
+
+static void vx1_sw_reset(void)
+{
+ /* force PHY to 0 */
+ lcd_combo_dphy_setb(COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0, 3, 8, 2);
+ lcd_vcbus_write(VBO_SOFT_RST, 0x1ff);
+ udelay(5);
+ /* realease PHY */
+ lcd_combo_dphy_setb(COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0, 0, 8, 2);
+ lcd_vcbus_write(VBO_SOFT_RST, 0);
+}
+
+#define VX1_HPD_WAIT_TIMEOUT 5000 /* 500ms */
+static void vx1_wait_hpd(void)
+{
+ int i = 0;
+ int ret = 1;
+
+ LCDPR("%s:", __func__);
+ while (i++ < VX1_HPD_WAIT_TIMEOUT) {
+ ret = (lcd_vcbus_read(VBO_STATUS_L) >> 6) & 1;
+ if (ret == 0)
+ break;
+ udelay(100);
+ }
+
+ if (ret)
+ printf("hpd=%d\n", ((lcd_vcbus_read(VBO_STATUS_L) >> 6) & 1));
+ else
+ printf("hpd=%d, i=%d\n", ((lcd_vcbus_read(VBO_STATUS_L) >> 6) & 1), i);
+
+ mdelay(10); /* add 10ms delay for compatibility */
+}
+
+#define VX1_LOCKN_WAIT_TIMEOUT 500 /* 500ms */
+static void vx1_wait_stable(void)
+{
+ int i = 0;
+ int ret = 1;
+
+ while (i++ < VX1_LOCKN_WAIT_TIMEOUT) {
+ ret = lcd_vcbus_read(VBO_STATUS_L) & 0x3f;
+ if (ret == 0x20)
+ break;
+ mdelay(1);
+ }
+ LCDPR("%s status: 0x%x, i=%d\n", __func__,
+ lcd_vcbus_read(VBO_STATUS_L), i);
+}
+
+static void vx1_clk_util_set(void)
+{
+ /* set fifo_clk_sel*/
+ lcd_combo_dphy_write(COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0, (3 << 5));
+ /* set cntl_ser_en: 8-channel to 1 */
+ lcd_combo_dphy_setb(COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0, 0xfff, 16, 8);
+
+ /* decoupling fifo enable, gated clock enable */
+ lcd_combo_dphy_write(COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1,
+ (1 << 6) | (1 << 0));
+ /* decoupling fifo write enable after fifo enable */
+ lcd_combo_dphy_setb(COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1, 1, 7, 1);
+}
+
+static int vx1_lanes_set(unsigned int lane_num, unsigned int region_num)
+{
+ unsigned int sublane_num, tmp;
+ unsigned int region_size[4];
+
+ sublane_num = lane_num / region_num; /* lane num in each region */
+ lcd_vcbus_setb(VBO_LANES, (8 - 1), 0, 3);
+ lcd_vcbus_setb(VBO_LANES, (2 - 1), 4, 2);
+ lcd_vcbus_setb(VBO_LANES, (sublane_num - 1), 8, 3);
+ lcd_vcbus_setb(VBO_LANES, (4 - 1), 11, 2);
+
+ region_size[3] = (3840 / 8) * sublane_num;
+ tmp = (3840 % lane_num);
+ region_size[0] = region_size[3] + (((tmp / sublane_num) > 0) ?
+ sublane_num : (tmp % sublane_num));
+ region_size[1] = region_size[3] + (((tmp / sublane_num) > 1) ?
+ sublane_num : (tmp % sublane_num));
+ region_size[2] = region_size[3] + (((tmp / sublane_num) > 2) ?
+ sublane_num : (tmp % sublane_num));
+ lcd_vcbus_write(VBO_REGION_00, region_size[0]);
+ lcd_vcbus_write(VBO_REGION_01, region_size[1]);
+ lcd_vcbus_write(VBO_REGION_02, region_size[2]);
+ lcd_vcbus_write(VBO_REGION_03, region_size[3]);
+
+ lcd_vcbus_write(VBO_ACT_VSIZE, 2160);
+ /* different from FBC code!!! */
+ /* lcd_vcbus_setb(VBO_CTRL_H,0x80,11,5); */
+ /* different from simulation code!!! */
+ lcd_vcbus_setb(VBO_CTRL_H, 0x0, 0, 4);
+ lcd_vcbus_setb(VBO_CTRL_H, 0x1, 9, 1);
+ /* lcd_vcbus_setb(VBO_CTRL_L,enable,0,1); */
+
+ return 0;
+}
+
+static void vx1_sync_pol(int hsync_pol, int vsync_pol)
+{
+ lcd_vcbus_setb(VBO_VIN_CTRL, hsync_pol, 4, 1);
+ lcd_vcbus_setb(VBO_VIN_CTRL, vsync_pol, 5, 1);
+
+ lcd_vcbus_setb(VBO_VIN_CTRL, hsync_pol, 6, 1);
+ lcd_vcbus_setb(VBO_VIN_CTRL, vsync_pol, 7, 1);
+}
+
+static void vx1_wait_timing_stable(void)
+{
+ unsigned int timing_state;
+ int i = 200;
+
+ timing_state = lcd_vcbus_read(VBO_INTR_STATE) & 0x1ff;
+ while ((timing_state) && (i > 0)) {
+ /* clear video timing error intr */
+ lcd_vcbus_setb(VBO_INTR_STATE_CTRL, 0x7, 0, 3);
+ lcd_vcbus_setb(VBO_INTR_STATE_CTRL, 0, 0, 3);
+ mdelay(2);
+ timing_state = lcd_vcbus_read(VBO_INTR_STATE) & 0x1ff;
+ i--;
+ };
+
+ LCDPR("vbyone timing state: 0x%03x, i=%d\n",
+ timing_state, (200 - i));
+
+ mdelay(2);
+}
+
+static void vx1_control_set(unsigned int lane_count, unsigned int region_num)
+{
+ /* int color_fmt; */
+ int vin_color, vin_bpp;
+
+ LCDPR("%s\n", __func__);
+
+ vx1_clk_util_set();
+
+ vin_color = 4; /* fixed RGB */
+ vin_bpp = 0; /* fixed 30bbp 4:4:4 */
+
+
+ /* set Vbyone vin color format */
+ lcd_vcbus_setb(VBO_VIN_CTRL, vin_color, 8, 3);
+ lcd_vcbus_setb(VBO_VIN_CTRL, vin_bpp, 11, 2);
+
+ vx1_lanes_set(lane_count, region_num);
+ /*set hsync/vsync polarity to let the polarity is low active
+ inside the VbyOne */
+ vx1_sync_pol(0, 0);
+
+ /* below line copy from simulation */
+ /* gate the input when vsync asserted */
+ lcd_vcbus_setb(VBO_VIN_CTRL, 1, 0, 2);
+ /* lcd_vcbus_write(VBO_VBK_CTRL_0,0x13);
+ //lcd_vcbus_write(VBO_VBK_CTRL_1,0x56);
+ //lcd_vcbus_write(VBO_HBK_CTRL,0x3478);
+ //lcd_vcbus_setb(VBO_PXL_CTRL,0x2,0,4);
+ //lcd_vcbus_setb(VBO_PXL_CTRL,0x3,VBO_PXL_CTR1_BIT,VBO_PXL_CTR1_WID);
+ //set_vbyone_ctlbits(1,0,0); */
+ /* VBO_RGN_GEN clk always on */
+ lcd_vcbus_setb(VBO_GCLK_MAIN, 2, 2, 2);
+
+ /* PAD select: */
+ if ((lane_count == 1) || (lane_count == 2))
+ lcd_vcbus_setb(LCD_PORT_SWAP, 1, 9, 2);
+ else if (lane_count == 4)
+ lcd_vcbus_setb(LCD_PORT_SWAP, 2, 9, 2);
+ else
+ lcd_vcbus_setb(LCD_PORT_SWAP, 0, 9, 2);
+ /* lcd_vcbus_setb(LCD_PORT_SWAP, 1, 8, 1);//reverse lane output order */
+
+ /* Mux pads in combo-phy: 0 for dsi; 1 for lvds or vbyone; 2 for edp */
+ //lcd_hiu_write(HHI_DSI_LVDS_EDP_CNTL0, 0x1);
+
+ lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 2, 2);
+
+ lcd_vcbus_setb(VBO_CTRL_L, 1, 0, 1);
+
+ /*force vencl clk enable, otherwise, it might auto turn off by mipi DSI
+ //lcd_vcbus_setb(VPU_MISC_CTRL, 1, 0, 1); */
+
+ vx1_wait_timing_stable();
+ vx1_sw_reset();
+}
+
+static void vx1_tx_init(void)
+{
+ unsigned int data32;
+
+ //Hot-plug GPIO
+ data32 = readl(PADCTRL_PIN_MUX_REGK);
+ data32 &= (~((0xf << 8) | (0xf << 16)));
+ data32 |= ((0x3 << 8) | (0x3 << 16));
+ writel(data32, PADCTRL_PIN_MUX_REGK);
+
+ vx1_control_set(8, 2); /* lane_num, region_num */
+ vx1_wait_hpd();
+ vx1_wait_stable();
+
+ LCDPR(" vx1 tx finish\n");
+}
+
+static void lcd_init_pre_vx1(void)
+{
+ unsigned int data32;
+ int cnt = 0, i;
+
+ //1.config pll
+set_pll_retry_vx1:
+ writel(0x000f04f7, ANACTRL_TCON_PLL0_CNTL0);//ok
+ udelay(10);
+ writel(0x200f04f7, ANACTRL_TCON_PLL0_CNTL0);//ok
+ udelay(10);
+ writel(0x300f04f7, ANACTRL_TCON_PLL0_CNTL0);//ok
+ udelay(10);
+ writel(0x10110000, ANACTRL_TCON_PLL0_CNTL1);//ok
+ udelay(10);
+ writel(0x00001108, ANACTRL_TCON_PLL0_CNTL2);//ok
+ udelay(10);
+ writel(0x10051400, ANACTRL_TCON_PLL0_CNTL3);//ok
+ udelay(10);
+ writel(0x010100c0, ANACTRL_TCON_PLL0_CNTL4);//ok
+ udelay(10);
+ writel(0x038300c0, ANACTRL_TCON_PLL0_CNTL4);//ok
+ udelay(10);
+ writel(0x340f04f7, ANACTRL_TCON_PLL0_CNTL0);//ok
+ udelay(10);
+ writel(0x140f04f7, ANACTRL_TCON_PLL0_CNTL0);//ok
+ udelay(10);
+ writel(0x0000300c, ANACTRL_TCON_PLL0_CNTL2);//ok
+ udelay(100);
+ i = 0;
+ while (i++ < 200) {
+ udelay(50);
+ if (readl(ANACTRL_TCON_PLL0_STS) & 0x80000000)
+ break;
+ }
+ if (!(readl(ANACTRL_TCON_PLL0_STS) & 0x80000000)) {
+ if (cnt++ < 20)
+ goto set_pll_retry_vx1;
+ else
+ LCDPR(" pll lock failed!!!\n");
+ }
+
+ //2.config divider
+ data32 = readl(CLKCTRL_VIID_CLK0_CTRL);
+ //cntrl_clk_en0 disable
+ data32 &= ~(1 << 19);
+ writel(data32, CLKCTRL_VIID_CLK0_CTRL);
+ /* Disable the div output clock */
+ data32 = readl(COMBO_DPHY_VID_PLL0_DIV);
+ //clk_final_en disable ?
+ data32 &= ~(1 << 19);
+ writel(data32, COMBO_DPHY_VID_PLL0_DIV);
+ //set_preset disable ?
+ data32 &= ~(1 << 15);
+ writel(data32, COMBO_DPHY_VID_PLL0_DIV);
+
+ lcd_clk_setb(COMBO_DPHY_VID_PLL0_DIV, 0, 18, 1);
+ lcd_clk_setb(COMBO_DPHY_VID_PLL0_DIV, 0, 16, 2);
+ lcd_clk_setb(COMBO_DPHY_VID_PLL0_DIV, 0, 15, 1);
+ lcd_clk_setb(COMBO_DPHY_VID_PLL0_DIV, 0, 0, 14);
+
+ lcd_clk_setb(COMBO_DPHY_VID_PLL0_DIV, 2, 16, 2);
+ lcd_clk_setb(COMBO_DPHY_VID_PLL0_DIV, 1, 15, 1);
+ lcd_clk_setb(COMBO_DPHY_VID_PLL0_DIV, 0x739c, 0, 15);
+ lcd_clk_setb(COMBO_DPHY_VID_PLL0_DIV, 0, 15, 1);
+ data32 = readl(COMBO_DPHY_VID_PLL0_DIV);
+
+ data32 = readl(COMBO_DPHY_VID_PLL0_DIV); //used COMBO not VID
+ data32 |= (1 << 19);
+ writel(data32, COMBO_DPHY_VID_PLL0_DIV);
+
+ //3.config vclk
+ writel(0x00000000, CLKCTRL_VIID_CLK0_DIV);
+ udelay(5);
+ writel(0x00080000, CLKCTRL_VIID_CLK0_CTRL);
+ udelay(5);
+ writel(0x00008000, CLKCTRL_VIID_CLK0_DIV);
+ writel(0x00018000, CLKCTRL_VIID_CLK0_DIV);
+ udelay(5);
+ writel(0x00080001, CLKCTRL_VIID_CLK0_CTRL);
+ writel(0x00088001, CLKCTRL_VIID_CLK0_CTRL);
+ udelay(10);
+ writel(0x00080001, CLKCTRL_VIID_CLK0_CTRL);
+ udelay(5);
+ writel(0x00000008, CLKCTRL_VID_CLK0_CTRL2);
+
+ //4. reset phy
+ data32 = readl(RESETCTRL_RESET1_MASK);
+ data32 &= ~((0x1 << 20) | (0x1 << 19) | (0x1 << 7));
+ writel(data32, RESETCTRL_RESET1_MASK);
+ data32 = readl(RESETCTRL_RESET1_LEVEL);
+ data32 &= ~((0x1 << 20) | (0x1 << 19) | (0x1 << 7));
+ writel(data32, RESETCTRL_RESET1_LEVEL);
+ udelay(1);
+ data32 |= (0x1 << 20) | (0x1 << 19) | (0x1 << 7);
+ writel(data32, RESETCTRL_RESET1_LEVEL);
+ udelay(10);
+
+ //5.select vx1
+ //to analog 8 lane 0=mipi(venc0/1);1=vx1/lvds/edp(venc0/1);2=lvds(only venc2)
+ writel(0x15, COMBO_DPHY_CNTL0);
+ writel(0x55555555, COMBO_DPHY_CNTL1);
+
+ //6. config phy
+ writel(0x26430028, ANACTRL_DIF_PHY_CNTL1);
+ writel(0x0000ffff, ANACTRL_DIF_PHY_CNTL2);
+ writel(0x26530028, ANACTRL_DIF_PHY_CNTL3);
+ writel(0x26530028, ANACTRL_DIF_PHY_CNTL4);
+ writel(0x26530028, ANACTRL_DIF_PHY_CNTL5);
+ writel(0x26530028, ANACTRL_DIF_PHY_CNTL6);
+ writel(0x26530028, ANACTRL_DIF_PHY_CNTL7);
+ writel(0x26530028, ANACTRL_DIF_PHY_CNTL8);
+ writel(0x26530028, ANACTRL_DIF_PHY_CNTL9);
+ writel(0x0, ANACTRL_DIF_PHY_CNTL10);
+ writel(0x0, ANACTRL_DIF_PHY_CNTL11);
+ writel(0x0, ANACTRL_DIF_PHY_CNTL12);
+ writel(0x0, ANACTRL_DIF_PHY_CNTL13);
+ writel(0x0, ANACTRL_DIF_PHY_CNTL14);
+ writel(0x0, ANACTRL_DIF_PHY_CNTL15);
+ writel(0x00401648, ANACTRL_DIF_PHY_CNTL19);
+ writel(0x0, ANACTRL_DIF_PHY_CNTL20);
+ writel(0x0, ANACTRL_DIF_PHY_CNTL21);
+
+ LCDPR(" vx1 init pre\n");
+}
+
+static void lcd_venc_set_vx1(void)
+{
+ unsigned int hactive = 3840;
+ unsigned int vactive = 2160;
+ unsigned int htotal = 4400;
+ unsigned int vtotal = 2250;
+ unsigned int hsw = 33;
+ unsigned int hbp = 477;
+ unsigned int vsw = 6;
+ unsigned int vbp = 65;
+ unsigned int data32;
+
+ writel(0, ENCL_VIDEO_EN);
+
+ writel(0x8000, ENCL_VIDEO_MODE);/*bit[15] shadown en*/
+ writel(0x0418, ENCL_VIDEO_MODE_ADV); /* Sampling rate: 1 */
+
+ writel(0x1000, ENCL_VIDEO_FILT_CTRL); /* bypass filter */
+ writel(htotal - 1, ENCL_VIDEO_MAX_PXCNT);
+ writel(vtotal - 1, ENCL_VIDEO_MAX_LNCNT);
+ writel(hsw + hbp, ENCL_VIDEO_HAVON_BEGIN);
+ writel(hactive - 1 + hsw + hbp, ENCL_VIDEO_HAVON_END);
+ writel(vsw + vbp, ENCL_VIDEO_VAVON_BLINE);
+ writel(vactive - 1 + vsw + vbp, ENCL_VIDEO_VAVON_ELINE);
+
+ writel(0, ENCL_VIDEO_HSO_BEGIN);
+ writel(hsw, ENCL_VIDEO_HSO_END);
+ writel(0, ENCL_VIDEO_VSO_BEGIN);
+ writel(0, ENCL_VIDEO_VSO_END);
+ writel(0, ENCL_VIDEO_VSO_BLINE);
+ writel(vsw, ENCL_VIDEO_VSO_ELINE);
+ writel(3, ENCL_VIDEO_RGBIN_CTRL); //yuv: 1, rgb: 3
+
+ writel((5 << 13) | (hactive - 1), ENCL_INBUF_CNTL1);
+ writel(0x200, ENCL_INBUF_CNTL0);
+
+ /* default colorbar pattern */
+ writel(1, ENCL_TST_MDSEL);
+ writel(0x200, ENCL_TST_Y);
+ writel(0x200, ENCL_TST_CB);
+ writel(0x200, ENCL_TST_CR);
+ writel(hsw + hbp, ENCL_TST_CLRBAR_STRT);
+ writel(240, ENCL_TST_CLRBAR_WIDTH);
+ writel(1, ENCL_TST_EN);
+ //writel(0x0410, ENCL_VIDEO_MODE_ADV);
+
+ writel(1, ENCL_VIDEO_EN);
+
+ //select venc to vx1
+ data32 = (0 << 31) | (1 << 30) | (0 << 29) | (0 << 28);
+ writel(data32, VPU_DISP_VIU0_CTRL);
+
+ //config venc_tcon
+ writel(0x0, LCD_RGB_BASE_ADDR);
+ writel(0x400, LCD_RGB_COEFF_ADDR);
+ //writel((1 << 0), LCD_POL_CNTL_ADDR);
+
+ /* DE signal */
+ writel(hsw + hbp, DE_HS_ADDR);
+ writel(hsw + hbp + hactive, DE_HE_ADDR);
+ writel(vsw + vbp, DE_VS_ADDR);
+ writel(vsw + vbp + vactive - 1, DE_VE_ADDR);
+
+ /* Hsync signal */
+ writel(0, HSYNC_HS_ADDR);
+ writel(hsw, HSYNC_HE_ADDR);
+ writel(0, HSYNC_VS_ADDR);
+ writel(vtotal - 1, HSYNC_VE_ADDR);
+
+ /* Vsync signal */
+ writel(0, VSYNC_HS_ADDR);
+ writel(0, VSYNC_HE_ADDR);
+ writel(0, VSYNC_VS_ADDR);
+ writel(vsw, VSYNC_VE_ADDR);
+
+ //select encl
+ writel(2, VPU_VENC_CTRL);
+
+ LCDPR(" lcd venc init\n");
+}
+
+static void lcd_init_pre_lvds(void)
+{
+ unsigned int data32;
+ int cnt = 0, i;
+
+ //1.config pll
+set_pll_retry_lvds:
+ lcd_ana_write(ANACTRL_TCON_PLL2_CNTL0, 0x008e04ad);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL2_CNTL0, 0x208e04ad);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL2_CNTL0, 0x308e04ad);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL2_CNTL1, 0x10108000);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL2_CNTL2, 0x0000110c);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL2_CNTL3, 0x10051400);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL2_CNTL4, 0x000100c0);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL2_CNTL4, 0x008300c0);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL2_CNTL0, 0x348e04ad);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL2_CNTL0, 0x148e04ad);
+ udelay(10);
+ lcd_ana_write(ANACTRL_TCON_PLL2_CNTL2, 0x0000300c);
+ //udelay(100);
+ //lcd_ana_write(ANACTRL_TCON_PLL2_CNTL4, 0x0b8300c0);
+ udelay(10);
+ i = 0;
+ while (i++ < 200) {
+ udelay(50);
+ if (lcd_ana_read(ANACTRL_TCON_PLL2_STS) & 0x80000000)
+ break;
+ }
+ if (!(lcd_ana_read(ANACTRL_TCON_PLL2_STS) & 0x80000000)) {
+ if (cnt++ < 20)
+ goto set_pll_retry_lvds;
+ else
+ LCDPR(" pll lock failed!!!\n");
+ }
+
+ //2.config divider
+ data32 = lcd_clk_read(CLKCTRL_VIID_CLK2_CTRL);
+ data32 &= ~(1 << 19);
+ lcd_clk_write(CLKCTRL_VIID_CLK2_CTRL, data32);
+ /* Disable the div output clock */
+ data32 = lcd_combo_dphy_read(COMBO_DPHY_VID_PLL2_DIV);
+ data32 &= ~(1 << 19);
+ lcd_combo_dphy_write(COMBO_DPHY_VID_PLL2_DIV, data32);
+ data32 &= ~(1 << 15);
+ lcd_combo_dphy_write(COMBO_DPHY_VID_PLL2_DIV, data32);
+
+ lcd_combo_dphy_setb(COMBO_DPHY_VID_PLL2_DIV, 0, 18, 1);
+ lcd_combo_dphy_setb(COMBO_DPHY_VID_PLL2_DIV, 0, 16, 2);
+ lcd_combo_dphy_setb(COMBO_DPHY_VID_PLL2_DIV, 0, 15, 1);
+ lcd_combo_dphy_setb(COMBO_DPHY_VID_PLL2_DIV, 0, 0, 14);
+
+ lcd_combo_dphy_setb(COMBO_DPHY_VID_PLL2_DIV, 1, 16, 2);
+ lcd_combo_dphy_setb(COMBO_DPHY_VID_PLL2_DIV, 1, 15, 1);
+ lcd_combo_dphy_setb(COMBO_DPHY_VID_PLL2_DIV, 0x3c78, 0, 15);
+ lcd_combo_dphy_setb(COMBO_DPHY_VID_PLL2_DIV, 0, 15, 1);
+ data32 = lcd_combo_dphy_read(COMBO_DPHY_VID_PLL2_DIV);
+
+ data32 |= (1 << 19);
+ lcd_combo_dphy_write(COMBO_DPHY_VID_PLL2_DIV, data32);
+
+ //3.config vclk
+ lcd_clk_write(CLKCTRL_VIID_CLK2_DIV, 0x00000000);
+ udelay(5);
+ lcd_clk_write(CLKCTRL_VIID_CLK2_CTRL, 0x00080000);
+ udelay(5);
+ lcd_clk_write(CLKCTRL_VIID_CLK2_DIV, 0x00008000);
+ lcd_clk_write(CLKCTRL_VIID_CLK2_DIV, 0x00018000);
+ udelay(5);
+ lcd_clk_write(CLKCTRL_VIID_CLK2_CTRL, 0x00080001);
+ lcd_clk_write(CLKCTRL_VIID_CLK2_CTRL, 0x00088001);
+ udelay(10);
+ lcd_clk_write(CLKCTRL_VIID_CLK2_CTRL, 0x00080001);
+ udelay(5);
+ lcd_clk_write(CLKCTRL_VID_CLK2_CTRL2, 0x00000008);
+
+ //4. config phy clk
+ //done by edp init
+
+ //5. reset phy
+ data32 = lcd_reset_read(RESETCTRL_RESET1_MASK);
+ data32 &= ~((0x1 << 20) | (0x1 << 19) | (0x1 << 7));
+ lcd_reset_write(RESETCTRL_RESET1_MASK, data32);
+ data32 = lcd_reset_read(RESETCTRL_RESET1_LEVEL);
+ data32 &= ~((0x1 << 20) | (0x1 << 19) | (0x1 << 7));
+ lcd_reset_write(RESETCTRL_RESET1_LEVEL, data32);
+ udelay(1);
+ data32 |= (0x1 << 20) | (0x1 << 19) | (0x1 << 7);
+ lcd_reset_write(RESETCTRL_RESET1_LEVEL, data32);
+ udelay(10);
+ lcd_combo_dphy_write(COMBO_DPHY_CNTL0, 0x10);
+ lcd_combo_dphy_write(COMBO_DPHY_CNTL1, 0xaaaaaaaa);
+
+ //6. config phy
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL1, 0xc6770038);//ch0
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL2, 0x0100ffff);//ch0_aux
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL3, 0x16530028);//ch1
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL4, 0x16530028);//ch2
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL5, 0x16530028);//ch3
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL6, 0x16530028);//ch4
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL7, 0x16530028);//ch5
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL8, 0x16530028);//ch6
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL9, 0x16530028);//ch7
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL10, 0x16430028);//ch8
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL11, 0x0100ffff);//ch8 AUX
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL12, 0x16530028);//ch9
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL13, 0x16530028);//ch10
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL14, 0x16530028);//ch11
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL15, 0x16530028);//ch12
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL16, 0x16530028);//ch13
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL17, 0x16530028);//ch14
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL19, 0x00406253);//COMMON
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL20, 0x0);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL21, 0x0);
+
+ LCDPR(" lcd init pre\n");
+}
+
+static void lvds_init(void)
+{
+ /* set fifo_clk_sel: div 7 */
+ lcd_combo_dphy_write(COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL0, (1 << 5));
+ /* set cntl_ser_en: 8-channel to 1 */
+ lcd_combo_dphy_setb(COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL0, 0x3ff, 16, 10);
+
+ /* decoupling fifo enable, gated clock enable */
+ lcd_combo_dphy_write(COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL1,
+ (1 << 6) | (1 << 0));
+ /* decoupling fifo write enable after fifo enable */
+ lcd_combo_dphy_setb(COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL1, 1, 7, 1);
+
+ lcd_vcbus_write(LVDS_SER_EN + (0x600 << 2), 0xfff );
+ lcd_vcbus_write(LVDS_PACK_CNTL_ADDR + (0x600 << 2),
+ (1 << 0) | // repack //[1:0]
+ (0 << 3) | // reserve
+ (0 << 4) | // lsb first
+ (0 << 5) | // pn swap
+ (1 << 6) | // dual port
+ (0 << 7) | // use tcon control
+ (1 << 8) | // 0:10bits, 1:8bits, 2:6bits, 3:4bits.
+ (0 << 10) | //r_select //0:R, 1:G, 2:B, 3:0
+ (1 << 12) | //g_select //0:R, 1:G, 2:B, 3:0
+ (2 << 14)); //b_select //0:R, 1:G, 2:B, 3:0;
+
+ lcd_vcbus_write(LVDS_GEN_CNTL + (0x600 << 2),
+ (lcd_vcbus_read(LVDS_GEN_CNTL + (0x600 << 2)) | (1 << 4) | (0x3 << 0)));
+ lcd_vcbus_setb(LVDS_GEN_CNTL + (0x600 << 2), 1, 3, 1);
+
+ lcd_vcbus_write(P2P_CH_SWAP0+(0x600<<2) , 0x87643210);//ch5 data4 none for LVDS
+ lcd_vcbus_write(P2P_CH_SWAP1+(0x600<<2) , 0x000000a9);//chb data4 none for LVDS
+ LCDPR("CH swap: 0x%x=0x%x, 0x%x=0x%x\n",
+ P2P_CH_SWAP0+(0x600<<2), lcd_vcbus_read(P2P_CH_SWAP0+(0x600<<2)),
+ P2P_CH_SWAP1+(0x600<<2), lcd_vcbus_read(P2P_CH_SWAP1+(0x600<<2)));
+ lcd_vcbus_write(P2P_BIT_REV+(0x600<<2) , 2);
+ LCDPR("bit rev: 0x%x=0x%x\n",
+ P2P_BIT_REV+(0x600<<2), lcd_vcbus_read(P2P_BIT_REV+(0x600<<2)));
+
+ LCDPR(" lvds init finish\n");
+}
+
+static void lcd_venc_set_lvds(void)
+{
+ unsigned int hactive = 1920;
+ unsigned int vactive = 1080;
+ unsigned int htotal = 2200;
+ unsigned int vtotal = 1120;
+ unsigned int hsw = 44;
+ unsigned int hbp = 148;
+ unsigned int vsw = 5;
+ unsigned int vbp = 30;
+ //unsigned int pclk = 147840000;
+ unsigned int data32;
+
+ lcd_vcbus_write(ENCL_VIDEO_EN + (0x800 << 2), 0);
+
+ lcd_vcbus_write(ENCL_VIDEO_MODE + (0x800 << 2), 0x8000);/*bit[15] shadown en*/
+ lcd_vcbus_write(ENCL_VIDEO_MODE_ADV + (0x800 << 2), 0x0418); /* Sampling rate: 1 */
+
+ lcd_vcbus_write(ENCL_VIDEO_FILT_CTRL + (0x800 << 2), 0x1000); /* bypass filter */
+ lcd_vcbus_write(ENCL_VIDEO_MAX_PXCNT + (0x800 << 2), htotal - 1);
+ lcd_vcbus_write(ENCL_VIDEO_MAX_LNCNT + (0x800 << 2), vtotal - 1);
+ lcd_vcbus_write(ENCL_VIDEO_HAVON_BEGIN + (0x800 << 2), hsw + hbp);
+ lcd_vcbus_write(ENCL_VIDEO_HAVON_END + (0x800 << 2), hactive - 1 + hsw + hbp);
+ lcd_vcbus_write(ENCL_VIDEO_VAVON_BLINE + (0x800 << 2), vsw + vbp);
+ lcd_vcbus_write(ENCL_VIDEO_VAVON_ELINE + (0x800 << 2), vactive - 1 + vsw + vbp);
+
+ lcd_vcbus_write(ENCL_VIDEO_HSO_BEGIN + (0x800 << 2), 0);
+ lcd_vcbus_write(ENCL_VIDEO_HSO_END + (0x800 << 2), hsw);
+ lcd_vcbus_write(ENCL_VIDEO_VSO_BEGIN + (0x800 << 2), 0);
+ lcd_vcbus_write(ENCL_VIDEO_VSO_END + (0x800 << 2), 0);
+ lcd_vcbus_write(ENCL_VIDEO_VSO_BLINE + (0x800 << 2), 0);
+ lcd_vcbus_write(ENCL_VIDEO_VSO_ELINE + (0x800 << 2), vsw);
+ lcd_vcbus_write(ENCL_VIDEO_RGBIN_CTRL + (0x800 << 2), 3); //yuv: 1, rgb: 3
+
+ lcd_vcbus_write(ENCL_INBUF_CNTL1 + (0x800 << 2), (5 << 13) | (hactive - 1));
+ lcd_vcbus_write(ENCL_INBUF_CNTL0 + (0x800 << 2), 0x200);
+
+ /* default colorbar pattern */
+ lcd_vcbus_write(ENCL_TST_MDSEL + (0x800 << 2), 1);
+ lcd_vcbus_write(ENCL_TST_Y + (0x800 << 2), 0x200);
+ lcd_vcbus_write(ENCL_TST_CB + (0x800 << 2), 0x200);
+ lcd_vcbus_write(ENCL_TST_CR + (0x800 << 2), 0x200);
+ lcd_vcbus_write(ENCL_TST_CLRBAR_STRT + (0x800 << 2), hsw + hbp);
+ lcd_vcbus_write(ENCL_TST_CLRBAR_WIDTH + (0x800 << 2), 240);
+ lcd_vcbus_write(ENCL_TST_EN + (0x800 << 2), 0);
+
+ lcd_vcbus_write(ENCL_VIDEO_EN + (0x800 << 2), 1);
+
+ //select venc to lvds
+ data32 = (1 << 31) | (0 << 30) | (0 << 29) | (0 << 28);
+ lcd_vcbus_write(VPU_DISP_VIU2_CTRL, data32);
+
+ //config venc_tcon
+ lcd_vcbus_write(LCD_RGB_BASE_ADDR + (0x200 << 2), 0x0);
+ lcd_vcbus_write(LCD_RGB_COEFF_ADDR + (0x200 << 2), 0x400);
+ lcd_vcbus_write(LCD_POL_CNTL_ADDR + (0x200 << 2), (1 << 0));
+
+ /* DE signal */
+ lcd_vcbus_write(DE_HS_ADDR + (0x600 << 2), hsw + hbp);
+ lcd_vcbus_write(DE_HE_ADDR + (0x600 << 2), hsw + hbp + hactive);
+ lcd_vcbus_write(DE_VS_ADDR + (0x600 << 2), vsw + vbp);
+ lcd_vcbus_write(DE_VE_ADDR + (0x600 << 2), vsw + vbp + vactive - 1);
+
+ /* Hsync signal */
+ lcd_vcbus_write(HSYNC_HS_ADDR + (0x600 << 2), 0);
+ lcd_vcbus_write(HSYNC_HE_ADDR + (0x600 << 2), hsw);
+ lcd_vcbus_write(HSYNC_VS_ADDR + (0x600 << 2), 0);
+ lcd_vcbus_write(HSYNC_VE_ADDR + (0x600 << 2), vtotal - 1);
+
+ /* Vsync signal */
+ lcd_vcbus_write(VSYNC_HS_ADDR + (0x600 << 2), 0);
+ lcd_vcbus_write(VSYNC_HE_ADDR + (0x600 << 2), 0);
+ lcd_vcbus_write(VSYNC_VS_ADDR + (0x600 << 2), 0);
+ lcd_vcbus_write(VSYNC_VE_ADDR + (0x600 << 2), vsw);
+
+ //select encl
+ lcd_vcbus_write(VPU_VENC_CTRL + (0x800 << 2), 2);
+
+ LCDPR(" lcd venc init\n");
+}
+
+void lcd_display_init_test(struct aml_lcd_drv_s *pdrv)
+{
+ int index = pdrv->index;
+
+ if (pdrv->config.basic.lcd_type == LCD_LVDS) {
+ if (index == 2) {
+ run_command("gpio set GPIOY_14", 0);
+ mdelay(20);
+
+ lcd_vcbus_write(VPU_VIU_VENC_MUX_CTRL, 0x6);
+ lcd_init_pre_lvds();
+ lcd_venc_set_lvds();
+ mdelay(100);
+ lvds_init();
+ LCDPR("lvds%d init test done\n", index);
+ }
+ } else if (pdrv->config.basic.lcd_type == LCD_EDP) {
+ if (index == 0) {
+ run_command("gpio set GPIOY_0", 0);
+ run_command("gpio set GPIOY_1", 0);
+ run_command("gpio set GPIOY_12", 0);
+ } else {
+ run_command("gpio set GPIOY_14", 0);
+ run_command("gpio set GPIOY_8", 0);
+ run_command("gpio set GPIOY_13", 0);
+ }
+ LCDPR("%s: edp index=%d\n", __func__, index);
+ mdelay(50);
+
+ lcd_vcbus_write(VPU_VIU_VENC_MUX_CTRL, 0x24);
+ lcd_init_pre_edp(index);
+ lcd_venc_set_edp(index);
+ mdelay(100);
+ edp_tx_init(index);
+ LCDPR("edp%d init test done\n", index);
+ } else if (pdrv->config.basic.lcd_type == LCD_MIPI) {
+ if (index == 0) {
+ run_command("gpio clear GPIOY_1", 0); //bl_pwm
+ run_command("gpio set GPIOY_12", 0); //bl_en
+
+ run_command("gpio clear GPIOY_4", 0);
+ run_command("gpio clear GPIOY_0", 0);
+ mdelay(500);
+ run_command("gpio set GPIOY_0", 0);
+ mdelay(100);
+ run_command("gpio set GPIOY_4", 0);
+ } else {
+ run_command("gpio clear GPIOY_8", 0); //bl_pwm
+ run_command("gpio set GPIOY_13", 0); //bl_en
+
+ run_command("gpio clear GPIOY_6", 0);
+ run_command("gpio clear GPIOY_14", 0);
+ mdelay(500);
+ run_command("gpio set GPIOY_14", 0);
+ mdelay(100);
+ run_command("gpio set GPIOY_6", 0);
+ }
+ mdelay(20);
+
+ lcd_vcbus_write(VPU_VIU_VENC_MUX_CTRL, 0x24);
+ lcd_init_pre_mipi_dsi(index);
+ lcd_venc_set_mipi_dsi(index);
+ mdelay(20);
+ mipi_dsi_power_init(index);
+ mipi_dsi_tx_init(pdrv);
+ LCDPR("mipi_dsi init test done\n");
+ } else if (pdrv->config.basic.lcd_type == LCD_VBYONE) {
+ if (index == 0) {
+ run_command("gpio set GPIOY_0", 0);
+ mdelay(50);
+
+ lcd_vcbus_write(VPU_VIU_VENC_MUX_CTRL, 0x24);
+ lcd_init_pre_vx1();
+ lcd_venc_set_vx1();
+ mdelay(20);
+ vx1_tx_init();
+ LCDPR("vbyone%d init test done\n", index);
+ }
+ }
+ pdrv->status |= (LCD_STATUS_IF_ON | LCD_STATUS_ENCL_ON);
+}
+
+void lcd_display_init_reg_dump(struct aml_lcd_drv_s *pdrv)
+{
+ int index = pdrv->index;
+ unsigned int offset;
+ unsigned int reg_stts, vid2_clk_ctrl, vid2_clk_div, vid2_clk_ctrl2;
+ unsigned int vid_pll_div, vpu_disp_ctrl;
+ unsigned int reg_dphy_tx_ctrl0, reg_dphy_tx_ctrl1;
+
+ if (pdrv->config.basic.lcd_type == LCD_LVDS) {
+ printf("pll regs:\n");
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n",
+ ANACTRL_TCON_PLL2_CNTL0,
+ readl(ANACTRL_TCON_PLL2_CNTL0),
+ ANACTRL_TCON_PLL2_CNTL1,
+ readl(ANACTRL_TCON_PLL2_CNTL1),
+ ANACTRL_TCON_PLL2_CNTL2,
+ readl(ANACTRL_TCON_PLL2_CNTL2),
+ ANACTRL_TCON_PLL2_CNTL3,
+ readl(ANACTRL_TCON_PLL2_CNTL3),
+ ANACTRL_TCON_PLL2_CNTL4,
+ readl(ANACTRL_TCON_PLL2_CNTL4),
+ ANACTRL_TCON_PLL2_STS,
+ readl(ANACTRL_TCON_PLL2_STS));
+
+ printf("clk regs:\n");
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n",
+ COMBO_DPHY_VID_PLL2_DIV,
+ readl(COMBO_DPHY_VID_PLL2_DIV),
+ CLKCTRL_VIID_CLK2_DIV,
+ readl(CLKCTRL_VIID_CLK2_DIV),
+ CLKCTRL_VIID_CLK2_CTRL,
+ readl(CLKCTRL_VIID_CLK2_CTRL),
+ CLKCTRL_VID_CLK2_CTRL2,
+ readl(CLKCTRL_VID_CLK2_CTRL2));
+
+ printf("lvds regs:\n");
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n",
+ COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL0,
+ readl(COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL0),
+ COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL1,
+ readl(COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL1),
+ LVDS_SER_EN + (0x600 << 2),
+ readl(LVDS_SER_EN + (0x600 << 2)),
+ LVDS_PACK_CNTL_ADDR + (0x600 << 2),
+ readl(LVDS_PACK_CNTL_ADDR + (0x600 << 2)),
+ LVDS_GEN_CNTL + (0x600 << 2),
+ readl(LVDS_GEN_CNTL + (0x600 << 2)),
+ P2P_CH_SWAP0 + (0x600 << 2),
+ readl(P2P_CH_SWAP0 + (0x600 << 2)),
+ P2P_CH_SWAP1 + (0x600 << 2),
+ readl(P2P_CH_SWAP1 + (0x600 << 2)),
+ P2P_BIT_REV + (0x600 << 2),
+ readl(P2P_BIT_REV + (0x600 << 2)));
+
+ printf("venc regs:\n");
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n",
+ ENCL_VIDEO_EN + (0x800 << 2),
+ readl(ENCL_VIDEO_EN + (0x800 << 2)),
+ ENCL_VIDEO_MODE + (0x800 << 2),
+ readl(ENCL_VIDEO_MODE + (0x800 << 2)),
+ ENCL_VIDEO_MODE_ADV + (0x800 << 2),
+ readl(ENCL_VIDEO_MODE_ADV + (0x800 << 2)),
+ ENCL_VIDEO_FILT_CTRL + (0x800 << 2),
+ readl(ENCL_VIDEO_FILT_CTRL + (0x800 << 2)),
+ ENCL_VIDEO_MAX_PXCNT + (0x800 << 2),
+ readl(ENCL_VIDEO_MAX_PXCNT + (0x800 << 2)),
+ ENCL_VIDEO_MAX_LNCNT + (0x800 << 2),
+ readl(ENCL_VIDEO_MAX_LNCNT + (0x800 << 2)),
+ ENCL_VIDEO_HAVON_BEGIN + (0x800 << 2),
+ readl(ENCL_VIDEO_HAVON_BEGIN + (0x800 << 2)),
+ ENCL_VIDEO_HAVON_END + (0x800 << 2),
+ readl(ENCL_VIDEO_HAVON_END + (0x800 << 2)),
+ ENCL_VIDEO_VAVON_BLINE + (0x800 << 2),
+ readl(ENCL_VIDEO_VAVON_BLINE + (0x800 << 2)),
+ ENCL_VIDEO_VAVON_ELINE + (0x800 << 2),
+ readl(ENCL_VIDEO_VAVON_ELINE + (0x800 << 2)),
+ ENCL_VIDEO_HSO_BEGIN + (0x800 << 2),
+ readl(ENCL_VIDEO_HSO_BEGIN + (0x800 << 2)),
+ ENCL_VIDEO_HSO_END + (0x800 << 2),
+ readl(ENCL_VIDEO_HSO_END + (0x800 << 2)),
+ ENCL_VIDEO_VSO_BEGIN + (0x800 << 2),
+ readl(ENCL_VIDEO_VSO_BEGIN + (0x800 << 2)),
+ ENCL_VIDEO_VSO_END + (0x800 << 2),
+ readl(ENCL_VIDEO_VSO_END + (0x800 << 2)),
+ ENCL_VIDEO_VSO_BLINE + (0x800 << 2),
+ readl(ENCL_VIDEO_VSO_BLINE + (0x800 << 2)),
+ ENCL_VIDEO_VSO_ELINE + (0x800 << 2),
+ readl(ENCL_VIDEO_VSO_ELINE + (0x800 << 2)),
+ ENCL_VIDEO_RGBIN_CTRL + (0x800 << 2),
+ readl(ENCL_VIDEO_RGBIN_CTRL + (0x800 << 2)),
+ ENCL_INBUF_CNTL1 + (0x800 << 2),
+ readl(ENCL_INBUF_CNTL1 + (0x800 << 2)),
+ ENCL_INBUF_CNTL0 + (0x800 << 2),
+ readl(ENCL_INBUF_CNTL0 + (0x800 << 2)),
+ VPU_DISP_VIU2_CTRL,
+ readl(VPU_DISP_VIU2_CTRL),
+ VPU_VENC_CTRL + (0x800 << 2),
+ readl(VPU_VENC_CTRL + (0x800 << 2)));
+ } else if (pdrv->config.basic.lcd_type == LCD_EDP) {
+ switch (index) {
+ case 0:
+ reg_stts = ANACTRL_TCON_PLL0_STS;
+ vid2_clk_ctrl = CLKCTRL_VIID_CLK0_CTRL;
+ vid2_clk_div = CLKCTRL_VIID_CLK0_DIV;
+ vid2_clk_ctrl2 = CLKCTRL_VID_CLK0_CTRL2;
+ vid_pll_div = COMBO_DPHY_VID_PLL0_DIV;
+ reg_dphy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0;
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1;
+ vpu_disp_ctrl = VPU_DISP_VIU0_CTRL;
+ break;
+ case 1:
+ reg_stts = ANACTRL_TCON_PLL1_STS;
+ vid2_clk_ctrl = CLKCTRL_VIID_CLK1_CTRL;
+ vid2_clk_div = CLKCTRL_VIID_CLK1_DIV;
+ vid2_clk_ctrl2 = CLKCTRL_VID_CLK1_CTRL2;
+ vid_pll_div = COMBO_DPHY_VID_PLL1_DIV;
+ reg_dphy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL0;
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL1;
+ vpu_disp_ctrl = VPU_DISP_VIU1_CTRL;
+ break;
+ default:
+ return;
+ }
+ printf("\nedp%d regs:\n", index);
+ offset = (pll_table[index] << 2);
+ printf("pll regs:\n");
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n",
+ ANACTRL_TCON_PLL0_CNTL0 + offset,
+ readl(ANACTRL_TCON_PLL0_CNTL0 + offset),
+ ANACTRL_TCON_PLL0_CNTL1 + offset,
+ readl(ANACTRL_TCON_PLL0_CNTL1 + offset),
+ ANACTRL_TCON_PLL0_CNTL2 + offset,
+ readl(ANACTRL_TCON_PLL0_CNTL2 + offset),
+ ANACTRL_TCON_PLL0_CNTL3 + offset,
+ readl(ANACTRL_TCON_PLL0_CNTL3 + offset),
+ ANACTRL_TCON_PLL0_CNTL4 + offset,
+ readl(ANACTRL_TCON_PLL0_CNTL4 + offset),
+ reg_stts,
+ readl(reg_stts));
+
+ printf("clk regs:\n");
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n",
+ COMBO_DPHY_EDP_PIXEL_CLK_DIV,
+ readl(COMBO_DPHY_EDP_PIXEL_CLK_DIV),
+ vid_pll_div,
+ readl(vid_pll_div),
+ vid2_clk_div,
+ readl(vid2_clk_div),
+ vid2_clk_ctrl,
+ readl(vid2_clk_ctrl),
+ vid2_clk_ctrl2,
+ readl(vid2_clk_ctrl2));
+
+ printf("edp regs:\n");
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n",
+ reg_dphy_tx_ctrl0,
+ readl(reg_dphy_tx_ctrl0),
+ reg_dphy_tx_ctrl1,
+ readl(reg_dphy_tx_ctrl1),
+ EDP_TX_LINK_BW_SET,
+ dptx_reg_read(index, EDP_TX_LINK_BW_SET),
+ EDP_TX_LINK_COUNT_SET,
+ dptx_reg_read(index, EDP_TX_LINK_COUNT_SET),
+ EDP_TX_TRAINING_PATTERN_SET,
+ dptx_reg_read(index, EDP_TX_TRAINING_PATTERN_SET),
+ EDP_TX_SCRAMBLING_DISABLE,
+ dptx_reg_read(index, EDP_TX_SCRAMBLING_DISABLE),
+ EDP_TX_TRANSMITTER_OUTPUT_ENABLE,
+ dptx_reg_read(index, EDP_TX_TRANSMITTER_OUTPUT_ENABLE),
+ EDP_TX_MAIN_STREAM_ENABLE,
+ dptx_reg_read(index, EDP_TX_MAIN_STREAM_ENABLE),
+ EDP_TX_PHY_RESET,
+ dptx_reg_read(index, EDP_TX_PHY_RESET),
+ EDP_TX_PHY_STATUS,
+ dptx_reg_read(index, EDP_TX_PHY_STATUS),
+ EDP_TX_AUX_COMMAND,
+ dptx_reg_read(index, EDP_TX_AUX_COMMAND),
+ EDP_TX_AUX_ADDRESS,
+ dptx_reg_read(index, EDP_TX_AUX_ADDRESS),
+ EDP_TX_AUX_STATE,
+ dptx_reg_read(index, EDP_TX_AUX_STATE),
+ EDP_TX_AUX_REPLY_CODE,
+ dptx_reg_read(index, EDP_TX_AUX_REPLY_CODE),
+ EDP_TX_AUX_REPLY_COUNT,
+ dptx_reg_read(index, EDP_TX_AUX_REPLY_COUNT),
+ EDP_TX_AUX_REPLY_DATA_COUNT,
+ dptx_reg_read(index, EDP_TX_AUX_REPLY_DATA_COUNT),
+ EDP_TX_AUX_TRANSFER_STATUS,
+ dptx_reg_read(index, EDP_TX_AUX_TRANSFER_STATUS));
+
+ offset = (venc_table[index] << 2);
+ printf("venc regs:\n");
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n",
+ ENCL_VIDEO_EN + offset,
+ readl(ENCL_VIDEO_EN + offset),
+ ENCL_VIDEO_MODE + offset,
+ readl(ENCL_VIDEO_MODE + offset),
+ ENCL_VIDEO_MODE_ADV + offset,
+ readl(ENCL_VIDEO_MODE_ADV + offset),
+ ENCL_VIDEO_FILT_CTRL + offset,
+ readl(ENCL_VIDEO_FILT_CTRL + offset),
+ ENCL_VIDEO_MAX_PXCNT + offset,
+ readl(ENCL_VIDEO_MAX_PXCNT + offset),
+ ENCL_VIDEO_MAX_LNCNT + offset,
+ readl(ENCL_VIDEO_MAX_LNCNT + offset),
+ ENCL_VIDEO_HAVON_BEGIN + offset,
+ readl(ENCL_VIDEO_HAVON_BEGIN + offset),
+ ENCL_VIDEO_HAVON_END + offset,
+ readl(ENCL_VIDEO_HAVON_END + offset),
+ ENCL_VIDEO_VAVON_BLINE + offset,
+ readl(ENCL_VIDEO_VAVON_BLINE + offset),
+ ENCL_VIDEO_VAVON_ELINE + offset,
+ readl(ENCL_VIDEO_VAVON_ELINE + offset),
+ ENCL_VIDEO_HSO_BEGIN + offset,
+ readl(ENCL_VIDEO_HSO_BEGIN + offset),
+ ENCL_VIDEO_HSO_END + offset,
+ readl(ENCL_VIDEO_HSO_END + offset),
+ ENCL_VIDEO_VSO_BEGIN + offset,
+ readl(ENCL_VIDEO_VSO_BEGIN + offset),
+ ENCL_VIDEO_VSO_END + offset,
+ readl(ENCL_VIDEO_VSO_END + offset),
+ ENCL_VIDEO_VSO_BLINE + offset,
+ readl(ENCL_VIDEO_VSO_BLINE + offset),
+ ENCL_VIDEO_VSO_ELINE + offset,
+ readl(ENCL_VIDEO_VSO_ELINE + offset),
+ ENCL_VIDEO_RGBIN_CTRL + offset,
+ readl(ENCL_VIDEO_RGBIN_CTRL + offset),
+ ENCL_INBUF_CNTL1 + offset,
+ readl(ENCL_INBUF_CNTL1 + offset),
+ ENCL_INBUF_CNTL0 + offset,
+ readl(ENCL_INBUF_CNTL0 + offset),
+ vpu_disp_ctrl,
+ readl(vpu_disp_ctrl),
+ VPU_VENC_CTRL + offset,
+ readl(VPU_VENC_CTRL + offset));
+ } else if (pdrv->config.basic.lcd_type == LCD_MIPI) {
+ printf("pll regs:\n");
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n",
+ ANACTRL_TCON_PLL0_CNTL0,
+ readl(ANACTRL_TCON_PLL0_CNTL0),
+ ANACTRL_TCON_PLL0_CNTL1,
+ readl(ANACTRL_TCON_PLL0_CNTL1),
+ ANACTRL_TCON_PLL0_CNTL2,
+ readl(ANACTRL_TCON_PLL0_CNTL2),
+ ANACTRL_TCON_PLL0_CNTL3,
+ readl(ANACTRL_TCON_PLL0_CNTL3),
+ ANACTRL_TCON_PLL0_CNTL4,
+ readl(ANACTRL_TCON_PLL0_CNTL4),
+ ANACTRL_TCON_PLL0_STS,
+ readl(ANACTRL_TCON_PLL0_STS));
+
+ printf("clk regs:\n");
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n",
+ CLKCTRL_MIPIDSI_PHY_CLK_CTRL,
+ readl(CLKCTRL_MIPIDSI_PHY_CLK_CTRL),
+ CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL,
+ readl(CLKCTRL_MIPI_DSI_MEAS_CLK_CTRL),
+ COMBO_DPHY_VID_PLL0_DIV,
+ readl(COMBO_DPHY_VID_PLL0_DIV),
+ CLKCTRL_VIID_CLK0_DIV,
+ readl(CLKCTRL_VIID_CLK0_DIV),
+ CLKCTRL_VIID_CLK0_CTRL,
+ readl(CLKCTRL_VIID_CLK0_CTRL),
+ CLKCTRL_VID_CLK0_CTRL2,
+ readl(CLKCTRL_VID_CLK0_CTRL2));
+
+ printf("mipi-dsi host regs:\n");
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n",
+ MIPI_DSI_TOP_CNTL,
+ readl(MIPI_DSI_TOP_CNTL),
+ MIPI_DSI_TOP_SW_RESET,
+ readl(MIPI_DSI_TOP_SW_RESET),
+ MIPI_DSI_TOP_CLK_CNTL,
+ readl(MIPI_DSI_TOP_CLK_CNTL),
+ MIPI_DSI_TOP_MEM_PD,
+ readl(MIPI_DSI_TOP_MEM_PD),
+ MIPI_DSI_TOP_INTR_CNTL_STAT,
+ readl(MIPI_DSI_TOP_INTR_CNTL_STAT),
+ MIPI_DSI_TOP_MEAS_CNTL,
+ readl(MIPI_DSI_TOP_MEAS_CNTL));
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n",
+ MIPI_DSI_DWC_PHY_TST_CTRL0_OS,
+ readl(MIPI_DSI_DWC_PHY_TST_CTRL0_OS),
+ MIPI_DSI_DWC_PHY_TST_CTRL1_OS,
+ readl(MIPI_DSI_DWC_PHY_TST_CTRL1_OS),
+ MIPI_DSI_DWC_PHY_RSTZ_OS,
+ readl(MIPI_DSI_DWC_PHY_RSTZ_OS),
+ MIPI_DSI_DWC_PHY_IF_CFG_OS,
+ readl(MIPI_DSI_DWC_PHY_IF_CFG_OS),
+ MIPI_DSI_DWC_PHY_TMR_CFG_OS,
+ readl(MIPI_DSI_DWC_PHY_TMR_CFG_OS),
+ MIPI_DSI_DWC_PHY_TMR_LPCLK_CFG_OS,
+ readl(MIPI_DSI_DWC_PHY_TMR_LPCLK_CFG_OS),
+ MIPI_DSI_DWC_CMD_MODE_CFG_OS,
+ readl(MIPI_DSI_DWC_CMD_MODE_CFG_OS),
+ MIPI_DSI_DWC_PCKHDL_CFG_OS,
+ readl(MIPI_DSI_DWC_PCKHDL_CFG_OS),
+ MIPI_DSI_DWC_DPI_COLOR_CODING_OS,
+ readl(MIPI_DSI_DWC_DPI_COLOR_CODING_OS),
+ MIPI_DSI_DWC_DPI_CFG_POL_OS,
+ readl(MIPI_DSI_DWC_DPI_CFG_POL_OS),
+ MIPI_DSI_DWC_VID_MODE_CFG_OS,
+ readl(MIPI_DSI_DWC_VID_MODE_CFG_OS),
+ MIPI_DSI_DWC_DPI_LP_CMD_TIM_OS,
+ readl(MIPI_DSI_DWC_DPI_LP_CMD_TIM_OS),
+ MIPI_DSI_DWC_CLKMGR_CFG_OS,
+ readl(MIPI_DSI_DWC_CLKMGR_CFG_OS),
+ MIPI_DSI_DWC_MODE_CFG_OS,
+ readl(MIPI_DSI_DWC_MODE_CFG_OS));
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n",
+ MIPI_DSI_DWC_VID_PKT_SIZE_OS,
+ readl(MIPI_DSI_DWC_VID_PKT_SIZE_OS),
+ MIPI_DSI_DWC_VID_NUM_CHUNKS_OS,
+ readl(MIPI_DSI_DWC_VID_NUM_CHUNKS_OS),
+ MIPI_DSI_DWC_VID_NULL_SIZE_OS,
+ readl(MIPI_DSI_DWC_VID_NULL_SIZE_OS),
+ MIPI_DSI_DWC_VID_HLINE_TIME_OS,
+ readl(MIPI_DSI_DWC_VID_HLINE_TIME_OS),
+ MIPI_DSI_DWC_VID_HSA_TIME_OS,
+ readl(MIPI_DSI_DWC_VID_HSA_TIME_OS),
+ MIPI_DSI_DWC_VID_HBP_TIME_OS,
+ readl(MIPI_DSI_DWC_VID_HBP_TIME_OS),
+ MIPI_DSI_DWC_VID_VSA_LINES_OS,
+ readl(MIPI_DSI_DWC_VID_VSA_LINES_OS),
+ MIPI_DSI_DWC_VID_VBP_LINES_OS,
+ readl(MIPI_DSI_DWC_VID_VBP_LINES_OS),
+ MIPI_DSI_DWC_VID_VFP_LINES_OS,
+ readl(MIPI_DSI_DWC_VID_VFP_LINES_OS),
+ MIPI_DSI_DWC_VID_VACTIVE_LINES_OS,
+ readl(MIPI_DSI_DWC_VID_VACTIVE_LINES_OS));
+
+ printf("mipi-dsi phy regs:\n");
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n",
+ MIPI_DSI_PHY_CTRL,
+ readl(MIPI_DSI_PHY_CTRL),
+ MIPI_DSI_CLK_TIM,
+ readl(MIPI_DSI_CLK_TIM),
+ MIPI_DSI_CLK_TIM1,
+ readl(MIPI_DSI_CLK_TIM1),
+ MIPI_DSI_HS_TIM,
+ readl(MIPI_DSI_HS_TIM),
+ MIPI_DSI_LP_TIM,
+ readl(MIPI_DSI_LP_TIM),
+ MIPI_DSI_ANA_UP_TIM,
+ readl(MIPI_DSI_ANA_UP_TIM),
+ MIPI_DSI_INIT_TIM,
+ readl(MIPI_DSI_INIT_TIM),
+ MIPI_DSI_WAKEUP_TIM,
+ readl(MIPI_DSI_WAKEUP_TIM),
+ MIPI_DSI_LPOK_TIM,
+ readl(MIPI_DSI_LPOK_TIM),
+ MIPI_DSI_ULPS_CHECK,
+ readl(MIPI_DSI_ULPS_CHECK),
+ MIPI_DSI_LP_WCHDOG,
+ readl(MIPI_DSI_LP_WCHDOG),
+ MIPI_DSI_TURN_WCHDOG,
+ readl(MIPI_DSI_TURN_WCHDOG),
+ MIPI_DSI_CHAN_CTRL,
+ readl(MIPI_DSI_CHAN_CTRL),
+ MIPI_DSI_PHY_CTRL,
+ readl(MIPI_DSI_PHY_CTRL),
+ MIPI_DSI_LP_WCHDOG,
+ readl(MIPI_DSI_LP_WCHDOG));
+
+ printf("venc regs:\n");
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n",
+ ENCL_VIDEO_EN,
+ readl(ENCL_VIDEO_EN),
+ ENCL_VIDEO_MODE,
+ readl(ENCL_VIDEO_MODE),
+ ENCL_VIDEO_MODE_ADV,
+ readl(ENCL_VIDEO_MODE_ADV),
+ ENCL_VIDEO_FILT_CTRL,
+ readl(ENCL_VIDEO_FILT_CTRL),
+ ENCL_VIDEO_MAX_PXCNT,
+ readl(ENCL_VIDEO_MAX_PXCNT),
+ ENCL_VIDEO_MAX_LNCNT,
+ readl(ENCL_VIDEO_MAX_LNCNT),
+ ENCL_VIDEO_HAVON_BEGIN,
+ readl(ENCL_VIDEO_HAVON_BEGIN),
+ ENCL_VIDEO_HAVON_END,
+ readl(ENCL_VIDEO_HAVON_END),
+ ENCL_VIDEO_VAVON_BLINE,
+ readl(ENCL_VIDEO_VAVON_BLINE),
+ ENCL_VIDEO_VAVON_ELINE,
+ readl(ENCL_VIDEO_VAVON_ELINE),
+ ENCL_VIDEO_HSO_BEGIN,
+ readl(ENCL_VIDEO_HSO_BEGIN),
+ ENCL_VIDEO_HSO_END,
+ readl(ENCL_VIDEO_HSO_END),
+ ENCL_VIDEO_VSO_BEGIN,
+ readl(ENCL_VIDEO_VSO_BEGIN),
+ ENCL_VIDEO_VSO_END,
+ readl(ENCL_VIDEO_VSO_END),
+ ENCL_VIDEO_VSO_BLINE,
+ readl(ENCL_VIDEO_VSO_BLINE),
+ ENCL_VIDEO_VSO_ELINE,
+ readl(ENCL_VIDEO_VSO_ELINE),
+ ENCL_VIDEO_RGBIN_CTRL,
+ readl(ENCL_VIDEO_RGBIN_CTRL),
+ ENCL_INBUF_CNTL1,
+ readl(ENCL_INBUF_CNTL1),
+ ENCL_INBUF_CNTL0,
+ readl(ENCL_INBUF_CNTL0),
+ VPU_DISP_VIU0_CTRL,
+ readl(VPU_DISP_VIU0_CTRL),
+ VPU_VENC_CTRL,
+ readl(VPU_VENC_CTRL));
+ } else if (pdrv->config.basic.lcd_type == LCD_VBYONE) {
+ printf("pll regs:\n");
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n",
+ ANACTRL_TCON_PLL0_CNTL0,
+ readl(ANACTRL_TCON_PLL0_CNTL0),
+ ANACTRL_TCON_PLL0_CNTL1,
+ readl(ANACTRL_TCON_PLL0_CNTL1),
+ ANACTRL_TCON_PLL0_CNTL2,
+ readl(ANACTRL_TCON_PLL0_CNTL2),
+ ANACTRL_TCON_PLL0_CNTL3,
+ readl(ANACTRL_TCON_PLL0_CNTL3),
+ ANACTRL_TCON_PLL0_CNTL4,
+ readl(ANACTRL_TCON_PLL0_CNTL4),
+ ANACTRL_TCON_PLL0_STS,
+ readl(ANACTRL_TCON_PLL0_STS));
+
+ printf("clk regs:\n");
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n",
+ COMBO_DPHY_VID_PLL0_DIV,
+ readl(COMBO_DPHY_VID_PLL0_DIV),
+ CLKCTRL_VIID_CLK0_DIV,
+ readl(CLKCTRL_VIID_CLK0_DIV),
+ CLKCTRL_VIID_CLK0_CTRL,
+ readl(CLKCTRL_VIID_CLK0_CTRL),
+ CLKCTRL_VID_CLK0_CTRL2,
+ readl(CLKCTRL_VID_CLK0_CTRL2));
+
+ printf("vx1 regs:\n");
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n"
+ "0x%04x: 0x%08x\n",
+ VBO_VIN_CTRL,
+ readl(VBO_VIN_CTRL),
+ VBO_STATUS_L,
+ readl(VBO_STATUS_L),
+ VBO_LANES,
+ readl(VBO_LANES),
+ VBO_REGION_00,
+ readl(VBO_REGION_00),
+ VBO_REGION_01,
+ readl(VBO_REGION_01),
+ VBO_REGION_02,
+ readl(VBO_REGION_02),
+ VBO_REGION_03,
+ readl(VBO_REGION_03),
+ VBO_ACT_VSIZE,
+ readl(VBO_ACT_VSIZE),
+ VBO_CTRL_H,
+ readl(VBO_CTRL_H),
+ VBO_INTR_STATE_CTRL,
+ readl(VBO_INTR_STATE_CTRL),
+ VBO_INTR_STATE,
+ readl(VBO_INTR_STATE),
+ VBO_GCLK_MAIN,
+ readl(VBO_GCLK_MAIN),
+ VBO_INSGN_CTRL,
+ readl(VBO_INSGN_CTRL),
+ VBO_CTRL_L,
+ readl(VBO_CTRL_L));
+
+ printf("venc regs:\n");
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n",
+ ENCL_VIDEO_EN,
+ readl(ENCL_VIDEO_EN),
+ ENCL_VIDEO_MODE,
+ readl(ENCL_VIDEO_MODE),
+ ENCL_VIDEO_MODE_ADV,
+ readl(ENCL_VIDEO_MODE_ADV),
+ ENCL_VIDEO_FILT_CTRL,
+ readl(ENCL_VIDEO_FILT_CTRL),
+ ENCL_VIDEO_MAX_PXCNT,
+ readl(ENCL_VIDEO_MAX_PXCNT),
+ ENCL_VIDEO_MAX_LNCNT,
+ readl(ENCL_VIDEO_MAX_LNCNT),
+ ENCL_VIDEO_HAVON_BEGIN,
+ readl(ENCL_VIDEO_HAVON_BEGIN),
+ ENCL_VIDEO_HAVON_END,
+ readl(ENCL_VIDEO_HAVON_END),
+ ENCL_VIDEO_VAVON_BLINE,
+ readl(ENCL_VIDEO_VAVON_BLINE),
+ ENCL_VIDEO_VAVON_ELINE,
+ readl(ENCL_VIDEO_VAVON_ELINE),
+ ENCL_VIDEO_HSO_BEGIN,
+ readl(ENCL_VIDEO_HSO_BEGIN),
+ ENCL_VIDEO_HSO_END,
+ readl(ENCL_VIDEO_HSO_END),
+ ENCL_VIDEO_VSO_BEGIN,
+ readl(ENCL_VIDEO_VSO_BEGIN),
+ ENCL_VIDEO_VSO_END,
+ readl(ENCL_VIDEO_VSO_END),
+ ENCL_VIDEO_VSO_BLINE,
+ readl(ENCL_VIDEO_VSO_BLINE),
+ ENCL_VIDEO_VSO_ELINE,
+ readl(ENCL_VIDEO_VSO_ELINE),
+ ENCL_VIDEO_RGBIN_CTRL,
+ readl(ENCL_VIDEO_RGBIN_CTRL),
+ ENCL_INBUF_CNTL1,
+ readl(ENCL_INBUF_CNTL1),
+ ENCL_INBUF_CNTL0,
+ readl(ENCL_INBUF_CNTL0),
+ VPU_DISP_VIU0_CTRL,
+ readl(VPU_DISP_VIU0_CTRL),
+ VPU_VENC_CTRL,
+ readl(VPU_VENC_CTRL));
+ }
+ printf("0x%08x: 0x%08x\n",
+ VPU_VIU_VENC_MUX_CTRL,
+ readl(VPU_VIU_VENC_MUX_CTRL));
+
+ printf("phy regs:\n");
+ printf("0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n"
+ "0x%08x: 0x%08x\n",
+ ANACTRL_DIF_PHY_CNTL1,
+ readl(ANACTRL_DIF_PHY_CNTL1),
+ ANACTRL_DIF_PHY_CNTL2,
+ readl(ANACTRL_DIF_PHY_CNTL2),
+ ANACTRL_DIF_PHY_CNTL3,
+ readl(ANACTRL_DIF_PHY_CNTL3),
+ ANACTRL_DIF_PHY_CNTL4,
+ readl(ANACTRL_DIF_PHY_CNTL4),
+ ANACTRL_DIF_PHY_CNTL5,
+ readl(ANACTRL_DIF_PHY_CNTL5),
+ ANACTRL_DIF_PHY_CNTL6,
+ readl(ANACTRL_DIF_PHY_CNTL6),
+ ANACTRL_DIF_PHY_CNTL7,
+ readl(ANACTRL_DIF_PHY_CNTL7),
+ ANACTRL_DIF_PHY_CNTL8,
+ readl(ANACTRL_DIF_PHY_CNTL8),
+ ANACTRL_DIF_PHY_CNTL9,
+ readl(ANACTRL_DIF_PHY_CNTL9),
+ ANACTRL_DIF_PHY_CNTL10,
+ readl(ANACTRL_DIF_PHY_CNTL10),
+ ANACTRL_DIF_PHY_CNTL11,
+ readl(ANACTRL_DIF_PHY_CNTL11),
+ ANACTRL_DIF_PHY_CNTL12,
+ readl(ANACTRL_DIF_PHY_CNTL12),
+ ANACTRL_DIF_PHY_CNTL13,
+ readl(ANACTRL_DIF_PHY_CNTL13),
+ ANACTRL_DIF_PHY_CNTL14,
+ readl(ANACTRL_DIF_PHY_CNTL14),
+ ANACTRL_DIF_PHY_CNTL15,
+ readl(ANACTRL_DIF_PHY_CNTL15),
+ ANACTRL_DIF_PHY_CNTL16,
+ readl(ANACTRL_DIF_PHY_CNTL16),
+ ANACTRL_DIF_PHY_CNTL17,
+ readl(ANACTRL_DIF_PHY_CNTL17),
+ ANACTRL_DIF_PHY_CNTL18,
+ readl(ANACTRL_DIF_PHY_CNTL18),
+ ANACTRL_DIF_PHY_CNTL19,
+ readl(ANACTRL_DIF_PHY_CNTL19),
+ ANACTRL_DIF_PHY_CNTL20,
+ readl(ANACTRL_DIF_PHY_CNTL20),
+ ANACTRL_DIF_PHY_CNTL21,
+ readl(ANACTRL_DIF_PHY_CNTL21));
+}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_phy_config.c b/drivers/amlogic/media/vout/lcd/lcd_phy_config.c
new file mode 100644
index 0000000..b4ddb37
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/lcd_phy_config.c
@@ -0,0 +1,958 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+#include "lcd_reg.h"
+#include "lcd_phy_config.h"
+#include "lcd_common.h"
+
+static struct lcd_phy_ctrl_s *lcd_phy_ctrl;
+
+static void lcd_mipi_phy_set_g12a(struct aml_lcd_drv_s *pdrv, int status)
+{
+ unsigned int phy_reg, phy_bit, phy_width;
+ unsigned int lane_cnt;
+
+ if (status) {
+ /* HHI_MIPI_CNTL0 */
+ /* DIF_REF_CTL1:31-16bit, DIF_REF_CTL0:15-0bit */
+ lcd_ana_write(HHI_MIPI_CNTL0,
+ (0xa487 << 16) | (0x8 << 0));
+
+ /* HHI_MIPI_CNTL1 */
+ /* DIF_REF_CTL2:15-0bit; bandgap bit16 */
+ lcd_ana_write(HHI_MIPI_CNTL1,
+ (0x1 << 16) | (0x002e << 0));
+
+ /* HHI_MIPI_CNTL2 */
+ /* DIF_TX_CTL1:31-16bit, DIF_TX_CTL0:15-0bit */
+ lcd_ana_write(HHI_MIPI_CNTL2,
+ (0x2680 << 16) | (0x45a << 0));
+
+ phy_reg = HHI_MIPI_CNTL2;
+ phy_bit = MIPI_PHY_LANE_BIT;
+ phy_width = MIPI_PHY_LANE_WIDTH;
+ switch (pdrv->config.control.mipi_cfg.lane_num) {
+ case 1:
+ lane_cnt = DSI_LANE_COUNT_1;
+ break;
+ case 2:
+ lane_cnt = DSI_LANE_COUNT_2;
+ break;
+ case 3:
+ lane_cnt = DSI_LANE_COUNT_3;
+ break;
+ case 4:
+ lane_cnt = DSI_LANE_COUNT_4;
+ break;
+ default:
+ lane_cnt = 0;
+ break;
+ }
+ lcd_ana_setb(phy_reg, lane_cnt, phy_bit, phy_width);
+ } else {
+ lcd_ana_write(HHI_MIPI_CNTL0, 0);
+ lcd_ana_write(HHI_MIPI_CNTL1, 0);
+ lcd_ana_write(HHI_MIPI_CNTL2, 0);
+ }
+}
+
+static void lcd_phy_cntl_set_tl1(int status, unsigned int chreg, int bypass,
+ unsigned int ckdi)
+{
+ unsigned int tmp = 0;
+ unsigned int data = 0;
+ unsigned int cntl16 = 0;
+
+ if (!lcd_phy_ctrl)
+ return;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s: %d\n", __func__, status);
+
+ if (status) {
+ chreg |= ((lcd_phy_ctrl->ctrl_bit_on << 16) |
+ (lcd_phy_ctrl->ctrl_bit_on << 0));
+ if (bypass)
+ tmp |= ((1 << 18) | (1 << 2));
+ cntl16 = ckdi | 0x80000000;
+ } else {
+ if (lcd_phy_ctrl->ctrl_bit_on)
+ data = 0;
+ else
+ data = 1;
+ chreg |= ((data << 16) | (data << 0));
+ cntl16 = 0;
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL14, 0);
+ }
+
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL15, tmp);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL16, cntl16);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL8, tmp);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL1, chreg);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL9, tmp);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL2, chreg);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL10, tmp);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL3, chreg);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL11, tmp);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL4, chreg);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL12, tmp);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL6, chreg);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL13, tmp);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL7, chreg);
+}
+
+void lcd_phy_tcon_chpi_bbc_init_tl1(struct lcd_config_s *pconf)
+{
+ unsigned int data32 = 0x06020602;
+ unsigned int preem;
+ unsigned int size;
+ unsigned int n = 10;
+ struct p2p_config_s *p2p_conf;
+
+ if (!lcd_phy_ctrl)
+ return;
+
+ n = env_get_ulong("tcon_delay", 10, 10);
+ p2p_conf = &pconf->control.p2p_cfg;
+ size = sizeof(p2p_low_common_phy_preem_tl1) / sizeof(unsigned int);
+
+ /*get tcon tx pre_emphasis*/
+ preem = p2p_conf->phy_preem & 0xf;
+
+ /*check tx pre_emphasis ok or no*/
+ if (preem >= size) {
+ LCDERR("%s: invalid preem=0x%x, use default\n",
+ __func__, preem);
+ preem = 0x1;
+ }
+
+ udelay(n);
+ lcd_ana_setb(HHI_DIF_CSI_PHY_CNTL1, 1, 3, 1);
+ lcd_ana_setb(HHI_DIF_CSI_PHY_CNTL1, 1, 19, 1);
+ lcd_ana_setb(HHI_DIF_CSI_PHY_CNTL2, 1, 3, 1);
+ lcd_ana_setb(HHI_DIF_CSI_PHY_CNTL2, 1, 19, 1);
+ lcd_ana_setb(HHI_DIF_CSI_PHY_CNTL3, 1, 3, 1);
+ lcd_ana_setb(HHI_DIF_CSI_PHY_CNTL3, 1, 19, 1);
+ lcd_ana_setb(HHI_DIF_CSI_PHY_CNTL4, 1, 3, 1);
+ lcd_ana_setb(HHI_DIF_CSI_PHY_CNTL4, 1, 19, 1);
+ lcd_ana_setb(HHI_DIF_CSI_PHY_CNTL6, 1, 3, 1);
+ lcd_ana_setb(HHI_DIF_CSI_PHY_CNTL6, 1, 19, 1);
+ lcd_ana_setb(HHI_DIF_CSI_PHY_CNTL7, 1, 3, 1);
+ lcd_ana_setb(HHI_DIF_CSI_PHY_CNTL7, 1, 19, 1);
+ LCDPR("%s: delay: %dus\n", __func__, n);
+
+ /*follow pre-emphasis*/
+ data32 = p2p_low_common_phy_preem_tl1[preem];
+
+ if (lcd_phy_ctrl->ctrl_bit_on)
+ data32 &= ~((1 << 16) | (1 << 0));
+ else
+ data32 |= ((1 << 16) | (1 << 0));
+
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL1, data32);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL2, data32);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL3, data32);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL4, data32);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL6, data32);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL7, data32);
+}
+
+static void lcd_lvds_phy_set_tl1(struct aml_lcd_drv_s *pdrv, int status)
+{
+ unsigned int vswing, preem;
+ unsigned int data32 = 0, size;
+ struct lvds_config_s *lvds_conf;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s: %d\n", __func__, status);
+
+ lvds_conf = &pdrv->config.control.lvds_cfg;
+ if (status) {
+ vswing = lvds_conf->phy_vswing & 0xf;
+ preem = lvds_conf->phy_preem & 0xf;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("vswing=0x%x, preem=0x%x\n", vswing, preem);
+
+ size = sizeof(lvds_vx1_p2p_phy_preem_tl1) /
+ sizeof(unsigned int);
+ if (preem >= size) {
+ LCDERR("%s: invalid preem=0x%x, use default\n",
+ __func__, preem);
+ preem = 0;
+ }
+ data32 = lvds_vx1_p2p_phy_preem_tl1[preem];
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL14, 0xff2027e0 | vswing);
+ lcd_phy_cntl_set_tl1(status, data32, 0, 0);
+ } else {
+ lcd_phy_cntl_set_tl1(status, data32, 0, 0);
+ }
+}
+
+static void lcd_vbyone_phy_set_tl1(struct aml_lcd_drv_s *pdrv, int status)
+{
+ unsigned int vswing, preem, ext_pullup;
+ unsigned int data32 = 0, size;
+ struct vbyone_config_s *vbyone_conf;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s: %d\n", __func__, status);
+
+ vbyone_conf = &pdrv->config.control.vbyone_cfg;
+ if (status) {
+ ext_pullup = (vbyone_conf->phy_vswing >> 4) & 0x3;
+ vswing = vbyone_conf->phy_vswing & 0xf;
+ preem = vbyone_conf->phy_preem & 0xf;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("vswing=0x%x, preem=0x%x\n",
+ vbyone_conf->phy_vswing, preem);
+ }
+
+ size = sizeof(lvds_vx1_p2p_phy_preem_tl1) /
+ sizeof(unsigned int);
+ if (preem >= size) {
+ LCDERR("%s: invalid preem=0x%x, use default\n",
+ __func__, preem);
+ preem = 0x1;
+ }
+ data32 = lvds_vx1_p2p_phy_preem_tl1[preem];
+ if (ext_pullup) {
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL14,
+ 0xff2027e0 | vswing);
+ } else {
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL14,
+ 0xf02027a0 | vswing);
+ }
+ lcd_phy_cntl_set_tl1(status, data32, 1, 0);
+ } else {
+ lcd_phy_cntl_set_tl1(status, data32, 1, 0);
+ }
+}
+
+static void lcd_mlvds_phy_set_tl1(struct aml_lcd_drv_s *pdrv, int status)
+{
+ unsigned int vswing, preem;
+ unsigned int data32 = 0, size, ckdi;
+ struct mlvds_config_s *mlvds_conf;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s: %d\n", __func__, status);
+
+ mlvds_conf = &pdrv->config.control.mlvds_cfg;
+ if (status) {
+ vswing = mlvds_conf->phy_vswing & 0xf;
+ preem = mlvds_conf->phy_preem & 0xf;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("vswing=0x%x, preem=0x%x\n", vswing, preem);
+
+ size = sizeof(lvds_vx1_p2p_phy_preem_tl1) /
+ sizeof(unsigned int);
+ if (preem >= size) {
+ LCDERR("%s: invalid preem=0x%x, use default\n",
+ __func__, preem);
+ preem = 0;
+ }
+ data32 = lvds_vx1_p2p_phy_preem_tl1[preem];
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL14, 0xff2027e0 | vswing);
+ ckdi = (mlvds_conf->pi_clk_sel << 12);
+ lcd_phy_cntl_set_tl1(status, data32, 0, ckdi);
+ } else {
+ lcd_phy_cntl_set_tl1(status, data32, 0, 0);
+ }
+}
+
+static void lcd_p2p_phy_set_tl1(struct aml_lcd_drv_s *pdrv, int status)
+{
+ unsigned int vswing, preem, p2p_type;
+ unsigned int data32 = 0, size;
+ struct p2p_config_s *p2p_conf;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s: %d\n", __func__, status);
+
+ p2p_conf = &pdrv->config.control.p2p_cfg;
+ if (status) {
+ vswing = p2p_conf->phy_vswing & 0xf;
+ preem = p2p_conf->phy_preem & 0xf;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("vswing=0x%x, preem=0x%x\n", vswing, preem);
+
+ p2p_type = p2p_conf->p2p_type & 0x1f;
+ switch (p2p_type) {
+ case P2P_CEDS:
+ case P2P_CMPI:
+ case P2P_ISP:
+ case P2P_EPI:
+ size = sizeof(lvds_vx1_p2p_phy_preem_tl1) /
+ sizeof(unsigned int);
+ if (preem >= size) {
+ LCDERR("%s: invalid preem=0x%x, use default\n",
+ __func__, preem);
+ preem = 0x1;
+ }
+ data32 = lvds_vx1_p2p_phy_preem_tl1[preem];
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL14,
+ 0xff2027a0 | vswing);
+ lcd_phy_cntl_set_tl1(status, data32, 1, 0);
+ break;
+ case P2P_CHPI: /* low common mode */
+ case P2P_CSPI:
+ case P2P_USIT:
+ size = sizeof(p2p_low_common_phy_preem_tl1) /
+ sizeof(unsigned int);
+ if (preem >= size) {
+ LCDERR("%s: invalid preem=0x%x, use default\n",
+ __func__, preem);
+ preem = 0x1;
+ }
+ data32 = p2p_low_common_phy_preem_tl1[preem];
+ if (p2p_type == P2P_CHPI) {
+ /* weakly pull down */
+ data32 &= ~((1 << 19) | (1 << 3));
+ }
+
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL14, 0xfe60027f);
+ lcd_phy_cntl_set_tl1(status, data32, 1, 0);
+ break;
+ default:
+ LCDERR("%s: invalid p2p_type %d\n", __func__, p2p_type);
+ break;
+ }
+ } else {
+ lcd_phy_cntl_set_tl1(status, data32, 1, 0);
+ }
+}
+
+/*
+ * chreg: channel ctrl
+ * bypass: 1=bypass
+ * mode: 1=normal mode, 0=low common mode
+ * ckdi: clk phase for minilvds
+ */
+static void lcd_phy_cntl_set_t5(int status, unsigned int chreg, int bypass,
+ unsigned int mode, unsigned int ckdi)
+{
+ unsigned int cntl15 = 0, cntl16 = 0;
+ unsigned int data = 0;
+ unsigned int tmp = 0;
+
+ if (!lcd_phy_ctrl)
+ return;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s: %d\n", __func__, status);
+
+ if (status) {
+ chreg |= ((lcd_phy_ctrl->ctrl_bit_on << 16) |
+ (lcd_phy_ctrl->ctrl_bit_on << 0));
+ if (bypass)
+ tmp |= ((1 << 18) | (1 << 2));
+ if (mode)
+ cntl15 = 0x00070000;
+ else
+ cntl15 = 0x000e0000;
+ cntl16 = ckdi | 0x80000000;
+ } else {
+ if (lcd_phy_ctrl->ctrl_bit_on)
+ data = 0;
+ else
+ data = 1;
+ chreg |= ((data << 16) | (data << 0));
+ cntl15 = 0;
+ cntl16 = 0;
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL14, 0);
+ }
+
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL15, cntl15);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL16, cntl16);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL8, tmp);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL1, chreg);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL9, tmp);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL2, chreg);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL10, tmp);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL3, chreg);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL11, tmp);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL4, chreg);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL12, tmp);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL6, chreg);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL13, tmp);
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL7, chreg);
+}
+
+static void lcd_lvds_phy_set_t5(struct aml_lcd_drv_s *pdrv, int status)
+{
+ unsigned int vswing, preem;
+ unsigned int data32 = 0, size;
+ struct lvds_config_s *lvds_conf;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s: %d\n", __func__, status);
+
+ lvds_conf = &pdrv->config.control.lvds_cfg;
+ if (status) {
+ vswing = lvds_conf->phy_vswing & 0xf;
+ preem = lvds_conf->phy_preem & 0xf;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("vswing=0x%x, preem=0x%x\n", vswing, preem);
+
+ size = sizeof(lvds_vx1_p2p_phy_preem_tl1) /
+ sizeof(unsigned int);
+ if (preem >= size) {
+ LCDERR("%s: invalid preem=0x%x, use default\n",
+ __func__, preem);
+ preem = 0;
+ }
+ data32 = lvds_vx1_p2p_phy_preem_tl1[preem];
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL14, 0xff2027e0 | vswing);
+ lcd_phy_cntl_set_t5(status, data32, 0, 1, 0);
+ } else {
+ lcd_phy_cntl_set_t5(status, data32, 0, 0, 0);
+ }
+}
+
+static void lcd_vbyone_phy_set_t5(struct aml_lcd_drv_s *pdrv, int status)
+{
+ unsigned int vswing, preem, ext_pullup;
+ unsigned int data32 = 0, size;
+ struct vbyone_config_s *vbyone_conf;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s: %d\n", __func__, status);
+
+ vbyone_conf = &pdrv->config.control.vbyone_cfg;
+ if (status) {
+ ext_pullup = (vbyone_conf->phy_vswing >> 4) & 0x3;
+ vswing = vbyone_conf->phy_vswing & 0xf;
+ preem = vbyone_conf->phy_preem & 0xf;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("vswing=0x%x, preem=0x%x\n",
+ vbyone_conf->phy_vswing, preem);
+ }
+
+ size = sizeof(lvds_vx1_p2p_phy_preem_tl1) /
+ sizeof(unsigned int);
+ if (preem >= size) {
+ LCDERR("%s: invalid preem=0x%x, use default\n",
+ __func__, preem);
+ preem = 0x1;
+ }
+ data32 = lvds_vx1_p2p_phy_preem_tl1[preem];
+ if (ext_pullup) {
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL14,
+ 0xff2027e0 | vswing);
+ } else {
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL14,
+ 0xf02027a0 | vswing);
+ }
+ lcd_phy_cntl_set_t5(status, data32, 1, 1, 0);
+ } else {
+ lcd_phy_cntl_set_t5(status, data32, 1, 0, 0);
+ }
+}
+
+static void lcd_mlvds_phy_set_t5(struct aml_lcd_drv_s *pdrv, int status)
+{
+ unsigned int vswing, preem;
+ unsigned int data32 = 0, size, ckdi;
+ struct mlvds_config_s *mlvds_conf;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s: %d\n", __func__, status);
+
+ mlvds_conf = &pdrv->config.control.mlvds_cfg;
+ if (status) {
+ vswing = mlvds_conf->phy_vswing & 0xf;
+ preem = mlvds_conf->phy_preem & 0xf;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("vswing=0x%x, preem=0x%x\n", vswing, preem);
+
+ size = sizeof(lvds_vx1_p2p_phy_preem_tl1) /
+ sizeof(unsigned int);
+ if (preem >= size) {
+ LCDERR("%s: invalid preem=0x%x, use default\n",
+ __func__, preem);
+ preem = 0;
+ }
+ data32 = lvds_vx1_p2p_phy_preem_tl1[preem];
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL14, 0xff2027e0 | vswing);
+ ckdi = (mlvds_conf->pi_clk_sel << 12);
+ lcd_phy_cntl_set_t5(status, data32, 0, 1, ckdi);
+ } else {
+ lcd_phy_cntl_set_t5(status, data32, 0, 0, 0);
+ }
+}
+
+static void lcd_p2p_phy_set_t5(struct aml_lcd_drv_s *pdrv, int status)
+{
+ unsigned int vswing, preem, p2p_type, vcm_flag;
+ unsigned int data32 = 0, size;
+ struct p2p_config_s *p2p_conf;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s: %d\n", __func__, status);
+
+ p2p_conf = &pdrv->config.control.p2p_cfg;
+ if (status) {
+ vswing = p2p_conf->phy_vswing & 0xf;
+ preem = p2p_conf->phy_preem & 0xf;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("vswing=0x%x, preem=0x%x\n", vswing, preem);
+
+ p2p_type = p2p_conf->p2p_type & 0x1f;
+ vcm_flag = (p2p_conf->p2p_type >> 5) & 0x1;
+ switch (p2p_type) {
+ case P2P_CEDS:
+ case P2P_CMPI:
+ case P2P_ISP:
+ case P2P_EPI:
+ size = sizeof(lvds_vx1_p2p_phy_preem_tl1) /
+ sizeof(unsigned int);
+ if (preem >= size) {
+ LCDERR("%s: invalid preem=0x%x, use default\n",
+ __func__, preem);
+ preem = 0x1;
+ }
+ data32 = lvds_vx1_p2p_phy_preem_tl1[preem];
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL14,
+ 0xff2027a0 | vswing);
+ lcd_phy_cntl_set_t5(status, data32, 1, 1, 0);
+ break;
+ case P2P_CHPI: /* low common mode */
+ case P2P_CSPI:
+ case P2P_USIT:
+ size = sizeof(p2p_low_common_phy_preem_tl1) /
+ sizeof(unsigned int);
+ if (preem >= size) {
+ LCDERR("%s: invalid preem=0x%x, use default\n",
+ __func__, preem);
+ preem = 0x1;
+ }
+ data32 = p2p_low_common_phy_preem_tl1[preem];
+ if (p2p_type == P2P_CHPI) {
+ /* weakly pull down */
+ data32 &= ~((1 << 19) | (1 << 3));
+ }
+
+ if (vcm_flag) { /* 580mV */
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL14,
+ 0xe0600272);
+ } else {
+ lcd_ana_write(HHI_DIF_CSI_PHY_CNTL14,
+ 0xfe60027f);
+ } /* default 385mV */
+ lcd_phy_cntl_set_t5(status, data32, 1, 0, 0);
+ break;
+ default:
+ LCDERR("%s: invalid p2p_type %d\n", __func__, p2p_type);
+ break;
+ }
+ } else {
+ lcd_phy_cntl_set_t5(status, data32, 1, 0, 0);
+ }
+}
+
+static void lcd_phy_cntl_set_t7(unsigned int flag,
+ unsigned int data_lane0_aux,
+ unsigned int data_lane1_aux,
+ unsigned int data_lane)
+{
+ if (flag & (1 << 0)) {
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL1, data_lane0_aux);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL2, data_lane1_aux);
+ }
+ if (flag & (1 << 1))
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL3, data_lane);
+ if (flag & (1 << 2))
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL4, data_lane);
+ if (flag & (1 << 3))
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL5, data_lane);
+ if (flag & (1 << 4))
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL6, data_lane);
+ if (flag & (1 << 5))
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL7, data_lane);
+ if (flag & (1 << 6))
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL8, data_lane);
+ if (flag & (1 << 7))
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL9, data_lane);
+ if (flag & (1 << 8)) {
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL10, data_lane0_aux);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL11, data_lane1_aux);
+ }
+ if (flag & (1 << 9))
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL12, data_lane);
+ if (flag & (1 << 10))
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL13, data_lane);
+ if (flag & (1 << 11))
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL14, data_lane);
+ if (flag & (1 << 12))
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL15, data_lane);
+ if (flag & (1 << 13))
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL16, data_lane);
+ if (flag & (1 << 14))
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL17, data_lane);
+ if (flag & (1 << 15))
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL18, data_lane);
+}
+
+static void lcd_lvds_phy_set_t7(struct aml_lcd_drv_s *pdrv, int status)
+{
+ unsigned int vswing, preem;
+ unsigned int flag, data_lane0_aux, data_lane1_aux, data_lane;
+ struct lvds_config_s *lvds_conf;
+
+ if (!lcd_phy_ctrl)
+ return;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s: %d\n", __func__, status);
+
+ lvds_conf = &pdrv->config.control.lvds_cfg;
+ switch (pdrv->index) {
+ case 0:
+ if (lvds_conf->dual_port) {
+ LCDERR("don't suuport lvds dual_port for drv_index %d\n",
+ pdrv->index);
+ return;
+ }
+ flag = 0x1f;
+ break;
+ case 1:
+ if (lvds_conf->dual_port) {
+ LCDERR("don't suuport lvds dual_port for drv_index %d\n",
+ pdrv->index);
+ return;
+ }
+ flag = (0x1f << 5);
+ break;
+ case 2:
+ if (lvds_conf->dual_port)
+ flag = (0x3ff << 5);
+ else
+ flag = (0x1f << 10);
+ break;
+ default:
+ LCDERR("invalid drv_index %d for lvds\n", pdrv->index);
+ return;
+ }
+
+ if (status) {
+ if (lcd_phy_ctrl->lane_lock & flag) {
+ LCDERR("phy lane already locked: 0x%x, invalid 0x%x\n",
+ lcd_phy_ctrl->lane_lock, flag);
+ return;
+ }
+ lcd_phy_ctrl->lane_lock |= flag;
+ vswing = lvds_conf->phy_vswing & 0xf;
+ preem = lvds_conf->phy_preem & 0xf;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("vswing=0x%x, preem=0x%x\n", vswing, preem);
+
+ data_lane0_aux = 0x16430028;
+ data_lane1_aux = 0x0100ffff;
+ data_lane = 0x06530028 | (preem << 28);
+ lcd_phy_cntl_set_t7(flag, data_lane0_aux, data_lane1_aux, data_lane);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL19, 0x00406240 | vswing);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL20, 0);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL21, 0);
+ } else {
+ lcd_phy_ctrl->lane_lock &= ~flag;
+ lcd_phy_cntl_set_t7(flag, 0, 0, 0);
+ if (lcd_phy_ctrl->lane_lock == 0)
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL19, 0);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL20, 0);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL21, 0);
+ }
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("phy lane_lock: 0x%x\n", lcd_phy_ctrl->lane_lock);
+}
+
+static void lcd_vbyone_phy_set_t7(struct aml_lcd_drv_s *pdrv, int status)
+{
+ unsigned int vswing, preem;
+ unsigned int flag, data_lane0_aux, data_lane1_aux, data_lane;
+ struct vbyone_config_s *vbyone_conf;
+
+ if (!lcd_phy_ctrl)
+ return;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s: %d\n", __func__, status);
+
+ switch (pdrv->index) {
+ case 0:
+ flag = 0xff;
+ break;
+ case 1:
+ flag = (0xff << 8);
+ break;
+ default:
+ LCDERR("invalid drv_index %d for vbyone\n", pdrv->index);
+ return;
+ }
+
+ vbyone_conf = &pdrv->config.control.vbyone_cfg;
+ if (status) {
+ if (lcd_phy_ctrl->lane_lock & flag) {
+ LCDERR("phy lane already locked: 0x%x, invalid 0x%x\n",
+ lcd_phy_ctrl->lane_lock, flag);
+ return;
+ }
+ lcd_phy_ctrl->lane_lock |= flag;
+ vswing = vbyone_conf->phy_vswing & 0xf;
+ preem = vbyone_conf->phy_preem & 0xf;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("vswing=0x%x, preem=0x%x\n", vswing, preem);
+
+ data_lane0_aux = 0x26430028;
+ data_lane1_aux = 0x0000ffff;
+ data_lane = 0x06530028 | (preem << 28);
+ lcd_phy_cntl_set_t7(flag, data_lane0_aux, data_lane1_aux, data_lane);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL19, 0x00401640 | vswing);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL20, 0);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL21, 0);
+ } else {
+ lcd_phy_ctrl->lane_lock &= ~flag;
+ lcd_phy_cntl_set_t7(flag, 0, 0, 0);
+ if (lcd_phy_ctrl->lane_lock == 0)
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL19, 0);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL20, 0);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL21, 0);
+ }
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("phy lane_lock: 0x%x\n", lcd_phy_ctrl->lane_lock);
+}
+
+static void lcd_mipi_phy_set_t7(struct aml_lcd_drv_s *pdrv, int status)
+{
+ unsigned int flag, data_lane0_aux, data_lane1_aux, data_lane;
+
+ if (!lcd_phy_ctrl)
+ return;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s: %d\n", __func__, status);
+
+ switch (pdrv->index) {
+ case 0:
+ flag = 0x1f;
+ break;
+ case 1:
+ flag = (0x1f << 8);
+ break;
+ default:
+ LCDERR("invalid drv_index %d for mipi-dsi\n", pdrv->index);
+ return;
+ }
+
+ if (status) {
+ if (lcd_phy_ctrl->lane_lock & flag) {
+ LCDERR("phy lane already locked: 0x%x, invalid 0x%x\n",
+ lcd_phy_ctrl->lane_lock, flag);
+ return;
+ }
+ lcd_phy_ctrl->lane_lock |= flag;
+
+ data_lane0_aux = 0x022a0028;
+ data_lane1_aux = 0x0000ffcf;
+ data_lane = 0x022a0028;
+ lcd_phy_cntl_set_t7(flag, data_lane0_aux, data_lane1_aux, data_lane);
+ if (pdrv->index)
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL13, 0x822a0028);
+ else
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL4, 0x822a0028);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL19, 0x1e406253);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL20, 0xffff0000);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL21, 0);
+ } else {
+ lcd_phy_ctrl->lane_lock &= ~flag;
+ lcd_phy_cntl_set_t7(flag, 0, 0, 0);
+ if (lcd_phy_ctrl->lane_lock == 0)
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL19, 0);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL20, 0);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL21, 0);
+ }
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("phy lane_lock: 0x%x\n", lcd_phy_ctrl->lane_lock);
+}
+
+static void lcd_edp_phy_set_t7(struct aml_lcd_drv_s *pdrv, int status)
+{
+ unsigned int vswing, preem;
+ unsigned int flag, data_lane0_aux, data_lane1_aux, data_lane;
+ struct edp_config_s *edp_conf;
+
+ if (!lcd_phy_ctrl)
+ return;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s: %d\n", __func__, status);
+
+ switch (pdrv->index) {
+ case 0:
+ flag = 0x1f;
+ break;
+ case 1:
+ flag = (0x1f << 8);
+ break;
+ default:
+ LCDERR("invalid drv_index %d for edp\n", pdrv->index);
+ return;
+ }
+
+ edp_conf = &pdrv->config.control.edp_cfg;
+ if (status) {
+ if (lcd_phy_ctrl->lane_lock & flag) {
+ LCDERR("phy lane already locked: 0x%x, invalid 0x%x\n",
+ lcd_phy_ctrl->lane_lock, flag);
+ return;
+ }
+ lcd_phy_ctrl->lane_lock |= flag;
+ vswing = edp_conf->phy_vswing & 0xf;
+ preem = edp_conf->phy_preem & 0xf;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("vswing=0x%x, preem=0x%x\n", vswing, preem);
+
+ data_lane0_aux = 0x46770038;
+ data_lane1_aux = 0x0000ffff;
+ data_lane = 0x06530028 | (preem << 28);
+ lcd_phy_cntl_set_t7(flag, data_lane0_aux, data_lane1_aux, data_lane);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL19, 0x00406240 | vswing);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL20, 0);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL21, 0);
+ } else {
+ lcd_phy_ctrl->lane_lock &= ~flag;
+ lcd_phy_cntl_set_t7(flag, 0, 0, 0);
+ if (lcd_phy_ctrl->lane_lock == 0)
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL19, 0);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL20, 0);
+ lcd_ana_write(ANACTRL_DIF_PHY_CNTL21, 0);
+ }
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("phy lane_lock: 0x%x\n", lcd_phy_ctrl->lane_lock);
+}
+
+void lcd_phy_set(struct aml_lcd_drv_s *pdrv, int status)
+{
+ if (!pdrv->phy_set)
+ return;
+
+ pdrv->phy_set(pdrv, status);
+}
+
+struct lcd_phy_ctrl_s lcd_phy_ctrl_g12a = {
+ .lane_lock = 0,
+ .phy_set_lvds = NULL,
+ .phy_set_vx1 = NULL,
+ .phy_set_mlvds = NULL,
+ .phy_set_p2p = NULL,
+ .phy_set_mipi = lcd_mipi_phy_set_g12a,
+ .phy_set_edp = NULL,
+};
+
+struct lcd_phy_ctrl_s lcd_phy_ctrl_tl1 = {
+ .lane_lock = 0,
+ .phy_set_lvds = lcd_lvds_phy_set_tl1,
+ .phy_set_vx1 = lcd_vbyone_phy_set_tl1,
+ .phy_set_mlvds = lcd_mlvds_phy_set_tl1,
+ .phy_set_p2p = lcd_p2p_phy_set_tl1,
+ .phy_set_mipi = NULL,
+ .phy_set_edp = NULL,
+};
+
+struct lcd_phy_ctrl_s lcd_phy_ctrl_t5 = {
+ .lane_lock = 0,
+ .phy_set_lvds = lcd_lvds_phy_set_t5,
+ .phy_set_vx1 = lcd_vbyone_phy_set_t5,
+ .phy_set_mlvds = lcd_mlvds_phy_set_t5,
+ .phy_set_p2p = lcd_p2p_phy_set_t5,
+ .phy_set_mipi = NULL,
+ .phy_set_edp = NULL,
+};
+
+struct lcd_phy_ctrl_s lcd_phy_ctrl_t7 = {
+ .lane_lock = 0,
+ .phy_set_lvds = lcd_lvds_phy_set_t7,
+ .phy_set_vx1 = lcd_vbyone_phy_set_t7,
+ .phy_set_mlvds = NULL,
+ .phy_set_p2p = NULL,
+ .phy_set_mipi = lcd_mipi_phy_set_t7,
+ .phy_set_edp = lcd_edp_phy_set_t7,
+};
+
+int lcd_phy_probe(struct aml_lcd_drv_s *pdrv)
+{
+#ifdef CONFIG_AML_LCD_PXP
+ pdrv->phy_set = NULL;
+ return 0;
+#endif
+
+ if (!lcd_phy_ctrl)
+ return 0;
+
+ switch (pdrv->config.basic.lcd_type) {
+ case LCD_LVDS:
+ pdrv->phy_set = lcd_phy_ctrl->phy_set_lvds;
+ break;
+ case LCD_VBYONE:
+ pdrv->phy_set = lcd_phy_ctrl->phy_set_vx1;
+ break;
+ case LCD_MLVDS:
+ pdrv->phy_set = lcd_phy_ctrl->phy_set_mlvds;
+ break;
+ case LCD_P2P:
+ pdrv->phy_set = lcd_phy_ctrl->phy_set_p2p;
+ break;
+ case LCD_MIPI:
+ pdrv->phy_set = lcd_phy_ctrl->phy_set_mipi;
+ break;
+ case LCD_EDP:
+ pdrv->phy_set = lcd_phy_ctrl->phy_set_edp;
+ break;
+ default:
+ pdrv->phy_set = NULL;
+ break;
+ }
+
+ return 0;
+}
+
+int lcd_phy_config_init(struct aml_lcd_data_s *pdata)
+{
+ lcd_phy_ctrl = NULL;
+
+ switch (pdata->chip_type) {
+ case LCD_CHIP_G12A:
+ case LCD_CHIP_G12B:
+ case LCD_CHIP_SM1:
+ lcd_phy_ctrl = &lcd_phy_ctrl_g12a;
+ break;
+ case LCD_CHIP_TL1:
+ lcd_phy_ctrl = &lcd_phy_ctrl_tl1;
+ if (pdata->rev_type == 0xA || pdata->rev_type == 0xB)
+ lcd_phy_ctrl->ctrl_bit_on = 0;
+ else
+ lcd_phy_ctrl->ctrl_bit_on = 1;
+ break;
+ case LCD_CHIP_TM2:
+ lcd_phy_ctrl = &lcd_phy_ctrl_tl1;
+ if (pdata->rev_type == 0xA)
+ lcd_phy_ctrl->ctrl_bit_on = 0;
+ else
+ lcd_phy_ctrl->ctrl_bit_on = 1;
+ break;
+ case LCD_CHIP_T5:
+ case LCD_CHIP_T5D:
+ lcd_phy_ctrl = &lcd_phy_ctrl_t5;
+ break;
+ case LCD_CHIP_T7:
+ lcd_phy_ctrl = &lcd_phy_ctrl_t7;
+ break;
+ default:
+ break;
+ }
+
+ return 0;
+}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_phy_config.h b/drivers/amlogic/media/vout/lcd/lcd_phy_config.h
new file mode 100644
index 0000000..a15a3af
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/lcd_phy_config.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _AML_LCD_PHY_CONFIG_H
+#define _AML_LCD_PHY_CONFIG_H
+#include <amlogic/media/vout/lcd/lcd_vout.h>
+
+struct lcd_phy_ctrl_s {
+ unsigned int lane_lock;
+ unsigned int ctrl_bit_on;
+ void (*phy_set_lvds)(struct aml_lcd_drv_s *pdrv, int status);
+ void (*phy_set_vx1)(struct aml_lcd_drv_s *pdrv, int status);
+ void (*phy_set_mlvds)(struct aml_lcd_drv_s *pdrv, int status);
+ void (*phy_set_p2p)(struct aml_lcd_drv_s *pdrv, int status);
+ void (*phy_set_mipi)(struct aml_lcd_drv_s *pdrv, int status);
+ void (*phy_set_edp)(struct aml_lcd_drv_s *pdrv, int status);
+};
+
+/* -------------------------- */
+/* lvsd phy parameters define */
+/* -------------------------- */
+#define LVDS_PHY_CNTL1_G9TV 0x606cca80
+#define LVDS_PHY_CNTL2_G9TV 0x0000006c
+#define LVDS_PHY_CNTL3_G9TV 0x00000800
+
+#define LVDS_PHY_CNTL1_TXHD 0x6c60ca80
+#define LVDS_PHY_CNTL2_TXHD 0x00000070
+#define LVDS_PHY_CNTL3_TXHD 0x03ff0c00
+/* -------------------------- */
+
+/* -------------------------- */
+/* vbyone phy parameters define */
+/* -------------------------- */
+#define VX1_PHY_CNTL1_G9TV 0x6e0ec900
+#define VX1_PHY_CNTL1_G9TV_PULLUP 0x6e0f4d00
+#define VX1_PHY_CNTL2_G9TV 0x0000007c
+#define VX1_PHY_CNTL3_G9TV 0x00ff0800
+/* -------------------------- */
+
+/* -------------------------- */
+/* minilvds phy parameters define */
+/* -------------------------- */
+#define MLVDS_PHY_CNTL1_TXHD 0x6c60ca80
+#define MLVDS_PHY_CNTL2_TXHD 0x00000070
+#define MLVDS_PHY_CNTL3_TXHD 0x03ff0c00
+/* -------------------------- */
+
+/* ******** MIPI_DSI_PHY ******** */
+/* bit[15:11] */
+#define MIPI_PHY_LANE_BIT 11
+#define MIPI_PHY_LANE_WIDTH 5
+
+/* MIPI-DSI */
+#define DSI_LANE_0 BIT(4)
+#define DSI_LANE_1 BIT(3)
+#define DSI_LANE_CLK BIT(2)
+#define DSI_LANE_2 BIT(1)
+#define DSI_LANE_3 BIT(0)
+#define DSI_LANE_COUNT_1 (DSI_LANE_CLK | DSI_LANE_0)
+#define DSI_LANE_COUNT_2 (DSI_LANE_CLK | DSI_LANE_0 | DSI_LANE_1)
+#define DSI_LANE_COUNT_3 (DSI_LANE_CLK | DSI_LANE_0 |\
+ DSI_LANE_1 | DSI_LANE_2)
+#define DSI_LANE_COUNT_4 (DSI_LANE_CLK | DSI_LANE_0 |\
+ DSI_LANE_1 | DSI_LANE_2 | DSI_LANE_3)
+
+static unsigned int lvds_vx1_p2p_phy_preem_tl1[] = {
+ 0x06020602,
+ 0x26022602,
+ 0x46024602,
+ 0x66026602,
+ 0x86028602,
+ 0xa602a602,
+ 0xf602f602,
+};
+
+static unsigned int p2p_low_common_phy_preem_tl1[] = {
+ 0x070b070b,
+ 0x170b170b,
+ 0x370b370b,
+ 0x770b770b,
+ 0xf70bf70b,
+ 0xff0bff0b,
+};
+
+#endif
+
diff --git a/drivers/amlogic/media/vout/lcd/lcd_reg.h b/drivers/amlogic/media/vout/lcd/lcd_reg.h
index 6c2e618..f5a0134 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_reg.h
+++ b/drivers/amlogic/media/vout/lcd/lcd_reg.h
@@ -1,29 +1,14 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/vout/lcd/lcd_reg.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __AML_LCD_REG_H__
#define __AML_LCD_REG_H__
+#include <asm/arch/cpu.h>
#include <asm/arch/io.h>
#include <asm/arch/secure_apb.h>
-#include <asm/arch/cpu.h>
+#include "edp_tx_reg.h"
#include "lcd_dummy_reg.h"
/* ********************************
@@ -32,45 +17,28 @@
/* base & offset */
#define REG_OFFSET_CBUS(reg) ((reg) << 2)
#define REG_OFFSET_VCBUS(reg) ((reg) << 2)
-#define REG_OFFSET_DSI_HOST(reg) ((reg) << 2)
+#define REG_OFFSET_DSI_HOST(reg) ((reg > 0x10000) ? (reg & 0xfff) : ((reg & 0xff) << 2))
+#define REG_OFFSET_DSI_PHY(reg) (reg & 0xfff)
#define REG_OFFSET_TCON_APB(reg) ((reg) << 2)
#define REG_OFFSET_TCON_APB_BYTE(reg) (reg)
/* memory mapping */
#define REG_ADDR_AOBUS(reg) (reg + 0L)
#define REG_ADDR_PERIPHS(reg) (reg + 0L)
-#define REG_ADDR_CBUS(reg) (REG_BASE_CBUS + REG_OFFSET_CBUS(reg))
+#define REG_ADDR_CBUS(reg) ((reg > 0x10000) ? (reg + 0L) : \
+ (REG_BASE_CBUS + REG_OFFSET_CBUS(reg)))
+#define REG_ADDR_RESET(reg) (reg + 0L)
#define REG_ADDR_HIU(reg) (reg + 0L)
-#define REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg))
-#define REG_ADDR_DSI_HOST(reg) (REG_BASE_DSI_HOST + REG_OFFSET_DSI_HOST(reg))
-#define REG_ADDR_DSI_PHY(reg) (reg + 0L)
+#define REG_ADDR_COMBO(reg) (reg + 0L)
+#define REG_ADDR_VCBUS(reg) ((reg > 0x10000) ? (reg + 0L) : \
+ (REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg)))
+#define REG_ADDR_DSI_HOST(reg) (MIPI_DSI_BASE + REG_OFFSET_DSI_HOST(reg))
+#define REG_ADDR_DSI_PHY(reg) (MIPI_DSI_PHY_BASE + REG_OFFSET_DSI_PHY(reg))
+#define REG_ADDR_DSI_B_HOST(reg) (MIPI_DSI_B_BASE + REG_OFFSET_DSI_HOST(reg))
+#define REG_ADDR_DSI_B_PHY(reg) (MIPI_DSI_B_PHY_BASE + REG_OFFSET_DSI_PHY(reg))
#define REG_ADDR_TCON_APB(reg) (REG_TCON_APB_BASE + REG_OFFSET_TCON_APB(reg))
#define REG_ADDR_TCON_APB_BYTE(reg) (REG_TCON_APB_BASE + REG_OFFSET_TCON_APB_BYTE(reg))
-
-#if (defined(CONFIG_CHIP_AML_GXB) || \
- defined(CONFIG_AML_MESON_GXTVBB))
-#define HHI_HPLL_CNTL HHI_HDMI_PLL_CNTL
-#define HHI_HPLL_CNTL2 HHI_HDMI_PLL_CNTL2
-#define HHI_HPLL_CNTL3 HHI_HDMI_PLL_CNTL3
-#define HHI_HPLL_CNTL4 HHI_HDMI_PLL_CNTL4
-#define HHI_HPLL_CNTL5 HHI_HDMI_PLL_CNTL5
-#define HHI_HPLL_CNTL6 HHI_HDMI_PLL_CNTL6
-#else
-#define HHI_HPLL_CNTL HHI_HDMI_PLL_CNTL
-#define HHI_HPLL_CNTL2 HHI_HDMI_PLL_CNTL1
-#define HHI_HPLL_CNTL3 HHI_HDMI_PLL_CNTL2
-#define HHI_HPLL_CNTL4 HHI_HDMI_PLL_CNTL3
-#define HHI_HPLL_CNTL5 HHI_HDMI_PLL_CNTL4
-#define HHI_HPLL_CNTL6 HHI_HDMI_PLL_CNTL5
-#endif
-
-#define LVDS_CH_SWAP0 LVDS_PHY_CNTL0
-#define LVDS_CH_SWAP1 LVDS_PHY_CNTL1
-#define LVDS_CH_SWAP2 LVDS_PHY_CNTL2
-
-
-
/*#define HHI_VIID_CLK_DIV 0x4a*/
#define DAC0_CLK_SEL 28
#define DAC1_CLK_SEL 24
@@ -121,306 +89,601 @@
#define ENCT_GATE_VCLK 1
#define ENCI_GATE_VCLK 0
+//#define LCD_REG_DEBUG 1
+
/* ********************************
* register access api
* ********************************* */
/* use offset address */
-static inline unsigned int lcd_hiu_read(unsigned int _reg)
+static inline unsigned int lcd_combo_dphy_read(unsigned int reg)
{
- return *(volatile unsigned int *)(REG_ADDR_HIU(_reg));
+ unsigned int val;
+
+ val = *(volatile unsigned int *)(REG_ADDR_COMBO(reg));
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%08x\n", __func__, reg, val);
+
+ return val;
};
-static inline void lcd_hiu_write(unsigned int _reg, unsigned int _value)
+static inline void lcd_combo_dphy_write(unsigned int reg, unsigned int val)
{
- *(volatile unsigned int *)REG_ADDR_HIU(_reg) = (_value);
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%08x\n", __func__, reg, val);
+ *(volatile unsigned int *)REG_ADDR_COMBO(reg) = (val);
};
-static inline void lcd_hiu_setb(unsigned int _reg, unsigned int _value,
- unsigned int _start, unsigned int _len)
+static inline void lcd_combo_dphy_setb(unsigned int reg, unsigned int val,
+ unsigned int start, unsigned int len)
{
- lcd_hiu_write(_reg, ((lcd_hiu_read(_reg) &
- ~(((1L << (_len))-1) << (_start))) |
- (((_value)&((1L<<(_len))-1)) << (_start))));
+ lcd_combo_dphy_write(reg, ((lcd_combo_dphy_read(reg) &
+ ~(((1L << (len))-1) << (start))) |
+ (((val)&((1L<<(len))-1)) << (start))));
}
-static inline unsigned int lcd_hiu_getb(unsigned int _reg,
- unsigned int _start, unsigned int _len)
+static inline unsigned int lcd_combo_dphy_getb(unsigned int reg,
+ unsigned int start,
+ unsigned int len)
{
- return (lcd_hiu_read(_reg) >> (_start)) & ((1L << (_len)) - 1);
+ return (lcd_combo_dphy_read(reg) >> (start)) & ((1L << (len)) - 1);
}
-static inline void lcd_hiu_set_mask(unsigned int _reg, unsigned int _mask)
+static inline void lcd_combo_dphy_set_mask(unsigned int reg, unsigned int _mask)
{
- lcd_hiu_write(_reg, (lcd_hiu_read(_reg) | (_mask)));
+ lcd_combo_dphy_write(reg, (lcd_combo_dphy_read(reg) | (_mask)));
}
-static inline void lcd_hiu_clr_mask(unsigned int _reg, unsigned int _mask)
+static inline void lcd_combo_dphy_clr_mask(unsigned int reg, unsigned int _mask)
{
- lcd_hiu_write(_reg, (lcd_hiu_read(_reg) & (~(_mask))));
+ lcd_combo_dphy_write(reg, (lcd_combo_dphy_read(reg) & (~(_mask))));
}
-static inline unsigned int lcd_cbus_read(unsigned int _reg)
+static inline unsigned int lcd_clk_read(unsigned int reg)
{
- return (*(volatile unsigned int *)REG_ADDR_CBUS(_reg));
+ unsigned int val;
+
+ val = *(volatile unsigned int *)(REG_ADDR_HIU(reg));
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%08x\n", __func__, reg, val);
+
+ return val;
};
-static inline void lcd_cbus_write(unsigned int _reg, unsigned int _value)
+static inline void lcd_clk_write(unsigned int reg, unsigned int val)
{
- *(volatile unsigned int *)REG_ADDR_CBUS(_reg) = (_value);
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%08x\n", __func__, reg, val);
+ *(volatile unsigned int *)REG_ADDR_HIU(reg) = (val);
};
-static inline void lcd_cbus_setb(unsigned int _reg, unsigned int _value,
- unsigned int _start, unsigned int _len)
+static inline void lcd_clk_setb(unsigned int reg, unsigned int val,
+ unsigned int start, unsigned int len)
{
- lcd_cbus_write(_reg, ((lcd_cbus_read(_reg) &
- ~(((1L << (_len))-1) << (_start))) |
- (((_value)&((1L<<(_len))-1)) << (_start))));
+ lcd_clk_write(reg, ((lcd_clk_read(reg) &
+ ~(((1L << (len))-1) << (start))) |
+ (((val)&((1L<<(len))-1)) << (start))));
}
-static inline unsigned int lcd_cbus_getb(unsigned int _reg,
- unsigned int _start, unsigned int _len)
+static inline unsigned int lcd_clk_getb(unsigned int reg,
+ unsigned int start, unsigned int len)
{
- return (lcd_cbus_read(_reg) >> (_start)) & ((1L << (_len)) - 1);
+ return (lcd_clk_read(reg) >> (start)) & ((1L << (len)) - 1);
}
-static inline void lcd_cbus_set_mask(unsigned int _reg, unsigned int _mask)
+static inline void lcd_clk_set_mask(unsigned int reg, unsigned int _mask)
{
- lcd_cbus_write(_reg, (lcd_cbus_read(_reg) | (_mask)));
+ lcd_clk_write(reg, (lcd_clk_read(reg) | (_mask)));
}
-static inline void lcd_cbus_clr_mask(unsigned int _reg, unsigned int _mask)
+static inline void lcd_clk_clr_mask(unsigned int reg, unsigned int _mask)
{
- lcd_cbus_write(_reg, (lcd_cbus_read(_reg) & (~(_mask))));
+ lcd_clk_write(reg, (lcd_clk_read(reg) & (~(_mask))));
}
-static inline unsigned int lcd_vcbus_read(unsigned int _reg)
+static inline unsigned int lcd_ana_read(unsigned int reg)
{
- return (*(volatile unsigned int *)REG_ADDR_VCBUS(_reg));
+ unsigned int val;
+
+ val = *(volatile unsigned int *)(REG_ADDR_HIU(reg));
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%08x\n", __func__, reg, val);
+
+ return val;
};
-static inline void lcd_vcbus_write(unsigned int _reg, unsigned int _value)
+static inline void lcd_ana_write(unsigned int reg, unsigned int val)
{
- *(volatile unsigned int *)REG_ADDR_VCBUS(_reg) = (_value);
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%08x\n", __func__, reg, val);
+ *(volatile unsigned int *)REG_ADDR_HIU(reg) = (val);
};
-static inline void lcd_vcbus_setb(unsigned int _reg, unsigned int _value,
- unsigned int _start, unsigned int _len)
+static inline void lcd_ana_setb(unsigned int reg, unsigned int val,
+ unsigned int start, unsigned int len)
{
- lcd_vcbus_write(_reg, ((lcd_vcbus_read(_reg) &
- ~(((1L << (_len))-1) << (_start))) |
- (((_value)&((1L<<(_len))-1)) << (_start))));
+ lcd_ana_write(reg, ((lcd_ana_read(reg) &
+ ~(((1L << (len))-1) << (start))) |
+ (((val)&((1L<<(len))-1)) << (start))));
}
-static inline unsigned int lcd_vcbus_getb(unsigned int _reg,
- unsigned int _start, unsigned int _len)
+static inline unsigned int lcd_ana_getb(unsigned int reg,
+ unsigned int start, unsigned int len)
{
- return (lcd_vcbus_read(_reg) >> (_start)) & ((1L << (_len)) - 1);
+ return (lcd_ana_read(reg) >> (start)) & ((1L << (len)) - 1);
}
-static inline void lcd_vcbus_set_mask(unsigned int _reg, unsigned int _mask)
+static inline void lcd_ana_set_mask(unsigned int reg, unsigned int _mask)
{
- lcd_vcbus_write(_reg, (lcd_vcbus_read(_reg) | (_mask)));
+ lcd_ana_write(reg, (lcd_ana_read(reg) | (_mask)));
}
-static inline void lcd_vcbus_clr_mask(unsigned int _reg, unsigned int _mask)
+static inline void lcd_ana_clr_mask(unsigned int reg, unsigned int _mask)
{
- lcd_vcbus_write(_reg, (lcd_vcbus_read(_reg) & (~(_mask))));
+ lcd_ana_write(reg, (lcd_ana_read(reg) & (~(_mask))));
}
-static inline unsigned int lcd_aobus_read(unsigned int _reg)
+static inline unsigned int lcd_cbus_read(unsigned int reg)
{
- return (*(volatile unsigned int *)REG_ADDR_AOBUS(_reg));
+ unsigned int val;
+
+ val = (*(volatile unsigned int *)REG_ADDR_CBUS(reg));
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%08x\n", __func__, reg, val);
+
+ return val;
};
-static inline void lcd_aobus_write(unsigned int _reg, unsigned int _value)
+static inline void lcd_cbus_write(unsigned int reg, unsigned int val)
{
- *(volatile unsigned int *)REG_ADDR_AOBUS(_reg) = (_value);
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%08x\n", __func__, reg, val);
+ *(volatile unsigned int *)REG_ADDR_CBUS(reg) = (val);
};
-static inline void lcd_aobus_setb(unsigned int _reg, unsigned int _value,
- unsigned int _start, unsigned int _len)
+static inline void lcd_cbus_setb(unsigned int reg, unsigned int val,
+ unsigned int start, unsigned int len)
{
- lcd_aobus_write(_reg, ((lcd_aobus_read(_reg) &
- ~(((1L << (_len))-1) << (_start))) |
- (((_value)&((1L<<(_len))-1)) << (_start))));
+ lcd_cbus_write(reg, ((lcd_cbus_read(reg) &
+ ~(((1L << (len))-1) << (start))) |
+ (((val)&((1L<<(len))-1)) << (start))));
}
-static inline unsigned int lcd_aobus_getb(unsigned int _reg,
- unsigned int _start, unsigned int _len)
+static inline unsigned int lcd_cbus_getb(unsigned int reg,
+ unsigned int start, unsigned int len)
{
- return (lcd_aobus_read(_reg) & (((1L << (_len)) - 1) << (_start)));
+ return (lcd_cbus_read(reg) >> (start)) & ((1L << (len)) - 1);
}
-static inline unsigned int lcd_periphs_read(unsigned int _reg)
+static inline void lcd_cbus_set_mask(unsigned int reg, unsigned int _mask)
{
- return (*(volatile unsigned int *)REG_ADDR_PERIPHS(_reg));
+ lcd_cbus_write(reg, (lcd_cbus_read(reg) | (_mask)));
+}
+
+static inline void lcd_cbus_clr_mask(unsigned int reg, unsigned int _mask)
+{
+ lcd_cbus_write(reg, (lcd_cbus_read(reg) & (~(_mask))));
+}
+
+static inline unsigned int lcd_reset_read(unsigned int reg)
+{
+ unsigned int val;
+
+ val = (*(volatile unsigned int *)REG_ADDR_RESET(reg));
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%08x\n", __func__, reg, val);
+
+ return val;
};
-static inline void lcd_periphs_write(unsigned int _reg, unsigned int _value)
+static inline void lcd_reset_write(unsigned int reg, unsigned int val)
{
- *(volatile unsigned int *)REG_ADDR_PERIPHS(_reg) = (_value);
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%08x\n", __func__, reg, val);
+ *(volatile unsigned int *)REG_ADDR_RESET(reg) = (val);
};
-static inline void lcd_periphs_setb(unsigned int _reg, unsigned int _value,
- unsigned int _start, unsigned int _len)
+static inline void lcd_reset_setb(unsigned int reg, unsigned int val,
+ unsigned int start, unsigned int len)
{
- lcd_periphs_write(_reg, ((lcd_periphs_read(_reg) &
- ~(((1L << (_len))-1) << (_start))) |
- (((_value)&((1L<<(_len))-1)) << (_start))));
+ lcd_reset_write(reg, ((lcd_reset_read(reg) &
+ ~(((1L << (len))-1) << (start))) |
+ (((val)&((1L<<(len))-1)) << (start))));
}
-static inline unsigned int lcd_periphs_getb(unsigned int _reg,
- unsigned int _start, unsigned int _len)
+static inline unsigned int lcd_vcbus_read(unsigned int reg)
{
- return (lcd_periphs_read(_reg) & (((1L << (_len)) - 1) << (_start)));
+ unsigned int val;
+
+ val = (*(volatile unsigned int *)REG_ADDR_VCBUS(reg));
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%08x\n", __func__, reg, val);
+
+ return val;
+}
+
+static inline void lcd_vcbus_write(unsigned int reg, unsigned int val)
+{
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%08x\n", __func__, reg, val);
+ (*(volatile unsigned int *)REG_ADDR_VCBUS(reg)) = (val);
+}
+
+static inline void lcd_vcbus_setb(unsigned int reg, unsigned int val,
+ unsigned int start, unsigned int len)
+{
+ lcd_vcbus_write(reg, ((lcd_vcbus_read(reg) &
+ ~(((1L << (len))-1) << (start))) |
+ (((val)&((1L<<(len))-1)) << (start))));
+}
+
+static inline unsigned int lcd_vcbus_getb(unsigned int reg,
+ unsigned int start, unsigned int len)
+{
+ return (lcd_vcbus_read(reg) >> (start)) & ((1L << (len)) - 1);
+}
+
+static inline void lcd_vcbus_set_mask(unsigned int reg, unsigned int _mask)
+{
+ lcd_vcbus_write(reg, (lcd_vcbus_read(reg) | (_mask)));
+}
+
+static inline void lcd_vcbus_clr_mask(unsigned int reg, unsigned int _mask)
+{
+ lcd_vcbus_write(reg, (lcd_vcbus_read(reg) & (~(_mask))));
+}
+
+static inline unsigned int lcd_aobus_read(unsigned int reg)
+{
+ unsigned int val;
+
+ val = (*(volatile unsigned int *)REG_ADDR_AOBUS(reg));
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%08x\n", __func__, reg, val);
+
+ return val;
+};
+
+static inline void lcd_aobus_write(unsigned int reg, unsigned int val)
+{
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%08x\n", __func__, reg, val);
+ *(volatile unsigned int *)REG_ADDR_AOBUS(reg) = (val);
+};
+
+static inline void lcd_aobus_setb(unsigned int reg, unsigned int val,
+ unsigned int start, unsigned int len)
+{
+ lcd_aobus_write(reg, ((lcd_aobus_read(reg) &
+ ~(((1L << (len))-1) << (start))) |
+ (((val)&((1L<<(len))-1)) << (start))));
+}
+
+static inline unsigned int lcd_aobus_getb(unsigned int reg,
+ unsigned int start, unsigned int len)
+{
+ return (lcd_aobus_read(reg) & (((1L << (len)) - 1) << (start)));
+}
+
+static inline unsigned int lcd_periphs_read(unsigned int reg)
+{
+ unsigned int val;
+
+ val = (*(volatile unsigned int *)REG_ADDR_PERIPHS(reg));
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%08x\n", __func__, reg, val);
+
+ return val;
+};
+
+static inline void lcd_periphs_write(unsigned int reg, unsigned int val)
+{
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%08x\n", __func__, reg, val);
+ *(volatile unsigned int *)REG_ADDR_PERIPHS(reg) = (val);
+};
+
+static inline void lcd_periphs_setb(unsigned int reg, unsigned int val,
+ unsigned int start, unsigned int len)
+{
+ lcd_periphs_write(reg, ((lcd_periphs_read(reg) &
+ ~(((1L << (len))-1) << (start))) |
+ (((val)&((1L<<(len))-1)) << (start))));
+}
+
+static inline unsigned int lcd_periphs_getb(unsigned int reg,
+ unsigned int start, unsigned int len)
+{
+ return (lcd_periphs_read(reg) & (((1L << (len)) - 1) << (start)));
}
static inline void lcd_pinmux_set_mask(unsigned int n, unsigned int _mask)
{
- unsigned int _reg = PERIPHS_PIN_MUX_0;
+ unsigned int reg = PERIPHS_PIN_MUX_0;
- if (n > 15)
- return;
-
- _reg += (n << 2);
- lcd_periphs_write(_reg, (lcd_periphs_read(_reg) | (_mask)));
+ reg += (n << 2);
+ lcd_periphs_write(reg, (lcd_periphs_read(reg) | (_mask)));
}
static inline void lcd_pinmux_clr_mask(unsigned int n, unsigned int _mask)
{
- unsigned int _reg = PERIPHS_PIN_MUX_0;
+ unsigned int reg = PERIPHS_PIN_MUX_0;
- if (n > 15)
- return;
-
- _reg += (n << 2);
- lcd_periphs_write(_reg, (lcd_periphs_read(_reg) & (~(_mask))));
+ reg += (n << 2);
+ lcd_periphs_write(reg, (lcd_periphs_read(reg) & (~(_mask))));
}
-static inline unsigned int dsi_host_read(unsigned int _reg)
+static inline unsigned int dsi_host_read(int index, unsigned int reg)
{
- return *(volatile unsigned int *)(REG_ADDR_DSI_HOST(_reg));
+ unsigned long paddr;
+ unsigned int val;
+
+ if (index)
+ paddr = (REG_ADDR_DSI_B_HOST(reg));
+ else
+ paddr = (REG_ADDR_DSI_HOST(reg));
+ val = *(volatile unsigned int *)paddr;
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08lx]=0x%08x\n", __func__, paddr, val);
+
+ return val;
+}
+
+static inline void dsi_host_write(int index, unsigned int reg, unsigned int val)
+{
+ unsigned long paddr;
+
+ if (index)
+ paddr = REG_ADDR_DSI_B_HOST(reg);
+ else
+ paddr = REG_ADDR_DSI_HOST(reg);
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08lx]=0x%08x\n", __func__, paddr, val);
+ *(volatile unsigned int *)paddr = (val);
+}
+
+static inline void dsi_host_setb(int index, unsigned int reg, unsigned int val,
+ unsigned int start, unsigned int len)
+{
+ dsi_host_write(index, reg, ((dsi_host_read(index, reg) &
+ ~(((1L << (len)) - 1) << (start))) |
+ (((val) & ((1L << (len)) - 1)) << (start))));
+}
+
+static inline unsigned int dsi_host_getb(int index, unsigned int reg,
+ unsigned int start, unsigned int len)
+{
+ return (dsi_host_read(index, reg) >> (start)) & ((1L << (len)) - 1);
+}
+
+static inline void dsi_host_set_mask(int index, unsigned int reg, unsigned int _mask)
+{
+ dsi_host_write(index, reg, (dsi_host_read(index, reg) | (_mask)));
+}
+
+static inline void dsi_host_clr_mask(int index, unsigned int reg, unsigned int _mask)
+{
+ dsi_host_write(index, reg, (dsi_host_read(index, reg) & (~(_mask))));
+}
+
+static inline unsigned int dsi_phy_read(int index, unsigned int reg)
+{
+ unsigned long paddr;
+ unsigned int val;
+
+ if (index)
+ paddr = (REG_ADDR_DSI_B_PHY(reg));
+ else
+ paddr = (REG_ADDR_DSI_PHY(reg));
+ val = *(volatile unsigned int *)paddr;
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08lx]=0x%08x\n", __func__, paddr, val);
+
+ return val;
};
-static inline void dsi_host_write(unsigned int _reg, unsigned int _value)
+static inline void dsi_phy_write(int index, unsigned int reg, unsigned int val)
{
- *(volatile unsigned int *)REG_ADDR_DSI_HOST(_reg) = (_value);
+ unsigned long paddr;
+
+ if (index)
+ paddr = REG_ADDR_DSI_B_PHY(reg);
+ else
+ paddr = REG_ADDR_DSI_PHY(reg);
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08lx]=0x%08x\n", __func__, paddr, val);
+ *(volatile unsigned int *)paddr = (val);
};
-static inline void dsi_host_setb(unsigned int _reg, unsigned int _value,
- unsigned int _start, unsigned int _len)
+static inline void dsi_phy_setb(int index, unsigned int reg, unsigned int val,
+ unsigned int start, unsigned int len)
{
- dsi_host_write(_reg, ((dsi_host_read(_reg) &
- ~(((1L << (_len))-1) << (_start))) |
- (((_value)&((1L<<(_len))-1)) << (_start))));
+ dsi_phy_write(index, reg, ((dsi_phy_read(index, reg) &
+ ~(((1L << (len)) - 1) << (start))) |
+ (((val) & ((1L << (len)) - 1)) << (start))));
}
-static inline unsigned int dsi_host_getb(unsigned int _reg,
- unsigned int _start, unsigned int _len)
+static inline unsigned int dsi_phy_getb(int index, unsigned int reg,
+ unsigned int start, unsigned int len)
{
- return (dsi_host_read(_reg) >> (_start)) & ((1L << (_len)) - 1);
+ return (dsi_phy_read(index, reg) >> (start)) & ((1L << (len)) - 1);
}
-static inline void dsi_host_set_mask(unsigned int _reg, unsigned int _mask)
+static inline void dsi_phy_set_mask(int index, unsigned int reg, unsigned int _mask)
{
- dsi_host_write(_reg, (dsi_host_read(_reg) | (_mask)));
+ dsi_phy_write(index, reg, (dsi_phy_read(index, reg) | (_mask)));
}
-static inline void dsi_host_clr_mask(unsigned int _reg, unsigned int _mask)
+static inline void dsi_phy_clr_mask(int index, unsigned int reg, unsigned int _mask)
{
- dsi_host_write(_reg, (dsi_host_read(_reg) & (~(_mask))));
+ dsi_phy_write(index, reg, (dsi_phy_read(index, reg) & (~(_mask))));
}
-static inline unsigned int dsi_phy_read(unsigned int _reg)
+static inline unsigned int lcd_tcon_read(unsigned int reg)
{
- return *(volatile unsigned int *)(REG_ADDR_DSI_PHY(_reg));
+ unsigned int val;
+
+ val = *(volatile unsigned int *)(REG_ADDR_TCON_APB(reg));
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%08x\n", __func__, reg, val);
+
+ return val;
};
-static inline void dsi_phy_write(unsigned int _reg, unsigned int _value)
+static inline void lcd_tcon_write(unsigned int reg, unsigned int val)
{
- *(volatile unsigned int *)REG_ADDR_DSI_PHY(_reg) = (_value);
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%08x\n", __func__, reg, val);
+ *(volatile unsigned int *)REG_ADDR_TCON_APB(reg) = (val);
};
-static inline void dsi_phy_setb(unsigned int _reg, unsigned int _value,
- unsigned int _start, unsigned int _len)
+static inline void lcd_tcon_setb(unsigned int reg, unsigned int val,
+ unsigned int start, unsigned int len)
{
- dsi_phy_write(_reg, ((dsi_phy_read(_reg) &
- ~(((1L << (_len))-1) << (_start))) |
- (((_value)&((1L<<(_len))-1)) << (_start))));
+ lcd_tcon_write(reg, ((lcd_tcon_read(reg) &
+ ~(((1L << (len))-1) << (start))) |
+ (((val)&((1L<<(len))-1)) << (start))));
}
-static inline unsigned int dsi_phy_getb(unsigned int _reg,
- unsigned int _start, unsigned int _len)
+static inline unsigned int lcd_tcon_getb(unsigned int reg,
+ unsigned int start, unsigned int len)
{
- return (dsi_phy_read(_reg) >> (_start)) & ((1L << (_len)) - 1);
+ return (lcd_tcon_read(reg) >> (start)) & ((1L << (len)) - 1);
}
-static inline void dsi_phy_set_mask(unsigned int _reg, unsigned int _mask)
+static inline void lcd_tcon_set_mask(unsigned int reg, unsigned int _mask)
{
- dsi_phy_write(_reg, (dsi_phy_read(_reg) | (_mask)));
+ lcd_tcon_write(reg, (lcd_tcon_read(reg) | (_mask)));
}
-static inline void dsi_phy_clr_mask(unsigned int _reg, unsigned int _mask)
+static inline void lcd_tcon_clr_mask(unsigned int reg, unsigned int _mask)
{
- dsi_phy_write(_reg, (dsi_phy_read(_reg) & (~(_mask))));
+ lcd_tcon_write(reg, (lcd_tcon_read(reg) & (~(_mask))));
}
-static inline unsigned int lcd_tcon_read(unsigned int _reg)
+static inline void lcd_tcon_update_bits(unsigned int reg,
+ unsigned int mask,
+ unsigned int value)
{
- return *(volatile unsigned int *)(REG_ADDR_TCON_APB(_reg));
+ if (mask == 0xffffffff) {
+ lcd_tcon_write(reg, value);
+ } else {
+ lcd_tcon_write(reg, (lcd_tcon_read(reg) & (~(mask))) |
+ (value & mask));
+ }
+}
+
+static inline int lcd_tcon_check_bits(unsigned int reg,
+ unsigned int mask,
+ unsigned int value)
+{
+ unsigned int temp;
+
+ temp = lcd_tcon_read(reg) & mask;
+ if (value != temp)
+ return -1;
+
+ return 0;
+}
+
+static inline unsigned char lcd_tcon_read_byte(unsigned int reg)
+{
+ unsigned int val;
+
+ val = *(volatile unsigned char *)(REG_ADDR_TCON_APB_BYTE(reg));
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%02x\n", __func__, reg, val);
+
+ return (unsigned char)val;
};
-static inline void lcd_tcon_write(unsigned int _reg, unsigned int _value)
+static inline void lcd_tcon_write_byte(unsigned int reg, unsigned char val)
{
- *(volatile unsigned int *)REG_ADDR_TCON_APB(_reg) = (_value);
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [0x%08x]=0x%02x\n", __func__, reg, val);
+ *(volatile unsigned char *)REG_ADDR_TCON_APB_BYTE(reg) = (val);
};
-static inline void lcd_tcon_setb(unsigned int _reg, unsigned int _value,
- unsigned int _start, unsigned int _len)
+static inline void lcd_tcon_setb_byte(unsigned int reg, unsigned char val,
+ unsigned int start, unsigned int len)
{
- lcd_tcon_write(_reg, ((lcd_tcon_read(_reg) &
- ~(((1L << (_len))-1) << (_start))) |
- (((_value)&((1L<<(_len))-1)) << (_start))));
+ lcd_tcon_write_byte(reg, ((lcd_tcon_read_byte(reg) &
+ ~(((1L << (len))-1) << (start))) |
+ (((val)&((1L<<(len))-1)) << (start))));
}
-static inline unsigned int lcd_tcon_getb(unsigned int _reg,
- unsigned int _start, unsigned int _len)
+static inline unsigned char lcd_tcon_getb_byte(unsigned int reg,
+ unsigned int start,
+ unsigned int len)
{
- return (lcd_tcon_read(_reg) >> (_start)) & ((1L << (_len)) - 1);
+ return (lcd_tcon_read_byte(reg) >> (start)) & ((1L << (len)) - 1);
}
-static inline void lcd_tcon_set_mask(unsigned int _reg, unsigned int _mask)
+static inline void lcd_tcon_update_bits_byte(unsigned int reg,
+ unsigned char mask,
+ unsigned char value)
{
- lcd_tcon_write(_reg, (lcd_tcon_read(_reg) | (_mask)));
+ if (mask == 0xff) {
+ lcd_tcon_write_byte(reg, value);
+ } else {
+ lcd_tcon_write_byte(reg, (lcd_tcon_read_byte(reg) & (~(mask))) |
+ (value & mask));
+ }
}
-static inline void lcd_tcon_clr_mask(unsigned int _reg, unsigned int _mask)
+static inline int lcd_tcon_check_bits_byte(unsigned int reg,
+ unsigned char mask,
+ unsigned char value)
{
- lcd_tcon_write(_reg, (lcd_tcon_read(_reg) & (~(_mask))));
+ unsigned char temp;
+
+ temp = lcd_tcon_read_byte(reg) & mask;
+ if ((value & mask) != temp)
+ return -1;
+
+ return 0;
}
-static inline unsigned char lcd_tcon_read_byte(unsigned int _reg)
+static inline unsigned int dptx_reg_read(int index, unsigned int reg)
{
- return *(volatile unsigned char *)(REG_ADDR_TCON_APB_BYTE(_reg));
-};
+ unsigned long paddr;
+ unsigned int val;
-static inline void lcd_tcon_write_byte(unsigned int _reg, unsigned char _value)
-{
- *(volatile unsigned char *)REG_ADDR_TCON_APB_BYTE(_reg) = (_value);
-};
+ if (index)
+ paddr = EDPTX1_BASE + reg;
+ else
+ paddr = EDPTX0_BASE + reg;
+ val = *(volatile unsigned int *)paddr;
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [%d][0x%04x]=0x%08x\n", __func__, index, reg, val);
-static inline void lcd_tcon_setb_byte(unsigned int _reg, unsigned char _value,
- unsigned int _start, unsigned int _len)
-{
- lcd_tcon_write_byte(_reg, ((lcd_tcon_read_byte(_reg) &
- ~(((1L << (_len))-1) << (_start))) |
- (((_value)&((1L<<(_len))-1)) << (_start))));
+ return val;
}
-static inline unsigned char lcd_tcon_getb_byte(unsigned int _reg,
- unsigned int _start, unsigned int _len)
+static inline void dptx_reg_write(int index, unsigned int reg, unsigned int val)
{
- return (lcd_tcon_read_byte(_reg) >> (_start)) & ((1L << (_len)) - 1);
+ unsigned long paddr;
+
+ if (index)
+ paddr = EDPTX1_BASE + reg;
+ else
+ paddr = EDPTX0_BASE + reg;
+ *(volatile unsigned int *)paddr = (val);
+ if (lcd_debug_print_flag & LCD_DBG_PR_REG)
+ printf("%s: [%d][0x%04x]=0x%08x\n", __func__, index, reg, val);
+}
+
+static inline void dptx_reg_setb(int index, unsigned int reg,
+ unsigned int val, unsigned int start, unsigned int len)
+{
+ dptx_reg_write(index, reg,
+ ((dptx_reg_read(index, reg) & ~(((1L << (len)) - 1) << (start))) |
+ (((val) & ((1L << (len)) - 1)) << (start))));
+}
+
+static inline unsigned int dptx_reg_getb(int index, unsigned int reg,
+ unsigned int start, unsigned int len)
+{
+ return (dptx_reg_read(index, reg) >> (start)) & ((1L << (len)) - 1);
}
#endif
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/Kconfig b/drivers/amlogic/media/vout/lcd/lcd_tablet/Kconfig
index c89e206..a84171c 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_tablet/Kconfig
+++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/Kconfig
@@ -1,5 +1,5 @@
config AML_LCD_TABLET
bool "lcd_tablet output"
+ depends on AML_LCD
help
Support for lcd tablet mode output
-
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/Makefile b/drivers/amlogic/media/vout/lcd/lcd_tablet/Makefile
index c374e80..9dfaec0 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_tablet/Makefile
+++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/Makefile
@@ -1,2 +1,2 @@
-obj-$(CONFIG_AML_LCD_TABLET) += lcd_tablet.o lcd_drv.o mipi_dsi_util.o
+obj-$(CONFIG_AML_LCD_TABLET) += lcd_tablet.o lcd_drv.o mipi_dsi_util.o edp_tx.o
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/edp_tx.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/edp_tx.c
new file mode 100644
index 0000000..dfdca37
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/edp_tx.c
@@ -0,0 +1,444 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <linux/kernel.h>
+#ifdef CONFIG_SECURE_POWER_CONTROL
+#include <asm/arch/pwr_ctrl.h>
+#endif
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+#include "../lcd_reg.h"
+#include "../lcd_common.h"
+
+#define EDP_TX_AUX_REQ_TIMEOUT 1000
+#define EDP_TX_AUX_REQ_INTERVAL 1
+#define EDP_AUX_RETRY_CNT 5
+#define EDP_AUX_TIMEOUT 1000
+#define EDP_AUX_INTERVAL 200
+static int dptx_aux_write(int index, unsigned int addr, unsigned int len, unsigned char *buf)
+{
+ unsigned int data, i, state;
+ unsigned int retry_cnt = 0, timeout = 0;
+
+dptx_aux_write_retry:
+ timeout = 0;
+ while (timeout++ < EDP_TX_AUX_REQ_TIMEOUT) { /* wait REQUEST_IN_PROGRESS */
+ state = dptx_reg_getb(index, EDP_TX_AUX_STATE, 1, 1);
+ if (state == 0)
+ break;
+ udelay(EDP_TX_AUX_REQ_INTERVAL);
+ };
+
+ dptx_reg_write(index, EDP_TX_AUX_ADDRESS, addr);
+ for (i = 0; i < len; i++)
+ dptx_reg_write(index, EDP_TX_AUX_WRITE_FIFO, buf[i]);
+
+ dptx_reg_write(index, EDP_TX_AUX_COMMAND, (0x800 | ((len - 1) & 0xf)));
+
+ timeout = 0;
+ while (timeout++ < EDP_AUX_TIMEOUT) {
+ udelay(EDP_AUX_INTERVAL);
+ data = dptx_reg_read(index, EDP_TX_AUX_TRANSFER_STATUS);
+ if (data & (1 << 0)) {
+ state = dptx_reg_read(index, EDP_TX_AUX_REPLY_CODE);
+ if (state == 0)
+ return 0;
+ if (state == 1) {
+ LCDPR("[%d]: edp aux write addr 0x%x NACK!\n",
+ index, addr);
+ return -1;
+ }
+ if (state == 2) {
+ LCDPR("[%d]: edp aux write addr 0x%x Defer!\n",
+ index, addr);
+ }
+ break;
+ }
+
+ if (data & (1 << 3)) {
+ LCDPR("[%d]: edp aux write addr 0x%x Error!\n", index, addr);
+ break;
+ }
+ }
+
+ if (retry_cnt++ < EDP_AUX_RETRY_CNT) {
+ udelay(EDP_AUX_INTERVAL);
+ LCDPR("[%d]: edp aux write addr 0x%x timeout, retry %d\n",
+ index, addr, retry_cnt);
+ goto dptx_aux_write_retry;
+ }
+
+ LCDPR("[%d]: edp aux write addr 0x%x failed\n", index, addr);
+ return -1;
+}
+
+static int dptx_aux_read(int index, unsigned int addr, unsigned int len, unsigned char *buf)
+{
+ unsigned int data, i, state;
+ unsigned int retry_cnt = 0, timeout = 0;
+
+dptx_aux_read_retry:
+ timeout = 0;
+ while (timeout++ < EDP_TX_AUX_REQ_TIMEOUT) { /* wait REQUEST_IN_PROGRESS */
+ state = dptx_reg_getb(index, EDP_TX_AUX_STATE, 1, 1);
+ if (state == 0)
+ break;
+ udelay(EDP_TX_AUX_REQ_INTERVAL);
+ };
+
+ dptx_reg_write(index, EDP_TX_AUX_ADDRESS, addr);
+ dptx_reg_write(index, EDP_TX_AUX_COMMAND, (0x900 | ((len - 1) & 0xf)));
+
+ timeout = 0;
+ while (timeout++ < EDP_AUX_TIMEOUT) {
+ udelay(EDP_AUX_INTERVAL);
+ data = dptx_reg_read(index, EDP_TX_AUX_TRANSFER_STATUS);
+ if (data & (1 << 0)) {
+ state = dptx_reg_read(index, EDP_TX_AUX_REPLY_CODE);
+ if (state == 0)
+ goto dptx_aux_read_succeed;
+ if (state == 1) {
+ LCDPR("[%d]: edp aux read addr 0x%x NACK!\n",
+ index, addr);
+ return -1;
+ }
+ if (state == 2) {
+ LCDPR("[%d]: edp aux read addr 0x%x Defer!\n",
+ index, addr);
+ }
+ break;
+ }
+
+ if (data & (1 << 3)) {
+ LCDPR("[%d]: edp aux read addr 0x%x Error!\n", index, addr);
+ break;
+ }
+ }
+
+ if (retry_cnt++ < EDP_AUX_RETRY_CNT) {
+ udelay(EDP_AUX_INTERVAL);
+ LCDPR("[%d]: edp aux read addr 0x%x timeout, retry %d\n",
+ index, addr, retry_cnt);
+ goto dptx_aux_read_retry;
+ }
+
+ LCDPR("[%d]: edp aux read addr 0x%x failed\n", index, addr);
+ return -1;
+
+dptx_aux_read_succeed:
+ for (i = 0; i < len; i++)
+ buf[i] = (unsigned char)(dptx_reg_read(index, EDP_TX_AUX_REPLY_DATA));
+
+ return 0;
+}
+
+static void dptx_link_fast_training(int index)
+{
+ unsigned char p_data = 0;
+ int ret;
+
+ // disable scrambling
+ dptx_reg_write(index, EDP_TX_SCRAMBLING_DISABLE ,0x1);
+
+ // set training pattern 1
+ dptx_reg_write(index, EDP_TX_TRAINING_PATTERN_SET, 0x1);
+ p_data = 0x21;
+ ret = dptx_aux_write(index, EDP_DPCD_TRAINING_PATTERN_SET, 1, &p_data);
+ if (ret)
+ LCDERR("[%d]: edp training pattern 1 failed.....\n", index);
+ udelay(10);
+
+ // set training pattern 2
+ dptx_reg_write(index, EDP_TX_TRAINING_PATTERN_SET, 0x2);
+ p_data = 0x22;
+ ret = dptx_aux_write(index, EDP_DPCD_TRAINING_PATTERN_SET, 1, &p_data);
+ if (ret)
+ LCDERR("[%d]: edp training pattern 2 failed.....\n", index);
+ udelay(10);
+
+ // set training pattern 3
+ dptx_reg_write(index, EDP_TX_TRAINING_PATTERN_SET, 0x3);
+ p_data = 0x23;
+ ret = dptx_aux_write(index, EDP_DPCD_TRAINING_PATTERN_SET, 1, &p_data);
+ if (ret)
+ LCDERR("[%d]: edp training pattern 3 failed.....\n", index);
+ udelay(10);
+
+ // disable the training pattern
+ p_data = 0x20;
+ ret = dptx_aux_write(index, EDP_DPCD_TRAINING_PATTERN_SET, 1, &p_data);
+ if (ret)
+ LCDERR("[%d]: edp training pattern off failed.....\n", index);
+ dptx_reg_write(index, EDP_TX_TRAINING_PATTERN_SET, 0x0);
+}
+
+void dptx_dpcd_dump(struct aml_lcd_drv_s *pdrv)
+{
+ int index;
+ unsigned char p_data[12];
+ int ret, i;
+
+ index = pdrv->index;
+ if (index > 1) {
+ LCDERR("[%d]: %s: invalid drv_index\n", index, __func__);
+ return;
+ }
+
+ memset(p_data, 0, 12);
+ LCDPR("[%d]: edp DPCD link status:\n", index);
+ ret = dptx_aux_read(index, 0x100, 8, p_data);
+ if (ret == 0) {
+ for (i = 0; i < 8; i++)
+ printf("0x%04x: 0x%02x\n", (0x100 + i), p_data[i]);
+ printf("\n");
+ }
+
+ memset(p_data, 0, 12);
+ LCDPR("[%d]: edp DPCD training status:\n", index);
+ ret = dptx_aux_read(index, 0x200, 12, p_data);
+ if (ret == 0) {
+ for (i = 0; i < 12; i++)
+ printf("0x%04x: 0x%02x\n", (0x200 + i), p_data[i]);
+ printf("\n");
+ }
+}
+
+static void dptx_set_msa(int index, struct lcd_config_s *pconf)
+{
+ unsigned int hactive = pconf->basic.h_active;
+ unsigned int vactive = pconf->basic.v_active;
+ unsigned int htotal = pconf->basic.h_period;
+ unsigned int vtotal = pconf->basic.v_period;
+ unsigned int hsw = pconf->timing.hsync_width;
+ unsigned int hbp = pconf->timing.hsync_bp;
+ unsigned int vsw = pconf->timing.vsync_width;
+ unsigned int vbp = pconf->timing.vsync_bp;
+ unsigned int bpc = pconf->basic.lcd_bits; // bits per color
+ unsigned int data_per_lane, misc0_data, bit_depth, sync_mode;
+ unsigned int m_vid; //pclk/1000
+ unsigned int n_vid; //162000, 270000, 540000
+ unsigned int ppc = 1; // 1 pix per clock pix0 only
+ unsigned int cfmt = 0; // RGB
+
+ m_vid = pconf->timing.lcd_clk / 1000;
+ switch (pconf->control.edp_cfg.link_rate) {
+ case 1: /* 2.7G */
+ n_vid = 270000;
+ break;
+ case 0: /* 1.62G */
+ default:
+ n_vid = 162000;
+ break;
+ }
+ //6bit:0x0, 8bit:0x1, 10bit:0x2, 12bit:0x3
+ switch (pconf->basic.lcd_bits) {
+ case 6:
+ bit_depth = 0x0;
+ break;
+ case 8:
+ bit_depth = 0x1;
+ break;
+ case 10:
+ bit_depth = 0x2;
+ break;
+ default:
+ bit_depth = 0x7;
+ break;
+ }
+ sync_mode = pconf->control.edp_cfg.sync_clk_mode;
+ data_per_lane = ((hactive * bpc * 3) + 15) / 16 - 1;
+
+ //bit[0] sync mode (1=sync 0=async)
+ misc0_data = (cfmt << 1) | (sync_mode << 0);
+ misc0_data |= (bit_depth << 5);
+
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_HTOTAL, htotal);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_VTOTAL, vtotal);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_POLARITY, (0 << 1) | (0 << 0));
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_HSWIDTH, hsw);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_VSWIDTH, vsw);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_HRES, hactive);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_VRES, vactive);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_HSTART, (hsw + hbp));
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_VSTART, (vsw + vbp));
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_MISC0, misc0_data);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_MISC1, 0x00000000);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_M_VID, m_vid); //unit: 1kHz
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_N_VID, n_vid); //unit: 10kHz
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_TRANSFER_UNIT_SIZE, 32);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_DATA_COUNT_PER_LANE, data_per_lane);
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_USER_PIXEL_WIDTH, ppc);
+}
+
+static void dptx_reset(int index)
+{
+ unsigned int bit;
+
+ if (index)
+ bit = 18;
+ else
+ bit = 17;
+
+ lcd_reset_setb(RESETCTRL_RESET1_MASK, 0, bit, 1);
+ lcd_reset_setb(RESETCTRL_RESET1_LEVEL, 0, bit, 1);
+ udelay(1);
+ lcd_reset_setb(RESETCTRL_RESET1_LEVEL, 1, bit, 1);
+ udelay(1);
+}
+
+static void dptx_phy_reset(int index)
+{
+ unsigned int bit;
+
+ if (index)
+ bit = 20;
+ else
+ bit = 19;
+
+ lcd_reset_setb(RESETCTRL_RESET1_MASK, 0, bit, 1);
+ lcd_reset_setb(RESETCTRL_RESET1_LEVEL, 0, bit, 1);
+ udelay(1);
+ lcd_reset_setb(RESETCTRL_RESET1_LEVEL, 1, bit, 1);
+ udelay(1);
+}
+
+static int dptx_wait_phy_ready(int index)
+{
+ unsigned int data = 0;
+ unsigned int done = 100;
+
+ do {
+ data = dptx_reg_read(index, EDP_TX_PHY_STATUS);
+ if (done < 20) {
+ LCDPR("[%d]: dptx wait phy ready: reg_val=0x%x, wait_count=%u\n",
+ index, data, (100 - done));
+ }
+ done--;
+ udelay(100);
+ }while(((data & 0x7f) != 0x7f) && (done > 0));
+
+ if ((data & 0x7f) == 0x7f)
+ return 0;
+
+ LCDERR("[%d]: edp tx phy error!\n", index);
+ return -1;
+}
+
+#define EDP_HPD_TIMEOUT 1000
+static void edp_tx_init(struct aml_lcd_drv_s *pdrv)
+{
+ unsigned int hpd_state = 0;
+ unsigned char auxdata[2];
+ unsigned int offset;
+ int i, index, ret;
+
+ index = pdrv->index;
+ if (index > 1) {
+ LCDERR("[%d]: %s: invalid drv_index\n", index, __func__);
+ return;
+ }
+
+ offset = pdrv->data->offset_venc_data[pdrv->index];
+
+ dptx_phy_reset(index);
+ dptx_reset(index);
+ mdelay(2);
+
+ lcd_vcbus_write(ENCL_VIDEO_EN + offset, 0);
+
+ // Set Aux channel clk-div: 24MHz
+ dptx_reg_write(index, EDP_TX_AUX_CLOCK_DIVIDER, 24);
+
+ // Enable the transmitter
+ // remove the reset on the PHY
+ dptx_reg_write(index, EDP_TX_PHY_RESET, 0);
+ dptx_wait_phy_ready(index);
+ mdelay(2);
+ dptx_reg_write(index, EDP_TX_TRANSMITTER_OUTPUT_ENABLE, 0x1);
+
+ i = 0;
+ while (i++ < EDP_HPD_TIMEOUT) {
+ hpd_state = dptx_reg_getb(index, EDP_TX_AUX_STATE, 0, 1);
+ if (hpd_state)
+ break;
+ mdelay(2);
+ }
+ LCDPR("[%d]: edp HPD state: %d, i=%d\n", index, hpd_state, i);
+
+ // tx Link-rate and Lane_count
+ dptx_reg_write(index, EDP_TX_LINK_BW_SET, 0x0a); // Link-rate
+ dptx_reg_write(index, EDP_TX_LINK_COUNT_SET, 0x02); // Number of Lanes
+
+ // sink Link-rate and Lane_count
+ auxdata[0] = 0x0a; // 2.7GHz //EDP_DPCD_LINK_BANDWIDTH_SET
+ auxdata[1] = 2; //EDP_DPCD_LANE_COUNT_SET
+ ret = dptx_aux_write(index, EDP_DPCD_LINK_BANDWIDTH_SET, 2, auxdata);
+ if (ret)
+ LCDERR("[%d]: edp sink set lane rate & count failed.....\n", index);
+
+ // Power up link
+ auxdata[0] = 0x1;
+ ret = dptx_aux_write(index, EDP_DPCD_SET_POWER, 1, auxdata);
+ if (ret)
+ LCDERR("[%d]: edp sink power up link failed.....\n", index);
+
+ dptx_link_fast_training(index);
+ //dptx_dpcd_dump(pdrv);
+
+ dptx_set_msa(index, &pdrv->config);
+ lcd_vcbus_write(ENCL_VIDEO_EN + offset, 1);
+
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_ENABLE, 0x1);
+ LCDPR("[%d]: edp enable main stream video\n", index);
+}
+
+static void edp_tx_disable(struct aml_lcd_drv_s *pdrv)
+{
+ unsigned char auxdata;
+ int index, ret;
+
+ index = pdrv->index;
+ if (index > 1) {
+ LCDERR("[%d]: %s: invalid drv_index\n", index, __func__);
+ return;
+ }
+
+ // Power down link
+ auxdata = 0x2;
+ ret = dptx_aux_write(index, EDP_DPCD_SET_POWER, 1, &auxdata);
+ if (ret)
+ LCDERR("[%d]: edp sink power down link failed.....\n", index);
+
+ dptx_reg_write(index, EDP_TX_MAIN_STREAM_ENABLE, 0x0);
+ LCDPR("[%d]: edp disable main stream video\n", index);
+
+ // disable the transmitter
+ dptx_reg_write(index, EDP_TX_TRANSMITTER_OUTPUT_ENABLE, 0x0);
+}
+
+static void edp_power_init(int index)
+{
+#ifdef CONFIG_SECURE_POWER_CONTROL
+//#define PM_EDP0 48
+//#define PM_EDP1 49
+//#define PM_MIPI_DSI1 50
+//#define PM_MIPI_DSI0 41
+ if (index)
+ pwr_ctrl_psci_smc(PM_EDP1, 1);
+ else
+ pwr_ctrl_psci_smc(PM_EDP0, 1);
+ LCDPR("[%d]: edp power domain on\n", index);
+#endif
+}
+
+void edp_tx_ctrl(struct aml_lcd_drv_s *pdrv, int flag)
+{
+ if (flag) {
+ edp_power_init(pdrv->index);
+ edp_tx_init(pdrv);
+ } else {
+ edp_tx_disable(pdrv);
+ }
+}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c
index b4569b3..5a242a6 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_drv.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -28,10 +13,9 @@
#include "lcd_tablet.h"
#include "mipi_dsi_util.h"
-
static int lcd_type_supported(struct lcd_config_s *pconf)
{
- int lcd_type = pconf->lcd_basic.lcd_type;
+ int lcd_type = pconf->basic.lcd_type;
int ret = -1;
switch (lcd_type) {
@@ -39,6 +23,7 @@
case LCD_LVDS:
case LCD_VBYONE:
case LCD_MIPI:
+ case LCD_EDP:
ret = 0;
break;
default:
@@ -49,377 +34,238 @@
return ret;
}
-static void lcd_mipi_phy_set(struct lcd_config_s *pconf, int status)
+static void lcd_ttl_control_set(struct aml_lcd_drv_s *pdrv)
{
- unsigned int phy_reg, phy_bit, phy_width;
- unsigned int lane_cnt;
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
-
- if (status) {
- switch (lcd_drv->chip_type) {
- case LCD_CHIP_G12A:
- case LCD_CHIP_G12B:
- case LCD_CHIP_SM1:
- /* HHI_MIPI_CNTL0 */
- /* DIF_REF_CTL1:31-16bit, DIF_REF_CTL0:15-0bit */
- lcd_hiu_write(HHI_MIPI_CNTL0, (0xa487 << 16) | (0x8 << 0));
-
- /* HHI_MIPI_CNTL1 */
- /* DIF_REF_CTL2:15-0bit; bandgap bit16 */
- lcd_hiu_write(HHI_MIPI_CNTL1, (0x1 << 16) | (0x002e << 0));
-
- /* HHI_MIPI_CNTL2 */
- /* DIF_TX_CTL1:31-16bit, DIF_TX_CTL0:15-0bit */
- lcd_hiu_write(HHI_MIPI_CNTL2, (0x2680 << 16) | (0x45a << 0));
- break;
- default:
- break;
- }
-
- phy_reg = HHI_MIPI_CNTL2;
- phy_bit = MIPI_PHY_LANE_BIT;
- phy_width = MIPI_PHY_LANE_WIDTH;
- switch (pconf->lcd_control.mipi_config->lane_num) {
- case 1:
- lane_cnt = DSI_LANE_COUNT_1;
- break;
- case 2:
- lane_cnt = DSI_LANE_COUNT_2;
- break;
- case 3:
- lane_cnt = DSI_LANE_COUNT_3;
- break;
- case 4:
- lane_cnt = DSI_LANE_COUNT_4;
- break;
- default:
- lane_cnt = 0;
- break;
- }
- lcd_hiu_setb(phy_reg, lane_cnt, phy_bit, phy_width);
- } else {
- switch (lcd_drv->chip_type) {
- case LCD_CHIP_G12A:
- case LCD_CHIP_G12B:
- case LCD_CHIP_SM1:
- lcd_hiu_write(HHI_MIPI_CNTL0, 0);
- lcd_hiu_write(HHI_MIPI_CNTL1, 0);
- lcd_hiu_write(HHI_MIPI_CNTL2, 0);
- break;
- default:
- break;
- }
- }
-}
-
-static void lcd_lvds_phy_set(struct lcd_config_s *pconf, int status)
-{
- unsigned int vswing, preem, clk_vswing, clk_preem, channel_on;
- unsigned int data32;
-
- if (lcd_debug_print_flag)
- LCDPR("%s: %d\n", __func__, status);
-
- if (status) {
- vswing = pconf->lcd_control.lvds_config->phy_vswing;
- preem = pconf->lcd_control.lvds_config->phy_preem;
- clk_vswing = pconf->lcd_control.lvds_config->phy_clk_vswing;
- clk_preem = pconf->lcd_control.lvds_config->phy_clk_preem;
- if (vswing > 7) {
- LCDERR("%s: wrong vswing_level=0x%x, use default\n",
- __func__, vswing);
- vswing = LVDS_PHY_VSWING_DFT;
- }
- channel_on = lcd_lvds_channel_on_value(pconf);
-
- if (preem > 7) {
- LCDERR("%s: wrong preemphasis_level=0x%x, use default\n",
- __func__, preem);
- preem = LVDS_PHY_PREEM_DFT;
- }
- if (clk_vswing > 3) {
- LCDERR("%s: wrong clk_vswing_level=0x%x, use default\n",
- __func__, clk_vswing);
- clk_vswing = LVDS_PHY_CLK_VSWING_DFT;
- }
- if (clk_preem > 7) {
- LCDERR("%s: wrong clk_preem_level=0x%x, use default\n",
- __func__, clk_preem);
- clk_preem = LVDS_PHY_CLK_PREEM_DFT;
- }
-
- data32 = LVDS_PHY_CNTL1_G9TV |
- (vswing << 26) | (preem << 0);
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
- /*lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x6c6cca80);*/
- data32 = LVDS_PHY_CNTL2_G9TV;
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
- data32 = LVDS_PHY_CNTL3_G9TV |
- (channel_on << 16) | /* DIF_TX_CTL5 */
- (clk_vswing << 8) | (clk_preem << 5); /* DIF_TX_CTL4 */
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
- /*lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0fff0800);*/
- } else {
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0);
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0);
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0);
- }
-}
-
-static void lcd_vbyone_phy_set(struct lcd_config_s *pconf, int status)
-{
- unsigned int vswing, preem, ext_pullup;
- unsigned int data32;
- unsigned int rinner_table[] = {0xa, 0xa, 0x6, 0x4};
-
- if (lcd_debug_print_flag)
- LCDPR("%s: %d\n", __func__, status);
-
- if (status) {
- ext_pullup = (pconf->lcd_control.vbyone_config->phy_vswing >> 4) & 0x3;
- vswing = pconf->lcd_control.vbyone_config->phy_vswing & 0xf;
- preem = pconf->lcd_control.vbyone_config->phy_preem;
- if (vswing > 7) {
- LCDERR("%s: wrong vswing_level=0x%x, use default\n",
- __func__, vswing);
- vswing = VX1_PHY_VSWING_DFT;
- }
- if (preem > 7) {
- LCDERR("%s: wrong preemphasis_level=0x%x, use default\n",
- __func__, preem);
- preem = VX1_PHY_PREEM_DFT;
- }
- if (ext_pullup)
- data32 = VX1_PHY_CNTL1_G9TV_PULLUP | (vswing << 3);
- else
- data32 = VX1_PHY_CNTL1_G9TV | (vswing << 3);
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
- data32 = VX1_PHY_CNTL2_G9TV | (preem << 20) |
- (rinner_table[ext_pullup] << 8);
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
- data32 = VX1_PHY_CNTL3_G9TV;
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
- } else {
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0);
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0);
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0);
- }
-}
-
-#define STV2_SEL 5
-#define STV1_SEL 4
-static void lcd_encl_tcon_set(struct lcd_config_s *pconf)
-{
- struct lcd_timing_s *tcon_adr = &pconf->lcd_timing;
-
- lcd_vcbus_write(L_RGB_BASE_ADDR, 0);
- lcd_vcbus_write(L_RGB_COEFF_ADDR, 0x400);
-
- switch (pconf->lcd_basic.lcd_bits) {
- case 6:
- lcd_vcbus_write(L_DITH_CNTL_ADDR, 0x600);
- break;
- case 8:
- lcd_vcbus_write(L_DITH_CNTL_ADDR, 0x400);
- break;
- case 10:
- default:
- lcd_vcbus_write(L_DITH_CNTL_ADDR, 0x0);
- break;
- }
-
- switch (pconf->lcd_basic.lcd_type) {
- case LCD_LVDS:
- lcd_vcbus_setb(L_POL_CNTL_ADDR, 1, 0, 1);
- if (pconf->lcd_timing.vsync_pol)
- lcd_vcbus_setb(L_POL_CNTL_ADDR, 1, 1, 1);
- break;
- case LCD_VBYONE:
- if (pconf->lcd_timing.hsync_pol)
- lcd_vcbus_setb(L_POL_CNTL_ADDR, 1, 0, 1);
- if (pconf->lcd_timing.vsync_pol)
- lcd_vcbus_setb(L_POL_CNTL_ADDR, 1, 1, 1);
- break;
- case LCD_MIPI:
- //lcd_vcbus_setb(L_POL_CNTL_ADDR, 0x3, 0, 2);
- /*lcd_vcbus_write(L_POL_CNTL_ADDR, (lcd_vcbus_read(L_POL_CNTL_ADDR) | ((0 << 2) | (vs_pol_adj << 1) | (hs_pol_adj << 0))));*/
- /*lcd_vcbus_write(L_POL_CNTL_ADDR, (lcd_vcbus_read(L_POL_CNTL_ADDR) | ((1 << LCD_TCON_DE_SEL) | (1 << LCD_TCON_VS_SEL) | (1 << LCD_TCON_HS_SEL))));*/
- break;
- default:
- break;
- }
-
- /* DE signal for TTL m8,m8m2 */
- lcd_vcbus_write(L_OEH_HS_ADDR, tcon_adr->de_hs_addr);
- lcd_vcbus_write(L_OEH_HE_ADDR, tcon_adr->de_he_addr);
- lcd_vcbus_write(L_OEH_VS_ADDR, tcon_adr->de_vs_addr);
- lcd_vcbus_write(L_OEH_VE_ADDR, tcon_adr->de_ve_addr);
- /* DE signal for TTL m8b */
- lcd_vcbus_write(L_OEV1_HS_ADDR, tcon_adr->de_hs_addr);
- lcd_vcbus_write(L_OEV1_HE_ADDR, tcon_adr->de_he_addr);
- lcd_vcbus_write(L_OEV1_VS_ADDR, tcon_adr->de_vs_addr);
- lcd_vcbus_write(L_OEV1_VE_ADDR, tcon_adr->de_ve_addr);
-
- /* Hsync signal for TTL m8,m8m2 */
- if (tcon_adr->hsync_pol == 0) {
- lcd_vcbus_write(L_STH1_HS_ADDR, tcon_adr->hs_he_addr);
- lcd_vcbus_write(L_STH1_HE_ADDR, tcon_adr->hs_hs_addr);
- } else {
- lcd_vcbus_write(L_STH1_HS_ADDR, tcon_adr->hs_hs_addr);
- lcd_vcbus_write(L_STH1_HE_ADDR, tcon_adr->hs_he_addr);
- }
- lcd_vcbus_write(L_STH1_VS_ADDR, tcon_adr->hs_vs_addr);
- lcd_vcbus_write(L_STH1_VE_ADDR, tcon_adr->hs_ve_addr);
-
- /* Vsync signal for TTL m8,m8m2 */
- lcd_vcbus_write(L_STV1_HS_ADDR, tcon_adr->vs_hs_addr);
- lcd_vcbus_write(L_STV1_HE_ADDR, tcon_adr->vs_he_addr);
- if (tcon_adr->vsync_pol == 0) {
- lcd_vcbus_write(L_STV1_VS_ADDR, tcon_adr->vs_ve_addr);
- lcd_vcbus_write(L_STV1_VE_ADDR, tcon_adr->vs_vs_addr);
- } else {
- lcd_vcbus_write(L_STV1_VS_ADDR, tcon_adr->vs_vs_addr);
- lcd_vcbus_write(L_STV1_VE_ADDR, tcon_adr->vs_ve_addr);
- }
-
- /* DE signal */
- lcd_vcbus_write(L_DE_HS_ADDR, tcon_adr->de_hs_addr);
- lcd_vcbus_write(L_DE_HE_ADDR, tcon_adr->de_he_addr);
- lcd_vcbus_write(L_DE_VS_ADDR, tcon_adr->de_vs_addr);
- lcd_vcbus_write(L_DE_VE_ADDR, tcon_adr->de_ve_addr);
-
- /* Hsync signal */
- lcd_vcbus_write(L_HSYNC_HS_ADDR, tcon_adr->hs_hs_addr);
- lcd_vcbus_write(L_HSYNC_HE_ADDR, tcon_adr->hs_he_addr);
- lcd_vcbus_write(L_HSYNC_VS_ADDR, tcon_adr->hs_vs_addr);
- lcd_vcbus_write(L_HSYNC_VE_ADDR, tcon_adr->hs_ve_addr);
-
- /* Vsync signal */
- lcd_vcbus_write(L_VSYNC_HS_ADDR, tcon_adr->vs_hs_addr);
- lcd_vcbus_write(L_VSYNC_HE_ADDR, tcon_adr->vs_he_addr);
- lcd_vcbus_write(L_VSYNC_VS_ADDR, tcon_adr->vs_vs_addr);
- lcd_vcbus_write(L_VSYNC_VE_ADDR, tcon_adr->vs_ve_addr);
-
- lcd_vcbus_write(L_INV_CNT_ADDR, 0);
- lcd_vcbus_write(L_TCON_MISC_SEL_ADDR, ((1 << STV1_SEL) | (1 << STV2_SEL)));
-
- lcd_vcbus_write(VPP_MISC, lcd_vcbus_read(VPP_MISC) & ~(VPP_OUT_SATURATE));
-}
-
-static void lcd_venc_set(struct lcd_config_s *pconf)
-{
- unsigned int h_active, v_active;
- unsigned int video_on_pixel, video_on_line;
-
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
-
- h_active = pconf->lcd_basic.h_active;
- v_active = pconf->lcd_basic.v_active;
- video_on_pixel = pconf->lcd_timing.video_on_pixel;
- video_on_line = pconf->lcd_timing.video_on_line;
-
- lcd_vcbus_write(ENCL_VIDEO_EN, 0);
-
- /* viu1 select encl | viu2 select encl */
- lcd_vcbus_write(VPU_VIU_VENC_MUX_CTRL, (0 << 0) | (0 << 2));
- lcd_vcbus_write(ENCL_VIDEO_MODE, 0x8000); /* bit[15] shadown en */
- lcd_vcbus_write(ENCL_VIDEO_MODE_ADV, 0x0418); /* Sampling rate: 1 */
-
- lcd_vcbus_write(ENCL_VIDEO_FILT_CTRL, 0x1000); /* bypass filter */
- lcd_vcbus_write(ENCL_VIDEO_MAX_PXCNT, pconf->lcd_basic.h_period - 1);
- lcd_vcbus_write(ENCL_VIDEO_MAX_LNCNT, pconf->lcd_basic.v_period - 1);
- lcd_vcbus_write(ENCL_VIDEO_HAVON_BEGIN, video_on_pixel);
- lcd_vcbus_write(ENCL_VIDEO_HAVON_END, h_active - 1 + video_on_pixel);
- lcd_vcbus_write(ENCL_VIDEO_VAVON_BLINE, video_on_line);
- lcd_vcbus_write(ENCL_VIDEO_VAVON_ELINE, v_active - 1 + video_on_line);
-
- lcd_vcbus_write(ENCL_VIDEO_HSO_BEGIN, pconf->lcd_timing.hs_hs_addr);
- lcd_vcbus_write(ENCL_VIDEO_HSO_END, pconf->lcd_timing.hs_he_addr);
- lcd_vcbus_write(ENCL_VIDEO_VSO_BEGIN, pconf->lcd_timing.vs_hs_addr);
- lcd_vcbus_write(ENCL_VIDEO_VSO_END, pconf->lcd_timing.vs_he_addr);
- lcd_vcbus_write(ENCL_VIDEO_VSO_BLINE, pconf->lcd_timing.vs_vs_addr);
- lcd_vcbus_write(ENCL_VIDEO_VSO_ELINE, pconf->lcd_timing.vs_ve_addr);
- lcd_vcbus_write(ENCL_VIDEO_RGBIN_CTRL, 3);
-
- /* default black pattern */
- lcd_vcbus_write(ENCL_TST_MDSEL, 0);
- lcd_vcbus_write(ENCL_TST_Y, 0);
- lcd_vcbus_write(ENCL_TST_CB, 0);
- lcd_vcbus_write(ENCL_TST_CR, 0);
- lcd_vcbus_write(ENCL_TST_EN, 1);
- lcd_vcbus_setb(ENCL_VIDEO_MODE_ADV, 0, 3, 1);
-
- lcd_vcbus_write(ENCL_VIDEO_EN, 1);
-}
-
-static void lcd_ttl_control_set(struct lcd_config_s *pconf)
-{
+ struct lcd_config_s *pconf = &pdrv->config;
unsigned int clk_pol, rb_swap, bit_swap;
- clk_pol = pconf->lcd_control.ttl_config->clk_pol;
- rb_swap = (pconf->lcd_control.ttl_config->swap_ctrl >> 1) & 1;
- bit_swap = (pconf->lcd_control.ttl_config->swap_ctrl >> 0) & 1;
+ clk_pol = pconf->control.ttl_cfg.clk_pol;
+ rb_swap = (pconf->control.ttl_cfg.swap_ctrl >> 1) & 1;
+ bit_swap = (pconf->control.ttl_cfg.swap_ctrl >> 0) & 1;
lcd_vcbus_setb(L_POL_CNTL_ADDR, clk_pol, 6, 1);
lcd_vcbus_setb(L_DUAL_PORT_CNTL_ADDR, rb_swap, 1, 1);
lcd_vcbus_setb(L_DUAL_PORT_CNTL_ADDR, bit_swap, 0, 1);
}
-static void lcd_lvds_clk_util_set(struct lcd_config_s *pconf)
+static void lcd_mipi_control_set(struct aml_lcd_drv_s *pdrv)
{
- unsigned int phy_div;
+ unsigned int bit_lane_sel;
- if (pconf->lcd_control.lvds_config->dual_port)
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
+
+ if (pdrv->data->chip_type == LCD_CHIP_T7) {
+ switch (pdrv->index) {
+ case 0:
+ bit_lane_sel = 0;
+ break;
+ case 1:
+ bit_lane_sel = 16;
+ break;
+ default:
+ LCDERR("[%d]: %s: invalid drv_index\n",
+ pdrv->index, __func__);
+ return;
+ }
+ // sel dphy lane
+ lcd_combo_dphy_setb(COMBO_DPHY_CNTL1, 0x0, bit_lane_sel, 10);
+ }
+
+ mipi_dsi_tx_ctrl(pdrv, 1);
+}
+
+static void lcd_mipi_disable(struct aml_lcd_drv_s *pdrv)
+{
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
+
+ mipi_dsi_tx_ctrl(pdrv, 0);
+}
+
+static void lcd_edp_control_set(struct aml_lcd_drv_s *pdrv)
+{
+ unsigned int reg_dphy_tx_ctrl0, reg_dphy_tx_ctrl1;
+ unsigned int bit_data_in_lvds, bit_data_in_edp, bit_lane_sel;
+
+ switch (pdrv->index) {
+ case 0:
+ reg_dphy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0;
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1;
+ bit_data_in_lvds = 0;
+ bit_data_in_edp = 1;
+ bit_lane_sel = 0;
+ break;
+ case 1:
+ reg_dphy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL0;
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL1;
+ bit_data_in_lvds = 2;
+ bit_data_in_edp = 3;
+ bit_lane_sel = 16;
+ break;
+ default:
+ LCDERR("[%d]: %s: invalid drv_index\n", pdrv->index, __func__);
+ return;
+ }
+
+ // sel dphy data_in
+ lcd_combo_dphy_setb(COMBO_DPHY_CNTL0, 0, bit_data_in_lvds, 1);
+ lcd_combo_dphy_setb(COMBO_DPHY_CNTL0, 1, bit_data_in_edp, 1);
+ // sel dphy lane
+ lcd_combo_dphy_setb(COMBO_DPHY_CNTL1, 0x155, bit_lane_sel, 10);
+
+ // sel edp fifo clkdiv 20, enable lane
+ lcd_combo_dphy_write(reg_dphy_tx_ctrl0, ((0x4 << 5) | (0x1f << 16)));
+
+ // fifo enable
+ lcd_combo_dphy_setb(reg_dphy_tx_ctrl1, 1, 6, 10);
+ // fifo wr enable
+ lcd_combo_dphy_setb(reg_dphy_tx_ctrl1, 1, 7, 10);
+
+ edp_tx_ctrl(pdrv, 1);
+}
+
+static void lcd_edp_disable(struct aml_lcd_drv_s *pdrv)
+{
+ unsigned int reg_dphy_tx_ctrl0, reg_dphy_tx_ctrl1;
+
+ switch (pdrv->index) {
+ case 0:
+ reg_dphy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0;
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1;
+ break;
+ case 1:
+ reg_dphy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL0;
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL1;
+ break;
+ default:
+ LCDERR("[%d]: %s: invalid drv_index\n", pdrv->index, __func__);
+ return;
+ }
+
+ edp_tx_ctrl(pdrv, 0);
+
+ // fifo wr disable
+ lcd_combo_dphy_setb(reg_dphy_tx_ctrl1, 0, 7, 10);
+ // fifo disable
+ lcd_combo_dphy_setb(reg_dphy_tx_ctrl1, 0, 6, 10);
+ // lane disable
+ lcd_combo_dphy_setb(reg_dphy_tx_ctrl0, 0, 16, 8);
+}
+
+static void lcd_lvds_clk_util_set(struct aml_lcd_drv_s *pdrv)
+{
+ unsigned int reg_phy_tx_ctrl0, reg_phy_tx_ctrl1;
+ unsigned int bit_data_in_lvds, bit_data_in_edp, bit_lane_sel;
+ unsigned int phy_div, val_lane_sel, len_lane_sel;
+
+ if (pdrv->config.control.lvds_cfg.dual_port)
phy_div = 2;
else
phy_div = 1;
- /* set fifo_clk_sel: div 7 */
- lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL0, (1 << 6));
- /* set cntl_ser_en: 8-channel to 1 */
- lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12);
+ if (pdrv->data->chip_type == LCD_CHIP_T7) {
+ switch (pdrv->index) {
+ case 0:
+ reg_phy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0;
+ reg_phy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1;
+ bit_data_in_lvds = 0;
+ bit_data_in_edp = 1;
+ bit_lane_sel = 0;
+ val_lane_sel = 0x155;
+ len_lane_sel = 10;
+ break;
+ case 1:
+ reg_phy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL0;
+ reg_phy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL1;
+ bit_data_in_lvds = 2;
+ bit_data_in_edp = 3;
+ bit_lane_sel = 10;
+ val_lane_sel = 0x155;
+ len_lane_sel = 10;
+ break;
+ case 2:
+ reg_phy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL0;
+ reg_phy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL1;
+ bit_data_in_lvds = 4;
+ bit_data_in_edp = 0xff;
+ if (pdrv->config.control.lvds_cfg.dual_port) {
+ bit_lane_sel = 10;
+ val_lane_sel = 0xaaaaa;
+ len_lane_sel = 20;
+ } else {
+ bit_lane_sel = 20;
+ val_lane_sel = 0x2aa;
+ len_lane_sel = 10;
+ }
+ break;
+ default:
+ LCDERR("[%d]: %s: invalid drv_index\n",
+ pdrv->index, __func__);
+ return;
+ }
- /* decoupling fifo enable, gated clock enable */
- lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL1,
- (1 << 30) | ((phy_div - 1) << 25) | (1 << 24));
- /* decoupling fifo write enable after fifo enable */
- lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL1, 1, 31, 1);
+ // sel dphy data_in
+ if (bit_data_in_edp < 0xff)
+ lcd_combo_dphy_setb(COMBO_DPHY_CNTL0, 0, bit_data_in_edp, 1);
+ lcd_combo_dphy_setb(COMBO_DPHY_CNTL0, 1, bit_data_in_lvds, 1);
+ // sel dphy lane
+ lcd_combo_dphy_setb(COMBO_DPHY_CNTL1, val_lane_sel,
+ bit_lane_sel, len_lane_sel);
+
+ /* set fifo_clk_sel: div 7 */
+ lcd_combo_dphy_write(reg_phy_tx_ctrl0, (1 << 5));
+ /* set cntl_ser_en: 8-channel */
+ lcd_combo_dphy_setb(reg_phy_tx_ctrl0, 0x3ff, 16, 10);
+
+ /* decoupling fifo enable, gated clock enable */
+ lcd_combo_dphy_write(reg_phy_tx_ctrl1, (1 << 6) | (1 << 0));
+ /* decoupling fifo write enable after fifo enable */
+ lcd_combo_dphy_setb(reg_phy_tx_ctrl1, 1, 7, 1);
+ } else {
+ /* set fifo_clk_sel: div 7 */
+ lcd_ana_write(HHI_LVDS_TX_PHY_CNTL0, (1 << 6));
+ /* set cntl_ser_en: 8-channel to 1 */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12);
+ /* pn swap */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL0, 1, 2, 1);
+
+ /* decoupling fifo enable, gated clock enable */
+ lcd_ana_write(HHI_LVDS_TX_PHY_CNTL1,
+ (1 << 30) | ((phy_div - 1) << 25) | (1 << 24));
+ /* decoupling fifo write enable after fifo enable */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL1, 1, 31, 1);
+ }
}
-static void lcd_lvds_control_set(struct lcd_config_s *pconf)
+static void lcd_lvds_control_set(struct aml_lcd_drv_s *pdrv)
{
- unsigned int bit_num = 1;
- unsigned int pn_swap, port_swap, lane_reverse;
- unsigned int dual_port, fifo_mode;
- unsigned int lvds_repack = 1;
+ unsigned int bit_num, pn_swap, port_swap, lane_reverse;
+ unsigned int dual_port, fifo_mode, lvds_repack;
+ unsigned int offset;
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
- lcd_lvds_clk_util_set(pconf);
+ lcd_lvds_clk_util_set(pdrv);
- lvds_repack = (pconf->lcd_control.lvds_config->lvds_repack) & 0x3;
- pn_swap = (pconf->lcd_control.lvds_config->pn_swap) & 0x1;
- dual_port = (pconf->lcd_control.lvds_config->dual_port) & 0x1;
- port_swap = (pconf->lcd_control.lvds_config->port_swap) & 0x1;
- lane_reverse = (pconf->lcd_control.lvds_config->lane_reverse) & 0x1;
+ offset = pdrv->data->offset_venc_if[pdrv->index];
+ lvds_repack = (pdrv->config.control.lvds_cfg.lvds_repack) & 0x3;
+ pn_swap = (pdrv->config.control.lvds_cfg.pn_swap) & 0x1;
+ dual_port = (pdrv->config.control.lvds_cfg.dual_port) & 0x1;
+ port_swap = (pdrv->config.control.lvds_cfg.port_swap) & 0x1;
+ lane_reverse = (pdrv->config.control.lvds_cfg.lane_reverse) & 0x1;
- switch (pconf->lcd_basic.lcd_bits) {
+ switch (pdrv->config.basic.lcd_bits) {
case 10:
- bit_num=0;
- break;
- case 8:
- bit_num=1;
+ bit_num = 0;
break;
case 6:
- bit_num=2;
+ bit_num = 2;
break;
- case 4:
- bit_num=3;
- break;
+ case 8:
default:
- bit_num=1;
+ bit_num = 1;
break;
}
if (dual_port)
@@ -427,7 +273,10 @@
else
fifo_mode = 0x1;
- lcd_vcbus_write(LVDS_PACK_CNTL_ADDR,
+ if (pdrv->data->chip_type == LCD_CHIP_T7)
+ lcd_vcbus_write(LVDS_SER_EN + offset, 0xfff);
+
+ lcd_vcbus_write(LVDS_PACK_CNTL_ADDR + offset,
(lvds_repack << 0) | // repack //[1:0]
(0 << 3) | // reserve
(0 << 4) | // lsb first
@@ -440,36 +289,178 @@
(2 << 14)); //b_select //0:R, 1:G, 2:B, 3:0;
/* lvsd swap */
- lcd_vcbus_setb(LCD_PORT_SWAP, port_swap, 12, 1);
- if (lane_reverse)
- lcd_vcbus_setb(LVDS_GEN_CNTL, 0x03, 13, 2);
+ switch (pdrv->data->chip_type) {
+ case LCD_CHIP_TL1:
+ case LCD_CHIP_TM2:
+ /* lvds channel: //tx 12 channels
+ * 0: d0_a
+ * 1: d1_a
+ * 2: d2_a
+ * 3: clk_a
+ * 4: d3_a
+ * 5: d4_a
+ * 6: d0_b
+ * 7: d1_b
+ * 8: d2_b
+ * 9: clk_b
+ * a: d3_b
+ * b: d4_b
+ */
+ if (port_swap) {
+ if (lane_reverse) {
+ lcd_vcbus_write(P2P_CH_SWAP0, 0x456789ab);
+ lcd_vcbus_write(P2P_CH_SWAP1, 0x0123);
+ } else {
+ lcd_vcbus_write(P2P_CH_SWAP0, 0x10ba9876);
+ lcd_vcbus_write(P2P_CH_SWAP1, 0x5432);
+ }
+ } else {
+ if (lane_reverse) {
+ lcd_vcbus_write(P2P_CH_SWAP0, 0xab012345);
+ lcd_vcbus_write(P2P_CH_SWAP1, 0x6789);
+ } else {
+ lcd_vcbus_write(P2P_CH_SWAP0, 0x76543210);
+ lcd_vcbus_write(P2P_CH_SWAP1, 0xba98);
+ }
+ }
+ break;
+ case LCD_CHIP_T5:
+ case LCD_CHIP_T5D:
+ /* lvds channel: //tx 12 channels
+ * 0: d0_a
+ * 1: d1_a
+ * 2: d2_a
+ * 3: clk_a
+ * 4: d3_a
+ * 5: d4_a
+ * 6: d0_b
+ * 7: d1_b
+ * 8: d2_b
+ * 9: clk_b
+ * a: d3_b
+ * b: d4_b
+ */
+ if (port_swap) {
+ if (lane_reverse) {
+ lcd_vcbus_write(P2P_CH_SWAP0, 0x345789ab);
+ lcd_vcbus_write(P2P_CH_SWAP1, 0x0612);
+ } else {
+ lcd_vcbus_write(P2P_CH_SWAP0, 0x210a9876);
+ lcd_vcbus_write(P2P_CH_SWAP1, 0x5b43);
+ }
+ } else {
+ if (lane_reverse) {
+ lcd_vcbus_write(P2P_CH_SWAP0, 0xab12345);
+ lcd_vcbus_write(P2P_CH_SWAP1, 0x60789);
+ } else {
+ lcd_vcbus_write(P2P_CH_SWAP0, 0x87643210);
+ lcd_vcbus_write(P2P_CH_SWAP1, 0xb5a9);
+ }
+ }
+ break;
+ case LCD_CHIP_T7:
+ /* lvds channel: //tx 12 channels
+ * 0: d0_a
+ * 1: d1_a
+ * 2: d2_a
+ * 3: clk_a
+ * 4: d3_a
+ * 5: d4_a
+ * 6: d0_b
+ * 7: d1_b
+ * 8: d2_b
+ * 9: clk_b
+ * a: d3_b
+ * b: d4_b
+ */
+ if (port_swap) {
+ if (lane_reverse) {
+ lcd_vcbus_write(P2P_CH_SWAP0 + offset, 0x345789ab);
+ lcd_vcbus_write(P2P_CH_SWAP1 + offset, 0x0612);
+ } else {
+ lcd_vcbus_write(P2P_CH_SWAP0 + offset, 0x210a9876);
+ lcd_vcbus_write(P2P_CH_SWAP1 + offset, 0x5b43);
+ }
+ } else {
+ if (lane_reverse) {
+ lcd_vcbus_write(P2P_CH_SWAP0 + offset, 0xab12345);
+ lcd_vcbus_write(P2P_CH_SWAP1 + offset, 0x60789);
+ } else {
+ lcd_vcbus_write(P2P_CH_SWAP0 + offset, 0x87643210);
+ lcd_vcbus_write(P2P_CH_SWAP1 + offset, 0xb5a9);
+ }
+ }
+ lcd_vcbus_write(P2P_BIT_REV + offset, 2);
+ break;
+ default:
+ break;
+ }
- lcd_vcbus_write(LVDS_GEN_CNTL, (lcd_vcbus_read(LVDS_GEN_CNTL) | (1 << 4) | (fifo_mode << 0)));
- lcd_vcbus_setb(LVDS_GEN_CNTL, 1, 3, 1);
+ lcd_vcbus_write(LVDS_GEN_CNTL + offset,
+ (lcd_vcbus_read(LVDS_GEN_CNTL + offset) | (1 << 4) | (fifo_mode << 0)));
+ lcd_vcbus_setb(LVDS_GEN_CNTL + offset, 1, 3, 1);
}
-static void lcd_lvds_disable(void)
+static void lcd_lvds_disable(struct aml_lcd_drv_s *pdrv)
{
- lcd_vcbus_setb(LVDS_GEN_CNTL, 0, 3, 1); /* disable lvds fifo */
+ unsigned int reg_dphy_tx_ctrl0, reg_dphy_tx_ctrl1, offset = 0;
+
+ if (pdrv->data->chip_type == LCD_CHIP_T7) {
+ switch (pdrv->index) {
+ case 0:
+ reg_dphy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0;
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1;
+ break;
+ case 1:
+ reg_dphy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL0;
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL1;
+ break;
+ case 2:
+ reg_dphy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL0;
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL1;
+ break;
+ default:
+ LCDERR("[%d]: %s: invalid drv_index\n", pdrv->index, __func__);
+ return;
+ }
+ offset = pdrv->data->offset_venc_if[pdrv->index];
+
+ /* disable lvds fifo */
+ lcd_vcbus_setb(LVDS_GEN_CNTL + offset, 0, 3, 1);
+ /* disable fifo */
+ lcd_combo_dphy_setb(reg_dphy_tx_ctrl1, 0, 6, 2);
+ /* disable lane */
+ lcd_combo_dphy_setb(reg_dphy_tx_ctrl0, 0, 16, 10);
+ } else {
+ /* disable lvds fifo */
+ lcd_vcbus_setb(LVDS_GEN_CNTL, 0, 3, 1);
+ /* disable fifo */
+ lcd_clk_setb(HHI_LVDS_TX_PHY_CNTL1, 0, 30, 2);
+ /* disable lane */
+ lcd_clk_setb(HHI_LVDS_TX_PHY_CNTL0, 0, 16, 12);
+ }
}
-static void lcd_vbyone_sync_pol(int hsync_pol, int vsync_pol)
+static void lcd_vbyone_sync_pol(unsigned int offset, int hsync_pol, int vsync_pol)
{
- lcd_vcbus_setb(VBO_VIN_CTRL, hsync_pol, 4, 1);
- lcd_vcbus_setb(VBO_VIN_CTRL, vsync_pol, 5, 1);
+ lcd_vcbus_setb(VBO_VIN_CTRL + offset, hsync_pol, 4, 1);
+ lcd_vcbus_setb(VBO_VIN_CTRL + offset, vsync_pol, 5, 1);
- lcd_vcbus_setb(VBO_VIN_CTRL, hsync_pol, 6, 1);
- lcd_vcbus_setb(VBO_VIN_CTRL, vsync_pol, 7, 1);
+ lcd_vcbus_setb(VBO_VIN_CTRL + offset, hsync_pol, 6, 1);
+ lcd_vcbus_setb(VBO_VIN_CTRL + offset, vsync_pol, 7, 1);
}
-static void lcd_vbyone_clk_util_set(struct lcd_config_s *pconf)
+static void lcd_vbyone_clk_util_set(struct aml_lcd_drv_s *pdrv)
{
- unsigned int lcd_bits;
- unsigned int div_sel, phy_div;
+ unsigned int lcd_bits, div_sel, phy_div;
+ unsigned int reg_phy_tx_ctrl0, reg_phy_tx_ctrl1;
+ unsigned int bit_data_in_lvds, bit_data_in_edp, bit_lane_sel;
- phy_div = pconf->lcd_control.vbyone_config->phy_div;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
- lcd_bits = 10;
+ phy_div = pdrv->config.control.vbyone_cfg.phy_div;
+ lcd_bits = pdrv->config.basic.lcd_bits;
switch (lcd_bits) {
case 6:
div_sel = 0;
@@ -478,26 +469,66 @@
div_sel = 2;
break;
case 10:
- div_sel = 3;
- break;
default:
div_sel = 3;
break;
}
- /* set fifo_clk_sel */
- lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL0, (div_sel << 6));
- /* set cntl_ser_en: 8-channel to 1 */
- lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12);
- /* decoupling fifo enable, gated clock enable */
- lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL1,
- (1 << 30) | ((phy_div - 1) << 25) | (1 << 24));
- /* decoupling fifo write enable after fifo enable */
- lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL1, 1, 31, 1);
+ if (pdrv->data->chip_type == LCD_CHIP_T7) {
+ switch (pdrv->index) {
+ case 0:
+ reg_phy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0;
+ reg_phy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1;
+ bit_data_in_lvds = 0;
+ bit_data_in_edp = 1;
+ bit_lane_sel = 0;
+ break;
+ case 1:
+ reg_phy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL0;
+ reg_phy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL1;
+ bit_data_in_lvds = 2;
+ bit_data_in_edp = 3;
+ bit_lane_sel = 16;
+ break;
+ default:
+ LCDERR("[%d]: %s: invalid drv_index\n",
+ pdrv->index, __func__);
+ return;
+ }
+
+ // sel dphy data_in
+ lcd_combo_dphy_setb(COMBO_DPHY_CNTL0, 0, bit_data_in_edp, 1);
+ lcd_combo_dphy_setb(COMBO_DPHY_CNTL0, 1, bit_data_in_lvds, 1);
+ // sel dphy lane
+ lcd_combo_dphy_setb(COMBO_DPHY_CNTL1, 0x5555, bit_lane_sel, 16);
+
+ /* set fifo_clk_sel: div 7 */
+ lcd_combo_dphy_write(reg_phy_tx_ctrl0, (div_sel << 5));
+ /* set cntl_ser_en: 8-channel to 1 */
+ lcd_combo_dphy_setb(reg_phy_tx_ctrl0, 0xff, 16, 8);
+
+ /* decoupling fifo enable, gated clock enable */
+ lcd_combo_dphy_write(reg_phy_tx_ctrl1, (1 << 6) | (1 << 0));
+ /* decoupling fifo write enable after fifo enable */
+ lcd_combo_dphy_setb(reg_phy_tx_ctrl1, 1, 7, 1);
+ } else {
+ /* set fifo_clk_sel: div 10 */
+ lcd_ana_write(HHI_LVDS_TX_PHY_CNTL0, (div_sel << 6));
+ /* set cntl_ser_en: 8-channel to 1 */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12);
+ /* pn swap */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL0, 1, 2, 1);
+
+ /* decoupling fifo enable, gated clock enable */
+ lcd_ana_write(HHI_LVDS_TX_PHY_CNTL1,
+ (1 << 30) | ((phy_div - 1) << 25) | (1 << 24));
+ /* decoupling fifo write enable after fifo enable */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL1, 1, 31, 1);
+ }
}
-static int lcd_vbyone_lanes_set(int lane_num, int byte_mode, int region_num,
- int hsize, int vsize)
+static int lcd_vbyone_lanes_set(unsigned int offset, int lane_num, int byte_mode,
+ int region_num, int hsize, int vsize)
{
int sublane_num;
int region_size[4];
@@ -529,16 +560,16 @@
default:
return -1;
}
- if (lcd_debug_print_flag) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
LCDPR("byte_mode=%d, lane_num=%d, region_num=%d\n",
byte_mode, lane_num, region_num);
}
sublane_num = lane_num / region_num; /* lane num in each region */
- lcd_vcbus_setb(VBO_LANES, (lane_num - 1), 0, 3);
- lcd_vcbus_setb(VBO_LANES, (region_num - 1), 4, 2);
- lcd_vcbus_setb(VBO_LANES, (sublane_num - 1), 8, 3);
- lcd_vcbus_setb(VBO_LANES, (byte_mode - 1), 11, 2);
+ lcd_vcbus_setb(VBO_LANES + offset, (lane_num - 1), 0, 3);
+ lcd_vcbus_setb(VBO_LANES + offset, (region_num - 1), 4, 2);
+ lcd_vcbus_setb(VBO_LANES + offset, (sublane_num - 1), 8, 3);
+ lcd_vcbus_setb(VBO_LANES + offset, (byte_mode - 1), 11, 2);
if (region_num > 1) {
region_size[3] = (hsize / lane_num) * sublane_num;
@@ -549,363 +580,256 @@
sublane_num : (tmp % sublane_num));
region_size[2] = region_size[3] + (((tmp / sublane_num) > 2) ?
sublane_num : (tmp % sublane_num));
- lcd_vcbus_write(VBO_REGION_00, region_size[0]);
- lcd_vcbus_write(VBO_REGION_01, region_size[1]);
- lcd_vcbus_write(VBO_REGION_02, region_size[2]);
- lcd_vcbus_write(VBO_REGION_03, region_size[3]);
+ lcd_vcbus_write(VBO_REGION_00 + offset, region_size[0]);
+ lcd_vcbus_write(VBO_REGION_01 + offset, region_size[1]);
+ lcd_vcbus_write(VBO_REGION_02 + offset, region_size[2]);
+ lcd_vcbus_write(VBO_REGION_03 + offset, region_size[3]);
}
- lcd_vcbus_write(VBO_ACT_VSIZE, vsize);
+ lcd_vcbus_write(VBO_ACT_VSIZE + offset, vsize);
/* different from FBC code!!! */
- /* lcd_vcbus_setb(VBO_CTRL_H,0x80,11,5); */
+ /* lcd_vcbus_setb(VBO_CTRL_H + offset,0x80,11,5); */
/* different from simulation code!!! */
- lcd_vcbus_setb(VBO_CTRL_H, 0x0, 0, 4);
- lcd_vcbus_setb(VBO_CTRL_H, 0x1, 9, 1);
- /* lcd_vcbus_setb(VBO_CTRL_L,enable,0,1); */
+ lcd_vcbus_setb(VBO_CTRL_H + offset, 0x0, 0, 4);
+ lcd_vcbus_setb(VBO_CTRL_H + offset, 0x1, 9, 1);
+ /* lcd_vcbus_setb(VBO_CTRL_L + offset,enable,0,1); */
return 0;
}
-static void lcd_vbyone_sw_reset(void)
-{
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
-
- /* force PHY to 0 */
- lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0, 3, 8, 2);
- lcd_vcbus_write(VBO_SOFT_RST, 0x1ff);
- udelay(5);
- /* realease PHY */
- lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0, 0, 8, 2);
- lcd_vcbus_write(VBO_SOFT_RST, 0);
-}
-
-static void lcd_vbyone_wait_timing_stable(void)
-{
- unsigned int timing_state;
- int i = 200;
-
- timing_state = lcd_vcbus_read(VBO_INTR_STATE) & 0x1ff;
- while ((timing_state) && (i > 0)) {
- /* clear video timing error intr */
- lcd_vcbus_setb(VBO_INTR_STATE_CTRL, 0x7, 0, 3);
- lcd_vcbus_setb(VBO_INTR_STATE_CTRL, 0, 0, 3);
- mdelay(2);
- timing_state = lcd_vcbus_read(VBO_INTR_STATE) & 0x1ff;
- i--;
- };
- if (lcd_debug_print_flag) {
- LCDPR("vbyone timing state: 0x%03x, i=%d\n",
- timing_state, (200 - i));
- }
- mdelay(2);
-}
-
-static void lcd_vbyone_control_set(struct lcd_config_s *pconf)
+static void lcd_vbyone_control_set(struct aml_lcd_drv_s *pdrv)
{
int lane_count, byte_mode, region_num, hsize, vsize;
/* int color_fmt; */
int vin_color, vin_bpp;
+ unsigned int offset;
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
- hsize = pconf->lcd_basic.h_active;
- vsize = pconf->lcd_basic.v_active;
- lane_count = pconf->lcd_control.vbyone_config->lane_count; /* 8 */
- region_num = pconf->lcd_control.vbyone_config->region_num; /* 2 */
- byte_mode = pconf->lcd_control.vbyone_config->byte_mode; /* 4 */
- /* color_fmt = pconf->lcd_control.vbyone_config->color_fmt; // 4 */
+ offset = pdrv->data->offset_venc_if[pdrv->index];
- lcd_vbyone_clk_util_set(pconf);
-#if 0
- switch (color_fmt) {
- case 0:/* SDVT_VBYONE_18BPP_RGB */
- vin_color = 4;
- vin_bpp = 2;
- break;
- case 1:/* SDVT_VBYONE_18BPP_YCBCR444 */
- vin_color = 0;
- vin_bpp = 2;
- break;
- case 2:/* SDVT_VBYONE_24BPP_RGB */
- vin_color = 4;
- vin_bpp = 1;
- break;
- case 3:/* SDVT_VBYONE_24BPP_YCBCR444 */
- vin_color = 0;
- vin_bpp = 1;
- break;
- case 4:/* SDVT_VBYONE_30BPP_RGB */
- vin_color = 4;
- vin_bpp = 0;
- break;
- case 5:/* SDVT_VBYONE_30BPP_YCBCR444 */
- vin_color = 0;
- vin_bpp = 0;
- break;
- default:
- LCDERR("vbyone COLOR_FORMAT unsupport\n");
- return;
- }
-#else
+ hsize = pdrv->config.basic.h_active;
+ vsize = pdrv->config.basic.v_active;
+ lane_count = pdrv->config.control.vbyone_cfg.lane_count; /* 8 */
+ region_num = pdrv->config.control.vbyone_cfg.region_num; /* 2 */
+ byte_mode = pdrv->config.control.vbyone_cfg.byte_mode; /* 4 */
+ /* color_fmt = pdrv->config.control.vbyone_cfg.color_fmt; // 4 */
+
vin_color = 4; /* fixed RGB */
- vin_bpp = 0; /* fixed 30bbp 4:4:4 */
-#endif
+ switch (pdrv->config.basic.lcd_bits) {
+ case 6:
+ vin_bpp = 2; /* 18bbp 4:4:4 */
+ break;
+ case 8:
+ vin_bpp = 1; /* 24bbp 4:4:4 */
+ break;
+ case 10:
+ default:
+ vin_bpp = 0; /* 30bbp 4:4:4 */
+ break;
+ }
+
+ lcd_vbyone_clk_util_set(pdrv);
/* set Vbyone vin color format */
- lcd_vcbus_setb(VBO_VIN_CTRL, vin_color, 8, 3);
- lcd_vcbus_setb(VBO_VIN_CTRL, vin_bpp, 11, 2);
+ lcd_vcbus_setb(VBO_VIN_CTRL + offset, vin_color, 8, 3);
+ lcd_vcbus_setb(VBO_VIN_CTRL + offset, vin_bpp, 11, 2);
- lcd_vbyone_lanes_set(lane_count, byte_mode, region_num, hsize, vsize);
+ lcd_vbyone_lanes_set(offset, lane_count, byte_mode, region_num, hsize, vsize);
/*set hsync/vsync polarity to let the polarity is low active
inside the VbyOne */
- lcd_vbyone_sync_pol(0, 0);
+ lcd_vbyone_sync_pol(offset, 0, 0);
/* below line copy from simulation */
/* gate the input when vsync asserted */
- lcd_vcbus_setb(VBO_VIN_CTRL, 1, 0, 2);
- /* lcd_vcbus_write(VBO_VBK_CTRL_0,0x13);
- //lcd_vcbus_write(VBO_VBK_CTRL_1,0x56);
- //lcd_vcbus_write(VBO_HBK_CTRL,0x3478);
- //lcd_vcbus_setb(VBO_PXL_CTRL,0x2,0,4);
- //lcd_vcbus_setb(VBO_PXL_CTRL,0x3,VBO_PXL_CTR1_BIT,VBO_PXL_CTR1_WID);
+ lcd_vcbus_setb(VBO_VIN_CTRL + offset, 1, 0, 2);
+ /* lcd_vcbus_write(VBO_VBK_CTRL_0 + offset,0x13);
+ //lcd_vcbus_write(VBO_VBK_CTRL_1 + offset,0x56);
+ //lcd_vcbus_write(VBO_HBK_CTRL + offset,0x3478);
+ //lcd_vcbus_setb(VBO_PXL_CTRL + offset,0x2,0,4);
+ //lcd_vcbus_setb(VBO_PXL_CTRL + offset,0x3,VBO_PXL_CTR1_BIT,VBO_PXL_CTR1_WID);
//set_vbyone_ctlbits(1,0,0); */
+ /* VBO_RGN_GEN clk always on */
+ lcd_vcbus_setb(VBO_GCLK_MAIN + offset, 2, 2, 2);
/* PAD select: */
if ((lane_count == 1) || (lane_count == 2))
- lcd_vcbus_setb(LCD_PORT_SWAP, 1, 9, 2);
+ lcd_vcbus_setb(LCD_PORT_SWAP + offset, 1, 9, 2);
else if (lane_count == 4)
- lcd_vcbus_setb(LCD_PORT_SWAP, 2, 9, 2);
+ lcd_vcbus_setb(LCD_PORT_SWAP + offset, 2, 9, 2);
else
- lcd_vcbus_setb(LCD_PORT_SWAP, 0, 9, 2);
- /* lcd_vcbus_setb(LCD_PORT_SWAP, 1, 8, 1);//reverse lane output order */
+ lcd_vcbus_setb(LCD_PORT_SWAP + offset, 0, 9, 2);
+ /* lcd_vcbus_setb(LCD_PORT_SWAP + offset, 1, 8, 1);//reverse lane output order */
- /* Mux pads in combo-phy: 0 for dsi; 1 for lvds or vbyone; 2 for edp */
- lcd_hiu_write(HHI_DSI_LVDS_EDP_CNTL0, 0x1);
- lcd_vcbus_setb(VBO_CTRL_L, 1, 0, 1);
+ lcd_vbyone_hw_filter(pdrv, 1);
+ lcd_vcbus_setb(VBO_INSGN_CTRL + offset, 0, 2, 2);
- /*force vencl clk enable, otherwise, it might auto turn off by mipi DSI
- //lcd_vcbus_setb(VPU_MISC_CTRL, 1, 0, 1); */
+ lcd_vcbus_setb(VBO_CTRL_L + offset, 1, 0, 1);
- lcd_vbyone_wait_timing_stable();
- lcd_vbyone_sw_reset();
+ lcd_vbyone_wait_timing_stable(pdrv);
+ lcd_vbyone_sw_reset(pdrv);
+
+ /* training hold */
+ if ((pdrv->config.control.vbyone_cfg.ctrl_flag) & 0x4)
+ lcd_vbyone_cdr_training_hold(pdrv, 1);
}
-static void lcd_vbyone_disable(void)
+static void lcd_vbyone_disable(struct aml_lcd_drv_s *pdrv)
{
- lcd_vcbus_setb(VBO_CTRL_L, 0, 0, 1);
-}
+ unsigned int reg_dphy_tx_ctrl0, reg_dphy_tx_ctrl1, offset;
-static void lcd_vbyone_wait_stable(void)
-{
- int i = 500;
-
- while (((lcd_vcbus_read(VBO_STATUS_L) & 0x3f) != 0x20) && (i > 0)) {
- mdelay(2);
- i--;
- }
- LCDPR("%s status: 0x%x, i=%d\n", __func__, lcd_vcbus_read(VBO_STATUS_L), (500 - i));
-}
-
-static void lcd_vx1_wait_hpd(void)
-{
- int i = 0;
- while (lcd_vcbus_read(VBO_STATUS_L) & 0x40) {
- if (i++ >= 10000)
+ if (pdrv->data->chip_type == LCD_CHIP_T7) {
+ switch (pdrv->index) {
+ case 0:
+ reg_dphy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0;
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1;
break;
- udelay(50);
- }
- if (lcd_vcbus_read(VBO_STATUS_L) & 0x40)
- LCDPR("%s: hpd=%d\n", __func__,
- ((lcd_vcbus_read(VBO_STATUS_L) >> 6) & 0x1));
- else
- LCDPR("%s: hpd=%d, i=%d\n", __func__,
- ((lcd_vcbus_read(VBO_STATUS_L) >> 6) & 0x1), i);
-}
-
-static unsigned int vbyone_lane_num[] = {
- 1,
- 2,
- 4,
- 8,
- 8,
-};
-
-#define VBYONE_BIT_RATE_MAX 3100 //MHz
-#define VBYONE_BIT_RATE_MIN 600
-static void lcd_vbyone_config_set(struct lcd_config_s *pconf)
-{
- unsigned int band_width, bit_rate, pclk, phy_div;
- unsigned int byte_mode, lane_count, minlane;
- unsigned int temp, i;
-
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
-
- //auto calculate bandwidth, clock
- lane_count = pconf->lcd_control.vbyone_config->lane_count;
- byte_mode = pconf->lcd_control.vbyone_config->byte_mode;
- /* byte_mode * byte2bit * 8/10_encoding * pclk =
- byte_mode * 8 * 10 / 8 * pclk */
- pclk = pconf->lcd_timing.lcd_clk / 1000; /* kHz */
- band_width = byte_mode * 10 * pclk;
-
- temp = VBYONE_BIT_RATE_MAX * 1000;
- temp = (band_width + temp - 1) / temp;
- for (i = 0; i < 4; i++) {
- if (temp <= vbyone_lane_num[i])
+ case 1:
+ reg_dphy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL0;
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL1;
break;
- }
- minlane = vbyone_lane_num[i];
- if (lane_count < minlane) {
- LCDERR("vbyone lane_num(%d) is less than min(%d)\n",
- lane_count, minlane);
- lane_count = minlane;
- pconf->lcd_control.vbyone_config->lane_count = lane_count;
- LCDPR("change to min lane_num %d\n", minlane);
- }
+ default:
+ LCDERR("[%d]: %s: invalid drv_index\n", pdrv->index, __func__);
+ return;
+ }
+ offset = pdrv->data->offset_venc_if[pdrv->index];
- bit_rate = band_width / minlane;
- phy_div = lane_count / minlane;
- if (phy_div == 8) {
- phy_div /= 2;
- bit_rate /= 2;
- }
- if (bit_rate > (VBYONE_BIT_RATE_MAX * 1000)) {
- LCDERR("vbyone bit rate(%dKHz) is out of max(%dKHz)\n",
- bit_rate, (VBYONE_BIT_RATE_MAX * 1000));
- }
- if (bit_rate < (VBYONE_BIT_RATE_MIN * 1000)) {
- LCDERR("vbyone bit rate(%dKHz) is out of min(%dKHz)\n",
- bit_rate, (VBYONE_BIT_RATE_MIN * 1000));
- }
- bit_rate = bit_rate * 1000; /* Hz */
+ lcd_vcbus_setb(VBO_CTRL_L + offset, 0, 0, 1);
+ /* clear insig setting */
+ lcd_vcbus_setb(VBO_INSGN_CTRL + offset, 0, 2, 1);
+ lcd_vcbus_setb(VBO_INSGN_CTRL + offset, 0, 0, 1);
- pconf->lcd_control.vbyone_config->phy_div = phy_div;
- pconf->lcd_control.vbyone_config->bit_rate = bit_rate;
+ /* disable fifo */
+ lcd_combo_dphy_setb(reg_dphy_tx_ctrl1, 0, 6, 2);
+ /* disable lane */
+ lcd_combo_dphy_setb(reg_dphy_tx_ctrl0, 0, 16, 8);
+ } else {
+ lcd_vcbus_setb(VBO_CTRL_L, 0, 0, 1);
+ /* clear insig setting */
+ lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 2, 1);
+ lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 0, 1);
- if (lcd_debug_print_flag) {
- LCDPR("lane_count=%u, bit_rate = %uMHz, pclk=%u.%03uMhz\n",
- lane_count, (bit_rate / 1000000),
- (pclk / 1000), (pclk % 1000));
+ /* disable fifo */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL1, 0, 30, 2);
+ /* disable lane */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL0, 0, 16, 12);
}
}
-void lcd_tablet_config_update(struct lcd_config_s *pconf)
+void lcd_tablet_config_update(struct aml_lcd_drv_s *pdrv)
{
/* update interface timing */
- switch (pconf->lcd_basic.lcd_type) {
+ switch (pdrv->config.basic.lcd_type) {
case LCD_VBYONE:
- lcd_vbyone_config_set(pconf);
+ lcd_vbyone_config_set(pdrv);
break;
case LCD_MIPI:
- lcd_mipi_dsi_config_set(pconf);
+ lcd_mipi_dsi_config_set(pdrv);
+ break;
+ case LCD_EDP:
+ lcd_edp_config_set(pdrv);
break;
default:
break;
}
}
-void lcd_tablet_driver_init_pre(void)
+void lcd_tablet_driver_init_pre(struct aml_lcd_drv_s *pdrv)
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- struct lcd_config_s *pconf;
int ret;
- pconf = lcd_drv->lcd_config;
- LCDPR("tablet driver init(ver %s): %s\n", lcd_drv->version,
- lcd_type_type_to_str(pconf->lcd_basic.lcd_type));
- ret = lcd_type_supported(pconf);
+ LCDPR("[%d]: tablet driver init(ver %s): %s\n",
+ pdrv->index,
+ LCD_DRV_VERSION,
+ lcd_type_type_to_str(pdrv->config.basic.lcd_type));
+ ret = lcd_type_supported(&pdrv->config);
if (ret)
return;
- lcd_clk_set(pconf);
- lcd_venc_set(pconf);
- lcd_encl_tcon_set(pconf);
+ lcd_set_clk(pdrv);
+ lcd_set_venc(pdrv);
}
-int lcd_tablet_driver_init(void)
+int lcd_tablet_driver_init(struct aml_lcd_drv_s *pdrv)
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- struct lcd_config_s *pconf;
int ret;
- pconf = lcd_drv->lcd_config;
- ret = lcd_type_supported(pconf);
+ ret = lcd_type_supported(&pdrv->config);
if (ret)
return -1;
/* init driver */
- switch (pconf->lcd_basic.lcd_type) {
+ switch (pdrv->config.basic.lcd_type) {
case LCD_TTL:
- lcd_ttl_control_set(pconf);
- lcd_pinmux_set(1);
+ lcd_ttl_control_set(pdrv);
+ lcd_pinmux_set(pdrv, 1);
break;
case LCD_LVDS:
- lcd_lvds_control_set(pconf);
- lcd_lvds_phy_set(pconf, 1);
+ lcd_lvds_control_set(pdrv);
+ lcd_phy_set(pdrv, 1);
break;
case LCD_VBYONE:
- lcd_pinmux_set(1);
- lcd_vbyone_control_set(pconf);
- lcd_vx1_wait_hpd();
- lcd_vbyone_phy_set(pconf, 1);
- lcd_vbyone_wait_stable();
+ lcd_pinmux_set(pdrv, 1);
+ lcd_vbyone_control_set(pdrv);
+ lcd_vbyone_wait_hpd(pdrv);
+ lcd_phy_set(pdrv, 1);
+ lcd_vbyone_wait_stable(pdrv);
break;
case LCD_MIPI:
- lcd_mipi_phy_set(pconf, 1);
- lcd_mipi_control_set(pconf, 1);
+ lcd_phy_set(pdrv, 1);
+ lcd_mipi_control_set(pdrv);
+ break;
+ case LCD_EDP:
+ lcd_pinmux_set(pdrv, 1);
+ lcd_phy_set(pdrv, 1);
+ lcd_edp_control_set(pdrv);
break;
default:
break;
}
- lcd_vcbus_write(VENC_INTCTRL, 0x200);
-
- if (lcd_debug_print_flag)
- LCDPR("%s finished\n", __func__);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s finished\n", pdrv->index, __func__);
return 0;
}
-void lcd_tablet_driver_disable(void)
+void lcd_tablet_driver_disable(struct aml_lcd_drv_s *pdrv)
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- struct lcd_config_s *pconf;
int ret;
- LCDPR("disable driver\n");
- pconf = lcd_drv->lcd_config;
- ret = lcd_type_supported(pconf);
+ LCDPR("[%d]: disable driver\n", pdrv->index);
+ ret = lcd_type_supported(&pdrv->config);
if (ret)
return;
- switch (pconf->lcd_basic.lcd_type) {
+ switch (pdrv->config.basic.lcd_type) {
case LCD_TTL:
- lcd_pinmux_set(0);
+ lcd_pinmux_set(pdrv, 0);
break;
case LCD_LVDS:
- lcd_lvds_phy_set(pconf, 0);
- lcd_lvds_disable();
+ lcd_phy_set(pdrv, 0);
+ lcd_lvds_disable(pdrv);
break;
case LCD_VBYONE:
- lcd_vbyone_phy_set(pconf, 0);
- lcd_pinmux_set(0);
- lcd_vbyone_disable();
+ lcd_phy_set(pdrv, 0);
+ lcd_pinmux_set(pdrv, 0);
+ lcd_vbyone_disable(pdrv);
break;
case LCD_MIPI:
- mipi_dsi_link_off(pconf);
- lcd_mipi_phy_set(pconf, 0);
- lcd_mipi_control_set(pconf, 0);
+ mipi_dsi_link_off(pdrv);
+ lcd_phy_set(pdrv, 0);
+ lcd_mipi_disable(pdrv);
+ break;
+ case LCD_EDP:
+ lcd_edp_disable(pdrv);
+ lcd_phy_set(pdrv, 0);
+ lcd_pinmux_set(pdrv, 0);
break;
default:
break;
}
- lcd_vcbus_write(ENCL_VIDEO_EN, 0);
-
- lcd_clk_disable();
-
- if (lcd_debug_print_flag)
- LCDPR("%s finished\n", __func__);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s finished\n", pdrv->index, __func__);
}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c
index c119807..c2e3208 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -28,851 +13,84 @@
#include "lcd_tablet.h"
#include "mipi_dsi_util.h"
-static int check_lcd_output_mode(char *mode)
+static int check_lcd_output_mode(struct aml_lcd_drv_s *pdrv, char *mode, unsigned int frac)
{
- if (strcmp(mode, "panel") != 0) {
- LCDERR("outputmode[%s] is not support\n", mode);
+ char str[10];
+
+ if (frac) {
+ LCDERR("don't support frac\n");
+ return -1;
+ }
+
+ if (pdrv->index == 0)
+ sprintf(str, "panel");
+ else
+ sprintf(str, "panel%d", pdrv->index);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("[%d]: %s: outputmode=%s, support mode=%s\n",
+ pdrv->index, __func__, mode, str);
+ }
+
+ if (strcmp(mode, str) != 0) {
+ //LCDERR("outputmode[%s] is not support\n", mode);
return -1;
}
return 0;
}
-static void lcd_list_support_mode(void)
+static void lcd_list_support_mode(struct lcd_config_s *pconf)
{
printf("panel\n");
}
-static void lcd_config_load_print(struct lcd_config_s *pconf)
+static void lcd_config_init(struct aml_lcd_drv_s *pdrv)
{
- if (lcd_debug_print_flag == 0)
- return;
+ struct lcd_config_s *pconf = &pdrv->config;
+ unsigned int h_period, v_period, clk, sync_duration;
- LCDPR("%s, %s, %dbit, %dx%d\n",
- pconf->lcd_basic.model_name,
- lcd_type_type_to_str(pconf->lcd_basic.lcd_type),
- pconf->lcd_basic.lcd_bits,
- pconf->lcd_basic.h_active, pconf->lcd_basic.v_active);
-
- LCDPR("h_period = %d\n", pconf->lcd_basic.h_period);
- LCDPR("v_period = %d\n", pconf->lcd_basic.v_period);
-
- LCDPR("h_period_min = %d\n", pconf->lcd_basic.h_period_min);
- LCDPR("h_period_max = %d\n", pconf->lcd_basic.h_period_max);
- LCDPR("v_period_min = %d\n", pconf->lcd_basic.v_period_min);
- LCDPR("v_period_max = %d\n", pconf->lcd_basic.v_period_max);
- LCDPR("pclk_min = %d\n", pconf->lcd_basic.lcd_clk_min);
- LCDPR("pclk_max = %d\n", pconf->lcd_basic.lcd_clk_max);
-
- LCDPR("hsync_width = %d\n", pconf->lcd_timing.hsync_width);
- LCDPR("hsync_bp = %d\n", pconf->lcd_timing.hsync_bp);
- LCDPR("hsync_pol = %d\n", pconf->lcd_timing.hsync_pol);
- LCDPR("vsync_width = %d\n", pconf->lcd_timing.vsync_width);
- LCDPR("vsync_bp = %d\n", pconf->lcd_timing.vsync_bp);
- LCDPR("vsync_pol = %d\n", pconf->lcd_timing.vsync_pol);
-
- LCDPR("fr_adjust_type = %d\n", pconf->lcd_timing.fr_adjust_type);
- LCDPR("ss_level = %d\n", pconf->lcd_timing.ss_level);
- LCDPR("clk_auto = %d\n", pconf->lcd_timing.clk_auto);
- LCDPR("clk = %dHz\n", pconf->lcd_timing.lcd_clk);
-
- if (pconf->lcd_basic.lcd_type == LCD_TTL) {
- LCDPR("clk_pol = %d\n", pconf->lcd_control.ttl_config->clk_pol);
- LCDPR("sync_valid = %d\n", pconf->lcd_control.ttl_config->sync_valid);
- LCDPR("swap_ctrl = %d\n", pconf->lcd_control.ttl_config->swap_ctrl);
- } else if (pconf->lcd_basic.lcd_type == LCD_LVDS) {
- LCDPR("lvds_repack = %d\n", pconf->lcd_control.lvds_config->lvds_repack);
- LCDPR("pn_swap = %d\n", pconf->lcd_control.lvds_config->pn_swap);
- LCDPR("dual_port = %d\n", pconf->lcd_control.lvds_config->dual_port);
- LCDPR("port_swap = %d\n", pconf->lcd_control.lvds_config->port_swap);
- LCDPR("lane_reverse = %d\n", pconf->lcd_control.lvds_config->lane_reverse);
- } else if (pconf->lcd_basic.lcd_type == LCD_VBYONE) {
- LCDPR("lane_count = %d\n", pconf->lcd_control.vbyone_config->lane_count);
- LCDPR("byte_mode = %d\n", pconf->lcd_control.vbyone_config->byte_mode);
- LCDPR("region_num = %d\n", pconf->lcd_control.vbyone_config->region_num);
- LCDPR("color_fmt = %d\n", pconf->lcd_control.vbyone_config->color_fmt);
- } else if (pconf->lcd_basic.lcd_type == LCD_MIPI) {
- if (pconf->lcd_control.mipi_config->check_en) {
- LCDPR("check_reg = 0x%02x\n",
- pconf->lcd_control.mipi_config->check_reg);
- LCDPR("check_cnt = %d\n",
- pconf->lcd_control.mipi_config->check_cnt);
- }
- LCDPR("lane_num = %d\n",
- pconf->lcd_control.mipi_config->lane_num);
- LCDPR("bit_rate_max = %d\n",
- pconf->lcd_control.mipi_config->bit_rate_max);
- LCDPR("pclk_lanebyteclk_factor = %d\n",
- pconf->lcd_control.mipi_config->factor_numerator);
- LCDPR("operation_mode_init = %d\n",
- pconf->lcd_control.mipi_config->operation_mode_init);
- LCDPR("operation_mode_disp = %d\n",
- pconf->lcd_control.mipi_config->operation_mode_display);
- LCDPR("video_mode_type = %d\n",
- pconf->lcd_control.mipi_config->video_mode_type);
- LCDPR("clk_always_hs = %d\n",
- pconf->lcd_control.mipi_config->clk_always_hs);
- LCDPR("phy_switch = %d\n",
- pconf->lcd_control.mipi_config->phy_switch);
- LCDPR("extern_init = %d\n",
- pconf->lcd_control.mipi_config->extern_init);
- }
-}
-
-static int lcd_config_load_from_dts(const void *dt_blob, struct lcd_config_s *pconf)
-{
- int parent_offset;
- int child_offset;
- char propname[30];
- char *propdata;
- unsigned int temp;
- int len;
-
- parent_offset = fdt_path_offset(dt_blob, "/lcd");
- if (parent_offset < 0) {
- LCDERR("not find /lcd node: %s\n",fdt_strerror(parent_offset));
- return -1;
- }
-
- propdata = (char *)fdt_getprop(dt_blob, parent_offset, "pinctrl_version", NULL);
- if (propdata) {
- pconf->pinctrl_ver = (unsigned char)(be32_to_cpup((u32*)propdata));
- } else {
- pconf->pinctrl_ver = 0;
- }
- LCDPR("pinctrl_version: %d\n", pconf->pinctrl_ver);
-
- /* check panel_type */
- char *panel_type = env_get("panel_type");
- if (panel_type == NULL) {
- LCDERR("no panel_type, use default lcd config\n ");
- return -1;
- }
- LCDPR("use panel_type=%s\n", panel_type);
-
- sprintf(propname, "/lcd/%s", panel_type);
- child_offset = fdt_path_offset(dt_blob, propname);
- if (child_offset < 0) {
- LCDERR("not find /lcd/%s node: %s\n",
- panel_type, fdt_strerror(child_offset));
- return -1;
- }
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "model_name", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get model_name\n");
- strcpy(pconf->lcd_basic.model_name, panel_type);
- } else {
- strcpy(pconf->lcd_basic.model_name, propdata);
- }
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "interface", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get interface\n");
- return -1;
- } else {
- pconf->lcd_basic.lcd_type = lcd_type_str_to_type(propdata);
- }
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "basic_setting", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get basic_setting\n");
- return -1;
- } else {
- pconf->lcd_basic.h_active = be32_to_cpup((u32*)propdata);
- pconf->lcd_basic.v_active = be32_to_cpup((((u32*)propdata)+1));
- pconf->lcd_basic.h_period = be32_to_cpup((((u32*)propdata)+2));
- pconf->lcd_basic.v_period = be32_to_cpup((((u32*)propdata)+3));
- pconf->lcd_basic.lcd_bits = be32_to_cpup((((u32*)propdata)+4));
- pconf->lcd_basic.screen_width = be32_to_cpup((((u32*)propdata)+5));
- pconf->lcd_basic.screen_height = be32_to_cpup((((u32*)propdata)+6));
- }
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "range_setting", NULL);
- if (propdata == NULL) {
- pconf->lcd_basic.h_period_min = pconf->lcd_basic.h_period;
- pconf->lcd_basic.h_period_max = pconf->lcd_basic.h_period;
- pconf->lcd_basic.v_period_min = pconf->lcd_basic.v_period;
- pconf->lcd_basic.v_period_max = pconf->lcd_basic.v_period;
- pconf->lcd_basic.lcd_clk_min = 0;
- pconf->lcd_basic.lcd_clk_max = 0;
- } else {
- pconf->lcd_basic.h_period_min = be32_to_cpup((u32*)propdata);
- pconf->lcd_basic.h_period_max = be32_to_cpup((((u32*)propdata)+1));
- pconf->lcd_basic.v_period_min = be32_to_cpup((((u32*)propdata)+2));
- pconf->lcd_basic.v_period_max = be32_to_cpup((((u32*)propdata)+3));
- pconf->lcd_basic.lcd_clk_min = be32_to_cpup((((u32*)propdata)+4));
- pconf->lcd_basic.lcd_clk_max = be32_to_cpup((((u32*)propdata)+5));
- }
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "lcd_timing", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get lcd_timing\n");
- return -1;
- } else {
- pconf->lcd_timing.hsync_width = (unsigned short)(be32_to_cpup((u32*)propdata));
- pconf->lcd_timing.hsync_bp = (unsigned short)(be32_to_cpup((((u32*)propdata)+1)));
- pconf->lcd_timing.hsync_pol = (unsigned short)(be32_to_cpup((((u32*)propdata)+2)));
- pconf->lcd_timing.vsync_width = (unsigned short)(be32_to_cpup((((u32*)propdata)+3)));
- pconf->lcd_timing.vsync_bp = (unsigned short)(be32_to_cpup((((u32*)propdata)+4)));
- pconf->lcd_timing.vsync_pol = (unsigned short)(be32_to_cpup((((u32*)propdata)+5)));
- }
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "clk_attr", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get clk_attr\n");
- pconf->lcd_timing.fr_adjust_type = 0;
- pconf->lcd_timing.ss_level = 0;
- pconf->lcd_timing.clk_auto = 1;
- pconf->lcd_timing.lcd_clk = 60;
- } else {
- pconf->lcd_timing.fr_adjust_type = (unsigned char)(be32_to_cpup((u32*)propdata));
- pconf->lcd_timing.ss_level = (unsigned char)(be32_to_cpup((((u32*)propdata)+1)));
- pconf->lcd_timing.clk_auto = (unsigned char)(be32_to_cpup((((u32*)propdata)+2)));
- temp = be32_to_cpup((((u32*)propdata)+3));
- if (temp > 0) {
- pconf->lcd_timing.lcd_clk = temp;
- } else { /* avoid 0 mistake */
- pconf->lcd_timing.lcd_clk = 60;
- LCDERR("lcd_clk is 0, default to 60Hz\n");
- }
- }
- if (pconf->lcd_timing.clk_auto == 0) {
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "clk_para", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get clk_para\n");
- pconf->lcd_timing.pll_ctrl = 0x00140248;
- pconf->lcd_timing.div_ctrl = 0x00000901;
- pconf->lcd_timing.clk_ctrl = 0x000000c0;
- } else {
- pconf->lcd_timing.pll_ctrl = be32_to_cpup((u32*)propdata);
- pconf->lcd_timing.div_ctrl = be32_to_cpup((((u32*)propdata)+1));
- pconf->lcd_timing.clk_ctrl = be32_to_cpup((((u32*)propdata)+2));
- }
- }
-
- switch (pconf->lcd_basic.lcd_type) {
- case LCD_TTL:
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "ttl_attr", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get ttl_attr\n");
- } else {
- pconf->lcd_control.ttl_config->clk_pol = be32_to_cpup((u32*)propdata);
- pconf->lcd_control.ttl_config->sync_valid =
- (((be32_to_cpup((((u32*)propdata)+1))) << 1) |
- ((be32_to_cpup((((u32*)propdata)+2))) << 0));
- pconf->lcd_control.ttl_config->swap_ctrl =
- (((be32_to_cpup((((u32*)propdata)+3))) << 1) |
- ((be32_to_cpup((((u32*)propdata)+4))) << 0));
- }
- break;
- case LCD_LVDS:
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "lvds_attr", &len);
- if (propdata == NULL) {
- LCDERR("failed to get lvds_attr\n");
- } else {
- len = len / 4;
- if (len == 5) {
- pconf->lcd_control.lvds_config->lvds_repack = be32_to_cpup((u32*)propdata);
- pconf->lcd_control.lvds_config->dual_port = be32_to_cpup((((u32*)propdata)+1));
- pconf->lcd_control.lvds_config->pn_swap = be32_to_cpup((((u32*)propdata)+2));
- pconf->lcd_control.lvds_config->port_swap = be32_to_cpup((((u32*)propdata)+3));
- pconf->lcd_control.lvds_config->lane_reverse = be32_to_cpup((((u32*)propdata)+4));
- } else if (len == 4) {
- pconf->lcd_control.lvds_config->lvds_repack = be32_to_cpup((u32*)propdata);
- pconf->lcd_control.lvds_config->dual_port = be32_to_cpup((((u32*)propdata)+1));
- pconf->lcd_control.lvds_config->pn_swap = be32_to_cpup((((u32*)propdata)+2));
- pconf->lcd_control.lvds_config->port_swap = be32_to_cpup((((u32*)propdata)+3));
- pconf->lcd_control.lvds_config->lane_reverse = 0;
- } else {
- LCDERR("invalid lvds_attr parameters cnt: %d\n", len);
- }
- }
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "phy_attr", &len);
- if (propdata == NULL) {
- if (lcd_debug_print_flag)
- LCDPR("failed to get phy_attr\n");
- pconf->lcd_control.lvds_config->phy_vswing = LVDS_PHY_VSWING_DFT;
- pconf->lcd_control.lvds_config->phy_preem = LVDS_PHY_PREEM_DFT;
- } else {
- len = len / 4;
- if (len == 4) {
- pconf->lcd_control.lvds_config->phy_vswing = be32_to_cpup((u32*)propdata);
- pconf->lcd_control.lvds_config->phy_preem = be32_to_cpup((((u32*)propdata)+1));
- pconf->lcd_control.lvds_config->phy_clk_vswing = be32_to_cpup((((u32*)propdata)+2));
- pconf->lcd_control.lvds_config->phy_clk_preem = be32_to_cpup((((u32*)propdata)+3));
- if (lcd_debug_print_flag) {
- LCDPR("set phy vswing=0x%x, preemphasis=0x%x\n",
- pconf->lcd_control.lvds_config->phy_vswing,
- pconf->lcd_control.lvds_config->phy_preem);
- LCDPR("set phy clk_vswing=0x%x, clk_preemphasis=0x%x\n",
- pconf->lcd_control.lvds_config->phy_clk_vswing,
- pconf->lcd_control.lvds_config->phy_clk_preem);
- }
- } else if (len == 2) {
- pconf->lcd_control.lvds_config->phy_vswing = be32_to_cpup((u32*)propdata);
- pconf->lcd_control.lvds_config->phy_preem = be32_to_cpup((((u32*)propdata)+1));
- pconf->lcd_control.lvds_config->phy_clk_vswing = LVDS_PHY_CLK_VSWING_DFT;
- pconf->lcd_control.lvds_config->phy_clk_preem = LVDS_PHY_CLK_PREEM_DFT;
- if (lcd_debug_print_flag) {
- LCDPR("set phy vswing=0x%x, preemphasis=0x%x\n",
- pconf->lcd_control.lvds_config->phy_vswing,
- pconf->lcd_control.lvds_config->phy_preem);
- }
- } else {
- LCDERR("invalid phy_attr parameters cnt: %d\n", len);
- }
- }
- break;
- case LCD_VBYONE:
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "vbyone_attr", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get vbyone_attr\n");
- } else {
- pconf->lcd_control.vbyone_config->lane_count = be32_to_cpup((u32*)propdata);
- pconf->lcd_control.vbyone_config->region_num = be32_to_cpup((((u32*)propdata)+1));
- pconf->lcd_control.vbyone_config->byte_mode = be32_to_cpup((((u32*)propdata)+2));
- pconf->lcd_control.vbyone_config->color_fmt = be32_to_cpup((((u32*)propdata)+3));
- }
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "phy_attr", NULL);
- if (propdata == NULL) {
- if (lcd_debug_print_flag)
- LCDPR("failed to get phy_attr\n");
- pconf->lcd_control.vbyone_config->phy_vswing = VX1_PHY_VSWING_DFT;
- pconf->lcd_control.vbyone_config->phy_preem = VX1_PHY_PREEM_DFT;
- } else {
- pconf->lcd_control.vbyone_config->phy_vswing = be32_to_cpup((u32*)propdata);
- pconf->lcd_control.vbyone_config->phy_preem = be32_to_cpup((((u32*)propdata)+1));
- if (lcd_debug_print_flag) {
- LCDPR("set phy vswing=%d, preemphasis=%d\n",
- pconf->lcd_control.vbyone_config->phy_vswing,
- pconf->lcd_control.vbyone_config->phy_preem);
- }
- }
- break;
- case LCD_MIPI:
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "mipi_attr", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get mipi_attr\n");
- } else {
- pconf->lcd_control.mipi_config->lane_num = be32_to_cpup((u32*)propdata);
- pconf->lcd_control.mipi_config->bit_rate_max = be32_to_cpup((((u32*)propdata)+1));
- pconf->lcd_control.mipi_config->factor_numerator = be32_to_cpup((((u32*)propdata)+2));
- pconf->lcd_control.mipi_config->factor_denominator = 100;
- pconf->lcd_control.mipi_config->operation_mode_init = be32_to_cpup((((u32*)propdata)+3));
- pconf->lcd_control.mipi_config->operation_mode_display = be32_to_cpup((((u32*)propdata)+4));
- pconf->lcd_control.mipi_config->video_mode_type = be32_to_cpup((((u32*)propdata)+5));
- pconf->lcd_control.mipi_config->clk_always_hs = be32_to_cpup((((u32*)propdata)+6));
- pconf->lcd_control.mipi_config->phy_switch = be32_to_cpup((((u32*)propdata)+7));
- }
-
- pconf->lcd_control.mipi_config->check_en = 0;
- pconf->lcd_control.mipi_config->check_reg = 0xff;
- pconf->lcd_control.mipi_config->check_cnt = 0;
- lcd_mipi_dsi_init_table_detect(dt_blob, child_offset, pconf->lcd_control.mipi_config, 1);
- lcd_mipi_dsi_init_table_detect(dt_blob, child_offset, pconf->lcd_control.mipi_config, 0);
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "extern_init", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get extern_init\n");
- } else {
- pconf->lcd_control.mipi_config->extern_init = be32_to_cpup((u32*)propdata);
- }
- break;
- default:
- LCDERR("invalid lcd type\n");
- break;
- }
-
- /* check power_step */
- lcd_power_load_from_dts(pconf, dt_blob, child_offset);
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "backlight_index", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get backlight_index\n");
- pconf->backlight_index = 0xff;
- return 0;
- } else {
- pconf->backlight_index = be32_to_cpup((u32*)propdata);
- }
-
- return 0;
-}
-
-static int lcd_config_load_from_bsp(struct lcd_config_s *pconf)
-{
- struct ext_lcd_config_s *ext_lcd = NULL;
- char *panel_type = env_get("panel_type");
- unsigned int i, j;
- unsigned int temp;
- struct lcd_power_step_s *power_step;
-
- if (panel_type == NULL) {
- LCDERR("no panel_type, use default lcd config\n ");
- return -1;
- }
- for (i = 0 ; i < LCD_NUM_MAX ; i++) {
- ext_lcd = &ext_lcd_config[i];
- if (strcmp(ext_lcd->panel_type, panel_type) == 0)
- break;
- if (strcmp(ext_lcd->panel_type, "invalid") == 0) {
- i = LCD_NUM_MAX;
- break;
- }
- }
- if (i >= LCD_NUM_MAX) {
- LCDERR("can't find %s, use default lcd config\n ", panel_type);
- return -1;
- }
- LCDPR("use panel_type=%s\n", panel_type);
-
- strcpy(pconf->lcd_basic.model_name, panel_type);
- pconf->lcd_basic.lcd_type = ext_lcd->lcd_type;
- pconf->lcd_basic.lcd_bits = ext_lcd->lcd_bits;
-
- pconf->lcd_basic.h_active = ext_lcd->h_active;
- pconf->lcd_basic.v_active = ext_lcd->v_active;
- pconf->lcd_basic.h_period = ext_lcd->h_period;
- pconf->lcd_basic.v_period = ext_lcd->v_period;
-
- pconf->lcd_basic.h_period_min = pconf->lcd_basic.h_period;
- pconf->lcd_basic.h_period_max = pconf->lcd_basic.h_period;
- pconf->lcd_basic.v_period_min = pconf->lcd_basic.v_period;
- pconf->lcd_basic.v_period_max = pconf->lcd_basic.v_period;
- pconf->lcd_basic.lcd_clk_min = 0;
- pconf->lcd_basic.lcd_clk_max = 0;
-
- pconf->lcd_timing.hsync_width = ext_lcd->hsync_width;
- pconf->lcd_timing.hsync_bp = ext_lcd->hsync_bp;
- pconf->lcd_timing.hsync_pol = ext_lcd->hsync_pol;
- pconf->lcd_timing.vsync_width = ext_lcd->vsync_width;
- pconf->lcd_timing.vsync_bp = ext_lcd->vsync_bp;
- pconf->lcd_timing.vsync_pol = ext_lcd->vsync_pol;
-
- /* fr_adjust_type */
- temp = ext_lcd->customer_val_0;
- if (temp == Rsv_val)
- pconf->lcd_timing.fr_adjust_type = 0;
- else
- pconf->lcd_timing.fr_adjust_type = (unsigned char)temp;
- /* ss_level */
- temp = ext_lcd->customer_val_1;
- if (temp == Rsv_val)
- pconf->lcd_timing.ss_level = 0;
- else
- pconf->lcd_timing.ss_level = (unsigned char)temp;
- /* clk_auto_generate */
- temp = ext_lcd->customer_val_2;
- if (temp == Rsv_val)
- pconf->lcd_timing.clk_auto = 1;
- else
- pconf->lcd_timing.clk_auto = (unsigned char)temp;
- /* lcd_clk */
- temp = ext_lcd->customer_val_3;
- if (temp == Rsv_val)
- pconf->lcd_timing.lcd_clk = 60;
- else
- pconf->lcd_timing.lcd_clk = temp;
-
- if (pconf->lcd_basic.lcd_type == LCD_TTL) {
- pconf->lcd_control.ttl_config->clk_pol = ext_lcd->if_attr_val0;
- pconf->lcd_control.ttl_config->sync_valid =
- ((ext_lcd->if_attr_val1 << 1) |
- (ext_lcd->if_attr_val2 << 0));
- pconf->lcd_control.ttl_config->swap_ctrl =
- ((ext_lcd->if_attr_val3 << 1) |
- (ext_lcd->if_attr_val4 << 0));
- } else if (pconf->lcd_basic.lcd_type == LCD_LVDS) {
- pconf->lcd_control.lvds_config->lvds_repack = ext_lcd->if_attr_val0;
- pconf->lcd_control.lvds_config->dual_port = ext_lcd->if_attr_val1;
- pconf->lcd_control.lvds_config->pn_swap = ext_lcd->if_attr_val2;
- pconf->lcd_control.lvds_config->port_swap = ext_lcd->if_attr_val3;
- pconf->lcd_control.lvds_config->lane_reverse = ext_lcd->if_attr_val4;
- pconf->lcd_control.lvds_config->phy_vswing = LVDS_PHY_VSWING_DFT;
- pconf->lcd_control.lvds_config->phy_preem = LVDS_PHY_PREEM_DFT;
- pconf->lcd_control.lvds_config->phy_clk_vswing = LVDS_PHY_CLK_VSWING_DFT;
- pconf->lcd_control.lvds_config->phy_clk_preem = LVDS_PHY_CLK_PREEM_DFT;
- } else if (pconf->lcd_basic.lcd_type == LCD_VBYONE) {
- pconf->lcd_control.vbyone_config->lane_count = ext_lcd->if_attr_val0;
- pconf->lcd_control.vbyone_config->region_num = ext_lcd->if_attr_val1;
- pconf->lcd_control.vbyone_config->byte_mode = ext_lcd->if_attr_val2;
- pconf->lcd_control.vbyone_config->color_fmt = ext_lcd->if_attr_val3;
- pconf->lcd_control.vbyone_config->phy_vswing = VX1_PHY_VSWING_DFT;
- pconf->lcd_control.vbyone_config->phy_preem = VX1_PHY_PREEM_DFT;
- } else if (pconf->lcd_basic.lcd_type == LCD_MIPI) {
- pconf->lcd_control.mipi_config->lane_num = ext_lcd->if_attr_val0;
- pconf->lcd_control.mipi_config->bit_rate_max = ext_lcd->if_attr_val1;
- pconf->lcd_control.mipi_config->factor_numerator = ext_lcd->if_attr_val2;
- pconf->lcd_control.mipi_config->operation_mode_init = ext_lcd->if_attr_val3;
- pconf->lcd_control.mipi_config->operation_mode_display = ext_lcd->if_attr_val4;
- pconf->lcd_control.mipi_config->video_mode_type = ext_lcd->if_attr_val5;
- pconf->lcd_control.mipi_config->clk_always_hs = ext_lcd->if_attr_val6;
- pconf->lcd_control.mipi_config->phy_switch = ext_lcd->if_attr_val7;
- pconf->lcd_control.mipi_config->factor_denominator = 100;
-
- pconf->lcd_control.mipi_config->dsi_init_on = ext_lcd->cmd_init_on;
- pconf->lcd_control.mipi_config->dsi_init_off = ext_lcd->cmd_init_off;
- pconf->lcd_control.mipi_config->check_en = 0;
- pconf->lcd_control.mipi_config->check_reg = 0xff;
- pconf->lcd_control.mipi_config->check_cnt = 0;
- lcd_mipi_dsi_init_table_check_bsp(pconf->lcd_control.mipi_config, 1);
- lcd_mipi_dsi_init_table_check_bsp(pconf->lcd_control.mipi_config, 0);
-
- if (ext_lcd->if_attr_val9 == Rsv_val)
- pconf->lcd_control.mipi_config->extern_init = 0xff;
- else
- pconf->lcd_control.mipi_config->extern_init = ext_lcd->if_attr_val9;
- }
-
- i = 0;
- while (i < LCD_PWR_STEP_MAX) {
- power_step = &ext_lcd->power_on_step[i];
- if (lcd_debug_print_flag) {
- LCDPR("power_on: step %d: type=%d, index=%d, value=%d, delay=%d\n",
- i, power_step->type, power_step->index,
- power_step->value, power_step->delay);
- }
- pconf->lcd_power->power_on_step[i].type = power_step->type;
- pconf->lcd_power->power_on_step[i].index = power_step->index;
- pconf->lcd_power->power_on_step[i].value = power_step->value;
- pconf->lcd_power->power_on_step[i].delay = power_step->delay;
- if (power_step->type >= LCD_POWER_TYPE_MAX)
- break;
- else
- i++;
- }
-
- i = 0;
- while (i < LCD_PWR_STEP_MAX) {
- power_step = &ext_lcd->power_off_step[i];
- if (lcd_debug_print_flag) {
- LCDPR("power_off: step %d: type=%d, index=%d, value=%d, delay=%d\n",
- i, power_step->type, power_step->index,
- power_step->value, power_step->delay);
- }
- pconf->lcd_power->power_off_step[i].type = power_step->type;
- pconf->lcd_power->power_off_step[i].index = power_step->index;
- pconf->lcd_power->power_off_step[i].value = power_step->value;
- pconf->lcd_power->power_off_step[i].delay = power_step->delay;
- if (power_step->type >= LCD_POWER_TYPE_MAX)
- break;
- else
- i++;
- }
-
- i = 0;
- while (i < LCD_CPU_GPIO_NUM_MAX) {
- if (strcmp(pconf->lcd_power->cpu_gpio[i], "invalid") == 0)
- break;
- i++;
- }
- for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++) {
- strcpy(pconf->lcd_power->cpu_gpio[j], "invalid");
- }
-
- return 0;
-}
-
-static int lcd_config_load_from_unifykey(struct lcd_config_s *pconf)
-{
- unsigned char *para;
- int key_len, len;
- unsigned char *p;
- const char *str;
- struct aml_lcd_unifykey_header_s lcd_header;
- unsigned int temp;
- int ret;
-
- para = (unsigned char *)malloc(sizeof(unsigned char) * LCD_UKEY_LCD_SIZE);
- if (!para) {
- LCDERR("%s: Not enough memory\n", __func__);
- return -1;
- }
- key_len = LCD_UKEY_LCD_SIZE;
- memset(para, 0, (sizeof(unsigned char) * key_len));
- ret = aml_lcd_unifykey_get("lcd", para, &key_len);
- if (ret) {
- free(para);
- return -1;
- }
-
- /* step 1: check header */
- len = LCD_UKEY_HEAD_SIZE;
- ret = aml_lcd_unifykey_len_check(key_len, len);
- if (ret) {
- LCDERR("unifykey header length is incorrect\n");
- free(para);
- return -1;
- }
-
- aml_lcd_unifykey_header_check(para, &lcd_header);
- LCDPR("unifykey version: 0x%04x\n", lcd_header.version);
- switch (lcd_header.version) {
- case 2:
- len = LCD_UKEY_DATA_LEN_V2; /*10+36+18+31+20+44+10*/
- break;
- default:
- len = LCD_UKEY_DATA_LEN_V1; /*10+36+18+31+20*/
- break;
- }
- if (lcd_debug_print_flag) {
- LCDPR("unifykey header:\n");
- LCDPR("crc32 = 0x%08x\n", lcd_header.crc32);
- LCDPR("data_len = %d\n", lcd_header.data_len);
- LCDPR("reserved = 0x%04x\n", lcd_header.reserved);
- }
-
- /* step 2: check lcd parameters */
- ret = aml_lcd_unifykey_len_check(key_len, len);
- if (ret) {
- LCDERR("unifykey parameters length is incorrect\n");
- free(para);
- return -1;
- }
-
- /* basic: 36byte */
- p = para;
- *(p + LCD_UKEY_MODEL_NAME - 1) = '\0'; /* ensure string ending */
- str = (const char *)(p + LCD_UKEY_HEAD_SIZE);
- strcpy(pconf->lcd_basic.model_name, str);
- pconf->lcd_basic.lcd_type = *(p + LCD_UKEY_INTERFACE);
- pconf->lcd_basic.lcd_bits = *(p + LCD_UKEY_LCD_BITS);
- pconf->lcd_basic.screen_width = (*(p + LCD_UKEY_SCREEN_WIDTH) |
- ((*(p + LCD_UKEY_SCREEN_WIDTH + 1)) << 8));
- pconf->lcd_basic.screen_height = (*(p + LCD_UKEY_SCREEN_HEIGHT) |
- ((*(p + LCD_UKEY_SCREEN_HEIGHT + 1)) << 8));
-
- /* timing: 18byte */
- pconf->lcd_basic.h_active = (*(p + LCD_UKEY_H_ACTIVE) |
- ((*(p + LCD_UKEY_H_ACTIVE + 1)) << 8));
- pconf->lcd_basic.v_active = (*(p + LCD_UKEY_V_ACTIVE)) |
- ((*(p + LCD_UKEY_V_ACTIVE + 1)) << 8);
- pconf->lcd_basic.h_period = (*(p + LCD_UKEY_H_PERIOD)) |
- ((*(p + LCD_UKEY_H_PERIOD + 1)) << 8);
- pconf->lcd_basic.v_period = (*(p + LCD_UKEY_V_PERIOD)) |
- ((*(p + LCD_UKEY_V_PERIOD + 1)) << 8);
- pconf->lcd_timing.hsync_width = (*(p + LCD_UKEY_HS_WIDTH) |
- ((*(p + LCD_UKEY_HS_WIDTH + 1)) << 8));
- pconf->lcd_timing.hsync_bp = (*(p + LCD_UKEY_HS_BP) | ((*(p + LCD_UKEY_HS_BP + 1)) << 8));
- pconf->lcd_timing.hsync_pol = *(p + LCD_UKEY_HS_POL);
- pconf->lcd_timing.vsync_width = (*(p + LCD_UKEY_VS_WIDTH) |
- ((*(p + LCD_UKEY_VS_WIDTH + 1)) << 8));
- pconf->lcd_timing.vsync_bp = (*(p + LCD_UKEY_VS_BP) |
- ((*(p + LCD_UKEY_VS_BP + 1)) << 8));
- pconf->lcd_timing.vsync_pol = *(p + LCD_UKEY_VS_POL);
-
- /* customer: 31byte */
- pconf->lcd_timing.fr_adjust_type = *(p + LCD_UKEY_FR_ADJ_TYPE);
- pconf->lcd_timing.ss_level = *(p + LCD_UKEY_SS_LEVEL);
- pconf->lcd_timing.clk_auto = *(p + LCD_UKEY_CLK_AUTO_GEN);
- pconf->lcd_timing.lcd_clk = (*(p + LCD_UKEY_PCLK) |
- ((*(p + LCD_UKEY_PCLK + 1)) << 8) |
- ((*(p + LCD_UKEY_PCLK + 2)) << 16) |
- ((*(p + LCD_UKEY_PCLK + 3)) << 24));
- pconf->lcd_basic.h_period_min = (*(p + LCD_UKEY_H_PERIOD_MIN) |
- ((*(p + LCD_UKEY_H_PERIOD_MIN + 1)) << 8));
- pconf->lcd_basic.h_period_max = (*(p + LCD_UKEY_H_PERIOD_MAX) |
- ((*(p + LCD_UKEY_H_PERIOD_MAX + 1)) << 8));
- pconf->lcd_basic.v_period_min = (*(p + LCD_UKEY_V_PERIOD_MIN) |
- ((*(p + LCD_UKEY_V_PERIOD_MIN + 1)) << 8));
- pconf->lcd_basic.v_period_max = (*(p + LCD_UKEY_V_PERIOD_MAX) |
- ((*(p + LCD_UKEY_V_PERIOD_MAX + 1)) << 8));
- pconf->lcd_basic.lcd_clk_min = (*(p + LCD_UKEY_PCLK_MIN) |
- ((*(p + LCD_UKEY_PCLK_MIN + 1)) << 8) |
- ((*(p + LCD_UKEY_PCLK_MIN + 2)) << 16) | ((*(p + LCD_UKEY_PCLK_MIN + 3)) << 24));
- pconf->lcd_basic.lcd_clk_max = (*(p + LCD_UKEY_PCLK_MAX) | ((*(p + LCD_UKEY_PCLK_MAX + 1)) << 8) |
- ((*(p + LCD_UKEY_PCLK_MAX + 2)) << 16) | ((*(p + LCD_UKEY_PCLK_MAX + 3)) << 24));
-
- /* interface: 20byte */
- if (pconf->lcd_basic.lcd_type == LCD_LVDS) {
- if (lcd_header.version == 2) {
- pconf->lcd_control.lvds_config->lvds_repack =
- (*(p + LCD_UKEY_IF_ATTR_0) |
- ((*(p + LCD_UKEY_IF_ATTR_0 + 1)) << 8)) & 0xff;
- pconf->lcd_control.lvds_config->dual_port =
- (*(p + LCD_UKEY_IF_ATTR_1) |
- ((*(p + LCD_UKEY_IF_ATTR_1 + 1)) << 8)) & 0xff;
- pconf->lcd_control.lvds_config->pn_swap =
- (*(p + LCD_UKEY_IF_ATTR_2) |
- ((*(p + LCD_UKEY_IF_ATTR_2 + 1)) << 8)) & 0xff;
- pconf->lcd_control.lvds_config->port_swap =
- (*(p + LCD_UKEY_IF_ATTR_3) |
- ((*(p + LCD_UKEY_IF_ATTR_3 + 1)) << 8)) & 0xff;
- pconf->lcd_control.lvds_config->lane_reverse =
- (*(p + LCD_UKEY_IF_ATTR_4) |
- ((*(p + LCD_UKEY_IF_ATTR_4 + 1)) << 8)) & 0xff;
- } else {
- pconf->lcd_control.lvds_config->lvds_repack =
- (*(p + LCD_UKEY_IF_ATTR_0) |
- ((*(p + LCD_UKEY_IF_ATTR_0 + 1)) << 8)) & 0xff;
- pconf->lcd_control.lvds_config->dual_port =
- (*(p + LCD_UKEY_IF_ATTR_1) |
- ((*(p + LCD_UKEY_IF_ATTR_1 + 1)) << 8)) & 0xff;
- pconf->lcd_control.lvds_config->pn_swap =
- (*(p + LCD_UKEY_IF_ATTR_2) |
- ((*(p + LCD_UKEY_IF_ATTR_2 + 1)) << 8)) & 0xff;
- pconf->lcd_control.lvds_config->port_swap =
- (*(p + LCD_UKEY_IF_ATTR_3) |
- ((*(p + LCD_UKEY_IF_ATTR_3 + 1)) << 8)) & 0xff;
- pconf->lcd_control.lvds_config->phy_vswing =
- (*(p + LCD_UKEY_IF_ATTR_4) |
- ((*(p + LCD_UKEY_IF_ATTR_4 + 1)) << 8)) & 0xff;
- pconf->lcd_control.lvds_config->phy_preem =
- (*(p + LCD_UKEY_IF_ATTR_5) |
- ((*(p + LCD_UKEY_IF_ATTR_5 + 1)) << 8)) & 0xff;
- pconf->lcd_control.lvds_config->phy_clk_vswing =
- (*(p + LCD_UKEY_IF_ATTR_6) |
- ((*(p + LCD_UKEY_IF_ATTR_6 + 1)) << 8)) & 0xff;
- pconf->lcd_control.lvds_config->phy_clk_preem =
- (*(p + LCD_UKEY_IF_ATTR_7) |
- ((*(p + LCD_UKEY_IF_ATTR_7 + 1)) << 8)) & 0xff;
-
- pconf->lcd_control.lvds_config->lane_reverse = 0;
- }
- } else if (pconf->lcd_basic.lcd_type == LCD_TTL) {
- pconf->lcd_control.ttl_config->clk_pol =
- (*(p + LCD_UKEY_IF_ATTR_0) |
- ((*(p + LCD_UKEY_IF_ATTR_0 + 1)) << 8)) & 0x1;
- temp = (*(p + LCD_UKEY_IF_ATTR_1) |
- ((*(p + LCD_UKEY_IF_ATTR_1 + 1)) << 8)) & 0x1; /* de_valid */
- pconf->lcd_control.ttl_config->sync_valid = (temp << 1);
- temp = (*(p + LCD_UKEY_IF_ATTR_2) |
- ((*(p + LCD_UKEY_IF_ATTR_2 + 1)) << 8)) & 0x1; /* hvsync_valid */
- pconf->lcd_control.ttl_config->sync_valid |= (temp << 0);
- temp = (*(p + LCD_UKEY_IF_ATTR_3) |
- ((*(p + LCD_UKEY_IF_ATTR_3 + 1)) << 8)) & 0x1; /* rb_swap */
- pconf->lcd_control.ttl_config->swap_ctrl = (temp << 1);
- temp = (*(p + LCD_UKEY_IF_ATTR_4) |
- ((*(p + LCD_UKEY_IF_ATTR_4 + 1)) << 8)) & 0x1; /* bit_swap */
- pconf->lcd_control.ttl_config->swap_ctrl |= (temp << 0);
- } else if (pconf->lcd_basic.lcd_type == LCD_VBYONE) {
- if (lcd_header.version == 2) {
- pconf->lcd_control.vbyone_config->lane_count =
- (*(p + LCD_UKEY_IF_ATTR_0) |
- ((*(p + LCD_UKEY_IF_ATTR_0 + 1)) << 8)) & 0xff;
- pconf->lcd_control.vbyone_config->region_num =
- (*(p + LCD_UKEY_IF_ATTR_1) |
- ((*(p + LCD_UKEY_IF_ATTR_1 + 1)) << 8)) & 0xff;
- pconf->lcd_control.vbyone_config->byte_mode =
- (*(p + LCD_UKEY_IF_ATTR_2) |
- ((*(p + LCD_UKEY_IF_ATTR_2 + 1)) << 8)) & 0xff;
- pconf->lcd_control.vbyone_config->color_fmt =
- (*(p + LCD_UKEY_IF_ATTR_3) |
- ((*(p + LCD_UKEY_IF_ATTR_3 + 1)) << 8)) & 0xff;
- } else {
- pconf->lcd_control.vbyone_config->lane_count =
- (*(p + LCD_UKEY_IF_ATTR_0) |
- ((*(p + LCD_UKEY_IF_ATTR_0 + 1)) << 8)) & 0xff;
- pconf->lcd_control.vbyone_config->region_num =
- (*(p + LCD_UKEY_IF_ATTR_1) |
- ((*(p + LCD_UKEY_IF_ATTR_1 + 1)) << 8)) & 0xff;
- pconf->lcd_control.vbyone_config->byte_mode =
- (*(p + LCD_UKEY_IF_ATTR_2) |
- ((*(p + LCD_UKEY_IF_ATTR_2 + 1)) << 8)) & 0xff;
- pconf->lcd_control.vbyone_config->color_fmt =
- (*(p + LCD_UKEY_IF_ATTR_3) |
- ((*(p + LCD_UKEY_IF_ATTR_3 + 1)) << 8)) & 0xff;
- pconf->lcd_control.vbyone_config->phy_vswing =
- (*(p + LCD_UKEY_IF_ATTR_4) |
- ((*(p + LCD_UKEY_IF_ATTR_4 + 1)) << 8)) & 0xff;
- pconf->lcd_control.vbyone_config->phy_preem =
- (*(p + LCD_UKEY_IF_ATTR_5) |
- ((*(p + LCD_UKEY_IF_ATTR_5 + 1)) << 8)) & 0xff;
- }
- } else
- LCDERR("unsupport lcd_type: %d\n", pconf->lcd_basic.lcd_type);
-
- if (lcd_header.version == 2) {
- /* phy: 10byte */ /* v2 */
- if (pconf->lcd_basic.lcd_type == LCD_LVDS) {
- pconf->lcd_control.lvds_config->phy_vswing = *(p +LCD_UKEY_PHY_ATTR_0);
- pconf->lcd_control.lvds_config->phy_preem = *(p + LCD_UKEY_PHY_ATTR_1);
- pconf->lcd_control.lvds_config->phy_clk_vswing = *(p + LCD_UKEY_PHY_ATTR_2);
- pconf->lcd_control.lvds_config->phy_clk_preem = *(p + LCD_UKEY_PHY_ATTR_3);
- } else if (pconf->lcd_basic.lcd_type == LCD_VBYONE) {
- pconf->lcd_control.vbyone_config->phy_vswing =
- (*(p + LCD_UKEY_PHY_ATTR_0) |
- ((*(p + LCD_UKEY_PHY_ATTR_0 + 1)) << 8)) & 0xff;
- pconf->lcd_control.vbyone_config->phy_preem =
- (*(p + LCD_UKEY_PHY_ATTR_1) |
- ((*(p + LCD_UKEY_PHY_ATTR_1 + 1)) << 8)) & 0xff;
- }
- }
-
- /* step 3: check power sequence */
- ret = lcd_power_load_from_unifykey(pconf, para, key_len, len);
- if (ret < 0) {
- free(para);
- return -1;
- }
-
- free(para);
- return 0;
-}
-
-static void lcd_config_init(struct lcd_config_s *pconf)
-{
- unsigned int h_period = pconf->lcd_basic.h_period;
- unsigned int v_period = pconf->lcd_basic.v_period;
- unsigned int clk = pconf->lcd_timing.lcd_clk;
- unsigned int sync_duration;
+ h_period = pconf->basic.h_period;
+ v_period = pconf->basic.v_period;
+ clk = pconf->timing.lcd_clk;
if (clk < 200) { /* regard as frame_rate */
sync_duration = clk * 100;
- pconf->lcd_timing.lcd_clk = clk * h_period * v_period;
+ pconf->timing.lcd_clk = clk * h_period * v_period;
} else { /* regard as pixel clock */
sync_duration = ((clk / h_period) * 100) / v_period;
}
- pconf->lcd_timing.lcd_clk_dft = pconf->lcd_timing.lcd_clk;
- pconf->lcd_timing.h_period_dft = pconf->lcd_basic.h_period;
- pconf->lcd_timing.v_period_dft = pconf->lcd_basic.v_period;
- pconf->lcd_timing.sync_duration_num = sync_duration;
- pconf->lcd_timing.sync_duration_den = 100;
+ pconf->timing.lcd_clk_dft = pconf->timing.lcd_clk;
+ pconf->timing.h_period_dft = pconf->basic.h_period;
+ pconf->timing.v_period_dft = pconf->basic.v_period;
+ pconf->timing.sync_duration_num = sync_duration;
+ pconf->timing.sync_duration_den = 100;
lcd_timing_init_config(pconf);
- lcd_tablet_config_update(pconf);
- lcd_clk_generate_parameter(pconf);
+ lcd_tablet_config_update(pdrv);
+ lcd_clk_generate_parameter(pdrv);
}
-static int lcd_config_check(char *mode)
+static int lcd_config_check(struct aml_lcd_drv_s *pdrv, char *mode, unsigned int frac)
{
int ret;
- ret = check_lcd_output_mode(mode);
+ ret = check_lcd_output_mode(pdrv, mode, frac);
if (ret)
return -1;
return 0;
}
-int get_lcd_tablet_config(const void *dt_blob, int load_id)
+int lcd_mode_tablet_init(struct aml_lcd_drv_s *pdrv)
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- int ret = 0;
+ pdrv->list_support_mode = lcd_list_support_mode;
+ pdrv->outputmode_check = check_lcd_output_mode;
+ pdrv->config_check = lcd_config_check;
+ pdrv->driver_init_pre = lcd_tablet_driver_init_pre;
+ pdrv->driver_init = lcd_tablet_driver_init;
+ pdrv->driver_disable = lcd_tablet_driver_disable;
- strcpy(lcd_drv->version, LCD_DRV_VERSION);
- lcd_drv->list_support_mode = lcd_list_support_mode;
- lcd_drv->outputmode_check = check_lcd_output_mode;
- lcd_drv->config_check = lcd_config_check;
- lcd_drv->driver_init_pre = lcd_tablet_driver_init_pre;
- lcd_drv->driver_init = lcd_tablet_driver_init;
- lcd_drv->driver_disable = lcd_tablet_driver_disable;
-
- if (load_id & 0x10) { /* unifykey */
- ret = lcd_config_load_from_unifykey(lcd_drv->lcd_config);
- ret = lcd_pinmux_load_config(dt_blob, lcd_drv->lcd_config);
- } else if (load_id & 0x1) { /* dts */
- ret = lcd_config_load_from_dts(dt_blob, lcd_drv->lcd_config);
- ret = lcd_pinmux_load_config(dt_blob, lcd_drv->lcd_config);
- } else { /* bsp */
- ret = lcd_config_load_from_bsp(lcd_drv->lcd_config);
- }
- if (ret)
- return -1;
-
- lcd_config_init(lcd_drv->lcd_config);
- lcd_config_load_print(lcd_drv->lcd_config);
+ lcd_config_init(pdrv);
return 0;
}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.h b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.h
index 86f86a7..c06114f 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.h
+++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.h
@@ -1,26 +1,11 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/vout/lcd/lcd_tablet/lcd_tablet.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __AML_LCD_TABLET_H__
#define __AML_LCD_TABLET_H__
+#include <amlogic/media/vout/lcd/lcd_vout.h>
//**********************************
//lcd driver version
@@ -29,9 +14,9 @@
//**********************************
-extern void lcd_tablet_config_update(struct lcd_config_s *pconf);
-extern void lcd_tablet_driver_init_pre(void);
-extern int lcd_tablet_driver_init(void);
-extern void lcd_tablet_driver_disable(void);
+void lcd_tablet_config_update(struct aml_lcd_drv_s *pdrv);
+void lcd_tablet_driver_init_pre(struct aml_lcd_drv_s *pdrv);
+int lcd_tablet_driver_init(struct aml_lcd_drv_s *pdrv);
+void lcd_tablet_driver_disable(struct aml_lcd_drv_s *pdrv);
#endif
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.c b/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.c
index 2c07c76..71a50cf 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.c
@@ -1,24 +1,15 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/display/lcd/lcd_tablet/mipi_dsi_util.c
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
#include <malloc.h>
#include <asm/arch/gpio.h>
#include <fdtdec.h>
+#ifdef CONFIG_SECURE_POWER_CONTROL
+#include <asm/arch/pwr_ctrl.h>
+#endif
#include <amlogic/media/vout/lcd/aml_lcd.h>
#include "../lcd_reg.h"
#include "../lcd_common.h"
@@ -140,11 +131,11 @@
}
}
-static void mipi_dsi_dphy_print_info(struct dsi_config_s *dconf)
+static void mipi_dsi_dphy_print_info(struct lcd_config_s *pconf)
{
unsigned int temp;
- temp = ((1000000 * 100) / (dconf->bit_rate / 1000)) * 8;
+ temp = ((1000000 * 100) / (pconf->timing.bit_rate / 1000)) * 8;
printf("MIPI DSI DPHY timing (unit: ns)\n"
" UI: %d.%02d\n"
" LP TESC: %d\n"
@@ -204,8 +195,8 @@
unsigned int esc_clk, factor;
struct dsi_config_s *dconf;
- dconf = pconf->lcd_control.mipi_config;
- esc_clk = dconf->bit_rate / 8 / dsi_phy_config.lp_tesc;
+ dconf = &pconf->control.mipi_cfg;
+ esc_clk = pconf->timing.bit_rate / 8 / dsi_phy_config.lp_tesc;
factor = dconf->factor_numerator;
factor = ((factor * 1000 / dconf->factor_denominator) + 5) / 10;
@@ -231,7 +222,8 @@
" data format: %s\n"
" lp escape clock: %d.%03dMHz\n",
dconf->lane_num, dconf->bit_rate_max,
- (dconf->bit_rate / 1000000), (dconf->bit_rate % 1000000) / 1000,
+ (pconf->timing.bit_rate / 1000000),
+ (pconf->timing.bit_rate % 1000000) / 1000,
factor,
operation_mode_table[dconf->operation_mode_init],
dconf->operation_mode_init,
@@ -255,12 +247,12 @@
{
mipi_dsi_host_print_info(pconf);
- mipi_dsi_dphy_print_info(pconf->lcd_control.mipi_config);
- mipi_dsi_video_print_info(pconf->lcd_control.mipi_config);
+ mipi_dsi_dphy_print_info(pconf);
+ mipi_dsi_video_print_info(&pconf->control.mipi_cfg);
}
-int lcd_mipi_dsi_init_table_detect(const void *dt_blob, int nodeoffset,
- struct dsi_config_s *dconf, int flag)
+int lcd_mipi_dsi_init_table_detect(char *dtaddr, int nodeoffset,
+ struct dsi_config_s *dconf, int flag)
{
unsigned char cmd_size, type;
int i, j, max_len;
@@ -279,7 +271,7 @@
}
i = 0;
- propdata = (char *)fdt_getprop(dt_blob, nodeoffset, propname, NULL);
+ propdata = (char *)fdt_getprop(dtaddr, nodeoffset, propname, NULL);
if (propdata == NULL) {
LCDERR("get %s failed\n", propname);
init_table[0] = 0xff;
@@ -328,7 +320,7 @@
i += (cmd_size + 2);
}
- if (lcd_debug_print_flag)
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
mipi_dsi_init_table_print(dconf, flag);
return 0;
@@ -385,7 +377,7 @@
i += (cmd_size + 2);
}
- if (lcd_debug_print_flag)
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
mipi_dsi_init_table_print(dconf, flag);
return 0;
@@ -398,9 +390,9 @@
* int req_ack, // 1: request ack, 0: do not need ack
* int tear_en // 1: enable tear ack, 0: disable tear ack
*/
-static void mipi_dcs_set(int trans_type, int req_ack, int tear_en)
+static void mipi_dcs_set(int index, int trans_type, int req_ack, int tear_en)
{
- dsi_host_write(MIPI_DSI_DWC_CMD_MODE_CFG_OS,
+ dsi_host_write(index, MIPI_DSI_DWC_CMD_MODE_CFG_OS,
(trans_type << BIT_MAX_RD_PKT_SIZE) |
(trans_type << BIT_DCS_LW_TX) |
(trans_type << BIT_DCS_SR_0P_TX) |
@@ -418,15 +410,15 @@
if (tear_en == MIPI_DCS_ENABLE_TEAR) {
/* Enable Tear Interrupt if tear_en is valid */
- dsi_host_set_mask(MIPI_DSI_TOP_INTR_CNTL_STAT,
+ dsi_host_set_mask(index, MIPI_DSI_TOP_INTR_CNTL_STAT,
(0x1 << BIT_EDPITE_INT_EN));
/* Enable Measure Vsync */
- dsi_host_set_mask(MIPI_DSI_TOP_MEAS_CNTL,
+ dsi_host_set_mask(index, MIPI_DSI_TOP_MEAS_CNTL,
(0x1 << BIT_VSYNC_MEAS_EN) | (0x1 << BIT_TE_MEAS_EN));
}
/* Packet header settings */
- dsi_host_write(MIPI_DSI_DWC_PCKHDL_CFG_OS,
+ dsi_host_write(index, MIPI_DSI_DWC_PCKHDL_CFG_OS,
(1 << BIT_CRC_RX_EN) |
(1 << BIT_ECC_RX_EN) |
(req_ack << BIT_BTA_EN) |
@@ -439,10 +431,10 @@
* Function: set_mipi_int
* Configure relative registers for mipi interrupt
*/
-static void set_mipi_int(void)
+static void set_mipi_int(int index)
{
- dsi_host_write(MIPI_DSI_DWC_INT_MSK0_OS, 0);
- dsi_host_write(MIPI_DSI_DWC_INT_MSK1_OS, 0);
+ dsi_host_write(index, MIPI_DSI_DWC_INT_MSK0_OS, 0);
+ dsi_host_write(index, MIPI_DSI_DWC_INT_MSK1_OS, 0);
}
#endif
@@ -452,14 +444,14 @@
* to decide if the DPHY is ready
*/
#define DPHY_TIMEOUT 200000
-static void check_phy_status(void)
+static void check_phy_status(int index)
{
int i = 0;
- while (dsi_host_getb(MIPI_DSI_DWC_PHY_STATUS_OS,
+ while (dsi_host_getb(index, MIPI_DSI_DWC_PHY_STATUS_OS,
BIT_PHY_LOCK, 1) == 0) {
if (i++ >= DPHY_TIMEOUT) {
- LCDERR("%s: phy_lock timeout\n", __func__);
+ LCDERR("[%d]: %s: phy_lock timeout\n", index, __func__);
break;
}
udelay(6);
@@ -467,29 +459,26 @@
i = 0;
udelay(10);
- while (dsi_host_getb(MIPI_DSI_DWC_PHY_STATUS_OS,
+ while (dsi_host_getb(index, MIPI_DSI_DWC_PHY_STATUS_OS,
BIT_PHY_STOPSTATECLKLANE, 1) == 0) {
if (i == 0)
- LCDPR(" Waiting STOP STATE LANE\n");
+ LCDPR("[%d]: Waiting STOP STATE LANE\n", index);
if (i++ >= DPHY_TIMEOUT) {
- LCDERR("%s: lane_state timeout\n", __func__);
+ LCDERR("[%d]: %s: lane_state timeout\n", index, __func__);
break;
}
udelay(6);
}
}
-static void dsi_phy_init(struct dsi_phy_s *dphy, unsigned char lane_num)
+static void dsi_phy_init(struct aml_lcd_drv_s *pdrv, struct dsi_phy_s *dphy,
+ unsigned char lane_num)
{
- struct lcd_config_s *pconf;
- struct dsi_config_s *dconf;
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
+ int index = pdrv->index;
- pconf = lcd_drv->lcd_config;
- dconf = pconf->lcd_control.mipi_config;
/* enable phy clock. */
- dsi_phy_write(MIPI_DSI_PHY_CTRL, 0x1); /* enable DSI top clock. */
- dsi_phy_write(MIPI_DSI_PHY_CTRL,
+ dsi_phy_write(index, MIPI_DSI_PHY_CTRL, 0x1); /* enable DSI top clock. */
+ dsi_phy_write(index, MIPI_DSI_PHY_CTRL,
(1 << 0) | /* enable the DSI PLL clock . */
(1 << 7) |
/* enable pll clock which connected to
@@ -504,124 +493,133 @@
*/
(0 << 12)); /* enable the byte clock generateion. */
/* enable the divider clock out */
- dsi_phy_setb(MIPI_DSI_PHY_CTRL, 1, 9, 1);
+ dsi_phy_setb(index, MIPI_DSI_PHY_CTRL, 1, 9, 1);
/* enable the byte clock generateion. */
- dsi_phy_setb(MIPI_DSI_PHY_CTRL, 1, 12, 1);
- dsi_phy_setb(MIPI_DSI_PHY_CTRL, 1, 31, 1);
- dsi_phy_setb(MIPI_DSI_PHY_CTRL, 0, 31, 1);
+ dsi_phy_setb(index, MIPI_DSI_PHY_CTRL, 1, 12, 1);
+ dsi_phy_setb(index, MIPI_DSI_PHY_CTRL, 1, 31, 1);
+ dsi_phy_setb(index, MIPI_DSI_PHY_CTRL, 0, 31, 1);
/* 0x05210f08);//0x03211c08 */
- dsi_phy_write(MIPI_DSI_CLK_TIM,
- (dphy->clk_trail | ((dphy->clk_post+dphy->hs_trail) << 8) |
- (dphy->clk_zero << 16) | (dphy->clk_prepare << 24)));
- dsi_phy_write(MIPI_DSI_CLK_TIM1, dphy->clk_pre); /* ?? */
+ dsi_phy_write(index, MIPI_DSI_CLK_TIM,
+ (dphy->clk_trail |
+ ((dphy->clk_post + dphy->hs_trail) << 8) |
+ (dphy->clk_zero << 16) |
+ (dphy->clk_prepare << 24)));
+ dsi_phy_write(index, MIPI_DSI_CLK_TIM1, dphy->clk_pre); /* ?? */
/* 0x050f090d */
- if (dconf->bit_rate > 500000000UL) /*more than 500M*/
- dsi_phy_write(MIPI_DSI_HS_TIM,
- (dphy->hs_exit | (dphy->hs_trail << 8) |
- (dphy->hs_zero << 16) | (dphy->hs_prepare << 24)));
- else
- dsi_phy_write(MIPI_DSI_HS_TIM,
- (dphy->hs_exit | ((dphy->hs_trail / 2 + 1)<< 8) |
- (dphy->hs_zero << 16) | (dphy->hs_prepare << 24)));
-
+ if ((pdrv->config.timing.bit_rate / 1000000) > 500) { /*MAX than 500MHZ*/
+ dsi_phy_write(index, MIPI_DSI_HS_TIM,
+ (dphy->hs_exit |
+ (dphy->hs_trail << 8) |
+ (dphy->hs_zero << 16) |
+ (dphy->hs_prepare << 24)));
+ } else {
+ LCDPR("[%d]: %s: bit_rate: %dMhz\n",
+ pdrv->index, __func__,
+ (pdrv->config.timing.bit_rate / 1000000));
+ dsi_phy_write(index, MIPI_DSI_HS_TIM,
+ (dphy->hs_exit |
+ ((dphy->hs_trail / 2) << 8) |
+ (dphy->hs_zero << 16) |
+ (dphy->hs_prepare << 24)));
+ }
/* 0x4a370e0e */
- dsi_phy_write(MIPI_DSI_LP_TIM,
+ dsi_phy_write(index, MIPI_DSI_LP_TIM,
(dphy->lp_lpx | (dphy->lp_ta_sure << 8) |
(dphy->lp_ta_go << 16) | (dphy->lp_ta_get << 24)));
/* ?? //some number to reduce sim time. */
- dsi_phy_write(MIPI_DSI_ANA_UP_TIM, 0x0100);
+ dsi_phy_write(index, MIPI_DSI_ANA_UP_TIM, 0x0100);
/* 0xe20 //30d4 -> d4 to reduce sim time. */
- dsi_phy_write(MIPI_DSI_INIT_TIM, dphy->init);
+ dsi_phy_write(index, MIPI_DSI_INIT_TIM, dphy->init);
/* 0x8d40 //1E848-> 48 to reduct sim time. */
- dsi_phy_write(MIPI_DSI_WAKEUP_TIM, dphy->wakeup);
-
- dsi_phy_setb(MIPI_DSI_TEST_CTRL1, 1, 24, 1);
-
+ dsi_phy_write(index, MIPI_DSI_WAKEUP_TIM, dphy->wakeup);
/* wait for the LP analog ready. */
- dsi_phy_write(MIPI_DSI_LPOK_TIM, 0x7C);
+ dsi_phy_write(index, MIPI_DSI_LPOK_TIM, 0x7C);
/* 1/3 of the tWAKEUP. */
- dsi_phy_write(MIPI_DSI_ULPS_CHECK, 0x927C);
+ dsi_phy_write(index, MIPI_DSI_ULPS_CHECK, 0x927C);
/* phy TURN watch dog. */
- dsi_phy_write(MIPI_DSI_LP_WCHDOG, 0x1000);
+ dsi_phy_write(index, MIPI_DSI_LP_WCHDOG, 0x1000);
/* phy ESC command watch dog. */
- dsi_phy_write(MIPI_DSI_TURN_WCHDOG, 0x1000);
+ dsi_phy_write(index, MIPI_DSI_TURN_WCHDOG, 0x1000);
/* Powerup the analog circuit. */
switch (lane_num) {
case 1:
- dsi_phy_write(MIPI_DSI_CHAN_CTRL, 0x0e);
+ dsi_phy_write(index, MIPI_DSI_CHAN_CTRL, 0x0e);
break;
case 2:
- dsi_phy_write(MIPI_DSI_CHAN_CTRL, 0x0c);
+ dsi_phy_write(index, MIPI_DSI_CHAN_CTRL, 0x0c);
break;
case 3:
- dsi_phy_write(MIPI_DSI_CHAN_CTRL, 0x08);
+ dsi_phy_write(index, MIPI_DSI_CHAN_CTRL, 0x08);
break;
case 4:
default:
- dsi_phy_write(MIPI_DSI_CHAN_CTRL, 0);
+ dsi_phy_write(index, MIPI_DSI_CHAN_CTRL, 0);
break;
}
}
-static void set_dsi_phy_config(struct dsi_config_s *dconf)
+static void set_dsi_phy_config(struct aml_lcd_drv_s *pdrv)
{
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
+ struct dsi_config_s *dconf = &pdrv->config.control.mipi_cfg;
+ int index = pdrv->index;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
/* Digital */
/* Power up DSI */
- dsi_host_write(MIPI_DSI_DWC_PWR_UP_OS, 1);
+ dsi_host_write(index, MIPI_DSI_DWC_PWR_UP_OS, 1);
/* Setup Parameters of DPHY */
- dsi_host_write(MIPI_DSI_DWC_PHY_TST_CTRL1_OS, 0x00010044);/*testcode*/
- dsi_host_write(MIPI_DSI_DWC_PHY_TST_CTRL0_OS, 0x2);
- dsi_host_write(MIPI_DSI_DWC_PHY_TST_CTRL0_OS, 0x0);
- dsi_host_write(MIPI_DSI_DWC_PHY_TST_CTRL1_OS, 0x00000074);/*testwrite*/
- dsi_host_write(MIPI_DSI_DWC_PHY_TST_CTRL0_OS, 0x2);
- dsi_host_write(MIPI_DSI_DWC_PHY_TST_CTRL0_OS, 0x0);
+ dsi_host_write(index, MIPI_DSI_DWC_PHY_TST_CTRL1_OS, 0x00010044);/*testcode*/
+ dsi_host_write(index, MIPI_DSI_DWC_PHY_TST_CTRL0_OS, 0x2);
+ dsi_host_write(index, MIPI_DSI_DWC_PHY_TST_CTRL0_OS, 0x0);
+ dsi_host_write(index, MIPI_DSI_DWC_PHY_TST_CTRL1_OS, 0x00000074);/*testwrite*/
+ dsi_host_write(index, MIPI_DSI_DWC_PHY_TST_CTRL0_OS, 0x2);
+ dsi_host_write(index, MIPI_DSI_DWC_PHY_TST_CTRL0_OS, 0x0);
/* Power up D-PHY */
- dsi_host_write(MIPI_DSI_DWC_PHY_RSTZ_OS, 0xf);
+ dsi_host_write(index, MIPI_DSI_DWC_PHY_RSTZ_OS, 0xf);
/* Analog */
- dsi_phy_init(&dsi_phy_config, dconf->lane_num);
+ dsi_phy_init(pdrv, &dsi_phy_config, dconf->lane_num);
/* Check the phylock/stopstateclklane to decide if the DPHY is ready */
- check_phy_status();
+ check_phy_status(index);
/* Trigger a sync active for esc_clk */
- dsi_phy_set_mask(MIPI_DSI_PHY_CTRL, (1 << 1));
+ dsi_phy_set_mask(index, MIPI_DSI_PHY_CTRL, (1 << 1));
}
-static void startup_mipi_dsi_host(void)
+static void startup_mipi_dsi_host(int index)
{
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", index, __func__);
/* Enable dwc mipi_dsi_host's clock */
- dsi_host_set_mask(MIPI_DSI_TOP_CNTL, ((1 << 4) | (1 << 5) | (0 << 6)));
+ dsi_host_set_mask(index, MIPI_DSI_TOP_CNTL, ((1 << 4) | (1 << 5) | (0 << 6)));
/* mipi_dsi_host's reset */
- dsi_host_set_mask(MIPI_DSI_TOP_SW_RESET, 0xf);
+ dsi_host_set_mask(index, MIPI_DSI_TOP_SW_RESET, 0xf);
/* Release mipi_dsi_host's reset */
- dsi_host_clr_mask(MIPI_DSI_TOP_SW_RESET, 0xf);
+ dsi_host_clr_mask(index, MIPI_DSI_TOP_SW_RESET, 0xf);
/* Enable dwc mipi_dsi_host's clock */
- dsi_host_set_mask(MIPI_DSI_TOP_CLK_CNTL, 0x3);
+ dsi_host_set_mask(index, MIPI_DSI_TOP_CLK_CNTL, 0x3);
- dsi_host_write(MIPI_DSI_TOP_MEM_PD, 0);
+ dsi_host_write(index, MIPI_DSI_TOP_MEM_PD, 0);
- mdelay(2);
+ mdelay(10);
}
-static void mipi_dsi_lpclk_ctrl(struct dsi_config_s *dconf)
+static void mipi_dsi_lpclk_ctrl(int index, struct dsi_config_s *dconf)
{
unsigned int lpclk;
/* when lpclk = 1, enable clk lp state */
lpclk = (dconf->clk_always_hs) ? 0 : 1;
- dsi_host_write(MIPI_DSI_DWC_LPCLK_CTRL_OS,
+ dsi_host_write(index, MIPI_DSI_DWC_LPCLK_CTRL_OS,
(lpclk << BIT_AUTOCLKLANE_CTRL) |
(0x1 << BIT_TXREQUESTCLKHS));
}
@@ -634,14 +632,15 @@
* p, //lcd config
*/
static void set_mipi_dsi_host(unsigned int vcid, unsigned int chroma_subsample,
- unsigned int operation_mode, struct lcd_config_s *p)
+ unsigned int operation_mode, struct aml_lcd_drv_s *pdrv)
{
unsigned int dpi_data_format, venc_data_width;
unsigned int lane_num, vid_mode_type;
unsigned int temp;
struct dsi_config_s *dconf;
+ int index = pdrv->index;
- dconf = p->lcd_control.mipi_config;
+ dconf = &pdrv->config.control.mipi_cfg;
venc_data_width = dconf->venc_data_width;
dpi_data_format = dconf->dpi_data_format;
lane_num = (unsigned int)(dconf->lane_num);
@@ -652,34 +651,34 @@
/* ----------------------------------------------------- */
/* 1, Configure Lane number and phy stop wait time */
if (dsi_phy_config.state_change == 2) {
- dsi_host_write(MIPI_DSI_DWC_PHY_IF_CFG_OS,
+ dsi_host_write(index, MIPI_DSI_DWC_PHY_IF_CFG_OS,
(0x28 << BIT_PHY_STOP_WAIT_TIME) |
((lane_num-1) << BIT_N_LANES));
} else {
- dsi_host_write(MIPI_DSI_DWC_PHY_IF_CFG_OS,
+ dsi_host_write(index, MIPI_DSI_DWC_PHY_IF_CFG_OS,
(1 << BIT_PHY_STOP_WAIT_TIME) |
((lane_num-1) << BIT_N_LANES));
}
/* 2.1, Configure Virtual channel settings */
- dsi_host_write(MIPI_DSI_DWC_DPI_VCID_OS, vcid);
+ dsi_host_write(index, MIPI_DSI_DWC_DPI_VCID_OS, vcid);
/* 2.2, Configure Color format */
- dsi_host_write(MIPI_DSI_DWC_DPI_COLOR_CODING_OS,
+ dsi_host_write(index, MIPI_DSI_DWC_DPI_COLOR_CODING_OS,
(((dpi_data_format == COLOR_18BIT_CFG_2) ?
1 : 0) << BIT_LOOSELY18_EN) |
(dpi_data_format << BIT_DPI_COLOR_CODING));
/* 2.2.1 Configure Set color format for DPI register */
- temp = (dsi_host_read(MIPI_DSI_TOP_CNTL) &
+ temp = (dsi_host_read(index, MIPI_DSI_TOP_CNTL) &
~(0xf<<BIT_DPI_COLOR_MODE) &
~(0x7<<BIT_IN_COLOR_MODE) &
~(0x3<<BIT_CHROMA_SUBSAMPLE));
- dsi_host_write(MIPI_DSI_TOP_CNTL,
+ dsi_host_write(index, MIPI_DSI_TOP_CNTL,
(temp |
(dpi_data_format << BIT_DPI_COLOR_MODE) |
(venc_data_width << BIT_IN_COLOR_MODE) |
(chroma_subsample << BIT_CHROMA_SUBSAMPLE)));
/* 2.3 Configure Signal polarity */
- dsi_host_write(MIPI_DSI_DWC_DPI_CFG_POL_OS,
+ dsi_host_write(index, MIPI_DSI_DWC_DPI_CFG_POL_OS,
(0x0 << BIT_COLORM_ACTIVE_LOW) |
(0x0 << BIT_SHUTD_ACTIVE_LOW) |
(0 << BIT_HSYNC_ACTIVE_LOW) |
@@ -688,7 +687,7 @@
if (operation_mode == OPERATION_VIDEO_MODE) {
/* 3.1 Configure Low power and video mode type settings */
- dsi_host_write(MIPI_DSI_DWC_VID_MODE_CFG_OS,
+ dsi_host_write(index, MIPI_DSI_DWC_VID_MODE_CFG_OS,
(1 << BIT_LP_HFP_EN) | /* enalbe lp */
(1 << BIT_LP_HBP_EN) | /* enalbe lp */
(1 << BIT_LP_VCAT_EN) | /* enalbe lp */
@@ -702,20 +701,20 @@
(vid_mode_type << BIT_VID_MODE_TYPE));
/* burst non burst mode */
/* [23:16]outvact, [7:0]invact */
- dsi_host_write(MIPI_DSI_DWC_DPI_LP_CMD_TIM_OS,
+ dsi_host_write(index, MIPI_DSI_DWC_DPI_LP_CMD_TIM_OS,
(4 << 16) | (4 << 0));
#if 0
/* 3.2 Configure video packet size settings */
if (vid_mode_type == BURST_MODE) {
/* should be one line in pixels, such as 480/240... */
- dsi_host_write(MIPI_DSI_DWC_VID_PKT_SIZE_OS,
+ dsi_host_write(index, MIPI_DSI_DWC_VID_PKT_SIZE_OS,
p->lcd_basic.h_active);
} else { /* non-burst mode */
/* in unit of pixels,
* (pclk period/byte clk period)*num_of_lane
* should be integer
*/
- dsi_host_write(MIPI_DSI_DWC_VID_PKT_SIZE_OS,
+ dsi_host_write(index, MIPI_DSI_DWC_VID_PKT_SIZE_OS,
dsi_vconf.pixel_per_chunk);
}
@@ -723,36 +722,36 @@
* for one line
*/
if (vid_mode_type == BURST_MODE) {
- dsi_host_write(MIPI_DSI_DWC_VID_NUM_CHUNKS_OS, 0);
- dsi_host_write(MIPI_DSI_DWC_VID_NULL_SIZE_OS, 0);
+ dsi_host_write(index, MIPI_DSI_DWC_VID_NUM_CHUNKS_OS, 0);
+ dsi_host_write(index, MIPI_DSI_DWC_VID_NULL_SIZE_OS, 0);
} else { /* non burst mode */
/* HACT/VID_PKT_SIZE */
- dsi_host_write(MIPI_DSI_DWC_VID_NUM_CHUNKS_OS,
+ dsi_host_write(index, MIPI_DSI_DWC_VID_NUM_CHUNKS_OS,
dsi_vconf.vid_num_chunks);
/* video null size */
- dsi_host_write(MIPI_DSI_DWC_VID_NULL_SIZE_OS,
+ dsi_host_write(index, MIPI_DSI_DWC_VID_NULL_SIZE_OS,
dsi_vconf.vid_null_size);
}
#else
/* 3.2 Configure video packet size settings */
- dsi_host_write(MIPI_DSI_DWC_VID_PKT_SIZE_OS,
+ dsi_host_write(index, MIPI_DSI_DWC_VID_PKT_SIZE_OS,
dsi_vconf.pixel_per_chunk);
- dsi_host_write(MIPI_DSI_DWC_VID_NUM_CHUNKS_OS,
+ dsi_host_write(index, MIPI_DSI_DWC_VID_NUM_CHUNKS_OS,
dsi_vconf.vid_num_chunks);
- dsi_host_write(MIPI_DSI_DWC_VID_NULL_SIZE_OS,
+ dsi_host_write(index, MIPI_DSI_DWC_VID_NULL_SIZE_OS,
dsi_vconf.vid_null_size);
#endif
/* 4 Configure the video relative parameters according to
* the output type
*/
/* include horizontal timing and vertical line */
- dsi_host_write(MIPI_DSI_DWC_VID_HLINE_TIME_OS, dsi_vconf.hline);
- dsi_host_write(MIPI_DSI_DWC_VID_HSA_TIME_OS, dsi_vconf.hsa);
- dsi_host_write(MIPI_DSI_DWC_VID_HBP_TIME_OS, dsi_vconf.hbp);
- dsi_host_write(MIPI_DSI_DWC_VID_VSA_LINES_OS, dsi_vconf.vsa);
- dsi_host_write(MIPI_DSI_DWC_VID_VBP_LINES_OS, dsi_vconf.vbp);
- dsi_host_write(MIPI_DSI_DWC_VID_VFP_LINES_OS, dsi_vconf.vfp);
- dsi_host_write(MIPI_DSI_DWC_VID_VACTIVE_LINES_OS,
+ dsi_host_write(index, MIPI_DSI_DWC_VID_HLINE_TIME_OS, dsi_vconf.hline);
+ dsi_host_write(index, MIPI_DSI_DWC_VID_HSA_TIME_OS, dsi_vconf.hsa);
+ dsi_host_write(index, MIPI_DSI_DWC_VID_HBP_TIME_OS, dsi_vconf.hbp);
+ dsi_host_write(index, MIPI_DSI_DWC_VID_VSA_LINES_OS, dsi_vconf.vsa);
+ dsi_host_write(index, MIPI_DSI_DWC_VID_VBP_LINES_OS, dsi_vconf.vbp);
+ dsi_host_write(index, MIPI_DSI_DWC_VID_VFP_LINES_OS, dsi_vconf.vfp);
+ dsi_host_write(index, MIPI_DSI_DWC_VID_VACTIVE_LINES_OS,
dsi_vconf.vact);
} /* operation_mode == OPERATION_VIDEO_MODE */
@@ -761,11 +760,11 @@
/* ----------------------------------------------------- */
/* Inner clock divider settings */
- dsi_host_write(MIPI_DSI_DWC_CLKMGR_CFG_OS,
+ dsi_host_write(index, MIPI_DSI_DWC_CLKMGR_CFG_OS,
(0x1 << BIT_TO_CLK_DIV) |
(dsi_phy_config.lp_tesc << BIT_TX_ESC_CLK_DIV));
/* Packet header settings //move to mipi_dcs_set */
- /* dsi_host_write(MIPI_DSI_DWC_PCKHDL_CFG_OS,
+ /* dsi_host_write(index, MIPI_DSI_DWC_PCKHDL_CFG_OS,
* (1 << BIT_CRC_RX_EN) |
* (1 << BIT_ECC_RX_EN) |
* (0 << BIT_BTA_EN) |
@@ -773,46 +772,46 @@
* (0 << BIT_EOTP_TX_EN) );
*/
/* operation mode setting: video/command mode */
- dsi_host_write(MIPI_DSI_DWC_MODE_CFG_OS, operation_mode);
+ dsi_host_write(index, MIPI_DSI_DWC_MODE_CFG_OS, operation_mode);
/* Phy Timer */
if (dsi_phy_config.state_change == 2)
- dsi_host_write(MIPI_DSI_DWC_PHY_TMR_CFG_OS, 0x03320000);
+ dsi_host_write(index, MIPI_DSI_DWC_PHY_TMR_CFG_OS, 0x03320000);
else
- dsi_host_write(MIPI_DSI_DWC_PHY_TMR_CFG_OS, 0x090f0000);
+ dsi_host_write(index, MIPI_DSI_DWC_PHY_TMR_CFG_OS, 0x090f0000);
if (dsi_phy_config.state_change == 2)
- dsi_host_write(MIPI_DSI_DWC_PHY_TMR_LPCLK_CFG_OS, 0x870025);
+ dsi_host_write(index, MIPI_DSI_DWC_PHY_TMR_LPCLK_CFG_OS, 0x870025);
else
- dsi_host_write(MIPI_DSI_DWC_PHY_TMR_LPCLK_CFG_OS, 0x260017);
+ dsi_host_write(index, MIPI_DSI_DWC_PHY_TMR_LPCLK_CFG_OS, 0x260017);
}
/* *************************************************************
* mipi dsi command support
*/
-static inline void print_mipi_cmd_status(int cnt, unsigned int status)
+static inline void print_mipi_cmd_status(int index, int cnt, unsigned int status)
{
if (cnt == 0) {
- LCDPR("cmd error: status=0x%04x, int0=0x%06x, int1=0x%06x\n",
- status,
- dsi_host_read(MIPI_DSI_DWC_INT_ST0_OS),
- dsi_host_read(MIPI_DSI_DWC_INT_ST1_OS));
+ LCDPR("[%d]: cmd error: status=0x%04x, int0=0x%06x, int1=0x%06x\n",
+ index, status,
+ dsi_host_read(index, MIPI_DSI_DWC_INT_ST0_OS),
+ dsi_host_read(index, MIPI_DSI_DWC_INT_ST1_OS));
}
}
#ifdef DSI_CMD_READ_VALID
-static void dsi_bta_control(int en)
+static void dsi_bta_control(int index, int en)
{
if (en) {
- dsi_host_setb(MIPI_DSI_DWC_CMD_MODE_CFG_OS,
+ dsi_host_setb(index, MIPI_DSI_DWC_CMD_MODE_CFG_OS,
MIPI_DSI_DCS_REQ_ACK, BIT_ACK_RQST_EN, 1);
- dsi_host_setb(MIPI_DSI_DWC_PCKHDL_CFG_OS,
+ dsi_host_setb(index, MIPI_DSI_DWC_PCKHDL_CFG_OS,
MIPI_DSI_DCS_REQ_ACK, BIT_BTA_EN, 1);
} else {
- dsi_host_setb(MIPI_DSI_DWC_PCKHDL_CFG_OS,
+ dsi_host_setb(index, MIPI_DSI_DWC_PCKHDL_CFG_OS,
MIPI_DSI_DCS_NO_ACK, BIT_BTA_EN, 1);
- dsi_host_setb(MIPI_DSI_DWC_CMD_MODE_CFG_OS,
+ dsi_host_setb(index, MIPI_DSI_DWC_CMD_MODE_CFG_OS,
MIPI_DSI_DCS_NO_ACK, BIT_ACK_RQST_EN, 1);
}
}
@@ -821,14 +820,14 @@
* Function: generic_if_rd
* Generic interface read, address has to be MIPI_DSI_DWC_GEN_PLD_DATA_OS
*/
-static unsigned int generic_if_rd(unsigned int address)
+static unsigned int generic_if_rd(int index, unsigned int address)
{
unsigned int data_out;
if (address != MIPI_DSI_DWC_GEN_PLD_DATA_OS)
- LCDERR(" Error Address : %x\n", address);
+ LCDERR("[%d]: Error Address : %x\n", index, address);
- data_out = dsi_host_read(address);
+ data_out = dsi_host_read(index, address);
return data_out;
}
#endif
@@ -840,17 +839,17 @@
* MIPI_DSI_DWC_GEN_HDR_OS,
* MIPI_DSI_DWC_GEN_VCID_OS
*/
-static unsigned int generic_if_wr(unsigned int address, unsigned int data_in)
+static unsigned int generic_if_wr(int index, unsigned int address, unsigned int data_in)
{
if ((address != MIPI_DSI_DWC_GEN_HDR_OS) &&
(address != MIPI_DSI_DWC_GEN_PLD_DATA_OS)) {
- LCDERR(" Error Address : 0x%x\n", address);
+ LCDERR("[%d]: Error Address : 0x%x\n", index, address);
}
- if (lcd_debug_print_flag)
- LCDPR("address 0x%x = 0x%08x\n", address, data_in);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: address 0x%x = 0x%08x\n", index, address, data_in);
- dsi_host_write(address, data_in);
+ dsi_host_write(index, address, data_in);
return 0;
}
@@ -859,7 +858,7 @@
* Function: wait_bta_ack
* Poll to check if the BTA ack is finished
*/
-static int wait_bta_ack(void)
+static int wait_bta_ack(int index)
{
unsigned int phy_status;
int i;
@@ -869,10 +868,10 @@
do {
udelay(10);
i--;
- phy_status = dsi_host_read(MIPI_DSI_DWC_PHY_STATUS_OS);
+ phy_status = dsi_host_read(index, MIPI_DSI_DWC_PHY_STATUS_OS);
} while ((((phy_status & 0x2) >> BIT_PHY_DIRECTION) == 0x0) && (i > 0));
if (i == 0) {
- LCDERR("phy direction error: RX\n");
+ LCDERR("[%d]: phy direction error: RX\n", index);
return -1;
}
@@ -881,10 +880,10 @@
do {
udelay(10);
i--;
- phy_status = dsi_host_read(MIPI_DSI_DWC_PHY_STATUS_OS);
+ phy_status = dsi_host_read(index, MIPI_DSI_DWC_PHY_STATUS_OS);
} while ((((phy_status & 0x2) >> BIT_PHY_DIRECTION) == 0x1) && (i > 0));
if (i == 0) {
- LCDERR("phy direction error: TX\n");
+ LCDERR("[%d]: phy direction error: TX\n", index);
return -1;
}
@@ -895,7 +894,7 @@
* Function: wait_cmd_fifo_empty
* Poll to check if the generic command fifo is empty
*/
-static int wait_cmd_fifo_empty(void)
+static int wait_cmd_fifo_empty(int index)
{
unsigned int cmd_status;
int i = CMD_TIMEOUT_CNT;
@@ -903,13 +902,13 @@
do {
udelay(10);
i--;
- cmd_status = dsi_host_getb(MIPI_DSI_DWC_CMD_PKT_STATUS_OS,
+ cmd_status = dsi_host_getb(index, MIPI_DSI_DWC_CMD_PKT_STATUS_OS,
BIT_GEN_CMD_EMPTY, 1);
} while ((cmd_status != 0x1) && (i > 0));
if (cmd_status == 0) {
- cmd_status = dsi_host_read(MIPI_DSI_DWC_CMD_PKT_STATUS_OS);
- print_mipi_cmd_status(i, cmd_status);
+ cmd_status = dsi_host_read(index, MIPI_DSI_DWC_CMD_PKT_STATUS_OS);
+ print_mipi_cmd_status(index, i, cmd_status);
return -1;
}
@@ -921,26 +920,26 @@
* Function: wait_for_generic_read_response
* Wait for generic read response
*/
-static unsigned int wait_for_generic_read_response(void)
+static unsigned int wait_for_generic_read_response(int index)
{
unsigned int timeout, phy_status, data_out;
- phy_status = dsi_host_read(MIPI_DSI_DWC_PHY_STATUS_OS);
+ phy_status = dsi_host_read(index, MIPI_DSI_DWC_PHY_STATUS_OS);
for (timeout = 0; timeout < 50; timeout++) {
if (((phy_status & 0x40) >> BIT_PHY_RXULPSESC0LANE) == 0x0)
break;
- phy_status = dsi_host_read(MIPI_DSI_DWC_PHY_STATUS_OS);
+ phy_status = dsi_host_read(index, MIPI_DSI_DWC_PHY_STATUS_OS);
udelay(1);
}
- phy_status = dsi_host_read(MIPI_DSI_DWC_PHY_STATUS_OS);
+ phy_status = dsi_host_read(index, MIPI_DSI_DWC_PHY_STATUS_OS);
for (timeout = 0; timeout < 50; timeout++) {
if (((phy_status & 0x40) >> BIT_PHY_RXULPSESC0LANE) == 0x1)
break;
- phy_status = dsi_host_read(MIPI_DSI_DWC_PHY_STATUS_OS);
+ phy_status = dsi_host_read(index, MIPI_DSI_DWC_PHY_STATUS_OS);
udelay(1);
}
- data_out = dsi_host_read(MIPI_DSI_DWC_GEN_PLD_DATA_OS);
+ data_out = dsi_host_read(index, MIPI_DSI_DWC_GEN_PLD_DATA_OS);
return data_out;
}
@@ -959,7 +958,7 @@
/* lcd_print(" para is %x, dcs_command is %x\n", para, dcs_command); */
/* lcd_print(" vc_id %x, data_type is %x\n", vc_id, data_type); */
- generic_if_wr(MIPI_DSI_DWC_GEN_HDR_OS,
+ generic_if_wr(index, MIPI_DSI_DWC_GEN_HDR_OS,
((0 << BIT_GEN_WC_MSBYTE) |
(((unsigned int)dcs_command) << BIT_GEN_WC_LSBYTE) |
(((unsigned int)vc_id) << BIT_GEN_VC) |
@@ -971,26 +970,26 @@
}
#endif
-static void dsi_set_max_return_pkt_size(struct dsi_cmd_request_s *req)
+static void dsi_set_max_return_pkt_size(int index, struct dsi_cmd_request_s *req)
{
unsigned int d_para[2];
d_para[0] = (unsigned int)(req->payload[2] & 0xff);
d_para[1] = (unsigned int)(req->payload[3] & 0xff);
dsi_rx_n = (unsigned short)((d_para[1] << 8) | d_para[0]);
- generic_if_wr(MIPI_DSI_DWC_GEN_HDR_OS,
+ generic_if_wr(index, MIPI_DSI_DWC_GEN_HDR_OS,
((d_para[1] << BIT_GEN_WC_MSBYTE) |
(d_para[0] << BIT_GEN_WC_LSBYTE) |
(((unsigned int)req->vc_id) << BIT_GEN_VC) |
(DT_SET_MAX_RET_PKT_SIZE << BIT_GEN_DT)));
if (req->req_ack == MIPI_DSI_DCS_REQ_ACK)
- wait_bta_ack();
+ wait_bta_ack(index);
else if (req->req_ack == MIPI_DSI_DCS_NO_ACK)
- wait_cmd_fifo_empty();
+ wait_cmd_fifo_empty(index);
}
#ifdef DSI_CMD_READ_VALID
-static int dsi_generic_read_packet(struct dsi_cmd_request_s *req,
+static int dsi_generic_read_packet(int index, struct dsi_cmd_request_s *req,
unsigned char *r_data)
{
unsigned int d_para[2], read_data;
@@ -1017,20 +1016,20 @@
}
if (MIPI_DSI_DCS_ACK_TYPE == MIPI_DSI_DCS_NO_ACK)
- dsi_bta_control(1);
- generic_if_wr(MIPI_DSI_DWC_GEN_HDR_OS,
+ dsi_bta_control(index, 1);
+ generic_if_wr(index, MIPI_DSI_DWC_GEN_HDR_OS,
((d_para[1] << BIT_GEN_WC_MSBYTE) |
(d_para[0] << BIT_GEN_WC_LSBYTE) |
(((unsigned int)req->vc_id) << BIT_GEN_VC) |
(((unsigned int)req->data_type) << BIT_GEN_DT)));
- ret = wait_bta_ack();
+ ret = wait_bta_ack(index);
if (ret)
return -1;
i = 0;
done = 0;
while (done == 0) {
- read_data = generic_if_rd(MIPI_DSI_DWC_GEN_PLD_DATA_OS);
+ read_data = generic_if_rd(index, MIPI_DSI_DWC_GEN_PLD_DATA_OS);
for (j = 0; j < 4; j++) {
if (i < dsi_rx_n) {
r_data[i] = (unsigned char)
@@ -1043,12 +1042,12 @@
}
}
if (MIPI_DSI_DCS_ACK_TYPE == MIPI_DSI_DCS_NO_ACK)
- dsi_bta_control(0);
+ dsi_bta_control(index, 0);
return dsi_rx_n;
}
-static int dsi_dcs_read_packet(struct dsi_cmd_request_s *req,
+static int dsi_dcs_read_packet(int index, struct dsi_cmd_request_s *req,
unsigned char *r_data)
{
unsigned int d_command, read_data;
@@ -1058,20 +1057,20 @@
d_command = ((unsigned int)req->payload[2]) & 0xff;
if (MIPI_DSI_DCS_ACK_TYPE == MIPI_DSI_DCS_NO_ACK)
- dsi_bta_control(1);
- generic_if_wr(MIPI_DSI_DWC_GEN_HDR_OS,
+ dsi_bta_control(index, 1);
+ generic_if_wr(index, MIPI_DSI_DWC_GEN_HDR_OS,
((0 << BIT_GEN_WC_MSBYTE) |
(d_command << BIT_GEN_WC_LSBYTE) |
(((unsigned int)req->vc_id) << BIT_GEN_VC) |
(((unsigned int)req->data_type) << BIT_GEN_DT)));
- ret = wait_bta_ack();
+ ret = wait_bta_ack(index);
if (ret)
return -1;
i = 0;
done = 0;
while (done == 0) {
- read_data = generic_if_rd(MIPI_DSI_DWC_GEN_PLD_DATA_OS);
+ read_data = generic_if_rd(index, MIPI_DSI_DWC_GEN_PLD_DATA_OS);
for (j = 0; j < 4; j++) {
if (i < dsi_rx_n) {
r_data[i] = (unsigned char)
@@ -1085,7 +1084,7 @@
}
if (MIPI_DSI_DCS_ACK_TYPE == MIPI_DSI_DCS_NO_ACK)
- dsi_bta_control(0);
+ dsi_bta_control(index, 0);
return dsi_rx_n;
}
@@ -1098,7 +1097,7 @@
DT_GEN_SHORT_WR_1,
DT_GEN_SHORT_WR_2,
*/
-static int dsi_generic_write_short_packet(struct dsi_cmd_request_s *req)
+static int dsi_generic_write_short_packet(int index, struct dsi_cmd_request_s *req)
{
unsigned int d_para[2];
int ret = 0;
@@ -1122,15 +1121,15 @@
break;
}
- generic_if_wr(MIPI_DSI_DWC_GEN_HDR_OS,
+ generic_if_wr(index, MIPI_DSI_DWC_GEN_HDR_OS,
((d_para[1] << BIT_GEN_WC_MSBYTE) |
(d_para[0] << BIT_GEN_WC_LSBYTE) |
(((unsigned int)req->vc_id) << BIT_GEN_VC) |
(((unsigned int)req->data_type) << BIT_GEN_DT)));
if (req->req_ack == MIPI_DSI_DCS_REQ_ACK)
- ret = wait_bta_ack();
+ ret = wait_bta_ack(index);
else if (req->req_ack == MIPI_DSI_DCS_NO_ACK)
- ret = wait_cmd_fifo_empty();
+ ret = wait_cmd_fifo_empty(index);
return ret;
}
@@ -1140,7 +1139,7 @@
* DCS Write Short Packet with Generic Interface
* Supported Data Type: DT_DCS_SHORT_WR_0, DT_DCS_SHORT_WR_1,
*/
-static int dsi_dcs_write_short_packet(struct dsi_cmd_request_s *req)
+static int dsi_dcs_write_short_packet(int index, struct dsi_cmd_request_s *req)
{
unsigned int d_command, d_para;
int ret = 0;
@@ -1149,15 +1148,15 @@
d_para = (req->pld_count < 2) ?
0 : (((unsigned int)req->payload[3]) & 0xff);
- generic_if_wr(MIPI_DSI_DWC_GEN_HDR_OS,
+ generic_if_wr(index, MIPI_DSI_DWC_GEN_HDR_OS,
((d_para << BIT_GEN_WC_MSBYTE) |
(d_command << BIT_GEN_WC_LSBYTE) |
(((unsigned int)req->vc_id) << BIT_GEN_VC) |
(((unsigned int)req->data_type) << BIT_GEN_DT)));
if (req->req_ack == MIPI_DSI_DCS_REQ_ACK)
- ret = wait_bta_ack();
+ ret = wait_bta_ack(index);
else if (req->req_ack == MIPI_DSI_DCS_NO_ACK)
- ret = wait_cmd_fifo_empty();
+ ret = wait_cmd_fifo_empty(index);
return ret;
}
@@ -1167,7 +1166,7 @@
* Write Long Packet with Generic Interface
* Supported Data Type: DT_GEN_LONG_WR, DT_DCS_LONG_WR
*/
-static int dsi_write_long_packet(struct dsi_cmd_request_s *req)
+static int dsi_write_long_packet(int index, struct dsi_cmd_request_s *req)
{
unsigned int d_command, payload_data, header_data;
unsigned int cmd_status;
@@ -1199,20 +1198,20 @@
do {
udelay(10);
j--;
- cmd_status = dsi_host_read(
+ cmd_status = dsi_host_read(index,
MIPI_DSI_DWC_CMD_PKT_STATUS_OS);
} while ((((cmd_status >> BIT_GEN_PLD_W_FULL) & 0x1) ==
0x1) && (j > 0));
- print_mipi_cmd_status(j, cmd_status);
+ print_mipi_cmd_status(index, j, cmd_status);
}
/* Use direct memory write to save time when in
* WRITE_MEMORY_CONTINUE
*/
if (d_command == DCS_WRITE_MEMORY_CONTINUE) {
- dsi_host_write(MIPI_DSI_DWC_GEN_PLD_DATA_OS,
+ dsi_host_write(index, MIPI_DSI_DWC_GEN_PLD_DATA_OS,
payload_data);
} else {
- generic_if_wr(MIPI_DSI_DWC_GEN_PLD_DATA_OS,
+ generic_if_wr(index, MIPI_DSI_DWC_GEN_PLD_DATA_OS,
payload_data);
}
}
@@ -1222,19 +1221,19 @@
do {
udelay(10);
j--;
- cmd_status = dsi_host_read(MIPI_DSI_DWC_CMD_PKT_STATUS_OS);
+ cmd_status = dsi_host_read(index, MIPI_DSI_DWC_CMD_PKT_STATUS_OS);
} while ((((cmd_status >> BIT_GEN_CMD_FULL) & 0x1) == 0x1) && (j > 0));
- print_mipi_cmd_status(j, cmd_status);
+ print_mipi_cmd_status(index, j, cmd_status);
/* Write Header Register */
/* include command */
header_data = ((((unsigned int)req->pld_count) << BIT_GEN_WC_LSBYTE) |
(((unsigned int)req->vc_id) << BIT_GEN_VC) |
(((unsigned int)req->data_type) << BIT_GEN_DT));
- generic_if_wr(MIPI_DSI_DWC_GEN_HDR_OS, header_data);
+ generic_if_wr(index, MIPI_DSI_DWC_GEN_HDR_OS, header_data);
if (req->req_ack == MIPI_DSI_DCS_REQ_ACK)
- ret = wait_bta_ack();
+ ret = wait_bta_ack(index);
else if (req->req_ack == MIPI_DSI_DCS_NO_ACK)
- ret = wait_cmd_fifo_empty();
+ ret = wait_cmd_fifo_empty(index);
return ret;
}
@@ -1246,7 +1245,7 @@
* DT_DCS_RD_0
* Return: data count, -1 for error
*/
-int dsi_read_single(unsigned char *payload, unsigned char *rd_data,
+int dsi_read_single(int index, unsigned char *payload, unsigned char *rd_data,
unsigned int rd_byte_len)
{
int num = 0;
@@ -1265,7 +1264,7 @@
dsi_cmd_req.payload = &temp[0];
dsi_cmd_req.pld_count = 2;
dsi_cmd_req.req_ack = req_ack;
- dsi_set_max_return_pkt_size(&dsi_cmd_req);
+ dsi_set_max_return_pkt_size(index, &dsi_cmd_req);
/* payload struct: */
/* data_type, data_cnt, command, parameters... */
@@ -1279,85 +1278,85 @@
case DT_GEN_RD_0:
case DT_GEN_RD_1:
case DT_GEN_RD_2:
- num = dsi_generic_read_packet(&dsi_cmd_req, rd_data);
+ num = dsi_generic_read_packet(index, &dsi_cmd_req, rd_data);
break;
case DT_DCS_RD_0:
- num = dsi_dcs_read_packet(&dsi_cmd_req, rd_data);
+ num = dsi_dcs_read_packet(index, &dsi_cmd_req, rd_data);
break;
default:
- LCDPR("read un-support data_type: 0x%02x\n",
- dsi_cmd_req.data_type);
+ LCDPR("[%d]: read un-support data_type: 0x%02x\n",
+ index, dsi_cmd_req.data_type);
break;
}
if (num < 0)
- LCDERR("mipi-dsi read error\n");
+ LCDERR("[%d]: mipi-dsi read error\n", index);
return num;
}
#else
-int dsi_read_single(unsigned char *payload, unsigned char *rd_data,
+int dsi_read_single(int index, unsigned char *payload, unsigned char *rd_data,
unsigned int rd_byte_len)
{
- LCDPR("Don't support mipi-dsi read command\n");
+ LCDPR("[%d]: Don't support mipi-dsi read command\n", index);
return -1;
}
#endif
-static int mipi_dsi_check_state(unsigned char reg, unsigned char cnt)
+static int mipi_dsi_check_state(struct aml_lcd_drv_s *pdrv,
+ unsigned char reg, unsigned char cnt)
{
int ret = 0, i;
unsigned char *rd_data;
unsigned char payload[3] = {DT_GEN_RD_1, 1, 0x04};
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
struct dsi_config_s *dconf;
- unsigned int ddic_reg = 0;
- dconf = lcd_drv->lcd_config->lcd_control.mipi_config;
+ unsigned int offset;
+ int index = pdrv->index;
+
+ dconf = &pdrv->config.control.mipi_cfg;
if (dconf->check_en == 0)
return 0;
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
rd_data = (unsigned char *)malloc(sizeof(unsigned char) * cnt);
- if (rd_data == NULL) {
- LCDERR("%s: rd_data malloc error\n", __func__);
+ if (!rd_data) {
+ LCDERR("[%d]: %s: rd_data malloc error\n", pdrv->index, __func__);
return 0;
}
+ offset = pdrv->data->offset_venc_if[pdrv->index];
+
payload[2] = reg;
- ret = dsi_read_single(payload, rd_data, cnt);
+ ret = dsi_read_single(index, payload, rd_data, cnt);
if (ret < 0)
goto mipi_dsi_check_state_err;
if (ret > cnt) {
- LCDERR("%s: read back cnt is wrong\n", __func__);
+ LCDERR("[%d]: %s: read back cnt is wrong\n", pdrv->index, __func__);
goto mipi_dsi_check_state_err;
}
- pr_info("read reg 0x%02x: ", reg);
+ printf("read reg 0x%02x: ", reg);
for (i = 0; i < ret; i++) {
- ddic_reg |= (rd_data[i] << ((ret - i-1)*8));
if (i == 0)
- pr_info("0x%02x", rd_data[i]);
+ printf("0x%02x", rd_data[i]);
else
- pr_info(",0x%02x", rd_data[i]);
+ printf(",0x%02x", rd_data[i]);
}
- pr_info("\n");
+ printf("\n");
- /*ret value range:0-3*/
- ddic_reg |= (ret << 24);
- env_set_hex("ddic_reg", ddic_reg);
dconf->check_state = 1;
- lcd_vcbus_setb(L_VCOM_VS_ADDR, 1, 12, 1);
- lcd_drv->lcd_config->retry_enable_flag = 0;
- LCDPR("%s: %d\n", __func__, dconf->check_state);
+ lcd_vcbus_setb(L_VCOM_VS_ADDR + offset, 1, 12, 1);
+ pdrv->config.retry_enable_flag = 0;
+ LCDPR("[%d]: %s: %d\n", pdrv->index, __func__, dconf->check_state);
free(rd_data);
return 0;
mipi_dsi_check_state_err:
dconf->check_state = 0;
- lcd_vcbus_setb(L_VCOM_VS_ADDR, 0, 12, 1);
- LCDPR("%s: %d\n", __func__, dconf->check_state);
- lcd_drv->lcd_config->retry_enable_flag = 1;
+ lcd_vcbus_setb(L_VCOM_VS_ADDR + offset, 0, 12, 1);
+ LCDPR("[%d]: %s: %d\n", pdrv->index, __func__, dconf->check_state);
+ pdrv->config.retry_enable_flag = 1;
free(rd_data);
return -1;
}
@@ -1372,7 +1371,7 @@
* DT_DCS_RD_0
* Return: command number
*/
-int dsi_write_cmd(unsigned char *payload)
+int dsi_write_cmd(struct aml_lcd_drv_s *pdrv, unsigned char *payload)
{
int i = 0, j = 0, step = 0;
unsigned char cmd_size;
@@ -1383,7 +1382,15 @@
struct dsi_cmd_request_s dsi_cmd_req;
unsigned char vc_id = MIPI_DSI_VIRTUAL_CHAN_ID;
unsigned int req_ack = MIPI_DSI_DCS_ACK_TYPE;
- int delay_ms, ret = 0;
+ char *str;
+ int gpio, delay_ms, ret = 0;
+ int index;
+
+ if (!pdrv) {
+ LCDERR("%s: pdrv is null\n", __func__);
+ return 0;
+ }
+ index = pdrv->index;
/* mipi command(payload) */
/* format: data_type, cmd_size, data.... */
@@ -1398,7 +1405,7 @@
*/
while ((i + DSI_CMD_SIZE_INDEX) < DSI_CMD_SIZE_MAX) {
if (ret) {
- LCDERR("%s: error, exit\n", __func__);
+ LCDERR("[%d]: %s: error, exit\n", index, __func__);
break;
}
cmd_size = payload[i+DSI_CMD_SIZE_INDEX];
@@ -1406,7 +1413,7 @@
if ((cmd_size == 0xff) || (cmd_size == 0))
break;
cmd_size = 0;
- mdelay(payload[i+1]);
+ mdelay(payload[i + 1]);
}
if (cmd_size == 0) {
@@ -1414,68 +1421,78 @@
continue;
}
if (i + 2 + cmd_size > DSI_CMD_SIZE_MAX) {
- LCDERR("step %d: cmd_size out of support\n", step);
+ LCDERR("[%d]: step %d: cmd_size out of support\n",
+ index, step);
break;
}
if (payload[i] == LCD_EXT_CMD_TYPE_DELAY) { /* delay */
delay_ms = 0;
for (j = 0; j < cmd_size; j++)
- delay_ms += payload[i+2+j];
+ delay_ms += payload[i + 2 + j];
if (delay_ms > 0)
mdelay(delay_ms);
} else if (payload[i] == LCD_EXT_CMD_TYPE_GPIO) { /* gpio */
if (cmd_size < 2) {
- LCDERR("step %d: invalid cmd_size %d for gpio\n",
- step, cmd_size);
+ LCDERR("[%d]: step %d: invalid cmd_size %d for gpio\n",
+ index, step, cmd_size);
break;
}
- lcd_gpio_set(payload[i+2], payload[i+3]);
+ str = pdrv->config.power.cpu_gpio[payload[i + 2]];
+ gpio = lcd_gpio_name_map_num(str);
+ lcd_gpio_set(gpio, payload[i + 3]);
if (cmd_size > 2) {
- if (payload[i+4])
- mdelay(payload[i+4]);
+ if (payload[i + 4])
+ mdelay(payload[i + 4]);
}
} else if (payload[i] == LCD_EXT_CMD_TYPE_CHECK) { /* check state */
if (cmd_size < 2) {
- LCDERR("step %d: invalid cmd_size %d for check state\n",
- step, cmd_size);
+ LCDERR("[%d]: step %d: invalid cmd_size %d for check state\n",
+ index, step, cmd_size);
break;
}
- if (payload[i+3] > 0)
- ret = mipi_dsi_check_state(payload[i+2], payload[i+3]);
+ if (!pdrv) {
+ LCDERR("[%d]: step %d: invalid pdrv for check state\n",
+ index, step);
+ break;
+ }
+ if (payload[i + 3] > 0)
+ ret = mipi_dsi_check_state(pdrv,
+ payload[i + 2],
+ payload[i + 3]);
} else {
/* payload[i+DSI_CMD_SIZE_INDEX] is data count */
dsi_cmd_req.data_type = payload[i];
dsi_cmd_req.vc_id = (vc_id & 0x3);
dsi_cmd_req.payload = &payload[i];
- dsi_cmd_req.pld_count = payload[i+DSI_CMD_SIZE_INDEX];
+ dsi_cmd_req.pld_count = payload[i + DSI_CMD_SIZE_INDEX];
dsi_cmd_req.req_ack = req_ack;
switch (dsi_cmd_req.data_type) {/* analysis data_type */
case DT_GEN_SHORT_WR_0:
case DT_GEN_SHORT_WR_1:
case DT_GEN_SHORT_WR_2:
- ret = dsi_generic_write_short_packet(&dsi_cmd_req);
+ ret = dsi_generic_write_short_packet(index, &dsi_cmd_req);
break;
case DT_DCS_SHORT_WR_0:
case DT_DCS_SHORT_WR_1:
- ret = dsi_dcs_write_short_packet(&dsi_cmd_req);
+ ret = dsi_dcs_write_short_packet(index, &dsi_cmd_req);
break;
case DT_DCS_LONG_WR:
case DT_GEN_LONG_WR:
- ret = dsi_write_long_packet(&dsi_cmd_req);
+ ret = dsi_write_long_packet(index, &dsi_cmd_req);
break;
case DT_TURN_ON:
- dsi_host_setb(MIPI_DSI_TOP_CNTL, 1, 2, 1);
- mdelay(5); /* wait for vsync trigger */
- dsi_host_setb(MIPI_DSI_TOP_CNTL, 0, 2, 1);
- mdelay(5); /* wait for vsync trigger */
+ dsi_host_setb(index, MIPI_DSI_TOP_CNTL, 1, 2, 1);
+ mdelay(20); /* wait for vsync trigger */
+ dsi_host_setb(index, MIPI_DSI_TOP_CNTL, 0, 2, 1);
+ mdelay(20); /* wait for vsync trigger */
break;
case DT_SHUT_DOWN:
- dsi_host_setb(MIPI_DSI_TOP_CNTL, 1, 2, 1);
- mdelay(5); /* wait for vsync trigger */
+ dsi_host_setb(index, MIPI_DSI_TOP_CNTL, 1, 2, 1);
+ mdelay(20); /* wait for vsync trigger */
break;
case DT_SET_MAX_RET_PKT_SIZE:
- dsi_set_max_return_pkt_size(&dsi_cmd_req);
+ dsi_set_max_return_pkt_size(index, &dsi_cmd_req);
break;
#ifdef DSI_CMD_READ_VALID
case DT_GEN_RD_0:
@@ -1486,9 +1503,9 @@
dsi_cmd_req.pld_count =
(dsi_cmd_req.pld_count > 2) ?
2 : dsi_cmd_req.pld_count;
- n = dsi_generic_read_packet(&dsi_cmd_req,
+ n = dsi_generic_read_packet(index, &dsi_cmd_req,
&rd_data[0]);
- LCDPR("generic read data");
+ LCDPR("[%d]: generic read data", index);
for (k = 0; k < dsi_cmd_req.pld_count; k++) {
printf(" 0x%02x",
dsi_cmd_req.payload[k+2]);
@@ -1500,7 +1517,7 @@
case DT_DCS_RD_0:
/* need BTA ack */
dsi_cmd_req.req_ack = MIPI_DSI_DCS_REQ_ACK;
- n = dsi_dcs_read_packet(&dsi_cmd_req,
+ n = dsi_dcs_read_packet(index, &dsi_cmd_req,
&rd_data[0]);
printf("dcs read data 0x%02x:\n",
dsi_cmd_req.payload[2]);
@@ -1510,8 +1527,8 @@
break;
#endif
default:
- LCDPR("[warning]: step %d: un-support data_type: 0x%02x\n",
- step, dsi_cmd_req.data_type);
+ LCDPR("[%d]: step %d: un-support data_type: 0x%02x\n",
+ index, step, dsi_cmd_req.data_type);
break;
}
@@ -1597,7 +1614,7 @@
if ((dphy->hs_zero * temp) < t_req_min)
dphy->hs_zero += 1;
- if (lcd_debug_print_flag) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
LCDPR("%s:\n"
"lp_tesc = 0x%02x\n"
"lp_lpx = 0x%02x\n"
@@ -1631,26 +1648,26 @@
unsigned int den, num;
unsigned short v_period, v_active, vs_width, vs_bp;
- h_period = pconf->lcd_basic.h_period;
- hs_width = pconf->lcd_timing.hsync_width;
- hs_bp = pconf->lcd_timing.hsync_bp;
- den = pconf->lcd_control.mipi_config->factor_denominator;
- num = pconf->lcd_control.mipi_config->factor_numerator;
+ h_period = pconf->basic.h_period;
+ hs_width = pconf->timing.hsync_width;
+ hs_bp = pconf->timing.hsync_bp;
+ den = pconf->control.mipi_cfg.factor_denominator;
+ num = pconf->control.mipi_cfg.factor_numerator;
dsi_vconf.hline = (h_period * den + num - 1) / num;
dsi_vconf.hsa = (hs_width * den + num - 1) / num;
dsi_vconf.hbp = (hs_bp * den + num - 1) / num;
- v_period = pconf->lcd_basic.v_period;
- v_active = pconf->lcd_basic.v_active;
- vs_width = pconf->lcd_timing.vsync_width;
- vs_bp = pconf->lcd_timing.vsync_bp;
+ v_period = pconf->basic.v_period;
+ v_active = pconf->basic.v_active;
+ vs_width = pconf->timing.vsync_width;
+ vs_bp = pconf->timing.vsync_bp;
dsi_vconf.vsa = vs_width;
dsi_vconf.vbp = vs_bp;
dsi_vconf.vfp = v_period - v_active - vs_bp - vs_width;
dsi_vconf.vact = v_active;
- if (lcd_debug_print_flag) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
LCDPR("MIPI DSI video timing:\n"
" HLINE = %d\n"
" HSA = %d\n"
@@ -1667,7 +1684,7 @@
#define DSI_PACKET_HEADER_CRC 6 /* 4(header)+2(CRC) */
static void mipi_dsi_non_burst_packet_config(struct lcd_config_s *pconf)
{
- struct dsi_config_s *dconf = pconf->lcd_control.mipi_config;
+ struct dsi_config_s *dconf = &pconf->control.mipi_cfg;
unsigned int lane_num, clk_factor, hactive, multi_pkt_en;
unsigned int bit_rate_required;
unsigned int pixel_per_chunk = 0, vid_num_chunks = 0;
@@ -1678,16 +1695,16 @@
lane_num = (int)(dconf->lane_num);
clk_factor = dconf->clk_factor;
- hactive = pconf->lcd_basic.h_active;
- bit_rate_required = pconf->lcd_timing.lcd_clk * 3 * dsi_vconf.data_bits;
+ hactive = pconf->basic.h_active;
+ bit_rate_required = pconf->timing.lcd_clk * 3 * dsi_vconf.data_bits;
bit_rate_required = bit_rate_required / lane_num;
- if (dconf->bit_rate > bit_rate_required)
+ if (pconf->timing.bit_rate > bit_rate_required)
multi_pkt_en = 1;
else
multi_pkt_en = 0;
- if (lcd_debug_print_flag) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
LCDPR("non-burst: bit_rate_required=%d, bit_rate=%d, multi_pkt_en=%d\n",
- bit_rate_required, dconf->bit_rate, multi_pkt_en);
+ bit_rate_required, pconf->timing.bit_rate, multi_pkt_en);
}
if (multi_pkt_en == 0) {
@@ -1775,7 +1792,7 @@
dsi_vconf.byte_per_chunk = byte_per_chunk;
dsi_vconf.multi_pkt_en = multi_pkt_en;
- if (lcd_debug_print_flag) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
LCDPR("MIPI DSI NON-BURST setting:\n"
" multi_pkt_en = %d\n"
" vid_num_chunks = %d\n"
@@ -1794,8 +1811,8 @@
static void mipi_dsi_vid_mode_config(struct lcd_config_s *pconf)
{
- if (pconf->lcd_control.mipi_config->video_mode_type == BURST_MODE) {
- dsi_vconf.pixel_per_chunk = pconf->lcd_basic.h_active;
+ if (pconf->control.mipi_cfg.video_mode_type == BURST_MODE) {
+ dsi_vconf.pixel_per_chunk = pconf->basic.h_active;
dsi_vconf.vid_num_chunks = 0;
dsi_vconf.vid_null_size = 0;
} else {
@@ -1805,36 +1822,36 @@
mipi_dsi_video_config(pconf);
}
-static void mipi_dsi_link_on(struct lcd_config_s *pconf)
+static void mipi_dsi_link_on(struct aml_lcd_drv_s *pdrv)
{
unsigned int op_mode_init, op_mode_disp;
struct dsi_config_s *dconf;
#ifdef CONFIG_AML_LCD_EXTERN
- struct aml_lcd_extern_driver_s *lcd_ext;
+ struct lcd_extern_driver_s *pext;
#endif
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
- dconf = pconf->lcd_control.mipi_config;
+ dconf = &pdrv->config.control.mipi_cfg;
op_mode_init = dconf->operation_mode_init;
op_mode_disp = dconf->operation_mode_display;
if (dconf->dsi_init_on) {
- dsi_write_cmd(dconf->dsi_init_on);
- LCDPR("dsi init on\n");
+ dsi_write_cmd(pdrv, dconf->dsi_init_on);
+ LCDPR("[%d]: dsi init on\n", pdrv->index);
}
#ifdef CONFIG_AML_LCD_EXTERN
if (dconf->extern_init < LCD_EXTERN_INDEX_INVALID) {
- lcd_ext = aml_lcd_extern_get_driver();
- if (lcd_ext == NULL) {
- LCDPR("no lcd_extern driver\n");
+ pext = lcd_extern_get_driver(dconf->extern_init);
+ if (!pext) {
+ LCDPR("[%d]: no lcd_extern driver\n", pdrv->index);
} else {
- if (lcd_ext->config->table_init_on) {
- dsi_write_cmd(lcd_ext->config->table_init_on);
- LCDPR("[extern]%s dsi init on\n",
- lcd_ext->config->name);
+ if (pext->config->table_init_on) {
+ dsi_write_cmd(pdrv, pext->config->table_init_on);
+ LCDPR("[%d]: [extern]%s dsi init on\n",
+ pdrv->index, pext->config->name);
}
}
}
@@ -1846,24 +1863,22 @@
* YUV 422 or 420, even or odd
*/
op_mode_disp, /* DSI operation mode, video or command */
- pconf);
- if (op_mode_disp == MIPI_DSI_OPERATION_MODE_VIDEO)
- lcd_vcbus_write(ENCL_VIDEO_EN, 1);
+ pdrv);
}
}
-void mipi_dsi_link_off(struct lcd_config_s *pconf)
+void mipi_dsi_link_off(struct aml_lcd_drv_s *pdrv)
{
unsigned int op_mode_init, op_mode_disp;
struct dsi_config_s *dconf;
#ifdef CONFIG_AML_LCD_EXTERN
- struct aml_lcd_extern_driver_s *lcd_ext;
+ struct lcd_extern_driver_s *pext;
#endif
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
- dconf = pconf->lcd_control.mipi_config;
+ dconf = &pdrv->config.control.mipi_cfg;
op_mode_init = dconf->operation_mode_init;
op_mode_disp = dconf->operation_mode_display;
@@ -1873,103 +1888,56 @@
* YUV 422 or 420, even or odd
*/
op_mode_init, /* DSI operation mode, video or command */
- pconf);
+ pdrv);
}
#ifdef CONFIG_AML_LCD_EXTERN
if (dconf->extern_init < LCD_EXTERN_INDEX_INVALID) {
- lcd_ext = aml_lcd_extern_get_driver();
- if (lcd_ext == NULL) {
- LCDPR("no lcd_extern driver\n");
+ pext = lcd_extern_get_driver(dconf->extern_init);
+ if (!pext) {
+ LCDPR("[%d]: no lcd_extern driver\n", pdrv->index);
} else {
- if (lcd_ext->config->table_init_off) {
- dsi_write_cmd(lcd_ext->config->table_init_off);
- LCDPR("[extern]%s dsi init off\n",
- lcd_ext->config->name);
+ if (pext->config->table_init_off) {
+ dsi_write_cmd(pdrv, pext->config->table_init_off);
+ LCDPR("[%d]: [extern]%s dsi init off\n",
+ pdrv->index, pext->config->name);
}
}
}
#endif
if (dconf->dsi_init_off) {
- dsi_write_cmd(dconf->dsi_init_off);
- LCDPR("dsi init off\n");
+ dsi_write_cmd(pdrv, dconf->dsi_init_off);
+ LCDPR("[%d]: dsi init off\n", pdrv->index);
}
}
-void lcd_mipi_dsi_config_set(struct lcd_config_s *pconf)
+void mipi_dsi_config_init(struct lcd_config_s *pconf)
{
- unsigned int pclk, bit_rate, lcd_bits;
- unsigned int bit_rate_max, bit_rate_min, pll_out_fmin = 0;
- struct dsi_config_s *dconf = pconf->lcd_control.mipi_config;
- struct lcd_clk_config_s *cConf = get_lcd_clk_config();
- int n;
- unsigned int temp;
- char *str;
-
- /* unit in kHz for calculation */
- if (cConf->data)
- pll_out_fmin = cConf->data->pll_out_fmin;
- pclk = pconf->lcd_timing.lcd_clk / 1000;
+ struct dsi_config_s *dconf = &pconf->control.mipi_cfg;
+ unsigned int status;
/* data format */
- if (pconf->lcd_basic.lcd_bits == 6) {
+ if (pconf->basic.lcd_bits == 6) {
dconf->venc_data_width = MIPI_DSI_VENC_COLOR_18B;
dconf->dpi_data_format = MIPI_DSI_COLOR_18BIT;
if (dconf->dpi_data_format == COLOR_18BIT_CFG_2)
- lcd_bits = 8;
+ dconf->data_bits = 8;
else
- lcd_bits = 6;
+ dconf->data_bits = 6;
} else {
dconf->venc_data_width = MIPI_DSI_VENC_COLOR_24B;
dconf->dpi_data_format = MIPI_DSI_COLOR_24BIT;
- lcd_bits = 8;
+ dconf->data_bits = 8;
}
- dsi_vconf.data_bits = lcd_bits;
-
- /* bit rate max */
- if (dconf->bit_rate_max == 0) { /* auto calculate */
- if ((dconf->operation_mode_display == OPERATION_VIDEO_MODE) &&
- (dconf->video_mode_type != BURST_MODE)) {
- temp = pclk * 4 * lcd_bits;
- bit_rate = temp / dconf->lane_num;
- } else {
- temp = pclk * 3 * lcd_bits;
- bit_rate = temp / dconf->lane_num;
- }
- n = 0;
- bit_rate_min = 0;
- bit_rate_max = 0;
- while ((bit_rate_min < pll_out_fmin) && (n < 100)) {
- bit_rate_max = bit_rate + (pclk / 2) + (n * pclk);
- bit_rate_min = bit_rate_max - pclk;
- n++;
- }
- dconf->bit_rate_max = bit_rate_max / 1000; /* unit: MHz*/
- if (dconf->bit_rate_max > MIPI_PHY_CLK_MAX)
- dconf->bit_rate_max = MIPI_PHY_CLK_MAX;
-
- LCDPR("mipi dsi bit_rate max=%dMHz\n", dconf->bit_rate_max);
- } else { /* user define */
- if (dconf->bit_rate_max < pll_out_fmin / 1000) {
- LCDERR("mipi-dsi can't support bit_rate %dMHz (min=%dMHz)\n",
- dconf->bit_rate_max, (pll_out_fmin / 1000));
- }
- if (dconf->bit_rate_max > MIPI_PHY_CLK_MAX) {
- LCDPR("[warning]: mipi-dsi bit_rate_max %dMHz is out of standard (%dMHz)\n",
- dconf->bit_rate_max, MIPI_PHY_CLK_MAX);
- }
- }
+ dsi_vconf.data_bits = dconf->data_bits;
/* check_state */
if (dconf->check_en) {
- str = env_get("lcd_mipi_check");
- if (str) {
- temp = simple_strtoul(str, NULL, 10);
- if (temp == 0) {
- dconf->check_en = 0;
- LCDPR("lcd_mipi_check flag disable check_state\n");
- }
+ status = env_get_ulong("lcd_mipi_check", 10, 0xffff);
+ if (status == 0) {
+ dconf->check_en = 0;
+ LCDPR("lcd_mipi_check disable check_state\n");
}
}
dconf->check_state = 0;
@@ -1984,10 +1952,10 @@
break;
case 0: /* auto */
default:
- if ((pconf->lcd_basic.h_active != 240) &&
- (pconf->lcd_basic.h_active != 768) &&
- (pconf->lcd_basic.h_active != 1920) &&
- (pconf->lcd_basic.h_active != 2560)) {
+ if ((pconf->basic.h_active != 240) &&
+ (pconf->basic.h_active != 768) &&
+ (pconf->basic.h_active != 1920) &&
+ (pconf->basic.h_active != 2560)) {
dsi_phy_config.state_change = 2;
} else {
dsi_phy_config.state_change = 1;
@@ -2001,17 +1969,17 @@
{
unsigned int pclk, lanebyteclk;
unsigned int den, num;
- struct dsi_config_s *dconf = pconf->lcd_control.mipi_config;
+ struct dsi_config_s *dconf = &pconf->control.mipi_cfg;
- pclk = pconf->lcd_timing.lcd_clk / 1000;
+ pclk = pconf->timing.lcd_clk / 1000;
/* pclk lanebyteclk factor */
if (dconf->factor_numerator == 0) {
- lanebyteclk = dconf->bit_rate / 8 / 1000;
+ lanebyteclk = pconf->timing.bit_rate / 8 / 1000;
LCDPR("pixel_clk = %d.%03dMHz, bit_rate = %d.%03dMHz, lanebyteclk = %d.%03dMHz\n",
(pclk / 1000), (pclk % 1000),
- (dconf->bit_rate / 1000000),
- ((dconf->bit_rate / 1000) % 1000),
+ (pconf->timing.bit_rate / 1000000),
+ ((pconf->timing.bit_rate / 1000) % 1000),
(lanebyteclk / 1000), (lanebyteclk % 1000));
#if 0
dconf->factor_numerator = pclk;
@@ -2023,7 +1991,7 @@
}
num = dconf->factor_numerator;
den = dconf->factor_denominator;
- if (lcd_debug_print_flag) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
LCDPR("num=%d, den=%d, factor=%d.%02d\n",
num, den, (den / num), ((den % num) * 100 / num));
}
@@ -2032,79 +2000,137 @@
mipi_dsi_vid_mode_config(pconf);
/* phy config */
- mipi_dsi_phy_config(&dsi_phy_config, dconf->bit_rate);
+ mipi_dsi_phy_config(&dsi_phy_config, pconf->timing.bit_rate);
}
-static void mipi_dsi_host_on(struct lcd_config_s *pconf)
+static void mipi_dsi_host_on(struct aml_lcd_drv_s *pdrv)
{
- unsigned int op_mode_init;
+ unsigned int op_mode_init, op_mode_disp, offset;
+ unsigned int venc_en = 0;
+ int index = pdrv->index;
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
+
+ offset = pdrv->data->offset_venc[pdrv->index];
/* disable encl */
- lcd_vcbus_write(ENCL_VIDEO_EN, 0);
+ lcd_vcbus_write(ENCL_VIDEO_EN + offset, 0);
+ venc_en = 0;
udelay(100);
- mipi_dsi_config_post(pconf);
+ mipi_dsi_config_post(&pdrv->config);
- startup_mipi_dsi_host();
+ startup_mipi_dsi_host(index);
- set_dsi_phy_config(pconf->lcd_control.mipi_config);
+ set_dsi_phy_config(pdrv);
- op_mode_init = pconf->lcd_control.mipi_config->operation_mode_init;
- mipi_dcs_set(MIPI_DSI_CMD_TRANS_TYPE, /* 0: high speed, 1: low power */
+ op_mode_init = pdrv->config.control.mipi_cfg.operation_mode_init;
+ op_mode_disp = pdrv->config.control.mipi_cfg.operation_mode_display;
+ mipi_dcs_set(index, MIPI_DSI_CMD_TRANS_TYPE, /* 0: high speed, 1: low power */
MIPI_DSI_DCS_ACK_TYPE, /* if need bta ack check */
MIPI_DSI_TEAR_SWITCH); /* enable tear ack */
set_mipi_dsi_host(MIPI_DSI_VIRTUAL_CHAN_ID, /* Virtual channel id */
0, /* Chroma sub sample, only for YUV 422 or 420, even or odd */
op_mode_init, /* DSI operation mode, video or command */
- pconf);
+ pdrv);
/* Startup transfer */
- mipi_dsi_lpclk_ctrl(pconf->lcd_control.mipi_config);
- if (op_mode_init == MIPI_DSI_OPERATION_MODE_VIDEO)
- lcd_vcbus_write(ENCL_VIDEO_EN, 1);
-
- mipi_dsi_link_on(pconf);
-
- if (lcd_debug_print_flag)
- mipi_dsi_host_print_info(pconf);
-}
-
-static void mipi_dsi_host_off(void)
-{
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
-
- /* Power down DSI */
- dsi_host_write(MIPI_DSI_DWC_PWR_UP_OS, 0);
-
- /* Power down D-PHY, do not have to close dphy */
- /* dsi_host_write(MIPI_DSI_DWC_PHY_RSTZ_OS,
- * (dsi_host_read( MIPI_DSI_DWC_PHY_RSTZ_OS ) & 0xc));
- */
- /* dsi_host_write(MIPI_DSI_DWC_PHY_RSTZ_OS, 0xc); */
-
- dsi_phy_write(MIPI_DSI_CHAN_CTRL, 0x1f);
- //LCDPR("MIPI_DSI_PHY_CTRL=0x%x\n", dsi_phy_read(MIPI_DSI_PHY_CTRL));
- dsi_phy_setb(MIPI_DSI_PHY_CTRL, 0, 7, 1);
-}
-
-void lcd_mipi_control_set(struct lcd_config_s *pconf, int status)
-{
- if (lcd_debug_print_flag)
- LCDPR("%s: %d\n", __func__, status);
-
- if (pconf->lcd_control.mipi_config == NULL) {
- LCDERR("%s: dsi config is NULL\n", __func__);
- return;
+ mipi_dsi_lpclk_ctrl(index, &pdrv->config.control.mipi_cfg);
+ if (op_mode_init == MIPI_DSI_OPERATION_MODE_VIDEO) {
+ lcd_vcbus_write(ENCL_VIDEO_EN + offset, 1);
+ venc_en = 1;
}
- if (status)
- mipi_dsi_host_on(pconf);
- else
- mipi_dsi_host_off();
+ mipi_dsi_link_on(pdrv);
+ if (op_mode_disp == MIPI_DSI_OPERATION_MODE_VIDEO) {
+ if (venc_en == 0) {
+ lcd_vcbus_write(ENCL_VIDEO_EN + offset, 1);
+ venc_en = 1;
+ }
+ }
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ mipi_dsi_host_print_info(&pdrv->config);
}
+static void mipi_dsi_host_off(struct aml_lcd_drv_s *pdrv)
+{
+ int index = pdrv->index;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
+
+ /* Power down DSI */
+ dsi_host_write(index, MIPI_DSI_DWC_PWR_UP_OS, 0);
+
+ /* Power down D-PHY, do not have to close dphy */
+ /* dsi_host_write(index, MIPI_DSI_DWC_PHY_RSTZ_OS,
+ * (dsi_host_read(index, MIPI_DSI_DWC_PHY_RSTZ_OS ) & 0xc));
+ */
+ /* dsi_host_write(index, MIPI_DSI_DWC_PHY_RSTZ_OS, 0xc); */
+
+ dsi_phy_write(index, MIPI_DSI_CHAN_CTRL, 0x1f);
+ //LCDPR("MIPI_DSI_PHY_CTRL=0x%x\n", dsi_phy_read(index, MIPI_DSI_PHY_CTRL));
+ dsi_phy_setb(index, MIPI_DSI_PHY_CTRL, 0, 7, 1);
+}
+
+static void mipi_dsi_host_reset(int index)
+{
+ unsigned int bit;
+
+ if (index)
+ bit = 31;
+ else
+ bit = 30;
+
+ lcd_reset_setb(RESETCTRL_RESET1_MASK, 0, bit, 1);
+ lcd_reset_setb(RESETCTRL_RESET1_LEVEL, 0, bit, 1);
+ udelay(1);
+ lcd_reset_setb(RESETCTRL_RESET1_LEVEL, 1, bit, 1);
+ udelay(1);
+}
+
+static void mipi_dsi_phy_reset(int index)
+{
+ unsigned int bit;
+
+ if (index)
+ bit = 29;
+ else
+ bit = 28;
+
+ lcd_reset_setb(RESETCTRL_RESET1_MASK, 0, bit, 1);
+ lcd_reset_setb(RESETCTRL_RESET1_LEVEL, 0, bit, 1);
+ udelay(1);
+ lcd_reset_setb(RESETCTRL_RESET1_LEVEL, 1, bit, 1);
+ udelay(1);
+}
+
+static void mipi_dsi_power_init(int index)
+{
+#ifdef CONFIG_SECURE_POWER_CONTROL
+//#define PM_MIPI_DSI1 50
+//#define PM_MIPI_DSI0 41
+ if (index)
+ pwr_ctrl_psci_smc(PM_MIPI_DSI1, 1);
+ else
+ pwr_ctrl_psci_smc(PM_MIPI_DSI0, 1);
+ LCDPR("[%d]: dsi power domain on\n", index);
+#endif
+}
+
+void mipi_dsi_tx_ctrl(struct aml_lcd_drv_s *pdrv, int flag)
+{
+ if (flag) {
+ if (pdrv->data->chip_type == LCD_CHIP_T7) {
+ mipi_dsi_power_init(pdrv->index);
+ mipi_dsi_phy_reset(pdrv->index);
+ mipi_dsi_host_reset(pdrv->index);
+ }
+ mipi_dsi_host_on(pdrv);
+ } else {
+ mipi_dsi_host_off(pdrv);
+ }
+}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.h b/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.h
index 4960921..cc7663e 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.h
+++ b/drivers/amlogic/media/vout/lcd/lcd_tablet/mipi_dsi_util.h
@@ -1,18 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/display/lcd/lcd_tablet/mipi_dsi_util.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef MIPI_DSI_UTIL_H
@@ -455,8 +443,6 @@
#define DCS_CMD_CODE_SOFT_RESET 0xc
/* DPHY standard timing */
-/* unit: MHz */
-#define MIPI_PHY_CLK_MAX 1000
/* **** DPHY timing parameter Value (unit: 0.01ns) **** */
/* >100ns (4M) */
@@ -539,12 +525,4 @@
#define DSI_CMD_SIZE_MAX 3000
#define DSI_CMD_READ_VALID
-extern void mipi_dsi_print_info(struct lcd_config_s *pconf);
-extern void lcd_mipi_dsi_config_set(struct lcd_config_s *pConf);
-extern void mipi_dsi_link_off(struct lcd_config_s *pConf);
-extern void lcd_mipi_control_set(struct lcd_config_s *pConf, int status);
-extern int lcd_mipi_dsi_init_table_detect(const void *dt_blob, int child_offset,
- struct dsi_config_s *dconf, int flag);
-extern int lcd_mipi_dsi_init_table_check_bsp(struct dsi_config_s *dconf, int flag);
-
#endif
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tcon.c b/drivers/amlogic/media/vout/lcd/lcd_tcon.c
index 635f72e..a17650c 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_tcon.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_tcon.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/aml_lcd_tcon.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -26,15 +11,20 @@
#include "lcd_common.h"
#include "lcd_tcon.h"
-static struct lcd_tcon_data_s *lcd_tcon_data;
+#define PR_BUF_MAX 200
-static int lcd_tcon_valid_check(void)
+#define TCON_IRQ_TIMEOUT_MAX BIT(17)
+static struct lcd_tcon_config_s *lcd_tcon_conf;
+static struct tcon_rmem_s tcon_rmem;
+static struct tcon_mem_map_table_s tcon_mm_table;
+
+int lcd_tcon_valid_check(void)
{
- if (lcd_tcon_data == NULL) {
+ if (!lcd_tcon_conf) {
LCDERR("invalid tcon data\n");
return -1;
}
- if (lcd_tcon_data->tcon_valid == 0) {
+ if (lcd_tcon_conf->tcon_valid == 0) {
LCDERR("invalid tcon\n");
return -1;
}
@@ -42,122 +32,269 @@
return 0;
}
-static void lcd_tcon_config_axi_offset_default(void)
+struct lcd_tcon_config_s *get_lcd_tcon_config(void)
{
- char *str;
-
- str = env_get("tcon_fb_addr");
- if (str) {
- lcd_tcon_data->axi_offset_addr = simple_strtoul(str, NULL, 16);
- } else {
- LCDERR("can't find env tcon_fb_addr\n");
- lcd_tcon_data->axi_offset_addr = 0;
- }
-}
-
-static int lcd_tcon_config(const void *dt_blob, struct lcd_config_s *pconf, int load_id)
-{
- int key_len, reg_len;
- int parent_offset;
- char *propdata;
int ret;
- if (load_id & 0x1) {
- parent_offset = fdt_path_offset(dt_blob, "/lcd");
- if (parent_offset < 0) {
- LCDERR("can't find /lcd node: %s\n", fdt_strerror(parent_offset));
- lcd_tcon_config_axi_offset_default();
- } else {
- propdata = (char *)fdt_getprop(dt_blob,
- parent_offset, "tcon_fb_addr", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get tcon_fb_addr from dts\n");
- lcd_tcon_config_axi_offset_default();
- } else {
- lcd_tcon_data->axi_offset_addr =
- be32_to_cpup(((u32*)propdata));
- }
- }
- } else {
- lcd_tcon_config_axi_offset_default();
- }
+ ret = lcd_tcon_valid_check();
+ if (ret)
+ return NULL;
- /* get reg table from unifykey */
- reg_len = lcd_tcon_data->reg_table_len;
- if (lcd_tcon_data->reg_table == NULL) {
- lcd_tcon_data->reg_table =
- (unsigned char *)malloc(sizeof(unsigned char) * reg_len);
- if (!lcd_tcon_data->reg_table) {
- LCDERR("%s: Not enough memory\n", __func__);
- return -1;
- }
- }
- memset(lcd_tcon_data->reg_table, 0, (sizeof(unsigned char) * reg_len));
- key_len = reg_len;
- ret = aml_lcd_unifykey_get_no_header("lcd_tcon",
- lcd_tcon_data->reg_table, &key_len);
- if (ret) {
- free(lcd_tcon_data->reg_table);
- lcd_tcon_data->reg_table = NULL;
- LCDERR("%s: !!!!!!!!tcon unifykey load error!!!!!!!!\n", __func__);
- return -1;
- }
- if (key_len != reg_len) {
- free(lcd_tcon_data->reg_table);
- lcd_tcon_data->reg_table = NULL;
- LCDERR("%s: !!!!!!!!tcon unifykey load length error!!!!!!!!\n", __func__);
- return -1;
- }
+ return lcd_tcon_conf;
+}
- LCDPR("tcon: load key len: %d\n", key_len);
- return 0;
+struct tcon_rmem_s *get_lcd_tcon_rmem(void)
+{
+ int ret;
+
+ ret = lcd_tcon_valid_check();
+ if (ret)
+ return NULL;
+
+ return &tcon_rmem;
+}
+
+struct tcon_mem_map_table_s *get_lcd_tcon_mm_table(void)
+{
+ int ret;
+
+ ret = lcd_tcon_valid_check();
+ if (ret)
+ return NULL;
+
+ return &tcon_mm_table;
+}
+
+unsigned int lcd_tcon_data_size_align(unsigned int size)
+{
+ unsigned int new_size;
+
+ /* ready for burst 128bit */
+ new_size = ((size + 15) / 16) * 16;
+
+ return new_size;
+}
+
+unsigned char lcd_tcon_checksum(unsigned char *buf, unsigned int len)
+{
+ unsigned int temp = 0;
+ unsigned int i;
+
+ if (!buf)
+ return 0;
+ if (len == 0)
+ return 0;
+ for (i = 0; i < len; i++)
+ temp += buf[i];
+
+ return (unsigned char)(temp & 0xff);
+}
+
+unsigned char lcd_tcon_lrc(unsigned char *buf, unsigned int len)
+{
+ unsigned char temp = 0;
+ unsigned int i;
+
+ if (!buf)
+ return 0xff;
+ if (len == 0)
+ return 0xff;
+ temp = buf[0];
+ for (i = 1; i < len; i++)
+ temp = temp ^ buf[i];
+
+ return temp;
}
/* **********************************
* tcon function api
* **********************************
*/
-#define PR_BUF_MAX 200
-void lcd_tcon_reg_table_print(void)
+static unsigned int lcd_tcon_reg_read(unsigned int addr, unsigned int flag)
{
- int i, j, n, cnt;
- char *buf;
+ unsigned int val;
+ int ret;
+
+ ret = lcd_tcon_valid_check();
+ if (ret)
+ return 0;
+
+ if (flag)
+ val = lcd_tcon_read_byte(addr);
+ else
+ val = lcd_tcon_read(addr);
+
+ return val;
+}
+
+static void lcd_tcon_reg_write(unsigned int addr, unsigned int val,
+ unsigned int flag)
+{
+ unsigned char temp;
int ret;
ret = lcd_tcon_valid_check();
if (ret)
return;
- if (lcd_tcon_data->reg_table == NULL) {
+ if (flag) {
+ temp = (unsigned char)val;
+ lcd_tcon_write_byte(addr, temp);
+ } else {
+ lcd_tcon_write(addr, val);
+ }
+}
+
+static void lcd_tcon_reg_table_print(void)
+{
+ int i, j, cnt;
+ int ret;
+
+ ret = lcd_tcon_valid_check();
+ if (ret)
+ return;
+
+ if (!tcon_mm_table.core_reg_table) {
LCDERR("%s: reg_table is null\n", __func__);
return;
}
- buf = (char *)malloc(PR_BUF_MAX * sizeof(char));
- if (buf == NULL) {
- LCDERR("%s: buf malloc error\n", __func__);
- return;
- }
-
LCDPR("%s:\n", __func__);
- cnt = lcd_tcon_data->reg_table_len;
+ cnt = tcon_mm_table.core_reg_table_size;
for (i = 0; i < cnt; i += 16) {
- n = snprintf(buf, PR_BUF_MAX, "0x%04x: ", i);
+ printf("%04x: ", i);
for (j = 0; j < 16; j++) {
if ((i + j) >= cnt)
break;
- n += snprintf(buf+n, PR_BUF_MAX, " 0x%02x",
- lcd_tcon_data->reg_table[i+j]);
+ printf(" %02x", tcon_mm_table.core_reg_table[i + j]);
}
- buf[n] = '\0';
- printf("%s\n", buf);
+ printf("\n");
}
- free(buf);
}
-void lcd_tcon_reg_readback_print(void)
+static void lcd_tcon_reg_readback_print(void)
{
- int i, j, n, cnt;
+ unsigned int i, j, cnt, offset;
+ int ret;
+
+ ret = lcd_tcon_valid_check();
+ if (ret)
+ return;
+
+ LCDPR("%s:\n", __func__);
+ cnt = tcon_mm_table.core_reg_table_size;
+ offset = lcd_tcon_conf->core_reg_start;
+ if (lcd_tcon_conf->core_reg_width == 8) {
+ for (i = offset; i < cnt; i += 16) {
+ printf("%04x: ", i);
+ for (j = 0; j < 16; j++) {
+ if ((i + j) >= cnt)
+ break;
+ printf(" %02x", lcd_tcon_read_byte(i + j));
+ }
+ printf("\n");
+ }
+ } else {
+ if (lcd_tcon_conf->reg_table_width == 32) {
+ cnt /= 4;
+ for (i = offset; i < cnt; i += 4) {
+ printf("%04x: ", i);
+ for (j = 0; j < 4; j++) {
+ if ((i + j) >= cnt)
+ break;
+ printf(" %08x", lcd_tcon_read(i + j));
+ }
+ printf("\n");
+ }
+ } else {
+ for (i = offset; i < cnt; i += 16) {
+ printf("%04x: ", i);
+ for (j = 0; j < 16; j++) {
+ if ((i + j) >= cnt)
+ break;
+ printf(" %02x", lcd_tcon_read(i + j));
+ }
+ printf("\n");
+ }
+ }
+ }
+}
+
+static unsigned int lcd_tcon_table_read(unsigned int addr)
+{
+ unsigned char *table8;
+ unsigned int *table32, size = 0, val = 0;
+ int ret;
+
+ ret = lcd_tcon_valid_check();
+ if (ret)
+ return 0;
+
+ if (!tcon_mm_table.core_reg_table) {
+ LCDERR("tcon reg_table is null\n");
+ return 0;
+ }
+
+ if (lcd_tcon_conf->core_reg_width == 8)
+ size = tcon_mm_table.core_reg_table_size;
+ else
+ size = tcon_mm_table.core_reg_table_size / 4;
+ if (addr >= size) {
+ LCDERR("invalid tcon reg_table addr: 0x%04x\n", addr);
+ return 0;
+ }
+
+ if (lcd_tcon_conf->core_reg_width == 8) {
+ table8 = tcon_mm_table.core_reg_table;
+ val = table8[addr];
+ } else {
+ table32 = (unsigned int *)tcon_mm_table.core_reg_table;
+ val = table32[addr];
+ }
+
+ return val;
+}
+
+static unsigned int lcd_tcon_table_write(unsigned int addr, unsigned int val)
+{
+ unsigned char *table8;
+ unsigned int *table32, size = 0, read_val = 0;
+ int ret;
+
+ ret = lcd_tcon_valid_check();
+ if (ret)
+ return 0;
+
+ if (!tcon_mm_table.core_reg_table) {
+ LCDERR("tcon reg_table is null\n");
+ return 0;
+ }
+
+ if (lcd_tcon_conf->core_reg_width == 8)
+ size = tcon_mm_table.core_reg_table_size;
+ else
+ size = tcon_mm_table.core_reg_table_size / 4;
+ if (addr >= size) {
+ LCDERR("invalid tcon reg_table addr: 0x%04x\n", addr);
+ return 0;
+ }
+
+ if (lcd_tcon_conf->core_reg_width == 8) {
+ table8 = tcon_mm_table.core_reg_table;
+ table8[addr] = (unsigned char)(val & 0xff);
+ read_val = table8[addr];
+ } else {
+ table32 = (unsigned int *)tcon_mm_table.core_reg_table;
+ table32[addr] = val;
+ read_val = table32[addr];
+ }
+
+ return read_val;
+}
+
+static void lcd_tcon_vac_print(void)
+{
+ int i, j, n, size;
char *buf;
int ret;
@@ -165,48 +302,382 @@
if (ret)
return;
+ if (tcon_mm_table.version) {
+ LCDERR("%s: mem map version invalid\n", __func__);
+ return;
+ }
+
+ if ((tcon_mm_table.valid_flag & LCD_TCON_DATA_VALID_VAC) == 0) {
+ LCDERR("%s: vac invalid\n", __func__);
+ return;
+ }
+
buf = (char *)malloc(PR_BUF_MAX * sizeof(char));
if (buf == NULL) {
LCDERR("%s: buf malloc error\n", __func__);
return;
}
- LCDPR("%s:\n", __func__);
- cnt = lcd_tcon_data->reg_table_len;
- for (i = 0; i < cnt; i += 16) {
+ printf("%s:\n", __func__);
+ size = tcon_rmem.vac_rmem.mem_vaddr[0] |
+ (tcon_rmem.vac_rmem.mem_vaddr[1] << 8) |
+ (tcon_rmem.vac_rmem.mem_vaddr[2] << 16) |
+ (tcon_rmem.vac_rmem.mem_vaddr[3] << 24);
+ size += 8; /* header for data_cnt & crc */
+ for (i = 0; i < size; i += 16) {
n = snprintf(buf, PR_BUF_MAX, "0x%04x: ", i);
for (j = 0; j < 16; j++) {
- if ((i + j) >= cnt)
+ if ((i + j) >= size)
break;
- if (lcd_tcon_data->core_reg_width == 8) {
- n += snprintf(buf+n, PR_BUF_MAX, " 0x%02x",
- lcd_tcon_read_byte(i+j));
- } else {
- n += snprintf(buf+n, PR_BUF_MAX, " 0x%02x",
- lcd_tcon_read(i+j));
- }
+ n += snprintf(buf + n, PR_BUF_MAX, " %02x",
+ tcon_rmem.vac_rmem.mem_vaddr[i + j]);
}
buf[n] = '\0';
printf("%s\n", buf);
}
+
+ free(buf);
+}
+
+static void lcd_tcon_demura_print(void)
+{
+ int i, j, n, size;
+ char *buf;
+ int ret;
+
+ ret = lcd_tcon_valid_check();
+ if (ret)
+ return;
+
+ if (tcon_mm_table.version) {
+ LCDERR("%s: mem map version invalid\n", __func__);
+ return;
+ }
+
+ if ((tcon_mm_table.valid_flag & LCD_TCON_DATA_VALID_DEMURA) == 0) {
+ LCDERR("%s: demura invalid\n", __func__);
+ return;
+ }
+
+ buf = (char *)malloc(PR_BUF_MAX * sizeof(char));
+ if (buf == NULL) {
+ LCDERR("%s: buf malloc error\n", __func__);
+ return;
+ }
+
+ printf("%s: demura_set:\n", __func__);
+ size = tcon_rmem.demura_set_rmem.mem_vaddr[0] |
+ (tcon_rmem.demura_set_rmem.mem_vaddr[1] << 8) |
+ (tcon_rmem.demura_set_rmem.mem_vaddr[2] << 16) |
+ (tcon_rmem.demura_set_rmem.mem_vaddr[3] << 24);
+ size += 8; /* header for data_cnt & crc */
+ for (i = 0; i < size; i += 16) {
+ n = snprintf(buf, PR_BUF_MAX, "0x%04x: ", i);
+ for (j = 0; j < 16; j++) {
+ if ((i + j) >= size)
+ break;
+ n += snprintf
+ (buf + n, PR_BUF_MAX, " %02x",
+ tcon_rmem.demura_set_rmem.mem_vaddr[i + j]);
+ }
+ buf[n] = '\0';
+ printf("%s\n", buf);
+ }
+
+ printf("\n%s: demura_lut:\n", __func__);
+ size = tcon_rmem.demura_lut_rmem.mem_vaddr[0] |
+ (tcon_rmem.demura_lut_rmem.mem_vaddr[1] << 8) |
+ (tcon_rmem.demura_lut_rmem.mem_vaddr[2] << 16) |
+ (tcon_rmem.demura_lut_rmem.mem_vaddr[3] << 24);
+ size += 8; /* header for data_cnt & crc */
+ for (i = 0; i < size; i += 16) {
+ n = snprintf(buf, PR_BUF_MAX, "0x%04x: ", i);
+ for (j = 0; j < 16; j++) {
+ if ((i + j) >= size)
+ break;
+ n += snprintf
+ (buf + n, PR_BUF_MAX, " %02x",
+ tcon_rmem.demura_lut_rmem.mem_vaddr[i + j]);
+ }
+ buf[n] = '\0';
+ printf("%s\n", buf);
+ }
+
+ free(buf);
+}
+
+static void lcd_tcon_acc_print(void)
+{
+ int i, j, n, size;
+ char *buf;
+ int ret;
+
+ ret = lcd_tcon_valid_check();
+ if (ret)
+ return;
+
+ if (tcon_mm_table.version) {
+ LCDERR("%s: mem map version invalid\n", __func__);
+ return;
+ }
+
+ if ((tcon_mm_table.valid_flag & LCD_TCON_DATA_VALID_ACC) == 0) {
+ LCDERR("%s: acc_lut invalid\n", __func__);
+ return;
+ }
+
+ buf = (char *)malloc(PR_BUF_MAX * sizeof(char));
+ if (!buf) {
+ LCDERR("%s: buf malloc error\n", __func__);
+ return;
+ }
+
+ LCDPR("%s\n", __func__);
+ size = tcon_rmem.acc_lut_rmem.mem_vaddr[0] |
+ (tcon_rmem.acc_lut_rmem.mem_vaddr[1] << 8) |
+ (tcon_rmem.acc_lut_rmem.mem_vaddr[2] << 16) |
+ (tcon_rmem.acc_lut_rmem.mem_vaddr[3] << 24);
+ size += 8; /* header for data_cnt & crc */
+ for (i = 0; i < size; i += 16) {
+ n = snprintf(buf, PR_BUF_MAX, "0x%04x: ", i);
+ for (j = 0; j < 16; j++) {
+ if ((i + j) >= size)
+ break;
+ n += snprintf
+ (buf + n, PR_BUF_MAX, " %02x",
+ tcon_rmem.acc_lut_rmem.mem_vaddr[i + j]);
+ }
+ buf[n] = '\0';
+ printf("%s\n", buf);
+ }
+
+ free(buf);
+}
+
+static void lcd_tcon_data_block_print(char *buf, unsigned char *data_mem)
+{
+ int i, j, n, size;
+
+ size = data_mem[8] |
+ (data_mem[9] << 8) |
+ (data_mem[10] << 16) |
+ (data_mem[11] << 24);
+ for (i = 0; i < size; i += 16) {
+ n = snprintf(buf, PR_BUF_MAX, "0x%04x: ", i);
+ for (j = 0; j < 16; j++) {
+ if ((i + j) >= size)
+ break;
+ n += snprintf(buf + n, PR_BUF_MAX, " %02x",
+ data_mem[i + j]);
+ }
+ buf[n] = '\0';
+ printf("%s\n", buf);
+ }
+}
+
+static void lcd_tcon_data_print(unsigned char index)
+{
+ int i;
+ char *buf;
+ int ret;
+
+ ret = lcd_tcon_valid_check();
+ if (ret)
+ return;
+
+ if (tcon_mm_table.version == 0) {
+ LCDERR("%s: mem map version invalid\n", __func__);
+ return;
+ }
+
+ buf = (char *)malloc(PR_BUF_MAX * sizeof(char));
+ if (!buf) {
+ LCDERR("%s: buf malloc error\n", __func__);
+ return;
+ }
+
+ if (index == 0xff) {
+ for (i = 0; i < tcon_mm_table.block_cnt; i++) {
+ if (!tcon_mm_table.data_mem_vaddr[i])
+ continue;
+
+ printf("tcon data[%d] print:\n", i);
+ lcd_tcon_data_block_print
+ (buf, tcon_mm_table.data_mem_vaddr[i]);
+ }
+ } else {
+ if (index >= tcon_mm_table.block_cnt) {
+ LCDERR("%s: invalid index %d\n", __func__, index);
+ free(buf);
+ return;
+ }
+ if (!tcon_mm_table.data_mem_vaddr[index]) {
+ LCDERR("%s: invalid data_mem buf\n", __func__);
+ free(buf);
+ return;
+ }
+
+ printf("tcon data[%d] print:\n", index);
+ lcd_tcon_data_block_print
+ (buf, tcon_mm_table.data_mem_vaddr[index]);
+ }
+
free(buf);
}
void lcd_tcon_info_print(void)
{
- int ret;
+ unsigned int size, cnt, file_size, n;
+ char *str;
+ int i, ret;
ret = lcd_tcon_valid_check();
if (ret)
return;
LCDPR("%s:\n", __func__);
- printf("core_reg_width: %d\n", lcd_tcon_data->core_reg_width);
- printf("reg_table_len: %d\n", lcd_tcon_data->reg_table_len);
- printf("axi_offset_addr: 0x%08x\n", lcd_tcon_data->axi_offset_addr);
+ printf("core_reg_width: %d\n"
+ "reg_table_len: %d\n"
+ "tcon_rmem_flag: %d\n"
+ "rsv_mem addr: 0x%08x\n"
+ "rsv_mem size: 0x%08x\n\n",
+ lcd_tcon_conf->core_reg_width,
+ lcd_tcon_conf->reg_table_len,
+ tcon_rmem.flag,
+ tcon_rmem.rsv_mem_paddr,
+ tcon_rmem.rsv_mem_size);
+ if (tcon_rmem.flag) {
+ for (i = 0; i < lcd_tcon_conf->axi_bank; i++) {
+ printf("axi_mem[%d]_paddr: 0x%lx\n"
+ "axi_mem[%d]_vaddr: 0x%p\n"
+ "axi_mem[%d]_size: 0x%x\n",
+ i,
+ (unsigned long)tcon_rmem.axi_rmem[i].mem_paddr,
+ i, tcon_rmem.axi_rmem[i].mem_vaddr,
+ i, tcon_rmem.axi_rmem[i].mem_size);
+ }
+ }
+ if (tcon_rmem.bin_path_rmem.mem_size) {
+ printf("bin_path_mem paddr: 0x%08x\n"
+ "bin_path_mem vaddr: 0x%p\n"
+ "bin_path_mem size: 0x%08x\n\n",
+ tcon_rmem.bin_path_rmem.mem_paddr,
+ tcon_rmem.bin_path_rmem.mem_vaddr,
+ tcon_rmem.bin_path_rmem.mem_size);
+ }
+ if (tcon_mm_table.version == 0) {
+ if (tcon_rmem.vac_rmem.mem_size) {
+ printf("vac_mem vaddr: 0x%p\n"
+ "vac_mem size: 0x%08x\n",
+ tcon_rmem.vac_rmem.mem_vaddr,
+ tcon_rmem.vac_rmem.mem_size);
+ }
+ if (tcon_rmem.demura_set_rmem.mem_size) {
+ printf("demura_set_mem vaddr: 0x%p\n"
+ "demura_set_mem size: 0x%08x\n",
+ tcon_rmem.demura_set_rmem.mem_vaddr,
+ tcon_rmem.demura_set_rmem.mem_size);
+ }
+ if (tcon_rmem.demura_lut_rmem.mem_size) {
+ printf("demura_lut_mem vaddr: 0x%p\n"
+ "demura_lut_mem size: 0x%08x\n",
+ tcon_rmem.demura_lut_rmem.mem_vaddr,
+ tcon_rmem.demura_lut_rmem.mem_size);
+ }
+ if (tcon_rmem.acc_lut_rmem.mem_size) {
+ printf("acc_lut_mem vaddr: 0x%p\n"
+ "acc_lut_mem size: 0x%08x\n",
+ tcon_rmem.acc_lut_rmem.mem_vaddr,
+ tcon_rmem.acc_lut_rmem.mem_size);
+ }
+ } else {
+ printf("data_mem_block_cnt: %d\n",
+ tcon_mm_table.block_cnt);
+ for (i = 0; i < tcon_mm_table.block_cnt; i++) {
+ if (tcon_mm_table.data_mem_vaddr[i]) {
+ size = tcon_mm_table.data_mem_vaddr[i][8] |
+ (tcon_mm_table.data_mem_vaddr[i][9] << 8) |
+ (tcon_mm_table.data_mem_vaddr[i][10] << 16) |
+ (tcon_mm_table.data_mem_vaddr[i][11] << 24);
+ printf("data_mem[%d] vaddr: 0x%p\n"
+ "data_mem[%d] size: 0x%08x\n",
+ i, tcon_mm_table.data_mem_vaddr[i],
+ i, size);
+ }
+ }
+ }
+ if (tcon_rmem.bin_path_rmem.mem_vaddr) {
+ size = tcon_rmem.bin_path_rmem.mem_vaddr[4] |
+ (tcon_rmem.bin_path_rmem.mem_vaddr[5] << 8) |
+ (tcon_rmem.bin_path_rmem.mem_vaddr[6] << 16) |
+ (tcon_rmem.bin_path_rmem.mem_vaddr[7] << 24);
+ cnt = tcon_rmem.bin_path_rmem.mem_vaddr[16] |
+ (tcon_rmem.bin_path_rmem.mem_vaddr[17] << 8) |
+ (tcon_rmem.bin_path_rmem.mem_vaddr[18] << 16) |
+ (tcon_rmem.bin_path_rmem.mem_vaddr[19] << 24);
+ if (size < (32 + 256 * cnt))
+ return;
+ printf("\n");
+ for (i = 0; i < cnt; i++) {
+ n = 32 + 256 * i;
+ file_size = tcon_rmem.bin_path_rmem.mem_vaddr[n] |
+ (tcon_rmem.bin_path_rmem.mem_vaddr[n + 1] << 8) |
+ (tcon_rmem.bin_path_rmem.mem_vaddr[n + 2] << 16) |
+ (tcon_rmem.bin_path_rmem.mem_vaddr[n + 3] << 24);
+ str = (char *)&tcon_rmem.bin_path_rmem.mem_vaddr[n + 4];
+ printf("tcon_path[%d]: size: 0x%x, %s\n", i,
+ file_size, str);
+ }
+ }
+ printf("\n");
}
-int lcd_tcon_enable(struct lcd_config_s *pconf)
+#ifdef CONFIG_CMD_INI
+static int lcd_tcon_bin_path_resv_mem_set(void)
+{
+ unsigned char *buf, *mem_vaddr;
+ unsigned int data_size, block_size, temp_crc, n, i;
+
+ if (tcon_rmem.flag == 0)
+ return 0;
+
+ buf = handle_tcon_path_mem_get(tcon_rmem.bin_path_rmem.mem_size);
+ if (!buf) {
+ LCDERR("%s: bin_path buf invalid\n", __func__);
+ return -1;
+ }
+
+ data_size = buf[4] | (buf[5] << 8) | (buf[6] << 16) | (buf[7] << 24);
+
+ if (tcon_mm_table.data_size) {
+ for (i = 0; i < tcon_mm_table.block_cnt; i++) {
+ block_size = tcon_mm_table.data_size[i];
+ if (block_size == 0)
+ continue;
+ n = 32 + (i * 256);
+ buf[n] = block_size & 0xff;
+ buf[n + 1] = (block_size >> 8) & 0xff;
+ buf[n + 2] = (block_size >> 16) & 0xff;
+ buf[n + 3] = (block_size >> 24) & 0xff;
+ }
+
+ /* update data check */
+ temp_crc = crc32(0, &buf[4], (data_size - 4));
+ buf[0] = temp_crc & 0xff;
+ buf[1] = (temp_crc >> 8) & 0xff;
+ buf[2] = (temp_crc >> 16) & 0xff;
+ buf[3] = (temp_crc >> 24) & 0xff;
+ }
+
+ mem_vaddr = (unsigned char *)
+ (unsigned long)(tcon_rmem.bin_path_rmem.mem_paddr);
+ memcpy(mem_vaddr, buf, data_size);
+
+ return 0;
+}
+#endif
+
+int lcd_tcon_enable(struct aml_lcd_drv_s *pdrv)
{
int ret;
@@ -214,13 +685,17 @@
if (ret)
return -1;
- if (lcd_tcon_data->tcon_enable)
- lcd_tcon_data->tcon_enable(pconf);
+ if (lcd_tcon_conf->tcon_enable)
+ lcd_tcon_conf->tcon_enable(pdrv);
+
+#ifdef CONFIG_CMD_INI
+ lcd_tcon_bin_path_resv_mem_set();
+#endif
return 0;
}
-void lcd_tcon_disable(void)
+void lcd_tcon_disable(struct aml_lcd_drv_s *pdrv)
{
unsigned int reg, i, cnt, offset, bit;
int ret;
@@ -231,57 +706,1012 @@
LCDPR("%s\n", __func__);
/* disable over_drive */
- if (lcd_tcon_data->reg_core_od != REG_LCD_TCON_MAX) {
- reg = lcd_tcon_data->reg_core_od + TCON_CORE_REG_START;
- if (lcd_tcon_data->core_reg_width == 8)
- lcd_tcon_write_byte(reg, 0);
+ if (lcd_tcon_conf->reg_core_od != REG_LCD_TCON_MAX) {
+ reg = lcd_tcon_conf->reg_core_od;
+ bit = lcd_tcon_conf->bit_od_en;
+ if (lcd_tcon_conf->core_reg_width == 8)
+ lcd_tcon_setb_byte(reg, 0, bit, 1);
else
- lcd_tcon_write(reg, 0);
+ lcd_tcon_setb(reg, 0, bit, 1);
mdelay(100);
}
/* disable all ctrl signal */
- if (lcd_tcon_data->reg_core_ctrl_timing_base != REG_LCD_TCON_MAX) {
- reg = lcd_tcon_data->reg_core_ctrl_timing_base + TCON_CORE_REG_START;
- offset = lcd_tcon_data->ctrl_timing_offset;
- cnt = lcd_tcon_data->ctrl_timing_cnt;
+ if (lcd_tcon_conf->reg_ctrl_timing_base != REG_LCD_TCON_MAX) {
+ reg = lcd_tcon_conf->reg_ctrl_timing_base;
+ offset = lcd_tcon_conf->ctrl_timing_offset;
+ cnt = lcd_tcon_conf->ctrl_timing_cnt;
for (i = 0; i < cnt; i++) {
- if (lcd_tcon_data->core_reg_width == 8)
- lcd_tcon_setb_byte((reg + (i * offset)), 1, 3, 1);
+ if (lcd_tcon_conf->core_reg_width == 8)
+ lcd_tcon_setb_byte((reg + (i * offset)),
+ 1, 3, 1);
else
lcd_tcon_setb((reg + (i * offset)), 1, 3, 1);
}
}
/* disable top */
- if (lcd_tcon_data->reg_top_ctrl != REG_LCD_TCON_MAX) {
- reg = lcd_tcon_data->reg_top_ctrl;
- bit = lcd_tcon_data->bit_en;
+ if (lcd_tcon_conf->reg_top_ctrl != REG_LCD_TCON_MAX) {
+ reg = lcd_tcon_conf->reg_top_ctrl;
+ bit = lcd_tcon_conf->bit_en;
lcd_tcon_setb(reg, 0, bit, 1);
}
}
/* **********************************
+ * tcon config
+ * **********************************
+ */
+static int lcd_tcon_vac_load(void)
+{
+ unsigned char *buff = tcon_rmem.vac_rmem.mem_vaddr;
+#ifdef CONFIG_CMD_INI
+ unsigned int i, data_cnt = 0;
+ unsigned char data_checksum, data_lrc, temp_checksum, temp_lrc;
+#endif
+ int ret = -1;
+
+ if (tcon_rmem.vac_rmem.mem_size == 0 || !buff)
+ return -1;
+
+#ifdef CONFIG_CMD_INI
+ ret = handle_tcon_vac(buff, tcon_rmem.vac_rmem.mem_size);
+ if (ret) {
+ LCDPR("%s: no vac data\n", __func__);
+ return -1;
+ }
+ data_cnt = (buff[0] |
+ (buff[1] << 8) |
+ (buff[2] << 16) |
+ (buff[3] << 24));
+ if (data_cnt == 0) {
+ LCDERR("%s: vac_data data_cnt error\n", __func__);
+ return -1;
+ }
+ data_checksum = buff[4];
+ data_lrc = buff[5];
+ temp_checksum = lcd_tcon_checksum(&buff[8], data_cnt);
+ temp_lrc = lcd_tcon_lrc(&buff[8], data_cnt);
+ if (data_checksum != temp_checksum) {
+ LCDERR("%s: vac_data checksum error\n", __func__);
+ return -1;
+ }
+ if (data_lrc != temp_lrc) {
+ LCDERR("%s: vac_data lrc error\n", __func__);
+ return -1;
+ }
+ if (buff[6] != 0x55 || buff[7] != 0xaa) {
+ LCDERR("%s: vac_data pattern error\n", __func__);
+ return -1;
+ }
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_ADV) {
+ for (i = 0; i < 30; i++)
+ LCDPR("vac_data[%d]: 0x%02x\n", i, buff[i * 1]);
+ }
+#endif
+ return ret;
+}
+
+static int lcd_tcon_demura_set_load(void)
+{
+ unsigned char *buff = tcon_rmem.demura_set_rmem.mem_vaddr;
+#ifdef CONFIG_CMD_INI
+ unsigned int i, data_cnt = 0;
+ unsigned char data_checksum, data_lrc, temp_checksum, temp_lrc;
+#endif
+ int ret = -1;
+
+ if (tcon_rmem.demura_set_rmem.mem_size == 0 || !buff)
+ return -1;
+
+#ifdef CONFIG_CMD_INI
+ ret = handle_tcon_demura_set(buff, tcon_rmem.demura_set_rmem.mem_size);
+ if (ret) {
+ LCDPR("%s: no demura_set data\n", __func__);
+ return -1;
+ }
+
+ data_cnt = (buff[0] |
+ (buff[1] << 8) |
+ (buff[2] << 16) |
+ (buff[3] << 24));
+ if (data_cnt == 0) {
+ LCDERR("%s: demura_set data_cnt error\n", __func__);
+ return -1;
+ }
+ data_checksum = buff[4];
+ data_lrc = buff[5];
+ temp_checksum = lcd_tcon_checksum(&buff[8], data_cnt);
+ temp_lrc = lcd_tcon_lrc(&buff[8], data_cnt);
+ if (data_checksum != temp_checksum) {
+ LCDERR("%s: demura_set checksum error\n", __func__);
+ return -1;
+ }
+ if (data_lrc != temp_lrc) {
+ LCDERR("%s: demura_set lrc error\n", __func__);
+ return -1;
+ }
+ if (buff[6] != 0x55 || buff[7] != 0xaa) {
+ LCDERR("%s: demura_set pattern error\n", __func__);
+ return -1;
+ }
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_ADV) {
+ for (i = 0; i < 100; i++)
+ LCDPR("demura_set[%d]: 0x%x\n", i, buff[i]);
+ }
+#endif
+ return ret;
+}
+
+static int lcd_tcon_demura_lut_load(void)
+{
+ unsigned char *buff = tcon_rmem.demura_lut_rmem.mem_vaddr;
+#ifdef CONFIG_CMD_INI
+ unsigned int i, data_cnt = 0;
+ unsigned char data_checksum, data_lrc, temp_checksum, temp_lrc;
+#endif
+ int ret = -1;
+
+ if (tcon_rmem.demura_lut_rmem.mem_size == 0 || !buff)
+ return -1;
+
+#ifdef CONFIG_CMD_INI
+ ret = handle_tcon_demura_lut(buff, tcon_rmem.demura_lut_rmem.mem_size);
+ if (ret) {
+ LCDPR("%s: no demura_lut data\n", __func__);
+ return -1;
+ }
+ data_cnt = (buff[0] |
+ (buff[1] << 8) |
+ (buff[2] << 16) |
+ (buff[3] << 24));
+ if (data_cnt == 0) {
+ LCDERR("%s: demura_lut data_cnt error\n", __func__);
+ return -1;
+ }
+ data_checksum = buff[4];
+ data_lrc = buff[5];
+ temp_checksum = lcd_tcon_checksum(&buff[8], data_cnt);
+ temp_lrc = lcd_tcon_lrc(&buff[8], data_cnt);
+ if (data_checksum != temp_checksum) {
+ LCDERR("%s: demura_lut checksum error\n", __func__);
+ return -1;
+ }
+ if (data_lrc != temp_lrc) {
+ LCDERR("%s: demura_lut lrc error\n", __func__);
+ return -1;
+ }
+ if ((buff[6] != 0x55) || (buff[7] != 0xaa)) {
+ LCDERR("%s: demura_lut pattern error\n", __func__);
+ return -1;
+ }
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_ADV) {
+ for (i = 0; i < 100; i++)
+ LCDPR("demura_lut[%d]: 0x%02x\n", i, buff[i]);
+ }
+#endif
+ return ret;
+}
+
+static int lcd_tcon_acc_lut_load(void)
+{
+ unsigned char *buff = tcon_rmem.acc_lut_rmem.mem_vaddr;
+#ifdef CONFIG_CMD_INI
+ unsigned int i, data_cnt = 0;
+ unsigned char data_checksum, data_lrc, temp_checksum, temp_lrc;
+#endif
+ int ret = -1;
+
+ if (tcon_rmem.acc_lut_rmem.mem_size == 0 || !buff)
+ return -1;
+
+#ifdef CONFIG_CMD_INI
+ ret = handle_tcon_acc_lut(buff, tcon_rmem.acc_lut_rmem.mem_size);
+ if (ret) {
+ LCDPR("%s: no acc_lut data\n", __func__);
+ return -1;
+ }
+ data_cnt = (buff[0] |
+ (buff[1] << 8) |
+ (buff[2] << 16) |
+ (buff[3] << 24));
+ if (data_cnt == 0) {
+ LCDERR("%s: acc_lut data_cnt error\n", __func__);
+ return -1;
+ }
+ data_checksum = buff[4];
+ data_lrc = buff[5];
+ temp_checksum = lcd_tcon_checksum(&buff[8], data_cnt);
+ temp_lrc = lcd_tcon_lrc(&buff[8], data_cnt);
+ if (data_checksum != temp_checksum) {
+ LCDERR("%s: acc_lut checksum error\n", __func__);
+ return -1;
+ }
+ if (data_lrc != temp_lrc) {
+ LCDERR("%s: acc_lut lrc error\n", __func__);
+ return -1;
+ }
+ if (buff[6] != 0x55 || buff[7] != 0xaa) {
+ LCDERR("%s: acc_lut pattern error\n", __func__);
+ return -1;
+ }
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_ADV) {
+ for (i = 0; i < 100; i++)
+ LCDPR("acc_lut[%d]: 0x%02x\n", i, buff[i]);
+ }
+#endif
+ return ret;
+}
+
+static int lcd_tcon_data_load(struct aml_lcd_drv_s *pdrv)
+{
+ unsigned char *table;
+#ifdef CONFIG_CMD_INI
+ struct lcd_tcon_data_block_header_s block_header;
+ struct tcon_data_priority_s *data_prio;
+ unsigned int i, j, priority, demura_cnt = 0;
+#endif
+ int ret;
+
+ ret = lcd_tcon_valid_check();
+ if (ret)
+ return -1;
+ table = tcon_mm_table.core_reg_table;
+ if (!table)
+ return 0;
+
+ if (tcon_mm_table.version == 0) {
+ if (pdrv->data->chip_type == LCD_CHIP_TL1 ||
+ pdrv->data->chip_type == LCD_CHIP_TM2) {
+ ret = lcd_tcon_vac_load();
+ if (ret == 0)
+ tcon_mm_table.valid_flag |= LCD_TCON_DATA_VALID_VAC;
+ ret = lcd_tcon_demura_set_load();
+ if (ret) {
+ table[0x178] = 0x38;
+ table[0x17c] = 0x20;
+ table[0x181] = 0x00;
+ table[0x23d] &= ~(1 << 0);
+ } else {
+ ret = lcd_tcon_demura_lut_load();
+ if (ret) {
+ table[0x178] = 0x38;
+ table[0x17c] = 0x20;
+ table[0x181] = 0x00;
+ table[0x23d] &= ~(1 << 0);
+ } else {
+ tcon_mm_table.valid_flag |=
+ LCD_TCON_DATA_VALID_DEMURA;
+ }
+ }
+ }
+
+ ret = lcd_tcon_acc_lut_load();
+ if (ret == 0)
+ tcon_mm_table.valid_flag |= LCD_TCON_DATA_VALID_ACC;
+ } else {
+ if (!tcon_mm_table.data_mem_vaddr) {
+ LCDERR("%s: data_mem error\n", __func__);
+ return -1;
+ }
+ if (!tcon_mm_table.data_priority) {
+ LCDERR("%s: data_priority error\n", __func__);
+ return -1;
+ }
+ if (!tcon_mm_table.data_size) {
+ LCDERR("%s: data_size error\n", __func__);
+ return -1;
+ }
+#ifdef CONFIG_CMD_INI
+ data_prio = tcon_mm_table.data_priority;
+ for (i = 0; i < tcon_mm_table.block_cnt; i++) {
+ ret = handle_tcon_data_load
+ (tcon_mm_table.data_mem_vaddr, i);
+ if (ret)
+ continue;
+
+ memcpy(&block_header, tcon_mm_table.data_mem_vaddr[i],
+ LCD_TCON_DATA_BLOCK_HEADER_SIZE);
+ tcon_mm_table.valid_flag |= block_header.block_flag;
+ if (block_header.block_flag ==
+ LCD_TCON_DATA_VALID_DEMURA)
+ demura_cnt++;
+
+ /* insertion sort for block data init_priority */
+ data_prio[i].index = i;
+ //data_prio[i].priority = block_header.init_priority;
+ /* update init_priority by index */
+ priority = i;
+ data_prio[i].priority = priority;
+ if (i > 0) {
+ j = i - 1;
+ while (j >= 0) {
+ if (priority > data_prio[j].priority)
+ break;
+ if (priority == data_prio[j].priority) {
+ LCDERR
+ ("%s: block %d init_priority same as block %d\n",
+ __func__,
+ data_prio[i].index,
+ data_prio[j].index);
+ return -1;
+ }
+ data_prio[j + 1].index =
+ data_prio[j].index;
+ data_prio[j + 1].priority =
+ data_prio[j].priority;
+ j--;
+ }
+ data_prio[j + 1].index = i;
+ data_prio[j + 1].priority = priority;
+ }
+ tcon_mm_table.data_size[i] = block_header.block_size;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("%s %d: block size=0x%x, type=0x%02x, name=%s, init_priority=%d\n",
+ __func__, i,
+ block_header.block_size,
+ block_header.block_type,
+ block_header.name, priority);
+ }
+ }
+
+ /* specially check demura setting */
+ if (pdrv->data->chip_type == LCD_CHIP_TL1 ||
+ pdrv->data->chip_type == LCD_CHIP_TM2) {
+ if (demura_cnt < 2) {
+ tcon_mm_table.valid_flag &=
+ ~LCD_TCON_DATA_VALID_DEMURA;
+ /* disable demura */
+ table[0x178] = 0x38;
+ table[0x17c] = 0x20;
+ table[0x181] = 0x00;
+ table[0x23d] &= ~(1 << 0);
+ }
+ }
+#endif
+ }
+
+ return 0;
+}
+
+static int lcd_tcon_bin_path_update(unsigned int size)
+{
+#ifdef CONFIG_CMD_INI
+ unsigned char *mem_vaddr;
+ unsigned int data_size;
+ unsigned int data_crc32, temp_crc32;
+
+ /* notice: different with kernel flow: mem_vaddr is not mapping to mem_paddr */
+ tcon_rmem.bin_path_rmem.mem_vaddr = handle_tcon_path_mem_get(size);
+ if (!tcon_rmem.bin_path_rmem.mem_vaddr) {
+ LCDERR("%s: get mem error\n", __func__);
+ return -1;
+ }
+ mem_vaddr = tcon_rmem.bin_path_rmem.mem_vaddr;
+ data_size = mem_vaddr[4] |
+ (mem_vaddr[5] << 8) |
+ (mem_vaddr[6] << 16) |
+ (mem_vaddr[7] << 24);
+ if (data_size < 4) {
+ LCDERR("%s: tcon_bin_path data_size error\n", __func__);
+ return -1;
+ }
+ data_crc32 = mem_vaddr[0] |
+ (mem_vaddr[1] << 8) |
+ (mem_vaddr[2] << 16) |
+ (mem_vaddr[3] << 24);
+ temp_crc32 = crc32(0, &mem_vaddr[4], (data_size - 4));
+ if (data_crc32 != temp_crc32) {
+ LCDERR("%s: tcon_bin_path data crc error\n", __func__);
+ return -1;
+ }
+
+ tcon_mm_table.version = mem_vaddr[8] |
+ (mem_vaddr[9] << 8) |
+ (mem_vaddr[10] << 16) |
+ (mem_vaddr[11] << 24);
+ tcon_mm_table.data_load_level = mem_vaddr[12] |
+ (mem_vaddr[13] << 8) |
+ (mem_vaddr[14] << 16) |
+ (mem_vaddr[15] << 24);
+ tcon_mm_table.block_cnt = mem_vaddr[16] |
+ (mem_vaddr[17] << 8) |
+ (mem_vaddr[18] << 16) |
+ (mem_vaddr[19] << 24);
+#endif
+
+ return 0;
+}
+
+static int lcd_tcon_mm_table_config_v0(void)
+{
+ unsigned int max_size;
+
+ /* reserved memory */
+ max_size = lcd_tcon_conf->axi_size +
+ lcd_tcon_conf->bin_path_size +
+ lcd_tcon_conf->vac_size +
+ lcd_tcon_conf->demura_set_size +
+ lcd_tcon_conf->demura_lut_size +
+ lcd_tcon_conf->acc_lut_size;
+ if (tcon_rmem.rsv_mem_size < max_size) {
+ LCDERR("%s: tcon mem size 0x%x is not enough, need 0x%x\n",
+ __func__, tcon_rmem.rsv_mem_size, max_size);
+ return -1;
+ }
+
+ if (tcon_mm_table.block_cnt != 4) {
+ LCDERR("%s: tcon data block_cnt %d invalid\n",
+ __func__, tcon_mm_table.block_cnt);
+ return -1;
+ }
+
+ tcon_rmem.vac_rmem.mem_size = lcd_tcon_conf->vac_size;
+ tcon_rmem.vac_rmem.mem_paddr =
+ tcon_rmem.bin_path_rmem.mem_paddr +
+ tcon_rmem.bin_path_rmem.mem_size;
+ tcon_rmem.vac_rmem.mem_vaddr =
+ (unsigned char *)(unsigned long)(tcon_rmem.vac_rmem.mem_paddr);
+ if ((lcd_debug_print_flag & LCD_DBG_PR_NORMAL) && tcon_rmem.vac_rmem.mem_size > 0)
+ LCDPR("tcon vac paddr: 0x%08x, size: 0x%x\n",
+ tcon_rmem.vac_rmem.mem_paddr,
+ tcon_rmem.vac_rmem.mem_size);
+
+ tcon_rmem.demura_set_rmem.mem_size = lcd_tcon_conf->demura_set_size;
+ tcon_rmem.demura_set_rmem.mem_paddr =
+ tcon_rmem.vac_rmem.mem_paddr + tcon_rmem.vac_rmem.mem_size;
+ tcon_rmem.demura_set_rmem.mem_vaddr = (unsigned char *)
+ (unsigned long)(tcon_rmem.demura_set_rmem.mem_paddr);
+ if ((lcd_debug_print_flag & LCD_DBG_PR_NORMAL) && tcon_rmem.demura_set_rmem.mem_size > 0)
+ LCDPR("tcon demura set_paddr: 0x%08x, size: 0x%x\n",
+ tcon_rmem.demura_set_rmem.mem_paddr,
+ tcon_rmem.demura_set_rmem.mem_size);
+
+ tcon_rmem.demura_lut_rmem.mem_size = lcd_tcon_conf->demura_lut_size;
+ tcon_rmem.demura_lut_rmem.mem_paddr =
+ tcon_rmem.demura_set_rmem.mem_paddr +
+ tcon_rmem.demura_set_rmem.mem_size;
+ tcon_rmem.demura_lut_rmem.mem_vaddr = (unsigned char *)
+ (unsigned long)(tcon_rmem.demura_lut_rmem.mem_paddr);
+ if ((lcd_debug_print_flag & LCD_DBG_PR_NORMAL) && tcon_rmem.demura_lut_rmem.mem_size > 0)
+ LCDPR("tcon demura lut_paddr: 0x%08x, size: 0x%x\n",
+ tcon_rmem.demura_lut_rmem.mem_paddr,
+ tcon_rmem.demura_lut_rmem.mem_size);
+
+ tcon_rmem.acc_lut_rmem.mem_size = lcd_tcon_conf->acc_lut_size;
+ tcon_rmem.acc_lut_rmem.mem_paddr =
+ tcon_rmem.demura_lut_rmem.mem_paddr +
+ tcon_rmem.demura_lut_rmem.mem_size;
+ tcon_rmem.acc_lut_rmem.mem_vaddr = (unsigned char *)
+ (unsigned long)(tcon_rmem.acc_lut_rmem.mem_paddr);
+ if ((lcd_debug_print_flag & LCD_DBG_PR_NORMAL) && tcon_rmem.acc_lut_rmem.mem_size > 0)
+ LCDPR("tcon acc lut_paddr: 0x%08x, size: 0x%x\n",
+ tcon_rmem.acc_lut_rmem.mem_paddr,
+ tcon_rmem.acc_lut_rmem.mem_size);
+
+ return 0;
+}
+
+static int lcd_tcon_mm_table_config_v1(void)
+{
+ if (tcon_mm_table.block_cnt > 32) {
+ LCDERR("%s: tcon data block_cnt %d invalid\n",
+ __func__, tcon_mm_table.block_cnt);
+ return -1;
+ }
+
+ if (tcon_mm_table.data_mem_vaddr)
+ return 0;
+ if (tcon_mm_table.block_cnt == 0) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s: block_cnt is zero\n", __func__);
+ return 0;
+ }
+
+ tcon_mm_table.data_mem_vaddr = (unsigned char **)malloc
+ (tcon_mm_table.block_cnt * sizeof(unsigned char *));
+ if (!tcon_mm_table.data_mem_vaddr) {
+ LCDERR("%s: Not enough memory\n", __func__);
+ return -1;
+ }
+ memset(tcon_mm_table.data_mem_vaddr, 0,
+ tcon_mm_table.block_cnt * sizeof(unsigned char *));
+
+ tcon_mm_table.data_priority = (struct tcon_data_priority_s *)malloc
+ (tcon_mm_table.block_cnt * sizeof(struct tcon_data_priority_s));
+ if (!tcon_mm_table.data_priority) {
+ LCDERR("%s: Not enough memory\n", __func__);
+ return -1;
+ }
+ memset(tcon_mm_table.data_priority, 0xff,
+ tcon_mm_table.block_cnt * sizeof(struct tcon_data_priority_s));
+
+ tcon_mm_table.data_size = (unsigned int *)malloc
+ (tcon_mm_table.block_cnt * sizeof(unsigned int));
+ if (!tcon_mm_table.data_size) {
+ LCDERR("%s: Not enough memory\n", __func__);
+ return -1;
+ }
+ memset(tcon_mm_table.data_size, 0,
+ tcon_mm_table.block_cnt * sizeof(unsigned int));
+
+ return 0;
+}
+
+static void lcd_tcon_axi_mem_config_tl1(void)
+{
+ unsigned int size[3] = {4162560, 4162560, 1960440};
+ unsigned int total_size = 0, temp_size = 0;
+ int i;
+
+ for (i = 0; i < lcd_tcon_conf->axi_bank; i++)
+ total_size += size[i];
+ if (total_size > tcon_rmem.axi_mem_size) {
+ LCDERR("%s: tcon axi_mem size 0x%x is not enough, need 0x%x\n",
+ __func__, tcon_rmem.axi_mem_size, total_size);
+ return;
+ }
+
+ tcon_rmem.axi_rmem = (struct tcon_rmem_config_s *)
+ malloc(lcd_tcon_conf->axi_bank * sizeof(struct tcon_rmem_config_s));
+ if (!tcon_rmem.axi_rmem)
+ return;
+ memset(tcon_rmem.axi_rmem, 0,
+ lcd_tcon_conf->axi_bank * sizeof(struct tcon_rmem_config_s));
+
+ for (i = 0; i < lcd_tcon_conf->axi_bank; i++) {
+ tcon_rmem.axi_rmem[i].mem_paddr = tcon_rmem.axi_mem_paddr +
+ temp_size;
+ tcon_rmem.axi_rmem[i].mem_vaddr = (unsigned char *)
+ (unsigned long)tcon_rmem.axi_rmem[i].mem_paddr;
+ tcon_rmem.axi_rmem[i].mem_size = size[i];
+ temp_size += size[i];
+ }
+}
+
+static void lcd_tcon_axi_mem_config_t5(void)
+{
+ unsigned int size[2] = {0x00800000, 0x100000};
+ unsigned int reg[2] = {0x261, 0x1a9};
+ unsigned int total_size = 0, temp_size = 0;
+ int i;
+
+ for (i = 0; i < lcd_tcon_conf->axi_bank; i++)
+ total_size += size[i];
+ if (total_size > tcon_rmem.axi_mem_size) {
+ LCDERR("%s: tcon axi_mem size 0x%x is not enough, need 0x%x\n",
+ __func__, tcon_rmem.axi_mem_size, total_size);
+ return;
+ }
+
+ temp_size = lcd_tcon_conf->axi_bank * sizeof(struct tcon_rmem_config_s);
+ tcon_rmem.axi_rmem = (struct tcon_rmem_config_s *)malloc(temp_size);
+ if (!tcon_rmem.axi_rmem)
+ return;
+ memset(tcon_rmem.axi_rmem, 0, temp_size);
+
+ temp_size = lcd_tcon_conf->axi_bank * sizeof(unsigned int);
+ lcd_tcon_conf->axi_reg = (unsigned int *)malloc(temp_size);
+ if (!lcd_tcon_conf->axi_reg) {
+ free(tcon_rmem.axi_rmem);
+ return;
+ }
+ memset(lcd_tcon_conf->axi_reg, 0, temp_size);
+
+ temp_size = 0;
+ for (i = 0; i < lcd_tcon_conf->axi_bank; i++) {
+ tcon_rmem.axi_rmem[i].mem_paddr = tcon_rmem.axi_mem_paddr + temp_size;
+ tcon_rmem.axi_rmem[i].mem_vaddr = (unsigned char *)
+ (unsigned long)tcon_rmem.axi_rmem[i].mem_paddr;
+ tcon_rmem.axi_rmem[i].mem_size = size[i];
+ temp_size += size[i];
+
+ lcd_tcon_conf->axi_reg[i] = reg[i];
+ }
+}
+
+static int lcd_tcon_mem_config(void)
+{
+ unsigned char *mem_vaddr;
+ unsigned int max_size;
+ int ret;
+
+ /* reserved memory */
+ max_size = lcd_tcon_conf->axi_size + lcd_tcon_conf->bin_path_size;
+ if (tcon_rmem.rsv_mem_size < max_size) {
+ LCDERR("%s: tcon mem size 0x%x is not enough, need 0x%x\n",
+ __func__, tcon_rmem.rsv_mem_size, max_size);
+ return -1;
+ }
+
+ tcon_rmem.axi_mem_size = lcd_tcon_conf->axi_size;
+ tcon_rmem.axi_mem_paddr = tcon_rmem.rsv_mem_paddr;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("tcon axi_mem paddr: 0x%08x, size: 0x%x\n",
+ tcon_rmem.axi_mem_paddr, tcon_rmem.axi_mem_size);
+ lcd_tcon_conf->tcon_axi_mem_config();
+
+ tcon_rmem.bin_path_rmem.mem_size = lcd_tcon_conf->bin_path_size;
+ tcon_rmem.bin_path_rmem.mem_paddr =
+ tcon_rmem.axi_mem_paddr + tcon_rmem.axi_mem_size;
+ /* don't set bin_path_rmem.mem_vaddr here */
+ if ((lcd_debug_print_flag & LCD_DBG_PR_NORMAL) && tcon_rmem.bin_path_rmem.mem_size > 0)
+ LCDPR("tcon bin_path paddr: 0x%08x, size: 0x%x\n",
+ tcon_rmem.bin_path_rmem.mem_paddr,
+ tcon_rmem.bin_path_rmem.mem_size);
+
+ /* default clear tcon rmem */
+ mem_vaddr = (unsigned char *)(unsigned long)(tcon_rmem.rsv_mem_paddr);
+ memset(mem_vaddr, 0, tcon_rmem.rsv_mem_size);
+
+ ret = lcd_tcon_bin_path_update(tcon_rmem.bin_path_rmem.mem_size);
+ if (ret)
+ return -1;
+
+ /* allocated memory, memory map table config */
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("tcon mm_table version: %d\n", tcon_mm_table.version);
+ if (tcon_mm_table.version == 0)
+ ret = lcd_tcon_mm_table_config_v0();
+ else
+ ret = lcd_tcon_mm_table_config_v1();
+
+ return ret;
+}
+
+static void lcd_tcon_config_axi_offset_default(void)
+{
+
+ tcon_rmem.rsv_mem_paddr = env_get_ulong("tcon_mem_addr", 16, 0);
+ if (tcon_rmem.rsv_mem_paddr) {
+ tcon_rmem.rsv_mem_size = lcd_tcon_conf->rsv_mem_size;
+ LCDPR("get lcd_tcon mem_addr from default\n");
+ } else {
+ LCDERR("can't find env tcon_mem_addr\n");
+ }
+}
+
+static int lcd_tcon_load_init_data_from_unifykey(void)
+{
+ int key_len, data_len, ret;
+
+ data_len = tcon_mm_table.core_reg_table_size;
+ if (!tcon_mm_table.core_reg_table) {
+ tcon_mm_table.core_reg_table = (unsigned char *)malloc
+ (sizeof(unsigned char) * data_len);
+ if (!tcon_mm_table.core_reg_table)
+ return -1;
+ }
+ memset(tcon_mm_table.core_reg_table, 0, (sizeof(unsigned char) * data_len));
+ key_len = data_len;
+ ret = lcd_unifykey_get_no_header("lcd_tcon",
+ tcon_mm_table.core_reg_table,
+ &key_len);
+ if (ret)
+ goto lcd_tcon_load_init_data_err;
+ if (key_len != data_len)
+ goto lcd_tcon_load_init_data_err;
+
+ LCDPR("tcon: load init data len: %d\n", data_len);
+ return 0;
+
+lcd_tcon_load_init_data_err:
+ free(tcon_mm_table.core_reg_table);
+ tcon_mm_table.core_reg_table = NULL;
+ LCDERR("%s: !!!!!!tcon unifykey load error!!!!!!\n", __func__);
+ return -1;
+}
+
+static int lcd_tcon_load_init_data_from_unifykey_new(void)
+{
+ int key_len, data_len;
+ unsigned char *buf, *p;
+ struct lcd_tcon_init_block_header_s *data_header;
+ int ret;
+
+ data_len = tcon_mm_table.core_reg_table_size + LCD_TCON_DATA_BLOCK_HEADER_SIZE;
+ buf = (unsigned char *)malloc(data_len * sizeof(unsigned char));
+ if (!buf)
+ return -1;
+
+ key_len = data_len;
+ ret = lcd_unifykey_get_tcon("lcd_tcon", buf, &key_len);
+ if (ret)
+ goto lcd_tcon_load_init_data_new_err;
+ if (key_len != data_len)
+ goto lcd_tcon_load_init_data_new_err;
+
+ data_header = (struct lcd_tcon_init_block_header_s *)buf;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("unifykey header:\n");
+ LCDPR("crc32 = 0x%08x\n", data_header->crc32);
+ LCDPR("block_size = %d\n", data_header->block_size);
+ LCDPR("chipid = %d\n", data_header->chipid);
+ LCDPR("name = %s\n", data_header->name);
+ }
+
+ data_len = tcon_mm_table.core_reg_table_size;
+ if (!tcon_mm_table.core_reg_table) {
+ tcon_mm_table.core_reg_table = (unsigned char *)
+ malloc(data_len * sizeof(unsigned char));
+ if (!tcon_mm_table.core_reg_table)
+ goto lcd_tcon_load_init_data_new_err;
+ memset(tcon_mm_table.core_reg_table, 0,
+ (sizeof(unsigned char) * data_len));
+ }
+ p = buf + LCD_TCON_DATA_BLOCK_HEADER_SIZE;
+ memcpy(tcon_mm_table.core_reg_table, p, data_len);
+ free(buf);
+
+ LCDPR("tcon: load init data len: %d\n", data_len);
+ return 0;
+
+lcd_tcon_load_init_data_new_err:
+ free(buf);
+ LCDERR("%s: !!!!!!tcon unifykey load error!!!!!!\n", __func__);
+ return -1;
+}
+
+static int lcd_tcon_get_config(char *dt_addr, struct aml_lcd_drv_s *pdrv,
+ int load_id)
+{
+ struct lcd_config_s *pconf = &pdrv->config;
+ int parent_offset, size;
+ char *propdata;
+ unsigned int mem_size;
+
+ if (load_id & 0x1) {
+ parent_offset = fdt_path_offset(dt_addr, "/reserved-memory");
+ size = fdt_address_cells(dt_addr, parent_offset);
+ parent_offset = fdt_path_offset(dt_addr, "/reserved-memory/linux,lcd_tcon");
+ if (parent_offset < 0) {
+ LCDERR("can't find node: /reserved-memory/linux,lcd_tcon\n");
+ } else {
+ propdata = (char *)fdt_getprop(dt_addr, parent_offset,
+ "alloc-ranges", NULL);
+ if (!propdata) {
+ LCDERR("failed to get lcd_tcon reserved-memory from dts\n");
+ lcd_tcon_config_axi_offset_default();
+ } else {
+ if (size == 2)
+ tcon_rmem.rsv_mem_paddr =
+ be32_to_cpup((((u32 *)propdata) + 1));
+ else
+ tcon_rmem.rsv_mem_paddr =
+ be32_to_cpup(((u32 *)propdata));
+ }
+
+ propdata = (char *)fdt_getprop(dt_addr, parent_offset,
+ "size", NULL);
+ if (!propdata) {
+ LCDERR("failed to get tcon size from dts\n");
+ lcd_tcon_config_axi_offset_default();
+ } else {
+ if (size == 2)
+ mem_size = be32_to_cpup((((u32 *)propdata) + 1));
+ else
+ mem_size = be32_to_cpup(((u32 *)propdata));
+
+ if (mem_size < lcd_tcon_conf->rsv_mem_size) {
+ LCDERR("tcon mem_size is not enough\n");
+ tcon_rmem.rsv_mem_paddr = 0;
+ tcon_rmem.flag = 0;
+ } else {
+ tcon_rmem.rsv_mem_size =
+ lcd_tcon_conf->rsv_mem_size;
+ }
+ }
+ }
+ } else {
+ lcd_tcon_config_axi_offset_default();
+ }
+ if (tcon_rmem.rsv_mem_paddr) {
+ tcon_rmem.flag = 1;
+ lcd_tcon_mem_config();
+ LCDPR("tcon: rsv_mem addr: 0x%x\n", tcon_rmem.rsv_mem_paddr);
+ }
+
+ tcon_mm_table.core_reg_table_size = lcd_tcon_conf->reg_table_len;
+ if (lcd_tcon_conf->core_reg_ver)
+ lcd_tcon_load_init_data_from_unifykey_new();
+ else
+ lcd_tcon_load_init_data_from_unifykey();
+
+ lcd_tcon_data_load(pdrv);
+
+ return 0;
+}
+
+static int lcd_tcon_core_flag(enum lcd_chip_e chip_type)
+{
+ int ret = 0;
+
+ switch (chip_type) {
+ case LCD_CHIP_TL1:
+ case LCD_CHIP_TM2:
+ ret = (readl(TCON_CORE_FLAG_LIC2) >> 17) & 0x1;
+ break;
+ default:
+ break;
+ }
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ if (ret)
+ LCDPR("%s: tcon invalid\n", __func__);
+ }
+
+ return ret;
+}
+
+/* **********************************
* tcon match data
* **********************************
*/
-int lcd_tcon_probe(const void *dt_blob, struct aml_lcd_drv_s *lcd_drv, int load_id)
+static struct lcd_tcon_config_s tcon_data_tl1 = {
+ .tcon_valid = 0,
+
+ .core_reg_ver = 0,
+ .core_reg_width = LCD_TCON_CORE_REG_WIDTH_TL1,
+ .reg_table_width = LCD_TCON_TABLE_WIDTH_TL1,
+ .reg_table_len = LCD_TCON_TABLE_LEN_TL1,
+ .core_reg_start = TCON_CORE_REG_START_TL1,
+
+ .reg_top_ctrl = TCON_TOP_CTRL,
+ .bit_en = BIT_TOP_EN_TL1,
+
+ .reg_core_od = REG_CORE_OD_TL1,
+ .bit_od_en = BIT_OD_EN_TL1,
+
+ .reg_ctrl_timing_base = REG_LCD_TCON_MAX,
+ .ctrl_timing_offset = CTRL_TIMING_OFFSET_TL1,
+ .ctrl_timing_cnt = CTRL_TIMING_CNT_TL1,
+
+ .axi_bank = LCD_TCON_AXI_BANK_TL1,
+
+ .rsv_mem_size = 0x00c00000, /* 12M */
+ .axi_size = 0x00a00000, /* 10M */
+ .bin_path_size = 0x00002800, /* 10K */
+ .vac_size = 0x00002000, /* 8K */
+ .demura_set_size = 0x00001000, /* 4K */
+ .demura_lut_size = 0x00120000, /* 1152K */
+ .acc_lut_size = 0x00001000, /* 4K */
+
+ .axi_reg = NULL,
+ .tcon_axi_mem_config = lcd_tcon_axi_mem_config_tl1,
+ .tcon_enable = lcd_tcon_enable_tl1,
+};
+
+static struct lcd_tcon_config_s tcon_data_t5 = {
+ .tcon_valid = 0,
+
+ .core_reg_ver = 1, /* new version with header */
+ .core_reg_width = LCD_TCON_CORE_REG_WIDTH_T5,
+ .reg_table_width = LCD_TCON_TABLE_WIDTH_T5,
+ .reg_table_len = LCD_TCON_TABLE_LEN_T5,
+ .core_reg_start = TCON_CORE_REG_START_T5,
+
+ .reg_top_ctrl = REG_LCD_TCON_MAX,
+ .bit_en = BIT_TOP_EN_T5,
+
+ .reg_core_od = REG_LCD_TCON_MAX,
+ .bit_od_en = BIT_OD_EN_T5,
+
+ .reg_ctrl_timing_base = REG_LCD_TCON_MAX,
+ .ctrl_timing_offset = CTRL_TIMING_OFFSET_T5,
+ .ctrl_timing_cnt = CTRL_TIMING_CNT_T5,
+
+ .axi_bank = LCD_TCON_AXI_BANK_T5,
+
+ .rsv_mem_size = 0x00c00000, /* 12M */
+ .axi_size = 0x00a00000, /* 9M */
+ .bin_path_size = 0x00002800, /* 10K */
+ .vac_size = 0,
+ .demura_set_size = 0,
+ .demura_lut_size = 0,
+ .acc_lut_size = 0,
+
+ .axi_reg = NULL,
+ .tcon_axi_mem_config = lcd_tcon_axi_mem_config_t5,
+ .tcon_enable = lcd_tcon_enable_t5,
+};
+
+static struct lcd_tcon_config_s tcon_data_t5d = {
+ .tcon_valid = 0,
+
+ .core_reg_ver = 1, /* new version with header */
+ .core_reg_width = LCD_TCON_CORE_REG_WIDTH_T5,
+ .reg_table_len = LCD_TCON_TABLE_LEN_T5,
+ .core_reg_start = TCON_CORE_REG_START_T5,
+
+ .reg_top_ctrl = REG_LCD_TCON_MAX,
+ .bit_en = BIT_TOP_EN_T5,
+
+ .reg_core_od = REG_LCD_TCON_MAX,
+ .bit_od_en = BIT_OD_EN_T5,
+
+ .reg_ctrl_timing_base = REG_LCD_TCON_MAX,
+ .ctrl_timing_offset = CTRL_TIMING_OFFSET_T5,
+ .ctrl_timing_cnt = CTRL_TIMING_CNT_T5,
+
+ .axi_bank = LCD_TCON_AXI_BANK_T5,
+
+ .rsv_mem_size = 0x00c00000, /* 12M */
+ .axi_size = 0x00a00000, /* 10M */
+ .bin_path_size = 0x00002800, /* 10K */
+ .vac_size = 0,
+ .demura_set_size = 0,
+ .demura_lut_size = 0,
+ .acc_lut_size = 0,
+
+ .tcon_axi_mem_config = lcd_tcon_axi_mem_config_t5,
+ .tcon_enable = lcd_tcon_enable_t5,
+};
+
+int lcd_tcon_probe(char *dt_addr, struct aml_lcd_drv_s *pdrv, int load_id)
{
int ret = 0;
- struct lcd_config_s *pconf = lcd_drv->lcd_config;
+ struct lcd_config_s *pconf = &pdrv->config;
- LCDPR("%s\n", __func__);
-
- switch (lcd_drv->chip_type) {
+ lcd_tcon_conf = NULL;
+ switch (pdrv->data->chip_type) {
+ case LCD_CHIP_TL1:
+ case LCD_CHIP_TM2:
+ if (lcd_tcon_core_flag(pdrv->data->chip_type) == 0)
+ lcd_tcon_conf = &tcon_data_tl1;
+ break;
+ case LCD_CHIP_T5:
+ case LCD_CHIP_T7:
+ lcd_tcon_conf = &tcon_data_t5;
+ break;
+ case LCD_CHIP_T5D:
+ lcd_tcon_conf = &tcon_data_t5d;
+ break;
default:
- lcd_tcon_data = NULL;
break;
}
- ret = lcd_tcon_valid_check();
- if (ret)
- return -1;
+ if (!lcd_tcon_conf)
+ return 0;
- ret = lcd_tcon_config(dt_blob, pconf, load_id);
+ switch (pconf->basic.lcd_type) {
+ case LCD_MLVDS:
+ lcd_tcon_conf->tcon_valid = 1;
+ break;
+ case LCD_P2P:
+ if (pdrv->data->chip_type == LCD_CHIP_T5D)
+ lcd_tcon_conf->tcon_valid = 0;
+ else
+ lcd_tcon_conf->tcon_valid = 1;
+ break;
+ default:
+ break;
+ }
+ if (lcd_tcon_conf->tcon_valid == 0)
+ return 0;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s\n", __func__);
+
+ memset(&tcon_rmem, 0, sizeof(struct tcon_rmem_s));
+ memset(&tcon_mm_table, 0, sizeof(struct tcon_mem_map_table_s));
+ /*must before tcon_config, for memory alloc*/
+ lcd_tcon_spi_data_probe(pdrv);
+ ret = lcd_tcon_get_config(dt_addr, pdrv, load_id);
+
+ pdrv->tcon_reg_print = lcd_tcon_reg_readback_print;
+ pdrv->tcon_table_print = lcd_tcon_reg_table_print;
+ pdrv->tcon_vac_print = lcd_tcon_vac_print;
+ pdrv->tcon_demura_print = lcd_tcon_demura_print;
+ pdrv->tcon_acc_print = lcd_tcon_acc_print;
+ pdrv->tcon_data_print = lcd_tcon_data_print;
+ pdrv->tcon_reg_read = lcd_tcon_reg_read;
+ pdrv->tcon_reg_write = lcd_tcon_reg_write;
+ pdrv->tcon_table_read = lcd_tcon_table_read;
+ pdrv->tcon_table_write = lcd_tcon_table_write;
return ret;
}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tcon.h b/drivers/amlogic/media/vout/lcd/lcd_tcon.h
index 5d9fa24..e1a71a1 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_tcon.h
+++ b/drivers/amlogic/media/vout/lcd/lcd_tcon.h
@@ -1,21 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * driver/amlogic/media/vout/lcd/aml_lcd_tcon.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef _AML_LCD_TCON_H
@@ -24,11 +9,14 @@
#define REG_LCD_TCON_MAX 0xffff
-struct lcd_tcon_data_s {
+struct lcd_tcon_config_s {
unsigned char tcon_valid;
+ unsigned int core_reg_ver;
unsigned int core_reg_width;
+ unsigned int reg_table_width;
unsigned int reg_table_len;
+ unsigned int core_reg_start;
unsigned int reg_top_ctrl;
unsigned int bit_en;
@@ -36,14 +24,66 @@
unsigned int reg_core_od;
unsigned int bit_od_en;
- unsigned int reg_core_ctrl_timing_base;
+ unsigned int reg_ctrl_timing_base;
unsigned int ctrl_timing_offset;
unsigned int ctrl_timing_cnt;
- unsigned int axi_offset_addr;
- unsigned char *reg_table;
+ unsigned int axi_bank;
- int (*tcon_enable)(struct lcd_config_s *pconf);
+ unsigned int rsv_mem_size;
+ unsigned int axi_size;
+ unsigned int bin_path_size;
+ unsigned int vac_size;
+ unsigned int demura_set_size;
+ unsigned int demura_lut_size;
+ unsigned int acc_lut_size;
+
+ unsigned int *axi_reg;
+ void (*tcon_axi_mem_config)(void);
+ int (*tcon_enable)(struct aml_lcd_drv_s *pdrv);
+ int (*tcon_disable)(struct aml_lcd_drv_s *pdrv);
+};
+
+struct tcon_rmem_config_s {
+ unsigned int mem_paddr;
+ unsigned char *mem_vaddr;
+ unsigned int mem_size;
+};
+
+struct tcon_rmem_s {
+ unsigned int flag;
+
+ unsigned int rsv_mem_paddr;
+ unsigned int axi_mem_paddr;
+ unsigned int rsv_mem_size;
+ unsigned int axi_mem_size;
+
+ struct tcon_rmem_config_s *axi_rmem;
+ struct tcon_rmem_config_s bin_path_rmem;
+
+ struct tcon_rmem_config_s vac_rmem;
+ struct tcon_rmem_config_s demura_set_rmem;
+ struct tcon_rmem_config_s demura_lut_rmem;
+ struct tcon_rmem_config_s acc_lut_rmem;
+};
+
+struct tcon_data_priority_s {
+ unsigned int index;
+ unsigned int priority;
+};
+
+struct tcon_mem_map_table_s {
+ unsigned int version;
+ unsigned int data_load_level;
+ unsigned int block_cnt;
+ unsigned int valid_flag;
+
+ unsigned int core_reg_table_size;
+ unsigned char *core_reg_table;
+
+ struct tcon_data_priority_s *data_priority;
+ unsigned int *data_size;
+ unsigned char **data_mem_vaddr;
};
/* **********************************
@@ -52,17 +92,59 @@
/* TL1 */
#define LCD_TCON_CORE_REG_WIDTH_TL1 8
+#define LCD_TCON_TABLE_WIDTH_TL1 8
#define LCD_TCON_TABLE_LEN_TL1 24000
#define LCD_TCON_AXI_BANK_TL1 3
#define BIT_TOP_EN_TL1 4
-#define REG_CORE_OD_TL1 0x5c
-#define BIT_OD_EN_TL1 6
-#define REG_CORE_CTRL_TIMING_BASE_TL1 0x1b
+#define TCON_CORE_REG_START_TL1 0x0000
+#define REG_CORE_OD_TL1 0x247
+#define BIT_OD_EN_TL1 0
+#define REG_CTRL_TIMING_BASE_TL1 0x1b
#define CTRL_TIMING_OFFSET_TL1 12
#define CTRL_TIMING_CNT_TL1 0
+/* T5 */
+#define LCD_TCON_CORE_REG_WIDTH_T5 32
+#define LCD_TCON_TABLE_WIDTH_T5 32
+#define LCD_TCON_TABLE_LEN_T5 0x18d4 /* 0x635*4 */
+#define LCD_TCON_AXI_BANK_T5 2
+
+#define BIT_TOP_EN_T5 4
+
+#define TCON_CORE_REG_START_T5 0x0100
+#define REG_CORE_OD_T5 0x247
+#define BIT_OD_EN_T5 0
+#define REG_CTRL_TIMING_BASE_T5 0x1b
+#define CTRL_TIMING_OFFSET_T5 12
+#define CTRL_TIMING_CNT_T5 0
+
+#ifdef CONFIG_CMD_INI
+void *handle_lcd_ext_buf_get(void);
+void *handle_tcon_path_mem_get(unsigned int size);
+int handle_tcon_vac(unsigned char *vac_data, unsigned int vac_mem_size);
+int handle_tcon_demura_set(unsigned char *demura_set_data,
+ unsigned int demura_set_size);
+int handle_tcon_demura_lut(unsigned char *demura_lut_data,
+ unsigned int demura_lut_size);
+int handle_tcon_acc_lut(unsigned char *acc_lut_data,
+ unsigned int acc_lut_size);
+int handle_tcon_data_load(unsigned char **buf, unsigned int index);
+#endif
+
+#define TCON_VAC_SET_PARAM_NUM 3
+#define TCON_VAC_LUT_PARAM_NUM 256
+
+int lcd_tcon_spi_data_probe(struct lcd_drv_s *lcd_drv);
+
+int lcd_tcon_valid_check(void);
+struct lcd_tcon_config_s *get_lcd_tcon_config(void);
+struct tcon_rmem_s *get_lcd_tcon_rmem(void);
+struct tcon_mem_map_table_s *get_lcd_tcon_mm_table(void);
+
+int lcd_tcon_enable_tl1(struct aml_lcd_drv_s *pdrv);
+int lcd_tcon_enable_t5(struct aml_lcd_drv_s *pdrv);
#endif
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tcon_hw.c b/drivers/amlogic/media/vout/lcd/lcd_tcon_hw.c
new file mode 100644
index 0000000..faaffce
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/lcd_tcon_hw.c
@@ -0,0 +1,888 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/io.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+#include "lcd_reg.h"
+#include "lcd_common.h"
+#include "lcd_tcon.h"
+
+static void lcd_tcon_od_check_byte(struct lcd_tcon_config_s *tcon_conf,
+ unsigned char *table)
+{
+ struct tcon_rmem_s *tcon_rmem = get_lcd_tcon_rmem();
+ unsigned int reg, bit;
+
+ if (tcon_conf->reg_core_od == REG_LCD_TCON_MAX)
+ return;
+
+ reg = tcon_conf->reg_core_od;
+ bit = tcon_conf->bit_od_en;
+ if (((table[reg] >> bit) & 1) == 0)
+ return;
+
+ if (tcon_rmem->flag == 0) {
+ table[reg] &= ~(1 << bit);
+ LCDPR("%s: invalid memory, disable od function\n", __func__);
+ }
+}
+
+static inline void lcd_tcon_od_check(struct lcd_tcon_config_s *tcon_conf,
+ unsigned int *table)
+{
+ struct tcon_rmem_s *tcon_rmem = get_lcd_tcon_rmem();
+ unsigned int reg, bit;
+
+ if (tcon_conf->reg_core_od == REG_LCD_TCON_MAX)
+ return;
+
+ reg = tcon_conf->reg_core_od;
+ bit = tcon_conf->bit_od_en;
+ if (((table[reg] >> bit) & 1) == 0)
+ return;
+
+ if (tcon_rmem->flag == 0) {
+ table[reg] &= ~(1 << bit);
+ LCDPR("%s: invalid buf, disable od function\n", __func__);
+ }
+}
+
+static void lcd_tcon_core_reg_update(struct lcd_tcon_config_s *tcon_conf,
+ struct tcon_mem_map_table_s *mm_table)
+{
+ unsigned char *table8;
+ unsigned int *table32;
+ unsigned int len, offset;
+ int i;
+
+ if (!mm_table->core_reg_table) {
+ LCDERR("%s: table is NULL\n", __func__);
+ return;
+ }
+
+ len = mm_table->core_reg_table_size;
+ offset = tcon_conf->core_reg_start;
+ if (tcon_conf->core_reg_width == 8) {
+ table8 = mm_table->core_reg_table;
+ lcd_tcon_od_check_byte(tcon_conf, table8);
+ for (i = offset; i < len; i++)
+ lcd_tcon_write_byte(i, table8[i]);
+ } else {
+ if (tcon_conf->reg_table_width == 32) {
+ len /= 4;
+ table32 = (unsigned int *)mm_table->core_reg_table;
+ lcd_tcon_od_check(tcon_conf, table32);
+ for (i = offset; i < len; i++)
+ lcd_tcon_write(i, table32[i]);
+ } else {
+ table8 = mm_table->core_reg_table;
+ lcd_tcon_od_check_byte(tcon_conf, table8);
+ for (i = offset; i < len; i++)
+ lcd_tcon_write(i, table8[i]);
+ }
+ }
+ LCDPR("tcon core regs update\n");
+}
+
+static void lcd_tcon_axi_rmem_set(struct lcd_tcon_config_s *tcon_conf)
+{
+ struct tcon_rmem_s *tcon_rmem = get_lcd_tcon_rmem();
+ unsigned int paddr, i;
+
+ if (!tcon_conf)
+ return;
+ if (!tcon_rmem)
+ return;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s\n", __func__);
+
+ if (tcon_rmem->flag == 0 || !tcon_rmem->axi_rmem) {
+ LCDERR("%s: invalid axi_mem\n", __func__);
+ return;
+ }
+
+ for (i = 0; i < tcon_conf->axi_bank; i++) {
+ paddr = tcon_rmem->axi_rmem[i].mem_paddr;
+ lcd_tcon_write(tcon_conf->axi_reg[i], paddr);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("set tcon axi_mem[%d] paddr: 0x%08x\n", i, paddr);
+ }
+}
+
+static void lcd_tcon_vac_set_tl1(unsigned int demura_valid)
+{
+ struct tcon_rmem_s *tcon_rmem = get_lcd_tcon_rmem();
+ int len, i, j, n;
+ unsigned int d0, d1, temp, dly0, dly1, set2;
+ unsigned char *buf;
+
+ buf = tcon_rmem->vac_rmem.mem_vaddr;
+ if (!buf) {
+ LCDERR("%s: vac_mem_vaddr is null\n", __func__);
+ return;
+ }
+
+ n = 8;
+ len = TCON_VAC_SET_PARAM_NUM;
+ dly0 = buf[n];
+ dly1 = buf[n + 2];
+ set2 = buf[n + 4];
+
+ n += (len * 2);
+ if (lcd_debug_print_flag & LCD_DBG_PR_ADV)
+ LCDPR("vac_set:0x%x, 0x%x, 0x%x\n", dly0, dly1, set2);
+
+ lcd_tcon_write_byte(0x0267, lcd_tcon_read_byte(0x0267) | 0xa0);
+ /*vac_cntl, 12pipe delay temp for pre_dt*/
+ lcd_tcon_write(0x2800, 0x807);
+ if (demura_valid) /* vac delay with demura */
+ lcd_tcon_write(0x2817, (0x1e | ((dly1 & 0xff) << 8)));
+ else /* vac delay without demura */
+ lcd_tcon_write(0x2817, (0x1e | ((dly0 & 0xff) << 8)));
+
+ len = TCON_VAC_LUT_PARAM_NUM;
+ if (lcd_debug_print_flag & LCD_DBG_PR_ADV)
+ LCDPR("%s: start write vac_ramt1~2\n", __func__);
+ /*write vac_ramt1: 8bit, 256 regs*/
+ for (i = 0; i < len; i++)
+ lcd_tcon_write_byte(0xa100 + i, buf[n + i * 2]);
+
+ for (i = 0; i < len; i++)
+ lcd_tcon_write_byte(0xa200 + i, buf[n + i * 2]);
+
+ /*write vac_ramt2: 8bit, 256 regs*/
+ n += (len * 2);
+ for (i = 0; i < len; i++)
+ lcd_tcon_write_byte(0xa300 + i, buf[n + i * 2]);
+
+ for (i = 0; i < len; i++)
+ lcd_tcon_write_byte(0xbc00 + i, buf[n + i * 2]);
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_ADV)
+ LCDPR("%s: write vac_ramt1~2 ok\n", __func__);
+ for (i = 0; i < len; i++)
+ lcd_tcon_read_byte(0xbc00 + i);
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_ADV)
+ LCDPR("%s: start write vac_ramt3\n", __func__);
+ /*write vac_ramt3_1~6: 24bit({data0[11:0],data1[11:0]},128 regs)*/
+ for (j = 0; j < 6; j++) {
+ n += (len * 2);
+ for (i = 0; i < (len >> 1); i++) {
+ d0 = (buf[n + (i * 4)] |
+ (buf[n + (i * 4 + 1)] << 8)) & 0xfff;
+ d1 = (buf[n + (i * 4 + 2)] |
+ (buf[n + (i * 4 + 3)] << 8)) & 0xfff;
+ temp = ((d0 << 12) | d1);
+ lcd_tcon_write((0x2900 + i + (j * 128)), temp);
+ }
+ }
+ if (lcd_debug_print_flag & LCD_DBG_PR_ADV)
+ LCDPR("%s: write vac_ramt3 ok\n", __func__);
+ for (i = 0; i < ((len >> 1) * 6); i++)
+ lcd_tcon_read(0x2900 + i);
+
+ lcd_tcon_write(0x2801, 0x0f000870); /* vac_size */
+ lcd_tcon_write(0x2802, (0x58e00d00 | (set2 & 0xff)));
+ lcd_tcon_write(0x2803, 0x80400058);
+ lcd_tcon_write(0x2804, 0x58804000);
+ lcd_tcon_write(0x2805, 0x80400000);
+ lcd_tcon_write(0x2806, 0xf080a032);
+ lcd_tcon_write(0x2807, 0x4c08a864);
+ lcd_tcon_write(0x2808, 0x10200000);
+ lcd_tcon_write(0x2809, 0x18200000);
+ lcd_tcon_write(0x280a, 0x18000004);
+ lcd_tcon_write(0x280b, 0x735244c2);
+ lcd_tcon_write(0x280c, 0x9682383d);
+ lcd_tcon_write(0x280d, 0x96469449);
+ lcd_tcon_write(0x280e, 0xaf363ce7);
+ lcd_tcon_write(0x280f, 0xc71fbb56);
+ lcd_tcon_write(0x2810, 0x953885a1);
+ lcd_tcon_write(0x2811, 0x7a7a7900);
+ lcd_tcon_write(0x2812, 0xc4640708);
+ lcd_tcon_write(0x2813, 0x4b14b08a);
+ lcd_tcon_write(0x2814, 0x4004b12c);
+ lcd_tcon_write(0x2815, 0x0);
+ /*vac_cntl,always read*/
+ lcd_tcon_write(0x2800, 0x381f);
+
+ LCDPR("tcon vac finish\n");
+}
+
+static int lcd_tcon_demura_set_tl1(void)
+{
+ struct tcon_rmem_s *tcon_rmem = get_lcd_tcon_rmem();
+ unsigned char *data_buf;
+ unsigned int data_cnt, i;
+
+ if (!tcon_rmem->demura_set_rmem.mem_vaddr) {
+ LCDERR("%s: demura_set_mem_vaddr is null\n", __func__);
+ return -1;
+ }
+
+ if (lcd_tcon_getb_byte(0x23d, 0, 1) == 0) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_ADV)
+ LCDPR("%s: demura function disabled\n", __func__);
+ return 0;
+ }
+
+ data_cnt = (tcon_rmem->demura_set_rmem.mem_vaddr[0] |
+ (tcon_rmem->demura_set_rmem.mem_vaddr[1] << 8) |
+ (tcon_rmem->demura_set_rmem.mem_vaddr[2] << 16) |
+ (tcon_rmem->demura_set_rmem.mem_vaddr[3] << 24));
+ data_buf = &tcon_rmem->demura_set_rmem.mem_vaddr[8];
+ for (i = 0; i < data_cnt; i++)
+ lcd_tcon_write_byte(0x186, data_buf[i]);
+
+ LCDPR("tcon demura_set cnt %d\n", data_cnt);
+
+ return 0;
+}
+
+static int lcd_tcon_demura_lut_tl1(void)
+{
+ struct tcon_rmem_s *tcon_rmem = get_lcd_tcon_rmem();
+ unsigned char *data_buf;
+ unsigned int data_cnt, i;
+
+ if (!tcon_rmem->demura_lut_rmem.mem_vaddr) {
+ LCDERR("%s: demura_lut_mem_vaddr is null\n", __func__);
+ return -1;
+ }
+
+ if (lcd_tcon_getb_byte(0x23d, 0, 1) == 0)
+ return 0;
+
+ /*disable demura when load lut data*/
+ lcd_tcon_setb_byte(0x23d, 0, 0, 1);
+
+ lcd_tcon_setb_byte(0x181, 1, 0, 1);
+ lcd_tcon_write_byte(0x182, 0x01);
+ lcd_tcon_write_byte(0x183, 0x86);
+ lcd_tcon_write_byte(0x184, 0x01);
+ lcd_tcon_write_byte(0x185, 0x87);
+
+ data_cnt = (tcon_rmem->demura_lut_rmem.mem_vaddr[0] |
+ (tcon_rmem->demura_lut_rmem.mem_vaddr[1] << 8) |
+ (tcon_rmem->demura_lut_rmem.mem_vaddr[2] << 16) |
+ (tcon_rmem->demura_lut_rmem.mem_vaddr[3] << 24));
+ data_buf = &tcon_rmem->demura_lut_rmem.mem_vaddr[8];
+ /* fixed 2 byte 0 for border */
+ lcd_tcon_write_byte(0x187, 0);
+ lcd_tcon_write_byte(0x187, 0);
+ for (i = 0; i < data_cnt; i++)
+ lcd_tcon_write_byte(0x187, data_buf[i]);
+
+ /*enable demura when load lut data finished*/
+ lcd_tcon_setb_byte(0x23d, 1, 0, 1);
+
+ LCDPR("tcon demura_lut cnt %d\n", data_cnt);
+ if (lcd_debug_print_flag & LCD_DBG_PR_ADV)
+ LCDPR("tcon demura 0x23d = 0x%02x\n",
+ lcd_tcon_read_byte(0x23d));
+
+ return 0;
+}
+
+static int lcd_tcon_acc_lut_tl1(void)
+{
+ struct tcon_rmem_s *tcon_rmem = get_lcd_tcon_rmem();
+ unsigned char *data_buf;
+ unsigned int data_cnt, i;
+
+ if (!tcon_rmem->acc_lut_rmem.mem_vaddr) {
+ LCDERR("%s: acc_lut_mem_vaddr is null\n", __func__);
+ return -1;
+ }
+
+ /* enable lut access, disable gamma en*/
+ lcd_tcon_setb_byte(0x262, 0x2, 0, 2);
+
+ /* write gamma lut */
+ data_cnt = (tcon_rmem->acc_lut_rmem.mem_vaddr[0] |
+ (tcon_rmem->acc_lut_rmem.mem_vaddr[1] << 8) |
+ (tcon_rmem->acc_lut_rmem.mem_vaddr[2] << 16) |
+ (tcon_rmem->acc_lut_rmem.mem_vaddr[3] << 24));
+ if (data_cnt > 1161) { /* 0xb50~0xfd8, 1161 */
+ LCDPR("%s: data_cnt %d is invalid, force to 1161\n",
+ __func__, data_cnt);
+ data_cnt = 1161;
+ }
+
+ data_buf = &tcon_rmem->acc_lut_rmem.mem_vaddr[8];
+ for (i = 0; i < data_cnt; i++)
+ lcd_tcon_write_byte((0xb50 + i), data_buf[i]);
+
+ /* enable gamma */
+ lcd_tcon_setb_byte(0x262, 0x3, 0, 2);
+
+ LCDPR("tcon acc_lut cnt %d\n", data_cnt);
+
+ return 0;
+}
+
+void lcd_tcon_axi_rmem_lut_load(unsigned int index, unsigned char *buf,
+ unsigned int size)
+{
+ struct tcon_rmem_s *tcon_rmem = get_lcd_tcon_rmem();
+ struct lcd_tcon_config_s *tcon_conf = get_lcd_tcon_config();
+
+ if (!tcon_rmem || !tcon_rmem->axi_rmem) {
+ LCDERR("axi_rmem is NULL\n");
+ return;
+ }
+ if (!tcon_conf)
+ return;
+ if (index > tcon_conf->axi_bank) {
+ LCDERR("axi_rmem index %d invalid\n", index);
+ return;
+ }
+ if (tcon_rmem->axi_rmem[index].mem_size < size) {
+ LCDERR("axi_mem[%d] size 0x%x is not enough, need 0x%x\n",
+ index, tcon_rmem->axi_rmem[index].mem_size, size);
+ return;
+ }
+
+ memcpy(tcon_rmem->axi_rmem[index].mem_vaddr, buf, size);
+}
+
+static int lcd_tcon_data_common_parse_set(unsigned char *data_buf,
+ struct lcd_tcon_data_block_header_s *block_header)
+{
+ unsigned char *p;
+ unsigned short part_cnt;
+ unsigned char part_type;
+ unsigned int size, reg, data, mask, temp, reg_base = 0;
+ struct lcd_tcon_config_s *tcon_conf = get_lcd_tcon_config();
+ struct lcd_tcon_data_block_ext_header_s *ext_header;
+ union lcd_tcon_data_part_u data_part;
+ unsigned int data_offset, offset, i, j, k, d, m, n, step = 0;
+ unsigned int reg_cnt, reg_byte, data_cnt, data_byte;
+ int ret;
+
+ if (tcon_conf)
+ reg_base = tcon_conf->core_reg_start;
+
+ p = data_buf + LCD_TCON_DATA_BLOCK_HEADER_SIZE;
+ ext_header = (struct lcd_tcon_data_block_ext_header_s *)p;
+ part_cnt = ext_header->part_cnt;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s: part_cnt: %d\n", __func__, part_cnt);
+
+ data_offset = LCD_TCON_DATA_BLOCK_HEADER_SIZE +
+ block_header->ext_header_size;
+ size = 0;
+ for (i = 0; i < part_cnt; i++) {
+ p = data_buf + data_offset;
+ part_type = p[LCD_TCON_DATA_PART_NAME_SIZE + 3];
+ if (lcd_debug_print_flag & LCD_DBG_PR_ADV) {
+ LCDPR("%s: start step %d, %s, type=0x%02x\n",
+ __func__, step, p, part_type);
+ }
+ switch (part_type) {
+ case LCD_TCON_DATA_PART_TYPE_WR_N:
+ data_part.wr_n = (struct lcd_tcon_data_part_wr_n_s *)p;
+ offset = LCD_TCON_DATA_PART_WR_N_SIZE_PRE;
+ size = offset +
+ (data_part.wr_n->reg_cnt * data_part.wr_n->reg_addr_byte) +
+ (data_part.wr_n->data_cnt * data_part.wr_n->reg_data_byte);
+ if ((size + data_offset) > block_header->block_size)
+ goto lcd_tcon_data_common_parse_set_err_size;
+ reg_cnt = data_part.wr_n->reg_cnt;
+ reg_byte = data_part.wr_n->reg_addr_byte;
+ m = offset; /* for reg */
+ n = m + (reg_cnt * reg_byte); /* for data */
+ for (j = 0; j < reg_cnt; j++) {
+ reg = 0;
+ for (d = 0; d < reg_byte; d++)
+ reg |= (p[m + d] << (d * 8));
+ if (reg < reg_base)
+ goto
+ lcd_tcon_data_common_parse_set_err_reg;
+ if (data_part.wr_n->reg_inc) {
+ for (k = 0;
+ k < data_part.wr_n->data_cnt;
+ k++) {
+ data = 0;
+ for (d = 0;
+ d < data_part.wr_n->reg_data_byte;
+ d++)
+ data |= (p[n + d] << (d * 8));
+ if (data_part.wr_n->reg_data_byte == 1)
+ lcd_tcon_write_byte((reg + k),
+ data);
+ else
+ lcd_tcon_write((reg + k), data);
+ n += data_part.wr_n->reg_data_byte;
+ }
+ } else {
+ for (k = 0;
+ k < data_part.wr_n->data_cnt;
+ k++) {
+ data = 0;
+ for (d = 0;
+ d < data_part.wr_n->reg_data_byte;
+ d++)
+ data |= (p[n + d] << (d * 8));
+ if (data_part.wr_n->reg_data_byte == 1)
+ lcd_tcon_write_byte(reg, data);
+ else
+ lcd_tcon_write(reg, data);
+ n += data_part.wr_n->reg_data_byte;
+ }
+ }
+ m += reg_byte;
+ }
+ break;
+ case LCD_TCON_DATA_PART_TYPE_WR_DDR:
+ data_part.wr_ddr =
+ (struct lcd_tcon_data_part_wr_ddr_s *)p;
+ offset = LCD_TCON_DATA_PART_WR_DDR_SIZE_PRE;
+ m = data_part.wr_ddr->data_cnt *
+ data_part.wr_ddr->data_byte;
+ size = offset + m;
+ if ((size + data_offset) > block_header->block_size)
+ goto lcd_tcon_data_common_parse_set_err_size;
+ n = data_part.wr_ddr->axi_buf_id;
+ lcd_tcon_axi_rmem_lut_load(n, &p[offset], m);
+ break;
+ case LCD_TCON_DATA_PART_TYPE_WR_MASK:
+ data_part.wr_mask =
+ (struct lcd_tcon_data_part_wr_mask_s *)p;
+ offset = LCD_TCON_DATA_PART_WR_MASK_SIZE_PRE;
+ size = offset + data_part.wr_mask->reg_addr_byte +
+ (2 * data_part.wr_mask->reg_data_byte);
+ if ((size + data_offset) > block_header->block_size)
+ goto lcd_tcon_data_common_parse_set_err_size;
+ reg_byte = data_part.wr_mask->reg_addr_byte;
+ data_byte = data_part.wr_mask->reg_data_byte;
+ m = offset; /* for reg */
+ n = m + reg_byte; /* for data */
+ reg = 0;
+ for (d = 0; d < reg_byte; d++)
+ reg |= (p[m + d] << (d * 8));
+ if (reg < reg_base)
+ goto lcd_tcon_data_common_parse_set_err_reg;
+ mask = 0;
+ for (d = 0; d < data_byte; d++)
+ mask |= (p[n + d] << (d * 8));
+ n += data_byte;
+ data = 0;
+ for (d = 0; d < data_byte; d++)
+ data |= (p[n + d] << (d * 8));
+ if (data_byte == 1)
+ lcd_tcon_update_bits_byte(reg, mask, data);
+ else
+ lcd_tcon_update_bits(reg, mask, data);
+ break;
+ case LCD_TCON_DATA_PART_TYPE_RD_MASK:
+ data_part.rd_mask =
+ (struct lcd_tcon_data_part_rd_mask_s *)p;
+ offset = LCD_TCON_DATA_PART_RD_MASK_SIZE_PRE;
+ size = offset + data_part.rd_mask->reg_addr_byte +
+ data_part.rd_mask->reg_data_byte;
+ if ((size + data_offset) > block_header->block_size)
+ goto lcd_tcon_data_common_parse_set_err_size;
+ reg_byte = data_part.rd_mask->reg_addr_byte;
+ data_byte = data_part.rd_mask->reg_data_byte;
+ m = offset; /* for reg */
+ n = m + reg_byte; /* for data */
+ reg = 0;
+ for (d = 0; d < reg_byte; d++)
+ reg |= (p[m + d] << (d * 8));
+ if (reg < reg_base)
+ goto lcd_tcon_data_common_parse_set_err_reg;
+ mask = 0;
+ for (d = 0; d < data_byte; d++)
+ mask |= (p[n + d] << (d * 8));
+ if (data_byte == 1) {
+ data = lcd_tcon_read_byte(reg) & mask;
+ if (lcd_debug_print_flag & LCD_DBG_PR_ADV) {
+ LCDPR("%s: read reg 0x%04x = 0x%02x, mask = 0x%02x\n",
+ __func__, reg, data, mask);
+ }
+ } else {
+ data = lcd_tcon_read(reg) & mask;
+ if (lcd_debug_print_flag & LCD_DBG_PR_ADV) {
+ LCDPR("%s: read reg 0x%04x = 0x%08x, mask = 0x%08x\n",
+ __func__, reg, data, mask);
+ }
+ }
+ break;
+ case LCD_TCON_DATA_PART_TYPE_CHK_WR_MASK:
+ data_part.chk_wr_mask =
+ (struct lcd_tcon_data_part_chk_wr_mask_s *)p;
+ offset = LCD_TCON_DATA_PART_CHK_WR_MASK_SIZE_PRE;
+ //include mask
+ size = offset + data_part.chk_wr_mask->reg_chk_addr_byte +
+ data_part.chk_wr_mask->reg_chk_data_byte *
+ (data_part.chk_wr_mask->data_chk_cnt + 1) +
+ data_part.chk_wr_mask->reg_wr_addr_byte +
+ data_part.chk_wr_mask->reg_wr_data_byte *
+ (data_part.chk_wr_mask->data_chk_cnt + 2);
+ if ((size + data_offset) > block_header->block_size)
+ goto lcd_tcon_data_common_parse_set_err_size;
+ reg_byte = data_part.chk_wr_mask->reg_chk_addr_byte;
+ data_cnt = data_part.chk_wr_mask->data_chk_cnt;
+ data_byte = data_part.chk_wr_mask->reg_chk_data_byte;
+ m = offset; /* for reg */
+ n = m + reg_byte; /* for data */
+ reg = 0;
+ for (d = 0; d < reg_byte; d++)
+ reg |= (p[m + d] << (d * 8));
+ if (reg < reg_base)
+ goto lcd_tcon_data_common_parse_set_err_reg;
+ mask = 0;
+ for (d = 0; d < data_byte; d++)
+ mask |= (p[n + d] << (d * 8));
+ if (data_byte == 1)
+ temp = lcd_tcon_read_byte(reg) & mask;
+ else
+ temp = lcd_tcon_read(reg) & mask;
+ n += data_byte;
+ for (j = 0; j < data_cnt; j++) {
+ data = 0;
+ for (d = 0; d < data_byte; d++)
+ data |= (p[n + d] << (d * 8));
+ if ((data & mask) == temp)
+ break;
+ n += data_byte;
+ }
+ k = j;
+
+ /* for reg */
+ m = offset + reg_byte + data_byte * (data_cnt + 1);
+ /* for data */
+ n = m + data_part.chk_wr_mask->reg_wr_addr_byte;
+ reg_byte = data_part.chk_wr_mask->reg_wr_addr_byte;
+ data_byte = data_part.chk_wr_mask->reg_wr_data_byte;
+ reg = 0;
+ for (d = 0; d < reg_byte; d++)
+ reg |= (p[m + d] << (d * 8));
+ if (reg < reg_base)
+ goto lcd_tcon_data_common_parse_set_err_reg;
+ mask = 0;
+ for (d = 0; d < data_byte; d++)
+ mask |= (p[n + d] << (d * 8));
+ n += data_byte;
+ n += data_byte * k;
+ data = 0;
+ for (d = 0; d < data_byte; d++)
+ data |= (p[n + d] << (d * 8));
+ if (data_byte == 1)
+ lcd_tcon_update_bits_byte(reg, mask, data);
+ else
+ lcd_tcon_update_bits(reg, mask, data);
+ break;
+ case LCD_TCON_DATA_PART_TYPE_CHK_EXIT:
+ data_part.chk_exit =
+ (struct lcd_tcon_data_part_chk_exit_s *)p;
+ offset = LCD_TCON_DATA_PART_CHK_EXIT_SIZE_PRE;
+ size = offset + data_part.chk_exit->reg_addr_byte +
+ (2 * data_part.chk_exit->reg_data_byte);
+ if ((size + data_offset) > block_header->block_size)
+ goto lcd_tcon_data_common_parse_set_err_size;
+ reg_byte = data_part.chk_exit->reg_addr_byte;
+ data_byte = data_part.chk_exit->reg_data_byte;
+ m = offset; /* for reg */
+ n = m + reg_byte; /* for data */
+ reg = 0;
+ for (d = 0; d < reg_byte; d++)
+ reg |= (p[m + d] << (d * 8));
+ if (reg < reg_base)
+ goto lcd_tcon_data_common_parse_set_err_reg;
+ mask = 0;
+ for (d = 0; d < data_byte; d++)
+ mask |= (p[n + d] << (d * 8));
+ n += data_byte;
+ data = 0;
+ for (d = 0; d < data_byte; d++)
+ data |= (p[n + d] << (d * 8));
+ if (data_byte == 1)
+ ret = lcd_tcon_check_bits_byte(reg, mask, data);
+ else
+ ret = lcd_tcon_check_bits(reg, mask, data);
+ if (ret) {
+ LCDPR("%s: block %s data_part %d check exit\n",
+ __func__, block_header->name, i);
+ return 0;
+ }
+ break;
+ case LCD_TCON_DATA_PART_TYPE_DELAY:
+ data_part.delay = (struct lcd_tcon_data_part_delay_s *)p;
+ size = LCD_TCON_DATA_PART_DELAY_SIZE;
+ if ((size + data_offset) > block_header->block_size)
+ goto lcd_tcon_data_common_parse_set_err_size;
+ if (data_part.delay->delay_us > 1000) {
+ m = data_part.delay->delay_us / 1000;
+ n = data_part.delay->delay_us % 1000;
+ mdelay(m);
+ if (n)
+ udelay(n);
+ }
+ break;
+ case LCD_TCON_DATA_PART_TYPE_PARAM:
+ data_part.param =
+ (struct lcd_tcon_data_part_param_s *)p;
+ offset = LCD_TCON_DATA_PART_PARAM_SIZE_PRE;
+ size = offset + data_part.param->param_size;
+ if ((size + data_offset) > block_header->block_size)
+ goto lcd_tcon_data_common_parse_set_err_size;
+ break;
+ default:
+ LCDERR("%s: unsupport part type 0x%02x\n",
+ __func__, part_type);
+ break;
+ }
+ if (lcd_debug_print_flag & LCD_DBG_PR_ADV) {
+ LCDPR("%s: end step %d, %s, type=0x%02x, size=%d\n",
+ __func__, step, p, part_type, size);
+ }
+ data_offset += size;
+ step++;
+ }
+
+ return 0;
+
+lcd_tcon_data_common_parse_set_err_reg:
+ LCDERR("%s: block %s step %d reg 0x%04x error\n",
+ __func__, block_header->name, step, reg);
+ return -1;
+
+lcd_tcon_data_common_parse_set_err_size:
+ LCDERR("%s: block %s step %d size error\n",
+ __func__, block_header->name, step);
+ return -1;
+}
+
+static int lcd_tcon_data_set(struct tcon_mem_map_table_s *mm_table)
+{
+ struct lcd_tcon_data_block_header_s block_header;
+ unsigned char *data_buf;
+ unsigned int temp_crc32;
+ int i;
+
+ if (!mm_table->data_mem_vaddr) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s: no data_mem, exit\n", __func__);
+ return 0;
+ }
+
+ if (!mm_table->data_priority) {
+ LCDERR("%s: data_priority is null\n", __func__);
+ return -1;
+ }
+
+ for (i = 0; i < mm_table->block_cnt; i++) {
+ if (mm_table->data_priority[i].index >= mm_table->block_cnt ||
+ mm_table->data_priority[i].priority == 0xff) {
+ LCDERR("%s: data index or priority is invalid\n",
+ __func__);
+ return -1;
+ }
+ data_buf =
+ mm_table->data_mem_vaddr[mm_table->data_priority[i].index];
+ if (!data_buf) {
+ LCDERR("%s: data %d buf is null\n",
+ __func__, mm_table->data_priority[i].index);
+ return -1;
+ }
+ memcpy(&block_header, data_buf,
+ LCD_TCON_DATA_BLOCK_HEADER_SIZE);
+ temp_crc32 = crc32(0, &data_buf[4],
+ (block_header.block_size - 4));
+ if (temp_crc32 != block_header.crc32) {
+ LCDERR("%s: block %d, %s data crc error\n",
+ __func__, mm_table->data_priority[i].index,
+ block_header.name);
+ continue;
+ }
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("%s: block %d, %s, init_priority %d: block_size=0x%x, block_type=0x%02x(%s)\n",
+ __func__, mm_table->data_priority[i].index,
+ block_header.name,
+ mm_table->data_priority[i].priority,
+ block_header.block_size,
+ block_header.block_type,
+ block_header.name);
+ }
+ lcd_tcon_data_common_parse_set(data_buf, &block_header);
+ }
+
+ LCDPR("%s finish\n", __func__);
+ return 0;
+}
+
+static int lcd_tcon_top_set_tl1(struct lcd_config_s *pconf)
+{
+ struct tcon_rmem_s *tcon_rmem = get_lcd_tcon_rmem();
+ unsigned int axi_reg[3] = {0x200c, 0x2013, 0x2014};
+ unsigned int paddr;
+ int i;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("%s\n", __func__);
+
+ if (tcon_rmem->flag) {
+ if (!tcon_rmem->axi_rmem) {
+ LCDERR("%s: invalid axi_mem\n", __func__);
+ } else {
+ for (i = 0; i < 3; i++) {
+ paddr = tcon_rmem->axi_rmem[i].mem_paddr;
+ lcd_tcon_write(axi_reg[i], paddr);
+ LCDPR("set tcon axi_mem paddr[%d]: 0x%08x\n",
+ i, paddr);
+ }
+ }
+ }
+
+ lcd_tcon_write(TCON_CLK_CTRL, 0x001f);
+ if (pconf->basic.lcd_type == LCD_P2P) {
+ switch (pconf->control.p2p_cfg.p2p_type) {
+ case P2P_CHPI:
+ case P2P_USIT:
+ lcd_tcon_write(TCON_TOP_CTRL, 0x8199);
+ break;
+ default:
+ lcd_tcon_write(TCON_TOP_CTRL, 0x8999);
+ break;
+ }
+ } else {
+ lcd_tcon_write(TCON_TOP_CTRL, 0x8999);
+ }
+ lcd_tcon_write(TCON_PLLLOCK_CNTL, 0x0037);
+ lcd_tcon_write(TCON_RST_CTRL, 0x003f);
+ lcd_tcon_write(TCON_RST_CTRL, 0x0000);
+ lcd_tcon_write(TCON_DDRIF_CTRL0, 0x33fff000);
+ lcd_tcon_write(TCON_DDRIF_CTRL1, 0x300300);
+
+ return 0;
+}
+
+static int lcd_tcon_top_set_t5(struct lcd_config_s *pconf)
+{
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("lcd tcon top set\n");
+
+ lcd_tcon_write(TCON_CLK_CTRL, 0x001f);
+ if (pconf->basic.lcd_type == LCD_P2P) {
+ switch (pconf->control.p2p_cfg.p2p_type) {
+ case P2P_CHPI:
+ case P2P_USIT:
+ lcd_tcon_write(TCON_TOP_CTRL, 0x8399);
+ break;
+ default:
+ lcd_tcon_write(TCON_TOP_CTRL, 0x8b99);
+ break;
+ }
+ } else {
+ lcd_tcon_write(TCON_TOP_CTRL, 0x8b99);
+ }
+ lcd_tcon_write(TCON_PLLLOCK_CNTL, 0x0037);
+ lcd_tcon_write(TCON_RST_CTRL, 0x003f);
+ lcd_tcon_write(TCON_RST_CTRL, 0x0000);
+ lcd_tcon_write(TCON_DDRIF_CTRL0, 0x33fff000);
+ lcd_tcon_write(TCON_DDRIF_CTRL1, 0x300300);
+
+ return 0;
+}
+
+int lcd_tcon_enable_tl1(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_config_s *pconf = &pdrv->config;
+ struct lcd_tcon_config_s *tcon_conf = get_lcd_tcon_config();
+ struct tcon_mem_map_table_s *mm_table = get_lcd_tcon_mm_table();
+ int ret;
+
+ ret = lcd_tcon_valid_check();
+ if (ret)
+ return -1;
+
+ /* step 1: tcon top */
+ lcd_tcon_top_set_tl1(pconf);
+
+ /* step 2: tcon_core_reg_update */
+ lcd_tcon_core_reg_update(tcon_conf, mm_table);
+ if (pconf->basic.lcd_type == LCD_P2P) {
+ switch (pconf->control.p2p_cfg.p2p_type) {
+ case P2P_CHPI:
+ lcd_phy_tcon_chpi_bbc_init_tl1(pconf);
+ break;
+ default:
+ break;
+ }
+ }
+
+ if (mm_table->valid_flag & LCD_TCON_DATA_VALID_DEMURA) {
+ if (!mm_table->valid_flag & LCD_TCON_DATA_VALID_VAC) {
+ /*enable gamma*/
+ lcd_tcon_setb_byte(0x262, 0x3, 0, 2);
+ }
+ } else {
+ /*enable gamma*/
+ lcd_tcon_setb_byte(0x262, 0x3, 0, 2);
+ }
+
+ if (mm_table->version == 0) {
+ if (mm_table->valid_flag & LCD_TCON_DATA_VALID_VAC) {
+ if (mm_table->valid_flag & LCD_TCON_DATA_VALID_DEMURA)
+ lcd_tcon_vac_set_tl1(1);
+ else
+ lcd_tcon_vac_set_tl1(0);
+ }
+ if (mm_table->valid_flag & LCD_TCON_DATA_VALID_DEMURA) {
+ lcd_tcon_demura_set_tl1();
+ lcd_tcon_demura_lut_tl1();
+ }
+ if (mm_table->valid_flag & LCD_TCON_DATA_VALID_ACC)
+ lcd_tcon_acc_lut_tl1();
+ } else {
+ lcd_tcon_data_set(mm_table);
+ }
+
+ /* step 3: tcon_top_output_set */
+ lcd_tcon_write(TCON_OUT_CH_SEL1, 0xba98); /* out swap for ch8~11 */
+
+ return 0;
+}
+
+int lcd_tcon_enable_t5(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_config_s *pconf = &pdrv->config;
+ struct lcd_tcon_config_s *tcon_conf = get_lcd_tcon_config();
+ struct tcon_mem_map_table_s *mm_table = get_lcd_tcon_mm_table();
+ int ret;
+
+ ret = lcd_tcon_valid_check();
+ if (ret)
+ return -1;
+ if (!tcon_conf)
+ return -1;
+ if (!mm_table)
+ return -1;
+
+ /* step 1: tcon top */
+ lcd_tcon_top_set_t5(pconf);
+
+ /* step 2: tcon_core_reg_update */
+ lcd_tcon_core_reg_update(tcon_conf, mm_table);
+
+ /* step 3: set axi rmem, must before tcon data */
+ lcd_tcon_axi_rmem_set(tcon_conf);
+
+ /* step 4: tcon data set */
+ if (mm_table->version)
+ lcd_tcon_data_set(mm_table);
+
+ /* step 5: tcon_top_output_set */
+ lcd_tcon_write(TCON_OUT_CH_SEL0, 0x76543210);
+ lcd_tcon_write(TCON_OUT_CH_SEL1, 0xba98);
+
+ return 0;
+}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tcon_ref.h b/drivers/amlogic/media/vout/lcd/lcd_tcon_ref.h
deleted file mode 100644
index 2f78db4..0000000
--- a/drivers/amlogic/media/vout/lcd/lcd_tcon_ref.h
+++ /dev/null
@@ -1,40992 +0,0 @@
-/*
- * driver/display/lcd/aml_lcd_tcon_ref.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
- */
-
-#ifndef _AML_LCD_TCON_REF_H
-#define _AML_LCD_TCON_REF_H
-
-#define LCD_TCON_TABLE_MAX 4096
-
-static unsigned char tcon_boe_hd_hsd_n56_1366x768[LCD_TCON_TABLE_MAX] = {
- 0x40,
- 0x44,
- 0x44,
- 0x44,
- 0x44,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x44,
- 0x44,
- 0x44,
- 0x40,
- 0x00,
- 0x00,
- 0x00,
- 0xE4,
- 0x1B,
- 0x00,
- 0x00,
- 0x0F,
- 0xC8,
- 0x00,
- 0x11,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0xC0,
- 0x6F,
- 0x00,
- 0x88,
- 0x2B,
- 0x00,
- 0x10,
- 0x32,
- 0x54,
- 0x76,
- 0x90,
- 0x06,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x07,
- 0x80,
- 0x03,
- 0x28,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x40,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x40, /* 0x05c //0x00 --> 0x40 //[6]:od_en */
- 0x00,
- 0x04,
- 0x00,
- 0x80,
- 0x0F,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x03,
- 0x80,
- 0x08,
- 0x10,
- 0x09,
- 0x20,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0xB4,
- 0x33,
- 0x00,
- 0x3B,
- 0x00,
- 0x06,
- 0x01,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0xE8,
- 0x01,
- 0x5A,
- 0x00,
- 0x2A,
- 0xE8,
- 0x00,
- 0x02,
- 0x00,
- 0x02,
- 0x3D,
- 0xA3,
- 0xC2,
- 0x33,
- 0x82,
- 0xCA,
- 0x28,
- 0xC2,
- 0x2D,
- 0x22,
- 0xB1,
- 0xFB,
- 0x1F,
- 0xA1,
- 0x56,
- 0x11,
- 0x90,
- 0xBD,
- 0x02,
- 0xD0,
- 0x14,
- 0x00,
- 0x20,
- 0x56,
- 0x55,
- 0x6E,
- 0xFF,
- 0x3F,
- 0x00,
- 0x12,
- 0xF3,
- 0xC0,
- 0x44,
- 0x04,
- 0x96,
- 0xCC,
- 0x01,
- 0xFF,
- 0x0A,
- 0x0A,
- 0x0A,
- 0x0C,
- 0x69,
- 0x40,
- 0x03,
- 0x26,
- 0x64,
- 0x88,
- 0x4C,
- 0x00,
- 0x11,
- 0xC7,
- 0x80,
- 0x32,
- 0x8E,
- 0x88,
- 0x00,
- 0x0A,
- 0x00,
- 0x08,
- 0x05,
- 0xDC,
- 0x03,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x0A,
- 0x00,
- 0x00,
- 0x20, /* 0x113: 0x00 --> 0x20, bit[5] */
- 0xAB,
- 0x42,
- 0x00,
- 0x00,
- 0x00,
- 0x01,
- 0x0C,
- 0x01,
- 0x00,
- 0x00,
- 0xC0,
- 0x03,
- 0x1E,
- 0x0C,
- 0x20,
- 0x00,
- 0x88,
- 0x08,
- 0x00,
- 0x64,
- 0xC8,
- 0x00,
- 0x00,
- 0x0A,
- 0x20,
- 0x00,
- 0xCC,
- 0x99,
- 0x33,
- 0x66,
- 0x33,
- 0x55,
- 0xAA,
- 0xBB,
- 0x77,
- 0x66,
- 0x33,
- 0x55,
- 0xAA,
- 0xBB,
- 0x77,
- 0x66,
- 0x33,
- 0x55,
- 0xAA,
- 0xBB,
- 0x77,
- 0x66,
- 0x33,
- 0x55,
- 0xAA,
- 0xBB,
- 0x77,
- 0x10,
- 0x88,
- 0x8F,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x08,
- 0x10,
- 0x18,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x30,
- 0xE8,
- 0xFC,
- 0x03,
- 0x21,
- 0x49,
- 0xFF,
- 0xFF,
- 0xFF,
- 0x04,
- 0x20,
- 0xA0,
- 0x86,
- 0x01,
- 0x03,
- 0xA0,
- 0x86,
- 0x01,
- 0xD4,
- 0x38,
- 0x34,
- 0xC0,
- 0x38,
- 0x74,
- 0x01,
- 0xF9,
- 0xC7,
- 0x11,
- 0xC7,
- 0x73,
- 0x3C,
- 0x80,
- 0xE0,
- 0xC7,
- 0x1E,
- 0x38,
- 0x6D,
- 0x60,
- 0x64,
- 0xF9,
- 0xC3,
- 0x06,
- 0x18,
- 0x9C,
- 0x40,
- 0x80,
- 0xE0,
- 0xC7,
- 0x1E,
- 0x38,
- 0x4A,
- 0x38,
- 0x64,
- 0x2C,
- 0x07,
- 0x00,
- 0x07,
- 0x0B,
- 0xB8,
- 0x80,
- 0x70,
- 0x07,
- 0x00,
- 0x07,
- 0x05,
- 0x14,
- 0x80,
- 0x3E,
- 0xCC,
- 0xCC,
- 0xCC,
- 0xFD,
- 0xE8,
- 0x80,
- 0x20,
- 0x89,
- 0x85,
- 0x22,
- 0x03,
- 0xE8,
- 0x80,
- 0x04,
- 0x50,
- 0xFF,
- 0x30,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x01,
- 0x00,
- 0x01,
- 0xF0,
- 0xFF,
- 0x02,
- 0x23,
- 0x03,
- 0x44,
- 0x29,
- 0x11,
- 0x10,
- 0x01,
- 0x00,
- 0x01,
- 0xF0,
- 0xFF,
- 0xFA,
- 0xA0,
- 0x0F,
- 0x20,
- 0x00,
- 0x00,
- 0x00,
- 0x01,
- 0x00,
- 0x02,
- 0xF0,
- 0xFF,
- 0xBC,
- 0xC2,
- 0x30,
- 0x40,
- 0x01,
- 0x14,
- 0x40,
- 0x01,
- 0x00,
- 0x02,
- 0x30,
- 0x00,
- 0xBC,
- 0xC2,
- 0x2B,
- 0x40,
- 0x01,
- 0x35,
- 0x40,
- 0x01,
- 0x00,
- 0x03,
- 0x40,
- 0x00,
- 0x79,
- 0xE2,
- 0x19,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x01,
- 0x00,
- 0x05,
- 0xF0,
- 0xFF,
- 0x79,
- 0x02,
- 0x23,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x01,
- 0x00,
- 0x02,
- 0xF0,
- 0xFF,
- 0x79,
- 0x02,
- 0x23,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x70,
- 0x50,
- 0x31,
- 0xF0,
- 0xF0,
- 0xF4,
- 0x20,
- 0x00,
- 0x10,
- 0xF0,
- 0xF0,
- 0xF0,
- 0xF0,
- 0xF0,
- 0xF0,
- 0xF0,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x10,
- 0x02,
- 0x10,
- 0x10,
- 0x10,
- 0x10,
- 0x10,
- 0x10,
- 0x04,
- 0xAA,
- 0x55,
- 0x00,
- 0x00,
- 0x00,
- 0x60,
- 0x08,
- 0x80,
- 0x00, /* 0x2b1: 0x00 */
- 0x08, /* 0x2b2: 0x08 */
- 0x05, /* 0x2b3: 0x00 --> 0x05 */
- 0x58, /* 0x2b4: 0x08 --> 0x58 */
- 0x05, /* 0x2b5: 0x05 */
- 0x58,
- 0x02,
- 0x00,
- 0x20,
- 0x01,
- 0x08,
- 0x00,
- 0x13,
- 0x00,
- 0x0C,
- 0x0D,
- 0xB7,
- 0x03,
- 0x94,
- 0x18,
- 0x00,
- 0x10,
- 0xF0,
- 0x07,
- 0x80,
- 0x20,
- 0x00,
- 0x06,
- 0x0B,
- 0x0B,
- 0x33,
- 0x0E,
- 0x1C,
- 0x2A,
- 0x38,
- 0x46,
- 0x54,
- 0x62,
- 0x69,
- 0x70,
- 0x77,
- 0x79,
- 0x7B,
- 0x7D,
- 0x7E,
- 0x02,
- 0x04,
- 0x00,
- 0x04,
- 0x00,
- 0x0D,
- 0x3E,
- 0x0E,
- 0x3C,
- 0x1F,
- 0x3A,
- 0x1F,
- 0x38,
- 0x1F,
- 0x78,
- 0x18,
- 0x78,
- 0x19,
- 0x76,
- 0x1A,
- 0x76,
- 0x1B,
- 0x74,
- 0x2C,
- 0x74,
- 0x2D,
- 0x74,
- 0x3D,
- 0x74,
- 0x6F,
- 0x00,
- 0x08,
- 0x11,
- 0x1A,
- 0x23,
- 0x2C,
- 0x2D,
- 0x3E,
- 0x10,
- 0x22,
- 0x33,
- 0x44,
- 0x55,
- 0x66,
- 0x87,
- 0x88,
- 0x4F,
- 0xA5, /* 0x30d: 0xa5 */
- 0xD7, /* 0x30e: 0x09 --> 0xd7 */
- 0x80, /* 0x30f: 0x60 --> 0x80 */
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x2B,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x01,
- 0x20,
- 0x00,
- 0x03,
- 0x40,
- 0x00,
- 0x05,
- 0x60,
- 0x00,
- 0x07,
- 0x80,
- 0x00,
- 0x09,
- 0xA0,
- 0x00,
- 0x0B,
- 0xC0,
- 0x00,
- 0x0D,
- 0xE0,
- 0x00,
- 0x0F,
- 0x00,
- 0x01,
- 0x11,
- 0x20,
- 0x01,
- 0x13,
- 0x40,
- 0x01,
- 0x15,
- 0x60,
- 0x01,
- 0x17,
- 0x80,
- 0x01,
- 0x19,
- 0xA0,
- 0x01,
- 0x1B,
- 0xC0,
- 0x01,
- 0x1D,
- 0xE0,
- 0x01,
- 0x1F,
- 0x00,
- 0x02,
- 0x21,
- 0x20,
- 0x02,
- 0x23,
- 0x40,
- 0x02,
- 0x25,
- 0x60,
- 0x02,
- 0x27,
- 0x80,
- 0x02,
- 0x29,
- 0xA0,
- 0x02,
- 0x2B,
- 0xC0,
- 0x02,
- 0x2D,
- 0xE0,
- 0x02,
- 0x2F,
- 0x00,
- 0x03,
- 0x31,
- 0x20,
- 0x03,
- 0x33,
- 0x40,
- 0x03,
- 0x35,
- 0x60,
- 0x03,
- 0x37,
- 0x80,
- 0x03,
- 0x39,
- 0xA0,
- 0x03,
- 0x3B,
- 0xC0,
- 0x03,
- 0x3D,
- 0xE0,
- 0x03,
- 0x3F,
- 0x00,
- 0x04,
- 0x41,
- 0x20,
- 0x04,
- 0x43,
- 0x40,
- 0x04,
- 0x45,
- 0x60,
- 0x04,
- 0x47,
- 0x80,
- 0x04,
- 0x49,
- 0xA0,
- 0x04,
- 0x4B,
- 0xC0,
- 0x04,
- 0x4D,
- 0xE0,
- 0x04,
- 0x4F,
- 0x00,
- 0x05,
- 0x51,
- 0x20,
- 0x05,
- 0x53,
- 0x40,
- 0x05,
- 0x55,
- 0x60,
- 0x05,
- 0x57,
- 0x80,
- 0x05,
- 0x59,
- 0xA0,
- 0x05,
- 0x5B,
- 0xC0,
- 0x05,
- 0x5D,
- 0xE0,
- 0x05,
- 0x5F,
- 0x00,
- 0x06,
- 0x61,
- 0x20,
- 0x06,
- 0x63,
- 0x40,
- 0x06,
- 0x65,
- 0x60,
- 0x06,
- 0x67,
- 0x80,
- 0x06,
- 0x69,
- 0xA0,
- 0x06,
- 0x6B,
- 0xC0,
- 0x06,
- 0x6D,
- 0xE0,
- 0x06,
- 0x6F,
- 0x00,
- 0x07,
- 0x71,
- 0x20,
- 0x07,
- 0x73,
- 0x40,
- 0x07,
- 0x75,
- 0x60,
- 0x07,
- 0x77,
- 0x80,
- 0x07,
- 0x79,
- 0xA0,
- 0x07,
- 0x7B,
- 0xC0,
- 0x07,
- 0x7D,
- 0xE0,
- 0x07,
- 0x7F,
- 0x00,
- 0x08,
- 0x81,
- 0x20,
- 0x08,
- 0x83,
- 0x40,
- 0x08,
- 0x85,
- 0x60,
- 0x08,
- 0x87,
- 0x80,
- 0x08,
- 0x89,
- 0xA0,
- 0x08,
- 0x8B,
- 0xC0,
- 0x08,
- 0x8D,
- 0xE0,
- 0x08,
- 0x8F,
- 0x00,
- 0x09,
- 0x91,
- 0x20,
- 0x09,
- 0x93,
- 0x40,
- 0x09,
- 0x95,
- 0x60,
- 0x09,
- 0x97,
- 0x80,
- 0x09,
- 0x99,
- 0xA0,
- 0x09,
- 0x9B,
- 0xC0,
- 0x09,
- 0x9D,
- 0xE0,
- 0x09,
- 0x9F,
- 0x00,
- 0x0A,
- 0xA1,
- 0x20,
- 0x0A,
- 0xA3,
- 0x40,
- 0x0A,
- 0xA5,
- 0x60,
- 0x0A,
- 0xA7,
- 0x80,
- 0x0A,
- 0xA9,
- 0xA0,
- 0x0A,
- 0xAB,
- 0xC0,
- 0x0A,
- 0xAD,
- 0xE0,
- 0x0A,
- 0xAF,
- 0x00,
- 0x0B,
- 0xB1,
- 0x20,
- 0x0B,
- 0xB3,
- 0x40,
- 0x0B,
- 0xB5,
- 0x60,
- 0x0B,
- 0xB7,
- 0x80,
- 0x0B,
- 0xB9,
- 0xA0,
- 0x0B,
- 0xBB,
- 0xC0,
- 0x0B,
- 0xBD,
- 0xE0,
- 0x0B,
- 0xBF,
- 0x00,
- 0x0C,
- 0xC1,
- 0x20,
- 0x0C,
- 0xC3,
- 0x40,
- 0x0C,
- 0xC5,
- 0x60,
- 0x0C,
- 0xC7,
- 0x80,
- 0x0C,
- 0xC9,
- 0xA0,
- 0x0C,
- 0xCB,
- 0xC0,
- 0x0C,
- 0xCD,
- 0xE0,
- 0x0C,
- 0xCF,
- 0x00,
- 0x0D,
- 0xD1,
- 0x20,
- 0x0D,
- 0xD3,
- 0x40,
- 0x0D,
- 0xD5,
- 0x60,
- 0x0D,
- 0xD7,
- 0x80,
- 0x0D,
- 0xD9,
- 0xA0,
- 0x0D,
- 0xDB,
- 0xC0,
- 0x0D,
- 0xDD,
- 0xE0,
- 0x0D,
- 0xDF,
- 0x00,
- 0x0E,
- 0xE1,
- 0x20,
- 0x0E,
- 0xE3,
- 0x40,
- 0x0E,
- 0xE5,
- 0x60,
- 0x0E,
- 0xE7,
- 0x80,
- 0x0E,
- 0xE9,
- 0xA0,
- 0x0E,
- 0xEB,
- 0xC0,
- 0x0E,
- 0xED,
- 0xE0,
- 0x0E,
- 0xEF,
- 0x00,
- 0x0F,
- 0xF1,
- 0x20,
- 0x0F,
- 0xF3,
- 0x40,
- 0x0F,
- 0xF5,
- 0x60,
- 0x0F,
- 0xF7,
- 0x80,
- 0x0F,
- 0xF9,
- 0xA0,
- 0x0F,
- 0xFB,
- 0xC0,
- 0x0F,
- 0xFD,
- 0xE0,
- 0x0F,
- 0xFF,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x01,
- 0x20,
- 0x00,
- 0x03,
- 0x40,
- 0x00,
- 0x05,
- 0x60,
- 0x00,
- 0x07,
- 0x80,
- 0x00,
- 0x09,
- 0xA0,
- 0x00,
- 0x0B,
- 0xC0,
- 0x00,
- 0x0D,
- 0xE0,
- 0x00,
- 0x0F,
- 0x00,
- 0x01,
- 0x11,
- 0x20,
- 0x01,
- 0x13,
- 0x40,
- 0x01,
- 0x15,
- 0x60,
- 0x01,
- 0x17,
- 0x80,
- 0x01,
- 0x19,
- 0xA0,
- 0x01,
- 0x1B,
- 0xC0,
- 0x01,
- 0x1D,
- 0xE0,
- 0x01,
- 0x1F,
- 0x00,
- 0x02,
- 0x21,
- 0x20,
- 0x02,
- 0x23,
- 0x40,
- 0x02,
- 0x25,
- 0x60,
- 0x02,
- 0x27,
- 0x80,
- 0x02,
- 0x29,
- 0xA0,
- 0x02,
- 0x2B,
- 0xC0,
- 0x02,
- 0x2D,
- 0xE0,
- 0x02,
- 0x2F,
- 0x00,
- 0x03,
- 0x31,
- 0x20,
- 0x03,
- 0x33,
- 0x40,
- 0x03,
- 0x35,
- 0x60,
- 0x03,
- 0x37,
- 0x80,
- 0x03,
- 0x39,
- 0xA0,
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- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x24,
- 0xD5,
-};/*end of boe hd hsd n56*/
-
-static unsigned char tcon_boe_fhd_goa_n10_1920x1080[LCD_TCON_TABLE_MAX] = {
- 0x40,
- 0x44,
- 0x44,
- 0x44,
- 0x44,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x44,
- 0x44,
- 0x44,
- 0x40,
- 0x00,
- 0x00,
- 0x00,
- 0xE4,
- 0x1B,
- 0x00,
- 0x20, /* 0x013 //0x00 --> 0x20 */
- 0x0F,
- 0xC8,
- 0x00,
- 0x11,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0xC0,
- 0x6F,
- 0x00,
- 0x88,
- 0x2B,
- 0x00,
- 0x10,
- 0x32,
- 0x54,
- 0x76,
- 0x90,
- 0x06,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x07,
- 0x80,
- 0x03,
- 0x28,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x40,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x40, /* 0x05c //0x00 --> 0x40 //[6]:od_en */
- 0x00,
- 0x04,
- 0x00,
- 0x80,
- 0x0F,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x03,
- 0x80,
- 0x08,
- 0x10,
- 0x09,
- 0x20,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0xB4,
- 0x33,
- 0x00,
- 0x3B,
- 0x00,
- 0x06,
- 0x01,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0xE8,
- 0x01,
- 0x5A,
- 0x00,
- 0x2A,
- 0xE8,
- 0x00,
- 0x02,
- 0x00,
- 0x02,
- 0x3D,
- 0xA3,
- 0xC2,
- 0x33,
- 0x82,
- 0xCA,
- 0x28,
- 0xC2,
- 0x2D,
- 0x22,
- 0xB1,
- 0xFB,
- 0x1F,
- 0xA1,
- 0x56,
- 0x11,
- 0x90,
- 0xBD,
- 0x02,
- 0xD0,
- 0x14,
- 0x00,
- 0x20,
- 0x80,
- 0x77,
- 0x98,
- 0xFF,
- 0x4F,
- 0x38,
- 0x3E,
- 0xF4,
- 0xC0,
- 0x44,
- 0x04,
- 0x96,
- 0xCC,
- 0x01,
- 0xFF,
- 0x0A,
- 0x0A,
- 0x0A,
- 0x0C,
- 0x89,
- 0x70,
- 0x04,
- 0x4C,
- 0x64,
- 0xC0,
- 0x6C,
- 0x68,
- 0x21,
- 0xD0,
- 0x80,
- 0x52,
- 0x00,
- 0x88,
- 0x00,
- 0x0A,
- 0x00,
- 0x08,
- 0x05,
- 0xDC,
- 0x03,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x38,
- 0x11,
- 0x11,
- 0x20, /* 0x113: 0x00 --> 0x20, bit[5] */
- 0x80,
- 0x37,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x0C,
- 0x01,
- 0x10,
- 0x3C,
- 0x82, /* 0x11e //0xc0 --> 0x82 */
- 0x27, /* 0x11f //0x03 --> 0x27 */
- 0x3C, /* 0x120 //0x1e --> 0x3c */
- 0x0C,
- 0x20,
- 0x00,
- 0x18,
- 0x0F, /* 0x125 //0x0b --> 0x0f */
- 0x00,
- 0x64,
- 0xC8,
- 0x00,
- 0x00,
- 0x0A,
- 0x20,
- 0x00,
- 0xCC,
- 0x99,
- 0x33,
- 0xCC,
- 0xDD,
- 0xEE,
- 0xCC,
- 0xDD,
- 0xEE,
- 0xCC,
- 0xDD,
- 0xEE,
- 0xCC,
- 0xDD,
- 0xEE,
- 0xCC,
- 0xDD,
- 0xEE,
- 0xCC,
- 0xDD,
- 0xEE,
- 0xCC,
- 0xDD,
- 0xEE,
- 0xCC,
- 0xDD,
- 0xEE,
- 0x10,
- 0x88,
- 0x8F,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x08,
- 0x10,
- 0x18,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x30,
- 0xE8,
- 0xFC,
- 0x03,
- 0x21,
- 0x49,
- 0xFF,
- 0xFF,
- 0xFF,
- 0x04,
- 0x20,
- 0xA0,
- 0x86,
- 0x01,
- 0x03,
- 0xA0,
- 0x86,
- 0x01,
- 0xD4,
- 0x38,
- 0x34,
- 0xC0,
- 0x38,
- 0x74,
- 0x01,
- 0xF9,
- 0xC7,
- 0x11,
- 0xC7,
- 0x73,
- 0x3C,
- 0x80,
- 0xE0,
- 0xC7,
- 0x1E,
- 0x38,
- 0x6D,
- 0x60,
- 0x64,
- 0xF9,
- 0xC3,
- 0x06,
- 0x18,
- 0x9C,
- 0x40,
- 0x80,
- 0xE0,
- 0xC7,
- 0x1E,
- 0x38,
- 0x4A,
- 0x38,
- 0x64,
- 0x2C,
- 0x07,
- 0x00,
- 0x07,
- 0x0B,
- 0xB8,
- 0x80,
- 0x70,
- 0x07,
- 0x00,
- 0x07,
- 0x05,
- 0x14,
- 0x80,
- 0x3E,
- 0xCC,
- 0xCC,
- 0xCC,
- 0xFD,
- 0xE8,
- 0x80,
- 0x20,
- 0x89,
- 0x85,
- 0x22,
- 0x03,
- 0xE8,
- 0x80,
- 0x04,
- 0x50,
- 0xFF,
- 0x30,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x01,
- 0x00,
- 0x01,
- 0xF0,
- 0xFF,
- 0xE9,
- 0x87,
- 0x07,
- 0x20,
- 0x0C,
- 0x01,
- 0x10,
- 0x01,
- 0x00,
- 0x01,
- 0xF0,
- 0xFF,
- 0x64,
- 0x80,
- 0x70,
- 0x24,
- 0x41,
- 0x03,
- 0x20,
- 0x01,
- 0x00,
- 0x01,
- 0xF0,
- 0xFF,
- 0x32,
- 0x20,
- 0x4E,
- 0x24,
- 0x41,
- 0x03,
- 0x20,
- 0x01,
- 0x00,
- 0x01,
- 0xF0,
- 0xFF,
- 0x32,
- 0x00,
- 0x78,
- 0x40,
- 0x01,
- 0x05,
- 0x3B,
- 0x01,
- 0x00,
- 0x01,
- 0x10,
- 0x44,
- 0xB0,
- 0x04,
- 0x4B,
- 0x44,
- 0x01,
- 0x05,
- 0x3A,
- 0x01,
- 0x00,
- 0x02,
- 0x20,
- 0x44,
- 0xB0,
- 0x04,
- 0x4B,
- 0x44,
- 0x01,
- 0x05,
- 0x39,
- 0x01,
- 0x00,
- 0x03,
- 0x30,
- 0x44,
- 0xB0,
- 0x04,
- 0x4B,
- 0x44,
- 0x01,
- 0x05,
- 0x38,
- 0x01,
- 0x00,
- 0x04,
- 0x40,
- 0x44,
- 0xB0,
- 0x04,
- 0x4B,
- 0x44,
- 0x01,
- 0x05,
- 0x37,
- 0x01,
- 0x00,
- 0x05,
- 0x50,
- 0x44,
- 0xB0,
- 0x04,
- 0x4B,
- 0x44,
- 0x01,
- 0x05,
- 0x36,
- 0x01,
- 0x00,
- 0x06,
- 0x60,
- 0x44,
- 0xB0,
- 0x04,
- 0x4B,
- 0x46,
- 0x01,
- 0x66,
- 0x25,
- 0x01,
- 0x00,
- 0x03,
- 0xA0,
- 0x43,
- 0xC8,
- 0x40,
- 0x06,
- 0x46,
- 0x01,
- 0x77,
- 0x14,
- 0x01,
- 0x00,
- 0x03,
- 0xA0,
- 0x43,
- 0xC8,
- 0x40,
- 0x06,
- 0x40,
- 0x29,
- 0x10,
- 0x10,
- 0xB4,
- 0x00,
- 0x01,
- 0xF0,
- 0xFF,
- 0x00,
- 0x00,
- 0x00,
- 0x41,
- 0x29,
- 0x10,
- 0x10,
- 0xB4,
- 0x00,
- 0x01,
- 0xF0,
- 0xFF,
- 0x00,
- 0x00,
- 0x00,
- 0x24,
- 0x41,
- 0x03,
- 0x30,
- 0x01,
- 0x00,
- 0x01,
- 0xF0,
- 0xFF,
- 0x32,
- 0x40,
- 0x06,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x90,
- 0x80,
- 0x70,
- 0x60,
- 0x50,
- 0x40,
- 0x20,
- 0x00,
- 0x10,
- 0xF0,
- 0xF0,
- 0xF0,
- 0xC0,
- 0xD0,
- 0xF0,
- 0xF0,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x00,
- 0x10,
- 0x02,
- 0x10,
- 0x10,
- 0x10,
- 0x10,
- 0x10,
- 0x10,
- 0x04,
- 0xAA,
- 0x55,
- 0x00,
- 0x00,
- 0x00,
- 0x87,
- 0x00,
- 0x80,
- 0x00,
- 0x08,
- 0x07, /* 0x2b3 //0x00 --> 0x07 */
- 0x80, /* 0x2b4 //0x08 --> 0x80 */
- 0x07,
- 0x80,
- 0x02,
- 0x00,
- 0x20,
- 0x01,
- 0x1E,
- 0x00,
- 0x1A,
- 0x00,
- 0x0C,
- 0x0D,
- 0xB7,
- 0x03,
- 0x94,
- 0x18,
- 0x00,
- 0x10,
- 0xF0,
- 0x07,
- 0x80,
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-};/*end of boe fhd goa n10*/
-
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-};
-
-#endif
-
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tcon_spi.c b/drivers/amlogic/media/vout/lcd/lcd_tcon_spi.c
new file mode 100644
index 0000000..dc01bf9
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/lcd_tcon_spi.c
@@ -0,0 +1,625 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/io.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+#include "lcd_common.h"
+#include "lcd_tcon.h"
+
+static struct lcd_tcon_spi_s tcon_spi = {
+ .block_cnt = 0,
+ .init_flag = 0,
+
+ .spi_block = NULL,
+ .ext_buf = NULL,
+
+ .data_read = NULL,
+ .data_conv = NULL,
+};
+
+struct lcd_tcon_spi_s *lcd_tcon_spi_get(void)
+{
+ return &tcon_spi;
+}
+
+static void lcd_tcon_spi_print(void)
+{
+ struct lcd_tcon_spi_block_s *spi_block;
+ int i, j;
+
+ if (tcon_spi.version == 0) {
+ LCDPR("tcon_spi invalid for version 0\n");
+ return;
+ }
+
+ printf("lcd_tcon_spi info:\n");
+ printf("version = %d\n", tcon_spi.version);
+ printf("block_cnt = %d\n", tcon_spi.block_cnt);
+ printf("init_flag = 0x%x\n", tcon_spi.init_flag);
+ if (tcon_spi.init_flag == 0)
+ return;
+ for (i = 0; i < tcon_spi.block_cnt; i++) {
+ spi_block = tcon_spi.spi_block[i];
+ printf("spi_block %d:\n"
+ "data_type 0x%02x\n"
+ "data_index %d\n"
+ "data_flag 0x%08x\n"
+ "spi_offset 0x%08x\n"
+ "spi_size 0x%08x\n"
+ "param_cnt 0x%08x\n",
+ i, spi_block->data_type,
+ spi_block->data_index, spi_block->data_flag,
+ spi_block->spi_offset, spi_block->spi_size,
+ spi_block->param_cnt);
+ for (j = 0; j < spi_block->param_cnt; j++) {
+ printf("param_%d 0x%08x\n",
+ j, spi_block->param[j]);
+ }
+ }
+ printf("\n");
+}
+
+#ifdef CONFIG_AML_LCD_EXTERN
+static int lcd_tcon_spi_ext_update(struct lcd_extern_driver_s *ext_drv)
+{
+ unsigned char *buf;
+ unsigned int size, crc;
+
+ if (!ext_drv) {
+ LCDERR("%s: ext_drv is null\n", __func__);
+ return -1;
+ }
+
+ buf = tcon_spi.ext_buf;
+
+ /* write lcd_extern unifykey and driver init_on_table */
+ memcpy(ext_drv->config->table_init_on,
+ &buf[LCD_UKEY_EXT_INIT],
+ tcon_spi.ext_init_on_cnt);
+ ext_drv->config->table_init_on_cnt = tcon_spi.ext_init_on_cnt;
+
+ /* update size & crc, then write to unifykey */
+ size = LCD_UKEY_EXT_INIT + tcon_spi.ext_init_on_cnt +
+ tcon_spi.ext_init_off_cnt;
+ buf[4] = size & 0xff;
+ buf[5] = (size >> 8) & 0xff;
+ buf[6] = (size >> 16) & 0xff;
+ buf[7] = (size >> 24) & 0xff;
+
+ crc = (unsigned int)(crc32(0, &buf[4], (size - 4)));
+ buf[0] = crc & 0xff;
+ buf[1] = (crc >> 8) & 0xff;
+ buf[2] = (crc >> 16) & 0xff;
+ buf[3] = (crc >> 24) & 0xff;
+
+ lcd_unifykey_write("lcd_extern", buf, size);
+
+ return 0;
+}
+
+static int lcd_tcon_spi_update_data(struct lcd_tcon_spi_block_s *spi_block,
+ unsigned char *cmp_buf, int flag, int i,
+ unsigned int offset, unsigned int data_len)
+{
+ if (flag) {
+ if (spi_block->data_new_size > offset + data_len) {
+ memcpy(&cmp_buf[i + 2], &spi_block->new_buf[offset],
+ data_len - 1);
+ spi_block->new_buf[0] = data_len;
+ }
+ } else {
+ memcpy(&cmp_buf[i + 1], spi_block->new_buf,
+ spi_block->data_new_size);
+ }
+
+ return 0;
+}
+
+/* for ext_data, need update cmd table when compare */
+static int lcd_tcon_spi_ext_cmp(unsigned char index,
+ struct lcd_tcon_spi_block_s *spi_block)
+{
+ unsigned char *cmp_buf, *tmp_buf;
+ unsigned int cmp_buf_size, ext_size;
+ unsigned char type, cnt;
+ int i = 0, j = 0, k;
+ unsigned int offset = 0, data_len = 0;
+ int flag = 0;
+
+ if (!spi_block->new_buf) {
+ LCDERR("%s: new_buf is null\n", __func__);
+ return -1;
+ }
+ if (!tcon_spi.ext_buf) {
+ LCDERR("%s: ext_buf is null\n", __func__);
+ return -1;
+ }
+
+ ext_size = LCD_EXTERN_INIT_ON_MAX + LCD_EXTERN_INIT_OFF_MAX;
+ tmp_buf = (unsigned char *)malloc((ext_size * sizeof(unsigned char)));
+ if (!tmp_buf) {
+ LCDERR("%s: failed to alloc tmp_buf\n", __func__);
+ return -1;
+ }
+ memset(tmp_buf, 0, (ext_size * sizeof(unsigned char)));
+
+ cmp_buf = &tcon_spi.ext_buf[LCD_UKEY_EXT_INIT];
+ cmp_buf_size = tcon_spi.ext_init_on_cnt;
+ while ((i + 1) < cmp_buf_size) {
+ type = cmp_buf[i];
+ cnt = cmp_buf[i + 1];
+ if (type == 0xff)
+ break;
+ if ((i + 2 + cnt) > cmp_buf_size)
+ break;
+ if ((((type >> 4) & 0xf) == 0xb) ||
+ (((type >> 4) & 0xf) == 0xd) ||
+ (((type >> 4) & 0xf) == 0xa)) {
+ if (index != (type & 0xf))
+ goto lcd_tcon_spi_ext_cmp_next;
+ if (((type >> 4) & 0xf) == 0xa) {
+ flag = 1;
+ data_len = cmp_buf[i + 1];
+ offset = cmp_buf[i + 2];
+ } else {
+ j = i + cnt + 2;
+ }
+
+ k = cmp_buf_size - j + tcon_spi.ext_init_off_cnt;
+ if (cnt == 0) {
+ if (spi_block->new_buf[0]) { /* new cnt */
+ /* save data behind */
+ memcpy(tmp_buf, &cmp_buf[j], k);
+ /* update current data */
+ lcd_tcon_spi_update_data(spi_block,
+ cmp_buf, flag,
+ i, offset,
+ data_len);
+ /* recover data behind */
+ j = i + spi_block->new_buf[0] + 2;
+ memcpy(&cmp_buf[j], tmp_buf, k);
+ tcon_spi.ext_init_on_cnt +=
+ spi_block->new_buf[0];
+ goto lcd_tcon_spi_ext_cmp_diff;
+ }
+ goto lcd_tcon_spi_ext_cmp_no_diff;
+ }
+ if (memcmp(&cmp_buf[i + 2], spi_block->new_buf,
+ spi_block->data_new_size)) {
+ /* save data behind */
+ memcpy(tmp_buf, &cmp_buf[j], k);
+ /* update current data */
+ lcd_tcon_spi_update_data(spi_block,
+ cmp_buf, flag,
+ i, offset,
+ data_len);
+ /* recover data behind */
+ j = i + spi_block->new_buf[0] + 2;
+ memcpy(&cmp_buf[j], tmp_buf, k);
+ tcon_spi.ext_init_on_cnt =
+ tcon_spi.ext_init_on_cnt - cnt +
+ spi_block->new_buf[0];
+ goto lcd_tcon_spi_ext_cmp_diff;
+ }
+ }
+lcd_tcon_spi_ext_cmp_next:
+ i += (cnt + 2);
+ }
+
+lcd_tcon_spi_ext_cmp_no_diff:
+ free(tmp_buf);
+ return 0;
+
+lcd_tcon_spi_ext_cmp_diff:
+ free(tmp_buf);
+ return -1;
+}
+#endif
+
+static int lcd_tcon_spi_data_cmp(struct lcd_tcon_spi_block_s *spi_block,
+ unsigned char *cmp_buf)
+{
+ unsigned int raw_data_check;
+
+ raw_data_check = cmp_buf[4] | (cmp_buf[5] << 8) |
+ (cmp_buf[6] << 16) | (cmp_buf[7] << 24);
+ if (raw_data_check != spi_block->data_raw_check)
+ return -1;
+
+ return 0;
+}
+
+static int lcd_tcon_spi_data_load(void)
+{
+ struct tcon_mem_map_table_s *mm_table = get_lcd_tcon_mm_table();
+#ifdef CONFIG_AML_LCD_EXTERN
+ struct lcd_extern_driver_s *ext_drv = NULL;
+ unsigned int ext_index;
+ unsigned int ext_need_update = 0;
+#endif
+ unsigned int i, j, size, new_size;
+ int ret;
+
+ if (tcon_spi.version == 0)
+ return 0;
+
+ if (mm_table->version == 0)
+ return 0;
+
+ if (!tcon_spi.spi_block) {
+ LCDERR("%s: spi_block buf is null\n", __func__);
+ return -1;
+ }
+
+ if (!tcon_spi.data_read) {
+ LCDERR("%s: data_read is null\n", __func__);
+ return -1;
+ }
+ if (!tcon_spi.data_conv) {
+ LCDERR("%s: data_conv is null\n", __func__);
+ return -1;
+ }
+
+ for (i = 0; i < tcon_spi.block_cnt; i++) {
+ switch (tcon_spi.spi_block[i]->data_type) {
+ case LCD_TCON_DATA_BLOCK_TYPE_DEMURA_LUT:
+ case LCD_TCON_DATA_BLOCK_TYPE_ACC_LUT:
+ if (!mm_table->data_mem_vaddr) {
+ LCDERR("%s %d: data_mem error\n", __func__, i);
+ continue;
+ }
+ ret = tcon_spi.data_read(tcon_spi.spi_block[i]);
+ if (ret)
+ continue;
+
+ j = tcon_spi.spi_block[i]->data_index;
+
+ /* update tcon data buf */
+ if (!mm_table->data_mem_vaddr[j]) {
+ /* no default bin file exist */
+ ret = tcon_spi.data_conv(tcon_spi.spi_block[i]);
+ if (ret)
+ continue;
+ if (!tcon_spi.spi_block[i]->new_buf) {
+ LCDERR("%s: spi_block[%d] new_buf is null\n",
+ __func__, i);
+ continue;
+ }
+ /* note: all the tcon data buf size must align to 32byte */
+ new_size = lcd_tcon_data_size_align(tcon_spi.spi_block[i]->data_new_size);
+ mm_table->data_mem_vaddr[j] = (unsigned char *)malloc(new_size);
+ if (!mm_table->data_mem_vaddr[j]) {
+ LCDERR("%s: Not enough memory\n",
+ __func__);
+ continue;
+ }
+ memset(mm_table->data_mem_vaddr[j], 0, new_size);
+ memcpy(mm_table->data_mem_vaddr[j],
+ tcon_spi.spi_block[i]->new_buf,
+ tcon_spi.spi_block[i]->data_new_size);
+ } else {
+ ret = lcd_tcon_spi_data_cmp(tcon_spi.spi_block[i],
+ mm_table->data_mem_vaddr[j]);
+ if (ret == 0)
+ continue;
+
+ ret = tcon_spi.data_conv(tcon_spi.spi_block[i]);
+ if (ret) {
+ free(mm_table->data_mem_vaddr[j]);
+ mm_table->data_mem_vaddr[j] = NULL;
+ LCDERR("%s: block_data[%d] disabled\n",
+ __func__, i);
+ continue;
+ }
+ if (!tcon_spi.spi_block[i]->new_buf) {
+ LCDERR("%s: spi_block[%d] new_buf is null\n",
+ __func__, i);
+ continue;
+ }
+ size = mm_table->data_mem_vaddr[j][8] |
+ (mm_table->data_mem_vaddr[j][9] << 8) |
+ (mm_table->data_mem_vaddr[j][10] << 16) |
+ (mm_table->data_mem_vaddr[j][11] << 24);
+ if (tcon_spi.spi_block[i]->data_new_size > size) {
+ LCDERR("%s: block_data[%d] size is not match\n",
+ __func__, i);
+ continue;
+ }
+ new_size = lcd_tcon_data_size_align(size);
+ memset(mm_table->data_mem_vaddr[j], 0, new_size);
+ memcpy(mm_table->data_mem_vaddr[j],
+ tcon_spi.spi_block[i]->new_buf,
+ tcon_spi.spi_block[i]->data_new_size);
+ }
+ break;
+ case LCD_TCON_DATA_BLOCK_TYPE_EXT: /* pmu */
+#ifdef CONFIG_AML_LCD_EXTERN
+ if (!tcon_spi.ext_buf)
+ break;
+ ext_index = (tcon_spi.spi_block[i]->data_index >> 8) &
+ 0xff;
+ if (ext_drv) {
+ if (ext_drv->config->index != ext_index) {
+ LCDERR
+ ("%s: don't support multi ext device for tcon data\n",
+ __func__);
+ continue;
+ }
+ } else {
+ ext_drv = lcd_extern_get_driver(ext_index);
+ if (!ext_drv)
+ break;
+ }
+ tcon_spi.ext_init_on_cnt =
+ ext_drv->config->table_init_on_cnt;
+ tcon_spi.ext_init_off_cnt =
+ ext_drv->config->table_init_off_cnt;
+
+ j = tcon_spi.spi_block[i]->data_index & 0xff;
+ ret = tcon_spi.data_read(tcon_spi.spi_block[i]);
+ if (ret)
+ continue;
+ ret = tcon_spi.data_conv(tcon_spi.spi_block[i]);
+ if (ret)
+ continue;
+ if (!tcon_spi.spi_block[i]->new_buf) {
+ LCDERR("%s: spi_block[%d] new_buf is null\n",
+ __func__, i);
+ continue;
+ }
+ ret = lcd_tcon_spi_ext_cmp(j, tcon_spi.spi_block[i]);
+ if (ret)
+ ext_need_update = 1;
+#endif
+ break;
+ default:
+ break;
+ }
+ }
+#ifdef CONFIG_AML_LCD_EXTERN
+ if (ext_need_update)
+ lcd_tcon_spi_ext_update(ext_drv);
+#endif
+
+ for (i = 0; i < tcon_spi.block_cnt; i++) {
+ if (tcon_spi.spi_block[i]->param) {
+ free(tcon_spi.spi_block[i]->param);
+ tcon_spi.spi_block[i]->param = NULL;
+ }
+ if (tcon_spi.spi_block[i]->raw_buf) {
+ free(tcon_spi.spi_block[i]->raw_buf);
+ tcon_spi.spi_block[i]->raw_buf = NULL;
+ }
+ if (tcon_spi.spi_block[i]->temp_buf) {
+ free(tcon_spi.spi_block[i]->temp_buf);
+ tcon_spi.spi_block[i]->temp_buf = NULL;
+ }
+ if (tcon_spi.spi_block[i]->new_buf) {
+ free(tcon_spi.spi_block[i]->new_buf);
+ tcon_spi.spi_block[i]->new_buf = NULL;
+ }
+ }
+
+ return 0;
+}
+
+static int lcd_tcon_spi_data_parse(void)
+{
+ unsigned char *para, *p;
+#ifdef CONFIG_AML_LCD_EXTERN
+ unsigned int ext_size;
+#ifdef CONFIG_CMD_INI
+ unsigned char *data_buf = (unsigned char *)handle_lcd_ext_buf_get();
+ unsigned int data_buf_size;
+#endif
+#endif
+ struct lcd_tcon_spi_unifykey_header_s spi_header;
+ unsigned int i, j, n, block_size;
+ int key_len, len, ret;
+
+ if (tcon_spi.init_flag) /* already parsed */
+ return 0;
+
+ ret = lcd_unifykey_check_exist("lcd_tcon_spi");
+ if (ret)
+ return -1;
+
+ para = (unsigned char *)
+ malloc(sizeof(unsigned char) * LCD_UKEY_TCON_SPI_SIZE);
+ if (!para) {
+ LCDERR("%s: Not enough memory\n", __func__);
+ return -1;
+ }
+ key_len = LCD_UKEY_TCON_SPI_SIZE;
+ memset(para, 0, (sizeof(unsigned char) * key_len));
+ ret = lcd_unifykey_get("lcd_tcon_spi", para, &key_len);
+ if (ret)
+ goto lcd_tcon_spi_data_parse_err0;
+
+ /* check lcd_tcon_spi unifykey length */
+ len = 10;
+ ret = lcd_unifykey_len_check(key_len, len);
+ if (ret) {
+ LCDERR("lcd_tcon_spi unifykey length is not correct\n");
+ goto lcd_tcon_spi_data_parse_err0;
+ }
+
+ /* header: 16byte */
+ memcpy(&spi_header, para, LCD_UKEY_TCON_SPI_HEAD_SIZE);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("lcd_tcon_spi unifykey header:\n");
+ LCDPR("crc32 = 0x%08x\n", spi_header.crc32);
+ LCDPR("data_size = %d\n", spi_header.data_size);
+ LCDPR("version = %d\n", spi_header.version);
+ LCDPR("block_cnt = %d\n", spi_header.block_cnt);
+ }
+ tcon_spi.version = spi_header.version;
+ tcon_spi.block_cnt = spi_header.block_cnt;
+ if (tcon_spi.version == 0) {
+ free(para);
+ return 0;
+ }
+ if (tcon_spi.block_cnt == 0) {
+ LCDERR("%s: block_cnt 0, exit\n", __func__);
+ free(para);
+ return 0;
+ }
+ if (tcon_spi.block_cnt > LCD_UKEY_TCON_SPI_BLOCK_CNT_MAX) {
+ LCDERR("%s: lcd_tcon_spi block_cnt %d out of support(max %d), limit to %d\n",
+ __func__, tcon_spi.block_cnt,
+ LCD_UKEY_TCON_SPI_BLOCK_CNT_MAX,
+ LCD_UKEY_TCON_SPI_BLOCK_CNT_MAX);
+ tcon_spi.block_cnt = LCD_UKEY_TCON_SPI_BLOCK_CNT_MAX;
+ }
+
+ len = LCD_UKEY_TCON_SPI_HEAD_SIZE + LCD_UKEY_TCON_SPI_BLOCK_SIZE_PRE;
+ ret = lcd_unifykey_len_check(key_len, len);
+ if (ret) {
+ LCDERR("lcd_tcon_spi unifykey length is not correct\n");
+ goto lcd_tcon_spi_data_parse_err0;
+ }
+
+ tcon_spi.spi_block = (struct lcd_tcon_spi_block_s **)malloc
+ (tcon_spi.block_cnt * sizeof(struct lcd_tcon_spi_block_s *));
+ if (!tcon_spi.spi_block) {
+ LCDERR("failed to alloc tcon_spi\n");
+ goto lcd_tcon_spi_data_parse_err0;
+ }
+ memset(tcon_spi.spi_block, 0,
+ (tcon_spi.block_cnt * sizeof(struct lcd_tcon_spi_block_s *)));
+
+ len = LCD_UKEY_TCON_SPI_HEAD_SIZE;
+ p = para + len;
+#ifdef CONFIG_AML_LCD_EXTERN
+ ext_size = LCD_UKEY_EXT_INIT + LCD_EXTERN_INIT_ON_MAX +
+ LCD_EXTERN_INIT_OFF_MAX;
+#endif
+ for (i = 0; i < tcon_spi.block_cnt; i++) {
+ tcon_spi.spi_block[i] = (struct lcd_tcon_spi_block_s *)malloc
+ (sizeof(struct lcd_tcon_spi_block_s));
+ if (!tcon_spi.spi_block[i]) {
+ LCDERR("failed to alloc tcon_spi_block\n");
+ for (j = 0; j < i; j++) {
+ free(tcon_spi.spi_block[j]);
+ tcon_spi.spi_block[j] = NULL;
+ }
+ goto lcd_tcon_spi_data_parse_err1;
+ }
+ memset(tcon_spi.spi_block[i], 0,
+ sizeof(struct lcd_tcon_spi_block_s));
+ memcpy(tcon_spi.spi_block[i], p,
+ LCD_UKEY_TCON_SPI_BLOCK_SIZE_PRE);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("lcd_tcon_spi block %d:\n", i);
+ LCDPR(" data_type = 0x%02x\n",
+ tcon_spi.spi_block[i]->data_type);
+ LCDPR(" data_index = %d\n",
+ tcon_spi.spi_block[i]->data_index);
+ LCDPR(" data_flag = %d\n",
+ tcon_spi.spi_block[i]->data_flag);
+ LCDPR(" spi_offset = 0x%08x\n",
+ tcon_spi.spi_block[i]->spi_offset);
+ LCDPR(" spi_size = 0x%08x\n",
+ tcon_spi.spi_block[i]->spi_size);
+ LCDPR(" param_cnt = %d\n",
+ tcon_spi.spi_block[i]->param_cnt);
+ }
+
+ block_size = LCD_UKEY_TCON_SPI_BLOCK_SIZE_PRE +
+ tcon_spi.spi_block[i]->param_cnt * 4;
+ len += block_size;
+ ret = lcd_unifykey_len_check(key_len, len);
+ if (ret) {
+ LCDERR("lcd_tcon_spi unifykey length is incorrect\n");
+ goto lcd_tcon_spi_data_parse_err0;
+ }
+
+ if (tcon_spi.spi_block[i]->param_cnt > 0) {
+ tcon_spi.spi_block[i]->param = (unsigned int *)malloc
+ (tcon_spi.spi_block[i]->param_cnt * sizeof(unsigned int));
+ if (!tcon_spi.spi_block[i]->param) {
+ LCDERR("failed to alloc spi_block[%d] param\n", i);
+ for (j = 0; j <= i; j++) {
+ free(tcon_spi.spi_block[j]);
+ tcon_spi.spi_block[j] = NULL;
+ }
+ goto lcd_tcon_spi_data_parse_err1;
+ }
+ memset(tcon_spi.spi_block[i]->param, 0,
+ tcon_spi.spi_block[i]->param_cnt * sizeof(unsigned int));
+ n = LCD_UKEY_TCON_SPI_BLOCK_SIZE_PRE;
+ for (j = 0; j < tcon_spi.spi_block[i]->param_cnt; j++) {
+ tcon_spi.spi_block[i]->param[j] = p[n] |
+ (p[n + 1] << 8) |
+ (p[n + 2] << 16) |
+ (p[n + 3] << 24);
+ n += 4;
+ }
+ }
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ if (tcon_spi.spi_block[i]->data_type == LCD_TCON_DATA_BLOCK_TYPE_EXT &&
+ !tcon_spi.ext_buf) {
+ tcon_spi.ext_buf = (unsigned char *)malloc
+ ((ext_size * sizeof(unsigned char)));
+ if (!tcon_spi.ext_buf) {
+ LCDERR("failed to alloc ext_buf\n");
+ for (j = 0; j <= i; j++) {
+ free(tcon_spi.spi_block[j]->raw_buf);
+ tcon_spi.spi_block[j]->raw_buf = NULL;
+ if (tcon_spi.spi_block[j]->param) {
+ free(tcon_spi.spi_block[j]->param);
+ tcon_spi.spi_block[j]->param = NULL;
+ }
+ free(tcon_spi.spi_block[j]);
+ tcon_spi.spi_block[j] = NULL;
+ }
+ goto lcd_tcon_spi_data_parse_err1;
+ }
+ memset(tcon_spi.ext_buf, 0,
+ (ext_size * sizeof(unsigned char)));
+#ifdef CONFIG_CMD_INI
+ if (data_buf) {
+ data_buf_size = data_buf[4] |
+ (data_buf[5] << 8) |
+ (data_buf[6] << 16) |
+ (data_buf[7] << 24);
+ memcpy(tcon_spi.ext_buf, data_buf,
+ data_buf_size);
+ }
+#endif
+ }
+#endif
+ p += block_size;
+ }
+
+ tcon_spi.init_flag = 1;
+
+ free(para);
+ return 0;
+
+lcd_tcon_spi_data_parse_err1:
+ free(tcon_spi.spi_block);
+ tcon_spi.spi_block = NULL;
+lcd_tcon_spi_data_parse_err0:
+ free(para);
+ return -1;
+}
+
+int lcd_tcon_spi_data_probe(struct lcd_drv_s *lcd_drv)
+{
+ int ret;
+
+ ret = lcd_tcon_spi_data_parse();
+ if (ret)
+ return -1;
+
+ lcd_drv->lcd_tcon_spi_print = lcd_tcon_spi_print;
+ lcd_drv->lcd_tcon_spi_data_load = lcd_tcon_spi_data_load;
+
+ return 0;
+}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tv/Kconfig b/drivers/amlogic/media/vout/lcd/lcd_tv/Kconfig
index 8b55478..4b64852 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_tv/Kconfig
+++ b/drivers/amlogic/media/vout/lcd/lcd_tv/Kconfig
@@ -1,5 +1,5 @@
config AML_LCD_TV
bool "lcd_tv output"
+ depends on AML_LCD
help
Support for lcd tv mode output
-
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c
index eb00428..3baec2c 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_tv/lcd_drv.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -29,13 +14,14 @@
static int lcd_type_supported(struct lcd_config_s *pconf)
{
- int lcd_type = pconf->lcd_basic.lcd_type;
+ int lcd_type = pconf->basic.lcd_type;
int ret = -1;
switch (lcd_type) {
case LCD_LVDS:
case LCD_VBYONE:
case LCD_MLVDS:
+ case LCD_P2P:
ret = 0;
break;
default:
@@ -46,278 +32,119 @@
return ret;
}
-static void lcd_vbyone_phy_set(struct lcd_config_s *pconf, int status)
+static void lcd_lvds_clk_util_set(struct aml_lcd_drv_s *pdrv)
{
- unsigned int vswing, preem, ext_pullup;
- unsigned int data32;
- unsigned int rinner_table[] = {0xa, 0xa, 0x6, 0x4};
+ unsigned int reg_phy_tx_ctrl0, reg_phy_tx_ctrl1;
+ unsigned int bit_data_in_lvds, bit_data_in_edp, bit_lane_sel;
+ unsigned int phy_div, val_lane_sel, len_lane_sel;
- if (lcd_debug_print_flag)
- LCDPR("%s: %d\n", __func__, status);
-
- if (status) {
- ext_pullup = (pconf->lcd_control.vbyone_config->phy_vswing >> 4) & 0x3;
- vswing = pconf->lcd_control.vbyone_config->phy_vswing & 0xf;
- preem = pconf->lcd_control.vbyone_config->phy_preem;
- if (vswing > 7) {
- LCDERR("%s: wrong vswing_level=%d, use default\n",
- __func__, vswing);
- vswing = VX1_PHY_VSWING_DFT;
- }
- if (preem > 7) {
- LCDERR("%s: wrong preemphasis_level=%d, use default\n",
- __func__, preem);
- preem = VX1_PHY_PREEM_DFT;
- }
- if (ext_pullup)
- data32 = VX1_PHY_CNTL1_G9TV_PULLUP | (vswing << 3);
- else
- data32 = VX1_PHY_CNTL1_G9TV | (vswing << 3);
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
- data32 = VX1_PHY_CNTL2_G9TV | (preem << 20) |
- (rinner_table[ext_pullup] << 8);
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
- data32 = VX1_PHY_CNTL3_G9TV;
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
- } else {
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0);
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0);
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0);
- }
-}
-
-static void lcd_lvds_phy_set(struct lcd_config_s *pconf, int status)
-{
- unsigned int vswing, preem, clk_vswing, clk_preem, channel_on;
- unsigned int data32;
-
- if (lcd_debug_print_flag)
- LCDPR("%s: %d\n", __func__, status);
-
- if (status) {
- vswing = pconf->lcd_control.lvds_config->phy_vswing;
- preem = pconf->lcd_control.lvds_config->phy_preem;
- clk_vswing = pconf->lcd_control.lvds_config->phy_clk_vswing;
- clk_preem = pconf->lcd_control.lvds_config->phy_clk_preem;
- if (vswing > 7) {
- LCDERR("%s: wrong vswing_level=%d, use default\n",
- __func__, vswing);
- vswing = LVDS_PHY_VSWING_DFT;
- }
- channel_on = lcd_lvds_channel_on_value(pconf);
-
- if (preem > 7) {
- LCDERR("%s: wrong preemphasis_level=%d, use default\n",
- __func__, preem);
- preem = LVDS_PHY_PREEM_DFT;
- }
- if (clk_vswing > 3) {
- LCDERR("%s: wrong clk_vswing_level=%d, use default\n",
- __func__, clk_vswing);
- clk_vswing = LVDS_PHY_CLK_VSWING_DFT;
- }
- if (clk_preem > 7) {
- LCDERR("%s: wrong clk_preem_level=%d, use default\n",
- __func__, clk_preem);
- clk_preem = LVDS_PHY_CLK_PREEM_DFT;
- }
-
- data32 = LVDS_PHY_CNTL1_G9TV |
- (vswing << 26) | (preem << 0);
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
- /*lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x6c6cca80);*/
- data32 = LVDS_PHY_CNTL2_G9TV;
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
- data32 = LVDS_PHY_CNTL3_G9TV |
- (channel_on << 16) | /* DIF_TX_CTL5 */
- (clk_vswing << 8) | (clk_preem << 5); /* DIF_TX_CTL4 */
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
- /*lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0fff0800);*/
- } else {
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0);
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0);
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0);
- }
-}
-
-static void lcd_mlvds_phy_set(struct lcd_config_s *pconf, int status)
-{
- unsigned int vswing, preem;
- unsigned int data32;
-
- if (lcd_debug_print_flag)
- LCDPR("%s: %d\n", __func__, status);
-
- if (status) {
- vswing = pconf->lcd_control.mlvds_config->phy_vswing;
- preem = pconf->lcd_control.mlvds_config->phy_preem;
- if (vswing > 7) {
- LCDERR("%s: wrong vswing_level=%d, use default\n",
- __func__, vswing);
- vswing = LVDS_PHY_VSWING_DFT;
- }
- if (preem > 3) {
- LCDERR("%s: wrong preemphasis_level=%d, use default\n",
- __func__, preem);
- preem = LVDS_PHY_PREEM_DFT;
- }
-
- data32 = MLVDS_PHY_CNTL1_TXHD |
- (vswing << 3) | (vswing << 0) | (preem << 23);
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, data32);
- data32 = MLVDS_PHY_CNTL2_TXHD |
- (preem << 14) | (preem << 12) |
- (preem << 26) | (preem << 24);
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, data32);
- data32 = MLVDS_PHY_CNTL3_TXHD |
- (preem << 6) | (preem << 4) |
- (preem << 2) | (preem << 0) | (preem << 30);
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, data32);
- } else {
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL1, 0x0);
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL2, 0x0);
- lcd_hiu_write(HHI_DIF_CSI_PHY_CNTL3, 0x0);
- }
-}
-
-static void lcd_encl_tcon_set(struct lcd_config_s *pconf)
-{
- lcd_vcbus_write(L_RGB_BASE_ADDR, 0);
- lcd_vcbus_write(L_RGB_COEFF_ADDR, 0x400);
-
- switch (pconf->lcd_basic.lcd_bits) {
- case 6:
- lcd_vcbus_write(L_DITH_CNTL_ADDR, 0x600);
- break;
- case 8:
- lcd_vcbus_write(L_DITH_CNTL_ADDR, 0x400);
- break;
- case 10:
- default:
- lcd_vcbus_write(L_DITH_CNTL_ADDR, 0x0);
- break;
- }
-
- switch (pconf->lcd_basic.lcd_type) {
- case LCD_LVDS:
- lcd_vcbus_setb(L_POL_CNTL_ADDR, 1, 0, 1);
- if (pconf->lcd_timing.vsync_pol)
- lcd_vcbus_setb(L_POL_CNTL_ADDR, 1, 1, 1);
- break;
- case LCD_VBYONE:
- if (pconf->lcd_timing.hsync_pol)
- lcd_vcbus_setb(L_POL_CNTL_ADDR, 1, 0, 1);
- if (pconf->lcd_timing.vsync_pol)
- lcd_vcbus_setb(L_POL_CNTL_ADDR, 1, 1, 1);
- break;
- default:
- break;
- }
-
- lcd_vcbus_write(VPP_MISC, lcd_vcbus_read(VPP_MISC) & ~(VPP_OUT_SATURATE));
-}
-
-static void lcd_venc_set(struct lcd_config_s *pconf)
-{
- unsigned int h_active, v_active;
- unsigned int video_on_pixel, video_on_line;
-
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
-
- h_active = pconf->lcd_basic.h_active;
- v_active = pconf->lcd_basic.v_active;
- video_on_pixel = pconf->lcd_timing.video_on_pixel;
- video_on_line = pconf->lcd_timing.video_on_line;
-
- lcd_vcbus_write(ENCL_VIDEO_EN, 0);
-
- /* viu1 select encl | viu2 select encl */
- lcd_vcbus_write(VPU_VIU_VENC_MUX_CTRL, (0 << 0) | (0 << 2));
- lcd_vcbus_write(ENCL_VIDEO_MODE, 0x8000); /* bit[15] shadown en */
- lcd_vcbus_write(ENCL_VIDEO_MODE_ADV, 0x0418); /* Sampling rate: 1 */
-
- lcd_vcbus_write(ENCL_VIDEO_FILT_CTRL, 0x1000); /* bypass filter */
- lcd_vcbus_write(ENCL_VIDEO_MAX_PXCNT, pconf->lcd_basic.h_period - 1);
- lcd_vcbus_write(ENCL_VIDEO_MAX_LNCNT, pconf->lcd_basic.v_period - 1);
- lcd_vcbus_write(ENCL_VIDEO_HAVON_BEGIN, video_on_pixel);
- lcd_vcbus_write(ENCL_VIDEO_HAVON_END, h_active - 1 + video_on_pixel);
- lcd_vcbus_write(ENCL_VIDEO_VAVON_BLINE, video_on_line);
- lcd_vcbus_write(ENCL_VIDEO_VAVON_ELINE, v_active - 1 + video_on_line);
-
- lcd_vcbus_write(ENCL_VIDEO_HSO_BEGIN, pconf->lcd_timing.hs_hs_addr);
- lcd_vcbus_write(ENCL_VIDEO_HSO_END, pconf->lcd_timing.hs_he_addr);
- lcd_vcbus_write(ENCL_VIDEO_VSO_BEGIN, pconf->lcd_timing.vs_hs_addr);
- lcd_vcbus_write(ENCL_VIDEO_VSO_END, pconf->lcd_timing.vs_he_addr);
- lcd_vcbus_write(ENCL_VIDEO_VSO_BLINE, pconf->lcd_timing.vs_vs_addr);
- lcd_vcbus_write(ENCL_VIDEO_VSO_ELINE, pconf->lcd_timing.vs_ve_addr);
- lcd_vcbus_write(ENCL_VIDEO_RGBIN_CTRL, 3);
-
- /* default black pattern */
- lcd_vcbus_write(ENCL_TST_MDSEL, 0);
- lcd_vcbus_write(ENCL_TST_Y, 0);
- lcd_vcbus_write(ENCL_TST_CB, 0);
- lcd_vcbus_write(ENCL_TST_CR, 0);
- lcd_vcbus_write(ENCL_TST_EN, 1);
- lcd_vcbus_setb(ENCL_VIDEO_MODE_ADV, 0, 3, 1);
-
- lcd_vcbus_write(ENCL_VIDEO_EN, 1);
-}
-
-static void lcd_lvds_clk_util_set(struct lcd_config_s *pconf)
-{
- unsigned int phy_div;
-
- if (pconf->lcd_control.lvds_config->dual_port)
+ if (pdrv->config.control.lvds_cfg.dual_port)
phy_div = 2;
else
phy_div = 1;
- /* set fifo_clk_sel: div 7 */
- lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL0, (1 << 6));
- /* set cntl_ser_en: 8-channel to 1 */
- lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12);
+ if (pdrv->data->chip_type == LCD_CHIP_T7) {
+ switch (pdrv->index) {
+ case 0:
+ reg_phy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0;
+ reg_phy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1;
+ bit_data_in_lvds = 0;
+ bit_data_in_edp = 1;
+ bit_lane_sel = 0;
+ val_lane_sel = 0x155;
+ len_lane_sel = 10;
+ break;
+ case 1:
+ reg_phy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL0;
+ reg_phy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL1;
+ bit_data_in_lvds = 2;
+ bit_data_in_edp = 3;
+ bit_lane_sel = 10;
+ val_lane_sel = 0x155;
+ len_lane_sel = 10;
+ break;
+ case 2:
+ reg_phy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL0;
+ reg_phy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL1;
+ bit_data_in_lvds = 4;
+ bit_data_in_edp = 0xff;
+ if (pdrv->config.control.lvds_cfg.dual_port) {
+ bit_lane_sel = 10;
+ val_lane_sel = 0xaaaaa;
+ len_lane_sel = 20;
+ } else {
+ bit_lane_sel = 20;
+ val_lane_sel = 0x2aa;
+ len_lane_sel = 10;
+ }
+ break;
+ default:
+ LCDERR("[%d]: %s: invalid drv_index\n",
+ pdrv->index, __func__);
+ return;
+ }
- /* decoupling fifo enable, gated clock enable */
- lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL1,
- (1 << 30) | ((phy_div - 1) << 25) | (1 << 24));
- /* decoupling fifo write enable after fifo enable */
- lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL1, 1, 31, 1);
+ // sel dphy data_in
+ if (bit_data_in_edp < 0xff)
+ lcd_combo_dphy_setb(COMBO_DPHY_CNTL0, 0, bit_data_in_edp, 1);
+ lcd_combo_dphy_setb(COMBO_DPHY_CNTL0, 1, bit_data_in_lvds, 1);
+ // sel dphy lane
+ lcd_combo_dphy_setb(COMBO_DPHY_CNTL1, val_lane_sel,
+ bit_lane_sel, len_lane_sel);
+
+ /* set fifo_clk_sel: div 7 */
+ lcd_combo_dphy_write(reg_phy_tx_ctrl0, (1 << 5));
+ /* set cntl_ser_en: 8-channel */
+ lcd_combo_dphy_setb(reg_phy_tx_ctrl0, 0x3ff, 16, 10);
+
+ /* decoupling fifo enable, gated clock enable */
+ lcd_combo_dphy_write(reg_phy_tx_ctrl1, (1 << 6) | (1 << 0));
+ /* decoupling fifo write enable after fifo enable */
+ lcd_combo_dphy_setb(reg_phy_tx_ctrl1, 1, 7, 1);
+ } else {
+ /* set fifo_clk_sel: div 7 */
+ lcd_ana_write(HHI_LVDS_TX_PHY_CNTL0, (1 << 6));
+ /* set cntl_ser_en: 8-channel to 1 */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12);
+ /* pn swap */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL0, 1, 2, 1);
+
+ /* decoupling fifo enable, gated clock enable */
+ lcd_ana_write(HHI_LVDS_TX_PHY_CNTL1,
+ (1 << 30) | ((phy_div - 1) << 25) | (1 << 24));
+ /* decoupling fifo write enable after fifo enable */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL1, 1, 31, 1);
+ }
}
-static void lcd_lvds_control_set(struct lcd_config_s *pconf)
+static void lcd_lvds_control_set(struct aml_lcd_drv_s *pdrv)
{
- unsigned int bit_num = 1;
- unsigned int pn_swap, port_swap, lane_reverse;
- unsigned int dual_port, fifo_mode;
- unsigned int lvds_repack = 1;
+ unsigned int bit_num, pn_swap, port_swap, lane_reverse;
+ unsigned int dual_port, fifo_mode, lvds_repack;
+ unsigned int offset;
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
- lcd_lvds_clk_util_set(pconf);
+ lcd_lvds_clk_util_set(pdrv);
- lvds_repack = (pconf->lcd_control.lvds_config->lvds_repack) & 0x3;
- pn_swap = (pconf->lcd_control.lvds_config->pn_swap) & 0x1;
- dual_port = (pconf->lcd_control.lvds_config->dual_port) & 0x1;
- port_swap = (pconf->lcd_control.lvds_config->port_swap) & 0x1;
- lane_reverse = (pconf->lcd_control.lvds_config->lane_reverse) & 0x1;
+ offset = pdrv->data->offset_venc_if[pdrv->index];
+ lvds_repack = (pdrv->config.control.lvds_cfg.lvds_repack) & 0x3;
+ pn_swap = (pdrv->config.control.lvds_cfg.pn_swap) & 0x1;
+ dual_port = (pdrv->config.control.lvds_cfg.dual_port) & 0x1;
+ port_swap = (pdrv->config.control.lvds_cfg.port_swap) & 0x1;
+ lane_reverse = (pdrv->config.control.lvds_cfg.lane_reverse) & 0x1;
- switch (pconf->lcd_basic.lcd_bits) {
+ switch (pdrv->config.basic.lcd_bits) {
case 10:
- bit_num=0;
- break;
- case 8:
- bit_num=1;
+ bit_num = 0;
break;
case 6:
- bit_num=2;
+ bit_num = 2;
break;
- case 4:
- bit_num=3;
- break;
+ case 8:
default:
- bit_num=1;
+ bit_num = 1;
break;
}
if (dual_port)
@@ -325,7 +152,10 @@
else
fifo_mode = 0x1;
- lcd_vcbus_write(LVDS_PACK_CNTL_ADDR,
+ if (pdrv->data->chip_type == LCD_CHIP_T7)
+ lcd_vcbus_write(LVDS_SER_EN + offset, 0xfff);
+
+ lcd_vcbus_write(LVDS_PACK_CNTL_ADDR + offset,
(lvds_repack << 0) | // repack //[1:0]
(0 << 3) | // reserve
(0 << 4) | // lsb first
@@ -338,118 +168,178 @@
(2 << 14)); //b_select //0:R, 1:G, 2:B, 3:0;
/* lvsd swap */
- lcd_vcbus_setb(LCD_PORT_SWAP, port_swap, 12, 1);
- if (lane_reverse)
- lcd_vcbus_setb(LVDS_GEN_CNTL, 0x03, 13, 2);
-
- lcd_vcbus_write(LVDS_GEN_CNTL, (lcd_vcbus_read(LVDS_GEN_CNTL) | (1 << 4) | (fifo_mode << 0)));
- lcd_vcbus_setb(LVDS_GEN_CNTL, 1, 3, 1);
-}
-
-static void lcd_lvds_disable(void)
-{
- lcd_vcbus_setb(LVDS_GEN_CNTL, 0, 3, 1); /* disable lvds fifo */
-}
-
-static void lcd_mlvds_clk_util_set(struct lcd_config_s *pconf)
-{
- unsigned int lcd_bits, div_sel;
-
- lcd_bits = pconf->lcd_basic.lcd_bits;
-
- switch (lcd_bits) {
- case 6:
- div_sel = 0;
+ switch (pdrv->data->chip_type) {
+ case LCD_CHIP_TL1:
+ case LCD_CHIP_TM2:
+ /* lvds channel: //tx 12 channels
+ * 0: d0_a
+ * 1: d1_a
+ * 2: d2_a
+ * 3: clk_a
+ * 4: d3_a
+ * 5: d4_a
+ * 6: d0_b
+ * 7: d1_b
+ * 8: d2_b
+ * 9: clk_b
+ * a: d3_b
+ * b: d4_b
+ */
+ if (port_swap) {
+ if (lane_reverse) {
+ lcd_vcbus_write(P2P_CH_SWAP0, 0x456789ab);
+ lcd_vcbus_write(P2P_CH_SWAP1, 0x0123);
+ } else {
+ lcd_vcbus_write(P2P_CH_SWAP0, 0x10ba9876);
+ lcd_vcbus_write(P2P_CH_SWAP1, 0x5432);
+ }
+ } else {
+ if (lane_reverse) {
+ lcd_vcbus_write(P2P_CH_SWAP0, 0xab012345);
+ lcd_vcbus_write(P2P_CH_SWAP1, 0x6789);
+ } else {
+ lcd_vcbus_write(P2P_CH_SWAP0, 0x76543210);
+ lcd_vcbus_write(P2P_CH_SWAP1, 0xba98);
+ }
+ }
break;
- case 8:
- div_sel = 2;
+ case LCD_CHIP_T5:
+ case LCD_CHIP_T5D:
+ /* lvds channel: //tx 12 channels
+ * 0: d0_a
+ * 1: d1_a
+ * 2: d2_a
+ * 3: clk_a
+ * 4: d3_a
+ * 5: d4_a
+ * 6: d0_b
+ * 7: d1_b
+ * 8: d2_b
+ * 9: clk_b
+ * a: d3_b
+ * b: d4_b
+ */
+ if (port_swap) {
+ if (lane_reverse) {
+ lcd_vcbus_write(P2P_CH_SWAP0, 0x345789ab);
+ lcd_vcbus_write(P2P_CH_SWAP1, 0x0612);
+ } else {
+ lcd_vcbus_write(P2P_CH_SWAP0, 0x210a9876);
+ lcd_vcbus_write(P2P_CH_SWAP1, 0x5b43);
+ }
+ } else {
+ if (lane_reverse) {
+ lcd_vcbus_write(P2P_CH_SWAP0, 0xab12345);
+ lcd_vcbus_write(P2P_CH_SWAP1, 0x60789);
+ } else {
+ lcd_vcbus_write(P2P_CH_SWAP0, 0x87643210);
+ lcd_vcbus_write(P2P_CH_SWAP1, 0xb5a9);
+ }
+ }
+ break;
+ case LCD_CHIP_T7:
+ /* lvds channel: //tx 12 channels
+ * 0: d0_a
+ * 1: d1_a
+ * 2: d2_a
+ * 3: clk_a
+ * 4: d3_a
+ * 5: d4_a
+ * 6: d0_b
+ * 7: d1_b
+ * 8: d2_b
+ * 9: clk_b
+ * a: d3_b
+ * b: d4_b
+ */
+ if (port_swap) {
+ if (lane_reverse) {
+ lcd_vcbus_write(P2P_CH_SWAP0 + offset, 0x345789ab);
+ lcd_vcbus_write(P2P_CH_SWAP1 + offset, 0x0612);
+ } else {
+ lcd_vcbus_write(P2P_CH_SWAP0 + offset, 0x210a9876);
+ lcd_vcbus_write(P2P_CH_SWAP1 + offset, 0x5b43);
+ }
+ } else {
+ if (lane_reverse) {
+ lcd_vcbus_write(P2P_CH_SWAP0 + offset, 0xab12345);
+ lcd_vcbus_write(P2P_CH_SWAP1 + offset, 0x60789);
+ } else {
+ lcd_vcbus_write(P2P_CH_SWAP0 + offset, 0x87643210);
+ lcd_vcbus_write(P2P_CH_SWAP1 + offset, 0xb5a9);
+ }
+ }
+ lcd_vcbus_write(P2P_BIT_REV + offset, 2);
break;
default:
- div_sel = 2;
break;
}
- /* set fifo_clk_sel */
- lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL0, (div_sel << 6));
- /* set cntl_ser_en: 8-channel to 1 */
- lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12);
-
- /* decoupling fifo enable, gated clock enable */
- lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL1,
- (1 << 30) | (0 << 25) | (1 << 24));
- /* decoupling fifo write enable after fifo enable */
- lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL1, 1, 31, 1);
+ lcd_vcbus_write(LVDS_GEN_CNTL + offset,
+ (lcd_vcbus_read(LVDS_GEN_CNTL + offset) | (1 << 4) | (fifo_mode << 0)));
+ lcd_vcbus_setb(LVDS_GEN_CNTL + offset, 1, 3, 1);
}
-static void lcd_mlvds_control_set(struct lcd_config_s *pconf)
+static void lcd_lvds_disable(struct aml_lcd_drv_s *pdrv)
{
- unsigned int bit_num = 1;
+ unsigned int reg_dphy_tx_ctrl0, reg_dphy_tx_ctrl1, offset = 0;
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
+ if (pdrv->data->chip_type == LCD_CHIP_T7) {
+ switch (pdrv->index) {
+ case 0:
+ reg_dphy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0;
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1;
+ break;
+ case 1:
+ reg_dphy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL0;
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL1;
+ break;
+ case 2:
+ reg_dphy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL0;
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY2_CNTL1;
+ break;
+ default:
+ LCDERR("[%d]: %s: invalid drv_index\n", pdrv->index, __func__);
+ return;
+ }
+ offset = pdrv->data->offset_venc_if[pdrv->index];
- lcd_mlvds_clk_util_set(pconf);
-
- switch (pconf->lcd_basic.lcd_bits) {
- case 10:
- bit_num=0;
- break;
- case 8:
- bit_num=1;
- break;
- case 6:
- bit_num=2;
- break;
- case 4:
- bit_num=3;
- break;
- default:
- bit_num=1;
- break;
+ /* disable lvds fifo */
+ lcd_vcbus_setb(LVDS_GEN_CNTL + offset, 0, 3, 1);
+ /* disable fifo */
+ lcd_combo_dphy_setb(reg_dphy_tx_ctrl1, 0, 6, 2);
+ /* disable lane */
+ lcd_combo_dphy_setb(reg_dphy_tx_ctrl0, 0, 16, 10);
+ } else {
+ /* disable lvds fifo */
+ lcd_vcbus_setb(LVDS_GEN_CNTL, 0, 3, 1);
+ /* disable fifo */
+ lcd_clk_setb(HHI_LVDS_TX_PHY_CNTL1, 0, 30, 2);
+ /* disable lane */
+ lcd_clk_setb(HHI_LVDS_TX_PHY_CNTL0, 0, 16, 12);
}
-
- lcd_vcbus_write(LVDS_PACK_CNTL_ADDR,
- (1 << 0) | // repack //[1:0]
- (0 << 3) | // reserve
- (0 << 4) | // lsb first
- (0 << 5) | // pn swap
- (1 << 6) | // dual port
- (0 << 7) | // use tcon control
- (bit_num << 8) | // 0:10bits, 1:8bits, 2:6bits, 3:4bits.
- (0 << 10) | //r_select //0:R, 1:G, 2:B, 3:0
- (1 << 12) | //g_select //0:R, 1:G, 2:B, 3:0
- (2 << 14)); //b_select //0:R, 1:G, 2:B, 3:0;
-
- lcd_vcbus_write(LVDS_GEN_CNTL, (lcd_vcbus_read(LVDS_GEN_CNTL) | (1 << 4) | (0x3 << 0)));
- lcd_vcbus_setb(LVDS_GEN_CNTL, 1, 3, 1);
-
- lcd_tcon_enable(pconf);
}
-static void lcd_mlvds_disable(void)
+static void lcd_vbyone_sync_pol(unsigned int offset, int hsync_pol, int vsync_pol)
{
- lcd_tcon_disable();
+ lcd_vcbus_setb(VBO_VIN_CTRL + offset, hsync_pol, 4, 1);
+ lcd_vcbus_setb(VBO_VIN_CTRL + offset, vsync_pol, 5, 1);
- lcd_vcbus_setb(LVDS_GEN_CNTL, 0, 3, 1); /* disable lvds fifo */
+ lcd_vcbus_setb(VBO_VIN_CTRL + offset, hsync_pol, 6, 1);
+ lcd_vcbus_setb(VBO_VIN_CTRL + offset, vsync_pol, 7, 1);
}
-static void lcd_vbyone_sync_pol(int hsync_pol, int vsync_pol)
+static void lcd_vbyone_clk_util_set(struct aml_lcd_drv_s *pdrv)
{
- lcd_vcbus_setb(VBO_VIN_CTRL, hsync_pol, 4, 1);
- lcd_vcbus_setb(VBO_VIN_CTRL, vsync_pol, 5, 1);
+ unsigned int lcd_bits, div_sel, phy_div;
+ unsigned int reg_phy_tx_ctrl0, reg_phy_tx_ctrl1;
+ unsigned int bit_data_in_lvds, bit_data_in_edp, bit_lane_sel;
- lcd_vcbus_setb(VBO_VIN_CTRL, hsync_pol, 6, 1);
- lcd_vcbus_setb(VBO_VIN_CTRL, vsync_pol, 7, 1);
-}
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
-static void lcd_vbyone_clk_util_set(struct lcd_config_s *pconf)
-{
- unsigned int lcd_bits;
- unsigned int div_sel, phy_div;
-
- phy_div = pconf->lcd_control.vbyone_config->phy_div;
- lcd_bits = pconf->lcd_basic.lcd_bits;
-
+ phy_div = pdrv->config.control.vbyone_cfg.phy_div;
+ lcd_bits = pdrv->config.basic.lcd_bits;
switch (lcd_bits) {
case 6:
div_sel = 0;
@@ -458,26 +348,66 @@
div_sel = 2;
break;
case 10:
- div_sel = 3;
- break;
default:
div_sel = 3;
break;
}
- /* set fifo_clk_sel */
- lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL0, (div_sel << 6));
- /* set cntl_ser_en: 8-channel to 1 */
- lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12);
- /* decoupling fifo enable, gated clock enable */
- lcd_hiu_write(HHI_LVDS_TX_PHY_CNTL1,
- (1 << 30) | ((phy_div - 1) << 25) | (1 << 24));
- /* decoupling fifo write enable after fifo enable */
- lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL1, 1, 31, 1);
+ if (pdrv->data->chip_type == LCD_CHIP_T7) {
+ switch (pdrv->index) {
+ case 0:
+ reg_phy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0;
+ reg_phy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1;
+ bit_data_in_lvds = 0;
+ bit_data_in_edp = 1;
+ bit_lane_sel = 0;
+ break;
+ case 1:
+ reg_phy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL0;
+ reg_phy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL1;
+ bit_data_in_lvds = 2;
+ bit_data_in_edp = 3;
+ bit_lane_sel = 16;
+ break;
+ default:
+ LCDERR("[%d]: %s: invalid drv_index\n",
+ pdrv->index, __func__);
+ return;
+ }
+
+ // sel dphy data_in
+ lcd_combo_dphy_setb(COMBO_DPHY_CNTL0, 0, bit_data_in_edp, 1);
+ lcd_combo_dphy_setb(COMBO_DPHY_CNTL0, 1, bit_data_in_lvds, 1);
+ // sel dphy lane
+ lcd_combo_dphy_setb(COMBO_DPHY_CNTL1, 0x5555, bit_lane_sel, 16);
+
+ /* set fifo_clk_sel: div 7 */
+ lcd_combo_dphy_write(reg_phy_tx_ctrl0, (div_sel << 5));
+ /* set cntl_ser_en: 8-channel to 1 */
+ lcd_combo_dphy_setb(reg_phy_tx_ctrl0, 0xff, 16, 8);
+
+ /* decoupling fifo enable, gated clock enable */
+ lcd_combo_dphy_write(reg_phy_tx_ctrl1, (1 << 6) | (1 << 0));
+ /* decoupling fifo write enable after fifo enable */
+ lcd_combo_dphy_setb(reg_phy_tx_ctrl1, 1, 7, 1);
+ } else {
+ /* set fifo_clk_sel: div 10 */
+ lcd_ana_write(HHI_LVDS_TX_PHY_CNTL0, (div_sel << 6));
+ /* set cntl_ser_en: 8-channel to 1 */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12);
+ /* pn swap */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL0, 1, 2, 1);
+
+ /* decoupling fifo enable, gated clock enable */
+ lcd_ana_write(HHI_LVDS_TX_PHY_CNTL1,
+ (1 << 30) | ((phy_div - 1) << 25) | (1 << 24));
+ /* decoupling fifo write enable after fifo enable */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL1, 1, 31, 1);
+ }
}
-static int lcd_vbyone_lanes_set(int lane_num, int byte_mode, int region_num,
- int hsize, int vsize)
+static int lcd_vbyone_lanes_set(unsigned int offset, int lane_num, int byte_mode,
+ int region_num, int hsize, int vsize)
{
int sublane_num;
int region_size[4];
@@ -509,16 +439,16 @@
default:
return -1;
}
- if (lcd_debug_print_flag) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
LCDPR("byte_mode=%d, lane_num=%d, region_num=%d\n",
byte_mode, lane_num, region_num);
}
sublane_num = lane_num / region_num; /* lane num in each region */
- lcd_vcbus_setb(VBO_LANES, (lane_num - 1), 0, 3);
- lcd_vcbus_setb(VBO_LANES, (region_num - 1), 4, 2);
- lcd_vcbus_setb(VBO_LANES, (sublane_num - 1), 8, 3);
- lcd_vcbus_setb(VBO_LANES, (byte_mode - 1), 11, 2);
+ lcd_vcbus_setb(VBO_LANES + offset, (lane_num - 1), 0, 3);
+ lcd_vcbus_setb(VBO_LANES + offset, (region_num - 1), 4, 2);
+ lcd_vcbus_setb(VBO_LANES + offset, (sublane_num - 1), 8, 3);
+ lcd_vcbus_setb(VBO_LANES + offset, (byte_mode - 1), 11, 2);
if (region_num > 1) {
region_size[3] = (hsize / lane_num) * sublane_num;
@@ -529,602 +459,354 @@
sublane_num : (tmp % sublane_num));
region_size[2] = region_size[3] + (((tmp / sublane_num) > 2) ?
sublane_num : (tmp % sublane_num));
- lcd_vcbus_write(VBO_REGION_00, region_size[0]);
- lcd_vcbus_write(VBO_REGION_01, region_size[1]);
- lcd_vcbus_write(VBO_REGION_02, region_size[2]);
- lcd_vcbus_write(VBO_REGION_03, region_size[3]);
+ lcd_vcbus_write(VBO_REGION_00 + offset, region_size[0]);
+ lcd_vcbus_write(VBO_REGION_01 + offset, region_size[1]);
+ lcd_vcbus_write(VBO_REGION_02 + offset, region_size[2]);
+ lcd_vcbus_write(VBO_REGION_03 + offset, region_size[3]);
}
- lcd_vcbus_write(VBO_ACT_VSIZE, vsize);
+ lcd_vcbus_write(VBO_ACT_VSIZE + offset, vsize);
/* different from FBC code!!! */
- /* lcd_vcbus_setb(VBO_CTRL_H,0x80,11,5); */
+ /* lcd_vcbus_setb(VBO_CTRL_H + offset,0x80,11,5); */
/* different from simulation code!!! */
- lcd_vcbus_setb(VBO_CTRL_H, 0x0, 0, 4);
- lcd_vcbus_setb(VBO_CTRL_H, 0x1, 9, 1);
- /* lcd_vcbus_setb(VBO_CTRL_L,enable,0,1); */
+ lcd_vcbus_setb(VBO_CTRL_H + offset, 0x0, 0, 4);
+ lcd_vcbus_setb(VBO_CTRL_H + offset, 0x1, 9, 1);
+ /* lcd_vcbus_setb(VBO_CTRL_L + offset,enable,0,1); */
return 0;
}
-static void lcd_vbyone_sw_reset(void)
-{
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
-
- /* force PHY to 0 */
- lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0, 3, 8, 2);
- lcd_vcbus_write(VBO_SOFT_RST, 0x1ff);
- udelay(5);
- /* realease PHY */
- lcd_hiu_setb(HHI_LVDS_TX_PHY_CNTL0, 0, 8, 2);
- lcd_vcbus_write(VBO_SOFT_RST, 0);
-}
-
-static void lcd_vbyone_wait_timing_stable(void)
-{
- unsigned int timing_state;
- int i = 200;
-
- timing_state = lcd_vcbus_read(VBO_INTR_STATE) & 0x1ff;
- while ((timing_state) && (i > 0)) {
- /* clear video timing error intr */
- lcd_vcbus_setb(VBO_INTR_STATE_CTRL, 0x7, 0, 3);
- lcd_vcbus_setb(VBO_INTR_STATE_CTRL, 0, 0, 3);
- mdelay(2);
- timing_state = lcd_vcbus_read(VBO_INTR_STATE) & 0x1ff;
- i--;
- };
- if (lcd_debug_print_flag) {
- LCDPR("vbyone timing state: 0x%03x, i=%d\n",
- timing_state, (200 - i));
- }
- mdelay(2);
-}
-
-#define VX1_LOCKN_GPIO "GPIOH_0"
-static int lcd_vbyone_get_lockn_gpio(void)
-{
- int ret;
-
- lcd_periphs_setb(PREG_PAD_GPIO1_EN_N, 1, 20, 1);
- ret =lcd_periphs_getb(PREG_PAD_GPIO1_I, 20, 1);
- if (lcd_debug_print_flag)
- LCDPR("gpio %s = %d\n", VX1_LOCKN_GPIO, ret);
-
- return ret;
-}
-
-static int lcd_vbyone_sw_fliter(struct vbyone_config_s *vx1_conf)
-{
- int i,t;
- int lock_temp, lock_state = 1;
-
- for (i = 0; i < vx1_conf->vx1_sw_filter_cnt; i++) {
- for (t = 0; t < vx1_conf->vx1_sw_filter_time; t++)
- udelay(100);
- lock_temp = lcd_vbyone_get_lockn_gpio();
- if (lock_temp == 0)
- lock_state = 0;
- }
-
- return lock_state;
-}
-
-static void lcd_vbyone_cdr_training_hold(struct vbyone_config_s *vx1_conf, int flag)
-{
- if (flag) {
- LCDPR("ctrl_flag for cdr_training_hold\n");
- lcd_vcbus_setb(VBO_FSM_HOLDER_H, 0xffff, 0, 16);
- } else {
- mdelay(vx1_conf->cdr_training_hold);
- lcd_vcbus_setb(VBO_FSM_HOLDER_H, 0, 0, 16);
- }
-}
-
-static void lcd_vbyone_control_set(struct lcd_config_s *pconf)
+static void lcd_vbyone_control_set(struct aml_lcd_drv_s *pdrv)
{
int lane_count, byte_mode, region_num, hsize, vsize;
/* int color_fmt; */
int vin_color, vin_bpp;
+ unsigned int offset;
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
- hsize = pconf->lcd_basic.h_active;
- vsize = pconf->lcd_basic.v_active;
- lane_count = pconf->lcd_control.vbyone_config->lane_count; /* 8 */
- region_num = pconf->lcd_control.vbyone_config->region_num; /* 2 */
- byte_mode = pconf->lcd_control.vbyone_config->byte_mode; /* 4 */
- /* color_fmt = pconf->lcd_control.vbyone_config->color_fmt; // 4 */
+ offset = pdrv->data->offset_venc_if[pdrv->index];
- lcd_vbyone_clk_util_set(pconf);
-#if 0
- switch (color_fmt) {
- case 0:/* SDVT_VBYONE_18BPP_RGB */
- vin_color = 4;
- vin_bpp = 2;
- break;
- case 1:/* SDVT_VBYONE_18BPP_YCBCR444 */
- vin_color = 0;
- vin_bpp = 2;
- break;
- case 2:/* SDVT_VBYONE_24BPP_RGB */
- vin_color = 4;
- vin_bpp = 1;
- break;
- case 3:/* SDVT_VBYONE_24BPP_YCBCR444 */
- vin_color = 0;
- vin_bpp = 1;
- break;
- case 4:/* SDVT_VBYONE_30BPP_RGB */
- vin_color = 4;
- vin_bpp = 0;
- break;
- case 5:/* SDVT_VBYONE_30BPP_YCBCR444 */
- vin_color = 0;
- vin_bpp = 0;
- break;
- default:
- LCDERR("vbyone COLOR_FORMAT unsupport\n");
- return;
- }
-#else
+ hsize = pdrv->config.basic.h_active;
+ vsize = pdrv->config.basic.v_active;
+ lane_count = pdrv->config.control.vbyone_cfg.lane_count; /* 8 */
+ region_num = pdrv->config.control.vbyone_cfg.region_num; /* 2 */
+ byte_mode = pdrv->config.control.vbyone_cfg.byte_mode; /* 4 */
+ /* color_fmt = pdrv->config.control.vbyone_cfg.color_fmt; // 4 */
+
vin_color = 4; /* fixed RGB */
- vin_bpp = 0; /* fixed 30bbp 4:4:4 */
-#endif
+ switch (pdrv->config.basic.lcd_bits) {
+ case 6:
+ vin_bpp = 2; /* 18bbp 4:4:4 */
+ break;
+ case 8:
+ vin_bpp = 1; /* 24bbp 4:4:4 */
+ break;
+ case 10:
+ default:
+ vin_bpp = 0; /* 30bbp 4:4:4 */
+ break;
+ }
+
+ lcd_vbyone_clk_util_set(pdrv);
/* set Vbyone vin color format */
- lcd_vcbus_setb(VBO_VIN_CTRL, vin_color, 8, 3);
- lcd_vcbus_setb(VBO_VIN_CTRL, vin_bpp, 11, 2);
+ lcd_vcbus_setb(VBO_VIN_CTRL + offset, vin_color, 8, 3);
+ lcd_vcbus_setb(VBO_VIN_CTRL + offset, vin_bpp, 11, 2);
- lcd_vbyone_lanes_set(lane_count, byte_mode, region_num, hsize, vsize);
+ lcd_vbyone_lanes_set(offset, lane_count, byte_mode, region_num, hsize, vsize);
/*set hsync/vsync polarity to let the polarity is low active
inside the VbyOne */
- lcd_vbyone_sync_pol(0, 0);
+ lcd_vbyone_sync_pol(offset, 0, 0);
/* below line copy from simulation */
/* gate the input when vsync asserted */
- lcd_vcbus_setb(VBO_VIN_CTRL, 1, 0, 2);
- /* lcd_vcbus_write(VBO_VBK_CTRL_0,0x13);
- //lcd_vcbus_write(VBO_VBK_CTRL_1,0x56);
- //lcd_vcbus_write(VBO_HBK_CTRL,0x3478);
- //lcd_vcbus_setb(VBO_PXL_CTRL,0x2,0,4);
- //lcd_vcbus_setb(VBO_PXL_CTRL,0x3,VBO_PXL_CTR1_BIT,VBO_PXL_CTR1_WID);
+ lcd_vcbus_setb(VBO_VIN_CTRL + offset, 1, 0, 2);
+ /* lcd_vcbus_write(VBO_VBK_CTRL_0 + offset,0x13);
+ //lcd_vcbus_write(VBO_VBK_CTRL_1 + offset,0x56);
+ //lcd_vcbus_write(VBO_HBK_CTRL + offset,0x3478);
+ //lcd_vcbus_setb(VBO_PXL_CTRL + offset,0x2,0,4);
+ //lcd_vcbus_setb(VBO_PXL_CTRL + offset,0x3,VBO_PXL_CTR1_BIT,VBO_PXL_CTR1_WID);
//set_vbyone_ctlbits(1,0,0); */
+ /* VBO_RGN_GEN clk always on */
+ lcd_vcbus_setb(VBO_GCLK_MAIN + offset, 2, 2, 2);
/* PAD select: */
if ((lane_count == 1) || (lane_count == 2))
- lcd_vcbus_setb(LCD_PORT_SWAP, 1, 9, 2);
+ lcd_vcbus_setb(LCD_PORT_SWAP + offset, 1, 9, 2);
else if (lane_count == 4)
- lcd_vcbus_setb(LCD_PORT_SWAP, 2, 9, 2);
+ lcd_vcbus_setb(LCD_PORT_SWAP + offset, 2, 9, 2);
else
- lcd_vcbus_setb(LCD_PORT_SWAP, 0, 9, 2);
- /* lcd_vcbus_setb(LCD_PORT_SWAP, 1, 8, 1);//reverse lane output order */
+ lcd_vcbus_setb(LCD_PORT_SWAP + offset, 0, 9, 2);
+ /* lcd_vcbus_setb(LCD_PORT_SWAP + offset, 1, 8, 1);//reverse lane output order */
- if (pconf->lcd_control.vbyone_config->vx1_sw_filter_en) {
- /* hpd */
- /*lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 3, 1);
- lcd_vcbus_setb(VBO_INSGN_CTRL, 1, 2, 1);*/
- /* lockn */
- /*lcd_vcbus_setb(VBO_INSGN_CTRL, 1, 1, 1);
- lcd_vcbus_setb(VBO_INSGN_CTRL, 1, 0, 1);*/
- }
+ lcd_vbyone_hw_filter(pdrv, 1);
+ lcd_vcbus_setb(VBO_INSGN_CTRL + offset, 0, 2, 2);
- /* Mux pads in combo-phy: 0 for dsi; 1 for lvds or vbyone; 2 for edp */
- lcd_hiu_write(HHI_DSI_LVDS_EDP_CNTL0, 0x1);
+ lcd_vcbus_setb(VBO_CTRL_L + offset, 1, 0, 1);
- /* set hpd & lockn hw filter */
- lcd_vcbus_write(VBO_INFILTER_CTRL, 0xff77);
- lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 2, 2);
+ lcd_vbyone_wait_timing_stable(pdrv);
+ lcd_vbyone_sw_reset(pdrv);
- lcd_vcbus_setb(VBO_CTRL_L, 1, 0, 1);
-
- /*force vencl clk enable, otherwise, it might auto turn off by mipi DSI
- //lcd_vcbus_setb(VPU_MISC_CTRL, 1, 0, 1); */
-
- lcd_vbyone_wait_timing_stable();
- lcd_vbyone_sw_reset();
-
- if ((pconf->lcd_control.vbyone_config->ctrl_flag) & 0x4) /* training hold */
- lcd_vbyone_cdr_training_hold(pconf->lcd_control.vbyone_config, 1);
+ /* training hold */
+ if ((pdrv->config.control.vbyone_cfg.ctrl_flag) & 0x4)
+ lcd_vbyone_cdr_training_hold(pdrv, 1);
}
-static void lcd_vbyone_disable(void)
+static void lcd_vbyone_disable(struct aml_lcd_drv_s *pdrv)
{
- lcd_vcbus_setb(VBO_CTRL_L, 0, 0, 1);
- lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 2, 1);
- lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 0, 1);
-}
+ unsigned int reg_dphy_tx_ctrl0, reg_dphy_tx_ctrl1, offset;
-#define VX1_LOCKN_DETECT_FSM 0
-#define VX1_LOCKN_DETECT_GPIO 1
-#define VX1_LOCKN_DETECT_METHOD VX1_LOCKN_DETECT_FSM
-static void lcd_vbyone_wait_sw_lockn(struct vbyone_config_s *vx1_conf)
-{
- int i = 0, j = 0;
- int ret = 1, lockn = 0;
-
-#if (VX1_LOCKN_DETECT_METHOD == VX1_LOCKN_DETECT_FSM)
- lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 0, 1);
-#endif
- while (i++ < vx1_conf->vx1_sw_cdr_timeout_cnt) {
- j = 0;
- lockn = 0;
- while (j++ < vx1_conf->vx1_sw_cdr_detect_cnt) {
-#if (VX1_LOCKN_DETECT_METHOD == VX1_LOCKN_DETECT_FSM)
- //ret = (lcd_vcbus_read(VBO_STATUS_L) >> 7) & 1;
- ret = lcd_vcbus_read(VBO_STATUS_L) & 0x3f;
- if (ret == 0x20)
- ret = 0;
- else
- ret = 1;
-#else
- ret = lcd_vbyone_get_lockn_gpio();
-#endif
- lockn += ret;
- udelay(vx1_conf->vx1_sw_cdr_detect_time);
- }
- if (lockn == 0)
+ if (pdrv->data->chip_type == LCD_CHIP_T7) {
+ switch (pdrv->index) {
+ case 0:
+ reg_dphy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0;
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL1;
break;
- }
- /* lockn */
- lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 1, 1);
-#if (VX1_LOCKN_DETECT_METHOD == VX1_LOCKN_DETECT_FSM)
- lcd_vcbus_setb(VBO_INSGN_CTRL, 1, 0, 1);
-#endif
- mdelay(5);
- LCDPR("%s: %d, i=%d\n", __func__, lockn, i);
-}
-
-static void lcd_vbyone_sw_lockn(struct lcd_config_s *pconf)
-{
- struct vbyone_config_s *vx1_conf = pconf->lcd_control.vbyone_config;
- int i, ret;
-
- /* step 1: detect training lock */
- lcd_vbyone_wait_sw_lockn(vx1_conf);
- mdelay(vx1_conf->vx1_sw_filter_retry_delay);
- /* step 2: detect lockn noise */
- for (i = 0; i < vx1_conf->vx1_sw_filter_retry_cnt; i++) {
- ret = lcd_vbyone_sw_fliter(vx1_conf);
- if (ret) {
- lcd_vcbus_setb(VBO_INSGN_CTRL, ret, 1, 1);
- if (vx1_conf->vx1_sw_filter_en == 2)
- lcd_vbyone_sw_reset();
- lcd_vbyone_wait_sw_lockn(vx1_conf);
- }
- mdelay(vx1_conf->vx1_sw_filter_retry_delay);
- }
-}
-
-#define VX1_LOCKN_WAIT_TIMEOUT 500 /* 500ms */
-static void lcd_vbyone_wait_stable(struct lcd_config_s *pconf)
-{
- int i = 0;
- int ret = 1;
-
- if (pconf->lcd_control.vbyone_config->vx1_sw_filter_en) {
- lcd_vbyone_sw_lockn(pconf);
- LCDPR("%s status: 0x%x, i=%d\n", __func__, lcd_vcbus_read(VBO_STATUS_L), i);
- } else {
- if ((pconf->lcd_control.vbyone_config->ctrl_flag) & 0x4) /* training hold */
- lcd_vbyone_cdr_training_hold(pconf->lcd_control.vbyone_config, 0);
- while (i++ < VX1_LOCKN_WAIT_TIMEOUT) {
- ret = lcd_vcbus_read(VBO_STATUS_L) & 0x3f;
- if (ret == 0x20)
- break;
- mdelay(1);
- }
- LCDPR("%s status: 0x%x, i=%d\n", __func__, lcd_vcbus_read(VBO_STATUS_L), i);
- if ((pconf->lcd_control.vbyone_config->ctrl_flag) & 0x1) { /* power on reset */
- LCDPR("ctrl_flag for power on reset\n");
- mdelay(pconf->lcd_control.vbyone_config->power_on_reset_delay);
- lcd_vbyone_sw_reset();
- }
- }
-}
-
-static void lcd_vbyone_sw_hpd(void)
-{
- /* hpd */
- lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 3, 1);
- lcd_vcbus_setb(VBO_INSGN_CTRL, 1, 2, 1);
- /* lockn */
-#if (VX1_LOCKN_DETECT_METHOD == VX1_LOCKN_DETECT_GPIO)
- lcd_vcbus_setb(VBO_INSGN_CTRL, 1, 1, 1);
- lcd_vcbus_setb(VBO_INSGN_CTRL, 1, 0, 1);
-#endif
-}
-
-#define VX1_HPD_WAIT_TIMEOUT 5000 /* 500ms */
-static void lcd_vbyone_wait_hpd(struct lcd_config_s *pconf)
-{
- int i = 0;
- int ret = 1;
-
- LCDPR("%s:", __func__);
-#if 0
- if (vx1_sw_filter_en > 0) {
- while (i++ < VX1_HPD_WAIT_TIMEOUT) {
- ret = lcd_vbyone_get_hpd_gpio();
- if (ret == 0)
- break;
- mdelay(1);
- }
- if (ret)
- LCDPR("%s: hpd=%d\n", __func__, ret);
- else
- LCDPR("%s: hpd=%d, i=%d\n", __func__, ret, i);
- } else {
- while (i++ < VX1_HPD_WAIT_TIMEOUT) {
- ret = (lcd_vcbus_read(VBO_STATUS_L) >> 6) & 1;
- if (ret == 0)
- break;
- mdelay(1);
- }
- if (ret)
- LCDPR("%s: hpd=%d\n", __func__,
- ((lcd_vcbus_read(VBO_STATUS_L) >> 6) & 0x1));
- else
- LCDPR("%s: hpd=%d, i=%d\n", __func__,
- ((lcd_vcbus_read(VBO_STATUS_L) >> 6) & 0x1), i);
- }
-#else
- while (i++ < VX1_HPD_WAIT_TIMEOUT) {
- ret = (lcd_vcbus_read(VBO_STATUS_L) >> 6) & 1;
- if (ret == 0)
+ case 1:
+ reg_dphy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL0;
+ reg_dphy_tx_ctrl1 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL1;
break;
- udelay(100);
- }
- if (ret)
- printf("hpd=%d\n", ((lcd_vcbus_read(VBO_STATUS_L) >> 6) & 1));
- else {
- printf("hpd=%d, i=%d\n", ((lcd_vcbus_read(VBO_STATUS_L) >> 6) & 1), i);
- if (pconf->lcd_control.vbyone_config->vx1_sw_filter_en)
- lcd_vbyone_sw_hpd();
- }
-#endif
- /* musk htpd */
- lcd_vcbus_setb(VBO_INSGN_CTRL, 1, 2, 2);
+ default:
+ LCDERR("[%d]: %s: invalid drv_index\n", pdrv->index, __func__);
+ return;
+ }
+ offset = pdrv->data->offset_venc_if[pdrv->index];
- if ((pconf->lcd_control.vbyone_config->ctrl_flag) & 0x2) {
- LCDPR("ctrl_flag for hpd_data delay\n");
- mdelay(pconf->lcd_control.vbyone_config->hpd_data_delay);
+ lcd_vcbus_setb(VBO_CTRL_L + offset, 0, 0, 1);
+ /* clear insig setting */
+ lcd_vcbus_setb(VBO_INSGN_CTRL + offset, 0, 2, 1);
+ lcd_vcbus_setb(VBO_INSGN_CTRL + offset, 0, 0, 1);
+
+ /* disable fifo */
+ lcd_combo_dphy_setb(reg_dphy_tx_ctrl1, 0, 6, 2);
+ /* disable lane */
+ lcd_combo_dphy_setb(reg_dphy_tx_ctrl0, 0, 16, 8);
} else {
- mdelay(10); /* add 10ms delay for compatibility */
+ lcd_vcbus_setb(VBO_CTRL_L, 0, 0, 1);
+ /* clear insig setting */
+ lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 2, 1);
+ lcd_vcbus_setb(VBO_INSGN_CTRL, 0, 0, 1);
+
+ /* disable fifo */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL1, 0, 30, 2);
+ /* disable lane */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL0, 0, 16, 12);
}
}
-static unsigned int vbyone_lane_num[] = {
- 1,
- 2,
- 4,
- 8,
- 8,
-};
-
-#define VBYONE_BIT_RATE_MAX 3100 //MHz
-#define VBYONE_BIT_RATE_MIN 600
-static void lcd_vbyone_config_set(struct lcd_config_s *pconf)
+#ifdef CONFIG_AML_LCD_TCON
+static void lcd_mlvds_control_set(struct aml_lcd_drv_s *pdrv)
{
- unsigned int band_width, bit_rate, pclk, phy_div;
- unsigned int byte_mode, lane_count, minlane;
- unsigned int temp, i;
+ unsigned int div_sel, channel_sel0, channel_sel1;
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
- //auto calculate bandwidth, clock
- lane_count = pconf->lcd_control.vbyone_config->lane_count;
- byte_mode = pconf->lcd_control.vbyone_config->byte_mode;
- /* byte_mode * byte2bit * 8/10_encoding * pclk =
- byte_mode * 8 * 10 / 8 * pclk */
- pclk = pconf->lcd_timing.lcd_clk / 1000; /* kHz */
- band_width = byte_mode * 10 * pclk;
-
- temp = VBYONE_BIT_RATE_MAX * 1000;
- temp = (band_width + temp - 1) / temp;
- for (i = 0; i < 4; i++) {
- if (temp <= vbyone_lane_num[i])
- break;
- }
- minlane = vbyone_lane_num[i];
- if (lane_count < minlane) {
- LCDERR("vbyone lane_num(%d) is less than min(%d)\n",
- lane_count, minlane);
- lane_count = minlane;
- pconf->lcd_control.vbyone_config->lane_count = lane_count;
- LCDPR("change to min lane_num %d\n", minlane);
+ /* phy_div: 0=div6, 1=div 7, 2=div8, 3=div10 */
+ switch (pdrv->config.basic.lcd_bits) {
+ case 6:
+ div_sel = 0;
+ break;
+ case 8:
+ default:
+ div_sel = 2;
+ break;
}
- bit_rate = band_width / minlane;
- phy_div = lane_count / minlane;
- if (phy_div == 8) {
- phy_div /= 2;
- bit_rate /= 2;
- }
- if (bit_rate > (VBYONE_BIT_RATE_MAX * 1000)) {
- LCDERR("vbyone bit rate(%dKHz) is out of max(%dKHz)\n",
- bit_rate, (VBYONE_BIT_RATE_MAX * 1000));
- }
- if (bit_rate < (VBYONE_BIT_RATE_MIN * 1000)) {
- LCDERR("vbyone bit rate(%dKHz) is out of min(%dKHz)\n",
- bit_rate, (VBYONE_BIT_RATE_MIN * 1000));
- }
- bit_rate = bit_rate * 1000; /* Hz */
+ /* fifo_clk_sel[7:6]: 0=div6, 1=div 7, 2=div8, 3=div10 */
+ lcd_ana_write(HHI_LVDS_TX_PHY_CNTL0, (div_sel << 6));
+ /* serializer_en[27:16] */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12);
+ /* pn swap[2] */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL0, 1, 2, 1);
- pconf->lcd_control.vbyone_config->phy_div = phy_div;
- pconf->lcd_control.vbyone_config->bit_rate = bit_rate;
+ /* fifo enable[30], phy_clock gating[24] */
+ lcd_ana_write(HHI_LVDS_TX_PHY_CNTL1, (1 << 30) | (1 << 24));
+ /* fifo write enable[31] */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL1, 1, 31, 1);
- if (lcd_debug_print_flag) {
- LCDPR("lane_count=%u, bit_rate = %uMHz, pclk=%u.%03uMhz\n",
- lane_count, (bit_rate / 1000000),
- (pclk / 1000), (pclk % 1000));
- }
+ channel_sel0 = pdrv->config.control.mlvds_cfg.channel_sel0;
+ channel_sel1 = pdrv->config.control.mlvds_cfg.channel_sel1;
+ lcd_vcbus_write(P2P_CH_SWAP0, channel_sel0);
+ lcd_vcbus_write(P2P_CH_SWAP1, channel_sel1);
+
+ lcd_tcon_enable(pdrv);
}
-static void lcd_mlvds_config_set(struct lcd_config_s *pconf)
+static void lcd_mlvds_disable(struct aml_lcd_drv_s *pdrv)
{
- unsigned int bit_rate, pclk;
- unsigned int lcd_bits, channel_num;
- unsigned int channel_sel0, channel_sel1, pi_clk_sel;
- unsigned int i, temp;
+ lcd_tcon_disable(pdrv);
- if (lcd_debug_print_flag)
- LCDPR("%s\n", __func__);
-
- lcd_bits = pconf->lcd_basic.lcd_bits;
- channel_num = pconf->lcd_control.mlvds_config->channel_num;
- pclk = pconf->lcd_timing.lcd_clk / 1000;
- bit_rate = lcd_bits * 3 * pclk / channel_num;
-
- pconf->lcd_control.mlvds_config->bit_rate = bit_rate * 1000;
-
- if (lcd_debug_print_flag) {
- LCDPR("channel_num=%u, bit_rate=%u.%03uMHz, pclk=%u.%03uMhz\n",
- channel_num, (bit_rate / 1000), (bit_rate % 1000),
- (pclk / 1000), (pclk % 1000));
- }
-
- /* pi_clk select */
- /* mlvds channel: //tx 10 channels
- * 0: d0_a
- * 1: d1_a
- * 2: d2_a
- * 3: clk_a
- * 4: d0_b
- * 5: d1_b
- * 6: d2_b
- * 7: clk_b */
- channel_sel0 = pconf->lcd_control.mlvds_config->channel_sel0;
- channel_sel1 = pconf->lcd_control.mlvds_config->channel_sel1;
- pi_clk_sel = 0;
- for (i = 0; i < 8; i++) {
- temp = (channel_sel0 >> (i*4)) & 0xf;
- if ((temp == 3) || (temp == 7))
- pi_clk_sel |= (1 << i);
- }
- for (i = 0; i < 2; i++) {
- temp = (channel_sel1 >> (i*4)) & 0xf;
- if ((temp == 3) || (temp == 7))
- pi_clk_sel |= (1 << (i + 8));
- }
- pconf->lcd_control.mlvds_config->pi_clk_sel = pi_clk_sel;
- if (lcd_debug_print_flag) {
- LCDPR("channel_sel0=0x%08x, channel_sel1=0x%08x, pi_clk_sel=0x%03x\n",
- channel_sel0, channel_sel1, pi_clk_sel);
- }
+ /* disable fifo */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL1, 0, 30, 2);
+ /* disable lane */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL0, 0, 16, 12);
}
-void lcd_tv_config_update(struct lcd_config_s *pconf)
+static void lcd_p2p_control_set(struct aml_lcd_drv_s *pdrv)
+{
+ unsigned int phy_div, channel_sel0, channel_sel1;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
+
+ /* phy_div: 0=div6, 1=div 7, 2=div8, 3=div10 */
+ switch (pdrv->config.control.p2p_cfg.p2p_type) {
+ case P2P_CHPI: /* 8/10 coding */
+ case P2P_USIT:
+ phy_div = 3;
+ break;
+ default:
+ phy_div = 2;
+ break;
+ }
+
+ /* fifo_clk_sel[7:6]: 0=div6, 1=div 7, 2=div8, 3=div10 */
+ lcd_ana_write(HHI_LVDS_TX_PHY_CNTL0, (phy_div << 6));
+ /* serializer_en[27:16] */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL0, 0xfff, 16, 12);
+ /* pn swap[2] */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL0, 1, 2, 1);
+
+ /* fifo enable[30], phy_clock gating[24] */
+ lcd_ana_write(HHI_LVDS_TX_PHY_CNTL1, (1 << 30) | (1 << 24));
+ /* fifo write enable[31] */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL1, 1, 31, 1);
+
+ channel_sel0 = pdrv->config.control.p2p_cfg.channel_sel0;
+ channel_sel1 = pdrv->config.control.p2p_cfg.channel_sel1;
+ lcd_vcbus_write(P2P_CH_SWAP0, channel_sel0);
+ lcd_vcbus_write(P2P_CH_SWAP1, channel_sel1);
+
+ lcd_tcon_enable(pdrv);
+}
+
+static void lcd_p2p_disable(struct aml_lcd_drv_s *pdrv)
+{
+ lcd_tcon_disable(pdrv);
+
+ /* disable fifo */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL1, 0, 30, 2);
+ /* disable lane */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL0, 0, 16, 12);
+}
+#endif
+
+void lcd_tv_config_update(struct aml_lcd_drv_s *pdrv)
{
/* update interface timing */
- switch (pconf->lcd_basic.lcd_type) {
+ switch (pdrv->config.basic.lcd_type) {
case LCD_VBYONE:
- lcd_vbyone_config_set(pconf);
+ lcd_vbyone_config_set(pdrv);
break;
+#ifdef CONFIG_AML_LCD_TCON
case LCD_MLVDS:
- lcd_mlvds_config_set(pconf);
+ lcd_mlvds_config_set(pdrv);
break;
+ case LCD_P2P:
+ lcd_p2p_config_set(pdrv);
+ break;
+#endif
default:
break;
}
}
-void lcd_tv_driver_init_pre(void)
+void lcd_tv_driver_init_pre(struct aml_lcd_drv_s *pdrv)
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- struct lcd_config_s *pconf;
int ret;
- pconf = lcd_drv->lcd_config;
- LCDPR("tv driver init(ver %s): %s\n", lcd_drv->version,
- lcd_type_type_to_str(pconf->lcd_basic.lcd_type));
- ret = lcd_type_supported(pconf);
+ LCDPR("[%d]: tv driver init(ver %s): %s\n",
+ pdrv->index,
+ LCD_DRV_VERSION,
+ lcd_type_type_to_str(pdrv->config.basic.lcd_type));
+ ret = lcd_type_supported(&pdrv->config);
if (ret)
return;
- lcd_clk_set(pconf);
- lcd_venc_set(pconf);
- lcd_encl_tcon_set(pconf);
- vpp_init_lcd_gamma_table();
+ lcd_set_clk(pdrv);
+ lcd_set_venc(pdrv);
}
-int lcd_tv_driver_init(void)
+int lcd_tv_driver_init(struct aml_lcd_drv_s *pdrv)
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- struct lcd_config_s *pconf;
int ret;
- pconf = lcd_drv->lcd_config;
- ret = lcd_type_supported(pconf);
+ ret = lcd_type_supported(&pdrv->config);
if (ret)
return -1;
/* init driver */
- switch (pconf->lcd_basic.lcd_type) {
+ switch (pdrv->config.basic.lcd_type) {
case LCD_LVDS:
- lcd_lvds_control_set(pconf);
- lcd_lvds_phy_set(pconf, 1);
+ lcd_lvds_control_set(pdrv);
+ lcd_phy_set(pdrv, 1);
break;
case LCD_VBYONE:
- lcd_pinmux_set(1);
- lcd_vbyone_control_set(pconf);
- lcd_vbyone_wait_hpd(pconf);
- lcd_vbyone_phy_set(pconf, 1);
- lcd_vbyone_wait_stable(pconf);
+ lcd_pinmux_set(pdrv, 1);
+ lcd_vbyone_control_set(pdrv);
+ lcd_vbyone_wait_hpd(pdrv);
+ lcd_phy_set(pdrv, 1);
+ lcd_vbyone_wait_stable(pdrv);
break;
+#ifdef CONFIG_AML_LCD_TCON
case LCD_MLVDS:
- lcd_mlvds_control_set(pconf);
- lcd_pinmux_set(1);
- lcd_mlvds_phy_set(pconf, 1);
+ lcd_mlvds_control_set(pdrv);
+ lcd_pinmux_set(pdrv, 1);
+ lcd_phy_set(pdrv, 1);
break;
+ case LCD_P2P:
+ lcd_pinmux_set(pdrv, 1);
+ lcd_phy_set(pdrv, 1);
+ lcd_p2p_control_set(pdrv);
+ break;
+#endif
default:
break;
}
- lcd_vcbus_write(VENC_INTCTRL, 0x200);
-
- if (lcd_debug_print_flag)
- LCDPR("%s finished\n", __func__);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s finished\n", pdrv->index, __func__);
return 0;
}
-void lcd_tv_driver_disable(void)
+void lcd_tv_driver_disable(struct aml_lcd_drv_s *pdrv)
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- struct lcd_config_s *pconf;
int ret;
- LCDPR("disable driver\n");
- pconf = lcd_drv->lcd_config;
- ret = lcd_type_supported(pconf);
+ LCDPR("[%d]: disable driver\n", pdrv->index);
+ ret = lcd_type_supported(&pdrv->config);
if (ret)
return;
- switch (pconf->lcd_basic.lcd_type) {
+ switch (pdrv->config.basic.lcd_type) {
case LCD_LVDS:
- lcd_lvds_phy_set(pconf, 0);
- lcd_lvds_disable();
+ lcd_phy_set(pdrv, 0);
+ lcd_lvds_disable(pdrv);
break;
case LCD_VBYONE:
- lcd_vbyone_phy_set(pconf, 0);
- lcd_pinmux_set(0);
- lcd_vbyone_disable();
+ lcd_phy_set(pdrv, 0);
+ lcd_pinmux_set(pdrv, 0);
+ lcd_vbyone_disable(pdrv);
break;
+#ifdef CONFIG_AML_LCD_TCON
case LCD_MLVDS:
- lcd_mlvds_disable();
- lcd_mlvds_phy_set(pconf, 0);
- lcd_pinmux_set(0);
+ lcd_mlvds_disable(pdrv);
+ lcd_phy_set(pdrv, 0);
+ lcd_pinmux_set(pdrv, 0);
break;
+ case LCD_P2P:
+ lcd_p2p_disable(pdrv);
+ lcd_phy_set(pdrv, 0);
+ lcd_pinmux_set(pdrv, 0);
+ break;
+#endif
default:
break;
}
- lcd_vcbus_write(ENCL_VIDEO_EN, 0);
-
- lcd_clk_disable();
-
- if (lcd_debug_print_flag)
- LCDPR("%s finished\n", __func__);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s finished\n", pdrv->index, __func__);
}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c
index 0ad7103..3024ef0 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -43,6 +28,7 @@
unsigned int width;
unsigned int height;
unsigned int frame_rate;
+ unsigned int frac;
};
@@ -61,6 +47,7 @@
.width = 1024,
.height = 600,
.frame_rate = 60,
+ .frac = 0,
},
{
.name = "768p",
@@ -68,6 +55,7 @@
.width = 1366,
.height = 768,
.frame_rate = 60,
+ .frac = 0,
},
{
.name = "1080p",
@@ -75,6 +63,7 @@
.width = 1920,
.height = 1080,
.frame_rate = 60,
+ .frac = 0,
},
{
.name = "2160p",
@@ -82,6 +71,7 @@
.width = 3840,
.height = 2160,
.frame_rate = 60,
+ .frac = 0,
},
{
.name = "invalid",
@@ -89,19 +79,20 @@
.width = 1920,
.height = 1080,
.frame_rate = 60,
+ .frac = 0,
},
};
static int lcd_vmode_is_mached(struct lcd_config_s *pconf, int index)
{
- if ((pconf->lcd_basic.h_active == lcd_vmode_info[index].width) &&
- (pconf->lcd_basic.v_active == lcd_vmode_info[index].height))
+ if ((pconf->basic.h_active == lcd_vmode_info[index].width) &&
+ (pconf->basic.v_active == lcd_vmode_info[index].height))
return 0;
else
return -1;
}
-static int lcd_outputmode_to_lcd_vmode(const char *mode)
+static int lcd_outputmode_to_vmode(const char *mode)
{
int lcd_vmode = LCD_VMODE_MAX;
int i, count = ARRAY_SIZE(lcd_vmode_info) - 1;
@@ -114,7 +105,7 @@
n = p - mode + 1;
strncpy(temp, mode, n);
temp[n] = '\0';
- if (lcd_debug_print_flag)
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
LCDPR("outputmode=%s, lcd_vmode=%s\n", mode, temp);
for (i = 0; i < count; i++) {
@@ -126,7 +117,7 @@
return lcd_vmode;
}
-static int lcd_outputmode_to_lcd_frame_rate(const char *mode)
+static int lcd_outputmode_to_frame_rate(const char *mode)
{
int frame_rate = 0;
char temp[30], *p;
@@ -142,7 +133,7 @@
return 0;
*p = '\0';
n = (int)simple_strtoul(temp, NULL, 10);
- if (lcd_debug_print_flag)
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
LCDPR("outputmode=%s, frame_rate=%d\n", mode, n);
for (i = 0; i < ARRAY_SIZE(lcd_std_frame_rate); i++) {
@@ -154,49 +145,59 @@
return frame_rate;
}
-static int check_lcd_output_mode(struct lcd_config_s *pconf, char *mode)
+static int check_lcd_output_mode(struct aml_lcd_drv_s *pdrv, char *mode,
+ unsigned int frac)
{
int lcd_vmode, frame_rate;
int ret;
- if (mode == NULL)
+ if (!mode)
return LCD_VMODE_MAX;
- lcd_vmode = lcd_outputmode_to_lcd_vmode(mode);
+ lcd_vmode = lcd_outputmode_to_vmode(mode);
if (lcd_vmode >= LCD_VMODE_MAX) {
LCDERR("%s: outputmode %s is not support\n", __func__, mode);
return LCD_VMODE_MAX;
}
- frame_rate = lcd_outputmode_to_lcd_frame_rate(mode);
- if (frame_rate == 0) {
- LCDERR("%s: frame_rate is not support\n", __func__);
- return LCD_VMODE_MAX;
- } else {
- lcd_vmode_info[lcd_vmode].frame_rate = frame_rate;
- }
- ret = lcd_vmode_is_mached(pconf, lcd_vmode);
+
+ ret = lcd_vmode_is_mached(&pdrv->config, lcd_vmode);
if (ret) {
LCDERR("outputmode[%s] and panel_type is not match\n",
lcd_vmode_info[lcd_vmode].name);
return LCD_VMODE_MAX;
}
+ frame_rate = lcd_outputmode_to_frame_rate(mode);
+ if (frame_rate == 0) {
+ LCDERR("%s: frame_rate is not support\n", __func__);
+ return LCD_VMODE_MAX;
+ }
+ if (frac) {
+ if (frame_rate != 60) {
+ LCDERR("%s: don't support frac under mode %s\n",
+ __func__, mode);
+ return LCD_VMODE_MAX;
+ }
+ lcd_vmode_info[lcd_vmode].frac = 1;
+ } else {
+ lcd_vmode_info[lcd_vmode].frac = 0;
+ }
+ lcd_vmode_info[lcd_vmode].frame_rate = frame_rate;
+
return lcd_vmode;
}
-static void lcd_list_support_mode(void)
+static void lcd_list_support_mode(struct lcd_config_s *pconf)
{
int i, j;
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- struct lcd_basic_s *lcd_basic;
char str[30];
- lcd_basic = &lcd_drv->lcd_config->lcd_basic;
for (i = 0; i < (ARRAY_SIZE(lcd_vmode_info) - 1); i++) {
- if ((lcd_basic->h_active == lcd_vmode_info[i].width) &&
- (lcd_basic->v_active == lcd_vmode_info[i].height)) {
+ if ((pconf->basic.h_active == lcd_vmode_info[i].width) &&
+ (pconf->basic.v_active == lcd_vmode_info[i].height)) {
for (j = 0; j < ARRAY_SIZE(lcd_std_frame_rate); j++) {
- sprintf(str, "%s%dhz", lcd_vmode_info[i].name, lcd_std_frame_rate[j]);
+ sprintf(str, "%s%dhz",
+ lcd_vmode_info[i].name, lcd_std_frame_rate[j]);
printf("%s\n", str);
}
break;
@@ -204,893 +205,79 @@
}
}
-static void lcd_config_load_print(struct lcd_config_s *pconf)
+static void lcd_config_init(struct aml_lcd_drv_s *pdrv)
{
- if (lcd_debug_print_flag == 0)
- return;
-
- LCDPR("%s, %s, %dbit, %dx%d\n",
- pconf->lcd_basic.model_name,
- lcd_type_type_to_str(pconf->lcd_basic.lcd_type),
- pconf->lcd_basic.lcd_bits,
- pconf->lcd_basic.h_active, pconf->lcd_basic.v_active);
-
- LCDPR("h_period = %d\n", pconf->lcd_basic.h_period);
- LCDPR("v_period = %d\n", pconf->lcd_basic.v_period);
-
- LCDPR("h_period_min = %d\n", pconf->lcd_basic.h_period_min);
- LCDPR("h_period_max = %d\n", pconf->lcd_basic.h_period_max);
- LCDPR("v_period_min = %d\n", pconf->lcd_basic.v_period_min);
- LCDPR("v_period_max = %d\n", pconf->lcd_basic.v_period_max);
- LCDPR("pclk_min = %d\n", pconf->lcd_basic.lcd_clk_min);
- LCDPR("pclk_max = %d\n", pconf->lcd_basic.lcd_clk_max);
-
- LCDPR("hsync_width = %d\n", pconf->lcd_timing.hsync_width);
- LCDPR("hsync_bp = %d\n", pconf->lcd_timing.hsync_bp);
- LCDPR("hsync_pol = %d\n", pconf->lcd_timing.hsync_pol);
- LCDPR("vsync_width = %d\n", pconf->lcd_timing.vsync_width);
- LCDPR("vsync_bp = %d\n", pconf->lcd_timing.vsync_bp);
- LCDPR("vsync_pol = %d\n", pconf->lcd_timing.vsync_pol);
-
- LCDPR("fr_adjust_type = %d\n", pconf->lcd_timing.fr_adjust_type);
- LCDPR("ss_level = %d\n", pconf->lcd_timing.ss_level);
- LCDPR("clk_auto = %d\n", pconf->lcd_timing.clk_auto);
-
- if (pconf->lcd_basic.lcd_type == LCD_VBYONE) {
- LCDPR("lane_count = %d\n", pconf->lcd_control.vbyone_config->lane_count);
- LCDPR("byte_mode = %d\n", pconf->lcd_control.vbyone_config->byte_mode);
- LCDPR("region_num = %d\n", pconf->lcd_control.vbyone_config->region_num);
- LCDPR("color_fmt = %d\n", pconf->lcd_control.vbyone_config->color_fmt);
- } else if (pconf->lcd_basic.lcd_type == LCD_LVDS) {
- LCDPR("lvds_repack = %d\n", pconf->lcd_control.lvds_config->lvds_repack);
- LCDPR("pn_swap = %d\n", pconf->lcd_control.lvds_config->pn_swap);
- LCDPR("dual_port = %d\n", pconf->lcd_control.lvds_config->dual_port);
- LCDPR("port_swap = %d\n", pconf->lcd_control.lvds_config->port_swap);
- LCDPR("lane_reverse = %d\n", pconf->lcd_control.lvds_config->lane_reverse);
- }
-}
-
-static int lcd_config_load_from_dts(const void *dt_blob, struct lcd_config_s *pconf)
-{
- int parent_offset;
- int child_offset;
- char propname[30];
- char *propdata;
- int len;
- struct lvds_config_s *lvds_conf;
- struct vbyone_config_s *vx1_conf;
- struct mlvds_config_s *mlvds_conf;
-
- parent_offset = fdt_path_offset(dt_blob, "/lcd");
- if (parent_offset < 0) {
- LCDERR("not find /lcd node: %s\n",fdt_strerror(parent_offset));
- return -1;
- }
-
- propdata = (char *)fdt_getprop(dt_blob, parent_offset, "pinctrl_version", NULL);
- if (propdata) {
- pconf->pinctrl_ver = (unsigned char)(be32_to_cpup((u32*)propdata));
- } else {
- pconf->pinctrl_ver = 0;
- }
- LCDPR("pinctrl_version: %d\n", pconf->pinctrl_ver);
-
- /* check panel_type */
- char *panel_type = env_get("panel_type");
- if (panel_type == NULL) {
- LCDERR("no panel_type, use default lcd config\n ");
- return -1;
- }
- LCDPR("use panel_type=%s\n", panel_type);
-
- sprintf(propname, "/lcd/%s", panel_type);
- child_offset = fdt_path_offset(dt_blob, propname);
- if (child_offset < 0) {
- LCDERR("not find /lcd/%s node: %s\n",
- panel_type, fdt_strerror(child_offset));
- return -1;
- }
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "model_name", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get model_name\n");
- strcpy(pconf->lcd_basic.model_name, panel_type);
- } else {
- strcpy(pconf->lcd_basic.model_name, propdata);
- }
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "interface", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get interface\n");
- return -1;
- } else {
- pconf->lcd_basic.lcd_type = lcd_type_str_to_type(propdata);
- }
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "basic_setting", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get basic_setting\n");
- return -1;
- } else {
- pconf->lcd_basic.h_active = be32_to_cpup((u32*)propdata);
- pconf->lcd_basic.v_active = be32_to_cpup((((u32*)propdata)+1));
- pconf->lcd_basic.h_period = be32_to_cpup((((u32*)propdata)+2));
- pconf->lcd_basic.v_period = be32_to_cpup((((u32*)propdata)+3));
- pconf->lcd_basic.lcd_bits = be32_to_cpup((((u32*)propdata)+4));
- pconf->lcd_basic.screen_width = be32_to_cpup((((u32*)propdata)+5));
- pconf->lcd_basic.screen_height = be32_to_cpup((((u32*)propdata)+6));
- }
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "range_setting", NULL);
- if (propdata == NULL) {
- LCDPR("no range_setting\n");
- pconf->lcd_basic.h_period_min = pconf->lcd_basic.h_period;
- pconf->lcd_basic.h_period_max = pconf->lcd_basic.h_period;
- pconf->lcd_basic.v_period_min = pconf->lcd_basic.v_period;
- pconf->lcd_basic.v_period_max = pconf->lcd_basic.v_period;
- pconf->lcd_basic.lcd_clk_min = 0;
- pconf->lcd_basic.lcd_clk_max = 0;
- } else {
- pconf->lcd_basic.h_period_min = be32_to_cpup((u32*)propdata);
- pconf->lcd_basic.h_period_max = be32_to_cpup((((u32*)propdata)+1));
- pconf->lcd_basic.v_period_min = be32_to_cpup((((u32*)propdata)+2));
- pconf->lcd_basic.v_period_max = be32_to_cpup((((u32*)propdata)+3));
- pconf->lcd_basic.lcd_clk_min = be32_to_cpup((((u32*)propdata)+4));
- pconf->lcd_basic.lcd_clk_max = be32_to_cpup((((u32*)propdata)+5));
- }
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "lcd_timing", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get lcd_timing\n");
- return -1;
- } else {
- pconf->lcd_timing.hsync_width = (unsigned short)(be32_to_cpup((u32*)propdata));
- pconf->lcd_timing.hsync_bp = (unsigned short)(be32_to_cpup((((u32*)propdata)+1)));
- pconf->lcd_timing.hsync_pol = (unsigned short)(be32_to_cpup((((u32*)propdata)+2)));
- pconf->lcd_timing.vsync_width = (unsigned short)(be32_to_cpup((((u32*)propdata)+3)));
- pconf->lcd_timing.vsync_bp = (unsigned short)(be32_to_cpup((((u32*)propdata)+4)));
- pconf->lcd_timing.vsync_pol = (unsigned short)(be32_to_cpup((((u32*)propdata)+5)));
- }
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "clk_attr", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get clk_attr\n");
- pconf->lcd_timing.fr_adjust_type = 0;
- pconf->lcd_timing.ss_level = 0;
- pconf->lcd_timing.clk_auto = 1;
- pconf->lcd_timing.lcd_clk = 60;
- } else {
- pconf->lcd_timing.fr_adjust_type = (unsigned char)(be32_to_cpup((u32*)propdata));
- pconf->lcd_timing.ss_level = (unsigned char)(be32_to_cpup((((u32*)propdata)+1)));
- pconf->lcd_timing.clk_auto = (unsigned char)(be32_to_cpup((((u32*)propdata)+2)));
- pconf->lcd_timing.lcd_clk = (unsigned char)(be32_to_cpup((((u32*)propdata)+3)));
- }
-
- switch (pconf->lcd_basic.lcd_type) {
- case LCD_LVDS:
- lvds_conf = pconf->lcd_control.lvds_config;
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "lvds_attr", &len);
- if (propdata == NULL) {
- LCDERR("failed to get lvds_attr\n");
- } else {
- len = len / 4;
- if (len == 5) {
- lvds_conf->lvds_repack = be32_to_cpup((u32*)propdata);
- lvds_conf->dual_port = be32_to_cpup((((u32*)propdata)+1));
- lvds_conf->pn_swap = be32_to_cpup((((u32*)propdata)+2));
- lvds_conf->port_swap = be32_to_cpup((((u32*)propdata)+3));
- lvds_conf->lane_reverse = be32_to_cpup((((u32*)propdata)+4));
- } else if (len == 4) {
- lvds_conf->lvds_repack = be32_to_cpup((u32*)propdata);
- lvds_conf->dual_port = be32_to_cpup((((u32*)propdata)+1));
- lvds_conf->pn_swap = be32_to_cpup((((u32*)propdata)+2));
- lvds_conf->port_swap = be32_to_cpup((((u32*)propdata)+3));
- lvds_conf->lane_reverse = 0;
- } else {
- LCDERR("invalid lvds_attr parameters cnt: %d\n", len);
- }
- }
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "phy_attr", &len);
- if (propdata == NULL) {
- if (lcd_debug_print_flag)
- LCDPR("failed to get phy_attr\n");
- lvds_conf->phy_vswing = LVDS_PHY_VSWING_DFT;
- lvds_conf->phy_preem = LVDS_PHY_PREEM_DFT;
- lvds_conf->phy_clk_vswing = LVDS_PHY_CLK_VSWING_DFT;
- lvds_conf->phy_clk_preem = LVDS_PHY_CLK_PREEM_DFT;
- } else {
- len = len / 4;
- if (len == 4) {
- lvds_conf->phy_vswing = be32_to_cpup((u32*)propdata);
- lvds_conf->phy_preem = be32_to_cpup((((u32*)propdata)+1));
- lvds_conf->phy_clk_vswing = be32_to_cpup((((u32*)propdata)+2));
- lvds_conf->phy_clk_preem = be32_to_cpup((((u32*)propdata)+3));
- if (lcd_debug_print_flag) {
- LCDPR("set phy vswing=0x%x, preemphasis=0x%x\n",
- lvds_conf->phy_vswing, lvds_conf->phy_preem);
- LCDPR("set phy clk_vswing=0x%x, clk_preemphasis=0x%x\n",
- lvds_conf->phy_clk_vswing, lvds_conf->phy_clk_preem);
- }
- } else if (len == 2) {
- lvds_conf->phy_vswing = be32_to_cpup((u32*)propdata);
- lvds_conf->phy_preem = be32_to_cpup((((u32*)propdata)+1));
- lvds_conf->phy_clk_vswing = LVDS_PHY_CLK_VSWING_DFT;
- lvds_conf->phy_clk_preem = LVDS_PHY_CLK_PREEM_DFT;
- if (lcd_debug_print_flag) {
- LCDPR("set phy vswing=0x%x, preemphasis=0x%x\n",
- lvds_conf->phy_vswing, lvds_conf->phy_preem);
- }
- } else {
- LCDERR("invalid phy_attr parameters cnt: %d\n", len);
- }
- }
- break;
- case LCD_MLVDS:
- mlvds_conf = pconf->lcd_control.mlvds_config;
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "minilvds_attr", &len);
- if (propdata == NULL) {
- LCDERR("failed to get minilvds_attr\n");
- } else {
- mlvds_conf->channel_num = be32_to_cpup((u32*)propdata);
- mlvds_conf->channel_sel0 = be32_to_cpup((((u32*)propdata)+1));
- mlvds_conf->channel_sel1 = be32_to_cpup((((u32*)propdata)+2));
- mlvds_conf->clk_phase = be32_to_cpup((((u32*)propdata)+3));
- mlvds_conf->pn_swap = be32_to_cpup((((u32*)propdata)+4));
- mlvds_conf->bit_swap = be32_to_cpup((((u32*)propdata)+5));
- }
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "phy_attr", &len);
- if (propdata == NULL) {
- if (lcd_debug_print_flag)
- LCDPR("failed to get phy_attr\n");
- mlvds_conf->phy_vswing = LVDS_PHY_VSWING_DFT;
- mlvds_conf->phy_preem = LVDS_PHY_PREEM_DFT;
- } else {
- mlvds_conf->phy_vswing = be32_to_cpup((u32*)propdata);
- mlvds_conf->phy_preem = be32_to_cpup((((u32*)propdata)+1));
- if (lcd_debug_print_flag) {
- LCDPR("set phy vswing=0x%x, preemphasis=0x%x\n",
- mlvds_conf->phy_vswing, mlvds_conf->phy_preem);
- }
- }
- break;
- case LCD_VBYONE:
- vx1_conf = pconf->lcd_control.vbyone_config;
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "vbyone_attr", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get vbyone_attr\n");
- } else {
- vx1_conf->lane_count = be32_to_cpup((u32*)propdata);
- vx1_conf->region_num = be32_to_cpup((((u32*)propdata)+1));
- vx1_conf->byte_mode = be32_to_cpup((((u32*)propdata)+2));
- vx1_conf->color_fmt = be32_to_cpup((((u32*)propdata)+3));
- }
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "phy_attr", NULL);
- if (propdata == NULL) {
- if (lcd_debug_print_flag)
- LCDPR("failed to get phy_attr\n");
- vx1_conf->phy_vswing = VX1_PHY_VSWING_DFT;
- vx1_conf->phy_preem = VX1_PHY_PREEM_DFT;
- } else {
- vx1_conf->phy_vswing = be32_to_cpup((u32*)propdata);
- vx1_conf->phy_preem = be32_to_cpup((((u32*)propdata)+1));
- if (lcd_debug_print_flag) {
- LCDPR("set phy vswing=0x%x, preemphasis=0x%x\n",
- vx1_conf->phy_vswing, vx1_conf->phy_preem);
- }
- }
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "vbyone_ctrl_flag", NULL);
- if (propdata == NULL) {
- if (lcd_debug_print_flag)
- LCDPR("failed to get vbyone_ctrl_flag\n");
- vx1_conf->ctrl_flag = 0;
- vx1_conf->power_on_reset_delay = VX1_PWR_ON_RESET_DLY_DFT;
- vx1_conf->hpd_data_delay = VX1_HPD_DATA_DELAY_DFT;
- vx1_conf->cdr_training_hold = VX1_CDR_TRAINING_HOLD_DFT;
- vx1_conf->vx1_sw_filter_en = 0;
- vx1_conf->vx1_sw_filter_time = VX1_SW_FILTER_TIME_DFT;
- vx1_conf->vx1_sw_filter_cnt = VX1_SW_FILTER_CNT_DFT;
- vx1_conf->vx1_sw_filter_retry_cnt = VX1_SW_FILTER_RETRY_CNT_DFT;
- vx1_conf->vx1_sw_filter_retry_delay = VX1_SW_FILTER_RETRY_DLY_DFT;
- vx1_conf->vx1_sw_cdr_detect_time = VX1_SW_CDR_DET_TIME_DFT;
- vx1_conf->vx1_sw_cdr_detect_cnt = VX1_SW_CDR_DET_CNT_DFT;
- vx1_conf->vx1_sw_cdr_timeout_cnt = VX1_SW_CDR_TIMEOUT_CNT_DFT;
- } else {
- vx1_conf->ctrl_flag = be32_to_cpup((u32*)propdata);
- vx1_conf->vx1_sw_filter_en = (vx1_conf->ctrl_flag >> 4) & 3;
- LCDPR("vbyone ctrl_flag=0x%x\n", vx1_conf->ctrl_flag);
- }
- if (vx1_conf->ctrl_flag & 0x7) {
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "vbyone_ctrl_timing", NULL);
- if (propdata == NULL) {
- LCDPR("failed to get vbyone_ctrl_timing\n");
- vx1_conf->power_on_reset_delay = VX1_PWR_ON_RESET_DLY_DFT;
- vx1_conf->hpd_data_delay = VX1_HPD_DATA_DELAY_DFT;
- vx1_conf->cdr_training_hold = VX1_CDR_TRAINING_HOLD_DFT;
- } else {
- vx1_conf->power_on_reset_delay = be32_to_cpup((u32*)propdata);
- vx1_conf->hpd_data_delay = be32_to_cpup((((u32*)propdata)+1));
- vx1_conf->cdr_training_hold = be32_to_cpup((((u32*)propdata)+2));
- }
- if (lcd_debug_print_flag) {
- LCDPR("power_on_reset_delay: %d\n", vx1_conf->power_on_reset_delay);
- LCDPR("hpd_data_delay: %d\n", vx1_conf->hpd_data_delay);
- LCDPR("cdr_training_hold: %d\n", vx1_conf->cdr_training_hold);
- }
- }
- if (vx1_conf->vx1_sw_filter_en) {
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "vbyone_sw_filter", NULL);
- if (propdata == NULL) {
- LCDPR("failed to get vbyone_sw_filter\n");
- vx1_conf->vx1_sw_filter_time = VX1_SW_FILTER_TIME_DFT;
- vx1_conf->vx1_sw_filter_cnt = VX1_SW_FILTER_CNT_DFT;
- vx1_conf->vx1_sw_filter_retry_cnt = VX1_SW_FILTER_RETRY_CNT_DFT;
- vx1_conf->vx1_sw_filter_retry_delay = VX1_SW_FILTER_RETRY_DLY_DFT;
- vx1_conf->vx1_sw_cdr_detect_time = VX1_SW_CDR_DET_TIME_DFT;
- vx1_conf->vx1_sw_cdr_detect_cnt = VX1_SW_CDR_DET_CNT_DFT;
- vx1_conf->vx1_sw_cdr_timeout_cnt = VX1_SW_CDR_TIMEOUT_CNT_DFT;
- } else {
- vx1_conf->vx1_sw_filter_time = be32_to_cpup((u32*)propdata);
- vx1_conf->vx1_sw_filter_cnt = be32_to_cpup((((u32*)propdata)+1));
- vx1_conf->vx1_sw_filter_retry_cnt = be32_to_cpup((((u32*)propdata)+2));
- vx1_conf->vx1_sw_filter_retry_delay = be32_to_cpup((((u32*)propdata)+3));
- vx1_conf->vx1_sw_cdr_detect_time = be32_to_cpup((((u32*)propdata)+4));
- vx1_conf->vx1_sw_cdr_detect_cnt = be32_to_cpup((((u32*)propdata)+5));
- vx1_conf->vx1_sw_cdr_timeout_cnt = be32_to_cpup((((u32*)propdata)+6));
- if (lcd_debug_print_flag) {
- LCDPR("vx1_sw_filter_en: %d\n", vx1_conf->vx1_sw_filter_en);
- LCDPR("vx1_sw_filter_time: %d\n", vx1_conf->vx1_sw_filter_time);
- LCDPR("vx1_sw_filter_cnt: %d\n", vx1_conf->vx1_sw_filter_cnt);
- LCDPR("vx1_sw_filter_retry_cnt: %d\n", vx1_conf->vx1_sw_filter_retry_cnt);
- LCDPR("vx1_sw_filter_retry_delay: %d\n", vx1_conf->vx1_sw_filter_retry_delay);
- LCDPR("vx1_sw_cdr_detect_time: %d\n", vx1_conf->vx1_sw_cdr_detect_time);
- LCDPR("vx1_sw_cdr_detect_cnt: %d\n", vx1_conf->vx1_sw_cdr_detect_cnt);
- LCDPR("vx1_sw_cdr_timeout_cnt: %d\n", vx1_conf->vx1_sw_cdr_timeout_cnt);
- }
- }
- }
- break;
- default:
- LCDERR("invalid lcd type\n");
- break;
- }
-
- /* check power_step */
- lcd_power_load_from_dts(pconf, dt_blob, child_offset);
-
- propdata = (char *)fdt_getprop(dt_blob, child_offset, "backlight_index", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get backlight_index\n");
- pconf->backlight_index = 0xff;
- return 0;
- } else {
- pconf->backlight_index = be32_to_cpup((u32*)propdata);
- }
-
- return 0;
-}
-
-static int lcd_config_load_from_bsp(struct lcd_config_s *pconf)
-{
- struct ext_lcd_config_s *ext_lcd = NULL;
- char *panel_type = env_get("panel_type");
- unsigned int i;
- unsigned int temp;
- struct lcd_power_step_s *power_step;
-
- if (panel_type == NULL) {
- LCDERR("no panel_type, use default lcd config\n ");
- return -1;
- }
- for (i = 0 ; i < LCD_NUM_MAX ; i++) {
- ext_lcd = &ext_lcd_config[i];
- if (strcmp(ext_lcd->panel_type, panel_type) == 0)
- break ;
- if (strcmp(ext_lcd->panel_type, "invalid") == 0) {
- i = LCD_NUM_MAX;
- break;
- }
- }
- if (i >= LCD_NUM_MAX) {
- LCDERR("can't find %s, use default lcd config\n ", panel_type);
- return -1;
- }
- LCDPR("use panel_type=%s\n", panel_type);
-
- strcpy(pconf->lcd_basic.model_name, panel_type);
- pconf->lcd_basic.lcd_type = ext_lcd->lcd_type;
- pconf->lcd_basic.lcd_bits = ext_lcd->lcd_bits;
-
- pconf->lcd_basic.h_active = ext_lcd->h_active;
- pconf->lcd_basic.v_active = ext_lcd->v_active;
- pconf->lcd_basic.h_period = ext_lcd->h_period;
- pconf->lcd_basic.v_period = ext_lcd->v_period;
-
- pconf->lcd_basic.h_period_min = pconf->lcd_basic.h_period;
- pconf->lcd_basic.h_period_max = pconf->lcd_basic.h_period;
- pconf->lcd_basic.v_period_min = pconf->lcd_basic.v_period;
- pconf->lcd_basic.v_period_max = pconf->lcd_basic.v_period;
- pconf->lcd_basic.lcd_clk_min = 0;
- pconf->lcd_basic.lcd_clk_max = 0;
-
- pconf->lcd_timing.hsync_width = ext_lcd->hsync_width;
- pconf->lcd_timing.hsync_bp = ext_lcd->hsync_bp;
- pconf->lcd_timing.hsync_pol = ext_lcd->hsync_pol;
- pconf->lcd_timing.vsync_width = ext_lcd->vsync_width;
- pconf->lcd_timing.vsync_bp = ext_lcd->vsync_bp;
- pconf->lcd_timing.vsync_pol = ext_lcd->vsync_pol;
-
- /* fr_adjust_type */
- temp = ext_lcd->customer_val_0;
- if (temp == Rsv_val)
- pconf->lcd_timing.fr_adjust_type = 0;
- else
- pconf->lcd_timing.fr_adjust_type = (unsigned char)temp;
- /* ss_level */
- temp = ext_lcd->customer_val_1;
- if (temp == Rsv_val)
- pconf->lcd_timing.ss_level = 0;
- else
- pconf->lcd_timing.ss_level = (unsigned char)temp;
- /* clk_auto_generate */
- temp = ext_lcd->customer_val_2;
- if (temp == Rsv_val)
- pconf->lcd_timing.clk_auto = 1;
- else
- pconf->lcd_timing.clk_auto = (unsigned char)temp;
-
- if (pconf->lcd_basic.lcd_type == LCD_VBYONE) {
- pconf->lcd_control.vbyone_config->lane_count = ext_lcd->if_attr_val0;
- pconf->lcd_control.vbyone_config->region_num = ext_lcd->if_attr_val1;
- pconf->lcd_control.vbyone_config->byte_mode = ext_lcd->if_attr_val2;
- pconf->lcd_control.vbyone_config->color_fmt = ext_lcd->if_attr_val3;
- pconf->lcd_control.vbyone_config->phy_vswing = VX1_PHY_VSWING_DFT;
- pconf->lcd_control.vbyone_config->phy_preem = VX1_PHY_PREEM_DFT;
-
- pconf->lcd_control.vbyone_config->ctrl_flag = 0;
- pconf->lcd_control.vbyone_config->power_on_reset_delay = VX1_PWR_ON_RESET_DLY_DFT;
- pconf->lcd_control.vbyone_config->hpd_data_delay = VX1_HPD_DATA_DELAY_DFT;
- pconf->lcd_control.vbyone_config->cdr_training_hold = VX1_CDR_TRAINING_HOLD_DFT;
- pconf->lcd_control.vbyone_config->vx1_sw_filter_en = 0;
- pconf->lcd_control.vbyone_config->vx1_sw_filter_time = VX1_SW_FILTER_TIME_DFT;
- pconf->lcd_control.vbyone_config->vx1_sw_filter_cnt = VX1_SW_FILTER_CNT_DFT;
- pconf->lcd_control.vbyone_config->vx1_sw_filter_retry_cnt = VX1_SW_FILTER_RETRY_CNT_DFT;
- pconf->lcd_control.vbyone_config->vx1_sw_filter_retry_delay = VX1_SW_FILTER_RETRY_DLY_DFT;
- pconf->lcd_control.vbyone_config->vx1_sw_cdr_detect_time = VX1_SW_CDR_DET_TIME_DFT;
- pconf->lcd_control.vbyone_config->vx1_sw_cdr_detect_cnt = VX1_SW_CDR_DET_CNT_DFT;
- pconf->lcd_control.vbyone_config->vx1_sw_cdr_timeout_cnt = VX1_SW_CDR_TIMEOUT_CNT_DFT;
- } else if (pconf->lcd_basic.lcd_type == LCD_LVDS) {
- pconf->lcd_control.lvds_config->lvds_repack = ext_lcd->if_attr_val0;
- pconf->lcd_control.lvds_config->dual_port = ext_lcd->if_attr_val1;
- pconf->lcd_control.lvds_config->pn_swap = ext_lcd->if_attr_val2;
- pconf->lcd_control.lvds_config->port_swap = ext_lcd->if_attr_val3;
- pconf->lcd_control.lvds_config->lane_reverse = ext_lcd->if_attr_val4;
- pconf->lcd_control.lvds_config->phy_vswing = LVDS_PHY_VSWING_DFT;
- pconf->lcd_control.lvds_config->phy_preem = LVDS_PHY_PREEM_DFT;
- pconf->lcd_control.lvds_config->phy_clk_vswing = LVDS_PHY_CLK_VSWING_DFT;
- pconf->lcd_control.lvds_config->phy_clk_preem = LVDS_PHY_CLK_PREEM_DFT;
- } else if (pconf->lcd_basic.lcd_type == LCD_MLVDS) {
- pconf->lcd_control.mlvds_config->channel_num = ext_lcd->if_attr_val0;
- pconf->lcd_control.mlvds_config->channel_sel0 = ext_lcd->if_attr_val1;
- pconf->lcd_control.mlvds_config->channel_sel1 = ext_lcd->if_attr_val2;
- pconf->lcd_control.mlvds_config->clk_phase = ext_lcd->if_attr_val3;
- pconf->lcd_control.mlvds_config->pn_swap = ext_lcd->if_attr_val4;
- pconf->lcd_control.mlvds_config->bit_swap = ext_lcd->if_attr_val5;
- pconf->lcd_control.mlvds_config->phy_vswing = LVDS_PHY_VSWING_DFT;
- pconf->lcd_control.mlvds_config->phy_preem = LVDS_PHY_PREEM_DFT;
- } else if (pconf->lcd_basic.lcd_type == LCD_TTL) {
- LCDERR("unsupport lcd_type: %d\n", pconf->lcd_basic.lcd_type);
- }
-
- i = 0;
- while (i < LCD_PWR_STEP_MAX) {
- power_step = &ext_lcd->power_on_step[i];
- if (lcd_debug_print_flag) {
- LCDPR("power_on: step %d: type=%d, index=%d, value=%d, delay=%d\n",
- i, power_step->type, power_step->index,
- power_step->value, power_step->delay);
- }
- pconf->lcd_power->power_on_step[i].type = power_step->type;
- pconf->lcd_power->power_on_step[i].index = power_step->index;
- pconf->lcd_power->power_on_step[i].value = power_step->value;
- pconf->lcd_power->power_on_step[i].delay = power_step->delay;
- if (power_step->type >= LCD_POWER_TYPE_MAX)
- break;
- else
- i++;
- }
-
- i = 0;
- while (i < LCD_PWR_STEP_MAX) {
- power_step = &ext_lcd->power_off_step[i];
- if (lcd_debug_print_flag) {
- LCDPR("power_off: step %d: type=%d, index=%d, value=%d, delay=%d\n",
- i, power_step->type, power_step->index,
- power_step->value, power_step->delay);
- }
- pconf->lcd_power->power_off_step[i].type = power_step->type;
- pconf->lcd_power->power_off_step[i].index = power_step->index;
- pconf->lcd_power->power_off_step[i].value = power_step->value;
- pconf->lcd_power->power_off_step[i].delay = power_step->delay;
- if (power_step->type >= LCD_POWER_TYPE_MAX)
- break;
- else
- i++;
- }
-
- return 0;
-}
-
-static int lcd_config_load_from_unifykey(struct lcd_config_s *pconf)
-{
- unsigned char *para;
- int key_len, len;
- unsigned char *p;
- const char *str;
- struct aml_lcd_unifykey_header_s lcd_header;
- int ret;
- struct lvds_config_s *lvdsconf = pconf->lcd_control.lvds_config;
- struct vbyone_config_s *vx1_conf = pconf->lcd_control.vbyone_config;
- struct mlvds_config_s *mlvds_conf = pconf->lcd_control.mlvds_config;
-
- para = (unsigned char *)malloc(sizeof(unsigned char) * LCD_UKEY_LCD_SIZE);
- if (!para) {
- LCDERR("%s: Not enough memory\n", __func__);
- return -1;
- }
- key_len = LCD_UKEY_LCD_SIZE;
- memset(para, 0, (sizeof(unsigned char) * key_len));
- ret = aml_lcd_unifykey_get("lcd", para, &key_len);
- if (ret) {
- free(para);
- return -1;
- }
-
- /* step 1: check header */
- len = LCD_UKEY_HEAD_SIZE;
- ret = aml_lcd_unifykey_len_check(key_len, len);
- if (ret) {
- LCDERR("unifykey header length is incorrect\n");
- free(para);
- return -1;
- }
-
- aml_lcd_unifykey_header_check(para, &lcd_header);
- LCDPR("unifykey version: 0x%04x\n", lcd_header.version);
- switch (lcd_header.version) {
- case 2:
- len = LCD_UKEY_DATA_LEN_V2; /*10+36+18+31+20+44+10*/
- break;
- default:
- len = LCD_UKEY_DATA_LEN_V1; /*10+36+18+31+20*/
- break;
- }
- if (lcd_debug_print_flag) {
- LCDPR("unifykey header:\n");
- LCDPR("crc32 = 0x%08x\n", lcd_header.crc32);
- LCDPR("data_len = %d\n", lcd_header.data_len);
- LCDPR("reserved = 0x%04x\n", lcd_header.reserved);
- }
-
- /* step 2: check lcd parameters */
- ret = aml_lcd_unifykey_len_check(key_len, len);
- if (ret) {
- LCDERR("unifykey parameters length is incorrect\n");
- free(para);
- return -1;
- }
-
- /* basic: 36byte */
- p = para;
- *(p + LCD_UKEY_MODEL_NAME - 1) = '\0'; /* ensure string ending */
- str = (const char *)(p + LCD_UKEY_HEAD_SIZE);
- strcpy(pconf->lcd_basic.model_name, str);
- pconf->lcd_basic.lcd_type = *(p + LCD_UKEY_INTERFACE);
- pconf->lcd_basic.lcd_bits = *(p + LCD_UKEY_LCD_BITS);
- pconf->lcd_basic.screen_width = (*(p + LCD_UKEY_SCREEN_WIDTH) |
- ((*(p + LCD_UKEY_SCREEN_WIDTH + 1)) << 8));
- pconf->lcd_basic.screen_height = (*(p + LCD_UKEY_SCREEN_HEIGHT) |
- ((*(p + LCD_UKEY_SCREEN_HEIGHT + 1)) << 8));
-
- /* timing: 18byte */
- pconf->lcd_basic.h_active = (*(p + LCD_UKEY_H_ACTIVE) |
- ((*(p + LCD_UKEY_H_ACTIVE + 1)) << 8));
- pconf->lcd_basic.v_active = (*(p + LCD_UKEY_V_ACTIVE)) |
- ((*(p + LCD_UKEY_V_ACTIVE + 1)) << 8);
- pconf->lcd_basic.h_period = (*(p + LCD_UKEY_H_PERIOD)) |
- ((*(p + LCD_UKEY_H_PERIOD + 1)) << 8);
- pconf->lcd_basic.v_period = (*(p + LCD_UKEY_V_PERIOD)) |
- ((*(p + LCD_UKEY_V_PERIOD + 1)) << 8);
- pconf->lcd_timing.hsync_width = (*(p + LCD_UKEY_HS_WIDTH) |
- ((*(p + LCD_UKEY_HS_WIDTH + 1)) << 8));
- pconf->lcd_timing.hsync_bp = (*(p + LCD_UKEY_HS_BP) |
- ((*(p + LCD_UKEY_HS_BP + 1)) << 8));
- pconf->lcd_timing.hsync_pol = *(p + LCD_UKEY_HS_POL);
- pconf->lcd_timing.vsync_width = (*(p + LCD_UKEY_VS_WIDTH) |
- ((*(p + LCD_UKEY_VS_WIDTH + 1)) << 8));
- pconf->lcd_timing.vsync_bp = (*(p + LCD_UKEY_VS_BP) |
- ((*(p + LCD_UKEY_VS_BP + 1)) << 8));
- pconf->lcd_timing.vsync_pol = *(p + LCD_UKEY_VS_POL);
-
- /* customer: 31byte */
- pconf->lcd_timing.fr_adjust_type = *(p + LCD_UKEY_FR_ADJ_TYPE);
- pconf->lcd_timing.ss_level = *(p + LCD_UKEY_SS_LEVEL);
- pconf->lcd_timing.clk_auto = *(p + LCD_UKEY_CLK_AUTO_GEN);
- pconf->lcd_timing.lcd_clk = (*(p + LCD_UKEY_PCLK) |
- ((*(p + LCD_UKEY_PCLK + 1)) << 8) |
- ((*(p + LCD_UKEY_PCLK + 2)) << 16) |
- ((*(p + LCD_UKEY_PCLK + 3)) << 24));
- pconf->lcd_basic.h_period_min = (*(p + LCD_UKEY_H_PERIOD_MIN) |
- ((*(p + LCD_UKEY_H_PERIOD_MIN + 1)) << 8));
- pconf->lcd_basic.h_period_max = (*(p + LCD_UKEY_H_PERIOD_MAX) |
- ((*(p + LCD_UKEY_H_PERIOD_MAX + 1)) << 8));
- pconf->lcd_basic.v_period_min = (*(p + LCD_UKEY_V_PERIOD_MIN) |
- ((*(p + LCD_UKEY_V_PERIOD_MIN + 1)) << 8));
- pconf->lcd_basic.v_period_max = (*(p + LCD_UKEY_V_PERIOD_MAX) |
- ((*(p + LCD_UKEY_V_PERIOD_MAX + 1)) << 8));
- pconf->lcd_basic.lcd_clk_min = (*(p + LCD_UKEY_PCLK_MIN) |
- ((*(p + LCD_UKEY_PCLK_MIN + 1)) << 8) |
- ((*(p + LCD_UKEY_PCLK_MIN + 2)) << 16) |
- ((*(p + LCD_UKEY_PCLK_MIN + 3)) << 24));
- pconf->lcd_basic.lcd_clk_max = (*(p + LCD_UKEY_PCLK_MAX) |
- ((*(p + LCD_UKEY_PCLK_MAX + 1)) << 8) |
- ((*(p + LCD_UKEY_PCLK_MAX + 2)) << 16) |
- ((*(p + LCD_UKEY_PCLK_MAX + 3)) << 24));
-
- /* interface: 20byte */
- if (pconf->lcd_basic.lcd_type == LCD_VBYONE) {
- if (lcd_header.version == 2) {
- vx1_conf->lane_count = (*(p + LCD_UKEY_IF_ATTR_0) |
- ((*(p + LCD_UKEY_IF_ATTR_0 + 1)) << 8)) & 0xff;
- vx1_conf->region_num = (*(p + LCD_UKEY_IF_ATTR_1) |
- ((*(p + LCD_UKEY_IF_ATTR_1 + 1)) << 8)) & 0xff;
- vx1_conf->byte_mode = (*(p + LCD_UKEY_IF_ATTR_2) |
- ((*(p + LCD_UKEY_IF_ATTR_2 + 1)) << 8)) & 0xff;
- vx1_conf->color_fmt = (*(p + LCD_UKEY_IF_ATTR_3) |
- ((*(p + LCD_UKEY_IF_ATTR_3 + 1)) << 8)) & 0xff;
- } else {
- vx1_conf->lane_count = (*(p + LCD_UKEY_IF_ATTR_0) |
- ((*(p + LCD_UKEY_IF_ATTR_0 + 1)) << 8)) & 0xff;
- vx1_conf->region_num = (*(p + LCD_UKEY_IF_ATTR_1) |
- ((*(p + LCD_UKEY_IF_ATTR_1 + 1)) << 8)) & 0xff;
- vx1_conf->byte_mode = (*(p + LCD_UKEY_IF_ATTR_2) |
- ((*(p + LCD_UKEY_IF_ATTR_2 + 1)) << 8)) & 0xff;
- vx1_conf->color_fmt = (*(p + LCD_UKEY_IF_ATTR_3) |
- ((*(p + LCD_UKEY_IF_ATTR_3 + 1)) << 8)) & 0xff;
- vx1_conf->phy_vswing = (*(p + LCD_UKEY_IF_ATTR_4) |
- ((*(p + LCD_UKEY_IF_ATTR_4 + 1)) << 8)) & 0xff;
- vx1_conf->phy_preem = (*(p + LCD_UKEY_IF_ATTR_5) |
- ((*(p + LCD_UKEY_IF_ATTR_5 + 1)) << 8)) & 0xff;
- }
- } else if (pconf->lcd_basic.lcd_type == LCD_LVDS) {
- if (lcd_header.version == 2) {
- lvdsconf->lvds_repack = (*(p + LCD_UKEY_IF_ATTR_0) |
- ((*(p + LCD_UKEY_IF_ATTR_0 + 1)) << 8)) & 0xff;
- lvdsconf->dual_port = (*(p + LCD_UKEY_IF_ATTR_1) |
- ((*(p + LCD_UKEY_IF_ATTR_1 + 1)) << 8)) & 0xff;
- lvdsconf->pn_swap = (*(p + LCD_UKEY_IF_ATTR_2) |
- ((*(p + LCD_UKEY_IF_ATTR_2 + 1)) << 8)) & 0xff;
- lvdsconf->port_swap = (*(p + LCD_UKEY_IF_ATTR_3) |
- ((*(p + LCD_UKEY_IF_ATTR_3 + 1)) << 8)) & 0xff;
- lvdsconf->lane_reverse = (*(p + LCD_UKEY_IF_ATTR_4) |
- ((*(p + LCD_UKEY_IF_ATTR_4 + 1)) << 8)) & 0xff;
- } else {
- lvdsconf->lvds_repack = (*(p + LCD_UKEY_IF_ATTR_0) |
- ((*(p + LCD_UKEY_IF_ATTR_0 + 1)) << 8)) & 0xff;
- lvdsconf->dual_port = (*(p + LCD_UKEY_IF_ATTR_1) |
- ((*(p + LCD_UKEY_IF_ATTR_1 + 1)) << 8)) & 0xff;
- lvdsconf->pn_swap = (*(p + LCD_UKEY_IF_ATTR_2) |
- ((*(p + LCD_UKEY_IF_ATTR_2 + 1)) << 8)) & 0xff;
- lvdsconf->port_swap = (*(p + LCD_UKEY_IF_ATTR_3) |
- ((*(p + LCD_UKEY_IF_ATTR_3 + 1)) << 8)) & 0xff;
- lvdsconf->phy_vswing = (*(p + LCD_UKEY_IF_ATTR_4) |
- ((*(p + LCD_UKEY_IF_ATTR_4 + 1)) << 8)) & 0xff;
- lvdsconf->phy_preem = (*(p + LCD_UKEY_IF_ATTR_5) |
- ((*(p + LCD_UKEY_IF_ATTR_5 + 1)) << 8)) & 0xff;
- lvdsconf->phy_clk_vswing = (*(p + LCD_UKEY_IF_ATTR_6) |
- ((*(p + LCD_UKEY_IF_ATTR_6 + 1)) << 8)) & 0xff;
- lvdsconf->phy_clk_preem = (*(p + LCD_UKEY_IF_ATTR_7) |
- ((*(p + LCD_UKEY_IF_ATTR_7 + 1)) << 8)) & 0xff;
-
- lvdsconf->lane_reverse = 0;
- }
- } else if (pconf->lcd_basic.lcd_type == LCD_MLVDS) {
- if (lcd_header.version == 2) {
- mlvds_conf->channel_num = (*(p + LCD_UKEY_IF_ATTR_0) |
- ((*(p + LCD_UKEY_IF_ATTR_0 + 1)) << 8)) & 0xff;
- mlvds_conf->channel_sel0 = (*(p + LCD_UKEY_IF_ATTR_1) |
- ((*(p + LCD_UKEY_IF_ATTR_1 + 1)) << 8) |
- ((*(p + LCD_UKEY_IF_ATTR_2)) << 16) |
- ((*(p + LCD_UKEY_IF_ATTR_2 + 1)) << 24));
- mlvds_conf->channel_sel1 = (*(p + LCD_UKEY_IF_ATTR_3) |
- ((*(p + LCD_UKEY_IF_ATTR_3 + 1)) << 8) |
- ((*(p + LCD_UKEY_IF_ATTR_4)) << 16) |
- ((*(p + LCD_UKEY_IF_ATTR_4 + 1)) << 24));
- mlvds_conf->clk_phase = (*(p + LCD_UKEY_IF_ATTR_5) |
- ((*(p + LCD_UKEY_IF_ATTR_5 + 1)) << 8)) & 0xff;
- mlvds_conf->pn_swap = (*(p + LCD_UKEY_IF_ATTR_6) |
- ((*(p + LCD_UKEY_IF_ATTR_6 + 1)) << 8)) & 0xff;
- mlvds_conf->bit_swap = (*(p + LCD_UKEY_IF_ATTR_7) |
- ((*(p + LCD_UKEY_IF_ATTR_7 + 1)) << 8)) & 0xff;
- } else if (lcd_header.version == 1) {
- mlvds_conf->channel_num = (*(p + LCD_UKEY_IF_ATTR_0) |
- ((*(p + LCD_UKEY_IF_ATTR_0 + 1)) << 8)) & 0xff;
- mlvds_conf->channel_sel0 = (*(p + LCD_UKEY_IF_ATTR_1) |
- ((*(p + LCD_UKEY_IF_ATTR_1 + 1)) << 8) |
- ((*(p + LCD_UKEY_IF_ATTR_2)) << 16) |
- ((*(p + LCD_UKEY_IF_ATTR_2 + 1)) << 24));
- mlvds_conf->channel_sel1 = (*(p + LCD_UKEY_IF_ATTR_3) |
- ((*(p + LCD_UKEY_IF_ATTR_3 + 1)) << 8) |
- ((*(p + LCD_UKEY_IF_ATTR_4)) << 16) |
- ((*(p + LCD_UKEY_IF_ATTR_4 + 1)) << 24));
- mlvds_conf->clk_phase = (*(p + LCD_UKEY_IF_ATTR_5) |
- ((*(p + LCD_UKEY_IF_ATTR_5 + 1)) << 8)) & 0xff;
- mlvds_conf->pn_swap = (*(p + LCD_UKEY_IF_ATTR_6) |
- ((*(p + LCD_UKEY_IF_ATTR_6 + 1)) << 8)) & 0xff;
- mlvds_conf->bit_swap = (*(p + LCD_UKEY_IF_ATTR_7) |
- ((*(p + LCD_UKEY_IF_ATTR_7 + 1)) << 8)) & 0xff;
- mlvds_conf->phy_vswing = (*(p + LCD_UKEY_IF_ATTR_8) |
- ((*(p + LCD_UKEY_IF_ATTR_8 + 1)) << 8)) & 0xff;
- mlvds_conf->phy_preem = (*(p + LCD_UKEY_IF_ATTR_9) |
- ((*(p + LCD_UKEY_IF_ATTR_9 + 1)) << 8)) & 0xff;
- }
- } else
- LCDERR("unsupport lcd_type: %d\n", pconf->lcd_basic.lcd_type);
-
- if (lcd_header.version == 2) {
- /* ctrl: 44byte */ /* v2 */
- if (pconf->lcd_basic.lcd_type == LCD_VBYONE) {
- vx1_conf->ctrl_flag = (*(p + LCD_UKEY_CTRL_FLAG) |
- ((*(p + LCD_UKEY_CTRL_FLAG + 1)) << 8) |
- ((*(p + LCD_UKEY_CTRL_FLAG + 2)) << 16) |
- ((*(p + LCD_UKEY_CTRL_FLAG + 3)) << 24));
- vx1_conf->power_on_reset_delay = (*(p + LCD_UKEY_CTRL_ATTR_0) |
- ((*(p + LCD_UKEY_CTRL_ATTR_0 + 1)) << 8));
- vx1_conf->hpd_data_delay = (*(p + LCD_UKEY_CTRL_ATTR_1) |
- ((*(p + LCD_UKEY_CTRL_ATTR_1 + 1)) << 8));
- vx1_conf->cdr_training_hold = (*(p + LCD_UKEY_CTRL_ATTR_2) |
- ((*(p + LCD_UKEY_CTRL_ATTR_2 + 1)) << 8));
-
- vx1_conf->vx1_sw_filter_en = (vx1_conf->ctrl_flag >> 4) & 0x3;
- vx1_conf->vx1_sw_filter_time = (*(p + LCD_UKEY_CTRL_ATTR_7) |
- ((*(p + LCD_UKEY_CTRL_ATTR_7 + 1)) << 8)) & 0xff;
- vx1_conf->vx1_sw_filter_cnt = (*(p + LCD_UKEY_CTRL_ATTR_8) |
- ((*(p + LCD_UKEY_CTRL_ATTR_8 + 1)) << 8)) & 0xff;
- vx1_conf->vx1_sw_filter_retry_cnt = (*(p + LCD_UKEY_CTRL_ATTR_9) |
- ((*(p + LCD_UKEY_CTRL_ATTR_9 + 1)) << 8)) & 0xff;
- vx1_conf->vx1_sw_filter_retry_delay = (*(p + LCD_UKEY_CTRL_ATTR_10) |
- ((*(p + LCD_UKEY_CTRL_ATTR_10 + 1)) << 8)) & 0xff;
- vx1_conf->vx1_sw_cdr_detect_time = (*(p + LCD_UKEY_CTRL_ATTR_11) |
- ((*(p + LCD_UKEY_CTRL_ATTR_11 + 1)) << 8)) & 0xff;
- vx1_conf->vx1_sw_cdr_detect_cnt = (*(p + LCD_UKEY_CTRL_ATTR_12) |
- ((*(p + LCD_UKEY_CTRL_ATTR_12 + 1)) << 8)) & 0xff;
- vx1_conf->vx1_sw_cdr_timeout_cnt = (*(p + LCD_UKEY_CTRL_ATTR_13) |
- ((*(p + LCD_UKEY_CTRL_ATTR_13 + 1)) << 8)) & 0xff;
- }
-
- /* phy: 10byte */ /* v2 */
- if (pconf->lcd_basic.lcd_type == LCD_VBYONE) {
- vx1_conf->phy_vswing = *(p + LCD_UKEY_PHY_ATTR_0);
- vx1_conf->phy_preem = *(p + LCD_UKEY_PHY_ATTR_1);
- } else if (pconf->lcd_basic.lcd_type == LCD_LVDS) {
- lvdsconf->phy_vswing = *(p + LCD_UKEY_PHY_ATTR_0);
- lvdsconf->phy_preem = *(p + LCD_UKEY_PHY_ATTR_1);
- lvdsconf->phy_clk_vswing = *(p + LCD_UKEY_PHY_ATTR_2);
- lvdsconf->phy_clk_preem = *(p + LCD_UKEY_PHY_ATTR_3);
- } else if (pconf->lcd_basic.lcd_type == LCD_MLVDS) {
- mlvds_conf->phy_vswing = *(p + LCD_UKEY_PHY_ATTR_0);
- mlvds_conf->phy_preem = *(p + LCD_UKEY_PHY_ATTR_1);
- }
- } else if (lcd_header.version == 1) {
- if (pconf->lcd_basic.lcd_type == LCD_VBYONE) {
- vx1_conf->ctrl_flag = 0;
- vx1_conf->power_on_reset_delay = VX1_PWR_ON_RESET_DLY_DFT;
- vx1_conf->hpd_data_delay = VX1_HPD_DATA_DELAY_DFT;
- vx1_conf->cdr_training_hold = VX1_CDR_TRAINING_HOLD_DFT;
- vx1_conf->vx1_sw_filter_en = 0;
- vx1_conf->vx1_sw_filter_time = VX1_SW_FILTER_TIME_DFT;
- vx1_conf->vx1_sw_filter_cnt = VX1_SW_FILTER_CNT_DFT;
- vx1_conf->vx1_sw_filter_retry_cnt = VX1_SW_FILTER_RETRY_CNT_DFT;
- vx1_conf->vx1_sw_filter_retry_delay = VX1_SW_FILTER_RETRY_DLY_DFT;
- vx1_conf->vx1_sw_cdr_detect_time = VX1_SW_CDR_DET_TIME_DFT;
- vx1_conf->vx1_sw_cdr_detect_cnt = VX1_SW_CDR_DET_CNT_DFT;
- vx1_conf->vx1_sw_cdr_timeout_cnt = VX1_SW_CDR_TIMEOUT_CNT_DFT;
- }
- }
-
- /* step 3: check power sequence */
- ret = lcd_power_load_from_unifykey(pconf, para, key_len, len);
- if (ret < 0) {
- free(para);
- return -1;
- }
-
- free(para);
- return 0;
-}
-
-static void lcd_config_init(struct lcd_config_s *pconf)
-{
+ struct lcd_config_s *pconf = &pdrv->config;
unsigned int clk;
- if (pconf->lcd_timing.lcd_clk == 0) /* default 0 for 60hz */
- pconf->lcd_timing.lcd_clk = 60;
- else
- LCDPR("custome clk: %d\n", pconf->lcd_timing.lcd_clk);
- clk = pconf->lcd_timing.lcd_clk;
+ if (pconf->timing.lcd_clk == 0) {/* default 0 for 60hz */
+ pconf->timing.lcd_clk = 60;
+ } else {
+ LCDPR("[%d]: custome clk: %d\n",
+ pdrv->index, pconf->timing.lcd_clk);
+ }
+ clk = pconf->timing.lcd_clk;
if (clk < 200) { /* regard as frame_rate */
- pconf->lcd_timing.lcd_clk = clk * pconf->lcd_basic.h_period *
- pconf->lcd_basic.v_period;
+ pconf->timing.lcd_clk = clk * pconf->basic.h_period *
+ pconf->basic.v_period;
} else /* regard as pixel clock */
- pconf->lcd_timing.lcd_clk = clk;
- pconf->lcd_timing.lcd_clk_dft = pconf->lcd_timing.lcd_clk;
- pconf->lcd_timing.h_period_dft = pconf->lcd_basic.h_period;
- pconf->lcd_timing.v_period_dft = pconf->lcd_basic.v_period;
- pconf->lcd_timing.sync_duration_num = ((pconf->lcd_timing.lcd_clk / pconf->lcd_basic.h_period) * 100) / pconf->lcd_basic.v_period;
- pconf->lcd_timing.sync_duration_den = 100;
+ pconf->timing.lcd_clk = clk;
+ pconf->timing.lcd_clk_dft = pconf->timing.lcd_clk;
+ pconf->timing.h_period_dft = pconf->basic.h_period;
+ pconf->timing.v_period_dft = pconf->basic.v_period;
+ pconf->timing.sync_duration_num =
+ ((pconf->timing.lcd_clk / pconf->basic.h_period) * 100) /
+ pconf->basic.v_period;
+ pconf->timing.sync_duration_den = 100;
lcd_timing_init_config(pconf);
}
-static int lcd_outputmode_check(char *mode)
+static int lcd_outputmode_check(struct aml_lcd_drv_s *pdrv, char *mode, unsigned int frac)
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
int lcd_vmode;
- lcd_vmode = check_lcd_output_mode(lcd_drv->lcd_config, mode);
+ lcd_vmode = check_lcd_output_mode(pdrv, mode, frac);
if (lcd_vmode >= LCD_VMODE_MAX)
return -1;
return 0;
}
-static int lcd_config_check(char *mode)
+static int lcd_config_check(struct aml_lcd_drv_s *pdrv, char *mode, unsigned int frac)
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
+ struct lcd_config_s *pconf = &pdrv->config;
int lcd_vmode;
- lcd_vmode = check_lcd_output_mode(lcd_drv->lcd_config, mode);
+ lcd_vmode = check_lcd_output_mode(pdrv, mode, frac);
if (lcd_vmode >= LCD_VMODE_MAX)
return -1;
- lcd_drv->lcd_config->lcd_timing.sync_duration_num = lcd_vmode_info[lcd_vmode].frame_rate;
- lcd_drv->lcd_config->lcd_timing.sync_duration_den = 1;
- /* update clk & timing config */
- lcd_vmode_change(lcd_drv->lcd_config);
- lcd_tv_config_update(lcd_drv->lcd_config);
- lcd_clk_generate_parameter(lcd_drv->lcd_config);
-
- return 0;
-}
-
-int get_lcd_tv_config(const void *dt_blob, int load_id)
-{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- int ret = 0;
-
- strcpy(lcd_drv->version, LCD_DRV_VERSION);
- lcd_drv->list_support_mode = lcd_list_support_mode;
- lcd_drv->outputmode_check = lcd_outputmode_check;
- lcd_drv->config_check = lcd_config_check;
- lcd_drv->driver_init_pre = lcd_tv_driver_init_pre;
- lcd_drv->driver_init = lcd_tv_driver_init;
- lcd_drv->driver_disable = lcd_tv_driver_disable;
-
- if (load_id & 0x10) { /* unifykey */
- ret = lcd_config_load_from_unifykey(lcd_drv->lcd_config);
- ret = lcd_pinmux_load_config(dt_blob, lcd_drv->lcd_config);
- } else if (load_id & 0x1) { /* dts */
- ret = lcd_config_load_from_dts(dt_blob, lcd_drv->lcd_config);
- ret = lcd_pinmux_load_config(dt_blob, lcd_drv->lcd_config);
- } else { /* bsp */
- ret = lcd_config_load_from_bsp(lcd_drv->lcd_config);
+ if (lcd_vmode_info[lcd_vmode].frac) {
+ pconf->timing.sync_duration_num = 5994;
+ pconf->timing.sync_duration_den = 100;
+ } else {
+ pconf->timing.sync_duration_num = lcd_vmode_info[lcd_vmode].frame_rate;
+ pconf->timing.sync_duration_den = 1;
}
- if (ret)
- return -1;
+ /* update clk & timing config */
+ lcd_vmode_change(pconf);
+ lcd_tv_config_update(pdrv);
+ lcd_clk_generate_parameter(pdrv);
- lcd_config_load_print(lcd_drv->lcd_config);
- lcd_config_init(lcd_drv->lcd_config);
+ return 0;
+}
+
+int lcd_mode_tv_init(struct aml_lcd_drv_s *pdrv)
+{
+ pdrv->list_support_mode = lcd_list_support_mode;
+ pdrv->outputmode_check = lcd_outputmode_check;
+ pdrv->config_check = lcd_config_check;
+ pdrv->driver_init_pre = lcd_tv_driver_init_pre;
+ pdrv->driver_init = lcd_tv_driver_init;
+ pdrv->driver_disable = lcd_tv_driver_disable;
+
+ lcd_config_init(pdrv);
return 0;
}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.h b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.h
index b8b42bf..2349cb4 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.h
+++ b/drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.h
@@ -1,27 +1,11 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/vout/lcd/lcd_tv/lcd_tv.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __AML_LCD_TV_H__
#define __AML_LCD_TV_H__
-#include <amlogic/media/vout/lcd/aml_lcd.h>
+#include <amlogic/media/vout/lcd/lcd_vout.h>
//**********************************
//lcd driver version
@@ -30,9 +14,9 @@
//**********************************
-extern void lcd_tv_config_update(struct lcd_config_s *pconf);
-extern void lcd_tv_driver_init_pre(void);
-extern int lcd_tv_driver_init(void);
-extern void lcd_tv_driver_disable(void);
+void lcd_tv_config_update(struct aml_lcd_drv_s *pdrv);
+void lcd_tv_driver_init_pre(struct aml_lcd_drv_s *pdrv);
+int lcd_tv_driver_init(struct aml_lcd_drv_s *pdrv);
+void lcd_tv_driver_disable(struct aml_lcd_drv_s *pdrv);
#endif
diff --git a/drivers/amlogic/media/vout/lcd/lcd_unifykey.c b/drivers/amlogic/media/vout/lcd/lcd_unifykey.c
index e5fbd77..48b8b0e 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_unifykey.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_unifykey.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_unifykey.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -26,16 +11,13 @@
#include <amlogic/media/vout/lcd/aml_lcd.h>
#include "lcd_reg.h"
#include "lcd_common.h"
-#ifdef CONFIG_UNIFY_KEY_MANAGE
-#include "lcd_tcon_ref.h"
-#endif
#define LCD_UNIFYKEY_TEST
#define LCDUKEY(fmt, args...) printf("lcd ukey: "fmt"", ## args)
#define LCDUKEYERR(fmt, args...) printf("lcd ukey err: "fmt"", ## args)
#ifdef CONFIG_UNIFY_KEY_MANAGE
-int aml_lcd_unifykey_len_check(int key_len, int len)
+int lcd_unifykey_len_check(int key_len, int len)
{
if (key_len < len) {
LCDUKEYERR("invalid unifykey length %d, need %d\n", key_len, len);
@@ -44,7 +26,8 @@
return 0;
}
-int aml_lcd_unifykey_header_check(unsigned char *buf, struct aml_lcd_unifykey_header_s *header)
+int lcd_unifykey_header_check(unsigned char *buf,
+ struct lcd_unifykey_header_s *header)
{
header->crc32 = (buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24));
header->data_len = (buf[4] | (buf[5] << 8));
@@ -54,12 +37,37 @@
return 0;
}
-int aml_lcd_unifykey_check(const char *key_name)
+int lcd_unifykey_check_exist(const char *key_name)
+{
+ int key_exist = 0;
+ int ret;
+
+ if (!key_name) {
+ LCDUKEYERR("%s: key_name is null\n", __func__);
+ return -1;
+ }
+
+ ret = key_unify_query_exist(key_name, &key_exist);
+ if (ret) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDUKEYERR("%s query exist error\n", key_name);
+ return -1;
+ }
+ if (key_exist == 0) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDUKEYERR("%s is not exist\n", key_name);
+ return -1;
+ }
+
+ return 0;
+}
+
+int lcd_unifykey_check(const char *key_name)
{
ssize_t key_size;
int key_exist, isSecure, key_len;
unsigned char *buf;
- struct aml_lcd_unifykey_header_s key_header;
+ struct lcd_unifykey_header_s key_header;
int retry_cnt = 0;
uint32_t key_crc;
unsigned int key_crc32;
@@ -69,12 +77,12 @@
key_exist = 0;
ret = key_unify_query_exist(key_name, &key_exist);
if (ret) {
- if (lcd_debug_print_flag)
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
LCDUKEYERR("%s query exist error\n", key_name);
return -1;
}
if (key_exist == 0) {
- if (lcd_debug_print_flag)
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
LCDUKEYERR("%s is not exist\n", key_name);
return -1;
}
@@ -94,11 +102,11 @@
}
key_len = (int)key_size;
if (key_len == 0) {
- if (lcd_debug_print_flag)
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
LCDUKEY("%s size is zero\n", key_name);
return -1;
}
- if (lcd_debug_print_flag)
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
LCDUKEY("%s size: %d\n", key_name, key_len);
lcd_unifykey_read:
@@ -118,14 +126,15 @@
LCDUKEYERR("%s unify key_len %d error\n", key_name, key_len);
return -1;
}
- aml_lcd_unifykey_header_check(buf, &key_header);
+ lcd_unifykey_header_check(buf, &key_header);
if (key_len != key_header.data_len) { //length check
- if (lcd_debug_print_flag) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
LCDUKEYERR("data_len %d is not match key_len %d\n",
key_header.data_len, key_len);
}
if (retry_cnt < LCD_UKEY_RETRY_CNT_MAX) {
retry_cnt++;
+ memset(buf, 0, key_len);
goto lcd_unifykey_read;
} else {
LCDUKEYERR("%s: load unifykey failed\n", key_name);
@@ -135,12 +144,13 @@
key_crc = crc32(0, &buf[4], (key_len - 4)); //except crc32
key_crc32 = (unsigned int)key_crc;
if (key_crc32 != key_header.crc32) { //crc32 check
- if (lcd_debug_print_flag) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
LCDUKEYERR("crc32 0x%08x is not match 0x%08x\n",
key_header.crc32, key_crc32);
}
if (retry_cnt < LCD_UKEY_RETRY_CNT_MAX) {
retry_cnt++;
+ memset(buf, 0, key_len);
goto lcd_unifykey_read;
} else {
LCDUKEYERR("%s: load unifykey failed\n", key_name);
@@ -148,17 +158,128 @@
}
}
+ free(buf);
return 0;
}
-int aml_lcd_unifykey_get(const char *key_name, unsigned char *buf, int *len)
+#ifdef CONFIG_AML_LCD_TCON
+static int lcd_unifykey_check_tcon(const char *key_name)
+{
+ ssize_t key_size;
+ int key_exist, is_secure, key_len, data_size;
+ unsigned char *buf;
+ int retry_cnt = 0;
+ unsigned int key_crc;
+ unsigned int key_crc32, raw_crc32;
+ int ret;
+
+ key_size = 0;
+ key_exist = 0;
+ ret = key_unify_query_exist(key_name, &key_exist);
+ if (ret) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDUKEYERR("%s query exist error\n", key_name);
+ return -1;
+ }
+ if (key_exist == 0) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDUKEYERR("%s is not exist\n", key_name);
+ return -1;
+ }
+ ret = key_unify_query_secure(key_name, &is_secure);
+ if (ret) {
+ LCDUKEYERR("%s query secure error\n", key_name);
+ return -1;
+ }
+ if (is_secure) {
+ LCDUKEYERR("%s is secure key\n", key_name);
+ return -1;
+ }
+ ret = key_unify_query_size(key_name, &key_size);
+ if (ret) {
+ LCDUKEYERR("%s query size error\n", key_name);
+ return -1;
+ }
+ key_len = (int)key_size;
+ if (key_len == 0) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDUKEY("%s size is zero\n", key_name);
+ return -1;
+ }
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDUKEY("%s size: %d\n", key_name, key_len);
+
+ buf = (unsigned char *)malloc(sizeof(unsigned char) * key_len);
+ if (!buf) {
+ LCDERR("%s: Not enough memory\n", __func__);
+ return -1;
+ }
+
+lcd_unifykey_tcon_read:
+ ret = key_unify_read(key_name, buf, key_len);
+ if (ret) {
+ LCDUKEYERR("%s unify read error\n", key_name);
+ goto lcd_unifykey_tcon_err;
+ }
+
+ /* check header */
+ if (key_len <= LCD_TCON_DATA_BLOCK_HEADER_SIZE) {
+ LCDUKEYERR("%s unify key_len %d error\n", key_name, key_len);
+ goto lcd_unifykey_tcon_err;
+ }
+ data_size = (buf[8] | (buf[9] << 8) |
+ (buf[10] << 16) | (buf[11] << 24));
+ if (key_len != data_size) { //length check
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDUKEYERR("data_len %d is not match key_len %d\n",
+ data_size, key_len);
+ }
+ if (retry_cnt < LCD_UKEY_RETRY_CNT_MAX) {
+ retry_cnt++;
+ memset(buf, 0, key_len);
+ goto lcd_unifykey_tcon_read;
+ }
+ LCDUKEYERR("%s: load unifykey failed\n", key_name);
+ goto lcd_unifykey_tcon_err;
+ }
+ raw_crc32 = (buf[0] | (buf[1] << 8) | (buf[2] << 16) | (buf[3] << 24));
+ key_crc = crc32(0, &buf[4], (key_len - 4)); //except crc32
+ key_crc32 = (unsigned int)key_crc;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDUKEY("crc32: 0x%08x, header_crc32: 0x%08x\n",
+ key_crc32, raw_crc32);
+ }
+ if (key_crc32 != raw_crc32) { //crc32 check
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDUKEYERR("crc32 0x%08x is not match 0x%08x\n",
+ raw_crc32, key_crc32);
+ }
+ if (retry_cnt < LCD_UKEY_RETRY_CNT_MAX) {
+ retry_cnt++;
+ memset(buf, 0, key_len);
+ goto lcd_unifykey_tcon_read;
+ }
+ LCDUKEYERR("%s: load unifykey failed\n", key_name);
+ goto lcd_unifykey_tcon_err;
+ }
+
+ free(buf);
+ return 0;
+
+lcd_unifykey_tcon_err:
+ free(buf);
+ return -1;
+}
+#endif
+
+int lcd_unifykey_get(const char *key_name, unsigned char *buf, int *len)
{
ssize_t key_size;
int key_len;
int ret;
key_size = 0;
- ret = aml_lcd_unifykey_check(key_name);
+ ret = lcd_unifykey_check(key_name);
if (ret)
return -1;
ret = key_unify_query_size(key_name, &key_size);
@@ -178,7 +299,39 @@
return 0;
}
-int aml_lcd_unifykey_check_no_header(const char *key_name)
+int lcd_unifykey_get_tcon(const char *key_name, unsigned char *buf, int *len)
+{
+#ifdef CONFIG_AML_LCD_TCON
+ ssize_t key_size;
+ int key_len;
+ int ret;
+
+ key_size = 0;
+ ret = lcd_unifykey_check_tcon(key_name);
+ if (ret)
+ return -1;
+ ret = key_unify_query_size(key_name, &key_size);
+ key_len = (int)key_size;
+ if (key_len > *len) {
+ LCDUKEYERR("%s size(0x%x) is bigger than buf_size(0x%x)\n",
+ key_name, key_len, *len);
+ return -1;
+ }
+ *len = key_len;
+
+ ret = key_unify_read(key_name, buf, key_len);
+ if (ret) {
+ LCDUKEYERR("%s unify read error\n", key_name);
+ return -1;
+ }
+ return 0;
+#else
+ LCDUKEYERR("Don't support tcon\n");
+ return -1;
+#endif
+}
+
+int lcd_unifykey_check_no_header(const char *key_name)
{
ssize_t key_size;
int key_exist, isSecure, key_len;
@@ -188,12 +341,12 @@
key_exist = 0;
ret = key_unify_query_exist(key_name, &key_exist);
if (ret) {
- if (lcd_debug_print_flag)
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
LCDUKEYERR("%s query exist error\n", key_name);
return -1;
}
if (key_exist == 0) {
- if (lcd_debug_print_flag)
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
LCDUKEYERR("%s is not exist\n", key_name);
return -1;
}
@@ -213,24 +366,25 @@
}
key_len = (int)key_size;
if (key_len == 0) {
- if (lcd_debug_print_flag)
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
LCDUKEY("%s size is zero\n", key_name);
return -1;
}
- if (lcd_debug_print_flag)
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
LCDUKEY("%s size: %d\n", key_name, key_len);
return 0;
}
-int aml_lcd_unifykey_get_no_header(const char *key_name, unsigned char *buf, int *len)
+int lcd_unifykey_get_no_header(const char *key_name, unsigned char *buf,
+ int *len)
{
ssize_t key_size;
int key_len;
int ret;
key_size = 0;
- ret = aml_lcd_unifykey_check_no_header(key_name);
+ ret = lcd_unifykey_check_no_header(key_name);
if (ret)
return -1;
ret = key_unify_query_size(key_name, &key_size);
@@ -250,8 +404,14 @@
return 0;
}
+int lcd_unifykey_write(const char *key_name, unsigned char *buf, int len)
+{
+ key_unify_write(key_name, buf, len);
+ return 0;
+}
+
#ifdef LCD_UNIFYKEY_TEST
-static void aml_lcd_test_unifykey(void)
+static void lcd_test_unifykey(void)
{
int len;
unsigned char buf[204];
@@ -476,7 +636,7 @@
key_unify_write("lcd", buf, len);
}
-static void aml_lcd_extern_test_unifykey(void)
+static void lcd_extern_test_unifykey(void)
{
int len;
unsigned char buf[99];
@@ -620,7 +780,7 @@
key_unify_write("lcd_extern", buf, len);
}
-static void aml_bl_test_unifykey(void)
+static void bl_test_unifykey(void)
{
int len;
unsigned char buf[102];
@@ -748,43 +908,15 @@
key_unify_write("backlight", buf, len);
}
-
-static void aml_lcd_tcon_test_unifykey(int n)
-{
- int len;
- unsigned char *buf;
-
- switch (n) {
- case 768:
- buf = &tcon_boe_hd_hsd_n56_1366x768[0];
- len = sizeof(tcon_boe_hd_hsd_n56_1366x768);
- break;
- case 1080:
- buf = &tcon_boe_fhd_goa_n10_1920x1080[0];
- len = sizeof(tcon_boe_fhd_goa_n10_1920x1080);
- break;
- case 2160:
- buf = &uhd_tcon_setting_ceds_3840x2160[0];
- len = sizeof(uhd_tcon_setting_ceds_3840x2160);
- default:
- buf = NULL;
- break;
- }
-
- if (buf)
- key_unify_write("lcd_tcon", buf, len);
- else
- LCDUKEYERR("tcon_test error data\n");
-}
#endif
-void aml_lcd_unifykey_test(void)
+void lcd_unifykey_test(void)
{
#ifdef LCD_UNIFYKEY_TEST
LCDUKEY("Be Careful!! This test will overwrite lcd unifykeys!!\n");
- aml_lcd_test_unifykey();
- aml_lcd_extern_test_unifykey();
- aml_bl_test_unifykey();
+ lcd_test_unifykey();
+ lcd_extern_test_unifykey();
+ bl_test_unifykey();
#else
LCDUKEY("default bypass for lcd unifykey test\n");
LCDUKEY("should enable macro definition: LCD_UNIFYKEY_TEST\n");
@@ -792,24 +924,24 @@
#endif
}
-void aml_lcd_unifykey_tcon_test(int n)
-{
-#ifdef LCD_UNIFYKEY_TEST
- LCDUKEY("Be Careful!! This test will overwrite lcd_tcon unifykeys!!\n");
- aml_lcd_tcon_test_unifykey(n);
-#else
- LCDUKEY("default bypass for lcd unifykey test\n");
- LCDUKEY("should enable macro definition: LCD_UNIFYKEY_TEST\n");
- LCDUKEY("Be Careful!! This test will overwrite lcd unifykeys!!\n");
-#endif
-}
-
-void aml_lcd_unifykey_dump(int flag)
+void lcd_unifykey_dump(int index, unsigned int flag)
{
unsigned char *para;
int key_len;
+ char str[20];
+#ifdef CONFIG_AML_LCD_TCON
+ int tcon_len;
+#endif
int ret, i;
+#ifdef CONFIG_AML_LCD_TCON
+ if ((flag & LCD_UKEY_DEBUG_NORMAL) == 0)
+ goto lcd_unifykey_dump_tcon;
+#else
+ if ((flag & LCD_UKEY_DEBUG_NORMAL) == 0)
+ return;
+#endif
+
/* dump unifykey: lcd */
para = (unsigned char *)malloc(sizeof(unsigned char) * LCD_UKEY_LCD_SIZE);
if (!para) {
@@ -818,9 +950,13 @@
}
key_len = LCD_UKEY_LCD_SIZE;
memset(para, 0, (sizeof(unsigned char) * key_len));
- ret = aml_lcd_unifykey_get("lcd", para, &key_len);
+ if (index > 0)
+ sprintf(str, "lcd%d", index);
+ else
+ sprintf(str, "lcd");
+ ret = lcd_unifykey_get(str, para, &key_len);
if (ret == 0) {
- printf("unifykey: lcd:");
+ printf("unifykey: %s:", str);
for (i = 0; i < key_len; i++) {
if ((i % 16) == 0)
printf("\n%03x0:", (i / 16));
@@ -838,9 +974,13 @@
}
key_len = LCD_UKEY_LCD_EXT_SIZE;
memset(para, 0, (sizeof(unsigned char) * key_len));
- ret = aml_lcd_unifykey_get("lcd_extern", para, &key_len);
+ if (index > 0)
+ sprintf(str, "lcd%d_extern", index);
+ else
+ sprintf(str, "lcd_extern");
+ ret = lcd_unifykey_get(str, para, &key_len);
if (ret == 0) {
- printf("unifykey: lcd_extern:");
+ printf("unifykey: %s:", str);
for (i = 0; i < key_len; i++) {
if ((i % 16) == 0)
printf("\n%03x0:", (i / 16));
@@ -858,9 +998,13 @@
}
key_len = LCD_UKEY_BL_SIZE;
memset(para, 0, (sizeof(unsigned char) * key_len));
- ret = aml_lcd_unifykey_get("backlight", para, &key_len);
+ if (index > 0)
+ sprintf(str, "backlight%d", index);
+ else
+ sprintf(str, "backlight");
+ ret = lcd_unifykey_get(str, para, &key_len);
if (ret == 0) {
- printf("unifykey: backlight:");
+ printf("unifykey: %s:", str);
for (i = 0; i < key_len; i++) {
if ((i % 16) == 0)
printf("\n%03x0:", (i / 16));
@@ -869,20 +1013,28 @@
}
printf("\n");
free(para);
+ return;
+#ifdef CONFIG_AML_LCD_TCON
+lcd_unifykey_dump_tcon:
if ((flag & LCD_UKEY_DEBUG_TCON) == 0)
return;
+ tcon_len = flag & LCD_UKEY_DEBUG_TCON_LEN_MASK;
/* dump unifykey: lcd_tcon */
- para = (unsigned char *)malloc(sizeof(unsigned char) * LCD_UKEY_TCON_SIZE);
+ para = (unsigned char *)malloc(sizeof(unsigned char) * tcon_len);
if (!para) {
LCDUKEYERR("%s: Not enough memory\n", __func__);
return;
}
- key_len = LCD_UKEY_TCON_SIZE;
+ key_len = tcon_len;
memset(para, 0, (sizeof(unsigned char) * key_len));
- ret = aml_lcd_unifykey_get_no_header("lcd_tcon", para, &key_len);
+ if (index > 0)
+ sprintf(str, "lcd%d_tcon", index);
+ else
+ sprintf(str, "lcd_tcon");
+ ret = lcd_unifykey_get_no_header(str, para, &key_len);
if (ret == 0) {
- printf("unifykey: lcd_tcon:");
+ printf("unifykey: %s:", str);
for (i = 0; i < key_len; i++) {
if ((i % 16) == 0)
printf("\n%03x0:", (i / 16));
@@ -891,57 +1043,92 @@
}
printf("\n");
free(para);
+
+ /* dump unifykey: lcd_tcon */
+ para = (unsigned char *)malloc
+ (sizeof(unsigned char) * LCD_UKEY_TCON_SPI_SIZE);
+ if (!para) {
+ LCDUKEYERR("%s: Not enough memory\n", __func__);
+ return;
+ }
+ key_len = LCD_UKEY_TCON_SPI_SIZE;
+ memset(para, 0, (sizeof(unsigned char) * key_len));
+ if (index > 0)
+ sprintf(str, "lcd%d_tcon_spi", index);
+ else
+ sprintf(str, "lcd_tcon_spi");
+ ret = lcd_unifykey_get(str, para, &key_len);
+ if (ret == 0) {
+ printf("unifykey: %s:", str);
+ for (i = 0; i < key_len; i++) {
+ if ((i % 16) == 0)
+ printf("\n%03x0:", (i / 16));
+ printf(" %02x", para[i]);
+ }
+ }
+ printf("\n");
+ free(para);
+#endif
}
#else
/* dummy driver */
-int aml_lcd_unifykey_len_check(int key_len, int len)
+int lcd_unifykey_len_check(int key_len, int len)
{
LCDUKEYERR("Don't support unifykey\n");
return -1;
}
-int aml_lcd_unifykey_header_check(unsigned char *buf, struct aml_lcd_unifykey_header_s *header)
+int lcd_unifykey_header_check(unsigned char *buf,
+ struct lcd_unifykey_header_s *header)
{
LCDUKEYERR("Don't support unifykey\n");
return -1;
}
-int aml_lcd_unifykey_check(const char *key_name)
+int lcd_unifykey_check(const char *key_name)
{
LCDUKEYERR("Don't support unifykey\n");
return -1;
}
-int aml_lcd_unifykey_get(const char *key_name, unsigned char *buf, int *len)
+int lcd_unifykey_get(const char *key_name, unsigned char *buf, int *len)
{
LCDUKEYERR("Don't support unifykey\n");
return -1;
}
-int aml_lcd_unifykey_check_no_header(const char *key_name)
+int lcd_unifykey_get_tcon(const char *key_name, unsigned char *buf, int *len)
{
LCDUKEYERR("Don't support unifykey\n");
return -1;
}
-int aml_lcd_unifykey_get_no_header(const char *key_name, unsigned char *buf, int *len)
+int lcd_unifykey_check_no_header(const char *key_name)
{
LCDUKEYERR("Don't support unifykey\n");
return -1;
}
-void aml_lcd_unifykey_test(void)
+int lcd_unifykey_get_no_header(const char *key_name, unsigned char *buf,
+ int *len)
+{
+ LCDUKEYERR("Don't support unifykey\n");
+ return -1;
+}
+
+int lcd_unifykey_write(const char *key_name, unsigned char *buf, int len)
+{
+ LCDUKEYERR("Don't support unifykey\n");
+ return -1;
+}
+
+void lcd_unifykey_test(void)
{
LCDUKEYERR("Don't support unifykey\n");
}
-void aml_lcd_unifykey_tcon_test(int n)
-{
- LCDUKEYERR("Don't support unifykey\n");
-}
-
-void aml_lcd_unifykey_dump(int flag)
+void lcd_unifykey_dump(int index, unsigned int flag)
{
LCDUKEYERR("Don't support unifykey\n");
}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_unifykey.h b/drivers/amlogic/media/vout/lcd/lcd_unifykey.h
index 9527ff4..9630688 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_unifykey.h
+++ b/drivers/amlogic/media/vout/lcd/lcd_unifykey.h
@@ -1,22 +1,6 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * drivers/amlogic/media/vout/lcd/lcd_unifykey.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __AML_LCD_UNIFYKEY_H__
@@ -38,7 +22,7 @@
#define LCD_UKEY_HEAD_VERSION 2
#define LCD_UKEY_HEAD_RESERVED 2
-struct aml_lcd_unifykey_header_s {
+struct lcd_unifykey_header_s {
unsigned int crc32;
unsigned short data_len;
unsigned short version;
@@ -240,25 +224,50 @@
#define LCD_UKEY_TCON_SIZE 4096
#define LCD_UKEY_TCON_SIZE_NEW 24000
+#define LCD_UKEY_TCON_SPI_SIZE 1552 /* 16+48*32 */
+
+#define LCD_UKEY_TCON_SPI_HEAD_SIZE 16
+#define LCD_UKEY_TCON_SPI_HEAD_CRC32 4
+#define LCD_UKEY_TCON_SPI_HEAD_DATA_LEN 4
+#define LCD_UKEY_TCON_SPI_HEAD_VERSION 2
+#define LCD_UKEY_TCON_SPI_HEAD_DATA_LOAD_LEVEL 2
+#define LCD_UKEY_TCON_SPI_HEAD_BLOCK_CNT 2
+
+#define LCD_UKEY_TCON_SPI_BLOCK_CNT_MAX 32
+
+struct lcd_tcon_spi_unifykey_header_s {
+ unsigned int crc32;
+ unsigned int data_size;
+ unsigned short version;
+ unsigned short load_level;
+ unsigned short reserved;
+ unsigned short block_cnt;
+};
/* ********************************
* debug flag
* ********************************* */
-#define LCD_UKEY_DEBUG_NORMAL (1 << 0)
-#define LCD_UKEY_DEBUG_TCON (1 << 1)
+#define LCD_UKEY_DEBUG_TCON_LEN_MASK (0xffffff)
+#define LCD_UKEY_DEBUG_NORMAL BIT(24)
+#define LCD_UKEY_DEBUG_TCON BIT(25)
/* ********************************
* API
* ********************************* */
-extern int aml_lcd_unifykey_len_check(int key_len, int len);
-extern int aml_lcd_unifykey_header_check(unsigned char *buf, struct aml_lcd_unifykey_header_s *header);
-extern int aml_lcd_unifykey_check(const char *key_name);
-extern int aml_lcd_unifykey_get(const char *key_name, unsigned char *buf, int *len);
-extern int aml_lcd_unifykey_check_no_header(const char *key_name);
-extern int aml_lcd_unifykey_get_no_header(const char *key_name, unsigned char *buf, int *len);
+int lcd_unifykey_len_check(int key_len, int len);
+int lcd_unifykey_header_check(unsigned char *buf,
+ struct lcd_unifykey_header_s *header);
+int lcd_unifykey_check_exist(const char *key_name);
+int lcd_unifykey_check(const char *key_name);
+int lcd_unifykey_get(const char *key_name, unsigned char *buf, int *len);
+int lcd_unifykey_get_tcon(const char *key_name, unsigned char *buf, int *len);
+int lcd_unifykey_check_no_header(const char *key_name);
+int lcd_unifykey_get_no_header(const char *key_name, unsigned char *buf,
+ int *len);
+int lcd_unifykey_write(const char *key_name, unsigned char *buf, int len);
-extern void aml_lcd_unifykey_test(void);
-extern void aml_lcd_unifykey_tcon_test(int n);
-extern void aml_lcd_unifykey_dump(int flag);
+void lcd_unifykey_test(void);
+void lcd_unifykey_tcon_test(int n);
+void lcd_unifykey_dump(int index, unsigned int flag);
#endif
diff --git a/drivers/amlogic/media/vout/lcd/lcd_vbyone.c b/drivers/amlogic/media/vout/lcd/lcd_vbyone.c
new file mode 100644
index 0000000..00a1609
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/lcd_vbyone.c
@@ -0,0 +1,213 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/io.h>
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+#include "lcd_reg.h"
+#include "lcd_common.h"
+
+void lcd_vbyone_sw_reset(struct aml_lcd_drv_s *pdrv)
+{
+ unsigned int reg_phy_tx_ctrl0, offset;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
+
+ switch (pdrv->index) {
+ case 0:
+ reg_phy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY0_CNTL0;
+ break;
+ case 1:
+ reg_phy_tx_ctrl0 = COMBO_DPHY_EDP_LVDS_TX_PHY1_CNTL0;
+ break;
+ default:
+ LCDERR("[%d]: %s: invalid drv_index\n", pdrv->index, __func__);
+ return;
+ }
+ offset = pdrv->data->offset_venc_if[pdrv->index];
+
+ if (pdrv->data->chip_type == LCD_CHIP_T7) {
+ /* force PHY to 0 */
+ lcd_combo_dphy_setb(reg_phy_tx_ctrl0, 3, 8, 2);
+ lcd_vcbus_write(VBO_SOFT_RST + offset, 0x1ff);
+ udelay(5);
+ /* realease PHY */
+ lcd_combo_dphy_setb(reg_phy_tx_ctrl0, 0, 8, 2);
+ lcd_vcbus_write(VBO_SOFT_RST + offset, 0);
+ } else {
+ /* force PHY to 0 */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL0, 3, 8, 2);
+ lcd_vcbus_write(VBO_SOFT_RST, 0x1ff);
+ udelay(5);
+ /* realease PHY */
+ lcd_ana_setb(HHI_LVDS_TX_PHY_CNTL0, 0, 8, 2);
+ lcd_vcbus_write(VBO_SOFT_RST, 0);
+ }
+}
+
+void lcd_vbyone_wait_timing_stable(struct aml_lcd_drv_s *pdrv)
+{
+ unsigned int offset, timing_state;
+ int i = 200;
+
+ offset = pdrv->data->offset_venc[pdrv->index];
+
+ timing_state = lcd_vcbus_read(VBO_INTR_STATE + offset) & 0x1ff;
+ while ((timing_state) && (i > 0)) {
+ /* clear video timing error intr */
+ lcd_vcbus_setb(VBO_INTR_STATE_CTRL + offset, 0x7, 0, 3);
+ lcd_vcbus_setb(VBO_INTR_STATE_CTRL + offset, 0, 0, 3);
+ mdelay(2);
+ timing_state = lcd_vcbus_read(VBO_INTR_STATE + offset) & 0x1ff;
+ i--;
+ };
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("[%d]: vbyone timing state: 0x%03x, i=%d\n",
+ pdrv->index, timing_state, (200 - i));
+ }
+ mdelay(2);
+}
+
+void lcd_vbyone_cdr_training_hold(struct aml_lcd_drv_s *pdrv, int flag)
+{
+ unsigned int offset, reg;
+
+ offset = pdrv->data->offset_venc[pdrv->index];
+ reg = VBO_FSM_HOLDER_H + offset;
+ if (flag) {
+ LCDPR("[%d]: ctrl_flag for cdr_training_hold\n", pdrv->index);
+ lcd_vcbus_setb(reg, 0xffff, 0, 16);
+ } else {
+ mdelay(pdrv->config.control.vbyone_cfg.cdr_training_hold);
+ lcd_vcbus_setb(reg, 0, 0, 16);
+ }
+}
+
+#define VX1_HPD_WAIT_TIMEOUT 10000 /* 500ms */
+void lcd_vbyone_wait_hpd(struct aml_lcd_drv_s *pdrv)
+{
+ unsigned int reg, offset, val;
+ int i = 0;
+
+ offset = pdrv->data->offset_venc_if[pdrv->index];
+ reg = VBO_STATUS_L + offset;
+
+ LCDPR("[%d]: %s ...\n", pdrv->index, __func__);
+ while (i++ < VX1_HPD_WAIT_TIMEOUT) {
+ if (lcd_vcbus_getb(reg, 6, 1) == 0)
+ break;
+ udelay(100);
+ }
+
+ val = lcd_vcbus_getb(reg, 6, 1);
+ if (val) {
+ printf("hpd=%d\n", val);
+ } else {
+ printf("hpd=%d, i=%d\n", val, i);
+ /* force low only activated for actual hpd is low */
+ lcd_vcbus_setb(VBO_INSGN_CTRL + offset, 1, 2, 2);
+ }
+
+ if (pdrv->config.control.vbyone_cfg.ctrl_flag & 0x2) {
+ LCDPR("[%d]: ctrl_flag for hpd_data delay\n", pdrv->index);
+ mdelay(pdrv->config.control.vbyone_cfg.hpd_data_delay);
+ } else {
+ mdelay(10);; /* add 10ms delay for compatibility */
+ }
+}
+
+#define VX1_LOCKN_WAIT_TIMEOUT 500 /* 500ms */
+void lcd_vbyone_wait_stable(struct aml_lcd_drv_s *pdrv)
+{
+ unsigned int reg, offset;
+ int i = 0;
+
+ offset = pdrv->data->offset_venc_if[pdrv->index];
+ reg = VBO_STATUS_L + offset;
+
+ /* training hold release */
+ if (pdrv->config.control.vbyone_cfg.ctrl_flag & 0x4)
+ lcd_vbyone_cdr_training_hold(pdrv, 0);
+
+ while (i++ < VX1_LOCKN_WAIT_TIMEOUT) {
+ if ((lcd_vcbus_read(reg) & 0x3f) == 0x20)
+ break;
+ mdelay(1);
+ }
+ LCDPR("[%d]: %s status: 0x%x, i=%d\n",
+ pdrv->index, __func__, lcd_vcbus_read(reg), i);
+
+ /* power on reset */
+ if (pdrv->config.control.vbyone_cfg.ctrl_flag & 0x1) {
+ LCDPR("[%d]: ctrl_flag for power on reset\n", pdrv->index);
+ mdelay(pdrv->config.control.vbyone_cfg.power_on_reset_delay);
+ lcd_vbyone_sw_reset(pdrv);
+ }
+}
+
+void lcd_vbyone_hw_filter(struct aml_lcd_drv_s *pdrv, int flag)
+{
+ struct vbyone_config_s *vx1_conf;
+ unsigned int temp, period, offset;
+ unsigned int tick_period[] = {
+ 0xfff,
+ 0xff, /* 1: 0.8us */
+ 0x1ff, /* 2: 1.7us */
+ 0x3ff, /* 3: 3.4us */
+ 0x7ff, /* 4: 6.9us */
+ 0xfff, /* 5: 13.8us */
+ 0x1fff, /* 6: 27us */
+ 0x3fff, /* 7: 55us */
+ 0x7fff, /* 8: 110us */
+ 0xffff, /* 9: 221us */
+ 0x1ffff, /* 10: 441us */
+ 0x3ffff, /* 11: 883us */
+ 0x7ffff, /* 12: 1.76ms */
+ 0xfffff, /* 13: 3.53ms */
+ };
+
+ offset = pdrv->data->offset_venc_if[pdrv->index];
+
+ vx1_conf = &pdrv->config.control.vbyone_cfg;
+ if (flag) {
+ period = vx1_conf->hw_filter_time & 0xff;
+ if (period >= (sizeof(tick_period) / sizeof(unsigned int)))
+ period = tick_period[0];
+ else
+ period = tick_period[period];
+ temp = period & 0xffff;
+ lcd_vcbus_write(VBO_INFILTER_TICK_PERIOD_L + offset, temp);
+ temp = (period >> 16) & 0xf;
+ lcd_vcbus_write(VBO_INFILTER_TICK_PERIOD_H + offset, temp);
+ /* hpd */
+ temp = vx1_conf->hw_filter_cnt & 0xff;
+ if (temp == 0xff) {
+ lcd_vcbus_setb(VBO_INSGN_CTRL + offset, 0, 8, 4);
+ } else {
+ temp = (temp == 0) ? 0x7 : temp;
+ lcd_vcbus_setb(VBO_INSGN_CTRL + offset, temp, 8, 4);
+ }
+ /* lockn */
+ temp = (vx1_conf->hw_filter_cnt >> 8) & 0xff;
+ if (temp == 0xff) {
+ lcd_vcbus_setb(VBO_INSGN_CTRL + offset, 0, 12, 4);
+ } else {
+ temp = (temp == 0) ? 0x7 : temp;
+ lcd_vcbus_setb(VBO_INSGN_CTRL + offset, temp, 12, 4);
+ }
+ } else {
+ temp = (vx1_conf->hw_filter_time >> 8) & 0x1;
+ if (temp) {
+ lcd_vcbus_write(VBO_INFILTER_TICK_PERIOD_L + offset, 0xff);
+ lcd_vcbus_write(VBO_INFILTER_TICK_PERIOD_H + offset, 0x0);
+ lcd_vcbus_setb(VBO_INSGN_CTRL + offset, 0, 8, 4);
+ lcd_vcbus_setb(VBO_INSGN_CTRL + offset, 0, 12, 4);
+ LCDPR("[%d]: %s: %d disable for debug\n",
+ pdrv->index, __func__, flag);
+ }
+ }
+}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_venc.c b/drivers/amlogic/media/vout/lcd/lcd_venc.c
new file mode 100644
index 0000000..705ec13
--- /dev/null
+++ b/drivers/amlogic/media/vout/lcd/lcd_venc.c
@@ -0,0 +1,311 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <asm/arch/io.h>
+#ifdef CONFIG_AML_VPP
+#include <amlogic/media/vpp/vpp.h>
+#endif
+#include <amlogic/media/vout/lcd/aml_lcd.h>
+#include "lcd_reg.h"
+#include "lcd_common.h"
+
+#define LCD_WAIT_VSYNC_TIMEOUT 50000
+void lcd_wait_vsync(struct aml_lcd_drv_s *pdrv)
+{
+#ifndef CONFIG_AML_LCD_PXP
+ unsigned int offset, reg;
+ int line_cnt, line_cnt_previous;
+ int i = 0;
+
+ if (pdrv->data->chip_type >= LCD_CHIP_T7) {
+ offset = pdrv->data->offset_venc[pdrv->index];
+ reg = VPU_VENCP_STAT + offset;
+ } else {
+ reg = ENCL_INFO_READ;
+ }
+
+ line_cnt = 0x1fff;
+ line_cnt_previous = lcd_vcbus_getb(reg, 16, 13);
+ while (i++ < LCD_WAIT_VSYNC_TIMEOUT) {
+ line_cnt = lcd_vcbus_getb(reg, 16, 13);
+ if (line_cnt < line_cnt_previous)
+ break;
+ line_cnt_previous = line_cnt;
+ udelay(2);
+ }
+ /*LCDPR("line_cnt=%d, line_cnt_previous=%d, i=%d\n",
+ * line_cnt, line_cnt_previous, i);
+ */
+#endif
+}
+
+static void lcd_gamma_init(struct aml_lcd_drv_s *pdrv)
+{
+ if (pdrv->data->chip_type == LCD_CHIP_T7)
+ return;
+#ifndef CONFIG_AML_LCD_PXP
+#ifdef CONFIG_AML_VPP
+ lcd_wait_vsync(pdrv);
+ vpp_disable_lcd_gamma_table(pdrv->index);
+
+ vpp_init_lcd_gamma_table(pdrv->index);
+
+ lcd_wait_vsync(pdrv);
+ vpp_enable_lcd_gamma_table(pdrv->index);
+#endif
+#endif
+}
+
+static void lcd_set_encl_tcon(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_config_s *pconf = &pdrv->config;
+ unsigned int offset_if, offset_data;
+ unsigned int reg_rgb_base, reg_rgb_coeff, reg_dith_ctrl, reg_pol_ctrl;
+ unsigned int reg_de_hs, reg_de_he, reg_de_vs, reg_de_ve;
+ unsigned int reg_hsync_hs, reg_hsync_he, reg_hsync_vs, reg_hsync_ve;
+ unsigned int reg_vsync_hs, reg_vsync_he, reg_vsync_vs, reg_vsync_ve;
+
+ if (pdrv->data->chip_type == LCD_CHIP_T7) {
+ offset_data = pdrv->data->offset_venc_data[pdrv->index];
+ offset_if = pdrv->data->offset_venc_if[pdrv->index];
+ reg_rgb_base = LCD_RGB_BASE_ADDR + offset_data;
+ reg_rgb_coeff = LCD_RGB_COEFF_ADDR + offset_data;
+ reg_dith_ctrl = LCD_DITH_CNTL_ADDR + offset_data;
+ reg_pol_ctrl = LCD_POL_CNTL_ADDR + offset_data;
+ reg_de_hs = DE_HS_ADDR + offset_if;
+ reg_de_he = DE_HE_ADDR + offset_if;
+ reg_de_vs = DE_VS_ADDR + offset_if;
+ reg_de_ve = DE_VE_ADDR + offset_if;
+ reg_hsync_hs = HSYNC_HS_ADDR + offset_if;
+ reg_hsync_he = HSYNC_HE_ADDR + offset_if;
+ reg_hsync_vs = HSYNC_VS_ADDR + offset_if;
+ reg_hsync_ve = HSYNC_VE_ADDR + offset_if;
+ reg_vsync_hs = VSYNC_HS_ADDR + offset_if;
+ reg_vsync_he = VSYNC_HE_ADDR + offset_if;
+ reg_vsync_vs = VSYNC_VS_ADDR + offset_if;
+ reg_vsync_ve = VSYNC_VE_ADDR + offset_if;
+ } else {
+ reg_rgb_base = L_RGB_BASE_ADDR;
+ reg_rgb_coeff = L_RGB_COEFF_ADDR;
+ reg_dith_ctrl = L_POL_CNTL_ADDR;
+ reg_pol_ctrl = L_DITH_CNTL_ADDR;
+ reg_de_hs = L_DE_HS_ADDR;
+ reg_de_he = L_DE_HE_ADDR;
+ reg_de_vs = L_DE_VS_ADDR;
+ reg_de_ve = L_DE_VE_ADDR;
+ reg_hsync_hs = L_HSYNC_HS_ADDR;
+ reg_hsync_he = L_HSYNC_HE_ADDR;
+ reg_hsync_vs = L_HSYNC_VS_ADDR;
+ reg_hsync_ve = L_HSYNC_VE_ADDR;
+ reg_vsync_hs = L_VSYNC_HS_ADDR;
+ reg_vsync_he = L_VSYNC_HE_ADDR;
+ reg_vsync_vs = L_VSYNC_VS_ADDR;
+ reg_vsync_ve = L_VSYNC_VE_ADDR;
+ }
+
+ lcd_vcbus_write(reg_rgb_base, 0x0);
+ lcd_vcbus_write(reg_rgb_coeff, 0x400);
+
+ switch (pconf->basic.lcd_bits) {
+ case 6:
+ lcd_vcbus_write(reg_dith_ctrl, 0x600);
+ break;
+ case 8:
+ lcd_vcbus_write(reg_dith_ctrl, 0x400);
+ break;
+ case 10:
+ default:
+ lcd_vcbus_write(reg_dith_ctrl, 0x0);
+ break;
+ }
+
+ switch (pconf->basic.lcd_type) {
+ case LCD_LVDS:
+ lcd_vcbus_setb(reg_pol_ctrl, 1, 0, 1);
+ if (pconf->timing.vsync_pol)
+ lcd_vcbus_setb(reg_pol_ctrl, 1, 1, 1);
+ break;
+ case LCD_VBYONE:
+ if (pconf->timing.hsync_pol)
+ lcd_vcbus_setb(reg_pol_ctrl, 1, 0, 1);
+ if (pconf->timing.vsync_pol)
+ lcd_vcbus_setb(reg_pol_ctrl, 1, 1, 1);
+ break;
+ case LCD_MIPI:
+ //lcd_vcbus_setb(reg_pol_ctrl, 0x3, 0, 2);
+ /*lcd_vcbus_write(reg_pol_ctrl,
+ * (lcd_vcbus_read(reg_pol_ctrl) |
+ * ((0 << 2) | (vs_pol_adj << 1) | (hs_pol_adj << 0))));
+ */
+ /*lcd_vcbus_write(reg_pol_ctrl, (lcd_vcbus_read(reg_pol_ctrl) |
+ * ((1 << LCD_TCON_DE_SEL) | (1 << LCD_TCON_VS_SEL) |
+ * (1 << LCD_TCON_HS_SEL))));
+ */
+ break;
+ case LCD_EDP:
+ lcd_vcbus_setb(reg_pol_ctrl, 1, 0, 1);
+ break;
+ default:
+ break;
+ }
+
+ /* DE signal */
+ lcd_vcbus_write(reg_de_hs, pconf->timing.de_hs_addr);
+ lcd_vcbus_write(reg_de_he, pconf->timing.de_he_addr);
+ lcd_vcbus_write(reg_de_vs, pconf->timing.de_vs_addr);
+ lcd_vcbus_write(reg_de_ve, pconf->timing.de_ve_addr);
+
+ /* Hsync signal */
+ lcd_vcbus_write(reg_hsync_hs, pconf->timing.hs_hs_addr);
+ lcd_vcbus_write(reg_hsync_he, pconf->timing.hs_he_addr);
+ lcd_vcbus_write(reg_hsync_vs, pconf->timing.hs_vs_addr);
+ lcd_vcbus_write(reg_hsync_ve, pconf->timing.hs_ve_addr);
+
+ /* Vsync signal */
+ lcd_vcbus_write(reg_vsync_hs, pconf->timing.vs_hs_addr);
+ lcd_vcbus_write(reg_vsync_he, pconf->timing.vs_he_addr);
+ lcd_vcbus_write(reg_vsync_vs, pconf->timing.vs_vs_addr);
+ lcd_vcbus_write(reg_vsync_ve, pconf->timing.vs_ve_addr);
+}
+
+void lcd_set_venc(struct aml_lcd_drv_s *pdrv)
+{
+ struct lcd_config_s *pconf = &pdrv->config;
+ unsigned int hstart, hend, vstart, vend;
+ unsigned int reg_disp_viu_ctrl, offset;
+ unsigned int pre_de_vs = 0, pre_de_ve = 0, pre_de_hs = 0, pre_de_he = 0;
+
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s\n", pdrv->index, __func__);
+
+ hstart = pconf->timing.video_on_pixel;
+ hend = pconf->basic.h_active + hstart - 1;
+ vstart = pconf->timing.video_on_line;
+ vend = pconf->basic.v_active + vstart - 1;
+ offset = pdrv->data->offset_venc[pdrv->index];
+ switch (pdrv->index) {
+ case 0:
+ reg_disp_viu_ctrl = VPU_DISP_VIU0_CTRL;
+ break;
+ case 1:
+ reg_disp_viu_ctrl = VPU_DISP_VIU1_CTRL;
+ break;
+ case 2:
+ reg_disp_viu_ctrl = VPU_DISP_VIU2_CTRL;
+ break;
+ default:
+ LCDERR("[%d]: %s: invalid drv_index\n", pdrv->index, __func__);
+ return;
+ }
+
+ lcd_vcbus_write(ENCL_VIDEO_EN + offset, 0);
+
+ lcd_vcbus_write(ENCL_VIDEO_MODE + offset, 0x8000); /* bit[15] shadown en */
+ lcd_vcbus_write(ENCL_VIDEO_MODE_ADV + offset, 0x0418); /* Sampling rate: 1 */
+
+ lcd_vcbus_write(ENCL_VIDEO_FILT_CTRL + offset, 0x1000); /* bypass filter */
+ lcd_vcbus_write(ENCL_VIDEO_MAX_PXCNT + offset, pconf->basic.h_period - 1);
+ lcd_vcbus_write(ENCL_VIDEO_MAX_LNCNT + offset, pconf->basic.v_period - 1);
+ lcd_vcbus_write(ENCL_VIDEO_HAVON_BEGIN + offset, hstart);
+ lcd_vcbus_write(ENCL_VIDEO_HAVON_END + offset, hend);
+ lcd_vcbus_write(ENCL_VIDEO_VAVON_BLINE + offset, vstart);
+ lcd_vcbus_write(ENCL_VIDEO_VAVON_ELINE + offset, vend);
+ if (pconf->basic.lcd_type == LCD_P2P ||
+ pconf->basic.lcd_type == LCD_MLVDS) {
+ switch (pdrv->data->chip_type) {
+ case LCD_CHIP_TL1:
+ case LCD_CHIP_TM2:
+ pre_de_vs = vstart - 1 - 4;
+ pre_de_ve = vstart - 1;
+ pre_de_hs = hstart + PRE_DE_DELAY;
+ pre_de_he = pconf->basic.h_active - 1 + pre_de_hs;
+ break;
+ default:
+ pre_de_vs = vstart - 8;
+ pre_de_ve = pconf->basic.v_active + pre_de_vs;
+ pre_de_hs = hstart + PRE_DE_DELAY;
+ pre_de_he = pconf->basic.h_active - 1 + pre_de_hs;
+ break;
+ }
+ lcd_vcbus_write(ENCL_VIDEO_V_PRE_DE_BLINE + offset, pre_de_vs);
+ lcd_vcbus_write(ENCL_VIDEO_V_PRE_DE_ELINE + offset, pre_de_ve);
+ lcd_vcbus_write(ENCL_VIDEO_H_PRE_DE_BEGIN + offset, pre_de_hs);
+ lcd_vcbus_write(ENCL_VIDEO_H_PRE_DE_END + offset, pre_de_he);
+ }
+
+ lcd_vcbus_write(ENCL_VIDEO_HSO_BEGIN + offset, pconf->timing.hs_hs_addr);
+ lcd_vcbus_write(ENCL_VIDEO_HSO_END + offset, pconf->timing.hs_he_addr);
+ lcd_vcbus_write(ENCL_VIDEO_VSO_BEGIN + offset, pconf->timing.vs_hs_addr);
+ lcd_vcbus_write(ENCL_VIDEO_VSO_END + offset, pconf->timing.vs_he_addr);
+ lcd_vcbus_write(ENCL_VIDEO_VSO_BLINE + offset, pconf->timing.vs_vs_addr);
+ lcd_vcbus_write(ENCL_VIDEO_VSO_ELINE + offset, pconf->timing.vs_ve_addr);
+ lcd_vcbus_write(ENCL_VIDEO_RGBIN_CTRL + offset, 3);
+
+ switch (pdrv->data->chip_type) {
+ case LCD_CHIP_TL1:
+ case LCD_CHIP_TM2:
+ case LCD_CHIP_T5:
+ case LCD_CHIP_T5D:
+ /*[15:14]: 2'b10 or 2'b01*/
+ lcd_vcbus_write(ENCL_INBUF_CNTL1 + offset,
+ (2 << 14) | (pconf->basic.h_active - 1));
+ lcd_vcbus_write(ENCL_INBUF_CNTL0 + offset, 0x200);
+ break;
+ case LCD_CHIP_T7:
+ lcd_vcbus_write(ENCL_INBUF_CNTL1 + offset,
+ (5 << 13) | (pconf->basic.h_active - 1));
+ lcd_vcbus_write(ENCL_INBUF_CNTL0 + offset, 0x200);
+ break;
+ default:
+ break;
+ }
+
+ /* default black pattern */
+ lcd_vcbus_write(ENCL_TST_MDSEL + offset, 0);
+ lcd_vcbus_write(ENCL_TST_Y + offset, 0);
+ lcd_vcbus_write(ENCL_TST_CB + offset, 0);
+ lcd_vcbus_write(ENCL_TST_CR + offset, 0);
+ lcd_vcbus_write(ENCL_TST_EN + offset, 1);
+ lcd_vcbus_setb(ENCL_VIDEO_MODE_ADV + offset, 0, 3, 1);
+
+ lcd_vcbus_write(ENCL_VIDEO_EN + offset, 1);
+ if (pdrv->data->chip_type == LCD_CHIP_T7) {
+ /*
+ * bit31: lvds enable
+ * bit30: vx1 enable
+ * bit29: hdmitx enable
+ * bit28: dsi_edp enable
+ */
+ switch (pdrv->config.basic.lcd_type) {
+ case LCD_LVDS:
+ lcd_vcbus_write(reg_disp_viu_ctrl, (1 << 31) |
+ (0 << 30) |
+ (0 << 29) |
+ (0 << 28));
+ break;
+ case LCD_VBYONE:
+ lcd_vcbus_write(reg_disp_viu_ctrl, (0 << 31) |
+ (1 << 30) |
+ (0 << 29) |
+ (0 << 28));
+ break;
+ case LCD_MIPI:
+ case LCD_EDP:
+ lcd_vcbus_write(reg_disp_viu_ctrl, (0 << 31) |
+ (0 << 30) |
+ (0 << 29) |
+ (1 << 28));
+ break;
+ default:
+ break;
+ }
+ }
+ lcd_vcbus_write(VPU_VENC_CTRL + offset, 2);
+
+ lcd_set_encl_tcon(pdrv);
+ lcd_gamma_init(pdrv);
+}
diff --git a/drivers/amlogic/media/vout/lcd/lcd_vout.c b/drivers/amlogic/media/vout/lcd/lcd_vout.c
index 780930e..102f7db 100644
--- a/drivers/amlogic/media/vout/lcd/lcd_vout.c
+++ b/drivers/amlogic/media/vout/lcd/lcd_vout.c
@@ -1,102 +1,203 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/lcd/lcd_vout.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
#include <malloc.h>
-#include <asm/arch/cpu_id.h>
+#include <amlogic/cpu_id.h>
#include <fdtdec.h>
#include <amlogic/keyunify.h>
+#include <amlogic/media/vout/aml_vout.h>
#include <amlogic/media/vout/lcd/aml_lcd.h>
#ifdef CONFIG_AML_LCD_EXTERN
#include <amlogic/media/vout/lcd/lcd_extern.h>
#endif
#include "lcd_reg.h"
#include "lcd_common.h"
-#ifdef CONFIG_AML_LCD_TABLET
-#include "lcd_tablet/mipi_dsi_util.h"
-#endif
#define PANEL_NAME "panel"
-DECLARE_GLOBAL_DATA_PTR;
+//DECLARE_GLOBAL_DATA_PTR;
unsigned int lcd_debug_print_flag;
-unsigned int lcd_debug_load_flag;
-static struct aml_lcd_drv_s aml_lcd_driver;
+unsigned int lcd_debug_test;
+struct aml_lcd_data_s *lcd_data;
+static struct aml_lcd_drv_s *lcd_driver[LCD_MAX_DRV];
+static struct lcd_debug_ctrl_s debug_ctrl;
+
+static struct aml_lcd_data_s lcd_data_g12a = {
+ .chip_type = LCD_CHIP_G12A,
+ .chip_name = "g12a",
+ .rev_type = 0,
+ .drv_max = 1,
+ .offset_venc = {0},
+ .offset_venc_if = {0},
+ .offset_venc_data = {0},
+ .dft_conf = {NULL, NULL, NULL},
+};
+
+static struct aml_lcd_data_s lcd_data_g12b = {
+ .chip_type = LCD_CHIP_G12B,
+ .chip_name = "g12b",
+ .rev_type = 0,
+ .drv_max = 1,
+ .offset_venc = {0},
+ .offset_venc_if = {0},
+ .offset_venc_data = {0},
+ .dft_conf = {NULL, NULL, NULL},
+};
+
+static struct aml_lcd_data_s lcd_data_tl1 = {
+ .chip_type = LCD_CHIP_TL1,
+ .chip_name = "tl1",
+ .rev_type = 0,
+ .drv_max = 1,
+ .offset_venc = {0},
+ .offset_venc_if = {0},
+ .offset_venc_data = {0},
+ .dft_conf = {NULL, NULL, NULL},
+};
+
+static struct aml_lcd_data_s lcd_data_sm1 = {
+ .chip_type = LCD_CHIP_SM1,
+ .chip_name = "sm1",
+ .rev_type = 0,
+ .drv_max = 1,
+ .offset_venc = {0},
+ .offset_venc_if = {0},
+ .offset_venc_data = {0},
+ .dft_conf = {NULL, NULL, NULL},
+};
+
+static struct aml_lcd_data_s lcd_data_tm2 = {
+ .chip_type = LCD_CHIP_TM2,
+ .chip_name = "tm2",
+ .rev_type = 0,
+ .drv_max = 1,
+ .offset_venc = {0},
+ .offset_venc_if = {0},
+ .offset_venc_data = {0},
+ .dft_conf = {NULL, NULL, NULL},
+};
+
+static struct aml_lcd_data_s lcd_data_t5 = {
+ .chip_type = LCD_CHIP_T5,
+ .chip_name = "t5",
+ .rev_type = 0,
+ .drv_max = 1,
+ .offset_venc = {0},
+ .offset_venc_if = {0},
+ .offset_venc_data = {0},
+ .dft_conf = {NULL, NULL, NULL},
+};
+
+static struct aml_lcd_data_s lcd_data_t5d = {
+ .chip_type = LCD_CHIP_T5D,
+ .chip_name = "t5d",
+ .rev_type = 0,
+ .drv_max = 1,
+ .offset_venc = {0},
+ .offset_venc_if = {0},
+ .offset_venc_data = {0},
+ .dft_conf = {NULL, NULL, NULL},
+};
+
+static struct aml_lcd_data_s lcd_data_t7 = {
+ .chip_type = LCD_CHIP_T7,
+ .chip_name = "t7",
+ .rev_type = 0,
+ .drv_max = 3,
+ .offset_venc = {0x0, (0x600 << 2), (0x800 << 2)},
+ .offset_venc_if = {0x0, (0x500 << 2), (0x600 << 2)},
+ .offset_venc_data = {0x0, (0x100 << 2), (0x200 << 2)},
+ .dft_conf = {NULL, NULL, NULL},
+};
static void lcd_chip_detect(void)
{
#if 1
unsigned int cpu_type;
+ unsigned int rev_type;
cpu_type = get_cpu_id().family_id;
+ rev_type = get_cpu_id().chip_rev;
switch (cpu_type) {
case MESON_CPU_MAJOR_ID_G12A:
- aml_lcd_driver.chip_type = LCD_CHIP_G12A;
+ lcd_data = &lcd_data_g12a;
break;
case MESON_CPU_MAJOR_ID_G12B:
- aml_lcd_driver.chip_type = LCD_CHIP_G12B;
+ lcd_data = &lcd_data_g12b;
break;
case MESON_CPU_MAJOR_ID_TL1:
- aml_lcd_driver.chip_type = LCD_CHIP_TL1;
+ lcd_data = &lcd_data_tl1;
break;
case MESON_CPU_MAJOR_ID_SM1:
- aml_lcd_driver.chip_type = LCD_CHIP_SM1;
+ lcd_data = &lcd_data_sm1;
+ break;
+ case MESON_CPU_MAJOR_ID_TM2:
+ lcd_data = &lcd_data_tm2;
+ break;
+ case MESON_CPU_MAJOR_ID_T5:
+ lcd_data = &lcd_data_t5;
+ break;
+ case MESON_CPU_MAJOR_ID_T5D:
+ lcd_data = &lcd_data_t5d;
+ break;
+ case MESON_CPU_MAJOR_ID_T7:
+ lcd_data = &lcd_data_t7;
break;
default:
- aml_lcd_driver.chip_type = LCD_CHIP_MAX;
- break;
+ lcd_data = NULL;
+ return;
}
+ lcd_data->rev_type = rev_type;
#else
- aml_lcd_driver.chip_type = LCD_CHIP_G12B;
+ lcd_data = &lcd_data_t7;
#endif
- if (lcd_debug_print_flag)
- LCDPR("check chip: %d\n", aml_lcd_driver.chip_type);
-}
-
-static int lcd_check_valid(void)
-{
- if (aml_lcd_driver.config_check == NULL) {
- LCDERR("invalid lcd config\n");
- return -1;
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("check chip: %d %s\n",
+ lcd_data->chip_type, lcd_data->chip_name);
}
- return 0;
}
-static void lcd_power_ctrl(int status)
+struct aml_lcd_data_s *aml_lcd_get_data(void)
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
+ return lcd_data;
+}
+
+static struct aml_lcd_drv_s *lcd_driver_check_valid(int index)
+{
+ if (!lcd_driver[index] || !lcd_driver[index]->config_check) {
+ LCDERR("invalid lcd%d config\n", index);
+ return NULL;
+ }
+ return lcd_driver[index];
+}
+
+struct aml_lcd_drv_s *aml_lcd_get_driver(int index)
+{
+ return lcd_driver_check_valid(index);
+}
+
+static void lcd_power_ctrl(struct aml_lcd_drv_s *pdrv, int status)
+{
struct lcd_power_ctrl_s *lcd_power;
struct lcd_power_step_s *power_step;
+ char *str;
+ unsigned int i, wait, gpio;
+ int value = LCD_PMU_GPIO_NUM_MAX;
#ifdef CONFIG_AML_LCD_EXTERN
- struct aml_lcd_extern_driver_s *ext_drv;
+ struct lcd_extern_driver_s *ext_drv;
#endif
- int i;
-
i = 0;
- lcd_power = lcd_drv->lcd_config->lcd_power;
+ lcd_power = &pdrv->config.power;
if (status) {
/* check if factory test */
- if (lcd_drv->factory_lcd_power_on_step) {
- LCDPR("%s: factory test power_on_step!\n", __func__);
- power_step = lcd_drv->factory_lcd_power_on_step;
+ if (pdrv->factory_lcd_power_on_step) {
+ LCDPR("[%d]: %s: factory test power_on_step!\n",
+ pdrv->index, __func__);
+ power_step = pdrv->factory_lcd_power_on_step;
} else {
power_step = &lcd_power->power_on_step[0];
}
@@ -107,29 +208,41 @@
while (i < LCD_PWR_STEP_MAX) {
if (power_step->type >= LCD_POWER_TYPE_MAX)
break;
- if (lcd_debug_print_flag) {
- LCDPR("power_ctrl: %d, step %d: type=%d, index=%d, value=%d, delay=%d\n",
- status, i, power_step->type, power_step->index,
- power_step->value, power_step->delay);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("[%d]: power_ctrl: %d, step %d: type=%d, index=%d, value=%d, delay=%d\n",
+ pdrv->index, status, i,
+ power_step->type, power_step->index,
+ power_step->value, power_step->delay);
}
switch (power_step->type) {
case LCD_POWER_TYPE_CPU:
- lcd_gpio_set(power_step->index, power_step->value);
+ if (power_step->index < LCD_CPU_GPIO_NUM_MAX) {
+ str = lcd_power->cpu_gpio[power_step->index];
+ gpio = lcd_gpio_name_map_num(str);
+ lcd_gpio_set(gpio, power_step->value);
+ } else {
+ LCDERR("[%d]: invalid cpu_gpio index: %d\n",
+ pdrv->index, power_step->index);
+ }
break;
case LCD_POWER_TYPE_PMU:
- LCDPR("to do\n");
+ if (power_step->index < LCD_PMU_GPIO_NUM_MAX)
+ LCDPR("to do\n");
+ else
+ LCDERR("pmu_gpio invalid index: %d\n",
+ power_step->index);
break;
case LCD_POWER_TYPE_SIGNAL:
if (status)
- lcd_drv->driver_init();
+ pdrv->driver_init(pdrv);
else
- lcd_drv->driver_disable();
+ pdrv->driver_disable(pdrv);
break;
#ifdef CONFIG_AML_LCD_EXTERN
case LCD_POWER_TYPE_EXTERN:
- ext_drv = aml_lcd_extern_get_driver();
- if (ext_drv == NULL) {
- LCDERR("ext_drv is null\n");
+ ext_drv = lcd_extern_get_driver(power_step->index);
+ if (!ext_drv) {
+ LCDERR("no ext_drv\n");
break;
}
if (status) {
@@ -145,193 +258,180 @@
}
break;
#endif
+ case LCD_POWER_TYPE_WAIT_GPIO:
+ if (power_step->index < LCD_CPU_GPIO_NUM_MAX) {
+ str = lcd_power->cpu_gpio[power_step->index];
+ gpio = lcd_gpio_name_map_num(str);
+ lcd_gpio_set(gpio, LCD_GPIO_INPUT);
+ } else {
+ LCDERR("[%d]: wait_gpio index: %d\n",
+ pdrv->index, power_step->index);
+ break;
+ }
+ LCDPR("[%d]: lcd_power_type_wait_gpio wait\n", pdrv->index);
+ for (wait = 0; wait < power_step->delay; wait++) {
+ value = lcd_gpio_input_get(gpio);
+ if (value == power_step->value) {
+ LCDPR("[%d]: get value: %d, wait ok\n",
+ pdrv->index, value);
+ break;
+ }
+ mdelay(1);
+ }
+ if (wait == power_step->delay) {
+ LCDERR("[%d]: get value: %d, wait timeout!\n",
+ pdrv->index, value);
+ }
+ break;
+ case LCD_POWER_TYPE_CLK_SS:
+ break;
+#ifdef CONFIG_AML_LCD_TCON
+ case LCD_POWER_TYPE_TCON_SPI_DATA_LOAD:
+ if (pdrv->lcd_tcon_spi_data_load)
+ pdrv->lcd_tcon_spi_data_load();
+ break;
+#endif
default:
break;
}
- if (power_step->delay)
- mdelay(power_step->delay);
+
+ if (power_step->type != LCD_POWER_TYPE_WAIT_GPIO) {
+#ifndef CONFIG_AML_LCD_PXP
+ if (power_step->delay > 0)
+ mdelay(power_step->delay);
+#endif
+ }
i++;
power_step++;
}
- if (lcd_debug_print_flag)
- LCDPR("%s: %d\n", __func__, status);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: %s: %d\n", pdrv->index, __func__, status);
}
-static void lcd_gamma_init(void)
+static void lcd_encl_on(struct aml_lcd_drv_s *pdrv)
{
- lcd_wait_vsync();
- vpp_disable_lcd_gamma_table();
+ pdrv->driver_init_pre(pdrv);
+ if (lcd_debug_test)
+ aml_lcd_debug_test(pdrv, lcd_debug_test);
- vpp_init_lcd_gamma_table();
-
- lcd_wait_vsync();
- vpp_enable_lcd_gamma_table();
+ pdrv->status |= LCD_STATUS_ENCL_ON;
}
-static void lcd_module_enable(char *mode)
+static void lcd_interface_on(struct aml_lcd_drv_s *pdrv)
+{
+ lcd_power_ctrl(pdrv, 1);
+ pdrv->config.retry_enable_cnt = 0;
+ while (pdrv->config.retry_enable_flag) {
+ if (pdrv->config.retry_enable_cnt++ >= LCD_ENABLE_RETRY_MAX)
+ break;
+ LCDPR("[%d]: retry enable...%d\n",
+ pdrv->index, pdrv->config.retry_enable_cnt);
+ lcd_power_ctrl(pdrv, 0);
+ mdelay(1000);
+ lcd_power_ctrl(pdrv, 1);
+ }
+ pdrv->config.retry_enable_cnt = 0;
+ pdrv->status |= LCD_STATUS_IF_ON;
+}
+
+static void lcd_module_enable(struct aml_lcd_drv_s *pdrv, char *mode, unsigned int frac)
{
unsigned int sync_duration;
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
- struct lcd_config_s *pconf = lcd_drv->lcd_config;
+ struct lcd_config_s *pconf;
int ret;
- ret = lcd_drv->config_check(mode);
+ pconf = &pdrv->config;
+ ret = pdrv->config_check(pdrv, mode, frac);
if (ret) {
- LCDERR("init exit\n");
+ LCDERR("[%d]: init exit\n", pdrv->index);
return;
}
- sync_duration = pconf->lcd_timing.sync_duration_num;
- sync_duration = (sync_duration * 10 / pconf->lcd_timing.sync_duration_den);
- LCDPR("enable: %s, %s, %ux%u@%u.%uHz\n", pconf->lcd_basic.model_name,
- lcd_type_type_to_str(pconf->lcd_basic.lcd_type),
- pconf->lcd_basic.h_active, pconf->lcd_basic.v_active,
- (sync_duration / 10), (sync_duration % 10));
+ sync_duration = pconf->timing.sync_duration_num;
+ sync_duration = (sync_duration * 100 /
+ pconf->timing.sync_duration_den);
+ LCDPR("[%d]: enable: %s, %s, %ux%u@%u.%02uHz\n",
+ pdrv->index, pconf->basic.model_name,
+ lcd_type_type_to_str(pconf->basic.lcd_type),
+ pconf->basic.h_active, pconf->basic.v_active,
+ (sync_duration / 100), (sync_duration % 100));
- lcd_drv->driver_init_pre();
- lcd_gamma_init();
- lcd_power_ctrl(1);
-
- pconf->retry_enable_cnt = 0;
- while (pconf->retry_enable_flag) {
- if (pconf->retry_enable_cnt++ >= LCD_ENABLE_RETRY_MAX)
- break;
- LCDPR("retry enable...%d\n", pconf->retry_enable_cnt);
- lcd_power_ctrl(0);
- lcd_drv->driver_init_pre();
- mdelay(100);
- lcd_power_ctrl(1);
+ if ((pdrv->status & LCD_STATUS_ENCL_ON) == 0)
+ lcd_encl_on(pdrv);
+ if ((pdrv->status & LCD_STATUS_IF_ON) == 0) {
+ if (pdrv->boot_ctrl.init_level == LCD_INIT_LEVEL_NORMAL) {
+ lcd_interface_on(pdrv);
+#ifdef CONFIG_AML_LCD_BACKLIGHT
+ aml_bl_driver_enable(pdrv->index);
+#endif
+ }
}
- pconf->retry_enable_cnt = 0;
-
- lcd_vcbus_write(VPP_POSTBLEND_H_SIZE, pconf->lcd_basic.h_active);
- lcd_vcbus_write(VENC_INTCTRL, 0x200);
-
- bl_pwm_config_update(lcd_drv->bl_config);
- bl_set_level(lcd_drv->bl_config->level_default);
- bl_power_ctrl(1);
- lcd_mute_setting(0);
-
- lcd_drv->lcd_status = 1;
+ if (!lcd_debug_test)
+ lcd_mute_setting(pdrv, 0);
}
-static void lcd_module_disable(void)
+static void lcd_module_disable(struct aml_lcd_drv_s *pdrv)
{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
+ unsigned int offset;
- LCDPR("disable: %s\n", lcd_drv->lcd_config->lcd_basic.model_name);
+ LCDPR("[%d]: disable: %s\n", pdrv->index, pdrv->config.basic.model_name);
- lcd_mute_setting(1);
- bl_power_ctrl(0);
+ offset = pdrv->data->offset_venc[pdrv->index];
- lcd_power_ctrl(0);
+ lcd_mute_setting(pdrv, 1);
+ if (pdrv->status & LCD_STATUS_IF_ON) {
+#ifdef CONFIG_AML_LCD_BACKLIGHT
+ aml_bl_driver_disable(pdrv->index);
+#endif
+ lcd_power_ctrl(pdrv, 0);
+ }
- lcd_drv->lcd_status = 0;
+ lcd_vcbus_write(ENCL_VIDEO_EN + offset, 0);
+ lcd_disable_clk(pdrv);
+ pdrv->status = 0;
}
-static void lcd_vbyone_filter_flag_print(struct lcd_config_s *pconf)
+static void lcd_module_prepare(struct aml_lcd_drv_s *pdrv,
+ char *mode, unsigned int frac)
{
- struct vbyone_config_s *vx1_conf = pconf->lcd_control.vbyone_config;
+ int ret;
- LCDPR("vx1_sw_filter_en: %d\n", vx1_conf->vx1_sw_filter_en);
- LCDPR("vx1_sw_filter_time: %d\n", vx1_conf->vx1_sw_filter_time);
- LCDPR("vx1_sw_filter_cnt: %d\n", vx1_conf->vx1_sw_filter_cnt);
- LCDPR("vx1_sw_filter_retry_cnt: %d\n", vx1_conf->vx1_sw_filter_retry_cnt);
- LCDPR("vx1_sw_filter_retry_delay: %d\n", vx1_conf->vx1_sw_filter_retry_delay);
- LCDPR("vx1_sw_cdr_detect_time: %d\n", vx1_conf->vx1_sw_cdr_detect_time);
- LCDPR("vx1_sw_cdr_detect_cnt: %d\n", vx1_conf->vx1_sw_cdr_detect_cnt);
- LCDPR("vx1_sw_cdr_timeout_cnt: %d\n", vx1_conf->vx1_sw_cdr_timeout_cnt);
-}
-
-static void lcd_vbyone_filter_env_init(struct lcd_config_s *pconf)
-{
- struct vbyone_config_s *vx1_conf = pconf->lcd_control.vbyone_config;
- char *str;
- unsigned int temp = 0;
-
- str = env_get("lcd_debug_vx1_sw_filter");
- if (str)
- temp = simple_strtoul(str, NULL, 10);
- if (temp == 0)
+ ret = pdrv->config_check(pdrv, mode, frac);
+ if (ret) {
+ LCDERR("[%d]: prepare exit\n", pdrv->index);
return;
-
- LCDPR("%s\n", __func__);
- str = env_get("vx1_sw_filter_en");
- if (str) {
- vx1_conf->vx1_sw_filter_en = simple_strtoul(str, NULL, 10);
- LCDPR("vx1_sw_filter_en: %d\n", vx1_conf->vx1_sw_filter_en);
}
- str = env_get("vx1_sw_filter_time"); /* 100us */
- if (str) {
- vx1_conf->vx1_sw_filter_time = simple_strtoul(str, NULL, 10);
- LCDPR("vx1_sw_filter_time: %d\n", vx1_conf->vx1_sw_filter_time);
- }
-
- str = env_get("vx1_sw_filter_cnt");
- if (str) {
- vx1_conf->vx1_sw_filter_cnt = simple_strtoul(str, NULL, 10);
- LCDPR("vx1_sw_filter_cnt: %d\n", vx1_conf->vx1_sw_filter_cnt);
- }
-
- str = env_get("vx1_sw_filter_retry_cnt");
- if (str) {
- vx1_conf->vx1_sw_filter_retry_cnt = simple_strtoul(str, NULL, 10);
- LCDPR("vx1_sw_filter_retry_cnt: %d\n", vx1_conf->vx1_sw_filter_retry_cnt);
- }
-
- str = env_get("vx1_sw_filter_retry_delay"); /* ms */
- if (str) {
- vx1_conf->vx1_sw_filter_retry_delay = simple_strtoul(str, NULL, 10);
- LCDPR("vx1_sw_filter_retry_delay: %d\n", vx1_conf->vx1_sw_filter_retry_delay);
- }
-
- str = env_get("vx1_sw_cdr_detect_time"); /* us * 100 */
- if (str) {
- vx1_conf->vx1_sw_cdr_detect_time = simple_strtoul(str, NULL, 10);
- LCDPR("vx1_sw_cdr_detect_time: %d\n", vx1_conf->vx1_sw_cdr_detect_time);
- }
-
- str = env_get("vx1_sw_cdr_detect_cnt");
- if (str) {
- vx1_conf->vx1_sw_cdr_detect_cnt = simple_strtoul(str, NULL, 10);
- LCDPR("vx1_sw_cdr_detect_cnt: %d\n", vx1_conf->vx1_sw_cdr_detect_cnt);
- }
-
- str = env_get("vx1_sw_cdr_timeout_cnt");
- if (str) {
- vx1_conf->vx1_sw_cdr_timeout_cnt = simple_strtoul(str, NULL, 10);
- LCDPR("vx1_sw_cdr_timeout_cnt: %d\n", vx1_conf->vx1_sw_cdr_timeout_cnt);
- }
+ if ((pdrv->status & LCD_STATUS_ENCL_ON) == 0)
+ lcd_encl_on(pdrv);
}
#ifdef CONFIG_AML_LCD_EXTERN
-static int lcd_extern_load_config(const void *dt_blob, struct lcd_config_s *pconf)
+static int lcd_extern_load_config(char *dt_addr, struct lcd_config_s *pconf)
{
struct lcd_power_step_s *power_step;
- int index, i;
+ int index, i = 0;
/* mipi extern_init is special */
if (pconf->lcd_basic.lcd_type == LCD_MIPI) {
index = pconf->lcd_control.mipi_config->extern_init;
if (index < LCD_EXTERN_INDEX_INVALID)
- aml_lcd_extern_probe(dt_blob, index);
+ lcd_extern_probe(dt_addr, index);
}
- i = 0;
while (i < LCD_PWR_STEP_MAX) {
power_step = &pconf->lcd_power->power_on_step[i];
if (power_step->type >= LCD_POWER_TYPE_MAX)
break;
if (power_step->type == LCD_POWER_TYPE_EXTERN) {
- if (lcd_debug_print_flag) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
LCDPR("power_on: step %d: type=%d, index=%d\n",
i, power_step->type, power_step->index);
}
index = power_step->index;
if (index < LCD_EXTERN_INDEX_INVALID)
- aml_lcd_extern_probe(dt_blob, index);
+ lcd_extern_probe(dt_addr, index);
}
i++;
}
@@ -340,508 +440,844 @@
}
#endif
-static int lcd_init_load_from_dts(const void *dt_blob)
+static int lcd_init_load_from_dts(char *dt_addr, struct aml_lcd_drv_s *pdrv)
{
- struct lcd_config_s *pconf = aml_lcd_driver.lcd_config;
+#ifdef CONFIG_OF_LIBFDT
+ struct lcd_config_s *pconf = &pdrv->config;
int parent_offset;
- char *propdata, *p;
+ char *propdata, *p, snode[10];
const char *str;
- int i, temp;
+ unsigned int temp;
+ int i, j;
-/* Not use dts to control the backlight*/
-#ifdef CONFIG_NOT_DTS_CONTROL_BL
- aml_lcd_driver.bl_config->bl_key_valid = 0;
-#else
- /* check bl_key_valid */
- parent_offset = fdt_path_offset(dt_blob, "/backlight");
+ if (pdrv->index == 0)
+ sprintf(snode, "/lcd");
+ else
+ sprintf(snode, "/lcd%d", pdrv->index);
+ parent_offset = fdt_path_offset(dt_addr, snode);
if (parent_offset < 0) {
- LCDERR("not find /backlight node: %s\n", fdt_strerror(parent_offset));
- aml_lcd_driver.bl_config->bl_key_valid = 0;
- }
- propdata = (char *)fdt_getprop(dt_blob, parent_offset, "key_valid", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get key_valid\n");
- aml_lcd_driver.bl_config->bl_key_valid = 0;
- } else {
- aml_lcd_driver.bl_config->bl_key_valid = (unsigned char)(be32_to_cpup((u32*)propdata));
- }
-#endif
-
- parent_offset = fdt_path_offset(dt_blob, "/lcd");
- if (parent_offset < 0) {
- LCDERR("not find /lcd node: %s\n", fdt_strerror(parent_offset));
+ LCDERR("[%d]: not find %s node: %s\n",
+ pdrv->index, snode, fdt_strerror(parent_offset));
return -1;
}
+ sprintf(snode, "lcd%d", pdrv->index);
/* check lcd_mode & lcd_key_valid */
- propdata = (char *)fdt_getprop(dt_blob, parent_offset, "mode", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get mode\n");
+ propdata = (char *)fdt_getprop(dt_addr, parent_offset, "mode", NULL);
+ if (!propdata) {
+ LCDERR("[%d]: failed to get mode\n", pdrv->index);
return -1;
} else {
- pconf->lcd_mode = lcd_mode_str_to_mode(propdata);
+ pdrv->mode = lcd_mode_str_to_mode(propdata);
}
- str = propdata;
- propdata = (char *)fdt_getprop(dt_blob, parent_offset, "key_valid", NULL);
- if (propdata == NULL) {
- LCDERR("failed to get key_valid\n");
- pconf->lcd_key_valid = 0;
+ propdata = (char *)fdt_getprop(dt_addr, parent_offset, "key_valid", NULL);
+ if (!propdata) {
+ LCDERR("[%d]: failed to get key_valid\n", pdrv->index);
+ pdrv->key_valid = 0;
} else {
- pconf->lcd_key_valid = (unsigned char)(be32_to_cpup((u32*)propdata));
+ pdrv->key_valid = (unsigned char)(be32_to_cpup((u32*)propdata));
}
- LCDPR("detect mode: %s, key_valid: %d\n", str, pconf->lcd_key_valid);
/* check lcd_clk_path */
- propdata = (char *)fdt_getprop(dt_blob, parent_offset, "clk_path", NULL);
- if (propdata == NULL) {
- if (lcd_debug_print_flag)
- LCDPR("failed to get clk_path\n");
- pconf->lcd_clk_path = 0;
+ propdata = (char *)fdt_getprop(dt_addr, parent_offset, "clk_path", NULL);
+ if (!propdata) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("[%d]: failed to get clk_path\n", pdrv->index);
+ pdrv->clk_path = 0;
} else {
- pconf->lcd_clk_path = (unsigned char)(be32_to_cpup((u32*)propdata));
- LCDPR("detect lcd_clk_path: %d\n", pconf->lcd_clk_path);
+ pdrv->clk_path = (unsigned char)(be32_to_cpup((u32 *)propdata));
}
- str = env_get("lcd_clk_path");
- if (str) {
- temp = simple_strtoul(str, NULL, 10);
+ LCDPR("[%d]: detect mode: %s, key_valid: %d, clk_path: %d\n",
+ pdrv->index, lcd_mode_mode_to_str(pdrv->mode),
+ pdrv->key_valid, pdrv->clk_path);
+
+ temp = env_get_ulong("lcd_clk_path", 10, 0xffff);
+ if (temp != 0xffff) {
if (temp)
- pconf->lcd_clk_path = 1;
+ pdrv->clk_path = 1;
else
- pconf->lcd_clk_path = 0;
- LCDPR("lcd_clk_path flag set clk_path: %d\n", pconf->lcd_clk_path);
+ pdrv->clk_path = 0;
+ LCDPR("[%d]: lcd_clk_path flag set clk_path: %d\n",
+ pdrv->index, pdrv->clk_path);
}
i = 0;
- propdata = (char *)fdt_getprop(dt_blob, parent_offset, "lcd_cpu_gpio_names", NULL);
- if (propdata == NULL) {
- LCDPR("failed to get lcd_cpu_gpio_names\n");
+ propdata = (char *)fdt_getprop(dt_addr, parent_offset,
+ "lcd_cpu_gpio_names", NULL);
+ if (!propdata) {
+ LCDPR("[%d]: failed to get lcd_cpu_gpio_names\n", pdrv->index);
} else {
p = propdata;
while (i < LCD_CPU_GPIO_NUM_MAX) {
str = p;
if (strlen(str) == 0)
break;
- lcd_gpio_probe(str, i);
+ strcpy(pconf->power.cpu_gpio[i], str);
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL) {
+ LCDPR("[%d]: i=%d, gpio=%s\n",
+ pdrv->index, i, pconf->power.cpu_gpio[i]);
+ }
p += strlen(p) + 1;
i++;
}
}
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(pconf->power.cpu_gpio[j], "invalid");
+#endif
return 0;
}
-static int lcd_init_load_from_bsp(void)
+static int lcd_init_load_from_bsp(struct aml_lcd_drv_s *pdrv)
{
- struct lcd_config_s *pconf = aml_lcd_driver.lcd_config;
- int i, temp;
- char *str;
+ struct lcd_dft_config_s *dft_conf;
+ unsigned int temp;
+ char snode[10];
+ char (*lcd_gpio)[LCD_CPU_GPIO_NAME_MAX];
+ int i, j;
- /*pconf->lcd_key_valid = 0;
- aml_lcd_driver.bl_config->bl_key_valid = 0;*/
- LCDPR("detect mode: %s, key_valid: %d\n",
- lcd_mode_mode_to_str(pconf->lcd_mode), pconf->lcd_key_valid);
+ dft_conf = lcd_data->dft_conf[pdrv->index];
+ if (!dft_conf) {
+ LCDERR("%s: dft_conf is NULL\n", __func__);
+ return -1;
+ }
+ sprintf(snode, "lcd%d", pdrv->index);
+
+ pdrv->mode = dft_conf->mode;
+ pdrv->key_valid = dft_conf->key_valid;
+ pdrv->clk_path = dft_conf->clk_path;
+ LCDPR("[%d]: detect mode: %s, key_valid: %d, clk_path: %d\n",
+ pdrv->index, lcd_mode_mode_to_str(pdrv->mode),
+ pdrv->key_valid, pdrv->clk_path);
+
+ temp = env_get_ulong("lcd_clk_path", 10, 0xffff);
+ if (temp != 0xffff) {
+ if (temp)
+ pdrv->clk_path = 1;
+ else
+ pdrv->clk_path = 0;
+ LCDPR("[%d]: lcd_clk_path flag set clk_path: %d\n",
+ pdrv->index, pdrv->clk_path);
+ }
i = 0;
+ lcd_gpio = pdrv->data->dft_conf[pdrv->index]->lcd_gpio;
+ if (!lcd_gpio) {
+ LCDERR("[%d]: %s lcd_gpio is null\n", pdrv->index, __func__);
+ return -1;
+ }
while (i < LCD_CPU_GPIO_NUM_MAX) {
- if (strcmp(pconf->lcd_power->cpu_gpio[i], "invalid") == 0)
+ if (strcmp(lcd_gpio[i], "invalid") == 0)
break;
- lcd_gpio_probe(pconf->lcd_power->cpu_gpio[i], i);
+ strcpy(pdrv->config.power.cpu_gpio[i], lcd_gpio[i]);
i++;
}
-
- str = env_get("lcd_clk_path");
- if (str) {
- temp = simple_strtoul(str, NULL, 10);
- if (temp)
- pconf->lcd_clk_path = 1;
- else
- pconf->lcd_clk_path = 0;
- LCDPR("lcd_clk_path flag set clk_path: %d\n", pconf->lcd_clk_path);
- }
+ for (j = i; j < LCD_CPU_GPIO_NUM_MAX; j++)
+ strcpy(pdrv->config.power.cpu_gpio[j], "invalid");
return 0;
}
-static int lcd_config_probe(void)
+static int lcd_mode_init(struct aml_lcd_drv_s *pdrv)
{
- const void *dt_blob;
- int load_id = 0;
- char *str;
- int parent_offset;
- int ret;
+ int ret = -1;
- dt_blob = gd->fdt_blob;
- if (dt_blob == NULL) {
- LCDERR("dt_blob is null, load default lcd parameters\n");
- } else {
- ret = fdt_check_header(dt_blob);
- if (ret) {
- LCDERR("check dts: %s, load default lcd parameters\n",
- fdt_strerror(ret));
- } else {
- parent_offset = fdt_path_offset(dt_blob, "/lcd");
- if (parent_offset < 0) {
- LCDERR("not find /lcd node: %s\n",
- fdt_strerror(parent_offset));
- } else {
- load_id = 0x1;
- }
- }
+ switch (debug_ctrl.debug_lcd_mode) {
+ case 1:
+ LCDPR("[%d]: lcd_debug_mode: 1,tv\n", pdrv->index);
+ pdrv->mode = LCD_MODE_TV;
+ break;
+ case 2:
+ LCDPR("[%d]: lcd_debug_mode: 2,tablet\n", pdrv->index);
+ pdrv->mode = LCD_MODE_TABLET;
+ break;
+ default:
+ break;
}
- lcd_debug_load_flag = 0;
- str = env_get("lcd_debug_test");
- if (str == NULL)
- lcd_debug_load_flag = 0;
- else
- lcd_debug_load_flag = simple_strtoul(str, NULL, 10);
- if (lcd_debug_load_flag) {
- load_id = 0x0;
- LCDPR("lcd_debug_load_flag: %d\n", lcd_debug_load_flag);
- }
-
- /* default setting */
- aml_lcd_driver.lcd_config->retry_enable_flag = 0;
- aml_lcd_driver.lcd_config->retry_enable_cnt = 0;
-
- if (load_id & 0x1) {
- ret = lcd_init_load_from_dts(dt_blob);
- if (ret)
- return -1;
- if (aml_lcd_driver.unifykey_test_flag) {
- aml_lcd_driver.bl_config->bl_key_valid = 1;
- aml_lcd_driver.lcd_config->lcd_key_valid = 1;
- LCDPR("force bl_key_valid & lcd_key_valid to 1\n");
- }
- if (aml_lcd_driver.lcd_config->lcd_key_valid) {
- ret = aml_lcd_unifykey_check("lcd");
- if (ret == 0) {
- LCDPR("load config from unifykey\n");
- load_id |= 0x10;
- } else {
- LCDPR("load config from dts\n");
- }
- } else {
- LCDPR("load config from dts\n");
- }
- } else {
- ret = lcd_init_load_from_bsp();
- if (ret)
- return -1;
- if (aml_lcd_driver.unifykey_test_flag) {
- aml_lcd_driver.bl_config->bl_key_valid = 1;
- aml_lcd_driver.lcd_config->lcd_key_valid = 1;
- LCDPR("force bl_key_valid & lcd_key_valid to 1\n");
- }
- if (aml_lcd_driver.lcd_config->lcd_key_valid) {
- ret = aml_lcd_unifykey_check("lcd");
- if (ret == 0) {
- LCDPR("load lcd_config from unifykey\n");
- load_id |= 0x10;
- } else {
- LCDPR("load lcd_config from bsp\n");
- }
- } else {
- LCDPR("load config from bsp\n");
- }
- }
-
- lcd_clk_config_probe();
-
- /* load lcd config */
- switch (aml_lcd_driver.lcd_config->lcd_mode) {
+ switch (pdrv->mode) {
#ifdef CONFIG_AML_LCD_TV
case LCD_MODE_TV:
- ret = get_lcd_tv_config(dt_blob, load_id);
+ ret = lcd_mode_tv_init(pdrv);
break;
#endif
#ifdef CONFIG_AML_LCD_TABLET
case LCD_MODE_TABLET:
- ret = get_lcd_tablet_config(dt_blob, load_id);
+ ret = lcd_mode_tablet_init(pdrv);
break;
#endif
default:
- LCDERR("invalid lcd mode: %d\n", aml_lcd_driver.lcd_config->lcd_mode);
+ LCDERR("[%d]: invalid lcd mode: %d\n", pdrv->index, pdrv->mode);
break;
}
+
if (ret) {
- aml_lcd_driver.config_check = NULL;
- LCDERR("invalid lcd config\n");
+ pdrv->config_check = NULL;
+ LCDERR("[%d]: %s: invalid config\n", pdrv->index, __func__);
return -1;
}
- if (aml_lcd_driver.lcd_config->lcd_basic.lcd_type == LCD_VBYONE)
- lcd_vbyone_filter_env_init(aml_lcd_driver.lcd_config);
-#if 0
- if (aml_lcd_driver.chip_type == LCD_CHIP_TXHD)
- lcd_tcon_probe(dt_blob, &aml_lcd_driver, load_id);
-#endif
-#ifdef CONFIG_AML_LCD_EXTERN
- lcd_extern_load_config(dt_blob, aml_lcd_driver.lcd_config);
-#endif
+ return 0;
+}
- /* load bl config */
- if (aml_lcd_driver.bl_config->bl_key_valid) {
- ret = aml_lcd_unifykey_check("backlight");
- if (ret == 0) {
- LCDPR("load backlight_config from unifykey\n");
- load_id |= 0x10;
+static unsigned int lcd_get_drv_cnt_flag_from_dts(char *dt_addr)
+{
+#ifdef CONFIG_OF_LIBFDT
+ int parent_offset;
+ char str[10];
+ unsigned int i, flag = 0;
+
+ for (i = 0; i < lcd_data->drv_max; i++) {
+ if (i == 0)
+ sprintf(str, "/lcd");
+ else
+ sprintf(str, "/lcd%d", i);
+
+ parent_offset = fdt_path_offset(dt_addr, str);
+ if (parent_offset < 0) {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("not find %s node\n", str);
} else {
- load_id &= ~(0x10);
+ flag |= (1 << i);
+ }
+ }
+
+ return flag;
+#else
+ return 0;
+#endif
+}
+
+static unsigned int lcd_get_drv_cnt_flag_from_bsp(void)
+{
+ unsigned int i, flag = 0;
+
+ for (i = 0; i < lcd_data->drv_max; i++) {
+ if (!lcd_data->dft_conf[i])
+ continue;
+ if (lcd_data->dft_conf[i]->ext_lcd) {
+ flag |= (1 << i);
+ } else {
+ if (lcd_debug_print_flag & LCD_DBG_PR_NORMAL)
+ LCDPR("not find ext_lcd[%d]\n", i);
+ }
+ }
+
+ return flag;
+}
+
+static struct aml_lcd_drv_s *lcd_driver_add(int index)
+{
+ struct aml_lcd_drv_s *pdrv;
+
+ if (index >= lcd_data->drv_max) {
+ LCDERR("%s: invalid index: %d\n", __func__, index);
+ return NULL;
+ }
+ if (!lcd_data->dft_conf[index]) {
+ LCDERR("%s: no lcd%d dft_conf\n", __func__, index);
+ return NULL;
+ }
+ if (!lcd_driver[index]) {
+ lcd_driver[index] = (struct aml_lcd_drv_s *)
+ malloc(sizeof(struct aml_lcd_drv_s));
+ if (!lcd_driver[index]) {
+ LCDERR("%s: Not enough memory\n", __func__);
+ return NULL;
+ }
+ }
+ pdrv = lcd_driver[index];
+ memset(pdrv, 0, sizeof(struct aml_lcd_drv_s));
+ pdrv->index = index;
+
+ /* default config */
+ pdrv->data = lcd_data;
+ pdrv->config.basic.lcd_type = LCD_TYPE_MAX;
+ pdrv->config.power.power_on_step[0].type = LCD_POWER_TYPE_MAX;
+ pdrv->config.power.power_off_step[0].type = LCD_POWER_TYPE_MAX;
+ pdrv->config.pinmux_set[0][0] = LCD_PINMUX_END;
+ pdrv->config.pinmux_set[0][1] = 0x0;
+ pdrv->config.pinmux_clr[0][0] = LCD_PINMUX_END;
+ pdrv->config.pinmux_clr[0][1] = 0x0;
+ pdrv->config.backlight_index = 0xff;
+
+ /* default setting */
+ pdrv->config.retry_enable_flag = 0;
+ pdrv->config.retry_enable_cnt = 0;
+
+ return pdrv;
+}
+
+static int lcd_driver_remove(int index)
+{
+ if (index >= lcd_data->drv_max)
+ return 0;
+
+ if (!lcd_driver[index])
+ return 0;
+
+ free(lcd_driver[index]);
+ lcd_driver[index] = NULL;
+
+ return 0;
+}
+
+static void lcd_update_ctrl_bootargs(struct aml_lcd_drv_s *pdrv)
+{
+ unsigned int val = 0;
+ char env_str[15], ctrl_str[20];
+
+ pdrv->boot_ctrl.lcd_type = pdrv->config.basic.lcd_type;
+ pdrv->boot_ctrl.lcd_bits = pdrv->config.basic.lcd_bits;
+ switch (pdrv->config.basic.lcd_type) {
+ case LCD_TTL:
+ pdrv->boot_ctrl.advanced_flag =
+ pdrv->config.control.ttl_cfg.sync_valid;
+ break;
+ case LCD_P2P:
+ pdrv->boot_ctrl.advanced_flag =
+ pdrv->config.control.p2p_cfg.p2p_type;
+ break;
+ default:
+ break;
+ }
+ pdrv->boot_ctrl.init_level = env_get_ulong("lcd_init_level", 10, 0);
+
+ /*
+ *bit[31:20]: reserved
+ *bit[19:18]: lcd_init_level
+ *bit[17:16]: reserved
+ *bit[15:8]: advanced flag(p2p_type when lcd_type=p2p)
+ *bit[7:4]: lcd bits
+ *bit[3:0]: lcd_type
+ */
+ val |= (pdrv->boot_ctrl.lcd_type & 0xf);
+ val |= (pdrv->boot_ctrl.lcd_bits & 0xf) << 4;
+ val |= (pdrv->boot_ctrl.advanced_flag & 0xff) << 8;
+ val |= (pdrv->boot_ctrl.init_level & 0x3) << 18;
+ sprintf(ctrl_str, "0x%08x", val);
+
+ if (pdrv->index == 0)
+ sprintf(env_str, "lcd_ctrl");
+ else
+ sprintf(env_str, "lcd%d_ctrl", pdrv->index);
+ env_set(env_str, ctrl_str);
+}
+
+static void lcd_update_debug_bootargs(void)
+{
+ unsigned int val = 0;
+ char ctrl_str[20];
+
+ debug_ctrl.debug_print_flag = lcd_debug_print_flag;
+ debug_ctrl.debug_test_pattern = lcd_debug_test;
+ debug_ctrl.debug_para_source = env_get_ulong("lcd_debug_para", 10, 0);
+ debug_ctrl.debug_lcd_mode = env_get_ulong("lcd_debug_mode", 10, 0);
+
+ /*
+ *bit[31:30]: lcd mode(0=normal, 1=tv; 2=tablet, 3=TBD)
+ *bit[29:28]: lcd debug para source(0=normal, 1=dts, 2=unifykey,
+ * 3=bsp for uboot)
+ *bit[27:16]: reserved
+ *bit[15:8]: lcd test pattern
+ *bit[7:0]: lcd debug print flag
+ */
+ val |= (debug_ctrl.debug_print_flag & 0xff);
+ val |= (debug_ctrl.debug_test_pattern & 0xff) << 8;
+ val |= (debug_ctrl.debug_para_source & 0x3) << 28;
+ val |= (debug_ctrl.debug_lcd_mode & 0x3) << 30;
+ sprintf(ctrl_str, "0x%08x", val);
+ env_set("lcd_debug", ctrl_str);
+}
+
+static int lcd_config_probe(void)
+{
+ int load_id = 0, load_id_lcd;
+ char *dt_addr = NULL;
+ struct aml_lcd_drv_s *pdrv;
+ unsigned int drv_cnt_flag;
+ int i, ret;
+
+#ifdef CONFIG_DTB_MEM_ADDR
+ dt_addr = (char *)CONFIG_DTB_MEM_ADDR;
+#else
+ dt_addr = (char *)0x01000000;
+#endif
+
+#ifdef CONFIG_OF_LIBFDT
+ if (fdt_check_header(dt_addr) < 0) {
+ LCDERR("check dts: %s, load default lcd parameters\n",
+ fdt_strerror(fdt_check_header(dt_addr)));
+ } else {
+ load_id = 0x1;
+ }
+#endif
+
+ switch (debug_ctrl.debug_para_source) {
+ case 1:
+ LCDPR("lcd_debug_para: 1,dts\n");
+ load_id = 0x1;
+ break;
+ case 2:
+ LCDPR("lcd_debug_para: 2,unifykey\n");
+ load_id = 0x11;
+ break;
+ case 3:
+ LCDPR("lcd_debug_para: 3,bsp\n");
+ load_id = 0x0;
+ break;
+ default:
+ break;
+ }
+
+ load_id_lcd = load_id;
+ if (load_id & 0x1) {
+ drv_cnt_flag = lcd_get_drv_cnt_flag_from_dts(dt_addr);
+ if (drv_cnt_flag == 0) {
+ LCDPR("not find /lcd node\n");
+ drv_cnt_flag = lcd_get_drv_cnt_flag_from_bsp();
+ load_id_lcd = 0x0;
}
} else {
- load_id &= ~(0x10);
- }
- bl_config_load(dt_blob, load_id);
-
- if (lcd_debug_print_flag) {
- if (aml_lcd_driver.lcd_config->lcd_basic.lcd_type == LCD_VBYONE)
- lcd_vbyone_filter_flag_print(aml_lcd_driver.lcd_config);
+ drv_cnt_flag = lcd_get_drv_cnt_flag_from_bsp();
}
- lcd_debug_probe(&aml_lcd_driver);
+ if (load_id_lcd & 0x1) {
+ for (i = 0; i < lcd_data->drv_max; i++) {
+ if ((drv_cnt_flag & (1 << i)) == 0)
+ continue;
+ pdrv = lcd_driver_add(i);
+ if (!pdrv)
+ continue;
+
+ ret = lcd_init_load_from_dts(dt_addr, pdrv);
+ if (ret) {
+ lcd_driver_remove(i);
+ continue;
+ }
+ lcd_clk_config_probe(pdrv);
+ ret = lcd_get_config(dt_addr, load_id_lcd, pdrv);
+ if (ret) {
+ lcd_driver_remove(i);
+ continue;
+ }
+ lcd_phy_probe(pdrv);
+ lcd_debug_probe(pdrv);
+ lcd_update_ctrl_bootargs(pdrv);
+ lcd_mode_init(pdrv);
+ }
+ } else {
+ for (i = 0; i < lcd_data->drv_max; i++) {
+ if ((drv_cnt_flag & (1 << i)) == 0)
+ continue;
+ pdrv = lcd_driver_add(i);
+ if (!pdrv)
+ continue;
+
+ ret = lcd_init_load_from_bsp(pdrv);
+ if (ret) {
+ lcd_driver_remove(i);
+ continue;
+ }
+ lcd_clk_config_probe(pdrv);
+ ret = lcd_get_config(dt_addr, load_id_lcd, pdrv);
+ if (ret) {
+ lcd_driver_remove(i);
+ continue;
+ }
+ lcd_phy_probe(pdrv);
+ lcd_debug_probe(pdrv);
+ lcd_update_ctrl_bootargs(pdrv);
+ lcd_mode_init(pdrv);
+ }
+ }
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ lcd_extern_load_config(dt_addr, load_id);
+#endif
+#ifdef CONFIG_AML_LCD_BACKLIGHT
+ aml_bl_probe(dt_addr, load_id);
+#endif
return 0;
}
int lcd_probe(void)
{
-#ifdef LCD_DEBUG_INFO
- lcd_debug_print_flag = 1;
-#else
- char *str;
+ int ret = 0;
- str = env_get("lcd_debug_print");
- if (str == NULL) {
- lcd_debug_print_flag = 0;
- } else {
- lcd_debug_print_flag = simple_strtoul(str, NULL, 10);
- LCDPR("lcd_debug_print flag: %d\n", lcd_debug_print_flag);
- }
+ lcd_debug_print_flag = env_get_ulong("lcd_debug_print", 16, 0);
+ LCDPR("lcd_debug_print flag: %d\n", lcd_debug_print_flag);
+
+ lcd_debug_test = env_get_ulong("lcd_debug_test", 10, 0);
+
+ debug_ctrl.debug_print_flag = lcd_debug_print_flag;
+ debug_ctrl.debug_test_pattern = lcd_debug_test;
+ debug_ctrl.debug_para_source = env_get_ulong("lcd_debug_para", 10, 0);
+ debug_ctrl.debug_lcd_mode = env_get_ulong("lcd_debug_mode", 10, 0);
+
+#ifdef CONFIG_AML_LCD_EXTERN
+ lcd_extern_init();
+#endif
+#ifdef CONFIG_AML_LCD_BACKLIGHT
+ aml_bl_init();
#endif
lcd_chip_detect();
+ if (!lcd_data) {
+ LCDERR("%s: invalid lcd data\n", __func__);
+ return -1;
+ }
lcd_config_bsp_init();
- lcd_config_probe();
+ lcd_phy_config_init(lcd_data);
+ ret = lcd_config_probe();
+ if (ret)
+ return -1;
+
+ lcd_update_debug_bootargs();
return 0;
}
int lcd_remove(void)
{
+ int i;
+
+ if (!lcd_data)
+ return 0;
+
+ aml_bl_remove();
#ifdef CONFIG_AML_LCD_EXTERN
- aml_lcd_extern_remove();
+ lcd_extern_remove();
#endif
- return 0;
-}
-
-#define LCD_WAIT_VSYNC_TIMEOUT 50000
-void lcd_wait_vsync(void)
-{
- int line_cnt, line_cnt_previous;
- int i = 0;
-
- line_cnt = 0x1fff;
- line_cnt_previous = lcd_vcbus_getb(ENCL_INFO_READ, 16, 13);
- while (i++ < LCD_WAIT_VSYNC_TIMEOUT) {
- line_cnt = lcd_vcbus_getb(ENCL_INFO_READ, 16, 13);
- if (line_cnt < line_cnt_previous)
- break;
- line_cnt_previous = line_cnt;
- udelay(2);
+ for (i = 0; i < LCD_MAX_DRV; i++) {
+ if (lcd_driver[i]) {
+ free(lcd_driver[i]);
+ lcd_driver[i] = NULL;
+ }
}
- /*LCDPR("line_cnt=%d, line_cnt_previous=%d, i=%d\n",
- * line_cnt, line_cnt_previous, i);
- */
+
+ return 0;
}
/* ********************************************** *
lcd driver API
* ********************************************** */
-static int lcd_outputmode_check(char *mode)
+int aml_lcd_driver_probe(int index)
{
- if (aml_lcd_driver.outputmode_check)
- return aml_lcd_driver.outputmode_check(mode);
-
- LCDERR("invalid lcd config\n");
- return -1;
+ return lcd_probe();
}
-static void lcd_enable(char *mode)
+/***********************************************
+ * use for vout
+ ************************************************/
+void aml_lcd_driver_list_support_mode(void)
{
- if (lcd_check_valid())
- return;
- if (aml_lcd_driver.lcd_status)
- LCDPR("already enabled\n");
- else
- lcd_module_enable(mode);
-}
+ struct aml_lcd_drv_s *pdrv;
+ int index;
-static void lcd_disable(void)
-{
- if (lcd_check_valid())
- return;
- if (aml_lcd_driver.lcd_status)
- lcd_module_disable();
- else
- LCDPR("already disabled\n");
-}
+ for (index = 0; index < LCD_MAX_DRV; index++) {
+ pdrv = lcd_driver_check_valid(index);
+ if (!pdrv)
+ continue;
-static void lcd_set_ss(int level)
-{
- struct aml_lcd_drv_s *lcd_drv = aml_lcd_get_driver();
-
- if (lcd_check_valid())
- return;
- if (aml_lcd_driver.lcd_status) {
- lcd_drv->lcd_config->lcd_timing.ss_level = level;
- lcd_set_spread_spectrum(level);
- } else {
- LCDPR("already disabled\n");
+ if (pdrv->list_support_mode)
+ pdrv->list_support_mode(&pdrv->config);
}
}
-static char *lcd_get_ss(void)
+/***********************************************
+ * use for vout
+ * parameters: mode, such as panel, panel2, 1080p60hz...
+ * frac, 1=59.94hz
+ * return: viu_mux
+ ************************************************/
+unsigned int aml_lcd_driver_outputmode_check(char *mode, unsigned int frac)
{
- char *str = "invalid";
+ struct aml_lcd_drv_s *pdrv;
+ unsigned int viu_mux = VIU_MUX_MAX;
+ int index, ret;
- if (lcd_check_valid())
- return str;
- if (aml_lcd_driver.lcd_status)
- str = lcd_get_spread_spectrum();
- else
- LCDPR("already disabled\n");
+ for (index = 0; index < LCD_MAX_DRV; index++) {
+ pdrv = lcd_driver_check_valid(index);
+ if (!pdrv)
+ continue;
- return str;
+ if (pdrv->outputmode_check) {
+ ret = pdrv->outputmode_check(pdrv, mode, frac);
+ if (ret == 0) {
+ viu_mux = ((pdrv->index << 4) | VIU_MUX_ENCL);
+ break;
+ }
+ }
+ }
+
+ return viu_mux;
}
-static void lcd_test(int num)
+void aml_lcd_driver_prepare(int index, char *mode, unsigned int frac)
{
- if (lcd_check_valid())
+ struct aml_lcd_drv_s *pdrv;
+
+ pdrv = lcd_driver_check_valid(index);
+ if (!pdrv)
return;
- if (aml_lcd_driver.lcd_status)
- lcd_debug_test(num);
- else
- LCDPR("already disabled\n");
-}
-static void lcd_clk_info(void)
-{
- if (lcd_check_valid())
+ if (pdrv->status & LCD_STATUS_ENCL_ON) {
+ LCDPR("[%d]: already enabled\n", pdrv->index);
return;
- lcd_clk_config_print();
+ }
+
+ lcd_module_prepare(pdrv, mode, frac);
}
-static void lcd_info(void)
+void aml_lcd_driver_enable(int index, char *mode, unsigned int frac)
{
- if (lcd_check_valid())
+ struct aml_lcd_drv_s *pdrv;
+
+ pdrv = lcd_driver_check_valid(index);
+ if (!pdrv)
return;
- lcd_info_print();
-}
-static void lcd_reg_info(void)
-{
- if (lcd_check_valid())
+ if (pdrv->status & LCD_STATUS_IF_ON) {
+ LCDPR("[%d]: already enabled\n", pdrv->index);
return;
- lcd_reg_print();
+ }
+
+ lcd_module_enable(pdrv, mode, frac);
}
-static void lcd_tcon_reg_info(void)
+void aml_lcd_driver_disable(int index)
{
- if (lcd_check_valid())
+ struct aml_lcd_drv_s *pdrv;
+
+ pdrv = lcd_driver_check_valid(index);
+ if (!pdrv)
return;
- lcd_tcon_reg_readback_print();
-}
-static void lcd_tcon_table_info(void)
-{
- if (lcd_check_valid())
+ if ((pdrv->status & LCD_STATUS_ENCL_ON) == 0) {
+ LCDPR("[%d]: already disabled\n", pdrv->index);
return;
- lcd_tcon_reg_table_print();
+ }
+
+ lcd_module_disable(pdrv);
}
-static void lcd_key_test(void)
+void aml_lcd_driver_set_ss(int index, unsigned int level, unsigned int freq,
+ unsigned int mode)
{
- if (aml_lcd_driver.unifykey_test_flag) {
- aml_lcd_unifykey_test();
- lcd_config_probe();
- } else {
- printf("lcd unifykey test disabled\n");
+ struct aml_lcd_drv_s *pdrv;
+ unsigned int temp;
+ int ret;
+
+ pdrv = lcd_driver_check_valid(index);
+ if (!pdrv)
+ return;
+
+ if ((pdrv->status & LCD_STATUS_ENCL_ON) == 0) {
+ LCDPR("[%d]: already disabled\n", pdrv->index);
+ return;
+ }
+
+ temp = pdrv->config.timing.ss_level;
+ ret = lcd_set_ss(pdrv, level, freq, mode);
+ if (ret == 0) {
+ if (level < 0xff) {
+ temp &= ~(0xff);
+ temp |= level;
+ pdrv->config.timing.ss_level = temp;
+ }
+ if (freq < 0xff) {
+ temp &= ~((0xf << LCD_CLK_SS_BIT_FREQ) << 8);
+ temp |= ((freq << LCD_CLK_SS_BIT_FREQ) << 8);
+ pdrv->config.timing.ss_level = temp;
+ }
+ if (mode < 0xff) {
+ temp &= ~((0xf << LCD_CLK_SS_BIT_MODE) << 8);
+ temp |= ((mode << LCD_CLK_SS_BIT_MODE) << 8);
+ pdrv->config.timing.ss_level = temp;
+ }
}
}
-static void lcd_key_tcon_test(void)
+void aml_lcd_driver_get_ss(int index)
{
- if (aml_lcd_driver.unifykey_test_flag) {
- aml_lcd_unifykey_tcon_test(1080);
- lcd_config_probe();
- } else {
- printf("lcd unifykey test disabled\n");
+ struct aml_lcd_drv_s *pdrv;
+
+ pdrv = lcd_driver_check_valid(index);
+ if (!pdrv)
+ return;
+
+ if ((pdrv->status & LCD_STATUS_ENCL_ON) == 0) {
+ LCDPR("[%d]: already disabled\n", pdrv->index);
+ return;
}
+
+ lcd_get_ss(pdrv);
}
-static void lcd_key_dump(void)
+void aml_lcd_driver_test(int index, int num)
{
- int flag = LCD_UKEY_DEBUG_NORMAL;
-#if 0
- switch (aml_lcd_driver.chip_type) {
- case LCD_CHIP_TXHD:
- flag |= LCD_UKEY_DEBUG_TCON;
- break;
- default:
- break;
+ struct aml_lcd_drv_s *pdrv;
+
+ pdrv = lcd_driver_check_valid(index);
+ if (!pdrv)
+ return;
+
+ if (num == 10) {
+ lcd_display_init_test(pdrv);
+ return;
+ } else if (num == 20) {
+ lcd_display_init_reg_dump(pdrv);
+ return;
}
-#endif
- aml_lcd_unifykey_dump(flag);
+
+ if ((pdrv->status & LCD_STATUS_IF_ON) == 0) {
+ LCDPR("[%d]: already disabled\n", pdrv->index);
+ return;
+ }
+
+ aml_lcd_debug_test(pdrv, num);
}
-static void lcd_extern_info(void)
+void aml_lcd_driver_clk_info(int index)
{
-#ifdef CONFIG_AML_LCD_EXTERN
- struct aml_lcd_extern_driver_s *ext_drv;
+ struct aml_lcd_drv_s *pdrv;
- ext_drv = aml_lcd_extern_get_driver();
- if (ext_drv)
- ext_drv->info_print();
-#else
- printf("lcd_extern is not support\n");
+ pdrv = lcd_driver_check_valid(index);
+ if (!pdrv)
+ return;
+
+ lcd_clk_config_print(pdrv);
+}
+
+void aml_lcd_driver_info(int index)
+{
+ struct aml_lcd_drv_s *pdrv;
+
+ pdrv = lcd_driver_check_valid(index);
+ if (!pdrv)
+ return;
+
+ lcd_info_print(pdrv);
+}
+
+void aml_lcd_driver_reg_info(int index)
+{
+ struct aml_lcd_drv_s *pdrv;
+
+ pdrv = lcd_driver_check_valid(index);
+ if (!pdrv)
+ return;
+
+ lcd_reg_print(pdrv);
+}
+
+void aml_lcd_vbyone_rst(int index)
+{
+ struct aml_lcd_drv_s *pdrv;
+
+ pdrv = lcd_driver_check_valid(index);
+ if (!pdrv)
+ return;
+
+ lcd_vbyone_rst(pdrv);
+}
+
+void aml_lcd_vbyone_cdr(int index)
+{
+ struct aml_lcd_drv_s *pdrv;
+
+ pdrv = lcd_driver_check_valid(index);
+ if (!pdrv)
+ return;
+
+ lcd_vbyone_cdr(pdrv);
+}
+
+void aml_lcd_driver_bl_on(int index)
+{
+ struct aml_lcd_drv_s *pdrv;
+
+ pdrv = lcd_driver_check_valid(index);
+ if (!pdrv)
+ return;
+#ifdef CONFIG_AML_LCD_BACKLIGHT
+ aml_bl_driver_enable(pdrv->index);
#endif
}
-static struct aml_lcd_drv_s aml_lcd_driver = {
- .lcd_status = 0,
- .lcd_config = &lcd_config_dft,
- .bl_config = &bl_config_dft,
- .config_check = NULL,
- .lcd_probe = lcd_probe,
- .lcd_outputmode_check = lcd_outputmode_check,
- .lcd_enable = lcd_enable,
- .lcd_disable = lcd_disable,
- .lcd_set_ss = lcd_set_ss,
- .lcd_get_ss = lcd_get_ss,
- .lcd_test = lcd_test,
- .lcd_clk = lcd_clk_info,
- .lcd_info = lcd_info,
- .lcd_reg = lcd_reg_info,
- .lcd_tcon_reg = lcd_tcon_reg_info,
- .lcd_tcon_table = lcd_tcon_table_info,
- .bl_power_ctrl = bl_power_ctrl,
- .bl_set_level = bl_set_level,
- .bl_get_level = bl_get_level,
- .bl_config_print = bl_config_print,
- .unifykey_test_flag = 0, /* default disable unifykey test */
- .unifykey_test = lcd_key_test,
- .unifykey_tcon_test = lcd_key_tcon_test,
- .unifykey_dump = lcd_key_dump,
- .lcd_extern_info = lcd_extern_info,
-
- /* for factory test */
- .factory_lcd_power_on_step = NULL,
- .factory_bl_power_on_delay = -1,
-};
-
-struct aml_lcd_drv_s *aml_lcd_get_driver(void)
+void aml_lcd_driver_bl_off(int index)
{
- return &aml_lcd_driver;
+ struct aml_lcd_drv_s *pdrv;
+
+ pdrv = lcd_driver_check_valid(index);
+ if (!pdrv)
+ return;
+#ifdef CONFIG_AML_LCD_BACKLIGHT
+ aml_bl_driver_disable(pdrv->index);
+#endif
+}
+
+void aml_lcd_driver_set_bl_level(int index, int level)
+{
+ struct aml_lcd_drv_s *pdrv;
+
+ pdrv = lcd_driver_check_valid(index);
+ if (!pdrv)
+ return;
+#ifdef CONFIG_AML_LCD_BACKLIGHT
+ aml_bl_set_level(pdrv->index, level);
+#endif
+}
+
+unsigned int aml_lcd_driver_get_bl_level(int index)
+{
+ struct aml_lcd_drv_s *pdrv;
+
+ pdrv = lcd_driver_check_valid(index);
+ if (!pdrv)
+ return 0;
+#ifdef CONFIG_AML_LCD_BACKLIGHT
+ return aml_bl_get_level(pdrv->index);
+#endif
+ return 0;
+}
+
+void aml_lcd_driver_bl_config_print(int index)
+{
+ struct aml_lcd_drv_s *pdrv;
+
+ pdrv = lcd_driver_check_valid(index);
+ if (!pdrv)
+ return;
+#ifdef CONFIG_AML_LCD_BACKLIGHT
+ aml_bl_config_print(pdrv->index);
+#endif
+}
+
+int aml_lcd_driver_prbs(int index, unsigned int s, unsigned int mode_flag)
+{
+ struct aml_lcd_drv_s *pdrv;
+
+ pdrv = lcd_driver_check_valid(index);
+ if (!pdrv)
+ return 0;
+
+ return lcd_prbs_test(pdrv, s, mode_flag);
+}
+
+void aml_lcd_driver_unifykey_dump(int index, unsigned int flag)
+{
+ unsigned int key_flag = LCD_UKEY_DEBUG_NORMAL;
+
+ if (flag & (1 << 0)) {
+ key_flag = LCD_UKEY_DEBUG_NORMAL;
+ } else if (flag & (1 << 1)) {
+#ifdef CONFIG_AML_LCD_TCON
+ key_flag = (LCD_UKEY_DEBUG_TCON | LCD_UKEY_TCON_SIZE_NEW);
+#endif
+ }
+ lcd_unifykey_dump(index, key_flag);
}
diff --git a/drivers/amlogic/media/vout/vout.c b/drivers/amlogic/media/vout/vout.c
index 18c450d..a4b9c4c 100644
--- a/drivers/amlogic/media/vout/vout.c
+++ b/drivers/amlogic/media/vout/vout.c
@@ -1,32 +1,19 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/amlogic/media/vout/vout.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
-
#include <common.h>
#include <asm/arch/io.h>
#include <asm/arch/secure_apb.h>
+#include <amlogic/cpu_id.h>
+#include <amlogic/media/vpp/vpp.h>
#include <amlogic/media/vout/aml_vmode.h>
#include <amlogic/media/vout/aml_vout.h>
#ifdef CONFIG_AML_LCD
#include <amlogic/media/vout/lcd/aml_lcd.h>
#endif
+#include "vout.h"
#define VOUT_LOG_DBG 0
#define VOUT_LOG_TAG "[VOUT]"
@@ -37,27 +24,49 @@
vout_log("%s:%d\n", __func__, __LINE__); \
} while (0)
-#define REG_OFFSET_VCBUS(reg) ((reg << 2))
-#define REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg))
-
static int g_vmode = -1;
+static struct vout_conf_s *vout_conf;
+static int vout_conf_check(void);
+#include "vout_reg.h"
-typedef struct vout_set_s {
- char *name;
- int mode;
- ulong width;
- ulong height;
- ulong field_height;
-} vout_set_t;
+static const struct vout_set_s vout_sets_lcd[] = {
+ { /* VMODE_LCD */
+ .name = "panel",
+ .mode = VMODE_LCD,
+ .width = 1920,
+ .height = 1080,
+ .field_height = 1080,
+ .viu_color_fmt = VPP_CM_RGB,
+ .viu_mux = VIU_MUX_ENCL,
+ },
+ { /* VMODE_LCD */
+ .name = "panel1",
+ .mode = VMODE_LCD,
+ .width = 1920,
+ .height = 1080,
+ .field_height = 1080,
+ .viu_color_fmt = VPP_CM_RGB,
+ .viu_mux = (1 << 4) | VIU_MUX_ENCL,
+ },{ /* VMODE_LCD */
+ .name = "panel2",
+ .mode = VMODE_LCD,
+ .width = 1920,
+ .height = 1080,
+ .field_height = 1080,
+ .viu_color_fmt = VPP_CM_RGB,
+ .viu_mux = (2 << 4) | VIU_MUX_ENCL,
+ }
+};
-
-static const vout_set_t vout_sets[] = {
+static const struct vout_set_s vout_sets_dft[] = {
{ /* VMODE_480I */
.name = "480i",
.mode = VMODE_480I,
.width = 720,
.height = 480,
.field_height = 240,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCI,
},
{ /* VMODE_480CVBS*/
.name = "480cvbs",
@@ -65,6 +74,8 @@
.width = 720,
.height = 480,
.field_height = 240,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCI,
},
{ /* VMODE_480P */
.name = "480p",
@@ -72,6 +83,8 @@
.width = 720,
.height = 480,
.field_height = 480,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_576I */
.name = "576i",
@@ -79,6 +92,8 @@
.width = 720,
.height = 576,
.field_height = 288,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCI,
},
{ /* VMODE_576I */
.name = "576cvbs",
@@ -86,6 +101,8 @@
.width = 720,
.height = 576,
.field_height = 288,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCI,
},
{ /* VMODE_576P */
.name = "576p",
@@ -93,6 +110,8 @@
.width = 720,
.height = 576,
.field_height = 576,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_720P */
.name = "720p",
@@ -100,6 +119,8 @@
.width = 1280,
.height = 720,
.field_height = 720,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_768P */
.name = "768p",
@@ -107,6 +128,8 @@
.width = 1366,
.height = 768,
.field_height = 768,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_1080I */
.name = "1080i",
@@ -114,6 +137,8 @@
.width = 1920,
.height = 1080,
.field_height = 540,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_1080P */
.name = "1080p",
@@ -121,6 +146,8 @@
.width = 1920,
.height = 1080,
.field_height = 1080,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_4K2K_60HZ */
.name = "2160p",
@@ -128,6 +155,8 @@
.width = 3840,
.height = 2160,
.field_height = 2160,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_4K2K_SMPTE */
.name = "smpte",
@@ -135,6 +164,8 @@
.width = 4096,
.height = 2160,
.field_height = 2160,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_vga */
.name = "vga",
@@ -142,6 +173,8 @@
.width = 640,
.height = 480,
.field_height = 480,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_SVGA */
.name = "svga",
@@ -149,6 +182,8 @@
.width = 800,
.height = 600,
.field_height = 600,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_XGA */
.name = "xga",
@@ -156,6 +191,8 @@
.width = 1024,
.height = 768,
.field_height = 768,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_sxga */
.name = "sxga",
@@ -163,6 +200,8 @@
.width = 1280,
.height = 1024,
.field_height = 1024,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_wsxga */
.name = "wsxga",
@@ -170,6 +209,8 @@
.width = 1440,
.height = 900,
.field_height = 900,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_fhdvga */
.name = "fhdvga",
@@ -177,158 +218,201 @@
.width = 1920,
.height = 1080,
.field_height = 1080,
- },
- { /* VMODE_LCD */
- .name = "panel",
- .mode = VMODE_LCD,
- .width = 1920,
- .height = 1080,
- .field_height = 1080,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_640x480p60hz */
.name = "640x480p60hz",
.mode = VMODE_640x480p60hz,
.width = 640,
.height = 480,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_800x480p60hz */
.name = "800x480p60hz",
.mode = VMODE_800x480p60hz,
.width = 800,
.height = 480,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_800x600p60hz */
.name = "800x600p60hz",
.mode = VMODE_800x600p60hz,
.width = 800,
.height = 600,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_852x480p60hz */
.name = "852x480p60hz",
.mode = VMODE_852x480p60hz,
.width = 852,
.height = 480,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_854x480p60hz */
.name = "854x480p60hz",
.mode = VMODE_854x480p60hz,
.width = 854,
.height = 480,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_1024x768p60hz */
.name = "1024x768p60hz",
.mode = VMODE_1024x768p60hz,
.width = 1024,
.height = 768,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_1152x864p75hz */
.name = "1152x864p75hz",
.mode = VMODE_1152x864p75hz,
.width = 1152,
.height = 864,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_1280x600p60hz */
.name = "1280x600p60hz",
.mode = VMODE_1280x600p60hz,
.width = 1280,
.height = 600,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_1280x768p60hz */
.name = "1280x768p60hz",
.mode = VMODE_1280x768p60hz,
.width = 1280,
.height = 768,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_1280x800p60hz */
.name = "1280x800p60hz",
.mode = VMODE_1280x800p60hz,
.width = 1280,
.height = 800,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_1280x960p60hz */
.name = "1280x960p60hz",
.mode = VMODE_1280x960p60hz,
.width = 1280,
.height = 960,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_1280x1024p60hz */
.name = "1280x1024p60hz",
.mode = VMODE_1280x1024p60hz,
.width = 1280,
.height = 1024,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_1360x768p60hz */
.name = "1360x768p60hz",
.mode = VMODE_1360x768p60hz,
.width = 1360,
.height = 768,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_1366x768p60hz */
.name = "1366x768p60hz",
.mode = VMODE_1366x768p60hz,
.width = 1366,
.height = 768,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_1400x1050p60hz */
.name = "1400x1050p60hz",
.mode = VMODE_1400x1050p60hz,
.width = 1400,
.height = 1050,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_1440x900p60hz */
.name = "1440x900p60hz",
.mode = VMODE_1440x900p60hz,
.width = 1440,
.height = 900,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_1440x2560p60hz */
.name = "1440x2560p60hz",
.mode = VMODE_1440x2560p60hz,
.width = 1440,
.height = 2560,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_1440x2560p70hz */
.name = "1440x2560p70hz",
.mode = VMODE_1440x2560p70hz,
.width = 1440,
.height = 2560,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_1600x900p60hz */
.name = "1600x900p60hz",
.mode = VMODE_1600x900p60hz,
.width = 1600,
.height = 900,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_1600x1200p60hz */
.name = "1600x1200p60hz",
.mode = VMODE_1600x1200p60hz,
.width = 1600,
.height = 1200,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_1680x1050p60hz */
.name = "1680x1050p60hz",
.mode = VMODE_1680x1050p60hz,
.width = 1680,
.height = 1050,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_1920x1200p60hz */
.name = "1920x1200p60hz",
.mode = VMODE_1920x1200p60hz,
.width = 1920,
.height = 1200,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_2160x1200p90hz */
.name = "2160x1200p90hz",
.mode = VMODE_2160x1200p90hz,
.width = 2160,
.height = 1200,
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
},
{ /* VMODE_2560x1080p60hz */
.name = "2560x1080p60hz",
.mode = VMODE_2560x1080p60hz,
.width = 2560,
.height = 1080,
- },
+ .viu_color_fmt = VPP_CM_YUV,
+ .viu_mux = VIU_MUX_ENCP,
+ }
};
static struct vinfo_s vout_info = {
@@ -348,70 +432,46 @@
.priv = NULL, /* Pointer to driver-specific data */
};
-static inline void vout_reg_write(u32 reg, const u32 val)
+static int vout_conf_check(void)
{
- *(volatile unsigned int *)REG_ADDR_VCBUS(reg) = (val);
+ if (vout_conf)
+ return 0;
+
+ vout_probe();
+ if (!vout_conf) {
+ vout_log("error: %s: no vout_conf\n", __func__);
+ return -1;
+ }
+
+ return 0;
}
-static int vout_find_mode_by_name(const char *name)
+static const struct vout_set_s *vout_find_mode_by_name(const char *name)
{
- int mode = -1;
+ const struct vout_set_s *vset = NULL;
int i = 0;
- for (i = 0; i < sizeof(vout_sets) / sizeof(struct vout_set_s); i++) {
- if (strncmp(name, vout_sets[i].name, strlen(vout_sets[i].name)) == 0) {
- mode = vout_sets[i].mode;
- return mode;
- }
+ vset = vout_sets_dft;
+ for (i = 0; i < sizeof(vout_sets_dft) / sizeof(struct vout_set_s); i++) {
+ if (strncmp(name, vset->name, strlen(vset->name)) == 0)
+ return vset;
+ vset++;
+ }
+
+ vset = vout_sets_lcd;
+ for (i = 0; i < sizeof(vout_sets_lcd) / sizeof(struct vout_set_s); i++) {
+ if (strcmp(name, vset->name) == 0)
+ return vset;
+ vset++;
}
vout_log("mode: %s not found\n", name);
- return -1;
+ return NULL;
}
-static int vout_find_width_by_name(const char* name)
+static unsigned int vout_env2uint(const char *name, int base)
{
- int i = 0;
- ulong width = 0;
-
- for (i = 0; i < sizeof(vout_sets) / sizeof(struct vout_set_s); i++) {
- if (strncmp(name, vout_sets[i].name, strlen(vout_sets[i].name)) == 0) {
- width = vout_sets[i].width;
- return width;
- }
- }
-
- return width;
-}
-
-static int vout_find_height_by_name(const char* name)
-{
- int height = 0;
- int i = 0;
-
- for (i = 0; i < sizeof(vout_sets) / sizeof(struct vout_set_s); i++) {
- if (strncmp(name, vout_sets[i].name, strlen(vout_sets[i].name)) == 0) {
- height = vout_sets[i].height;
- return height;
- }
- }
-
- return height;
-}
-
-static int vout_find_field_height_by_name(const char* name)
-{
- int height = 0;
- int i = 0;
-
- for (i = 0; i < sizeof(vout_sets) / sizeof(struct vout_set_s); i++) {
- if (strncmp(name, vout_sets[i].name, strlen(vout_sets[i].name)) == 0) {
- height = vout_sets[i].field_height;
- return height;
- }
- }
-
- return height;
+ return (unsigned int)env_get_ulong(name, base, 0);
}
static void vout_vinfo_init(ulong width, ulong height, ulong field_height)
@@ -420,9 +480,9 @@
vout_info.height = height;
vout_info.field_height = field_height;
vout_info.vd_base = (void *)get_fb_addr();
- vout_info.vl_bpix = simple_strtoul(env_get("display_bpp"), NULL, 10);
- vout_info.vd_color_fg = simple_strtoul(env_get("display_color_fg"), NULL, 0);
- vout_info.vd_color_bg = simple_strtoul(env_get("display_color_bg"), NULL, 0);
+ vout_info.vl_bpix = (unsigned char)vout_env2uint("display_bpp", 10);
+ vout_info.vd_color_fg = vout_env2uint("display_color_fg", 0);
+ vout_info.vd_color_bg = vout_env2uint("display_color_bg", 0);
}
static void vout_axis_init(ulong w, ulong h)
@@ -437,33 +497,39 @@
static void vout_vmode_init(void)
{
char *outputmode = NULL;
+ const struct vout_set_s *vset = NULL;
int vmode = -1;
ulong width = 0;
ulong height = 0;
ulong field_height = 0;
#ifdef CONFIG_AML_LCD
- struct aml_lcd_drv_s *lcd_drv;
+ struct aml_lcd_drv_s *pdrv;
+ unsigned int venc_index;
#endif
outputmode = env_get("outputmode");
- vmode = vout_find_mode_by_name(outputmode);
+ vset = vout_find_mode_by_name(outputmode);
+ if (!vset)
+ return;
+
+ vmode = vset->mode;
vout_set_current_vmode(vmode);
switch (vmode) {
#ifdef CONFIG_AML_LCD
case VMODE_LCD:
- lcd_drv = aml_lcd_get_driver();
- width = lcd_drv->lcd_config->lcd_basic.h_active;
- height = lcd_drv->lcd_config->lcd_basic.v_active;
- field_height = lcd_drv->lcd_config->lcd_basic.v_active;
+ venc_index = (vset->viu_mux >> 4) & 0xf;
+ pdrv = aml_lcd_get_driver(venc_index);
+ width = pdrv->config.basic.h_active;
+ height = pdrv->config.basic.v_active;
+ field_height = pdrv->config.basic.v_active;
break;
#endif
default:
- width = vout_find_width_by_name(outputmode);
- height = vout_find_height_by_name(outputmode);
- field_height = vout_find_field_height_by_name(outputmode);
+ width = vset->width;
+ height = vset->height;
+ field_height = vset->field_height;
break;
}
- vout_reg_write(VPP_POSTBLEND_H_SIZE, width);
vout_axis_init(width, height);
vout_vinfo_init(width, height, field_height);
@@ -612,6 +678,111 @@
vout_log("vinfo.vl_bpix: %d\n", info->vl_bpix);
vout_log("vinfo.vd_color_fg: %d\n", info->vd_color_fg);
vout_log("vinfo.vd_color_bg: %d\n", info->vd_color_bg);
+
+ if (vout_conf_check())
+ return;
+ if (vout_conf->reg_dump)
+ vout_conf->reg_dump();
+}
+
+static void vout_reg_dump(void)
+{
+ unsigned int reg;
+
+ if (vout_conf_check())
+ return;
+
+ reg = vout_conf->viu_mux_reg;
+ vout_log("viu_mux: 0x%x = 0x%08x\n", reg, vout_reg_read(reg));
+}
+
+static unsigned int vout_viu1_mux = VIU_MUX_MAX;
+static unsigned int vout_viu2_mux = VIU_MUX_MAX;
+static void vout_viu_mux_default(int index, unsigned int mux_sel)
+{
+ unsigned int clk_bit = 0xff, clk_sel = 0;
+ unsigned int vout_viu_sel = 0xf;
+ unsigned int venc_sel = mux_sel;
+
+ switch (index) {
+ case VOUT_VIU2_SEL:
+ if (vout_conf->viu_valid[1]) {
+ /* set cts_vpu_clkc to 200MHz*/
+ vout_clk_setb(HHI_VPU_CLKC_CNTL, 2, 9, 3);
+ vout_clk_setb(HHI_VPU_CLKC_CNTL, 1, 0, 1);
+ vout_clk_setb(HHI_VPU_CLKC_CNTL, 1, 8, 3);
+ clk_sel = 1;
+ }
+ if (venc_sel == vout_viu1_mux)
+ vout_viu1_mux = VIU_MUX_MAX;
+ vout_viu2_mux = venc_sel;
+ break;
+ case VOUT_VIU1_SEL:
+ clk_sel = 0;
+ if (venc_sel == vout_viu2_mux) {
+ if (vout_conf->viu_valid[1])
+ vout_clk_setb(HHI_VPU_CLKC_CNTL, 0, 8, 1);
+ vout_viu2_mux = VIU_MUX_MAX;
+ }
+ vout_viu1_mux = venc_sel;
+ break;
+ default:
+ break;
+ }
+ vout_viu_sel = (vout_viu1_mux | (vout_viu2_mux << 2));
+
+ switch (venc_sel) {
+ case VIU_MUX_ENCL:
+ clk_bit = 1;
+ break;
+ case VIU_MUX_ENCI:
+ clk_bit = 2;
+ break;
+ case VIU_MUX_ENCP:
+ clk_bit = 0;
+ break;
+ default:
+ break;
+ }
+
+ vout_reg_setb(VPU_VIU_VENC_MUX_CTRL, vout_viu_sel, 0, 4);
+ if (vout_conf->viu_valid[1]) {
+ if (clk_bit < 0xff)
+ vout_reg_setb(VPU_VENCX_CLK_CTRL, clk_sel, clk_bit, 1);
+ }
+}
+
+static void vout_viu_mux_t7(int index, unsigned int mux_sel)
+{
+ unsigned int viu_bit = 0xff, venc_idx;
+
+ switch (index) {
+ case VOUT_VIU1_SEL:
+ viu_bit = 0;
+ break;
+ case VOUT_VIU2_SEL:
+ viu_bit = 2;
+ break;
+ case VOUT_VIU3_SEL:
+ viu_bit = 4;
+ break;
+ default:
+ vout_log("error: %s: invalid index %d\n", __func__, index);
+ return;
+ }
+ venc_idx = (mux_sel >> 4) & 0xf;
+
+ /* viu_mux: viu0_sel: 0=venc0, 1=venc1, 2=venc2, 3=invalid */
+ vout_reg_setb(VPU_VIU_VENC_MUX_CTRL, venc_idx, viu_bit, 2);
+}
+
+void vout_viu_mux(int index, unsigned int mux_sel)
+{
+ if (vout_conf_check())
+ return;
+
+ if (vout_conf->viu_mux)
+ vout_conf->viu_mux(index, mux_sel);
}
void vout_init(void)
@@ -619,3 +790,62 @@
vout_logl();
vout_vmode_init();
}
+
+/* **********************************
+ * vout match data
+ * **********************************
+ */
+static struct vout_conf_s vout_config_single = {
+ .viu_valid[0] = 1,
+ .viu_valid[1] = 0,
+ .viu_valid[2] = 0,
+
+ .viu_mux_reg = VPU_VIU_VENC_MUX_CTRL,
+
+ .viu_mux = vout_viu_mux_default,
+ .reg_dump = vout_reg_dump,
+};
+
+static struct vout_conf_s vout_config_dual = {
+ .viu_valid[0] = 1,
+ .viu_valid[1] = 1,
+ .viu_valid[2] = 0,
+
+ .viu_mux_reg = VPU_VIU_VENC_MUX_CTRL,
+
+ .viu_mux = vout_viu_mux_default,
+ .reg_dump = vout_reg_dump,
+};
+
+static struct vout_conf_s vout_config_triple = {
+ .viu_valid[0] = 1,
+ .viu_valid[1] = 1,
+ .viu_valid[2] = 1,
+
+ .viu_mux_reg = VPU_VENC_CTRL,
+
+ .viu_mux = vout_viu_mux_t7,
+ .reg_dump = vout_reg_dump,
+};
+
+void vout_probe(void)
+{
+ switch (get_cpu_id().family_id) {
+ case MESON_CPU_MAJOR_ID_G12A:
+ case MESON_CPU_MAJOR_ID_G12B:
+ case MESON_CPU_MAJOR_ID_TL1:
+ case MESON_CPU_MAJOR_ID_TM2:
+ case MESON_CPU_MAJOR_ID_SM1:
+ case MESON_CPU_MAJOR_ID_T5:
+ case MESON_CPU_MAJOR_ID_T5D:
+ vout_conf = &vout_config_dual;
+ break;
+ case MESON_CPU_MAJOR_ID_T7:
+ vout_conf = &vout_config_triple;
+ vout_reg_write(VPU_VIU_VENC_MUX_CTRL, 0x3f);
+ break;
+ default:
+ vout_conf = &vout_config_single;
+ break;
+ }
+}
diff --git a/drivers/amlogic/media/vout/vout.h b/drivers/amlogic/media/vout/vout.h
new file mode 100644
index 0000000..a8e3157
--- /dev/null
+++ b/drivers/amlogic/media/vout/vout.h
@@ -0,0 +1,27 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _VOUT_H
+#define _VOUT_H
+
+struct vout_conf_s {
+ unsigned int viu_valid[3];
+ unsigned int viu_mux_reg;
+
+ void (*viu_mux)(int index, unsigned int mux_sel);
+ void (*reg_dump)(void);
+};
+
+struct vout_set_s {
+ char *name;
+ int mode;
+ ulong width;
+ ulong height;
+ ulong field_height;
+ int viu_color_fmt;
+ unsigned int viu_mux;
+};
+
+#endif
diff --git a/drivers/amlogic/media/vout/vout_reg.h b/drivers/amlogic/media/vout/vout_reg.h
new file mode 100644
index 0000000..945aa3a
--- /dev/null
+++ b/drivers/amlogic/media/vout/vout_reg.h
@@ -0,0 +1,80 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _VOUT_REG_H
+#define _VOUT_REG_H
+
+#ifndef REG_BASE_VCBUS
+#define REG_BASE_VCBUS (0xff900000L)
+#endif
+#define REG_OFFSET_VCBUS(reg) ((reg << 2))
+#define REG_ADDR_VCBUS(reg) (REG_BASE_VCBUS + REG_OFFSET_VCBUS(reg) + 0L)
+
+#define REG_CLK_ADDR(reg) (reg + 0L)
+#define REG_VOUT_ADDR(reg) (reg + 0L)
+
+#ifndef HHI_VPU_CLKC_CNTL
+#define HHI_VPU_CLKC_CNTL (0xff63c000L + (0x06d << 2))
+#endif
+#ifndef CLKCTRL_VPU_CLKC_CTRL
+#define CLKCTRL_VPU_CLKC_CTRL ((0x003c << 2) + 0xfe000000L)
+#endif
+#ifndef VPU_VIU_VENC_MUX_CTRL
+#define VPU_VIU_VENC_MUX_CTRL ((0x271a << 2) + 0xff000000L)
+#endif
+#ifndef VPU_VENCX_CLK_CTRL
+#define VPU_VENCX_CLK_CTRL ((0x2785 << 2) + 0xff000000L)
+#endif
+#ifndef VPU_VENC_CTRL
+#define VPU_VENC_CTRL ((0x1cef << 2) + 0xff000000L)
+#endif
+
+static inline unsigned int vout_reg_read(u32 reg)
+{
+ unsigned int val;
+
+ if (reg > 0x10000)
+ val = *(volatile unsigned int *)REG_VOUT_ADDR(reg);
+ else
+ val = *(volatile unsigned int *)REG_ADDR_VCBUS(reg);
+
+ return val;
+}
+
+static inline void vout_reg_write(u32 reg, const u32 val)
+{
+ if (reg > 0x10000)
+ *(volatile unsigned int *)REG_VOUT_ADDR(reg) = (val);
+ else
+ *(volatile unsigned int *)REG_ADDR_VCBUS(reg) = (val);
+}
+
+static inline void vout_reg_setb(unsigned int reg, unsigned int val,
+ unsigned int start, unsigned int len)
+{
+ vout_reg_write(reg, ((vout_reg_read(reg) &
+ ~(((1L << (len))-1) << (start))) |
+ (((val)&((1L<<(len))-1)) << (start))));
+}
+
+static inline unsigned int vout_clk_read(u32 reg)
+{
+ return *(volatile unsigned int *)(REG_CLK_ADDR(reg));
+}
+
+static inline void vout_clk_write(u32 reg, const u32 val)
+{
+ *(volatile unsigned int *)REG_CLK_ADDR(reg) = (val);
+}
+
+static inline void vout_clk_setb(unsigned int reg, unsigned int val,
+ unsigned int start, unsigned int len)
+{
+ vout_clk_write(reg, ((vout_clk_read(reg) &
+ ~(((1L << (len))-1) << (start))) |
+ (((val)&((1L<<(len))-1)) << (start))));
+}
+
+#endif
diff --git a/drivers/amlogic/power/Kconfig b/drivers/amlogic/power/Kconfig
new file mode 100644
index 0000000..38fa10e
--- /dev/null
+++ b/drivers/amlogic/power/Kconfig
@@ -0,0 +1,5 @@
+config SECURE_POWER_CONTROL
+ bool "Amlogic device MEM_PD control"
+
+config PMIC_BD71837
+ bool "Amlogic device bd71837"
diff --git a/drivers/amlogic/power/Makefile b/drivers/amlogic/power/Makefile
new file mode 100644
index 0000000..97c54f4
--- /dev/null
+++ b/drivers/amlogic/power/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_SECURE_POWER_CONTROL) += sec_pwr_ctrl.o
+obj-$(CONFIG_PMIC_BD71837) += pmic_bd71837.o
diff --git a/drivers/amlogic/power/pmic_bd71837.c b/drivers/amlogic/power/pmic_bd71837.c
new file mode 100644
index 0000000..9c52265
--- /dev/null
+++ b/drivers/amlogic/power/pmic_bd71837.c
@@ -0,0 +1,35 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <i2c.h>
+#include <asm/arch/pmic_bd71837.h>
+
+struct udevice *dev;
+
+void bd71837_set_muxsw_switch(int enable)
+{
+ uint8_t val = 0;
+ int ret = 0;
+
+ if (enable)
+ val = 1;
+ else
+ val = 0;
+
+ ret = dm_i2c_write(dev, BD71837_REG_MUXSW_EN, &val, 1);
+ if (ret)
+ printf("%s i2c write failed\n", __func__);
+}
+
+
+void pmic_bd71837_init(void)
+{
+ int rc;
+
+ rc = i2c_get_chip_for_busnum(I2C_BUS_ID, BD71837_CHIP_DEV, 1, &dev);
+ if (rc)
+ printf("%s i2c write failed\n", __func__);
+}
diff --git a/drivers/amlogic/power/sec_pwr_ctrl.c b/drivers/amlogic/power/sec_pwr_ctrl.c
new file mode 100644
index 0000000..513bc09
--- /dev/null
+++ b/drivers/amlogic/power/sec_pwr_ctrl.c
@@ -0,0 +1,25 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <linux/arm-smccc.h>
+#include <asm/arch/pwr_ctrl.h>
+
+unsigned long pwr_ctrl_psci_smc(unsigned int power_domain, bool power_control)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(0x82000093, power_domain, power_control, 0,
+ 0, 0, 0, 0, &res);
+ return res.a0;
+}
+
+unsigned long pwr_ctrl_status_psci_smc(unsigned int power_domain)
+{
+ struct arm_smccc_res res;
+
+ arm_smccc_smc(0x82000095, power_domain, 0, 0,
+ 0, 0, 0, 0, &res);
+ return res.a0;
+}
diff --git a/drivers/amlogic/provision/Kconfig b/drivers/amlogic/provision/Kconfig
new file mode 100644
index 0000000..b258e45
--- /dev/null
+++ b/drivers/amlogic/provision/Kconfig
@@ -0,0 +1,4 @@
+config FAT_WRITE
+ bool "enable fat write"
+config AML_FACTORY_PROVISION
+ bool "enable factory provision"
diff --git a/drivers/amlogic/storagekey/Kconfig b/drivers/amlogic/storagekey/Kconfig
index f98b198..311ab7e 100644
--- a/drivers/amlogic/storagekey/Kconfig
+++ b/drivers/amlogic/storagekey/Kconfig
@@ -1,3 +1,2 @@
config SECURE_STORAGE
bool "Amlogic bl31 storage key"
-
diff --git a/drivers/amlogic/storagekey/Makefile b/drivers/amlogic/storagekey/Makefile
index d7ae8cd..6e7ccb4 100644
--- a/drivers/amlogic/storagekey/Makefile
+++ b/drivers/amlogic/storagekey/Makefile
@@ -1,2 +1,3 @@
obj-$(CONFIG_SECURE_STORAGE) += storagekey.o
obj-$(CONFIG_SECURE_STORAGE) += securestorage.o
+obj-$(CONFIG_SECURE_STORAGE) += normal_key.o
diff --git a/drivers/amlogic/storagekey/normal_key.c b/drivers/amlogic/storagekey/normal_key.c
new file mode 100644
index 0000000..f53f2ca
--- /dev/null
+++ b/drivers/amlogic/storagekey/normal_key.c
@@ -0,0 +1,675 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <linux/types.h>
+#include <linux/list.h>
+#include <u-boot/sha256.h>
+#include <malloc.h>
+#include "normal_key.h"
+
+#undef pr_info
+#define pr_info(fmt ...) printf("[KM]Msg:"fmt)
+#undef pr_err
+#define pr_err(fmt ...) printf("[KM]Error:f[%s]L%d:", __func__, __LINE__),printf(fmt)
+
+#define DBG 0
+
+/* Storage BLOCK RAW HEAD: fixed 512B*/
+#define ENC_TYPE_DEFAULT 0
+#define ENC_TYPE_EFUSE 1
+#define ENC_TYPE_FIXED 2
+
+#define STORAGE_BLOCK_RAW_HEAD_SIZE 512
+
+#define BLOCK_VERSION_0 0
+
+#define ERR_HEADER 0x1
+#define ERR_KEYMEMFAIL 0x2
+#define ERR_KEYRDFAIL 0x4
+#define ERR_KEYCHKFAIL 0x8
+#define ERR_ENCHDFAIL 0x10
+#define ERR_DATASZ 0x20
+struct storage_block_raw_head {
+ u8 mark[16]; /* AMLNORMAL*/
+ u32 version;
+ u32 enctype; /*from EFUSE, from default, from fixed*/
+ u32 keycnt;
+ u32 initcnt;
+ u32 wrtcnt;
+ u32 errcnt;
+ u32 flags;
+ u8 headhash[32];
+ u8 hash[32];
+};
+
+/* Storage BLOCK ENC HEAD: fixed 512B*/
+#define STORAGE_BLOCK_ENC_HEAD_SIZE 512
+struct storage_block_enc_head {
+ u32 blocksize;
+ u32 flashsize;
+};
+
+/* Storage Format: TLV*/
+enum emTLVTag {
+ EMTLVNONE,
+
+ EMTLVHEAD,
+ EMTLVHEADSIZE,
+
+ EMTLVOBJECT,
+ EMTLVOBJNAMESIZE,
+ EMTLVOBJNAME,
+ EMTLVOBJDATASIZE,
+ EMTLVOBJDATABUF,
+ EMTLVOBJTYPE,
+ EMTLVOBJATTR,
+ EMTLVOBJHASHBUF,
+
+ EMTLVHEADFLASHSIZE,
+};
+
+struct storage_node {
+ struct list_head node;
+ struct storage_object object;
+};
+
+static LIST_HEAD(keys);
+static int blockinited;
+static struct storage_block_raw_head rawhead;
+static struct storage_block_enc_head enchead;
+static char *blockmark = "AMLNORMAL";
+
+#if DBG
+static void dump_mem(const u8 *p, int len);
+static void dump_raw_head(struct storage_block_raw_head *prawhead)
+{
+ pr_info("rawhead:\n");
+ pr_info("mark: %s\n", prawhead->mark);
+ pr_info("keycnt: %u\n", prawhead->keycnt);
+ pr_info("initcnt: %u\n", prawhead->initcnt);
+ pr_info("wrtcnt: %u\n", prawhead->wrtcnt);
+ pr_info("errcnt: %u\n", prawhead->errcnt);
+ pr_info("flags: 0x%x\n", prawhead->flags);
+ pr_info("headhash:\n");
+ dump_mem(prawhead->headhash, 32);
+ pr_info("hash:\n");
+ dump_mem(prawhead->hash, 32);
+}
+
+static void dump_enc_head(struct storage_block_enc_head *penchead)
+{
+ pr_info("enchead:\n");
+ pr_info("blocksize: %u\n", penchead->blocksize);
+ pr_info("flashsize: %u\n", penchead->flashsize);
+}
+
+static void dump_mem(const u8 *p, int len)
+{
+ int idx = 0, j, tmp;
+ char buf[64];
+ int total;
+
+ while (idx < len) {
+ total = 0;
+ tmp = min(((int)len - idx), 16);
+ for (j = 0; j < tmp; j++)
+ total += snprintf(buf + total, 64 - total,
+ "%02x ", p[idx + j]);
+ buf[total] = 0;
+ pr_info("%s\n", buf);
+ idx += tmp;
+ }
+}
+
+static void dump_object(struct storage_object *obj)
+{
+ pr_info("key: [%u, %.*s, %x, %x, %u]\n",
+ obj->namesize, obj->namesize, obj->name,
+ obj->type, obj->attribute, obj->datasize);
+ if (obj->dataptr) {
+ pr_info("data:\n");
+ dump_mem(obj->dataptr, obj->datasize);
+ }
+}
+#endif
+
+static u32 Tlv_WriteUint32(u8 *output, s32 len,
+ u32 tag, u32 value)
+{
+ u32 *out = (u32 *)output;
+
+ if (len < 12)
+ return 0;
+
+ out[0] = tag;
+ out[1] = 4;
+ out[2] = value;
+ return 12;
+}
+
+static u32 Tlv_WriteBuf(u8 *output, s32 len,
+ u32 tag,
+ u32 length, u8 *input)
+{
+ u8 *out = output;
+ u32 tmplen = (((length + 3) / 4) * 4);
+
+ if (len < (s32)(8 + tmplen))
+ return 0;
+
+ *((u32 *)out) = tag;
+ *((u32 *)(out + 4)) = tmplen;
+ memset(out + 8, 0, tmplen);
+ memcpy(out + 8, input, length);
+
+ return tmplen + 8;
+}
+
+static u32 Tlv_ReadTl(u8 *input, int32_t len,
+ u32 *tag, u32 *length,
+ u32 *idx)
+{
+ if (len < 8)
+ return 0;
+
+ *tag = *((u32 *)input);
+ *length = *((u32 *)(input + 4));
+
+ if ((8 + *length) > len)
+ return 0;
+ *idx += 8;
+
+ return 8;
+}
+
+static u32 Tlv_ReadHead(u8 *input, int32_t len,
+ struct storage_block_enc_head *pblockhead)
+{
+ u32 tag;
+ u32 sum;
+ u32 length;
+ u32 idx = 0;
+ u32 ret;
+
+ ret = Tlv_ReadTl(input, len,
+ &tag, &sum, &idx);
+ if (!ret)
+ return 0;
+
+ if (tag != EMTLVHEAD)
+ return 0;
+
+ sum += ret;
+ while (idx < sum) {
+ ret = Tlv_ReadTl(input + idx, len - idx,
+ &tag, &length, &idx);
+ if (!ret)
+ return 0;
+
+ switch (tag) {
+ case EMTLVHEADSIZE:
+ pblockhead->blocksize = *((u32 *)(input + idx));
+ break;
+ case EMTLVHEADFLASHSIZE:
+ pblockhead->flashsize = *((u32 *)(input + idx));
+ break;
+ default:
+ break;
+ }
+ idx += length;
+ }
+ return sum;
+}
+
+static u32 Tlv_ReadObject(u8 *input, int32_t len,
+ struct storage_object *pcontent)
+{
+ u32 tag;
+ u32 length;
+ u32 sum;
+ u32 idx = 0;
+ u32 ret;
+
+ memset(pcontent, 0, sizeof(*pcontent));
+ ret = Tlv_ReadTl(input, len,
+ &tag, &sum, &idx);
+ if (!ret)
+ return 0;
+
+ if (tag != EMTLVOBJECT)
+ return 0;
+
+ sum += ret;
+ while (idx < sum) {
+ ret = Tlv_ReadTl(input + idx, len - idx,
+ &tag, &length, &idx);
+ if (!ret)
+ goto tlv_readkeycontent_err;
+
+ switch (tag) {
+ case EMTLVOBJNAMESIZE:
+ pcontent->namesize = *((u32 *)(input + idx));
+ break;
+ case EMTLVOBJNAME:
+ memset(pcontent->name, 0, MAX_OBJ_NAME_LEN);
+ memcpy(pcontent->name, input + idx, pcontent->namesize);
+ break;
+ case EMTLVOBJTYPE:
+ pcontent->type = *((u32 *)(input + idx));
+ break;
+ case EMTLVOBJATTR:
+ pcontent->attribute = *((u32 *)(input + idx));
+ break;
+ case EMTLVOBJDATASIZE:
+ pcontent->datasize = *((u32 *)(input + idx));
+ break;
+ case EMTLVOBJHASHBUF:
+ if (length != 32)
+ goto tlv_readkeycontent_err;
+ memcpy(pcontent->hashptr, input + idx, length);
+ break;
+ case EMTLVOBJDATABUF:
+ pcontent->dataptr = malloc(pcontent->datasize);
+ if (!pcontent->dataptr)
+ goto tlv_readkeycontent_err;
+ memcpy(pcontent->dataptr,
+ input + idx, pcontent->datasize);
+ break;
+ default:
+ break;
+ }
+ idx += length;
+ }
+ return sum;
+
+tlv_readkeycontent_err:
+ free(pcontent->dataptr);
+ return 0;
+}
+
+#define WRT_UINT32(tag, field) \
+ ({ \
+ u32 __tmp; \
+ __tmp = Tlv_WriteUint32(output + idx, len - idx, \
+ tag, field); \
+ if (__tmp) \
+ idx += __tmp; \
+ __tmp; \
+ })
+
+#define WRT_BUF(tag, buflen, buf) \
+ ({ \
+ u32 __tmp; \
+ __tmp = Tlv_WriteBuf(output + idx, len - idx, \
+ tag, buflen, buf); \
+ if (__tmp) \
+ idx += __tmp; \
+ __tmp; \
+ })
+
+u32 Tlv_WriteHead(struct storage_block_enc_head *enchead,
+ u8 *output, int32_t len)
+{
+ u32 *sum;
+ u32 idx = 0;
+
+ if (len < 8)
+ return 0;
+
+ *(u32 *)output = EMTLVHEAD;
+ sum = (u32 *)(output + 4);
+ idx += 8;
+
+ if (!WRT_UINT32(EMTLVHEADSIZE, enchead->blocksize))
+ return 0;
+ if (!WRT_UINT32(EMTLVHEADFLASHSIZE, enchead->flashsize))
+ return 0;
+
+ *sum = idx - 8;
+ return idx;
+}
+
+u32 Tlv_WriteObject(struct storage_object *object,
+ u8 *output, int32_t len)
+{
+ u32 *sum;
+ u32 idx = 0;
+
+ if (len < 8)
+ return 0;
+
+ *(u32 *)output = EMTLVOBJECT;
+ sum = (u32 *)(output + 4);
+ idx += 8;
+
+ if (object->namesize != 0) {
+ if (!WRT_UINT32(EMTLVOBJNAMESIZE, object->namesize))
+ return 0;
+ if (!WRT_BUF(EMTLVOBJNAME, object->namesize,
+ (u8 *)object->name))
+ return 0;
+ }
+
+ if (object->dataptr && object->datasize != 0) {
+ if (!WRT_UINT32(EMTLVOBJDATASIZE, object->datasize))
+ return 0;
+ if (!WRT_BUF(EMTLVOBJDATABUF, object->datasize,
+ object->dataptr))
+ return 0;
+ }
+
+ if (!WRT_BUF(EMTLVOBJHASHBUF, 32, object->hashptr))
+ return 0;
+ if (!WRT_UINT32(EMTLVOBJTYPE, object->type))
+ return 0;
+ if (!WRT_UINT32(EMTLVOBJATTR, object->attribute))
+ return 0;
+
+ *sum = idx - 8;
+ return idx;
+}
+
+static int normalkey_hash(u8 *data, u32 len, u8 *hash)
+{
+ sha256_context ctx;
+ sha256_starts(&ctx);
+ sha256_update(&ctx, data, len);
+ sha256_finish(&ctx, hash);
+ return 0;
+}
+
+int normalkey_init(void)
+{
+ if (blockinited)
+ return 0;
+
+ blockinited = 1;
+ return 0;
+}
+
+void normalkey_deinit(void)
+{
+ struct storage_node *pos, *n;
+
+ if (!blockinited)
+ return;
+
+ blockinited = 0;
+
+ list_for_each_entry_safe(pos, n, &keys, node) {
+ list_del(&pos->node);
+ free(pos->object.dataptr);
+ free(pos);
+ }
+}
+
+struct storage_object *normalkey_get(const u8 *name)
+{
+ struct storage_node *pos;
+ struct storage_object *obj;
+ u32 len;
+
+ if (!name)
+ return NULL;
+
+ len = strlen((const char*)name);
+ list_for_each_entry(pos, &keys, node) {
+ obj = &pos->object;
+ if (len == obj->namesize &&
+ !memcmp(name, obj->name, len))
+ return obj;
+ }
+
+ return NULL;
+}
+
+int normalkey_add(const u8 *name, u8 *buffer, u32 len, u32 attr)
+{
+ struct storage_object *obj;
+ struct storage_node *node;
+ u32 namelen;
+ u8 *data;
+
+ if (blockinited != 2)
+ return -1;
+
+ if (!name || !buffer || !len || (attr & OBJ_ATTR_SECURE))
+ return -1;
+
+ namelen = strlen((const char*)name);
+ if (namelen > MAX_OBJ_NAME_LEN)
+ return -1;
+
+ obj = normalkey_get(name);
+ if (obj) {
+ if (attr != obj->attribute)
+ return -1;
+ if (len > obj->datasize) {
+ data = malloc(len);
+ if (!data)
+ return -1;
+ free(obj->dataptr);
+ obj->dataptr = data;
+ }
+ } else {
+ node = malloc(sizeof(*node));
+ if (!node)
+ return -1;
+ data = malloc(len);
+ if (!data) {
+ free(node);
+ return -1;
+ }
+ obj = &node->object;
+ memcpy(obj->name, name, namelen);
+ obj->namesize = namelen;
+ obj->attribute = attr;
+ obj->type = OBJ_TYPE_GENERIC;
+ obj->dataptr = data;
+ list_add(&node->node, &keys);
+ }
+ obj->datasize = len;
+ memcpy(obj->dataptr, buffer, len);
+ normalkey_hash(buffer, len, obj->hashptr);
+ return 0;
+}
+
+int normalkey_del(const u8 *name)
+{
+ struct storage_object *obj;
+ struct storage_node *node;
+
+ if (blockinited != 2)
+ return -1;
+
+ obj = normalkey_get(name);
+ if (!obj)
+ return -1;
+
+ node = container_of(obj, struct storage_node, object);
+ list_del(&node->node);
+ free(obj->dataptr);
+ free(node);
+
+ return 0;
+}
+
+int normalkey_readfromblock(void *block, unsigned long size)
+{
+ struct storage_block_raw_head *prawhead;
+ u8 *penchead, *pdata;
+ struct storage_node *node = NULL;
+ u8 hash[32];
+ u32 idx;
+ u32 ret;
+
+ if (blockinited != 1)
+ return -1;
+
+ prawhead = (struct storage_block_raw_head *)block;
+ penchead = (u8 *)block + STORAGE_BLOCK_RAW_HEAD_SIZE;
+ pdata = penchead + STORAGE_BLOCK_ENC_HEAD_SIZE;
+
+ if (!block || size <=
+ (STORAGE_BLOCK_ENC_HEAD_SIZE + STORAGE_BLOCK_RAW_HEAD_SIZE))
+ return -1;
+
+ blockinited = 2;
+
+#if DBG
+ pr_info("size is %lu\n", size);
+ dump_raw_head(prawhead);
+#endif
+
+ memset(&rawhead, 0, sizeof(rawhead));
+ strncpy((char*)rawhead.mark, blockmark, 15);
+ rawhead.version = BLOCK_VERSION_0;
+
+ enchead.flashsize = size;
+ if (strcmp((const char *)prawhead->mark, blockmark) != 0) {
+ pr_info("mark is not found\n");
+ return 0;
+ }
+
+ flush_dcache_range((unsigned long)block, (unsigned long)block + size);
+ normalkey_hash((u8 *)prawhead, sizeof(*prawhead) - 64,
+ rawhead.headhash);
+ if (memcmp(rawhead.headhash, prawhead->headhash, 32)) {
+ pr_info("rawhead hash check fail\n");
+ rawhead.flags |= ERR_HEADER;
+ } else {
+ pr_info("rawhead hash check successful\n");
+ rawhead.keycnt = prawhead->keycnt;
+ rawhead.initcnt = prawhead->initcnt;
+ rawhead.wrtcnt = prawhead->wrtcnt;
+ rawhead.errcnt = prawhead->errcnt;
+ rawhead.flags = prawhead->flags;
+ }
+
+ rawhead.initcnt++;
+
+ normalkey_hash(penchead, size - STORAGE_BLOCK_RAW_HEAD_SIZE,
+ rawhead.hash);
+#if DBG
+ dump_raw_head(&rawhead);
+#endif
+ if (memcmp(rawhead.hash, prawhead->hash, 32)) {
+ pr_info("data hash check fail\n");
+ rawhead.errcnt++;
+ return 0;
+ }
+
+ ret = Tlv_ReadHead(penchead, STORAGE_BLOCK_ENC_HEAD_SIZE,
+ &enchead);
+ if (!ret) {
+ pr_info("read head fail\n");
+ rawhead.flags |= ERR_ENCHDFAIL;
+ return 0;
+ }
+
+#if DBG
+ dump_enc_head(&enchead);
+#endif
+
+ if (size < (enchead.blocksize + STORAGE_BLOCK_ENC_HEAD_SIZE +
+ STORAGE_BLOCK_RAW_HEAD_SIZE)) {
+ rawhead.flags |= ERR_DATASZ;
+ return 0;
+ }
+
+ idx = 0;
+ while (idx < enchead.blocksize) {
+ struct storage_object *obj = NULL;
+
+ if (!node) {
+ node = malloc(sizeof(*node));
+ if (!node) {
+ rawhead.flags |= ERR_KEYMEMFAIL;
+ break;
+ }
+ }
+ obj = &node->object;
+ ret = Tlv_ReadObject(pdata + idx,
+ enchead.blocksize - idx, obj);
+ if (!ret) {
+ rawhead.flags |= ERR_KEYRDFAIL;
+ break;
+ }
+ idx += ret;
+
+ normalkey_hash(obj->dataptr, obj->datasize, hash);
+ if (memcmp(hash, obj->hashptr, 32)) {
+ free(obj->dataptr);
+ rawhead.flags |= ERR_KEYCHKFAIL;
+ continue;
+ }
+#if DBG
+ dump_object(obj);
+#endif
+ list_add(&node->node, &keys);
+ node = NULL;
+ }
+
+ free(node);
+ return 0;
+}
+
+int normalkey_writetoblock(void *block, unsigned long size)
+{
+ u8 *prawhead;
+ u8 *penchead, *pdata;
+ struct storage_object *obj = NULL;
+ struct storage_node *node = NULL;
+ u32 idx;
+ u32 ret;
+
+ if (blockinited != 2)
+ return -1;
+
+ prawhead = (u8 *)block;
+ penchead = prawhead + STORAGE_BLOCK_RAW_HEAD_SIZE;
+ pdata = penchead + STORAGE_BLOCK_ENC_HEAD_SIZE;
+
+ if (!block || size <=
+ (STORAGE_BLOCK_ENC_HEAD_SIZE + STORAGE_BLOCK_RAW_HEAD_SIZE))
+ return -1;
+
+ enchead.flashsize = size;
+ size -= (STORAGE_BLOCK_ENC_HEAD_SIZE + STORAGE_BLOCK_RAW_HEAD_SIZE);
+ idx = 0;
+ rawhead.keycnt = 0;
+ list_for_each_entry(node, &keys, node) {
+ obj = &node->object;
+ ret = Tlv_WriteObject(obj, pdata + idx, size - idx);
+ if (!ret)
+ return -1;
+ idx += ret;
+ rawhead.keycnt++;
+ }
+ enchead.blocksize = idx;
+
+ ret = Tlv_WriteHead(&enchead, penchead, STORAGE_BLOCK_ENC_HEAD_SIZE);
+ if (!ret)
+ return -1;
+
+ rawhead.wrtcnt++;
+ flush_dcache_range((unsigned long)&rawhead, (unsigned long)&rawhead + sizeof(rawhead));
+ flush_dcache_range((unsigned long)block, (unsigned long)block + size);
+ memset(rawhead.headhash, 0, sizeof(rawhead.headhash));
+ normalkey_hash((u8 *)&rawhead, sizeof(rawhead) - 64,
+ rawhead.headhash);
+ memset(rawhead.hash, 0, sizeof(rawhead.hash));
+ normalkey_hash(penchead,
+ enchead.flashsize - STORAGE_BLOCK_RAW_HEAD_SIZE,
+ rawhead.hash);
+ memcpy(prawhead, &rawhead, sizeof(rawhead));
+#if DBG
+ pr_info("size is %lu\n", enchead.flashsize);
+ dump_raw_head(prawhead);
+#endif
+
+ return 0;
+}
diff --git a/drivers/amlogic/storagekey/normal_key.h b/drivers/amlogic/storagekey/normal_key.h
new file mode 100644
index 0000000..a95b821
--- /dev/null
+++ b/drivers/amlogic/storagekey/normal_key.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _AML_NORMAL_KEY_H_
+#define _AML_NORMAL_KEY_H_
+
+#define MAX_OBJ_NAME_LEN 80
+
+/*Attribute*/
+#define OBJ_ATTR_SECURE BIT(0)
+#define OBJ_ATTR_OTP BIT(1)
+#define OBJ_ATTR_ENC BIT(8)
+
+/* Type */
+#define OBJ_TYPE_GENERIC 0xA00000BF
+
+struct storage_object {
+ char name[MAX_OBJ_NAME_LEN];
+ u32 namesize;
+ u32 attribute; /*secure, OTP*/
+ u32 type; /*AES, RSA, GENERIC, ...*/
+ u32 datasize;
+ u8 *dataptr;
+ u8 hashptr[32];
+};
+
+int normalkey_init(void);
+void normalkey_deinit(void);
+struct storage_object *normalkey_get(const u8 *name);
+int normalkey_add(const u8 *name, u8 *buffer, u32 len, u32 attr);
+int normalkey_del(const u8 *name);
+int normalkey_readfromblock(void *block, unsigned long size);
+int normalkey_writetoblock(void *block, unsigned long size);
+
+#endif
diff --git a/drivers/amlogic/storagekey/securestorage.c b/drivers/amlogic/storagekey/securestorage.c
index af37221..c1e0c08 100644
--- a/drivers/amlogic/storagekey/securestorage.c
+++ b/drivers/amlogic/storagekey/securestorage.c
@@ -1,3 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include <common.h>
#include <linux/types.h>
#include <asm/arch/secure_apb.h>
diff --git a/drivers/amlogic/storagekey/storagekey.c b/drivers/amlogic/storagekey/storagekey.c
index 6bca9c5..26eef04 100644
--- a/drivers/amlogic/storagekey/storagekey.c
+++ b/drivers/amlogic/storagekey/storagekey.c
@@ -1,22 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/storagekey/storagekey.c
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
/* extern from bl31 */
/*
@@ -32,9 +17,11 @@
#include <amlogic/secure_storage.h>
#include <amlogic/amlkey_if.h>
#include <amlogic/storage.h>
+#include <linux/libfdt.h>
#ifdef CONFIG_STORE_COMPATIBLE
#include <partition_table.h>
#endif
+#include "normal_key.h"
/* key buffer status */
/* bit0, dirty flag*/
@@ -60,7 +47,7 @@
*1.init
* return ok 0, fail 1
*/
-int32_t amlkey_init(uint8_t *seed, uint32_t len, int encrypt_type)
+static int32_t _amlkey_init(uint8_t *seed, uint32_t len, int encrypt_type)
{
int32_t ret = 0;
uint32_t buffer_size, actual_size;
@@ -84,22 +71,27 @@
if (encrypt_type == -1)
encrypt_type = 0;
secure_storage_set_enctype(encrypt_type);
+ actual_size = store_rsv_size("key");
+ printf("%s %d actual_size: 0x%x\n", __func__, __LINE__,
+ actual_size);
- /* full fill key infos from storage. */
+ storagekey_info.size = min_t(uint32_t, actual_size, buffer_size);
ret = store_rsv_read("key", storagekey_info.size, storagekey_info.buffer);
+ /* When the key is invalid at the first burn, it should be initialized again. */
+ if (ret == RSV_UNVAIL)
+ ret = 0;
if (ret) {
+ printf("amlkey init rsv read key faill\n");
/* memset head info for bl31 */
memset(storagekey_info.buffer, 0, SECUESTORAGE_HEAD_SIZE);
ret = 0;
goto _out;
}
- actual_size = storagekey_info.size;
- storagekey_info.size = actual_size;
- secure_storage_notifier_ex(actual_size, 0);
+ secure_storage_notifier_ex(storagekey_info.size, 0);
storagekey_info.buffer = secure_storage_getbuffer(&buffer_size);
- if (buffer_size != actual_size) {
+ if (buffer_size != storagekey_info.size) {
ret = -1;
goto _out;
}
@@ -115,7 +107,7 @@
*2. query if the key already programmed
* return: exsit 1, non 0
*/
-int32_t amlkey_isexsit(const uint8_t * name)
+static int32_t _amlkey_isexsit(const uint8_t * name)
{
int32_t ret = 0;
uint32_t retval;
@@ -134,7 +126,7 @@
return (int32_t)retval;
}
-static int32_t amlkey_get_attr(const uint8_t * name)
+static uint32_t _amlkey_get_attr(const uint8_t * name)
{
int32_t ret = 0;
uint32_t retval;
@@ -150,7 +142,7 @@
retval = 0;
}
- return (int32_t)(retval);
+ return retval;
}
/**
@@ -174,7 +166,7 @@
* 4. actual bytes of key value
* return actual size.
*/
-ssize_t amlkey_size(const uint8_t *name)
+static ssize_t _amlkey_size(const uint8_t *name)
{
ssize_t size = 0;
int32_t ret = 0;
@@ -198,7 +190,7 @@
*5. read non-secure key in bytes, return bytes readback actully.
* return actual size read back.
*/
-ssize_t amlkey_read(const uint8_t *name, uint8_t *buffer, uint32_t len)
+static ssize_t _amlkey_read(const uint8_t *name, uint8_t *buffer, uint32_t len)
{
int32_t ret = 0;
ssize_t retval = 0;
@@ -225,11 +217,11 @@
* bit8, encrypt/non-encrypt;
* return actual size write down.
*/
-ssize_t amlkey_write(const uint8_t *name, uint8_t *buffer, uint32_t len, uint32_t attr)
+static ssize_t _amlkey_write(const uint8_t *name, uint8_t *buffer, uint32_t len, uint32_t attr)
{
int32_t ret = 0;
ssize_t retval = 0;
- uint32_t actual_size;
+ //uint32_t actual_size;
if ( NULL == name ) {
printf("%s() %d, invalid key ", __func__, __LINE__);
@@ -250,7 +242,7 @@
__func__, __LINE__);
retval = 0;
}
- actual_size = storagekey_info.size;
+ //actual_size = storagekey_info.size;
}
}
_out:
@@ -260,7 +252,7 @@
* 7. get the hash value of programmed secure key | 32bytes length, sha256
* return success 0, fail -1
*/
-int32_t amlkey_hash_4_secure(const uint8_t * name, uint8_t * hash)
+static int32_t _amlkey_hash_4_secure(const uint8_t * name, uint8_t * hash)
{
int32_t ret = 0;
@@ -273,10 +265,9 @@
* 7. del key by name
* return success 0, fail -1
*/
-int32_t amlkey_del(const uint8_t * name)
+static int32_t __maybe_unused _amlkey_del(const uint8_t * name)
{
int32_t ret = 0;
- uint32_t actual_size;
ret = secure_storage_remove((uint8_t *)name);
if ((ret == 0) && (storagekey_info.buffer != NULL)) {
@@ -294,3 +285,287 @@
return ret;
}
+
+
+#define DEFINE_MUTEX(...)
+#define mutex_lock(...)
+#define mutex_unlock(...)
+#define PAGE_ALIGNED(a) (((a)&0xFFF)==0)
+#undef pr_info
+#define pr_info(fmt ...) printf("[KM]Msg:"fmt)
+#undef pr_err
+#define pr_err(fmt ...) printf("[KM]Error:f[%s]L%d:", __func__, __LINE__),printf(fmt)
+
+#define DEF_NORMAL_BLOCK_SIZE (256 * 1024)
+//static DEFINE_MUTEX(normalkey_lock);
+static uint32_t normal_blksz = DEF_NORMAL_BLOCK_SIZE;
+static uint32_t normal_flashsize = DEF_NORMAL_BLOCK_SIZE;
+static uint8_t *normal_block;
+
+static int _store_key_read(uint8_t * buffer, uint32_t length, uint32_t *actual_lenth)
+{
+ int ret;
+ uint32_t actual_size;
+ actual_size = store_rsv_size("key");
+ if (actual_size <= 1024)
+ return -1;
+
+ length = min_t(uint32_t, actual_size, length);
+ ret = store_rsv_read("key", length, buffer);
+ /* When the key is invalid at the first burn, it should be initialized again. */
+ if (ret && ret != RSV_UNVAIL) {
+ printf("amlkey init rsv read key faill\n");
+ return -1;
+ }
+ if (actual_lenth)
+ *actual_lenth = length;
+ return 0;
+}
+static int _store_key_write(uint8_t * buffer, uint32_t length, uint32_t *actual_lenth)
+{
+ int32_t ret;
+ ret = store_rsv_write("key", length, buffer);
+ if (ret)
+ return -1;
+ if (actual_lenth)
+ *actual_lenth = length;
+ return 0;
+}
+
+static int32_t _amlkey_init_normal(uint8_t *seed, uint32_t len, int encrypt_type)
+{
+ static int inited = 0;
+ int ret;
+
+ if (inited)
+ return 0;
+ inited = 1;
+
+ if (!normal_block)
+ return -1;
+
+ if (normalkey_init())
+ return -1;
+
+ mutex_lock(&normalkey_lock);
+ ret = _store_key_read(normal_block,
+ normal_blksz,
+ &normal_flashsize);
+ if (ret) {
+ pr_err("read storage fail\n");
+ goto finish;
+ }
+
+ ret = normalkey_readfromblock(normal_block, normal_flashsize);
+ if (ret) {
+ pr_err("init block key fail\n");
+ goto finish;
+ }
+
+#ifdef CONFIG_STORE_COMPATIBLE
+ info_disprotect &= ~DISPROTECT_KEY; //protect
+#endif
+ ret = 0;
+finish:
+ if (ret)
+ normalkey_deinit();
+ mutex_unlock(&normalkey_lock);
+
+ return ret;
+}
+
+static int32_t _amlkey_exist_normal(const uint8_t *name)
+{
+ struct storage_object *obj;
+
+ mutex_lock(&normalkey_lock);
+ obj = normalkey_get(name);
+ mutex_unlock(&normalkey_lock);
+
+ return !!obj;
+}
+
+static uint32_t _amlkey_get_attr_normal(const uint8_t *name)
+{
+ uint32_t attr = 0;
+ struct storage_object *obj;
+
+ mutex_lock(&normalkey_lock);
+ obj = normalkey_get(name);
+ if (obj)
+ attr = obj->attribute;
+ mutex_unlock(&normalkey_lock);
+
+ return attr;
+}
+
+static ssize_t _amlkey_size_normal(const uint8_t *name)
+{
+ unsigned int size = 0;
+ struct storage_object *obj;
+
+ mutex_lock(&normalkey_lock);
+ obj = normalkey_get(name);
+ if (obj)
+ size = obj->datasize;
+ mutex_unlock(&normalkey_lock);
+
+ return size;
+}
+
+static ssize_t _amlkey_read_normal(const uint8_t *name, uint8_t *buffer, uint32_t len)
+{
+ unsigned int size = 0;
+ struct storage_object *obj;
+
+ mutex_lock(&normalkey_lock);
+ obj = normalkey_get(name);
+ if (obj && len >= obj->datasize) {
+ size = obj->datasize;
+ memcpy(buffer, obj->dataptr, size);
+ }
+ mutex_unlock(&normalkey_lock);
+
+ return size;
+}
+
+static ssize_t _amlkey_write_normal(const uint8_t *name, uint8_t *buffer,
+ uint32_t len, uint32_t attr)
+{
+ int ret;
+ uint32_t wrtsz = 0;
+
+ if (attr & OBJ_ATTR_SECURE) {
+ pr_err("can't write secure key\n");
+ return 0;
+ }
+
+ mutex_lock(&normalkey_lock);
+ ret = normalkey_add(name, buffer, len, attr);
+ if (ret) {
+ pr_err("write key fail\n");
+ ret = 0;
+ goto unlock;
+ }
+
+ ret = normalkey_writetoblock(normal_block, normal_flashsize);
+ if (ret) {
+ pr_err("write block fail\n");
+ ret = 0;
+ goto unlock;
+ }
+
+ ret = _store_key_write(normal_block,
+ normal_flashsize,
+ &wrtsz);
+ if (ret) {
+ pr_err("write storage fail\n");
+ ret = 0;
+ goto unlock;
+ }
+ ret = len;
+unlock:
+ mutex_unlock(&normalkey_lock);
+ return ret;
+}
+
+static int32_t _amlkey_hash_normal(const uint8_t *name, uint8_t *hash)
+{
+ int ret = -1;
+ struct storage_object *obj;
+
+ mutex_lock(&normalkey_lock);
+ obj = normalkey_get(name);
+ if (obj) {
+ ret = 0;
+ memcpy(hash, obj->hashptr, 32);
+ }
+ mutex_unlock(&normalkey_lock);
+
+ return ret;
+}
+
+int normal_key_init(const void* dt_addr)
+{
+ uint32_t blksz = 0;
+ int nodeoffset;
+ char *pblksz;
+
+ if (!dt_addr || fdt_check_header(dt_addr)!= 0) {
+ goto blkalloc;
+ }
+
+ nodeoffset = fdt_path_offset(dt_addr, "/unifykey");
+ if (nodeoffset < 0) {
+ goto blkalloc;
+ }
+
+ pblksz = (char*)fdt_getprop((const void *)dt_addr, nodeoffset, "blocksize",NULL);
+ if (pblksz) {
+ blksz = be32_to_cpup((unsigned int*)pblksz);
+ }
+
+ if (blksz && PAGE_ALIGNED(blksz)) {
+ normal_blksz = blksz;
+ pr_info("block size from config: %x\n", blksz);
+ }
+
+blkalloc:
+ normal_block = malloc(normal_blksz);
+ if (!normal_block) {
+ pr_err("malloc block buffer fail: %x\n", normal_blksz);
+ return -1;
+ }
+
+ return 0;
+}
+
+enum amlkey_if_type {
+ IFTYPE_SECURE_STORAGE,
+ IFTYPE_NORMAL_STORAGE,
+ IFTYPE_MAX
+};
+
+struct amlkey_if amlkey_ifs[] = {
+ [IFTYPE_SECURE_STORAGE] = {
+ .init = _amlkey_init,
+ .exsit = _amlkey_isexsit,
+ .get_attr = _amlkey_get_attr,
+ .size = _amlkey_size,
+ .read = _amlkey_read,
+ .write = _amlkey_write,
+ .hash = _amlkey_hash_4_secure,
+ },
+ [IFTYPE_NORMAL_STORAGE] = {
+ .init = _amlkey_init_normal,
+ .exsit = _amlkey_exist_normal,
+ .get_attr = _amlkey_get_attr_normal,
+ .size = _amlkey_size_normal,
+ .read = _amlkey_read_normal,
+ .write = _amlkey_write_normal,
+ .hash = _amlkey_hash_normal,
+ }
+};
+
+struct amlkey_if *amlkey_if = &amlkey_ifs[IFTYPE_SECURE_STORAGE];
+int amlkey_if_init(const void* dt_addr)
+{
+ static int inited = 0;
+ uint32_t buffer_size;
+ int ret = 0;
+
+ if (inited)
+ return 0;
+ inited = 1;
+
+ if (secure_storage_getbuffer(&buffer_size)) {
+ amlkey_if = &amlkey_ifs[IFTYPE_SECURE_STORAGE];
+ return ret;
+ }
+
+ pr_info("normal key used!\n");
+ ret = normal_key_init(dt_addr);
+ amlkey_if = &amlkey_ifs[IFTYPE_NORMAL_STORAGE];
+
+ return ret;
+}
diff --git a/drivers/ata/Kconfig b/drivers/ata/Kconfig
index a2b6d09..49a056e 100644
--- a/drivers/ata/Kconfig
+++ b/drivers/ata/Kconfig
@@ -111,4 +111,3 @@
If unsure, say N.
endmenu
-
diff --git a/drivers/axi/Kconfig b/drivers/axi/Kconfig
index ba69eb6..f81d843 100644
--- a/drivers/axi/Kconfig
+++ b/drivers/axi/Kconfig
@@ -30,4 +30,3 @@
environment.
endif
-
diff --git a/drivers/block/Kconfig b/drivers/block/Kconfig
index f23ea35..33f4aa2 100644
--- a/drivers/block/Kconfig
+++ b/drivers/block/Kconfig
@@ -64,4 +64,3 @@
This allows access to raw blocks and filesystems on an IDE drive
from U-Boot. See also CMD_IDE which provides an 'ide' command for
performing various IDE operations.
-
diff --git a/drivers/board/Kconfig b/drivers/board/Kconfig
index d55151e..2a3fc9c 100644
--- a/drivers/board/Kconfig
+++ b/drivers/board/Kconfig
@@ -20,4 +20,3 @@
Support querying device information for the Sandbox boards.
endif
-
diff --git a/drivers/bootcount/Kconfig b/drivers/bootcount/Kconfig
index d276832..b7c29f2 100644
--- a/drivers/bootcount/Kconfig
+++ b/drivers/bootcount/Kconfig
@@ -162,4 +162,3 @@
Set the magic value used for the boot counter.
endif
-
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 2a22878..ce42f4c 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -130,4 +130,3 @@
Support for the clock driver of the MPC83xx series of SoCs.
endmenu
-
diff --git a/drivers/clk/at91/Kconfig b/drivers/clk/at91/Kconfig
index d7bb1b4..8d482a2 100644
--- a/drivers/clk/at91/Kconfig
+++ b/drivers/clk/at91/Kconfig
@@ -54,4 +54,3 @@
that may be different from the system clock. This second
clock is the generic clock (GCLK) and is managed by
the PMC via PMC_PCR register.
-
diff --git a/drivers/clk/exynos/Kconfig b/drivers/clk/exynos/Kconfig
index 8a73083..eb0efa9 100644
--- a/drivers/clk/exynos/Kconfig
+++ b/drivers/clk/exynos/Kconfig
@@ -16,4 +16,3 @@
on Samsung Exynos7420 SoC.
endmenu
-
diff --git a/drivers/clk/imx/Kconfig b/drivers/clk/imx/Kconfig
index 64d7656..a6fb58d 100644
--- a/drivers/clk/imx/Kconfig
+++ b/drivers/clk/imx/Kconfig
@@ -4,4 +4,3 @@
select CLK
help
This enables support clock driver for i.MX8 platforms.
-
diff --git a/drivers/clk/meson/Kconfig b/drivers/clk/meson/Kconfig
index a0d2a23..57edb6b 100644
--- a/drivers/clk/meson/Kconfig
+++ b/drivers/clk/meson/Kconfig
@@ -2,6 +2,54 @@
bool "Support G12A/G12B Clock"
depends on CLK
help
- This option is used to enable the meson g12a clock
- driver.
+ This option is used to enable the meson g12a clock
+ driver.
+config CLK_MESON_A1
+ bool "Support A1 Clock"
+ depends on CLK
+ help
+ This option is used to enable the meson a1 clock
+ driver.
+
+config CLK_MESON_C1
+ bool "Support C1 Clock"
+ depends on CLK
+ help
+ This option is used to enable the meson c1 clock
+ driver.
+
+config CLK_MESON_S4
+ bool "Support S4 Clock"
+ depends on CLK
+ help
+ This option is used to enable the meson s4 clock
+ driver
+
+config CLK_MESON_SC2
+ bool "Support SC2 Clock"
+ depends on CLK
+ help
+ This option is used to enable the meson sc2 clock
+ driver
+
+config CLK_MESON_C2
+ bool "Support C2 Clock"
+ depends on CLK
+ help
+ This option is used to enable the meson c2 clock
+ driver.
+
+config CLK_MESON_T7
+ bool "Support T7 Clock"
+ depends on CLK
+ help
+ This option is used to enable the meson t7 clock
+ driver
+
+config CLK_MESON_C2
+ bool "Support C2 Clock"
+ depends on CLK
+ help
+ This option is used to enable the meson c2 clock
+ driver.
diff --git a/drivers/clk/meson/Makefile b/drivers/clk/meson/Makefile
index bdb3ccf..1ebd125 100644
--- a/drivers/clk/meson/Makefile
+++ b/drivers/clk/meson/Makefile
@@ -4,4 +4,10 @@
# SPDX-License-Identifier: GPL-2.0+
#
obj-$(CONFIG_CLK_MESON) += clk.o
-obj-$(CONFIG_CLK_MESON_G12) += clk_meson_g12.o
+obj-$(CONFIG_CLK_MESON_G12) += clk_meson_g12.o clk_measure.o
+obj-$(CONFIG_CLK_MESON_A1) += clk_meson_a1.o clk_measure.o
+obj-$(CONFIG_CLK_MESON_C1) += clk_meson_c1.o clk_measure.o
+obj-$(CONFIG_CLK_MESON_S4) += clk_meson_s4.o clk_measure.o
+obj-$(CONFIG_CLK_MESON_SC2) += clk_meson_sc2.o clk_measure.o
+obj-$(CONFIG_CLK_MESON_C2) += clk_meson_c2.o clk_measure.o
+obj-$(CONFIG_CLK_MESON_T7) += clk_meson_t7.o clk_measure.o
diff --git a/drivers/clk/meson/clk.c b/drivers/clk/meson/clk.c
index 34d071a..76afe1c 100644
--- a/drivers/clk/meson/clk.c
+++ b/drivers/clk/meson/clk.c
@@ -1,8 +1,8 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2018 - Jian Hu <jian.hu@amlogic.com>
- * Author: Jian Hu <jian.hu@amlogic.com>
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include <common.h>
#include <asm/io.h>
#include <clk-uclass.h>
@@ -118,10 +118,11 @@
unsigned int div_val)
{
unsigned int val;
+ unsigned int div_max = (1 << div->width) - 1;
val = readl(priv->addr + div->reg);
- val &= ~((1 << div->width) - 1);
- val |= (div_val & ((1 << div->width) - 1)) << div->shift;
+ val &= ~(div_max << div->shift);
+ val |= min_t(unsigned int, div_val, div_max) << div->shift;
writel(val, priv->addr + div->reg);
return 0;
diff --git a/drivers/clk/meson/clk_measure.c b/drivers/clk/meson/clk_measure.c
new file mode 100644
index 0000000..54306d4
--- /dev/null
+++ b/drivers/clk/meson/clk_measure.c
@@ -0,0 +1,55 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/arch/clk_measure_tab.h>
+#include <asm/arch/io.h>
+#include <asm/arch/secure_apb.h>
+
+unsigned long clk_util_clk_msr(unsigned long clk_mux)
+{
+ unsigned int regval = 0;
+
+ writel(0, MSR_CLK_REG0);
+ /* Set the measurement gate to 64uS */
+ /* 64uS is enough for measure the frequence? */
+ setbits_le32(MSR_CLK_REG0, 64 - 1);
+ /* Disable continuous measurement */
+ /* Disable interrupts */
+ clrbits_le32(MSR_CLK_REG0, (1 << 17) | (1 << 18));
+ clrbits_le32(MSR_CLK_REG0, 0x7f << 20);
+ setbits_le32(MSR_CLK_REG0, (clk_mux) << 20 | (1 << 19) | (1 << 16));
+ /* Wait for the measurement to be done */
+ regval = readl(MSR_CLK_REG0);
+ do {
+ regval = readl(MSR_CLK_REG0);
+ } while (regval & (1 << 31));
+
+ /* Disable measuring */
+ clrbits_le32(MSR_CLK_REG0, 1 << 16);
+ regval = (readl(MSR_CLK_REG2) + 31) & 0x000fffff;
+
+ return (regval >> 6);
+}
+
+int clk_msr(int index)
+{
+ unsigned int index_total = sizeof(clk_msr_table) / sizeof(clk_msr_table[0]);
+ int i;
+
+ if (index == 0xff) {
+ for (i = 0; i < index_total; i++)
+ printf("[%4d][%4ld MHz] %s\n", i, clk_util_clk_msr(i), clk_msr_table[i]);
+ } else {
+ if (index >= index_total) {
+ printf("clk msr legal range: [0-%d]\n", index_total-1);
+ return -1;
+ }
+ printf("[%4d][%4ld MHz] %s\n", index, clk_util_clk_msr(index), clk_msr_table[index]);
+ }
+
+ return 0;
+}
diff --git a/drivers/clk/meson/clk_meson.h b/drivers/clk/meson/clk_meson.h
index ce72e78..ce39682 100644
--- a/drivers/clk/meson/clk_meson.h
+++ b/drivers/clk/meson/clk_meson.h
@@ -1,8 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * (C) Copyright 2018 - Beniamino Galvani <b.galvani@gmail.com>
- * (C) Copyright 2018 - BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef CLK_MESON_H
@@ -55,6 +53,7 @@
struct meson_clk {
void __iomem *addr;
struct clk clkin;
+ u32 actual_rate;
};
/* MPLL Parameters */
diff --git a/drivers/clk/meson/clk_meson_a1.c b/drivers/clk/meson/clk_meson_a1.c
new file mode 100644
index 0000000..83b155c
--- /dev/null
+++ b/drivers/clk/meson/clk_meson_a1.c
@@ -0,0 +1,217 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <dt-bindings/clock/a1-clkc.h>
+#include "clk_meson.h"
+
+/* change it later */
+#define SYS_CLK 64000000
+
+/* clk81 gates */
+static struct meson_gate gates[] = {
+ {CLKID_SPIFC_XTAL_GATE, A1_SPIFC_CLK_CTRL, 15},
+ {CLKID_SPIFC_GATE, A1_SPIFC_CLK_CTRL, 8},
+ {CLKID_SPICC_A_GATE, A1_SPICC_CLK_CTRL, 8},
+ {CLKID_SAR_ADC_GATE, A1_SAR_ADC_CLK_CTRL, 8},
+ {CLKID_SD_EMMC_XTAL_GATE, A1_SD_EMMC_CLK_CTRL, 15},
+ {CLKID_SD_EMMC_GATE, A1_SD_EMMC_CLK_CTRL, 8},
+ {CLKID_I2C_M_A, A1_SYS_CLK_EN0, 23},
+ {CLKID_I2C_M_B, A1_SYS_CLK_EN0, 22},
+ {CLKID_I2C_M_C, A1_SYS_CLK_EN0, 21},
+ {CLKID_I2C_M_D, A1_SYS_CLK_EN0, 20},
+};
+
+static unsigned int spifc_parents[] = {CLKID_FCLK_DIV2, CLKID_FCLK_DIV3,
+CLKID_FCLK_DIV5, CLKID_UNREALIZED};
+
+static unsigned int saradc_parents[] = {CLKID_XTAL, CLKID_SYS_CLK};
+static unsigned int sd_emmc_parents[] = {CLKID_FCLK_DIV2, CLKID_FCLK_DIV3,
+CLKID_FCLK_DIV5, CLKID_UNREALIZED};
+
+static struct meson_mux muxes[] = {
+ {CLKID_SPIFC_MUX, A1_SPIFC_CLK_CTRL, 9, 0x3, spifc_parents, ARRAY_SIZE(spifc_parents)},
+ {CLKID_SPICC_A_MUX, A1_SPICC_CLK_CTRL, 9, 0x7, spifc_parents, ARRAY_SIZE(spifc_parents)},
+ {CLKID_SARADC_MUX, A1_SAR_ADC_CLK_CTRL, 9, 0x1, saradc_parents, ARRAY_SIZE(saradc_parents)},
+ {CLKID_SD_EMMC_MUX, A1_SD_EMMC_CLK_CTRL, 9, 0x3, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
+};
+
+static struct meson_div divs[] = {
+ {CLKID_SPIFC_DIV, A1_SPIFC_CLK_CTRL, 0, 8, CLKID_SPIFC_MUX},
+ {CLKID_SPICC_A_DIV, A1_SPICC_CLK_CTRL, 0, 8, CLKID_SPICC_A_MUX},
+ {CLKID_SARADC_DIV, A1_SAR_ADC_CLK_CTRL, 0, 8, CLKID_SARADC_MUX},
+ {CLKID_SD_EMMC_DIV, A1_SD_EMMC_CLK_CTRL, 0, 8, CLKID_SD_EMMC_MUX},
+};
+
+static struct parm meson_fixed_pll_parm[3] = {
+ {A1_ANACTRL_FIXPLL_CTRL0, 0, 8}, /* pm */
+ {A1_ANACTRL_FIXPLL_CTRL0, 10, 5}, /* pn */
+ /* {ANACTRL_FIXPLL_CTRL0, 16, 2}, pod */
+};
+
+static struct parm meson_sys_pll_parm[3] = {
+ {A1_ANACTRL_SYSPLL_CTRL0, 0, 8}, /* pm */
+ {A1_ANACTRL_SYSPLL_CTRL0, 10, 5}, /* pn */
+ /* {A1_ANACTRL_SYSPLL_CTRL0, 16, 2}, pod */
+};
+
+static int meson_clk_enable(struct clk *clk)
+{
+ return meson_set_gate_by_id(clk, gates, ARRAY_SIZE(gates), true);
+}
+
+static int meson_clk_disable(struct clk *clk)
+{
+ return meson_set_gate_by_id(clk, gates, ARRAY_SIZE(gates), false);
+}
+
+static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
+{
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ struct parm *pm, *pn;
+ unsigned long parent_rate_mhz = clk_get_rate(&priv->clkin)/1000000;
+ u16 n, m;
+ u32 reg;
+
+ switch (id) {
+ case CLKID_FIXED_PLL:
+ pm = &meson_fixed_pll_parm[0];
+ pn = &meson_fixed_pll_parm[1];
+ /*pod = &meson_fixed_pll_parm[2];*/
+ break;
+ case CLKID_SYS_PLL:
+ pm = &meson_sys_pll_parm[0];
+ pn = &meson_sys_pll_parm[1];
+ /*pod = &meson_sys_pll_parm[2];*/
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ reg = readl(priv->addr + pn->reg_off);
+ n = PARM_GET(pn->width, pn->shift, reg);
+
+ reg = readl(priv->addr + pm->reg_off);
+ m = PARM_GET(pm->width, pm->shift, reg);
+
+ /* there is no OD in A1
+ reg = readl(priv->addr + pod->reg_off);
+ od = PARM_GET(pod->width, pod->shift, reg);
+ ((parent_rate_mhz * m / n) >> od) * 1000000;
+ */
+
+ return (parent_rate_mhz * m / n) * 1000000;
+}
+
+static ulong meson_clk_get_rate_by_id(struct clk *clk, ulong id)
+{
+ ulong rate;
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+
+ switch (id) {
+ case CLKID_XTAL:
+ rate = clk_get_rate(&priv->clkin);
+ break;
+ case CLKID_FIXED_PLL:
+ case CLKID_SYS_PLL:
+ rate = meson_pll_get_rate(clk, id);
+ break;
+ case CLKID_FCLK_DIV2:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
+ break;
+ case CLKID_FCLK_DIV3:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
+ break;
+ case CLKID_FCLK_DIV5:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
+ break;
+ case CLKID_FCLK_DIV7:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
+ break;
+ /* sys clk has realized in rom code*/
+ case CLKID_SYS_CLK:
+ rate = SYS_CLK;
+ break;
+ default:
+ rate = priv->actual_rate;
+ break;
+ }
+
+ return rate;
+}
+
+static ulong meson_clk_get_rate(struct clk *clk)
+{
+ return meson_clk_get_rate_by_id(clk, clk->id);
+}
+
+static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
+{
+ ulong div_parent, mux_parent, parent_rate;
+ unsigned int div_val;
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ unsigned int i;
+ struct meson_div *div;
+
+ for (i = 0; i < ARRAY_SIZE(divs); i++) {
+ if (clk->id == divs[i].index)
+ div = &divs[i];
+ }
+ div_parent = div->parent_index;
+ mux_parent = meson_clk_get_mux_parent(clk, muxes,
+ ARRAY_SIZE(muxes), div_parent);
+ parent_rate = meson_clk_get_rate_by_id(clk, mux_parent);
+
+ div_val = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
+
+ priv->actual_rate = DIV_ROUND_CLOSEST(parent_rate, div_val + 1);
+ meson_clk_set_div(priv, div, div_val);
+
+ return 0;
+}
+
+static int meson_clk_set_parent(struct clk* clk, struct clk* parent_clk)
+{
+ return meson_mux_set_parent_by_id(clk, muxes, ARRAY_SIZE(muxes), parent_clk);
+}
+
+static struct clk_ops meson_clk_ops = {
+ .disable = meson_clk_disable,
+ .enable = meson_clk_enable,
+ .get_rate = meson_clk_get_rate,
+ .set_rate = meson_clk_set_rate,
+ .set_parent = meson_clk_set_parent,
+};
+
+static int meson_clk_probe(struct udevice *dev)
+{
+ struct meson_clk *priv = dev_get_priv(dev);
+
+ clk_get_by_name(dev, "xtal", &priv->clkin);
+ priv->addr = dev_read_addr_ptr(dev);
+
+ debug("meson-clk: probed at addr %p\n", priv->addr);
+
+ return 0;
+}
+
+static const struct udevice_id meson_clk_ids[] = {
+ { .compatible = "amlogic,a1-clkc" },
+ { }
+};
+
+U_BOOT_DRIVER(meson_clk) = {
+ .name = "meson-clk-a1",
+ .id = UCLASS_CLK,
+ .of_match = meson_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct meson_clk),
+ .ops = &meson_clk_ops,
+ .probe = meson_clk_probe,
+};
diff --git a/drivers/clk/meson/clk_meson_c1.c b/drivers/clk/meson/clk_meson_c1.c
new file mode 100644
index 0000000..2b0d31b
--- /dev/null
+++ b/drivers/clk/meson/clk_meson_c1.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <dt-bindings/clock/c1-clkc.h>
+#include "clk_meson.h"
+
+/* change it later */
+#define SYS_CLK 166666666
+
+/* clk81 gates */
+static struct meson_gate gates[] = {
+ {CLKID_SYS_SPIFC, C1_SYS_CLK_EN1, 28},
+ {CLKID_SPIFC_GATE, C1_SPIFC_CLK_CTRL, 8},
+ {CLKID_SPIFC_XTAL_GATE, C1_SPIFC_CLK_CTRL, 15},
+ {CLKID_SAR_ADC_GATE, C1_SAR_ADC_CLK_CTRL, 8},
+ {CLKID_SPICC_A_GATE, C1_SPICC_CLK_CTRL, 8},
+ {CLKID_SPICC_B_GATE, C1_SPICC_CLK_CTRL, 24},
+ {CLKID_SD_EMMC_A_GATE, C1_SD_EMMC_CLK_CTRL, 8},
+ {CLKID_SD_EMMC_A_XTAL_GATE, C1_SD_EMMC_CLK_CTRL, 15},
+ {CLKID_SD_EMMC_B_GATE, C1_SD_EMMC_CLK_CTRL, 24},
+ {CLKID_SD_EMMC_B_XTAL_GATE, C1_SD_EMMC_CLK_CTRL, 31},
+ {CLKID_SD_EMMC_C_GATE, C1_SD_EMMC_CLK_CTRL1, 8},
+ {CLKID_SD_EMMC_C_XTAL_GATE, C1_SD_EMMC_CLK_CTRL1, 15},
+};
+
+static unsigned int spifc_parents[] = {CLKID_FCLK_DIV2, CLKID_FCLK_DIV3,
+CLKID_FCLK_DIV2P5, CLKID_UNREALIZED, CLKID_UNREALIZED,
+CLKID_FCLK_DIV4, CLKID_FCLK_DIV5, CLKID_FCLK_DIV7};
+
+static unsigned int saradc_parents[] = {CLKID_XTAL, CLKID_SYS_CLK};
+
+static unsigned int sd_emmc_parents[] = {CLKID_FCLK_DIV2, CLKID_FCLK_DIV3,
+CLKID_FCLK_DIV2P5, CLKID_UNREALIZED, CLKID_UNREALIZED,
+CLKID_FCLK_DIV4, CLKID_FCLK_DIV5, CLKID_FCLK_DIV7};
+
+static struct meson_mux muxes[] = {
+ {CLKID_SPIFC_MUX, C1_SPIFC_CLK_CTRL, 9, 0x7, spifc_parents, ARRAY_SIZE(spifc_parents)},
+ {CLKID_SARADC_MUX, C1_SAR_ADC_CLK_CTRL, 9, 0x1, saradc_parents, ARRAY_SIZE(saradc_parents)},
+ {CLKID_SPICC_A_MUX, C1_SPICC_CLK_CTRL, 9, 0x7, spifc_parents, ARRAY_SIZE(spifc_parents)},
+ {CLKID_SPICC_B_MUX, C1_SPICC_CLK_CTRL, 25, 0x7, spifc_parents, ARRAY_SIZE(spifc_parents)},
+ {CLKID_SD_EMMC_A_MUX, C1_SD_EMMC_CLK_CTRL, 9, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
+ {CLKID_SD_EMMC_B_MUX, C1_SD_EMMC_CLK_CTRL, 25, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
+ {CLKID_SD_EMMC_C_MUX, C1_SD_EMMC_CLK_CTRL1, 9, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
+};
+
+static struct meson_div divs[] = {
+ {CLKID_SPIFC_DIV, C1_SPIFC_CLK_CTRL, 0, 8, CLKID_SPIFC_MUX},
+ {CLKID_SARADC_DIV, C1_SAR_ADC_CLK_CTRL, 0, 8, CLKID_SARADC_MUX},
+ {CLKID_SPICC_A_DIV, C1_SPICC_CLK_CTRL, 0, 8, CLKID_SPICC_A_MUX},
+ {CLKID_SPICC_B_DIV, C1_SPICC_CLK_CTRL, 16, 8, CLKID_SPICC_B_MUX},
+ {CLKID_SD_EMMC_A_DIV, C1_SD_EMMC_CLK_CTRL, 0, 8, CLKID_SD_EMMC_A_MUX},
+ {CLKID_SD_EMMC_B_DIV, C1_SD_EMMC_CLK_CTRL, 16, 8, CLKID_SD_EMMC_B_MUX},
+ {CLKID_SD_EMMC_C_DIV, C1_SD_EMMC_CLK_CTRL1, 0, 8, CLKID_SD_EMMC_C_MUX},
+};
+
+static struct parm meson_fixed_pll_parm[3] = {
+ {C1_ANACTRL_FIXPLL_CTRL0, 0, 8}, /* pm */
+ {C1_ANACTRL_FIXPLL_CTRL0, 10, 5}, /* pn */
+ {C1_ANACTRL_FIXPLL_CTRL0, 16, 2}, /* pod */
+};
+
+static struct parm meson_sys_pll_parm[3] = {
+ {C1_ANACTRL_SYSPLL_CTRL0, 0, 8}, /* pm */
+ {C1_ANACTRL_SYSPLL_CTRL0, 10, 5}, /* pn */
+ {C1_ANACTRL_SYSPLL_CTRL0, 16, 2}, /* pod */
+};
+
+static int meson_clk_enable(struct clk *clk)
+{
+ return meson_set_gate_by_id(clk, gates, ARRAY_SIZE(gates), true);
+}
+
+static int meson_clk_disable(struct clk *clk)
+{
+ return meson_set_gate_by_id(clk, gates, ARRAY_SIZE(gates), false);
+}
+
+static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
+{
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ struct parm *pm, *pn, *pod;
+ unsigned long parent_rate_mhz = clk_get_rate(&priv->clkin)/1000000;
+ u16 n, m, od;
+ u32 reg;
+
+ switch (id) {
+ case CLKID_FIXED_PLL:
+ pm = &meson_fixed_pll_parm[0];
+ pn = &meson_fixed_pll_parm[1];
+ pod = &meson_fixed_pll_parm[2];
+ break;
+ case CLKID_SYS_PLL:
+ pm = &meson_sys_pll_parm[0];
+ pn = &meson_sys_pll_parm[1];
+ pod = &meson_sys_pll_parm[2];
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ reg = readl(priv->addr + pn->reg_off);
+ n = PARM_GET(pn->width, pn->shift, reg);
+
+ reg = readl(priv->addr + pm->reg_off);
+ m = PARM_GET(pm->width, pm->shift, reg);
+
+ /* there is OD in C1 */
+ reg = readl(priv->addr + pod->reg_off);
+ od = PARM_GET(pod->width, pod->shift, reg);
+
+ return ((parent_rate_mhz * m / n) >> od) * 1000000;
+}
+
+static ulong meson_clk_get_rate_by_id(struct clk *clk, ulong id)
+{
+ ulong rate;
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+
+ switch (id) {
+ case CLKID_XTAL:
+ rate = clk_get_rate(&priv->clkin);
+ break;
+ case CLKID_FIXED_PLL:
+ case CLKID_SYS_PLL:
+ rate = meson_pll_get_rate(clk, id);
+ break;
+ case CLKID_FCLK_DIV2:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
+ break;
+ case CLKID_FCLK_DIV3:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
+ break;
+ case CLKID_FCLK_DIV4:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
+ break;
+ case CLKID_FCLK_DIV5:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
+ break;
+ case CLKID_FCLK_DIV7:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
+ break;
+ case CLKID_FCLK_DIV2P5:
+ rate = (meson_pll_get_rate(clk, CLKID_FIXED_PLL) * 2) / 5;
+ break;
+ /* sys clk has realized in rom code*/
+ case CLKID_SYS_CLK:
+ rate = SYS_CLK;
+ break;
+ default:
+ rate = priv->actual_rate;
+ break;
+ }
+
+ return rate;
+}
+
+static ulong meson_clk_get_rate(struct clk *clk)
+{
+ return meson_clk_get_rate_by_id(clk, clk->id);
+}
+
+static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
+{
+ ulong div_parent, mux_parent, parent_rate;
+ unsigned int div_val;
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ unsigned int i;
+ struct meson_div *div = NULL;
+
+ for (i = 0; i < ARRAY_SIZE(divs); i++) {
+ if (clk->id == divs[i].index)
+ div = &divs[i];
+ }
+ div_parent = div->parent_index;
+ mux_parent = meson_clk_get_mux_parent(clk, muxes,
+ ARRAY_SIZE(muxes), div_parent);
+ parent_rate = meson_clk_get_rate_by_id(clk, mux_parent);
+
+ div_val = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
+
+ priv->actual_rate = DIV_ROUND_CLOSEST(parent_rate, div_val + 1);
+ meson_clk_set_div(priv, div, div_val);
+
+ return 0;
+}
+
+static int meson_clk_set_parent(struct clk* clk, struct clk* parent_clk)
+{
+ return meson_mux_set_parent_by_id(clk, muxes, ARRAY_SIZE(muxes), parent_clk);
+}
+
+static struct clk_ops meson_clk_ops = {
+ .disable = meson_clk_disable,
+ .enable = meson_clk_enable,
+ .get_rate = meson_clk_get_rate,
+ .set_rate = meson_clk_set_rate,
+ .set_parent = meson_clk_set_parent,
+};
+
+static int meson_clk_probe(struct udevice *dev)
+{
+ struct meson_clk *priv = dev_get_priv(dev);
+
+ clk_get_by_name(dev, "xtal", &priv->clkin);
+ priv->addr = dev_read_addr_ptr(dev);
+
+ debug("meson-clk: probed at addr %p\n", priv->addr);
+
+ return 0;
+}
+
+static const struct udevice_id meson_clk_ids[] = {
+ { .compatible = "amlogic,c1-clkc" },
+ { }
+};
+
+U_BOOT_DRIVER(meson_clk) = {
+ .name = "meson-clk-c1",
+ .id = UCLASS_CLK,
+ .of_match = meson_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct meson_clk),
+ .ops = &meson_clk_ops,
+ .probe = meson_clk_probe,
+};
diff --git a/drivers/clk/meson/clk_meson_c2.c b/drivers/clk/meson/clk_meson_c2.c
new file mode 100644
index 0000000..fa67f91
--- /dev/null
+++ b/drivers/clk/meson/clk_meson_c2.c
@@ -0,0 +1,232 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <dt-bindings/clock/c2-clkc.h>
+#include "clk_meson.h"
+
+/* change it later */
+#define SYS_CLK 166666666
+
+/* clk81 gates */
+static struct meson_gate gates[] = {
+ {CLKID_SYS_SPIFC, C2_SYS_CLK_EN1, 28},
+ {CLKID_SPIFC_GATE, C2_SPIFC_CLK_CTRL, 8},
+ {CLKID_SPIFC_XTAL_GATE, C2_SPIFC_CLK_CTRL, 15},
+ {CLKID_SAR_ADC_GATE, C2_SAR_ADC_CLK_CTRL, 8},
+ {CLKID_SPICC_A_GATE, C2_SPICC_CLK_CTRL, 8},
+ {CLKID_SPICC_B_GATE, C2_SPICC_CLK_CTRL, 24},
+ {CLKID_SD_EMMC_A_GATE, C2_SD_EMMC_CLK_CTRL, 8},
+ {CLKID_SD_EMMC_A_XTAL_GATE, C2_SD_EMMC_CLK_CTRL, 15},
+ {CLKID_SD_EMMC_B_GATE, C2_SD_EMMC_CLK_CTRL, 24},
+ {CLKID_SD_EMMC_B_XTAL_GATE, C2_SD_EMMC_CLK_CTRL, 31},
+ {CLKID_SD_EMMC_C_GATE, C2_SD_EMMC_CLK_CTRL1, 8},
+ {CLKID_SD_EMMC_C_XTAL_GATE, C2_SD_EMMC_CLK_CTRL1, 15},
+};
+
+static unsigned int spifc_parents[] = {CLKID_FCLK_DIV2, CLKID_FCLK_DIV3,
+CLKID_FCLK_DIV2P5, CLKID_UNREALIZED, CLKID_UNREALIZED,
+CLKID_FCLK_DIV4, CLKID_FCLK_DIV5, CLKID_FCLK_DIV7};
+
+static unsigned int saradc_parents[] = {CLKID_XTAL, CLKID_SYS_CLK};
+
+static unsigned int sd_emmc_parents[] = {CLKID_FCLK_DIV2, CLKID_FCLK_DIV3,
+CLKID_FCLK_DIV2P5, CLKID_UNREALIZED, CLKID_UNREALIZED,
+CLKID_FCLK_DIV4, CLKID_FCLK_DIV5, CLKID_FCLK_DIV7};
+
+static struct meson_mux muxes[] = {
+ {CLKID_SPIFC_MUX, C2_SPIFC_CLK_CTRL, 9, 0x7, spifc_parents, ARRAY_SIZE(spifc_parents)},
+ {CLKID_SARADC_MUX, C2_SAR_ADC_CLK_CTRL, 9, 0x1, saradc_parents, ARRAY_SIZE(saradc_parents)},
+ {CLKID_SPICC_A_MUX, C2_SPICC_CLK_CTRL, 9, 0x7, spifc_parents, ARRAY_SIZE(spifc_parents)},
+ {CLKID_SPICC_B_MUX, C2_SPICC_CLK_CTRL, 25, 0x7, spifc_parents, ARRAY_SIZE(spifc_parents)},
+ {CLKID_SD_EMMC_A_MUX, C2_SD_EMMC_CLK_CTRL, 9, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
+ {CLKID_SD_EMMC_B_MUX, C2_SD_EMMC_CLK_CTRL, 25, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
+ {CLKID_SD_EMMC_C_MUX, C2_SD_EMMC_CLK_CTRL1, 9, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
+};
+
+static struct meson_div divs[] = {
+ {CLKID_SPIFC_DIV, C2_SPIFC_CLK_CTRL, 0, 8, CLKID_SPIFC_MUX},
+ {CLKID_SARADC_DIV, C2_SAR_ADC_CLK_CTRL, 0, 8, CLKID_SARADC_MUX},
+ {CLKID_SPICC_A_DIV, C2_SPICC_CLK_CTRL, 0, 8, CLKID_SPICC_A_MUX},
+ {CLKID_SPICC_B_DIV, C2_SPICC_CLK_CTRL, 16, 8, CLKID_SPICC_B_MUX},
+ {CLKID_SD_EMMC_A_DIV, C2_SD_EMMC_CLK_CTRL, 0, 8, CLKID_SD_EMMC_A_MUX},
+ {CLKID_SD_EMMC_B_DIV, C2_SD_EMMC_CLK_CTRL, 16, 8, CLKID_SD_EMMC_B_MUX},
+ {CLKID_SD_EMMC_C_DIV, C2_SD_EMMC_CLK_CTRL1, 0, 8, CLKID_SD_EMMC_C_MUX},
+};
+
+static struct parm meson_fixed_pll_parm[3] = {
+ {C2_ANACTRL_FIXPLL_CTRL0, 0, 8}, /* pm */
+ {C2_ANACTRL_FIXPLL_CTRL0, 10, 5}, /* pn */
+ {C2_ANACTRL_FIXPLL_CTRL0, 16, 2}, /* pod */
+};
+
+static struct parm meson_sys_pll_parm[3] = {
+ {C2_ANACTRL_SYSPLL_CTRL0, 0, 8}, /* pm */
+ {C2_ANACTRL_SYSPLL_CTRL0, 10, 5}, /* pn */
+ {C2_ANACTRL_SYSPLL_CTRL0, 24, 2}, /* pod */
+};
+
+static int meson_clk_enable(struct clk *clk)
+{
+ return meson_set_gate_by_id(clk, gates, ARRAY_SIZE(gates), true);
+}
+
+static int meson_clk_disable(struct clk *clk)
+{
+ return meson_set_gate_by_id(clk, gates, ARRAY_SIZE(gates), false);
+}
+
+static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
+{
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ struct parm *pm, *pn, *pod;
+ unsigned long parent_rate_mhz = clk_get_rate(&priv->clkin)/1000000;
+ u16 n, m, od;
+ u32 reg;
+
+ switch (id) {
+ case CLKID_FIXED_PLL:
+ pm = &meson_fixed_pll_parm[0];
+ pn = &meson_fixed_pll_parm[1];
+ pod = &meson_fixed_pll_parm[2];
+ break;
+ case CLKID_SYS_PLL:
+ pm = &meson_sys_pll_parm[0];
+ pn = &meson_sys_pll_parm[1];
+ pod = &meson_sys_pll_parm[2];
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ reg = readl(priv->addr + pn->reg_off);
+ n = PARM_GET(pn->width, pn->shift, reg);
+
+ reg = readl(priv->addr + pm->reg_off);
+ m = PARM_GET(pm->width, pm->shift, reg);
+
+ /* there is OD in C1 */
+ reg = readl(priv->addr + pod->reg_off);
+ od = PARM_GET(pod->width, pod->shift, reg);
+
+ return ((parent_rate_mhz * m * 2 / n) >> od) * 1000000;
+}
+
+static ulong meson_clk_get_rate_by_id(struct clk *clk, ulong id)
+{
+ ulong rate;
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+
+ switch (id) {
+ case CLKID_XTAL:
+ rate = clk_get_rate(&priv->clkin);
+ break;
+ case CLKID_FIXED_PLL:
+ case CLKID_SYS_PLL:
+ rate = meson_pll_get_rate(clk, id);
+ break;
+ case CLKID_FCLK_DIV2:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
+ break;
+ case CLKID_FCLK_DIV3:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
+ break;
+ case CLKID_FCLK_DIV4:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
+ break;
+ case CLKID_FCLK_DIV5:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
+ break;
+ case CLKID_FCLK_DIV7:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
+ break;
+ case CLKID_FCLK_DIV2P5:
+ rate = (meson_pll_get_rate(clk, CLKID_FIXED_PLL) * 2) / 5;
+ break;
+ /* sys clk has realized in rom code*/
+ case CLKID_SYS_CLK:
+ rate = SYS_CLK;
+ break;
+ default:
+ rate = priv->actual_rate;
+ break;
+ }
+
+ return rate;
+}
+
+static ulong meson_clk_get_rate(struct clk *clk)
+{
+ return meson_clk_get_rate_by_id(clk, clk->id);
+}
+
+static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
+{
+ ulong div_parent, mux_parent, parent_rate;
+ unsigned int div_val;
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ unsigned int i;
+ struct meson_div *div = NULL;
+
+ for (i = 0; i < ARRAY_SIZE(divs); i++) {
+ if (clk->id == divs[i].index)
+ div = &divs[i];
+ }
+ div_parent = div->parent_index;
+ mux_parent = meson_clk_get_mux_parent(clk, muxes,
+ ARRAY_SIZE(muxes), div_parent);
+ parent_rate = meson_clk_get_rate_by_id(clk, mux_parent);
+
+ div_val = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
+
+ priv->actual_rate = DIV_ROUND_CLOSEST(parent_rate, div_val + 1);
+ meson_clk_set_div(priv, div, div_val);
+
+ return 0;
+}
+
+static int meson_clk_set_parent(struct clk* clk, struct clk* parent_clk)
+{
+ return meson_mux_set_parent_by_id(clk, muxes, ARRAY_SIZE(muxes), parent_clk);
+}
+
+static struct clk_ops meson_clk_ops = {
+ .disable = meson_clk_disable,
+ .enable = meson_clk_enable,
+ .get_rate = meson_clk_get_rate,
+ .set_rate = meson_clk_set_rate,
+ .set_parent = meson_clk_set_parent,
+};
+
+static int meson_clk_probe(struct udevice *dev)
+{
+ struct meson_clk *priv = dev_get_priv(dev);
+
+ clk_get_by_name(dev, "xtal", &priv->clkin);
+ priv->addr = dev_read_addr_ptr(dev);
+
+ debug("meson-clk: probed at addr %p\n", priv->addr);
+
+ return 0;
+}
+
+static const struct udevice_id meson_clk_ids[] = {
+ { .compatible = "amlogic,c1-clkc" },
+ { }
+};
+
+U_BOOT_DRIVER(meson_clk) = {
+ .name = "meson-clk-c2",
+ .id = UCLASS_CLK,
+ .of_match = meson_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct meson_clk),
+ .ops = &meson_clk_ops,
+ .probe = meson_clk_probe,
+};
diff --git a/drivers/clk/meson/clk_meson_g12.c b/drivers/clk/meson/clk_meson_g12.c
index 886eee5..5bc5700 100644
--- a/drivers/clk/meson/clk_meson_g12.c
+++ b/drivers/clk/meson/clk_meson_g12.c
@@ -1,7 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2018 - Jian Hu <jian.hu@amlogic.com>
- * Author: Jian Hu <jian.hu@amlogic.com>
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -15,43 +14,43 @@
/* clk81 gates */
static struct meson_gate gates[] = {
- {CLKID_MIPI_DSI_HOST, HHI_GCLK_MPEG0, 3},
- {CLKID_ETH_PHY, HHI_GCLK_MPEG0, 4},
- {CLKID_SPICC0, HHI_GCLK_MPEG0, 8},
- {CLKID_I2C, HHI_GCLK_MPEG0, 9},
- {CLKID_UART0, HHI_GCLK_MPEG0, 13},
- {CLKID_SPICC1, HHI_GCLK_MPEG0, 14},
- {CLKID_MIPI_DSI_PHY, HHI_GCLK_MPEG0, 20},
- {CLKID_SD_EMMC_A, HHI_GCLK_MPEG0, 24},
- {CLKID_SD_EMMC_B, HHI_GCLK_MPEG0, 25},
- {CLKID_SD_EMMC_C, HHI_GCLK_MPEG0, 26},
- {CLKID_ETH_CORE, HHI_GCLK_MPEG1, 3},
- {CLKID_ADC, HHI_GCLK_MPEG1, 13},
- {CLKID_UART1, HHI_GCLK_MPEG1, 16},
- {CLKID_HTX_HDCP22, HHI_GCLK_MPEG2, 3},
- {CLKID_HTX_PCLK, HHI_GCLK_MPEG2, 4},
- {CLKID_UART2, HHI_GCLK_MPEG2, 15},
- {CLKID_VCLK2_VENCI0, HHI_GCLK_OTHER, 1},
- {CLKID_VCLK2_VENCI1, HHI_GCLK_OTHER, 2},
- {CLKID_VCLK2_VENCP0, HHI_GCLK_OTHER, 3},
- {CLKID_VCLK2_VENCP1, HHI_GCLK_OTHER, 4},
- {CLKID_VCLK2_VENCT0, HHI_GCLK_OTHER, 5},
- {CLKID_VCLK2_VENCT1, HHI_GCLK_OTHER, 6},
- {CLKID_VCLK2_OTHER, HHI_GCLK_OTHER, 7},
- {CLKID_VCLK2_ENCI, HHI_GCLK_OTHER, 8},
- {CLKID_VCLK2_ENCP, HHI_GCLK_OTHER, 9},
- {CLKID_VCLK2_ENCT, HHI_GCLK_OTHER, 22},
- {CLKID_VCLK2_ENCL, HHI_GCLK_OTHER, 23},
- {CLKID_VCLK2_VENCLMMC, HHI_GCLK_OTHER, 24},
- {CLKID_VCLK2_VENCL, HHI_GCLK_OTHER, 25},
- {CLKID_VCLK2_OTHER1, HHI_GCLK_OTHER, 26},
- {CLKID_SPICC0_GATE, HHI_SPICC_CLK_CNTL, 6},
- {CLKID_SPICC1_GATE, HHI_SPICC_CLK_CNTL, 22},
- {CLKID_SARADC_GATE, AO_SAR_CLK, 8},
- {CLKID_AO_I2C, AO_CLK_GATE0, 2},
- {CLKID_SD_EMMC_A_P0_GATE, HHI_SD_EMMC_CLK_CNTL, 7},
- {CLKID_SD_EMMC_B_P0_GATE, HHI_SD_EMMC_CLK_CNTL, 23},
- {CLKID_SD_EMMC_C_P0_GATE, HHI_NAND_CLK_CNTL, 7},
+ {CLKID_MIPI_DSI_HOST, G12_HHI_GCLK_MPEG0, 3},
+ {CLKID_ETH_PHY, G12_HHI_GCLK_MPEG0, 4},
+ {CLKID_SPICC0, G12_HHI_GCLK_MPEG0, 8},
+ {CLKID_I2C, G12_HHI_GCLK_MPEG0, 9},
+ {CLKID_UART0, G12_HHI_GCLK_MPEG0, 13},
+ {CLKID_SPICC1, G12_HHI_GCLK_MPEG0, 14},
+ {CLKID_MIPI_DSI_PHY, G12_HHI_GCLK_MPEG0, 20},
+ {CLKID_SD_EMMC_A, G12_HHI_GCLK_MPEG0, 24},
+ {CLKID_SD_EMMC_B, G12_HHI_GCLK_MPEG0, 25},
+ {CLKID_SD_EMMC_C, G12_HHI_GCLK_MPEG0, 26},
+ {CLKID_ETH_CORE, G12_HHI_GCLK_MPEG1, 3},
+ {CLKID_ADC, G12_HHI_GCLK_MPEG1, 13},
+ {CLKID_UART1, G12_HHI_GCLK_MPEG1, 16},
+ {CLKID_HTX_HDCP22, G12_HHI_GCLK_MPEG2, 3},
+ {CLKID_HTX_PCLK, G12_HHI_GCLK_MPEG2, 4},
+ {CLKID_UART2, G12_HHI_GCLK_MPEG2, 15},
+ {CLKID_VCLK2_VENCI0, G12_HHI_GCLK_OTHER, 1},
+ {CLKID_VCLK2_VENCI1, G12_HHI_GCLK_OTHER, 2},
+ {CLKID_VCLK2_VENCP0, G12_HHI_GCLK_OTHER, 3},
+ {CLKID_VCLK2_VENCP1, G12_HHI_GCLK_OTHER, 4},
+ {CLKID_VCLK2_VENCT0, G12_HHI_GCLK_OTHER, 5},
+ {CLKID_VCLK2_VENCT1, G12_HHI_GCLK_OTHER, 6},
+ {CLKID_VCLK2_OTHER, G12_HHI_GCLK_OTHER, 7},
+ {CLKID_VCLK2_ENCI, G12_HHI_GCLK_OTHER, 8},
+ {CLKID_VCLK2_ENCP, G12_HHI_GCLK_OTHER, 9},
+ {CLKID_VCLK2_ENCT, G12_HHI_GCLK_OTHER, 22},
+ {CLKID_VCLK2_ENCL, G12_HHI_GCLK_OTHER, 23},
+ {CLKID_VCLK2_VENCLMMC, G12_HHI_GCLK_OTHER, 24},
+ {CLKID_VCLK2_VENCL, G12_HHI_GCLK_OTHER, 25},
+ {CLKID_VCLK2_OTHER1, G12_HHI_GCLK_OTHER, 26},
+ {CLKID_SPICC0_GATE, G12_HHI_SPICC_CLK_CNTL, 6},
+ {CLKID_SPICC1_GATE, G12_HHI_SPICC_CLK_CNTL, 22},
+ {CLKID_SARADC_GATE, G12_AO_SAR_CLK, 8},
+ {CLKID_AO_I2C, G12_AO_CLK_GATE0, 2},
+ {CLKID_SD_EMMC_A_P0_GATE, G12_HHI_SD_EMMC_CLK_CNTL, 7},
+ {CLKID_SD_EMMC_B_P0_GATE, G12_HHI_SD_EMMC_CLK_CNTL, 23},
+ {CLKID_SD_EMMC_C_P0_GATE, G12_HHI_NAND_CLK_CNTL, 7},
};
static unsigned int spicc_parents[] = {CLKID_XTAL, CLKID_CLK81, CLKID_FCLK_DIV4,
@@ -63,33 +62,33 @@
static struct meson_mux muxes[] = {
- {CLKID_SPICC0_MUX, HHI_SPICC_CLK_CNTL, 7, 7, spicc_parents, ARRAY_SIZE(spicc_parents)},
- {CLKID_SPICC1_MUX, HHI_SPICC_CLK_CNTL, 23, 7, spicc_parents, ARRAY_SIZE(spicc_parents)},
- {CLKID_SARADC_MUX, AO_SAR_CLK, 9, 3, saradc_parents, ARRAY_SIZE(saradc_parents)},
- {CLKID_SD_EMMC_A_P0_MUX, HHI_SD_EMMC_CLK_CNTL, 9, 7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
- {CLKID_SD_EMMC_B_P0_MUX, HHI_SD_EMMC_CLK_CNTL, 25, 7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
- {CLKID_SD_EMMC_C_P0_MUX, HHI_NAND_CLK_CNTL, 9, 7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
+ {CLKID_SPICC0_MUX, G12_HHI_SPICC_CLK_CNTL, 7, 7, spicc_parents, ARRAY_SIZE(spicc_parents)},
+ {CLKID_SPICC1_MUX, G12_HHI_SPICC_CLK_CNTL, 23, 7, spicc_parents, ARRAY_SIZE(spicc_parents)},
+ {CLKID_SARADC_MUX, G12_AO_SAR_CLK, 9, 3, saradc_parents, ARRAY_SIZE(saradc_parents)},
+ {CLKID_SD_EMMC_A_P0_MUX, G12_HHI_SD_EMMC_CLK_CNTL, 9, 7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
+ {CLKID_SD_EMMC_B_P0_MUX, G12_HHI_SD_EMMC_CLK_CNTL, 25, 7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
+ {CLKID_SD_EMMC_C_P0_MUX, G12_HHI_NAND_CLK_CNTL, 9, 7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
};
static struct meson_div divs[] = {
- {CLKID_SPICC0_DIV, HHI_SPICC_CLK_CNTL, 0, 6, CLKID_SPICC0_MUX},
- {CLKID_SPICC1_DIV, HHI_SPICC_CLK_CNTL, 16, 7, CLKID_SPICC1_MUX},
- {CLKID_SARADC_DIV, AO_SAR_CLK, 0, 8, CLKID_SARADC_MUX},
- {CLKID_SD_EMMC_A_P0_DIV, HHI_SD_EMMC_CLK_CNTL, 0, 7, CLKID_SD_EMMC_A_P0_MUX},
- {CLKID_SD_EMMC_B_P0_DIV, HHI_SD_EMMC_CLK_CNTL, 16, 7, CLKID_SD_EMMC_B_P0_MUX},
- {CLKID_SD_EMMC_C_P0_DIV, HHI_NAND_CLK_CNTL, 0, 7, CLKID_SD_EMMC_C_P0_MUX},
+ {CLKID_SPICC0_DIV, G12_HHI_SPICC_CLK_CNTL, 0, 6, CLKID_SPICC0_MUX},
+ {CLKID_SPICC1_DIV, G12_HHI_SPICC_CLK_CNTL, 16, 6, CLKID_SPICC1_MUX},
+ {CLKID_SARADC_DIV, G12_AO_SAR_CLK, 0, 8, CLKID_SARADC_MUX},
+ {CLKID_SD_EMMC_A_P0_DIV, G12_HHI_SD_EMMC_CLK_CNTL, 0, 7, CLKID_SD_EMMC_A_P0_MUX},
+ {CLKID_SD_EMMC_B_P0_DIV, G12_HHI_SD_EMMC_CLK_CNTL, 16, 7, CLKID_SD_EMMC_B_P0_MUX},
+ {CLKID_SD_EMMC_C_P0_DIV, G12_HHI_NAND_CLK_CNTL, 0, 7, CLKID_SD_EMMC_C_P0_MUX},
};
static struct parm meson_fixed_pll_parm[3] = {
- {HHI_FIX_PLL_CNTL0, 0, 8}, /* pm */
- {HHI_FIX_PLL_CNTL0, 10, 5}, /* pn */
- {HHI_FIX_PLL_CNTL0, 16, 2}, /* pod */
+ {G12_HHI_FIX_PLL_CNTL0, 0, 8}, /* pm */
+ {G12_HHI_FIX_PLL_CNTL0, 10, 5}, /* pn */
+ {G12_HHI_FIX_PLL_CNTL0, 16, 2}, /* pod */
};
static struct parm meson_sys_pll_parm[3] = {
- {HHI_SYS_PLL_CNTL0, 0, 8}, /* pm */
- {HHI_SYS_PLL_CNTL0, 10, 5}, /* pn */
- {HHI_SYS_PLL_CNTL0, 16, 2}, /* pod */
+ {G12_HHI_SYS_PLL_CNTL0, 0, 8}, /* pm */
+ {G12_HHI_SYS_PLL_CNTL0, 10, 5}, /* pn */
+ {G12_HHI_SYS_PLL_CNTL0, 16, 2}, /* pod */
};
static int meson_clk_enable(struct clk *clk)
@@ -171,8 +170,7 @@
rate = CLK81_RATE;
break;
default:
- pr_err("Unknown clock, Can not get its rate\n");
- rate = 0;
+ rate = priv->actual_rate;
break;
}
@@ -190,7 +188,7 @@
unsigned int div_val;
struct meson_clk *priv = dev_get_priv(clk->dev);
unsigned int i;
- struct meson_div *div;
+ struct meson_div *div = NULL;
for (i = 0; i < ARRAY_SIZE(divs); i++) {
if (clk->id == divs[i].index)
@@ -203,6 +201,7 @@
div_val = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
+ priv->actual_rate = DIV_ROUND_CLOSEST(parent_rate, div_val + 1);
meson_clk_set_div(priv, div, div_val);
return 0;
diff --git a/drivers/clk/meson/clk_meson_s4.c b/drivers/clk/meson/clk_meson_s4.c
new file mode 100644
index 0000000..cc1efe9
--- /dev/null
+++ b/drivers/clk/meson/clk_meson_s4.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <dt-bindings/clock/s4-clkc.h>
+#include "clk_meson.h"
+
+/* change it later */
+#define SYS_CLK 166666666
+
+/* clk81 gates, sys_clk */
+static struct meson_gate gates[] = {
+ {CLKID_SPICC_A_GATE, S4_CLKCTRL_SPICC_CLK_CTRL, 6},
+ {CLKID_SAR_ADC_GATE, S4_CLKCTRL_SAR_CLK_CTRL, 8},
+ {CLKID_SD_EMMC_A_GATE, S4_CLKCTRL_SD_EMMC_CLK_CTRL, 7},
+ {CLKID_SD_EMMC_B_GATE, S4_CLKCTRL_SD_EMMC_CLK_CTRL, 23},
+ {CLKID_SD_EMMC_C_GATE, S4_CLKCTRL_NAND_CLK_CTRL, 7},
+};
+
+static unsigned int spicc_parents[] = {CLKID_XTAL, CLKID_SYS_CLK,
+CLKID_FCLK_DIV4, CLKID_FCLK_DIV3, CLKID_FCLK_DIV2,
+CLKID_FCLK_DIV5, CLKID_FCLK_DIV7, CLKID_UNREALIZED};
+
+static unsigned int saradc_parents[] = {CLKID_XTAL, CLKID_SYS_CLK};
+
+static unsigned int sd_emmc_parents[] = {CLKID_XTAL, CLKID_FCLK_DIV2,
+CLKID_FCLK_DIV3, CLKID_UNREALIZED, CLKID_UNREALIZED,
+CLKID_UNREALIZED, CLKID_UNREALIZED, CLKID_UNREALIZED};
+
+static struct meson_mux muxes[] = {
+ {CLKID_SPICC_A_MUX, S4_CLKCTRL_SPICC_CLK_CTRL, 7, 0x7, spicc_parents, ARRAY_SIZE(spicc_parents)},
+ {CLKID_SARADC_MUX, S4_CLKCTRL_SAR_CLK_CTRL, 9, 0x3, saradc_parents, ARRAY_SIZE(saradc_parents)},
+ {CLKID_SD_EMMC_A_MUX, S4_CLKCTRL_SD_EMMC_CLK_CTRL, 9, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
+ {CLKID_SD_EMMC_B_MUX, S4_CLKCTRL_SD_EMMC_CLK_CTRL, 25, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
+ {CLKID_SD_EMMC_C_MUX, S4_CLKCTRL_NAND_CLK_CTRL, 9, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
+};
+
+static struct meson_div divs[] = {
+ {CLKID_SPICC_A_DIV, S4_CLKCTRL_SPICC_CLK_CTRL, 0, 6, CLKID_SPICC_A_MUX},
+ {CLKID_SARADC_DIV, S4_CLKCTRL_SAR_CLK_CTRL, 0, 8, CLKID_SARADC_MUX},
+ {CLKID_SD_EMMC_A_DIV, S4_CLKCTRL_SD_EMMC_CLK_CTRL, 0, 7, CLKID_SD_EMMC_A_MUX},
+ {CLKID_SD_EMMC_B_DIV, S4_CLKCTRL_SD_EMMC_CLK_CTRL, 16, 7, CLKID_SD_EMMC_B_MUX},
+ {CLKID_SD_EMMC_C_DIV, S4_CLKCTRL_NAND_CLK_CTRL, 0, 7, CLKID_SD_EMMC_C_MUX},
+};
+
+static struct parm meson_fixed_pll_parm[3] = {
+ {S4_ANACTRL_FIXPLL_CTRL0, 0, 8}, /* pm */
+ {S4_ANACTRL_FIXPLL_CTRL0, 10, 5}, /* pn */
+ {S4_ANACTRL_FIXPLL_CTRL0, 16, 2}, /* pod */
+};
+
+static struct parm meson_sys_pll_parm[3] = {
+ {S4_ANACTRL_SYSPLL_CTRL0, 0, 8}, /* pm */
+ {S4_ANACTRL_SYSPLL_CTRL0, 10, 5}, /* pn */
+ {S4_ANACTRL_SYSPLL_CTRL0, 16, 3}, /* pod */
+};
+
+static int meson_clk_enable(struct clk *clk)
+{
+ return meson_set_gate_by_id(clk, gates, ARRAY_SIZE(gates), true);
+}
+
+static int meson_clk_disable(struct clk *clk)
+{
+ return meson_set_gate_by_id(clk, gates, ARRAY_SIZE(gates), false);
+}
+
+static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
+{
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ struct parm *pm, *pn, *pod;
+ unsigned long parent_rate_mhz = clk_get_rate(&priv->clkin)/1000000;
+ u16 n, m, od;
+ u32 reg;
+
+ switch (id) {
+ case CLKID_FIXED_PLL:
+ pm = &meson_fixed_pll_parm[0];
+ pn = &meson_fixed_pll_parm[1];
+ pod = &meson_fixed_pll_parm[2];
+ break;
+ case CLKID_SYS_PLL:
+ pm = &meson_sys_pll_parm[0];
+ pn = &meson_sys_pll_parm[1];
+ pod = &meson_sys_pll_parm[2];
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ reg = readl(priv->addr + pn->reg_off);
+ n = PARM_GET(pn->width, pn->shift, reg);
+
+ reg = readl(priv->addr + pm->reg_off);
+ m = PARM_GET(pm->width, pm->shift, reg);
+
+ /* there is OD in C1 */
+ reg = readl(priv->addr + pod->reg_off);
+ od = PARM_GET(pod->width, pod->shift, reg);
+
+ return ((parent_rate_mhz * m / n) >> od) * 1000000;
+}
+
+static ulong meson_clk_get_rate_by_id(struct clk *clk, ulong id)
+{
+ ulong rate;
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+
+ switch (id) {
+ case CLKID_XTAL:
+ rate = clk_get_rate(&priv->clkin);
+ break;
+ case CLKID_FIXED_PLL:
+ case CLKID_SYS_PLL:
+ rate = meson_pll_get_rate(clk, id);
+ break;
+ case CLKID_FCLK_DIV2:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
+ break;
+ case CLKID_FCLK_DIV3:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
+ break;
+ case CLKID_FCLK_DIV4:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
+ break;
+ case CLKID_FCLK_DIV5:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
+ break;
+ case CLKID_FCLK_DIV7:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
+ break;
+ case CLKID_FCLK_DIV2P5:
+ rate = (meson_pll_get_rate(clk, CLKID_FIXED_PLL) * 2) / 5;
+ break;
+ /* sys clk has realized in rom code*/
+ case CLKID_SYS_CLK:
+ rate = SYS_CLK;
+ break;
+ default:
+ pr_err("Unknown clock, Can not get its rate\n");
+ rate = 0;
+ break;
+ }
+
+ return rate;
+}
+
+static ulong meson_clk_get_rate(struct clk *clk)
+{
+ return meson_clk_get_rate_by_id(clk, clk->id);
+}
+
+static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
+{
+ ulong div_parent, mux_parent, parent_rate;
+ unsigned int div_val;
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ unsigned int i;
+ struct meson_div *div = NULL;
+
+ for (i = 0; i < ARRAY_SIZE(divs); i++) {
+ if (clk->id == divs[i].index)
+ div = &divs[i];
+ }
+ div_parent = div->parent_index;
+ mux_parent = meson_clk_get_mux_parent(clk, muxes,
+ ARRAY_SIZE(muxes), div_parent);
+ parent_rate = meson_clk_get_rate_by_id(clk, mux_parent);
+
+ div_val = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
+
+ meson_clk_set_div(priv, div, div_val);
+
+ return 0;
+}
+
+static int meson_clk_set_parent(struct clk* clk, struct clk* parent_clk)
+{
+ return meson_mux_set_parent_by_id(clk, muxes, ARRAY_SIZE(muxes), parent_clk);
+}
+
+static struct clk_ops meson_clk_ops = {
+ .disable = meson_clk_disable,
+ .enable = meson_clk_enable,
+ .get_rate = meson_clk_get_rate,
+ .set_rate = meson_clk_set_rate,
+ .set_parent = meson_clk_set_parent,
+};
+
+static int meson_clk_probe(struct udevice *dev)
+{
+ struct meson_clk *priv = dev_get_priv(dev);
+
+ clk_get_by_name(dev, "xtal", &priv->clkin);
+ priv->addr = dev_read_addr_ptr(dev);
+
+ debug("meson-clk: probed at addr %p\n", priv->addr);
+
+ return 0;
+}
+
+static const struct udevice_id meson_clk_ids[] = {
+ { .compatible = "amlogic,s4-clkc" },
+ { }
+};
+
+U_BOOT_DRIVER(meson_clk) = {
+ .name = "meson-clk-s4",
+ .id = UCLASS_CLK,
+ .of_match = meson_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct meson_clk),
+ .ops = &meson_clk_ops,
+ .probe = meson_clk_probe,
+};
diff --git a/drivers/clk/meson/clk_meson_sc2.c b/drivers/clk/meson/clk_meson_sc2.c
new file mode 100644
index 0000000..93b8529
--- /dev/null
+++ b/drivers/clk/meson/clk_meson_sc2.c
@@ -0,0 +1,225 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <dt-bindings/clock/sc2-clkc.h>
+#include "clk_meson.h"
+
+/* change it later */
+#define SYS_CLK 166666666
+
+/* clk81 gates, sys_clk */
+static struct meson_gate gates[] = {
+// {CLKID_SYS_SPIFC, SC2_CLKCTRL_SYS_CLK_EN0_REG0, 29},
+ {CLKID_SPICC_A_GATE, SC2_CLKCTRL_SPICC_CLK_CTRL, 6},
+ {CLKID_SPICC_B_GATE, SC2_CLKCTRL_SPICC_CLK_CTRL, 22},
+ {CLKID_SAR_ADC_GATE, SC2_CLKCTRL_SAR_CLK_CTRL0, 8},
+ {CLKID_SD_EMMC_A_GATE, SC2_CLKCTRL_SD_EMMC_CLK_CTRL, 7},
+ {CLKID_SD_EMMC_B_GATE, SC2_CLKCTRL_SD_EMMC_CLK_CTRL, 23},
+ {CLKID_SD_EMMC_C_GATE, SC2_CLKCTRL_NAND_CLK_CTRL, 7},
+};
+
+static unsigned int spicc_parents[] = {CLKID_XTAL, CLKID_SYS_CLK,
+CLKID_FCLK_DIV4, CLKID_FCLK_DIV3, CLKID_FCLK_DIV2,
+CLKID_FCLK_DIV5, CLKID_FCLK_DIV7, CLKID_UNREALIZED};
+
+static unsigned int saradc_parents[] = {CLKID_XTAL, CLKID_SYS_CLK};
+
+static unsigned int sd_emmc_parents[] = {CLKID_XTAL, CLKID_FCLK_DIV2,
+CLKID_FCLK_DIV3, CLKID_UNREALIZED, CLKID_UNREALIZED,
+CLKID_UNREALIZED, CLKID_UNREALIZED, CLKID_UNREALIZED};
+
+static struct meson_mux muxes[] = {
+ {CLKID_SPICC_A_MUX, SC2_CLKCTRL_SPICC_CLK_CTRL, 7, 0x7, spicc_parents, ARRAY_SIZE(spicc_parents)},
+ {CLKID_SPICC_B_MUX, SC2_CLKCTRL_SPICC_CLK_CTRL, 23, 0x7, spicc_parents, ARRAY_SIZE(spicc_parents)},
+ {CLKID_SARADC_MUX, SC2_CLKCTRL_SAR_CLK_CTRL0, 9, 0x3, saradc_parents, ARRAY_SIZE(saradc_parents)},
+ {CLKID_SD_EMMC_A_MUX, SC2_CLKCTRL_SD_EMMC_CLK_CTRL, 9, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
+ {CLKID_SD_EMMC_B_MUX, SC2_CLKCTRL_SD_EMMC_CLK_CTRL, 25, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
+ {CLKID_SD_EMMC_C_MUX, SC2_CLKCTRL_NAND_CLK_CTRL, 9, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
+};
+
+static struct meson_div divs[] = {
+ {CLKID_SPICC_A_DIV, SC2_CLKCTRL_SPICC_CLK_CTRL, 0, 6, CLKID_SPICC_A_MUX},
+ {CLKID_SPICC_B_DIV, SC2_CLKCTRL_SPICC_CLK_CTRL, 16, 6, CLKID_SPICC_B_MUX},
+ {CLKID_SARADC_DIV, SC2_CLKCTRL_SAR_CLK_CTRL0, 0, 8, CLKID_SARADC_MUX},
+ {CLKID_SD_EMMC_A_DIV, SC2_CLKCTRL_SD_EMMC_CLK_CTRL, 0, 7, CLKID_SD_EMMC_A_MUX},
+ {CLKID_SD_EMMC_B_DIV, SC2_CLKCTRL_SD_EMMC_CLK_CTRL, 16, 7, CLKID_SD_EMMC_B_MUX},
+ {CLKID_SD_EMMC_C_DIV, SC2_CLKCTRL_NAND_CLK_CTRL, 0, 7, CLKID_SD_EMMC_C_MUX},
+};
+
+static struct parm meson_fixed_pll_parm[3] = {
+ {SC2_ANACTRL_FIXPLL_CTRL0, 0, 8}, /* pm */
+ {SC2_ANACTRL_FIXPLL_CTRL0, 10, 5}, /* pn */
+ {SC2_ANACTRL_FIXPLL_CTRL0, 16, 2}, /* pod */
+};
+
+static struct parm meson_sys_pll_parm[3] = {
+ {SC2_ANACTRL_SYSPLL_CTRL0, 0, 8}, /* pm */
+ {SC2_ANACTRL_SYSPLL_CTRL0, 10, 5}, /* pn */
+ {SC2_ANACTRL_SYSPLL_CTRL0, 16, 3}, /* pod */
+};
+
+static int meson_clk_enable(struct clk *clk)
+{
+ return meson_set_gate_by_id(clk, gates, ARRAY_SIZE(gates), true);
+}
+
+static int meson_clk_disable(struct clk *clk)
+{
+ return meson_set_gate_by_id(clk, gates, ARRAY_SIZE(gates), false);
+}
+
+static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
+{
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ struct parm *pm, *pn, *pod;
+ unsigned long parent_rate_mhz = clk_get_rate(&priv->clkin)/1000000;
+ u16 n, m, od;
+ u32 reg;
+
+ switch (id) {
+ case CLKID_FIXED_PLL:
+ pm = &meson_fixed_pll_parm[0];
+ pn = &meson_fixed_pll_parm[1];
+ pod = &meson_fixed_pll_parm[2];
+ break;
+ case CLKID_SYS_PLL:
+ pm = &meson_sys_pll_parm[0];
+ pn = &meson_sys_pll_parm[1];
+ pod = &meson_sys_pll_parm[2];
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ reg = readl(priv->addr + pn->reg_off);
+ n = PARM_GET(pn->width, pn->shift, reg);
+
+ reg = readl(priv->addr + pm->reg_off);
+ m = PARM_GET(pm->width, pm->shift, reg);
+
+ /* there is OD in C1 */
+ reg = readl(priv->addr + pod->reg_off);
+ od = PARM_GET(pod->width, pod->shift, reg);
+
+ return ((parent_rate_mhz * m / n) >> od) * 1000000;
+}
+
+static ulong meson_clk_get_rate_by_id(struct clk *clk, ulong id)
+{
+ ulong rate;
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+
+ switch (id) {
+ case CLKID_XTAL:
+ rate = clk_get_rate(&priv->clkin);
+ break;
+ case CLKID_FIXED_PLL:
+ case CLKID_SYS_PLL:
+ rate = meson_pll_get_rate(clk, id);
+ break;
+ case CLKID_FCLK_DIV2:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
+ break;
+ case CLKID_FCLK_DIV3:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
+ break;
+ case CLKID_FCLK_DIV4:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
+ break;
+ case CLKID_FCLK_DIV5:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
+ break;
+ case CLKID_FCLK_DIV7:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
+ break;
+ case CLKID_FCLK_DIV2P5:
+ rate = (meson_pll_get_rate(clk, CLKID_FIXED_PLL) * 2) / 5;
+ break;
+ /* sys clk has realized in rom code*/
+ case CLKID_SYS_CLK:
+ rate = SYS_CLK;
+ break;
+ default:
+ rate = priv->actual_rate;
+ break;
+ }
+
+ return rate;
+}
+
+static ulong meson_clk_get_rate(struct clk *clk)
+{
+ return meson_clk_get_rate_by_id(clk, clk->id);
+}
+
+static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
+{
+ ulong div_parent, mux_parent, parent_rate;
+ unsigned int div_val;
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ unsigned int i;
+ struct meson_div *div = NULL;
+
+ for (i = 0; i < ARRAY_SIZE(divs); i++) {
+ if (clk->id == divs[i].index)
+ div = &divs[i];
+ }
+ div_parent = div->parent_index;
+ mux_parent = meson_clk_get_mux_parent(clk, muxes,
+ ARRAY_SIZE(muxes), div_parent);
+ parent_rate = meson_clk_get_rate_by_id(clk, mux_parent);
+
+ div_val = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
+
+ priv->actual_rate = DIV_ROUND_CLOSEST(parent_rate, div_val + 1);
+ meson_clk_set_div(priv, div, div_val);
+
+ return 0;
+}
+
+static int meson_clk_set_parent(struct clk* clk, struct clk* parent_clk)
+{
+ return meson_mux_set_parent_by_id(clk, muxes, ARRAY_SIZE(muxes), parent_clk);
+}
+
+static struct clk_ops meson_clk_ops = {
+ .disable = meson_clk_disable,
+ .enable = meson_clk_enable,
+ .get_rate = meson_clk_get_rate,
+ .set_rate = meson_clk_set_rate,
+ .set_parent = meson_clk_set_parent,
+};
+
+static int meson_clk_probe(struct udevice *dev)
+{
+ struct meson_clk *priv = dev_get_priv(dev);
+
+ clk_get_by_name(dev, "xtal", &priv->clkin);
+ priv->addr = dev_read_addr_ptr(dev);
+
+ debug("meson-clk: probed at addr %p\n", priv->addr);
+
+ return 0;
+}
+
+static const struct udevice_id meson_clk_ids[] = {
+ { .compatible = "amlogic,sc2-clkc" },
+ { }
+};
+
+U_BOOT_DRIVER(meson_clk) = {
+ .name = "meson-clk-sc2",
+ .id = UCLASS_CLK,
+ .of_match = meson_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct meson_clk),
+ .ops = &meson_clk_ops,
+ .probe = meson_clk_probe,
+};
diff --git a/drivers/clk/meson/clk_meson_t7.c b/drivers/clk/meson/clk_meson_t7.c
new file mode 100644
index 0000000..ebf714b
--- /dev/null
+++ b/drivers/clk/meson/clk_meson_t7.c
@@ -0,0 +1,248 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <asm/arch/clock.h>
+#include <asm/io.h>
+#include <clk-uclass.h>
+#include <div64.h>
+#include <dm.h>
+#include <dt-bindings/clock/t7-clkc.h>
+#include "clk_meson.h"
+
+/* change it later */
+#define SYS_CLK 166666666
+
+/* clk81 gates, sys_clk */
+static struct meson_gate gates[] = {
+ {CLKID_SPICC_A_GATE, T7_CLKCTRL_SPICC_CLK_CTRL, 6},
+ {CLKID_SPICC_B_GATE, T7_CLKCTRL_SPICC_CLK_CTRL, 22},
+ {CLKID_SPICC_C_GATE, T7_CLKCTRL_SPICC_CLK_CTRL1, 6},
+ {CLKID_SPICC_D_GATE, T7_CLKCTRL_SPICC_CLK_CTRL1, 22},
+ {CLKID_SPICC_E_GATE, T7_CLKCTRL_SPICC_CLK_CTRL2, 6},
+ {CLKID_SPICC_F_GATE, T7_CLKCTRL_SPICC_CLK_CTRL2, 22},
+ {CLKID_SAR_ADC_GATE, T7_CLKCTRL_SAR_CLK_CTRL0, 8},
+ {CLKID_SD_EMMC_A_GATE, T7_CLKCTRL_SD_EMMC_CLK_CTRL, 7},
+ {CLKID_SD_EMMC_B_GATE, T7_CLKCTRL_SD_EMMC_CLK_CTRL, 23},
+ {CLKID_SD_EMMC_C_GATE, T7_CLKCTRL_NAND_CLK_CTRL, 7},
+};
+
+static unsigned int spicc_parents[] = {CLKID_XTAL, CLKID_SYS_CLK,
+CLKID_FCLK_DIV4, CLKID_FCLK_DIV3, CLKID_FCLK_DIV2,
+CLKID_FCLK_DIV5, CLKID_FCLK_DIV7, CLKID_UNREALIZED};
+
+static unsigned int saradc_parents[] = {CLKID_XTAL, CLKID_SYS_CLK};
+
+static unsigned int sd_emmc_parents[] = {CLKID_XTAL, CLKID_FCLK_DIV2,
+CLKID_FCLK_DIV3, CLKID_UNREALIZED, CLKID_UNREALIZED,
+CLKID_UNREALIZED, CLKID_UNREALIZED, CLKID_GP0_PLL};
+
+static struct meson_mux muxes[] = {
+ {CLKID_SPICC_A_MUX, T7_CLKCTRL_SPICC_CLK_CTRL, 7, 0x7, spicc_parents, ARRAY_SIZE(spicc_parents)},
+ {CLKID_SPICC_B_MUX, T7_CLKCTRL_SPICC_CLK_CTRL, 23, 0x7, spicc_parents, ARRAY_SIZE(spicc_parents)},
+ {CLKID_SPICC_C_MUX, T7_CLKCTRL_SPICC_CLK_CTRL1, 7, 0x7, spicc_parents, ARRAY_SIZE(spicc_parents)},
+ {CLKID_SPICC_D_MUX, T7_CLKCTRL_SPICC_CLK_CTRL1, 23, 0x7, spicc_parents, ARRAY_SIZE(spicc_parents)},
+ {CLKID_SPICC_E_MUX, T7_CLKCTRL_SPICC_CLK_CTRL2, 7, 0x7, spicc_parents, ARRAY_SIZE(spicc_parents)},
+ {CLKID_SPICC_F_MUX, T7_CLKCTRL_SPICC_CLK_CTRL2, 23, 0x7, spicc_parents, ARRAY_SIZE(spicc_parents)},
+ {CLKID_SARADC_MUX, T7_CLKCTRL_SAR_CLK_CTRL0, 9, 0x3, saradc_parents, ARRAY_SIZE(saradc_parents)},
+ {CLKID_SD_EMMC_A_MUX, T7_CLKCTRL_SD_EMMC_CLK_CTRL, 9, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
+ {CLKID_SD_EMMC_B_MUX, T7_CLKCTRL_SD_EMMC_CLK_CTRL, 25, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
+ {CLKID_SD_EMMC_C_MUX, T7_CLKCTRL_NAND_CLK_CTRL, 9, 0x7, sd_emmc_parents, ARRAY_SIZE(sd_emmc_parents)},
+};
+
+static struct meson_div divs[] = {
+ {CLKID_SPICC_A_DIV, T7_CLKCTRL_SPICC_CLK_CTRL, 0, 6, CLKID_SPICC_A_MUX},
+ {CLKID_SPICC_B_DIV, T7_CLKCTRL_SPICC_CLK_CTRL, 16, 6, CLKID_SPICC_B_MUX},
+ {CLKID_SPICC_C_DIV, T7_CLKCTRL_SPICC_CLK_CTRL1, 0, 6, CLKID_SPICC_C_MUX},
+ {CLKID_SPICC_D_DIV, T7_CLKCTRL_SPICC_CLK_CTRL1, 16, 6, CLKID_SPICC_D_MUX},
+ {CLKID_SPICC_E_DIV, T7_CLKCTRL_SPICC_CLK_CTRL2, 0, 6, CLKID_SPICC_E_MUX},
+ {CLKID_SPICC_F_DIV, T7_CLKCTRL_SPICC_CLK_CTRL2, 16, 6, CLKID_SPICC_F_MUX},
+ {CLKID_SARADC_DIV, T7_CLKCTRL_SAR_CLK_CTRL0, 0, 8, CLKID_SARADC_MUX},
+ {CLKID_SD_EMMC_A_DIV, T7_CLKCTRL_SD_EMMC_CLK_CTRL, 0, 7, CLKID_SD_EMMC_A_MUX},
+ {CLKID_SD_EMMC_B_DIV, T7_CLKCTRL_SD_EMMC_CLK_CTRL, 16, 7, CLKID_SD_EMMC_B_MUX},
+ {CLKID_SD_EMMC_C_DIV, T7_CLKCTRL_NAND_CLK_CTRL, 0, 7, CLKID_SD_EMMC_C_MUX},
+};
+
+static struct parm meson_fixed_pll_parm[3] = {
+ {T7_ANACTRL_FIXPLL_CTRL0, 0, 8}, /* pm */
+ {T7_ANACTRL_FIXPLL_CTRL0, 10, 5}, /* pn */
+ {T7_ANACTRL_FIXPLL_CTRL0, 16, 2}, /* pod */
+};
+
+static struct parm meson_sys_pll_parm[3] = {
+ {T7_ANACTRL_SYSPLL_CTRL0, 0, 8}, /* pm */
+ {T7_ANACTRL_SYSPLL_CTRL0, 10, 5}, /* pn */
+ {T7_ANACTRL_SYSPLL_CTRL0, 16, 3}, /* pod */
+};
+
+static struct parm meson_gp0_pll_parm[3] = {
+ {T7_ANACTRL_GP0PLL_CTRL0, 0, 8}, /* pm */
+ {T7_ANACTRL_GP0PLL_CTRL0, 10, 5}, /* pn */
+ {T7_ANACTRL_GP0PLL_CTRL0, 16, 3}, /* pod */
+};
+
+static int meson_clk_enable(struct clk *clk)
+{
+ return meson_set_gate_by_id(clk, gates, ARRAY_SIZE(gates), true);
+}
+
+static int meson_clk_disable(struct clk *clk)
+{
+ return meson_set_gate_by_id(clk, gates, ARRAY_SIZE(gates), false);
+}
+
+static ulong meson_pll_get_rate(struct clk *clk, unsigned long id)
+{
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ struct parm *pm, *pn, *pod;
+ unsigned long parent_rate_mhz = clk_get_rate(&priv->clkin)/1000000;
+ u16 n, m, od;
+ u32 reg;
+
+ switch (id) {
+ case CLKID_FIXED_PLL:
+ pm = &meson_fixed_pll_parm[0];
+ pn = &meson_fixed_pll_parm[1];
+ pod = &meson_fixed_pll_parm[2];
+ break;
+ case CLKID_SYS_PLL:
+ pm = &meson_sys_pll_parm[0];
+ pn = &meson_sys_pll_parm[1];
+ pod = &meson_sys_pll_parm[2];
+ break;
+ case CLKID_GP0_PLL:
+ pm = &meson_gp0_pll_parm[0];
+ pn = &meson_gp0_pll_parm[1];
+ pod = &meson_gp0_pll_parm[2];
+ break;
+ default:
+ return -ENOENT;
+ }
+
+ reg = readl(priv->addr + pn->reg_off);
+ n = PARM_GET(pn->width, pn->shift, reg);
+
+ reg = readl(priv->addr + pm->reg_off);
+ m = PARM_GET(pm->width, pm->shift, reg);
+
+ /* there is OD in C1 */
+ reg = readl(priv->addr + pod->reg_off);
+ od = PARM_GET(pod->width, pod->shift, reg);
+
+ return ((parent_rate_mhz * m / n) >> od) * 1000000;
+}
+
+static ulong meson_clk_get_rate_by_id(struct clk *clk, ulong id)
+{
+ ulong rate;
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+
+ switch (id) {
+ case CLKID_XTAL:
+ rate = clk_get_rate(&priv->clkin);
+ break;
+ case CLKID_FIXED_PLL:
+ case CLKID_SYS_PLL:
+ case CLKID_GP0_PLL:
+ rate = meson_pll_get_rate(clk, id);
+ break;
+ case CLKID_FCLK_DIV2:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 2;
+ break;
+ case CLKID_FCLK_DIV3:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 3;
+ break;
+ case CLKID_FCLK_DIV4:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 4;
+ break;
+ case CLKID_FCLK_DIV5:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 5;
+ break;
+ case CLKID_FCLK_DIV7:
+ rate = meson_pll_get_rate(clk, CLKID_FIXED_PLL) / 7;
+ break;
+ case CLKID_FCLK_DIV2P5:
+ rate = (meson_pll_get_rate(clk, CLKID_FIXED_PLL) * 2) / 5;
+ break;
+ /* sys clk has realized in rom code*/
+ case CLKID_SYS_CLK:
+ rate = SYS_CLK;
+ break;
+ default:
+ /* only for DIV type, others such as GATE/MUX is always 0 */
+ rate = priv->actual_rate;
+ break;
+ }
+
+ return rate;
+}
+
+static ulong meson_clk_get_rate(struct clk *clk)
+{
+ return meson_clk_get_rate_by_id(clk, clk->id);
+}
+
+static ulong meson_clk_set_rate(struct clk *clk, ulong rate)
+{
+ ulong div_parent, mux_parent, parent_rate;
+ unsigned int div_val;
+ struct meson_clk *priv = dev_get_priv(clk->dev);
+ unsigned int i;
+ struct meson_div *div = NULL;
+
+ for (i = 0; i < ARRAY_SIZE(divs); i++) {
+ if (clk->id == divs[i].index)
+ div = &divs[i];
+ }
+ div_parent = div->parent_index;
+ mux_parent = meson_clk_get_mux_parent(clk, muxes,
+ ARRAY_SIZE(muxes), div_parent);
+ parent_rate = meson_clk_get_rate_by_id(clk, mux_parent);
+ div_val = DIV_ROUND_CLOSEST(parent_rate, rate) - 1;
+
+ priv->actual_rate = DIV_ROUND_CLOSEST(parent_rate, div_val + 1);
+ meson_clk_set_div(priv, div, div_val);
+
+ return 0;
+}
+
+static int meson_clk_set_parent(struct clk* clk, struct clk* parent_clk)
+{
+ return meson_mux_set_parent_by_id(clk, muxes, ARRAY_SIZE(muxes), parent_clk);
+}
+
+static struct clk_ops meson_clk_ops = {
+ .disable = meson_clk_disable,
+ .enable = meson_clk_enable,
+ .get_rate = meson_clk_get_rate,
+ .set_rate = meson_clk_set_rate,
+ .set_parent = meson_clk_set_parent,
+};
+
+static int meson_clk_probe(struct udevice *dev)
+{
+ struct meson_clk *priv = dev_get_priv(dev);
+
+ clk_get_by_name(dev, "xtal", &priv->clkin);
+ priv->addr = dev_read_addr_ptr(dev);
+
+ debug("meson-clk: probed at addr %p\n", priv->addr);
+
+ return 0;
+}
+
+static const struct udevice_id meson_clk_ids[] = {
+ { .compatible = "amlogic,t7-clkc" },
+ { }
+};
+
+U_BOOT_DRIVER(meson_clk) = {
+ .name = "meson-clk-t7",
+ .id = UCLASS_CLK,
+ .of_match = meson_clk_ids,
+ .priv_auto_alloc_size = sizeof(struct meson_clk),
+ .ops = &meson_clk_ops,
+ .probe = meson_clk_probe,
+};
diff --git a/drivers/clk/mvebu/Kconfig b/drivers/clk/mvebu/Kconfig
index 6711d51..e776a15 100644
--- a/drivers/clk/mvebu/Kconfig
+++ b/drivers/clk/mvebu/Kconfig
@@ -9,4 +9,3 @@
depends on CLK_MVEBU && ARM64
help
Enable this to support the clocks on Marvell Armada 3720 SoC.
-
diff --git a/drivers/clk/owl/Kconfig b/drivers/clk/owl/Kconfig
index 7b0a192..661f198 100644
--- a/drivers/clk/owl/Kconfig
+++ b/drivers/clk/owl/Kconfig
@@ -10,4 +10,3 @@
depends on CLK_OWL && ARM64
help
Enable support for the clocks in Actions Semi S900 SoC.
-
diff --git a/drivers/clk/renesas/Kconfig b/drivers/clk/renesas/Kconfig
index 5e2cbb5..578e6a8 100644
--- a/drivers/clk/renesas/Kconfig
+++ b/drivers/clk/renesas/Kconfig
@@ -87,4 +87,3 @@
depends on CLK_RCAR_GEN3
help
Enable this to support the clocks on Renesas R8A77995 SoC.
-
diff --git a/drivers/clk/tegra/Kconfig b/drivers/clk/tegra/Kconfig
index f5b317c..ce80b1f 100644
--- a/drivers/clk/tegra/Kconfig
+++ b/drivers/clk/tegra/Kconfig
@@ -11,4 +11,3 @@
help
Enable support for manipulating Tegra's on-SoC clocks via IPC
requests to the BPMP (Boot and Power Management Processor).
-
diff --git a/drivers/clk/uniphier/Kconfig b/drivers/clk/uniphier/Kconfig
index ca5ed25..a26ca8c 100644
--- a/drivers/clk/uniphier/Kconfig
+++ b/drivers/clk/uniphier/Kconfig
@@ -6,4 +6,3 @@
Support for clock controllers on UniPhier SoCs.
Say Y if you want to control clocks provided by System Control
block, Media I/O block, Peripheral Block.
-
diff --git a/drivers/core/Kconfig b/drivers/core/Kconfig
index 8408014..046b87a 100644
--- a/drivers/core/Kconfig
+++ b/drivers/core/Kconfig
@@ -253,4 +253,3 @@
default y if !OF_LIVE
endmenu
-
diff --git a/drivers/cpu/Kconfig b/drivers/cpu/Kconfig
index bf4617d..3d5729f 100644
--- a/drivers/cpu/Kconfig
+++ b/drivers/cpu/Kconfig
@@ -19,4 +19,3 @@
depends on CPU && RISCV
help
Support CPU cores for RISC-V architecture.
-
diff --git a/drivers/crypto/Kconfig b/drivers/crypto/Kconfig
index fc555ce..1ea116b 100644
--- a/drivers/crypto/Kconfig
+++ b/drivers/crypto/Kconfig
@@ -3,4 +3,3 @@
source drivers/crypto/fsl/Kconfig
endmenu
-
diff --git a/drivers/crypto/fsl/Kconfig b/drivers/crypto/fsl/Kconfig
index c1655b2..181a1e5 100644
--- a/drivers/crypto/fsl/Kconfig
+++ b/drivers/crypto/fsl/Kconfig
@@ -45,4 +45,3 @@
config SYS_FSL_SEC_LE
bool "Little-endian access to Freescale Secure Boot"
-
diff --git a/drivers/crypto/rsa_mod_exp/Kconfig b/drivers/crypto/rsa_mod_exp/Kconfig
index 22e95c3..6dcb39a 100644
--- a/drivers/crypto/rsa_mod_exp/Kconfig
+++ b/drivers/crypto/rsa_mod_exp/Kconfig
@@ -3,4 +3,3 @@
depends on DM
help
If you want to use driver model for RSA Modular Exponentiation, say Y.
-
diff --git a/drivers/ddr/Kconfig b/drivers/ddr/Kconfig
index ae1117d..d4b393d 100644
--- a/drivers/ddr/Kconfig
+++ b/drivers/ddr/Kconfig
@@ -1,3 +1,2 @@
source "drivers/ddr/altera/Kconfig"
source "drivers/ddr/imx/Kconfig"
-
diff --git a/drivers/ddr/altera/Kconfig b/drivers/ddr/altera/Kconfig
index 2f469a7..2b28a97 100644
--- a/drivers/ddr/altera/Kconfig
+++ b/drivers/ddr/altera/Kconfig
@@ -3,4 +3,3 @@
depends on TARGET_SOCFPGA_GEN5 || TARGET_SOCFPGA_ARRIA10
help
Enable DDR SDRAM controller for the SoCFPGA devices.
-
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index dd7b9a4..c5bd8a8 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -171,4 +171,3 @@
config SYS_FSL_ERRATUM_DDR_A003474
bool
-
diff --git a/drivers/ddr/imx/Kconfig b/drivers/ddr/imx/Kconfig
index 31f3000..7e06fb2 100644
--- a/drivers/ddr/imx/Kconfig
+++ b/drivers/ddr/imx/Kconfig
@@ -1,2 +1 @@
source "drivers/ddr/imx/imx8m/Kconfig"
-
diff --git a/drivers/ddr/imx/imx8m/Kconfig b/drivers/ddr/imx/imx8m/Kconfig
index 8803afc..71f466f 100644
--- a/drivers/ddr/imx/imx8m/Kconfig
+++ b/drivers/ddr/imx/imx8m/Kconfig
@@ -20,4 +20,3 @@
info into memory for low power use. OCRAM_S is used for this
purpose on i.MX8MM.
default 0x180000
-
diff --git a/drivers/demo/Kconfig b/drivers/demo/Kconfig
index 3d441b1..98bb633 100644
--- a/drivers/demo/Kconfig
+++ b/drivers/demo/Kconfig
@@ -28,4 +28,3 @@
works.
endmenu
-
diff --git a/drivers/dfu/Kconfig b/drivers/dfu/Kconfig
index f707a4d..4692736 100644
--- a/drivers/dfu/Kconfig
+++ b/drivers/dfu/Kconfig
@@ -48,4 +48,3 @@
endif
endmenu
-
diff --git a/drivers/dma/Kconfig b/drivers/dma/Kconfig
index 2b11bf2..1820676 100644
--- a/drivers/dma/Kconfig
+++ b/drivers/dma/Kconfig
@@ -58,4 +58,3 @@
endif
endmenu # menu "DMA Support"
-
diff --git a/drivers/efuse/Kconfig b/drivers/efuse/Kconfig
index 62cf661..3ee4047 100644
--- a/drivers/efuse/Kconfig
+++ b/drivers/efuse/Kconfig
@@ -2,4 +2,3 @@
bool "AML EFUSE Support"
help
Enable support for the Amlogic EFUSE controller.
-
diff --git a/drivers/efuse/aml_efuse.c b/drivers/efuse/aml_efuse.c
index c4e6887..bb46642 100644
--- a/drivers/efuse/aml_efuse.c
+++ b/drivers/efuse/aml_efuse.c
@@ -1,28 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (C) 2014-2018 Amlogic, Inc. All rights reserved.
- *
- * All information contained herein is Amlogic confidential.
- *
- * This software is provided to you pursuant to Software License Agreement
- * (SLA) with Amlogic Inc ("Amlogic"). This software may be used
- * only in accordance with the terms of this agreement.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification is strictly prohibited without prior written permission from
- * Amlogic.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
/*
*
* Copyright (C) 2018 Amlogic, Inc. All rights reserved.
@@ -42,6 +22,9 @@
#ifdef EFUSE_LIC0
#define ADDR_IS_FEAT_BOOT_VERIFY (EFUSE_LIC0)
#define OSET_IS_FEAT_BOOT_VERIFY (0)
+ #elif defined(OTP_LIC0)
+ #define ADDR_IS_FEAT_BOOT_VERIFY (OTP_LIC0)
+ #define OSET_IS_FEAT_BOOT_VERIFY (0)
#else
#define ADDR_IS_FEAT_BOOT_VERIFY (AO_SEC_SD_CFG10)
#define OSET_IS_FEAT_BOOT_VERIFY (4)
@@ -59,6 +42,9 @@
#ifdef EFUSE_LIC0
#define ADDR_IS_FEAT_BOOT_ENCRYPT (EFUSE_LIC0)
#define OSET_IS_FEAT_BOOT_ENCRYPT (1)
+ #elif defined(OTP_LIC0)
+ #define ADDR_IS_FEAT_BOOT_ENCRYPT (OTP_LIC0)
+ #define OSET_IS_FEAT_BOOT_ENCRYPT (1)
#else
#define ADDR_IS_FEAT_BOOT_ENCRYPT (AO_SEC_SD_CFG10)
#define OSET_IS_FEAT_BOOT_ENCRYPT (28)
@@ -70,3 +56,48 @@
#undef ADDR_IS_FEAT_BOOT_ENCRYPT
#undef OSET_IS_FEAT_BOOT_ENCRYPT
}
+
+int __attribute__((weak)) IS_FEAT_DIS_EMMC_USER(void)
+{
+ return 0;
+}
+
+int __attribute__((weak)) IS_FEAT_DIS_EMMC_BOOT_0(void)
+{
+ return 0;
+}
+
+int __attribute__((weak)) IS_FEAT_DIS_EMMC_BOOT_1(void)
+{
+ return 0;
+}
+
+int __attribute__((weak)) IS_FEAT_EN_4BL2_SNOR(void)
+{
+ return 0;
+}
+
+int __attribute__((weak)) IS_FEAT_DIS_NBL2_SNOR(void)
+{
+ return 0;
+}
+
+int __attribute__((weak)) IS_FEAT_EN_8BL2_SNAND(void)
+{
+ return 0;
+}
+
+int __attribute__((weak)) IS_FEAT_DIS_NBL2_SNAND(void)
+{
+ return 0;
+}
+
+int __attribute__((weak)) IS_FEAT_DIS_8BL2_NAND(void)
+{
+ return 0;
+}
+
+int __attribute__((weak)) IS_FEAT_DIS_NBL2_NAND(void)
+{
+ return 1;
+}
diff --git a/drivers/efuse/efuse.c b/drivers/efuse/efuse.c
index 9a6649b..09687de 100644
--- a/drivers/efuse/efuse.c
+++ b/drivers/efuse/efuse.c
@@ -1,21 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * drivers/efuse/efuse.c
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <config.h>
diff --git a/drivers/efuse/efuse_usr_space_api.c b/drivers/efuse/efuse_usr_space_api.c
index 79561ee..685310a 100644
--- a/drivers/efuse/efuse_usr_space_api.c
+++ b/drivers/efuse/efuse_usr_space_api.c
@@ -1,15 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file efuse_usr_space_api.c
- * \brief support read/write user space using keyname mode
- * mapping keyname to offset by looking /efusekey in dtb
- *
- * \version 1.0.0
- * \date 15/07/14
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2015 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include <config.h>
#include <common.h>
#include <command.h>
@@ -45,6 +38,8 @@
unsigned efusekeynum = 0;
struct efusekey_info * efusekey_infos = NULL;
+ extern int fdt_check_header(const void *fdt);
+ extern const char *fdt_strerror(int errval);
ret = fdt_check_header(dt_addr);
if (ret < 0) {
EFUSE_ERR("fdt check failed [%s]\n", fdt_strerror(ret));
@@ -52,12 +47,15 @@
}
_efuseKeyInfos.initMaigc = 0;
+ extern int fdt_path_offset(const void *fdt, const char *path);
nodeoffset = fdt_path_offset(dt_addr, "/efusekey");
if (nodeoffset < 0) {
EFUSE_ERR("not find /efusekey node [%s].\n", fdt_strerror(nodeoffset));
return __LINE__;
}
+ extern const void *fdt_getprop(const void *fdt, int nodeoffset,
+ const char *name, int *lenp);
phandle = fdt_getprop(dt_addr, nodeoffset, "keynum", NULL);
efusekeynum = be32_to_cpup((u32 *)phandle);
EFUSE_MSG("keynum is %x\n", efusekeynum);
@@ -81,6 +79,8 @@
EFUSE_ERR("don't find match %s\n", propname);
goto err;
}
+
+ extern int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle);
poffset = fdt_node_offset_by_phandle(dt_addr,
be32_to_cpup((u32 *)phandle));
if (!poffset) {
@@ -351,6 +351,7 @@
ret = hex_ascii_to_buf(input, tmpBuf, bufSz);
if (ret) {
EFUSE_ERR("Failed in change hex ascii to buf\n");
+ free(tmpBuf);
return __LINE__;
}
keydata = (char*)tmpBuf;
diff --git a/drivers/fastboot/Kconfig b/drivers/fastboot/Kconfig
index a78b630..4b45671 100644
--- a/drivers/fastboot/Kconfig
+++ b/drivers/fastboot/Kconfig
@@ -138,4 +138,3 @@
endif # FASTBOOT
endmenu
-
diff --git a/drivers/fastboot/fb_command.c b/drivers/fastboot/fb_command.c
index 200f991..862c780 100644
--- a/drivers/fastboot/fb_command.c
+++ b/drivers/fastboot/fb_command.c
@@ -10,6 +10,8 @@
#include <fb_nand.h>
#include <part.h>
#include <stdlib.h>
+#include <emmc_partitions.h>
+#include <amlogic/storage.h>
/**
* image_size - final fastboot image size
@@ -26,6 +28,8 @@
*/
static u32 fastboot_bytes_expected;
+int busy_flag;
+
static void okay(char *, char *);
static void getvar(char *, char *);
static void download(char *, char *);
@@ -33,10 +37,19 @@
static void flash(char *, char *);
static void erase(char *, char *);
#endif
+static void flashing(char *, char *);
static void reboot_bootloader(char *, char *);
+static void reboot_fastboot(char *, char *);
#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_FORMAT)
static void oem_format(char *, char *);
#endif
+static void oem_cmd(char *, char *);
+static void set_active_cmd(char *, char *);
+static void snapshot_update_cmd(char *, char *);
+
+#ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK
+extern int is_partition_logical(char* parition_name);
+#endif
static const struct {
const char *command;
@@ -50,6 +63,12 @@
.command = "download",
.dispatch = download
},
+#if !CONFIG_IS_ENABLED(NO_FASTBOOT_FLASHING)
+ [FASTBOOT_COMMAND_FLASHING] = {
+ .command = "flashing",
+ .dispatch = flashing
+ },
+#endif// #if !CONFIG_IS_ENABLED(NO_FASTBOOT_FLASHING)
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
[FASTBOOT_COMMAND_FLASH] = {
.command = "flash",
@@ -68,17 +87,25 @@
.command = "continue",
.dispatch = okay
},
- [FASTBOOT_COMMAND_REBOOT] = {
- .command = "reboot",
- .dispatch = okay
- },
[FASTBOOT_COMMAND_REBOOT_BOOTLOADER] = {
.command = "reboot-bootloader",
.dispatch = reboot_bootloader
},
+ [FASTBOOT_COMMAND_REBOOT_FASTBOOT] = {
+ .command = "reboot-fastboot",
+ .dispatch = reboot_fastboot
+ },
+ [FASTBOOT_COMMAND_REBOOT] = {
+ .command = "reboot",
+ .dispatch = okay
+ },
[FASTBOOT_COMMAND_SET_ACTIVE] = {
.command = "set_active",
- .dispatch = okay
+ .dispatch = set_active_cmd
+ },
+ [FASTBOOT_COMMAND_SNAOSHOT_UPDATE] = {
+ .command = "snapshot-update",
+ .dispatch = snapshot_update_cmd
},
#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_FORMAT)
[FASTBOOT_COMMAND_OEM_FORMAT] = {
@@ -86,8 +113,19 @@
.dispatch = oem_format,
},
#endif
+ [FASTBOOT_COMMAND_OEM] = {
+ .command = "oem",
+ .dispatch = oem_cmd,
+ },
};
+static int strcmp_l1(const char *s1, const char *s2)
+{
+ if (!s1 || !s2)
+ return -1;
+ return strncmp(s1, s2, strlen(s1));
+}
+
/**
* fastboot_handle_command - Handle fastboot command
*
@@ -105,10 +143,15 @@
strsep(&cmd_parameter, ":");
for (i = 0; i < FASTBOOT_COMMAND_COUNT; i++) {
- if (!strcmp(commands[i].command, cmd_string)) {
+ if (!strcmp_l1(commands[i].command, cmd_string)) {
if (commands[i].dispatch) {
- commands[i].dispatch(cmd_parameter,
+ if (strcmp(cmd_parameter, NULL)) {
+ commands[i].dispatch(cmd_parameter,
response);
+ } else {
+ commands[i].dispatch(cmd_string,
+ response);
+ }
return i;
} else {
break;
@@ -136,6 +179,68 @@
fastboot_okay(NULL, response);
}
+void dump_lock_info(LockData_t* info)
+{
+#if 0
+ printf("info->version_major = %d\n", info->version_major);
+ printf("info->version_minor = %d\n", info->version_minor);
+ printf("info->unlock_ability = %d\n", info->unlock_ability);
+ printf("info->lock_state = %d\n", info->lock_state);
+ printf("info->lock_critical_state = %d\n", info->lock_critical_state);
+ printf("info->lock_bootloader = %d\n", info->lock_bootloader);
+#endif
+}
+
+static const char* getvar_list[] = {
+ "version-baseband", "version-bootloader", "version", "hw-revision", "max-download-size",
+ "serialno", "product", "off-mode-charge", "variant", "battery-soc-ok",
+ "battery-voltage", "partition-type:boot", "partition-size:boot",
+ "partition-type:system", "partition-size:system", "partition-type:vendor", "partition-size:vendor",
+ "partition-type:odm", "partition-size:odm", "partition-type:data", "partition-size:data",
+ "erase-block-size", "logical-block-size", "secure", "unlocked",
+};
+
+static const char* getvar_list_dynamic[] = {
+ "hw-revision", "battery-voltage", "is-userspace", "is-logical:data",
+ "is-logical:metadata", "is-logical:misc", "is-logical:super", "is-logical:boot",
+ "is-logical:system", "is-logical:vendor", "is-logical:product", "is-logical:odm",
+ "slot-count", "max-download-size", "serialno", "product", "unlocked",
+ "secure", "super-partition-name", "version-baseband", "version-bootloader",
+ "partition-size:boot", "partition-size:metadata", "partition-size:misc",
+ "partition-size:super", "partition-size:data", "version",
+};
+
+static const char* getvar_list_dynamic_ab[] = {
+ "hw-revision", "battery-voltage", "is-userspace", "is-logical:data",
+ "is-logical:misc", "is-logical:super",
+ "is-logical:boot_a", "is-logical:boot_b", "is-logical:system_a", "is-logical:system_b",
+ "is-logical:vendor_a", "is-logical:vendor_b", "is-logical:product_a", "is-logical:product_b",
+ "is-logical:odm_a", "is-logical:odm_b",
+ "slot-count", "max-download-size", "serialno", "product", "unlocked", "has-slot:data",
+ "has-slot:metadata", "has-slot:misc", "has-slot:super", "has-slot:boot",
+ "has-slot:system", "has-slot:vendor", "has-slot:product", "has-slot:odm", "current-slot",
+ "secure", "super-partition-name", "version-baseband", "version-bootloader",
+ "partition-size:super",
+ "partition-size:boot_a", "partition-size:boot_b", "partition-size:misc",
+ "partition-size:data", "version",
+};
+
+
+static const char* getvar_list_ab[] = {
+ "version-baseband", "version-bootloader", "version", "hw-revision", "max-download-size",
+ "serialno", "product", "off-mode-charge", "variant", "battery-soc-ok",
+ "battery-voltage", "partition-type:boot_a", "partition-size:boot_a",
+ "partition-type:system_a", "partition-size:system_a", "partition-type:vendor_a", "partition-size:vendor_a",
+ "partition-type:odm_a", "partition-size:odm_a", "partition-type:data", "partition-size:data",
+ "erase-block-size", "logical-block-size", "secure", "unlocked",
+ "slot-count", "slot-suffixes","current-slot", "has-slot:bootloader", "has-slot:boot",
+ "has-slot:system", "has-slot:vendor", "has-slot:odm", "has-slot:vbmeta",
+ "has-slot:metadata", "has-slot:product", "has-slot:dtbo",
+ "slot-successful:a", "slot-unbootable:a", "slot-retry-count:a",
+ "slot-successful:b", "slot-unbootable:b", "slot-retry-count:b",
+};
+
+
/**
* getvar() - Read a config/version variable
*
@@ -144,7 +249,40 @@
*/
static void getvar(char *cmd_parameter, char *response)
{
- fastboot_getvar(cmd_parameter, response);
+ run_command("get_valid_slot", 0);
+ if (!strncmp(cmd_parameter, "all", 3)) {
+ static int cmdIndex = 0;
+ int getvar_num = 0;
+ char* cmd=cmd_parameter;
+
+ busy_flag = 1;
+
+ if (dynamic_partition && has_boot_slot == 1 && strlen(getvar_list_dynamic_ab[cmdIndex]) < 64) {
+ strncpy(cmd, getvar_list_dynamic_ab[cmdIndex], 64);
+ getvar_num = (sizeof(getvar_list_dynamic_ab) / sizeof(getvar_list_dynamic_ab[0]));
+ } else if (has_boot_slot == 1 && strlen(getvar_list_ab[cmdIndex]) < 64) {
+ strncpy(cmd, getvar_list_ab[cmdIndex], 64);
+ getvar_num = (sizeof(getvar_list_ab) / sizeof(getvar_list_ab[0]));
+ } else if (dynamic_partition && strlen(getvar_list_dynamic[cmdIndex]) < 64) {
+ strncpy(cmd, getvar_list_dynamic[cmdIndex], 64);//only support no-arg cmd
+ getvar_num = (sizeof(getvar_list_dynamic) / sizeof(getvar_list_dynamic[0]));
+ } else if (strlen(getvar_list[cmdIndex]) < 64) {
+ strncpy(cmd, getvar_list[cmdIndex], 64);//only support no-arg cmd
+ getvar_num = (sizeof(getvar_list) / sizeof(getvar_list[0]));
+ }
+ //printf("getvar_num: %d\n", getvar_num);
+ //printf("all cmd:%s\n", cmd);
+ if ( ++cmdIndex >= getvar_num) {
+ cmdIndex = 0;
+ busy_flag = 0;
+ fastboot_okay(NULL, response);
+ } else {
+ fastboot_getvar(cmd, response);
+ }
+
+ }else {
+ fastboot_getvar(cmd_parameter, response);
+ }
}
/**
@@ -266,14 +404,123 @@
*/
static void flash(char *cmd_parameter, char *response)
{
+ char name[32] = {0};
+ u64 rc = 0;
+
+ if (check_lock() == 1) {
+ printf("device is locked, can not run this cmd.Please flashing unlock & flashing unlock_critical\n");
+ fastboot_fail("locked device", response);
+ return;
+ }
+
+ printf("cmd_parameter: %s\n", cmd_parameter);
+
+#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
+#ifdef CONFIG_AML_GPT
+ struct mmc *mmc = find_mmc_device(CONFIG_FASTBOOT_FLASH_MMC_DEV);
+ if (mmc && strcmp(cmd_parameter, "bootloader") == 0) {
+ printf("try to read gpt data from bootloader.img\n");
+ struct blk_desc *dev_desc;
+ /* the max size of bootloader.img is 4M, we reserve 128k for gpt.bin
+ * so we put gpt.bin at offset 0x3DFE00
+ * 0 ~ 512 bootloader secure boot, we don't care it here.
+ * 512 ~ 0x3DFDFF original bootloader.img and 0
+ * 0x3DFE00 ~ end gpt.bin
+ */
+
+ dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
+ if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
+ printf("invalid mmc device\n");
+ fastboot_fail("invalid mmc device", response);
+ return;
+ }
+
+ if (is_valid_gpt_buf(dev_desc, fastboot_buf_addr + 0x3DFE00)) {
+ printf("printf normal bootloader.img, no gpt partition table\n");
+ } else {
+ printf("find gpt parition table, update it\n"
+ "and write bootloader to boot0/boot1\n");
+
+ if (write_mbr_and_gpt_partitions(dev_desc, fastboot_buf_addr + 0x3DFE00)) {
+ printf("%s: writing GPT partitions failed\n", __func__);
+ fastboot_fail("writing GPT partitions failed", response);
+ return;
+ }
+ if (mmc_device_init(mmc) != 0) {
+ printf(" update gpt partition table fail\n");
+ fastboot_fail("fastboot update gpt partition fail", response);
+ return;
+ }
+ printf("%s: writing GPT partitions ok\n", __func__);
+ }
+
+ if (aml_gpt_valid(mmc) == 0) {
+ printf("gpt mode\n");
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
- fastboot_mmc_flash_write(cmd_parameter, fastboot_buf_addr, image_size,
+ fastboot_mmc_flash_write("bootloader-boot0", fastboot_buf_addr, image_size,
+ response);
+ fastboot_mmc_flash_write("bootloader-boot1", fastboot_buf_addr, image_size,
+ response);
+ run_command("mmc dev 1 0;", 0);
+#endif
+ env_set("default_env", "1");
+ run_command("saveenv;", 0);
+ return;
+ }
+ }
+#endif // CONFIG_AML_GPT
+
+#if CONFIG_IS_ENABLED(CHROMECAST_AB)
+#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
+ char *slot = env_get("slot-suffixes");
+ if ((!strcmp(slot, "0") && !strcmp(cmd_parameter, "bootloader_a")) ||
+ (!strcmp(slot, "1") && !strcmp(cmd_parameter, "bootloader_b"))) {
+ fastboot_mmc_flash_write("bootloader-boot0", fastboot_buf_addr,
+ image_size, response);
+ fastboot_mmc_flash_write("bootloader-boot1", fastboot_buf_addr,
+ image_size, response);
+ run_command("mmc dev 1 0;", 0);
+ }
+#endif
+#endif
+
+#endif // CONFIG_FASTBOOT_FLASH_MMC_DEV
+
+ if (strcmp(cmd_parameter, "userdata") == 0 || strcmp(cmd_parameter, "data") == 0) {
+ rc = store_part_size("userdata");
+ if (-1 == rc)
+ strncpy(name, "data", 4);
+ else
+ strncpy(name, "userdata", 8);
+ } else if (strcmp(cmd_parameter, "dts") == 0) {
+ strncpy(name, "dtb", 3);
+ } else {
+ strncpy(name, cmd_parameter, 32);
+ }
+
+#ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK
+ if (dynamic_partition) {
+ if (is_partition_logical(name) == 0) {
+ printf("%s is logic partition, can not write here.......\n", name);
+ fastboot_fail("logic partition", response);
+ return;
+ }
+ }
+#endif
+
+#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
+ fastboot_mmc_flash_write(name, fastboot_buf_addr, image_size,
response);
#endif
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_NAND)
- fastboot_nand_flash_write(cmd_parameter, fastboot_buf_addr, image_size,
+ fastboot_nand_flash_write(name, fastboot_buf_addr, image_size,
response);
#endif
+
+ if (strcmp(name, "bootloader") == 0) {
+ env_set("default_env", "1");
+ run_command("saveenv;", 0);
+ }
}
/**
@@ -287,15 +534,308 @@
*/
static void erase(char *cmd_parameter, char *response)
{
+ char name[32] = {0};
+ u64 rc = 0;
+
+ if (check_lock() == 1) {
+ printf("device is locked, can not run this cmd.Please flashing unlock & flashing unlock_critical\n");
+ fastboot_fail("locked device", response);
+ return;
+ }
+
+ printf("cmd_parameter: %s\n", cmd_parameter);
+
+#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
+#ifdef CONFIG_AML_GPT
+ struct mmc *mmc = find_mmc_device(CONFIG_FASTBOOT_FLASH_MMC_DEV);
+ if ((mmc != NULL) && strcmp(cmd_parameter, "bootloader") == 0 && (aml_gpt_valid(mmc) == 0)) {
+ printf("we write gpt partition table to bootloader now\n");
+ printf("plese write bootloader to bootloader-boot0/bootloader-boot1\n");
+ fastboot_okay("gpt mode, skip", response);
+ return;
+ }
+#endif
+#endif
+
+ struct misc_virtual_ab_message message;
+ get_mergestatus(&message);
+
+ if (strcmp(cmd_parameter, "userdata") == 0 || strcmp(cmd_parameter, "data") == 0) {
+ rc = store_part_size("userdata");
+ if (-1 == rc)
+ strncpy(name, "data", 4);
+ else
+ strncpy(name, "userdata", 8);
+ if (message.merge_status == SNAPSHOTTED || message.merge_status == MERGING) {
+ fastboot_fail("in merge state, cannot erase data", response);
+ return;
+ }
+ } else if (strcmp(cmd_parameter, "dts") == 0) {
+ strncpy(name, "dtb", 3);
+ } else {
+ strncpy(name, cmd_parameter, 32);
+ }
+
+#ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK
+ if (dynamic_partition) {
+ if (is_partition_logical(name) == 0) {
+ printf("%s is logic partition, can not erase here.......\n", name);
+ fastboot_fail("logic partition", response);
+ return;
+ }
+ }
+#endif
+
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
- fastboot_mmc_erase(cmd_parameter, response);
+ fastboot_mmc_erase(name, response);
#endif
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_NAND)
- fastboot_nand_erase(cmd_parameter, response);
+ fastboot_nand_erase(name, response);
#endif
}
#endif
+static void set_active_cmd(char *cmd_parameter, char *response)
+{
+ char *cmd;
+ int ret = 0;
+ char str[128];
+
+ printf("cmd cb_set_active is %s\n", cmd_parameter);
+ cmd = cmd_parameter;
+
+ if (check_lock() == 1) {
+ printf("device is locked, can not run this cmd.Please flashing unlock & flashing unlock_critical\n");
+ fastboot_fail("locked device", response);
+ return;
+ }
+
+ struct misc_virtual_ab_message message;
+ get_mergestatus(&message);
+ if (message.merge_status == MERGING) {
+ fastboot_fail("in merge state, cannot set active", response);
+ return;
+ }
+
+ sprintf(str, "set_active_slot %s", cmd);
+ printf("command: %s\n", str);
+ ret = run_command(str, 0);
+ printf("ret = %d\n", ret);
+ if (ret == 0)
+ fastboot_okay(NULL, response);
+ else
+ fastboot_fail("set slot error", response);
+}
+
+static void snapshot_update_cmd(char *cmd_parameter, char *response)
+{
+ char *cmd;
+
+ printf("cmd snapshot_update_cmd is %s\n", cmd_parameter);
+ cmd = cmd_parameter;
+
+ if (check_lock() == 1) {
+ printf("device is locked, can not run this cmd.Please flashing unlock & flashing unlock_critical\n");
+ fastboot_fail("locked device", response);
+ return;
+ }
+
+ if (!strcmp_l1("cancel", cmd)) {
+ struct misc_virtual_ab_message message;
+ set_mergestatus_cancel(&message);
+ }
+ fastboot_okay(NULL, response);
+}
+
+#if !CONFIG_IS_ENABLED(NO_FASTBOOT_FLASHING)
+/**
+ * flashing() - lock/unlock.
+ *
+ * @cmd_parameter: Pointer to partition name
+ * @response: Pointer to fastboot response buffer
+ *
+ * Writes the previously downloaded image to the partition indicated by
+ * cmd_parameter. Writes to response.
+ */
+static void flashing(char *cmd_parameter, char *response)
+{
+ char *cmd;
+ char* lock_s;
+ LockData_t* info;
+ char lock_d[LOCK_DATA_SIZE];
+ u64 rc;
+
+ lock_s = env_get("lock");
+ if (!lock_s) {
+ printf("lock state is NULL \n");
+ strncpy(lock_d, "10101000", 8);
+ lock_s = "10101000";
+ env_set("lock", "10101000");
+ run_command("defenv_reserv; saveenv;", 0);
+ } else {
+ printf("lock state: %s\n", lock_s);
+ if (strlen(lock_s) > 15)
+ strncpy(lock_d, lock_s, 15);
+ else
+ strncpy(lock_d, lock_s, strlen(lock_s));
+ }
+
+ info = malloc(sizeof(struct LockData));
+ if (!info) {
+ printf("malloc error\n");
+ fastboot_fail("malloc error", response);
+ return;
+ }
+ memset(info,0,LOCK_DATA_SIZE);
+ info->version_major = (int)(lock_d[0] - '0');
+ info->version_minor = (int)(lock_d[1] - '0');
+ info->unlock_ability = (int)(lock_d[2] - '0');
+ info->lock_state = (int)(lock_d[4] - '0');
+ info->lock_critical_state = (int)(lock_d[5] - '0');
+ info->lock_bootloader = (int)(lock_d[6] - '0');
+
+ printf("cb_flashing cmd_parameter: %s\n", cmd_parameter);
+ cmd = cmd_parameter;
+ strsep(&cmd, " ");
+ printf("cb_flashing: %s\n", cmd);
+ if (!cmd) {
+ printf("missing variable\n");
+ fastboot_fail("missing var", response);
+ free(info);
+ return;
+ }
+
+ rc = store_part_size("userdata");
+
+ if (!strcmp_l1("unlock_critical", cmd)) {
+ info->lock_critical_state = 0;
+ fastboot_okay(NULL, response);
+ } else if (!strcmp_l1("lock_critical", cmd)) {
+ info->lock_critical_state = 1;
+ fastboot_okay(NULL, response);
+ } else if (!strcmp_l1("get_unlock_ability", cmd)) {
+ char str[32];
+ static bool is_unlock_ability_sent = false;
+ if (is_unlock_ability_sent) {
+ is_unlock_ability_sent = false;
+ fastboot_okay(NULL, response);
+ busy_flag = 0;
+ } else {
+ sprintf(str, "get_unlock_ability: %d",
+ info->unlock_ability);
+ fastboot_response("INFO", response, "%s", str);
+ is_unlock_ability_sent = true;
+ busy_flag = 1;
+ }
+ free(info);
+ return;
+ } else if (!strcmp_l1("get_unlock_bootloader_nonce", cmd)) {
+ char str_num[8];
+ sprintf(str_num, "%d", info->lock_critical_state);
+ fastboot_response("OKAY", response, "%s", str_num);
+ } else if (!strcmp_l1("lock_bootloader", cmd)) {
+ info->lock_bootloader = 1;
+ } else if (!strcmp_l1("unlock", cmd)) {
+ if (info->unlock_ability == 1 ) {
+ if (info->lock_state == 1 ) {
+ char *avb_s;
+ avb_s = env_get("avb2");
+ if (avb_s == NULL) {
+ run_command("get_avb_mode;", 0);
+ avb_s = env_get("avb2");
+ }
+ printf("avb2: %s\n", avb_s);
+ if (strcmp(avb_s, "1") == 0) {
+#ifdef CONFIG_AML_ANTIROLLBACK
+ if (avb_unlock()) {
+ if (-1 == rc) {
+ printf("unlocking device. Erasing data partition!\n");
+ run_command("store erase data 0 0", 0);
+ } else {
+ printf("unlocking device. Erasing userdata partition!\n");
+ run_command("store erase userdata 0 0", 0);
+ }
+ printf("unlocking device. Erasing metadata partition!\n");
+ run_command("store erase metadata 0 0", 0);
+ } else {
+ printf("unlock failed!\n");
+ }
+#else
+ if (-1 == rc) {
+ printf("unlocking device. Erasing data partition!\n");
+ run_command("store erase data 0 0", 0);
+ } else {
+ printf("unlocking device. Erasing userdata partition!\n");
+ run_command("store erase userdata 0 0", 0);
+ }
+ printf("unlocking device. Erasing metadata partition!\n");
+ run_command("store erase metadata 0 0", 0);
+#endif
+ }
+ }
+ info->lock_state = 0;
+ info->lock_critical_state = 0;
+ env_set("lock_state", "green");
+ fastboot_okay(NULL, response);
+ } else {
+ printf("unlock_ability is 0, can not unlock, please set it in android setting\n");
+ fastboot_response("FAIL", response, "%s", "unlock_ability is 0, can not unlock");
+ }
+ } else if (!strcmp_l1("lock", cmd)) {
+ if (info->lock_state == 0 ) {
+ char *avb_s;
+ avb_s = env_get("avb2");
+ if (avb_s == NULL) {
+ run_command("get_avb_mode;", 0);
+ avb_s = env_get("avb2");
+ }
+ printf("avb2: %s\n", avb_s);
+ if (strcmp(avb_s, "1") == 0) {
+#ifdef CONFIG_AML_ANTIROLLBACK
+ if (avb_lock()) {
+ printf("lock failed!\n");
+ } else {
+ if (-1 == rc) {
+ printf("locking device. Erasing data partition!\n");
+ run_command("store erase data 0 0", 0);
+ } else {
+ printf("locking device. Erasing userdata partition!\n");
+ run_command("store erase userdata 0 0", 0);
+ }
+ printf("unlocking device. Erasing metadata partition!\n");
+ run_command("store erase metadata 0 0", 0);
+ }
+#else
+ if (-1 == rc) {
+ printf("locking device. Erasing data partition!\n");
+ run_command("store erase data 0 0", 0);
+ } else {
+ printf("locking device. Erasing userdata partition!\n");
+ run_command("store erase userdata 0 0", 0);
+ }
+ printf("unlocking device. Erasing metadata partition!\n");
+ run_command("store erase metadata 0 0", 0);
+
+#endif
+ }
+ }
+ info->lock_state = 1;
+ env_set("lock_state", "orange");
+ fastboot_okay(NULL, response);
+ } else {
+ printf("unknown variable: %s\n", cmd);
+ fastboot_response("FAIL", response, "%s", "Variable not implemented");
+ }
+
+ sprintf(lock_d, "%d%d%d0%d%d%d0", info->version_major, info->version_minor, info->unlock_ability, info->lock_state, info->lock_critical_state, info->lock_bootloader);
+ printf("lock_d state: %s\n", lock_d);
+ env_set("lock", lock_d);
+ run_command("defenv_reserv; saveenv;", 0);
+ free(info);
+ return;
+}
+#endif// #if !CONFIG_IS_ENABLED(NO_FASTBOOT_FLASHING)
+
/**
* reboot_bootloader() - Sets reboot bootloader flag.
*
@@ -304,12 +844,46 @@
*/
static void reboot_bootloader(char *cmd_parameter, char *response)
{
- if (fastboot_set_reboot_flag())
- fastboot_fail("Cannot set reboot flag", response);
- else
- fastboot_okay(NULL, response);
+ fastboot_okay(NULL, response);
}
+/**
+ * reboot_fastboot() - Sets reboot fastboot flag.
+ *
+ * @cmd_parameter: Pointer to command parameter
+ * @response: Pointer to fastboot response buffer
+ */
+static void reboot_fastboot(char *cmd_parameter, char *response)
+{
+ fastboot_okay(NULL, response);
+}
+
+static void oem_cmd(char *cmd_parameter, char *response)
+{
+ char *cmd;
+ int i = 0, len = 0, j = 0;
+ char cmd_str[FASTBOOT_RESPONSE_LEN];
+ printf("oem cmd_parameter: %s\n", cmd_parameter);
+ cmd = cmd_parameter;
+ strsep(&cmd, " ");
+ printf("To run cmd[%s]\n", cmd);
+
+ len = strlen(cmd);
+ for (i = 0; i < len; i++) {
+ if (cmd[i] != '\'') {
+ cmd_str[j++] = cmd[i];
+ }
+ }
+ cmd_str[j] = '\0';
+ printf("cmd_str2: %s\n", cmd_str);
+
+ run_command(cmd_str, 0);
+
+ fastboot_okay(NULL, response);
+ return;
+}
+
+
#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_FORMAT)
/**
* oem_format() - Execute the OEM format command
diff --git a/drivers/fastboot/fb_common.c b/drivers/fastboot/fb_common.c
index c6e06aa..cc2f6a3 100644
--- a/drivers/fastboot/fb_common.c
+++ b/drivers/fastboot/fb_common.c
@@ -13,6 +13,15 @@
#include <common.h>
#include <fastboot.h>
#include <net/fastboot.h>
+#include <emmc_partitions.h>
+#include <amlogic/storage.h>
+
+#ifndef getenv
+#define getenv env_get
+#define setenv env_set
+#endif//#ifndef getenv
+
+#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
/**
* fastboot_buf_addr - base address of the fastboot download buffer
@@ -63,6 +72,17 @@
}
/**
+ * fastboot_busy() - Write a INFO response of the form "INFO$reason".
+ *
+ * @reason: Pointer to returned reason string
+ * @response: Pointer to fastboot response buffer
+ */
+void fastboot_busy(const char *reason, char *response)
+{
+ fastboot_response("INFO", response, "%s", reason);
+}
+
+/**
* fastboot_okay() - Write an OKAY response of the form "OKAY$reason".
*
* @reason: Pointer to returned reason string, or NULL to send a bare "OKAY"
@@ -77,6 +97,108 @@
}
/**
+ *check lock state
+ *return 1 if locked
+ *return 0 if unlocked
+ */
+int check_lock(void)
+{
+ char *lock_s;
+ LockData_t* info;
+
+ lock_s = env_get("lock");
+ if (!lock_s) {
+ printf("lock state is NULL \n");
+ lock_s = "10101000";
+ env_set("lock", "10101000");
+ run_command("defenv_reserv; saveenv;", 0);
+ }
+ printf("lock state: %s\n", lock_s);
+
+ info = malloc(sizeof(struct LockData));
+ if (info) {
+ memset(info,0,LOCK_DATA_SIZE);
+ info->version_major = (int)(lock_s[0] - '0');
+ info->version_minor = (int)(lock_s[1] - '0');
+ info->unlock_ability = (int)(lock_s[2] - '0');
+ info->lock_state = (int)(lock_s[4] - '0');
+ info->lock_critical_state = (int)(lock_s[5] - '0');
+ info->lock_bootloader = (int)(lock_s[6] - '0');
+
+ extern void dump_lock_info(LockData_t* info);
+ dump_lock_info(info);
+ } else
+ return 0;
+
+ if ((info->lock_state == 1 ) || ( info->lock_critical_state == 1 )) {
+ free (info);
+ return 1;
+ }
+ else {
+ free (info);
+ return 0;
+ }
+}
+
+/**
+ *get merge status
+*/
+int get_mergestatus(struct misc_virtual_ab_message *message)
+{
+ char *partition = "misc";
+ char vab_buf[1024] = {0};
+
+ if (store_read((const char *)partition,
+ SYSTEM_SPACE_OFFSET_IN_MISC, 1024, (unsigned char *)vab_buf) < 0) {
+ printf("failed to store read %s.\n", partition);
+ return -1;
+ }
+
+ run_command("get_valid_slot", 0);
+ int current_slot = 0;
+ char *slot;
+ slot = env_get("slot-suffixes");
+ if (strcmp(slot, "0") == 0) {
+ current_slot = 0;
+ } else if (strcmp(slot, "1") == 0) {
+ current_slot = 1;
+ }
+
+ memcpy(message, vab_buf, sizeof(struct misc_virtual_ab_message));
+ printf("message.merge_status: %d\n", message->merge_status);
+ printf("message.source_slot: %d\n", message->source_slot);
+ if (message->merge_status == SNAPSHOTTED && current_slot == message->source_slot) {
+ message->merge_status = NONE;
+ printf("set message.merge_status NONE\n");
+ }
+ return 0;
+}
+
+/**
+ *set merge status
+*/
+int set_mergestatus_cancel(struct misc_virtual_ab_message *message)
+{
+ char *partition = "misc";
+ char vab_buf[1024] = {0};
+
+ if (store_read((const char *)partition,
+ SYSTEM_SPACE_OFFSET_IN_MISC, 1024, (unsigned char *)vab_buf) < 0) {
+ printf("failed to store read %s.\n", partition);
+ return -1;
+ }
+
+ memcpy(message, vab_buf, sizeof(struct misc_virtual_ab_message));
+ printf("message.merge_status: %d\n", message->merge_status);
+ if (message->merge_status == SNAPSHOTTED || message->merge_status == MERGING) {
+ message->merge_status = CANCELLED;
+ printf("set message.merge_status CANCELLED\n");
+ }
+ store_write((const char *)partition, SYSTEM_SPACE_OFFSET_IN_MISC, 1024, (unsigned char *)vab_buf);
+ return 0;
+}
+
+/**
* fastboot_set_reboot_flag() - Set flag to indicate reboot-bootloader
*
* Set flag which indicates that we should reboot into the bootloader
@@ -119,7 +241,7 @@
if (s) {
run_command(s, CMD_FLAG_ENV);
} else {
- static char boot_addr_start[12];
+ static char boot_addr_start[24];
static char *const bootm_args[] = {
"bootm", boot_addr_start, NULL
};
@@ -165,5 +287,11 @@
fastboot_buf_addr = buf_addr ? buf_addr :
(void *)CONFIG_FASTBOOT_BUF_ADDR;
fastboot_buf_size = buf_size ? buf_size : CONFIG_FASTBOOT_BUF_SIZE;
+
+#if defined CONFIG_FASTBOOT_MAX_DOWN_SIZE
+ if (fastboot_buf_size > CONFIG_FASTBOOT_MAX_DOWN_SIZE)
+ fastboot_buf_size = CONFIG_FASTBOOT_MAX_DOWN_SIZE;
+#endif
+
fastboot_set_progress_callback(NULL);
}
diff --git a/drivers/fastboot/fb_getvar.c b/drivers/fastboot/fb_getvar.c
index 4d264c9..3b5a24e 100644
--- a/drivers/fastboot/fb_getvar.c
+++ b/drivers/fastboot/fb_getvar.c
@@ -10,23 +10,42 @@
#include <fb_nand.h>
#include <fs.h>
#include <version.h>
+#include <partition_table.h>
+#include <amlogic/storage.h>
static void getvar_version(char *var_parameter, char *response);
static void getvar_bootloader_version(char *var_parameter, char *response);
static void getvar_downloadsize(char *var_parameter, char *response);
static void getvar_serialno(char *var_parameter, char *response);
static void getvar_version_baseband(char *var_parameter, char *response);
+static void getvar_hw_revision(char *var_parameter, char *response);
+static void getvar_off_mode_charge(char *var_parameter, char *response);
+static void getvar_variant(char *var_parameter, char *response);
+static void getvar_battery_soc_ok(char *var_parameter, char *response);
+static void getvar_battery_voltage(char *var_parameter, char *response);
+static void getvar_block_size(char *var_parameter, char *response);
+static void getvar_secure(char *var_parameter, char *response);
+static void getvar_unlocked(char *var_parameter, char *response);
+static void getvar_is_userspace(char *var_parameter, char *response);
+static void getvar_is_logical(char *var_parameter, char *response);
+static void getvar_slot_count(char *var_parameter, char *response);
+static void getvar_super_partition_name(char *var_parameter, char *response);
+static void getvar_snapshot_update_status(char *var_parameter, char *response);
+
static void getvar_product(char *var_parameter, char *response);
static void getvar_current_slot(char *var_parameter, char *response);
static void getvar_slot_suffixes(char *var_parameter, char *response);
static void getvar_has_slot(char *var_parameter, char *response);
-#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
-static void getvar_partition_type(char *part_name, char *response);
-#endif
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
+static void getvar_partition_type(char *part_name, char *response);
static void getvar_partition_size(char *part_name, char *response);
#endif
+#ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK
+extern int is_partition_logical(char* parition_name);
+#endif
+
+
static const struct {
const char *variable;
void (*dispatch)(char *var_parameter, char *response);
@@ -41,6 +60,42 @@
.variable = "version-bootloader",
.dispatch = getvar_bootloader_version
}, {
+ .variable = "off-mode-charge",
+ .dispatch = getvar_off_mode_charge
+ }, {
+ .variable = "hw-revision",
+ .dispatch = getvar_hw_revision
+ }, {
+ .variable = "variant",
+ .dispatch = getvar_variant
+ }, {
+ .variable = "battery-soc-ok",
+ .dispatch = getvar_battery_soc_ok
+ }, {
+ .variable = "battery-voltage",
+ .dispatch = getvar_battery_voltage
+ }, {
+ .variable = "erase-block-size",
+ .dispatch = getvar_block_size
+ }, {
+ .variable = "logical-block-size",
+ .dispatch = getvar_block_size
+ }, {
+ .variable = "secure",
+ .dispatch = getvar_secure
+ }, {
+ .variable = "unlocked",
+ .dispatch = getvar_unlocked
+ }, {
+ .variable = "is-userspace",
+ .dispatch = getvar_is_userspace
+ }, {
+ .variable = "is-logical",
+ .dispatch = getvar_is_logical
+ }, {
+ .variable = "super-partition-name",
+ .dispatch = getvar_super_partition_name
+ }, {
.variable = "downloadsize",
.dispatch = getvar_downloadsize
}, {
@@ -59,12 +114,18 @@
.variable = "current-slot",
.dispatch = getvar_current_slot
}, {
+ .variable = "slot-count",
+ .dispatch = getvar_slot_count
+ }, {
.variable = "slot-suffixes",
.dispatch = getvar_slot_suffixes
}, {
- .variable = "has_slot",
+ .variable = "snapshot-update-status",
+ .dispatch = getvar_snapshot_update_status
+ }, {
+ .variable = "has-slot",
.dispatch = getvar_has_slot
-#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
+#if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
}, {
.variable = "partition-type",
.dispatch = getvar_partition_type
@@ -79,107 +140,447 @@
static void getvar_version(char *var_parameter, char *response)
{
- fastboot_okay(FASTBOOT_VERSION, response);
+ if (busy_flag == 1)
+ fastboot_response("INFOversion: ", response, "%s", FASTBOOT_VERSION);
+ else
+ fastboot_okay(FASTBOOT_VERSION, response);
}
static void getvar_bootloader_version(char *var_parameter, char *response)
{
- fastboot_okay(U_BOOT_VERSION, response);
+ char s_version[32];
+ strncpy(s_version, "01.01.", 6);
+ strcat(s_version, U_BOOT_DATE_TIME);
+ printf("s_version: %s\n", s_version);
+ if (busy_flag == 1) {
+ fastboot_response("INFOversion-bootloader: ", response, "%s", s_version);
+ } else
+ fastboot_okay(s_version, response);
+}
+
+static void getvar_hw_revision(char *var_parameter, char *response)
+{
+ if (busy_flag == 1)
+ fastboot_busy("hw-revision: 0", response);
+ else
+ fastboot_okay("0", response);
+}
+
+static void getvar_off_mode_charge(char *var_parameter, char *response)
+{
+ if (busy_flag == 1)
+ fastboot_busy("off-mode-charge: 0", response);
+ else
+ fastboot_okay("0", response);
+}
+
+static void getvar_variant(char *var_parameter, char *response)
+{
+ if (busy_flag == 1)
+ fastboot_busy("variant: US", response);
+ else
+ fastboot_okay("US", response);
+}
+
+static void getvar_battery_soc_ok(char *var_parameter, char *response)
+{
+ if (busy_flag == 1)
+ fastboot_busy("battery-soc-ok: yes", response);
+ else
+ fastboot_okay("yes", response);
+}
+
+static void getvar_battery_voltage(char *var_parameter, char *response)
+{
+ if (busy_flag == 1)
+ fastboot_busy("battery-voltage: 4", response);
+ else
+ fastboot_okay("4", response);
+}
+
+static void getvar_block_size(char *var_parameter, char *response)
+{
+ if (busy_flag == 1)
+ fastboot_busy("block-size: 2000", response);
+ else
+ fastboot_okay("2000", response);
+}
+
+static void getvar_secure(char *var_parameter, char *response)
+{
+ if (check_lock()) {
+ if (busy_flag == 1)
+ fastboot_busy("secure: yes", response);
+ else
+ fastboot_okay("yes", response);
+ } else {
+ if (busy_flag == 1)
+ fastboot_busy("secure: no", response);
+ else
+ fastboot_okay("no", response);
+ }
+}
+
+static void getvar_unlocked(char *var_parameter, char *response)
+{
+ if (check_lock()) {
+ if (busy_flag == 1)
+ fastboot_busy("unlocked: no", response);
+ else
+ fastboot_okay("no", response);
+ } else {
+ if (busy_flag == 1)
+ fastboot_busy("unlocked: yes", response);
+ else
+ fastboot_okay("yes", response);
+ }
+}
+
+static void getvar_is_userspace(char *var_parameter, char *response)
+{
+ if (dynamic_partition) {
+ if (busy_flag == 1)
+ fastboot_busy("is-userspace: no", response);
+ else
+ fastboot_okay("no", response);
+ } else {
+ if (busy_flag == 1)
+ fastboot_busy("is-userspace: do not use dynamic", response);
+ else
+ fastboot_fail("do not use dynamic", response);
+ }
+}
+
+static void getvar_super_partition_name(char *var_parameter, char *response)
+{
+ char *slot_name;
+ slot_name = env_get("slot-suffixes");
+ char name[64];
+ if (has_boot_slot == 0) {
+ strncpy(name, "super-partition-name: super", 64);
+ } else {
+ printf("slot-suffixes: %s\n", slot_name);
+ if (strcmp(slot_name, "0") == 0) {
+ strncpy(name, "super-partition-name: super_a", 64);
+ } else if (strcmp(slot_name, "1") == 0) {
+ strncpy(name, "super-partition-name: super_b", 64);
+ }
+ }
+ if (busy_flag == 1)
+ fastboot_busy(name, response);
+ else
+ fastboot_okay(name, response);
+}
+
+static void getvar_is_logical(char *var_parameter, char *response)
+{
+ char name[64] = {0};
+ strncpy(name, var_parameter, strnlen(var_parameter, 64));
+ name[63] = 0;
+ if (has_boot_slot == 1) {
+ char *slot_name;
+ slot_name = env_get("slot-suffixes");
+ if ((strcmp(var_parameter, "system") == 0) || (strcmp(var_parameter, "vendor") == 0)
+ || (strcmp(var_parameter, "odm") == 0) || (strcmp(var_parameter, "product") == 0)
+ || (strcmp(var_parameter, "system_ext") == 0) || (strcmp(var_parameter, "dtbo") == 0)
+ || (strcmp(var_parameter, "boot") == 0) || (strcmp(var_parameter, "recovery") == 0)
+ || (strcmp(var_parameter, "oem") == 0) || (strcmp(var_parameter, "vbmeta_system") == 0)
+ || (strcmp(var_parameter, "vendor_boot") == 0) || (strcmp(var_parameter, "vbmeta") == 0)) {
+ if (strcmp(slot_name, "0") == 0) {
+ strcat(name, "_a");
+ } else if (strcmp(slot_name, "1") == 0) {
+ strcat(name, "_b");
+ }
+ }
+ }
+ printf("partition name is %s\n", name);
+
+ if (!dynamic_partition) {
+ if (busy_flag == 1)
+ fastboot_response("INFOis_logical:", response, "%s: no", var_parameter);
+ else
+ fastboot_okay("no", response);
+ } else {
+ if (busy_flag == 1) {
+#ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK
+ if (is_partition_logical(name) == 0) {
+ printf("%s is logic partition\n", name);
+ fastboot_response("INFOis_logical:", response, "%s: yes", name);
+ } else {
+ fastboot_response("INFOis_logical:", response, "%s: no", name);
+ }
+#else
+ fastboot_response("INFOis_logical:", response, "%s: no", name);
+#endif
+ } else {
+#ifdef CONFIG_BOOTLOADER_CONTROL_BLOCK
+ if (is_partition_logical(name) == 0) {
+ printf("%s is logic partition\n", name);
+ fastboot_okay("yes", response);
+ } else {
+ fastboot_okay("no", response);
+ }
+#else
+ fastboot_okay("no", response);
+#endif
+ }
+ }
+}
+
+static void getvar_slot_count(char *var_parameter, char *response)
+{
+ if (has_boot_slot == 1) {
+ if (busy_flag == 1)
+ fastboot_busy("slot-count: 2", response);
+ else
+ fastboot_okay("2", response);
+ }
+ else {
+ if (busy_flag == 1)
+ fastboot_busy("slot-count: 0", response);
+ else
+ fastboot_okay("0", response);
+ }
}
static void getvar_downloadsize(char *var_parameter, char *response)
{
- fastboot_response("OKAY", response, "0x%08x", fastboot_buf_size);
+ if (busy_flag == 1)
+ fastboot_response("INFOdownloadsize: ", response, "0x%08x", fastboot_buf_size);
+ else
+ fastboot_response("OKAY", response, "0x%08x", fastboot_buf_size);
}
static void getvar_serialno(char *var_parameter, char *response)
{
const char *tmp = env_get("serial#");
- if (tmp)
- fastboot_okay(tmp, response);
- else
- fastboot_fail("Value not set", response);
+ if (busy_flag == 1) {
+ if (tmp)
+ fastboot_response("INFOserialno: ", response, "%s", tmp);
+ else
+ fastboot_busy("serialno: Value not set", response);
+ } else {
+ if (tmp)
+ fastboot_okay(tmp, response);
+ else
+ fastboot_fail("Value not set", response);
+ }
}
static void getvar_version_baseband(char *var_parameter, char *response)
{
- fastboot_okay("N/A", response);
+ if (busy_flag == 1)
+ fastboot_busy("version-baseband: N/A", response);
+ else
+ fastboot_okay("N/A", response);
}
static void getvar_product(char *var_parameter, char *response)
{
const char *board = env_get("board");
- if (board)
- fastboot_okay(board, response);
- else
- fastboot_fail("Board not set", response);
+ if (busy_flag == 1) {
+ if (board)
+ fastboot_response("INFOproduct: ", response, "%s", board);
+ else
+ fastboot_busy("product: Board not set", response);
+ } else {
+ if (board)
+ fastboot_okay(board, response);
+ else
+ fastboot_fail("Board not set", response);
+ }
}
static void getvar_current_slot(char *var_parameter, char *response)
{
+ char *slot;
+ slot = env_get("slot-suffixes");
+ printf("slot-suffixes: %s\n", slot);
/* A/B not implemented, for now always return _a */
- fastboot_okay("_a", response);
+ if (busy_flag == 1) {
+ if (strcmp(slot, "0") == 0)
+ fastboot_busy("current-slot: a", response);
+ else if (strcmp(slot, "1") == 0)
+ fastboot_busy("current-slot: b", response);
+ }
+ else {
+ if (strcmp(slot, "0") == 0)
+ fastboot_okay("a", response);
+ else if (strcmp(slot, "1") == 0)
+ fastboot_okay("b", response);
+ }
+}
+
+static void getvar_snapshot_update_status(char *var_parameter, char *response)
+{
+ struct misc_virtual_ab_message message;
+ get_mergestatus(&message);
+ if (busy_flag == 1) {
+ if (has_boot_slot == 1) {
+ switch (message.merge_status) {
+ case SNAPSHOTTED:
+ fastboot_busy("snapshotted", response);
+ break;
+ case MERGING:
+ fastboot_busy("merging", response);
+ break;
+ default:
+ fastboot_busy("none", response);
+ break;
+ }
+ } else
+ fastboot_busy("none", response);
+ }
+ else {
+ if (has_boot_slot == 1) {
+ switch (message.merge_status) {
+ case SNAPSHOTTED:
+ fastboot_okay("snapshotted", response);
+ break;
+ case MERGING:
+ fastboot_okay("merging", response);
+ break;
+ default:
+ fastboot_okay("none", response);
+ break;
+ }
+ } else
+ fastboot_fail("not ab mode", response);
+ }
}
static void getvar_slot_suffixes(char *var_parameter, char *response)
{
- fastboot_okay("_a,_b", response);
+ char *s;
+ s = env_get("slot-suffixes");
+ printf("slot-suffixes: %s\n", s);
+ if (busy_flag == 1) {
+ if (!strcmp(s, "-1") == 0)
+ fastboot_response("INFOslot-suffixes:", response, "%s", s);
+ else
+ fastboot_busy("slot-suffixes: 0", response);
+ }
+ else {
+ if (!strcmp(s, "-1") == 0)
+ fastboot_okay(s, response);
+ else
+ fastboot_okay("0", response);
+ }
}
static void getvar_has_slot(char *part_name, char *response)
{
- if (part_name && (!strcmp(part_name, "boot") ||
- !strcmp(part_name, "system")))
- fastboot_okay("yes", response);
- else
- fastboot_okay("no", response);
+ if (has_boot_slot == 0) {
+ if (busy_flag == 1)
+ fastboot_response("INFOhas-slot:", response, "%s: no", part_name);
+ else
+ fastboot_okay("no", response);
+ } else {
+ if ((strcmp(part_name, "system") == 0) || (strcmp(part_name, "vendor") == 0)
+ || (strcmp(part_name, "odm") == 0) || (strcmp(part_name, "product") == 0)
+ || (strcmp(part_name, "system_ext") == 0) || (strcmp(part_name, "dtbo") == 0)
+ || (strcmp(part_name, "boot") == 0) || (strcmp(part_name, "recovery") == 0)
+ || (strcmp(part_name, "vendor_boot") == 0) || (strcmp(part_name, "vbmeta") == 0)
+ || (strcmp(part_name, "vbmeta_system") == 0)
+#if CONFIG_IS_ENABLED(CHROMECAST_AB)
+ || (strcmp(part_name, "bootloader") == 0)
+#endif
+ || (strcmp(part_name, "odm_ext") == 0) || (strcmp(part_name, "oem") == 0)){
+ if (busy_flag == 1)
+ fastboot_response("INFOhas-slot:", response, "%s: yes", part_name);
+ else
+ fastboot_okay("yes", response);
+ } else {
+ if (busy_flag == 1)
+ fastboot_response("INFOhas-slot:", response, "%s: no", part_name);
+ else
+ fastboot_okay("no", response);
+ }
+ }
}
-#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
+#if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
static void getvar_partition_type(char *part_name, char *response)
{
int r;
- struct blk_desc *dev_desc;
- disk_partition_t part_info;
+ char name[32] = {0};
+ u64 rc = 0;
- r = fastboot_mmc_get_part_info(part_name, &dev_desc, &part_info,
- response);
- if (r >= 0) {
- r = fs_set_blk_dev_with_part(dev_desc, r);
- if (r < 0)
- fastboot_fail("failed to set partition", response);
+ if (strcmp(part_name, "userdata") == 0 || strcmp(part_name, "data") == 0) {
+ rc = store_part_size("userdata");
+ if (-1 == rc)
+ strlcpy(name, "data", sizeof(name));
else
- fastboot_okay(fs_get_type_name(), response);
+ strlcpy(name, "userdata", sizeof(name));
+ } else {
+ strlcpy(name, part_name, sizeof(name));
}
-}
-#endif
-
-#if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
-static void getvar_partition_size(char *part_name, char *response)
-{
- int r;
- size_t size;
-
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
struct blk_desc *dev_desc;
disk_partition_t part_info;
- r = fastboot_mmc_get_part_info(part_name, &dev_desc, &part_info,
+ r = fastboot_mmc_get_part_info(name, &dev_desc, &part_info,
response);
- if (r >= 0)
- size = part_info.size;
#endif
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_NAND)
struct part_info *part_info;
- r = fastboot_nand_get_part_info(part_name, &part_info, response);
- if (r >= 0)
- size = part_info->size;
+ r = fastboot_nand_get_part_info(name, &part_info, response);
#endif
+ if (r >= 0) {
+ if (busy_flag == 1)
+ fastboot_response("INFOpartition-type:", response, "%s: raw", part_name);
+ else
+ fastboot_okay("raw", response);
+ }
+}
+
+static void getvar_partition_size(char *part_name, char *response)
+{
+ int r;
+ size_t size;
+ char name[32] = {0};
+ u64 rc = 0;
+
+ if (strcmp(part_name, "userdata") == 0 || strcmp(part_name, "data") == 0) {
+ rc = store_part_size("userdata");
+ if (-1 == rc)
+ strncpy(name, "data", 4);
+ else
+ strncpy(name, "userdata", 8);
+ } else {
+ strncpy(name, part_name, 32);
+ }
+
+#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_MMC)
+ struct blk_desc *dev_desc;
+ disk_partition_t part_info;
+
+ r = fastboot_mmc_get_part_info(name, &dev_desc, &part_info,
+ response);
if (r >= 0)
- fastboot_response("OKAY", response, "0x%016zx", size);
+ size = part_info.size * 512;
+#endif
+#if CONFIG_IS_ENABLED(FASTBOOT_FLASH_NAND)
+ struct part_info *part_info;
+
+ r = fastboot_nand_get_part_info(name, &part_info, response);
+ if (r >= 0)
+ size = part_info->size * 512;
+#endif
+ if (r >= 0) {
+ if (busy_flag == 1) {
+ char all_name[64];
+ strncpy(all_name, "INFOpartition-size:", 64);
+ strcat(all_name, name);
+ strcat(all_name, ": ");
+ fastboot_response(all_name, response, "0x%016zx", size);
+ }
+ else
+ fastboot_response("OKAY", response, "0x%016zx", size);
+ }
}
#endif
@@ -215,6 +616,8 @@
return;
}
+ printf("fastboot_getvar cmd_parameter: %s\n", cmd_parameter);
+
strsep(&var_parameter, ":");
for (i = 0; i < ARRAY_SIZE(getvar_dispatch); ++i) {
if (!strcmp(getvar_dispatch[i].variable,
diff --git a/drivers/fastboot/fb_mmc.c b/drivers/fastboot/fb_mmc.c
index 4c1c7fd..a309b9f 100644
--- a/drivers/fastboot/fb_mmc.c
+++ b/drivers/fastboot/fb_mmc.c
@@ -15,6 +15,8 @@
#include <div64.h>
#include <linux/compat.h>
#include <android_image.h>
+#include <amlogic/aml_mmc.h>
+#include <emmc_partitions.h>
#define FASTBOOT_MAX_BLK_WRITE 16384
@@ -36,7 +38,7 @@
char *aliased_part_name;
/* check for alias */
- strcpy(env_alias_name, "fastboot_partition_alias_");
+ strncpy(env_alias_name, "fastboot_partition_alias_", 26);
strncat(env_alias_name, name, 32);
aliased_part_name = env_get(env_alias_name);
if (aliased_part_name != NULL)
@@ -63,21 +65,22 @@
lbaint_t blks = 0;
int i;
- for (i = 0; i < blkcnt; i += FASTBOOT_MAX_BLK_WRITE) {
- cur_blkcnt = min((int)blkcnt - i, FASTBOOT_MAX_BLK_WRITE);
- if (buffer) {
+ if (buffer) {
+ for (i = 0; i < blkcnt; i += FASTBOOT_MAX_BLK_WRITE) {
+ cur_blkcnt = min((int)blkcnt - i, FASTBOOT_MAX_BLK_WRITE);
if (fastboot_progress_callback)
fastboot_progress_callback("writing");
blks_written = blk_dwrite(block_dev, blk, cur_blkcnt,
buffer + (i * block_dev->blksz));
- } else {
- if (fastboot_progress_callback)
- fastboot_progress_callback("erasing");
- blks_written = blk_derase(block_dev, blk, cur_blkcnt);
+ blk += blks_written;
+ blks += blks_written;
}
- blk += blks_written;
- blks += blks_written;
+ } else {
+ if (fastboot_progress_callback)
+ fastboot_progress_callback("erasing");
+ blks = blk_derase(block_dev, start, blkcnt);
}
+
return blks;
}
@@ -140,7 +143,7 @@
*/
static lbaint_t fb_mmc_get_boot_header(struct blk_desc *dev_desc,
disk_partition_t *info,
- struct andr_img_hdr *hdr,
+ boot_img_hdr_t *hdr,
char *response)
{
ulong sector_size; /* boot partition sector size */
@@ -149,7 +152,7 @@
/* Calculate boot image sectors count */
sector_size = info->blksz;
- hdr_sectors = DIV_ROUND_UP(sizeof(struct andr_img_hdr), sector_size);
+ hdr_sectors = DIV_ROUND_UP(sizeof(boot_img_hdr_t), sector_size);
if (hdr_sectors == 0) {
pr_err("invalid number of boot sectors: 0\n");
fastboot_fail("invalid number of boot sectors: 0", response);
@@ -191,7 +194,7 @@
char *response)
{
uintptr_t hdr_addr; /* boot image header address */
- struct andr_img_hdr *hdr; /* boot image header */
+ boot_img_hdr_t *hdr; /* boot image header */
lbaint_t hdr_sectors; /* boot image header sectors */
u8 *ramdisk_buffer;
u32 ramdisk_sector_start;
@@ -214,7 +217,7 @@
/* Put boot image header in fastboot buffer after downloaded zImage */
hdr_addr = (uintptr_t)download_buffer + ALIGN(download_bytes, PAGE_SIZE);
- hdr = (struct andr_img_hdr *)hdr_addr;
+ hdr = (boot_img_hdr_t *)hdr_addr;
/* Read boot image header */
hdr_sectors = fb_mmc_get_boot_header(dev_desc, &info, hdr, response);
@@ -322,6 +325,68 @@
return r;
}
+/* erase or flash, when buffer is not NULL, it's write */
+static void fb_mmc_bootloader_ops(const char *cmd,
+ struct blk_desc *dev_desc,
+ void *buffer, unsigned int bytes,
+ char *response)
+{
+ char *delim = "-";
+ char *hwpart;
+ int map = 0, ret = 0;
+ char *scmd = (char *) cmd;
+ char *ops[] = {"erase", "write"};
+
+ hwpart = strchr(scmd, (int)*delim);
+
+ if (!hwpart) {
+ map = AML_BL_USER;
+ } else if (!strcmp(hwpart, "-boot0")) {
+ map = AML_BL_BOOT0;
+ } else if (!strcmp(hwpart, "-boot1")) {
+ map = AML_BL_BOOT1;
+ }
+ if (map) {
+ if (buffer)
+ ret = amlmmc_write_bootloader(CONFIG_FASTBOOT_FLASH_MMC_DEV, map,
+ bytes, buffer);
+ else
+ ret = amlmmc_erase_bootloader(CONFIG_FASTBOOT_FLASH_MMC_DEV, map);
+ if (ret) {
+ printf("failed %s %s from device %d", (buffer? ops[1]: ops[0]),
+ cmd, dev_desc->devnum);
+ fastboot_fail("failed bootloader operating to device", response);
+ return;
+ }
+ printf("........ %s %s\n", (buffer? ops[1]: ops[0]), cmd);
+ fastboot_okay("", response);
+ } else
+ fastboot_fail("failed opearting from device", response);
+ return;
+}
+
+/**
+ * write bootloader on user/boot0/boot1
+ * according to bootloader name.
+ */
+static void fb_mmc_write_bootloader(const char *cmd,
+ struct blk_desc *dev_desc,
+ void *buffer, unsigned int bytes,
+ char *response)
+{
+ return fb_mmc_bootloader_ops(cmd, dev_desc, buffer, bytes, response);
+}
+
+/**
+ * erase bootloader on user/boot0/boot1
+ * according to bootloader name.
+ */
+static void fb_mmc_erase_bootloader(const char *cmd, struct blk_desc *dev_desc,
+ char *response)
+{
+ return fb_mmc_bootloader_ops(cmd, dev_desc, NULL, 0, response);
+}
+
/**
* fastboot_mmc_flash_write() - Write image to eMMC for fastboot
*
@@ -334,7 +399,15 @@
u32 download_bytes, char *response)
{
struct blk_desc *dev_desc;
+ int ret = 0;
disk_partition_t info;
+ struct mmc *mmc = find_mmc_device(CONFIG_FASTBOOT_FLASH_MMC_DEV);
+
+ if (mmc == NULL) {
+ pr_err("invalid mmc device\n");
+ fastboot_fail("invalid mmc device", response);
+ return;
+ }
dev_desc = blk_get_dev("mmc", CONFIG_FASTBOOT_FLASH_MMC_DEV);
if (!dev_desc || dev_desc->type == DEV_TYPE_UNKNOWN) {
@@ -380,6 +453,11 @@
response);
return;
}
+ if (mmc_device_init(mmc) != 0) {
+ printf(" update gpt partition table fail\n");
+ fastboot_fail("fastboot update gpt partition fail", response);
+ return;
+ }
printf("........ success\n");
fastboot_okay(NULL, response);
return;
@@ -394,37 +472,66 @@
}
#endif
- if (part_get_info_by_name_or_alias(dev_desc, cmd, &info) < 0) {
- pr_err("cannot find partition: '%s'\n", cmd);
- fastboot_fail("cannot find partition", response);
+ if (strcmp(cmd, "dtb") == 0) {
+#ifndef DTB_BIND_KERNEL
+ if (aml_gpt_valid(mmc) == 0)
+ erase_gpt_part_table(dev_desc);
+ ret = dtb_write(download_buffer);
+ if (ret)
+ fastboot_fail("fastboot write dtb fail", response);
+ else {
+ if (!gpt_partition) {
+ /* renew partition table @ once*/
+ printf("renew partition table\n");
+ if (renew_partition_tbl(download_buffer))
+ fastboot_fail("fastboot write dtb fail", response);
+ }
+ fastboot_okay("", response);
+ }
+#else
+ fastboot_fail("dtb is bind in kernel, return", response);
+#endif
+#if CONFIG_IS_ENABLED(CHROMECAST_AB)
+ } else if (!strncmp(cmd, "bootloader-boot", strlen("bootloader-boot"))) {
+#else
+ } else if (!strncmp(cmd, "bootloader", strlen("bootloader"))) {
+#endif
+ fb_mmc_write_bootloader(cmd, dev_desc, download_buffer,
+ download_bytes, response);
return;
- }
-
- if (is_sparse_image(download_buffer)) {
- struct fb_mmc_sparse sparse_priv;
- struct sparse_storage sparse;
- int err;
-
- sparse_priv.dev_desc = dev_desc;
-
- sparse.blksz = info.blksz;
- sparse.start = info.start;
- sparse.size = info.size;
- sparse.write = fb_mmc_sparse_write;
- sparse.reserve = fb_mmc_sparse_reserve;
- sparse.mssg = fastboot_fail;
-
- printf("Flashing sparse image at offset " LBAFU "\n",
- sparse.start);
-
- sparse.priv = &sparse_priv;
- err = write_sparse_image(&sparse, cmd, download_buffer,
- response);
- if (!err)
- fastboot_okay(NULL, response);
} else {
- write_raw_image(dev_desc, &info, cmd, download_buffer,
- download_bytes, response);
+ if (part_get_info_by_name_or_alias(dev_desc, cmd, &info) < 0) {
+ pr_err("cannot find partition: '%s'\n", cmd);
+ fastboot_fail("cannot find partition", response);
+ return;
+ }
+
+ if (is_sparse_image(download_buffer)) {
+ struct fb_mmc_sparse sparse_priv;
+ struct sparse_storage sparse;
+ int err;
+
+ sparse_priv.dev_desc = dev_desc;
+
+ sparse.blksz = info.blksz;
+ sparse.start = info.start;
+ sparse.size = info.size;
+ sparse.write = fb_mmc_sparse_write;
+ sparse.reserve = fb_mmc_sparse_reserve;
+ sparse.mssg = fastboot_fail;
+
+ printf("Flashing sparse image at offset " LBAFU "\n",
+ sparse.start);
+
+ sparse.priv = &sparse_priv;
+ err = write_sparse_image(&sparse, cmd, download_buffer,
+ response);
+ if (!err)
+ fastboot_okay(NULL, response);
+ } else {
+ write_raw_image(dev_desc, &info, cmd, download_buffer,
+ download_bytes, response);
+ }
}
}
@@ -455,34 +562,64 @@
return;
}
- ret = part_get_info_by_name_or_alias(dev_desc, cmd, &info);
- if (ret < 0) {
- pr_err("cannot find partition: '%s'\n", cmd);
- fastboot_fail("cannot find partition", response);
+#if CONFIG_IS_ENABLED(EFI_PARTITION)
+ if (strcmp(cmd, CONFIG_FASTBOOT_GPT_NAME) == 0) {
+ printf("%s: erase gpt, cmd:%s\n", __func__, cmd);
+ ret = erase_gpt_part_table(dev_desc);
+ if (ret) {
+ fastboot_fail("failed erase gpt", response);
+ return;
+ }
+ fastboot_okay("", response);
return;
}
+#endif
- /* Align blocks to erase group size to avoid erasing other partitions */
- grp_size = mmc->erase_grp_size;
- blks_start = (info.start + grp_size - 1) & ~(grp_size - 1);
- if (info.size >= grp_size)
- blks_size = (info.size - (blks_start - info.start)) &
- (~(grp_size - 1));
- else
- blks_size = 0;
-
- printf("Erasing blocks " LBAFU " to " LBAFU " due to alignment\n",
- blks_start, blks_start + blks_size);
-
- blks = fb_mmc_blk_write(dev_desc, blks_start, blks_size, NULL);
-
- if (blks != blks_size) {
- pr_err("failed erasing from device %d\n", dev_desc->devnum);
- fastboot_fail("failed erasing from device", response);
+ if (strcmp(cmd, "dtb") == 0) {
+#ifndef DTB_BIND_KERNEL
+ extern int emmc_erase_rsv(struct mmc *mmc, char *rsv_part);
+ ret = emmc_erase_rsv(mmc, (char *)cmd);
+ if (ret) {
+ fastboot_fail("fastboot erase dtb fail", response);
+ return;
+ }
+ fastboot_okay(NULL, response);
+#else
+ fastboot_fail("dtb is bind in kernel, return", response);
+#endif
+ } else if (!strncmp(cmd, "bootloader", strlen("bootloader"))) {
+ fb_mmc_erase_bootloader(cmd, dev_desc, response);
return;
- }
+ } else {
+ ret = part_get_info_by_name_or_alias(dev_desc, cmd, &info);
+ if (ret < 0) {
+ pr_err("cannot find partition: '%s'\n", cmd);
+ fastboot_fail("cannot find partition", response);
+ return;
+ }
- printf("........ erased " LBAFU " bytes from '%s'\n",
- blks_size * info.blksz, cmd);
- fastboot_okay(NULL, response);
+ /* Align blocks to erase group size to avoid erasing other partitions */
+ grp_size = mmc->erase_grp_size;
+ blks_start = (info.start + grp_size - 1) & ~(grp_size - 1);
+ if (info.size >= grp_size)
+ blks_size = (info.size - (blks_start - info.start)) &
+ (~(grp_size - 1));
+ else
+ blks_size = 0;
+
+ printf("Erasing blocks " LBAFU " to " LBAFU " due to alignment\n",
+ blks_start, blks_start + blks_size);
+
+ blks = fb_mmc_blk_write(dev_desc, blks_start, blks_size, NULL);
+
+ if (blks) {
+ pr_err("failed erasing from device %d\n", dev_desc->devnum);
+ fastboot_fail("failed erasing from device", response);
+ return;
+ }
+
+ printf("........ erased " LBAFU " bytes from '%s'\n",
+ blks_size * info.blksz, cmd);
+ fastboot_okay(NULL, response);
+ }
}
diff --git a/drivers/fastboot/fb_nand.c b/drivers/fastboot/fb_nand.c
index 526bc12..15d5de3 100644
--- a/drivers/fastboot/fb_nand.c
+++ b/drivers/fastboot/fb_nand.c
@@ -13,6 +13,12 @@
#include <linux/mtd/mtd.h>
#include <jffs2/jffs2.h>
#include <nand.h>
+#include <amlogic/storage.h>
+#include <amlogic/aml_mtd.h>
+#include <amlogic/aml_nand.h>
+#include <amlogic/aml_rsv.h>
+#include <amlogic/storage.h>
+#include <amlogic/cpu_id.h>
struct fb_nand_sparse {
struct mtd_info *mtd;
@@ -45,6 +51,8 @@
return ret;
}
+ if (strcmp(partname, "dtb") == 0)
+ return 0;
ret = find_dev_and_part(partname, &dev, &pnum, part);
if (ret) {
pr_err("cannot find partition: '%s'", partname);
@@ -160,6 +168,60 @@
return fb_nand_lookup(part_name, &mtd, part_info, response);
}
+int get_bootnum(struct mtd_info *mtd, size_t rwsize)
+{
+ size_t bad_blk_len_low = 0, bad_blk_len_up = 0, skip;
+ size_t aviable_space;
+ size_t block_len, block_off;
+ loff_t block_start;
+ loff_t offset = 0;
+ int ret = 1; /*inital for only one copy*/
+
+ if (!rwsize) { /*not need to policy call, only one */
+ ret = 1;
+ return ret;
+ }
+
+ /* algin with page size */
+ rwsize = ((rwsize + mtd->writesize - 1)/mtd->writesize)*mtd->writesize;
+
+ while (offset < mtd->size) {
+ block_start = offset & ~(loff_t)(mtd->erasesize - 1);
+ block_off = offset & (mtd->erasesize - 1);
+ block_len = mtd->erasesize - block_off;
+
+ if (nand_block_isbad(mtd, block_start)) {
+ if ( offset < mtd->size / 2) /*no understand*/
+ bad_blk_len_low += block_len;
+ else if (offset > mtd->size / 2)
+ bad_blk_len_up += block_len;
+ else {
+ bad_blk_len_up = offset;
+ }
+ }
+ offset += block_len;
+ }
+
+ printk("rwsize:0x%zx skip_low:0x%zx skip_up:0x%zx\n",
+ rwsize, bad_blk_len_low, bad_blk_len_up);
+
+ skip = bad_blk_len_low + bad_blk_len_up;
+ aviable_space = mtd->size - skip - 2 * mtd->writesize; /*no understand*/
+
+ if (rwsize*2 <= aviable_space) {
+ ret = 1;
+ if (rwsize + mtd->writesize + bad_blk_len_low > mtd->size / 2)
+ return 1; /*1st must be write*/
+ if (rwsize + mtd->writesize + bad_blk_len_up <= mtd->size / 2)
+ ret ++;
+ } else /*needn't consider bad block length, unlikly so many bad blocks*/
+ ret = 1;
+
+ printk("self-adaption boot count:%d\n", ret);
+
+ return ret;
+}
+
/**
* fastboot_nand_flash_write() - Write image to NAND for fastboot
*
@@ -173,7 +235,12 @@
{
struct part_info *part;
struct mtd_info *mtd = NULL;
- int ret;
+ int ret, err;
+ int copy_num = 0, i = 0;
+ u64 off = 0;
+ size_t rwsize = 0, limit = 0;
+
+ enum boot_type_e medium_type = store_get_type();
ret = fb_nand_lookup(cmd, &mtd, &part, response);
if (ret) {
@@ -182,6 +249,72 @@
return;
}
+ if (strcmp(cmd, "bootloader") == 0) {
+ rwsize = download_bytes;
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER) {
+ copy_num = CONFIG_BL2_COPY_NUM;
+ limit = mtd->size / copy_num;
+ } else {
+ copy_num = get_bootnum(mtd, rwsize);
+ limit = mtd->size / copy_num;
+ }
+
+ for (i = 0; i < copy_num; i++) {
+ printf("off = 0x%llx,wsize = 0x%lx\n",
+ off, rwsize);
+ err = nand_write_skip_bad(mtd, off, &rwsize,
+ NULL, limit,
+ (u_char *)download_buffer, 0);
+ if (err) {
+ rwsize = download_bytes;
+ printf("bootloader write err,code = %d\n",err);
+ }
+ off += limit;
+ }
+ fastboot_okay("write bootloader", response);
+ return;
+ }
+
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER) {
+ if (strcmp(cmd, "tpl") == 0) {
+ if (BOOT_SNAND == medium_type ||
+ BOOT_NAND_MTD == medium_type)
+ copy_num = CONFIG_NAND_TPL_COPY_NUM;
+ else if (medium_type == BOOT_SNOR)
+ copy_num = CONFIG_NOR_TPL_COPY_NUM;
+ rwsize = download_bytes;
+ limit = CONFIG_TPL_SIZE_PER_COPY;
+ off = 1024 * mtd->writesize +
+ NAND_RSV_BLOCK_NUM * mtd->erasesize;
+
+ for (i = 0; i < copy_num; i++) {
+ printf("off = 0x%llx,wsize = 0x%lx\n", off, rwsize);
+ err = nand_write_skip_bad(mtd, off, &rwsize,
+ NULL, limit,
+ (u_char *)download_buffer, 0);
+ if (err) {
+ rwsize = download_bytes;
+ printf("tpl write err,code = %d\n",err);
+ }
+ off += CONFIG_TPL_SIZE_PER_COPY;
+ }
+ fastboot_okay("write tpl", response);
+ return;
+ }
+ }
+
+ if (strcmp(cmd, "dtb") == 0) {
+ ret = store_rsv_write("dtb", download_bytes, (u8 *)download_buffer);
+ printf("Flashing dtb...len:0x%x\n", download_bytes);
+ if (ret) {
+ printf("write dtb fail,result code %d\n", ret);
+ fastboot_fail("write dtb", response);
+ } else {
+ fastboot_okay("write dtb", response);
+ }
+ return;
+ }
+
ret = board_fastboot_write_partition_setup(part->name);
if (ret)
return;
@@ -246,6 +379,18 @@
return;
}
+ if (strcmp(cmd, "dtb") == 0) {
+ ret = store_rsv_erase("dtb");
+ if (ret) {
+ pr_err("erase dtb fail,ret = %d\n", ret);
+ fastboot_fail("erase dtb",
+ response);
+ } else {
+ fastboot_okay("erase dtb", response);
+ }
+ return;
+ }
+
ret = board_fastboot_erase_partition_setup(part->name);
if (ret)
return;
diff --git a/drivers/firmware/Kconfig b/drivers/firmware/Kconfig
index c9aac1a..7d8f161 100644
--- a/drivers/firmware/Kconfig
+++ b/drivers/firmware/Kconfig
@@ -21,4 +21,3 @@
This protocol library is used by client drivers to use the features
provided by the system controller.
-
diff --git a/drivers/fpga/Kconfig b/drivers/fpga/Kconfig
index 848165d..8f59193 100644
--- a/drivers/fpga/Kconfig
+++ b/drivers/fpga/Kconfig
@@ -69,4 +69,3 @@
on Xilinx Zynq devices.
endmenu
-
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index c625e53..c8c6c60 100644
--- a/drivers/gpio/Kconfig
+++ b/drivers/gpio/Kconfig
@@ -330,4 +330,3 @@
Say yes here to support MediaTek MT7621 compatible GPIOs.
endmenu
-
diff --git a/drivers/hwspinlock/Kconfig b/drivers/hwspinlock/Kconfig
index ad53156..96d4f5d 100644
--- a/drivers/hwspinlock/Kconfig
+++ b/drivers/hwspinlock/Kconfig
@@ -22,4 +22,3 @@
various processors on the SoC.
endmenu
-
diff --git a/drivers/i2c/Kconfig b/drivers/i2c/Kconfig
index af119be..1ef22e6 100644
--- a/drivers/i2c/Kconfig
+++ b/drivers/i2c/Kconfig
@@ -491,4 +491,3 @@
source "drivers/i2c/muxes/Kconfig"
endmenu
-
diff --git a/drivers/i2c/i2c-gpio.c b/drivers/i2c/i2c-gpio.c
index 4e8fa21..d77aa77 100644
--- a/drivers/i2c/i2c-gpio.c
+++ b/drivers/i2c/i2c-gpio.c
@@ -24,6 +24,8 @@
PIN_COUNT,
};
+static unsigned int is_odpin;
+
struct i2c_gpio_bus {
/**
* udelay - delay [us] between GPIO toggle operations,
@@ -51,6 +53,15 @@
{
ulong flags = GPIOD_IS_OUT;
+ if (is_odpin) {
+ if (bit)
+ dm_gpio_set_dir_flags(scl, GPIOD_IS_IN);
+ else
+ dm_gpio_set_dir_flags(scl, flags | GPIOD_IS_OUT_ACTIVE);
+
+ return;
+ }
+
if (bit)
flags |= GPIOD_IS_OUT_ACTIVE;
dm_gpio_set_dir_flags(scl, flags);
@@ -320,6 +331,8 @@
bus->udelay = fdtdec_get_int(blob, node, "i2c-gpio,delay-us",
DEFAULT_UDELAY);
+ is_odpin = fdtdec_get_int(blob, node, "is_odpin", 0);
+
return 0;
error:
pr_err("Can't get %s gpios! Error: %d", dev->name, ret);
diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
old mode 100755
new mode 100644
index c5a3c4e..975318e
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
@@ -347,6 +347,17 @@
debug("Cannot find I2C bus %d\n", busnum);
return ret;
}
+
+ /* detect the presence of the chip on the bus */
+ ret = i2c_probe_chip(bus, chip_addr, 0);
+ debug("%s: bus='%s', address %02x, ret=%d\n", __func__, bus->name,
+ chip_addr, ret);
+ if (ret) {
+ debug("Cannot detect I2C chip %02x on bus %d\n", chip_addr,
+ busnum);
+ return ret;
+ }
+
ret = i2c_get_chip(bus, chip_addr, offset_len, devp);
if (ret) {
debug("Cannot find I2C chip %02x on bus %d\n", chip_addr,
diff --git a/drivers/i2c/meson_i2c.c b/drivers/i2c/meson_i2c.c
old mode 100755
new mode 100644
index a84ca50..754a8ae
--- a/drivers/i2c/meson_i2c.c
+++ b/drivers/i2c/meson_i2c.c
@@ -45,6 +45,7 @@
struct meson_i2c_data {
u8 delay_ajust;
u8 div_factor;
+ u32 clkin_rate;
};
struct meson_i2c {
@@ -217,8 +218,6 @@
struct meson_i2c *i2c = dev_get_priv(bus);
int i, ret = 0;
- //i2c bus need 300us to ready
- udelay(300);
for (i = 0; i < nmsgs; i++) {
ret = meson_i2c_xfer_msg(i2c, msg + i, i == nmsgs - 1);
if (ret)
@@ -231,7 +230,7 @@
static int meson_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
{
struct meson_i2c *i2c = dev_get_priv(bus);
- unsigned int clk_rate = MESON_I2C_CLK_RATE;
+ unsigned int clk_rate = i2c->data->clkin_rate;
unsigned int div;
div = DIV_ROUND_UP(clk_rate, speed * i2c->data->div_factor);
@@ -248,7 +247,7 @@
clrsetbits_le32(&i2c->regs->ctrl, REG_CTRL_CLKDIVEXT_MASK,
(div >> 10) << REG_CTRL_CLKDIVEXT_SHIFT);
- debug("meson i2c: set clk %u, src %lu, div %u\n", speed, clk_rate, div);
+ debug("meson i2c: set clk %u, src %u, div %u\n", speed, clk_rate, div);
return 0;
}
@@ -259,8 +258,6 @@
i2c->data = (struct meson_i2c_data *)dev_get_driver_data(bus);
- clk_enable(&i2c->clk);
-
clrbits_le32(&i2c->regs->ctrl, REG_CTRL_START);
return 0;
@@ -269,33 +266,34 @@
static int meson_i2c_ofdata_to_platdata(struct udevice *dev)
{
struct meson_i2c *i2c = dev_get_priv(dev);
- int ret;
i2c->regs = dev_read_addr_ptr(dev);
- ret = clk_get_by_name(dev, "clk_i2c", &i2c->clk);
- if (ret < 0) {
- debug("%s: Can't get clock for %s: %d\n", __func__, dev->name,
- ret);
- return ret;
- }
-
return 0;
}
static const struct meson_i2c_data i2c_meson_meson6_data = {
.div_factor = 4,
.delay_ajust = 15,
+ .clkin_rate = MESON_I2C_CLK_RATE,
};
static const struct meson_i2c_data i2c_meson_gx_data = {
.div_factor = 4,
.delay_ajust = 15,
+ .clkin_rate = MESON_I2C_CLK_RATE,
};
static const struct meson_i2c_data i2c_meson_data = {
.div_factor = 3,
.delay_ajust = 15,
+ .clkin_rate = MESON_I2C_CLK_RATE,
+};
+
+static const struct meson_i2c_data i2c_meson_a1_data = {
+ .div_factor = 3,
+ .delay_ajust = 15,
+ .clkin_rate = 64000000,
};
static const struct dm_i2c_ops meson_i2c_ops = {
@@ -308,6 +306,7 @@
{ .compatible = "amlogic,meson-gx-i2c", .data = (long)&i2c_meson_gx_data },
{ .compatible = "amlogic,meson-gxbb-i2c", .data = (long)&i2c_meson_gx_data },
{ .compatible = "amlogic,meson-i2c", .data = (long)&i2c_meson_data },
+ { .compatible = "amlogic,meson-a1-i2c", .data = (long)&i2c_meson_a1_data },
{ }
};
diff --git a/drivers/i2c/muxes/Kconfig b/drivers/i2c/muxes/Kconfig
index b0a6b8c..b0da67c 100644
--- a/drivers/i2c/muxes/Kconfig
+++ b/drivers/i2c/muxes/Kconfig
@@ -43,4 +43,3 @@
a GPIO based I2C multiplexer. This driver provides access to
I2C busses connected through a MUX, which is controlled
through GPIO pins.
-
diff --git a/drivers/input/Kconfig b/drivers/input/Kconfig
index cbbcb0b..7afdafe 100644
--- a/drivers/input/Kconfig
+++ b/drivers/input/Kconfig
@@ -77,4 +77,3 @@
bool "Enable TWL4030 Input controller"
help
Enable TWL4030 Input controller
-
diff --git a/drivers/jtag/Makefile b/drivers/jtag/Makefile
new file mode 100644
index 0000000..feef07d
--- /dev/null
+++ b/drivers/jtag/Makefile
@@ -0,0 +1 @@
+obj-$(CONFIG_CMD_JTAG) += jtag.o
\ No newline at end of file
diff --git a/drivers/jtag/jtag.c b/drivers/jtag/jtag.c
new file mode 100644
index 0000000..8d43128
--- /dev/null
+++ b/drivers/jtag/jtag.c
@@ -0,0 +1,69 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <dm.h>
+#include <misc.h>
+#include <errno.h>
+#include <dm/pinctrl.h>
+#include <asm/arch/bl31_apis.h>
+#include <amlogic/jtag.h>
+
+static int meson_jtag_ioctl(struct udevice *dev, unsigned long cmd, void *buf)
+{
+ int jtag_id = *(int *)buf;
+ int jtag_type = JTAG_TYPE_GET(jtag_id);
+ int ret;
+
+ switch (cmd) {
+ case JTAG_SETPINMUX:
+ if (jtag_type == JTAG_A) {
+ ret = pinctrl_select_state(dev, "jtag_a_pins");
+ if (ret) {
+ printf("select state jtag_a_pins failed!\n");
+ return -EINVAL;
+ }
+ } else if (jtag_type == JTAG_B){
+ ret = pinctrl_select_state(dev, "jtag_b_pins");
+ if (ret) {
+ printf("select state jtag_b_pins failed!\n");
+ return -EINVAL;
+ }
+ } else if (jtag_type == SWD_A){
+ ret = pinctrl_select_state(dev, "swd_a_pins");
+ if (ret) {
+ printf("select state swd_a_pins failed!\n");
+ return -EINVAL;
+ }
+ }
+ break;
+ case JTAG_CLRPINMUX:
+ /* nothing to do now */
+ break;
+ case JTAG_EANBLE:
+ aml_set_jtag_state(JTAG_STATE_ON, jtag_id);
+ break;
+ case JTAG_DISABLE:
+ aml_set_jtag_state(JTAG_STATE_OFF, jtag_id);
+ break;
+ }
+
+ return 0;
+}
+
+static const struct misc_ops meson_jtag_ops = {
+ .ioctl = meson_jtag_ioctl,
+};
+
+static const struct udevice_id meson_jtag_ids[] = {
+ { .compatible = "amlogic, jtag" },
+ {}
+};
+
+U_BOOT_DRIVER(meson_jtag) = {
+ .name = "meson_jtag",
+ .id = UCLASS_MISC,
+ .of_match = meson_jtag_ids,
+ .ops = &meson_jtag_ops,
+};
diff --git a/drivers/led/Kconfig b/drivers/led/Kconfig
index 050fb3e..c5012a8 100644
--- a/drivers/led/Kconfig
+++ b/drivers/led/Kconfig
@@ -55,6 +55,14 @@
The GPIO driver must used driver model. LEDs are configured using
the device tree.
+config AML_LED_PWM
+ bool "LED support for AMLOGIC LED_PWM LEDs"
+ depends on LED && DM_PWM
+ help
+ Enable support for LEDs which are connected to PWM lines.
+ The PWM driver must used driver model. LEDs are configured using
+ the device tree.
+
config SPL_LED_GPIO
bool "LED support for GPIO-connected LEDs in SPL"
depends on SPL_LED && DM_GPIO
@@ -385,4 +393,3 @@
endif # LED_STATUS
endmenu
-
diff --git a/drivers/led/Makefile b/drivers/led/Makefile
index 160a8f3..eb3afa1 100644
--- a/drivers/led/Makefile
+++ b/drivers/led/Makefile
@@ -7,3 +7,4 @@
obj-$(CONFIG_LED_BCM6328) += led_bcm6328.o
obj-$(CONFIG_LED_BCM6358) += led_bcm6358.o
obj-$(CONFIG_$(SPL_)LED_GPIO) += led_gpio.o
+obj-$(CONFIG_AML_LED_PWM) += led_meson_pwm.o
diff --git a/drivers/led/led-uclass.c b/drivers/led/led-uclass.c
index 2859475..d69a61f 100644
--- a/drivers/led/led-uclass.c
+++ b/drivers/led/led-uclass.c
@@ -52,6 +52,28 @@
return ops->get_state(dev);
}
+#ifdef CONFIG_AML_LED_PWM
+int led_set_brightness(struct udevice *dev, int brightness)
+{
+ struct led_ops *ops = led_get_ops(dev);
+
+ if (!ops->set_brightness)
+ return -ENOSYS;
+
+ return ops->set_brightness(dev, brightness);
+}
+
+int led_get_brightness(struct udevice *dev)
+{
+ struct led_ops *ops = led_get_ops(dev);
+
+ if (!ops->set_brightness)
+ return -ENOSYS;
+
+ return ops->get_brightness(dev);
+}
+#endif
+
#ifdef CONFIG_LED_BLINK
int led_set_period(struct udevice *dev, int period_ms)
{
diff --git a/drivers/led/led_meson_pwm.c b/drivers/led/led_meson_pwm.c
new file mode 100644
index 0000000..bd09a0c
--- /dev/null
+++ b/drivers/led/led_meson_pwm.c
@@ -0,0 +1,151 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <led.h>
+#include <pwm.h>
+#include <dm/lists.h>
+#include <div64.h>
+
+struct led_pwm_priv {
+ struct udevice *pwm;
+};
+
+struct led_pwm_child_priv {
+ struct udevice *pwm;
+ uint max_brightness;
+ uint default_brightness;
+ uint brightness;
+ uint channel;
+ uint period_ns;
+};
+
+static int pwm_led_set_state(struct udevice *dev, enum led_state_t state)
+{
+ return 0;
+}
+
+static enum led_state_t pwm_led_get_state(struct udevice *dev)
+{
+ return 0;
+}
+
+static int pwm_led_set_brightness(struct udevice *dev, int brightness)
+{
+ struct led_pwm_child_priv *priv = dev_get_parent_platdata(dev);
+ unsigned long long duty = priv->period_ns;
+ int ret;
+
+ duty *= brightness;
+ do_div(duty, priv->max_brightness);
+ ret = pwm_set_config(priv->pwm, priv->channel, priv->period_ns, duty);
+ if (ret)
+ return ret;
+
+ ret = pwm_set_enable(priv->pwm, priv->channel, 1);
+ if (ret)
+ return ret;
+
+ priv->brightness = brightness;
+
+ return 0;
+}
+
+static int pwm_led_get_brightness(struct udevice *dev)
+{
+ struct led_pwm_child_priv *priv = dev_get_parent_platdata(dev);
+
+ return priv->brightness;
+}
+
+static int led_pwm_probe(struct udevice *dev)
+{
+ return 0;
+}
+
+static int led_pwm_remove(struct udevice *dev)
+{
+ return 0;
+}
+
+static int led_pwm_bind(struct udevice *parent)
+{
+ struct udevice *dev;
+ struct led_pwm_child_priv *child_priv;
+ struct ofnode_phandle_args args;
+ ofnode node;
+ int ret;
+
+ dev_for_each_subnode(node, parent) {
+ struct led_uc_plat *uc_plat;
+ const char *label;
+
+ label = ofnode_read_string(node, "label");
+ if (!label) {
+ debug("%s: node %s has no label\n", __func__,
+ ofnode_get_name(node));
+ return -EINVAL;
+ }
+ ret = device_bind_driver_to_node(parent, "pwm_led",
+ ofnode_get_name(node),
+ node, &dev);
+ if (ret)
+ return ret;
+
+ child_priv = dev_get_parent_platdata(dev);
+ ret = ofnode_read_u32(node, "max-brightness", &child_priv->max_brightness);
+ if (ret)
+ return ret;
+
+ ret = ofnode_read_u32(node, "default-brightness", &child_priv->default_brightness);
+ if (ret)
+ return ret;
+
+ ret = dev_read_phandle_with_args(dev, "pwms", "#pwm-cells", 0, 0,&args);
+ if (ret) {
+ debug("%s: Cannot get PWM phandle: ret=%d\n", __func__, ret);
+ return ret;
+ }
+
+ child_priv->channel = args.args[0];
+ child_priv->period_ns = args.args[1];
+ ret = uclass_get_device_by_ofnode(UCLASS_PWM, args.node, &child_priv->pwm);
+ if (ret) {
+ debug("%s: Cannot get PWM: ret=%d\n", __func__, ret);
+ return ret;
+ }
+
+ uc_plat = dev_get_uclass_platdata(dev);
+ uc_plat->label = label;
+ pwm_led_set_brightness(dev,child_priv->default_brightness);
+ }
+ return 0;
+}
+
+static const struct led_ops pwm_led_ops = {
+ .set_state = pwm_led_set_state,
+ .get_state = pwm_led_get_state,
+ .set_brightness = pwm_led_set_brightness,
+ .get_brightness = pwm_led_get_brightness,
+};
+
+static const struct udevice_id led_pwm_ids[] = {
+ { .compatible = "pwm-leds" },
+ { }
+};
+
+U_BOOT_DRIVER(led_pwm) = {
+ .name = "pwm_led",
+ .id = UCLASS_LED,
+ .of_match = led_pwm_ids,
+ .ops = &pwm_led_ops,
+ .priv_auto_alloc_size = sizeof(struct led_pwm_priv),
+ .per_child_platdata_auto_alloc_size = sizeof(struct led_pwm_child_priv),
+ .bind = led_pwm_bind,
+ .probe = led_pwm_probe,
+ .remove = led_pwm_remove,
+};
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 8190f14..2836ee4 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -35,4 +35,3 @@
block.
endmenu
-
diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig
index de4564c..4fbb5aa 100644
--- a/drivers/memory/Kconfig
+++ b/drivers/memory/Kconfig
@@ -16,4 +16,3 @@
time via four chip selects with 64M byte access per chip select.
endmenu
-
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index b39ba94..704c8dd 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -336,4 +336,3 @@
devices, depending on the device tree entry.
endmenu
-
diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig
index 9591457..3b744af 100644
--- a/drivers/mmc/Kconfig
+++ b/drivers/mmc/Kconfig
@@ -18,6 +18,12 @@
help
Enable write access to MMC and SD Cards
+config MMC_FBOOT
+ bool "support for MMC fast boot"
+ default n
+ help
+ Enable MMC fast boot
+
config MMC_BROKEN_CD
bool "Poll for broken card detection case"
help
@@ -619,21 +625,6 @@
This is needed if support for any SD/SDIO/MMC devices is required.
If unsure, say N.
-config AML_REMOVE_BOOTLOADER_PARTITION
- bool "aml remove bootloader partition macro"
- default n
- help
- aml remove bootloader partition macro.
-
-config AML_GPT_SYNC_ENTIRE_ENTRY
- bool "aml restore the entire backup GPT entry data macro"
- default n
- help
- Disable this macro, GPT entry's type_guid&uuid uses the mapping table in u-boot,
- and the attribute byte maybe is different.
- Enable this macro, When restoring a damaged GPT, restore all bytes from the
- backup GPT entry.
-
endif
config TEGRA124_MMC_DISABLE_EXT_LOOPBACK
@@ -666,4 +657,3 @@
config SYS_FSL_ERRATUM_ESDHC_A001
bool
-
diff --git a/drivers/mmc/aml_emmc_partition.c b/drivers/mmc/aml_emmc_partition.c
old mode 100755
new mode 100644
index d52d702..22d8a47
--- a/drivers/mmc/aml_emmc_partition.c
+++ b/drivers/mmc/aml_emmc_partition.c
@@ -1,10 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright 2016, Amlogic Inc
- * yonghui.yu
- *
- * Based vaguely on the Linux code
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <config.h>
@@ -19,8 +15,11 @@
#include <div64.h>
#include "mmc_private.h"
#include <emmc_partitions.h>
-#include <asm/arch-g12a/cpu_id.h>
+#include <amlogic/cpu_id.h>
#include <part_efi.h>
+#include <partition_table.h>
+#include <linux/compat.h>
+
DECLARE_GLOBAL_DATA_PTR;
/* using mbr*/
@@ -36,12 +35,8 @@
#endif
/* debug info*/
#define CONFIG_MPT_DEBUG (0)
-#define GPT_PRIORITY (1)
+#define GPT_SIZE 0x4400
-#ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY
-#define FALSE 0
-#define TRUE 1
-#endif
#define apt_err(fmt, ...) printf( "%s()-%d: " fmt , \
__func__, __LINE__, ##__VA_ARGS__)
@@ -84,12 +79,11 @@
/* virtual partitions which are in "reserved" */
#define MAX_MMC_VIRTUAL_PART_CNT (5)
-
/* BinaryLayout of partition table stored in rsv area */
struct ptbl_rsv {
char magic[4]; /* MPT */
unsigned char version[12]; /* binary version */
- unsigned int count; /* partition count in using */
+ int count; /* partition count in using */
int checksum;
struct partitions partitions[MAX_MMC_PART_NUM];
};
@@ -97,25 +91,20 @@
/* partition table for innor usage*/
struct _iptbl {
struct partitions *partitions;
- unsigned int count; /* partition count in use */
+ int count; /* partition count in use */
};
unsigned device_boot_flag = 0xff;
-bool is_partition_checked = false;
+extern bool is_partition_checked;
#ifndef CONFIG_AML_MMC_INHERENT_PART
/* fixme, name should be changed as aml_inherent_ptbl */
struct partitions emmc_partition_table[] = {
-#ifndef CONFIG_AML_REMOVE_BOOTLOADER_PARTITION
PARTITION_ELEMENT(MMC_BOOT_NAME, MMC_BOOT_DEVICE_SIZE, 0),
-#endif
PARTITION_ELEMENT(MMC_RESERVED_NAME, MMC_RESERVED_SIZE, 0),
/* prior partitions, same partition name with dts*/
/* partition size will be overide by dts*/
- /* not needed for google*/
-#if 0
PARTITION_ELEMENT(MMC_CACHE_NAME, 0, 0),
-#endif
PARTITION_ELEMENT(MMC_ENV_NAME, MMC_ENV_SIZE, 0),
};
@@ -133,6 +122,8 @@
#endif
VIRTUAL_PARTITION_ELEMENT(MMC_KEY_NAME, EMMCKEY_RESERVE_OFFSET, MMC_KEY_SIZE),
VIRTUAL_PARTITION_ELEMENT(MMC_PATTERN_NAME, CALI_PATTERN_OFFSET, CALI_PATTERN_SIZE),
+ VIRTUAL_PARTITION_ELEMENT(MMC_MAGIC_NAME, MAGIC_OFFSET, MAGIC_SIZE),
+ VIRTUAL_PARTITION_ELEMENT(MMC_RANDOM_NAME, RANDOM_OFFSET, RANDOM_SIZE),
#ifndef DTB_BIND_KERNEL
VIRTUAL_PARTITION_ELEMENT(MMC_DTB_NAME, DTB_OFFSET, DTB_SIZE),
#endif
@@ -167,26 +158,24 @@
static int _get_part_index_by_name(struct partitions *tbl,
int cnt, const char *name)
{
- int i=0;
- struct partitions *part = NULL;
+ int i=0;
+ struct partitions *part = NULL;
- while (i < cnt) {
- part = &tbl[i];
- if (!strcmp(name, part->name)) {
- apt_info("find %s @ tbl[%d]\n", name, i);
- break;
- }
- i++;
- };
- if (i == cnt) {
- i = -1;
- apt_wrn("do not find match in table %s\n", name);
- }
- return i;
+ while (i < cnt) {
+ part = &tbl[i];
+ if (!strcmp(name, part->name)) {
+ apt_info("find %s @ tbl[%d]\n", name, i);
+ break;
+ }
+ i++;
+ };
+ if (i == cnt) {
+ i = -1;
+ apt_wrn("do not find match in table %s\n", name);
+ }
+ return i;
}
-
-
static struct partitions *_find_partition_by_name(struct partitions *tbl,
int cnt, const char *name)
{
@@ -194,7 +183,6 @@
struct partitions *part = NULL;
while (i < cnt) {
-
part = &tbl[i];
if (!strcmp(name, part->name)) {
apt_info("find %s @ tbl[%d]\n", name, i);
@@ -253,6 +241,103 @@
}
#endif
+int fill_ept_by_gpt(struct mmc *mmc, struct _iptbl *p_iptbl_ept)
+{
+ struct blk_desc *dev_desc = mmc_get_blk_desc(mmc);
+ gpt_entry *gpt_pte = NULL;
+ int i, k;
+ size_t efiname_len, dosname_len;
+ struct _iptbl *ept = p_iptbl_ept;
+ struct partitions *partitions = ept->partitions;
+
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz);
+
+ if (!dev_desc) {
+ printf("%s: Invalid Argument(s)\n", __func__);
+ return 1;
+ }
+
+ if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
+ gpt_head, &gpt_pte) != 1) {
+ if (is_gpt_valid(dev_desc, (dev_desc->lba - 1),
+ gpt_head, &gpt_pte) != 1) {
+ printf("%s: invalid gpt ***\n", __func__);
+ return 1;
+ }
+ printf("%s: *** Using Backup GPT ***\n", __func__);
+ }
+
+ for (i = 0; i < le32_to_cpu(gpt_head->num_partition_entries); i++) {
+ if (!is_pte_valid(&gpt_pte[i]))
+ break;
+
+ partitions[i].offset = le64_to_cpu(gpt_pte[i].starting_lba << 9ULL);
+ partitions[i].size = ((le64_to_cpu(gpt_pte[i].ending_lba) + 1) -
+ le64_to_cpu(gpt_pte[i].starting_lba)) << 9ULL;
+ /* mask flag */
+ partitions[i].mask_flags =
+ (uint32_t)le64_to_cpu(gpt_pte[i].attributes.fields.type_guid_specific);
+ /* partition name */
+ efiname_len = sizeof(gpt_pte[i].partition_name)
+ / sizeof(efi_char16_t);
+ dosname_len = sizeof(partitions[i].name);
+
+ memset(partitions[i].name, 0, sizeof(partitions[i].name));
+ for (k = 0; k < min(dosname_len, efiname_len); k++)
+ partitions[i].name[k] = (char)gpt_pte[i].partition_name[k];
+
+ if (strcmp(partitions[i].name, "boot_a") == 0) {
+ has_boot_slot = 1;
+ printf("set has_boot_slot = 1\n");
+ } else if (strcmp(partitions[i].name, "boot") == 0) {
+ has_boot_slot = 0;
+ printf("set has_boot_slot = 0\n");
+ }
+ if (strcmp(partitions[i].name, "system_a") == 0)
+ has_system_slot = 1;
+ else if (strcmp(partitions[i].name, "system") == 0)
+ has_system_slot = 0;
+
+ if (strcmp(partitions[i].name, "super") == 0) {
+ dynamic_partition = true;
+ env_set("partition_mode", "dynamic");
+ printf("enable dynamic_partition\n");
+ }
+
+ if (strncmp(partitions[i].name, "vendor_boot", 11) == 0) {
+ vendor_boot_partition = true;
+ env_set("vendor_boot_mode", "true");
+ printf("enable vendor_boot\n");
+ }
+ }
+ ept->count = i;
+ free(gpt_pte);
+ return 0;
+}
+
+/*
+ * 1. gpt is writed on emmc
+ * parse gpt and compose ept and part_table
+ *
+ */
+int get_ept_from_gpt(struct mmc *mmc)
+{
+ struct partitions *ptbl = p_iptbl_ept->partitions;
+
+ if (!fill_ept_by_gpt(mmc, p_iptbl_ept)) {
+ printf("get ept from gpt success\n");
+ gpt_partition = true;
+ return 0;
+ } else if (part_table && part_table[0].offset != 0) {
+ memcpy(ptbl, part_table, sizeof(struct partitions) * parts_total_num);
+ p_iptbl_ept->count = parts_total_num;
+ printf("get ept from part_table success\n");
+ gpt_partition = true;
+ return 0;
+ }
+
+ return 1;
+}
static struct partitions * get_ptbl_from_dtb(struct mmc *mmc)
{
@@ -308,9 +393,6 @@
#endif
}
-
-
-
static struct partitions *is_prio_partition(struct _iptbl *list, struct partitions *part)
{
int i;
@@ -351,17 +433,9 @@
_dump_part_tbl(part, itbl->count);
#endif
-#if CONFIG_AML_GPT
- part->offset = RESERVED_GPT_OFFSET;
-#endif
-
if (!strcmp(part->name, "bootloader")) {
part->offset = 0;
gap = MMC_BOOT_PARTITION_RESERVED;
-#ifdef CONFIG_AML_REMOVE_BOOTLOADER_PARTITION
- } else {
- part->offset = MMC_BOOT_PARTITION_RESERVED + MMC_BOOT_DEVICE_SIZE;
-#endif
}
for (i=1; i<itbl->count; i++) {
/**/
@@ -493,10 +567,7 @@
ret = -2;
goto _out;
}
- if (src->count > MAX_MMC_PART_NUM) {
- ret = -3;
- goto _out;
- }
+
dst->count = src->count;
memcpy(dst->partitions, src->partitions, sizeof(struct partitions) * src->count);
@@ -504,7 +575,6 @@
return ret;
}
-
/* get ptbl from rsv area from emmc */
static int get_ptbl_rsv(struct mmc *mmc, struct _iptbl *rsv)
{
@@ -572,7 +642,6 @@
return ret;
}
-
/* update partition tables from src
if success, return 0;
else, return 1
@@ -700,7 +769,6 @@
return ret;
}
-
/* iptbl buffer opt. */
static int _zalloc_iptbl(struct _iptbl **_iptbl)
{
@@ -1036,7 +1104,6 @@
return ret;
}
-#ifdef CONFIG_AML_GPT
int is_gpt_changed(struct mmc *mmc, struct _iptbl *p_iptbl_ept)
{
int i, k;
@@ -1050,13 +1117,14 @@
char name[PARTNAME_SZ];
int gpt_changed = 0;
struct blk_desc *dev_desc = mmc_get_blk_desc(mmc);
- ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz);
- if (!dev_desc) {
+ if (dev_desc == NULL) {
printf("%s: Invalid Argument(s)\n", __func__);
return 1;
}
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz);
+
if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
gpt_head, &gpt_pte) != 1) {
printf("%s: ***ERROR:Invalid GPT ***\n", __func__);
@@ -1069,7 +1137,6 @@
printf("%s: *** Using Backup GPT ***\n",
__func__);
}
- //return 1;
}
for (i = 0; i < le32_to_cpu(gpt_head->num_partition_entries); i++) {
if (!is_pte_valid(&gpt_pte[i]))
@@ -1077,7 +1144,7 @@
offset = le64_to_cpu(gpt_pte[i].starting_lba<<9ULL);
if (partitions[i].offset != offset) {
- pr_info("Caution! GPT offset had been changed\n");
+ printf("Caution! GPT offset had been changed\n");
gpt_changed = 1;
break;
}
@@ -1086,13 +1153,13 @@
le64_to_cpu(gpt_pte[i].starting_lba)) << 9ULL;
if (i == parts_num - 1) {
if ((partitions[i].size - GPT_TOTAL_SIZE) != size) {
- pr_info("Caution! GPT size had been changed\n");
+ printf("Caution! GPT size had been changed\n");
gpt_changed = 1;
break;
}
} else {
if (partitions[i].size != size) {
- pr_info("Caution! GPT size had been changed\n");
+ printf("Caution! GPT size had been changed\n");
gpt_changed = 1;
break;
}
@@ -1106,7 +1173,7 @@
for (k = 0; k < efiname_len; k++)
name[k] = (char)gpt_pte[i].partition_name[k];
if (strcmp(name, partitions[i].name) != 0) {
- pr_info("Caution! GPT name had been changed\n");
+ printf("Caution! GPT name had been changed\n");
gpt_changed = 1;
break;
}
@@ -1114,163 +1181,85 @@
}
if ((i != parts_num) && (gpt_changed == 0)) {
gpt_changed = 1;
- pr_info("Caution! GPT number had been changed\n");
+ printf("Caution! GPT number had been changed\n");
}
free(gpt_pte);
return gpt_changed;
}
+
int is_gpt_broken(struct mmc *mmc)
{
gpt_entry *gpt_pte = NULL;
int broken_status = 0;
struct blk_desc *dev_desc = mmc_get_blk_desc(mmc);
- ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz);
if (!dev_desc) {
printf("%s: Invalid Argument(s)\n", __func__);
return 1;
}
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz);
if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
gpt_head, &gpt_pte) != 1) {
broken_status += 1;
printf("%s: ***ERROR:Invalid GPT ***\n", __func__);
- } else {
- free(gpt_pte);
}
if (is_gpt_valid(dev_desc, (dev_desc->lba - 1),
gpt_head, &gpt_pte) != 1) {
printf("%s: ***ERROR: Invalid Backup GPT ***\n",
__func__);
broken_status += 2;
- } else {
- free(gpt_pte);
}
+ if (broken_status != 3)
+ free(gpt_pte);
return broken_status;
}
-int fill_ept_by_gpt(struct mmc *mmc, struct _iptbl *p_iptbl_ept)
-{
+/*
+ * check is gpt is valid
+ * if valid return 0
+ * else return 1
+ */
+int aml_gpt_valid(struct mmc *mmc) {
struct blk_desc *dev_desc = mmc_get_blk_desc(mmc);
- ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz);
- gpt_entry *gpt_pte = NULL;
- int i, k;
- size_t efiname_len, dosname_len;
- struct _iptbl *ept = p_iptbl_ept;
- struct partitions *partitions = ept->partitions;
-
if (!dev_desc) {
printf("%s: Invalid Argument(s)\n", __func__);
return 1;
- }
-
- if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
+ } else {
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz);
+ gpt_entry *gpt_pte = NULL;
+ if (is_gpt_valid(dev_desc, GPT_PRIMARY_PARTITION_TABLE_LBA,
gpt_head, &gpt_pte) != 1) {
- printf("%s: ***ERROR:Invalid GPT ***\n", __func__);
- if (is_gpt_valid(dev_desc, (dev_desc->lba - 1),
+ if (is_gpt_valid(dev_desc, (dev_desc->lba - 1),
gpt_head, &gpt_pte) != 1) {
- printf("%s: ***ERROR: Invalid Backup GPT ***\n",
+ printf("gpt is invalid\n");
+ return 1;
+ } else {
+ printf("%s: *** Using Backup GPT ***\n",
__func__);
- return 1;
- } else {
- printf("%s: *** Using Backup GPT ***\n",
- __func__);
+ }
}
- //return 1;
}
- for (i = 0; i < le32_to_cpu(gpt_head->num_partition_entries); i++) {
- if (!is_pte_valid(&gpt_pte[i]))
- break;
-
- partitions[i].offset = le64_to_cpu(gpt_pte[i].starting_lba<<9ULL);
- partitions[i].size = ((le64_to_cpu(gpt_pte[i].ending_lba)+1) -
- le64_to_cpu(gpt_pte[i].starting_lba)) << 9ULL;
-
- #ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY
- memcpy(partitions[i].type_guid.b, gpt_pte[i].partition_type_guid.b, sizeof(efi_guid_t));
- memcpy(partitions[i].uuid.b, gpt_pte[i].unique_partition_guid.b, sizeof(efi_guid_t));
- memcpy(&(partitions[i].attributes), &(gpt_pte[i].attributes), sizeof(gpt_entry_attributes));
- #endif
- /* partition name */
- efiname_len = sizeof(gpt_pte[i].partition_name)
- / sizeof(efi_char16_t);
- dosname_len = sizeof(partitions[i].name);
-
- memset(partitions[i].name, 0, sizeof(partitions[i].name));
- for (k = 0; k < min(dosname_len, efiname_len); k++)
- partitions[i].name[k] = (char)gpt_pte[i].partition_name[k];
-
- }
- ept->count = i;
- free(gpt_pte);
return 0;
}
-#ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY
-void trans_ept_to_diskpart(struct _iptbl *ept, disk_partition_t *disk_part, bool gpt_broken_status) {
-#else
+
void trans_ept_to_diskpart(struct _iptbl *ept, disk_partition_t *disk_part) {
-#endif
struct partitions *part = ept->partitions;
int count = ept->count;
int i;
for (i = 0; i < count; i++) {
disk_part[i].start = part[i].offset >> 9;
strcpy((char *)disk_part[i].name, part[i].name);
-#ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY
- if (gpt_broken_status) {
- memcpy(disk_part[i].partition_type_guid.b, part[i].type_guid.b, sizeof(efi_guid_t));
- memcpy(disk_part[i].unique_partition_guid.b, part[i].uuid.b, sizeof(efi_guid_t));
- memcpy(&(disk_part[i].attributes), &(part[i].attributes), sizeof(gpt_entry_attributes));
- } else {
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- char *str_uuid;
- unsigned char *bin_uuid;
-#endif
+ /* store maskflag into type, 8bits ONLY! */
+ disk_part[i].type[0] = (uchar)part[i].mask_flags;
#ifdef CONFIG_PARTITION_TYPE_GUID
- char *str_type_guid;
- unsigned char *bin_type_guid;
-#endif
-#ifdef CONFIG_PARTITION_TYPE_GUID
- str_type_guid = part[i].name;
- bin_type_guid = disk_part[i].partition_type_guid.b;
-#endif
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- gen_rand_uuid_str(disk_part[i].uuid, UUID_STR_FORMAT_STD);
- str_uuid = disk_part[i].uuid;
- bin_uuid = disk_part[i].unique_partition_guid.b;
-#endif
-#ifdef CONFIG_PARTITION_TYPE_GUID
- if (strlen(str_type_guid)) {
- if (uuid_str_to_bin(str_type_guid, bin_type_guid,
- UUID_STR_FORMAT_GUID)) {
-#ifdef CONFIG_AML_GPT
- char str[8] = {"default"};
- uuid_str_to_bin(str, bin_type_guid,
- UUID_STR_FORMAT_GUID);
- }
- }
-#else
- printf("Partition no. %d: invalid type guid: %s\n",
- i, str_type_guid);
- return;
- }
- }
-#endif
-#endif
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- if (uuid_str_to_bin(str_uuid, bin_uuid, UUID_STR_FORMAT_GUID)) {
- printf("Partition no. %d: invalid guid: %s\n",
- i, str_uuid);
- return;
- }
-#endif
- }
-#else
strcpy((char *)disk_part[i].type_guid, part[i].name);
+#endif
+#ifdef CONFIG_RANDOM_UUID
gen_rand_uuid_str(disk_part[i].uuid, UUID_STR_FORMAT_STD);
#endif
disk_part[i].bootable = 0;
@@ -1282,11 +1271,73 @@
return;
}
+#ifdef CONFIG_AML_PARTITION
+/*
+ * compare ept and rsv
+ *
+ * if different:
+ * update rsv write back on emmc
+ *
+ */
+int enable_rsv_part_table(struct mmc *mmc)
+{
+ struct _iptbl *p_iptbl_rsv = NULL;
+ int ret = -1;
+ /* try to get partition table from rsv */
+ ret = _zalloc_iptbl(&p_iptbl_rsv);
+ if (ret)
+ return ret;
-
+ if (!get_ptbl_rsv(mmc, p_iptbl_rsv)) {
+ if (_cmp_iptbl(p_iptbl_ept, p_iptbl_rsv)) {
+ apt_wrn("update rsv with gpt!\n");
+ ret = update_ptbl_rsv(mmc, p_iptbl_ept);
+ if (ret)
+ printf("update rsv with gpt failed\n");
+ }
+ }
+ _free_iptbl(p_iptbl_rsv);
+ return ret;
+}
#endif
+int resize_gpt(struct mmc *mmc)
+{
+ gpt_header *gpt_h;
+ void *buf;
+ int ret;
+ struct blk_desc *dev_desc = mmc_get_blk_desc(mmc);
+
+ buf = malloc(GPT_SIZE);
+ if (!buf) {
+ printf("not enough space for gpt buffer\n");
+ return -1;
+ }
+
+ ret = mmc_gpt_read(buf);
+ if (ret == 0) {
+ /* determine start of GPT Header in the buffer */
+ gpt_h = buf + (GPT_PRIMARY_PARTITION_TABLE_LBA *
+ dev_desc->blksz);
+ if (le64_to_cpu(gpt_h->last_usable_lba) > dev_desc->lba) {
+ ret = write_mbr_and_gpt_partitions(dev_desc, (u_char *)buf);
+ if (ret) {
+ printf("%s: writing GPT partitions failed\n", __func__);
+ free(buf);
+ return -1;
+ }
+ printf("resize gpt success\n");
+ }
+ } else if (ret == -1) {
+ printf("%s: read gpt failed\n", __func__);
+ free(buf);
+ return -1;
+ }
+ free(buf);
+ return 0;
+}
+
/***************************************************
* init partition table for emmc device.
* returns 0 means ok.
@@ -1329,6 +1380,20 @@
/* partition table from dtb/code/emmc rsv */
struct _iptbl iptbl_dtb, iptbl_inh;
+ /* For re-entry */
+ if (!p_iptbl_ept) {
+ ret = _zalloc_iptbl(&p_iptbl_ept);
+ if (ret)
+ goto _out;
+ } else {
+ p_iptbl_ept->count = 0;
+ memset(p_iptbl_ept->partitions, 0,
+ sizeof(struct partitions) * MAX_PART_COUNT);
+ }
+
+ if (resize_gpt(mmc))
+ goto _out;
+
/* calculate inherent offset */
iptbl_inh.count = get_emmc_partition_arraysize();
if (iptbl_inh.count) {
@@ -1336,20 +1401,20 @@
_calculate_offset(mmc, &iptbl_inh, 0);
}
apt_info("inh count %d\n", iptbl_inh.count);
+
+ ret = get_ept_from_gpt(mmc);
+ if (!ret) {
+#ifdef CONFIG_AML_PARTITION
+ return enable_rsv_part_table(mmc);
+#else
+ return ret;
+#endif
+ }
+
#if (CONFIG_MPT_DEBUG)
apt_info("inherent partition table\n");
_dump_part_tbl(iptbl_inh.partitions, iptbl_inh.count);
#endif
- /* For re-entry */
- if (NULL == p_iptbl_ept) {
- ret = _zalloc_iptbl(&p_iptbl_ept);
- if (ret)
- goto _out;
- } else {
- p_iptbl_ept->count = 0;
- memset(p_iptbl_ept->partitions, 0,
- sizeof(struct partitions)*MAX_PART_COUNT);
- }
/* try to get partition table from dtb(ddr or emmc) */
iptbl_dtb.partitions = get_ptbl_from_dtb(mmc);
@@ -1378,11 +1443,8 @@
ret = -1;
goto _out;
}
- } else {
-#ifdef BL33_DEBUG_PRINT
+ } else
apt_wrn("get partition table from dtb failed\n");
-#endif
- }
#ifndef CONFIG_AML_PARTITION
if (cpu_id.family_id < MESON_CPU_MAJOR_ID_G12B) {
printf("CONFIG_AML_PARTITION should define before G12B\n");
@@ -1424,7 +1486,7 @@
}
}
- if (update && iptbl_dtb.partitions) {
+ if (update && iptbl_dtb.partitions && (aml_gpt_valid(mmc) != 0)) {
apt_wrn("update rsv with dtb!\n");
ret = update_ptbl_rsv(mmc, p_iptbl_ept);
}
@@ -1440,63 +1502,7 @@
}
}
#endif
-#ifdef CONFIG_AML_GPT
- char *str_disk_guid;
- int gpt_priority = GPT_PRIORITY;
- disk_partition_t *disk_partition;
- int dcount = p_iptbl_ept->count;
- struct blk_desc *dev_desc = mmc_get_blk_desc(mmc);
- disk_partition = calloc(1, PAD_TO_BLOCKSIZE(sizeof(disk_partition_t) * dcount, dev_desc));
-#ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY
- trans_ept_to_diskpart(p_iptbl_ept, disk_partition, FALSE);
-#else
- trans_ept_to_diskpart(p_iptbl_ept, disk_partition);
-#endif
- str_disk_guid = malloc(UUID_STR_LEN + 1);
- if (str_disk_guid == NULL) {
- free(disk_partition);
- return -ENOMEM;
- }
- gen_rand_uuid_str(str_disk_guid, UUID_STR_FORMAT_STD);
- if (part_test_efi(mmc_get_blk_desc(mmc)) != 0) {
- ret = gpt_restore(mmc_get_blk_desc(mmc), str_disk_guid, disk_partition, dcount);
- printf("GPT IS RESTORED %s\n", ret ? "Failed!" : "OK!");
- } else if (is_gpt_changed(mmc, p_iptbl_ept)) {
- if (gpt_priority) {
- fill_ept_by_gpt(mmc, p_iptbl_ept);
- pr_info("and gpt has higher priority, so ept had been update\n");
- } else {
- gpt_restore(mmc_get_blk_desc(mmc), str_disk_guid, disk_partition, dcount);
- pr_info("but EPT has higher priority, so gpt had been recover\n");
- }
- }
-
- int broken_status = is_gpt_broken(mmc);
- if (broken_status != 0 && broken_status != 3) {
- fill_ept_by_gpt(mmc, p_iptbl_ept);
- free(disk_partition);
- dcount = p_iptbl_ept->count;
- disk_partition = calloc(1, PAD_TO_BLOCKSIZE(sizeof(disk_partition_t) * dcount, dev_desc));
-#ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY
- trans_ept_to_diskpart(p_iptbl_ept, disk_partition, TRUE);
- memset(str_disk_guid, 0, UUID_STR_LEN + 1);
- get_disk_guid(mmc_get_blk_desc(mmc), str_disk_guid);
-#else
- trans_ept_to_diskpart(p_iptbl_ept, disk_partition);
-#endif
- ret = gpt_restore(mmc_get_blk_desc(mmc), str_disk_guid, disk_partition, p_iptbl_ept->count);
- if (broken_status == 1)
- printf("The first gpt has been restore\n");
- else if (broken_status == 2)
- printf("The second gpt has been restore\n");
- else
- printf("Both gpt has been restore\n");
- }
-
- free(str_disk_guid);
- free(disk_partition);
-#endif
/* init part again */
part_init(mmc_get_blk_desc(mmc));
@@ -1508,17 +1514,23 @@
return ret;
}
-
struct partitions *find_mmc_partition_by_name (char const *name)
{
struct partitions *partition = NULL;
+ apt_info("p_iptbl_ept %p\n", p_iptbl_ept);
if (NULL == p_iptbl_ept) {
goto _out;
}
partition = p_iptbl_ept->partitions;
partition = _find_partition_by_name(partition,
p_iptbl_ept->count, name);
+ apt_info("partition %p\n", partition);
+ if (!partition) {
+ partition = _find_partition_by_name(emmc_partition_table,
+ get_emmc_partition_arraysize(), name);
+ }
+ apt_info("partition %p\n", partition);
_out:
return partition;
}
@@ -1612,7 +1624,6 @@
}
#endif
-
struct partitions *aml_get_partition_by_name(const char *name)
{
struct partitions *partition = NULL;
@@ -1704,3 +1715,21 @@
return ret;
}
+/*
+ * get the partition info by number
+ * return value
+ * < 0 means no partition found
+ * >= 0 means valid partition
+ */
+__weak struct partitions *get_partition_info_by_num(const int num)
+{
+ struct partitions *partition = NULL;
+
+ if ((NULL == p_iptbl_ept)
+ || (num >= p_iptbl_ept->count))
+ goto _out;
+ partition = &p_iptbl_ept->partitions[num];
+
+_out:
+ return partition;
+}
diff --git a/drivers/mmc/meson_gx_mmc.c b/drivers/mmc/meson_gx_mmc.c
index 9a74fea..5fa6e1a 100644
--- a/drivers/mmc/meson_gx_mmc.c
+++ b/drivers/mmc/meson_gx_mmc.c
@@ -14,7 +14,9 @@
#include <asm/arch/cpu_sdio.h>
#include <asm/arch/sd_emmc.h>
#include <linux/log2.h>
+#include <dm/pinctrl.h>
#include "mmc_private.h"
+#include <asm/arch/register.h>
static inline void *get_regbase(const struct mmc *mmc)
{
@@ -105,7 +107,7 @@
struct mmc *mmc = host->mmc;
uint32_t clk = 0, clk_src = 0, clk_div = 0;
uint32_t co_phase = 0, tx_phase = 0;
- uint32_t meson_mmc_clk = 0;
+ uint32_t meson_mmc_clk = 0, cfg = 0;
if (!mmc->clock)
return;
@@ -113,14 +115,27 @@
if (mmc->clock > 12000000) {
clk = 1000000000;
clk_src = 1;
+ if (host->src_clk != 0) {
+ clk = host->src_clk;
+ clk_src = 0;
+ }
+ clk_disable(&host->xtal);
+ clk_set_parent(&host->mux, &host->div2);
+ clk_set_rate(&host->div, clk);
+ cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
+ cfg |= CFG_AUTO_CLK;
+ meson_write(mmc, cfg, MESON_SD_EMMC_CFG);
} else {
clk = 24000000;
clk_src = 0;
+ clk_enable(&host->xtal);
+ clk_set_rate(&host->div, clk);
}
clk_div = clk / mmc->clock;
if (clk % mmc->clock)
clk_div++;
+ mmc->clock = clk / clk_div;
if (mmc->ddr_mode) {
clk_div /= 2;
pr_info("DDR: \n");
@@ -131,32 +146,34 @@
case MMC_LEGACY:
case SD_LEGACY:
co_phase = dev_read_u32_default(mmc->dev, "init_co_phase", 2);
- tx_phase = dev_read_u32_default(mmc->dev, "init_to_phase", 0);
+ tx_phase = dev_read_u32_default(mmc->dev, "init_tx_phase", 0);
break;
case MMC_HS:
case MMC_HS_52:
dev_read_u32(mmc->dev, "hs_co_phase", &co_phase);
- dev_read_u32(mmc->dev, "hs_to_phase", &tx_phase);
+ dev_read_u32(mmc->dev, "hs_tx_phase", &tx_phase);
break;
case SD_HS:
+ dev_read_u32(mmc->dev, "sd_hs_co_phase", &co_phase);
+ dev_read_u32(mmc->dev, "sd_hs_tx_phase", &tx_phase);
break;
case MMC_HS_200:
dev_read_u32(mmc->dev, "hs2_co_phase", &co_phase);
- dev_read_u32(mmc->dev, "hs2_to_phase", &tx_phase);
+ dev_read_u32(mmc->dev, "hs2_tx_phase", &tx_phase);
break;
case UHS_SDR104:
dev_read_u32(mmc->dev, "sdr104_co_phase", &co_phase);
- dev_read_u32(mmc->dev, "sdr104_to_phase", &tx_phase);
+ dev_read_u32(mmc->dev, "sdr104_tx_phase", &tx_phase);
break;
case MMC_DDR_52:
dev_read_u32(mmc->dev, "ddr_co_phase", &co_phase);
- dev_read_u32(mmc->dev, "ddr_to_phase", &tx_phase);
+ dev_read_u32(mmc->dev, "ddr_tx_phase", &tx_phase);
break;
case MMC_HS_400:
break;
default:
co_phase = dev_read_u32_default(mmc->dev, "init_co_phase", 2);
- tx_phase = dev_read_u32_default(mmc->dev, "init_to_phase", 0);
+ tx_phase = dev_read_u32_default(mmc->dev, "init_tx_phase", 0);
break;
}
@@ -186,9 +203,7 @@
meson_write(mmc, 0, MESON_SD_EMMC_DELAY2);
meson_write(mmc, 0, MESON_SD_EMMC_ADJUST);
}
-
meson_mmc_config_clock(host);
-
meson_mmc_cfg = meson_read(mmc, MESON_SD_EMMC_CFG);
meson_mmc_cfg &= ~CFG_BUS_WIDTH_MASK;
@@ -201,24 +216,12 @@
else
return -EINVAL;
- /* 512 bytes block length */
- meson_mmc_cfg &= ~CFG_BL_LEN_MASK;
- meson_mmc_cfg |= CFG_BL_LEN_512;
-
- /* Response timeout 256 clk */
- meson_mmc_cfg &= ~CFG_RESP_TIMEOUT_MASK;
- meson_mmc_cfg |= CFG_RESP_TIMEOUT_256;
-
- /* Command-command gap 16 clk */
- meson_mmc_cfg &= ~CFG_RC_CC_MASK;
- meson_mmc_cfg |= CFG_RC_CC_16;
-
meson_write(mmc, meson_mmc_cfg, MESON_SD_EMMC_CFG);
return 0;
}
-static void meson_mmc_setup_cmd(struct mmc *mmc, struct mmc_data *data,
+__attribute__((unused)) static void meson_mmc_setup_cmd(struct mmc *mmc, struct mmc_data *data,
struct mmc_cmd *cmd)
{
uint32_t meson_mmc_cmd = 0, cfg, bl_len = 0;
@@ -264,7 +267,7 @@
meson_write(mmc, meson_mmc_cmd, MESON_SD_EMMC_CMD_CFG);
}
-static void meson_mmc_setup_addr(struct mmc *mmc, struct mmc_data *data)
+__attribute__((unused)) static void meson_mmc_setup_addr(struct mmc *mmc, struct mmc_data *data)
{
struct meson_mmc_platdata *pdata = mmc->priv;
unsigned int data_size;
@@ -371,10 +374,8 @@
struct sd_emmc_desc_info *desc_cur)
{
struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
- struct meson_host *host = dev_get_priv(dev);
- struct mmc *mmc = &pdata->mmc;
uint32_t *meson_mmc_cmd = NULL;
- unsigned int data_size, blks = 0, desc_cnt = 0, bl_len = 0;
+ unsigned int data_size, desc_cnt = 0;
uint32_t data_addr = 0;
meson_mmc_cmd = &(desc_cur->cmd_info);
@@ -455,7 +456,9 @@
}
meson_mmc_cmd = &(desc_cur->cmd_info);
- *meson_mmc_cmd |= CMD_CFG_TIMEOUT_4S;
+ /* It takes longer to erase large amounts of data */
+ if (cmd->cmdidx != MMC_CMD_ERASE)
+ *meson_mmc_cmd |= CMD_CFG_TIMEOUT_4S;
*meson_mmc_cmd |= CMD_CFG_END_OF_CHAIN;
}
@@ -498,7 +501,6 @@
struct mmc_data *data)
{
struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
- struct meson_host *host = dev_get_priv(dev);
struct mmc *mmc = &pdata->mmc;
uint32_t status;
ulong start;
@@ -508,13 +510,23 @@
if (data && data->blocksize > MMC_MAX_BLOCK_LEN)
return -EINVAL;
- ret = meson_mmc_desc_transfer(dev, cmd, data);
+#if 0
+ meson_mmc_setup_cmd(mmc, data, cmd);
+ meson_mmc_setup_addr(mmc, data);
- /* use 10s timeout */
+ meson_write(mmc, cmd->cmdarg, MESON_SD_EMMC_CMD_ARG);
+
+ /* reset status bits */
+ meson_write(mmc, STATUS_MASK, MESON_SD_EMMC_STATUS);
+#else
+ ret = meson_mmc_desc_transfer(dev, cmd, data);
+#endif
+
+ /* use 30s timeout */
start = get_timer(0);
do {
status = meson_read(mmc, MESON_SD_EMMC_STATUS);
- } while(!(status & STATUS_END_OF_CHAIN) && get_timer(start) < 10000);
+ } while(!(status & STATUS_END_OF_CHAIN) && get_timer(start) < 30000);
meson_mmc_read_response(mmc, cmd);
@@ -533,11 +545,15 @@
void meson_hw_reset(struct udevice *dev)
{
- struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
struct meson_host *host = dev_get_priv(dev);
- struct mmc *mmc = &pdata->mmc;
+ u32 cfg = 0;
- if (!strcmp(mmc->cfg->name, "emmc")) {
+ /* send the initialization stream: 74 clock cycles */
+ cfg = meson_read(host->mmc, MESON_SD_EMMC_CFG);
+ cfg &= ~CFG_AUTO_CLK;
+ meson_write(host->mmc, cfg, MESON_SD_EMMC_CFG);
+
+ if (aml_card_type_mmc(host)) {
dm_gpio_set_value(&host->gpio_reset, 0);
mdelay(2);
dm_gpio_set_value(&host->gpio_reset, 1);
@@ -550,13 +566,28 @@
struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
struct meson_host *host = dev_get_priv(dev);
struct mmc *mmc = &pdata->mmc;
- int ret = 0;
+ int ret = 0, sduart_f = 0;
+ u32 status = 0;
- if (!strcmp(mmc->cfg->name, "sd")) {
+ if (aml_card_type_non_sdio(host)) {
+ sduart_f = pinctrl_select_state(mmc->dev, "sd_all_pins");
ret = dm_gpio_get_value(&host->gpio_cd);
if (ret < 0)
pr_err("card detect get failed!\n");
- host->is_in = !ret;
+ else if (!ret) {
+ host->is_in = 1;
+ status = meson_read(mmc, MESON_SD_EMMC_STATUS);
+ if (!(status & (1 << 19)) && !sduart_f) {
+ pinctrl_select_state(mmc->dev, "sd_uart");
+ host->is_sduart = 1;
+ host->is_in = 0;
+ printf("uart in\n");
+ } else {
+ host->is_sduart = 0;
+ printf("card in\n");
+ }
+ } else
+ host->is_in = 0;
}
return host->is_in;
@@ -566,7 +597,6 @@
{
struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
struct mmc *mmc = &pdata->mmc;
- struct meson_host *host = dev_get_priv(dev);
int err = 0, ret = 0;
struct mmc_cmd cmd = {0};
struct mmc_cmd stop = {0};
@@ -594,7 +624,7 @@
pr_debug("%s: send calibration read blocks error %d cnt = %d\n",
mmc->cfg->name, err, cnt);
if (cnt > 1 || err) {
- ret = meson_dm_mmc_send_cmd(mmc, &stop, NULL);
+ ret = meson_dm_mmc_send_cmd(dev, &stop, NULL);
if (ret)
pr_debug("%s: send calibration stop blocks error %d\n",
mmc->cfg->name, ret);
@@ -609,7 +639,6 @@
struct meson_mmc_platdata *pdata = dev_get_platdata(dev);
struct meson_host *host = dev_get_priv(dev);
struct mmc *mmc = &pdata->mmc;
- u32 vctrl = meson_read(mmc, MESON_SD_EMMC_CFG);
u32 tuning_err = 0, start_blk = CALI_PATTERN_ADDR;
int cmd_err = 0, n, nmatch;
@@ -625,7 +654,7 @@
if (!tuning_err) {
nmatch++;
} else {
- pr_err("Tuning transfer error: nmatch=%d tuning_err:0x%x\n",
+ pr_debug("Tuning transfer error: nmatch=%d tuning_err:0x%x\n",
nmatch, tuning_err);
break;
}
@@ -701,25 +730,31 @@
struct mmc *mmc = &pdata->mmc;
u32 clk_src, clock;
u32 vclk = 0, clk_div = 0, adj = 0, dly = 0, d1_dly, old_dly;
- int err = 0, ret = 0, adj_delay = 0;
+ int ret = 0, adj_delay = 0;
int tuning_num = 0;
#ifdef MMC_HS200_MODE
int pre_status = 0;
int start = 0;
#endif
- int n, nmatch;
+ int nmatch;
int wrap_win_start = -1, wrap_win_size = 0;
int best_win_start = -1, best_win_size = -1;
int curr_win_start = -1, curr_win_size = 0;
u8 rx_tuning_result[25] = { 0 };
+ if (opcode == MMC_SD_HS_TUNING) {
+ meson_write(mmc, 0x2000, MESON_SD_EMMC_ADJUST);
+ return 0;
+ }
+
if (host->blk_test == NULL)
return -EINVAL;
+ printf("%s: tuning start:\n", mmc->cfg->name);
meson_write(mmc, 0, MESON_SD_EMMC_ADJUST);
old_dly = meson_read(mmc, MESON_SD_EMMC_DELAY1);
d1_dly = (old_dly & DLY_D1_MASK) >> Dly_d1;
- printf("Data 1 aligned delay is %d\n", d1_dly);
+ pr_debug("Data 1 aligned delay is %d\n", d1_dly);
tuning:
wrap_win_start = -1;
@@ -736,7 +771,7 @@
else
clk_src = 1000000000;
clock = (clk_src / clk_div);
- printf("%s: clk %d tuning start:\n", mmc->cfg->name, clock);
+ pr_debug("%s: clk %d tuning start:\n", mmc->cfg->name, clock);
host->is_tuning = 1;
for (adj_delay = 0; adj_delay < clk_div; adj_delay++) {
@@ -761,7 +796,7 @@
curr_win_start = adj_delay;
curr_win_size++;
- printf("%s: rx_tuning_result[%d] = %d\n",
+ pr_debug("%s: rx_tuning_result[%d] = %d\n",
mmc->cfg->name, adj_delay, nmatch);
} else {
if (curr_win_start >= 0) {
@@ -923,39 +958,54 @@
if (ret)
return ret;
+ host->src_clk = dev_read_u32_default(dev, "source-clock", 0);
+
dev->name = dev_read_string(dev, "pinname");
if (dev_read_bool(dev, "non-removable"))
host->is_in = 1;
- if (!strcmp(dev->name, "sd")) {
+ dev_read_u32(dev, "card_type", &host->card_type);
+ if (aml_card_type_non_sdio(host)) {
ret = gpio_request_by_name(dev,
- "cd-detect", 0, &host->gpio_cd, GPIOD_IS_IN);
+ "cd-gpios", 0, &host->gpio_cd, GPIOD_IS_IN);
if (ret)
return ret;
}
- if (!strcmp(dev->name, "emmc")) {
+ if (aml_card_type_mmc(host)) {
ret = gpio_request_by_name(dev,
- "hw_reset", 0, &host->gpio_reset, GPIOD_IS_OUT);
+ "hw_reset", 0, &host->gpio_reset,
+ GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
if (ret)
return ret;
- dm_gpio_set_value(&host->gpio_reset, 1);
}
uclass_get_device_by_name(UCLASS_CLK, "amlogic,g12a-clkc", &clk_udevice);
- clk_get_by_name(dev, "core", &host->core);
- clk_get_by_name(dev, "clkin0", &host->xtal);
- clk_get_by_name(dev, "clkin1", &host->div2);
+ clk_get_by_name(dev, "clkin", &host->div2);
+ clk_get_by_name(dev, "xtal", &host->xtal);
clk_get_by_name(dev, "mux", &host->mux);
clk_get_by_name(dev, "div", &host->div);
clk_get_by_name(dev, "gate", &host->gate);
- clk_enable(&host->core);
+ //clk_enable(&host->core);
clk_enable(&host->gate);
return 0;
}
+/*void mmc_set_source_clock(struct udevice *dev)
+{
+ struct meson_host *host = dev_get_priv(dev);
+ unsigned long rate;
+
+ clk_set_rate(&host->div, 1000000000);
+ clk_disable(&host->xtal);
+ clk_enable(&host->gate);
+
+ printf("sd_emmc_clk_ctrl:0x%x\n", readl(((0x0038<<2) + 0xfe000800)));
+ printf("sd_emmc_clk_ctrl1:0x%x\n", readl(((0x0048<<2) + 0xfe000800)));
+}*/
+
static int meson_mmc_probe(struct udevice *dev)
{
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
@@ -989,6 +1039,8 @@
mmc->priv = pdata;
upriv->mmc = mmc;
+ //mmc_set_source_clock(dev);
+
mmc_set_clock(mmc, cfg->f_min, false);
/* reset all status bits */
@@ -1001,12 +1053,24 @@
val = meson_read(mmc, MESON_SD_EMMC_CFG);
val &= ~CFG_SDCLK_ALWAYS_ON;
val |= CFG_AUTO_CLK;
+
+ /* 512 bytes block length */
+ val &= ~CFG_BL_LEN_MASK;
+ val |= CFG_BL_LEN_512;
+
+ /* Response timeout 256 clk */
+ val &= ~CFG_RESP_TIMEOUT_MASK;
+ val |= CFG_RESP_TIMEOUT_256;
+
+ /* Command-command gap 16 clk */
+ val &= ~CFG_RC_CC_MASK;
+ val |= CFG_RC_CC_16;
meson_write(mmc, val, MESON_SD_EMMC_CFG);
- pr_info("%s: probe success!\n", mmc->cfg->name);
+ printf("[%s]%s: Controller probe success!\n", __func__, mmc->cfg->name);
return 0;
err:
- pr_err("%s: probe fail, ret = %d!\n", mmc->cfg->name, ret);
+ pr_err("[%s]%s: probe fail, ret = %d!\n", __func__, mmc->cfg->name, ret);
if (host->blk_test)
free(host->blk_test);
if (host->desc_buf)
diff --git a/drivers/mmc/mmc-uclass.c b/drivers/mmc/mmc-uclass.c
index 5626806..5ee3b4d 100644
--- a/drivers/mmc/mmc-uclass.c
+++ b/drivers/mmc/mmc-uclass.c
@@ -305,7 +305,10 @@
ret = dev_read_alias_seq(dev, &devnum);
debug("%s: alias ret=%d, devnum=%d\n", __func__, ret, devnum);
#endif
-
+ if (!strcmp(dev->name, "emmc"))
+ devnum = 1;
+ else
+ devnum = 0;
ret = blk_create_devicef(dev, "mmc_blk", "blk", IF_TYPE_MMC,
devnum, 512, 0, &bdev);
if (ret) {
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index a2bd7f7..009b774 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/mmc.c
@@ -23,9 +23,18 @@
#include <emmc_partitions.h>
#include <partition_table.h>
#include <amlogic/storage.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/sd_emmc.h>
-static int amlmmc_init = 0;
+#define stamp_after(a, b) ((int)(b) - (int)(a) < 0)
+#define KEY_BACKUP
+
+struct aml_pattern aml_pattern_table[] = {
+ AML_PATTERN_ELEMENT(MMC_PATTERN_NAME, CALI_PATTERN),
+ AML_PATTERN_ELEMENT(MMC_MAGIC_NAME, MAGIC_PATTERN),
+ AML_PATTERN_ELEMENT(MMC_RANDOM_NAME, RANDOM_PATTERN),
+};
static int mmc_set_signal_voltage(struct mmc *mmc, uint signal_voltage);
static int mmc_power_cycle(struct mmc *mmc);
#if !CONFIG_IS_ENABLED(MMC_TINY)
@@ -33,28 +42,38 @@
#endif
extern int emmc_probe(uint32_t init_flag);
-int amlmmc_is_inited(void) {
- return amlmmc_init;
-}
+
+#ifdef KEY_BACKUP
+static struct aml_key_info key_infos[2] = { {0, 0, 0}, {0, 0, 0} };
+#endif
+
bool emmckey_is_access_range_legal (struct mmc *mmc, ulong start, lbaint_t blkcnt) {
ulong key_start_blk, key_end_blk;
u64 key_glb_offset;
struct partitions * part = NULL;
struct virtual_partition *vpart = NULL;
+#ifdef KEY_BACKUP
+ int cpy = KEY_COPIES;
+#endif
if (IS_MMC(mmc)) {
vpart = aml_get_virtual_partition_by_name(MMC_KEY_NAME);
part = aml_get_partition_by_name(MMC_RESERVED_NAME);
key_glb_offset = part->offset + vpart->offset;
key_start_blk = (key_glb_offset / MMC_BLOCK_SIZE);
+#ifdef KEY_BACKUP
+ key_end_blk = ((key_glb_offset + vpart->size * cpy) / MMC_BLOCK_SIZE - 1) + 2;
+#else
key_end_blk = ((key_glb_offset + vpart->size) / MMC_BLOCK_SIZE - 1);
+#endif
+
if (!(info_disprotect & DISPROTECT_KEY)) {
if ((key_start_blk <= (start + blkcnt -1))
&& (key_end_blk >= start)
&& (blkcnt != start)) {
- pr_info("%s, keys %ld, keye %ld, start %ld, blkcnt %ld\n",
+ printf("%s, keys %ld, keye %ld, start %ld, blkcnt %ld\n",
mmc->cfg->name, key_start_blk,
key_end_blk, start, blkcnt);
- pr_err("Emmckey: Access range is illegal!\n");
+ pr_err("eMMCkey: Access range is illegal!\n");
return 0;
}
}
@@ -62,6 +81,21 @@
return 1;
}
+int emmc_boot_chk(struct mmc *mmc)
+{
+ u32 val = 0;
+
+ if (strcmp(mmc->dev->name, "emmc"))
+ return 0;
+
+ val = readl(SEC_AO_SEC_GP_CFG0);
+ pr_info("SEC_AO_SEC_GP_CFG0 = %x\n", val);
+ if ((val & 0xf) == 0x1)
+ return 1;
+
+ return 0;
+}
+
#if CONFIG_IS_ENABLED(MMC_TINY)
static struct mmc mmc_static;
struct mmc *find_mmc_device(int dev_num)
@@ -966,46 +1000,10 @@
return 0;
}
-#if CONFIG_IS_ENABLED(MMC_HS200_SUPPORT)
-static int mmc_boot_part_access_chk(struct mmc *mmc, unsigned int part_num)
-{
- int forbidden = 0;
- bool change = false;
-
- if (part_num & PART_ACCESS_MASK)
- forbidden = MMC_CAP(MMC_HS_200);
-
- if (MMC_CAP(mmc->selected_mode) & forbidden) {
- pr_debug("selected mode (%s) is forbidden for part %d\n",
- mmc_mode_name(mmc->selected_mode), part_num);
- change = true;
- } else if (mmc->selected_mode != mmc->best_mode) {
- pr_debug("selected mode is not optimal\n");
- change = true;
- }
-
- if (change)
- return mmc_select_mode_and_width(mmc,
- mmc->card_caps & ~forbidden);
-
- return 0;
-}
-#else
-static inline int mmc_boot_part_access_chk(struct mmc *mmc,
- unsigned int part_num)
-{
- return 0;
-}
-#endif
-
int mmc_switch_part(struct mmc *mmc, unsigned int part_num)
{
int ret;
- ret = mmc_boot_part_access_chk(mmc, part_num);
- if (ret)
- return ret;
-
ret = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_PART_CONF,
(mmc->part_config & ~PART_ACCESS_MASK)
| (part_num & PART_ACCESS_MASK));
@@ -1697,6 +1695,9 @@
{
.mode = SD_HS,
.widths = MMC_MODE_4BIT | MMC_MODE_1BIT,
+#ifdef MMC_SUPPORTS_TUNING
+ .tuning = MMC_SD_HS_TUNING
+#endif
},
#if CONFIG_IS_ENABLED(MMC_UHS_SUPPORT)
{
@@ -1902,6 +1903,9 @@
{
.mode = MMC_HS_52,
.widths = MMC_MODE_8BIT | MMC_MODE_4BIT | MMC_MODE_1BIT,
+#ifdef MMC_SUPPORTS_TUNING
+ .tuning = MMC_SD_HS_TUNING
+#endif
},
{
.mode = MMC_HS,
@@ -2008,8 +2012,6 @@
return -ENOTSUPP;
}
- mmc_set_clock(mmc, mmc->legacy_speed, MMC_CLK_ENABLE);
-
for_each_mmc_mode_by_pref(card_caps, mwt) {
for_each_supported_width(card_caps & mwt->widths,
mmc_is_mode_ddr(mwt->mode), ecbw) {
@@ -2024,10 +2026,6 @@
if (err)
continue;
- err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_HS_TIMING, 1);
- if (err)
- goto error;
-
/* configure the bus width (card + host) */
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL,
EXT_CSD_BUS_WIDTH,
@@ -2326,52 +2324,82 @@
}
#endif
- /* Put the Card in Identify Mode */
- cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
- MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
- cmd.resp_type = MMC_RSP_R2;
- cmd.cmdarg = 0;
+#ifdef CONFIG_MMC_FBOOT
+ if (emmc_boot_chk(mmc)) {
+ mmc_switch_part(mmc, 0);
- err = mmc_send_cmd(mmc, &cmd, NULL);
-
-#ifdef CONFIG_MMC_QUIRKS
- if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
- int retries = 4;
- /*
- * It has been seen that SEND_CID may fail on the first
- * attempt, let's try a few more time
- */
- do {
+ /* disSelect the card, and put it into detect Mode */
+ if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
+ cmd.cmdidx = MMC_CMD_SELECT_CARD;
+ cmd.resp_type = MMC_RSP_NONE;
+ cmd.cmdarg = 0;
err = mmc_send_cmd(mmc, &cmd, NULL);
- if (!err)
- break;
- } while (retries--);
- }
-#endif
- if (err)
- return err;
+ if (err)
+ return err;
+ }
- memcpy(mmc->cid, cmd.response, 16);
-
- /*
- * For MMC cards, set the Relative Address.
- * For SD cards, get the Relatvie Address.
- * This also puts the cards into Standby State
- */
- if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
- cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
+ /* Put the Card in Identify Mode */
+ cmd.cmdidx = MMC_CMD_SEND_CID;
+ cmd.resp_type = MMC_RSP_R2;
cmd.cmdarg = mmc->rca << 16;
- cmd.resp_type = MMC_RSP_R6;
err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (err)
+ return err;
+
+ memcpy(mmc->cid, cmd.response, 16);
+ } else {
+#endif
+ /* Put the Card in Identify Mode */
+ cmd.cmdidx = mmc_host_is_spi(mmc) ? MMC_CMD_SEND_CID :
+ MMC_CMD_ALL_SEND_CID; /* cmd not supported in spi */
+ cmd.resp_type = MMC_RSP_R2;
+ cmd.cmdarg = 0;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+
+#ifdef CONFIG_MMC_QUIRKS
+ if (err && (mmc->quirks & MMC_QUIRK_RETRY_SEND_CID)) {
+ int retries = 4;
+ /*
+ * It has been seen that SEND_CID may fail on the first
+ * attempt, let's try a few more time
+ */
+ do {
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+ if (!err)
+ break;
+ } while (retries--);
+ }
+#endif
if (err)
return err;
- if (IS_SD(mmc))
- mmc->rca = (cmd.response[0] >> 16) & 0xffff;
+ memcpy(mmc->cid, cmd.response, 16);
+
+ /*
+ * For MMC cards, set the Relative Address.
+ * For SD cards, get the Relatvie Address.
+ * This also puts the cards into Standby State
+ */
+ if (!mmc_host_is_spi(mmc)) { /* cmd not supported in spi */
+ cmd.cmdidx = SD_CMD_SEND_RELATIVE_ADDR;
+ cmd.cmdarg = mmc->rca << 16;
+ cmd.resp_type = MMC_RSP_R6;
+
+ err = mmc_send_cmd(mmc, &cmd, NULL);
+
+ if (err)
+ return err;
+
+ if (IS_SD(mmc))
+ mmc->rca = (cmd.response[0] >> 16) & 0xffff;
+ }
+#ifdef CONFIG_MMC_FBOOT
}
+#endif
/* Get the Card-Specific Data */
cmd.cmdidx = MMC_CMD_SEND_CSD;
@@ -2564,7 +2592,6 @@
cmd.resp_type = MMC_RSP_R7;
err = mmc_send_cmd(mmc, &cmd, NULL);
-
if (err)
return err;
@@ -2727,7 +2754,6 @@
/* Reset the Card */
err = mmc_go_idle(mmc);
-
if (err)
return err;
@@ -2789,7 +2815,14 @@
return -ENOMEDIUM;
}
- err = mmc_get_op_cond(mmc);
+#ifdef CONFIG_MMC_FBOOT
+ if (emmc_boot_chk(mmc)) {
+ mmc->high_capacity = 1;
+ mmc->rca = 1;
+ mmc->version = MMC_VERSION_UNKNOWN;
+ } else
+#endif
+ err = mmc_get_op_cond(mmc);
if (!err)
mmc->init_in_progress = 1;
@@ -2814,47 +2847,68 @@
return err;
}
-static int enable_vendor_erase(struct mmc *mmc)
+void mmc_write_cali_mattern(void *addr, struct aml_pattern *table)
{
- int ret = 0;
- u8 ext_csd[512] = {0};
-
- /*read ext_csd[16]*/
- ret = mmc_get_ext_csd(mmc, ext_csd);
- if (!ret)
- {
- /*0x39(hex) --> 57(dec)*/
- if ((0x39) == ext_csd[16])
- return ret;
+ int i = 0;
+ unsigned int s = 10;
+ u32 *mattern = (u32 *)addr;
+ struct virtual_partition *vpart =
+ aml_get_virtual_partition_by_name(table->name);
+ for (i = 0;i < (vpart->size)/4 - 1;i++) {
+ if (!strcmp(table->name, "random"))
+ mattern[i] = rand_r(&s);
+ else
+ mattern[i] = table->pattern;
}
+ mattern[i] = crc32(0, (u8 *)addr, (vpart->size - 4));
+ return;
+}
- /*ext_csd[16] register description
- * * Bit[7:6]: Reserved
- * * Bit[5:4]: Configure Secure Removal Type
- * * 0x0: information removed by an erase of the physical memory
- * * 0x1: information removed by an overwriting the addressed locations
- * * with a character followed by an erase
- * * 0x2: information removed by an overwriting the addressed locations with
- * * a character, its complement, then a random character
- * * 0x3: information removed using a vendor defined
- * * Bit[3:0]: Supported Secure Removal Type
- * * Bit 0: information removed by an erase of the physical memory
- * * Bit 1: information removed by an overwriting the addressed locations
- * * with a character followed by an erase
- * * Bit 2: information removed by an overwriting the addressed locations
- * * with a character, its complement, then a random character
- * * Bit 3: information removed using a vendor defined
- */
- /*set ext_csd[16] Bit[5:4] to 0x3*/
- /*Bit[3:0} default value is 0x9*/
- /*ext_csd[16] setting property is OTP*/
- /*0x39(hex) --> 57(dec)*/
- return mmc_set_ext_csd(mmc, 16, 57);
+int mmc_pattern_check(struct mmc *mmc, struct aml_pattern *table)
+{
+ void *addr = NULL;
+ u64 cnt = 0, n = 0, blk = 0;
+ u32 *buf = NULL;
+ u32 crc32_s = 0;
+ struct partitions *part = NULL;
+ struct virtual_partition *vpart = NULL;
+
+ vpart = aml_get_virtual_partition_by_name(table->name);
+
+ addr = (void *)malloc(vpart->size);
+ if (!addr) {
+ printf("%s malloc failed\n", table->name);
+ return 1;
+ }
+ part = aml_get_partition_by_name(MMC_RESERVED_NAME);
+ blk = (part->offset + vpart->offset) / mmc->read_bl_len;
+ cnt = vpart->size / mmc->read_bl_len;
+ n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
+ if (n != cnt) {
+ printf("read pattern failed\n");
+ free(addr);
+ return 1;
+ } else {
+ buf = (u32 *)addr;
+ crc32_s = crc32(0, (u8 *)addr, (vpart->size - 4));
+ if (crc32_s != buf[vpart->size/4 - 1]) {
+ printf("check %s failed,need to write\n",
+ table->name);
+ mmc_write_cali_mattern(addr, table);
+ n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr);
+ printf("several 0x%x pattern blocks write %s\n",
+ table->pattern, (n == cnt) ? "OK" : "ERROR");
+ }
+ printf("crc32_s:0x%x == storage crc_pattern:0x%x!!!\n",
+ crc32_s, buf[vpart->size/4 - 1]);
+ }
+ free(addr);
+ return (n == cnt) ? 0 : 1;
}
int mmc_init(struct mmc *mmc)
{
- int err = 0;
+ int err = 0, i;
__maybe_unused ulong start;
#if CONFIG_IS_ENABLED(DM_MMC)
struct mmc_uclass_priv *upriv = dev_get_uclass_priv(mmc->dev);
@@ -2877,26 +2931,14 @@
if (IS_MMC(mmc)) {
if (!is_partition_checked) {
if (mmc_device_init(mmc) == 0) {
- is_partition_checked = true;
- pr_info("eMMC/TSD partition table have been checked OK!\n");
+ is_partition_checked = true;
+ printf("eMMC/TSD partition table have been checked OK!\n");
+ for (i = 0; i < ARRAY_SIZE(aml_pattern_table); i++)
+ mmc_pattern_check(mmc, &aml_pattern_table[i]);
}
}
- err = emmc_probe(0xff);
- /*For TOSHIBA(MID:0x11) emmc*/
- if ((0x11) == (mmc->cid[0] >> 24)) {
- if (enable_vendor_erase(mmc))
- pr_err("%s:%d TOSHIBA emmc enable vendor erase fail!\n", __func__, __LINE__);
- }
}
info_disprotect &= ~DISPROTECT_KEY;
-
- /*mmc init flag*/
- if (!err) {
- amlmmc_init = 1;
- } else {
- amlmmc_init = 0;
- }
-
return err;
}
@@ -2910,14 +2952,14 @@
if (!mmc || !blkcnt)
return 0;
- pr_info("mmc ffu start = %lx, cnt = %lx, addr = %p\n", start, blkcnt, src);
+ printf("mmc ffu start = %lx, cnt = %lx, addr = %p\n", start, blkcnt, src);
cmd.cmdidx = MMC_CMD_SET_BLOCK_COUNT;
cmd.cmdarg = blkcnt & 0xFFFF;
cmd.resp_type = MMC_RSP_R1;
ret = mmc_send_cmd(mmc, &cmd, NULL);
if (ret) {
- pr_err("mmc set blkcnt failed\n");
+ printf("mmc set blkcnt failed\n");
return 0;
}
@@ -2932,7 +2974,7 @@
ret = mmc_send_cmd(mmc, &cmd, &data);
if (ret) {
- pr_err("mmc write failed\n");
+ printf("mmc write failed\n");
return 0;
}
@@ -2953,14 +2995,16 @@
if (!mmc)
return -ENODEV;
- pr_info("ffu update start\n");
+ printf("ffu update start\n");
/* check Manufacturer MID */
if ((mmc->cid[0] >> 24) == SAMSUNG_MID) {
ffu_addr = SAMSUNG_FFU_ADDR;
} else if ((mmc->cid[0] >> 24) == KINGSTON_MID) {
ffu_addr = KINGSTON_FFU_ADDR;
+ } else if ((mmc->cid[0] >> 24) == BIWIN_MID) {
+ ffu_addr = BIWIN_FFU_ADDR;
} else {
- pr_err("FFU update for this manufacturer not support yet\n");
+ printf("FFU update for this manufacturer not support yet\n");
return -1;
}
@@ -2976,23 +3020,28 @@
supported_modes = ext_csd_ffu[EXT_CSD_SUPPORTED_MODES] & 0x1;
fw_cfg = ext_csd_ffu[EXT_CSD_FW_CFG] & 0x1;
- for (i = 0; i < 8; i++)
- fw_ver |= (ext_csd_ffu[EXT_CSD_FW_VERSION + i] << (i * 8));
- pr_info("old fw_ver = %llx\n", fw_ver);
+ for (i = 0; i < 8; i++) {
+ fw_ver |= ext_csd_ffu[EXT_CSD_FW_VERSION + 7 - i];
+ if (i < 7)
+ fw_ver <<= 8;
+ }
+ if ((mmc->cid[0] >> 24) == BIWIN_MID)
+ fw_ver = ((fw_ver >> 16) & 0xffffffff);
+ printf("old fw_ver = %llx\n", fw_ver);
if (!supported_modes || fw_cfg || (fw_ver >= ffu_ver))
return -1;
/* Set FFU Mode */
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_MODE_CFG, 1);
if (err) {
- pr_err("Failed: set FFU mode\n");
+ printf("Failed: set FFU mode\n");
return err;
}
/* Write patch file at one write command */
n = mmc_ffu_write(dev, ffu_addr, cnt, addr);
if (n != cnt) {
- pr_err("target is %llx block, but only %llx block has been write\n", cnt, n);
+ printf("target is %llx block, but only %llx block has been write\n", cnt, n);
return -1;
}
@@ -3001,9 +3050,14 @@
if (err)
return err;
- for (i = 0; i < 8; i++)
- fw_ver |= (ext_csd_ffu[EXT_CSD_FW_VERSION + i] << (i * 8));
- pr_info("new fw_ver = %llx\n", fw_ver);
+ for (i = 0; i < 8; i++) {
+ fw_ver |= ext_csd_ffu[EXT_CSD_FW_VERSION + 7 - i];
+ if (i < 7)
+ fw_ver <<= 8;
+ }
+ if ((mmc->cid[0] >> 24) == BIWIN_MID)
+ fw_ver = ((fw_ver >> 16) & 0xffffffff);
+ printf("new fw_ver = %llx\n", fw_ver);
if ((mmc->cid[0] >> 24) == SAMSUNG_MID) {
/* Set Normal Mode */
err = mmc_switch(mmc, EXT_CSD_CMD_SET_NORMAL, EXT_CSD_MODE_CFG, 0);
@@ -3029,13 +3083,18 @@
return err;
ffu_status = ext_csd_ffu[EXT_CSD_FFU_STATUS] & 0xff;
fw_ver = 0;
- for (i = 0; i < 8; i++)
- fw_ver |= (ext_csd_ffu[EXT_CSD_FW_VERSION + i] << (i * 8));
- pr_info("new fw_ver = %llx\n", fw_ver);
+ for (i = 0; i < 8; i++) {
+ fw_ver |= ext_csd_ffu[EXT_CSD_FW_VERSION + 7 - i];
+ if (i < 7)
+ fw_ver <<= 8;
+ }
+ if ((mmc->cid[0] >> 24) == BIWIN_MID)
+ fw_ver = ((fw_ver >> 16) & 0xffffffff);
+ printf("new fw_ver = %llx\n", fw_ver);
if (ffu_status || (fw_ver != ffu_ver))
return ffu_status;
- pr_info("FFU update ok!\n");
+ printf("FFU update ok!\n");
return 0;
}
@@ -3119,7 +3178,7 @@
return ret;
#ifndef CONFIG_SPL_BUILD
- print_mmc_devices(',');
+ //print_mmc_devices(',');
#endif
mmc_do_preinit();
@@ -3163,37 +3222,6 @@
extern unsigned long blk_dwrite(struct blk_desc *block_dev, lbaint_t start,
lbaint_t blkcnt, const void *buffer);
-int mmc_key_write(unsigned char *buf, unsigned int size, uint32_t *actual_lenth)
-{
- ulong start, start_blk, blkcnt, ret;
- unsigned char * temp_buf = buf;
- int i = 2, dev = EMMC_DTB_DEV;
- struct partitions * part = NULL;
- struct mmc *mmc;
- struct virtual_partition *vpart = NULL;
- vpart = aml_get_virtual_partition_by_name(MMC_KEY_NAME);
- part = aml_get_partition_by_name(MMC_RESERVED_NAME);
-
- mmc = find_mmc_device(dev);
-
- start = part->offset + vpart->offset;
- start_blk = (start / MMC_BLOCK_SIZE);
- blkcnt = (size / MMC_BLOCK_SIZE);
- info_disprotect |= DISPROTECT_KEY;
- do {
- ret = blk_dwrite(mmc_get_blk_desc(mmc), start_blk, blkcnt, temp_buf);
- if (ret != blkcnt) {
- pr_err("[%s] %d, mmc_bwrite error\n",
- __func__, __LINE__);
- return 1;
- }
- start_blk += vpart->size / MMC_BLOCK_SIZE;
- } while (--i);
- info_disprotect &= ~DISPROTECT_KEY;
- return 0;
-}
-
-
extern unsigned long blk_derase(struct blk_desc *block_dev, lbaint_t start,
@@ -3212,7 +3240,11 @@
mmc = find_mmc_device(dev);
start = part->offset + vpart->offset;
start_blk = (start / MMC_BLOCK_SIZE);
+#ifdef KEY_BACKUP
+ blkcnt = (vpart->size / MMC_BLOCK_SIZE) * 2 + 2;//key and backup key
+#else
blkcnt = (vpart->size / MMC_BLOCK_SIZE) * 2;//key and backup key
+#endif
info_disprotect |= DISPROTECT_KEY;
ret = blk_derase(mmc_get_blk_desc(mmc), start_blk, blkcnt);
info_disprotect &= ~DISPROTECT_KEY;
@@ -3224,32 +3256,407 @@
return 0;
}
+#ifdef KEY_BACKUP
+/* unifykey backup distributioin */
+
+/*--------------------------------------------------------
+ * offset | 0x12020 | 0x12220 | 0x12420 | 0x12421 |
+ *--------------------------------------------------------
+ * size | 200 block | 200 block | 1 block | 1 block |
+ *--------------------------------------------------------
+ *content | key1 | key2 | checksum1 | checksum2 |
+ *--------------------------------------------------------
+ */
+static u64 _calc_key_checksum(void *addr, int size)
+{
+ int i = 0;
+ u32 *buffer;
+ u64 checksum = 0;
+
+ if ((u64)addr % 4 != 0)
+ BUG();
+
+ buffer = (u32 *)addr;
+ size = size >> 2;
+ while (i < size)
+ checksum += buffer[i++];
+
+ return checksum;
+}
+
+static int _key_read(struct mmc *mmc, u64 blk, u64 cnt, void * addr)
+{
+ int dev = EMMC_DTB_DEV;
+ u64 n;
+ n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, addr);
+ if (n != cnt) {
+ printf("%s: dev # %d, block # %#llx, count # %#llx ERROR!\n",
+ __func__, dev, blk, cnt);
+ }
+
+ return (n != cnt);
+}
+
+static int _verify_key_checksum(struct mmc *mmc, void *addr, int cpy)
+{
+ u64 checksum;
+ int ret = 0;
+ u64 blk, key_glb_offset;
+ struct partitions * part = NULL;
+ struct virtual_partition *vpart = NULL;
+ char checksum_info[512] = {0};
+
+ vpart = aml_get_virtual_partition_by_name(MMC_KEY_NAME);
+ part = aml_get_partition_by_name(MMC_RESERVED_NAME);
+ key_glb_offset = part->offset + vpart->offset;
+
+ blk = (key_glb_offset + 2 * (vpart->size)) / MMC_BLOCK_SIZE + cpy;
+ ret = _key_read(mmc, blk, 1, (void *)checksum_info);
+ if (ret)
+ return -1;
+
+ memcpy(&key_infos[cpy], checksum_info, sizeof(struct aml_key_info));
+
+ checksum = _calc_key_checksum(addr, vpart->size);
+ printf("calc %llx, store %llx\n", checksum, key_infos[cpy].checksum);
+
+ return !(checksum == key_infos[cpy].checksum);
+}
+
+static int update_key_info(struct mmc *mmc, unsigned char *addr)
+{
+ int ret = 0;
+ u64 blk, cnt, key_glb_offset;
+ int cpy = 1;
+ struct partitions * part = NULL;
+ struct virtual_partition *vpart = NULL;
+ int valid_flag = 0;
+
+ vpart = aml_get_virtual_partition_by_name(MMC_KEY_NAME);
+ part = aml_get_partition_by_name(MMC_RESERVED_NAME);
+ key_glb_offset = part->offset + vpart->offset;
+
+ while (cpy >= 0) {
+ blk = (key_glb_offset + cpy * (vpart->size)) / MMC_BLOCK_SIZE;
+ cnt = vpart->size / mmc->read_bl_len;
+ ret = _key_read(mmc, blk, cnt, addr);
+ if (ret) {
+ printf("%s: block # %#llx, cnt # %#llx ERROR!\n",
+ __func__, blk, cnt);
+ return -1;
+ }
+
+ ret = _verify_key_checksum(mmc, addr, cpy);
+ if (!ret && key_infos[cpy].magic != 0)
+ valid_flag += cpy + 1;
+ else
+ printf("cpy %d is not valid\n", cpy);
+ cpy--;
+ }
+
+ if (key_infos[0].stamp > key_infos[1].stamp)
+ mmc->key_stamp = key_infos[0].stamp;
+ else
+ mmc->key_stamp = key_infos[1].stamp;
+
+ return valid_flag;
+}
+
+static int _key_write(struct mmc *mmc, u64 blk, u64 cnt, void *addr)
+{
+ int dev = EMMC_KEY_DEV;
+ u32 n;
+ n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, addr);
+ if (n != cnt) {
+ printf("%s: dev # %d, block # %#llx, count # %#llx ERROR!\n",
+ __func__, dev, blk, cnt);
+ }
+
+ return (n != cnt);
+}
+
+static int write_invalid_key(struct mmc *mmc, void *addr, int valid_flag)
+{
+ u64 blk, cnt, key_glb_offset;
+ int ret;
+ struct partitions * part = NULL;
+ struct virtual_partition *vpart = NULL;
+ char checksum_info[512] = {0};
+
+ if (valid_flag > 2 || valid_flag < 1)
+ return 1;
+
+ vpart = aml_get_virtual_partition_by_name(MMC_KEY_NAME);
+ part = aml_get_partition_by_name(MMC_RESERVED_NAME);
+ key_glb_offset = part->offset + vpart->offset;
+
+ blk = (key_glb_offset + (valid_flag - 1) * (vpart->size)) / MMC_BLOCK_SIZE;
+ cnt = vpart->size / mmc->read_bl_len;
+
+ if (_key_read(mmc, blk, cnt, addr)) {
+ printf("%s: block # %#llx,cnt # %#llx ERROR!\n",
+ __func__, blk, cnt);
+ ret = -2;
+ }
+ /* fixme, update the invalid one - key1 */
+ blk = (key_glb_offset + (valid_flag % 2) * vpart->size) / MMC_BLOCK_SIZE;
+ if (_key_write(mmc, blk, cnt, addr)) {
+ printf("%s: block # %#llx,cnt # %#llx ERROR!\n",
+ __func__, blk, cnt);
+ ret = -4;
+ }
+
+ memcpy(checksum_info, &key_infos[valid_flag - 1], sizeof(struct aml_key_info));
+ blk = (key_glb_offset + 2 * (vpart->size)) / MMC_BLOCK_SIZE + valid_flag % 2;
+ if (_key_write(mmc, blk, 1, checksum_info)) {
+ printf("%s: block # %#llx,cnt # %#llx ERROR!\n",
+ __func__, blk, cnt);
+ ret = -4;
+ }
+
+ return ret;
+}
+
+static int update_invalid_key(struct mmc *mmc, void *addr, int valid_flag)
+{
+ int ret = 0, dev = EMMC_KEY_DEV;
+ u64 blk, cnt, key_glb_offset;
+ struct partitions * part = NULL;
+ struct virtual_partition *vpart = NULL;
+ char checksum_info[512] = {0};
+
+ vpart = aml_get_virtual_partition_by_name(MMC_KEY_NAME);
+ part = aml_get_partition_by_name(MMC_RESERVED_NAME);
+ key_glb_offset = part->offset + vpart->offset;
+ cnt = vpart->size / mmc->read_bl_len;
+
+ if (valid_flag == 2) {
+ printf("update key1");
+ ret = write_invalid_key(mmc, addr, valid_flag);
+ if (ret)
+ ret = -2;
+ } else {
+ printf("update key2");
+ blk = (key_glb_offset + vpart->size) / MMC_BLOCK_SIZE;
+ if (_key_write(mmc, blk, cnt, addr)) {
+ printf("%s: dev # %d, block # %#llx,cnt # %#llx ERROR!\n",
+ __func__, dev, blk, cnt);
+ ret = -2;
+ }
+ memcpy(checksum_info, &key_infos[valid_flag - 1],
+ sizeof(struct aml_key_info));
+ blk = (key_glb_offset + 2 * (vpart->size)) / MMC_BLOCK_SIZE + valid_flag % 2;
+ if (_key_write(mmc, blk, 1, checksum_info)) {
+ printf("%s: block # %#llx,cnt # %#llx ERROR!\n",
+ __func__, blk, cnt);
+ ret = -4;
+ }
+ }
+ return ret;
+}
+
+int update_old_key(struct mmc *mmc, void *addr)
+{
+ int ret = 0;
+ int valid_flag;
+
+ if (stamp_after(key_infos[1].stamp, key_infos[0].stamp)) {
+ memcpy(&key_infos[1], &key_infos[0], sizeof(struct aml_key_info));
+ valid_flag = 2;
+ } else if (stamp_after(key_infos[0].stamp, key_infos[1].stamp)) {
+ memcpy(&key_infos[0], &key_infos[1], sizeof(struct aml_key_info));
+ valid_flag = 1;
+ } else {
+ printf("do nothing\n");
+ return ret;
+ }
+
+ ret = write_invalid_key(mmc, addr, valid_flag);
+ /*update key*/
+ if (ret)
+ ret = -3;
+ mmc->key_stamp = key_infos[0].stamp;
+ return ret;
+}
+
+static struct mmc *_rsv_init(void)
+{
+ struct mmc *mmc = find_mmc_device(EMMC_KEY_DEV);
+ if (!mmc) {
+ printf("not find mmc\n");
+ return NULL;
+ }
+
+ if (mmc_init(mmc)) {
+ printf("mmc init failed\n");
+ return NULL;
+ }
+
+ return mmc;
+}
+
+static int mmc_key_write_backup(const char *name,
+ unsigned char *addr, unsigned int size)
+{
+ int ret = 0;
+ u64 blk, cnt, key_glb_offset;
+ int cpy;
+ struct mmc * mmc;
+ struct partitions * part = NULL;
+ struct virtual_partition *vpart = NULL;
+ char checksum_info[512] = {0};
+
+ vpart = aml_get_virtual_partition_by_name(MMC_KEY_NAME);
+ part = aml_get_partition_by_name(MMC_RESERVED_NAME);
+ key_glb_offset = part->offset + vpart->offset;
+
+ mmc = _rsv_init();
+ if (mmc == NULL)
+ return -10;
+
+ key_infos[0].stamp = mmc->key_stamp + 1;
+ key_infos[0].magic = 9;
+ key_infos[0].checksum = _calc_key_checksum(addr, vpart->size);
+ printf("new stamp %d, checksum 0x%llx, magic %d\n",
+ key_infos[0].stamp, key_infos[0].checksum, key_infos[0].magic);
+
+ memcpy(checksum_info, &key_infos[0], sizeof(struct aml_key_info));
+
+ for (cpy = 0; cpy < KEY_COPIES; cpy++) {
+ blk = (key_glb_offset + cpy * (vpart->size)) / MMC_BLOCK_SIZE;
+ cnt = vpart->size / mmc->read_bl_len;
+ ret |= _key_write(mmc, blk, cnt, addr);
+
+ blk = (key_glb_offset + 2 * (vpart->size)) / MMC_BLOCK_SIZE + cpy;
+ ret |= _key_write(mmc, blk, 1, checksum_info);
+ }
+
+ if (ret) {
+ printf("%s() %d: emmc init %d\n", __func__, __LINE__, ret);
+ ret = -2;
+ }
+
+ return ret;
+}
+
+static int mmc_key_read_backup(const char *name,
+ unsigned char *addr, unsigned int size)
+{
+ int valid = 0;
+ struct mmc *mmc;
+
+ mmc = _rsv_init();
+ if (mmc == NULL)
+ return -10;
+
+ /* check valid key flag , addr save the first key content */
+ valid = update_key_info(mmc, addr);
+ switch (valid) {
+ /* none is valid, using the 1st one for compatibility*/
+ case 0:
+ goto _out;
+ break;
+ /* only first is valid, using the first update the second */
+ case 1:
+ update_invalid_key(mmc, addr, 1);
+ break;
+ /* only second is valid, using the second */
+ case 2:
+ update_invalid_key(mmc, addr, 2);
+ break;
+ case 3:
+ /*update the old key */
+ update_old_key(mmc, addr);
+ break;
+ default:
+ printf("impossble valid values.\n");
+ BUG();
+ break;
+ }
+_out:
+ return 0;
+}
+#endif
+
+int mmc_key_write(unsigned char *buf, unsigned int size, uint32_t *actual_lenth)
+{
+ ulong blkcnt, ret;
+ unsigned char * temp_buf = buf;
+#ifndef KEY_BACKUP
+ int dev = EMMC_DTB_DEV;
+ int i = 2;
+ struct mmc *mmc;
+ ulong start, start_blk;
+ struct virtual_partition *vpart = NULL;
+ vpart = aml_get_virtual_partition_by_name(MMC_KEY_NAME);
+ struct partitions * part = NULL;
+ part = aml_get_partition_by_name(MMC_RESERVED_NAME);
+
+ mmc = find_mmc_device(dev);
+ start_blk = (start / MMC_BLOCK_SIZE);
+ start = part->offset + vpart->offset;
+#endif
+ blkcnt = (size / MMC_BLOCK_SIZE);
+ info_disprotect |= DISPROTECT_KEY;
+#ifdef KEY_BACKUP
+ ret = mmc_key_write_backup(MMC_KEY_NAME, temp_buf, blkcnt);
+ if (ret != 0) {
+ pr_err("[%s] %d, mmc_bwrite error\n",
+ __func__, __LINE__);
+ return 1;
+ }
+#else
+ do {
+ ret = blk_dwrite(mmc_get_blk_desc(mmc), start_blk, blkcnt, temp_buf);
+ if (ret != blkcnt) {
+ pr_err("[%s] %d, mmc_bwrite error\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ start_blk += vpart->size / MMC_BLOCK_SIZE;
+ } while (--i);
+#endif
+ info_disprotect &= ~DISPROTECT_KEY;
+ return 0;
+}
int mmc_key_read(unsigned char *buf, unsigned int size, uint32_t *actual_lenth)
{
- ulong start, start_blk, blkcnt, ret;
- int dev = EMMC_DTB_DEV;
+ ulong blkcnt, ret;
unsigned char *temp_buf = buf;
- struct partitions * part = NULL;
+#ifndef KEY_BACKUP
struct mmc *mmc;
+ int dev = EMMC_DTB_DEV;
+ ulong start, start_blk;
+ struct partitions * part = NULL;
struct virtual_partition *vpart = NULL;
vpart = aml_get_virtual_partition_by_name(MMC_KEY_NAME);
part = aml_get_partition_by_name(MMC_RESERVED_NAME);
mmc = find_mmc_device(dev);
- *actual_lenth = 0x40000;/*key size is 256KB*/
start = part->offset + vpart->offset;
start_blk = (start / MMC_BLOCK_SIZE);
+#endif
+
+ *actual_lenth = 0x40000;/*key size is 256KB*/
blkcnt = (size / MMC_BLOCK_SIZE);
info_disprotect |= DISPROTECT_KEY;
+#ifdef KEY_BACKUP
+ ret = mmc_key_read_backup(MMC_KEY_NAME, temp_buf, blkcnt);
+ if (ret != 0) {
+ pr_err("[%s] %d, mmc_bread error\n",
+ __func__, __LINE__);
+ return 1;
+ }
+#else
ret = blk_dread(mmc_get_blk_desc(mmc), start_blk, blkcnt, temp_buf);
- info_disprotect &= ~DISPROTECT_KEY;
if (ret != blkcnt) {
pr_err("[%s] %d, mmc_bread error\n",
__func__, __LINE__);
return 1;
}
+#endif
+ info_disprotect &= ~DISPROTECT_KEY;
return 0;
}
-
diff --git a/drivers/mmc/mmc_private.h b/drivers/mmc/mmc_private.h
index d09ad34..cf2467f 100644
--- a/drivers/mmc/mmc_private.h
+++ b/drivers/mmc/mmc_private.h
@@ -9,20 +9,68 @@
#ifndef _MMC_PRIVATE_H_
#define _MMC_PRIVATE_H_
+#include <clk.h>
#include <mmc.h>
-#define SAMSUNG_MID 0x15
+#define SAMSUNG_MID 0x15
#define KINGSTON_MID 0x70
+#define BIWIN_MID 0xf4
#define SAMSUNG_FFU_ADDR 0xc7810000
#define KINGSTON_FFU_ADDR 0x0000ffff
+#define BIWIN_FFU_ADDR 0x0
#define MAX_TUNING_RETRY (4)
#define CALI_BLK_CNT (1024)
#define REFIX_BLK_CNT (100)
-#define CALI_PATTERN_ADDR (0x13800)
-#define TUNING_NUM_PER_POINT 10
+#define CALI_PATTERN_ADDR (0x13800)
+#define TUNING_NUM_PER_POINT 40
#define MMC_MAX_DESC_NUM 512
#define MAX_RESPONSE_BYTES 4
+/* unknown */
+#define CARD_TYPE_UNKNOWN 0
+/* MMC card */
+#define CARD_TYPE_MMC 1
+/* SD card */
+#define CARD_TYPE_SD 2
+/* SDIO card */
+#define CARD_TYPE_SDIO 3
+/* SD combo (IO+mem) card */
+#define CARD_TYPE_SD_COMBO 4
+/* NON sdio device (means SD/MMC card) */
+#define CARD_TYPE_NON_SDIO 5
+
+#define aml_card_type_unknown(c) ((c)->card_type == CARD_TYPE_UNKNOWN)
+#define aml_card_type_mmc(c) ((c)->card_type == CARD_TYPE_MMC)
+#define aml_card_type_sd(c) ((c)->card_type == CARD_TYPE_SD)
+#define aml_card_type_sdio(c) ((c)->card_type == CARD_TYPE_SDIO)
+#define aml_card_type_non_sdio(c) ((c)->card_type == CARD_TYPE_NON_SDIO)
+
+struct meson_host {
+ struct mmc *mmc;
+ uint is_in;
+ uint is_sduart;
+ uint is_tuning;
+ uint card_type;
+ uint src_clk;
+ struct clk core;
+ struct clk xtal;
+ struct clk div2;
+ struct clk mux;
+ struct clk div;
+ struct clk gate;
+ struct gpio_desc gpio_cd;
+ struct gpio_desc gpio_reset;
+ char *blk_test;
+ char* desc_buf;
+};
+
+struct meson_mmc_platdata {
+ struct mmc_config cfg;
+ struct mmc mmc;
+ void *regbase;
+ void *w_buf;
+};
+
extern int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd,
struct mmc_data *data);
extern int mmc_send_status(struct mmc *mmc, int timeout);
@@ -146,4 +194,5 @@
*/
int mmc_switch(struct mmc *mmc, u8 set, u8 index, u8 value);
+int emmc_boot_chk(struct mmc *mmc);
#endif /* _MMC_PRIVATE_H_ */
diff --git a/drivers/mmc/mmc_write.c b/drivers/mmc/mmc_write.c
index c53a624..1daf483 100644
--- a/drivers/mmc/mmc_write.c
+++ b/drivers/mmc/mmc_write.c
@@ -95,6 +95,7 @@
return -1;
if (blkcnt == 0) {
blkcnt = mmc->capacity/512 - (mmc->capacity/512)% mmc->erase_grp_size; // erase whole
+ blkcnt = blkcnt - start;
printf("blkcnt = %lu\n",blkcnt);
}
/*
diff --git a/drivers/mmc/storage_emmc.c b/drivers/mmc/storage_emmc.c
old mode 100755
new mode 100644
index afa79c3..a7a5188
--- a/drivers/mmc/storage_emmc.c
+++ b/drivers/mmc/storage_emmc.c
@@ -1,13 +1,17 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include <amlogic/storage.h>
#include <dm/pinctrl.h>
#include <partition_table.h>
#include <emmc_partitions.h>
-#include <asm/arch-g12a/cpu_id.h>
+#include <amlogic/cpu_id.h>
#include <asm/arch-g12a/bl31_apis.h>
#include <linux/compat.h>
#include <amlogic/aml_mmc.h>
-
+#include <linux/compat.h>
#define USER_PARTITION 0
#define BOOT0_PARTITION 1
@@ -26,7 +30,8 @@
#define BLOCK_SIZE 512
extern int find_dev_num_by_partition_name (char const *name);
-extern bool emmckey_is_protected (struct mmc *mmc);
+extern struct partitions *get_partition_info_by_num(const int num);
+extern bool emmckey_is_protected(struct mmc *mmc);
extern int info_disprotect;
extern int dtb_read(void *addr);
extern int dtb_write(void *addr);
@@ -38,7 +43,6 @@
cpu_id_t cpu_id = get_cpu_id();
-
if (strcmp(part_name, "bootloader") == 0) {
*off = 0;
if (cpu_id.family_id >= MESON_CPU_MAJOR_ID_GXL) {
@@ -56,6 +60,13 @@
printf("error partition name!\n");
return 1;
}
+ if ((part_info->mask_flags & PART_PROTECT_FLAG) &&
+ !(info_disprotect & DISPROTECT_KEY)) {
+ printf("%s is protected, pls open it in Dts\n",
+ part_info->name);
+ return 1;
+ }
+
*off = part_info->offset+offset;
if (offset >= part_info->size) {
printf("Start address out #%s# partition'address region,(off < 0x%llx)\n",
@@ -75,8 +86,6 @@
return 0;
}
-
-
static int storage_rsv_range_check(char const *part_name, size_t *size,loff_t *off) {
struct partitions *part = NULL;
@@ -105,7 +114,6 @@
return 0;
}
-
static int storage_byte_read(struct mmc *mmc,loff_t off, size_t size,void *addr) {
int blk_shift = 0;
@@ -115,6 +123,10 @@
void *addr_byte;
blk_shift = ffs(mmc->read_bl_len) - 1;
+ if (blk_shift < 0) {
+ printf("bad shift.\n");
+ return 1;
+ }
blk = off >> blk_shift ;
cnt = size >> blk_shift ;
sz_byte = size - ((cnt) << blk_shift) ;
@@ -143,8 +155,6 @@
free(addr_tmp);
}
return (n == cnt) ? 0 : 1;
-
-
}
static int storage_byte_write(struct mmc *mmc,loff_t off, size_t size,void *addr) {
@@ -153,6 +163,10 @@
u64 cnt = 0, n = 0, blk = 0, sz_byte = 0;
blk_shift = ffs(mmc->read_bl_len) - 1;
+ if (blk_shift < 0) {
+ printf("bad shift.\n");
+ return 1;
+ }
blk = off >> blk_shift ;
cnt = size >> blk_shift ;
sz_byte = size - ((cnt) << blk_shift);
@@ -189,13 +203,16 @@
return (n == cnt) ? 0 : 1;
}
-
static int storage_byte_erase(struct mmc *mmc,loff_t off, size_t size) {
int blk_shift = 0;
u64 cnt = 0, n = 0, blk = 0;
blk_shift = ffs(mmc->read_bl_len) - 1;
+ if (blk_shift < 0) {
+ printf("bad shift.\n");
+ return 1;
+ }
blk = off >> blk_shift ;
cnt = size >> blk_shift ;
mmc_init(mmc);
@@ -224,8 +241,6 @@
return (ret == 0) ? 0 : 1;
}
-
-
static int storage_read_in_part(char const *part_name, loff_t off, size_t size, void *dest)
{
int ret =1;
@@ -245,7 +260,6 @@
return ret;
}
-
static int storage_write_in_part(char const *part_name, loff_t off, size_t size, void *source)
{
int ret = 1;
@@ -264,6 +278,40 @@
return ret;
}
+static int storage_mmc_erase_user(struct mmc *mmc) {
+ int ret = 0, i;
+ struct partitions *part_info = NULL;
+
+ if (info_disprotect & DISPROTECT_KEY) {//key disprotect,erase all
+ ret = blk_derase(mmc_get_blk_desc(mmc), 0, 0);
+ } else {//key protect partition with the protect_flag
+ for (i = 0;;i++) {
+ part_info = get_partition_info_by_num(i);
+ if (part_info == NULL)
+ break;
+ if (!strcmp("reserved", part_info->name)) {
+ printf("Part:reserved is skiped\n");
+ continue;
+ }
+ if (part_info->size == 0) {
+ printf("Part:%s size is 0\n", part_info->name);
+ continue;
+ }
+ if (part_info->mask_flags & PART_PROTECT_FLAG) {
+ printf("Part:%s is protected\n", part_info->name);
+ continue;
+ }
+ ret = blk_derase(mmc_get_blk_desc(mmc),
+ part_info->offset / BLOCK_SIZE,
+ part_info->size / BLOCK_SIZE);
+ printf("Erased: %s %s\n",
+ part_info->name,
+ (ret == 0)? "OK" : "ERR");
+ }
+ }
+ printf("User partition erased: %s\n", (ret == 0) ? "OK" : "ERROR");
+ return ret;
+}
static int storage_mmc_erase(int flag, struct mmc *mmc) {
@@ -271,12 +319,8 @@
loff_t off = 0;
size_t size = 0;
- if (flag >= ERASE_ALL) {//erase all
-
- info_disprotect |= DISPROTECT_KEY;
- ret = blk_derase(mmc_get_blk_desc(mmc), 0, 0);
- printf("user partition erased: %s\n", (ret == 0) ? "OK" : "ERROR");
- info_disprotect &= ~DISPROTECT_KEY;
+ if (flag >= ERASE_ALL) {//erase all except reserved
+ ret = storage_mmc_erase_user(mmc);
if (ret != 0) {
return -1;
}
@@ -306,18 +350,13 @@
}
return ret;
-
-
}
-
-
int mmc_storage_init(unsigned char init_flag) {
int ret =1;
struct mmc *mmc;
mmc = find_mmc_device(STORAGE_EMMC);
- mmc->init_in_progress = 0;
mmc->has_init=0;
pinctrl_select_state(mmc->dev, "default");
if (!mmc) {
@@ -398,40 +437,36 @@
return 1;
if (!part_name) {//the operating object is the device,the unit of operation is block.
- info_disprotect |= DISPROTECT_KEY;
- ret = blk_derase(mmc_get_blk_desc(mmc), off, size);
- info_disprotect &= ~DISPROTECT_KEY;
- printf("%d blocks erased: %s\n", ret, (ret == 0) ? "OK" : "ERROR");
+ ret = storage_mmc_erase(ERASE_ALL, mmc);
return (ret == 0) ? 0 : 1;
} else {//the opering object is partition,the unit of operation is byte.
-
ret = storage_erase_in_part(part_name, off, size);
}
return ret;
}
uint8_t mmc_storage_get_copies(const char *part_name) {
+ struct mmc *mmc;
- char ret=3;
+ mmc = find_mmc_device(STORAGE_EMMC);
+ if (!mmc)
+ return 1;
- return ret;
+ if (aml_gpt_valid(mmc) == 0)
+ return 2;
+ return 3;
}
uint64_t mmc_get_copy_size(const char *part_name) {
-
struct partitions *part_info = NULL;
-#ifdef CONFIG_AML_GPT
- return UBOOT_SIZE*512;
-#else
- part_info = find_mmc_partition_by_name("bootloader");
+ part_info = aml_get_partition_by_name("bootloader");
if (part_info == NULL) {
printf("get partition info failed !!\n");
return -1;
}
return part_info->size;
-#endif
}
/* dtb read&write operation with backup updates */
@@ -448,13 +483,39 @@
return checksum;
}
+static int fill_mask8_part(struct part_property *mask8)
+{
+ struct partitions *part;
+ int i = 0, mask8_cnt = 0;
+
+ part = get_partition_info_by_num(i);
+ while (part) {
+ if ((part->mask_flags == 8)
+ && (mask8_cnt++ < BOOTINFO_MAX_PARTITIONS)) {
+ strncpy(mask8->name, part->name, strlen(part->name));
+ mask8->addr = part->offset / MMC_BLOCK_SIZE;
+ mask8->size = part->size / MMC_BLOCK_SIZE;
+ mask8++;
+ }
+ if (mask8_cnt == BOOTINFO_MAX_PARTITIONS)
+ break;
+ i++;
+ part = get_partition_info_by_num(i);
+ }
+
+ return mask8_cnt;
+}
+
static int amlmmc_write_info_sector(struct mmc *mmc)
{
struct storage_emmc_boot_info *boot_info;
struct virtual_partition *ddr_part;
struct partitions *part;
+ /* partitons with mask = 8 need to fill to bootinfo */
+ struct part_property *mask8;
+ int mask8_partition_count;
u8 *buffer;
- int ret = 0;
+ int ret = 0, i;
buffer = malloc(MMC_BLOCK_SIZE);
if (!buffer)
@@ -467,14 +528,25 @@
ddr_part = aml_get_virtual_partition_by_name(MMC_DDR_PARAMETER_NAME);
boot_info->ddr.addr = ddr_part->offset / MMC_BLOCK_SIZE;
boot_info->ddr.size = ddr_part->size / MMC_BLOCK_SIZE;
+
+ mask8 = boot_info->parts;
+ mask8_partition_count = fill_mask8_part(mask8);
+
boot_info->version = 1;
boot_info->checksum = _calc_boot_info_checksum(boot_info);
- printf("boot_info.rsv_base_addr\t:\t%04x\n", boot_info->rsv_base_addr);
- printf("boot_info.ddr.addr\t:\t%04x\n", boot_info->ddr.addr);
- printf("boot_info.ddr.size\t:\t%04x\n", boot_info->ddr.size);
- printf("boot_info.version\t:\t%04x\n", boot_info->version);
- printf("boot_info.checksum\t:\t%04x\n", boot_info->checksum);
+ printf("boot_info.rsv_base_addr:\t%04x\n", boot_info->rsv_base_addr);
+ printf("boot_info.ddr.addr:%04x\n", boot_info->ddr.addr);
+ printf("boot_info.ddr.size:%04x\n", boot_info->ddr.size);
+ printf("boot info: parts %d\n", mask8_partition_count);
+ for (i = 0; i < mask8_partition_count; i++) {
+ printf("boot_info.part[%d]\n", i);
+ printf("\t.name:%s\n", boot_info->parts[i].name);
+ printf("\t.addr:%04x\n", boot_info->parts[i].addr);
+ printf("\t.size:%04x\n", boot_info->parts[i].size);
+ }
+ printf("boot_info.version:%04x\n", boot_info->version);
+ printf("boot_info.checksum:%04x\n", boot_info->checksum);
if (blk_dwrite(mmc_get_blk_desc(mmc), 0, 1, buffer) != 1)
ret = -EIO;
@@ -483,79 +555,13 @@
return ret;
}
-#define MAX_REACHABLE_RSV_RANGE 0x30000
-static int amlmmc_boot_info_check(struct mmc *mmc)
-{
- struct storage_emmc_boot_info *boot_info;
- struct virtual_partition *ddr_part;
- u64 src;
- u32 *buffer, checksum = 0;
- int i = 0, ret = -1;
-
- buffer = malloc(MMC_BLOCK_SIZE);
- if (!buffer)
- return -ENOMEM;
-
- if (blk_dread(mmc_get_blk_desc(mmc), 0, 1, buffer) != 1) {
- ret = -EIO;
- goto _err;
- }
- boot_info = (struct storage_emmc_boot_info *)buffer;
- ddr_part = aml_get_virtual_partition_by_name(MMC_DDR_PARAMETER_NAME);
- if (boot_info->ddr.addr != ddr_part->offset / MMC_BLOCK_SIZE)
- goto _err;
-
- if (!boot_info->checksum || boot_info->version != 0x01)
- goto _err;
-
- src = boot_info->rsv_base_addr + boot_info->ddr.addr;
- if (!src || src == (uint64_t)(-1) || src > MAX_REACHABLE_RSV_RANGE)
- goto _err;
-
- do {
- checksum += buffer[i];
- } while (i++ < ((EMMC_BOOT_INFO_SIZE >> 2) - 2));
-
- if (!checksum)
- goto _err;
-
- if (checksum == boot_info->checksum)
- ret = 0;
-_err:
- free(buffer);
- return ret;
-}
-
-int amlmmc_check_and_update_boot_info(void)
-{
- struct mmc *mmc;
- int ret = 0, i;
-
- mmc = find_mmc_device(STORAGE_EMMC);
- if (!mmc)
- return -ENODEV;
-
- for (i = 1; i < 3; i++) {
- if (blk_select_hwpart_devnum(IF_TYPE_MMC, STORAGE_EMMC, i)) {
- printf("switch dev %d to boot%d fail\n",
- STORAGE_EMMC, i - 1);
- continue;
- }
- if (!amlmmc_boot_info_check(mmc))
- break;
- ret = amlmmc_write_info_sector(mmc);
- if (ret)
- return -EIO;
- }
- blk_select_hwpart_devnum(IF_TYPE_MMC, STORAGE_EMMC, USER_PARTITION);
- return ret;
-}
-
-
int mmc_boot_read(const char *part_name, uint8_t cpy, size_t size, void *dest) {
char ret=1;
int i;
+ struct mmc *mmc;
+
+ mmc = find_mmc_device(STORAGE_EMMC);
if (cpy == 0)
cpy = 1;
@@ -566,14 +572,13 @@
else if (cpy == 0xff)
cpy = 7;
for (i=0;i<3;i++) {//cpy:
-
if (cpy & 1) {
ret = blk_select_hwpart_devnum(IF_TYPE_MMC, STORAGE_EMMC, i);
if (ret) goto R_SWITCH_BACK;
-#ifdef CONFIG_AML_GPT
- if (i == 0)
+
+ if (mmc != NULL && i == 0 && aml_gpt_valid(mmc) == 0)
continue;
-#endif
+
ret = storage_read_in_part(part_name, 0, size, dest);
if (ret != 0) {
@@ -603,6 +608,7 @@
struct mmc *mmc;
mmc = find_mmc_device(STORAGE_EMMC);
+
if (cpy == 0)
cpy = 1;
else if (cpy == 1)
@@ -622,10 +628,10 @@
size = CONFIG_EMMC_BOOT1_TOUCH_REGION;
}
#endif
-#ifdef CONFIG_AML_GPT
- if (i == 0)
+
+ if (mmc != NULL && i == 0 && aml_gpt_valid(mmc) == 0)
continue;
-#endif
+
ret = storage_write_in_part(part_name, 0, size, source);
if (ret != 0) {
@@ -655,6 +661,9 @@
char ret=1;
int i;
size_t size = 0;
+ struct mmc *mmc;
+
+ mmc = find_mmc_device(STORAGE_EMMC);
if (cpy == 0)
cpy = 1;
@@ -674,10 +683,10 @@
size = CONFIG_EMMC_BOOT1_TOUCH_REGION;
}
#endif
-#ifdef CONFIG_AML_GPT
- if (i == 0)
+
+ if (mmc != NULL && i == 0 && aml_gpt_valid(mmc) == 0)
continue;
-#endif
+
ret = storage_erase_in_part(part_name, 0, size);
if (ret != 0) {
@@ -700,6 +709,87 @@
return ret;
}
+int mmc_gpt_read(void *source)
+{
+ struct mmc *mmc;
+ struct blk_desc *dev_desc;
+ unsigned long offset = 0;
+ size_t size = 34;
+ int ret;
+
+ mmc = find_mmc_device(STORAGE_EMMC);
+ if (!mmc)
+ return -1;
+
+ dev_desc = mmc_get_blk_desc(mmc);
+ ret = blk_dread(dev_desc, offset, size, (u_char *)source);
+ if (ret != size)
+ return -1;
+
+ if (is_valid_gpt_buf(dev_desc, (u_char *)source)) {
+ printf("%s: invalid GPT\n", __func__);
+ return 1;
+ }
+
+ return 0;
+}
+
+int mmc_gpt_write(void *source)
+{
+ struct blk_desc *dev_desc;
+ struct mmc *mmc;
+
+ mmc = find_mmc_device(STORAGE_EMMC);
+ if (!mmc)
+ return 1;
+
+ dev_desc = mmc_get_blk_desc(mmc);
+ if (is_valid_gpt_buf(dev_desc, (u_char *)source)) {
+ printf("%s: invalid GPT - refusing to write to flash\n", __func__);
+ return -1;
+ }
+
+ if (write_mbr_and_gpt_partitions(dev_desc, (u_char *)source)) {
+ printf("%s: writing GPT partitions failed\n", __func__);
+ return -1;
+ }
+
+ if (get_ept_from_gpt(mmc) != 0)
+ printf("get ept from gpt failed\n");
+
+ printf("update gpt and ept success\n");
+ return 0;
+}
+
+/*
+ * check is gpt is valid
+ * if valid return 0
+ * else return 1
+ */
+int mmc_gpt_erase(void)
+{
+ struct blk_desc *dev_desc;
+ struct mmc *mmc;
+ int ret;
+
+ mmc = find_mmc_device(STORAGE_EMMC);
+ if (!mmc)
+ return 1;
+
+ dev_desc = mmc_get_blk_desc(mmc);
+ if (!dev_desc) {
+ printf("%s: Invalid Argument(s)\n", __func__);
+ return 1;
+ }
+
+ ret = erase_gpt_part_table(dev_desc);
+ if (ret) {
+ printf("%s, failed erase gpt", __func__);
+ return 1;
+ }
+ return 0;
+}
+
uint32_t mmc_get_rsv_size(const char *rsv_name) {
struct virtual_partition *vpart = NULL;
@@ -709,13 +799,23 @@
}
+static inline int env_read(size_t size, void *buf) {
+ return storage_read_in_part("env", 0, size, buf);
+}
+
+static inline int env_write(size_t size, void *buf) {
+ return storage_write_in_part("env", 0, size, buf);
+}
+
int mmc_read_rsv(const char *rsv_name, size_t size, void *buf) {
char ret=1;
struct mmc *mmc;
loff_t off =0;
- unsigned long dtImgAddr = simple_strtoul(buf, NULL, 16);
- ret = !strcmp("key", rsv_name) || !strcmp("dtb", rsv_name)||!strcmp("fastboot", rsv_name)||!strcmp("ddr-parameter", rsv_name);
+ /*unsigned long dtImgAddr = simple_strtoul(buf, NULL, 16);*/
+ ret = !strcmp("env", rsv_name) || !strcmp("key", rsv_name)
+ || !strcmp("dtb", rsv_name)||!strcmp("fastboot", rsv_name)
+ ||!strcmp("ddr-parameter", rsv_name);
if (!ret) return 1;
mmc = find_mmc_device(STORAGE_EMMC);
@@ -723,6 +823,12 @@
puts("no mmc devices available\n");
return 1;
}
+
+ if (!strcmp("env", rsv_name)) {
+ ret = env_read(size, buf);
+ return ret;
+ }
+
ret = storage_rsv_range_check(rsv_name, &size, &off);
if (ret) return ret;
if (!strcmp("dtb", rsv_name)) {
@@ -730,25 +836,29 @@
return ret;
}
- if (!strcmp("key", rsv_name))
+ if (!strcmp("key", rsv_name)) {
info_disprotect |= DISPROTECT_KEY;
- ret = storage_byte_read(mmc, off, size, buf);
- if (!strcmp("key", rsv_name))
+ ret = mmc_key_read(buf, size, 0);
info_disprotect &= ~DISPROTECT_KEY;
- if (ret != 0) {
+ } else
+ ret = storage_byte_read(mmc, off, size, buf);
+
+ if (ret != 0)
printf("read resv failed\n");
- }
return ret;
}
int mmc_write_rsv(const char *rsv_name, size_t size, void *buf) {
- struct mmc *mmc;
- loff_t off =0;
- int ret = 1;
+ char ret=1;
- ret = !strcmp("key", rsv_name) || !strcmp("dtb", rsv_name)||!strcmp("fastboot", rsv_name)||!strcmp("ddr-parameter", rsv_name);
+ struct mmc *mmc;
+ loff_t off = 0;
+
+ ret = !strcmp("env", rsv_name) || !strcmp("key", rsv_name)
+ || !strcmp("dtb", rsv_name)||!strcmp("fastboot", rsv_name)
+ ||!strcmp("ddr-parameter", rsv_name);
if (!ret)
return 1;
mmc = find_mmc_device(STORAGE_EMMC);
@@ -756,35 +866,44 @@
puts("no mmc devices available\n");
return 1;
}
+
+ if (!strcmp("env", rsv_name)) {
+ ret = env_write(size, buf);
+ return ret;
+ }
+
ret = storage_rsv_range_check(rsv_name, &size, &off);
if (ret) return ret;
if (!strcmp("dtb", rsv_name)) {
ret = dtb_write(buf);
- ret |= renew_partition_tbl(buf);
- return ret;
- }
-
- if (!strcmp("key", rsv_name))
+ if (!gpt_partition) {
+ /* renew partition table @ once*/
+ printf("renew partition table\n");
+ ret |= renew_partition_tbl(buf);
+ }
+ } else if (!strcmp("key", rsv_name)) {
info_disprotect |= DISPROTECT_KEY;
- if (!strcmp("ddr-parameter", rsv_name))
- amlmmc_check_and_update_boot_info();
- ret = storage_byte_write(mmc, off, size, buf);
- if (!strcmp("key", rsv_name))
+ ret = mmc_key_write(buf, size, 0);
info_disprotect &= ~DISPROTECT_KEY;
- if (ret != 0) {
- printf("write resv failed\n");
- }
+ } else
+ ret = storage_byte_write(mmc, off, size, buf);
+
+ if (ret != 0)
+ printf("write rsv failed\n");
return ret;
}
+
int mmc_erase_rsv(const char *rsv_name) {
char ret=1;
struct mmc *mmc;
loff_t off = 0;
size_t size = 0;
- ret = !strcmp("key", rsv_name) || !strcmp("dtb", rsv_name)||!strcmp("fastboot", rsv_name)||!strcmp("ddr-parameter", rsv_name);
+ ret = !strcmp("key", rsv_name) || !strcmp("dtb", rsv_name)
+ ||!strcmp("fastboot", rsv_name)
+ ||!strcmp("ddr-parameter", rsv_name);
if (!ret) return 1;
mmc = find_mmc_device(STORAGE_EMMC);
if (!mmc) {
@@ -792,12 +911,16 @@
return 1;
}
ret = storage_rsv_range_check(rsv_name, &size, &off);
- if (ret) return ret;
- if (!strcmp("key", rsv_name))
+ if (ret)
+ return ret;
+
+ if (!strcmp("key", rsv_name)) {
info_disprotect |= DISPROTECT_KEY;
- ret = storage_byte_erase(mmc, off, size);
- if (!strcmp("key", rsv_name))
+ ret = mmc_key_erase();
info_disprotect &= ~DISPROTECT_KEY;
+ } else
+ ret = storage_byte_erase(mmc, off, size);
+
if (ret != 0) {
printf("erase resv failed\n");
}
@@ -822,75 +945,94 @@
}
+void config_storage_dev_func(struct storage_t *dev, struct mmc* mmc)
+{
+ /******basic info*******/
+ dev->type = BOOT_EMMC;
+ printf("store flag: %d, types: %d\n", dev->init_flag, dev->type);
+ /*dev->info.name = mmc->cid[0] & 0xff,
+ (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
+ (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff;
+ dev->info.id = mmc->cid[0] >> 24;*/
+ dev->info.read_unit = mmc->read_bl_len;
+ dev->info.write_unit = mmc->write_bl_len;
+ dev->info.erase_unit = mmc->erase_grp_size;
+ dev->info.caps = mmc->capacity_user;
+ dev->info.mode = COMPACT_BOOTLOADER;
+
+ dev->get_part_size = mmc_storage_get_part_size;
+ dev->read = mmc_storage_read;
+ dev->write = mmc_storage_write;
+ dev->erase = mmc_storage_erase;
+
+ dev->get_copies = mmc_storage_get_copies;
+ dev->get_copy_size = mmc_get_copy_size;
+ dev->boot_read = mmc_boot_read;
+ dev->boot_write = mmc_boot_write;
+ dev->boot_erase = mmc_boot_erase;
+
+ dev->get_rsv_size = mmc_get_rsv_size;
+ dev->read_rsv = mmc_read_rsv;
+ dev->write_rsv = mmc_write_rsv;
+ dev->erase_rsv = mmc_erase_rsv;
+ dev->protect_rsv = mmc_protect_rsv;
+
+ dev->gpt_read = mmc_gpt_read;
+ dev->gpt_write = mmc_gpt_write;
+ dev->gpt_erase = mmc_gpt_erase;
+
+ return;
+}
+
+DECLARE_GLOBAL_DATA_PTR;
+int sdcard_pre(void)
+{
+ return 0;
+}
+
+
+int sdcard_probe(uint32_t init_flag)
+{
+ return 0;
+}
+
int emmc_pre(void)
{
char ret = 1;
struct mmc *mmc;
+ static struct storage_t *storage_dev = NULL;
+
+ mmc_initialize(gd->bd);
mmc = find_mmc_device(STORAGE_EMMC);
+ mmc->has_init = 0;
ret = mmc_start_init(mmc);
- if (ret == 0)
- printf("emmc init success!\n");
- else
- printf("emmc init fail!\n");
+ if (ret == 0) {
+ /*struct store_operation *storage_opera = NULL;*/
+ storage_dev = kzalloc(sizeof(struct storage_t), GFP_KERNEL);
+ if (storage_dev == NULL) {
+ printf("malloc failed for storage_dev\n");
+ ret = -1;
+ return ret;
+ }
+ config_storage_dev_func(storage_dev, mmc);
+ store_register(storage_dev);
+ printf("emmc init success!\n");
+ } else
+ printf("emmc init fail!\n");
return ret;
}
-
int emmc_probe(uint32_t init_flag)
{
char ret = 0;
- struct mmc *mmc;
- static struct storage_t *storage_dev = NULL;
- /*struct store_operation *storage_opera = NULL;*/
- storage_dev = kzalloc(sizeof(struct storage_t), GFP_KERNEL);
- if (storage_dev == NULL) {
- printf("malloc failed for storage_dev\n");
- ret = -1;
- goto exit_error;
- }
- mmc = find_mmc_device(STORAGE_EMMC);
- if (init_flag != 0xff)
- ret = mmc_storage_init(init_flag); /*flag 0*/
+
+ ret = mmc_storage_init(init_flag); /*flag 0*/
if (ret) {
printf("mmc init failed ret:%x\n", ret);
goto exit_error;
}
- /******basic info*******/
- storage_dev->init_flag = init_flag;
- storage_dev->type = BOOT_EMMC;
-
- pr_info("store flag: %d, types: %d\n",storage_dev->init_flag,storage_dev->type);
- /*storage_dev->info.name = mmc->cid[0] & 0xff,
- (mmc->cid[1] >> 24), (mmc->cid[1] >> 16) & 0xff,
- (mmc->cid[1] >> 8) & 0xff, mmc->cid[1] & 0xff;
- storage_dev->info.id = mmc->cid[0] >> 24;*/
- storage_dev->info.read_unit = mmc->read_bl_len;
- storage_dev->info.write_unit = mmc->write_bl_len;
- storage_dev->info.erase_unit = mmc->erase_grp_size;
- storage_dev->info.caps = mmc->capacity_user;
- storage_dev->info.mode = DISCRETE_BOOTLOADER;
-
- storage_dev->get_part_size = mmc_storage_get_part_size;
- storage_dev->read = mmc_storage_read;
- storage_dev->write = mmc_storage_write;
- storage_dev->erase = mmc_storage_erase;
-
- storage_dev->get_copies = mmc_storage_get_copies;
- storage_dev->get_copy_size = mmc_get_copy_size;
- storage_dev->boot_read = mmc_boot_read;
- storage_dev->boot_write = mmc_boot_write;
- storage_dev->boot_erase = mmc_boot_erase;
-
- storage_dev->get_rsv_size = mmc_get_rsv_size;
- storage_dev->read_rsv = mmc_read_rsv;
- storage_dev->write_rsv = mmc_write_rsv;
- storage_dev->erase_rsv = mmc_erase_rsv;
- storage_dev->protect_rsv = mmc_protect_rsv;
- store_register(storage_dev);
printf("emmc probe success\n");
- if (init_flag != 0xff)
- return !is_partition_checked;
exit_error:
return ret;
}
diff --git a/drivers/mtd/Kconfig b/drivers/mtd/Kconfig
index 2386ae9..cb158b1 100644
--- a/drivers/mtd/Kconfig
+++ b/drivers/mtd/Kconfig
@@ -94,6 +94,25 @@
This enables access to Hyperflash memory through the Renesas
RCar Gen3 RPC controller.
+config AML_MTDPART
+ bool "Enable Amlogic partition"
+ depends on MTD
+ help
+ This option, if enabled, we will parse amlogic partition
+ table.
+
+config AML_MTD
+ bool "support AML MTD for Raw NAND or SPI NAND or SPI NOR"
+ default y if MESON_NFC || SPI_NAND || SPI_FLASH || MTD_SPI_NAND
+ help
+ This option, if enabled, support for AML MTD
+
+config AML_MTDPART
+ bool "support AML MTD partition for raw NAND or SPI nand or SPI NOR"
+ default y if AML_MTD
+ help
+ This option, if enabled, support for AML MTD partition
+
source "drivers/mtd/nand/Kconfig"
source "drivers/mtd/spi/Kconfig"
@@ -101,4 +120,3 @@
source "drivers/mtd/ubi/Kconfig"
endmenu
-
diff --git a/drivers/mtd/Makefile b/drivers/mtd/Makefile
index 2093030..4748a66 100644
--- a/drivers/mtd/Makefile
+++ b/drivers/mtd/Makefile
@@ -20,4 +20,6 @@
obj-$(CONFIG_RENESAS_RPC_HF) += renesas_rpc_hf.o
obj-y += nand/
+obj-y += aml_rsv.o
+#obj-$(CONFIG_AML_MTD) += aml_rsv.o
obj-$(CONFIG_AML_STORAGE) += aml_storage.o
diff --git a/drivers/mtd/aml_rsv.c b/drivers/mtd/aml_rsv.c
new file mode 100644
index 0000000..1baf98c
--- /dev/null
+++ b/drivers/mtd/aml_rsv.c
@@ -0,0 +1,1280 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <malloc.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <linux/mtd/mtd.h>
+#include <amlogic/aml_rsv.h>
+#include <amlogic/aml_mtd.h>
+#include <partition_table.h>
+#include <amlogic/storage.h>
+
+#undef pr_info
+#define pr_info printf
+
+extern int info_disprotect;
+static struct meson_rsv_handler_t *rsv_handler;
+
+static struct free_node_t *get_free_node(struct meson_rsv_info_t *rsv_info)
+{
+ struct meson_rsv_handler_t *handler = rsv_info->handler;
+ u32 index;
+
+ index =
+ find_first_zero_bit((void *)&handler->fn_bitmask,
+ NAND_RSV_BLOCK_NUM);
+ if (index > NAND_RSV_BLOCK_NUM) {
+ pr_info("%s %d index :%d is greater than max rsv block num\n",
+ __func__, __LINE__, index);
+ return NULL;
+ }
+ WARN_ON(test_and_set_bit(index, (void *)&handler->fn_bitmask));
+
+ return handler->free_node[index];
+}
+
+static void release_free_node(struct meson_rsv_info_t *rsv_info,
+ struct free_node_t *free_node)
+{
+ struct meson_rsv_handler_t *handler = rsv_info->handler;
+ u32 index = free_node->index;
+
+ pr_info("%s %d: bitmask = 0x%llx\n",
+ __func__, __LINE__, handler->fn_bitmask);
+ if (index > NAND_RSV_BLOCK_NUM) {
+ pr_info("%s %d index :%d is greater than max rsv block num\n",
+ __func__, __LINE__, index);
+ return;
+ }
+ WARN_ON(!test_and_clear_bit(index, (void *)&handler->fn_bitmask));
+ memset(free_node, 0, sizeof(struct free_node_t));
+ free_node->index = index;
+ pr_info("%s %d: bitmask = 0x%llx\n",
+ __func__, __LINE__, handler->fn_bitmask);
+}
+
+static inline void menson_rsv_disprotect(void)
+{
+ /*disprotect*/
+ info_disprotect |= DISPROTECT_KEY;
+ info_disprotect |= DISPROTECT_FBBT;
+}
+static inline void menson_rsv_protect(void)
+{
+ /*protect*/
+ info_disprotect &= ~DISPROTECT_KEY;
+ info_disprotect &= ~DISPROTECT_FBBT;
+
+}
+
+int meson_rsv_erase_protect(struct meson_rsv_handler_t *handler,
+ u32 block_addr)
+{
+ if (handler->key && handler->key->valid) {
+ if (!(info_disprotect & DISPROTECT_KEY) &&
+ block_addr >= handler->key->start &&
+ block_addr < handler->key->end)
+ return -1;
+ }
+ if (handler->bbt && handler->bbt->valid) {
+ if ((!(info_disprotect & DISPROTECT_FBBT)) &&
+ (block_addr >= handler->bbt->start) &&
+ (block_addr < handler->bbt->end))
+ return -1;
+ }
+ return 0;
+}
+
+int meson_rsv_free(struct meson_rsv_info_t *rsv_info)
+{
+ struct mtd_info *mtd = rsv_info->mtd;
+ struct free_node_t *tmp_node, *next_node = NULL;
+ int error = 0;
+ loff_t addr = 0;
+ struct erase_info erase_info;
+
+ pr_info("free %s\n", rsv_info->name);
+
+ if (rsv_info->valid) {
+ addr = rsv_info->nvalid->blk_addr;
+ addr *= mtd->erasesize;
+ memset(&erase_info, 0, sizeof(struct erase_info));
+ erase_info.mtd = mtd;
+ erase_info.addr = addr;
+ erase_info.len = mtd->erasesize;
+ menson_rsv_disprotect();
+ error = mtd_erase(mtd, &erase_info);
+ menson_rsv_protect();
+ pr_info("erasing valid info block: %llx\n", addr);
+ rsv_info->nvalid->blk_addr = -1;
+ rsv_info->nvalid->ec = -1;
+ rsv_info->nvalid->page_addr = 0;
+ rsv_info->nvalid->timestamp = 0;
+ rsv_info->nvalid->status = 0;
+ rsv_info->valid = 0;
+ }
+ tmp_node = rsv_info->nfree;
+ while (tmp_node) {
+ next_node = tmp_node->next;
+ release_free_node(rsv_info, tmp_node);
+ tmp_node = next_node;
+ }
+ rsv_info->nfree = NULL;
+
+ return error;
+}
+
+int meson_rsv_save(struct meson_rsv_info_t *rsv_info, u_char *buf)
+{
+ struct mtd_info *mtd = rsv_info->mtd;
+ struct free_node_t *free_node, *temp_node;
+ struct erase_info erase_info;
+ int ret = 0, i = 1, pages_per_blk;
+ loff_t offset = 0;
+
+ pages_per_blk = 1 << (mtd->erasesize_shift - mtd->writesize_shift);
+ if ((rsv_info->nvalid->status & POWER_ABNORMAL_FLAG) ||
+ (rsv_info->nvalid->status & ECC_ABNORMAL_FLAG))
+ rsv_info->nvalid->page_addr = pages_per_blk;
+ if (mtd->writesize < rsv_info->size)
+ i = (rsv_info->size + mtd->writesize - 1) / mtd->writesize;
+ pr_info("%s %d: %s, valid = %d, pages = %d\n", __func__, __LINE__,
+ rsv_info->name, rsv_info->valid, i);
+RE_SEARCH:
+ if (rsv_info->valid) {
+ rsv_info->nvalid->page_addr += i;
+ if ((rsv_info->nvalid->page_addr + i) > pages_per_blk) {
+ if ((rsv_info->nvalid->page_addr - i) ==
+ pages_per_blk) {
+ offset = rsv_info->nvalid->blk_addr;
+ offset *= mtd->erasesize;
+ erase_info.mtd = mtd;
+ erase_info.addr = offset;
+ erase_info.len = mtd->erasesize;
+ menson_rsv_disprotect();
+ ret = mtd_erase(mtd, &erase_info);
+ menson_rsv_protect();
+ rsv_info->nvalid->ec++;
+ pr_info("%s %d: erasing bad info block:0x%llx\n",
+ __func__, __LINE__, offset);
+ }
+ free_node = get_free_node(rsv_info);
+ if (!free_node)
+ return -ENOMEM;
+ /* set current valid node to free list */
+ free_node->blk_addr = rsv_info->nvalid->blk_addr;
+ free_node->ec = rsv_info->nvalid->ec;
+ temp_node = rsv_info->nfree;
+ while (temp_node->next)
+ temp_node = temp_node->next;
+ temp_node->next = free_node;
+ /* get one node from free list and set to current */
+ temp_node = rsv_info->nfree;
+ rsv_info->nvalid->blk_addr = temp_node->blk_addr;
+ rsv_info->nvalid->page_addr = 0;
+ rsv_info->nvalid->ec = temp_node->ec;
+ rsv_info->nvalid->timestamp++;
+ rsv_info->nfree = temp_node->next;
+ release_free_node(rsv_info, temp_node);
+ }
+ } else {
+ temp_node = rsv_info->nfree;
+ rsv_info->nvalid->blk_addr = temp_node->blk_addr;
+ rsv_info->nvalid->page_addr = 0;
+ rsv_info->nvalid->ec = temp_node->ec;
+ rsv_info->nvalid->timestamp++;
+ rsv_info->nfree = temp_node->next;
+ release_free_node(rsv_info, temp_node);
+ }
+ offset = rsv_info->nvalid->blk_addr;
+ offset *= mtd->erasesize;
+ offset += rsv_info->nvalid->page_addr * mtd->writesize;
+ if (rsv_info->nvalid->page_addr == 0) {
+ ret = mtd_block_isbad(mtd, offset);
+ if (ret) {
+ /**
+ * cause our rsv list includes bad block,
+ * so we need check it here and for fear
+ * of data lost.
+ */
+ pr_info("%s %d: %s bad block here 0x%llx\n",
+ __func__, __LINE__, rsv_info->name, offset);
+ rsv_info->nvalid->page_addr = pages_per_blk - i;
+ goto RE_SEARCH;
+ }
+ memset(&erase_info, 0, sizeof(struct erase_info));
+ erase_info.mtd = mtd;
+ erase_info.addr = offset;
+ erase_info.len = mtd->erasesize;
+ menson_rsv_disprotect();
+ ret = mtd_erase(mtd, &erase_info);
+ menson_rsv_protect();
+ if (ret) {
+ pr_info("%s %d %s erase failed at 0x%llx ,mark it bad\n",
+ __func__, __LINE__, rsv_info->name, offset);
+ mtd_block_markbad(mtd, offset);
+ //return ret;
+ rsv_info->nvalid->page_addr = pages_per_blk;
+ goto RE_SEARCH;
+ }
+ rsv_info->nvalid->ec++;
+ }
+ ret = meson_rsv_write(rsv_info, buf);
+ if (ret) {
+ pr_info("%s %d rsv info: %s save failed!\n",
+ __func__, __LINE__, rsv_info->name);
+ return ret;
+ }
+ rsv_info->valid = 1;
+ rsv_info->nvalid->status = 0;
+ return ret;
+}
+
+int meson_rsv_write(struct meson_rsv_info_t *rsv_info, u_char *buf)
+{
+ struct mtd_info *mtd = rsv_info->mtd;
+ struct oobinfo_t oobinfo;
+ struct mtd_oob_ops oob_ops;
+ size_t length = 0;
+ loff_t offset;
+ int ret = 0;
+
+ offset = rsv_info->nvalid->blk_addr;
+ offset *= mtd->erasesize;
+ offset += rsv_info->nvalid->page_addr * mtd->writesize;
+ pr_info("%s %d write %s to 0x%llx\n",
+ __func__, __LINE__, rsv_info->name, offset);
+ memcpy(oobinfo.name, rsv_info->name, 4);
+ oobinfo.ec = rsv_info->nvalid->ec;
+ /* TODO: prevent the unrolling situation here */
+ oobinfo.timestamp = rsv_info->nvalid->timestamp;
+ while (length < rsv_info->size) {
+ oob_ops.mode = MTD_OPS_AUTO_OOB;
+ oob_ops.len = min_t(u32, mtd->writesize,
+ (rsv_info->size - length));
+ oob_ops.ooblen = sizeof(struct oobinfo_t);
+ oob_ops.ooboffs = 0;
+ oob_ops.datbuf = buf + length;
+ oob_ops.oobbuf = (u8 *)&oobinfo;
+ ret = mtd_write_oob(mtd, offset, &oob_ops);
+ if (ret) {
+ pr_info("fail to write %s to 0x%llx ret:%d\n",
+ rsv_info->name, offset, ret);
+ return -EIO;
+ }
+ offset += mtd->writesize;
+ length += oob_ops.len;
+ }
+ return ret;
+}
+
+int meson_rsv_read(struct meson_rsv_info_t *rsv_info, u_char *buf)
+{
+ struct mtd_info *mtd = rsv_info->mtd;
+ struct oobinfo_t oobinfo;
+ struct mtd_oob_ops oob_ops;
+ size_t length = 0;
+ loff_t offset;
+ int ret = 0;
+
+READ_RSV_AGAIN:
+ offset = rsv_info->nvalid->blk_addr;
+ offset *= mtd->erasesize;
+ offset += rsv_info->nvalid->page_addr * mtd->writesize;
+ pr_info("%s %d read %s from 0x%llx\n",
+ __func__, __LINE__, rsv_info->name, offset);
+ memset(buf, 0, rsv_info->size);
+ while (length < rsv_info->size) {
+ oob_ops.mode = MTD_OPS_AUTO_OOB;
+ oob_ops.len = min_t(u32, mtd->writesize,
+ (rsv_info->size - length));
+ oob_ops.ooblen = sizeof(struct oobinfo_t);
+ oob_ops.ooboffs = 0;
+ oob_ops.datbuf = buf + length;
+ oob_ops.oobbuf = (u8 *)&oobinfo;
+
+ memset((u8 *)&oobinfo, 0, oob_ops.ooblen);
+ ret = mtd_read_oob(mtd, offset, &oob_ops);
+ if (ret && (ret != -EUCLEAN)) {
+ pr_info("blk good but read failed: %llx, %d\n",
+ (u64)offset, ret);
+ ret = meson_rsv_scan(rsv_info);
+ if (ret)
+ return -EIO;
+ goto READ_RSV_AGAIN;
+ }
+ /* Do not use strlen ,Use ARRAY_SIZE to make the length 4 */
+ if (memcmp(oobinfo.name, rsv_info->name,
+ 4))
+ pr_info("invalid %s info in %llx:%s\n",
+ rsv_info->name, offset, oobinfo.name);
+ offset += mtd->writesize;
+ length += oob_ops.len;
+ }
+ return ret;
+}
+
+int meson_rsv_erase(struct meson_rsv_info_t *rsv_info)
+{
+ struct mtd_info *mtd = rsv_info->mtd;
+ struct free_node_t *free_node, *temp_node = NULL;
+ int ret = 0;
+ struct erase_info erase_info;
+
+
+ printf("%s %d rsv erasing %s\n",
+ __func__, __LINE__, rsv_info->name);
+
+ if (rsv_info->valid) {
+ rsv_info->nvalid->ec++;
+ rsv_info->nvalid->page_addr = -1;
+ rsv_info->nvalid->timestamp = 1;
+ rsv_info->valid = 0;
+
+ free_node = get_free_node(rsv_info);
+ if (!free_node)
+ return -ENOMEM;
+ /* set current valid node to free list */
+ free_node->blk_addr = rsv_info->nvalid->blk_addr;
+ free_node->ec = rsv_info->nvalid->ec;
+ temp_node = rsv_info->nfree;
+ while (temp_node->next)
+ temp_node = temp_node->next;
+ temp_node->next = free_node;
+ }
+
+ temp_node = rsv_info->nfree;
+ while (temp_node) {
+ memset(&erase_info, 0, sizeof(struct erase_info));
+ erase_info.mtd = mtd;
+ erase_info.addr = temp_node->blk_addr* mtd->erasesize;
+ erase_info.len = mtd->erasesize;
+ menson_rsv_disprotect();
+ ret = mtd_erase(mtd, &erase_info);
+ menson_rsv_protect();
+ printk("erasing valid info block: %llx \n", erase_info.addr);
+ rsv_info->nvalid->ec = -1;
+ temp_node->dirty_flag = 0;
+ temp_node = temp_node->next;
+ }
+ return ret;
+}
+
+int meson_rsv_scan(struct meson_rsv_info_t *rsv_info)
+{
+ struct mtd_info *mtd = rsv_info->mtd;
+ struct mtd_oob_ops oob_ops;
+ struct oobinfo_t oobinfo;
+ struct free_node_t *free_node, *temp_node;
+ loff_t offset;
+ u32 start, end;
+ int ret = 0, error, rsv_status, i, k;
+
+ u8 scan_status;
+ u8 good_addr[256] = {0};
+ u32 page_num, pages_per_blk;
+
+RE_RSV_INFO_EXT:
+ start = rsv_info->start;
+ end = rsv_info->end;
+ pr_info("%s:info size = 0x%x, start blk = %d, end blk = %d\n",
+ rsv_info->name, rsv_info->size, start, end);
+ do {
+ offset = start;
+ offset *= mtd->erasesize;
+ scan_status = 0;
+RE_RSV_INFO:
+ oob_ops.mode = MTD_OPS_AUTO_OOB;
+ oob_ops.len = 0;
+ oob_ops.ooblen = sizeof(struct oobinfo_t);
+ oob_ops.ooboffs = 0;
+ oob_ops.datbuf = NULL;
+ oob_ops.oobbuf = (u8 *)&oobinfo;
+ memset((u8 *)&oobinfo, 0, sizeof(struct oobinfo_t));
+ error = mtd_read_oob(mtd, offset, &oob_ops);
+ if (error && (error != -EUCLEAN)) {
+ pr_info("%s %d blk check good but read failed: %llx, %d\n",
+ __func__, __LINE__, (u64)offset, error);
+ offset += rsv_info->size;
+ if ((scan_status++ > 6) ||
+ (!(offset % mtd->erasesize))) {
+ pr_info("ECC error, scan ONE block exit\n");
+ scan_status = 0;
+ continue;
+ }
+ goto RE_RSV_INFO;
+ }
+ rsv_info->init = 1;
+ rsv_info->nvalid->status = 0;
+ /* Do not use strlen ,Use ARRAY_SIZE to make the length 4 */
+ if (!memcmp(oobinfo.name, rsv_info->name,
+ 4)) {
+ rsv_info->valid = 1;
+ if (rsv_info->nvalid->blk_addr >= 0) {
+ free_node = get_free_node(rsv_info);
+ if (!free_node)
+ return -ENOMEM;
+ free_node->dirty_flag = 1;
+ if (oobinfo.timestamp >
+ rsv_info->nvalid->timestamp) {
+ free_node->blk_addr =
+ rsv_info->nvalid->blk_addr;
+ free_node->ec = rsv_info->nvalid->ec;
+ rsv_info->nvalid->blk_addr = start;
+ rsv_info->nvalid->page_addr = 0;
+ rsv_info->nvalid->ec = oobinfo.ec;
+ rsv_info->nvalid->timestamp =
+ oobinfo.timestamp;
+ } else {
+ free_node->blk_addr = start;
+ free_node->ec = oobinfo.ec;
+ }
+ if (!rsv_info->nfree) {
+ rsv_info->nfree = free_node;
+ } else {
+ temp_node = rsv_info->nfree;
+ while (temp_node->next)
+ temp_node = temp_node->next;
+ temp_node->next = free_node;
+ }
+ } else {
+ rsv_info->nvalid->blk_addr = start;
+ rsv_info->nvalid->page_addr = 0;
+ rsv_info->nvalid->ec = oobinfo.ec;
+ rsv_info->nvalid->timestamp = oobinfo.timestamp;
+ }
+ } else {
+ free_node = get_free_node(rsv_info);
+ if (!free_node)
+ return -ENOMEM;
+ free_node->blk_addr = start;
+ free_node->ec = oobinfo.ec;
+ if (!rsv_info->nfree) {
+ rsv_info->nfree = free_node;
+ } else {
+ temp_node = rsv_info->nfree;
+ while (temp_node->next)
+ temp_node = temp_node->next;
+ temp_node->next = free_node;
+ }
+ }
+ } while ((++start) < end);
+
+ printf("%s blk = %d, ec = %d, page = %d, timestamp = %d\n",
+ rsv_info->name, rsv_info->nvalid->blk_addr, rsv_info->nvalid->ec,
+ rsv_info->nvalid->page_addr, rsv_info->nvalid->timestamp);
+ printf("%s free list: \n", rsv_info->name);
+ temp_node = rsv_info->nfree;
+ while (temp_node) {
+ pr_info("block num = %d, ec = %d, dirty_flag = %d\n",
+ temp_node->blk_addr,
+ temp_node->ec,
+ temp_node->dirty_flag);
+ temp_node = temp_node->next;
+ }
+ /**
+ * step 2, find the newest in the block
+ * watch out here, cause erase size and write size must be
+ * power of 2, and write size must equal page size.
+ */
+ pages_per_blk = 1 << (mtd->erasesize_shift - mtd->writesize_shift);
+ page_num = rsv_info->size >> mtd->writesize_shift;
+ if (!page_num)
+ page_num++;
+ if (rsv_info->valid == 1) {
+ pr_info("%s %d selecting in block: %d\n",
+ __func__, __LINE__, rsv_info->nvalid->blk_addr);
+ oob_ops.mode = MTD_OPS_AUTO_OOB;
+ oob_ops.len = 0;
+ oob_ops.ooblen = sizeof(struct oobinfo_t);
+ oob_ops.ooboffs = 0;
+ oob_ops.datbuf = NULL;
+ oob_ops.oobbuf = (u8 *)&oobinfo;
+ for (i = 0; i < pages_per_blk; i++) {
+ memset((u8 *)&oobinfo, 0, oob_ops.ooblen);
+ offset = rsv_info->nvalid->blk_addr;
+ offset *= mtd->erasesize;
+ offset += mtd->writesize * i;
+ error = mtd_read_oob(mtd, offset, &oob_ops);
+ if (error && error != -EUCLEAN) {
+ pr_info("%s %d blk good but read failed:%llx, %d\n",
+ __func__, __LINE__, (u64)offset, error);
+ rsv_info->nvalid->status |= ECC_ABNORMAL_FLAG;
+ ret = -1;
+ continue;
+ }
+ /* Do not use strlen ,Use ARRAY_SIZE to make the length 4 */
+ if (!memcmp(oobinfo.name, rsv_info->name,
+ 4)) {
+ good_addr[i] = 1;
+ rsv_info->nvalid->page_addr = i;
+ } else {
+ break;
+ }
+ }
+ }
+ if (mtd->writesize < rsv_info->size &&
+ rsv_info->valid == 1) {
+ i = rsv_info->nvalid->page_addr;
+ if (((i + 1) % page_num) != 0) {
+ ret = -1;
+ rsv_info->nvalid->status |= POWER_ABNORMAL_FLAG;
+ pr_info("find %s incomplete\n", rsv_info->name);
+ }
+ pr_info("%s %d page_num %d\n", __func__, __LINE__, page_num);
+ if (ret == -1) {
+ for (i = 0; i < (pages_per_blk / page_num); i++) {
+ rsv_status = 0;
+ for (k = 0; k < page_num; k++) {
+ if (!good_addr[k + i * page_num]) {
+ rsv_status = 1;
+ break;
+ }
+ }
+ if (!rsv_status) {
+ pr_info("find %d page ok\n",
+ i * page_num);
+ rsv_info->nvalid->page_addr =
+ k + i * page_num - 1;
+ ret = 0;
+ }
+ }
+ }
+ if (ret == -1) {
+ rsv_info->nvalid->status = 0;
+ meson_rsv_free(rsv_info);
+ goto RE_RSV_INFO_EXT;
+ }
+ i = (rsv_info->size + mtd->writesize - 1) / mtd->writesize;
+ rsv_info->nvalid->page_addr -= (i - 1);
+ }
+ if (rsv_info->valid != 1)
+ ret = -1;
+ offset = rsv_info->nvalid->blk_addr;
+ offset *= mtd->erasesize;
+ offset += rsv_info->nvalid->page_addr * mtd->writesize;
+ pr_info("%s valid address 0x%llx\n", rsv_info->name, offset);
+ return ret;
+}
+
+int meson_rsv_check(struct meson_rsv_info_t *rsv_info)
+{
+ int ret = 0;
+
+ ret = meson_rsv_scan(rsv_info);
+ if (ret)
+ pr_info("%s %d %s info check failed ret %d\n",
+ __func__, __LINE__, rsv_info->name, ret);
+ if (!rsv_info->valid) {
+ pr_info("%s %d no %s info exist\n",
+ __func__, __LINE__, rsv_info->name);
+ ret = 1;
+ }
+ return ret;
+}
+
+int meson_rsv_init(struct mtd_info *mtd,
+ struct meson_rsv_handler_t *handler)
+{
+ int i, ret = 0;
+ u32 pages_per_blk_shift, start, vernier;
+ enum boot_type_e medium_type = store_get_type();
+
+ pages_per_blk_shift = mtd->erasesize_shift - mtd->writesize_shift;
+ start = BOOT_TOTAL_PAGES >> pages_per_blk_shift;
+ start += NAND_GAP_BLOCK_NUM;
+ vernier = start;
+ handler->fn_bitmask = 0;
+ for (i = 0; i < NAND_RSV_BLOCK_NUM; i++) {
+ handler->free_node[i] =
+ kzalloc(sizeof(struct free_node_t), GFP_KERNEL);
+ if (!handler->free_node[i]) {
+ ret = -ENOMEM;
+ goto error0;
+ }
+ memset(handler->free_node[i], 0, sizeof(struct free_node_t));
+ handler->free_node[i]->index = i;
+ }
+
+ handler->bbt =
+ kzalloc(sizeof(*handler->bbt), GFP_KERNEL);
+ if (!handler->bbt) {
+ ret = -ENOMEM;
+ goto error0;
+ }
+ handler->bbt->nvalid =
+ kzalloc(sizeof(*handler->bbt->nvalid), GFP_KERNEL);
+ if (!handler->bbt->nvalid) {
+ ret = -ENOMEM;
+ goto error1;
+ }
+ handler->bbt->mtd = mtd;
+ handler->bbt->start = vernier;
+ handler->bbt->end = vernier + NAND_BBT_BLOCK_NUM;
+ handler->bbt->nvalid->blk_addr = -1;
+ handler->bbt->size = mtd->size >> mtd->erasesize_shift;
+ handler->bbt->handler = handler;
+ memcpy(handler->bbt->name, BBT_NAND_MAGIC, 4);
+ vernier += NAND_BBT_BLOCK_NUM;
+#ifndef CONFIG_ENV_IS_IN_NAND
+ handler->env =
+ kzalloc(sizeof(*handler->env), GFP_KERNEL);
+ if (!handler->env) {
+ ret = -ENOMEM;
+ goto error2;
+ }
+ handler->env->nvalid =
+ kzalloc(sizeof(*handler->env->nvalid), GFP_KERNEL);
+ if (!handler->env->nvalid) {
+ ret = -ENOMEM;
+ goto error3;
+ }
+ handler->env->mtd = mtd;
+ handler->env->start = vernier;
+ handler->env->end = vernier + NAND_ENV_BLOCK_NUM;
+ handler->env->nvalid->blk_addr = -1;
+ handler->env->size = CONFIG_ENV_SIZE;
+ handler->env->handler = handler;
+ memcpy(handler->env->name, ENV_NAND_MAGIC, 4);
+ vernier += NAND_ENV_BLOCK_NUM;
+#endif
+ handler->key =
+ kzalloc(sizeof(*handler->key), GFP_KERNEL);
+ if (!handler->key) {
+ ret = -ENOMEM;
+ goto error4;
+ }
+ handler->key->nvalid =
+ kzalloc(sizeof(*handler->key->nvalid), GFP_KERNEL);
+ if (!handler->key->nvalid) {
+ ret = -ENOMEM;
+ goto error5;
+ }
+ handler->key->mtd = mtd;
+ handler->key->start = vernier;
+ handler->key->end = vernier + NAND_KEY_BLOCK_NUM;
+ handler->key->nvalid->blk_addr = -1;
+ handler->key->size = 0;
+ handler->key->handler = handler;
+ memcpy(handler->key->name, KEY_NAND_MAGIC, 4);
+ vernier += NAND_KEY_BLOCK_NUM;
+
+ handler->dtb =
+ kzalloc(sizeof(*handler->dtb), GFP_KERNEL);
+ if (!handler->dtb) {
+ ret = -ENOMEM;
+ goto error6;
+ }
+ handler->dtb->nvalid =
+ kzalloc(sizeof(*handler->dtb->nvalid), GFP_KERNEL);
+ if (!handler->dtb->nvalid) {
+ ret = -ENOMEM;
+ goto error7;
+ }
+ handler->dtb->mtd = mtd;
+ handler->dtb->start = vernier;
+ handler->dtb->end = vernier + NAND_DTB_BLOCK_NUM;
+ handler->dtb->nvalid->blk_addr = -1;
+ handler->dtb->size = 0;
+ handler->dtb->handler = handler;
+ memcpy(handler->dtb->name, DTB_NAND_MAGIC, 4);
+ vernier += NAND_DTB_BLOCK_NUM;
+
+ handler->ddr_para =
+ kzalloc(sizeof(*handler->ddr_para), GFP_KERNEL);
+ if (!handler->ddr_para) {
+ ret = -ENOMEM;
+ goto error8;
+ }
+ handler->ddr_para->nvalid =
+ kzalloc(sizeof(*handler->ddr_para->nvalid), GFP_KERNEL);
+ if (!handler->ddr_para->nvalid) {
+ ret = -ENOMEM;
+ goto error9;
+ }
+ handler->ddr_para->mtd = mtd;
+ handler->ddr_para->start = vernier;
+ handler->ddr_para->end = vernier + NAND_DDR_BLOCK_NUM;
+ handler->ddr_para->nvalid->blk_addr = -1;
+ handler->ddr_para->size = DDR_PARA_SIZE;
+ handler->ddr_para->handler = handler;
+ memcpy(handler->ddr_para->name, DDR_NAND_MAGIC, 4);
+ vernier += NAND_DDR_BLOCK_NUM;
+
+ if (mtd->erasesize < 0x40000) {
+ handler->key->size = mtd->erasesize >> 2;
+ /* reduce memory usage in sram */
+ handler->dtb->size = mtd->erasesize >> 1;
+ } else {
+ if (BOOT_SNAND == medium_type) {
+ /* Reduce space use, malloc may fail */
+ handler->key->size = mtd->erasesize >> 2;
+ handler->dtb->size = mtd->erasesize >> 2;
+ } else {
+ handler->key->size = 0x40000;
+ handler->dtb->size = 0x40000;
+ }
+ }
+
+ if ((vernier - start) > NAND_RSV_BLOCK_NUM) {
+ pr_info("ERROR: total blk number is over the limit\n");
+ ret = -ENOMEM;
+ goto error10;
+ }
+ rsv_handler = handler;
+
+ printf("bbt_start=%d, size:0x%x\n", handler->bbt->start,handler->bbt->size);
+#ifndef CONFIG_ENV_IS_IN_NAND
+ printf("env_start=%d, size:0x%x\n", handler->env->start,handler->env->size);
+#endif
+ printf("key_start=%d, size:0x%x\n", handler->key->start,handler->key->size);
+ printf("dtb_start=%d, size:0x%x\n", handler->dtb->start,handler->dtb->size);
+ printf("ddr_start=%d, size:0x%x\n", handler->ddr_para->start,
+ handler->ddr_para->size);
+
+ return ret;
+
+error10:
+ kfree(handler->ddr_para->nvalid);
+ handler->ddr_para->nvalid = NULL;
+error9:
+ kfree(handler->ddr_para);
+ handler->ddr_para = NULL;
+error8:
+ kfree(handler->dtb->nvalid);
+ handler->dtb->nvalid = NULL;
+error7:
+ kfree(handler->dtb);
+ handler->dtb = NULL;
+error6:
+ kfree(handler->key->nvalid);
+ handler->key->nvalid = NULL;
+error5:
+ kfree(handler->key);
+ handler->key = NULL;
+#ifndef CONFIG_ENV_IS_IN_NAND
+error4:
+ kfree(handler->env->nvalid);
+ handler->env->nvalid = NULL;
+error3:
+ kfree(handler->env);
+ handler->env = NULL;
+#endif
+error2:
+ kfree(handler->bbt->nvalid);
+ handler->bbt->nvalid = NULL;
+error1:
+ kfree(handler->bbt);
+ handler->bbt = NULL;
+
+error0:
+ for (i = 0; i < NAND_RSV_BLOCK_NUM; i++) {
+ kfree(handler->free_node[i]);
+ handler->free_node[i] = NULL;
+ }
+
+ return ret;
+}
+
+int meson_rsv_bbt_read(u_char *dest, size_t size)
+{
+ u_char *temp;
+ size_t len;
+ int ret;
+
+ if (!rsv_handler ||
+ !rsv_handler->bbt) {
+ pr_info("%s %d %s not inited yet!\n",
+ __func__, __LINE__,
+ rsv_handler->bbt->name);
+ return 1;
+ }
+
+ if (!rsv_handler->bbt->valid) {
+ pr_info("%s, %d, %s invalid!, read exit!\n",
+ __func__, __LINE__,
+ rsv_handler->bbt->name);
+ return RSV_UNVAIL;
+ }
+ if (!dest || size == 0) {
+ pr_info("%s %d parameter error %p %ld\n",
+ __func__, __LINE__, dest, size);
+ return 1;
+ }
+ len = rsv_handler->bbt->size;
+ temp = kzalloc(len, GFP_KERNEL);
+ if (!temp) {
+ pr_err("%s %d kzalloc fail size = %ld\n",
+ __func__, __LINE__, len);
+ return -ENOMEM;
+ }
+ memset(temp, 0, len);
+ ret = meson_rsv_read(rsv_handler->bbt, temp);
+ memcpy(dest, temp, len > size ? size : len);
+ pr_info("%s %d read 0x%lx bytes from bbt, ret %d\n",
+ __func__, __LINE__, len > size ? size : len, ret);
+ kfree(temp);
+ return ret;
+}
+
+int meson_rsv_key_read(u_char *dest, size_t size)
+{
+ u_char *temp;
+ size_t len;
+ int ret;
+
+ if (!rsv_handler ||
+ !rsv_handler->key) {
+ pr_info("%s %d %s not inited yet!\n",
+ __func__, __LINE__,
+ rsv_handler->key->name);
+ return 1;
+ }
+
+ if (!rsv_handler->key->valid) {
+ pr_info("%s, %d, %s invalid!, read exit!\n",
+ __func__, __LINE__,
+ rsv_handler->key->name);
+ return RSV_UNVAIL;
+ }
+ if (!dest || size == 0) {
+ pr_info("%s %d parameter error %p %ld\n",
+ __func__, __LINE__, dest, size);
+ return 1;
+ }
+ len = rsv_handler->key->size;
+ temp = kzalloc(len, GFP_KERNEL);
+ if (!temp) {
+ pr_err("%s %d kzalloc fail size = 0x%lx\n",
+ __func__, __LINE__, len);
+ return -ENOMEM;
+ }
+ memset(temp, 0, len);
+ ret = meson_rsv_read(rsv_handler->key, temp);
+ memcpy(dest, temp, len > size ? size : len);
+ pr_info("%s %d read 0x%lx bytes from key, ret %d\n",
+ __func__, __LINE__, len > size ? size : len, ret);
+ kfree(temp);
+ return ret;
+}
+
+int meson_rsv_ddr_para_read(u_char *dest, size_t size)
+{
+ u_char *temp;
+ size_t len;
+ int ret;
+
+ if (!rsv_handler ||
+ !rsv_handler->ddr_para) {
+ pr_info("%s %d %s not inited yet!\n",
+ __func__, __LINE__,
+ rsv_handler->ddr_para->name);
+ return 1;
+ }
+
+ if (!rsv_handler->ddr_para->valid) {
+ pr_info("%s, %d, %s invalid!, read exit!\n",
+ __func__, __LINE__,
+ rsv_handler->ddr_para->name);
+ return RSV_UNVAIL;
+ }
+ if (!dest || size == 0) {
+ pr_info("%s %d parameter error %p %ld\n",
+ __func__, __LINE__, dest, size);
+ return 1;
+ }
+ len = rsv_handler->ddr_para->size;
+ temp = kzalloc(len, GFP_KERNEL);
+ if (!temp) {
+ pr_err("%s %d kzalloc fail size = 0x%lx\n",
+ __func__, __LINE__, len);
+ return -ENOMEM;
+ }
+ memset(temp, 0, len);
+ ret = meson_rsv_read(rsv_handler->ddr_para, temp);
+ memcpy(dest, temp, len > size ? size : len);
+ pr_info("%s %d read 0x%lx bytes from ddr_para, ret %d\n",
+ __func__, __LINE__, len > size ? size : len, ret);
+ kfree(temp);
+ return ret;
+}
+
+int meson_rsv_env_read(u_char *dest, size_t size)
+{
+ u_char *temp;
+ size_t len;
+ int ret;
+
+ if (!rsv_handler ||
+ !rsv_handler->env) {
+ pr_info("%s %d %s not inited yet!\n",
+ __func__, __LINE__,
+ rsv_handler->env->name);
+ return 1;
+ }
+ if (!rsv_handler->env->valid) {
+ pr_info("%s, %d, %s invalid!, read exit!\n",
+ __func__, __LINE__,
+ rsv_handler->env->name);
+ return RSV_UNVAIL;
+ }
+ if (!dest || size == 0) {
+ pr_info("%s %d parameter error %p %ld\n",
+ __func__, __LINE__, dest, size);
+ return 1;
+ }
+ len = rsv_handler->env->size;
+ temp = kzalloc(len, GFP_KERNEL);
+ if (!temp) {
+ pr_err("%s %d kzalloc fail size = 0x%lx\n",
+ __func__, __LINE__, len);
+ return -ENOMEM;
+ }
+ memset(temp, 0, len);
+ ret = meson_rsv_read(rsv_handler->env, temp);
+ memcpy(dest, temp, len > size ? size : len);
+ pr_info("%s %d read 0x%lx bytes from env, ret %d\n",
+ __func__, __LINE__, len > size ? size : len, ret);
+ kfree(temp);
+ return ret;
+}
+
+int meson_rsv_dtb_read(u_char *dest, size_t size)
+{
+ u_char *temp;
+ size_t len;
+ int ret;
+
+ if (!rsv_handler ||
+ !rsv_handler->dtb) {
+ pr_info("%s %d rsv info %s not inited yet!\n",
+ __func__, __LINE__,
+ rsv_handler->dtb->name);
+ return 1;
+ }
+ if (!rsv_handler->dtb->valid) {
+ pr_info("%s, %d, %s invalid!, read exit!\n",
+ __func__, __LINE__,
+ rsv_handler->dtb->name);
+ return RSV_UNVAIL;
+ }
+ if (!dest || size == 0) {
+ pr_info("%s %d parameter error %p %ld\n",
+ __func__, __LINE__, dest, size);
+ return 1;
+ }
+ len = rsv_handler->dtb->size;
+ temp = kzalloc(len, GFP_KERNEL);
+ if (!temp) {
+ pr_err("%s %d kzalloc fail size = 0x%lx\n",
+ __func__, __LINE__, len);
+ return -ENOMEM;
+ }
+ memset(temp, 0, len);
+ ret = meson_rsv_read(rsv_handler->dtb, temp);
+ memcpy(dest, temp, len > size ? size : len);
+ pr_info("%s %d read 0x%lx bytes from dtb, ret %d\n",
+ __func__, __LINE__, len > size ? size : len, ret);
+ kfree(temp);
+ return ret;
+}
+
+/*update bbt*/
+int meson_rsv_bbt_write(u_char *source, size_t size)
+{
+ u_char *temp;
+ size_t len;
+ int ret;
+
+ if (!rsv_handler ||
+ !rsv_handler->bbt) {
+ pr_info("%s %d rsv info not inited yet!\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ if (!source || size == 0) {
+ pr_info("%s %d parameter error %p %ld\n",
+ __func__, __LINE__, source, size);
+ return 1;
+ }
+ len = rsv_handler->bbt->size;
+ temp = kzalloc(len, GFP_KERNEL);
+ if (!temp) {
+ pr_err("%s %d kzalloc fail size = 0x%lx\n",
+ __func__, __LINE__, len);
+ return -ENOMEM;
+ }
+ memset(temp, 0, len);
+ memcpy(temp, source, len > size ? size : len);
+ ret = meson_rsv_save(rsv_handler->bbt, temp);
+ pr_info("%s %d write 0x%lx bytes to bbt, ret %d\n",
+ __func__, __LINE__, len > size ? size : len, ret);
+ kfree(temp);
+ return ret;
+}
+
+int meson_rsv_key_write(u_char *source, size_t size)
+{
+ u_char *temp;
+ size_t len;
+ int ret;
+
+ if (!rsv_handler ||
+ !rsv_handler->key) {
+ pr_info("%s %d rsv info not inited yet!\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ if (!source || size == 0) {
+ pr_info("%s %d parameter error %p %ld\n",
+ __func__, __LINE__, source, size);
+ return 1;
+ }
+ len = rsv_handler->key->size;
+ temp = kzalloc(len, GFP_KERNEL);
+ if (!temp) {
+ pr_err("%s %d kzalloc fail size = 0x%lx\n",
+ __func__, __LINE__, len);
+ return -ENOMEM;
+ }
+ memset(temp, 0, len);
+ memcpy(temp, source, len > size ? size : len);
+ ret = meson_rsv_save(rsv_handler->key, temp);
+ pr_info("%s %d write 0x%lx bytes to key, ret %d\n",
+ __func__, __LINE__, len > size ? size : len, ret);
+ kfree(temp);
+ return ret;
+}
+
+int meson_rsv_ddr_para_write(u_char *source, size_t size)
+{
+ u_char *temp;
+ size_t len;
+ int ret;
+
+ if (!rsv_handler ||
+ !rsv_handler->ddr_para) {
+ pr_info("%s %d rsv info not inited yet!\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ if (!source || size == 0) {
+ pr_info("%s %d parameter error %p %ld\n",
+ __func__, __LINE__, source, size);
+ return 1;
+ }
+ len = rsv_handler->ddr_para->size;
+ temp = kzalloc(len, GFP_KERNEL);
+ if (!temp) {
+ pr_err("%s %d kzalloc fail size = 0x%lx\n",
+ __func__, __LINE__, len);
+ return -ENOMEM;
+ }
+ memset(temp, 0, len);
+ memcpy(temp, source, len > size ? size : len);
+ ret = meson_rsv_save(rsv_handler->ddr_para, temp);
+ pr_info("%s %d write 0x%lx bytes to key, ret %d\n",
+ __func__, __LINE__, len > size ? size : len, ret);
+ kfree(temp);
+ return ret;
+}
+
+
+int meson_rsv_env_write(u_char *source, size_t size)
+{
+ u_char *temp;
+ size_t len;
+ int ret;
+
+ if (!rsv_handler ||
+ !rsv_handler->env) {
+ pr_info("%s %d rsv info has not inited yet!\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ if (!source || size == 0) {
+ pr_info("%s %d parameter error %p %ld\n",
+ __func__, __LINE__, source, size);
+ return 1;
+ }
+ len = rsv_handler->env->size;
+ temp = kzalloc(len, GFP_KERNEL);
+ if (!temp) {
+ pr_err("%s %d kzalloc fail size = 0x%lx\n",
+ __func__, __LINE__, len);
+ return -ENOMEM;
+ }
+ memset(temp, 0, len);
+ memcpy(temp, source, len > size ? size : len);
+ ret = meson_rsv_save(rsv_handler->env, temp);
+ pr_info("%s %d write 0x%lx bytes to env, ret %d\n",
+ __func__, __LINE__, len > size ? size : len, ret);
+ kfree(temp);
+ return ret;
+}
+
+int meson_rsv_dtb_write(u_char *source, size_t size)
+{
+ u_char *temp;
+ size_t len;
+ int ret;
+
+ if (!rsv_handler ||
+ !rsv_handler->dtb) {
+ pr_info("%s %d rsv info has not inited yet!\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ if (!source || size == 0) {
+ pr_info("%s %d parameter error %p %ld\n",
+ __func__, __LINE__, source, size);
+ return 1;
+ }
+ len = rsv_handler->dtb->size;
+ temp = kzalloc(len, GFP_KERNEL);
+ if (!temp) {
+ pr_err("%s %d kzalloc fail size = 0x%lx\n",
+ __func__, __LINE__, len);
+ return -ENOMEM;
+ }
+ memset(temp, 0, len);
+ memcpy(temp, source, len > size ? size : len);
+ ret = meson_rsv_save(rsv_handler->dtb, temp);
+ pr_info("%s %d write 0x%lx bytes to dtb, ret %d\n",
+ __func__, __LINE__, len > size ? size : len, ret);
+ kfree(temp);
+ return ret;
+}
+
+u32 meson_rsv_bbt_size(void)
+{
+ if (!rsv_handler ||
+ !rsv_handler->bbt) {
+ pr_info("%s %d rsv info has not inited yet!\n",
+ __func__, __LINE__);
+ return 0;
+ }
+ return rsv_handler->bbt->size;
+}
+
+u32 meson_rsv_key_size(void)
+{
+ if (!rsv_handler ||
+ !rsv_handler->key) {
+ pr_info("%s %d rsv info has not inited yet!\n",
+ __func__, __LINE__);
+ return 0;
+ }
+ return rsv_handler->key->size;
+}
+
+u32 meson_rsv_ddr_para_size(void)
+{
+ if (!rsv_handler ||
+ !rsv_handler->ddr_para) {
+ pr_info("%s %d rsv info has not inited yet!\n",
+ __func__, __LINE__);
+ return 0;
+ }
+ return rsv_handler->ddr_para->size;
+}
+
+
+u32 meson_rsv_env_size(void)
+{
+ if (!rsv_handler ||
+ !rsv_handler->env) {
+ pr_info("%s %d rsv info has not inited yet!\n",
+ __func__, __LINE__);
+ return 0;
+ }
+ return rsv_handler->env->size;
+}
+
+u32 meson_rsv_dtb_size(void)
+{
+ if (!rsv_handler ||
+ !rsv_handler->dtb) {
+ pr_info("%s %d rsv info has not inited yet!\n",
+ __func__, __LINE__);
+ return 0;
+ }
+ return rsv_handler->dtb->size;
+}
+
+int meson_rsv_bbt_erase(void)
+{
+ if (!rsv_handler ||
+ !rsv_handler->bbt) {
+ pr_info("%s %d rsv info has not inited yet!\n",
+ __func__, __LINE__);
+ return 1;
+ }
+
+ if (rsv_handler->bbt->valid) {
+ return meson_rsv_erase(rsv_handler->bbt);
+ }
+ return 0;
+}
+
+int meson_rsv_key_erase(void)
+{
+ if (!rsv_handler ||
+ !rsv_handler->key) {
+ pr_info("%s %d rsv info has not inited yet!\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ if (rsv_handler->key->valid) {
+ return meson_rsv_erase(rsv_handler->key);
+ }
+ return 0;
+}
+
+int meson_rsv_ddr_para_erase(void)
+{
+ if (!rsv_handler ||
+ !rsv_handler->ddr_para) {
+ pr_info("%s %d rsv info has not inited yet!\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ if (rsv_handler->ddr_para->valid) {
+ return meson_rsv_erase(rsv_handler->ddr_para);
+ }
+ return 0;
+}
+
+
+int meson_rsv_env_erase(void)
+{
+ if (!rsv_handler ||
+ !rsv_handler->env) {
+ pr_info("%s %d rsv info has not inited yet!\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ if (rsv_handler->env->valid) {
+ return meson_rsv_erase(rsv_handler->env);
+ }
+ return 0;
+}
+
+int meson_rsv_dtb_erase(void)
+{
+ if (!rsv_handler ||
+ !rsv_handler->dtb) {
+ pr_info("%s %d rsv info has not inited yet!\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ if (rsv_handler->dtb->valid) {
+ return meson_rsv_erase(rsv_handler->dtb);
+ }
+ return 0;
+
+}
diff --git a/drivers/mtd/aml_storage.c b/drivers/mtd/aml_storage.c
index 28654a4..fb973b7 100644
--- a/drivers/mtd/aml_storage.c
+++ b/drivers/mtd/aml_storage.c
@@ -1,11 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * mtd adaptive to storage interface module
- *
- * Copyright (C) 2018 Amlogic Corporation
- *
- * Licensed under the GPL-2 or later.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -19,6 +14,7 @@
#include <amlogic/storage.h>
#include <amlogic/aml_mtd.h>
#include <amlogic/aml_rsv.h>
+#include <amlogic/cpu_id.h>
#include <asm/arch/cpu_config.h>
#include <partition_table.h>
#include <time.h>
@@ -31,53 +27,82 @@
u16 valid_max;
u8 init_flag;
};
-
-static struct map_handler_t mtd_map;
static struct mtd_info *mtd_store_list[MAX_MTD_CNT];
extern int info_disprotect;
+extern struct storage_startup_parameter g_ssp;
-static inline struct mtd_info *mtd_store_get(int dev)
+struct mtd_info *mtd_store_get(int dev)
{
-#if defined(CONFIG_SPI_FLASH) || defined(CONFIG_SPI_NAND)
- return mtd_store_list[0];
-#else
- return mtd_store_list[dev];
-#endif
+ enum boot_type_e medium_type = store_get_type();
+
+ if ((medium_type == BOOT_SNAND) || (medium_type == BOOT_SNOR))
+ return mtd_store_list[0];
+ else if (medium_type == BOOT_NAND_MTD)
+ return mtd_store_list[dev];
+ else
+ return NULL;
+
}
-#ifndef CONFIG_DISCRETE_BOOTLOADER
static u8 boot_num_get(void)
{
/* TODO get from page0, if page0 0xff, return 1 */
return 1;
}
+
+int get_meson_mtd_partition_table(struct mtd_partition **partitions)
+{
+#if defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND) || defined(CONFIG_MESON_NFC) || defined(CONFIG_SPI_FLASH)
+ enum boot_type_e medium_type = store_get_type();
#endif
+ int mtdParts = -1;
+
+#ifdef CONFIG_MESON_NFC
+ extern struct mtd_partition *get_aml_mtd_partition(void);
+ extern int get_aml_partition_count(void);
+ if (BOOT_NAND_MTD == medium_type) {
+ mtdParts = get_aml_partition_count();
+ *partitions = get_aml_mtd_partition();
+ }
+#endif
+#if defined(CONFIG_SPI_NAND) || defined(CONFIG_MTD_SPI_NAND)
+ extern const struct mtd_partition *get_spinand_partition_table(int *partitions);
+ if (BOOT_SNAND == medium_type)
+ *partitions = (struct mtd_partition *)get_spinand_partition_table(&mtdParts);
+#endif
+#ifdef CONFIG_SPI_FLASH
+ extern const struct mtd_partition *get_spiflash_partition_table(int *partitions);
+ if (medium_type == BOOT_SNOR)
+ *partitions = (struct mtd_partition *)get_spiflash_partition_table(&mtdParts);
+#endif
+ return mtdParts;
+}
static struct mtd_info *mtd_store_get_by_name(const char *part_name,
int boot)
{
- if (!strcmp(part_name, BOOT_LOADER) ||
- !strcmp(part_name, BOOT_BL2) ||
- !strcmp(part_name, BOOT_SPL)) {
- return mtd_store_get(0);
- } else if (!strcmp(part_name, BOOT_TPL) ||
- !strcmp(part_name, BOOT_FIP)) {
- return mtd_store_get(1);
- } else if (boot) {
- pr_info("%s %d invalid name: %s\n",
- __func__, __LINE__, part_name);
- return ERR_PTR(-ENXIO);
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER) {
+ if (!strcmp(part_name, BOOT_BL2) ||
+ !strcmp(part_name, BOOT_SPL))
+ return mtd_store_get(0);
+ } else {
+ if (!strcmp(part_name, BOOT_LOADER))
+ return mtd_store_get(0);
}
+
return mtd_store_get(1);
}
void mtd_store_set(struct mtd_info *mtd, int dev)
{
-#if defined(CONFIG_SPI_FLASH) || defined(CONFIG_SPI_NAND)
- mtd_store_list[0] = mtd;
-#else
- mtd_store_list[dev] = mtd;
-#endif
+ enum boot_type_e medium_type = store_get_type();
+
+ if ((medium_type == BOOT_SNAND) || (medium_type == BOOT_SNOR))
+ mtd_store_list[0] = mtd;
+ else if (medium_type == BOOT_NAND_MTD)
+ mtd_store_list[dev] = mtd;
+ else
+ pr_info("unsupport boot device\n");
}
#ifdef CONFIG_CMD_NAND_TRIMFFS
@@ -371,25 +396,6 @@
return 0;
}
-static loff_t mtd_store_ltop(loff_t off)
-{
- struct mtd_info *mtd = mtd_store_get(1);
- loff_t remainder = off % mtd->erasesize;
- u16 logic_blk = off / mtd->erasesize;
-
- if (!mtd_map.init_flag) {
- pr_info("%s %d error: no valid map handler\n",
- __func__, __LINE__);
- return (loff_t)-1;
- }
- if (logic_blk > mtd_map.valid_max) {
- pr_info("%s %d error: over valid address\n",
- __func__, __LINE__);
- return (loff_t)-1;
- }
- return (mtd_map.map[logic_blk] * mtd->erasesize) + remainder;
-}
-
static size_t mtd_store_logic_part_size(struct mtd_info *mtd,
struct part_info *part)
{
@@ -405,89 +411,33 @@
return part->size - cnt * mtd->erasesize;
}
-void mtd_store_init_map(void)
-{
- struct mtd_info *mtd = mtd_store_get(1);
- u16 blk_cnt = 0, skip = 0, page_per_blk = 0;
- int i, j = 0;
-
- if (mtd->erasesize)
- blk_cnt = mtd->size / mtd->erasesize;
- else
- pr_info("%s %d can not calculate block cnt\n",
- __func__, __LINE__);
-
- printf("%s %d block cnt: 0x%x\n",
- __func__, __LINE__, blk_cnt);
- page_per_blk = mtd->erasesize / mtd->writesize;
- skip = BOOT_TOTAL_PAGES / page_per_blk;
- skip += NAND_RSV_BLOCK_NUM;
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- skip += ((CONFIG_TPL_SIZE_PER_COPY * CONFIG_TPL_COPY_NUM +
- mtd->erasesize - 1) / mtd->erasesize);
-#endif
- mtd_map.map = (u16 *)malloc(sizeof(u16) * blk_cnt);
- for (i = 0; i < blk_cnt; i++) {
- if (mtd_block_isbad(mtd, i * mtd->erasesize) &&
- i >= skip)
- continue;
- else
- mtd_map.map[j++] = i;
- }
- mtd_map.valid_max = j;
- mtd_map.init_flag = 1;
- pr_info("%s %d: skipped %d, bad block need re-map: %d\n",
- __func__, __LINE__, skip, blk_cnt - j);
-}
-
-static int mtd_store_get_offset(const char *partname,
- loff_t *retoff, loff_t off)
+static int mtd_store_get_offset(const char *partname, loff_t *retoff, loff_t off)
{
int ret = 0;
loff_t offset;
#if defined(CONFIG_CMD_MTDPARTS)
- u8 pnum;
struct mtd_device *dev;
struct part_info *part;
+ char tmp_part_name[20] = {0};
+ u8 pnum;
#endif
+
*retoff = 0;
- if (!partname) {
+ if (!partname)
offset = off;
- }
+
#if defined(CONFIG_CMD_MTDPARTS)
else if (!mtdparts_init()) {
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- if (!strcmp(partname, BOOT_LOADER) ||
- !strcmp(partname, BOOT_BL2) ||
- !strcmp(partname, BOOT_SPL)) {
- ret = find_dev_and_part(BOOT_LOADER,
- &dev,
- &pnum,
- &part);
- if (ret)
- return ret; /* avoid operates null pointer */
- *retoff = part->offset + off;
- return 0;
+ strncpy(tmp_part_name, partname, strlen(partname));
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER) {
+ if (!strcmp(partname, BOOT_BL2) ||
+ !strcmp(partname, BOOT_SPL))
+ strncpy(tmp_part_name, BOOT_LOADER, strlen(BOOT_LOADER));
}
- if (!strcmp(partname, BOOT_TPL) ||
- !strcmp(partname, BOOT_FIP)) {
- ret = find_dev_and_part(BOOT_TPL,
- &dev,
- &pnum,
- &part);
- if (ret)
- return ret;
- *retoff = part->offset + off;
- return 0;
- }
-#endif
- ret = find_dev_and_part(partname,
- &dev,
- &pnum,
- &part);
+ ret = find_dev_and_part(tmp_part_name, &dev, &pnum, &part);
if (ret) {
- pr_info("%s %d can not find part:%s",
- __func__, __LINE__, partname);
+ pr_info("%s %d can not find part:%s\n",
+ __func__, __LINE__, tmp_part_name);
ret = -EINVAL;
}
offset = part->offset + off;
@@ -498,42 +448,63 @@
__func__, __LINE__);
offset = off;
}
+
if (!ret)
*retoff = offset;
+
+ return ret;
+}
+
+extern int get_aml_mtdpart_count(void);
+static int mtd_store_count(void)
+{
+ mtdparts_init();
+ return get_aml_mtdpart_count();
+}
+
+extern int get_aml_mtdpart_name(struct mtd_info *master, int idx, char *name);
+static int mtd_store_name(int idx, char *partname)
+{
+ int ret = 0;
+ struct mtd_info *mtd = mtd_store_get(1);
+
+ if (idx >= mtd_store_count())
+ return -1;
+ ret = get_aml_mtdpart_name(mtd, idx, partname);
+
return ret;
}
static u64 mtd_store_size(const char *part_name)
{
struct mtd_info *mtd = mtd_store_get(1);
-
- if (!part_name)
- return mtd->size;
-#ifndef CONFIG_CMD_MTDPARTS
- if (!strcmp(part_name, BOOT_LOADER))
- mtd = mtd_store_get(0);
- else
- pr_info("no partition, whole device size\n");
- return mtd->size;
-#else
+ char tmp_part_name[20] = {0};
u8 pnum;
struct mtd_device *dev;
struct part_info *part;
int ret;
+ if (!part_name)
+ return mtd->size;
+
if (!mtdparts_init()) {
- ret = find_dev_and_part(part_name,
+ strncpy(tmp_part_name, part_name, strlen(part_name));
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER) {
+ if (!strcmp(part_name, BOOT_BL2) ||
+ !strcmp(part_name, BOOT_SPL))
+ strncpy(tmp_part_name, BOOT_LOADER, strlen(BOOT_LOADER));
+ }
+ ret = find_dev_and_part(tmp_part_name,
&dev,
&pnum,
&part);
if (ret) {
- pr_info("%s %d can not find part:%s",
- __func__, __LINE__, part_name);
+ pr_info("%s %d can not find part:%s\n",
+ __func__, __LINE__, tmp_part_name);
return 0;
}
return mtd_store_logic_part_size(mtd, part);
}
-#endif
return 0;
}
@@ -544,21 +515,28 @@
loff_t offset = 0;
size_t retlen = 0;
int ret;
+ u8 backup_num = 0;
+ enum boot_type_e medium_type = store_get_type();
+
ret = mtd_store_get_offset((const char *)part_name, &offset, off);
if (ret)
return ret;
if (!part_name) {/*normal area except tpl*/
offset = off;
- off += BOOT_TOTAL_PAGES * mtd->writesize;
- off += NAND_RSV_BLOCK_NUM * mtd->erasesize;
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- off += CONFIG_TPL_SIZE_PER_COPY * CONFIG_TPL_COPY_NUM;
-#endif
+ offset += BOOT_TOTAL_PAGES * mtd->writesize;
+ offset += NAND_RSV_BLOCK_NUM * mtd->erasesize;
+
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER) {
+ if (BOOT_NAND_MTD == medium_type ||
+ BOOT_SNAND == medium_type)
+ backup_num = CONFIG_NAND_TPL_COPY_NUM;
+ else if (medium_type == BOOT_SNOR)
+ backup_num = CONFIG_NOR_TPL_COPY_NUM;
+
+ offset += CONFIG_TPL_SIZE_PER_COPY * backup_num;
+ }
}
-
- offset = mtd_store_ltop(offset);
-
ret = mtd_store_read_skip_bad(mtd, offset, &size,
&retlen, mtd->size, (u_char *)dest);
if (ret) {
@@ -566,7 +544,7 @@
__func__, __LINE__, ret);
return ret;
}
- if (retlen != size) {
+ if (retlen < size) {
ret = -EIO;
pr_info("%s %d mtd read err, size(%ld), retlen(%ld)\n",
__func__, __LINE__, size, retlen);
@@ -582,20 +560,25 @@
loff_t offset = 0;
size_t retlen = 0;
int ret;
+ enum boot_type_e medium_type = store_get_type();
ret = mtd_store_get_offset((const char *)part_name, &offset, off);
if (ret)
return ret;
if (!part_name) {/*normal area except tpl*/
offset = off;
- off += BOOT_TOTAL_PAGES * mtd->writesize;
- off += NAND_RSV_BLOCK_NUM * mtd->erasesize;
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- off += CONFIG_TPL_SIZE_PER_COPY * CONFIG_TPL_COPY_NUM;
-#endif
+ offset += BOOT_TOTAL_PAGES * mtd->writesize;
+ offset += NAND_RSV_BLOCK_NUM * mtd->erasesize;
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER) {
+ if (BOOT_NAND_MTD == medium_type ||
+ BOOT_SNAND == medium_type)
+ offset += CONFIG_TPL_SIZE_PER_COPY *
+ CONFIG_NAND_TPL_COPY_NUM;
+ else if (medium_type == BOOT_SNOR)
+ offset += CONFIG_TPL_SIZE_PER_COPY *
+ CONFIG_NOR_TPL_COPY_NUM;
+ }
}
- offset = mtd_store_ltop(offset);
-
ret = mtd_store_write_skip_bad(mtd, offset, &size,
&retlen, mtd->size, (u_char *)source, 0);
if (ret) {
@@ -603,7 +586,7 @@
__func__, __LINE__, ret);
return ret;
}
- if (retlen != size) {
+ if (retlen < size) {
ret = -EIO;
pr_info("%s %d mtd write err, size(%ld), retlen(%ld)\n",
__func__, __LINE__, size, retlen);
@@ -617,13 +600,18 @@
{
struct mtd_info *mtd;
loff_t offset = 0;
- unsigned long erased_size, erase_len;
+ unsigned long erased_size, erase_len, chip_size;
struct erase_info info;
int ret;
+ /* Record the current chip size first */
+ mtd = mtd_store_get(1);
+ chip_size = mtd->size;
+
+ /*part_name=NULL,operation target is whole device*/
if (!part_name) {
mtd = mtd_store_get(1);
- printf("!!!warn: erase all chip\n");
+ printf("!!!warn: erase all chip!!!\n");
size = mtd->size;
mtd = mtd_store_get(0);
}
@@ -635,70 +623,103 @@
ret = mtd_store_get_offset((const char *)part_name, &offset, off);
if (ret)
return ret;
- offset = mtd_store_ltop(offset);
+ if (size == 0)
+ size = mtd_store_size(part_name) - off;
erase_len = lldiv(size + mtd->erasesize - 1,
mtd->erasesize);
printf("erasing from 0x%llx, length 0x%lx\n",
offset, size);
-
- for (erased_size = 0; erased_size < erase_len;
- offset += mtd->erasesize) {
- if (!part_name)/*erase chip,erase_len include bb*/
- erased_size++;
- WATCHDOG_RESET();
- if (!scrub_flag) {
- ret = mtd_block_isbad(mtd, offset);
- if (ret > 0) {
- pr_info("skip bad block in 0x%08llx\n", offset);
- continue;
- } else if (ret < 0) {
- pr_info("MTD get bad block failed in 0x%08llx\n",
- offset);
- return ret;
- }
- }
+ if ((MTD_NORFLASH == mtd->type)
+ && (size == mtd->size) && (0 == offset)) {
+ /* erase whole spi flash in one cmd */
info.mtd = mtd;
info.addr = offset;
- info.len = mtd->erasesize;
+ info.len = size;
info.scrub = scrub_flag;
info.callback = NULL;
- if (part_name) /*erase partition,erase_len except bb*/
- erased_size++;
-
- loff_t bootloader_max_addr = BOOT_TOTAL_PAGES * mtd->writesize;
- if (offset >= bootloader_max_addr) {
- mtd = mtd_store_get(1);
- }
-
ret = mtd_erase(mtd, &info);
if (ret)
pr_info("%s %d mtd erase err, ret %d\n",
__func__, __LINE__, ret);
+ } else {
+ for (erased_size = 0; erased_size < erase_len;
+ offset += mtd->erasesize) {
+ if (!part_name)/*erase chip,erase_len include bb*/
+ erased_size++;
+ WATCHDOG_RESET();
+ if (!scrub_flag) {
+ ret = mtd_block_isbad(mtd, offset);
+ if (ret > 0) {
+ pr_info("skip bad block in 0x%08llx\n", offset);
+ /* If the last block of chip is a bad block */
+ if (offset == (chip_size - mtd->erasesize))
+ return 0;
+ continue;
+ } else if (ret < 0) {
+ pr_info("MTD get bad block failed in 0x%08llx\n",
+ offset);
+ return ret;
+ }
+ }
+ info.mtd = mtd;
+ info.addr = offset;
+ info.len = mtd->erasesize;
+ info.scrub = scrub_flag;
+ info.callback = NULL;
+ if (part_name) /*erase partition,erase_len except bb*/
+ erased_size++;
+
+ loff_t bootloader_max_addr = BOOT_TOTAL_PAGES * mtd->writesize;
+ if (offset >= bootloader_max_addr) {
+ mtd = mtd_store_get(1);
+ }
+
+ ret = mtd_erase(mtd, &info);
+ if (ret) {
+ pr_info("%s %d mtd erase err, ret %d\n",
+ __func__, __LINE__, ret);
+ /* If the last block of chip is a bad block */
+ if (offset == (chip_size - mtd->erasesize))
+ return 0;
+ }
+ }
}
return ret;
}
static u8 mtd_store_boot_copy_num(const char *part_name)
{
+ cpu_id_t cpu_id = get_cpu_id();
+ enum boot_type_e medium_type = store_get_type();
+
if (!part_name) {
pr_info("%s %d invalid name!\n",
__func__, __LINE__);
return 0;
}
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- if (!strcmp(part_name, BOOT_LOADER) ||
- !strcmp(part_name, BOOT_BL2) ||
- !strcmp(part_name, BOOT_SPL))
- return CONFIG_BL2_COPY_NUM;
- if (!strcmp(part_name, BOOT_TPL) ||
- !strcmp(part_name, BOOT_FIP))
- return CONFIG_TPL_COPY_NUM;
-#else
- if (!strcmp(part_name, BOOT_LOADER))
- return boot_num_get();
-#endif
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER) {
+ if (!strcmp(part_name, BOOT_TPL) ||
+ !strcmp(part_name, BOOT_FIP) ||
+ !strcmp(part_name, BOOT_DEVFIP)) {
+ if (BOOT_NAND_MTD == medium_type ||
+ BOOT_SNAND == medium_type)
+ return CONFIG_NAND_TPL_COPY_NUM;
+ if (medium_type == BOOT_SNOR)
+ return CONFIG_NOR_TPL_COPY_NUM;
+ } else {
+ if ((cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) || (cpu_id.family_id == MESON_CPU_MAJOR_ID_T7)
+ || (cpu_id.family_id == MESON_CPU_MAJOR_ID_S4)) {
+ return g_ssp.boot_bakups;
+ } else {
+ return CONFIG_BL2_COPY_NUM;
+ }
+ }
+ } else {
+ if (!strcmp(part_name, BOOT_LOADER))
+ return boot_num_get();
+ }
pr_info("%s %d invalid name: %s!\n",
__func__, __LINE__, part_name);
@@ -713,54 +734,105 @@
return 0;
}
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- if (!strcmp(part_name, BOOT_LOADER) ||
- !strcmp(part_name, BOOT_BL2) ||
- !strcmp(part_name, BOOT_SPL))
- return 1;
-
- if (!strcmp(part_name, BOOT_TPL) ||
- !strcmp(part_name, BOOT_FIP))
- return 1;
-#else
- if (!strcmp(part_name, BOOT_LOADER))
- return 1;
-#endif
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER) {
+ if (!strcmp(part_name, BOOT_BL2) ||
+ !strcmp(part_name, BOOT_SPL) ||
+ !strcmp(part_name, BOOT_TPL) ||
+ !strcmp(part_name, BOOT_FIP) ||
+ !strcmp(part_name, BOOT_BL2E) ||
+ !strcmp(part_name, BOOT_BL2X) ||
+ !strcmp(part_name, BOOT_DDRFIP) ||
+ !strcmp(part_name, BOOT_DEVFIP))
+ return 1;
+ } else {
+ if (!strcmp(part_name, BOOT_LOADER))
+ return 1;
+ }
return 0;
}
+char *boot_entry_old[] = {BOOT_BL2, BOOT_TPL};
+char *boot_entry_sc2[] = {BOOT_BL2, BOOT_BL2E, BOOT_BL2X, BOOT_DDRFIP, BOOT_DEVFIP};
+static char **get_bootloader_entry(int *boot_count)
+{
+ cpu_id_t cpu_id = get_cpu_id();
+ char **boot_entry = boot_entry_old;
+
+ if ((cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) || (cpu_id.family_id == MESON_CPU_MAJOR_ID_T7)
+ || (cpu_id.family_id == MESON_CPU_MAJOR_ID_S4)) {
+ *boot_count = 5;
+ boot_entry = boot_entry_sc2;
+ }
+ return boot_entry;
+
+}
+
static u64 mtd_store_boot_copy_size(const char *part_name)
{
+ cpu_id_t cpu_id = get_cpu_id();
struct mtd_info *mtd = mtd_store_get(0);
- int pages_per_copy = 0;
+ int pages_per_copy = 0, boot_count = 2 , i;
+ u64 size = 0;
+ char **boot_entry;
if (!part_name) {
- pr_info("%s %d invalid name!\n",
- __func__, __LINE__);
+ pr_info("%s %d invalid name!\n", __func__, __LINE__);
return 0;
}
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- if (!strcmp(part_name, BOOT_LOADER) ||
- !strcmp(part_name, BOOT_BL2) ||
- !strcmp(part_name, BOOT_SPL)) {
- pages_per_copy = BOOT_TOTAL_PAGES / CONFIG_BL2_COPY_NUM;
- return mtd->writesize * pages_per_copy;
- } else if (!strcmp(part_name, BOOT_TPL) ||
- !strcmp(part_name, BOOT_FIP)) {
- return CONFIG_TPL_SIZE_PER_COPY;
- }
- return 0;
-#else
- u8 num;
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER) {
+ if (!strcmp(part_name, BOOT_BL2) ||
+ !strcmp(part_name, BOOT_SPL)) {
+ if ((cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) || (cpu_id.family_id == MESON_CPU_MAJOR_ID_T7)
+ || (cpu_id.family_id == MESON_CPU_MAJOR_ID_S4)) {
+ return g_ssp.boot_entry[BOOT_AREA_BB1ST].size;
+ } else {
+ pages_per_copy = BOOT_TOTAL_PAGES / CONFIG_BL2_COPY_NUM;
+ return mtd->writesize * pages_per_copy;
+ }
+ } else if (!strcmp(part_name, BOOT_TPL) ||
+ !strcmp(part_name, BOOT_FIP) ||
+ !strcmp(part_name, BOOT_DEVFIP)) {
+ if ((cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) || (cpu_id.family_id == MESON_CPU_MAJOR_ID_T7)
+ || (cpu_id.family_id == MESON_CPU_MAJOR_ID_S4)) {
+ return g_ssp.boot_entry[BOOT_AREA_DEVFIP].size;
+ } else {
+ return CONFIG_TPL_SIZE_PER_COPY;
+ }
+ } else if (!strcmp(part_name, BOOT_BL2E))
+ return g_ssp.boot_entry[BOOT_AREA_BL2E].size;
+ else if (!strcmp(part_name, BOOT_BL2X))
+ return g_ssp.boot_entry[BOOT_AREA_BL2X].size;
+ else if (!strcmp(part_name, BOOT_DDRFIP))
+ return g_ssp.boot_entry[BOOT_AREA_DDRFIP].size;
+ else if (!strcmp(part_name, BOOT_LOADER)) {
+ if ((cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) || (cpu_id.family_id == MESON_CPU_MAJOR_ID_T7)
+ || (cpu_id.family_id == MESON_CPU_MAJOR_ID_S4)) {
+ boot_entry = get_bootloader_entry(&boot_count);
+ for (i = 0; i < boot_count; i++, boot_entry++)
+ size += g_ssp.boot_entry[i].size;
+ } else
+ size = CONFIG_TPL_SIZE_PER_COPY +
+ (BOOT_TOTAL_PAGES / CONFIG_BL2_COPY_NUM)*mtd->writesize;
+ return size;
- if (strcmp(part_name, BOOT_LOADER))
- return 0;
- num = mtd_store_boot_copy_num(part_name);
- if (!num)
- return 0;
- pages_per_copy = BOOT_TOTAL_PAGES / num;
- return mtd->writesize * pages_per_copy;
-#endif
+ } else
+ return 0;
+ } else {
+ u8 num;
+
+ if (strcmp(part_name, BOOT_LOADER))
+ return 0;
+ num = mtd_store_boot_copy_num(part_name);
+ if (!num)
+ return 0;
+ pages_per_copy = BOOT_TOTAL_PAGES / num;
+
+ if (mtd->writesize == 1)
+ size = mtd_store_size(BOOT_LOADER);
+ else
+ size = mtd->writesize * pages_per_copy;
+ return size;
+ }
}
static int mtd_store_boot_read(const char *part_name,
@@ -772,6 +844,7 @@
size_t retlen = 0, len = size;
u8 num = 0;
u64 size_per_copy = 0;
+ enum boot_type_e medium_type = store_get_type();
if (!part_name) {
pr_info("%s %d invalid name!\n",
@@ -790,55 +863,60 @@
size_per_copy = mtd_store_boot_copy_size(part_name);
if (size_per_copy == 0)
return -ENXIO;
- if (cpy >= num)
+ if (cpy >= num) {
+ pr_info("error: read cpy:0x%x >= num: 0x%x\
+ please input again\n",
+ cpy, num);
return -ENXIO;
+ }
offset += (cpy * size_per_copy);
limit = offset + size_per_copy;
-#if defined(CONFIG_SPI_NAND)
- /**
- * TODO:
- * Need delete this part of code when we fix the
- * romcode read size limit bug and afunction of
- * bad block skipping.
- */
- if (!strcmp(part_name, BOOT_LOADER) ||
- !strcmp(part_name, BOOT_BL2) ||
- !strcmp(part_name, BOOT_SPL)) {
- int i, read_cnt;
- loff_t off = offset;
- size_t sz_read = SZ_2K;
- size_t length = (size > BL2_SIZE) ? BL2_SIZE : size;
+ if (BOOT_SNAND == medium_type) {
+ /**
+ * TODO:
+ * Need delete this part of code when we fix the
+ * romcode read size limit bug and afunction of
+ * bad block skipping.
+ */
+ if (!strcmp(part_name, BOOT_BL2) ||
+ !strcmp(part_name, BOOT_SPL)) {
+ int i, read_cnt;
+ loff_t off = offset;
+ size_t sz_read = SZ_2K;
+ size_t length = (size > BL2_SIZE) ? BL2_SIZE : size;
- read_cnt = (length + sz_read - 1) / sz_read;
- for (i = 0; i < read_cnt; i++) {
- len = min(sz_read, (length - i * sz_read));
- ret = mtd_store_read_skip_bad(mtd,
- off,
- &len,
- &retlen,
- limit,
- (u_char *)(dest + i * sz_read));
- if (ret)
- return -EIO;
- off += mtd->writesize;
- if (retlen > len)
- off += (retlen - len);
- }
-#ifndef CONFIG_DISCRETE_BOOTLOADER
- if (size <= BL2_SIZE)
- return ret;
- ret = mtd_store_read_skip_bad(mtd,
- off,
- &(size - BL2_SIZE),
- &retlen,
- limit,
- (u_char *)(dest + BL2_SIZE));
- if (ret)
- return -EIO;
-#endif
+ read_cnt = (length + sz_read - 1) / sz_read;
+ for (i = 0; i < read_cnt; i++) {
+ len = min(sz_read, (length - i * sz_read));
+ ret = mtd_store_read_skip_bad(mtd,
+ off,
+ &len,
+ &retlen,
+ limit,
+ (u_char *)(dest + i * sz_read));
+ if (ret)
+ return -EIO;
+ off += mtd->writesize;
+ if (retlen > len)
+ off += (retlen - len);
+ }
+ if (store_get_device_bootloader_mode() == COMPACT_BOOTLOADER) {
+ if (size <= BL2_SIZE)
+ return ret;
+ len = size - BL2_SIZE;
+ ret = mtd_store_read_skip_bad(mtd,
+ off,
+ &len,
+ &retlen,
+ limit,
+ (u_char *)(dest + BL2_SIZE));
+ if (ret)
+ return -EIO;
+ }
+
return ret;
+ }
}
-#endif
ret = mtd_store_read_skip_bad(mtd,
offset,
&len,
@@ -859,6 +937,7 @@
size_t retlen = 0, len = size;
u8 num = 0;
u64 size_per_copy = 0;
+ enum boot_type_e medium_type = store_get_type();
if (!part_name) {
pr_info("%s %d invalid name!\n",
@@ -877,9 +956,17 @@
size_per_copy = mtd_store_boot_copy_size(part_name);
if (size_per_copy == 0)
return -ENXIO;
+
+ if (size > size_per_copy)
+ return -EINVAL;
+
if (cpy != BOOT_OPS_ALL) {
- if (cpy >= num)
+ if (cpy >= num) {
+ pr_info("error: write cpy:0x%x >= num: 0x%x\
+ please input again\n",
+ cpy, num);
return -ENXIO;
+ }
offset += (cpy * size_per_copy);
endoff = offset + size_per_copy;
} else {
@@ -889,47 +976,48 @@
pr_info("write %lx bytes to %llx\n",
size, offset);
limit = offset + size_per_copy;
-#if defined(CONFIG_SPI_NAND)
- /**
- * TODO:
- * 1.Need delete this part of code when we fix the
- * romcode read size limit bug and afunction of
- * bad block skipping.
- * 2.Need handle info page position there, not in
- * SPI NAND drvier, which we can not know the bad
- * block skiped or not.
- */
- if (!strcmp(part_name, BOOT_LOADER) ||
- !strcmp(part_name, BOOT_BL2) ||
- !strcmp(part_name, BOOT_SPL)) {
- int i, write_cnt;
- loff_t off = offset;
- size_t sz_write = SZ_2K;
- size_t length = (size > BL2_SIZE) ? BL2_SIZE : size;
+ if (BOOT_SNAND == medium_type) {
- write_cnt = (length + sz_write - 1) / sz_write;
- for (i = 0; i < write_cnt; i++) {
- len = min(sz_write, (length - i * sz_write));
- ret = mtd_store_write_skip_bad(mtd,
- off,
- &len,
- &retlen,
- limit,
- (u_char *)(source +
- i * sz_write),
- 0);
- if (ret)
- return -EIO;
- off += mtd->writesize;
- if (retlen > len)
- off += (retlen - len);
- }
-#ifndef CONFIG_DISCRETE_BOOTLOADER
+ /**
+ * TODO:
+ * 1.Need delete this part of code when we fix the
+ * romcode read size limit bug and afunction of
+ * bad block skipping.
+ * 2.Need handle info page position there, not in
+ * SPI NAND drvier, which we can not know the bad
+ * block skiped or not.
+ */
+ if (!strcmp(part_name, BOOT_BL2) ||
+ !strcmp(part_name, BOOT_SPL)) {
+ int i, write_cnt;
+ loff_t off = offset;
+ size_t sz_write = SZ_2K;
+ size_t length = (size > BL2_SIZE) ? BL2_SIZE : size;
+
+ write_cnt = (length + sz_write - 1) / sz_write;
+ for (i = 0; i < write_cnt; i++) {
+ len = min(sz_write, (length - i * sz_write));
+ ret = mtd_store_write_skip_bad(mtd,
+ off,
+ &len,
+ &retlen,
+ limit,
+ (u_char *)(source +
+ i * sz_write),
+ 0);
+ if (ret)
+ return -EIO;
+ off += mtd->writesize;
+ if (retlen > len)
+ off += (retlen - len);
+ }
+ if (store_get_device_bootloader_mode() == COMPACT_BOOTLOADER) {
if (size <= BL2_SIZE)
return ret;
+ len = size - BL2_SIZE;
ret = mtd_store_write_skip_bad(mtd,
off,
- &(size - BL2_SIZE),
+ &len,
&retlen,
limit,
(u_char *)(source +
@@ -937,10 +1025,11 @@
0);
if (ret)
return -EIO;
-#endif
- continue;
}
-#endif
+ continue;
+ }
+ }
+
ret = mtd_store_write_skip_bad(mtd,
offset,
&len,
@@ -954,18 +1043,12 @@
return ret;
}
-static int mtd_store_boot_erase(const char *part_name, u8 cpy)
+static int _mtd_store_boot_erase(const char *part_name, u8 cpy)
{
u8 num;
size_t size_per_copy = 0, erasesize = 0;
loff_t offset = 0;
- if (!part_name) {
- pr_info("%s %d invalid name!\n",
- __func__, __LINE__);
- return 1;
- }
-
num = mtd_store_boot_copy_num(part_name);
size_per_copy = mtd_store_boot_copy_size(part_name);
if ((cpy > (num - 1)) && cpy != BOOT_OPS_ALL) {
@@ -981,6 +1064,58 @@
return mtd_store_erase(part_name, offset, erasesize, 0);
}
+static int mtd_store_boot_erase(const char *part_name, u8 cpy)
+{
+ cpu_id_t cpu_id = get_cpu_id();
+ char **boot_entry = boot_entry_old;
+ u8 num, i = 0, boot_entry_cnt = 2;
+ int ret;
+ u8 backup_num = 0;
+ enum boot_type_e medium_type = store_get_type();
+
+ if (!part_name) {
+ pr_info("%s %d invalid name!\n",
+ __func__, __LINE__);
+ return 1;
+ }
+
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER) {
+ if ((cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) || (cpu_id.family_id == MESON_CPU_MAJOR_ID_T7)
+ || (cpu_id.family_id == MESON_CPU_MAJOR_ID_S4)) {
+ boot_entry = boot_entry_sc2;
+ boot_entry_cnt = 5;
+ }
+ if (BOOT_SNOR == medium_type)
+ backup_num = CONFIG_NOR_TPL_COPY_NUM;
+ else if (BOOT_NAND_MTD == medium_type ||
+ BOOT_SNAND == medium_type)
+ backup_num = CONFIG_NAND_TPL_COPY_NUM;
+ if (!strcmp(part_name, BOOT_LOADER)) {
+ num = CONFIG_BL2_COPY_NUM;
+ if (num != backup_num) {
+ if (cpy != BOOT_OPS_ALL) {
+ pr_info("%s %d unsupport erase bl2&tpl cpy %d\n",
+ __func__, __LINE__, cpy);
+ pr_info("BL2 backups: %d, TPL backups: %d\n",
+ CONFIG_BL2_COPY_NUM,
+ backup_num);
+ return 1;
+ }
+ } else
+ cpy = BOOT_OPS_ALL;
+ for (i = 0; i < boot_entry_cnt; i++, boot_entry++) {
+ ret = _mtd_store_boot_erase(*boot_entry, cpy);
+ if (ret)
+ pr_info("boot partition erase failed\n");
+ }
+ return ret;
+ }
+ }
+
+ return _mtd_store_boot_erase(part_name, cpy);
+}
+
+
static u32 mtd_store_rsv_size(const char *rsv_name)
{
if (!rsv_name) {
@@ -996,6 +1131,8 @@
return meson_rsv_env_size();
else if (!strcmp(rsv_name, RSV_DTB))
return meson_rsv_dtb_size();
+ else if (!strcmp(rsv_name, RSV_DDR_PARA))
+ return meson_rsv_ddr_para_size();
pr_info("%s %d invalid rsv info name: %s\n",
__func__, __LINE__, rsv_name);
return 0;
@@ -1016,6 +1153,8 @@
return meson_rsv_env_read((u_char *)dest, size);
else if (!strcmp(rsv_name, RSV_DTB))
return meson_rsv_dtb_read((u_char *)dest, size);
+ else if (!strcmp(rsv_name, RSV_DDR_PARA))
+ return meson_rsv_ddr_para_read((u_char *)dest, size);
pr_info("%s %d invalid rsv info name: %s\n",
__func__, __LINE__, rsv_name);
return 1;
@@ -1037,7 +1176,8 @@
return meson_rsv_env_write((u_char *)source, size);
else if (!strcmp(rsv_name, RSV_DTB))
return meson_rsv_dtb_write((u_char *)source, size);
-
+ else if (!strcmp(rsv_name, RSV_DDR_PARA))
+ return meson_rsv_ddr_para_write((u_char *)source, size);
pr_info("%s %d invalid rsv info name: %s\n",
__func__, __LINE__, rsv_name);
return 1;
@@ -1059,6 +1199,8 @@
return meson_rsv_env_erase();
else if (!strcmp(rsv_name, RSV_DTB))
return meson_rsv_dtb_erase();
+ else if (!strcmp(rsv_name, RSV_DDR_PARA))
+ return meson_rsv_ddr_para_erase();
pr_info("%s %d invalid rsv info name: %s\n",
__func__, __LINE__, rsv_name);
return 1;
@@ -1119,29 +1261,6 @@
return mtd_read(mtd, offset, length, &length, buf);
}
-static int nor_rsv_write(const char *name, size_t size, void *buf)
-{
- struct mtd_info *mtd;
- loff_t offset;
- size_t length, total;
- int ret = 0;
-
- if (!name)
- return 1;
- length = size;
- mtd = mtd_store_get(0);
- total = mtd_store_size(name);
- if (length > total) {
- pr_info("request 0x%lx over the rsv size 0x%lx\n",
- length, total);
- return 1;
- }
- ret = mtd_store_get_offset(name, &offset, 0);
- if (ret)
- return ret;
- return mtd_write(mtd, offset, length, &length, buf);
-}
-
static int nor_rsv_erase(const char *name)
{
struct mtd_info *mtd;
@@ -1160,9 +1279,51 @@
erase.mtd = mtd;
erase.addr = offset;
erase.len = length;
+ erase.callback = NULL;
return mtd_erase(mtd, &erase);
}
+static int nor_rsv_write(const char *name, size_t size, void *buf)
+{
+ struct mtd_info *mtd;
+ loff_t offset;
+ size_t length, total;
+ int ret = 0;
+ struct erase_info erase;
+
+ if (!name)
+ return 1;
+
+ length = size;
+ mtd = mtd_store_get(0);
+ total = mtd_store_size(name);
+ if (length > total) {
+ pr_info("request 0x%lx over the rsv size 0x%lx\n",
+ length, total);
+ return 1;
+ }
+
+ ret = mtd_store_get_offset(name, &offset, 0);
+ if (ret)
+ return ret;
+ /* special path for erase */
+ if (!strcmp(name, RSV_ENV) || !strcmp(name, RSV_DTB) || !strcmp(name, RSV_KEY)) {
+ erase.mtd = mtd;
+ erase.addr = offset;
+ erase.callback = NULL;
+ erase.len = length;
+ if (mtd_mod_by_eb(length, mtd))
+ erase.len = (mtd_div_by_eb(length, mtd) + 1)
+ * mtd->erasesize;
+ ret = mtd_erase(mtd, &erase);
+ if (!ret)
+ printf("%s() %d, erase %s error %d\n",
+ __func__, __LINE__, name, ret);
+ }
+
+ return mtd_write(mtd, offset, length, &length, buf);
+}
+
static int nor_rsv_protect(const char *name, bool ops)
{
pr_info("spi nor flash not support this yet!\n");
@@ -1171,6 +1332,8 @@
void mtd_store_mount_ops(struct storage_t *store)
{
+ store->get_part_count = mtd_store_count;
+ store->list_part_name = mtd_store_name;
store->get_part_size = mtd_store_size;
store->read = mtd_store_read;
store->write = mtd_store_write;
diff --git a/drivers/mtd/mtdpart.c b/drivers/mtd/mtdpart.c
index a889f79..a111fcf 100644
--- a/drivers/mtd/mtdpart.c
+++ b/drivers/mtd/mtdpart.c
@@ -29,6 +29,11 @@
#include <linux/sizes.h>
#include "mtdcore.h"
+#ifdef CONFIG_AML_MTDPART
+#include <jffs2/load_kernel.h>
+#include <amlogic/aml_mtd.h>
+#include <amlogic/storage.h>
+#endif
#ifndef __UBOOT__
static DEFINE_MUTEX(mtd_partitions_mutex);
@@ -861,6 +866,43 @@
* We don't register the master, or expect the caller to have done so,
* for reasons of data integrity.
*/
+#ifdef CONFIG_AML_MTDPART
+struct list_head aml_device;
+static int aml_nbparts = 0;
+int get_aml_mtdpart_count(void)
+{
+ return aml_nbparts;
+}
+
+int get_aml_mtdpart_name(struct mtd_info *master, int idx, char *name)
+{
+ struct part_info *temp;
+ struct mtd_device *dentry;
+ if (idx >= get_aml_mtdpart_count())
+ return -1;
+
+ list_for_each_entry(dentry, &aml_device, link) {
+ list_for_each_entry(temp, &dentry->parts, link) {
+ printf("0x%012llx-0x%012llx : \"%s\"\n",
+ (unsigned long long)temp->offset,
+ (unsigned long long)(temp->offset + temp->size),
+ temp->name);
+ }
+ }
+ return 0;
+}
+
+void list_aml_mtd_partitions(struct mtd_info *master)
+{
+ struct mtd_info *slave;
+ int i = 0;
+
+ list_for_each_entry(slave, &master->partitions, node)
+ printf("%2d: %-20s0x%08llx\t0x%08llx\n",
+ i++, slave->name, slave->size, slave->offset);
+ return;
+}
+#endif
int add_mtd_partitions(struct mtd_info *master,
const struct mtd_partition *parts,
@@ -870,6 +912,13 @@
uint64_t cur_offset = 0;
int i;
+#ifdef CONFIG_AML_MTDPART
+ printf("%s, %d, master: %p, master->partitions: %p\n", __func__, __LINE__, master, &master->partitions);
+ if (master->partitions.next == NULL) {
+ printf("%s, %d INIT partition\n", __func__, __LINE__);
+ INIT_LIST_HEAD(&master->partitions);
+ }
+#endif
printk("Creating %d MTD partitions on \"%s\":\n", nbparts, master->name);
for (i = 0; i < nbparts; i++) {
@@ -997,81 +1046,70 @@
EXPORT_SYMBOL_GPL(mtd_get_device_size);
#ifdef CONFIG_AML_MTDPART
-struct list_head aml_device;
+extern struct mtd_info *mtd_store_get(int dev);
int mtdparts_init(void)
{
-#if 0
- struct mtd_part *mtdpart;
- int i;
-
- if (aml_part) {
- pr_info("%s %d already init\n",
- __func__, __LINE__);
- return 0;
- }
-
- list_for_each_entry(mtdpart, &mtd_partitions, list) {
- aml_part_cnt++;
- }
- aml_part = (struct part_info *)malloc(aml_part_cnt *
- sizeof(struct part_info));
- i = aml_part_cnt - 1;
- list_for_each_entry(mtdpart, &mtd_partitions, list) {
- aml_part[i].name = mtdpart->mtd.name;
- aml_part[i].offset = mtdpart->offset;
- aml_part[i].size = mtdpart->mtd.size;
- i--;
- }
- for (i = 0; i < aml_part_cnt; i++)
- pr_info("0x%012llx-0x%012llx : \"%s\"\n",
- (unsigned long long)aml_part[i].offset,
- (unsigned long long)(aml_part[i].offset +
- aml_part[i].size),
- aml_part[i].name);
- return 0;
-#endif
static int init_flag = 0;
- struct mtd_part *part;
+ struct mtd_info *part;
struct part_info *temp;
struct mtd_device *dev, *dentry;
+ struct mtd_info *mtd = NULL;
+ u8 i = 0;
+ u8 cnt = 0;
+ enum boot_type_e medium_type = store_get_type();
+
+ if (BOOT_NAND_MTD == medium_type)
+ cnt = MAX_MTD_CNT;
+ else if ((BOOT_SNAND == medium_type) || (BOOT_SNOR == medium_type))
+ cnt = MAX_MTD_CNT - 1;
+ else {
+ printf("no valid storage device\n");
+ return 1;
+ }
if (init_flag) {
debug("%s %d part already init\n", __func__, __LINE__);
return 0;
}
INIT_LIST_HEAD(&aml_device);
- list_for_each_entry(part, &mtd_partitions, list) {
- dev = kzalloc(sizeof(*dev), GFP_KERNEL);
- dev->num_parts = 1;
- dev->id = kzalloc(sizeof(*dev->id), GFP_KERNEL);
- if (part->mtd.type == MTD_NANDFLASH)
- dev->id->type = MTD_DEV_TYPE_NAND;
- else if (part->mtd.type == MTD_NORFLASH)
- dev->id->type = MTD_DEV_TYPE_NOR;
- else
- dev->id->type = 0;
- dev->id->size = part->mtd.size;
- dev->id->num = 0;
-#ifdef CONFIG_MESON_NFC
- if (strcmp(part->mtd.name, "bootloader"))
+
+ for (i = 0; i < cnt; i++) {
+ mtd = mtd_store_get(i);
+ printf("%s, %d,mtd->partition: 0x%p, mtd: 0x%p\n", __func__, __LINE__, &mtd->partitions, mtd);
+ list_for_each_entry(part, &mtd->partitions, node) {
+ dev = kzalloc(sizeof(*dev), GFP_KERNEL);
+ dev->num_parts = 1;
+ dev->id = kzalloc(sizeof(*dev->id), GFP_KERNEL);
+ if (part->type == MTD_NANDFLASH)
+ dev->id->type = MTD_DEV_TYPE_NAND;
+ else if (part->type == MTD_NORFLASH)
+ dev->id->type = MTD_DEV_TYPE_NOR;
+ else
+ dev->id->type = 0;
+ dev->id->size = part->size;
+ dev->id->num = 0;
+ if ((BOOT_NAND_MTD == medium_type) && strcmp(part->name, "bootloader"))
dev->id->num = 1;
-#endif
temp = kzalloc(sizeof(*temp), GFP_KERNEL);
- temp->name = part->mtd.name;
+ temp->name = part->name;
+
temp->offset = part->offset;
- temp->size = part->mtd.size;
+ temp->size = part->size;
temp->dev = dev;
INIT_LIST_HEAD(&dev->parts);
- list_add(&temp->link, &dev->parts);
- list_add(&dev->link, &aml_device);
+ list_add_tail(&temp->link, &dev->parts);
+ list_add_tail(&dev->link, &aml_device);
+ }
}
list_for_each_entry(dentry, &aml_device, link) {
- list_for_each_entry(temp, &dentry->parts, link)
+ list_for_each_entry(temp, &dentry->parts, link) {
printf("0x%012llx-0x%012llx : \"%s\"\n",
(unsigned long long)temp->offset,
(unsigned long long)(temp->offset + temp->size),
temp->name);
+ aml_nbparts++;
+ }
}
init_flag = 1;
return 0;
diff --git a/drivers/mtd/nand/Kconfig b/drivers/mtd/nand/Kconfig
index 10b083d..78ae04b 100644
--- a/drivers/mtd/nand/Kconfig
+++ b/drivers/mtd/nand/Kconfig
@@ -4,289 +4,3 @@
source "drivers/mtd/nand/raw/Kconfig"
source "drivers/mtd/nand/spi/Kconfig"
-
-config SYS_NAND_SELF_INIT
- bool
- help
- This option, if enabled, provides more flexible and linux-like
- NAND initialization process.
-
-config NAND_DENALI
- bool
- select SYS_NAND_SELF_INIT
- imply CMD_NAND
-
-config SPI_NAND
- bool "Enable SPI NAND DRIVER"
- depends on MTD && AML_SPIFC
- help
- This option, if enabled, SOC can support SPI-NAND flash
- driver.
-
-config AML_MTDPART
- bool "Enable Amlogic partition"
- depends on MTD
- help
- This option, if enabled, we will parse amlogic partition
- table.
-
-config NAND_DENALI_DT
- bool "Support Denali NAND controller as a DT device"
- select NAND_DENALI
- depends on OF_CONTROL && DM
- help
- Enable the driver for NAND flash on platforms using a Denali NAND
- controller as a DT device.
-
-config NAND_DENALI_SPARE_AREA_SKIP_BYTES
- int "Number of bytes skipped in OOB area"
- depends on NAND_DENALI
- range 0 63
- help
- This option specifies the number of bytes to skip from the beginning
- of OOB area before last ECC sector data starts. This is potentially
- used to preserve the bad block marker in the OOB area.
-
-config NAND_OMAP_GPMC
- bool "Support OMAP GPMC NAND controller"
- depends on ARCH_OMAP2PLUS
- help
- Enables omap_gpmc.c driver for OMAPx and AMxxxx platforms.
- GPMC controller is used for parallel NAND flash devices, and can
- do ECC calculation (not ECC error detection) for HAM1, BCH4, BCH8
- and BCH16 ECC algorithms.
-
-config NAND_OMAP_GPMC_PREFETCH
- bool "Enable GPMC Prefetch"
- depends on NAND_OMAP_GPMC
- default y
- help
- On OMAP platforms that use the GPMC controller
- (CONFIG_NAND_OMAP_GPMC_PREFETCH), this options enables the code that
- uses the prefetch mode to speed up read operations.
-
-config NAND_OMAP_ELM
- bool "Enable ELM driver for OMAPxx and AMxx platforms."
- depends on NAND_OMAP_GPMC && !OMAP34XX
- help
- ELM controller is used for ECC error detection (not ECC calculation)
- of BCH4, BCH8 and BCH16 ECC algorithms.
- Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
- thus such SoC platforms need to depend on software library for ECC error
- detection. However ECC calculation on such plaforms would still be
- done by GPMC controller.
-
-config NAND_VF610_NFC
- bool "Support for Freescale NFC for VF610"
- select SYS_NAND_SELF_INIT
- imply CMD_NAND
- help
- Enables support for NAND Flash Controller on some Freescale
- processors like the VF610, MCF54418 or Kinetis K70.
- The driver supports a maximum 2k page size. The driver
- currently does not support hardware ECC.
-
-choice
- prompt "Hardware ECC strength"
- depends on NAND_VF610_NFC
- default SYS_NAND_VF610_NFC_45_ECC_BYTES
- help
- Select the ECC strength used in the hardware BCH ECC block.
-
-config SYS_NAND_VF610_NFC_45_ECC_BYTES
- bool "24-error correction (45 ECC bytes)"
-
-config SYS_NAND_VF610_NFC_60_ECC_BYTES
- bool "32-error correction (60 ECC bytes)"
-
-endchoice
-
-config NAND_PXA3XX
- bool "Support for NAND on PXA3xx and Armada 370/XP/38x"
- select SYS_NAND_SELF_INIT
- imply CMD_NAND
- help
- This enables the driver for the NAND flash device found on
- PXA3xx processors (NFCv1) and also on Armada 370/XP (NFCv2).
-
-config NAND_SUNXI
- bool "Support for NAND on Allwinner SoCs"
- default ARCH_SUNXI
- depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I || MACH_SUN8I
- select SYS_NAND_SELF_INIT
- select SYS_NAND_U_BOOT_LOCATIONS
- select SPL_NAND_SUPPORT
- imply CMD_NAND
- ---help---
- Enable support for NAND. This option enables the standard and
- SPL drivers.
- The SPL driver only supports reading from the NAND using DMA
- transfers.
-
-if NAND_SUNXI
-
-config NAND_SUNXI_SPL_ECC_STRENGTH
- int "Allwinner NAND SPL ECC Strength"
- default 64
-
-config NAND_SUNXI_SPL_ECC_SIZE
- int "Allwinner NAND SPL ECC Step Size"
- default 1024
-
-config NAND_SUNXI_SPL_USABLE_PAGE_SIZE
- int "Allwinner NAND SPL Usable Page Size"
- default 1024
-
-endif
-
-config NAND_ARASAN
- bool "Configure Arasan Nand"
- select SYS_NAND_SELF_INIT
- imply CMD_NAND
- help
- This enables Nand driver support for Arasan nand flash
- controller. This uses the hardware ECC for read and
- write operations.
-
-config NAND_MXC
- bool "MXC NAND support"
- depends on CPU_ARM926EJS || CPU_ARM1136 || MX5
- imply CMD_NAND
- help
- This enables the NAND driver for the NAND flash controller on the
- i.MX27 / i.MX31 / i.MX5 rocessors.
-
-config NAND_MXS
- bool "MXS NAND support"
- depends on MX23 || MX28 || MX6 || MX7
- imply CMD_NAND
- select APBH_DMA
- select APBH_DMA_BURST if ARCH_MX6 || ARCH_MX7
- select APBH_DMA_BURST8 if ARCH_MX6 || ARCH_MX7
- help
- This enables NAND driver for the NAND flash controller on the
- MXS processors.
-
-config NAND_ZYNQ
- bool "Support for Zynq Nand controller"
- select SYS_NAND_SELF_INIT
- imply CMD_NAND
- help
- This enables Nand driver support for Nand flash controller
- found on Zynq SoC.
-
-config NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
- bool "Enable use of 1st stage bootloader timing for NAND"
- depends on NAND_ZYNQ
- help
- This flag prevent U-boot reconfigure NAND flash controller and reuse
- the NAND timing from 1st stage bootloader.
-
-config MESON_NFC
- bool "Support for NAND on Amlogic SoCs"
- depends on ARCH_MESON && MTD
- help
- This option, if enabled, support for MESON Nand flash controller.
-
-config AML_MTD
- bool "support AML MTD for Raw NAND or SPI NAND or SPI NOR"
- default y if MESON_NFC
- default y if SPI_NAND
- default y if SPI_FLASH
- help
- This option, if enabled, support for AML MTD
-
-comment "Generic NAND options"
-
-config SYS_NAND_BLOCK_SIZE
- hex "NAND chip eraseblock size"
- depends on ARCH_SUNXI
- help
- Number of data bytes in one eraseblock for the NAND chip on the
- board. This is the multiple of NAND_PAGE_SIZE and the number of
- pages.
-
-config SYS_NAND_PAGE_SIZE
- hex "NAND chip page size"
- depends on ARCH_SUNXI
- help
- Number of data bytes in one page for the NAND chip on the
- board, not including the OOB area.
-
-config SYS_NAND_OOBSIZE
- hex "NAND chip OOB size"
- depends on ARCH_SUNXI
- help
- Number of bytes in the Out-Of-Band area for the NAND chip on
- the board.
-
-# Enhance depends when converting drivers to Kconfig which use this config
-# option (mxc_nand, ndfc, omap_gpmc).
-config SYS_NAND_BUSWIDTH_16BIT
- bool "Use 16-bit NAND interface"
- depends on NAND_VF610_NFC || NAND_OMAP_GPMC || NAND_MXC || ARCH_DAVINCI
- help
- Indicates that NAND device has 16-bit wide data-bus. In absence of this
- config, bus-width of NAND device is assumed to be either 8-bit and later
- determined by reading ONFI params.
- Above config is useful when NAND device's bus-width information cannot
- be determined from on-chip ONFI params, like in following scenarios:
- - SPL boot does not support reading of ONFI parameters. This is done to
- keep SPL code foot-print small.
- - In current U-Boot flow using nand_init(), driver initialization
- happens in board_nand_init() which is called before any device probe
- (nand_scan_ident + nand_scan_tail), thus device's ONFI parameters are
- not available while configuring controller. So a static CONFIG_NAND_xx
- is needed to know the device's bus-width in advance.
-
-if SPL
-
-config SYS_NAND_U_BOOT_LOCATIONS
- bool "Define U-boot binaries locations in NAND"
- help
- Enable CONFIG_SYS_NAND_U_BOOT_OFFS though Kconfig.
- This option should not be enabled when compiling U-boot for boards
- defining CONFIG_SYS_NAND_U_BOOT_OFFS in their include/configs/<board>.h
- file.
-
-config SYS_NAND_U_BOOT_OFFS
- hex "Location in NAND to read U-Boot from"
- default 0x800000 if NAND_SUNXI
- depends on SYS_NAND_U_BOOT_LOCATIONS
- help
- Set the offset from the start of the nand where u-boot should be
- loaded from.
-
-config SYS_NAND_U_BOOT_OFFS_REDUND
- hex "Location in NAND to read U-Boot from"
- default SYS_NAND_U_BOOT_OFFS
- depends on SYS_NAND_U_BOOT_LOCATIONS
- help
- Set the offset from the start of the nand where the redundant u-boot
- should be loaded from.
-
-config SPL_NAND_AM33XX_BCH
- bool "Enables SPL-NAND driver which supports ELM based"
- depends on NAND_OMAP_GPMC && !OMAP34XX
- default y
- help
- Hardware ECC correction. This is useful for platforms which have ELM
- hardware engine and use NAND boot mode.
- Some legacy platforms like OMAP3xx do not have in-built ELM h/w engine,
- so those platforms should use CONFIG_SPL_NAND_SIMPLE for enabling
- SPL-NAND driver with software ECC correction support.
-
-config SPL_NAND_DENALI
- bool "Support Denali NAND controller for SPL"
- help
- This is a small implementation of the Denali NAND controller
- for use on SPL.
-
-config SPL_NAND_SIMPLE
- bool "Use simple SPL NAND driver"
- depends on !SPL_NAND_AM33XX_BCH
- help
- Support for NAND boot using simple NAND drivers that
- expose the cmd_ctrl() interface.
-endif
-
diff --git a/drivers/mtd/nand/aml_nand/aml_hwctrl.h b/drivers/mtd/nand/aml_nand/aml_hwctrl.h
deleted file mode 100644
index 2d62d3a..0000000
--- a/drivers/mtd/nand/aml_nand/aml_hwctrl.h
+++ /dev/null
@@ -1,535 +0,0 @@
-#ifndef __AML_HWCTRL_H__
-#define __AML_HWCTRL_H__
-
-//#include <asm/arch/secure_apb.h>
-#include <asm/arch/cpu_sdio.h>
-#include <asm/io.h>
-#include <clk.h>
-#define AML_NAND_UBOOT
-#define NAND_TWB_TIME_CYCLE 10
-
-#define HHI_NAND_CLK_CNTL1 (0xff63c000 + (0x097 << 2))
-#define P_PAD_PULL_UP_EN_REG2 (volatile uint32_t *)(0xff634400 + (0x04a << 2))
-#define P_PERIPHS_PIN_MUX_7 (volatile uint32_t *)(0xff634400 + (0x0b7 << 2))
-#define P_PERIPHS_PIN_MUX_4 (volatile uint32_t *)(0xff634400 + (0x0b4 << 2))
-#define P_PERIPHS_PIN_MUX_0 (volatile uint32_t *)(0xff634400 + (0x0b0 << 2))
-#define P_PERIPHS_PIN_MUX_5 (volatile uint32_t *)(0xff634400 + (0x0b5 << 2))
-#define P_PAD_PULL_UP_EN_REG4 (volatile uint32_t *)(0xff634400 + (0x04c << 2))
-#define P_PERIPHS_PIN_MUX_1 (volatile uint32_t *)(0xff634400 + (0x0b1 << 2))
-#define P_PAD_PULL_UP_EN_REG0 (volatile uint32_t *)(0xff634400 + (0x048 << 2))
-#define P_PAD_PULL_UP_REG2 (volatile uint32_t *)(0xff634400 + (0x03c << 2))
-#define P_PAD_PULL_UP_REG4 (volatile uint32_t *)(0xff634400 + (0x03e << 2))
-#define P_PAD_PULL_UP_REG0 (volatile uint32_t *)(0xff634400 + (0x03a << 2))
-
-#define CONFIG_AMLOGIC_DM_FLASH
-
-#define CE_PAD_DEFAULT \
- ((AML_NAND_CE0) | \
- (AML_NAND_CE1 << 4) | \
- (AML_NAND_CE2 << 8) | \
- (AML_NAND_CE3 << 12))
-
-#define RB_PAD_DEFAULT (AML_NAND_CE0)
-#define MAX_CHIP_NUM 4
-
-/*** HW controller configuration ***/
-struct hw_controller {
-#ifdef CONFIG_AMLOGIC_DM_FLASH
- struct udevice *device;
-#endif
- u32 chip_selected;
- u32 rb_received;
- u8 chip_num;
- u32 ce_enable[MAX_CHIP_NUM];
- u32 rb_enable[MAX_CHIP_NUM];
- struct clk clk[4];
-
- void __iomem *reg_base;
- void __iomem *nand_clk_reg;
- void __iomem *nand_clk_reg1;
- u32 irq;
-};
-
-#ifndef AML_NAND_UBOOT
-#include <linux/types.h>
-#endif /* AML_NAND_UBOOT */
-
-#define NF_REG_INDEX 0
-#define EXTCLK_REG_INDEX 1
-#define EXTPORT_REG_INDEX 2
-
-#define RETURN_PAGE_ALL_0XFF 0x01
-#define RETURN_PAGE_NEED_READRETRY 0x02
-
-#ifdef AML_NAND_UBOOT
-#define MESON_CPU_MAJOR_ID_M8 0x19
-#define MESON_CPU_MAJOR_ID_GX 0x21
-#endif /* AML_NAND_UBOOT */
-
-#ifdef AML_NAND_UBOOT
-static inline int get_cpu_type(void)
-{
- return MESON_CPU_MAJOR_ID_GX;
-}
-#endif /* AML_NAND_UBOOT */
-
-#define NAND_CYCLE_DELAY ((get_cpu_type() >= MESON_CPU_MAJOR_ID_M8)?(84):(90))
-
-#ifdef AML_NAND_UBOOT
-/* gxb and later, for pxp and ic. */
-#define P_NAND_BASE (SD_EMMC_BASE_C | (1<<11))
-#define NAND_BASE_APB (P_NAND_BASE)
-#define NAND_CLK_REG (SD_EMMC_BASE_C)
-#endif /* AML_NAND_UBOOT */
-
-/* NAND Write Command And Read Status Register */
-#define P_NAND_CMD (0x00)
-/* NAND Configuration Register */
-#define P_NAND_CFG (0x04)
-/* NAND Data Address Register */
-#define P_NAND_DADR (0x08)
-/* NAND Information Address Register */
-#define P_NAND_IADR (0x0c)
-/* NAND Read Data Buffer Register */
-#define P_NAND_BUF (0x10)
-/* NAND Information Register */
-#define P_NAND_INFO (0x14)
-/* NAND DDR interface Register */
-#define P_NAND_DC (0x18)
-/* NAND DDR Address Register */
-#define P_NAND_ADR (0x1c)
-/* NAND DDR Low 32 bits Data Register */
-#define P_NAND_DL (0x20)
-/* NAND DDR High 32 bits Data Register */
-#define P_NAND_DH (0x24)
-/* NAND Command Queus Address Register */
-#define P_NAND_CADR (0x28)
-/* NAND Status Address Register */
-#define P_NAND_SADR (0x2c)
-/* NAND CS2: SDRAM/NAND pin sharing Register */
-#define P_NAND_PINS (0x30)
-/* NAND Version number Register */
-#define P_NAND_VER (0x38)
-
-/*...other way to access cfg...*/
-typedef union _nand_cfg {
- /** raw register data */
- u32 d;
- /** register bits */
- struct {
- u32 bus_cyc:5; //0
- u32 bus_tim:5; //5
- u32 sync:2; //10
- u32 cmd_start:1; //12
- u32 cmd_auto:1; //13
- u32 apb_mode:1; //14
- u32 spare_only:1; //15
- u32 sync_adj:1; //16
- u32 secure_des:1; //17
- u32 reserved18:2; //18
- u32 sts_irq_en:1; //20
- u32 cmd_irq_en:1; //21
- u32 reserved22:4; //25
- u32 oob_on:1; //26
- u32 oob_mode:1; //27
- u32 dc_ugt:1; //28
- u32 nand_wpn:1; //29
- u32 dma_power:1; //30
- u32 bus_power:1; //31
- } b;
-} nand_cfg_t;
-
-typedef struct _nand_reg {
- volatile u32 cmd;
- volatile u32 cfg;
-} nand_reg_t;
-
-extern nand_reg_t *p_nand_reg;
-static inline u32 amlnf_read_reg32(volatile uint32_t *_reg)
-{
- /*---*/
-#ifndef AML_NAND_UBOOT
- smp_rmb();
-#endif /* AML_NAND_UBOOT */
- return __raw_readl(_reg);
-};
-
-static inline void amlnf_write_reg32(volatile uint32_t *_reg,
- const u32 _value)
-{
- __raw_writel(_value, _reg);
- /*---*/
-#ifndef AML_NAND_UBOOT
- smp_mb();
-#endif /* AML_NAND_UBOOT */
-};
-
-static inline void amlnf_set_reg32_bits(volatile uint32_t *_reg,
- const u32 _value,
- const u32 _start,
- const u32 _len)
-{
- /*---*/
-#ifndef AML_NAND_UBOOT
- smp_rmb();
-#endif /* AML_NAND_UBOOT */
- __raw_writel(((__raw_readl(_reg) & ~(((1L << (_len))-1) << (_start)))
- | ((u32)((_value)&((1L<<(_len))-1)) << (_start))), _reg);
- /*---*/
-#ifndef AML_NAND_UBOOT
- smp_wmb();
-#endif /* AML_NAND_UBOOT */
-}
-
-static inline void amlnf_clrset_reg32_bits(volatile uint32_t *_reg,
- const u32 clr,
- const u32 set)
-{
- /*---*/
-#ifndef AML_NAND_UBOOT
- smp_rmb();
-#endif /* AML_NAND_UBOOT */
- __raw_writel((__raw_readl(_reg) & ~(clr)) | (set), _reg);
- /*---*/
-#ifndef AML_NAND_UBOOT
- smp_wmb();
-#endif /* AML_NAND_UBOOT */
-}
-
-static inline u32 amlnf_get_reg32_bits(volatile uint32_t *_reg,
- const u32 _start,
- const u32 _len)
-{
- /*---*/
-#ifndef AML_NAND_UBOOT
- smp_rmb();
-#endif /* AML_NAND_UBOOT */
- return (__raw_readl(_reg) >> (_start)) & ((1L << (_len)) - 1);
-}
-
-static inline void amlnf_set_reg32_mask(volatile uint32_t *_reg,
- const u32 _mask)
-{
- /*---*/
-#ifndef AML_NAND_UBOOT
- smp_rmb();
-#endif /* AML_NAND_UBOOT */
- __raw_writel((__raw_readl(_reg) | (_mask)), _reg);
- /*---*/
-#ifndef AML_NAND_UBOOT
- smp_wmb();
-#endif /* AML_NAND_UBOOT */
-}
-
-static inline void amlnf_clr_reg32_mask(volatile uint32_t *_reg,
- const u32 _mask)
-{
- /*---*/
-#ifndef AML_NAND_UBOOT
- smp_rmb();
-#endif /* AML_NAND_UBOOT */
- __raw_writel((__raw_readl(_reg) & (~(_mask))), _reg);
- /*---*/
-#ifndef AML_NAND_UBOOT
- smp_wmb();
-#endif /* AML_NAND_UBOOT */
-}
-
-/*
-#define nfc_readl(host, reg) \
- __raw_readl((host)->reg_base + P_##reg)
-#define nfc_writel(host, reg, value) \
- __raw_writel((value), (host)->reg_base + P_##reg)
-#define nfc_readw(host, reg) \
- __raw_readw((host)->reg_base + P_##reg)
-#define nfc_writew(host, reg, value) \
- __raw_writew((value), (host)->reg_base + P_##reg)
- #define nfc_readb(host, reg) \
- __raw_readb((host)->reg_base + P_##reg)
-#define nfc_writeb(host, reg, value) \
- __raw_writeb((value), (host)->reg_base + P_##reg)
-
-#define nfc_set_bits(host, reg) \
- {\
- u32 value;\
- value = __raw_readl((host)->reg_base + P_##reg);\
- value &= ~((( 1L << (_len) )-1) << (_start)); \
- value |= ((u32)((_value)&((1L<<(_len))-1)) << (_start));\
- __raw_writel(value, (host)->reg_base + P_##reg);\
- }
-*/
-
-#define AMLNF_WRITE_REG(reg, val) (amlnf_write_reg32(reg, (val)))
-#define AMLNF_READ_REG(reg) (amlnf_read_reg32(reg))
-/*
-#define AMLNF_WRITE_REG_BITS(reg, val, start, len) \
- (amlnf_set_reg32_bits((volatile uint32_t *)(reg), (val), start, len))
-*/
-#define AMLNF_WRITE_REG_BITS(reg, val, start, len) \
- (amlnf_set_reg32_bits(reg, val, start, len))
-/*
-#define AMLNF_READ_REG_BITS(bus,reg, start, len) \
- (amlnf_get_reg32_bits(reg,start,len))
-*/
-/*
-#define AMLNF_CLEAR_REG_MASK(reg, mask) \
- (amlnf_clr_reg32_mask((volatile uint32_t *)(reg), (mask)))
-#define AMLNF_SET_REG_MASK(reg, mask) \
- (amlnf_set_reg32_mask((volatile uint32_t *)(reg), (mask)))
-*/
-#define AMLNF_CLEAR_REG_MASK(reg, mask) (amlnf_clr_reg32_mask(reg, mask))
-#define AMLNF_SET_REG_MASK(reg, mask) (amlnf_set_reg32_mask(reg, mask))
-
-/*
-#define NFC_SET_TIMING(host, mode, cycles, adjust) \
- AMLNF_WRITE_REG_BITS((host)->reg_base + P_NAND_CFG, \
- ((cycles)|((adjust&0xf)<<10)|((mode&7)<<5)), 0, 14)
-#define NFC_SET_CMD_START(host) \
- AMLNF_SET_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<12)
-
-#define NFC_SET_CMD_AUTO(host) \
- AMLNF_SET_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<13)
-
-#define NFC_SET_STS_IRQ(host, en) \
- AMLNF_WRITE_REG_BITS((host)->reg_base + P_NAND_CFG, en, 20, 1)
-
-#define NFC_SET_CMD_IRQ(host, en) \
- AMLNF_WRITE_REG_BITS((host)->reg_base + P_NAND_CFG, en, 21, 1)
-*/
-#define NFC_SET_TIMING_ASYC(host, bus_tim, bus_cyc) \
- AMLNF_WRITE_REG_BITS((host)->reg_base + P_NAND_CFG, \
- ((bus_cyc&31)|((bus_tim&31)<<5)|(0<<10)), \
- 0, \
- 12)
-/*
-#define NFC_SET_TIMING_SYNC(host, bus_tim, bus_cyc, sync_mode) \
- AMLNF_WRITE_REG_BITS((host)->reg_base + P_NAND_CFG, \
- (bus_cyc&31)|((bus_tim&31)<<5)|((sync_mode&2)<<10), \
- 0, \
- 12)
-#define NFC_SET_TIMING_SYNC_ADJUST()
-#define NFC_SET_DMA_MODE(host, is_apb, spare_only) \
- AMLNF_WRITE_REG_BITS((host)->reg_base + P_NAND_CFG, \
- ((spare_only<<1)|(is_apb)), \
- 14, \
- 2)
-*/
-#define NFC_SET_OOB_MODE(host, mode) \
- AMLNF_SET_REG_MASK((host)->reg_base + P_NAND_CFG, mode);
-#define NFC_CLR_OOB_MODE(host, mode) \
- AMLNF_CLEAR_REG_MASK((host)->reg_base + P_NAND_CFG, mode);
-/*
-#define NFC_ENABLE_STS_IRQ(host) \
- AMLNF_SET_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<20)
-#define NFC_DISABLE_STS_IRQ(host) \
- AMLNF_CLEAR_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<20)
-*/
-#define NFC_ENABLE_IO_IRQ(host) \
- AMLNF_SET_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<21)
-#define NFC_DISABLE_IO_IRQ(host) \
- AMLNF_CLEAR_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<21)
-
-#define NFC_ENABLE_ENCRYPT(host) \
- AMLNF_SET_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<17)
-#define NFC_DISABLE_ENCRYPT(host) \
- AMLNF_CLEAR_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<17)
-
-
-/**
- ADDR operations
-*/
-#define NFC_SET_DADDR(host, a) \
- (AMLNF_WRITE_REG((host)->reg_base + P_NAND_DADR, (u32)a))
-#define NFC_SET_IADDR(host, a) \
- (AMLNF_WRITE_REG((host)->reg_base + P_NAND_IADR, (u32)a))
-#define NFC_SET_SADDR(host, a) \
- (AMLNF_WRITE_REG((host)->reg_base + P_NAND_SADR, (u32)a))
-
-#define NFC_INFO_GET(host) \
- (AMLNF_READ_REG((host)->reg_base + P_NAND_CMD))
-
-#define NFC_GET_BUF(host) \
- AMLNF_READ_REG((host)->reg_base + P_NAND_BUF)
-#define NFC_SET_CFG(host, val) \
- (AMLNF_WRITE_REG((host)->reg_base + P_NAND_CFG, (u32)val))
-
-/*Common Nand Read Flow*/
- #define CE0 (0xe<<10)
-#define CE1 (0xd<<10)
-#define CE2 (0xb<<10)
-#define CE3 (0x7<<10)
-#define CE_NOT_SEL (0xf<<10)
-#define IO4 ((0xe<<10)|(1<<18))
-#define IO5 ((0xd<<10)|(1<<18))
-#define IO6 ((0xb<<10)|(1<<18))
-#define CLE (0x5<<14)
-#define ALE (0x6<<14)
-#define DWR (0x4<<14)
-#define DRD (0x8<<14)
-#define IDLE (0xc<<14)
-#define RB (1<<20)
-#define STANDBY (0xf<<10)
-
-#define M2N ((0<<17) | (2<<20) | (1<<19))
-#define N2M ((1<<17) | (2<<20) | (1<<19))
-
-#define M2N_NORAN 0x00200000
-#define N2M_NORAN 0x00220000
-
-#define STS ((3<<17) | (2<<20))
-#define ADL ((0<<16) | (3<<20))
-#define ADH ((1<<16) | (3<<20))
-#define AIL ((2<<16) | (3<<20))
-#define AIH ((3<<16) | (3<<20))
-#define ASL ((4<<16) | (3<<20))
-#define ASH ((5<<16) | (3<<20))
-#define SEED ((8<<16) | (3<<20))
-
-#define SEED_OFFSET 0xc2
-
-#define NFC_CMD_IDLE(ce, time) ((ce)|IDLE|(time&0x3ff))
-#define NFC_CMD_CLE(ce, cmd) ((ce)|CLE | (cmd & 0x0ff))
-#define NFC_CMD_ALE(ce, addr) ((ce)|ALE | (addr&0x0ff))
-#define NFC_CMD_STANDBY(time) (STANDBY | (time&0x3ff))
-#define NFC_CMD_ADL(addr) (ADL | (addr&0xffff))
-#define NFC_CMD_ADH(addr) (ADH|((addr>>16)&0xffff))
-#define NFC_CMD_AIL(addr) (AIL | (addr&0xffff))
-#define NFC_CMD_AIH(addr) (AIH|((addr>>16)&0xffff))
-#define NFC_CMD_DWR(ce, data) (ce|DWR | (data&0xff))
-#define NFC_CMD_DRD(ce, size) (ce|DRD|size)
-#define NFC_CMD_RB(ce, time) ((ce)|RB | (time&0x1f))
-#define NFC_CMD_RB_INT(ce, time) \
- ((ce)|RB|(((ce>>10)^0xf)<<14)|(time&0x1f))
-#define NFC_CMD_RBIO(time, io) (RB|io|(time&0x1f))
-#define NFC_CMD_RBIO_IRQ(time) (RB|IO6|(1<<16)|(time&0x1f))
-#define NFC_CMD_RBIO_INT(io, time) (RB|(((io>>10)^0x7)<<14)|(time&0x1f))
-#define NFC_CMD_SEED(seed) (SEED|(SEED_OFFSET + (seed&0x7fff)))
-#define NFC_CMD_STS(tim) (STS|(tim&3))
-#define NFC_CMD_M2N(ran, ecc, sho, pgsz, pag) \
- ((ran?M2N:M2N_NORAN)|(ecc<<14)|(sho<<13)|((pgsz&0x7f)<<6)|(pag&0x3f))
-#define NFC_CMD_N2M(ran, ecc, sho, pgsz, pag)\
- ((ran?N2M:N2M_NORAN)|(ecc<<14)|(sho<<13)|((pgsz&0x7f)<<6)|(pag&0x3f))
-
-/**
-Alias for CMD
-#define NFC_CMD_D_ADR(addr) NFC_CMD_ADL(addr), NFC_CMD_ADH(addr)
-#define NFC_CMD_I_ADR(addr) NFC_CMD_ADI(addr), NFC_CMD_ADI(addr)
-*/
-#define NAND_ECC_NONE (0x0)
-#define NAND_ECC_BCH8 (0x1)
-#define NAND_ECC_BCH8_1K (0x2)
-#define NAND_ECC_BCH24_1K (0x3)
-#define NAND_ECC_BCH30_1K (0x4)
-#define NAND_ECC_BCH40_1K (0x5)
-#define NAND_ECC_BCH50_1K (0x6)
-/*NAND_ECC_BCH50_1K only for mtd general*/
-#define NAND_ECC_BCH60_1K (0x7)
-#define NAND_ECC_BCH_SHORT (0x8)
-
-#define PER_INFO_BYTE 8
-/*Register Operation and Controller Status*/
-#define NFC_SEND_CMD(host, cmd) \
- (AMLNF_WRITE_REG((host)->reg_base + P_NAND_CMD, cmd))
-#define NFC_READ_INFO(host) \
- (AMLNF_READ_REG((host)->reg_base + P_NAND_CMD))
-
-/*Send command directly*/
-#define NFC_SEND_CMD_IDLE(host, time) \
- {\
- while (NFC_CMDFIFO_SIZE(host) > 0)\
- ; \
- NFC_SEND_CMD(host, NFC_CMD_IDLE((host)->chip_selected, time)); \
- }
-#define NFC_SEND_CMD_CLE(host, ce, cmd) \
- NFC_SEND_CMD(host, NFC_CMD_CLE(ce, cmd))
-#define NFC_SEND_CMD_ALE(host, ce, addr) \
- NFC_SEND_CMD(host, NFC_CMD_ALE(ce, addr))
-#define NFC_SEND_CMD_STANDBY(host, time) \
- NFC_SEND_CMD(host, NFC_CMD_STANDBY(time))
-#define NFC_SEND_CMD_ADL(host, addr) \
- NFC_SEND_CMD(host, NFC_CMD_ADL(addr))
-#define NFC_SEND_CMD_ADH(host, addr) \
- NFC_SEND_CMD(host, NFC_CMD_ADH(addr))
-#define NFC_SEND_CMD_AIL(host, addr) \
- NFC_SEND_CMD(host, NFC_CMD_AIL(addr))
-#define NFC_SEND_CMD_AIH(host, addr) \
- NFC_SEND_CMD(host, NFC_CMD_AIH(addr))
-#define NFC_SEND_CMD_DWR(host, ce, data) \
- NFC_SEND_CMD(host, NFC_CMD_DWR(ce, data))
-#define NFC_SEND_CMD_DRD(host, ce, size) \
- NFC_SEND_CMD(host, NFC_CMD_DRD(ce, size))
-#define NFC_SEND_CMD_RB(host, ce, time) \
- NFC_SEND_CMD(host, NFC_CMD_RB(ce, time))
-#define NFC_SEND_CMD_SEED(host, seed) \
- NFC_SEND_CMD(host, NFC_CMD_SEED(seed))
-#define NFC_SEND_CMD_M2N(host, ran, ecc, sho, pgsz, pag) \
- NFC_SEND_CMD(host, NFC_CMD_M2N(ran, ecc, sho, pgsz, pag))
-#define NFC_SEND_CMD_N2M(host, ran, ecc, sho, pgsz, pag) \
- NFC_SEND_CMD(host, NFC_CMD_N2M(ran, ecc, sho, pgsz, pag))
-
-#define NFC_SEND_CMD_M2N_RAW(host, ran, len) \
- NFC_SEND_CMD(host, (ran?M2N:M2N_NORAN)|(len&0x3fff))
-#define NFC_SEND_CMD_N2M_RAW(host, ran, len) \
- NFC_SEND_CMD(host, (ran?N2M:N2M_NORAN)|(len&0x3fff))
-
-#define NFC_SEND_CMD_STS(host, time, irq) \
- NFC_SEND_CMD(host, NFC_CMD_STS(time | irq))
-
-#define NFC_SEND_CMD_RB_IRQ(host, time) \
- NFC_SEND_CMD(host, NFC_CMD_RBIO_IRQ(time))
-
-/*Cmd Info Macros*/
-#define NFC_CMDFIFO_SIZE(host) ((NFC_INFO_GET(host)>>22)&0x1f)
-#define NFC_CHECEK_RB_TIMEOUT(host) ((NFC_INFO_GET(host)>>27)&0x1)
-#define NFC_FIFO_CUR_CMD(host) ((NFC_INFO_GET(host)>>22)&0x3FFFFF)
-#define NFC_GET_RB_STATUS(host, ce) \
- (((NFC_INFO_GET(host)>>28)&(~(ce>>10)))&0xf)
-
-
-#define NAND_INFO_DONE(a) (((a)>>31)&1)
-#define NAND_ECC_ENABLE(a) (((a)>>30)&1)
-#define NAND_ECC_CNT(a) (((a)>>24)&0x3f)
-#define NAND_ZERO_CNT(a) (((a)>>16)&0x3f)
-#define NAND_INFO_DATA_2INFO(a) ((a)&0xffff)
-#define NAND_INFO_DATA_1INFO(a) ((a)&0xff)
-
-#define POR_CONFIG READ_CBUS_REG(ASSIST_POR_CONFIG)
-
-#define POC_NAND_CFG (1<<2)
-#define POC_NAND_NO_RB (1<<0)
-#define POC_NAND_ASYNC (1<<7)
-/*nand relate define for hw controller*/
-/*ecc type define*/
-#define NAND_ECC_SOFT_MODE 0x00000000
-#define NAND_ECC_SHORT_MODE 0x00000001
-#define NAND_ECC_BCH9_MODE 0x00000002
-#define NAND_ECC_BCH8_MODE 0x00000003
-#define NAND_ECC_BCH12_MODE 0x00000004
-#define NAND_ECC_BCH16_MODE 0x00000005
-#define NAND_ECC_BCH8_1K_MODE 0x00000006
-#define NAND_ECC_BCH16_1K_MODE 0x00000007
-#define NAND_ECC_BCH24_1K_MODE 0x00000008
-#define NAND_ECC_BCH30_1K_MODE 0x00000009
-#define NAND_ECC_BCH40_1K_MODE 0x0000000a
-#define NAND_ECC_BCH50_1K_MODE 0x0000000b
-#define NAND_ECC_BCH60_1K_MODE 0x0000000c
-
-/*ecc page unit define*/
-#define NAND_ECC_UNIT_SIZE 512
-#define NAND_ECC_UNIT_1KSIZE 1024
-#define NAND_ECC_UNIT_SHORT 384
-
-/*ecc type oob size(bytes) needed*/
-#define NAND_BCH9_ECC_SIZE 15
-#define NAND_BCH8_ECC_SIZE 14
-#define NAND_BCH12_ECC_SIZE 20
-#define NAND_BCH16_ECC_SIZE 26
-#define NAND_BCH8_1K_ECC_SIZE 14
-#define NAND_BCH16_1K_ECC_SIZE 28
-#define NAND_BCH24_1K_ECC_SIZE 42
-#define NAND_BCH30_1K_ECC_SIZE 54
-#define NAND_BCH40_1K_ECC_SIZE 70
-#define NAND_BCH50_1K_ECC_SIZE 88
-#define NAND_BCH60_1K_ECC_SIZE 106
-
-#endif /* __HW_CTRL_H__ */
\ No newline at end of file
diff --git a/drivers/mtd/nand/aml_nand/aml_nand.c b/drivers/mtd/nand/aml_nand/aml_nand.c
deleted file mode 100644
index 257c638..0000000
--- a/drivers/mtd/nand/aml_nand/aml_nand.c
+++ /dev/null
@@ -1,2310 +0,0 @@
-#include <common.h>
-#include <environment.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <linux/err.h>
-#include <asm/cache.h>
-//#include <asm/arch/secure_apb.h>
-#include <asm/arch-g12a/cpu_id.h>
-#include <linux/log2.h>
-#include <dm/pinctrl.h>
-#include <dm/uclass.h>
-#include <dm/device.h>
-
-#include "aml_nand.h"
-#include <time.h> /*test*/
-
-#if 0
-#define aml_nand_debug(a...) \
- { printk("%s()[%s,%d]",__func__,__FILE__,__LINE__); printk(a); }
-#else
-#define aml_nand_debug(a...)
-#endif
-
-//extern int aml_nand_scan_bbt(struct mtd_info *mtd);
-extern int aml_nand_scan_shipped_bbt(struct mtd_info *mtd);
-
-uint8_t nand_boot_flag = 0;
-extern unsigned char pagelist_1ynm_hynix256_mtd[128];
-extern struct aml_nand_flash_dev aml_nand_flash_ids[];
-extern struct hw_controller *controller;
-
-#define NAND_CMD_SANDISK_DSP_OFF 0x25
-#define SANDISK_A19NM_4G 53
-#define INTEL_20NM 60
-
-#define SZ_1M 0x100000
-extern struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
-
-/*
-* mtd nand partition table, only care the size!
-* offset will be calculated by nand driver.
-*/
-static struct mtd_partition normal_partition_info[] = {
-#ifdef CONFIG_DISCRETE_BOOTLOADER
-/* MUST NOT CHANGE this part unless u know what you are doing!
-* inherent parition for descrete bootloader to store fip
-* size is determind by TPL_SIZE_PER_COPY*TPL_COPY_NUM
-* name must be same with TPL_PART_NAME
-*/
-{
- .name = "tpl",
- .offset = 0,
- .size = 0,
-},
-#endif
-{
- .name = "logo",
- .offset = 0,
- .size = 2*SZ_1M,
-},
-{
- .name = "recovery",
- .offset = 0,
- .size = 16*SZ_1M,
-},
-{
- .name = "boot",
- .offset = 0,
- .size = 15*SZ_1M,
-},
-{
- .name = "system",
- .offset = 0,
- .size = 280*SZ_1M,
-},
-/* last partition get the rest capacity */
-{
- .name = "data",
- .offset = MTDPART_OFS_APPEND,
- .size = MTDPART_SIZ_FULL,
-},
-};
-
-struct mtd_partition *get_aml_mtd_partition(void)
-{
- return normal_partition_info;
-}
-
-int get_aml_partition_count(void)
-{
- return ARRAY_SIZE(normal_partition_info);
-}
-
-
-static struct nand_ecclayout aml_nand_uboot_oob = {
- .eccbytes = 84,
- .oobfree = {
- {.offset = 0,
- .length = 6}}
-};
-
-static struct nand_ecclayout aml_nand_oob_64 = {
- .eccbytes = 56,
- .oobfree = {
- {.offset = 0,
- .length = 8}}
-};
-
-static struct nand_ecclayout aml_nand_oob_128 = {
- .eccbytes = 120,
- .oobfree = {
- {.offset = 0,
- .length = 8}}
-};
-
-static struct nand_ecclayout aml_nand_oob_218 = {
- .eccbytes = 200,
- .oobfree = {
- {.offset = 0,
- .length = 8}}
-};
-
-static struct nand_ecclayout aml_nand_oob_224 = {
- .eccbytes = 208,
- .oobfree = {
- {.offset = 0,
- .length = 8}}
-};
-
-static struct nand_ecclayout aml_nand_oob_256 = {
- .eccbytes = 240,
- .oobfree = {
- {.offset = 0,
- .length = 16}}
-};
-
-static struct nand_ecclayout aml_nand_oob_376 = {
- .eccbytes = 352,
- .oobfree = {
- {.offset = 0,
- .length = 16}}
-};
-
-static struct nand_ecclayout aml_nand_oob_436 = {
- .eccbytes = 352,
- .oobfree = {
- {.offset = 0,
- .length = 16}}
-};
-
-static struct nand_ecclayout aml_nand_oob_448 = {
- .eccbytes = 416,
- .oobfree = {
- {.offset = 0,
- .length = 16}}
-};
-
-static struct nand_ecclayout aml_nand_oob_640 = {
- .eccbytes = 608,
- .oobfree = {
- {.offset = 0,
- .length = 16}}
-};
-
-static struct nand_ecclayout aml_nand_oob_744 = {
- .eccbytes = 700,
- .oobfree = {
- {.offset = 0,
- .length = 16}}
-};
-
-static struct nand_ecclayout aml_nand_oob_1280 = {
- .eccbytes = 1200,
- .oobfree = {
- {.offset = 0,
- .length = 32}}
-};
-
-static struct nand_ecclayout aml_nand_oob_1664 = {
- .eccbytes = 1584,
- .oobfree = {
- {.offset = 0,
- .length = 32}}
-};
-
-void aml_platform_get_user_byte(struct aml_nand_chip *aml_chip,
- unsigned char *oob_buf, int byte_num)
-{
- int read_times = 0;
- unsigned int len = PER_INFO_BYTE / sizeof(unsigned int);
-
- while (byte_num > 0) {
- *oob_buf++ = (aml_chip->user_info_buf[read_times*len] & 0xff);
- byte_num--;
- if (aml_chip->user_byte_mode == 2) {
- *oob_buf++ =
- ((aml_chip->user_info_buf[read_times*len] >> 8) & 0xff);
- byte_num--;
- }
- read_times++;
- }
-}
-
-void aml_platform_set_user_byte(struct aml_nand_chip *aml_chip,
- unsigned char *oob_buf, int byte_num)
-{
- int write_times = 0;
- unsigned int len = PER_INFO_BYTE/sizeof(unsigned int);
-
- while (byte_num > 0) {
- aml_chip->user_info_buf[write_times*len] = *oob_buf++;
- byte_num--;
- if (aml_chip->user_byte_mode == 2) {
- aml_chip->user_info_buf[write_times*len] |=
- (*oob_buf++ << 8);
- byte_num--;
- }
- write_times++;
- }
-}
-
-int aml_nand_block_bad_scrub_update_bbt(struct mtd_info *mtd)
-{
- return 0;
-}
-
-/****get partition table****/
-static int aml_nand_add_partition(struct aml_nand_chip *aml_chip)
-{
- struct nand_chip *chip = &aml_chip->chip;
- struct mtd_info *mtd = &chip->mtd;
- struct aml_nand_platform *plat = aml_chip->platform;
-#ifdef CONFIG_MTD_PARTITIONS
- struct mtd_partition *temp_parts = NULL;
- struct mtd_partition *parts;
- int nr, i, ret = 0;
- loff_t adjust_offset = 0;
- uint64_t part_size = 0;
- int reserved_part_blk_num = NAND_RSV_BLOCK_NUM;
- uint64_t fip_part_size = 0;
- int normal_base = 0;
-#ifndef CONFIG_NOT_SKIP_BAD_BLOCK
- int phys_erase_shift, error = 0;
- uint64_t start_blk = 0, part_blk = 0;
- loff_t offset;
-
- phys_erase_shift = fls(mtd->erasesize) - 1;
-#endif
-
- if (!strncmp((char*)plat->name,
- NAND_BOOT_NAME, strlen((const char*)NAND_BOOT_NAME))) {\
- /* boot partition must be set as this because of romboot restrict */
- parts = kzalloc(sizeof(struct mtd_partition),
- GFP_KERNEL);
- if (!parts)
- return -ENOMEM;
- parts->name = NAND_BOOT_NAME;
- parts->offset = 0;
- parts->size = (mtd->writesize * 1024);
- nr = 1;
- nand_boot_flag = 1;
- } else {
- /* normal partitions */
- parts = get_aml_mtd_partition();
- nr = get_aml_partition_count();
- if (nand_boot_flag)
- adjust_offset =
- (1024 * mtd->writesize / aml_chip->plane_num);
- #ifdef CONFIG_DISCRETE_BOOTLOADER
- /* reserved area size is fixed 48 blocks and
- * have fip between rsv and normal, so
- * don't skip factory bad block and set fip part size.
- */
- fip_part_size = CONFIG_TPL_SIZE_PER_COPY * CONFIG_TPL_COPY_NUM;
- /* TODO: add fip 2 partition list */
- temp_parts = parts;
- if (strcmp(BOOT_TPL, temp_parts->name)) {
- printf("nand: double check your mtd partition table!\n");
- printf("%s should be the 1st part!\n", BOOT_TPL);
- return -ENODEV;
- }
- if (temp_parts->size) {
- printf("nand: size of %s should not be pre-set\n",
- temp_parts->name);
- printf("it's should be determined by TPL_COPY_NUM*TPL_SIZE_PER_COPY\n");
- printf("which is %lld\n", fip_part_size);
- }
- temp_parts->offset = adjust_offset + reserved_part_blk_num * mtd->erasesize;
- temp_parts->size = fip_part_size;
- printf("%s : off %lld, size %lld\n", temp_parts->name,
- temp_parts->offset, temp_parts->size);
- normal_base = 1;
- #endif /* CONFIG_DISCRETE_BOOTLOADER */
- adjust_offset += reserved_part_blk_num * mtd->erasesize
- + fip_part_size;
- for (i = normal_base; i < nr; i++) {
- temp_parts = parts + i;
- if (mtd->size < adjust_offset) {
- printf("%s %d error : over the nand size!!!\n",
- __func__, __LINE__);
- return -ENOMEM;
- }
- temp_parts->offset = adjust_offset;
- part_size = temp_parts->size;
- if (i == nr - 1)
- part_size = mtd->size - adjust_offset;
- #ifndef CONFIG_NOT_SKIP_BAD_BLOCK
- offset = 0;
- start_blk = 0;
- part_blk = part_size >> phys_erase_shift;
-
- do {
- offset = adjust_offset + start_blk *
- mtd->erasesize;
-
- error = mtd->_block_isbad(mtd, offset);
-
- if (error) {
- pr_info("%s:%d factory bad addr=%llx\n",
- __func__, __LINE__,
- (uint64_t)(offset >>
- phys_erase_shift));
- if (i != nr - 1) {
- adjust_offset += mtd->erasesize;
- continue;
- }
- }
- start_blk++;
- } while (start_blk < part_blk);
- #endif
- if (temp_parts->name == NULL) {
- temp_parts->name =
- kzalloc(MAX_MTD_PART_NAME_LEN,
- GFP_KERNEL);
- if (!temp_parts->name)
- return -ENOMEM;
- sprintf((char *)temp_parts->name,
- "mtd%d", nr);
- }
- adjust_offset += part_size;
- temp_parts->size = adjust_offset - temp_parts->offset;
- }
- }
- ret = add_mtd_partitions(mtd, parts, nr);
- if (nr == 1)
- kfree(parts);
- return ret;
-#else
- return add_mtd_device(mtd);
-#endif
-}
-
-#ifndef P_PAD_DS_REG0A
-#define P_PAD_DS_REG0A (volatile uint32_t *)(0xff634400 + (0x0d0 << 2))
-#endif
-void nand_get_chip(void *chip)
-{
-
- struct aml_nand_chip *aml_chip = (struct aml_nand_chip *)chip;
- struct hw_controller *controller = aml_chip->controller;
- int retry = 0, ret = 0;
-
- while (1) {
- ret = pinctrl_select_state(controller->device, "default");
- if (!ret) {
- if (aml_chip->aml_nand_adjust_timing)
- aml_chip->aml_nand_adjust_timing(aml_chip);
- break;
- }
-
- if (retry++ > 10) {
- pr_info("get pin fail over 10 times retry=%d\n",
- retry);
- break;
- }
- }
-
-}
-
-
-static void inline nand_release_chip(void)
-{
- NFC_SEND_CMD_STANDBY(controller, 5);
-
- return;
-}
-
-static void aml_nand_select_chip(struct mtd_info *mtd, int chipnr)
-{
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
-
- switch (chipnr) {
- case -1:
- nand_release_chip();
- break;
- case 0:
- nand_get_chip(aml_chip);
- aml_chip->aml_nand_select_chip(aml_chip, chipnr);
- break;
- case 1:
- case 2:
- case 3:
- aml_chip->aml_nand_select_chip(aml_chip, chipnr);
- break;
-
- default:
- BUG();
- }
- return;
-}
-
-void aml_platform_cmd_ctrl(struct aml_nand_chip *aml_chip,
- int cmd, unsigned int ctrl)
-{
- if (cmd == NAND_CMD_NONE)
- return;
-
- if (ctrl & NAND_CLE)
- cmd=NFC_CMD_CLE(controller->chip_selected, cmd);
- else
- cmd=NFC_CMD_ALE(controller->chip_selected, cmd);
-
- NFC_SEND_CMD(controller, cmd);
-}
-
-int aml_platform_wait_devready(struct aml_nand_chip *aml_chip, int chipnr)
-{
- struct nand_chip *chip = &aml_chip->chip;
- struct mtd_info *mtd = &chip->mtd;
- unsigned time_out_cnt = 0;
- int status;
-
- /* wait until command is processed or timeout occures */
- aml_chip->aml_nand_select_chip(aml_chip, chipnr);
-
- NFC_SEND_CMD_IDLE(controller, 0);
- NFC_SEND_CMD_IDLE(controller, 0);
- while (NFC_CMDFIFO_SIZE(controller) > 0);
-
- if (aml_chip->ops_mode & AML_CHIP_NONE_RB) {
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_STATUS, -1, -1, chipnr);
- udelay(2);
- NFC_SEND_CMD(controller, controller->chip_selected | IDLE | 0);
- NFC_SEND_CMD(controller, controller->chip_selected | IDLE | 0);
- while (NFC_CMDFIFO_SIZE(controller) > 0) ;
-
- do {
- status = (int)chip->read_byte(mtd);
- if (status & NAND_STATUS_READY)
- break;
- udelay(1);
- } while(time_out_cnt++ <= 0x1000); /*10ms max*/
-
- if (time_out_cnt > 0x1000)
- return 0;
- } else {
- do {
- if (chip->dev_ready(mtd))
- break;
- } while(time_out_cnt++ <= 0x40000);
-
- if (time_out_cnt > 0x40000)
- return 0;
- }
- return 1;
-}
-
-void aml_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
-{
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
-
- aml_chip->aml_nand_cmd_ctrl(aml_chip, cmd, ctrl);
-}
-
-int aml_nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
-{
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
- int status[MAX_CHIP_NUM], i = 0, time_cnt = 0;
- struct aml_nand_platform *plat = aml_chip->platform;
- int read_status =0;
- /* Apply this short delay always to ensure that we do wait tWB in
- * any case on any machine. */
- ndelay(100);
- /*SET_CBUS_REG_MASK(PREG_PAD_GPIO3_O, 1 << 11);*/
- for (i = 0; i < controller->chip_num; i++) {
- if (aml_chip->valid_chip[i]) {
- /*active ce for operation chip and send cmd*/
- aml_chip->aml_nand_select_chip(aml_chip, i);
-
- NFC_SEND_CMD(controller,
- controller->chip_selected | IDLE | 0);
- NFC_SEND_CMD(controller,
- controller->chip_selected | IDLE | 0);
- while (NFC_CMDFIFO_SIZE(controller)>0) ;
-
- /*if ((state == FL_ERASING)
- && (chip->options & NAND_IS_AND))
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_STATUS_MULTI, -1, -1, i);
- else*/
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_STATUS, -1, -1, i);
-
- NFC_SEND_CMD(controller,
- controller->chip_selected | IDLE | 0);
- NFC_SEND_CMD(controller,
- controller->chip_selected | IDLE | 0);
- while (NFC_CMDFIFO_SIZE(controller)>0) ;
-
- time_cnt = 0;
-retry_status:
- while (time_cnt++ < 0x40000) {
- if (chip->dev_ready) {
- if (chip->dev_ready(mtd))
- break;
- udelay(2);
- } else {
- /*if(time_cnt == 1)*/
- udelay(2);
- if (chip->read_byte(mtd) & NAND_STATUS_READY)
- break;
- /*aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_STATUS, -1, -1, i);
- udelay(50);*/
-
- }
- /*udelay(200);*/
- }
- status[i] = (int)chip->read_byte(mtd);
- /*printk("s:%x\n", status[i]);*/
- if ((read_status++ < 3) && (!(status[i] & NAND_STATUS_READY))) {
- printk("after wirte,read %d status =%d fail\n",
- read_status,status[i]);
- goto retry_status;
- }
- status[0] |= status[i];
- }
- }
- if (!strncmp((char*)plat->name,
- NAND_BOOT_NAME, strlen((const char*)NAND_BOOT_NAME)))
- status[0] = 0xe0;
-
- return status[0];
-}
-
-/*
- * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
- * a flash. NAND flash is initialized prior to interrupts so standard timers
- * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
- * which is greater than (max NAND reset time / NAND status read time).
- * A conservative default of 200000 (500 us / 25 ns) is used as a default.
- */
-#ifndef CONFIG_SYS_NAND_RESET_CNT
-#define CONFIG_SYS_NAND_RESET_CNT 200000
-#endif
-void aml_nand_base_command(struct aml_nand_chip *aml_chip,
- unsigned command, int column, int page_addr, int chipnr)
-{
- struct nand_chip *chip = &aml_chip->chip;
- struct mtd_info *mtd = &chip->mtd;
- unsigned command_temp;
- unsigned pages_per_blk_shift, plane_page_addr = 0, plane_blk_addr = 0;
-
- pages_per_blk_shift = (chip->phys_erase_shift - chip->page_shift);
- uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
- if (page_addr != -1) {
- page_addr /= aml_chip->plane_num;
- plane_page_addr =(page_addr & ((1 << pages_per_blk_shift) - 1));
- plane_blk_addr = (page_addr >> pages_per_blk_shift);
- plane_blk_addr = (plane_blk_addr << 1);
- }
-
- if (aml_chip->plane_num == 2) {
- switch (command) {
- case NAND_CMD_READ0:
- if ((aml_chip->mfr_type == NAND_MFR_MICRON)
- || (aml_chip->mfr_type == NAND_MFR_INTEL))
- command_temp = command;
- else {
- command_temp =
- NAND_CMD_TWOPLANE_PREVIOS_READ;
- column = -1;
- }
- plane_page_addr |=
- (plane_blk_addr << pages_per_blk_shift);
- break;
-
- case NAND_CMD_TWOPLANE_READ1:
- command_temp = NAND_CMD_READ0;
- if ((aml_chip->mfr_type == NAND_MFR_MICRON)
- || (aml_chip->mfr_type == NAND_MFR_INTEL))
- /*plane_page_addr |=
- ((plane_blk_addr + 1) << 8);*/
- return;
- else
- plane_page_addr |=
- (plane_blk_addr << pages_per_blk_shift);
- break;
-
- case NAND_CMD_TWOPLANE_READ2:
- if ((aml_chip->mfr_type == NAND_MFR_MICRON)
- || (aml_chip->mfr_type == NAND_MFR_INTEL))
- command_temp =
- NAND_CMD_PLANE2_READ_START;
- else
- command_temp = NAND_CMD_READ0;
- plane_page_addr |=
- ((plane_blk_addr + 1) << pages_per_blk_shift);
- break;
-
- case NAND_CMD_SEQIN:
- command_temp = command;
- plane_page_addr |=
- (plane_blk_addr << pages_per_blk_shift);
- break;
-
- case NAND_CMD_TWOPLANE_WRITE2:
- if ((aml_chip->mfr_type == NAND_MFR_HYNIX)
- || (aml_chip->mfr_type == NAND_MFR_SAMSUNG))
- command_temp = command;
- else
- command_temp =
- NAND_CMD_TWOPLANE_WRITE2_MICRO;
- plane_page_addr |=
- ((plane_blk_addr + 1) << pages_per_blk_shift);
- break;
-
- case NAND_CMD_ERASE1:
- command_temp = command;
- plane_page_addr |=
- (plane_blk_addr << pages_per_blk_shift);
- break;
-
- case NAND_CMD_MULTI_CHIP_STATUS:
- command_temp = command;
- plane_page_addr |=
- (plane_blk_addr << pages_per_blk_shift);
- break;
-
- default:
- command_temp = command;
- break;
-
- }
- chip->cmd_ctrl(mtd,
- command_temp & 0xff,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
-
- /*
- if ((command_temp == NAND_CMD_SEQIN)
- || (command_temp == NAND_CMD_TWOPLANE_WRITE2)
- || (command_temp == NAND_CMD_READ0))
- printk("plane_page_addr:%x plane_blk_addr:%x cmd:%x\n",
- plane_page_addr, plane_blk_addr, command);
- */
-
- if (column != -1 || page_addr != -1) {
- int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
- /* Serially input address */
- if (column != -1) {
- /* Adjust columns for 16 bit buswidth */
- if (chip->options & NAND_BUSWIDTH_16 &&
- !nand_opcode_8bits(command))
- column >>= 1;
- chip->cmd_ctrl(mtd, column, ctrl);
- ctrl &= ~NAND_CTRL_CHANGE;
- if (!nand_opcode_8bits(command))
- chip->cmd_ctrl(mtd, column >> 8, ctrl);
- }
- if (page_addr != -1) {
- chip->cmd_ctrl(mtd, plane_page_addr, ctrl);
- chip->cmd_ctrl(mtd,
- plane_page_addr >> 8, NAND_NCE | NAND_ALE);
- /* One more address cycle for devices > 128MiB*/
- if (chip->chipsize > (128 << 20))
- chip->cmd_ctrl(mtd,
- plane_page_addr >> 16, NAND_NCE | NAND_ALE);
- }
- }
-
- switch (command) {
- case NAND_CMD_READ0:
- plane_page_addr =
- page_addr % (1 << pages_per_blk_shift);
-
- if ((aml_chip->mfr_type == NAND_MFR_MICRON)
- || (aml_chip->mfr_type == NAND_MFR_INTEL)) {
- plane_page_addr |=
- ((plane_blk_addr + 1) << pages_per_blk_shift);
- command_temp = command;
- chip->cmd_ctrl(mtd,
- command_temp & 0xff,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
- } else {
- command_temp =
- NAND_CMD_TWOPLANE_PREVIOS_READ;
- column = -1;
- plane_page_addr |=
- ((plane_blk_addr + 1) << pages_per_blk_shift);
- chip->cmd_ctrl(mtd,
- command_temp & 0xff,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
- }
-
- break;
-
- case NAND_CMD_TWOPLANE_READ1:
- if ((aml_chip->mfr_type == NAND_MFR_MICRON)
- || (aml_chip->mfr_type == NAND_MFR_INTEL)) {
- page_addr = -1;
- column = -1;
- } else {
- command_temp = NAND_CMD_RNDOUT;
- page_addr = -1;
- chip->cmd_ctrl(mtd,
- command_temp & 0xff,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
- }
- break;
-
- case NAND_CMD_TWOPLANE_READ2:
- if ((aml_chip->mfr_type == NAND_MFR_MICRON)
- || (aml_chip->mfr_type == NAND_MFR_INTEL)) {
- page_addr = -1;
- column = -1;
- } else {
- command_temp = NAND_CMD_RNDOUT;
- page_addr = -1;
- chip->cmd_ctrl(mtd,
- command_temp & 0xff,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
- }
- break;
-
- case NAND_CMD_ERASE1:
- if ((aml_chip->mfr_type == NAND_MFR_MICRON)
- || (aml_chip->mfr_type == NAND_MFR_INTEL)) {
- command_temp = NAND_CMD_ERASE1_END;
- chip->cmd_ctrl(mtd,
- command_temp & 0xff,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
- aml_chip->aml_nand_wait_devready(aml_chip,
- chipnr);
- }
-
- command_temp = command;
- chip->cmd_ctrl(mtd,
- command_temp & 0xff,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
- plane_page_addr =
- page_addr % (1 << pages_per_blk_shift);
- plane_page_addr |=
- ((plane_blk_addr + 1) << pages_per_blk_shift);
- break;
-
- default:
- column = -1;
- page_addr = -1;
- break;
- }
-
- if (column != -1 || page_addr != -1) {
- int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
-
- /* Serially input address */
- if (column != -1) {
- /* Adjust columns for 16 bit buswidth */
- if (chip->options & NAND_BUSWIDTH_16 &&
- !nand_opcode_8bits(command))
- column >>= 1;
- chip->cmd_ctrl(mtd, column, ctrl);
- ctrl &= ~NAND_CTRL_CHANGE;
- if (!nand_opcode_8bits(command))
- chip->cmd_ctrl(mtd, column >> 8, ctrl);
- }
- if (page_addr != -1) {
- /*plane_page_addr |=
- (1 << (pages_per_blk_shift + 1));
- BUG_ON((plane_page_addr & 0x7FF) == 0);*/
-
- chip->cmd_ctrl(mtd, plane_page_addr, ctrl);
- chip->cmd_ctrl(mtd, plane_page_addr >> 8,
- NAND_NCE | NAND_ALE);
- /* One more address cycle for devices > 128MiB*/
- if (chip->chipsize > (128 << 20))
- chip->cmd_ctrl(mtd,
- plane_page_addr >> 16, NAND_NCE | NAND_ALE);
- }
- }
-
- if ((command == NAND_CMD_RNDOUT)
- || (command == NAND_CMD_TWOPLANE_READ2))
- chip->cmd_ctrl(mtd,
- NAND_CMD_RNDOUTSTART,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
- else if ((command == NAND_CMD_TWOPLANE_READ1))
- chip->cmd_ctrl(mtd,
- NAND_CMD_RNDOUTSTART,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
-
- else if (command == NAND_CMD_READ0)
- chip->cmd_ctrl(mtd,
- NAND_CMD_READSTART,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
-
- chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
- } else {
- chip->cmd_ctrl(mtd,
- command & 0xff,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
-
- if (column != -1 || page_addr != -1) {
- int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
-
- /* Serially input address */
- if (column != -1) {
- /* Adjust columns for 16 bit buswidth */
- if (chip->options & NAND_BUSWIDTH_16 &&
- !nand_opcode_8bits(command))
- column >>= 1;
- chip->cmd_ctrl(mtd, column, ctrl);
- ctrl &= ~NAND_CTRL_CHANGE;
- /* Only output a single addr
- * cycle for 8bits opcodes.
- */
- if (!nand_opcode_8bits(command))
- chip->cmd_ctrl(mtd, column >> 8, ctrl);
- }
- if (page_addr != -1) {
-
- chip->cmd_ctrl(mtd, page_addr, ctrl);
- chip->cmd_ctrl(mtd, page_addr >> 8,
- NAND_NCE | NAND_ALE);
- /* One more address cycle for devices > 128MiB*/
- if (chip->chipsize > (128 << 20))
- chip->cmd_ctrl(mtd,
- page_addr >> 16, NAND_NCE | NAND_ALE);
- }
- }
- if (command == NAND_CMD_RNDOUT)
- chip->cmd_ctrl(mtd,
- NAND_CMD_RNDOUTSTART,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
- else if (command == NAND_CMD_READ0)
- chip->cmd_ctrl(mtd,
- NAND_CMD_READSTART,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
-
- chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
- }
-
- /*
- * program and erase have their own busy handlers
- * status, sequential in, and deplete1 need no delay
- */
- switch (command) {
-
- case NAND_CMD_CACHEDPROG:
- case NAND_CMD_PAGEPROG:
- case NAND_CMD_ERASE1:
- case NAND_CMD_ERASE2:
- case NAND_CMD_SEQIN:
- case NAND_CMD_RNDIN:
- case NAND_CMD_STATUS:
- case NAND_CMD_DEPLETE1:
- return;
-
- /*
- * read error status commands require only a short delay
- */
- case NAND_CMD_STATUS_ERROR:
- case NAND_CMD_STATUS_ERROR0:
- case NAND_CMD_STATUS_ERROR1:
- case NAND_CMD_STATUS_ERROR2:
- case NAND_CMD_STATUS_ERROR3:
- udelay(chip->chip_delay);
- return;
-
- case NAND_CMD_RESET:
- if (!aml_chip->aml_nand_wait_devready(aml_chip, chipnr))
- printk ("couldn`t found selected chip: %d ready\n",
- chipnr);
- chip->cmd_ctrl(mtd,
- NAND_CMD_STATUS,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
- chip->cmd_ctrl(mtd,
- NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
- while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
- (rst_sts_cnt--));
- return;
-
- default:
- /*
- * If we don't have access to the busy pin, we apply the given
- * command delay
- */
- break;
- }
-
- /* Apply this short delay always to ensure that we do wait tWB in
- * any case on any machine. */
- ndelay(100);
-}
-
-void aml_nand_command(struct mtd_info *mtd,
- unsigned command, int column, int page_addr)
-{
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
- struct nand_chip *chip = &aml_chip->chip;
- int i = 0, valid_page_num = 1;
-
- if (page_addr != -1) {
- valid_page_num = (mtd->writesize >> chip->page_shift);
- valid_page_num /= aml_chip->plane_num;
- aml_chip->page_addr = page_addr / valid_page_num;
- if (unlikely(aml_chip->page_addr >= aml_chip->internal_page_nums)) {
- /*internal_chip =
- aml_chip->page_addr / aml_chip->internal_page_nums;*/
- aml_chip->page_addr -= aml_chip->internal_page_nums;
- aml_chip->page_addr |=
- (1 << aml_chip->internal_chip_shift)*aml_chip->internal_chipnr;
- }
- } else
- aml_chip->page_addr = page_addr;
-
- /* Emulate NAND_CMD_READOOB */
- if (command == NAND_CMD_READOOB) {
- command = NAND_CMD_READ0;
- aml_chip->aml_nand_wait_devready(aml_chip, 0);
- aml_chip->aml_nand_command(aml_chip, command,
- column, aml_chip->page_addr, 0);
- return;
- }
- if (command == NAND_CMD_PAGEPROG)
- return;
-
- /*if (command == NAND_CMD_SEQIN) {
- aml_chip->aml_nand_select_chip(aml_chip, 0);
- aml_chip->aml_nand_command(aml_chip,
- command, column, page_addr, 0);
- return;
- }*/
-
- for (i=0; i<controller->chip_num; i++) {
- if (aml_chip->valid_chip[i]) {
- /*active ce for operation chip and send cmd*/
- aml_chip->aml_nand_wait_devready(aml_chip, i);
- aml_chip->aml_nand_command(aml_chip,
- command, column, aml_chip->page_addr, i);
- }
- }
-
- return;
-}
-
-int aml_nand_erase_cmd(struct mtd_info *mtd, int page)
-{
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
- struct nand_chip *chip = mtd->priv;
- unsigned pages_per_blk_shift;
- unsigned vt_page_num, internal_chipnr = 1, page_addr, valid_page_num;
- unsigned i = 0, j = 0;
- unsigned block_addr;
-
- pages_per_blk_shift = (chip->phys_erase_shift - chip->page_shift);
-
- vt_page_num = (mtd->writesize / (1 << chip->page_shift));
- vt_page_num *= (1 << pages_per_blk_shift);
- /* printk("%s() page 0x%x\n", __func__, page);*/
- if (page % vt_page_num)
- return 1;
- /* fixme, skip bootloader */
- if (page < 1024)
- return 1;
- /* Send commands to erase a block */
- valid_page_num = (mtd->writesize >> chip->page_shift);
-
- block_addr = ((page / valid_page_num) >> pages_per_blk_shift);
-
- if (meson_rsv_erase_protect(aml_chip->rsv, block_addr) == -1) {
- printf("%s blk 0x%x is protected\n", __func__, block_addr);
- return 1;
- }
-
- valid_page_num /= aml_chip->plane_num;
-
- aml_chip->page_addr = page / valid_page_num;
- if (unlikely(aml_chip->page_addr >= aml_chip->internal_page_nums)) {
- //internal_chipnr =
- // aml_chip->page_addr / aml_chip->internal_page_nums;
- aml_chip->page_addr -= aml_chip->internal_page_nums;
- aml_chip->page_addr |=
- (1 << aml_chip->internal_chip_shift) *aml_chip->internal_chipnr;
- }
-
- if (unlikely(aml_chip->ops_mode & AML_INTERLEAVING_MODE))
- internal_chipnr = aml_chip->internal_chipnr;
- else
- internal_chipnr = 1;
-
- for (i=0; i<controller->chip_num; i++) {
- if (aml_chip->valid_chip[i]) {
- aml_chip->aml_nand_select_chip(aml_chip, i);
- page_addr = aml_chip->page_addr;
- for (j=0; j<internal_chipnr; j++) {
- if (j > 0) {
- page_addr = aml_chip->page_addr;
- page_addr |=
- (1 << aml_chip->internal_chip_shift) *j;
- }
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_ERASE1, -1, page_addr, i);
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_ERASE2, -1, -1, i);
- }
- }
- }
- return 0;
-}
-
-void aml_nand_dma_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
-{
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
-
- aml_chip->aml_nand_dma_read(aml_chip, buf, len, 0);
-}
-
-void aml_nand_dma_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
-{
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
-
- aml_chip->aml_nand_dma_write(aml_chip, (unsigned char *)buf, len, 0);
-}
-
-int aml_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
- uint8_t *buf, int oob_required, int page)
-{
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
- unsigned nand_page_size = aml_chip->page_size;
- unsigned nand_oob_size = aml_chip->oob_size;
- uint8_t *oob_buf = chip->oob_poi;
- int i, error = 0, j = 0, page_addr, internal_chipnr = 1;
-
- if (aml_chip->ops_mode & AML_INTERLEAVING_MODE)
- internal_chipnr = aml_chip->internal_chipnr;
-
- for (i = 0; i < controller->chip_num; i++) {
- if (aml_chip->valid_chip[i]) {
- page_addr = aml_chip->page_addr;
- for (j = 0; j < internal_chipnr; j++) {
- if (j > 0) {
- page_addr = aml_chip->page_addr;
- page_addr |=
- (1 << aml_chip->internal_chip_shift) * j;
- aml_chip->aml_nand_select_chip(aml_chip,
- i);
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_READ0, 0, page_addr,i);
- }
-
- if (!aml_chip->aml_nand_wait_devready(aml_chip,
- i)) {
- printk ("didn't found selected chip:%dready\n",
- i);
- error = -EBUSY;
- goto exit;
- }
-
- if (aml_chip->ops_mode & AML_CHIP_NONE_RB)
- chip->cmd_ctrl(mtd,
- NAND_CMD_READ0 & 0xff,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
- if (aml_chip->plane_num == 2) {
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_TWOPLANE_READ1,
- 0x00, page_addr, i);
- chip->read_buf(mtd,
- aml_chip->aml_nand_data_buf,
- (nand_page_size+nand_oob_size));
- memcpy(buf, aml_chip->aml_nand_data_buf,
- (nand_page_size+nand_oob_size));
- memcpy(oob_buf,
- aml_chip->aml_nand_data_buf + nand_page_size,
- nand_oob_size);
-
- oob_buf += nand_oob_size;
- buf += (nand_page_size + nand_oob_size);
-
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_TWOPLANE_READ2,
- 0x00, page_addr, i);
- chip->read_buf(mtd,
- aml_chip->aml_nand_data_buf,
- nand_page_size + nand_oob_size);
- memcpy(buf, aml_chip->aml_nand_data_buf,
- nand_page_size + nand_oob_size);
- memcpy(oob_buf,
- aml_chip->aml_nand_data_buf + nand_page_size,
- nand_oob_size);
-
- oob_buf += nand_oob_size;
- buf += (nand_page_size + nand_oob_size);
- } else if (aml_chip->plane_num == 1) {
- chip->read_buf(mtd,
- aml_chip->aml_nand_data_buf,
- nand_page_size + nand_oob_size);
- memcpy(buf, aml_chip->aml_nand_data_buf,
- nand_page_size);
- memcpy(oob_buf,
- aml_chip->aml_nand_data_buf + nand_page_size,
- nand_oob_size);
- oob_buf += nand_oob_size;
- buf += nand_page_size;
- } else {
- error = -ENODEV;
- goto exit;
- }
- }
- }
- }
-
-exit:
- return error;
-}
-
-int aml_nand_write_page_raw(struct mtd_info *mtd,
- struct nand_chip *chip, const uint8_t *buf, int oob_required,
- int page)
-{
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
- unsigned nand_page_size = aml_chip->page_size;
- unsigned nand_oob_size = aml_chip->oob_size;
- uint8_t *oob_buf = chip->oob_poi;
- int i, error = 0, j = 0, page_addr, internal_chipnr = 1;
-
- if (aml_chip->ops_mode & AML_INTERLEAVING_MODE)
- internal_chipnr = aml_chip->internal_chipnr;
-
- for (i=0; i<controller->chip_num; i++) {
- if (aml_chip->valid_chip[i]) {
- aml_chip->aml_nand_select_chip(aml_chip, i);
- page_addr = aml_chip->page_addr;
- for (j = 0; j < internal_chipnr; j++) {
- if (j > 0) {
- page_addr = aml_chip->page_addr;
- page_addr |=
- (1 << aml_chip->internal_chip_shift) *j;
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_SEQIN, 0, page_addr, i);
- }
-
- if (aml_chip->plane_num == 2) {
- memcpy(aml_chip->aml_nand_data_buf,
- buf, nand_page_size);
- memcpy(aml_chip->aml_nand_data_buf + nand_page_size,
- oob_buf, nand_oob_size);
- chip->write_buf(mtd,
- aml_chip->aml_nand_data_buf,
- nand_page_size + nand_oob_size);
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_DUMMY_PROGRAM, -1, -1, i);
-
- oob_buf += nand_oob_size;
- buf += nand_page_size;
-
- if (!aml_chip->aml_nand_wait_devready(aml_chip, i)) {
- printk ("didn't found selected chip:%d ready\n",
- i);
- error = -EBUSY;
- goto exit;
- }
-
- memcpy(aml_chip->aml_nand_data_buf,
- buf, nand_page_size);
- memcpy(aml_chip->aml_nand_data_buf + nand_page_size,
- oob_buf, nand_oob_size);
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_TWOPLANE_WRITE2, 0x00, page_addr, i);
- chip->write_buf(mtd, aml_chip->aml_nand_data_buf,
- (nand_page_size + nand_oob_size));
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_PAGEPROG, -1, -1, i);
-
- oob_buf += nand_oob_size;
- buf += nand_page_size;
- } else if (aml_chip->plane_num == 1) {
- memcpy(aml_chip->aml_nand_data_buf,
- buf, nand_page_size);
- memcpy(aml_chip->aml_nand_data_buf + nand_page_size,
- oob_buf, nand_oob_size);
- chip->write_buf(mtd,
- aml_chip->aml_nand_data_buf,
- nand_page_size + nand_oob_size);
- if (chip->cmdfunc == aml_nand_command)
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_PAGEPROG,
- -1, -1, i);
-
- oob_buf += nand_oob_size;
- buf += nand_page_size;
- } else {
- error = -ENODEV;
- goto exit;
- }
- }
- }
- }
-exit:
- return error;
-}
-
-int aml_nand_read_page_hwecc(struct mtd_info *mtd,
- struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
-{
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
- uint8_t *oob_buf = chip->oob_poi;
- unsigned nand_page_size = (1 << chip->page_shift);
- unsigned pages_per_blk_shift;
- int user_byte_num;
- int error = 0, i = 0, stat = 0, j = 0, page_addr, internal_chipnr = 1;
- int ran_mode = aml_chip->ran_mode;
-
- pages_per_blk_shift = (chip->phys_erase_shift - chip->page_shift);
- user_byte_num = (((nand_page_size + chip->ecc.size - 1) /chip->ecc.size)
- * aml_chip->user_byte_mode);
-
- if (aml_chip->ops_mode & AML_INTERLEAVING_MODE)
- internal_chipnr = aml_chip->internal_chipnr;
-
- if (nand_page_size > chip->ecc.steps * chip->ecc.size) {
- nand_page_size = chip->ecc.steps * chip->ecc.size;
- user_byte_num = chip->ecc.steps;
- }
-
- for (i = 0; i < controller->chip_num; i++) {
- if (aml_chip->valid_chip[i]) {
- page_addr = aml_chip->page_addr;
- for (j = 0; j < internal_chipnr; j++) {
- if (j > 0) {
- page_addr = aml_chip->page_addr;
- page_addr |= (1 << aml_chip->internal_chip_shift) * j;
- aml_chip->aml_nand_select_chip(aml_chip, i);
- aml_chip->aml_nand_command(aml_chip, NAND_CMD_READ0,
- 0, page_addr, i);
- }
- if (!aml_chip->aml_nand_wait_devready(aml_chip, i)) {
- printk ("read couldn`t found selected chip: %d ready\n",
- i);
- error = -EBUSY;
- goto exit;
- }
- if (aml_chip->ops_mode & AML_CHIP_NONE_RB)
- chip->cmd_ctrl(mtd, NAND_CMD_READ0 & 0xff,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
- if (aml_chip->plane_num == 2) {
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_TWOPLANE_READ1, 0x00, page_addr, i);
-dma_retry_plane0:
- error = aml_chip->aml_nand_dma_read(aml_chip,
- buf, nand_page_size, aml_chip->bch_mode);
- if (error)
- goto exit;
-
- aml_chip->aml_nand_get_user_byte(aml_chip,
- oob_buf, user_byte_num);
- stat = aml_chip->aml_nand_hwecc_correct(aml_chip,
- buf, nand_page_size, oob_buf);
- if (stat < 0) {
- if (aml_chip->ran_mode
- && (aml_chip->zero_cnt < aml_chip->ecc_max)) {
- memset(buf, 0xff, nand_page_size);
- memset(oob_buf, 0xff, user_byte_num);
- goto plane0_ff;
- }
-
- if (ran_mode && aml_chip->ran_mode) {
- aml_chip->ran_mode = 0;
- ndelay(300);
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_RNDOUT, 0, -1, i);
- ndelay(500);
- goto dma_retry_plane0;
- }
- memset(buf, 0xff, nand_page_size);
- memset(oob_buf, 0xff, user_byte_num);
-
- mtd->ecc_stats.failed++;
- printk("read ecc pl0 failed at page%d chip%d\n",
- page_addr, i);
- } else {
- if (aml_chip->ecc_cnt_cur > aml_chip->ecc_cnt_limit) {
- printk("%s %d uncorrect ecc_cnt_cur:%d limit:%d pg:%d,blk:%d chip%d\n",
- __func__, __LINE__,
- aml_chip->ecc_cnt_cur, aml_chip->ecc_cnt_limit,
- page_addr, page_addr >> pages_per_blk_shift, i);
- mtd->ecc_stats.corrected++;
- }
- mtd->ecc_stats.corrected += stat;
- }
-plane0_ff:
- aml_chip->ran_mode = ran_mode;
- oob_buf += user_byte_num;
- buf += nand_page_size;
-
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_TWOPLANE_READ2, 0x00, page_addr, i);
-dma_retry_plane1:
- error = aml_chip->aml_nand_dma_read(aml_chip,
- buf, nand_page_size, aml_chip->bch_mode);
- if (error)
- goto exit;
-
- aml_chip->aml_nand_get_user_byte(aml_chip,
- oob_buf, user_byte_num);
- stat = aml_chip->aml_nand_hwecc_correct(aml_chip,
- buf, nand_page_size, oob_buf);
- if (stat < 0) {
- if(aml_chip->ran_mode
- && (aml_chip->zero_cnt < aml_chip->ecc_max)) {
- memset(buf, 0xff, nand_page_size);
- memset(oob_buf, 0xff, user_byte_num);
- oob_buf += user_byte_num;
- buf += nand_page_size;
- continue;
- }
-
- if (ran_mode && aml_chip->ran_mode) {
- aml_chip->ran_mode = 0;
- ndelay(300);
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_RNDOUT, 0, -1, i);
- ndelay(500);
- goto dma_retry_plane1;
- }
- memset(buf, 0xff, nand_page_size);
- memset(oob_buf, 0xff, user_byte_num);
-
- mtd->ecc_stats.failed++;
- printk("read ecc pl1 failed at page%d chip%d\n",
- page_addr, i);
- } else {
- if (aml_chip->ecc_cnt_cur > aml_chip->ecc_cnt_limit) {
- printk("%s %d uncorrect ecc_cnt_cur:%d limit:%d pg:%d blk:%d chip%d\n",
- __func__, __LINE__,
- aml_chip->ecc_cnt_cur, aml_chip->ecc_cnt_limit,
- page_addr, page_addr >> pages_per_blk_shift, i);
- mtd->ecc_stats.corrected++;
- }
- mtd->ecc_stats.corrected += stat;
- }
- aml_chip->ran_mode = ran_mode;
- oob_buf += user_byte_num;
- buf += nand_page_size;
-
- } else if (aml_chip->plane_num == 1) {
- error = aml_chip->aml_nand_dma_read(aml_chip,
- buf, nand_page_size, aml_chip->bch_mode);
- if (error)
- goto exit;
-
- aml_chip->aml_nand_get_user_byte(aml_chip,
- oob_buf, user_byte_num);
- stat = aml_chip->aml_nand_hwecc_correct(aml_chip,
- buf, nand_page_size, oob_buf);
- if (stat < 0) {
- if(aml_chip->ran_mode
- && (aml_chip->zero_cnt < aml_chip->ecc_max)) {
- memset(buf, 0xff, nand_page_size);
- memset(oob_buf, 0xff, user_byte_num);
- oob_buf += user_byte_num;
- buf += nand_page_size;
- continue;
- }
- /*memset(buf, 0xff, nand_page_size);*/
- memset(oob_buf, 0x22, user_byte_num);
- printk("%s %d read ecc failed here at at page:%d, blk:%d chip[%d]\n",
- __func__, __LINE__, page_addr,
- (page_addr >> pages_per_blk_shift), i);
- mtd->ecc_stats.failed++;
- } else {
- aml_chip->ran_mode = ran_mode;
- mtd->ecc_stats.corrected += stat;
- }
- oob_buf += user_byte_num;
- buf += nand_page_size;
- } else {
- error = -ENODEV;
- goto exit;
- }
- }
- }
- }
-exit:
- return error;
-}
-
-int aml_nand_write_page_hwecc(struct mtd_info *mtd,
- struct nand_chip *chip, const uint8_t *buf, int oob_required,
- int page)
-{
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
- uint8_t *oob_buf = chip->oob_poi;
- unsigned nand_page_size = (1 << chip->page_shift);
- int user_byte_num, temp_value;
- int error = 0, i = 0, j = 0, page_addr, internal_chipnr = 1;
-
- temp_value = nand_page_size + chip->ecc.size - 1;
- user_byte_num = (temp_value /chip->ecc.size) * aml_chip->user_byte_mode;
-
- if (aml_chip->ops_mode & AML_INTERLEAVING_MODE)
- internal_chipnr = aml_chip->internal_chipnr;
-
- memset(oob_buf + mtd->oobavail,
- 0xa5, user_byte_num * (mtd->writesize / nand_page_size));
-
- for (i = 0; i < controller->chip_num; i++) {
- if (aml_chip->valid_chip[i]) {
- page_addr = aml_chip->page_addr;
- for (j = 0; j < internal_chipnr; j++) {
- aml_chip->aml_nand_select_chip(aml_chip, i);
- if (j > 0) {
- page_addr = aml_chip->page_addr;
- page_addr |=
- (1 <<aml_chip->internal_chip_shift) * j;
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_SEQIN, 0, page_addr, i);
- }
- if (aml_chip->plane_num == 2) {
- aml_chip->aml_nand_set_user_byte(aml_chip,
- oob_buf, user_byte_num);
- error = aml_chip->aml_nand_dma_write(aml_chip,
- (unsigned char *)buf,
- nand_page_size, aml_chip->bch_mode);
- if (error) {
- printk("dma write 1 err at page %x\n",
- page_addr);
- goto exit;
- }
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_DUMMY_PROGRAM, -1, -1, i);
-
- oob_buf += user_byte_num;
- buf += nand_page_size;
-
- if (!aml_chip->aml_nand_wait_devready(aml_chip, i)) {
- printk ("write couldn't found chip:%d ready\n",
- i);
- error = -EBUSY;
- goto exit;
- }
-
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_TWOPLANE_WRITE2, 0x00, page_addr, i);
- aml_chip->aml_nand_set_user_byte(aml_chip,
- oob_buf, user_byte_num);
- error = aml_chip->aml_nand_dma_write(aml_chip,
- (u8 *)buf,
- nand_page_size, aml_chip->bch_mode);
- if (error) {
- printk("aml_nand_dma_write 2 err at page %x\n",
- page_addr);
- goto exit;
- }
- if (aml_chip->cached_prog_status)
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_CACHEDPROG, -1, -1, i);
- else
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_PAGEPROG, -1, -1, i);
-
- oob_buf += user_byte_num;
- buf += nand_page_size;
- } else if (aml_chip->plane_num == 1) {
- aml_chip->aml_nand_set_user_byte(aml_chip,
- oob_buf, user_byte_num);
- error = aml_chip->aml_nand_dma_write(aml_chip,
- (unsigned char *)buf,
- nand_page_size, aml_chip->bch_mode);
- if (error) {
- printk("aml_nand_dma_write err at page %x\n",
- page_addr);
- goto exit;
- }
- if (chip->cmdfunc == aml_nand_command) {
- if (aml_chip->cached_prog_status)
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_CACHEDPROG, -1, -1, i);
- else
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_PAGEPROG, -1, -1, i);
- }
-
- oob_buf += user_byte_num;
- buf += nand_page_size;
- }
- else {
- error = -ENODEV;
- goto exit;
- }
- }
- }
- }
-exit:
- return error;
-}
-
-int aml_nand_write_page(struct mtd_info *mtd,
- struct nand_chip *chip, uint32_t offset,
- int data_len,
- const uint8_t *buf,
- int oob_required, int page, int raw)
-{
- int status;
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
-
- chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
-
- if (chip->options & NAND_CACHEPRG)
- aml_chip->cached_prog_status = 1;
- else
- aml_chip->cached_prog_status = 0;
- if (unlikely(raw))
- chip->ecc.write_page_raw(mtd, chip, buf, 0, 0);
- else
- chip->ecc.write_page(mtd, chip, buf, 0, 0);
-
- if (!(chip->options & NAND_CACHEPRG)) {
- status = chip->waitfunc(mtd, chip);
- /*
- * See if operation failed and additional status checks are
- * available
- */
- if (status & NAND_STATUS_FAIL) {
- printk("wr page=0x%x, status = 0x%x\n",
- page,status);
- return -EIO;
- }
- } else
- status = chip->waitfunc(mtd, chip);
-
- aml_chip->cached_prog_status = 0;
- return 0;
-}
-
-int aml_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
-{
- int32_t page_addr;
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
- unsigned char *nand_buffer = aml_chip->aml_nand_data_buf;
- int32_t error=0;
- int oob_required = 1;
-
- page_addr = page;
-
- if (chip->cmdfunc == aml_nand_command)
- chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page_addr);
- else {
- aml_chip->aml_nand_select_chip(aml_chip, 0);
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page_addr);
- }
-
- error = aml_nand_read_page_hwecc(mtd, chip, nand_buffer, oob_required, page);
- if (error) {
- printk("%s, %d,read oob failed\n", __func__, __LINE__);
- }
- return error;
-}
-
-int aml_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
-{
- printk("our host controller`s structure couldn`t support oob write\n");
- BUG();
- return 0;
-}
-
-int aml_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
-{
- struct nand_chip * chip = mtd->priv;
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
- struct aml_nand_platform *plat = aml_chip->platform;
- struct mtd_oob_ops aml_oob_ops;
- int32_t ret=0, read_cnt, mtd_erase_shift, blk_addr, pages_per_blk;
- loff_t addr;
-
- if ((!strncmp((char*)plat->name,
- NAND_BOOT_NAME, strlen((const char*)NAND_BOOT_NAME))))
- return 0;
-
- mtd_erase_shift = fls(mtd->erasesize) - 1;
- blk_addr = (int)(ofs >> mtd_erase_shift);
- if (aml_chip->block_status != NULL) {
- if (aml_chip->block_status[blk_addr] == NAND_BLOCK_BAD) {
- printk(" NAND bbt detect Bad block at %llx \n",
- (uint64_t)ofs);
- return EFAULT;
- }
- if (aml_chip->block_status[blk_addr] == NAND_FACTORY_BAD) {
- printk(" NAND bbt detect factory Bad block at %llx \n",
- (uint64_t)ofs);
- return FACTORY_BAD_BLOCK_ERROR; //159 EFAULT
- } else if (aml_chip->block_status[blk_addr] ==NAND_BLOCK_GOOD)
- return 0;
- }
- chip->pagebuf = -1;
- pages_per_blk = (1 << (chip->phys_erase_shift - chip->page_shift));
-
- aml_oob_ops.mode = MTD_OPS_AUTO_OOB;
- aml_oob_ops.len = mtd->writesize;
- aml_oob_ops.ooblen = mtd->oobavail;
- aml_oob_ops.ooboffs = chip->ecc.layout->oobfree[0].offset;
- aml_oob_ops.datbuf = chip->buffers->databuf;
- aml_oob_ops.oobbuf = chip->oob_poi;
-
- for (read_cnt = 0; read_cnt < 2; read_cnt++) {
- addr =
- ofs + (pages_per_blk - 1) * read_cnt * mtd->writesize;
- ret = mtd->_read_oob(mtd, addr, &aml_oob_ops);
- if (ret == -EUCLEAN)
- ret = 0;
- if (ret < 0) {
- printk("1 NAND detect Bad block:%llx\n",
- (uint64_t)addr);
- return EFAULT;
- }
- if (aml_oob_ops.oobbuf[chip->badblockpos] == 0xFF)
- continue;
- if (aml_oob_ops.oobbuf[chip->badblockpos] == 0) {
- memset(aml_chip->aml_nand_data_buf,
- 0, aml_oob_ops.ooblen);
- if (!memcmp(aml_chip->aml_nand_data_buf,
- aml_oob_ops.oobbuf, aml_oob_ops.ooblen)) {
- printk("2 NAND detect Bad block:%llx\n",
- (uint64_t)addr);
- return EFAULT;
- }
- }
- }
-
-
- return 0;
-}
-
-extern int meson_rsv_bbt_write(u_char *source, size_t size);
-int aml_nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
-{
- struct nand_chip * chip = mtd->priv;
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
- struct mtd_oob_ops aml_oob_ops;
- int blk_addr, mtd_erase_shift;
- int8_t *buf = NULL;
-
- mtd_erase_shift = fls(mtd->erasesize) - 1;
- blk_addr = (int)(ofs >> mtd_erase_shift);
- if (aml_chip->block_status != NULL) {
- if ((aml_chip->block_status[blk_addr] == NAND_BLOCK_BAD)
- ||(aml_chip->block_status[blk_addr] == NAND_FACTORY_BAD)) {
- goto mark_bad;
-
- } else if (aml_chip->block_status[blk_addr] ==NAND_BLOCK_GOOD) {
- aml_chip->block_status[blk_addr] = NAND_BLOCK_BAD;
- buf = aml_chip->block_status;
- meson_rsv_bbt_write((u_char *)buf, aml_chip->rsv->bbt->size);
- }
- }
-mark_bad:
- /*no erase here, fixit*/
- aml_oob_ops.mode = MTD_OPS_AUTO_OOB;
- aml_oob_ops.len = mtd->writesize;
- aml_oob_ops.ooblen = mtd->oobavail;
- aml_oob_ops.ooboffs = chip->ecc.layout->oobfree[0].offset;
- aml_oob_ops.datbuf = chip->buffers->databuf;
- aml_oob_ops.oobbuf = chip->oob_poi;
- chip->pagebuf = -1;
-
- memset((unsigned char *)aml_oob_ops.datbuf, 0x0, mtd->writesize);
- memset((unsigned char *)aml_oob_ops.oobbuf, 0x0, aml_oob_ops.ooblen);
-
- return mtd->_write_oob(mtd, ofs, &aml_oob_ops);
-}
-
-static uint8_t aml_platform_read_byte(struct mtd_info *mtd)
-{
- uint8_t status;
-
- NFC_SEND_CMD_DRD(controller, controller->chip_selected, 0);
- NFC_SEND_CMD_IDLE(controller, NAND_TWB_TIME_CYCLE);
-
- NFC_SEND_CMD_IDLE(controller, 0);
- NFC_SEND_CMD_IDLE(controller, 0);
-
- while (NFC_CMDFIFO_SIZE(controller) > 0) ;
- status = amlnf_read_reg32(controller->reg_base + P_NAND_BUF);
- return status;
-}
-
-void aml_platform_write_byte(struct aml_nand_chip *aml_chip, uint8_t data)
-{
- NFC_SEND_CMD_IDLE(controller, NAND_TWB_TIME_CYCLE);
- NFC_SEND_CMD_DWR(controller, controller->chip_selected, data);
- NFC_SEND_CMD_IDLE(controller, NAND_TWB_TIME_CYCLE);
-
- NFC_SEND_CMD_IDLE(controller, 0);
- NFC_SEND_CMD_IDLE(controller, 0);
-
- while (NFC_CMDFIFO_SIZE(controller) > 0)
- ;
-}
-
-int aml_nand_init(struct aml_nand_chip *aml_chip)
-{
- struct aml_nand_platform *plat = aml_chip->platform;
- struct nand_chip *chip = &aml_chip->chip;
- struct mtd_info *mtd = &chip->mtd;
- int err = 0, i = 0;
- int oobmul;
- unsigned valid_chip_num = 0;
- struct nand_oobfree *oobfree = NULL;
- cpu_id_t cpu_id = get_cpu_id();
-
- chip->IO_ADDR_R = chip->IO_ADDR_W =
- (void __iomem *)((volatile u32 *)(NAND_BASE_APB + P_NAND_BUF));
-
- chip->options |= NAND_SKIP_BBTSCAN;
- chip->options |= NAND_NO_SUBPAGE_WRITE;
-
- chip->ecc.layout = &aml_nand_oob_64;
- chip->select_chip = aml_nand_select_chip;
- chip->cmd_ctrl = aml_nand_cmd_ctrl;
- chip->read_byte = aml_platform_read_byte;
-
- controller->chip_num = plat->platform_nand_data.chip.nr_chips;
- if (controller->chip_num > MAX_CHIP_NUM) {
- err = -ENXIO;
- goto exit_error;
- }
-
- for (i=0; i<controller->chip_num; i++)
- aml_chip->valid_chip[i] = 1;
-
- /*use NO RB mode to detect nand chip num*/
- aml_chip->ops_mode |= AML_CHIP_NONE_RB;
- chip->chip_delay = 100;
-
- aml_chip->aml_nand_hw_init(aml_chip);
- aml_chip->toggle_mode =0;
- aml_chip->bch_info = NAND_ECC_BCH60_1K;
- if ((cpu_id.family_id == MESON_CPU_MAJOR_ID_AXG) ||
- (cpu_id.family_id == MESON_CPU_MAJOR_ID_TXHD))
- aml_chip->bch_info = NAND_ECC_BCH8_1K;
-
- chip->options = 0;
- chip->options |= NAND_SKIP_BBTSCAN;
- chip->options |= NAND_NO_SUBPAGE_WRITE;
- if (aml_nand_scan(mtd, controller->chip_num)) {
- err = -ENXIO;
- goto exit_error;
- }
-
- valid_chip_num = 0;
- for (i=0; i < controller->chip_num; i++) {
- if (aml_chip->valid_chip[i])
- valid_chip_num++;
- }
-
- chip->scan_bbt = aml_nand_scan_shipped_bbt;//aml_nand_scan_bbt;
- if (aml_chip->aml_nand_adjust_timing)
- aml_chip->aml_nand_adjust_timing(aml_chip);
-
- if (aml_chip->aml_nand_options_confirm(aml_chip)) {
- err = -ENXIO;
- goto exit_error;
- }
-
- oobmul = mtd->oobsize /aml_chip->oob_size ;
- if (!chip->ecc.layout)
- chip->ecc.layout =
- kzalloc(sizeof(struct nand_ecclayout), GFP_KERNEL);
- if (!chip->ecc.layout) {
- err = -ENOMEM;
- goto exit_error ;
- }
- if (!strncmp((char*)plat->name, NAND_BOOT_NAME,
- strlen((const char*)NAND_BOOT_NAME)))
- memcpy(chip->ecc.layout,
- &aml_nand_uboot_oob, sizeof(struct nand_ecclayout));
- else if (chip->ecc.mode != NAND_ECC_SOFT) {
- switch (aml_chip->oob_size) {
- case 64:
- memcpy(chip->ecc.layout,
- &aml_nand_oob_64,
- sizeof(struct nand_ecclayout));
- break;
- case 128:
- memcpy(chip->ecc.layout,
- &aml_nand_oob_128,
- sizeof(struct nand_ecclayout));
- break;
- case 218:
- memcpy(chip->ecc.layout,
- &aml_nand_oob_218,
- sizeof(struct nand_ecclayout));
- break;
- case 224:
- memcpy(chip->ecc.layout,
- &aml_nand_oob_224,
- sizeof(struct nand_ecclayout));
- break;
- case 256:
- memcpy(chip->ecc.layout,
- &aml_nand_oob_256,
- sizeof(struct nand_ecclayout));
- break;
- case 376:
- memcpy(chip->ecc.layout,
- &aml_nand_oob_376,
- sizeof(struct nand_ecclayout));
- break;
- case 436:
- memcpy(chip->ecc.layout,
- &aml_nand_oob_436,
- sizeof(struct nand_ecclayout));
- break;
- case 448:
- memcpy(chip->ecc.layout,
- &aml_nand_oob_448,
- sizeof(struct nand_ecclayout));
- break;
- case 640:
- memcpy(chip->ecc.layout,
- &aml_nand_oob_640,
- sizeof(struct nand_ecclayout));
- break;
- case 744:
- memcpy(chip->ecc.layout,
- &aml_nand_oob_744,
- sizeof(struct nand_ecclayout));
- break;
- case 1280:
- memcpy(chip->ecc.layout,
- &aml_nand_oob_1280,
- sizeof(struct nand_ecclayout));
- break;
- case 1664:
- memcpy(chip->ecc.layout,
- &aml_nand_oob_1664,
- sizeof(struct nand_ecclayout));
- break;
- default:
- printk("default, use nand base oob layout %d\n",
- mtd->oobsize);
- oobfree[0].length =
- ((mtd->writesize / chip->ecc.size) * aml_chip->user_byte_mode);
- break;
- }
-
- chip->ecc.layout->oobfree[0].length *= oobmul;
- chip->ecc.layout->eccbytes *= oobmul;
- printk("%s :oobmul=%d,oobfree.length=%d,oob_size=%d\n",
- __func__,
- oobmul,
- chip->ecc.layout->oobfree[0].length,
- aml_chip->oob_size);
- }
-
- /*
- * The number of bytes available for a client to place data into
- * the out of band area
- */
- chip->ecc.layout->oobavail = 0;
- oobfree = chip->ecc.layout->oobfree;
- for (i = 0; oobfree[i].length && i < ARRAY_SIZE(oobfree); i++)
- chip->ecc.layout->oobavail += oobfree[i].length;
- printk("oob avail size %d\n", chip->ecc.layout->oobavail);
-
- mtd->oobavail = chip->ecc.layout->oobavail;
- mtd->ecclayout = chip->ecc.layout;
-
- aml_chip->virtual_page_size = mtd->writesize;
- aml_chip->virtual_block_size = mtd->erasesize;
-
- aml_chip->aml_nand_data_buf =
- kzalloc((mtd->writesize + mtd->oobsize), GFP_KERNEL);
- if (aml_chip->aml_nand_data_buf == NULL) {
- printk("no memory for flash data buf\n");
- err = -ENOMEM;
- goto exit_error;
- }
- aml_chip->user_info_buf =
- kzalloc((mtd->writesize / chip->ecc.size) * PER_INFO_BYTE,
- GFP_KERNEL);
- if (aml_chip->user_info_buf == NULL) {
- printk("no memory for flash info buf\n");
- err = -ENOMEM;
- goto exit_error;
- }
-
- if (aml_chip->rsv == NULL) {
- aml_chip->rsv = kzalloc(sizeof (struct meson_rsv_handler_t), GFP_KERNEL);
- if (aml_chip->rsv == NULL) {
- printk("no memory for aml_chip rsv\n");
- err = -ENOMEM;
- goto exit_error;
- }
- }
-
- if (chip->buffers == NULL) {
- printk("no memory for flash data buf\n");
- err = -ENOMEM;
- goto exit_error;
- }
-
- chip->oob_poi = chip->buffers->databuf + mtd->writesize;
- chip->options |= NAND_OWN_BUFFERS;
-
- if (is_power_of_2(mtd->erasesize))
- mtd->erasesize_shift = ffs(mtd->erasesize) - 1;
- else
- mtd->erasesize_shift = 0;
-
- if (is_power_of_2(mtd->writesize))
- mtd->writesize_shift = ffs(mtd->writesize) - 1;
- else
- mtd->writesize_shift = 0;
-
- if (strncmp((char*)plat->name,
- NAND_BOOT_NAME, strlen((const char*)NAND_BOOT_NAME))) {
- meson_rsv_init(mtd, aml_chip->rsv);
- /*block status*/
- aml_chip->block_status =
- kzalloc((mtd->size >> mtd->erasesize_shift), GFP_KERNEL);
- if (aml_chip->block_status == NULL) {
- printk("no memory for flash block status\n");
- return -ENOMEM;
- }
- memset(aml_chip->block_status, 0, (mtd->size >> mtd->erasesize_shift));
-
- err = aml_nand_bbt_check(mtd);
- if (err) {
- printk("invalid nand bbt\n");
- goto exit_error;
- }
-#ifndef CONFIG_ENV_IS_IN_NAND
- meson_rsv_check(aml_chip->rsv->env);
-#endif
- meson_rsv_check(aml_chip->rsv->key);
- meson_rsv_check(aml_chip->rsv->dtb);
- }
- if (aml_nand_add_partition(aml_chip) != 0) {
- err = -ENXIO;
- goto exit_error;
- }
-
- printk("%s initialized ok\n", mtd->name);
- return 0;
-
-exit_error:
- if (aml_chip->user_info_buf) {
- kfree(aml_chip->user_info_buf);
- aml_chip->user_info_buf = NULL;
- }
- if (chip->buffers) {
- kfree(chip->buffers);
- chip->buffers = NULL;
- }
- if (aml_chip->aml_nand_data_buf) {
- kfree(aml_chip->aml_nand_data_buf);
- aml_chip->aml_nand_data_buf = NULL;
- }
- if (aml_chip->block_status) {
- kfree(aml_chip->block_status);
- aml_chip->block_status = NULL;
- }
-
- if (aml_chip->rsv) {
- kfree(aml_chip->rsv);
- aml_chip->rsv = NULL;
- }
- return err;
-}
-
-/**need fixed**/
-int aml_nand_scan_bbt(struct mtd_info *mtd)
-{
- return 0;
-}
-
-/* fixme, mxic's bad block identify is not checked yet! */
-//only read bad block labeled ops
-int aml_nand_scan_shipped_bbt(struct mtd_info *mtd)
-{
- struct nand_chip * chip = mtd->priv;
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
- unsigned char *data_buf;
- int32_t read_cnt, page, pages_per_blk;
- loff_t addr, offset;
- int start_blk =0, total_blk =0,i, j, bad_blk_cnt =0, phys_erase_shift;
- int realpage, col0_data=0, col0_oob=0, valid_page_num = 1;
- int col_data_sandisk[6], bad_sandisk_flag=0;
-
- phys_erase_shift = fls(mtd->erasesize) - 1;
- chip->pagebuf = -1;
- pages_per_blk = (1 << (chip->phys_erase_shift - chip->page_shift));
-
- data_buf = kzalloc(mtd->writesize, GFP_KERNEL);
- if (data_buf == NULL) {
- printk("%s %d malloc failed\n",__func__,__LINE__);
- return -ENOMEM;
- }
-
- /*need scan factory bad block in bootloader area*/
- start_blk = 0;
- total_blk = (int)(mtd->size >> phys_erase_shift);
- /* fixme, need check the total block number avoid mtd->size was changed outside! */
- printk("scaning flash total block %d\n", total_blk);
- do {
- offset = mtd->erasesize;
- offset *= start_blk;
- for (i=0; i < controller->chip_num; i++) {
- //if (aml_chip->valid_chip[i]) {
- for (read_cnt = 0; read_cnt < 3; read_cnt++) {
- if (read_cnt == 2) {
- if (aml_chip->mfr_type == NAND_MFR_AMD)
- addr = offset + mtd->writesize;
- else
- break;
- } else {
- if (aml_chip->mfr_type == NAND_MFR_SANDISK) {
- addr = offset + read_cnt*mtd->writesize;
- } else
- addr = offset +
- (pages_per_blk - 1) * read_cnt * mtd->writesize;
- }
-
- realpage = (int)(addr >> chip->page_shift);
- page = realpage & chip->pagemask;
-
- if (page != -1) {
- valid_page_num=mtd->writesize>>chip->page_shift;
- valid_page_num /= aml_chip->plane_num;
-
- aml_chip->page_addr = page/ valid_page_num;
- if (unlikely(aml_chip->page_addr >= aml_chip->internal_page_nums)) {
- aml_chip->page_addr -= aml_chip->internal_page_nums;
- aml_chip->page_addr |=
- (1 << aml_chip->internal_chip_shift)*aml_chip->internal_chipnr;
- }
- }
- if (aml_chip->plane_num == 2) {
- aml_chip->aml_nand_wait_devready(aml_chip, i);
- if (aml_nand_get_fbb_issue()) {
- chip->cmd_ctrl(mtd,
- NAND_CMD_SEQIN, NAND_CTRL_CLE);
- chip->cmd_ctrl(mtd,
- 0, NAND_CTRL_ALE);
- }
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_READ0,
- 0x00,aml_chip->page_addr, i);
-
- if (!aml_chip->aml_nand_wait_devready(aml_chip, i))
- printk ("%s, %d,selected chip%d not ready\n",
- __func__, __LINE__, i);
-
- if (aml_chip->ops_mode & AML_CHIP_NONE_RB)
- chip->cmd_ctrl(mtd,
- NAND_CMD_READ0 & 0xff,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
- udelay(2);
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_TWOPLANE_READ1,
- 0x00, aml_chip->page_addr, i);
- udelay(2);
-
- if (aml_chip->mfr_type == NAND_MFR_SANDISK) {
- for (j = 0; j < 6; j++)
- col_data_sandisk[j] = chip->read_byte(mtd);
- } else
- col0_data = chip->read_byte(mtd);
-
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_TWOPLANE_READ2,
- aml_chip->page_size,
- aml_chip->page_addr, i);
- //aml_chip->aml_nand_wait_devready(aml_chip, i);
- udelay(2);
-
- if (aml_chip->mfr_type == NAND_MFR_SANDISK)
- col0_oob = 0x0;
- else
- col0_oob = chip->read_byte(mtd);
- //printk("col0_oob=%x\n",col0_oob);
-
- } else if (aml_chip->plane_num == 1) {
-
- if (aml_nand_get_fbb_issue()) {
- chip->cmd_ctrl(mtd,
- NAND_CMD_SEQIN, NAND_CTRL_CLE);
- chip->cmd_ctrl(mtd,
- 0, NAND_CTRL_ALE);
- }
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_READ0, 0x00,
- aml_chip->page_addr , i);
- udelay(2);
-
- if (!aml_chip->aml_nand_wait_devready(aml_chip, i))
- printk ("%s, %d,selected chip%d not ready\n",
- __func__, __LINE__, i);
-
- if (aml_chip->ops_mode & AML_CHIP_NONE_RB)
- chip->cmd_ctrl(mtd,
- NAND_CMD_READ0 & 0xff,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
- udelay(2);
-
- if (aml_chip->mfr_type == NAND_MFR_SANDISK) {
- for (j = 0; j < 6; j++)
- col_data_sandisk[j] =
- chip->read_byte(mtd);
- } else
- col0_data = chip->read_byte(mtd);
-
- //printk("col0_data =%x\n",col0_data);
-
- if (aml_chip->mfr_type != NAND_MFR_SANDISK)
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_RNDOUT,
- aml_chip->page_size, -1, i);
- udelay(2);
-
- if (aml_chip->mfr_type == NAND_MFR_SANDISK)
- col0_oob = 0x0;
- else
- col0_oob = chip->read_byte(mtd);
- //printk("col0_oob =%x\n",col0_oob);
- }
-
- if ((aml_chip->mfr_type == 0xC8 )) {
- if ((col0_oob != 0xFF) || (col0_data != 0xFF)) {
- printk("detect factory Bad block:%llx blk:%d chip:%d\n",
- (uint64_t)addr, start_blk, i);
-
- aml_chip->block_status[start_blk] = NAND_FACTORY_BAD;
- break;
- }
- }
-
- if (aml_chip->mfr_type == NAND_MFR_AMD ) {
- if (col0_oob != 0xFF) {
- printk("detect factory Bad block:%llx blk:%d chip:%d\n",
- (uint64_t)addr, start_blk, i);
-
- aml_chip->block_status[start_blk] = NAND_FACTORY_BAD;
- break;
- }
- }
-
- if ((col0_oob == 0xFF))
- continue;
-
- if (col0_oob != 0xFF) {
- printk("%s:%d factory ship bbt found\n", __func__, __LINE__);
- if (aml_chip->mfr_type == 0xc2 ) {
- if (col0_oob != 0xFF) {
- printk("detect factory Bad block:%llx blk=%d chip=%d\n",
- (uint64_t)addr, start_blk, i);
- aml_chip->block_status[start_blk] = NAND_FACTORY_BAD;
- break;
- }
- }
-
- if (aml_chip->mfr_type == NAND_MFR_DOSILICON ||
- aml_chip->mfr_type == NAND_MFR_ATO ||
- aml_chip->mfr_type == NAND_MFR_HYNIX) {
- if (col0_oob != 0xFF) {
- pr_info("detect a fbb:%llx blk=%d chip=%d\n",
- (uint64_t)addr, start_blk, i);
-
- aml_chip->block_status[start_blk] =
- NAND_FACTORY_BAD;
- break;
- }
- }
-
- if (aml_chip->mfr_type == 0xef ) {
- if (col0_oob != 0xFF) {
- printk("detect factory Bad block:%llx blk=%d chip=%d\n",
- (uint64_t)addr, start_blk, i);
- aml_chip->block_status[start_blk] = NAND_FACTORY_BAD;
- break;
- }
- }
-
- if ((aml_chip->mfr_type == NAND_MFR_SANDISK) ) {
- for (j = 0; j < 6; j++) {
- if (col_data_sandisk[j] == 0x0) {
- bad_sandisk_flag = 1;
- break;
- }
- }
- if (bad_sandisk_flag ) {
- printk("detect factory Bad block:%llx blk=%d chip=%d\n",
- (uint64_t)addr, start_blk, i);
- aml_chip->block_status[start_blk] = NAND_FACTORY_BAD;
- bad_sandisk_flag=0;
- break;
- }
- }
-
- if ((aml_chip->mfr_type == NAND_MFR_SAMSUNG ) ) {
- if ((col0_oob != 0xFF) && (col0_data != 0xFF)) {
- printk("detect factory Bad block:%llx blk=%d chip=%d\n",
- (uint64_t)addr, start_blk, i);
- aml_chip->block_status[start_blk] = NAND_FACTORY_BAD;
- break;
- }
- }
-
- if ((aml_chip->mfr_type == NAND_MFR_TOSHIBA ) ) {
- if ((col0_oob != 0xFF) && (col0_data != 0xFF)) {
- printk("detect factory Bad block:%llx blk=%d chip=%d\n",
- (uint64_t)addr, start_blk, i);
- aml_chip->block_status[start_blk] = NAND_FACTORY_BAD;
- break;
- }
- }
-
- if (aml_chip->mfr_type == NAND_MFR_MICRON ) {
- if (col0_oob == 0x0) {
- printk("detect factory Bad block:%llx blk=%d chip=%d\n",
- (uint64_t)addr, start_blk, i);
- aml_chip->block_status[start_blk] = NAND_FACTORY_BAD;
- break;
- }
- }
- }
- }
- //}
- }
- } while((++start_blk) < total_blk);
-
- printk("aml_nand_scan_bbt: factory Bad block bad_blk_cnt=%d\n",
- bad_blk_cnt);
- kfree(data_buf);
- return 0;
-}
-
-int aml_nand_bbt_check(struct mtd_info *mtd)
-{
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
- struct aml_nand_chip *aml_chip_boot = mtd_to_nand_chip(nand_info[0]);
- int ret =0;
- int8_t *buf = NULL;
-
- ret = meson_rsv_scan(aml_chip->rsv->bbt);
- if ((ret !=0) && ((ret != (-1)))) {
- printk("%s %d\n", __func__, __LINE__);
- goto exit_error;
- }
-
- ret = 0;
- buf = aml_chip->block_status;
- if (aml_chip->rsv->bbt->valid == 1) {
- /*read bbt*/
- printk("%s %d bbt is valid, reading.\n", __func__, __LINE__);
- meson_rsv_read(aml_chip->rsv->bbt, (u_char *)buf);
- } else {
- printk("%s %d bbt is invalid, scanning.\n", __func__, __LINE__);
- /*no bbt haven't been found, abnormal or clean nand! rebuild*/
- aml_nand_scan_shipped_bbt(mtd);
- meson_rsv_bbt_write((u_char *)buf, aml_chip->rsv->bbt->size);
- }
-
- /*make uboot bbt perspective the same with normal bbt*/
- aml_chip_boot->block_status = aml_chip->block_status;
-exit_error:
- return ret;
-}
-
-/**read partiton from dtb**/
-extern int get_partition_from_dts(unsigned char * buffer);
-int amlnf_dtb_init_partitions(struct aml_nand_chip *aml_chip)
-{
- int ret = 0;
- u8 *dtb_buf = NULL;
-
- dtb_buf = kzalloc(aml_chip->dtbsize, GFP_KERNEL);
- if (dtb_buf == NULL) {
- printk("nand malloc for dtb_buf failed\n");
- ret = -1;
- goto exit_err;
- }
- memset(dtb_buf, 0x0, aml_chip->dtbsize);
-
- /*parse partitions table */
- ret = get_partition_from_dts(dtb_buf);
- if (ret) {
- printk("%s get_partition_from_dts failed\n", __func__);
- }
-exit_err:
- if (dtb_buf) {
- kfree(dtb_buf);
- dtb_buf = NULL;
- }
- return ret;
-}
-
-
diff --git a/drivers/mtd/nand/aml_nand/aml_nand.h b/drivers/mtd/nand/aml_nand/aml_nand.h
deleted file mode 100644
index 97cc334..0000000
--- a/drivers/mtd/nand/aml_nand/aml_nand.h
+++ /dev/null
@@ -1,548 +0,0 @@
-#ifndef __AML_SLCNAND_H_
-#define __AML_SLCNAND_H_
-
-
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/nand_ecc.h>
-#include <nand.h>
-#include <amlogic/aml_nand.h>
-#include "aml_hwctrl.h"
-#include <partition_table.h>
-#include <linux/mtd/partitions.h>
-
-#include <amlogic/aml_rsv.h>
-#include <amlogic/aml_mtd.h>
-
-#define NAND_MAX_DEVICE 4
-
-#define CONFIG_MTD_PARTITIONS 1
-
-/*MAX page list cnt for usrdef mode*/
-#define NAND_PAGELIST_CNT 16
-
-/*nand read retry info,max equal to zero,
-*that means no need retry*/
-struct nand_retry_t {
- unsigned id;
- unsigned max;
- unsigned no_rb;
-};
-
-typedef struct _nand_cmd {
- unsigned char type;
- unsigned char val;
-}nand_cmd_t;
-
-struct meson_slcnand_platdata {
- u32 reg_base;
- u8 nand_user_mode;
- u8 nand_ran_mode;
-};
-
-/**must same with arch/arm/include/asm/nand.h
-*ext bits:
-* bit 26: pagelist enable flag,
-* bit 24: a2 cmd enable flag,
-* bit 23: no_rb,
-* bit 22: large. large for what?
-* bit 19: randomizer mode.
-* bit 14-16: ecc mode
-* bit 13: short mode
-* bit 6-12: short page size
-* bit 0-5: ecc pages.
-***/
-typedef struct nand_setup {
- union {
- uint32_t d32;
- struct {
- unsigned cmd:22;
- unsigned large_page:1; //22
- unsigned no_rb:1; //23 from efuse
- unsigned a2:1; //24
- unsigned reserved25:1; //25
- unsigned page_list:1; //26
- unsigned sync_mode:2; //27 from efuse
- unsigned size:2; //29 from efuse
- unsigned active:1; //31
- }b;
- }cfg;
- uint16_t id;
- uint16_t max; //id:0x100 user,max:0 disable.
-} nand_setup_t;
-
-typedef struct _ext_info{
- uint32_t read_info; //nand_read_info;
- uint32_t new_type; //new_nand_type;
- uint32_t page_per_blk; //pages_in_block;
- uint32_t xlc; //slc=1,mlc=2,tlc=3;
- uint32_t ce_mask;
- /*copact mode: boot means whole uboot
- it's easy to understand that copies off_type
- bl2 and fip are the same.
- * discrete mode,boot means the fip only*/
- uint32_t boot_num;
- uint32_t each_boot_pages;
- /*for comptible reason*/
- uint32_t bbt_occupy_pages;
- uint32_t bbt_start_block;
-} ext_info_t;
-
-#define NAND_FIPMODE_COMPACT (0)
-#define NAND_FIPMODE_DISCRETE (1)
-
-/* if you don't need skip the bad blocks when address
- * partitions,please enable this macro.
- * #define CONFIG_NOT_SKIP_BAD_BLOCK
- */
-
-typedef struct _fip_info {
- uint16_t version; //version
- uint16_t mode; //compact or discrete
- uint32_t fip_start; //fip start,pages
-}fip_info_t;
-
- typedef struct _nand_page0 {
- nand_setup_t nand_setup; //8
- unsigned char page_list[16]; //16
- nand_cmd_t retry_usr[32]; //64(32 cmd max I/F)
- ext_info_t ext_info; //72
- /*added for slc nand in mtd drivers 20170503*/
- fip_info_t fip_info;
- }nand_page0_t; //384 byte max.
-
-
-typedef union nand_core_clk {
- /*raw register data*/
- uint32_t d32;
- struct {
- unsigned clk_div:7;
- unsigned reserved0:1;
- unsigned clk_en:1;
- unsigned clk_sel:3;
- unsigned not_used:20;
- }b;
-}nand_core_clk_t;
-
-/***************ERROR CODING*******************/
-#define NAND_CHIP_ID_ERR 1
-#define NAND_SHIP_BAD_BLOCK_ERR 2
-#define NAND_CHIP_REVB_HY_ERR 3
-
-/** Register defination **/
-#define NAND_BOOT_NAME "bootloader"
-#define NAND_NORMAL_NAME "nandnormal"
-#define NAND_RESERVED_NAME "nandreserved"
-
-
-#define BOOT_PAGES_PER_COPY (1024)
-#define BOOT_COPY_NUM (BOOT_TOTAL_PAGES/BOOT_PAGES_PER_COPY)
-
-
-#define AML_CHIP_NONE_RB 4
-#define AML_INTERLEAVING_MODE 8
-
-#define AML_NAND_CE0 0xe
-#define AML_NAND_CE1 0xd
-#define AML_NAND_CE2 0xb
-#define AML_NAND_CE3 0x7
-
-#define AML_BADBLK_POS 0
-
-#define NAND_ECC_OPTIONS_MASK 0x0000000f
-#define NAND_PLANE_OPTIONS_MASK 0x000000f0
-#define NAND_TIMING_OPTIONS_MASK 0x00000f00
-#define NAND_BUSW_OPTIONS_MASK 0x0000f000
-#define NAND_INTERLEAVING_OPTIONS_MASK 0x000f0000
-
-#define NAND_TWO_PLANE_MODE 0x00000010
-#define NAND_TIMING_MODE0 0x00000000
-#define NAND_TIMING_MODE1 0x00000100
-#define NAND_TIMING_MODE2 0x00000200
-#define NAND_TIMING_MODE3 0x00000300
-#define NAND_TIMING_MODE4 0x00000400
-#define NAND_TIMING_MODE5 0x00000500
-#define NAND_INTERLEAVING_MODE 0x00010000
-
-#define DEFAULT_T_REA 40
-#define DEFAULT_T_RHOH 0
-#define NAND_DEFAULT_OPTIONS (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)
-
-#define AML_NAND_BUSY_TIMEOUT 0x40000
-#define AML_DMA_BUSY_TIMEOUT 0x100000
-#define MAX_ID_LEN 8
-
-#define NAND_CMD_PLANE2_READ_START 0x06
-#define NAND_CMD_TWOPLANE_PREVIOS_READ 0x60
-#define NAND_CMD_TWOPLANE_READ1 0x5a
-#define NAND_CMD_TWOPLANE_READ2 0xa5
-#define NAND_CMD_TWOPLANE_WRITE2_MICRO 0x80
-#define NAND_CMD_TWOPLANE_WRITE2 0x81
-#define NAND_CMD_DUMMY_PROGRAM 0x11
-#define NAND_CMD_ERASE1_END 0xd1
-#define NAND_CMD_MULTI_CHIP_STATUS 0x78
-
-#define ONFI_TIMING_ADDR 0x01
-
-#define NAND_STATUS_READY_MULTI 0x20
-
-#define NAND_BLOCK_GOOD 0
-#define NAND_BLOCK_BAD 1
-#define NAND_FACTORY_BAD 2
-#define BAD_BLK_LEVEL 2
-#define FACTORY_BAD_BLOCK_ERROR 159
-#define MINI_PART_SIZE 0x100000
-#define NAND_MINI_PART_NUM 4
-#define MAX_BAD_BLK_NUM 2000
-#define MAX_MTD_PART_NUM 16
-#define MAX_MTD_PART_NAME_LEN 24
-
-#define NAND_SYS_PART_SIZE 0x8000000
-
-struct aml_nand_flash_dev {
- char *name;
- u8 id[MAX_ID_LEN];
- unsigned pagesize;
- unsigned chipsize;
- unsigned erasesize;
- unsigned oobsize;
- unsigned internal_chipnr;
- unsigned T_REA;
- unsigned T_RHOH;
- u8 onfi_mode;
- unsigned options;
-};
-
-struct aml_nand_part_info {
- char mtd_part_magic[4];
- char mtd_part_name[MAX_MTD_PART_NAME_LEN];
- uint64_t size;
- uint64_t offset;
- u_int32_t mask_flags;
-};
-
-struct aml_nand_bch_desc {
- char * name;
- unsigned bch_mode;
- unsigned bch_unit_size;
- unsigned bch_bytes;
- unsigned user_byte_mode;
-};
-
-struct aml_nand_chip {
- struct nand_chip chip;
- struct hw_controller *controller;
-
- /* mtd info */
- u8 mfr_type;
- unsigned onfi_mode;
- unsigned T_REA;
- unsigned T_RHOH;
- unsigned options;
- unsigned page_size;
- unsigned block_size;
- unsigned oob_size;
- unsigned virtual_page_size;
- unsigned virtual_block_size;
- u8 plane_num;
- u8 internal_chipnr;
- unsigned internal_page_nums;
-
- unsigned internal_chip_shift;
- unsigned int ran_mode;
- unsigned int rbpin_mode;
- unsigned int rbpin_detect;
- unsigned int short_pgsz;
- /* bch for infopage on short mode */
- unsigned int bch_info;
-
- unsigned bch_mode;
- u8 user_byte_mode;
- u8 ops_mode;
- u8 cached_prog_status;
- u8 max_bch_mode;
- unsigned valid_chip[MAX_CHIP_NUM];
- unsigned page_addr;
- unsigned char *aml_nand_data_buf;
- unsigned int *user_info_buf;
- int8_t *block_status;
- unsigned int toggle_mode;
- u8 ecc_cnt_limit;
- u8 ecc_cnt_cur;
- u8 ecc_max;
- unsigned zero_cnt;
- unsigned oob_fill_cnt;
- unsigned boot_oob_fill_cnt;
- /*add property field for key private data*/
- int dtbsize;
- int keysize;
- uint32_t boot_copy_num; /*tell how many bootloader copies*/
-
- u8 key_protect;
- unsigned char *rsv_data_buf;
-
- struct meson_rsv_handler_t *rsv;
-
- struct aml_nand_bch_desc *bch_desc;
- /* platform info */
- struct aml_nand_platform *platform;
-
- /* device info */
- struct device *device;
-
- unsigned max_ecc;
- struct ecc_desc_s * ecc;
- // unsigned onfi_mode;
- unsigned err_sts;
- /* plateform operation function*/
- void (*aml_nand_hw_init)(struct aml_nand_chip *aml_chip);
- void (*aml_nand_adjust_timing)(struct aml_nand_chip *aml_chip);
- int (*aml_nand_options_confirm)(struct aml_nand_chip *aml_chip);
- void (*aml_nand_cmd_ctrl)(struct aml_nand_chip *aml_chip,
- int cmd, unsigned int ctrl);
- void (*aml_nand_select_chip)(struct aml_nand_chip *aml_chip,
- int chipnr);
- void (*aml_nand_write_byte)(struct aml_nand_chip *aml_chip,
- uint8_t data);
- void (*aml_nand_get_user_byte)(struct aml_nand_chip *aml_chip,
- unsigned char *oob_buf, int byte_num);
- void (*aml_nand_set_user_byte)(struct aml_nand_chip *aml_chip,
- unsigned char *oob_buf, int byte_num);
- void (*aml_nand_command)(struct aml_nand_chip *aml_chip,
- unsigned command, int column, int page_addr, int chipnr);
- int (*aml_nand_wait_devready)(struct aml_nand_chip *aml_chip,
- int chipnr);
- int (*aml_nand_dma_read)(struct aml_nand_chip *aml_chip,
- unsigned char *buf, int len, unsigned bch_mode);
- int (*aml_nand_dma_write)(struct aml_nand_chip *aml_chip,
- unsigned char *buf, int len, unsigned bch_mode);
- int (*aml_nand_hwecc_correct)(struct aml_nand_chip *aml_chip,
- unsigned char *buf, unsigned size, unsigned char *oob_buf);
- int (*aml_nand_block_bad_scrub)(struct mtd_info *mtd);
-};
-
-struct aml_nand_platform {
- struct aml_nand_flash_dev *nand_flash_dev;
- char *name;
- unsigned chip_enable_pad;
- unsigned ready_busy_pad;
-
- /* DMA RD/WR delay loop timing */
- unsigned int T_REA; /* for dma wating delay */
- /* not equal of (nandchip->delay, which is for dev ready func)*/
- unsigned int T_RHOH;
- unsigned int ran_mode; /*def close, for all part*/
- unsigned int rbpin_mode; /*may get from romboot*/
- unsigned int rbpin_detect;
- unsigned int short_pgsz; /*zero means no short*/
-
- struct aml_nand_chip *aml_chip;
- struct platform_nand_data platform_nand_data;
-};
-
-struct aml_nand_device {
- struct aml_nand_platform *aml_nand_platform;
- u8 dev_num;
-};
-
-static inline struct aml_nand_chip *mtd_to_nand_chip(struct mtd_info *mtd)
-{
- struct nand_chip *chip = mtd->priv;
- return container_of(chip, struct aml_nand_chip, chip);
-}
-
-#ifdef CONFIG_PARAMETER_PAGE
-struct parameter_page {
- /*0~31 byte: Revision information and features block*/
- unsigned char signature[4];
- unsigned short ver;
- unsigned short feature;
- unsigned short opt_commd;
- unsigned short reserve0;
- unsigned short ex_para_page_len;
- unsigned char num_para_page;
- unsigned char reserve1[17];
- /*32~79 byte: Manufacturer information block*/
- unsigned char dev_manu[12];
- unsigned char dev_model[20];
- unsigned char JEDEC_manu_ID;
- unsigned short date_code;
- unsigned char reserve2[13];
- /*80~127 byte: Memory organization block*/
- unsigned int data_bytes_perpage;
- unsigned short spare_bytes_perpage;
- unsigned int data_bytes_perpartial;
- unsigned short spare_bytes_perpartial;
- unsigned int pages_perblk;
- unsigned int blks_perLUN;
- unsigned char num_LUN;
- /* 4-7: column addr cycles; 0-3: row addr cycles*/
- unsigned char num_addr_cycle;
- unsigned char bits_percell;
- unsigned short max_badblk_perLUN;
- unsigned short blk_edurce;
- /*Guaranteed valid blocks at beginning of target*/
- unsigned char g_v_blk_begin;
- unsigned short blk_edurce_g_v_blk;
- unsigned char progm_perpage;
- unsigned char prt_prog_att;//obsolete
- unsigned char bits_ECC_corretable;
- /*0-3: number of interleaved address bits*/
- unsigned char bits_intleav_addr;
- /*6-7 Reserved (0)
- 5 1 = lower bit XNOR block address restriction
- 4 1 = read cache supported
- 3 Address restrictions for cache operations
- 2 1 = program cache supported
- 1 1 = no block address restrictions
- 0 Overlapped / concurrent interleaving support
- */
- unsigned char intleav_op_attr;
- unsigned char reserve3[13];
- /*128~163 byte: Electrical parameters block*/
- unsigned char max_io_pin;
- /*6-15 Reserved (0)
- 5 1 = supports timing mode 5
- 4 1 = supports timing mode 4
- 3 1 = supports timing mode 3
- 2 1 = supports timing mode 2
- 1 1 = supports timing mode 1
- 0 1 = supports timing mode 0, shall be 1
- */
- unsigned short asy_time_mode;
- unsigned short asy_prog_cach_time_mode; /*obsolete*/
- unsigned short Tprog; /*Maximum page program time (Ts)*/
- unsigned short Tbers; /*Maximum block erase time (Ts)*/
- unsigned short Tr; /*Maximum page read time (Ts)*/
- unsigned short Tccs; /*Minimum change column setup time (ns)*/
- /* 6-15 Reserved (0)
- 5 1 = supports timing mode 5
- 4 1 = supports timing mode 4
- 3 1 = supports timing mode 3
- 2 1 = supports timing mode 2
- 1 1 = supports timing mode 1
- 0 1 = supports timing mode 0
- */
- unsigned short src_syn_time_mode;
- /*3-7 Reserved (0)
- 2 1 = device supports CLK stopped for data input
- 1 1 = typical capacitance values present
- 0 tCAD value to use
- */
- unsigned char src_syn_feature;
- unsigned short CLK_input_pin;
- unsigned short IO_pin;
- unsigned short input_pin;
- unsigned char max_input_pin;
- unsigned char dr_strgth;
- /*Maximum interleaved page read time (Ts)*/
- unsigned short Tir;
- /*Program page register clear enhancement tADL value (ns)*/
- unsigned short Tadl;
- unsigned char reserve4[8];
- /*164~255 byte: Vendor block*/
- unsigned short vd_ver;
- unsigned char vd_spec[88];
- unsigned short int_CRC;
- /*256~ byte: Redundant Parameter Pages*/
-
-}__attribute__ ((__packed__));
-#endif
-
-int aml_nand_init(struct aml_nand_chip *aml_chip);
-
-int aml_nand_read_page_raw(struct mtd_info *mtd,
- struct nand_chip *chip, uint8_t *buf, int oob_required, int page);
-
-int aml_nand_write_page_raw(struct mtd_info *mtd,
- struct nand_chip *chip, const uint8_t *buf, int oob_required,
- int page);
-
-int aml_nand_read_page_hwecc(struct mtd_info *mtd,
- struct nand_chip *chip, uint8_t *buf, int oob_required, int page);
-
-int aml_nand_write_page_hwecc(struct mtd_info *mtd,
- struct nand_chip *chip, const uint8_t *buf, int oob_required,
- int page);
-
-int aml_nand_read_oob(struct mtd_info *mtd,
- struct nand_chip *chip, int page);
-
-int aml_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, int page);
-
-int aml_nand_block_bad(struct mtd_info *mtd, loff_t ofs);
-
-int aml_nand_block_markbad(struct mtd_info *mtd, loff_t ofs);
-
-void aml_nand_dma_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
-
-void aml_nand_dma_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
-
-void aml_platform_cmd_ctrl(struct aml_nand_chip *aml_chip,
- int cmd, unsigned int ctrl);
-
-void aml_platform_write_byte(struct aml_nand_chip *aml_chip, uint8_t data);
-
-int aml_platform_wait_devready(struct aml_nand_chip *aml_chip, int chipnr);
-
-void aml_platform_get_user_byte(struct aml_nand_chip *aml_chip,
- unsigned char *oob_buf, int byte_num);
-
-void aml_platform_set_user_byte(struct aml_nand_chip *aml_chip,
- unsigned char *oob_buf, int byte_num);
-
-void aml_nand_base_command(struct aml_nand_chip *aml_chip,
- unsigned command, int column, int page_addr, int chipnr);
-
-int aml_nand_block_bad_scrub_update_bbt(struct mtd_info *mtd);
-
-int aml_ubootenv_init(struct aml_nand_chip *aml_chip);
-
-int amlnf_dtb_init(struct aml_nand_chip *aml_chip);
-
-int aml_key_init(struct aml_nand_chip *aml_chip);
-
-int aml_nand_erase_key(struct mtd_info *mtd);
-
-int aml_nand_bbt_check(struct mtd_info *mtd);/*fixed by liuxj*/
-
-int aml_nand_scan(struct mtd_info *mtd, int maxchips);
-
-int aml_nand_write_page_raw(struct mtd_info *mtd,
- struct nand_chip *chip, const uint8_t *buf, int oob_required,
- int page);
-
-int aml_nand_write_page(struct mtd_info *mtd,
- struct nand_chip *chip, uint32_t offset,
- int data_len,
- const uint8_t *buf,
- int oob_required, int page, int raw);
-
-void aml_nand_base_command(struct aml_nand_chip *aml_chip,
- unsigned command, int column, int page_addr, int chipnr);
-
-void aml_nand_command(struct mtd_info *mtd,
- unsigned command, int column, int page_addr);
-
-int aml_nand_wait(struct mtd_info *mtd, struct nand_chip *chip);
-
-int aml_nand_erase_cmd(struct mtd_info *mtd, int page);
-
-int m3_nand_boot_erase_cmd(struct mtd_info *mtd, int page);
-
-int m3_nand_boot_read_page_hwecc(struct mtd_info *mtd,
- struct nand_chip *chip, uint8_t *buf, int oob_required, int page);
-
-int m3_nand_boot_write_page_hwecc(struct mtd_info *mtd,
- struct nand_chip *chip, const uint8_t *buf, int oob_required,
- int page);
-
-int m3_nand_boot_write_page(struct mtd_info *mtd, struct nand_chip *chip,
- uint32_t offset, int data_len, const uint8_t *buf,
- int oob_required, int page, int raw);
-
-int aml_nand_get_fbb_issue(void);
-
-void aml_nand_check_fbb_issue(u8 *dev_id);
-
-#endif
diff --git a/drivers/mtd/nand/aml_nand/boot.c b/drivers/mtd/nand/aml_nand/boot.c
deleted file mode 100644
index 33f3717..0000000
--- a/drivers/mtd/nand/aml_nand/boot.c
+++ /dev/null
@@ -1,503 +0,0 @@
-#include <common.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <linux/err.h>
-#include <asm/cache.h>
-//#include <asm/arch/secure_apb.h>
-#include <asm/arch-g12a/cpu_id.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/nand_ecc.h>
-
-#include "aml_nand.h"
-#include "version.h"
-
-extern struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
-extern struct hw_controller *controller;
-/* provide a policy that caluate the bakups of bootloader */
-int get_boot_num(struct mtd_info *mtd, size_t rwsize)
-{
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
- size_t bad_blk_len_low = 0, bad_blk_len_up = 0, skip;
- size_t aviable_space;
- size_t block_len, block_off;
- loff_t block_start;
- loff_t offset = 0;
- int ret = 1; /*inital for only one copy*/
-
- if (!rwsize) { /*not need to policy call, only one */
- ret = 1;
- return ret;
- }
-
- /* algin with page size */
- rwsize = ((rwsize + mtd->writesize - 1)/mtd->writesize)*mtd->writesize;
-
- while (offset < mtd->size) {
- block_start = offset & ~(loff_t)(mtd->erasesize - 1);
- block_off = offset & (mtd->erasesize - 1);
- block_len = mtd->erasesize - block_off;
-
- if (nand_block_isbad(mtd, block_start)) {
- if ( offset < mtd->size / 2) /*no understand*/
- bad_blk_len_low += block_len;
- else if (offset > mtd->size / 2)
- bad_blk_len_up += block_len;
- else {
- bad_blk_len_up = offset;
- }
- }
- offset += block_len;
- }
-
- printk("rwsize:0x%zx skip_low:0x%zx skip_up:0x%zx\n",
- rwsize, bad_blk_len_low, bad_blk_len_up);
-
- skip = bad_blk_len_low + bad_blk_len_up;
- aviable_space = mtd->size - skip - 2 * mtd->writesize; /*no understand*/
-
- if (rwsize*2 <= aviable_space) {
- ret = 1;
- if (rwsize + mtd->writesize + bad_blk_len_low > mtd->size / 2)
- return 1; /*1st must be write*/
- if (rwsize + mtd->writesize + bad_blk_len_up <= mtd->size / 2)
- ret ++;
- } else /*needn't consider bad block length, unlikly so many bad blocks*/
- ret = 1;
-
- aml_chip->boot_copy_num = ret;
- printk("self-adaption boot count:%d\n", ret);
-
- return ret;
-}
-
-/*set nand info into page0_buf for romboot.*/
-void nand_info_page_prepare(struct aml_nand_chip *aml_chip, u8 *page0_buf)
-{
- struct nand_chip *chip = &aml_chip->chip;
- struct mtd_info *mtd = &chip->mtd;
- struct aml_nand_chip *aml_chip_normal = mtd_to_nand_chip(nand_info[1]);
- int nand_read_info;
- u32 configure_data;
- nand_page0_t *p_nand_page0 = NULL;
- ext_info_t *p_ext_info = NULL;
- nand_setup_t *p_nand_setup = NULL;
- int each_boot_pages, boot_num, bbt_pages;
- unsigned int pages_per_blk_shift ,bbt_size;
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- fip_info_t *p_fip_info = NULL;
-#endif
-
- pages_per_blk_shift = (chip->phys_erase_shift - chip->page_shift);
- bbt_size = aml_chip_normal->rsv->bbt->size;
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- boot_num = CONFIG_TPL_COPY_NUM;
- /* fip size */
- each_boot_pages = CONFIG_TPL_SIZE_PER_COPY / mtd->writesize;
-#else
- /* fixme, boot number self-adapt but not macro */
- boot_num = (!aml_chip->boot_copy_num)? 1: aml_chip->boot_copy_num;
- each_boot_pages = BOOT_TOTAL_PAGES / boot_num;
-#endif /* CONFIG_DISCRETE_BOOTLOADER */
-
- p_nand_page0 = (nand_page0_t *) page0_buf;
- p_nand_setup = &p_nand_page0->nand_setup;
- p_ext_info = &p_nand_page0->ext_info;
-
- configure_data = NFC_CMD_N2M(aml_chip->ran_mode,
- aml_chip->bch_mode, 0, (chip->ecc.size >> 3),
- chip->ecc.steps);
-
- memset(p_nand_page0, 0x0, sizeof(nand_page0_t));
- /* info_cfg->ext = (configure_data | (1<<23) |(1<<22) | (2<<20)); */
- /*p_nand_setup->cfg.d32 = (configure_data|(1<<23) | (1<<22) | (2<<20) | (1<<19));*/
- /* randomizer mode depends on chip's config */
- p_nand_setup->cfg.d32 = (configure_data|(1<<23) | (1<<22) | (2<<20));
- printk("cfg.d32 0x%x\n", p_nand_setup->cfg.d32);
- /* need finish here for romboot retry */
- p_nand_setup->id = 0;
- p_nand_setup->max = 0;
-
- /*fixme, alreay memset 0 */
- memset(p_nand_page0->page_list,
- 0,
- NAND_PAGELIST_CNT);
-
- /* chip_num occupy the lowest 2 bit */
- nand_read_info = controller->chip_num;
-
- p_ext_info->read_info = nand_read_info;
- p_ext_info->page_per_blk = aml_chip->block_size / aml_chip->page_size;
- /* fixme, only ce0 is enabled! */
- p_ext_info->ce_mask = 0x01;
- /* xlc is not in using for now */
- p_ext_info->xlc = 1;
- p_ext_info->boot_num = boot_num;
- p_ext_info->each_boot_pages = each_boot_pages;
- bbt_pages =
- (bbt_size + mtd->writesize - 1) / mtd->writesize;
- p_ext_info->bbt_occupy_pages = bbt_pages;
- p_ext_info->bbt_start_block =
- (BOOT_TOTAL_PAGES >> pages_per_blk_shift) + NAND_GAP_BLOCK_NUM;
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- p_fip_info = &p_nand_page0->fip_info;
- p_fip_info->version = 1;
- p_fip_info->mode = NAND_FIPMODE_DISCRETE;
- /* in pages, fixme, should it stored in amlchip? */
- p_fip_info->fip_start =
- 1024 + NAND_RSV_BLOCK_NUM * p_ext_info->page_per_blk;
- printk("bl: version %d, mode %d, start 0x%x\n",
- p_fip_info->version, p_fip_info->mode, p_fip_info->fip_start);
-#endif
- printk("page_per_blk = 0x%x bbt_pages = 0x%x \n",
- p_ext_info->page_per_blk, bbt_pages);
- printk("boot_num = %d each_boot_pages = %d\n", boot_num,
- each_boot_pages);
-}
-
-/* mtd support interface:
- * function:int (*_erase) (struct mtd_info *mtd, struct erase_info *instr);
- */
-int m3_nand_boot_erase_cmd(struct mtd_info *mtd, int page)
-{
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
- struct nand_chip *chip = mtd->priv;
- loff_t ofs;
-
- ofs = (page << chip->page_shift);
-
- if (chip->block_bad(mtd, ofs))
- return 0;
- aml_chip->aml_nand_select_chip(aml_chip, 0);
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_ERASE1, -1, page, 0);
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_ERASE2, -1, -1, 0);
- chip->waitfunc(mtd, chip);
-
- return 0;
-}
-
-/* mtd support interface:
- * chip->ecc.read_page
- * function:int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
- * uint8_t *buf, int oob_required, int page);
- */
-int m3_nand_boot_read_page_hwecc(struct mtd_info *mtd,
- struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
-{
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
- uint8_t *oob_buf = chip->oob_poi;
- unsigned nand_page_size = chip->ecc.steps * chip->ecc.size;
- unsigned pages_per_blk_shift =chip->phys_erase_shift - chip->page_shift;
- int user_byte_num = (chip->ecc.steps * aml_chip->user_byte_mode);
- int bch_mode = aml_chip->bch_mode, ran_mode=0;
- int error = 0, i = 0, stat = 0;
- int ecc_size, configure_data_w, pages_per_blk_w, configure_data;
- int pages_per_blk, read_page;
- int en_slc = 0;
- /* using info page structure */
- nand_page0_t *p_nand_page0 = NULL;
- ext_info_t *p_ext_info = NULL;
- nand_setup_t * p_nand_setup = NULL;
- int each_boot_pages, boot_num;
- loff_t ofs;
-
-
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- boot_num = CONFIG_BL2_COPY_NUM;
-#else
- boot_num = (!aml_chip->boot_copy_num)? 1: aml_chip->boot_copy_num;
-#endif
-
- each_boot_pages = BOOT_TOTAL_PAGES/boot_num;
-
- if (page >= (each_boot_pages * boot_num)) {
- memset(buf, 0, (1 << chip->page_shift));
- printk("nand boot read out of uboot failed, page:%d\n", page);
- goto exit;
- }
- /* nand page info */
- if ((page % each_boot_pages) == 0) {
- if (aml_chip->bch_mode == NAND_ECC_BCH_SHORT)
- configure_data_w =
- NFC_CMD_N2M(aml_chip->ran_mode,
- NAND_ECC_BCH60_1K, 1, (chip->ecc.size >> 3), chip->ecc.steps);
- else
- configure_data_w =
- NFC_CMD_N2M(aml_chip->ran_mode,
- aml_chip->bch_mode, 0, (chip->ecc.size >> 3), chip->ecc.steps);
-
- ecc_size = chip->ecc.size; //backup ecc size
-
- if (aml_chip->bch_mode != NAND_ECC_BCH_SHORT) {
- nand_page_size =
- (mtd->writesize / 512) * NAND_ECC_UNIT_SHORT;
- bch_mode = NAND_ECC_BCH_SHORT;
- chip->ecc.size = NAND_ECC_UNIT_SHORT;
- } else
- bch_mode = aml_chip->bch_mode;
-
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
- memset(buf, 0xff, (1 << chip->page_shift));
- /* read back page0 and check it */
- if (aml_chip->valid_chip[0]) {
- if (!aml_chip->aml_nand_wait_devready(aml_chip, i)) {
- printk("don't found selected chip:%d ready\n",
- i);
- error = -EBUSY;
- }
- if (aml_chip->ops_mode & AML_CHIP_NONE_RB)
- chip->cmd_ctrl(mtd, NAND_CMD_READ0 & 0xff,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
- if (en_slc == 0) {
- ran_mode = aml_chip->ran_mode;
- aml_chip->ran_mode = 1;
- }
- error = aml_chip->aml_nand_dma_read(aml_chip,
- buf, nand_page_size, bch_mode);
-
- if (error) {
- printk(" page0 aml_nand_dma_read failed\n");
- }
-
- aml_chip->aml_nand_get_user_byte(aml_chip,
- oob_buf, user_byte_num);
- stat = aml_chip->aml_nand_hwecc_correct(aml_chip,
- buf, nand_page_size, oob_buf);
- if (stat < 0) {
- if(aml_chip->ran_mode
- && (aml_chip->zero_cnt < aml_chip->ecc_max)) {
- memset(buf, 0xff, nand_page_size);
- memset(oob_buf, 0xff, user_byte_num);
- } else {
- mtd->ecc_stats.failed++;
- printk("page0 read ecc failed at blk0 chip0\n");
- }
- } else
- mtd->ecc_stats.corrected += stat;
- if (en_slc == 0)
- aml_chip->ran_mode = ran_mode;
- } else {
- printk("nand boot page 0 no valid chip failed\n");
- error = -ENODEV;
- //goto exit;
- }
-
- //check page 0 info here
- p_nand_page0 = (nand_page0_t *) buf;
- p_nand_setup = &p_nand_page0->nand_setup;
- p_ext_info = &p_nand_page0->ext_info;
-
- configure_data = p_nand_setup->cfg.b.cmd;
- pages_per_blk = p_ext_info->page_per_blk;
- pages_per_blk_w =
- (1 << (chip->phys_erase_shift - chip->page_shift));
-
- if ((pages_per_blk_w != pages_per_blk)
- || (configure_data != configure_data_w))
- printk("page%d warnning, configure:0x%x-0x%x "
- "pages_per_blk:0x%x-0x%x\n",
- page, configure_data_w, configure_data,
- pages_per_blk_w, pages_per_blk);
- #ifdef CONFIG_DISCRETE_BOOTLOADER
- /* fixme, check fip_info_t */
- printk(" TODO: check fip info\n");
- #endif
- bch_mode = aml_chip->bch_mode;
- chip->ecc.size = ecc_size;
- nand_page_size = chip->ecc.steps * chip->ecc.size;
- }
-
- read_page = page;
- read_page++;
-READ_BAD_BLOCK:
- ofs = (read_page << chip->page_shift);
- if (!(ofs % mtd->erasesize)) {
- if (chip->block_bad(mtd, ofs)) {
- read_page +=
- 1 << (chip->phys_erase_shift-chip->page_shift);
- goto READ_BAD_BLOCK;
- }
- }
-
- chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, read_page);
-
- memset(buf, 0xff, (1 << chip->page_shift));
- if (aml_chip->valid_chip[0]) {
- if (!aml_chip->aml_nand_wait_devready(aml_chip, 0)) {
- printk("don't found selected chip0 ready, page: %d \n",
- page);
- error = -EBUSY;
- goto exit;
- }
- if (aml_chip->ops_mode & AML_CHIP_NONE_RB)
- chip->cmd_ctrl(mtd, NAND_CMD_READ0 & 0xff,
- NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
-
- error = aml_chip->aml_nand_dma_read(aml_chip,
- buf, nand_page_size, bch_mode);
- if (error) {
- error = -ENODEV;
- printk("aml_nand_dma_read failed: page:%d \n", page);
- goto exit;
- }
-
- aml_chip->aml_nand_get_user_byte(aml_chip,
- oob_buf, user_byte_num);
- stat = aml_chip->aml_nand_hwecc_correct(aml_chip,
- buf, nand_page_size, oob_buf);
- if (stat < 0) {
- error = -ENODEV;
- mtd->ecc_stats.failed++;
- printk("read data ecc failed at page%d blk%d chip%d\n",
- page, (page >> pages_per_blk_shift), i);
- } else
- mtd->ecc_stats.corrected += stat;
- } else
- error = -ENODEV;
-
-exit:
- return error;
-}
-
-
-/* mtd support interface:
- * chip->ecc.write_page
- * function:int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
- * uint8_t *buf, int oob_required, int page);
- */
-int m3_nand_boot_write_page_hwecc(struct mtd_info *mtd,
- struct nand_chip *chip, const uint8_t *buf, int oob_required,
- int page)
-{
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
- uint8_t *oob_buf = chip->oob_poi;
- unsigned nand_page_size = chip->ecc.steps * chip->ecc.size;
- int user_byte_num = (chip->ecc.steps * aml_chip->user_byte_mode);
- int error = 0, i = 0, bch_mode, ecc_size;
- int each_boot_pages, boot_num;
-
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- boot_num = CONFIG_BL2_COPY_NUM;
-#else
- boot_num = (!aml_chip->boot_copy_num)? 1: aml_chip->boot_copy_num;
-#endif
-
- each_boot_pages = BOOT_TOTAL_PAGES/boot_num;
-
- ecc_size = chip->ecc.size;
- if (((aml_chip->page_addr % each_boot_pages) == 0)
- && (aml_chip->bch_mode != NAND_ECC_BCH_SHORT)) {
- nand_page_size = (mtd->writesize / 512) * NAND_ECC_UNIT_SHORT;
- bch_mode = NAND_ECC_BCH_SHORT;
- chip->ecc.size = NAND_ECC_UNIT_SHORT;
- } else
- bch_mode = aml_chip->bch_mode;
- /* setting magic for romboot checks. */
- for (i = 0; i < mtd->oobavail; i += 2) {
- oob_buf[i] = 0x55;
- oob_buf[i+1] = 0xaa;
- }
-
- i = 0;
- if (aml_chip->valid_chip[i]) {
- aml_chip->aml_nand_select_chip(aml_chip, i);
- aml_chip->aml_nand_set_user_byte(aml_chip,
- oob_buf, user_byte_num);
- error = aml_chip->aml_nand_dma_write(aml_chip,
- (unsigned char *)buf, nand_page_size, bch_mode);
- if (error)
- goto exit;
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_PAGEPROG, -1, -1, i);
- } else {
- error = -ENODEV;
- goto exit;
- }
-exit:
- if (((aml_chip->page_addr % each_boot_pages) == 0)
- && (aml_chip->bch_mode != NAND_ECC_BCH_SHORT))
- chip->ecc.size = ecc_size;
- return error;
-}
-
-/* mtd support interface:
- * chip->write_page
- * function: int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
- * uint32_t offset, int data_len, const uint8_t *buf,
- * int oob_required, int page, int cached, int raw);
- */
-int m3_nand_boot_write_page(struct mtd_info *mtd, struct nand_chip *chip,
- uint32_t offset, int data_len, const uint8_t *buf,
- int oob_required, int page, int raw)
-{
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
- int status, write_page, ran_mode=0;
- int en_slc = 0, each_boot_pages, boot_num;
- loff_t ofs;
-
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- boot_num = CONFIG_BL2_COPY_NUM;
-#else
- boot_num = (!aml_chip->boot_copy_num)? 1: aml_chip->boot_copy_num;
-#endif
- each_boot_pages = BOOT_TOTAL_PAGES / boot_num;
-
- /* actual page to be written */
- write_page = page;
- /* zero page of each copy */
- if ((write_page % each_boot_pages) == 0) {
- nand_info_page_prepare(aml_chip, chip->buffers->databuf);
- chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, write_page);
- /* must enable ran_mode for info page */
- if (en_slc == 0) {
- ran_mode = aml_chip->ran_mode;
- aml_chip->ran_mode = 1;
- }
- chip->ecc.write_page(mtd, chip, chip->buffers->databuf, 0, 0);
- if (en_slc == 0)
- aml_chip->ran_mode = ran_mode;
-
- status = chip->waitfunc(mtd, chip);
-
- if (status & NAND_STATUS_FAIL) {
- printk("uboot wr 0 page=0x%x, status=0x%x\n",
- page, status);
- return -EIO;
- }
- }
- /* +1 for skipping nand info page */
- if (en_slc) {
- } else
- write_page++;
-
-WRITE_BAD_BLOCK:
- ofs = (write_page << chip->page_shift);
- if (!(ofs % mtd->erasesize)) {
- if (chip->block_bad(mtd, ofs)) {
- write_page +=
- 1 << (chip->phys_erase_shift-chip->page_shift);
- goto WRITE_BAD_BLOCK;
- }
- }
- chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, write_page);
-
- if (unlikely(raw))
- chip->ecc.write_page_raw(mtd, chip, buf, 0, 0);
- else
- chip->ecc.write_page(mtd, chip, buf, 0, 0);
-
- if (!(chip->options & NAND_CACHEPRG)) {
- status = chip->waitfunc(mtd, chip);
-
- if (status & NAND_STATUS_FAIL) {
- printk("uboot wr page=0x%x, status=0x%x\n",
- page,status);
- return -EIO;
- }
- } else
- status = chip->waitfunc(mtd, chip);
- return 0;
-}
diff --git a/drivers/mtd/nand/aml_nand/cmd_amlmtd.c b/drivers/mtd/nand/aml_nand/cmd_amlmtd.c
deleted file mode 100644
index 4d04071..0000000
--- a/drivers/mtd/nand/aml_nand/cmd_amlmtd.c
+++ /dev/null
@@ -1,598 +0,0 @@
-/*cmd c files for aml mtd,overide amlnf cmds*/
-#include <config.h>
-#include <common.h>
-#include <command.h>
-#include <environment.h>
-#include <nand.h>
-#include "aml_nand.h"
-
-extern struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
-
-/* debug macros */
-#define CONFIG_AML_MTD_DBG (1)
-#ifdef CONFIG_AML_MTD_DBG
-static void dump_args(int argc, char * const argv[])
-{
- int i;
- /* debug codes for mtd cmd */
- for (i = 0; i < argc; i++)
- printk("arg %d: %s\n", i, argv[i]);
-
- return;
-}
-#else
-static void dump_args(int argc, char * const argv[])
-{
- return;
-}
-#endif
-
-/*
- * operations for bootloader
- * we call it rom as legarcy reasons.
- * call nand's opeartions.
- * switch to normal device after doing this.
- */
-#define CONFIG_AMLMTD_CURRDEV (0)
-extern int set_mtd_dev(int dev);
-extern int get_mtd_dev(void);
-static int do_rom_ops(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- int ret = 0;
- int copy_num = 4;
- int i;
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- ulong cpy;
-#endif
- char *sub;
- struct mtd_info *nand;
- unsigned long addr;
- int base = 2;
- u64 off, maxsize;
- size_t rwsize, limit, wsize;
-#if (CONFIG_AMLMTD_CURRDEV)
- int curr_mtd_dev;
-#endif
- printk("%s(): argc %d\n", __func__, argc);
- dump_args(argc, argv);
-#if (CONFIG_AMLMTD_CURRDEV)
- curr_mtd_dev = get_mtd_dev();
- if (curr_mtd_dev != 0)
- set_mtd_dev(0);
-#endif
- nand = nand_info[0];
- maxsize = nand->size;
- if (strlen(argv[1]) > 3)
- sub = &argv[1][4];
- else {
- sub = argv[2];
- base = 3;
- }
- if (!strcmp("read", sub)) {
- printk("%s() %s\n", __func__, sub);
- if (argc - base < 3) {
- ret = CMD_RET_USAGE;
- goto _out;
- }
- addr = (ulong)simple_strtoul(argv[base], NULL, 16);
- off = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
- rwsize = (ulong)simple_strtoul(argv[base + 2], NULL, 16);
- ret = nand_read_skip_bad(nand, off, &rwsize,
- NULL, maxsize, (u8 *)addr);
- } else if (!strcmp("write", sub)) {
- printk("%s() %s\n", __func__, sub);
- if (argc - base < 2) {
- ret = CMD_RET_USAGE;
- goto _out;
- }
- addr = (ulong)simple_strtoul(argv[base], NULL, 16);
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- limit = nand->size / CONFIG_BL2_COPY_NUM;
- /* write all copies if off do not exist */
- if (argc -base == 2) {
- off = 0;
- rwsize = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
- copy_num = CONFIG_BL2_COPY_NUM;
- } else {
- off = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
- rwsize = (ulong)simple_strtoul(argv[base + 2], NULL, 16);
- copy_num = 1;
- }
-#else
- /* write all, offset must be 0 */
- off = 0;
- rwsize = (ulong)simple_strtoul(argv[base + 2], NULL, 16);
- copy_num = get_boot_num(nand, rwsize);
- limit = nand->size / copy_num;
-#endif
- printf("%s() %d\n", __func__, copy_num);
- wsize = rwsize;
- for (i = 0; i < copy_num; i++) {
- ret = nand_write_skip_bad(nand, off, &rwsize,
- NULL, limit,
- (u8 *)addr, 0);
- if (ret)
- rwsize = wsize;
- off += nand->size/copy_num;
- }
- } else if (!strcmp("erase", sub)) {
- nand_erase_options_t opts;
- printk("%s() %s\n", __func__, sub);
- memset(&opts, 0, sizeof(opts));
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- if (argc - base == 0) {
- opts.offset = 0;
- /* whole boot area size */
- opts.length = nand->size;
- } else {
- cpy = (ulong)simple_strtoul(argv[base], NULL, 16);
- copy_num = CONFIG_BL2_COPY_NUM;
- if (cpy >= copy_num) {
- printk("max cpies %d\n", copy_num);
- ret = CMD_RET_USAGE;
- goto _out;
- }
- opts.offset = nand->size / copy_num * cpy;
- opts.length = nand->size / copy_num;
-
- }
-#else
- /* whole boot area size */
- opts.offset = 0;
- opts.length = nand->size;
-#endif
- opts.jffs2 = 0;
- opts.quiet = 0;
- opts.spread = 0;
- ret = nand_erase_opts(nand, &opts);
-
- } else {
- ret = CMD_RET_USAGE;
- goto _out;
- }
-
-_out:
-#if (CONFIG_AMLMTD_CURRDEV)
- /* restore mtd device */
- if (curr_mtd_dev != 0)
- set_mtd_dev(curr_mtd_dev);
-#endif
- return ret;
-}
-
-#ifdef CONFIG_DISCRETE_BOOTLOADER
-/* bl2 operations */
-static int do_bl2_ops(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- int ret = 0;
- int copy_num = 4;
- int i;
- ulong cpy;
- char *sub;
- struct mtd_info *nand;
- unsigned long addr;
- int base = 2;
- u64 off, maxsize;
- size_t rwsize, limit, wsize;
- /* fixme, using this?! */
-#if (CONFIG_AMLMTD_CURRDEV)
- int curr_mtd_dev;
-#endif
- printk("%s(): argc %d\n", __func__, argc);
- dump_args(argc, argv);
-#if (CONFIG_AMLMTD_CURRDEV)
- curr_mtd_dev = get_mtd_dev();
- if (curr_mtd_dev != 0)
- set_mtd_dev(0);
-#endif
- nand = nand_info[0];
- maxsize = nand->size;
- limit = maxsize / CONFIG_BL2_COPY_NUM;
- if (strlen(argv[1]) > 3)
- sub = &argv[1][4];
- else {
- sub = argv[2];
- base = 3;
- }
- if (!strcmp("info", sub)) {
- printk("bl2 infos:\ncopies %d\n", CONFIG_BL2_COPY_NUM);
- } else if (!strcmp("read", sub)) {
- printk("%s() %s\n", __func__, sub);
- if (argc - base < 3) {
- ret = CMD_RET_USAGE;
- goto _out;
- }
- addr = (ulong)simple_strtoul(argv[base], NULL, 16);
- cpy = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
- rwsize = (ulong)simple_strtoul(argv[base + 2], NULL, 16);
- off = cpy * limit;
- ret = nand_read_skip_bad(nand, off, &rwsize,
- NULL, limit,
- (u8 *)addr);
- } else if (!strcmp("write", sub)) {
- printk("%s() %s\n", __func__, sub);
- if (argc - base < 2) {
- ret = CMD_RET_USAGE;
- goto _out;
- }
- addr = (ulong)simple_strtoul(argv[base], NULL, 16);
- /* write all copies if off do not exist */
- if (argc - base == 2) {
- off = 0;
- rwsize = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
- copy_num = CONFIG_BL2_COPY_NUM;
- } else {
- cpy = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
- off = cpy * limit;
- rwsize = (ulong)simple_strtoul(argv[base + 2], NULL, 16);
- copy_num = 1;
- }
- printf("%s() %d\n", __func__, copy_num);
- wsize = rwsize;
- for (i = 0; i < copy_num; i++) {
- ret = nand_write_skip_bad(nand, off, &rwsize,
- NULL, limit,
- (u8 *)addr, 0);
- if (ret)
- rwsize = wsize;
- off += nand->size/copy_num;
- }
- } else if (!strcmp("erase", sub)) {
- nand_erase_options_t opts;
- printk("%s() %s\n", __func__, sub);
- memset(&opts, 0, sizeof(opts));
- if (argc - base == 0) {
- opts.offset = 0;
- /* whole boot area size */
- opts.length = nand->size;
- } else {
- copy_num = CONFIG_BL2_COPY_NUM;
- cpy = (ulong)simple_strtoul(argv[base], NULL, 16);
- if (cpy >= copy_num) {
- printk("max cpies %d\n", copy_num);
- ret = CMD_RET_USAGE;
- goto _out;
- }
- opts.offset = nand->size / copy_num * cpy;
- opts.length = nand->size / copy_num;
- }
- printf("%s, off 0x%llx, len 0x%llx\n", __func__, opts.offset, opts.length);
-
- opts.jffs2 = 0;
- opts.quiet = 0;
- opts.spread = 0;
- ret = nand_erase_opts(nand, &opts);
-
- } else {
- ret = CMD_RET_USAGE;
- goto _out;
- }
-
-_out:
-#if (CONFIG_AMLMTD_CURRDEV)
- /* restore mtd device */
- if (curr_mtd_dev != 0)
- set_mtd_dev(curr_mtd_dev);
-#endif
- return ret;
-}
-
-static int do_fip_ops(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
-{
- int ret = 0;
- int copy_num = 1;
- int i;
- char *sub;
- struct mtd_info *nand;
- ulong addr;
- ulong cpy;
- int base = 2;
- u64 off, maxsize = CONFIG_TPL_SIZE_PER_COPY*CONFIG_TPL_COPY_NUM;
- u64 fip_base;
- size_t rwsize, wsize;
-
- /* fixme, using this?! */
-#if (CONFIG_AMLMTD_CURRDEV)
- int curr_mtd_dev;
-#endif
- printk("%s(): argc %d\n", __func__, argc);
- dump_args(argc, argv);
-#if (CONFIG_AMLMTD_CURRDEV)
- curr_mtd_dev = get_mtd_dev();
- if (curr_mtd_dev != 0)
- set_mtd_dev(0);
-#endif
- nand = nand_info[1];
- if (strlen(argv[1]) > 3)
- sub = &argv[1][4];
- else {
- sub = argv[2];
- base = 3;
- }
- /*calculate the fip_start_addr*/
- fip_base = 1024*nand->writesize + NAND_RSV_BLOCK_NUM*nand->erasesize;
- if (!strcmp("read", sub)) {
- printk("%s() %s\n", __func__, sub);
- if (argc - base < 2) {
- ret = CMD_RET_USAGE;
- goto _out;
- }
- addr = (ulong)simple_strtoul(argv[base], NULL, 16);
- off = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
- rwsize = (ulong)simple_strtoul(argv[base + 2], NULL, 16);
- off +=fip_base;
- ret = nand_read_skip_bad(nand,
- off, &rwsize, NULL, maxsize, (u8 *)addr);
- } else if (!strcmp("write", sub)) {
- printk("%s() %s\n", __func__, sub);
- if (argc - base < 2) {
- ret = CMD_RET_USAGE;
- goto _out;
- }
- addr = (ulong)simple_strtoul(argv[base], NULL, 16);
- if (argc - base == 2) {
- off = fip_base;
- rwsize = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
- copy_num = CONFIG_TPL_COPY_NUM;
- printk("%s %d: off=0x%llx rwsize=0x%zx\n",
- __func__, __LINE__, off, rwsize);
-
- } else {
- //addr off size
- off = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
- off += fip_base;
- rwsize = (ulong)simple_strtoul(argv[base + 2], NULL, 16);
- copy_num = 1;
- }
- if (rwsize > CONFIG_TPL_SIZE_PER_COPY) {
- printk("size %ld > max per cpy %d\n", rwsize, CONFIG_TPL_COPY_NUM);
- ret = CMD_RET_USAGE;
- goto _out;
- }
- wsize = rwsize;
- /* fixme, write it once! */
- for (i = 0; i < copy_num; i++) {
- printk("cpy %d\n", i);
- ret = nand_write_skip_bad(nand,
- off, &rwsize, NULL, CONFIG_TPL_SIZE_PER_COPY, (u8 *)addr, 0);
- if (ret)
- rwsize = wsize;
- off += CONFIG_TPL_SIZE_PER_COPY;
- }
-
- } else if (!strcmp("erase", sub)) {
- nand_erase_options_t opts;
- printk("%s() %s, base %d\n", __func__, sub, base);
- memset(&opts, 0, sizeof(opts));
- if (argc - base == 0) {
- opts.offset = fip_base;
- /* whole boot area size */
- opts.length = maxsize;
- } else {
- cpy = (ulong)simple_strtoul(argv[base], NULL, 16);
- if (cpy >= CONFIG_TPL_COPY_NUM) {
- printk("max cpies %d\n", CONFIG_TPL_COPY_NUM);
- ret = CMD_RET_USAGE;
- goto _out;
- }
- opts.offset = fip_base + cpy * CONFIG_TPL_SIZE_PER_COPY;
- opts.length = CONFIG_TPL_SIZE_PER_COPY;
- }
- opts.jffs2 = 0;
- opts.quiet = 0;
- opts.spread = 0;
- ret = nand_erase_opts(nand, &opts);
- } else if (!strcmp("info", sub)) {
- printk("tpl infos:\ncopies %d, size/copy 0x%x\n",
- CONFIG_TPL_COPY_NUM, CONFIG_TPL_SIZE_PER_COPY);
- } else{
- ret = CMD_RET_USAGE;
- goto _out;
- }
-_out:
-#if (CONFIG_AMLMTD_CURRDEV)
- /* restore mtd device */
- if (curr_mtd_dev != 0)
- set_mtd_dev(curr_mtd_dev);
-#endif
- return ret;
-}
-#endif
-/****operations for dtb.****/
-static int do_dtb_ops(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
-{
- int ret = 0;
- printk("%s(): argc %d\n", __func__, argc);
- dump_args(argc, argv);
- char *sub;
- int base = 2;
- unsigned long addr;
- u64 size = 0;
-
- if (strlen(argv[1]) > 3)
- sub = &argv[1][4];
- else {
- sub = argv[2];
- base = 3;
- }
-
- if (!strcmp("read", sub)) {
- printk("%s() %s\n", __func__, sub);
- addr = (ulong)simple_strtoul(argv[base], NULL, 16);
- size = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
- ret = meson_rsv_dtb_read((u8 *)addr, (int)size);
- printk("%s(): %llu bytes %s : %s\n",
- __func__,
- size,
- sub,
- ret ? "ERROR" : "OK");
- } else if (!strcmp("write", sub)) {
- printk("%s() %s\n", __func__, sub);
- addr = (ulong)simple_strtoul(argv[base], NULL, 16);
- size = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
- ret = meson_rsv_dtb_write((u8 *)addr, (unsigned int)size);
- printk("%s(): %llu bytes %s : %s\n",
- __func__,
- size,
- sub,
- ret ? "ERROR" : "OK");
- } else if (!strcmp("erase", sub)) {
- printk("%s() %s\n", __func__, sub);
- ret = meson_rsv_dtb_erase();
- printk("%s() erase %s\n", __func__, ret ? "Fail" : "Okay");
- } else
- return CMD_RET_USAGE;
-
- return ret;
-}
-
-/*
- * operations for key.
- * should never be used by users, just for nand team debug.
- */
-static int do_key_ops(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
-{
- int ret = 0;
- printk("%s(): argc %d\n", __func__, argc);
- dump_args(argc, argv);
- char *sub;
- int base = 2;
- unsigned long addr;
- u64 size = 0;
-
- if (strlen(argv[1]) > 3)
- sub = &argv[1][4];
- else {
- sub = argv[2];
- base = 3;
- }
-
- if (!strcmp("read", sub)) {
- printk("%s() %s\n", __func__, sub);
- addr = (ulong)simple_strtoul(argv[base], NULL, 16);
- size = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
- ret = meson_rsv_key_read((u8 *)addr, (int)size);
- printk("%s(): %llu bytes %s : %s\n",
- __func__,
- size,
- sub,
- ret ? "ERROR" : "OK");
- } else if (!strcmp("write", sub)) {
- printk("%s() %s\n", __func__, sub);
- addr = (ulong)simple_strtoul(argv[base], NULL, 16);
- size = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
- ret = meson_rsv_key_write((u8 *)addr, (int)size);
- printk("%s(): %llu bytes %s : %s\n",
- __func__,
- size,
- sub,
- ret ? "ERROR" : "OK");
- } else if (!strcmp("erase", sub)) {
- printk("%s() %s\n", __func__, sub);
- ret = meson_rsv_key_erase();
- printk("%s() erase %s\n", __func__, ret ? "Fail" : "Okay");
- } else
- return CMD_RET_USAGE;
-
- return ret;
-}
-
-/*for test*/
-extern int meson_rsv_bbt_erase(void);
-static int do_bbt_ops(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
-{
- int ret = 0;
- printk("%s(): argc %d\n", __func__, argc);
- dump_args(argc, argv);
- char *sub;
-
- if (strlen(argv[1]) > 3)
- sub = &argv[1][4];
- else {
- sub = argv[2];
- }
-
- if (!strcmp("erase", sub)) {
- printk("%s() %s\n", __func__, sub);
- ret = meson_rsv_bbt_erase();
- printk("%s() erase %s\n", __func__, ret ? "Fail" : "Okay");
- } else
- return CMD_RET_USAGE;
-
- return ret;
-}
-
-
-static cmd_tbl_t cmd_amlmtd_sub[] = {
- U_BOOT_CMD_MKENT(rom, 5, 0, do_rom_ops, "", ""),
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- U_BOOT_CMD_MKENT(bl2, 5, 0, do_bl2_ops, "", ""),
- U_BOOT_CMD_MKENT(fip, 5, 0, do_fip_ops, "", ""),
-#endif
- U_BOOT_CMD_MKENT(dtb, 5, 0, do_dtb_ops, "", ""),
- U_BOOT_CMD_MKENT(key, 5, 0, do_key_ops, "", ""),
- U_BOOT_CMD_MKENT(bbt, 5, 0, do_bbt_ops, "", ""),
-};
-
-static int do_amlmtd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
-{
- cmd_tbl_t *c;
- char subcmd[4];
-
- if (argc < 2) return CMD_RET_USAGE;
- /* process subcmd which is longger than 3 characaters */
- c = find_cmd_tbl(argv[1], cmd_amlmtd_sub, ARRAY_SIZE(cmd_amlmtd_sub));
- if (!c) {
- strncpy(subcmd, argv[1], 3);
- if (strlen(argv[1]) > 3) {
- subcmd[3] = 0;
- }
- printk("sub cmd %s\n", subcmd);
- c = find_cmd_tbl(subcmd, cmd_amlmtd_sub, ARRAY_SIZE(cmd_amlmtd_sub));
- if (c) {
- printf("new argv[1] %s\n", argv[1]);
- return c->cmd(cmdtp, flag, argc, argv);
- }
- } else {
- return c->cmd(cmdtp, flag, argc, argv);
- }
-
- return CMD_RET_USAGE;
-}
-
-
-#ifdef CONFIG_SYS_LONGHELP
-static char amlmtd_help_text[] =
-#ifndef CONFIG_DISCRETE_BOOTLOADER
- "amlnf rom_read addr off size - read uboot by offset.\n"
- "amlnf rom_write addr off size - write all uboot at once.\n"
- "amlnf rom_erase - erase whole boot area\n"
-#else
-#if 0 /* hide for interal usage */
- "amlnf rom_erase [cpy] - erase bl2 area, erase all without cpy!\n"
- "amlnf rom_read addr off size - read bl2 by offset.\n"
- "amlnf rom_write addr [off] size - write bl2.\n"
- "\t[off] inside offset\n\twirte all copies if without off\n"
-#endif
- "amlnf bl2_info - show bl2 infos\n"
- "amlnf bl2_erase [cpy] - erase bl2 area, erase all without cpy!\n"
- "amlnf bl2_read addr cpy size - read bl2 by cpy.\n"
- "amlnf bl2_write addr [cpy] size - write bl2.\n"
- "\t[cpy] copy to operate\n\twirte all copies if without cpy\n"
- "amlnf fip_info - show fip infos\n"
- "amlnf fip_read addr off size - read fip.\n"
- "amlnf fip_write addr [off] size - write fip.\n"
- "\t[off] inside offset\n\twirte all copies if without off\n"
- "amlnf fip_erase [cpy] - erase fip area, erase all without cpy!\n"
-#endif
- "amlnf dtb_read/write addr size - read/write dtd.\n"
- "amlnf dtb_erase - erase dtb area!\n"
- "amlnf key_read/write addr size - read/write keys.\n"
- "amlnf key_erase - erase keys!\n"
- "";
-#endif
-U_BOOT_CMD(
- amlnf, CONFIG_SYS_MAXARGS, 0, do_amlmtd,
- "aml mtd nand sub-system",
- amlmtd_help_text
-);
diff --git a/drivers/mtd/nand/aml_nand/meson_nand.c b/drivers/mtd/nand/aml_nand/meson_nand.c
deleted file mode 100644
index c4ced02..0000000
--- a/drivers/mtd/nand/aml_nand/meson_nand.c
+++ /dev/null
@@ -1,1011 +0,0 @@
-#include <common.h>
-#include <dm.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <linux/err.h>
-#include <asm/cache.h>
-//#include <asm/arch/secure_apb.h>
-#include <asm/arch-g12a/cpu_id.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <linux/mtd/nand_ecc.h>
-#include <dm/device-internal.h>
-#include <dm/uclass-internal.h>
-#include <dm/root.h>
-#include <dm/lists.h>
-#include <dm/util.h>
-
-#include <fdtdec.h>
-#include <memalign.h>
-#include <linux/io.h>
-#include <asm/gpio.h>
-#include <asm/arch/clock.h>
-#include <dt-bindings/clock/g12-clkc.h>
-#include <clk.h>
-#include <dm/pinctrl.h>
-
-#include "aml_nand.h"
-#include "version.h"
-#include <time.h>
-
-struct hw_controller *controller = NULL;
-
-extern struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
-extern void mtd_store_set(struct mtd_info *mtd, int dev);
-
-
-
-#ifdef CONFIG_MTD_DEVICE
-static __attribute__((unused)) char dev_name[CONFIG_SYS_MAX_NAND_DEVICE][8];
-#endif
-
-
-static struct aml_nand_platform aml_nand_mid_platform[] = {
- {
- .name = NAND_BOOT_NAME,
- .chip_enable_pad = AML_NAND_CE0,
- .ready_busy_pad = AML_NAND_CE0,
- .platform_nand_data = {
- .chip = {
- .nr_chips = 1,
- .options = (NAND_TIMING_MODE5 | NAND_ECC_BCH60_1K_MODE),
- },
- },
- .rbpin_mode=1,
- .short_pgsz=384,
- .ran_mode=0,
- .T_REA = 20,
- .T_RHOH = 15,
- },
- {
- .name = NAND_NORMAL_NAME,
- .chip_enable_pad = (AML_NAND_CE0) | (AML_NAND_CE1 << 4),
- .ready_busy_pad = (AML_NAND_CE0) | (AML_NAND_CE1 << 4),
- .platform_nand_data = {
- .chip = {
- .nr_chips = 1,
- /* moved to board config as different board
- * may have different partition table
- */
- /* .nr_partitions = ARRAY_SIZE(normal_partition_info),
- .partitions = normal_partition_info,*/
- .options = (NAND_TIMING_MODE5
- | NAND_ECC_BCH60_1K_MODE
- | NAND_TWO_PLANE_MODE),
- },
- },
- .rbpin_mode = 1,
- .short_pgsz = 0,
- .ran_mode = 0,
- .T_REA = 20,
- .T_RHOH = 15,
- }
-};
-
-struct aml_nand_device aml_nand_mid_device = {
- .aml_nand_platform = aml_nand_mid_platform,
- .dev_num = ARRAY_SIZE(aml_nand_mid_platform),
-};
-
-#define ECC_INFORMATION(name_a, bch_a, size_a, parity_a, user_a) \
- {\
- .name=name_a,\
- .bch_mode=bch_a,\
- .bch_unit_size=size_a,\
- .bch_bytes=parity_a,\
- .user_byte_mode=user_a\
- }
-
-static struct aml_nand_bch_desc m3_bch_list[] = {
- [0] = ECC_INFORMATION("NAND_RAW_MODE",
- NAND_ECC_SOFT_MODE,
- 0,
- 0,
- 0),
- [1] = ECC_INFORMATION("NAND_BCH8_MODE",
- NAND_ECC_BCH8_MODE,
- NAND_ECC_UNIT_SIZE,
- NAND_BCH8_ECC_SIZE,
- 2),
- [2] = ECC_INFORMATION("NAND_BCH8_1K_MODE" ,
- NAND_ECC_BCH8_1K_MODE,
- NAND_ECC_UNIT_1KSIZE,
- NAND_BCH8_1K_ECC_SIZE,
- 2),
- [3] = ECC_INFORMATION("NAND_BCH24_1K_MODE" ,
- NAND_ECC_BCH24_1K_MODE,
- NAND_ECC_UNIT_1KSIZE,
- NAND_BCH24_1K_ECC_SIZE,
- 2),
- [4] = ECC_INFORMATION("NAND_BCH30_1K_MODE" ,
- NAND_ECC_BCH30_1K_MODE,
- NAND_ECC_UNIT_1KSIZE,
- NAND_BCH30_1K_ECC_SIZE,
- 2),
- [5] = ECC_INFORMATION("NAND_BCH40_1K_MODE" ,
- NAND_ECC_BCH40_1K_MODE,
- NAND_ECC_UNIT_1KSIZE,
- NAND_BCH40_1K_ECC_SIZE,
- 2),
- [6] = ECC_INFORMATION("NAND_BCH50_1K_MODE" ,
- NAND_ECC_BCH50_1K_MODE,
- NAND_ECC_UNIT_1KSIZE,
- NAND_BCH50_1K_ECC_SIZE,
- 2),
- [7] = ECC_INFORMATION("NAND_BCH60_1K_MODE" ,
- NAND_ECC_BCH60_1K_MODE,
- NAND_ECC_UNIT_1KSIZE,
- NAND_BCH60_1K_ECC_SIZE,
- 2),
- [8] = ECC_INFORMATION("NAND_SHORT_MODE" ,
- NAND_ECC_SHORT_MODE,
- NAND_ECC_UNIT_SHORT,
- NAND_BCH60_1K_ECC_SIZE,
- 2),
-};
-
-extern uint8_t nand_boot_flag;
-
-unsigned char pagelist_hynix256[128] = {
- 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x0A, 0x0B,
- 0x0E, 0x0F, 0x12, 0x13, 0x16, 0x17, 0x1A, 0x1B,
- 0x1E, 0x1F, 0x22, 0x23, 0x26, 0x27, 0x2A, 0x2B,
- 0x2E, 0x2F, 0x32, 0x33, 0x36, 0x37, 0x3A, 0x3B,
-
- 0x3E, 0x3F, 0x42, 0x43, 0x46, 0x47, 0x4A, 0x4B,
- 0x4E, 0x4F, 0x52, 0x53, 0x56, 0x57, 0x5A, 0x5B,
- 0x5E, 0x5F, 0x62, 0x63, 0x66, 0x67, 0x6A, 0x6B,
- 0x6E, 0x6F, 0x72, 0x73, 0x76, 0x77, 0x7A, 0x7B,
-
- 0x7E, 0x7F, 0x82, 0x83, 0x86, 0x87, 0x8A, 0x8B,
- 0x8E, 0x8F, 0x92, 0x93, 0x96, 0x97, 0x9A, 0x9B,
- 0x9E, 0x9F, 0xA2, 0xA3, 0xA6, 0xA7, 0xAA, 0xAB,
- 0xAE, 0xAF, 0xB2, 0xB3, 0xB6, 0xB7, 0xBA, 0xBB,
-
- 0xBE, 0xBF, 0xC2, 0xC3, 0xC6, 0xC7, 0xCA, 0xCB,
- 0xCE, 0xCF, 0xD2, 0xD3, 0xD6, 0xD7, 0xDA, 0xDB,
- 0xDE, 0xDF, 0xE2, 0xE3, 0xE6, 0xE7, 0xEA, 0xEB,
- 0xEE, 0xEF, 0xF2, 0xF3, 0xF6, 0xF7, 0xFA, 0xFB,
-};
-unsigned char pagelist_1ynm_hynix256_mtd[128] = {
- 0x00, 0x01, 0x03, 0x05, 0x07, 0x09, 0x0b, 0x0d,
- 0x0f, 0x11, 0x13, 0x15, 0x17, 0x19, 0x1b, 0x1d,
- 0x1f, 0x21, 0x23, 0x25, 0x27, 0x29, 0x2b, 0x2d,
- 0x2f, 0x31, 0x33, 0x35, 0x37, 0x39, 0x3b, 0x3d,
- 0x3f, 0x41, 0x43, 0x45, 0x47, 0x49, 0x4b, 0x4d,
- 0x4f, 0x51, 0x53, 0x55, 0x57, 0x59, 0x5b, 0x5d,
- 0x5f, 0x61, 0x63, 0x65, 0x67, 0x69, 0x6b, 0x6d,
- 0x6f, 0x71, 0x73, 0x75, 0x77, 0x79, 0x7b, 0x7d,
- 0x7f, 0x81, 0x83, 0x85, 0x87, 0x89, 0x8b, 0x8d,
- 0x8f, 0x91, 0x93, 0x95, 0x97, 0x99, 0x9b, 0x9d,
- 0x9f, 0xa1, 0xA3, 0xA5, 0xA7, 0xA9, 0xAb, 0xAd,
- 0xAf, 0xb1, 0xB3, 0xB5, 0xB7, 0xB9, 0xBb, 0xBd,
- 0xBf, 0xc1, 0xC3, 0xC5, 0xC7, 0xC9, 0xCb, 0xCd,
- 0xCf, 0xd1, 0xD3, 0xD5, 0xD7, 0xD9, 0xDb, 0xDd,
- 0xDf, 0xe1, 0xE3, 0xE5, 0xE7, 0xE9, 0xEb, 0xEd,
- 0xEf, 0xf1, 0xF3, 0xF5, 0xF7, 0xF9, 0xFb, 0xFd,
-};
-
-static int controller_select_chip(struct hw_controller *controller,
- u8 chipnr)
-{
- int ret = 0;
-
- switch (chipnr) {
- case 0:
- case 1:
- case 2:
- case 3:
- controller->chip_selected = controller->ce_enable[chipnr];
- controller->rb_received = controller->rb_enable[chipnr];
-
- NFC_SEND_CMD_IDLE(controller, 0);
- break;
- default:
- BUG();
- ret = -12;
- break;
- }
-
- return ret;
-}
-
-static void m3_nand_select_chip(struct aml_nand_chip *aml_chip, int chipnr)
-{
- controller_select_chip(controller, chipnr);
- return;
-}
-
-void aml_nfc_get_clk_name(struct hw_controller *controller)
-{
- static struct udevice *clk_udevice;
- unsigned int rate;
-
- uclass_get_device_by_name(UCLASS_CLK, "amlogic,g12a-clkc", &clk_udevice);
- clk_get_by_name(controller->device, "clkin", &controller->clk[0]);
- rate = clk_get_rate(&controller->clk[0]);
- printf("____fclk rate0: %d\n", rate);
- clk_get_by_name(controller->device, "clkin1", &controller->clk[1]);
- clk_get_by_name(controller->device, "clkin2", &controller->clk[2]);
- clk_get_by_name(controller->device, "clkin3", &controller->clk[3]);
-}
-
-void get_sys_clk_rate_mtd(struct hw_controller *controller, int *rate)
-{
- unsigned int clk;
-#if 0 /**Clock source come from Fix PLL***/
- int clk_freq = *rate;
- cpu_id_t cpu_id = get_cpu_id();
- unsigned int always_on = 0x1 << 24;
- /* fixme, axg clock may be the same setting with gxl/gxm */
- if ((cpu_id.family_id == MESON_CPU_MAJOR_ID_AXG) ||
- (cpu_id.family_id == MESON_CPU_MAJOR_ID_TXHD) ||
- (cpu_id.family_id >= MESON_CPU_MAJOR_ID_G12A))
- always_on = 0x1 << 28;
-
- printk("%s() %d, clock setting %d!\n",
- __func__, __LINE__, clk_freq);
-
- if ((cpu_id.family_id == MESON_CPU_MAJOR_ID_GXBB) ||
- (cpu_id.family_id == MESON_CPU_MAJOR_ID_GXL) ||
- (cpu_id.family_id == MESON_CPU_MAJOR_ID_AXG) ||
- (cpu_id.family_id == MESON_CPU_MAJOR_ID_TXHD) ||
- (cpu_id.family_id >= MESON_CPU_MAJOR_ID_G12A)) {
-
- switch (clk_freq) {
- case 24:
- clk = 0x80000201;
- break;
- case 112:
- clk = 0x80000249;
- break;
- case 200:
- clk = 0x80000245;
- break;
- case 250:
- clk = 0x80000244;
- break;
- default:
- clk = 0x80000245;
- break;
- }
- clk |= always_on;
- amlnf_write_reg32(controller->nand_clk_reg, clk);
- return;
- } else {
- BUG();
- }
-#else /**Clock source come from HHI_NAND_CLK_CNTL***/
- clk = 0x80000201;
- amlnf_write_reg32(controller->nand_clk_reg, clk);
- return;
-#endif
-
- return;
-}
-
-
-static void m3_nand_hw_init(struct aml_nand_chip *aml_chip)
-{
- int bus_cycle, bus_timing;
- int sys_clk_rate = 200;
-
- clk_set_parent(&controller->clk[1], &controller->clk[0]);
- clk_set_rate(&controller->clk[2], sys_clk_rate*1000000);
- clk_enable(&controller->clk[3]);
- get_sys_clk_rate_mtd(controller, &sys_clk_rate);
-
-
- bus_cycle = 6;
- bus_timing = bus_cycle + 1;
-
- NFC_SET_CFG(controller, 0);
- NFC_SET_TIMING_ASYC(controller, bus_timing, (bus_cycle - 1));
- NFC_SEND_CMD(controller, 1<<31);
-
- return;
-}
-
-static void m3_nand_adjust_timing(struct aml_nand_chip *aml_chip)
-{
- int sys_clk_rate, bus_cycle, bus_timing;
- //clock_t start, finish, duration;
-
- //start = timer_get_us();
- if (!aml_chip->T_REA)
- aml_chip->T_REA = 20;
- if (!aml_chip->T_RHOH)
- aml_chip->T_RHOH = 15;
-
- if (aml_chip->T_REA > 30)
- sys_clk_rate = 112;
- else if (aml_chip->T_REA > 16)
- sys_clk_rate = 200;
- else
- sys_clk_rate = 250;
-
- clk_set_parent(&controller->clk[1], &controller->clk[0]);
- clk_set_rate(&controller->clk[2], sys_clk_rate*1000000);
- clk_enable(&controller->clk[3]);
- get_sys_clk_rate_mtd(controller, &sys_clk_rate);
-
- bus_cycle = 6;
- bus_timing = bus_cycle + 1;
- /*printf("%s() sys_clk_rate %d, bus_c %d, bus_t %d\n",
- __func__, sys_clk_rate, bus_cycle, bus_timing);*/
- NFC_SET_CFG(controller , 0);
- NFC_SET_TIMING_ASYC(controller, bus_timing, (bus_cycle - 1));
-
- NFC_SEND_CMD(controller, 1<<31);
-
- //finish = timer_get_us();
- //duration = finish - start;
- //printf("___time111: %ld\n", duration);
-}
-
-static int m3_nand_options_confirm(struct aml_nand_chip *aml_chip)
-{
- struct nand_chip *chip = &aml_chip->chip;
- struct mtd_info *mtd = &chip->mtd;
- struct aml_nand_platform *plat = aml_chip->platform;
- struct aml_nand_bch_desc *ecc_supports = aml_chip->bch_desc;
- unsigned int max_bch_mode = aml_chip->max_bch_mode;
- unsigned int options_selected = 0, options_support = 0, options_define;
- unsigned int eep_need_oobsize = 0, ecc_page_num = 0, ecc_bytes;
- int error = 0, i, valid_chip_num = 0;
- cpu_id_t cpu_id = get_cpu_id();
-
- /****bootloader only support short mode
- **ecc_supports[8] is short mode ecc
- ***/
- if (!strncmp((char*)plat->name,
- NAND_BOOT_NAME,
- strlen((const char*)NAND_BOOT_NAME))) {
- eep_need_oobsize =
- ecc_supports[8].bch_bytes + ecc_supports[8].user_byte_mode;
- ecc_page_num =
- aml_chip->page_size / ecc_supports[8].bch_unit_size;
- aml_chip->boot_oob_fill_cnt = aml_chip->oob_size -
- eep_need_oobsize * ecc_page_num;
- }
-
- /*select fit ecc mode by flash oob size */
- for (i = max_bch_mode - 1; i > 0; i--) {
- eep_need_oobsize =
- ecc_supports[i].bch_bytes + ecc_supports[i].user_byte_mode;
- ecc_page_num =
- aml_chip->page_size / ecc_supports[i].bch_unit_size;
- ecc_bytes = aml_chip->oob_size / ecc_page_num;
- if (ecc_bytes >= eep_need_oobsize) {
- options_support = ecc_supports[i].bch_mode;
- break;
- }
- }
- /**aml_chip->oob_size equal nand oobsize**/
- aml_chip->oob_fill_cnt =
- aml_chip->oob_size - eep_need_oobsize * ecc_page_num;
- printk("oob_fill_cnt =%d oob_size =%d, bch_bytes =%d\n",
- aml_chip->oob_fill_cnt,
- aml_chip->oob_size,
- ecc_supports[i].bch_bytes);
- printk("ecc mode:%d ecc_page_num=%d eep_need_oobsize=%d\n",
- options_support, ecc_page_num, eep_need_oobsize);
-
- printk("options_support :%d\n", options_support);
- if (options_support != NAND_ECC_SOFT_MODE) {
- chip->ecc.read_page_raw = aml_nand_read_page_raw;
- chip->ecc.write_page_raw = aml_nand_write_page_raw;
- chip->ecc.read_page = aml_nand_read_page_hwecc;
- chip->ecc.write_page = aml_nand_write_page_hwecc;
- chip->ecc.read_oob = aml_nand_read_oob;
- chip->ecc.write_oob = aml_nand_write_oob;
- chip->block_bad = aml_nand_block_bad;
- chip->block_markbad = aml_nand_block_markbad;
- chip->ecc.mode = NAND_ECC_HW;
- } else {
- chip->ecc.read_page_raw = aml_nand_read_page_raw;
- chip->ecc.write_page_raw = aml_nand_write_page_raw;
- chip->ecc.mode = NAND_ECC_SOFT;
- }
- chip->write_buf = aml_nand_dma_write_buf;
- chip->read_buf = aml_nand_dma_read_buf;
-
- if ((mtd->writesize <= 2048) ||
- (cpu_id.family_id == MESON_CPU_MAJOR_ID_AXG) ||
- (cpu_id.family_id == MESON_CPU_MAJOR_ID_TXHD))
- options_support = NAND_ECC_BCH8_MODE;
-
- switch (options_support) {
-
- case NAND_ECC_BCH8_MODE:
- chip->ecc.strength = 8;
- chip->ecc.size = NAND_ECC_UNIT_SIZE;
- chip->ecc.bytes = NAND_BCH8_ECC_SIZE;
- aml_chip->bch_mode = NAND_ECC_BCH8;
- aml_chip->user_byte_mode = 2;
- aml_chip->ecc_cnt_limit = 6;
- aml_chip->ecc_max = 8;
- chip->ecc.steps = mtd->writesize / chip->ecc.size;
- break;
-
- case NAND_ECC_BCH8_1K_MODE:
- chip->ecc.strength = 8;
- chip->ecc.size = NAND_ECC_UNIT_1KSIZE;
- chip->ecc.bytes = NAND_BCH8_1K_ECC_SIZE;
- aml_chip->bch_mode = NAND_ECC_BCH8_1K;
- aml_chip->user_byte_mode = 2;
- aml_chip->ecc_cnt_limit = 6;
- aml_chip->ecc_max = 8;
- chip->ecc.steps = mtd->writesize / chip->ecc.size;
- break;
-
- case NAND_ECC_BCH24_1K_MODE:
- chip->ecc.strength = 24;
- chip->ecc.size = NAND_ECC_UNIT_1KSIZE;
- chip->ecc.bytes = NAND_BCH24_1K_ECC_SIZE;
- aml_chip->bch_mode = NAND_ECC_BCH24_1K;
- aml_chip->user_byte_mode = 2;
- aml_chip->ecc_cnt_limit = 22;
- aml_chip->ecc_max = 24;
- chip->ecc.steps = mtd->writesize / chip->ecc.size;
- break;
-
- case NAND_ECC_BCH30_1K_MODE:
- chip->ecc.strength = 30;
- chip->ecc.size = NAND_ECC_UNIT_1KSIZE;
- chip->ecc.bytes = NAND_BCH30_1K_ECC_SIZE;
- aml_chip->bch_mode = NAND_ECC_BCH30_1K;
- aml_chip->user_byte_mode = 2;
- aml_chip->ecc_cnt_limit = 26;
- aml_chip->ecc_max = 30;
- chip->ecc.steps = mtd->writesize / chip->ecc.size;
- break;
-
- case NAND_ECC_BCH40_1K_MODE:
- chip->ecc.strength = 40;
- chip->ecc.size = NAND_ECC_UNIT_1KSIZE;
- chip->ecc.bytes = NAND_BCH40_1K_ECC_SIZE;
- aml_chip->bch_mode = NAND_ECC_BCH40_1K;
- aml_chip->user_byte_mode = 2;
- aml_chip->ecc_cnt_limit = 34;
- aml_chip->ecc_max = 40;
- chip->ecc.steps = mtd->writesize / chip->ecc.size;
- break;
-
- case NAND_ECC_BCH50_1K_MODE:
- chip->ecc.strength = 40;
- chip->ecc.size = NAND_ECC_UNIT_1KSIZE;
- chip->ecc.bytes = NAND_BCH50_1K_ECC_SIZE;
- aml_chip->bch_mode = NAND_ECC_BCH50_1K;
- aml_chip->user_byte_mode = 2;
- aml_chip->ecc_cnt_limit = 45;
- aml_chip->ecc_max = 50;
- chip->ecc.steps = mtd->writesize / chip->ecc.size;
- break;
-
- case NAND_ECC_BCH60_1K_MODE:
- chip->ecc.strength = 60;
- chip->ecc.size = NAND_ECC_UNIT_1KSIZE;
- chip->ecc.bytes = NAND_BCH60_1K_ECC_SIZE;
- aml_chip->bch_mode = NAND_ECC_BCH60_1K;
- aml_chip->user_byte_mode = 2;
- aml_chip->ecc_cnt_limit = 55;
- aml_chip->ecc_max = 60;
- chip->ecc.steps = mtd->writesize / chip->ecc.size;
- break;
-
- case NAND_ECC_SHORT_MODE:
- chip->ecc.strength = 60;
- chip->ecc.size = NAND_ECC_UNIT_SHORT;
- chip->ecc.bytes = NAND_BCH60_1K_ECC_SIZE;
- aml_chip->bch_mode = NAND_ECC_BCH_SHORT;
- aml_chip->user_byte_mode = 2;
- aml_chip->ecc_cnt_limit = 55;
- aml_chip->ecc_max = 60;
- chip->ecc.steps = mtd->writesize / 512;
- break;
- /*not support for amlogic chip*/
- case NAND_ECC_SOFT_MODE:
- aml_chip->user_byte_mode = 1;
- aml_chip->bch_mode = 0;
- /*don't care*/
- aml_chip->ecc_cnt_limit = 9;
- aml_chip->ecc_max = 16;
- break;
- default :
- printk("unknow ecc mode, error!");
- error = -ENXIO;
- break;
- }
-
- options_selected =
- plat->platform_nand_data.chip.options & NAND_INTERLEAVING_OPTIONS_MASK;
- options_define = (aml_chip->options & NAND_INTERLEAVING_OPTIONS_MASK);
- if (options_selected > options_define) {
- printk("INTERLEAV change! \n");
- options_selected = options_define;
- }
- switch (options_selected) {
- case NAND_INTERLEAVING_MODE:
- aml_chip->ops_mode |= AML_INTERLEAVING_MODE;
- mtd->erasesize *= aml_chip->internal_chipnr;
- mtd->writesize *= aml_chip->internal_chipnr;
- mtd->oobsize *= aml_chip->internal_chipnr;
- break;
- default:
- break;
- }
-
- options_selected =
- plat->platform_nand_data.chip.options & NAND_PLANE_OPTIONS_MASK;
- options_define = (aml_chip->options & NAND_PLANE_OPTIONS_MASK);
- printf("options_selected: 0x%x, options_define:0x%x\n",options_selected,
- options_define);
- if (options_selected > options_define) {
- printk("PLANE change!\n");
- options_selected = options_define;
- }
-
- valid_chip_num = 0;
- for (i=0; i < controller->chip_num; i++)
- if (aml_chip->valid_chip[i])
- valid_chip_num++;
- if (aml_chip->ops_mode & AML_INTERLEAVING_MODE)
- valid_chip_num *= aml_chip->internal_chipnr;
-
- if (valid_chip_num > 2) {
- aml_chip->plane_num = 1;
- printk("detect valid_chip_num over 2\n");
- } else {
- switch (options_selected) {
- case NAND_TWO_PLANE_MODE:
- aml_chip->plane_num = 2;
- mtd->erasesize *= 2;
- mtd->writesize *= 2;
- mtd->oobsize *= 2;
- printk("two plane!@\n");
- break;
- default:
- aml_chip->plane_num = 1;
- break;
- }
- }
-
- printk("plane_num=%d writesize=0x%x ecc.size=0x%0x bch_mode=%d\n",
- aml_chip->plane_num,
- mtd->writesize,
- chip->ecc.size,
- aml_chip->bch_mode);
-
- return error;
-}
-
-
-static int aml_platform_dma_waiting(struct aml_nand_chip *aml_chip)
-{
- unsigned time_out_cnt = 0;
-
- NFC_SEND_CMD_IDLE(controller, 0);
- NFC_SEND_CMD_IDLE(controller, 0);
- do {
- if (NFC_CMDFIFO_SIZE(controller) <= 0)
- break;
- }while (time_out_cnt++ <= AML_DMA_BUSY_TIMEOUT);
-
- if (time_out_cnt < AML_DMA_BUSY_TIMEOUT)
- return 0;
-
- return -EBUSY;
-}
-
-static int m3_nand_dma_write(struct aml_nand_chip *aml_chip,
- unsigned char *buf, int len, unsigned bch_mode)
-{
- int ret = 0;
- unsigned dma_unit_size = 0, count = 0;
- struct nand_chip *chip = &aml_chip->chip;
- struct mtd_info *mtd = &chip->mtd;
- uint32_t temp;
-
- if (bch_mode == NAND_ECC_NONE)
- count = 1;
- else if (bch_mode == NAND_ECC_BCH_SHORT) {
- dma_unit_size = (chip->ecc.size >> 3);
- /*caculate ecc pages cnt*/
- count = len/chip->ecc.size;
- }
- else
- count = len/chip->ecc.size;
-
- flush_dcache_range((unsigned long)buf, (unsigned long)buf + len);
- flush_dcache_range((unsigned long)aml_chip->user_info_buf,
- (unsigned long)aml_chip->user_info_buf + count*PER_INFO_BYTE);
-
- NFC_SEND_CMD_ADL(controller, (u32)(unsigned long)buf);
- NFC_SEND_CMD_ADH(controller, (u32)(unsigned long)buf);
- NFC_SEND_CMD_AIL(controller, (u32)(unsigned long)aml_chip->user_info_buf);
- NFC_SEND_CMD_AIH(controller, (u32)(unsigned long)aml_chip->user_info_buf);
-
- if (aml_chip->ran_mode) {
- temp = mtd->writesize>>chip->page_shift;
- if (aml_chip->plane_num == 2)
- NFC_SEND_CMD_SEED(controller,
- (aml_chip->page_addr / temp) * temp);
- else
- NFC_SEND_CMD_SEED(controller, aml_chip->page_addr);
- }
- if (!bch_mode)
- NFC_SEND_CMD_M2N_RAW(controller, 0, len);
- else
- NFC_SEND_CMD_M2N(controller, aml_chip->ran_mode,
- ((bch_mode == NAND_ECC_BCH_SHORT)?aml_chip->bch_info:bch_mode),
- ((bch_mode == NAND_ECC_BCH_SHORT)?1:0), dma_unit_size, count);
-
- ret = aml_platform_dma_waiting(aml_chip);
-
- if (aml_chip->oob_fill_cnt >0) {
- NFC_SEND_CMD_M2N_RAW(controller,
- aml_chip->ran_mode, aml_chip->oob_fill_cnt);
- ret = aml_platform_dma_waiting(aml_chip);
- }
- return ret;
-}
-
-static int m3_nand_dma_read(struct aml_nand_chip *aml_chip,
- unsigned char *buf, int len, unsigned bch_mode)
-{
- volatile unsigned int * info_buf=0;
- volatile int cmp=0;
-
- struct nand_chip *chip = &aml_chip->chip;
- unsigned dma_unit_size = 0, count = 0, info_times_int_len;
- int ret = 0;
- struct mtd_info *mtd = &chip->mtd;
- uint32_t temp;
-
- info_times_int_len = PER_INFO_BYTE/sizeof(unsigned int);
- if (bch_mode == NAND_ECC_NONE)
- count = 1;
- else if (bch_mode == NAND_ECC_BCH_SHORT) {
- dma_unit_size = (chip->ecc.size >> 3);
- count = len/chip->ecc.size;
- } else
- count = chip->ecc.steps;
- /*printk("___count: %d, bch_mod:%d",count,bch_mode);*/
- memset((unsigned char *)aml_chip->user_info_buf,
- 0, count*PER_INFO_BYTE);
- flush_dcache_range((unsigned long)aml_chip->user_info_buf,
- (unsigned long)aml_chip->user_info_buf + count*PER_INFO_BYTE);
- invalidate_dcache_range((unsigned long)buf, (unsigned long)buf + len);
-
- NFC_SEND_CMD_ADL(controller, (u32)(unsigned long)buf);
- NFC_SEND_CMD_ADH(controller, (u32)(unsigned long)buf);
- NFC_SEND_CMD_AIL(controller,
- (u32)(unsigned long)aml_chip->user_info_buf);
- NFC_SEND_CMD_AIH(controller,
- (u32)(unsigned long)aml_chip->user_info_buf);
- if (aml_chip->ran_mode) {
- temp = mtd->writesize >> chip->page_shift;
- if (aml_chip->plane_num == 2)
- NFC_SEND_CMD_SEED(controller,
- (aml_chip->page_addr / temp) * temp);
- else
- NFC_SEND_CMD_SEED(controller,
- aml_chip->page_addr);
- }
-
- if (bch_mode == NAND_ECC_NONE)
- NFC_SEND_CMD_N2M_RAW(controller, 0, len);
- else
- NFC_SEND_CMD_N2M(controller, aml_chip->ran_mode,
- ((bch_mode == NAND_ECC_BCH_SHORT)?aml_chip->bch_info:bch_mode),
- ((bch_mode == NAND_ECC_BCH_SHORT)?1:0), dma_unit_size, count);
-
- ret = aml_platform_dma_waiting(aml_chip);
- if (ret)
- return ret;
- do {
- invalidate_dcache_range((unsigned long)aml_chip->user_info_buf,
- (unsigned long)aml_chip->user_info_buf + count*PER_INFO_BYTE);
- info_buf =
-(volatile unsigned *)&(aml_chip->user_info_buf[(count-1)*info_times_int_len]);
- cmp = *info_buf;
- } while((cmp)==0);/*judge DMA read over*/
-
- return 0;
-}
-
-static int m3_nand_hwecc_correct(struct aml_nand_chip *aml_chip,
- unsigned char *buf, unsigned size, unsigned char *oob_buf)
-{
- struct nand_chip *chip = &aml_chip->chip;
- unsigned ecc_step_num, usr_info, tmp_value;
- unsigned info_times_int_len = PER_INFO_BYTE / sizeof(unsigned int);
-
- if (size % chip->ecc.size) {
- printk ("error parameter size for ecc correct %x\n", size);
- return -EINVAL;
- }
-
- for (ecc_step_num = 0;
- ecc_step_num < (size / chip->ecc.size); ecc_step_num++) {
- /* check if there have uncorrectable sector */
- tmp_value = ecc_step_num * info_times_int_len;
- usr_info = *(unsigned *)(&aml_chip->user_info_buf[tmp_value]);
- if (NAND_ECC_CNT(usr_info) == 0x3f) {
- aml_chip->zero_cnt = NAND_ZERO_CNT(usr_info);
- return -EIO;
-
- } else
- aml_chip->ecc_cnt_cur =
- NAND_ECC_CNT(usr_info);
- }
-
- return 0;
-}
-
-static int m3_nand_probe(struct aml_nand_platform *plat, unsigned dev_num)
-{
- struct aml_nand_chip *aml_chip = NULL;
- struct nand_chip *chip = NULL;
- struct mtd_info *mtd = NULL;
- int err = 0, i, array_length;
- struct nand_oobfree *oobfree;
-
- if (!plat) {
- printk("no platform specific information\n");
- goto exit_error;
- }
-
- aml_chip = kzalloc(sizeof(*aml_chip), GFP_KERNEL);
- if (aml_chip == NULL) {
- printk("no memory for flash info\n");
- err = -ENOMEM;
- goto exit_error;
- }
-
- plat->nand_flash_dev = kzalloc(sizeof(struct aml_nand_flash_dev), GFP_KERNEL);
- if (plat->nand_flash_dev == NULL) {
- printk("no memory for plat->nand_flash_dev\n");
- err = -ENOMEM;
- goto exit_error;
- }
-
- /* initialize mtd info data struct */
- aml_chip->controller = controller;
- aml_chip->platform = plat;
- aml_chip->bch_desc = m3_bch_list;
- aml_chip->max_bch_mode = sizeof(m3_bch_list) / sizeof(m3_bch_list[0]);
-
- chip = &aml_chip->chip;
- chip->priv = aml_chip; //chip->priv = &aml_chip->mtd;
- mtd = &chip->mtd;
- mtd->priv = chip;
- plat->aml_chip = aml_chip;
- mtd->name = plat->name;
-
- /*register amlogic hw controller functions*/
- aml_chip->aml_nand_hw_init = m3_nand_hw_init;
- aml_chip->aml_nand_adjust_timing = m3_nand_adjust_timing;
- aml_chip->aml_nand_select_chip = m3_nand_select_chip;
- aml_chip->aml_nand_options_confirm = m3_nand_options_confirm;
- aml_chip->aml_nand_dma_read = m3_nand_dma_read;
- aml_chip->aml_nand_dma_write = m3_nand_dma_write;
- aml_chip->aml_nand_hwecc_correct = m3_nand_hwecc_correct;
- aml_chip->aml_nand_cmd_ctrl = aml_platform_cmd_ctrl;
- aml_chip->aml_nand_write_byte = aml_platform_write_byte;
- aml_chip->aml_nand_wait_devready = aml_platform_wait_devready;
- aml_chip->aml_nand_get_user_byte = aml_platform_get_user_byte;
- aml_chip->aml_nand_set_user_byte = aml_platform_set_user_byte;
- aml_chip->aml_nand_command = aml_nand_base_command;
- aml_chip->aml_nand_block_bad_scrub =
- aml_nand_block_bad_scrub_update_bbt;
-
- aml_chip->ran_mode = plat->ran_mode;
- aml_chip->rbpin_detect = plat->rbpin_detect;
- aml_nfc_get_clk_name(controller);
- err = aml_nand_init(aml_chip);
- if (err)
- goto exit_error;
-
- if (!strncmp((char*)plat->name,
- NAND_BOOT_NAME, strlen((const char*)NAND_BOOT_NAME))) {
- chip->erase = m3_nand_boot_erase_cmd;
- chip->ecc.read_page = m3_nand_boot_read_page_hwecc;
- chip->ecc.write_page = m3_nand_boot_write_page_hwecc;
- chip->write_page = m3_nand_boot_write_page;
- oobfree = chip->ecc.layout->oobfree;
- array_length = ARRAY_SIZE(chip->ecc.layout->oobfree);
- if (chip->ecc.layout)
- oobfree[0].length =
- (mtd->writesize / 512) * aml_chip->user_byte_mode;
- chip->ecc.layout->oobavail = 0;
- for (i = 0; oobfree[i].length && i < array_length; i++)
- chip->ecc.layout->oobavail += oobfree[i].length;
- mtd->oobavail = chip->ecc.layout->oobavail;
- mtd->ecclayout = chip->ecc.layout;
- }
-
- nand_info[dev_num] = mtd;
- mtd_store_set(nand_info[dev_num], dev_num);/*need fix*/
- printf("mtd name: %s\n", mtd->name);/*nand name*/
- return 0;
-
-exit_error:
- if (aml_chip)
- kfree(aml_chip);
- mtd->name = NULL;
- return err;
-}
-
-void nand_hw_init(struct aml_nand_platform *plat)
-{
- struct aml_nand_chip *aml_chip = NULL;
-
- if (!plat) {
- printf("no platform specific information\n");
- return;
- }
-
- aml_chip = plat->aml_chip;
-
- aml_chip->aml_nand_hw_init(aml_chip);
- if (aml_chip->aml_nand_adjust_timing)
- aml_chip->aml_nand_adjust_timing(aml_chip);
- aml_chip->aml_nand_select_chip(aml_chip, 0);
-}
-
-#ifdef CONFIG_AMLOGIC_DM_FLASH
-static void meson_nfc_init_dm(void)
-{
- struct udevice *dev;
-
- for (uclass_first_device(UCLASS_MTD, &dev);
- dev;
- uclass_next_device(&dev));
-}
-#endif
-
-
-/******liuxj nand init-->DM(probe)*****/
-/**fixed me after use DM***/
-void board_nand_init(void)
-{
-#ifdef CONFIG_AMLOGIC_DM_FLASH
- meson_nfc_init_dm();
-#endif
-}
-
-#ifdef CONFIG_AML_STORAGE
- extern int slcnand_fit_storage(void);
-#endif
-
-int amlmtd_init = 0;
-#ifdef CONFIG_AMLOGIC_DM_FLASH
-int meson_nfc_probe(struct udevice *dev)
-{
- struct mtd_info *mtd;
-
- struct aml_nand_platform *plat = NULL;
- const void *blob = gd->fdt_blob;
- fdt_addr_t regs, clk_regs;
- int node;
- int i, ret = 0;
-#ifdef clk_tree_test
- static struct udevice *clk_udvice;
- struct clk w_clk;
- struct clk p_clk;
- unsigned int rate;
-#endif
- printf("%s\n", __func__);
- if (1 == amlmtd_init) {
- ret = pinctrl_select_state(controller->device, "default");
- if (ret) {
- printf("select state %s failed\n", "default");
- return ret;
- }
- nand_hw_init(&aml_nand_mid_device.aml_nand_platform[0]);
- return 0;
- }
-
- mtd = dev_get_uclass_priv(dev);
- mtd->name = (char *)dev->name;
- mtd->dev = dev;
-
- controller = kzalloc(sizeof(struct hw_controller), GFP_KERNEL);
- if (controller == NULL) {
- printk("%s kzalloc controller failed\n", __func__);
- return 1;
- }
-
- controller->device = mtd->dev;
-
- controller->chip_num = 1; /* assume chip num is 1 */
- for (i = 0; i < MAX_CHIP_NUM; i++) {
- controller->ce_enable[i] =
- (((CE_PAD_DEFAULT >> i*4) & 0xf) << 10);
- controller->rb_enable[i] =
- (((RB_PAD_DEFAULT >> i*4) & 0xf) << 10);
- }
-
- controller->nand_clk_reg1 = (void *)(volatile uint32_t *)HHI_NAND_CLK_CNTL1;
-
- printk("nand clock1 register %p,value:0x%x\n",
- controller->nand_clk_reg1,
- readl(controller->nand_clk_reg1));
-
- node = fdtdec_next_compatible(blob, 0, COMPAT_MESON_NAND);
- if (node < 0) {
- printk("unable to find nfc node in device tree\n");
- return 1;
- }
-
- if (!fdtdec_get_is_enabled(blob, node)) {
- printk("nfc disabled in device tree\n");
- return 1;
-
- }
-
- regs = fdtdec_get_addr(blob, node, "reg");
- if (regs == FDT_ADDR_T_NONE) {
- printk("unabled to find nfc address in device tree\n");
- return 1;
- }
- printk("___regs :0x%llx", regs);
- controller->reg_base = (void *)regs;
- printk("nand register base =%p\n", controller->reg_base);
-#ifdef clk_tree_test
- uclass_get_device_by_name(UCLASS_CLK, "amlogic,g12a-clkc", &clk_udvice);
- clk_get_by_name(dev, "clkin", &p_clk);
- rate = clk_get_rate(&p_clk);
- printf("fclk rate: %d\n", rate);
-#endif
-
- clk_regs = fdtdec_get_addr(blob, node, "clk_reg");
- if (clk_regs == FDT_ADDR_T_NONE) {
- printk("unabled to find nfc clk address in device tree\n");
- return 1;
- }
- controller->nand_clk_reg = (void *)clk_regs;
- printk("nand clk register base =%p,value:0x%x\n", controller->nand_clk_reg,
- readl(controller->nand_clk_reg));
-
- for (i=0; i<aml_nand_mid_device.dev_num; i++) {
- plat = &aml_nand_mid_device.aml_nand_platform[i];
- if (!plat) {
- printk("error for not platform data\n");
- continue;
- }
-
- ret = m3_nand_probe(plat, i);
- if (ret)
- printk("nand init failed: %d\n", ret);
- }
-
- nand_curr_device = 1; //fixit
- amlmtd_init = 1;
- if (ret)
- free(controller);
-#ifdef CONFIG_AML_STORAGE
- else
- slcnand_fit_storage();
-#endif
-
- return 0;
-}
-
-
-static const struct udevice_id aml_nfc_ids[] = {
- { .compatible = "amlogic,meson-g12a-nfc" },
- {}
-};
-
-U_BOOT_DRIVER(meson_nfc) = {
- .name = "mesong_nfc",
- .id = UCLASS_MTD,
- .of_match = aml_nfc_ids,
- .probe = meson_nfc_probe,
-};
-#endif /* CONFIG_AMLOGIC_DM_FLASH */
-
diff --git a/drivers/mtd/nand/aml_nand/nand_flash.c b/drivers/mtd/nand/aml_nand/nand_flash.c
deleted file mode 100644
index d7f20cb..0000000
--- a/drivers/mtd/nand/aml_nand/nand_flash.c
+++ /dev/null
@@ -1,1307 +0,0 @@
-#include <common.h>
-#include <environment.h>
-#include <nand.h>
-#include <asm/io.h>
-#include <malloc.h>
-#include <linux/err.h>
-#include <asm/cache.h>
-
-//#include <asm/arch/secure_apb.h>
-#include <asm/arch-g12a/cpu_id.h>
-
-#include "aml_nand.h"
-
-extern struct hw_controller *controller;
-
-#if 0
-extern void test_timing(struct mtd_info *mtd, struct nand_chip *chip);
-#endif
-
-int nand_fbb_issue_flag;
-struct aml_nand_flash_dev aml_nand_flash_ids[] = {
- {"B revision NAND 8GiB MT29F64G08CBABA",
- {NAND_MFR_MICRON, 0x64, 0x44, 0x4B, 0xA9},
- 8192,
- 8192,
- 0x200000,
- 744,
- 1,
- 16,
- 15,
- 5,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE )},
-
- {"A revision NAND 2GiB H27UAG8T2A",
- {NAND_MFR_HYNIX, 0xd5, 0x94, 0x25, 0x44, 0x41},
- 4096,
- 2048,
- 0x80000,
- 224,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"A revision NAND 4GiB H27UBG8T2A",
- {NAND_MFR_HYNIX, 0xd7, 0x94, 0x9a, 0x74, 0x42},
- 8192,
- 4096,
- 0x200000,
- 448,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"B revision NAND 2GiB H27UAG8T2B",
- {NAND_MFR_HYNIX, 0xd5, 0x94, 0x9a, 0x74, 0x42},
- 8192,
- 2048,
- 0x200000,
- 448,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
- | NAND_TWO_PLANE_MODE)},
-
-
- {"SamSung NAND K9F4G08U0F 4Gb",
- {NAND_MFR_SAMSUNG, 0xdc, 0x10, 0x95, 0x56},
- 2048,
- 512,
- 0x20000,
- 64,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
- {"SamSung NAND k9f2g08u0d 2Gb",
- {NAND_MFR_SAMSUNG, 0xda, 0x10, 0x95, 0x46},
- 2048,
- 256,
- 0x20000,
- 64,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
- {"Dosilicon NAND FMND1GXXX3D 3.3V 1Gb",
- {NAND_MFR_DOSILICON, 0xf1, 0x80, 0x95},
- 2048,
- 128,
- 0x20000,
- 64,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
- {"Dosilicon NAND FMND1GXXX3D 1.8V 1Gb",
- {NAND_MFR_DOSILICON, 0xa1, 0x80, 0x15},
- 2048,
- 128,
- 0x20000,
- 64,
- 1,
- 30,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
- {"Dosilicon NAND FMND2GXXX3D 3.3V 2Gb",
- {NAND_MFR_DOSILICON, 0xda, 0x90, 0x95, 0x46},
- 2048,
- 256,
- 0x20000,
- 64,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
- {"Dosilicon NAND FMND2GXXX3D 1.8V 2Gb",
- {NAND_MFR_DOSILICON, 0xaa, 0x90, 0x15, 0x46},
- 2048,
- 256,
- 0x20000,
- 64,
- 1,
- 30,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
- {"ATO NAND AFND1G08U3 1Gb",
- {NAND_MFR_ATO, 0xf1, 0x00, 0x1d},
- 2048,
- 128,
- 0x20000,
- 64,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
- {"ATO NAND AFND2G08U3A 2Gb",
- {NAND_MFR_HYNIX, 0xda, 0x90, 0x95, 0x46, 0xad},
- 2048,
- 256,
- 0x20000,
- 64,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
- {"A revision NAND 1GiB sF1G-A",
- {NAND_MFR_AMD, 0xf1, 0x80, 0x1d, 0x01,0xf1},
- 2048,
- 128,
- 0x20000,
- 64,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE )},
-
- {"A revision NAND 1GiB sF1G-A",
- {NAND_MFR_AMD, 0xf1, 0x0, 0x1d, 0x01,0xf1},
- 2048,
- 128,
- 0x20000,
- 64,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
-
- {"AMD/Spansion Slc NAND 2Gib S34ML02G1(MLO2G100BH1OO)",
- {NAND_MFR_AMD, 0xda, 0x90, 0x95, 0x44, 0x01},
- 2048,
- 256,
- 0x20000,
- 64,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
-
- {"AMD/Spansion Slc NAND 2Gib S34ML02G1(MLO2G200BH1OO)",
- {NAND_MFR_AMD, 0xda, 0x90, 0x95, 0x46, 0x01},
- 2048,
- 256,
- 0x20000,
- 64,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
-
- {"AMD/Spansion Slc NAND 8Gib S34ML08G1",
- {NAND_MFR_AMD, 0xd3, 0xd1, 0x95, 0x58},
- 2048,
- 1024,
- 0x20000,
- 64,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
-
- {"A revision NAND 1Gib W29N01HV ",
- {NAND_ID_WINBOND, 0xf1, 0x00, 0x95, 0x00, 0x00},
- 2048,
- 128,
- 0x20000,
- 64,
- 1,
- 16,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
-
- {"A revision NAND 4Gib W29N04GV ",
- {NAND_ID_WINBOND, 0xdc, 0x90, 0x95, 0x54, 0x00},
- 2048,
- 512,
- 0x20000,
- 64,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
-
- {"A revision NAND 1Gib W29N01GV ",
- {NAND_ID_WINBOND, 0xf1, 0x80, 0x95, 0x00, 0x00},
- 2048,
- 128,
- 0x20000,
- 64,
- 1,
- 16,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
-
- {"A revision NAND 2Gib W29N02GV ",
- {NAND_ID_WINBOND, 0xda, 0x90, 0x95, 0x04, 0x00},
- 2048,
- 256,
- 0x20000,
- 64,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
-
- {"A revision NAND 1GiB H27U1G8F2CTR ",
- {NAND_MFR_HYNIX, 0xf1, 0x80, 0x1d, 0xad, 0xf1},
- 2048,
- 128,
- 0x20000,
- 64,
- 1,
- 16,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
-
- {"A revision NAND 4Gib EMST ",
- {NAND_ID_ESMT, 0xac, 0x90, 0x15, 0x54, 0x7f},
- 2048,
- 512,
- 0x20000,
- 64,
- 1,
- 16,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
-
- {"A revision NAND 4Gib GD9FU1G8F2AMGI",
- {NAND_ID_ESMT, 0xf1, 0x80, 0x1d, 0x42, 0xc8},
- 2048,
- 128,
- 0x20000,
- 128,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
-
- {"ESMT SLC 256MiB 3.3V 8-bit",
- {NAND_ID_ESMT, 0xda, 0x90, 0x95, 0x44, 0x7f},
- 2048,
- 256,
- 0x20000,
- 64,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
- {"ESMT SLC 128MiB 3.3V 8-bit F59L1G81Lxxx",
- {NAND_ID_ESMT, 0xd1, 0x80, 0x95, 0x42, 0x7f},
- 2048,
- 128,
- 0x20000,
- 64,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
- {"ESMT SLC 128MiB 3.3V 8-bit F59L1G81Mxxx",
- {NAND_ID_ESMT, 0xd1, 0x80, 0x95, 0x40, 0x7f},
- 2048,
- 128,
- 0x20000,
- 64,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
- {"A revision NAND 2Gib TC58BVG1S3HTA00 ",
- {NAND_MFR_TOSHIBA, 0xda, 0x90, 0x15, 0xF6},
- 2048,
- 256,
- 0x20000,
- 64,
- 1,
- 20,
- 25,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
- {"A revision NAND 2Gib TC58NVG1S3HBAI4 ",
- {NAND_MFR_TOSHIBA, 0xda, 0x90, 0x15, 0x76},
- 2048,
- 256,
- 0x20000,
- 64,
- 1,
- 20,
- 25,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
- {"A revision NAND 4Gib TH58NVG2S3HTA00 ",
- {NAND_MFR_TOSHIBA, 0xdc, 0x91, 0x15, 0x76},
- 2048,
- 512,
- 0x20000,
- 64,
- 1,
- 35, /* trc = 50, 20MHz max ! */
- 10,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
- {"A revision NAND 4Gib TC58NVG2S0HTA00 ",
- {NAND_MFR_TOSHIBA, 0xdc, 0x90, 0x26, 0x76},
- 4096,
- 512,
- 0x40000,
- 256,
- 1,
- 20,
- 25,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
- {"A revision NAND 4Gib TC58BVG2S0HTA00 ",
- {NAND_MFR_TOSHIBA, 0xdc, 0x90, 0x26, 0xF6},
- 4096,
- 512,
- 0x40000,
- 128,
- 1,
- 20,
- 25,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
- {"A revision NAND 1Gib TC58BVG0S3HTA00",
- {NAND_MFR_TOSHIBA, 0xf1, 0x80, 0x15, 0xf2},
- 2048,
- 128,
- 0x20000,
- 64,
- 1,
- 20,
- 25,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
- {"Slc NAND 1Gib MX30LF1G18AC ",
- {NAND_MFR_MACRONIX, 0xf1, 0x80, 0x95, 0x02},
- 2048,
- 128,
- 0x20000,
- 64,
- 1,
- 20,
- 25,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
- {"Slc NAND 2Gib MX30LF2G18AC ",
- {NAND_MFR_MACRONIX, 0xda, 0x90, 0x95, 0x06},
- 2048,
- 256,
- 0x20000,
- 64,
- 1,
- 20,
- 25,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
-
- {"Slc NAND 4Gib MX30LF4G18AC ",
- {NAND_MFR_MACRONIX, 0xdc, 0x90, 0x95, 0x56},
- 2048,
- 512,
- 0x20000,
- 64,
- 1,
- 16,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
-
- {"A revision NAND 128MB TC58NVG0S3HTA00 ",
- {NAND_MFR_TOSHIBA, 0xf1, 0x80, 0x15, 0x72},
- 2048,
- 128,
- 0x20000,
- 64,
- 1,
- 20,
- 25,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
-
- {"4Gib MT29F4G08ABAEA",
- {NAND_MFR_MICRON, 0xdc, 0x90, 0xA6, 0x54},
- 4096,
- 512,
- 0x40000,
- 224,
- 1,
- 16,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
-
- {"4Gib MT29F4G08ABADA",
- {NAND_MFR_MICRON, 0xdc, 0x90, 0x95, 0x56},
- 2048,
- 512,
- 0x20000,
- 64,
- 1,
- 16,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
-
- {"A revision NAND 2Gib MT29F2G08-A",
- {NAND_MFR_MICRON, 0xda, 0x90, 0x95, 0x06},
- 2048,
- 256,
- 0x20000,
- 64,
- 1,
- 16,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
-
- {"A revision NAND 1GiB MT29F1G-A",
- {NAND_MFR_MICRON, 0xf1, 0x80, 0x95, 0x04},
- 2048,
- 128,
- 0x20000,
- 64,
- 1,
- 16,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE )},
-
- {"A revision NAND 2GiB MT29F16G08ABABA",
- {NAND_MFR_MICRON, 0x48, 0x00, 0x26, 0x89},
- 4096,
- 2048,
- 0x80000,
- 224,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE4 | NAND_ECC_BCH8_MODE)},
-
- {"A revision NAND 4GiB MT29F32G-A",
- {NAND_MFR_MICRON, 0xd7, 0x94, 0x3e, 0x84},
- 4096,
- 4096,
- 0x80000,
- 218,
- 1,
- 16,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"A revision NAND 16GiB MT29F128G-A",
- {NAND_MFR_MICRON, 0xd9, 0xd5, 0x3e, 0x88},
- 4096,
- 16384,
- 0x80000,
- 218,
- 1,
- 16,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"B revision NAND 4GiB MT29F32G-B",
- {NAND_MFR_MICRON, 0x68, 0x04, 0x46, 0x89},
- 4096,
- 4096,
- 0x100000,
- 224,
- 1,
- 20,
- 15,
- 4,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"B revision NAND 8GiB MT29F64G-B",
- {NAND_MFR_MICRON, 0x88, 0x05, 0xc6, 0x89},
- 4096,
- 8192,
- 0x100000,
- 224,
- 1,
- 20,
- 15,
- 4,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"C revision NAND 4GiB MT29F32G-C",
- {NAND_MFR_MICRON, 0x68, 0x04, 0x4a, 0xa9},
- 4096,
- 4096,
- 0x100000,
- 224,
- 1,
- 16,
- 15,
- 5,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"C revision NAND 8GiB MT29F64G-C",
- {NAND_MFR_MICRON, 0x88, 0x04, 0x4b, 0xa9},
- 8192,
- 8192,
- 0x200000,
- 448,
- 1,
- 16,
- 15,
- 5,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"C revision NAND 1GiB MT29F8G08ABABA",
- {NAND_MFR_MICRON, 0x38, 0x00, 0x26, 0x85},
- 4096,
- 1024,
- 0x80000,
- 224,
- 1,
- 16,
- 15,
- 5,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
- |NAND_TWO_PLANE_MODE)},
-
- {"C revision NAND 32GiB MT29F256G-C",
- {NAND_MFR_MICRON, 0xa8, 0x05, 0xcb, 0xa9},
- 8192,
- 16384,
- 0x200000,
- 448,
- 2,
- 16,
- 15,
- 5,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
- | NAND_TWO_PLANE_MODE | NAND_INTERLEAVING_MODE)},
-
- {"1 Generation NAND 4GiB JS29F32G08AA-1",
- {NAND_MFR_INTEL, 0x68, 0x04, 0x46, 0xA9},
- 4096,
- 4096,
- 0x100000,
- 218,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"1 Generation NAND 8GiB JS29F64G08AA-1",
- {NAND_MFR_INTEL, 0x88, 0x24, 0x4b, 0xA9},
- 8192,
- 8192,
- 0x200000,
- 448,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"E serials NAND 2GiB TC58NVG4D2ETA00",
- {NAND_MFR_TOSHIBA, 0xD5, 0x94, 0x32, 0x76, 0x54},
- 8192,
- 2048,
- 0x100000,
- 376,
- 1,
- 20,
- 25,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"E serials NAND 4GiB TC58NVG5D2ETA00",
- {NAND_MFR_TOSHIBA, 0xD7, 0x94, 0x32, 0x76, 0x54},
- 8192,
- 4096,
- 0x100000,
- 376,
- 1,
- 20,
- 25,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"F serials NAND 2GiB TC58NVG4D2FTA00",
- {NAND_MFR_TOSHIBA, 0xD5, 0x94, 0x32, 0x76, 0x55},
- 8192,
- 2076,
- 0x100000,
- 448,
- 1,
- 20,
- 25,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"F serials NAND 4GiB TC58NVG5D2FTA00",
- {NAND_MFR_TOSHIBA, 0xD7, 0x94, 0x32, 0x76, 0x55},
- 8192,
- 4096,
- 0x100000,
- 448,
- 1,
- 20,
- 25,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"F serials NAND 8GiB TC58NVG6D2FTA00",
- {NAND_MFR_TOSHIBA, 0xDE, 0x94, 0x32, 0x76, 0x55},
- 8192,
- 8192,
- 0x100000,
- 448,
- 1,
- 20,
- 25,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"F serials NAND 8GiB TH58NVG7D2FTA20",
- {NAND_MFR_TOSHIBA, 0xDE, 0x95, 0x32, 0x7a, 0x55},
- 8192,
- 8200,
- 0x100000,
- 448,
- 2,
- 20,
- 25,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
- | NAND_TWO_PLANE_MODE | NAND_INTERLEAVING_MODE)},
-
- {"M Generation NAND 4Gib K9F4G08U0D",
- {NAND_MFR_SAMSUNG, 0xDC, 0x10, 0x95, 0x54,0XEC,},
- 2048,
- 512,
- 0x20000,
- 64,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
-
- {"M Generation NAND 1Gib FS33ND01GS108TFI0",
- {NAND_MFR_SAMSUNG, 0xF1, 0x00, 0x95, 0x42},
- 2048,
- 128,
- 0x20000,
- 64,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
-
- {"M Generation NAND 2GiB K9GAG08U0M",
- {NAND_MFR_SAMSUNG, 0xD5, 0x14, 0xb6, 0x74},
- 4096,
- 2048,
- 0x80000,
- 128,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
-
- {"5 Generation NAND 2GiB K9GAG08X0D",
- {NAND_MFR_SAMSUNG, 0xD5, 0x94, 0x29, 0x34, 0x41},
- 4096,
- 2048,
- 0x80000,
- 218,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"6 Generation NAND 2GiB K9GAG08U0E",
- {NAND_MFR_SAMSUNG, 0xD5, 0x84, 0x72, 0x50, 0x42},
- 8192,
- 2048,
- 0x100000,
- 436,
- 1,
- 25,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE)},
-
- {"7 Generation NAND 2GiB K9GAG08U0F",
- {NAND_MFR_SAMSUNG, 0xD5, 0x94, 0x76, 0x54, 0x43},
- 8192,
- 2048,
- 0x100000,
- 512,
- 1,
- 25,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"6 Generation NAND 4GiB K9LBG08U0E",
- {NAND_MFR_SAMSUNG, 0xD7, 0xC5, 0x72, 0x54, 0x42},
- 8192,
- 4096,
- 0x100000,
- 436,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"6 Generation NAND 8GiB K9HCG08U0E",
- {NAND_MFR_SAMSUNG, 0xDE, 0xC5, 0x72, 0x54, 0x42},
- 8192,
- 8192,
- 0x100000,
- 436,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"2 Generation NAND 4GiB K9GBG08U0A",
- {NAND_MFR_SAMSUNG, 0xD7, 0x94, 0x7a, 0x54, 0x43},
- 8192,
- 4152,
- 0x100000,
- 640,
- 1,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
- | NAND_TWO_PLANE_MODE)},
-
- {"2 Generation NAND 8GiB K9LCG08U0A",
- {NAND_MFR_SAMSUNG, 0xDE, 0xD5, 0x7a, 0x58, 0x43},
- 8192,
- 8304,
- 0x100000,
- 640,
- 2,
- 20,
- 15,
- 0,
- (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
- | NAND_TWO_PLANE_MODE | NAND_INTERLEAVING_MODE)},
-
- {NULL,}
-};
-
-int aml_nand_get_fbb_issue(void)
-{
- return nand_fbb_issue_flag;
-}
-
-void aml_nand_check_fbb_issue(u8 *dev_id)
-{
- int i, k;
- u8 samsung_nand_id[][MAX_ID_LEN] = {
- {NAND_MFR_SAMSUNG, 0xdc, 0x10, 0x95, 0x56},
- {NAND_MFR_SAMSUNG, 0xda, 0x10, 0x95, 0x46},
- };
-
- k = ARRAY_SIZE(samsung_nand_id);
- for (i = 0; i < k; i++) {
- if (!strncmp((char *)samsung_nand_id[i], (char *)dev_id,
- strlen((const char *)samsung_nand_id[i])))
- nand_fbb_issue_flag = 1;
- }
-}
-
-#ifdef CONFIG_PARAMETER_PAGE
-struct parameter_page para_page;
-
-void aml_nand_read_parameter_page(struct mtd_info *mtd, int ce, char * buf)
-{
-
- struct nand_chip *chip = mtd->priv;
-
- NFC_SEND_CMD(ce | CLE | 0xec);
- NFC_SEND_CMD(ce | ALE | 0x00);
- NFC_SEND_CMD(ce | IDLE | 5);
-
- signed long i,count;
- memset(buf,0,256);
- for (i=0,count=0;i<256 && count<256;i++)
- {
- *buf=chip->read_byte(mtd);
- if ((0 == i) && (0x4f != *buf))
- {
- i=-1;
- count++;
- continue;
- }
-
- buf++;
- }
-}
-
-void display_para_page(struct parameter_page para_page,unsigned long log_level)
-{
- unsigned long i;
- signed long j;
- unsigned char* buf = (unsigned char*)¶_page;
-
- printk("\nNand parameter page: \n");
-
- if ((para_page.signature[0] != 0x4f)
- || (para_page.signature[1] != 0x4e)
- || (para_page.signature[2] != 0x46)
- || (para_page.signature[3] != 0x49)) {
- printk("Wrong parameter page reading.\n");
- return;
- }
-
- if (1 == log_level) {
- printk("The parameter value is show as following list,"
- "please refer to ONFI SPEC for more infomation.\n");
- printk("index val index val index val index val ");
- for (i = 0; i < sizeof(para_page); i++, buf++) {
- if (!(i % 4))
- printf("\n");
- if (0 == i)
- printk("0~31 byte:Revision info and features blk:\n");
- else if(32 == i)
- printk("32~79 byte: Manufacturer info blk:\n");
- else if(80 == i)
- printk("80~127 byte: Memory organization blk:\n");
- else if(128 == i)
- printk("128~163 byte: Electrical parameters block:\n");
- else if(164 == i)
- printk("164~255 byte: Vendor block:\n");
- printk("%03d 0x%02x ",i, *buf);
-
- }
- } else {
- printk("Manu info: ");
- for (j=0; j<12; j++)
- printk("%c", para_page.dev_manu[j]);
- printk("\n");
-
- printk("ONFI v");
- if (para_page.ver & 0x40)
- printk("3.0 ");
- if (para_page.ver & 0x20)
- printk("2.3 ");
- if (para_page.ver & 0x10)
- printk("2.2 ");
- if (para_page.ver & 0x08)
- printk("2.1 ");
- if (para_page.ver & 0x04)
- printk("2.0 ");
- if (para_page.ver & 0x02)
- printk("1.0");
- printk("\n");
-
- printk("Feature supprot: 0x%x\n",para_page.feature);
-
- printk("%d bytes per page.\n",para_page.data_bytes_perpage);
- printk("%d spare bytes per page.\n",
- para_page.spare_bytes_perpage);
- printk("%d pages per block.\n",para_page.pages_perblk);
- printk("%d blocks per LUN.\n",para_page.blks_perLUN);
- printk("%d LUNs.\n",para_page.num_LUN);
- para_page.num_addr_cycle;
- printk("Column address cycles %d, Row address cycles %d.\n",
- para_page.num_addr_cycle & 0xf0,
- para_page.num_addr_cycle & 0xf);
- printk("%d bits per cell.\n",para_page.bits_percell);
-
- printk("Bad blocks maximum per LUN: %d\n",
- para_page.max_badblk_perLUN);
- printk("%d bits ECC correctability.\n",
- para_page.bits_ECC_corretable);
-
- printk("Support time mode: ");
- for (j = 5; j >= 0; j--) {
- if (para_page.asy_time_mode & (1<<j))
- printk("%d ",j);
- }
- }
- printk("\nEnd of Nand parameter page.\n\n");
- return;
-}
-#endif //CONFIG_PARAMETER_PAGE
-
-uint8_t aml_nand_get_onfi_features(struct aml_nand_chip *aml_chip,
- uint8_t *buf, int addr)
-{
- struct nand_chip *chip = &aml_chip->chip;
- struct mtd_info *mtd = &chip->mtd;
- int i, j;
-
- for (i=0; i<controller->chip_num; i++) {
- if (aml_chip->valid_chip[i]) {
- aml_chip->aml_nand_select_chip(aml_chip, i);
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_GET_FEATURES, -1, -1, i);
- chip->cmd_ctrl(mtd, addr,
- NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE);
- NFC_SEND_CMD_IDLE(controller, 20);
- for (j = 0; j < 4; j++)
- buf[j] = chip->read_byte(mtd);
- }
- }
- return 0;
-}
-
-void aml_nand_set_onfi_features(struct aml_nand_chip *aml_chip,
- uint8_t *buf, int addr)
-{
- int i, j;
- struct nand_chip *chip = &aml_chip->chip;
- struct mtd_info *mtd = &chip->mtd;
- for (i=0; i<controller->chip_num; i++) {
- if (aml_chip->valid_chip[i]) {
- aml_chip->aml_nand_select_chip(aml_chip, i);
- aml_chip->aml_nand_command(aml_chip,
- NAND_CMD_SET_FEATURES, -1, -1, i);
- chip->cmd_ctrl(mtd, addr,
- NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE);
- NFC_SEND_CMD_IDLE(controller, 20);
- for (j=0; j<4; j++)
- aml_chip->aml_nand_write_byte(aml_chip, buf[j]);
- aml_chip->aml_nand_wait_devready(aml_chip, i);
- }
- }
-}
-
-static struct aml_nand_flash_dev *aml_nand_get_flash_type(struct mtd_info *mtd,
- struct nand_chip *chip,
- int busw, int *maf_id)
-{
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
- struct aml_nand_platform *plat = aml_chip->platform;
- struct aml_nand_flash_dev *type = NULL;
- int i, maf_idx;
- u8 dev_id[MAX_ID_LEN];
-
-
- /* Send the command for reading device ID */
- chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
-
- /* Read manufacturer and device IDs */
- for (i=0; i<MAX_ID_LEN; i++) {
- dev_id[i] = chip->read_byte(mtd);
- }
- *maf_id = dev_id[0];
- printk("NAND device id: %x %x %x %x %x %x \n",
- dev_id[0], dev_id[1], dev_id[2], dev_id[3], dev_id[4], dev_id[5]);
-
-#if 0
- test_timing(mtd, chip);
-#endif
- /* Lookup the flash id */
- for (i = 0; aml_nand_flash_ids[i].name != NULL; i++) {
- if (!strncmp((char*) aml_nand_flash_ids[i].id,
- (char*)dev_id, strlen((const char*)aml_nand_flash_ids[i].id))) {
- type = &aml_nand_flash_ids[i];
- break;
- }
- }
- if (!type) {
- if (plat->nand_flash_dev) {
- if (!strncmp((char*) plat->nand_flash_dev->id,
- (char*)dev_id, strlen((const char*)plat->nand_flash_dev->id)))
- type = plat->nand_flash_dev;
- }
-
- if (!type)
- return ERR_PTR(-ENODEV);
- }
- aml_nand_check_fbb_issue(dev_id);
-
- /**fixme**/
- if (plat->nand_flash_dev) {
- plat->nand_flash_dev = type;
- }
-#ifdef CONFIG_MTD_DEVICE
- mtd->name = type->name;
-#else
- if (!mtd->name)
- mtd->name = type->name;
-#endif
-
- chip->chipsize = type->chipsize;
- chip->chipsize = chip->chipsize << 20;
-
- /* Newer devices have all the information in additional id bytes */
- if (!type->pagesize) {
- int extid;
- /* The 3rd id byte holds MLC / multichip data */
- /*chip->cellinfo = chip->read_byte(mtd);*/
- /* The 4th id byte is the important one */
- extid = chip->read_byte(mtd);
- /* Calc pagesize */
- mtd->writesize = 1024 << (extid & 0x3);
- extid >>= 2;
- /* Calc oobsize */
- mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
- extid >>= 2;
- /* Calc blocksize. Blocksize is multiples of 64KiB */
- mtd->erasesize = (64 * 1024) << (extid & 0x03);
- extid >>= 2;
- /* Get buswidth information */
- busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
-
- } else {
- /*Old devices have chip data hardcoded in the device id table*/
- mtd->erasesize = type->erasesize;
- mtd->writesize = type->pagesize;
- mtd->oobsize = type->oobsize;
- busw = type->options & NAND_BUSW_OPTIONS_MASK;
- }
-
- /* Try to identify manufacturer */
- for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
- if (nand_manuf_ids[maf_idx].id == *maf_id)
- break;
- }
-
- /*Check, if buswidth is correct. Hardware drivers should set
- * chip correct !*/
- if (busw != (chip->options & NAND_BUSWIDTH_16)) {
- printk(KERN_INFO "NAND device: Manufacturer ID:"
- " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
- dev_id[0], nand_manuf_ids[maf_idx].name, mtd->name);
- printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
- (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
- busw ? 16 : 8);
- return ERR_PTR(-EINVAL);
- }
-
- /* Calculate the address shift from the page size */
- chip->page_shift = ffs(mtd->writesize) - 1;
- /* Convert chipsize to number of pages per chip -1. */
- chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
-
- chip->bbt_erase_shift = chip->phys_erase_shift= ffs(mtd->erasesize) - 1;
- chip->chip_shift = ffs(chip->chipsize) - 1;
-
- /* Set the bad block position */
- chip->badblockpos = AML_BADBLK_POS;
-
- /* Get chip options, preserve non chip based options */
- /*chip->options &= ~NAND_CHIPOPTIONS_MSK;*/
- /*chip->options |= type->options & NAND_CHIPOPTIONS_MSK;*/
-
- /*Set chip as a default. Board drivers can override it, if necessary*/
- /*chip->options |= NAND_NO_AUTOINCR;*/
-
- /* Check if chip is a not a samsung device. Do not clear the
- * options for chips which are not having an extended id.
- */
- /*if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
- chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;*/
-
- printk(KERN_INFO "NAND device: Manufacturer ID:"
- " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id[0],
- nand_manuf_ids[maf_idx].name, type->name);
-
- return type;
-}
-
-
-static int aml_nand_scan_ident(struct mtd_info *mtd, int maxchips)
-{
- int i, busw, nand_maf_id, valid_chip_num = 1;
- struct nand_chip *chip = mtd->priv;
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
- struct aml_nand_flash_dev *aml_type;
- struct aml_nand_platform *plat = aml_chip->platform;
- u8 dev_id[MAX_ID_LEN], onfi_features[4];
- unsigned temp_chip_shift;
-
- chip->cmdfunc = aml_nand_command;
- chip->waitfunc = aml_nand_wait;
- chip->erase = aml_nand_erase_cmd;
- chip->write_page = aml_nand_write_page;
-
- /* Get buswidth to select the correct functions */
- busw = chip->options & NAND_BUSWIDTH_16;
-
- /* Select the device */
- chip->select_chip(mtd, 0);
-
- /*reset chip for some nand need reset after power up*/
- chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
- aml_chip->aml_nand_wait_devready(aml_chip, 0);
-
- /* Read the flash type */
- aml_type = aml_nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
-
- if (IS_ERR(aml_type)) {
- printk(KERN_WARNING "No NAND device found!!!\n");
- chip->select_chip(mtd, -1);
- return PTR_ERR(aml_type);
- }
- chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
- for (i=0; i<MAX_ID_LEN; i++) {
- dev_id[i] = chip->read_byte(mtd);
- }
- if (!memcmp((char*)dev_id, "ONFI", 4))
- aml_chip->onfi_mode = aml_type->onfi_mode;
-
- aml_chip->T_REA = aml_type->T_REA;
- aml_chip->T_RHOH = aml_type->T_RHOH;
- aml_chip->mfr_type = aml_type->id[0];
-#ifdef CONFIG_PARAMETER_PAGE
- aml_nand_read_parameter_page(mtd, CE0, ¶_page);
- display_para_page(para_page, 0);
-#endif
- /* Check for a chip array */
- for (i = 1; i < maxchips; i++) {
- aml_chip->aml_nand_select_chip(aml_chip, i);
- chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
- aml_chip->aml_nand_wait_devready(aml_chip, i);
-
- /* Send the command for reading device ID */
- chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
- /* Read manufacturer and device IDs */
-
- if (nand_maf_id != chip->read_byte(mtd)
- || aml_type->id[1] != chip->read_byte(mtd))
- /*if (nand_maf_id != dev_id[0] || aml_type->id[1] != dev_id[1])*/
- aml_chip->valid_chip[i] = 0;
- else
- valid_chip_num ++;
- }
-
- if (i > 1) {
- printk(KERN_INFO "%d NAND chips detected\n", valid_chip_num);
- }
-
- /*
- *fixit, Need to send dummy cmd for spansion(MLO2G100BH1OO) which is different
- *from others.
- */
- if (aml_chip->mfr_type == NAND_MFR_AMD )
- chip->cmdfunc(mtd, 0x00, -1, -1);
-
- if (aml_chip->onfi_mode) {
- aml_nand_set_onfi_features(aml_chip,
- (uint8_t *)(&aml_chip->onfi_mode), ONFI_TIMING_ADDR);
- aml_nand_get_onfi_features(aml_chip,
- onfi_features, ONFI_TIMING_ADDR);
- if (onfi_features[0] != aml_chip->onfi_mode) {
- aml_chip->T_REA = DEFAULT_T_REA;
- aml_chip->T_RHOH = DEFAULT_T_RHOH;
- printk("onfi timing mode set failed: %x\n",
- onfi_features[0]);
- }
- }
-
- /* Store the number of chips and calc total size for mtd */
- chip->numchips = 1;
- if ((chip->chipsize >> 32) & 0xffffffff)
- chip->chip_shift =
- fls((unsigned)(chip->chipsize >> 32)) * valid_chip_num + 32 - 1;
- else
- chip->chip_shift =
- fls((unsigned)chip->chipsize) * valid_chip_num - 1;
-
- chip->pagemask =
- ((chip->chipsize * valid_chip_num) >> chip->page_shift) - 1;
- chip->options &= ~NAND_CACHEPRG;
- aml_chip->internal_chipnr = aml_type->internal_chipnr;
- aml_chip->internal_page_nums = (chip->chipsize >> chip->page_shift);
- aml_chip->internal_page_nums /= aml_chip->internal_chipnr;
- aml_chip->internal_chip_shift =
- fls((unsigned)aml_chip->internal_page_nums) - 1;
- temp_chip_shift = ffs((unsigned)aml_chip->internal_page_nums) - 1;
- if (aml_chip->internal_chip_shift != temp_chip_shift) {
- aml_chip->internal_chip_shift += 1;
- chip->chip_shift += 1;
- chip->pagemask =
- ((1 << (chip->chip_shift + 1)) >> chip->page_shift) - 1;
- }
- chip->bits_per_cell = 1;
- aml_chip->options = aml_type->options;
- aml_chip->page_size = aml_type->pagesize;
- aml_chip->block_size = aml_type->erasesize;
- aml_chip->oob_size = aml_type->oobsize;
- mtd->erasesize = valid_chip_num * aml_type->erasesize;
- mtd->writesize = valid_chip_num * aml_type->pagesize;
- mtd->oobsize = valid_chip_num * aml_type->oobsize;
- mtd->size = valid_chip_num * chip->chipsize;
-
- /* overide bootloader's size consdering info page */
- /* fixme, need -1 for each copies? */
- if (!strncmp((char*)plat->name,
- NAND_BOOT_NAME, strlen((const char*)NAND_BOOT_NAME)))
- mtd->size = BOOT_TOTAL_PAGES * mtd->writesize;
-
- return 0;
-}
-
-int aml_nand_scan(struct mtd_info *mtd, int maxchips)
-{
- int ret;
-
- ret = aml_nand_scan_ident(mtd, maxchips);
- if (!ret)
- ret = nand_scan_tail(mtd);
- return ret;
-}
-
-
-
diff --git a/drivers/mtd/nand/aml_nand/storage_nand.c b/drivers/mtd/nand/aml_nand/storage_nand.c
deleted file mode 100644
index ec8a51c..0000000
--- a/drivers/mtd/nand/aml_nand/storage_nand.c
+++ /dev/null
@@ -1,107 +0,0 @@
-#include <common.h>
-#include <dm.h>
-#include <linux/mtd/mtd.h>
-#include <linux/mtd/rawnand.h>
-#include <amlogic/storage.h>
-#include <amlogic/aml_mtd.h>
-#include "aml_nand.h"
-#include <dm/device.h>
-
-static struct storage_t *slcnand_storage;
-
-extern void mtd_store_init_map(void);
-extern void mtd_store_set(struct mtd_info *mtd, int dev);
-extern void mtd_store_mount_ops(struct storage_t* store);
-
-static inline void set_slc_nand_storage(struct storage_t *slc_nand)
-{
- slcnand_storage = slc_nand;
-}
-
-static inline struct storage_t *get_slc_nand_storage(void)
-{
- return slcnand_storage;
-}
-
-
-int nand_pre(void)
-{
- return 0;
-}
-
-extern struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
-//extern struct aml_nand_flash_dev aml_nand_flash_ids[];
-int slcnand_fit_storage(void)
-{
- struct storage_t *slc_nand = NULL;
-
- struct aml_nand_chip *aml_chip = mtd_to_nand_chip(nand_info[0]);
- struct aml_nand_flash_dev *type = NULL;
-
- if (get_slc_nand_storage())
- return 0;
-
- type = aml_chip->platform->nand_flash_dev;
-
- if (slc_nand == NULL) {
- slc_nand = kzalloc(sizeof(struct storage_t), GFP_KERNEL);
- if (!slc_nand) {
- debug("%s %d no enough memory!\n", __func__, __LINE__);
- return -ENOMEM;
- }
- }
-
- slc_nand->type = BOOT_NAND_MTD;
- slc_nand->init_flag = 0;
- printf("storage dev type: 0x%x, storage device is slc NAND\n",slc_nand->type);
-
- memcpy(slc_nand->info.name, type->name, 32*sizeof(char));
- memcpy(slc_nand->info.id, type->id, 8);
- printf("name: %s\n",slc_nand->info.name);
-
- slc_nand->info.read_unit = type->pagesize;
- slc_nand->info.write_unit = type->pagesize;
- slc_nand->info.erase_unit = type->erasesize;
- slc_nand->info.caps = ((type->chipsize) << 20);
- printf("cap: 0x%llx\n", slc_nand->info.caps);
-#ifdef CONFIG_DISCRETE_BOOTLOADER
- slc_nand->info.mode = 1;
-#else
- slc_nand->info.mode = 0;
-#endif
-
- set_slc_nand_storage(slc_nand);
- mtd_store_mount_ops(slc_nand);
-
- //mtd_store_set(nand_info[0], 0);
-
- mtd_store_init_map();
-
- return store_register(slc_nand);
-}
-
-extern int amlmtd_init;
-extern void board_nand_init(void);
-extern int meson_nfc_probe(struct udevice *dev);
-int nand_probe(uint32_t init_flag)
-{
- struct storage_t *slc_nand = get_slc_nand_storage();
-
- if (slc_nand) {
- slc_nand->init_flag = init_flag;
- printf("nand probe success\n");
- return 0;
- }
-
- board_nand_init();
- slc_nand = get_slc_nand_storage();
- if (!slc_nand) {
- printf("%s %d can not get slc nand!\n",
- __func__, __LINE__);
- return 1;
- }
- slc_nand->init_flag = init_flag;
- printf("nand probe success\n");
- return 0;
-}
-
diff --git a/drivers/mtd/nand/bbt.c b/drivers/mtd/nand/bbt.c
index 7e0ad31..2d04edf 100644
--- a/drivers/mtd/nand/bbt.c
+++ b/drivers/mtd/nand/bbt.c
@@ -10,6 +10,7 @@
#define pr_fmt(fmt) "nand-bbt: " fmt
#include <linux/mtd/nand.h>
+#include <linux/bitops.h>
#ifndef __UBOOT__
#include <linux/slab.h>
#endif
diff --git a/drivers/mtd/nand/core.c b/drivers/mtd/nand/core.c
index 0b79369..8ed6e79 100644
--- a/drivers/mtd/nand/core.c
+++ b/drivers/mtd/nand/core.c
@@ -7,13 +7,16 @@
* Peter Pan <peterpandong@micron.com>
*/
-#define pr_fmt(fmt) "nand: " fmt
-
+//#define pr_fmt(fmt) "nand: " fmt
+#include <linux/bitops.h>
#ifndef __UBOOT__
#include <linux/module.h>
#endif
#include <linux/mtd/nand.h>
-
+#ifdef CONFIG_MTD_SPI_NAND
+#include <linux/mtd/spinand.h>
+#include <amlogic/aml_rsv.h>
+#endif
/**
* nanddev_isbad() - Check if a block is bad
* @nand: NAND device
@@ -23,6 +26,31 @@
*/
bool nanddev_isbad(struct nand_device *nand, const struct nand_pos *pos)
{
+#ifdef CONFIG_MTD_SPI_NAND
+ struct spinand_device *spinand = nand_to_spinand(nand);
+ u8 bad_block;
+
+ /* If bbt is already initialized, use the bbt of meson
+ * to manage bad blocks.
+ */
+ if (spinand->bbt && !spinand->bbt_scan) {
+ bad_block = spinand->bbt[pos->eraseblock];
+ if (bad_block != NAND_BLOCK_BAD &&
+ bad_block != NAND_FACTORY_BAD &&
+ bad_block != NAND_BLOCK_GOOD) {
+ pr_err("bad block table is mixed\n");
+ return true;
+ }
+
+ if (bad_block == NAND_BLOCK_GOOD)
+ return false;
+
+ pr_err("meson %s bad block at 0x%x\n",
+ (bad_block == NAND_FACTORY_BAD) ? "factory" : "user",
+ pos->eraseblock*(u32)nanddev_eraseblock_size(nand));
+ return true;
+ }
+#endif
if (nanddev_bbt_is_initialized(nand)) {
unsigned int entry;
int status;
@@ -71,9 +99,39 @@
ret = nand->ops->markbad(nand, pos);
if (ret)
- pr_warn("failed to write BBM to block @%llx (err = %d)\n",
+ pr_err("failed to write BBM to block @%llx (err = %d)\n",
nanddev_pos_to_offs(nand, pos), ret);
+#ifdef CONFIG_MTD_SPI_NAND
+ extern int meson_rsv_bbt_write(u_char *source, size_t size);
+ struct spinand_device *spinand = nand_to_spinand(nand);
+ u8 bad_block;
+ u8 *buf = NULL;
+
+ /* If bbt is already initialized, use the bbt of meson
+ * to manage bad blocks.
+ */
+ if (spinand->bbt && !spinand->bbt_scan) {
+ bad_block = spinand->bbt[pos->eraseblock];
+ if (bad_block != NAND_BLOCK_BAD &&
+ bad_block != NAND_FACTORY_BAD &&
+ bad_block != NAND_BLOCK_GOOD) {
+ pr_err("bad block table is mixed\n");
+ return -EINVAL;
+ }
+
+ if (bad_block == NAND_BLOCK_GOOD) {
+ buf = spinand->bbt;
+ buf[pos->eraseblock] = NAND_BLOCK_BAD;
+ meson_rsv_bbt_write((u_char *)buf,
+ spinand->rsv->bbt->size);
+ }
+ } else {
+ pr_err("meson bbt table is not initial");
+ return -EINVAL;
+ }
+#endif
+
if (!nanddev_bbt_is_initialized(nand))
goto out;
@@ -106,6 +164,10 @@
unsigned int entry;
int status;
+#ifdef CONFIG_MTD_SPI_NAND
+ return false;
+#endif
+
if (!nanddev_bbt_is_initialized(nand))
return false;
diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig
index 78dda74..db11bc0 100644
--- a/drivers/mtd/nand/raw/Kconfig
+++ b/drivers/mtd/nand/raw/Kconfig
@@ -27,6 +27,13 @@
select SYS_NAND_SELF_INIT
imply CMD_NAND
+config SPI_NAND
+ bool "Enable SPI NAND DRIVER"
+ depends on MTD
+ help
+ This option, if enabled, SOC can support SPI-NAND flash
+ driver.
+
config NAND_DENALI_DT
bool "Support Denali NAND controller as a DT device"
select NAND_DENALI
@@ -211,6 +218,12 @@
This flag prevent U-boot reconfigure NAND flash controller and reuse
the NAND timing from 1st stage bootloader.
+config MESON_NFC
+ bool "Support for NAND on Amlogic SoCs"
+ depends on ARCH_MESON && MTD
+ help
+ This option, if enabled, support for MESON Nand flash controller.
+
comment "Generic NAND options"
config SYS_NAND_BLOCK_SIZE
@@ -306,4 +319,3 @@
endif
endif # if NAND
-
diff --git a/drivers/mtd/nand/raw/Makefile b/drivers/mtd/nand/raw/Makefile
index c61e3f3..b0c80a8 100644
--- a/drivers/mtd/nand/raw/Makefile
+++ b/drivers/mtd/nand/raw/Makefile
@@ -33,6 +33,7 @@
obj-y += nand_base.o
obj-y += nand_timings.o
+
endif # not spl
ifdef NORMAL_DRIVERS
diff --git a/drivers/mtd/nand/aml_nand/Makefile b/drivers/mtd/nand/raw/aml_nand/Makefile
similarity index 100%
rename from drivers/mtd/nand/aml_nand/Makefile
rename to drivers/mtd/nand/raw/aml_nand/Makefile
diff --git a/drivers/mtd/nand/raw/aml_nand/aml_hwctrl.h b/drivers/mtd/nand/raw/aml_nand/aml_hwctrl.h
new file mode 100644
index 0000000..6d1ace7
--- /dev/null
+++ b/drivers/mtd/nand/raw/aml_nand/aml_hwctrl.h
@@ -0,0 +1,527 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AML_HWCTRL_H__
+#define __AML_HWCTRL_H__
+
+//#include <asm/arch/secure_apb.h>
+#include <asm/arch/cpu_sdio.h>
+#include <asm/io.h>
+#include <clk.h>
+#define AML_NAND_UBOOT
+#define NAND_TWB_TIME_CYCLE 10
+
+#define HHI_NAND_CLK_CNTL1 (0xff63c000 + (0x097 << 2))
+
+#define CE_PAD_DEFAULT \
+ ((AML_NAND_CE0) | \
+ (AML_NAND_CE1 << 4) | \
+ (AML_NAND_CE2 << 8) | \
+ (AML_NAND_CE3 << 12))
+
+#define RB_PAD_DEFAULT (AML_NAND_CE0)
+#define MAX_CHIP_NUM 4
+
+/*** HW controller configuration ***/
+struct hw_controller {
+ struct udevice *device;
+ u32 chip_selected;
+ u32 rb_received;
+ u8 chip_num;
+ u32 ce_enable[MAX_CHIP_NUM];
+ u32 rb_enable[MAX_CHIP_NUM];
+ struct clk xtal;
+ struct clk fdiv2;
+ struct clk mux;
+ struct clk div;
+ struct clk gate;
+ void __iomem *reg_base;
+ void __iomem *nand_clk_reg;
+ u32 irq;
+};
+
+#ifndef AML_NAND_UBOOT
+#include <linux/types.h>
+#endif /* AML_NAND_UBOOT */
+
+#define NF_REG_INDEX 0
+#define EXTCLK_REG_INDEX 1
+#define EXTPORT_REG_INDEX 2
+
+#define RETURN_PAGE_ALL_0XFF 0x01
+#define RETURN_PAGE_NEED_READRETRY 0x02
+
+#ifdef AML_NAND_UBOOT
+#define MESON_CPU_MAJOR_ID_M8 0x19
+#define MESON_CPU_MAJOR_ID_GX 0x21
+#endif /* AML_NAND_UBOOT */
+
+#ifdef AML_NAND_UBOOT
+static inline int get_cpu_type(void)
+{
+ return MESON_CPU_MAJOR_ID_GX;
+}
+#endif /* AML_NAND_UBOOT */
+
+#define NAND_CYCLE_DELAY ((get_cpu_type() >= MESON_CPU_MAJOR_ID_M8)?(84):(90))
+
+#ifdef AML_NAND_UBOOT
+/* gxb and later, for pxp and ic. */
+#define P_NAND_BASE (SD_EMMC_BASE_C | (1<<11))
+#define NAND_BASE_APB (P_NAND_BASE)
+#define NAND_CLK_REG (SD_EMMC_BASE_C)
+#endif /* AML_NAND_UBOOT */
+
+/* NAND Write Command And Read Status Register */
+#define P_NAND_CMD (0x00)
+/* NAND Configuration Register */
+#define P_NAND_CFG (0x04)
+/* NAND Data Address Register */
+#define P_NAND_DADR (0x08)
+/* NAND Information Address Register */
+#define P_NAND_IADR (0x0c)
+/* NAND Read Data Buffer Register */
+#define P_NAND_BUF (0x10)
+/* NAND Information Register */
+#define P_NAND_INFO (0x14)
+/* NAND DDR interface Register */
+#define P_NAND_DC (0x18)
+/* NAND DDR Address Register */
+#define P_NAND_ADR (0x1c)
+/* NAND DDR Low 32 bits Data Register */
+#define P_NAND_DL (0x20)
+/* NAND DDR High 32 bits Data Register */
+#define P_NAND_DH (0x24)
+/* NAND Command Queus Address Register */
+#define P_NAND_CADR (0x28)
+/* NAND Status Address Register */
+#define P_NAND_SADR (0x2c)
+/* NAND CS2: SDRAM/NAND pin sharing Register */
+#define P_NAND_PINS (0x30)
+/* NAND Version number Register */
+#define P_NAND_VER (0x38)
+
+/*...other way to access cfg...*/
+typedef union _nand_cfg {
+ /** raw register data */
+ u32 d;
+ /** register bits */
+ struct {
+ u32 bus_cyc:5; //0
+ u32 bus_tim:5; //5
+ u32 sync:2; //10
+ u32 cmd_start:1; //12
+ u32 cmd_auto:1; //13
+ u32 apb_mode:1; //14
+ u32 spare_only:1; //15
+ u32 sync_adj:1; //16
+ u32 secure_des:1; //17
+ u32 reserved18:2; //18
+ u32 sts_irq_en:1; //20
+ u32 cmd_irq_en:1; //21
+ u32 reserved22:4; //25
+ u32 oob_on:1; //26
+ u32 oob_mode:1; //27
+ u32 dc_ugt:1; //28
+ u32 nand_wpn:1; //29
+ u32 dma_power:1; //30
+ u32 bus_power:1; //31
+ } b;
+} nand_cfg_t;
+
+typedef struct _nand_reg {
+ volatile u32 cmd;
+ volatile u32 cfg;
+} nand_reg_t;
+
+extern nand_reg_t *p_nand_reg;
+static inline u32 amlnf_read_reg32(volatile uint32_t *_reg)
+{
+ /*---*/
+#ifndef AML_NAND_UBOOT
+ smp_rmb();
+#endif /* AML_NAND_UBOOT */
+ return __raw_readl(_reg);
+};
+
+static inline void amlnf_write_reg32(volatile uint32_t *_reg,
+ const u32 _value)
+{
+ __raw_writel(_value, _reg);
+ /*---*/
+#ifndef AML_NAND_UBOOT
+ smp_mb();
+#endif /* AML_NAND_UBOOT */
+};
+
+static inline void amlnf_set_reg32_bits(volatile uint32_t *_reg,
+ const u32 _value,
+ const u32 _start,
+ const u32 _len)
+{
+ /*---*/
+#ifndef AML_NAND_UBOOT
+ smp_rmb();
+#endif /* AML_NAND_UBOOT */
+ __raw_writel(((__raw_readl(_reg) & ~(((1L << (_len))-1) << (_start)))
+ | ((u32)((_value)&((1L<<(_len))-1)) << (_start))), _reg);
+ /*---*/
+#ifndef AML_NAND_UBOOT
+ smp_wmb();
+#endif /* AML_NAND_UBOOT */
+}
+
+static inline void amlnf_clrset_reg32_bits(volatile uint32_t *_reg,
+ const u32 clr,
+ const u32 set)
+{
+ /*---*/
+#ifndef AML_NAND_UBOOT
+ smp_rmb();
+#endif /* AML_NAND_UBOOT */
+ __raw_writel((__raw_readl(_reg) & ~(clr)) | (set), _reg);
+ /*---*/
+#ifndef AML_NAND_UBOOT
+ smp_wmb();
+#endif /* AML_NAND_UBOOT */
+}
+
+static inline u32 amlnf_get_reg32_bits(volatile uint32_t *_reg,
+ const u32 _start,
+ const u32 _len)
+{
+ /*---*/
+#ifndef AML_NAND_UBOOT
+ smp_rmb();
+#endif /* AML_NAND_UBOOT */
+ return (__raw_readl(_reg) >> (_start)) & ((1L << (_len)) - 1);
+}
+
+static inline void amlnf_set_reg32_mask(volatile uint32_t *_reg,
+ const u32 _mask)
+{
+ /*---*/
+#ifndef AML_NAND_UBOOT
+ smp_rmb();
+#endif /* AML_NAND_UBOOT */
+ __raw_writel((__raw_readl(_reg) | (_mask)), _reg);
+ /*---*/
+#ifndef AML_NAND_UBOOT
+ smp_wmb();
+#endif /* AML_NAND_UBOOT */
+}
+
+static inline void amlnf_clr_reg32_mask(volatile uint32_t *_reg,
+ const u32 _mask)
+{
+ /*---*/
+#ifndef AML_NAND_UBOOT
+ smp_rmb();
+#endif /* AML_NAND_UBOOT */
+ __raw_writel((__raw_readl(_reg) & (~(_mask))), _reg);
+ /*---*/
+#ifndef AML_NAND_UBOOT
+ smp_wmb();
+#endif /* AML_NAND_UBOOT */
+}
+
+/*
+#define nfc_readl(host, reg) \
+ __raw_readl((host)->reg_base + P_##reg)
+#define nfc_writel(host, reg, value) \
+ __raw_writel((value), (host)->reg_base + P_##reg)
+#define nfc_readw(host, reg) \
+ __raw_readw((host)->reg_base + P_##reg)
+#define nfc_writew(host, reg, value) \
+ __raw_writew((value), (host)->reg_base + P_##reg)
+ #define nfc_readb(host, reg) \
+ __raw_readb((host)->reg_base + P_##reg)
+#define nfc_writeb(host, reg, value) \
+ __raw_writeb((value), (host)->reg_base + P_##reg)
+
+#define nfc_set_bits(host, reg) \
+ {\
+ u32 value;\
+ value = __raw_readl((host)->reg_base + P_##reg);\
+ value &= ~((( 1L << (_len) )-1) << (_start)); \
+ value |= ((u32)((_value)&((1L<<(_len))-1)) << (_start));\
+ __raw_writel(value, (host)->reg_base + P_##reg);\
+ }
+*/
+
+#define AMLNF_WRITE_REG(reg, val) (amlnf_write_reg32(reg, (val)))
+#define AMLNF_READ_REG(reg) (amlnf_read_reg32(reg))
+/*
+#define AMLNF_WRITE_REG_BITS(reg, val, start, len) \
+ (amlnf_set_reg32_bits((volatile uint32_t *)(reg), (val), start, len))
+*/
+#define AMLNF_WRITE_REG_BITS(reg, val, start, len) \
+ (amlnf_set_reg32_bits(reg, val, start, len))
+/*
+#define AMLNF_READ_REG_BITS(bus,reg, start, len) \
+ (amlnf_get_reg32_bits(reg,start,len))
+*/
+/*
+#define AMLNF_CLEAR_REG_MASK(reg, mask) \
+ (amlnf_clr_reg32_mask((volatile uint32_t *)(reg), (mask)))
+#define AMLNF_SET_REG_MASK(reg, mask) \
+ (amlnf_set_reg32_mask((volatile uint32_t *)(reg), (mask)))
+*/
+#define AMLNF_CLEAR_REG_MASK(reg, mask) (amlnf_clr_reg32_mask(reg, mask))
+#define AMLNF_SET_REG_MASK(reg, mask) (amlnf_set_reg32_mask(reg, mask))
+
+/*
+#define NFC_SET_TIMING(host, mode, cycles, adjust) \
+ AMLNF_WRITE_REG_BITS((host)->reg_base + P_NAND_CFG, \
+ ((cycles)|((adjust&0xf)<<10)|((mode&7)<<5)), 0, 14)
+#define NFC_SET_CMD_START(host) \
+ AMLNF_SET_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<12)
+
+#define NFC_SET_CMD_AUTO(host) \
+ AMLNF_SET_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<13)
+
+#define NFC_SET_STS_IRQ(host, en) \
+ AMLNF_WRITE_REG_BITS((host)->reg_base + P_NAND_CFG, en, 20, 1)
+
+#define NFC_SET_CMD_IRQ(host, en) \
+ AMLNF_WRITE_REG_BITS((host)->reg_base + P_NAND_CFG, en, 21, 1)
+*/
+#define NFC_SET_TIMING_ASYC(host, bus_tim, bus_cyc) \
+ AMLNF_WRITE_REG_BITS((host)->reg_base + P_NAND_CFG, \
+ ((bus_cyc&31)|((bus_tim&31)<<5)|(0<<10)), \
+ 0, \
+ 12)
+/*
+#define NFC_SET_TIMING_SYNC(host, bus_tim, bus_cyc, sync_mode) \
+ AMLNF_WRITE_REG_BITS((host)->reg_base + P_NAND_CFG, \
+ (bus_cyc&31)|((bus_tim&31)<<5)|((sync_mode&2)<<10), \
+ 0, \
+ 12)
+#define NFC_SET_TIMING_SYNC_ADJUST()
+#define NFC_SET_DMA_MODE(host, is_apb, spare_only) \
+ AMLNF_WRITE_REG_BITS((host)->reg_base + P_NAND_CFG, \
+ ((spare_only<<1)|(is_apb)), \
+ 14, \
+ 2)
+*/
+#define NFC_SET_OOB_MODE(host, mode) \
+ AMLNF_SET_REG_MASK((host)->reg_base + P_NAND_CFG, mode);
+#define NFC_CLR_OOB_MODE(host, mode) \
+ AMLNF_CLEAR_REG_MASK((host)->reg_base + P_NAND_CFG, mode);
+/*
+#define NFC_ENABLE_STS_IRQ(host) \
+ AMLNF_SET_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<20)
+#define NFC_DISABLE_STS_IRQ(host) \
+ AMLNF_CLEAR_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<20)
+*/
+#define NFC_ENABLE_IO_IRQ(host) \
+ AMLNF_SET_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<21)
+#define NFC_DISABLE_IO_IRQ(host) \
+ AMLNF_CLEAR_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<21)
+
+#define NFC_ENABLE_ENCRYPT(host) \
+ AMLNF_SET_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<17)
+#define NFC_DISABLE_ENCRYPT(host) \
+ AMLNF_CLEAR_REG_MASK((host)->reg_base + P_NAND_CFG, 1<<17)
+
+
+/**
+ ADDR operations
+*/
+#define NFC_SET_DADDR(host, a) \
+ (AMLNF_WRITE_REG((host)->reg_base + P_NAND_DADR, (u32)a))
+#define NFC_SET_IADDR(host, a) \
+ (AMLNF_WRITE_REG((host)->reg_base + P_NAND_IADR, (u32)a))
+#define NFC_SET_SADDR(host, a) \
+ (AMLNF_WRITE_REG((host)->reg_base + P_NAND_SADR, (u32)a))
+
+#define NFC_INFO_GET(host) \
+ (AMLNF_READ_REG((host)->reg_base + P_NAND_CMD))
+
+#define NFC_GET_BUF(host) \
+ AMLNF_READ_REG((host)->reg_base + P_NAND_BUF)
+#define NFC_SET_CFG(host, val) \
+ (AMLNF_WRITE_REG((host)->reg_base + P_NAND_CFG, (u32)val))
+
+/*Common Nand Read Flow*/
+ #define CE0 (0xe<<10)
+#define CE1 (0xd<<10)
+#define CE2 (0xb<<10)
+#define CE3 (0x7<<10)
+#define CE_NOT_SEL (0xf<<10)
+#define IO4 ((0xe<<10)|(1<<18))
+#define IO5 ((0xd<<10)|(1<<18))
+#define IO6 ((0xb<<10)|(1<<18))
+#define CLE (0x5<<14)
+#define ALE (0x6<<14)
+#define DWR (0x4<<14)
+#define DRD (0x8<<14)
+#define IDLE (0xc<<14)
+#define RB (1<<20)
+#define STANDBY (0xf<<10)
+
+#define M2N ((0<<17) | (2<<20) | (1<<19))
+#define N2M ((1<<17) | (2<<20) | (1<<19))
+
+#define M2N_NORAN 0x00200000
+#define N2M_NORAN 0x00220000
+
+#define STS ((3<<17) | (2<<20))
+#define ADL ((0<<16) | (3<<20))
+#define ADH ((1<<16) | (3<<20))
+#define AIL ((2<<16) | (3<<20))
+#define AIH ((3<<16) | (3<<20))
+#define ASL ((4<<16) | (3<<20))
+#define ASH ((5<<16) | (3<<20))
+#define SEED ((8<<16) | (3<<20))
+
+#define SEED_OFFSET 0xc2
+
+#define NFC_CMD_IDLE(ce, time) ((ce)|IDLE|(time&0x3ff))
+#define NFC_CMD_CLE(ce, cmd) ((ce)|CLE | (cmd & 0x0ff))
+#define NFC_CMD_ALE(ce, addr) ((ce)|ALE | (addr&0x0ff))
+#define NFC_CMD_STANDBY(time) (STANDBY | (time&0x3ff))
+#define NFC_CMD_ADL(addr) (ADL | (addr&0xffff))
+#define NFC_CMD_ADH(addr) (ADH|((addr>>16)&0xffff))
+#define NFC_CMD_AIL(addr) (AIL | (addr&0xffff))
+#define NFC_CMD_AIH(addr) (AIH|((addr>>16)&0xffff))
+#define NFC_CMD_DWR(ce, data) (ce|DWR | (data&0xff))
+#define NFC_CMD_DRD(ce, size) (ce|DRD|size)
+#define NFC_CMD_RB(ce, time) ((ce)|RB | (time&0x1f))
+#define NFC_CMD_RB_INT(ce, time) \
+ ((ce)|RB|(((ce>>10)^0xf)<<14)|(time&0x1f))
+#define NFC_CMD_RBIO(time, io) (RB|io|(time&0x1f))
+#define NFC_CMD_RBIO_IRQ(time) (RB|IO6|(1<<16)|(time&0x1f))
+#define NFC_CMD_RBIO_INT(io, time) (RB|(((io>>10)^0x7)<<14)|(time&0x1f))
+#define NFC_CMD_SEED(seed) (SEED|(SEED_OFFSET + (seed&0x7fff)))
+#define NFC_CMD_STS(tim) (STS|(tim&3))
+#define NFC_CMD_M2N(ran, ecc, sho, pgsz, pag) \
+ ((ran?M2N:M2N_NORAN)|(ecc<<14)|(sho<<13)|((pgsz&0x7f)<<6)|(pag&0x3f))
+#define NFC_CMD_N2M(ran, ecc, sho, pgsz, pag)\
+ ((ran?N2M:N2M_NORAN)|(ecc<<14)|(sho<<13)|((pgsz&0x7f)<<6)|(pag&0x3f))
+
+/**
+Alias for CMD
+#define NFC_CMD_D_ADR(addr) NFC_CMD_ADL(addr), NFC_CMD_ADH(addr)
+#define NFC_CMD_I_ADR(addr) NFC_CMD_ADI(addr), NFC_CMD_ADI(addr)
+*/
+#define NAND_ECC_NONE (0x0)
+#define NAND_ECC_BCH8 (0x1)
+#define NAND_ECC_BCH8_1K (0x2)
+#define NAND_ECC_BCH24_1K (0x3)
+#define NAND_ECC_BCH30_1K (0x4)
+#define NAND_ECC_BCH40_1K (0x5)
+#define NAND_ECC_BCH50_1K (0x6)
+/*NAND_ECC_BCH50_1K only for mtd general*/
+#define NAND_ECC_BCH60_1K (0x7)
+#define NAND_ECC_BCH_SHORT (0x8)
+
+#define PER_INFO_BYTE 8
+/*Register Operation and Controller Status*/
+#define NFC_SEND_CMD(host, cmd) \
+ (AMLNF_WRITE_REG((host)->reg_base + P_NAND_CMD, cmd))
+#define NFC_READ_INFO(host) \
+ (AMLNF_READ_REG((host)->reg_base + P_NAND_CMD))
+
+/*Send command directly*/
+#define NFC_SEND_CMD_IDLE(host, time) \
+ {\
+ while (NFC_CMDFIFO_SIZE(host) > 0)\
+ ; \
+ NFC_SEND_CMD(host, NFC_CMD_IDLE((host)->chip_selected, time)); \
+ }
+#define NFC_SEND_CMD_CLE(host, ce, cmd) \
+ NFC_SEND_CMD(host, NFC_CMD_CLE(ce, cmd))
+#define NFC_SEND_CMD_ALE(host, ce, addr) \
+ NFC_SEND_CMD(host, NFC_CMD_ALE(ce, addr))
+#define NFC_SEND_CMD_STANDBY(host, time) \
+ NFC_SEND_CMD(host, NFC_CMD_STANDBY(time))
+#define NFC_SEND_CMD_ADL(host, addr) \
+ NFC_SEND_CMD(host, NFC_CMD_ADL(addr))
+#define NFC_SEND_CMD_ADH(host, addr) \
+ NFC_SEND_CMD(host, NFC_CMD_ADH(addr))
+#define NFC_SEND_CMD_AIL(host, addr) \
+ NFC_SEND_CMD(host, NFC_CMD_AIL(addr))
+#define NFC_SEND_CMD_AIH(host, addr) \
+ NFC_SEND_CMD(host, NFC_CMD_AIH(addr))
+#define NFC_SEND_CMD_DWR(host, ce, data) \
+ NFC_SEND_CMD(host, NFC_CMD_DWR(ce, data))
+#define NFC_SEND_CMD_DRD(host, ce, size) \
+ NFC_SEND_CMD(host, NFC_CMD_DRD(ce, size))
+#define NFC_SEND_CMD_RB(host, ce, time) \
+ NFC_SEND_CMD(host, NFC_CMD_RB(ce, time))
+#define NFC_SEND_CMD_SEED(host, seed) \
+ NFC_SEND_CMD(host, NFC_CMD_SEED(seed))
+#define NFC_SEND_CMD_M2N(host, ran, ecc, sho, pgsz, pag) \
+ NFC_SEND_CMD(host, NFC_CMD_M2N(ran, ecc, sho, pgsz, pag))
+#define NFC_SEND_CMD_N2M(host, ran, ecc, sho, pgsz, pag) \
+ NFC_SEND_CMD(host, NFC_CMD_N2M(ran, ecc, sho, pgsz, pag))
+
+#define NFC_SEND_CMD_M2N_RAW(host, ran, len) \
+ NFC_SEND_CMD(host, (ran?M2N:M2N_NORAN)|(len&0x3fff))
+#define NFC_SEND_CMD_N2M_RAW(host, ran, len) \
+ NFC_SEND_CMD(host, (ran?N2M:N2M_NORAN)|(len&0x3fff))
+
+#define NFC_SEND_CMD_STS(host, time, irq) \
+ NFC_SEND_CMD(host, NFC_CMD_STS(time | irq))
+
+#define NFC_SEND_CMD_RB_IRQ(host, time) \
+ NFC_SEND_CMD(host, NFC_CMD_RBIO_IRQ(time))
+
+/*Cmd Info Macros*/
+#define NFC_CMDFIFO_SIZE(host) ((NFC_INFO_GET(host)>>22)&0x1f)
+#define NFC_CHECEK_RB_TIMEOUT(host) ((NFC_INFO_GET(host)>>27)&0x1)
+#define NFC_FIFO_CUR_CMD(host) ((NFC_INFO_GET(host)>>22)&0x3FFFFF)
+#define NFC_GET_RB_STATUS(host, ce) \
+ (((NFC_INFO_GET(host)>>28)&(~(ce>>10)))&0xf)
+
+
+#define NAND_INFO_DONE(a) (((a)>>31)&1)
+#define NAND_ECC_ENABLE(a) (((a)>>30)&1)
+#define NAND_ECC_CNT(a) (((a)>>24)&0x3f)
+#define NAND_ZERO_CNT(a) (((a)>>16)&0x3f)
+#define NAND_INFO_DATA_2INFO(a) ((a)&0xffff)
+#define NAND_INFO_DATA_1INFO(a) ((a)&0xff)
+
+#define POR_CONFIG READ_CBUS_REG(ASSIST_POR_CONFIG)
+
+#define POC_NAND_CFG (1<<2)
+#define POC_NAND_NO_RB (1<<0)
+#define POC_NAND_ASYNC (1<<7)
+/*nand relate define for hw controller*/
+/*ecc type define*/
+#define NAND_ECC_SOFT_MODE 0x00000000
+#define NAND_ECC_SHORT_MODE 0x00000001
+#define NAND_ECC_BCH9_MODE 0x00000002
+#define NAND_ECC_BCH8_MODE 0x00000003
+#define NAND_ECC_BCH12_MODE 0x00000004
+#define NAND_ECC_BCH16_MODE 0x00000005
+#define NAND_ECC_BCH8_1K_MODE 0x00000006
+#define NAND_ECC_BCH16_1K_MODE 0x00000007
+#define NAND_ECC_BCH24_1K_MODE 0x00000008
+#define NAND_ECC_BCH30_1K_MODE 0x00000009
+#define NAND_ECC_BCH40_1K_MODE 0x0000000a
+#define NAND_ECC_BCH50_1K_MODE 0x0000000b
+#define NAND_ECC_BCH60_1K_MODE 0x0000000c
+
+/*ecc page unit define*/
+#define NAND_ECC_UNIT_SIZE 512
+#define NAND_ECC_UNIT_1KSIZE 1024
+#define NAND_ECC_UNIT_SHORT 384
+
+/*ecc type oob size(bytes) needed*/
+#define NAND_BCH9_ECC_SIZE 15
+#define NAND_BCH8_ECC_SIZE 14
+#define NAND_BCH12_ECC_SIZE 20
+#define NAND_BCH16_ECC_SIZE 26
+#define NAND_BCH8_1K_ECC_SIZE 14
+#define NAND_BCH16_1K_ECC_SIZE 28
+#define NAND_BCH24_1K_ECC_SIZE 42
+#define NAND_BCH30_1K_ECC_SIZE 54
+#define NAND_BCH40_1K_ECC_SIZE 70
+#define NAND_BCH50_1K_ECC_SIZE 88
+#define NAND_BCH60_1K_ECC_SIZE 106
+
+#endif /* __HW_CTRL_H__ */
diff --git a/drivers/mtd/nand/raw/aml_nand/aml_nand.c b/drivers/mtd/nand/raw/aml_nand/aml_nand.c
new file mode 100644
index 0000000..586a743
--- /dev/null
+++ b/drivers/mtd/nand/raw/aml_nand/aml_nand.c
@@ -0,0 +1,2206 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <environment.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <linux/err.h>
+#include <asm/cache.h>
+#include <amlogic/storage.h>
+#include <amlogic/cpu_id.h>
+#include <linux/log2.h>
+#include <dm/pinctrl.h>
+#include <dm/uclass.h>
+#include <dm/device.h>
+
+#include "aml_nand.h"
+#include <time.h> /*test*/
+
+#define aml_nand_debug(a...)
+
+extern int aml_nand_scan_shipped_bbt(struct mtd_info *mtd);
+
+uint8_t nand_boot_flag = 0;
+extern unsigned char pagelist_1ynm_hynix256_mtd[128];
+extern struct hw_controller *controller;
+
+#define NAND_CMD_SANDISK_DSP_OFF 0x25
+#define SANDISK_A19NM_4G 53
+#define INTEL_20NM 60
+
+#define SZ_1M 0x100000
+extern struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
+
+static struct nand_ecclayout aml_nand_uboot_oob = {
+ .eccbytes = 84,
+ .oobfree = {
+ {.offset = 0,
+ .length = 6}}
+};
+
+static struct nand_ecclayout aml_nand_oob_64 = {
+ .eccbytes = 56,
+ .oobfree = {
+ {.offset = 0,
+ .length = 8}}
+};
+
+static struct nand_ecclayout aml_nand_oob_128 = {
+ .eccbytes = 120,
+ .oobfree = {
+ {.offset = 0,
+ .length = 8}}
+};
+
+static struct nand_ecclayout aml_nand_oob_218 = {
+ .eccbytes = 200,
+ .oobfree = {
+ {.offset = 0,
+ .length = 8}}
+};
+
+static struct nand_ecclayout aml_nand_oob_224 = {
+ .eccbytes = 208,
+ .oobfree = {
+ {.offset = 0,
+ .length = 8}}
+};
+
+static struct nand_ecclayout aml_nand_oob_256 = {
+ .eccbytes = 240,
+ .oobfree = {
+ {.offset = 0,
+ .length = 16}}
+};
+
+static struct nand_ecclayout aml_nand_oob_376 = {
+ .eccbytes = 352,
+ .oobfree = {
+ {.offset = 0,
+ .length = 16}}
+};
+
+static struct nand_ecclayout aml_nand_oob_436 = {
+ .eccbytes = 352,
+ .oobfree = {
+ {.offset = 0,
+ .length = 16}}
+};
+
+static struct nand_ecclayout aml_nand_oob_448 = {
+ .eccbytes = 416,
+ .oobfree = {
+ {.offset = 0,
+ .length = 16}}
+};
+
+static struct nand_ecclayout aml_nand_oob_640 = {
+ .eccbytes = 608,
+ .oobfree = {
+ {.offset = 0,
+ .length = 16}}
+};
+
+static struct nand_ecclayout aml_nand_oob_744 = {
+ .eccbytes = 700,
+ .oobfree = {
+ {.offset = 0,
+ .length = 16}}
+};
+
+static struct nand_ecclayout aml_nand_oob_1280 = {
+ .eccbytes = 1200,
+ .oobfree = {
+ {.offset = 0,
+ .length = 32}}
+};
+
+static struct nand_ecclayout aml_nand_oob_1664 = {
+ .eccbytes = 1584,
+ .oobfree = {
+ {.offset = 0,
+ .length = 32}}
+};
+
+void aml_platform_get_user_byte(struct aml_nand_chip *aml_chip,
+ unsigned char *oob_buf, int byte_num)
+{
+ int read_times = 0;
+ unsigned int len = PER_INFO_BYTE / sizeof(unsigned int);
+
+ while (byte_num > 0) {
+ *oob_buf++ = (aml_chip->user_info_buf[read_times*len] & 0xff);
+ byte_num--;
+ if (aml_chip->user_byte_mode == 2) {
+ *oob_buf++ =
+ ((aml_chip->user_info_buf[read_times*len] >> 8) & 0xff);
+ byte_num--;
+ }
+ read_times++;
+ }
+}
+
+void aml_platform_set_user_byte(struct aml_nand_chip *aml_chip,
+ unsigned char *oob_buf, int byte_num)
+{
+ int write_times = 0;
+ unsigned int len = PER_INFO_BYTE/sizeof(unsigned int);
+
+ while (byte_num > 0) {
+ aml_chip->user_info_buf[write_times*len] = *oob_buf++;
+ byte_num--;
+ if (aml_chip->user_byte_mode == 2) {
+ aml_chip->user_info_buf[write_times*len] |=
+ (*oob_buf++ << 8);
+ byte_num--;
+ }
+ write_times++;
+ }
+}
+
+int aml_nand_block_bad_scrub_update_bbt(struct mtd_info *mtd)
+{
+ return 0;
+}
+
+extern struct mtd_partition *get_aml_mtd_partition(void);
+extern int get_aml_partition_count(void);
+extern struct storage_startup_parameter g_ssp;
+static int aml_nand_add_partition(struct aml_nand_chip *aml_chip)
+{
+ struct nand_chip *chip = &aml_chip->chip;
+ struct mtd_info *mtd = &chip->mtd;
+ struct aml_nand_platform *plat = aml_chip->platform;
+ cpu_id_t cpu_id = get_cpu_id();
+#ifdef CONFIG_MTD_PARTITIONS
+ struct mtd_partition *temp_parts = NULL;
+ struct mtd_partition *parts;
+ int nr, i, ret = 0;
+ loff_t adjust_offset = 0;
+ uint64_t part_size = 0;
+ int reserved_part_blk_num = NAND_RSV_BLOCK_NUM;
+ uint64_t fip_part_size = 0;
+#ifndef CONFIG_NOT_SKIP_BAD_BLOCK
+ int phys_erase_shift, error = 0, internal_part_count = 0;
+ uint64_t start_blk = 0, part_blk = 0;
+ loff_t offset;
+
+ phys_erase_shift = fls(mtd->erasesize) - 1;
+#endif
+ if (!strncmp((char*)plat->name, NAND_BOOT_NAME, strlen((const char*)NAND_BOOT_NAME))) {
+ /* boot partition must be set as this because of romboot restrict */
+ parts = kzalloc(sizeof(struct mtd_partition),
+ GFP_KERNEL);
+ if (!parts)
+ return -ENOMEM;
+ parts->name = NAND_BOOT_NAME;
+ parts->offset = 0;
+ parts->size = (mtd->writesize * 1024);
+ nr = 1;
+ } else {
+ /* normal partitions */
+ parts = get_aml_mtd_partition();
+ nr = get_aml_partition_count();
+ adjust_offset = 1024 * mtd->writesize + reserved_part_blk_num * mtd->erasesize;
+
+ if (store_get_device_bootloader_mode() != DISCRETE_BOOTLOADER)
+ goto _COMPAT_BOOTLOADER;
+
+ if ((cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) ||
+ (cpu_id.family_id == MESON_CPU_MAJOR_ID_S4)) {
+ fip_part_size = g_ssp.boot_entry[BOOT_AREA_DEVFIP].size * CONFIG_NAND_TPL_COPY_NUM;
+ adjust_offset = g_ssp.boot_entry[BOOT_AREA_DEVFIP].offset + fip_part_size;
+ internal_part_count = 4;
+ } else {
+ fip_part_size = CONFIG_TPL_SIZE_PER_COPY * CONFIG_NAND_TPL_COPY_NUM;
+ internal_part_count = 1;
+ }
+
+ for (i = 0; i < internal_part_count; i++) {
+ temp_parts = parts + i;
+ if ((cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) ||
+ (cpu_id.family_id == MESON_CPU_MAJOR_ID_S4)) {
+ temp_parts->offset = g_ssp.boot_entry[i + 1].offset;
+ if (i == internal_part_count -1)
+ temp_parts->size = fip_part_size;
+ else
+ temp_parts->size = g_ssp.boot_entry[i + 1].size * g_ssp.boot_bakups;
+ } else {
+ temp_parts->offset = adjust_offset;
+ temp_parts->size = fip_part_size;
+ adjust_offset += fip_part_size;
+ }
+ }
+
+_COMPAT_BOOTLOADER:
+ for (i = internal_part_count; i < nr; i++) {
+ temp_parts = parts + i;
+ if (mtd->size < adjust_offset) {
+ printf("%s %d error : over the nand size!!!\n",
+ __func__, __LINE__);
+ return -ENOMEM;
+ }
+ temp_parts->offset = adjust_offset;
+ part_size = temp_parts->size;
+ if (i == nr - 1)
+ part_size = mtd->size - adjust_offset;
+#ifndef CONFIG_NOT_SKIP_BAD_BLOCK
+ offset = 0;
+ start_blk = 0;
+ part_blk = part_size >> phys_erase_shift;
+
+ do {
+ offset = adjust_offset + start_blk *
+ mtd->erasesize;
+ error = mtd->_block_isbad(mtd, offset);
+ if (error) {
+ pr_info("%s:%d factory bad addr=%llx\n",
+ __func__, __LINE__,
+ (uint64_t)(offset >> phys_erase_shift));
+ if (i != nr - 1) {
+ adjust_offset += mtd->erasesize;
+ continue;
+ }
+ }
+ start_blk++;
+ } while (start_blk < part_blk);
+#endif
+ if (temp_parts->name == NULL) {
+ temp_parts->name = kzalloc(MAX_MTD_PART_NAME_LEN, GFP_KERNEL);
+ if (!temp_parts->name)
+ return -ENOMEM;
+ sprintf((char *)temp_parts->name, "mtd%d", nr);
+ }
+ adjust_offset += part_size;
+ temp_parts->size = adjust_offset - temp_parts->offset;
+ }
+ }
+ ret = add_mtd_partitions(mtd, parts, nr);
+ if (nr == 1)
+ kfree(parts);
+ return ret;
+#else
+ return add_mtd_device(mtd);
+#endif
+}
+
+/*
+void nand_get_chip(void *chip)
+{
+
+ struct aml_nand_chip *aml_chip = (struct aml_nand_chip *)chip;
+ struct hw_controller *controller = aml_chip->controller;
+ int ret = 0;
+
+ ret = pinctrl_select_state(controller->device, "default");
+ if (ret) {
+ printf("ERROR get pinmux failed\n");
+ }
+ return;
+}
+*/
+
+static void inline nand_release_chip(void)
+{
+ NFC_SEND_CMD_STANDBY(controller, 5);
+
+ return;
+}
+
+static void aml_nand_select_chip(struct mtd_info *mtd, int chipnr)
+{
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+
+ switch (chipnr) {
+ case -1:
+ nand_release_chip();
+ break;
+ case 0:
+ //nand_get_chip(aml_chip);
+ aml_chip->aml_nand_select_chip(aml_chip, chipnr);
+ break;
+ case 1:
+ case 2:
+ case 3:
+ aml_chip->aml_nand_select_chip(aml_chip, chipnr);
+ break;
+
+ default:
+ BUG();
+ }
+ return;
+}
+
+void aml_platform_cmd_ctrl(struct aml_nand_chip *aml_chip,
+ int cmd, unsigned int ctrl)
+{
+ if (cmd == NAND_CMD_NONE)
+ return;
+
+ if (ctrl & NAND_CLE)
+ cmd=NFC_CMD_CLE(controller->chip_selected, cmd);
+ else
+ cmd=NFC_CMD_ALE(controller->chip_selected, cmd);
+
+ NFC_SEND_CMD(controller, cmd);
+}
+
+int aml_platform_wait_devready(struct aml_nand_chip *aml_chip, int chipnr)
+{
+ struct nand_chip *chip = &aml_chip->chip;
+ struct mtd_info *mtd = &chip->mtd;
+ unsigned time_out_cnt = 0;
+ int status;
+
+ /* wait until command is processed or timeout occures */
+ aml_chip->aml_nand_select_chip(aml_chip, chipnr);
+
+ NFC_SEND_CMD_IDLE(controller, 0);
+ NFC_SEND_CMD_IDLE(controller, 0);
+ while (NFC_CMDFIFO_SIZE(controller) > 0);
+
+ if (aml_chip->ops_mode & AML_CHIP_NONE_RB) {
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_STATUS, -1, -1, chipnr);
+ udelay(2);
+ NFC_SEND_CMD(controller, controller->chip_selected | IDLE | 0);
+ NFC_SEND_CMD(controller, controller->chip_selected | IDLE | 0);
+ while (NFC_CMDFIFO_SIZE(controller) > 0) ;
+
+ do {
+ status = (int)chip->read_byte(mtd);
+ if (status & NAND_STATUS_READY)
+ break;
+ udelay(1);
+ } while(time_out_cnt++ <= 0x1000); /*10ms max*/
+
+ if (time_out_cnt > 0x1000)
+ return 0;
+ } else {
+ do {
+ if (chip->dev_ready(mtd))
+ break;
+ } while(time_out_cnt++ <= 0x40000);
+
+ if (time_out_cnt > 0x40000)
+ return 0;
+ }
+ return 1;
+}
+
+void aml_nand_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl)
+{
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+
+ aml_chip->aml_nand_cmd_ctrl(aml_chip, cmd, ctrl);
+}
+
+int aml_nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
+{
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+ int status[MAX_CHIP_NUM], i = 0, time_cnt = 0;
+ struct aml_nand_platform *plat = aml_chip->platform;
+ int read_status =0;
+ /* Apply this short delay always to ensure that we do wait tWB in
+ * any case on any machine. */
+ ndelay(100);
+ /*SET_CBUS_REG_MASK(PREG_PAD_GPIO3_O, 1 << 11);*/
+ for (i = 0; i < controller->chip_num; i++) {
+ if (aml_chip->valid_chip[i]) {
+ /*active ce for operation chip and send cmd*/
+ aml_chip->aml_nand_select_chip(aml_chip, i);
+
+ NFC_SEND_CMD(controller,
+ controller->chip_selected | IDLE | 0);
+ NFC_SEND_CMD(controller,
+ controller->chip_selected | IDLE | 0);
+ while (NFC_CMDFIFO_SIZE(controller)>0) ;
+
+ /*if ((state == FL_ERASING)
+ && (chip->options & NAND_IS_AND))
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_STATUS_MULTI, -1, -1, i);
+ else*/
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_STATUS, -1, -1, i);
+
+ NFC_SEND_CMD(controller,
+ controller->chip_selected | IDLE | 0);
+ NFC_SEND_CMD(controller,
+ controller->chip_selected | IDLE | 0);
+ while (NFC_CMDFIFO_SIZE(controller)>0) ;
+
+ time_cnt = 0;
+retry_status:
+ while (time_cnt++ < 0x40000) {
+ if (chip->dev_ready) {
+ if (chip->dev_ready(mtd))
+ break;
+ udelay(2);
+ } else {
+ /*if(time_cnt == 1)*/
+ udelay(2);
+ if (chip->read_byte(mtd) & NAND_STATUS_READY)
+ break;
+ /*aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_STATUS, -1, -1, i);
+ udelay(50);*/
+
+ }
+ /*udelay(200);*/
+ }
+ status[i] = (int)chip->read_byte(mtd);
+ /*printk("s:%x\n", status[i]);*/
+ if ((read_status++ < 3) && (!(status[i] & NAND_STATUS_READY))) {
+ printk("after wirte,read %d status =%d fail\n",
+ read_status,status[i]);
+ goto retry_status;
+ }
+ status[0] |= status[i];
+ }
+ }
+ if (!strncmp((char*)plat->name,
+ NAND_BOOT_NAME, strlen((const char*)NAND_BOOT_NAME)))
+ status[0] = 0xe0;
+
+ return status[0];
+}
+
+/*
+ * CONFIG_SYS_NAND_RESET_CNT is used as a timeout mechanism when resetting
+ * a flash. NAND flash is initialized prior to interrupts so standard timers
+ * can't be used. CONFIG_SYS_NAND_RESET_CNT should be set to a value
+ * which is greater than (max NAND reset time / NAND status read time).
+ * A conservative default of 200000 (500 us / 25 ns) is used as a default.
+ */
+#ifndef CONFIG_SYS_NAND_RESET_CNT
+#define CONFIG_SYS_NAND_RESET_CNT 200000
+#endif
+void aml_nand_base_command(struct aml_nand_chip *aml_chip,
+ unsigned command, int column, int page_addr, int chipnr)
+{
+ struct nand_chip *chip = &aml_chip->chip;
+ struct mtd_info *mtd = &chip->mtd;
+ unsigned command_temp;
+ unsigned pages_per_blk_shift, plane_page_addr = 0, plane_blk_addr = 0;
+
+ pages_per_blk_shift = (chip->phys_erase_shift - chip->page_shift);
+ uint32_t rst_sts_cnt = CONFIG_SYS_NAND_RESET_CNT;
+ if (page_addr != -1) {
+ page_addr /= aml_chip->plane_num;
+ plane_page_addr =(page_addr & ((1 << pages_per_blk_shift) - 1));
+ plane_blk_addr = (page_addr >> pages_per_blk_shift);
+ plane_blk_addr = (plane_blk_addr << 1);
+ }
+
+ if (aml_chip->plane_num == 2) {
+ switch (command) {
+ case NAND_CMD_READ0:
+ if ((aml_chip->mfr_type == NAND_MFR_MICRON)
+ || (aml_chip->mfr_type == NAND_MFR_INTEL))
+ command_temp = command;
+ else {
+ command_temp =
+ NAND_CMD_TWOPLANE_PREVIOS_READ;
+ column = -1;
+ }
+ plane_page_addr |=
+ (plane_blk_addr << pages_per_blk_shift);
+ break;
+
+ case NAND_CMD_TWOPLANE_READ1:
+ command_temp = NAND_CMD_READ0;
+ if ((aml_chip->mfr_type == NAND_MFR_MICRON)
+ || (aml_chip->mfr_type == NAND_MFR_INTEL))
+ /*plane_page_addr |=
+ ((plane_blk_addr + 1) << 8);*/
+ return;
+ else
+ plane_page_addr |=
+ (plane_blk_addr << pages_per_blk_shift);
+ break;
+
+ case NAND_CMD_TWOPLANE_READ2:
+ if ((aml_chip->mfr_type == NAND_MFR_MICRON)
+ || (aml_chip->mfr_type == NAND_MFR_INTEL))
+ command_temp =
+ NAND_CMD_PLANE2_READ_START;
+ else
+ command_temp = NAND_CMD_READ0;
+ plane_page_addr |=
+ ((plane_blk_addr + 1) << pages_per_blk_shift);
+ break;
+
+ case NAND_CMD_SEQIN:
+ command_temp = command;
+ plane_page_addr |=
+ (plane_blk_addr << pages_per_blk_shift);
+ break;
+
+ case NAND_CMD_TWOPLANE_WRITE2:
+ if ((aml_chip->mfr_type == NAND_MFR_HYNIX)
+ || (aml_chip->mfr_type == NAND_MFR_SAMSUNG))
+ command_temp = command;
+ else
+ command_temp =
+ NAND_CMD_TWOPLANE_WRITE2_MICRO;
+ plane_page_addr |=
+ ((plane_blk_addr + 1) << pages_per_blk_shift);
+ break;
+
+ case NAND_CMD_ERASE1:
+ command_temp = command;
+ plane_page_addr |=
+ (plane_blk_addr << pages_per_blk_shift);
+ break;
+
+ case NAND_CMD_MULTI_CHIP_STATUS:
+ command_temp = command;
+ plane_page_addr |=
+ (plane_blk_addr << pages_per_blk_shift);
+ break;
+
+ default:
+ command_temp = command;
+ break;
+
+ }
+ chip->cmd_ctrl(mtd,
+ command_temp & 0xff,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+
+ /*
+ if ((command_temp == NAND_CMD_SEQIN)
+ || (command_temp == NAND_CMD_TWOPLANE_WRITE2)
+ || (command_temp == NAND_CMD_READ0))
+ printk("plane_page_addr:%x plane_blk_addr:%x cmd:%x\n",
+ plane_page_addr, plane_blk_addr, command);
+ */
+
+ if (column != -1 || page_addr != -1) {
+ int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
+ /* Serially input address */
+ if (column != -1) {
+ /* Adjust columns for 16 bit buswidth */
+ if (chip->options & NAND_BUSWIDTH_16 &&
+ !nand_opcode_8bits(command))
+ column >>= 1;
+ chip->cmd_ctrl(mtd, column, ctrl);
+ ctrl &= ~NAND_CTRL_CHANGE;
+ if (!nand_opcode_8bits(command))
+ chip->cmd_ctrl(mtd, column >> 8, ctrl);
+ }
+ if (page_addr != -1) {
+ chip->cmd_ctrl(mtd, plane_page_addr, ctrl);
+ chip->cmd_ctrl(mtd,
+ plane_page_addr >> 8, NAND_NCE | NAND_ALE);
+ /* One more address cycle for devices > 128MiB*/
+ if (chip->chipsize > (128 << 20))
+ chip->cmd_ctrl(mtd,
+ plane_page_addr >> 16, NAND_NCE | NAND_ALE);
+ }
+ }
+
+ switch (command) {
+ case NAND_CMD_READ0:
+ plane_page_addr =
+ page_addr % (1 << pages_per_blk_shift);
+
+ if ((aml_chip->mfr_type == NAND_MFR_MICRON)
+ || (aml_chip->mfr_type == NAND_MFR_INTEL)) {
+ plane_page_addr |=
+ ((plane_blk_addr + 1) << pages_per_blk_shift);
+ command_temp = command;
+ chip->cmd_ctrl(mtd,
+ command_temp & 0xff,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ } else {
+ command_temp =
+ NAND_CMD_TWOPLANE_PREVIOS_READ;
+ column = -1;
+ plane_page_addr |=
+ ((plane_blk_addr + 1) << pages_per_blk_shift);
+ chip->cmd_ctrl(mtd,
+ command_temp & 0xff,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ }
+
+ break;
+
+ case NAND_CMD_TWOPLANE_READ1:
+ if ((aml_chip->mfr_type == NAND_MFR_MICRON)
+ || (aml_chip->mfr_type == NAND_MFR_INTEL)) {
+ page_addr = -1;
+ column = -1;
+ } else {
+ command_temp = NAND_CMD_RNDOUT;
+ page_addr = -1;
+ chip->cmd_ctrl(mtd,
+ command_temp & 0xff,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ }
+ break;
+
+ case NAND_CMD_TWOPLANE_READ2:
+ if ((aml_chip->mfr_type == NAND_MFR_MICRON)
+ || (aml_chip->mfr_type == NAND_MFR_INTEL)) {
+ page_addr = -1;
+ column = -1;
+ } else {
+ command_temp = NAND_CMD_RNDOUT;
+ page_addr = -1;
+ chip->cmd_ctrl(mtd,
+ command_temp & 0xff,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ }
+ break;
+
+ case NAND_CMD_ERASE1:
+ if ((aml_chip->mfr_type == NAND_MFR_MICRON)
+ || (aml_chip->mfr_type == NAND_MFR_INTEL)) {
+ command_temp = NAND_CMD_ERASE1_END;
+ chip->cmd_ctrl(mtd,
+ command_temp & 0xff,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ aml_chip->aml_nand_wait_devready(aml_chip,
+ chipnr);
+ }
+
+ command_temp = command;
+ chip->cmd_ctrl(mtd,
+ command_temp & 0xff,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ plane_page_addr =
+ page_addr % (1 << pages_per_blk_shift);
+ plane_page_addr |=
+ ((plane_blk_addr + 1) << pages_per_blk_shift);
+ break;
+
+ default:
+ column = -1;
+ page_addr = -1;
+ break;
+ }
+
+ if (column != -1 || page_addr != -1) {
+ int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
+
+ /* Serially input address */
+ if (column != -1) {
+ /* Adjust columns for 16 bit buswidth */
+ if (chip->options & NAND_BUSWIDTH_16 &&
+ !nand_opcode_8bits(command))
+ column >>= 1;
+ chip->cmd_ctrl(mtd, column, ctrl);
+ ctrl &= ~NAND_CTRL_CHANGE;
+ if (!nand_opcode_8bits(command))
+ chip->cmd_ctrl(mtd, column >> 8, ctrl);
+ }
+ if (page_addr != -1) {
+ /*plane_page_addr |=
+ (1 << (pages_per_blk_shift + 1));
+ BUG_ON((plane_page_addr & 0x7FF) == 0);*/
+
+ chip->cmd_ctrl(mtd, plane_page_addr, ctrl);
+ chip->cmd_ctrl(mtd, plane_page_addr >> 8,
+ NAND_NCE | NAND_ALE);
+ /* One more address cycle for devices > 128MiB*/
+ if (chip->chipsize > (128 << 20))
+ chip->cmd_ctrl(mtd,
+ plane_page_addr >> 16, NAND_NCE | NAND_ALE);
+ }
+ }
+
+ if ((command == NAND_CMD_RNDOUT)
+ || (command == NAND_CMD_TWOPLANE_READ2))
+ chip->cmd_ctrl(mtd,
+ NAND_CMD_RNDOUTSTART,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ else if ((command == NAND_CMD_TWOPLANE_READ1))
+ chip->cmd_ctrl(mtd,
+ NAND_CMD_RNDOUTSTART,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+
+ else if (command == NAND_CMD_READ0)
+ chip->cmd_ctrl(mtd,
+ NAND_CMD_READSTART,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+
+ chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ } else {
+ chip->cmd_ctrl(mtd,
+ command & 0xff,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+
+ if (column != -1 || page_addr != -1) {
+ int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
+
+ /* Serially input address */
+ if (column != -1) {
+ /* Adjust columns for 16 bit buswidth */
+ if (chip->options & NAND_BUSWIDTH_16 &&
+ !nand_opcode_8bits(command))
+ column >>= 1;
+ chip->cmd_ctrl(mtd, column, ctrl);
+ ctrl &= ~NAND_CTRL_CHANGE;
+ /* Only output a single addr
+ * cycle for 8bits opcodes.
+ */
+ if (!nand_opcode_8bits(command))
+ chip->cmd_ctrl(mtd, column >> 8, ctrl);
+ }
+ if (page_addr != -1) {
+
+ chip->cmd_ctrl(mtd, page_addr, ctrl);
+ chip->cmd_ctrl(mtd, page_addr >> 8,
+ NAND_NCE | NAND_ALE);
+ /* One more address cycle for devices > 128MiB*/
+ if (chip->chipsize > (128 << 20))
+ chip->cmd_ctrl(mtd,
+ page_addr >> 16, NAND_NCE | NAND_ALE);
+ }
+ }
+ if (command == NAND_CMD_RNDOUT)
+ chip->cmd_ctrl(mtd,
+ NAND_CMD_RNDOUTSTART,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ else if (command == NAND_CMD_READ0)
+ chip->cmd_ctrl(mtd,
+ NAND_CMD_READSTART,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+
+ chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ }
+
+ /*
+ * program and erase have their own busy handlers
+ * status, sequential in, and deplete1 need no delay
+ */
+ switch (command) {
+
+ case NAND_CMD_CACHEDPROG:
+ case NAND_CMD_PAGEPROG:
+ case NAND_CMD_ERASE1:
+ case NAND_CMD_ERASE2:
+ case NAND_CMD_SEQIN:
+ case NAND_CMD_RNDIN:
+ case NAND_CMD_STATUS:
+ case NAND_CMD_DEPLETE1:
+ return;
+
+ /*
+ * read error status commands require only a short delay
+ */
+ case NAND_CMD_STATUS_ERROR:
+ case NAND_CMD_STATUS_ERROR0:
+ case NAND_CMD_STATUS_ERROR1:
+ case NAND_CMD_STATUS_ERROR2:
+ case NAND_CMD_STATUS_ERROR3:
+ udelay(chip->chip_delay);
+ return;
+
+ case NAND_CMD_RESET:
+ if (!aml_chip->aml_nand_wait_devready(aml_chip, chipnr))
+ printk ("couldn`t found selected chip: %d ready\n",
+ chipnr);
+ chip->cmd_ctrl(mtd,
+ NAND_CMD_STATUS,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ chip->cmd_ctrl(mtd,
+ NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
+ while (!(chip->read_byte(mtd) & NAND_STATUS_READY) &&
+ (rst_sts_cnt--));
+ return;
+
+ default:
+ /*
+ * If we don't have access to the busy pin, we apply the given
+ * command delay
+ */
+ break;
+ }
+
+ /* Apply this short delay always to ensure that we do wait tWB in
+ * any case on any machine. */
+ ndelay(100);
+}
+
+void aml_nand_command(struct mtd_info *mtd,
+ unsigned command, int column, int page_addr)
+{
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+ struct nand_chip *chip = &aml_chip->chip;
+ int i = 0, valid_page_num = 1;
+
+ if (page_addr != -1) {
+ valid_page_num = (mtd->writesize >> chip->page_shift);
+ valid_page_num /= aml_chip->plane_num;
+ aml_chip->page_addr = page_addr / valid_page_num;
+ if (unlikely(aml_chip->page_addr >= aml_chip->internal_page_nums)) {
+ /*internal_chip =
+ aml_chip->page_addr / aml_chip->internal_page_nums;*/
+ aml_chip->page_addr -= aml_chip->internal_page_nums;
+ aml_chip->page_addr |=
+ (1 << aml_chip->internal_chip_shift)*aml_chip->internal_chipnr;
+ }
+ } else
+ aml_chip->page_addr = page_addr;
+
+ /* Emulate NAND_CMD_READOOB */
+ if (command == NAND_CMD_READOOB) {
+ command = NAND_CMD_READ0;
+ aml_chip->aml_nand_wait_devready(aml_chip, 0);
+ aml_chip->aml_nand_command(aml_chip, command,
+ column, aml_chip->page_addr, 0);
+ return;
+ }
+ if (command == NAND_CMD_PAGEPROG)
+ return;
+
+ /*if (command == NAND_CMD_SEQIN) {
+ aml_chip->aml_nand_select_chip(aml_chip, 0);
+ aml_chip->aml_nand_command(aml_chip,
+ command, column, page_addr, 0);
+ return;
+ }*/
+
+ for (i=0; i<controller->chip_num; i++) {
+ if (aml_chip->valid_chip[i]) {
+ /*active ce for operation chip and send cmd*/
+ aml_chip->aml_nand_wait_devready(aml_chip, i);
+ aml_chip->aml_nand_command(aml_chip,
+ command, column, aml_chip->page_addr, i);
+ }
+ }
+
+ return;
+}
+
+int aml_nand_erase_cmd(struct mtd_info *mtd, int page)
+{
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+ struct nand_chip *chip = mtd->priv;
+ unsigned pages_per_blk_shift;
+ unsigned vt_page_num, internal_chipnr = 1, page_addr, valid_page_num;
+ unsigned i = 0, j = 0;
+ unsigned block_addr;
+
+ pages_per_blk_shift = (chip->phys_erase_shift - chip->page_shift);
+
+ vt_page_num = (mtd->writesize / (1 << chip->page_shift));
+ vt_page_num *= (1 << pages_per_blk_shift);
+ /* printk("%s() page 0x%x\n", __func__, page);*/
+ if (page % vt_page_num)
+ return 1;
+ /* fixme, skip bootloader */
+ if (page < 1024)
+ return 0;
+ /* Send commands to erase a block */
+ valid_page_num = (mtd->writesize >> chip->page_shift);
+
+ block_addr = ((page / valid_page_num) >> pages_per_blk_shift);
+
+ if (meson_rsv_erase_protect(aml_chip->rsv, block_addr) == -1) {
+ printf("%s blk 0x%x is protected\n", __func__, block_addr);
+ return 1;
+ }
+
+ valid_page_num /= aml_chip->plane_num;
+
+ aml_chip->page_addr = page / valid_page_num;
+ if (unlikely(aml_chip->page_addr >= aml_chip->internal_page_nums)) {
+ //internal_chipnr =
+ // aml_chip->page_addr / aml_chip->internal_page_nums;
+ aml_chip->page_addr -= aml_chip->internal_page_nums;
+ aml_chip->page_addr |=
+ (1 << aml_chip->internal_chip_shift) *aml_chip->internal_chipnr;
+ }
+
+ if (unlikely(aml_chip->ops_mode & AML_INTERLEAVING_MODE))
+ internal_chipnr = aml_chip->internal_chipnr;
+ else
+ internal_chipnr = 1;
+
+ for (i=0; i<controller->chip_num; i++) {
+ if (aml_chip->valid_chip[i]) {
+ aml_chip->aml_nand_select_chip(aml_chip, i);
+ page_addr = aml_chip->page_addr;
+ for (j=0; j<internal_chipnr; j++) {
+ if (j > 0) {
+ page_addr = aml_chip->page_addr;
+ page_addr |=
+ (1 << aml_chip->internal_chip_shift) *j;
+ }
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_ERASE1, -1, page_addr, i);
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_ERASE2, -1, -1, i);
+ }
+ }
+ }
+ return 0;
+}
+
+void aml_nand_dma_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
+{
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+
+ aml_chip->aml_nand_dma_read(aml_chip, buf, len, 0);
+}
+
+void aml_nand_dma_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
+{
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+
+ aml_chip->aml_nand_dma_write(aml_chip, (unsigned char *)buf, len, 0);
+}
+
+int aml_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
+ uint8_t *buf, int oob_required, int page)
+{
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+ unsigned nand_page_size = aml_chip->page_size;
+ unsigned nand_oob_size = aml_chip->oob_size;
+ uint8_t *oob_buf = chip->oob_poi;
+ int i, error = 0, j = 0, page_addr, internal_chipnr = 1;
+
+ if (aml_chip->ops_mode & AML_INTERLEAVING_MODE)
+ internal_chipnr = aml_chip->internal_chipnr;
+
+ for (i = 0; i < controller->chip_num; i++) {
+ if (aml_chip->valid_chip[i]) {
+ page_addr = aml_chip->page_addr;
+ for (j = 0; j < internal_chipnr; j++) {
+ if (j > 0) {
+ page_addr = aml_chip->page_addr;
+ page_addr |=
+ (1 << aml_chip->internal_chip_shift) * j;
+ aml_chip->aml_nand_select_chip(aml_chip,
+ i);
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_READ0, 0, page_addr,i);
+ }
+
+ if (!aml_chip->aml_nand_wait_devready(aml_chip,
+ i)) {
+ printk ("didn't found selected chip:%dready\n",
+ i);
+ error = -EBUSY;
+ goto exit;
+ }
+
+ if (aml_chip->ops_mode & AML_CHIP_NONE_RB)
+ chip->cmd_ctrl(mtd,
+ NAND_CMD_READ0 & 0xff,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ if (aml_chip->plane_num == 2) {
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_TWOPLANE_READ1,
+ 0x00, page_addr, i);
+ chip->read_buf(mtd,
+ aml_chip->aml_nand_data_buf,
+ (nand_page_size+nand_oob_size));
+ memcpy(buf, aml_chip->aml_nand_data_buf,
+ (nand_page_size+nand_oob_size));
+ memcpy(oob_buf,
+ aml_chip->aml_nand_data_buf + nand_page_size,
+ nand_oob_size);
+
+ oob_buf += nand_oob_size;
+ buf += (nand_page_size + nand_oob_size);
+
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_TWOPLANE_READ2,
+ 0x00, page_addr, i);
+ chip->read_buf(mtd,
+ aml_chip->aml_nand_data_buf,
+ nand_page_size + nand_oob_size);
+ memcpy(buf, aml_chip->aml_nand_data_buf,
+ nand_page_size + nand_oob_size);
+ memcpy(oob_buf,
+ aml_chip->aml_nand_data_buf + nand_page_size,
+ nand_oob_size);
+
+ oob_buf += nand_oob_size;
+ buf += (nand_page_size + nand_oob_size);
+ } else if (aml_chip->plane_num == 1) {
+ chip->read_buf(mtd,
+ aml_chip->aml_nand_data_buf,
+ nand_page_size + nand_oob_size);
+ memcpy(buf, aml_chip->aml_nand_data_buf,
+ nand_page_size);
+ memcpy(oob_buf,
+ aml_chip->aml_nand_data_buf + nand_page_size,
+ nand_oob_size);
+ oob_buf += nand_oob_size;
+ buf += nand_page_size;
+ } else {
+ error = -ENODEV;
+ goto exit;
+ }
+ }
+ }
+ }
+
+exit:
+ return error;
+}
+
+int aml_nand_write_page_raw(struct mtd_info *mtd,
+ struct nand_chip *chip, const uint8_t *buf, int oob_required,
+ int page)
+{
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+ unsigned nand_page_size = aml_chip->page_size;
+ unsigned nand_oob_size = aml_chip->oob_size;
+ uint8_t *oob_buf = chip->oob_poi;
+ int i, error = 0, j = 0, page_addr, internal_chipnr = 1;
+
+ if (aml_chip->ops_mode & AML_INTERLEAVING_MODE)
+ internal_chipnr = aml_chip->internal_chipnr;
+
+ for (i=0; i<controller->chip_num; i++) {
+ if (aml_chip->valid_chip[i]) {
+ aml_chip->aml_nand_select_chip(aml_chip, i);
+ page_addr = aml_chip->page_addr;
+ for (j = 0; j < internal_chipnr; j++) {
+ if (j > 0) {
+ page_addr = aml_chip->page_addr;
+ page_addr |=
+ (1 << aml_chip->internal_chip_shift) *j;
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_SEQIN, 0, page_addr, i);
+ }
+
+ if (aml_chip->plane_num == 2) {
+ memcpy(aml_chip->aml_nand_data_buf,
+ buf, nand_page_size);
+ memcpy(aml_chip->aml_nand_data_buf + nand_page_size,
+ oob_buf, nand_oob_size);
+ chip->write_buf(mtd,
+ aml_chip->aml_nand_data_buf,
+ nand_page_size + nand_oob_size);
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_DUMMY_PROGRAM, -1, -1, i);
+
+ oob_buf += nand_oob_size;
+ buf += nand_page_size;
+
+ if (!aml_chip->aml_nand_wait_devready(aml_chip, i)) {
+ printk ("didn't found selected chip:%d ready\n",
+ i);
+ error = -EBUSY;
+ goto exit;
+ }
+
+ memcpy(aml_chip->aml_nand_data_buf,
+ buf, nand_page_size);
+ memcpy(aml_chip->aml_nand_data_buf + nand_page_size,
+ oob_buf, nand_oob_size);
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_TWOPLANE_WRITE2, 0x00, page_addr, i);
+ chip->write_buf(mtd, aml_chip->aml_nand_data_buf,
+ (nand_page_size + nand_oob_size));
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_PAGEPROG, -1, -1, i);
+
+ oob_buf += nand_oob_size;
+ buf += nand_page_size;
+ } else if (aml_chip->plane_num == 1) {
+ memcpy(aml_chip->aml_nand_data_buf,
+ buf, nand_page_size);
+ memcpy(aml_chip->aml_nand_data_buf + nand_page_size,
+ oob_buf, nand_oob_size);
+ chip->write_buf(mtd,
+ aml_chip->aml_nand_data_buf,
+ nand_page_size + nand_oob_size);
+ if (chip->cmdfunc == aml_nand_command)
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_PAGEPROG,
+ -1, -1, i);
+
+ oob_buf += nand_oob_size;
+ buf += nand_page_size;
+ } else {
+ error = -ENODEV;
+ goto exit;
+ }
+ }
+ }
+ }
+exit:
+ return error;
+}
+
+int aml_nand_read_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
+{
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+ uint8_t *oob_buf = chip->oob_poi;
+ unsigned nand_page_size = (1 << chip->page_shift);
+ unsigned pages_per_blk_shift;
+ int user_byte_num;
+ int error = 0, i = 0, stat = 0, j = 0, page_addr, internal_chipnr = 1;
+ int ran_mode = aml_chip->ran_mode;
+
+ pages_per_blk_shift = (chip->phys_erase_shift - chip->page_shift);
+ user_byte_num = (((nand_page_size + chip->ecc.size - 1) /chip->ecc.size)
+ * aml_chip->user_byte_mode);
+
+ if (aml_chip->ops_mode & AML_INTERLEAVING_MODE)
+ internal_chipnr = aml_chip->internal_chipnr;
+
+ if (nand_page_size > chip->ecc.steps * chip->ecc.size) {
+ nand_page_size = chip->ecc.steps * chip->ecc.size;
+ user_byte_num = chip->ecc.steps;
+ }
+
+ for (i = 0; i < controller->chip_num; i++) {
+ if (aml_chip->valid_chip[i]) {
+ page_addr = aml_chip->page_addr;
+ for (j = 0; j < internal_chipnr; j++) {
+ if (j > 0) {
+ page_addr = aml_chip->page_addr;
+ page_addr |= (1 << aml_chip->internal_chip_shift) * j;
+ aml_chip->aml_nand_select_chip(aml_chip, i);
+ aml_chip->aml_nand_command(aml_chip, NAND_CMD_READ0,
+ 0, page_addr, i);
+ }
+ if (!aml_chip->aml_nand_wait_devready(aml_chip, i)) {
+ printk ("read couldn`t found selected chip: %d ready\n",
+ i);
+ error = -EBUSY;
+ goto exit;
+ }
+ if (aml_chip->ops_mode & AML_CHIP_NONE_RB)
+ chip->cmd_ctrl(mtd, NAND_CMD_READ0 & 0xff,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ if (aml_chip->plane_num == 2) {
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_TWOPLANE_READ1, 0x00, page_addr, i);
+dma_retry_plane0:
+ error = aml_chip->aml_nand_dma_read(aml_chip,
+ buf, nand_page_size, aml_chip->bch_mode);
+ if (error)
+ goto exit;
+
+ aml_chip->aml_nand_get_user_byte(aml_chip,
+ oob_buf, user_byte_num);
+ stat = aml_chip->aml_nand_hwecc_correct(aml_chip,
+ buf, nand_page_size, oob_buf);
+ if (stat < 0) {
+ if (aml_chip->ran_mode
+ && (aml_chip->zero_cnt < aml_chip->ecc_max)) {
+ memset(buf, 0xff, nand_page_size);
+ memset(oob_buf, 0xff, user_byte_num);
+ goto plane0_ff;
+ }
+
+ if (ran_mode && aml_chip->ran_mode) {
+ aml_chip->ran_mode = 0;
+ ndelay(300);
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_RNDOUT, 0, -1, i);
+ ndelay(500);
+ goto dma_retry_plane0;
+ }
+ memset(buf, 0xff, nand_page_size);
+ memset(oob_buf, 0xff, user_byte_num);
+
+ mtd->ecc_stats.failed++;
+ printk("read ecc pl0 failed at page%d chip%d\n",
+ page_addr, i);
+ } else {
+ if (aml_chip->ecc_cnt_cur > aml_chip->ecc_cnt_limit) {
+ printk("%s %d uncorrect ecc_cnt_cur:%d limit:%d pg:%d,blk:%d chip%d\n",
+ __func__, __LINE__,
+ aml_chip->ecc_cnt_cur, aml_chip->ecc_cnt_limit,
+ page_addr, page_addr >> pages_per_blk_shift, i);
+ mtd->ecc_stats.corrected++;
+ }
+ mtd->ecc_stats.corrected += stat;
+ }
+plane0_ff:
+ aml_chip->ran_mode = ran_mode;
+ oob_buf += user_byte_num;
+ buf += nand_page_size;
+
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_TWOPLANE_READ2, 0x00, page_addr, i);
+dma_retry_plane1:
+ error = aml_chip->aml_nand_dma_read(aml_chip,
+ buf, nand_page_size, aml_chip->bch_mode);
+ if (error)
+ goto exit;
+
+ aml_chip->aml_nand_get_user_byte(aml_chip,
+ oob_buf, user_byte_num);
+ stat = aml_chip->aml_nand_hwecc_correct(aml_chip,
+ buf, nand_page_size, oob_buf);
+ if (stat < 0) {
+ if(aml_chip->ran_mode
+ && (aml_chip->zero_cnt < aml_chip->ecc_max)) {
+ memset(buf, 0xff, nand_page_size);
+ memset(oob_buf, 0xff, user_byte_num);
+ oob_buf += user_byte_num;
+ buf += nand_page_size;
+ continue;
+ }
+
+ if (ran_mode && aml_chip->ran_mode) {
+ aml_chip->ran_mode = 0;
+ ndelay(300);
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_RNDOUT, 0, -1, i);
+ ndelay(500);
+ goto dma_retry_plane1;
+ }
+ memset(buf, 0xff, nand_page_size);
+ memset(oob_buf, 0xff, user_byte_num);
+
+ mtd->ecc_stats.failed++;
+ printk("read ecc pl1 failed at page%d chip%d\n",
+ page_addr, i);
+ } else {
+ if (aml_chip->ecc_cnt_cur > aml_chip->ecc_cnt_limit) {
+ printk("%s %d uncorrect ecc_cnt_cur:%d limit:%d pg:%d blk:%d chip%d\n",
+ __func__, __LINE__,
+ aml_chip->ecc_cnt_cur, aml_chip->ecc_cnt_limit,
+ page_addr, page_addr >> pages_per_blk_shift, i);
+ mtd->ecc_stats.corrected++;
+ }
+ mtd->ecc_stats.corrected += stat;
+ }
+ aml_chip->ran_mode = ran_mode;
+ oob_buf += user_byte_num;
+ buf += nand_page_size;
+
+ } else if (aml_chip->plane_num == 1) {
+ error = aml_chip->aml_nand_dma_read(aml_chip,
+ buf, nand_page_size, aml_chip->bch_mode);
+ if (error)
+ goto exit;
+
+ aml_chip->aml_nand_get_user_byte(aml_chip,
+ oob_buf, user_byte_num);
+ stat = aml_chip->aml_nand_hwecc_correct(aml_chip,
+ buf, nand_page_size, oob_buf);
+ if (stat < 0) {
+ if(aml_chip->ran_mode
+ && (aml_chip->zero_cnt < aml_chip->ecc_max)) {
+ memset(buf, 0xff, nand_page_size);
+ memset(oob_buf, 0xff, user_byte_num);
+ oob_buf += user_byte_num;
+ buf += nand_page_size;
+ continue;
+ }
+ /*memset(buf, 0xff, nand_page_size);*/
+ memset(oob_buf, 0x22, user_byte_num);
+ printk("%s %d read ecc failed here at at page:%d, blk:%d chip[%d]\n",
+ __func__, __LINE__, page_addr,
+ (page_addr >> pages_per_blk_shift), i);
+ mtd->ecc_stats.failed++;
+ } else {
+ aml_chip->ran_mode = ran_mode;
+ mtd->ecc_stats.corrected += stat;
+ }
+ oob_buf += user_byte_num;
+ buf += nand_page_size;
+ } else {
+ error = -ENODEV;
+ goto exit;
+ }
+ }
+ }
+ }
+exit:
+ return error;
+}
+
+int aml_nand_write_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, const uint8_t *buf, int oob_required,
+ int page)
+{
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+ uint8_t *oob_buf = chip->oob_poi;
+ unsigned nand_page_size = (1 << chip->page_shift);
+ int user_byte_num, temp_value;
+ int error = 0, i = 0, j = 0, page_addr, internal_chipnr = 1;
+
+ temp_value = nand_page_size + chip->ecc.size - 1;
+ user_byte_num = (temp_value /chip->ecc.size) * aml_chip->user_byte_mode;
+
+ if (aml_chip->ops_mode & AML_INTERLEAVING_MODE)
+ internal_chipnr = aml_chip->internal_chipnr;
+
+ memset(oob_buf + mtd->oobavail,
+ 0xa5, user_byte_num * (mtd->writesize / nand_page_size));
+
+ for (i = 0; i < controller->chip_num; i++) {
+ if (aml_chip->valid_chip[i]) {
+ page_addr = aml_chip->page_addr;
+ for (j = 0; j < internal_chipnr; j++) {
+ aml_chip->aml_nand_select_chip(aml_chip, i);
+ if (j > 0) {
+ page_addr = aml_chip->page_addr;
+ page_addr |=
+ (1 <<aml_chip->internal_chip_shift) * j;
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_SEQIN, 0, page_addr, i);
+ }
+ if (aml_chip->plane_num == 2) {
+ aml_chip->aml_nand_set_user_byte(aml_chip,
+ oob_buf, user_byte_num);
+ error = aml_chip->aml_nand_dma_write(aml_chip,
+ (unsigned char *)buf,
+ nand_page_size, aml_chip->bch_mode);
+ if (error) {
+ printk("dma write 1 err at page %x\n",
+ page_addr);
+ goto exit;
+ }
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_DUMMY_PROGRAM, -1, -1, i);
+
+ oob_buf += user_byte_num;
+ buf += nand_page_size;
+
+ if (!aml_chip->aml_nand_wait_devready(aml_chip, i)) {
+ printk ("write couldn't found chip:%d ready\n",
+ i);
+ error = -EBUSY;
+ goto exit;
+ }
+
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_TWOPLANE_WRITE2, 0x00, page_addr, i);
+ aml_chip->aml_nand_set_user_byte(aml_chip,
+ oob_buf, user_byte_num);
+ error = aml_chip->aml_nand_dma_write(aml_chip,
+ (u8 *)buf,
+ nand_page_size, aml_chip->bch_mode);
+ if (error) {
+ printk("aml_nand_dma_write 2 err at page %x\n",
+ page_addr);
+ goto exit;
+ }
+ if (aml_chip->cached_prog_status)
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_CACHEDPROG, -1, -1, i);
+ else
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_PAGEPROG, -1, -1, i);
+
+ oob_buf += user_byte_num;
+ buf += nand_page_size;
+ } else if (aml_chip->plane_num == 1) {
+ aml_chip->aml_nand_set_user_byte(aml_chip,
+ oob_buf, user_byte_num);
+ error = aml_chip->aml_nand_dma_write(aml_chip,
+ (unsigned char *)buf,
+ nand_page_size, aml_chip->bch_mode);
+ if (error) {
+ printk("aml_nand_dma_write err at page %x\n",
+ page_addr);
+ goto exit;
+ }
+
+ if (chip->cmdfunc == aml_nand_command) {
+ if (aml_chip->cached_prog_status)
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_CACHEDPROG, -1, -1, i);
+ else
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_PAGEPROG, -1, -1, i);
+ }
+
+ oob_buf += user_byte_num;
+ buf += nand_page_size;
+ }
+ else {
+ error = -ENODEV;
+ goto exit;
+ }
+ }
+ }
+ }
+exit:
+ return error;
+}
+
+int aml_nand_write_page(struct mtd_info *mtd,
+ struct nand_chip *chip, uint32_t offset,
+ int data_len,
+ const uint8_t *buf,
+ int oob_required, int page, int raw)
+{
+ int status;
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
+
+ if (chip->options & NAND_CACHEPRG)
+ aml_chip->cached_prog_status = 1;
+ else
+ aml_chip->cached_prog_status = 0;
+ if (unlikely(raw))
+ chip->ecc.write_page_raw(mtd, chip, buf, 0, 0);
+ else
+ chip->ecc.write_page(mtd, chip, buf, 0, 0);
+
+ if (!(chip->options & NAND_CACHEPRG)) {
+ status = chip->waitfunc(mtd, chip);
+ /*
+ * See if operation failed and additional status checks are
+ * available
+ */
+ if (status & NAND_STATUS_FAIL) {
+ printk("wr page=0x%x, status = 0x%x\n",
+ page,status);
+ return -EIO;
+ }
+ } else
+ status = chip->waitfunc(mtd, chip);
+
+ aml_chip->cached_prog_status = 0;
+ return 0;
+}
+
+int aml_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
+{
+ int32_t page_addr;
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+ unsigned char *nand_buffer = aml_chip->aml_nand_data_buf;
+ int32_t error=0;
+ int oob_required = 1;
+
+ page_addr = page;
+
+ if (chip->cmdfunc == aml_nand_command)
+ chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page_addr);
+ else {
+ aml_chip->aml_nand_select_chip(aml_chip, 0);
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page_addr);
+ }
+
+ error = aml_nand_read_page_hwecc(mtd, chip, nand_buffer, oob_required, page);
+ if (error) {
+ printk("%s, %d,read oob failed\n", __func__, __LINE__);
+ }
+ return error;
+}
+
+int aml_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, int page)
+{
+ printk("our host controller`s structure couldn`t support oob write\n");
+ BUG();
+ return 0;
+}
+
+int aml_nand_block_bad(struct mtd_info *mtd, loff_t ofs)
+{
+ struct nand_chip * chip = mtd->priv;
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+ struct aml_nand_platform *plat = aml_chip->platform;
+ struct mtd_oob_ops aml_oob_ops;
+ int32_t ret=0, read_cnt, mtd_erase_shift, blk_addr, pages_per_blk;
+ loff_t addr;
+
+ if ((!strncmp((char*)plat->name,
+ NAND_BOOT_NAME, strlen((const char*)NAND_BOOT_NAME))))
+ return 0;
+
+ mtd_erase_shift = fls(mtd->erasesize) - 1;
+ blk_addr = (int)(ofs >> mtd_erase_shift);
+ if (aml_chip->block_status != NULL) {
+ if (aml_chip->block_status[blk_addr] == NAND_BLOCK_BAD) {
+ printk(" NAND bbt detect Bad block at %llx \n",
+ (uint64_t)ofs);
+ return EFAULT;
+ }
+ if (aml_chip->block_status[blk_addr] == NAND_FACTORY_BAD) {
+ printk(" NAND bbt detect factory Bad block at %llx \n",
+ (uint64_t)ofs);
+ return FACTORY_BAD_BLOCK_ERROR; //159 EFAULT
+ } else if (aml_chip->block_status[blk_addr] ==NAND_BLOCK_GOOD)
+ return 0;
+ }
+ chip->pagebuf = -1;
+ pages_per_blk = (1 << (chip->phys_erase_shift - chip->page_shift));
+
+ aml_oob_ops.mode = MTD_OPS_AUTO_OOB;
+ aml_oob_ops.len = mtd->writesize;
+ aml_oob_ops.ooblen = mtd->oobavail;
+ aml_oob_ops.ooboffs = chip->ecc.layout->oobfree[0].offset;
+ aml_oob_ops.datbuf = chip->buffers->databuf;
+ aml_oob_ops.oobbuf = chip->oob_poi;
+ for (read_cnt = 0; read_cnt < 2; read_cnt++) {
+ addr =
+ ofs + (pages_per_blk - 1) * read_cnt * mtd->writesize;
+ ret = mtd->_read_oob(mtd, addr, &aml_oob_ops);
+ if (ret == -EUCLEAN)
+ ret = 0;
+ if (ret < 0) {
+ printk("1 NAND detect Bad block:%llx\n",
+ (uint64_t)addr);
+ return EFAULT;
+ }
+ if (aml_oob_ops.oobbuf[chip->badblockpos] == 0xFF)
+ continue;
+ if (aml_oob_ops.oobbuf[chip->badblockpos] == 0) {
+ memset(aml_chip->aml_nand_data_buf,
+ 0, aml_oob_ops.ooblen);
+ if (!memcmp(aml_chip->aml_nand_data_buf,
+ aml_oob_ops.oobbuf, aml_oob_ops.ooblen)) {
+ printk("2 NAND detect Bad block:%llx\n",
+ (uint64_t)addr);
+ return EFAULT;
+ }
+ }
+ }
+
+
+ return 0;
+}
+
+extern int meson_rsv_bbt_write(u_char *source, size_t size);
+int aml_nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
+{
+ struct nand_chip * chip = mtd->priv;
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+ struct mtd_oob_ops aml_oob_ops;
+ int blk_addr, mtd_erase_shift;
+ int8_t *buf = NULL;
+
+ mtd_erase_shift = fls(mtd->erasesize) - 1;
+ blk_addr = (int)(ofs >> mtd_erase_shift);
+ if (aml_chip->block_status != NULL) {
+ if ((aml_chip->block_status[blk_addr] == NAND_BLOCK_BAD)
+ ||(aml_chip->block_status[blk_addr] == NAND_FACTORY_BAD)) {
+ goto mark_bad;
+
+ } else if (aml_chip->block_status[blk_addr] ==NAND_BLOCK_GOOD) {
+ aml_chip->block_status[blk_addr] = NAND_BLOCK_BAD;
+ buf = aml_chip->block_status;
+ meson_rsv_bbt_write((u_char *)buf, aml_chip->rsv->bbt->size);
+ }
+ }
+mark_bad:
+ /*no erase here, fixit*/
+ aml_oob_ops.mode = MTD_OPS_AUTO_OOB;
+ aml_oob_ops.len = mtd->writesize;
+ aml_oob_ops.ooblen = mtd->oobavail;
+ aml_oob_ops.ooboffs = chip->ecc.layout->oobfree[0].offset;
+ aml_oob_ops.datbuf = chip->buffers->databuf;
+ aml_oob_ops.oobbuf = chip->oob_poi;
+ chip->pagebuf = -1;
+
+ memset((unsigned char *)aml_oob_ops.datbuf, 0x0, mtd->writesize);
+ memset((unsigned char *)aml_oob_ops.oobbuf, 0x0, aml_oob_ops.ooblen);
+
+ return mtd->_write_oob(mtd, ofs, &aml_oob_ops);
+}
+
+static uint8_t aml_platform_read_byte(struct mtd_info *mtd)
+{
+ uint8_t status;
+
+ NFC_SEND_CMD_DRD(controller, controller->chip_selected, 0);
+ NFC_SEND_CMD_IDLE(controller, NAND_TWB_TIME_CYCLE);
+
+ NFC_SEND_CMD_IDLE(controller, 0);
+ NFC_SEND_CMD_IDLE(controller, 0);
+
+ while (NFC_CMDFIFO_SIZE(controller) > 0) ;
+ status = amlnf_read_reg32(controller->reg_base + P_NAND_BUF);
+ return status;
+}
+
+void aml_platform_write_byte(struct aml_nand_chip *aml_chip, uint8_t data)
+{
+ NFC_SEND_CMD_IDLE(controller, NAND_TWB_TIME_CYCLE);
+ NFC_SEND_CMD_DWR(controller, controller->chip_selected, data);
+ NFC_SEND_CMD_IDLE(controller, NAND_TWB_TIME_CYCLE);
+
+ NFC_SEND_CMD_IDLE(controller, 0);
+ NFC_SEND_CMD_IDLE(controller, 0);
+
+ while (NFC_CMDFIFO_SIZE(controller) > 0)
+ ;
+}
+
+extern struct aml_pre_scan *pre_scan;
+int aml_nand_init(struct aml_nand_chip *aml_chip)
+{
+ struct aml_nand_platform *plat = aml_chip->platform;
+ struct nand_chip *chip = &aml_chip->chip;
+ struct mtd_info *mtd = &chip->mtd;
+ int err = 0, i = 0;
+ int oobmul;
+ unsigned valid_chip_num = 0;
+ struct nand_oobfree *oobfree = NULL;
+ cpu_id_t cpu_id = get_cpu_id();
+
+ chip->ecc.layout = &aml_nand_oob_64;
+ chip->select_chip = aml_nand_select_chip;
+ chip->cmd_ctrl = aml_nand_cmd_ctrl;
+ chip->read_byte = aml_platform_read_byte;
+
+ controller->chip_num = plat->platform_nand_data.chip.nr_chips;
+ if (controller->chip_num > MAX_CHIP_NUM) {
+ err = -ENXIO;
+ goto exit_error;
+ }
+
+ for (i=0; i<controller->chip_num; i++)
+ aml_chip->valid_chip[i] = 1;
+
+ /*use NO RB mode to detect nand chip num*/
+ aml_chip->ops_mode |= AML_CHIP_NONE_RB;
+ chip->chip_delay = 100;
+ aml_chip->aml_nand_hw_init(aml_chip);
+ aml_chip->toggle_mode =0;
+ aml_chip->bch_info = NAND_ECC_BCH60_1K;
+ if ((cpu_id.family_id == MESON_CPU_MAJOR_ID_AXG) ||
+ (cpu_id.family_id == MESON_CPU_MAJOR_ID_TXHD)||
+ (cpu_id.family_id == MESON_CPU_MAJOR_ID_C1) ||
+ (cpu_id.family_id == MESON_CPU_MAJOR_ID_C2) ||
+ (cpu_id.family_id == MESON_CPU_MAJOR_ID_S4))
+ aml_chip->bch_info = NAND_ECC_BCH8_1K;
+
+ chip->options = 0;
+ chip->options |= NAND_SKIP_BBTSCAN;
+ chip->options |= NAND_NO_SUBPAGE_WRITE;
+
+ err = aml_nand_scan(mtd, controller->chip_num);
+ if (err || (pre_scan->pre_scan_flag)) {
+ goto exit_error;
+ }
+
+ valid_chip_num = 0;
+ for (i=0; i < controller->chip_num; i++) {
+ if (aml_chip->valid_chip[i])
+ valid_chip_num++;
+ }
+
+ chip->scan_bbt = aml_nand_scan_shipped_bbt;//aml_nand_scan_bbt;
+ if (aml_chip->aml_nand_adjust_timing)
+ aml_chip->aml_nand_adjust_timing(aml_chip);
+
+ if (aml_chip->aml_nand_options_confirm(aml_chip)) {
+ err = -ENXIO;
+ goto exit_error;
+ }
+
+ oobmul = mtd->oobsize /aml_chip->oob_size ;
+ if (!chip->ecc.layout)
+ chip->ecc.layout =
+ kzalloc(sizeof(struct nand_ecclayout), GFP_KERNEL);
+ if (!chip->ecc.layout) {
+ err = -ENOMEM;
+ goto exit_error ;
+ }
+ if (!strncmp((char*)plat->name, NAND_BOOT_NAME,
+ strlen((const char*)NAND_BOOT_NAME)))
+ memcpy(chip->ecc.layout,
+ &aml_nand_uboot_oob, sizeof(struct nand_ecclayout));
+ else if (chip->ecc.mode != NAND_ECC_SOFT) {
+ switch (aml_chip->oob_size) {
+ case 64:
+ memcpy(chip->ecc.layout,
+ &aml_nand_oob_64,
+ sizeof(struct nand_ecclayout));
+ break;
+ case 128:
+ memcpy(chip->ecc.layout,
+ &aml_nand_oob_128,
+ sizeof(struct nand_ecclayout));
+ break;
+ case 218:
+ memcpy(chip->ecc.layout,
+ &aml_nand_oob_218,
+ sizeof(struct nand_ecclayout));
+ break;
+ case 224:
+ memcpy(chip->ecc.layout,
+ &aml_nand_oob_224,
+ sizeof(struct nand_ecclayout));
+ break;
+ case 256:
+ memcpy(chip->ecc.layout,
+ &aml_nand_oob_256,
+ sizeof(struct nand_ecclayout));
+ break;
+ case 376:
+ memcpy(chip->ecc.layout,
+ &aml_nand_oob_376,
+ sizeof(struct nand_ecclayout));
+ break;
+ case 436:
+ memcpy(chip->ecc.layout,
+ &aml_nand_oob_436,
+ sizeof(struct nand_ecclayout));
+ break;
+ case 448:
+ memcpy(chip->ecc.layout,
+ &aml_nand_oob_448,
+ sizeof(struct nand_ecclayout));
+ break;
+ case 640:
+ memcpy(chip->ecc.layout,
+ &aml_nand_oob_640,
+ sizeof(struct nand_ecclayout));
+ break;
+ case 744:
+ memcpy(chip->ecc.layout,
+ &aml_nand_oob_744,
+ sizeof(struct nand_ecclayout));
+ break;
+ case 1280:
+ memcpy(chip->ecc.layout,
+ &aml_nand_oob_1280,
+ sizeof(struct nand_ecclayout));
+ break;
+ case 1664:
+ memcpy(chip->ecc.layout,
+ &aml_nand_oob_1664,
+ sizeof(struct nand_ecclayout));
+ break;
+ default:
+ printk("default, use nand base oob layout %d\n",
+ mtd->oobsize);
+ oobfree[0].length =
+ ((mtd->writesize / chip->ecc.size) * aml_chip->user_byte_mode);
+ break;
+ }
+
+ chip->ecc.layout->oobfree[0].length *= oobmul;
+ chip->ecc.layout->eccbytes *= oobmul;
+ printk("%s :oobmul=%d,oobfree.length=%d,oob_size=%d\n",
+ __func__,
+ oobmul,
+ chip->ecc.layout->oobfree[0].length,
+ aml_chip->oob_size);
+ }
+
+ /*
+ * The number of bytes available for a client to place data into
+ * the out of band area
+ */
+ chip->ecc.layout->oobavail = 0;
+ oobfree = chip->ecc.layout->oobfree;
+ for (i = 0; oobfree[i].length && i < ARRAY_SIZE(oobfree); i++)
+ chip->ecc.layout->oobavail += oobfree[i].length;
+ printk("oob avail size %d\n", chip->ecc.layout->oobavail);
+ mtd->oobavail = chip->ecc.layout->oobavail;
+ mtd->ecclayout = chip->ecc.layout;
+
+ aml_chip->virtual_page_size = mtd->writesize;
+ aml_chip->virtual_block_size = mtd->erasesize;
+
+ aml_chip->aml_nand_data_buf =
+ kzalloc((mtd->writesize + mtd->oobsize), GFP_KERNEL);
+ if (aml_chip->aml_nand_data_buf == NULL) {
+ printk("no memory for flash data buf\n");
+ err = -ENOMEM;
+ goto exit_error;
+ }
+ aml_chip->user_info_buf =
+ kzalloc((mtd->writesize / chip->ecc.size) * PER_INFO_BYTE,
+ GFP_KERNEL);
+ if (aml_chip->user_info_buf == NULL) {
+ printk("no memory for flash info buf\n");
+ err = -ENOMEM;
+ goto exit_error;
+ }
+
+ if (aml_chip->rsv == NULL) {
+ aml_chip->rsv = kzalloc(sizeof (struct meson_rsv_handler_t), GFP_KERNEL);
+ if (aml_chip->rsv == NULL) {
+ printk("no memory for aml_chip rsv\n");
+ err = -ENOMEM;
+ goto exit_error;
+ }
+ }
+
+ if (chip->buffers == NULL) {
+ printk("no memory for flash data buf\n");
+ err = -ENOMEM;
+ goto exit_error;
+ }
+
+ chip->oob_poi = chip->buffers->databuf + mtd->writesize;
+ chip->options |= NAND_OWN_BUFFERS;
+
+ if (is_power_of_2(mtd->erasesize))
+ mtd->erasesize_shift = ffs(mtd->erasesize) - 1;
+ else
+ mtd->erasesize_shift = 0;
+
+ if (is_power_of_2(mtd->writesize))
+ mtd->writesize_shift = ffs(mtd->writesize) - 1;
+ else
+ mtd->writesize_shift = 0;
+
+ if (strncmp((char*)plat->name,
+ NAND_BOOT_NAME, strlen((const char*)NAND_BOOT_NAME))) {
+ meson_rsv_init(mtd, aml_chip->rsv);
+ /*block status*/
+ aml_chip->block_status =
+ kzalloc((mtd->size >> mtd->erasesize_shift), GFP_KERNEL);
+ if (aml_chip->block_status == NULL) {
+ printk("no memory for flash block status\n");
+ return -ENOMEM;
+ }
+ memset(aml_chip->block_status, 0, (mtd->size >> mtd->erasesize_shift));
+
+ err = aml_nand_bbt_check(mtd);
+ if (err) {
+ printk("invalid nand bbt\n");
+ goto exit_error;
+ }
+#ifndef CONFIG_ENV_IS_IN_NAND
+ meson_rsv_check(aml_chip->rsv->env);
+#endif
+ meson_rsv_check(aml_chip->rsv->key);
+ meson_rsv_check(aml_chip->rsv->dtb);
+ meson_rsv_check(aml_chip->rsv->ddr_para);
+ }
+
+ if (aml_nand_add_partition(aml_chip) != 0) {
+ err = -ENXIO;
+ goto exit_error;
+ }
+
+ printk("%s initialized ok\n", mtd->name);
+ return 0;
+
+exit_error:
+ if (aml_chip->user_info_buf) {
+ kfree(aml_chip->user_info_buf);
+ aml_chip->user_info_buf = NULL;
+ }
+ if (chip->buffers) {
+ kfree(chip->buffers);
+ chip->buffers = NULL;
+ }
+ if (aml_chip->aml_nand_data_buf) {
+ kfree(aml_chip->aml_nand_data_buf);
+ aml_chip->aml_nand_data_buf = NULL;
+ }
+ if (aml_chip->block_status) {
+ kfree(aml_chip->block_status);
+ aml_chip->block_status = NULL;
+ }
+
+ if (aml_chip->rsv) {
+ kfree(aml_chip->rsv);
+ aml_chip->rsv = NULL;
+ }
+ return err;
+}
+
+/**need fixed**/
+int aml_nand_scan_bbt(struct mtd_info *mtd)
+{
+ return 0;
+}
+
+/* fixme, mxic's bad block identify is not checked yet! */
+//only read bad block labeled ops
+int aml_nand_scan_shipped_bbt(struct mtd_info *mtd)
+{
+ struct nand_chip * chip = mtd->priv;
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+ unsigned char *data_buf;
+ int32_t read_cnt, page, pages_per_blk;
+ loff_t addr, offset;
+ int start_blk =0, total_blk =0,i, j, bad_blk_cnt =0, phys_erase_shift;
+ int realpage, col0_data=0, col0_oob=0, valid_page_num = 1;
+ int col_data_sandisk[6], bad_sandisk_flag=0;
+
+ phys_erase_shift = fls(mtd->erasesize) - 1;
+ chip->pagebuf = -1;
+ pages_per_blk = (1 << (chip->phys_erase_shift - chip->page_shift));
+
+ data_buf = kzalloc(mtd->writesize, GFP_KERNEL);
+ if (data_buf == NULL) {
+ printk("%s %d malloc failed\n",__func__,__LINE__);
+ return -ENOMEM;
+ }
+
+ /*need scan factory bad block in bootloader area*/
+ start_blk = 0;
+ total_blk = (int)(mtd->size >> phys_erase_shift);
+ /* fixme, need check the total block number avoid mtd->size was changed outside! */
+ printk("scaning flash total block %d\n", total_blk);
+ do {
+ offset = mtd->erasesize;
+ offset *= start_blk;
+ for (i=0; i < controller->chip_num; i++) {
+ for (read_cnt = 0; read_cnt < 3; read_cnt++) {
+ if (read_cnt == 2) {
+ if (aml_chip->mfr_type == NAND_MFR_AMD)
+ addr = offset + mtd->writesize;
+ else
+ break;
+ } else {
+ if ((aml_chip->mfr_type == NAND_MFR_SANDISK) ||
+ (aml_chip->mfr_type == NAND_ID_ESMT) ||
+ (aml_chip->mfr_type == NAND_MFR_MACRONIX) ||
+ aml_get_samsung_fbbt_flag()) {
+ addr = offset + read_cnt*mtd->writesize;
+ } else
+ addr = offset +
+ (pages_per_blk - 1) * read_cnt * mtd->writesize;
+ }
+
+ realpage = (int)(addr >> chip->page_shift);
+ page = realpage & chip->pagemask;
+
+ if (page != -1) {
+ valid_page_num=mtd->writesize>>chip->page_shift;
+ valid_page_num /= aml_chip->plane_num;
+
+ aml_chip->page_addr = page/ valid_page_num;
+ if (unlikely(aml_chip->page_addr >= aml_chip->internal_page_nums)) {
+ aml_chip->page_addr -= aml_chip->internal_page_nums;
+ aml_chip->page_addr |=
+ (1 << aml_chip->internal_chip_shift)*aml_chip->internal_chipnr;
+ }
+ }
+ if (aml_chip->plane_num == 2) {
+ aml_chip->aml_nand_wait_devready(aml_chip, i);
+ if (aml_nand_get_fbb_issue()) {
+ chip->cmd_ctrl(mtd,
+ NAND_CMD_SEQIN, NAND_CTRL_CLE);
+ chip->cmd_ctrl(mtd,
+ 0, NAND_CTRL_ALE);
+ }
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_READ0,
+ 0x00,aml_chip->page_addr, i);
+
+ if (!aml_chip->aml_nand_wait_devready(aml_chip, i))
+ printk ("%s, %d,selected chip%d not ready\n",
+ __func__, __LINE__, i);
+
+ if (aml_chip->ops_mode & AML_CHIP_NONE_RB)
+ chip->cmd_ctrl(mtd,
+ NAND_CMD_READ0 & 0xff,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ udelay(2);
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_TWOPLANE_READ1,
+ 0x00, aml_chip->page_addr, i);
+ udelay(2);
+
+ if (aml_chip->mfr_type == NAND_MFR_SANDISK) {
+ for (j = 0; j < 6; j++)
+ col_data_sandisk[j] = chip->read_byte(mtd);
+ } else
+ col0_data = chip->read_byte(mtd);
+
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_TWOPLANE_READ2,
+ aml_chip->page_size,
+ aml_chip->page_addr, i);
+ //aml_chip->aml_nand_wait_devready(aml_chip, i);
+ udelay(2);
+
+ if (aml_chip->mfr_type == NAND_MFR_SANDISK)
+ col0_oob = 0x0;
+ else
+ col0_oob = chip->read_byte(mtd);
+ //printk("col0_oob=%x\n",col0_oob);
+
+ } else if (aml_chip->plane_num == 1) {
+
+ if (aml_nand_get_fbb_issue()) {
+ chip->cmd_ctrl(mtd,
+ NAND_CMD_SEQIN, NAND_CTRL_CLE);
+ chip->cmd_ctrl(mtd,
+ 0, NAND_CTRL_ALE);
+ }
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_READ0, 0x00,
+ aml_chip->page_addr , i);
+ udelay(2);
+
+ if (!aml_chip->aml_nand_wait_devready(aml_chip, i))
+ printk ("%s, %d,selected chip%d not ready\n",
+ __func__, __LINE__, i);
+
+ if (aml_chip->ops_mode & AML_CHIP_NONE_RB)
+ chip->cmd_ctrl(mtd,
+ NAND_CMD_READ0 & 0xff,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ udelay(2);
+
+ if (aml_chip->mfr_type == NAND_MFR_SANDISK) {
+ for (j = 0; j < 6; j++)
+ col_data_sandisk[j] =
+ chip->read_byte(mtd);
+ } else
+ col0_data = chip->read_byte(mtd);
+
+ //printk("col0_data =%x\n",col0_data);
+
+ if (aml_chip->mfr_type != NAND_MFR_SANDISK)
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_RNDOUT,
+ aml_chip->page_size, -1, i);
+ udelay(2);
+
+ if (aml_chip->mfr_type == NAND_MFR_SANDISK)
+ col0_oob = 0x0;
+ else
+ col0_oob = chip->read_byte(mtd);
+ //printk("col0_oob =%x\n",col0_oob);
+ }
+
+ if ((col0_oob == 0xFF))
+ continue;
+
+ if (col0_oob != 0xFF) {
+ printk("%s:%d factory ship bbt found\n", __func__, __LINE__);
+
+ if (aml_chip->mfr_type == NAND_MFR_DOSILICON ||
+ aml_chip->mfr_type == NAND_MFR_ATO ||
+ aml_chip->mfr_type == NAND_MFR_HYNIX ||
+ aml_chip->mfr_type == NAND_ID_WINBOND ||
+ aml_chip->mfr_type == NAND_ID_ESMT ||
+ aml_chip->mfr_type == NAND_MFR_MACRONIX ||
+ aml_chip->mfr_type == NAND_MFR_AMD ||
+ aml_get_samsung_fbbt_flag()) {
+ printk("col0_data =%x col0_oob =%x\n",col0_data,col0_oob);
+ printk("detect a fbb:%llx blk=%d chip=%d\n",
+ (uint64_t)addr, start_blk, i);
+ bad_blk_cnt++;
+ aml_chip->block_status[start_blk] =
+ NAND_FACTORY_BAD;
+ break;
+ }
+
+ if ((aml_chip->mfr_type == NAND_MFR_SANDISK) ) {
+ for (j = 0; j < 6; j++) {
+ if (col_data_sandisk[j] == 0x0) {
+ bad_sandisk_flag = 1;
+ break;
+ }
+ }
+ if (bad_sandisk_flag ) {
+ printk("detect factory Bad block:%llx blk=%d chip=%d\n",
+ (uint64_t)addr, start_blk, i);
+ bad_blk_cnt++;
+ aml_chip->block_status[start_blk] = NAND_FACTORY_BAD;
+ bad_sandisk_flag=0;
+ break;
+ }
+ }
+
+ if ((aml_chip->mfr_type == NAND_MFR_SAMSUNG ) ) {
+ if ((col0_oob != 0xFF) && (col0_data != 0xFF)) {
+ printk("detect factory Bad block:%llx blk=%d chip=%d\n",
+ (uint64_t)addr, start_blk, i);
+ bad_blk_cnt++;
+ aml_chip->block_status[start_blk] = NAND_FACTORY_BAD;
+ break;
+ }
+ }
+
+ if ((aml_chip->mfr_type == NAND_MFR_TOSHIBA ) ) {
+ if ((col0_oob != 0xFF) && (col0_data != 0xFF)) {
+ printk("detect factory Bad block:%llx blk=%d chip=%d\n",
+ (uint64_t)addr, start_blk, i);
+ bad_blk_cnt++;
+ aml_chip->block_status[start_blk] = NAND_FACTORY_BAD;
+ break;
+ }
+ }
+
+ if (aml_chip->mfr_type == NAND_MFR_MICRON ) {
+ if (col0_oob == 0x0) {
+ printk("detect factory Bad block:%llx blk=%d chip=%d\n",
+ (uint64_t)addr, start_blk, i);
+ bad_blk_cnt++;
+ aml_chip->block_status[start_blk] = NAND_FACTORY_BAD;
+ break;
+ }
+ }
+ }
+ }
+ }
+ } while((++start_blk) < total_blk);
+
+ printk("aml_nand_scan_bbt: factory Bad block bad_blk_cnt=%d\n",
+ bad_blk_cnt);
+ kfree(data_buf);
+ return 0;
+}
+
+int aml_nand_bbt_check(struct mtd_info *mtd)
+{
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+ struct aml_nand_chip *aml_chip_boot = mtd_to_nand_chip(nand_info[0]);
+ int ret =0;
+ int8_t *buf = NULL;
+
+ ret = meson_rsv_scan(aml_chip->rsv->bbt);
+ if ((ret !=0) && ((ret != (-1)))) {
+ printk("%s %d\n", __func__, __LINE__);
+ goto exit_error;
+ }
+
+ ret = 0;
+ buf = aml_chip->block_status;
+ if (aml_chip->rsv->bbt->valid == 1) {
+ /*read bbt*/
+ printk("%s %d bbt is valid, reading.\n", __func__, __LINE__);
+ meson_rsv_read(aml_chip->rsv->bbt, (u_char *)buf);
+ } else {
+ printk("%s %d bbt is invalid, scanning.\n", __func__, __LINE__);
+ /*no bbt haven't been found, abnormal or clean nand! rebuild*/
+ aml_nand_scan_shipped_bbt(mtd);
+ meson_rsv_bbt_write((u_char *)buf, aml_chip->rsv->bbt->size);
+ }
+
+ /*make uboot bbt perspective the same with normal bbt*/
+ aml_chip_boot->block_status = aml_chip->block_status;
+exit_error:
+ return ret;
+}
+
+/**read partiton from dtb**/
+extern int get_partition_from_dts(unsigned char * buffer);
+int amlnf_dtb_init_partitions(struct aml_nand_chip *aml_chip)
+{
+ int ret = 0;
+ u8 *dtb_buf = NULL;
+
+ dtb_buf = kzalloc(aml_chip->dtbsize, GFP_KERNEL);
+ if (dtb_buf == NULL) {
+ printk("nand malloc for dtb_buf failed\n");
+ ret = -1;
+ goto exit_err;
+ }
+ memset(dtb_buf, 0x0, aml_chip->dtbsize);
+
+ /*parse partitions table */
+ ret = get_partition_from_dts(dtb_buf);
+ if (ret) {
+ printk("%s get_partition_from_dts failed\n", __func__);
+ }
+exit_err:
+ if (dtb_buf) {
+ kfree(dtb_buf);
+ dtb_buf = NULL;
+ }
+ return ret;
+}
+
+
diff --git a/drivers/mtd/nand/raw/aml_nand/aml_nand.h b/drivers/mtd/nand/raw/aml_nand/aml_nand.h
new file mode 100644
index 0000000..bfa5588
--- /dev/null
+++ b/drivers/mtd/nand/raw/aml_nand/aml_nand.h
@@ -0,0 +1,568 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AML_SLCNAND_H_
+#define __AML_SLCNAND_H_
+
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <nand.h>
+#include <amlogic/aml_nand.h>
+#include "aml_hwctrl.h"
+#include <partition_table.h>
+#include <linux/mtd/partitions.h>
+
+#include <amlogic/aml_rsv.h>
+#include <amlogic/aml_mtd.h>
+
+#define NAND_MAX_DEVICE 4
+/*MAX page list cnt for usrdef mode*/
+#define NAND_PAGELIST_CNT 16
+
+/*nand read retry info,max equal to zero,
+*that means no need retry*/
+struct nand_retry_t {
+ unsigned id;
+ unsigned max;
+ unsigned no_rb;
+};
+
+typedef struct _nand_cmd {
+ unsigned char type;
+ unsigned char val;
+}nand_cmd_t;
+
+struct meson_slcnand_platdata {
+ u32 reg_base;
+ u8 nand_user_mode;
+ u8 nand_ran_mode;
+};
+
+union sc2_cmdinfo {
+ uint32_t d32;
+ struct {
+ unsigned cmd:22; //20-21b' code0/1 17b' WE_n(r/w->1/0b)
+ unsigned page_list:1;
+ unsigned reserved:1;
+ unsigned new_type:8;
+ } b;
+};
+
+typedef struct nand_setup_sc2 {
+ union sc2_cmdinfo cfg;
+ uint16_t id;
+ uint16_t max; // id:0x100 user, max:0 disable.
+} nand_setup_sc2_t;
+
+union cmdinfo {
+ uint32_t d32;
+ struct {
+ unsigned cmd:22;
+ unsigned large_page:1; // 22
+ unsigned no_rb:1; // 23 from efuse
+ unsigned a2:1; // 24
+ unsigned reserved25:1; // 25
+ unsigned page_list:1; // 26
+ unsigned sync_mode:2; // 27 from efuse
+ unsigned size:2; // 29 from efuse
+ unsigned active:1; // 31
+ } b;
+};
+
+typedef struct nand_setup {
+ union cmdinfo cfg;
+ uint16_t id;
+ uint16_t max; // id:0x100 user, max:0 disable.
+} nand_setup_t;
+
+typedef struct _ext_info{
+ uint32_t read_info; //nand_read_info;
+ uint32_t new_type; //new_nand_type;
+ uint32_t page_per_blk; //pages_in_block;
+ uint32_t xlc; //slc=1,mlc=2,tlc=3;
+ uint32_t ce_mask;
+ /*copact mode: boot means whole uboot
+ it's easy to understand that copies off_type
+ bl2 and fip are the same.
+ * discrete mode,boot means the fip only*/
+ uint32_t boot_num;
+ uint32_t each_boot_pages;
+ /*for comptible reason*/
+ uint32_t bbt_occupy_pages;
+ uint32_t bbt_start_block;
+} ext_info_t;
+
+#define NAND_FIPMODE_COMPACT (0)
+#define NAND_FIPMODE_DISCRETE (1)
+
+/* if you don't need skip the bad blocks when address
+ * partitions,please enable this macro.
+ * #define CONFIG_NOT_SKIP_BAD_BLOCK
+ */
+typedef struct _fip_info {
+ uint16_t version; //version
+ uint16_t mode; //compact or discrete
+ uint32_t fip_start; //fip start,pages
+}fip_info_t;
+
+typedef struct _nand_page0_sc2 {
+ nand_setup_sc2_t nand_setup;
+ unsigned char page_list[32];
+ nand_cmd_t retry_usr[32];
+ ext_info_t ext_info;
+ fip_info_t fip_info;
+} nand_page0_sc2_t;
+
+ typedef struct _nand_page0 {
+ nand_setup_t nand_setup;
+ unsigned char page_list[16];
+ nand_cmd_t retry_usr[32];
+ ext_info_t ext_info;
+ fip_info_t fip_info;
+ uint32_t ddrp_start_page;
+ }nand_page0_t;
+
+typedef union nand_core_clk {
+ /*raw register data*/
+ uint32_t d32;
+ struct {
+ unsigned clk_div:7;
+ unsigned reserved0:1;
+ unsigned clk_en:1;
+ unsigned clk_sel:3;
+ unsigned not_used:20;
+ }b;
+}nand_core_clk_t;
+
+/***************ERROR CODING*******************/
+#define NAND_CHIP_ID_ERR 1
+#define NAND_SHIP_BAD_BLOCK_ERR 2
+#define NAND_CHIP_REVB_HY_ERR 3
+
+/** Register defination **/
+#define NAND_BOOT_NAME "bootloader"
+#define NAND_NORMAL_NAME "nandnormal"
+#define NAND_RESERVED_NAME "nandreserved"
+
+
+#define BOOT_PAGES_PER_COPY (1024)
+#define BOOT_COPY_NUM (BOOT_TOTAL_PAGES/BOOT_PAGES_PER_COPY)
+
+
+#define AML_CHIP_NONE_RB 4
+#define AML_INTERLEAVING_MODE 8
+
+#define AML_NAND_CE0 0xe
+#define AML_NAND_CE1 0xd
+#define AML_NAND_CE2 0xb
+#define AML_NAND_CE3 0x7
+
+#define AML_BADBLK_POS 0
+
+#define NAND_ECC_OPTIONS_MASK 0x0000000f
+#define NAND_PLANE_OPTIONS_MASK 0x000000f0
+#define NAND_TIMING_OPTIONS_MASK 0x00000f00
+#define NAND_BUSW_OPTIONS_MASK 0x0000f000
+#define NAND_INTERLEAVING_OPTIONS_MASK 0x000f0000
+
+#define NAND_TWO_PLANE_MODE 0x00000010
+#define NAND_TIMING_MODE0 0x00000000
+#define NAND_TIMING_MODE1 0x00000100
+#define NAND_TIMING_MODE2 0x00000200
+#define NAND_TIMING_MODE3 0x00000300
+#define NAND_TIMING_MODE4 0x00000400
+#define NAND_TIMING_MODE5 0x00000500
+#define NAND_INTERLEAVING_MODE 0x00010000
+
+#define DEFAULT_T_REA 40
+#define DEFAULT_T_RHOH 0
+#define NAND_DEFAULT_OPTIONS (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)
+
+#define AML_NAND_BUSY_TIMEOUT 0x40000
+#define AML_DMA_BUSY_TIMEOUT 0x100000
+#define MAX_ID_LEN 8
+
+#define NAND_CMD_PLANE2_READ_START 0x06
+#define NAND_CMD_TWOPLANE_PREVIOS_READ 0x60
+#define NAND_CMD_TWOPLANE_READ1 0x5a
+#define NAND_CMD_TWOPLANE_READ2 0xa5
+#define NAND_CMD_TWOPLANE_WRITE2_MICRO 0x80
+#define NAND_CMD_TWOPLANE_WRITE2 0x81
+#define NAND_CMD_DUMMY_PROGRAM 0x11
+#define NAND_CMD_ERASE1_END 0xd1
+#define NAND_CMD_MULTI_CHIP_STATUS 0x78
+
+#define ONFI_TIMING_ADDR 0x01
+
+#define NAND_STATUS_READY_MULTI 0x20
+
+#define NAND_BLOCK_GOOD 0
+#define NAND_BLOCK_BAD 1
+#define NAND_FACTORY_BAD 2
+#define BAD_BLK_LEVEL 2
+#define FACTORY_BAD_BLOCK_ERROR 159
+#define MINI_PART_SIZE 0x100000
+#define NAND_MINI_PART_NUM 4
+#define MAX_BAD_BLK_NUM 2000
+#define MAX_MTD_PART_NUM 16
+#define MAX_MTD_PART_NAME_LEN 24
+
+#define NAND_SYS_PART_SIZE 0x8000000
+
+struct aml_nand_flash_dev {
+ char *name;
+ u8 id[MAX_ID_LEN];
+ unsigned pagesize;
+ unsigned chipsize;
+ unsigned erasesize;
+ unsigned oobsize;
+ unsigned internal_chipnr;
+ unsigned T_REA;
+ unsigned T_RHOH;
+ u8 onfi_mode;
+ unsigned options;
+};
+
+struct aml_nand_part_info {
+ char mtd_part_magic[4];
+ char mtd_part_name[MAX_MTD_PART_NAME_LEN];
+ uint64_t size;
+ uint64_t offset;
+ u_int32_t mask_flags;
+};
+
+struct aml_nand_bch_desc {
+ char * name;
+ unsigned bch_mode;
+ unsigned bch_unit_size;
+ unsigned bch_bytes;
+ unsigned user_byte_mode;
+};
+
+struct aml_nand_chip {
+ struct nand_chip chip;
+ struct hw_controller *controller;
+
+ /* mtd info */
+ u8 mfr_type;
+ unsigned onfi_mode;
+ unsigned T_REA;
+ unsigned T_RHOH;
+ unsigned options;
+ unsigned page_size;
+ unsigned block_size;
+ unsigned oob_size;
+ unsigned virtual_page_size;
+ unsigned virtual_block_size;
+ u8 plane_num;
+ u8 internal_chipnr;
+ unsigned internal_page_nums;
+
+ unsigned internal_chip_shift;
+ unsigned int ran_mode;
+ unsigned int rbpin_mode;
+ unsigned int rbpin_detect;
+ unsigned int short_pgsz;
+ /* bch for infopage on short mode */
+ unsigned int bch_info;
+
+ unsigned bch_mode;
+ u8 user_byte_mode;
+ u8 ops_mode;
+ u8 cached_prog_status;
+ u8 max_bch_mode;
+ unsigned valid_chip[MAX_CHIP_NUM];
+ unsigned page_addr;
+ unsigned char *aml_nand_data_buf;
+ unsigned int *user_info_buf;
+ int8_t *block_status;
+ unsigned int toggle_mode;
+ u8 ecc_cnt_limit;
+ u8 ecc_cnt_cur;
+ u8 ecc_max;
+ unsigned zero_cnt;
+ unsigned oob_fill_cnt;
+ unsigned boot_oob_fill_cnt;
+ /*add property field for key private data*/
+ int dtbsize;
+ int keysize;
+ uint32_t boot_copy_num; /*tell how many bootloader copies*/
+
+ u8 key_protect;
+ unsigned char *rsv_data_buf;
+
+ struct meson_rsv_handler_t *rsv;
+
+ struct aml_nand_bch_desc *bch_desc;
+ /* platform info */
+ struct aml_nand_platform *platform;
+
+ /* device info */
+ struct device *device;
+
+ unsigned max_ecc;
+ struct ecc_desc_s * ecc;
+ // unsigned onfi_mode;
+ unsigned err_sts;
+ /* plateform operation function*/
+ void (*aml_nand_hw_init)(struct aml_nand_chip *aml_chip);
+ void (*aml_nand_adjust_timing)(struct aml_nand_chip *aml_chip);
+ int (*aml_nand_options_confirm)(struct aml_nand_chip *aml_chip);
+ void (*aml_nand_cmd_ctrl)(struct aml_nand_chip *aml_chip,
+ int cmd, unsigned int ctrl);
+ void (*aml_nand_select_chip)(struct aml_nand_chip *aml_chip,
+ int chipnr);
+ void (*aml_nand_write_byte)(struct aml_nand_chip *aml_chip,
+ uint8_t data);
+ void (*aml_nand_get_user_byte)(struct aml_nand_chip *aml_chip,
+ unsigned char *oob_buf, int byte_num);
+ void (*aml_nand_set_user_byte)(struct aml_nand_chip *aml_chip,
+ unsigned char *oob_buf, int byte_num);
+ void (*aml_nand_command)(struct aml_nand_chip *aml_chip,
+ unsigned command, int column, int page_addr, int chipnr);
+ int (*aml_nand_wait_devready)(struct aml_nand_chip *aml_chip,
+ int chipnr);
+ int (*aml_nand_dma_read)(struct aml_nand_chip *aml_chip,
+ unsigned char *buf, int len, unsigned bch_mode);
+ int (*aml_nand_dma_write)(struct aml_nand_chip *aml_chip,
+ unsigned char *buf, int len, unsigned bch_mode);
+ int (*aml_nand_hwecc_correct)(struct aml_nand_chip *aml_chip,
+ unsigned char *buf, unsigned size, unsigned char *oob_buf);
+ int (*aml_nand_block_bad_scrub)(struct mtd_info *mtd);
+};
+
+struct aml_pre_scan {
+ u8 pre_scan_flag;
+ u8 is_nand;
+};
+
+
+struct aml_nand_platform {
+ struct aml_nand_flash_dev *nand_flash_dev;
+ char *name;
+ unsigned chip_enable_pad;
+ unsigned ready_busy_pad;
+
+ /* DMA RD/WR delay loop timing */
+ unsigned int T_REA; /* for dma wating delay */
+ /* not equal of (nandchip->delay, which is for dev ready func)*/
+ unsigned int T_RHOH;
+ unsigned int ran_mode; /*def close, for all part*/
+ unsigned int rbpin_mode; /*may get from romboot*/
+ unsigned int rbpin_detect;
+ unsigned int short_pgsz; /*zero means no short*/
+
+ struct aml_nand_chip *aml_chip;
+ struct platform_nand_data platform_nand_data;
+};
+
+struct aml_nand_device {
+ struct aml_nand_platform *aml_nand_platform;
+ u8 dev_num;
+};
+
+static inline struct aml_nand_chip *mtd_to_nand_chip(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+ return container_of(chip, struct aml_nand_chip, chip);
+}
+
+#ifdef CONFIG_PARAMETER_PAGE
+struct parameter_page {
+ /*0~31 byte: Revision information and features block*/
+ unsigned char signature[4];
+ unsigned short ver;
+ unsigned short feature;
+ unsigned short opt_commd;
+ unsigned short reserve0;
+ unsigned short ex_para_page_len;
+ unsigned char num_para_page;
+ unsigned char reserve1[17];
+ /*32~79 byte: Manufacturer information block*/
+ unsigned char dev_manu[12];
+ unsigned char dev_model[20];
+ unsigned char JEDEC_manu_ID;
+ unsigned short date_code;
+ unsigned char reserve2[13];
+ /*80~127 byte: Memory organization block*/
+ unsigned int data_bytes_perpage;
+ unsigned short spare_bytes_perpage;
+ unsigned int data_bytes_perpartial;
+ unsigned short spare_bytes_perpartial;
+ unsigned int pages_perblk;
+ unsigned int blks_perLUN;
+ unsigned char num_LUN;
+ /* 4-7: column addr cycles; 0-3: row addr cycles*/
+ unsigned char num_addr_cycle;
+ unsigned char bits_percell;
+ unsigned short max_badblk_perLUN;
+ unsigned short blk_edurce;
+ /*Guaranteed valid blocks at beginning of target*/
+ unsigned char g_v_blk_begin;
+ unsigned short blk_edurce_g_v_blk;
+ unsigned char progm_perpage;
+ unsigned char prt_prog_att;//obsolete
+ unsigned char bits_ECC_corretable;
+ /*0-3: number of interleaved address bits*/
+ unsigned char bits_intleav_addr;
+ /*6-7 Reserved (0)
+ 5 1 = lower bit XNOR block address restriction
+ 4 1 = read cache supported
+ 3 Address restrictions for cache operations
+ 2 1 = program cache supported
+ 1 1 = no block address restrictions
+ 0 Overlapped / concurrent interleaving support
+ */
+ unsigned char intleav_op_attr;
+ unsigned char reserve3[13];
+ /*128~163 byte: Electrical parameters block*/
+ unsigned char max_io_pin;
+ /*6-15 Reserved (0)
+ 5 1 = supports timing mode 5
+ 4 1 = supports timing mode 4
+ 3 1 = supports timing mode 3
+ 2 1 = supports timing mode 2
+ 1 1 = supports timing mode 1
+ 0 1 = supports timing mode 0, shall be 1
+ */
+ unsigned short asy_time_mode;
+ unsigned short asy_prog_cach_time_mode; /*obsolete*/
+ unsigned short Tprog; /*Maximum page program time (Ts)*/
+ unsigned short Tbers; /*Maximum block erase time (Ts)*/
+ unsigned short Tr; /*Maximum page read time (Ts)*/
+ unsigned short Tccs; /*Minimum change column setup time (ns)*/
+ /* 6-15 Reserved (0)
+ 5 1 = supports timing mode 5
+ 4 1 = supports timing mode 4
+ 3 1 = supports timing mode 3
+ 2 1 = supports timing mode 2
+ 1 1 = supports timing mode 1
+ 0 1 = supports timing mode 0
+ */
+ unsigned short src_syn_time_mode;
+ /*3-7 Reserved (0)
+ 2 1 = device supports CLK stopped for data input
+ 1 1 = typical capacitance values present
+ 0 tCAD value to use
+ */
+ unsigned char src_syn_feature;
+ unsigned short CLK_input_pin;
+ unsigned short IO_pin;
+ unsigned short input_pin;
+ unsigned char max_input_pin;
+ unsigned char dr_strgth;
+ /*Maximum interleaved page read time (Ts)*/
+ unsigned short Tir;
+ /*Program page register clear enhancement tADL value (ns)*/
+ unsigned short Tadl;
+ unsigned char reserve4[8];
+ /*164~255 byte: Vendor block*/
+ unsigned short vd_ver;
+ unsigned char vd_spec[88];
+ unsigned short int_CRC;
+ /*256~ byte: Redundant Parameter Pages*/
+
+}__attribute__ ((__packed__));
+#endif
+
+int aml_nand_init(struct aml_nand_chip *aml_chip);
+
+int aml_nand_read_page_raw(struct mtd_info *mtd,
+ struct nand_chip *chip, uint8_t *buf, int oob_required, int page);
+
+int aml_nand_write_page_raw(struct mtd_info *mtd,
+ struct nand_chip *chip, const uint8_t *buf, int oob_required,
+ int page);
+
+int aml_nand_read_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, uint8_t *buf, int oob_required, int page);
+
+int aml_nand_write_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, const uint8_t *buf, int oob_required,
+ int page);
+
+int aml_nand_read_oob(struct mtd_info *mtd,
+ struct nand_chip *chip, int page);
+
+int aml_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip, int page);
+
+int aml_nand_block_bad(struct mtd_info *mtd, loff_t ofs);
+
+int aml_nand_block_markbad(struct mtd_info *mtd, loff_t ofs);
+
+void aml_nand_dma_read_buf(struct mtd_info *mtd, uint8_t *buf, int len);
+
+void aml_nand_dma_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len);
+
+void aml_platform_cmd_ctrl(struct aml_nand_chip *aml_chip,
+ int cmd, unsigned int ctrl);
+
+void aml_platform_write_byte(struct aml_nand_chip *aml_chip, uint8_t data);
+
+int aml_platform_wait_devready(struct aml_nand_chip *aml_chip, int chipnr);
+
+void aml_platform_get_user_byte(struct aml_nand_chip *aml_chip,
+ unsigned char *oob_buf, int byte_num);
+
+void aml_platform_set_user_byte(struct aml_nand_chip *aml_chip,
+ unsigned char *oob_buf, int byte_num);
+
+void aml_nand_base_command(struct aml_nand_chip *aml_chip,
+ unsigned command, int column, int page_addr, int chipnr);
+
+int aml_nand_block_bad_scrub_update_bbt(struct mtd_info *mtd);
+
+int aml_ubootenv_init(struct aml_nand_chip *aml_chip);
+
+int amlnf_dtb_init(struct aml_nand_chip *aml_chip);
+
+int aml_key_init(struct aml_nand_chip *aml_chip);
+
+int aml_nand_erase_key(struct mtd_info *mtd);
+
+int aml_nand_bbt_check(struct mtd_info *mtd);/*fixed by liuxj*/
+
+int aml_nand_scan(struct mtd_info *mtd, int maxchips);
+
+int aml_nand_write_page_raw(struct mtd_info *mtd,
+ struct nand_chip *chip, const uint8_t *buf, int oob_required,
+ int page);
+
+int aml_nand_write_page(struct mtd_info *mtd,
+ struct nand_chip *chip, uint32_t offset,
+ int data_len,
+ const uint8_t *buf,
+ int oob_required, int page, int raw);
+
+void aml_nand_base_command(struct aml_nand_chip *aml_chip,
+ unsigned command, int column, int page_addr, int chipnr);
+
+void aml_nand_command(struct mtd_info *mtd,
+ unsigned command, int column, int page_addr);
+
+int aml_nand_wait(struct mtd_info *mtd, struct nand_chip *chip);
+
+int aml_nand_erase_cmd(struct mtd_info *mtd, int page);
+
+int m3_nand_boot_erase_cmd(struct mtd_info *mtd, int page);
+
+int m3_nand_boot_read_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, uint8_t *buf, int oob_required, int page);
+
+int m3_nand_boot_write_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, const uint8_t *buf, int oob_required,
+ int page);
+
+int m3_nand_boot_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+ uint32_t offset, int data_len, const uint8_t *buf,
+ int oob_required, int page, int raw);
+
+int aml_get_samsung_fbbt_flag(void);
+int aml_nand_get_fbb_issue(void);
+
+void aml_nand_check_fbb_issue(u8 *dev_id);
+
+#endif
diff --git a/drivers/mtd/nand/raw/aml_nand/boot.c b/drivers/mtd/nand/raw/aml_nand/boot.c
new file mode 100644
index 0000000..87df0d5
--- /dev/null
+++ b/drivers/mtd/nand/raw/aml_nand/boot.c
@@ -0,0 +1,504 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <linux/err.h>
+#include <asm/cache.h>
+//#include <asm/arch/secure_apb.h>
+#include <amlogic/cpu_id.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/mtd/nand_ecc.h>
+
+#include "aml_nand.h"
+#include "version.h"
+
+extern struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
+extern struct hw_controller *controller;
+/* provide a policy that caluate the bakups of bootloader */
+int get_boot_num(struct mtd_info *mtd, size_t rwsize)
+{
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+ size_t bad_blk_len_low = 0, bad_blk_len_up = 0, skip;
+ size_t aviable_space;
+ size_t block_len, block_off;
+ loff_t block_start;
+ loff_t offset = 0;
+ int ret = 1; /*inital for only one copy*/
+
+ if (!rwsize) { /*not need to policy call, only one */
+ ret = 1;
+ return ret;
+ }
+
+ /* algin with page size */
+ rwsize = ((rwsize + mtd->writesize - 1)/mtd->writesize)*mtd->writesize;
+
+ while (offset < mtd->size) {
+ block_start = offset & ~(loff_t)(mtd->erasesize - 1);
+ block_off = offset & (mtd->erasesize - 1);
+ block_len = mtd->erasesize - block_off;
+
+ if (nand_block_isbad(mtd, block_start)) {
+ if ( offset < mtd->size / 2) /*no understand*/
+ bad_blk_len_low += block_len;
+ else if (offset > mtd->size / 2)
+ bad_blk_len_up += block_len;
+ else {
+ bad_blk_len_up = offset;
+ }
+ }
+ offset += block_len;
+ }
+
+ printk("rwsize:0x%zx skip_low:0x%zx skip_up:0x%zx\n",
+ rwsize, bad_blk_len_low, bad_blk_len_up);
+
+ skip = bad_blk_len_low + bad_blk_len_up;
+ aviable_space = mtd->size - skip - 2 * mtd->writesize; /*no understand*/
+
+ if (rwsize*2 <= aviable_space) {
+ ret = 1;
+ if (rwsize + mtd->writesize + bad_blk_len_low > mtd->size / 2)
+ return 1; /*1st must be write*/
+ if (rwsize + mtd->writesize + bad_blk_len_up <= mtd->size / 2)
+ ret ++;
+ } else /*needn't consider bad block length, unlikly so many bad blocks*/
+ ret = 1;
+
+ aml_chip->boot_copy_num = ret;
+ printk("self-adaption boot count:%d\n", ret);
+
+ return ret;
+}
+
+/*set nand info into page0_buf for romboot.*/
+void nand_info_page_prepare(struct aml_nand_chip *aml_chip, u8 *page0_buf)
+{
+ struct nand_chip *chip = &aml_chip->chip;
+ struct mtd_info *mtd = &chip->mtd;
+ struct aml_nand_chip *aml_chip_normal = mtd_to_nand_chip(nand_info[1]);
+ u32 configure_data;
+ nand_page0_t *p_nand_page0 = NULL;
+ nand_page0_sc2_t *p_nand_page0_sc2 = NULL;
+ ext_info_t *p_ext_info = NULL;
+ nand_setup_t *p_nand_setup = NULL;
+ nand_setup_sc2_t * p_nand_setup_sc2 = NULL;
+ cpu_id_t cpu_id = get_cpu_id();
+ int each_boot_pages, boot_num, bbt_pages;
+ unsigned int pages_per_blk_shift ,bbt_size;
+ fip_info_t *p_fip_info = NULL;
+ uint32_t ddrp_start_block = 0;
+
+ pages_per_blk_shift = (chip->phys_erase_shift - chip->page_shift);
+ bbt_size = aml_chip_normal->rsv->bbt->size;
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER) {
+ boot_num = CONFIG_NAND_TPL_COPY_NUM;
+ each_boot_pages = CONFIG_TPL_SIZE_PER_COPY / mtd->writesize;
+ } else {
+ boot_num = (!aml_chip->boot_copy_num)? 1: aml_chip->boot_copy_num;
+ each_boot_pages = BOOT_TOTAL_PAGES / boot_num;
+ }
+
+ p_nand_page0 = (nand_page0_t *) page0_buf;
+ p_nand_setup = &p_nand_page0->nand_setup;
+ p_ext_info = &p_nand_page0->ext_info;
+
+ configure_data = NFC_CMD_N2M(aml_chip->ran_mode,
+ aml_chip->bch_mode, 0, (chip->ecc.size >> 3),
+ chip->ecc.steps);
+
+ memset(p_nand_page0, 0x0, sizeof(nand_page0_t));
+ if ((cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) ||
+ (cpu_id.family_id == MESON_CPU_MAJOR_ID_S4)) {
+ p_nand_page0_sc2 = (nand_page0_sc2_t *) page0_buf;
+ p_nand_setup_sc2 = &p_nand_page0_sc2->nand_setup;
+ p_ext_info = &p_nand_page0_sc2->ext_info;
+ p_nand_setup_sc2->cfg.d32 = configure_data;
+ p_nand_setup_sc2->cfg.b.page_list = 0;
+ p_nand_setup_sc2->cfg.b.new_type = 0;
+ p_fip_info = &p_nand_page0_sc2->fip_info;
+ printk("sc2 cfg.d32 0x%x\n", p_nand_setup_sc2->cfg.d32);
+ } else {
+ p_nand_page0 = (nand_page0_t *) page0_buf;
+ p_nand_setup = &p_nand_page0->nand_setup;
+ p_ext_info = &p_nand_page0->ext_info;
+ p_nand_setup->cfg.d32 = (configure_data | (1<<23) | (1<<22) | (2<<20));
+ memset(p_nand_page0->page_list, 0, NAND_PAGELIST_CNT);
+ p_fip_info = &p_nand_page0->fip_info;
+ printk("cfg.d32 0x%x\n", p_nand_setup->cfg.d32);
+ }
+ p_ext_info->page_per_blk = aml_chip->block_size / aml_chip->page_size;
+ p_ext_info->boot_num = boot_num;
+ p_ext_info->each_boot_pages = each_boot_pages;
+ bbt_pages =
+ (bbt_size + mtd->writesize - 1) / mtd->writesize;
+ p_ext_info->bbt_occupy_pages = bbt_pages;
+ p_ext_info->bbt_start_block =
+ (BOOT_TOTAL_PAGES >> pages_per_blk_shift) + NAND_GAP_BLOCK_NUM;
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER) {
+ p_fip_info->version = 1;
+ p_fip_info->mode = NAND_FIPMODE_DISCRETE;
+ /* in pages, fixme, should it stored in amlchip? */
+ p_fip_info->fip_start =
+ 1024 + NAND_RSV_BLOCK_NUM * p_ext_info->page_per_blk;
+ ddrp_start_block = aml_chip_normal->rsv->ddr_para->nvalid->blk_addr;
+ p_nand_page0->ddrp_start_page = (ddrp_start_block << pages_per_blk_shift) +
+ aml_chip_normal->rsv->ddr_para->nvalid->page_addr;
+ printk("ddrp_start_page = 0x%x ddr_start_block = 0x%x\n",
+ p_nand_page0->ddrp_start_page, ddrp_start_block);
+ printk("bl: version %d, mode %d, start 0x%x\n",
+ p_fip_info->version, p_fip_info->mode, p_fip_info->fip_start);
+ }
+ printk("page_per_blk = 0x%x bbt_pages = 0x%x \n",
+ p_ext_info->page_per_blk, bbt_pages);
+ printk("boot_num = %d each_boot_pages = %d\n", boot_num,
+ each_boot_pages);
+}
+
+/* mtd support interface:
+ * function:int (*_erase) (struct mtd_info *mtd, struct erase_info *instr);
+ */
+int m3_nand_boot_erase_cmd(struct mtd_info *mtd, int page)
+{
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+ struct nand_chip *chip = mtd->priv;
+ loff_t ofs;
+
+ ofs = (page << chip->page_shift);
+
+ if (chip->block_bad(mtd, ofs))
+ return 0;
+ aml_chip->aml_nand_select_chip(aml_chip, 0);
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_ERASE1, -1, page, 0);
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_ERASE2, -1, -1, 0);
+ chip->waitfunc(mtd, chip);
+
+ return 0;
+}
+
+/* mtd support interface:
+ * chip->ecc.read_page
+ * function:int (*read_page)(struct mtd_info *mtd, struct nand_chip *chip,
+ * uint8_t *buf, int oob_required, int page);
+ */
+int m3_nand_boot_read_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
+{
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+ uint8_t *oob_buf = chip->oob_poi;
+ unsigned nand_page_size = chip->ecc.steps * chip->ecc.size;
+ unsigned pages_per_blk_shift =chip->phys_erase_shift - chip->page_shift;
+ int user_byte_num = (chip->ecc.steps * aml_chip->user_byte_mode);
+ int bch_mode = aml_chip->bch_mode, ran_mode=0;
+ int error = 0, i = 0, stat = 0;
+ int ecc_size, configure_data_w, pages_per_blk_w, configure_data;
+ int pages_per_blk, read_page;
+ int en_slc = 0;
+ /* using info page structure */
+ nand_page0_t *p_nand_page0 = NULL;
+ ext_info_t *p_ext_info = NULL;
+ nand_setup_t * p_nand_setup = NULL;
+ int each_boot_pages, boot_num;
+ loff_t ofs;
+
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER)
+ boot_num = CONFIG_BL2_COPY_NUM;
+ else
+ boot_num = (!aml_chip->boot_copy_num)? 1: aml_chip->boot_copy_num;
+
+ each_boot_pages = BOOT_TOTAL_PAGES/boot_num;
+
+ if (page >= (each_boot_pages * boot_num)) {
+ memset(buf, 0, (1 << chip->page_shift));
+ printk("nand boot read out of uboot failed, page:%d\n", page);
+ goto exit;
+ }
+ /* nand page info */
+ if ((page % each_boot_pages) == 0) {
+ if (aml_chip->bch_mode == NAND_ECC_BCH_SHORT)
+ configure_data_w =
+ NFC_CMD_N2M(aml_chip->ran_mode,
+ NAND_ECC_BCH60_1K, 1, (chip->ecc.size >> 3), chip->ecc.steps);
+ else
+ configure_data_w =
+ NFC_CMD_N2M(aml_chip->ran_mode,
+ aml_chip->bch_mode, 0, (chip->ecc.size >> 3), chip->ecc.steps);
+
+ ecc_size = chip->ecc.size; //backup ecc size
+
+ if (aml_chip->bch_mode != NAND_ECC_BCH_SHORT) {
+ nand_page_size =
+ (mtd->writesize / 512) * NAND_ECC_UNIT_SHORT;
+ bch_mode = NAND_ECC_BCH_SHORT;
+ chip->ecc.size = NAND_ECC_UNIT_SHORT;
+ } else
+ bch_mode = aml_chip->bch_mode;
+
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
+ memset(buf, 0xff, (1 << chip->page_shift));
+ /* read back page0 and check it */
+ if (aml_chip->valid_chip[0]) {
+ if (!aml_chip->aml_nand_wait_devready(aml_chip, i)) {
+ printk("don't found selected chip:%d ready\n",
+ i);
+ error = -EBUSY;
+ }
+ if (aml_chip->ops_mode & AML_CHIP_NONE_RB)
+ chip->cmd_ctrl(mtd, NAND_CMD_READ0 & 0xff,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+ if (en_slc == 0) {
+ ran_mode = aml_chip->ran_mode;
+ aml_chip->ran_mode = 1;
+ }
+ error = aml_chip->aml_nand_dma_read(aml_chip,
+ buf, nand_page_size, bch_mode);
+
+ if (error) {
+ printk(" page0 aml_nand_dma_read failed\n");
+ }
+
+ aml_chip->aml_nand_get_user_byte(aml_chip,
+ oob_buf, user_byte_num);
+ stat = aml_chip->aml_nand_hwecc_correct(aml_chip,
+ buf, nand_page_size, oob_buf);
+ if (stat < 0) {
+ if(aml_chip->ran_mode
+ && (aml_chip->zero_cnt < aml_chip->ecc_max)) {
+ memset(buf, 0xff, nand_page_size);
+ memset(oob_buf, 0xff, user_byte_num);
+ } else {
+ mtd->ecc_stats.failed++;
+ printk("page0 read ecc failed at blk0 chip0\n");
+ }
+ } else
+ mtd->ecc_stats.corrected += stat;
+ if (en_slc == 0)
+ aml_chip->ran_mode = ran_mode;
+ } else {
+ printk("nand boot page 0 no valid chip failed\n");
+ error = -ENODEV;
+ //goto exit;
+ }
+
+ //check page 0 info here
+ p_nand_page0 = (nand_page0_t *) buf;
+ p_nand_setup = &p_nand_page0->nand_setup;
+ p_ext_info = &p_nand_page0->ext_info;
+
+ configure_data = p_nand_setup->cfg.b.cmd;
+ pages_per_blk = p_ext_info->page_per_blk;
+ pages_per_blk_w =
+ (1 << (chip->phys_erase_shift - chip->page_shift));
+
+ if ((pages_per_blk_w != pages_per_blk)
+ || (configure_data != configure_data_w))
+ printk("page%d warnning, configure:0x%x-0x%x "
+ "pages_per_blk:0x%x-0x%x\n",
+ page, configure_data_w, configure_data,
+ pages_per_blk_w, pages_per_blk);
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER)
+ /* fixme, check fip_info_t */
+ printk(" TODO: check fip info\n");
+
+ bch_mode = aml_chip->bch_mode;
+ chip->ecc.size = ecc_size;
+ nand_page_size = chip->ecc.steps * chip->ecc.size;
+ }
+
+ read_page = page;
+ read_page++;
+READ_BAD_BLOCK:
+ ofs = (read_page << chip->page_shift);
+ if (!(ofs % mtd->erasesize)) {
+ if (chip->block_bad(mtd, ofs)) {
+ read_page +=
+ 1 << (chip->phys_erase_shift-chip->page_shift);
+ goto READ_BAD_BLOCK;
+ }
+ }
+
+ chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, read_page);
+
+ memset(buf, 0xff, (1 << chip->page_shift));
+ if (aml_chip->valid_chip[0]) {
+ if (!aml_chip->aml_nand_wait_devready(aml_chip, 0)) {
+ printk("don't found selected chip0 ready, page: %d \n",
+ page);
+ error = -EBUSY;
+ goto exit;
+ }
+ if (aml_chip->ops_mode & AML_CHIP_NONE_RB)
+ chip->cmd_ctrl(mtd, NAND_CMD_READ0 & 0xff,
+ NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
+
+ error = aml_chip->aml_nand_dma_read(aml_chip,
+ buf, nand_page_size, bch_mode);
+ if (error) {
+ error = -ENODEV;
+ printk("aml_nand_dma_read failed: page:%d \n", page);
+ goto exit;
+ }
+
+ aml_chip->aml_nand_get_user_byte(aml_chip,
+ oob_buf, user_byte_num);
+ stat = aml_chip->aml_nand_hwecc_correct(aml_chip,
+ buf, nand_page_size, oob_buf);
+ if (stat < 0) {
+ error = -ENODEV;
+ mtd->ecc_stats.failed++;
+ printk("read data ecc failed at page%d blk%d chip%d\n",
+ page, (page >> pages_per_blk_shift), i);
+ } else
+ mtd->ecc_stats.corrected += stat;
+ } else
+ error = -ENODEV;
+
+exit:
+ return error;
+}
+
+
+/* mtd support interface:
+ * chip->ecc.write_page
+ * function:int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
+ * uint8_t *buf, int oob_required, int page);
+ */
+int m3_nand_boot_write_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, const uint8_t *buf, int oob_required,
+ int page)
+{
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+ uint8_t *oob_buf = chip->oob_poi;
+ unsigned nand_page_size = chip->ecc.steps * chip->ecc.size;
+ int user_byte_num = (chip->ecc.steps * aml_chip->user_byte_mode);
+ int error = 0, i = 0, bch_mode, ecc_size;
+ int each_boot_pages, boot_num;
+
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER)
+ boot_num = CONFIG_BL2_COPY_NUM;
+ else
+ boot_num = (!aml_chip->boot_copy_num)? 1: aml_chip->boot_copy_num;
+ each_boot_pages = BOOT_TOTAL_PAGES/boot_num;
+
+ ecc_size = chip->ecc.size;
+ if (((aml_chip->page_addr % each_boot_pages) == 0)
+ && (aml_chip->bch_mode != NAND_ECC_BCH_SHORT)) {
+ nand_page_size = (mtd->writesize / 512) * NAND_ECC_UNIT_SHORT;
+ bch_mode = NAND_ECC_BCH_SHORT;
+ chip->ecc.size = NAND_ECC_UNIT_SHORT;
+ } else
+ bch_mode = aml_chip->bch_mode;
+ /* setting magic for romboot checks. */
+ for (i = 0; i < mtd->oobavail; i += 2) {
+ oob_buf[i] = 0x55;
+ oob_buf[i+1] = 0xaa;
+ }
+
+ i = 0;
+ if (aml_chip->valid_chip[i]) {
+ aml_chip->aml_nand_select_chip(aml_chip, i);
+ aml_chip->aml_nand_set_user_byte(aml_chip,
+ oob_buf, user_byte_num);
+ error = aml_chip->aml_nand_dma_write(aml_chip,
+ (unsigned char *)buf, nand_page_size, bch_mode);
+ if (error)
+ goto exit;
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_PAGEPROG, -1, -1, i);
+ } else {
+ error = -ENODEV;
+ goto exit;
+ }
+exit:
+ if (((aml_chip->page_addr % each_boot_pages) == 0)
+ && (aml_chip->bch_mode != NAND_ECC_BCH_SHORT))
+ chip->ecc.size = ecc_size;
+ return error;
+}
+
+/* mtd support interface:
+ * chip->write_page
+ * function: int (*write_page)(struct mtd_info *mtd, struct nand_chip *chip,
+ * uint32_t offset, int data_len, const uint8_t *buf,
+ * int oob_required, int page, int cached, int raw);
+ */
+int m3_nand_boot_write_page(struct mtd_info *mtd, struct nand_chip *chip,
+ uint32_t offset, int data_len, const uint8_t *buf,
+ int oob_required, int page, int raw)
+{
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+ int status, write_page, ran_mode=0;
+ int en_slc = 0, each_boot_pages, boot_num;
+ loff_t ofs;
+
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER)
+ boot_num = CONFIG_BL2_COPY_NUM;
+ else
+ boot_num = (!aml_chip->boot_copy_num)? 1: aml_chip->boot_copy_num;
+
+ each_boot_pages = BOOT_TOTAL_PAGES / boot_num;
+
+ /* actual page to be written */
+ write_page = page;
+ /* zero page of each copy */
+ if ((write_page % each_boot_pages) == 0) {
+ nand_info_page_prepare(aml_chip, chip->buffers->databuf);
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, write_page);
+ /* must enable ran_mode for info page */
+ if (en_slc == 0) {
+ ran_mode = aml_chip->ran_mode;
+ aml_chip->ran_mode = 1;
+ }
+ chip->ecc.write_page(mtd, chip, chip->buffers->databuf, 0, 0);
+ if (en_slc == 0)
+ aml_chip->ran_mode = ran_mode;
+
+ status = chip->waitfunc(mtd, chip);
+
+ if (status & NAND_STATUS_FAIL) {
+ printk("uboot wr 0 page=0x%x, status=0x%x\n",
+ page, status);
+ return -EIO;
+ }
+ }
+ /* +1 for skipping nand info page */
+ if (en_slc) {
+ } else
+ write_page++;
+
+WRITE_BAD_BLOCK:
+ ofs = (write_page << chip->page_shift);
+ if (!(ofs % mtd->erasesize)) {
+ if (chip->block_bad(mtd, ofs)) {
+ write_page +=
+ 1 << (chip->phys_erase_shift-chip->page_shift);
+ goto WRITE_BAD_BLOCK;
+ }
+ }
+ chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, write_page);
+
+ if (unlikely(raw))
+ chip->ecc.write_page_raw(mtd, chip, buf, 0, 0);
+ else
+ chip->ecc.write_page(mtd, chip, buf, 0, 0);
+
+ if (!(chip->options & NAND_CACHEPRG)) {
+ status = chip->waitfunc(mtd, chip);
+
+ if (status & NAND_STATUS_FAIL) {
+ printk("uboot wr page=0x%x, status=0x%x\n",
+ page,status);
+ return -EIO;
+ }
+ } else
+ status = chip->waitfunc(mtd, chip);
+ return 0;
+}
diff --git a/drivers/mtd/nand/raw/aml_nand/cmd_amlmtd.c b/drivers/mtd/nand/raw/aml_nand/cmd_amlmtd.c
new file mode 100644
index 0000000..83e800d
--- /dev/null
+++ b/drivers/mtd/nand/raw/aml_nand/cmd_amlmtd.c
@@ -0,0 +1,587 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <environment.h>
+#include <nand.h>
+#include "aml_nand.h"
+
+extern struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
+
+/* debug macros */
+#define CONFIG_AML_MTD_DBG (1)
+#ifdef CONFIG_AML_MTD_DBG
+static void dump_args(int argc, char * const argv[])
+{
+ int i;
+ /* debug codes for mtd cmd */
+ for (i = 0; i < argc; i++)
+ printk("arg %d: %s\n", i, argv[i]);
+
+ return;
+}
+#else
+static void dump_args(int argc, char * const argv[])
+{
+ return;
+}
+#endif
+
+/*
+ * operations for bootloader
+ * we call it rom as legarcy reasons.
+ * call nand's opeartions.
+ * switch to normal device after doing this.
+ */
+#define CONFIG_AMLMTD_CURRDEV (0)
+extern int set_mtd_dev(int dev);
+extern int get_mtd_dev(void);
+static int do_rom_ops(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ int ret = 0;
+ int copy_num = 4;
+ int i;
+ ulong cpy;
+ char *sub;
+ struct mtd_info *nand;
+ unsigned long addr;
+ int base = 2;
+ u64 off, maxsize;
+ size_t rwsize, limit, wsize;
+#if (CONFIG_AMLMTD_CURRDEV)
+ int curr_mtd_dev;
+#endif
+ printk("%s(): argc %d\n", __func__, argc);
+ dump_args(argc, argv);
+#if (CONFIG_AMLMTD_CURRDEV)
+ curr_mtd_dev = get_mtd_dev();
+ if (curr_mtd_dev != 0)
+ set_mtd_dev(0);
+#endif
+ nand = nand_info[0];
+ maxsize = nand->size;
+ if (strlen(argv[1]) > 3)
+ sub = &argv[1][4];
+ else {
+ sub = argv[2];
+ base = 3;
+ }
+ if (!strcmp("read", sub)) {
+ printk("%s() %s\n", __func__, sub);
+ if (argc - base < 3) {
+ ret = CMD_RET_USAGE;
+ goto _out;
+ }
+ addr = (ulong)simple_strtoul(argv[base], NULL, 16);
+ off = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
+ rwsize = (ulong)simple_strtoul(argv[base + 2], NULL, 16);
+ ret = nand_read_skip_bad(nand, off, &rwsize,
+ NULL, maxsize, (u8 *)addr);
+ } else if (!strcmp("write", sub)) {
+ printk("%s() %s\n", __func__, sub);
+ if (argc - base < 2) {
+ ret = CMD_RET_USAGE;
+ goto _out;
+ }
+ addr = (ulong)simple_strtoul(argv[base], NULL, 16);
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER) {
+ limit = nand->size / CONFIG_BL2_COPY_NUM;
+ /* write all copies if off do not exist */
+ if (argc -base == 2) {
+ off = 0;
+ rwsize = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
+ copy_num = CONFIG_BL2_COPY_NUM;
+ } else {
+ off = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
+ rwsize = (ulong)simple_strtoul(argv[base + 2], NULL, 16);
+ copy_num = 1;
+ }
+ } else {
+ /* write all, offset must be 0 */
+ off = 0;
+ rwsize = (ulong)simple_strtoul(argv[base + 2], NULL, 16);
+ copy_num = get_boot_num(nand, rwsize);
+ limit = nand->size / copy_num;
+ }
+ printf("%s() %d\n", __func__, copy_num);
+ wsize = rwsize;
+ for (i = 0; i < copy_num; i++) {
+ ret = nand_write_skip_bad(nand, off, &rwsize,
+ NULL, limit,
+ (u8 *)addr, 0);
+ if (ret)
+ rwsize = wsize;
+ off += nand->size/copy_num;
+ }
+ } else if (!strcmp("erase", sub)) {
+ nand_erase_options_t opts;
+ printk("%s() %s\n", __func__, sub);
+ memset(&opts, 0, sizeof(opts));
+ if (store_get_device_bootloader_mode() ==
+ DISCRETE_BOOTLOADER) {
+ if (argc - base == 0) {
+ opts.offset = 0;
+ /* whole boot area size */
+ opts.length = nand->size;
+ } else {
+ cpy = (ulong)simple_strtoul(argv[base], NULL, 16);
+ copy_num = CONFIG_BL2_COPY_NUM;
+ if (cpy >= copy_num) {
+ printk("max cpies %d\n", copy_num);
+ ret = CMD_RET_USAGE;
+ goto _out;
+ }
+ opts.offset = nand->size / copy_num * cpy;
+ opts.length = nand->size / copy_num;
+ }
+ } else {
+ /* whole boot area size */
+ opts.offset = 0;
+ opts.length = nand->size;
+ }
+ opts.jffs2 = 0;
+ opts.quiet = 0;
+ opts.spread = 0;
+ ret = nand_erase_opts(nand, &opts);
+
+ } else {
+ ret = CMD_RET_USAGE;
+ goto _out;
+ }
+
+_out:
+#if (CONFIG_AMLMTD_CURRDEV)
+ /* restore mtd device */
+ if (curr_mtd_dev != 0)
+ set_mtd_dev(curr_mtd_dev);
+#endif
+ return ret;
+}
+
+/* bl2 operations */
+static int do_bl2_ops(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ int ret = 0;
+ int copy_num = 4;
+ int i;
+ ulong cpy;
+ char *sub;
+ struct mtd_info *nand;
+ unsigned long addr;
+ int base = 2;
+ u64 off, maxsize;
+ size_t rwsize, limit, wsize;
+ /* fixme, using this?! */
+#if (CONFIG_AMLMTD_CURRDEV)
+ int curr_mtd_dev;
+#endif
+ printk("%s(): argc %d\n", __func__, argc);
+ dump_args(argc, argv);
+#if (CONFIG_AMLMTD_CURRDEV)
+ curr_mtd_dev = get_mtd_dev();
+ if (curr_mtd_dev != 0)
+ set_mtd_dev(0);
+#endif
+ nand = nand_info[0];
+ maxsize = nand->size;
+ limit = maxsize / CONFIG_BL2_COPY_NUM;
+ if (strlen(argv[1]) > 3)
+ sub = &argv[1][4];
+ else {
+ sub = argv[2];
+ base = 3;
+ }
+ if (!strcmp("info", sub)) {
+ printk("bl2 infos:\ncopies %d\n", CONFIG_BL2_COPY_NUM);
+ } else if (!strcmp("read", sub)) {
+ printk("%s() %s\n", __func__, sub);
+ if (argc - base < 3) {
+ ret = CMD_RET_USAGE;
+ goto _out;
+ }
+ addr = (ulong)simple_strtoul(argv[base], NULL, 16);
+ cpy = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
+ rwsize = (ulong)simple_strtoul(argv[base + 2], NULL, 16);
+ off = cpy * limit;
+ ret = nand_read_skip_bad(nand, off, &rwsize,
+ NULL, limit,
+ (u8 *)addr);
+ } else if (!strcmp("write", sub)) {
+ printk("%s() %s\n", __func__, sub);
+ if (argc - base < 2) {
+ ret = CMD_RET_USAGE;
+ goto _out;
+ }
+ addr = (ulong)simple_strtoul(argv[base], NULL, 16);
+ /* write all copies if off do not exist */
+ if (argc - base == 2) {
+ off = 0;
+ rwsize = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
+ copy_num = CONFIG_BL2_COPY_NUM;
+ } else {
+ cpy = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
+ off = cpy * limit;
+ rwsize = (ulong)simple_strtoul(argv[base + 2], NULL, 16);
+ copy_num = 1;
+ }
+ printf("%s() %d\n", __func__, copy_num);
+ wsize = rwsize;
+ for (i = 0; i < copy_num; i++) {
+ ret = nand_write_skip_bad(nand, off, &rwsize,
+ NULL, limit,
+ (u8 *)addr, 0);
+ if (ret)
+ rwsize = wsize;
+ off += nand->size/copy_num;
+ }
+ } else if (!strcmp("erase", sub)) {
+ nand_erase_options_t opts;
+ printk("%s() %s\n", __func__, sub);
+ memset(&opts, 0, sizeof(opts));
+ if (argc - base == 0) {
+ opts.offset = 0;
+ /* whole boot area size */
+ opts.length = nand->size;
+ } else {
+ copy_num = CONFIG_BL2_COPY_NUM;
+ cpy = (ulong)simple_strtoul(argv[base], NULL, 16);
+ if (cpy >= copy_num) {
+ printk("max cpies %d\n", copy_num);
+ ret = CMD_RET_USAGE;
+ goto _out;
+ }
+ opts.offset = nand->size / copy_num * cpy;
+ opts.length = nand->size / copy_num;
+ }
+ printf("%s, off 0x%llx, len 0x%llx\n", __func__, opts.offset, opts.length);
+
+ opts.jffs2 = 0;
+ opts.quiet = 0;
+ opts.spread = 0;
+ ret = nand_erase_opts(nand, &opts);
+
+ } else {
+ ret = CMD_RET_USAGE;
+ goto _out;
+ }
+
+_out:
+#if (CONFIG_AMLMTD_CURRDEV)
+ /* restore mtd device */
+ if (curr_mtd_dev != 0)
+ set_mtd_dev(curr_mtd_dev);
+#endif
+ return ret;
+}
+
+static int do_fip_ops(cmd_tbl_t * cmdtp, int flag, int argc, char * const argv[])
+{
+ int ret = 0;
+ int copy_num = 1;
+ int i;
+ char *sub;
+ struct mtd_info *nand;
+ ulong addr;
+ ulong cpy;
+ int base = 2;
+ u64 off, maxsize = CONFIG_TPL_SIZE_PER_COPY * CONFIG_NAND_TPL_COPY_NUM;
+ u64 fip_base;
+ size_t rwsize, wsize;
+
+ /* fixme, using this?! */
+#if (CONFIG_AMLMTD_CURRDEV)
+ int curr_mtd_dev;
+#endif
+ printk("%s(): argc %d\n", __func__, argc);
+ dump_args(argc, argv);
+#if (CONFIG_AMLMTD_CURRDEV)
+ curr_mtd_dev = get_mtd_dev();
+ if (curr_mtd_dev != 0)
+ set_mtd_dev(0);
+#endif
+ nand = nand_info[1];
+ if (strlen(argv[1]) > 3)
+ sub = &argv[1][4];
+ else {
+ sub = argv[2];
+ base = 3;
+ }
+ /*calculate the fip_start_addr*/
+ fip_base = 1024*nand->writesize + NAND_RSV_BLOCK_NUM*nand->erasesize;
+ if (!strcmp("read", sub)) {
+ printk("%s() %s\n", __func__, sub);
+ if (argc - base < 2) {
+ ret = CMD_RET_USAGE;
+ goto _out;
+ }
+ addr = (ulong)simple_strtoul(argv[base], NULL, 16);
+ off = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
+ rwsize = (ulong)simple_strtoul(argv[base + 2], NULL, 16);
+ off +=fip_base;
+ ret = nand_read_skip_bad(nand,
+ off, &rwsize, NULL, maxsize, (u8 *)addr);
+ } else if (!strcmp("write", sub)) {
+ printk("%s() %s\n", __func__, sub);
+ if (argc - base < 2) {
+ ret = CMD_RET_USAGE;
+ goto _out;
+ }
+ addr = (ulong)simple_strtoul(argv[base], NULL, 16);
+ if (argc - base == 2) {
+ off = fip_base;
+ rwsize = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
+ copy_num = CONFIG_NAND_TPL_COPY_NUM;
+ printk("%s %d: off=0x%llx rwsize=0x%zx\n",
+ __func__, __LINE__, off, rwsize);
+
+ } else {
+ //addr off size
+ off = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
+ off += fip_base;
+ rwsize = (ulong)simple_strtoul(argv[base + 2], NULL, 16);
+ copy_num = 1;
+ }
+ if (rwsize > CONFIG_TPL_SIZE_PER_COPY) {
+ printk("size %ld > max per cpy %d\n", rwsize,
+ CONFIG_NAND_TPL_COPY_NUM);
+ ret = CMD_RET_USAGE;
+ goto _out;
+ }
+ wsize = rwsize;
+ /* fixme, write it once! */
+ for (i = 0; i < copy_num; i++) {
+ printk("cpy %d\n", i);
+ ret = nand_write_skip_bad(nand,
+ off, &rwsize, NULL, CONFIG_TPL_SIZE_PER_COPY, (u8 *)addr, 0);
+ if (ret)
+ rwsize = wsize;
+ off += CONFIG_TPL_SIZE_PER_COPY;
+ }
+
+ } else if (!strcmp("erase", sub)) {
+ nand_erase_options_t opts;
+ printk("%s() %s, base %d\n", __func__, sub, base);
+ memset(&opts, 0, sizeof(opts));
+ if (argc - base == 0) {
+ opts.offset = fip_base;
+ /* whole boot area size */
+ opts.length = maxsize;
+ } else {
+ cpy = (ulong)simple_strtoul(argv[base], NULL, 16);
+ if (cpy >= CONFIG_NAND_TPL_COPY_NUM) {
+ printk("max cpies %d\n", CONFIG_NAND_TPL_COPY_NUM);
+ ret = CMD_RET_USAGE;
+ goto _out;
+ }
+ opts.offset = fip_base + cpy * CONFIG_TPL_SIZE_PER_COPY;
+ opts.length = CONFIG_TPL_SIZE_PER_COPY;
+ }
+ opts.jffs2 = 0;
+ opts.quiet = 0;
+ opts.spread = 0;
+ ret = nand_erase_opts(nand, &opts);
+ } else if (!strcmp("info", sub)) {
+ printk("tpl infos:\ncopies %d, size/copy 0x%x\n",
+ CONFIG_NAND_TPL_COPY_NUM, CONFIG_TPL_SIZE_PER_COPY);
+ } else{
+ ret = CMD_RET_USAGE;
+ goto _out;
+ }
+_out:
+#if (CONFIG_AMLMTD_CURRDEV)
+ /* restore mtd device */
+ if (curr_mtd_dev != 0)
+ set_mtd_dev(curr_mtd_dev);
+#endif
+ return ret;
+}
+
+/****operations for dtb.****/
+static int do_dtb_ops(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int ret = 0;
+ printk("%s(): argc %d\n", __func__, argc);
+ dump_args(argc, argv);
+ char *sub;
+ int base = 2;
+ unsigned long addr;
+ u64 size = 0;
+
+ if (strlen(argv[1]) > 3)
+ sub = &argv[1][4];
+ else {
+ sub = argv[2];
+ base = 3;
+ }
+
+ if (!strcmp("read", sub)) {
+ printk("%s() %s\n", __func__, sub);
+ addr = (ulong)simple_strtoul(argv[base], NULL, 16);
+ size = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
+ ret = meson_rsv_dtb_read((u8 *)addr, (int)size);
+ printk("%s(): %llu bytes %s : %s\n",
+ __func__,
+ size,
+ sub,
+ ret ? "ERROR" : "OK");
+ } else if (!strcmp("write", sub)) {
+ printk("%s() %s\n", __func__, sub);
+ addr = (ulong)simple_strtoul(argv[base], NULL, 16);
+ size = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
+ ret = meson_rsv_dtb_write((u8 *)addr, (unsigned int)size);
+ printk("%s(): %llu bytes %s : %s\n",
+ __func__,
+ size,
+ sub,
+ ret ? "ERROR" : "OK");
+ } else if (!strcmp("erase", sub)) {
+ printk("%s() %s\n", __func__, sub);
+ ret = meson_rsv_dtb_erase();
+ printk("%s() erase %s\n", __func__, ret ? "Fail" : "Okay");
+ } else
+ return CMD_RET_USAGE;
+
+ return ret;
+}
+
+/*
+ * operations for key.
+ * should never be used by users, just for nand team debug.
+ */
+static int do_key_ops(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int ret = 0;
+ printk("%s(): argc %d\n", __func__, argc);
+ dump_args(argc, argv);
+ char *sub;
+ int base = 2;
+ unsigned long addr;
+ u64 size = 0;
+
+ if (strlen(argv[1]) > 3)
+ sub = &argv[1][4];
+ else {
+ sub = argv[2];
+ base = 3;
+ }
+
+ if (!strcmp("read", sub)) {
+ printk("%s() %s\n", __func__, sub);
+ addr = (ulong)simple_strtoul(argv[base], NULL, 16);
+ size = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
+ ret = meson_rsv_key_read((u8 *)addr, (int)size);
+ printk("%s(): %llu bytes %s : %s\n",
+ __func__,
+ size,
+ sub,
+ ret ? "ERROR" : "OK");
+ } else if (!strcmp("write", sub)) {
+ printk("%s() %s\n", __func__, sub);
+ addr = (ulong)simple_strtoul(argv[base], NULL, 16);
+ size = (ulong)simple_strtoul(argv[base + 1], NULL, 16);
+ ret = meson_rsv_key_write((u8 *)addr, (int)size);
+ printk("%s(): %llu bytes %s : %s\n",
+ __func__,
+ size,
+ sub,
+ ret ? "ERROR" : "OK");
+ } else if (!strcmp("erase", sub)) {
+ printk("%s() %s\n", __func__, sub);
+ ret = meson_rsv_key_erase();
+ printk("%s() erase %s\n", __func__, ret ? "Fail" : "Okay");
+ } else
+ return CMD_RET_USAGE;
+
+ return ret;
+}
+
+/*for test*/
+extern int meson_rsv_bbt_erase(void);
+static int do_bbt_ops(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ int ret = 0;
+ printk("%s(): argc %d\n", __func__, argc);
+ dump_args(argc, argv);
+ char *sub;
+
+ if (strlen(argv[1]) > 3)
+ sub = &argv[1][4];
+ else {
+ sub = argv[2];
+ }
+
+ if (!strcmp("erase", sub)) {
+ printk("%s() %s\n", __func__, sub);
+ ret = meson_rsv_bbt_erase();
+ printk("%s() erase %s\n", __func__, ret ? "Fail" : "Okay");
+ } else
+ return CMD_RET_USAGE;
+
+ return ret;
+}
+
+
+static cmd_tbl_t cmd_amlmtd_sub[] = {
+ U_BOOT_CMD_MKENT(rom, 5, 0, do_rom_ops, "", ""),
+ U_BOOT_CMD_MKENT(bl2, 5, 0, do_bl2_ops, "", ""),
+ U_BOOT_CMD_MKENT(fip, 5, 0, do_fip_ops, "", ""),
+ U_BOOT_CMD_MKENT(dtb, 5, 0, do_dtb_ops, "", ""),
+ U_BOOT_CMD_MKENT(key, 5, 0, do_key_ops, "", ""),
+ U_BOOT_CMD_MKENT(bbt, 5, 0, do_bbt_ops, "", ""),
+};
+
+static int do_amlmtd(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ cmd_tbl_t *c;
+ char subcmd[4];
+
+ if (argc < 2) return CMD_RET_USAGE;
+ /* process subcmd which is longger than 3 characaters */
+ c = find_cmd_tbl(argv[1], cmd_amlmtd_sub, ARRAY_SIZE(cmd_amlmtd_sub));
+ if (!c) {
+ strncpy(subcmd, argv[1], 3);
+ if (strlen(argv[1]) > 3) {
+ subcmd[3] = 0;
+ }
+ printk("sub cmd %s\n", subcmd);
+ c = find_cmd_tbl(subcmd, cmd_amlmtd_sub, ARRAY_SIZE(cmd_amlmtd_sub));
+ if (c) {
+ printf("new argv[1] %s\n", argv[1]);
+ return c->cmd(cmdtp, flag, argc, argv);
+ }
+ } else {
+ return c->cmd(cmdtp, flag, argc, argv);
+ }
+
+ return CMD_RET_USAGE;
+}
+
+
+#ifdef CONFIG_SYS_LONGHELP
+static char amlmtd_help_text[] =
+ "amlnf bl2_info - show bl2 infos\n"
+ "amlnf bl2_erase [cpy] - erase bl2 area, erase all without cpy!\n"
+ "amlnf bl2_read addr cpy size - read bl2 by cpy.\n"
+ "amlnf bl2_write addr [cpy] size - write bl2.\n"
+ "\t[cpy] copy to operate\n\twirte all copies if without cpy\n"
+ "amlnf fip_info - show fip infos\n"
+ "amlnf fip_read addr off size - read fip.\n"
+ "amlnf fip_write addr [off] size - write fip.\n"
+ "\t[off] inside offset\n\twirte all copies if without off\n"
+ "amlnf fip_erase [cpy] - erase fip area, erase all without cpy!\n"
+
+ "amlnf dtb_read/write addr size - read/write dtd.\n"
+ "amlnf dtb_erase - erase dtb area!\n"
+ "amlnf key_read/write addr size - read/write keys.\n"
+ "amlnf key_erase - erase keys!\n"
+ "";
+#endif
+U_BOOT_CMD(
+ amlnf, CONFIG_SYS_MAXARGS, 0, do_amlmtd,
+ "aml mtd nand sub-system",
+ amlmtd_help_text
+);
diff --git a/drivers/mtd/nand/raw/aml_nand/meson_nand.c b/drivers/mtd/nand/raw/aml_nand/meson_nand.c
new file mode 100644
index 0000000..e54279f
--- /dev/null
+++ b/drivers/mtd/nand/raw/aml_nand/meson_nand.c
@@ -0,0 +1,923 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <linux/err.h>
+#include <asm/cache.h>
+//#include <asm/arch/secure_apb.h>
+#include <amlogic/cpu_id.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/mtd/nand_ecc.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+#include <dm/root.h>
+#include <dm/lists.h>
+#include <dm/util.h>
+
+#include <fdtdec.h>
+#include <memalign.h>
+#include <linux/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/clock.h>
+#include <clk.h>
+#include <dm/pinctrl.h>
+#include <asm/arch/register.h>
+
+#include "aml_nand.h"
+#include "version.h"
+#include <time.h>
+
+struct hw_controller *controller = NULL;
+
+extern struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
+extern void mtd_store_set(struct mtd_info *mtd, int dev);
+extern struct aml_pre_scan *pre_scan;;
+
+#ifdef CONFIG_MTD_DEVICE
+static __attribute__((unused)) char dev_name[CONFIG_SYS_MAX_NAND_DEVICE][8];
+#endif
+
+static struct aml_nand_platform aml_nand_mid_platform[] = {
+ {
+ .name = NAND_BOOT_NAME,
+ .chip_enable_pad = AML_NAND_CE0,
+ .ready_busy_pad = AML_NAND_CE0,
+ .platform_nand_data = {
+ .chip = {
+ .nr_chips = 1,
+ .options = (NAND_TIMING_MODE5 | NAND_ECC_BCH60_1K_MODE),
+ },
+ },
+ .rbpin_mode=1,
+ .short_pgsz=384,
+ .ran_mode=0,
+ .T_REA = 20,
+ .T_RHOH = 15,
+ },
+ {
+ .name = NAND_NORMAL_NAME,
+ .chip_enable_pad = (AML_NAND_CE0) | (AML_NAND_CE1 << 4),
+ .ready_busy_pad = (AML_NAND_CE0) | (AML_NAND_CE1 << 4),
+ .platform_nand_data = {
+ .chip = {
+ .nr_chips = 1,
+ /* moved to board config as different board
+ * may have different partition table
+ */
+ /* .nr_partitions = ARRAY_SIZE(normal_partition_info),
+ .partitions = normal_partition_info,*/
+ .options = (NAND_TIMING_MODE5
+ | NAND_ECC_BCH60_1K_MODE
+ | NAND_TWO_PLANE_MODE),
+ },
+ },
+ .rbpin_mode = 1,
+ .short_pgsz = 0,
+ .ran_mode = 0,
+ .T_REA = 20,
+ .T_RHOH = 15,
+ }
+};
+
+struct aml_nand_device aml_nand_mid_device = {
+ .aml_nand_platform = aml_nand_mid_platform,
+ .dev_num = ARRAY_SIZE(aml_nand_mid_platform),
+};
+
+#define ECC_INFORMATION(name_a, bch_a, size_a, parity_a, user_a) \
+ {\
+ .name=name_a,\
+ .bch_mode=bch_a,\
+ .bch_unit_size=size_a,\
+ .bch_bytes=parity_a,\
+ .user_byte_mode=user_a\
+ }
+
+static struct aml_nand_bch_desc m3_bch_list[] = {
+ [0] = ECC_INFORMATION("NAND_RAW_MODE",
+ NAND_ECC_SOFT_MODE,
+ 0,
+ 0,
+ 0),
+ [1] = ECC_INFORMATION("NAND_BCH8_MODE",
+ NAND_ECC_BCH8_MODE,
+ NAND_ECC_UNIT_SIZE,
+ NAND_BCH8_ECC_SIZE,
+ 2),
+ [2] = ECC_INFORMATION("NAND_BCH8_1K_MODE" ,
+ NAND_ECC_BCH8_1K_MODE,
+ NAND_ECC_UNIT_1KSIZE,
+ NAND_BCH8_1K_ECC_SIZE,
+ 2),
+ [3] = ECC_INFORMATION("NAND_BCH24_1K_MODE" ,
+ NAND_ECC_BCH24_1K_MODE,
+ NAND_ECC_UNIT_1KSIZE,
+ NAND_BCH24_1K_ECC_SIZE,
+ 2),
+ [4] = ECC_INFORMATION("NAND_BCH30_1K_MODE" ,
+ NAND_ECC_BCH30_1K_MODE,
+ NAND_ECC_UNIT_1KSIZE,
+ NAND_BCH30_1K_ECC_SIZE,
+ 2),
+ [5] = ECC_INFORMATION("NAND_BCH40_1K_MODE" ,
+ NAND_ECC_BCH40_1K_MODE,
+ NAND_ECC_UNIT_1KSIZE,
+ NAND_BCH40_1K_ECC_SIZE,
+ 2),
+ [6] = ECC_INFORMATION("NAND_BCH50_1K_MODE" ,
+ NAND_ECC_BCH50_1K_MODE,
+ NAND_ECC_UNIT_1KSIZE,
+ NAND_BCH50_1K_ECC_SIZE,
+ 2),
+ [7] = ECC_INFORMATION("NAND_BCH60_1K_MODE" ,
+ NAND_ECC_BCH60_1K_MODE,
+ NAND_ECC_UNIT_1KSIZE,
+ NAND_BCH60_1K_ECC_SIZE,
+ 2),
+ [8] = ECC_INFORMATION("NAND_SHORT_MODE" ,
+ NAND_ECC_SHORT_MODE,
+ NAND_ECC_UNIT_SHORT,
+ NAND_BCH60_1K_ECC_SIZE,
+ 2),
+};
+
+extern uint8_t nand_boot_flag;
+
+unsigned char pagelist_hynix256[128] = {
+ 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x0A, 0x0B,
+ 0x0E, 0x0F, 0x12, 0x13, 0x16, 0x17, 0x1A, 0x1B,
+ 0x1E, 0x1F, 0x22, 0x23, 0x26, 0x27, 0x2A, 0x2B,
+ 0x2E, 0x2F, 0x32, 0x33, 0x36, 0x37, 0x3A, 0x3B,
+
+ 0x3E, 0x3F, 0x42, 0x43, 0x46, 0x47, 0x4A, 0x4B,
+ 0x4E, 0x4F, 0x52, 0x53, 0x56, 0x57, 0x5A, 0x5B,
+ 0x5E, 0x5F, 0x62, 0x63, 0x66, 0x67, 0x6A, 0x6B,
+ 0x6E, 0x6F, 0x72, 0x73, 0x76, 0x77, 0x7A, 0x7B,
+
+ 0x7E, 0x7F, 0x82, 0x83, 0x86, 0x87, 0x8A, 0x8B,
+ 0x8E, 0x8F, 0x92, 0x93, 0x96, 0x97, 0x9A, 0x9B,
+ 0x9E, 0x9F, 0xA2, 0xA3, 0xA6, 0xA7, 0xAA, 0xAB,
+ 0xAE, 0xAF, 0xB2, 0xB3, 0xB6, 0xB7, 0xBA, 0xBB,
+
+ 0xBE, 0xBF, 0xC2, 0xC3, 0xC6, 0xC7, 0xCA, 0xCB,
+ 0xCE, 0xCF, 0xD2, 0xD3, 0xD6, 0xD7, 0xDA, 0xDB,
+ 0xDE, 0xDF, 0xE2, 0xE3, 0xE6, 0xE7, 0xEA, 0xEB,
+ 0xEE, 0xEF, 0xF2, 0xF3, 0xF6, 0xF7, 0xFA, 0xFB,
+};
+unsigned char pagelist_1ynm_hynix256_mtd[128] = {
+ 0x00, 0x01, 0x03, 0x05, 0x07, 0x09, 0x0b, 0x0d,
+ 0x0f, 0x11, 0x13, 0x15, 0x17, 0x19, 0x1b, 0x1d,
+ 0x1f, 0x21, 0x23, 0x25, 0x27, 0x29, 0x2b, 0x2d,
+ 0x2f, 0x31, 0x33, 0x35, 0x37, 0x39, 0x3b, 0x3d,
+ 0x3f, 0x41, 0x43, 0x45, 0x47, 0x49, 0x4b, 0x4d,
+ 0x4f, 0x51, 0x53, 0x55, 0x57, 0x59, 0x5b, 0x5d,
+ 0x5f, 0x61, 0x63, 0x65, 0x67, 0x69, 0x6b, 0x6d,
+ 0x6f, 0x71, 0x73, 0x75, 0x77, 0x79, 0x7b, 0x7d,
+ 0x7f, 0x81, 0x83, 0x85, 0x87, 0x89, 0x8b, 0x8d,
+ 0x8f, 0x91, 0x93, 0x95, 0x97, 0x99, 0x9b, 0x9d,
+ 0x9f, 0xa1, 0xA3, 0xA5, 0xA7, 0xA9, 0xAb, 0xAd,
+ 0xAf, 0xb1, 0xB3, 0xB5, 0xB7, 0xB9, 0xBb, 0xBd,
+ 0xBf, 0xc1, 0xC3, 0xC5, 0xC7, 0xC9, 0xCb, 0xCd,
+ 0xCf, 0xd1, 0xD3, 0xD5, 0xD7, 0xD9, 0xDb, 0xDd,
+ 0xDf, 0xe1, 0xE3, 0xE5, 0xE7, 0xE9, 0xEb, 0xEd,
+ 0xEf, 0xf1, 0xF3, 0xF5, 0xF7, 0xF9, 0xFb, 0xFd,
+};
+
+static int controller_select_chip(struct hw_controller *controller,
+ u8 chipnr)
+{
+ int ret = 0;
+
+ switch (chipnr) {
+ case 0:
+ case 1:
+ case 2:
+ case 3:
+ controller->chip_selected = controller->ce_enable[chipnr];
+ controller->rb_received = controller->rb_enable[chipnr];
+
+ NFC_SEND_CMD_IDLE(controller, 0);
+ break;
+ default:
+ BUG();
+ ret = -12;
+ break;
+ }
+ return ret;
+}
+
+static void m3_nand_select_chip(struct aml_nand_chip *aml_chip, int chipnr)
+{
+ controller_select_chip(controller, chipnr);
+ return;
+}
+
+void aml_nfc_get_clk_name(struct hw_controller *controller)
+{
+ struct udevice *clk_udevice, *dev = controller->device;
+
+ uclass_get_device_by_name(UCLASS_CLK, "amlogic,g12a-clkc", &clk_udevice);
+
+ clk_get_by_name(dev, "fdiv2", &controller->fdiv2);
+ clk_get_by_name(dev, "xtal", &controller->xtal);
+ clk_get_by_name(dev, "mux", &controller->mux);
+ clk_get_by_name(dev, "div", &controller->div);
+ clk_get_by_name(dev, "gate", &controller->gate);
+
+ clk_enable(&controller->gate);
+}
+
+void get_sys_clk_rate_mtd(struct hw_controller *controller, int *rate)
+{
+ int bus_cycle, bus_timing;
+ unsigned int clk, clk_div, clk_src;
+ int clk_freq = *rate * 1000000;
+ unsigned int always_on = 0x1 << 28;
+
+ if (clk_freq <= 24) {
+ clk = 24000000;
+ clk_src = 0;
+ clk_enable(&controller->xtal); // for c1 clk arthitecture compatitable. xtal was not controlled by clk driver.
+ clk_set_rate(&controller->div, clk);
+ clk_div = 1;
+ bus_cycle = 4;
+ bus_timing = 3;
+ goto __NAND_CLK_CFG__;
+ } else {
+ clk = 1000000000;
+ clk_src = 1;
+ clk_disable(&controller->xtal);
+ clk_set_parent(&controller->mux, &controller->fdiv2);
+ clk_set_rate(&controller->div, clk);
+ bus_cycle = 6;
+ bus_timing = bus_cycle + 1;
+ }
+ clk_div = clk /clk_freq;
+ if (clk % clk_freq)
+ clk_div++;
+__NAND_CLK_CFG__:
+ AMLNF_WRITE_REG(controller->nand_clk_reg,
+ (clk_src << 6) | clk_div | always_on | (1 << 31) | (2 << 8));
+ printf("%s:gclock=%x\n", __func__,
+ AMLNF_READ_REG(controller->nand_clk_reg));
+ NFC_SET_CFG(controller, 0);
+ NFC_SET_TIMING_ASYC(controller, bus_timing, (bus_cycle - 1));
+ NFC_SEND_CMD(controller, 1<<31);
+ printf("%s:P_NAND_CFG=%x\n", __func__,
+ AMLNF_READ_REG(controller->reg_base + P_NAND_CFG));
+}
+
+static void m3_nand_hw_init(struct aml_nand_chip *aml_chip)
+{
+ int sys_clk_rate = 200;
+
+ get_sys_clk_rate_mtd(controller, &sys_clk_rate);
+
+ return;
+}
+
+static void m3_nand_adjust_timing(struct aml_nand_chip *aml_chip)
+{
+ int sys_clk_rate;
+
+ if (!aml_chip->T_REA)
+ aml_chip->T_REA = 20;
+ if (!aml_chip->T_RHOH)
+ aml_chip->T_RHOH = 15;
+
+ if (aml_chip->T_REA > 30)
+ sys_clk_rate = 112;
+ else if (aml_chip->T_REA > 16)
+ sys_clk_rate = 200;
+ else
+ sys_clk_rate = 250;
+
+ get_sys_clk_rate_mtd(controller, &sys_clk_rate);
+}
+
+static int m3_nand_options_confirm(struct aml_nand_chip *aml_chip)
+{
+ struct nand_chip *chip = &aml_chip->chip;
+ struct mtd_info *mtd = &chip->mtd;
+ struct aml_nand_platform *plat = aml_chip->platform;
+ struct aml_nand_bch_desc *ecc_supports = aml_chip->bch_desc;
+ unsigned int max_bch_mode = aml_chip->max_bch_mode;
+ unsigned int options_selected = 0, options_support = 0, options_define;
+ unsigned int eep_need_oobsize = 0, ecc_page_num = 0, ecc_bytes;
+ int error = 0, i, valid_chip_num = 0;
+ cpu_id_t cpu_id = get_cpu_id();
+
+ if (!strncmp((char*)plat->name,
+ NAND_BOOT_NAME,
+ strlen((const char*)NAND_BOOT_NAME))) {
+ eep_need_oobsize =
+ ecc_supports[8].bch_bytes + ecc_supports[8].user_byte_mode;
+ ecc_page_num =
+ aml_chip->page_size / ecc_supports[8].bch_unit_size;
+ aml_chip->boot_oob_fill_cnt = aml_chip->oob_size -
+ eep_need_oobsize * ecc_page_num;
+ }
+
+ /*select fit ecc mode by flash oob size */
+ for (i = max_bch_mode - 1; i > 0; i--) {
+ eep_need_oobsize =
+ ecc_supports[i].bch_bytes + ecc_supports[i].user_byte_mode;
+ ecc_page_num =
+ aml_chip->page_size / ecc_supports[i].bch_unit_size;
+ ecc_bytes = aml_chip->oob_size / ecc_page_num;
+ if (ecc_bytes >= eep_need_oobsize) {
+ options_support = ecc_supports[i].bch_mode;
+ break;
+ }
+ }
+ /**aml_chip->oob_size equal nand oobsize**/
+ aml_chip->oob_fill_cnt =
+ aml_chip->oob_size - eep_need_oobsize * ecc_page_num;
+ printk("oob_fill_cnt =%d oob_size =%d, bch_bytes =%d\n",
+ aml_chip->oob_fill_cnt,
+ aml_chip->oob_size,
+ ecc_supports[i].bch_bytes);
+ printk("ecc mode:%d ecc_page_num=%d eep_need_oobsize=%d\n",
+ options_support, ecc_page_num, eep_need_oobsize);
+
+ printk("options_support :%d\n", options_support);
+ if (options_support != NAND_ECC_SOFT_MODE) {
+ chip->ecc.read_page_raw = aml_nand_read_page_raw;
+ chip->ecc.write_page_raw = aml_nand_write_page_raw;
+ chip->ecc.read_page = aml_nand_read_page_hwecc;
+ chip->ecc.write_page = aml_nand_write_page_hwecc;
+ chip->ecc.read_oob = aml_nand_read_oob;
+ chip->ecc.write_oob = aml_nand_write_oob;
+ chip->block_bad = aml_nand_block_bad;
+ chip->block_markbad = aml_nand_block_markbad;
+ chip->ecc.mode = NAND_ECC_HW;
+ } else {
+ chip->ecc.read_page_raw = aml_nand_read_page_raw;
+ chip->ecc.write_page_raw = aml_nand_write_page_raw;
+ chip->ecc.mode = NAND_ECC_SOFT;
+ }
+ chip->write_buf = aml_nand_dma_write_buf;
+ chip->read_buf = aml_nand_dma_read_buf;
+
+ if ((mtd->writesize <= 2048) ||
+ (cpu_id.family_id == MESON_CPU_MAJOR_ID_AXG) ||
+ (cpu_id.family_id == MESON_CPU_MAJOR_ID_TXHD)||
+ (cpu_id.family_id == MESON_CPU_MAJOR_ID_C1) ||
+ (cpu_id.family_id == MESON_CPU_MAJOR_ID_C2) ||
+ (cpu_id.family_id == MESON_CPU_MAJOR_ID_S4))
+ options_support = NAND_ECC_BCH8_MODE;
+
+ switch (options_support) {
+
+ case NAND_ECC_BCH8_MODE:
+ chip->ecc.strength = 8;
+ chip->ecc.size = NAND_ECC_UNIT_SIZE;
+ chip->ecc.bytes = NAND_BCH8_ECC_SIZE;
+ aml_chip->bch_mode = NAND_ECC_BCH8;
+ aml_chip->user_byte_mode = 2;
+ aml_chip->ecc_cnt_limit = 6;
+ aml_chip->ecc_max = 8;
+ chip->ecc.steps = mtd->writesize / chip->ecc.size;
+ break;
+
+ case NAND_ECC_BCH8_1K_MODE:
+ chip->ecc.strength = 8;
+ chip->ecc.size = NAND_ECC_UNIT_1KSIZE;
+ chip->ecc.bytes = NAND_BCH8_1K_ECC_SIZE;
+ aml_chip->bch_mode = NAND_ECC_BCH8_1K;
+ aml_chip->user_byte_mode = 2;
+ aml_chip->ecc_cnt_limit = 6;
+ aml_chip->ecc_max = 8;
+ chip->ecc.steps = mtd->writesize / chip->ecc.size;
+ break;
+
+ case NAND_ECC_BCH24_1K_MODE:
+ chip->ecc.strength = 24;
+ chip->ecc.size = NAND_ECC_UNIT_1KSIZE;
+ chip->ecc.bytes = NAND_BCH24_1K_ECC_SIZE;
+ aml_chip->bch_mode = NAND_ECC_BCH24_1K;
+ aml_chip->user_byte_mode = 2;
+ aml_chip->ecc_cnt_limit = 22;
+ aml_chip->ecc_max = 24;
+ chip->ecc.steps = mtd->writesize / chip->ecc.size;
+ break;
+
+ case NAND_ECC_BCH30_1K_MODE:
+ chip->ecc.strength = 30;
+ chip->ecc.size = NAND_ECC_UNIT_1KSIZE;
+ chip->ecc.bytes = NAND_BCH30_1K_ECC_SIZE;
+ aml_chip->bch_mode = NAND_ECC_BCH30_1K;
+ aml_chip->user_byte_mode = 2;
+ aml_chip->ecc_cnt_limit = 26;
+ aml_chip->ecc_max = 30;
+ chip->ecc.steps = mtd->writesize / chip->ecc.size;
+ break;
+
+ case NAND_ECC_BCH40_1K_MODE:
+ chip->ecc.strength = 40;
+ chip->ecc.size = NAND_ECC_UNIT_1KSIZE;
+ chip->ecc.bytes = NAND_BCH40_1K_ECC_SIZE;
+ aml_chip->bch_mode = NAND_ECC_BCH40_1K;
+ aml_chip->user_byte_mode = 2;
+ aml_chip->ecc_cnt_limit = 34;
+ aml_chip->ecc_max = 40;
+ chip->ecc.steps = mtd->writesize / chip->ecc.size;
+ break;
+
+ case NAND_ECC_BCH50_1K_MODE:
+ chip->ecc.strength = 40;
+ chip->ecc.size = NAND_ECC_UNIT_1KSIZE;
+ chip->ecc.bytes = NAND_BCH50_1K_ECC_SIZE;
+ aml_chip->bch_mode = NAND_ECC_BCH50_1K;
+ aml_chip->user_byte_mode = 2;
+ aml_chip->ecc_cnt_limit = 45;
+ aml_chip->ecc_max = 50;
+ chip->ecc.steps = mtd->writesize / chip->ecc.size;
+ break;
+
+ case NAND_ECC_BCH60_1K_MODE:
+ chip->ecc.strength = 60;
+ chip->ecc.size = NAND_ECC_UNIT_1KSIZE;
+ chip->ecc.bytes = NAND_BCH60_1K_ECC_SIZE;
+ aml_chip->bch_mode = NAND_ECC_BCH60_1K;
+ aml_chip->user_byte_mode = 2;
+ aml_chip->ecc_cnt_limit = 55;
+ aml_chip->ecc_max = 60;
+ chip->ecc.steps = mtd->writesize / chip->ecc.size;
+ break;
+
+ case NAND_ECC_SHORT_MODE:
+ chip->ecc.strength = 60;
+ chip->ecc.size = NAND_ECC_UNIT_SHORT;
+ chip->ecc.bytes = NAND_BCH60_1K_ECC_SIZE;
+ aml_chip->bch_mode = NAND_ECC_BCH_SHORT;
+ aml_chip->user_byte_mode = 2;
+ aml_chip->ecc_cnt_limit = 55;
+ aml_chip->ecc_max = 60;
+ chip->ecc.steps = mtd->writesize / 512;
+ break;
+ /*not support for amlogic chip*/
+ case NAND_ECC_SOFT_MODE:
+ aml_chip->user_byte_mode = 1;
+ aml_chip->bch_mode = 0;
+ /*don't care*/
+ aml_chip->ecc_cnt_limit = 9;
+ aml_chip->ecc_max = 16;
+ break;
+ default :
+ printk("unknow ecc mode, error!");
+ error = -ENXIO;
+ break;
+ }
+
+ options_selected =
+ plat->platform_nand_data.chip.options & NAND_INTERLEAVING_OPTIONS_MASK;
+ options_define = (aml_chip->options & NAND_INTERLEAVING_OPTIONS_MASK);
+ if (options_selected > options_define) {
+ printk("INTERLEAV change! \n");
+ options_selected = options_define;
+ }
+ switch (options_selected) {
+ case NAND_INTERLEAVING_MODE:
+ aml_chip->ops_mode |= AML_INTERLEAVING_MODE;
+ mtd->erasesize *= aml_chip->internal_chipnr;
+ mtd->writesize *= aml_chip->internal_chipnr;
+ mtd->oobsize *= aml_chip->internal_chipnr;
+ break;
+ default:
+ break;
+ }
+
+ options_selected =
+ plat->platform_nand_data.chip.options & NAND_PLANE_OPTIONS_MASK;
+ options_define = (aml_chip->options & NAND_PLANE_OPTIONS_MASK);
+ printf("options_selected: 0x%x, options_define:0x%x\n",options_selected,
+ options_define);
+ if (options_selected > options_define) {
+ printk("PLANE change!\n");
+ options_selected = options_define;
+ }
+
+ valid_chip_num = 0;
+ for (i=0; i < controller->chip_num; i++)
+ if (aml_chip->valid_chip[i])
+ valid_chip_num++;
+ if (aml_chip->ops_mode & AML_INTERLEAVING_MODE)
+ valid_chip_num *= aml_chip->internal_chipnr;
+
+ if (valid_chip_num > 2) {
+ aml_chip->plane_num = 1;
+ printk("detect valid_chip_num over 2\n");
+ } else {
+ switch (options_selected) {
+ case NAND_TWO_PLANE_MODE:
+ aml_chip->plane_num = 2;
+ mtd->erasesize *= 2;
+ mtd->writesize *= 2;
+ mtd->oobsize *= 2;
+ printk("two plane!@\n");
+ break;
+ default:
+ aml_chip->plane_num = 1;
+ break;
+ }
+ }
+
+ printk("plane_num=%d writesize=0x%x ecc.size=0x%0x bch_mode=%d\n",
+ aml_chip->plane_num,
+ mtd->writesize,
+ chip->ecc.size,
+ aml_chip->bch_mode);
+
+ return error;
+}
+
+
+static int aml_platform_dma_waiting(struct aml_nand_chip *aml_chip)
+{
+ unsigned time_out_cnt = 0;
+
+ NFC_SEND_CMD_IDLE(controller, 0);
+ NFC_SEND_CMD_IDLE(controller, 0);
+ do {
+ if (NFC_CMDFIFO_SIZE(controller) <= 0)
+ break;
+ }while (time_out_cnt++ <= AML_DMA_BUSY_TIMEOUT);
+
+ if (time_out_cnt < AML_DMA_BUSY_TIMEOUT)
+ return 0;
+
+ return -EBUSY;
+}
+
+static int m3_nand_dma_write(struct aml_nand_chip *aml_chip,
+ unsigned char *buf, int len, unsigned bch_mode)
+{
+ int ret = 0;
+ unsigned dma_unit_size = 0, count = 0;
+ struct nand_chip *chip = &aml_chip->chip;
+ struct mtd_info *mtd = &chip->mtd;
+ uint32_t temp;
+
+ if (bch_mode == NAND_ECC_NONE)
+ count = 1;
+ else if (bch_mode == NAND_ECC_BCH_SHORT) {
+ dma_unit_size = (chip->ecc.size >> 3);
+ /*caculate ecc pages cnt*/
+ count = len/chip->ecc.size;
+ }
+ else
+ count = len/chip->ecc.size;
+
+ flush_dcache_range((unsigned long)buf, (unsigned long)buf + len);
+ flush_dcache_range((unsigned long)aml_chip->user_info_buf,
+ (unsigned long)aml_chip->user_info_buf + count*PER_INFO_BYTE);
+
+ NFC_SEND_CMD_ADL(controller, (u32)(unsigned long)buf);
+ NFC_SEND_CMD_ADH(controller, (u32)(unsigned long)buf);
+ NFC_SEND_CMD_AIL(controller, (u32)(unsigned long)aml_chip->user_info_buf);
+ NFC_SEND_CMD_AIH(controller, (u32)(unsigned long)aml_chip->user_info_buf);
+
+ if (aml_chip->ran_mode) {
+ temp = mtd->writesize>>chip->page_shift;
+ if (aml_chip->plane_num == 2)
+ NFC_SEND_CMD_SEED(controller,
+ (aml_chip->page_addr / temp) * temp);
+ else
+ NFC_SEND_CMD_SEED(controller, aml_chip->page_addr);
+ }
+ if (!bch_mode)
+ NFC_SEND_CMD_M2N_RAW(controller, 0, len);
+ else
+ NFC_SEND_CMD_M2N(controller, aml_chip->ran_mode,
+ ((bch_mode == NAND_ECC_BCH_SHORT)?aml_chip->bch_info:bch_mode),
+ ((bch_mode == NAND_ECC_BCH_SHORT)?1:0), dma_unit_size, count);
+
+ ret = aml_platform_dma_waiting(aml_chip);
+
+ if (aml_chip->oob_fill_cnt >0) {
+ NFC_SEND_CMD_M2N_RAW(controller,
+ aml_chip->ran_mode, aml_chip->oob_fill_cnt);
+ ret = aml_platform_dma_waiting(aml_chip);
+ }
+ return ret;
+}
+
+static int m3_nand_dma_read(struct aml_nand_chip *aml_chip,
+ unsigned char *buf, int len, unsigned bch_mode)
+{
+ volatile unsigned int * info_buf=0;
+ volatile int cmp=0;
+
+ struct nand_chip *chip = &aml_chip->chip;
+ unsigned dma_unit_size = 0, count = 0, info_times_int_len;
+ int ret = 0;
+ struct mtd_info *mtd = &chip->mtd;
+ uint32_t temp;
+
+ info_times_int_len = PER_INFO_BYTE/sizeof(unsigned int);
+ if (bch_mode == NAND_ECC_NONE)
+ count = 1;
+ else if (bch_mode == NAND_ECC_BCH_SHORT) {
+ dma_unit_size = (chip->ecc.size >> 3);
+ count = len/chip->ecc.size;
+ } else
+ count = chip->ecc.steps;
+ /*printk("___count: %d, bch_mod:%d",count,bch_mode);*/
+ memset((unsigned char *)aml_chip->user_info_buf,
+ 0, count*PER_INFO_BYTE);
+ flush_dcache_range((unsigned long)aml_chip->user_info_buf,
+ (unsigned long)aml_chip->user_info_buf + count*PER_INFO_BYTE);
+ invalidate_dcache_range((unsigned long)buf, (unsigned long)buf + len);
+
+ NFC_SEND_CMD_ADL(controller, (u32)(unsigned long)buf);
+ NFC_SEND_CMD_ADH(controller, (u32)(unsigned long)buf);
+ NFC_SEND_CMD_AIL(controller,
+ (u32)(unsigned long)aml_chip->user_info_buf);
+ NFC_SEND_CMD_AIH(controller,
+ (u32)(unsigned long)aml_chip->user_info_buf);
+ if (aml_chip->ran_mode) {
+ temp = mtd->writesize >> chip->page_shift;
+ if (aml_chip->plane_num == 2)
+ NFC_SEND_CMD_SEED(controller,
+ (aml_chip->page_addr / temp) * temp);
+ else
+ NFC_SEND_CMD_SEED(controller,
+ aml_chip->page_addr);
+ }
+
+ if (bch_mode == NAND_ECC_NONE)
+ NFC_SEND_CMD_N2M_RAW(controller, 0, len);
+ else
+ NFC_SEND_CMD_N2M(controller, aml_chip->ran_mode,
+ ((bch_mode == NAND_ECC_BCH_SHORT)?aml_chip->bch_info:bch_mode),
+ ((bch_mode == NAND_ECC_BCH_SHORT)?1:0), dma_unit_size, count);
+
+ ret = aml_platform_dma_waiting(aml_chip);
+ if (ret)
+ return ret;
+ do {
+ invalidate_dcache_range((unsigned long)aml_chip->user_info_buf,
+ (unsigned long)aml_chip->user_info_buf + count*PER_INFO_BYTE);
+ info_buf =
+(volatile unsigned *)&(aml_chip->user_info_buf[(count-1)*info_times_int_len]);
+ cmp = *info_buf;
+ } while((cmp)==0);/*judge DMA read over*/
+
+ return 0;
+}
+
+static int m3_nand_hwecc_correct(struct aml_nand_chip *aml_chip,
+ unsigned char *buf, unsigned size, unsigned char *oob_buf)
+{
+ struct nand_chip *chip = &aml_chip->chip;
+ unsigned ecc_step_num, usr_info, tmp_value;
+ unsigned info_times_int_len = PER_INFO_BYTE / sizeof(unsigned int);
+
+ if (size % chip->ecc.size) {
+ printk ("error parameter size for ecc correct %x\n", size);
+ return -EINVAL;
+ }
+
+ for (ecc_step_num = 0;
+ ecc_step_num < (size / chip->ecc.size); ecc_step_num++) {
+ /* check if there have uncorrectable sector */
+ tmp_value = ecc_step_num * info_times_int_len;
+ usr_info = *(unsigned *)(&aml_chip->user_info_buf[tmp_value]);
+ if (NAND_ECC_CNT(usr_info) == 0x3f) {
+ aml_chip->zero_cnt = NAND_ZERO_CNT(usr_info);
+ return -EIO;
+
+ } else
+ aml_chip->ecc_cnt_cur =
+ NAND_ECC_CNT(usr_info);
+ }
+
+ return 0;
+}
+
+void register_aml_chip_contorller(struct aml_nand_chip *aml_chip)
+{
+ /*register amlogic hw controller functions*/
+ aml_chip->aml_nand_hw_init = m3_nand_hw_init;
+ aml_chip->aml_nand_adjust_timing = m3_nand_adjust_timing;
+ aml_chip->aml_nand_select_chip = m3_nand_select_chip;
+ aml_chip->aml_nand_options_confirm = m3_nand_options_confirm;
+ aml_chip->aml_nand_dma_read = m3_nand_dma_read;
+ aml_chip->aml_nand_dma_write = m3_nand_dma_write;
+ aml_chip->aml_nand_hwecc_correct = m3_nand_hwecc_correct;
+ aml_chip->aml_nand_cmd_ctrl = aml_platform_cmd_ctrl;
+ aml_chip->aml_nand_write_byte = aml_platform_write_byte;
+ aml_chip->aml_nand_wait_devready = aml_platform_wait_devready;
+ aml_chip->aml_nand_get_user_byte = aml_platform_get_user_byte;
+ aml_chip->aml_nand_set_user_byte = aml_platform_set_user_byte;
+ aml_chip->aml_nand_command = aml_nand_base_command;
+ aml_chip->aml_nand_block_bad_scrub =
+ aml_nand_block_bad_scrub_update_bbt;
+}
+
+extern int slcnand_fit_storage(void);
+static int m3_nand_probe(struct aml_nand_platform *plat, unsigned dev_num)
+{
+ struct aml_nand_chip *aml_chip = NULL;
+ struct nand_chip *chip = NULL;
+ struct mtd_info *mtd = NULL;
+ int err = 0, i, array_length;
+ struct nand_oobfree *oobfree;
+
+ aml_chip = kzalloc(sizeof(*aml_chip), GFP_KERNEL);
+ if (aml_chip == NULL) {
+ printk("no memory for flash info\n");
+ err = -ENOMEM;
+ goto exit_error;
+ }
+
+ /* initialize mtd info data struct */
+ aml_chip->controller = controller;
+ aml_chip->platform = plat;
+ aml_chip->bch_desc = m3_bch_list;
+ aml_chip->max_bch_mode = sizeof(m3_bch_list) / sizeof(m3_bch_list[0]);
+
+ chip = &aml_chip->chip;
+ chip->priv = aml_chip;
+ mtd = &chip->mtd;
+ mtd->priv = chip;
+ plat->aml_chip = aml_chip;
+ mtd->name = plat->name;
+
+ register_aml_chip_contorller(aml_chip);
+ aml_chip->ran_mode = plat->ran_mode;
+ aml_chip->rbpin_detect = plat->rbpin_detect;
+ aml_nfc_get_clk_name(controller);
+ chip->IO_ADDR_R = chip->IO_ADDR_W =
+ (void __iomem *)((volatile u32 *)(NAND_BASE_APB + P_NAND_BUF));
+
+ err = aml_nand_init(aml_chip);
+ if (!err) {
+ nand_info[dev_num] = mtd;
+ slcnand_fit_storage();
+ mtd_store_set(nand_info[dev_num], dev_num);
+ }
+ if (err || pre_scan->pre_scan_flag)
+ goto exit_error;
+
+ if (!strncmp((char*)plat->name,
+ NAND_BOOT_NAME, strlen((const char*)NAND_BOOT_NAME))) {
+ chip->erase = m3_nand_boot_erase_cmd;
+ chip->ecc.read_page = m3_nand_boot_read_page_hwecc;
+ chip->ecc.write_page = m3_nand_boot_write_page_hwecc;
+ chip->write_page = m3_nand_boot_write_page;
+ oobfree = chip->ecc.layout->oobfree;
+ array_length = ARRAY_SIZE(chip->ecc.layout->oobfree);
+ if (chip->ecc.layout)
+ oobfree[0].length =
+ (mtd->writesize / 512) * aml_chip->user_byte_mode;
+ chip->ecc.layout->oobavail = 0;
+ for (i = 0; oobfree[i].length && i < array_length; i++)
+ chip->ecc.layout->oobavail += oobfree[i].length;
+ mtd->oobavail = chip->ecc.layout->oobavail;
+ mtd->ecclayout = chip->ecc.layout;
+ }
+
+ return 0;
+
+exit_error:
+ if (aml_chip)
+ kfree(aml_chip);
+ mtd->name = NULL;
+ return err;
+}
+
+void nand_hw_init(struct aml_nand_platform *plat)
+{
+ struct aml_nand_chip *aml_chip = NULL;
+
+ aml_chip = plat->aml_chip;
+
+ aml_chip->aml_nand_hw_init(aml_chip);
+ if (aml_chip->aml_nand_adjust_timing)
+ aml_chip->aml_nand_adjust_timing(aml_chip);
+ aml_chip->aml_nand_select_chip(aml_chip, 0);
+}
+
+static void meson_nfc_init_dm(void)
+{
+ struct udevice *dev;
+
+ for (uclass_first_device(UCLASS_MTD, &dev);
+ dev;
+ uclass_next_device(&dev));
+}
+
+void board_nand_init(void)
+{
+ meson_nfc_init_dm();
+}
+
+int amlmtd_init = 0;
+extern struct udevice *nand_dev;
+int meson_nfc_probe(struct udevice *dev)
+{
+ struct aml_nand_platform *plat = NULL;
+ const void *blob = gd->fdt_blob;
+ fdt_addr_t regs, clk_regs;
+ int node;
+ int i, ret = 0;
+
+ if (1 == amlmtd_init) {
+ ret = pinctrl_select_state(controller->device, "default");
+ if (ret) {
+ printf("select state %s failed\n", "default");
+ return ret;
+ }
+ nand_hw_init(&aml_nand_mid_device.aml_nand_platform[0]);
+ return 0;
+ }
+
+ controller = kzalloc(sizeof(struct hw_controller), GFP_KERNEL);
+ if (controller == NULL) {
+ printk("%s kzalloc controller failed\n", __func__);
+ return 1;
+ }
+ nand_dev = dev;
+ controller->device = dev;
+
+ ret = pinctrl_select_state(controller->device, "default");
+ if (ret) {
+ printf("ERROR get pinmux failed\n");
+ }
+
+ controller->chip_num = 1; /* assume chip num is 1 */
+ for (i = 0; i < MAX_CHIP_NUM; i++) {
+ controller->ce_enable[i] =
+ (((CE_PAD_DEFAULT >> i*4) & 0xf) << 10);
+ controller->rb_enable[i] =
+ (((RB_PAD_DEFAULT >> i*4) & 0xf) << 10);
+ }
+
+ node = fdtdec_next_compatible(blob, 0, COMPAT_MESON_NAND);
+ if (node < 0) {
+ printk("unable to find nfc node in device tree\n");
+ return 1;
+ }
+ if (!fdtdec_get_is_enabled(blob, node)) {
+ printk("nfc disabled in device tree\n");
+ return 1;
+ }
+
+ regs = fdtdec_get_addr(blob, node, "reg");
+ if (regs == FDT_ADDR_T_NONE) {
+ printk("unabled to find nfc address in device tree\n");
+ return 1;
+ }
+ controller->reg_base = (void *)regs;
+
+ clk_regs = fdtdec_get_addr(blob, node, "clk_reg");
+ if (clk_regs == FDT_ADDR_T_NONE) {
+ printk("unabled to find nfc clk address in device tree\n");
+ return 1;
+ }
+ controller->nand_clk_reg = (void *)clk_regs;
+
+ for (i=0; i<aml_nand_mid_device.dev_num; i++) {
+ plat = &aml_nand_mid_device.aml_nand_platform[i];
+ if (!plat) {
+ printk("error for not platform data\n");
+ continue;
+ }
+
+ ret = m3_nand_probe(plat, i);
+ if (pre_scan->pre_scan_flag && !i) {
+ free(controller);
+ return 0;
+ }
+ if (ret)
+ printk("nand init failed: %d\n", ret);
+ }
+ nand_curr_device = 1; //fixit
+ amlmtd_init = 1;
+ if (ret)
+ free(controller);
+
+ return 0;
+}
+
+static const struct udevice_id aml_nfc_ids[] = {
+ { .compatible = "amlogic,meson-nfc" },
+ {}
+};
+
+U_BOOT_DRIVER(meson_nfc) = {
+ .name = "meson-nfc",
+ .id = UCLASS_MTD,
+ .of_match = aml_nfc_ids,
+ .probe = meson_nfc_probe,
+};
+
diff --git a/drivers/mtd/nand/raw/aml_nand/nand_flash.c b/drivers/mtd/nand/raw/aml_nand/nand_flash.c
new file mode 100644
index 0000000..fe30962
--- /dev/null
+++ b/drivers/mtd/nand/raw/aml_nand/nand_flash.c
@@ -0,0 +1,1371 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <environment.h>
+#include <nand.h>
+#include <asm/io.h>
+#include <malloc.h>
+#include <linux/err.h>
+#include <asm/cache.h>
+
+//#include <asm/arch/secure_apb.h>
+#include <amlogic/cpu_id.h>
+
+#include "aml_nand.h"
+
+extern struct hw_controller *controller;
+
+#if 0
+extern void test_timing(struct mtd_info *mtd, struct nand_chip *chip);
+#endif
+
+int nand_fbb_issue_flag;
+int check_1_2page_sparebyte;
+struct aml_nand_flash_dev aml_nand_flash_ids[] = {
+ {"B revision NAND 8GiB MT29F64G08CBABA",
+ {NAND_MFR_MICRON, 0x64, 0x44, 0x4B, 0xA9},
+ 8192,
+ 8192,
+ 0x200000,
+ 744,
+ 1,
+ 16,
+ 15,
+ 5,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE )},
+
+ {"A revision NAND 2GiB H27UAG8T2A",
+ {NAND_MFR_HYNIX, 0xd5, 0x94, 0x25, 0x44, 0x41},
+ 4096,
+ 2048,
+ 0x80000,
+ 224,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"A revision NAND 4GiB H27UBG8T2A",
+ {NAND_MFR_HYNIX, 0xd7, 0x94, 0x9a, 0x74, 0x42},
+ 8192,
+ 4096,
+ 0x200000,
+ 448,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"B revision NAND 2GiB H27UAG8T2B",
+ {NAND_MFR_HYNIX, 0xd5, 0x94, 0x9a, 0x74, 0x42},
+ 8192,
+ 2048,
+ 0x200000,
+ 448,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+
+ {"SamSung NAND K9F4G08U0F 4Gb",
+ {NAND_MFR_SAMSUNG, 0xdc, 0x10, 0x95, 0x56},
+ 2048,
+ 512,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
+ {"SamSung NAND k9f2g08u0d 2Gb",
+ {NAND_MFR_SAMSUNG, 0xda, 0x10, 0x95, 0x46},
+ 2048,
+ 256,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
+ {"Dosilicon NAND FMND1GXXX3D 3.3V 1Gb",
+ {NAND_MFR_DOSILICON, 0xf1, 0x80, 0x95},
+ 2048,
+ 128,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
+ {"Dosilicon NAND FMND1GXXX3D 1.8V 1Gb",
+ {NAND_MFR_DOSILICON, 0xa1, 0x80, 0x15},
+ 2048,
+ 128,
+ 0x20000,
+ 64,
+ 1,
+ 30,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
+ {"Dosilicon NAND FMND2GXXX3D 3.3V 2Gb",
+ {NAND_MFR_DOSILICON, 0xda, 0x90, 0x95, 0x46},
+ 2048,
+ 256,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
+ {"Dosilicon NAND FMND2GXXX3D 1.8V 2Gb",
+ {NAND_MFR_DOSILICON, 0xaa, 0x90, 0x15, 0x46},
+ 2048,
+ 256,
+ 0x20000,
+ 64,
+ 1,
+ 30,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
+ {"ATO NAND AFND1G08U3 1Gb",
+ {NAND_MFR_ATO, 0xf1, 0x00, 0x1d},
+ 2048,
+ 128,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
+ {"ATO NAND AFND2G08U3A 2Gb",
+ {NAND_MFR_HYNIX, 0xda, 0x90, 0x95, 0x46, 0xad},
+ 2048,
+ 256,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
+ {"A revision NAND 1GiB sF1G-A",
+ {NAND_MFR_AMD, 0xf1, 0x80, 0x1d, 0x01,0xf1},
+ 2048,
+ 128,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE )},
+
+ {"A revision NAND 1GiB sF1G-A",
+ {NAND_MFR_AMD, 0xf1, 0x0, 0x1d, 0x01,0xf1},
+ 2048,
+ 128,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+
+ {"AMD/Spansion Slc NAND 2Gib S34ML02G1(MLO2G100BH1OO)",
+ {NAND_MFR_AMD, 0xda, 0x90, 0x95, 0x44, 0x01},
+ 2048,
+ 256,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+
+ {"AMD/Spansion Slc NAND 2Gib S34ML02G1(MLO2G200BH1OO)",
+ {NAND_MFR_AMD, 0xda, 0x90, 0x95, 0x46, 0x01},
+ 2048,
+ 256,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+
+ {"AMD/Spansion Slc NAND 8Gib S34ML08G1",
+ {NAND_MFR_AMD, 0xd3, 0xd1, 0x95, 0x58},
+ 2048,
+ 1024,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+
+ {"A revision NAND 1Gib W29N01HV ",
+ {NAND_ID_WINBOND, 0xf1, 0x00, 0x95, 0x00, 0x00},
+ 2048,
+ 128,
+ 0x20000,
+ 64,
+ 1,
+ 16,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+
+ {"A revision NAND 4Gib W29N04GV ",
+ {NAND_ID_WINBOND, 0xdc, 0x90, 0x95, 0x54, 0x00},
+ 2048,
+ 512,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
+
+ {"A revision NAND 1Gib W29N01GV ",
+ {NAND_ID_WINBOND, 0xf1, 0x80, 0x95, 0x00, 0x00},
+ 2048,
+ 128,
+ 0x20000,
+ 64,
+ 1,
+ 16,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+
+ {"A revision NAND 2Gib W29N02GV ",
+ {NAND_ID_WINBOND, 0xda, 0x90, 0x95, 0x04, 0x00},
+ 2048,
+ 256,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+
+ {"A revision NAND 1GiB H27U1G8F2CTR ",
+ {NAND_MFR_HYNIX, 0xf1, 0x80, 0x1d, 0xad, 0xf1},
+ 2048,
+ 128,
+ 0x20000,
+ 64,
+ 1,
+ 16,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+
+ {"A revision NAND 4Gib EMST ",
+ {NAND_ID_ESMT, 0xac, 0x90, 0x15, 0x54, 0x7f},
+ 2048,
+ 512,
+ 0x20000,
+ 64,
+ 1,
+ 16,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+
+ {"A revision NAND 4Gib GD9FU1G8F2AMGI",
+ {NAND_ID_ESMT, 0xf1, 0x80, 0x1d, 0x42, 0xc8},
+ 2048,
+ 128,
+ 0x20000,
+ 128,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
+
+ {"ESMT SLC 256MiB 3.3V 8-bit",
+ {NAND_ID_ESMT, 0xda, 0x90, 0x95, 0x44, 0x7f},
+ 2048,
+ 256,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+ {"ESMT SLC 128MiB 3.3V 8-bit F59L1G81Lxxx",
+ {NAND_ID_ESMT, 0xd1, 0x80, 0x95, 0x42, 0x7f},
+ 2048,
+ 128,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+ {"ESMT SLC 128MiB 3.3V 8-bit F59L1G81Mxxx",
+ {NAND_ID_ESMT, 0xd1, 0x80, 0x95, 0x40, 0x7f},
+ 2048,
+ 128,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+ {"A revision NAND 2Gib TC58BVG1S3HTA00 ",
+ {NAND_MFR_TOSHIBA, 0xda, 0x90, 0x15, 0xF6},
+ 2048,
+ 256,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 25,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+ {"A revision NAND 2Gib TC58NVG1S3HBAI4 ",
+ {NAND_MFR_TOSHIBA, 0xda, 0x90, 0x15, 0x76},
+ 2048,
+ 256,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 25,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+ {"A revision NAND 4Gib TH58NVG2S3HTA00 ",
+ {NAND_MFR_TOSHIBA, 0xdc, 0x91, 0x15, 0x76},
+ 2048,
+ 512,
+ 0x20000,
+ 64,
+ 1,
+ 35, /* trc = 50, 20MHz max ! */
+ 10,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+ {"A revision NAND 4Gib TC58NVG2S0HTA00 ",
+ {NAND_MFR_TOSHIBA, 0xdc, 0x90, 0x26, 0x76},
+ 4096,
+ 512,
+ 0x40000,
+ 256,
+ 1,
+ 20,
+ 25,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+ {"A revision NAND 4Gib TC58BVG2S0HTA00 ",
+ {NAND_MFR_TOSHIBA, 0xdc, 0x90, 0x26, 0xF6},
+ 4096,
+ 512,
+ 0x40000,
+ 128,
+ 1,
+ 20,
+ 25,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+ {"A revision NAND 1Gib TC58BVG0S3HTA00",
+ {NAND_MFR_TOSHIBA, 0xf1, 0x80, 0x15, 0xf2},
+ 2048,
+ 128,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 25,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
+ {"Slc NAND 1Gib MX30LF1G18AC ",
+ {NAND_MFR_MACRONIX, 0xf1, 0x80, 0x95, 0x02},
+ 2048,
+ 128,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 25,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+ {"Slc NAND 2Gib MX30LF2G18AC ",
+ {NAND_MFR_MACRONIX, 0xda, 0x90, 0x95, 0x06},
+ 2048,
+ 256,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 25,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+
+ {"Slc NAND 4Gib MX30LF4G18AC ",
+ {NAND_MFR_MACRONIX, 0xdc, 0x90, 0x95, 0x56},
+ 2048,
+ 512,
+ 0x20000,
+ 64,
+ 1,
+ 16,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+
+ {"Slc NAND 4Gib MX30LF4G28AD ",
+ {NAND_MFR_MACRONIX, 0xdc, 0x90, 0xA2, 0x57, 0x03},
+ 4096,
+ 512,
+ 0x40000,
+ 256,
+ 1,
+ 16,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+
+ {"A revision NAND 128MB TC58NVG0S3HTA00 ",
+ {NAND_MFR_TOSHIBA, 0xf1, 0x80, 0x15, 0x72},
+ 2048,
+ 128,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 25,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+
+ {"4Gib MT29F4G08ABAEA",
+ {NAND_MFR_MICRON, 0xdc, 0x90, 0xA6, 0x54},
+ 4096,
+ 512,
+ 0x40000,
+ 224,
+ 1,
+ 16,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
+
+ {"4Gib MT29F4G08ABADA",
+ {NAND_MFR_MICRON, 0xdc, 0x90, 0x95, 0x56},
+ 2048,
+ 512,
+ 0x20000,
+ 64,
+ 1,
+ 16,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
+
+ {"A revision NAND 2Gib MT29F2G08-A",
+ {NAND_MFR_MICRON, 0xda, 0x90, 0x95, 0x06},
+ 2048,
+ 256,
+ 0x20000,
+ 64,
+ 1,
+ 16,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE )},
+
+ {"A revision NAND 1GiB MT29F1G-A",
+ {NAND_MFR_MICRON, 0xf1, 0x80, 0x95, 0x04},
+ 2048,
+ 128,
+ 0x20000,
+ 64,
+ 1,
+ 16,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE )},
+
+ {"A revision NAND 2GiB MT29F16G08ABABA",
+ {NAND_MFR_MICRON, 0x48, 0x00, 0x26, 0x89},
+ 4096,
+ 2048,
+ 0x80000,
+ 224,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE4 | NAND_ECC_BCH8_MODE)},
+
+ {"A revision NAND 4GiB MT29F32G-A",
+ {NAND_MFR_MICRON, 0xd7, 0x94, 0x3e, 0x84},
+ 4096,
+ 4096,
+ 0x80000,
+ 218,
+ 1,
+ 16,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"A revision NAND 16GiB MT29F128G-A",
+ {NAND_MFR_MICRON, 0xd9, 0xd5, 0x3e, 0x88},
+ 4096,
+ 16384,
+ 0x80000,
+ 218,
+ 1,
+ 16,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"B revision NAND 4GiB MT29F32G-B",
+ {NAND_MFR_MICRON, 0x68, 0x04, 0x46, 0x89},
+ 4096,
+ 4096,
+ 0x100000,
+ 224,
+ 1,
+ 20,
+ 15,
+ 4,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"B revision NAND 8GiB MT29F64G-B",
+ {NAND_MFR_MICRON, 0x88, 0x05, 0xc6, 0x89},
+ 4096,
+ 8192,
+ 0x100000,
+ 224,
+ 1,
+ 20,
+ 15,
+ 4,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"C revision NAND 4GiB MT29F32G-C",
+ {NAND_MFR_MICRON, 0x68, 0x04, 0x4a, 0xa9},
+ 4096,
+ 4096,
+ 0x100000,
+ 224,
+ 1,
+ 16,
+ 15,
+ 5,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"C revision NAND 8GiB MT29F64G-C",
+ {NAND_MFR_MICRON, 0x88, 0x04, 0x4b, 0xa9},
+ 8192,
+ 8192,
+ 0x200000,
+ 448,
+ 1,
+ 16,
+ 15,
+ 5,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"C revision NAND 1GiB MT29F8G08ABABA",
+ {NAND_MFR_MICRON, 0x38, 0x00, 0x26, 0x85},
+ 4096,
+ 1024,
+ 0x80000,
+ 224,
+ 1,
+ 16,
+ 15,
+ 5,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
+ |NAND_TWO_PLANE_MODE)},
+
+ {"C revision NAND 32GiB MT29F256G-C",
+ {NAND_MFR_MICRON, 0xa8, 0x05, 0xcb, 0xa9},
+ 8192,
+ 16384,
+ 0x200000,
+ 448,
+ 2,
+ 16,
+ 15,
+ 5,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
+ | NAND_TWO_PLANE_MODE | NAND_INTERLEAVING_MODE)},
+
+ {"1 Generation NAND 4GiB JS29F32G08AA-1",
+ {NAND_MFR_INTEL, 0x68, 0x04, 0x46, 0xA9},
+ 4096,
+ 4096,
+ 0x100000,
+ 218,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"1 Generation NAND 8GiB JS29F64G08AA-1",
+ {NAND_MFR_INTEL, 0x88, 0x24, 0x4b, 0xA9},
+ 8192,
+ 8192,
+ 0x200000,
+ 448,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"E serials NAND 2GiB TC58NVG4D2ETA00",
+ {NAND_MFR_TOSHIBA, 0xD5, 0x94, 0x32, 0x76, 0x54},
+ 8192,
+ 2048,
+ 0x100000,
+ 376,
+ 1,
+ 20,
+ 25,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"E serials NAND 4GiB TC58NVG5D2ETA00",
+ {NAND_MFR_TOSHIBA, 0xD7, 0x94, 0x32, 0x76, 0x54},
+ 8192,
+ 4096,
+ 0x100000,
+ 376,
+ 1,
+ 20,
+ 25,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"F serials NAND 2GiB TC58NVG4D2FTA00",
+ {NAND_MFR_TOSHIBA, 0xD5, 0x94, 0x32, 0x76, 0x55},
+ 8192,
+ 2076,
+ 0x100000,
+ 448,
+ 1,
+ 20,
+ 25,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"F serials NAND 4GiB TC58NVG5D2FTA00",
+ {NAND_MFR_TOSHIBA, 0xD7, 0x94, 0x32, 0x76, 0x55},
+ 8192,
+ 4096,
+ 0x100000,
+ 448,
+ 1,
+ 20,
+ 25,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"F serials NAND 8GiB TC58NVG6D2FTA00",
+ {NAND_MFR_TOSHIBA, 0xDE, 0x94, 0x32, 0x76, 0x55},
+ 8192,
+ 8192,
+ 0x100000,
+ 448,
+ 1,
+ 20,
+ 25,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"F serials NAND 8GiB TH58NVG7D2FTA20",
+ {NAND_MFR_TOSHIBA, 0xDE, 0x95, 0x32, 0x7a, 0x55},
+ 8192,
+ 8200,
+ 0x100000,
+ 448,
+ 2,
+ 20,
+ 25,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
+ | NAND_TWO_PLANE_MODE | NAND_INTERLEAVING_MODE)},
+
+ {"M Generation NAND 4Gib K9F4G08U0D",
+ {NAND_MFR_SAMSUNG, 0xDC, 0x10, 0x95, 0x54,0XEC,},
+ 2048,
+ 512,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
+
+ {"M Generation NAND 1Gib FS33ND01GS108TFI0",
+ {NAND_MFR_SAMSUNG, 0xF1, 0x00, 0x95, 0x42},
+ 2048,
+ 128,
+ 0x20000,
+ 64,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
+
+ {"M Generation NAND 2GiB K9GAG08U0M",
+ {NAND_MFR_SAMSUNG, 0xD5, 0x14, 0xb6, 0x74},
+ 4096,
+ 2048,
+ 0x80000,
+ 128,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH8_MODE)},
+
+ {"5 Generation NAND 2GiB K9GAG08X0D",
+ {NAND_MFR_SAMSUNG, 0xD5, 0x94, 0x29, 0x34, 0x41},
+ 4096,
+ 2048,
+ 0x80000,
+ 218,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"6 Generation NAND 2GiB K9GAG08U0E",
+ {NAND_MFR_SAMSUNG, 0xD5, 0x84, 0x72, 0x50, 0x42},
+ 8192,
+ 2048,
+ 0x100000,
+ 436,
+ 1,
+ 25,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE)},
+
+ {"7 Generation NAND 2GiB K9GAG08U0F",
+ {NAND_MFR_SAMSUNG, 0xD5, 0x94, 0x76, 0x54, 0x43},
+ 8192,
+ 2048,
+ 0x100000,
+ 512,
+ 1,
+ 25,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"6 Generation NAND 4GiB K9LBG08U0E",
+ {NAND_MFR_SAMSUNG, 0xD7, 0xC5, 0x72, 0x54, 0x42},
+ 8192,
+ 4096,
+ 0x100000,
+ 436,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"6 Generation NAND 8GiB K9HCG08U0E",
+ {NAND_MFR_SAMSUNG, 0xDE, 0xC5, 0x72, 0x54, 0x42},
+ 8192,
+ 8192,
+ 0x100000,
+ 436,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH12_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"2 Generation NAND 4GiB K9GBG08U0A",
+ {NAND_MFR_SAMSUNG, 0xD7, 0x94, 0x7a, 0x54, 0x43},
+ 8192,
+ 4152,
+ 0x100000,
+ 640,
+ 1,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
+ | NAND_TWO_PLANE_MODE)},
+
+ {"2 Generation NAND 8GiB K9LCG08U0A",
+ {NAND_MFR_SAMSUNG, 0xDE, 0xD5, 0x7a, 0x58, 0x43},
+ 8192,
+ 8304,
+ 0x100000,
+ 640,
+ 2,
+ 20,
+ 15,
+ 0,
+ (NAND_TIMING_MODE5 | NAND_ECC_BCH16_MODE
+ | NAND_TWO_PLANE_MODE | NAND_INTERLEAVING_MODE)},
+
+ {NULL,}
+};
+
+/* detects factory bad blocks for the following samsung nand,
+ * it needs to detect the first byte of the spare area at
+ * the first page and the second page
+ */
+u8 samsung_nand_id0[][MAX_ID_LEN] = {
+ {NAND_MFR_SAMSUNG, 0xf1, 0x00, 0x95, 0x42},
+ {NAND_MFR_SAMSUNG, 0xda, 0x10, 0x15, 0x44},
+ {NAND_MFR_SAMSUNG, 0xdc, 0x10, 0x95, 0x54},
+ {NAND_MFR_SAMSUNG, 0xd3, 0x11, 0x95, 0x58},
+ {NAND_MFR_SAMSUNG, 0xdc, 0x10, 0x95, 0x55},
+ {NAND_MFR_SAMSUNG, 0xd3, 0x51, 0x95, 0x59},
+ {NAND_MFR_SAMSUNG, 0xdc, 0x10, 0x95, 0x56},
+ {NAND_MFR_SAMSUNG, 0xd3, 0x51, 0x95, 0x5a},
+};
+
+
+int aml_get_samsung_fbbt_flag(void)
+{
+ return check_1_2page_sparebyte;
+}
+
+void aml_nand_check_samsung_fbbt_flag(u8 *dev_id)
+{
+ int i, k;
+
+ k = ARRAY_SIZE(samsung_nand_id0);
+ for (i = 0; i < k; i++) {
+ if (!strncmp((char *)samsung_nand_id0[i], (char *)dev_id,
+ strlen((const char *)samsung_nand_id0[i])))
+ check_1_2page_sparebyte = 1;
+ }
+}
+
+int aml_nand_get_fbb_issue(void)
+{
+ return nand_fbb_issue_flag;
+}
+
+void aml_nand_check_fbb_issue(u8 *dev_id)
+{
+ int i, k;
+ u8 samsung_nand_id[][MAX_ID_LEN] = {
+ {NAND_MFR_SAMSUNG, 0xdc, 0x10, 0x95, 0x56},
+ {NAND_MFR_SAMSUNG, 0xda, 0x10, 0x95, 0x46},
+ };
+
+ k = ARRAY_SIZE(samsung_nand_id);
+ for (i = 0; i < k; i++) {
+ if (!strncmp((char *)samsung_nand_id[i], (char *)dev_id,
+ strlen((const char *)samsung_nand_id[i])))
+ nand_fbb_issue_flag = 1;
+ }
+}
+
+#ifdef CONFIG_PARAMETER_PAGE
+struct parameter_page para_page;
+
+void aml_nand_read_parameter_page(struct mtd_info *mtd, int ce, char * buf)
+{
+
+ struct nand_chip *chip = mtd->priv;
+
+ NFC_SEND_CMD(ce | CLE | 0xec);
+ NFC_SEND_CMD(ce | ALE | 0x00);
+ NFC_SEND_CMD(ce | IDLE | 5);
+
+ signed long i,count;
+ memset(buf,0,256);
+ for (i=0,count=0;i<256 && count<256;i++)
+ {
+ *buf=chip->read_byte(mtd);
+ if ((0 == i) && (0x4f != *buf))
+ {
+ i=-1;
+ count++;
+ continue;
+ }
+
+ buf++;
+ }
+}
+
+void display_para_page(struct parameter_page para_page,unsigned long log_level)
+{
+ unsigned long i;
+ signed long j;
+ unsigned char* buf = (unsigned char*)¶_page;
+
+ printk("\nNand parameter page: \n");
+
+ if ((para_page.signature[0] != 0x4f)
+ || (para_page.signature[1] != 0x4e)
+ || (para_page.signature[2] != 0x46)
+ || (para_page.signature[3] != 0x49)) {
+ printk("Wrong parameter page reading.\n");
+ return;
+ }
+
+ if (1 == log_level) {
+ printk("The parameter value is show as following list,"
+ "please refer to ONFI SPEC for more infomation.\n");
+ printk("index val index val index val index val ");
+ for (i = 0; i < sizeof(para_page); i++, buf++) {
+ if (!(i % 4))
+ printf("\n");
+ if (0 == i)
+ printk("0~31 byte:Revision info and features blk:\n");
+ else if(32 == i)
+ printk("32~79 byte: Manufacturer info blk:\n");
+ else if(80 == i)
+ printk("80~127 byte: Memory organization blk:\n");
+ else if(128 == i)
+ printk("128~163 byte: Electrical parameters block:\n");
+ else if(164 == i)
+ printk("164~255 byte: Vendor block:\n");
+ printk("%03d 0x%02x ",i, *buf);
+
+ }
+ } else {
+ printk("Manu info: ");
+ for (j=0; j<12; j++)
+ printk("%c", para_page.dev_manu[j]);
+ printk("\n");
+
+ printk("ONFI v");
+ if (para_page.ver & 0x40)
+ printk("3.0 ");
+ if (para_page.ver & 0x20)
+ printk("2.3 ");
+ if (para_page.ver & 0x10)
+ printk("2.2 ");
+ if (para_page.ver & 0x08)
+ printk("2.1 ");
+ if (para_page.ver & 0x04)
+ printk("2.0 ");
+ if (para_page.ver & 0x02)
+ printk("1.0");
+ printk("\n");
+
+ printk("Feature supprot: 0x%x\n",para_page.feature);
+
+ printk("%d bytes per page.\n",para_page.data_bytes_perpage);
+ printk("%d spare bytes per page.\n",
+ para_page.spare_bytes_perpage);
+ printk("%d pages per block.\n",para_page.pages_perblk);
+ printk("%d blocks per LUN.\n",para_page.blks_perLUN);
+ printk("%d LUNs.\n",para_page.num_LUN);
+ para_page.num_addr_cycle;
+ printk("Column address cycles %d, Row address cycles %d.\n",
+ para_page.num_addr_cycle & 0xf0,
+ para_page.num_addr_cycle & 0xf);
+ printk("%d bits per cell.\n",para_page.bits_percell);
+
+ printk("Bad blocks maximum per LUN: %d\n",
+ para_page.max_badblk_perLUN);
+ printk("%d bits ECC correctability.\n",
+ para_page.bits_ECC_corretable);
+
+ printk("Support time mode: ");
+ for (j = 5; j >= 0; j--) {
+ if (para_page.asy_time_mode & (1<<j))
+ printk("%d ",j);
+ }
+ }
+ printk("\nEnd of Nand parameter page.\n\n");
+ return;
+}
+#endif //CONFIG_PARAMETER_PAGE
+
+uint8_t aml_nand_get_onfi_features(struct aml_nand_chip *aml_chip,
+ uint8_t *buf, int addr)
+{
+ struct nand_chip *chip = &aml_chip->chip;
+ struct mtd_info *mtd = &chip->mtd;
+ int i, j;
+
+ for (i=0; i<controller->chip_num; i++) {
+ if (aml_chip->valid_chip[i]) {
+ aml_chip->aml_nand_select_chip(aml_chip, i);
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_GET_FEATURES, -1, -1, i);
+ chip->cmd_ctrl(mtd, addr,
+ NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE);
+ NFC_SEND_CMD_IDLE(controller, 20);
+ for (j = 0; j < 4; j++)
+ buf[j] = chip->read_byte(mtd);
+ }
+ }
+ return 0;
+}
+
+void aml_nand_set_onfi_features(struct aml_nand_chip *aml_chip,
+ uint8_t *buf, int addr)
+{
+ int i, j;
+ struct nand_chip *chip = &aml_chip->chip;
+ struct mtd_info *mtd = &chip->mtd;
+ for (i=0; i<controller->chip_num; i++) {
+ if (aml_chip->valid_chip[i]) {
+ aml_chip->aml_nand_select_chip(aml_chip, i);
+ aml_chip->aml_nand_command(aml_chip,
+ NAND_CMD_SET_FEATURES, -1, -1, i);
+ chip->cmd_ctrl(mtd, addr,
+ NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE);
+ NFC_SEND_CMD_IDLE(controller, 20);
+ for (j=0; j<4; j++)
+ aml_chip->aml_nand_write_byte(aml_chip, buf[j]);
+ aml_chip->aml_nand_wait_devready(aml_chip, i);
+ }
+ }
+}
+
+extern struct aml_pre_scan *pre_scan;
+static struct aml_nand_flash_dev *aml_nand_get_flash_type(struct mtd_info *mtd,
+ struct nand_chip *chip,
+ int busw, int *maf_id)
+{
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+ struct aml_nand_platform *plat = aml_chip->platform;
+ struct aml_nand_flash_dev *type = NULL;
+ int i, maf_idx;
+ u8 dev_id[MAX_ID_LEN]= {0};
+
+
+ /* Send the command for reading device ID */
+ chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+
+ /* Read manufacturer and device IDs */
+ for (i=0; i<MAX_ID_LEN; i++) {
+ dev_id[i] = chip->read_byte(mtd);
+ }
+ *maf_id = dev_id[0];
+ printk("NAND device id: %x %x %x %x %x %x \n",
+ dev_id[0], dev_id[1], dev_id[2], dev_id[3], dev_id[4], dev_id[5]);
+
+ /* Lookup the flash id */
+ for (i = 0; aml_nand_flash_ids[i].name != NULL; i++) {
+ if (!strncmp((char*) aml_nand_flash_ids[i].id,
+ (char*)dev_id, 6)) {
+ type = &aml_nand_flash_ids[i];
+ break;
+ }
+ }
+
+ if (!type) {
+ if (plat->nand_flash_dev) {
+ if (!strncmp((char*) plat->nand_flash_dev->id,
+ (char*)dev_id, strlen((const char*)plat->nand_flash_dev->id)))
+ type = plat->nand_flash_dev;
+ }
+
+ if (!type) {
+ pre_scan->is_nand = 0;
+ return type;
+ }
+ }
+ aml_nand_check_fbb_issue(dev_id);
+ if (NAND_MFR_SAMSUNG == dev_id[0])
+ aml_nand_check_samsung_fbbt_flag(dev_id);
+
+ plat->nand_flash_dev = type;
+
+ if (pre_scan->pre_scan_flag) {
+ if (type)
+ pre_scan->is_nand = 1;
+ return type;
+ }
+#ifdef CONFIG_MTD_DEVICE
+ mtd->name = type->name;
+#else
+ if (!mtd->name)
+ mtd->name = type->name;
+#endif
+
+ chip->chipsize = type->chipsize;
+ chip->chipsize = chip->chipsize << 20;
+
+ /* Newer devices have all the information in additional id bytes */
+ if (!type->pagesize) {
+ int extid;
+ /* The 3rd id byte holds MLC / multichip data */
+ /*chip->cellinfo = chip->read_byte(mtd);*/
+ /* The 4th id byte is the important one */
+ extid = chip->read_byte(mtd);
+ /* Calc pagesize */
+ mtd->writesize = 1024 << (extid & 0x3);
+ extid >>= 2;
+ /* Calc oobsize */
+ mtd->oobsize = (8 << (extid & 0x01)) * (mtd->writesize >> 9);
+ extid >>= 2;
+ /* Calc blocksize. Blocksize is multiples of 64KiB */
+ mtd->erasesize = (64 * 1024) << (extid & 0x03);
+ extid >>= 2;
+ /* Get buswidth information */
+ busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
+
+ } else {
+ /*Old devices have chip data hardcoded in the device id table*/
+ mtd->erasesize = type->erasesize;
+ mtd->writesize = type->pagesize;
+ mtd->oobsize = type->oobsize;
+ busw = type->options & NAND_BUSW_OPTIONS_MASK;
+ }
+
+ /* Try to identify manufacturer */
+ for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
+ if (nand_manuf_ids[maf_idx].id == *maf_id)
+ break;
+ }
+
+ /*Check, if buswidth is correct. Hardware drivers should set
+ * chip correct !*/
+ if (busw != (chip->options & NAND_BUSWIDTH_16)) {
+ printk(KERN_INFO "NAND device: Manufacturer ID:"
+ " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id,
+ dev_id[0], nand_manuf_ids[maf_idx].name, mtd->name);
+ printk(KERN_WARNING "NAND bus width %d instead %d bit\n",
+ (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
+ busw ? 16 : 8);
+ return ERR_PTR(-EINVAL);
+ }
+
+ /* Calculate the address shift from the page size */
+ chip->page_shift = ffs(mtd->writesize) - 1;
+ /* Convert chipsize to number of pages per chip -1. */
+ chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
+
+ chip->bbt_erase_shift = chip->phys_erase_shift= ffs(mtd->erasesize) - 1;
+ chip->chip_shift = ffs(chip->chipsize) - 1;
+
+ /* Set the bad block position */
+ chip->badblockpos = AML_BADBLK_POS;
+
+ /* Get chip options, preserve non chip based options */
+ /*chip->options &= ~NAND_CHIPOPTIONS_MSK;*/
+ /*chip->options |= type->options & NAND_CHIPOPTIONS_MSK;*/
+
+ /*Set chip as a default. Board drivers can override it, if necessary*/
+ /*chip->options |= NAND_NO_AUTOINCR;*/
+
+ /* Check if chip is a not a samsung device. Do not clear the
+ * options for chips which are not having an extended id.
+ */
+ /*if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
+ chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;*/
+
+ printk(KERN_INFO "NAND device: Manufacturer ID:"
+ " 0x%02x, Chip ID: 0x%02x (%s %s)\n", *maf_id, dev_id[0],
+ nand_manuf_ids[maf_idx].name, type->name);
+
+ return type;
+}
+
+
+static int aml_nand_scan_ident(struct mtd_info *mtd, int maxchips)
+{
+ int i, busw, nand_maf_id, valid_chip_num = 1;
+ struct nand_chip *chip = mtd->priv;
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(mtd);
+ struct aml_nand_flash_dev *aml_type = NULL;
+ struct aml_nand_platform *plat = aml_chip->platform;
+ u8 dev_id[MAX_ID_LEN], onfi_features[4];
+ unsigned temp_chip_shift;
+
+ chip->cmdfunc = aml_nand_command;
+ chip->waitfunc = aml_nand_wait;
+ chip->erase = aml_nand_erase_cmd;
+ chip->write_page = aml_nand_write_page;
+
+ /* Get buswidth to select the correct functions */
+ busw = chip->options & NAND_BUSWIDTH_16;
+
+ /* Select the device */
+ chip->select_chip(mtd, 0);
+
+ /*reset chip for some nand need reset after power up*/
+ chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ aml_chip->aml_nand_wait_devready(aml_chip, 0);
+
+ /* Read the flash type */
+ aml_type = aml_nand_get_flash_type(mtd, chip, busw, &nand_maf_id);
+ if (pre_scan->pre_scan_flag) {
+ if (!aml_type) {
+ chip->select_chip(mtd, -1);
+ return -ENODEV;
+ }
+ return 0;
+ }
+
+ if (IS_ERR(aml_type)) {
+ printk(KERN_WARNING "No NAND device found!!!\n");
+ chip->select_chip(mtd, -1);
+ return PTR_ERR(aml_type);
+ }
+ chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
+ for (i=0; i<MAX_ID_LEN; i++) {
+ dev_id[i] = chip->read_byte(mtd);
+ }
+ if (!memcmp((char*)dev_id, "ONFI", 4))
+ aml_chip->onfi_mode = aml_type->onfi_mode;
+
+ aml_chip->T_REA = aml_type->T_REA;
+ aml_chip->T_RHOH = aml_type->T_RHOH;
+ aml_chip->mfr_type = aml_type->id[0];
+#ifdef CONFIG_PARAMETER_PAGE
+ aml_nand_read_parameter_page(mtd, CE0, ¶_page);
+ display_para_page(para_page, 0);
+#endif
+ /* Check for a chip array */
+ for (i = 1; i < maxchips; i++) {
+ aml_chip->aml_nand_select_chip(aml_chip, i);
+ chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
+ aml_chip->aml_nand_wait_devready(aml_chip, i);
+
+ /* Send the command for reading device ID */
+ chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
+ /* Read manufacturer and device IDs */
+
+ if (nand_maf_id != chip->read_byte(mtd)
+ || aml_type->id[1] != chip->read_byte(mtd))
+ /*if (nand_maf_id != dev_id[0] || aml_type->id[1] != dev_id[1])*/
+ aml_chip->valid_chip[i] = 0;
+ else
+ valid_chip_num ++;
+ }
+
+ if (i > 1) {
+ printk(KERN_INFO "%d NAND chips detected\n", valid_chip_num);
+ }
+
+ /*
+ *fixit, Need to send dummy cmd for spansion(MLO2G100BH1OO) which is different
+ *from others.
+ */
+ if (aml_chip->mfr_type == NAND_MFR_AMD )
+ chip->cmdfunc(mtd, 0x00, -1, -1);
+
+ if (aml_chip->onfi_mode) {
+ aml_nand_set_onfi_features(aml_chip,
+ (uint8_t *)(&aml_chip->onfi_mode), ONFI_TIMING_ADDR);
+ aml_nand_get_onfi_features(aml_chip,
+ onfi_features, ONFI_TIMING_ADDR);
+ if (onfi_features[0] != aml_chip->onfi_mode) {
+ aml_chip->T_REA = DEFAULT_T_REA;
+ aml_chip->T_RHOH = DEFAULT_T_RHOH;
+ printk("onfi timing mode set failed: %x\n",
+ onfi_features[0]);
+ }
+ }
+
+ /* Store the number of chips and calc total size for mtd */
+ chip->numchips = 1;
+ if ((chip->chipsize >> 32) & 0xffffffff)
+ chip->chip_shift =
+ fls((unsigned)(chip->chipsize >> 32)) * valid_chip_num + 32 - 1;
+ else
+ chip->chip_shift =
+ fls((unsigned)chip->chipsize) * valid_chip_num - 1;
+
+ chip->pagemask =
+ ((chip->chipsize * valid_chip_num) >> chip->page_shift) - 1;
+ chip->options &= ~NAND_CACHEPRG;
+ aml_chip->internal_chipnr = aml_type->internal_chipnr;
+ aml_chip->internal_page_nums = (chip->chipsize >> chip->page_shift);
+ aml_chip->internal_page_nums /= aml_chip->internal_chipnr;
+ aml_chip->internal_chip_shift =
+ fls((unsigned)aml_chip->internal_page_nums) - 1;
+ temp_chip_shift = ffs((unsigned)aml_chip->internal_page_nums) - 1;
+ if (aml_chip->internal_chip_shift != temp_chip_shift) {
+ aml_chip->internal_chip_shift += 1;
+ chip->chip_shift += 1;
+ chip->pagemask =
+ ((1 << (chip->chip_shift + 1)) >> chip->page_shift) - 1;
+ }
+ chip->bits_per_cell = 1;
+ aml_chip->options = aml_type->options;
+ aml_chip->page_size = aml_type->pagesize;
+ aml_chip->block_size = aml_type->erasesize;
+ aml_chip->oob_size = aml_type->oobsize;
+ mtd->erasesize = valid_chip_num * aml_type->erasesize;
+ mtd->writesize = valid_chip_num * aml_type->pagesize;
+ mtd->oobsize = valid_chip_num * aml_type->oobsize;
+ mtd->size = valid_chip_num * chip->chipsize;
+
+ /* overide bootloader's size consdering info page */
+ /* fixme, need -1 for each copies? */
+ if (!strncmp((char*)plat->name,
+ NAND_BOOT_NAME, strlen((const char*)NAND_BOOT_NAME)))
+ mtd->size = BOOT_TOTAL_PAGES * mtd->writesize;
+
+ return 0;
+}
+
+int aml_nand_scan(struct mtd_info *mtd, int maxchips)
+{
+ int ret;
+
+ ret = aml_nand_scan_ident(mtd, maxchips);
+ if (!ret && !(pre_scan->pre_scan_flag))
+ ret = nand_scan_tail(mtd);
+ return ret;
+}
+
+
+
diff --git a/drivers/mtd/nand/raw/aml_nand/storage_nand.c b/drivers/mtd/nand/raw/aml_nand/storage_nand.c
new file mode 100644
index 0000000..76cd968
--- /dev/null
+++ b/drivers/mtd/nand/raw/aml_nand/storage_nand.c
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
+#include <amlogic/storage.h>
+#include <amlogic/aml_mtd.h>
+#include "aml_nand.h"
+#include <dm/device.h>
+
+extern void mtd_store_mount_ops(struct storage_t* store);
+struct aml_pre_scan *pre_scan;
+
+int nand_pre(void)
+{
+ int ret = 0;
+
+ pre_scan->pre_scan_flag = 1;
+ board_nand_init();
+ ret = (pre_scan->is_nand)? 0:1;
+ pre_scan->pre_scan_flag = 0;
+ return ret;
+}
+
+extern struct mtd_info *nand_info[CONFIG_SYS_MAX_NAND_DEVICE];
+int slcnand_fit_storage(void)
+{
+ struct storage_t *slc_nand = NULL;
+
+ struct aml_nand_chip *aml_chip = mtd_to_nand_chip(nand_info[0]);
+ struct aml_nand_flash_dev *type = NULL;
+
+ type = aml_chip->platform->nand_flash_dev;
+
+ if (slc_nand == NULL) {
+ slc_nand = kzalloc(sizeof(struct storage_t), GFP_KERNEL);
+ if (!slc_nand) {
+ debug("%s %d no enough memory!\n", __func__, __LINE__);
+ return -ENOMEM;
+ }
+ }
+
+ slc_nand->type = BOOT_NAND_MTD;
+ slc_nand->init_flag = 0;
+ printf("storage dev type: 0x%x, storage device is slc NAND\n",slc_nand->type);
+
+ memcpy(slc_nand->info.name, type->name, 32 * sizeof(char));
+ memcpy(slc_nand->info.id, type->id, 8);
+ printf("name: %s\n",slc_nand->info.name);
+
+ slc_nand->info.read_unit = type->pagesize;
+ slc_nand->info.write_unit = type->pagesize;
+ slc_nand->info.erase_unit = type->erasesize;
+ slc_nand->info.caps = ((type->chipsize) << 20);
+ printf("cap: 0x%llx\n", slc_nand->info.caps);
+ slc_nand->info.mode = 1;
+
+ mtd_store_mount_ops(slc_nand);
+
+ return store_register(slc_nand);
+}
+
+extern int meson_nfc_probe(struct udevice *dev);
+struct udevice *nand_dev;
+int nand_probe(uint32_t init_flag)
+{
+
+ meson_nfc_probe(nand_dev);
+
+ return 0;
+}
+
diff --git a/drivers/mtd/nand/raw/nand.c b/drivers/mtd/nand/raw/nand.c
index 806eaa6..19d6c77 100644
--- a/drivers/mtd/nand/raw/nand.c
+++ b/drivers/mtd/nand/raw/nand.c
@@ -156,7 +156,7 @@
initialized = 1;
#ifdef CONFIG_SYS_NAND_SELF_INIT
- printf("borad nand init\n");
+ printf("board nand init\n");
board_nand_init();
#else
int i;
diff --git a/drivers/mtd/nand/raw/nand_ids.c b/drivers/mtd/nand/raw/nand_ids.c
index 3104f87..2183b3a 100644
--- a/drivers/mtd/nand/raw/nand_ids.c
+++ b/drivers/mtd/nand/raw/nand_ids.c
@@ -202,6 +202,8 @@
{NAND_MFR_SANDISK, "SanDisk"},
{NAND_MFR_INTEL, "Intel"},
{NAND_MFR_ATO, "ATO"},
+ {NAND_MFR_GIGA, "Gigadevice"},
+ {NAND_MFR_ZETTA, "Zetta"},
{0x0, "Unknown"}
};
diff --git a/drivers/mtd/nand/spi-nand/Makefile b/drivers/mtd/nand/spi-nand/Makefile
new file mode 100644
index 0000000..22e7530
--- /dev/null
+++ b/drivers/mtd/nand/spi-nand/Makefile
@@ -0,0 +1,8 @@
+# SPDX-License-Identifier: GPL-2.0+
+#
+# (C) Copyright 2006
+#
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+
+obj-$(CONFIG_SPI_NAND) += aml_spinand.o
+obj-$(CONFIG_AML_STORAGE) += storage_sn.o
diff --git a/drivers/mtd/nand/spi-nand/aml_spinand.c b/drivers/mtd/nand/spi-nand/aml_spinand.c
new file mode 100644
index 0000000..739e0ab
--- /dev/null
+++ b/drivers/mtd/nand/spi-nand/aml_spinand.c
@@ -0,0 +1,2789 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <nand.h>
+#include <linux/log2.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/nand_ecc.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/mtd/partitions.h>
+#include <spi.h>
+#include <linux/types.h>
+#include <linux/sizes.h>
+#include <malloc.h>
+#include <linux/errno.h>
+#include <linux/io.h>
+#include <amlogic/aml_rsv.h>
+#include <amlogic/aml_mtd.h>
+#include <amlogic/spifc.h>
+#include <asm/arch/cpu_config.h>
+
+#define DUMMY_BYTE 0xab
+
+#define SPINAND_DRV_NAME "spinand"
+
+/* Flash opcodes. */
+ /* Write enable */
+#define SPINAND_CMD_WREN 0x06
+ /* Write disable */
+#define SPINAND_CMD_WRDI 0x04
+ /* Get feature */
+#define SPINAND_CMD_GETFEA 0x0F
+ /* Set feature */
+#define SPINAND_CMD_SETFEA 0x1F
+ /* read data to cache */
+#define SPINAND_CMD_READ 0x13
+ /* Read data bytes (low frequency) */
+#define SPINAND_CMD_NORM_READ 0x03
+ /* Read data bytes (high frequency) */
+#define SPINAND_CMD_FAST_READ 0x0B
+ /* Read data bytes (x2) */
+#define SPINAND_CMD_DUAL_READ 0x3B
+ /* Read data bytes (x4) */
+#define SPINAND_CMD_QUAD_READ 0x6B
+ /* Program load */
+#define SPINAND_CMD_PLOAD 0x02
+ /* Program load (x4) */
+#define SPINAND_CMD_QUAD_PLOAD 0x32
+ /* Program execute */
+#define SPINAND_CMD_PROG 0x10
+ /* Block erase */
+#define SPINAND_CMD_ERASE 0xD8
+ /* Read JEDEC ID */
+#define SPINAND_CMD_RDID 0x9F
+ /* reset nand flash */
+#define SPINAND_CMD_RESET 0xFF
+
+/* Flash Protection register */
+#define SPINAND_PROTEC_REG 0xA0
+#define SPINAND_PROTEC_BRWD 0x80
+#define SPINAND_PROTEC_BP2 0x20
+#define SPINAND_PROTEC_BP1 0x10
+#define SPINAND_PROTEC_BP0 0x08
+#define SPINAND_PROTEC_INV 0x04
+#define SPINAND_PROTEC_CMP 0x02
+
+/* Flash feature register */
+#define SPINAND_FEATURE_REG 0xB0
+#define SPINAND_FEATURE_OTPPRT 0x80
+#define SPINAND_FEATURE_OPTEN 0x40
+#define SPINAND_FEATURE_ECC_EN 0x10
+#define SPINAND_FEATURE_QE 0x01
+
+/* Flash status register. */
+#define SPINAND_STATUS_REG 0xC0
+#define SPINAND_STATUS_BUSY 0x1
+#define SPINAND_STATUS_WREN 0x2
+#define SPINAND_STATUS_EFAIL 0x4
+#define SPINAND_STATUS_PFAIL 0x8
+#define SPINAND_STATUS_ECCMASK 0x30
+#define SPINAND_STATUS_ECC(x) (x << 4)
+#define SPINAND_STATUS_ECC0 0x0
+#define SPINAND_STATUS_ECC1 0x1
+#define SPINAND_STATUS_ECC2 0x2
+#define SPINAND_STATUS_ECC3 0x3
+
+#define SPINAND_VERC_STATUS_ECCMASK 0x70
+#define SPINAND_VERC_STATUS_ERR 0x7
+
+/* Define max times to check status register before we give up. */
+#define MAX_CMD_SIZE 8
+#define SPINAND_SUBFEATURE_LEN 1
+
+#define MAX_READY_WAIT_JIFFIES (40 * HZ)
+#define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
+
+#define OOB1_ECCWRITE_SECTION 0xC
+#define OOB2_ECCWRITE_SECTION 0x1C
+#define OOB3_ECCWRITE_SECTION 0x2C
+#define OOB4_OOB1_SECTION 0x30
+#define OOB4_OOB2_SECTION 0x34
+#define OOB4_OOB3_SECTION 0x38
+
+#define OOB_REMOVESIZE 4
+#define OOB_SECTION_SIZE 16
+
+#define MANUFACTURE_ID 0xC8
+#define DEVICE_ID_A_1G_3V 0xF1
+#define DEVICE_ID_A_2G_3V 0xF2
+#define DEVICE_ID_A_4G_3V 0xF4
+#define DEVICE_ID_A_1G_1V 0xE1
+#define DEVICE_ID_A_2G_1V 0xE2
+#define DEVICE_ID_A_4G_1V 0xE4
+#define DEVICE_ID_B_1G_3V 0xD1
+#define DEVICE_ID_B_2G_3V 0xD2
+#define DEVICE_ID_B_4G_3V 0xD4
+#define DEVICE_ID_B_1G_1V 0xC1
+#define DEVICE_ID_B_2G_1V 0xC2
+#define DEVICE_ID_B_4G_1V 0xC4
+#define DEVICE_ID_C_1G_3V 0xB1
+#define DEVICE_ID_C_2G_3V 0xB2
+#define DEVICE_ID_C_4G_3V 0xB4
+#define DEVICE_ID_C_1G_1V 0xA1
+#define DEVICE_ID_C_2G_1V 0xA2
+#define DEVICE_ID_C_4G_1V 0xA4
+
+#define GIGA_SPINAND_CHIP_VER_A 0x0
+#define GIGA_SPINAND_CHIP_VER_B 0x1
+#define GIGA_SPINAND_CHIP_VER_B_LP 0x2
+#define GIGA_SPINAND_CHIP_VER_C 0x3
+
+/*
+ * we should put the spinand device in nand_info[x],
+ * and use command 'nand device x' to set spinand as
+ * current device before use nand command.
+ */
+#define SPINAND_INFO_ID 0
+
+struct spinand_info {
+ struct nand_hw_control controller;
+ struct nand_chip chip;
+ unsigned int planes_per_lun;
+#ifndef __UBOOT__
+ struct spi_device *pdev;
+#else
+ struct spi_slave *pdev;
+#endif
+ u8 cmd[MAX_CMD_SIZE];
+ u8 read_cmd;
+ u8 pload_cmd;
+ u8 chip_ver;
+ u16 cmd_len;
+ u16 oob_required;
+ u32 status;
+ u8 *bbt;
+ u8 bbt_scan;
+ char *name;
+ u8 id[NAND_MAX_ID_LEN];
+ struct meson_rsv_handler_t *rsv;
+};
+
+struct info_page {
+ char magic[8]; /* magic header of info page */
+ /* info page version, +1 when you update this struct */
+ u8 version; /* 1 for now */
+ u8 mode; /* 1 discrete, 0 compact */
+ u8 bl2_num; /* bl2 copy number */
+ u8 fip_num; /* fip copy number */
+ union {
+ struct {
+#define SPINAND_MAGIC "AMLIFPG"
+#define SPINAND_INFO_VER 1
+ u8 rd_max; /* spi nand max read io */
+ u8 oob_offset; /* user bytes offset */
+ u8 planes_per_lun;
+ u8 reserved;
+ u32 fip_start; /* start pages */
+ u32 fip_pages; /* pages per fip */
+ u32 page_size; /* spi nand page size (bytes) */
+ u32 page_per_blk; /* page number per block */
+ u32 oob_size; /* valid oob size (bytes) */
+ u32 bbt_start; /* bbt start pages */
+ u32 bbt_valid; /* bbt valid offset pages */
+ u32 bbt_size; /* bbt occupied bytes */
+ } s;/* spi nand */
+ struct {
+ u32 reserved;
+ } e;/* emmc */
+ } dev;
+
+};
+
+/*
+ * The chip ID list:
+ * name, device ID, page size, chip size in MiB, eraseblock size, options
+ */
+struct nand_flash_dev spi_nand_ids[] = {
+ {"SPI NAND GD5F1GQ4UA 128MiB 3.3V",
+ { .id = {0xc8, 0xf1} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_128M,
+ .erasesize = SZ_128K,
+ .options = 0,
+ .id_len = 2,
+ .oobsize = 64
+ },
+ {"SPI NAND GD5F2GQ4UA 256MiB 3.3V",
+ { .id = {0xc8, 0xf2} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_256M,
+ .erasesize = SZ_128K,
+ .options = 0,
+ .id_len = 2,
+ .oobsize = 64
+ },
+ {"SPI NAND GD5F4GQ4UA 512MiB 3.3V",
+ { .id = {0xc8, 0xf4} },
+ .pagesize = SZ_4K,
+ .chipsize = SZ_512M,
+ .erasesize = SZ_256K,
+ .options = 0,
+ .id_len = 2,
+ .oobsize = 128
+ },
+ {"SPI NAND GD5F1GQ4RA 128MiB 1.8V",
+ { .id = {0xc8, 0xe1} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_128M,
+ .erasesize = SZ_128K,
+ .options = 0,
+ .id_len = 2,
+ .oobsize = 64
+ },
+ {"SPI NAND GD5F2GQ4RA 256MiB 1.8V",
+ { .id = {0xc8, 0xe2} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_256M,
+ .erasesize = SZ_128K,
+ .options = 0,
+ .id_len = 2,
+ .oobsize = 64
+ },
+ {"SPI NAND GD5F4GQ4RA 512MiB 1.8V",
+ { .id = {0xc8, 0xe4} },
+ .pagesize = SZ_4K,
+ .chipsize = SZ_512M,
+ .erasesize = SZ_256K,
+ .options = 0,
+ .id_len = 2,
+ .oobsize = 128
+ },
+ {"SPI NAND GD5F1GQ4UB 128MiB 3.3V",
+ { .id = {0xc8, 0xD1} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_128M,
+ .erasesize = SZ_128K,
+ .options = SPI_RX_QUAD | SPI_TX_QUAD,
+ .id_len = 2,
+ .oobsize = 64
+ },
+ {"SPI NAND GD5F2GQ4UB 256MiB 3.3V",
+ { .id = {0xc8, 0xD2} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_256M,
+ .erasesize = SZ_128K,
+ .options = 0,
+ .id_len = 2,
+ .oobsize = 64
+ },
+ {"SPI NAND GD5F4GQ4UB 512MiB 3.3V",
+ { .id = {0xc8, 0xD4} },
+ .pagesize = SZ_4K,
+ .chipsize = SZ_512M,
+ .erasesize = SZ_256K,
+ .options = SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD,
+ //.options = 0,
+ .id_len = 2,
+ .oobsize = 128
+ },
+ {"SPI NAND GD5F1GQ4RB 128MiB 1.8V",
+ { .id = {0xc8, 0xC1} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_128M,
+ .erasesize = SZ_128K,
+ .options = 0,
+ .id_len = 2,
+ .oobsize = 64
+ },
+ {"SPI NAND GD5F2GQ4RB 256MiB 1.8V",
+ { .id = {0xc8, 0xC2} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_256M,
+ .erasesize = SZ_128K,
+ .options = 0,
+ .id_len = 2,
+ .oobsize = 64
+ },
+ {"SPI NAND GD5F4GQ4RB 512MiB 1.8V",
+ { .id = {0xc8, 0xC4} },
+ .pagesize = SZ_4K,
+ .chipsize = SZ_512M,
+ .erasesize = SZ_256K,
+ .options = 0,
+ .id_len = 2,
+ .oobsize = 128
+ },
+ {"SPI NAND GD5F1GQ1UC 128MiB 3.3V",
+ { .id = {0xc8, 0xB1} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_128M,
+ .erasesize = SZ_128K,
+ .options = 0,
+ .id_len = 2,
+ .oobsize = 64
+ },
+ {"SPI NAND GD5F2GQ4UC 256MiB 3.3V",
+ { .id = {0xc8, 0xB2} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_256M,
+ .erasesize = SZ_128K,
+ .options = 0,
+ .id_len = 2,
+ .oobsize = 64
+ },
+ {"SPI NAND GD5F4GQ4UC 512MiB 3.3V",
+ { .id = {0xc8, 0xB4} },
+ .pagesize = SZ_4K,
+ .chipsize = SZ_512M,
+ .erasesize = SZ_256K,
+ .options = 0,
+ .id_len = 2,
+ .oobsize = 128
+ },
+ {"SPI NAND GD5F1GQ1RC 128MiB 1.8V",
+ { .id = {0xc8, 0xA1} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_128M,
+ .erasesize = SZ_128K,
+ .options = 0,
+ .id_len = 2,
+ .oobsize = 64
+ },
+ {"SPI NAND GD5F2GQ4RC 256MiB 1.8V",
+ { .id = {0xc8, 0xA2} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_256M,
+ .erasesize = SZ_128K,
+ .options = 0,
+ .id_len = 2,
+ .oobsize = 64
+ },
+ {"SPI NAND GD5F4GQ4RC 512MiB 1.8V",
+ { .id = {0xc8, 0xA4} },
+ .pagesize = SZ_4K,
+ .chipsize = SZ_512M,
+ .erasesize = SZ_256K,
+ .options = 0,
+ .id_len = 2,
+ .oobsize = 128
+ },
+ {"SPI NAND TC58CVG1S3HRAIG 128MiB 3.3V",
+ { .id = {0x98, 0xcb} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_256M,
+ .erasesize = SZ_128K,
+ .options = 0,
+ .id_len = 2,
+ .oobsize = 64
+ },
+ {"SPI NAND TC58CVG0S3HRAIG 128MiB 3.3V",
+ { .id = {0x98, 0xc2} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_128M,
+ .erasesize = SZ_128K,
+ .options = SPI_RX_QUAD,
+ .id_len = 2,
+ .oobsize = 64
+ },
+ {"SPI NAND TC58CVG1S3HRAIG 256MiB 3.3V",
+ { .id = {0x98, 0xcb} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_256M,
+ .erasesize = SZ_128K,
+ .options = SPI_RX_QUAD,
+ .id_len = 2,
+ .oobsize = 64
+ },
+ {"SPI NAND ZD35Q1GA 128MiB 3.3V",
+ { .id = {0xba, 0x71} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_128M,
+ .erasesize = SZ_128K,
+ .options = SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD,
+ .id_len = 2,
+ .oobsize = 64
+ },
+ {"SPI NAND ZD35Q2GA 256MiB 3.3V",
+ { .id = {0xba, 0x72} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_256M,
+ .erasesize = SZ_128K,
+ .options = SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD,
+ .id_len = 2,
+ .oobsize = 64
+ },
+ {"SPI NAND ZD35M1GA 128MiB 1.8V",
+ { .id = {0xba, 0x21} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_128M,
+ .erasesize = SZ_128K,
+ .options = SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD,
+ .id_len = 2,
+ .oobsize = 64
+ },
+ {"SPI NAND MX35LF1GE4AB 128MiB 3.3V",
+ { .id = {0xc2, 0x12} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_128M,
+ .erasesize = SZ_128K,
+ .options = SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD,
+ .id_len = 2,
+ .oobsize = 64
+ },
+ {"MT29F2G01ABAGD/F50L2G41XA 256MiB 3.3V",
+ { .id = {0x2c, 0x24} },
+ .pagesize = SZ_2K,
+ .chipsize = SZ_256M,
+ .erasesize = SZ_128K,
+ .options = SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD,
+ .id_len = 2,
+ .oobsize = 64
+ },
+
+ {NULL}
+};
+
+static int chip_plane_ids[][3] = {
+ { 0xba, 0x72, 2 }, /* ZD35Q2GA */
+ { 0x2c, 0x24, 2 }, /* MT29F2G01ABAGD/F50L2G41XA */
+};
+
+
+#ifdef CONFIG_AML_STORAGE
+extern int spinand_fit_storage(struct nand_chip *chip, char *name, u8 *id);
+#endif
+
+#ifdef __UBOOT__
+static inline int spi_write(struct spi_slave *spi,
+ const void *buf, size_t len)
+{
+ return spi_xfer(spi, len << 3, buf, NULL,
+ SPI_XFER_BEGIN | SPI_XFER_END);
+}
+
+static inline int spi_write_then_read(struct spi_slave *spi,
+ const void *txbuf, unsigned int n_tx,
+ void *rxbuf, unsigned int n_rx)
+{
+ spi_xfer(spi, n_tx << 3, txbuf, NULL, SPI_XFER_BEGIN);
+ return spi_xfer(spi, n_rx << 3, NULL, rxbuf, SPI_XFER_END);
+}
+#endif /* __UBOOT__ */
+
+/* Define default oob placement schemes for large and small page devices */
+static struct nand_ecclayout nand_oob_8 = {
+ .eccbytes = 3,
+ .eccpos = {0, 1, 2},
+ .oobfree = {
+ {
+ .offset = 3,
+ .length = 2
+ },
+ {
+ .offset = 6,
+ .length = 2
+ }
+ }
+};
+
+static struct nand_ecclayout nand_oob_16 = {
+ .eccbytes = 6,
+ .eccpos = {0, 1, 2, 3, 6, 7},
+ .oobfree = {
+ {
+ .offset = 8,
+ .length = 8
+ }
+ }
+};
+
+static struct nand_ecclayout nand_oob_64 = {
+ .eccbytes = 24,
+ .eccpos = {
+ 40, 41, 42, 43, 44, 45, 46, 47,
+ 48, 49, 50, 51, 52, 53, 54, 55,
+ 56, 57, 58, 59, 60, 61, 62, 63
+ },
+ .oobfree = {
+ {
+ /* Spare Area 62 */
+ .offset = 2,
+ .length = 62
+ }
+ }
+};
+
+static struct nand_ecclayout nand_oob_128 = {
+ .eccbytes = 48,
+ .eccpos = {
+ 80, 81, 82, 83, 84, 85, 86, 87,
+ 88, 89, 90, 91, 92, 93, 94, 95,
+ 96, 97, 98, 99, 100, 101, 102, 103,
+ 104, 105, 106, 107, 108, 109, 110, 111,
+ 112, 113, 114, 115, 116, 117, 118, 119,
+ 120, 121, 122, 123, 124, 125, 126, 127
+ },
+ .oobfree = {
+ {
+ .offset = 2,
+ .length = 78
+ }
+ }
+};
+
+static int spinand_get_feature(struct mtd_info *mtd, struct nand_chip *chip,
+ int addr, u8 *subfeature_param);
+static int spinand_set_feature(struct mtd_info *mtd, struct nand_chip *chip,
+ int addr, u8 *subfeature_param);
+static int spinand_set_qeb(struct mtd_info *mtd, struct nand_chip *chip);
+
+static inline struct spinand_info *mtd_to_spinand(struct mtd_info *mtd)
+{
+ /* see nand_info in spinand_probe() */
+ struct nand_chip *chip = mtd->priv;
+
+ return container_of(chip, struct spinand_info, chip);
+}
+
+static int check_offs_len(struct mtd_info *mtd, loff_t offs, u64 len)
+{
+ struct nand_chip *chip = mtd->priv;
+ int ret = 0;
+
+ /* Start address must align on block boundary */
+ if (offs & ((1 << chip->phys_erase_shift) - 1)) {
+ pr_err("%s: unaligned address\n", __func__);
+ ret = -EINVAL;
+ }
+ /* Length must align on block boundary */
+ if (len & ((1 << chip->phys_erase_shift) - 1)) {
+ pr_err("%s: length not block aligned\n", __func__);
+ ret = -EINVAL;
+ }
+ return ret;
+}
+
+static u8 *transfer_oob(struct nand_chip *chip, u8 *oob,
+ struct mtd_oob_ops *ops, size_t len)
+{
+ switch (ops->mode) {
+ case MTD_OPS_PLACE_OOB:
+ case MTD_OPS_RAW:
+ memcpy(oob, chip->oob_poi + ops->ooboffs, len);
+ return oob + len;
+
+ case MTD_OPS_AUTO_OOB: {
+ struct nand_oobfree *free = chip->ecc.layout->oobfree;
+ u32 boffs = 0, roffs = ops->ooboffs;
+ size_t bytes = 0;
+
+ for (; free->length && len; free++, len -= bytes) {
+ /* Read request not from offset 0? */
+ if (unlikely(roffs)) {
+ if (roffs >= free->length) {
+ roffs -= free->length;
+ continue;
+ }
+ boffs = free->offset + roffs;
+ bytes = min_t(size_t, len,
+ (free->length - roffs));
+ roffs = 0;
+ } else {
+ bytes = min_t(size_t, len, free->length);
+ boffs = free->offset;
+ }
+ memcpy(oob, chip->oob_poi + boffs, bytes);
+ oob += bytes;
+ }
+ return oob;
+ }
+ default:
+ WARN_ON(1);
+ }
+ return NULL;
+}
+
+static unsigned int plane_of_page_addr(struct mtd_info *mtd,
+ u32 page_addr)
+{
+ struct spinand_info *info = mtd_to_spinand(mtd);
+ struct nand_chip *chip = mtd->priv;
+
+ return ((page_addr >> (chip->phys_erase_shift - chip->page_shift))
+ % info->planes_per_lun);
+}
+
+static void spinand_cmdfunc(struct mtd_info *mtd,
+ unsigned int command,
+ int column, int page_addr)
+{
+ struct spinand_info *info = mtd_to_spinand(mtd);
+ struct nand_chip *chip = mtd->priv;
+ unsigned int plane;
+
+ memset(info->cmd, 0, MAX_CMD_SIZE);
+ info->cmd[0] = command;
+ switch (info->cmd[0]) {
+ case SPINAND_CMD_RESET:
+ case SPINAND_CMD_WREN:
+ case SPINAND_CMD_WRDI:
+ info->cmd_len = 1;
+ spi_write(info->pdev, info->cmd, info->cmd_len);
+ break;
+
+ case SPINAND_CMD_RDID:
+ info->cmd[1] = column;
+ info->cmd_len = 2;
+ break;
+
+ case SPINAND_CMD_GETFEA:
+ info->cmd[1] = page_addr;
+ info->cmd_len = 2;
+ break;
+
+ case SPINAND_CMD_SETFEA:
+ info->cmd[1] = page_addr;
+ info->cmd[2] = column;
+ info->cmd_len = 3;
+ break;
+
+ case SPINAND_CMD_READ:
+ case SPINAND_CMD_PROG:
+ case SPINAND_CMD_ERASE:
+ info->cmd[1] = (u8)(page_addr >> 16);
+ info->cmd[2] = (u8)(page_addr >> 8);
+ info->cmd[3] = (u8)(page_addr);
+ info->cmd_len = 4;
+ spi_write(info->pdev, info->cmd, info->cmd_len);
+ break;
+
+ case SPINAND_CMD_PLOAD:
+ case SPINAND_CMD_QUAD_PLOAD:
+ if (info->planes_per_lun > 1) {
+ plane = plane_of_page_addr(mtd, page_addr);
+ column |= plane << (chip->page_shift + 1);
+ }
+ info->cmd[1] = (u8)(column >> 8);
+ info->cmd[2] = (u8)(column);
+ info->cmd_len = 3;
+ break;
+
+ case SPINAND_CMD_NORM_READ:
+ case SPINAND_CMD_FAST_READ:
+ case SPINAND_CMD_DUAL_READ:
+ case SPINAND_CMD_QUAD_READ:
+ if (info->planes_per_lun > 1) {
+ plane = plane_of_page_addr(mtd, page_addr);
+ column |= plane << (chip->page_shift + 1);
+ }
+ if (info->chip_ver != GIGA_SPINAND_CHIP_VER_C) {
+ info->cmd[1] = (u8)(column >> 8);
+ info->cmd[2] = (u8)(column);
+ info->cmd_len = 4;
+ } else {
+ info->cmd[2] = (u8)(column >> 8);
+ info->cmd[3] = (u8)(column);
+ info->cmd_len = 4;
+ }
+ break;
+
+ default:
+ break;
+ }
+}
+
+static int spinand_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
+{
+ int status, state = chip->state;
+ unsigned long timeo = (state == FL_ERASING ? 400 : 30);
+
+ /**
+ * Apply this short delay always to ensure that we do wait tWB in any
+ * case on any machine.
+ */
+ ndelay(100);
+
+ chip->cmdfunc(mtd, SPINAND_CMD_GETFEA, -1, 0xC0);
+#ifndef __UBOOT__
+ timeo = jiffies + msecs_to_jiffies(timeo);
+ while (time_before(jiffies, timeo)) {
+#else
+ timeo <<= 10;
+ while (timeo--) {
+#endif
+ status = chip->read_byte(mtd);
+ if ((status & SPINAND_STATUS_BUSY) == 0x0)
+ break;
+ cond_resched();
+ }
+
+ status = (int)chip->read_byte(mtd);
+
+ /* This_can_happen if_in case_of timeout or_buggy_dev_ready */
+ WARN_ON(status & SPINAND_STATUS_BUSY);
+ return status;
+}
+
+static int spinand_get_device(struct mtd_info *mtd, int new_state)
+{
+ struct nand_chip *chip = mtd->priv;
+#ifndef __UBOOT__
+ spinlock_t *lock = &chip->controller->lock;
+ wait_queue_head_t *wq = &chip->controller->wq;
+ DECLARE_WAITQUEUE(wait, current);
+retry:
+ spin_lock(lock);
+
+ /* Hardware controller shared among independent devices */
+ if (!chip->controller->active)
+ chip->controller->active = chip;
+
+ if (chip->controller->active == chip && chip->state == FL_READY) {
+ chip->state = new_state;
+ spin_unlock(lock);
+ return 0;
+ }
+ if (new_state == FL_PM_SUSPENDED) {
+ if (chip->controller->active->state == FL_PM_SUSPENDED) {
+ chip->state = FL_PM_SUSPENDED;
+ spin_unlock(lock);
+ return 0;
+ }
+ }
+ set_current_state(TASK_UNINTERRUPTIBLE);
+ add_wait_queue(wq, &wait);
+ spin_unlock(lock);
+ schedule();
+ remove_wait_queue(wq, &wait);
+ goto retry;
+#else
+ if (!chip->controller->active)
+ chip->controller->active = chip;
+ if (chip->controller->active == chip && chip->state == FL_READY)
+ chip->state = new_state;
+ return 0;
+#endif
+}
+
+static void spinand_release_device(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+#ifndef __UBOOT__
+ /* Release the controller and the chip */
+ spin_lock(&chip->controller->lock);
+ chip->controller->active = NULL;
+ chip->state = FL_READY;
+ wake_up(&chip->controller->wq);
+ spin_unlock(&chip->controller->lock);
+#else
+ chip->state = FL_READY;
+#endif
+}
+
+static void reset_spinand_device(struct mtd_info *mtd)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ chip->cmdfunc(mtd, SPINAND_CMD_RESET, -1, -1);
+ chip->waitfunc(mtd, chip);
+}
+
+static u8 *fill_oob(struct mtd_info *mtd, u8 *oob,
+ size_t len, struct mtd_oob_ops *ops)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ /**
+ * Initialise to all 0xFF, to avoid the possibility of left over OOB
+ * data from a previous OOB read.
+ */
+ memset(chip->oob_poi, 0xff, mtd->oobsize);
+
+ switch (ops->mode) {
+ case MTD_OPS_PLACE_OOB:
+ case MTD_OPS_RAW:
+ memcpy(chip->oob_poi + ops->ooboffs, oob, len);
+ return oob + len;
+
+ case MTD_OPS_AUTO_OOB: {
+ struct nand_oobfree *free = chip->ecc.layout->oobfree;
+ u32 boffs = 0, woffs = ops->ooboffs;
+ size_t bytes = 0;
+
+ for (; free->length && len; free++, len -= bytes) {
+ /* Write request not from offset 0? */
+ if (unlikely(woffs)) {
+ if (woffs >= free->length) {
+ woffs -= free->length;
+ continue;
+ }
+ boffs = free->offset + woffs;
+ bytes = min_t(size_t, len,
+ (free->length - woffs));
+ woffs = 0;
+ } else {
+ bytes = min_t(size_t, len, free->length);
+ boffs = free->offset;
+ }
+ memcpy(chip->oob_poi + boffs, oob, bytes);
+ oob += bytes;
+ }
+ return oob;
+ }
+ default:
+ WARN_ON(1);
+ }
+ return NULL;
+}
+
+static int spinand_erase_block(struct mtd_info *mtd, int page)
+{
+ struct nand_chip *chip = mtd->priv;
+ int status;
+
+ chip->cmdfunc(mtd, SPINAND_CMD_WREN, -1, -1);
+ chip->cmdfunc(mtd, SPINAND_CMD_ERASE, 0, page);
+ status = chip->waitfunc(mtd, chip);
+ chip->cmdfunc(mtd, SPINAND_CMD_WRDI, -1, -1);
+ return status;
+}
+
+int erase_nand(struct mtd_info *mtd, struct erase_info *instr, int allowbbt)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct spinand_info *info = mtd_to_spinand(mtd);
+ int page;
+ int status;
+ int pages_per_block;
+ int ret;
+ u64 len;
+
+ if (check_offs_len(mtd, instr->addr, instr->len))
+ return -EINVAL;
+
+ /* Grab_the_lock and see if_the device is available */
+ spinand_get_device(mtd, FL_ERASING);
+
+ if (meson_rsv_erase_protect(info->rsv, instr->addr / mtd->erasesize)) {
+ printf("%s blk 0x%x is protected\n", __func__,
+ (unsigned int)instr->addr / mtd->erasesize);
+ goto erase_exit;
+ }
+
+ /* Shift to get first page */
+ page = (int)(instr->addr >> chip->page_shift);
+
+ /* Calculate pages in each block */
+ pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
+
+ /* Loop through the pages */
+ len = instr->len;
+
+ instr->state = MTD_ERASING;
+
+ while (len) {
+ /**
+ * Invalidate the page cache, if we erase the block which
+ * contains the current cached page.
+ */
+ if (page <= chip->pagebuf &&
+ chip->pagebuf < (page + pages_per_block))
+ chip->pagebuf = -1;
+
+ chip->erase(mtd, page);
+ status = chip->waitfunc(mtd, chip);
+
+ /* See if block erase succeeded */
+ if (status & SPINAND_STATUS_EFAIL) {
+ pr_err("%s: failed erase, page 0x%08x\n",
+ __func__, page);
+ instr->state = MTD_ERASE_FAILED;
+ instr->fail_addr = ((loff_t)page << chip->page_shift);
+ goto erase_exit;
+ }
+
+ /* Increment page address and decrement length */
+ len -= (1 << chip->phys_erase_shift);
+ page += pages_per_block;
+ }
+
+ instr->state = MTD_ERASE_DONE;
+
+erase_exit:
+ ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
+ spinand_release_device(mtd);
+
+ /* Do call back function */
+ if (!ret)
+ mtd_erase_callback(instr);
+
+ /* Return more or less happy */
+ return ret;
+}
+
+static int spinand_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
+{
+ pr_debug("%s: from = 0x%08x, len = 0x%04x\n",
+ __func__, (u32)instr->addr, (u32)instr->len);
+
+ return erase_nand(mtd, instr, 0);
+}
+
+static u8 spinand_read_byte(struct mtd_info *mtd)
+{
+ struct spinand_info *info = mtd_to_spinand(mtd);
+ u8 val = 0;
+ int retval;
+
+ retval = spi_write_then_read(info->pdev,
+ info->cmd,
+ info->cmd_len,
+ &val,
+ 1);
+
+ if (retval < 0)
+ dev_err(&info->pdev->dev,
+ "error %d reading byte\n",
+ (int)retval);
+
+ return val;
+}
+
+static void spinand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
+{
+ struct spinand_info *info = mtd_to_spinand(mtd);
+ struct nand_chip *chip = mtd->priv;
+ u8 *oobtemp;
+#ifdef __UBOOT__
+ info->status = spi_xfer(info->pdev, info->cmd_len << 3,
+ info->cmd, NULL, SPI_XFER_BEGIN);
+ info->status = spi_xfer(info->pdev, len << 3, NULL, buf, 0);
+ info->status = spi_xfer(info->pdev, mtd->oobsize << 3, NULL,
+ chip->oob_poi, SPI_XFER_END);
+#else
+ struct spi_transfer xfers[3];
+ struct spi_message msg;
+
+ spi_message_init(&msg);
+ memset(xfers, 0, sizeof(xfers));
+
+ xfers[0].tx_buf = info->cmd;
+ xfers[0].len = info->cmd_len;
+ if (info->read_cmd == SPINAND_CMD_DUAL_READ)
+ xfers[0].rx_nbits = SPI_NBITS_DUAL;
+ else if (info->read_cmd == SPINAND_CMD_QUAD_READ)
+ xfers[0].rx_nbits = SPI_NBITS_QUAD;
+ spi_message_add_tail(&xfers[0], &msg);
+
+ if (buf) {
+ xfers[1].rx_buf = buf;
+ xfers[1].len = len;
+ spi_message_add_tail(&xfers[1], &msg);
+ }
+
+ if (info->oob_required) {
+ xfers[2].rx_buf = chip->oob_poi;
+ xfers[2].len = mtd->oobsize;
+ spi_message_add_tail(&xfers[2], &msg);
+ }
+
+ info->status = spi_sync(info->pdev, &msg);
+#endif
+ if (info->oob_required) {
+ if (info->chip_ver == GIGA_SPINAND_CHIP_VER_A) {
+ memcpy((chip->oob_poi + OOB1_ECCWRITE_SECTION),
+ (chip->oob_poi + OOB4_OOB1_SECTION),
+ OOB_REMOVESIZE);
+ memcpy((chip->oob_poi + OOB2_ECCWRITE_SECTION),
+ (chip->oob_poi + OOB4_OOB2_SECTION),
+ OOB_REMOVESIZE);
+ memcpy((chip->oob_poi + OOB3_ECCWRITE_SECTION),
+ (chip->oob_poi + OOB4_OOB3_SECTION),
+ OOB_REMOVESIZE);
+
+ oobtemp = (chip->oob_poi + OOB4_OOB1_SECTION);
+ memset(oobtemp, 0xff, OOB_SECTION_SIZE);
+ }
+ }
+ info->oob_required = 0;
+}
+
+static int spinand_read_page_raw(struct mtd_info *mtd,
+ struct nand_chip *chip, u8 *buf,
+ int oob_required,
+ int page)
+{
+ struct spinand_info *info = mtd_to_spinand(mtd);
+
+ info->oob_required = oob_required;
+ chip->read_buf(mtd, buf, mtd->writesize);
+
+ return info->status;
+}
+
+static int spinand_read_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip,
+ u8 *buf, int oob_required, int page)
+{
+ struct spinand_info *info = mtd_to_spinand(mtd);
+ u8 get_feature = 0x0;
+
+ info->oob_required = oob_required;
+ chip->read_buf(mtd, buf, mtd->writesize);
+ spinand_set_feature(mtd, chip, SPINAND_STATUS_REG, &get_feature);
+ if (info->chip_ver != GIGA_SPINAND_CHIP_VER_C) {
+ if ((get_feature & SPINAND_STATUS_ECCMASK) ==
+ (SPINAND_STATUS_ECC(SPINAND_STATUS_ECC2))) {
+ mtd->ecc_stats.failed++;
+ pr_debug("ecc err for page read\n");
+ return -EBADMSG;
+ }
+ } else {
+ if ((get_feature & SPINAND_VERC_STATUS_ECCMASK) ==
+ (SPINAND_STATUS_ECC(SPINAND_VERC_STATUS_ERR))) {
+ mtd->ecc_stats.failed++;
+ pr_debug("ecc err for page read\n");
+ return -EBADMSG;
+ }
+ }
+ mtd->ecc_stats.corrected++;
+ return info->status;
+}
+
+static int spinand_do_read_ops(struct mtd_info *mtd,
+ loff_t from, struct mtd_oob_ops *ops)
+{
+ int page, realpage, col, bytes, aligned, oob_required;
+ struct nand_chip *chip = mtd->priv;
+ struct mtd_ecc_stats stats;
+ int ret = 0;
+ u32 readlen = ops->len;
+ u32 oobreadlen = ops->ooblen;
+ u32 max_oobsize =
+ ops->mode == MTD_OPS_AUTO_OOB ? mtd->oobavail : mtd->oobsize;
+ u8 *bufpoi, *oob, *buf;
+ unsigned int max_bitflips = 0;
+
+ stats = mtd->ecc_stats;
+ realpage = (int)(from >> chip->page_shift);
+ page = realpage & chip->pagemask;
+
+ col = (int)(from & (mtd->writesize - 1));
+
+ buf = ops->datbuf;
+ oob = ops->oobbuf;
+ oob_required = oob ? 1 : 0;
+
+ while (1) {
+ bytes = min(mtd->writesize - col, readlen);
+ aligned = (bytes == mtd->writesize);
+ max_bitflips = 0;
+
+ /* Is the current page in the buffer? */
+ if (realpage != chip->pagebuf || oob) {
+ bufpoi = aligned ? buf : chip->buffers->databuf;
+
+ chip->cmdfunc(mtd, SPINAND_CMD_READ, -1, page);
+ chip->waitfunc(mtd, chip);
+
+ /**
+ * Now read the page into the buffer. Absent an error,
+ * the read methods return max bitflips per ecc step.
+ */
+ struct spinand_info *info = mtd_to_spinand(mtd);
+ if (info->read_cmd == SPINAND_CMD_QUAD_READ &&
+ ((info->id[0] == NAND_MFR_GIGA) ||
+ (info->id[0] == NAND_MFR_MACRONIX) ||
+ (info->id[0] == NAND_MFR_ZETTA)))
+ spinand_set_qeb(mtd, chip);
+ chip->cmdfunc(mtd, info->read_cmd, 0, page);
+ if (unlikely(ops->mode == MTD_OPS_RAW))
+ ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
+ oob_required, page);
+ else
+ ret = chip->ecc.read_page(mtd, chip, bufpoi,
+ oob_required, page);
+
+ if (ret < 0) {
+ if (!aligned) {
+ /* Invalidate page cache */
+ chip->pagebuf = -1;
+ break;
+ }
+ }
+ max_bitflips = max_t(unsigned int, max_bitflips, ret);
+
+ /* Transfer not aligned data */
+ if (!aligned) {
+ if (!oob &&
+ !(mtd->ecc_stats.failed - stats.failed) &&
+ ops->mode != MTD_OPS_RAW) {
+ chip->pagebuf = realpage;
+ chip->pagebuf_bitflips = ret;
+ } else {
+ /* Invalidate page cache */
+ chip->pagebuf = -1;
+ }
+ memcpy(buf,
+ chip->buffers->databuf + col,
+ bytes);
+ }
+
+ buf += bytes;
+
+ if (unlikely(oob)) {
+ int toread = min(oobreadlen, max_oobsize);
+
+ if (toread) {
+ oob = transfer_oob(chip,
+ oob, ops, toread);
+ oobreadlen -= toread;
+ }
+ }
+ } else {
+ memcpy(buf, chip->buffers->databuf + col, bytes);
+ buf += bytes;
+ max_bitflips = max_t(unsigned int, max_bitflips,
+ chip->pagebuf_bitflips);
+ }
+
+ readlen -= bytes;
+
+ if (!readlen)
+ break;
+
+ /* For subsequent reads align to page boundary */
+ col = 0;
+ /* Increment page address */
+ realpage++;
+
+ page = realpage & chip->pagemask;
+ }
+
+ ops->retlen = ops->len - (size_t)readlen;
+ if (oob)
+ ops->oobretlen = ops->ooblen - oobreadlen;
+
+ if (ret < 0)
+ return ret;
+
+ if (mtd->ecc_stats.failed - stats.failed)
+ return -EBADMSG;
+
+ return max_bitflips;
+}
+
+static int spinand_mtd_read(struct mtd_info *mtd,
+ loff_t from, size_t len, size_t *retlen, u8 *buf)
+{
+ struct mtd_oob_ops ops;
+ int ret;
+
+ pr_debug("%s: from = 0x%08x, len = 0x%04x\n",
+ __func__, (u32)from, (u32)len);
+
+ spinand_get_device(mtd, FL_READING);
+ memset(&ops, 0, sizeof(struct mtd_oob_ops));
+ ops.len = len;
+ ops.datbuf = buf;
+ ops.mode = MTD_OPS_PLACE_OOB;
+ ret = spinand_do_read_ops(mtd, from, &ops);
+ *retlen = ops.retlen;
+ spinand_release_device(mtd);
+ return ret;
+}
+
+static int spinand_read_oob_std(struct mtd_info *mtd,
+ struct nand_chip *chip, int page)
+{
+ struct spinand_info *info = mtd_to_spinand(mtd);
+
+ info->oob_required = 1;
+ chip->read_buf(mtd, NULL, 0);
+ return 0;
+}
+
+static int spinand_set_infopage(struct mtd_info *mtd,
+ struct info_page *info_page)
+{
+ struct spinand_info *spinand = mtd_to_spinand(mtd);
+ u32 page_per_blk;
+
+ page_per_blk = mtd->erasesize / mtd->writesize;
+ memcpy(info_page->magic, SPINAND_MAGIC, strlen(SPINAND_MAGIC));
+ info_page->version = SPINAND_INFO_VER;
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER)
+ info_page->mode = 1;
+ else
+ info_page->mode = 0;
+
+ info_page->bl2_num = CONFIG_BL2_COPY_NUM;
+ info_page->fip_num = CONFIG_NAND_TPL_COPY_NUM;
+ switch (spinand->read_cmd) {
+ case SPINAND_CMD_QUAD_READ:
+ if (spinand->id[0] != NAND_MFR_GIGA)
+ info_page->dev.s.rd_max = 4;
+ else
+ info_page->dev.s.rd_max = 2;
+ break;
+ case SPINAND_CMD_DUAL_READ:
+ info_page->dev.s.rd_max = 2;
+ break;
+ default:
+ info_page->dev.s.rd_max = 1;
+ break;
+ }
+ info_page->dev.s.fip_start =
+ BOOT_TOTAL_PAGES + NAND_RSV_BLOCK_NUM * page_per_blk;
+ info_page->dev.s.fip_pages = CONFIG_TPL_SIZE_PER_COPY / mtd->writesize;
+ info_page->dev.s.page_size = mtd->writesize;
+ info_page->dev.s.page_per_blk = page_per_blk;
+ info_page->dev.s.oob_size = mtd->oobsize;
+ info_page->dev.s.planes_per_lun = spinand->planes_per_lun;
+ info_page->dev.s.oob_offset = mtd->ecclayout->oobfree[0].offset;
+ if (spinand->rsv->bbt->valid) {
+ info_page->dev.s.bbt_start =
+ spinand->rsv->bbt->nvalid->blk_addr / mtd->writesize;
+ info_page->dev.s.bbt_valid =
+ spinand->rsv->bbt->nvalid->page_addr / mtd->writesize;
+ info_page->dev.s.bbt_size = spinand->rsv->bbt->size;
+ } else {
+ pr_debug("%s %d error! please scan bbt first!\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ return 0;
+}
+
+static int spinand_do_read_oob(struct mtd_info *mtd,
+ loff_t from, struct mtd_oob_ops *ops)
+{
+ int page, realpage;
+ struct nand_chip *chip = mtd->priv;
+ struct mtd_ecc_stats stats;
+ int readlen = ops->ooblen;
+ int len;
+ u8 *buf = ops->oobbuf;
+ int ret = 0;
+
+ stats = mtd->ecc_stats;
+
+ if (ops->mode == MTD_OPS_AUTO_OOB)
+ len = chip->ecc.layout->oobavail;
+ else
+ len = mtd->oobsize;
+
+ if (unlikely(ops->ooboffs >= len)) {
+ pr_err("%s: attempt to start read outside oob\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ /* Do not allow reads past end of device */
+ if (unlikely(from >= mtd->size ||
+ ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
+ (from >> chip->page_shift)) * len)) {
+ pr_err("%s: attempt to read beyond end of device\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ /* Shift to get page */
+ realpage = (int)(from >> chip->page_shift);
+ page = realpage & chip->pagemask;
+
+ while (1) {
+ chip->cmdfunc(mtd, SPINAND_CMD_READ, -1, page);
+ chip->waitfunc(mtd, chip);
+ struct spinand_info *info = mtd_to_spinand(mtd);
+ if (info->read_cmd == SPINAND_CMD_QUAD_READ &&
+ ((info->id[0] == NAND_MFR_GIGA) ||
+ (info->id[0] == NAND_MFR_MACRONIX) ||
+ (info->id[0] == NAND_MFR_ZETTA)))
+ spinand_set_qeb(mtd, chip);
+ chip->cmdfunc(mtd, info->read_cmd, mtd->writesize, page);
+
+ if (ops->mode == MTD_OPS_RAW)
+ ret = chip->ecc.read_oob_raw(mtd, chip, page);
+ else
+ ret = chip->ecc.read_oob(mtd, chip, page);
+
+ if (ret < 0)
+ break;
+
+ len = min(len, readlen);
+ buf = transfer_oob(chip, buf, ops, len);
+
+ readlen -= len;
+ if (!readlen)
+ break;
+
+ /* Increment page address */
+ realpage++;
+
+ page = realpage & chip->pagemask;
+ /* Check, if we cross a chip boundary */
+ }
+
+ ops->oobretlen = ops->ooblen - readlen;
+
+ if (ret < 0)
+ return ret;
+
+ if (mtd->ecc_stats.failed - stats.failed)
+ return -EBADMSG;
+
+ return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
+}
+
+static int spinand_mtd_read_oob(struct mtd_info *mtd,
+ loff_t from, struct mtd_oob_ops *ops)
+{
+ int ret = -ENOTSUPP;
+
+ pr_debug("%s: %s, from = 0x%08x, len = 0x%04x, ",
+ __func__, ops->datbuf ? "DATA" : "NULL",
+ (u32)from, (u32)ops->len);
+ pr_debug("ooboffs = 0x%04x, ooblen = 0x%02x\n",
+ (u32)ops->ooboffs, (u32)ops->ooblen);
+
+ ops->retlen = 0;
+
+ /* Do not allow reads past end of device */
+ if (ops->datbuf && (from + ops->len) > mtd->size) {
+ pr_err("%s: attempt to read beyond end of device\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ spinand_get_device(mtd, FL_READING);
+
+ switch (ops->mode) {
+ case MTD_OPS_PLACE_OOB:
+ case MTD_OPS_AUTO_OOB:
+ case MTD_OPS_RAW:
+ break;
+
+ default:
+ goto out;
+ }
+
+ if (!ops->datbuf)
+ ret = spinand_do_read_oob(mtd, from, ops);
+ else
+ ret = spinand_do_read_ops(mtd, from, ops);
+
+ spinand_release_device(mtd);
+out:
+ return ret;
+}
+
+static void spinand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
+{
+ struct spinand_info *info = mtd_to_spinand(mtd);
+ struct nand_chip *chip = mtd->priv;
+
+ if (info->oob_required) {
+ if (info->chip_ver == GIGA_SPINAND_CHIP_VER_A) {
+ memcpy((chip->oob_poi + OOB4_OOB1_SECTION),
+ (chip->oob_poi + OOB1_ECCWRITE_SECTION),
+ OOB_REMOVESIZE);
+ memcpy((chip->oob_poi + OOB4_OOB2_SECTION),
+ (chip->oob_poi + OOB2_ECCWRITE_SECTION),
+ OOB_REMOVESIZE);
+ memcpy((chip->oob_poi + OOB4_OOB3_SECTION),
+ (chip->oob_poi + OOB3_ECCWRITE_SECTION),
+ OOB_REMOVESIZE);
+ }
+ }
+#ifdef __UBOOT__
+ info->status = spi_xfer(info->pdev, info->cmd_len << 3,
+ info->cmd, NULL, SPI_XFER_BEGIN);
+ info->status = spi_xfer(info->pdev, len << 3, buf, NULL, 0);
+ info->status = spi_xfer(info->pdev, mtd->oobsize << 3,
+ chip->oob_poi, NULL, SPI_XFER_END);
+#else
+ struct spi_transfer xfers[3];
+ struct spi_message msg;
+
+ spi_message_init(&msg);
+ memset(xfers, 0, sizeof(xfers));
+ xfers[0].tx_buf = info->cmd;
+ xfers[0].len = info->cmd_len;
+
+ if (info->pload_cmd == SPINAND_CMD_QUAD_PLOAD)
+ xfers[0].tx_nbits = SPI_NBITS_QUAD;
+ spi_message_add_tail(&xfers[0], &msg);
+
+ if (buf) {
+ xfers[1].tx_buf = buf;
+ xfers[1].len = len;
+ spi_message_add_tail(&xfers[1], &msg);
+ }
+
+ if (info->oob_required) {
+ xfers[2].tx_buf = chip->oob_poi;
+ xfers[2].len = mtd->oobsize;
+ spi_message_add_tail(&xfers[2], &msg);
+ }
+ info->status = spi_sync(info->pdev, &msg);
+#endif
+ info->oob_required = 0;
+}
+
+static int spinand_write_page_raw(struct mtd_info *mtd,
+ struct nand_chip *chip, const u8 *buf,
+ int oob_required, int page)
+{
+ struct spinand_info *info = mtd_to_spinand(mtd);
+ int status;
+
+ info->oob_required = oob_required;
+ chip->write_buf(mtd, buf, mtd->writesize);
+
+ if (info->status < 0)
+ return info->status;
+
+ chip->cmdfunc(mtd, SPINAND_CMD_PROG, -1, page);
+ status = chip->waitfunc(mtd, chip);
+ chip->cmdfunc(mtd, SPINAND_CMD_WRDI, -1, -1);
+
+ /**
+ * See if operation failed and additional status checks are
+ * available.
+ */
+ if (status & SPINAND_STATUS_PFAIL) {
+ pr_err("%s: error %02x program failed\n",
+ __func__, (u32)status);
+ return -EIO;
+ }
+ #if 1
+ /**
+ * TODO:
+ * 1.modify this 2048 size when romcode limit fixed up
+ * 2.you should consider about handle info page position
+ * in here or in upon caller(ps: bad block count)
+ */
+ if (unlikely((page % 128) == ((BL2_SIZE / 2048) - 1) &&
+ page < BOOT_TOTAL_PAGES)) {
+ struct info_page *info_buf = NULL;
+
+ info_buf = kzalloc(sizeof(*info_buf), GFP_KERNEL);
+ memset(info_buf, 0, sizeof(struct info_page));
+ if (spinand_set_infopage(mtd, info_buf))
+ return -EIO;
+
+ pr_debug("%s %d write info page to page %d\n",
+ __func__, __LINE__, (page + 1));
+ chip->cmdfunc(mtd, SPINAND_CMD_WREN, -1, -1);
+ chip->cmdfunc(mtd, info->pload_cmd, 0x00, page + 1);
+ chip->write_buf(mtd, (u8 *)info_buf, mtd->writesize);
+
+ if (info->status < 0)
+ return info->status;
+
+ chip->cmdfunc(mtd, SPINAND_CMD_PROG, -1, page + 1);
+ status = chip->waitfunc(mtd, chip);
+ chip->cmdfunc(mtd, SPINAND_CMD_WRDI, -1, -1);
+ if (status & SPINAND_STATUS_PFAIL) {
+ pr_err("%s: error %02x program failed\n",
+ __func__, (u32)status);
+ free(info_buf);
+ return -EIO;
+ }
+ free(info_buf);
+ }
+ #endif
+ return 0;
+}
+
+static int spinand_write_page_hwecc(struct mtd_info *mtd,
+ struct nand_chip *chip, const u8 *buf,
+ int oob_required, int page)
+{
+ return spinand_write_page_raw(mtd, chip, buf, oob_required, page);
+}
+
+static int spinand_write_page(struct mtd_info *mtd,
+ struct nand_chip *chip, u32 offset, int data_len,
+ const u8 *buf, int oob_required,
+ int page, int raw)
+{
+ int status;
+ struct spinand_info *info = mtd_to_spinand(mtd);
+ if (info->pload_cmd == SPINAND_CMD_QUAD_PLOAD &&
+ ((info->id[0] == NAND_MFR_GIGA) ||
+ (info->id[0] == NAND_MFR_MACRONIX) ||
+ (info->id[0] == NAND_MFR_ZETTA)))
+ spinand_set_qeb(mtd, chip);
+ chip->cmdfunc(mtd, SPINAND_CMD_WREN, -1, -1);
+ chip->cmdfunc(mtd, info->pload_cmd, 0x00, page);
+
+ if (unlikely(raw))
+ status = chip->ecc.write_page_raw(mtd, chip, buf,
+ oob_required, page);
+ else
+ status = chip->ecc.write_page(mtd, chip, buf,
+ oob_required, page);
+
+ if (status < 0)
+ return status;
+
+ return 0;
+}
+
+static int spinand_do_write_ops(struct mtd_info *mtd,
+ loff_t to, struct mtd_oob_ops *ops)
+{
+ int realpage, page, column;
+ struct nand_chip *chip = mtd->priv;
+ u32 writelen = ops->len;
+ u32 oobwritelen = ops->ooblen;
+ u32 oobmaxlen =
+ ops->mode == MTD_OPS_AUTO_OOB ? mtd->oobavail : mtd->oobsize;
+
+ u8 *oob = ops->oobbuf;
+ u8 *buf = ops->datbuf;
+ int ret;
+ int oob_required = oob ? 1 : 0;
+
+ ops->retlen = 0;
+ if (!writelen)
+ return 0;
+
+ /* Reject writes, which are not page aligned */
+ if (NOTALIGNED(to)) {
+ pr_debug("%s: attempt to write non page aligned data\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ column = to & (mtd->writesize - 1);
+ realpage = (int)(to >> chip->page_shift);
+ page = realpage & chip->pagemask;
+
+ /* Invalidate the page cache, when we write to the cached page */
+ if (to <= (chip->pagebuf << chip->page_shift) &&
+ (chip->pagebuf << chip->page_shift) < (to + ops->len))
+ chip->pagebuf = -1;
+
+ /* Don't allow multipage oob writes with offset */
+ if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
+ pr_debug("do not allow multi pages oob writes with offset\n");
+ ret = -EINVAL;
+ goto err_out;
+ }
+
+ while (1) {
+ int bytes = mtd->writesize;
+ u8 *wbuf = buf;
+
+ /* Partial page write? */
+ if (unlikely(column || writelen < (mtd->writesize - 1))) {
+ bytes = min_t(int, bytes - column, (int)writelen);
+ chip->pagebuf = -1;
+ memset(chip->buffers->databuf, 0xff, mtd->writesize);
+ memcpy(&chip->buffers->databuf[column], buf, bytes);
+ wbuf = chip->buffers->databuf;
+ }
+
+ if (unlikely(oob)) {
+ size_t len = min(oobwritelen, oobmaxlen);
+
+ oob = fill_oob(mtd, oob, len, ops);
+ oobwritelen -= len;
+ } else {
+ /* We still need to erase leftover OOB data */
+ memset(chip->oob_poi, 0xff, mtd->oobsize);
+ }
+
+ ret = chip->write_page(mtd, chip, column, bytes, wbuf,
+ oob_required, page,
+ ops->mode ==
+ MTD_OPS_RAW);
+ if (ret)
+ break;
+
+ writelen -= bytes;
+ if (!writelen)
+ break;
+
+ column = 0;
+ buf += bytes;
+ realpage++;
+
+ page = realpage & chip->pagemask;
+ }
+
+ ops->retlen = ops->len - writelen;
+ if (unlikely(oob))
+ ops->oobretlen = ops->ooblen - oobwritelen;
+
+err_out:
+ return ret;
+}
+
+static int spinand_mtd_write(struct mtd_info *mtd, loff_t to, size_t len,
+ size_t *retlen, const u_char *buf)
+{
+ struct mtd_oob_ops ops;
+ int ret;
+
+ pr_debug("%s: to = 0x%08x, len = 0x%04x\n",
+ __func__, (u32)to, (u32)len);
+
+ spinand_get_device(mtd, FL_WRITING);
+ memset(&ops, 0, sizeof(struct mtd_oob_ops));
+ ops.len = len;
+ ops.datbuf = (u8 *)buf;
+ ops.mode = MTD_OPS_PLACE_OOB;
+ ret = spinand_do_write_ops(mtd, to, &ops);
+ *retlen = ops.retlen;
+ spinand_release_device(mtd);
+
+ return ret;
+}
+
+static int spinand_write_oob_raw(struct mtd_info *mtd,
+ struct nand_chip *chip, int page)
+{
+ struct spinand_info *info = mtd_to_spinand(mtd);
+ int status = 0;
+ if (info->pload_cmd == SPINAND_CMD_QUAD_PLOAD &&
+ ((info->id[0] == NAND_MFR_GIGA) ||
+ (info->id[0] == NAND_MFR_MACRONIX) ||
+ (info->id[0] == NAND_MFR_ZETTA)))
+ spinand_set_qeb(mtd, chip);
+ chip->cmdfunc(mtd, SPINAND_CMD_WREN, -1, -1);
+ chip->cmdfunc(mtd, info->pload_cmd, mtd->writesize, -1);
+
+ info->oob_required = 1;
+ chip->write_buf(mtd, NULL, 0);
+
+ chip->cmdfunc(mtd, SPINAND_CMD_PROG, -1, page);
+ status = chip->waitfunc(mtd, chip);
+ chip->cmdfunc(mtd, SPINAND_CMD_WRDI, -1, -1);
+
+ return status & SPINAND_STATUS_PFAIL ? -EIO : 0;
+}
+
+static int spinand_write_oob_std(struct mtd_info *mtd,
+ struct nand_chip *chip, int page)
+{
+ struct spinand_info *info = mtd_to_spinand(mtd);
+ int status = 0;
+ if (info->pload_cmd == SPINAND_CMD_QUAD_PLOAD &&
+ ((info->id[0] == NAND_MFR_GIGA) ||
+ (info->id[0] == NAND_MFR_MACRONIX) ||
+ (info->id[0] == NAND_MFR_ZETTA)))
+ spinand_set_qeb(mtd, chip);
+ chip->cmdfunc(mtd, SPINAND_CMD_WREN, -1, -1);
+ chip->cmdfunc(mtd, info->pload_cmd, mtd->writesize, page);
+
+ info->oob_required = 1;
+ chip->write_buf(mtd, NULL, 0);
+
+ chip->cmdfunc(mtd, SPINAND_CMD_PROG, -1, page);
+ status = chip->waitfunc(mtd, chip);
+ chip->cmdfunc(mtd, SPINAND_CMD_WRDI, -1, -1);
+
+ return status & SPINAND_STATUS_PFAIL ? -EIO : 0;
+}
+
+static int spinand_do_write_oob(struct mtd_info *mtd,
+ loff_t to, struct mtd_oob_ops *ops)
+{
+ int page, status, len;
+ struct nand_chip *chip = mtd->priv;
+
+ if (ops->mode == MTD_OPS_AUTO_OOB)
+ len = chip->ecc.layout->oobavail;
+ else
+ len = mtd->oobsize;
+
+ if (unlikely(ops->ooboffs >= len)) {
+ pr_err("%s: attempt to start write outside oob\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ /* Do not allow write past end of page */
+ if ((ops->ooboffs + ops->ooblen) > len) {
+ pr_err("%s: attempt to write past end of page\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ /* Do not allow write past end of device */
+ if (unlikely(to >= mtd->size ||
+ ops->ooboffs + ops->ooblen >
+ ((mtd->size >> chip->page_shift) -
+ (to >> chip->page_shift)) * len)) {
+ pr_err("%s: attempt to write beyond end of device\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ /* Shift to get page */
+ page = (int)(to >> chip->page_shift);
+
+ /* Invalidate the page cache, if we write to the cached page */
+ if (page == chip->pagebuf)
+ chip->pagebuf = -1;
+
+ fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
+
+ if (ops->mode == MTD_OPS_RAW)
+ status =
+ chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
+ else
+ status =
+ chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
+
+ if (status)
+ return status;
+
+ ops->oobretlen = ops->ooblen;
+ return 0;
+}
+
+static int spinand_mtd_write_oob(struct mtd_info *mtd,
+ loff_t to, struct mtd_oob_ops *ops)
+{
+ int ret = -ENOTSUPP;
+
+ pr_debug("%s: %s, to = 0x%08x, len = 0x%04x, ",
+ __func__, ops->datbuf ? "DATA" : "NULL",
+ (u32)to, (u32)ops->len);
+ pr_debug("ooboffs = 0x%04x, ooblen = 0x%02x\n",
+ (u32)ops->ooboffs, (int)ops->ooblen);
+
+ ops->retlen = 0;
+ ops->oobretlen = 0;
+
+ /* Do not allow writes past end of device */
+ if (ops->datbuf && (to + ops->len) > mtd->size) {
+ pr_err("%s: attempt to write beyond end of device\n",
+ __func__);
+ return -EINVAL;
+ }
+
+ switch (ops->mode) {
+ case MTD_OPS_PLACE_OOB:
+ case MTD_OPS_AUTO_OOB:
+ case MTD_OPS_RAW:
+ break;
+ default:
+ goto out;
+ }
+
+ if (ops->datbuf)
+ ret = spinand_do_write_ops(mtd, to, ops);
+ else
+ ret = spinand_do_write_oob(mtd, to, ops);
+
+out:
+ return ret;
+}
+
+static void spinand_mtd_sync(struct mtd_info *mtd)
+{
+ pr_debug("%s: called\n", __func__);
+
+ /* Grab the lock and see if the device is available */
+ spinand_get_device(mtd, FL_SYNCING);
+ /* Release it and go back */
+ spinand_release_device(mtd);
+}
+
+static int spinand_block_bad(struct mtd_info *mtd, loff_t offs)
+{
+ struct nand_chip *chip = mtd->priv;
+ struct spinand_info *info = mtd_to_spinand(mtd);
+ int page, res = 0, i = 0;
+ u8 bad;
+
+ if (info->bbt && !info->bbt_scan)
+ return info->bbt[offs >> chip->phys_erase_shift];
+ if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
+ offs += mtd->erasesize - mtd->writesize;
+
+ page = (int)(offs >> chip->page_shift) & chip->pagemask;
+
+ spinand_get_device(mtd, FL_READING);
+
+ do {
+ chip->cmdfunc(mtd, SPINAND_CMD_READ, -1, page);
+ chip->waitfunc(mtd, chip);
+ if (info->read_cmd == SPINAND_CMD_QUAD_READ &&
+ ((info->id[0] == NAND_MFR_GIGA) ||
+ (info->id[0] == NAND_MFR_MACRONIX) ||
+ (info->id[0] == NAND_MFR_ZETTA)))
+ spinand_set_qeb(mtd, chip);
+ chip->cmdfunc(mtd, info->read_cmd,
+ mtd->writesize + chip->badblockpos, page);
+ bad = chip->read_byte(mtd);
+
+ if (likely(chip->badblockbits == 8))
+ res = bad != 0xFF;
+
+ offs += mtd->writesize;
+ page = (int)(offs >> chip->page_shift) & chip->pagemask;
+ i++;
+ } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
+
+ spinand_release_device(mtd);
+
+ return res;
+}
+
+static int block_checkbad(struct mtd_info *mtd, loff_t offs,
+ int getchip, int allowbbt)
+{
+ struct nand_chip *chip = mtd->priv;
+
+ if (!chip->bbt)
+ return chip->block_bad(mtd, offs);
+
+ /* Return info from the table */
+ return nand_isbad_bbt(mtd, offs, allowbbt);
+}
+
+static int spinand_mtd_block_isbad(struct mtd_info *mtd, loff_t offs)
+{
+ int res;
+
+ res = block_checkbad(mtd, offs, 1, 0);
+
+ pr_debug("%s: offs = 0x%08x, res = %x\t%s\n",
+ __func__, (u32)offs, res, res ? "BAD" : "GOOD");
+
+ return res;
+}
+
+static int spinand_block_markbad(struct mtd_info *mtd, loff_t offs)
+{
+ struct nand_chip *chip = mtd->priv;
+ u8 buf[2] = { 0, 0 };
+ int block, res, ret = 0, i = 0;
+ int write_oob = !(chip->bbt_options & NAND_BBT_NO_OOB_BBM);
+
+ if (write_oob) {
+ struct erase_info einfo;
+
+ /* Attempt erase before marking OOB */
+ memset(&einfo, 0, sizeof(einfo));
+ einfo.mtd = mtd;
+ einfo.addr = offs;
+ einfo.len = 1 << chip->phys_erase_shift;
+ erase_nand(mtd, &einfo, 0);
+ }
+
+ /* Get block number */
+ block = (int)(offs >> chip->bbt_erase_shift);
+ /* Mark block bad in memory-based BBT */
+ if (chip->bbt)
+ chip->bbt[block >> 2] |= 0x01 << ((block & 0x03) << 1);
+
+ /* Write bad block marker to OOB */
+ if (write_oob) {
+ struct mtd_oob_ops ops;
+ loff_t wr_offs = offs;
+
+ spinand_get_device(mtd, FL_WRITING);
+
+ ops.datbuf = NULL;
+ ops.oobbuf = buf;
+ ops.ooboffs = chip->badblockpos;
+ ops.ooblen = 1;
+ ops.len = ops.ooblen;
+ ops.mode = MTD_OPS_PLACE_OOB;
+
+ /* Write to first/last page(s) if necessary */
+ if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
+ wr_offs += mtd->erasesize - mtd->writesize;
+ do {
+ res = spinand_do_write_oob(mtd, wr_offs, &ops);
+ if (!ret)
+ ret = res;
+
+ i++;
+ wr_offs += mtd->writesize;
+ } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
+ spinand_release_device(mtd);
+ }
+
+ /* Update flash-based bad block table */
+ if (chip->bbt_options & NAND_BBT_USE_FLASH) {
+ res = nand_markbad_bbt(mtd, offs);
+ if (!ret)
+ ret = res;
+ }
+
+ if (!ret)
+ mtd->ecc_stats.badblocks++;
+
+ return ret;
+}
+
+static int spinand_scan_bbt(struct mtd_info *mtd)
+{
+ struct spinand_info *info = mtd_to_spinand(mtd);
+ loff_t offset = 0;
+ u64 block_cnt = mtd->size >> mtd->erasesize_shift;
+ int i = 0, ret = 0;
+
+ info->bbt_scan = 1;
+ memset(info->bbt, 0, block_cnt);
+ for (i = 0; i < block_cnt; i++) {
+ offset = i * mtd->erasesize;
+ ret = spinand_block_bad(mtd, offset);
+ if (ret) {
+ pr_debug("%s %d detected a bad block at 0x%llx\n",
+ __func__, __LINE__, offset);
+ info->bbt[i] = 0x02;
+ }
+ }
+ info->bbt_scan = 0;
+ return 0;
+}
+
+static int spinand_mtd_block_markbad(struct mtd_info *mtd, loff_t offs)
+{
+ struct nand_chip *chip = mtd->priv;
+ int ret;
+
+ pr_debug("%s: offs = 0x%08x\n",
+ __func__, (u32)offs);
+
+ ret = spinand_mtd_block_isbad(mtd, offs);
+ if (ret) {
+ /* If it was bad already, return success and do nothing */
+ if (ret > 0)
+ return 0;
+ return ret;
+ }
+
+ return chip->block_markbad(mtd, offs);
+}
+
+static int spinand_get_feature(struct mtd_info *mtd,
+ struct nand_chip *chip,
+ int addr, u8 *subfeature_param)
+{
+ struct spinand_info *info = mtd_to_spinand(mtd);
+
+ /* clear the sub feature parameters */
+ memset(subfeature_param, 0, SPINAND_SUBFEATURE_LEN);
+
+ chip->cmdfunc(mtd, SPINAND_CMD_GETFEA, -1, addr);
+
+ spi_write_then_read(info->pdev, info->cmd, info->cmd_len,
+ subfeature_param, SPINAND_SUBFEATURE_LEN);
+ return 0;
+}
+
+static int spinand_set_feature(struct mtd_info *mtd,
+ struct nand_chip *chip,
+ int addr, u8 *subfeature_param)
+{
+ struct spinand_info *info = mtd_to_spinand(mtd);
+ int status;
+ u8 val = *subfeature_param;
+
+ chip->cmdfunc(mtd, SPINAND_CMD_SETFEA, val, addr);
+ spi_write(info->pdev, info->cmd, info->cmd_len);
+ status = chip->waitfunc(mtd, chip);
+ if (status & NAND_STATUS_FAIL)
+ return -EIO;
+ return 0;
+}
+
+static int spinand_set_qeb(struct mtd_info *mtd, struct nand_chip *chip)
+{
+ u8 feature = 0;
+ int ret;
+
+ ret = spinand_get_feature(mtd, chip, SPINAND_FEATURE_REG, &feature);
+ if (ret)
+ return ret;
+ if (feature & SPINAND_FEATURE_QE) {
+ debug("spiand: QEB is already set\n");
+ } else {
+ feature |= SPINAND_FEATURE_QE;
+ ret = spinand_set_feature(mtd, chip,
+ SPINAND_FEATURE_REG, &feature);
+ }
+ return ret;
+}
+
+static void spinand_set_defaults(struct nand_chip *chip)
+{
+ /* check for proper chip_delay setup, set 20us if not */
+ if (!chip->chip_delay)
+ chip->chip_delay = 50;
+
+ /* check, if a user supplied command function given */
+ if (!chip->cmdfunc)
+ chip->cmdfunc = spinand_cmdfunc;
+ /* check, if a user supplied wait function given */
+ if (!chip->waitfunc)
+ chip->waitfunc = spinand_waitfunc;
+
+ if (!chip->read_byte)
+ chip->read_byte = spinand_read_byte;
+
+ if (!chip->block_bad)
+ chip->block_bad = spinand_block_bad;
+ if (!chip->block_markbad)
+ chip->block_markbad = spinand_block_markbad;
+ if (!chip->write_buf)
+ chip->write_buf = spinand_write_buf;
+ if (!chip->read_buf)
+ chip->read_buf = spinand_read_buf;
+ if (!chip->scan_bbt)
+ chip->scan_bbt = spinand_scan_bbt;
+}
+
+static struct nand_flash_dev *
+spinand_get_flash_type(struct mtd_info *mtd,
+ struct nand_chip *chip,
+ int *maf_id, int *dev_id,
+ struct nand_flash_dev *type)
+{
+ struct spinand_info *info = mtd_to_spinand(mtd);
+ u8 status = 0x00;
+ int maf_idx;
+ u8 id_data[8];
+
+ /**
+ * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
+ * after power-up.
+ */
+ reset_spinand_device(mtd);
+
+ spinand_set_feature(mtd, chip, SPINAND_PROTEC_REG, &status);
+ spinand_get_feature(mtd, chip, SPINAND_PROTEC_REG, &status);
+
+ status = 0x00;
+ spinand_set_feature(mtd, chip, SPINAND_FEATURE_REG, &status);
+ spinand_get_feature(mtd, chip, SPINAND_FEATURE_REG, &status);
+
+ /* Send the command for reading device ID */
+ chip->cmdfunc(mtd, SPINAND_CMD_RDID, 0x00, -1);
+ spi_write_then_read(info->pdev, info->cmd, info->cmd_len, id_data, 2);
+
+ /* Read manufacturer and device IDs */
+ *maf_id = id_data[0];
+ *dev_id = id_data[1];
+ /**
+ * if (*maf_id != MANUFACTURE_ID) {
+ * id_data[1] = id_data[0];
+ * }
+ */
+ switch (id_data[1]) {
+ case DEVICE_ID_A_1G_3V:
+ case DEVICE_ID_A_2G_3V:
+ case DEVICE_ID_A_4G_3V:
+ case DEVICE_ID_A_1G_1V:
+ case DEVICE_ID_A_2G_1V:
+ case DEVICE_ID_A_4G_1V:
+ info->chip_ver = GIGA_SPINAND_CHIP_VER_A;
+ break;
+ case DEVICE_ID_B_1G_1V:
+ case DEVICE_ID_B_2G_1V:
+ case DEVICE_ID_B_1G_3V:
+ case DEVICE_ID_B_2G_3V:
+ info->chip_ver = GIGA_SPINAND_CHIP_VER_B;
+ break;
+ case DEVICE_ID_B_4G_1V:
+ case DEVICE_ID_B_4G_3V:
+ info->chip_ver = GIGA_SPINAND_CHIP_VER_B_LP;
+ break;
+ case DEVICE_ID_C_4G_3V:
+ case DEVICE_ID_C_4G_1V:
+ case DEVICE_ID_C_2G_3V:
+ case DEVICE_ID_C_2G_1V:
+ case DEVICE_ID_C_1G_3V:
+ case DEVICE_ID_C_1G_1V:
+ info->chip_ver = GIGA_SPINAND_CHIP_VER_C;
+ break;
+ default:
+ info->chip_ver = GIGA_SPINAND_CHIP_VER_A;
+ break;
+ }
+ if ((id_data[0] == NAND_MFR_TOSHIBA) || (id_data[0] == NAND_MFR_ZETTA) || (id_data[0] == NAND_MFR_MACRONIX))
+ info->chip_ver = GIGA_SPINAND_CHIP_VER_B;
+
+ if (info->chip_ver == GIGA_SPINAND_CHIP_VER_C) {
+ /* Send the command for reading device ID */
+ info->cmd[0] = SPINAND_CMD_RDID;
+ info->cmd_len = 1;
+ spi_write_then_read(info->pdev,
+ info->cmd, info->cmd_len, id_data, 2);
+ *maf_id = id_data[0];
+ *dev_id = id_data[1];
+ }
+
+ if (!type)
+ type = spi_nand_ids;
+
+ for (; type->name; type++) {
+ if (!strncmp((const char *)type->id,
+ (const char *)id_data,
+ type->id_len)) {
+ mtd->writesize = type->pagesize;
+ mtd->erasesize = type->erasesize;
+ mtd->oobsize = type->oobsize;
+ chip->chipsize = (u64)type->chipsize;
+ //chip->options |= type->options;
+ pr_debug("name=%s, ws=0x%x, es=0x%x, os=0x%x, cs=0x%x\n",
+ type->name, mtd->writesize, mtd->erasesize,
+ mtd->oobsize, type->chipsize);
+ break;
+ }
+ }
+
+ if (!type->name)
+ return ERR_PTR(-ENODEV);
+
+ if (!mtd->name)
+ mtd->name = type->name;
+
+ /* Try to identify manufacturer */
+ for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++)
+ if (nand_manuf_ids[maf_idx].id == *maf_id)
+ break;
+
+ /* nand_decode_bbm_options(mtd, chip, id_data); */
+ chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
+ chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
+
+ /* Calculate the address shift from the page size */
+ chip->page_shift = ffs(mtd->writesize) - 1;
+ /* Convert chipsize to number of pages per chip -1 */
+ chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
+
+ chip->phys_erase_shift = ffs(mtd->erasesize) - 1;
+ chip->bbt_erase_shift = chip->phys_erase_shift;
+ if (chip->chipsize & 0xffffffff) {
+ chip->chip_shift = ffs((unsigned int)chip->chipsize) - 1;
+ } else {
+ chip->chip_shift = ffs((unsigned int)(chip->chipsize >> 32));
+ chip->chip_shift += 32 - 1;
+ }
+
+ chip->badblockbits = 8;
+ chip->erase = spinand_erase_block;
+
+#ifndef __UBOOT__
+ printf("SPI NAND: MFR ID: 0x%02x, Chip ID: 0x%02x (%s %s),",
+ *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
+ chip->onfi_version ? chip->onfi_params.model : type->name);
+ printf(" %dMiB, page size: %d, OOB size: %d\n",
+ (int)(chip->chipsize >> 20), mtd->writesize, mtd->oobsize);
+#else
+ printf("SPI NAND: MFR ID: 0x%02x, Chip ID: 0x%02x (%s %d),",
+ *maf_id, *dev_id, nand_manuf_ids[maf_idx].name,
+ chip->onfi_version);
+ printf(" %dMiB, page size: %d, OOB size: %d\n",
+ (int)(chip->chipsize >> 20), mtd->writesize, mtd->oobsize);
+#endif
+
+ return type;
+}
+
+static int spinand_add_partitions(struct mtd_info *mtd,
+ const struct mtd_partition *parts,
+ int nbparts)
+{
+ int part_num = 0, i = 0;
+ struct mtd_partition *temp, *parts_nm;
+ loff_t off;
+ part_num = nbparts + 2;
+
+ temp = kzalloc(sizeof(*temp) * part_num, GFP_KERNEL);
+ memset(temp, 0, sizeof(*temp) * part_num);
+ temp[0].name = BOOT_LOADER;
+ temp[0].offset = 0;
+ temp[0].size = BOOT_TOTAL_PAGES * mtd->writesize;
+ if (temp[0].size % mtd->erasesize)
+ WARN_ON(1);
+ off = temp[0].size + NAND_RSV_BLOCK_NUM * mtd->erasesize;
+
+ temp[1].name = BOOT_TPL;
+ temp[1].offset = off;
+ temp[1].size = CONFIG_TPL_SIZE_PER_COPY * CONFIG_NAND_TPL_COPY_NUM;
+ if (temp[1].size % mtd->erasesize)
+ WARN_ON(1);
+ parts_nm = &temp[2];
+ off += temp[1].size;
+
+ for (; i < nbparts; i++) {
+ if (!parts[i].name) {
+ pr_err("name can't be null! ");
+ pr_err("please check your %d th partition name!\n",
+ i + 1);
+ return 1;
+ }
+ if ((off + parts[i].size) > mtd->size) {
+ pr_err("%s %d over nand size!\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ parts_nm[i].name = parts[i].name;
+#ifndef CONFIG_NOT_SKIP_BAD_BLOCK
+ loff_t offset = off, end = off + parts[i].size;
+
+ do {
+ if (mtd->_block_isbad(mtd, offset)) {
+ printf("%s %d found bad block in 0x%llx\n",
+ __func__, __LINE__, offset);
+ end += mtd->erasesize;
+ }
+ offset += mtd->erasesize;
+ } while (offset < end && offset < mtd->size);
+ parts_nm[i].size = end - off - parts[i].size;
+#endif/* CONFIG_NOT_SKIP_BAD_BLOCK */
+ parts_nm[i].offset = off;
+ if (parts[i].size % mtd->erasesize) {
+ pr_err("%s %d \"%s\" size auto align to block size\n",
+ __func__, __LINE__, parts[i].name);
+ parts_nm[i].size += parts[i].size % mtd->erasesize;
+ }
+ /* it's ok "+=" here because size has been set to 0 */
+ parts_nm[i].size += parts[i].size;
+ off += parts_nm[i].size;
+ if (i == (nbparts - 1))
+ parts_nm[i].size = mtd->size - off;
+ }
+ return add_mtd_partitions(mtd, temp, part_num);
+}
+
+int spinand_scan_ident(struct mtd_info *mtd, int maxchips,
+ struct nand_flash_dev *table)
+{
+ int maf_id, dev_id;
+ u32 mode = 0;
+ struct nand_chip *chip = mtd->priv;
+ struct spinand_info *info = mtd_to_spinand(mtd);
+ struct nand_flash_dev *type;
+ struct udevice *bus = info->pdev->dev->parent;
+ struct spifc_platdata *plat = dev_get_platdata(bus);
+
+ /* Set the default functions */
+ spinand_set_defaults(chip);
+
+ /* Read the flash type */
+ type = spinand_get_flash_type(mtd, chip, &maf_id, &dev_id, table);
+
+ if (IS_ERR(type)) {
+ if (!(chip->options & NAND_SCAN_SILENT_NODEV))
+ pr_warn("No NAND device found\n");
+ return PTR_ERR(type);
+ }
+
+ if (type->options & SPI_RX_QUAD &&
+ plat->io_num == 4) {
+ info->read_cmd = SPINAND_CMD_QUAD_READ;
+ mode |= SPI_RX_QUAD;
+ } else if (type->options & SPI_RX_DUAL &&
+ plat->io_num >= 2) {
+ info->read_cmd = SPINAND_CMD_DUAL_READ;
+ mode |= SPI_RX_DUAL;
+ } else {
+ info->read_cmd = SPINAND_CMD_NORM_READ;
+ }
+ if (type->options & SPI_TX_QUAD &&
+ plat->io_num == 4) {
+ info->pload_cmd = SPINAND_CMD_QUAD_PLOAD;
+ mode |= SPI_TX_QUAD;
+ } else {
+ info->pload_cmd = SPINAND_CMD_PLOAD;
+ }
+
+ info->pdev->mode = mode;
+ mtd->size = chip->chipsize;
+ info->name = type->name;
+
+ info->planes_per_lun = 1;
+ for (int i=0; i<ARRAY_SIZE(chip_plane_ids); i++)
+ if ((maf_id == chip_plane_ids[i][0]) &&
+ (dev_id == chip_plane_ids[i][1])) {
+ info->planes_per_lun = chip_plane_ids[i][2];
+ break;
+ }
+
+ memset(info->id, 0, NAND_MAX_ID_LEN);
+ memcpy(info->id, type->id, type->id_len);
+ return 0;
+}
+
+int spinand_scan_tail(struct mtd_info *mtd)
+{
+ int i;
+ struct nand_chip *chip = mtd->priv;
+ u8 setfeature = 0x0;
+
+ /* New bad blocks should be marked in OOB, flash-based BBT, or both */
+ WARN_ON(((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
+ !(chip->bbt_options & NAND_BBT_USE_FLASH)));
+
+ /* Set the internal oob buffer location, just after the page data */
+ chip->oob_poi = chip->buffers->databuf + mtd->writesize;
+
+ /* If no default placement scheme is given, select an appropriate one */
+ if (!chip->ecc.layout && chip->ecc.mode != NAND_ECC_SOFT_BCH) {
+ switch (mtd->oobsize) {
+ case 8:
+ chip->ecc.layout = &nand_oob_8;
+ break;
+ case 16:
+ chip->ecc.layout = &nand_oob_16;
+ break;
+ case 64:
+ chip->ecc.layout = &nand_oob_64;
+ break;
+ case 128:
+ chip->ecc.layout = &nand_oob_128;
+ break;
+ default:
+ pr_warn("No oob scheme defined for oobsize %d\n",
+ mtd->oobsize);
+ WARN_ON(1);
+ break;
+ }
+ }
+
+ if (!chip->write_page)
+ chip->write_page = spinand_write_page;
+
+ if (!chip->onfi_set_features)
+ chip->onfi_set_features = spinand_set_feature;
+ if (!chip->onfi_get_features)
+ chip->onfi_get_features = spinand_get_feature;
+ /**
+ * Check ECC mode, default to software if 3byte/512byte hardware ECC is
+ * selected and we have 256 byte pagesize fallback to software ECC
+ */
+
+ switch (chip->ecc.mode) {
+ case NAND_ECC_HW_OOB_FIRST:
+ case NAND_ECC_HW:
+ pr_debug("NAND_ECC_HW selected by board driver.\n");
+ chip->ecc.read_page = spinand_read_page_hwecc;
+ chip->ecc.write_page = spinand_write_page_hwecc;
+ chip->ecc.read_oob = spinand_read_oob_std;
+ chip->ecc.read_page_raw = spinand_read_page_raw;
+ chip->ecc.write_page_raw = spinand_write_page_raw;
+ chip->ecc.write_oob = spinand_write_oob_std;
+ chip->ecc.size = mtd->writesize;
+ chip->ecc.bytes = 0;
+ chip->ecc.strength = 0;
+ setfeature = SPINAND_FEATURE_ECC_EN;
+ spinand_set_feature(mtd, chip,
+ SPINAND_FEATURE_REG, &setfeature);
+ setfeature = 0x00;
+ spinand_get_feature(mtd, chip,
+ SPINAND_FEATURE_REG, &setfeature);
+ break;
+ case NAND_ECC_HW_SYNDROME:
+ case NAND_ECC_SOFT:
+ case NAND_ECC_SOFT_BCH:
+ case NAND_ECC_NONE:
+ pr_debug("NAND_ECC_NONE selected by board driver.");
+ pr_debug("This is not recommended!\n");
+ chip->ecc.read_page = spinand_read_page_raw;
+ chip->ecc.write_page = spinand_write_page_hwecc;
+ chip->ecc.read_oob = spinand_read_oob_std;
+ chip->ecc.read_page_raw = spinand_read_page_raw;
+ chip->ecc.write_page_raw = spinand_write_page_raw;
+ chip->ecc.write_oob = spinand_write_oob_std;
+ chip->ecc.size = mtd->writesize;
+ chip->ecc.bytes = 0;
+ chip->ecc.strength = 0;
+ break;
+
+ default:
+ pr_warn("Invalid NAND_ECC_MODE %d\n", chip->ecc.mode);
+ WARN_ON(1);
+ break;
+ }
+
+ /* For many systems, the standard OOB write also works for raw */
+ if (!chip->ecc.read_oob_raw)
+ chip->ecc.read_oob_raw = spinand_read_oob_std;
+ if (!chip->ecc.write_oob_raw)
+ chip->ecc.write_oob_raw = spinand_write_oob_raw;
+
+ /*
+ * The number of bytes available for a client to place data into
+ * the out of band area.
+ */
+ chip->ecc.layout->oobavail = 0;
+ for (i = 0; chip->ecc.layout->oobfree[i].length &&
+ i < ARRAY_SIZE(chip->ecc.layout->oobfree); i++)
+ chip->ecc.layout->oobavail +=
+ chip->ecc.layout->oobfree[i].length;
+ mtd->oobavail = chip->ecc.layout->oobavail;
+
+ /*
+ * Set the number of read / write steps for one page depending on ECC
+ * mode.
+ */
+ chip->ecc.steps = mtd->writesize / chip->ecc.size;
+ if (chip->ecc.steps * chip->ecc.size != mtd->writesize) {
+ pr_warn("Invalid ECC parameters\n");
+ WARN_ON(1);
+ }
+ chip->ecc.total = chip->ecc.steps * chip->ecc.bytes;
+
+ mtd->subpage_sft = 0;
+ chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
+
+ /* Initialize state */
+ chip->state = FL_READY;
+
+ /* Invalidate the pagebuffer reference */
+ chip->pagebuf = -1;
+
+ /* Large page NAND with SOFT_ECC should support subpage reads */
+ if (chip->ecc.mode == NAND_ECC_SOFT && chip->page_shift > 9)
+ chip->options |= NAND_SUBPAGE_READ;
+
+ /* Fill in remaining MTD driver data */
+ mtd->type = MTD_NANDFLASH;
+ mtd->flags = MTD_CAP_NANDFLASH;
+ mtd->_erase = spinand_mtd_erase;
+ #ifndef __UBOOT__
+ mtd->_point = NULL;
+ mtd->_unpoint = NULL;
+ #endif
+ mtd->_read = spinand_mtd_read;
+ mtd->_write = spinand_mtd_write;
+ mtd->_panic_write = spinand_mtd_write;
+ mtd->_read_oob = spinand_mtd_read_oob;
+ mtd->_write_oob = spinand_mtd_write_oob;
+ mtd->_sync = spinand_mtd_sync;
+ mtd->_lock = NULL;
+ mtd->_unlock = NULL;
+ mtd->_block_isbad = spinand_mtd_block_isbad;
+ mtd->_block_markbad = spinand_mtd_block_markbad;
+ mtd->writebufsize = mtd->writesize;
+
+ /* propagate ecc info to mtd_info */
+ mtd->ecclayout = chip->ecc.layout;
+ mtd->ecc_strength = chip->ecc.strength;
+ /*
+ * Initialize bitflip_threshold to its default prior scan_bbt() call.
+ * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
+ * properly set.
+ */
+ if (!mtd->bitflip_threshold)
+ mtd->bitflip_threshold = mtd->ecc_strength;
+
+ struct spinand_info *info = mtd_to_spinand(mtd);
+
+ if ((info->read_cmd == SPINAND_CMD_QUAD_READ ||
+ info->pload_cmd == SPINAND_CMD_QUAD_PLOAD) &&
+ ((info->id[0] == NAND_MFR_GIGA) ||
+ (info->id[0] == NAND_MFR_MACRONIX) ||
+ (info->id[0] == NAND_MFR_ZETTA)))
+ spinand_set_qeb(mtd, chip);
+
+ /* Check, if we should skip the bad block table scan */
+ /*
+ * if (chip->options & NAND_SKIP_BBTSCAN)
+ * return 0;
+ */
+
+ /* Build bad block table */
+ return 0;
+}
+
+#ifndef __UBOOT__
+#ifdef MODULE
+#define caller_is_module() (1)
+#else
+#define caller_is_module() \
+ is_module_text_address((unsigned long)__builtin_return_address(0))
+#endif
+#endif
+
+int spinand_scan(struct mtd_info *mtd, int maxchips)
+{
+ int ret;
+#ifndef __UBOOT__
+ /* Many callers got this wrong, so check for it for a while... */
+ if (!mtd->owner && caller_is_module()) {
+ pr_crit("%s called with NULL mtd->owner!\n", __func__);
+ WARN_ON();
+ }
+#endif
+
+ ret = spinand_scan_ident(mtd, maxchips, NULL);
+ if (!ret)
+ ret = spinand_scan_tail(mtd);
+ return ret;
+}
+
+#ifdef CONFIG_OF
+static void of_spinand_free_data(struct flash_platform_data *data)
+{
+ kfree(data->parts);
+ kfree(data);
+}
+
+static struct flash_platform_data *
+of_spinand_get_data(struct device *dev)
+{
+ struct flash_platform_data *data = 0;
+ struct device_node *np, *part_np;
+ char *propname;
+ phandle phandle;
+ int err, i;
+
+ data = kzalloc(sizeof(*data), GFP_KERNEL);
+ if (!data)
+ return 0;
+
+ np = dev->of_node;
+ err = of_property_read_u32(np, "nr-parts", &data->nr_parts);
+ if (err || !data->nr_parts) {
+ dev_err(dev, "match nr-parts failed!\n");
+ return 0;
+ }
+
+ data->parts = kzalloc(sizeof(*data->parts) *
+ data->nr_parts, GFP_KERNEL);
+ if (!data->parts)
+ goto get_data_err;
+
+ for (i = 0; i < data->nr_parts; i++) {
+ propname = kaspr_debug(GFP_KERNEL, "nr-part-%d", i);
+ if (of_property_read_u32(np, propname, &phandle)) {
+ dev_err(dev, "match %s failed!\n", propname);
+ goto get_data_err;
+ }
+ part_np = of_find_node_by_phandle(phandle);
+ if (!part_np) {
+ dev_err(dev, "find %s node failed!\n", propname);
+ goto get_data_err;
+ }
+ if (of_property_read_string(part_np, "name",
+ &data->parts[i].name)) {
+ dev_err(dev, "match %s name failed!\n", propname);
+ goto get_data_err;
+ }
+ if (of_property_read_u32(part_np, "offset",
+ (u32 *)&data->parts[i].offset)) {
+ dev_err(dev, "match %s offset failed!\n", propname);
+ goto get_data_err;
+ }
+ if (of_property_read_u32(part_np, "size",
+ (u32 *)&data->parts[i].size)) {
+ dev_err(dev, "match %s size failed!\n", propname);
+ goto get_data_err;
+ }
+ }
+ return data;
+
+get_data_err:
+ of_spinand_free_data(data);
+ return 0;
+}
+#endif
+
+#ifndef __UBOOT__
+static int spinand_probe(struct spi_device *pdev)
+#else
+static int spinand_probe(struct udevice *dev)
+#endif
+{
+#ifdef __UBOOT__
+ struct spi_slave *pdev = dev_get_parent_priv(dev);
+#endif
+ struct mtd_info *mtd;
+ struct spinand_info *info;
+ struct nand_chip *chip;
+ int retval = 0;
+ struct mtd_partition *spinand_partitions;
+ int partition_count;
+#ifndef __UBOOT__
+ struct flash_platform_data *data;
+#ifdef CONFIG_OF
+
+ data = of_spinand_get_data(&pdev->dev);
+ pdev->dev.platform_data = data;
+#else
+ data = pdev->dev.platform_data;
+#endif
+ if (!data) {
+ dev_err(&pdev->dev, "no platform data or alloc failed!\n");
+ return -ENODEV;
+ }
+#endif
+ struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
+
+ info = dev_get_priv(dev);
+ if (plat) {
+ pdev->max_hz = plat->max_hz;
+ pdev->mode = plat->mode;
+ }
+
+ memset(info->cmd, 0, MAX_CMD_SIZE);
+
+ info->chip.buffers = kmalloc(sizeof(*info->chip.buffers), GFP_KERNEL);
+ if (!info->chip.buffers) {
+ retval = -ENOMEM;
+ goto exit_error2;
+ }
+
+ dev_set_drvdata(&pdev->dev, info);
+
+ spin_lock_init(&info->controller.lock);
+ init_waitqueue_head(&info->controller.wq);
+
+ info->pdev = pdev;
+ chip = &info->chip;
+ mtd = &chip->mtd;
+ chip->priv = info;
+ mtd->priv = chip;
+
+ chip->controller = &info->controller;
+ chip->IO_ADDR_W = NULL;
+ chip->cmd_ctrl = NULL;
+ chip->dev_ready = NULL;
+ chip->IO_ADDR_R = chip->IO_ADDR_W;
+
+ chip->options = 0;
+ chip->ecc.mode = NAND_ECC_HW;
+ chip->ecc.calculate = nand_calculate_ecc;
+ chip->ecc.correct = nand_correct_data;
+ chip->ecc.hwctl = NULL;
+
+ /* initialise mtd info data struct */
+ mtd->owner = THIS_MODULE;
+ mtd->name = "spi-nand";
+#ifndef __UBOOT__
+ mtd->dev.parent = &pdev->dev;
+ pdev->max_speed_hz = 3000000;
+#elif defined CONFIG_DM_SPI
+ retval = spi_claim_bus(pdev);
+ if (retval) {
+ pr_debug("%s: Failed to claim SPI bus\n", __func__);
+ goto exit_error3;
+ }
+#endif
+ if (spinand_scan(mtd, 1)) {
+ retval = -ENXIO;
+ goto exit_error3;
+ }
+
+ /**
+ * Warning: This is a copy. Don't get spinand_info by
+ * container_of(mtd, struct spinand_info, mtd) but
+ * container_of(mtd->priv, struct spinand_info, chip)
+ */
+ if (is_power_of_2(mtd->erasesize))
+ mtd->erasesize_shift = ffs(mtd->erasesize) - 1;
+ else
+ mtd->erasesize_shift = 0;
+
+ if (is_power_of_2(mtd->writesize))
+ mtd->writesize_shift = ffs(mtd->writesize) - 1;
+ else
+ mtd->writesize_shift = 0;
+ info->rsv = kzalloc(sizeof(*info->rsv), GFP_KERNEL);
+ meson_rsv_init(mtd, info->rsv);
+ info->bbt = kzalloc(mtd->size >> mtd->erasesize_shift, GFP_KERNEL);
+ if (meson_rsv_check(info->rsv->bbt)) {
+ pr_err("no valid bbt info, scanning!\n");
+ chip->scan_bbt(mtd);/* must read from oob */
+ meson_rsv_save(info->rsv->bbt, info->bbt);
+ } else {
+ pr_err("reading bbt info from %s!\n", mtd->name);
+ meson_rsv_read(info->rsv->bbt, info->bbt);
+ }
+#ifndef CONFIG_ENV_IS_IN_NAND
+ meson_rsv_check(info->rsv->env);
+#endif
+ meson_rsv_check(info->rsv->key);
+ meson_rsv_check(info->rsv->dtb);
+ /*
+ * nand_register must be before add_mtd_partition
+ * because nand_register will init mtd->partitions
+ */
+ nand_register(0, mtd);
+#ifdef __UBOOT__
+ extern struct mtd_partition *get_spinand_partition_table(int *partitions);
+ spinand_partitions = get_spinand_partition_table(&partition_count);
+ WARN_ON(spinand_add_partitions(mtd, spinand_partitions,
+ partition_count));
+#elif defined CONFIG_OF
+ mtd_device_register(mtd, data->parts, data->nr_parts);
+#endif
+#ifdef CONFIG_AML_STORAGE
+ spinand_fit_storage(chip, info->name, info->id);
+#endif
+ printf("%s: max_hz=%d, mode=0x%x, read_cmd=0x%x, pload_cmd=0x%x\n",
+ __func__, pdev->max_hz, pdev->mode,
+ info->read_cmd, info->pload_cmd);
+ return 0;
+
+exit_error3:
+ kfree(info->chip.buffers);
+exit_error2: //kfree(info);
+#ifdef CONFIG_OF
+ of_spinand_free_data(data);
+#endif
+ return retval;
+}
+
+void board_nand_init(void)
+{
+ u32 bus = SPIFC_BUS_NUM, cs = SPIFC_SNAND_CS, speed = 0, mode = 0;
+ struct spi_slave *slave;
+ struct udevice *dev;
+ int ret;
+
+ ret = spi_get_bus_and_cs(bus, cs, speed, mode,
+ NULL, NULL, &dev, &slave);
+ if (ret)
+ printf("%s %d probe spi nand fail!\n",
+ __func__, __LINE__);
+}
+
+#ifdef CONFIG_OF_CONTROL
+static int spinand_ofdata_to_platdata(struct udevice *dev)
+{
+ struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
+ struct udevice *bus = dev_get_parent(dev);
+ struct spifc_platdata *data = dev_get_platdata(bus);
+
+ plat->max_hz = data->speed;
+ plat->mode = data->mode;
+
+ return 0;
+}
+
+static const struct udevice_id spinand_ids[] = {
+ { .compatible = "spi-nand" },
+ { }
+};
+#endif
+
+static int spinand_bind(struct udevice *dev)
+{
+ struct dm_spi_slave_platdata *plat = dev_get_parent_platdata(dev);
+
+ plat->cs = SPIFC_SNAND_CS;
+ return 0;
+}
+
+U_BOOT_DRIVER(spinand) = {
+ .name = SPINAND_DRV_NAME,
+ .id = UCLASS_SPI_GENERIC,
+#ifdef CONFIG_OF_CONTROL
+ .of_match = spinand_ids,
+ .ofdata_to_platdata = spinand_ofdata_to_platdata,
+ //.platdata_auto_alloc_size = sizeof(struct spinand_platdata),
+#endif
+ .priv_auto_alloc_size = sizeof(struct spinand_info),
+ .bind = spinand_bind,
+ .probe = spinand_probe,
+};
diff --git a/drivers/mtd/nand/spi-nand/storage_sn.c b/drivers/mtd/nand/spi-nand/storage_sn.c
new file mode 100644
index 0000000..265e0a2
--- /dev/null
+++ b/drivers/mtd/nand/spi-nand/storage_sn.c
@@ -0,0 +1,87 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spi.h>
+#include <nand.h>
+#include <dm/device-internal.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
+#include <amlogic/storage.h>
+#include <amlogic/aml_mtd.h>
+
+static struct storage_t *snand_storage;
+extern void mtd_store_set(struct mtd_info *mtd, int dev);
+extern void mtd_store_mount_ops(struct storage_t *store);
+
+static inline void set_snand_storage(struct storage_t *snand)
+{
+ snand_storage = snand;
+}
+
+static inline struct storage_t *get_snand_storage(void)
+{
+ return snand_storage;
+}
+
+int spinand_fit_storage(struct nand_chip *chip, char *name, u8 *id)
+{
+ struct storage_t *spi_nand = NULL;
+ struct mtd_info *mtd = &chip->mtd;
+ int ret = 0;
+
+ if (get_snand_storage())
+ return 0;
+ spi_nand = kzalloc(sizeof(*spi_nand), GFP_KERNEL);
+ if (!spi_nand) {
+ debug("%s %d no enough memory!\n", __func__, __LINE__);
+ return -ENOMEM;
+ }
+ spi_nand->type = BOOT_SNAND;
+ spi_nand->init_flag = 0;
+ /* TODO:set name and id parameter */
+ memcpy(spi_nand->info.name,
+ name, strlen(name) > 32 ? 32 : strlen(name));
+ memcpy(spi_nand->info.id, id, NAND_MAX_ID_LEN);
+ spi_nand->info.read_unit = mtd->writesize;
+ spi_nand->info.write_unit = mtd->writesize;
+ spi_nand->info.erase_unit = mtd->erasesize;
+ spi_nand->info.caps = mtd->size;
+ spi_nand->info.mode = 1;
+
+ set_snand_storage(spi_nand);
+ mtd_store_mount_ops(spi_nand);
+ ret = store_register(spi_nand);
+ if (ret)
+ return ret;
+ mtd_store_set(mtd, 0);
+ return ret;
+}
+
+int spi_nand_pre(void)
+{
+ return 0;
+}
+
+int spi_nand_probe(u32 init_flag)
+{
+ struct storage_t *spi_nand = get_snand_storage();
+
+ if (spi_nand) {
+ spi_nand->init_flag = init_flag;
+ return 0;
+ }
+
+ board_nand_init();
+ spi_nand = get_snand_storage();
+ if (!spi_nand) {
+ printf("%s %d can not get spi nand!\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ spi_nand->init_flag = init_flag;
+ return 0;
+}
diff --git a/drivers/mtd/nand/spi/Kconfig b/drivers/mtd/nand/spi/Kconfig
index 52960b6..e2c9090 100644
--- a/drivers/mtd/nand/spi/Kconfig
+++ b/drivers/mtd/nand/spi/Kconfig
@@ -6,3 +6,13 @@
help
This is the framework for the SPI NAND device drivers.
+config SPI_NAND_AML_ADVANCED
+ bool "SPI Nand meson advanced support"
+ depends on MTD_SPI_NAND
+ default n
+ help
+ SC2 needs to support a new burning mode (ADVANCED), we implement
+ it based on the original discrete modem. If say Y enabled ADVANCED
+ mode, spinand will use ADVANCED mode to burning.
+ If unsure, say N
+
diff --git a/drivers/mtd/nand/spi/Makefile b/drivers/mtd/nand/spi/Makefile
index dd6baca..59b046d 100644
--- a/drivers/mtd/nand/spi/Makefile
+++ b/drivers/mtd/nand/spi/Makefile
@@ -1,4 +1,4 @@
# SPDX-License-Identifier: GPL-2.0
-spinand-objs := core.o gigadevice.o macronix.o micron.o winbond.o
+spinand-objs := core.o gigadevice.o macronix.o micron.o winbond.o toshiba.o zetta.o xtx.o storage_sn.o
obj-$(CONFIG_MTD_SPI_NAND) += spinand.o
diff --git a/drivers/mtd/nand/spi/core.c b/drivers/mtd/nand/spi/core.c
index cb8ffa3..72f1814 100644
--- a/drivers/mtd/nand/spi/core.c
+++ b/drivers/mtd/nand/spi/core.c
@@ -25,10 +25,21 @@
#include <spi.h>
#include <spi-mem.h>
#include <linux/mtd/spinand.h>
+#include <linux/mtd/partitions.h>
+#include <spi.h>
+#include <amlogic/aml_rsv.h>
+#include <amlogic/aml_mtd.h>
+#include <linux/log2.h>
+#include <asm/arch/cpu_config.h>
+#include <amlogic/storage.h>
+#include <amlogic/cpu_id.h>
#endif
/* SPI NAND index visible in MTD names */
static int spi_nand_idx;
+#ifdef CONFIG_AML_STORAGE
+extern int spinand_fit_storage(struct mtd_info *info, char *name, u8 *id);
+#endif
static void spinand_cache_op_adjust_colum(struct spinand_device *spinand,
const struct nand_page_io_req *req,
@@ -207,6 +218,7 @@
spinand->op_templates.update_cache->data.buswidth == 4)
enable = true;
+ printf("spinand qe is %s\n",enable ? "enable" : "disabled");
return spinand_upd_cfg(spinand, CFG_QUAD_ENABLE,
enable ? CFG_QUAD_ENABLE : 0);
}
@@ -450,12 +462,17 @@
{
struct spi_mem_op op = SPINAND_READID_OP(0, spinand->scratchbuf,
SPINAND_MAX_ID_LEN);
- int ret;
+ int ret, i;
ret = spi_mem_exec_op(spinand->slave, &op);
if (!ret)
memcpy(buf, spinand->scratchbuf, SPINAND_MAX_ID_LEN);
+ /* Success or failure print id */
+ printf("spinand id detect\n");
+ for (i = 0; i < SPINAND_MAX_ID_LEN; i++)
+ printf("id[%d] = 0x%x\n",i,spinand->id.data[i]);
+
return ret;
}
@@ -608,6 +625,72 @@
return ret ? ret : max_bitflips;
}
+/* add for meson info_page */
+#if SPINAND_MESON_INFO_PAGE
+bool spinand_is_info_page(struct nand_device *nand, int page)
+{
+ return unlikely((page % 128) == ((BL2_SIZE / 2048) - 1) &&
+ page < BOOT_TOTAL_PAGES);
+}
+
+int spinand_set_info_page(struct mtd_info *mtd, void *buf)
+{
+ u32 page_per_blk;
+ struct mtd_oob_region region;
+ struct nand_device* dev = mtd_to_nanddev(mtd);
+ struct info_page *info_page = (struct info_page *)buf;
+
+ page_per_blk = mtd->erasesize / mtd->writesize;
+ memcpy(info_page->magic, SPINAND_MAGIC, strlen(SPINAND_MAGIC));
+ info_page->version = SPINAND_INFO_VER;
+ /* DISCRETE only */
+ info_page->mode = 1;
+ info_page->bl2_num = CONFIG_BL2_COPY_NUM;
+ info_page->fip_num = CONFIG_NAND_TPL_COPY_NUM;
+ info_page->dev.s.rd_max = 2;
+ info_page->dev.s.fip_start =
+ BOOT_TOTAL_PAGES + NAND_RSV_BLOCK_NUM * page_per_blk;
+ info_page->dev.s.fip_pages = CONFIG_TPL_SIZE_PER_COPY / mtd->writesize;
+ info_page->dev.s.page_size = mtd->writesize;
+ info_page->dev.s.page_per_blk = page_per_blk;
+ info_page->dev.s.oob_size = mtd->oobsize;
+ mtd->ooblayout->free(mtd, 0, ®ion);
+ info_page->dev.s.oob_offset = region.offset;
+ info_page->dev.s.bbt_start = 0;
+ info_page->dev.s.bbt_valid = 0;
+ info_page->dev.s.bbt_size = 0;
+ info_page->dev.s.planes_per_lun = dev->memorg.planes_per_lun;
+
+ return 0;
+}
+
+static int spinand_append_info_page(struct mtd_info *mtd,
+ struct nand_page_io_req *last_req)
+{
+ struct spinand_device *spinand = mtd_to_spinand(mtd);
+ struct nand_device *nand = mtd_to_nanddev(mtd);
+ struct nand_page_io_req req;
+ int page;
+ u8 *buf;
+ int ret = 0;
+
+ page = nanddev_pos_to_row(nand, &last_req->pos);
+ if (spinand_is_info_page(nand, page)) {
+ req = *last_req;
+ req.datalen = mtd->writesize;
+ req.dataoffs = 0;
+ req.ooblen = 0;
+ buf = kzalloc(mtd->writesize, GFP_KERNEL);
+ req.databuf.in = buf;
+ spinand_set_info_page(mtd, buf);
+ nanddev_pos_next_page(nand, &req.pos);
+ ret = spinand_write_page(spinand, &req);
+ kfree(buf);
+ pr_info("%s: %d\n", __func__, page);
+ }
+ return ret;
+}
+#endif
static int spinand_mtd_write(struct mtd_info *mtd, loff_t to,
struct mtd_oob_ops *ops)
{
@@ -637,6 +720,12 @@
if (ret)
break;
+ /* add for meson info page */
+ #if SPINAND_MESON_INFO_PAGE
+ ret = spinand_append_info_page(mtd, &iter.req);
+ if (ret)
+ break;
+ #endif
ops->retlen += iter.req.datalen;
ops->oobretlen += iter.req.ooblen;
}
@@ -747,8 +836,18 @@
{
struct spinand_device *spinand = nand_to_spinand(nand);
u8 status;
- int ret;
+ int ret = 0;
+#if SPINAND_MESON_RSV
+ unsigned int block = nanddev_pos_to_offs(nand, pos) /
+ (nand->memorg.pages_per_eraseblock * nand->memorg.pagesize);
+
+ /* meson rsv protect */
+ if (meson_rsv_erase_protect(spinand->rsv, block)) {
+ pr_err("blk 0x%x is protected\n", block);
+ return ret;
+ }
+#endif
ret = spinand_select_target(spinand, pos->target);
if (ret)
return ret;
@@ -831,9 +930,12 @@
static const struct spinand_manufacturer *spinand_manufacturers[] = {
&gigadevice_spinand_manufacturer,
+ &toshiba_spinand_manufacturer,
¯onix_spinand_manufacturer,
µn_spinand_manufacturer,
&winbond_spinand_manufacturer,
+ &zetta_spinand_manufacturer,
+ &xtx_spinand_manufacturer,
};
static int spinand_manufacturer_detect(struct spinand_device *spinand)
@@ -937,6 +1039,8 @@
spinand->eccinfo = table[i].eccinfo;
spinand->flags = table[i].flags;
spinand->select_target = table[i].select_target;
+ /* Record the current spinand */
+ spinand->model = table[i].model;
op = spinand_select_op_variant(spinand,
info->op_variants.read_cache);
@@ -990,12 +1094,12 @@
return -EINVAL;
}
- dev_info(spinand->slave->dev,
- "%s SPI NAND was found.\n", spinand->manufacturer->name);
- dev_info(spinand->slave->dev,
- "%llu MiB, block size: %zu KiB, page size: %zu, OOB size: %u\n",
+ printf("%s %s SPI NAND was found.\n", spinand->manufacturer->name, spinand->model);
+ printf("%llu MiB, block size: %zu KiB, page size: %zu, OOB size: %u\n",
nanddev_size(nand) >> 20, nanddev_eraseblock_size(nand) >> 10,
nanddev_page_size(nand), nanddev_per_page_oobsize(nand));
+ printf("read cmd: 0x%x write cmd: 0x%x\n",spinand->op_templates.read_cache->cmd.opcode,
+ spinand->op_templates.write_cache->cmd.opcode);
return 0;
}
@@ -1138,6 +1242,148 @@
kfree(spinand->scratchbuf);
}
+#ifdef CONFIG_AML_MTDPART
+/* The size of the partition must be block aligned */
+int spinand_add_partitions(struct mtd_info *mtd,
+ const struct mtd_partition *parts,
+ int nbparts)
+{
+ int part_num = 0, i = 0;
+ struct mtd_partition *temp, *parts_nm;
+ loff_t off;
+ cpu_id_t cpu_id = get_cpu_id();
+
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER) {
+ if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2)
+ part_num = nbparts + 5;
+ else
+ part_num = nbparts + 2;
+ } else
+ part_num = nbparts + 1;
+
+ temp = kzalloc(sizeof(*temp) * part_num, GFP_KERNEL);
+ memset(temp, 0, sizeof(*temp) * part_num);
+ temp[0].name = BOOT_LOADER;
+ temp[0].offset = 0;
+ temp[0].size = BOOT_TOTAL_PAGES * mtd->writesize;
+ if (temp[0].size % mtd->erasesize)
+ WARN_ON(1);
+ off = temp[0].size + NAND_RSV_BLOCK_NUM * mtd->erasesize;
+
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER) {
+ if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) {
+ extern struct storage_startup_parameter g_ssp;
+ temp[BOOT_AREA_BL2E].name = BOOT_BL2E;
+ temp[BOOT_AREA_BL2E].offset =
+ g_ssp.boot_entry[BOOT_AREA_BL2E].offset;
+ temp[BOOT_AREA_BL2E].size =
+ g_ssp.boot_entry[BOOT_AREA_BL2E].size * g_ssp.boot_bakups;
+ if (temp[0].size % mtd->erasesize)
+ WARN_ON(1);
+
+ temp[BOOT_AREA_BL2X].name = BOOT_BL2X;
+ temp[BOOT_AREA_BL2X].offset =
+ g_ssp.boot_entry[BOOT_AREA_BL2X].offset;
+ temp[BOOT_AREA_BL2X].size =
+ g_ssp.boot_entry[BOOT_AREA_BL2X].size * g_ssp.boot_bakups;
+ if (temp[0].size % mtd->erasesize)
+ WARN_ON(1);
+
+ temp[BOOT_AREA_DDRFIP].name = BOOT_DDRFIP;
+ temp[BOOT_AREA_DDRFIP].offset =
+ g_ssp.boot_entry[BOOT_AREA_DDRFIP].offset;
+ temp[BOOT_AREA_DDRFIP].size =
+ g_ssp.boot_entry[BOOT_AREA_DDRFIP].size * g_ssp.boot_bakups;
+ if (temp[0].size % mtd->erasesize)
+ WARN_ON(1);
+
+ temp[BOOT_AREA_DEVFIP].name = BOOT_DEVFIP;
+ temp[BOOT_AREA_DEVFIP].offset =
+ g_ssp.boot_entry[BOOT_AREA_DEVFIP].offset;
+ temp[BOOT_AREA_DEVFIP].size =
+ g_ssp.boot_entry[BOOT_AREA_DEVFIP].size * CONFIG_NAND_TPL_COPY_NUM;
+ if (temp[0].size % mtd->erasesize)
+ WARN_ON(1);
+ off = temp[BOOT_AREA_DEVFIP].offset + temp[BOOT_AREA_DEVFIP].size;
+ parts_nm = &temp[5];
+ } else {
+ temp[1].name = BOOT_TPL;
+ temp[1].offset = off;
+ temp[1].size = CONFIG_TPL_SIZE_PER_COPY * CONFIG_NAND_TPL_COPY_NUM;
+ if (temp[1].size % mtd->erasesize)
+ WARN_ON(1);
+ parts_nm = &temp[2];
+ off += temp[1].size;
+ }
+ } else
+ parts_nm = &temp[1];
+
+ for (; i < nbparts; i++) {
+ //printf("add_partitions ==== name = %s\n",parts[i].name);
+ if (!parts[i].name) {
+ pr_err("name can't be null! ");
+ pr_err("please check your %d th partition name!\n",
+ i + 1);
+ return 1;
+ }
+ if ((off + parts[i].size) > mtd->size) {
+ pr_err("%s %d over nand size!\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ parts_nm[i].name = parts[i].name;
+#ifndef CONFIG_NOT_SKIP_BAD_BLOCK
+ loff_t offset = off, end = off + parts[i].size;
+
+ do {
+ if (mtd->_block_isbad(mtd, offset)) {
+ pr_err("%s %d found bad block in 0x%llx\n",
+ __func__, __LINE__, offset);
+ end += mtd->erasesize;
+ }
+ offset += mtd->erasesize;
+ } while (offset < end && offset < mtd->size);
+ parts_nm[i].size = end - off - parts[i].size;
+#endif/* CONFIG_NOT_SKIP_BAD_BLOCK */
+ parts_nm[i].offset = off;
+ if (parts[i].size % mtd->erasesize) {
+ pr_err("%s %d \"%s\" size auto align to block size\n",
+ __func__, __LINE__, parts[i].name);
+ parts_nm[i].size += parts[i].size % mtd->erasesize;
+ }
+ /* it's ok "+=" here because size has been set to 0 */
+ parts_nm[i].size += parts[i].size;
+ off += parts_nm[i].size;
+ if (i == (nbparts - 1))
+ parts_nm[i].size = mtd->size - off;
+ }
+ return add_mtd_partitions(mtd, temp, part_num);
+}
+#endif
+
+#if SPINAND_MESON_RSV /* add for meson rsv */
+static int spinand_scan_bbt(struct spinand_device *spinand, struct mtd_info *mtd)
+{
+ loff_t offset = 0;
+ u64 block_cnt = mtd->size >> mtd->erasesize_shift;
+ int i = 0, ret = 0;
+
+ spinand->bbt_scan = 1;
+ memset(spinand->bbt, 0, block_cnt);
+ for (i = 0; i < block_cnt; i++) {
+ offset = i * mtd->erasesize;
+ ret = mtd->_block_isbad(mtd, offset);
+ if (ret) {
+ pr_err("%s %d detected a bad block at 0x%llx\n",
+ __func__, __LINE__, offset);
+ spinand->bbt[i] = NAND_FACTORY_BAD;
+ }
+ }
+ spinand->bbt_scan = 0;
+ return 0;
+}
+#endif
+
static int spinand_probe(struct udevice *dev)
{
struct spinand_device *spinand = dev_get_priv(dev);
@@ -1177,13 +1423,45 @@
#ifndef __UBOOT__
ret = mtd_device_register(mtd, NULL, 0);
-#else
- ret = add_mtd_device(mtd);
+/*#else
+ ret = add_mtd_device(mtd);*/
#endif
if (ret)
goto err_spinand_cleanup;
- return 0;
+#ifdef CONFIG_AML_STORAGE
+ ret = spinand_fit_storage(mtd, mtd->name, spinand->id.data);
+#endif
+
+#if SPINAND_MESON_RSV /* add for meson rsv management */
+ if (is_power_of_2(mtd->erasesize))
+ mtd->erasesize_shift = ffs(mtd->erasesize) - 1;
+ else
+ mtd->erasesize_shift = 0;
+
+ if (is_power_of_2(mtd->writesize))
+ mtd->writesize_shift = ffs(mtd->writesize) - 1;
+ else
+ mtd->writesize_shift = 0;
+
+ spinand->rsv = kzalloc(sizeof(*spinand->rsv), GFP_KERNEL);
+ meson_rsv_init(mtd, spinand->rsv);
+ spinand->bbt = kzalloc(mtd->size >> mtd->erasesize_shift, GFP_KERNEL);
+ if (meson_rsv_check(spinand->rsv->bbt)) {
+ pr_err("no valid bbt info, scanning!\n");
+ spinand_scan_bbt(spinand, mtd);
+ meson_rsv_save(spinand->rsv->bbt, spinand->bbt);
+ } else {
+ pr_err("reading bbt info from %s!\n", mtd->name);
+ meson_rsv_read(spinand->rsv->bbt, spinand->bbt);
+ }
+
+ meson_rsv_check(spinand->rsv->env);
+ meson_rsv_check(spinand->rsv->key);
+ meson_rsv_check(spinand->rsv->dtb);
+#endif
+
+ return ret;
err_spinand_cleanup:
spinand_cleanup(spinand);
diff --git a/drivers/mtd/nand/spi/gigadevice.c b/drivers/mtd/nand/spi/gigadevice.c
index 0bade20..d1b3221 100644
--- a/drivers/mtd/nand/spi/gigadevice.c
+++ b/drivers/mtd/nand/spi/gigadevice.c
@@ -20,9 +20,9 @@
#define GIGADEVICE_STATUS_ECC_8_BITFLIPS (3 << 4)
static SPINAND_OP_VARIANTS(read_cache_variants,
- SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+ //SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
- SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ //SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
@@ -91,14 +91,90 @@
return -EINVAL;
}
+static int gd5f4gq4u_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ region->offset = 128;
+ region->length = 128;
+
+ return 0;
+}
+
+static int gd5f4gq4u_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ /* Reserve 2 bytes for the BBM. */
+ region->offset = 2;
+ region->length = 126;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops gd5f4gq4u_ooblayout = {
+ .ecc = gd5f4gq4u_ooblayout_ecc,
+ .free = gd5f4gq4u_ooblayout_free,
+};
+
+static int gd5f4gq4u_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ if (status)
+ debug("%s (%d): status=%02x\n", __func__, __LINE__, status);
+
+ switch (status & GIGADEVICE_STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case GIGADEVICE_STATUS_ECC_1TO7_BITFLIPS:
+ return 7;
+
+ case GIGADEVICE_STATUS_ECC_8_BITFLIPS:
+ return 8;
+
+ case STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
static const struct spinand_info gigadevice_spinand_table[] = {
- SPINAND_INFO("GD5F1GQ4UC", 0xd1,
+ SPINAND_INFO("GD5F1GQ4UB 3.3v", 0xd1,
NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
- NAND_ECCREQ(8, 2048),
+ NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
- 0,
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5f1gq4u_ooblayout,
+ gd5f1gq4u_ecc_get_status)),
+
+ SPINAND_INFO("GD5F4GQ4UB 3.3v", 0xd4,
+ NAND_MEMORG(1, 4096, 256, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&gd5f4gq4u_ooblayout,
+ gd5f4gq4u_ecc_get_status)),
+
+ SPINAND_INFO("GD5F2GQ5UE 3.3v", 0x52,
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&gd5f1gq4u_ooblayout,
gd5f1gq4u_ecc_get_status)),
};
@@ -108,16 +184,12 @@
u8 *id = spinand->id.data;
int ret;
- /*
- * Gigadevice SPI NAND read ID need a dummy byte,
- * so the first byte in raw_id is dummy.
- */
- if (id[1] != SPINAND_MFR_GIGADEVICE)
+ if (id[0] != SPINAND_MFR_GIGADEVICE)
return 0;
ret = spinand_match_and_init(spinand, gigadevice_spinand_table,
ARRAY_SIZE(gigadevice_spinand_table),
- id[2]);
+ id[1]);
if (ret)
return ret;
diff --git a/drivers/mtd/nand/spi/macronix.c b/drivers/mtd/nand/spi/macronix.c
index 662c561..8f60dea 100644
--- a/drivers/mtd/nand/spi/macronix.c
+++ b/drivers/mtd/nand/spi/macronix.c
@@ -12,6 +12,9 @@
#include <linux/mtd/spinand.h>
#define SPINAND_MFR_MACRONIX 0xC2
+/* Read ECCSR (7Ch) command for ECC Status Read */
+#define MACRONIX_CURRENT_ECCSR_MASK 0x0F
+#define MACRONIX_ACCUMULATE_ECCSR_MASK (0x0F << 4);
static SPINAND_OP_VARIANTS(read_cache_variants,
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
@@ -36,20 +39,68 @@
static int mx35lfxge4ab_ooblayout_free(struct mtd_info *mtd, int section,
struct mtd_oob_region *region)
{
- if (section)
+ if (section > 3)
return -ERANGE;
- region->offset = 2;
- region->length = mtd->oobsize - 2;
+ region->offset = (16 * section) + 2;
+ region->length = 14;
return 0;
}
+static int MX35LF2GE4AD_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ return -ERANGE;
+}
+
+static int MX35LF2GE4AD_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 3)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 2;
+ region->length = 14;
+
+ return 0;
+}
+#if 0
+static int MX35LF4GE4AD_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ return -ERANGE;
+}
+
+static int MX35LF4GE4AD_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section > 7)
+ return -ERANGE;
+
+ region->offset = (16 * section) + 2;
+ region->length = 14;
+
+ return 0;
+}
+#endif
static const struct mtd_ooblayout_ops mx35lfxge4ab_ooblayout = {
.ecc = mx35lfxge4ab_ooblayout_ecc,
.free = mx35lfxge4ab_ooblayout_free,
};
+static const struct mtd_ooblayout_ops MX35LF2GE4AD_ooblayout = {
+ .ecc = MX35LF2GE4AD_ooblayout_ecc,
+ .free = MX35LF2GE4AD_ooblayout_free,
+};
+
+#if 0
+static const struct mtd_ooblayout_ops MX35LF4GE4AD_ooblayout = {
+ .ecc = MX35LF4GE4AD_ooblayout_ecc,
+ .free = MX35LF4GE4AD_ooblayout_free,
+};
+#endif
+
static int mx35lf1ge4ab_get_eccsr(struct spinand_device *spinand, u8 *eccsr)
{
struct spi_mem_op op = SPI_MEM_OP(SPI_MEM_OP_CMD(0x7c, 1),
@@ -82,6 +133,49 @@
if (mx35lf1ge4ab_get_eccsr(spinand, &eccsr))
return nand->eccreq.strength;
+ eccsr &= MACRONIX_CURRENT_ECCSR_MASK;
+ if (WARN_ON(eccsr > nand->eccreq.strength || !eccsr)) {
+ pr_err("spinand eccsr error! %d\n", eccsr);
+ return nand->eccreq.strength;
+ }
+
+ return eccsr;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static int mx35lf2ge4ad_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ struct nand_device *nand = spinand_to_nand(spinand);
+ u8 eccsr;
+
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ case STATUS_ECC_HAS_BITFLIPS:
+ /*
+ * Let's try to retrieve the real maximum number of bitflips
+ * in order to avoid forcing the wear-leveling layer to move
+ * data around if it's not necessary.
+ */
+ if (mx35lf1ge4ab_get_eccsr(spinand, &eccsr))
+ return nand->eccreq.strength;
+
+ /*
+ * note:
+ * bit0~3 ECC Status for the current page
+ * bit4~7 ECC Status for the accumulated page
+ */
+ eccsr &= MACRONIX_CURRENT_ECCSR_MASK;
if (WARN_ON(eccsr > nand->eccreq.strength || !eccsr))
return nand->eccreq.strength;
@@ -95,7 +189,7 @@
}
static const struct spinand_info macronix_spinand_table[] = {
- SPINAND_INFO("MX35LF1GE4AB", 0x12,
+ SPINAND_INFO("MX35LF1GE4AB 3.3v", 0x12,
NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
NAND_ECCREQ(4, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
@@ -104,14 +198,27 @@
SPINAND_HAS_QE_BIT,
SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout,
mx35lf1ge4ab_ecc_get_status)),
- SPINAND_INFO("MX35LF2GE4AB", 0x22,
- NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),
- NAND_ECCREQ(4, 512),
+
+ SPINAND_INFO("MX35LF2GE4AD", 0x26,
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
&write_cache_variants,
&update_cache_variants),
SPINAND_HAS_QE_BIT,
- SPINAND_ECCINFO(&mx35lfxge4ab_ooblayout, NULL)),
+ SPINAND_ECCINFO(&MX35LF2GE4AD_ooblayout,
+ mx35lf2ge4ad_ecc_get_status)),
+
+ SPINAND_INFO("MX35LF4GE4AD", 0x37,
+ NAND_MEMORG(1, 4096, 128, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&MX35LF2GE4AD_ooblayout,
+ mx35lf2ge4ad_ecc_get_status)),
+
};
static int macronix_spinand_detect(struct spinand_device *spinand)
@@ -119,16 +226,12 @@
u8 *id = spinand->id.data;
int ret;
- /*
- * Macronix SPI NAND read ID needs a dummy byte, so the first byte in
- * raw_id is garbage.
- */
- if (id[1] != SPINAND_MFR_MACRONIX)
+ if (id[0] != SPINAND_MFR_MACRONIX)
return 0;
ret = spinand_match_and_init(spinand, macronix_spinand_table,
ARRAY_SIZE(macronix_spinand_table),
- id[2]);
+ id[1]);
if (ret)
return ret;
diff --git a/drivers/mtd/nand/spi/micron.c b/drivers/mtd/nand/spi/micron.c
index 83951c5..cdec93c 100644
--- a/drivers/mtd/nand/spi/micron.c
+++ b/drivers/mtd/nand/spi/micron.c
@@ -21,9 +21,9 @@
#define MICRON_STATUS_ECC_7TO8_BITFLIPS (5 << 4)
static SPINAND_OP_VARIANTS(read_cache_variants,
- SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+ //SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
- SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ //SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
@@ -33,7 +33,7 @@
SPINAND_PROG_LOAD(true, 0, NULL, 0));
static SPINAND_OP_VARIANTS(update_cache_variants,
- SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ //SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section,
@@ -93,7 +93,7 @@
}
static const struct spinand_info micron_spinand_table[] = {
- SPINAND_INFO("MT29F2G01ABAGD", 0x24,
+ SPINAND_INFO("MT29F2G01ABAGD/F50L2G41XA", 0x24,
NAND_MEMORG(1, 2048, 128, 64, 2048, 2, 1, 1),
NAND_ECCREQ(8, 512),
SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
@@ -109,15 +109,11 @@
u8 *id = spinand->id.data;
int ret;
- /*
- * Micron SPI NAND read ID need a dummy byte,
- * so the first byte in raw_id is dummy.
- */
- if (id[1] != SPINAND_MFR_MICRON)
+ if (id[0] != SPINAND_MFR_MICRON)
return 0;
ret = spinand_match_and_init(spinand, micron_spinand_table,
- ARRAY_SIZE(micron_spinand_table), id[2]);
+ ARRAY_SIZE(micron_spinand_table), id[1]);
if (ret)
return ret;
diff --git a/drivers/mtd/nand/spi/storage_sn.c b/drivers/mtd/nand/spi/storage_sn.c
new file mode 100644
index 0000000..455f354
--- /dev/null
+++ b/drivers/mtd/nand/spi/storage_sn.c
@@ -0,0 +1,144 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <spi.h>
+//#include <nand.h>
+#include <dm/device-internal.h>
+#include <linux/mtd/mtd.h>
+#include <linux/mtd/rawnand.h>
+#include <linux/mtd/partitions.h>
+#include <amlogic/storage.h>
+#include <amlogic/aml_mtd.h>
+#include <linux/mtd/spinand.h>
+#include <dm/pinctrl.h>
+
+
+static struct storage_t *snand_storage;
+extern void mtd_store_set(struct mtd_info *mtd, int dev);
+extern void mtd_store_mount_ops(struct storage_t *store);
+extern int spinand_add_partitions(struct mtd_info *mtd,
+ const struct mtd_partition *parts,
+ int nbparts);
+
+static inline void set_snand_storage(struct storage_t *snand)
+{
+ snand_storage = snand;
+}
+
+static inline struct storage_t *get_snand_storage(void)
+{
+ return snand_storage;
+}
+
+int board_nand_init(void)
+{
+ u32 bus = 0, cs = 1, speed = 0, mode = 0;
+ struct spi_slave *slave;
+ struct udevice *dev;
+ int ret;
+
+ ret = spi_get_bus_and_cs(bus, cs, speed, mode,
+ NULL, NULL, &dev, &slave);
+ if (ret) {
+ printf("%s %d probe spi nand fail!\n",
+ __func__, __LINE__);
+ return 1;
+ }
+
+ return 0;
+}
+
+int spinand_fit_storage(struct mtd_info *info, char *name, u8 *id)
+{
+ struct storage_t *spi_nand = NULL;
+ struct mtd_info *mtd = info;
+ int ret = 0;
+
+ if (get_snand_storage())
+ return 0;
+ spi_nand = kzalloc(sizeof(*spi_nand), GFP_KERNEL);
+ if (!spi_nand) {
+ debug("%s %d no enough memory!\n", __func__, __LINE__);
+ return -ENOMEM;
+ }
+ spi_nand->type = BOOT_SNAND;
+ spi_nand->init_flag = 0;
+ /* TODO:set name and id parameter */
+ memcpy(spi_nand->info.name,
+ name, strlen(name) > 32 ? 32 : strlen(name));
+ memcpy(spi_nand->info.id, id, NAND_MAX_ID_LEN);
+ spi_nand->info.read_unit = mtd->writesize;
+ spi_nand->info.write_unit = mtd->writesize;
+ spi_nand->info.erase_unit = mtd->erasesize;
+ spi_nand->info.caps = mtd->size;
+ spi_nand->info.mode = 1;
+
+ set_snand_storage(spi_nand);
+ mtd_store_mount_ops(spi_nand);
+ ret = store_register(spi_nand);
+ if (ret)
+ return ret;
+ mtd_store_set(mtd, 0);
+ return ret;
+}
+
+int spi_nand_pre(void)
+{
+ struct storage_t *spi_nand = get_snand_storage();
+
+ if (spi_nand)
+ return 0;
+
+ return board_nand_init();
+}
+
+int spi_nand_probe(u32 init_flag)
+{
+ struct spinand_device *spinand_dev;
+ struct storage_t *spi_nand = get_snand_storage();
+ const struct mtd_partition *spinand_partitions;
+ struct mtd_info *mtd;
+ int partition_count, ret;
+ static int probe_flag;
+
+ /* Maybe pinmux be modified by emmc, set again here */
+ extern struct mtd_info *mtd_store_get(int dev);
+ mtd = mtd_store_get(0);
+ spinand_dev = mtd_to_spinand(mtd);
+ //dm_spi_claim_bus(spinand_dev->slave->dev);
+ ret = pinctrl_select_state(spinand_dev->slave->dev->parent, "default");
+ if (ret) {
+ pr_err("select state %s failed\n", "default");
+ return 1;
+ }
+
+ if (probe_flag)
+ return 0;
+
+#ifdef CONFIG_AML_MTDPART
+ extern const struct mtd_partition *get_spinand_partition_table(int *partitions);
+ spinand_partitions = get_spinand_partition_table(&partition_count);
+ ret = spinand_add_partitions(mtd, spinand_partitions,
+ partition_count);
+ if (ret) {
+ printf("%s %d can not add spinand partition!\n",
+ __func__, __LINE__);
+ return 1;
+ }
+#endif
+
+ spi_nand = get_snand_storage();
+ if (!spi_nand) {
+ printf("%s %d can not get spi nand!\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ spi_nand->init_flag = init_flag;
+ probe_flag = 1;
+
+ return 0;
+}
diff --git a/drivers/mtd/nand/spi/toshiba.c b/drivers/mtd/nand/spi/toshiba.c
new file mode 100644
index 0000000..9af8ea3
--- /dev/null
+++ b/drivers/mtd/nand/spi/toshiba.c
@@ -0,0 +1,159 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __UBOOT__
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_TOSHIBA 0x98
+
+/* Bit errors were detected and corrected.
+ * Bit error count exceeded the bit flip detection threshold.
+ * The threshold is set by bits [7:4] in address 10h in the feature table
+ */
+#define TOSHIBA_STATUS_ECC_8_BITFLIPS (3 << 4)
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+ //SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+ SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int tc58cvg0s3hraig_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ /* Unable to know the layout of ECC */
+ return -ERANGE;
+}
+
+static int tc58cvg0s3hraig_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ /* Reserve 2 bytes for the BBM. */
+ region->offset = 2;
+ region->length = 62;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops tc58cvg0s3hraig_ooblayout = {
+ .ecc = tc58cvg0s3hraig_ooblayout_ecc,
+ .free = tc58cvg0s3hraig_ooblayout_free,
+};
+
+static int tc58cvg0s3hraig_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case STATUS_ECC_HAS_BITFLIPS:
+ /*
+ * We have no way to know exactly how many bitflips have been
+ * fixed, so let's return the maximum possible value so that
+ * wear-leveling layers move the data immediately.
+ */
+ return 7;
+
+ case TOSHIBA_STATUS_ECC_8_BITFLIPS:
+ /*
+ * We have no way to know exactly how many bitflips have been
+ * fixed, so let's return the maximum possible value so that
+ * wear-leveling layers move the data immediately.
+ */
+ return 8;
+
+ case STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static const struct spinand_info toshiba_spinand_table[] = {
+ SPINAND_INFO("TC58CVG0S3HRAIG 3.3V", 0xc2,
+ NAND_MEMORG(1, 2048, 128, 64, 1024, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&tc58cvg0s3hraig_ooblayout,
+ tc58cvg0s3hraig_ecc_get_status)),
+
+ SPINAND_INFO("TC58CYG1S3HRAIG 1.8V", 0xdb,
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&tc58cvg0s3hraig_ooblayout,
+ tc58cvg0s3hraig_ecc_get_status)),
+
+ SPINAND_INFO("TC58CVG1S3HRAIG 3.3V", 0xcb,
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&tc58cvg0s3hraig_ooblayout,
+ tc58cvg0s3hraig_ecc_get_status)),
+
+ SPINAND_INFO("TC58CVG2S0HRAIG 3.3V", 0xcd,
+ NAND_MEMORG(1, 4096, 128, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ 0,
+ SPINAND_ECCINFO(&tc58cvg0s3hraig_ooblayout,
+ tc58cvg0s3hraig_ecc_get_status)),
+};
+
+static int toshiba_spinand_detect(struct spinand_device *spinand)
+{
+ u8 *id = spinand->id.data;
+ int ret;
+
+ if (id[0] != SPINAND_MFR_TOSHIBA)
+ return 0;
+
+ ret = spinand_match_and_init(spinand, toshiba_spinand_table,
+ ARRAY_SIZE(toshiba_spinand_table),
+ id[1]);
+ if (ret)
+ return ret;
+
+ return 1;
+}
+
+static const struct spinand_manufacturer_ops toshiba_spinand_manuf_ops = {
+ .detect = toshiba_spinand_detect,
+};
+
+const struct spinand_manufacturer toshiba_spinand_manufacturer = {
+ .id = SPINAND_MFR_TOSHIBA,
+ .name = "Toshiba",
+ .ops = &toshiba_spinand_manuf_ops,
+};
diff --git a/drivers/mtd/nand/spi/winbond.c b/drivers/mtd/nand/spi/winbond.c
index eac811d..4d42dac 100644
--- a/drivers/mtd/nand/spi/winbond.c
+++ b/drivers/mtd/nand/spi/winbond.c
@@ -18,9 +18,9 @@
#define WINBOND_CFG_BUF_READ BIT(3)
static SPINAND_OP_VARIANTS(read_cache_variants,
- SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
+ //SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
- SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
+ //SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
@@ -30,7 +30,7 @@
SPINAND_PROG_LOAD(true, 0, NULL, 0));
static SPINAND_OP_VARIANTS(update_cache_variants,
- SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ //SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
SPINAND_PROG_LOAD(false, 0, NULL, 0));
static int w25m02gv_ooblayout_ecc(struct mtd_info *mtd, int section,
@@ -98,15 +98,11 @@
u8 *id = spinand->id.data;
int ret;
- /*
- * Winbond SPI NAND read ID need a dummy byte,
- * so the first byte in raw_id is dummy.
- */
- if (id[1] != SPINAND_MFR_WINBOND)
+ if (id[0] != SPINAND_MFR_WINBOND)
return 0;
ret = spinand_match_and_init(spinand, winbond_spinand_table,
- ARRAY_SIZE(winbond_spinand_table), id[2]);
+ ARRAY_SIZE(winbond_spinand_table), id[1]);
if (ret)
return ret;
diff --git a/drivers/mtd/nand/spi/xtx.c b/drivers/mtd/nand/spi/xtx.c
new file mode 100644
index 0000000..319b147
--- /dev/null
+++ b/drivers/mtd/nand/spi/xtx.c
@@ -0,0 +1,158 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __UBOOT__
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_XTX 0x0b
+#define ZETTA_STATUS_ECC_NO_BITFLIPS (0 << 2)
+#define ZETTA_STATUS_ECC_1_BITFLIPS (1 << 2)
+#define ZETTA_STATUS_ECC_2_BITFLIPS (2 << 2)
+#define ZETTA_STATUS_ECC_3_BITFLIPS (3 << 2)
+#define ZETTA_STATUS_ECC_4_BITFLIPS (4 << 2)
+#define ZETTA_STATUS_ECC_5_BITFLIPS (5 << 2)
+#define ZETTA_STATUS_ECC_6_BITFLIPS (6 << 2)
+#define ZETTA_STATUS_ECC_7_BITFLIPS (7 << 2)
+#define ZETTA_STATUS_ECC_ECC_UNCOR_ERROR (8 << 2)
+#define ZETTA_STATUS_ECC_8_BITFLIPS (0xc << 2)
+#define ZETTA_STATUS_ECC_MASK GENMASK(5, 2)
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+ //SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int ZXT26G01AWSEGA_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ region->offset = 48;
+ region->length = 16;
+
+ return 0;
+
+}
+
+static int ZXT26G01AWSEGA_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ /* Reserve 2 bytes for the BBM. */
+ region->offset = 2;
+ region->length = 46;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops ZXT26G01AWSEGA_ooblayout = {
+ .ecc = ZXT26G01AWSEGA_ooblayout_ecc,
+ .free = ZXT26G01AWSEGA_ooblayout_free,
+};
+
+static int ZXT26G01AWSEGA_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ switch (status & ZETTA_STATUS_ECC_MASK) {
+ case ZETTA_STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case ZETTA_STATUS_ECC_1_BITFLIPS:
+ return 1;
+
+ case ZETTA_STATUS_ECC_2_BITFLIPS:
+ return 2;
+
+ case ZETTA_STATUS_ECC_3_BITFLIPS:
+ return 3;
+
+ case ZETTA_STATUS_ECC_4_BITFLIPS:
+ return 4;
+
+ case ZETTA_STATUS_ECC_5_BITFLIPS:
+ return 5;
+
+ case ZETTA_STATUS_ECC_6_BITFLIPS:
+ return 6;
+
+ case ZETTA_STATUS_ECC_7_BITFLIPS:
+ return 7;
+
+ case ZETTA_STATUS_ECC_8_BITFLIPS:
+ return 8;
+
+ case ZETTA_STATUS_ECC_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static const struct spinand_info xtx_spinand_table[] = {
+ SPINAND_INFO("XT26G01AWSEGA 3.3V", 0xe1,
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ZXT26G01AWSEGA_ooblayout,
+ ZXT26G01AWSEGA_ecc_get_status)),
+
+ SPINAND_INFO("XT26G02AWSEGA 3.3V", 0xe2,
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 1, 1, 1),
+ NAND_ECCREQ(8, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ZXT26G01AWSEGA_ooblayout,
+ ZXT26G01AWSEGA_ecc_get_status)),
+};
+
+static int xtx_spinand_detect(struct spinand_device *spinand)
+{
+ u8 *id = spinand->id.data;
+ int ret;
+
+ if (id[0] != SPINAND_MFR_XTX)
+ return 0;
+
+ ret = spinand_match_and_init(spinand, xtx_spinand_table,
+ ARRAY_SIZE(xtx_spinand_table),
+ id[1]);
+ if (ret)
+ return ret;
+
+ return 1;
+}
+
+static const struct spinand_manufacturer_ops xtx_spinand_manuf_ops = {
+ .detect = xtx_spinand_detect,
+};
+
+const struct spinand_manufacturer xtx_spinand_manufacturer = {
+ .id = SPINAND_MFR_XTX,
+ .name = "xtx",
+ .ops = &xtx_spinand_manuf_ops,
+};
diff --git a/drivers/mtd/nand/spi/zetta.c b/drivers/mtd/nand/spi/zetta.c
new file mode 100644
index 0000000..a136ed3
--- /dev/null
+++ b/drivers/mtd/nand/spi/zetta.c
@@ -0,0 +1,138 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __UBOOT__
+#include <linux/device.h>
+#include <linux/kernel.h>
+#endif
+#include <linux/mtd/spinand.h>
+
+#define SPINAND_MFR_ZETTA 0xba
+
+static SPINAND_OP_VARIANTS(read_cache_variants,
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
+
+static SPINAND_OP_VARIANTS(write_cache_variants,
+ SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
+ SPINAND_PROG_LOAD(true, 0, NULL, 0));
+
+static SPINAND_OP_VARIANTS(update_cache_variants,
+ //SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
+ SPINAND_PROG_LOAD(false, 0, NULL, 0));
+
+static int ZD35Q1GA_ooblayout_ecc(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ /* the ECC parity code can be calculated
+ * properly and stored in the additional
+ * hidden spare area
+ */
+ return -ERANGE;
+}
+
+static int ZD35Q1GA_ooblayout_free(struct mtd_info *mtd, int section,
+ struct mtd_oob_region *region)
+{
+ if (section)
+ return -ERANGE;
+
+ /* Reserve 2 bytes for the BBM. */
+ region->offset = 2;
+ region->length = 62;
+
+ return 0;
+}
+
+static const struct mtd_ooblayout_ops ZD35Q1GA_ooblayout = {
+ .ecc = ZD35Q1GA_ooblayout_ecc,
+ .free = ZD35Q1GA_ooblayout_free,
+};
+
+static int ZD35Q1GA_ecc_get_status(struct spinand_device *spinand,
+ u8 status)
+{
+ switch (status & STATUS_ECC_MASK) {
+ case STATUS_ECC_NO_BITFLIPS:
+ return 0;
+
+ case STATUS_ECC_HAS_BITFLIPS:
+ /*
+ * We have no way to know exactly how many bitflips have been
+ * fixed, so let's return the maximum possible value so that
+ * wear-leveling layers move the data immediately.
+ */
+ return 4;
+
+ case STATUS_ECC_UNCOR_ERROR:
+ return -EBADMSG;
+
+ default:
+ break;
+ }
+
+ return -EINVAL;
+}
+
+static const struct spinand_info zetta_spinand_table[] = {
+ SPINAND_INFO("ZD35Q1GA 3.3V", 0x71,
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ZD35Q1GA_ooblayout,
+ ZD35Q1GA_ecc_get_status)),
+#if 0
+ SPINAND_INFO("ZD35M1GA 1.8V", 0x21,
+ NAND_MEMORG(1, 2048, 64, 64, 1024, 1, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ZD35Q1GA_ooblayout,
+ ZD35Q1GA_ecc_get_status)),
+#endif
+ SPINAND_INFO("ZD35M2GA 3.3V", 0x72,
+ NAND_MEMORG(1, 2048, 64, 64, 2048, 2, 1, 1),
+ NAND_ECCREQ(4, 512),
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+ &write_cache_variants,
+ &update_cache_variants),
+ SPINAND_HAS_QE_BIT,
+ SPINAND_ECCINFO(&ZD35Q1GA_ooblayout,
+ ZD35Q1GA_ecc_get_status)),
+};
+
+static int zetta_spinand_detect(struct spinand_device *spinand)
+{
+ u8 *id = spinand->id.data;
+ int ret;
+
+ if (id[0] != SPINAND_MFR_ZETTA)
+ return 0;
+
+ ret = spinand_match_and_init(spinand, zetta_spinand_table,
+ ARRAY_SIZE(zetta_spinand_table),
+ id[1]);
+ if (ret)
+ return ret;
+
+ return 1;
+}
+
+static const struct spinand_manufacturer_ops zetta_spinand_manuf_ops = {
+ .detect = zetta_spinand_detect,
+};
+
+const struct spinand_manufacturer zetta_spinand_manufacturer = {
+ .id = SPINAND_MFR_ZETTA,
+ .name = "Zetta",
+ .ops = &zetta_spinand_manuf_ops,
+};
diff --git a/drivers/mtd/spi/Kconfig b/drivers/mtd/spi/Kconfig
index 9912d91..b810274 100644
--- a/drivers/mtd/spi/Kconfig
+++ b/drivers/mtd/spi/Kconfig
@@ -146,5 +146,14 @@
If unsure, say N
-endmenu # menu "SPI Flash Support"
+config SPI_FLASH_AML_ADVANCED
+ bool "SPI Flash meson advanced support"
+ depends on SPI_FLASH && DM_SPI_FLASH
+ default n
+ help
+ SC2 needs to support a new burning mode (ADVANCED), we implement
+ it based on the original discrete modem. If say Y enabled ADVANCED
+ mode, spinor will use DISCRETE mode to burning.
+ If unsure, say N
+endmenu # menu "SPI Flash Support"
diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile
index b4c7e1c..00a179e 100644
--- a/drivers/mtd/spi/Makefile
+++ b/drivers/mtd/spi/Makefile
@@ -13,3 +13,7 @@
obj-$(CONFIG_SPI_FLASH_DATAFLASH) += sf_dataflash.o
obj-$(CONFIG_SPI_FLASH_MTD) += sf_mtd.o
obj-$(CONFIG_SPI_FLASH_SANDBOX) += sandbox.o
+ifeq ($(CONFIG_SPI_FLASH),y)
+obj-$(CONFIG_AML_STORAGE) += storage_sf.o
+obj-$(CONFIG_AML_MTDPART) += sf_partition.o
+endif
diff --git a/drivers/mtd/spi/sf_internal.h b/drivers/mtd/spi/sf_internal.h
index 46a5044..08b99e0 100644
--- a/drivers/mtd/spi/sf_internal.h
+++ b/drivers/mtd/spi/sf_internal.h
@@ -37,6 +37,7 @@
#define SPI_FLASH_CFI_MFR_SST 0xbf
#define SPI_FLASH_CFI_MFR_WINBOND 0xef
#define SPI_FLASH_CFI_MFR_ATMEL 0x1f
+#define SPI_FLASH_CFI_MFR_GIGA 0xc8
/* Erase commands */
#define CMD_ERASE_4K 0x20
@@ -84,6 +85,7 @@
#define SPI_FLASH_PROG_TIMEOUT (2 * CONFIG_SYS_HZ)
#define SPI_FLASH_PAGE_ERASE_TIMEOUT (5 * CONFIG_SYS_HZ)
#define SPI_FLASH_SECTOR_ERASE_TIMEOUT (10 * CONFIG_SYS_HZ)
+#define SPI_FLASH_CHIP_ERASE_TIMEOUT (60 * CONFIG_SYS_HZ)
/* SST specific */
#ifdef CONFIG_SPI_FLASH_SST
@@ -194,6 +196,12 @@
return spi_flash_cmd(flash->spi, CMD_WRITE_DISABLE, NULL, 0);
}
+/* Erase the whole chip on the SPI flash */
+static inline int spi_flash_cmd_erase_chip(struct spi_flash *flash)
+{
+ return spi_flash_cmd(flash->spi, CMD_ERASE_CHIP, NULL, 0);
+}
+
/*
* Used for spi_flash write operation
* - SPI claim
diff --git a/drivers/mtd/spi/sf_mtd.c b/drivers/mtd/spi/sf_mtd.c
index 68c3600..87ec799 100644
--- a/drivers/mtd/spi/sf_mtd.c
+++ b/drivers/mtd/spi/sf_mtd.c
@@ -8,11 +8,24 @@
#include <linux/errno.h>
#include <linux/mtd/mtd.h>
#include <spi_flash.h>
+#include <linux/log2.h>
+
+#ifdef CONFIG_AML_MTDPART
+extern int spinor_add_partitions(struct mtd_info *mtd);
+extern int spinor_del_partitions(struct mtd_info *mtd);
+#endif
static struct mtd_info sf_mtd_info;
static bool sf_mtd_registered;
static char sf_mtd_name[8];
+#ifdef CONFIG_AML_STORAGE
+struct mtd_info *spi_flash_get_mtd(void)
+{
+ return &sf_mtd_info;
+}
+#endif
+
static int spi_flash_mtd_erase(struct mtd_info *mtd, struct erase_info *instr)
{
struct spi_flash *flash = mtd->priv;
@@ -86,7 +99,11 @@
int ret;
if (sf_mtd_registered) {
+ #ifndef CONFIG_AML_MTDPART
ret = del_mtd_device(&sf_mtd_info);
+ #else
+ ret = spinor_del_partitions(&sf_mtd_info);
+ #endif
if (ret)
return ret;
@@ -119,6 +136,15 @@
if (!ret)
sf_mtd_registered = true;
+#ifdef CONFIG_AML_MTDPART
+ /*
+ * add_mtd_device must be before spinor_add_partitions
+ * because add_mtd_device will init mtd->partitions
+ */
+ if (is_power_of_2(sf_mtd_info.erasesize))
+ sf_mtd_info.erasesize_shift = ffs(sf_mtd_info.erasesize) - 1;
+ ret = spinor_add_partitions(&sf_mtd_info);
+#endif /* CONFIG_AML_MTDPART */
return ret;
}
diff --git a/drivers/mtd/spi/sf_partition.c b/drivers/mtd/spi/sf_partition.c
new file mode 100644
index 0000000..42908c0
--- /dev/null
+++ b/drivers/mtd/spi/sf_partition.c
@@ -0,0 +1,143 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <malloc.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <linux/mtd/partitions.h>
+#include <linux/types.h>
+#include <linux/sizes.h>
+#include <malloc.h>
+#include <linux/errno.h>
+#include <mtd.h>
+#include <amlogic/aml_mtd.h>
+#include <amlogic/storage.h>
+#include <amlogic/cpu_id.h>
+
+/* Hard code, all partitions are aligned in block size, fast erasing */
+#define SPINOR_ALIGNED_SIZE (64 * 1024)
+extern struct storage_startup_parameter g_ssp;
+
+/* do not use default value, rewrite this function in the board file */
+uint64_t __weak spiflash_bootloader_size(void)
+{
+ return SZ_2M;
+}
+
+uint32_t __weak spiflash_rsv_block_num(void)
+{
+ return 0;
+}
+
+extern boot_area_entry_t general_boot_part_entry[MAX_BOOT_AREA_ENTRIES];
+/* The size of the partition must be block aligned */
+static int _spinor_add_partitions(struct mtd_info *mtd,
+ const struct mtd_partition *parts,
+ int nbparts)
+{
+ int part_num = 0, i = 0;
+ struct mtd_partition *temp, *parts_nm;
+ loff_t off;
+
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER)
+ /* spinor add discrete mode for advanced */
+ part_num = nbparts + 5;
+ else
+ part_num = nbparts + 1;
+
+ temp = kzalloc(sizeof(*temp) * part_num, GFP_KERNEL);
+ memset(temp, 0, sizeof(*temp) * part_num);
+ if (store_get_device_bootloader_mode() == DISCRETE_BOOTLOADER) {
+ temp[BOOT_AREA_BB1ST].name = BOOT_LOADER;
+ temp[BOOT_AREA_BB1ST].offset = general_boot_part_entry[BOOT_AREA_BB1ST].offset;
+ temp[BOOT_AREA_BB1ST].size = general_boot_part_entry[BOOT_AREA_BB1ST].size * g_ssp.boot_bakups;
+ if (temp[BOOT_AREA_BB1ST].size % SPINOR_ALIGNED_SIZE)
+ WARN_ON(1);
+
+ temp[BOOT_AREA_BL2E].name = BOOT_BL2E;
+ temp[BOOT_AREA_BL2E].offset = general_boot_part_entry[BOOT_AREA_BL2E].offset;
+ temp[BOOT_AREA_BL2E].size = general_boot_part_entry[BOOT_AREA_BL2E].size * g_ssp.boot_bakups;
+ if (temp[0].size % SPINOR_ALIGNED_SIZE)
+ WARN_ON(1);
+
+ temp[BOOT_AREA_BL2X].name = BOOT_BL2X;
+ temp[BOOT_AREA_BL2X].offset = general_boot_part_entry[BOOT_AREA_BL2X].offset;
+ temp[BOOT_AREA_BL2X].size = general_boot_part_entry[BOOT_AREA_BL2X].size * g_ssp.boot_bakups;
+ if (temp[0].size % SPINOR_ALIGNED_SIZE)
+ WARN_ON(1);
+
+ temp[BOOT_AREA_DDRFIP].name = BOOT_DDRFIP;
+ temp[BOOT_AREA_DDRFIP].offset = general_boot_part_entry[BOOT_AREA_DDRFIP].offset;
+ temp[BOOT_AREA_DDRFIP].size = general_boot_part_entry[BOOT_AREA_DDRFIP].size * g_ssp.boot_bakups;
+ if (temp[0].size % SPINOR_ALIGNED_SIZE)
+ WARN_ON(1);
+
+ temp[BOOT_AREA_DEVFIP].name = BOOT_DEVFIP;
+ temp[BOOT_AREA_DEVFIP].offset = general_boot_part_entry[BOOT_AREA_DEVFIP].offset;
+ temp[BOOT_AREA_DEVFIP].size = general_boot_part_entry[BOOT_AREA_DEVFIP].size *
+ CONFIG_NOR_TPL_COPY_NUM;
+ if (temp[0].size % SPINOR_ALIGNED_SIZE)
+ WARN_ON(1);
+
+ off = temp[BOOT_AREA_DEVFIP].offset + temp[BOOT_AREA_DEVFIP].size;
+ parts_nm = &temp[5];
+ } else {
+ temp[0].name = BOOT_LOADER;
+ temp[0].offset = 0;
+ temp[0].size = spiflash_bootloader_size();
+ if (temp[0].size % SPINOR_ALIGNED_SIZE)
+ WARN_ON(1);
+ /* rsv size is aligned with blocksize(64K) */
+ off = temp[0].size + spiflash_rsv_block_num() * SPINOR_ALIGNED_SIZE;
+ parts_nm = &temp[1];
+ }
+ for (i = 0; i < nbparts; i++) {
+ if (!parts[i].name) {
+ pr_err("name can't be null! ");
+ pr_err("please check your %d th partition name!\n",
+ i + 1);
+ return 1;
+ }
+ if ((off + parts[i].size) > mtd->size) {
+ pr_err("%s %d over nand size!\n",
+ __func__, __LINE__);
+ return 1;
+ }
+ parts_nm[i].name = parts[i].name;
+ parts_nm[i].offset = off;
+ if (parts[i].size % SPINOR_ALIGNED_SIZE) {
+ pr_err("%s %d \"%s\" size auto align to block size\n",
+ __func__, __LINE__, parts[i].name);
+ parts_nm[i].size += parts[i].size % SPINOR_ALIGNED_SIZE;
+ }
+ /* it's ok "+=" here because size has been set to 0 */
+ parts_nm[i].size += parts[i].size;
+ off += parts_nm[i].size;
+ if (i == (nbparts - 1))
+ parts_nm[i].size = mtd->size - off;
+ }
+
+ return add_mtd_partitions(mtd, temp, part_num);
+}
+
+extern struct mtd_partition *get_spiflash_partition_table(int *partitions);
+int spinor_add_partitions(struct mtd_info *mtd)
+{
+ struct mtd_partition *spiflash_partitions;
+ int partition_count;
+
+ spiflash_partitions = get_spiflash_partition_table(&partition_count);
+
+ return _spinor_add_partitions(mtd, spiflash_partitions,
+ partition_count);
+}
+
+int spinor_del_partitions(struct mtd_info *mtd)
+{
+ return del_mtd_partitions(mtd);
+}
diff --git a/drivers/mtd/spi/sf_probe.c b/drivers/mtd/spi/sf_probe.c
index 00f8558..761833f 100644
--- a/drivers/mtd/spi/sf_probe.c
+++ b/drivers/mtd/spi/sf_probe.c
@@ -16,6 +16,10 @@
#include "sf_internal.h"
+#ifdef CONFIG_AML_STORAGE
+extern int spi_flash_fit_storage(struct spi_flash *flash);
+#endif
+
/**
* spi_flash_probe_slave() - Probe for a SPI flash device on a bus
*
@@ -45,8 +49,13 @@
goto err_read_id;
#ifdef CONFIG_SPI_FLASH_MTD
- ret = spi_flash_mtd_register(flash);
-#endif
+ /* for advanced support */
+ //ret = spi_flash_mtd_register(flash);
+#ifdef CONFIG_AML_STORAGE
+ if (!ret)
+ ret = spi_flash_fit_storage(flash);
+#endif /* CONFIG_AML_STORAGE */
+#endif /* CONFIG_SPI_FLASH_MTD */
err_read_id:
spi_release_bus(spi);
diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c
index 0c2392f..57509d2 100644
--- a/drivers/mtd/spi/spi_flash.c
+++ b/drivers/mtd/spi/spi_flash.c
@@ -72,7 +72,7 @@
return 0;
}
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) || defined(CONFIG_SPI_FLASH_GIGADEVICE)
static int read_cr(struct spi_flash *flash, u8 *rc)
{
int ret;
@@ -323,26 +323,49 @@
return ret;
}
-int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+/* erase whole chip in one command */
+static int spi_flash_erase_chip(struct spi_flash *flash)
+{
+ struct spi_slave *spi = flash->spi;
+ unsigned long timeout = SPI_FLASH_CHIP_ERASE_TIMEOUT;
+ int ret;
+
+ ret = spi_claim_bus(spi);
+ if (ret) {
+ debug("SF: unable to claim SPI bus\n");
+ return ret;
+ }
+
+ ret = spi_flash_cmd_write_enable(flash);
+ if (ret < 0) {
+ debug("SF: enabling write failed\n");
+ return ret;
+ }
+
+ ret = spi_flash_cmd_erase_chip(flash);
+ if (ret < 0) {
+ debug("SF: erase chip cmd failed\n");
+ return ret;
+ }
+
+ ret = spi_flash_wait_till_ready(flash, timeout);
+ if (ret < 0) {
+ debug("SF: chip erase timed out\n");
+ return ret;
+ }
+
+ spi_release_bus(spi);
+
+ return ret;
+}
+
+static int _spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
{
u32 erase_size, erase_addr;
u8 cmd[SPI_FLASH_CMD_LEN];
int ret = -1;
erase_size = flash->erase_size;
- if (offset % erase_size || len % erase_size) {
- printf("SF: Erase offset/length not multiple of erase size\n");
- return -1;
- }
-
- if (flash->flash_is_locked) {
- if (flash->flash_is_locked(flash, offset, len) > 0) {
- printf("offset 0x%x is protected and cannot be erased\n",
- offset);
- return -EINVAL;
- }
- }
-
cmd[0] = flash->erase_cmd;
while (len) {
erase_addr = offset;
@@ -378,8 +401,41 @@
return ret;
}
+int spi_flash_cmd_erase_ops(struct spi_flash *flash, u32 offset, size_t len)
+{
+ u32 erase_size;
+ int ret = -1;
+
+ erase_size = flash->erase_size;
+ if (offset % erase_size || len % erase_size) {
+ printf("SF: Erase offset/length not multiple of erase size\n");
+ return -1;
+ }
+
+ if (flash->flash_is_locked) {
+ if (flash->flash_is_locked(flash, offset, len) > 0) {
+ printf("offset 0x%x is protected and cannot be erased\n",
+ offset);
+ return -EINVAL;
+ }
+ }
+
+ if ((offset == 0) && (len == flash->size))
+ ret = spi_flash_erase_chip(flash);
+ else
+ ret = _spi_flash_cmd_erase_ops(flash, offset, len);
+
+ return ret;
+
+}
+
+#ifndef CONFIG_AML_SPIFCV2
int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
size_t len, const void *buf)
+#else
+static int _spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ size_t len, const void *buf)
+#endif
{
struct spi_slave *spi = flash->spi;
unsigned long byte_addr, page_size;
@@ -440,6 +496,31 @@
return ret;
}
+#ifdef CONFIG_AML_SPIFCV2
+int spi_flash_cmd_write_ops(struct spi_flash *flash, u32 offset,
+ size_t len, const void *buf)
+{
+ int ret;
+ size_t lening = len;
+
+ if ((len > 16) && (len % 16)) {
+ lening >>= 4;
+ lening <<= 4;
+ ret = _spi_flash_cmd_write_ops(flash, offset,
+ lening, buf);
+
+ offset += lening;
+ len -= lening;
+ buf += lening;
+ }
+
+ ret = _spi_flash_cmd_write_ops(flash, offset,
+ len, buf);
+
+ return ret;
+}
+#endif
+
int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd,
size_t cmd_len, void *data, size_t data_len)
{
@@ -1035,7 +1116,7 @@
}
#endif
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) || defined(CONFIG_SPI_FLASH_GIGADEVICE)
static int spansion_quad_enable(struct spi_flash *flash)
{
u8 qeb_status;
@@ -1063,7 +1144,7 @@
}
#endif
-static const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash)
+const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash)
{
int tmp;
u8 id[SPI_FLASH_MAX_ID_LEN];
@@ -1096,9 +1177,10 @@
case SPI_FLASH_CFI_MFR_MACRONIX:
return macronix_quad_enable(flash);
#endif
-#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND)
+#if defined(CONFIG_SPI_FLASH_SPANSION) || defined(CONFIG_SPI_FLASH_WINBOND) || defined(CONFIG_SPI_FLASH_GIGADEVICE)
case SPI_FLASH_CFI_MFR_SPANSION:
case SPI_FLASH_CFI_MFR_WINBOND:
+ case SPI_FLASH_CFI_MFR_GIGA:
return spansion_quad_enable(flash);
#endif
#ifdef CONFIG_SPI_FLASH_STMICRO
@@ -1320,6 +1402,8 @@
print_size(flash->size, "");
if (flash->memory_map)
printf(", mapped at %p", flash->memory_map);
+ printf(" erase_cmd = 0x%x read_cmd = 0x%x write_cmd = 0x%x\n",
+ flash->erase_cmd, flash->read_cmd, flash->write_cmd);
puts("\n");
#endif
diff --git a/drivers/mtd/spi/spi_flash_ids.c b/drivers/mtd/spi/spi_flash_ids.c
index ad0a0c8..3073e3a 100644
--- a/drivers/mtd/spi/spi_flash_ids.c
+++ b/drivers/mtd/spi/spi_flash_ids.c
@@ -60,12 +60,20 @@
{"en25q64", INFO(0x1c3017, 0x0, 64 * 1024, 128, SECT_4K) },
{"en25q128b", INFO(0x1c3018, 0x0, 64 * 1024, 256, 0) },
{"en25s64", INFO(0x1c3817, 0x0, 64 * 1024, 128, 0) },
+ {"en25qh128", INFO(0x1c7018, 0x0, 64 * 1024, 256, SECT_4K) },
#endif
#ifdef CONFIG_SPI_FLASH_GIGADEVICE /* GIGADEVICE */
{"gd25q16c", INFO(0xc84015, 0x0, 64 * 1024, 32, RD_FULL | WR_QPP | SECT_4K) },
- {"gd25q64b", INFO(0xc84017, 0x0, 64 * 1024, 128, SECT_4K) },
+ {"gd25q127c", INFO(0xc84018, 0x0, 64 * 1024, 256, SECT_4K) },
+ /*
+ * The id of gd25q64b and gd25q64c are the same, but the commands
+ * that enable qe are different. For software compatibility,
+ * temporarily fixed for single line read and write
+ */
+ {"gd25q64b/c", INFO(0xc84017, 0x0, 64 * 1024, 128, SECT_4K) },
{"gd25q32b", INFO(0xc84016, 0x0, 64 * 1024, 64, SECT_4K) },
{"gd25lq32", INFO(0xc86016, 0x0, 64 * 1024, 64, SECT_4K) },
+ {"gd25lq64", INFO(0xc86017, 0x0, 64 * 1024, 128, SECT_4K) },
#endif
#ifdef CONFIG_SPI_FLASH_ISSI /* ISSI */
{"is25lq040b", INFO(0x9d4013, 0x0, 64 * 1024, 8, 0) },
diff --git a/drivers/mtd/spi/storage_sf.c b/drivers/mtd/spi/storage_sf.c
new file mode 100644
index 0000000..46c6b62
--- /dev/null
+++ b/drivers/mtd/spi/storage_sf.c
@@ -0,0 +1,150 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <malloc.h>
+#include <spi.h>
+#include <spi_flash.h>
+#include <amlogic/storage.h>
+#include "sf_internal.h"
+#include <amlogic/cpu_id.h>
+
+struct storage_t *snor_storage;
+static struct spi_flash *spi_flash;
+
+
+extern const struct spi_flash_info *spi_flash_read_id(struct spi_flash *flash);
+extern void mtd_store_set(struct mtd_info *mtd, int dev);
+extern void mtd_store_mount_ops(struct storage_t *store);
+extern struct mtd_info *spi_flash_get_mtd(void);
+
+inline void set_snor_storage(struct storage_t *snor)
+{
+ snor_storage = snor;
+}
+
+inline struct storage_t *get_snor_storage(void)
+{
+ return snor_storage;
+}
+
+void set_spi_flash(struct spi_flash *snor)
+{
+ spi_flash = snor;
+}
+
+struct spi_flash *get_spi_flash(void)
+{
+ return spi_flash;
+}
+
+int spi_flash_fit_storage(struct spi_flash *flash)
+{
+ const struct spi_flash_info *info = NULL;
+ struct storage_t *spi_nor = NULL;
+ int ret = 0;
+ cpu_id_t cpu_id = get_cpu_id();
+
+ if (get_snor_storage())
+ return 0;
+ info = spi_flash_read_id(flash);
+ if (IS_ERR_OR_NULL(info)) {
+ debug("%s %d no matched flash\n", __func__, __LINE__);
+ return 1;
+ }
+ spi_nor = kzalloc(sizeof(*spi_nor), GFP_KERNEL);
+ if (!spi_nor) {
+ debug("%s %d no enough memory!\n", __func__, __LINE__);
+ return -ENOMEM;
+ }
+ spi_nor->type = BOOT_SNOR;
+ spi_nor->init_flag = 0;
+ memcpy(spi_nor->info.name, info->name,
+ strlen(info->name) > 32 ? 32 : strlen(info->name));
+ memcpy(spi_nor->info.id, info->id, info->id_len);
+ spi_nor->info.read_unit = flash->page_size;
+ spi_nor->info.write_unit = flash->page_size;
+ spi_nor->info.erase_unit = flash->erase_size;
+ spi_nor->info.caps = flash->size;
+ if ((cpu_id.family_id == MESON_CPU_MAJOR_ID_SC2) || (cpu_id.family_id == MESON_CPU_MAJOR_ID_T7)
+ || (cpu_id.family_id == MESON_CPU_MAJOR_ID_S4))
+ spi_nor->info.mode = 1;
+ else
+ spi_nor->info.mode = 0;
+ set_snor_storage(spi_nor);
+ mtd_store_mount_ops(spi_nor);
+ ret = store_register(spi_nor);
+ if (ret)
+ return ret;
+ mtd_store_set(spi_flash_get_mtd(), 0);
+ return ret;
+}
+
+int spi_nor_pre(void)
+{
+ u32 bus = 0, cs = 0, speed = 0, mode = 0;
+ struct storage_t *spi_nor = get_snor_storage();
+ struct spi_flash *flash = NULL;
+
+ if (spi_nor)
+ return 0;
+
+ flash = spi_flash_probe(bus, cs, speed, mode);
+ if (!flash) {
+ debug("spi flash probe fail!\n");
+ return 1;
+ }
+
+ set_spi_flash(flash);
+
+ printf("storage-sf mode 0x%x, speed %dHz\n", flash->spi->mode,
+ flash->spi->max_hz);
+
+ return 0;
+}
+
+int spi_nor_probe(u32 init_flag)
+{
+ static int probe_flag;
+ struct storage_t *spi_nor = NULL;
+ struct spi_flash *flash = NULL;
+ int ret;
+
+ flash = (struct spi_flash *)get_spi_flash();
+ if (!flash) {
+ printf("get spi flash fail!\n");
+ return 1;
+ }
+
+ /* Maybe pinmux be modified by emmc, set again here */
+ extern int pinctrl_select_state(struct udevice *dev, const char *statename);
+ ret = pinctrl_select_state(flash->spi->dev->parent, "default");
+ if (ret) {
+ pr_err("select state %s failed\n", "default");
+ return 1;
+ }
+
+ if (probe_flag)
+ return 0;
+
+ ret = spi_flash_mtd_register(flash);
+ if (ret) {
+ printf("spi flash mtd register fail!\n");
+ return 1;
+ }
+
+ spi_nor = get_snor_storage();
+ if (!spi_nor) {
+ printf("can not get spi nor!\n");
+ return 1;
+ }
+
+ spi_nor->init_flag = init_flag;
+ probe_flag = 1;
+
+ return 0;
+}
diff --git a/drivers/mtd/ubi/Kconfig b/drivers/mtd/ubi/Kconfig
index 44cf872..cf84783 100644
--- a/drivers/mtd/ubi/Kconfig
+++ b/drivers/mtd/ubi/Kconfig
@@ -105,4 +105,3 @@
endif # MTD_UBI
endmenu # "Enable UBI - Unsorted block images"
-
diff --git a/drivers/nand/Kconfig b/drivers/nand/Kconfig
index cd9df7a..0fe6798 100644
--- a/drivers/nand/Kconfig
+++ b/drivers/nand/Kconfig
@@ -6,4 +6,3 @@
config SECURE_NAND
bool "secure nand"
depends on AML_NAND
-
diff --git a/drivers/nand/dev/amlnf_config.c b/drivers/nand/dev/amlnf_config.c
index cbbccb0..a203193 100644
--- a/drivers/nand/dev/amlnf_config.c
+++ b/drivers/nand/dev/amlnf_config.c
@@ -1,3 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include "../include/amlnf_dev.h"
#include "../include/phynand.h"
@@ -219,7 +223,7 @@
memcpy(amlnand_config[i].name, part_table[i].name, MAX_PART_NAME_LEN);
amlnand_config[i].size = part_table[i].size;
amlnand_config[i].offset = part_table[i].offset;
- amlnand_config[i].mask_flags = part_table[i].mask_flags;
+ amlnand_config[i].mask_flags = (part_table[i].mask_flags & 0x0f);
if (amlnand_config[i].mask_flags == STORE_CACHE) {
aml_chip->h_cache_dev = 1;/*have cache dev*/
diff --git a/drivers/nand/dev/amlnf_ctrl.c b/drivers/nand/dev/amlnf_ctrl.c
index 28f4b61..32a23a4 100644
--- a/drivers/nand/dev/amlnf_ctrl.c
+++ b/drivers/nand/dev/amlnf_ctrl.c
@@ -1,13 +1,12 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Aml
- *
- * (C) 2012 8
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "../include/phynand.h"
#include <asm/arch/secure_apb.h>
/*when more chips,the patch need fixed, by liuxj*/
-#include <asm/arch-g12a/cpu_id.h>
+#include <amlogic/cpu_id.h>
extern int aml_ubootenv_init(struct amlnand_chip *aml_chip);
#if (AML_CFG_DTB_RSV_EN)
diff --git a/drivers/nand/dev/amlnf_dev.c b/drivers/nand/dev/amlnf_dev.c
index 7611af3..641524c 100644
--- a/drivers/nand/dev/amlnf_dev.c
+++ b/drivers/nand/dev/amlnf_dev.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Aml nftl dev
- *
- * (C) 2012 8
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include "../include/amlnf_dev.h"
diff --git a/drivers/nand/dev/amlnf_dtb.c b/drivers/nand/dev/amlnf_dtb.c
index d96481e..8c83ae9 100644
--- a/drivers/nand/dev/amlnf_dtb.c
+++ b/drivers/nand/dev/amlnf_dtb.c
@@ -1,4 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include "../include/phynand.h"
#ifndef AML_NAND_UBOOT
diff --git a/drivers/nand/dev/amlnf_env.c b/drivers/nand/dev/amlnf_env.c
index 8756cd3..a361aab 100644
--- a/drivers/nand/dev/amlnf_env.c
+++ b/drivers/nand/dev/amlnf_env.c
@@ -1,3 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include "../include/phynand.h"
#ifndef AML_NAND_UBOOT
diff --git a/drivers/nand/dev/amlnf_key.c b/drivers/nand/dev/amlnf_key.c
index de8ba74..d082682 100644
--- a/drivers/nand/dev/amlnf_key.c
+++ b/drivers/nand/dev/amlnf_key.c
@@ -1,3 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include "../include/phynand.h"
diff --git a/drivers/nand/dev/cmd_amlnf.c b/drivers/nand/dev/cmd_amlnf.c
index 062691c..a45f81b 100644
--- a/drivers/nand/dev/cmd_amlnf.c
+++ b/drivers/nand/dev/cmd_amlnf.c
@@ -1,15 +1,8 @@
-/*****************************************************************
-**
-** Copyright (C) 2012 Amlogic,Inc. All rights reserved
-**
-** Filename : driver_uboot.c
-** Revision : 1.001
-** Author: Benjamin Zhao
-** Description:
-** amlnand_init, mainly init nand phy driver.
-**
-**
-*****************************************************************/
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include <config.h>
#include <common.h>
#include <command.h>
diff --git a/drivers/nand/dev/cmd_amlnf_storage.c b/drivers/nand/dev/cmd_amlnf_storage.c
index a0f10a1..d72aa2f 100644
--- a/drivers/nand/dev/cmd_amlnf_storage.c
+++ b/drivers/nand/dev/cmd_amlnf_storage.c
@@ -1,3 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include "../include/phynand.h"
/*#include "storage.h"*/
diff --git a/drivers/nand/dev/cmd_amlnf_test.c b/drivers/nand/dev/cmd_amlnf_test.c
index e1ea3f4..14855b2 100644
--- a/drivers/nand/dev/cmd_amlnf_test.c
+++ b/drivers/nand/dev/cmd_amlnf_test.c
@@ -1,3 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include "../include/phynand.h"
diff --git a/drivers/nand/dev/nandkey.c b/drivers/nand/dev/nandkey.c
index 519ec53..e6bab27 100644
--- a/drivers/nand/dev/nandkey.c
+++ b/drivers/nand/dev/nandkey.c
@@ -1,3 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include "../include/phynand.h"
#ifndef AML_NAND_UBOOT
#include <linux/module.h>
diff --git a/drivers/nand/dev/secure_storage.c b/drivers/nand/dev/secure_storage.c
index cdd89c8..8ccd7a3 100644
--- a/drivers/nand/dev/secure_storage.c
+++ b/drivers/nand/dev/secure_storage.c
@@ -1,3 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include "../include/phynand.h"
diff --git a/drivers/nand/include/aml_nftl_cfg.h b/drivers/nand/include/aml_nftl_cfg.h
index 7cdc5f7..d2db35d 100644
--- a/drivers/nand/include/aml_nftl_cfg.h
+++ b/drivers/nand/include/aml_nftl_cfg.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __AML_NFTL_CFG_H__
#define __AML_NFTL_CFG_H__
#include "../logic/aml_nftl_type.h"
diff --git a/drivers/nand/include/amlnf_cfg.h b/drivers/nand/include/amlnf_cfg.h
index 97f2ba4..26e3790 100644
--- a/drivers/nand/include/amlnf_cfg.h
+++ b/drivers/nand/include/amlnf_cfg.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __AML_NF_CFG_H__
#define __AML_NF_CFG_H__
diff --git a/drivers/nand/include/amlnf_ctrl.h b/drivers/nand/include/amlnf_ctrl.h
index fdb1a6a..f494278 100644
--- a/drivers/nand/include/amlnf_ctrl.h
+++ b/drivers/nand/include/amlnf_ctrl.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef AMLNAND_PHYDEV_H_INCLUDED
#define AMLNAND_PHYDEV_H_INCLUDED
diff --git a/drivers/nand/include/amlnf_dev.h b/drivers/nand/include/amlnf_dev.h
index ae98d5e..60e34a3 100644
--- a/drivers/nand/include/amlnf_dev.h
+++ b/drivers/nand/include/amlnf_dev.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __AML_NFTL_BLOCK_H
#define __AML_NFTL_BLOCK_H
diff --git a/drivers/nand/include/amlnf_type.h b/drivers/nand/include/amlnf_type.h
index 2925f2b..99edb8b 100644
--- a/drivers/nand/include/amlnf_type.h
+++ b/drivers/nand/include/amlnf_type.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __AML_NF_TYPE_H__
#define __AML_NF_TYPE_H__
diff --git a/drivers/nand/include/hw_ctrl.h b/drivers/nand/include/hw_ctrl.h
index 869b6a5..43bc7e0 100644
--- a/drivers/nand/include/hw_ctrl.h
+++ b/drivers/nand/include/hw_ctrl.h
@@ -1,3 +1,7 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __HW_CTRL_H__
#define __HW_CTRL_H__
diff --git a/drivers/nand/include/phynand.h b/drivers/nand/include/phynand.h
index cfc11c2..a45fdc6 100644
--- a/drivers/nand/include/phynand.h
+++ b/drivers/nand/include/phynand.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef PHYNAND_H_INCLUDED
#define PHYNAND_H_INCLUDED
diff --git a/drivers/nand/phy/amlnand_init.c b/drivers/nand/phy/amlnand_init.c
index 446bdcb..a064894 100644
--- a/drivers/nand/phy/amlnand_init.c
+++ b/drivers/nand/phy/amlnand_init.c
@@ -1,15 +1,7 @@
-/*****************************************************************
-**
-** Copyright (C) 2012 Amlogic,Inc. All rights reserved
-**
-** Filename : driver_uboot.c
-** Revision : 1.001
-** Author: Benjamin Zhao
-** Description:
-** amlnand_init, mainly init nand phy driver.
-**
-**
-*****************************************************************/
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include "../include/phynand.h"
#include <amlogic/secure_storage.h>
diff --git a/drivers/nand/phy/boot_operation.c b/drivers/nand/phy/boot_operation.c
index d0930eb..b9b5518 100644
--- a/drivers/nand/phy/boot_operation.c
+++ b/drivers/nand/phy/boot_operation.c
@@ -1,4 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include "../include/phynand.h"
diff --git a/drivers/nand/phy/chip.c b/drivers/nand/phy/chip.c
index ca2443d..46ed55b 100644
--- a/drivers/nand/phy/chip.c
+++ b/drivers/nand/phy/chip.c
@@ -1,15 +1,8 @@
-/*****************************************************************
-**
-** Copyright (C) 2012 Amlogic,Inc. All rights reserved
-**
-** Filename : chip.c
-** Revision : 1.001
-** Author: Benjamin Zhao
-** Description:
-** chip init/bbt/config/scan function, mainly for nand phy driver.
-**
-**
-*****************************************************************/
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include "../include/phynand.h"
int get_flash_type(struct amlnand_chip *aml_chip)
diff --git a/drivers/nand/phy/chip_operation.c b/drivers/nand/phy/chip_operation.c
index 4b6d6b1..5a9269a 100644
--- a/drivers/nand/phy/chip_operation.c
+++ b/drivers/nand/phy/chip_operation.c
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
-/*****************************************************************
-**
-** Copyright (C) 2012 Amlogic,Inc. All rights reserved
-**
-** Filename : chip_operation.c
-** Revision : 1.001
-** Author: Benjamin Zhao
-** Description:
-**chip operation function, contains read/write/erase, and bad block function.
-**mainly init nand phy driver.
-**
-*****************************************************************/
#include "../include/phynand.h"
extern int mt_L04A_nand_check(struct amlnand_chip *aml_chip);
extern int mt_L05B_nand_check(struct amlnand_chip *aml_chip);
diff --git a/drivers/nand/phy/chipenv.c b/drivers/nand/phy/chipenv.c
index ed4ba4f..e9b35fd 100644
--- a/drivers/nand/phy/chipenv.c
+++ b/drivers/nand/phy/chipenv.c
@@ -1,4 +1,7 @@
-
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include "../include/phynand.h"
diff --git a/drivers/nand/phy/cmd_utils.c b/drivers/nand/phy/cmd_utils.c
index 76bf2be..4e5f764 100644
--- a/drivers/nand/phy/cmd_utils.c
+++ b/drivers/nand/phy/cmd_utils.c
@@ -1,3 +1,7 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#include "../include/phynand.h"
extern int nand_hardreset(struct amlnand_chip *aml_chip, u8 chipnr);
diff --git a/drivers/nand/phy/hw_controller.c b/drivers/nand/phy/hw_controller.c
index e7907dc..147f6d2 100644
--- a/drivers/nand/phy/hw_controller.c
+++ b/drivers/nand/phy/hw_controller.c
@@ -1,15 +1,8 @@
-/*****************************************************************
-**
-** Copyright (C) 2012 Amlogic,Inc. All rights reserved
-**
-** Filename : hw_controller.c
-** Revision : 1.001
-** Author: Benjamin Zhao
-** Description:
-** hw controller operation function, mainly init nand phy driver.
-**
-**
-*****************************************************************/
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include "../include/phynand.h"
#include <asm/arch/secure_apb.h>
static int controller_select_chip(struct hw_controller *controller,
diff --git a/drivers/nand/phy/id_table.c b/drivers/nand/phy/id_table.c
index 194c1c1..faba119 100644
--- a/drivers/nand/phy/id_table.c
+++ b/drivers/nand/phy/id_table.c
@@ -1,15 +1,8 @@
-/*****************************************************************
-**
-** Copyright (C) 2012 Amlogic,Inc. All rights reserved
-**
-** Filename : id_table.c
-** Revision : 1.001
-** Author: Benjamin Zhao
-** Description:
-** all supported nand id table, provide nand flash basic information,
-** mainly init nand phy driver.
-**
-*****************************************************************/
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include "../include/phynand.h"
diff --git a/drivers/nand/phy/new_nand.c b/drivers/nand/phy/new_nand.c
index 90b438d..17463a3 100644
--- a/drivers/nand/phy/new_nand.c
+++ b/drivers/nand/phy/new_nand.c
@@ -1,15 +1,8 @@
-/*****************************************************************
-**
-** Copyright (C) 2012 Amlogic,Inc. All rights reserved
-**
-** Filename : retry_slc.c
-** Revision : 1.001
-** Author: Benjamin Zhao
-** Description:
-** read retry and enchance slc program function information,
-** mainly init nand phy driver.
-**
-*****************************************************************/
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include "../include/phynand.h"
static u8 pagelist_hynix256[128] = {
diff --git a/drivers/nand/phy/phydev.c b/drivers/nand/phy/phydev.c
index 8c58925..0480527 100644
--- a/drivers/nand/phy/phydev.c
+++ b/drivers/nand/phy/phydev.c
@@ -1,16 +1,8 @@
-/*****************************************************************
-**
-** Copyright (C) 2012 Amlogic,Inc. All rights reserved
-**
-** Filename : phydev.c
-** Revision : 1.001
-** Author: Benjamin Zhao
-** Description:
-** 1) Phydev basic operation based on phydev
-** contains read/write/erase/block_isbad/block_markbad.
-** 2) Get/release chip function ensure only one entry to nand chip;
-**
-*****************************************************************/
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include "../include/phynand.h"
#ifdef AML_NAND_UBOOT
diff --git a/drivers/net/Kconfig b/drivers/net/Kconfig
index af800d8..7044c6a 100644
--- a/drivers/net/Kconfig
+++ b/drivers/net/Kconfig
@@ -514,4 +514,3 @@
Ethernet Controller found on Freescale SoCs.
endif # NETDEVICES
-
diff --git a/drivers/net/designware.c b/drivers/net/designware.c
index 1d17b74..794da98 100644
--- a/drivers/net/designware.c
+++ b/drivers/net/designware.c
@@ -23,6 +23,44 @@
#include <asm/io.h>
#include <power/regulator.h>
#include "designware.h"
+#include <linux/ioport.h>
+
+#ifdef CONFIG_DM_ETH
+#include <asm/arch/pwr_ctrl.h>
+#include <asm/arch/register.h>
+#include <dm/pinctrl.h>
+#ifdef CONFIG_DM_GPIO
+#include <asm/gpio.h>
+#endif
+struct dw_eth_dev *priv_tool = NULL;
+struct phy_device *p_phydev = NULL;
+
+#ifndef ANACTRL_PLL_GATE_DIS
+#define ANACTRL_PLL_GATE_DIS 0xffffffff
+#endif
+
+#endif
+
+#define AML_ETH_PLL_CTL0 0x44
+#define AML_ETH_PLL_CTL1 0x48
+#define AML_ETH_PLL_CTL2 0x4C
+#define AML_ETH_PLL_CTL3 0x50
+#define AML_ETH_PLL_CTL4 0x54
+#define AML_ETH_PLL_CTL5 0x58
+#define AML_ETH_PLL_CTL6 0x5C
+#define AML_ETH_PLL_CTL7 0x60
+
+#define AML_ETH_PHY_CNTL0 0x80
+#define AML_ETH_PHY_CNTL1 0x84
+#define AML_ETH_PHY_CNTL2 0x88
+
+enum {
+ /* chip num */
+ ETH_PHY = 0x0,
+ ETH_PHY_C1 = 0x1,
+ ETH_PHY_C2 = 0x2,
+ ETH_PHY_SC2 = 0x3,
+};
static int dw_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
{
@@ -668,13 +706,28 @@
return 0;
}
+#ifdef CONFIG_DM_ETH
+unsigned int setup_amp;
+void setup_tx_amp(struct udevice *dev)
+{
+ unsigned int tx_amp_src = 0;
+ tx_amp_src = dev_read_u32_default(dev, "tx_amp_src", 0);
+ if (0 == tx_amp_src) {
+ printf("not set tx_amp_src\n");
+ } else {
+ setup_amp = readl((uintptr_t)tx_amp_src);
+ printf("addr 0x%x = 0x%x\n", tx_amp_src, readl((uintptr_t)tx_amp_src));
+ }
+}
static void setup_internal_phy(struct udevice *dev)
{
int phy_cntl1 = 0;
int mc_val = 0;
- int pll_val[3] = {0};
- int analog_val[3] = {0};
+ int chip_num = 0;
+ unsigned int pll_val[3] = {0};
+ unsigned int analog_val[3] = {0};
int rtn = 0;
+ struct resource eth_top, eth_cfg;
phy_cntl1 = dev_read_u32_default(dev, "phy_cntl1", 4);
if (phy_cntl1 < 0) {
@@ -686,6 +739,13 @@
printf("miss mc_val\n");
}
+ chip_num = dev_read_u32_default(dev, "chip_num", 4);
+ if (chip_num < 0) {
+ chip_num = 0;
+ printf("use 0 as default chip num\n");
+ }
+ printf("chip num %d\n", chip_num);
+
rtn = dev_read_u32_array(dev, "pll_val", pll_val, ARRAY_SIZE(pll_val));
if (rtn < 0) {
printf("miss pll_val\n");
@@ -703,72 +763,139 @@
for (int i = 0;i <3; i++) {
debug("analog_val 0x%08x\n", analog_val[i]);
}
- /*top*/
- setbits_le32(P_PREG_ETH_REG0, mc_val);
+ rtn = dev_read_resource_byname(dev, "eth_top", ð_top);
+ if (rtn) {
+ printf("can't get eth_top resource(ret = %d)\n", rtn);
+ }
+
+ rtn = dev_read_resource_byname(dev, "eth_cfg", ð_cfg);
+ if (rtn) {
+ printf("can't get eth_cfg resource(ret = %d)\n", rtn);
+ }
+// printf("wzh eth_top 0x%x eth_cfg 0x%x \n", eth_top.start, eth_cfg.start);
+
+ setup_tx_amp(dev);
+ /*top*/
+// setbits_le32(ETHTOP_CNTL0, mc_val);
+ setbits_le32(eth_top.start, mc_val);
/*pll*/
- writel(pll_val[0] | 0x30000000, P_ETH_PLL_CTL0);
- writel(pll_val[1], P_ETH_PLL_CTL1);
- writel(pll_val[2], P_ETH_PLL_CTL2);
- writel(0x00000000, P_ETH_PLL_CTL3);
+ writel(pll_val[0] | 0x30000000, eth_cfg.start + AML_ETH_PLL_CTL0);
+ writel(pll_val[1], eth_cfg.start + AML_ETH_PLL_CTL1);
+ writel(pll_val[2], eth_cfg.start + AML_ETH_PLL_CTL2);
+ writel(0x00000000, eth_cfg.start + AML_ETH_PLL_CTL3);
udelay(200);
- writel(pll_val[0] | 0x10000000, P_ETH_PLL_CTL0);
+ writel(pll_val[0] | 0x10000000, eth_cfg.start + AML_ETH_PLL_CTL0);
/*analog*/
- writel(analog_val[0], P_ETH_PLL_CTL5);
- writel(analog_val[1], P_ETH_PLL_CTL6);
- writel(analog_val[2], P_ETH_PLL_CTL7);
+ writel(analog_val[0], eth_cfg.start + AML_ETH_PLL_CTL5);
+ writel(analog_val[1], eth_cfg.start + AML_ETH_PLL_CTL6);
+ writel(analog_val[2], eth_cfg.start + AML_ETH_PLL_CTL7);
/*ctrl*/
/*config phyid should between a 0~0xffffffff*/
/*please don't use 44000181, this has been used by internal phy*/
- writel(0x33000180, P_ETH_PHY_CNTL0);
+ writel(0x33000180, eth_cfg.start + AML_ETH_PHY_CNTL0);
/*use_phy_smi | use_phy_ip | co_clkin from eth_phy_top*/
- writel(0x260, P_ETH_PHY_CNTL2);
- writel(phy_cntl1, P_ETH_PHY_CNTL1);
- writel(phy_cntl1 & (~0x40000), P_ETH_PHY_CNTL1);
- writel(phy_cntl1, P_ETH_PHY_CNTL1);
+ writel(0x260, eth_cfg.start + AML_ETH_PHY_CNTL2);
+ writel(phy_cntl1, eth_cfg.start + AML_ETH_PHY_CNTL1);
+ writel(phy_cntl1 & (~0x40000), eth_cfg.start + AML_ETH_PHY_CNTL1);
+ writel(phy_cntl1, eth_cfg.start + AML_ETH_PHY_CNTL1);
udelay(200);
- /* eth core clock */
- setbits_le32(HHI_GCLK_MPEG1, (0x1 << 3));
- /* eth phy clock */
- setbits_le32(HHI_GCLK_MPEG0, (0x1 << 4));
- /* eth phy pll, clk50m */
- setbits_le32(HHI_FIX_PLL_CNTL3, (0x1 << 5));
- /* power on memory */
- clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
-
+ if (chip_num != ETH_PHY_SC2) {
+ clrbits_le32(ANACTRL_PLL_GATE_DIS, (0x1 << 6));
+ clrbits_le32(ANACTRL_PLL_GATE_DIS, (0x1 << 7));
+ clrbits_le32(ANACTRL_PLL_GATE_DIS, (0x1 << 19));
+ }
}
static void setup_external_phy(struct udevice *dev)
{
- u32 mc_val;
+ int mc_val = 0;
+ int cali_val = 0;
+ int analog_ver = 0;
+ int chip_num = 0;
+ int rtn = 0;
+ struct resource eth_top, eth_cfg;
+ /*reset phy*/
+ struct gpio_desc desc;
+ int ret;
- /*driver strength*/
- writel(0xaaaaaaa5, P_PAD_DS_REG4A);
+ chip_num = dev_read_u32_default(dev, "chip_num", 4);
+ if (chip_num < 0) {
+ chip_num = 0;
+ printf("use 0 as default chip num\n");
+ }
+ printf("chip num %d\n", chip_num);
- /*pinmux*/
- writel(0x11111111, P_PERIPHS_PIN_MUX_6);
- writel(0x111111, P_PERIPHS_PIN_MUX_7);
+ if (chip_num != ETH_PHY_SC2) {
+ ret = gpio_request_by_name(dev, "reset-gpios", 0, &desc, GPIOD_IS_OUT);
+ if (ret) {
+ printf("request gpio failed!\n");
+ // return ret;
+ }
+ if (dm_gpio_is_valid(&desc)) {
+ dm_gpio_set_value(&desc, 1);
+ mdelay(100);
+ }
+ dm_gpio_free(dev, &desc);
+ }
- /*top*/
mc_val = dev_read_u32_default(dev, "mc_val", 4);
- debug("mc_val = 0x%x\n", mc_val);
- setbits_le32(P_PREG_ETH_REG0, mc_val);
+ if (mc_val < 0) {
+ printf("miss mc_val\n");
+ }
- /*switch to exphy*/
- writel(0x0, P_ETH_PHY_CNTL2);
- /*81*/
- setbits_le32(HHI_GCLK_MPEG1, 0x1 << 3);
- /* power on memory */
- clrbits_le32(HHI_MEM_PD_REG0, (1 << 3) | (1<<2));
+ cali_val = dev_read_u32_default(dev, "cali_val", 4);
+ if (mc_val < 0) {
+ printf("miss cali_val\n");
+ }
+ /*set rmii pinmux*/
+ if (mc_val & 0x4) {
+ pinctrl_select_state(dev, "external_eth_rmii_pins");
+ printf("set rmii\n");
+ }
+ /*set rgmii pinmux*/
+ if (mc_val & 0x1) {
+ pinctrl_select_state(dev, "external_eth_rgmii_pins");
+ printf("set rgmii\n");
+ }
+ rtn = dev_read_resource_byname(dev, "eth_top", ð_top);
+ if (rtn) {
+ printf("can't get eth_top resource(ret = %d)\n", rtn);
+ }
+
+ rtn = dev_read_resource_byname(dev, "eth_cfg", ð_cfg);
+ if (rtn) {
+ printf("can't get eth_cfg resource(ret = %d)\n", rtn);
+ }
+// printf("eth_top 0x%x eth_cfg 0x%x \n", eth_top.start, eth_cfg.start);
+
+ setbits_le32(eth_top.start, mc_val);
+ setbits_le32(eth_top.start + 4, cali_val);
+
+ analog_ver = dev_read_u32_default(dev, "analog_ver", 4);
+ if (mc_val < 0) {
+ printf("miss analog_ver\n");
+ }
+ if (analog_ver != 2)
+ writel(0x0, eth_cfg.start + AML_ETH_PHY_CNTL2);
+
+ if (chip_num != ETH_PHY_SC2) {
+ clrbits_le32(ANACTRL_PLL_GATE_DIS, (0x1 << 6));
+ clrbits_le32(ANACTRL_PLL_GATE_DIS, (0x1 << 7));
+ clrbits_le32(ANACTRL_PLL_GATE_DIS, (0x1 << 19));
+ }
}
+
+#endif
+#ifdef CONFIG_DM_ETH
static void __iomem *DM_network_interface_setup(struct udevice *dev)
{
- u32 internal_phy = 0;
+ int internal_phy = 0;
internal_phy = dev_read_u32_default(dev, "internal_phy", 1);
if (internal_phy < 0) {
@@ -783,8 +910,11 @@
setup_external_phy(dev);
}
udelay(1000);
+ return 0;
}
+#endif
/*parse dts end*/
+
int designware_eth_probe(struct udevice *dev)
{
struct eth_pdata *pdata = dev_get_platdata(dev);
@@ -794,8 +924,11 @@
int ret;
struct reset_ctl_bulk reset_bulk;
+#ifdef CONFIG_DM_ETH
+ printf("pwr up eth\n");
+ pwr_ctrl_psci_smc(PM_ETH, 1);
DM_network_interface_setup(dev);
-
+#endif
#ifdef CONFIG_CLK
int i, err, clock_nb;
@@ -876,6 +1009,9 @@
ret = dw_phy_init(priv, dev);
debug("%s, ret=%d\n", __func__, ret);
+#ifdef CONFIG_DM_ETH
+ priv_tool = priv;
+#endif
return ret;
#ifdef CONFIG_CLK
@@ -903,6 +1039,852 @@
#endif
}
+static void *eqos_alloc_descs(unsigned int num)
+{
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+ return (void *)noncached_alloc(EQOS_DESCRIPTORS_SIZE,
+ EQOS_DESCRIPTOR_ALIGN);
+#else
+ return memalign(EQOS_DESCRIPTOR_ALIGN, EQOS_DESCRIPTORS_SIZE);
+#endif
+}
+
+static void eqos_free_descs(void *descs)
+{
+#ifdef CONFIG_SYS_NONCACHED_MEMORY
+ /* FIXME: noncached_alloc() has no opposite */
+#else
+ free(descs);
+#endif
+}
+
+static int eqos_mdio_read(struct mii_dev *bus, int addr, int devad, int reg)
+{
+ struct eqos_mac_regs *mac_p = bus->priv;
+ ulong start;
+ u32 miiaddr;
+ int timeout = CONFIG_MDIO_TIMEOUT;
+ miiaddr = (((addr & 0x1f ) << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
+ ((reg & 0x1f) << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
+ (EQOS_MAC_MDIO_ADDRESS_CR_150_250 << EQOS_MAC_MDIO_ADDRESS_CR_SHIFT)|
+ (EQOS_MAC_MDIO_ADDRESS_GOC_READ << EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT));
+
+ writel(miiaddr | EQOS_MAC_MDIO_ADDRESS_GB, &mac_p->mdio_address);
+
+ start = get_timer(0);
+ while (get_timer(start) < timeout) {
+ if (!(readl(&mac_p->mdio_address) & EQOS_MAC_MDIO_ADDRESS_GB))
+ return readl(&mac_p->mdio_data);
+ udelay(10);
+ };
+ return -1;
+}
+
+static int eqos_mdio_write(struct mii_dev *bus, int addr, int devad, int reg,
+ u16 val)
+{
+ struct eqos_mac_regs *mac_p = bus->priv;
+ ulong start;
+ u32 miiaddr;
+ int ret = -1, timeout = CONFIG_MDIO_TIMEOUT;
+ writel(val, &mac_p->mdio_data);
+ miiaddr = (((addr & 0x1f ) << EQOS_MAC_MDIO_ADDRESS_PA_SHIFT) |
+ ((reg & 0x1f) << EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT) |
+ (EQOS_MAC_MDIO_ADDRESS_CR_150_250 << EQOS_MAC_MDIO_ADDRESS_CR_SHIFT)|
+ (EQOS_MAC_MDIO_ADDRESS_GOC_WRITE<< EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT));
+
+ writel(miiaddr | EQOS_MAC_MDIO_ADDRESS_GB, &mac_p->mdio_address);
+
+ start = get_timer(0);
+ while (get_timer(start) < timeout) {
+ if (!(readl(&mac_p->mdio_address) & EQOS_MAC_MDIO_ADDRESS_GB)) {
+ ret = 0;
+ break;
+ }
+ udelay(10);
+ };
+
+ return ret;
+}
+
+static int eqos_mdio_init(const char *name, void *mac_regs_p)
+{
+ struct mii_dev *bus = mdio_alloc();
+
+ if (!bus) {
+ printf("Failed to allocate MDIO bus\n");
+ return -1;
+ }
+
+ bus->read = eqos_mdio_read;
+ bus->write = eqos_mdio_write;
+ sprintf(bus->name, name);
+
+ bus->priv = (void *)mac_regs_p;
+
+ return mdio_register(bus);
+}
+
+static void eqos_inval_buffer(void *buf, size_t size)
+{
+ unsigned long start = (unsigned long)buf & ~(ARCH_DMA_MINALIGN - 1);
+ unsigned long end = ALIGN(start + size, ARCH_DMA_MINALIGN);
+
+ invalidate_dcache_range(start, end);
+}
+
+static void eqos_flush_buffer(void *buf, size_t size)
+{
+ flush_dcache_range((phys_addr_t)buf,
+ (phys_addr_t)((unsigned char *)buf+size));
+}
+
+static void eqos_inval_desc(void *desc)
+{
+#ifndef CONFIG_SYS_NONCACHED_MEMORY
+ unsigned long start = (unsigned long)desc & ~(ARCH_DMA_MINALIGN - 1);
+ unsigned long end = ALIGN(start + EQOS_DESCRIPTOR_SIZE,
+ ARCH_DMA_MINALIGN);
+
+ invalidate_dcache_range(start, end);
+#endif
+}
+
+static void eqos_flush_desc(void *desc)
+{
+#ifndef CONFIG_SYS_NONCACHED_MEMORY
+ flush_dcache_range((phys_addr_t)desc, (phys_addr_t)((unsigned char *)desc+EQOS_DESCRIPTOR_SIZE));
+#endif
+}
+
+static int eqos_set_full_duplex(struct udevice *dev)
+{
+ struct eqos_eth_dev *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ setbits_le32(&eqos->mac_regs_p->configuration, EQOS_MAC_CONFIGURATION_DM);
+
+ return 0;
+}
+
+static int eqos_set_half_duplex(struct udevice *dev)
+{
+ struct eqos_eth_dev *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ clrbits_le32(&eqos->mac_regs_p->configuration, EQOS_MAC_CONFIGURATION_DM);
+
+ /* WAR: Flush TX queue when switching to half-duplex */
+ setbits_le32(&eqos->mtl_regs_p->txq0_operation_mode,
+ EQOS_MTL_TXQ0_OPERATION_MODE_FTQ);
+
+ return 0;
+}
+
+static int eqos_set_gmii_speed(struct udevice *dev)
+{
+ struct eqos_eth_dev *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ clrbits_le32(&eqos->mac_regs_p->configuration,
+ EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
+
+ return 0;
+}
+
+static int eqos_set_mii_speed_100(struct udevice *dev)
+{
+ struct eqos_eth_dev *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ setbits_le32(&eqos->mac_regs_p->configuration,
+ EQOS_MAC_CONFIGURATION_PS | EQOS_MAC_CONFIGURATION_FES);
+
+ return 0;
+}
+
+static int eqos_set_mii_speed_10(struct udevice *dev)
+{
+ struct eqos_eth_dev *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ clrsetbits_le32(&eqos->mac_regs_p->configuration,
+ EQOS_MAC_CONFIGURATION_FES, EQOS_MAC_CONFIGURATION_PS);
+
+ return 0;
+}
+
+static int eqos_adjust_link(struct udevice *dev)
+{
+ struct eqos_eth_dev *eqos = dev_get_priv(dev);
+ int ret;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ if (eqos->phydev->duplex)
+ ret = eqos_set_full_duplex(dev);
+ else
+ ret = eqos_set_half_duplex(dev);
+ if (ret < 0) {
+ printf("eqos_set_*_duplex() failed: %d", ret);
+ return ret;
+ }
+
+ switch (eqos->phydev->speed) {
+ case SPEED_1000:
+ ret = eqos_set_gmii_speed(dev);
+ break;
+ case SPEED_100:
+ ret = eqos_set_mii_speed_100(dev);
+ break;
+ case SPEED_10:
+ ret = eqos_set_mii_speed_10(dev);
+ break;
+ default:
+ printf("invalid speed %d", eqos->phydev->speed);
+ return -EINVAL;
+ }
+ if (ret < 0) {
+ printf("eqos_set_*mii_speed*() failed: %d", ret);
+ return ret;
+ }
+
+ return 0;
+}
+
+static int eqos_write_hwaddr(struct udevice *dev)
+{
+ struct eth_pdata *plat = dev_get_platdata(dev);
+ struct eqos_eth_dev *eqos = dev_get_priv(dev);
+ u32 macid_lo, macid_hi;
+ u8 *mac_id = &plat->enetaddr[0];
+
+ macid_lo = mac_id[0] + (mac_id[1] << 8) + (mac_id[2] << 16) +
+ (mac_id[3] << 24);
+ macid_hi = mac_id[4] + (mac_id[5] << 8);
+
+ writel(macid_hi, &eqos->mac_regs_p->address0_high);
+ writel(macid_lo, &eqos->mac_regs_p->address0_low);
+
+ return 0;
+}
+
+static void eqos_stop(struct udevice *dev)
+{
+ struct eqos_eth_dev *eqos = dev_get_priv(dev);
+ int i;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ /* Disable TX DMA */
+ clrbits_le32(&eqos->dma_regs_p->ch0_tx_control,
+ EQOS_DMA_CH0_TX_CONTROL_ST);
+
+ /* Wait for TX all packets to drain out of MTL */
+ for (i = 0; i < 1000000; i++) {
+ u32 val = readl(&eqos->mtl_regs_p->txq0_debug);
+ u32 trcsts = (val >> EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT) &
+ EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK;
+ u32 txqsts = val & EQOS_MTL_TXQ0_DEBUG_TXQSTS;
+ if ((trcsts != 1) && (!txqsts))
+ break;
+ }
+
+ /* Turn off MAC TX and RX */
+ clrbits_le32(&eqos->mac_regs_p->configuration,
+ EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
+
+ /* Wait for all RX packets to drain out of MTL */
+ for (i = 0; i < 1000000; i++) {
+ u32 val = readl(&eqos->mtl_regs_p->rxq0_debug);
+ u32 prxq = (val >> EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT) &
+ EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK;
+ u32 rxqsts = (val >> EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT) &
+ EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK;
+ if ((!prxq) && (!rxqsts))
+ break;
+ }
+
+ /* Turn off RX DMA */
+ clrbits_le32(&eqos->dma_regs_p->ch0_rx_control,
+ EQOS_DMA_CH0_RX_CONTROL_SR);
+
+ if (eqos->phydev) {
+ phy_shutdown(eqos->phydev);
+ }
+
+ debug("%s: OK\n", __func__);
+}
+
+
+static int eqos_start(struct udevice *dev)
+{
+ struct eqos_eth_dev *eqos = dev_get_priv(dev);
+ int ret, i;
+ u32 val, tx_fifo_sz, rx_fifo_sz, tqs, rqs, pbl;
+ ulong last_rx_desc;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ eqos->tx_desc_idx = 0;
+ eqos->rx_desc_idx = 0;
+
+ setbits_le32(&eqos->dma_regs_p->mode,
+ EQOS_DMA_MODE_SWR);
+
+ ret = -1;
+
+ ret = phy_startup(eqos->phydev);
+ if (ret < 0) {
+ printf("phy_startup() failed: %d", ret);
+ goto err_shutdown_phy;
+ }
+ if (!eqos->phydev->link) {
+ printf("No link");
+ goto err_shutdown_phy;
+ }
+
+ ret = eqos_adjust_link(dev);
+ if (ret < 0) {
+ printf("eqos_adjust_link() failed: %d", ret);
+ goto err_shutdown_phy;
+ }
+
+ /* Configure MTL */
+
+ /* Enable Store and Forward mode for TX */
+ /* Program Tx operating mode */
+ setbits_le32(&eqos->mtl_regs_p->txq0_operation_mode,
+ EQOS_MTL_TXQ0_OPERATION_MODE_TSF |
+ (EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED <<
+ EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT));
+
+ /* Transmit Queue weight */
+ writel(0x10, &eqos->mtl_regs_p->txq0_quantum_weight);
+
+ /* Enable Store and Forward mode for RX, since no jumbo frame */
+ setbits_le32(&eqos->mtl_regs_p->rxq0_operation_mode,
+ EQOS_MTL_RXQ0_OPERATION_MODE_RSF);
+
+ /* Transmit/Receive queue fifo size; use all RAM for 1 queue */
+ val = readl(&eqos->mac_regs_p->hw_feature1);
+ tx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT) &
+ EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK;
+ rx_fifo_sz = (val >> EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT) &
+ EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK;
+
+ /*
+ * r/tx_fifo_sz is encoded as log2(n / 128). Undo that by shifting.
+ * r/tqs is encoded as (n / 256) - 1.
+ */
+ tqs = (128 << tx_fifo_sz) / 256 - 1;
+ rqs = (128 << rx_fifo_sz) / 256 - 1;
+
+ clrsetbits_le32(&eqos->mtl_regs_p->txq0_operation_mode,
+ EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK <<
+ EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT,
+ tqs << EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT);
+ clrsetbits_le32(&eqos->mtl_regs_p->rxq0_operation_mode,
+ EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK <<
+ EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT,
+ rqs << EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT);
+
+ /* Flow control used only if each channel gets 4KB or more FIFO */
+ if (rqs >= ((4096 / 256) - 1)) {
+ u32 rfd, rfa;
+
+ setbits_le32(&eqos->mtl_regs_p->rxq0_operation_mode,
+ EQOS_MTL_RXQ0_OPERATION_MODE_EHFC);
+
+ /*
+ * Set Threshold for Activating Flow Contol space for min 2
+ * frames ie, (1500 * 1) = 1500 bytes.
+ *
+ * Set Threshold for Deactivating Flow Contol for space of
+ * min 1 frame (frame size 1500bytes) in receive fifo
+ */
+ if (rqs == ((4096 / 256) - 1)) {
+ /*
+ * This violates the above formula because of FIFO size
+ * limit therefore overflow may occur inspite of this.
+ */
+ rfd = 0x3; /* Full-3K */
+ rfa = 0x1; /* Full-1.5K */
+ } else if (rqs == ((8192 / 256) - 1)) {
+ rfd = 0x6; /* Full-4K */
+ rfa = 0xa; /* Full-6K */
+ } else if (rqs == ((16384 / 256) - 1)) {
+ rfd = 0x6; /* Full-4K */
+ rfa = 0x12; /* Full-10K */
+ } else {
+ rfd = 0x6; /* Full-4K */
+ rfa = 0x1E; /* Full-16K */
+ }
+
+ clrsetbits_le32(&eqos->mtl_regs_p->rxq0_operation_mode,
+ (EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK <<
+ EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
+ (EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK <<
+ EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT),
+ (rfd <<
+ EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT) |
+ (rfa <<
+ EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT));
+ }
+
+ /* Configure MAC */
+
+ clrsetbits_le32(&eqos->mac_regs_p->rxq_ctrl0,
+ EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK <<
+ EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT,
+ EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB <<
+ EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT);
+
+ /* Set TX flow control parameters */
+ /* Set Pause Time */
+ setbits_le32(&eqos->mac_regs_p->q0_tx_flow_ctrl,
+ 0xffff << EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT);
+ /* Assign priority for TX flow control */
+ clrbits_le32(&eqos->mac_regs_p->txq_prty_map0,
+ EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK <<
+ EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT);
+ /* Assign priority for RX flow control */
+ clrbits_le32(&eqos->mac_regs_p->rxq_ctrl2,
+ EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK <<
+ EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT);
+ /* Enable flow control */
+ setbits_le32(&eqos->mac_regs_p->q0_tx_flow_ctrl,
+ EQOS_MAC_Q0_TX_FLOW_CTRL_TFE);
+ setbits_le32(&eqos->mac_regs_p->rx_flow_ctrl,
+ EQOS_MAC_RX_FLOW_CTRL_RFE);
+
+ clrsetbits_le32(&eqos->mac_regs_p->configuration,
+ EQOS_MAC_CONFIGURATION_GPSLCE |
+ EQOS_MAC_CONFIGURATION_WD |
+ EQOS_MAC_CONFIGURATION_JD |
+ EQOS_MAC_CONFIGURATION_JE,
+ EQOS_MAC_CONFIGURATION_CST |
+ EQOS_MAC_CONFIGURATION_ACS);
+
+ eqos_write_hwaddr(dev);
+
+ /* Configure DMA */
+
+ /* Enable OSP mode */
+ setbits_le32(&eqos->dma_regs_p->ch0_tx_control,
+ EQOS_DMA_CH0_TX_CONTROL_OSP);
+
+ /* RX buffer size. Must be a multiple of bus width */
+ clrsetbits_le32(&eqos->dma_regs_p->ch0_rx_control,
+ EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK <<
+ EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT,
+ EQOS_MAX_PACKET_SIZE <<
+ EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT);
+
+ setbits_le32(&eqos->dma_regs_p->ch0_control,
+ EQOS_DMA_CH0_CONTROL_PBLX8);
+
+ /*
+ * Burst length must be < 1/2 FIFO size.
+ * FIFO size in tqs is encoded as (n / 256) - 1.
+ * Each burst is n * 8 (PBLX8) * 16 (AXI width) == 128 bytes.
+ * Half of n * 256 is n * 128, so pbl == tqs, modulo the -1.
+ */
+ pbl = tqs + 1;
+ if (pbl > 32)
+ pbl = 32;
+ clrsetbits_le32(&eqos->dma_regs_p->ch0_tx_control,
+ EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK <<
+ EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT,
+ pbl << EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT);
+
+ clrsetbits_le32(&eqos->dma_regs_p->ch0_rx_control,
+ EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK <<
+ EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT,
+ 8 << EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT);
+
+ /* DMA performance configuration */
+ val = (2 << EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT) |
+ EQOS_DMA_SYSBUS_MODE_EAME | EQOS_DMA_SYSBUS_MODE_BLEN16 |
+ EQOS_DMA_SYSBUS_MODE_BLEN8 | EQOS_DMA_SYSBUS_MODE_BLEN4;
+ writel(val, &eqos->dma_regs_p->sysbus_mode);
+
+ /* Set up descriptors */
+
+ memset(eqos->descs, 0, EQOS_DESCRIPTORS_SIZE);
+
+ for (i = 0; i < EQOS_DESCRIPTORS_RX; i++) {
+ struct eqos_desc *rx_desc = &(eqos->rx_descs[i]);
+ rx_desc->des0 = (u32)(ulong)(eqos->rx_dma_buf +
+ (i * EQOS_MAX_PACKET_SIZE));
+ rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
+ }
+
+ flush_dcache_range((phys_addr_t)eqos->descs, (phys_addr_t)((unsigned char *)eqos->descs + EQOS_DESCRIPTORS_SIZE));
+ flush_dcache_range((phys_addr_t)eqos->rx_dma_buf, (phys_addr_t)((unsigned char *)eqos->rx_dma_buf + EQOS_DESCRIPTORS_RX*EQOS_MAX_PACKET_SIZE));
+
+ writel(0, &eqos->dma_regs_p->ch0_txdesc_list_haddress);
+ writel((ulong)eqos->tx_descs, &eqos->dma_regs_p->ch0_txdesc_list_address);
+ writel(EQOS_DESCRIPTORS_TX - 1,
+ &eqos->dma_regs_p->ch0_txdesc_ring_length);
+
+ writel(0, &eqos->dma_regs_p->ch0_rxdesc_list_haddress);
+ writel((ulong)eqos->rx_descs, &eqos->dma_regs_p->ch0_rxdesc_list_address);
+ writel(EQOS_DESCRIPTORS_RX - 1,
+ &eqos->dma_regs_p->ch0_rxdesc_ring_length);
+
+ /* Enable everything */
+
+ setbits_le32(&eqos->mac_regs_p->configuration,
+ EQOS_MAC_CONFIGURATION_TE | EQOS_MAC_CONFIGURATION_RE);
+
+ setbits_le32(&eqos->dma_regs_p->ch0_tx_control,
+ EQOS_DMA_CH0_TX_CONTROL_ST);
+ setbits_le32(&eqos->dma_regs_p->ch0_rx_control,
+ EQOS_DMA_CH0_RX_CONTROL_SR);
+
+ /* TX tail pointer not written until we need to TX a packet */
+ /*
+ * Point RX tail pointer at last descriptor. Ideally, we'd point at the
+ * first descriptor, implying all descriptors were available. However,
+ * that's not distinguishable from none of the descriptors being
+ * available.
+ */
+ last_rx_desc = (ulong)&(eqos->rx_descs[(EQOS_DESCRIPTORS_RX - 1)]);
+ writel(last_rx_desc, &eqos->dma_regs_p->ch0_rxdesc_tail_pointer);
+
+ return 0;
+
+err_shutdown_phy:
+ phy_shutdown(eqos->phydev);
+// eqos->phydev = NULL;
+ printf("eth init FAILED\n");
+ return ret;
+}
+
+static int eqos_send(struct udevice *dev, void *packet, int length)
+{
+ struct eqos_eth_dev *eqos = dev_get_priv(dev);
+ struct eqos_desc *tx_desc;
+ int i;
+
+ debug("%s(dev=%p, packet=%p, length=%d):\n", __func__, dev, packet,
+ length);
+
+ memcpy(eqos->tx_dma_buf, packet, length);
+ eqos_flush_buffer(eqos->tx_dma_buf, length);
+
+ tx_desc = &(eqos->tx_descs[eqos->tx_desc_idx]);
+ eqos_inval_desc(tx_desc);
+ eqos->tx_desc_idx++;
+ eqos->tx_desc_idx %= EQOS_DESCRIPTORS_TX;
+
+ tx_desc->des0 = (ulong)eqos->tx_dma_buf;
+ tx_desc->des1 = 0;
+ tx_desc->des2 = length;
+ /*
+ * Make sure that if HW sees the _OWN write below, it will see all the
+ * writes to the rest of the descriptor too.
+ */
+ mb();
+ tx_desc->des3 = EQOS_DESC3_OWN | EQOS_DESC3_FD | EQOS_DESC3_LD | length;
+ eqos_flush_desc(tx_desc);
+
+ writel((ulong)(tx_desc + 1), &eqos->dma_regs_p->ch0_txdesc_tail_pointer);
+
+ for (i = 0; i < 1000000; i++) {
+ eqos_inval_desc(tx_desc);
+ if (!(readl(&tx_desc->des3) & EQOS_DESC3_OWN)) {
+ return 0;
+ }
+ udelay(1);
+ }
+
+ printf("%s: TX timeout\n", __func__);
+
+ return -ETIMEDOUT;
+}
+
+static int eqos_recv(struct udevice *dev, int flags, uchar **packetp)
+{
+ struct eqos_eth_dev *eqos = dev_get_priv(dev);
+ struct eqos_desc *rx_desc;
+ int length;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
+ eqos_inval_desc(rx_desc);
+ if (rx_desc->des3 & EQOS_DESC3_OWN) {
+ debug("%s: RX packet not available\n", __func__);
+ return -EAGAIN;
+ }
+
+ *packetp = eqos->rx_dma_buf +
+ (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
+ length = rx_desc->des3 & 0x7fff;
+ debug("%s: *packetp=%p, length=%d\n", __func__, *packetp, length);
+
+ eqos_inval_buffer(*packetp, length);
+
+ return length;
+}
+
+int eqos_free_pkt(struct udevice *dev, uchar *packet, int length)
+{
+ struct eqos_eth_dev *eqos = dev_get_priv(dev);
+ uchar *packet_expected;
+ struct eqos_desc *rx_desc;
+
+ debug("%s(packet=%p, length=%d)\n", __func__, packet, length);
+
+ packet_expected = eqos->rx_dma_buf +
+ (eqos->rx_desc_idx * EQOS_MAX_PACKET_SIZE);
+ if (packet != packet_expected) {
+ debug("%s: Unexpected packet (expected %p)\n", __func__,
+ packet_expected);
+ return -EINVAL;
+ }
+
+ rx_desc = &(eqos->rx_descs[eqos->rx_desc_idx]);
+ rx_desc->des0 = (u32)(ulong)packet;
+ rx_desc->des1 = 0;
+ rx_desc->des2 = 0;
+ /*
+ * Make sure that if HW sees the _OWN write below, it will see all the
+ * writes to the rest of the descriptor too.
+ */
+ mb();
+ rx_desc->des3 |= EQOS_DESC3_OWN | EQOS_DESC3_BUF1V;
+ eqos_flush_desc(rx_desc);
+
+ writel((ulong)rx_desc, &eqos->dma_regs_p->ch0_rxdesc_tail_pointer);
+
+ eqos->rx_desc_idx++;
+ eqos->rx_desc_idx %= EQOS_DESCRIPTORS_RX;
+
+ return 0;
+}
+
+static int eqos_probe_resources_core(struct udevice * dev)
+{
+ struct eqos_eth_dev *eqos = dev_get_priv(dev);
+ int ret;
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ eqos->descs = eqos_alloc_descs(EQOS_DESCRIPTORS_TX +
+ EQOS_DESCRIPTORS_RX);
+ if (!eqos->descs) {
+ debug("%s: eqos_alloc_descs() failed\n", __func__);
+ ret = -ENOMEM;
+ goto err;
+ }
+ eqos->tx_descs = (struct eqos_desc *)eqos->descs;
+ eqos->rx_descs = (eqos->tx_descs + EQOS_DESCRIPTORS_TX);
+ debug("%s: tx_descs=%p, rx_descs=%p\n", __func__, eqos->tx_descs,
+ eqos->rx_descs);
+
+ eqos->tx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_MAX_PACKET_SIZE);
+ if (!eqos->tx_dma_buf) {
+ debug("%s: memalign(tx_dma_buf) failed\n", __func__);
+ ret = -ENOMEM;
+ goto err_free_descs;
+ }
+ debug("%s: rx_dma_buf=%p\n", __func__, eqos->rx_dma_buf);
+
+ eqos->rx_dma_buf = memalign(EQOS_BUFFER_ALIGN, EQOS_RX_BUFFER_SIZE);
+ if (!eqos->rx_dma_buf) {
+ debug("%s: memalign(rx_dma_buf) failed\n", __func__);
+ ret = -ENOMEM;
+ goto err_free_tx_dma_buf;
+ }
+ debug("%s: tx_dma_buf=%p\n", __func__, eqos->tx_dma_buf);
+
+ eqos->rx_pkt = malloc(EQOS_MAX_PACKET_SIZE);
+ if (!eqos->rx_pkt) {
+ debug("%s: malloc(rx_pkt) failed\n", __func__);
+ ret = -ENOMEM;
+ goto err_free_rx_dma_buf;
+ }
+ debug("%s: rx_pkt=%p\n", __func__, eqos->rx_pkt);
+
+ debug("%s: OK\n", __func__);
+ return 0;
+
+err_free_rx_dma_buf:
+ free(eqos->rx_dma_buf);
+err_free_tx_dma_buf:
+ free(eqos->tx_dma_buf);
+err_free_descs:
+ eqos_free_descs(eqos->descs);
+err:
+
+ debug("%s: returns %d\n", __func__, ret);
+ return ret;
+}
+
+static int eqos_remove_resources_core(struct udevice *dev)
+{
+ struct eqos_eth_dev *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ free(eqos->rx_pkt);
+ free(eqos->rx_dma_buf);
+ free(eqos->tx_dma_buf);
+ eqos_free_descs(eqos->descs);
+
+ debug("%s: OK\n", __func__);
+ return 0;
+}
+
+static int eqos_phy_init(struct udevice *dev)
+{
+ struct eqos_eth_dev *eqos = dev_get_priv(dev);
+ struct phy_device *phydev;
+ int mask = 0xffffffff;
+
+#ifdef CONFIG_PHY_ADDR
+ mask = 1 << CONFIG_PHY_ADDR;
+#endif
+
+ phydev = phy_find_by_mask(eqos->bus, mask, eqos->interface);
+ if (!phydev)
+ return -1;
+
+ phy_connect_dev(phydev, dev);
+
+ phydev->supported &= PHY_GBIT_FEATURES;
+ phydev->advertising = phydev->supported;
+
+ eqos->phydev = phydev;
+ p_phydev = phydev;
+ phy_config(phydev);
+
+ return 0;
+}
+
+// from eqos_initialize(ulong base_addr, u32 interface)
+int eqos_probe(struct udevice *dev)
+{
+ struct eqos_eth_dev *eqos = dev_get_priv(dev);
+ ulong base_addr;
+ int ret;
+
+#ifdef CONFIG_DM_ETH
+ printf("pwr up eth\n");
+ pwr_ctrl_psci_smc(PM_ETH, 1);
+ DM_network_interface_setup(dev);
+#endif
+
+ eqos->dev = dev;
+
+ base_addr = devfdt_get_addr(dev);
+ if (base_addr == FDT_ADDR_T_NONE) {
+ pr_err("devfdt_get_addr() failed");
+ return -ENODEV;
+ }
+
+ eqos->mac_regs_p = (void *)base_addr;
+ eqos->mtl_regs_p = (void *)(base_addr + EQOS_MTL_REGS_BASE);
+ eqos->dma_regs_p = (void *)(base_addr + EQOS_DMA_REGS_BASE);
+
+ ret = eqos_probe_resources_core(dev);
+
+ eqos->interface = 0;
+
+ eqos_mdio_init((char *)dev->name, eqos->mac_regs_p);
+ eqos->bus = miiphy_get_dev_by_name(dev->name);
+ ret = eqos_phy_init(dev);
+ if (ret < 0) {
+ pr_err("eqos_phy_init() failed");
+ return -ENODEV;
+ }
+
+ return 0;
+}
+
+static int eqos_remove(struct udevice *dev)
+{
+ struct eqos_eth_dev *eqos = dev_get_priv(dev);
+
+ debug("%s(dev=%p):\n", __func__, dev);
+
+ free(eqos->phydev);
+ mdio_unregister(eqos->bus);
+ mdio_free(eqos->bus);
+ eqos_remove_resources_core(dev);
+
+ debug("%s: OK\n", __func__);
+ return 0;
+}
+
+/* amlogic debug cmd start */
+/*********************ethernet debug function****************************/
+static int do_phyreg(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
+{
+ unsigned int reg, value;
+ unsigned char *cmd = NULL;
+ unsigned int i;
+
+ if (argc < 2) {
+ return cmd_usage(cmdtp);
+ }
+
+ if (p_phydev != NULL)
+ priv_tool->phydev = p_phydev;
+// if (priv_tool == NULL || priv_tool->phydev == NULL) {
+// return -1;
+// }
+
+ cmd = (unsigned char *)argv[1];
+ switch (*cmd) {
+ case 'd':
+ printf("=== ethernet phy register dump:\n");
+ for (i = 0; i < 32; i++)
+ printf("[reg_%d] 0x%x\n", i, phy_read(priv_tool->phydev, MDIO_DEVAD_NONE, i));
+ break;
+ case 'r':
+ if (argc != 3) {
+ return cmd_usage(cmdtp);
+ }
+ printf("=== ethernet phy register read:\n");
+ reg = simple_strtoul(argv[2], NULL, 10);
+ printf("[reg_%d] 0x%x\n", reg, phy_read(priv_tool->phydev, MDIO_DEVAD_NONE, reg));
+
+ break;
+ case 'w':
+ if (argc != 4) {
+ return cmd_usage(cmdtp);
+ }
+ printf("=== ethernet phy register write:\n");
+ reg = simple_strtoul(argv[2], NULL, 10);
+ value = simple_strtoul(argv[3], NULL, 16);
+ phy_write(priv_tool->phydev, MDIO_DEVAD_NONE, reg, value);
+ printf("[reg_%d] 0x%x\n", reg, phy_read(priv_tool->phydev, MDIO_DEVAD_NONE, reg));
+ break;
+
+ default:
+ return cmd_usage(cmdtp);
+ }
+
+ return 0;
+}
+
+U_BOOT_CMD(
+ phyreg, 4, 1, do_phyreg,
+ "ethernet phy register read/write/dump",
+ "d - dump phy registers\n"
+ " r reg - read phy register\n"
+ " w reg val - write phy register"
+);
+
const struct eth_ops designware_eth_ops = {
.start = designware_eth_start,
.send = designware_eth_send,
@@ -912,6 +1894,15 @@
.write_hwaddr = designware_eth_write_hwaddr,
};
+const struct eth_ops eqos_ops = {
+ .start = eqos_start,
+ .send = eqos_send,
+ .recv = eqos_recv,
+ .free_pkt = eqos_free_pkt,
+ .stop = eqos_stop,
+ .write_hwaddr = eqos_write_hwaddr,
+};
+
int designware_eth_ofdata_to_platdata(struct udevice *dev)
{
struct dw_eth_pdata *dw_pdata = dev_get_platdata(dev);
@@ -980,6 +1971,22 @@
.flags = DM_FLAG_ALLOC_PRIV_DMA,
};
+static const struct udevice_id eth_qos_ids[] = {
+ { .compatible = "amlogic,t7-eth-dwmac" },
+ { }
+};
+
+U_BOOT_DRIVER(eth_qos) = {
+ .name = "eth_qos",
+ .id = UCLASS_ETH,
+ .of_match = eth_qos_ids,
+ .probe = eqos_probe,
+ .remove = eqos_remove,
+ .ops = &eqos_ops,
+ .priv_auto_alloc_size = sizeof(struct eqos_eth_dev),
+ .platdata_auto_alloc_size = sizeof(struct eth_pdata),
+};
+
static struct pci_device_id supported[] = {
{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_QRK_EMAC) },
{ }
diff --git a/drivers/net/designware.h b/drivers/net/designware.h
index dea12b7..9e6b9ce 100644
--- a/drivers/net/designware.h
+++ b/drivers/net/designware.h
@@ -267,4 +267,205 @@
int designware_eth_write_hwaddr(struct udevice *dev);
#endif
+struct eqos_mac_regs {
+ uint32_t configuration; /* 0x000 */
+ uint32_t unused_004[(0x070 - 0x004) / 4]; /* 0x004 */
+ uint32_t q0_tx_flow_ctrl; /* 0x070 */
+ uint32_t unused_070[(0x090 - 0x074) / 4]; /* 0x074 */
+ uint32_t rx_flow_ctrl; /* 0x090 */
+ uint32_t unused_094; /* 0x094 */
+ uint32_t txq_prty_map0; /* 0x098 */
+ uint32_t unused_09c; /* 0x09c */
+ uint32_t rxq_ctrl0; /* 0x0a0 */
+ uint32_t unused_0a4; /* 0x0a4 */
+ uint32_t rxq_ctrl2; /* 0x0a8 */
+ uint32_t unused_0ac[(0x0dc - 0x0ac) / 4]; /* 0x0ac */
+ uint32_t us_tic_counter; /* 0x0dc */
+ uint32_t unused_0e0[(0x11c - 0x0e0) / 4]; /* 0x0e0 */
+ uint32_t hw_feature0; /* 0x11c */
+ uint32_t hw_feature1; /* 0x120 */
+ uint32_t hw_feature2; /* 0x124 */
+ uint32_t unused_128[(0x200 - 0x128) / 4]; /* 0x128 */
+ uint32_t mdio_address; /* 0x200 */
+ uint32_t mdio_data; /* 0x204 */
+ uint32_t unused_208[(0x300 - 0x208) / 4]; /* 0x208 */
+ uint32_t address0_high; /* 0x300 */
+ uint32_t address0_low; /* 0x304 */
+};
+
+#define EQOS_MAC_CONFIGURATION_GPSLCE BIT(23)
+#define EQOS_MAC_CONFIGURATION_CST BIT(21)
+#define EQOS_MAC_CONFIGURATION_ACS BIT(20)
+#define EQOS_MAC_CONFIGURATION_WD BIT(19)
+#define EQOS_MAC_CONFIGURATION_JD BIT(17)
+#define EQOS_MAC_CONFIGURATION_JE BIT(16)
+#define EQOS_MAC_CONFIGURATION_PS BIT(15)
+#define EQOS_MAC_CONFIGURATION_FES BIT(14)
+#define EQOS_MAC_CONFIGURATION_DM BIT(13)
+#define EQOS_MAC_CONFIGURATION_TE BIT(1)
+#define EQOS_MAC_CONFIGURATION_RE BIT(0)
+
+#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_SHIFT 16
+#define EQOS_MAC_Q0_TX_FLOW_CTRL_PT_MASK 0xffff
+#define EQOS_MAC_Q0_TX_FLOW_CTRL_TFE BIT(1)
+
+#define EQOS_MAC_RX_FLOW_CTRL_RFE BIT(0)
+
+#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_SHIFT 0
+#define EQOS_MAC_TXQ_PRTY_MAP0_PSTQ0_MASK 0xff
+
+#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_SHIFT 0
+#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_MASK 3
+#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_NOT_ENABLED 0
+#define EQOS_MAC_RXQ_CTRL0_RXQ0EN_ENABLED_DCB 2
+
+#define EQOS_MAC_RXQ_CTRL2_PSRQ0_SHIFT 0
+#define EQOS_MAC_RXQ_CTRL2_PSRQ0_MASK 0xff
+
+#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_SHIFT 6
+#define EQOS_MAC_HW_FEATURE1_TXFIFOSIZE_MASK 0x1f
+#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_SHIFT 0
+#define EQOS_MAC_HW_FEATURE1_RXFIFOSIZE_MASK 0x1f
+
+#define EQOS_MAC_MDIO_ADDRESS_PA_SHIFT 21
+#define EQOS_MAC_MDIO_ADDRESS_RDA_SHIFT 16
+#define EQOS_MAC_MDIO_ADDRESS_CR_SHIFT 8
+#define EQOS_MAC_MDIO_ADDRESS_CR_20_35 2
+#define EQOS_MAC_MDIO_ADDRESS_CR_150_250 4
+#define EQOS_MAC_MDIO_ADDRESS_SKAP BIT(4)
+#define EQOS_MAC_MDIO_ADDRESS_GOC_SHIFT 2
+#define EQOS_MAC_MDIO_ADDRESS_GOC_READ 3
+#define EQOS_MAC_MDIO_ADDRESS_GOC_WRITE 1
+#define EQOS_MAC_MDIO_ADDRESS_C45E BIT(1)
+#define EQOS_MAC_MDIO_ADDRESS_GB 1
+
+#define EQOS_MAC_MDIO_DATA_GD_MASK 0xffff
+
+#define EQOS_MTL_REGS_BASE 0xd00
+struct eqos_mtl_regs {
+ uint32_t txq0_operation_mode; /* 0xd00 */
+ uint32_t unused_d04; /* 0xd04 */
+ uint32_t txq0_debug; /* 0xd08 */
+ uint32_t unused_d0c[(0xd18 - 0xd0c) / 4]; /* 0xd0c */
+ uint32_t txq0_quantum_weight; /* 0xd18 */
+ uint32_t unused_d1c[(0xd30 - 0xd1c) / 4]; /* 0xd1c */
+ uint32_t rxq0_operation_mode; /* 0xd30 */
+ uint32_t unused_d34; /* 0xd34 */
+ uint32_t rxq0_debug; /* 0xd38 */
+ //uint32_t rxq0_cntl; /* 0xd3C */
+};
+
+#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_SHIFT 16
+#define EQOS_MTL_TXQ0_OPERATION_MODE_TQS_MASK 0x1ff
+#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_SHIFT 2
+#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_MASK 3
+#define EQOS_MTL_TXQ0_OPERATION_MODE_TXQEN_ENABLED 2
+#define EQOS_MTL_TXQ0_OPERATION_MODE_TSF BIT(1)
+#define EQOS_MTL_TXQ0_OPERATION_MODE_FTQ BIT(0)
+
+#define EQOS_MTL_TXQ0_DEBUG_TXQSTS BIT(4)
+#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_SHIFT 1
+#define EQOS_MTL_TXQ0_DEBUG_TRCSTS_MASK 3
+
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_SHIFT 20
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RQS_MASK 0x3ff
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_SHIFT 14
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RFD_MASK 0x3f
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_SHIFT 8
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RFA_MASK 0x3f
+#define EQOS_MTL_RXQ0_OPERATION_MODE_EHFC BIT(7)
+#define EQOS_MTL_RXQ0_OPERATION_MODE_RSF BIT(5)
+
+#define EQOS_MTL_RXQ0_DEBUG_PRXQ_SHIFT 16
+#define EQOS_MTL_RXQ0_DEBUG_PRXQ_MASK 0x7fff
+#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_SHIFT 4
+#define EQOS_MTL_RXQ0_DEBUG_RXQSTS_MASK 3
+
+#define EQOS_DMA_REGS_BASE 0x1000
+struct eqos_dma_regs {
+ uint32_t mode; /* 0x1000 */
+ uint32_t sysbus_mode; /* 0x1004 */
+ uint32_t unused_1008[(0x1100 - 0x1008) / 4]; /* 0x1008 */
+ uint32_t ch0_control; /* 0x1100 */
+ uint32_t ch0_tx_control; /* 0x1104 */
+ uint32_t ch0_rx_control; /* 0x1108 */
+ uint32_t unused_110c; /* 0x110c */
+ uint32_t ch0_txdesc_list_haddress; /* 0x1110 */
+ uint32_t ch0_txdesc_list_address; /* 0x1114 */
+ uint32_t ch0_rxdesc_list_haddress; /* 0x1118 */
+ uint32_t ch0_rxdesc_list_address; /* 0x111c */
+ uint32_t ch0_txdesc_tail_pointer; /* 0x1120 */
+ uint32_t unused_1124; /* 0x1124 */
+ uint32_t ch0_rxdesc_tail_pointer; /* 0x1128 */
+ uint32_t ch0_txdesc_ring_length; /* 0x112c */
+ uint32_t ch0_rxdesc_ring_length; /* 0x1130 */
+};
+
+#define EQOS_DMA_MODE_SWR BIT(0)
+
+#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_SHIFT 16
+#define EQOS_DMA_SYSBUS_MODE_RD_OSR_LMT_MASK 0xf
+#define EQOS_DMA_SYSBUS_MODE_EAME BIT(11)
+#define EQOS_DMA_SYSBUS_MODE_BLEN16 BIT(3)
+#define EQOS_DMA_SYSBUS_MODE_BLEN8 BIT(2)
+#define EQOS_DMA_SYSBUS_MODE_BLEN4 BIT(1)
+
+#define EQOS_DMA_CH0_CONTROL_PBLX8 BIT(16)
+
+#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_SHIFT 16
+#define EQOS_DMA_CH0_TX_CONTROL_TXPBL_MASK 0x3f
+#define EQOS_DMA_CH0_TX_CONTROL_OSP BIT(4)
+#define EQOS_DMA_CH0_TX_CONTROL_ST BIT(0)
+
+#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_SHIFT 16
+#define EQOS_DMA_CH0_RX_CONTROL_RXPBL_MASK 0x3f
+#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_SHIFT 1
+#define EQOS_DMA_CH0_RX_CONTROL_RBSZ_MASK 0x3fff
+#define EQOS_DMA_CH0_RX_CONTROL_SR BIT(0)
+
+
+/* Descriptors */
+
+#define EQOS_DESCRIPTOR_WORDS 4
+#define EQOS_DESCRIPTOR_SIZE (EQOS_DESCRIPTOR_WORDS * 4)
+/* We assume ARCH_DMA_MINALIGN >= 16; 16 is the EQOS HW minimum */
+#define EQOS_DESCRIPTOR_ALIGN ARCH_DMA_MINALIGN
+#define EQOS_DESCRIPTORS_TX 4
+#define EQOS_DESCRIPTORS_RX 4
+#define EQOS_DESCRIPTORS_NUM (EQOS_DESCRIPTORS_TX + EQOS_DESCRIPTORS_RX)
+#define EQOS_DESCRIPTORS_SIZE ALIGN(EQOS_DESCRIPTORS_NUM * \
+ EQOS_DESCRIPTOR_SIZE, ARCH_DMA_MINALIGN)
+#define EQOS_BUFFER_ALIGN ARCH_DMA_MINALIGN
+#define EQOS_MAX_PACKET_SIZE ALIGN(1568, ARCH_DMA_MINALIGN)
+#define EQOS_RX_BUFFER_SIZE (EQOS_DESCRIPTORS_RX * EQOS_MAX_PACKET_SIZE)
+
+struct eqos_desc {
+ u32 des0;
+ u32 des1;
+ u32 des2;
+ u32 des3;
+};
+
+#define EQOS_DESC3_OWN BIT(31)
+#define EQOS_DESC3_FD BIT(29)
+#define EQOS_DESC3_LD BIT(28)
+#define EQOS_DESC3_BUF1V BIT(24)
+
+struct eqos_eth_dev {
+ struct udevice *dev;
+ struct eqos_mac_regs *mac_regs_p;
+ struct eqos_mtl_regs *mtl_regs_p;
+ struct eqos_dma_regs *dma_regs_p;
+ struct mii_dev *bus;
+ struct phy_device *phydev;
+ u32 interface;
+ void *descs;
+ struct eqos_desc *tx_descs;
+ struct eqos_desc *rx_descs;
+ int tx_desc_idx, rx_desc_idx;
+ void *tx_dma_buf;
+ void *rx_dma_buf;
+ void *rx_pkt;
+};
+
#endif
diff --git a/drivers/net/fsl-mc/mc.c b/drivers/net/fsl-mc/mc.c
index 87dfddb..b245fbc 100644
--- a/drivers/net/fsl-mc/mc.c
+++ b/drivers/net/fsl-mc/mc.c
@@ -129,7 +129,7 @@
return -EINVAL;
}
- if (fit_check_format(fit_hdr, IMAGE_SIZE_INVAL)) {
+ if (!fit_check_format(fit_hdr)) {
printf("fsl-mc: ERR: Bad firmware image (bad FIT header)\n");
return -EINVAL;
}
diff --git a/drivers/net/pfe_eth/Kconfig b/drivers/net/pfe_eth/Kconfig
index 4ad62da..a13b331 100644
--- a/drivers/net/pfe_eth/Kconfig
+++ b/drivers/net/pfe_eth/Kconfig
@@ -10,4 +10,3 @@
default 0x04000000
endif
-
diff --git a/drivers/net/pfe_eth/pfe_firmware.c b/drivers/net/pfe_eth/pfe_firmware.c
index 7b930ec..adb2d06 100644
--- a/drivers/net/pfe_eth/pfe_firmware.c
+++ b/drivers/net/pfe_eth/pfe_firmware.c
@@ -150,7 +150,7 @@
return ret;
}
- if (fit_check_format(pfe_fit_addr, IMAGE_SIZE_INVAL)) {
+ if (!fit_check_format(pfe_fit_addr)) {
printf("PFE Firmware: Bad firmware image (bad FIT header)\n");
ret = -1;
return ret;
diff --git a/drivers/net/phy/Kconfig b/drivers/net/phy/Kconfig
index 043083b..8902059 100644
--- a/drivers/net/phy/Kconfig
+++ b/drivers/net/phy/Kconfig
@@ -115,6 +115,9 @@
config PHY_MESON_GXL
bool "Amlogic Meson GXL Internal PHY support"
+config PHY_AMLOGIC
+ bool "Amlogic Internal PHY support"
+
config PHY_MICREL
bool "Micrel Ethernet PHYs support"
help
@@ -228,4 +231,3 @@
More information: doc/device-tree-bindings/net/fixed-link.txt
endif #PHYLIB
-
diff --git a/drivers/net/phy/Makefile b/drivers/net/phy/Makefile
index 555da83..7887721 100644
--- a/drivers/net/phy/Makefile
+++ b/drivers/net/phy/Makefile
@@ -30,3 +30,4 @@
obj-$(CONFIG_PHY_VITESSE) += vitesse.o
obj-$(CONFIG_PHY_MSCC) += mscc.o
obj-$(CONFIG_PHY_FIXED) += fixed.o
+obj-$(CONFIG_PHY_AMLOGIC) += amlogic.o
diff --git a/drivers/net/phy/amlogic.c b/drivers/net/phy/amlogic.c
new file mode 100644
index 0000000..89e6509
--- /dev/null
+++ b/drivers/net/phy/amlogic.c
@@ -0,0 +1,73 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <config.h>
+#include <common.h>
+#include <linux/bitops.h>
+#include <dm.h>
+#include <phy.h>
+
+/* This function is provided to cope with the possible failures of this phy
+ * during aneg process. When aneg fails, the PHY reports that aneg is done
+ * but the value found in MII_LPA is wrong:
+ * - Early failures: MII_LPA is just 0x0001. if MII_EXPANSION reports that
+ * the link partner (LP) supports aneg but the LP never acked our base
+ * code word, it is likely that we never sent it to begin with.
+ * - Late failures: MII_LPA is filled with a value which seems to make sense
+ * but it actually is not what the LP is advertising. It seems that we
+ * can detect this using a magic bit in the WOL bank (reg 12 - bit 12).
+ * If this particular bit is not set when aneg is reported being done,
+ * it means MII_LPA is likely to be wrong.
+ *
+ * In both case, forcing a restart of the aneg process solve the problem.
+ * When this failure happens, the first retry is usually successful but,
+ * in some cases, it may take up to 6 retries to get a decent result
+ */
+extern unsigned int setup_amp;
+
+int meson_aml_startup(struct phy_device *phydev)
+{
+ int ret;
+
+ ret = genphy_update_link(phydev);
+ if (ret)
+ return ret;
+
+ return genphy_parse_link(phydev);
+}
+static int meson_phy_config(struct phy_device *phydev)
+{
+// unsigned int setup_amp = readl(SYSCTRL_SEC_STATUS_REG12);
+ unsigned int efuse_valid = 0;
+ efuse_valid = setup_amp >> 4;
+ if (efuse_valid) {
+ /*Enable Analog and DSP register Bank access by*/
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0000);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x0400);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x17, setup_amp & 0xf);
+ phy_write(phydev, MDIO_DEVAD_NONE, 0x14, 0x4418);
+ printf("setup_amp = %x\n", (setup_amp & 0xf));
+ }
+ return genphy_config(phydev);
+}
+
+static struct phy_driver amlogic_internal_driver = {
+ .name = "Meson GXL Internal PHY",
+ .uid = 0x01803300,
+ .mask = 0xfffffff0,
+ .features = PHY_BASIC_FEATURES,
+ .config = &meson_phy_config,
+ .startup = &meson_aml_startup,
+ .shutdown = &genphy_shutdown,
+};
+
+int phy_amlogic_init(void)
+{
+ phy_register(&amlogic_internal_driver);
+
+ return 0;
+}
diff --git a/drivers/net/phy/phy.c b/drivers/net/phy/phy.c
index 2f0637f..501e80a 100644
--- a/drivers/net/phy/phy.c
+++ b/drivers/net/phy/phy.c
@@ -528,6 +528,9 @@
#ifdef CONFIG_PHY_FIXED
phy_fixed_init();
#endif
+#ifdef CONFIG_PHY_AMLOGIC
+ phy_amlogic_init();
+#endif
return 0;
}
diff --git a/drivers/net/ti/Kconfig b/drivers/net/ti/Kconfig
index f1716c9..82bc9f5 100644
--- a/drivers/net/ti/Kconfig
+++ b/drivers/net/ti/Kconfig
@@ -18,4 +18,3 @@
bool "TI Keystone 2 Ethernet"
help
This driver supports the TI Keystone 2 Ethernet subsystem
-
diff --git a/drivers/nvme/Kconfig b/drivers/nvme/Kconfig
index f3ecac8..1f6d1f5 100644
--- a/drivers/nvme/Kconfig
+++ b/drivers/nvme/Kconfig
@@ -9,4 +9,3 @@
help
This option enables support for NVM Express devices.
It supports basic functions of NVMe (read/write).
-
diff --git a/drivers/pci/Kconfig b/drivers/pci/Kconfig
index faa4650..f59803d 100644
--- a/drivers/pci/Kconfig
+++ b/drivers/pci/Kconfig
@@ -113,4 +113,3 @@
FPGA, example Stratix 10.
endif
-
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 7ea4e6a..778cec2 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -188,4 +188,3 @@
This PHY is found on some Keystone (K2) devices supporting USB.
endmenu
-
diff --git a/drivers/phy/allwinner/Kconfig b/drivers/phy/allwinner/Kconfig
index 2be18be..dba3bae 100644
--- a/drivers/phy/allwinner/Kconfig
+++ b/drivers/phy/allwinner/Kconfig
@@ -11,4 +11,3 @@
This driver controls the entire USB PHY block, both the USB OTG
parts, as well as the 2 regular USB 2 host PHYs.
-
diff --git a/drivers/phy/marvell/Kconfig b/drivers/phy/marvell/Kconfig
index ddcf33d..4240028 100644
--- a/drivers/phy/marvell/Kconfig
+++ b/drivers/phy/marvell/Kconfig
@@ -7,4 +7,3 @@
This driver passes over the lanes
and initialize the lane depends on the
type and speed.
-
diff --git a/drivers/phy/phy-aml-usb2.c b/drivers/phy/phy-aml-usb2.c
index 1881d02..cf66677 100644
--- a/drivers/phy/phy-aml-usb2.c
+++ b/drivers/phy/phy-aml-usb2.c
@@ -1,10 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Meson GXL and GXM USB2 PHY driver
- *
- * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
- * Copyright (C) 2018 BayLibre, SAS
- * Author: Neil Armstrong <narmstron@baylibre.com>
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -12,212 +8,80 @@
#include <bitfield.h>
#include <dm.h>
#include <errno.h>
-#include <generic-phy.h>
#include <regmap.h>
#include <power/regulator.h>
#include <clk.h>
#include <asm/arch/usb.h>
-#include <asm/arch/cpu_id.h>
-
+#include <amlogic/cpu_id.h>
#include <linux/compat.h>
#include <linux/ioport.h>
#define RESET_COMPLETE_TIME 500
-struct phy_aml_usb2_priv {
- /* controller */
- unsigned int base_addr;
- unsigned int reset_addr;
- /* role */
- int id_mode;
- /* vbus call back */
- unsigned int usb_phy2_base_addr;
- unsigned int u2_port_num;
- unsigned int usb_phy2_pll_base_addr[4];
-};
-
-static int Rev_flag = 0;
-
-/*Rev_flag == 0XB, g12b and revB, tl1 */
-/*Rev_flag == 1, sm1 */
-static void phy_aml_usb2_check_rev (void)
-{
- cpu_id_t cpu_id = get_cpu_id();
-
- if (cpu_id.family_id == MESON_CPU_MAJOR_ID_G12B) {
- if (cpu_id.chip_rev == 0xb)
- Rev_flag = 0xb;
- else
- Rev_flag = 0;
- } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SM1){
- Rev_flag = MESON_CPU_MAJOR_ID_SM1;
- }
- return;
-}
-
-static int phy_aml_usb2_get_rev_type (void)
-{
- return Rev_flag;
-}
-
-
-static void set_usb_pll(struct phy *phy, uint32_t volatile *phy2_pll_base)
-{
- unsigned int pll_set1, pll_set2, pll_set3;
- unsigned int tuning_disconnect_threshold = 0x34;
-
- dev_read_u32(phy->dev, "pll-setting-1", &pll_set1);
- dev_read_u32(phy->dev, "pll-setting-2", &pll_set2);
- dev_read_u32(phy->dev, "pll-setting-3", &pll_set3);
- debug("pll1=0x%08x, pll2=0x%08x, pll-setting-3 =0x%08x\n",
- pll_set1, pll_set2, pll_set3);
-
- if (phy_aml_usb2_get_rev_type() == MESON_CPU_MAJOR_ID_SM1) {
- pll_set3 = 0xAC5F69E5;
- }
-
- (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x40))
- = (pll_set1 | USB_PHY2_RESET | USB_PHY2_ENABLE);
- (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x44)) =
- pll_set2;
- (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0x48)) =
- pll_set3;
- udelay(100);
- (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x40))
- = (((pll_set1) | (USB_PHY2_ENABLE))
- & (~(USB_PHY2_RESET)));
-
- dev_read_u32(phy->dev, "disconnect-threshold", &tuning_disconnect_threshold);
- (*(volatile uint32_t *)((unsigned long)phy2_pll_base + 0xc)) =
- tuning_disconnect_threshold;
- debug("tuning_disconnect_threshold=0x%x\n", tuning_disconnect_threshold);
-}
-
-static int phy_aml_usb2_phy_init(struct phy *phy)
-{
- struct u2p_aml_regs *u2p_aml_reg;
+static int usb_get_priv_data (struct phy *phy){
struct phy_aml_usb2_priv *priv = dev_get_priv(phy->dev);
- u2p_r0_t dev_u2p_r0;
- u2p_r1_t dev_u2p_r1;
- int i;
- int cnt, u2portnum, node;
- int time_dly = RESET_COMPLETE_TIME;
-
- phy_aml_usb2_check_rev();
- if (phy_aml_usb2_get_rev_type() == MESON_CPU_MAJOR_ID_SM1) {
- writel((readl(P_AO_RTI_GEN_PWR_SLEEP0) & (~(0x1<<17))),
- P_AO_RTI_GEN_PWR_SLEEP0);
- writel((readl(P_AO_RTI_GEN_PWR_ISO0) & (~(0x1<<17))),
- P_AO_RTI_GEN_PWR_ISO0);
- writel((readl(HHI_MEM_PD_REG0) & (~(0x3<<30))), HHI_MEM_PD_REG0);
- }
+ unsigned int dwc2_reg, u2portnum = 0;
+ int ret, i;
priv->reset_addr = dev_read_addr_index(phy->dev, 1);
if (priv->reset_addr == FDT_ADDR_T_NONE) {
- pr_err("Coun't get usb_phy2_pll_base_addr[%d]\n", i);
+ pr_err("Coun't get usb_phy2_pll_base_addr[1]: reset addr\n");
return -1;
}
- *(volatile unsigned long *)priv->reset_addr |= (1<<2);
- udelay(time_dly);
dev_read_u32(phy->dev, "portnum", &u2portnum);
priv->u2_port_num = u2portnum;
- priv->usb_phy2_pll_base_addr[0] = dev_read_addr_index(phy->dev, 2);
- if (priv->usb_phy2_pll_base_addr[0] == FDT_ADDR_T_NONE) {
- pr_err("Coun't get usb_phy2_pll_base_addr[%d]\n", i);
+ ret = dev_read_u32(phy->dev, "dwc2_a_reg", &dwc2_reg);
+ if (ret) {
+ pr_err("Coun't get dwc2_a_reg!!!!\n");
return -1;
}
+ priv->dwc2_a_addr = dwc2_reg;
+
+ for (i = 2; i < (u2portnum + 2); i++) {
+ priv->usb_phy2_pll_base_addr[i-2] = dev_read_addr_index(phy->dev, i);
+ if (priv->usb_phy2_pll_base_addr[i-2] == FDT_ADDR_T_NONE) {
+ pr_err("Coun't get usb_phy2_pll_base_addr[%d]\n", i-2);
+ return -1;
+ }
+ }
- priv->usb_phy2_pll_base_addr[1] = dev_read_addr_index(phy->dev, 3);
- if (priv->usb_phy2_pll_base_addr[1] == FDT_ADDR_T_NONE) {
- pr_err("Coun't get usb_phy2_pll_base_addr[%d]\n", i);
- return -1;
- }
priv->base_addr = dev_read_addr(phy->dev);
debug("usb2 phy: portnum=%d, addr1= 0x%08x, addr2= 0x%08x\n",
u2portnum, priv->usb_phy2_pll_base_addr[0],
priv->usb_phy2_pll_base_addr[1]);
+ debug("dwc2_a base addr: 0x%08x\n", priv->dwc2_a_addr);
- for (i = 0; i < u2portnum; i++) {
- u2p_aml_reg = (struct u2p_aml_regs *)((ulong)priv->base_addr + i * PHY_REGISTER_SIZE);
- dev_u2p_r0.d32 = u2p_aml_reg->u2p_r0;
- dev_u2p_r0.b.host_device= 1;
- dev_u2p_r0.b.POR= 0;
- u2p_aml_reg->u2p_r0 = dev_u2p_r0.d32;
- udelay(10);
- *(volatile unsigned long *)priv->reset_addr |= (1 << (16 + i));
- udelay(50);
-
- /* wait for phy ready */
- dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
- cnt = 0;
- while (dev_u2p_r1.b.phy_rdy != 1) {
- dev_u2p_r1.d32 = u2p_aml_reg->u2p_r1;
- /*we wait phy ready max 1ms, common is 100us*/
- if (cnt > 200)
- break;
- else {
- cnt++;
- udelay(5);
- }
- }
- }
-
- for (i = 0; i < u2portnum; i++) {
- debug("------set usb pll\n");
- set_usb_pll(phy, priv->usb_phy2_pll_base_addr[i]);
- }
return 0;
+
}
-static void phy_aml_usb2_reset(struct phy_aml_usb2_priv *priv)
+static int phy_aml_usb2_getinfo(struct phy *phy)
{
- return;
+ return usb_get_priv_data(phy);
}
-static int phy_aml_usb2_tuning(struct phy *phy, int port)
+static int phy_aml_usb2_phy_init(struct phy *phy)
{
+ int ret = -1;
+ ret = usb_get_priv_data(phy);
+ if (ret !=0)
+ return ret;
+
+ return usb2_phy_init(phy);
+}
+
+static int phy_aml_usb2_tuning(struct phy *phy, int port) {
struct phy_aml_usb2_priv *priv = dev_get_priv(phy->dev);
unsigned long phy_reg_base;
- unsigned int pll_set1, pll_set2, pll_set3, pll_set4;
-
- if (port > 2)
- return 0;
-
- dev_read_u32(phy->dev, "pll-setting-4", &pll_set1);
- dev_read_u32(phy->dev, "pll-setting-5", &pll_set2);
- dev_read_u32(phy->dev, "pll-setting-7", &pll_set4);
- dev_read_u32(phy->dev, "pll-setting-6", &pll_set3);
-
- debug("pll1=0x%08x, pll2=0x%08x, pll-setting-3 =0x%08x\n",
- pll_set2, pll_set1, pll_set3);
-
phy_reg_base = priv->usb_phy2_pll_base_addr[port];
-
- if (phy_aml_usb2_get_rev_type() == 0xb
- || phy_aml_usb2_get_rev_type() == MESON_CPU_MAJOR_ID_SM1) {
- (*(volatile uint32_t *)(phy_reg_base + 0x50)) = pll_set1;
- (*(volatile uint32_t *)(phy_reg_base + 0x54)) = 0x2a;
- (*(volatile uint32_t *)(phy_reg_base + 0x34)) = pll_set3 & (0x1f << 16);
+ if (phy_reg_base == 0)
return 0;
- }
-
- (*(volatile uint32_t *)(phy_reg_base + 0x10)) = pll_set2;
- (*(volatile uint32_t *)(phy_reg_base + 0x50)) = pll_set1;
- (*(volatile uint32_t *)(phy_reg_base + 0x38)) = pll_set4;
- (*(volatile uint32_t *)(phy_reg_base + 0x34)) = pll_set3;
- return 0;
-}
-
-
-static void
-phy_aml_usb2_set_host_mode(struct phy_aml_usb2_priv *priv)
-{
- return;
+ return usb2_phy_tuning(phy_reg_base, port);
}
static int phy_aml_usb2_power_on(struct phy *phy)
@@ -235,9 +99,10 @@
.power_on = phy_aml_usb2_power_on,
.power_off = phy_aml_usb2_power_off,
.tuning = phy_aml_usb2_tuning,
+ .getinfo = phy_aml_usb2_getinfo,
};
-int phy_aml_usb2_probe(struct udevice *dev)
+static int phy_aml_usb2_probe(struct udevice *dev)
{
return 0;
}
@@ -247,7 +112,7 @@
{ }
};
-U_BOOT_DRIVER(meson_gxl_usb2_phy) = {
+U_BOOT_DRIVER(meson_usb2_phy) = {
.name = "amlogic_new_usb2_phy",
.id = UCLASS_PHY,
.of_match = phy_aml_usb2_phy_ids,
diff --git a/drivers/phy/phy-aml-usb3.c b/drivers/phy/phy-aml-usb3.c
index 76b2179..e435808 100644
--- a/drivers/phy/phy-aml-usb3.c
+++ b/drivers/phy/phy-aml-usb3.c
@@ -1,10 +1,6 @@
-// SPDX-License-Identifier: GPL-2.0+
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Meson GXL USB3 PHY driver
- *
- * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
- * Copyright (C) 2018 BayLibre, SAS
- * Author: Neil Armstrong <narmstron@baylibre.com>
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -17,62 +13,88 @@
#include <clk.h>
#include <asm/arch/usb.h>
#include <linux/libfdt.h>
-//#include <asm/gpio.h>
#include <asm-generic/gpio.h>
#include <linux/compat.h>
#include <linux/bitfield.h>
-struct phy_aml_usb3_priv {
- unsigned int base_addr;
- unsigned int usb3_port_num;
-};
-
-static int
-phy_aml_usb3_set_host_mode(struct phy_aml_usb3_priv *priv)
-{
- return 0;
-}
-
-static int phy_aml_usb3_power_on(struct phy *phy){
+static int phy_aml_usb3_power_info(struct phy *phy){
+#ifdef CONFIG_DM_GPIO
int ret;
- struct gpio_desc desc;
+ //struct gpio_desc desc;
const char *usb_vbus_gpioname;
const void *fdt = gd->fdt_blob;
+ struct phy_aml_usb3_priv *priv = dev_get_priv(phy->dev);
usb_vbus_gpioname = fdt_getprop(fdt, dev_of_offset(phy->dev), "gpio-vbus-power", NULL);
- debug("usb_vbus_gpioname=%s\n", usb_vbus_gpioname);
-
- ret = dm_gpio_lookup_name(usb_vbus_gpioname, &desc);
- if (ret) {
- printf("%s: not found\n", usb_vbus_gpioname);
+ if (!usb_vbus_gpioname) {
+ printf("No ----gpio-vbus-power\n");
return 0;
}
- ret = dm_gpio_request(&desc, usb_vbus_gpioname);
+ debug("usb_vbus_gpioname=%s\n", usb_vbus_gpioname);
+
+ ret = dm_gpio_lookup_name(usb_vbus_gpioname, &priv->desc);
if (ret) {
- dm_gpio_free(phy->dev, &desc);
- dm_gpio_request(&desc, usb_vbus_gpioname);
+ printf("%s: not found\n", usb_vbus_gpioname);
+ return ret;
+ }
+
+ ret = dm_gpio_request(&priv->desc, usb_vbus_gpioname);
+ if (ret) {
+ dm_gpio_free(phy->dev, &priv->desc);
+ dm_gpio_request(&priv->desc, usb_vbus_gpioname);
pr_info("%s: after usb stop, retry request gpio\n",
usb_vbus_gpioname);
}
- ret = dm_gpio_set_dir_flags(&desc, GPIOD_IS_OUT);
+ ret = dm_gpio_set_dir_flags(&priv->desc, GPIOD_IS_OUT);
if (ret) {
pr_err("%s: failed to set direction\n", usb_vbus_gpioname);
- return 0;
+ return ret;
}
-
- dm_gpio_set_value(&desc, 1);
+#endif
return 0;
}
+static int phy_aml_usb3_power_on(struct phy *phy){
+#ifdef CONFIG_DM_GPIO
+ int ret;
+ struct phy_aml_usb3_priv *priv = dev_get_priv(phy->dev);
+
+ ret = phy_aml_usb3_power_info(phy);
+ if (ret)
+ return 0;
+
+ if (priv)
+ dm_gpio_set_value(&priv->desc, 1);
+#endif
+ return 0;
+}
static int phy_aml_usb3_power_off(struct phy *phy)
{
return 0;
}
+static int phy_aml_usb3_getinfo(struct phy *phy)
+{
+ unsigned int u3portnum;
+ struct phy_aml_usb3_priv *priv = dev_get_priv(phy->dev);
+
+ dev_read_u32(phy->dev, "portnum", &u3portnum);
+ priv->usb3_port_num = u3portnum;
+
+ priv->base_addr = dev_read_addr(phy->dev);
+ if (priv->base_addr == FDT_ADDR_T_NONE) {
+ pr_err("Coun't get usb3 base addr\n");
+ return -1;
+ }
+
+ phy_aml_usb3_power_info(phy);
+ return 0;
+}
+
static int phy_aml_usb3_init(struct phy *phy)
{
usb_r1_t r1 = {.d32 = 0};
@@ -105,7 +127,7 @@
}
for (i = 0; i < u3portnum; i++) {
- usb_aml_reg = (struct usb_aml_regs *)((ulong)priv->base_addr+i*PHY_REGISTER_SIZE);
+ usb_aml_reg = (struct usb_aml_regs *)((ulong)(priv->base_addr + i*PHY_REGISTER_SIZE));
r3.d32 = usb_aml_reg->usb_r3;
r3.b.p30_ssc_en = 1;
@@ -122,86 +144,8 @@
r1.b.u3h_fladj_30mhz_reg = 32;
usb_aml_reg->usb_r1 = r1.d32;
udelay(2);
-#if 0
- /*
- * WORKAROUND: There is SSPHY suspend bug due to which USB enumerates
- * in HS mode instead of SS mode. Workaround it by asserting
- * LANE0.TX_ALT_BLOCK.EN_ALT_BUS to enable TX to use alt bus mode
- */
- data = cr_bus_read(0x102d);
- data |= (1 << 7);
- cr_bus_write(0x102D, data);
-
- data = cr_bus_read(0x1010);
- data &= ~0xff0;
- data |= 0x20;
- cr_bus_write(0x1010, data);
-
- /*
- * Fix RX Equalization setting as follows
- * LANE0.RX_OVRD_IN_HI. RX_EQ_EN set to 0
- * LANE0.RX_OVRD_IN_HI.RX_EQ_EN_OVRD set to 1
- * LANE0.RX_OVRD_IN_HI.RX_EQ set to 3
- * LANE0.RX_OVRD_IN_HI.RX_EQ_OVRD set to 1
- */
- data = cr_bus_read(0x1006);
- data &= ~(1 << 6);
- data |= (1 << 7);
- data &= ~(0x7 << 8);
- data |= (0x3 << 8);
- data |= (0x1 << 11);
- cr_bus_write(0x1006, data);
-
- /*
- * Set EQ and TX launch amplitudes as follows
- * LANE0.TX_OVRD_DRV_LO.PREEMPH set to 22
- * LANE0.TX_OVRD_DRV_LO.AMPLITUDE set to 127
- * LANE0.TX_OVRD_DRV_LO.EN set to 1.
- */
- data = cr_bus_read(0x1002);
- data &= ~0x3f80;
- data |= (0x16 << 7);
- data &= ~0x7f;
- data |= (0x7f | (1 << 14));
- cr_bus_write(0x1002, data);
-
- /*
- * TX_FULL_SWING to 127
- */
- data = cr_bus_read(0x30);
- data &= ~(0xf << 4);
- cr_bus_write(0x30, data);
-
- /*
- * TX_FULL_SWING to 127
- */
- r1.d32 = usb_aml_reg->usb_r1;
- r1.b.p30_pcs_tx_swing_full = 127;
- r1.b.u3h_fladj_30mhz_reg = 0x20;
- usb_aml_reg->usb_r1 = r1.d32;
- udelay(2);
-
- /*
- * TX_DEEMPH_3_5DB to 22
- */
- r2.d32 = usb_aml_reg->usb_r2;
- r2.b.p30_pcs_tx_deemph_3p5db = 22;
- usb_aml_reg->usb_r2 = r2.d32;
-
- udelay(2);
- /*
- * LOS_BIAS to 0x5
- * LOS_LEVEL to 0x9
- */
- r3.d32 = usb_aml_reg->usb_r3;
- r3.b.p30_los_bias = 0x5;
- r3.b.p30_los_level = 0x9;
- r3.b.p30_ssc_en = 1;
- r3.b.p30_ssc_range = 2;
- usb_aml_reg->usb_r3 = r3.d32;
-#endif
}
-
+ usb_save_phy_dev(1, phy);
return 0;
}
@@ -210,11 +154,11 @@
.init = phy_aml_usb3_init,
.power_on = phy_aml_usb3_power_on,
.power_off = phy_aml_usb3_power_off,
+ .getinfo = phy_aml_usb3_getinfo,
};
int phy_aml_usb3_probe(struct udevice *dev)
{
-
return 0;
}
@@ -223,7 +167,7 @@
{ }
};
-U_BOOT_DRIVER(meson_gxl_usb3_phy) = {
+U_BOOT_DRIVER(meson_usb3_phy) = {
.name = "amlogic_new_usb3_phy",
.id = UCLASS_PHY,
.of_match = phy_aml_usb3_phy_ids,
diff --git a/drivers/phy/phy-uclass.c b/drivers/phy/phy-uclass.c
index c43d702..b7f4fbb 100644
--- a/drivers/phy/phy-uclass.c
+++ b/drivers/phy/phy-uclass.c
@@ -149,6 +149,13 @@
return ops->power_off ? ops->power_off(phy) : 0;
}
+int generic_phy_getinfo(struct phy *phy)
+{
+ struct phy_ops const *ops = phy_dev_ops(phy->dev);
+
+ return ops->getinfo ? ops->getinfo(phy) : 0;
+}
+
UCLASS_DRIVER(phy) = {
.id = UCLASS_PHY,
.name = "phy",
diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index 5861097..30a6aa6 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -321,4 +321,3 @@
source "drivers/pinctrl/broadcom/Kconfig"
endmenu
-
diff --git a/drivers/pinctrl/broadcom/Kconfig b/drivers/pinctrl/broadcom/Kconfig
index 458f51a..b01b725 100644
--- a/drivers/pinctrl/broadcom/Kconfig
+++ b/drivers/pinctrl/broadcom/Kconfig
@@ -13,4 +13,3 @@
help
Support pin multiplexing and pin configuration control on
Broadcom's 6838 family of SoCs.
-
diff --git a/drivers/pinctrl/exynos/Kconfig b/drivers/pinctrl/exynos/Kconfig
index 993ff65..84b6aaa 100644
--- a/drivers/pinctrl/exynos/Kconfig
+++ b/drivers/pinctrl/exynos/Kconfig
@@ -8,4 +8,3 @@
help
Support pin multiplexing and pin configuration control on
Samsung's Exynos7420 SoC.
-
diff --git a/drivers/pinctrl/mediatek/Kconfig b/drivers/pinctrl/mediatek/Kconfig
index 683ebd6..1bd9a92 100644
--- a/drivers/pinctrl/mediatek/Kconfig
+++ b/drivers/pinctrl/mediatek/Kconfig
@@ -13,4 +13,3 @@
select PINCTRL_MTK
endif
-
diff --git a/drivers/pinctrl/meson/Kconfig b/drivers/pinctrl/meson/Kconfig
index fd8aa4e..e731129 100644
--- a/drivers/pinctrl/meson/Kconfig
+++ b/drivers/pinctrl/meson/Kconfig
@@ -40,5 +40,53 @@
select PINCTRL_MESON
select PINCTRL_MESON_AXG_PMX
select PINCONF_MESON_G12A
-endif
+config PINCTRL_MESON_A1
+ bool "Amlogic Meson A1 SoC pinctrl driver"
+ depends on PINCTRL_GENERIC
+ depends on PINCONF
+ select PINCTRL_MESON
+ select PINCTRL_MESON_AXG_PMX
+ select PINCONF_MESON_G12A
+
+config PINCTRL_MESON_C1
+ bool "Amlogic Meson C1 SoC pinctrl driver"
+ depends on PINCTRL_GENERIC
+ depends on PINCONF
+ select PINCTRL_MESON
+ select PINCTRL_MESON_AXG_PMX
+ select PINCONF_MESON_G12A
+
+config PINCTRL_MESON_S4
+ bool "Amlogic Meson S4 SoC pinctrl driver"
+ depends on PINCTRL_GENERIC
+ depends on PINCONF
+ select PINCTRL_MESON
+ select PINCTRL_MESON_AXG_PMX
+ select PINCONF_MESON_G12A
+
+config PINCTRL_MESON_SC2
+ bool "Amlogic Meson SC2 SoC pinctrl driver"
+ depends on PINCTRL_GENERIC
+ depends on PINCONF
+ select PINCTRL_MESON
+ select PINCTRL_MESON_AXG_PMX
+ select PINCONF_MESON_G12A
+
+config PINCTRL_MESON_C2
+ bool "Amlogic Meson C2 SoC pinctrl driver"
+ depends on PINCTRL_GENERIC
+ depends on PINCONF
+ select PINCTRL_MESON
+ select PINCTRL_MESON_AXG_PMX
+ select PINCONF_MESON_G12A
+
+config PINCTRL_MESON_T7
+ bool "Amlogic Meson T7 SoC pinctrl driver"
+ depends on PINCTRL_GENERIC
+ depends on PINCONF
+ select PINCTRL_MESON
+ select PINCTRL_MESON_AXG_PMX
+ select PINCONF_MESON_G12A
+
+endif
diff --git a/drivers/pinctrl/meson/Makefile b/drivers/pinctrl/meson/Makefile
index faf8579..8d6a2a9 100644
--- a/drivers/pinctrl/meson/Makefile
+++ b/drivers/pinctrl/meson/Makefile
@@ -8,3 +8,9 @@
obj-$(CONFIG_PINCTRL_MESON_GXL) += pinctrl-meson-gxl.o
obj-$(CONFIG_PINCTRL_MESON_AXG) += pinctrl-meson-axg.o
obj-$(CONFIG_PINCTRL_MESON_G12A) += pinctrl-meson-g12a.o
+obj-$(CONFIG_PINCTRL_MESON_A1) += pinctrl-meson-a1.o
+obj-$(CONFIG_PINCTRL_MESON_C1) += pinctrl-meson-c1.o
+obj-$(CONFIG_PINCTRL_MESON_S4) += pinctrl-meson-s4.o
+obj-$(CONFIG_PINCTRL_MESON_SC2) += pinctrl-meson-sc2.o
+obj-$(CONFIG_PINCTRL_MESON_C2) += pinctrl-meson-c2.o
+obj-$(CONFIG_PINCTRL_MESON_T7) += pinctrl-meson-t7.o
diff --git a/drivers/pinctrl/meson/pinconf-meson-g12a.c b/drivers/pinctrl/meson/pinconf-meson-g12a.c
index 3472ff9..f81124e 100644
--- a/drivers/pinctrl/meson/pinconf-meson-g12a.c
+++ b/drivers/pinctrl/meson/pinconf-meson-g12a.c
@@ -1,17 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <linux/io.h>
@@ -58,10 +47,13 @@
if (ret)
return ret;
- if (arg >= 4) {
- debug("pin %u: invalid drive-strength [0-3]: %d\n", pin, arg);
+ if (arg < 1 || arg > 4) {
+ debug("pin %u: invalid drive-strength [1-4]: %d\n", pin, arg);
return -EINVAL;
}
+
+ arg = arg - 1;
+
meson_drive_calc_reg_and_bit(drive_bank, pin, ®, &bit);
clrsetbits_le32(priv->reg_drive + reg, 0x3 << bit, (arg & 0x3) << bit);
diff --git a/drivers/pinctrl/meson/pinconf-meson-g12a.h b/drivers/pinctrl/meson/pinconf-meson-g12a.h
index 276fb98..b77dea6 100644
--- a/drivers/pinctrl/meson/pinconf-meson-g12a.h
+++ b/drivers/pinctrl/meson/pinconf-meson-g12a.h
@@ -1,17 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef PINCONF_MESON_G12A_H
diff --git a/drivers/pinctrl/meson/pinctrl-meson-a1.c b/drivers/pinctrl/meson/pinctrl-meson-a1.c
new file mode 100644
index 0000000..2a387d9
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-a1.c
@@ -0,0 +1,862 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <dt-bindings/gpio/meson-a1-gpio.h>
+
+#include "pinctrl-meson.h"
+#include "pinctrl-meson-axg-pmx.h"
+
+/*bank P func1 */
+static const unsigned int psram_clkn_pins[] = {GPIOP_0};
+static const unsigned int psram_clkp_pins[] = {GPIOP_1};
+static const unsigned int psram_ce_n_pins[] = {GPIOP_2};
+static const unsigned int psram_rst_n_pins[] = {GPIOP_3};
+static const unsigned int psram_adq0_pins[] = {GPIOP_4};
+static const unsigned int psram_adq1_pins[] = {GPIOP_5};
+static const unsigned int psram_adq2_pins[] = {GPIOP_6};
+static const unsigned int psram_adq3_pins[] = {GPIOP_7};
+static const unsigned int psram_adq4_pins[] = {GPIOP_8};
+static const unsigned int psram_adq5_pins[] = {GPIOP_9};
+static const unsigned int psram_adq6_pins[] = {GPIOP_10};
+static const unsigned int psram_adq7_pins[] = {GPIOP_11};
+static const unsigned int psram_dqs_dm_pins[] = {GPIOP_12};
+
+/*bank P func2 */
+static const unsigned int pwm_e_p_pins[] = {GPIOP_3};
+
+/*bank B func1 */
+static const unsigned int spif_mo_pins[] = {GPIOB_0};
+static const unsigned int spif_mi_pins[] = {GPIOB_1};
+static const unsigned int spif_wp_n_pins[] = {GPIOB_2};
+static const unsigned int spif_hold_n_pins[] = {GPIOB_3};
+static const unsigned int spif_clk_pins[] = {GPIOB_4};
+static const unsigned int spif_cs_pins[] = {GPIOB_5};
+static const unsigned int pwm_f_b_pins[] = {GPIOB_6};
+
+/*bank B func2 */
+static const unsigned int sdcard_d0_b_pins[] = {GPIOB_0};
+static const unsigned int sdcard_d1_b_pins[] = {GPIOB_1};
+static const unsigned int sdcard_d2_b_pins[] = {GPIOB_2};
+static const unsigned int sdcard_d3_b_pins[] = {GPIOB_3};
+static const unsigned int sdcard_clk_b_pins[] = {GPIOB_4};
+static const unsigned int sdcard_cmd_b_pins[] = {GPIOB_5};
+
+/*bank X func1 */
+static const unsigned int sdcard_d0_x_pins[] = {GPIOX_0};
+static const unsigned int sdcard_d1_x_pins[] = {GPIOX_1};
+static const unsigned int sdcard_d2_x_pins[] = {GPIOX_2};
+static const unsigned int sdcard_d3_x_pins[] = {GPIOX_3};
+static const unsigned int sdcard_clk_x_pins[] = {GPIOX_4};
+static const unsigned int sdcard_cmd_x_pins[] = {GPIOX_5};
+static const unsigned int pwm_a_x6_pins[] = {GPIOX_6};
+static const unsigned int tdm_a_dout1_pins[] = {GPIOX_7};
+static const unsigned int tdm_a_dout0_pins[] = {GPIOX_8};
+static const unsigned int tdm_a_fs_pins[] = {GPIOX_9};
+static const unsigned int tdm_a_sclk_pins[] = {GPIOX_10};
+static const unsigned int uart_a_tx_pins[] = {GPIOX_11};
+static const unsigned int uart_a_rx_pins[] = {GPIOX_12};
+static const unsigned int uart_a_cts_pins[] = {GPIOX_13};
+static const unsigned int uart_a_rts_pins[] = {GPIOX_14};
+static const unsigned int pwm_d_x15_pins[] = {GPIOX_15};
+static const unsigned int pwm_e_x16_pins[] = {GPIOX_16};
+
+/*bank X func2 */
+static const unsigned int i2c_c_scl_x0_pins[] = {GPIOX_0};
+static const unsigned int i2c_c_sda_x1_pins[] = {GPIOX_1};
+static const unsigned int spi_a_mosi_x2_pins[] = {GPIOX_2};
+static const unsigned int spi_a_ss0_x3_pins[] = {GPIOX_3};
+static const unsigned int spi_a_sclk_x4_pins[] = {GPIOX_4};
+static const unsigned int spi_a_miso_x5_pins[] = {GPIOX_5};
+static const unsigned int tdm_a_din1_pins[] = {GPIOX_7};
+static const unsigned int tdm_a_din0_pins[] = {GPIOX_8};
+static const unsigned int tdm_a_slv_fs_pins[] = {GPIOX_9};
+static const unsigned int tdm_a_slv_sclk_pins[] = {GPIOX_10};
+static const unsigned int i2c_d_scl_x_pins[] = {GPIOX_11};
+static const unsigned int i2c_d_sda_x_pins[] = {GPIOX_12};
+static const unsigned int pwm_d_x13_pins[] = {GPIOX_13};
+static const unsigned int pwm_e_x14_pins[] = {GPIOX_14};
+static const unsigned int i2c_c_scl_x15_pins[] = {GPIOX_15};
+static const unsigned int i2c_c_sda_x16_pins[] = {GPIOX_16};
+
+/*bank X func3 */
+static const unsigned int uart_c_tx_x0_pins[] = {GPIOX_0};
+static const unsigned int uart_c_rx_x1_pins[] = {GPIOX_1};
+static const unsigned int uart_c_cts_pins[] = {GPIOX_2};
+static const unsigned int uart_c_rts_pins[] = {GPIOX_3};
+static const unsigned int pdm_din0_x_pins[] = {GPIOX_7};
+static const unsigned int pdm_din1_x_pins[] = {GPIOX_8};
+static const unsigned int pdm_din2_x_pins[] = {GPIOX_9};
+static const unsigned int pdm_dclk_x_pins[] = {GPIOX_10};
+static const unsigned int uart_c_tx_x15_pins[] = {GPIOX_15};
+static const unsigned int uart_c_rx_x16_pins[] = {GPIOX_16};
+
+/*bank X func4 */
+static const unsigned int pwm_e_x2_pins[] = {GPIOX_2};
+static const unsigned int pwm_f_x_pins[] = {GPIOX_3};
+static const unsigned int spi_a_mosi_x7_pins[] = {GPIOX_7};
+static const unsigned int spi_a_miso_x8_pins[] = {GPIOX_8};
+static const unsigned int spi_a_ss0_x9_pins[] = {GPIOX_9};
+static const unsigned int spi_a_sclk_x10_pins[] = {GPIOX_10};
+
+/*bank X func5 */
+static const unsigned int uart_b_tx_x_pins[] = {GPIOX_7};
+static const unsigned int uart_b_rx_x_pins[] = {GPIOX_8};
+static const unsigned int i2c_b_sda_x_pins[] = {GPIOX_9};
+static const unsigned int i2c_b_scl_x_pins[] = {GPIOX_10};
+
+/*bank X func6 */
+static const unsigned int pwm_a_x7_pins[] = {GPIOX_7};
+static const unsigned int pwm_b_x_pins[] = {GPIOX_8};
+static const unsigned int pwm_c_x_pins[] = {GPIOX_9};
+static const unsigned int pwm_d_x10_pins[] = {GPIOX_10};
+
+/*bank X func7 */
+static const unsigned int gen_clk_x_pins[] = {GPIOX_7};
+
+/*bank F func1 */
+static const unsigned int uart_b_tx_f_pins[] = {GPIOF_0};
+static const unsigned int uart_b_rx_f_pins[] = {GPIOF_1};
+static const unsigned int ir_remote_in_f_pins[] = {GPIOF_3};
+static const unsigned int jtag_a_clk_pins[] = {GPIOF_4};
+static const unsigned int jtag_a_tms_pins[] = {GPIOF_5};
+static const unsigned int jtag_a_tdi_pins[] = {GPIOF_6};
+static const unsigned int jtag_a_tdo_pins[] = {GPIOF_7};
+static const unsigned int gen_clk_f8_pins[] = {GPIOF_8};
+static const unsigned int pwm_a_f10_pins[] = {GPIOF_10};
+static const unsigned int i2c_a_scl_f11_pins[] = {GPIOF_11};
+static const unsigned int i2c_a_sda_f12_pins[] = {GPIOF_12};
+
+/*bank F func2 */
+static const unsigned int clk_32k_in_pins[] = {GPIOF_2};
+static const unsigned int pwm_e_f_pins[] = {GPIOF_3};
+static const unsigned int pwm_f_f4_pins[] = {GPIOF_4};
+static const unsigned int ir_remote_out_pins[] = {GPIOF_5};
+static const unsigned int spdif_in_f6_pins[] = {GPIOF_6};
+static const unsigned int spdif_in_f7_pins[] = {GPIOF_7};
+static const unsigned int pwm_a_hiz_f8_pins[] = {GPIOF_8};
+static const unsigned int pwm_a_hiz_f10_pins[] = {GPIOF_10};
+static const unsigned int pwm_d_f_pins[] = {GPIOF_11};
+static const unsigned int pwm_f_f12_pins[] = {GPIOF_12};
+
+/*bank F func3 */
+static const unsigned int pwm_c_f3_pins[] = {GPIOF_3};
+static const unsigned int swclk_pins[] = {GPIOF_4};
+static const unsigned int swdio_pins[] = {GPIOF_5};
+static const unsigned int pwm_a_f6_pins[] = {GPIOF_6};
+static const unsigned int pwm_b_f_pins[] = {GPIOF_7};
+static const unsigned int pwm_c_f8_pins[] = {GPIOF_8};
+static const unsigned int clk25_pins[] = {GPIOF_10};
+static const unsigned int i2c_slave_scl_f_pins[] = {GPIOF_11};
+static const unsigned int i2c_slave_sda_f_pins[] = {GPIOF_12};
+
+/*bank F func4 */
+static const unsigned int cec_a_pins[] = {GPIOF_2};
+static const unsigned int i2c_d_scl_f_pins[] = {GPIOF_4};
+static const unsigned int i2c_d_sda_f_pins[] = {GPIOF_5};
+static const unsigned int pmw_a_hiz_f6_pins[] = {GPIOF_6};
+static const unsigned int pwm_b_hiz_pins[] = {GPIOF_7};
+static const unsigned int pwm_c_hiz_pins[] = {GPIOF_8};
+static const unsigned int i2c_a_scl_f9_pins[] = {GPIOF_9};
+static const unsigned int i2c_a_sda_f10_pins[] = {GPIOF_10};
+
+/*bank F func5 */
+static const unsigned int cec_b_pins[] = {GPIOF_2};
+static const unsigned int clk12_24_pins[] = {GPIOF_10};
+
+/*bank F func7 */
+static const unsigned int gen_clk_f10_pins[] = {GPIOF_10};
+
+/*bank A func1 */
+static const unsigned int mclk_0_pins[] = {GPIOA_0};
+static const unsigned int tdm_b_sclk_pins[] = {GPIOA_1};
+static const unsigned int tdm_b_fs_pins[] = {GPIOA_2};
+static const unsigned int tdm_b_dout0_pins[] = {GPIOA_3};
+static const unsigned int tdm_b_dout1_pins[] = {GPIOA_4};
+static const unsigned int tdm_b_dout2_pins[] = {GPIOA_5};
+static const unsigned int tdm_b_dout3_pins[] = {GPIOA_6};
+static const unsigned int tdm_b_dout4_pins[] = {GPIOA_7};
+static const unsigned int tdm_b_dout5_pins[] = {GPIOA_8};
+static const unsigned int ir_remote_in_a_pins[] = {GPIOA_11};
+
+/*bank A func2 */
+static const unsigned int pwm_e_a_pins[] = {GPIOA_0};
+static const unsigned int tdm_b_slv_sclk_pins[] = {GPIOA_5};
+static const unsigned int tdm_b_slv_fs_pins[] = {GPIOA_6};
+static const unsigned int tdm_b_din0_pins[] = {GPIOA_7};
+static const unsigned int tdm_b_din1_pins[] = {GPIOA_8};
+static const unsigned int tdm_b_din2_pins[] = {GPIOA_9};
+static const unsigned int i2c_b_sda_a_pins[] = {GPIOA_10};
+static const unsigned int i2c_b_scl_a_pins[] = {GPIOA_11};
+
+/*bank A func3 */
+static const unsigned int i2c_c_scl_a4_pins[] = {GPIOA_4};
+static const unsigned int i2c_c_sda_a5_pins[] = {GPIOA_5};
+static const unsigned int pdm_din2_a_pins[] = {GPIOA_6};
+static const unsigned int pdm_din1_a_pins[] = {GPIOA_7};
+static const unsigned int pdm_din0_a_pins[] = {GPIOA_8};
+static const unsigned int pdm_dclk_pins[] = {GPIOA_9};
+static const unsigned int pwm_c_a_pins[] = {GPIOA_10};
+static const unsigned int pwm_b_a_pins[] = {GPIOA_11};
+
+/*bank A func4 */
+static const unsigned int pwm_a_a_pins[] = {GPIOA_5};
+static const unsigned int spi_a_mosi_a_pins[] = {GPIOA_6};
+static const unsigned int spi_a_miso_a_pins[] = {GPIOA_7};
+static const unsigned int spi_a_ss0_a_pins[] = {GPIOA_8};
+static const unsigned int spi_a_sclk_a_pins[] = {GPIOA_9};
+static const unsigned int i2c_slave_scl_a_pins[] = {GPIOA_10};
+static const unsigned int i2c_slave_sda_a_pins[] = {GPIOA_11};
+
+/*bank A func5 */
+static const unsigned int mclk_vad_pins[] = {GPIOA_0};
+static const unsigned int tdm_vad_sclk_a1_pins[] = {GPIOA_1};
+static const unsigned int tdm_vad_fs_a2_pins[] = {GPIOA_2};
+static const unsigned int tdm_vad_sclk_a5_pins[] = {GPIOA_5};
+static const unsigned int tdm_vad_fs_a6_pins[] = {GPIOA_6};
+static const unsigned int i2c_c_scl_a8_pins[] = {GPIOA_8};
+static const unsigned int i2c_c_sda_a9_pins[] = {GPIOA_9};
+
+/*bank A func6 */
+static const unsigned int tst_out0_pins[] = {GPIOA_0};
+static const unsigned int tst_out1_pins[] = {GPIOA_1};
+static const unsigned int tst_out2_pins[] = {GPIOA_2};
+static const unsigned int tst_out3_pins[] = {GPIOA_3};
+static const unsigned int tst_out4_pins[] = {GPIOA_4};
+static const unsigned int tst_out5_pins[] = {GPIOA_5};
+static const unsigned int tst_out6_pins[] = {GPIOA_6};
+static const unsigned int tst_out7_pins[] = {GPIOA_7};
+static const unsigned int tst_out8_pins[] = {GPIOA_8};
+static const unsigned int tst_out9_pins[] = {GPIOA_9};
+static const unsigned int tst_out10_pins[] = {GPIOA_10};
+static const unsigned int tst_out11_pins[] = {GPIOA_11};
+
+/*bank A func7 */
+static const unsigned int mute_key_pins[] = {GPIOA_4};
+static const unsigned int mute_en_pins[] = {GPIOA_5};
+static const unsigned int gen_clk_a_pins[] = {GPIOA_11};
+
+static struct meson_pmx_group meson_a1_periphs_groups[] = {
+ GPIO_GROUP(GPIOP_0),
+ GPIO_GROUP(GPIOP_1),
+ GPIO_GROUP(GPIOP_2),
+ GPIO_GROUP(GPIOP_3),
+ GPIO_GROUP(GPIOP_4),
+ GPIO_GROUP(GPIOP_5),
+ GPIO_GROUP(GPIOP_6),
+ GPIO_GROUP(GPIOP_7),
+ GPIO_GROUP(GPIOP_8),
+ GPIO_GROUP(GPIOP_9),
+ GPIO_GROUP(GPIOP_10),
+ GPIO_GROUP(GPIOP_11),
+ GPIO_GROUP(GPIOP_12),
+ GPIO_GROUP(GPIOB_0),
+ GPIO_GROUP(GPIOB_1),
+ GPIO_GROUP(GPIOB_2),
+ GPIO_GROUP(GPIOB_3),
+ GPIO_GROUP(GPIOB_4),
+ GPIO_GROUP(GPIOB_5),
+ GPIO_GROUP(GPIOB_6),
+ GPIO_GROUP(GPIOX_0),
+ GPIO_GROUP(GPIOX_1),
+ GPIO_GROUP(GPIOX_2),
+ GPIO_GROUP(GPIOX_3),
+ GPIO_GROUP(GPIOX_4),
+ GPIO_GROUP(GPIOX_5),
+ GPIO_GROUP(GPIOX_6),
+ GPIO_GROUP(GPIOX_7),
+ GPIO_GROUP(GPIOX_8),
+ GPIO_GROUP(GPIOX_9),
+ GPIO_GROUP(GPIOX_10),
+ GPIO_GROUP(GPIOX_11),
+ GPIO_GROUP(GPIOX_12),
+ GPIO_GROUP(GPIOX_13),
+ GPIO_GROUP(GPIOX_14),
+ GPIO_GROUP(GPIOX_15),
+ GPIO_GROUP(GPIOX_16),
+ GPIO_GROUP(GPIOF_0),
+ GPIO_GROUP(GPIOF_1),
+ GPIO_GROUP(GPIOF_2),
+ GPIO_GROUP(GPIOF_3),
+ GPIO_GROUP(GPIOF_4),
+ GPIO_GROUP(GPIOF_5),
+ GPIO_GROUP(GPIOF_6),
+ GPIO_GROUP(GPIOF_7),
+ GPIO_GROUP(GPIOF_8),
+ GPIO_GROUP(GPIOF_9),
+ GPIO_GROUP(GPIOF_10),
+ GPIO_GROUP(GPIOF_11),
+ GPIO_GROUP(GPIOF_12),
+ GPIO_GROUP(GPIOA_0),
+ GPIO_GROUP(GPIOA_1),
+ GPIO_GROUP(GPIOA_2),
+ GPIO_GROUP(GPIOA_3),
+ GPIO_GROUP(GPIOA_4),
+ GPIO_GROUP(GPIOA_5),
+ GPIO_GROUP(GPIOA_6),
+ GPIO_GROUP(GPIOA_7),
+ GPIO_GROUP(GPIOA_8),
+ GPIO_GROUP(GPIOA_9),
+ GPIO_GROUP(GPIOA_10),
+ GPIO_GROUP(GPIOA_11),
+
+ GPIO_GROUP(GPIO_TEST_N),
+
+ /* bank P func1 */
+ GROUP(psram_clkn, 1),
+ GROUP(psram_clkp, 1),
+ GROUP(psram_ce_n, 1),
+ GROUP(psram_rst_n, 1),
+ GROUP(psram_adq0, 1),
+ GROUP(psram_adq1, 1),
+ GROUP(psram_adq2, 1),
+ GROUP(psram_adq3, 1),
+ GROUP(psram_adq4, 1),
+ GROUP(psram_adq5, 1),
+ GROUP(psram_adq6, 1),
+ GROUP(psram_adq7, 1),
+ GROUP(psram_dqs_dm, 1),
+
+ /*bank P func2 */
+ GROUP(pwm_e_p, 2),
+
+ /*bank B func1 */
+ GROUP(spif_mo, 1),
+ GROUP(spif_mi, 1),
+ GROUP(spif_wp_n, 1),
+ GROUP(spif_hold_n, 1),
+ GROUP(spif_clk, 1),
+ GROUP(spif_cs, 1),
+ GROUP(pwm_f_b, 1),
+
+ /*bank B func2 */
+ GROUP(sdcard_d0_b, 2),
+ GROUP(sdcard_d1_b, 2),
+ GROUP(sdcard_d2_b, 2),
+ GROUP(sdcard_d3_b, 2),
+ GROUP(sdcard_clk_b, 2),
+ GROUP(sdcard_cmd_b, 2),
+
+ /*bank X func1 */
+ GROUP(sdcard_d0_x, 1),
+ GROUP(sdcard_d1_x, 1),
+ GROUP(sdcard_d2_x, 1),
+ GROUP(sdcard_d3_x, 1),
+ GROUP(sdcard_clk_x, 1),
+ GROUP(sdcard_cmd_x, 1),
+ GROUP(pwm_a_x6, 1),
+ GROUP(tdm_a_dout1, 1),
+ GROUP(tdm_a_dout0, 1),
+ GROUP(tdm_a_fs, 1),
+ GROUP(tdm_a_sclk, 1),
+ GROUP(uart_a_tx, 1),
+ GROUP(uart_a_rx, 1),
+ GROUP(uart_a_cts, 1),
+ GROUP(uart_a_rts, 1),
+ GROUP(pwm_d_x15, 1),
+ GROUP(pwm_e_x16, 1),
+
+ /*bank X func2 */
+ GROUP(i2c_c_scl_x0, 2),
+ GROUP(i2c_c_sda_x1, 2),
+ GROUP(spi_a_mosi_x2, 2),
+ GROUP(spi_a_ss0_x3, 2),
+ GROUP(spi_a_sclk_x4, 2),
+ GROUP(spi_a_miso_x5, 2),
+ GROUP(tdm_a_din1, 2),
+ GROUP(tdm_a_din0, 2),
+ GROUP(tdm_a_slv_fs, 2),
+ GROUP(tdm_a_slv_sclk, 2),
+ GROUP(i2c_d_scl_x, 2),
+ GROUP(i2c_d_sda_x, 2),
+ GROUP(pwm_d_x13, 2),
+ GROUP(pwm_e_x14, 2),
+ GROUP(i2c_c_scl_x15, 2),
+ GROUP(i2c_c_sda_x16, 2),
+
+ /*bank X func3 */
+ GROUP(uart_c_tx_x0, 3),
+ GROUP(uart_c_rx_x1, 3),
+ GROUP(uart_c_cts, 3),
+ GROUP(uart_c_rts, 3),
+ GROUP(pdm_din0_x, 3),
+ GROUP(pdm_din1_x, 3),
+ GROUP(pdm_din2_x, 3),
+ GROUP(pdm_dclk_x, 3),
+ GROUP(uart_c_tx_x15, 3),
+ GROUP(uart_c_rx_x16, 3),
+
+ /*bank X func4 */
+ GROUP(pwm_e_x2, 4),
+ GROUP(pwm_f_x, 4),
+ GROUP(spi_a_mosi_x7, 4),
+ GROUP(spi_a_miso_x8, 4),
+ GROUP(spi_a_ss0_x9, 4),
+ GROUP(spi_a_sclk_x10, 4),
+
+ /*bank X func5 */
+ GROUP(uart_b_tx_x, 5),
+ GROUP(uart_b_rx_x, 5),
+ GROUP(i2c_b_sda_x, 5),
+ GROUP(i2c_b_scl_x, 5),
+
+ /*bank X func6 */
+ GROUP(pwm_a_x7, 6),
+ GROUP(pwm_b_x, 6),
+ GROUP(pwm_c_x, 6),
+ GROUP(pwm_d_x10, 6),
+
+ /*bank X func7 */
+ GROUP(gen_clk_x, 7),
+
+ /*bank F func1 */
+ GROUP(uart_b_tx_f, 1),
+ GROUP(uart_b_rx_f, 1),
+ GROUP(ir_remote_in_f, 1),
+ GROUP(jtag_a_clk, 1),
+ GROUP(jtag_a_tms, 1),
+ GROUP(jtag_a_tdi, 1),
+ GROUP(jtag_a_tdo, 1),
+ GROUP(gen_clk_f8, 1),
+ GROUP(pwm_a_f10, 1),
+ GROUP(i2c_a_scl_f11, 1),
+ GROUP(i2c_a_sda_f12, 1),
+
+ /*bank F func2 */
+ GROUP(clk_32k_in, 2),
+ GROUP(pwm_e_f, 2),
+ GROUP(pwm_f_f4, 2),
+ GROUP(ir_remote_out, 2),
+ GROUP(spdif_in_f6, 2),
+ GROUP(spdif_in_f7, 2),
+ GROUP(pwm_a_hiz_f8, 2),
+ GROUP(pwm_a_hiz_f10, 2),
+ GROUP(pwm_d_f, 2),
+ GROUP(pwm_f_f12, 2),
+
+ /*bank F func3 */
+ GROUP(pwm_c_f3, 3),
+ GROUP(swclk, 3),
+ GROUP(swdio, 3),
+ GROUP(pwm_a_f6, 3),
+ GROUP(pwm_b_f, 3),
+ GROUP(pwm_c_f8, 3),
+ GROUP(clk25, 3),
+ GROUP(i2c_slave_scl_f, 3),
+ GROUP(i2c_slave_sda_f, 3),
+
+ /*bank F func4 */
+ GROUP(cec_a, 4),
+ GROUP(i2c_d_scl_f, 4),
+ GROUP(i2c_d_sda_f, 4),
+ GROUP(pmw_a_hiz_f6, 4),
+ GROUP(pwm_b_hiz, 4),
+ GROUP(pwm_c_hiz, 4),
+ GROUP(i2c_a_scl_f9, 4),
+ GROUP(i2c_a_sda_f10, 4),
+
+ /*bank F func5 */
+ GROUP(cec_b, 5),
+ GROUP(clk12_24, 5),
+
+ /*bank F func7 */
+ GROUP(gen_clk_f10, 7),
+
+ /*bank A func1 */
+ GROUP(mclk_0, 1),
+ GROUP(tdm_b_sclk, 1),
+ GROUP(tdm_b_fs, 1),
+ GROUP(tdm_b_dout0, 1),
+ GROUP(tdm_b_dout1, 1),
+ GROUP(tdm_b_dout2, 1),
+ GROUP(tdm_b_dout3, 1),
+ GROUP(tdm_b_dout4, 1),
+ GROUP(tdm_b_dout5, 1),
+ GROUP(ir_remote_in_a, 1),
+
+ /*bank A func2 */
+ GROUP(pwm_e_a, 2),
+ GROUP(tdm_b_slv_sclk, 2),
+ GROUP(tdm_b_slv_fs, 2),
+ GROUP(tdm_b_din0, 2),
+ GROUP(tdm_b_din1, 2),
+ GROUP(tdm_b_din2, 2),
+ GROUP(i2c_b_sda_a, 2),
+ GROUP(i2c_b_scl_a, 2),
+
+ /*bank A func3 */
+ GROUP(i2c_c_scl_a4, 3),
+ GROUP(i2c_c_sda_a5, 3),
+ GROUP(pdm_din2_a, 3),
+ GROUP(pdm_din1_a, 3),
+ GROUP(pdm_din0_a, 3),
+ GROUP(pdm_dclk, 3),
+ GROUP(pwm_c_a, 3),
+ GROUP(pwm_b_a, 3),
+
+ /*bank A func4 */
+ GROUP(pwm_a_a, 4),
+ GROUP(spi_a_mosi_a, 4),
+ GROUP(spi_a_miso_a, 4),
+ GROUP(spi_a_ss0_a, 4),
+ GROUP(spi_a_sclk_a, 4),
+ GROUP(i2c_slave_scl_a, 4),
+ GROUP(i2c_slave_sda_a, 4),
+
+ /*bank A func5 */
+ GROUP(mclk_vad, 5),
+ GROUP(tdm_vad_sclk_a1, 5),
+ GROUP(tdm_vad_fs_a2, 5),
+ GROUP(tdm_vad_sclk_a5, 5),
+ GROUP(tdm_vad_fs_a6, 5),
+ GROUP(i2c_c_scl_a8, 5),
+ GROUP(i2c_c_sda_a9, 5),
+
+ /*bank A func6 */
+ GROUP(tst_out0, 6),
+ GROUP(tst_out1, 6),
+ GROUP(tst_out2, 6),
+ GROUP(tst_out3, 6),
+ GROUP(tst_out4, 6),
+ GROUP(tst_out5, 6),
+ GROUP(tst_out6, 6),
+ GROUP(tst_out7, 6),
+ GROUP(tst_out8, 6),
+ GROUP(tst_out9, 6),
+ GROUP(tst_out10, 6),
+ GROUP(tst_out11, 6),
+
+ /*bank A func7 */
+ GROUP(mute_key, 7),
+ GROUP(mute_en, 7),
+ GROUP(gen_clk_a, 7),
+};
+
+static const char * const gpio_periphs_groups[] = {
+ "GPIO_TEST_N",
+
+ "GPIOP_0", "GPIOP_1", "GPIOP_2", "GPIOP_3", "GPIOP_4",
+ "GPIOP_5", "GPIOP_6", "GPIOP_7", "GPIOP_8", "GPIOP_9",
+ "GPIOP_10", "GPIOP_11", "GPIOP_12",
+
+ "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4",
+ "GPIOB_5", "GPIOB_6",
+
+ "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
+ "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
+ "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
+ "GPIOX_15", "GPIOX_16",
+
+ "GPIOF_0", "GPIOF_1", "GPIOF_2", "GPIOF_3", "GPIOF_4",
+ "GPIOF_5", "GPIOF_6", "GPIOF_7", "GPIOF_8", "GPIOF_9",
+ "GPIOF_10", "GPIOF_11", "GPIOF_12",
+
+ "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4",
+ "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9",
+ "GPIOA_10", "GPIOA_11",
+};
+
+static const char * const psram_groups[] = {
+ "psram_clkn", "psram_clkp", "psram_ce_n", "psram_rst_n", "psram_adq0",
+ "psram_adq1", "psram_adq2", "psram_adq3", "psram_adq4", "psram_adq5",
+ "psram_adq6", "psram_adq7", "psram_dqs_dm",
+};
+
+static const char * const pwm_a_groups[] = {
+ "pwm_a_x6", "pwm_a_x7", "pwm_a_f10", "pwm_a_f6", "pwm_a_a",
+};
+
+static const char * const pwm_b_groups[] = {
+ "pwm_b_x", "pwm_b_f", "pwm_b_a",
+};
+
+static const char * const pwm_c_groups[] = {
+ "pwm_c_x", "pwm_c_f3", "pwm_c_f8", "pwm_c_a",
+};
+
+static const char * const pwm_d_groups[] = {
+ "pwm_d_x15", "pwm_d_x13", "pwm_d_x10", "pwm_d_f",
+};
+
+static const char * const pwm_e_groups[] = {
+ "pwm_e_p", "pwm_e_x16", "pwm_e_x14", "pwm_e_x2", "pwm_e_f",
+ "pwm_e_a",
+};
+
+static const char * const pwm_f_groups[] = {
+ "pwm_f_b", "pwm_f_x", "pwm_f_f4", "pwm_f_f12",
+};
+
+static const char * const pwm_a_hiz_groups[] = {
+ "pwm_a_hiz_f8", "pwm_a_hiz_f10",
+};
+
+static const char * const pwm_b_hiz_groups[] = {
+ "pwm_b_hiz",
+};
+
+static const char * const pwm_c_hiz_groups[] = {
+ "pwm_c_hiz",
+};
+
+static const char * const spif_groups[] = {
+ "spif_mo", "spif_mi", "spif_wp_n", "spif_hold_n", "spif_clk",
+ "spif_cs",
+};
+
+static const char * const sdcard_groups[] = {
+ "sdcard_d0_b", "sdcard_d1_b", "sdcard_d2_b", "sdcard_d3_b",
+ "sdcard_clk_b", "sdcard_cmd_b",
+
+ "sdcard_d0_x", "sdcard_d1_x", "sdcard_d2_x", "sdcard_d3_x",
+ "sdcard_clk_x", "sdcard_cmd_x",
+};
+
+static const char * const tdm_a_groups[] = {
+ "tdm_a_din0", "tdm_a_din1", "tdm_a_sclk", "tdm_a_fs", "tdm_a_sclk",
+ "tdm_a_slv_fs", "tdm_a_slv_sclk",
+ "tdm_a_dout0", "tdm_a_dout1", "tdm_a_fs", "tdm_a_sclk", "tdm_a_sclk",
+ "tdm_a_slv_fs", "tdm_a_slv_sclk",
+};
+
+static const char * const uart_a_groups[] = {
+ "uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts",
+};
+
+static const char * const uart_b_groups[] = {
+ "uart_b_tx_x", "uart_b_rx_x", "uart_b_tx_f", "uart_b_rx_f",
+};
+
+static const char * const uart_c_groups[] = {
+ "uart_c_tx_x0", "uart_c_rx_x1", "uart_c_cts", "uart_c_rts",
+ "uart_c_tx_x15", "uart_c_rx_x16",
+};
+
+static const char * const i2c_a_groups[] = {
+ "i2c_a_scl_f11", "i2c_a_sda_f12", "i2c_a_scl_f9", "i2c_a_sda_f10",
+};
+
+static const char * const i2c_b_groups[] = {
+ "i2c_b_sda_x", "i2c_b_scl_x", "i2c_b_sda_a", "i2c_b_scl_a",
+};
+
+static const char * const i2c_c_groups[] = {
+ "i2c_c_scl_x0", "i2c_c_sda_x1", "i2c_c_scl_x15", "i2c_c_sda_x16",
+ "i2c_c_scl_a4", "i2c_c_sda_a5", "i2c_c_scl_a8", "i2c_c_sda_a9",
+};
+
+static const char * const i2c_d_groups[] = {
+ "i2c_d_scl_x", "i2c_d_sda_x",
+ "i2c_d_scl_f", "i2c_d_sda_f",
+};
+
+static const char * const spi_a_groups[] = {
+ "spi_a_mosi_x2", "spi_a_ss0_x3", "spi_a_sclk_x4", "spi_a_miso_x5",
+ "spi_a_mosi_x7", "spi_a_miso_x8", "spi_a_ss0_x9", "spi_a_sclk_x10",
+
+ "spi_a_mosi_a", "spi_a_miso_a", "spi_a_ss0_a", "spi_a_sclk_a",
+};
+
+static const char * const pdm_groups[] = {
+ "pdm_din0_x", "pdm_din1_x", "pdm_din2_x", "pdm_dclk_x", "pdm_din2_a",
+ "pdm_din1_a", "pdm_din0_a", "pdm_dclk",
+};
+
+static const char * const gen_clk_groups[] = {
+ "gen_clk_x", "gen_clk_f8", "gen_clk_f10", "gen_clk_a",
+};
+
+static const char * const ir_remote_in_groups[] = {
+ "ir_remote_in_f",
+ "ir_remote_in_a",
+};
+
+static const char * const jtag_a_groups[] = {
+ "jtag_a_clk", "jtag_a_tms", "jtag_a_tdi", "jtag_a_tdo",
+};
+
+static const char * const clk_32k_in_groups[] = {
+ "clk_32k_in",
+};
+
+static const char * const ir_remote_out_groups[] = {
+ "ir_remote_out",
+};
+
+static const char * const spdif_in_groups[] = {
+ "spdif_in_f6", "spdif_in_f7",
+};
+
+static const char * const sw_groups[] = {
+ "swclk", "swdio",
+};
+
+static const char * const clk25_groups[] = {
+ "clk_25",
+};
+
+static const char * const cec_a_groups[] = {
+ "cec_a",
+};
+
+static const char * const cec_b_groups[] = {
+ "cec_b",
+};
+
+static const char * const clk12_24_groups[] = {
+ "clk12_24",
+};
+
+static const char * const mclk_0_groups[] = {
+ "mclk_0",
+};
+
+static const char * const tdm_b_groups[] = {
+ "tdm_b_sclk", "tdm_b_fs", "tdm_b_slv_sclk", "tdm_b_slv_fs",
+ "tdm_b_din0", "tdm_b_din1", "tdm_b_din2",
+
+ "tdm_b_sclk", "tdm_b_fs", "tdm_b_dout0", "tdm_b_dout1",
+ "tdm_b_dout2", "tdm_b_dout3", "tdm_b_dout4", "tdm_b_dout5",
+ "tdm_b_slv_sclk", "tdm_b_slv_fs",
+};
+
+static const char * const mclk_vad_groups[] = {
+ "mclk_vad",
+};
+
+static const char * const tdm_vad_groups[] = {
+ "tdm_vad_sclk_a1", "tdm_vad_fs_a2", "tdm_vad_sclk_a5", "tdm_vad_fs_a6",
+};
+
+static const char * const tst_out_groups[] = {
+ "tst_out0", "tst_out1", "tst_out2", "tst_out3",
+ "tst_out4", "tst_out5", "tst_out6", "tst_out7",
+ "tst_out8", "tst_out9", "tst_out10", "tst_out11",
+};
+
+static const char * const mute_groups[] = {
+ "mute_key", "mute_en",
+};
+
+static struct meson_pmx_func meson_a1_periphs_functions[] = {
+ FUNCTION(gpio_periphs),
+ FUNCTION(psram),
+ FUNCTION(pwm_a),
+ FUNCTION(pwm_b),
+ FUNCTION(pwm_c),
+ FUNCTION(pwm_d),
+ FUNCTION(pwm_e),
+ FUNCTION(pwm_f),
+ FUNCTION(pwm_a_hiz),
+ FUNCTION(pwm_b_hiz),
+ FUNCTION(pwm_c_hiz),
+ FUNCTION(spif),
+ FUNCTION(sdcard),
+ FUNCTION(tdm_a),
+ FUNCTION(uart_a),
+ FUNCTION(uart_b),
+ FUNCTION(uart_c),
+ FUNCTION(i2c_a),
+ FUNCTION(i2c_b),
+ FUNCTION(i2c_c),
+ FUNCTION(i2c_d),
+ FUNCTION(spi_a),
+ FUNCTION(pdm),
+ FUNCTION(gen_clk),
+ FUNCTION(ir_remote_in),
+ FUNCTION(jtag_a),
+ FUNCTION(clk_32k_in),
+ FUNCTION(ir_remote_out),
+ FUNCTION(spdif_in),
+ FUNCTION(sw),
+ FUNCTION(clk25),
+ FUNCTION(cec_a),
+ FUNCTION(cec_b),
+ FUNCTION(clk12_24),
+ FUNCTION(mclk_0),
+ FUNCTION(tdm_b),
+ FUNCTION(mclk_vad),
+ FUNCTION(tdm_vad),
+ FUNCTION(tst_out),
+ FUNCTION(mute),
+};
+
+static struct meson_bank meson_a1_periphs_banks[] = {
+ /* name first last pullen pull dir out in */
+ BANK("GPIOP_", GPIOP_0, GPIOP_12,
+ 0x3, 0, 0x4, 0, 0x2, 0, 0x1, 0, 0x0, 0),
+ BANK("GPIOB_", GPIOB_0, GPIOB_6,
+ 0x13, 0, 0x14, 0, 0x12, 0, 0x11, 0, 0x10, 0),
+ BANK("GPIOX_", GPIOX_0, GPIOX_16,
+ 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0),
+ BANK("GPIOF_", GPIOF_0, GPIOF_12,
+ 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0),
+ BANK("GPIOA_", GPIOA_0, GPIOA_11,
+ 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0),
+ BANK("GPIO_TEST_N", GPIO_TEST_N, GPIO_TEST_N,
+ 0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0),
+};
+
+static struct meson_pmx_bank meson_a1_periphs_pmx_banks[] = {
+ /* name first lask reg offset */
+ BANK_PMX("P", GPIOP_0, GPIOP_12, 0x0, 0),
+ BANK_PMX("B", GPIOB_0, GPIOB_6, 0x2, 0),
+ BANK_PMX("X", GPIOX_0, GPIOX_16, 0x3, 0),
+ BANK_PMX("F", GPIOF_0, GPIOF_12, 0x6, 0),
+ BANK_PMX("A", GPIOA_0, GPIOA_11, 0x8, 0),
+ BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0xa, 0),
+};
+
+static struct meson_drive_bank meson_a1_periphs_drive_banks[] = {
+ /* name first lask reg offset */
+ BANK_DRIVE("P", GPIOP_0, GPIOP_12, 0x5, 0),
+ BANK_DRIVE("B", GPIOB_0, GPIOB_6, 0x15, 0),
+ BANK_DRIVE("X", GPIOX_0, GPIOX_16, 0x25, 0),
+ BANK_DRIVE("F", GPIOF_0, GPIOF_12, 0x35, 0),
+ BANK_DRIVE("A", GPIOA_0, GPIOA_11, 0x45, 0),
+ BANK_DRIVE("TESTN", GPIO_TEST_N, GPIO_TEST_N, 0x55, 0),
+};
+
+static struct meson_axg_pmx_data meson_a1_periphs_pmx_banks_data = {
+ .pmx_banks = meson_a1_periphs_pmx_banks,
+ .num_pmx_banks = ARRAY_SIZE(meson_a1_periphs_pmx_banks),
+};
+
+static struct meson_drive_data meson_a1_periphs_drive_data = {
+ .drive_banks = meson_a1_periphs_drive_banks,
+ .num_drive_banks = ARRAY_SIZE(meson_a1_periphs_drive_banks),
+};
+
+static struct meson_pinctrl_data meson_a1_periphs_pinctrl_data = {
+ .name = "periphs-banks",
+ .groups = meson_a1_periphs_groups,
+ .funcs = meson_a1_periphs_functions,
+ .banks = meson_a1_periphs_banks,
+ .num_pins = 63,
+ .num_groups = ARRAY_SIZE(meson_a1_periphs_groups),
+ .num_funcs = ARRAY_SIZE(meson_a1_periphs_functions),
+ .num_banks = ARRAY_SIZE(meson_a1_periphs_banks),
+ .pmx_data = &meson_a1_periphs_pmx_banks_data,
+ .drv_data = &meson_a1_periphs_drive_data,
+};
+
+static const struct udevice_id meson_a1_pinctrl_match[] = {
+ {
+ .compatible = "amlogic,meson-a1-periphs-pinctrl",
+ .data = (ulong)&meson_a1_periphs_pinctrl_data,
+ },
+ { },
+};
+
+U_BOOT_DRIVER(meson_g12a_pinctrl) = {
+ .name = "meson-a1-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(meson_a1_pinctrl_match),
+ .probe = meson_pinctrl_probe,
+ .priv_auto_alloc_size = sizeof(struct meson_pinctrl),
+ .ops = &meson_axg_pinctrl_ops,
+};
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
index a235831..97cea38 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.c
@@ -26,6 +26,7 @@
#include "pinctrl-meson.h"
#include "pinctrl-meson-axg-pmx.h"
+static char pin_name[PINNAME_SIZE];
static const struct pinconf_param meson_axg_pinconf_params[] = {
{ "bias-disable", PIN_CONFIG_BIAS_DISABLE, 0 },
{ "bias-pull-up", PIN_CONFIG_BIAS_PULL_UP, 1 },
@@ -119,11 +120,91 @@
return meson_axg_pmx_update_function(priv, offset, 0);
}
+static int meson_pinmux_get_pins_count(struct udevice *dev)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev);
+
+ return priv->data->num_pins;
+}
+
+static const char *meson_pinmux_get_pin_name(struct udevice *dev, unsigned selector)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev);
+ const char *name;
+ int i;
+ int offset = 0;
+
+ /*get bank name according to selector*/
+ for (i = 0; i < priv->data->num_banks; i++) {
+ if (selector >= priv->data->banks[i].first &&
+ selector <= priv->data->banks[i].last) {
+ name = priv->data->banks[i].name;
+ offset = selector - priv->data->banks[i].first;
+ break;
+ }
+ }
+
+ if (i >= priv->data->num_banks)
+ snprintf(pin_name, PINNAME_SIZE, "%s", "Error");
+ else
+ snprintf(pin_name, PINNAME_SIZE, "%s%d", name, offset);
+
+ return pin_name;
+}
+
+static int meson_pinmux_get_pin_muxing(struct udevice *dev,
+ unsigned int selector, char *buf,
+ int size)
+{
+ struct meson_pinctrl *priv = dev_get_priv(dev);
+ struct meson_pmx_bank *bank;
+ struct meson_pmx_group *group;
+ struct meson_pmx_axg_data *pmx_data;
+
+ void __iomem *addr;
+ unsigned int reg;
+ unsigned int offset;
+ int ret;
+ int func;
+ int i,j;
+
+ ret = meson_axg_pmx_get_bank(priv, selector, &bank);
+ if (ret)
+ return ret;
+
+ meson_pmx_calc_reg_and_offset(bank, selector, ®, &offset);
+ addr = priv->reg_mux + reg * 4;
+ func = (readl(addr) & (0xf << offset)) >> offset;
+
+ for (i = 0; i < priv->data->num_groups; i++) {
+ group = &priv->data->groups[i];
+ pmx_data = (struct meson_pmx_axg_data *)group->data;
+
+ if (pmx_data->func != func)
+ continue;
+
+ for (j = 0; j < group->num_pins; j++) {
+ if (group->pins[j] == selector) {
+ snprintf(buf, size, "%s (%x)",
+ group->name, func);
+ return 0;
+ }
+ }
+ }
+
+ snprintf(buf, size, "Unknown (%x)", func);
+
+ return 0;
+}
+
const struct pinctrl_ops meson_axg_pinctrl_ops = {
.get_groups_count = meson_pinctrl_get_groups_count,
.get_group_name = meson_pinctrl_get_group_name,
.get_functions_count = meson_pinmux_get_functions_count,
.get_function_name = meson_pinmux_get_function_name,
+ .get_pins_count = meson_pinmux_get_pins_count,
+ .get_pin_name = meson_pinmux_get_pin_name,
+ .get_pin_muxing = meson_pinmux_get_pin_muxing,
.pinmux_group_set = meson_axg_pmx_set_mux,
.set_state = pinctrl_generic_set_state,
.set_gpio_mux = meson_axg_pmx_request_gpio,
diff --git a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h
index a23a9d4..937e71a 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h
+++ b/drivers/pinctrl/meson/pinctrl-meson-axg-pmx.h
@@ -1,11 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Copyright (c) 2017 Baylibre SAS.
- * Author: Jerome Brunet <jbrunet@baylibre.com>
- *
- * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
- * Author: Xingyu Chen <xingyu.chen@amlogic.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ or MIT)
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
struct meson_pmx_bank {
diff --git a/drivers/pinctrl/meson/pinctrl-meson-c1.c b/drivers/pinctrl/meson/pinctrl-meson-c1.c
new file mode 100644
index 0000000..f27385b
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-c1.c
@@ -0,0 +1,1098 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <dt-bindings/gpio/meson-c1-gpio.h>
+
+#include "pinctrl-meson.h"
+#include "pinctrl-meson-axg-pmx.h"
+
+/*bank D func1 */
+static const unsigned int uart_b_tx_d_pins[] = { GPIOD_0 };
+static const unsigned int uart_b_rx_d_pins[] = { GPIOD_1 };
+static const unsigned int i2c_a_scl_d_pins[] = { GPIOD_2 };
+static const unsigned int i2c_a_sda_d_pins[] = { GPIOD_3 };
+static const unsigned int ir_out_d4_pins[] = { GPIOD_4 };
+static const unsigned int ir_in_d5_pins[] = { GPIOD_5 };
+static const unsigned int jtag_a_clk_pins[] = { GPIOD_6 };
+static const unsigned int jtag_a_tms_pins[] = { GPIOD_7 };
+static const unsigned int jtag_a_tdi_pins[] = { GPIOD_8 };
+static const unsigned int jtag_a_tdo_pins[] = { GPIOD_9 };
+static const unsigned int gen_clk_d_pins[] = { GPIOD_11 };
+static const unsigned int clk12_24_d_pins[] = { GPIOD_12 };
+
+/*bank D func2 */
+static const unsigned int uart_d_tx_d2_pins[] = { GPIOD_2 };
+static const unsigned int uart_d_rx_d3_pins[] = { GPIOD_3 };
+static const unsigned int swclk_pins[] = { GPIOD_6 };
+static const unsigned int swdio_pins[] = { GPIOD_7 };
+static const unsigned int ir_in_d8_pins[] = { GPIOD_8 };
+static const unsigned int ir_out_d9_pins[] = { GPIOD_9 };
+static const unsigned int clk25_pins[] = { GPIOD_12 };
+
+/*bank D func3 */
+static const unsigned int i2c_slave_scl_pins[] = { GPIOD_2 };
+static const unsigned int i2c_slave_sda_pins[] = { GPIOD_3 };
+static const unsigned int pwm_d_pins[] = { GPIOD_5 };
+static const unsigned int pwm_c_pins[] = { GPIOD_6 };
+static const unsigned int pwm_f_d_pins[] = { GPIOD_7 };
+static const unsigned int uart_d_tx_d8_pins[] = { GPIOD_8 };
+static const unsigned int uart_d_rx_d9_pins[] = { GPIOD_9 };
+static const unsigned int pwm_g_d_pins[] = { GPIOD_10 };
+static const unsigned int clk_32k_in_pins[] = { GPIOD_12 };
+
+/*bank D func4 */
+static const unsigned int pwm_d_hiz_pins[] = { GPIOD_5 };
+static const unsigned int pwm_c_hiz_pins[] = { GPIOD_6 };
+static const unsigned int pwm_f_hiz_pins[] = { GPIOD_7 };
+
+/*bank E func1 */
+static const unsigned int uart_b_cts_pins[] = { GPIOE_0 };
+static const unsigned int uart_b_rts_pins[] = { GPIOE_1 };
+
+/*bank E func2 */
+static const unsigned int uart_d_cts_e_pins[] = { GPIOE_0 };
+static const unsigned int uart_d_rts_e_pins[] = { GPIOE_1 };
+
+/*bank E func3 */
+static const unsigned int pwm_a_pins[] = { GPIOE_0 };
+static const unsigned int pwm_b_pins[] = { GPIOE_1 };
+
+/*bank E func4 */
+static const unsigned int i2c_a_scl_e_pins[] = { GPIOE_0 };
+static const unsigned int i2c_a_sda_e_pins[] = { GPIOE_1 };
+
+/*bank B func1 */
+static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 };
+static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 };
+static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 };
+static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 };
+static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 };
+static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 };
+static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 };
+static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 };
+static const unsigned int emmc_clk_pins[] = { GPIOB_8 };
+static const unsigned int emmc_cmd_pins[] = { GPIOB_10 };
+static const unsigned int emmc_nand_ds_pins[] = { GPIOB_11 };
+
+/*bank B func2 */
+static const unsigned int nand_wen_clk_pins[] = { GPIOB_8 };
+static const unsigned int nand_ale_pins[] = { GPIOB_9 };
+static const unsigned int nand_ren_wr_pins[] = { GPIOB_10 };
+static const unsigned int nand_cle_pins[] = { GPIOB_11 };
+static const unsigned int nand_ce0_pins[] = { GPIOB_12 };
+
+/*bank B func3 */
+static const unsigned int spif_hold_pins[] = { GPIOB_3 };
+static const unsigned int spif_mo_pins[] = { GPIOB_4 };
+static const unsigned int spif_mi_pins[] = { GPIOB_5 };
+static const unsigned int spif_clk_pins[] = { GPIOB_6 };
+static const unsigned int spif_wp_n_pins[] = { GPIOB_7 };
+static const unsigned int spif_cs_pins[] = { GPIOB_13 };
+
+/*bank C func1 */
+static const unsigned int sdcard_d0_pins[] = { GPIOC_0 };
+static const unsigned int sdcard_d1_pins[] = { GPIOC_1 };
+static const unsigned int sdcard_d2_pins[] = { GPIOC_2 };
+static const unsigned int sdcard_d3_pins[] = { GPIOC_3 };
+static const unsigned int sdcard_clk_pins[] = { GPIOC_4 };
+static const unsigned int sdcard_cmd_pins[] = { GPIOC_5 };
+
+/*bank C func2 */
+static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 };
+static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 };
+static const unsigned int uart_b_rx_c_pins[] = { GPIOC_2 };
+static const unsigned int uart_b_tx_c_pins[] = { GPIOC_3 };
+static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 };
+static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 };
+
+/*bank C func3 */
+static const unsigned int spi_a_mosi_c_pins[] = { GPIOC_0 };
+static const unsigned int spi_a_miso_c_pins[] = { GPIOC_1 };
+static const unsigned int spi_a_ss0_c_pins[] = { GPIOC_2 };
+static const unsigned int spi_a_sclk_c_pins[] = { GPIOC_3 };
+static const unsigned int i2c_e_sda_c_pins[] = { GPIOC_5 };
+static const unsigned int i2c_e_scl_c_pins[] = { GPIOC_6 };
+
+/*bank C func4 */
+static const unsigned int pdm_din0_c_pins[] = { GPIOC_0 };
+static const unsigned int pdm_din1_c_pins[] = { GPIOC_1 };
+static const unsigned int pdm_dclk_c_pins[] = { GPIOC_4 };
+
+/*bank X func1*/
+static const unsigned int sdio_d0_x_pins[] = { GPIOX_0 };
+static const unsigned int sdio_d1_x_pins[] = { GPIOX_1 };
+static const unsigned int sdio_d2_x_pins[] = { GPIOX_2 };
+static const unsigned int sdio_d3_x_pins[] = { GPIOX_3 };
+static const unsigned int sdio_clk_x_pins[] = { GPIOX_4 };
+static const unsigned int sdio_cmd_x_pins[] = { GPIOX_5 };
+static const unsigned int tdm_a_dout1_pins[] = { GPIOX_8 };
+static const unsigned int tdm_a_dout0_pins[] = { GPIOX_9 };
+static const unsigned int tdm_a_fs_pins[] = { GPIOX_10 };
+static const unsigned int tdm_a_sclk_pins[] = { GPIOX_11 };
+static const unsigned int uart_a_tx_x12_pins[] = { GPIOX_12 };
+static const unsigned int uart_a_rx_x13_pins[] = { GPIOX_13 };
+static const unsigned int uart_a_cts_pins[] = { GPIOX_14 };
+static const unsigned int uart_a_rts_pins[] = { GPIOX_15 };
+static const unsigned int pwm_e_pins[] = { GPIOX_16 };
+static const unsigned int pwm_f_x_pins[] = { GPIOX_17 };
+static const unsigned int i2c_c_sda_x_pins[] = { GPIOX_18 };
+static const unsigned int i2c_c_scl_x_pins[] = { GPIOX_19 };
+
+/*bank X func2*/
+static const unsigned int uart_e_tx_x_pins[] = { GPIOX_6 };
+static const unsigned int uart_e_rx_x_pins[] = { GPIOX_7 };
+static const unsigned int tdm_a_din1_pins[] = { GPIOX_8 };
+static const unsigned int tdm_a_din0_pins[] = { GPIOX_9 };
+static const unsigned int tdm_a_slv_fs_pins[] = { GPIOX_10 };
+static const unsigned int tdm_a_slv_sclk_pins[] = { GPIOX_11 };
+static const unsigned int i2c_d_sda_x_pins[] = { GPIOX_14 };
+static const unsigned int i2c_d_scl_x_pins[] = { GPIOX_15 };
+
+/*bank X func3*/
+static const unsigned int eth_mdio_pins[] = { GPIOX_0 };
+static const unsigned int eth_mdc_pins[] = { GPIOX_1 };
+static const unsigned int eth_rx_clk_pins[] = { GPIOX_2 };
+static const unsigned int eth_rx_dv_pins[] = { GPIOX_3 };
+static const unsigned int eth_rxd0_pins[] = { GPIOX_4 };
+static const unsigned int eth_rxd1_pins[] = { GPIOX_5 };
+static const unsigned int eth_rxd2_rgmii_pins[] = { GPIOX_6 };
+static const unsigned int eth_rxd3_rgmii_pins[] = { GPIOX_7 };
+static const unsigned int eth_tx_clk_pins[] = { GPIOX_8 };
+static const unsigned int eth_txen_pins[] = { GPIOX_9 };
+static const unsigned int eth_txd0_pins[] = { GPIOX_10 };
+static const unsigned int eth_txd1_pins[] = { GPIOX_11 };
+static const unsigned int eth_txd2_rgmii_pins[] = { GPIOX_12 };
+static const unsigned int eth_txd3_rgmii_pins[] = { GPIOX_13 };
+static const unsigned int uart_a_tx_x14_pins[] = { GPIOX_14 };
+static const unsigned int uart_a_rx_x15_pins[] = { GPIOX_15 };
+static const unsigned int eth_link_led_pins[] = { GPIOX_18 };
+static const unsigned int eth_act_led_pins[] = { GPIOX_19 };
+
+/*bank X func4*/
+static const unsigned int spi_b_mosi_x_pins[] = { GPIOX_8 };
+static const unsigned int spi_b_miso_x_pins[] = { GPIOX_9 };
+static const unsigned int spi_b_ss0_x_pins[] = { GPIOX_10 };
+static const unsigned int spi_b_sclk_x_pins[] = { GPIOX_11 };
+static const unsigned int pwm_h_x_pins[] = { GPIOX_14 };
+static const unsigned int pwm_g_x_pins[] = { GPIOX_15 };
+
+/*bank X func5 */
+static const unsigned int pwm_i_x_pins[] = { GPIOX_8 };
+static const unsigned int pwm_j_x_pins[] = { GPIOX_9 };
+static const unsigned int i2c_b_sda_x_pins[] = { GPIOX_10 };
+static const unsigned int i2c_b_scl_x_pins[] = { GPIOX_11 };
+
+/*bank M func1 */
+static const unsigned int sdio_d0_m_pins[] = { GPIOM_0 };
+static const unsigned int sdio_d1_m_pins[] = { GPIOM_1 };
+static const unsigned int sdio_d2_m_pins[] = { GPIOM_2 };
+static const unsigned int sdio_d3_m_pins[] = { GPIOM_3 };
+static const unsigned int sdio_clk_m_pins[] = { GPIOM_4 };
+static const unsigned int sdio_cmd_m_pins[] = { GPIOM_5 };
+static const unsigned int pwm_f_m_pins[] = { GPIOM_7 };
+static const unsigned int pwm_g_m_pins[] = { GPIOM_8 };
+static const unsigned int pwm_h_m_pins[] = { GPIOM_9 };
+static const unsigned int clk12_24_M10_pins[] = { GPIOM_10 };
+static const unsigned int clk12_24_M13_pins[] = { GPIOM_13 };
+static const unsigned int i2c_c_sda_m_pins[] = { GPIOM_14 };
+static const unsigned int i2c_c_scl_m_pins[] = { GPIOM_15 };
+
+/*bank M func2 */
+static const unsigned int pwm_i_m_pins[] = { GPIOM_0 };
+static const unsigned int pwm_j_m_pins[] = { GPIOM_1 };
+static const unsigned int pwm_g_hiz_pins[] = { GPIOM_8 };
+static const unsigned int pwm_h_hiz_pins[] = { GPIOM_9 };
+static const unsigned int gen_clk_m10_pins[] = { GPIOM_10 };
+static const unsigned int gen_clk_m13_pins[] = { GPIOM_13 };
+
+/*bank M func3 */
+static const unsigned int pdm_dclk_m_pins[] = { GPIOM_2 };
+static const unsigned int pdm_din0_m_pins[] = { GPIOM_3 };
+static const unsigned int pdm_din1_m_pins[] = { GPIOM_4 };
+static const unsigned int cmclkout1_pins[] = { GPIOM_10 };
+static const unsigned int cmclkout2_pins[] = { GPIOM_13 };
+
+/*bank M func4 */
+static const unsigned int i2c_e_sda_m_pins[] = { GPIOM_0 };
+static const unsigned int i2c_e_scl_m_pins[] = { GPIOM_1 };
+static const unsigned int i2c_b_sda_m_pins[] = { GPIOM_4 };
+static const unsigned int i2c_b_scl_m_pins[] = { GPIOM_5 };
+static const unsigned int i2c_d_sda_m_pins[] = { GPIOM_8 };
+static const unsigned int i2c_d_scl_m_pins[] = { GPIOM_9 };
+static const unsigned int xtal_m10_pins[] = { GPIOM_10 };
+static const unsigned int xtal_m13_pins[] = { GPIOM_13 };
+
+/*bank M func5 */
+static const unsigned int uart_e_cts_pins[] = { GPIOM_2 };
+static const unsigned int uart_e_rts_pins[] = { GPIOM_3 };
+static const unsigned int uart_e_tx_m_pins[] = { GPIOM_4 };
+static const unsigned int uart_e_rx_m_pins[] = { GPIOM_5 };
+static const unsigned int mic_mute_key_pins[] = { GPIOM_6 };
+static const unsigned int mic_mute_led_pins[] = { GPIOM_7 };
+
+/*bank A func1 */
+static const unsigned int mclk_0_pins[] = { GPIOA_0 };
+static const unsigned int tdm_b_sclk_pins[] = { GPIOA_1 };
+static const unsigned int tdm_b_fs_pins[] = { GPIOA_2 };
+static const unsigned int tdm_b_dout0_pins[] = { GPIOA_3 };
+static const unsigned int tdm_b_dout1_pins[] = { GPIOA_4 };
+static const unsigned int tdm_b_dout2_pins[] = { GPIOA_5 };
+static const unsigned int tdm_b_dout3_pins[] = { GPIOA_6 };
+static const unsigned int pwm_g_a7_pins[] = { GPIOA_7 };
+static const unsigned int pwm_h_a8_pins[] = { GPIOA_8 };
+static const unsigned int pwm_i_a9_pins[] = { GPIOA_9 };
+static const unsigned int pwm_j_a10_pins[] = { GPIOA_10 };
+static const unsigned int uart_c_tx_a12_pins[] = { GPIOA_12 };
+static const unsigned int uart_c_rx_a13_pins[] = { GPIOA_13 };
+static const unsigned int i2c_d_sda_a_pins[] = { GPIOA_14 };
+static const unsigned int i2c_d_scl_a_pins[] = { GPIOA_15 };
+
+/*bank A func2 */
+static const unsigned int tdm_b_slv_sclk_pins[] = { GPIOA_1 };
+static const unsigned int tdm_b_slv_fs_pins[] = { GPIOA_2 };
+static const unsigned int tdm_b_din0_pins[] = { GPIOA_3 };
+static const unsigned int tdm_b_din1_pins[] = { GPIOA_4 };
+static const unsigned int tdm_b_din2_pins[] = { GPIOA_5 };
+static const unsigned int tdm_b_din3_pins[] = { GPIOA_6 };
+
+/*bank A func3 */
+static const unsigned int pwm_g_a1_pins[] = { GPIOA_1 };
+static const unsigned int pwm_h_a2_pins[] = { GPIOA_2 };
+static const unsigned int pwm_i_a3_pins[] = { GPIOA_3 };
+static const unsigned int pwm_j_a4_pins[] = { GPIOA_4 };
+static const unsigned int spi_a_mosi_a_pins[] = { GPIOA_5 };
+static const unsigned int spi_a_miso_a_pins[] = { GPIOA_6 };
+static const unsigned int spi_a_sclk_a_pins[] = { GPIOA_7 };
+static const unsigned int spi_a_ss0_a_pins[] = { GPIOA_8 };
+static const unsigned int spi_a_ss1_pins[] = { GPIOA_9 };
+static const unsigned int spi_a_ss2_pins[] = { GPIOA_10 };
+static const unsigned int spi_b_mosi_a_pins[] = { GPIOA_11 };
+static const unsigned int spi_b_miso_a_pins[] = { GPIOA_12 };
+static const unsigned int spi_b_sclk_a_pins[] = { GPIOA_13 };
+static const unsigned int spi_b_ss0_a_pins[] = { GPIOA_14 };
+static const unsigned int spi_b_ss1_pins[] = { GPIOA_15 };
+
+/*bank A func4 */
+static const unsigned int uart_c_tx_a1_pins[] = { GPIOA_1 };
+static const unsigned int uart_c_rx_a2_pins[] = { GPIOA_2 };
+static const unsigned int uart_c_cts_pins[] = { GPIOA_3 };
+static const unsigned int uart_c_rts_pins[] = { GPIOA_4 };
+static const unsigned int uart_d_tx_a_pins[] = { GPIOA_5 };
+static const unsigned int uart_d_rx_a_pins[] = { GPIOA_6 };
+static const unsigned int uart_d_cts_a_pins[] = { GPIOA_7 };
+static const unsigned int uart_d_rts_a_pins[] = { GPIOA_8 };
+static const unsigned int i2c_e_sda_a_pins[] = { GPIOA_12 };
+static const unsigned int i2c_e_scl_a_pins[] = { GPIOA_13 };
+
+/*bank A func5 */
+static const unsigned int mclk_vad_pins[] = { GPIOA_0 };
+static const unsigned int tdm_vad_sclk_a1_pins[] = { GPIOA_1 };
+static const unsigned int tdm_vad_fs_a2_pins[] = { GPIOA_2 };
+static const unsigned int tdm_vad_sclk_a5_pins[] = { GPIOA_5 };
+static const unsigned int tdm_vad_fs_a6_pins[] = { GPIOA_6 };
+static const unsigned int i2c_b_sda_a_pins[] = { GPIOA_7 };
+static const unsigned int i2c_b_scl_a_pins[] = { GPIOA_8 };
+static const unsigned int i2c_c_sda_a_pins[] = { GPIOA_9 };
+static const unsigned int i2c_c_scl_a_pins[] = { GPIOA_10 };
+
+static struct meson_pmx_group meson_c1_periphs_groups[] = {
+ GPIO_GROUP(GPIOD_0),
+ GPIO_GROUP(GPIOD_1),
+ GPIO_GROUP(GPIOD_2),
+ GPIO_GROUP(GPIOD_3),
+ GPIO_GROUP(GPIOD_4),
+ GPIO_GROUP(GPIOD_5),
+ GPIO_GROUP(GPIOD_6),
+ GPIO_GROUP(GPIOD_7),
+ GPIO_GROUP(GPIOD_8),
+ GPIO_GROUP(GPIOD_9),
+ GPIO_GROUP(GPIOD_10),
+ GPIO_GROUP(GPIOD_11),
+ GPIO_GROUP(GPIOD_12),
+ GPIO_GROUP(GPIOE_0),
+ GPIO_GROUP(GPIOE_1),
+ GPIO_GROUP(GPIOB_0),
+ GPIO_GROUP(GPIOB_1),
+ GPIO_GROUP(GPIOB_2),
+ GPIO_GROUP(GPIOB_3),
+ GPIO_GROUP(GPIOB_4),
+ GPIO_GROUP(GPIOB_5),
+ GPIO_GROUP(GPIOB_6),
+ GPIO_GROUP(GPIOB_7),
+ GPIO_GROUP(GPIOB_8),
+ GPIO_GROUP(GPIOB_9),
+ GPIO_GROUP(GPIOB_10),
+ GPIO_GROUP(GPIOB_11),
+ GPIO_GROUP(GPIOB_12),
+ GPIO_GROUP(GPIOB_13),
+ GPIO_GROUP(GPIOC_0),
+ GPIO_GROUP(GPIOC_1),
+ GPIO_GROUP(GPIOC_2),
+ GPIO_GROUP(GPIOC_3),
+ GPIO_GROUP(GPIOC_4),
+ GPIO_GROUP(GPIOC_5),
+ GPIO_GROUP(GPIOC_6),
+ GPIO_GROUP(GPIOC_7),
+ GPIO_GROUP(GPIOX_0),
+ GPIO_GROUP(GPIOX_1),
+ GPIO_GROUP(GPIOX_2),
+ GPIO_GROUP(GPIOX_3),
+ GPIO_GROUP(GPIOX_4),
+ GPIO_GROUP(GPIOX_5),
+ GPIO_GROUP(GPIOX_6),
+ GPIO_GROUP(GPIOX_7),
+ GPIO_GROUP(GPIOX_8),
+ GPIO_GROUP(GPIOX_9),
+ GPIO_GROUP(GPIOX_10),
+ GPIO_GROUP(GPIOX_11),
+ GPIO_GROUP(GPIOX_12),
+ GPIO_GROUP(GPIOX_13),
+ GPIO_GROUP(GPIOX_14),
+ GPIO_GROUP(GPIOX_15),
+ GPIO_GROUP(GPIOX_16),
+ GPIO_GROUP(GPIOX_17),
+ GPIO_GROUP(GPIOX_18),
+ GPIO_GROUP(GPIOX_19),
+ GPIO_GROUP(GPIOM_0),
+ GPIO_GROUP(GPIOM_1),
+ GPIO_GROUP(GPIOM_2),
+ GPIO_GROUP(GPIOM_3),
+ GPIO_GROUP(GPIOM_4),
+ GPIO_GROUP(GPIOM_5),
+ GPIO_GROUP(GPIOM_6),
+ GPIO_GROUP(GPIOM_7),
+ GPIO_GROUP(GPIOM_8),
+ GPIO_GROUP(GPIOM_9),
+ GPIO_GROUP(GPIOM_10),
+ GPIO_GROUP(GPIOM_11),
+ GPIO_GROUP(GPIOM_12),
+ GPIO_GROUP(GPIOM_13),
+ GPIO_GROUP(GPIOM_14),
+ GPIO_GROUP(GPIOM_15),
+ GPIO_GROUP(GPIOA_0),
+ GPIO_GROUP(GPIOA_1),
+ GPIO_GROUP(GPIOA_2),
+ GPIO_GROUP(GPIOA_3),
+ GPIO_GROUP(GPIOA_4),
+ GPIO_GROUP(GPIOA_5),
+ GPIO_GROUP(GPIOA_6),
+ GPIO_GROUP(GPIOA_7),
+ GPIO_GROUP(GPIOA_8),
+ GPIO_GROUP(GPIOA_9),
+ GPIO_GROUP(GPIOA_10),
+ GPIO_GROUP(GPIOA_11),
+ GPIO_GROUP(GPIOA_12),
+ GPIO_GROUP(GPIOA_13),
+ GPIO_GROUP(GPIOA_14),
+ GPIO_GROUP(GPIOA_15),
+ GPIO_GROUP(GPIO_TEST_N),
+
+ /* bank D func1 */
+ GROUP(uart_b_tx_d, 1),
+ GROUP(uart_b_rx_d, 1),
+ GROUP(i2c_a_scl_d, 1),
+ GROUP(i2c_a_sda_d, 1),
+ GROUP(ir_out_d4, 1),
+ GROUP(ir_in_d5, 1),
+ GROUP(jtag_a_clk, 1),
+ GROUP(jtag_a_tms, 1),
+ GROUP(jtag_a_tdi, 1),
+ GROUP(jtag_a_tdo, 1),
+ GROUP(gen_clk_d, 1),
+ GROUP(clk12_24_d, 1),
+
+ /* bank D func2 */
+ GROUP(uart_d_tx_d2, 2),
+ GROUP(uart_d_rx_d3, 2),
+ GROUP(swclk, 2),
+ GROUP(swdio, 2),
+ GROUP(ir_in_d8, 2),
+ GROUP(ir_out_d9, 2),
+ GROUP(clk25, 2),
+
+ /* bank D func3 */
+ GROUP(i2c_slave_scl, 3),
+ GROUP(i2c_slave_sda, 3),
+ GROUP(pwm_d, 3),
+ GROUP(pwm_c, 3),
+ GROUP(pwm_f_d, 3),
+ GROUP(uart_d_tx_d8, 3),
+ GROUP(uart_d_rx_d9, 3),
+ GROUP(pwm_g_d, 3),
+ GROUP(clk_32k_in, 3),
+
+ /* bank D func4 */
+ GROUP(pwm_d_hiz, 4),
+ GROUP(pwm_c_hiz, 4),
+ GROUP(pwm_f_hiz, 4),
+
+ /* bank E func1 */
+ GROUP(uart_b_cts, 1),
+ GROUP(uart_b_rts, 1),
+
+ /* bank E func2 */
+ GROUP(uart_d_cts_e, 2),
+ GROUP(uart_d_rts_e, 2),
+
+ /* bank E func3 */
+ GROUP(pwm_a, 3),
+ GROUP(pwm_b, 3),
+
+ /* bank E func4 */
+ GROUP(i2c_a_scl_e, 4),
+ GROUP(i2c_a_sda_e, 4),
+
+ /* bank B func1 */
+ GROUP(emmc_nand_d0, 1),
+ GROUP(emmc_nand_d1, 1),
+ GROUP(emmc_nand_d2, 1),
+ GROUP(emmc_nand_d3, 1),
+ GROUP(emmc_nand_d4, 1),
+ GROUP(emmc_nand_d5, 1),
+ GROUP(emmc_nand_d6, 1),
+ GROUP(emmc_nand_d7, 1),
+ GROUP(emmc_clk, 1),
+ GROUP(emmc_cmd, 1),
+ GROUP(emmc_nand_ds, 1),
+
+ /* bank B func2 */
+ GROUP(nand_wen_clk, 2),
+ GROUP(nand_ale, 2),
+ GROUP(nand_ren_wr, 2),
+ GROUP(nand_cle, 2),
+ GROUP(nand_ce0, 2),
+
+ /* bank B func3 */
+ GROUP(spif_hold, 3),
+ GROUP(spif_mo, 3),
+ GROUP(spif_mi, 3),
+ GROUP(spif_clk, 3),
+ GROUP(spif_wp_n, 3),
+ GROUP(spif_cs, 3),
+
+ /* bank C func1 */
+ GROUP(sdcard_d0, 1),
+ GROUP(sdcard_d1, 1),
+ GROUP(sdcard_d2, 1),
+ GROUP(sdcard_d3, 1),
+ GROUP(sdcard_clk, 1),
+ GROUP(sdcard_cmd, 1),
+
+ /* bank C func2 */
+ GROUP(jtag_b_tdo, 2),
+ GROUP(jtag_b_tdi, 2),
+ GROUP(uart_b_rx_c, 2),
+ GROUP(uart_b_tx_c, 2),
+ GROUP(jtag_b_clk, 2),
+ GROUP(jtag_b_tms, 2),
+
+ /* bank C func3 */
+ GROUP(spi_a_mosi_c, 3),
+ GROUP(spi_a_miso_c, 3),
+ GROUP(spi_a_ss0_c, 3),
+ GROUP(spi_a_sclk_c, 3),
+ GROUP(i2c_e_sda_c, 3),
+ GROUP(i2c_e_scl_c, 3),
+
+ /* bank C func4 */
+ GROUP(pdm_din0_c, 4),
+ GROUP(pdm_din1_c, 4),
+ GROUP(pdm_dclk_c, 4),
+
+ /* bank X func1 */
+ GROUP(sdio_d0_x, 1),
+ GROUP(sdio_d1_x, 1),
+ GROUP(sdio_d2_x, 1),
+ GROUP(sdio_d3_x, 1),
+ GROUP(sdio_clk_x, 1),
+ GROUP(sdio_cmd_x, 1),
+ GROUP(tdm_a_dout1, 1),
+ GROUP(tdm_a_dout0, 1),
+ GROUP(tdm_a_fs, 1),
+ GROUP(tdm_a_sclk, 1),
+ GROUP(uart_a_tx_x12, 1),
+ GROUP(uart_a_rx_x13, 1),
+ GROUP(uart_a_cts, 1),
+ GROUP(uart_a_rts, 1),
+ GROUP(pwm_e, 1),
+ GROUP(pwm_f_x, 1),
+ GROUP(i2c_c_sda_x, 1),
+ GROUP(i2c_c_scl_x, 1),
+
+ /* bank X func2 */
+ GROUP(uart_e_tx_x, 2),
+ GROUP(uart_e_rx_x, 2),
+ GROUP(tdm_a_din1, 2),
+ GROUP(tdm_a_din0, 2),
+ GROUP(tdm_a_slv_fs, 2),
+ GROUP(tdm_a_slv_sclk, 2),
+ GROUP(i2c_d_sda_x, 2),
+ GROUP(i2c_d_scl_x, 2),
+
+ /* bank X func3 */
+ GROUP(eth_mdio, 3),
+ GROUP(eth_mdc, 3),
+ GROUP(eth_rx_clk, 3),
+ GROUP(eth_rx_dv, 3),
+ GROUP(eth_rxd0, 3),
+ GROUP(eth_rxd1, 3),
+ GROUP(eth_rxd2_rgmii, 3),
+ GROUP(eth_rxd3_rgmii, 3),
+ GROUP(eth_tx_clk, 3),
+ GROUP(eth_txen, 3),
+ GROUP(eth_txd0, 3),
+ GROUP(eth_txd1, 3),
+ GROUP(eth_txd2_rgmii, 3),
+ GROUP(eth_txd3_rgmii, 3),
+ GROUP(uart_a_tx_x14, 3),
+ GROUP(uart_a_rx_x15, 3),
+ GROUP(eth_link_led, 3),
+ GROUP(eth_act_led, 3),
+
+ /* bank X func4 */
+ GROUP(spi_b_mosi_x, 4),
+ GROUP(spi_b_miso_x, 4),
+ GROUP(spi_b_ss0_x, 4),
+ GROUP(spi_b_sclk_x, 4),
+ GROUP(pwm_h_x, 4),
+ GROUP(pwm_g_x, 4),
+
+ /* bank X func5 */
+ GROUP(pwm_i_x, 5),
+ GROUP(pwm_j_x, 5),
+ GROUP(i2c_b_sda_x, 5),
+ GROUP(i2c_b_scl_x, 5),
+
+ /* bank M func1 */
+ GROUP(sdio_d0_m, 1),
+ GROUP(sdio_d1_m, 1),
+ GROUP(sdio_d2_m, 1),
+ GROUP(sdio_d3_m, 1),
+ GROUP(sdio_clk_m, 1),
+ GROUP(sdio_cmd_m, 1),
+ GROUP(pwm_f_m, 1),
+ GROUP(pwm_g_m, 1),
+ GROUP(pwm_h_m, 1),
+ GROUP(clk12_24_M10, 1),
+ GROUP(clk12_24_M13, 1),
+ GROUP(i2c_c_sda_m, 1),
+ GROUP(i2c_c_scl_m, 1),
+
+ /* bank M func2 */
+ GROUP(pwm_i_m, 2),
+ GROUP(pwm_j_m, 2),
+ GROUP(pwm_g_hiz, 2),
+ GROUP(pwm_h_hiz, 2),
+ GROUP(gen_clk_m10, 2),
+ GROUP(gen_clk_m13, 2),
+
+ /* bank M func3 */
+ GROUP(pdm_dclk_m, 3),
+ GROUP(pdm_din0_m, 3),
+ GROUP(pdm_din1_m, 3),
+ GROUP(cmclkout1, 3),
+ GROUP(cmclkout2, 3),
+
+ /* bank M func4 */
+ GROUP(i2c_e_sda_m, 4),
+ GROUP(i2c_e_scl_m, 4),
+ GROUP(i2c_b_sda_m, 4),
+ GROUP(i2c_b_scl_m, 4),
+ GROUP(i2c_d_sda_m, 4),
+ GROUP(i2c_d_scl_m, 4),
+ GROUP(xtal_m10, 4),
+ GROUP(xtal_m13, 4),
+
+ /* bank M func5 */
+ GROUP(uart_e_cts, 5),
+ GROUP(uart_e_rts, 5),
+ GROUP(uart_e_tx_m, 5),
+ GROUP(uart_e_rx_m, 5),
+ GROUP(mic_mute_key, 5),
+ GROUP(mic_mute_led, 5),
+
+ /* bank A func1 */
+ GROUP(mclk_0, 1),
+ GROUP(tdm_b_sclk, 1),
+ GROUP(tdm_b_fs, 1),
+ GROUP(tdm_b_dout0, 1),
+ GROUP(tdm_b_dout1, 1),
+ GROUP(tdm_b_dout2, 1),
+ GROUP(tdm_b_dout3, 1),
+ GROUP(pwm_g_a7, 1),
+ GROUP(pwm_h_a8, 1),
+ GROUP(pwm_i_a9, 1),
+ GROUP(pwm_j_a10, 1),
+ GROUP(uart_c_tx_a12, 1),
+ GROUP(uart_c_rx_a13, 1),
+ GROUP(i2c_d_sda_a, 1),
+ GROUP(i2c_d_scl_a, 1),
+
+ /* bank A func2 */
+ GROUP(tdm_b_slv_sclk, 2),
+ GROUP(tdm_b_slv_fs, 2),
+ GROUP(tdm_b_din0, 2),
+ GROUP(tdm_b_din1, 2),
+ GROUP(tdm_b_din2, 2),
+ GROUP(tdm_b_din3, 2),
+
+ /* bank A func3 */
+ GROUP(pwm_g_a1, 3),
+ GROUP(pwm_h_a2, 3),
+ GROUP(pwm_i_a3, 3),
+ GROUP(pwm_j_a4, 3),
+ GROUP(spi_a_mosi_a, 3),
+ GROUP(spi_a_miso_a, 3),
+ GROUP(spi_a_sclk_a, 3),
+ GROUP(spi_a_ss0_a, 3),
+ GROUP(spi_a_ss1, 3),
+ GROUP(spi_a_ss2, 3),
+ GROUP(spi_b_mosi_a, 3),
+ GROUP(spi_b_miso_a, 3),
+ GROUP(spi_b_sclk_a, 3),
+ GROUP(spi_b_ss0_a, 3),
+ GROUP(spi_b_ss1, 3),
+
+ /* bank A func4 */
+ GROUP(uart_c_tx_a1, 4),
+ GROUP(uart_c_rx_a2, 4),
+ GROUP(uart_c_cts, 4),
+ GROUP(uart_c_rts, 4),
+ GROUP(uart_d_tx_a, 4),
+ GROUP(uart_d_rx_a, 4),
+ GROUP(uart_d_cts_a, 4),
+ GROUP(uart_d_rts_a, 4),
+ GROUP(i2c_e_sda_a, 4),
+ GROUP(i2c_e_scl_a, 4),
+
+ /* bank A func5 */
+ GROUP(mclk_vad, 5),
+ GROUP(tdm_vad_sclk_a1, 5),
+ GROUP(tdm_vad_fs_a2, 5),
+ GROUP(tdm_vad_sclk_a5, 5),
+ GROUP(tdm_vad_fs_a6, 5),
+ GROUP(i2c_b_sda_a, 5),
+ GROUP(i2c_b_scl_a, 5),
+ GROUP(i2c_c_sda_a, 5),
+ GROUP(i2c_c_scl_a, 5),
+};
+
+static const char * const gpio_periphs_groups[] = {
+ "GPIO_TEST_N",
+
+ "GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4",
+ "GPIOD_5", "GPIOD_6", "GPIOD_7", "GPIOD_8", "GPIOD_9",
+ "GPIOD_10", "GPIOD_11", "GPIOD_12",
+
+ "GPIOE_0", "GPIOE_1",
+
+ "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4",
+ "GPIOB_5", "GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9",
+ "GPIOB_10", "GPIOB_11", "GPIOB_12", "GPIOB_13",
+
+ "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4",
+ "GPIOC_5", "GPIOC_6", "GPIOC_7",
+
+ "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
+ "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
+ "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
+ "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
+
+ "GPIOM_0", "GPIOM_1", "GPIOM_2", "GPIOM_3", "GPIOM_4",
+ "GPIOM_5", "GPIOM_6", "GPIOM_7", "GPIOM_8", "GPIOM_9",
+ "GPIOM_10", "GPIOM_11", "GPIOM_12", "GPIOM_13", "GPIOM_14",
+ "GPIOM_15",
+
+ "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4",
+ "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9",
+ "GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14",
+ "GPIOA_15",
+};
+
+static const char * const uart_a_groups[] = {
+ "uart_a_tx_x12", "uart_a_rx_x13", "uart_a_cts", "uart_a_rts",
+ "uart_a_tx_x14", "uart_a_rx_x15",
+};
+
+static const char * const uart_b_groups[] = {
+ "uart_b_tx_d", "uart_b_rx_d", "uart_b_cts", "uart_b_rts",
+ "uart_b_rx_c", "uart_b_tx_c",
+};
+
+static const char * const uart_c_groups[] = {
+ "uart_c_tx_a12", "uart_c_rx_a13", "uart_c_tx_a1", "uart_c_rx_a2",
+ "uart_c_cts", "uart_c_rts",
+};
+
+static const char * const uart_d_groups[] = {
+ "uart_d_tx_d2", "uart_d_rx_d3", "uart_d_tx_d8", "uart_d_rx_d9",
+ "uart_d_cts_e", "uart_d_rts_e", "uart_d_tx_a", "uart_d_tx_a",
+ "uart_d_cts_a", "uart_d_rts_a",
+};
+
+static const char * const uart_e_groups[] = {
+ "uart_e_tx_x", "uart_e_rx_x", "uart_e_cts", "uart_e_rts", "uart_e_tx_m",
+ "uart_e_rx_m",
+};
+
+static const char * const i2c_a_groups[] = {
+ "i2c_a_scl_d", "i2c_a_sda_d", "i2c_a_scl_e", "i2c_a_sda_e",
+};
+
+static const char * const i2c_b_groups[] = {
+ "i2c_b_sda_x", "i2c_b_scl_x", "i2c_b_sda_a", "i2c_b_scl_a",
+ "i2c_b_sda_m", "i2c_b_scl_m",
+};
+
+static const char * const i2c_c_groups[] = {
+ "i2c_c_sda_x", "i2c_c_scl_x", "i2c_c_sda_m", "i2c_c_scl_m",
+ "i2c_c_sda_a", "i2c_c_scl_a",
+};
+
+static const char * const i2c_d_groups[] = {
+ "i2c_d_sda_x", "i2c_d_scl_x", "i2c_d_sda_a", "i2c_d_scl_a",
+ "i2c_d_sda_m", "i2c_d_scl_m",
+};
+
+static const char * const i2c_e_groups[] = {
+ "i2c_e_sda_c", "i2c_e_scl_c", "i2c_e_sda_m", "i2c_e_scl_m",
+ "i2c_e_sda_a", "i2c_e_scl_a",
+};
+
+static const char * const i2c_slave_groups[] = {
+ "i2c_slave_scl", "i2c_slave_sda",
+};
+
+static const char * const pwm_a_groups[] = {
+ "pwm_a",
+};
+
+static const char * const pwm_b_groups[] = {
+ "pwm_b",
+};
+
+static const char * const pwm_c_groups[] = {
+ "pwm_c",
+};
+
+static const char * const pwm_d_groups[] = {
+ "pwm_d",
+};
+
+static const char * const pwm_e_groups[] = {
+ "pwm_e",
+};
+
+static const char * const pwm_f_groups[] = {
+ "pwm_f_d", "pwm_f_m", "pwm_f_x"
+};
+
+static const char * const pwm_g_groups[] = {
+ "pwm_g_d", "pwm_g_x", "pwm_g_m", "pwm_g_a7",
+ "pwm_g_a1",
+};
+
+static const char * const pwm_h_groups[] = {
+ "pwm_h_x", "pwm_h_m", "pwm_h_a8", "pwm_h_a2",
+};
+
+static const char * const pwm_i_groups[] = {
+ "pwm_i_x", "pwm_i_m", "pwm_i_a9", "pwm_i_a3",
+};
+
+static const char * const pwm_j_groups[] = {
+ "pwm_j_x", "pwm_j_m", "pwm_j_a10", "pwm_j_a4",
+};
+
+static const char * const pwm_c_hiz_groups[] = {
+ "pwm_c_hiz",
+};
+
+static const char * const pwm_d_hiz_groups[] = {
+ "pwm_d_hiz",
+};
+
+static const char * const pwm_f_hiz_groups[] = {
+ "pwm_f_hiz",
+};
+
+static const char * const pwm_g_hiz_groups[] = {
+ "pwm_g_hiz",
+};
+
+static const char * const pwm_h_hiz_groups[] = {
+ "pwm_h_hiz",
+};
+
+static const char * const ir_out_groups[] = {
+ "ir_out_d4", "ir_out_d9",
+};
+
+static const char * const ir_in_groups[] = {
+ "ir_in_d5", "ir_in_d8",
+};
+
+static const char * const jtag_a_groups[] = {
+ "jtag_a_clk", "jtag_a_tms", "jtag_a_tdi", "jtag_a_tdo",
+};
+
+static const char * const jtag_b_groups[] = {
+ "jtag_b_tdo", "jtag_b_tdi", "jtag_b_clk", "jtag_b_tms",
+};
+
+static const char * const gen_clk_groups[] = {
+ "gen_clk_d", "gen_clk_m10", "gen_clk_m13",
+};
+
+static const char * const clk12_24_groups[] = {
+ "clk12_24_d", "clk12_24_m10", "clk12_24_m13",
+};
+
+static const char * const sw_groups[] = {
+ "swclk", "swdio",
+};
+
+static const char * const clk25_groups[] = {
+ "clk25",
+};
+
+static const char * const clk_32k_in_groups[] = {
+ "clk_32k_in",
+};
+
+static const char * const emmc_groups[] = {
+ "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3",
+ "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7",
+ "emmc_clk", "emmc_cmd", "emmc_nand_ds",
+};
+
+static const char * const nand_groups[] = {
+ "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3",
+ "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7",
+ "emmc_nand_ds", "nand_wen_clk", "nand_ale", "nand_ren_wr",
+ "nand_cle", "nand_ce0",
+};
+
+static const char * const spif_groups[] = {
+ "spif_hold", "spif_mo", "spif_mi", "spif_clk",
+ "spif_wp_n", "spif_cs",
+};
+
+static const char * const sdcard_groups[] = {
+ "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
+ "sdcard_clk", "sdcard_cmd",
+};
+
+static const char * const spi_a_groups[] = {
+ "spi_a_mosi_c", "spi_a_miso_c", "spi_a_ss0_c", "spi_a_sclk_c",
+ "spi_a_mosi_a", "spi_a_miso_a", "spi_a_sclk_a", "spi_a_ss0_a",
+ "spi_a_ss1", "spi_a_ss2",
+};
+
+static const char * const pdm_groups[] = {
+ "pdm_din0_c", "pdm_din1_c", "pdm_dclk_c", "pdm_dlck_m",
+ "pdm_din0_m", "pdm_din1_m",
+};
+
+static const char * const sdio_groups[] = {
+ "sdio_d0_x", "sdio_d1_x", "sdio_d2_x", "sdio_d3_x",
+ "sdio_clk_x", "sdio_cmd_x",
+
+ "sdio_d0_m", "sdio_d1_m", "sdio_d2_m", "sdio_d3_m",
+ "sdio_clk_m", "sdio_cmd_m",
+};
+
+static const char * const eth_groups[] = {
+ "eth_mdio", "eth_mdc", "eth_rx_clk", "eth_rx_dv",
+ "eth_rxd0", "eth_rxd1", "eth_rxd2_rgmii", "eth_rxd3_rgmii",
+ "eth_tx_clk", "eth_txen", "eth_txd0", "eth_txd1",
+ "eth_txd2_rgmii", "eth_txd3_rgmii", "eth_link_led", "eth_act_led",
+};
+
+static const char * const spi_b_groups[] = {
+ "spi_b_mosi_x", "spi_b_miso_x", "spi_b_ss0_x", "spi_b_sclk_x",
+ "spi_b_mosi_a", "spi_b_miso_a", "spi_b_ss0_a", "spi_b_sclk_a",
+ "spi_b_ss1",
+};
+
+static const char * const cmclkout_groups[] = {
+ "cmclkout1", "cmclkout2",
+};
+
+static const char * const xtal_groups[] = {
+ "xtal_m10", "xtal_m13",
+};
+
+static const char * const mic_mute_groups[] = {
+ "mic_mute_key", "mic_mute_led",
+};
+
+static const char * const mclk_0_groups[] = {
+ "mclk_0",
+};
+
+static const char * const tdm_a_groups[] = {
+ "tdm_a_dout1", "tdm_a_dout0", "tdm_a_fs", "tdm_a_sclk",
+ "tdm_a_din1", "tdm_a_din0", "tdm_a_slv_fs", "tdm_a_slv_sclk",
+};
+
+static const char * const tdm_b_groups[] = {
+ "tdm_b_sclk", "tdm_b_fs", "tdm_b_dout0", "tdm_b_dout1",
+ "tdm_b_dout2", "tdm_b_dout3",
+
+ "tdm_b_slv_sclk", "tdm_b_slv_fs", "tdm_b_din0", "tdm_b_din1",
+ "tdm_b_din2", "tdm_b_din3",
+};
+
+static const char * const tdm_vad_groups[] = {
+ "tdm_vad_sclk_a1", "tdm_vad_fs_a2", "tdm_vad_sclk_a5", "tdm_vad_fs_a6",
+};
+
+static const char * const mclk_vad_groups[] = {
+ "mclk_vad",
+};
+
+static struct meson_pmx_func meson_c1_periphs_functions[] = {
+ FUNCTION(gpio_periphs),
+ FUNCTION(uart_a),
+ FUNCTION(uart_b),
+ FUNCTION(uart_c),
+ FUNCTION(uart_d),
+ FUNCTION(uart_e),
+ FUNCTION(i2c_a),
+ FUNCTION(i2c_b),
+ FUNCTION(i2c_c),
+ FUNCTION(i2c_d),
+ FUNCTION(i2c_e),
+ FUNCTION(i2c_slave),
+ FUNCTION(pwm_a),
+ FUNCTION(pwm_b),
+ FUNCTION(pwm_c),
+ FUNCTION(pwm_d),
+ FUNCTION(pwm_e),
+ FUNCTION(pwm_f),
+ FUNCTION(pwm_g),
+ FUNCTION(pwm_h),
+ FUNCTION(pwm_i),
+ FUNCTION(pwm_j),
+ FUNCTION(pwm_c_hiz),
+ FUNCTION(pwm_d_hiz),
+ FUNCTION(pwm_f_hiz),
+ FUNCTION(pwm_g_hiz),
+ FUNCTION(pwm_h_hiz),
+ FUNCTION(ir_out),
+ FUNCTION(ir_in),
+ FUNCTION(jtag_a),
+ FUNCTION(jtag_b),
+ FUNCTION(gen_clk),
+ FUNCTION(clk12_24),
+ FUNCTION(sw),
+ FUNCTION(clk25),
+ FUNCTION(clk_32k_in),
+ FUNCTION(emmc),
+ FUNCTION(nand),
+ FUNCTION(spif),
+ FUNCTION(sdcard),
+ FUNCTION(spi_a),
+ FUNCTION(pdm),
+ FUNCTION(sdio),
+ FUNCTION(eth),
+ FUNCTION(spi_b),
+ FUNCTION(cmclkout),
+ FUNCTION(xtal),
+ FUNCTION(mic_mute),
+ FUNCTION(mclk_0),
+ FUNCTION(tdm_a),
+ FUNCTION(tdm_b),
+ FUNCTION(tdm_vad),
+ FUNCTION(mclk_vad),
+};
+
+static struct meson_bank meson_c1_periphs_banks[] = {
+ /* name first last irq pullen pull dir out in */
+ BANK("GPIOD_", GPIOD_0, GPIOD_12,
+ 0x3, 0, 0x4, 0, 0x2, 0, 0x1, 0, 0x0, 0),
+ BANK("GPIOE_", GPIOE_0, GPIOE_1,
+ 0x13, 0, 0x14, 0, 0x12, 0, 0x11, 0, 0x10, 0),
+ BANK("GPIOB_", GPIOB_0, GPIOB_13,
+ 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0),
+ BANK("GPIOC_", GPIOC_0, GPIOC_7,
+ 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0),
+ BANK("GPIOX_", GPIOX_0, GPIOX_19,
+ 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0),
+ BANK("GPIOM_", GPIOM_0, GPIOM_15,
+ 0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0),
+ BANK("GPIOA_", GPIOA_0, GPIOA_15,
+ 0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0),
+ BANK("GPIO_TEST_N", GPIO_TEST_N, GPIO_TEST_N,
+ 0x73, 0, 0x74, 0, 0x72, 0, 0x71, 0, 0x70, 0),
+};
+
+static struct meson_pmx_bank meson_c1_periphs_pmx_banks[] = {
+ /*name first lask reg offset*/
+ BANK_PMX("D", GPIOD_0, GPIOD_12, 0x0, 0),
+ BANK_PMX("E", GPIOE_0, GPIOE_1, 0x2, 0),
+ BANK_PMX("B", GPIOB_0, GPIOB_13, 0x3, 0),
+ BANK_PMX("C", GPIOC_0, GPIOC_7, 0x5, 0),
+ BANK_PMX("X", GPIOX_0, GPIOX_19, 0x6, 0),
+ BANK_PMX("M", GPIOM_0, GPIOM_15, 0x9, 0),
+ BANK_PMX("A", GPIOA_0, GPIOA_15, 0xb, 0),
+ BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0xf, 0),
+};
+
+static struct meson_drive_bank meson_c1_periphs_drive_banks[] = {
+ /* name first lask reg offset*/
+ BANK_DRIVE("D", GPIOD_0, GPIOD_12, 0x5, 0),
+ BANK_DRIVE("E", GPIOE_0, GPIOE_1, 0x15, 0),
+ BANK_DRIVE("B", GPIOB_0, GPIOB_13, 0x25, 0),
+ BANK_DRIVE("C", GPIOC_0, GPIOC_7, 0x35, 0),
+ BANK_DRIVE("X", GPIOX_0, GPIOX_19, 0x45, 0),
+ BANK_DRIVE("M", GPIOM_0, GPIOM_15, 0x55, 0),
+ BANK_DRIVE("A", GPIOA_0, GPIOA_15, 0x65, 0),
+ BANK_DRIVE("TESTN", GPIO_TEST_N, GPIO_TEST_N, 0x75, 0),
+};
+
+static struct meson_axg_pmx_data meson_c1_periphs_pmx_banks_data = {
+ .pmx_banks = meson_c1_periphs_pmx_banks,
+ .num_pmx_banks = ARRAY_SIZE(meson_c1_periphs_pmx_banks),
+};
+
+static struct meson_drive_data meson_c1_periphs_drive_data = {
+ .drive_banks = meson_c1_periphs_drive_banks,
+ .num_drive_banks = ARRAY_SIZE(meson_c1_periphs_drive_banks),
+};
+
+static struct meson_pinctrl_data meson_c1_periphs_pinctrl_data = {
+ .name = "periphs-banks",
+ .groups = meson_c1_periphs_groups,
+ .funcs = meson_c1_periphs_functions,
+ .banks = meson_c1_periphs_banks,
+ .num_pins = 90,
+ .num_groups = ARRAY_SIZE(meson_c1_periphs_groups),
+ .num_funcs = ARRAY_SIZE(meson_c1_periphs_functions),
+ .num_banks = ARRAY_SIZE(meson_c1_periphs_banks),
+ .pmx_data = &meson_c1_periphs_pmx_banks_data,
+ .drv_data = &meson_c1_periphs_drive_data,
+};
+
+static const struct udevice_id meson_c1_pinctrl_match[] = {
+ {
+ .compatible = "amlogic,meson-c1-periphs-pinctrl",
+ .data = (ulong)&meson_c1_periphs_pinctrl_data,
+ },
+ { },
+};
+
+U_BOOT_DRIVER(meson_c1_pinctrl) = {
+ .name = "meson-c1-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(meson_c1_pinctrl_match),
+ .probe = meson_pinctrl_probe,
+ .priv_auto_alloc_size = sizeof(struct meson_pinctrl),
+ .ops = &meson_axg_pinctrl_ops,
+};
diff --git a/drivers/pinctrl/meson/pinctrl-meson-c2.c b/drivers/pinctrl/meson/pinctrl-meson-c2.c
new file mode 100644
index 0000000..02260da
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-c2.c
@@ -0,0 +1,1083 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <dt-bindings/gpio/meson-c2-gpio.h>
+
+#include "pinctrl-meson.h"
+#include "pinctrl-meson-axg-pmx.h"
+
+/*bank D func1 */
+static const unsigned int uart_b_tx_d_pins[] = { GPIOD_0 };
+static const unsigned int uart_b_rx_d_pins[] = { GPIOD_1 };
+static const unsigned int i2c_a_scl_d_pins[] = { GPIOD_2 };
+static const unsigned int i2c_a_sda_d_pins[] = { GPIOD_3 };
+static const unsigned int ir_out_d4_pins[] = { GPIOD_4 };
+static const unsigned int ir_in_d5_pins[] = { GPIOD_5 };
+static const unsigned int jtag_a_clk_pins[] = { GPIOD_6 };
+static const unsigned int jtag_a_tms_pins[] = { GPIOD_7 };
+static const unsigned int jtag_a_tdi_pins[] = { GPIOD_8 };
+static const unsigned int jtag_a_tdo_pins[] = { GPIOD_9 };
+static const unsigned int gen_clk_d_pins[] = { GPIOD_11 };
+static const unsigned int clk12_24_d_pins[] = { GPIOD_12 };
+static const unsigned int pwm_g_d13_pins[] = { GPIOD_13 };
+
+/*bank D func2 */
+static const unsigned int uart_d_tx_d2_pins[] = { GPIOD_2 };
+static const unsigned int uart_d_rx_d3_pins[] = { GPIOD_3 };
+static const unsigned int swclk_pins[] = { GPIOD_6 };
+static const unsigned int swdio_pins[] = { GPIOD_7 };
+static const unsigned int ir_in_d8_pins[] = { GPIOD_8 };
+static const unsigned int ir_out_d9_pins[] = { GPIOD_9 };
+static const unsigned int clk25_d_pins[] = { GPIOD_12 };
+
+/*bank D func3 */
+static const unsigned int i2c_slave_scl_pins[] = { GPIOD_2 };
+static const unsigned int i2c_slave_sda_pins[] = { GPIOD_3 };
+static const unsigned int pwm_d_pins[] = { GPIOD_5 };
+static const unsigned int pwm_c_pins[] = { GPIOD_6 };
+static const unsigned int pwm_f_d_pins[] = { GPIOD_7 };
+static const unsigned int uart_d_tx_d8_pins[] = { GPIOD_8 };
+static const unsigned int uart_d_rx_d9_pins[] = { GPIOD_9 };
+static const unsigned int pwm_g_d10_pins[] = { GPIOD_10 };
+static const unsigned int clk_32k_in_pins[] = { GPIOD_12 };
+
+/*bank D func4 */
+static const unsigned int pwm_d_hiz_pins[] = { GPIOD_5 };
+static const unsigned int pwm_c_hiz_pins[] = { GPIOD_6 };
+static const unsigned int pwm_f_hiz_pins[] = { GPIOD_7 };
+static const unsigned int pwm_i_d_pins[] = { GPIOD_8 };
+static const unsigned int pwm_g_d12_pins[] = { GPIOD_12 };
+
+/*bank E func1 */
+static const unsigned int uart_b_cts_pins[] = { GPIOE_0 };
+static const unsigned int uart_b_rts_pins[] = { GPIOE_1 };
+static const unsigned int pwm_h_d_pins[] = { GPIOE_2 };
+
+/*bank E func2 */
+static const unsigned int uart_d_cts_e_pins[] = { GPIOE_0 };
+static const unsigned int uart_d_rts_e_pins[] = { GPIOE_1 };
+static const unsigned int clk25_e_pins[] = { GPIOE_2 };
+
+/*bank E func3 */
+static const unsigned int pwm_a_pins[] = { GPIOE_0 };
+static const unsigned int pwm_b_pins[] = { GPIOE_1 };
+
+/*bank E func4 */
+static const unsigned int i2c_a_scl_e_pins[] = { GPIOE_0 };
+static const unsigned int i2c_a_sda_e_pins[] = { GPIOE_1 };
+
+/*bank B func1 */
+static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 };
+static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 };
+static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 };
+static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 };
+static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 };
+static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 };
+static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 };
+static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 };
+static const unsigned int emmc_clk_pins[] = { GPIOB_8 };
+static const unsigned int emmc_cmd_pins[] = { GPIOB_10 };
+static const unsigned int emmc_nand_ds_pins[] = { GPIOB_11 };
+
+/*bank B func2 */
+static const unsigned int nand_wen_clk_pins[] = { GPIOB_8 };
+static const unsigned int nand_ale_pins[] = { GPIOB_9 };
+static const unsigned int nand_ren_wr_pins[] = { GPIOB_10 };
+static const unsigned int nand_cle_pins[] = { GPIOB_11 };
+static const unsigned int nand_ce0_pins[] = { GPIOB_12 };
+
+/*bank B func3 */
+static const unsigned int spif_hold_pins[] = { GPIOB_3 };
+static const unsigned int spif_mo_pins[] = { GPIOB_4 };
+static const unsigned int spif_mi_pins[] = { GPIOB_5 };
+static const unsigned int spif_clk_pins[] = { GPIOB_6 };
+static const unsigned int spif_wp_n_pins[] = { GPIOB_7 };
+static const unsigned int spif_cs_pins[] = { GPIOB_13 };
+
+/*bank C func1 */
+static const unsigned int sdcard_d0_pins[] = { GPIOC_0 };
+static const unsigned int sdcard_d1_pins[] = { GPIOC_1 };
+static const unsigned int sdcard_d2_pins[] = { GPIOC_2 };
+static const unsigned int sdcard_d3_pins[] = { GPIOC_3 };
+static const unsigned int sdcard_clk_pins[] = { GPIOC_4 };
+static const unsigned int sdcard_cmd_pins[] = { GPIOC_5 };
+
+/*bank C func2 */
+static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 };
+static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 };
+static const unsigned int uart_b_rx_c_pins[] = { GPIOC_2 };
+static const unsigned int uart_b_tx_c_pins[] = { GPIOC_3 };
+static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 };
+static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 };
+
+/*bank C func3 */
+static const unsigned int spi_a_mosi_c_pins[] = { GPIOC_0 };
+static const unsigned int spi_a_miso_c_pins[] = { GPIOC_1 };
+static const unsigned int spi_a_ss0_c_pins[] = { GPIOC_2 };
+static const unsigned int spi_a_sclk_c_pins[] = { GPIOC_3 };
+static const unsigned int i2c_e_sda_c_pins[] = { GPIOC_5 };
+static const unsigned int i2c_e_scl_c_pins[] = { GPIOC_6 };
+
+/*bank C func4 */
+static const unsigned int pdm_din0_c_pins[] = { GPIOC_0 };
+static const unsigned int pdm_dclk_c_pins[] = { GPIOC_4 };
+
+/*bank X func1*/
+static const unsigned int sdio_d0_x_pins[] = { GPIOX_0 };
+static const unsigned int sdio_d1_x_pins[] = { GPIOX_1 };
+static const unsigned int sdio_d2_x_pins[] = { GPIOX_2 };
+static const unsigned int sdio_d3_x_pins[] = { GPIOX_3 };
+static const unsigned int sdio_clk_x_pins[] = { GPIOX_4 };
+static const unsigned int sdio_cmd_x_pins[] = { GPIOX_5 };
+static const unsigned int tdm_a_dout1_pins[] = { GPIOX_8 };
+static const unsigned int tdm_a_dout0_pins[] = { GPIOX_9 };
+static const unsigned int tdm_a_fs_pins[] = { GPIOX_10 };
+static const unsigned int tdm_a_sclk_pins[] = { GPIOX_11 };
+static const unsigned int uart_a_tx_x12_pins[] = { GPIOX_12 };
+static const unsigned int uart_a_rx_x13_pins[] = { GPIOX_13 };
+static const unsigned int uart_a_cts_pins[] = { GPIOX_14 };
+static const unsigned int uart_a_rts_pins[] = { GPIOX_15 };
+static const unsigned int pwm_e_pins[] = { GPIOX_16 };
+static const unsigned int pwm_f_x_pins[] = { GPIOX_17 };
+static const unsigned int pwm_j_x_pins[] = { GPIOX_18 };
+static const unsigned int i2c_c_sda_x_pins[] = { GPIOX_19 };
+static const unsigned int i2c_c_scl_x_pins[] = { GPIOX_20 };
+
+/*bank X func2*/
+static const unsigned int uart_e_tx_x_pins[] = { GPIOX_6 };
+static const unsigned int uart_e_rx_x_pins[] = { GPIOX_7 };
+static const unsigned int tdm_a_din1_pins[] = { GPIOX_8 };
+static const unsigned int tdm_a_din0_pins[] = { GPIOX_9 };
+static const unsigned int tdm_a_slv_fs_pins[] = { GPIOX_10 };
+static const unsigned int tdm_a_slv_sclk_pins[] = { GPIOX_11 };
+static const unsigned int i2c_d_sda_x_pins[] = { GPIOX_14 };
+static const unsigned int i2c_d_scl_x_pins[] = { GPIOX_15 };
+
+/*bank X func3*/
+static const unsigned int eth_mdio_pins[] = { GPIOX_0 };
+static const unsigned int eth_mdc_pins[] = { GPIOX_1 };
+static const unsigned int eth_rx_clk_pins[] = { GPIOX_2 };
+static const unsigned int eth_rx_dv_pins[] = { GPIOX_3 };
+static const unsigned int eth_rxd0_pins[] = { GPIOX_4 };
+static const unsigned int eth_rxd1_pins[] = { GPIOX_5 };
+static const unsigned int eth_rxd2_rgmii_pins[] = { GPIOX_6 };
+static const unsigned int eth_rxd3_rgmii_pins[] = { GPIOX_7 };
+static const unsigned int eth_tx_clk_pins[] = { GPIOX_8 };
+static const unsigned int eth_txen_pins[] = { GPIOX_9 };
+static const unsigned int eth_txd0_pins[] = { GPIOX_10 };
+static const unsigned int eth_txd1_pins[] = { GPIOX_11 };
+static const unsigned int eth_txd2_rgmii_pins[] = { GPIOX_12 };
+static const unsigned int eth_txd3_rgmii_pins[] = { GPIOX_13 };
+static const unsigned int uart_a_tx_x14_pins[] = { GPIOX_14 };
+static const unsigned int uart_a_rx_x15_pins[] = { GPIOX_15 };
+
+/*bank X func4*/
+static const unsigned int spi_b_mosi_x_pins[] = { GPIOX_8 };
+static const unsigned int spi_b_miso_x_pins[] = { GPIOX_9 };
+static const unsigned int spi_b_ss0_x_pins[] = { GPIOX_10 };
+static const unsigned int spi_b_sclk_x_pins[] = { GPIOX_11 };
+static const unsigned int pwm_h_x_pins[] = { GPIOX_14 };
+static const unsigned int pwm_g_x_pins[] = { GPIOX_15 };
+
+/*bank X func5 */
+static const unsigned int clk25_x_pins[] = { GPIOX_8 };
+
+/*bank M func1 */
+static const unsigned int sdio_d0_m_pins[] = { GPIOM_0 };
+static const unsigned int sdio_d1_m_pins[] = { GPIOM_1 };
+static const unsigned int sdio_d2_m_pins[] = { GPIOM_2 };
+static const unsigned int sdio_d3_m_pins[] = { GPIOM_3 };
+static const unsigned int sdio_clk_m_pins[] = { GPIOM_4 };
+static const unsigned int sdio_cmd_m_pins[] = { GPIOM_5 };
+static const unsigned int pwm_f_m_pins[] = { GPIOM_7 };
+static const unsigned int pwm_g_m_pins[] = { GPIOM_8 };
+static const unsigned int pwm_h_m_pins[] = { GPIOM_9 };
+static const unsigned int i2c_c_sda_m_pins[] = { GPIOM_12 };
+static const unsigned int i2c_c_scl_m_pins[] = { GPIOM_13 };
+
+/*bank M func2 */
+static const unsigned int pwm_i_m_pins[] = { GPIOM_0 };
+static const unsigned int pwm_j_m_pins[] = { GPIOM_1 };
+static const unsigned int pwm_g_hiz_pins[] = { GPIOM_8 };
+static const unsigned int pwm_h_hiz_pins[] = { GPIOM_9 };
+
+/*bank M func3 */
+static const unsigned int pdm_dclk_m_pins[] = { GPIOM_2 };
+static const unsigned int pdm_din0_m_pins[] = { GPIOM_3 };
+
+/*bank M func4 */
+static const unsigned int i2c_e_sda_m_pins[] = { GPIOM_0 };
+static const unsigned int i2c_e_scl_m_pins[] = { GPIOM_1 };
+static const unsigned int i2c_b_sda_m_pins[] = { GPIOM_4 };
+static const unsigned int i2c_b_scl_m_pins[] = { GPIOM_5 };
+static const unsigned int i2c_d_sda_m_pins[] = { GPIOM_8 };
+static const unsigned int i2c_d_scl_m_pins[] = { GPIOM_9 };
+
+/*bank M func5 */
+static const unsigned int uart_e_cts_pins[] = { GPIOM_2 };
+static const unsigned int uart_e_rts_pins[] = { GPIOM_3 };
+static const unsigned int uart_e_tx_m_pins[] = { GPIOM_4 };
+static const unsigned int uart_e_rx_m_pins[] = { GPIOM_5 };
+static const unsigned int mic_mute_key_pins[] = { GPIOM_6 };
+static const unsigned int mic_mute_led_pins[] = { GPIOM_7 };
+
+/*bank M func6 */
+static const unsigned int gen_clk_m9_pins[] = { GPIOM_9 };
+static const unsigned int gen_clk_m10_pins[] = { GPIOM_10 };
+
+/*bank A func1 */
+static const unsigned int mclk_0_pins[] = { GPIOA_0 };
+static const unsigned int tdm_b_sclk_pins[] = { GPIOA_1 };
+static const unsigned int tdm_b_fs_pins[] = { GPIOA_2 };
+static const unsigned int tdm_b_dout0_pins[] = { GPIOA_3 };
+static const unsigned int tdm_b_dout1_pins[] = { GPIOA_4 };
+static const unsigned int tdm_b_dout2_pins[] = { GPIOA_5 };
+static const unsigned int tdm_b_dout3_pins[] = { GPIOA_6 };
+static const unsigned int pwm_g_a7_pins[] = { GPIOA_7 };
+static const unsigned int pwm_h_a8_pins[] = { GPIOA_8 };
+static const unsigned int pwm_i_a9_pins[] = { GPIOA_9 };
+static const unsigned int pwm_j_a10_pins[] = { GPIOA_10 };
+static const unsigned int clk12_24_a_pins[] = { GPIOA_11 };
+static const unsigned int uart_c_tx_a12_pins[] = { GPIOA_12 };
+static const unsigned int uart_c_rx_a13_pins[] = { GPIOA_13 };
+static const unsigned int i2c_d_sda_a_pins[] = { GPIOA_14 };
+static const unsigned int i2c_d_scl_a_pins[] = { GPIOA_15 };
+
+/*bank A func2 */
+static const unsigned int tdm_b_slv_sclk_pins[] = { GPIOA_1 };
+static const unsigned int tdm_b_slv_fs_pins[] = { GPIOA_2 };
+static const unsigned int tdm_b_din0_pins[] = { GPIOA_3 };
+static const unsigned int tdm_b_din1_pins[] = { GPIOA_4 };
+static const unsigned int tdm_b_din2_pins[] = { GPIOA_5 };
+static const unsigned int tdm_b_din3_pins[] = { GPIOA_6 };
+static const unsigned int uart_e_tx_a_pins[] = { GPIOA_14 };
+static const unsigned int uart_e_rx_a_pins[] = { GPIOA_15 };
+
+/*bank A func3 */
+static const unsigned int pwm_g_a1_pins[] = { GPIOA_1 };
+static const unsigned int pwm_h_a2_pins[] = { GPIOA_2 };
+static const unsigned int pwm_i_a3_pins[] = { GPIOA_3 };
+static const unsigned int pwm_j_a4_pins[] = { GPIOA_4 };
+static const unsigned int spi_a_mosi_a_pins[] = { GPIOA_5 };
+static const unsigned int spi_a_miso_a_pins[] = { GPIOA_6 };
+static const unsigned int spi_a_sclk_a_pins[] = { GPIOA_7 };
+static const unsigned int spi_a_ss0_a_pins[] = { GPIOA_8 };
+static const unsigned int spi_a_ss1_pins[] = { GPIOA_9 };
+static const unsigned int spi_a_ss2_pins[] = { GPIOA_10 };
+static const unsigned int spi_b_mosi_a_pins[] = { GPIOA_11 };
+static const unsigned int spi_b_miso_a_pins[] = { GPIOA_12 };
+static const unsigned int spi_b_sclk_a_pins[] = { GPIOA_13 };
+static const unsigned int spi_b_ss0_a_pins[] = { GPIOA_14 };
+static const unsigned int spi_b_ss1_pins[] = { GPIOA_15 };
+
+/*bank A func4 */
+static const unsigned int uart_c_tx_a1_pins[] = { GPIOA_1 };
+static const unsigned int uart_c_rx_a2_pins[] = { GPIOA_2 };
+static const unsigned int uart_c_cts_pins[] = { GPIOA_3 };
+static const unsigned int uart_c_rts_pins[] = { GPIOA_4 };
+static const unsigned int uart_d_tx_a_pins[] = { GPIOA_5 };
+static const unsigned int uart_d_rx_a_pins[] = { GPIOA_6 };
+static const unsigned int uart_d_cts_a_pins[] = { GPIOA_7 };
+static const unsigned int uart_d_rts_a_pins[] = { GPIOA_8 };
+static const unsigned int i2c_e_sda_a_pins[] = { GPIOA_12 };
+static const unsigned int i2c_e_scl_a_pins[] = { GPIOA_13 };
+
+/*bank A func5 */
+static const unsigned int mclk_vad_pins[] = { GPIOA_0 };
+static const unsigned int tdm_vad_sclk_a1_pins[] = { GPIOA_1 };
+static const unsigned int tdm_vad_fs_a2_pins[] = { GPIOA_2 };
+static const unsigned int tdm_vad_sclk_a5_pins[] = { GPIOA_5 };
+static const unsigned int tdm_vad_fs_a6_pins[] = { GPIOA_6 };
+static const unsigned int i2c_b_sda_a_pins[] = { GPIOA_7 };
+static const unsigned int i2c_b_scl_a_pins[] = { GPIOA_8 };
+static const unsigned int i2c_c_sda_a_pins[] = { GPIOA_9 };
+static const unsigned int i2c_c_scl_a_pins[] = { GPIOA_10 };
+
+static struct meson_pmx_group meson_c2_periphs_groups[] = {
+ GPIO_GROUP(GPIOD_0),
+ GPIO_GROUP(GPIOD_1),
+ GPIO_GROUP(GPIOD_2),
+ GPIO_GROUP(GPIOD_3),
+ GPIO_GROUP(GPIOD_4),
+ GPIO_GROUP(GPIOD_5),
+ GPIO_GROUP(GPIOD_6),
+ GPIO_GROUP(GPIOD_7),
+ GPIO_GROUP(GPIOD_8),
+ GPIO_GROUP(GPIOD_9),
+ GPIO_GROUP(GPIOD_10),
+ GPIO_GROUP(GPIOD_11),
+ GPIO_GROUP(GPIOD_12),
+ GPIO_GROUP(GPIOD_13),
+ GPIO_GROUP(GPIOE_0),
+ GPIO_GROUP(GPIOE_1),
+ GPIO_GROUP(GPIOE_2),
+ GPIO_GROUP(GPIOB_0),
+ GPIO_GROUP(GPIOB_1),
+ GPIO_GROUP(GPIOB_2),
+ GPIO_GROUP(GPIOB_3),
+ GPIO_GROUP(GPIOB_4),
+ GPIO_GROUP(GPIOB_5),
+ GPIO_GROUP(GPIOB_6),
+ GPIO_GROUP(GPIOB_7),
+ GPIO_GROUP(GPIOB_8),
+ GPIO_GROUP(GPIOB_9),
+ GPIO_GROUP(GPIOB_10),
+ GPIO_GROUP(GPIOB_11),
+ GPIO_GROUP(GPIOB_12),
+ GPIO_GROUP(GPIOB_13),
+ GPIO_GROUP(GPIOC_0),
+ GPIO_GROUP(GPIOC_1),
+ GPIO_GROUP(GPIOC_2),
+ GPIO_GROUP(GPIOC_3),
+ GPIO_GROUP(GPIOC_4),
+ GPIO_GROUP(GPIOC_5),
+ GPIO_GROUP(GPIOC_6),
+ GPIO_GROUP(GPIOX_0),
+ GPIO_GROUP(GPIOX_1),
+ GPIO_GROUP(GPIOX_2),
+ GPIO_GROUP(GPIOX_3),
+ GPIO_GROUP(GPIOX_4),
+ GPIO_GROUP(GPIOX_5),
+ GPIO_GROUP(GPIOX_6),
+ GPIO_GROUP(GPIOX_7),
+ GPIO_GROUP(GPIOX_8),
+ GPIO_GROUP(GPIOX_9),
+ GPIO_GROUP(GPIOX_10),
+ GPIO_GROUP(GPIOX_11),
+ GPIO_GROUP(GPIOX_12),
+ GPIO_GROUP(GPIOX_13),
+ GPIO_GROUP(GPIOX_14),
+ GPIO_GROUP(GPIOX_15),
+ GPIO_GROUP(GPIOX_16),
+ GPIO_GROUP(GPIOX_17),
+ GPIO_GROUP(GPIOX_18),
+ GPIO_GROUP(GPIOX_19),
+ GPIO_GROUP(GPIOX_20),
+ GPIO_GROUP(GPIOM_0),
+ GPIO_GROUP(GPIOM_1),
+ GPIO_GROUP(GPIOM_2),
+ GPIO_GROUP(GPIOM_3),
+ GPIO_GROUP(GPIOM_4),
+ GPIO_GROUP(GPIOM_5),
+ GPIO_GROUP(GPIOM_6),
+ GPIO_GROUP(GPIOM_7),
+ GPIO_GROUP(GPIOM_8),
+ GPIO_GROUP(GPIOM_9),
+ GPIO_GROUP(GPIOM_10),
+ GPIO_GROUP(GPIOM_11),
+ GPIO_GROUP(GPIOM_12),
+ GPIO_GROUP(GPIOM_13),
+ GPIO_GROUP(GPIOA_0),
+ GPIO_GROUP(GPIOA_1),
+ GPIO_GROUP(GPIOA_2),
+ GPIO_GROUP(GPIOA_3),
+ GPIO_GROUP(GPIOA_4),
+ GPIO_GROUP(GPIOA_5),
+ GPIO_GROUP(GPIOA_6),
+ GPIO_GROUP(GPIOA_7),
+ GPIO_GROUP(GPIOA_8),
+ GPIO_GROUP(GPIOA_9),
+ GPIO_GROUP(GPIOA_10),
+ GPIO_GROUP(GPIOA_11),
+ GPIO_GROUP(GPIOA_12),
+ GPIO_GROUP(GPIOA_13),
+ GPIO_GROUP(GPIOA_14),
+ GPIO_GROUP(GPIOA_15),
+ GPIO_GROUP(GPIO_TEST_N),
+
+ /* bank D func1 */
+ GROUP(uart_b_tx_d, 1),
+ GROUP(uart_b_rx_d, 1),
+ GROUP(i2c_a_scl_d, 1),
+ GROUP(i2c_a_sda_d, 1),
+ GROUP(ir_out_d4, 1),
+ GROUP(ir_in_d5, 1),
+ GROUP(jtag_a_clk, 1),
+ GROUP(jtag_a_tms, 1),
+ GROUP(jtag_a_tdi, 1),
+ GROUP(jtag_a_tdo, 1),
+ GROUP(gen_clk_d, 1),
+ GROUP(clk12_24_d, 1),
+ GROUP(pwm_g_d13, 1),
+
+ /* bank D func2 */
+ GROUP(uart_d_tx_d2, 2),
+ GROUP(uart_d_rx_d3, 2),
+ GROUP(swclk, 2),
+ GROUP(swdio, 2),
+ GROUP(ir_in_d8, 2),
+ GROUP(ir_out_d9, 2),
+ GROUP(clk25_d, 2),
+
+ /* bank D func3 */
+ GROUP(i2c_slave_scl, 3),
+ GROUP(i2c_slave_sda, 3),
+ GROUP(pwm_d, 3),
+ GROUP(pwm_c, 3),
+ GROUP(pwm_f_d, 3),
+ GROUP(uart_d_tx_d8, 3),
+ GROUP(uart_d_rx_d9, 3),
+ GROUP(pwm_g_d10, 3),
+ GROUP(clk_32k_in, 3),
+
+ /* bank D func4 */
+ GROUP(pwm_d_hiz, 4),
+ GROUP(pwm_c_hiz, 4),
+ GROUP(pwm_f_hiz, 4),
+ GROUP(pwm_i_d, 4),
+ GROUP(pwm_g_d12, 4),
+
+ /* bank E func1 */
+ GROUP(uart_b_cts, 1),
+ GROUP(uart_b_rts, 1),
+ GROUP(pwm_h_d, 1),
+
+ /* bank E func2 */
+ GROUP(uart_d_cts_e, 2),
+ GROUP(uart_d_rts_e, 2),
+ GROUP(clk25_e, 2),
+
+ /* bank E func3 */
+ GROUP(pwm_a, 3),
+ GROUP(pwm_b, 3),
+
+ /* bank E func4 */
+ GROUP(i2c_a_scl_e, 4),
+ GROUP(i2c_a_sda_e, 4),
+
+ /* bank B func1 */
+ GROUP(emmc_nand_d0, 1),
+ GROUP(emmc_nand_d1, 1),
+ GROUP(emmc_nand_d2, 1),
+ GROUP(emmc_nand_d3, 1),
+ GROUP(emmc_nand_d4, 1),
+ GROUP(emmc_nand_d5, 1),
+ GROUP(emmc_nand_d6, 1),
+ GROUP(emmc_nand_d7, 1),
+ GROUP(emmc_clk, 1),
+ GROUP(emmc_cmd, 1),
+ GROUP(emmc_nand_ds, 1),
+
+ /* bank B func2 */
+ GROUP(nand_wen_clk, 2),
+ GROUP(nand_ale, 2),
+ GROUP(nand_ren_wr, 2),
+ GROUP(nand_cle, 2),
+ GROUP(nand_ce0, 2),
+
+ /* bank B func3 */
+ GROUP(spif_hold, 3),
+ GROUP(spif_mo, 3),
+ GROUP(spif_mi, 3),
+ GROUP(spif_clk, 3),
+ GROUP(spif_wp_n, 3),
+ GROUP(spif_cs, 3),
+
+ /* bank C func1 */
+ GROUP(sdcard_d0, 1),
+ GROUP(sdcard_d1, 1),
+ GROUP(sdcard_d2, 1),
+ GROUP(sdcard_d3, 1),
+ GROUP(sdcard_clk, 1),
+ GROUP(sdcard_cmd, 1),
+
+ /* bank C func2 */
+ GROUP(jtag_b_tdo, 2),
+ GROUP(jtag_b_tdi, 2),
+ GROUP(uart_b_rx_c, 2),
+ GROUP(uart_b_tx_c, 2),
+ GROUP(jtag_b_clk, 2),
+ GROUP(jtag_b_tms, 2),
+
+ /* bank C func3 */
+ GROUP(spi_a_mosi_c, 3),
+ GROUP(spi_a_miso_c, 3),
+ GROUP(spi_a_ss0_c, 3),
+ GROUP(spi_a_sclk_c, 3),
+ GROUP(i2c_e_sda_c, 3),
+ GROUP(i2c_e_scl_c, 3),
+
+ /* bank C func4 */
+ GROUP(pdm_din0_c, 4),
+ GROUP(pdm_dclk_c, 4),
+
+ /* bank X func1 */
+ GROUP(sdio_d0_x, 1),
+ GROUP(sdio_d1_x, 1),
+ GROUP(sdio_d2_x, 1),
+ GROUP(sdio_d3_x, 1),
+ GROUP(sdio_clk_x, 1),
+ GROUP(sdio_cmd_x, 1),
+ GROUP(tdm_a_dout1, 1),
+ GROUP(tdm_a_dout0, 1),
+ GROUP(tdm_a_fs, 1),
+ GROUP(tdm_a_sclk, 1),
+ GROUP(uart_a_tx_x12, 1),
+ GROUP(uart_a_rx_x13, 1),
+ GROUP(uart_a_cts, 1),
+ GROUP(uart_a_rts, 1),
+ GROUP(pwm_e, 1),
+ GROUP(pwm_f_x, 1),
+ GROUP(pwm_j_x, 1),
+ GROUP(i2c_c_sda_x, 1),
+ GROUP(i2c_c_scl_x, 1),
+
+ /* bank X func2 */
+ GROUP(uart_e_tx_x, 2),
+ GROUP(uart_e_rx_x, 2),
+ GROUP(tdm_a_din1, 2),
+ GROUP(tdm_a_din0, 2),
+ GROUP(tdm_a_slv_fs, 2),
+ GROUP(tdm_a_slv_sclk, 2),
+ GROUP(i2c_d_sda_x, 2),
+ GROUP(i2c_d_scl_x, 2),
+
+ /* bank X func3 */
+ GROUP(eth_mdio, 3),
+ GROUP(eth_mdc, 3),
+ GROUP(eth_rx_clk, 3),
+ GROUP(eth_rx_dv, 3),
+ GROUP(eth_rxd0, 3),
+ GROUP(eth_rxd1, 3),
+ GROUP(eth_rxd2_rgmii, 3),
+ GROUP(eth_rxd3_rgmii, 3),
+ GROUP(eth_tx_clk, 3),
+ GROUP(eth_txen, 3),
+ GROUP(eth_txd0, 3),
+ GROUP(eth_txd1, 3),
+ GROUP(eth_txd2_rgmii, 3),
+ GROUP(eth_txd3_rgmii, 3),
+ GROUP(uart_a_tx_x14, 3),
+ GROUP(uart_a_rx_x15, 3),
+
+ /* bank X func4 */
+ GROUP(spi_b_mosi_x, 4),
+ GROUP(spi_b_miso_x, 4),
+ GROUP(spi_b_ss0_x, 4),
+ GROUP(spi_b_sclk_x, 4),
+ GROUP(pwm_h_x, 4),
+ GROUP(pwm_g_x, 4),
+
+ /* bank X func5 */
+ GROUP(clk25_x, 5),
+
+ /* bank M func1 */
+ GROUP(sdio_d0_m, 1),
+ GROUP(sdio_d1_m, 1),
+ GROUP(sdio_d2_m, 1),
+ GROUP(sdio_d3_m, 1),
+ GROUP(sdio_clk_m, 1),
+ GROUP(sdio_cmd_m, 1),
+ GROUP(pwm_f_m, 1),
+ GROUP(pwm_g_m, 1),
+ GROUP(pwm_h_m, 1),
+ GROUP(i2c_c_sda_m, 1),
+ GROUP(i2c_c_scl_m, 1),
+
+ /* bank M func2 */
+ GROUP(pwm_i_m, 2),
+ GROUP(pwm_j_m, 2),
+ GROUP(pwm_g_hiz, 2),
+ GROUP(pwm_h_hiz, 2),
+
+ /* bank M func3 */
+ GROUP(pdm_dclk_m, 3),
+ GROUP(pdm_din0_m, 3),
+
+ /* bank M func4 */
+ GROUP(i2c_e_sda_m, 4),
+ GROUP(i2c_e_scl_m, 4),
+ GROUP(i2c_b_sda_m, 4),
+ GROUP(i2c_b_scl_m, 4),
+ GROUP(i2c_d_sda_m, 4),
+ GROUP(i2c_d_scl_m, 4),
+
+ /* bank M func5 */
+ GROUP(uart_e_cts, 5),
+ GROUP(uart_e_rts, 5),
+ GROUP(uart_e_tx_m, 5),
+ GROUP(uart_e_rx_m, 5),
+ GROUP(mic_mute_key, 5),
+ GROUP(mic_mute_led, 5),
+
+ /* bank M func6 */
+ GROUP(gen_clk_m9, 6),
+ GROUP(gen_clk_m10, 6),
+
+ /* bank A func1 */
+ GROUP(mclk_0, 1),
+ GROUP(tdm_b_sclk, 1),
+ GROUP(tdm_b_fs, 1),
+ GROUP(tdm_b_dout0, 1),
+ GROUP(tdm_b_dout1, 1),
+ GROUP(tdm_b_dout2, 1),
+ GROUP(tdm_b_dout3, 1),
+ GROUP(pwm_g_a7, 1),
+ GROUP(pwm_h_a8, 1),
+ GROUP(pwm_i_a9, 1),
+ GROUP(pwm_j_a10, 1),
+ GROUP(clk12_24_a, 1),
+ GROUP(uart_c_tx_a12, 1),
+ GROUP(uart_c_rx_a13, 1),
+ GROUP(i2c_d_sda_a, 1),
+ GROUP(i2c_d_scl_a, 1),
+
+ /* bank A func2 */
+ GROUP(tdm_b_slv_sclk, 2),
+ GROUP(tdm_b_slv_fs, 2),
+ GROUP(tdm_b_din0, 2),
+ GROUP(tdm_b_din1, 2),
+ GROUP(tdm_b_din2, 2),
+ GROUP(tdm_b_din3, 2),
+ GROUP(uart_e_tx_a, 2),
+ GROUP(uart_e_rx_a, 2),
+
+ /* bank A func3 */
+ GROUP(pwm_g_a1, 3),
+ GROUP(pwm_h_a2, 3),
+ GROUP(pwm_i_a3, 3),
+ GROUP(pwm_j_a4, 3),
+ GROUP(spi_a_mosi_a, 3),
+ GROUP(spi_a_miso_a, 3),
+ GROUP(spi_a_sclk_a, 3),
+ GROUP(spi_a_ss0_a, 3),
+ GROUP(spi_a_ss1, 3),
+ GROUP(spi_a_ss2, 3),
+ GROUP(spi_b_mosi_a, 3),
+ GROUP(spi_b_miso_a, 3),
+ GROUP(spi_b_sclk_a, 3),
+ GROUP(spi_b_ss0_a, 3),
+ GROUP(spi_b_ss1, 3),
+
+ /* bank A func4 */
+ GROUP(uart_c_tx_a1, 4),
+ GROUP(uart_c_rx_a2, 4),
+ GROUP(uart_c_cts, 4),
+ GROUP(uart_c_rts, 4),
+ GROUP(uart_d_tx_a, 4),
+ GROUP(uart_d_rx_a, 4),
+ GROUP(uart_d_cts_a, 4),
+ GROUP(uart_d_rts_a, 4),
+ GROUP(i2c_e_sda_a, 4),
+ GROUP(i2c_e_scl_a, 4),
+
+ /* bank A func5 */
+ GROUP(mclk_vad, 5),
+ GROUP(tdm_vad_sclk_a1, 5),
+ GROUP(tdm_vad_fs_a2, 5),
+ GROUP(tdm_vad_sclk_a5, 5),
+ GROUP(tdm_vad_fs_a6, 5),
+ GROUP(i2c_b_sda_a, 5),
+ GROUP(i2c_b_scl_a, 5),
+ GROUP(i2c_c_sda_a, 5),
+ GROUP(i2c_c_scl_a, 5),
+};
+
+static const char * const gpio_periphs_groups[] = {
+ "GPIO_TEST_N",
+
+ "GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4",
+ "GPIOD_5", "GPIOD_6", "GPIOD_7", "GPIOD_8", "GPIOD_9",
+ "GPIOD_10", "GPIOD_11", "GPIOD_12", "GPIOD_13,"
+
+ "GPIOE_0", "GPIOE_1", "GPIOE_2"
+
+ "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4",
+ "GPIOB_5", "GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9",
+ "GPIOB_10", "GPIOB_11", "GPIOB_12", "GPIOB_13",
+
+ "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4",
+ "GPIOC_5", "GPIOC_6",
+
+ "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
+ "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
+ "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
+ "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
+ "GPIOX_20",
+
+ "GPIOM_0", "GPIOM_1", "GPIOM_2", "GPIOM_3", "GPIOM_4",
+ "GPIOM_5", "GPIOM_6", "GPIOM_7", "GPIOM_8", "GPIOM_9",
+ "GPIOM_10", "GPIOM_11", "GPIOM_12", "GPIOM_13",
+
+ "GPIOA_0", "GPIOA_1", "GPIOA_2", "GPIOA_3", "GPIOA_4",
+ "GPIOA_5", "GPIOA_6", "GPIOA_7", "GPIOA_8", "GPIOA_9",
+ "GPIOA_10", "GPIOA_11", "GPIOA_12", "GPIOA_13", "GPIOA_14",
+ "GPIOA_15",
+};
+
+static const char * const uart_a_groups[] = {
+ "uart_a_tx_x12", "uart_a_rx_x13", "uart_a_cts", "uart_a_rts",
+ "uart_a_tx_x14", "uart_a_rx_x15",
+};
+
+static const char * const uart_b_groups[] = {
+ "uart_b_tx_d", "uart_b_rx_d", "uart_b_cts", "uart_b_rts",
+ "uart_b_rx_c", "uart_b_tx_c",
+};
+
+static const char * const uart_c_groups[] = {
+ "uart_c_tx_a12", "uart_c_rx_a13", "uart_c_tx_a1", "uart_c_rx_a2",
+ "uart_c_cts", "uart_c_rts",
+};
+
+static const char * const uart_d_groups[] = {
+ "uart_d_tx_d2", "uart_d_rx_d3", "uart_d_tx_d8", "uart_d_rx_d9",
+ "uart_d_cts_e", "uart_d_rts_e", "uart_d_tx_a", "uart_d_tx_a",
+ "uart_d_cts_a", "uart_d_rts_a",
+};
+
+static const char * const uart_e_groups[] = {
+ "uart_e_tx_x", "uart_e_rx_x", "uart_e_cts", "uart_e_rts", "uart_e_tx_m",
+ "uart_e_rx_m", "uart_e_rx_a", "uart_e_tx_a",
+};
+
+static const char * const i2c_a_groups[] = {
+ "i2c_a_scl_d", "i2c_a_sda_d", "i2c_a_scl_e", "i2c_a_sda_e",
+};
+
+static const char * const i2c_b_groups[] = {
+ "i2c_b_sda_a", "i2c_b_scl_a", "i2c_b_sda_m", "i2c_b_scl_m",
+};
+
+static const char * const i2c_c_groups[] = {
+ "i2c_c_sda_x", "i2c_c_scl_x", "i2c_c_sda_m", "i2c_c_scl_m",
+ "i2c_c_sda_a", "i2c_c_scl_a",
+};
+
+static const char * const i2c_d_groups[] = {
+ "i2c_d_sda_x", "i2c_d_scl_x", "i2c_d_sda_a", "i2c_d_scl_a",
+ "i2c_d_sda_m", "i2c_d_scl_m",
+};
+
+static const char * const i2c_e_groups[] = {
+ "i2c_e_sda_c", "i2c_e_scl_c", "i2c_e_sda_m", "i2c_e_scl_m",
+ "i2c_e_sda_a", "i2c_e_scl_a",
+};
+
+static const char * const i2c_slave_groups[] = {
+ "i2c_slave_scl", "i2c_slave_sda",
+};
+
+static const char * const pwm_a_groups[] = {
+ "pwm_a",
+};
+
+static const char * const pwm_b_groups[] = {
+ "pwm_b",
+};
+
+static const char * const pwm_c_groups[] = {
+ "pwm_c",
+};
+
+static const char * const pwm_d_groups[] = {
+ "pwm_d",
+};
+
+static const char * const pwm_e_groups[] = {
+ "pwm_e",
+};
+
+static const char * const pwm_f_groups[] = {
+ "pwm_f_d", "pwm_f_m", "pwm_f_x"
+};
+
+static const char * const pwm_g_groups[] = {
+ "pwm_g_d10", "pwm_g_x", "pwm_g_m", "pwm_g_a7",
+ "pwm_g_a1", "pwm_g_d12", "pwm_g_d13",
+};
+
+static const char * const pwm_h_groups[] = {
+ "pwm_h_x", "pwm_h_m", "pwm_h_a8", "pwm_h_a2",
+ "pwm_h_d",
+};
+
+static const char * const pwm_i_groups[] = {
+ "pwm_i_m", "pwm_i_a9", "pwm_i_a3", "pwm_i_d",
+};
+
+static const char * const pwm_j_groups[] = {
+ "pwm_j_x", "pwm_j_m", "pwm_j_a10", "pwm_j_a4",
+};
+
+static const char * const pwm_c_hiz_groups[] = {
+ "pwm_c_hiz",
+};
+
+static const char * const pwm_d_hiz_groups[] = {
+ "pwm_d_hiz",
+};
+
+static const char * const pwm_f_hiz_groups[] = {
+ "pwm_f_hiz",
+};
+
+static const char * const pwm_g_hiz_groups[] = {
+ "pwm_g_hiz",
+};
+
+static const char * const pwm_h_hiz_groups[] = {
+ "pwm_h_hiz",
+};
+
+static const char * const ir_out_groups[] = {
+ "ir_out_d4", "ir_out_d9",
+};
+
+static const char * const ir_in_groups[] = {
+ "ir_in_d5", "ir_in_d8",
+};
+
+static const char * const jtag_a_groups[] = {
+ "jtag_a_clk", "jtag_a_tms", "jtag_a_tdi", "jtag_a_tdo",
+};
+
+static const char * const jtag_b_groups[] = {
+ "jtag_b_tdo", "jtag_b_tdi", "jtag_b_clk", "jtag_b_tms",
+};
+
+static const char * const gen_clk_groups[] = {
+ "gen_clk_d", "gen_clk_m10", "gen_clk_m9",
+};
+
+static const char * const clk12_24_groups[] = {
+ "clk12_24_d", "clk12_24_a",
+};
+
+static const char * const sw_groups[] = {
+ "swclk", "swdio",
+};
+
+static const char * const clk25_groups[] = {
+ "clk25_e", "clk25_x", "clk_25_d",
+};
+
+static const char * const clk_32k_in_groups[] = {
+ "clk_32k_in",
+};
+
+static const char * const emmc_groups[] = {
+ "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3",
+ "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7",
+ "emmc_clk", "emmc_cmd", "emmc_nand_ds",
+};
+
+static const char * const nand_groups[] = {
+ "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3",
+ "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7",
+ "emmc_nand_ds", "nand_wen_clk", "nand_ale", "nand_ren_wr",
+ "nand_cle", "nand_ce0",
+};
+
+static const char * const spif_groups[] = {
+ "spif_hold", "spif_mo", "spif_mi", "spif_clk",
+ "spif_wp_n", "spif_cs",
+};
+
+static const char * const sdcard_groups[] = {
+ "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3",
+ "sdcard_clk", "sdcard_cmd",
+};
+
+static const char * const spi_a_groups[] = {
+ "spi_a_mosi_c", "spi_a_miso_c", "spi_a_ss0_c", "spi_a_sclk_c",
+ "spi_a_mosi_a", "spi_a_miso_a", "spi_a_sclk_a", "spi_a_ss0_a",
+ "spi_a_ss1", "spi_a_ss2",
+};
+
+static const char * const pdm_groups[] = {
+ "pdm_din0_c", "pdm_dclk_c", "pdm_dclk_m", "pdm_din0_m",
+};
+
+static const char * const sdio_groups[] = {
+ "sdio_d0_x", "sdio_d1_x", "sdio_d2_x", "sdio_d3_x",
+ "sdio_clk_x", "sdio_cmd_x",
+
+ "sdio_d0_m", "sdio_d1_m", "sdio_d2_m", "sdio_d3_m",
+ "sdio_clk_m", "sdio_cmd_m",
+};
+
+static const char * const eth_groups[] = {
+ "eth_mdio", "eth_mdc", "eth_rx_clk", "eth_rx_dv",
+ "eth_rxd0", "eth_rxd1", "eth_rxd2_rgmii", "eth_rxd3_rgmii",
+ "eth_tx_clk", "eth_txen", "eth_txd0", "eth_txd1",
+ "eth_txd2_rgmii", "eth_txd3_rgmii",
+};
+
+static const char * const spi_b_groups[] = {
+ "spi_b_mosi_x", "spi_b_miso_x", "spi_b_ss0_x", "spi_b_sclk_x",
+ "spi_b_mosi_a", "spi_b_miso_a", "spi_b_ss0_a", "spi_b_sclk_a",
+ "spi_b_ss1",
+};
+
+static const char * const mic_mute_groups[] = {
+ "mic_mute_key", "mic_mute_led",
+};
+
+static const char * const mclk_0_groups[] = {
+ "mclk_0",
+};
+
+static const char * const tdm_a_groups[] = {
+ "tdm_a_dout1", "tdm_a_dout0", "tdm_a_fs", "tdm_a_sclk",
+ "tdm_a_din1", "tdm_a_din0", "tdm_a_slv_fs", "tdm_a_slv_sclk",
+};
+
+static const char * const tdm_b_groups[] = {
+ "tdm_b_sclk", "tdm_b_fs", "tdm_b_dout0", "tdm_b_dout1",
+ "tdm_b_dout2", "tdm_b_dout3",
+
+ "tdm_b_slv_sclk", "tdm_b_slv_fs", "tdm_b_din0", "tdm_b_din1",
+ "tdm_b_din2", "tdm_b_din3",
+};
+
+static const char * const tdm_vad_groups[] = {
+ "tdm_vad_sclk_a1", "tdm_vad_fs_a2", "tdm_vad_sclk_a5", "tdm_vad_fs_a6",
+};
+
+static const char * const mclk_vad_groups[] = {
+ "mclk_vad",
+};
+
+static struct meson_pmx_func meson_c2_periphs_functions[] = {
+ FUNCTION(gpio_periphs),
+ FUNCTION(uart_a),
+ FUNCTION(uart_b),
+ FUNCTION(uart_c),
+ FUNCTION(uart_d),
+ FUNCTION(uart_e),
+ FUNCTION(i2c_a),
+ FUNCTION(i2c_b),
+ FUNCTION(i2c_c),
+ FUNCTION(i2c_d),
+ FUNCTION(i2c_e),
+ FUNCTION(i2c_slave),
+ FUNCTION(pwm_a),
+ FUNCTION(pwm_b),
+ FUNCTION(pwm_c),
+ FUNCTION(pwm_d),
+ FUNCTION(pwm_e),
+ FUNCTION(pwm_f),
+ FUNCTION(pwm_g),
+ FUNCTION(pwm_h),
+ FUNCTION(pwm_i),
+ FUNCTION(pwm_j),
+ FUNCTION(pwm_c_hiz),
+ FUNCTION(pwm_d_hiz),
+ FUNCTION(pwm_f_hiz),
+ FUNCTION(pwm_g_hiz),
+ FUNCTION(pwm_h_hiz),
+ FUNCTION(ir_out),
+ FUNCTION(ir_in),
+ FUNCTION(jtag_a),
+ FUNCTION(jtag_b),
+ FUNCTION(gen_clk),
+ FUNCTION(clk12_24),
+ FUNCTION(sw),
+ FUNCTION(clk25),
+ FUNCTION(clk_32k_in),
+ FUNCTION(emmc),
+ FUNCTION(nand),
+ FUNCTION(spif),
+ FUNCTION(sdcard),
+ FUNCTION(spi_a),
+ FUNCTION(pdm),
+ FUNCTION(sdio),
+ FUNCTION(eth),
+ FUNCTION(spi_b),
+ FUNCTION(mic_mute),
+ FUNCTION(mclk_0),
+ FUNCTION(tdm_a),
+ FUNCTION(tdm_b),
+ FUNCTION(tdm_vad),
+ FUNCTION(mclk_vad),
+};
+
+static struct meson_bank meson_c2_periphs_banks[] = {
+ /* name first last irq pullen pull dir out in */
+ BANK("GPIOD_", GPIOD_0, GPIOD_13,
+ 0x3, 0, 0x4, 0, 0x2, 0, 0x1, 0, 0x0, 0),
+ BANK("GPIOE_", GPIOE_0, GPIOE_2,
+ 0x13, 0, 0x14, 0, 0x12, 0, 0x11, 0, 0x10, 0),
+ BANK("GPIOB_", GPIOB_0, GPIOB_13,
+ 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0),
+ BANK("GPIOC_", GPIOC_0, GPIOC_6,
+ 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0),
+ BANK("GPIOX_", GPIOX_0, GPIOX_20,
+ 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0),
+ BANK("GPIOM_", GPIOM_0, GPIOM_13,
+ 0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0),
+ BANK("GPIOA_", GPIOA_0, GPIOA_15,
+ 0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0),
+ BANK("GPIO_TEST_N", GPIO_TEST_N, GPIO_TEST_N,
+ 0x73, 0, 0x74, 0, 0x72, 0, 0x71, 0, 0x70, 0),
+};
+
+static struct meson_pmx_bank meson_c2_periphs_pmx_banks[] = {
+ /*name first lask reg offset*/
+ BANK_PMX("D", GPIOD_0, GPIOD_13, 0x0, 0),
+ BANK_PMX("E", GPIOE_0, GPIOE_2, 0x2, 0),
+ BANK_PMX("B", GPIOB_0, GPIOB_13, 0x3, 0),
+ BANK_PMX("C", GPIOC_0, GPIOC_6, 0x5, 0),
+ BANK_PMX("X", GPIOX_0, GPIOX_20, 0x6, 0),
+ BANK_PMX("M", GPIOM_0, GPIOM_13, 0x9, 0),
+ BANK_PMX("A", GPIOA_0, GPIOA_15, 0xb, 0),
+ BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0xf, 0),
+};
+
+static struct meson_drive_bank meson_c2_periphs_drive_banks[] = {
+ /* name first lask reg offset*/
+ BANK_DRIVE("D", GPIOD_0, GPIOD_13, 0x5, 0),
+ BANK_DRIVE("E", GPIOE_0, GPIOE_2, 0x15, 0),
+ BANK_DRIVE("B", GPIOB_0, GPIOB_13, 0x25, 0),
+ BANK_DRIVE("C", GPIOC_0, GPIOC_6, 0x35, 0),
+ BANK_DRIVE("X", GPIOX_0, GPIOX_20, 0x45, 0),
+ BANK_DRIVE("M", GPIOM_0, GPIOM_13, 0x55, 0),
+ BANK_DRIVE("A", GPIOA_0, GPIOA_15, 0x65, 0),
+ BANK_DRIVE("TESTN", GPIO_TEST_N, GPIO_TEST_N, 0x75, 0),
+};
+
+static struct meson_axg_pmx_data meson_c2_periphs_pmx_banks_data = {
+ .pmx_banks = meson_c2_periphs_pmx_banks,
+ .num_pmx_banks = ARRAY_SIZE(meson_c2_periphs_pmx_banks),
+};
+
+static struct meson_drive_data meson_c2_periphs_drive_data = {
+ .drive_banks = meson_c2_periphs_drive_banks,
+ .num_drive_banks = ARRAY_SIZE(meson_c2_periphs_drive_banks),
+};
+
+static struct meson_pinctrl_data meson_c2_periphs_pinctrl_data = {
+ .name = "periphs-banks",
+ .groups = meson_c2_periphs_groups,
+ .funcs = meson_c2_periphs_functions,
+ .banks = meson_c2_periphs_banks,
+ .num_pins = 90,
+ .num_groups = ARRAY_SIZE(meson_c2_periphs_groups),
+ .num_funcs = ARRAY_SIZE(meson_c2_periphs_functions),
+ .num_banks = ARRAY_SIZE(meson_c2_periphs_banks),
+ .pmx_data = &meson_c2_periphs_pmx_banks_data,
+ .drv_data = &meson_c2_periphs_drive_data,
+};
+
+static const struct udevice_id meson_c2_pinctrl_match[] = {
+ {
+ .compatible = "amlogic,meson-c2-periphs-pinctrl",
+ .data = (ulong)&meson_c2_periphs_pinctrl_data,
+ },
+ { },
+};
+
+U_BOOT_DRIVER(meson_c2_pinctrl) = {
+ .name = "meson-c2-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(meson_c2_pinctrl_match),
+ .probe = meson_pinctrl_probe,
+ .priv_auto_alloc_size = sizeof(struct meson_pinctrl),
+ .ops = &meson_axg_pinctrl_ops,
+};
diff --git a/drivers/pinctrl/meson/pinctrl-meson-g12a.c b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
index 8674a6c..77ee8b7 100644
--- a/drivers/pinctrl/meson/pinctrl-meson-g12a.c
+++ b/drivers/pinctrl/meson/pinctrl-meson-g12a.c
@@ -1,10 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Pin controller and GPIO driver for Amlogic Meson G12A SoC.
- *
- * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
- * Author: Xingyu Chen <xingyu.chen@amlogic.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ or MIT)
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
diff --git a/drivers/pinctrl/meson/pinctrl-meson-s4.c b/drivers/pinctrl/meson/pinctrl-meson-s4.c
new file mode 100644
index 0000000..72559d5
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-s4.c
@@ -0,0 +1,1108 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <dt-bindings/gpio/meson-s4-gpio.h>
+
+#include "pinctrl-meson.h"
+#include "pinctrl-meson-axg-pmx.h"
+
+/* BANK E func1 */
+static const unsigned int i2c0_sda_pins[] = { GPIOE_0 };
+static const unsigned int i2c0_scl_pins[] = { GPIOE_1 };
+
+/* BANK E func2 */
+static const unsigned int uart_b_tx_e_pins[] = { GPIOE_0 };
+static const unsigned int uart_b_rx_e_pins[] = { GPIOE_1 };
+
+/* BANK E func3 */
+static const unsigned int pwm_h_pins[] = { GPIOE_0 };
+static const unsigned int pwm_j_pins[] = { GPIOE_1 };
+
+/* BANK B func1 */
+static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 };
+static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 };
+static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 };
+static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 };
+static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 };
+static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 };
+static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 };
+static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 };
+static const unsigned int emmc_clk_pins[] = { GPIOB_8 };
+static const unsigned int emmc_rst_pins[] = { GPIOB_9 };
+static const unsigned int emmc_cmd_pins[] = { GPIOB_10 };
+static const unsigned int emmc_nand_ds_pins[] = { GPIOB_11 };
+
+/* Bank B func2 */
+static const unsigned int nand_wen_clk_pins[] = { GPIOB_8 };
+static const unsigned int nand_ale_pins[] = { GPIOB_9 };
+static const unsigned int nand_ren_wr_pins[] = { GPIOB_10 };
+static const unsigned int nand_cle_pins[] = { GPIOB_11 };
+static const unsigned int nand_ce0_pins[] = { GPIOB_12 };
+
+/* Bank B func3 */
+static const unsigned int spif_hold_pins[] = { GPIOB_3 };
+static const unsigned int spif_mo_pins[] = { GPIOB_4 };
+static const unsigned int spif_mi_pins[] = { GPIOB_5 };
+static const unsigned int spif_clk_pins[] = { GPIOB_6 };
+static const unsigned int spif_wp_pins[] = { GPIOB_7 };
+static const unsigned int spif_cs_pins[] = { GPIOB_13 };
+
+/* Bank C func1 */
+static const unsigned int sdcard_d0_c_pins[] = { GPIOC_0 };
+static const unsigned int sdcard_d1_c_pins[] = { GPIOC_1 };
+static const unsigned int sdcard_d2_c_pins[] = { GPIOC_2 };
+static const unsigned int sdcard_d3_c_pins[] = { GPIOC_3 };
+static const unsigned int sdcard_clk_c_pins[] = { GPIOC_4 };
+static const unsigned int sdcard_cmd_c_pins[] = { GPIOC_5 };
+static const unsigned int sdcard_cd_pins[] = { GPIOC_6 };
+
+/* Bank C func2 */
+static const unsigned int jtag_2_tdo_pins[] = { GPIOC_0 };
+static const unsigned int jtag_2_tdi_pins[] = { GPIOC_1 };
+static const unsigned int uart_b_rx_c_pins[] = { GPIOC_2 };
+static const unsigned int uart_b_tx_c_pins[] = { GPIOC_3 };
+static const unsigned int jtag_2_clk_pins[] = { GPIOC_4 };
+static const unsigned int jtag_2_tms_pins[] = { GPIOC_5 };
+static const unsigned int i2c1_sda_c_pins[] = { GPIOC_6 };
+static const unsigned int i2c1_scl_c_pins[] = { GPIOC_7 };
+
+/* Bank C func3 */
+static const unsigned int pdm_din1_c_pins[] = { GPIOC_0 };
+static const unsigned int pdm_din0_c_pins[] = { GPIOC_1 };
+static const unsigned int i2c4_sda_c_pins[] = { GPIOC_2 };
+static const unsigned int i2c4_scl_c_pins[] = { GPIOC_3 };
+static const unsigned int pdm_dclk_c_pins[] = { GPIOC_4 };
+static const unsigned int iso7816_clk_c_pins[] = { GPIOC_5 };
+static const unsigned int iso7816_data_c_pins[] = { GPIOC_6 };
+
+/* Bank C func4 */
+static const unsigned int tdm_d2_c_pins[] = { GPIOC_0 };
+static const unsigned int tdm_d3_c_pins[] = { GPIOC_1 };
+static const unsigned int tdm_fs1_c_pins[] = { GPIOC_2 };
+
+static const unsigned int mclk_1_c_pins[] = { GPIOC_4 };
+static const unsigned int tdm_d4_c_pins[] = { GPIOC_5 };
+static const unsigned int tdm_d5_c_pins[] = { GPIOC_6 };
+
+/* Bank D func1 */
+static const unsigned int uart_b_tx_d_pins[] = { GPIOD_0 };
+static const unsigned int uart_b_rx_d_pins[] = { GPIOD_1 };
+static const unsigned int uart_b_cts_d_pins[] = { GPIOD_2 };
+static const unsigned int uart_b_rts_d_pins[] = { GPIOD_3 };
+static const unsigned int remote_out_pins[] = { GPIOD_4 };
+static const unsigned int remote_in_pins[] = { GPIOD_5 };
+static const unsigned int jtag_1_clk_pins[] = { GPIOD_6 };
+static const unsigned int jtag_1_tms_pins[] = { GPIOD_7 };
+static const unsigned int jtag_1_tdi_pins[] = { GPIOD_8 };
+static const unsigned int jtag_1_tdo_pins[] = { GPIOD_9 };
+static const unsigned int clk12_24_pins[] = { GPIOD_10 };
+static const unsigned int pwm_g_hiz_pins[] = { GPIOD_11 };
+
+/* Bank D func2 */
+static const unsigned int i2c4_sda_d_pins[] = { GPIOD_2 };
+static const unsigned int i2c4_scl_d_pins[] = { GPIOD_3 };
+static const unsigned int mclk_1_d_pins[] = { GPIOD_4 };
+static const unsigned int tdm_sclk1_d_pins[] = { GPIOD_6 };
+static const unsigned int tdm_fs1_d_pins[] = { GPIOD_7 };
+static const unsigned int tdm_d4_d_pins[] = { GPIOD_8 };
+static const unsigned int tdm_d3_d_pins[] = { GPIOD_9 };
+static const unsigned int tdm_d2_d_pins[] = { GPIOD_10 };
+static const unsigned int pwm_g_d_pins[] = { GPIOD_11 };
+
+/* Bank D func3 */
+static const unsigned int uart_c_tx_pins[] = { GPIOD_2 };
+static const unsigned int uart_c_rx_pins[] = { GPIOD_3 };
+static const unsigned int pwm_b_d_pins[] = { GPIOD_4 };
+static const unsigned int pwm_a_d_pins[] = { GPIOD_6 };
+static const unsigned int pwm_c_d_pins[] = { GPIOD_7 };
+static const unsigned int pwm_d_d_pins[] = { GPIOD_8 };
+static const unsigned int pwm_i_d_pins[] = { GPIOD_9 };
+
+/* Bank D func4 */
+static const unsigned int clk_32k_in_pins[] = { GPIOD_2 };
+static const unsigned int pwm_b_hiz_pins[] = { GPIOD_4 };
+static const unsigned int pwm_a_hiz_pins[] = { GPIOD_6 };
+static const unsigned int pwm_c_hiz_pins[] = { GPIOD_7 };
+static const unsigned int pdm_dclk_d_pins[] = { GPIOD_8 };
+static const unsigned int pdm_din0_d_pins[] = { GPIOD_9 };
+static const unsigned int pdm_din1_d_pins[] = { GPIOD_10 };
+
+/* Bank D func5 */
+static const unsigned int mic_mute_en_pins[] = { GPIOD_2 };
+static const unsigned int mic_mute_key_pins[] = { GPIOD_3 };
+static const unsigned int i2c1_sda_d_pins[] = { GPIOD_6 };
+static const unsigned int i2c1_scl_d_pins[] = { GPIOD_7 };
+static const unsigned int i2c2_sda_d_pins[] = { GPIOD_10 };
+static const unsigned int i2c2_scl_d_pins[] = { GPIOD_11 };
+
+/* Bank D func6 */
+static const unsigned int gen_clk_d_pins[] = { GPIOD_10 };
+
+/* Bank H func1 */
+static const unsigned int hdmitx_sda_pins[] = { GPIOH_0 };
+static const unsigned int hdmitx_sck_pins[] = { GPIOH_1 };
+static const unsigned int hdmitx_hpd_in_pins[] = { GPIOH_2 };
+static const unsigned int ao_cec_a_pins[] = { GPIOH_3 };
+static const unsigned int spdif_out_h_pins[] = { GPIOH_4 };
+static const unsigned int spdif_in_pins[] = { GPIOH_5 };
+static const unsigned int i2c1_sda_h_pins[] = { GPIOH_6 };
+static const unsigned int i2c1_scl_h_pins[] = { GPIOH_7 };
+static const unsigned int i2c2_sda_h8_pins[] = { GPIOH_8 };
+static const unsigned int i2c2_scl_h9_pins[] = { GPIOH_9 };
+static const unsigned int eth_link_led_pins[] = { GPIOH_10 };
+static const unsigned int eth_act_led_pins[] = { GPIOH_11 };
+
+/* Bank H func2 */
+static const unsigned int i2c2_sda_h0_pins[] = { GPIOH_0 };
+static const unsigned int i2c2_scl_h1_pins[] = { GPIOH_1 };
+static const unsigned int ao_cec_b_pins[] = { GPIOH_3 };
+static const unsigned int uart_d_tx_h_pins[] = { GPIOH_4 };
+static const unsigned int uart_d_rx_h_pins[] = { GPIOH_5 };
+static const unsigned int uart_d_cts_h_pins[] = { GPIOH_6 };
+static const unsigned int uart_d_rts_h_pins[] = { GPIOH_7 };
+static const unsigned int iso7816_clk_h_pins[] = { GPIOH_8 };
+static const unsigned int iso7816_data_h_pins[] = { GPIOH_9 };
+static const unsigned int uart_e_tx_h_pins[] = { GPIOH_10 };
+static const unsigned int uart_e_rx_h_pins[] = { GPIOH_11 };
+
+/* Bank H func3 */
+static const unsigned int pwm_d_h_pins[] = { GPIOH_6 };
+static const unsigned int pwm_i_h_pins[] = { GPIOH_7 };
+static const unsigned int pdm_dclk_h_pins[] = { GPIOH_8 };
+static const unsigned int pdm_din0_h_pins[] = { GPIOH_9 };
+static const unsigned int pdm_din1_h_pins[] = { GPIOH_10 };
+
+/* Bank H func4 */
+static const unsigned int mclk_1_h_pins[] = { GPIOH_4 };
+static const unsigned int tdm_sclk1_h_pins[] = { GPIOH_5 };
+static const unsigned int tdm_fs1_h_pins[] = { GPIOH_6 };
+static const unsigned int tdm_d2_h_pins[] = { GPIOH_7 };
+static const unsigned int tdm_d3_h_pins[] = { GPIOH_8 };
+static const unsigned int tdm_d4_h_pins[] = { GPIOH_9 };
+
+/* Bank H func5 */
+static const unsigned int spi_a_miso_h_pins[] = { GPIOH_4 };
+static const unsigned int spi_a_mosi_h_pins[] = { GPIOH_5 };
+static const unsigned int spi_a_clk_h_pins[] = { GPIOH_6 };
+static const unsigned int spi_a_ss0_h_pins[] = { GPIOH_7 };
+
+/* Bank H func6 */
+static const unsigned int gen_clk_h_pins[] = { GPIOH_11 };
+
+/* Bank X func1 */
+static const unsigned int sdio_d0_pins[] = { GPIOX_0 };
+static const unsigned int sdio_d1_pins[] = { GPIOX_1 };
+static const unsigned int sdio_d2_pins[] = { GPIOX_2 };
+static const unsigned int sdio_d3_pins[] = { GPIOX_3 };
+static const unsigned int sdio_clk_pins[] = { GPIOX_4 };
+static const unsigned int sdio_cmd_pins[] = { GPIOX_5 };
+static const unsigned int pwm_a_x_pins[] = { GPIOX_6 };
+static const unsigned int pwm_f_x_pins[] = { GPIOX_7 };
+static const unsigned int tdm_d1_pins[] = { GPIOX_8 };
+static const unsigned int tdm_d0_pins[] = { GPIOX_9 };
+static const unsigned int tdm_fs0_pins[] = { GPIOX_10 };
+static const unsigned int tdm_sclk0_pins[] = { GPIOX_11 };
+static const unsigned int uart_a_tx_pins[] = { GPIOX_12 };
+static const unsigned int uart_a_rx_pins[] = { GPIOX_13 };
+static const unsigned int uart_a_cts_pins[] = { GPIOX_14 };
+static const unsigned int uart_a_rts_pins[] = { GPIOX_15 };
+static const unsigned int pwm_e_x_pins[] = { GPIOX_16 };
+static const unsigned int i2c1_sda_x_pins[] = { GPIOX_17 };
+static const unsigned int i2c1_scl_x_pins[] = { GPIOX_18 };
+static const unsigned int pwm_b_x_pins[] = { GPIOX_19 };
+
+/* Bank X func2 */
+static const unsigned int pdm_din0_x_pins[] = { GPIOX_8 };
+static const unsigned int pdm_din1_x_pins[] = { GPIOX_9 };
+static const unsigned int pdm_dclk_x_pins[] = { GPIOX_11 };
+
+/* Bank X func3 */
+static const unsigned int spi_a_mosi_x_pins[] = { GPIOX_8 };
+static const unsigned int spi_a_miso_x_pins[] = { GPIOX_9 };
+static const unsigned int spi_a_ss0_x_pins[] = { GPIOX_10 };
+static const unsigned int spi_a_clk_x_pins[] = { GPIOX_11 };
+
+/* Bank X func4 */
+static const unsigned int pwm_c_x_pins[] = { GPIOX_8 };
+static const unsigned int i2c_slave_scl_pins[] = { GPIOX_10 };
+static const unsigned int i2c_slave_sda_pins[] = { GPIOX_11 };
+
+/* Bank X func5 */
+static const unsigned int i2c3_sda_x_pins[] = { GPIOX_10 };
+static const unsigned int i2c3_scl_x_pins[] = { GPIOX_11 };
+
+/* Bank Z func1 */
+static const unsigned int tdm_fs2_pins[] = { GPIOZ_0 };
+static const unsigned int tdm_sclk2_pins[] = { GPIOZ_1 };
+static const unsigned int tdm_d4_z_pins[] = { GPIOZ_2 };
+static const unsigned int tdm_d5_z_pins[] = { GPIOZ_3 };
+static const unsigned int tdm_d6_pins[] = { GPIOZ_4 };
+static const unsigned int tdm_d7_pins[] = { GPIOZ_5 };
+static const unsigned int mclk_2_pins[] = { GPIOZ_6 };
+static const unsigned int spdif_out_z_pins[] = { GPIOZ_9 };
+static const unsigned int dtv_a_if_agc_z10_pins[] = { GPIOZ_10 };
+static const unsigned int uart_e_tx_z11_pins[] = { GPIOZ_11 };
+static const unsigned int uart_e_rx_z12_pins[] = { GPIOZ_12 };
+
+/* Bank Z func2 */
+static const unsigned int tsin_a_clk_pins[] = { GPIOZ_0 };
+static const unsigned int tsin_a_sop_pins[] = { GPIOZ_1 };
+static const unsigned int tsin_a_valid_pins[] = { GPIOZ_2 };
+static const unsigned int tsin_a_din0_pins[] = { GPIOZ_3 };
+static const unsigned int dtv_a_if_agc_z6_pins[] = { GPIOZ_6 };
+static const unsigned int dtv_b_if_agc_pins[] = { GPIOZ_7 };
+static const unsigned int i2c3_sda_z_pins[] = { GPIOZ_8 };
+static const unsigned int i2c3_scl_z_pins[] = { GPIOZ_9 };
+static const unsigned int dtv_a_rf_agc_pins[] = { GPIOZ_10 };
+static const unsigned int dtv_b_rf_agc_pins[] = { GPIOZ_11 };
+
+/* Bank Z func3 */
+static const unsigned int sdcard_d0_z_pins[] = { GPIOZ_0 };
+static const unsigned int sdcard_d1_z_pins[] = { GPIOZ_1 };
+static const unsigned int sdcard_d2_z_pins[] = { GPIOZ_2 };
+static const unsigned int sdcard_d3_z_pins[] = { GPIOZ_3 };
+static const unsigned int sdcard_clk_z_pins[] = { GPIOZ_4 };
+static const unsigned int sdcard_cmd_z_pins[] = { GPIOZ_5 };
+static const unsigned int uart_e_tx_z8_pins[] = { GPIOZ_8 };
+static const unsigned int uart_e_rx_z9_pins[] = { GPIOZ_9 };
+static const unsigned int pdm_din1_z_pins[] = { GPIOZ_10 };
+static const unsigned int pdm_din0_z_pins[] = { GPIOZ_11 };
+static const unsigned int pdm_dclk_z_pins[] = { GPIOZ_12 };
+
+/* Bank Z func4 */
+static const unsigned int spi_a_miso_z_pins[] = { GPIOZ_0 };
+static const unsigned int spi_a_mosi_z_pins[] = { GPIOZ_1 };
+static const unsigned int spi_a_clk_z_pins[] = { GPIOZ_2 };
+static const unsigned int spi_a_ss0_z_pins[] = { GPIOZ_3 };
+static const unsigned int spi_a_ss1_z_pins[] = { GPIOZ_4 };
+static const unsigned int spi_a_ss2_z_pins[] = { GPIOZ_5 };
+static const unsigned int i2c4_scl_z_pins[] = { GPIOZ_11 };
+static const unsigned int i2c4_sda_z_pins[] = { GPIOZ_12 };
+
+/* Bank Z func5 */
+static const unsigned int uart_d_tx_z_pins[] = { GPIOZ_0 };
+static const unsigned int uart_d_rx_z_pins[] = { GPIOZ_1 };
+static const unsigned int uart_d_cts_z_pins[] = { GPIOZ_2 };
+static const unsigned int uart_d_rts_z_pins[] = { GPIOZ_3 };
+static const unsigned int pwm_g_z_pins[] = { GPIOZ_4 };
+static const unsigned int pwm_f_z_pins[] = { GPIOZ_5 };
+static const unsigned int pwm_e_z_pins[] = { GPIOZ_6 };
+
+/* Bank Z func6 */
+static const unsigned int s2_demod_gpio7_pins[] = { GPIOZ_0 };
+static const unsigned int s2_demod_gpio6_pins[] = { GPIOZ_1 };
+static const unsigned int s2_demod_gpio5_pins[] = { GPIOZ_2 };
+static const unsigned int s2_demod_gpio4_pins[] = { GPIOZ_3 };
+static const unsigned int s2_demod_gpio3_pins[] = { GPIOZ_4 };
+static const unsigned int s2_demod_gpio2_pins[] = { GPIOZ_5 };
+static const unsigned int diseqc_out_pins[] = { GPIOZ_7 };
+static const unsigned int s2_demod_gpio1_pins[] = { GPIOZ_8 };
+static const unsigned int s2_demod_gpio0_pins[] = { GPIOZ_12 };
+
+/* Bank Z func7 */
+static const unsigned int gen_clk_z9_pins[] = { GPIOZ_9 };
+static const unsigned int gen_clk_z12_pins[] = { GPIOZ_12 };
+
+static struct meson_pmx_group meson_s4_periphs_groups[] = {
+ GPIO_GROUP(GPIOE_0),
+ GPIO_GROUP(GPIOE_1),
+
+ GPIO_GROUP(GPIOB_0),
+ GPIO_GROUP(GPIOB_1),
+ GPIO_GROUP(GPIOB_2),
+ GPIO_GROUP(GPIOB_3),
+ GPIO_GROUP(GPIOB_4),
+ GPIO_GROUP(GPIOB_5),
+ GPIO_GROUP(GPIOB_6),
+ GPIO_GROUP(GPIOB_7),
+ GPIO_GROUP(GPIOB_8),
+ GPIO_GROUP(GPIOB_9),
+ GPIO_GROUP(GPIOB_10),
+ GPIO_GROUP(GPIOB_11),
+ GPIO_GROUP(GPIOB_12),
+ GPIO_GROUP(GPIOB_13),
+
+ GPIO_GROUP(GPIOC_0),
+ GPIO_GROUP(GPIOC_1),
+ GPIO_GROUP(GPIOC_2),
+ GPIO_GROUP(GPIOC_3),
+ GPIO_GROUP(GPIOC_4),
+ GPIO_GROUP(GPIOC_5),
+ GPIO_GROUP(GPIOC_6),
+ GPIO_GROUP(GPIOC_7),
+
+ GPIO_GROUP(GPIOD_0),
+ GPIO_GROUP(GPIOD_1),
+ GPIO_GROUP(GPIOD_2),
+ GPIO_GROUP(GPIOD_3),
+ GPIO_GROUP(GPIOD_4),
+ GPIO_GROUP(GPIOD_5),
+ GPIO_GROUP(GPIOD_6),
+ GPIO_GROUP(GPIOD_7),
+ GPIO_GROUP(GPIOD_8),
+ GPIO_GROUP(GPIOD_9),
+ GPIO_GROUP(GPIOD_10),
+ GPIO_GROUP(GPIOD_11),
+
+ GPIO_GROUP(GPIOH_0),
+ GPIO_GROUP(GPIOH_1),
+ GPIO_GROUP(GPIOH_2),
+ GPIO_GROUP(GPIOH_3),
+ GPIO_GROUP(GPIOH_4),
+ GPIO_GROUP(GPIOH_5),
+ GPIO_GROUP(GPIOH_6),
+ GPIO_GROUP(GPIOH_7),
+ GPIO_GROUP(GPIOH_8),
+ GPIO_GROUP(GPIOH_9),
+ GPIO_GROUP(GPIOH_10),
+ GPIO_GROUP(GPIOH_11),
+
+ GPIO_GROUP(GPIOX_0),
+ GPIO_GROUP(GPIOX_1),
+ GPIO_GROUP(GPIOX_2),
+ GPIO_GROUP(GPIOX_3),
+ GPIO_GROUP(GPIOX_4),
+ GPIO_GROUP(GPIOX_5),
+ GPIO_GROUP(GPIOX_6),
+ GPIO_GROUP(GPIOX_7),
+ GPIO_GROUP(GPIOX_8),
+ GPIO_GROUP(GPIOX_9),
+ GPIO_GROUP(GPIOX_10),
+ GPIO_GROUP(GPIOX_11),
+ GPIO_GROUP(GPIOX_12),
+ GPIO_GROUP(GPIOX_13),
+ GPIO_GROUP(GPIOX_14),
+ GPIO_GROUP(GPIOX_15),
+ GPIO_GROUP(GPIOX_16),
+ GPIO_GROUP(GPIOX_17),
+ GPIO_GROUP(GPIOX_18),
+ GPIO_GROUP(GPIOX_19),
+
+ GPIO_GROUP(GPIOZ_0),
+ GPIO_GROUP(GPIOZ_1),
+ GPIO_GROUP(GPIOZ_2),
+ GPIO_GROUP(GPIOZ_3),
+ GPIO_GROUP(GPIOZ_4),
+ GPIO_GROUP(GPIOZ_5),
+ GPIO_GROUP(GPIOZ_6),
+ GPIO_GROUP(GPIOZ_7),
+ GPIO_GROUP(GPIOZ_8),
+ GPIO_GROUP(GPIOZ_9),
+ GPIO_GROUP(GPIOZ_10),
+ GPIO_GROUP(GPIOZ_11),
+ GPIO_GROUP(GPIOZ_12),
+
+ GPIO_GROUP(GPIO_TEST_N),
+
+ /* BANK E func1 */
+ GROUP(i2c0_sda, 1),
+ GROUP(i2c0_scl, 1),
+
+ /* BANK E func2 */
+ GROUP(uart_b_tx_e, 2),
+ GROUP(uart_b_rx_e, 2),
+
+ /* BANK E func3 */
+ GROUP(pwm_h, 3),
+ GROUP(pwm_j, 3),
+
+ /* BANK B func1 */
+ GROUP(emmc_nand_d0, 1),
+ GROUP(emmc_nand_d1, 1),
+ GROUP(emmc_nand_d2, 1),
+ GROUP(emmc_nand_d3, 1),
+ GROUP(emmc_nand_d4, 1),
+ GROUP(emmc_nand_d5, 1),
+ GROUP(emmc_nand_d6, 1),
+ GROUP(emmc_nand_d7, 1),
+ GROUP(emmc_clk, 1),
+ GROUP(emmc_rst, 1),
+ GROUP(emmc_cmd, 1),
+ GROUP(emmc_nand_ds, 1),
+
+ /* Bank B func2 */
+ GROUP(nand_wen_clk, 2),
+ GROUP(nand_ale, 2),
+ GROUP(nand_ren_wr, 2),
+ GROUP(nand_cle, 2),
+ GROUP(nand_ce0, 2),
+
+ /* Bank B func3 */
+ GROUP(spif_hold, 3),
+ GROUP(spif_mo, 3),
+ GROUP(spif_mi, 3),
+ GROUP(spif_clk, 3),
+ GROUP(spif_wp, 3),
+ GROUP(spif_cs, 3),
+
+ /* Bank C func1 */
+ GROUP(sdcard_d0_c, 1),
+ GROUP(sdcard_d1_c, 1),
+ GROUP(sdcard_d2_c, 1),
+ GROUP(sdcard_d3_c, 1),
+ GROUP(sdcard_clk_c, 1),
+ GROUP(sdcard_cmd_c, 1),
+ GROUP(sdcard_cd, 1),
+
+ /* Bank C func2 */
+ GROUP(jtag_2_tdo, 2),
+ GROUP(jtag_2_tdi, 2),
+ GROUP(uart_b_rx_c, 2),
+ GROUP(uart_b_tx_c, 2),
+ GROUP(jtag_2_clk, 2),
+ GROUP(jtag_2_tms, 2),
+ GROUP(i2c1_sda_c, 2),
+ GROUP(i2c1_scl_c, 2),
+
+ /* Bank C func3 */
+ GROUP(pdm_din1_c, 3),
+ GROUP(pdm_din0_c, 3),
+ GROUP(i2c4_sda_c, 3),
+ GROUP(i2c4_scl_c, 3),
+ GROUP(pdm_dclk_c, 3),
+ GROUP(iso7816_clk_c, 3),
+ GROUP(iso7816_data_c, 3),
+
+ /* Bank C func4 */
+ GROUP(tdm_d2_c, 4),
+ GROUP(tdm_d3_c, 4),
+ GROUP(tdm_fs1_c, 4),
+ GROUP(mclk_1_c, 4),
+ GROUP(tdm_d4_c, 4),
+ GROUP(tdm_d5_c, 4),
+
+ /* Bank D func1 */
+ GROUP(uart_b_tx_d, 1),
+ GROUP(uart_b_rx_d, 1),
+ GROUP(uart_b_cts_d, 1),
+ GROUP(uart_b_rts_d, 1),
+ GROUP(remote_out, 1),
+ GROUP(remote_in, 1),
+ GROUP(jtag_1_clk, 1),
+ GROUP(jtag_1_tms, 1),
+ GROUP(jtag_1_tdi, 1),
+ GROUP(jtag_1_tdo, 1),
+ GROUP(clk12_24, 1),
+ GROUP(pwm_g_hiz, 1),
+
+ /* Bank D func2 */
+ GROUP(i2c4_sda_d, 2),
+ GROUP(i2c4_scl_d, 2),
+ GROUP(mclk_1_d, 2),
+ GROUP(tdm_sclk1_d, 2),
+ GROUP(tdm_fs1_d, 2),
+ GROUP(tdm_d4_d, 2),
+ GROUP(tdm_d3_d, 2),
+ GROUP(tdm_d2_d, 2),
+ GROUP(pwm_g_d, 2),
+
+ /* Bank D func3 */
+ GROUP(uart_c_tx, 3),
+ GROUP(uart_c_rx, 3),
+ GROUP(pwm_b_d, 3),
+ GROUP(pwm_a_d, 3),
+ GROUP(pwm_c_d, 3),
+ GROUP(pwm_d_d, 3),
+ GROUP(pwm_i_d, 3),
+
+ /* Bank D func4 */
+ GROUP(clk_32k_in, 4),
+ GROUP(pwm_b_hiz, 4),
+ GROUP(pwm_a_hiz, 4),
+ GROUP(pwm_c_hiz, 4),
+ GROUP(pdm_dclk_d, 4),
+ GROUP(pdm_din0_d, 4),
+ GROUP(pdm_din1_d, 4),
+
+ /* Bank D func5 */
+ GROUP(mic_mute_en, 5),
+ GROUP(mic_mute_key, 5),
+ GROUP(i2c1_sda_d, 5),
+ GROUP(i2c1_scl_d, 5),
+ GROUP(i2c2_sda_d, 5),
+ GROUP(i2c2_scl_d, 5),
+
+ /* Bank D func6 */
+ GROUP(gen_clk_d, 6),
+
+ /* Bank H func1 */
+ GROUP(hdmitx_sda, 1),
+ GROUP(hdmitx_sck, 1),
+ GROUP(hdmitx_hpd_in, 1),
+ GROUP(ao_cec_a, 1),
+ GROUP(spdif_out_h, 1),
+ GROUP(spdif_in, 1),
+ GROUP(i2c1_sda_h, 1),
+ GROUP(i2c1_scl_h, 1),
+ GROUP(i2c2_sda_h8, 1),
+ GROUP(i2c2_scl_h9, 1),
+ GROUP(eth_link_led, 1),
+ GROUP(eth_act_led, 1),
+
+ /* Bank H func2 */
+ GROUP(i2c2_sda_h0, 2),
+ GROUP(i2c2_scl_h1, 2),
+ GROUP(ao_cec_b, 2),
+ GROUP(uart_d_tx_h, 2),
+ GROUP(uart_d_rx_h, 2),
+ GROUP(uart_d_cts_h, 2),
+ GROUP(uart_d_rts_h, 2),
+ GROUP(iso7816_clk_h, 2),
+ GROUP(iso7816_data_h, 2),
+ GROUP(uart_e_tx_h, 2),
+ GROUP(uart_e_rx_h, 2),
+
+ /* Bank H func3 */
+ GROUP(pwm_d_h, 3),
+ GROUP(pwm_i_h, 3),
+ GROUP(pdm_dclk_h, 3),
+ GROUP(pdm_din0_h, 3),
+ GROUP(pdm_din1_h, 3),
+
+ /* Bank H func4 */
+ GROUP(mclk_1_h, 4),
+ GROUP(tdm_sclk1_h, 4),
+ GROUP(tdm_fs1_h, 4),
+ GROUP(tdm_d2_h, 4),
+ GROUP(tdm_d3_h, 4),
+ GROUP(tdm_d4_h, 4),
+
+ /* Bank H func5 */
+ GROUP(spi_a_miso_h, 5),
+ GROUP(spi_a_mosi_h, 5),
+ GROUP(spi_a_clk_h, 5),
+ GROUP(spi_a_ss0_h, 5),
+
+ /* Bank H func6 */
+ GROUP(gen_clk_h, 6),
+
+
+ /* Bank X func1 */
+ GROUP(sdio_d0, 1),
+ GROUP(sdio_d1, 1),
+ GROUP(sdio_d2, 1),
+ GROUP(sdio_d3, 1),
+ GROUP(sdio_clk, 1),
+ GROUP(sdio_cmd, 1),
+ GROUP(pwm_a_x, 1),
+ GROUP(pwm_f_x, 1),
+ GROUP(tdm_d1, 1),
+ GROUP(tdm_d0, 1),
+ GROUP(tdm_fs0, 1),
+ GROUP(tdm_sclk0, 1),
+ GROUP(uart_a_tx, 1),
+ GROUP(uart_a_rx, 1),
+ GROUP(uart_a_cts, 1),
+ GROUP(uart_a_rts, 1),
+ GROUP(pwm_e_x, 1),
+ GROUP(i2c1_sda_x, 1),
+ GROUP(i2c1_scl_x, 1),
+ GROUP(pwm_b_x, 1),
+
+ /* Bank X func2 */
+ GROUP(pdm_din0_x, 2),
+ GROUP(pdm_din1_x, 2),
+ GROUP(pdm_dclk_x, 2),
+
+ /* Bank X func3 */
+ GROUP(spi_a_mosi_x, 3),
+ GROUP(spi_a_miso_x, 3),
+ GROUP(spi_a_ss0_x, 3),
+ GROUP(spi_a_clk_x, 3),
+
+ /* Bank X func4 */
+ GROUP(pwm_c_x, 4),
+ GROUP(i2c_slave_scl, 4),
+ GROUP(i2c_slave_sda, 4),
+
+ /* Bank X func5 */
+ GROUP(i2c3_sda_x, 5),
+ GROUP(i2c3_scl_x, 5),
+
+ /* Bank Z func1 */
+ GROUP(tdm_fs2, 1),
+ GROUP(tdm_sclk2, 1),
+ GROUP(tdm_d4_z, 1),
+ GROUP(tdm_d5_z, 1),
+ GROUP(tdm_d6, 1),
+ GROUP(tdm_d7, 1),
+ GROUP(mclk_2, 1),
+ GROUP(spdif_out_z, 1),
+ GROUP(dtv_a_if_agc_z10, 1),
+ GROUP(uart_e_tx_z11, 1),
+ GROUP(uart_e_rx_z12, 1),
+
+ /* Bank Z func2 */
+ GROUP(tsin_a_clk, 2),
+ GROUP(tsin_a_sop, 2),
+ GROUP(tsin_a_valid, 2),
+ GROUP(tsin_a_din0, 2),
+ GROUP(dtv_a_if_agc_z6, 2),
+ GROUP(dtv_b_if_agc, 2),
+ GROUP(i2c3_sda_z, 2),
+ GROUP(i2c3_scl_z, 2),
+ GROUP(dtv_a_rf_agc, 2),
+ GROUP(dtv_b_rf_agc, 2),
+
+ /* Bank Z func3 */
+ GROUP(sdcard_d0_z, 3),
+ GROUP(sdcard_d1_z, 3),
+ GROUP(sdcard_d2_z, 3),
+ GROUP(sdcard_d3_z, 3),
+ GROUP(sdcard_clk_z, 3),
+ GROUP(sdcard_cmd_z, 3),
+ GROUP(uart_e_tx_z8, 3),
+ GROUP(uart_e_rx_z9, 3),
+ GROUP(pdm_din1_z, 3),
+ GROUP(pdm_din0_z, 3),
+ GROUP(pdm_dclk_z, 3),
+
+ /* Bank Z func4 */
+ GROUP(spi_a_miso_z, 4),
+ GROUP(spi_a_mosi_z, 4),
+ GROUP(spi_a_clk_z, 4),
+ GROUP(spi_a_ss0_z, 4),
+ GROUP(spi_a_ss1_z, 4),
+ GROUP(spi_a_ss2_z, 4),
+ GROUP(i2c4_scl_z, 4),
+ GROUP(i2c4_sda_z, 4),
+
+ /* Bank Z func5 */
+ GROUP(uart_d_tx_z, 5),
+ GROUP(uart_d_rx_z, 5),
+ GROUP(uart_d_cts_z, 5),
+ GROUP(uart_d_rts_z, 5),
+ GROUP(pwm_g_z, 5),
+ GROUP(pwm_f_z, 5),
+ GROUP(pwm_e_z, 5),
+
+ /* Bank Z func6 */
+ GROUP(s2_demod_gpio7, 6),
+ GROUP(s2_demod_gpio6, 6),
+ GROUP(s2_demod_gpio5, 6),
+ GROUP(s2_demod_gpio4, 6),
+ GROUP(s2_demod_gpio3, 6),
+ GROUP(s2_demod_gpio2, 6),
+ GROUP(diseqc_out, 6),
+ GROUP(s2_demod_gpio1, 6),
+ GROUP(s2_demod_gpio0, 6),
+
+ /* Bank Z func7 */
+ GROUP(gen_clk_z9, 7),
+ GROUP(gen_clk_z12, 7)
+};
+
+static const char * const gpio_periphs_groups[] = {
+ "GPIOE_0", "GPIOE_1",
+
+ "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4", "GPIOB_5",
+ "GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9", "GPIOB_10", "GPIOB_11",
+ "GPIOB_12", "GPIOB_13",
+
+ "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", "GPIOC_5",
+ "GPIOC_6", "GPIOC_7",
+
+ "GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4", "GPIOD_5",
+ "GPIOD_6", "GPIOD_7", "GPIOD_8", "GPIOD_9", "GPIOD_10", "GPIOD_11",
+
+ "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", "GPIOH_5",
+ "GPIOH_6", "GPIOH_7", "GPIOH_8", "GPIOH_9", "GPIOH_10", "GPIOH_11",
+
+ "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", "GPIOX_5",
+ "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11",
+ "GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15", "GPIOX_16", "GPIOX_17",
+ "GPIOX_18", "GPIOX_19",
+
+ "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", "GPIOZ_5",
+ "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", "GPIOZ_10",
+ "GPIOZ_11", "GPIOZ_12",
+
+ "GPIO_TEST_N"
+};
+
+static const char * const i2c0_groups[] = {
+ "i2c0_sda", "i2c0_scl"
+};
+
+static const char * const i2c1_groups[] = {
+ "i2c1_sda_c", "i2c1_scl_c",
+ "i2c1_sda_d", "i2c1_scl_d",
+ "i2c1_sda_h", "i2c1_scl_h",
+ "i2c1_sda_x", "i2c1_scl_x"
+};
+
+static const char * const i2c2_groups[] = {
+ "i2c2_sda_d", "i2c2_scl_d",
+ "i2c2_sda_h8", "i2c2_scl_h9",
+ "i2c2_sda_h0", "i2c2_scl_h1"
+};
+
+static const char * const i2c3_groups[] = {
+ "i2c3_sda_x", "i2c3_scl_x",
+ "i2c3_sda_z", "i2c3_scl_z"
+};
+
+static const char * const i2c4_groups[] = {
+ "i2c4_sda_c", "i2c4_scl_c",
+ "i2c4_sda_d", "i2c4_scl_d",
+ "i2c4_scl_z", "i2c4_sda_z"
+};
+
+static const char * const uart_a_groups[] = {
+ "uart_a_tx", "uart_a_rx", "uart_a_cts", "uart_a_rts"
+};
+
+static const char * const uart_b_groups[] = {
+ "uart_b_tx_e", "uart_b_rx_e", "uart_b_rx_c", "uart_b_tx_c",
+ "uart_b_tx_d", "uart_b_rx_d", "uart_b_cts_d", "uart_b_rts_d"
+};
+
+static const char * const uart_c_groups[] = {
+ "uart_c_tx", "uart_c_rx"
+};
+
+static const char * const uart_d_groups[] = {
+ "uart_d_tx_h", "uart_d_rx_h", "uart_d_cts_h", "uart_d_rts_h",
+ "uart_d_tx_z", "uart_d_rx_z", "uart_d_cts_z", "uart_d_rts_z"
+};
+
+static const char * const uart_e_groups[] = {
+ "uart_e_tx_h", "uart_e_rx_h", "uart_e_tx_z11", "uart_e_rx_z12",
+ "uart_e_tx_z8", "uart_e_rx_z9"
+};
+
+static const char * const emmc_groups[] = {
+ "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3",
+ "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7",
+ "emmc_clk", "emmc_rst", "emmc_cmd", "emmc_nand_ds"
+};
+
+static const char * const nand_groups[] = {
+ "nand_wen_clk", "nand_ale", "nand_ren_wr", "nand_cle", "nand_ce0"
+};
+
+static const char * const spif_groups[] = {
+ "spif_hold", "spif_mo", "spif_mi", "spif_clk", "spif_wp",
+ "spif_cs"
+};
+
+static const char * const sdcard_groups[] = {
+ "sdcard_d0_c", "sdcard_d1_c", "sdcard_d2_c", "sdcard_d3_c",
+ "sdcard_clk_c", "sdcard_cmd_c", "sdcard_cd",
+ "sdcard_d0_z", "sdcard_d1_z", "sdcard_d2_z", "sdcard_d3_z",
+ "sdcard_clk_z", "sdcard_cmd_z"
+};
+
+static const char * const jtag_1_groups[] = {
+ "jtag_1_clk", "jtag_1_tms", "jtag_1_tdi", "jtag_1_tdo"
+};
+
+static const char * const jtag_2_groups[] = {
+ "jtag_2_tdo", "jtag_2_tdi", "jtag_2_clk", "jtag_2_tms"
+};
+
+static const char * const pdm_groups[] = {
+ "pdm_din1_c", "pdm_din0_c", "pdm_dclk_c",
+ "pdm_dclk_d", "pdm_din0_d", "pdm_din1_d",
+ "pdm_dclk_h", "pdm_din0_h", "pdm_din1_h",
+ "pdm_din0_x", "pdm_din1_x", "pdm_dclk_x",
+ "pdm_din1_z", "pdm_din0_z", "pdm_dclk_z"
+};
+
+static const char * const iso7816_groups[] = {
+ "iso7816_clk_c", "iso7816_data_c",
+ "iso7816_clk_h", "iso7816_data_h"
+};
+
+static const char * const tdm_groups[] = {
+ "tdm_d2_c", "tdm_d3_c", "tdm_fs1_c", "tdm_d4_c", "tdm_d5_c",
+ "tdm_fs1_d", "tdm_d4_d", "tdm_d3_d", "tdm_d2_d",
+ "tdm_sclk1_h", "tdm_fs1_h", "tdm_d2_h", "tdm_d3_h", "tdm_d4_h",
+ "tdm_d1", "tdm_d0", "tdm_fs0", "tdm_sclk0", "tdm_fs2", "tdm_sclk2",
+ "tdm_d4_z", "tdm_d5_z", "tdm_d6", "tdm_d7"
+};
+
+static const char * const mclk_groups[] = {
+ "mclk_1_c", "mclk_1_d", "mclk_1_h", "mclk_2"
+};
+
+static const char * const remote_out_groups[] = {
+ "remote_out"
+};
+
+static const char * const remote_in_groups[] = {
+ "remote_in"
+};
+
+static const char * const clk12_24_groups[] = {
+ "clk12_24"
+};
+
+static const char * const clk_32k_in_groups[] = {
+ "clk_32k_in"
+};
+
+static const char * const pwm_a_hiz_groups[] = {
+ "pwm_a_hiz"
+};
+
+static const char * const pwm_b_hiz_groups[] = {
+ "pwm_b_hiz"
+};
+
+static const char * const pwm_c_hiz_groups[] = {
+ "pwm_c_hiz"
+};
+
+static const char * const pwm_g_hiz_groups[] = {
+ "pwm_g_hiz"
+};
+
+static const char * const pwm_a_groups[] = {
+ "pwm_a_d"
+};
+
+static const char * const pwm_b_groups[] = {
+ "pwm_b_d", "pwm_b_x"
+
+};
+
+static const char * const pwm_c_groups[] = {
+ "pwm_c_d", "pwm_c_x"
+};
+
+static const char * const pwm_d_groups[] = {
+ "pwm_d_d", "pwm_d_h"
+};
+
+static const char * const pwm_e_groups[] = {
+ "pwm_e_x", "pwm_e_z"
+};
+
+static const char * const pwm_f_groups[] = {
+ "pwm_f_x", "pwm_f_z"
+};
+
+static const char * const pwm_g_groups[] = {
+ "pwm_g_d", "pwm_g_z"
+};
+
+static const char * const pwm_h_groups[] = {
+ "pwm_h",
+};
+
+static const char * const pwm_i_groups[] = {
+ "pwm_i_d", "pwm_i_h"
+};
+
+static const char * const pwm_j_groups[] = {
+ "pwm_j"
+};
+
+static const char * const mic_mute_groups[] = {
+ "mic_mute_en", "mic_mute_key"
+};
+
+static const char * const hdmitx_groups[] = {
+ "hdmitx_sda", "hdmitx_sck", "hdmitx_hpd_in"
+};
+
+static const char * const ao_cec_a_groups[] = {
+ "ao_cec_a"
+};
+
+static const char * const ao_cec_b_groups[] = {
+ "ao_cec_b"
+};
+
+static const char * const spdif_out_groups[] = {
+ "spdif_out_h", "spdif_out_z"
+};
+
+static const char * const spdif_in_groups[] = {
+ "spdif_in"
+};
+
+static const char * const eth_groups[] = {
+ "eth_link_led", "eth_act_led"
+};
+
+static const char * const spi_a_groups[] = {
+ "spi_a_miso_h", "spi_a_mosi_h", "spi_a_clk_h", "spi_a_ss0_h",
+
+ "spi_a_mosi_x", "spi_a_miso_x", "spi_a_ss0_x", "spi_a_clk_x",
+
+ "spi_a_miso_z", "spi_a_mosi_z", "spi_a_clk_z", "spi_a_ss0_z",
+ "spi_a_ss1_z", "spi_a_ss2_z"
+};
+
+static const char * const gen_clk_groups[] = {
+ "gen_clk_h", "gen_clk_z9", "gen_clk_z12"
+};
+
+static const char * const sdio_groups[] = {
+ "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", "sdio_clk", "sdio_cmd"
+};
+
+static const char * const i2c_slave_groups[] = {
+ "i2c_slave_scl", "i2c_slave_sda"
+};
+
+static const char * const dtv_groups[] = {
+ "dtv_a_if_agc_z10", "dtv_a_if_agc_z6", "dtv_b_if_agc",
+ "dtv_a_rf_agc", "dtv_b_rf_agc"
+};
+
+static const char * const tsin_a_groups[] = {
+ "tsin_a_clk", "tsin_a_sop", "tsin_a_valid", "tsin_a_din0"
+};
+
+static const char * const s2_demod_groups[] = {
+ "s2_demod_gpio7", "s2_demod_gpio6", "s2_demod_gpio5", "s2_demod_gpio4",
+ "s2_demod_gpio3", "s2_demod_gpio2", "s2_demod_gpio1", "s2_demod_gpio0"
+};
+
+static struct meson_pmx_func meson_s4_periphs_functions[] = {
+ FUNCTION(gpio_periphs),
+ FUNCTION(i2c0),
+ FUNCTION(i2c1),
+ FUNCTION(i2c2),
+ FUNCTION(i2c3),
+ FUNCTION(i2c4),
+ FUNCTION(uart_a),
+ FUNCTION(uart_b),
+ FUNCTION(uart_c),
+ FUNCTION(uart_d),
+ FUNCTION(uart_e),
+ FUNCTION(emmc),
+ FUNCTION(nand),
+ FUNCTION(spif),
+ FUNCTION(sdcard),
+ FUNCTION(jtag_1),
+ FUNCTION(jtag_2),
+ FUNCTION(pdm),
+ FUNCTION(iso7816),
+ FUNCTION(tdm),
+ FUNCTION(mclk),
+ FUNCTION(remote_out),
+ FUNCTION(remote_in),
+ FUNCTION(clk12_24),
+ FUNCTION(clk_32k_in),
+ FUNCTION(pwm_a_hiz),
+ FUNCTION(pwm_b_hiz),
+ FUNCTION(pwm_c_hiz),
+ FUNCTION(pwm_g_hiz),
+ FUNCTION(pwm_a),
+ FUNCTION(pwm_b),
+ FUNCTION(pwm_c),
+ FUNCTION(pwm_d),
+ FUNCTION(pwm_e),
+ FUNCTION(pwm_f),
+ FUNCTION(pwm_g),
+ FUNCTION(pwm_h),
+ FUNCTION(pwm_i),
+ FUNCTION(pwm_j),
+ FUNCTION(mic_mute),
+ FUNCTION(hdmitx),
+ FUNCTION(ao_cec_a),
+ FUNCTION(ao_cec_b),
+ FUNCTION(spdif_out),
+ FUNCTION(spdif_in),
+ FUNCTION(eth),
+ FUNCTION(spi_a),
+ FUNCTION(gen_clk),
+ FUNCTION(sdio),
+ FUNCTION(i2c_slave),
+ FUNCTION(dtv),
+ FUNCTION(tsin_a),
+ FUNCTION(s2_demod)
+};
+
+static struct meson_bank meson_s4_periphs_banks[] = {
+ /* name first last irq pullen pull dir out in */
+ BANK("GPIOB_", GPIOB_0, GPIOB_13,
+ 0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0),
+ BANK("GPIOC_", GPIOC_0, GPIOC_7,
+ 0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0),
+ BANK("GPIOE_", GPIOE_0, GPIOE_1,
+ 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0),
+ BANK("GPIOD_", GPIOD_0, GPIOD_11,
+ 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0),
+ BANK("GPIOH_", GPIOH_0, GPIOH_11,
+ 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0),
+ BANK("GPIOX_", GPIOX_0, GPIOX_19,
+ 0x13, 0, 0x14, 0, 0x12, 0, 0x11, 0, 0x10, 0),
+ BANK("GPIOZ_", GPIOZ_0, GPIOZ_12,
+ 0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0),
+ BANK("GPIO_TEST_N_", GPIO_TEST_N, GPIO_TEST_N,
+ 0x83, 0, 0x84, 0, 0x82, 0, 0x81, 0, 0x80, 0)
+};
+
+static struct meson_pmx_bank meson_s4_periphs_pmx_banks[] = {
+ /*name first lask reg offset*/
+ BANK_PMX("B", GPIOB_0, GPIOB_13, 0x00, 0),
+ BANK_PMX("C", GPIOC_0, GPIOC_7, 0x9, 0),
+ BANK_PMX("E", GPIOE_0, GPIOE_1, 0x12, 0),
+ BANK_PMX("D", GPIOD_0, GPIOD_11, 0x10, 0),
+ BANK_PMX("H", GPIOH_0, GPIOH_11, 0xb, 0),
+ BANK_PMX("X", GPIOX_0, GPIOX_19, 0x3, 0),
+ BANK_PMX("Z", GPIOZ_0, GPIOZ_12, 0x6, 0),
+ BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0xf, 0)
+};
+
+static struct meson_drive_bank meson_s4_periphs_drive_banks[] = {
+ /* name first lask reg offset*/
+ BANK_DRIVE("B", GPIOB_0, GPIOB_13, 0x67, 0),
+ BANK_DRIVE("C", GPIOC_0, GPIOC_7, 0x57, 0),
+ BANK_DRIVE("E", GPIOE_0, GPIOE_1, 0x47, 0),
+ BANK_DRIVE("D", GPIOD_0, GPIOD_11, 0x37, 0),
+ BANK_DRIVE("H", GPIOH_0, GPIOH_11, 0x27, 0),
+ BANK_DRIVE("X", GPIOX_0, GPIOX_19, 0x17, 0),
+ BANK_DRIVE("Z", GPIOZ_0, GPIOZ_12, 0x07, 0),
+ BANK_DRIVE("TESTN", GPIO_TEST_N, GPIO_TEST_N, 0x87, 0)
+};
+
+static struct meson_axg_pmx_data meson_s4_periphs_pmx_banks_data = {
+ .pmx_banks = meson_s4_periphs_pmx_banks,
+ .num_pmx_banks = ARRAY_SIZE(meson_s4_periphs_pmx_banks),
+};
+
+static struct meson_drive_data meson_s4_periphs_drive_data = {
+ .drive_banks = meson_s4_periphs_drive_banks,
+ .num_drive_banks = ARRAY_SIZE(meson_s4_periphs_drive_banks),
+};
+
+static struct meson_pinctrl_data meson_s4_periphs_pinctrl_data = {
+ .name = "periphs-banks",
+ .groups = meson_s4_periphs_groups,
+ .funcs = meson_s4_periphs_functions,
+ .banks = meson_s4_periphs_banks,
+ .num_pins = 82,
+ .num_groups = ARRAY_SIZE(meson_s4_periphs_groups),
+ .num_funcs = ARRAY_SIZE(meson_s4_periphs_functions),
+ .num_banks = ARRAY_SIZE(meson_s4_periphs_banks),
+ .pmx_data = &meson_s4_periphs_pmx_banks_data,
+ .drv_data = &meson_s4_periphs_drive_data,
+};
+
+static const struct udevice_id meson_s4_pinctrl_match[] = {
+ {
+ .compatible = "amlogic,meson-s4-periphs-pinctrl",
+ .data = (ulong)&meson_s4_periphs_pinctrl_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(meson_s4_pinctrl) = {
+ .name = "meson-s4-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(meson_s4_pinctrl_match),
+ .probe = meson_pinctrl_probe,
+ .priv_auto_alloc_size = sizeof(struct meson_pinctrl),
+ .ops = &meson_axg_pinctrl_ops,
+};
diff --git a/drivers/pinctrl/meson/pinctrl-meson-sc2.c b/drivers/pinctrl/meson/pinctrl-meson-sc2.c
new file mode 100644
index 0000000..ce42116
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-sc2.c
@@ -0,0 +1,1285 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <dt-bindings/gpio/meson-sc2-gpio.h>
+
+#include "pinctrl-meson.h"
+#include "pinctrl-meson-axg-pmx.h"
+
+/*bank D func1 */
+static const unsigned int uart_b_tx_d_pins[] = { GPIOD_0 };
+static const unsigned int uart_b_rx_d_pins[] = { GPIOD_1 };
+static const unsigned int i2c_e_scl_d_pins[] = { GPIOD_2 };
+static const unsigned int i2c_e_sda_d_pins[] = { GPIOD_3 };
+static const unsigned int remote_out_d4_pins[] = { GPIOD_4 };
+static const unsigned int remote_input_d5_pins[] = { GPIOD_5 };
+static const unsigned int jtag_2_clk_pins[] = { GPIOD_6 };
+static const unsigned int jtag_2_tms_pins[] = { GPIOD_7 };
+static const unsigned int jtag_2_tdi_pins[] = { GPIOD_8 };
+static const unsigned int jtag_2_tdo_pins[] = { GPIOD_9 };
+static const unsigned int cec_a_d_pins[] = { GPIOD_10 };
+
+/*bank D func2 */
+static const unsigned int uart_a_tx_d2_pins[] = { GPIOD_2 };
+static const unsigned int uart_a_rx_d3_pins[] = { GPIOD_3 };
+static const unsigned int clk_32k_in_pins[] = { GPIOD_4 };
+static const unsigned int remote_out_d9_pins[] = { GPIOD_9 };
+static const unsigned int cec_b_d_pins[] = { GPIOD_10 };
+static const unsigned int pwm_g_hiz_pins[] = { GPIOD_11 };
+
+/*bank D func3 */
+static const unsigned int i2c_slave_scl_pins[] = { GPIOD_2 };
+static const unsigned int i2c_slave_sda_pins[] = { GPIOD_3 };
+static const unsigned int pwm_i_d4_pins[] = { GPIOD_4 };
+static const unsigned int pwm_j_d5_pins[] = { GPIOD_5 };
+static const unsigned int pwm_i_d6_pins[] = { GPIOD_6 };
+static const unsigned int uart_a_tx_d8_pins[] = { GPIOD_8 };
+static const unsigned int uart_a_rx_d9_pins[] = { GPIOD_9 };
+static const unsigned int pwm_j_d10_pins[] = { GPIOD_10 };
+static const unsigned int pwm_g_pins[] = { GPIOD_11 };
+
+/*bank D func4 */
+static const unsigned int pwm_i_hiz_pins[] = { GPIOD_4 };
+static const unsigned int tsin_a_sop_d_pins[] = { GPIOD_6 };
+static const unsigned int tsin_a_din0_d_pins[] = { GPIOD_7 };
+static const unsigned int tsin_a_clk_d_pins[] = { GPIOD_8 };
+static const unsigned int tsin_a_valid_d_pins[] = { GPIOD_9 };
+static const unsigned int spdif_out_d_pins[] = { GPIOD_10 };
+static const unsigned int gen_clk_d_pins[] = { GPIOD_11 };
+
+/*bank D func5 */
+static const unsigned int mic_mute_en_pins[] = { GPIOD_2 };
+static const unsigned int tdm_d0_pins[] = { GPIOD_4 };
+static const unsigned int tdm_d1_pins[] = { GPIOD_6 };
+static const unsigned int tdm_fs1_pins[] = { GPIOD_7 };
+static const unsigned int tdm_sclk1_pins[] = { GPIOD_8 };
+static const unsigned int mclk1_pins[] = { GPIOD_9 };
+static const unsigned int tdm_d2_d_pins[] = { GPIOD_10 };
+
+/*bank D func6 */
+static const unsigned int clk12_24_d_pins[] = { GPIOD_10 };
+
+/*bank E func1 */
+static const unsigned int uart_b_cts_pins[] = { GPIOE_0 };
+static const unsigned int uart_b_rts_pins[] = { GPIOE_1 };
+static const unsigned int clk12_24_e_pins[] = { GPIOE_2 };
+
+/*bank E funsc2 */
+static const unsigned int uart_a_cts_pins[] = { GPIOE_0 };
+static const unsigned int uart_a_rts_pins[] = { GPIOE_1 };
+static const unsigned int clk25_pins[] = { GPIOE_2 };
+
+/*bank E func3 */
+static const unsigned int pwm_h_pins[] = { GPIOE_0 };
+static const unsigned int pwm_j_e_pins[] = { GPIOE_1 };
+static const unsigned int pwm_a_e_pins[] = { GPIOE_2 };
+
+/*bank E func4 */
+static const unsigned int i2c_e_scl_e_pins[] = { GPIOE_0 };
+static const unsigned int i2c_e_sda_e_pins[] = { GPIOE_1 };
+
+/*bank E func5 */
+static const unsigned int mic_mute_key_pins[] = { GPIOE_2 };
+
+/*bank B func1 */
+static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 };
+static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 };
+static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 };
+static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 };
+static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 };
+static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 };
+static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 };
+static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 };
+static const unsigned int emmc_clk_pins[] = { GPIOB_8 };
+static const unsigned int emmc_cmd_pins[] = { GPIOB_10 };
+static const unsigned int emmc_nand_dqs_pins[] = { GPIOB_13 };
+
+/*bank B funsc2 */
+static const unsigned int nand_wen_clk_pins[] = { GPIOB_8 };
+static const unsigned int nand_ale_pins[] = { GPIOB_9 };
+static const unsigned int nand_cle_pins[] = { GPIOB_10 };
+static const unsigned int nand_ce0_pins[] = { GPIOB_11 };
+static const unsigned int nand_ren_wr_pins[] = { GPIOB_12 };
+static const unsigned int nand_rb0_pins[] = { GPIOB_14 };
+static const unsigned int nand_ce1_pins[] = { GPIOB_15 };
+
+/*bank B func3 */
+static const unsigned int nor_hold_pins[] = { GPIOB_3 };
+static const unsigned int nor_d_pins[] = { GPIOB_4 };
+static const unsigned int nor_q_pins[] = { GPIOB_5 };
+static const unsigned int nor_c_pins[] = { GPIOB_6 };
+static const unsigned int nor_wp_pins[] = { GPIOB_7 };
+static const unsigned int nor_cs_pins[] = { GPIOB_14 };
+
+/*bank C func1 */
+static const unsigned int sdcard_d0_c_pins[] = { GPIOC_0 };
+static const unsigned int sdcard_d1_c_pins[] = { GPIOC_1 };
+static const unsigned int sdcard_d2_c_pins[] = { GPIOC_2 };
+static const unsigned int sdcard_d3_c_pins[] = { GPIOC_3 };
+static const unsigned int sdcard_clk_c_pins[] = { GPIOC_4 };
+static const unsigned int sdcard_cmd_c_pins[] = { GPIOC_5 };
+static const unsigned int sdcard_cd_pins[] = { GPIOC_6 };
+static const unsigned int pcieck_reqn_pins[] = { GPIOC_7 };
+
+/*bank C funsc2 */
+static const unsigned int jtag_1_tdo_pins[] = { GPIOC_0 };
+static const unsigned int jtag_1_tdi_pins[] = { GPIOC_1 };
+static const unsigned int uart_b_rx_c_pins[] = { GPIOC_2 };
+static const unsigned int uart_b_tx_c_pins[] = { GPIOC_3 };
+static const unsigned int jtag_1_clk_pins[] = { GPIOC_4 };
+static const unsigned int jtag_1_tms_pins[] = { GPIOC_5 };
+
+/*bank C func3 */
+static const unsigned int tsin_c_valid_c_pins[] = { GPIOC_0 };
+static const unsigned int tsin_c_sop_c_pins[] = { GPIOC_1 };
+static const unsigned int tsin_c_din0_c_pins[] = { GPIOC_2 };
+static const unsigned int tsin_c_clk_c_pins[] = { GPIOC_3 };
+static const unsigned int i2c_a_sda_c_pins[] = { GPIOC_5 };
+static const unsigned int i2c_a_scl_c_pins[] = { GPIOC_6 };
+
+/*bank C func4 */
+static const unsigned int pdm_din0_c_pins[] = { GPIOC_0 };
+static const unsigned int pdm_din1_c1_pins[] = { GPIOC_1 };
+static const unsigned int pdm_din2_c_pins[] = { GPIOC_2 };
+static const unsigned int pdm_din3_c_pins[] = { GPIOC_3 };
+static const unsigned int pdm_dclk_c_pins[] = { GPIOC_4 };
+static const unsigned int pdm_din1_c7_pins[] = { GPIOC_7 };
+
+/*bank C func5 */
+static const unsigned int spi_a_mosi_c_pins[] = { GPIOC_0 };
+static const unsigned int spi_a_miso_c_pins[] = { GPIOC_1 };
+static const unsigned int spi_a_ss0_c_pins[] = { GPIOC_2 };
+static const unsigned int spi_a_sclk_c_pins[] = { GPIOC_3 };
+static const unsigned int pwm_c_c_pins[] = { GPIOC_4 };
+static const unsigned int iso7816_clk_c_pins[] = { GPIOC_5 };
+static const unsigned int iso7816_data_c_pins[] = { GPIOC_6 };
+
+/*bank X func1*/
+static const unsigned int sdio_d0_x_pins[] = { GPIOX_0 };
+static const unsigned int sdio_d1_x_pins[] = { GPIOX_1 };
+static const unsigned int sdio_d2_x_pins[] = { GPIOX_2 };
+static const unsigned int sdio_d3_x_pins[] = { GPIOX_3 };
+static const unsigned int sdio_clk_x_pins[] = { GPIOX_4 };
+static const unsigned int sdio_cmd_x_pins[] = { GPIOX_5 };
+static const unsigned int pwm_a_x_pins[] = { GPIOX_6 };
+static const unsigned int pwm_f_x_pins[] = { GPIOX_7 };
+static const unsigned int tdm_d3_pins[] = { GPIOX_8 };
+static const unsigned int tdm_d4_pins[] = { GPIOX_9 };
+static const unsigned int tdm_fs0_pins[] = { GPIOX_10 };
+static const unsigned int tdm_sclk0_pins[] = { GPIOX_11 };
+static const unsigned int uart_e_tx_pins[] = { GPIOX_12 };
+static const unsigned int uart_e_rx_pins[] = { GPIOX_13 };
+static const unsigned int uart_e_cts_pins[] = { GPIOX_14 };
+static const unsigned int uart_e_rts_pins[] = { GPIOX_15 };
+static const unsigned int pwm_e_pins[] = { GPIOX_16 };
+static const unsigned int i2c_c_sda_x_pins[] = { GPIOX_17 };
+static const unsigned int i2c_c_scl_x_pins[] = { GPIOX_18 };
+static const unsigned int pwm_b_x19_pins[] = { GPIOX_19 };
+
+/*bank X func2*/
+static const unsigned int pdm_din0_x_pins[] = { GPIOX_0 };
+static const unsigned int pdm_din1_x_pins[] = { GPIOX_1 };
+static const unsigned int pdm_din2_x_pins[] = { GPIOX_2 };
+static const unsigned int pdm_din3_x_pins[] = { GPIOX_3 };
+static const unsigned int pdm_dclk_x_pins[] = { GPIOX_4 };
+static const unsigned int mclk_0_pins[] = { GPIOX_5 };
+static const unsigned int uart_d_tx_x6_pins[] = { GPIOX_6 };
+static const unsigned int uart_d_rx_x7_pins[] = { GPIOX_7 };
+static const unsigned int uart_d_cts_pins[] = { GPIOX_8 };
+static const unsigned int uart_d_rts_pins[] = { GPIOX_9 };
+static const unsigned int uart_d_tx_x10_pins[] = { GPIOX_10 };
+static const unsigned int uart_d_rx_x11_pins[] = { GPIOX_11};
+static const unsigned int tdm_d15_x_pins[] = { GPIOX_19};
+
+/*bank X func3*/
+static const unsigned int tsin_a_din0_x_pins[] = { GPIOX_0 };
+static const unsigned int tsin_a_sop_x_pins[] = { GPIOX_1 };
+static const unsigned int tsin_a_valid_x_pins[] = { GPIOX_2 };
+static const unsigned int tsin_a_clk_x_pins[] = { GPIOX_3 };
+static const unsigned int tsin_d_sop_x_pins[] = { GPIOX_8 };
+static const unsigned int tsin_d_valid_x_pins[] = { GPIOX_9 };
+static const unsigned int tsin_d_din0_x_pins[] = { GPIOX_10 };
+static const unsigned int tsin_d_clk_x_pins[] = { GPIOX_11 };
+
+/*bank X func4*/
+static const unsigned int pwm_d_x3_pins[] = { GPIOX_3 };
+static const unsigned int pwm_c_x_pins[] = { GPIOX_5 };
+static const unsigned int pwm_d_x6_pins[] = { GPIOX_6 };
+static const unsigned int pwm_b_x7_pins[] = { GPIOX_7 };
+static const unsigned int spi_a_mosi_x_pins[] = { GPIOX_8 };
+static const unsigned int spi_a_miso_x_pins[] = { GPIOX_9 };
+static const unsigned int spi_a_ss0_x_pins[] = { GPIOX_10 };
+static const unsigned int spi_a_sclk_x_pins[] = { GPIOX_11 };
+
+/*bank X func5 */
+static const unsigned int sdcard_d0_x_pins[] = { GPIOX_0 };
+static const unsigned int sdcard_d1_x_pins[] = { GPIOX_1 };
+static const unsigned int sdcard_d2_x_pins[] = { GPIOX_2 };
+static const unsigned int sdcard_d3_x_pins[] = { GPIOX_3 };
+static const unsigned int sdcard_clk_x_pins[] = { GPIOX_4 };
+static const unsigned int sdcard_cd_x_pins[] = { GPIOX_5 };
+static const unsigned int iso7816_clk_x_pins[] = { GPIOX_8 };
+static const unsigned int iso7816_data_x_pins[] = { GPIOX_9 };
+static const unsigned int i2c_b_sda_x_pins[] = { GPIOX_10 };
+static const unsigned int i2c_b_scl_x_pins[] = { GPIOX_11 };
+static const unsigned int gen_clk_x_pins[] = { GPIOX_19 };
+
+/*bank H func1 */
+static const unsigned int hdmitx_sda_pins[] = { GPIOH_0 };
+static const unsigned int hdmitx_scl_pins[] = { GPIOH_1 };
+static const unsigned int hdmitx_hpd_in_pins[] = { GPIOH_2 };
+static const unsigned int spdif_out_h_pins[] = { GPIOH_4 };
+static const unsigned int spdif_in_h_pins[] = { GPIOH_5 };
+static const unsigned int iso7816_clk_h_pins[] = { GPIOH_6 };
+static const unsigned int iso7816_data_h_pins[] = { GPIOH_7 };
+
+/*bank H func2 */
+static const unsigned int i2c_d_sda_h_pins[] = { GPIOH_0 };
+static const unsigned int i2c_d_scl_h_pins[] = { GPIOH_1 };
+static const unsigned int i2c_b_sda_h2_pins[] = { GPIOH_2 };
+static const unsigned int i2c_b_scl_h3_pins[] = { GPIOH_3 };
+static const unsigned int uart_c_rts_pins[] = { GPIOH_4 };
+static const unsigned int uart_c_cts_pins[] = { GPIOH_5 };
+static const unsigned int uart_c_rx_pins[] = { GPIOH_6 };
+static const unsigned int uart_c_tx_pins[] = { GPIOH_7 };
+
+/*bank H func3 */
+static const unsigned int spi_b_mosi_h_pins[] = { GPIOH_4 };
+static const unsigned int spi_b_miso_h_pins[] = { GPIOH_5 };
+static const unsigned int spi_b_ss0_h_pins[] = { GPIOH_6 };
+static const unsigned int spi_b_sclk_h_pins[] = { GPIOH_7 };
+
+/*bank H func4 */
+static const unsigned int cec_a_h_pins[] = { GPIOH_3 };
+static const unsigned int pwm_f_h_pins[] = { GPIOH_5 };
+static const unsigned int i2c_b_sda_h6_pins[] = { GPIOH_6 };
+static const unsigned int i2c_b_scl_h7_pins[] = { GPIOH_7 };
+
+/*bank H func5 */
+static const unsigned int cec_b_h_pins[] = { GPIOH_3 };
+static const unsigned int tdm_d5_pins[] = { GPIOH_5 };
+static const unsigned int remote_out_h_pins[] = { GPIOH_6 };
+static const unsigned int pwm_b_h_pins[] = { GPIOH_7 };
+
+/*bank H func6 */
+static const unsigned int i2c_a_sda_h_pins[] = { GPIOH_4 };
+static const unsigned int i2c_a_scl_h_pins[] = { GPIOH_5 };
+
+/*bank Z func1 */
+static const unsigned int eth_mdio_pins[] = { GPIOZ_0 };
+static const unsigned int eth_mdc_pins[] = { GPIOZ_1 };
+static const unsigned int eth_rgmii_rx_clk_pins[] = { GPIOZ_2 };
+static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 };
+static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 };
+static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 };
+static const unsigned int eth_rxd2_rgmii_pins[] = { GPIOZ_6 };
+static const unsigned int eth_rxd3_rgmii_pins[] = { GPIOZ_7 };
+static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 };
+static const unsigned int eth_txen_pins[] = { GPIOZ_9 };
+static const unsigned int eth_txd0_pins[] = { GPIOZ_10 };
+static const unsigned int eth_txd1_pins[] = { GPIOZ_11 };
+static const unsigned int eth_txd2_rgmii_pins[] = { GPIOZ_12 };
+static const unsigned int eth_txd3_rgmii_pins[] = { GPIOZ_13 };
+static const unsigned int eth_link_led_pins[] = { GPIOZ_14 };
+static const unsigned int eth_act_led_pins[] = { GPIOZ_15 };
+
+/*bank Z func2 */
+static const unsigned int pwm_d_z_pins[] = { GPIOZ_2 };
+static const unsigned int clk12_24_z_pins[] = { GPIOZ_13 };
+
+/*bank Z func3 */
+static const unsigned int iso7816_clk_z0_pins[] = { GPIOZ_0 };
+static const unsigned int iso7816_data_z1_pins[] = { GPIOZ_1 };
+static const unsigned int tsin_b_valid_pins[] = { GPIOZ_2 };
+static const unsigned int tsin_b_sop_pins[] = { GPIOZ_3 };
+static const unsigned int tsin_b_din0_pins[] = { GPIOZ_4 };
+static const unsigned int tsin_b_clk_pins[] = { GPIOZ_5 };
+static const unsigned int tsin_b_fail_pins[] = { GPIOZ_6 };
+static const unsigned int tsin_b_din1_pins[] = { GPIOZ_7 };
+static const unsigned int tsin_b_din2_pins[] = { GPIOZ_8 };
+static const unsigned int tsin_b_din3_pins[] = { GPIOZ_9 };
+static const unsigned int tsin_b_din4_pins[] = { GPIOZ_10 };
+static const unsigned int tsin_b_din5_pins[] = { GPIOZ_11 };
+static const unsigned int tsin_b_din6_pins[] = { GPIOZ_12 };
+static const unsigned int tsin_b_din7_pins[] = { GPIOZ_13 };
+static const unsigned int i2c_c_sda_z14_pins[] = { GPIOZ_14 };
+static const unsigned int i2c_c_scl_z15_pins[] = { GPIOZ_15 };
+
+/*bank Z func4 */
+static const unsigned int i2c_a_sda_z0_pins[] = { GPIOZ_0 };
+static const unsigned int i2c_a_scl_z1_pins[] = { GPIOZ_1 };
+static const unsigned int tdm_d6_pins[] = { GPIOZ_2 };
+static const unsigned int tdm_d7_pins[] = { GPIOZ_3 };
+static const unsigned int tdm_d8_pins[] = { GPIOZ_4 };
+static const unsigned int tdm_d9_pins[] = { GPIOZ_5 };
+static const unsigned int tdm_fs2_pins[] = { GPIOZ_6 };
+static const unsigned int tdm_sclk2_pins[] = { GPIOZ_7 };
+static const unsigned int mclk_2_pins[] = { GPIOZ_8 };
+static const unsigned int tdm_d10_pins[] = { GPIOZ_9 };
+static const unsigned int tdm_d11_pins[] = { GPIOZ_10 };
+static const unsigned int tdm_d12_pins[] = { GPIOZ_11 };
+static const unsigned int tdm_d13_pins[] = { GPIOZ_12 };
+static const unsigned int tdm_d14_pins[] = { GPIOZ_13 };
+
+/*bank Z func5 */
+static const unsigned int pwm_b_z0_pins[] = { GPIOZ_0 };
+static const unsigned int pwm_c_z_pins[] = { GPIOZ_1 };
+static const unsigned int sdcard_d0_z_pins[] = { GPIOZ_2 };
+static const unsigned int sdcard_d1_z_pins[] = { GPIOZ_3 };
+static const unsigned int sdcard_d2_z_pins[] = { GPIOZ_4 };
+static const unsigned int sdcard_d3_z_pins[] = { GPIOZ_5 };
+static const unsigned int sdcard_clk_z_pins[] = { GPIOZ_6 };
+static const unsigned int sdcard_cmd_z_pins[] = { GPIOZ_7 };
+static const unsigned int iso7816_clk_z8_pins[] = { GPIOZ_8 };
+static const unsigned int iso7816_data_z9_pins[] = { GPIOZ_9 };
+static const unsigned int remote_out_z_pins[] = { GPIOZ_10 };
+static const unsigned int pwm_f_z_pins[] = { GPIOZ_12 };
+static const unsigned int pwm_b_z13_pins[] = { GPIOZ_13 };
+
+/*bank Z func6 */
+static const unsigned int i2c_b_sda_z_pins[] = { GPIOZ_0 };
+static const unsigned int i2c_b_scl_z_pins[] = { GPIOZ_1 };
+static const unsigned int tdm_fs3_pins[] = { GPIOZ_2 };
+static const unsigned int tdm_sclk3_pins[] = { GPIOZ_3 };
+static const unsigned int tdm_fs4_pins[] = { GPIOZ_4 };
+static const unsigned int tdm_sclk4_pins[] = { GPIOZ_5 };
+static const unsigned int tsin_c_valid_z_pins[] = { GPIOZ_6 };
+static const unsigned int tsin_c_sop_z_pins[] = { GPIOZ_7 };
+static const unsigned int tsin_c_din0_z_pins[] = { GPIOZ_8 };
+static const unsigned int tsin_c_clk_z_pins[] = { GPIOZ_9 };
+static const unsigned int tsin_d_valid_z_pins[] = { GPIOZ_10 };
+static const unsigned int tsin_d_sop_z_pins[] = { GPIOZ_11 };
+static const unsigned int tsin_d_din0_z_pins[] = { GPIOZ_12 };
+static const unsigned int tsin_d_clk_z_pins[] = { GPIOZ_13 };
+
+/*bank Z func7 */
+static const unsigned int pdm_din0_z_pins[] = { GPIOZ_2 };
+static const unsigned int pdm_din1_z_pins[] = { GPIOZ_3 };
+static const unsigned int pdm_din2_z_pins[] = { GPIOZ_4 };
+static const unsigned int pdm_din3_z_pins[] = { GPIOZ_5 };
+static const unsigned int pdm_dclk_z_pins[] = { GPIOZ_6 };
+static const unsigned int i2c_a_sda_z7_pins[] = { GPIOZ_7 };
+static const unsigned int i2c_a_scl_z8_pins[] = { GPIOZ_8 };
+static const unsigned int i2c_c_sda_z10_pins[] = { GPIOZ_10 };
+static const unsigned int i2c_c_scl_z11_pins[] = { GPIOZ_11 };
+static const unsigned int gen_clk_z_pins[] = { GPIOZ_13 };
+
+/*bank A func1 */
+static const unsigned int remote_input_a_pins[] = { GPIOA_15 };
+/*bank A func3 */
+static const unsigned int i2c_d_sda_a_pins[] = { GPIOA_14 };
+static const unsigned int i2c_d_scl_a_pins[] = { GPIOA_15 };
+/*bank A func5 */
+static const unsigned int pdm_din0_a_pins[] = { GPIOA_14 };
+static const unsigned int pdm_dclk_a_pins[] = { GPIOA_15 };
+/*bank A func7 */
+static const unsigned int gen_clk_a_pins[] = { GPIOA_15 };
+
+static struct meson_pmx_group meson_sc2_periphs_groups[] = {
+ GPIO_GROUP(GPIOD_0),
+ GPIO_GROUP(GPIOD_1),
+ GPIO_GROUP(GPIOD_2),
+ GPIO_GROUP(GPIOD_3),
+ GPIO_GROUP(GPIOD_4),
+ GPIO_GROUP(GPIOD_5),
+ GPIO_GROUP(GPIOD_6),
+ GPIO_GROUP(GPIOD_7),
+ GPIO_GROUP(GPIOD_8),
+ GPIO_GROUP(GPIOD_9),
+ GPIO_GROUP(GPIOD_10),
+ GPIO_GROUP(GPIOD_11),
+ GPIO_GROUP(GPIOE_0),
+ GPIO_GROUP(GPIOE_1),
+ GPIO_GROUP(GPIOE_2),
+ GPIO_GROUP(GPIOB_0),
+ GPIO_GROUP(GPIOB_1),
+ GPIO_GROUP(GPIOB_2),
+ GPIO_GROUP(GPIOB_3),
+ GPIO_GROUP(GPIOB_4),
+ GPIO_GROUP(GPIOB_5),
+ GPIO_GROUP(GPIOB_6),
+ GPIO_GROUP(GPIOB_7),
+ GPIO_GROUP(GPIOB_8),
+ GPIO_GROUP(GPIOB_9),
+ GPIO_GROUP(GPIOB_10),
+ GPIO_GROUP(GPIOB_11),
+ GPIO_GROUP(GPIOB_12),
+ GPIO_GROUP(GPIOB_13),
+ GPIO_GROUP(GPIOB_14),
+ GPIO_GROUP(GPIOB_15),
+ GPIO_GROUP(GPIOC_0),
+ GPIO_GROUP(GPIOC_1),
+ GPIO_GROUP(GPIOC_2),
+ GPIO_GROUP(GPIOC_3),
+ GPIO_GROUP(GPIOC_4),
+ GPIO_GROUP(GPIOC_5),
+ GPIO_GROUP(GPIOC_6),
+ GPIO_GROUP(GPIOC_7),
+ GPIO_GROUP(GPIOX_0),
+ GPIO_GROUP(GPIOX_1),
+ GPIO_GROUP(GPIOX_2),
+ GPIO_GROUP(GPIOX_3),
+ GPIO_GROUP(GPIOX_4),
+ GPIO_GROUP(GPIOX_5),
+ GPIO_GROUP(GPIOX_6),
+ GPIO_GROUP(GPIOX_7),
+ GPIO_GROUP(GPIOX_8),
+ GPIO_GROUP(GPIOX_9),
+ GPIO_GROUP(GPIOX_10),
+ GPIO_GROUP(GPIOX_11),
+ GPIO_GROUP(GPIOX_12),
+ GPIO_GROUP(GPIOX_13),
+ GPIO_GROUP(GPIOX_14),
+ GPIO_GROUP(GPIOX_15),
+ GPIO_GROUP(GPIOX_16),
+ GPIO_GROUP(GPIOX_17),
+ GPIO_GROUP(GPIOX_18),
+ GPIO_GROUP(GPIOX_19),
+ GPIO_GROUP(GPIOH_0),
+ GPIO_GROUP(GPIOH_1),
+ GPIO_GROUP(GPIOH_2),
+ GPIO_GROUP(GPIOH_3),
+ GPIO_GROUP(GPIOH_4),
+ GPIO_GROUP(GPIOH_5),
+ GPIO_GROUP(GPIOH_6),
+ GPIO_GROUP(GPIOH_7),
+ GPIO_GROUP(GPIOH_8),
+ GPIO_GROUP(GPIOZ_0),
+ GPIO_GROUP(GPIOZ_1),
+ GPIO_GROUP(GPIOZ_2),
+ GPIO_GROUP(GPIOZ_3),
+ GPIO_GROUP(GPIOZ_4),
+ GPIO_GROUP(GPIOZ_5),
+ GPIO_GROUP(GPIOZ_6),
+ GPIO_GROUP(GPIOZ_7),
+ GPIO_GROUP(GPIOZ_8),
+ GPIO_GROUP(GPIOZ_9),
+ GPIO_GROUP(GPIOZ_10),
+ GPIO_GROUP(GPIOZ_11),
+ GPIO_GROUP(GPIOZ_12),
+ GPIO_GROUP(GPIOZ_13),
+ GPIO_GROUP(GPIOZ_14),
+ GPIO_GROUP(GPIOZ_15),
+ GPIO_GROUP(GPIOA_14),
+ GPIO_GROUP(GPIOA_15),
+ GPIO_GROUP(GPIO_TEST_N),
+
+ /* bank D func1 */
+ GROUP(uart_b_tx_d, 1),
+ GROUP(uart_b_rx_d, 1),
+ GROUP(i2c_e_scl_d, 1),
+ GROUP(i2c_e_sda_d, 1),
+ GROUP(remote_out_d4, 1),
+ GROUP(remote_input_d5, 1),
+ GROUP(jtag_2_clk, 1),
+ GROUP(jtag_2_tms, 1),
+ GROUP(jtag_2_tdi, 1),
+ GROUP(jtag_2_tdo, 1),
+ GROUP(cec_a_d, 1),
+
+ /* bank D funsc2 */
+ GROUP(uart_a_tx_d2, 2),
+ GROUP(uart_a_rx_d3, 2),
+ GROUP(clk_32k_in, 2),
+ GROUP(remote_out_d9, 2),
+ GROUP(cec_b_d, 2),
+ GROUP(pwm_g_hiz, 2),
+
+ /* bank D func3 */
+ GROUP(i2c_slave_scl, 3),
+ GROUP(i2c_slave_sda, 3),
+ GROUP(pwm_i_d4, 3),
+ GROUP(pwm_j_d5, 3),
+ GROUP(pwm_i_d6, 3),
+ GROUP(uart_a_tx_d8, 3),
+ GROUP(uart_a_rx_d9, 3),
+ GROUP(pwm_j_d10, 3),
+ GROUP(pwm_g, 3),
+
+ /* bank D func4 */
+ GROUP(pwm_i_hiz, 4),
+ GROUP(tsin_a_sop_d, 4),
+ GROUP(tsin_a_din0_d, 4),
+ GROUP(tsin_a_clk_d, 4),
+ GROUP(tsin_a_valid_d, 4),
+ GROUP(spdif_out_d, 4),
+ GROUP(gen_clk_d, 4),
+
+ /* bank D func5 */
+ GROUP(mic_mute_en, 4),
+ GROUP(tdm_d0, 4),
+ GROUP(tdm_d1, 4),
+ GROUP(tdm_fs1, 4),
+ GROUP(tdm_sclk1, 4),
+ GROUP(mclk1, 4),
+ GROUP(tdm_d2_d, 4),
+
+ /* bank D func6 */
+ GROUP(clk12_24_d, 4),
+
+ /* bank E func1 */
+ GROUP(uart_b_cts, 1),
+ GROUP(uart_b_rts, 1),
+ GROUP(clk12_24_e, 1),
+
+ /* bank E funsc2 */
+ GROUP(uart_a_cts, 2),
+ GROUP(uart_a_rts, 2),
+ GROUP(clk25, 2),
+
+ /* bank E func3 */
+ GROUP(pwm_h, 3),
+ GROUP(pwm_j_e, 3),
+ GROUP(pwm_a_e, 3),
+
+ /* bank E func4 */
+ GROUP(i2c_e_scl_e, 4),
+ GROUP(i2c_e_sda_e, 4),
+
+ /*bank E func5 */
+ GROUP(mic_mute_key, 5),
+
+ /* bank B func1 */
+ GROUP(emmc_nand_d0, 1),
+ GROUP(emmc_nand_d1, 1),
+ GROUP(emmc_nand_d2, 1),
+ GROUP(emmc_nand_d3, 1),
+ GROUP(emmc_nand_d4, 1),
+ GROUP(emmc_nand_d5, 1),
+ GROUP(emmc_nand_d6, 1),
+ GROUP(emmc_nand_d7, 1),
+ GROUP(emmc_clk, 1),
+ GROUP(emmc_cmd, 1),
+ GROUP(emmc_nand_dqs, 1),
+
+ /* bank B funsc2 */
+ GROUP(nand_wen_clk, 2),
+ GROUP(nand_ale, 2),
+ GROUP(nand_cle, 2),
+ GROUP(nand_ce0, 2),
+ GROUP(nand_ren_wr, 2),
+ GROUP(nand_rb0, 2),
+ GROUP(nand_ce1, 2),
+
+ /* bank B func3 */
+ GROUP(nor_hold, 3),
+ GROUP(nor_d, 3),
+ GROUP(nor_q, 3),
+ GROUP(nor_c, 3),
+ GROUP(nor_wp, 3),
+ GROUP(nor_cs, 3),
+
+ /* bank C func1 */
+ GROUP(sdcard_d0_c, 1),
+ GROUP(sdcard_d1_c, 1),
+ GROUP(sdcard_d2_c, 1),
+ GROUP(sdcard_d3_c, 1),
+ GROUP(sdcard_clk_c, 1),
+ GROUP(sdcard_cmd_c, 1),
+ GROUP(sdcard_cd, 1),
+ GROUP(pcieck_reqn, 1),
+
+ /* bank C funsc2 */
+ GROUP(jtag_1_tdo, 2),
+ GROUP(jtag_1_tdi, 2),
+ GROUP(uart_b_rx_c, 2),
+ GROUP(uart_b_tx_c, 2),
+ GROUP(jtag_1_clk, 2),
+ GROUP(jtag_1_tms, 2),
+
+ /* bank C func3 */
+ GROUP(tsin_c_valid_c, 3),
+ GROUP(tsin_c_sop_c, 3),
+ GROUP(tsin_c_din0_c, 3),
+ GROUP(tsin_c_clk_c, 3),
+ GROUP(i2c_a_sda_c, 3),
+ GROUP(i2c_a_scl_c, 3),
+
+ /* bank C func4 */
+ GROUP(pdm_din0_c, 4),
+ GROUP(pdm_din1_c1, 4),
+ GROUP(pdm_din2_c, 4),
+ GROUP(pdm_din3_c, 4),
+ GROUP(pdm_dclk_c, 4),
+ GROUP(pdm_din1_c7, 4),
+
+ /* bank C func5 */
+ GROUP(spi_a_mosi_c, 4),
+ GROUP(spi_a_miso_c, 4),
+ GROUP(spi_a_ss0_c, 4),
+ GROUP(spi_a_sclk_c, 4),
+ GROUP(pwm_c_c, 4),
+ GROUP(iso7816_clk_c, 4),
+ GROUP(iso7816_data_c, 4),
+
+ /* bank X func1 */
+ GROUP(sdio_d0_x, 1),
+ GROUP(sdio_d1_x, 1),
+ GROUP(sdio_d2_x, 1),
+ GROUP(sdio_d3_x, 1),
+ GROUP(sdio_clk_x, 1),
+ GROUP(sdio_cmd_x, 1),
+ GROUP(pwm_a_x, 1),
+ GROUP(pwm_f_x, 1),
+ GROUP(tdm_d3, 1),
+ GROUP(tdm_d4, 1),
+ GROUP(tdm_fs0, 1),
+ GROUP(tdm_sclk0, 1),
+ GROUP(uart_e_tx, 1),
+ GROUP(uart_e_rx, 1),
+ GROUP(uart_e_cts, 1),
+ GROUP(uart_e_rts, 1),
+ GROUP(pwm_e, 1),
+ GROUP(i2c_c_sda_x, 1),
+ GROUP(i2c_c_scl_x, 1),
+ GROUP(pwm_b_x19, 1),
+
+ /* bank X funsc2 */
+ GROUP(pdm_din0_x, 2),
+ GROUP(pdm_din1_x, 2),
+ GROUP(pdm_din2_x, 2),
+ GROUP(pdm_din3_x, 2),
+ GROUP(pdm_dclk_x, 2),
+ GROUP(mclk_0, 2),
+ GROUP(uart_d_tx_x6, 2),
+ GROUP(uart_d_rx_x7, 2),
+ GROUP(uart_d_rts, 2),
+ GROUP(uart_d_cts, 2),
+ GROUP(uart_d_tx_x10, 2),
+ GROUP(uart_d_rx_x11, 2),
+ GROUP(tdm_d15_x, 2),
+
+ /* bank X func3 */
+ GROUP(tsin_a_din0_x, 3),
+ GROUP(tsin_a_sop_x, 3),
+ GROUP(tsin_a_valid_x, 3),
+ GROUP(tsin_a_clk_x, 3),
+ GROUP(tsin_d_sop_x, 3),
+ GROUP(tsin_d_valid_x, 3),
+ GROUP(tsin_d_din0_x, 3),
+ GROUP(tsin_d_clk_x, 3),
+
+ /* bank X func4 */
+ GROUP(pwm_d_x3, 4),
+ GROUP(pwm_c_x, 4),
+ GROUP(pwm_d_x6, 4),
+ GROUP(pwm_b_x7, 4),
+ GROUP(spi_a_mosi_x, 4),
+ GROUP(spi_a_miso_x, 4),
+ GROUP(spi_a_ss0_x, 4),
+ GROUP(spi_a_sclk_x, 4),
+
+ /* bank X func5 */
+ GROUP(sdcard_d0_x, 5),
+ GROUP(sdcard_d1_x, 5),
+ GROUP(sdcard_d2_x, 5),
+ GROUP(sdcard_d3_x, 5),
+ GROUP(sdcard_clk_x, 5),
+ GROUP(sdcard_cd_x, 5),
+ GROUP(iso7816_clk_x, 5),
+ GROUP(iso7816_data_x, 5),
+ GROUP(i2c_b_sda_x, 5),
+ GROUP(i2c_b_scl_x, 5),
+ GROUP(gen_clk_x, 5),
+
+ /* bank H func1 */
+ GROUP(hdmitx_sda, 1),
+ GROUP(hdmitx_scl, 1),
+ GROUP(hdmitx_hpd_in, 1),
+ GROUP(spdif_out_h, 1),
+ GROUP(spdif_in_h, 1),
+ GROUP(iso7816_data_h, 1),
+ GROUP(iso7816_clk_h, 1),
+
+ /* bank H funsc2 */
+ GROUP(i2c_d_sda_h, 2),
+ GROUP(i2c_d_scl_h, 2),
+ GROUP(i2c_b_sda_h2, 2),
+ GROUP(i2c_b_scl_h3, 2),
+ GROUP(uart_c_rts, 2),
+ GROUP(uart_c_cts, 2),
+ GROUP(uart_c_rx, 2),
+ GROUP(uart_c_tx, 2),
+
+ /* bank H func3 */
+ GROUP(spi_b_mosi_h, 3),
+ GROUP(spi_b_miso_h, 3),
+ GROUP(spi_b_ss0_h, 3),
+ GROUP(spi_b_sclk_h, 3),
+
+ /* bank H func4 */
+ GROUP(cec_a_h, 4),
+ GROUP(pwm_f_h, 4),
+ GROUP(i2c_b_sda_h6, 4),
+ GROUP(i2c_b_scl_h7, 4),
+
+ /* bank H func5 */
+ GROUP(cec_b_h, 5),
+ GROUP(tdm_d5, 5),
+ GROUP(remote_out_h, 5),
+ GROUP(pwm_b_h, 5),
+
+ /* bank H func6 */
+ GROUP(i2c_a_sda_h, 6),
+ GROUP(i2c_a_scl_h, 6),
+
+ /* bank Z func1 */
+ GROUP(eth_mdio, 1),
+ GROUP(eth_mdc, 1),
+ GROUP(eth_rgmii_rx_clk, 1),
+ GROUP(eth_rx_dv, 1),
+ GROUP(eth_rxd0, 1),
+ GROUP(eth_rxd1, 1),
+ GROUP(eth_rxd2_rgmii, 1),
+ GROUP(eth_rxd3_rgmii, 1),
+ GROUP(eth_rgmii_tx_clk, 1),
+ GROUP(eth_txen, 1),
+ GROUP(eth_txd0, 1),
+ GROUP(eth_txd1, 1),
+ GROUP(eth_txd2_rgmii, 1),
+ GROUP(eth_txd3_rgmii, 1),
+ GROUP(eth_link_led, 1),
+ GROUP(eth_act_led, 1),
+
+ /* bank Z funsc2 */
+ GROUP(pwm_d_z, 2),
+ GROUP(clk12_24_z, 2),
+
+ /* bank Z func3 */
+ GROUP(iso7816_clk_z0, 3),
+ GROUP(iso7816_data_z1, 3),
+ GROUP(tsin_b_valid, 3),
+ GROUP(tsin_b_sop, 3),
+ GROUP(tsin_b_din0, 3),
+ GROUP(tsin_b_clk, 3),
+ GROUP(tsin_b_fail, 3),
+ GROUP(tsin_b_din1, 3),
+ GROUP(tsin_b_din2, 3),
+ GROUP(tsin_b_din3, 3),
+ GROUP(tsin_b_din4, 3),
+ GROUP(tsin_b_din5, 3),
+ GROUP(tsin_b_din6, 3),
+ GROUP(tsin_b_din7, 3),
+ GROUP(i2c_c_sda_z14, 3),
+ GROUP(i2c_c_scl_z15, 3),
+
+ /* bank Z func4 */
+ GROUP(i2c_a_sda_z0, 4),
+ GROUP(i2c_a_scl_z1, 4),
+ GROUP(tdm_d6, 4),
+ GROUP(tdm_d7, 4),
+ GROUP(tdm_d8, 4),
+ GROUP(tdm_d9, 4),
+ GROUP(tdm_fs2, 4),
+ GROUP(tdm_sclk2, 4),
+ GROUP(mclk_2, 4),
+ GROUP(tdm_d10, 4),
+ GROUP(tdm_d11, 4),
+ GROUP(tdm_d12, 4),
+ GROUP(tdm_d13, 4),
+ GROUP(tdm_d14, 4),
+
+ /* bank Z func5 */
+ GROUP(pwm_b_z0, 5),
+ GROUP(pwm_c_z, 5),
+ GROUP(sdcard_d0_z, 5),
+ GROUP(sdcard_d1_z, 5),
+ GROUP(sdcard_d2_z, 5),
+ GROUP(sdcard_d3_z, 5),
+ GROUP(sdcard_clk_z, 5),
+ GROUP(sdcard_cmd_z, 5),
+ GROUP(iso7816_clk_z8, 5),
+ GROUP(iso7816_data_z9, 5),
+ GROUP(remote_out_z, 5),
+ GROUP(pwm_f_z, 5),
+ GROUP(pwm_b_z13, 5),
+
+ /* bank Z func6 */
+ GROUP(i2c_b_sda_z, 6),
+ GROUP(i2c_b_scl_z, 6),
+ GROUP(tdm_fs3, 6),
+ GROUP(tdm_sclk3, 6),
+ GROUP(tdm_fs4, 6),
+ GROUP(tdm_sclk4, 6),
+ GROUP(tsin_c_valid_z, 6),
+ GROUP(tsin_c_sop_z, 6),
+ GROUP(tsin_c_din0_z, 6),
+ GROUP(tsin_c_clk_z, 6),
+ GROUP(tsin_d_valid_z, 6),
+ GROUP(tsin_d_sop_z, 6),
+ GROUP(tsin_d_din0_z, 6),
+ GROUP(tsin_d_clk_z, 6),
+
+ /* bank Z func7 */
+ GROUP(pdm_din0_z, 7),
+ GROUP(pdm_din1_z, 7),
+ GROUP(pdm_din2_z, 7),
+ GROUP(pdm_din3_z, 7),
+ GROUP(pdm_dclk_z, 7),
+ GROUP(i2c_a_sda_z7, 7),
+ GROUP(i2c_a_scl_z8, 7),
+ GROUP(i2c_c_sda_z10, 7),
+ GROUP(i2c_c_scl_z11, 7),
+ GROUP(gen_clk_z, 7),
+
+ /* bank A func1 */
+ GROUP(remote_input_a, 1),
+ /* bank A func3 */
+ GROUP(i2c_d_sda_a, 3),
+ GROUP(i2c_d_scl_a, 3),
+ /* bank A func5 */
+ GROUP(pdm_din0_a, 5),
+ GROUP(pdm_dclk_a, 5),
+ /* bank A func7 */
+ GROUP(gen_clk_a, 7),
+
+};
+
+static const char * const gpio_periphs_groups[] = {
+ "GPIO_TEST_N",
+
+ "GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4",
+ "GPIOD_5", "GPIOD_6", "GPIOD_7", "GPIOD_8", "GPIOD_9",
+ "GPIOD_10", "GPIOD_11", "GPIOD_12",
+
+ "GPIOE_0", "GPIOE_1", "GPIOE_2",
+
+ "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4",
+ "GPIOB_5", "GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9",
+ "GPIOB_10", "GPIOB_11", "GPIOB_12", "GPIOB_13",
+ "GPIOB_14", "GPIOB_15",
+
+ "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4",
+ "GPIOC_5", "GPIOC_6", "GPIOC_7",
+
+ "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4",
+ "GPIOX_5", "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9",
+ "GPIOX_10", "GPIOX_11", "GPIOX_12", "GPIOX_13", "GPIOX_14",
+ "GPIOX_15", "GPIOX_16", "GPIOX_17", "GPIOX_18", "GPIOX_19",
+
+ "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4",
+ "GPIOH_5", "GPIOH_6", "GPIOH_7", "GPIOH_8",
+
+ "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4",
+ "GPIOZ_5", "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9",
+ "GPIOZ_10", "GPIOZ_11", "GPIOZ_12", "GPIOZ_13",
+ "GPIOZ_14", "GPIOZ_15",
+
+ "GPIOA_14", "GPIOA_15",
+};
+
+static const char * const uart_a_groups[] = {
+ "uart_a_cts", "uart_a_rts", "uart_a_tx_d2", "uart_a_rx_d3",
+ "uart_a_tx_d8", "uart_a_rx_d9",
+};
+
+static const char * const uart_b_groups[] = {
+ "uart_b_tx_d", "uart_b_rx_d", "uart_b_cts", "uart_b_rts",
+ "uart_b_rx_c", "uart_b_tx_c",
+};
+
+static const char * const uart_c_groups[] = {
+ "uart_c_rts", "uart_c_cts", "uart_c_tx", "uart_c_rx",
+};
+
+static const char * const uart_d_groups[] = {
+ "uart_d_rts", "uart_d_cts", "uart_d_tx_x6", "uart_d_tx_x10",
+ "uart_d_tx_x10", "uart_d_tx_x11",
+};
+
+static const char * const uart_e_groups[] = {
+ "uart_e_tx", "uart_e_rx", "uart_e_ctx", "uart_e_rtx",
+};
+
+static const char * const i2c_a_groups[] = {
+ "i2c_a_scl_c", "i2c_a_sda_c", "i2c_a_scl_h", "i2c_a_sda_h",
+ "i2c_a_scl_z1", "i2c_a_sda_z0", "i2c_a_scl_z8", "i2c_a_sda_z7",
+};
+
+static const char * const i2c_b_groups[] = {
+ "i2c_b_sda_z", "i2c_b_scl_z", "i2c_b_sda_x", "i2c_b_scl_x",
+ "i2c_b_sda_h2", "i2c_b_scl_h3", "i2c_b_sda_h6", "i2c_b_scl_h7",
+};
+
+static const char * const i2c_c_groups[] = {
+ "i2c_c_sda_x", "i2c_c_scl_x", "i2c_c_sda_z10", "i2c_c_scl_z11",
+ "i2c_c_sda_z14", "i2c_c_scl_z15",
+};
+
+static const char * const i2c_d_groups[] = {
+ "i2c_d_sda_h", "i2c_d_scl_h", "i2c_d_sda_a", "i2c_d_scl_a",
+};
+
+static const char * const i2c_e_groups[] = {
+ "i2c_e_sda_d", "i2c_e_scl_d", "i2c_e_sda_e", "i2c_e_scl_e",
+};
+
+static const char * const i2c_slave_groups[] = {
+ "i2c_slave_scl", "i2c_slave_sda",
+};
+
+static const char * const pwm_a_groups[] = {
+ "pwm_a_e", "pwm_a_x",
+};
+
+static const char * const pwm_b_groups[] = {
+ "pwm_b_h", "pwm_b_z0", "pwm_b_z13", "pwm_b_x7",
+ "pwm_b_x19",
+};
+
+static const char * const pwm_c_groups[] = {
+ "pwm_c_c", "pwm_c_x", "pwm_c_z",
+};
+
+static const char * const pwm_d_groups[] = {
+ "pwm_d_z", "pwm_d_x3", "pwm_d_x6",
+};
+
+static const char * const pwm_e_groups[] = {
+ "pwm_e",
+};
+
+static const char * const pwm_f_groups[] = {
+ "pwm_f_x", "pwm_f_h", "pwm_f_z"
+};
+
+static const char * const pwm_g_groups[] = {
+ "pwm_g",
+};
+
+static const char * const pwm_h_groups[] = {
+ "pwm_h",
+};
+
+static const char * const pwm_i_groups[] = {
+ "pwm_i_d4", "pwm_i_d6",
+};
+
+static const char * const pwm_j_groups[] = {
+ "pwm_j_e", "pwm_j_d5", "pwm_j_d10",
+};
+
+static const char * const pwm_i_hiz_groups[] = {
+ "pwm_i_hiz",
+};
+
+static const char * const pwm_g_hiz_groups[] = {
+ "pwm_g_hiz",
+};
+
+static const char * const remote_out_groups[] = {
+ "remote_out_h", "remote_out_z", "remote_out_d4", "remote_out_d9",
+};
+
+static const char * const remote_input_groups[] = {
+ "remote_input_a", "remote_input_d5",
+};
+
+static const char * const jtag_1_groups[] = {
+ "jtag_1_clk", "jtag_1_tms", "jtag_1_tdi", "jtag_1_tdo",
+};
+
+static const char * const jtag_2_groups[] = {
+ "jtag_2_tdo", "jtag_2_tdi", "jtag_2_clk", "jtag_2_tms",
+};
+
+static const char * const gen_clk_groups[] = {
+ "gen_clk_d", "gen_clk_z", "gen_clk_a", "gen_clk_x",
+};
+
+static const char * const clk12_24_groups[] = {
+ "clk12_24_d", "clk12_24_e", "clk12_24_z",
+};
+
+static const char * const clk25_groups[] = {
+ "clk25",
+};
+
+static const char * const clk_32k_in_groups[] = {
+ "clk_32k_in",
+};
+
+static const char * const emmc_groups[] = {
+ "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3",
+ "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7",
+ "emmc_clk", "emmc_cmd", "emmc_nand_dqs",
+};
+
+static const char * const nand_groups[] = {
+ "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3",
+ "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7",
+ "emmc_nand_dqs", "nand_wen_clk", "nand_ale", "nand_ren_wr",
+ "nand_cle", "nand_ce0", "nand_ce1", "nand_rb0",
+};
+
+static const char * const sdcard_groups[] = {
+ "sdcard_d0_c", "sdcard_d1_c", "sdcard_d2_c", "sdcard_d3_c",
+ "sdcaed_cd_c", "sdcard_clk_c", "sdcard_cmd_c",
+
+ "sdcard_d0_x", "sdcard_d1_x", "sdcard_d2_x", "sdcard_d3_x",
+ "sdcard_clk_x", "sdcard_cmd_x",
+
+ "sdcard_d0_z", "sdcard_d1_z", "sdcard_d2_z", "sdcard_d3_z",
+ "sdcard_clk_z", "sdcard_cmd_z",
+};
+
+static const char * const nor_groups[] = {
+ "nor_hold", "nor_d", "nor_q", "nor_c",
+ "nor_wp", "nor_cs",
+};
+
+static const char * const spi_a_groups[] = {
+ "spi_a_mosi_c", "spi_a_miso_c", "spi_a_ss0_c", "spi_a_sclk_c",
+ "spi_a_mosi_x", "spi_a_miso_x", "spi_a_sclk_x", "spi_a_ss0_x",
+};
+
+static const char * const spi_b_groups[] = {
+ "spi_b_mosi_h", "spi_b_miso_h", "spi_b_ss0_h", "spi_b_sclk_h",
+};
+
+static const char * const pdm_groups[] = {
+ "pdm_din0_c", "pdm_din1_c1", "pdm_din2_c", "pdm_din3_c",
+ "pdm_din1_c7", "pdm_dclk_c",
+
+ "pdm_din0_x", "pdm_din1_x", "pdm_din2_x", "pdm_din3_x",
+ "pdm_dclk_x",
+
+ "pdm_din0_z", "pdm_din1_z", "pdm_din2_z", "pdm_din3_z",
+ "pdm_dclk_z",
+
+ "pdm_din0_a", "pdm_dclk_a",
+
+};
+
+static const char * const sdio_groups[] = {
+ "sdio_d0_x", "sdio_d1_x", "sdio_d2_x", "sdio_d3_x",
+ "sdio_clk_x", "sdio_cmd_x",
+};
+
+static const char * const eth_groups[] = {
+ "eth_mdc", "eth_mdio", "eth_rxd0", "eth_rxd1",
+ "eth_txen", "eth_txd0", "eth_txd1", "eth_rx_dv",
+ "eth_act_led", "eth_link_led", "eth_rxd2_rgmii", "eth_rxd3_rgmii",
+ "eth_txd2_rgmii", "eth_txd3_rgmii", "eth_rgmii_rx_clk",
+ "eth_rgmii_tx_clk",
+};
+
+static const char * const mic_mute_groups[] = {
+ "mic_mute_en", "mic_mute_key",
+};
+
+static const char * const mclk_groups[] = {
+ "mclk1", "mclk_0", "mclk_2",
+};
+
+static const char * const tdm_groups[] = {
+ "tdm_d0", "tdm_d1", "tdm_d2", "tdm_d3",
+ "tdm_d4", "tdm_d5", "tdm_d6", "tdm_d7",
+ "tdm_d8", "tdm_d9", "tdm_d10", "tdm_d11",
+ "tdm_d12", "tdm_d13", "tdm_d14", "tdm_d15",
+ "tdm_fs0", "tdm_fs1", "tdm_fs2", "tdm_fs3",
+ "tdm_fs4", "tdm_sclk0", "tdm_sclk1", "tdm_sclk2",
+ "tdm_sclk3", "tdm_sclk4",
+};
+
+static const char * const tsin_a_groups[] = {
+ "tsin_a_sop_d", "tsin_a_clk_d", "tsin_a_clk_x", "tsin_sop_x",
+ "tsin_din0_d", "tsin_a_din0_x", "tsin_a_valid_d", "tsin_a_valid_x",
+};
+
+static const char * const tsin_b_groups[] = {
+ "tsin_b_sop", "tsin_b_clk", "tsin_b_din0", "tsin_fail",
+ "tsin_b_din1", "tsin_b_din2", "tsin_b_din3", "tsin_b_din4",
+ "tsin_b_din5", "tsin_b_din6", "tsin_b_din7", "tsin_b_valid",
+};
+
+static const char * const tsin_c_groups[] = {
+ "tsin_c_sop_c", "tsin_c_clk_c", "tsin_c_sop_z", "tsin_c_clk_z",
+ "tsin_c_din0_c", "tsin_din0_z", "tsin_c_valid_c", "tsin_c_valid_z",
+};
+
+static const char * const tsin_d_groups[] = {
+ "tsin_d_sop_x", "tsin_d_clk_x", "tsin_d_sop_z", "tsin_d_clk_z",
+ "tsin_d_din0_x", "tsin_d_din0_z", "tsin_d_valid_x", "tsin_d_valid_z",
+};
+
+static const char * const cec_a_groups[] = {
+ "cec_a_h", "cec_a_d",
+};
+
+static const char * const cec_b_groups[] = {
+ "cec_b_h", "cec_b_d",
+};
+
+static const char * const spdif_in_groups[] = {
+ "spdif_in_h",
+};
+
+static const char * const spdif_out_groups[] = {
+ "spdif_out_d", "spdif_out_h",
+};
+
+static const char * const pcieck_reqn_groups[] = {
+ "pcieck_reqn",
+};
+
+static const char * const iso7816_groups[] = {
+ "iso7816_clk_c", "iso7816_clk_h", "iso7816_data_c", "iso7816_clk_x",
+ "iso7816_data_x", "iso7816_data_h", "iso7816_clk_z0",
+ "iso7816_clk_z8", "iso7816_data_z1", "is7816_data_z9",
+};
+
+static const char * const hdmitx_groups[] = {
+ "hdmitx_sda", "hdmitx_scl", "hdmitx_hpd_in",
+};
+
+static struct meson_pmx_func meson_sc2_periphs_functions[] = {
+ FUNCTION(gpio_periphs),
+ FUNCTION(uart_a),
+ FUNCTION(uart_b),
+ FUNCTION(uart_c),
+ FUNCTION(uart_d),
+ FUNCTION(uart_e),
+ FUNCTION(i2c_a),
+ FUNCTION(i2c_b),
+ FUNCTION(i2c_c),
+ FUNCTION(i2c_d),
+ FUNCTION(i2c_e),
+ FUNCTION(i2c_slave),
+ FUNCTION(pwm_a),
+ FUNCTION(pwm_b),
+ FUNCTION(pwm_c),
+ FUNCTION(pwm_d),
+ FUNCTION(pwm_e),
+ FUNCTION(pwm_f),
+ FUNCTION(pwm_g),
+ FUNCTION(pwm_h),
+ FUNCTION(pwm_i),
+ FUNCTION(pwm_j),
+ FUNCTION(pwm_i_hiz),
+ FUNCTION(pwm_g_hiz),
+ FUNCTION(remote_out),
+ FUNCTION(remote_input),
+ FUNCTION(jtag_1),
+ FUNCTION(jtag_2),
+ FUNCTION(gen_clk),
+ FUNCTION(clk12_24),
+ FUNCTION(clk25),
+ FUNCTION(clk_32k_in),
+ FUNCTION(emmc),
+ FUNCTION(nand),
+ FUNCTION(nor),
+ FUNCTION(sdcard),
+ FUNCTION(spi_a),
+ FUNCTION(spi_b),
+ FUNCTION(pdm),
+ FUNCTION(sdio),
+ FUNCTION(eth),
+ FUNCTION(mic_mute),
+ FUNCTION(mclk),
+ FUNCTION(tdm),
+ FUNCTION(tsin_a),
+ FUNCTION(tsin_b),
+ FUNCTION(tsin_c),
+ FUNCTION(tsin_d),
+ FUNCTION(cec_a),
+ FUNCTION(cec_b),
+ FUNCTION(spdif_in),
+ FUNCTION(spdif_out),
+ FUNCTION(pcieck_reqn),
+ FUNCTION(iso7816),
+ FUNCTION(hdmitx),
+};
+
+static struct meson_bank meson_sc2_periphs_banks[] = {
+ /* name first last pullen pull dir out in */
+ BANK("GPIOZ_", GPIOZ_0, GPIOZ_15,
+ 0x3, 0, 0x4, 0, 0x2, 0, 0x1, 0, 0x0, 0),
+ BANK("GPIOX_", GPIOX_0, GPIOX_19,
+ 0x13, 0, 0x14, 0, 0x12, 0, 0x11, 0, 0x10, 0),
+ BANK("GPIOH_", GPIOH_0, GPIOH_8,
+ 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0),
+ BANK("GPIOD_", GPIOD_0, GPIOD_11,
+ 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0),
+ BANK("GPIOE_", GPIOE_0, GPIOE_2,
+ 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0),
+ BANK("GPIOC_", GPIOC_0, GPIOC_7,
+ 0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0),
+ BANK("GPIOB_", GPIOB_0, GPIOB_15,
+ 0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0),
+ BANK("GPIOA_", GPIOA_14, GPIOA_15,
+ 0x73, 14, 0x74, 14, 0x72, 14, 0x71, 14, 0x70, 14),
+ BANK("GPIO_TEST_N", GPIO_TEST_N, GPIO_TEST_N,
+ 0x83, 0, 0x84, 0, 0x82, 0, 0x81, 0, 0x80, 0),
+};
+
+static struct meson_pmx_bank meson_sc2_periphs_pmx_banks[] = {
+ /*name first lask reg offset*/
+ BANK_PMX("Z", GPIOZ_0, GPIOZ_15, 0x6, 0),
+ BANK_PMX("X", GPIOX_0, GPIOX_19, 0x3, 0),
+ BANK_PMX("H", GPIOH_0, GPIOH_8, 0xb, 0),
+ BANK_PMX("D", GPIOD_0, GPIOD_11, 0x10, 0),
+ BANK_PMX("E", GPIOE_0, GPIOE_2, 0x12, 0),
+ BANK_PMX("C", GPIOC_0, GPIOC_7, 0x9, 0),
+ BANK_PMX("B", GPIOB_0, GPIOB_15, 0x0, 0),
+ BANK_PMX("A", GPIOA_14, GPIOA_15, 0xe, 24),
+ BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0xf, 0),
+};
+
+static struct meson_drive_bank meson_sc2_periphs_drive_banks[] = {
+ /* name first lask reg offset*/
+ BANK_DRIVE("Z", GPIOZ_0, GPIOZ_15, 0x7, 0),
+ BANK_DRIVE("X", GPIOX_0, GPIOX_19, 0x17, 0),
+ BANK_DRIVE("H", GPIOH_0, GPIOH_8, 0x27, 0),
+ BANK_DRIVE("D", GPIOD_0, GPIOD_11, 0x37, 0),
+ BANK_DRIVE("E", GPIOE_0, GPIOE_2, 0x47, 0),
+ BANK_DRIVE("C", GPIOC_0, GPIOC_7, 0x57, 0),
+ BANK_DRIVE("B", GPIOB_0, GPIOB_15, 0x67, 0),
+ BANK_DRIVE("A", GPIOA_14, GPIOA_15, 0x77, 28),
+ BANK_DRIVE("TESTN", GPIO_TEST_N, GPIO_TEST_N, 0x87, 0),
+};
+
+static struct meson_axg_pmx_data meson_sc2_periphs_pmx_banks_data = {
+ .pmx_banks = meson_sc2_periphs_pmx_banks,
+ .num_pmx_banks = ARRAY_SIZE(meson_sc2_periphs_pmx_banks),
+};
+
+static struct meson_drive_data meson_sc2_periphs_drive_data = {
+ .drive_banks = meson_sc2_periphs_drive_banks,
+ .num_drive_banks = ARRAY_SIZE(meson_sc2_periphs_drive_banks),
+};
+
+static struct meson_pinctrl_data meson_sc2_periphs_pinctrl_data = {
+ .name = "periphs-banks",
+ .groups = meson_sc2_periphs_groups,
+ .funcs = meson_sc2_periphs_functions,
+ .banks = meson_sc2_periphs_banks,
+ .num_pins = 87,
+ .num_groups = ARRAY_SIZE(meson_sc2_periphs_groups),
+ .num_funcs = ARRAY_SIZE(meson_sc2_periphs_functions),
+ .num_banks = ARRAY_SIZE(meson_sc2_periphs_banks),
+ .pmx_data = &meson_sc2_periphs_pmx_banks_data,
+ .drv_data = &meson_sc2_periphs_drive_data,
+};
+
+static const struct udevice_id meson_sc2_pinctrl_match[] = {
+ {
+ .compatible = "amlogic,meson-sc2-periphs-pinctrl",
+ .data = (ulong)&meson_sc2_periphs_pinctrl_data,
+ },
+ { },
+};
+
+U_BOOT_DRIVER(meson_sc2_pinctrl) = {
+ .name = "meson-sc2-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(meson_sc2_pinctrl_match),
+ .probe = meson_pinctrl_probe,
+ .priv_auto_alloc_size = sizeof(struct meson_pinctrl),
+ .ops = &meson_axg_pinctrl_ops,
+};
diff --git a/drivers/pinctrl/meson/pinctrl-meson-t7.c b/drivers/pinctrl/meson/pinctrl-meson-t7.c
new file mode 100644
index 0000000..1c3437f
--- /dev/null
+++ b/drivers/pinctrl/meson/pinctrl-meson-t7.c
@@ -0,0 +1,1459 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <dm/pinctrl.h>
+#include <dt-bindings/gpio/meson-t7-gpio.h>
+
+#include "pinctrl-meson.h"
+#include "pinctrl-meson-axg-pmx.h"
+
+/* Bank B func1 */
+static const unsigned int emmc_nand_d0_pins[] = { GPIOB_0 };
+static const unsigned int emmc_nand_d1_pins[] = { GPIOB_1 };
+static const unsigned int emmc_nand_d2_pins[] = { GPIOB_2 };
+static const unsigned int emmc_nand_d3_pins[] = { GPIOB_3 };
+static const unsigned int emmc_nand_d4_pins[] = { GPIOB_4 };
+static const unsigned int emmc_nand_d5_pins[] = { GPIOB_5 };
+static const unsigned int emmc_nand_d6_pins[] = { GPIOB_6 };
+static const unsigned int emmc_nand_d7_pins[] = { GPIOB_7 };
+static const unsigned int emmc_clk_pins[] = { GPIOB_8 };
+static const unsigned int emmc_cmd_pins[] = { GPIOB_10 };
+static const unsigned int emmc_nand_ds_pins[] = { GPIOB_11 };
+
+/* Bank B func2 */
+static const unsigned int nor_hold_pins[] = { GPIOB_3 };
+static const unsigned int nor_d_pins[] = { GPIOB_4 };
+static const unsigned int nor_q_pins[] = { GPIOB_5 };
+static const unsigned int nor_c_pins[] = { GPIOB_6 };
+static const unsigned int nor_wp_pins[] = { GPIOB_7 };
+static const unsigned int nor_cs_pins[] = { GPIOB_12 };
+
+/* Bank C func1 */
+static const unsigned int sdcard_d0_pins[] = { GPIOC_0 };
+static const unsigned int sdcard_d1_pins[] = { GPIOC_1 };
+static const unsigned int sdcard_d2_pins[] = { GPIOC_2 };
+static const unsigned int sdcard_d3_pins[] = { GPIOC_3 };
+static const unsigned int sdcard_clk_pins[] = { GPIOC_4 };
+static const unsigned int sdcard_cmd_pins[] = { GPIOC_5 };
+static const unsigned int gen_clk_out_c_pins[] = { GPIOC_6 };
+
+/* Bank C func2 */
+static const unsigned int jtag_b_tdo_pins[] = { GPIOC_0 };
+static const unsigned int jtag_b_tdi_pins[] = { GPIOC_1 };
+static const unsigned int uart_ao_a_rx_c_pins[] = { GPIOC_2 };
+static const unsigned int uart_ao_a_tx_c_pins[] = { GPIOC_3 };
+static const unsigned int jtag_b_clk_pins[] = { GPIOC_4 };
+static const unsigned int jtag_b_tms_pins[] = { GPIOC_5 };
+
+/* Bank C func3 */
+static const unsigned int spi1_mosi_c_pins[] = { GPIOC_0 };
+static const unsigned int spi1_miso_c_pins[] = { GPIOC_1 };
+static const unsigned int spi1_sclk_c_pins[] = { GPIOC_2 };
+static const unsigned int spi1_ss0_c_pins[] = { GPIOC_3 };
+
+/* Bank X func1 */
+static const unsigned int sdio_d0_pins[] = { GPIOX_0 };
+static const unsigned int sdio_d1_pins[] = { GPIOX_1 };
+static const unsigned int sdio_d2_pins[] = { GPIOX_2 };
+static const unsigned int sdio_d3_pins[] = { GPIOX_3 };
+static const unsigned int sdio_clk_pins[] = { GPIOX_4 };
+static const unsigned int sdio_cmd_pins[] = { GPIOX_5 };
+static const unsigned int pwm_b_pins[] = { GPIOX_6 };
+static const unsigned int pwm_c_pins[] = { GPIOX_7 };
+static const unsigned int tdm_d0_pins[] = { GPIOX_8 };
+static const unsigned int tdm_d1_pins[] = { GPIOX_9 };
+static const unsigned int tdm_fs0_pins[] = { GPIOX_10 };
+static const unsigned int tdm_sclk0_pins[] = { GPIOX_11 };
+static const unsigned int uart_c_tx_pins[] = { GPIOX_12 };
+static const unsigned int uart_c_rx_pins[] = { GPIOX_13 };
+static const unsigned int uart_c_cts_pins[] = { GPIOX_14 };
+static const unsigned int uart_c_rts_pins[] = { GPIOX_15 };
+static const unsigned int pwm_a_pins[] = { GPIOX_16 };
+static const unsigned int i2c2_sda_x_pins[] = { GPIOX_17 };
+static const unsigned int i2c2_sck_x_pins[] = { GPIOX_18 };
+static const unsigned int pwm_d_pins[] = { GPIOX_19 };
+
+/* Bank X func2 */
+static const unsigned int clk12_24_x_pins[] = { GPIOX_14 };
+
+/* Bank W func1 */
+static const unsigned int hdmirx_a_hpd_pins[] = { GPIOW_0 };
+static const unsigned int hdmirx_a_det_pins[] = { GPIOW_1 };
+static const unsigned int hdmirx_a_sda_pins[] = { GPIOW_2 };
+static const unsigned int hdmirx_a_sck_pins[] = { GPIOW_3 };
+static const unsigned int hdmirx_c_hpd_pins[] = { GPIOW_4 };
+static const unsigned int hdmirx_c_det_pins[] = { GPIOW_5 };
+static const unsigned int hdmirx_c_sda_pins[] = { GPIOW_6 };
+static const unsigned int hdmirx_c_sck_pins[] = { GPIOW_7 };
+static const unsigned int hdmirx_b_hpd_pins[] = { GPIOW_8 };
+static const unsigned int hdmirx_b_det_pins[] = { GPIOW_9 };
+static const unsigned int hdmirx_b_sda_pins[] = { GPIOW_10 };
+static const unsigned int hdmirx_b_sck_pins[] = { GPIOW_11 };
+static const unsigned int cec_a_pins[] = { GPIOW_12 };
+static const unsigned int hdmitx_sda_w13_pins[] = { GPIOW_13 };
+static const unsigned int hdmitx_scl_w14_pins[] = { GPIOW_14 };
+static const unsigned int hdmitx_hpd_in_pins[] = { GPIOW_15 };
+static const unsigned int cec_b_pins[] = { GPIOW_16 };
+
+/* Bank W func2 */
+static const unsigned int uart_ao_a_tx_w2_pins[] = { GPIOW_2 };
+static const unsigned int uart_ao_a_rx_w3_pins[] = { GPIOW_3 };
+static const unsigned int uart_ao_a_tx_w6_pins[] = { GPIOW_6 };
+static const unsigned int uart_ao_a_rx_w7_pins[] = { GPIOW_7 };
+static const unsigned int uart_ao_a_tx_w10_pins[] = { GPIOW_10 };
+static const unsigned int uart_ao_a_rx_w11_pins[] = { GPIOW_11 };
+
+/* Bank W func3 */
+static const unsigned int hdmitx_sda_w2_pins[] = { GPIOW_2 };
+static const unsigned int hdmitx_scl_w3_pins[] = { GPIOW_3 };
+
+/* Bank D func1 */
+static const unsigned int uart_ao_a_tx_d0_pins[] = { GPIOD_0 };
+static const unsigned int uart_ao_a_rx_d1_pins[] = { GPIOD_1 };
+static const unsigned int i2c0_ao_sck_d_pins[] = { GPIOD_2 };
+static const unsigned int i2c0_ao_sda_d_pins[] = { GPIOD_3 };
+static const unsigned int remote_out_d4_pins[] = { GPIOD_4 };
+static const unsigned int remote_in_pins[] = { GPIOD_5 };
+static const unsigned int jtag_a_clk_pins[] = { GPIOD_6 };
+static const unsigned int jtag_a_tms_pins[] = { GPIOD_7 };
+static const unsigned int jtag_a_tdi_pins[] = { GPIOD_8 };
+static const unsigned int jtag_a_tdo_pins[] = { GPIOD_9 };
+static const unsigned int gen_clk_out_d_pins[] = { GPIOD_10 };
+static const unsigned int pwm_ao_g_d11_pins[] = { GPIOD_11 };
+static const unsigned int wd_rsto_pins[] = { GPIOD_12 };
+
+/* Bank D func2 */
+static const unsigned int i2c0_slave_ao_sck_pins[] = { GPIOD_2 };
+static const unsigned int i2c0_slave_ao_sda_pins[] = { GPIOD_3 };
+static const unsigned int rtc_clk_in_pins[] = { GPIOD_4 };
+static const unsigned int pwm_ao_h_d5_pins[] = { GPIOD_5 };
+static const unsigned int pwm_ao_c_d_pins[] = { GPIOD_6 };
+static const unsigned int pwm_ao_g_d7_pins[] = { GPIOD_7 };
+static const unsigned int spdif_out_d_pins[] = { GPIOD_8 };
+static const unsigned int spdif_in_d_pins[] = { GPIOD_9 };
+static const unsigned int pwm_ao_h_d10_pins[] = { GPIOD_10 };
+
+/* Bank D func3 */
+static const unsigned int uart_ao_b_tx_pins[] = { GPIOD_2 };
+static const unsigned int uart_ao_b_rx_pins[] = { GPIOD_3 };
+static const unsigned int uart_ao_b_cts_pins[] = { GPIOD_4 };
+static const unsigned int pwm_ao_c_hiz_pins[] = { GPIOD_6 };
+static const unsigned int pwm_ao_g_hiz_pins[] = { GPIOD_7 };
+static const unsigned int uart_ao_b_rts_pins[] = { GPIOD_10 };
+
+/* Bank D func4 */
+static const unsigned int remote_out_d6_pins[] = { GPIOD_6 };
+
+/* Bank E func1 */
+static const unsigned int pwm_ao_a_pins[] = { GPIOE_0 };
+static const unsigned int pwm_ao_b_pins[] = { GPIOE_1 };
+static const unsigned int pwm_ao_c_e_pins[] = { GPIOE_2 };
+static const unsigned int pwm_ao_d_pins[] = { GPIOE_3 };
+static const unsigned int pwm_ao_e_pins[] = { GPIOE_4 };
+static const unsigned int pwm_ao_f_pins[] = { GPIOE_5 };
+static const unsigned int pwm_ao_g_e_pins[] = { GPIOE_6 };
+
+/* Bank E func2 */
+static const unsigned int i2c0_ao_sck_e_pins[] = { GPIOE_0 };
+static const unsigned int i2c0_ao_sda_e_pins[] = { GPIOE_1 };
+static const unsigned int clk25m_pins[] = { GPIOE_2 };
+static const unsigned int i2c1_ao_sck_pins[] = { GPIOE_3 };
+static const unsigned int i2c1_ao_sda_pins[] = { GPIOE_4 };
+static const unsigned int rtc_clk_out_pins[] = { GPIOD_5 };
+
+/* Bank E func3 */
+static const unsigned int clk12_24_e_pins[] = { GPIOE_4 };
+
+/* Bank Z func1 */
+static const unsigned int eth_mdio_pins[] = { GPIOZ_0 };
+static const unsigned int eth_mdc_pins[] = { GPIOZ_1 };
+static const unsigned int eth_rgmii_rx_clk_pins[] = { GPIOZ_2 };
+static const unsigned int eth_rx_dv_pins[] = { GPIOZ_3 };
+static const unsigned int eth_rxd0_pins[] = { GPIOZ_4 };
+static const unsigned int eth_rxd1_pins[] = { GPIOZ_5 };
+static const unsigned int eth_rxd2_rgmii_pins[] = { GPIOZ_6 };
+static const unsigned int eth_rxd3_rgmii_pins[] = { GPIOZ_7 };
+static const unsigned int eth_rgmii_tx_clk_pins[] = { GPIOZ_8 };
+static const unsigned int eth_txen_pins[] = { GPIOZ_9 };
+static const unsigned int eth_txd0_pins[] = { GPIOZ_10 };
+static const unsigned int eth_txd1_pins[] = { GPIOZ_11 };
+static const unsigned int eth_txd2_rgmii_pins[] = { GPIOZ_12 };
+static const unsigned int eth_txd3_rgmii_pins[] = { GPIOZ_13 };
+
+/* Bank Z func2 */
+static const unsigned int iso7816_clk_z_pins[] = { GPIOZ_0 };
+static const unsigned int iso7816_data_z_pins[] = { GPIOZ_1 };
+static const unsigned int tsin_b_valid_pins[] = { GPIOZ_2 };
+static const unsigned int tsin_b_sop_pins[] = { GPIOZ_3 };
+static const unsigned int tsin_b_din0_pins[] = { GPIOZ_4 };
+static const unsigned int tsin_b_clk_pins[] = { GPIOZ_5 };
+static const unsigned int tsin_b_fail_pins[] = { GPIOZ_6 };
+static const unsigned int tsin_b_din1_pins[] = { GPIOZ_7 };
+static const unsigned int tsin_b_din2_pins[] = { GPIOZ_8 };
+static const unsigned int tsin_b_din3_pins[] = { GPIOZ_9 };
+static const unsigned int tsin_b_din4_pins[] = { GPIOZ_10 };
+static const unsigned int tsin_b_din5_pins[] = { GPIOZ_11 };
+static const unsigned int tsin_b_din6_pins[] = { GPIOZ_12 };
+static const unsigned int tsin_b_din7_pins[] = { GPIOZ_13 };
+
+/* Bank Z func3 */
+static const unsigned int tsin_c_z_valid_pins[] = { GPIOZ_6 };
+static const unsigned int tsin_c_z_sop_pins[] = { GPIOZ_7 };
+static const unsigned int tsin_c_z_din0_pins[] = { GPIOZ_8 };
+static const unsigned int tsin_c_z_clk_pins[] = { GPIOZ_9 };
+static const unsigned int tsin_d_z_valid_pins[] = { GPIOZ_10 };
+static const unsigned int tsin_d_z_sop_pins[] = { GPIOZ_11 };
+static const unsigned int tsin_d_z_din0_pins[] = { GPIOZ_12 };
+static const unsigned int tsin_d_z_clk_pins[] = { GPIOZ_13 };
+
+/* Bank Z func4 */
+static const unsigned int spi4_mosi_pins[] = { GPIOZ_0 };
+static const unsigned int spi4_miso_pins[] = { GPIOZ_1 };
+static const unsigned int spi4_sclk_pins[] = { GPIOZ_2 };
+static const unsigned int spi4_ss0_pins[] = { GPIOZ_3 };
+static const unsigned int spi5_mosi_pins[] = { GPIOZ_4 };
+static const unsigned int spi5_miso_pins[] = { GPIOZ_5 };
+static const unsigned int spi5_sclk_pins[] = { GPIOZ_6 };
+static const unsigned int spi5_ss0_pins[] = { GPIOZ_7 };
+
+/* Bank T func1 */
+static const unsigned int mclk1_pins[] = { GPIOT_0 };
+static const unsigned int tdm_sclk1_pins[] = { GPIOT_1 };
+static const unsigned int tdm_fs1_pins[] = { GPIOT_2 };
+static const unsigned int tdm_d2_pins[] = { GPIOT_3 };
+static const unsigned int tdm_d3_pins[] = { GPIOT_4 };
+static const unsigned int tdm_d4_pins[] = { GPIOT_5 };
+static const unsigned int tdm_d5_pins[] = { GPIOT_6 };
+static const unsigned int tdm_d6_pins[] = { GPIOT_7 };
+static const unsigned int tdm_d7_pins[] = { GPIOT_8 };
+static const unsigned int tdm_d8_pins[] = { GPIOT_9 };
+static const unsigned int tdm_d9_pins[] = { GPIOT_10 };
+static const unsigned int tdm_d10_pins[] = { GPIOT_11 };
+static const unsigned int tdm_d11_pins[] = { GPIOT_12 };
+static const unsigned int mclk2_pins[] = { GPIOT_13 };
+static const unsigned int tdm_sclk2_pins[] = { GPIOT_14 };
+static const unsigned int tdm_fs2_pins[] = { GPIOT_15 };
+static const unsigned int i2c1_sck_pins[] = { GPIOT_16 };
+static const unsigned int i2c1_sda_pins[] = { GPIOT_17 };
+static const unsigned int spi0_mosi_pins[] = { GPIOT_18 };
+static const unsigned int spi0_miso_pins[] = { GPIOT_19 };
+static const unsigned int spi0_sclk_pins[] = { GPIOT_20 };
+static const unsigned int spi0_ss0_pins[] = { GPIOT_21 };
+static const unsigned int spi0_ss1_pins[] = { GPIOT_22 };
+static const unsigned int spi0_ss2_pins[] = { GPIOT_23 };
+
+/* Bank T func2 */
+static const unsigned int spdif_in_t_pins[] = { GPIOT_3 };
+static const unsigned int spdif_out_t_pins[] = { GPIOT_4 };
+static const unsigned int iso7816_clk_t_pins[] = { GPIOT_5 };
+static const unsigned int iso7816_data_t_pins[] = { GPIOT_6 };
+static const unsigned int tsin_a_sop_t_pins[] = { GPIOT_7 };
+static const unsigned int tsin_a_din0_t_pins[] = { GPIOT_8 };
+static const unsigned int tsin_a_clk_t_pins[] = { GPIOT_9 };
+static const unsigned int tsin_a_valid_t_pins[] = { GPIOT_10 };
+static const unsigned int i2c0_sck_t_pins[] = { GPIOT_20 };
+static const unsigned int i2c0_sda_t_pins[] = { GPIOT_21 };
+static const unsigned int i2c2_sck_t_pins[] = { GPIOT_22 };
+static const unsigned int i2c2_sda_t_pins[] = { GPIOT_23 };
+
+/* Bank T func3 */
+static const unsigned int spi3_mosi_pins[] = { GPIOT_6 };
+static const unsigned int spi3_miso_pins[] = { GPIOT_7 };
+static const unsigned int spi3_sclk_pins[] = { GPIOT_8 };
+static const unsigned int spi3_ss0_pins[] = { GPIOT_9 };
+
+/* Bank M func1 */
+static const unsigned int tdm_d12_pins[] = { GPIOM_0 };
+static const unsigned int tdm_d13_pins[] = { GPIOM_1 };
+static const unsigned int tdm_d14_pins[] = { GPIOM_2 };
+static const unsigned int tdm_d15_pins[] = { GPIOM_3 };
+static const unsigned int tdm_sclk3_pins[] = { GPIOM_4 };
+static const unsigned int tdm_fs3_pins[] = { GPIOM_5 };
+static const unsigned int i2c3_sda_m_pins[] = { GPIOM_6 };
+static const unsigned int i2c3_sck_m_pins[] = { GPIOM_7 };
+static const unsigned int spi1_mosi_m_pins[] = { GPIOM_8 };
+static const unsigned int spi1_miso_m_pins[] = { GPIOM_9 };
+static const unsigned int spi1_sclk_m_pins[] = { GPIOM_10 };
+static const unsigned int spi1_ss0_m_pins[] = { GPIOM_11 };
+static const unsigned int spi1_ss1_m_pins[] = { GPIOM_12 };
+static const unsigned int spi1_ss2_m_pins[] = { GPIOM_13 };
+
+/* Bank M func2 */
+static const unsigned int pdm_din1_m0_pins[] = { GPIOM_0 };
+static const unsigned int pdm_din2_pins[] = { GPIOM_1 };
+static const unsigned int pdm_din3_pins[] = { GPIOM_2 };
+static const unsigned int pdm_dclk_pins[] = { GPIOM_3 };
+static const unsigned int pdm_din0_pins[] = { GPIOM_4 };
+static const unsigned int pdm_din1_m5_pins[] = { GPIOM_5 };
+static const unsigned int uart_d_tx_m_pins[] = { GPIOM_8 };
+static const unsigned int uart_d_rx_m_pins[] = { GPIOM_9 };
+static const unsigned int uart_d_cts_m_pins[] = { GPIOM_10 };
+static const unsigned int uart_d_rts_m_pins[] = { GPIOM_11 };
+static const unsigned int i2c2_sda_m_pins[] = { GPIOM_12 };
+static const unsigned int i2c2_sck_m_pins[] = { GPIOM_13 };
+
+/* Bank Y func1 */
+static const unsigned int spi2_mosi_pins[] = { GPIOY_0 };
+static const unsigned int spi2_miso_pins[] = { GPIOY_1 };
+static const unsigned int spi2_sclk_pins[] = { GPIOY_2 };
+static const unsigned int spi2_ss0_pins[] = { GPIOY_3 };
+static const unsigned int spi2_ss1_pins[] = { GPIOY_4 };
+static const unsigned int spi2_ss2_pins[] = { GPIOY_5 };
+static const unsigned int uart_e_tx_pins[] = { GPIOY_6 };
+static const unsigned int uart_e_rx_pins[] = { GPIOY_7 };
+static const unsigned int uart_e_cts_pins[] = { GPIOY_8 };
+static const unsigned int uart_e_rts_pins[] = { GPIOY_9 };
+static const unsigned int uart_d_cts_y_pins[] = { GPIOY_10 };
+static const unsigned int uart_d_rts_y_pins[] = { GPIOY_11 };
+static const unsigned int uart_d_tx_y_pins[] = { GPIOY_12 };
+static const unsigned int uart_d_rx_y_pins[] = { GPIOY_13 };
+static const unsigned int i2c4_sck_y_pins[] = { GPIOY_15 };
+static const unsigned int i2c4_sda_y_pins[] = { GPIOY_16 };
+static const unsigned int i2c5_sck_pins[] = { GPIOY_17 };
+static const unsigned int i2c5_sda_pins[] = { GPIOY_18 };
+
+/* Bank Y func2 */
+static const unsigned int tsin_c_y_sop_pins[] = { GPIOY_4 };
+static const unsigned int tsin_c_y_din0_pins[] = { GPIOY_5 };
+static const unsigned int tsin_c_y_clk_pins[] = { GPIOY_6 };
+static const unsigned int tsin_c_y_valid_pins[] = { GPIOY_7 };
+static const unsigned int tsin_d_y_sop_pins[] = { GPIOY_8 };
+static const unsigned int tsin_d_y_din0_pins[] = { GPIOY_9 };
+static const unsigned int tsin_d_y_clk_pins[] = { GPIOY_10 };
+static const unsigned int tsin_d_y_valid_pins[] = { GPIOY_11 };
+static const unsigned int pcieck_reqn_y_pins[] = { GPIOY_18 };
+
+/* Bank Y func3 */
+static const unsigned int pwm_e_pins[] = { GPIOY_1 };
+static const unsigned int hsync_pins[] = { GPIOY_4 };
+static const unsigned int vsync_pins[] = { GPIOY_5 };
+static const unsigned int pwm_f_pins[] = { GPIOY_8 };
+static const unsigned int sync_3d_out_pins[] = { GPIOY_9 };
+static const unsigned int vx1_a_htpdn_pins[] = { GPIOY_10 };
+static const unsigned int vx1_b_htpdn_pins[] = { GPIOY_11 };
+static const unsigned int vx1_a_lockn_pins[] = { GPIOY_12 };
+static const unsigned int vx1_b_lockn_pins[] = { GPIOY_13 };
+static const unsigned int pwm_vs_y_pins[] = { GPIOY_14 };
+
+/* Bank Y func4 */
+static const unsigned int edp_a_hpd_pins[] = { GPIOY_10 };
+static const unsigned int edp_b_hpd_pins[] = { GPIOY_11 };
+
+/* Bank H func1 */
+static const unsigned int mic_mute_key_pins[] = { GPIOH_0 };
+static const unsigned int mic_mute_led_pins[] = { GPIOH_1 };
+static const unsigned int i2c3_sck_h_pins[] = { GPIOH_2 };
+static const unsigned int i2c3_sda_h_pins[] = { GPIOH_3 };
+static const unsigned int i2c4_sck_h_pins[] = { GPIOH_4 };
+static const unsigned int i2c4_sda_h_pins[] = { GPIOH_5 };
+static const unsigned int eth_link_led_pins[] = { GPIOH_6 };
+static const unsigned int eth_act_led_pins[] = { GPIOH_7 };
+
+/* Bank H func2 */
+static const unsigned int pwm_vs_h_pins[] = { GPIOH_1 };
+static const unsigned int uart_f_tx_pins[] = { GPIOH_2 };
+static const unsigned int uart_f_rx_pins[] = { GPIOH_3 };
+static const unsigned int uart_f_cts_pins[] = { GPIOH_4 };
+static const unsigned int uart_f_rts_pins[] = { GPIOH_5 };
+static const unsigned int i2c0_sda_h_pins[] = { GPIOH_6 };
+static const unsigned int i2c0_sck_h_pins[] = { GPIOH_7 };
+
+/* Bank H func3 */
+static const unsigned int pcieck_reqn_h_pins[] = { GPIOH_2 };
+
+static struct meson_pmx_group meson_t7_periphs_groups[] = {
+ GPIO_GROUP(GPIOB_0),
+ GPIO_GROUP(GPIOB_1),
+ GPIO_GROUP(GPIOB_2),
+ GPIO_GROUP(GPIOB_3),
+ GPIO_GROUP(GPIOB_4),
+ GPIO_GROUP(GPIOB_5),
+ GPIO_GROUP(GPIOB_6),
+ GPIO_GROUP(GPIOB_7),
+ GPIO_GROUP(GPIOB_8),
+ GPIO_GROUP(GPIOB_9),
+ GPIO_GROUP(GPIOB_10),
+ GPIO_GROUP(GPIOB_11),
+ GPIO_GROUP(GPIOB_12),
+
+ GPIO_GROUP(GPIOC_0),
+ GPIO_GROUP(GPIOC_1),
+ GPIO_GROUP(GPIOC_2),
+ GPIO_GROUP(GPIOC_3),
+ GPIO_GROUP(GPIOC_4),
+ GPIO_GROUP(GPIOC_5),
+ GPIO_GROUP(GPIOC_6),
+
+ GPIO_GROUP(GPIOX_0),
+ GPIO_GROUP(GPIOX_1),
+ GPIO_GROUP(GPIOX_2),
+ GPIO_GROUP(GPIOX_3),
+ GPIO_GROUP(GPIOX_4),
+ GPIO_GROUP(GPIOX_5),
+ GPIO_GROUP(GPIOX_6),
+ GPIO_GROUP(GPIOX_7),
+ GPIO_GROUP(GPIOX_8),
+ GPIO_GROUP(GPIOX_9),
+ GPIO_GROUP(GPIOX_10),
+ GPIO_GROUP(GPIOX_11),
+ GPIO_GROUP(GPIOX_12),
+ GPIO_GROUP(GPIOX_13),
+ GPIO_GROUP(GPIOX_14),
+ GPIO_GROUP(GPIOX_15),
+ GPIO_GROUP(GPIOX_16),
+ GPIO_GROUP(GPIOX_17),
+ GPIO_GROUP(GPIOX_18),
+ GPIO_GROUP(GPIOX_19),
+
+ GPIO_GROUP(GPIOW_0),
+ GPIO_GROUP(GPIOW_1),
+ GPIO_GROUP(GPIOW_2),
+ GPIO_GROUP(GPIOW_3),
+ GPIO_GROUP(GPIOW_4),
+ GPIO_GROUP(GPIOW_5),
+ GPIO_GROUP(GPIOW_6),
+ GPIO_GROUP(GPIOW_7),
+ GPIO_GROUP(GPIOW_8),
+ GPIO_GROUP(GPIOW_9),
+ GPIO_GROUP(GPIOW_10),
+ GPIO_GROUP(GPIOW_11),
+ GPIO_GROUP(GPIOW_12),
+ GPIO_GROUP(GPIOW_13),
+ GPIO_GROUP(GPIOW_14),
+ GPIO_GROUP(GPIOW_15),
+ GPIO_GROUP(GPIOW_16),
+
+ GPIO_GROUP(GPIOD_0),
+ GPIO_GROUP(GPIOD_1),
+ GPIO_GROUP(GPIOD_2),
+ GPIO_GROUP(GPIOD_3),
+ GPIO_GROUP(GPIOD_4),
+ GPIO_GROUP(GPIOD_5),
+ GPIO_GROUP(GPIOD_6),
+ GPIO_GROUP(GPIOD_7),
+ GPIO_GROUP(GPIOD_8),
+ GPIO_GROUP(GPIOD_9),
+ GPIO_GROUP(GPIOD_10),
+ GPIO_GROUP(GPIOD_11),
+ GPIO_GROUP(GPIOD_12),
+
+ GPIO_GROUP(GPIOE_0),
+ GPIO_GROUP(GPIOE_1),
+ GPIO_GROUP(GPIOE_2),
+ GPIO_GROUP(GPIOE_3),
+ GPIO_GROUP(GPIOE_4),
+ GPIO_GROUP(GPIOE_5),
+ GPIO_GROUP(GPIOE_6),
+
+ GPIO_GROUP(GPIOZ_0),
+ GPIO_GROUP(GPIOZ_1),
+ GPIO_GROUP(GPIOZ_2),
+ GPIO_GROUP(GPIOZ_3),
+ GPIO_GROUP(GPIOZ_4),
+ GPIO_GROUP(GPIOZ_5),
+ GPIO_GROUP(GPIOZ_6),
+ GPIO_GROUP(GPIOZ_7),
+ GPIO_GROUP(GPIOZ_8),
+ GPIO_GROUP(GPIOZ_9),
+ GPIO_GROUP(GPIOZ_10),
+ GPIO_GROUP(GPIOZ_11),
+ GPIO_GROUP(GPIOZ_12),
+ GPIO_GROUP(GPIOZ_13),
+
+ GPIO_GROUP(GPIOT_0),
+ GPIO_GROUP(GPIOT_1),
+ GPIO_GROUP(GPIOT_2),
+ GPIO_GROUP(GPIOT_3),
+ GPIO_GROUP(GPIOT_4),
+ GPIO_GROUP(GPIOT_5),
+ GPIO_GROUP(GPIOT_6),
+ GPIO_GROUP(GPIOT_7),
+ GPIO_GROUP(GPIOT_8),
+ GPIO_GROUP(GPIOT_9),
+ GPIO_GROUP(GPIOT_10),
+ GPIO_GROUP(GPIOT_11),
+ GPIO_GROUP(GPIOT_12),
+ GPIO_GROUP(GPIOT_13),
+ GPIO_GROUP(GPIOT_14),
+ GPIO_GROUP(GPIOT_15),
+ GPIO_GROUP(GPIOT_16),
+ GPIO_GROUP(GPIOT_17),
+ GPIO_GROUP(GPIOT_18),
+ GPIO_GROUP(GPIOT_19),
+ GPIO_GROUP(GPIOT_20),
+ GPIO_GROUP(GPIOT_21),
+ GPIO_GROUP(GPIOT_22),
+ GPIO_GROUP(GPIOT_23),
+
+ GPIO_GROUP(GPIOM_0),
+ GPIO_GROUP(GPIOM_1),
+ GPIO_GROUP(GPIOM_2),
+ GPIO_GROUP(GPIOM_3),
+ GPIO_GROUP(GPIOM_4),
+ GPIO_GROUP(GPIOM_5),
+ GPIO_GROUP(GPIOM_6),
+ GPIO_GROUP(GPIOM_7),
+ GPIO_GROUP(GPIOM_8),
+ GPIO_GROUP(GPIOM_9),
+ GPIO_GROUP(GPIOM_10),
+ GPIO_GROUP(GPIOM_11),
+ GPIO_GROUP(GPIOM_12),
+ GPIO_GROUP(GPIOM_13),
+
+ GPIO_GROUP(GPIOY_0),
+ GPIO_GROUP(GPIOY_1),
+ GPIO_GROUP(GPIOY_2),
+ GPIO_GROUP(GPIOY_3),
+ GPIO_GROUP(GPIOY_4),
+ GPIO_GROUP(GPIOY_5),
+ GPIO_GROUP(GPIOY_6),
+ GPIO_GROUP(GPIOY_7),
+ GPIO_GROUP(GPIOY_8),
+ GPIO_GROUP(GPIOY_9),
+ GPIO_GROUP(GPIOY_10),
+ GPIO_GROUP(GPIOY_11),
+ GPIO_GROUP(GPIOY_12),
+ GPIO_GROUP(GPIOY_13),
+ GPIO_GROUP(GPIOY_14),
+ GPIO_GROUP(GPIOY_15),
+ GPIO_GROUP(GPIOY_16),
+ GPIO_GROUP(GPIOY_17),
+ GPIO_GROUP(GPIOY_18),
+
+ GPIO_GROUP(GPIOH_0),
+ GPIO_GROUP(GPIOH_1),
+ GPIO_GROUP(GPIOH_2),
+ GPIO_GROUP(GPIOH_3),
+ GPIO_GROUP(GPIOH_4),
+ GPIO_GROUP(GPIOH_5),
+ GPIO_GROUP(GPIOH_6),
+ GPIO_GROUP(GPIOH_7),
+ GPIO_GROUP(GPIO_TEST_N),
+
+ /* Bank B func1 */
+ GROUP(emmc_nand_d0, 1),
+ GROUP(emmc_nand_d1, 1),
+ GROUP(emmc_nand_d2, 1),
+ GROUP(emmc_nand_d3, 1),
+ GROUP(emmc_nand_d4, 1),
+ GROUP(emmc_nand_d5, 1),
+ GROUP(emmc_nand_d6, 1),
+ GROUP(emmc_nand_d7, 1),
+ GROUP(emmc_clk, 1),
+ GROUP(emmc_cmd, 1),
+ GROUP(emmc_nand_ds, 1),
+
+ /* Bank B func1 */
+ GROUP(nor_hold, 2),
+ GROUP(nor_d, 2),
+ GROUP(nor_q, 2),
+ GROUP(nor_c, 2),
+ GROUP(nor_wp, 2),
+ GROUP(nor_cs, 2),
+
+
+ /* Bank C func1 */
+ GROUP(sdcard_d0, 1),
+ GROUP(sdcard_d1, 1),
+ GROUP(sdcard_d2, 1),
+ GROUP(sdcard_d3, 1),
+ GROUP(sdcard_clk, 1),
+ GROUP(sdcard_cmd, 1),
+ GROUP(gen_clk_out_c, 1),
+
+ /* Bank C func2 */
+ GROUP(jtag_b_tdo, 2),
+ GROUP(jtag_b_tdi, 2),
+ GROUP(uart_ao_a_rx_c, 2),
+ GROUP(uart_ao_a_tx_c, 2),
+ GROUP(jtag_b_clk, 2),
+ GROUP(jtag_b_tms, 2),
+
+ /* Bank C func3 */
+ GROUP(spi1_mosi_c, 3),
+ GROUP(spi1_miso_c, 3),
+ GROUP(spi1_sclk_c, 3),
+ GROUP(spi1_ss0_c, 3),
+
+ /* Bank X func1 */
+ GROUP(sdio_d0, 1),
+ GROUP(sdio_d1, 1),
+ GROUP(sdio_d2, 1),
+ GROUP(sdio_d3, 1),
+ GROUP(sdio_clk, 1),
+ GROUP(sdio_cmd, 1),
+ GROUP(pwm_b, 1),
+ GROUP(pwm_c, 1),
+ GROUP(tdm_d0, 1),
+ GROUP(tdm_d1, 1),
+ GROUP(tdm_fs0, 1),
+ GROUP(tdm_sclk0, 1),
+ GROUP(uart_c_tx, 1),
+ GROUP(uart_c_rx, 1),
+ GROUP(uart_c_cts, 1),
+ GROUP(uart_c_rts, 1),
+ GROUP(pwm_a, 1),
+ GROUP(i2c2_sda_x, 1),
+ GROUP(i2c2_sck_x, 1),
+ GROUP(pwm_d, 1),
+
+ /* Bank X func2 */
+ GROUP(clk12_24_x, 2),
+
+ /* Bank W func1 */
+ GROUP(hdmirx_a_hpd, 1),
+ GROUP(hdmirx_a_det, 1),
+ GROUP(hdmirx_a_sda, 1),
+ GROUP(hdmirx_a_sck, 1),
+ GROUP(hdmirx_c_hpd, 1),
+ GROUP(hdmirx_c_det, 1),
+ GROUP(hdmirx_c_sda, 1),
+ GROUP(hdmirx_c_sck, 1),
+ GROUP(hdmirx_b_hpd, 1),
+ GROUP(hdmirx_b_det, 1),
+ GROUP(hdmirx_b_sda, 1),
+ GROUP(hdmirx_b_sck, 1),
+ GROUP(cec_a, 1),
+ GROUP(hdmitx_sda_w13, 1),
+ GROUP(hdmitx_scl_w14, 1),
+ GROUP(hdmitx_hpd_in, 1),
+ GROUP(cec_b, 1),
+
+ /* Bank W func2 */
+ GROUP(uart_ao_a_tx_w2, 2),
+ GROUP(uart_ao_a_rx_w3, 2),
+ GROUP(uart_ao_a_tx_w6, 2),
+ GROUP(uart_ao_a_rx_w7, 2),
+ GROUP(uart_ao_a_tx_w10, 2),
+ GROUP(uart_ao_a_rx_w11, 2),
+
+ /* Bank W func3 */
+ GROUP(hdmitx_sda_w2, 3),
+ GROUP(hdmitx_scl_w3, 3),
+
+ /* Bank D func1 */
+ GROUP(uart_ao_a_tx_d0, 1),
+ GROUP(uart_ao_a_rx_d1, 1),
+ GROUP(i2c0_ao_sck_d, 1),
+ GROUP(i2c0_ao_sda_d, 1),
+ GROUP(remote_out_d4, 1),
+ GROUP(remote_in, 1),
+ GROUP(jtag_a_clk, 1),
+ GROUP(jtag_a_tms, 1),
+ GROUP(jtag_a_tdi, 1),
+ GROUP(jtag_a_tdo, 1),
+ GROUP(gen_clk_out_d, 1),
+ GROUP(pwm_ao_g_d11, 1),
+ GROUP(wd_rsto, 1),
+
+ /* Bank D func2 */
+ GROUP(i2c0_slave_ao_sck, 2),
+ GROUP(i2c0_slave_ao_sda, 2),
+ GROUP(rtc_clk_in, 2),
+ GROUP(pwm_ao_h_d5, 2),
+ GROUP(pwm_ao_c_d, 2),
+ GROUP(pwm_ao_g_d7, 2),
+ GROUP(spdif_out_d, 2),
+ GROUP(spdif_in_d, 2),
+ GROUP(pwm_ao_h_d10, 2),
+
+ /* Bank D func3 */
+ GROUP(uart_ao_b_tx, 3),
+ GROUP(uart_ao_b_rx, 3),
+ GROUP(uart_ao_b_cts, 3),
+ GROUP(pwm_ao_c_hiz, 3),
+ GROUP(pwm_ao_g_hiz, 3),
+ GROUP(uart_ao_b_rts, 3),
+
+ /* Bank D func4 */
+ GROUP(remote_out_d6, 4),
+
+ /* Bank E func1 */
+ GROUP(pwm_ao_a, 1),
+ GROUP(pwm_ao_b, 1),
+ GROUP(pwm_ao_c_e, 1),
+ GROUP(pwm_ao_d, 1),
+ GROUP(pwm_ao_e, 1),
+ GROUP(pwm_ao_f, 1),
+ GROUP(pwm_ao_g_e, 1),
+
+ /* Bank E func2 */
+ GROUP(i2c0_ao_sck_e, 2),
+ GROUP(i2c0_ao_sda_e, 2),
+ GROUP(clk25m, 2),
+ GROUP(i2c1_ao_sck, 2),
+ GROUP(i2c1_ao_sda, 2),
+ GROUP(rtc_clk_out, 2),
+
+ /* Bank E func3 */
+ GROUP(clk12_24_e, 3),
+
+ /* Bank Z func1 */
+ GROUP(eth_mdio, 1),
+ GROUP(eth_mdc, 1),
+ GROUP(eth_rgmii_rx_clk, 1),
+ GROUP(eth_rx_dv, 1),
+ GROUP(eth_rxd0, 1),
+ GROUP(eth_rxd1, 1),
+ GROUP(eth_rxd2_rgmii, 1),
+ GROUP(eth_rxd3_rgmii, 1),
+ GROUP(eth_rgmii_tx_clk, 1),
+ GROUP(eth_txen, 1),
+ GROUP(eth_txd0, 1),
+ GROUP(eth_txd1, 1),
+ GROUP(eth_txd2_rgmii, 1),
+ GROUP(eth_txd3_rgmii, 1),
+
+ /* Bank Z func2 */
+ GROUP(iso7816_clk_z, 2),
+ GROUP(iso7816_data_z, 2),
+ GROUP(tsin_b_valid, 2),
+ GROUP(tsin_b_sop, 2),
+ GROUP(tsin_b_din0, 2),
+ GROUP(tsin_b_clk, 2),
+ GROUP(tsin_b_fail, 2),
+ GROUP(tsin_b_din1, 2),
+ GROUP(tsin_b_din2, 2),
+ GROUP(tsin_b_din3, 2),
+ GROUP(tsin_b_din4, 2),
+ GROUP(tsin_b_din5, 2),
+ GROUP(tsin_b_din6, 2),
+ GROUP(tsin_b_din7, 2),
+
+ /* Bank Z func3 */
+ GROUP(tsin_c_z_valid, 3),
+ GROUP(tsin_c_z_sop, 3),
+ GROUP(tsin_c_z_din0, 3),
+ GROUP(tsin_c_z_clk, 3),
+ GROUP(tsin_d_z_valid, 3),
+ GROUP(tsin_d_z_sop, 3),
+ GROUP(tsin_d_z_din0, 3),
+ GROUP(tsin_d_z_clk, 3),
+
+ /* Bank Z func4 */
+ GROUP(spi4_mosi, 4),
+ GROUP(spi4_miso, 4),
+ GROUP(spi4_sclk, 4),
+ GROUP(spi4_ss0, 4),
+ GROUP(spi5_mosi, 4),
+ GROUP(spi5_miso, 4),
+ GROUP(spi5_sclk, 4),
+ GROUP(spi5_ss0, 4),
+
+ /* Bank T func1 */
+ GROUP(mclk1, 1),
+ GROUP(tdm_sclk1, 1),
+ GROUP(tdm_fs1, 1),
+ GROUP(tdm_d2, 1),
+ GROUP(tdm_d3, 1),
+ GROUP(tdm_d4, 1),
+ GROUP(tdm_d5, 1),
+ GROUP(tdm_d6, 1),
+ GROUP(tdm_d7, 1),
+ GROUP(tdm_d8, 1),
+ GROUP(tdm_d9, 1),
+ GROUP(tdm_d10, 1),
+ GROUP(tdm_d11, 1),
+ GROUP(mclk2, 1),
+ GROUP(tdm_sclk2, 1),
+ GROUP(tdm_fs2, 1),
+ GROUP(i2c1_sck, 1),
+ GROUP(i2c1_sda, 1),
+ GROUP(spi0_mosi, 1),
+ GROUP(spi0_miso, 1),
+ GROUP(spi0_sclk, 1),
+ GROUP(spi0_ss0, 1),
+ GROUP(spi0_ss1, 1),
+ GROUP(spi0_ss2, 1),
+
+ /* Bank T func2 */
+ GROUP(spdif_in_t, 2),
+ GROUP(spdif_out_t, 2),
+ GROUP(iso7816_clk_t, 2),
+ GROUP(iso7816_data_t, 2),
+ GROUP(tsin_a_sop_t, 2),
+ GROUP(tsin_a_din0_t, 2),
+ GROUP(tsin_a_clk_t, 2),
+ GROUP(tsin_a_valid_t, 2),
+ GROUP(i2c0_sck_t, 2),
+ GROUP(i2c0_sda_t, 2),
+ GROUP(i2c2_sck_t, 2),
+ GROUP(i2c2_sda_t, 2),
+
+ /* Bank T func3 */
+ GROUP(spi3_mosi, 3),
+ GROUP(spi3_miso, 3),
+ GROUP(spi3_sclk, 3),
+ GROUP(spi3_ss0, 3),
+
+ /* Bank M func1 */
+ GROUP(tdm_d12, 1),
+ GROUP(tdm_d13, 1),
+ GROUP(tdm_d14, 1),
+ GROUP(tdm_d15, 1),
+ GROUP(tdm_sclk3, 1),
+ GROUP(tdm_fs3, 1),
+ GROUP(i2c3_sda_m, 1),
+ GROUP(i2c3_sck_m, 1),
+ GROUP(spi1_mosi_m, 1),
+ GROUP(spi1_miso_m, 1),
+ GROUP(spi1_sclk_m, 1),
+ GROUP(spi1_ss0_m, 1),
+ GROUP(spi1_ss1_m, 1),
+ GROUP(spi1_ss2_m, 1),
+
+ /* Bank M func2 */
+ GROUP(pdm_din1_m0, 2),
+ GROUP(pdm_din2, 2),
+ GROUP(pdm_din3, 2),
+ GROUP(pdm_dclk, 2),
+ GROUP(pdm_din0, 2),
+ GROUP(pdm_din1_m5, 2),
+ GROUP(uart_d_tx_m, 2),
+ GROUP(uart_d_rx_m, 2),
+ GROUP(uart_d_cts_m, 2),
+ GROUP(uart_d_rts_m, 2),
+ GROUP(i2c2_sda_m, 2),
+ GROUP(i2c2_sck_m, 2),
+
+ /* Bank Y func1 */
+ GROUP(spi2_mosi, 1),
+ GROUP(spi2_miso, 1),
+ GROUP(spi2_sclk, 1),
+ GROUP(spi2_ss0, 1),
+ GROUP(spi2_ss1, 1),
+ GROUP(spi2_ss2, 1),
+ GROUP(uart_e_tx, 1),
+ GROUP(uart_e_rx, 1),
+ GROUP(uart_e_cts, 1),
+ GROUP(uart_e_rts, 1),
+ GROUP(uart_d_cts_y, 1),
+ GROUP(uart_d_rts_y, 1),
+ GROUP(uart_d_tx_y, 1),
+ GROUP(uart_d_rx_y, 1),
+ GROUP(i2c4_sck_y, 1),
+ GROUP(i2c4_sda_y, 1),
+ GROUP(i2c5_sck, 1),
+ GROUP(i2c5_sda, 1),
+
+ /* Bank Y func2 */
+ GROUP(tsin_c_y_sop, 2),
+ GROUP(tsin_c_y_din0, 2),
+ GROUP(tsin_c_y_clk, 2),
+ GROUP(tsin_c_y_valid, 2),
+ GROUP(tsin_d_y_sop, 2),
+ GROUP(tsin_d_y_din0, 2),
+ GROUP(tsin_d_y_clk, 2),
+ GROUP(tsin_d_y_valid, 2),
+ GROUP(pcieck_reqn_y, 2),
+
+ /* Bank Y func3 */
+ GROUP(pwm_e, 3),
+ GROUP(hsync, 3),
+ GROUP(vsync, 3),
+ GROUP(pwm_f, 3),
+ GROUP(sync_3d_out, 3),
+ GROUP(vx1_a_htpdn, 3),
+ GROUP(vx1_b_htpdn, 3),
+ GROUP(vx1_a_lockn, 3),
+ GROUP(vx1_b_lockn, 3),
+ GROUP(pwm_vs_y, 3),
+
+ /* Bank Y func4 */
+ GROUP(edp_a_hpd, 4),
+ GROUP(edp_b_hpd, 4),
+
+ /* Bank H func1 */
+ GROUP(mic_mute_key, 1),
+ GROUP(mic_mute_led, 1),
+ GROUP(i2c3_sck_h, 1),
+ GROUP(i2c3_sda_h, 1),
+ GROUP(i2c4_sck_h, 1),
+ GROUP(i2c4_sda_h, 1),
+ GROUP(eth_link_led, 1),
+ GROUP(eth_act_led, 1),
+
+ /* Bank H func2 */
+ GROUP(pwm_vs_h, 2),
+ GROUP(uart_f_tx, 2),
+ GROUP(uart_f_rx, 2),
+ GROUP(uart_f_cts, 2),
+ GROUP(uart_f_rts, 2),
+ GROUP(i2c0_sda_h, 2),
+ GROUP(i2c0_sck_h, 2),
+
+ /* Bank H func3 */
+ GROUP(pcieck_reqn_h, 3)
+};
+
+static const char * const gpio_periphs_groups[] = {
+ "GPIOB_0", "GPIOB_1", "GPIOB_2", "GPIOB_3", "GPIOB_4", "GPIOB_5",
+ "GPIOB_6", "GPIOB_7", "GPIOB_8", "GPIOB_9", "GPIOB_10",
+ "GPIOB_11", "GPIOB_12",
+
+ "GPIOC_0", "GPIOC_1", "GPIOC_2", "GPIOC_3", "GPIOC_4", "GPIOC_5",
+ "GPIOC_6",
+
+ "GPIOX_0", "GPIOX_1", "GPIOX_2", "GPIOX_3", "GPIOX_4", "GPIOX_5",
+ "GPIOX_6", "GPIOX_7", "GPIOX_8", "GPIOX_9", "GPIOX_10", "GPIOX_11",
+ "GPIOX_12", "GPIOX_13", "GPIOX_14", "GPIOX_15", "GPIOX_16", "GPIOX_17",
+ "GPIOX_18", "GPIOX_19",
+
+ "GPIOW_0", "GPIOW_1", "GPIOW_2", "GPIOW_3", "GPIOW_4", "GPIOW_5",
+ "GPIOW_6", "GPIOW_7", "GPIOW_8", "GPIOW_9", "GPIOW_10", "GPIOW_11",
+ "GPIOW_12", "GPIOW_13", "GPIOW_14", "GPIOW_15", "GPIOW_16",
+
+ "GPIOD_0", "GPIOD_1", "GPIOD_2", "GPIOD_3", "GPIOD_4", "GPIOD_5",
+ "GPIOD_6", "GPIOD_7", "GPIOD_8", "GPIOD_9", "GPIOD_10", "GPIOD_11",
+ "GPIOD_12",
+
+ "GPIOE_0", "GPIOE_1", "GPIOE_2", "GPIOE_3", "GPIOE_4", "GPIOE_5",
+ "GPIOE_6",
+
+ "GPIOZ_0", "GPIOZ_1", "GPIOZ_2", "GPIOZ_3", "GPIOZ_4", "GPIOZ_5",
+ "GPIOZ_6", "GPIOZ_7", "GPIOZ_8", "GPIOZ_9", "GPIOZ_10", "GPIOZ_11",
+ "GPIOZ_12", "GPIOZ_13",
+
+ "GPIOT_0", "GPIOT_1", "GPIOT_2", "GPIOT_3", "GPIOT_4", "GPIOT_5",
+ "GPIOT_6", "GPIOT_7", "GPIOT_8", "GPIOT_9", "GPIOT_10", "GPIOT_11",
+ "GPIOT_12", "GPIOT_13", "GPIOT_14", "GPIOT_15", "GPIOT_16",
+ "GPIOT_17", "GPIOT_18", "GPIOT_19", "GPIOT_20", "GPIOT_21",
+ "GPIOT_22", "GPIOT_23",
+
+ "GPIOM_0", "GPIOM_1", "GPIOM_2", "GPIOM_3", "GPIOM_4", "GPIOM_5",
+ "GPIOM_6", "GPIOM_7", "GPIOM_8", "GPIOM_9", "GPIOM_10", "GPIOM_11",
+ "GPIOM_12", "GPIOM_13",
+
+ "GPIOY_0", "GPIOY_1", "GPIOY_2", "GPIOY_3", "GPIOY_4", "GPIOY_5",
+ "GPIOY_6", "GPIOY_7", "GPIOY_8", "GPIOY_9", "GPIOY_10", "GPIOY_11",
+ "GPIOY_12", "GPIOY_13", "GPIOY_14", "GPIOY_15", "GPIOY_16",
+ "GPIOY_17", "GPIOY_18",
+
+ "GPIOH_0", "GPIOH_1", "GPIOH_2", "GPIOH_3", "GPIOH_4", "GPIOH_5",
+ "GPIOH_6", "GPIOH_7",
+
+ "GPIO_TEST_N"
+};
+
+static const char * const emmc_groups[] = {
+ "emmc_nand_d0", "emmc_nand_d1", "emmc_nand_d2", "emmc_nand_d3",
+ "emmc_nand_d4", "emmc_nand_d5", "emmc_nand_d6", "emmc_nand_d7",
+ "emmc_clk", "emmc_cmd", "emmc_nand_ds"
+};
+
+static const char * const nor_groups[] = {
+ "nor_hold", "nor_d", "nor_q", "nor_c", "nor_wp", "nor_cs"
+};
+
+static const char * const sdcard_groups[] = {
+ "sdcard_d0", "sdcard_d1", "sdcard_d2", "sdcard_d3", "sdcard_clk",
+ "sdcard_cmd"
+};
+
+static const char * const sdio_groups[] = {
+ "sdio_d0", "sdio_d1", "sdio_d2", "sdio_d3", "sdio_clk", "sdio_cmd"
+};
+
+static const char * const gen_clk_groups[] = {
+ "gen_clk_out_c", "gen_clk_out_d"
+};
+
+static const char * const jtag_a_groups[] = {
+ "jtag_a_clk", "jtag_a_tms", "jtag_a_tdi", "jtag_a_tdo"
+};
+
+static const char * const jtag_b_groups[] = {
+ "jtag_b_tdo", "jtag_b_tdi", "jtag_b_clk", "jtag_b_tms"
+};
+
+static const char * const uart_c_groups[] = {
+ "uart_c_tx", "uart_c_rx", "uart_c_cts", "uart_c_rts"
+};
+
+static const char * const uart_d_groups[] = {
+ "uart_d_tx_m", "uart_d_rx_m", "uart_d_cts_m", "uart_d_rts_m",
+ "uart_d_rts_y", "uart_d_tx_y", "uart_d_rx_y", "uart_d_cts_y"
+};
+
+static const char * const uart_e_groups[] = {
+ "uart_e_tx", "uart_e_rx", "uart_e_cts", "uart_e_rts"
+};
+
+static const char * const uart_f_groups[] = {
+ "uart_f_tx", "uart_f_rx", "uart_f_cts", "uart_f_rts"
+};
+
+static const char * const uart_ao_a_groups[] = {
+ "uart_ao_a_rx_c", "uart_ao_a_tx_c", "uart_ao_a_tx_w2",
+ "uart_ao_a_rx_w3", "uart_ao_a_tx_w6", "uart_ao_a_rx_w7",
+ "uart_ao_a_tx_w10", "uart_ao_a_rx_w11", "uart_ao_a_tx_d0",
+ "uart_ao_a_rx_d1"
+};
+
+static const char * const uart_ao_b_groups[] = {
+ "uart_ao_b_tx", "uart_ao_b_rx", "uart_ao_b_cts", "uart_ao_b_rts"
+};
+
+static const char * const spi0_groups[] = {
+ "spi0_mosi", "spi0_miso", "spi0_sclk", "spi0_ss0", "spi0_ss1",
+ "spi0_ss2"
+};
+
+static const char * const spi1_groups[] = {
+ "spi1_mosi_c", "spi1_miso_c", "spi1_sclk_c", "spi1_ss0_c",
+ "spi1_mosi_m", "spi1_miso_m", "spi1_sclk_m", "spi1_ss0_m",
+ "spi1_ss1_m", "spi1_ss2_m"
+};
+
+static const char * const spi2_groups[] = {
+ "spi2_mosi", "spi2_miso", "spi2_sclk", "spi2_ss0", "spi2_ss1",
+ "spi2_ss2"
+};
+
+static const char * const spi3_groups[] = {
+ "spi3_mosi", "spi3_miso", "spi3_sclk", "spi3_ss0"
+};
+
+static const char * const spi4_groups[] = {
+ "spi4_mosi", "spi4_miso", "spi4_sclk", "spi4_ss0"
+};
+
+static const char * const spi5_groups[] = {
+ "spi5_mosi", "spi5_miso", "spi5_sclk", "spi5_ss0"
+};
+
+static const char * const pwm_a_groups[] = {
+ "pwm_a"
+};
+
+static const char * const pwm_b_groups[] = {
+ "pwm_b"
+};
+
+static const char * const pwm_c_groups[] = {
+ "pwm_c"
+};
+
+static const char * const pwm_d_groups[] = {
+ "pwm_d"
+};
+
+static const char * const pwm_e_groups[] = {
+ "pwm_e"
+};
+
+static const char * const pwm_f_groups[] = {
+ "pwm_f"
+};
+
+static const char * const pwm_ao_c_hiz_groups[] = {
+ "pwm_ao_c_hiz"
+};
+
+static const char * const pwm_ao_g_hiz_groups[] = {
+ "pwm_ao_g_hiz"
+};
+
+static const char * const pwm_ao_a_groups[] = {
+ "pwm_ao_a"
+};
+
+static const char * const pwm_ao_b_groups[] = {
+ "pwm_ao_b"
+};
+
+static const char * const pwm_ao_c_groups[] = {
+ "pwm_ao_c_d", "pwm_ao_c_e"
+};
+
+static const char * const pwm_ao_d_groups[] = {
+ "pwm_ao_d"
+};
+
+static const char * const pwm_ao_e_groups[] = {
+ "pwm_ao_e"
+};
+
+static const char * const pwm_ao_f_groups[] = {
+ "pwm_ao_f"
+};
+
+static const char * const pwm_ao_h_groups[] = {
+ "pwm_ao_h_d5", "pwm_ao_h_d10"
+};
+
+static const char * const pwm_ao_g_groups[] = {
+ "pwm_ao_g_d11", "pwm_ao_g_d7", "pwm_ao_g_e"
+};
+
+static const char * const pwm_vs_groups[] = {
+ "pwm_vs_y", "pwm_vs_h"
+};
+
+static const char * const tdm_groups[] = {
+ "tdm_d0", "tdm_d1", "tdm_fs0", "tdm_sclk0", "tdm_sclk1", "tdm_fs1",
+ "tdm_d2", "tdm_d3", "tdm_d4", "tdm_d5", "tdm_d6", "tdm_d7",
+ "tdm_d8", "tdm_d9", "tdm_d10", "tdm_d11", "tdm_sclk2", "tdm_fs2",
+
+ "tdm_d12", "tdm_d13", "tdm_d14", "tdm_d15", "tdm_sclk3", "tdm_fs3"
+};
+
+static const char * const i2c0_slave_ao_groups[] = {
+ "i2c0_slave_ao_sck", "i2c0_slave_ao_sda"
+};
+
+static const char * const i2c0_ao_groups[] = {
+ "i2c0_ao_sck_d", "i2c0_ao_sda_d",
+ "i2c0_ao_sck_e", "i2c0_ao_sda_e"
+};
+
+static const char * const i2c1_ao_groups[] = {
+ "i2c1_ao_sck", "i2c1_ao_sda"
+};
+
+static const char * const i2c0_groups[] = {
+ "i2c0_sck_t", "i2c0_sda_t", "i2c0_sck_h", "i2c0_sda_h"
+};
+
+static const char * const i2c1_groups[] = {
+ "i2c1_sck", "i2c1_sda"
+};
+
+static const char * const i2c2_groups[] = {
+ "i2c2_sda_x", "i2c2_sck_x",
+ "i2c2_sda_t", "i2c2_sck_t",
+ "i2c2_sda_m", "i2c2_sck_m"
+};
+
+static const char * const i2c3_groups[] = {
+ "i2c3_sda_m", "i2c3_sck_m", "i2c3_sck_h", "i2c3_sda_h"
+};
+
+static const char * const i2c4_groups[] = {
+ "i2c4_sck_y", "i2c4_sda_y", "i2c4_sck_h", "i2c4_sda_h"
+};
+
+static const char * const i2c5_groups[] = {
+ "i2c5_sck", "i2c5_sda"
+};
+
+static const char * const clk12_24_groups[] = {
+ "clk12_24_x", "clk12_24_e"
+};
+
+static const char * const hdmirx_a_groups[] = {
+ "hdmirx_a_hpd", "hdmirx_a_det", "hdmirx_a_sda", "hdmirx_a_sck"
+};
+
+static const char * const hdmirx_b_groups[] = {
+ "hdmirx_b_hpd", "hdmirx_b_det", "hdmirx_b_sda", "hdmirx_b_sck"
+};
+
+static const char * const hdmirx_c_groups[] = {
+ "hdmirx_c_hpd", "hdmirx_c_det", "hdmirx_c_sda", "hdmirx_c_sck"
+};
+
+static const char * const cec_a_groups[] = {
+ "cec_a"
+};
+
+static const char * const cec_b_groups[] = {
+ "cec_b"
+};
+
+static const char * const hdmitx_groups[] = {
+ "hdmitx_sda_w13", "hdmitx_scl_w14", "hdmitx_hpd_in",
+ "hdmitx_sda_w2", "hdmitx_scl_w3"
+};
+
+static const char * const remote_out_groups[] = {
+ "remote_out_d4", "remote_out_d6"
+};
+
+static const char * const remote_in_groups[] = {
+ "remote_in"
+};
+
+static const char * const wd_rsto_groups[] = {
+ "wd_rsto"
+};
+
+static const char * const rtc_clk_groups[] = {
+ "rtc_clk_in", "rtc_clk_out"
+};
+
+static const char * const spdif_out_groups[] = {
+ "spdif_out_d", "spdif_out_t"
+};
+
+static const char * const spdif_in_groups[] = {
+ "spdif_in_d", "spdif_in_t"
+};
+
+static const char * const clk25m_groups[] = {
+ "clk25m"
+};
+
+static const char * const eth_groups[] = {
+ "eth_mdio", "eth_mdc", "eth_rgmii_rx_clk", "eth_rx_dv", "eth_rxd0",
+ "eth_rxd1", "eth_rxd2_rgmii", "eth_rxd3_rgmii", "eth_rgmii_tx_clk",
+ "eth_txen", "eth_txd0", "eth_txd1", "eth_txd2_rgmii",
+ "eth_txd3_rgmii",
+
+ "eth_link_led", "eth_act_led"
+};
+
+static const char * const iso7816_groups[] = {
+ "iso7816_clk_z", "iso7816_data_z",
+ "iso7816_clk_t", "iso7816_data_t"
+};
+
+static const char * const tsin_a_groups[] = {
+ "tsin_a_sop_t", "tsin_a_din0_t", "tsin_a_clk_t", "tsin_a_valid_t"
+};
+
+static const char * const tsin_b_groups[] = {
+ "tsin_b_valid", "tsin_b_sop", "tsin_b_din0", "tsin_b_clk",
+ "tsin_b_fail", "tsin_b_din1", "tsin_b_din2", "tsin_b_din3",
+ "tsin_b_din4", "tsin_b_din5", "tsin_b_din6", "tsin_b_din7"
+};
+
+static const char * const tsin_c_groups[] = {
+ "tsin_c_z_valid", "tsin_c_z_sop", "tsin_c_z_din0", "tsin_c_z_clk",
+ "tsin_c_y_sop", "tsin_c_y_din0", "tsin_c_y_clk", "tsin_c_y_valid"
+};
+
+static const char * const tsin_d_groups[] = {
+ "tsin_d_z_valid", "tsin_d_z_sop", "tsin_d_z_din0", "tsin_d_z_clk",
+ "tsin_d_y_sop", "tsin_d_y_din0", "tsin_d_y_clk", "tsin_d_y_valid"
+};
+
+static const char * const mclk_groups[] = {
+ "mclk1", "mclk2"
+};
+
+static const char * const pdm_groups[] = {
+ "pdm_din1_m0", "pdm_din2", "pdm_din3", "pdm_dclk", "pdm_din0",
+ "pdm_din1_m5"
+};
+
+static const char * const pcieck_groups[] = {
+ "pcieck_reqn_y", "pcieck_reqn_h"
+};
+
+static const char * const hsync_groups[] = {
+ "hsync"
+};
+
+static const char * const vsync_groups[] = {
+ "vsync"
+};
+
+static const char * const sync_3d_groups[] = {
+ "sync_3d_out"
+};
+
+static const char * const vx1_a_groups[] = {
+ "vx1_a_htpdn", "vx1_a_lockn"
+};
+
+static const char * const vx1_b_groups[] = {
+ "vx1_b_htpdn", "vx1_b_lockn"
+};
+
+static const char * const edp_a_groups[] = {
+ "edp_a_hpd"
+};
+
+static const char * const edp_b_groups[] = {
+ "edp_b_hpd"
+};
+
+static const char * const mic_mute_groups[] = {
+ "mic_mute_key", "mic_mute_led"
+};
+
+static struct meson_pmx_func meson_t7_periphs_functions[] = {
+ FUNCTION(gpio_periphs),
+ FUNCTION(emmc),
+ FUNCTION(nor),
+ FUNCTION(sdcard),
+ FUNCTION(sdio),
+ FUNCTION(gen_clk),
+ FUNCTION(jtag_a),
+ FUNCTION(jtag_b),
+ FUNCTION(uart_c),
+ FUNCTION(uart_d),
+ FUNCTION(uart_e),
+ FUNCTION(uart_f),
+ FUNCTION(uart_ao_a),
+ FUNCTION(uart_ao_b),
+ FUNCTION(spi0),
+ FUNCTION(spi1),
+ FUNCTION(spi2),
+ FUNCTION(spi3),
+ FUNCTION(spi4),
+ FUNCTION(spi5),
+ FUNCTION(pwm_a),
+ FUNCTION(pwm_b),
+ FUNCTION(pwm_c),
+ FUNCTION(pwm_d),
+ FUNCTION(pwm_e),
+ FUNCTION(pwm_f),
+ FUNCTION(pwm_ao_c_hiz),
+ FUNCTION(pwm_ao_g_hiz),
+ FUNCTION(pwm_ao_a),
+ FUNCTION(pwm_ao_b),
+ FUNCTION(pwm_ao_c),
+ FUNCTION(pwm_ao_d),
+ FUNCTION(pwm_ao_e),
+ FUNCTION(pwm_ao_f),
+ FUNCTION(pwm_ao_h),
+ FUNCTION(pwm_ao_g),
+ FUNCTION(pwm_vs),
+ FUNCTION(tdm),
+ FUNCTION(i2c0_slave_ao),
+ FUNCTION(i2c0_ao),
+ FUNCTION(i2c1_ao),
+ FUNCTION(i2c0),
+ FUNCTION(i2c1),
+ FUNCTION(i2c2),
+ FUNCTION(i2c3),
+ FUNCTION(i2c4),
+ FUNCTION(i2c5),
+ FUNCTION(clk12_24),
+ FUNCTION(hdmirx_a),
+ FUNCTION(hdmirx_b),
+ FUNCTION(hdmirx_c),
+ FUNCTION(cec_a),
+ FUNCTION(cec_b),
+ FUNCTION(hdmitx),
+ FUNCTION(remote_out),
+ FUNCTION(remote_in),
+ FUNCTION(wd_rsto),
+ FUNCTION(rtc_clk),
+ FUNCTION(spdif_out),
+ FUNCTION(spdif_in),
+ FUNCTION(clk25m),
+ FUNCTION(eth),
+ FUNCTION(iso7816),
+ FUNCTION(tsin_a),
+ FUNCTION(tsin_b),
+ FUNCTION(tsin_c),
+ FUNCTION(tsin_d),
+ FUNCTION(mclk),
+ FUNCTION(pdm),
+ FUNCTION(pcieck),
+ FUNCTION(hsync),
+ FUNCTION(vsync),
+ FUNCTION(sync_3d),
+ FUNCTION(vx1_a),
+ FUNCTION(vx1_b),
+ FUNCTION(edp_a),
+ FUNCTION(edp_b),
+ FUNCTION(mic_mute)
+};
+
+static struct meson_bank meson_t7_periphs_banks[] = {
+ /* name first last pullen pull dir out in */
+ BANK("GPIOD_", GPIOD_0, GPIOD_12,
+ 0x03, 0, 0x04, 0, 0x02, 0, 0x01, 0, 0x00, 0),
+ BANK("GPIOE_", GPIOE_0, GPIOE_6,
+ 0x0b, 0, 0x0c, 0, 0x0a, 0, 0x09, 0, 0x08, 0),
+ BANK("GPIOZ_", GPIOZ_0, GPIOZ_13,
+ 0x13, 0, 0x14, 0, 0x12, 0, 0x11, 0, 0x10, 0),
+ BANK("GPIOH_", GPIOH_0, GPIOH_7,
+ 0x1b, 0, 0x1c, 0, 0x1a, 0, 0x19, 0, 0x18, 0),
+ BANK("GPIOC_", GPIOC_0, GPIOC_6,
+ 0x23, 0, 0x24, 0, 0x22, 0, 0x21, 0, 0x20, 0),
+ BANK("GPIOB_", GPIOB_0, GPIOB_12,
+ 0x2b, 0, 0x2c, 0, 0x2a, 0, 0x29, 0, 0x28, 0),
+ BANK("GPIOX_", GPIOX_0, GPIOX_19,
+ 0x33, 0, 0x34, 0, 0x32, 0, 0x31, 0, 0x30, 0),
+ BANK("GPIOT_", GPIOT_0, GPIOT_23,
+ 0x43, 0, 0x44, 0, 0x42, 0, 0x41, 0, 0x40, 0),
+ BANK("GPIOY_", GPIOY_0, GPIOY_18,
+ 0x53, 0, 0x54, 0, 0x52, 0, 0x51, 0, 0x50, 0),
+ BANK("GPIOW_", GPIOW_0, GPIOW_16,
+ 0x63, 0, 0x64, 0, 0x62, 0, 0x61, 0, 0x60, 0),
+ BANK("GPIOM_", GPIOM_0, GPIOM_13,
+ 0x73, 0, 0x74, 0, 0x72, 0, 0x71, 0, 0x70, 0),
+ BANK("GPIO_TEST_N", GPIO_TEST_N, GPIO_TEST_N,
+ 0x83, 0, 0x84, 0, 0x82, 0, 0x81, 0, 0x80, 0)
+};
+
+static struct meson_pmx_bank meson_t7_periphs_pmx_banks[] = {
+ /*name first lask reg offset*/
+ BANK_PMX("D", GPIOD_0, GPIOD_12, 0xa, 0),
+ BANK_PMX("E", GPIOE_0, GPIOE_6, 0xc, 0),
+ BANK_PMX("Z", GPIOZ_0, GPIOZ_13, 0x5, 0),
+ BANK_PMX("H", GPIOH_0, GPIOH_7, 0x8, 0),
+ BANK_PMX("C", GPIOC_0, GPIOC_6, 0x7, 0),
+ BANK_PMX("B", GPIOB_0, GPIOB_12, 0x0, 0),
+ BANK_PMX("X", GPIOX_0, GPIOX_19, 0x2, 0),
+ BANK_PMX("T", GPIOT_0, GPIOT_23, 0xf, 0),
+ BANK_PMX("Y", GPIOY_0, GPIOY_18, 0x13, 0),
+ BANK_PMX("W", GPIOW_0, GPIOW_16, 0x16, 0),
+ BANK_PMX("M", GPIOM_0, GPIOM_13, 0xd, 0),
+ BANK_PMX("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0x9, 0)
+};
+
+static struct meson_drive_bank meson_t7_periphs_drive_banks[] = {
+ /* name first lask reg offset*/
+ BANK_DRIVE("D", GPIOD_0, GPIOD_12, 0x7, 0),
+ BANK_DRIVE("E", GPIOE_0, GPIOE_6, 0x0f, 0),
+ BANK_DRIVE("Z", GPIOZ_0, GPIOZ_13, 0x17, 0),
+ BANK_DRIVE("H", GPIOH_0, GPIOH_7, 0x1f, 0),
+ BANK_DRIVE("C", GPIOC_0, GPIOC_6, 0x27, 0),
+ BANK_DRIVE("B", GPIOB_0, GPIOB_12, 0x2f, 0),
+ BANK_DRIVE("X", GPIOX_0, GPIOX_19, 0x37, 0),
+ BANK_DRIVE("T", GPIOT_0, GPIOT_23, 0x47, 0),
+ BANK_DRIVE("Y", GPIOY_0, GPIOY_18, 0x57, 0),
+ BANK_DRIVE("W", GPIOW_0, GPIOW_16, 0x67, 0),
+ BANK_DRIVE("M", GPIOM_0, GPIOM_13, 0x77, 0),
+ BANK_DRIVE("TEST_N", GPIO_TEST_N, GPIO_TEST_N, 0x87, 0)
+};
+
+static struct meson_axg_pmx_data meson_t7_periphs_pmx_banks_data = {
+ .pmx_banks = meson_t7_periphs_pmx_banks,
+ .num_pmx_banks = ARRAY_SIZE(meson_t7_periphs_pmx_banks),
+};
+
+static struct meson_drive_data meson_t7_periphs_drive_data = {
+ .drive_banks = meson_t7_periphs_drive_banks,
+ .num_drive_banks = ARRAY_SIZE(meson_t7_periphs_drive_banks),
+};
+
+static struct meson_pinctrl_data meson_t7_periphs_pinctrl_data = {
+ .name = "periphs-banks",
+ .groups = meson_t7_periphs_groups,
+ .funcs = meson_t7_periphs_functions,
+ .banks = meson_t7_periphs_banks,
+ .num_pins = 157,
+ .num_groups = ARRAY_SIZE(meson_t7_periphs_groups),
+ .num_funcs = ARRAY_SIZE(meson_t7_periphs_functions),
+ .num_banks = ARRAY_SIZE(meson_t7_periphs_banks),
+ .pmx_data = &meson_t7_periphs_pmx_banks_data,
+ .drv_data = &meson_t7_periphs_drive_data,
+};
+
+static const struct udevice_id meson_t7_pinctrl_match[] = {
+ {
+ .compatible = "amlogic,meson-t7-periphs-pinctrl",
+ .data = (ulong)&meson_t7_periphs_pinctrl_data,
+ },
+ { }
+};
+
+U_BOOT_DRIVER(meson_t7_pinctrl) = {
+ .name = "meson-t7-pinctrl",
+ .id = UCLASS_PINCTRL,
+ .of_match = of_match_ptr(meson_t7_pinctrl_match),
+ .probe = meson_pinctrl_probe,
+ .priv_auto_alloc_size = sizeof(struct meson_pinctrl),
+ .ops = &meson_axg_pinctrl_ops,
+};
diff --git a/drivers/pinctrl/meson/pinctrl-meson.c b/drivers/pinctrl/meson/pinctrl-meson.c
index d5760c3..eaf9052 100644
--- a/drivers/pinctrl/meson/pinctrl-meson.c
+++ b/drivers/pinctrl/meson/pinctrl-meson.c
@@ -429,7 +429,9 @@
priv->reg_pullen = (void __iomem *)addr;
}
- if (!check_string(gpio, "reg-names", "drive-strength")) {
+ if (check_string(gpio, "reg-names", "drive-strength")) {
+ priv->reg_drive = priv->reg_pullen;
+ } else {
addr = parse_address(gpio, "drive-strength", na, ns);
if (addr == FDT_ADDR_T_NONE) {
debug("drive address not found\n");
diff --git a/drivers/pinctrl/meson/pinctrl-meson8-pmx.c b/drivers/pinctrl/meson/pinctrl-meson8-pmx.c
index 5f6b431..614cddb 100644
--- a/drivers/pinctrl/meson/pinctrl-meson8-pmx.c
+++ b/drivers/pinctrl/meson/pinctrl-meson8-pmx.c
@@ -1,15 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * First generation of pinmux driver for Amlogic Meson SoCs
- *
- * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
- * Copyright (C) 2017 Jerome Brunet <jbrunet@baylibre.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
/* For this first generation of pinctrl driver every pinmux group can be
diff --git a/drivers/pinctrl/meson/pinctrl-meson8-pmx.h b/drivers/pinctrl/meson/pinctrl-meson8-pmx.h
index dd10e88..1fc4b6a 100644
--- a/drivers/pinctrl/meson/pinctrl-meson8-pmx.h
+++ b/drivers/pinctrl/meson/pinctrl-meson8-pmx.h
@@ -1,15 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * First generation of pinmux driver for Amlogic Meson SoCs
- *
- * Copyright (C) 2014 Beniamino Galvani <b.galvani@gmail.com>
- * Copyright (C) 2017 Jerome Brunet <jbrunet@baylibre.com>
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License
- * version 2 as published by the Free Software Foundation.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program. If not, see <http://www.gnu.org/licenses/>.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
struct meson8_pmx_data {
diff --git a/drivers/pinctrl/mscc/Kconfig b/drivers/pinctrl/mscc/Kconfig
index 57abd3f..cfc6c06 100644
--- a/drivers/pinctrl/mscc/Kconfig
+++ b/drivers/pinctrl/mscc/Kconfig
@@ -20,4 +20,3 @@
help
Support pin multiplexing and pin configuration control on
Microsemi luton SoCs.
-
diff --git a/drivers/pinctrl/mvebu/Kconfig b/drivers/pinctrl/mvebu/Kconfig
index f8882d7..07d4f3e 100644
--- a/drivers/pinctrl/mvebu/Kconfig
+++ b/drivers/pinctrl/mvebu/Kconfig
@@ -15,4 +15,3 @@
Marvell's Armada-8K SoC.
endif
-
diff --git a/drivers/pinctrl/nxp/Kconfig b/drivers/pinctrl/nxp/Kconfig
index 13690dd..f1d5a5c 100644
--- a/drivers/pinctrl/nxp/Kconfig
+++ b/drivers/pinctrl/nxp/Kconfig
@@ -88,4 +88,3 @@
configuration. This driver is different from the linux one,
this is a simple implementation, only parses the 'fsl,pins'
property and configure related registers.
-
diff --git a/drivers/pinctrl/pinctrl-uclass.c b/drivers/pinctrl/pinctrl-uclass.c
index 5978963..f7b4d34 100644
--- a/drivers/pinctrl/pinctrl-uclass.c
+++ b/drivers/pinctrl/pinctrl-uclass.c
@@ -303,14 +303,10 @@
{
struct pinctrl_ops *ops = pinctrl_get_ops(dev);
-#if 0
if (!ops->get_pin_muxing)
return -ENOSYS;
return ops->get_pin_muxing(dev, selector, buf, size);
-#else
- return 0;
-#endif
}
/**
diff --git a/drivers/pinctrl/renesas/Kconfig b/drivers/pinctrl/renesas/Kconfig
index 0df4335..1baab90 100644
--- a/drivers/pinctrl/renesas/Kconfig
+++ b/drivers/pinctrl/renesas/Kconfig
@@ -117,4 +117,3 @@
multiplex function.
endif
-
diff --git a/drivers/pinctrl/uniphier/Kconfig b/drivers/pinctrl/uniphier/Kconfig
index 61d8003..b6abcd1 100644
--- a/drivers/pinctrl/uniphier/Kconfig
+++ b/drivers/pinctrl/uniphier/Kconfig
@@ -58,4 +58,3 @@
select PINCTRL_UNIPHIER
endif
-
diff --git a/drivers/power/Kconfig b/drivers/power/Kconfig
index 41e8ba9..9495dca 100644
--- a/drivers/power/Kconfig
+++ b/drivers/power/Kconfig
@@ -365,4 +365,3 @@
GPIO and it is commonly used with the OMAP3 family of processors
endmenu
-
diff --git a/drivers/power/domain/Kconfig b/drivers/power/domain/Kconfig
index eff520f..93deaef 100644
--- a/drivers/power/domain/Kconfig
+++ b/drivers/power/domain/Kconfig
@@ -59,4 +59,3 @@
Generic power domain implementation for TI devices implementing the
TI SCI protocol.
endmenu
-
diff --git a/drivers/power/pmic/Kconfig b/drivers/power/pmic/Kconfig
index cc8c085..8cf60eb 100644
--- a/drivers/power/pmic/Kconfig
+++ b/drivers/power/pmic/Kconfig
@@ -238,4 +238,3 @@
The STPMU1 PMIC provides 4 BUCKs, 6 LDOs, 1 VREF and 2 power switches.
It is accessed via an I2C interface. The device is used with STM32MP1
SoCs. This driver implements register read/write operations.
-
diff --git a/drivers/power/regulator/Kconfig b/drivers/power/regulator/Kconfig
index e21c3a4..3ed0dd2 100644
--- a/drivers/power/regulator/Kconfig
+++ b/drivers/power/regulator/Kconfig
@@ -252,4 +252,3 @@
driver implements get/set api for the various BUCKS and LDOs supported
by the PMIC device. This driver is controlled by a device tree node
which includes voltage limits.
-
diff --git a/drivers/pwm/pwm-meson.c b/drivers/pwm/pwm-meson.c
index 1b6f35d..98f13c6 100644
--- a/drivers/pwm/pwm-meson.c
+++ b/drivers/pwm/pwm-meson.c
@@ -1,10 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Pwm controller driver for Amlogic Meson AXG SOC
- *
- * Copyright (c) 2018 Amlogic, Inc. All rights reserved.
- * Auther: Bichao Zheng <bichao.zheng@amlogic.com>
- *
- * SPDX-License-Identifier: (GPL-2.0+ or MIT)
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -22,6 +18,8 @@
struct meson_pwm_priv{
struct meson_pwm_reg *regs;
struct meson_pwm_state *pwm_state;
+ struct meson_pwm_data *pwm_data;
+ u32 extern_clk_addr;
};
static u64 meson_pwm_clock_get_rate(void)
@@ -115,18 +113,25 @@
struct meson_pwm_priv *priv = dev_get_priv(dev);
struct meson_pwm_reg *regs = priv->regs;
struct meson_pwm_state *pwm_state = priv->pwm_state;
+ fdt_addr_t clk_addr = priv->extern_clk_addr;
switch (channel) {
case MESON_PWM0:
/*set div and clock enable*/
- setbits_le32(®s->miscr, (pwm_state[channel].pre_div << 8 | 1 << 15));
+ if (priv->pwm_data->extern_clk)
+ clrsetbits_le32(clk_addr, (0xff << 0) | (3 << 9) ,(pwm_state[channel].pre_div << 0 | 1 << 8));
+ else
+ setbits_le32(®s->miscr, (pwm_state[channel].pre_div << 8 | 1 << 15));
/*set duty*/
writel((pwm_state[channel].hi << 16 | pwm_state[channel].lo), ®s->dar);
break;
case MESON_PWM1:
/*set div and clock enable*/
- setbits_le32(®s->miscr, (pwm_state[channel].pre_div << 16 | 1 << 23));
+ if (priv->pwm_data->extern_clk)
+ clrsetbits_le32(clk_addr, (0xff << 16) | (3 << 25) ,(pwm_state[channel].pre_div << 16 | 1 << 24));
+ else
+ setbits_le32(®s->miscr, (pwm_state[channel].pre_div << 16 | 1 << 23));
/*set duty*/
writel((pwm_state[channel].hi << 16 | pwm_state[channel].lo), ®s->dbr);
break;
@@ -273,20 +278,25 @@
struct meson_pwm_priv *priv = dev_get_priv(dev);
struct meson_pwm_reg *regs = priv->regs;
struct meson_pwm_state *pwm_state = priv->pwm_state;
- unsigned int val, orig;
+ fdt_addr_t clk_addr = priv->extern_clk_addr;
+ unsigned int val, val_clk, orig;
switch (channel) {
case MESON_PWM0:
val = 1 << 0;
+ val_clk = 1 << 8;
break;
case MESON_PWM1:
val = 1 << 1;
+ val_clk = 1 << 24;
break;
case MESON_PWM2:
val = 1 << 25;
+ val_clk = 1 << 8;
break;
case MESON_PWM3:
val = 1 << 24;
+ val_clk = 1 << 24;
break;
default:
pr_err("channel is not legal\n");
@@ -296,6 +306,11 @@
orig = readl(®s->miscr);
orig |= val;
writel(orig, ®s->miscr);
+ if (priv->pwm_data->extern_clk) {
+ orig = readl(clk_addr);
+ orig |= val_clk;
+ writel(orig, clk_addr);
+ }
pwm_state[channel].enabled = 1;
}
@@ -304,20 +319,25 @@
struct meson_pwm_priv *priv = dev_get_priv(dev);
struct meson_pwm_reg *regs = priv->regs;
struct meson_pwm_state *pwm_state = priv->pwm_state;
- unsigned int val, orig;
+ fdt_addr_t clk_addr = priv->extern_clk_addr;
+ unsigned int val, val_clk, orig;
switch (channel) {
case MESON_PWM0:
val = 1 << 0;
+ val_clk = 1 << 8;
break;
case MESON_PWM1:
val = 1 << 1;
+ val_clk = 1 << 24;
break;
case MESON_PWM2:
val = 1 << 25;
+ val_clk = 1 << 8;
break;
case MESON_PWM3:
val = 1 << 24;
+ val_clk = 1 << 24;
break;
default:
pr_err("channel is not legal\n");
@@ -327,6 +347,11 @@
orig = readl(®s->miscr);
orig &= ~val;
writel(orig, ®s->miscr);
+ if (priv->pwm_data->extern_clk) {
+ orig = readl(clk_addr);
+ orig &= ~val_clk;
+ writel(orig, clk_addr);
+ }
pwm_state[channel].enabled = 0;
}
@@ -483,7 +508,22 @@
{
struct meson_pwm_priv *priv = dev_get_priv(dev);
- priv->regs = (struct meson_pwm_reg *)dev_read_addr(dev);
+ priv->pwm_data = (struct meson_pwm_data *)dev_get_driver_data(dev);
+ priv->regs = (struct meson_pwm_reg *)dev_read_addr_index(dev, 0);
+ if (priv->regs == (void *)FDT_ADDR_T_NONE) {
+ pr_err("Coun't get pwm base regs addr\n");
+ return -1;
+ }
+
+ /* If you use external clk, get clk regs addr */
+ if (priv->pwm_data->extern_clk) {
+ priv->extern_clk_addr = dev_read_addr_index(dev, 1);
+ if (priv->extern_clk_addr == FDT_ADDR_T_NONE) {
+ pr_err("Coun't get pwm clk regs addr\n");
+ return -1;
+ }
+ }
+
priv->pwm_state = (struct meson_pwm_state *)calloc(4, sizeof(struct meson_pwm_state));
return 0;
@@ -498,6 +538,14 @@
return 0;
}
+static const struct meson_pwm_data pwm_meson_g12a_data = {
+ .extern_clk = 0,
+};
+
+static const struct meson_pwm_data pwm_meson_v2_data = {
+ .extern_clk = 1,
+};
+
static const struct pwm_ops meson_pwm_ops = {
.set_config = meson_pwm_set_config,
.set_enable = meson_pwm_set_enable,
@@ -508,8 +556,9 @@
};
static const struct udevice_id meson_pwm_ids[] = {
- {.compatible = "amlogic,g12a-ee-pwm"},
- {.compatible = "amlogic,g12a-ao-pwm"},
+ {.compatible = "amlogic,g12a-ee-pwm", .data = (long)&pwm_meson_g12a_data},
+ {.compatible = "amlogic,g12a-ao-pwm", .data = (long)&pwm_meson_g12a_data},
+ {.compatible = "amlogic,meson-v2-pwm", .data = (long)&pwm_meson_v2_data},
{}
};
diff --git a/drivers/pwm/pwm-meson.h b/drivers/pwm/pwm-meson.h
index 1db81cb..9c129c4 100644
--- a/drivers/pwm/pwm-meson.h
+++ b/drivers/pwm/pwm-meson.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef PWM_MESON_H
#define PWM_MESON_H
@@ -19,6 +24,10 @@
u32 br;/*Blink Register*/
};
+struct meson_pwm_data {
+ u8 extern_clk; /* use external clktree */
+};
+
enum pwm_polarity {
PWM_POLARITY_NORMAL,
PWM_POLARITY_INVERSED,
diff --git a/drivers/qe/Kconfig b/drivers/qe/Kconfig
index 73efe0d..49a6e32 100644
--- a/drivers/qe/Kconfig
+++ b/drivers/qe/Kconfig
@@ -10,4 +10,3 @@
|| (TARGET_LS1043ARDB && !SPL_NO_QE && !NAND_BOOT && !QSPI_BOOT)
help
Choose this option to add support for U QUICC Engine.
-
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig
index 0bd4784..fbf7d7b 100644
--- a/drivers/ram/Kconfig
+++ b/drivers/ram/Kconfig
@@ -55,4 +55,3 @@
SDRAM devices connected to DDR subsystem.
source "drivers/ram/stm32mp1/Kconfig"
-
diff --git a/drivers/ram/stm32mp1/Kconfig b/drivers/ram/stm32mp1/Kconfig
index 28dc30d..b9c8166 100644
--- a/drivers/ram/stm32mp1/Kconfig
+++ b/drivers/ram/stm32mp1/Kconfig
@@ -10,4 +10,3 @@
family: support for LPDDR2, LPDDR3 and DDR3
the SDRAM parameters for controleur and phy need to be provided
in device tree (computed by DDR tuning tools)
-
diff --git a/drivers/remoteproc/Kconfig b/drivers/remoteproc/Kconfig
index a0811b7..9eb532b 100644
--- a/drivers/remoteproc/Kconfig
+++ b/drivers/remoteproc/Kconfig
@@ -50,4 +50,3 @@
Say 'y' here to add support for TI power processors such as those
found on certain TI keystone and OMAP generation SoCs.
endmenu
-
diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index e7fc963..9c5208b 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -107,4 +107,3 @@
Support for reset controller on SoCFPGA platform.
endmenu
-
diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig
index e49bded..fd0009b 100644
--- a/drivers/rtc/Kconfig
+++ b/drivers/rtc/Kconfig
@@ -111,4 +111,3 @@
It is a serial (I2C) real-time clock (RTC) with alarm.
endmenu
-
diff --git a/drivers/scsi/Kconfig b/drivers/scsi/Kconfig
index d9a0981..3c826c9 100644
--- a/drivers/scsi/Kconfig
+++ b/drivers/scsi/Kconfig
@@ -16,4 +16,3 @@
which supports SCSI and SATA HDDs. For every device configuration
(IDs/LUNs) a block device is created with RAW read/write and
filesystem support.
-
diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig
index 594294b..b7ff296 100644
--- a/drivers/serial/Kconfig
+++ b/drivers/serial/Kconfig
@@ -779,4 +779,3 @@
default 0
endmenu
-
diff --git a/drivers/serial/serial_meson.c b/drivers/serial/serial_meson.c
index b3dad77..672bbc4 100644
--- a/drivers/serial/serial_meson.c
+++ b/drivers/serial/serial_meson.c
@@ -66,6 +66,7 @@
static int meson_serial_getc(struct udevice *dev)
{
+#ifndef CONFIG_DISABLE_AML_SERIAL
struct meson_serial_platdata *plat = dev->platdata;
struct meson_uart *const uart = plat->reg;
@@ -73,10 +74,14 @@
return -EAGAIN;
return readl(&uart->rfifo) & 0xff;
+#else
+ return 0;
+#endif
}
static int meson_serial_putc(struct udevice *dev, const char ch)
{
+#ifndef CONFIG_DISABLE_AML_SERIAL
struct meson_serial_platdata *plat = dev->platdata;
struct meson_uart *const uart = plat->reg;
@@ -85,6 +90,7 @@
writel(ch, &uart->wfifo);
+#endif
return 0;
}
diff --git a/drivers/smem/Kconfig b/drivers/smem/Kconfig
index 7c84041..7169d0f 100644
--- a/drivers/smem/Kconfig
+++ b/drivers/smem/Kconfig
@@ -22,4 +22,3 @@
processors in a Qualcomm platform.
endif # menu "SMEM Support"
-
diff --git a/drivers/sound/Kconfig b/drivers/sound/Kconfig
index eed14b2..c0d97cc 100644
--- a/drivers/sound/Kconfig
+++ b/drivers/sound/Kconfig
@@ -65,4 +65,3 @@
with the Samsung I2S driver.
endmenu
-
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index 693dd9c..5e14404 100644
--- a/drivers/spi/Kconfig
+++ b/drivers/spi/Kconfig
@@ -293,11 +293,17 @@
config AML_SPIFC
bool "Amlogic SPIFC Driver"
- default y if SPI_NAND
- default y if SPI_FLASH
help
- Enable support for SPI Flash Controller on all meson SoCs.
+ Enable support for SPI Flash Controller on meson SoCs.
It should be set when user want SPI NAND or SPI NOR on meson SoCs.
+ If SPI NAND/SPI FLASH is enabled, please open it in defconfig
+
+config AML_SPIFCV2
+ bool "Amlogic SPIFC_V2 Driver"
+ help
+ Enable support for SPI Flash Controller v2 on a1 meson SoCs.
+ It should be set when user want SPI NAND or SPI NOR on a1 meson SoCs.
+ If SPI NAND/SPI FLASH is enabled, please open it in defconfig
endif # if DM_SPI
@@ -387,4 +393,3 @@
embedding this OMAP3 McSPI IP core.
endif # menu "SPI Support"
-
diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile
index f5ec184..f1c6810 100644
--- a/drivers/spi/Makefile
+++ b/drivers/spi/Makefile
@@ -61,3 +61,4 @@
obj-$(CONFIG_ZYNQMP_GQSPI) += zynqmp_gqspi.o
obj-$(CONFIG_AML_SPICC) += spicc.o
obj-$(CONFIG_AML_SPIFC) += spifc.o
+obj-$(CONFIG_AML_SPIFCV2) += spifc_v2.o
diff --git a/drivers/spi/spi-mem.c b/drivers/spi/spi-mem.c
index af9aef0..e6877c7 100644
--- a/drivers/spi/spi-mem.c
+++ b/drivers/spi/spi-mem.c
@@ -323,6 +323,8 @@
return -EIO;
#else
+/* meson need suppport x2 x4 */
+#ifndef CONFIG_MTD_SPI_NAND
/* U-Boot does not support parallel SPI data lanes */
if ((op->cmd.buswidth != 1) ||
(op->addr.nbytes && op->addr.buswidth != 1) ||
@@ -331,7 +333,7 @@
printf("Dual/Quad raw SPI transfers not supported\n");
return -ENOTSUPP;
}
-
+#endif
if (op->data.nbytes) {
if (op->data.dir == SPI_MEM_DATA_IN)
rx_buf = op->data.buf.in;
diff --git a/drivers/spi/spicc.c b/drivers/spi/spicc.c
index 4d5ca8f..4ed2cb6 100644
--- a/drivers/spi/spicc.c
+++ b/drivers/spi/spicc.c
@@ -1,10 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Driver for Amlogic Meson SPI communication controller (SPICC)
- *
- * Copyright (C) BayLibre, SAS
- * Author: Neil Armstrong <narmstrong@baylibre.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -21,7 +17,13 @@
#include <dm/root.h>
#include <dm/lists.h>
#include <dm/util.h>
+#ifdef CONFIG_SECURE_POWER_CONTROL
+#include <asm/arch/pwr_ctrl.h>
+#endif
+#ifdef CONFIG_CLK_MESON_A1
+#define CONFIG_CLK_IF
+#endif
/* Register Map */
#define SPICC_RXDATA 0x00
@@ -178,22 +180,17 @@
bool has_enhance_clk_div;
bool has_cs_pre_delay;
bool has_enhance_io_delay;
- bool has_comp_clk;
- bool is_div_parent_comp_clk;
+ bool has_async_clk;
+ bool is_div_parent_async_clk;
bool has_enhance_tt_ti_delay;
};
struct meson_spicc_device {
void __iomem *base;
-#ifdef CONFIG_CLK
- struct clk core;
- struct clk comp;
- struct clk clk;
-#else
+ u32 pm_id;
u32 parent_clk_rate;
u32 speed_hz;
u32 real_speed_hz;
-#endif
int num_chipselect;
struct gpio_desc cs_gpios[CS_GPIO_MAX];
const struct meson_spicc_data *data;
@@ -240,11 +237,8 @@
mi_delay = SPICC_MI_NO_DELAY;
cap_delay = SPICC_CAP_AHEAD_2_CYCLE;
-#ifdef CONFIG_CLK
- hz = clk_get_rate(&spicc->clk);
-#else
+
hz = spicc->real_speed_hz;
-#endif
if (hz >= 100000000)
cap_delay = SPICC_CAP_DELAY_1_CYCLE;
else if (hz >= 80000000)
@@ -420,10 +414,6 @@
static int spicc_set_speed(struct udevice *bus, uint hz)
{
struct meson_spicc_device *spicc = dev_get_priv(bus);
-
-#ifdef CONFIG_CLK
- clk_set_rate(&spicc->clk, hz);
-#else
u32 sys_clk_rate, div, mid, real_hz;
u32 regv;
@@ -433,10 +423,9 @@
sys_clk_rate = spicc->parent_clk_rate;
if (spicc->data->has_enhance_clk_div) {
/* speed = sys_clk_rate / 2 / (div+1) */
- div = sys_clk_rate/hz;
- if (div < 2)
- div = 2;
- div = (div >> 1) - 1;
+ div = DIV_ROUND_UP(sys_clk_rate, hz << 1);
+ if (div)
+ div--;
if (div > 0xff)
div = 0xff;
regv = readl_relaxed(spicc->base + SPICC_ENH_CTL0);
@@ -463,7 +452,6 @@
spicc->speed_hz = hz;
spicc->real_speed_hz = real_hz;
spicc_dbg("set speed %dHz (real %dHz)\n", hz, real_hz);
-#endif
meson_spicc_auto_io_delay(spicc);
@@ -506,7 +494,7 @@
writel_relaxed(conf, spicc->base + SPICC_TESTREG);
spicc->mode = mode;
- spicc_dbg("set mode %d\n", mode);
+ spicc_dbg("set mode 0x%x\n", mode);
return 0;
}
@@ -581,62 +569,29 @@
static int spicc_clk_init(struct udevice *bus)
{
struct meson_spicc_device *spicc = dev_get_priv(bus);
-#ifdef CONFIG_CLK
- int ret;
+ struct clk clk;
- /* Get core clk */
- ret = clk_get_by_name(bus, "core", &spicc->core);
- if (ret) {
- spicc_err("get clk_core failed(%d)\n", ret);
- return ret;
- }
- ret = clk_enable(&spicc->core);
- if (ret) {
- spicc_err("enable clk_core failed(%d)\n", ret);
- return ret;
+ spicc->parent_clk_rate = 0;
+ if (!clk_get_by_name(bus, "core", &clk)) {
+ if (!spicc->data->is_div_parent_async_clk)
+ spicc->parent_clk_rate = clk_get_rate(&clk);
}
- /* Get composite clk */
- if (spicc->data->has_comp_clk) {
- ret = clk_get_by_name(bus, "comp", &spicc->comp);
- if (ret) {
- spicc_err("get clk_comp failed(%d)\n", ret);
- return ret;
+ if (!clk_get_by_name(bus, "core-gate", &clk))
+ clk_enable(&clk);
+
+ if (spicc->data->has_async_clk) {
+ if (!clk_get_by_name(bus, "async", &clk)) {
+ if (spicc->data->is_div_parent_async_clk)
+ spicc->parent_clk_rate = clk_get_rate(&clk);
}
- ret = clk_enable(&spicc->comp);
- if (ret) {
- spicc_err("enable clk_comp failed(%d)\n", ret);
- return ret;
- }
- clk_set_parent(&spicc->clk, &spicc->comp);
+
+ if (!clk_get_by_name(bus, "async-gate", &clk))
+ clk_enable(&clk);
}
- else
- clk_set_parent(&spicc->clk, &spicc->core);
-#else
- u32 regv;
- u8 mux=3, div = 0;
- unsigned long comp_rate[] = {
- 24000000, /* XTAL */
- 166666666, /* CLK81 */
- 500000000, /* FCLK_DIV4 */
- 666666666, /* FCLK_DIV3 */
- 1000000000, /* FCLK_DIV2 */
- 400000000, /* FCLK_DIV5 */
- 285700000, /* FCLK_DIV7 */
- };
- regv = readl(P_HHI_SPICC_CLK_CNTL);
- /* mux[25:23], gate[22], div[21:16] */
- regv &= ~((0x7 << 23) | (1 << 22) | (0x3f << 16));
- regv |= (mux << 23) | (1 << 22) | (div << 16);
- writel(regv, P_HHI_SPICC_CLK_CNTL);
- spicc->parent_clk_rate = comp_rate[mux];
-
- regv = readl(P_HHI_GCLK_MPEG0);
- regv |= 1 << 14;
- writel(regv, P_HHI_GCLK_MPEG0);
-#endif
- return 0;
+ spicc_info("parent clk rate %d\n", spicc->parent_clk_rate);
+ return spicc->parent_clk_rate ? 0 : -ENODEV;
}
static int spicc_cs_init(struct udevice *bus)
@@ -670,6 +625,12 @@
spicc->data = (struct meson_spicc_data *)dev_get_driver_data(bus);
spicc->base = (void __iomem *)dev_read_addr(bus);
+#ifdef CONFIG_SECURE_POWER_CONTROL
+ if (!dev_read_u32(bus, "pm-id", &spicc->pm_id)) {
+ pwr_ctrl_psci_smc(spicc->pm_id, true);
+ spicc_info("power on %d\n", spicc->pm_id);
+ }
+#endif
spicc_info("0x%p\n", spicc->base);
if (spicc_clk_init(bus))
return -ENODEV;
@@ -696,6 +657,9 @@
return 0;
}
+/* g9tv/gxbb */
+
+/* gxtvbb/gxl/gxm/ (LD_CNTL) */
static const struct meson_spicc_data meson_spicc_gx_data = {
.min_speed_hz = 325000,
.max_speed_hz = 4166667,
@@ -703,6 +667,7 @@
.fifo_size = 16,
};
+/* txl/gxlx/txlx (ENHANCE_CNTL) */
static const struct meson_spicc_data meson_spicc_txlx_data = {
.min_speed_hz = 325000,
.max_speed_hz = 83333333,
@@ -713,6 +678,7 @@
.has_cs_pre_delay = true,
};
+/* axg (ENHANCE_CNTL1, async-clk is only used for delay ctrl) */
static const struct meson_spicc_data meson_spicc_axg_data = {
.min_speed_hz = 325000,
.max_speed_hz = 83333333,
@@ -721,9 +687,11 @@
.has_enhance_clk_div = true,
.has_cs_pre_delay = true,
.has_enhance_io_delay = true,
- .has_comp_clk = true,
+ .has_async_clk = true,
};
+/* g12a (ENHANCE_CNTL2, async-clk can be used for spi-io-clk)
+ txhd hasn't ENHANCE_CNTL2 */
static const struct meson_spicc_data meson_spicc_g12a_data = {
.min_speed_hz = 50000,
.max_speed_hz = 166666667,
@@ -732,8 +700,8 @@
.has_enhance_clk_div = true,
.has_cs_pre_delay = true,
.has_enhance_io_delay = true,
- .has_comp_clk = true,
- .is_div_parent_comp_clk = true,
+ .has_async_clk = true,
+ .is_div_parent_async_clk = true,
.has_enhance_tt_ti_delay = true,
};
diff --git a/drivers/spi/spifc.c b/drivers/spi/spifc.c
index fb0b7bf..c6a9f5a 100644
--- a/drivers/spi/spifc.c
+++ b/drivers/spi/spifc.c
@@ -1,11 +1,6 @@
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Amlogic Meson SPI flash controller(SPIFC)
- *
- * Copyright (C) 2018 Amlogic Corporation
- *
- * Licensed under the GPL-2 or later.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -24,6 +19,9 @@
#include <dm/util.h>
#include <dm/pinctrl.h>
+
+//#define CONFIG_SPIFC_COMPATIBLE_TO_APPOLO
+
DECLARE_GLOBAL_DATA_PTR;
struct spifc_regs {
@@ -156,6 +154,12 @@
{
unsigned int val;
+ val = 1 << USER_CMD_INCLUDE_DIN;
+#ifdef CONFIG_SPIFC_COMPATIBLE_TO_APPOLO
+ val |= 1 << COMPATIBLE_TO_APPOLO;
+#endif
+ writel(val, &priv->regs->user);
+
val = readl(&priv->regs->ctrl);
val &= ~((1 << FAST_READ_DUAL_OUT) |
(1 << FAST_READ_QUAD_OUT) |
@@ -176,8 +180,12 @@
static void spifc_set_tx_op_mode(struct spifc_priv *priv,
unsigned int slave_mode, unsigned char cmd)
{
- unsigned int val = 0;
+ unsigned int val;
+ val = 1 << USER_CMD_INCLUDE_DOUT;
+#ifdef CONFIG_SPIFC_COMPATIBLE_TO_APPOLO
+ val |= 1 << COMPATIBLE_TO_APPOLO;
+#endif
if (slave_mode & SPI_TX_QUAD) {
if (cmd == FCMD_WRITE_QUAD_OUT)
val |= 1 << FAST_WRITE_QUAD_OUT;
@@ -199,17 +207,18 @@
(1 << FAST_READ_QUAD_OUT) |
(1 << FAST_READ_DUAL_IO) |
(1 << FAST_READ_QUAD_IO));
- writel((1 << USER_CMD_INCLUDE_CMD) |
- ((!!len) << USER_CMD_INCLUDE_ADDR),
- ®s->user);
+ writel((1 << USER_CMD_INCLUDE_CMD)
+#ifdef CONFIG_SPIFC_COMPATIBLE_TO_APPOLO
+ | (1 << COMPATIBLE_TO_APPOLO)
+#endif
+ | ((!!len) << USER_CMD_INCLUDE_ADDR),
+ ®s->user);
writel((7 << USER_CMD_CMD_BITS) |
(cmd << USER_CMD_CMD_VALUE),
®s->user2);
writel(bits << USER_CMD_ADDR_BITS, ®s->user1);
writel(addr << SPI_FLASH_ADDR_START, ®s->addr);
- writel((1 << SPI_FLASH_USR) |
- (cmd << SPI_FLASH_USR_CMD),
- ®s->cmd);
+ writel(1 << SPI_FLASH_USR, ®s->cmd);
while ((readl(®s->cmd) >> SPI_FLASH_USR) & 1)
;
return 0;
@@ -229,10 +238,7 @@
for (i = 0; i < len32; i++)
writel(*p++, cache++);
- setbits_le32(®s->user, 1 << USER_CMD_INCLUDE_DOUT);
- writel(0, ®s->user2);
writel(((len << 3) - 1) << USER_CMD_DOUT_BITS, ®s->user1);
- writel(0, ®s->addr);
writel(1 << SPI_FLASH_USR, ®s->cmd);
while ((readl(®s->cmd) >> SPI_FLASH_USR) & 1)
;
@@ -248,10 +254,7 @@
int len32, i;
u8 temp_buf[SPIFC_CACHE_SIZE_IN_BYTE];
- writel(1 << USER_CMD_INCLUDE_DIN, ®s->user);
- writel(0, ®s->user2);
writel(((len << 3) - 1) << USER_CMD_DIN_BITS, ®s->user1);
- writel(0, ®s->addr);
writel(1 << SPI_FLASH_USR, ®s->cmd);
while ((readl(®s->cmd) >> SPI_FLASH_USR) & 1)
;
@@ -266,35 +269,13 @@
static int spifc_claim_bus(struct udevice *dev)
{
- struct udevice *bus = dev->parent;
- struct spifc_priv *priv = dev_get_priv(bus);
- int ret;
-
- ret = pinctrl_select_state(bus, "default");
- if (ret) {
- pr_err("%s %d ret %d\n", __func__, __LINE__, ret);
- return ret;
- }
-
- dm_gpio_free(bus, &priv->cs_gpios);
- ret = gpio_request_by_name(bus, "cs-gpios",
- 0, &priv->cs_gpios, 0);
- if (ret) {
- pr_err("%s %d request gpio error!\n", __func__, __LINE__);
- return ret;
- }
- if (!dm_gpio_is_valid(&priv->cs_gpios)) {
- pr_err("%s %d cs pin gpio invalid!\n", __func__, __LINE__);
- return 1;
- }
- ret = dm_gpio_set_dir_flags(&priv->cs_gpios, GPIOD_IS_OUT);
- if (ret)
- pr_err("%s %d set dir error!\n", __func__, __LINE__);
-
- return ret;
+ /* Deleted invalid gpio operations, otherwise it
+ * will seriously reduce the read and write speed
+ */
+ return 0;
}
-static int spifc_release_bus(struct udevice *bus)
+static int spifc_release_bus(struct udevice *dev)
{
return 0;
}
@@ -335,8 +316,7 @@
if (div < 2) {
pr_err("%s %d can not support %d speed!\n",
__func__, __LINE__, hz);
- if (!plat->speed)
- div = 2;
+ div = 2;
hz = SPIFC_MAX_CLK_RATE / div;
}
#ifdef CONFIG_SPIFC_COMPATIBLE_TO_APPOLO
@@ -396,9 +376,9 @@
printf("%s: error bitlen\n", __func__);
return -EINVAL;
}
- spifc_claim_bus(dev);
- spifc_set_speed(bus, slave->max_hz);
- spifc_set_mode(bus, slave->mode);
+// spifc_claim_bus(dev);
+// spifc_set_speed(bus, slave->max_hz);
+// spifc_set_mode(bus, slave->mode);
if (flags & SPI_XFER_BEGIN) {
spifc_chipselect(dev, 1);
buf = (u8 *)dout;
@@ -446,18 +426,21 @@
struct spifc_priv *priv = dev_get_priv(bus);
int ret = 0;
+ /* In consideration of compatibility with other storage media,
+ * reset pinmux to spifc here.
+ */
+ ret = pinctrl_select_state(bus, "default");
+ if (ret) {
+ pr_err("select state %s failed\n", "default");
+ return ret;
+ }
+
priv->regs = (struct spifc_regs *)plat->reg;
#if defined(CONFIG_CLK) && (CONFIG_CLK)
- ret = clk_get_by_name(bus, "core", &priv->core);
- if (ret) {
- printf("can't get clk source!\n");
- return ret;
- }
- ret = clk_enable(&priv->core);
- if (ret) {
- printf("enable clk source fail\n");
- return ret;
- }
+ if (clk_get_by_name(bus, "core", &priv->core))
+ printf("%s can't get clk source!\n", __func__);
+ else if (clk_enable(&priv->core))
+ printf("%s enable clk source fail\n", __func__);
#endif/* CONFIG_CLK */
ret = gpio_request_by_name(bus, "cs-gpios",
@@ -475,7 +458,7 @@
if (ret)
pr_err("%s %d set dir error!\n", __func__, __LINE__);
- return ret;
+ return dm_gpio_set_value(&priv->cs_gpios, 1);
}
static int spifc_ofdata_to_platdata(struct udevice *bus)
diff --git a/drivers/spi/spifc_v2.c b/drivers/spi/spifc_v2.c
new file mode 100644
index 0000000..0424444
--- /dev/null
+++ b/drivers/spi/spifc_v2.c
@@ -0,0 +1,469 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <clk.h>
+#include <asm/io.h>
+#include <asm/gpio.h>
+#include <asm/arch/secure_apb.h>
+#include <spi.h>
+#include <amlogic/spifc.h>
+#include <dm/device-internal.h>
+#include <dm/uclass-internal.h>
+#include <dm/root.h>
+#include <dm/lists.h>
+#include <dm/util.h>
+#include <dm/pinctrl.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+struct spifc_priv {
+ struct spifc_regs *regs;
+ void __iomem *mem_map;
+#if defined(CONFIG_CLK) && (CONFIG_CLK)
+ struct clk spifc_source;
+ struct clk spifc_mux;
+ struct clk spifc_div;
+ struct clk spifc_gate;
+ struct clk spifc_xtal_gate;
+#endif/* CONFIG_CLK */
+ unsigned int wordlen;
+ unsigned char cmd;
+ /* If datain or dataout is included, save the current command address */
+ unsigned char save_cmd;
+ u32 save_addr;
+ u32 save_addr_len;
+ u32 loop;
+};
+
+/* flash dual/quad read command */
+#define FCMD_READ 0x03
+#define FCMD_READ_FAST 0x0b
+#define FCMD_READ_DUAL_OUT 0x3b
+#define FCMD_READ_QUAD_OUT 0x6b
+#define FCMD_READ_DUAL_IO 0xbb
+#define FCMD_READ_QUAD_IO 0xeb
+/* flash quad write command */
+#define FCMD_WRITE 0x02
+#define FCMD_WRITE_QUAD_OUT 0x32
+#define FCMD_RANDOM_DATA_PROGRAM 0x84
+#define FCMD_RANDOM_DATA_PROGRAM_QUAD 0x34
+
+#define SPIFC_DEFAULT_SPEED 24000000
+#define SPIFC_CACHE_SIZE_IN_WORD 128
+#define SPIFC_CACHE_SIZE_IN_BYTE SPIFC_CACHE_SIZE_IN_WORD << 2
+
+static void spifc_set_rx_op_mode(struct spifc_priv *priv,
+ unsigned int slave_mode, unsigned char cmd)
+{
+ unsigned int val;
+
+ val = readl(SPIFC_USER_CTRL3);
+ val &= ~(3 << 27);
+
+ if (slave_mode & SPI_RX_DUAL) {
+ if (cmd == FCMD_READ_DUAL_OUT)
+ val |= 1 << 27;
+ }
+ if (slave_mode & SPI_RX_QUAD) {
+ if (cmd == FCMD_READ_QUAD_OUT)
+ val |= 1 << 28;
+ }
+ writel(val, SPIFC_USER_CTRL3);
+}
+
+static void spifc_set_tx_op_mode(struct spifc_priv *priv,
+ unsigned int slave_mode, unsigned char cmd)
+{
+ unsigned int val = 0;
+
+ val = readl(SPIFC_USER_CTRL1);
+ val &= ~(3 << 10);
+
+ if (slave_mode & SPI_TX_QUAD) {
+ if (cmd == FCMD_WRITE_QUAD_OUT)
+ val |= 1 << 11;
+ }
+ writel(val, SPIFC_USER_CTRL1);
+}
+
+static void spifc_init(void)
+{
+ /* disable ahb */
+ writel((readl(SPIFC_AHB_REQ_CTRL) & ~(1 << 31)), SPIFC_AHB_REQ_CTRL);
+ writel((readl(SPIFC_AHB_CTRL) & ~(1 << 31)), SPIFC_AHB_CTRL);
+}
+
+static int spifc_user_cmd(struct spifc_priv *priv,
+ u8 cmd, u8 *buf, u8 len)
+{
+ u16 bits = len ? (len - 1) : 0;
+ u32 addr = 0;
+ int i = 0;
+
+ if (len)
+ for (i = 0; i < len; i++) {
+ addr = addr << 8;
+ addr |= buf[i];
+ }
+ writel((1 << 30) | ((!!len) << 19) | (cmd << 20) | (bits << 15), SPIFC_USER_CTRL1);
+ writel(0, SPIFC_USER_CTRL2);
+ writel(0, SPIFC_USER_CTRL3);
+ writel(addr, SPIFC_USER_ADDR);
+ writel(1 << 31, SPIFC_USER_CTRL0);
+ while (!(readl(SPIFC_USER_CTRL0) & 0x40000000));
+
+ return 0;
+}
+
+static int spifc_user_cmd_dout(struct spifc_priv *priv,
+ u8 *buf, int len, unsigned long flags)
+{
+ u32 *p;
+ unsigned int val;
+ int len32, i;
+ u16 bits = priv->save_addr_len ? (priv->save_addr_len - 1) : 0;
+
+ /* The commands FCMD_WRITE and FCMD_WRITE_QUAD_OUT
+ * do not support continuous writes. You need to change
+ * the commands to FCMD_RANDOM_DATA_PROGRAM and
+ * FCMD_RANDOM_DATA_PROGRAM_QUAD.
+ */
+ if (priv->loop) {
+ if (priv->save_cmd == FCMD_WRITE)
+ priv->save_cmd = FCMD_RANDOM_DATA_PROGRAM;
+ else if (priv->save_cmd == FCMD_WRITE_QUAD_OUT)
+ priv->save_cmd = FCMD_RANDOM_DATA_PROGRAM_QUAD;
+ }
+ /* set write DBUF. auto update address */
+ writel((0x3 << 30), SPIFC_DBUF_CTRL);
+
+ p = (u32 *)buf;
+ len32 = (len / 4) + !!(len % 4);
+ for (i = 0; i < len32; i++)
+ writel(*p++, SPIFC_DBUF_DATA);
+
+ val = readl(SPIFC_USER_CTRL1);
+ val &= ~((3 << 28) | (0xff << 20) | (1 << 19) | (3 << 17) | (3 << 15) | (1 << 13) | (1 << 12) | (0x3FF << 0));
+ val |= ((1 << 30) | ((priv->save_cmd << 20)) | ((!!priv->save_addr_len) << 19) | (bits << 15) | (1 << 14) | (len << 0));
+ writel(val, SPIFC_USER_CTRL1);
+ /* disable dummy */
+ writel(0, SPIFC_USER_CTRL2);
+ /* disable date in */
+ writel(0, SPIFC_USER_CTRL3);
+ /* clear buffer start address */
+ writel(0, SPIFC_USER_DBUF_ADDR);
+ writel(priv->save_addr, SPIFC_USER_ADDR);
+ writel(1 << 31, SPIFC_USER_CTRL0);
+ while (!(readl(SPIFC_USER_CTRL0) & 0x40000000));
+
+ return 0;
+}
+
+static int spifc_user_cmd_din(struct spifc_priv *priv,
+ u8 *buf, int len, unsigned long flags)
+{
+ u32 *p;
+ int len32, i;
+ unsigned int val;
+ u8 temp_buf[SPIFC_CACHE_SIZE_IN_BYTE];
+ u16 bits = priv->save_addr_len ? (priv->save_addr_len - 1) : 0;
+
+ /* enable and set cmd addr */
+ writel((1 << 30) | ((!!priv->save_addr_len) << 19) | (priv->save_cmd << 20) | (bits << 15), SPIFC_USER_CTRL1);
+ writel(priv->save_addr, SPIFC_USER_ADDR);
+ /* disable dummy */
+ writel(0, SPIFC_USER_CTRL2);
+ val = readl(SPIFC_USER_CTRL3);
+ val &= ~((1 << 30) | (1 << 29) | (0x3FF << 16));
+ val |= ((1 << 31) | (len << 16));
+ writel(val, SPIFC_USER_CTRL3);
+ /* clear buffer start address */
+ writel(0, SPIFC_USER_DBUF_ADDR);
+ writel(1 << 31, SPIFC_USER_CTRL0);
+ while (!(readl(SPIFC_USER_CTRL0) & 0x40000000));
+ while (!(readl(SPIFC_USER_CTRL0) & 1));
+
+ writel((0x1 << 30) ,SPIFC_DBUF_CTRL);
+ p = (u32 *)temp_buf;
+ len32 = (len / 4) + !!(len % 4);
+ for (i = 0; i < len32; i++) {
+ *p++ = readl(SPIFC_DBUF_DATA);
+ }
+ memcpy(buf, temp_buf, len);
+
+ return 0;
+}
+
+static int spifc_claim_bus(struct udevice *dev)
+{
+ return 0;
+}
+
+static int spifc_release_bus(struct udevice *dev)
+{
+ return 0;
+}
+
+static int spifc_set_speed(struct udevice *bus, uint hz)
+{
+ struct spifc_priv *priv = dev_get_priv(bus);
+ struct spifc_platdata *plat = dev_get_platdata(bus);
+ int ret;
+
+ if (!hz)
+ return 0;
+
+ ret = clk_set_rate(&priv->spifc_div, plat->speed);
+ if (ret) {
+ pr_err("can't set clk rate 0x%x\n !",plat->speed);
+ return ret;
+ }
+ writel((1 << 30) | (1 << 28) | (7 << 16) | (4 << 12) | (4 << 8) | (2), SPIFC_ACTIMING0);
+
+ return 0;
+}
+
+static int spifc_set_mode(struct udevice *bus, uint mode)
+{
+ struct spifc_platdata *plat= dev_get_platdata(bus);
+
+ if (mode == plat->mode)
+ return 0;
+ plat->mode = mode;
+
+ return 0;
+}
+
+static int spifc_set_wordlen(struct udevice *bus, unsigned int wordlen)
+{
+ if (wordlen != 8)
+ return -1;
+
+ return 0;
+}
+
+#define CMD_NREAD 0x03
+
+int spifc_xip_prepare(void)
+{
+ uint32_t ctrl, ctrl1;
+ /* Temporary default x1 for pxp */
+ ctrl = (1 << 31) | (1 << 30) | (CMD_NREAD << 20) | (1 << 19) | (2 << 15);
+ ctrl1 = 0;
+
+ writel(0, SPIFC_USER_CTRL1);
+ writel(ctrl, SPIFC_AHB_REQ_CTRL);
+ writel(ctrl1, SPIFC_AHB_REQ_CTRL1);
+ writel(0, SPIFC_AHB_REQ_CTRL2);
+ writel(0, SPIFC_USER_DBUF_ADDR);
+ writel((1 << 31), SPIFC_AHB_CTRL);
+
+ return 0;
+}
+
+static int spifc_xfer(struct udevice *dev,
+ unsigned int bitlen,
+ const void *dout,
+ void *din,
+ unsigned long flags)
+{
+ struct udevice *bus = dev->parent;
+ struct spi_slave *slave = dev_get_parent_priv(dev);
+ struct spifc_priv *priv = dev_get_priv(bus);
+ u8 *buf;
+ int len = bitlen >> 3;
+ int lening, ret = 0, i = 0;
+
+ if (bitlen % 8) {
+ pr_err("%s: error bitlen\n", __func__);
+ return -EINVAL;
+ }
+
+ /* spi core will call back, No need to call repeatedly */
+ //spifc_claim_bus(dev);
+ spifc_set_speed(bus, slave->max_hz);
+ spifc_set_mode(bus, slave->mode);
+ if (flags & SPI_XFER_BEGIN) {
+ if (flags & SPI_XFER_END) {
+ buf = (u8 *)dout;
+ if (!buf || len > 5) {
+ pr_err("%s: error command\n", __func__);
+ ret = -EINVAL;
+ } else {
+ spifc_user_cmd(priv, buf[0], &buf[1], len - 1);
+ /* save the command for next xfer dual/quad setting */
+ priv->cmd = buf[0];
+ }
+ } else {
+ buf = (u8 *)dout;
+ priv->save_cmd = buf[0];
+ priv->save_addr_len = len - 1;
+ priv->save_addr = 0;
+ if (priv->save_addr_len) {
+ for (i = 0; i < priv->save_addr_len; i++) {
+ priv->save_addr = priv->save_addr << 8;
+ priv->save_addr |= buf[i + 1];
+ }
+ }
+ else
+ priv->save_addr = 0;
+
+ priv->cmd = buf[0];
+ }
+ } else if (dout && priv->cmd) {
+ buf = (u8 *)dout;
+ priv->loop = 0;
+ spifc_set_tx_op_mode(priv, slave->mode, priv->cmd);
+ while (len > 0) {
+ lening = min_t(size_t, 512, len);
+ ret = spifc_user_cmd_dout(priv, buf, lening, flags);
+ if (ret)
+ break;
+ buf += lening;
+ len -= lening;
+ priv->save_addr += lening;
+ priv->loop++;
+ }
+ } else if (din && priv->cmd) {
+ buf = (u8 *)din;
+ spifc_set_rx_op_mode(priv, slave->mode, priv->cmd);
+ while (len > 0) {
+ lening = min_t(size_t, 512, len);
+ ret = spifc_user_cmd_din(priv, buf, lening, flags);
+ if (ret)
+ break;
+ buf += lening;
+ len -= lening;
+ priv->save_addr = priv->save_addr >> 8;
+ priv->save_addr += lening;
+ priv->save_addr = priv->save_addr << 8;
+ }
+ }
+ if (ret || flags & SPI_XFER_END) {
+ priv->cmd = 0;
+ }
+ return ret;
+}
+
+static int spifc_probe(struct udevice *bus)
+{
+ struct spifc_priv *priv = dev_get_priv(bus);
+ int ret = 0;
+
+ /* In consideration of compatibility with other storage media,
+ * reset pinmux to spifc here.
+ */
+ ret = pinctrl_select_state(bus, "default");
+ if (ret) {
+ pr_err("select state %s failed\n", "default");
+ return ret;
+ }
+
+#if defined(CONFIG_CLK) && (CONFIG_CLK)
+ ret = clk_get_by_name(bus, "fclk_source", &priv->spifc_source);
+ if (ret) {
+ pr_err("can't get clk fclk_source!\n");
+ return ret;
+ }
+
+ ret = clk_get_by_name(bus, "spifc_mux", &priv->spifc_mux);
+ if (ret) {
+ pr_err("can't get clk spifc_mux!\n");
+ return ret;
+ }
+
+ ret = clk_get_by_name(bus, "spifc_div", &priv->spifc_div);
+ if (ret) {
+ pr_err("can't get clk spifc_div!\n");
+ return ret;
+ }
+
+ ret = clk_get_by_name(bus, "spifc_gate", &priv->spifc_gate);
+ if (ret) {
+ pr_err("can't get clk spifc_gate!\n");
+ return ret;
+ }
+
+ ret = clk_get_by_name(bus, "spifc_xtal_gate", &priv->spifc_xtal_gate);
+ if (ret) {
+ pr_err("can't get clk spifc_xtal_gate!\n");
+ return ret;
+ }
+
+ /* Do not use xtal */
+ ret = clk_disable(&priv->spifc_xtal_gate);
+ if (ret) {
+ pr_err("disable xtal_gate fail\n");
+ return ret;
+ }
+
+ ret = clk_set_parent(&priv->spifc_mux, &priv->spifc_source);
+ if (ret) {
+ pr_err("can't set clk parent!\n");
+ return ret;
+ }
+
+ ret = clk_set_rate(&priv->spifc_div, SPIFC_DEFAULT_SPEED);
+ if (ret) {
+ pr_err("failed to set rate to 24M\n");
+ return ret;
+ }
+
+ ret = clk_enable(&priv->spifc_gate);
+ if (ret) {
+ pr_err("enable clk fail\n");
+ return ret;
+ }
+#endif
+ spifc_init();
+
+ return ret;
+}
+
+static int spifc_ofdata_to_platdata(struct udevice *bus)
+{
+ struct spifc_platdata *plat = dev_get_platdata(bus);
+ const void *blob = gd->fdt_blob;
+ int node = dev_of_offset(bus);
+
+ plat->speed = fdtdec_get_uint(blob, node,
+ "max-frequency",
+ 40000000);
+ plat->max_cs = fdtdec_get_uint(blob, node,
+ "max-cs",
+ 2);
+ plat->mode = 0;
+ printf("spifc freq %d reg %p\n", plat->speed, (void *)plat->reg);
+ return 0;
+}
+
+static const struct udevice_id spifc_ids[] = {
+ { .compatible = "amlogic,spifc" },
+ { }
+};
+
+static struct dm_spi_ops spifc_ops = {
+ .claim_bus = spifc_claim_bus,
+ .release_bus = spifc_release_bus,
+ .xfer = spifc_xfer,
+ .set_speed = spifc_set_speed,
+ .set_mode = spifc_set_mode,
+ .set_wordlen = spifc_set_wordlen,
+};
+
+U_BOOT_DRIVER(spifc) = {
+ .name = "spifc",
+ .id = UCLASS_SPI,
+ .of_match = spifc_ids,
+ .ofdata_to_platdata = spifc_ofdata_to_platdata,
+ .platdata_auto_alloc_size = sizeof(struct spifc_platdata),
+ .priv_auto_alloc_size = sizeof(struct spifc_priv),
+ .per_child_auto_alloc_size = sizeof(struct spi_slave),
+ .ops = &spifc_ops,
+ .probe = spifc_probe,
+};
diff --git a/drivers/spmi/Kconfig b/drivers/spmi/Kconfig
index fb3c1e1..ab4878e 100644
--- a/drivers/spmi/Kconfig
+++ b/drivers/spmi/Kconfig
@@ -21,4 +21,3 @@
Demo SPMI bus implementation. Emulates part of PM8916 as single
slave (0) on bus. It has 4 GPIO peripherals, pid 0xC0-0xC3.
endmenu
-
diff --git a/drivers/sysreset/Kconfig b/drivers/sysreset/Kconfig
index de75266..8ce3e2e 100644
--- a/drivers/sysreset/Kconfig
+++ b/drivers/sysreset/Kconfig
@@ -70,4 +70,3 @@
Reboot support for NXP MPC83xx SoCs.
endmenu
-
diff --git a/drivers/tee/Kconfig b/drivers/tee/Kconfig
index ac40132..5c0c890 100644
--- a/drivers/tee/Kconfig
+++ b/drivers/tee/Kconfig
@@ -33,4 +33,3 @@
endmenu
endif
-
diff --git a/drivers/tee/optee/Kconfig b/drivers/tee/optee/Kconfig
index b5a3791..d489834 100644
--- a/drivers/tee/optee/Kconfig
+++ b/drivers/tee/optee/Kconfig
@@ -25,4 +25,3 @@
endmenu
endif
-
diff --git a/drivers/thermal/Kconfig b/drivers/thermal/Kconfig
index 37470a0..a71b9be 100644
--- a/drivers/thermal/Kconfig
+++ b/drivers/thermal/Kconfig
@@ -24,4 +24,3 @@
The driver supports reading CPU temperature.
endif # if DM_THERMAL
-
diff --git a/drivers/timer/Kconfig b/drivers/timer/Kconfig
index 6508f47..df37a79 100644
--- a/drivers/timer/Kconfig
+++ b/drivers/timer/Kconfig
@@ -175,4 +175,3 @@
MediaTek devices.
endmenu
-
diff --git a/drivers/tpm/Kconfig b/drivers/tpm/Kconfig
index e5634f9..94629df 100644
--- a/drivers/tpm/Kconfig
+++ b/drivers/tpm/Kconfig
@@ -148,4 +148,3 @@
endif # TPM_V2
endmenu
-
diff --git a/drivers/usb/Kconfig b/drivers/usb/Kconfig
index 1baa9b2..b542d66 100644
--- a/drivers/usb/Kconfig
+++ b/drivers/usb/Kconfig
@@ -125,8 +125,10 @@
source "drivers/usb/gadget/Kconfig"
source "drivers/usb/gadget/v2_burning/Kconfig"
+source "drivers/usb/gadget/v3_burning/Kconfig"
source "drivers/usb/eth/Kconfig"
+source "drivers/usb/roles/Kconfig"
+source "drivers/usb/typec/Kconfig"
endif
-
diff --git a/drivers/usb/dwc3/Kconfig b/drivers/usb/dwc3/Kconfig
index 9ce1147..bbd8105 100644
--- a/drivers/usb/dwc3/Kconfig
+++ b/drivers/usb/dwc3/Kconfig
@@ -69,4 +69,3 @@
endmenu
endif
-
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
index 56e2a04..64ec417 100644
--- a/drivers/usb/dwc3/core.c
+++ b/drivers/usb/dwc3/core.c
@@ -120,8 +120,10 @@
evt->length = length;
evt->buf = dma_alloc_coherent(length,
(unsigned long *)&evt->dma);
- if (!evt->buf)
+ if (!evt->buf) {
+ devm_kfree((struct udevice *)dwc->dev, evt);
return ERR_PTR(-ENOMEM);
+ }
dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
@@ -812,6 +814,7 @@
if (ret && ret != -ENOENT) {
pr_err("Failed to get USB PHY%d for %s\n",
i, dev->name);
+ devm_kfree(dev, usb_phys);
return ret;
}
}
diff --git a/drivers/usb/emul/Kconfig b/drivers/usb/emul/Kconfig
index 949ae9d..ae1ab23 100644
--- a/drivers/usb/emul/Kconfig
+++ b/drivers/usb/emul/Kconfig
@@ -6,4 +6,3 @@
to use device emulators instead. This allows testing of the USB
stack on sandbox without needing a real device, or any host machine
USB resources.
-
diff --git a/drivers/usb/eth/Kconfig b/drivers/usb/eth/Kconfig
index 043f2e7..2f6bfa8 100644
--- a/drivers/usb/eth/Kconfig
+++ b/drivers/usb/eth/Kconfig
@@ -63,4 +63,3 @@
Ethernet Devices.
endif
-
diff --git a/drivers/usb/gadget/Kconfig b/drivers/usb/gadget/Kconfig
index a6b3fa6..785ffe8 100644
--- a/drivers/usb/gadget/Kconfig
+++ b/drivers/usb/gadget/Kconfig
@@ -39,6 +39,7 @@
config USB_GADGET_MANUFACTURER
string "Vendor name of the USB device"
default "Allwinner Technology" if ARCH_SUNXI
+ default "Amlogic Inc." if ARCH_MESON
default "U-Boot"
help
Vendor name of the USB device emulated, reported to the host device.
@@ -47,6 +48,7 @@
config USB_GADGET_VENDOR_NUM
hex "Vendor ID of the USB device"
default 0x1f3a if ARCH_SUNXI
+ default 0x1b8e if ARCH_MESON
default 0x0
help
Vendor ID of the USB device emulated, reported to the host device.
@@ -56,6 +58,7 @@
config USB_GADGET_PRODUCT_NUM
hex "Product ID of the USB device"
default 0x1010 if ARCH_SUNXI
+ default 0xc004 if ARCH_MESON
default 0x0
help
Product ID of the USB device emulated, reported to the host device.
@@ -127,6 +130,9 @@
bool "fastboot usb driver support"
select USB_DEVICE_V2
+config USB_GADGET_CRG
+ bool "fastboot corgine usb driver support"
+
config USB_GADGET_DOWNLOAD
bool "Enable USB download gadget"
help
@@ -223,4 +229,3 @@
endif # USB_ETHER
endif # USB_GADGET
-
diff --git a/drivers/usb/gadget/Makefile b/drivers/usb/gadget/Makefile
index 639093f..12b56b7 100644
--- a/drivers/usb/gadget/Makefile
+++ b/drivers/usb/gadget/Makefile
@@ -3,9 +3,13 @@
# (C) Copyright 2000-2007
# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-obj-$(CONFIG_USB_GADGET) += epautoconf.o config.o usbstring.o
+obj-$(CONFIG_USB_GADGET) += epautoconf.o config.o usbstring.o platform.o
obj-$(CONFIG_USB_ETHER) += epautoconf.o config.o usbstring.o
+ifndef CONFIG_USB_GADGET_CRG
obj-$(CONFIG_FASTBOOT_DWC_PCD) += fastboot/dwc_pcd.o fastboot/dwc_pcd_irq.o
+else
+obj-$(CONFIG_USB_GADGET_CRG) += crg_udc.o
+endif
ifdef CONFIG_SPL_BUILD
obj-$(CONFIG_SPL_USB_GADGET) += g_dnl.o
diff --git a/drivers/usb/gadget/composite.c b/drivers/usb/gadget/composite.c
index c7e7623..aedd65c 100644
--- a/drivers/usb/gadget/composite.c
+++ b/drivers/usb/gadget/composite.c
@@ -893,9 +893,10 @@
break;
}
- if (f && f->setup)
+ if (f && f->setup) {
value = f->setup(f, ctrl);
- else {
+ break;
+ } else {
c = cdev->config;
if (c->setup)
value = c->setup(c, ctrl);
diff --git a/drivers/usb/gadget/crg_udc.c b/drivers/usb/gadget/crg_udc.c
new file mode 100644
index 0000000..37d7ecb
--- /dev/null
+++ b/drivers/usb/gadget/crg_udc.c
@@ -0,0 +1,3604 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#define pr_fmt(fmt) "[%lu] " fmt, get_timer(0)
+
+#include <common.h>
+#include <command.h>
+#include <config.h>
+#include <net.h>
+#include <malloc.h>
+#include <asm/byteorder.h>
+#include <linux/errno.h>
+#include <asm/io.h>
+#include <asm/unaligned.h>
+#include <linux/types.h>
+#include <linux/bitops.h>
+#include <asm/dma-mapping.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <usb/crg_udc.h>
+#include <asm/system.h>
+#include <asm/arch/usb.h>
+#include <asm/cache.h>
+
+//#define DEBUG
+//#define debug printf
+//#define printf
+
+//#define XFER_DEBUG
+#ifdef XFER_DEBUG
+#define xdebug(fmt, args...) printf(fmt, ##args)
+#else
+#define xdebug(fmt, args...)
+#endif
+
+//#define PORTSC_DEBUG
+#ifdef PORTSC_DEBUG
+#define pdebug(fmt, args...) printf(fmt, ##args)
+#else
+#define pdebug(fmt, args...)
+#endif
+
+#define DMA_ADDR_INVALID (~(dma_addr_t)0)
+
+#define CRG_ERST_SIZE 1
+#define CRG_EVENT_RING_SIZE 8
+#define CRG_NUM_EP_CX 6
+
+#define TRB_MAX_BUFFER_SIZE 65536
+#define CRGUDC_CONTROL_EP_TD_RING_SIZE 8
+#define CRGUDC_BULK_EP_TD_RING_SIZE 8
+#define CRGUDC_ISOC_EP_TD_RING_SIZE 8
+#define CRGUDC_INT_EP_TD_RING_SIZE 8
+
+//#define U1_TIMEOUT_VAL 0x70
+//#define U2_TIMEOUT_VAL 0x70
+#define U1_TIMEOUT_VAL 0x70
+#define U2_TIMEOUT_VAL 0x70
+
+/*********Feature switches********************/
+#define U12_FORBIDDEN 0
+#define U12_INITIATE_FORBIDDEN 1
+/*********************************************/
+
+enum EP_STATE_E {
+ EP_STATE_DISABLED = 0,
+ EP_STATE_RUNNING = 1,
+ EP_STATE_HALTED = 2,
+ EP_STATE_STOPPED = 3
+};
+
+enum EP_TYPE_E {
+ EP_TYPE_INVALID = 0,
+ EP_TYPE_ISOCH_OUTBOUND,
+ EP_TYPE_BULK_OUTBOUND,
+ EP_TYPE_INTR_OUTBOUND,
+ EP_TYPE_INVALID2,
+ EP_TYPE_ISOCH_INBOUND,
+ EP_TYPE_BULK_INBOUND,
+ EP_TYPE_INTR_INBOUND
+};
+
+enum TRB_TYPE_E {
+ TRB_TYPE_RSVD = 0,
+ TRB_TYPE_XFER_NORMAL,
+ TRB_TYPE_RSVD2,
+ TRB_TYPE_XFER_DATA_STAGE,
+ TRB_TYPE_XFER_STATUS_STAGE,
+ TRB_TYPE_XFER_DATA_ISOCH, /* 5*/
+ TRB_TYPE_LINK,
+ TRB_TYPE_RSVD7,
+ TRB_TYPE_NO_OP,
+
+ TRB_TYPE_EVT_TRANSFER = 32,
+ TRB_TYPE_EVT_CMD_COMPLETION = 33,
+ TRB_TYPE_EVT_PORT_STATUS_CHANGE = 34,
+ TRB_TYPE_EVT_MFINDEX_WRAP = 39,
+ TRB_TYPE_EVT_SETUP_PKT = 40,
+};
+
+/*Table 127*/
+enum TRB_CMPL_CODES_E {
+ CMPL_CODE_INVALID = 0,
+ CMPL_CODE_SUCCESS,
+ CMPL_CODE_DATA_BUFFER_ERR,
+ CMPL_CODE_BABBLE_DETECTED_ERR,
+ CMPL_CODE_USB_TRANS_ERR,
+ CMPL_CODE_TRB_ERR, /*5*/
+ CMPL_CODE_TRB_STALL,
+ CMPL_CODE_INVALID_STREAM_TYPE_ERR = 10,
+ CMPL_CODE_SHORT_PKT = 13,
+ CMPL_CODE_RING_UNDERRUN,
+ CMPL_CODE_RING_OVERRUN, /*15*/
+ CMPL_CODE_EVENT_RING_FULL_ERR = 21,
+ CMPL_CODE_STOPPED = 26,
+ CMPL_CODE_STOPPED_LENGTH_INVALID = 27,
+ CMPL_CODE_ISOCH_BUFFER_OVERRUN = 31,
+ /*192-224 vendor defined error*/
+ CMPL_CODE_PROTOCOL_STALL = 192,
+ CMPL_CODE_SETUP_TAG_MISMATCH = 193,
+ CMPL_CODE_HALTED = 194,
+ CMPL_CODE_HALTED_LENGTH_INVALID = 195,
+ CMPL_CODE_DISABLED = 196,
+ CMPL_CODE_DISABLED_LENGTH_INVALID = 197,
+};
+
+
+struct buffer_info {
+ void *vaddr;
+ dma_addr_t dma;
+ u32 len;
+};
+
+struct transfer_trb_s {
+ __le32 dw0;
+ __le32 dw1;
+
+#define TRB_TRANSFER_LEN_MASK 0x0001FFFF
+#define TRB_TRANSFER_LEN_SHIFT 0
+#define TRB_TD_SIZE_MASK 0x003E0000
+#define TRB_TD_SIZE_SHIFT 17
+#define TRB_INTR_TARGET_MASK 0xFFC00000
+#define TRB_INTR_TARGET_SHIFT 22
+ __le32 dw2;
+
+#define TRB_CYCLE_BIT_MASK 0x00000001
+#define TRB_CYCLE_BIT_SHIFT 0
+#define TRB_LINK_TOGGLE_CYCLE_MASK 0x00000002
+#define TRB_LINK_TOGGLE_CYCLE_SHIFT 1
+#define TRB_INTR_ON_SHORT_PKT_MASK 0x00000004
+#define TRB_INTR_ON_SHORT_PKT_SHIFT 2
+#define TRB_NO_SNOOP_MASK 0x00000008
+#define TRB_NO_SNOOP_SHIFT 3
+#define TRB_CHAIN_BIT_MASK 0x00000010
+#define TRB_CHAIN_BIT_SHIFT 4
+#define TRB_INTR_ON_COMPLETION_MASK 0x00000020
+#define TRB_INTR_ON_COMPLETION_SHIFT 5
+
+#define TRB_APPEND_ZLP_MASK 0x00000080
+#define TRB_APPEND_ZLP_SHIFT 7
+
+#define TRB_BLOCK_EVENT_INT_MASK 0x00000200
+#define TRB_BLOCK_EVENT_INT_SHIFT 9
+#define TRB_TYPE_MASK 0x0000FC00
+#define TRB_TYPE_SHIFT 10
+#define DATA_STAGE_TRB_DIR_MASK 0x00010000
+#define DATA_STAGE_TRB_DIR_SHIFT 16
+#define TRB_SETUP_TAG_MASK 0x00060000
+#define TRB_SETUP_TAG_SHIFT 17
+#define STATUS_STAGE_TRB_STALL_MASK 0x00080000
+#define STATUS_STAGE_TRB_STALL_SHIFT 19
+#define STATUS_STAGE_TRB_SET_ADDR_MASK 0x00100000
+#define STATUS_STAGE_TRB_SET_ADDR_SHIFT 20
+
+
+#define ISOC_TRB_FRAME_ID_MASK 0x7FF00000
+#define ISOC_TRB_FRAME_ID_SHIFT 20
+#define ISOC_TRB_SIA_MASK 0x80000000
+#define ISOC_TRB_SIA_SHIFT 31
+ __le32 dw3;
+};
+
+struct event_trb_s {
+ __le32 dw0;
+ __le32 dw1;
+
+#define EVE_TRB_TRAN_LEN_MASK 0x0001FFFF
+#define EVE_TRB_TRAN_LEN_SHIFT 0
+#define EVE_TRB_COMPL_CODE_MASK 0xFF000000
+#define EVE_TRB_COMPL_CODE_SHIFT 24
+ __le32 dw2;
+
+#define EVE_TRB_CYCLE_BIT_MASK 0x00000001
+#define EVE_TRB_CYCLE_BIT_SHIFT 0
+#define EVE_TRB_TYPE_MASK 0x0000FC00
+#define EVE_TRB_TYPE_SHIFT 10
+#define EVE_TRB_ENDPOINT_ID_MASK 0x001F0000
+#define EVE_TRB_ENDPOINT_ID_SHIFT 16
+#define EVE_TRB_SETUP_TAG_MASK 0x00600000
+#define EVE_TRB_SETUP_TAG_SHIFT 21
+ __le32 dw3;
+};
+
+struct ep_cx_s {
+//#define EP_CX_EP_STATE_MASK 0x00000007
+//#define EP_CX_EP_STATE_SHIFT 0
+
+
+#define EP_CX_LOGICAL_EP_NUM_MASK 0x00000078
+#define EP_CX_LOGICAL_EP_NUM_SHIFT 3
+
+//#define EP_CX_LOGICAL_EP_NUM_MASK 0x0000003c
+//#define EP_CX_LOGICAL_EP_NUM_SHIFT 2
+
+#define EP_CX_INTERVAL_MASK 0x00FF0000
+#define EP_CX_INTERVAL_SHIFT 16
+ __le32 dw0;
+
+#define EP_CX_EP_TYPE_MASK 0x00000038
+#define EP_CX_EP_TYPE_SHIFT 3
+#define EP_CX_MAX_BURST_SIZE_MASK 0x0000FF00
+#define EP_CX_MAX_BURST_SIZE_SHIFT 8
+#define EP_CX_MAX_PACKET_SIZE_MASK 0xFFFF0000
+#define EP_CX_MAX_PACKET_SIZE_SHIFT 16
+ __le32 dw1;
+
+#define EP_CX_DEQ_CYC_STATE_MASK 0x00000001
+#define EP_CX_DEQ_CYC_STATE_SHIFT 0
+#define EP_CX_TR_DQPT_LO_MASK 0xFFFFFFF0
+#define EP_CX_TR_DQPT_LO_SHIFT 4
+ __le32 dw2;
+ __le32 dw3;
+};
+
+struct erst_s {
+ /* 64-bit event ring segment address */
+ __le32 seg_addr_lo;
+ __le32 seg_addr_hi;
+ __le32 seg_size;
+ /* Set to zero */
+ __le32 rsvd;
+};
+
+struct sel_value_s {
+ u16 u2_pel_value;
+ u16 u2_sel_value;
+ u8 u1_pel_value;
+ u8 u1_sel_value;
+};
+
+struct crg_udc_request {
+ struct usb_request usb_req;
+ struct list_head queue;
+ bool mapped;
+ u64 buff_len_left;
+ u32 trbs_needed;
+ struct transfer_trb_s *first_trb;
+ struct transfer_trb_s *last_trb;
+ bool all_trbs_queued;
+ bool short_pkt;
+};
+
+struct crg_udc_ep {
+ struct usb_ep usb_ep;
+
+ struct buffer_info tran_ring_info;
+ struct transfer_trb_s *first_trb;
+ struct transfer_trb_s *last_trb;
+
+ struct transfer_trb_s *enq_pt;
+ struct transfer_trb_s *deq_pt;
+ u8 pcs;
+
+ char name[10];
+ u8 DCI;
+ struct list_head queue;
+ struct crg_udc_request *ep_req;
+ const struct usb_endpoint_descriptor *desc;
+ bool tran_ring_full;
+ struct crg_gadget_dev *crg_udc;
+
+ int ep_state;
+
+ unsigned wedge:1;
+};
+
+#define CRG_RING_NUM 1
+
+struct crg_udc_event {
+ struct buffer_info erst;
+ struct erst_s *p_erst;
+ struct buffer_info event_ring;
+ struct event_trb_s *evt_dq_pt;
+ u8 CCS;
+ struct event_trb_s *evt_seg0_last_trb;
+};
+
+struct crg_setup_packet {
+ struct usb_ctrlrequest usbctrlreq;
+ u16 setup_tag;
+};
+
+#define EP_TOTAL 6
+
+struct usb_gadget_crg {
+ struct usb_ep *ep0;
+ struct usb_ep *epin;
+ struct usb_ep *epout;
+ enum usb_device_speed speed;
+ unsigned is_dualspeed:1;
+ unsigned is_otg:1;
+ unsigned is_a_peripheral:1;
+ unsigned b_hnp_enable:1;
+ unsigned a_hnp_support:1;
+ unsigned a_alt_hnp_support:1;
+ const char *name;
+ void *driver_data;
+ //const struct usb_gadget_ops *ops;
+ struct list_head ep_list; /* of usb_ep */
+ enum usb_device_speed max_speed;
+ //enum usb_device_state state;
+ unsigned quirk_ep_out_aligned_size:1;
+};
+
+
+struct crg_gadget_dev {
+ void __iomem *reg_base;
+ struct crg_uccr *uccr;
+ struct crg_uicr *uicr[CRG_RING_NUM];
+
+ int controller_index;
+
+ struct device dev;
+ struct usb_gadget gadget;
+ struct usb_gadget_driver *gadget_driver;
+
+ int irq;
+
+ struct crg_udc_ep udc_ep[EP_TOTAL];
+ struct buffer_info ep_cx;
+ struct ep_cx_s *p_epcx;
+
+ struct crg_udc_event udc_event[CRG_RING_NUM];
+
+ struct crg_udc_request *status_req;
+ u16 statusbuf;
+ struct sel_value_s sel_value;
+ void (*setup_fn_call_back)(struct crg_gadget_dev *);
+
+#define WAIT_FOR_SETUP 0
+#define SETUP_PKT_PROCESS_IN_PROGRESS 1
+#define DATA_STAGE_XFER 2
+#define DATA_STAGE_RECV 3
+#define STATUS_STAGE_XFER 4
+#define STATUS_STAGE_RECV 5
+ u8 setup_status;
+#define CTRL_REQ_QUEUE_DEPTH 5
+ struct crg_setup_packet ctrl_req_queue[CTRL_REQ_QUEUE_DEPTH];
+ u8 ctrl_req_enq_idx;
+
+ u8 device_state;
+ u8 resume_state;
+ u16 dev_addr;
+ u8 setup_tag;
+ u8 set_tm;
+
+ u32 num_enabled_eps;
+
+ int connected;
+
+ unsigned u2_RWE:1;
+ unsigned feature_u1_enable:1;
+ unsigned feature_u2_enable:1;
+
+ //int setup_tag_mismatch_found;
+ int portsc_on_reconnecting;
+
+};
+
+/*An array should be implemented if we want to support multi
+ * usb device controller
+ */
+static struct crg_gadget_dev crg_udc_dev;
+
+static struct usb_endpoint_descriptor crg_udc_ep0_desc = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = 0,
+ .bmAttributes = USB_ENDPOINT_XFER_CONTROL,
+ .wMaxPacketSize = cpu_to_le16(64),
+};
+
+static int get_ep_state(struct crg_gadget_dev *crg_udc, int DCI)
+{
+ struct crg_udc_ep *udc_ep_ptr;
+
+ if (DCI < 0 || DCI == 1)
+ return -EINVAL;
+
+ udc_ep_ptr = &crg_udc->udc_ep[DCI];
+
+ return udc_ep_ptr->ep_state;
+
+}
+
+
+#define CACHELINE_SIZE CONFIG_SYS_CACHELINE_SIZE
+
+void crg_flush_cache(uintptr_t addr, u32 len)
+{
+ BUG_ON((void *)addr == NULL || len == 0);
+
+ flush_dcache_range(addr & ~(CACHELINE_SIZE - 1),
+ ALIGN(addr + len, CACHELINE_SIZE));
+}
+
+void crg_inval_cache(uintptr_t addr, u32 len)
+{
+ BUG_ON((void *)addr == NULL || len == 0);
+
+ invalidate_dcache_range(addr & ~(CACHELINE_SIZE - 1),
+ ALIGN(addr + len, CACHELINE_SIZE));
+}
+
+
+
+/************command related ops**************************/
+static int crg_issue_command(struct crg_gadget_dev *crg_udc,
+ enum crg_cmd_type type, u32 param0, u32 param1)
+{
+
+ struct crg_uccr *uccr = crg_udc->uccr;
+ u32 status;
+ bool check_complete = false;
+ u32 tmp;
+
+ tmp = reg_read(&uccr->control);
+ if (tmp & CRG_U3DC_CTRL_RUN)
+ check_complete = true;
+
+ if (check_complete) {
+ tmp = reg_read(&uccr->cmd_control);
+ if (tmp & CRG_U3DC_CMD_CTRL_ACTIVE) {
+ printf("%s prev command is not complete!\n", __func__);
+ return -1;
+ }
+ }
+
+ reg_write(&uccr->cmd_param0, param0);
+ reg_write(&uccr->cmd_param1, param1);
+
+
+ /*ignore CMD IOC, in uboot no irq is*/
+ tmp = CRG_U3DC_CMD_CTRL_ACTIVE |
+ CRG_U3DC_CMD_CTRL_TYPE(type);
+ reg_write(&uccr->cmd_control, tmp);
+
+ debug("%s start, type=%d, par0=0x%x, par1=0x%x\n",
+ __func__, type, param0, param1);
+
+#if 1
+
+ if (check_complete) {
+ do {
+ tmp = reg_read(&uccr->cmd_control);
+ } while (tmp & CRG_U3DC_CMD_CTRL_ACTIVE);
+
+ debug("%s successful\n", __func__);
+
+ status = CRG_U3DC_CMD_CTRL_STATUS_GET(tmp);
+ if (status != 0) {
+ debug("%s fail\n", __func__);
+ return -EIO;
+ }
+ }
+#endif
+ debug("%s end\n", __func__);
+
+ return 0;
+}
+
+
+static void setup_link_trb(struct transfer_trb_s *link_trb,
+ bool toggle, ulong next_trb)
+{
+ u32 dw = 0;
+
+ link_trb->dw0 = cpu_to_le32(lower_32_bits(next_trb));
+ link_trb->dw1 = cpu_to_le32(upper_32_bits(next_trb));
+
+ link_trb->dw2 = 0;
+
+ SETF_VAR(TRB_TYPE, dw, TRB_TYPE_LINK);
+ if (toggle)
+ SETF_VAR(TRB_LINK_TOGGLE_CYCLE, dw, 1);
+ else
+ SETF_VAR(TRB_LINK_TOGGLE_CYCLE, dw, 0);
+
+ link_trb->dw3 = cpu_to_le32(dw);
+ crg_flush_cache((uintptr_t)link_trb, sizeof(struct transfer_trb_s));
+}
+
+static dma_addr_t tran_trb_virt_to_dma(struct crg_udc_ep *udc_ep,
+ struct transfer_trb_s *trb)
+{
+ unsigned long offset;
+ int trb_idx;
+ dma_addr_t dma_addr = 0;
+
+ trb_idx = trb - udc_ep->first_trb;
+ if (unlikely(trb_idx < 0))
+ return 0;
+
+ offset = trb_idx * sizeof(*trb);
+ if (unlikely(offset > udc_ep->tran_ring_info.len))
+ return 0;
+ dma_addr = udc_ep->tran_ring_info.dma + offset;
+ return dma_addr;
+}
+
+static struct transfer_trb_s *tran_trb_dma_to_virt(
+ struct crg_udc_ep *udc_ep, dma_addr_t address)
+{
+ unsigned long offset;
+ struct transfer_trb_s *trb_virt;
+
+ if (lower_32_bits(address) & 0xf) {
+ printf("transfer ring dma address incorrect\n");
+ return NULL;
+ }
+
+ offset = address - udc_ep->tran_ring_info.dma;
+ if (unlikely(offset > udc_ep->tran_ring_info.len))
+ return NULL;
+ offset = offset / sizeof(struct transfer_trb_s);
+ trb_virt = udc_ep->first_trb + offset;
+ return trb_virt;
+}
+/* Completes request. Calls gadget completion handler
+ * caller must have acquired spin lock.
+ */
+static void req_done(struct crg_udc_ep *udc_ep,
+ struct crg_udc_request *udc_req, int status)
+{
+// struct crg_gadget_dev *crg_udc = udc_ep->crg_udc;
+ if (likely(udc_req->usb_req.status == -EINPROGRESS))
+ udc_req->usb_req.status = status;
+
+ //list_del_init(&udc_req->queue);
+
+ if (udc_req->mapped) {
+ if (udc_req->usb_req.length) {
+ dma_unmap_single((volatile void *)udc_req->usb_req.dma,
+ udc_req->usb_req.length, usb_endpoint_dir_in(udc_ep->desc)
+ ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+ }
+#define DMA_ADDR_INVALID (~(dma_addr_t)0)
+ udc_req->usb_req.dma = DMA_ADDR_INVALID;
+ udc_req->mapped = 0;
+ }
+
+ if (udc_req->usb_req.complete)
+ udc_req->usb_req.complete(&udc_ep->usb_ep, &udc_req->usb_req);
+}
+
+static void nuke(struct crg_udc_ep *udc_ep, int status)
+{
+ //struct crg_udc_request *req = NULL;
+
+ //while (!list_empty(&udc_ep->queue)) {
+
+ // req = list_entry(udc_ep->queue.next,
+ // struct crg_udc_request,
+ // queue);
+
+ // req_done(udc_ep, req, status);
+ //}
+
+ req_done(udc_ep, udc_ep->ep_req, status);
+
+}
+
+void clear_req_container(struct crg_udc_request *udc_req_ptr)
+{
+ udc_req_ptr->buff_len_left = 0;
+ udc_req_ptr->trbs_needed = 0;
+ udc_req_ptr->all_trbs_queued = 0;
+ udc_req_ptr->first_trb = NULL;
+ udc_req_ptr->last_trb = NULL;
+ udc_req_ptr->short_pkt = 0;
+}
+
+bool is_pointer_less_than(struct transfer_trb_s *a, struct transfer_trb_s *b,
+ struct crg_udc_ep *udc_ep)
+{
+ if ((b > a) && ((udc_ep->enq_pt >= b) || (udc_ep->enq_pt < a)))
+ return true;
+ if ((b < a) && ((udc_ep->enq_pt >= b) && (udc_ep->enq_pt < a)))
+ return true;
+ return false;
+}
+
+/* num_trbs here is the size of the ring. */
+u32 room_on_ring(struct crg_gadget_dev *crg_udc, u32 num_trbs,
+ struct transfer_trb_s *p_ring, struct transfer_trb_s *enq_pt,
+ struct transfer_trb_s *dq_pt)
+{
+ u32 i = 0;
+
+ /* debug("room_on_ring enq_pt = 0x%p, dq_pt = 0x%p", enq_pt, dq_pt); */
+ if (enq_pt == dq_pt) {
+ /* ring is empty */
+ return num_trbs - 1;
+ }
+
+ while (enq_pt != dq_pt) {
+ i++;
+
+ enq_pt++;
+
+ if (GETF(TRB_TYPE, enq_pt->dw3) == TRB_TYPE_LINK)
+ enq_pt = p_ring;
+
+ if (i > num_trbs)
+ break;
+ }
+
+ /* debug("room_on_ring 0x%x\n", i); */
+ return i-1;
+}
+
+static void crg_udc_epcx_setup(struct crg_udc_ep *udc_ep)
+{
+ struct crg_gadget_dev *crg_udc = udc_ep->crg_udc;
+ const struct usb_endpoint_descriptor *desc = udc_ep->desc;
+ //const struct usb_ss_ep_comp_descriptor *comp_desc = udc_ep->comp_desc;
+ u8 DCI = udc_ep->DCI;
+ struct ep_cx_s *epcx = (struct ep_cx_s *)(crg_udc->p_epcx + DCI - 2);
+ enum EP_TYPE_E ep_type;
+ u16 maxburst = 0;
+ u16 maxsize;
+ u32 dw;
+
+ debug("crgudc->p_epcx %p, epcx %p\n", crg_udc->p_epcx, epcx);
+ debug("DCI %d, sizeof ep_cx %ld\n", DCI, sizeof(struct ep_cx_s));
+ debug("desc epaddr = 0x%x\n", desc->bEndpointAddress);
+
+ /*corigine gadget dir should be opposite to host dir*/
+ if (usb_endpoint_dir_out(desc))
+ ep_type = usb_endpoint_type(desc) + EP_TYPE_INVALID2;
+ else
+ ep_type = usb_endpoint_type(desc);
+
+ maxsize = usb_endpoint_maxp(desc) & 0x07ff; /* D[0:10] */
+
+ maxburst = (usb_endpoint_maxp(desc) >> 11) & 0x3;
+ if (maxburst == 0x3) {
+ printf("invalid maxburst\n");
+ maxburst = 0x2; /* really need ? */
+ }
+
+ /* fill ep_dw0 */
+ dw = 0;
+ SETF_VAR(EP_CX_LOGICAL_EP_NUM, dw, udc_ep->DCI / 2);
+ SETF_VAR(EP_CX_INTERVAL, dw, desc->bInterval);
+ //SETF_VAR(EP_CX_MULT, dw, mult);
+
+ epcx->dw0 = cpu_to_le32(dw);
+
+ /* fill ep_dw1 */
+ dw = 0;
+ SETF_VAR(EP_CX_EP_TYPE, dw, ep_type);
+ SETF_VAR(EP_CX_MAX_PACKET_SIZE, dw, maxsize);
+ SETF_VAR(EP_CX_MAX_BURST_SIZE, dw, maxburst);
+ epcx->dw1 = cpu_to_le32(dw);
+
+ /* fill ep_dw2 */
+ dw = lower_32_bits(udc_ep->tran_ring_info.dma) & EP_CX_TR_DQPT_LO_MASK;
+ SETF_VAR(EP_CX_DEQ_CYC_STATE, dw, udc_ep->pcs);
+ epcx->dw2 = cpu_to_le32(dw);
+
+ /* fill ep_dw3 */
+ dw = upper_32_bits(udc_ep->tran_ring_info.dma);
+ epcx->dw3 = cpu_to_le32(dw);
+
+ crg_flush_cache((uintptr_t)epcx, sizeof(struct ep_cx_s));
+}
+
+
+
+
+static void crg_udc_epcx_update_dqptr(struct crg_udc_ep *udc_ep)
+{
+ struct crg_gadget_dev *crg_udc = udc_ep->crg_udc;
+ u8 DCI = udc_ep->DCI;
+ struct ep_cx_s *epcx = (struct ep_cx_s *)(crg_udc->p_epcx + DCI - 2);
+ u32 dw;
+ dma_addr_t dqptaddr;
+ u32 cmd_param0;
+
+ if (DCI == 0) {
+ printf("%s Cannot update dqptr for ep0\n", __func__);
+ return;
+ }
+
+ dqptaddr = tran_trb_virt_to_dma(udc_ep, udc_ep->deq_pt);
+ //dqptaddr = (dma_addr_t)(u64)udc_ep->deq_pt;
+ /* fill ep_dw2 */
+ dw = lower_32_bits(dqptaddr) & EP_CX_TR_DQPT_LO_MASK;
+ SETF_VAR(EP_CX_DEQ_CYC_STATE, dw, udc_ep->pcs);
+ epcx->dw2 = cpu_to_le32(dw);
+
+ /* fill ep_dw3 */
+ dw = upper_32_bits(dqptaddr);
+ epcx->dw3 = cpu_to_le32(dw);
+
+ cmd_param0 = (0x1 << udc_ep->DCI);
+
+ crg_flush_cache((uintptr_t)epcx, sizeof(struct ep_cx_s));
+
+ crg_issue_command(crg_udc, CRG_CMD_SET_TR_DQPTR, cmd_param0, 0);
+
+}
+
+void setup_status_trb(struct crg_gadget_dev *crg_udc,
+ struct transfer_trb_s *p_trb,
+ struct usb_request *usb_req, u8 pcs, u8 set_addr, u8 stall)
+{
+
+ u32 tmp, dir = 0;
+
+ /* There are some cases where seutp_status_trb() is called with
+ * usb_req set to NULL.
+ */
+ if (usb_req != NULL) {
+ p_trb->dw0 = lower_32_bits(usb_req->dma);
+ p_trb->dw1 = upper_32_bits(usb_req->dma);
+ }
+
+ //debug("data_buf_ptr_lo = 0x%x, data_buf_ptr_hi = 0x%x\n",
+ // p_trb->dw0, p_trb->dw1);
+
+ tmp = 0;
+ SETF_VAR(TRB_INTR_TARGET, tmp, 0);
+ p_trb->dw2 = tmp;
+
+ tmp = 0;
+ SETF_VAR(TRB_CYCLE_BIT, tmp, pcs);
+ SETF_VAR(TRB_INTR_ON_COMPLETION, tmp, 1);
+ SETF_VAR(TRB_TYPE, tmp, TRB_TYPE_XFER_STATUS_STAGE);
+
+ dir = (crg_udc->setup_status == STATUS_STAGE_XFER) ? 0 : 1;
+ SETF_VAR(DATA_STAGE_TRB_DIR, tmp, dir);
+
+ SETF_VAR(TRB_SETUP_TAG, tmp, crg_udc->setup_tag);
+ SETF_VAR(STATUS_STAGE_TRB_STALL, tmp, stall);
+ SETF_VAR(STATUS_STAGE_TRB_SET_ADDR, tmp, set_addr);
+
+ p_trb->dw3 = tmp;
+
+ crg_flush_cache((uintptr_t)p_trb, sizeof(struct transfer_trb_s));
+ //debug("trb_dword2 = 0x%x, trb_dword3 = 0x%x\n",
+ // p_trb->dw2, p_trb->dw3);
+
+}
+
+
+void knock_doorbell(struct crg_gadget_dev *crg_udc, int DCI)
+{
+ u32 tmp;
+ struct crg_uccr *uccr;
+
+ uccr = crg_udc->uccr;
+
+ tmp = CRG_U3DC_DB_TARGET(DCI);
+ reg_write(&uccr->doorbell, tmp);
+
+}
+
+void setup_datastage_trb(struct crg_gadget_dev *crg_udc,
+ struct transfer_trb_s *p_trb, struct usb_request *usb_req,
+ u8 pcs, u32 num_trb, u32 transfer_length, u32 td_size,
+ u8 IOC, u8 AZP, u8 dir, u8 setup_tag)
+{
+
+ u32 tmp;
+
+ p_trb->dw0 = lower_32_bits(usb_req->dma);
+ p_trb->dw1 = upper_32_bits(usb_req->dma);
+
+ debug("data_buf_ptr_lo = 0x%x, data_buf_ptr_hi = 0x%x\n",
+ p_trb->dw0, p_trb->dw1);
+
+ /* TRB_Transfer_Length
+ *For USB_DIR_OUT, this field is the number of data bytes expected from
+ *xhc. For USB_DIR_IN, this field is the number of data bytes the device
+ *will send.
+ */
+ tmp = 0;
+ SETF_VAR(TRB_TRANSFER_LEN, tmp, transfer_length);
+ SETF_VAR(TRB_TD_SIZE, tmp, td_size);
+ SETF_VAR(TRB_INTR_TARGET, tmp, 0);
+ p_trb->dw2 = tmp;
+
+ tmp = 0;
+ SETF_VAR(TRB_CYCLE_BIT, tmp, pcs);
+ SETF_VAR(TRB_INTR_ON_SHORT_PKT, tmp, 1);
+ SETF_VAR(TRB_INTR_ON_COMPLETION, tmp, IOC);
+ SETF_VAR(TRB_TYPE, tmp, TRB_TYPE_XFER_DATA_STAGE);
+ SETF_VAR(TRB_APPEND_ZLP, tmp, AZP);
+ SETF_VAR(DATA_STAGE_TRB_DIR, tmp, dir);
+ SETF_VAR(TRB_SETUP_TAG, tmp, setup_tag);
+
+ p_trb->dw3 = tmp;
+
+ crg_flush_cache((uintptr_t)p_trb, sizeof(struct transfer_trb_s));
+ debug("trb_dword2 = 0x%x, trb_dword3 = 0x%x\n",
+ p_trb->dw2, p_trb->dw3);
+
+}
+
+
+void setup_trb(struct crg_gadget_dev *crg_udc, struct transfer_trb_s *p_trb,
+ struct usb_request *usb_req, u32 xfer_len,
+ dma_addr_t xfer_buf_addr, u8 td_size, u8 pcs,
+ u8 trb_type, u8 short_pkt, u8 chain_bit,
+ u8 intr_on_compl, bool b_setup_stage, u8 usb_dir,
+ bool b_isoc, u8 tlb_pc, u16 frame_i_d, u8 SIA, u8 AZP)
+{
+ u32 tmp;
+
+ p_trb->dw0 = lower_32_bits(xfer_buf_addr);
+ p_trb->dw1 = upper_32_bits(xfer_buf_addr);
+
+ //debug("data_buf_ptr_lo = 0x%x, data_buf_ptr_hi = 0x%x\n",
+ // p_trb->dw0, p_trb->dw1);
+
+ tmp = 0;
+ SETF_VAR(TRB_TRANSFER_LEN, tmp, xfer_len);
+ SETF_VAR(TRB_TD_SIZE, tmp, td_size);
+ SETF_VAR(TRB_INTR_TARGET, tmp, 0);
+
+ p_trb->dw2 = tmp;
+
+ tmp = 0;
+ SETF_VAR(TRB_CYCLE_BIT, tmp, pcs);
+ SETF_VAR(TRB_INTR_ON_SHORT_PKT, tmp, short_pkt);
+ SETF_VAR(TRB_CHAIN_BIT, tmp, chain_bit);
+ SETF_VAR(TRB_INTR_ON_COMPLETION, tmp, intr_on_compl);
+ SETF_VAR(TRB_APPEND_ZLP, tmp, AZP);
+ SETF_VAR(TRB_TYPE, tmp, trb_type);
+
+ if (b_setup_stage)
+ SETF_VAR(DATA_STAGE_TRB_DIR, tmp, usb_dir);
+
+ p_trb->dw3 = tmp;
+ crg_flush_cache((uintptr_t)p_trb, sizeof(struct transfer_trb_s));
+ //debug("trb_dword2 = 0x%.8x, trb_dword3 = 0x%.8x\n",
+ // p_trb->dw2, p_trb->dw3);
+}
+
+int crg_udc_queue_trbs(struct crg_udc_ep *udc_ep_ptr,
+ struct crg_udc_request *udc_req_ptr, bool b_isoc,
+ u32 xfer_ring_size,
+ u32 num_trbs_needed, u64 buffer_length)
+{
+ struct crg_gadget_dev *crg_udc = udc_ep_ptr->crg_udc;
+ struct transfer_trb_s *p_xfer_ring = udc_ep_ptr->first_trb;
+ u32 num_trbs_ava = 0;
+ struct usb_request *usb_req = &udc_req_ptr->usb_req;
+ u64 buff_len_temp = 0;
+ u32 i, j = 1;
+ struct transfer_trb_s *enq_pt = udc_ep_ptr->enq_pt;
+ u8 td_size;
+ u8 chain_bit = 1;
+ u8 short_pkt = 0;
+ u8 intr_on_compl = 0;
+ u32 count;
+ bool full_td = true;
+ u32 intr_rate;
+ dma_addr_t trb_buf_addr;
+ bool need_zlp = false;
+
+ //debug("crg_udc_queue_trbs\n");
+
+ if (udc_req_ptr->usb_req.zero == 1 &&
+ udc_req_ptr->usb_req.length != 0 &&
+ ((udc_req_ptr->usb_req.length %
+ udc_ep_ptr->usb_ep.maxpacket) == 0)) {
+ need_zlp = true;
+ }
+
+ td_size = num_trbs_needed;
+
+ num_trbs_ava = room_on_ring(crg_udc, xfer_ring_size, p_xfer_ring,
+ udc_ep_ptr->enq_pt, udc_ep_ptr->deq_pt);
+
+
+ /* trb_buf_addr points to the addr of the buffer that we write in
+ * each TRB. If this function is called to complete the pending TRB
+ * transfers of a previous request, point it to the buffer that is
+ * not transferred, or else point it to the starting address of the
+ * buffer received in usb_request
+ */
+ if (udc_req_ptr->trbs_needed) {
+ /* Here udc_req_ptr->trbs_needed is used to indicate if we
+ * are completing a previous req
+ */
+ trb_buf_addr = usb_req->dma +
+ (usb_req->length - udc_req_ptr->buff_len_left);
+ } else {
+ trb_buf_addr = usb_req->dma;
+ }
+
+
+ if (num_trbs_ava >= num_trbs_needed)
+ count = num_trbs_needed;
+ else {
+ /* always keep one trb for zlp. */
+ count = num_trbs_ava;
+ full_td = false;
+ xdebug("TRB Ring Full. Avail: 0x%x Req: 0x%x\n",
+ num_trbs_ava, num_trbs_needed);
+ udc_ep_ptr->tran_ring_full = true;
+
+ /*xyl: if there is still some trb not queued,
+ *it means last queued
+ *trb is not the last trb of TD, so no need zlp
+ */
+ need_zlp = false;
+ }
+
+ //debug("queue_trbs count = 0x%x\n", count);
+ for (i = 0; i < count; i++) {
+ if (buffer_length > TRB_MAX_BUFFER_SIZE)
+ buff_len_temp = TRB_MAX_BUFFER_SIZE;
+ else
+ buff_len_temp = buffer_length;
+
+ buffer_length -= buff_len_temp;
+
+ if (usb_endpoint_dir_out(udc_ep_ptr->desc))
+ short_pkt = 1;
+
+ if (buffer_length == 0) {
+ chain_bit = 0;
+ intr_on_compl = 1;
+ udc_req_ptr->all_trbs_queued = 1;
+ }
+
+#define BULK_EP_INTERRUPT_RATE 5
+ intr_rate = BULK_EP_INTERRUPT_RATE;
+
+ if ((!full_td) && (j == intr_rate)) {
+ intr_on_compl = 1;
+ j = 0;
+ }
+
+ u8 pcs = udc_ep_ptr->pcs;
+
+ //if (udc_ep_ptr->comp_desc
+ //&& usb_ss_max_streams(udc_ep_ptr->comp_desc)) {
+ // printf("%s don't do bulk stream\n", __func__);
+ //} else {
+ if (udc_req_ptr->all_trbs_queued) {
+ /*it is the last trb of TD,
+ * so consider zlp
+ */
+ u8 AZP = 0;
+ AZP = (need_zlp ? 1 : 0);
+ setup_trb(crg_udc, enq_pt, usb_req,
+ buff_len_temp, trb_buf_addr,
+ td_size-1, pcs,
+ TRB_TYPE_XFER_NORMAL, short_pkt,
+ chain_bit, intr_on_compl,
+ 0, 0, 0, 0, 0, 0, AZP);
+
+ } else {
+ setup_trb(crg_udc, enq_pt, usb_req,
+ buff_len_temp, trb_buf_addr,
+ td_size-1, pcs,
+ TRB_TYPE_XFER_NORMAL, short_pkt,
+ chain_bit, intr_on_compl,
+ 0, 0, 0, 0, 0, 0, 0);
+ }
+ //}
+ trb_buf_addr += buff_len_temp;
+ td_size--;
+ enq_pt++;
+ j++;
+ if (GETF(TRB_TYPE, enq_pt->dw3) == TRB_TYPE_LINK) {
+ if (GETF(TRB_LINK_TOGGLE_CYCLE,
+ enq_pt->dw3)) {
+
+ SETF_VAR(TRB_CYCLE_BIT,
+ enq_pt->dw3, udc_ep_ptr->pcs);
+ udc_ep_ptr->pcs ^= 0x1;
+ crg_flush_cache((uintptr_t)enq_pt, sizeof(struct transfer_trb_s));
+ enq_pt = udc_ep_ptr->first_trb;
+ }
+ }
+ }
+
+ if (!udc_req_ptr->trbs_needed)
+ udc_req_ptr->first_trb = udc_ep_ptr->enq_pt;
+ udc_ep_ptr->enq_pt = enq_pt;
+ udc_req_ptr->buff_len_left = buffer_length;
+ udc_req_ptr->trbs_needed = td_size;
+
+
+ if (udc_req_ptr->buff_len_left == 0) {
+ /* It is actually last trb of a request plus 1 */
+ if (udc_ep_ptr->enq_pt == udc_ep_ptr->first_trb)
+ udc_req_ptr->last_trb = udc_ep_ptr->last_trb - 1;
+ else
+ udc_req_ptr->last_trb = udc_ep_ptr->enq_pt - 1;
+ }
+
+ return 0;
+}
+
+
+
+int crg_udc_queue_ctrl(struct crg_udc_ep *udc_ep_ptr,
+ struct crg_udc_request *udc_req_ptr, u32 num_of_trbs_needed)
+{
+ struct crg_gadget_dev *crg_udc = udc_ep_ptr->crg_udc;
+ u8 ep_state;
+ struct transfer_trb_s *enq_pt = udc_ep_ptr->enq_pt;
+ struct transfer_trb_s *dq_pt = udc_ep_ptr->deq_pt;
+ struct usb_request *usb_req = &udc_req_ptr->usb_req;
+ struct transfer_trb_s *p_trb;
+ u32 transfer_length;
+ u32 td_size = 0;
+ u8 IOC;
+ u8 AZP;
+ u8 dir = 0;
+ u8 setup_tag = crg_udc->setup_tag;
+
+ ep_state = get_ep_state(crg_udc, 0);
+
+ //debug("num_of_trbs_needed = 0x%x\n", num_of_trbs_needed);
+
+ /* Need to queue the request even ep is paused or halted */
+ if (ep_state != EP_STATE_RUNNING) {
+ debug("EP State = 0x%x\n", ep_state);
+ return -EINVAL;
+ }
+
+// if (list_empty(&udc_ep_ptr->queue)) {
+ /* For control endpoint, we can handle one setup request at a
+ * time. so if there are TD pending in the transfer ring.
+ * wait for the sequence number error event. Then put the new
+ * request to tranfer ring
+ */
+ if (enq_pt == dq_pt) {
+ u32 tmp = 0, i;
+ bool need_zlp = false;
+
+ debug("Setup Data Stage TRBs\n");
+ /* Transfer ring is empty
+ * setup data stage TRBs
+ */
+ udc_req_ptr->first_trb = udc_ep_ptr->enq_pt;
+
+ if (crg_udc->setup_status == DATA_STAGE_XFER)
+ dir = 0;
+ else if (crg_udc->setup_status == DATA_STAGE_RECV)
+ dir = 1;
+ else
+ debug("unexpected setup_status!%d\n",
+ crg_udc->setup_status);
+
+ if (udc_req_ptr->usb_req.zero == 1 &&
+ udc_req_ptr->usb_req.length != 0 &&
+ ((udc_req_ptr->usb_req.length %
+ udc_ep_ptr->usb_ep.maxpacket) == 0))
+ need_zlp = true;
+
+ debug("dir=%d, enq_pt=0x%p\n", dir, enq_pt);
+
+ for (i = 0; i < num_of_trbs_needed; i++) {
+ p_trb = enq_pt;
+ if (i < (num_of_trbs_needed - 1)) {
+ transfer_length = TRB_MAX_BUFFER_SIZE;
+ IOC = 0;
+ AZP = 0;
+ } else {
+ tmp = TRB_MAX_BUFFER_SIZE * i;
+ transfer_length = (u32)usb_req->length
+ - tmp;
+
+ IOC = 1;
+ AZP = (need_zlp ? 1 : 0);
+ }
+
+ debug("tx_len = 0x%x, tmp = 0x%x\n",
+ transfer_length, tmp);
+
+ setup_datastage_trb(crg_udc, p_trb, usb_req,
+ udc_ep_ptr->pcs, i, transfer_length,
+ td_size, IOC, AZP, dir, setup_tag);
+ udc_req_ptr->all_trbs_queued = 1;
+ enq_pt++;
+
+ if (GETF(TRB_TYPE, enq_pt->dw3) ==
+ TRB_TYPE_LINK) {
+ if (GETF(TRB_LINK_TOGGLE_CYCLE,
+ enq_pt->dw3)) {
+
+ SETF_VAR(TRB_CYCLE_BIT,
+ enq_pt->dw3,
+ udc_ep_ptr->pcs);
+ udc_ep_ptr->pcs ^= 0x1;
+ }
+ crg_flush_cache((uintptr_t)enq_pt, sizeof(struct transfer_trb_s));
+ enq_pt = udc_ep_ptr->first_trb;
+ }
+ }
+
+ udc_ep_ptr->enq_pt = enq_pt;
+
+ tmp = 0;
+
+ //debug("DB register 0x%x\n", tmp);
+ //tmp = CRG_U3DC_DB_TARGET(0);
+ //reg_write(&uccr->doorbell, tmp);
+ knock_doorbell(crg_udc, 0);
+
+ if (udc_ep_ptr->enq_pt == udc_ep_ptr->first_trb)
+ udc_req_ptr->last_trb =
+ udc_ep_ptr->last_trb - 1;
+ else
+ udc_req_ptr->last_trb = udc_ep_ptr->enq_pt - 1;
+ } else {
+ /* we process one setup request at a time, so ring
+ * should already be empty.
+ */
+ printf("Eq = 0x%p != Dq = 0x%p\n", enq_pt, dq_pt);
+ /* Assert() */
+ }
+// } else {
+// printf("udc_ep_ptr->queue not empty\n");
+// /* New setup packet came
+// * Drop the this req..
+// */
+// return -EINVAL;
+// }
+
+ return 0;
+}
+
+void build_ep0_status(struct crg_udc_ep *udc_ep_ptr,
+ bool default_value, u32 status,
+ struct crg_udc_request *udc_req_ptr, u8 set_addr, u8 stall)
+{
+ struct crg_gadget_dev *crg_udc = udc_ep_ptr->crg_udc;
+ struct transfer_trb_s *enq_pt = udc_ep_ptr->enq_pt;
+
+ if (default_value) {
+ udc_req_ptr = crg_udc->status_req;
+ udc_req_ptr->usb_req.length = 0;
+ udc_req_ptr->usb_req.status = status;
+ udc_req_ptr->usb_req.actual = 0;
+ udc_req_ptr->usb_req.complete = NULL;
+ } else {
+ udc_req_ptr->usb_req.status = status;
+ udc_req_ptr->usb_req.actual = 0;
+ }
+
+ setup_status_trb(crg_udc, enq_pt, &udc_req_ptr->usb_req,
+ udc_ep_ptr->pcs, set_addr, stall);
+
+ enq_pt++;
+
+ /* check if we are at end of trb segment. If so, update
+ * pcs and enq for next segment
+ */
+ if (GETF(TRB_TYPE, enq_pt->dw3) == TRB_TYPE_LINK) {
+ if (GETF(TRB_LINK_TOGGLE_CYCLE, enq_pt->dw3)) {
+ SETF_VAR(TRB_CYCLE_BIT, enq_pt->dw3, udc_ep_ptr->pcs);
+ udc_ep_ptr->pcs ^= 0x1;
+ crg_flush_cache((uintptr_t)enq_pt, sizeof(struct transfer_trb_s));
+ }
+ enq_pt = udc_ep_ptr->first_trb;
+ }
+ udc_ep_ptr->enq_pt = enq_pt;
+
+
+ /* ring the doorbell of ep0*/
+ /* Note: for ep0, streamid field is also used for seqnum.*/
+ //tmp |= DB_STREAMID(nvudc->ctrl_seq_num);
+
+ //debug("doorbell register 0x%x\n", tmp);
+ //tmp = CRG_U3DC_DB_TARGET(0);
+ //reg_write(&uccr->doorbell, tmp);
+ knock_doorbell(crg_udc, 0);
+
+ //list_add_tail(&udc_req_ptr->queue, &udc_ep_ptr->queue);
+
+ debug("%s end\n", __func__);
+}
+
+
+void ep0_req_complete(struct crg_udc_ep *udc_ep_ptr)
+{
+ struct crg_gadget_dev *crg_udc = udc_ep_ptr->crg_udc;
+
+ switch (crg_udc->setup_status) {
+ case DATA_STAGE_XFER:
+ crg_udc->setup_status = STATUS_STAGE_RECV;
+ build_ep0_status(udc_ep_ptr, true, -EINPROGRESS, NULL, 0, 0);
+ break;
+ case DATA_STAGE_RECV:
+ crg_udc->setup_status = STATUS_STAGE_XFER;
+ build_ep0_status(udc_ep_ptr, true, -EINPROGRESS, NULL, 0, 0);
+ break;
+ default:
+ if (crg_udc->setup_fn_call_back)
+ crg_udc->setup_fn_call_back(crg_udc);
+
+ crg_udc->setup_status = WAIT_FOR_SETUP;
+ break;
+ }
+}
+
+
+void handle_cmpl_code_success(struct crg_gadget_dev *crg_udc,
+ struct event_trb_s *event, struct crg_udc_ep *udc_ep_ptr)
+{
+ u64 trb_pt;
+ struct transfer_trb_s *p_trb;
+ struct crg_udc_request *udc_req_ptr;
+ u32 trb_transfer_length;
+
+ trb_pt = (u64)event->dw0 + ((u64)(event->dw1) << 32);
+ p_trb = tran_trb_dma_to_virt(udc_ep_ptr, trb_pt);
+ //p_trb = (struct transfer_trb_s *)trb_pt;
+
+ xdebug("trb_pt = 0x%lx, p_trb = 0x%p\n", (unsigned long)trb_pt, p_trb);
+ xdebug("trb dw0 = 0x%x\n", p_trb->dw0);
+ xdebug("trb dw1 = 0x%x\n", p_trb->dw1);
+ xdebug("trb dw2 = 0x%x\n", p_trb->dw2);
+ xdebug("trb dw3 = 0x%x\n", p_trb->dw3);
+
+
+ if (!GETF(TRB_CHAIN_BIT, p_trb->dw3)) {
+ /* chain bit is not set, which means it
+ * is the end of a TD
+ */
+ //debug("end of TD\n");
+ //udc_req_ptr = list_entry(udc_ep_ptr->queue.next,
+ // struct crg_udc_request, queue);
+ udc_req_ptr = udc_ep_ptr->ep_req;
+
+ //debug("udc_req_ptr = 0x%p\n", udc_req_ptr);
+
+ trb_transfer_length = GETF(EVE_TRB_TRAN_LEN,
+ event->dw2);
+ udc_req_ptr->usb_req.actual = udc_req_ptr->usb_req.length -
+ trb_transfer_length;
+ //debug("Actual data xfer = 0x%x, tx_len = 0x%x\n",
+ // udc_req_ptr->usb_req.actual, trb_transfer_length);
+ if (udc_req_ptr->usb_req.actual != 0)
+ crg_inval_cache((uintptr_t)udc_req_ptr->usb_req.buf, udc_req_ptr->usb_req.actual);
+ req_done(udc_ep_ptr, udc_req_ptr, 0);
+
+ if (!udc_ep_ptr->desc) {
+ debug("udc_ep_ptr->desc is NULL\n");
+ } else {
+ if (usb_endpoint_xfer_control(udc_ep_ptr->desc))
+ ep0_req_complete(udc_ep_ptr);
+ }
+ }
+}
+
+
+void update_dequeue_pt(struct event_trb_s *event, struct crg_udc_ep *udc_ep)
+{
+ u32 deq_pt_lo = event->dw0;
+ u32 deq_pt_hi = event->dw1;
+ u64 dq_pt_addr = (u64)deq_pt_lo + ((u64)deq_pt_hi << 32);
+ struct transfer_trb_s *deq_pt;
+
+ deq_pt = tran_trb_dma_to_virt(udc_ep, dq_pt_addr);
+ //deq_pt = (struct transfer_trb_s *)dq_pt_addr;
+ deq_pt++;
+
+ if (GETF(TRB_TYPE, deq_pt->dw3) == TRB_TYPE_LINK)
+ deq_pt = udc_ep->first_trb;
+
+ udc_ep->deq_pt = deq_pt;
+
+}
+
+void advance_dequeue_pt(struct crg_udc_ep *udc_ep)
+{
+#if 0
+ struct crg_udc_request *udc_req;
+
+ if (!list_empty(&udc_ep->queue)) {
+ xdebug("%s\n", __func__);
+ udc_req = list_entry(udc_ep->queue.next,
+ struct crg_udc_request,
+ queue);
+
+ if (udc_req->first_trb) {
+ xdebug("%s first trb = 0x%p\n",
+ __func__, udc_req->first_trb);
+
+ udc_ep->deq_pt = udc_req->first_trb;
+ } else {
+ xdebug("%s enq_pt = 0x%p\n", __func__, udc_ep->enq_pt);
+ udc_ep->deq_pt = udc_ep->enq_pt;
+ }
+ } else {
+ xdebug("%s empty enq_pt = 0x%p\n", __func__, udc_ep->enq_pt);
+ udc_ep->deq_pt = udc_ep->enq_pt;
+ }
+#endif
+ udc_ep->deq_pt = udc_ep->enq_pt;
+
+}
+#if 0
+bool is_request_dequeued(struct crg_gadget_dev *crg_udc,
+ struct crg_udc_ep *udc_ep, struct event_trb_s *event)
+{
+ struct crg_udc_request *udc_req;
+ u32 trb_pt_lo = event->dw0;
+ u32 trb_pt_hi = event->dw1;
+ u64 trb_addr = (u64)trb_pt_lo + ((u64)trb_pt_hi << 32);
+ struct transfer_trb_s *trb_pt;
+ bool status = true;
+
+ if (udc_ep->DCI == 0)
+ return false;
+
+ trb_pt = tran_trb_dma_to_virt(udc_ep, trb_addr);
+ list_for_each_entry(udc_req, &udc_ep->queue, queue) {
+ if ((trb_pt == udc_req->last_trb) ||
+ (trb_pt == udc_req->first_trb)) {
+ status = false;
+ break;
+ }
+
+ if (is_pointer_less_than(trb_pt, udc_req->last_trb, udc_ep) &&
+ is_pointer_less_than(udc_req->first_trb, trb_pt,
+ udc_ep)) {
+ status = false;
+ break;
+ }
+ }
+
+ return status;
+}
+#endif
+
+int crg_udc_build_td(struct crg_udc_ep *udc_ep_ptr,
+ struct crg_udc_request *udc_req_ptr)
+{
+ int status = 0;
+ struct crg_gadget_dev *crg_udc = udc_ep_ptr->crg_udc;
+ u32 num_trbs_needed;
+ u64 buffer_length;
+ u32 tmp;
+
+ if (udc_req_ptr->trbs_needed) {
+ /* If this is called to complete pending TRB transfers
+ * of previous Request
+ */
+ buffer_length = udc_req_ptr->buff_len_left;
+ num_trbs_needed = udc_req_ptr->trbs_needed;
+ } else {
+ buffer_length = (u64)udc_req_ptr->usb_req.length;
+ num_trbs_needed = (u32)(buffer_length / TRB_MAX_BUFFER_SIZE);
+
+ if ((buffer_length == 0) ||
+ (buffer_length % TRB_MAX_BUFFER_SIZE))
+ num_trbs_needed += 1;
+ }
+
+ if (usb_endpoint_xfer_control(udc_ep_ptr->desc)) {
+ debug("crg_udc_queue_trbs control\n");
+ status = crg_udc_queue_ctrl(udc_ep_ptr,
+ udc_req_ptr, num_trbs_needed);
+ } else if (usb_endpoint_xfer_bulk(udc_ep_ptr->desc)) {
+ /* debug("crg_udc_queue_trbs bulk\n"); */
+ status = crg_udc_queue_trbs(udc_ep_ptr, udc_req_ptr, 0,
+ CRGUDC_BULK_EP_TD_RING_SIZE,
+ num_trbs_needed, buffer_length);
+ tmp = udc_ep_ptr->DCI;
+ tmp = CRG_U3DC_DB_TARGET(tmp);
+ /* debug("DOORBELL = 0x%x\n", tmp); */
+ //reg_write(&uccr->doorbell, tmp);
+ knock_doorbell(crg_udc, udc_ep_ptr->DCI);
+ }
+
+ return status;
+}
+
+/* This function will go through the list of the USB requests for the
+ * given endpoint and schedule any unscheduled trb's to the xfer ring
+ */
+ #if 0
+void queue_pending_trbs(struct crg_udc_ep *udc_ep_ptr)
+{
+ struct crg_udc_request *udc_req_ptr;
+ /* schedule trbs till there arent any pending unscheduled ones
+ * or the ring is full again
+ */
+
+ debug("%s 1\n", __func__);
+ list_for_each_entry(udc_req_ptr, &udc_ep_ptr->queue, queue) {
+ if (udc_req_ptr->all_trbs_queued == 0)
+ crg_udc_build_td(udc_ep_ptr, udc_req_ptr);
+
+ if (udc_ep_ptr->tran_ring_full == true)
+ break;
+ }
+
+ debug("%s 2\n", __func__);
+}
+ #endif
+
+static int set_ep0_halt(struct crg_gadget_dev *crg_udc)
+{
+ struct crg_udc_ep *udc_ep_ptr = &crg_udc->udc_ep[0];
+ int ep_state;
+
+ ep_state = get_ep_state(crg_udc, udc_ep_ptr->DCI);
+ if (ep_state == EP_STATE_HALTED ||
+ ep_state == EP_STATE_DISABLED) {
+ return 0;
+ }
+
+ debug("%s\n", __func__);
+ build_ep0_status(udc_ep_ptr, true, -EINVAL, NULL, 0, 1);
+
+ udc_ep_ptr->ep_state = EP_STATE_HALTED;
+
+ return 0;
+}
+
+static int set_ep_halt(struct crg_gadget_dev *crg_udc, int DCI)
+{
+ struct crg_uccr *uccr = crg_udc->uccr;
+ struct crg_udc_ep *udc_ep_ptr = &crg_udc->udc_ep[DCI];
+ u32 param0;
+ u32 tmp;
+
+ debug("%s DCI=%d !!\n", __func__, DCI);
+
+ if (DCI == 0)
+ return 0;
+
+ if (udc_ep_ptr->ep_state == EP_STATE_DISABLED ||
+ (udc_ep_ptr->ep_state == EP_STATE_HALTED)) {
+ return 0;
+ }
+
+ param0 = (0x1 << DCI);
+ crg_issue_command(crg_udc, CRG_CMD_SET_HALT, param0, 0);
+ do {
+ tmp = reg_read(&uccr->ep_running);
+ } while ((tmp & param0) != 0);
+
+
+ /* clean up the request queue */
+ nuke(udc_ep_ptr, -ECONNREFUSED);
+
+ udc_ep_ptr->deq_pt = udc_ep_ptr->enq_pt;
+ udc_ep_ptr->tran_ring_full = false;
+ udc_ep_ptr->ep_state = EP_STATE_HALTED;
+
+ return 0;
+}
+
+static int ep_halt(struct crg_udc_ep *udc_ep_ptr, int halt, int ignore_wedge)
+{
+ struct crg_gadget_dev *crg_udc = udc_ep_ptr->crg_udc;
+ struct crg_uccr *uccr = crg_udc->uccr;
+ int ep_state;
+ bool reset_seq_only = false;
+ int do_halt;
+ u32 param0;
+ u32 tmp;
+
+ if (!udc_ep_ptr->desc) {
+ printf("NULL desc\n");
+ return -EINVAL;
+ }
+
+ if (udc_ep_ptr->desc->bmAttributes == USB_ENDPOINT_XFER_ISOC) {
+ printf("Isoc ep, halt not supported\n");
+ return -EOPNOTSUPP;
+ }
+
+ if (udc_ep_ptr->DCI == 0)
+ return 0;
+
+ ep_state = get_ep_state(crg_udc, udc_ep_ptr->DCI);
+
+ if (ep_state == EP_STATE_DISABLED)
+ return 0;
+
+ if (ep_state == EP_STATE_HALTED) {
+ if (halt != 0)
+ return 0;
+
+ /* want unhalt an halted ep*/
+ if (udc_ep_ptr->wedge && !ignore_wedge) {
+ do_halt = -1;
+ reset_seq_only = true;
+ } else {
+ do_halt = 0;
+ }
+
+ } else {
+ /*ep state == running or stopped*/
+ if (halt != 0) {
+ /* want halt a running ep*/
+ do_halt = 1;
+ } else {
+ /* reset a running ep*/
+ do_halt = 0;
+ reset_seq_only = true;
+ }
+ }
+
+ param0 = (0x1 << udc_ep_ptr->DCI);
+ if (do_halt == 1) {
+ /* setting ep to halt */
+ debug("HALT EP DCI = %d\n", udc_ep_ptr->DCI);
+ crg_issue_command(crg_udc, CRG_CMD_SET_HALT, param0, 0);
+ do {
+ tmp = reg_read(&uccr->ep_running);
+ } while ((tmp & param0) != 0);
+
+
+ /* clean up the request queue */
+ nuke(udc_ep_ptr, -ECONNREFUSED);
+
+ udc_ep_ptr->deq_pt = udc_ep_ptr->enq_pt;
+ udc_ep_ptr->tran_ring_full = false;
+ udc_ep_ptr->ep_state = EP_STATE_HALTED;
+
+ } else if (do_halt == 0) {
+ /* clearing ep halt state */
+ debug("Clear EP HALT DCI = %d\n", udc_ep_ptr->DCI);
+ /* reset sequence number */
+ crg_issue_command(crg_udc, CRG_CMD_RESET_SEQNUM, param0, 0);
+
+ if (!reset_seq_only) {
+ /* Clear halt for a halted EP.*/
+ /* NOTE: we must CLEAR_HALT first, then SET_TR_DQPTR*/
+ crg_issue_command(crg_udc,
+ CRG_CMD_CLEAR_HALT, param0, 0);
+ crg_udc_epcx_update_dqptr(udc_ep_ptr);
+ }
+
+ udc_ep_ptr->wedge = 0;
+ udc_ep_ptr->ep_state = EP_STATE_RUNNING;
+ /* set endpoint to running state */
+
+ /* clear pause for the endpoint */
+
+ //if (!list_empty(&udc_ep_ptr->queue)) {
+ u32 tmp;
+
+ tmp = udc_ep_ptr->DCI;
+ tmp = CRG_U3DC_DB_TARGET(tmp);
+ //reg_write(&uccr->doorbell, tmp);
+ knock_doorbell(crg_udc, udc_ep_ptr->DCI);
+ debug("DOORBELL = 0x%x\n", tmp);
+ //}
+ } else {
+ /* wedged EP deny CLEAR HALT */
+ debug("wedged EP deny CLEAR HALT DCI = %d\n", udc_ep_ptr->DCI);
+ /* reset sequence number */
+ if (reset_seq_only)
+ crg_issue_command(crg_udc,
+ CRG_CMD_RESET_SEQNUM, param0, 0);
+
+
+ }
+
+ return 0;
+}
+
+
+/************ep related ops*******************************/
+static int crg_udc_ep_disable(struct usb_ep *ep)
+{
+ struct crg_udc_ep *udc_ep;
+ struct crg_gadget_dev *crg_udc;
+ struct ep_cx_s *p_ep_cx;
+ int ep_state;
+ struct crg_uccr *uccr;
+
+ debug("%s\n", __func__);
+
+ if (!ep)
+ return -EINVAL;
+
+ udc_ep = container_of(ep, struct crg_udc_ep, usb_ep);
+ crg_udc = udc_ep->crg_udc;
+
+ if (udc_ep->DCI == 0)
+ return 0;
+
+ uccr = crg_udc->uccr;
+ p_ep_cx = (struct ep_cx_s *)crg_udc->p_epcx + udc_ep->DCI - 2;
+
+ ep_state = get_ep_state(crg_udc, udc_ep->DCI);
+ if (ep_state == EP_STATE_DISABLED) {
+ /* get here if ep is already disabled */
+ return -EINVAL;
+ }
+
+ debug("EPDCI = 0x%x\n", udc_ep->DCI);
+
+
+/*Maybe we need to halt ep before ep disable*/
+ //ep_halt(udc_ep_ptr, 1);
+
+ reg_write(&uccr->ep_enable, 0x1 << udc_ep->DCI);
+
+ /* clean up the request queue */
+ nuke(udc_ep, -ESHUTDOWN);
+
+ /* decrement ep counters */
+ crg_udc->num_enabled_eps--;
+
+ /* release all the memory allocate for the endpoint
+ * dma_free_coherent(nvudc->dev, nvudc->event_ring0.buff_len,
+ * nvudc->event_ring0.virt_addr, nvudc->event_ring0.dma_addr);
+ */
+
+ udc_ep->desc = NULL;
+
+ /* clean up the endpoint context */
+ memset(p_ep_cx, 0, sizeof(struct ep_cx_s));
+
+ debug("num_enabled_eps = %d\n", crg_udc->num_enabled_eps);
+
+ /* If device state was changed to default by port
+ * reset, should not overwrite it again
+ */
+ if ((crg_udc->num_enabled_eps == 0) &&
+ (crg_udc->device_state == USB_STATE_CONFIGURED)) {
+ debug("Device State USB_STATE_CONFIGURED\n");
+ debug("Set Device State to addressed\n");
+ crg_udc->device_state = USB_STATE_ADDRESS;
+
+ /* power_gate(); */
+ }
+
+ udc_ep->ep_state = EP_STATE_DISABLED;
+
+ return 0;
+}
+
+static int crg_udc_ep_enable(struct usb_ep *ep,
+ const struct usb_endpoint_descriptor *desc)
+{
+ struct crg_udc_ep *udc_ep;
+ struct crg_gadget_dev *crg_udc;
+ //struct ep_cx_s *p_ep_cx;
+ u32 param0;
+
+ debug("%s\n", __func__);
+
+ if (!ep || !desc || (desc->bDescriptorType != USB_DT_ENDPOINT))
+ return -EINVAL;
+
+ udc_ep = container_of(ep, struct crg_udc_ep, usb_ep);
+
+
+ debug("%s DCI = %d\n", __func__, udc_ep->DCI);
+
+ /*ep0 is always running*/
+ if (udc_ep->DCI == 0)
+ return 0;
+
+ crg_udc = udc_ep->crg_udc;
+
+ if (!crg_udc->gadget_driver)
+ return -ESHUTDOWN;
+
+
+ /*crg ep context start from ep1*/
+ if (get_ep_state(crg_udc, udc_ep->DCI) != EP_STATE_DISABLED) {
+ debug("%s disable first\n", __func__);
+ crg_udc_ep_disable(ep);
+ }
+
+ udc_ep->desc = desc;
+
+ /* setup endpoint context for regular endpoint
+ * the endpoint context for control endpoint has been
+ * setted up in probe function
+ */
+ if (udc_ep->DCI) {
+ debug("ep_enable udc_ep->DCI = %d\n", udc_ep->DCI);
+
+ /* setup transfer ring */
+ if (!udc_ep->tran_ring_info.vaddr) {
+ dma_addr_t dma;
+ u32 ring_size = 0;
+ void *vaddr;
+ size_t len;
+
+ if (usb_endpoint_xfer_bulk(desc))
+ ring_size = CRGUDC_BULK_EP_TD_RING_SIZE;
+
+ len = ring_size * sizeof(struct transfer_trb_s);
+ vaddr = dma_alloc_coherent(len, (unsigned long *)&dma);
+ if (!vaddr) {
+ printf("failed to allocate trb ring\n");
+ return -ENOMEM;
+ }
+
+ udc_ep->tran_ring_info.vaddr = vaddr;
+ udc_ep->tran_ring_info.dma = dma;
+ udc_ep->tran_ring_info.len = len;
+ udc_ep->first_trb = vaddr;
+ udc_ep->last_trb = udc_ep->first_trb + ring_size - 1;
+ }
+ memset(udc_ep->first_trb, 0, udc_ep->tran_ring_info.len);
+ crg_flush_cache((uintptr_t)udc_ep->first_trb, udc_ep->tran_ring_info.len);
+
+ setup_link_trb(udc_ep->last_trb, true,
+ udc_ep->tran_ring_info.dma);
+
+ udc_ep->enq_pt = udc_ep->first_trb;
+ udc_ep->deq_pt = udc_ep->first_trb;
+ udc_ep->pcs = 1;
+ udc_ep->tran_ring_full = false;
+ crg_udc->num_enabled_eps++;
+ crg_udc_epcx_setup(udc_ep);
+ }
+
+ debug("num_enabled_eps = %d\n", crg_udc->num_enabled_eps);
+
+ param0 = (0x1 << udc_ep->DCI);
+ crg_issue_command(crg_udc, CRG_CMD_CONFIG_EP, param0, 0);
+
+ debug("config ep and start, DCI=%d\n", udc_ep->DCI);
+ if (crg_udc->device_state == USB_STATE_ADDRESS)
+ crg_udc->device_state = USB_STATE_CONFIGURED;
+
+ udc_ep->wedge = 0;
+ udc_ep->ep_state = EP_STATE_RUNNING;
+
+ return 0;
+}
+
+static struct usb_request *
+crg_udc_alloc_request(struct usb_ep *_ep, gfp_t gfp_flags)
+{
+ struct crg_udc_ep *udc_ep;
+ struct crg_udc_request *udc_req_ptr;
+
+ udc_ep = container_of(_ep, struct crg_udc_ep, usb_ep);
+ debug("%s\n", __func__);
+ udc_req_ptr = kzalloc(sizeof(struct crg_udc_request), gfp_flags);
+
+ memset(udc_req_ptr, 0, sizeof(struct crg_udc_request));
+
+ udc_req_ptr->usb_req.dma = DMA_ADDR_INVALID;
+ udc_ep->ep_req = udc_req_ptr;
+
+ return &udc_req_ptr->usb_req;
+}
+
+static void crg_udc_free_request(struct usb_ep *_ep, struct usb_request *_req)
+{
+
+}
+
+static int
+crg_udc_ep_queue(struct usb_ep *_ep, struct usb_request *_req, gfp_t gfp_flags)
+{
+ struct crg_udc_request *udc_req_ptr;
+ struct crg_udc_ep *udc_ep_ptr;
+ struct crg_gadget_dev *crg_udc;
+ int status;
+ int dma_data_dir;
+
+ xdebug("%s\n", __func__);
+
+ if (!_req || !_ep)
+ return -EINVAL;
+
+ udc_req_ptr = container_of(_req, struct crg_udc_request, usb_req);
+ udc_ep_ptr = container_of(_ep, struct crg_udc_ep, usb_ep);
+ crg_udc = udc_ep_ptr->crg_udc;
+
+ if (!udc_ep_ptr->first_trb ||
+ !udc_req_ptr->usb_req.complete ||
+ !udc_req_ptr->usb_req.buf
+ ) {
+ printf("%s, invalid usbrequest\n", __func__);
+ if (!udc_ep_ptr->first_trb)
+ printf("%s, no first_trb\n", __func__);
+
+ if (!udc_req_ptr->usb_req.complete)
+ printf("%s, no complete\n", __func__);
+
+ if (!udc_req_ptr->usb_req.buf)
+ printf("%s, no req buf\n", __func__);
+
+ return -EINVAL;
+ }
+ xdebug("enqueue EPDCI = 0x%x\n", udc_ep_ptr->DCI);
+ xdebug("udc_req buf = 0x%p\n", udc_req_ptr->usb_req.buf);
+
+ if (!udc_ep_ptr->desc) {
+ debug("udc_ep_ptr->Desc is null\n");
+ return -EINVAL;
+ }
+
+ if (udc_req_ptr->usb_req.length != 0)
+ crg_flush_cache((uintptr_t)udc_req_ptr->usb_req.buf, udc_req_ptr->usb_req.length);
+
+ /* Clearing the Values of the UDC_REQUEST container */
+ clear_req_container(udc_req_ptr);
+ udc_req_ptr->mapped = 0;
+
+ if (usb_endpoint_xfer_control(udc_ep_ptr->desc) &&
+ (_req->length == 0)) {
+ crg_udc->setup_status = STATUS_STAGE_XFER;
+ status = -EINPROGRESS;
+ if (udc_req_ptr) {
+ debug("udc_req_ptr = 0x%p\n", udc_req_ptr);
+
+ build_ep0_status(&crg_udc->udc_ep[0], false, status,
+ udc_req_ptr, 0, 0);
+ } else {
+ debug("udc_req_ptr = NULL\n");
+ build_ep0_status(&crg_udc->udc_ep[0],
+ true, status, NULL, 0, 0);
+ }
+ debug("act status request for control endpoint\n");
+ return 0;
+ }
+
+ if (udc_req_ptr->usb_req.dma == DMA_ADDR_INVALID && _req->length != 0) {
+ if (usb_endpoint_xfer_control(udc_ep_ptr->desc)) {
+ if (crg_udc->setup_status == DATA_STAGE_XFER ||
+ crg_udc->setup_status == STATUS_STAGE_XFER)
+ dma_data_dir = DMA_TO_DEVICE;
+
+ if (crg_udc->setup_status == DATA_STAGE_RECV ||
+ crg_udc->setup_status == STATUS_STAGE_RECV)
+ dma_data_dir = DMA_FROM_DEVICE;
+ } else {
+ dma_data_dir = (usb_endpoint_dir_in(udc_ep_ptr->desc)
+ ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
+ }
+ udc_req_ptr->usb_req.dma =
+ dma_map_single(udc_req_ptr->usb_req.buf,
+ udc_req_ptr->usb_req.length,
+ dma_data_dir);
+
+ udc_req_ptr->mapped = 1;
+ }
+
+ udc_req_ptr->usb_req.status = -EINPROGRESS;
+ udc_req_ptr->usb_req.actual = 0;
+
+
+ /* If the transfer ring for this particular end point is full,
+ * then simply queue the request and return
+ */
+ if (udc_ep_ptr->tran_ring_full == true) {
+ status = 0;
+ } else {
+ /* push the request to the transfer ring if possible. */
+ status = crg_udc_build_td(udc_ep_ptr, udc_req_ptr);
+ }
+
+ return status;
+}
+
+static int
+crg_udc_ep_dequeue(struct usb_ep *_ep, struct usb_request *_req)
+{
+ if (!_ep || !_req) {
+ printf("bad argument\n");
+ return -EINVAL;
+ }
+ return 0;
+}
+
+static int crg_udc_ep_set_halt(struct usb_ep *_ep, int value)
+{
+ struct crg_udc_ep *udc_ep_ptr;
+ int status;
+
+ debug("%s\n", __func__);
+
+ if (!_ep)
+ return -EINVAL;
+
+ udc_ep_ptr = container_of(_ep, struct crg_udc_ep, usb_ep);
+
+ status = ep_halt(udc_ep_ptr, value, 1);
+
+ return status;
+}
+
+static struct usb_ep_ops crg_udc_ep_ops = {
+ .enable = crg_udc_ep_enable,
+ .disable = crg_udc_ep_disable,
+ .alloc_request = crg_udc_alloc_request,
+ .free_request = crg_udc_free_request,
+ .queue = crg_udc_ep_queue,
+ .dequeue = crg_udc_ep_dequeue,
+ .set_halt = crg_udc_ep_set_halt,
+};
+
+
+static void crg_ep_struct_setup(struct crg_gadget_dev *crg_udc,
+ uint32_t DCI, const char *name){
+ struct crg_udc_ep *ep = &crg_udc->udc_ep[DCI];
+
+ ep->DCI = DCI;
+
+ if (DCI > 1) {
+ strcpy(ep->name, name);
+ ep->usb_ep.name = ep->name;
+ ep->usb_ep.maxpacket = 512;
+ //ep->usb_ep.max_streams = 16;
+ } else if (DCI == 0) {
+ strcpy(ep->name, "ep0");
+ ep->usb_ep.name = ep->name;
+ ep->usb_ep.maxpacket = 64;
+ } else {
+ return;
+ }
+
+ debug("ep = 0x%p, ep name = %s maxpacket = %d DCI=%d\n",
+ ep, ep->name, ep->usb_ep.maxpacket, ep->DCI);
+ ep->usb_ep.ops = &crg_udc_ep_ops;
+ ep->crg_udc = crg_udc;
+
+ INIT_LIST_HEAD(&ep->queue);
+ if (DCI > 1)
+ list_add_tail(&ep->usb_ep.ep_list, &crg_udc->gadget.ep_list);
+}
+
+
+#define ODB_SIZE_EP0 (512)
+#define ODB_SIZE_VAL_EP0 (3)
+
+#define ODB_SIZE_EPX (2048)
+#define ODB_SIZE_VAL_EPX (5)
+
+struct odb_table {
+ u32 odb_size;
+ u32 field_val;
+};
+
+static struct odb_table odb_array[CRG_NUM_EP_CX/2] = {
+ {ODB_SIZE_EP0, ODB_SIZE_VAL_EP0},
+ {ODB_SIZE_EPX, ODB_SIZE_VAL_EPX},
+ {ODB_SIZE_EPX, ODB_SIZE_VAL_EPX},
+};
+
+/*maxpacketsize should be 2^N * 64 Bytes, we are not checking this now*/
+static void resize_odb(struct crg_gadget_dev *crg_udc,
+ int DCI, int maxpacketsize)
+{
+ u32 tmp;
+ struct crg_uccr *uccr = crg_udc->uccr;
+ u32 offset = 0;
+ u32 blocks;
+ u32 size_val;
+ int i, ep_num;
+ u32 ep_odb_size;
+
+
+ if (DCI != 0)
+ return;
+
+ for (i = 0; i < CRG_NUM_EP_CX / 4; i++) {
+ ep_num = i * 2;
+ ep_odb_size = odb_array[ep_num].odb_size;
+ blocks = ep_odb_size / 64;
+ size_val = odb_array[ep_num].field_val;
+ tmp = (CRG_U3DC_ODBCFG_2N_OFFSET(offset) |
+ CRG_U3DC_ODBCFG_2N_SIZE(size_val));
+ xdebug("epnum=%d, offset=0x%x, size=%d, sizeval=0x%x\n",
+ ep_num, offset, ep_odb_size, size_val);
+ offset += blocks;
+
+ ep_num = i * 2 + 1;
+ ep_odb_size = odb_array[ep_num].odb_size;
+ blocks = ep_odb_size / 64;
+ size_val = odb_array[ep_num].field_val;
+ tmp |= (CRG_U3DC_ODBCFG_2N1_OFFSET(offset) |
+ CRG_U3DC_ODBCFG_2N1_SIZE(size_val));
+ xdebug("epnum=%d, offset=0x%x, size=%d, sizeval=0x%x\n",
+ ep_num, offset, ep_odb_size, size_val);
+ offset += blocks;
+
+ xdebug("%s,tmp=0x%x\n", __func__, tmp);
+
+ reg_write(&uccr->odb_config[i], tmp);
+ tmp = reg_read(&uccr->odb_config[i]);
+ xdebug("%s,odb_cfg[%d]=0x%x\n", __func__, i, tmp);
+ }
+}
+
+static void enable_setup_event(struct crg_gadget_dev *crg_udc)
+{
+ struct crg_uccr *uccr = crg_udc->uccr;
+
+ debug("before setup en config1[0x%p]=0x%x\n",
+ &uccr->config1, reg_read(&uccr->config1));
+
+ setbits_le32(&uccr->config1, CRG_U3DC_CFG1_SETUP_EVENT_EN);
+ debug("update config1[0x%p]=0x%x\n",
+ &uccr->config1, reg_read(&uccr->config1));
+}
+
+int is_event_ring_x_empty(struct crg_gadget_dev *crg_udc, int index)
+{
+ struct event_trb_s *event;
+ struct crg_udc_event *udc_event;
+
+ udc_event = &crg_udc->udc_event[index];
+ if (udc_event->evt_dq_pt) {
+ event = (struct event_trb_s *)udc_event->evt_dq_pt;
+
+ if (GETF(EVE_TRB_CYCLE_BIT, event->dw3) !=
+ udc_event->CCS)
+ return 1;
+ }
+
+ return 0;
+}
+
+int is_event_rings_empty(struct crg_gadget_dev *crg_udc)
+{
+ int i;
+
+ for (i = 0; i < CRG_RING_NUM; i++) {
+ if (!is_event_ring_x_empty(crg_udc, i)) {
+ printf("%s evt ring not empty\n", __func__);
+ return 0;
+ }
+ }
+ return 1;
+}
+
+static int enable_setup(struct crg_gadget_dev *crg_udc)
+{
+ enable_setup_event(crg_udc);
+ crg_udc->device_state = USB_STATE_DEFAULT;
+ crg_udc->setup_status = WAIT_FOR_SETUP;
+ debug("%s ready to receive setup events\n", __func__);
+
+ return 0;
+}
+
+static int prepare_for_setup(struct crg_gadget_dev *crg_udc)
+{
+ if (!is_event_rings_empty(crg_udc) ||
+ (crg_udc->portsc_on_reconnecting == 1))
+ return -EBUSY;
+
+/* If we reinit ep0 on bus reset, we just make ep0 dequeue pointer align
+ * with enqueue pointer, all remaining xfer trbs became dumb ones which
+ * will not produce xfer event anymore.
+ *
+ * If we considering the opposite solution, we should wait all ep0 xfer
+ * trbs be completed(with some err complete code)
+ */
+
+ enable_setup(crg_udc);
+
+ return 0;
+}
+
+static void update_ep0_maxpacketsize(struct crg_gadget_dev *crg_udc)
+{
+ u16 maxpacketsize = 0;
+ struct crg_udc_ep *udc_ep0 = &crg_udc->udc_ep[0];
+ u32 param0;
+
+ maxpacketsize = 64;
+
+ resize_odb(crg_udc, 0, maxpacketsize);
+
+ param0 = CRG_CMD1_0_MPS(maxpacketsize);
+ crg_issue_command(crg_udc, CRG_CMD_UPDATE_EP0_CFG, param0, 0);
+
+ crg_udc_ep0_desc.wMaxPacketSize = cpu_to_le16(maxpacketsize);
+ udc_ep0->usb_ep.maxpacket = maxpacketsize;
+
+}
+
+static int init_event_ring(struct crg_gadget_dev *crg_udc, int index)
+{
+ struct crg_uicr *uicr = crg_udc->uicr[index];
+ struct crg_udc_event *udc_event = &crg_udc->udc_event[index];
+ u32 buff_length;
+ ulong mapping;
+
+ buff_length = CRG_ERST_SIZE * sizeof(struct erst_s);
+ if (!udc_event->erst.vaddr) {
+ udc_event->erst.vaddr =
+ dma_alloc_coherent(buff_length, (unsigned long *)&mapping);
+ } else
+ mapping = udc_event->erst.dma;
+
+ udc_event->erst.len = buff_length;
+ udc_event->erst.dma = mapping;
+ udc_event->p_erst = udc_event->erst.vaddr;
+
+
+ buff_length = CRG_EVENT_RING_SIZE * sizeof(struct event_trb_s);
+ if (!udc_event->event_ring.vaddr) {
+ udc_event->event_ring.vaddr =
+ dma_alloc_coherent(buff_length, (unsigned long *)&mapping);
+ } else
+ mapping = udc_event->event_ring.dma;
+
+ udc_event->event_ring.len = buff_length;
+ udc_event->event_ring.dma = mapping;
+ udc_event->evt_dq_pt = udc_event->event_ring.vaddr;
+ udc_event->evt_seg0_last_trb =
+ (struct event_trb_s *)(udc_event->event_ring.vaddr)
+ + (CRG_EVENT_RING_SIZE - 1);
+
+ udc_event->CCS = 1;
+
+ udc_event->p_erst->seg_addr_lo =
+ lower_32_bits(udc_event->event_ring.dma);
+ udc_event->p_erst->seg_addr_hi =
+ upper_32_bits(udc_event->event_ring.dma);
+ udc_event->p_erst->seg_size = cpu_to_le32(CRG_EVENT_RING_SIZE);
+ udc_event->p_erst->rsvd = 0;
+ crg_flush_cache((uintptr_t)udc_event->p_erst, sizeof(struct erst_s));
+
+ /*clear the event ring, to avoid hw unexpected ops
+ *because of dirty data
+ */
+ memset(udc_event->event_ring.vaddr, 0, buff_length);
+ crg_flush_cache((uintptr_t)udc_event->event_ring.vaddr, buff_length);
+
+ /*hw related ops ERSTBA && ERSTSZ && ERDP*/
+
+ /**************************/
+ reg_write(&uicr->erstsz, CRG_ERST_SIZE);
+ reg_write(&uicr->erstbalo, lower_32_bits(udc_event->erst.dma));
+ reg_write(&uicr->erstbahi, upper_32_bits(udc_event->erst.dma));
+ reg_write(&uicr->erdplo,
+ lower_32_bits(udc_event->event_ring.dma) | CRG_U3DC_ERDPLO_EHB);
+ reg_write(&uicr->erdphi, upper_32_bits(udc_event->event_ring.dma));
+
+ reg_write(&uicr->iman, (CRG_U3DC_IMAN_INT_EN | CRG_U3DC_IMAN_INT_PEND));
+ reg_write(&uicr->imod, (0L<<0)|(4000L<<0));
+
+ return 0;
+
+}
+
+static int init_device_context(struct crg_gadget_dev *crg_udc)
+{
+ struct crg_uccr *uccr = crg_udc->uccr;
+ u32 buff_length;
+ ulong mapping;
+
+ /*ep0 is not included in ep contexts in crg udc*/
+ buff_length = (CRG_NUM_EP_CX - 2) * sizeof(struct ep_cx_s);
+
+ if (!crg_udc->ep_cx.vaddr) {
+ crg_udc->ep_cx.vaddr =
+ dma_alloc_coherent(buff_length, (unsigned long *)&mapping);
+ memset(crg_udc->ep_cx.vaddr, 0, buff_length);
+ crg_flush_cache((uintptr_t)crg_udc->ep_cx.vaddr, buff_length);
+ } else {
+ mapping = crg_udc->ep_cx.dma;
+ }
+
+ crg_udc->p_epcx = crg_udc->ep_cx.vaddr;
+ crg_udc->ep_cx.len = buff_length;
+ crg_udc->ep_cx.dma = mapping;
+
+ /*hw ops DCBAPLO DCBAPHI*/
+ reg_write(&uccr->dcbaplo, lower_32_bits(crg_udc->ep_cx.dma));
+ reg_write(&uccr->dcbaphi, upper_32_bits(crg_udc->ep_cx.dma));
+
+ debug("dcbaplo[0x%p]=0x%x\n", &uccr->dcbaplo, reg_read(&uccr->dcbaplo));
+ debug("dcbaphi[0x%p]=0x%x\n", &uccr->dcbaphi, reg_read(&uccr->dcbaphi));
+
+ return 0;
+
+}
+
+static int reset_data_struct(struct crg_gadget_dev *crg_udc)
+{
+ u32 tmp;
+
+ struct crg_uccr *uccr = crg_udc->uccr;
+
+ clrbits_le32(&uccr->control, (CRG_U3DC_CTRL_INT_EN|CRG_U3DC_CTRL_RUN));
+ debug("control=0x%x\n", reg_read(&uccr->control));
+
+ debug("capability[0x%p]=0x%x\n", &uccr->capability,
+ reg_read(&uccr->capability));
+
+
+ /*config0*/
+ tmp = CRG_U3DC_CFG0_MAXSPEED_HS;
+
+ reg_write(&uccr->config0, tmp);
+ debug("config0[0x%p]=0x%x\n", &uccr->config0, reg_read(&uccr->config0));
+
+ //for (i = 0; i < CRG_RING_NUM; i++)
+ init_event_ring(crg_udc, 0);
+
+ init_device_context(crg_udc);
+
+ if (!crg_udc->status_req) {
+ crg_udc->status_req =
+ container_of(crg_udc_alloc_request(&crg_udc->udc_ep[0].usb_ep,
+ GFP_ATOMIC), struct crg_udc_request,
+ usb_req);
+ }
+
+ /*other hw ops*/
+ return 0;
+}
+
+static int init_ep0(struct crg_gadget_dev *crg_udc)
+{
+ struct crg_udc_ep *udc_ep_ptr = &crg_udc->udc_ep[0];
+ u32 cmd_param0;
+ u32 cmd_param1;
+
+ /* setup transfer ring */
+ if (!udc_ep_ptr->tran_ring_info.vaddr) {
+ ulong dma;
+ u32 ring_size = CRGUDC_CONTROL_EP_TD_RING_SIZE;
+ void *vaddr;
+ size_t len;
+
+ len = ring_size * sizeof(struct transfer_trb_s);
+ vaddr =
+ dma_alloc_coherent(len, (unsigned long *)&dma);
+
+ udc_ep_ptr->tran_ring_info.vaddr = vaddr;
+ udc_ep_ptr->tran_ring_info.dma = dma;
+ udc_ep_ptr->tran_ring_info.len = len;
+ udc_ep_ptr->first_trb = vaddr;
+ udc_ep_ptr->last_trb = udc_ep_ptr->first_trb + ring_size - 1;
+ }
+
+ memset(udc_ep_ptr->first_trb, 0, udc_ep_ptr->tran_ring_info.len);
+ crg_flush_cache((uintptr_t)udc_ep_ptr->first_trb, udc_ep_ptr->tran_ring_info.len);
+ udc_ep_ptr->enq_pt = udc_ep_ptr->first_trb;
+ udc_ep_ptr->deq_pt = udc_ep_ptr->first_trb;
+ udc_ep_ptr->pcs = 1;
+ udc_ep_ptr->tran_ring_full = false;
+
+ setup_link_trb(udc_ep_ptr->last_trb,
+ true, udc_ep_ptr->tran_ring_info.dma);
+
+ /*context related ops*/
+ cmd_param0 = (lower_32_bits(udc_ep_ptr->tran_ring_info.dma) &
+ CRG_CMD0_0_DQPTRLO_MASK) |
+ CRG_CMD0_0_DCS(udc_ep_ptr->pcs);
+ cmd_param1 = upper_32_bits(udc_ep_ptr->tran_ring_info.dma);
+
+ debug("ep0 ring dma addr = 0x%llx\n", udc_ep_ptr->tran_ring_info.dma);
+
+ pdebug("ep0 ring vaddr = 0x%p\n", udc_ep_ptr->tran_ring_info.vaddr);
+
+ debug("INIT EP0 CMD, par0=0x%x, par1=0x%x\n", cmd_param0, cmd_param1);
+
+ crg_issue_command(crg_udc, CRG_CMD_INIT_EP0, cmd_param0, cmd_param1);
+
+ udc_ep_ptr->ep_state = EP_STATE_RUNNING;
+
+ return 0;
+
+}
+
+static int EP0_Start(struct crg_gadget_dev *crg_udc)
+{
+ crg_udc->udc_ep[0].desc = &crg_udc_ep0_desc;
+
+ return 0;
+}
+
+static void crg_udc_start(struct crg_gadget_dev *crg_udc)
+{
+ struct crg_uccr *uccr;
+
+ debug("%s %d\n", __func__, __LINE__);
+
+ uccr = crg_udc->uccr;
+
+ /*****interrupt related*****/
+ //reg_write(&uccr->config1,
+ setbits_le32(&uccr->config1,
+ CRG_U3DC_CFG1_CSC_EVENT_EN |
+ CRG_U3DC_CFG1_PEC_EVENT_EN |
+ CRG_U3DC_CFG1_PPC_EVENT_EN |
+ CRG_U3DC_CFG1_PRC_EVENT_EN |
+ CRG_U3DC_CFG1_PLC_EVENT_EN |
+ CRG_U3DC_CFG1_CEC_EVENT_EN);
+ debug("config1[0x%p]=0x%x\n", &uccr->config1, reg_read(&uccr->config1));
+ debug("config0[0x%p]=0x%x\n", &uccr->config0, reg_read(&uccr->config0));
+
+ setbits_le32(&uccr->control, CRG_U3DC_CTRL_SYSERR_EN |
+ CRG_U3DC_CTRL_INT_EN);
+ /*****interrupt related end*****/
+
+
+ setbits_le32(&uccr->control, CRG_U3DC_CTRL_RUN);
+ debug("%s, control=0x%x\n", __func__, reg_read(&uccr->control));
+
+}
+
+void crg_udc_clear_portpm(struct crg_gadget_dev *crg_udc)
+{
+ struct crg_uccr *uccr = crg_udc->uccr;
+ u32 tmp;
+
+ tmp = reg_read(&uccr->u3portpmsc);
+
+ tmp &= (~CRG_U3DC_U3PORTPM_U1IEN);
+ //tmp &= (~CRG_U3DC_U3PORTPM_U1AEN);
+ SETF_VAR(CRG_U3DC_U3PORTPM_U1TMOUT, tmp, 0);
+ tmp &= (~CRG_U3DC_U3PORTPM_U2IEN);
+ //tmp &= (~CRG_U3DC_U3PORTPM_U2AEN);
+ SETF_VAR(CRG_U3DC_U3PORTPM_U2TMOUT, tmp, 0);
+
+ reg_write(&uccr->u3portpmsc, tmp);
+}
+
+void crg_udc_reinit(struct crg_gadget_dev *crg_udc)
+{
+ struct crg_uccr *uccr = crg_udc->uccr;
+ u32 i, tmp;
+ struct crg_udc_ep *udc_ep_ptr;
+
+ crg_udc->setup_status = WAIT_FOR_SETUP;
+ /* Base on Figure 9-1, default USB_STATE is attached */
+ crg_udc->device_state = USB_STATE_RECONNECTING;
+
+ /* halt all the endpoints */
+ //halt_all_eps(crg_udc);
+
+ debug("ep_enable=0x%x\n", reg_read(&uccr->ep_enable));
+ debug("ep_running=0x%x\n", reg_read(&uccr->ep_running));
+
+ /* disable all the endpoints */
+ tmp = reg_read(&uccr->ep_enable);
+ reg_write(&uccr->ep_enable, tmp);
+ for (i = 0; i < 50; i++) {
+ tmp = reg_read(&uccr->ep_enable);
+ if (tmp == 0)
+ break;
+ }
+ debug("%s i=%d \n", __func__, i);
+ debug("after ep_enable=0x%x\n", reg_read(&uccr->ep_enable));
+
+ for (i = 2; i < EP_TOTAL; i++) {
+ udc_ep_ptr = &crg_udc->udc_ep[i];
+
+ if (udc_ep_ptr->desc)
+ nuke(udc_ep_ptr, -ESHUTDOWN);
+ udc_ep_ptr->tran_ring_full = false;
+ udc_ep_ptr->ep_state = EP_STATE_DISABLED;
+ }
+ crg_udc->num_enabled_eps = 0;
+
+/* we don't handle ep0 here, we init_ep0 when event ring is empty*/
+
+ if (crg_udc->dev_addr != 0) {
+ u32 param0;
+
+ param0 = CRG_CMD2_0_DEV_ADDR(0);
+ crg_issue_command(crg_udc, CRG_CMD_SET_ADDR, param0, 0);
+ crg_udc->dev_addr = 0;
+ }
+
+ crg_udc_clear_portpm(crg_udc);
+
+ if (crg_udc->gadget_driver) {
+ debug("calling disconnect\n");
+ //crg_udc->gadget_driver->disconnect(&crg_udc->gadget);
+ }
+}
+
+static int crg_udc_reset(struct crg_gadget_dev *crg_udc)
+{
+ struct crg_uccr *uccr = crg_udc->uccr;
+ u32 i, tmp;
+ struct crg_udc_ep *udc_ep_ptr;
+
+ debug("%s %d\n", __func__, __LINE__);
+
+ setbits_le32(&uccr->control, CRG_U3DC_CTRL_SWRST);
+ do {
+ tmp = reg_read(&uccr->control);
+ } while ((tmp & CRG_U3DC_CTRL_SWRST) != 0);
+
+ crg_udc_clear_portpm(crg_udc);
+
+ crg_udc->setup_status = WAIT_FOR_SETUP;
+ /* Base on Figure 9-1, default USB_STATE is attached */
+ crg_udc->device_state = USB_STATE_ATTACHED;
+ crg_udc->dev_addr = 0;
+
+ for (i = 2; i < EP_TOTAL; i++) {
+ udc_ep_ptr = &crg_udc->udc_ep[i];
+
+ if (udc_ep_ptr->desc)
+ nuke(udc_ep_ptr, -ESHUTDOWN);
+ udc_ep_ptr->tran_ring_full = false;
+ udc_ep_ptr->ep_state = EP_STATE_DISABLED;
+ }
+ crg_udc->num_enabled_eps = 0;
+
+ /* Complete any reqs on EP0 queue */
+ udc_ep_ptr = &crg_udc->udc_ep[0];
+ if (udc_ep_ptr->desc)
+ nuke(udc_ep_ptr, -ESHUTDOWN);
+
+ crg_udc->ctrl_req_enq_idx = 0;
+ memset(crg_udc->ctrl_req_queue, 0,
+ sizeof(struct crg_setup_packet) * CTRL_REQ_QUEUE_DEPTH);
+
+
+ debug("%s %d\n", __func__, __LINE__);
+
+ return 0;
+}
+
+
+/************controller related ops*******************************/
+static int crg_gadget_get_frame(struct usb_gadget *g)
+{
+ debug("%s\n", __func__);
+
+ return 0;
+}
+
+static int crg_gadget_wakeup(struct usb_gadget *g)
+{
+ debug("%s\n", __func__);
+
+ return 0;
+}
+
+static int crg_gadget_set_selfpowered(struct usb_gadget *g,
+ int is_selfpowered)
+{
+ debug("%s\n", __func__);
+
+ return 0;
+}
+
+static int crg_gadget_pullup(struct usb_gadget *g, int is_on)
+{
+ debug("%s\n", __func__);
+
+ return 0;
+}
+
+
+//#define gadget_to_udc(g) (container_of(g, struct crg_gadget_dev, gadget))
+
+static int crg_gadget_start(struct usb_gadget *g,
+ struct usb_gadget_driver *driver)
+{
+ struct crg_gadget_dev *crg_udc;
+
+ debug("%s %d\n", __func__, __LINE__);
+
+ crg_udc = &crg_udc_dev;
+ crg_udc->gadget_driver = driver;
+
+ debug("%s %d gadget speed=%d, max speed=%d\n",
+ __func__, __LINE__, g->speed, g->max_speed);
+ debug("%s %d driver speed=%d\n", __func__, __LINE__, driver->speed);
+
+ return 0;
+}
+
+static void crg_reg_dump(struct crg_gadget_dev *crg_udc)
+{
+ struct crg_uccr *uccr = crg_udc->uccr;
+
+ debug("portsc[0x%p]=0x%x\n", &uccr->portsc, reg_read(&uccr->portsc));
+ debug("control[0x%p]=0x%x\n", &uccr->control, reg_read(&uccr->control));
+ debug("status[0x%p]=0x%x\n", &uccr->status, reg_read(&uccr->status));
+}
+
+static int crg_gadget_stop(struct usb_gadget *g)
+{
+ struct crg_gadget_dev *crg_udc;
+
+ crg_udc = &crg_udc_dev;
+
+ crg_reg_dump(crg_udc);
+
+ crg_udc_reset(crg_udc);
+
+ reset_data_struct(crg_udc);
+ crg_udc->connected = 0;
+ crg_udc->gadget_driver = NULL;
+ crg_udc->gadget.speed = USB_SPEED_UNKNOWN;
+
+ init_ep0(crg_udc);
+
+ debug("%s %d\n", __func__, __LINE__);
+
+ return 0;
+}
+
+static const struct usb_gadget_ops crg_gadget_ops = {
+ .get_frame = crg_gadget_get_frame,
+ .wakeup = crg_gadget_wakeup,
+ .set_selfpowered = crg_gadget_set_selfpowered,
+ .pullup = crg_gadget_pullup,
+ .udc_start = crg_gadget_start,
+ .udc_stop = crg_gadget_stop,
+};
+
+static int init_ep_info(struct crg_gadget_dev *crg_udc)
+{
+ int i;
+
+ /*udc_ep[0] is reserved, */
+ crg_ep_struct_setup(crg_udc, 0, NULL);
+
+ for (i = 1; i < CRG_NUM_EP_CX/2; i++) {
+ char name[14];
+
+ sprintf(name, "ep%din", i);
+ crg_ep_struct_setup(crg_udc, i*2, name);
+ sprintf(name, "ep%dout", i);
+ crg_ep_struct_setup(crg_udc, i*2+1, name);
+ }
+
+ return 0;
+}
+
+void queue_setup_pkt(struct crg_gadget_dev *crg_udc,
+ struct usb_ctrlrequest *setup_pkt,
+ u16 setup_tag)
+{
+ if (crg_udc->ctrl_req_enq_idx == CTRL_REQ_QUEUE_DEPTH) {
+ printf("ctrl request queque is full\n");
+ return;
+ }
+
+ memcpy(&(crg_udc->ctrl_req_queue[crg_udc->ctrl_req_enq_idx].usbctrlreq),
+ setup_pkt, sizeof(struct usb_ctrlrequest));
+ crg_udc->ctrl_req_queue[crg_udc->ctrl_req_enq_idx].setup_tag =
+ setup_tag;
+
+ crg_udc->ctrl_req_enq_idx++;
+}
+
+static inline u32 index2DCI(u16 index)
+{
+ if (index == 0)
+ return 0;
+
+ return (index & USB_ENDPOINT_NUMBER_MASK)*2 + ((index &
+ USB_DIR_IN) ? 0 : 1);
+}
+
+void getstatusrequest(struct crg_gadget_dev *crg_udc,
+ u8 RequestType, u16 value, u16 index, u16 length)
+{
+ u32 status_val = 0;
+ u32 status = -EINPROGRESS;
+ struct crg_udc_request *udc_req_ptr = crg_udc->status_req;
+ struct crg_udc_ep *udc_ep_ptr;
+
+ if ((value) || (length > 2) || !length) {
+ status = -EINVAL;
+ goto get_status_error;
+ }
+
+ debug("Get status request RequestType = 0x%x Index=%x\n",
+ RequestType, index);
+ if ((RequestType & USB_RECIP_MASK) == USB_RECIP_DEVICE) {
+ debug("Get status request Device request\n");
+ if (index) {
+ status = -EINVAL;
+ goto get_status_error;
+ }
+
+ if (crg_udc->gadget.speed == USB_SPEED_HIGH ||
+ crg_udc->gadget.speed == USB_SPEED_FULL) {
+ if (crg_udc->u2_RWE)
+ status_val |= BIT(USB_DEVICE_REMOTE_WAKEUP);
+ }
+
+ status_val |= BIT(USB_DEVICE_SELF_POWERED);
+ debug("Status = 0x%x\n", status_val);
+
+ } else if ((RequestType & USB_RECIP_MASK) == USB_RECIP_INTERFACE) {
+
+ debug("Get status request Interface request\n");
+
+ status_val = 0;
+ } else if ((RequestType & USB_RECIP_MASK) == USB_RECIP_ENDPOINT) {
+
+ u32 DCI;
+
+ DCI = index2DCI(index);
+
+ debug("Get status request endpoint request DCI = %d\n", DCI);
+
+ if (DCI == 1) {
+ status_val = 0;
+ debug("Get status request INVALID! DCI = %d\n", DCI);
+ goto get_status_error;
+ }
+
+ /* if device state is address state, index should be 0
+ * if device state is configured state, index should be an
+ * endpoint configured.
+ */
+ if ((crg_udc->device_state == USB_STATE_ADDRESS)
+ && (DCI != 0)) {
+
+ status = -EINVAL;
+ goto get_status_error;
+ }
+
+ if (crg_udc->device_state == USB_STATE_CONFIGURED) {
+ /*crg ep context start from ep1*/
+ struct ep_cx_s *p_ep_cx =
+ (struct ep_cx_s *)crg_udc->p_epcx + DCI - 2;
+
+ debug("p_ep_cx->EPDWord0 = 0x%x\n", p_ep_cx->dw0);
+
+ if (get_ep_state(crg_udc, DCI) == EP_STATE_DISABLED) {
+ status = -EINVAL;
+ goto get_status_error;
+ }
+
+ if (get_ep_state(crg_udc, DCI) == EP_STATE_HALTED) {
+ status_val = BIT(USB_ENDPOINT_HALT);
+ debug("endpoint was halted = 0x%lx\n",
+ (unsigned long)status_val);
+ }
+ }
+ }
+
+get_status_error:
+ if (status != -EINPROGRESS)
+ udc_req_ptr->usb_req.length = 0;
+ else {
+ udc_req_ptr->usb_req.buf = &crg_udc->statusbuf;
+ *(u16 *)udc_req_ptr->usb_req.buf = cpu_to_le16(status_val);
+ debug("usb_req.buf = 0x%x\n",
+ *((u16 *)udc_req_ptr->usb_req.buf));
+
+ debug("usb_req.buf addr = 0x%p\n",
+ (udc_req_ptr->usb_req.buf));
+
+ udc_req_ptr->usb_req.length = 2;
+ }
+ udc_req_ptr->usb_req.status = status;
+ udc_req_ptr->usb_req.actual = 0;
+ udc_req_ptr->usb_req.complete = NULL;
+
+ if (udc_req_ptr->usb_req.dma == DMA_ADDR_INVALID) {
+ udc_req_ptr->usb_req.dma =
+ dma_map_single(udc_req_ptr->usb_req.buf,
+ udc_req_ptr->usb_req.length,
+ DMA_FROM_DEVICE);
+ udc_req_ptr->mapped = 1;
+ }
+ debug("status_val = 0x%x, cpu_to_le16(status_val) = 0x%x\n",
+ status_val, cpu_to_le16(status_val));
+ debug("udc_req_ptr->usb_req.buf = 0x%p, value = 0x%x\n",
+ udc_req_ptr->usb_req.buf, *(u16 *)(udc_req_ptr->usb_req.buf));
+ debug("udc_req_ptr->usb_req.dma = 0x%llx\n",
+ udc_req_ptr->usb_req.dma);
+
+ udc_ep_ptr = &crg_udc->udc_ep[0];
+
+ crg_udc->setup_status = DATA_STAGE_XFER;
+ status = crg_udc_build_td(udc_ep_ptr, udc_req_ptr);
+
+ debug("getstatus databuf eqpt = 0x%p\n", udc_ep_ptr->enq_pt);
+}
+
+void set_address_cmpl(struct crg_gadget_dev *crg_udc)
+{
+ if ((crg_udc->device_state == USB_STATE_DEFAULT) &&
+ crg_udc->dev_addr != 0) {
+ crg_udc->device_state = USB_STATE_ADDRESS;
+ debug("USB State Addressed\n");
+
+ } else if (crg_udc->device_state == USB_STATE_ADDRESS) {
+ if (crg_udc->dev_addr == 0) {
+ crg_udc->device_state = USB_STATE_DEFAULT;
+ debug("USB State set back to 0\n");
+ } else {
+ debug("cannot set addr, already have addr %d\n",
+ crg_udc->dev_addr);
+ }
+ }
+}
+
+void setaddressrequest(struct crg_gadget_dev *crg_udc,
+ u16 value, u16 index, u16 length)
+{
+ int status = -EINPROGRESS;
+ u8 status_set_addr = 0;
+
+ if ((value > 127) || (index != 0) || (length != 0)) {
+ status = -EINVAL;
+ goto set_address_error;
+ }
+
+ if (((crg_udc->device_state == USB_STATE_DEFAULT) && value != 0) ||
+ (crg_udc->device_state == USB_STATE_ADDRESS)) {
+ u32 param0;
+
+ crg_udc->dev_addr = value;
+
+ param0 = CRG_CMD2_0_DEV_ADDR(value);
+ crg_issue_command(crg_udc, CRG_CMD_SET_ADDR, param0, 0);
+ status_set_addr = 1;
+ } else
+ status = -EINVAL;
+
+
+set_address_error:
+ debug("build_ep0_status for Address Device\n");
+
+ crg_udc->setup_status = STATUS_STAGE_XFER;
+ crg_udc->setup_fn_call_back = &set_address_cmpl;
+ build_ep0_status(&crg_udc->udc_ep[0],
+ true, status, NULL, status_set_addr, 0);
+}
+
+bool setfeaturesrequest(struct crg_gadget_dev *crg_udc,
+ u8 RequestType, u8 bRequest, u16 value, u16 index, u16 length)
+{
+ int status = -EINPROGRESS;
+ u8 DCI;
+ struct crg_udc_ep *udc_ep_ptr;
+ //u32 tmp;
+ //bool set_feat = 0;
+// struct crg_uccr *uccr = crg_udc->uccr;
+
+ if (length != 0) {
+ status = -EINVAL;
+ goto set_feature_error;
+ }
+
+ if (crg_udc->device_state == USB_STATE_DEFAULT) {
+ status = -EINVAL;
+ goto set_feature_error;
+ }
+
+ //set_feat = (bRequest == USB_REQ_SET_FEATURE) ? 1 : 0;
+ if ((RequestType & (USB_RECIP_MASK | USB_TYPE_MASK)) ==
+ (USB_RECIP_ENDPOINT | USB_TYPE_STANDARD)) {
+ debug("Halt/Unhalt EP\n");
+ if (crg_udc->device_state == USB_STATE_ADDRESS) {
+ if (index != 0) {
+ status = -EINVAL;
+ goto set_feature_error;
+ }
+ }
+
+ DCI = index2DCI(index);
+
+ if (DCI == 1) {
+ debug("setfeat INVALID DCI = 0x%x !!\n", DCI);
+ goto set_feature_error;
+ }
+
+ udc_ep_ptr = &crg_udc->udc_ep[DCI];
+ debug("halt/Unhalt endpoint DCI = 0x%x\n", DCI);
+
+ status = ep_halt(udc_ep_ptr,
+ (bRequest == USB_REQ_SET_FEATURE) ? 1 : 0,
+ 0);
+
+ if (status < 0)
+ goto set_feature_error;
+ } else if ((RequestType & (USB_RECIP_MASK | USB_TYPE_MASK)) ==
+ (USB_RECIP_INTERFACE | USB_TYPE_STANDARD)) {
+ if (crg_udc->device_state != USB_STATE_CONFIGURED) {
+ printf("%s interface u12 enable fail, usb state=%d\n",
+ __func__, crg_udc->device_state);
+ status = -EINVAL;
+ goto set_feature_error;
+ }
+ }
+
+ crg_udc->setup_status = STATUS_STAGE_XFER;
+ build_ep0_status(&crg_udc->udc_ep[0], true, status, NULL, 0, 0);
+ return true;
+
+set_feature_error:
+ set_ep0_halt(crg_udc);
+ return true;
+}
+
+bool setconfigurationrequest(struct crg_gadget_dev *crg_udc, u16 value)
+{
+ if (crg_udc->device_state <= USB_STATE_DEFAULT)
+ goto set_config_error;
+
+ /*return false means need further process by composite gadget driver*/
+ return false;
+
+
+set_config_error:
+ set_ep0_halt(crg_udc);
+ return true;
+}
+
+void crg_handle_setup_pkt(struct crg_gadget_dev *crg_udc,
+ struct usb_ctrlrequest *setup_pkt, u8 setup_tag)
+{
+ u16 wValue = setup_pkt->wValue;
+ u16 wIndex = setup_pkt->wIndex;
+ u16 wLength = setup_pkt->wLength;
+ //u64 wData = 0;
+
+ debug("bRequest=0x%x, wValue=0x%.4x, wIndex=0x%x, wLength=%d\n",
+ setup_pkt->bRequest, wValue, wIndex, wLength);
+
+ /* EP0 come backs to running when new setup packet comes*/
+ crg_udc->udc_ep[0].ep_state = EP_STATE_RUNNING;
+
+ crg_udc->setup_tag = setup_tag;
+ crg_udc->setup_status = SETUP_PKT_PROCESS_IN_PROGRESS;
+ crg_udc->setup_fn_call_back = NULL;
+
+ if ((setup_pkt->bRequestType & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
+ switch (setup_pkt->bRequest) {
+ case USB_REQ_GET_STATUS:
+ debug("USB_REQ_GET_STATUS\n");
+ if ((setup_pkt->bRequestType & (USB_DIR_IN |
+ USB_TYPE_MASK))
+ != (USB_DIR_IN | USB_TYPE_STANDARD)) {
+ crg_udc->setup_status = WAIT_FOR_SETUP;
+ return;
+ }
+
+ getstatusrequest(crg_udc, setup_pkt->bRequestType,
+ wValue, wIndex, wLength);
+ return;
+ case USB_REQ_SET_ADDRESS:
+ debug("USB_REQ_SET_ADDRESS\n");
+ if (setup_pkt->bRequestType != (USB_DIR_OUT |
+ USB_RECIP_DEVICE |
+ USB_TYPE_STANDARD)) {
+ crg_udc->setup_status = WAIT_FOR_SETUP;
+ return;
+ }
+
+ setaddressrequest(crg_udc, wValue, wIndex, wLength);
+ return;
+ case USB_REQ_CLEAR_FEATURE:
+ case USB_REQ_SET_FEATURE:
+ debug("USB_REQ_CLEAR/SET_FEATURE\n");
+
+ /* Need composite gadget driver
+ * to process the function remote wakeup request
+ */
+ if (setfeaturesrequest(crg_udc, setup_pkt->bRequestType,
+ setup_pkt->bRequest,
+ wValue, wIndex, wLength)) {
+ /* Get here if request has been processed.*/
+ return;
+ }
+ break;
+ case USB_REQ_SET_CONFIGURATION:
+ debug("USB_REQ_SET_CONFIGURATION\n");
+ debug("CONFIGURATION wValue=%d\n", wValue);
+ if (setconfigurationrequest(crg_udc, wValue)) {
+ return;
+ }
+ break;
+ default:
+ debug("USB_REQ default bRequest=%d, bRequestType=%d\n",
+ setup_pkt->bRequest, setup_pkt->bRequestType);
+
+ }
+ }
+
+
+ if (wLength) {
+ /* data phase from gadget like GET_CONFIGURATION
+ * call the setup routine of gadget driver.
+ * remember the request direction.
+ */
+ crg_udc->setup_status =
+ (setup_pkt->bRequestType & USB_DIR_IN) ?
+ DATA_STAGE_XFER : DATA_STAGE_RECV;
+ }
+
+ if (crg_udc->gadget_driver->setup(&crg_udc->gadget, setup_pkt) < 0) {
+ set_ep0_halt(crg_udc);
+ return;
+ }
+}
+
+int crg_handle_xfer_event(struct crg_gadget_dev *crg_udc,
+ struct event_trb_s *event)
+{
+ u8 DCI = GETF(EVE_TRB_ENDPOINT_ID, event->dw3);
+ struct crg_udc_ep *udc_ep_ptr = &crg_udc->udc_ep[DCI];
+ /*Corigine ep contexts start from ep1*/
+ u16 comp_code;
+ struct crg_udc_request *udc_req_ptr;
+ //bool trbs_dequeued = false;
+
+ if (!udc_ep_ptr->first_trb ||
+ get_ep_state(crg_udc, DCI) == EP_STATE_DISABLED)
+ return -ENODEV;
+
+ comp_code = GETF(EVE_TRB_COMPL_CODE, event->dw2);
+
+ if (comp_code == CMPL_CODE_STOPPED ||
+ comp_code == CMPL_CODE_STOPPED_LENGTH_INVALID ||
+ comp_code == CMPL_CODE_DISABLED ||
+ comp_code == CMPL_CODE_DISABLED_LENGTH_INVALID ||
+ comp_code == CMPL_CODE_HALTED ||
+ comp_code == CMPL_CODE_HALTED_LENGTH_INVALID) {
+ debug("comp_code = %d(STOPPED/HALTED/DISABLED)\n", comp_code);
+ } else {
+ update_dequeue_pt(event, udc_ep_ptr);
+ }
+
+ xdebug("%s ep%d dqpt=0x%p, eqpt=0x%p\n", __func__,
+ DCI, udc_ep_ptr->deq_pt, udc_ep_ptr->enq_pt);
+ xdebug("comp_code = %d\n", comp_code);
+
+ //if (is_request_dequeued(crg_udc, udc_ep_ptr, event)) {
+ // trbs_dequeued = true;
+ // debug("WARNING: Drop the transfer event\n");
+ // goto queue_more_trbs;
+ //}
+
+ comp_code = GETF(EVE_TRB_COMPL_CODE, event->dw2);
+
+ switch (comp_code) {
+ case CMPL_CODE_SUCCESS:
+ {
+ xdebug("%s Complete SUCCESS\n", __func__);
+ handle_cmpl_code_success(crg_udc, event, udc_ep_ptr);
+
+ //debug("%s handle cmpl end\n", __func__);
+ //trbs_dequeued = true;
+ break;
+ }
+ case CMPL_CODE_SHORT_PKT:
+ {
+ u32 trb_transfer_length;
+
+ xdebug("handle_exfer_event CMPL_CODE_SHORT_PKT\n");
+ if (usb_endpoint_dir_out(udc_ep_ptr->desc)) {
+ trb_transfer_length = GETF(EVE_TRB_TRAN_LEN,
+ event->dw2);
+
+ udc_req_ptr = udc_ep_ptr->ep_req;
+
+
+ udc_req_ptr->usb_req.actual =
+ udc_req_ptr->usb_req.length -
+ trb_transfer_length;
+ if (udc_req_ptr->usb_req.actual != 0)
+ crg_inval_cache((uintptr_t)udc_req_ptr->usb_req.buf, udc_req_ptr->usb_req.actual);
+
+ if (udc_req_ptr->usb_req.actual != 512 &&
+ udc_req_ptr->usb_req.actual != 31) {
+
+ u64 trb_pt;
+ struct transfer_trb_s *p_trb;
+
+ debug("Actual Data transfered = %d\n",
+ udc_req_ptr->usb_req.actual);
+
+ trb_pt = (u64)event->dw0 +
+ ((u64)(event->dw1) << 32);
+
+ p_trb = tran_trb_dma_to_virt(
+ udc_ep_ptr, trb_pt);
+
+ debug("event dw0 = 0x%x\n", event->dw0);
+ debug("event dw1 = 0x%x\n", event->dw1);
+ debug("event dw2 = 0x%x\n", event->dw2);
+ debug("event dw3 = 0x%x\n", event->dw3);
+
+ debug("trb_pt = 0x%lx, p_trb = 0x%p\n",
+ (unsigned long)trb_pt, p_trb);
+
+ debug("trb dw0 = 0x%x\n", p_trb->dw0);
+ debug("trb dw1 = 0x%x\n", p_trb->dw1);
+ debug("trb dw2 = 0x%x\n", p_trb->dw2);
+ debug("trb dw3 = 0x%x\n", p_trb->dw3);
+ }
+ req_done(udc_ep_ptr, udc_req_ptr, 0);
+ } else
+ debug("ep dir in\n");
+
+ /* Advance the dequeue pointer to next TD */
+ advance_dequeue_pt(udc_ep_ptr);
+
+ break;
+ }
+
+ case CMPL_CODE_PROTOCOL_STALL:
+ {
+ debug("%s CMPL_CODE_PROTOCOL_STALL\n", __func__);
+
+ //udc_req_ptr = list_entry(udc_ep_ptr->queue.next,
+ // struct crg_udc_request, queue);
+
+ udc_req_ptr = udc_ep_ptr->ep_req;
+ req_done(udc_ep_ptr, udc_req_ptr, -EINVAL);
+ //trbs_dequeued = true;
+ crg_udc->setup_status = WAIT_FOR_SETUP;
+ advance_dequeue_pt(udc_ep_ptr);
+ break;
+ }
+
+ case CMPL_CODE_SETUP_TAG_MISMATCH:
+ {
+ u32 enq_idx = crg_udc->ctrl_req_enq_idx;
+ struct usb_ctrlrequest *setup_pkt;
+ struct crg_setup_packet *crg_setup_pkt;
+ u16 setup_tag;
+
+ pdebug("%s SETUP TAG MISMATCH\n", __func__);
+ debug("NOW setup tag = 0x%x\n", crg_udc->setup_tag);
+
+ /* skip seqnum err event until last one arrives. */
+ if (udc_ep_ptr->deq_pt == udc_ep_ptr->enq_pt) {
+
+ //udc_req_ptr = list_entry(udc_ep_ptr->queue.next,
+ // struct crg_udc_request,
+ // queue);
+ udc_req_ptr = udc_ep_ptr->ep_req;
+
+ if (udc_req_ptr)
+ req_done(udc_ep_ptr, udc_req_ptr, -EINVAL);
+
+ /* drop all the queued setup packet, only
+ * process the latest one.
+ */
+ crg_udc->setup_status = WAIT_FOR_SETUP;
+ if (enq_idx) {
+ crg_setup_pkt =
+ &crg_udc->ctrl_req_queue[enq_idx - 1];
+ setup_pkt = &crg_setup_pkt->usbctrlreq;
+ setup_tag = crg_setup_pkt->setup_tag;
+ crg_handle_setup_pkt(crg_udc, setup_pkt,
+ setup_tag);
+ /* flash the queue after the latest
+ * setup pkt got handled..
+ */
+ memset(crg_udc->ctrl_req_queue, 0,
+ sizeof(struct crg_setup_packet)
+ * CTRL_REQ_QUEUE_DEPTH);
+ crg_udc->ctrl_req_enq_idx = 0;
+ }
+
+ } else {
+ debug("setuptag mismatch skp dpt!=ept: 0x%p, 0x%p\n",
+ udc_ep_ptr->deq_pt, udc_ep_ptr->enq_pt);
+
+ }
+
+ //crg_udc->setup_tag_mismatch_found = 1;
+ debug("%s SETUP TAG MISMATCH END\n", __func__);
+ break;
+ }
+
+ case CMPL_CODE_BABBLE_DETECTED_ERR:
+ case CMPL_CODE_INVALID_STREAM_TYPE_ERR:
+ case CMPL_CODE_RING_UNDERRUN:
+ case CMPL_CODE_RING_OVERRUN:
+ case CMPL_CODE_ISOCH_BUFFER_OVERRUN:
+ case CMPL_CODE_USB_TRANS_ERR:
+ case CMPL_CODE_TRB_ERR:
+ {
+ printf("XFER event err, comp_code = 0x%x\n", comp_code);
+ set_ep_halt(crg_udc, DCI);
+ break;
+ }
+
+ case CMPL_CODE_STOPPED:
+ case CMPL_CODE_STOPPED_LENGTH_INVALID:
+ /* Any ep stop ops should deal with stopped trbs itselves
+ * Event handler didn't know whether the stopped trb should
+ * be discarded or continued. So we do nothing here
+ */
+ debug("STOP, comp_code = 0x%x\n", comp_code);
+ break;
+
+ default:
+ debug("CRG UNKNOWN comp_code = 0x%x\n", comp_code);
+ debug("EPDCI = 0x%x\n", udc_ep_ptr->DCI);
+ break;
+ }
+
+
+ xdebug("%s 2 ep%d dqpt=0x%p, eqpt=0x%p\n", __func__,
+ DCI, udc_ep_ptr->deq_pt, udc_ep_ptr->enq_pt);
+#if 0
+queue_more_trbs:
+ /* If there are some trbs dequeued by HW and the ring
+ * was full before, then schedule any pending TRB's
+ */
+ if ((trbs_dequeued == true) && (udc_ep_ptr->tran_ring_full == true)) {
+ udc_ep_ptr->tran_ring_full = false;
+ queue_pending_trbs(udc_ep_ptr);
+ }
+#endif
+ return 0;
+
+}
+
+
+/* workround, use high speed termination to help wakeup asmedia host*/
+unsigned int hs_term_wakeup;
+int init_connected = -1;
+
+/*temprory solution, this function should be board specific*/
+int g_dnl_board_usb_cable_connected(void)
+{
+ struct crg_gadget_dev *crg_udc;
+ struct crg_uccr *uccr;
+ u32 tmp;
+
+ crg_udc = &crg_udc_dev;
+ if (crg_udc == NULL)
+ return -EOPNOTSUPP;
+
+
+ uccr = crg_udc->uccr;
+ tmp = reg_read(&uccr->portsc);
+ if (tmp & CRG_U3DC_PORTSC_PP) {
+ if (init_connected < 0) {
+ init_connected = 1;
+ hs_term_wakeup = 1;
+ }
+
+ if (crg_udc->device_state < USB_STATE_POWERED) {
+ u32 tmp_cfg0;
+
+ debug("%s powered, portsc[0x%p]=0x%x\n", __func__,
+ &uccr->portsc, tmp);
+
+ if (hs_term_wakeup == 1) {
+ debug("%s wr hs term on start\n", __func__);
+ hs_term_wakeup = 0;
+ }
+
+ /*set usb 3 disable count to 15*/
+ tmp_cfg0 = reg_read(&uccr->config0);
+ tmp_cfg0 &= (~0xf0);
+ tmp_cfg0 |= 0xf0;
+ reg_write(&uccr->config0, tmp_cfg0);
+ /**/
+
+ mdelay(1);
+
+ crg_udc_start(crg_udc);
+
+ debug("%s device state powered\n", __func__);
+ crg_udc->device_state = USB_STATE_POWERED;
+ }
+
+ return 1;
+ }
+
+ /*PP is not set*/
+ if (init_connected < 0) {
+ init_connected = 0;
+ hs_term_wakeup = 0;
+ }
+
+ xdebug("%s no power, portsc[0x%p]=0x%x\n", __func__,
+ &uccr->portsc, tmp);
+
+ return 0;
+
+}
+
+
+unsigned int _sofintr_not_occur;
+
+int crg_handle_port_status(struct crg_gadget_dev *crg_udc)
+{
+ struct crg_uccr *uccr = crg_udc->uccr;
+ u32 portsc_val;
+ u32 tmp;
+
+ /* handle Port Reset */
+ portsc_val = reg_read(&uccr->portsc);
+ reg_write(&uccr->portsc, portsc_val);
+
+ tmp = reg_read(&uccr->portsc);
+ pdebug("%s RAW,portsc[0x%p]=0x%x\n", __func__,
+ &uccr->portsc, portsc_val);
+
+ if (portsc_val & CRG_U3DC_PORTSC_PRC) {
+ mdelay(3);
+
+ tmp = reg_read(&uccr->portsc);
+ if (tmp & CRG_U3DC_PORTSC_PRC) {
+ pdebug("PRC is still set\n");
+ } else if (tmp & CRG_U3DC_PORTSC_PR) {
+ /* first port status change event for port reset*/
+ pdebug("PRC is not set, but PR is set!!!!!!!!\n");
+ } else {
+ if (CRG_U3DC_PORTSC_PLS_GET(tmp) > 0x2 ||
+ (!(tmp & CRG_U3DC_PORTSC_PED))) {
+ pdebug("portsc[0x%p]=0x%x no PED return\n", &uccr->portsc, tmp);
+ return 0;
+ }
+
+ crg_udc_reinit(crg_udc);
+ if (_sofintr_not_occur) {
+ printf("crg cn\n");
+ _sofintr_not_occur = 0;
+ }
+
+ crg_udc->gadget.speed = USB_SPEED_HIGH;
+ pdebug("gadget speed = 0x%x\n", crg_udc->gadget.speed);
+
+ update_ep0_maxpacketsize(crg_udc);
+
+ crg_udc->connected = 1;
+
+ enable_setup(crg_udc);
+
+ pdebug("PORTSC = 0x%x\n", reg_read(&uccr->portsc));
+ }
+ }
+ /* handle Port Reset end */
+
+
+ /* handle Port Connection Change*/
+ if (portsc_val & CRG_U3DC_PORTSC_CSC) {
+ tmp = reg_read(&uccr->portsc);
+ if ((tmp & (CRG_U3DC_PORTSC_CCS | CRG_U3DC_PORTSC_PP)) ==
+ (CRG_U3DC_PORTSC_CCS | CRG_U3DC_PORTSC_PP)) {
+ pdebug("connect int checked\n");
+ pdebug("portsc[0x%p]=0x%x\n", &uccr->portsc, tmp);
+
+ if (CRG_U3DC_PORTSC_PLS_GET(tmp) > 0x2 ||
+ (!(tmp & CRG_U3DC_PORTSC_PED))) {
+ return 0;
+ }
+
+ if (_sofintr_not_occur) {
+ printf("CRG CN\n");
+ _sofintr_not_occur = 0;
+ }
+ crg_udc->gadget.speed = USB_SPEED_HIGH;
+
+ update_ep0_maxpacketsize(crg_udc);
+
+ crg_udc->connected = 1;
+
+ if (crg_udc->device_state < USB_STATE_RECONNECTING)
+ enable_setup(crg_udc);
+ } else if (!(tmp & CRG_U3DC_PORTSC_CCS)) {
+ int cable_connected;
+
+ cable_connected = g_dnl_board_usb_cable_connected();
+ if (!cable_connected) {
+ debug("cable disconnected, rst controller\n");
+ crg_udc->device_state = USB_STATE_ATTACHED;
+
+ crg_udc_reset(crg_udc);
+ if (crg_udc->gadget_driver->disconnect) {
+ crg_udc->gadget_driver->disconnect(
+ &crg_udc->gadget);
+ }
+
+ reset_data_struct(crg_udc);
+ crg_udc->connected = 0;
+ init_ep0(crg_udc);
+ crg_udc_start(crg_udc);
+ return -ECONNRESET;
+ }
+
+ }
+ }
+
+ return 0;
+}
+
+
+int crg_udc_handle_event(struct crg_gadget_dev *crg_udc,
+ struct event_trb_s *event)
+{
+ int ret;
+
+ switch (GETF(EVE_TRB_TYPE, event->dw3)) {
+ case TRB_TYPE_EVT_PORT_STATUS_CHANGE:
+ if (crg_udc->device_state == USB_STATE_RECONNECTING) {
+ crg_udc->portsc_on_reconnecting = 1;
+ break;
+ }
+
+ ret = crg_handle_port_status(crg_udc);
+ if (ret)
+ return ret;
+
+ break;
+ case TRB_TYPE_EVT_TRANSFER:
+ if (crg_udc->device_state < USB_STATE_RECONNECTING) {
+ debug("Xfer compl event rcved when dev state=%d !\n",
+ crg_udc->device_state);
+ break;
+ }
+
+ crg_handle_xfer_event(crg_udc, event);
+ break;
+ case TRB_TYPE_EVT_SETUP_PKT:
+ {
+ struct usb_ctrlrequest *setup_pkt;
+ u8 setup_tag;
+
+ debug("handle_setup_pkt(%d)\n", crg_udc->device_state);
+
+ if (crg_udc->device_state < USB_STATE_DEFAULT) {
+ debug("%s state(%d) < DEFAULT!\n",
+ __func__, crg_udc->device_state);
+ break;
+ }
+
+ setup_pkt = (struct usb_ctrlrequest *)&event->dw0;
+
+ setup_tag = GETF(EVE_TRB_SETUP_TAG, event->dw3);
+ debug("setup_pkt = 0x%p, setup_tag = 0x%x\n",
+ setup_pkt, setup_tag);
+ if (crg_udc->setup_status != WAIT_FOR_SETUP) {
+ /*previous setup packet hasn't
+ * completed yet. Just ignore the prev setup
+ */
+ debug("consecutive setup\n");
+ queue_setup_pkt(crg_udc, setup_pkt, setup_tag);
+ break;
+ }
+
+ crg_handle_setup_pkt(crg_udc, setup_pkt, setup_tag);
+
+ break;
+ }
+ default:
+ debug("unexpect TRB_TYPE = 0x%x",
+ GETF(EVE_TRB_TYPE, event->dw3));
+ break;
+ }
+
+ return 0;
+}
+
+#if 0
+static dma_addr_t event_trb_virt_to_dma
+ (struct crg_udc_event *udc_event, struct event_trb_s *event)
+{
+ dma_addr_t dma_addr = 0;
+ unsigned long seg_offset;
+
+ if (!udc_event || !event)
+ return 0;
+
+ /* update dequeue pointer */
+ seg_offset = (void *)event - udc_event->event_ring.vaddr;
+ dma_addr = udc_event->event_ring.dma + seg_offset;
+
+ return dma_addr;
+}
+#endif
+
+int process_event_ring(struct crg_gadget_dev *crg_udc, int index)
+{
+ struct event_trb_s *event;
+ struct crg_udc_event *udc_event;
+ struct crg_uicr *uicr = crg_udc->uicr[index];
+ u32 tmp;
+ dma_addr_t erdp;
+ int ret;
+
+ if (uicr == NULL)
+ return IRQ_NONE;
+
+ setbits_le32(&uicr->iman, CRG_U3DC_IMAN_INT_PEND);
+
+ udc_event = &crg_udc->udc_event[index];
+ while (udc_event->evt_dq_pt) {
+ crg_inval_cache((uintptr_t)udc_event->evt_dq_pt, sizeof(struct event_trb_s));
+ event = (struct event_trb_s *)udc_event->evt_dq_pt;
+
+ if (GETF(EVE_TRB_CYCLE_BIT, event->dw3) !=
+ udc_event->CCS)
+ break;
+
+ ret = crg_udc_handle_event(crg_udc, event);
+ if (ret == -ECONNRESET)
+ return ret;
+
+ if (event == udc_event->evt_seg0_last_trb) {
+ //debug("evt_last_trb = 0x%p\n",
+ // udc_event->evt_seg0_last_trb);
+ //debug("evt_dq_pt = 0x%p\n", udc_event->evt_dq_pt);
+ udc_event->CCS = udc_event->CCS ? 0 : 1;
+ udc_event->evt_dq_pt = udc_event->event_ring.vaddr;
+ //debug("wrap Event dq_pt to Event ring segment 0\n");
+ } else
+ udc_event->evt_dq_pt++;
+
+ }
+
+ /* update dequeue pointer */
+ //erdp = event_trb_virt_to_dma(udc_event, udc_event->evt_dq_pt);
+ erdp = (dma_addr_t)(u64)udc_event->evt_dq_pt;
+ tmp = upper_32_bits(erdp);
+ reg_write(&uicr->erdphi, tmp);
+ tmp = lower_32_bits(erdp);
+ tmp |= CRG_U3DC_ERDPLO_EHB;
+ reg_write(&uicr->erdplo, tmp);
+
+ return 0;
+}
+
+int crg_gadget_handle_interrupt(struct crg_gadget_dev *crg_udc)
+{
+ struct crg_uccr *uccr = crg_udc->uccr;
+ u32 tmp_status;
+
+ tmp_status = reg_read(&uccr->status);
+
+ if (tmp_status & CRG_U3DC_STATUS_SYS_ERR) {
+ printf("%s System error happens!!!\n", __func__);
+ /*Handle system error*/
+ reg_write(&uccr->status, CRG_U3DC_STATUS_SYS_ERR);
+ }
+
+ if (tmp_status & CRG_U3DC_STATUS_EINT) {
+ //debug("%s EINT happens!\n", __func__);
+ reg_write(&uccr->status, CRG_U3DC_STATUS_EINT);
+
+ /*process event rings*/
+ //for (i = 0; i < CRG_RING_NUM; i++)
+ process_event_ring(crg_udc, 0);
+
+ }
+
+ //if (crg_udc->device_state == USB_STATE_RECONNECTING &&
+ //(crg_udc->portsc_on_reconnecting == 1) &&
+ //is_event_rings_empty(crg_udc)) {
+ //crg_udc->portsc_on_reconnecting = 0;
+ //crg_handle_port_status(crg_udc);
+// }
+
+ if (crg_udc->device_state == USB_STATE_RECONNECTING &&
+ (crg_udc->connected == 1)) {
+ debug("check if ready for setup\n");
+ prepare_for_setup(crg_udc);
+ }
+
+ return 0;
+}
+
+/**
+ * crg_gadget_init - Initializes gadget driver
+ *
+ *
+ * Returns 0 on success otherwise negative errno.
+ */
+
+int phy_num = 1;
+EXPORT_SYMBOL_GPL(phy_num);
+
+int usb_gadget_register_driver(struct usb_gadget_driver *drive)
+{
+ int ret;
+ int i;
+ struct crg_gadget_dev *crg_udc;
+
+ //dcache_disable();
+
+ crg_udc = &crg_udc_dev;
+
+ if (phy_num == 1) {
+ usb_device_mode_init(phy_num);
+ crg_udc->reg_base = (void __iomem *)(u64)0xfdd00000;
+ crg_udc->uccr = crg_udc->reg_base + CRG_UCCR_OFFSET;
+ } else {
+ usb_device_mode_init(phy_num);
+ crg_udc->reg_base = (void __iomem *)(u64)0xfde00000;
+ crg_udc->uccr = crg_udc->reg_base + CRG_UCCR_OFFSET;
+ }
+ /* set controller device role */
+ reg_write(crg_udc->reg_base+0x20FC , (reg_read(crg_udc->reg_base+0x20FC) | 0x1));
+
+ for (i = 0; i < CRG_RING_NUM; i++) {
+ crg_udc->uicr[i] = crg_udc->reg_base +
+ CRG_UICR_OFFSET + i * CRG_UICR_STRIDE;
+ }
+
+ crg_udc->controller_index = phy_num;
+
+ spin_lock_init(&crg_udc->lock);
+
+ crg_udc->gadget.ops = &crg_gadget_ops;
+ crg_udc->gadget.ep0 = &crg_udc->udc_ep[0].usb_ep;
+ INIT_LIST_HEAD(&crg_udc->gadget.ep_list);
+ crg_udc->gadget.max_speed = USB_SPEED_HIGH;//USB_SPEED_SUPER_PLUS;
+ crg_udc->gadget.speed = USB_SPEED_UNKNOWN;
+ crg_udc->gadget.name = "crg-gadget";
+
+ crg_udc->gadget.quirk_ep_out_aligned_size = true;
+ crg_udc->connected = 0;
+ crg_udc->dev_addr = 0;
+ memset(crg_udc->udc_event, 0, sizeof(struct crg_udc_event));
+
+ crg_udc_reset(crg_udc);
+
+ crg_udc_clear_portpm(crg_udc);
+
+ ret = reset_data_struct(crg_udc);
+ if (ret)
+ goto err0;
+
+ init_ep_info(crg_udc);
+ init_ep0(crg_udc);
+
+ EP0_Start(crg_udc);
+
+ crg_udc->gadget.ep0 = &crg_udc->udc_ep[0].usb_ep;
+ crg_udc->gadget.epin = &crg_udc->udc_ep[2].usb_ep;
+ crg_udc->gadget.epout= &crg_udc->udc_ep[3].usb_ep;
+ crg_udc->gadget_driver = drive;
+ drive->bind(&crg_udc->gadget);
+
+ return 0;
+
+err0:
+ return -1;
+}
+
+int usb_gadget_unregister_driver(struct usb_gadget_driver *driver)
+{
+ struct crg_gadget_dev *crg_udc;
+
+ crg_udc = &crg_udc_dev;
+
+ if (!crg_udc)
+ return -ENODEV;
+ if (!driver || driver != crg_udc->gadget_driver)
+ return -EINVAL;
+
+ driver->disconnect(&crg_udc->gadget);
+
+ driver->unbind(&crg_udc->gadget);
+
+ crg_udc->gadget_driver = NULL;
+
+ return 0;
+}
+
+int crg_gadget_remove(struct crg_gadget_dev *crg_udc)
+{
+ usb_del_gadget_udc(&crg_udc->gadget);
+
+ return 0;
+}
+
+int usb_gadget_handle_interrupts(int index)
+{
+ return crg_gadget_handle_interrupt(&crg_udc_dev);
+}
+
+
+void dwc_otg_power_off_phy_fb(void)
+{
+ return;
+}
diff --git a/drivers/usb/gadget/f_fastboot.c b/drivers/usb/gadget/f_fastboot.c
index cba7350..173809a 100644
--- a/drivers/usb/gadget/f_fastboot.c
+++ b/drivers/usb/gadget/f_fastboot.c
@@ -19,17 +19,7 @@
#include <linux/usb/composite.h>
#include <linux/compiler.h>
#include <g_dnl.h>
-#ifdef CONFIG_FASTBOOT_FLASH_MMC_DEV
-#include <fb_mmc.h>
-#endif
-#ifdef CONFIG_FASTBOOT_FLASH_NAND_DEV
-#include <fb_nand.h>
-#endif
-#ifdef CONFIG_G_AB_SYSTEM
#include <partition_table.h>
-#endif
-
-#define FASTBOOT_VERSION "0.4"
#define FASTBOOT_INTERFACE_CLASS 0xff
#define FASTBOOT_INTERFACE_SUB_CLASS 0x42
@@ -39,13 +29,17 @@
#define RX_ENDPOINT_MAXIMUM_PACKET_SIZE_1_1 (0x0040)
#define TX_ENDPOINT_MAXIMUM_PACKET_SIZE (0x0040)
+#define DEVICE_SERIAL "1234567890"
+
#define EP_BUFFER_SIZE 4096
/*
* EP_BUFFER_SIZE must always be an integral multiple of maxpacket size
* (64 or 512 or 1024), else we break on certain controllers like DWC3
* that expect bulk OUT requests to be divisible by maxpacket size.
*/
-
+#ifndef CONFIG_USB_GADGET_CRG
+extern void f_dwc_otg_pullup(int is_on);
+#endif
struct f_fastboot {
struct usb_function usb_function;
@@ -151,6 +145,13 @@
static void fastboot_complete(struct usb_ep *ep, struct usb_request *req)
{
int status = req->status;
+
+ if ( (busy_flag == 1) && fastboot_func) {
+ struct usb_ep* out_ep = fastboot_func->out_ep;
+ struct usb_request* out_req = fastboot_func->out_req;
+ rx_handler_command(out_ep, out_req);
+ return;
+ }
if (!status)
return;
printf("status: %d ep '%s' trans: %d\n", status, ep->name, req->actual);
@@ -196,8 +197,11 @@
}
s = env_get("serial#");
- if (s)
+ if (s) {
+ printf("serial num: %s\n", s);
g_dnl_set_serialnumber((char *)s);
+ } else
+ g_dnl_set_serialnumber(DEVICE_SERIAL);
return 0;
}
@@ -297,20 +301,53 @@
return ret;
}
+static int fastboot_setup(struct usb_function *f,
+ const struct usb_ctrlrequest *ctrl)
+{
+ int value = -EOPNOTSUPP;
+ struct f_fastboot *f_fb = func_to_fastboot(f);
+
+ /* composite driver infrastructure handles everything; interface
+ * activation uses set_alt().
+ */
+ if (((ctrl->bRequestType & USB_RECIP_MASK) == USB_RECIP_ENDPOINT)
+ && (ctrl->bRequest == USB_REQ_CLEAR_FEATURE)
+ && (ctrl->wValue== USB_ENDPOINT_HALT)) {
+ switch (ctrl->wIndex & 0xfe) {
+ case USB_DIR_OUT:
+ value = ctrl->wLength;
+ usb_ep_clear_halt(f_fb->out_ep);
+ break;
+
+ case USB_DIR_IN:
+ value = ctrl->wLength;
+ usb_ep_clear_halt(f_fb->in_ep);
+ break;
+ default:
+ printf("unknown usb_ctrlrequest\n");
+ break;
+ }
+ }
+
+ return value;
+}
+
static int fastboot_add(struct usb_configuration *c)
{
- struct f_fastboot *f_fb = fastboot_func;
+ struct f_fastboot *f_fb;
int status;
debug("%s: cdev: 0x%p\n", __func__, c->cdev);
- if (!f_fb) {
+ if (fastboot_func == NULL) {
f_fb = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*f_fb));
if (!f_fb)
return -ENOMEM;
fastboot_func = f_fb;
memset(f_fb, 0, sizeof(*f_fb));
+ } else {
+ f_fb = fastboot_func;
}
f_fb->usb_function.name = "f_fastboot";
@@ -319,11 +356,12 @@
f_fb->usb_function.set_alt = fastboot_set_alt;
f_fb->usb_function.disable = fastboot_disable;
f_fb->usb_function.strings = fastboot_strings;
+ f_fb->usb_function.setup = fastboot_setup;
status = usb_add_function(c, &f_fb->usb_function);
if (status) {
free(f_fb);
- fastboot_func = f_fb;
+ fastboot_func = NULL;
}
return status;
@@ -353,166 +391,32 @@
static void compl_do_reset(struct usb_ep *ep, struct usb_request *req)
{
+#ifndef CONFIG_USB_GADGET_CRG
+ f_dwc_otg_pullup(0);
+#endif
do_reset(NULL, 0, 0, NULL);
}
-int __weak fb_set_reboot_flag(void)
+static void compl_do_reboot_bootloader(struct usb_ep *ep, struct usb_request *req)
{
- return -ENOSYS;
-}
-
-static void cb_reboot(struct usb_ep *ep, struct usb_request *req)
-{
- char *cmd = req->buf;
- if (!strcmp_l1("reboot-bootloader", cmd)) {
- if (fb_set_reboot_flag()) {
- fastboot_tx_write_str("FAILCannot set reboot flag");
- return;
- }
- }
- fastboot_func->in_req->complete = compl_do_reset;
- fastboot_tx_write_str("OKAY");
-}
-
-static int strcmp_l1(const char *s1, const char *s2)
-{
- if (!s1 || !s2)
- return -1;
- return strncmp(s1, s2, strlen(s1));
-}
-
-static void cb_getvar(struct usb_ep *ep, struct usb_request *req)
-{
- char *cmd = req->buf;
- char response[FASTBOOT_RESPONSE_LEN];
- const char *s;
- size_t chars_left;
-
- strcpy(response, "OKAY");
- chars_left = sizeof(response) - strlen(response) - 1;
-
- strsep(&cmd, ":");
- if (!cmd) {
- pr_err("missing variable");
- fastboot_tx_write_str("FAILmissing var");
- return;
- }
-
- if (!strcmp_l1("version", cmd)) {
- strncat(response, FASTBOOT_VERSION, chars_left);
- } else if (!strcmp_l1("bootloader-version", cmd)) {
- strncat(response, U_BOOT_VERSION, chars_left);
- } else if (!strcmp_l1("downloadsize", cmd) ||
- !strcmp_l1("max-download-size", cmd)) {
- char str_num[12];
-
- sprintf(str_num, "0x%08x", CONFIG_FASTBOOT_BUF_SIZE);
- strncat(response, str_num, chars_left);
- } else if (!strcmp_l1("serialno", cmd)) {
- s = env_get("serial#");
- if (s)
- strncat(response, s, chars_left);
- else
- strcpy(response, "FAILValue not set");
-#ifdef CONFIG_G_AB_SYSTEM
- } else if (!strcmp_l1("slot-count", cmd)) {
- strncat(response, "2", chars_left);
- } else if (!strcmp_l1("slot-suffixes", cmd)) {
- s = env_get("slot-suffixes");
- printf("slot-suffixes: %s\n", s);
- if (s)
- strncat(response, s, chars_left);
- else
- strncat(response, "0", chars_left);
- } else if (!strcmp_l1("current-slot", cmd)) {
- s = env_get("active_slot");
- printf("active_slot: %s\n", s);
- strncat(response, s, chars_left);
- } else if (!strcmp_l1("has-slot:bootloader", cmd)) {
- printf("has bootloader slot\n");
- strncat(response, "yes", chars_left);
- } else if (!strcmp_l1("has-slot:boot", cmd)) {
- printf("has boot slot\n");
- strncat(response, "yes", chars_left);
- } else if (!strcmp_l1("has-slot:system", cmd)) {
- printf("has system slot\n");
- strncat(response, "yes", chars_left);
- } else if (!strcmp_l1("slot-successful", cmd)) {
- char str[128];
- strsep(&cmd, ":");
- printf("cmd is %s\n", cmd);
- int ret;
- if (has_boot_slot == 1) {
- sprintf(str, "get_slot_state %s successful", cmd);
- printf("command: %s\n", str);
- ret = run_command(str, 0);
- printf("ret = %d\n", ret);
- if (ret == 0)
- strncat(response, "no", chars_left);
- else
- strncat(response, "yes", chars_left);
- } else
- strcpy(response, "FAILVariable not implemented in non ab mode");
- } else if (!strcmp_l1("slot-unbootable", cmd)) {
- char str[128];
- strsep(&cmd, ":");
- printf("cmd is %s\n", cmd);
- int ret;
- if (has_boot_slot == 1) {
- printf("has boot slot\n");
- sprintf(str, "get_slot_state %s unbootable", cmd);
- printf("command: %s\n", str);
- ret = run_command(str, 0);
- printf("ret = %d\n", ret);
- if (ret == 0)
- strncat(response, "yes", chars_left);
- else
- strncat(response, "no", chars_left);
- } else
- strcpy(response, "FAILVariable not implemented in non ab mode");
- } else if (!strcmp_l1("slot-retry-count", cmd)) {
- char str[128];
- strsep(&cmd, ":");
- printf("cmd is %s\n", cmd);
- int ret;
- if (has_boot_slot == 1) {
- char str_num[12];
- char *retry_count;
- printf("has boot slot\n");
- sprintf(str, "get_slot_state %s retry-count", cmd);
- printf("command: %s\n", str);
- ret = run_command(str, 0);
- printf("ret = %d\n", ret);
-
- retry_count = env_get("cur_retry_count");
- strcpy(str_num, retry_count);
- strncat(response, str_num, chars_left);
- } else
- strcpy(response, "FAILVariable not implemented in non ab mode");
+#ifndef CONFIG_USB_GADGET_CRG
+ f_dwc_otg_pullup(0);
#endif
- } else {
- char *envstr;
-
- envstr = malloc(strlen("fastboot.") + strlen(cmd) + 1);
- if (!envstr) {
- fastboot_tx_write_str("FAILmalloc error");
- return;
- }
-
- sprintf(envstr, "fastboot.%s", cmd);
- s = env_get(envstr);
- if (s) {
- strncat(response, s, chars_left);
- } else {
- printf("WARNING: unknown variable: %s\n", cmd);
- strcpy(response, "FAILVariable not implemented");
- }
-
- free(envstr);
- }
- fastboot_tx_write_str(response);
+ if (dynamic_partition)
+ run_command("reboot bootloader", 0);
+ else
+ run_command("reboot fastboot", 0);
}
+static void compl_do_reboot_fastboot(struct usb_ep *ep, struct usb_request *req)
+{
+#ifndef CONFIG_USB_GADGET_CRG
+ f_dwc_otg_pullup(0);
+#endif
+ run_command("reboot fastboot", 0);
+}
+
+
static unsigned int rx_bytes_expected(struct usb_ep *ep)
{
int rx_remain = fastboot_data_remaining();
@@ -563,7 +467,6 @@
*/
req->complete = rx_handler_command;
req->length = EP_BUFFER_SIZE;
-
fastboot_tx_write_str(response);
} else {
req->length = rx_bytes_expected(ep);
@@ -586,10 +489,12 @@
static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
{
- char *cmdbuf = req->buf;
+ char cmdbuf[256];
char response[FASTBOOT_RESPONSE_LEN] = {0};
int cmd = -1;
+ strncpy(cmdbuf, req->buf, 255);
+
if (req->status != 0 || req->length == 0)
return;
@@ -600,40 +505,6 @@
pr_err("buffer overflow");
fastboot_fail("buffer overflow", response);
}
-}
-
-#ifdef CONFIG_G_AB_SYSTEM
-static void cb_set_active(struct usb_ep *ep, struct usb_request *req)
-{
- char *cmd = req->buf;
- int switch_flag = 0;
- int ret = 0;
- char str[128];
-
- printf("cmd cb_set_active is %s\n", cmd);
- strsep(&cmd, ":");
- if (!cmd) {
- pr_err("missing slot name\n");
- fastboot_tx_write_str("FAILmissing slot name");
- return;
- }
-
- sprintf(str, "set_active_slot %s %d", cmd, switch_flag);
- printf("command: %s\n", str);
- ret = run_command(str, 0);
- printf("ret = %d\n", ret);
- if (ret == 0)
- fastboot_tx_write_str("OKAY");
- else
- fastboot_tx_write_str("FAILset slot error");
-}
-#endif
-
-#ifdef CONFIG_FASTBOOT_FLASH
-static void cb_erase(struct usb_ep *ep, struct usb_request *req)
-{
- char *cmd = req->buf;
- char response[FASTBOOT_RESPONSE_LEN];
if (!strncmp("DATA", response, 4)) {
req->complete = rx_handler_dl_image;
@@ -641,57 +512,6 @@
}
fastboot_tx_write_str(response);
-}
-#endif
-
-struct cmd_dispatch_info {
- char *cmd;
- void (*cb)(struct usb_ep *ep, struct usb_request *req);
-};
-
-static const struct cmd_dispatch_info cmd_dispatch_info[] = {
- {
- .cmd = "reboot",
- .cb = cb_reboot,
- }, {
- .cmd = "getvar:",
- .cb = cb_getvar,
- }, {
- .cmd = "download:",
- .cb = cb_download,
- }, {
- .cmd = "boot",
- .cb = cb_boot,
- }, {
- .cmd = "continue",
- .cb = cb_continue,
- },
-#ifdef CONFIG_FASTBOOT_FLASH
- {
- .cmd = "flash",
- .cb = cb_flash,
- }, {
- .cmd = "erase",
- .cb = cb_erase,
- },
-#endif
- {
- .cmd = "oem",
- .cb = cb_oem,
- },
-#ifdef CONFIG_G_AB_SYSTEM
- {
- .cmd = "set_active",
- .cb = cb_set_active,
- },
-#endif
-};
-
-static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
-{
- char *cmdbuf = req->buf;
- void (*func_cb)(struct usb_ep *ep, struct usb_request *req) = NULL;
- int i;
if (!strncmp("OKAY", response, 4)) {
switch (cmd) {
@@ -704,13 +524,20 @@
break;
case FASTBOOT_COMMAND_REBOOT:
- case FASTBOOT_COMMAND_REBOOT_BOOTLOADER:
fastboot_func->in_req->complete = compl_do_reset;
break;
+ case FASTBOOT_COMMAND_REBOOT_BOOTLOADER:
+ fastboot_func->in_req->complete = compl_do_reboot_bootloader;
+ break;
+ case FASTBOOT_COMMAND_REBOOT_FASTBOOT:
+ fastboot_func->in_req->complete = compl_do_reboot_fastboot;
+ break;
}
}
- *cmdbuf = '\0';
- req->actual = 0;
- usb_ep_queue(ep, req, 0);
+ if (busy_flag == 0) {
+ *cmdbuf = '\0';
+ req->actual = 0;
+ usb_ep_queue(ep, req, 0);
+ }
}
diff --git a/drivers/usb/gadget/fastboot/dwc_pcd.c b/drivers/usb/gadget/fastboot/dwc_pcd.c
index 9ba23d0..f9e9699 100644
--- a/drivers/usb/gadget/fastboot/dwc_pcd.c
+++ b/drivers/usb/gadget/fastboot/dwc_pcd.c
@@ -1,16 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (c) 2015 Amlogic, Inc. All rights reserved.
- *
- * This source code is subject to the terms and conditions defined in the
- * file 'LICENSE' which is part of this source code package.
- *
- * USB low level routines
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "usb_boot.h"
#include "usb_ch9.h"
#include "dwc_pcd.h"
#include "dwc_pcd_irq.h"
-#include "platform.c"
+#include "../platform.h"
gadget_wrapper_t gadget_wrapper;
@@ -125,7 +122,7 @@
DBG("\ndwc_otg core init enter!\n");
- f_set_usb_phy_config();
+ set_usb_phy_config(0);
if (0x4F543000 != (dwc_read_reg32(DWC_REG_GSNPSID) & 0xFFFFF000)) {
ERR("Bad value for SNPSID\n");
@@ -201,6 +198,12 @@
return 0;
}
+void f_dwc_otg_pullup(int is_on)
+{
+ if (is_on)
+ dwc_modify_reg32(DWC_REG_DCTL,2,0);// connect data line
+ else dwc_modify_reg32(DWC_REG_DCTL,0,2);// disconnect data line
+}
int usb_pcd_irq_loop()
@@ -334,7 +337,7 @@
if (pcd->dwc_eps[0].priv == handle)
return &pcd->dwc_eps[0];
- for (i = 1; i < 5; i++) {
+ for (i = 1; i < NUM_EP; i++) {
if (pcd->dwc_eps[i].priv == handle) {
return &pcd->dwc_eps[i];
}
@@ -349,7 +352,7 @@
{
pcd_struct_t *pcd;
struct dwc_otg_pcd_ep *ep = NULL;
- int retval = 0;
+// int retval = 0;
if (!usb_req || !usb_req->complete || !usb_req->buf) {
printf("bad params\n");
@@ -383,8 +386,11 @@
pcd_queue(ep->dwc_ep.num, ep->dwc_ep.is_in, usb_req);
+ /*deadcode
+ *
if (retval)
return -3;
+ */
return 0;
}
@@ -597,19 +603,12 @@
&& driver->speed != USB_SPEED_HIGH)
|| !driver->bind || !driver->disconnect || !driver->setup)
return -EINVAL;
- if (!dev)
- return -ENODEV;
if (dev->driver)
return -EBUSY;
/* first hook up the driver ... */
dev->driver = driver;
- if (retval) { /* TODO */
- printf("target device_add failed, error %d\n", retval);
- return retval;
- }
-
ep = &gadget_wrapper.pcd.dwc_eps[0];
dwc_otg_pcd_init_ep(&gadget_wrapper.pcd, ep, 0, 0);
@@ -628,6 +627,7 @@
retval = driver->bind(&dev->gadget);
if (retval) {
dev->driver = 0;
+ printf("target device_add failed, error %d\n", retval);
return retval;
}
@@ -640,8 +640,6 @@
{
gadget_wrapper_t *dev = &gadget_wrapper;
- if (!dev)
- return -ENODEV;
if (!driver || driver != dev->driver)
return -EINVAL;
@@ -685,7 +683,7 @@
if (!sof) {
ERR("sof timeout, reset usb phy tuning\n");
- set_usb_phy21_tuning_fb_reset();
+ set_usb_phy21_tuning_update_reset();
mdelay(150);
}
diff --git a/drivers/usb/gadget/fastboot/dwc_pcd.h b/drivers/usb/gadget/fastboot/dwc_pcd.h
index cc5ab35..5f9fbd4 100644
--- a/drivers/usb/gadget/fastboot/dwc_pcd.h
+++ b/drivers/usb/gadget/fastboot/dwc_pcd.h
@@ -1,10 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Copyright (c) 2015 Amlogic, Inc. All rights reserved.
- *
- * This source code is subject to the terms and conditions defined in the
- * file 'LICENSE' which is part of this source code package.
- *
- * USB low level defines
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __DWC_PCD_H__
diff --git a/drivers/usb/gadget/fastboot/dwc_pcd_irq.c b/drivers/usb/gadget/fastboot/dwc_pcd_irq.c
index ce4dc9b..92bb0d1 100644
--- a/drivers/usb/gadget/fastboot/dwc_pcd_irq.c
+++ b/drivers/usb/gadget/fastboot/dwc_pcd_irq.c
@@ -1,17 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright (c) 2015 Amlogic, Inc. All rights reserved.
- *
- * This source code is subject to the terms and conditions defined in the
- * file 'LICENSE' which is part of this source code package.
- *
- * USB low level irq routines
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include "usb_boot.h"
#include "usb_ch9.h"
#include "dwc_pcd.h"
#include "dwc_pcd_irq.h"
-#include "platform.h"
+#include "../platform.h"
static void ep0_out_start(void);
static int ep0_complete_request( pcd_struct_t * pcd);
@@ -670,7 +666,7 @@
printf("SPEED ENUM\n");
#ifdef CONFIG_USB_DEVICE_V2
- set_usb_phy21_tuning_fb();
+ set_usb_phy21_tuning_update();
#endif
gadget_wrapper.pcd.ep0state = EP0_IDLE;
@@ -1042,9 +1038,10 @@
dwc_write_reg32 (DWC_REG_GINTSTS, gintsts.d32);
}
+unsigned int _sofintr_not_occur;
#if (defined CONFIG_USB_DEVICE_V2)
-extern unsigned int fb_sofintr;
-extern unsigned fb_curTime_sof;
+unsigned int _sofintr;
+unsigned curTime_sof;
#endif
int f_dwc_pcd_irq(void)
@@ -1065,22 +1062,26 @@
gotgint.d32 = dwc_read_reg32(DWC_REG_GOTGINT);
if (gotgint.b.sesreqsucstschng)
- ERR("Session Request Success Status Change\n");
+ printf("Session Request Success Status Change\n");
else if (gotgint.b.sesenddet) {
/*break to romboot*/
- ERR("Session End Detected\n");
+ printf("Session End Detected\n");
ret = 11;
}
/* clear intr */
dwc_write_reg32(DWC_REG_GOTGINT, gotgint.d32);
+ if (gintr_status.b.sofintr) {
#if (defined CONFIG_USB_DEVICE_V2)
- if (gintr_status.b.sofintr) {
- fb_curTime_sof = get_timer(0);
- fb_sofintr = 1;
- }
+ curTime_sof = get_timer(0);
+ _sofintr = 1;
#endif
+ if (_sofintr_not_occur) {
+ printf("sof\n");
+ _sofintr_not_occur = 0;
+ }
+ }
if (gintr_status.b.rxstsqlvl) {
dwc_otg_pcd_handle_rx_status_q_level_intr();
diff --git a/drivers/usb/gadget/fastboot/dwc_pcd_irq.h b/drivers/usb/gadget/fastboot/dwc_pcd_irq.h
index 4e595ab..3930774 100644
--- a/drivers/usb/gadget/fastboot/dwc_pcd_irq.h
+++ b/drivers/usb/gadget/fastboot/dwc_pcd_irq.h
@@ -1,11 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Copyright (c) 2015 Amlogic, Inc. All rights reserved.
- *
- * This source code is subject to the terms and conditions defined in the
- * file 'LICENSE' which is part of this source code package.
- *
- * USB low level irq defines
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#ifndef __DWC_PCD_IRQ_H__
#define __DWC_PCD_IRQ_H__
diff --git a/drivers/usb/gadget/fastboot/platform.c b/drivers/usb/gadget/fastboot/platform.c
deleted file mode 100644
index e38bcba..0000000
--- a/drivers/usb/gadget/fastboot/platform.c
+++ /dev/null
@@ -1,572 +0,0 @@
-/* platform dirver header */
-/*
- * (C) Copyright 2010 Amlogic, Inc
- *
- * Victor Wan, victor.wan@amlogic.com,
- * 2010-03-24 @ Shanghai
- *
- */
- #include "platform.h"
-#include <asm/arch/cpu_id.h>
-#include <asm/arch/secure_apb.h>
-
-/*CONFIG_AML_MESON_8 include m8, m8baby, m8m2, etc... defined in cpu.h*/
-#if !(defined(CONFIG_USB_XHCI_HCD) || defined(CONFIG_USB_DWC_OTG_294))
-#error "platform is not GX !!"
-#endif
-#if !(defined (CONFIG_USB_DEVICE_V2))
-#error "define CONFIG_USB_DEVICE_V2 !!"
-
-#endif
-
-
-#if (defined CONFIG_USB_XHCI_HCD)
-#if (defined AML_TXLX_USB)
-#define PREI_USB_PHY_2_REG_BASE 0xffe09020
-#define PREI_USB_PHY_3_REG_BASE 0xffe09080
-#else
-#define PREI_USB_PHY_2_REG_BASE 0xd0078020
-#define PREI_USB_PHY_3_REG_BASE 0xd0078080
-#endif
-
-#if (defined CONFIG_USB_DEVICE_V2)
-typedef struct u2p_aml_regs {
- volatile uint32_t u2p_r0;
- volatile uint32_t u2p_r1;
-} u2p_aml_regs_t;
-
-typedef union u2p_r0 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned host_device:1;
- unsigned power_ok:1;
- unsigned hast_mode:1;
- unsigned POR:1;
- unsigned IDPULLUP0:1;
- unsigned DRVVBUS0:1;
- unsigned reserved:26;
- } b;
-} u2p_r0_t;
-
-typedef union u2p_r1 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned phy_rdy:1;
- unsigned IDDIG0:1;
- unsigned OTGSESSVLD0:1;
- unsigned VBUSVALID0:1;
- unsigned reserved:28;
- } b;
-} u2p_r1_t;
-
-typedef struct usb_aml_regs {
- volatile uint32_t usb_r0;
- volatile uint32_t usb_r1;
- volatile uint32_t usb_r2;
- volatile uint32_t usb_r3;
- volatile uint32_t usb_r4;
- volatile uint32_t usb_r5;
-} usb_aml_regs_t;
-
-typedef union usb_r0 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned reserved:17;
- unsigned p30_lane0_tx2rx_loopback:1;
- unsigned p30_lane0_ext_pclk_reg:1;
- unsigned p30_pcs_rx_los_mask_val:10;
- unsigned u2d_ss_scaledown_mode:2;
- unsigned u2d_act:1;
- } b;
-} usb_r0_t;
-
-typedef union usb_r1 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned u3h_bigendian_gs:1;
- unsigned u3h_pme_en:1;
- unsigned u3h_hub_port_overcurrent:3;
- unsigned reserved_1:2;
- unsigned u3h_hub_port_perm_attach:3;
- unsigned reserved_2:2;
- unsigned u3h_host_u2_port_disable:2;
- unsigned reserved_3:2;
- unsigned u3h_host_u3_port_disable:1;
- unsigned u3h_host_port_power_control_present:1;
- unsigned u3h_host_msi_enable:1;
- unsigned u3h_fladj_30mhz_reg:6;
- unsigned p30_pcs_tx_swing_full:7;
- } b;
-} usb_r1_t;
-
-typedef union usb_r2 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned reserved:20;
- unsigned p30_pcs_tx_deemph_3p5db:6;
- unsigned p30_pcs_tx_deemph_6db:6;
- } b;
-} usb_r2_t;
-
-typedef union usb_r3 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned p30_ssc_en:1;
- unsigned p30_ssc_range:3;
- unsigned p30_ssc_ref_clk_sel:9;
- unsigned p30_ref_ssp_en:1;
- unsigned reserved:18;
- } b;
-} usb_r3_t;
-
-typedef union usb_r4 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned p21_PORTRESET0:1;
- unsigned p21_SLEEPM0:1;
- unsigned mem_pd:2;
- unsigned p21_only:1;
- unsigned reserved:27;
- } b;
-} usb_r4_t;
-
-typedef union usb_r5 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned iddig_sync:1;
- unsigned iddig_reg:1;
- unsigned iddig_cfg:2;
- unsigned iddig_en0:1;
- unsigned iddig_en1:1;
- unsigned iddig_curr:1;
- unsigned usb_iddig_irq:1;
- unsigned iddig_th:8;
- unsigned iddig_cnt:8;
- unsigned reserved:8;
- } b;
-} usb_r5_t;
-
-static int f_platform_usb_check_rev(void)
-{
- int rev_flag = 0;
-
- cpu_id_t cpu_id = get_cpu_id();
-
- if (cpu_id.family_id == MESON_CPU_MAJOR_ID_G12B) {
- if (cpu_id.chip_rev == 0xb)
- rev_flag = 0xb;
- else
- rev_flag = 0;
- } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SM1){
- rev_flag = MESON_CPU_MAJOR_ID_SM1;
- }
-
- return rev_flag;
-}
-
-#define PLL_REG32_16 (0xFF63A000 + 0x40)
-#define PLL_REG32_17 (0xFF63A000 + 0x44)
-#define PLL_REG32_18 (0xFF63A000 + 0x48)
-#define USB_PHY2_ENABLE 0x10000000
-#define USB_PHY2_RESET 0x20000000
-
-static void set_usb_phy21_pll(void)
-{
- (*(volatile uint32_t *)(unsigned long)(PLL_REG32_16))
- = (USB_PHY2_PLL_PARAMETER_1 | USB_PHY2_RESET | USB_PHY2_ENABLE);
- (*(volatile uint32_t *)(unsigned long)(PLL_REG32_17)) =
- USB_PHY2_PLL_PARAMETER_2;
- if (f_platform_usb_check_rev() == MESON_CPU_MAJOR_ID_SM1)
- (*(volatile uint32_t *)(unsigned long)(PLL_REG32_18)) =
- 0xAC5F69E5;
- else
- (*(volatile uint32_t *)(unsigned long)(PLL_REG32_18)) =
- USB_PHY2_PLL_PARAMETER_3;
- udelay(100);
- (*(volatile uint32_t *)(unsigned long)(PLL_REG32_16))
- = (((USB_PHY2_PLL_PARAMETER_1) | (USB_PHY2_ENABLE))
- & (~(USB_PHY2_RESET)));
-}
-
-#ifdef CONFIG_USB_DEVICE_V2
-#define USB_REG_B 0xFF63A000
-
-void set_usb_phy21_tuning_fb(void)
-{
- unsigned long phy_reg_base = USB_REG_B;
-
- if (f_platform_usb_check_rev()) {
- (*(volatile uint32_t *)(phy_reg_base + 0x50)) = USB_G12x_PHY_PLL_SETTING_1;
- (*(volatile uint32_t *)(phy_reg_base + 0x54)) = 0x2a;
- (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB_G12x_PHY_PLL_SETTING_3 & (0x1f << 16);
- return;
- }
-
- (*(volatile uint32_t *)(phy_reg_base + 0x10)) = USB_G12x_PHY_PLL_SETTING_2;
- (*(volatile uint32_t *)(phy_reg_base + 0x50)) = USB_G12x_PHY_PLL_SETTING_1;
- (*(volatile uint32_t *)(phy_reg_base + 0x38)) = USB_G12x_PHY_PLL_SETTING_5;
- (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB_G12x_PHY_PLL_SETTING_3;
-}
-
-void set_usb_phy21_tuning_fb_reset(void)
-{
- unsigned long phy_reg_base = USB_REG_B;
-
- if (f_platform_usb_check_rev())
- return;
-
- (*(volatile uint32_t *)(phy_reg_base + 0x38)) = 0x0;
- (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB_G12x_PHY_PLL_SETTING_3;
-}
-
-#endif
-
-#if (defined AML_TXLX_USB)
-#define USB_RESET1 (volatile unsigned long *)0xffd04408
-#else
-#define USB_RESET1 (volatile unsigned long *)0xc1104408
-#endif
-
-void f_set_usb_phy_config(void)
-{
- u2p_r0_t dev_u2p_r0;
- u2p_r1_t dev_u2p_r1;
-
- usb_r0_t dev_usb_r0;
- usb_r4_t dev_usb_r4;
-
- u2p_aml_regs_t * u2p_aml_regs = (u2p_aml_regs_t * )PREI_USB_PHY_2_REG_BASE;
- usb_aml_regs_t *usb_aml_regs = (usb_aml_regs_t * )PREI_USB_PHY_3_REG_BASE;
- int cnt;
- u32 val;
-
- if (f_platform_usb_check_rev() == MESON_CPU_MAJOR_ID_SM1) {
- val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_SLEEP0;
- *P_AO_RTI_GEN_PWR_SLEEP0 = val & (~(0x1<<17));
- val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_ISO0;
- *P_AO_RTI_GEN_PWR_ISO0 = val & (~(0x1<<17));
- val = *(volatile uint32_t *)HHI_MEM_PD_REG0;
- *P_HHI_MEM_PD_REG0 = val & (~(0x3<<30));
- }
-
- printf("PHY2=0x%08x\n", PREI_USB_PHY_2_REG_BASE);
-#ifdef CONFIG_USB_DEVICE_V2
- if ((*(volatile uint32_t *)(USB_REG_B + 0x38)) != 0) {
- set_usb_phy21_tuning_fb_reset();
- mdelay(150);
- }
-#endif
-
- //step 1: usb controller reset
- *USB_RESET1 |= (1<<2);
-
- // step 3: enable usb INT internal USB
- dev_usb_r0.d32 = usb_aml_regs->usb_r0;
- dev_usb_r0.b.u2d_ss_scaledown_mode = 0;
- dev_usb_r0.b.u2d_act = 1;
- usb_aml_regs->usb_r0 = dev_usb_r0.d32;
-
- // step 4: disable usb phy sleep
- dev_usb_r4.d32 = usb_aml_regs->usb_r4;
- dev_usb_r4.b.p21_SLEEPM0 = 1;
- usb_aml_regs->usb_r4 = dev_usb_r4.d32;
-
- // step 5: config phy21 device mode
- dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0;
- dev_u2p_r0.b.host_device= 0;
- dev_u2p_r0.b.POR= 0;
- u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32;
-
- udelay(10);
- //step 6: phy21 reset
- *USB_RESET1 |= (1<<17);
-
- udelay(50);
- // step 6: wait for phy ready
- dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
- cnt = 0;
- while ((dev_u2p_r1.d32 & 0x00000001) != 1) {
- dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
- if (cnt > 200)
- break;
- else {
- cnt++;
- udelay(5);
- }
- }
-
- set_usb_phy21_pll();
- //--------------------------------------------------
-
- // ------------- usb phy21 initinal end ----------
-
- //--------------------------------------------------
-
-}
-
-#else
-typedef struct u2p_aml_regs {
- volatile uint32_t u2p_r0;
- volatile uint32_t u2p_r1;
- volatile uint32_t u2p_r2;
-} u2p_aml_regs_t;
-
-typedef union u2p_r0 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned bypass_sel:1;
- unsigned bypass_dm_en:1;
- unsigned bypass_dp_en:1;
- unsigned txbitstuffenh:1;
- unsigned txbitstuffen:1;
- unsigned dmpulldown:1;
- unsigned dppulldown:1;
- unsigned vbusvldextsel:1;
- unsigned vbusvldext:1;
- unsigned adp_prb_en:1;
- unsigned adp_dischrg:1;
- unsigned adp_chrg:1;
- unsigned drvvbus:1;
- unsigned idpullup:1;
- unsigned loopbackenb:1;
- unsigned otgdisable:1;
- unsigned commononn:1;
- unsigned fsel:3;
- unsigned refclksel:2;
- unsigned por:1;
- unsigned vatestenb:2;
- unsigned set_iddq:1;
- unsigned ate_reset:1;
- unsigned fsv_minus:1;
- unsigned fsv_plus:1;
- unsigned bypass_dm_data:1;
- unsigned bypass_dp_data:1;
- unsigned not_used:1;
- } b;
-} u2p_r0_t;
-
-typedef struct usb_aml_regs {
- volatile uint32_t usb_r0;
- volatile uint32_t usb_r1;
- volatile uint32_t usb_r2;
- volatile uint32_t usb_r3;
- volatile uint32_t usb_r4;
- volatile uint32_t usb_r5;
- volatile uint32_t usb_r6;
-} usb_aml_regs_t;
-
-typedef union usb_r0 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned p30_fsel:6;
- unsigned p30_phy_reset:1;
- unsigned p30_test_powerdown_hsp:1;
- unsigned p30_test_powerdown_ssp:1;
- unsigned p30_acjt_level:5;
- unsigned p30_tx_vboost_lvl:3;
- unsigned p30_lane0_tx2rx_loopbk:1;
- unsigned p30_lane0_ext_pclk_req:1;
- unsigned p30_pcs_rx_los_mask_val:10;
- unsigned u2d_ss_scaledown_mode:2;
- unsigned u2d_act:1;
- } b;
-} usb_r0_t;
-
-typedef union usb_r4 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned p21_PORTRESET0:1;
- unsigned p21_SLEEPM0:1;
- unsigned mem_pd:2;
- unsigned reserved4:28;
- } b;
-} usb_r4_t;
-
-#if (defined AML_TXLX_USB)
-#define P_RESET1_REGISTER (volatile unsigned long *)0xffd01008
-#define P_AO_RTC_ALT_CLK_CNTL0 (volatile uint32_t *)(0xff800000 + (0x25 << 2))
-#define P_AO_RTI_PWR_CNTL_REG0 (volatile uint32_t *)(0xff800000 + (0x04 << 2))
-#else
-#define P_RESET1_REGISTER (volatile unsigned long *)0xc1104408
-#define P_AO_RTC_ALT_CLK_CNTL0 (volatile uint32_t *)(0xc8100000 + (0x25 << 2))
-#define P_AO_RTI_PWR_CNTL_REG0 (volatile uint32_t *)(0xc8100000 + (0x04 << 2))
-#endif
-
-void f_set_usb_phy_config(void)
-{
- const int time_dly = 500;
- u2p_aml_regs_t * u2p_aml_regs = (u2p_aml_regs_t * )PREI_USB_PHY_2_REG_BASE;
- usb_aml_regs_t * usb_aml_regs = (usb_aml_regs_t * )PREI_USB_PHY_3_REG_BASE;
-
- u2p_r0_t u2p_r0;
- usb_r0_t usb_r0;
- usb_r4_t usb_r4;
-
- *P_RESET1_REGISTER = (1<<2);
-
- *P_AO_RTC_ALT_CLK_CNTL0 |= (1<<31)|(1<<30);
- *P_AO_RTI_PWR_CNTL_REG0 |= (4<<10);
-
- u2p_r0.d32 = u2p_aml_regs->u2p_r0;
-#if (defined CONFIG_AML_MESON_GXTVBB)
- u2p_r0.b.fsel = 5;
-
-#elif (defined CONFIG_AML_MESON_GXL)
- u2p_r0.b.fsel = 2;
-#endif
- u2p_r0.b.por = 1;
- u2p_r0.b.dppulldown = 0;
- u2p_r0.b.dmpulldown = 0;
- u2p_aml_regs->u2p_r0 = u2p_r0.d32;
-
- u2p_r0.d32 = u2p_aml_regs->u2p_r0;
- u2p_r0.b.por = 0;
- u2p_aml_regs->u2p_r0 = u2p_r0.d32;
-
- usb_r0.d32 = usb_aml_regs->usb_r0;
- usb_r0.b.u2d_act = 1;
- usb_aml_regs->usb_r0 = usb_r0.d32;
-
- usb_r4.d32 = usb_aml_regs->usb_r4;
- usb_r4.b.p21_SLEEPM0 = 1;
- usb_aml_regs->usb_r4 = usb_r4.d32;
-
- udelay(time_dly);
- return;
-}
-#endif
-
-#endif
-
-#if (defined CONFIG_USB_DWC_OTG_294)
-
-/*
- cfg = 0 : EXT clock
- cfg = 1 : INT clock
- */
-
-#define PREI_USB_PHY_A_REG_BASE 0xC0000000
-#define PREI_USB_PHY_B_REG_BASE 0xC1108420
-
-#ifdef __USE_PORT_B
-#define PREI_USB_PHY_REG_BASE PREI_USB_PHY_B_REG_BASE
-#else
-#define PREI_USB_PHY_REG_BASE PREI_USB_PHY_A_REG_BASE
-#endif
-#define P_RESET1_REGISTER_USB (volatile unsigned long *)0xc1104408
-
-#define USB_CLK_SEL_XTAL 0
-#define USB_CLK_SEL_XTAL_DIV_2 1
-#define USB_CLK_SEL_DDR_PLL 2
-#define USB_CLK_SEL_MPLL_OUT0 3
-#define USB_CLK_SEL_MPLL_OUT1 4
-#define USB_CLK_SEL_MPLL_OUT2 5
-#define USB_CLK_SEL_FCLK_DIV2 6
-#define USB_CLK_SEL_FCLK_DIV3 7
-
-typedef struct usb_aml_regs {
- volatile uint32_t config;
- volatile uint32_t ctrl;
- volatile uint32_t endp_intr;
- volatile uint32_t adp_bc;
- volatile uint32_t dbg_uart;
- volatile uint32_t test;
- volatile uint32_t tune;
-} usb_aml_regs_t;
-
-typedef union usb_config_data {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned clk_en :1;
- unsigned clk_sel :3;
- unsigned clk_div :7;
- unsigned reserved0 :1;
- unsigned clk_32k_alt_sel:1;
- unsigned reserved1 :15;
- unsigned test_trig :1;
- } b;
-} usb_config_data_t;
-
-typedef union usb_ctrl_data {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned soft_prst:1;
- unsigned soft_hreset:1;
- unsigned ss_scaledown_mode:2;
- unsigned clk_det_rst:1;
- unsigned intr_sel:1;
- unsigned reserved:2;
- unsigned clk_detected:1;
- unsigned sof_sent_rcvd_tgl:1;
- unsigned sof_toggle_out:1;
- unsigned not_used:4;
- unsigned por:1;
- unsigned sleepm:1;
- unsigned txbitstuffennh:1;
- unsigned txbitstuffenn:1;
- unsigned commononn:1;
- unsigned refclksel:2;
- unsigned fsel:3;
- unsigned portreset:1;
- unsigned thread_id:6;
- } b;
-} usb_ctrl_data_t;
-
-void f_set_usb_phy_config(void)
-{
- const int time_dly = 5000;
- usb_aml_regs_t * usb_aml_regs = (usb_aml_regs_t * )PREI_USB_PHY_REG_BASE;
- usb_config_data_t config;
- usb_ctrl_data_t control;
-
- *P_RESET1_REGISTER_USB = (1<<2);
- udelay(time_dly);
-
- config.d32 = usb_aml_regs->config;
- usb_aml_regs->config = config.d32;
-
- control.d32 = usb_aml_regs->ctrl;
- control.b.fsel = 5;
- control.b.por = 1;
- usb_aml_regs->ctrl = control.d32;
- udelay(time_dly);
-
- control.b.por = 0;
- usb_aml_regs->ctrl = control.d32;
- udelay(time_dly);
-
- control.d32 = usb_aml_regs->ctrl;
- if (!control.b.clk_detected) {
- printf("Error, usb phy clock not detected!\n");
- }
-
- return;
-}
-
-#endif
diff --git a/drivers/usb/gadget/fastboot/platform.h b/drivers/usb/gadget/fastboot/platform.h
deleted file mode 100644
index 39a7a4e..0000000
--- a/drivers/usb/gadget/fastboot/platform.h
+++ /dev/null
@@ -1,113 +0,0 @@
-/* platform header */
-/*
- * (C) Copyright 2010 Amlogic, Inc
- *
- * Victor Wan, victor.wan@amlogic.com,
- * 2010-03-24 @ Shanghai
- *
- */
-
-#ifndef __PLATFORM_H__
-#define __PLATFORM_H__
-
-#include <asm/arch/register.h>
-
-/* A3,CS2,M3 chip, PORT_A is OTG, work as ROM Boot port */
-#ifdef __USE_PORT_B
-#define PORT_REG_OFFSET 0x80000
-#else
-#define PORT_REG_OFFSET 0
-#endif
-
-#if (defined AML_TXLX_USB)
-#if ((defined CONFIG_USB_XHCI_HCD))
-#define DWC_REG_BASE 0xff400000
-#else
-#define DWC_REG_BASE (0xff500000 + PORT_REG_OFFSET)
-#endif
-#else
-#if ((defined CONFIG_USB_XHCI_HCD))
-#define DWC_REG_BASE 0xc9100000
-#else
-#define DWC_REG_BASE (0xC9000000 + PORT_REG_OFFSET)
-#endif
-#endif
-
-#define PREI_USB_PHY_A_POR (1 << 0)
-#define PREI_USB_PHY_B_POR (1 << 1)
-#define PREI_USB_PHY_CLK_SEL (7 << 5)
-#define PREI_USB_PHY_CLK_GATE (1 << 8)
-#define PREI_USB_PHY_B_AHB_RSET (1 << 11)
-#define PREI_USB_PHY_B_CLK_RSET (1 << 12)
-#define PREI_USB_PHY_B_PLL_RSET (1 << 13)
-#define PREI_USB_PHY_A_AHB_RSET (1 << 17)
-#define PREI_USB_PHY_A_CLK_RSET (1 << 18)
-#define PREI_USB_PHY_A_PLL_RSET (1 << 19)
-#define PREI_USB_PHY_A_DRV_VBUS (1 << 20)
-#define PREI_USB_PHY_B_DRV_VBUS (1 << 21)
-#define PREI_USB_PHY_B_CLK_DETECT (1 << 22)
-#define PREI_USB_PHY_CLK_DIV (0x7f << 24)
-#define PREI_USB_PHY_A_CLK_DETECT (1 << 31)
-
-#define PREI_USB_PHY_A_REG3_IDDIG_OVR (1 << 23)
-#define PREI_USB_PHY_A_REG3_IDDIG_VAL (1 << 24)
-
-#define PREI_USB_PHY_B_REG4_IDDIG_OVR (1 << 23)
-#define PREI_USB_PHY_B_REG4_IDDIG_VAL (1 << 24)
-
-#define IREG_TIMER_E_COUNT 0x2655
-
-
-#define flush_cpu_cache()
-
-
-#define dwc_write_reg32(x, v) (*(volatile uint32_t *)(unsigned long)(x + DWC_REG_BASE))=v
-#define dwc_read_reg32(x) (*(volatile uint32_t*)(unsigned long)(x + DWC_REG_BASE))
-#define dwc_modify_reg32(x, c, s) (*(volatile uint32_t *)(x + DWC_REG_BASE))=( ((dwc_read_reg32(x)) & (~c)) | (s))
-
-#define get_unaligned(ptr) ( ((unsigned long)ptr & 3) ? \
- (((__u8 *)ptr)[0] | (((__u8 *)ptr)[1]<<8) | (((__u8 *)ptr)[2]<<16) | (((__u8 *)ptr)[3]<<24)) : \
- (*(uint32_t*)ptr) )
-#define get_unaligned_16(ptr) (((__u8 *)ptr)[0] | (((__u8 *)ptr)[1]<<8))
-#define get_unaligned_32(ptr) (((__u8 *)ptr)[0] | (((__u8 *)ptr)[1]<<8) | (((__u8 *)ptr)[2]<<16) | (((__u8 *)ptr)[3]<<24))
-
-#define EXT_CLOCK 0
-#define INT_CLOCK 1
-
-#define USB_ROM_CONN_TIMEOUT 5*1000*1000
-
-
-/* Meet with spec */
-#define USB_ROM_VER_MAJOR 0
-#define USB_ROM_STAGE_MAJOR 0
-#define USB_ROM_STAGE_MINOR 16
-
-#ifdef CONFIG_M6
-#define USB_ROM_VER_MINOR 8
-#else
-#define USB_ROM_VER_MINOR 7
-#endif
-
-#define PRINTF(x...) do{}while(0)
-
-#define ERR(x...) printf(x)
-#define DBG(x...) PRINTF(x)
-
-#define USB_ERR(x...) printf("USBErr:%d", __LINE__),printf(x)
-#define USB_DBG(x...) PRINTF(x)
-
-
-void f_set_usb_phy_config(void);
-#ifdef CONFIG_USB_DEVICE_V2
-void set_usb_phy21_tuning_fb(void);
-#endif
-
-void usb_parameter_init(int timeout);
-int chip_utimer_set(int val);
-int chip_watchdog(void);
-#define udelay __udelay
-#define wait_ms(a) udelay(a*1000);
-int update_utime(void);
-int get_utime(void);
-
-#endif
diff --git a/drivers/usb/gadget/fastboot/usb_boot.h b/drivers/usb/gadget/fastboot/usb_boot.h
index 0349afa..80dd375 100644
--- a/drivers/usb/gadget/fastboot/usb_boot.h
+++ b/drivers/usb/gadget/fastboot/usb_boot.h
@@ -1,10 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Copyright (c) 2015 Amlogic, Inc. All rights reserved.
- *
- * This source code is subject to the terms and conditions defined in the
- * file 'LICENSE' which is part of this source code package.
- *
- * USB top level defines
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __USB_BOOT_H__
diff --git a/drivers/usb/gadget/fastboot/usb_ch9.h b/drivers/usb/gadget/fastboot/usb_ch9.h
index f2a448f..8e91830 100644
--- a/drivers/usb/gadget/fastboot/usb_ch9.h
+++ b/drivers/usb/gadget/fastboot/usb_ch9.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __LINUX_USB_CH9_H
#define __LINUX_USB_CH9_H
diff --git a/drivers/usb/gadget/g_dnl.c b/drivers/usb/gadget/g_dnl.c
index e9e1600..a32c123 100644
--- a/drivers/usb/gadget/g_dnl.c
+++ b/drivers/usb/gadget/g_dnl.c
@@ -43,9 +43,19 @@
#define DRIVER_VERSION "usb_dnl 2.0"
+#ifdef CONFIG_PRODUCT_NAME
+static const char product[] = CONFIG_PRODUCT_NAME;
+#else
static const char product[] = "USB download gadget";
+#endif
+
static char g_dnl_serial[MAX_STRING_SERIAL];
-static const char manufacturer[] = CONFIG_USB_GADGET_MANUFACTURER;
+
+#ifdef CONFIG_VENDOR_NAME
+const static char manufacturer[] = CONFIG_VENDOR_NAME;
+#else
+static const char manufacturer[] = "Amlogic";
+#endif
void g_dnl_set_serialnumber(char *s)
{
@@ -61,8 +71,8 @@
.bDeviceClass = USB_CLASS_PER_INTERFACE,
.bDeviceSubClass = 0, /*0x02:CDC-modem , 0x00:CDC-serial*/
- .idVendor = __constant_cpu_to_le16(CONFIG_USB_GADGET_VENDOR_NUM),
- .idProduct = __constant_cpu_to_le16(CONFIG_USB_GADGET_PRODUCT_NUM),
+ .idVendor = 0x18d1,
+ .idProduct = 0x4ee0,
/* .iProduct = DYNAMIC */
/* .iSerialNumber = DYNAMIC */
.bNumConfigurations = 1,
diff --git a/drivers/usb/gadget/platform.c b/drivers/usb/gadget/platform.c
new file mode 100644
index 0000000..263f92e
--- /dev/null
+++ b/drivers/usb/gadget/platform.c
@@ -0,0 +1,72 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "platform.h"
+#include <amlogic/cpu_id.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/usb.h>
+
+#ifndef CONFIG_USB_GADGET_CRG
+void dwc_write_reg32(unsigned int x, unsigned int v)
+{
+ unsigned int addr;
+
+ addr = usb_get_dwc_a_base_addr();
+ (*(volatile uint32_t *)(unsigned long)(x + addr))=v;
+}
+unsigned int dwc_read_reg32(unsigned int x)
+{
+ unsigned int addr;
+
+ addr = usb_get_dwc_a_base_addr();
+ return (*(volatile uint32_t*)((unsigned long)(x + addr)));
+}
+
+void dwc_modify_reg32(unsigned int x, unsigned int c, unsigned int s)
+{
+ unsigned int addr;
+
+ addr = usb_get_dwc_a_base_addr();
+ (*(volatile uint32_t *)(unsigned long)(x + addr)) =
+ ( ((dwc_read_reg32(x)) & (~c)) | (s));
+}
+
+void set_usb_phy21_tuning_update(void)
+{
+ unsigned long phy_reg_base = usb_get_device_mode_phy_base();
+
+ if (phy_reg_base == 0)
+ return;
+ usb2_phy_tuning(phy_reg_base, 1);
+ return;
+}
+
+void set_usb_phy21_tuning_update_reset(void)
+{
+ usb_phy_tuning_reset();
+}
+
+
+void set_usb_phy_config(int cfg)
+{
+ usb_device_mode_init();
+}
+
+//sleep sometime before and after disconnect,
+// to let usb_burning_tool.exe detect both fast plug-out and plug-in
+extern void dwc_otg_pullup(int is_on);
+void close_usb_phy_clock(int cfg)
+{
+ cfg = cfg;//avoid compiler warning
+
+ run_command("sleep 1", 0);//improve pc compatibility!!
+ dwc_otg_pullup(0);//disconnect
+ __udelay(20);
+ /*dwc_otg_power_off_phy();*///Don't call this as it may cause pull-down failed!!!!
+ run_command("sleep 1", 0);
+
+ return;
+}
+#endif
diff --git a/drivers/usb/gadget/platform.h b/drivers/usb/gadget/platform.h
new file mode 100644
index 0000000..099018c
--- /dev/null
+++ b/drivers/usb/gadget/platform.h
@@ -0,0 +1,86 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __PLATFORM_H__
+#define __PLATFORM_H__
+
+#include <asm/arch/register.h>
+
+#define PREI_USB_PHY_A_POR (1 << 0)
+#define PREI_USB_PHY_B_POR (1 << 1)
+#define PREI_USB_PHY_CLK_SEL (7 << 5)
+#define PREI_USB_PHY_CLK_GATE (1 << 8)
+#define PREI_USB_PHY_B_AHB_RSET (1 << 11)
+#define PREI_USB_PHY_B_CLK_RSET (1 << 12)
+#define PREI_USB_PHY_B_PLL_RSET (1 << 13)
+#define PREI_USB_PHY_A_AHB_RSET (1 << 17)
+#define PREI_USB_PHY_A_CLK_RSET (1 << 18)
+#define PREI_USB_PHY_A_PLL_RSET (1 << 19)
+#define PREI_USB_PHY_A_DRV_VBUS (1 << 20)
+#define PREI_USB_PHY_B_DRV_VBUS (1 << 21)
+#define PREI_USB_PHY_B_CLK_DETECT (1 << 22)
+#define PREI_USB_PHY_CLK_DIV (0x7f << 24)
+#define PREI_USB_PHY_A_CLK_DETECT (1 << 31)
+
+#define PREI_USB_PHY_A_REG3_IDDIG_OVR (1 << 23)
+#define PREI_USB_PHY_A_REG3_IDDIG_VAL (1 << 24)
+
+#define PREI_USB_PHY_B_REG4_IDDIG_OVR (1 << 23)
+#define PREI_USB_PHY_B_REG4_IDDIG_VAL (1 << 24)
+
+#define IREG_TIMER_E_COUNT 0x2655
+
+
+#define flush_cpu_cache()
+
+void dwc_write_reg32(unsigned int x, unsigned int v);
+unsigned int dwc_read_reg32(unsigned int x);
+void dwc_modify_reg32(unsigned int x, unsigned int c, unsigned int s);
+
+#define get_unaligned(ptr) ( ((unsigned long)ptr & 3) ? \
+ (((__u8 *)ptr)[0] | (((__u8 *)ptr)[1]<<8) | (((__u8 *)ptr)[2]<<16) | (((__u8 *)ptr)[3]<<24)) : \
+ (*(uint32_t*)ptr) )
+#define get_unaligned_16(ptr) (((__u8 *)ptr)[0] | (((__u8 *)ptr)[1]<<8))
+#define get_unaligned_32(ptr) (((__u8 *)ptr)[0] | (((__u8 *)ptr)[1]<<8) | (((__u8 *)ptr)[2]<<16) | (((__u8 *)ptr)[3]<<24))
+
+#define EXT_CLOCK 0
+#define INT_CLOCK 1
+
+#define USB_ROM_CONN_TIMEOUT 5*1000*1000
+
+
+/* Meet with spec */
+#define USB_ROM_VER_MAJOR 0
+#define USB_ROM_STAGE_MAJOR 0
+#define USB_ROM_STAGE_MINOR 16
+
+#ifdef CONFIG_M6
+#define USB_ROM_VER_MINOR 8
+#else
+#define USB_ROM_VER_MINOR 7
+#endif
+
+#define PRINTF(x...) do{}while(0)
+
+#define ERR(x...) printf(x)
+#define DBG(x...) PRINTF(x)
+
+#define USB_ERR(x...) printf("USBErr:%d", __LINE__),printf(x)
+#define USB_DBG(x...) PRINTF(x)
+
+void set_usb_phy_config(int cfg);
+void set_usb_phy21_tuning_update(void);
+void set_usb_phy21_tuning_update_reset(void);
+void close_usb_phy_clock(int cfg);
+
+void usb_parameter_init(int timeout);
+int chip_utimer_set(int val);
+int chip_watchdog(void);
+#define udelay __udelay
+#define wait_ms(a) udelay(a*1000);
+int update_utime(void);
+int get_utime(void);
+
+#endif
diff --git a/drivers/usb/gadget/v2_burning/Kconfig b/drivers/usb/gadget/v2_burning/Kconfig
index 231a9ec..12f793b 100644
--- a/drivers/usb/gadget/v2_burning/Kconfig
+++ b/drivers/usb/gadget/v2_burning/Kconfig
@@ -15,6 +15,7 @@
Say Y here if you want to support upgrade from sdcard and usb disk
config SD_BURNING_SUPPORT_UI
+ depends on CMD_BMP
bool "AML factory sdcard and usb disk with UI progress info"
---help---
Say Y here if you want to support sdcard and usb disk with UI progress info
@@ -36,4 +37,3 @@
#config USB_DEVICE_V2
# bool
endif # AML_V2_FACTORY_BURN
-
diff --git a/drivers/usb/gadget/v2_burning/Makefile b/drivers/usb/gadget/v2_burning/Makefile
index 475f8df..a93d781 100644
--- a/drivers/usb/gadget/v2_burning/Makefile
+++ b/drivers/usb/gadget/v2_burning/Makefile
@@ -23,16 +23,16 @@
EXTRA_CFLAGS = -I./v2_common -I./v2_usb_tool -I./v2_sdc_burn
obj-$(CONFIG_AML_V2_FACTORY_BURN) += aml_v2_burn.o
-
aml_v2_burn-y = aml_v2_burning.o
-aml_v2_burn-y += v2_usb_tool/optimus_core.o
-ccflags-$(CONFIG_USB_BURNING_TOOL) += -DAML_USB_BURN_TOOL
-ifdef CONFIG_USB_BURNING_TOOL
-aml_v2_burn-y += v2_usb_tool/optimus_core.o v2_usb_tool/optimus_transform.o
aml_v2_burn-y += v2_common/optimus_download.o v2_common/optimus_buffer_manager.o v2_common/optimus_simg2img.o
aml_v2_burn-y += v2_common/optimus_progress.o
-endif ##ifdef CONFIG_USB_BURNING_TOOL
aml_v2_burn-$(CONFIG_UNIFY_KEY_MANAGE) += v2_common/optimus_download_key.o
+
+ifdef CONFIG_USB_BURNING_TOOL
+aml_v2_burn-y += v2_usb_tool/optimus_core.o
+ccflags-$(CONFIG_USB_BURNING_TOOL) += -DAML_USB_BURN_TOOL
+aml_v2_burn-y += v2_usb_tool/optimus_core.o v2_usb_tool/optimus_transform.o
+endif ##ifdef CONFIG_USB_BURNING_TOOL
ifdef CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE
aml_v2_burn-y += v2_common/optimus_img_decoder.o v2_common/optimus_fat.o
aml_v2_burn-y += v2_sdc_burn/optimus_sdc_update.o v2_sdc_burn/optimus_sdc_burn.o v2_sdc_burn/optimus_ini_parser.o
diff --git a/drivers/usb/gadget/v2_burning/aml_sysrecovery/aml_sysrecovery.c b/drivers/usb/gadget/v2_burning/aml_sysrecovery/aml_sysrecovery.c
index c8a1c1b..a81ac30 100644
--- a/drivers/usb/gadget/v2_burning/aml_sysrecovery/aml_sysrecovery.c
+++ b/drivers/usb/gadget/v2_burning/aml_sysrecovery/aml_sysrecovery.c
@@ -1,19 +1,16 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file sysrecovery.c
- * \brief
- *
- * \version 1.0.0
- * \date Friday,14/11/21
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2014 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "../v2_burning_i.h"
#include "../v2_sdc_burn/optimus_sdc_burn_i.h"
#include "../v2_sdc_burn/optimus_led.h"
-#define CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA 1
+#ifndef CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA
+#define CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA "data"
+#endif// #ifndef CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA
+extern int sdc_burn_aml_keys(HIMAGE hImg, const int keyOverWrite, int licenseKey, int imgKey);
static int optimus_sysrec_check_whole_img_before_burn(const char* partName)
{
@@ -21,50 +18,27 @@
return 0;
}
-#if CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA
+#ifdef CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA
//clear data parts then the parts will formatted when firtsboot
//As fill half parttition need so much time, I just clear 2M
static int optimus_sysrec_clear_usr_data_parts(void)
{
- const char* const _usrDataParts[] = {"data",};
+ const char* const _usrDataParts[] = {CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA,};
const int dataPartsNum = sizeof(_usrDataParts)/sizeof(const char*);
- const unsigned BufSz = 1U<<20;//1MB
- unsigned char* clearBuf= (unsigned char*)OPTIMUS_DOWNLOAD_TRANSFER_BUF_ADDR;
int partIndex = 0;
int ret = 0;
+ char cmdbuf[128];
- memset(clearBuf, 0xff, BufSz);
for (partIndex = 0; partIndex < dataPartsNum; ++partIndex)
{
- u64 partCap = 0;
- const char* thePart = _usrDataParts[partIndex];
- int rcode = 0;
- u64 offset = 0;
- u64 ClearSz = 2U<<20;
-
- DWN_MSG("To clear data part[%s]\n", thePart);
- partCap = store_part_size(thePart);
- if (rcode) {
- DWN_ERR("Fail to get partSz for part[%s]\n", thePart);
- return rcode;
- }
- //FIXME: If there is fschk before firstboot, the 2MB to destroy the data if not enough
- /*ClearSz = partCap>>1;*/
- DWN_MSG("partCap 0x%llxMB, ClearSz=%llxMb\n", (partCap>>20), (ClearSz>>20));
-
- for (; offset < ClearSz; offset += BufSz)
- {
- rcode = store_write(thePart, offset, BufSz, clearBuf);
- if (rcode) {
- DWN_ERR("Failed when clear data part[%s], rcode=%d\n", thePart, rcode);
- ret += rcode;
- }
- }
+ sprintf(cmdbuf, "store erase partition %s", _usrDataParts[partIndex]);
+ ret = run_command(cmdbuf, 0);
+ if (ret) { DWN_WRN("Wrn:failed in cmd:%s\n", cmdbuf); }
}
return ret;
}
-#endif//#if CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA
+#endif//#ifdef CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA
/*
*.partName: aml_sysrecovery
@@ -78,8 +52,8 @@
__hdle hUiProgress = NULL;
HIMAGE hImg = NULL;
int ret = 0;
-
- ret = optimus_storage_init(0);//Init all partitions for burning
+ int hasBootloader = 0;
+ u64 datapartsSz = 0;
if (verifyPackageBeforeBurn)
{
@@ -102,6 +76,14 @@
}
show_logo_to_report_burning();
+ //update dtb for keyman
+ ret = optimus_sdc_burn_dtb_load(hImg);
+ if (ITEM_NOT_EXIST != ret && ret) {
+ DWN_ERR("Fail in load dtb for sdc_burn\n");
+ ret = __LINE__; goto _finish;
+ }
+ optimus_storage_init(0);
+
hUiProgress = optimus_progress_ui_request_for_sdc_burn();
if (!hUiProgress) {
DWN_ERR("request progress handle failed!\n");
@@ -109,8 +91,7 @@
}
optimus_progress_ui_direct_update_progress(hUiProgress, UPGRADE_STEPS_AFTER_DISK_INIT_OK);
- int hasBootloader = 0;
- u64 datapartsSz = optimus_img_decoder_get_data_parts_size(hImg, &hasBootloader);
+ datapartsSz = optimus_img_decoder_get_data_parts_size(hImg, &hasBootloader);
DWN_MSG("datapartsSz=[%8u]MB\n", (unsigned)(datapartsSz >> 20));
ret = optimus_progress_ui_set_smart_mode(hUiProgress, datapartsSz,
UPGRADE_STEPS_FOR_BURN_DATA_PARTS_IN_PKG(!pSdcCfgPara->burnEx.bitsMap.mediaPath));
@@ -126,24 +107,8 @@
ret = __LINE__; goto _finish;
}
-#if 0
- ret = optimus_sdc_burn_dtb_load(hImg);
- if (ITEM_NOT_EXIST != ret && ret) {
- DWN_ERR("Fail in load dtb for sdc_burn\n");
- ret = __LINE__; goto _finish;
- }
- ret = optimus_save_loaded_dtb_to_flash();
- if (ret) {
- DWN_ERR("FAiled in dtb wr\n");
- return __LINE__;
- }
-#endif
-
optimus_progress_ui_direct_update_progress(hUiProgress, UPGRADE_STPES_AFTER_BURN_DATA_PARTS_OK);
-#if CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA
- optimus_sysrec_clear_usr_data_parts();
-#endif// #if CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA
#if 1
if (hasBootloader)
{//burn bootloader
@@ -159,13 +124,24 @@
}
}
#endif
+#if CONFIG_SUPPORT_SDC_KEYBURN
+ ret = sdc_burn_aml_keys(hImg, 0, 0, 1);
+ if (ret) {
+ DWN_ERR("Fail in recovery keys from img\n");
+ ret = __LINE__; goto _finish;
+ }
+#endif// #if CONFIG_SUPPORT_SDC_KEYBURN
+#ifdef CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA
+ optimus_sysrec_clear_usr_data_parts();
+#endif// #ifdef CONFIG_AML_SYS_RECOVERY_CLEAR_USR_DATA
+
optimus_progress_ui_direct_update_progress(hUiProgress, UPGRADE_STEPS_AFTER_BURN_BOOTLOADER_OK);
_finish:
image_close(hImg);
- optimus_progress_ui_report_upgrade_stat(hUiProgress, !ret);
+ if (hUiProgress) optimus_progress_ui_report_upgrade_stat(hUiProgress, !ret);
optimus_report_burn_complete_sta(ret, 1/*pSdcCfgPara->custom.rebootAfterBurn*/);
- optimus_progress_ui_release(hUiProgress);
+ if (hUiProgress) optimus_progress_ui_release(hUiProgress);
//optimus_storage_exit();//temporary not exit storage driver when failed as may continue burning after burn
return ret;
}
@@ -189,6 +165,7 @@
optimus_led_show_in_process_of_burning();
optimus_work_mode_set(OPTIMUS_WORK_MODE_SYS_RECOVERY);
+ optimus_buf_manager_init(16*1024);
rcode = optimus_sysrec_burn_package_from_partition(AML_SYS_RECOVERY_PART, needVerify, verifyPackageBeforeBurn);
return rcode;
diff --git a/drivers/usb/gadget/v2_burning/aml_sysrecovery/cmd_detect_sys_recovery_key.c b/drivers/usb/gadget/v2_burning/aml_sysrecovery/cmd_detect_sys_recovery_key.c
index 0a33f97..2912bb9 100644
--- a/drivers/usb/gadget/v2_burning/aml_sysrecovery/cmd_detect_sys_recovery_key.c
+++ b/drivers/usb/gadget/v2_burning/aml_sysrecovery/cmd_detect_sys_recovery_key.c
@@ -1,14 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file cmd_detect_sys_recovery_key.c
- * \brief Detect whether user want to enter sys_recovery
- *
- * \version 1.0.0
- * \date 14/11/25
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2014 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include <config.h>
#include <common.h>
#include <asm/arch/io.h>
diff --git a/drivers/usb/gadget/v2_burning/aml_v2_burning.c b/drivers/usb/gadget/v2_burning/aml_v2_burning.c
index 8800b53..dc42fb6 100644
--- a/drivers/usb/gadget/v2_burning/aml_v2_burning.c
+++ b/drivers/usb/gadget/v2_burning/aml_v2_burning.c
@@ -1,19 +1,11 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file aml_v2_burning.c
- * \brief common interfaces for version 2 burning
- *
- * \version 1.0.0
- * \date 09/15/2013
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2013 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "v2_burning_i.h"
#include <mmc.h>
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/io.h>
-#include <asm/arch/bl31_apis.h>
+#include <amlogic/cpu_id.h>
#ifndef BOOT_DEVICE_USB
#define BOOT_DEVICE_SD 4
@@ -59,24 +51,37 @@
return 1;//is ready for sdcard producing
}
+#ifdef CONFIG_AML_V3_FACTORY_BURN
+extern unsigned _get_romcode_boot_id(void);
+#else
static unsigned _get_romcode_boot_id(void)
{
- DWN_DBG("P_AO_SEC_GP_CFG0=0x%p\n", P_AO_SEC_GP_CFG0);
- const unsigned boot_id = readl(P_AO_SEC_GP_CFG0) & 0xf;
-
- DWN_DBG("boot_id()=%x\n", boot_id);
- return boot_id;
+ unsigned boot_id = 0;
+#ifdef SYSCTRL_SEC_STATUS_REG2
+ cpu_id_t cpuid = get_cpu_id();
+ if (MESON_CPU_MAJOR_ID_SC2 <= cpuid.family_id) {
+ boot_id = readl(SYSCTRL_SEC_STATUS_REG2);
+ DWN_DBG("boot_id 0x%x\n", boot_id);
+ boot_id = (boot_id>>4) & 0xf;
+ } else
+#elif defined(P_AO_SEC_GP_CFG0)
+ {
+ DWN_DBG("cfg0 0x%08x\n", readl(P_AO_SEC_GP_CFG0));
+ boot_id = readl(P_AO_SEC_GP_CFG0) & 0xf;
+ }
+#else
+ DWN_MSG("both P_AO_SEC_GP_CFG0 and SYSCTRL_SEC_STATUS_REG2 undefined\n");
+#endif//#ifdef SYSCTRL_SEC_STATUS_REG2
+ DWN_MSG("boot_id 1x%x\n", boot_id);
+ return boot_id;
}
+#endif
//is the uboot loaded from usb otg
int is_tpl_loaded_from_usb(void)
{
const int boot_id = _get_romcode_boot_id();
- const unsigned forceUsbBoot = readl(P_AO_SEC_GP_CFG7) ;
- DWN_DBG("forceUsbBoot=%p, %x\n", P_AO_SEC_GP_CFG7, forceUsbBoot);
- int ret = (BOOT_DEVICE_USB == boot_id) || ( forceUsbBoot & (1U<<31) );
-
- return ret;
+ return (BOOT_DEVICE_USB == boot_id);
}
//is the uboot loaded from sdcard mmc 0
@@ -111,8 +116,16 @@
return 0;
}
+int aml_burn_sdc_producing(int flag, bd_t* bis)
+{
+ optimus_work_mode_set(OPTIMUS_WORK_MODE_SDC_PRODUCE);
+
+ return optimus_burn_package_in_sdmmc(getenv("sdcburncfg"));
+}
+
+#ifdef CONFIG_USB_BURNING_TOOL
//producing mode means boot from raw flash, i.e, uboot is loaded from usb
-int aml_burn_usb_producing(int flag, bd_t* bis)
+static int aml_burn_usb_producing(int flag, bd_t* bis)
{
flag = flag; bis = bis;//avoid compile warning
@@ -122,33 +135,10 @@
#endif//#if (defined AML_USB_BURN_TOOL)
close_usb_phy_clock(0);//disconect before re-connect to enhance pc compatibility
+ optimus_clear_ovd_register();//clear OVD register for normal reboot
return v2_usbburning(20000);
}
-int aml_burn_sdc_producing(int flag, bd_t* bis)
-{
- optimus_work_mode_set(OPTIMUS_WORK_MODE_SDC_PRODUCE);
-
- return optimus_burn_package_in_sdmmc(getenv("sdcburncfg"));
-}
-
-//burning flash from romboot stage
-int aml_burn_factory_producing(int flag, bd_t* bis)
-{
- if (is_tpl_loaded_from_usb())
- {
- return aml_burn_usb_producing(flag, bis);
- }
-
- if (is_tpl_loaded_from_ext_sdmmc())
- {
- return aml_burn_sdc_producing(flag, bis);
- }
-
- DWN_ERR("Shouldnot reach here!\n");
- return 0;
-}
-
extern void serial_initialize(void);
int aml_try_factory_usb_burning(int flag, bd_t* bis)
{
@@ -163,11 +153,35 @@
}
return aml_burn_usb_producing(flag, bis);
}
+#endif// #ifdef CONFIG_USB_BURNING_TOOL
+
+//burning flash from romboot stage
+int aml_burn_factory_producing(int flag, bd_t* bis)
+{
+#ifdef CONFIG_USB_BURNING_TOOL
+ if (is_tpl_loaded_from_usb())
+ {
+ return aml_burn_usb_producing(flag, bis);
+ }
+#endif// #ifdef CONFIG_USB_BURNING_TOOL
+
+ if (is_tpl_loaded_from_ext_sdmmc())
+ {
+ return aml_burn_sdc_producing(flag, bis);
+ }
+
+ DWN_ERR("Shouldnot reach here!\n");
+ return 0;
+}
+
int aml_try_factory_sdcard_burning(int flag, bd_t* bis)
{
if (!is_tpl_loaded_from_ext_sdmmc()) return 1;
-
+#ifdef CONFIG_SILENT_CONSOLE
+ /* enable console output */
+ gd->flags &= ~GD_FLG_SILENT;
+#endif
if ( aml_check_is_ready_for_sdc_produce() )
{
return aml_burn_sdc_producing(flag, bis);
diff --git a/drivers/usb/gadget/v2_burning/v2_burning_i.h b/drivers/usb/gadget/v2_burning/v2_burning_i.h
index 87b0b21..ec4ab28 100644
--- a/drivers/usb/gadget/v2_burning/v2_burning_i.h
+++ b/drivers/usb/gadget/v2_burning/v2_burning_i.h
@@ -1,13 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * \file v2_burning_i.h
- * \brief internal include interfaces
- *
- * \version 1.0.0
- * \date 2013/11/4
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2013 Amlogic Inc.. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __V2_BURNING_I_H__
@@ -22,6 +15,9 @@
#include <malloc.h>
#include <u-boot/sha1.h>
#include <console.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/io.h>
+#include <asm/arch/bl31_apis.h>
#include <amlogic/aml_v2_burning.h>
//#include <asm/arch/reboot.h>
@@ -32,6 +28,7 @@
#include "v2_common/optimus_download.h"
#include "v2_common/amlImage_if.h"
#include "v2_common/optimus_progress_ui.h"
+#include <amlogic/store_wrapper.h>
extern int cli_simple_parse_line(char *line, char *argv[]);
#ifndef getenv
diff --git a/drivers/usb/gadget/v2_burning/v2_common/amlImage_if.h b/drivers/usb/gadget/v2_burning/v2_common/amlImage_if.h
index 15373c1..a247448 100644
--- a/drivers/usb/gadget/v2_burning/v2_common/amlImage_if.h
+++ b/drivers/usb/gadget/v2_burning/v2_common/amlImage_if.h
@@ -1,13 +1,8 @@
-/* * \file amlImage_if.h
- * \brief Amlogic firmware image interface
- *
- * \version 1.0.0
- * \date 2013/5/21
- * \author Sam.Wu <yihui.wu@Amlogic.com>
- *
- * Copyright (c) 2013 Amlogic Inc. All Rights Reserved.
- *
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#ifndef __AMLIMAGE_IF_H__
#define __AMLIMAGE_IF_H__
@@ -120,5 +115,13 @@
u64 optimus_img_decoder_get_data_parts_size(HIMAGE hImg, int* hasBootloader);
+unsigned image_get_crc(HIMAGE hImg);
+
+int optimus_img_item2buf(HIMAGE hImg, const char* main, const char* sub, char* buf, int* bufsz);
+
+int get_subtype_nr(HIMAGE hImg, const char* main_type);
+
+int get_subtype_nm_by_index(HIMAGE hImg, const char* main_type, const char** sub_type, const int itemIndex);
+
#endif//ifndef __AMLIMAGE_IF_H__
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_buffer_manager.c b/drivers/usb/gadget/v2_burning/v2_common/optimus_buffer_manager.c
index 3aa4c6d..2378c36 100644
--- a/drivers/usb/gadget/v2_burning/v2_common/optimus_buffer_manager.c
+++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_buffer_manager.c
@@ -1,14 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file optimus_buffer_manager.c
- * \brief buffer manager for download data: A thin layer between receiving partition data and writing flash
- *
- * \version 1.0.0
- * \date 2013/5/2
- * \author Sam.Wu <yihui.wu@Amlogic.com>
- *
- * Copyright (c) 2013 Amlogic Inc.. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "../v2_burning_i.h"
#define OPTIMUS_SLOT_STA_FREE (0)//buffer slot not used yet
@@ -74,6 +68,10 @@
return OPT_DOWN_FAIL;
}
_bufManager.mediaAlignSz = mediaAlignSz;
+ *(u32*)(&_bufManager.transferUnitSz) = (OPTIMUS_WORK_MODE_USB_PRODUCE >= optimus_work_mode_get())
+ ? OPTIMUS_DOWNLOAD_SLOT_SZ : OPTIMUS_LOCAL_UPGRADE_SLOT_SZ;
+ _bufManager.writeBackUnitSz = _bufManager.transferUnitSz;
+
DWN_DBG("transfer=0x%p, transferBufSz=0x%x, transferUnitSz=0x%x, writeBackUnitSz=0x%x, totalSlotNum=%d\n", _bufManager.transferBuf,
_bufManager.transferBufSz, _bufManager.transferUnitSz, _bufManager.writeBackUnitSz, _bufManager.totalSlotNum);
@@ -122,6 +120,7 @@
_bufManager.destMediaType = !strcmp("mem", mediaType) ? OPTIMUS_MEDIA_TYPE_MEM : OPTIMUS_MEDIA_TYPE_STORE ;
if ( !cacheAll2Mem ) cacheAll2Mem = !strcmp("mem", mediaType) ;
+ if ( !cacheAll2Mem ) cacheAll2Mem = (pktSz4BufManager <= _bufManager.transferUnitSz);
if (cacheAll2Mem)
{
writeBackUnitSz = pktSz4BufManager + _bufManager.transferUnitSz - 1;
@@ -140,10 +139,10 @@
return OPT_DOWN_FAIL;
}
if (_bufManager.transferUnitSz > writeBackUnitSz) {
- DWN_ERR("write back size %d < align size %d\n", writeBackUnitSz, _bufManager.mediaAlignSz);
+ DWN_ERR("write back size %d < align size %d\n", writeBackUnitSz, _bufManager.transferUnitSz);
return OPT_DOWN_FAIL;
}
- DWN_DBG("writeBackUnitSz = 0x%x, pktSz4BufManager = %lld\n", writeBackUnitSz, pktSz4BufManager);
+ DWN_DBG("writeBackUnitSz = 0x%x, pktSz4BufManager = 0x%llx, itemSizeNotAligned 0x%x\n", writeBackUnitSz, pktSz4BufManager, itemSizeNotAligned);
_bufManager.writeBackUnitSz = writeBackUnitSz;
_bufManager.totalSlotNum = 0;
@@ -188,7 +187,7 @@
(u8*)(u64)_bufManager.partBaseOffset ;
if (wantSz < _bufManager.transferUnitSz && !isLastTransfer) {
- DWN_ERR("only last transfer can less 64K, this index %d at size 0x%u illegle\n", totalSlotNum + 1, wantSz);
+ DWN_ERR("only last transfer can less 64K, this index %d at size 0x%x illegle\n", totalSlotNum + 1, wantSz);
return OPT_DOWN_FAIL;
}
@@ -228,7 +227,7 @@
const u8* BufBase = (OPTIMUS_MEDIA_TYPE_MEM != _bufManager.destMediaType) ? _bufManager.transferBuf :
(u8*)(u64)_bufManager.partBaseOffset ;
- DWN_DBG("transferSz=0x%x\n", transferSz);
+ DWN_DBG("[%d]transferSz=0x%x\n", _bufManager.totalSlotNum, transferSz);
//state fileds to update
_bufManager.totalSlotNum += 1;
if (_bufManager.totalSlotNum == _bufManager.nextWriteBackSlot)
@@ -317,7 +316,7 @@
DWN_DBG("thisTransDataLen 0x%x, left 0x%x, total 0x%x\n", thisTransDataLen, (u32)leftPktSz, (u32)totalTransferSz);
DWN_DBG("totalSlotNum %d, totalTransferSz 0x%x\n", totalSlotNum, (u32)totalTransferSz);
- memset(cmdDataBuf, bufLen, 0);
+ memset(cmdDataBuf, 0, bufLen);
*(unsigned*)(cmdDataBuf + 0) = 0xefe8;
*(unsigned*)(cmdDataBuf + 4) = thisTransDataLen;//Fill transfer data length of this bulk transfer
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_download.c b/drivers/usb/gadget/v2_burning/v2_common/optimus_download.c
index 7b974fb..d6859e9 100644
--- a/drivers/usb/gadget/v2_burning/v2_common/optimus_download.c
+++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_download.c
@@ -1,14 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file optimu_download.c
- * \brief
- *
- * \version 1.0.0
- * \date 2013/4/25
- * \author Sam.Wu <yihui.wu@amlogic.com>
- *
- * Copyright (c) 2013 Amlogic Inc. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "../v2_burning_i.h"
#include <linux/libfdt.h>
#include <partition_table.h>
@@ -16,13 +10,7 @@
#include <asm/arch/bl31_apis.h>
#include <asm/io.h>
#include <asm/arch/mailbox.h>
-
-#define ROM_BOOT_SKIP_BOOT_ENABLED_4_USB 1//skip boot to usb supported by romboot
-#ifdef SCPI_CMD_SDCARD_BOOT
-#define ROM_BOOT_SKIP_BOOT_ENABLED_4_SDC 1//skip boot sdcard supported by romboot
-#else
-#define ROM_BOOT_SKIP_BOOT_ENABLED_4_SDC 0
-#endif//#ifdef SCPI_CMD_SDCARD_BOOT
+#include <asm/arch/cpu_config.h>
extern unsigned int get_multi_dt_entry(unsigned long fdt_addr);
int is_optimus_storage_inited(void);
@@ -47,6 +35,142 @@
return OPT_DOWN_FAIL;
}
#endif//#ifndef CONFIG_UNIFY_KEY_MANAGE
+#ifndef CONFIG_USB_BURNING_TOOL
+#define platform_busy_increase_un_reported_size(sz)
+#endif// #ifndef CONFIG_USB_BURNING_TOOL
+
+#if 1//storage wrapper
+#define FBS_ERR(a, fmt...) DWN_ERR(fmt)
+#define FBS_EXIT(a, fmt...) do {DWN_ERR(fmt); return -__LINE__;} while(0)
+#define FB_ERR DWN_ERR
+#define FB_MSG DWN_MSG
+static int is_bootloader_discrte(bool* discreteMode)
+{
+ struct storage_info_t storeInfo;
+ if (store_get_device_info(&storeInfo)) {
+ FB_ERR("Fail get store dev info\n");
+ return __LINE__;
+ }
+ *discreteMode = (DISCRETE_BOOTLOADER == storeInfo.mode);
+ return 0;
+}
+
+static int bootloader_copy_sz(void)
+{
+ bool discreteMode = false;
+ if (is_bootloader_discrte(&discreteMode)) {
+ return 0;
+ }
+ if (discreteMode) {
+ return BL2_SIZE/*store_boot_copy_size("bl2")*/ + store_boot_copy_size("tpl");
+ } else {
+ return store_boot_copy_size("bootloader");
+ }
+
+ return 0;
+}
+
+static int _bootloader_write(u8* dataBuf, unsigned off, unsigned binSz, const char* bootName)
+{
+ int iCopy = 0;
+ const int bootCpyNum = store_boot_copy_num(bootName);
+ const int bootCpySz = (int)store_boot_copy_size(bootName);
+ FB_MSG("[%s] CpyNum %d, bootCpySz 0x%x\n", bootName, bootCpyNum, bootCpySz);
+ if (binSz + off > bootCpySz) FBS_EXIT(_ACK, "bootloader sz(0x%x) + off(0x%x) > bootCpySz 0x%x\n", binSz, off, bootCpySz);
+
+ if (off) {
+ FBS_ERR(_ACK, "current only 0 suuported!\n");
+ return -__LINE__;
+ }
+
+ for (; iCopy < bootCpyNum; ++iCopy) {
+ int ret = store_boot_write(bootName, iCopy, binSz, dataBuf);
+ if (ret) FBS_EXIT(_ACK, "FAil in program[%s] at copy[%d]\n", bootName, iCopy);
+ }
+
+ return 0;
+}
+
+static int _discrete_bootloader_write(u8* dataBuf, unsigned off, unsigned binSz)
+{
+ int bl2CopySz = BL2_SIZE/*(int)store_boot_copy_size("bl2")*/;
+ FB_MSG("bl2CopySz 0x%x, binSz 0x%x\n", bl2CopySz, binSz);
+
+ int ret = _bootloader_write(dataBuf, 0, bl2CopySz, "bl2");
+ if (ret) FBS_EXIT(_ACK, "Fail in program bl2\n");
+ if (binSz <= bl2CopySz) return 0;
+
+ ret = _bootloader_write(dataBuf + bl2CopySz, 0, binSz - bl2CopySz, "tpl");
+ if (ret) FBS_EXIT(_ACK, "Fail in burn tpl\n");
+ return 0;
+}
+
+static int bootloader_write(u8* dataBuf, unsigned off, unsigned binSz)
+{
+ bool discreteMode = false;
+ if (is_bootloader_discrte(&discreteMode)) {
+ return -__LINE__;
+ }
+ if (!discreteMode) {
+ return _bootloader_write(dataBuf, off, binSz, "bootloader");
+ } else {
+ return _discrete_bootloader_write(dataBuf, off, binSz);
+ }
+ return -__LINE__;
+}
+
+static int _bootloader_read(u8* pBuf, unsigned off, unsigned binSz, const char* bootName)
+{
+ int iCopy = 0;
+ const int bootCpyNum = store_boot_copy_num(bootName);
+ const int bootCpySz = (int)store_boot_copy_size(bootName);
+
+ if (binSz + off > bootCpySz) {
+ FBS_ERR(_ACK, "bootloader sz(0x%x) + off(0x%x) > bootCpySz 0x%x\n", binSz, off, bootCpySz);
+ return -__LINE__;
+ }
+ if (off) FBS_EXIT(_ACK, "current only 0 suuported!\n");
+
+ for (iCopy = 0; iCopy < bootCpyNum; ++iCopy) {
+ void* dataBuf = iCopy ? pBuf + binSz : pBuf;
+ int ret = store_boot_read(bootName, iCopy, binSz, dataBuf);
+ if (ret) FBS_EXIT("Fail to read boot[%s] at copy[%d]\n", bootName, iCopy);
+ if (iCopy) {
+ if (memcmp(pBuf, dataBuf, binSz))
+ FBS_EXIT(_ACK, "[%s] copy[%d] content NOT the same as copy[0]\n", bootName, iCopy);
+ }
+ }
+
+ return 0;
+}
+
+static int _discrete_bootloader_read(u8* dataBuf, unsigned off, unsigned binSz)
+{
+ int bl2CopySz = BL2_SIZE/*(int)store_boot_copy_size("bl2")*/;
+ FB_MSG("bl2CopySz 0x%x, binSz 0x%x\n", bl2CopySz, binSz);
+
+ int ret = _bootloader_read(dataBuf, 0, bl2CopySz, "bl2");
+ if (ret) FBS_EXIT(_ACK, "Fail in program bl2\n");
+ if (binSz <= bl2CopySz) return 0;
+
+ ret = _bootloader_read(dataBuf + bl2CopySz, 0, binSz - bl2CopySz, "tpl");
+ if (ret) FBS_EXIT(_ACK, "Fail in burn tpl\n");
+ return 0;
+}
+
+static int bootloader_read(u8* pBuf, unsigned off, unsigned binSz)
+{
+ bool discreteMode = false;
+ if (is_bootloader_discrte(&discreteMode)) {
+ return -__LINE__;
+ }
+
+ if (discreteMode)
+ return _discrete_bootloader_read(pBuf, off, binSz);
+
+ return _bootloader_read(pBuf, off, binSz, "bootloader");
+}
+#endif// #if 1//storage wrapper
static unsigned long _dtb_is_loaded = 0;
@@ -121,8 +245,9 @@
int partIndex = 0;
struct partitions * thePart = NULL;
- if (NULL == part_table)
- return 0;
+ if (NULL == part_table) return 0;
+ if (!strcmp("1", thePartName)) return 0;
+
for (thePart = part_table; partIndex < 36; ++thePart, ++partIndex)
{
if (memcmp(thePartName, thePart->name, strnlen(thePartName, MAX_PART_NAME_LEN))) continue;
@@ -151,7 +276,7 @@
{
int ret = 0;
DWN_MSG("%s:dataSzReceived=0x%x\n", __func__, dataSzReceived);
- store_erase("dtb", 0, store_rsv_size("dtb"), 0);
+ store_rsv_erase("dtb");
ret = store_rsv_write("dtb", dataSzReceived, (u8*)data);
return ret ? 0 : dataSzReceived;
@@ -175,93 +300,43 @@
return ret;
}
-//32k, Now nand not need align any more, but I remember spi nor flash need 32k aligh
-#define BOOTLOADER_ALIGN_BITS 0//15
-
//return value is the actual size it write
static int optimus_download_bootloader_image(struct ImgBurnInfo* pDownInfo, u32 dataSzReceived, const u8* data)
{
int ret = OPT_DOWN_OK;
int size = dataSzReceived;
- int iCopy = 0;
if (dataSzReceived < pDownInfo->imgPktSz) {
DWN_ERR("please write back bootloader after all data rx end.0x(%x, %x)\n", dataSzReceived, (u32)pDownInfo->imgPktSz);
return 0;
}
- if (size > (2U<<20)) {
+ if (size > bootloader_copy_sz()) {
DWN_ERR("uboot.bin size 0x%x > 2M unsupported\n", size);
return 0;
}
- const char* bootName = "bootloader";
- const int bootCpyNum = store_boot_copy_num(bootName);
- const int bootCpySz = (int)store_boot_copy_size(bootName);
- DWN_MSG("bootCpyNum %d, bootCpySz 0x%x\n", bootCpyNum, bootCpySz);
- if (size > bootCpySz) {
- DWN_MSG("bootloader img sz 0x%x > bootCpySz 0x%x\n", size, bootCpySz);
+ ret = bootloader_write((u8*)data, 0, size);
+ if (ret) {
+ DWN_ERR("FAil in program bootloader\n");
return 0;
}
-#if BOOTLOADER_ALIGN_BITS
- size += (1U<<BOOTLOADER_ALIGN_BITS) -1;
- size >>= BOOTLOADER_ALIGN_BITS;
- size <<= BOOTLOADER_ALIGN_BITS;
- if (dataSzReceived != size)DWN_MSG("align bootloader sz from 0x%x to 0x%lx\n", dataSzReceived, size) ;
-#endif// #if BOOTLOADER_ALIGN_BITS
- for (; iCopy < bootCpyNum; ++iCopy) {
- ret = store_boot_write(bootName, iCopy, size, (u8*)data);
- if (ret) {
- DWN_ERR("FAil in program[%s] at copy[%d]\n", bootName, iCopy);
- return 0;
- }
- }
return ret ? 0 : dataSzReceived;
}
-extern unsigned device_boot_flag;
static int optimus_verify_bootloader(struct ImgBurnInfo* pDownInfo, u8* genSum)
{
int ret = OPT_DOWN_OK;
unsigned char* pBuf = (unsigned char*)OPTIMUS_DOWNLOAD_TRANSFER_BUF_ADDR;
int size = 0;
- int iCopy = 0;
int bootRealSz = pDownInfo->imgPktSz;
-#if defined(CONFIG_AML_MTD) && defined(CONFIG_DISCRETE_BOOTLOADER)
- uint64_t off = 0;
- if ( NAND_BOOT_FLAG == device_boot_flag )
- off = (1ULL << 62) - 1; //verify mode for verify discrete bootloader
-#endif//#if defined(CONFIG_AML_MTD)
-
size=bootRealSz;
- const char* bootName = "bootloader";
- const int bootCpyNum = store_boot_copy_num(bootName);
- const int bootCpySz = (int)store_boot_copy_size(bootName);
- DWN_MSG("bootCpyNum %d, bootCpySz 0x%x\n", bootCpyNum, bootCpySz);
- if (size > bootCpySz) {
- DWN_MSG("bootloader img sz 0x%x > bootCpySz 0x%x\n", size, bootCpySz);
- return 0;
- }
-#if BOOTLOADER_ALIGN_BITS
- size += (1U<<BOOTLOADER_ALIGN_BITS) -1;
- size >>= BOOTLOADER_ALIGN_BITS;
- size <<= BOOTLOADER_ALIGN_BITS;
-#endif// #if BOOTLOADER_ALIGN_BITS
- for (iCopy = 0; iCopy < bootCpyNum; ++iCopy) {
- void* dataBuf = iCopy ? pBuf + size : pBuf;
- ret = store_boot_read(bootName, iCopy, size, dataBuf);
- if (ret) {
- DWN_ERR("Fail to read boot[%s] at copy[%d]\n", bootName, iCopy);
- return __LINE__;
- }
- if (iCopy) {
- if (memcmp(pBuf, dataBuf, bootRealSz)) {
- DWN_ERR("copy[%d] content not the same as copy[0]\n", iCopy);
- return __LINE__;
- }
- }
+ ret = bootloader_read(pBuf, 0, size);
+ if (ret) {
+ DWN_ERR("Fail to read bootloader\n");
+ return __LINE__;
}
sha1_csum(pBuf, bootRealSz, genSum);
@@ -280,7 +355,7 @@
}
DWN_DBG("1addrOffset=0x%llx, dataSz=0x%x, data = 0x%p\t", (((u64)destAddrInSec)<<9), dataSzInBy, (void*)data);
- ret = store_write(partName, (((u64)destAddrInSec)<<9), dataSzInBy, (void*)data);
+ ret = store_logic_write(partName, (((u64)destAddrInSec)<<9), dataSzInBy, (void*)data);
if (ret) {
DWN_ERR("Fail to write to media, ret = %d\n", ret);
return 0;
@@ -317,7 +392,7 @@
DWN_DBG("addrOffset=0x%llx, dataSz=0x%x, data = 0x%p\n", addrOrOffsetInBy, dataSz, data);
- ret = store_write(pDownInfo->partName, addrOrOffsetInBy, dataSz, (void*)data);
+ ret = store_logic_write(pDownInfo->partName, addrOrOffsetInBy, dataSz, (void*)data);
if (ret) {
DWN_ERR("Fail to write to media\n");
return 0;
@@ -340,38 +415,6 @@
{
DWN_MSG("Burn Start...\n");
pDownInfo->imgBurnSta = OPTIMUS_IMG_STA_BURN_ING;
-#if defined(CONFIG_AML_MTD)
- //Need erasing if 'Have not erasing the WHOLE chip' and 'NOT bootloader'
- if ( (NAND_BOOT_FLAG == device_boot_flag || SPI_NAND_FLAG == device_boot_flag) && MediaType < OPTIMUS_MEDIA_TYPE_MEM )
- #if defined(CONFIG_DISCRETE_BOOTLOADER)
- if ( strcmp(CONFIG_TPL_PART_NAME, partName) )
- #endif//#if defined(CONFIG_DISCRETE_BOOTLOADER)
- if (!pDownInfo->isDumpMode && !(is_optimus_storage_inited()>>16) && strcmp("bootloader", partName)) {
- char cmd[96];
- sprintf(cmd, "store erase partition %s", partName);
- DWN_MSG("cmd[%s]\n", cmd);
- run_command(cmd, 0);
- }
- #if defined(OPTIMUS_BURN_TARGET_SUPPORT_UBIFS)
- if (IMG_TYPE_UBIFS == pDownInfo->imgType) //get size if not bootloader
- {
- char cmd[64];
- static int _ubiDeviceIndex = 0;
- sprintf(cmd, "ubi part %s", partName);
- ret = run_command(cmd, 0);
- if (ret) {
- DWN_ERR("Fail in run cmd[%s]\n", cmd); return __LINE__;
- }
- sprintf(cmd, "ubi device %d", _ubiDeviceIndex++);
- ret = run_command(cmd, 0);
- sprintf(cmd, "ubi create %s", partName);
- ret = run_command(cmd, 0);
- if (ret) {
- DWN_ERR("Fail in run cmd[%s]\n", cmd); return __LINE__;
- }
- }
- #endif// #if defined(OPTIMUS_BURN_TARGET_SUPPORT_UBIFS)
-#endif//#if defined(CONFIG_AML_MTD)
}
else if(pDownInfo->imgSzDisposed == pDownInfo->imgPktSz && OPTIMUS_IMG_STA_BURN_COMPLETE == pDownInfo->imgBurnSta)
{
@@ -551,14 +594,14 @@
{
if (IMG_TYPE_BOOTLOADER == pDownInfo->imgType)
{
- ret = store_boot_read("bootloader", 0, readSzInBy, (char*)buff);
+ ret = bootloader_read(buff, 0, readSzInBy);
}
else if (IMG_TYPE_DTB == pDownInfo->imgType) {
ret = store_rsv_read("dtb", readSzInBy, buff);
}
else
{
- ret = store_read(partName, addrOrOffsetInBy, readSzInBy, buff);
+ ret = store_logic_read(partName, addrOrOffsetInBy, readSzInBy, buff);
platform_busy_increase_un_reported_size(readSzInBy);
}
if (ret) {
@@ -800,7 +843,7 @@
}
else{
#ifdef CONFIG_AML_MTD
- if ( NAND_BOOT_FLAG == device_boot_flag ) {
+ if ( BOOT_NAND_MTD == store_get_type() ) {
extern int check_valid_dts(unsigned char *buffer);
ret = check_valid_dts(dtbLoadedAddr);
} else
@@ -813,10 +856,17 @@
}
}
+ ret = store_init(1);
+ if (ret <= 0) {
+ DWN_MSG("Fail in init storage,ret %d\n", ret);
+ return -__LINE__;
+ }
+
switch (toErase)
{
case 0://NO erase
- ret = store_init(1);
+ case 1:
+ case 2:
break;
case 3://erase all(with key)
@@ -828,10 +878,7 @@
DWN_ERR("Fail when run cmd[%s], ret %d\n", cmd, ret);
break;
}
- }
- case 1://normal erase, store init 3
- ret = store_init(3);
- break;
+ } break;
case 4://force erase all
{
@@ -842,53 +889,45 @@
DWN_ERR("Fail when run cmd[%s], ret %d\n", cmd, ret);
break;
}
- }
- case 2:
- ret = store_init(4);
- break;
+ } break;
default:
DWN_ERR("Unsupported erase flag %d\n", toErase); ret = -__LINE__;
break;
}
- if (!ret)
- {
- _disk_intialed_ok = 1;
- _disk_intialed_ok += toErase <<16;
-
-#if 0
- ret = optimus_save_loaded_dtb_to_flash();
+ if (toErase > 0) {
+ ret = store_erase(NULL, 0, 0, 0);
if (ret) {
- DWN_ERR("FAiled in dtb wr\n");
- return __LINE__;
- }
-#endif
-
- if (OPTIMUS_WORK_MODE_USB_PRODUCE == optimus_work_mode_get()) //env not relocated in this case
- {
- DWN_MSG("usb producing env_relocate\n");
- env_relocate();
- }
-
- if (_dtb_is_loaded)//for key init, or fail when get /unifykey
- {
- unsigned long fdtAddr = (unsigned long)dtbLoadedAddr;
-#ifdef CONFIG_MULTI_DTB
- fdtAddr = get_multi_dt_entry(fdtAddr);
-#endif// #ifdef CONFIG_MULTI_DTB
- ret = fdt_check_header((char*)fdtAddr);
- unsigned fdtsz = fdt_totalsize((char*)fdtAddr);
- if (ret || !fdtsz ) {
- DWN_ERR("Fail in fdt check header\n");
- return __LINE__;
- }
- // if (fdtsz < _dtb_is_loaded)
- memmove((char*)dtbLoadedAddr, (char*)fdtAddr, fdtsz);
+ DWN_ERR("Fail in erase flash,ret %d\n", ret);
+ return -__LINE__;
}
}
- return ret;
+ _disk_intialed_ok += toErase <<16;
+ if (OPTIMUS_WORK_MODE_USB_PRODUCE == optimus_work_mode_get()) //env not relocated in this case
+ {
+ DWN_MSG("usb producing env_relocate\n");
+ env_relocate();
+ }
+
+ if (_dtb_is_loaded)//for key init, or fail when get /unifykey
+ {
+ unsigned long fdtAddr = (unsigned long)dtbLoadedAddr;
+#ifdef CONFIG_MULTI_DTB
+ fdtAddr = get_multi_dt_entry(fdtAddr);
+#endif// #ifdef CONFIG_MULTI_DTB
+ ret = fdt_check_header((char*)fdtAddr);
+ unsigned fdtsz = fdt_totalsize((char*)fdtAddr);
+ if (ret || !fdtsz ) {
+ DWN_ERR("Fail in fdt check header\n");
+ return __LINE__;
+ }
+ // if (fdtsz < _dtb_is_loaded)
+ memmove((char*)dtbLoadedAddr, (char*)fdtAddr, fdtsz);
+ }
+
+ return 0;
}
int is_optimus_on_burn(void)//is now transfering image
@@ -1239,7 +1278,7 @@
if (IsTplLoadedFromBurningPackage)
{
/*rc = run_command("defenv", 0);//use new env directly if uboot is new !!!*/
- set_default_env("## save_setting ##\n");//use new env directly if uboot is new !!!
+ set_default_env("## save_setting ##\n", 0);//use new env directly if uboot is new !!!
#if 0
const char* def_env_initargs = getenv("initargs");
const char* def_env_bootargs = getenv("bootargs");
@@ -1385,52 +1424,3 @@
return rc;
}
-static int optimus_enable_romboot_skip_boot(const char* extBootDev)
-{
- if (!strcmp("usb", extBootDev))
- {
-#if ROM_BOOT_SKIP_BOOT_ENABLED_4_USB
-#if SCPI_CMD_USB_UNBOOT
- set_boot_first_timeout(SCPI_CMD_USB_UNBOOT);
-#else
- set_usb_boot_function(FORCE_USB_BOOT);
-#endif// #if SCPI_CMD_USB_UNBOOT
-#endif// #if ROM_BOOT_SKIP_BOOT_ENABLED_4_USB
- }
-
- if (!strcmp("sdc", extBootDev))
- {
-#if ROM_BOOT_SKIP_BOOT_ENABLED_4_SDC
- set_boot_first_timeout(SCPI_CMD_SDCARD_BOOT);
-#endif// #if ROM_BOOT_SKIP_BOOT_ENABLED_4_SDC
- }
-
- return 0;
-}
-
-//I assume that store_inited yet when "bootloader_is_old"!!!!
-int optimus_erase_bootloader(const char* extBootDev)
-{
- if (!strcmp("usb", extBootDev))
- {
-#if ROM_BOOT_SKIP_BOOT_ENABLED_4_USB
- return optimus_enable_romboot_skip_boot("usb");
-#endif// #if ROM_BOOT_SKIP_BOOT_ENABLED_4_USB
- }
-
- if (!strcmp("sdc", extBootDev))
- {
-#if ROM_BOOT_SKIP_BOOT_ENABLED_4_SDC
- return optimus_enable_romboot_skip_boot("sdc");
-#endif// #if ROM_BOOT_SKIP_BOOT_ENABLED_4_SDC
- }
-
- const char* bootName = "bootloader";
- const int bootCpyNum = store_boot_copy_num(bootName);
- int iCopy = 0;
- for (; iCopy < bootCpyNum; ++iCopy) {
- store_boot_erase(bootName, iCopy);
- }
- return 0;
-}
-
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_download.h b/drivers/usb/gadget/v2_burning/v2_common/optimus_download.h
index 6303e89..9929b12 100644
--- a/drivers/usb/gadget/v2_burning/v2_common/optimus_download.h
+++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_download.h
@@ -1,13 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * \file optimus_download.h
- * \brief common included files for optimus_*.c
- *
- * \version 1.0.0
- * \date 2013/5/3
- * \author Sam.Wu <yihui.wu@Amlogic.com>
- *
- * Copyright (c) 2013 Amlogic Inc.. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __OPTIMUS_DOWNLOAD_H__
@@ -83,6 +76,7 @@
#define OPTIMUS_DOWNLOAD_TRANSFER_BUF_ADDR (OPTIMUS_SPARSE_IMG_LEFT_DATA_ADDR_LOW + OPTIMUS_SPARSE_IMG_LEFT_DATA_MAX_SZ)
#define OPTIMUS_DOWNLOAD_SLOT_SZ (64<<10) //64K
+#define OPTIMUS_LOCAL_UPGRADE_SLOT_SZ (OPTIMUS_DOWNLOAD_SLOT_SZ * 16) //1M per time for fatload
#define OPTIMUS_DOWNLOAD_SLOT_SZ_SHIFT_BITS (16) //64K
#define OPTIMUS_DOWNLOAD_SLOT_NUM (OPTIMUS_DOWNLOAD_TRANSFER_BUF_TOTALSZ/OPTIMUS_DOWNLOAD_SLOT_SZ)
@@ -162,6 +156,8 @@
//common internal function
int optimus_erase_bootloader(const char* extBootDev);
+void optimus_clear_ovd_register(void);
+
void optimus_reset(const int cfgFlag);
int optimus_storage_init(int toErase);//init dest burning staorge
int optimus_storage_exit(void);
@@ -178,6 +174,8 @@
#define OPTIMUS_WORK_MODE_SDC_UPDATE (0xefe7)
#define OPTIMUS_WORK_MODE_SDC_PRODUCE (0xefe8)
#define OPTIMUS_WORK_MODE_SYS_RECOVERY (0xefe9)
+#define OPTIMUS_WORK_MODE_UDISK_UPDATE (0xefea)
+#define OPTIMUS_WORK_MODE_UDISK_PRODUCE (0xefeb)
int optimus_work_mode_get(void);
int optimus_work_mode_set(int workmode);
@@ -191,7 +189,9 @@
//ENV for auto jump into producing
#define _ENV_TIME_OUT_TO_AUTO_BURN "identifyWaitTime"
+#ifndef AML_SYS_RECOVERY_PART
#define AML_SYS_RECOVERY_PART "aml_sysrecovery"
+#endif// #ifndef AML_SYS_RECOVERY_PART
#if defined(CONFIG_AML_MTD) && (defined(UBIFS_IMG) || defined(CONFIG_CMD_UBIFS))
#define OPTIMUS_BURN_TARGET_SUPPORT_UBIFS 1
@@ -199,5 +199,10 @@
#define OPTIMUS_BURN_TARGET_SUPPORT_UBIFS 0
#endif// #if defined(CONFIG_AML_MTD) && (defined(UBIFS_IMG) || defined(CONFIG_CMD_UBIFS))
+#ifndef P_AO_SEC_SD_CFG0
+#define P_AO_SEC_GP_CFG0 SYSCTRL_SEC_STATUS_REG4
+#define P_PREG_STICKY_REG2 SYSCTRL_SEC_STICKY_REG2
+#endif// #ifndef P_AO_SEC_SD_CFG0
+
#endif//ifndef __OPTIMUS_DOWNLOAD_H__
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_download_key.c b/drivers/usb/gadget/v2_burning/v2_common/optimus_download_key.c
index 12179e0..c775d55 100644
--- a/drivers/usb/gadget/v2_burning/v2_common/optimus_download_key.c
+++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_download_key.c
@@ -1,20 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * =====================================================================================
- *
- * Filename: v2_download_key.c
- *
- * Version: 1.0
- * Created: 2013/9/4 14:10:07
- * Compiler: gcc
- *
- * Author: Sam Wu (yihui.wu@amlogic.com)
- * Organization: Amlogic Inc.
- *
- * Revision: none
- * Description: Funcitions and command to burn keys with key_unify driver
- *
- * =====================================================================================
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "../v2_burning_i.h"
#include <amlogic/keyunify.h>
@@ -77,14 +65,40 @@
#endif//#ifndef __HDCP22_HEY_H__
#define _AML_HDCP22_RX_KEY_NAME "aml_hdcp_key2.2"
-static struct {
+#define _AML_HDCP22_RP_KEY_NAME "aml_hdcp_key2.2rp"
+#define _AML_HDCP22_RX_TA_KEY_N "aml_hdcp_key2.2.ta"
+#define _HDCP22RxTypes 3//sizeof(_hdcprx22Keys)/sizeof(_hdcprx22Keys[0])
+#define _HDCP22_MAX_KEY_NUM 4
+
+static const char* _hdcprx22Keys[_HDCP22RxTypes] = {
+ _AML_HDCP22_RX_KEY_NAME,
+ _AML_HDCP22_RP_KEY_NAME,
+ _AML_HDCP22_RX_TA_KEY_N,
+};
+static struct AmlHdcp22RxKey{
const char* keyName;
+ const char* itemName;
int isEncrypt;
}
-_amlHdcp22RxKeys[] = {
- [0] = {.keyName = "hdcp22_rx_private", .isEncrypt = 1},
- [1] = {.keyName = "hdcp22_rx_fw", .isEncrypt = 0},
- [2] = {.keyName = "hdcp2_rx", .isEncrypt = 0},
+_amlHdcp22RxKeys[_HDCP22RxTypes][_HDCP22_MAX_KEY_NUM] = {
+ {//_AML_HDCP22_RX_KEY_NAME
+ [0] = {.keyName = "hdcp22_rx_private", .itemName = "hdcp22_rx_private", .isEncrypt = 1},
+ [1] = {.keyName = "hdcp22_rx_fw", .itemName = "extractedKey", .isEncrypt = 0},
+ [2] = {.keyName = "hdcp2_rx", .itemName = "hdcp2_rx", .isEncrypt = 0},
+ [3] = {.keyName = "hdcp22_rprx_fw", .itemName = "extractedKey_rxrp", .isEncrypt = 0},
+ },
+ {//_AML_HDCP22_RP_KEY_NAME
+ [0] = {.keyName = "hdcp22_rp_private", .itemName = "hdcp22_rx_private", .isEncrypt = 1},
+ [1] = {.keyName = "hdcp22_rprx_fw", .itemName = "extractedKey", .isEncrypt = 0},
+ [2] = {.keyName = "hdcp2_rx", .itemName = "hdcp2_rx", .isEncrypt = 0},
+ [3] = {.keyName = "hdcp22_rprp_fw", .itemName = "extractedKey_rxrp", .isEncrypt = 0},
+ },
+ {//_AML_HDCP22_RX_TA_KEY_N
+ [0] = {.keyName = "KEY_PROVISION_HDCP_RX22_FW_PRIVATE", .itemName = "hdcp22_rx_private", .isEncrypt = 0},
+ [1] = {.keyName = "KEY_PROVISION_HDCP_RX22_FW", .itemName = "extractedKey", .isEncrypt = 0},
+ [2] = {.keyName = "KEY_PROVISION_HDCP_RX22", .itemName = "hdcp2_rx", .isEncrypt = 0},
+ [3] = {.keyName = "KEY_PROVISION_HDCP_RP22_FW", .itemName = "extractedKey_rxrp", .isEncrypt = 0},
+ },
};
static char generalDataChange(const char input)
@@ -123,11 +137,18 @@
int ret = 0;
unsigned writtenLen = 0;
+ int hdcprx22KeyIndex = 0;
+ for (; hdcprx22KeyIndex < _HDCP22RxTypes; ++hdcprx22KeyIndex) {
+ const char* tmpKeyN = _hdcprx22Keys[hdcprx22KeyIndex];
+ if (!strcmp(keyName, tmpKeyN)) break;
+ }
+
DWN_DBG("to write key[%s] in len=%d\n", keyName, keyValLen);
- if (!strcmp(keyName, _AML_HDCP22_RX_KEY_NAME))
+ if (hdcprx22KeyIndex < _HDCP22RxTypes)
{
const AmlResImgHead_t* packedImgHead = (AmlResImgHead_t*)keyVal;
const AmlResItemHead_t* packedImgItem = (AmlResItemHead_t*)(packedImgHead + 1);
+ const struct AmlHdcp22RxKey* _amlHdcp22RxKey = _amlHdcp22RxKeys[hdcprx22KeyIndex];
int i = 0;
const unsigned gensum = add_sum(keyVal + 4, keyValLen - 4);
@@ -139,18 +160,29 @@
for (i = 0; i < packedImgHead->imgItemNum; ++i)
{
const AmlResItemHead_t* pItem = packedImgItem + i;
- const char* itemN = _amlHdcp22RxKeys[i].keyName;
+ const char* itemN = pItem->name;
u8* itembuf = (u8*)keyVal + pItem->dataOffset;
int itemSz = pItem->dataSz;
+ int k = 0;
- if (_amlHdcp22RxKeys[i].isEncrypt) {
+ for (; k < _HDCP22_MAX_KEY_NUM;++k) {
+ ret = strcmp(_amlHdcp22RxKey[k].itemName, itemN);
+ if (ret) continue;
+ break;
+ }
+ if ( _HDCP22_MAX_KEY_NUM == k ) {
+ DWN_ERR("Err, cannot find keyname for item[%d] %s\n", i, itemN);
+ return 0;
+ }
+ if (_amlHdcp22RxKey[k].isEncrypt) {
DWN_MSG("key[%s] at[%d] isEncrypted\n", itemN, i);
hdcp2DataDecryption(itemSz, (char*)itembuf, (char*)itembuf);
}
- DWN_MSG("burnkey[%s] at sz[%d]\n", itemN, itemSz);
- ret = key_manage_write(itemN, itembuf, itemSz);
- if (ret) {
- DWN_ERR("Fail to write key[%s] in len=%d\n", itemN, itemSz);
+ const char* keyN = _amlHdcp22RxKey[k].keyName;
+ DWN_MSG("burnkey[%s] at sz[%d]\n", keyN, itemSz);
+ ret = key_manage_write(keyN, itembuf, itemSz);
+ if (ret != 0) {
+ DWN_ERR("Fail to write key[[%s] in len=%d\n", keyN, itemSz);
return 0;
}
}
@@ -158,7 +190,7 @@
else
{
ret = key_manage_write(keyName, keyVal, keyValLen);
- if (ret) {
+ if (ret != 0) {
DWN_ERR("Fail to write key[%s] in len=%d\n", keyName, keyValLen);
return 0;
}
@@ -235,7 +267,14 @@
const char* queryKey = subCmd_argv[1];
int keyIsBurned = 0;
- if (!strcmp(_AML_HDCP22_RX_KEY_NAME, queryKey)) queryKey = _amlHdcp22RxKeys[0].keyName;
+ int hdcprx22KeyIndex = 0;
+ for (; hdcprx22KeyIndex < _HDCP22RxTypes; ++hdcprx22KeyIndex) {
+ const char* tmpKeyN = _hdcprx22Keys[hdcprx22KeyIndex];
+ if (!strcmp(queryKey, tmpKeyN)) {
+ queryKey = _amlHdcp22RxKeys[hdcprx22KeyIndex][0].keyName;
+ break;
+ }
+ }
rcode = key_manage_query_exist(queryKey, &keyIsBurned);
if (rcode) {
@@ -258,7 +297,14 @@
int exist = 0;
int canOverWrite = 0;
- if (!strcmp(_AML_HDCP22_RX_KEY_NAME, queryKey)) queryKey = _amlHdcp22RxKeys[0].keyName;
+ int hdcprx22KeyIndex = 0;
+ for (; hdcprx22KeyIndex < _HDCP22RxTypes; ++hdcprx22KeyIndex) {
+ const char* tmpKeyN = _hdcprx22Keys[hdcprx22KeyIndex];
+ if (!strcmp(queryKey, tmpKeyN)) {
+ queryKey = _amlHdcp22RxKeys[hdcprx22KeyIndex][0].keyName;
+ break;
+ }
+ }
rcode = key_manage_query_canOverWrite(queryKey, &canOverWrite);
if (rcode) {
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_fat.c b/drivers/usb/gadget/v2_burning/v2_common/optimus_fat.c
index 785b5b5..f630cc3 100644
--- a/drivers/usb/gadget/v2_burning/v2_common/optimus_fat.c
+++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_fat.c
@@ -1,14 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file optimus_fat.c
- * \brief fopen/fread/fclose for fat32
- *
- * \version 1.0.0
- * \date 2018/11/08
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2018 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
// SPDX-License-Identifier: GPL-2.0+
/*
* fat.c
@@ -156,15 +150,15 @@
*s_name = DELETED_FLAG;
}
-static int flush_dirty_fat_buffer(fsdata *mydata);
-#if !defined(CONFIG_FAT_WRITE)
+//static int flush_dirty_fat_buffer(fsdata *mydata);
+//#if !defined(CONFIG_FAT_WRITE)
/* Stub for read only operation */
static int flush_dirty_fat_buffer(fsdata *mydata)
{
(void)(mydata);
return 0;
}
-#endif
+//#endif
/*
* Get the entry at index 'entry' in a FAT (12/16/32) table.
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_img_decoder.c b/drivers/usb/gadget/v2_burning/v2_common/optimus_img_decoder.c
index d332426..200798b 100644
--- a/drivers/usb/gadget/v2_burning/v2_common/optimus_img_decoder.c
+++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_img_decoder.c
@@ -1,14 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file optimus_img_decoder.c
- * \brief
- *
- * \version 1.0.0
- * \date 2013-7-8
- * \author Sam.Wu <yihui.wu@amlogic.com>
- *
- * Copyright (c) 2013 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "../v2_sdc_burn/optimus_sdc_burn_i.h"
//FIMXE:
@@ -71,7 +65,7 @@
if (!strcmp("store", interface))
{
DWN_DBG("imgHead=0x%p, hImg=%p\n", &hImg->imgHead, hImg);
- ret = store_read(part, IMG_OFFSET_IN_PART, HeadSz, &hImg->imgHead);
+ ret = store_logic_read(part, IMG_OFFSET_IN_PART, HeadSz, &hImg->imgHead);
if (ret) {
DWN_ERR("Fail to read image header.\n");
ret = __LINE__; goto _err;
@@ -119,6 +113,12 @@
return NULL;
}
+unsigned image_get_crc(HIMAGE hImg)
+{
+ ImgInfo_t* imgInfo = (ImgInfo_t*)hImg;
+ return imgInfo->imgHead.crc;
+}
+
//close a Amlogic firmware image
int image_close(HIMAGE hImg)
@@ -292,7 +292,7 @@
DWN_MSG("offsetInPart %llx, wantSz=%x\n", offsetInPart, wantSz);
bufInABlk = (u8*)malloc(storeBlkSz);
- rc = store_read(part, readOffset, storeBlkSz, bufInABlk);
+ rc = store_logic_read(part, readOffset, storeBlkSz, bufInABlk);
if (rc) {
DWN_ERR("Fail to read: readOffset=%llx, storeBlkSz=%x\n", readOffset, storeBlkSz);
free(bufInABlk);
@@ -305,9 +305,9 @@
if (sizeNotAlignInFirstBlk < wantSz && offsetNotAlign)
{
- rc = store_read(part, (offsetInPart + sizeNotAlignInFirstBlk), thisTotalReadSz, pBuf);
+ rc = store_logic_read(part, (offsetInPart + sizeNotAlignInFirstBlk), thisTotalReadSz, pBuf);
if (rc) {
- DWN_ERR("Fail in store_read_ops to read %u at offset %llx.\n", wantSz,
+ DWN_ERR("Fail in store_logic_read_ops to read %u at offset %llx.\n", wantSz,
offsetInPart + sizeNotAlignInFirstBlk);
return __LINE__;
}
@@ -315,9 +315,9 @@
}
else
{
- rc = store_read(part, offsetInPart, wantSz, pBuf);
+ rc = store_logic_read(part, offsetInPart, wantSz, pBuf);
if (rc) {
- DWN_ERR("Fail in store_read_ops to read %u at offset %llx.\n", wantSz, offsetInPart);
+ DWN_ERR("Fail in store_logic_read_ops to read %u at offset %llx.\n", wantSz, offsetInPart);
return __LINE__;
}
}
@@ -447,6 +447,99 @@
return dataPartsSz;
}
+int optimus_img_item2buf(HIMAGE hImg, const char* main, const char* sub, char* buf, int* bufsz)
+{
+ HIMAGEITEM hImgItem = NULL;
+ hImgItem = image_item_open(hImg, main, sub);
+
+ if (!hImgItem) {
+ DWN_WRN("Fail to open item [%s,%s]\n", main, sub);
+ return ITEM_NOT_EXIST;
+ }
+
+ const s64 itemSz = image_item_get_size(hImgItem);
+ if (!itemSz) {
+ DWN_ERR("Item size 0\n");
+ image_item_close(hImgItem); return __LINE__;
+ }
+ if (itemSz > *bufsz) {
+ DWN_ERR("item sz %lld > bufsz %d\n", itemSz, *bufsz);
+ image_item_close(hImgItem); return __LINE__;
+ }
+
+ int rc = image_item_read(hImg, hImgItem, buf, (unsigned)itemSz);
+ if (rc) {
+ DWN_ERR("Fail read item data, rc %d\n", rc);
+ image_item_close(hImgItem); return __LINE__;
+ }
+
+ image_item_close(hImgItem);
+ *bufsz = itemSz;
+ return 0;
+}
+
+//get item num which has same main_type
+int get_subtype_nr(HIMAGE hImg, const char* main_type)
+{
+ int i = 0;
+ int ret = 0;
+ int itemNum = 0;
+ const int totalItemNum = get_total_itemnr(hImg);
+
+ for (i = 0; i < totalItemNum; i++)
+ {
+ const char* mainType = NULL;
+ const char* sub_type = NULL;
+
+ ret = get_item_name(hImg, i, &mainType, &sub_type);
+ if (ret) {
+ DWN_ERR("Exception:fail to get item name!\n");
+ return -__LINE__;
+ }
+
+ if (strcmp(main_type, mainType)) continue;
+ itemNum += 1;
+ }
+
+ return itemNum;
+}
+
+int get_subtype_nm_by_index(HIMAGE hImg, const char* main_type, const char** sub_type, const int itemIndex)
+{
+ int i = 0;
+ int ret = 0;
+ int itemNum = 0;
+ const int totalItemNum = get_total_itemnr(hImg);
+ const int nSubType = get_subtype_nr(hImg, main_type);
+
+ if (nSubType < 1) {
+ DWN_ERR("err main type[%s]\n", main_type);
+ return -__LINE__;
+ }
+ if (nSubType <= itemIndex) {
+ DWN_ERR("item index %d > max %d for main[%s]\n", itemIndex, nSubType, main_type);
+ return -__LINE__;
+ }
+
+ for (i = 0; i < totalItemNum; i++)
+ {
+ const char* mainType = NULL;
+
+ ret = get_item_name(hImg, i, &mainType, sub_type);
+ if (ret) {
+ DWN_ERR("Exception:fail to get item name!\n");
+ return __LINE__;
+ }
+
+ if (strcmp(mainType, main_type)) continue;
+ if (itemIndex == itemNum) return OPT_DOWN_OK;
+ itemNum += 1;
+ }
+
+ return OPT_DOWN_FAIL;
+}
+
+
#define MYDBG 0
#if MYDBG
static int test_item(HIMAGE hImg, const char* main_type, const char* sub_type, char* pBuf, const int sz)
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_progress.c b/drivers/usb/gadget/v2_burning/v2_common/optimus_progress.c
index 3080fc3..ddae689 100644
--- a/drivers/usb/gadget/v2_burning/v2_common/optimus_progress.c
+++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_progress.c
@@ -1,14 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file optimus_report_progress.c
- * \brief display and print progress info when burning a partition
- *
- * \version 1.0.0
- * \date 2013/6/23
- * \author Sam.Wu <wuehui@allwinnertech.com>
- *
- * Copyright (c) 2013 Allwinner Technology. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "../v2_burning_i.h"
#define OPTIMUS_PROMPT_SIZE_MIN (4U<<20)//mininal size to prompt burning progress step
@@ -140,3 +134,60 @@
return sum;
}
+#ifndef SCPI_CMD_USB_BOOT
+#define SCPI_CMD_USB_BOOT 0xB0 //skip to wait pc with timeout
+#define SCPI_CMD_USB_UNBOOT 0xB1 //skip to wait pc forever
+#define SCPI_CMD_SDCARD_BOOT 0xB2
+#define SCPI_CMD_CLEAR_BOOT 0xB3
+static void _erase_bootloader(uint64_t arg0)
+{
+ if (SCPI_CMD_CLEAR_BOOT == arg0) return;//dummy as not supported
+
+ const char* bootName = "bootloader";
+ const int bootCpyNum = store_boot_copy_num(bootName);
+
+ printf("arg0[0x%llx]\n", arg0);
+ printf("set_boot_first_timeout not defined so Really erase\n");
+ int iCopy = 0;
+ for (; iCopy < bootCpyNum; ++iCopy) {
+ store_boot_erase(bootName, iCopy);
+ }
+}
+extern void set_boot_first_timeout(uint64_t arg0) __attribute__((weak, alias("_erase_bootloader")));
+
+#include <asm/arch/bl31_apis.h>
+#include <amlogic/cpu_id.h>
+#endif//#ifndef SCPI_CMD_USB_BOOT
+//I assume that store_inited yet when "bootloader_is_old"!!!!
+int optimus_erase_bootloader(const char* extBootDev)
+{
+ if (!strcmp("usb", extBootDev))
+ {
+ set_boot_first_timeout(SCPI_CMD_USB_UNBOOT);
+ return 0;
+ }
+
+ if (!strcmp("usb-timeout", extBootDev))
+ {
+ set_boot_first_timeout(SCPI_CMD_USB_BOOT);
+ return 0;
+ }
+
+ if (!strcmp("sdc", extBootDev))
+ {
+ cpu_id_t cpuid = get_cpu_id();
+ if (MESON_CPU_MAJOR_ID_C1 == cpuid.family_id && MESON_CPU_CHIP_REVISION_A == cpuid.chip_rev)
+ _erase_bootloader(SCPI_CMD_SDCARD_BOOT);
+ else
+ set_boot_first_timeout(SCPI_CMD_SDCARD_BOOT);
+ return 0;
+ }
+
+ return 0;
+}
+
+void optimus_clear_ovd_register(void)
+{
+ set_boot_first_timeout(SCPI_CMD_CLEAR_BOOT);
+}
+
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_progress_ui.c b/drivers/usb/gadget/v2_burning/v2_common/optimus_progress_ui.c
index bccffe7..44c2152 100644
--- a/drivers/usb/gadget/v2_burning/v2_common/optimus_progress_ui.c
+++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_progress_ui.c
@@ -1,14 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file optimus_progress_ui.c
- * \brief Show progress info to UI
- *
- * \version 1.0.0
- * \date 2013/10/13
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2013 Amlogic Inc.. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "../v2_burning_i.h"
#include <bmp_layout.h>
#include <lcd.h>
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_progress_ui.h b/drivers/usb/gadget/v2_burning/v2_common/optimus_progress_ui.h
index faf8ab4..7e3f263 100644
--- a/drivers/usb/gadget/v2_burning/v2_common/optimus_progress_ui.h
+++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_progress_ui.h
@@ -1,14 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * \file optimus_progress_ui.h
- * \brief interfaces of optimus_progress_ui.c
- *
- * \version 1.0.0
- * \date 2013/10/13
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2013 Amlogic Inc.. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#ifndef __OPTIMUS_PROGRESS_UI__
#define __OPTIMUS_PROGRESS_UI__
diff --git a/drivers/usb/gadget/v2_burning/v2_common/optimus_simg2img.c b/drivers/usb/gadget/v2_burning/v2_common/optimus_simg2img.c
index 9881d36..3717941 100644
--- a/drivers/usb/gadget/v2_burning/v2_common/optimus_simg2img.c
+++ b/drivers/usb/gadget/v2_burning/v2_common/optimus_simg2img.c
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file optimus_simg2img.c
- * \brief sparse image to ext4 image in optimus system
- * a sparse image consit of "file_header + chunk_num * (chunk_header + [chunk_data]),
- * chunk data can be empty when chunk type is CHUNK_TYPE_DONT_CARE"
- *
- * \version 1.0.0
- * \date 2013/5/6
- * \author Sam.Wu <yihui.wu@Amlogic.com>
- *
- * Copyright (c) 2013 Amlogic Inc. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "../v2_burning_i.h"
#include <partition_table.h>
diff --git a/drivers/usb/gadget/v2_burning/v2_common/sparse_format.h b/drivers/usb/gadget/v2_burning/v2_common/sparse_format.h
index 6c62c34..a13c637 100644
--- a/drivers/usb/gadget/v2_burning/v2_common/sparse_format.h
+++ b/drivers/usb/gadget/v2_burning/v2_common/sparse_format.h
@@ -1,17 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Copyright (C) 2010 The Android Open Source Project
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
typedef struct sparse_header {
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini__aml_sdc_burn.c b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini__aml_sdc_burn.c
index 861f09c..ab1e467 100644
--- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini__aml_sdc_burn.c
+++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini__aml_sdc_burn.c
@@ -1,14 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file optimus_ini__aml_sdc_burn.c
- * \brief parse the aml_sdc_burn.ini
- *
- * \version 1.0.0
- * \date 2015/2/3
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2015 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "optimus_sdc_burn_i.h"
#define dbg(fmt ...) //printf("[INI_SDC]"fmt)
@@ -31,8 +25,8 @@
ConfigPara_t g_sdcBurnPara = {
.setsBitMap.burnParts = 0,
- .setsBitMap.custom = 0,
- .setsBitMap.burnEx = 0,
+ .setsBitMap.custom = 1,
+ .setsBitMap.burnEx = 1,
.burnParts = {
.burn_num = 0,
@@ -40,14 +34,14 @@
},
.custom = {
- .eraseBootloader = 1,//default to erase bootloader!
- .eraseFlash = 0,
- .bitsMap.eraseBootloader = 0,
- .bitsMap.eraseFlash = 0,
+ .eraseBootloader = 1,//default to erase bootloader! no effect for usb_upgrade
+ .eraseFlash = 1,//default erase flash for all cases
+ .bitsMap.eraseBootloader = 1,
+ .bitsMap.eraseFlash = 1,
},
.burnEx = {
- .bitsMap.pkgPath = 0,
+ .bitsMap.pkgPath = 1,
.bitsMap.mediaPath = 0,
},
};
@@ -90,7 +84,7 @@
return 0;
}
-static int print_sdc_burn_para(const ConfigPara_t* pCfgPara)
+int print_sdc_burn_para(const ConfigPara_t* pCfgPara)
{
printf("\n=========sdc_burn_paras=====>>>\n");
@@ -136,7 +130,7 @@
return __LINE__;
}
- strcpy(pBurnEx->pkgPath, strVal);
+ strncpy(pBurnEx->pkgPath, strVal, sizeof pBurnEx->pkgPath - 1);
pBurnEx->bitsMap.pkgPath = 1;
return 0;
@@ -150,7 +144,7 @@
}
if (strVal)
{
- strcpy(pBurnEx->mediaPath, strVal);
+ strncpy(pBurnEx->mediaPath, strVal, sizeof pBurnEx->mediaPath - 1);
pBurnEx->bitsMap.mediaPath = 1;
}
@@ -245,6 +239,19 @@
}
+ if (!strcmp(key, "erase_ddr_para"))
+ {
+ if (pCustome->bitsMap.eraseDdrPara) {
+ goto _key_dup;
+ }
+
+ if (strVal)
+ {
+ pCustome->eraseDdrPara = cfgVal;
+ pCustome->bitsMap.eraseDdrPara = 1;
+ }
+ }
+
return 0;
_key_dup:
@@ -323,7 +330,7 @@
return __LINE__;
}
- strcpy(partName, strVal);
+ strncpy(partName, strVal, PART_NAME_LEN_MAX - 1);
}
return 0;
@@ -399,7 +406,7 @@
return ret;
}
-int parse_ini_cfg_file(const char* filePath)
+static int _parse_ini_cfg_file(const char* filePath, HIMAGE hImg)
{
const int MaxFileSz = OPTIMUS_DOWNLOAD_SLOT_SZ;
char* CfgFileLoadAddr = (char*)OPTIMUS_DOWNLOAD_TRANSFER_BUF_ADDR;
@@ -410,7 +417,20 @@
init_config_para(&g_sdcBurnPara);
- validLineNum = parse_ini_file_2_valid_lines(filePath, CfgFileLoadAddr, MaxFileSz, lines);
+ if (hImg) {
+ DWN_MSG("try to fetch para from item aml_sdc_burn.ini\n");
+ int itemSz = MaxFileSz;
+ rcode = optimus_img_item2buf(hImg, "ini", "aml_sdc_burn", CfgFileLoadAddr, &itemSz);
+ if (ITEM_NOT_EXIST == rcode) {
+ DWN_MSG("Item ini not existed, so use hard-coded para\n");
+ return ITEM_NOT_EXIST;
+ } else if(rcode) {
+ DWN_ERR("Err when get item ini, rcode %d\n", rcode);
+ return __LINE__;
+ } else
+ validLineNum = parse_ini_buf_2_valid_lines(CfgFileLoadAddr, itemSz, lines);
+ } else
+ validLineNum = parse_ini_file_2_valid_lines(filePath, CfgFileLoadAddr, MaxFileSz, lines);
if (!validLineNum) {
err("error in parse ini file\n");
return __LINE__;
@@ -435,6 +455,16 @@
return 0;
}
+int parse_ini_cfg_file(const char* filePath)
+{
+ return _parse_ini_cfg_file(filePath, NULL);
+}
+
+int parse_ini_cfg_from_item(HIMAGE hImg)
+{
+ return _parse_ini_cfg_file(NULL, hImg);
+}
+
#define MYDBG 0
#if MYDBG
int do_ini_parser(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini_parser.c b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini_parser.c
index 3d2e753..a201349 100644
--- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini_parser.c
+++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_ini_parser.c
@@ -1,14 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file optimus_ini_parser.c
- * \brief ini parsing utilities for sdc burnning
- *
- * \version 1.0.0
- * \date 2013-7-11
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2013 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "optimus_sdc_burn_i.h"
#define dbg(fmt ...) //printf("[INI]"fmt)
@@ -230,6 +224,28 @@
return lineNum;
}
+int parse_ini_buf_2_valid_lines(char* iniBuf, const unsigned bufSz, char* lines[])
+{
+ const int MaxLines = 1024;//
+ int ret = 0;
+ unsigned lineNum = 0;
+
+ iniBuf[bufSz] = 0;
+
+ //step1:first loop to seprate buffer to lines
+ ret = _optimus_parse_buf_2_lines(iniBuf, bufSz, (const char**)lines, &lineNum, MaxLines);
+ if (ret) {
+ err("Fail to parse buf to lines.ret=%d\n", ret);
+ return 0;
+ }
+
+ //step 2: abandon comment or space lines
+ ret = _optimus_abandon_ini_comment_lines(lines, lineNum);
+
+ return lineNum;
+}
+
+
int optimus_ini_trans_lines_2_usr_params(const char* const lines[], const unsigned lineNum,
int (*pCheckSetUseFul)(const char* setName),
int (*pParseCfgVal)(const char* setName, const char* keyName, const char* keyVal))
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_led.c b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_led.c
index 8c86235..095bbbe 100644
--- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_led.c
+++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_led.c
@@ -1,14 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file optimus_led.c
- * \brief use led to indicate burning states
- *
- * \version 1.0.0
- * \date 2013/11/9
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2013 Amlogic Inc.. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "../v2_burning_i.h"
#include "optimus_led.h"
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_led.h b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_led.h
index 40ae2c3..782ac9b 100644
--- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_led.h
+++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_led.h
@@ -1,15 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * \file optimus_led.h
- * \brief show burning states by LED
- * current supported LED source is PWM, other type not supported yet!
- *
- * \version 1.0.0
- * \date 2013/11/9
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2013 Amlogic Inc.. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#ifndef __OPTIMUS_LED_H__
#define __OPTIMUS_LED_H__
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn.c b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn.c
index 82786aa..63e87d6 100644
--- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn.c
+++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn.c
@@ -1,14 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file optimus_sdc_burn.c
- * \brief burning itself from Pheripheral tf/sdmmc card
- *
- * \version 1.0.0
- * \date 2013-7-11
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2013 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "optimus_sdc_burn_i.h"
#include "optimus_led.h"
#include <asm/arch/secure_apb.h>
@@ -18,9 +12,14 @@
static int is_bootloader_old(void)
{
- int sdc_boot = is_tpl_loaded_from_ext_sdmmc();
+ const int sdc_boot = is_tpl_loaded_from_ext_sdmmc();
+ const int usbDiskNewBoot = env_get_hex("usbDiskNewBoot", 0);//default old
- return !sdc_boot;
+ switch (optimus_work_mode_get()) {
+ case OPTIMUS_WORK_MODE_SDC_PRODUCE: return !sdc_boot;
+ case OPTIMUS_WORK_MODE_UDISK_PRODUCE: return !usbDiskNewBoot;
+ default: return 1;//default old
+ }
}
int get_burn_parts_from_img(HIMAGE hImg, ConfigPara_t* pcfgPara)
@@ -52,7 +51,7 @@
if (OPTIMUS_WORK_MODE_SYS_RECOVERY == optimus_work_mode_get()) continue;
}
- strcpy(partName, sub_type);
+ strncpy(partName, sub_type, PART_NAME_LEN_MAX - 1);
pburnPartsCfg->bitsMap4BurnParts |= 1U<<burnNum;
burnNum += 1;
}
@@ -131,7 +130,7 @@
u32 thisReadLen = 0;
__hdle hImgItem = NULL;
char* downTransBuf = NULL;//get buffer from optimus_buffer_manager
- const unsigned ItemReadBufSz = OPTIMUS_DOWNLOAD_SLOT_SZ;//read this size from image item each time
+ const unsigned ItemReadBufSz = OPTIMUS_LOCAL_UPGRADE_SLOT_SZ;//read this size from image item each time
unsigned sequenceNo = 0;
const char* fileFmt = NULL;
/*static */char _errInfo[512];
@@ -180,7 +179,7 @@
goto _finish;
}
- //If the item head is not alinged to FAT cluster, Read it firstly to speed up mmc read
+ //If the item head is not alinged to FAT cluster, Read it firstly to speed up mmc read
if (itemSizeNotAligned && !sequenceNo)
{
if ( itemSizeNotAligned >= imgItemSz ) {
@@ -191,7 +190,7 @@
rcode = __LINE__; goto _finish;
}
}
- DWN_DBG("itemSizeNotAligned 0x%x, itemSizePreload 0x%x\n", itemSizeNotAligned, itemSizePreload);
+ DWN_MSG("itemSizeNotAligned 0x%x, itemSizePreload 0x%x\n", itemSizeNotAligned, itemSizePreload);
rcode = image_item_read(hImg, hImgItem, downTransBuf - itemSizePreload, itemSizePreload);
if (rcode) {
DWN_ERR("fail in read data from item,rcode %d, len 0x%x, sequenceNo %d\n", rcode, itemSizePreload, sequenceNo);
@@ -235,11 +234,11 @@
rcode = optimus_verify_partition(partName, hImg, _errInfo);
if (ITEM_NOT_EXIST == rcode)
{
- printf("WRN:part(%s) NOT verified\n", partName);
+ DWN_WRN("WRN:part(%s) NOT verified\n", partName);
return 0;
}
if (rcode) {
- printf("Fail in verify part(%s)\n", partName);
+ DWN_ERR("Fail in verify part(%s)\n", partName);
optimus_progress_ui_printf("Failed at VERIFY part[%s]\n", partName);
return __LINE__;
}
@@ -267,8 +266,8 @@
DWN_DBG("Data part num %d\n", burnNum);
}
if (!burnNum) {
- DWN_ERR("Data part num is 0!!\n");
- return __LINE__;
+ DWN_WRN("Data part num is 0!!\n");
+ /*return __LINE__;*/
}
for (i = 0; i < burnNum; i++)
@@ -337,11 +336,14 @@
unsigned char* dtbTransferBuf = (unsigned char*)partBaseOffset;
//meson1.dtb but not meson.dtb for m8 compatible
+#ifdef CONFIG_CMD_EFUSE
if (IS_FEAT_BOOT_VERIFY()) {
DWN_MSG("SecureEnabled, use meson1_ENC\n");
hImgItem = image_item_open(hImg, partName, "meson1_ENC");
}
- else {
+#endif//#ifdef CONFIG_CMD_EFUSE
+ if (!hImgItem)
+ {
hImgItem = image_item_open(hImg, partName, "meson1");
}
if (!hImgItem) {
@@ -472,7 +474,7 @@
}
//burn the amlogic keys like USB_Burning_Tool
-static int sdc_burn_aml_keys(HIMAGE hImg, const int keyOverWrite)
+int sdc_burn_aml_keys(HIMAGE hImg, const int keyOverWrite, int licenseKey, int imgKey)
{
int rc = 0;
const char* *keysName = NULL;
@@ -480,12 +482,6 @@
const char** pCurKeysName = NULL;
unsigned index = 0;
- rc = run_command("aml_key_burn probe vfat sdc", 0);
- if (rc) {
- DWN_ERR("Fail in probe for aml_key_burn\n");
- return __LINE__;
- }
-
{
unsigned random32 = 0;
unsigned seed = 0;
@@ -508,7 +504,17 @@
DWN_ERR("Fail to parse keys.conf, rc =%d\n", rc);
return __LINE__;
}
- DWN_MSG("keys.conf:\n");
+ if (keysNum > 0) {
+ if (strcmp("1", getenv("usb_update")))
+ rc = run_command("aml_key_burn probe vfat sdc", 0);
+ else
+ rc = run_command("aml_key_burn probe vfat udisk", 0);
+ if (rc) {
+ DWN_ERR("Fail in probe for aml_key_burn\n");
+ return __LINE__;
+ }
+ DWN_MSG("keys.conf:\n");
+ }
for (index = 0; index < keysNum; ++index)printf("\tkey[%d]\t%s\n", index, keysName[index]) ;
rc = optimus_sdc_keysprovider_init();
@@ -564,6 +570,40 @@
}
}
+ const char* mainTypeKey = "AML_KEY";
+ const int nrItems = get_subtype_nr(hImg, mainTypeKey);
+ for (index = 0; index < nrItems; ++index)
+ {
+ const char* keyName = NULL;
+ if (get_subtype_nm_by_index(hImg, mainTypeKey, &keyName, index)) {
+ DWN_ERR("fail in get key[%d] subtype\n", index);
+ return -__LINE__;
+ }
+ DWN_MSG("Now burn IMG key <---- [%s] ----> %d \n", keyName, index);
+ rc = sdc_check_key_need_to_burn(keyName, keyOverWrite);
+ if (rc < 0) {
+ DWN_ERR("Fail when when check stauts for key(%s)\n", keyName);
+ /*return __LINE__;*/
+ }
+ if (!rc) continue;//not need to burn this key
+
+ //1,using cmd_keysprovider to read a key to memory
+ char* keyValue = (char*)OPTIMUS_DOWNLOAD_TRANSFER_BUF_ADDR;
+ int keySz = OPTIMUS_DOWNLOAD_SLOT_SZ;//buffer size
+ rc = optimus_img_item2buf(hImg, mainTypeKey, keyName, keyValue, &keySz);
+ if (rc) {
+ DWN_ERR("Fail to get value for key[%s]\n", keyName);
+ return __LINE__;
+ }
+
+ //3, burn the key
+ rc = optimus_keysburn_onekey(keyName, (u8*)keyValue, keySz);
+ if (rc) {
+ DWN_ERR("Fail in burn the key[%s] at addr=%p, sz=%d\n", keyName, keyValue, keySz);
+ return __LINE__;
+ }
+ }
+
rc = optimus_sdc_keysprovider_exit();
if (rc) {
DWN_ERR("Fail in optimus_sdc_keysprovider_exit\n");
@@ -591,23 +631,63 @@
ConfigPara_t* pSdcCfgPara = &g_sdcBurnPara;
const char* pkgPath = pSdcCfgPara->burnEx.pkgPath;
__hdle hUiProgress = NULL;
+ int hasBootloader = 0;
+ u64 datapartsSz = 0;
+ int eraseFlag = pSdcCfgPara->custom.eraseFlash;
- ret = parse_ini_cfg_file(cfgFile);
- if (ret) {
- DWN_ERR("Fail to parse file %s\n", cfgFile);
- ret = __LINE__; goto _finish;
+ optimus_buf_manager_init(16*1024);
+ hImg = image_open("mmc", "0", "1", cfgFile);
+ if (!hImg) {
+ DWN_MSG("cfg[%s] not valid aml pkg, parse it as ini\n", cfgFile);
+ ret = parse_ini_cfg_file(cfgFile);
+ if (ret) {
+ DWN_ERR("Fail to parse file %s\n", cfgFile);
+ ret = __LINE__; goto _finish;
+ }
+ } else {//cfg path is valid aml pkg
+ DWN_MSG("cfg %s is valid aml pkg\n", cfgFile);
+
+ ret = parse_ini_cfg_from_item(hImg);
+ if (ITEM_NOT_EXIST == ret) {
+ ret = check_cfg_burn_parts(pSdcCfgPara);
+ if (ret) {
+ DWN_ERR("Fail in check burn parts.\n");
+ ret = __LINE__; goto _finish;
+ }
+ extern int print_sdc_burn_para(const ConfigPara_t* pCfgPara);
+ print_sdc_burn_para(pSdcCfgPara);
+ }
+ memcpy((void*)pkgPath, cfgFile, strnlen(cfgFile, 128));
}
- if (pSdcCfgPara->custom.eraseBootloader && strcmp("1", getenv("usb_update")))
+ hImg = hImg ? hImg : image_open("mmc", "0", "1", pkgPath);
+ if (!hImg) {
+ DWN_ERR("Fail to open image %s\n", pkgPath);
+ ret = __LINE__; goto _finish;
+ }
+ const int eraseBootloader = pSdcCfgPara->custom.eraseBootloader;
+ const int usbDiskUpgrade = (OPTIMUS_WORK_MODE_UDISK_PRODUCE == optimus_work_mode_get());
+ if (eraseBootloader && is_bootloader_old())
{
- if (is_bootloader_old())
- {
+ if (usbDiskUpgrade) {//upgrade new bootloader
+ if (optimus_burn_bootlader(hImg)) {
+ DWN_ERR("Fail in burn new bootloader from usb disk\n");
+ goto _finish;
+ }
+ setenv("usbDiskNewBoot", "1");
+ setenv("sdcburncfg", cfgFile);
+ setenv("usbDiskUpgrade", "run init_display; usb_burn $sdcburncfg");
+ setenv("preboot", "printenv usbDiskUpgrade; run usbDiskUpgrade");
+ run_command("saveenv", 0);
+ } else
+ {//sdc_burn
DWN_MSG("To erase OLD bootloader !\n");
ret = optimus_erase_bootloader("sdc");
if (ret) {
DWN_ERR("Fail to erase bootloader\n");
ret = __LINE__; goto _finish;
}
+ }
#if defined(CONFIG_VIDEO_AMLLCD)
//axp to low power off LCD, no-charging
@@ -622,7 +702,6 @@
DWN_MSG("Reset to load NEW uboot from ext-mmc!\n");
optimus_reset(OPTIMUS_BURN_COMPLETE__REBOOT_SDC_BURN);
return __LINE__;//should never reach here!!
- }
}
if (OPTIMUS_WORK_MODE_SDC_PRODUCE == optimus_work_mode_get()) //led not depend on image res, can init early
@@ -634,12 +713,6 @@
optimus_led_show_in_process_of_burning();
}
- hImg = image_open("mmc", "0", "1", pkgPath);
- if (!hImg) {
- DWN_ERR("Fail to open image %s\n", pkgPath);
- ret = __LINE__; goto _finish;
- }
-
//update dtb for burning drivers
ret = optimus_sdc_burn_dtb_load(hImg);
if (ITEM_NOT_EXIST != ret && ret) {
@@ -661,19 +734,39 @@
}
optimus_progress_ui_direct_update_progress(hUiProgress, UPGRADE_STEPS_AFTER_IMAGE_OPEN_OK);
- int hasBootloader = 0;
- u64 datapartsSz = optimus_img_decoder_get_data_parts_size(hImg, &hasBootloader);
-
- int eraseFlag = pSdcCfgPara->custom.eraseFlash;
+ datapartsSz = optimus_img_decoder_get_data_parts_size(hImg, &hasBootloader);
if (!datapartsSz) {
eraseFlag = 0;
DWN_MSG("Disable erase as data parts size is 0\n");
}
- ret = optimus_storage_init(eraseFlag);
+ if (eraseFlag && !strcmp("1", getenv("usb_update"))) {
+ ret = optimus_storage_init(0);
+ if (ret) {
+ DWN_ERR("FAil in init flash for usb upgrade\n");
+ return __LINE__;
+ }
+
+ DWN_MSG("store_get_type %d\n", store_get_type());
+ //erase after bootloader for usb disk
+ if (BOOT_EMMC == store_get_type()) ret = run_command("echo amlmmc erase non_loader;amlmmc erase non_loader", 0);
+ else ret = run_command("echo store erase.chip; store erase.chip", 0);
+ }
+ else
+ ret = optimus_storage_init(eraseFlag);
if (ret) {
DWN_ERR("Fail to init stoarge for sdc burn\n");
- return __LINE__;
+ ret = __LINE__; goto _finish;
}
+#if 0
+ if (pSdcCfgPara->custom.eraseDdrPara) {
+ extern int store_ddr_parameter_erase(void);
+ DWN_MSG("to erase ddr parameters\n");
+ if (store_ddr_parameter_erase()) {
+ DWN_ERR("Fail in erase ddr parameters\n");
+ return -__LINE__;
+ }
+ }
+#endif
optimus_progress_ui_direct_update_progress(hUiProgress, UPGRADE_STEPS_AFTER_DISK_INIT_OK);
@@ -707,37 +800,37 @@
optimus_progress_ui_direct_update_progress(hUiProgress, UPGRADE_STPES_AFTER_BURN_DATA_PARTS_OK);
//TO burn nandkey/securekey/efusekey
- ret = sdc_burn_aml_keys(hImg, pSdcCfgPara->custom.keyOverwrite);
+ ret = sdc_burn_aml_keys(hImg, pSdcCfgPara->custom.keyOverwrite, 1, 1);
if (ret) {
DWN_ERR("Fail in sdc_burn_aml_keys\n");
ret = __LINE__;goto _finish;
}
-#if 1
if (hasBootloader)
{//burn bootloader
+ if (usbDiskUpgrade && env_get_hex("usbDiskNewBoot", 0)) {//already upgrade bootloader from pkg
+ ;
+ } else {
ret = optimus_burn_bootlader(hImg);
if (ret) {
- DWN_ERR("Fail in burn bootloader\n");
- goto _finish;
+ DWN_ERR("Fail in burn bootloader\n");
+ goto _finish;
}
- else
- {//update bootloader ENV only when bootloader image is burned
- ret = optimus_set_burn_complete_flag();
- if (ret) {
- DWN_ERR("Fail in set_burn_complete_flag\n");
- ret = __LINE__; goto _finish;
- }
- }
+ }
+ //update bootloader ENV only when bootloader image is burned
+ ret = optimus_set_burn_complete_flag();
+ if (ret) {
+ DWN_ERR("Fail in set_burn_complete_flag\n");
+ ret = __LINE__; goto _finish;
+ }
}
-#endif
optimus_progress_ui_direct_update_progress(hUiProgress, UPGRADE_STEPS_AFTER_BURN_BOOTLOADER_OK);
_finish:
image_close(hImg);
- optimus_progress_ui_report_upgrade_stat(hUiProgress, !ret);
+ if (hUiProgress) optimus_progress_ui_report_upgrade_stat(hUiProgress, !ret);
optimus_report_burn_complete_sta(ret, pSdcCfgPara->custom.rebootAfterBurn);
- optimus_progress_ui_release(hUiProgress);
+ if (hUiProgress) optimus_progress_ui_release(hUiProgress);
//optimus_storage_exit();//temporary not exit storage driver when failed as may continue burning after burn
return ret;
}
@@ -776,7 +869,7 @@
}
if ( !aml_check_is_ready_for_sdc_produce() ) {
- DWN_DBG("Not ready\n");
+ DWN_DBG("sdcard Not ready for sdc_burn\n");
return __LINE__;
}
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn_i.h b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn_i.h
index e5a897c..e5f896d 100644
--- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn_i.h
+++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_burn_i.h
@@ -1,14 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * \file optimus_sdc_burn_i.h
- * \brief internal struct types and interfaces for sdc burn
- *
- * \version 1.0.0
- * \date 2013-7-12
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2013 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#ifndef __OPTIMUS_SDC_BURN_I_H__
#define __OPTIMUS_SDC_BURN_I_H__
@@ -34,12 +28,14 @@
int eraseFlash;
int rebootAfterBurn;
int keyOverwrite;
+ int eraseDdrPara;
struct{
unsigned eraseBootloader : 1;
unsigned eraseFlash : 1;
unsigned rebootAfterBurn : 1;
unsigned keyOverwrite : 1;
- unsigned resev : 32 - 4;
+ unsigned eraseDdrPara : 1;
+ unsigned resev : 32 - 5;
}bitsMap;
}CustomPara_t;
@@ -74,13 +70,17 @@
//ini parser
int _optimus_parse_buf_2_lines(char* pTextBuf, const unsigned textSz, const char* lines[],
unsigned* totalLineNum, const unsigned MaxLines);//parse text context to linces delimitted by (\r)\n
+
int parse_ini_file_2_valid_lines(const char* filePath, char* iniBuf, const unsigned bufSz, char* lines[]);
+int parse_ini_buf_2_valid_lines(char* iniBuf, const unsigned bufSz, char* lines[]);
+
int _optimus_abandon_ini_comment_lines(char* lines[], const unsigned lineNum);
int optimus_ini_trans_lines_2_usr_params(const char* const lines[], const unsigned lineNum,
int (*pCheckSetUseFul)(const char* setName),
int (*pParseCfgVal)(const char* setName, const char* keyName, const char* keyVal));
int parse_ini_cfg_file(const char* filePath);
+int parse_ini_cfg_from_item(HIMAGE hImg);
int check_cfg_burn_parts(const ConfigPara_t* burnPara);
int print_burn_parts_para(const BurnParts_t* pBurnParts);
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_update.c b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_update.c
index 575b89b..4d0c8c8 100644
--- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_update.c
+++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/optimus_sdc_update.c
@@ -1,15 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file optimus_sdc_update.c
- * \brief sdc_update command to burn a parition image from mmc
- * this update based on the burner is latest: (uboot for burnner can run from peripherals such as sdmmc/usb)
- *
- * \version 1.0.0
- * \date 2014-9-15
- * \author Sam.Wu <yihui.wu@amlogic.com>
- * Chunyu.Song <chunyu.song@amlogic.com>
- * Copyright (c) 2014 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "optimus_sdc_burn_i.h"
#include <partition_table.h>
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/optimus_key_burn.c b/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/optimus_key_burn.c
index 88871b3..4f1f91a 100644
--- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/optimus_key_burn.c
+++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/optimus_key_burn.c
@@ -1,13 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file optimus_key_burn.c
- * \brief burning keys from sdcard like update.exe
- *
- * \version 1.0.0
- * \date 2014/12/25
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2014 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
/*
@@ -92,11 +85,13 @@
if (!_udiskProbe)
{
+#if 0
rc = run_command("usb start 0", 0);
if (rc) {
_AML_KEY_ERR("Fail in mmcinfo\n");
return __LINE__;
}
+#endif
rc = optimus_device_probe("usb", "0");
if (rc) {
_AML_KEY_ERR("Fail to detect device mmc 0\n");
@@ -161,39 +156,18 @@
{
int rc = 0;
unsigned keySz = 0;
+ char cmd[128];
if (DEV_FILE_FMT_VFAT == _optKeyInfo.fileFmt)
{
- long hFile = -1;
- unsigned readSz = 0;
-
-#if 1//FIXME: remove this mmcinfo
- /*rc = run_command("mmcinfo 0", 0);*/
- rc = optimus_sdc_burn_switch_to_extmmc();
- if (rc) {
- DWN_ERR("Fail in mmcinfo\n");
- return __LINE__;
- }
-#endif//
- keySz = (unsigned)do_fat_get_fileSz(filePath);//can support both sdc and udisk
- if (!keySz) {
- DWN_ERR("size is 0 of file [%s]\n", filePath);
- return __LINE__;
- }
-
- hFile = do_fat_fopen(filePath);
- if (hFile < 0) {
- DWN_ERR("Fail to open file[%s]\n", filePath);
- return __LINE__;
- }
-
- readSz = do_fat_fread(hFile, buf, keySz);
- if (readSz != keySz) {
- DWN_ERR("Want read %d bytes, but %d\n", keySz, readSz);
- return __LINE__;
- }
-
- do_fat_fclose(hFile);
+ if (strcmp("1", getenv("usb_update")))
+ sprintf(cmd, "fatload mmc 0 %p %s", buf, filePath);
+ else
+ sprintf(cmd, "fatload usb 0 %p %s", buf, filePath);
+ rc = run_command(cmd, 0);
+ if (rc) {
+ DWN_ERR("Fail in load key cmd[%s]\n", cmd);
+ }
}
*keyValLen = keySz;
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_bootPart_license.c b/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_bootPart_license.c
index d0b57d3..69642f4 100644
--- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_bootPart_license.c
+++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_bootPart_license.c
@@ -1,14 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file sdc_bootPart_license.c
- * \brief
- *
- * \version 1.0.0
- * \date 2015/3/10
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2015 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "../optimus_sdc_burn_i.h"
#include "sdc_bootPart_license.h"
#include <crc.h>
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_bootPart_license.h b/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_bootPart_license.h
index 37503ad..57f9128 100644
--- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_bootPart_license.h
+++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_bootPart_license.h
@@ -1,14 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * \file sdc_bootPart_license.h
- * \brief Interfaces to read/update license in boot part
- *
- * \version 1.0.0
- * \date 2015/3/10
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2015 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#ifndef __V2_SDC_BURN_SDC_BOOTPART_LICENSE_H__
#define __V2_SDC_BURN_SDC_BOOTPART_LICENSE_H__
diff --git a/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_keysprovider.c b/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_keysprovider.c
index 91914fe..53784f5 100644
--- a/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_keysprovider.c
+++ b/drivers/usb/gadget/v2_burning/v2_sdc_burn/sdc_burnkeys/sdc_keysprovider.c
@@ -1,14 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file sdc_keysprovider.c
- * \brief Parse users' nankey/efusekey like PC's keysprovider.dll in sdcard burning mode
- *
- * \version 1.0.0
- * \date 2014/12/25
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2014 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "../optimus_sdc_burn_i.h"
#include "sdc_bootPart_license.h"
@@ -400,7 +394,10 @@
optimus_sdc_burn_switch_to_extmmc();
- sprintf(_cmd, "fatload mmc 0:1 0x%p %s", keyVal, licenseName);
+ if (strcmp("1", getenv("usb_update")))
+ sprintf(_cmd, "fatload mmc 0:1 0x%p %s", keyVal, licenseName);
+ else
+ sprintf(_cmd, "fatload usb 0:1 0x%p %s", keyVal, licenseName);
rc = run_command(_cmd, 0);
if (rc) {
errorP("failed in cmd[%s]\n", _cmd);
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_burn/optimus_usb_burn.c b/drivers/usb/gadget/v2_burning/v2_usb_burn/optimus_usb_burn.c
index 2b73d32..41391ed 100644
--- a/drivers/usb/gadget/v2_burning/v2_usb_burn/optimus_usb_burn.c
+++ b/drivers/usb/gadget/v2_burning/v2_usb_burn/optimus_usb_burn.c
@@ -1,15 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file optimus_usb_burn.c
- * \brief burning itself from Pheripheral usb host
- *
- * \version 1.0.0
- * \date 2014-9-15
- * \author Sam.Wu <yihui.wu@amlgic.com>
- * Chunyu.Song <chunyu.song@amlogic.com>
- *
- * Copyright (c) 2013 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "../v2_sdc_burn/optimus_sdc_burn_i.h"
#include "../v2_sdc_burn/optimus_led.h"
@@ -54,14 +47,14 @@
int rcode = 0;
const char* sdc_cfg_file = argv[1];
- setenv("usb_update","1");
+ setenv("usb_update","1");
if (argc < 2 ) {
cmd_usage(cmdtp);
return __LINE__;
}
- optimus_work_mode_set(OPTIMUS_WORK_MODE_SDC_UPDATE);
+ optimus_work_mode_set(OPTIMUS_WORK_MODE_UDISK_PRODUCE);
show_logo_to_report_burning();//indicate enter flow of burning! when 'run update'
if (optimus_led_open(LED_TYPE_PWM)) {
DWN_ERR("Fail to open led for burn\n");
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_burn/optimus_usb_update.c b/drivers/usb/gadget/v2_burning/v2_usb_burn/optimus_usb_update.c
index 0866374..4f44d1e 100644
--- a/drivers/usb/gadget/v2_burning/v2_usb_burn/optimus_usb_update.c
+++ b/drivers/usb/gadget/v2_burning/v2_usb_burn/optimus_usb_update.c
@@ -1,16 +1,8 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * \file optimus_usb_update.c
- * \brief usb_update command to burn a parition image from usb host
- * this update based on the burner is latest: (uboot for burnner can run from peripherals such as sdmmc/usb)
- *
- * \version 1.0.0
- * \date 2014-9-15
- * \author Chunyu.Song<chunyu.song@amlogic.com>
- * Sam.Wu <yihui.wu@amlogic.com>
- *
- * Copyright (c) 2013 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "../v2_sdc_burn/optimus_sdc_burn_i.h"
typedef int __hFileHdl;
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd.c b/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd.c
index aae619c..29db78f 100644
--- a/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd.c
+++ b/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd.c
@@ -1,13 +1,10 @@
-/* dwc controller pcd drivers */
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2010 Amlogic, Inc
- *
- * Victor Wan, victor.wan@amlogic.com,
- * 2010-03-24 @ Shanghai
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "../v2_burning_i.h"
-#include "platform.h"
+#include "../../platform.h"
#include "usb_ch9.h"
#include "dwc_pcd.h"
#include "dwc_pcd_irq.h"
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd.h b/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd.h
index bc874e3..1e33487 100644
--- a/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd.h
+++ b/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd.h
@@ -1,10 +1,6 @@
-/* dwc controller pcd drivers header */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * (C) Copyright 2010 Amlogic, Inc
- *
- * Victor Wan, victor.wan@amlogic.com,
- * 2010-03-24 @ Shanghai
- * From synopsys head file
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __DWC_PCD_H__
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd_irq.c b/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd_irq.c
index 5051b68..a651f19 100644
--- a/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd_irq.c
+++ b/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd_irq.c
@@ -1,12 +1,9 @@
-/* dwc controller pcd interrupt drivers */
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2010 Amlogic, Inc
- *
- * Victor Wan, victor.wan@amlogic.com,
- * 2010-03-30 @ Shanghai
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
-#include "platform.h"
+
+#include "../../platform.h"
#include "usb_ch9.h"
#include "dwc_pcd.h"
#include "dwc_pcd_irq.h"
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd_irq.h b/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd_irq.h
index 48cc165..b9773e2 100644
--- a/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd_irq.h
+++ b/drivers/usb/gadget/v2_burning/v2_usb_tool/dwc_pcd_irq.h
@@ -1,11 +1,8 @@
-/* dwc driver irq header */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * (C) Copyright 2010 Amlogic, Inc
- *
- * Victor Wan, victor.wan@amlogic.com,
- * 2010-03-30 @ Shanghai
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#ifndef __DWC_PCD_IRQ_H__
#define __DWC_PCD_IRQ_H__
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_tool/optimus_core.c b/drivers/usb/gadget/v2_burning/v2_usb_tool/optimus_core.c
index 1522f5c..464162a 100644
--- a/drivers/usb/gadget/v2_burning/v2_usb_tool/optimus_core.c
+++ b/drivers/usb/gadget/v2_burning/v2_usb_tool/optimus_core.c
@@ -1,11 +1,17 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include <common.h>
#include <command.h>
-#include "platform.h"
+#include "../../platform.h"
#include "usb_pcd.h"
#include "usb_pcd.c"
-#include "platform.c"
+//#include "../../platform.c"
+
#include "dwc_pcd.c"
#include "dwc_pcd_irq.c"
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_tool/optimus_transform.c b/drivers/usb/gadget/v2_burning/v2_usb_tool/optimus_transform.c
index a410803..ab8d974 100644
--- a/drivers/usb/gadget/v2_burning/v2_usb_tool/optimus_transform.c
+++ b/drivers/usb/gadget/v2_burning/v2_usb_tool/optimus_transform.c
@@ -1,8 +1,13 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#include "../v2_burning_i.h"
#include "usb_pcd.h"
-#include "platform.h"
+#include "../../platform.h"
//#include <partition_table.h>
-#include <asm/arch/cpu_id.h>
+#include <amlogic/cpu_id.h>
#define MYDBG(fmt ...) printf("OPT]"fmt)
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.c b/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.c
deleted file mode 100644
index a415124..0000000
--- a/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.c
+++ /dev/null
@@ -1,658 +0,0 @@
-/* platform dirver header */
-/*
- * (C) Copyright 2010 Amlogic, Inc
- *
- * Victor Wan, victor.wan@amlogic.com,
- * 2010-03-24 @ Shanghai
- *
- */
-#include "platform.h"
-#include <asm/arch/secure_apb.h>
-#include <asm/arch/cpu_id.h>
-
-/*CONFIG_AML_MESON_8 include m8, m8baby, m8m2, etc... defined in cpu.h*/
-#if !(defined(CONFIG_USB_XHCI_HCD) || defined(CONFIG_USB_DWC_OTG_294))
-#error "platform is not GX !!"
-#endif//#if
-
-
-#if (defined CONFIG_USB_XHCI_HCD)
-#if (defined AML_TXLX_USB)
-#define PREI_USB_PHY_2_REG_BASE 0xffe09020
-#define PREI_USB_PHY_3_REG_BASE 0xffe09080
-#else
-#define PREI_USB_PHY_2_REG_BASE 0xd0078020
-#define PREI_USB_PHY_3_REG_BASE 0xd0078080
-#endif
-
-#if (defined CONFIG_USB_DEVICE_V2)
-typedef struct u2p_aml_regs {
- volatile uint32_t u2p_r0;
- volatile uint32_t u2p_r1;
-} u2p_aml_regs_t;
-
-typedef union u2p_r0 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned host_device:1;
- unsigned power_ok:1;
- unsigned hast_mode:1;
- unsigned POR:1;
- unsigned IDPULLUP0:1;
- unsigned DRVVBUS0:1;
- unsigned reserved:26;
- } b;
-} u2p_r0_t;
-
-typedef union u2p_r1 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned phy_rdy:1;
- unsigned IDDIG0:1;
- unsigned OTGSESSVLD0:1;
- unsigned VBUSVALID0:1;
- unsigned reserved:28;
- } b;
-} u2p_r1_t;
-
-typedef struct usb_aml_regs {
- volatile uint32_t usb_r0;
- volatile uint32_t usb_r1;
- volatile uint32_t usb_r2;
- volatile uint32_t usb_r3;
- volatile uint32_t usb_r4;
- volatile uint32_t usb_r5;
-} usb_aml_regs_t;
-
-typedef union usb_r0 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned reserved:17;
- unsigned p30_lane0_tx2rx_loopback:1;
- unsigned p30_lane0_ext_pclk_reg:1;
- unsigned p30_pcs_rx_los_mask_val:10;
- unsigned u2d_ss_scaledown_mode:2;
- unsigned u2d_act:1;
- } b;
-} usb_r0_t;
-
-typedef union usb_r1 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned u3h_bigendian_gs:1;
- unsigned u3h_pme_en:1;
- unsigned u3h_hub_port_overcurrent:3;
- unsigned reserved_1:2;
- unsigned u3h_hub_port_perm_attach:3;
- unsigned reserved_2:2;
- unsigned u3h_host_u2_port_disable:2;
- unsigned reserved_3:2;
- unsigned u3h_host_u3_port_disable:1;
- unsigned u3h_host_port_power_control_present:1;
- unsigned u3h_host_msi_enable:1;
- unsigned u3h_fladj_30mhz_reg:6;
- unsigned p30_pcs_tx_swing_full:7;
- } b;
-} usb_r1_t;
-
-typedef union usb_r2 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned reserved:20;
- unsigned p30_pcs_tx_deemph_3p5db:6;
- unsigned p30_pcs_tx_deemph_6db:6;
- } b;
-} usb_r2_t;
-
-typedef union usb_r3 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned p30_ssc_en:1;
- unsigned p30_ssc_range:3;
- unsigned p30_ssc_ref_clk_sel:9;
- unsigned p30_ref_ssp_en:1;
- unsigned reserved:18;
- } b;
-} usb_r3_t;
-
-typedef union usb_r4 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned p21_PORTRESET0:1;
- unsigned p21_SLEEPM0:1;
- unsigned mem_pd:2;
- unsigned p21_only:1;
- unsigned reserved:27;
- } b;
-} usb_r4_t;
-
-typedef union usb_r5 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned iddig_sync:1;
- unsigned iddig_reg:1;
- unsigned iddig_cfg:2;
- unsigned iddig_en0:1;
- unsigned iddig_en1:1;
- unsigned iddig_curr:1;
- unsigned usb_iddig_irq:1;
- unsigned iddig_th:8;
- unsigned iddig_cnt:8;
- unsigned reserved:8;
- } b;
-} usb_r5_t;
-
-#define USB_REG_B 0xFF63A000
-#define PLL_REG32_16 (0xFF63A000 + 0x40)
-#define PLL_REG32_17 (0xFF63A000 + 0x44)
-#define PLL_REG32_18 (0xFF63A000 + 0x48)
-#define USB_PHY2_ENABLE 0x10000000
-#define USB_PHY2_RESET 0x20000000
-
-#define USB2_PHY_PLL_OFFSET_c (0x34)
-
-#if !defined(CONFIG_USB_AMLOGIC_PHY_V2) && !defined(USE_FULL_SPEED)
-static int b_platform_usb_check_rev (void)
-{
- int rev_flag = 0;
-
- cpu_id_t cpu_id = get_cpu_id();
-
- if (cpu_id.family_id == MESON_CPU_MAJOR_ID_G12B) {
- if (cpu_id.chip_rev == 0xb)
- rev_flag = 0xb;
- else
- rev_flag = 0;
- } else if (cpu_id.family_id == MESON_CPU_MAJOR_ID_SM1){
- rev_flag = MESON_CPU_MAJOR_ID_SM1;
- }
-
- return rev_flag;
-}
-#endif
-
-static void set_pll_Calibration_default(uint32_t volatile *phy2_pll_base)
-{
- u32 tmp;
-
- tmp = (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x8));
- tmp &= 0xfff;
- tmp |= (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10));
- (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10))
- = tmp;
-}
-
-static void set_usb_phy21_pll(uint32_t volatile *phy2_pll_base)
-{
- (*(volatile uint32_t *)(unsigned long)(PLL_REG32_16))
- = (USB_PHY2_PLL_PARAMETER_1 | USB_PHY2_RESET | USB_PHY2_ENABLE);
- (*(volatile uint32_t *)(unsigned long)(PLL_REG32_17)) =
- USB_PHY2_PLL_PARAMETER_2;
- (*(volatile uint32_t *)(unsigned long)(PLL_REG32_18)) =
- USB_PHY2_PLL_PARAMETER_3;
- udelay(100);
- (*(volatile uint32_t *)(unsigned long)(PLL_REG32_16))
- = (((USB_PHY2_PLL_PARAMETER_1) | (USB_PHY2_ENABLE))
- & (~(USB_PHY2_RESET)));
-
- (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0xC))
- = USB2_PHY_PLL_OFFSET_c;
- if (b_platform_usb_check_rev() == MESON_CPU_MAJOR_ID_SM1) {
- (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50))
- = 0xfe18;
- (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x54))
- = 0x2a;
- set_pll_Calibration_default(phy2_pll_base);
- } else {
- (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x10))
- = USB_G12x_PHY_PLL_SETTING_2;
- (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x50))
- = USB_G12x_PHY_PLL_SETTING_1;
- (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x38))
- = 0x0;
- }
-
- (*(volatile uint32_t *)(unsigned long)((unsigned long)phy2_pll_base + 0x34))
- = USB_G12x_PHY_PLL_SETTING_3;
-}
-
-#ifdef CONFIG_USB_DEVICE_V2
-
-void set_usb_phy21_tuning_update(void)
-{
-#if !defined(CONFIG_USB_AMLOGIC_PHY_V2) && !defined(USE_FULL_SPEED)
- unsigned long phy_reg_base = USB_REG_B;
-
- if (b_platform_usb_check_rev())
- return;
-
- (*(volatile uint32_t *)(phy_reg_base + 0x10)) = USB_G12x_PHY_PLL_SETTING_2;
- (*(volatile uint32_t *)(phy_reg_base + 0x50)) = USB_G12x_PHY_PLL_SETTING_1;
- (*(volatile uint32_t *)(phy_reg_base + 0x38)) = USB_G12x_PHY_PLL_SETTING_5;
- (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB_G12x_PHY_PLL_SETTING_3;
-#endif
-}
-
-void set_usb_phy21_tuning_update_reset(void)
-{
-#if !defined(CONFIG_USB_AMLOGIC_PHY_V2) && !defined(USE_FULL_SPEED)
- unsigned long phy_reg_base = USB_REG_B;
-
- if (b_platform_usb_check_rev())
- return;
- (*(volatile uint32_t *)(phy_reg_base + 0x38)) = 0x0;
- (*(volatile uint32_t *)(phy_reg_base + 0x34)) = USB_G12x_PHY_PLL_SETTING_3;
-#endif
-}
-
-#endif
-
-#if 0
-void usb_phy21_pll_disable(void)
-{
- (*(volatile uint32_t *)(unsigned long)PLL_REG32_16)
- = ((USB_PHY2_PLL_PARAMETER_1 | USB_PHY2_RESET)
- & (~(USB_PHY2_ENABLE)));
-}
-#endif
-
-#if (defined AML_TXLX_USB)
-#define USB_RESET1 (volatile unsigned long *)0xffd01008
-#else
-#define USB_RESET1 (volatile unsigned long *)0xc1104408
-#endif
-
-void set_usb_phy_config(int cfg)
-{
- u2p_r0_t dev_u2p_r0;
- u2p_r1_t dev_u2p_r1;
-
- usb_r0_t dev_usb_r0;
- usb_r4_t dev_usb_r4;
-
- u2p_aml_regs_t * u2p_aml_regs = (u2p_aml_regs_t * )PREI_USB_PHY_2_REG_BASE;
- usb_aml_regs_t *usb_aml_regs = (usb_aml_regs_t * )PREI_USB_PHY_3_REG_BASE;
- int cnt, val;
-
- if (b_platform_usb_check_rev() == MESON_CPU_MAJOR_ID_SM1) {
- val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_SLEEP0;
- *P_AO_RTI_GEN_PWR_SLEEP0 = val & (~(0x1<<17));
- val = *(volatile uint32_t *)P_AO_RTI_GEN_PWR_ISO0;
- *P_AO_RTI_GEN_PWR_ISO0 = val & (~(0x1<<17));
- val = *(volatile uint32_t *)HHI_MEM_PD_REG0;
- *P_HHI_MEM_PD_REG0 = val & (~(0x3<<30));
- }
-#ifdef CONFIG_USB_DEVICE_V2
- if ((*(volatile uint32_t *)(USB_REG_B + 0x38)) != 0) {
- set_usb_phy21_tuning_update_reset();
- mdelay(150);
- }
-#endif
- //step 1: usb controller reset
- *USB_RESET1 |= (1<<2);
-
- // step 3: enable usb INT internal USB
- dev_usb_r0.d32 = usb_aml_regs->usb_r0;
- dev_usb_r0.b.u2d_ss_scaledown_mode = 0;
- dev_usb_r0.b.u2d_act = 1;
- usb_aml_regs->usb_r0 = dev_usb_r0.d32;
-
- // step 4: disable usb phy sleep
- dev_usb_r4.d32 = usb_aml_regs->usb_r4;
- dev_usb_r4.b.p21_SLEEPM0 = 1;
- usb_aml_regs->usb_r4 = dev_usb_r4.d32;
-
- // step 5: config phy21 device mode
- dev_u2p_r0.d32 = u2p_aml_regs->u2p_r0;
- dev_u2p_r0.b.host_device= 0;
- dev_u2p_r0.b.POR= 0;
- u2p_aml_regs->u2p_r0 = dev_u2p_r0.d32;
-
- mdelay(10);
- //step 6: phy21 reset
- *USB_RESET1 |= (1<<17);
-
- mdelay(20);
- // step 6: wait for phy ready
- dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
- cnt = 0;
- while ((dev_u2p_r1.d32 & 0x00000001) != 1) {
- dev_u2p_r1.d32 = u2p_aml_regs->u2p_r1;
- if (cnt > 200)
- break;
- else {
- cnt++;
- udelay(5);
- }
- }
-
- set_usb_phy21_pll((uint32_t volatile *)USB_REG_B);
-
- mdelay(20);
- //--------------------------------------------------
-
- // ------------- usb phy21 initinal end ----------
-
- //--------------------------------------------------
-
-}
-
-#else
-typedef struct u2p_aml_regs {
- volatile uint32_t u2p_r0;
- volatile uint32_t u2p_r1;
- volatile uint32_t u2p_r2;
-} u2p_aml_regs_t;
-
-typedef union u2p_r0 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned bypass_sel:1; // 0
- unsigned bypass_dm_en:1; // 1
- unsigned bypass_dp_en:1; // 2
- unsigned txbitstuffenh:1;// 3
- unsigned txbitstuffen:1; // 4
- unsigned dmpulldown:1; // 5
- unsigned dppulldown:1; // 6
- unsigned vbusvldextsel:1;// 7
- unsigned vbusvldext:1; // 8
- unsigned adp_prb_en:1; // 9
- unsigned adp_dischrg:1; // 10
- unsigned adp_chrg:1; // 11
- unsigned drvvbus:1; // 12
- unsigned idpullup:1; // 13
- unsigned loopbackenb:1; // 14
- unsigned otgdisable:1; // 15
- unsigned commononn:1; // 16
- unsigned fsel:3; // 17
- unsigned refclksel:2; // 20
- unsigned por:1; // 22
- unsigned vatestenb:2; // 23
- unsigned set_iddq:1; // 25
- unsigned ate_reset:1; // 26
- unsigned fsv_minus:1; // 27
- unsigned fsv_plus:1; // 28
- unsigned bypass_dm_data:1; // 29
- unsigned bypass_dp_data:1; // 30
- unsigned not_used:1;
- } b;
-} u2p_r0_t;
-
-typedef struct usb_aml_regs {
- volatile uint32_t usb_r0;
- volatile uint32_t usb_r1;
- volatile uint32_t usb_r2;
- volatile uint32_t usb_r3;
- volatile uint32_t usb_r4;
- volatile uint32_t usb_r5;
- volatile uint32_t usb_r6;
-} usb_aml_regs_t;
-
-typedef union usb_r0 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned p30_fsel:6; // 0
- unsigned p30_phy_reset:1; // 6
- unsigned p30_test_powerdown_hsp:1; // 7
- unsigned p30_test_powerdown_ssp:1; // 8
- unsigned p30_acjt_level:5; // 9
- unsigned p30_tx_vboost_lvl:3; // 14
- unsigned p30_lane0_tx2rx_loopbk:1; // 17
- unsigned p30_lane0_ext_pclk_req:1; // 18
- unsigned p30_pcs_rx_los_mask_val:10; // 19
- unsigned u2d_ss_scaledown_mode:2; // 29
- unsigned u2d_act:1; // 31
- } b;
-} usb_r0_t;
-
-typedef union usb_r4 {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned p21_PORTRESET0:1; // 0
- unsigned p21_SLEEPM0:1; // 1
- unsigned mem_pd:2;
- unsigned reserved4:28; // 31
- } b;
-} usb_r4_t;
-//#define P_AO_RTC_ALT_CLK_CNTL0 (volatile uint32_t *)(0xc8100000 + (0x25 << 2))
-//#define P_AO_RTI_PWR_CNTL_REG0 (volatile uint32_t *)(0xc8100000 + (0x04 << 2))
-
-void set_usb_phy_config(int cfg)
-{
- const int time_dly = 500;
- u2p_aml_regs_t * u2p_aml_regs = (u2p_aml_regs_t * )PREI_USB_PHY_2_REG_BASE;
- usb_aml_regs_t * usb_aml_regs = (usb_aml_regs_t * )PREI_USB_PHY_3_REG_BASE;
-
- u2p_r0_t u2p_r0;
- usb_r0_t usb_r0;
- usb_r4_t usb_r4;
- //if (!IS_CLK_GATE_ON(USB0)) {
- // SET_CBUS_REG_MASK(GCLK_REG_USB0, GCLK_MASK_USB0);
- //}
- /*printf("%s %d\n", __func__, __LINE__);*/
- cfg = cfg;//avoid compiler warning
- *P_RESET1_REGISTER = (1<<2);//usb reset
- //writel((1 << 2),P_RESET1_REGISTER); //usb reset
- //udelay(time_dly);//by Sam: delay after reset
-
- *P_AO_RTC_ALT_CLK_CNTL0 |= (1<<31)|(1<<30);
- *P_AO_RTI_PWR_CNTL_REG0 |= (4<<10);
-
- u2p_r0.d32 = u2p_aml_regs->u2p_r0;
-#if (defined CONFIG_AML_MESON_GXTVBB)
- u2p_r0.b.fsel = 5;
-
-#elif (defined CONFIG_AML_MESON_GXL)
- u2p_r0.b.fsel = 2;
-#endif
- u2p_r0.b.por = 1;
- u2p_r0.b.dppulldown = 0;
- u2p_r0.b.dmpulldown = 0;
- u2p_aml_regs->u2p_r0 = u2p_r0.d32;
-
- u2p_r0.d32 = u2p_aml_regs->u2p_r0;
- u2p_r0.b.por = 0;
- u2p_aml_regs->u2p_r0 = u2p_r0.d32;
-
- usb_r0.d32 = usb_aml_regs->usb_r0;
- usb_r0.b.u2d_act = 1;
- usb_aml_regs->usb_r0 = usb_r0.d32;
-
- usb_r4.d32 = usb_aml_regs->usb_r4;
- usb_r4.b.p21_SLEEPM0 = 1;
- usb_aml_regs->usb_r4 = usb_r4.d32;
-
- udelay(time_dly);
- return;
-}
-#endif
-
-//sleep sometime before and after disconnect,
-// to let usb_burning_tool.exe detect both fast plug-out and plug-in
-void close_usb_phy_clock(int cfg)
-{
- cfg = cfg;//avoid compiler warning
-
- run_command("sleep 1", 0);//improve pc compatibility!!
- dwc_otg_pullup(0);//disconnect
- __udelay(20);
- /*dwc_otg_power_off_phy();*///Don't call this as it may cause pull-down failed!!!!
- run_command("sleep 1", 0);
-
- return;
-}
-#endif
-
-#if (defined CONFIG_USB_DWC_OTG_294)
-
-/*
- cfg = 0 : EXT clock
- cfg = 1 : INT clock
- */
-
-#if 1
-#define PREI_USB_PHY_A_REG_BASE 0xC0000000 //0x2100
-#define PREI_USB_PHY_B_REG_BASE 0xC1108420 //0X2108
-#else
-#define PREI_USB_PHY_A_REG_BASE P_USB_ADDR0
-#define PREI_USB_PHY_B_REG_BASE P_USB_ADDR1
-#endif//#if 0
-
-#ifdef __USE_PORT_B
-#define PREI_USB_PHY_REG_BASE PREI_USB_PHY_B_REG_BASE
-#else
-#define PREI_USB_PHY_REG_BASE PREI_USB_PHY_A_REG_BASE
-#endif
-//#define P_RESET1_REGISTER (volatile unsigned long *)0xc1104408
-#define P_RESET1_REGISTER_USB (volatile unsigned long *)0xc1104408
-
-#define USB_CLK_SEL_XTAL 0
-#define USB_CLK_SEL_XTAL_DIV_2 1
-#define USB_CLK_SEL_DDR_PLL 2
-#define USB_CLK_SEL_MPLL_OUT0 3
-#define USB_CLK_SEL_MPLL_OUT1 4
-#define USB_CLK_SEL_MPLL_OUT2 5
-#define USB_CLK_SEL_FCLK_DIV2 6
-#define USB_CLK_SEL_FCLK_DIV3 7
-
-typedef struct usb_aml_regs {
- volatile uint32_t config;
- volatile uint32_t ctrl;
- volatile uint32_t endp_intr;
- volatile uint32_t adp_bc;
- volatile uint32_t dbg_uart;
- volatile uint32_t test;
- volatile uint32_t tune;
-} usb_aml_regs_t;
-
-typedef union usb_config_data {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned clk_en :1;
- unsigned clk_sel :3;
- unsigned clk_div :7;
- unsigned reserved0 :1;
- unsigned clk_32k_alt_sel:1;
- unsigned reserved1 :15;
- unsigned test_trig :1;
- } b;
-} usb_config_data_t;
-
-typedef union usb_ctrl_data {
- /** raw register data */
- uint32_t d32;
- /** register bits */
- struct {
- unsigned soft_prst:1;
- unsigned soft_hreset:1;
- unsigned ss_scaledown_mode:2;
- unsigned clk_det_rst:1;
- unsigned intr_sel:1;
- unsigned reserved:2;
- unsigned clk_detected:1;
- unsigned sof_sent_rcvd_tgl:1;
- unsigned sof_toggle_out:1;
- unsigned not_used:4;
- unsigned por:1;
- unsigned sleepm:1;
- unsigned txbitstuffennh:1;
- unsigned txbitstuffenn:1;
- unsigned commononn:1;
- unsigned refclksel:2;
- unsigned fsel:3;
- unsigned portreset:1;
- unsigned thread_id:6;
- } b;
-} usb_ctrl_data_t;
-
-void set_usb_phy_config(int cfg)
-{
-
- const int time_dly = 5000;
- usb_aml_regs_t * usb_aml_regs = (usb_aml_regs_t * )PREI_USB_PHY_REG_BASE;
- usb_config_data_t config;
- usb_ctrl_data_t control;
-
- /*CLK_GATE_ON(USB0);*/
- //if(!IS_CLK_GATE_ON(USB0)){
- // SET_CBUS_REG_MASK(GCLK_REG_USB0, GCLK_MASK_USB0);
- //}
- /*printf("%s %d\n", __func__, __LINE__);*/
- cfg = cfg;//avoid compiler warning
- /**P_RESET1_REGISTER = (1<<2);//usb reset*/
- *P_RESET1_REGISTER_USB = (1<<2);//usb reset
- udelay(time_dly);//by Sam: delay after reset
-
- config.d32 = usb_aml_regs->config;
-
-// config.b.clk_sel = 0;
-// config.b.clk_div = 1;
-// config.b.clk_32k_alt_sel = 1;
- usb_aml_regs->config = config.d32;
-
- control.d32 = usb_aml_regs->ctrl;
- control.b.fsel = 5;
- control.b.por = 1;
- usb_aml_regs->ctrl = control.d32;
- udelay(time_dly);
-
- control.b.por = 0;
- usb_aml_regs->ctrl = control.d32;
- udelay(time_dly);//by Sam: delay 0.5s to wait usb clam down
-
- control.d32 = usb_aml_regs->ctrl;
- if (!control.b.clk_detected) {
- printf("Error, usb phy clock not detected!\n");
- }
-
- return;
-}
-
-#if 0
-int chip_watchdog(void)
-{
- watchdog_clear();
- return 0;
-};
-#endif
-
-//sleep sometime before and after disconnect,
-// to let usb_burning_tool.exe detect both fast plug-out and plug-in
-void close_usb_phy_clock(int cfg)
-{
- cfg = cfg;//avoid compiler warning
-
- run_command("sleep 1", 0);//sleep sometime to improve pc compatibility!!
- dwc_otg_pullup(0);//disconnect
- __udelay(20);
- /*dwc_otg_power_off_phy();*///Don't call this as it may cause pull-down failed!!!!
- run_command("sleep 1", 0);//sleep sometime to improve pc compatibility!!
-
- return;
-}
-#endif
-
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.h b/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.h
deleted file mode 100644
index 9b5b3ab..0000000
--- a/drivers/usb/gadget/v2_burning/v2_usb_tool/platform.h
+++ /dev/null
@@ -1,139 +0,0 @@
-/* platform header */
-/*
- * (C) Copyright 2010 Amlogic, Inc
- *
- * Victor Wan, victor.wan@amlogic.com,
- * 2010-03-24 @ Shanghai
- *
- */
-
-#ifndef __PLATFORM_H__
-#define __PLATFORM_H__
-
-#include <asm/arch/register.h>
-
-/* A3,CS2,M3 chip, PORT_A is OTG, work as ROM Boot port */
-#ifdef __USE_PORT_B
-#define PORT_REG_OFFSET 0x80000
-#else
-#define PORT_REG_OFFSET 0
-#endif
-
-#if (defined AML_TXLX_USB)
-#if ((defined CONFIG_USB_XHCI_HCD))
-#define DWC_REG_BASE 0xff400000
-#else
-#define DWC_REG_BASE (0xff500000 + PORT_REG_OFFSET)
-#endif
-#else
-#if ((defined CONFIG_USB_XHCI_HCD))
-#define DWC_REG_BASE 0xc9100000
-#else
-#define DWC_REG_BASE (0xC9000000 + PORT_REG_OFFSET)
-#endif
-#endif
-
-#define PREI_USB_PHY_A_POR (1 << 0)
-#define PREI_USB_PHY_B_POR (1 << 1)
-#define PREI_USB_PHY_CLK_SEL (7 << 5) // changed from A1H
-#define PREI_USB_PHY_CLK_GATE (1 << 8)
-#define PREI_USB_PHY_B_AHB_RSET (1 << 11)
-#define PREI_USB_PHY_B_CLK_RSET (1 << 12)
-#define PREI_USB_PHY_B_PLL_RSET (1 << 13)
-#define PREI_USB_PHY_A_AHB_RSET (1 << 17)
-#define PREI_USB_PHY_A_CLK_RSET (1 << 18)
-#define PREI_USB_PHY_A_PLL_RSET (1 << 19)
-#define PREI_USB_PHY_A_DRV_VBUS (1 << 20)
-#define PREI_USB_PHY_B_DRV_VBUS (1 << 21)
-#define PREI_USB_PHY_B_CLK_DETECT (1 << 22)
-#define PREI_USB_PHY_CLK_DIV (0x7f << 24)
-#define PREI_USB_PHY_A_CLK_DETECT (1 << 31)
-
-#define PREI_USB_PHY_A_REG3_IDDIG_OVR (1 << 23)
-#define PREI_USB_PHY_A_REG3_IDDIG_VAL (1 << 24)
-
-#define PREI_USB_PHY_B_REG4_IDDIG_OVR (1 << 23)
-#define PREI_USB_PHY_B_REG4_IDDIG_VAL (1 << 24)
-
-#define IREG_TIMER_E_COUNT 0x2655
-
-
-#define flush_cpu_cache()
-
-
-#define dwc_write_reg32(x, v) (*(volatile uint32_t *)(unsigned long)(x + DWC_REG_BASE))=v
-#define dwc_read_reg32(x) (*(volatile uint32_t*)(unsigned long)(x + DWC_REG_BASE))
-// void dwc_modify_reg32( volatile uint32_t *_reg, const uint32_t _clear_mask, const uint32_t _set_mask)
-#define dwc_modify_reg32(x, c, s) (*(volatile uint32_t *)(x + DWC_REG_BASE))=( ((dwc_read_reg32(x)) & (~c)) | (s))
-
-#define get_unaligned(ptr) ( ((unsigned long)ptr & 3) ? \
- (((__u8 *)ptr)[0] | (((__u8 *)ptr)[1]<<8) | (((__u8 *)ptr)[2]<<16) | (((__u8 *)ptr)[3]<<24)) : \
- (*(uint32_t*)ptr) )
-#define get_unaligned_16(ptr) (((__u8 *)ptr)[0] | (((__u8 *)ptr)[1]<<8))
-#define get_unaligned_32(ptr) (((__u8 *)ptr)[0] | (((__u8 *)ptr)[1]<<8) | (((__u8 *)ptr)[2]<<16) | (((__u8 *)ptr)[3]<<24))
-
-#if 0
-#define __constant_cpu_to_le16(x) (x)
-#define __constant_cpu_to_le32(x) (x)
-#define cpu_to_le16(x) (x)
-#define cpu_to_le32(x) (x)
-#define le16_to_cpu(x) (x)
-#define le32_to_cpu(x) (x)
-
-#ifndef max
-#define max(a, b) (((a) > (b))? (a): (b))
-#endif
-#ifndef min
-#define min(a, b) (((a) < (b))? (a): (b))
-#endif
-
-#endif//#if 0
-
-#define EXT_CLOCK 0
-#define INT_CLOCK 1
-
-
-// 32 bit TimerE, 1us
-#define USB_ROM_CONN_TIMEOUT 5*1000*1000 //us (5s timeout,)
-
-
-/* Meet with spec */
-#define USB_ROM_VER_MAJOR 0
-#define USB_ROM_STAGE_MAJOR 0
-#define USB_ROM_STAGE_MINOR 16 // IPL = 0, SPL = 8, TPL = 16
-
-#ifdef CONFIG_M6
-#define USB_ROM_VER_MINOR 8 // SPEC Version
-#else
-#define USB_ROM_VER_MINOR 7 // SPEC Version
-#endif
-
-#if 1
-#define PRINTF(x...) do{}while(0)
-#else
-#define PRINTF(x...) printf(x)
-#endif
-
-#define ERR(x...) printf(x)
-#define DBG(x...) PRINTF(x)
-#define USB_ERR(x...) printf("USBErr:%d", __LINE__),printf(x)
-#define USB_DBG(x...) PRINTF(x)
-
-
-void set_usb_phy_config(int cfg);
-#ifdef CONFIG_USB_DEVICE_V2
-void set_usb_phy21_tuning_update(void);
-#endif
-void close_usb_phy_clock(int cfg);
-void usb_parameter_init(int timeout);
-int chip_utimer_set(int val);
-int chip_watchdog(void);
-#define udelay __udelay
-#define wait_ms(a) udelay(a*1000);
-int update_utime(void);
-int get_utime(void);
-//int chip_watchdog(void);
-//#define usb_memcpy(dst,src,len) rom_memcpy((unsigned)src,(unsigned)dst,(unsigned)len)
-//#define usb_memcpy_32bits(dst,src,len) rom_memcpy((unsigned)src,(unsigned)dst,(unsigned)len)
-
-#endif
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_tool/usb_ch9.h b/drivers/usb/gadget/v2_burning/v2_usb_tool/usb_ch9.h
index 9b52b67..f36a972 100644
--- a/drivers/usb/gadget/v2_burning/v2_usb_tool/usb_ch9.h
+++ b/drivers/usb/gadget/v2_burning/v2_usb_tool/usb_ch9.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __LINUX_USB_CH9_H
#define __LINUX_USB_CH9_H
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_tool/usb_pcd.c b/drivers/usb/gadget/v2_burning/v2_usb_tool/usb_pcd.c
index 65545d3..2b68733 100644
--- a/drivers/usb/gadget/v2_burning/v2_usb_tool/usb_pcd.c
+++ b/drivers/usb/gadget/v2_burning/v2_usb_tool/usb_pcd.c
@@ -1,13 +1,10 @@
-/* usb pcd driver */
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * (C) Copyright 2010 Amlogic, Inc
- *
- * Victor Wan, victor.wan@amlogic.com,
- * 2010-03-24 @ Shanghai
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#include "../v2_burning_i.h"
-#include "platform.h"
+#include "../../platform.h"
#include "usb_ch9.h"
#include "dwc_pcd.h"
#include "dwc_pcd_irq.h"
@@ -226,7 +223,7 @@
static unsigned int _sofintr_not_occur;
#if (defined CONFIG_USB_DEVICE_V2)
static unsigned int _sofintr;
-unsigned curTime_sof;
+extern unsigned curTime_sof;
#endif
void usb_parameter_init(int time_out)
diff --git a/drivers/usb/gadget/v2_burning/v2_usb_tool/usb_pcd.h b/drivers/usb/gadget/v2_burning/v2_usb_tool/usb_pcd.h
index 12d0afe..8956f3e 100644
--- a/drivers/usb/gadget/v2_burning/v2_usb_tool/usb_pcd.h
+++ b/drivers/usb/gadget/v2_burning/v2_usb_tool/usb_pcd.h
@@ -1,11 +1,8 @@
-/* usb pcd driver header */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * (C) Copyright 2010 Amlogic, Inc
- *
- * Victor Wan, victor.wan@amlogic.com,
- * 2010-03-24 @ Shanghai
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#ifndef __USB_PCD_H__
#define __USB_PCD_H__
#include <asm/types.h>
diff --git a/drivers/usb/gadget/v3_burning/Kconfig b/drivers/usb/gadget/v3_burning/Kconfig
new file mode 100644
index 0000000..a43dd11
--- /dev/null
+++ b/drivers/usb/gadget/v3_burning/Kconfig
@@ -0,0 +1,52 @@
+#
+# AML V3 burning
+#
+menuconfig AML_V3_FACTORY_BURN
+ bool "Amlogic V3 burning Support"
+ depends on AML_STORE_WRAPPER
+ ---help---
+ Say Y here if you want to support amlogic V3 factory burning
+
+if AML_V3_FACTORY_BURN
+
+config AML_NO_USB_MODULE
+ bool "bl33 with full usb function"
+ default n
+
+config AML_V3_USB_TOOl
+ bool "DNL USB burning support"
+ select USB_GADGET_DOWNLOAD
+ select FASTBOOT_DWC_PCD #for fastboot/dwc_pcd.o fastboot/dwc_pcd_irq.o
+ depends on USB_GADGET
+ ---help---
+ Say Y here if you want to update firmware by aml DNL tool
+
+config V3_USB_BURN_FULL_SPEED
+ depends on AML_V3_USB_TOOl
+ bool "usb burning driver runing on Full-speed mode"
+ default n
+ ---help---
+ Change Y Only when u testing on usb or FS mode have problem
+
+config V3_KEY_BURNING_SUPPORT
+ depends on UNIFY_KEY_MANAGE
+ bool "support burning unifykey in v3 burning"
+ default y
+ select AML_V2_FACTORY_BURN
+
+config SUPPORT_BACKUP_PART_NORMAL_ERASE
+ bool "support backup part when normal erasing"
+ default n
+
+config BACKUP_PART_NORMAL_ERASE
+ depends on SUPPORT_BACKUP_PART_NORMAL_ERASE
+ string "config backup part name"
+ help
+ This configure define part which need backup to mem before normal erase
+ backup before erasing, and restore it after erasing
+ There is probablity data lost if erasing failed or write failed
+
+
+
+endif #AML_V3_FACTORY_BURN
+
diff --git a/drivers/usb/gadget/v3_burning/Makefile b/drivers/usb/gadget/v3_burning/Makefile
new file mode 100644
index 0000000..eada042
--- /dev/null
+++ b/drivers/usb/gadget/v3_burning/Makefile
@@ -0,0 +1,8 @@
+obj-$(CONFIG_AML_V3_FACTORY_BURN) += aml_v3_burning.o
+obj-$(CONFIG_AML_V3_FACTORY_BURN) += v3_common/
+ifdef CONFIG_AML_V3_FACTORY_BURN
+obj-$(CONFIG_AML_V3_USB_TOOl) += v3_usb_tool/
+obj-$(CONFIG_AML_V3_SDC_BURN) += v3_sdc_burn/
+obj-$(CONFIG_AML_V3_USB_BURN) += v3_usb_burn/
+endif #ifdef CONFIG_AML_V3_FACTORY_BURN
+
diff --git a/drivers/usb/gadget/v3_burning/aml_v3_burning.c b/drivers/usb/gadget/v3_burning/aml_v3_burning.c
new file mode 100644
index 0000000..cd25a04
--- /dev/null
+++ b/drivers/usb/gadget/v3_burning/aml_v3_burning.c
@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "include/v3_tool_def.h"
+#include <mmc.h>
+#include <amlogic/cpu_id.h>
+#ifndef BOOT_DEVICE_USB
+#define BOOT_DEVICE_SD 4
+#define BOOT_DEVICE_USB 5
+#endif// #ifndef BOOT_DEVICE_USB
+extern void serial_initialize(void);
+extern void board_init_mem(void);
+extern int aml_v3_usbburning(unsigned timeout, unsigned pcToolWaitTime);
+
+unsigned _get_romcode_boot_id(void)
+{
+ const cpu_id_t cpuid = get_cpu_id();
+ const int familyId = cpuid.family_id;
+
+ unsigned boot_id = 0;
+#ifdef SYSCTRL_SEC_STATUS_REG2
+ if (MESON_CPU_MAJOR_ID_SC2 <= familyId && MESON_CPU_MAJOR_ID_C2 != familyId) {
+ boot_id = readl(SYSCTRL_SEC_STATUS_REG2);
+ FB_DBG("boot_id 0x%x\n", boot_id);
+ boot_id = (boot_id>>4) & 0xf;
+ }
+ FB_DBG("boot_id 1x%x\n", boot_id);
+#endif// #ifdef SYSCTRL_SEC_STATUS_REG2
+
+#if defined(P_AO_SEC_GP_CFG0)
+ if (MESON_CPU_MAJOR_ID_C2 >= familyId &&
+ MESON_CPU_MAJOR_ID_SC2 != familyId) {
+ FB_DBG("cfg0 0x%08x\n", readl(P_AO_SEC_GP_CFG0));
+ boot_id = readl(P_AO_SEC_GP_CFG0) & 0xf;
+ }
+#endif// #if defined(P_AO_SEC_GP_CFG0)
+
+ return boot_id;
+}
+
+static int is_boot_device_usb(void)
+{
+ return BOOT_DEVICE_USB == _get_romcode_boot_id();
+}
+
+static int is_bl1_usb_protocol_DNL(void)
+{
+#ifdef SYSCTRL_SEC_STATUS_REG1
+ const unsigned cfg9 = readl(SYSCTRL_SEC_STATUS_REG1);
+ FB_DBG("SYSCTRL_SEC_STATUS_REG1 0x%x\n", cfg9);
+ return !(cfg9 & (1U<<12));
+#else
+ const unsigned cfg9 = readl(P_AO_SEC_SD_CFG9);
+ FB_DBG("cfg9 0x%x\n", cfg9);
+ return cfg9 & (1U<<15);
+#endif// #ifdef SYSCTRL_SEC_STATUS_REG1
+}
+
+
+int aml_v3_factory_usb_burning(int flag, bd_t* bis)
+{
+ if (!is_boot_device_usb()) return 1;
+ if (!is_bl1_usb_protocol_DNL()) return 1;
+
+ bis = bis;//avoid compiling warnning
+ if ( !flag ) {
+ serial_initialize();//init for write memory
+#ifdef CONFIG_GENERIC_MMC
+ FB_MSG("MMC init for dnl\n");
+ mmc_initialize(bis);
+#endif
+ set_default_env(NULL, 0);
+ board_init_mem();
+ }
+#ifdef CONFIG_SILENT_CONSOLE
+ /* enable console output */
+ gd->flags &= ~GD_FLG_SILENT;
+#endif
+ //pull down and sleep in bl2-->tpl,
+ //to improve pc compatibility
+ /*f_dwc_otg_pullup(0);*/
+ udelay(2*1000*1000);
+
+ v3tool_work_mode_set(V3TOOL_WORK_MODE_USB_PRODUCE);
+ optimus_clear_ovd_register();//clear OVD register for normal reboot
+ return aml_v3_usbburning(0, 0);
+}
+
diff --git a/drivers/usb/gadget/v3_burning/include/v3_tool_def.h b/drivers/usb/gadget/v3_burning/include/v3_tool_def.h
new file mode 100644
index 0000000..376df77
--- /dev/null
+++ b/drivers/usb/gadget/v3_burning/include/v3_tool_def.h
@@ -0,0 +1,234 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __V3_TOOL_DEF_H__
+#define __V3_TOOL_DEF_H__
+#include <config.h>
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <environment.h>
+#include <asm/string.h>
+#include <asm/byteorder.h>
+#include <cli.h>
+#include <u-boot/sha1.h>
+#include <asm/arch/secure_apb.h>
+#include <asm/arch/io.h>
+#include <asm/arch/bl31_apis.h>
+#include <partition_table.h>
+#include <amlogic/aml_efuse.h>
+#include <amlogic/keyunify.h>
+#include <amlogic/store_wrapper.h>
+
+extern unsigned long get_multi_dt_entry(unsigned long fdt_addr);
+extern void f_dwc_otg_pullup(int is_on);
+
+extern char* fb_response_str;
+#define _ACK fb_response_str
+
+#undef FB_DBG
+#undef FB_ERR
+#undef FB_MSG
+#define FB_ERR(fmt ...) printf("[ERR]%s:L%d:", __func__, __LINE__),printf(fmt)
+#define FB_EXIT(fmt ...) do{FB_ERR(fmt);return -__LINE__;}while(0)
+#define FB_MSG(fmt ...) printf("[MSG]"fmt)
+#define FB_WRN(fmt ...) printf("[WRN]"fmt)
+#define FB_DBG(fmt...) //printf("[DBG]"fmt)
+#define FB_HERE() printf("f(%s)L%d\n", __func__, __LINE__)
+
+#define RESPONSE_LEN (128)
+#define FBS_ERR(buf, fmt ...) do {\
+ snprintf((buf),RESPONSE_LEN - 4, fmt);\
+ printf("[ERR]%sL%d:%s\n", __func__, __LINE__, (buf));\
+}while(0)
+#define FBS_EXIT(buf, fmt ...) do {FBS_ERR(buf, fmt); return -__LINE__;} while(0)
+#define _mymin(a,b) ( (a) > (b) ? (b) : (a) )
+
+unsigned add_sum(const void* pBuf, const unsigned size);//Add-sum used for 64K transfer
+int optimus_erase_bootloader(const char* extBootDev);
+void optimus_clear_ovd_register(void);
+
+//outStr will be null-terminater after format
+int optimus_hex_data_2_ascii_str(const unsigned char* hexData, const unsigned nBytes, char* outStr, const unsigned strSz);
+
+//for prompting step info
+int optimus_progress_init(const unsigned itemSzHigh, const unsigned itemSzLow, const u32 startStep, const u32 endStep);
+int optimus_progress_exit(void);
+int optimus_update_progress(const unsigned thisBurnSz);
+
+enum {
+ V3TOOL_WORK_MODE_USB_UPDATE = (0xefe5),
+ V3TOOL_WORK_MODE_USB_PRODUCE ,
+ V3TOOL_WORK_MODE_SDC_UPDATE ,
+ V3TOOL_WORK_MODE_SDC_PRODUCE ,
+ V3TOOL_WORK_MODE_UDISK_UPDATE,
+ V3TOOL_WORK_MODE_SYS_RECOVERY,
+};
+
+#ifndef CONFIG_DTB_MEM_ADDR
+#define CONFIG_DTB_MEM_ADDR 0x1000
+#endif// #ifndef CONFIG_DTB_MEM_ADDR
+#define V3_DTB_LOAD_ADDR CONFIG_DTB_MEM_ADDR
+
+#define EP_BUFFER_SIZE 4096 //temp buffer for command 'Download'
+#define V3_DOWNLOAD_EP_DATA ( 0x02<<20 ) //CONFIG_DTB_MEM_ADDR + 2M
+#define V3_DOWNLOAD_EP_OUT (V3_DOWNLOAD_EP_DATA)
+#define V3_DOWNLOAD_EP_IN (V3_DOWNLOAD_EP_OUT + EP_BUFFER_SIZE * 2)
+
+#define V3_DOWNLOAD_MEM_BASE (V3_DOWNLOAD_EP_DATA) //CONFIG_DTB_MEM_ADDR + 3M
+#define V3_DOWNLOAD_MEM_SIZE (0X8<<20) //each mwrite size for sparse image
+#define V3_DOWNLOAD_SPARE_SZ (0X8<<10) //8k for sparse spare
+#define V3_DOWNLOAD_VERIFY_INFO (V3_DOWNLOAD_MEM_BASE + V3_DOWNLOAD_MEM_SIZE + V3_DOWNLOAD_SPARE_SZ)//1MB for temp use
+#define V3_DOWNLOAD_VERIFY_INFO_SZ (0x1<<20)//
+
+#define _RAW_IMG_TRANSFER_LEN (128<<10) //each mwrite size for raw image
+#define _UNIFYKEY_MAX_SZ (256<<10)
+
+#define V3_GPT_LOAD_ADDR (CONFIG_DTB_MEM_ADDR + 0x100000) //payload sz not fixed and > 1M, so payload be after
+#define V3_PAYLOAD_LOAD_ADDR (V3_GPT_LOAD_ADDR + 0x100000) //sheader for sc2 nand
+
+enum {
+ V3TOOL_PART_IMG_FMT_RAW = 0xabcd,
+ V3TOOL_PART_IMG_FMT_SPARSE ,
+ V3TOOL_PART_IMG_FMT_UBIFS ,
+};
+
+enum {
+ V3TOOL_MEDIA_TYPE_STORE = 0xefee,
+ V3TOOL_MEDIA_TYPE_MEM ,
+ V3TOOL_MEDIA_TYPE_UNIFYKEY ,
+ V3TOOL_MEDIA_TYPE_MMC ,//1-->emmc, 0-->sdcard
+};
+
+#define V3_PART_NAME_LEN 32
+typedef struct {
+ char partName[V3_PART_NAME_LEN];
+ int mediaType;
+ int64_t imgSzTotal;
+ int64_t partStartOff;//
+}ImgCommonPara;
+
+typedef struct {
+ ImgCommonPara commonInf;
+ int imgFmt;
+ int needVerify;
+
+}ImgDownloadPara;
+
+typedef struct {
+ ImgCommonPara commonInf;
+}ImgUploadPara;
+
+typedef union {
+ ImgCommonPara commonInf;
+ ImgDownloadPara download;
+ ImgUploadPara upload;
+
+}ImgTransPara;
+
+typedef struct {
+ //data size from @fileOffset, END transfer if '0==@dataSize'
+ int dataSize;
+ int64_t fileOffset;
+ char* dataBuf;
+
+}UsbDownInf;
+
+typedef struct {
+ int dataSize;
+ char* dataBuf;
+}UsbUpInf;
+
+typedef union {
+ UsbDownInf downloadInfo;
+ UsbUpInf uploadInfo;
+
+}TransferInfo;
+
+
+int v3tool_buffman_img_init(ImgTransPara* imgInf, const int isDownload);
+int v3tool_buffman_next_download_info(UsbDownInf** downloadInf);
+int v3tool_buffman_data_complete_download(const UsbDownInf* downloadInf);
+int v3tool_buffman_img_verify_sha1sum(unsigned char* vrySum);
+
+int v3tool_buffman_next_upload_info(UsbUpInf** uploadInfo);
+int v3tool_buffman_data_complete_upload(const UsbUpInf* uploadInf);
+
+//for usb
+#ifndef USE_FULL_SPEED
+#define BULK_EP_MPS (512)
+#ifndef CONFIG_USB_GADGET_CRG
+#define DWC_BLK_MAX_LEN (8*BULK_EP_MPS)
+#else
+#define DWC_BLK_MAX_LEN (2*64*BULK_EP_MPS)//one DMA block is 16K, one burst <=64k
+#endif//#ifndef CONFIG_USB_GADGET_CRG
+#else
+#define BULK_EP_MPS (64) //full speed
+#define DWC_BLK_MAX_LEN (6*BULK_EP_MPS)
+#endif// #ifndef USE_FULL_SPEED
+#define DWC_BLK_LEN(leftSz) ((leftSz) >= DWC_BLK_MAX_LEN ? DWC_BLK_MAX_LEN : \
+ (leftSz >= BULK_EP_MPS ? ((leftSz/BULK_EP_MPS)*BULK_EP_MPS): leftSz))
+#define DWC_BLK_NUM(totalTransLen) ( (totalTransLen/DWC_BLK_MAX_LEN) + \
+ ( (totalTransLen & (DWC_BLK_MAX_LEN-1)) >= BULK_EP_MPS ? 1 : 0 ) +\
+ ( (totalTransLen & (BULK_EP_MPS-1)) ? 1 : 0 ) )
+
+int v3tool_storage_init(int toErase, unsigned dtbImgSz, unsigned gptImgSz);
+int v3tool_storage_exit(void);
+int is_v3tool_storage_inited(void);
+int v3tool_is_flash_erased(void);
+
+int bootloader_read(u8* pBuf, unsigned off, unsigned binSz);
+int bootloader_write(u8* dataBuf, unsigned off, unsigned binSz);
+int store_dtb_rw(void* buf, unsigned dtbSz, int rwFlag);
+
+//for key opearations
+//
+#ifdef CONFIG_V3_KEY_BURNING_SUPPORT
+int v2_key_command(const int argc, char * const argv[], char *info);
+
+/*
+ *This fucntion called by mread command, mread= bulkcmd "upload key .." + n * upload transfer, for key n==1
+ *Attentions: return 0 if success, else failed
+ *@keyName: key name in null-terminated c style string
+ *@keyVal: the buffer to read back the key value
+ *@keyValLen: keyVal len is strict when read, i.e, user must know the length of key he/she wnat to read!!
+ *@errInfo: start it with success if burned ok, or format error info into it tell pc burned failed
+ */
+int v2_key_read(const char* keyName, u8* keyVal, const unsigned keyValLen, char* errInfo, unsigned* fmtLen);
+
+/*
+ *This fucntion called by mwrite command, mread= bulkcmd "download key .." + n * download transfer, for key n==1
+ *Attentions: return value is the key length if burn sucess
+ *@keyName: key name in null-terminated c style string
+ *@keyVal: key value download from USB, "the value for sepecial keyName" may need de-encrypt by user code
+ *@keyValLen: the key value downloaded from usb transfer!
+ *@errInfo: start it with success if burned ok, or format error info into it tell pc burned failed
+ */
+unsigned v2_key_burn(const char* keyName, const u8* keyVal, const unsigned keyValLen, char* errInfo);
+#endif//#ifdef CONFIG_V3_KEY_BURNING_SUPPORT
+
+
+int v3tool_media_check_image_size(int64_t imgSz, const char* partName);
+#define V3TOOL_WORK_MODE_NONE 0
+#define V3TOOL_WORK_MODE_USB_UPDATE (0xefe5)
+#define V3TOOL_WORK_MODE_USB_PRODUCE (0xefe6)
+#define V3TOOL_WORK_MODE_SDC_UPDATE (0xefe7)
+#define V3TOOL_WORK_MODE_SDC_PRODUCE (0xefe8)
+#define V3TOOL_WORK_MODE_SYS_RECOVERY (0xefe9)
+int v3tool_work_mode_get(void);
+int v3tool_work_mode_set(int workmode);
+
+void v3tool_media_set_busy(const char* info);
+void v3tool_media_set_free(const char* info);
+int v3tool_media_is_busy(void);
+
+#ifdef SYSCTRL_SEC_STATUS_REG4
+//#define P_AO_SEC_SD_CFG9 SYSCTRL_SEC_STATUS_REG1
+#define P_AO_SEC_GP_CFG0 SYSCTRL_SEC_STATUS_REG4
+#define P_PREG_STICKY_REG2 SYSCTRL_SEC_STICKY_REG2
+#endif// #ifndef P_AO_SEC_SD_CFG0
+
+#endif//#ifndef __V3_TOOL_DEF_H__
+
diff --git a/drivers/usb/gadget/v3_burning/v3_common/Makefile b/drivers/usb/gadget/v3_burning/v3_common/Makefile
new file mode 100644
index 0000000..eb20f05
--- /dev/null
+++ b/drivers/usb/gadget/v3_burning/v3_common/Makefile
@@ -0,0 +1,10 @@
+
+obj-y += aml_v3_common.o
+
+aml_v3_common-y += v3_tool_buff_manager.o
+aml_v3_common-y += v3_tool_simg2img.o
+aml_v3_common-y += v3_tool_media.o
+ifndef CONFIG_AML_V2_FACTORY_BURN
+aml_v3_common-y += ../../v2_burning/v2_common/optimus_progress.o
+endif
+
diff --git a/drivers/usb/gadget/v3_burning/v3_common/v3_tool_buff_manager.c b/drivers/usb/gadget/v3_burning/v3_common/v3_tool_buff_manager.c
new file mode 100644
index 0000000..76d3197
--- /dev/null
+++ b/drivers/usb/gadget/v3_burning/v3_common/v3_tool_buff_manager.c
@@ -0,0 +1,497 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "../include/v3_tool_def.h"
+#include <mmc.h>
+
+int v3tool_simg2img_init(const ImgDownloadPara* downPara);
+int v3tool_simg2img_get_img(UsbDownInf* downInf);
+int v3tool_simg2img_write_img(const UsbDownInf* downInf, const ImgDownloadPara* downPara);
+int v3tool_simg2img_verify_img(sha1_context* ctx, const char* partName, int64_t partBase);
+#ifndef CONFIG_V3_KEY_BURNING_SUPPORT
+static int v2_key_read(const char* keyName, u8* keyVal, const unsigned keyValLen, char* errInfo, unsigned* fmtLen)
+{
+ FB_ERR("burn key not supported as CONFIG_UNIFY_KEY_MANAGE undef!!");
+ return -1;
+}
+static unsigned v2_key_burn(const char* keyName, const u8* keyVal, const unsigned keyValLen, char* errInfo)
+{
+ FB_ERR("burn key not supported as CONFIG_UNIFY_KEY_MANAGE undef!!");
+ return -1;
+}
+#define key_manage_query_size(a,b) 1
+#endif// //#ifdef CONFIG_V3_KEY_BURNING_SUPPORT
+
+static struct {
+ ImgTransPara imgTransPara;//user para
+ int isDownload;
+ int dataBufCap;
+ char* dataBuf;
+ char* verifyInfo;//verifyInfo will saved while downloading, and used while verify
+ int inited;
+
+}_imgTransferInfo;
+
+static UsbDownInf _usbDownInf = {0};
+static UsbUpInf _usbUpInf = {0};
+static int64_t _rawImgFileOffset = 0;
+static int64_t _rawImgVryLen = 0;
+
+//isn't pc get busy info and so still waiting
+static int _dnl_check_if_PC_waiting(void)
+{
+ return !strncmp(fb_response_str - 4, "INFO", 4);
+}
+
+int v3tool_buffman_img_verify_sha1sum(unsigned char* vrySum)
+{
+ static sha1_context ctx;
+ const ImgDownloadPara* imgDownPara = &_imgTransferInfo.imgTransPara.download;
+ const ImgCommonPara* imgCmnPara = &imgDownPara->commonInf;
+ const int media = imgCmnPara->mediaType;
+ const int imgFmt = imgDownPara->imgFmt;
+ const char* part = imgCmnPara->partName;
+ const int64_t imgTotalLen = imgCmnPara->imgSzTotal;
+ const int64_t partBase = imgCmnPara->partStartOff;
+ unsigned char* vryBuff = (unsigned char*)V3_DOWNLOAD_MEM_BASE;
+ const int vryBuffLen = (2<<20);
+ int64_t vryLen = _rawImgVryLen;
+ int ret = 0;
+ if (!_imgTransferInfo.isDownload) {
+ FBS_ERR(_ACK, "only download can support verify now.");
+ return -__LINE__;
+ }
+ if ( V3TOOL_MEDIA_TYPE_STORE != media ) {
+ FBS_ERR(_ACK, "verify can'tsupport media[%d]", media);
+ return -__LINE__;
+ }
+ //report busy, then continue verify at next pc bulk-in request
+ if ( !_dnl_check_if_PC_waiting() ) {
+ sha1_starts(&ctx);
+ FB_DBG("init ctx\n");
+ }
+
+ if ( !strcmp("bootloader", part) ) {
+ ret = bootloader_read(vryBuff, 0, imgTotalLen);
+ sha1_update(&ctx, vryBuff, imgTotalLen);
+ } else if ( !strcmp("_aml_dtb", part) ) {
+ ret = store_dtb_rw(vryBuff, imgTotalLen, 2);
+ sha1_update(&ctx, vryBuff, imgTotalLen);
+ } else if (!strcmp("gpt", part)) {
+ ret = store_gpt_ops(imgTotalLen, vryBuff,0);
+ sha1_update(&ctx, vryBuff, imgTotalLen);
+ } else {
+ switch (imgFmt)
+ {
+ case V3TOOL_PART_IMG_FMT_RAW:
+ {
+ int thisVryLen = 0;
+ static unsigned long _lastReportTick = 0;
+ if (!vryLen) _lastReportTick = get_timer(0);
+ for (; vryLen < imgTotalLen; vryLen += thisVryLen)
+ {
+ thisVryLen = imgTotalLen - vryLen;
+ thisVryLen = thisVryLen > vryBuffLen ? vryBuffLen : thisVryLen;
+ ret = store_logic_read(part, vryLen + partBase, thisVryLen, vryBuff);
+ if ( ret ) {
+ FBS_ERR(_ACK, "FAil in store read");
+ return -__LINE__;
+ }
+ sha1_update(&ctx, vryBuff, thisVryLen);
+ if (get_timer(_lastReportTick) >= 4000) {
+ _lastReportTick += get_timer(_lastReportTick);
+ _rawImgVryLen = vryLen + thisVryLen;
+ char info[64];
+ sprintf(info, "%06lld / %06lld MBytes", (vryLen>>20), (imgTotalLen>>20));
+ v3tool_media_set_busy(info);
+ return 0;
+ }
+ }
+
+ }break;
+ case V3TOOL_PART_IMG_FMT_SPARSE:
+ {
+ ret = v3tool_simg2img_verify_img(&ctx, part, partBase);
+ if ( ret ) {
+ FB_ERR("fail in very img,ret %d\n", ret);
+ return -__LINE__;
+ }
+ if (v3tool_media_is_busy()) {
+ return 0;
+ }
+ }break;
+ default:
+ FBS_ERR(_ACK, "imgFmt[%x] cannot verify", imgFmt);
+ return -__LINE__;
+ }
+ }
+ sha1_finish(&ctx, vrySum);
+ v3tool_media_set_free(NULL);
+ return 0;
+}
+
+static int _buffman_img_init_mmc(const char* partName, const int isDownload, const int64_t imgSize, const int64_t partStartOff)
+{
+#if CONFIG_IS_ENABLED(MMC_WRITE)
+ int dev = -1;
+
+ if (strcmp("1", partName) && strcmp("0", partName)) {
+ FBS_ERR(_ACK, "mmc part[%s] invalid\n", partName); return -__LINE__;
+ }
+ env_set("mmc_dev_id", partName);
+ env_set("mmc_select_dev", "mmc dev ${mmc_dev_id}");
+ if (run_command("printenv mmc_select_dev; run mmc_select_dev", 0)) {
+ FBS_ERR(_ACK, "Fail in init mmc dev %s\n", partName); return -__LINE__;
+ }
+
+ dev = partName[0] - '0';
+ struct mmc* mmc = find_mmc_device(dev);
+ if (!mmc) {
+ FBS_ERR(_ACK, "no mmc device at slot %x\n", dev); return -__LINE__;
+ }
+ if (mmc_init(mmc)) {
+ FBS_ERR(_ACK, "fail in init mmc %d\n", dev); return -__LINE__;
+ }
+ const int64_t capacity = mmc->capacity_user;
+ if (capacity < partStartOff + imgSize) {
+ FBS_ERR(_ACK, "capacity < partStartOff + imgSize 0x:%llx %llx %llx\n", capacity, partStartOff, imgSize);
+ return -__LINE__;
+ }
+ if (mmc_getwp(mmc) == 1) {
+ FBS_ERR(_ACK, "Error: mmc(%s) is write protected!\n", partName);
+ return -__LINE__;
+ }
+ run_command("store rsv protect key off", 0);//disprotect key for write/dump all emmc
+
+ return 0;
+#else
+ FBS_ERR(_ACK, "CONFIG_MMC_WRITE not enabled\n");
+ return -__LINE__;
+#endif//#if CONFIG_IS_ENABLED(MMC_WRITE)
+}
+
+//@imgPara:
+//@isDownload: 1 if download, 0 if upload
+//@needVerify: 1 if need verify, if need verify, will save some info while downloading
+// will ignored if not download mode
+int v3tool_buffman_img_init(ImgTransPara* imgPara, const int isDownload)
+{
+ _imgTransferInfo.isDownload = isDownload;
+ memcpy(&_imgTransferInfo.imgTransPara, imgPara, sizeof(ImgTransPara));
+ _imgTransferInfo.dataBuf = (char*)V3_DOWNLOAD_MEM_BASE;
+ _imgTransferInfo.dataBufCap = V3_DOWNLOAD_MEM_SIZE;
+ _imgTransferInfo.verifyInfo = isDownload ? (char*)V3_DOWNLOAD_VERIFY_INFO : NULL;
+ _imgTransferInfo.inited = 1;
+ ImgCommonPara* commonInf = &imgPara->commonInf;
+ const int64_t imgSize = commonInf->imgSzTotal;
+ const int64_t partStartOff = commonInf->partStartOff;
+ const char* partName = commonInf->partName;
+ int ret = 0;
+
+ switch (commonInf->mediaType)
+ {
+ case V3TOOL_MEDIA_TYPE_MEM:
+ { //User should make sure mem address is able to access by himself if media is mem
+ _imgTransferInfo.dataBuf = (char*)commonInf->partStartOff;
+ _imgTransferInfo.dataBufCap = imgSize;
+ _imgTransferInfo.verifyInfo = NULL;
+ } break;
+ case V3TOOL_MEDIA_TYPE_STORE:
+ {
+ ret = v3tool_media_check_image_size(imgSize + partStartOff, partName);
+ if ( ret ) {
+ FB_EXIT("Fail in check img sz\n");
+ }
+ }break;
+ case V3TOOL_MEDIA_TYPE_UNIFYKEY:
+ {
+ if (!isDownload) {
+ const char* queryKey = commonInf->partName;
+ ssize_t keySz = 0;
+ ret = key_manage_query_size(queryKey,&keySz);
+ if (ret) {
+ FB_EXIT("Fail get sz for key[%s]\n", queryKey);
+ }
+ if (keySz != imgSize) {
+ FB_EXIT("key[%s] sz %zd != cmd key sz %lld\n", queryKey, keySz, imgSize);
+ }
+ }
+ } break;
+ case V3TOOL_MEDIA_TYPE_MMC:
+ {
+ ret = _buffman_img_init_mmc(partName, isDownload, imgSize, partStartOff);
+ if (ret) FB_EXIT("Fail in init mmc %s\n", partName);
+ } break;
+ default:
+ FB_EXIT("Exception, err media type 0x%x\n", commonInf->mediaType);
+ }
+ if (V3TOOL_PART_IMG_FMT_SPARSE == imgPara->download.imgFmt && isDownload) {
+ imgPara->download.needVerify = 1;
+ if (v3tool_simg2img_init(&imgPara->download)) {
+ FB_ERR("Fail in simg init\n");
+ return -__LINE__;
+ }
+ }
+ //Init _usbDownInf for raw image
+ _rawImgFileOffset = 0;
+ _rawImgVryLen = 0;
+ optimus_progress_init((unsigned)(imgSize>>32), (unsigned)imgSize, 0, 100);
+
+ return 0;
+}
+
+static int _v3tool_buffman_next_download_info_rawimg(ImgDownloadPara* imgPara)
+{
+ ImgCommonPara* cmnInf = &imgPara->commonInf;
+ switch (cmnInf->mediaType) {
+ case V3TOOL_MEDIA_TYPE_MEM:
+ {
+ _usbDownInf.fileOffset = _rawImgFileOffset;
+ int64_t leftLen = cmnInf->imgSzTotal - _rawImgFileOffset;
+ _usbDownInf.dataSize = _mymin(leftLen, _RAW_IMG_TRANSFER_LEN);
+ _usbDownInf.dataBuf = _imgTransferInfo.dataBuf + _rawImgFileOffset;
+ FB_DBG("dataBuf %p, dataSize %x\n", _usbDownInf.dataBuf, _usbDownInf.dataSize);
+ }break;
+ case V3TOOL_MEDIA_TYPE_MMC:
+ case V3TOOL_MEDIA_TYPE_STORE:
+ {
+ _usbDownInf.fileOffset = _rawImgFileOffset;
+ int64_t leftLen = cmnInf->imgSzTotal - _rawImgFileOffset;
+ if (strcmp("bootloader", cmnInf->partName) && strcmp("_aml_dtb", cmnInf->partName)
+ && strcmp("gpt", cmnInf->partName))
+ {_usbDownInf.dataSize = _mymin(leftLen, _RAW_IMG_TRANSFER_LEN);}
+ else _usbDownInf.dataSize = leftLen;
+ _usbDownInf.dataBuf = (char*)V3_DOWNLOAD_MEM_BASE;
+ }break;
+ case V3TOOL_MEDIA_TYPE_UNIFYKEY:
+ {
+ _usbDownInf.fileOffset = _rawImgFileOffset;
+ _usbDownInf.dataSize = cmnInf->imgSzTotal - _rawImgFileOffset;
+ _usbDownInf.dataBuf = (char*)V3_DOWNLOAD_MEM_BASE;
+ } break;
+ default:
+ {
+ FB_EXIT("err media type %d\n", cmnInf->mediaType);
+ }break;
+ }
+
+ //for next raw img download
+ _rawImgFileOffset += _usbDownInf.dataSize;
+ return 0;
+}
+
+int v3tool_buffman_next_download_info(UsbDownInf** downloadInf)
+{
+ int ret = 0;
+ *downloadInf = NULL;
+ if (!_imgTransferInfo.inited || !_imgTransferInfo.isDownload) {
+ FBS_ERR(_ACK, "buffman %d, %d\n", _imgTransferInfo.inited ,_imgTransferInfo.isDownload);
+ return -__LINE__;
+ }
+
+ ImgDownloadPara* imgPara = &_imgTransferInfo.imgTransPara.download;
+ ImgCommonPara* cmnInf = &imgPara->commonInf;
+ switch (imgPara->imgFmt) {
+ case V3TOOL_PART_IMG_FMT_RAW:
+ {
+ ret = _v3tool_buffman_next_download_info_rawimg(imgPara);
+ if ( ret ) FB_EXIT("FAil in get buf for raw img\n");
+ *downloadInf = &_usbDownInf;
+ return 0;
+ }
+ case V3TOOL_PART_IMG_FMT_SPARSE:
+ {
+ switch (cmnInf->mediaType) {
+ case V3TOOL_MEDIA_TYPE_STORE:
+ {
+ ret = v3tool_simg2img_get_img(&_usbDownInf);
+ if ( !ret ) *downloadInf = &_usbDownInf;
+ else {
+ FBS_ERR(_ACK, "fail in get next sp img data");
+ return -__LINE__;
+ }
+ }break;
+ default:
+ {
+ FBS_ERR(fb_response_str, "err media %d for sparse fmt", cmnInf->mediaType);
+ }break;
+ }
+ }break;
+ default:
+ FBS_ERR(_ACK, "unsupported imgFmt 0x%x", imgPara->imgFmt);
+ return -__LINE__;
+ }
+
+ return ret;
+}
+
+static int _v3tool_mmc_rw(const char* partName, const int write, const int thisTransferLen, loff_t partOffset, void* dataBuf)
+{
+#if CONFIG_IS_ENABLED(MMC_WRITE)
+ int dev = *partName - '0';
+ struct mmc *mmc = find_mmc_device(dev);
+ if (!mmc) {
+ FBS_ERR(_ACK, "no mmc device at slot %x\n", dev); return -__LINE__;
+ }
+ if (mmc_init(mmc)) {
+ FBS_ERR(_ACK, "fail mmc_init[%s]", partName); return -__LINE__;
+ }
+ u32 cnt = (thisTransferLen + 511) >> 9;
+ u32 blk = partOffset>>9;
+ u32 n = 0;
+ if (write) n = blk_dwrite(mmc_get_blk_desc(mmc), blk, cnt, dataBuf);
+ else n = blk_dread(mmc_get_blk_desc(mmc), blk, cnt, dataBuf);
+ return (n == cnt) ? 0 : -__LINE__;
+#else
+ FBS_ERR(_ACK, "CONFIG_MMC_WRITE not enabled\n");
+ return -__LINE__;
+#endif//#if CONFIG_IS_ENABLED(MMC_WRITE)
+}
+
+int v3tool_buffman_data_complete_download(const UsbDownInf* downloadInf)
+{
+ ImgCommonPara* cmnInf = &_imgTransferInfo.imgTransPara.commonInf;
+ ImgDownloadPara* downInf = &_imgTransferInfo.imgTransPara.download;
+ const int imgFmt = downInf->imgFmt;
+ /*const int needVerify = downInf->needVerify;*/
+ const int mediaType = cmnInf->mediaType;
+ const char* partName = cmnInf->partName;
+ int ret = 0;
+ const int thisTransferLen = downloadInf->dataSize;
+ u8* dataBuf = (u8*)downloadInf->dataBuf;
+ loff_t partOffset = downloadInf->fileOffset + cmnInf->partStartOff;
+
+ switch ( imgFmt ) {
+ case V3TOOL_PART_IMG_FMT_RAW:
+ {
+ switch ( mediaType ) {
+ case V3TOOL_MEDIA_TYPE_STORE:
+ {
+ if ( !strcmp("bootloader", partName) ) {
+ ret = bootloader_write(dataBuf, 0, thisTransferLen);
+ } else if ( !strcmp("_aml_dtb", partName) ) {
+ ret = store_dtb_rw(dataBuf, thisTransferLen, 1);
+ } else if ( !strcmp("gpt", partName) ) {
+ ret = store_gpt_ops(thisTransferLen, dataBuf, 1);
+ } else {
+ ret = store_logic_write(partName, partOffset, thisTransferLen, dataBuf);
+ }
+ } break;
+ case V3TOOL_MEDIA_TYPE_MEM:
+ break;
+ case V3TOOL_MEDIA_TYPE_UNIFYKEY:
+ ret = v2_key_burn(partName, dataBuf, thisTransferLen, _ACK);
+ if (ret != thisTransferLen) {
+ FBS_ERR(_ACK, "err in program key to media,ret %d", ret);
+ ret = -__LINE__;
+ } else ret = 0;
+ break;
+ case V3TOOL_MEDIA_TYPE_MMC:
+ {
+ ret = _v3tool_mmc_rw(partName, 1, thisTransferLen, partOffset, dataBuf);
+ } break;
+ default:
+ FBS_ERR(fb_response_str, "err media type %d for raw img", mediaType);
+ break;
+ }
+ }break;
+ case V3TOOL_PART_IMG_FMT_SPARSE:
+ {
+ FB_DBG("buf %p, sz %d\n", downloadInf->dataBuf, thisTransferLen);
+ ret = v3tool_simg2img_write_img(downloadInf, &_imgTransferInfo.imgTransPara.download);
+ } break;
+ case V3TOOL_PART_IMG_FMT_UBIFS:
+ break;
+ default:
+ FBS_ERR(fb_response_str, "err media type %d for sp img", mediaType);
+ break;
+ }
+ if ( !ret )optimus_update_progress(thisTransferLen);
+
+ return ret;
+}
+
+int v3tool_buffman_data_complete_upload(const UsbUpInf* uploadInf)
+{
+ //for next download
+ _rawImgFileOffset += uploadInf->dataSize;
+ return 0;
+}
+
+int v3tool_buffman_next_upload_info(UsbUpInf** uploadInfo)
+{
+ int ret = 0;
+ *uploadInfo = NULL;
+ if (!_imgTransferInfo.inited || _imgTransferInfo.isDownload) {
+ FB_ERR("buffman %d, %d\n", _imgTransferInfo.inited ,_imgTransferInfo.isDownload);
+ return -__LINE__;
+ }
+ ImgUploadPara* upInf = &_imgTransferInfo.imgTransPara.upload;
+ ImgCommonPara* cmnInf = &upInf->commonInf;
+ char* partName = (char*)cmnInf->partName;
+
+ int64_t leftLen = cmnInf->imgSzTotal - _rawImgFileOffset;
+ if ( !leftLen ) {
+ _usbUpInf.dataSize = 0;
+ *uploadInfo = &_usbUpInf;
+ return 0;
+ }
+
+ _usbUpInf.dataSize = _mymin(leftLen, _RAW_IMG_TRANSFER_LEN);
+ _usbUpInf.dataBuf = (char*)V3_DOWNLOAD_MEM_BASE;
+ u8* dataBuf = (u8*)_usbUpInf.dataBuf;
+ unsigned dataSize = _usbUpInf.dataSize;
+ loff_t partOffset = _rawImgFileOffset + cmnInf->partStartOff;
+ switch (cmnInf->mediaType) {
+ case V3TOOL_MEDIA_TYPE_MEM:
+ {
+ _usbUpInf.dataBuf = (char*)cmnInf->partStartOff + _rawImgFileOffset;
+ }break;
+ case V3TOOL_MEDIA_TYPE_STORE:
+ {
+ if ( !strcmp("bootloader", partName) || !strcmp("_aml_dtb", partName)
+ || !strcmp("gpt", partName)) {
+ dataSize = _usbUpInf.dataSize = leftLen;
+ }
+ if (!strcmp("bootloader", partName)) {
+ ret = bootloader_read(dataBuf, 0, dataSize);
+ } else if (!strcmp("_aml_dtb", partName)) {
+ //'2' means using 'store dtb iread' rather than 'read'
+ ret = store_dtb_rw(dataBuf, dataSize, 2);
+ } else if ( !strcmp("gpt", partName) ) {
+ ret = store_gpt_ops(dataSize, dataBuf, 0);
+ } else {
+ ret = store_logic_read(partName, _rawImgFileOffset + cmnInf->partStartOff, dataSize, dataBuf);
+ }
+ if (ret) {
+ FB_ERR("Fail in read store at offset %llx\n", _rawImgFileOffset);
+ return -__LINE__;
+ }
+ }break;
+ case V3TOOL_MEDIA_TYPE_UNIFYKEY:
+ {
+ _usbUpInf.dataSize = leftLen;
+ unsigned keySz = 0;
+ ret = v2_key_read(partName, (u8*)_usbUpInf.dataBuf, leftLen, _ACK, &keySz);
+ if (ret || keySz != leftLen) {
+ FB_ERR("Fail in key read,ret %d\n", ret);
+ return -__LINE__;
+ }
+ }break;
+ case V3TOOL_MEDIA_TYPE_MMC:
+ {
+ ret = _v3tool_mmc_rw(partName, 0, dataSize, partOffset, dataBuf);
+ } break;
+ default:
+ FB_ERR("unsupported media %d\n", cmnInf->mediaType);
+ break;
+ }
+
+ FB_DBG("dataBuf %p, dataSize %x\n", _usbUpInf.dataBuf, _usbUpInf.dataSize);
+
+ *uploadInfo = &_usbUpInf;
+ return 0;
+}
+
diff --git a/drivers/usb/gadget/v3_burning/v3_common/v3_tool_media.c b/drivers/usb/gadget/v3_burning/v3_common/v3_tool_media.c
new file mode 100644
index 0000000..8d72981
--- /dev/null
+++ b/drivers/usb/gadget/v3_burning/v3_common/v3_tool_media.c
@@ -0,0 +1,546 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "../include/v3_tool_def.h"
+#include <fdtdec.h>
+#include <asm/arch/cpu_config.h>
+#include <u-boot/sha256.h>
+#define DWN_ERR FB_ERR
+#define BOOTLOADER_MAX_SZ (0x2<<20)
+#define DTB_MAX_SZ (256<<10)
+#define DWN_DBG FB_DBG
+#define DWN_ERR FB_ERR
+#define DWN_MSG FB_MSG
+#define DWN_WRN FB_WRN
+
+DECLARE_GLOBAL_DATA_PTR;
+
+//make sure logic part sz == dtb configured sz
+static int _assert_logic_partition_cap(const char* thePartName, const uint64_t nandPartCap)
+{
+ extern struct partitions * part_table;
+
+ int partIndex = 0;
+ struct partitions * thePart = NULL;
+ if (NULL == part_table)
+ return 0;
+ for (thePart = part_table; partIndex < MAX_PART_NUM; ++thePart, ++partIndex)
+ {
+ const uint64_t partSzInBytes = thePart->size;
+ if (memcmp(thePartName, thePart->name, strlen(thePartName))) continue;
+
+ FB_DBG("cfg partSzInBytes %llx for part(%s)\n", partSzInBytes, thePartName);
+ if (NAND_PART_SIZE_FULL == partSzInBytes) {return 0;}
+ if (partSzInBytes > nandPartCap) {
+ FB_EXIT("partSz of logic part(%s): sz dts %llx > Sz flash %llx\n",
+ thePartName, partSzInBytes, nandPartCap);
+ }
+
+ return 0;
+ }
+
+ FB_EXIT("Can't find your download part(%s)\n", thePartName);
+}
+
+#if 1//storage wrapper
+static int is_bootloader_discrte(bool* discreteMode)
+{
+ struct storage_info_t storeInfo;
+ if (store_get_device_info(&storeInfo)) {
+ FB_ERR("Fail get store dev info\n");
+ return __LINE__;
+ }
+ *discreteMode = (DISCRETE_BOOTLOADER == storeInfo.mode);
+ return 0;
+}
+
+static int bootloader_copy_sz(void)
+{
+ bool discreteMode = false;
+ if (is_bootloader_discrte(&discreteMode)) {
+ return 0;
+ }
+
+ return store_boot_copy_size("bootloader");
+}
+
+static int _bootloader_write(u8* dataBuf, unsigned off, unsigned binSz, const char* bootName)
+{
+ int iCopy = 0;
+ const int bootCpyNum = store_boot_copy_num(bootName);
+ const int bootCpySz = (int)store_boot_copy_size(bootName);
+ FB_MSG("[%s] CpyNum %d, bootCpySz 0x%x\n", bootName, bootCpyNum, bootCpySz);
+ if (binSz + off > bootCpySz) FBS_EXIT(_ACK, "bootloader sz(0x%x) + off(0x%x) > bootCpySz 0x%x\n", binSz, off, bootCpySz);
+
+ if (off) {
+ FBS_ERR(_ACK, "current only 0 suuported!\n");
+ return -__LINE__;
+ }
+
+ for (; iCopy < bootCpyNum; ++iCopy) {
+ int ret = store_boot_write(bootName, iCopy, binSz, dataBuf);
+ if (ret) FBS_EXIT(_ACK, "FAil in program[%s] at copy[%d]\n", bootName, iCopy);
+ }
+
+ return 0;
+}
+
+static p_payload_info_t _bl2x_mode_detect(u8* dataBuf)
+{
+ p_payload_info_t pInfo = (p_payload_info_t)(dataBuf + BL2_SIZE);
+
+ if (AML_MAGIC_HDR_L == pInfo->hdr.nMagicL && AML_MAGIC_HDR_R == pInfo->hdr.nMagicR) {
+ FB_MSG("aml log : bootloader blxx mode!\n");
+ return pInfo;
+ }
+ return NULL;
+}
+
+#ifdef CONFIG_SHA256
+static int _bl2x_mode_check_header(p_payload_info_t pInfo)
+{
+ p_payload_info_hdr_t hdr = &pInfo->hdr;
+ uint8_t gensum[SHA256_SUM_LEN];
+ const int nItemNum = hdr->byItemNum;
+
+ printf("\naml log : info parse...\n");
+ printf("\tsztimes : %s\n",hdr->szTimeStamp);
+ printf("\tversion : %d\n",hdr->byVersion);
+ printf("\tItemNum : %d\n",nItemNum);
+ printf("\tSize : %d(0x%x)\n", hdr->nSize, hdr->nSize);
+ if (nItemNum > 8 || nItemNum < 3) { FBS_EXIT(_ACK, "illegal nitem num %d\n", nItemNum); }
+
+ const int nsz = sizeof(payload_info_hdr_t) + nItemNum * sizeof(payload_info_item_t) - SHA256_SUM_LEN;
+ FB_MSG("nsz 0x%x\n", nsz);
+ sha256_context ctx;
+ sha256_starts(&ctx);
+ sha256_update(&ctx, (u8*)&(hdr->nMagicL), nsz);
+ sha256_finish(&ctx, gensum);
+ int ret = memcmp(gensum, hdr->szSHA2, SHA256_SUM_LEN);
+ if (ret) { FBS_EXIT(_ACK, "hdr info sha256sum not matched\n"); }
+ FB_MSG("hdr info sha256sum DO matched\n");
+
+ return 0;
+}
+#else
+#define _bl2x_mode_check_header(...) 0
+#endif// #ifdef CONFIG_SHA256
+
+static const char* _flashPayload[] = {"bl2", "bl2e", "bl2x", "ddrfip", "devfip"};
+static p_payload_info_t _blxPayloadInf = NULL;
+static int _payloadInfoSz = 0;
+static int _discrete_bootloader_write(u8* dataBuf, unsigned off, unsigned binSz)
+{
+ int bl2CopySz = BL2_SIZE/*(int)store_boot_copy_size("bl2")*/;
+ FB_MSG("bl2CopySz 0x%x, binSz 0x%x\n", bl2CopySz, binSz);
+ int ret = 0;
+
+ if (binSz > bl2CopySz)
+ {
+ _blxPayloadInf = NULL;
+ p_payload_info_t pInfo = _bl2x_mode_detect(dataBuf);
+ if (!pInfo) {
+ ret = _bootloader_write(dataBuf + bl2CopySz, 0, binSz - bl2CopySz, "tpl");
+ if (ret) FBS_EXIT(_ACK, "Fail in burn tpl\n");
+ } else
+ {
+ if (_bl2x_mode_check_header(pInfo)) {
+ FBS_EXIT(_ACK, "Fail in check bl2x info\n");
+ }
+ char name[8];
+ int nIndex = 0;
+ p_payload_info_hdr_t hdr = &pInfo->hdr;
+ p_payload_info_item_t pItem = pInfo->arrItems;
+
+ int offPayload = 0, szPayload = 0;
+
+ memset(name, 0, 8);
+ for (nIndex = 1, pItem += 1; nIndex < hdr->byItemNum; ++nIndex, ++pItem)
+ {
+ memcpy(name, &pItem->nMagic, sizeof(unsigned int));
+ offPayload = pItem->nOffset;
+ szPayload = pItem->nPayLoadSize;
+ FB_MSG("Item[%d]%4s offset 0x%08x sz 0x%x\n", nIndex, name, offPayload, szPayload);
+ if (!szPayload) continue;
+ ret = _bootloader_write(dataBuf + offPayload, 0, szPayload, _flashPayload[nIndex]);
+ if (ret) FBS_EXIT(_ACK, "Fail in flash payload %s\n", name);
+ }
+ _blxPayloadInf = (p_payload_info_t)V3_DOWNLOAD_VERIFY_INFO;
+ _payloadInfoSz = sizeof(payload_info_hdr_t) + pInfo->hdr.byItemNum * sizeof(payload_info_item_t);
+ memcpy(_blxPayloadInf, pInfo, _payloadInfoSz);
+ }
+ }
+
+ ret = _bootloader_write(dataBuf, 0, bl2CopySz, "bl2");
+ if (ret) FBS_EXIT(_ACK, "Fail in program bl2\n");
+
+ return 0;
+}
+
+int bootloader_write(u8* dataBuf, unsigned off, unsigned binSz)
+{
+ bool discreteMode = false;
+ if (is_bootloader_discrte(&discreteMode)) {
+ return -__LINE__;
+ }
+ if (!discreteMode) {
+ return _bootloader_write(dataBuf, off, binSz, "bootloader");
+ } else {
+ return _discrete_bootloader_write(dataBuf, off, binSz);
+ }
+ return -__LINE__;
+}
+
+static int _bootloader_read(u8* pBuf, unsigned off, unsigned binSz, const char* bootName)
+{
+ int iCopy = 0;
+ const int bootCpyNum = store_boot_copy_num(bootName);
+ const int bootCpySz = (int)store_boot_copy_size(bootName);
+
+ if (binSz + off > bootCpySz) {
+ FBS_ERR(_ACK, "bootloader sz(0x%x) + off(0x%x) > bootCpySz 0x%x\n", binSz, off, bootCpySz);
+ return -__LINE__;
+ }
+ if (off) FBS_EXIT(_ACK, "current only 0 suuported!\n");
+
+ for (iCopy = 0; iCopy < bootCpyNum; ++iCopy) {
+ void* dataBuf = iCopy ? pBuf + binSz : pBuf;
+ int ret = store_boot_read(bootName, iCopy, binSz, dataBuf);
+ if (ret) FBS_EXIT("Fail to read boot[%s] at copy[%d]\n", bootName, iCopy);
+ if (iCopy) {
+ if (memcmp(pBuf, dataBuf, binSz))
+ FBS_EXIT(_ACK, "[%s] copy[%d] content NOT the same as copy[0]\n", bootName, iCopy);
+ }
+ }
+
+ return 0;
+}
+
+static int _discrete_bootloader_read(u8* dataBuf, unsigned off, unsigned binSz)
+{
+ int bl2CopySz = BL2_SIZE/*(int)store_boot_copy_size("bl2")*/;
+ FB_MSG("bl2CopySz 0x%x, binSz 0x%x\n", bl2CopySz, binSz);
+
+ int ret = _bootloader_read(dataBuf, 0, bl2CopySz, "bl2");
+ if (ret) FBS_EXIT(_ACK, "Fail in read bl2\n");
+ if (binSz <= bl2CopySz) return 0;
+ memset(dataBuf + bl2CopySz, 0, bl2CopySz);//clear 2k after bl2_size
+
+ if (!_blxPayloadInf) {
+ ret = _bootloader_read(dataBuf + bl2CopySz, 0, binSz - bl2CopySz, "tpl");
+ if (ret) FBS_EXIT(_ACK, "Fail in read tpl\n");
+ } else {
+ char name[8];
+ int nIndex = 0;
+ if (!_blxPayloadInf) FBS_EXIT(_ACK, "exception, _blxPayloadInf null\n");
+
+ p_payload_info_t pInfo = _blxPayloadInf;
+ p_payload_info_hdr_t hdr = &pInfo->hdr;
+ p_payload_info_item_t pItem = pInfo->arrItems;
+
+ int offPayload = 0, szPayload = 0;
+
+ memset(name, 0, 8);
+ for (nIndex = 1, pItem +=1; nIndex < hdr->byItemNum; ++nIndex, ++pItem)
+ {
+ memcpy(name, &pItem->nMagic, sizeof(unsigned int));
+ offPayload = pItem->nOffset;
+ szPayload = pItem->nPayLoadSize;
+ FB_MSG("Item[%d]%4s offset 0x%08x sz 0x%x\n", nIndex, name, offPayload, szPayload);
+ if (!szPayload) continue;
+ ret = _bootloader_read(dataBuf + offPayload, 0, szPayload, _flashPayload[nIndex]);
+ if (ret) FBS_EXIT(_ACK, "Fail in read payload %s\n", name);
+ }
+ memcpy(dataBuf + BL2_SIZE, _blxPayloadInf, _payloadInfoSz);
+ }
+
+ return 0;
+}
+
+int bootloader_read(u8* pBuf, unsigned off, unsigned binSz)
+{
+ bool discreteMode = false;
+ if (is_bootloader_discrte(&discreteMode)) {
+ return -__LINE__;
+ }
+
+ if (discreteMode)
+ return _discrete_bootloader_read(pBuf, off, binSz);
+
+ return _bootloader_read(pBuf, off, binSz, "bootloader");
+}
+
+//@rwFlag: 0---read, 1---write, 2---iread
+int store_dtb_rw(void* buf, unsigned dtbSz, int rwFlag)
+{
+ int ret = 0;
+ const unsigned dtbCap = store_rsv_size("dtb");
+ if (dtbCap <= dtbSz)
+ FBS_EXIT(_ACK, "dtb sz 0x%x > cap 0x%x\t", dtbSz, dtbCap);
+
+ switch (rwFlag) {
+ case 2: {//iread
+ ret = store_rsv_read("dtb", dtbSz, buf);
+ if (ret) FBS_EXIT(_ACK, "err(%d) in read dtb\t", ret);
+ }
+ case 0: {//read
+ if ( 2 == rwFlag ) return 0;
+ //TODO: add dtb parser
+ FBS_EXIT(_ACK, "dtb parser not implemented yet\t");
+ }break;
+ case 1: {//write
+ ret = store_rsv_erase("dtb");
+ if (ret) FBS_EXIT(_ACK, "Fail erase dtb, ret %d\n", ret);
+ ret = store_rsv_write("dtb", dtbSz, buf);
+ if (ret) FBS_EXIT(_ACK, "Fail in dtb write, ret %d\t", ret);
+ }break;
+ default: FBS_EXIT(_ACK, "err dtb rwFlag %d\n", rwFlag);
+ }
+
+ return 0;
+}
+#endif// #if 1//storage wrapper
+
+
+int v3tool_media_check_image_size(int64_t imgSz, const char* partName)
+{
+ int ret = 0;
+ u64 partCap = 0;
+
+ if (!strcmp("bootloader", partName)) {
+ const unsigned bootSz = bootloader_copy_sz();
+ if (imgSz > bootSz)
+ FBS_EXIT(_ACK, "imgsz 0x%llx > copy sz 0x%x !\t", imgSz, bootSz);
+ return 0;
+ }
+
+ if (!strcmp("_aml_dtb", partName)) {
+ const unsigned dtbCap = store_rsv_size("dtb");
+ if (imgSz >= dtbCap)
+ FB_EXIT("imgsz 0x%llx >= max sz 0x%x\n", imgSz, dtbCap);
+ return 0;
+ }
+ if (!strcmp("gpt", partName)) {
+ if (imgSz >= 0x100000) {
+ FB_EXIT("imgsz 0x%llx >= max sz 1M\n", imgSz);
+ }
+ return 0;
+ }
+
+ partCap = store_part_size(partName);
+ if (!partCap) {
+ DWN_ERR("Fail to get size for part %s\n", partName);
+ return __LINE__;
+ }
+ DWN_MSG("flash LOGIC partCap 0x%llxB\n", partCap);
+ if (imgSz > partCap) {
+ DWN_ERR("imgSz 0x%llx out of cap 0x%llx\n", imgSz, partCap);
+ return __LINE__;
+ }
+ ret = _assert_logic_partition_cap(partName, partCap);
+ if (ret) {
+ DWN_ERR("Fail in _assert_logic_partition_cap\n");
+ return __LINE__;
+ }
+
+ return 0;
+}
+
+static int _optimusWorkMode = V3TOOL_WORK_MODE_NONE;
+
+int v3tool_work_mode_get(void)
+{
+ return _optimusWorkMode;
+}
+
+int v3tool_work_mode_set(int workmode)
+{
+ _optimusWorkMode = workmode;
+ return 0;
+}
+
+
+static int _disk_intialed_ok = 0;
+
+int v3tool_is_flash_erased(void)
+{
+ return _disk_intialed_ok>>16;
+}
+
+static int should_load_env(void)
+{
+#ifdef CONFIG_OF_CONTROL
+ return fdtdec_get_config_int(gd->fdt_blob, "load-environment", 1);
+#elif defined CONFIG_DELAY_ENVIRONMENT
+ return 0;
+#else
+ return 1;
+#endif
+}
+
+static int initr_env(void)
+{
+ /* initialize environment */
+ if (should_load_env()) {
+ DWN_MSG("usb producing env_relocate\n");
+ env_relocate();
+ }
+ return 0;
+}
+
+struct mtd_partition* __attribute__((weak)) get_partition_table(int *partitions)
+{ FB_WRN("get_partition_table undefined\n"); return NULL;}
+
+int __attribute__((weak)) sheader_need(void) { FB_WRN("sheader_need undefined\n"); return 0;}
+void __attribute__((weak)) sheader_load(void *addr) { FB_WRN("sheader_load undefined\n"); return;}
+
+#ifdef CONFIG_BACKUP_PART_NORMAL_ERASE
+const char* BackupPart = (const char*)(CONFIG_BACKUP_PART_NORMAL_ERASE);
+char* BackupPartAddr = (char*)(V3_DOWNLOAD_MEM_BASE);
+#endif// #ifdef CONFIG_BACKUP_PART_NORMAL_ERASE
+
+int v3tool_storage_init(const int eraseFlash, unsigned dtbImgSz, unsigned gptImgSz)
+{
+ int ret = 0;
+ unsigned char* dtbLoadedAddr = (unsigned char*)V3_DTB_LOAD_ADDR;
+
+ if (V3TOOL_WORK_MODE_USB_PRODUCE != v3tool_work_mode_get()) {//Already inited in other work mode
+ /*DWN_MSG("Exit before re-init\n");*/
+ /*store_exit();*/
+ }
+
+ if (dtbImgSz && !gptImgSz) {
+#if defined(CONFIG_MTD) && defined(CONFIG_AML_MTDPART)
+ extern int get_meson_mtd_partition_table(struct mtd_partition **partitions);
+ int mtdParts = -1;
+ struct mtd_partition *partitions;
+
+ mtdParts = get_meson_mtd_partition_table(&partitions);
+ if (partitions && (mtdParts > 0)) {//
+ extern int check_valid_dts(unsigned char *buffer);
+ ret = check_valid_dts(dtbLoadedAddr);
+ } else
+#endif // #if defined(CONFIG_MTD) && defined(CONFIG_AML_MTDPART)
+ ret = get_partition_from_dts(dtbLoadedAddr);
+ if (ret) FBS_EXIT(_ACK, "Failed at check dts\n");
+ } else if (gptImgSz) {
+ if (get_partition_from_dts((unsigned char*)V3_GPT_LOAD_ADDR)) {
+ FBS_EXIT(_ACK, "Fail at check gpt\n");
+ } else FB_MSG("Parse partition table from GPT\n");
+ }
+
+ if (sheader_need()) sheader_load((void*)V3_PAYLOAD_LOAD_ADDR);
+
+ ret = store_init(1);
+ if (ret <= 0)
+ FBS_EXIT(_ACK, "Fail in store init %d, ret %d\n", 1, ret);
+
+#ifdef CONFIG_BACKUP_PART_NORMAL_ERASE
+ u32 backupPartSz = 0;
+#endif//#ifdef CONFIG_BACKUP_PART_NORMAL_ERASE
+ int initFlag = 0;
+ switch (eraseFlash) {
+ case 0://NO erase
+ case 5://NO erase
+ initFlag = 1;
+ break;
+
+ case 3://erase all(with key)
+ case 1://normal erase, store init 3
+ initFlag = 3;
+ if (3 == eraseFlash) {
+ if (store_rsv_protect("key", false))
+ FBS_EXIT(_ACK, "Fail in disprotect key\n");
+ } else {
+#ifdef CONFIG_BACKUP_PART_NORMAL_ERASE
+ //backup env to memory
+ backupPartSz = (u32)store_part_size(BackupPart);
+ FB_MSG("BackupPart %s sz 0x%x\n", BackupPart, backupPartSz);
+ if (!backupPartSz) { FBS_EXIT(_ACK, " FAil in find BackupPart %s\n", BackupPart);}
+ ret = store_read(BackupPart, 0, backupPartSz, BackupPartAddr);
+ if (ret) { FBS_EXIT(_ACK, "FAil in backup important part %s to mem\n", BackupPart);}
+#endif//#ifdef CONFIG_BACKUP_PART_NORMAL_ERASE
+ }
+ break;
+
+ case 4: {//force erase all
+ if (store_rsv_protect(NULL, false))
+ FBS_EXIT(_ACK, "Fail in disprotect all rsv\n");
+ }
+ case 2:
+ initFlag = 4;
+ break;
+
+ default:
+ FBS_EXIT(_ACK, "Unsupported erase flag %d\n", eraseFlash);
+ }
+
+ FB_MSG("eraseFlash %d, initFlag %d\n", eraseFlash, initFlag);
+ if (5 == eraseFlash) {//erase key only
+ ret = store_rsv_erase("key");
+ if (ret) FBS_EXIT(_ACK, "disk_initial 5, Fail in erase key\n");
+ } else if (initFlag > 1) {
+ if (store_get_type() == BOOT_EMMC) {
+ FB_MSG("to erase gpt for compatible\n");
+ store_gpt_erase();
+ }
+ ret = store_erase(NULL, 0, 0, 0);
+ if (ret) FBS_EXIT(_ACK, "Fail in erase flash, ret[%d]\n", ret);
+#ifdef CONFIG_BACKUP_PART_NORMAL_ERASE
+ if (backupPartSz) {
+ FB_MSG("restore BackupPart %s from mem\n", BackupPart);
+ store_write(BackupPart, 0, backupPartSz, BackupPartAddr);
+ }
+#endif//#ifdef CONFIG_BACKUP_PART_NORMAL_ERASE
+ }
+
+ if (V3TOOL_WORK_MODE_USB_PRODUCE == v3tool_work_mode_get()) {
+ if (!_disk_intialed_ok) {//last disk_initial also okay
+ initr_env();//can only be called once
+ }
+ }
+ _disk_intialed_ok = 1;
+ if (eraseFlash && eraseFlash < 5) _disk_intialed_ok += (1 <<16);
+
+ if (dtbImgSz)//for key init, or fail when get /unifykey
+ {
+ unsigned long fdtAddr = (unsigned long)dtbLoadedAddr;
+#ifdef CONFIG_MULTI_DTB
+ fdtAddr = get_multi_dt_entry(fdtAddr);
+#endif// #ifdef CONFIG_MULTI_DTB
+ ret = fdt_check_header((char*)fdtAddr);
+ if (ret) FBS_EXIT(_ACK, "Fail in fdt check header\n");
+
+ unsigned fdtsz = fdt_totalsize((char*)fdtAddr);
+ if (fdtAddr != (unsigned long)dtbLoadedAddr)
+ memmove((char*)dtbLoadedAddr, (char*)fdtAddr, fdtsz);
+ }
+
+ return 0;
+}
+
+static int _v3tool_is_busy = 0;
+static char* _v3tool_media_busy_info = "";
+void v3tool_media_set_busy(const char* busyInfo)
+{
+ _v3tool_is_busy = 1;
+ _v3tool_media_busy_info = fb_response_str - 4;
+ strncpy(_v3tool_media_busy_info, "INFO", 4 + 1);//add terminated 0
+ if (busyInfo)
+ strncpy(_v3tool_media_busy_info + 4, busyInfo, 64);
+}
+void v3tool_media_set_free(const char* info)
+{
+ _v3tool_is_busy = 0;
+ _v3tool_media_busy_info = fb_response_str - 4;
+ strncpy(_v3tool_media_busy_info, "OKAY", 4 + 1);
+ if (info)
+ strncpy(_v3tool_media_busy_info + 4, info, 64);
+}
+int v3tool_media_is_busy(void)
+{
+ return _v3tool_is_busy;
+}
+
diff --git a/drivers/usb/gadget/v3_burning/v3_common/v3_tool_simg2img.c b/drivers/usb/gadget/v3_burning/v3_common/v3_tool_simg2img.c
new file mode 100644
index 0000000..113f2a8
--- /dev/null
+++ b/drivers/usb/gadget/v3_burning/v3_common/v3_tool_simg2img.c
@@ -0,0 +1,495 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include "../include/v3_tool_def.h"
+#include <sparse_format.h>
+extern char* fb_response_str;
+#define CHUNK_HEAD_SIZE sizeof(chunk_header_t)
+#define FILE_HEAD_SIZE sizeof(sparse_header_t)
+#define SPARSE_HEADER_MAJOR_VER 1
+#define sperr(fmt...) FBS_ERR(fb_response_str, fmt)
+#define spmsg FB_MSG
+
+//states for a sparse packet, initialized when sparse packet probed
+static struct
+{
+ unsigned leftChunkNum;//chunks that not parsed yet
+ unsigned chunksBufLen;//>=OPTIMUS_DOWNLOAD_SPARSE_TRANSFER_SZ
+ unsigned sparseBlkSz;//block size of sparse format packet
+ int pktHeadLen;
+ char* chunkDataBuf;//buf for usb download
+
+ //back up infomation for verify
+ chunk_header_t* chunkInfoBackAddr;//file header and chunk info back address
+ uint32_t backChunkNum; //chunk number backed
+ int64_t leftTransLen;
+ int64_t nextFlashAddr;
+ int64_t fileOffset; //fileOffset for usb download
+ int64_t imgTotalLen; //fileOffset for usb download
+ chunk_header_t* chunkInfo;
+
+}_spPacketStates;
+static int _downloadState = 0;
+enum {
+ SP_DOWNLOAD_START = 0XF1,
+ SP_DOWNLOAD_OK ,
+ SP_VERIFY_ING ,
+};
+
+static int _simg_probe(const char* source, const u32 length)
+{
+ sparse_header_t *header = (sparse_header_t*) source;
+
+ if (length < FILE_HEAD_SIZE) {
+ sperr("length %d < sparse_header_t len %d\n", length, (int)FILE_HEAD_SIZE);
+ return 0;
+ }
+ if (header->magic != SPARSE_HEADER_MAGIC) {
+ spmsg("sparse bad magic, expect 0x%x but 0x%x\n", SPARSE_HEADER_MAGIC, header->magic);
+ return 0;
+ }
+
+ if(!(SPARSE_HEADER_MAJOR_VER == header->major_version
+ && FILE_HEAD_SIZE == header->file_hdr_sz
+ && CHUNK_HEAD_SIZE == header->chunk_hdr_sz))
+ {
+ sperr("want 0x [%x, %x, %x], but [%x, %x, %x]\n",
+ SPARSE_HEADER_MAJOR_VER, (unsigned)FILE_HEAD_SIZE, (unsigned)CHUNK_HEAD_SIZE,
+ header->major_version, header->file_hdr_sz, header->chunk_hdr_sz);
+ return 0;
+ }
+
+
+ return 1;
+}
+
+int v3tool_simg2img_init(const ImgDownloadPara* downPara)
+{
+ if ( V3TOOL_PART_IMG_FMT_SPARSE != downPara->imgFmt) {
+ FBS_ERR(fb_response_str, "err img fmt %d for sparse", downPara->imgFmt);
+ return -__LINE__;
+ }
+ memset(&_spPacketStates, 0, sizeof(_spPacketStates));
+ _spPacketStates.chunkDataBuf = (char*)V3_DOWNLOAD_MEM_BASE;
+ if ( downPara->needVerify )
+ _spPacketStates.chunkInfoBackAddr = (chunk_header_t*)V3_DOWNLOAD_VERIFY_INFO;
+ else FB_MSG("don't save inf for verify!\n");
+ _spPacketStates.imgTotalLen = downPara->commonInf.imgSzTotal;
+ _downloadState = SP_DOWNLOAD_START;
+
+ return 0;
+}
+
+/*v3tool_simg2img_get_img: decide sparse img offset/size for download
+ * if download info empty <==> first time download:
+ * then getSz = get header and one trunk info
+ * if download info @leftTransLen == 0 <==> download ended
+ * else leftSz =(chunk data len + chunkinfo)
+ * if leftSz > V3_DOWNLOAD_MEM_SIZE then getSz = V3_DOWNLOAD_MEM_SIZE
+ * if leftSz <= getSz + V3_DOWNLOAD_SPARE_SZ then getSz = leftSz
+ * else getSz = leftSz
+ * *******************************
+ * need support called more than once when usb-->ddr transfer addsum failed,
+ * so don't update global var in get_img,
+ * so update @leftTransLen in v3tool_simg2img_write_img, which is after usb->ddr check ok
+ * */
+/*
+ * code flow: first time, then {sz = header + first chunkinfo, offset = 0}
+ * else {
+ * offset = _spPacketStates.fileOffset;
+ * sz = V3_DOWNLOAD_MEM_SIZE ;
+ * if (sz + spare >= img left sz) then sz = img left sz
+ * ??write img only dispose DATA + chunkinfo, so maybe 8M > this, but not matter??
+ * }
+ */
+int v3tool_simg2img_get_img(UsbDownInf* downInf)
+{
+ downInf->dataBuf = (char*)V3_DOWNLOAD_MEM_BASE;
+ downInf->fileOffset = _spPacketStates.fileOffset;
+ int* dataSize = &(downInf->dataSize);
+ //Following update downInf->dataSize
+
+ //spmsg("L%d:leftTransLen 0x%llx\n", __LINE__, _spPacketStates.leftTransLen);
+ //update leftTransLen if consumered by usb
+ if (_spPacketStates.leftTransLen <= 0)
+ {
+ const int firstTime = !_spPacketStates.sparseBlkSz && !_spPacketStates.pktHeadLen;
+ if ( firstTime ) {
+ *dataSize = CHUNK_HEAD_SIZE + FILE_HEAD_SIZE;
+ return 0;
+ }
+
+ if (_spPacketStates.imgTotalLen == _spPacketStates.fileOffset) {
+ *dataSize = 0;
+ _downloadState = SP_DOWNLOAD_OK;
+ spmsg("Finish sparse img\n");
+ return 0;
+ }
+ FBS_ERR(fb_response_str, "Excep:NO leftTransLen but img not end, fileOffset %llx, leftChunkNum %d",
+ _spPacketStates.fileOffset, _spPacketStates.leftChunkNum);
+ return -__LINE__;
+ }
+
+ int thisLen = (_spPacketStates.leftTransLen > V3_DOWNLOAD_MEM_SIZE)
+ ? V3_DOWNLOAD_MEM_SIZE : _spPacketStates.leftTransLen;
+ //get all leftdata if left sz small than V3_DOWNLOAD_SPARE_SZ
+ if (_spPacketStates.leftTransLen <= thisLen + V3_DOWNLOAD_SPARE_SZ) {
+ thisLen = _spPacketStates.leftTransLen;
+ }
+ if (_spPacketStates.fileOffset + thisLen > _spPacketStates.imgTotalLen) {
+ sperr("Exception, fileOffset 0x%llx + thisLen %x > total %llx\n",
+ _spPacketStates.fileOffset , thisLen , _spPacketStates.imgTotalLen);
+ return -__LINE__;
+ }
+
+ *dataSize = thisLen;
+ return 0;
+}
+
+static int check_chunk_info(const chunk_header_t* chunk, unsigned* pDataLen, unsigned* pFlashAddr, unsigned* fillVal)
+{
+ unsigned chunkDataLen = 0;
+ unsigned nextFlashAddr = 0;//update flash addr for next write
+
+ nextFlashAddr = chunkDataLen = chunk->chunk_sz * _spPacketStates.sparseBlkSz;
+ switch (chunk->chunk_type)
+ {
+ case CHUNK_TYPE_RAW:
+ {
+ if (CHUNK_HEAD_SIZE + chunkDataLen != chunk->total_sz) {
+ sperr("sparse: bad chunk size: head 0x%x + data 0x%x != total 0x%x\n",
+ (unsigned)CHUNK_HEAD_SIZE, chunkDataLen, chunk->total_sz);
+ return -__LINE__;
+ }
+ }break;
+ case CHUNK_TYPE_DONT_CARE:
+ {
+ if (CHUNK_HEAD_SIZE != chunk->total_sz) {
+ sperr("bogus DONT CARE chunk\n");
+ return -__LINE__;
+ }
+ chunkDataLen = 0;
+ }break;
+ case CHUNK_TYPE_FILL:
+ {
+ if (CHUNK_HEAD_SIZE + 4 != chunk->total_sz) {
+ sperr("error FILL chunk\n");
+ return -__LINE__;
+ }
+ const int fillFieldLen = 4;
+ if (fillVal) *fillVal = *(unsigned*)(chunk+1);
+ chunkDataLen = fillFieldLen;
+ }break;
+ case CHUNK_TYPE_CRC32:
+ sperr("CHUNK_TYPE_CRC32 unsupported yet!\n");
+ return -__LINE__;
+ default:
+ sperr("unknown chunk ID 0x%x at %p, leftid %d\n", chunk->chunk_type, chunk,
+ _spPacketStates.leftChunkNum);
+ return -__LINE__;
+ }
+
+ if (pDataLen) *pDataLen = chunkDataLen;
+ if (pFlashAddr) *pFlashAddr = nextFlashAddr;
+ return 0;
+}
+
+static int simg2img_fill_chunk_write(const char* partName, int fillLen, const unsigned* pFillVal, int64_t flashAddr)
+{
+ const int BufSz = 256*1024;//heard from LarsonJ, 128K is max burst in emmc control read/write
+ u8* fillBuf = (u8*)pFillVal + sizeof(unsigned) + CHUNK_HEAD_SIZE;//fill trunk data format[4bytes body + nextDownInf]
+ const unsigned fillVal = *pFillVal;
+ int needFill = 1;
+
+ if (v3tool_is_flash_erased()) {
+ switch (store_get_type()) {
+ case BOOT_EMMC:
+ case BOOT_SD:
+ needFill = (fillVal != 0);
+ break;
+
+ case BOOT_NAND_NFTL:
+ needFill = (fillVal != 0XFFFFFFFFU);
+ break;
+
+ default: FBS_EXIT(_ACK, "unsupported boot dev %d\n", store_get_type());
+ }
+ } else {/* always need fill when flash NOT erased */}
+ //for, emmc, if fillVal is 0, then needFill = false if "disk_inital > 0"
+ if (!needFill) return 0;
+
+ int LeftDataLen = fillLen;
+ int i = 0;
+ const int szFill = min(BufSz, fillLen);
+ unsigned* tmpFill = (unsigned*)fillBuf;
+ //spmsg("Fill start 0x%llx by value 0x%x\n", flashAddr, fillVal);
+ for (; i < szFill; i += 4) {
+ *tmpFill++ = fillVal;
+ }
+ while (LeftDataLen >0) {
+ const unsigned thisWriteLen = min(LeftDataLen, BufSz);
+ FB_DBG("fill off/sz/val 0x%08llx %x %x\n", flashAddr, thisWriteLen, fillVal);
+ int ret = store_logic_write(partName, flashAddr, thisWriteLen, fillBuf);
+ if (ret) {
+ sperr("FILL_CHUNK:Want write 0x%x Bytes, but failed\n", thisWriteLen);
+ return -__LINE__;
+ }
+
+ LeftDataLen -= thisWriteLen;
+ flashAddr += thisWriteLen;
+ }
+
+ return 0;
+}
+
+
+//v3tool_simg2img_write_img called after transfer (and checksum) ok
+//Recevied data format: [file header] + [chunk info] or [chunk body >=0] + [next chunk info]
+// <==> <[file header]> + <[chunkBody]> + <[nextChunkInfo]>
+// //has [file header] if first download
+// //[chunkBody] size 0 if first download or CHUNK_TYPE_DONT_CARE
+// //has [nextChunkInfo] except that
+// last chunk or [chunkBody] > (V3_DOWNLOAD_MEM_SIZE + V3_DOWNLOAD_SPARE_SZ)
+// code part 1: check if [file header]
+// code part 2: dispose chunk body
+// code part 3: dispose next chunk info for next download
+//update global var: _spPacketStates.[fileOffset, leftTransLen, leftChunkNum]
+//_spPacketStates.chunkInfo: chunk info for rx chunk body
+// nextDownInf: chunk info for next download
+int v3tool_simg2img_write_img(const UsbDownInf* downInf, const ImgDownloadPara* downPara)
+{
+ char* dataBuf = downInf->dataBuf;
+ int dataSize = downInf->dataSize;
+ const chunk_header_t* nextDownInf = NULL;
+ bool hasFileHeader = false;
+ bool hasChunkBody = true;
+ bool hasNextChunkInfo = true;//nextChunkInfo
+
+ //update globals not affected by rx data format
+ _spPacketStates.fileOffset += dataSize;
+ _spPacketStates.leftTransLen -= dataSize;
+
+ hasFileHeader = !_spPacketStates.sparseBlkSz && !_spPacketStates.pktHeadLen;
+ if (hasFileHeader) //code part 1
+ {
+ hasChunkBody = false;
+ hasNextChunkInfo = true;
+ if ( !_simg_probe(dataBuf, dataSize) )
+ FBS_EXIT(_ACK, "err sparse img header");
+
+ if (dataSize != FILE_HEAD_SIZE + CHUNK_HEAD_SIZE) {
+ sperr("Excep:first download sz need %d, but rx %d\n", (int)(FILE_HEAD_SIZE + CHUNK_HEAD_SIZE), dataSize);
+ return -__LINE__;
+ }
+
+ //2,
+ sparse_header_t *header = (sparse_header_t*) dataBuf;
+ _spPacketStates.leftChunkNum = header->total_chunks - 1;//how many chunkinfo not parsed
+ _spPacketStates.pktHeadLen = header->file_hdr_sz;
+ _spPacketStates.sparseBlkSz = header->blk_sz;//often 4k
+ spmsg("totalChunkNum %d, fileHeadSz 0x%x, chunkHeadSz 0x%zx, blk 0x%x\n", _spPacketStates.leftChunkNum + 1,
+ _spPacketStates.pktHeadLen, CHUNK_HEAD_SIZE, _spPacketStates.sparseBlkSz);
+
+ //3,
+ memcpy(_spPacketStates.chunkInfoBackAddr, header, FILE_HEAD_SIZE);
+ _spPacketStates.chunkInfoBackAddr =
+ (chunk_header_t*)((sparse_header_t*)(_spPacketStates.chunkInfoBackAddr) + 1);
+ dataBuf += FILE_HEAD_SIZE;//to make same as other rx data format
+ dataSize -= FILE_HEAD_SIZE;
+ }
+
+ const bool lastChunk = !_spPacketStates.leftChunkNum;
+ if (!hasFileHeader)
+ {
+ if (lastChunk) {//img ended
+ hasNextChunkInfo = false;
+ spmsg("last chunk\n");
+ /*return 0;*/
+ }
+ if ( _spPacketStates.leftTransLen ) {//only data body
+ hasNextChunkInfo = false;
+ //spmsg("big chunk left 0x%llx\n", _spPacketStates.leftTransLen);
+ } else {
+ _spPacketStates.leftChunkNum -= 1;
+ }
+ }
+
+ if (hasNextChunkInfo) dataSize -= CHUNK_HEAD_SIZE;
+ if (hasChunkBody)
+ {
+ const chunk_header_t* pChunk = _spPacketStates.chunkInfo;//this download info
+ const char* part = downPara->commonInf.partName;
+ int64_t flashAddr = _spPacketStates.nextFlashAddr + downPara->commonInf.partStartOff;
+ unsigned flashWrLen = dataSize;
+ const unsigned chunkFlashSpace = pChunk->chunk_sz * _spPacketStates.sparseBlkSz;;
+
+ //spmsg("chunkInfo %p, %x\n", pChunk, pChunk->chunk_type);
+ const unsigned chunkType = pChunk->chunk_type;
+ if (CHUNK_TYPE_RAW == chunkType) {
+ FB_DBG("raw wr: off/sz 0x%08llx flashWrLen %x\n", flashAddr, flashWrLen);
+ if (store_logic_write(part, flashAddr, flashWrLen, dataBuf)) {
+ sperr("Fail in flash raw trunk\n");
+ return -__LINE__;
+ }
+ _spPacketStates.nextFlashAddr += dataSize;
+ } else if (CHUNK_TYPE_FILL == chunkType) {
+ if ( 4 != dataSize ) {
+ sperr("fill chunk but dataSize(%d) != 4\n", dataSize);
+ return -__LINE__;
+ }
+ const unsigned* fillVal = (unsigned*)dataBuf;
+ FB_DBG("fill wr: off/sz 0x%08llx flashWrLen %x\n", _spPacketStates.nextFlashAddr, chunkFlashSpace);
+ if (simg2img_fill_chunk_write((char*)part, chunkFlashSpace, fillVal, flashAddr)) {
+ sperr("Fail in fill fill-chunk\n");
+ return -__LINE__;
+ }
+ _spPacketStates.nextFlashAddr += chunkFlashSpace;
+ } else if (CHUNK_TYPE_DONT_CARE == chunkType) {
+ if (dataSize) {
+ sperr("DONT_CARE trunk sz %x err, should be 0\n", dataSize);
+ return -__LINE__;
+ }
+ FB_DBG("donnot care: off/sz 0x%08llx flashWrLen", _spPacketStates.nextFlashAddr, chunkFlashSpace);
+ _spPacketStates.nextFlashAddr += chunkFlashSpace;
+ } else {
+ sperr("chunk(%x) should not be here", chunkType);
+ return -__LINE__;
+ }
+ }
+
+ //just update for next download, not doing flash writing even don't care trunk
+ if (hasNextChunkInfo)
+ {
+ nextDownInf = (chunk_header_t*)(dataBuf + dataSize);
+ _spPacketStates.chunkInfo = _spPacketStates.chunkInfoBackAddr;
+ memcpy(_spPacketStates.chunkInfoBackAddr++, nextDownInf, CHUNK_HEAD_SIZE);
+ //spmsg("back chunkInfo 0x%p, next %p, %x\n", _spPacketStates.chunkInfo, nextDownInf, _spPacketStates.chunkInfo->chunk_type);
+
+ unsigned chunkDataLen = 0;
+ if (check_chunk_info(nextDownInf, &chunkDataLen, NULL, NULL)) {
+ sperr("Fail parse next chunk header\n");
+ return -__LINE__;
+ }
+ _spPacketStates.leftTransLen = chunkDataLen;
+ if (_spPacketStates.fileOffset + chunkDataLen < _spPacketStates.imgTotalLen) {
+ _spPacketStates.leftTransLen += CHUNK_HEAD_SIZE;
+ }
+ //spmsg("update leftTransLen 0x%llx\n", _spPacketStates.leftTransLen);
+ }
+
+ return 0;
+}
+
+int v3tool_simg2img_verify_img(sha1_context* ctx, const char* partName, int64_t partBase)
+{
+ const sparse_header_t *header = (sparse_header_t*)V3_DOWNLOAD_VERIFY_INFO;
+ const int nChunk = header->total_chunks;
+ const unsigned vryBuffLen = (1<<20);//small buffer to reply while verify long
+ unsigned char* dataBuf = (unsigned char*)V3_DOWNLOAD_MEM_BASE;
+ unsigned chunkDataLen = 0;
+ unsigned long timePeriod = 0;
+ const chunk_header_t* backInf = (chunk_header_t*)(header + 1);
+ int ret = -__LINE__;
+
+ static int _iChunk = 0;
+ static int64_t _partOffset = 0;
+ static unsigned long _lastReportTick = 0;
+ static unsigned _dataChunkLeft = 0;//initial value or chunk verified end
+
+ if (SP_DOWNLOAD_OK == _downloadState) {//first time
+ _iChunk = 0;
+ _partOffset = partBase;
+ _dataChunkLeft = 0;
+ _downloadState = SP_VERIFY_ING;
+ if ( !_simg_probe((char*)header, FILE_HEAD_SIZE) ) {
+ sperr("err backup header\n");
+ return -__LINE__;
+ }
+ sha1_update(ctx, (u8*)header, FILE_HEAD_SIZE);
+ _lastReportTick = get_timer(0);
+ v3tool_media_set_free(NULL);
+ FB_DBG("partBase 0x%llx\n", partBase);
+ } else {
+ backInf += _iChunk;
+ }
+ for ( ; _iChunk < nChunk; ++_iChunk, ++backInf )
+ {
+ if (!_dataChunkLeft) sha1_update(ctx, (u8*)backInf, CHUNK_HEAD_SIZE);
+ const int64_t flashSpace = backInf->chunk_sz * _spPacketStates.sparseBlkSz;
+ switch (backInf->chunk_type)
+ {
+ case CHUNK_TYPE_RAW:
+ {
+ chunkDataLen = flashSpace;
+ if (CHUNK_HEAD_SIZE + chunkDataLen != backInf->total_sz) {
+ sperr("sparse: bad chunk size: head 0x%x + data 0x%x != total 0x%x\n",
+ (unsigned)CHUNK_HEAD_SIZE, chunkDataLen, backInf->total_sz);
+ goto _verify_end;
+ }
+ }break;
+ case CHUNK_TYPE_DONT_CARE:
+ {
+ if (CHUNK_HEAD_SIZE != backInf->total_sz) {
+ sperr("bogus DONT CARE chunk\n");
+ goto _verify_end;
+ }
+ chunkDataLen = 0;
+ }break;
+ case CHUNK_TYPE_FILL:
+ {
+ if (CHUNK_HEAD_SIZE + 4 != backInf->total_sz) {
+ sperr("error FILL chunk\n");
+ goto _verify_end;
+ }
+ //spmsg("fill chunk start 0x%llx\n", _partOffset);
+ const int fillFieldLen = 4;
+ chunkDataLen = fillFieldLen;
+ }break;
+ case CHUNK_TYPE_CRC32:
+ sperr("CHUNK_TYPE_CRC32 unsupported yet!\n");
+ goto _verify_end;
+ default:
+ sperr("unknown chunk ID 0x%x at %p, leftid %d\n", backInf->chunk_type, backInf, _iChunk);
+ goto _verify_end;
+ }
+ if (!_dataChunkLeft)_dataChunkLeft = chunkDataLen;
+ int64_t flashAddr = _partOffset + chunkDataLen - _dataChunkLeft;
+ while ( _dataChunkLeft ) {
+ const int thisLen = min(vryBuffLen, _dataChunkLeft);
+ FB_DBG("rd chunk %x: off/sz 0x%08llx %x\n", backInf->chunk_type, flashAddr, thisLen);
+ if (store_logic_read(partName, flashAddr, thisLen, dataBuf)) {
+ sperr("Fail in read storage for verify\n");
+ goto _verify_end;
+ }
+ sha1_update(ctx, dataBuf, thisLen);
+
+ _dataChunkLeft -= thisLen;
+ flashAddr += thisLen;
+
+ if (_dataChunkLeft) {
+ timePeriod = get_timer(_lastReportTick);
+ if (timePeriod >= 2*1000) {//2Sec
+ _lastReportTick += timePeriod;
+ FB_DBG("cost %lu >= 2s\n", timePeriod);
+ FB_DBG("xx[%d]flashAddr 0x%llx, leftLen %x, thisLen %x\n",
+ _iChunk, flashAddr, _dataChunkLeft, thisLen);
+ char info[64];
+ sprintf(info, "%04d / %04d Chunks", _iChunk + 1, nChunk);
+ v3tool_media_set_busy(info);
+ return 0;
+ }
+ }
+ }
+ _partOffset += flashSpace;
+ }
+
+ ret = 0;
+_verify_end:
+ v3tool_media_set_free(NULL);
+ _iChunk = 0;
+ spmsg("verify end\n");
+ return ret;
+}
+
diff --git a/drivers/usb/gadget/v3_burning/v3_usb_tool/Makefile b/drivers/usb/gadget/v3_burning/v3_usb_tool/Makefile
new file mode 100644
index 0000000..5853ef1
--- /dev/null
+++ b/drivers/usb/gadget/v3_burning/v3_usb_tool/Makefile
@@ -0,0 +1,27 @@
+#
+# (C) Copyright 2000-2007
+# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
+#
+# See file CREDITS for list of people who contributed to this
+# project.
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; either version 2 of
+# the License, or (at your option) any later version.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+# MA 02111-1307 USA
+#
+obj-$(CONFIG_AML_V3_USB_TOOl) += aml_v3_burn.o
+aml_v3_burn-y = aml_dnl.o
+aml_v3_burn-y += f_v3_usb_tool.o
+aml_v3_burn-y += cmd_aml_dnl.o
+
diff --git a/drivers/usb/gadget/v3_burning/v3_usb_tool/aml_dnl.c b/drivers/usb/gadget/v3_burning/v3_usb_tool/aml_dnl.c
new file mode 100644
index 0000000..dc43ba0
--- /dev/null
+++ b/drivers/usb/gadget/v3_burning/v3_usb_tool/aml_dnl.c
@@ -0,0 +1,265 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <malloc.h>
+
+#include <mmc.h>
+#include <part.h>
+#include <usb.h>
+
+#include <g_dnl.h>
+#include <usb_mass_storage.h>
+#include <dfu.h>
+#include <thor.h>
+
+#include <env_callback.h>
+
+#include "../../gadget_chips.h"
+///#include "composite.c" //not need include twice
+
+/*
+ * One needs to define the following:
+ * CONFIG_USB_GADGET_VENDOR_NUM
+ * CONFIG_USB_GADGET_PRODUCT_NUM
+ * CONFIG_USB_GADGET_MANUFACTURER
+ * at e.g. ./configs/<board>_defconfig
+ */
+//#define CONFIG_USB_GADGET_VENDOR_NUM 0x1b8e
+//#define CONFIG_USB_GADGET_PRODUCT_NUM 0xc004
+//#define CONFIG_USB_GADGET_MANUFACTURER "Amlogic Inc"
+
+#define STRING_MANUFACTURER 25
+#define STRING_PRODUCT 2
+/* Index of String Descriptor describing this configuration */
+#define STRING_USBDOWN 2
+/* Index of String serial */
+#define STRING_SERIAL 3
+#define MAX_STRING_SERIAL 256
+/* Number of supported configurations */
+#define CONFIGURATION_NUMBER 1
+
+#define DRIVER_VERSION "aml dnl 1.0"
+
+static const char product[] = "DNL";
+static char g_dnl_serial[MAX_STRING_SERIAL];
+static const char manufacturer[] = CONFIG_USB_GADGET_MANUFACTURER;
+
+static struct usb_device_descriptor device_desc = {
+ .bLength = sizeof device_desc,
+ .bDescriptorType = USB_DT_DEVICE,
+
+ .bcdUSB = __constant_cpu_to_le16(0x0200),
+ .bDeviceClass = USB_CLASS_PER_INTERFACE,
+ .bDeviceSubClass = 0, /*0x02:CDC-modem , 0x00:CDC-serial*/
+
+ .idVendor = __constant_cpu_to_le16(CONFIG_USB_GADGET_VENDOR_NUM),
+ .idProduct = __constant_cpu_to_le16(CONFIG_USB_GADGET_PRODUCT_NUM),
+ /* .iProduct = DYNAMIC */
+ /* .iSerialNumber = DYNAMIC */
+ .bNumConfigurations = 1,
+};
+
+/*
+ * static strings, in UTF-8
+ * IDs for those strings are assigned dynamically at g_dnl_bind()
+ */
+static struct usb_string g_dnl_string_defs[] = {
+ {.s = manufacturer},
+ {.s = product},
+ {.s = g_dnl_serial},
+ { } /* end of list */
+};
+
+static struct usb_gadget_strings g_dnl_string_tab = {
+ .language = 0x0409, /* en-us */
+ .strings = g_dnl_string_defs,
+};
+
+static struct usb_gadget_strings *g_dnl_composite_strings[] = {
+ &g_dnl_string_tab,
+ NULL,
+};
+
+#include <amlogic/cpu_id.h>
+const char * get_usid_string(void)
+{
+ static char chipid_str[32];
+ unsigned char chipid[16];
+ int ret = get_chip_id(chipid, 16);
+ if ( ret ) {
+ printf("_get_chipid %d", ret);
+ return NULL;
+ }
+ char* buff = &chipid_str[0];
+ buff[0] = buff[24] = '\0';
+ int i = 0;
+ for (; i < 12; ++i) {
+ sprintf(buff, "%s%02x", buff, chipid[15-i]);
+ }
+ return buff;
+}
+
+static int g_dnl_unbind(struct usb_composite_dev *cdev)
+{
+ struct usb_gadget *gadget = cdev->gadget;
+
+ debug("%s: calling usb_gadget_disconnect for "
+ "controller '%s'\n", __func__, gadget->name);
+ usb_gadget_disconnect(gadget);
+
+ return 0;
+}
+
+static inline struct g_dnl_bind_callback *g_dnl_bind_callback_first(void)
+{
+ return ll_entry_start(struct g_dnl_bind_callback,
+ g_dnl_bind_callbacks);
+}
+
+static inline struct g_dnl_bind_callback *g_dnl_bind_callback_end(void)
+{
+ return ll_entry_end(struct g_dnl_bind_callback,
+ g_dnl_bind_callbacks);
+}
+
+static int g_dnl_do_config(struct usb_configuration *c)
+{
+ const char *s = c->cdev->driver->name;
+ struct g_dnl_bind_callback *callback = g_dnl_bind_callback_first();
+
+ debug("%s: configuration: 0x%p composite dev: 0x%p\n",
+ __func__, c, c->cdev);
+
+ for (; callback != g_dnl_bind_callback_end(); callback++)
+ if (!strcmp(s, callback->usb_function_name))
+ return callback->fptr(c);
+ return -ENODEV;
+}
+
+static int g_dnl_config_register(struct usb_composite_dev *cdev)
+{
+ struct usb_configuration *config;
+ const char *name = "usb_dnload";
+
+ config = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*config));
+ if (!config)
+ return -ENOMEM;
+
+ memset(config, 0, sizeof(*config));
+
+ config->label = name;
+ config->bmAttributes = USB_CONFIG_ATT_ONE | USB_CONFIG_ATT_SELFPOWER;
+ config->bConfigurationValue = CONFIGURATION_NUMBER;
+ config->iConfiguration = STRING_USBDOWN;
+ config->bind = g_dnl_do_config;
+
+ return usb_add_config(cdev, config);
+}
+
+static int g_dnl_get_bcd_device_number(struct usb_composite_dev *cdev)
+{
+ struct usb_gadget *gadget = cdev->gadget;
+ int gcnum;
+
+ gcnum = usb_gadget_controller_number(gadget);
+ if (gcnum > 0)
+ gcnum += 0x200;
+
+ /*return g_dnl_get_board_bcd_device_number(gcnum);*/
+ return gcnum;
+}
+
+static int g_dnl_bind(struct usb_composite_dev *cdev)
+{
+ struct usb_gadget *gadget = cdev->gadget;
+ int id, ret;
+ int gcnum;
+
+ debug("%s: gadget: 0x%p cdev: 0x%p\n", __func__, gadget, cdev);
+
+ id = usb_string_id(cdev);
+
+ if (id < 0)
+ return id;
+ g_dnl_string_defs[0].id = id;
+ device_desc.iManufacturer = id;
+
+ id = usb_string_id(cdev);
+ if (id < 0)
+ return id;
+
+ g_dnl_string_defs[1].id = id;
+ device_desc.iProduct = id;
+
+ /*g_dnl_bind_fixup(&device_desc, cdev->driver->name);*/
+
+ id = usb_string_id(cdev);
+ if (id < 0)
+ return id;
+ g_dnl_string_defs[2].id = id;
+ device_desc.iSerialNumber = id;
+
+ const char* s = get_usid_string();
+ if (s) strncpy(g_dnl_serial, s, strlen(s));
+ else printf("Fail in get chipid\n");
+
+ ret = g_dnl_config_register(cdev);
+ if (ret)
+ goto error;
+
+ gcnum = g_dnl_get_bcd_device_number(cdev);
+ if (gcnum >= 0)
+ device_desc.bcdDevice = cpu_to_le16(gcnum);
+ else {
+ debug("%s: controller '%s' not recognized\n",
+ __func__, gadget->name);
+ device_desc.bcdDevice = __constant_cpu_to_le16(0x9999);
+ }
+
+ debug("%s: calling usb_gadget_connect for "
+ "controller '%s'\n", __func__, gadget->name);
+ usb_gadget_connect(gadget);
+
+ return 0;
+
+ error:
+ g_dnl_unbind(cdev);
+ return -ENOMEM;
+}
+
+static struct usb_composite_driver g_dnl_driver = {
+ .name = NULL,
+ .dev = &device_desc,
+ .strings = g_dnl_composite_strings,
+
+ .bind = g_dnl_bind,
+ .unbind = g_dnl_unbind,
+};
+
+/*
+ * NOTICE:
+ * Registering via USB function name won't be necessary after rewriting
+ * g_dnl to support multiple USB functions.
+ */
+int aml_dnl_register(const char *name)
+{
+ int ret;
+
+ debug("%s: g_dnl_driver.name = %s\n", __func__, name);
+ g_dnl_driver.name = name;
+
+ ret = usb_composite_register(&g_dnl_driver);
+ if (ret) {
+ printf("%s: failed!, error: %d\n", __func__, ret);
+ return ret;
+ }
+ return 0;
+}
+
+void aml_dnl_unregister(void)
+{
+ usb_composite_unregister(&g_dnl_driver);
+}
diff --git a/drivers/usb/gadget/v3_burning/v3_usb_tool/cmd_aml_dnl.c b/drivers/usb/gadget/v3_burning/v3_usb_tool/cmd_aml_dnl.c
new file mode 100644
index 0000000..959a116
--- /dev/null
+++ b/drivers/usb/gadget/v3_burning/v3_usb_tool/cmd_aml_dnl.c
@@ -0,0 +1,145 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <command.h>
+#include <console.h>
+#include <g_dnl.h>
+#include <asm/io.h>
+#include <asm/arch/register.h>
+
+int optimus_erase_bootloader(const char* extBootDev);
+extern int aml_dnl_register(const char *name);
+extern void aml_dnl_unregister(void);
+#define SOF_WAIT_TIME_MIN 500 //400ms for wait sof, need more than wcp
+
+extern unsigned int _sofintr_not_occur;
+unsigned int adnl_enum_timeout;
+static unsigned int time_out_val;
+unsigned int adnl_identify_timeout = 0;
+static unsigned int time_out_wait_sof;
+#if (defined CONFIG_USB_DEVICE_V2)
+extern unsigned int _sofintr;
+extern unsigned curTime_sof;
+#endif
+
+static void usb_parameter_init(int time_out)
+{
+ adnl_enum_timeout = adnl_identify_timeout = 0;//clear every time
+
+ if (time_out) {
+ time_out_val = time_out;
+ adnl_enum_timeout = get_timer(0);/* clear utimer */
+ }
+
+ time_out_wait_sof =
+ (SOF_WAIT_TIME_MIN * 2 > time_out_val) ? SOF_WAIT_TIME_MIN : (time_out_val >> 1);
+ _sofintr_not_occur = 1;
+ return;
+}
+
+#ifdef CONFIG_USB_GADGET_CRG
+extern int phy_num;
+#endif
+
+int aml_v3_usbburning(unsigned timeout, unsigned pcToolWaitTime)
+{
+ int ret;
+
+#ifdef CONFIG_USB_GADGET_CRG
+ //printf("poc:0x%x\n", readl(SYSCTRL_POC));
+ phy_num = (readl(SYSCTRL_POC)>>1) & 0x1U;
+#endif
+ usb_parameter_init(timeout);
+
+ ret = aml_dnl_register("usb_dnl_amlogic");
+ if (ret)
+ return ret;
+
+#ifdef CONFIG_USB_GADGET_CRG
+ if (!g_dnl_board_usb_cable_connected()) {
+ puts("\rUSB cable not detected.\n" \
+ "Command exit.\n");
+ ret = CMD_RET_FAILURE;
+ return ret;
+ }
+#endif
+
+ while (1) {
+ if (ctrlc()) break;
+
+ if (adnl_enum_timeout) {
+ unsigned curTime = get_timer(adnl_enum_timeout);
+ if (curTime > time_out_wait_sof && _sofintr_not_occur) {
+ printf("noSof\n");
+ dwc_otg_power_off_phy_fb();
+ aml_dnl_unregister();
+ return 2;
+ }
+ if (curTime > time_out_val) {
+ dwc_otg_power_off_phy_fb();
+ aml_dnl_unregister();
+ printf("Try connect time out %u, %u, %u\n",
+ curTime, time_out_val, adnl_enum_timeout);
+ return 2;
+ }
+ }
+
+ if (adnl_identify_timeout && pcToolWaitTime) {
+ const unsigned waitIdentifyTime = get_timer(adnl_identify_timeout);
+ if (waitIdentifyTime > pcToolWaitTime) {
+ printf("waitIdentifyTime(%u) > timeout(%u)\n", waitIdentifyTime, pcToolWaitTime);
+ pcToolWaitTime = 0;//don't re-enter even plug-out and plug-in
+ adnl_identify_timeout = 0;
+ aml_dnl_unregister();
+ return __LINE__;
+ }
+ }
+
+#if (defined CONFIG_USB_DEVICE_V2) && !defined(CONFIG_USB_GADGET_CRG)
+ if ((get_timer(curTime_sof) > 0x200) && (_sofintr)) {
+ _sofintr = 0;
+ dwc_otg_power_off_phy_fb();
+ }
+#endif// #if (defined CONFIG_USB_DEVICE_V2) && !defined(CONFIG_USB_GADGET_CRG)
+ usb_gadget_handle_interrupts(0);
+ }
+
+ aml_dnl_unregister();
+ return CMD_RET_SUCCESS;
+}
+
+#ifndef CONFIG_AML_NO_USB_MODULE
+static int do_aml_DNL(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ unsigned timeout = (2 <= argc) ? simple_strtoul(argv[1], NULL, 0) : 0;
+ unsigned pcToolWaitTime = (3 <= argc) ? simple_strtoul(argv[2], NULL, 0) : 0;
+
+ return aml_v3_usbburning(timeout, pcToolWaitTime);
+}
+#else
+static int do_aml_DNL(cmd_tbl_t *cmdtp, int flag, int argc, char *const argv[])
+{
+ unsigned timeout = (2 <= argc) ? simple_strtoul(argv[1], NULL, 0) : 0;
+
+ optimus_erase_bootloader(timeout ? "usb-timeout" : "usb");//skip to bl1 usb rom driver
+
+#ifdef CONFIG_AML_REBOOT
+ run_command("reboot", 0);
+ udelay(2*1000*1000);
+#endif//#ifdef CONFIG_AML_REBOOT
+ printf("call reset as reboot not work\n");//should not be reach here
+ do_reset(NULL, 0, 0, NULL);//call reset if reboot undefined
+
+ return CMD_RET_SUCCESS;
+}
+#endif// #ifndef CONFIG_AML_NO_USB_MODULE
+
+U_BOOT_CMD(
+ adnl, 3, 0, do_aml_DNL,
+ "use Amlogic DNL protocol",
+ " [timeout_enum] [timeout_identify]"
+);
+
diff --git a/drivers/usb/gadget/v3_burning/v3_usb_tool/f_v3_usb_tool.c b/drivers/usb/gadget/v3_burning/v3_usb_tool/f_v3_usb_tool.c
new file mode 100644
index 0000000..6327599
--- /dev/null
+++ b/drivers/usb/gadget/v3_burning/v3_usb_tool/f_v3_usb_tool.c
@@ -0,0 +1,1281 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+//declares from f_fastboot.c
+#include <config.h>
+#include <common.h>
+#include <errno.h>
+#include <malloc.h>
+#include <linux/usb/ch9.h>
+#include <linux/usb/gadget.h>
+#include <linux/usb/composite.h>
+#include <linux/compiler.h>
+#include <version.h>
+#include <g_dnl.h>
+#include <asm/arch/cpu.h>
+#include <partition_table.h>
+#include <android_image.h>
+#include <image.h>
+#include <amlogic/cpu_id.h>
+#include "../include/v3_tool_def.h"
+DECLARE_GLOBAL_DATA_PTR;
+static void cb_aml_media_write(struct usb_ep *ep, struct usb_request *req);
+static void cb_aml_media_read(struct usb_ep *outep, struct usb_request *outreq);
+static void cb_oem_cmd(struct usb_ep *ep, struct usb_request *req);
+
+static const char* const _def_norisk_cmd_list_[] = {"printenv","help","echo",NULL};
+extern const char * const white_list_adnl_cmds[0] __attribute__((weak, alias("_def_norisk_cmd_list_")));
+
+#define DNL_PROTOCOL_VERSION "0.1"
+#define FASTBOOT_INTERFACE_CLASS 0xff
+#define FASTBOOT_INTERFACE_SUB_CLASS 0x42
+#define FASTBOOT_INTERFACE_PROTOCOL 0x03
+
+#define DEVICE_PRODUCT "amlogic"
+#define DEVICE_SERIAL "1234567890"
+
+#define CONFIG_USB_FASTBOOT_BUF_ADDR V3_DOWNLOAD_EP_DATA
+
+/* The 64 defined bytes plus \0 */
+
+static struct {
+ int hadDown; //already downloaded to mem
+ unsigned imgSize; //size of dtb.img
+}_memDtbImg[2];
+
+struct f_fastboot {
+ struct usb_function usb_function;
+
+ /* IN/OUT EP's and corresponding requests */
+ struct usb_ep *in_ep, *out_ep;
+ struct usb_request *in_req, *out_req;
+};
+
+static inline struct f_fastboot *func_to_fastboot(struct usb_function *f)
+{
+ return container_of(f, struct f_fastboot, usb_function);
+}
+
+static struct f_fastboot *fastboot_func;
+
+static struct usb_interface_descriptor interface_desc = {
+ .bLength = USB_DT_INTERFACE_SIZE,
+ .bDescriptorType = USB_DT_INTERFACE,
+ .bInterfaceNumber = 0x00,
+ .bAlternateSetting = 0x00,
+ .bNumEndpoints = 0x02,
+ .bInterfaceClass = FASTBOOT_INTERFACE_CLASS,
+ .bInterfaceSubClass = FASTBOOT_INTERFACE_SUB_CLASS,
+ .bInterfaceProtocol = FASTBOOT_INTERFACE_PROTOCOL,
+};
+
+static struct usb_endpoint_descriptor fs_ep_in = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = cpu_to_le16(64),
+};
+
+static struct usb_endpoint_descriptor fs_ep_out = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_OUT,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = cpu_to_le16(64),
+};
+
+static struct usb_endpoint_descriptor hs_ep_in = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_IN,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = cpu_to_le16(512),
+};
+
+static struct usb_endpoint_descriptor hs_ep_out = {
+ .bLength = USB_DT_ENDPOINT_SIZE,
+ .bDescriptorType = USB_DT_ENDPOINT,
+ .bEndpointAddress = USB_DIR_OUT,
+ .bmAttributes = USB_ENDPOINT_XFER_BULK,
+ .wMaxPacketSize = cpu_to_le16(512),
+};
+
+
+static struct usb_descriptor_header *fb_fs_function[] = {
+ (struct usb_descriptor_header *)&interface_desc,
+ (struct usb_descriptor_header *)&fs_ep_in,
+ (struct usb_descriptor_header *)&fs_ep_out,
+};
+
+static struct usb_descriptor_header *fb_hs_function[] = {
+ (struct usb_descriptor_header *)&interface_desc,
+ (struct usb_descriptor_header *)&hs_ep_in,
+ (struct usb_descriptor_header *)&hs_ep_out,
+ NULL,
+};
+
+static struct usb_endpoint_descriptor *
+fb_ep_desc(struct usb_gadget *g, struct usb_endpoint_descriptor *fs,
+ struct usb_endpoint_descriptor *hs)
+{
+ if (gadget_is_dualspeed(g) && g->speed == USB_SPEED_HIGH)
+ return hs;
+ return fs;
+}
+
+/*
+ * static strings, in UTF-8
+ */
+static const char fastboot_name[] = "Amlogic DNL";
+
+static struct usb_string fastboot_string_defs[] = {
+ [0].s = fastboot_name,
+ { } /* end of list */
+};
+
+static struct usb_gadget_strings stringtab_fastboot = {
+ .language = 0x0409, /* en-us */
+ .strings = fastboot_string_defs,
+};
+
+static struct usb_gadget_strings *fastboot_strings[] = {
+ &stringtab_fastboot,
+ NULL,
+};
+
+#if 0
+#define DRAM_UBOOT_RESERVE 0x01000000
+static unsigned int ddr_size_usable(unsigned int addr_start)
+{
+ unsigned int ddr_size=0;
+ unsigned int free_size = 0;
+ int i;
+
+ for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
+ ddr_size += gd->bd->bi_dram[i].size;
+
+ free_size = (ddr_size - DRAM_UBOOT_RESERVE - addr_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_MEM_TOP_HIDE);
+#if defined CONFIG_FASTBOOT_MAX_DOWN_SIZE
+ if (free_size > CONFIG_FASTBOOT_MAX_DOWN_SIZE)
+ free_size = CONFIG_FASTBOOT_MAX_DOWN_SIZE;
+#endif
+ return free_size;
+}
+#endif
+
+static void rx_handler_command(struct usb_ep *ep, struct usb_request *req);
+
+static char response_str[RESPONSE_LEN + 1];
+
+static void fastboot_fail(const char *s)
+{
+ strncpy(response_str, "FAIL", 4);
+ if (s)strncat(response_str, s, RESPONSE_LEN - 4 - 1) ;
+}
+
+static void fastboot_okay(const char *s)
+{
+ strncpy(response_str, "OKAY", 4);
+ if (s)strncat(response_str, s, RESPONSE_LEN - 4 - 1) ;
+}
+
+static void fastboot_busy(const char* s)
+{
+ strncpy(response_str, "INFO", 4 + 1);//add terminated 0
+ if (s)strncat(response_str, s, RESPONSE_LEN - 4 - 1) ;
+}
+static int fastboot_is_busy(void)
+{
+ return !strncmp("INFO", response_str, strlen("INFO"));
+}
+
+//cb for bulk in_req->complete
+static void fastboot_complete(struct usb_ep *ep, struct usb_request *req)
+{
+ int status = req->status;
+
+ if ( fastboot_is_busy() && fastboot_func) {
+ struct usb_ep* out_ep = fastboot_func->out_ep;
+ struct usb_request* out_req = fastboot_func->out_req;
+ rx_handler_command(out_ep, out_req);
+ return;
+ }
+ if (!status)
+ return;
+ printf("status: %d ep '%s' trans: %d\n", status, ep->name, req->actual);
+}
+
+static int fastboot_bind(struct usb_configuration *c, struct usb_function *f)
+{
+ int id;
+ struct usb_gadget *gadget = c->cdev->gadget;
+ struct f_fastboot *f_fb = func_to_fastboot(f);
+
+ /* DYNAMIC interface numbers assignments */
+ id = usb_interface_id(c, f);
+ if (id < 0)
+ return id;
+
+ interface_desc.bInterfaceNumber = id;
+
+ id = usb_string_id(c->cdev);
+ if (id < 0)
+ return id;
+
+ fastboot_string_defs[0].id = id;
+ interface_desc.iInterface = id;
+
+ f_fb->in_ep = usb_ep_autoconfig(gadget, &fs_ep_in);
+ if (!f_fb->in_ep)
+ return -ENODEV;
+
+ f_fb->in_ep->driver_data = c->cdev;
+
+ f_fb->out_ep = usb_ep_autoconfig(gadget, &fs_ep_out);
+ if (!f_fb->out_ep)
+ return -ENODEV;
+
+ f_fb->out_ep->driver_data = c->cdev;
+
+ f->descriptors = fb_fs_function;
+
+ if (gadget_is_dualspeed(gadget)) {
+ /* Assume endpoint addresses are the same for both speeds */
+ hs_ep_in.bEndpointAddress = fs_ep_in.bEndpointAddress;
+ hs_ep_out.bEndpointAddress = fs_ep_out.bEndpointAddress;
+ /* copy HS descriptors */
+ f->hs_descriptors = fb_hs_function;
+ }
+
+ return 0;
+}
+
+static void fastboot_unbind(struct usb_configuration *c, struct usb_function *f)
+{
+ memset(fastboot_func, 0, sizeof(*fastboot_func));
+}
+
+static void fastboot_disable(struct usb_function *f)
+{
+ struct f_fastboot *f_fb = func_to_fastboot(f);
+
+ usb_ep_disable(f_fb->out_ep);
+ usb_ep_disable(f_fb->in_ep);
+
+ if (f_fb->out_req) {
+ usb_ep_free_request(f_fb->out_ep, f_fb->out_req);
+ f_fb->out_req = NULL;
+ }
+ if (f_fb->in_req) {
+ usb_ep_free_request(f_fb->in_ep, f_fb->in_req);
+ f_fb->in_req = NULL;
+ }
+}
+
+#define EP_CMD_LEN_MAX 256
+static char EP_CMD_BUF[EP_CMD_LEN_MAX*2];
+static struct usb_request *fastboot_start_ep(struct usb_ep *ep)
+{
+ struct usb_request *req;
+ const char* epName = ep->name;
+
+ req = usb_ep_alloc_request(ep, 0);
+ if (!req)
+ return NULL;
+
+ const int isBulkOut = strnlen(epName, 12) == strlen("ep1out");
+ /*req->length = EP_BUFFER_SIZE;*/
+ /*req->buf = isBulkOut ? (char*)V3_DOWNLOAD_EP_OUT : (char*)V3_DOWNLOAD_EP_IN;*/
+ req->buf = isBulkOut ? &EP_CMD_BUF[0] : &EP_CMD_BUF[EP_CMD_LEN_MAX];
+ req->length = EP_CMD_LEN_MAX;
+ FB_DBG("start %s EP, [%p]\n", isBulkOut ? "OUT" : "IN", req->buf);
+
+ memset(req->buf, 0, req->length);
+ return req;
+}
+
+extern unsigned int adnl_enum_timeout;
+extern unsigned int adnl_identify_timeout;
+
+static int fastboot_set_alt(struct usb_function *f,
+ unsigned interface, unsigned alt)
+{
+ int ret;
+ struct usb_composite_dev *cdev = f->config->cdev;
+ struct usb_gadget *gadget = cdev->gadget;
+ struct f_fastboot *f_fb = func_to_fastboot(f);
+ const struct usb_endpoint_descriptor *d;
+
+ debug("%s: func: %s intf: %d alt: %d\n",
+ __func__, f->name, interface, alt);
+
+ /* make sure we don't enable the ep twice */
+ d = fb_ep_desc(gadget, &fs_ep_out, &hs_ep_out);
+ ret = usb_ep_enable(f_fb->out_ep, d);
+ if (ret) {
+ puts("failed to enable out ep\n");
+ return ret;
+ }
+
+ f_fb->out_req = fastboot_start_ep(f_fb->out_ep);
+ if (!f_fb->out_req) {
+ puts("failed to alloc out req\n");
+ ret = -EINVAL;
+ goto err;
+ }
+ f_fb->out_req->complete = rx_handler_command;
+
+ d = fb_ep_desc(gadget, &fs_ep_in, &hs_ep_in);
+ ret = usb_ep_enable(f_fb->in_ep, d);
+ if (ret) {
+ puts("failed to enable in ep\n");
+ goto err;
+ }
+
+ f_fb->in_req = fastboot_start_ep(f_fb->in_ep);
+ if (!f_fb->in_req) {
+ puts("failed alloc req in\n");
+ ret = -EINVAL;
+ goto err;
+ }
+ f_fb->in_req->complete = fastboot_complete;
+
+ ret = usb_ep_queue(f_fb->out_ep, f_fb->out_req, 0);
+ if (ret)
+ goto err;
+
+ adnl_enum_timeout = 0;
+ adnl_identify_timeout = get_timer(0);
+
+ return 0;
+err:
+ fastboot_disable(f);
+ return ret;
+}
+
+static int fastboot_setup(struct usb_function *f,
+ const struct usb_ctrlrequest *ctrl)
+{
+ int value = -EOPNOTSUPP;
+ struct f_fastboot *f_fb = func_to_fastboot(f);
+
+ /* composite driver infrastructure handles everything; interface
+ * activation uses set_alt().
+ */
+ if (((ctrl->bRequestType & USB_RECIP_MASK) == USB_RECIP_ENDPOINT)
+ && (ctrl->bRequest == USB_REQ_CLEAR_FEATURE)
+ && (ctrl->wValue== USB_ENDPOINT_HALT)) {
+ switch (ctrl->wIndex & 0xfe) {
+ case USB_DIR_OUT:
+ value = ctrl->wLength;
+ usb_ep_clear_halt(f_fb->out_ep);
+ break;
+
+ case USB_DIR_IN:
+ value = ctrl->wLength;
+ usb_ep_clear_halt(f_fb->in_ep);
+ break;
+ default:
+ printf("unknown usb_ctrlrequest\n");
+ break;
+ }
+ }
+
+ return value;
+}
+
+static int fastboot_add(struct usb_configuration *c)
+{
+ struct f_fastboot *f_fb = fastboot_func;
+ int status;
+
+ if (!f_fb) {
+ f_fb = memalign(CONFIG_SYS_CACHELINE_SIZE, sizeof(*f_fb));
+ if (!f_fb)
+ return -ENOMEM;
+
+ fastboot_func = f_fb;
+ memset(f_fb, 0, sizeof(*f_fb));
+ }
+
+ f_fb->usb_function.name = "f_aml_dnl";
+ /*f_fb->usb_function.hs_descriptors = fb_runtime_descs;*/
+ f_fb->usb_function.bind = fastboot_bind;
+ f_fb->usb_function.unbind = fastboot_unbind;
+ f_fb->usb_function.set_alt = fastboot_set_alt;
+ f_fb->usb_function.disable = fastboot_disable;
+ f_fb->usb_function.strings = fastboot_strings;
+ f_fb->usb_function.setup = fastboot_setup;
+
+ status = usb_add_function(c, &f_fb->usb_function);
+ if (status) {
+ free(f_fb);
+ fastboot_func = f_fb;
+ }
+
+ return status;
+}
+DECLARE_GADGET_BIND_CALLBACK(usb_dnl_amlogic, fastboot_add);
+
+static int fastboot_tx_write(const char *buffer, unsigned int buffer_size)
+{
+ struct usb_request *in_req = fastboot_func->in_req;
+ int ret;
+
+ memcpy(in_req->buf, buffer, buffer_size);
+ in_req->length = buffer_size;
+ ret = usb_ep_queue(fastboot_func->in_ep, in_req, 0);
+ if (ret)
+ printf("Error %d on queue\n", ret);
+ return 0;
+}
+
+static int fastboot_tx_write_str(const char *buffer)
+{
+ return fastboot_tx_write(buffer, strlen(buffer));
+}
+
+static void compl_do_reset(struct usb_ep *ep, struct usb_request *req)
+{
+#ifndef CONFIG_USB_GADGET_CRG
+ f_dwc_otg_pullup(0);//disconnect before reboot/plugin to enhance pc compatibility
+#endif
+ udelay(2*1000*1000);
+ do_reset(NULL, 0, 0, NULL);
+}
+
+static void compl_do_reboot_bootloader(struct usb_ep *ep, struct usb_request *req)
+{
+ run_command("reboot bootloader", 0);
+}
+static void compl_do_reboot_bl1usb(struct usb_ep *ep, struct usb_request *req)
+{
+#ifndef CONFIG_USB_GADGET_CRG
+ f_dwc_otg_pullup(0);//disconnect before reboot/plugin to enhance pc compatibility
+#endif
+ udelay(2*1000*1000);
+ optimus_erase_bootloader("usb");//skip to bl1 usb rom driver
+
+#ifdef CONFIG_AML_REBOOT
+ run_command("reboot", 0);
+ udelay(2*1000*1000);
+#endif//#ifdef CONFIG_AML_REBOOT
+ printf("call reset as reboot not work\n");//should not be reach here
+ do_reset(NULL, 0, 0, NULL);//call reset if reboot undefined
+}
+
+static void cb_reboot(struct usb_ep *ep, struct usb_request *req)
+{
+ char *cmd = req->buf;
+
+ printf("cmd cb_reboot is %s\n", cmd);
+
+ void (*do_after_bulk_in)(struct usb_ep*, struct usb_request*) = NULL;
+ strsep(&cmd, "-");
+ if (!cmd) {
+ do_after_bulk_in = compl_do_reset;
+ } else if (!strcmp("bootloader", cmd)) {
+ do_after_bulk_in = compl_do_reboot_bootloader;
+ } else if (!strcmp("romusb", cmd)) {
+ do_after_bulk_in = compl_do_reboot_bl1usb;
+ } else {
+ fastboot_fail("unsupported reboot cmd");
+ fastboot_tx_write_str(response_str);
+ return;
+ }
+
+ printf("reboot subcmd %s\n", cmd);
+ fastboot_func->in_req->complete = do_after_bulk_in;
+ fastboot_tx_write_str("OKAY");
+}
+
+static int strcmp_l1(const char *s1, const char *s2)
+{
+ if (!s1 || !s2)
+ return -1;
+ return strncmp(s1, s2, strlen(s1));
+}
+
+static const char* getvar_list[] = {
+ "version", "serialno", "product", "erase-block-size", "secure",
+};
+static const char* getvar_list_ab[] = {
+ "version", "serialno", "product", "erase-block-size",
+ "secure", "slot-count", "slot-suffixes","current-slot",
+};
+static void cb_getvar(struct usb_ep *ep, struct usb_request *req)
+{
+ char *cmd = req->buf;
+ char cmdBuf[RESPONSE_LEN];
+ char* response = response_str;
+ size_t chars_left;
+ int replyLen = 0;
+
+ strcpy(response, "OKAY");
+ chars_left = sizeof(response_str) - strlen(response) - 1;
+
+ memcpy(cmdBuf, cmd, strnlen(cmd, RESPONSE_LEN-1)+1);
+ cmd = cmdBuf;
+ strsep(&cmd, ":");
+ printf("cb_getvar: %s\n", cmd);
+ if (!cmd) {
+ FBS_ERR(response, "FAILmissing var\n");
+ fastboot_tx_write_str(response);
+ return;
+ }
+ if (!strncmp(cmd, "all", 3)) {
+ static int cmdIndex = 0;
+ int getvar_num;
+ if (has_boot_slot == 1) {
+ strcpy(cmd, getvar_list_ab[cmdIndex]);
+ getvar_num = (sizeof(getvar_list_ab) / sizeof(getvar_list_ab[0]));
+ } else {
+ strcpy(cmd, getvar_list[cmdIndex]);//only support no-arg cmd
+ getvar_num = (sizeof(getvar_list) / sizeof(getvar_list[0]));
+ }
+ printf("getvar_num: %d\n", getvar_num);
+ if ( ++cmdIndex >= getvar_num) cmdIndex = 0;
+ else fastboot_busy(NULL);
+ FB_MSG("all cmd:%s\n", cmd);
+ strncat(response, cmd, chars_left);
+ strncat(response, ":", 1);
+ chars_left -= strlen(cmd) + 1;
+ }
+
+ if (!strcmp_l1("version", cmd)) {
+ strncat(response, DNL_PROTOCOL_VERSION, chars_left);
+ } else if (!strcmp_l1("bootloader-version", cmd)) {
+ strncat(response, U_BOOT_VERSION, chars_left);
+ } else if (!strcmp_l1("burnsteps", cmd)) {
+ unsigned* steps = (unsigned*)(response + 4);
+ FB_DBG("SYSCTRL_STICKY_REG2 addr 0x%x\n", P_PREG_STICKY_REG2);
+ *steps = readl(P_PREG_STICKY_REG2);
+ fastboot_tx_write(response, 4 + sizeof(unsigned));
+ return;
+ } else if (!strcmp_l1("identify", cmd)) {
+ const int identifyLen = 8;
+ char fwVer[] = {5, 0, 0, 16, 0, 0, 0, 0};
+ cpu_id_t cpuid = get_cpu_id();
+ if (cpuid.family_id >= MESON_CPU_MAJOR_ID_SC2) fwVer[0] = 6;
+ memcpy(response + 4, fwVer, identifyLen);
+ replyLen = 4 + identifyLen;
+ adnl_identify_timeout = 0;
+ } else if (!strcmp_l1("secureboot", cmd)) {
+ unsigned securebootEnable = 0;
+#ifdef CONFIG_EFUSE
+ securebootEnable = IS_FEAT_BOOT_VERIFY() ? 1 : 0;
+#else
+ FB_MSG("Configure efuse not enabled\n");
+#endif//#ifdef CONFIG_EFUSE
+ memcpy(response + 4, &securebootEnable, sizeof(unsigned));
+ replyLen = 4 + sizeof(unsigned);
+ } else if (!strcmp_l1("serialno", cmd)) {
+ extern const char * get_usid_string(void);
+ const char* usid = get_usid_string();
+ if (usid) strncat(response, usid, chars_left);
+ else strncat(response, DEVICE_SERIAL, chars_left);
+ } else if (!strcmp_l1("soctype", cmd)) {
+ cpu_id_t cpuid = get_cpu_id();
+ *(unsigned*)(response+4) = cpuid.family_id;
+ *(unsigned*)(response+8) = cpuid.chip_rev;
+ FB_DBG("soctype 0x%08x, %08x\n", cpuid.family_id, cpuid.chip_rev);
+ replyLen = 4 + 8;
+ } else if (!strcmp_l1("product", cmd)) {
+ char* s1 = DEVICE_PRODUCT;
+ strncat(response, s1, chars_left);
+ } else if (!strcmp_l1("slot-count", cmd)) {
+ strncat(response, "2", chars_left);
+ } else if (!strcmp_l1("erase-block-size", cmd)) {
+ strncat(response, "2000", chars_left);
+ } else {
+ FB_ERR("unknown variable: %s\n", cmd);
+ strcpy(response, "FAILVariable not implemented");
+ }
+
+ replyLen = replyLen ? replyLen : strlen(response) + 1; //+1 means plus '\0'
+ fastboot_tx_write(response, replyLen);
+}
+
+static void cb_devices(struct usb_ep *ep, struct usb_request *req)
+{
+ char response[RESPONSE_LEN];
+ char *cmd = req->buf;
+
+ printf("cmd is %s\n", cmd);
+
+ strcpy(response, "AMLOGIC");
+
+ fastboot_tx_write_str(response);
+}
+
+struct cmd_dispatch_info {
+ char *cmd;
+ void (*cb)(struct usb_ep *ep, struct usb_request *req);
+};
+
+static const struct cmd_dispatch_info cmd_dispatch_info[] = {
+ {
+ .cmd = "reboot",
+ .cb = cb_reboot,
+ }, {
+ .cmd = "getvar:",
+ .cb = cb_getvar,
+ }, {
+ .cmd = "devices",
+ .cb = cb_devices,
+ },
+ {
+ .cmd = "reboot-bootloader",
+ .cb = cb_reboot,
+ },
+ {
+ .cmd = "mwrite",
+ .cb = cb_aml_media_write,
+ }, {
+ .cmd = "mread",
+ .cb = cb_aml_media_read,
+ }, {
+ .cmd = "oem",
+ .cb = cb_oem_cmd,
+ }
+};
+
+//cb for out_req->complete
+static void rx_handler_command(struct usb_ep *ep, struct usb_request *req)
+{
+ char *cmdbuf = req->buf;
+ void (*func_cb)(struct usb_ep *ep, struct usb_request *req) = NULL;
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(cmd_dispatch_info); i++) {
+ if (!strcmp_l1(cmd_dispatch_info[i].cmd, cmdbuf)) {
+ func_cb = cmd_dispatch_info[i].cb;
+ break;
+ }
+ }
+
+ if (!func_cb) {
+ FB_MSG("unknown command: %s,%ld\n", cmdbuf, strlen(cmdbuf));
+ fastboot_tx_write_str("FAILunknown command");
+ } else {
+ if (req->actual < req->length) {
+ u8 *buf = (u8 *)req->buf;
+ buf[req->actual] = 0;
+ func_cb(ep, req);
+ } else {
+ FB_ERR("buffer overflow\n");
+ fastboot_tx_write_str("FAILbuffer overflow");
+ }
+ }
+
+ if (req->status == 0 && !fastboot_is_busy()) {
+ *cmdbuf = '\0';
+ req->actual = 0;
+ usb_ep_queue(ep, req, 0);
+ }
+}
+
+//following extended amlogic commands
+//
+char* fb_response_str = &response_str[4];
+
+enum {
+ MWRITE_DATA_CHECK_ALG_NONE = 0, //not need check sum
+ MWRITE_DATA_CHECK_ALG_ADDSUM,
+ MWRITE_DATA_CHECK_ALG_CRC32,
+};
+static struct {
+ unsigned totalBytes;
+ unsigned transferredBytes; //transferredBytes <= totalBytes
+ unsigned dataCheckAlg;
+ void* priv;//now for backup req->buf
+}_mwriteInfo = {0}, _mreadInfo = {0};
+
+
+static UsbDownInf* _pUsbDownInf = NULL;
+static UsbUpInf* _pUsbUpInf = NULL;
+
+static void rx_handler_mwrite(struct usb_ep *ep, struct usb_request *req)
+{
+ const unsigned int transfer_size = req->actual;
+ char* dataBuf = _pUsbDownInf->dataBuf;
+ int ret = 0;
+
+ if (req->status != 0) {
+ printf("Bad status: %d\n", req->status);
+ return;
+ }
+
+ _mwriteInfo.transferredBytes += transfer_size;
+
+ /* Check if transfer is done */
+ if ((_mwriteInfo.transferredBytes == _mwriteInfo.totalBytes) &&
+ (_mwriteInfo.dataCheckAlg > MWRITE_DATA_CHECK_ALG_NONE)) {
+ req->length = 4;//rx addsum
+ req->buf += transfer_size;//remove copy
+ if ((int64_t)req->buf & 7) {//address not align 8
+ req->buf = (char*)((((int64_t)req->buf + 7)>>3)<<3);
+ }
+ }else if (_mwriteInfo.transferredBytes >= _mwriteInfo.totalBytes) {
+ fastboot_okay(NULL);
+ response_str[4] = 0;
+#ifndef CONFIG_USB_GADGET_CRG
+ //forward to hold on long-time wait and not need use driver api directly
+ fastboot_tx_write_str(response_str);//response_str will update following
+#endif//#ifndef CONFIG_USB_GADGET_CRG
+ if (MWRITE_DATA_CHECK_ALG_ADDSUM == _mwriteInfo.dataCheckAlg) {
+ const unsigned dataLen = _mwriteInfo.totalBytes;
+ const unsigned gensum = add_sum(dataBuf, dataLen);
+ const unsigned orisum = *(unsigned*)(((int64_t)(dataBuf + dataLen + 7)>>3)<<3);
+ if ( gensum != orisum ) {
+ FB_MSG("dataLen 0x%x, origsum 0x%x, 0x%x\n", dataLen, orisum, _mwriteInfo.transferredBytes);
+ FBS_ERR(response_str, "FAIL;gensum(0x%x) != origsum(0x%x)", gensum, orisum);
+ ret = -__LINE__;
+ }
+ }
+ if ( !ret ) {//no err
+ ret = v3tool_buffman_data_complete_download(_pUsbDownInf);
+ }
+ ret ? fastboot_fail(NULL) : fastboot_okay(NULL);
+ fastboot_tx_write_str(response_str);//just update tx buffer
+ FB_DBG("mwrite 0x%x bytes [%s]\n", _mwriteInfo.transferredBytes, ret ? "FAILED" : "OK");
+
+ req->complete = rx_handler_command;//mwrite ended and return to receive command
+ req->length = EP_CMD_LEN_MAX;
+ if (_mwriteInfo.priv)req->buf = (char*) _mwriteInfo.priv;
+
+ } else {
+ const unsigned leftLen = _mwriteInfo.totalBytes - _mwriteInfo.transferredBytes;
+ req->length = DWC_BLK_LEN(leftLen);
+ req->buf += transfer_size;//remove copy
+ }
+
+ req->actual = 0;
+ usb_ep_queue(ep, req, 0);
+}
+
+//[fastboot mwrite:verify=addsum]
+static void cb_aml_media_write(struct usb_ep *ep, struct usb_request *req)
+{
+ char *cmd = req->buf;
+ FB_DBG("cmd cb_mwrite[%s]\n", cmd);
+ strsep(&cmd, ":");
+ int ret = -__LINE__;
+ const char* field = cmd;
+ response_str[4] = 0;//clear for fastboot_tx_write_str
+
+ //default attributes for mwrite
+ _mwriteInfo.dataCheckAlg = MWRITE_DATA_CHECK_ALG_NONE;//default no transfer verify
+ _mwriteInfo.transferredBytes = 0;
+ for (strsep(&cmd, "="); cmd; ) {
+ if (!strcmp(field,"verify")) {
+ if (!strcmp("addsum", cmd)) {
+ _mwriteInfo.dataCheckAlg = MWRITE_DATA_CHECK_ALG_ADDSUM;
+ } else {
+ /**endptr = '\0';*/
+ FBS_ERR(_ACK, "unsupported dataCheckAlg %s", cmd);
+ fastboot_fail(NULL);
+ return;
+ }
+ } else {
+ sprintf(response_str, "FAILunknown field[%s]\n", field);
+ FB_ERR(response_str);
+ goto _exit;
+ }
+
+ strsep(&cmd, ",");
+ strsep(&cmd, "=");
+ }
+
+ ret = v3tool_buffman_next_download_info(&_pUsbDownInf);
+ if ( ret || NULL == _pUsbDownInf) {
+ FBS_ERR(_ACK, "Fail in buffman get, ret %d", ret);
+ goto _exit;
+ }
+ if (NULL == _pUsbDownInf) {
+ FBS_ERR(_ACK, "in get next img info");
+ goto _exit;
+ }
+ _mwriteInfo.totalBytes = _pUsbDownInf->dataSize;
+
+ ret = 0;
+_exit:
+ if (ret) {
+ fastboot_fail(NULL);
+ }else if(0 == _pUsbDownInf->dataSize){
+ fastboot_okay(NULL);
+ FB_MSG("OK in Partition Image\n\n");
+ }else {
+ sprintf(response_str, "DATAOUT0x%x:0x%llx", _pUsbDownInf->dataSize, _pUsbDownInf->fileOffset);
+ req->complete = rx_handler_mwrite;//handle for download complete
+ const unsigned leftLen = _mwriteInfo.totalBytes - _mwriteInfo.transferredBytes;
+ req->length = DWC_BLK_LEN(leftLen);
+ if (!_mwriteInfo.priv) _mwriteInfo.priv = req->buf;
+ req->buf = _pUsbDownInf->dataBuf;//to remove copy
+ }
+ fastboot_tx_write_str(response_str);
+
+ return;
+}
+
+static int v3tool_bl33_setvar_burnsteps(const int argc, char* const argv[])
+{
+ if ( 3 != argc ) {
+ FB_EXIT("err setvar argc %d\n", argc);
+ }
+ unsigned long reg2 = simple_strtoul(argv[2], NULL, 0);
+ if ( reg2 >> 32 ) {
+ FB_EXIT("argv[1](%s) too big for 32bits reg\n", argv[2]);
+ }
+ writel((unsigned)reg2, P_PREG_STICKY_REG2);
+ return 0;
+}
+
+static int v3tool_bl33_setvar(const int argc, char* const argv[])
+{
+ if ( 2 > argc ) {
+ FB_EXIT("too few setvar argc %d\n", argc);
+ }
+ const char* subcmd = argv[1];
+ if ( !strcmp("burnsteps", subcmd) ) {
+ return v3tool_bl33_setvar_burnsteps(argc, argv);
+ } else {
+ FB_EXIT("unsupported setvar cmd[%s]\n", subcmd);
+ }
+ return 0;
+}
+
+//forward declare for cb_oem_cmd
+static int _mwrite_cmd_parser(const int argc, char* argv[], char* ack);
+static int _verify_partition_img(const int argc, char* argv[], char* ack);
+static int _mread_cmd_parser(const int argc, char* argv[], char* ack);
+int __attribute__((weak)) sheader_need(void) { FB_WRN("sheader_need undefined\n"); return 0;}
+
+static void cb_oem_cmd(struct usb_ep *ep, struct usb_request *req)
+{
+ int ret = 0;
+ char tmp[RESPONSE_LEN + 1];
+ char* cmd = req->buf;
+ char* ack = response_str + 4;
+
+ ack[0] = '\0';//set err for which buf not setted
+ char* cmdBuf = tmp;
+ memcpy(cmdBuf, cmd, strnlen(cmd, RESPONSE_LEN)+1);//+1 to terminate str
+ strsep(&cmdBuf, " ");
+ printf("OEM cmd[%s]\n", cmdBuf);
+ response_str[4] = 0;
+
+ int argc = 33;
+ char *argv[CONFIG_SYS_MAXARGS + 1];
+ argc = cli_simple_parse_line(cmdBuf, argv);
+ if (argc == 0) {
+ fastboot_fail("oem no command at all");
+ FB_ERR("%s\n", response_str);;
+ return;
+ }
+
+ if ( !strcmp("mwrite", argv[0]) ) {
+ ret = _mwrite_cmd_parser(argc, argv, ack);
+ } else if( !strcmp("verify", argv[0]) ){
+ ret = _verify_partition_img(argc, argv, ack);
+ if (fastboot_is_busy()) {
+ fastboot_tx_write_str(response_str);
+ return;
+ }
+ } else if( !strcmp("mread", argv[0]) ){
+ FB_MSG("IS_FEAT_BOOT_VERIFY 0x%x\n", IS_FEAT_BOOT_VERIFY());
+ ret = _mread_cmd_parser(argc, argv, ack);
+#ifdef CONFIG_V3_KEY_BURNING_SUPPORT
+ } else if( !strcmp("key", argv[0]) ){
+ ret = v2_key_command(argc, argv, ack);
+#endif//#ifdef CONFIG_V3_KEY_BURNING_SUPPORT
+ } else if( !strcmp("disk_initial", argv[0]) ){
+ int toErase = argc > 1 ? simple_strtoul(argv[1], NULL, 0) : 0;
+ int dtbImgSz = (0x1b8e == _memDtbImg[0].hadDown) ? _memDtbImg[0].imgSize : 0;
+ int gptImgSz = (0x1b8e == _memDtbImg[1].hadDown) ? _memDtbImg[1].imgSize : 0;
+ ret = v3tool_storage_init(toErase, dtbImgSz, gptImgSz);
+ memset(_memDtbImg, 0, sizeof(_memDtbImg));
+ } else if( !strcmp("save_setting", argv[0]) ){
+#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
+ env_set("firstboot", "1");
+ env_set("upgrade_step", "1");
+ ret = run_command("store rsv erase env", 0);
+ ret = run_command("saveenv", 0);
+#else
+ FB_MSG("saveenv not implemented\n");
+ ret = 0;
+#endif//#if defined(CONFIG_CMD_SAVEENV) && !defined(CONFIG_ENV_IS_NOWHERE)
+ } else if( !strcmp("setvar", argv[0]) ){
+ ret = v3tool_bl33_setvar(argc, argv);
+ } else if( !strcmp("sheader_need", argv[0]) ){
+ ret = sheader_need() ? 0 : ret;
+ } else {
+ strsep(&cmd, " ");
+ char* p = cmd; strsep(&p, ";"); //only allow one command to execute
+ int cmdIsInWhiteList = 1;
+ if (IS_FEAT_BOOT_VERIFY()) {
+ cmdIsInWhiteList = 0;
+ const char** pCmdList = (const char**)white_list_adnl_cmds;
+ for (const char* aCmd = *pCmdList; aCmd; aCmd = *++pCmdList) {
+ FB_DBG("aCmd %s\n", aCmd);
+ if (strcmp(argv[0], aCmd)) continue;
+ cmdIsInWhiteList = 1; break;
+ }
+ if (!cmdIsInWhiteList) {
+ FBS_ERR(ack,"cmd %s not in secure boot white list", argv[0]);
+ ret = __LINE__;
+ }
+ }
+ if (cmdIsInWhiteList) {
+ ret = run_command(cmd, 0);
+ if ( ret ) {
+ FBS_ERR(ack,"fail in cmd,ret %d", ret);
+ }
+ }
+ }
+
+ ret ? fastboot_fail(NULL) :fastboot_okay(NULL);
+ fastboot_tx_write_str(response_str);
+ FB_MSG("response[%d][%s]\n", ret, response_str);
+ return ;
+}
+
+const char* _imgFmt[] = {"normal", "sparse", "ubifs"};
+const char* _mediatype[] = {"store", "mem", "key", "mmc"};
+
+static int _verify_partition_img(const int argc, char* argv[], char* ack)
+{
+ int ret = -__LINE__;
+ if (3 > argc) {
+ FBS_ERR(ack, "argc(%d) < 3 invalid\n", argc);
+ return -__LINE__;
+ }
+ const char* vryAlg = argv[1];
+ const char* origsumStr = argv[2];
+ unsigned char gensum[SHA1_SUM_LEN];
+ char gensumStr[SHA1_SUM_LEN*2+1];
+
+ ret = strcmp(vryAlg, "sha1sum");
+ if (ret) {
+ FBS_ERR(ack, "vryAlg[%s] unsupported\n", vryAlg);
+ return -__LINE__;
+ }
+ if (40 != strnlen(origsumStr,48)) {
+ FBS_ERR(ack, "err vrySum in len for vryAlg[%s]\n", vryAlg);
+ return -__LINE__;
+ }
+ ret = v3tool_buffman_img_verify_sha1sum(gensum);
+ if (v3tool_media_is_busy()) {
+ return 0;
+ }
+ if ( ret ) {
+ FB_ERR("Fail in gen sha1sum,ret=%d", ret);
+ return -__LINE__;
+ }
+ ret = optimus_hex_data_2_ascii_str(gensum, SHA1_SUM_LEN, gensumStr, sizeof(gensumStr)/sizeof(gensumStr[0]));
+ if ( ret ) {
+ FBS_ERR(ack, "Fail in pass hex to str,ret %d", ret);
+ return -__LINE__;
+ }
+ ret = strncmp(gensumStr, origsumStr, 40);
+ if ( ret ) {
+ /*FBS_ERR(ack, "gensum[%s] NOT match orisum[%s]", gensumStr, origsumStr);*/
+ FBS_ERR(ack, "gensum[%s] NOT match, origsum[%s]", gensumStr, origsumStr);
+ return -__LINE__;
+ }
+ FB_MSG("Verify finish and successful!\n");
+ return 0;
+}
+
+//[mwrite] $imgSize $imgFmt $mediaType $partition <$partOffset>
+static int _mwrite_cmd_parser(const int argc, char* argv[], char* ack)
+{
+ int i = 0, ret = 0;
+ if ( 5 > argc ) {
+ sprintf(ack, "argc(%d) too few for mwrite", argc);
+ FB_ERR("%s\n", ack);
+ return -__LINE__;
+ }
+ const int64_t imgSize = simple_strtoull(argv[1], NULL, 0);
+ const char* imgFmt = argv[2];
+ const char* media = argv[3];
+ const char* partition = argv[4];
+ const int64_t partOff = argc > 5 ? simple_strtoull(argv[5], NULL, 0) : 0;
+ ImgTransPara imgTransPara;
+ ImgDownloadPara* imgDownloadPara = &imgTransPara.download;
+ ImgCommonPara* commonInf = &imgDownloadPara->commonInf;
+
+ memset(&imgTransPara, 0 , sizeof(imgTransPara));
+ int imgFmtInt = -1;
+ for (; i < sizeof(_imgFmt)/sizeof(_imgFmt[0]); ++i) {
+ if (!strcmp(_imgFmt[i],imgFmt)) imgFmtInt = V3TOOL_PART_IMG_FMT_RAW + i;
+ }
+ if ( imgFmtInt == -1 ) {
+ FBS_ERR(ack, "illegal imgFmt %s", imgFmt);
+ return -__LINE__;
+ }
+ int mediaType = -1;
+ for (i=0; i < sizeof(_mediatype)/sizeof(_mediatype[0]); ++i) {
+ if (strcmp(_mediatype[i], media)) continue;
+ mediaType = V3TOOL_MEDIA_TYPE_STORE + i;
+ break;
+ }
+ if ( -1 == mediaType ) {
+ FBS_ERR(ack, "unsupprted media %s", media);
+ return -__LINE__;
+ }
+
+ imgDownloadPara->imgFmt = imgFmtInt;
+ commonInf->imgSzTotal = imgSize;
+ commonInf->mediaType = mediaType;
+ commonInf->partStartOff = partOff;
+ strncpy(commonInf->partName, partition,V3_PART_NAME_LEN);
+ switch (mediaType)
+ {
+ case V3TOOL_MEDIA_TYPE_MEM:
+ {
+ if (!strcmp("dtb", partition)) {
+ commonInf->partStartOff += V3_DTB_LOAD_ADDR;
+ _memDtbImg[0].hadDown = 0x1b8e;
+ _memDtbImg[0].imgSize = imgSize;
+ } else if (!strcmp("sheader", partition)) {
+ commonInf->partStartOff += V3_PAYLOAD_LOAD_ADDR;
+ } else if (!strcmp("gpt", partition)) {
+ _memDtbImg[1].hadDown = 0x1b8e;
+ _memDtbImg[1].imgSize = imgSize;
+ commonInf->partStartOff += V3_GPT_LOAD_ADDR;
+ } else {
+ if (IS_FEAT_BOOT_VERIFY()) {
+ FBS_ERR(ack, "partition memory not allowed when secure boot enabled\n");
+ return -__LINE__;
+ }
+ commonInf->partStartOff += simple_strtoull(partition, NULL, 0);
+ }
+ FB_MSG("mem base %llx\n", commonInf->partStartOff);
+ } break;
+ case V3TOOL_MEDIA_TYPE_STORE:
+ case V3TOOL_MEDIA_TYPE_MMC:
+ { }break;
+ case V3TOOL_MEDIA_TYPE_UNIFYKEY:
+ {
+ if ( imgSize >= _UNIFYKEY_MAX_SZ ) {
+ FBS_ERR(ack, "key sz 0x%llx too large\n", imgSize);
+ return -__LINE__;
+ }
+ }break;
+ default:
+ FBS_ERR(ack, "unsupported meida %s", media);
+ return -__LINE__;
+ }
+ ret = v3tool_buffman_img_init(&imgTransPara, 1);
+ if ( ret ) {
+ FB_ERR("Fail in buffman init, ret %d\n", ret);
+ return -__LINE__;
+ }
+ printf("Flash 0x%08llx Bytes %s img to %s:%s at off 0x%llx\n", imgSize, imgFmt, media, partition, partOff);
+
+ return ret;
+}
+
+//[mread] $imgSize $imgFmt $mediaType $partition <$partOffset>
+static int _mread_cmd_parser(const int argc, char* argv[], char* ack)
+{
+ int i = 0, ret = 0;
+ if ( 5 > argc ) {
+ sprintf(ack, "argc(%d) too few for mwrite", argc);
+ FB_ERR("%s\n", ack);
+ return -__LINE__;
+ }
+ const int64_t imgSize = simple_strtoull(argv[1], NULL, 0);
+ const char* imgFmt = argv[2];
+ const char* media = argv[3];
+ const char* partition = argv[4];
+ const int64_t partOff = argc > 5 ? simple_strtoull(argv[5], NULL, 0) : 0;
+ ImgTransPara imgTransPara;
+ ImgUploadPara* imgUploadPara = &imgTransPara.upload;
+ ImgCommonPara* commonInf = &imgUploadPara->commonInf;
+
+ memset(&imgTransPara, 0 , sizeof(imgTransPara));
+ int imgFmtInt = -1;
+ for (; i < sizeof(_imgFmt)/sizeof(_imgFmt[0]); ++i) {
+ if (!strcmp(_imgFmt[i],imgFmt)) imgFmtInt = V3TOOL_PART_IMG_FMT_RAW + i;
+ }
+ if ( imgFmtInt == -1 ) {
+ FBS_ERR(ack, "illegal imgFmt %s", imgFmt);
+ return -__LINE__;
+ }
+ if (imgFmtInt != V3TOOL_PART_IMG_FMT_RAW) {
+ FBS_ERR(ack, "oops, only support normal fmt in upload mode");
+ return -__LINE__;
+ }
+ int mediaType = -1;
+ for (i=0; i < sizeof(_mediatype)/sizeof(_mediatype[0]); ++i) {
+ if (strcmp(_mediatype[i], media)) continue;
+ mediaType = V3TOOL_MEDIA_TYPE_STORE + i;
+ break;
+ }
+ if ( -1 == mediaType ) {
+ FBS_ERR(ack, "unsupprted media %s", media);
+ return -__LINE__;
+ }
+ if (V3TOOL_MEDIA_TYPE_UNIFYKEY != mediaType && IS_FEAT_BOOT_VERIFY()) {
+ FBS_ERR(ack, "upload not allowed as secure boot enabled\n");
+ return -__LINE__;
+ }
+
+ commonInf->imgSzTotal = imgSize;
+ commonInf->mediaType = mediaType;
+ commonInf->partStartOff = partOff;
+ switch (mediaType)
+ {
+ case V3TOOL_MEDIA_TYPE_MEM:
+ {
+ commonInf->partStartOff += simple_strtoull(partition, NULL, 0);
+ FB_MSG("partStartOff 0x%llx\n", commonInf->partStartOff);
+ } break;
+ case V3TOOL_MEDIA_TYPE_STORE:
+ case V3TOOL_MEDIA_TYPE_UNIFYKEY:
+ case V3TOOL_MEDIA_TYPE_MMC:
+ {
+ strncpy(commonInf->partName, partition,V3_PART_NAME_LEN);
+ }break;
+ default:
+ FBS_ERR(ack, "unsupported meida %s", media);
+ return -__LINE__;
+ }
+ ret = v3tool_buffman_img_init(&imgTransPara, 0);
+ if ( ret ) {
+ FB_ERR("Fail in buffman init, ret %d\n", ret);
+ return -__LINE__;
+ }
+
+ return ret;
+}
+
+static void tx_handler_mread(struct usb_ep* inep, struct usb_request* inreq)
+{
+ const unsigned int transfer_size = inreq->actual;
+
+ if (inreq->status != 0) {
+ printf("in req Bad status: %d\n", inreq->status);
+ return;
+ }
+ if ( fastboot_func->in_req != inreq ) {
+ FB_ERR("exception, bogus req\n");
+ return ;
+ }
+ _mreadInfo.transferredBytes += transfer_size;
+
+ /* Check if transfer is done */
+ if (_mreadInfo.transferredBytes >= _mreadInfo.totalBytes) {
+ FB_DBG("mread 0x%x bytes end\n", _mreadInfo.transferredBytes);
+
+ inreq->complete = fastboot_complete;//mwrite ended and return to receive command
+ inreq->length = EP_BUFFER_SIZE;
+ if (_mreadInfo.priv)inreq->buf = (char*) _mreadInfo.priv;
+ //should return to rx next command
+ v3tool_buffman_data_complete_upload(_pUsbUpInf);
+ } else {
+ const unsigned leftLen = _mreadInfo.totalBytes - _mreadInfo.transferredBytes;
+ inreq->length = DWC_BLK_LEN(leftLen);
+ inreq->buf += transfer_size;//remove copy
+
+ inreq->actual = 0;
+ usb_ep_queue(inep, inreq, 0);
+ }
+
+ return;
+}
+
+enum {
+ MREAD_STATUS_REQUEST = 0xee,
+ MREAD_STATUS_UPLOAD ,
+ MREAD_STATUS_FINISH ,
+};
+
+//[fastboot mread boot.img.dump]
+void cb_aml_media_read(struct usb_ep *outep, struct usb_request *outreq)
+{
+ char *cmd = outreq->buf;
+ FB_DBG("cmd cb_mread[%s]\n", cmd);
+ strsep(&cmd, ":");
+ int ret = -__LINE__;
+ int staMread = 0;
+
+ //default attributes for mwrite
+ _mwriteInfo.dataCheckAlg = MWRITE_DATA_CHECK_ALG_NONE;//default no transfer verify
+ _mwriteInfo.transferredBytes = 0;
+
+ const char* field = cmd;
+ strsep(&cmd, "=");
+ /*const int64_t val = simple_strtoull(cmd, &endptr, 0);*/
+ if (!strcmp(field,"status")) {
+ if (!strcmp("request", cmd)) {
+ staMread = MREAD_STATUS_REQUEST;
+ } else if(!strcmp("upload", cmd)){
+ staMread = MREAD_STATUS_UPLOAD;
+ } else if(!strcmp("finish", cmd)){
+ staMread = MREAD_STATUS_FINISH;
+ } else {
+ FBS_ERR(_ACK, "unsupported mread status %s", cmd);
+ fastboot_fail(NULL);
+ return;
+ }
+ }
+
+ switch (staMread)
+ {
+ case MREAD_STATUS_REQUEST:
+ {
+ //default attributes for mwrite
+ _mreadInfo.transferredBytes = 0;
+ _mreadInfo.totalBytes = 0;
+
+ ret = v3tool_buffman_next_upload_info(&_pUsbUpInf);
+ if ( ret || NULL == _pUsbUpInf) {
+ FBS_ERR(_ACK, "Fail in buffman get, ret %d", ret);
+ fastboot_fail(NULL);
+ fastboot_tx_write_str(response_str);
+ return;
+ }
+ if ( 0 == _pUsbUpInf->dataSize ) {
+ fastboot_okay(NULL); response_str[4] = 0;//add NULL terminated
+ FB_MSG("OKAY in Upload Data\n\n");
+ } else {
+ _mreadInfo.totalBytes = _pUsbUpInf->dataSize;
+ sprintf(response_str, "DATAIN0x%x", _pUsbUpInf->dataSize);
+ }
+ fastboot_tx_write(response_str, strnlen(response_str, RESPONSE_LEN) + 1);//add 0 ternimated
+ FB_DBG("_pUsbUpInf %p,sz %d\n", _pUsbUpInf->dataBuf, _mreadInfo.totalBytes);
+ return ;
+ }
+ case MREAD_STATUS_UPLOAD:
+ {
+ struct usb_ep* inep = fastboot_func->in_ep;
+ struct usb_request* inreq = fastboot_func->in_req;
+ inreq->complete = tx_handler_mread;//handle for download complete
+ const unsigned leftLen = _mreadInfo.totalBytes - _mreadInfo.transferredBytes;
+ inreq->length = DWC_BLK_LEN(leftLen);
+ if (!_mreadInfo.priv) _mreadInfo.priv = inreq->buf;//backup command buf
+ inreq->buf = _pUsbUpInf->dataBuf;//to remove copy
+ FB_DBG("upload buf=%p, leftLen 0x%x, req len 0x%x\n",
+ inreq->buf, leftLen, inreq->length);
+ ret = usb_ep_queue(inep, inreq, 0);
+ if (ret)
+ FB_ERR("Error %d on queue\n", ret);
+ return;
+ }
+ case MREAD_STATUS_FINISH:
+ {
+ const int uploadOk = (_mreadInfo.totalBytes == _mreadInfo.transferredBytes);
+ const char* ack = uploadOk ? "OKAY" : "FAIL";
+ fastboot_tx_write_str(ack);
+ } break;//just reuturn
+ }
+
+ return;
+}
+
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index e2728ef..9207c1b 100644
--- a/drivers/usb/host/Kconfig
+++ b/drivers/usb/host/Kconfig
@@ -15,6 +15,12 @@
if USB_XHCI_HCD
+config USB_XHCI_CRG
+ bool "Corgine USB3 DRD Core Support"
+ help
+ Say Y or if your system has a Dual Role SuperSpeed
+ USB controller based on the Corgine USB3 IP Core.
+
config USB_XHCI_DWC3
bool "DesignWare USB3 DRD Core Support"
help
@@ -265,4 +271,3 @@
because larger transactions could be split in smaller ones.
endif # USB_DWC2
-
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile
index 948683a..319deb2 100644
--- a/drivers/usb/host/Makefile
+++ b/drivers/usb/host/Makefile
@@ -47,6 +47,7 @@
# xhci
obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o
obj-$(CONFIG_USB_XHCI_DWC3) += xhci-dwc3.o
+obj-$(CONFIG_USB_XHCI_CRG) += xhci-crg.o
obj-$(CONFIG_USB_XHCI_DWC3_OF_SIMPLE) += dwc3-of-simple.o
obj-$(CONFIG_USB_XHCI_ROCKCHIP) += xhci-rockchip.o
obj-$(CONFIG_USB_XHCI_ZYNQMP) += xhci-zynqmp.o
diff --git a/drivers/usb/host/xhci-crg.c b/drivers/usb/host/xhci-crg.c
new file mode 100644
index 0000000..85e0bfe
--- /dev/null
+++ b/drivers/usb/host/xhci-crg.c
@@ -0,0 +1,190 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <fdtdec.h>
+#include <generic-phy.h>
+#include <usb.h>
+#include <dwc3-uboot.h>
+
+#include "xhci.h"
+#include <asm/io.h>
+#include <linux/usb/dwc3.h>
+#include <linux/usb/otg.h>
+
+struct xhci_crg_platdata {
+ struct phy *usb_phys;
+ int num_phys;
+};
+#ifdef CONFIG_AML_USB
+unsigned int usb2portnum;
+#endif
+
+void crg_set_mode(struct xhci_hccr *hccr, u32 mode)
+{
+ u64 tmp;
+
+ if (mode == USB_DR_MODE_HOST) {
+ /* set controller host role*/
+ tmp = readl(hccr + 0x20FC) & ~0x1;
+ writel(tmp, hccr + 0x20FC);
+ }
+}
+
+
+#if CONFIG_IS_ENABLED(DM_USB)
+
+void xhci_crg_phy_tuning_1(struct udevice *dev, int port)
+{
+ /* nothing */
+}
+
+static int xhci_crg_setup_phy(struct udevice *dev)
+{
+ struct xhci_crg_platdata *plat = dev_get_platdata(dev);
+ int i, ret, count;
+#ifdef CONFIG_AML_USB
+ unsigned int usb_type = 0;
+#endif
+
+
+ /* Return if no phy declared */
+ if (!dev_read_prop(dev, "phys", NULL))
+ return 0;
+
+ count = dev_count_phandle_with_args(dev, "phys", "#phy-cells");
+ if (count <= 0)
+ return count;
+
+ plat->usb_phys = devm_kcalloc(dev, count, sizeof(struct phy),
+ GFP_KERNEL);
+ if (!plat->usb_phys)
+ return -ENOMEM;
+
+#ifdef CONFIG_AML_USB
+ plat->num_phys = 0;
+#endif
+
+ for (i = 0; i < count; i++) {
+ ret = generic_phy_get_by_index(dev, i, &plat->usb_phys[i]);
+ if (ret && ret != -ENOENT) {
+ pr_err("Failed to get USB PHY%d for %s\n",
+ i, dev->name);
+ return ret;
+ }
+
+ ++plat->num_phys;
+ }
+
+ for (i = 0; i < plat->num_phys; i++) {
+ ret = generic_phy_init(&plat->usb_phys[i]);
+ if (ret) {
+ pr_err("Can't init USB PHY%d for %s\n",
+ i, dev->name);
+ goto phys_init_err;
+ }
+ }
+
+ for (i = 0; i < plat->num_phys; i++) {
+ ret = generic_phy_power_on(&plat->usb_phys[i]);
+ if (ret) {
+ pr_err("Can't power USB PHY%d for %s\n",
+ i, dev->name);
+ goto phys_poweron_err;
+ }
+ }
+
+#ifdef CONFIG_AML_USB
+ for (i = 0; i < plat->num_phys; i++) {
+ dev_read_u32((&plat->usb_phys[i])->dev, "phy-version", &usb_type);
+ if (usb_type == 2) {
+ dev_read_u32((&plat->usb_phys[i])->dev, "portnum", &usb2portnum);
+ }
+ }
+#endif
+
+ return 0;
+
+phys_poweron_err:
+ for (; i >= 0; i--)
+ generic_phy_power_off(&plat->usb_phys[i]);
+
+ for (i = 0; i < plat->num_phys; i++)
+ generic_phy_exit(&plat->usb_phys[i]);
+
+ return ret;
+
+phys_init_err:
+ for (; i >= 0; i--)
+ generic_phy_exit(&plat->usb_phys[i]);
+
+ return ret;
+}
+
+static int xhci_crg_probe(struct udevice *dev)
+{
+ struct xhci_hcor *hcor;
+ struct xhci_hccr *hccr;
+ enum usb_dr_mode dr_mode;
+#ifndef CONFIG_AML_USB
+ struct xhci_crg_platdata *plat = dev_get_platdata(dev);
+#endif
+ int ret;
+
+#ifdef CONFIG_AML_USB
+ ret = xhci_crg_setup_phy(dev);
+ if (ret)
+ return ret;
+
+ hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
+ hcor = (struct xhci_hcor *)((uintptr_t)hccr +
+ HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
+#else
+ hccr = (struct xhci_hccr *)((uintptr_t)dev_read_addr(dev));
+ hcor = (struct xhci_hcor *)((uintptr_t)hccr +
+ HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));
+
+ ret = dwc3_setup_phy(dev, &plat->usb_phys, &plat->num_phys);
+ if (ret && (ret != -ENOTSUPP))
+ return ret;
+#endif
+
+ dr_mode = usb_get_dr_mode(dev_of_offset(dev));
+ if (dr_mode == USB_DR_MODE_UNKNOWN)
+ /* by default set dual role mode to HOST */
+ dr_mode = USB_DR_MODE_HOST;
+
+ crg_set_mode(hccr, dr_mode);
+
+ return xhci_register(dev, hccr, hcor);
+}
+
+static int xhci_crg_remove(struct udevice *dev)
+{
+ struct xhci_crg_platdata *plat = dev_get_platdata(dev);
+
+ dwc3_shutdown_phy(dev, plat->usb_phys, plat->num_phys);
+
+ return xhci_deregister(dev);
+}
+
+static const struct udevice_id xhci_crg_ids[] = {
+ { .compatible = "crg-xhci" },
+ { }
+};
+
+U_BOOT_DRIVER(xhci_crg) = {
+ .name = "xhci-crg",
+ .id = UCLASS_USB,
+ .of_match = xhci_crg_ids,
+ .probe = xhci_crg_probe,
+ .remove = xhci_crg_remove,
+ .ops = &xhci_usb_ops,
+ .priv_auto_alloc_size = sizeof(struct xhci_ctrl),
+ .platdata_auto_alloc_size = sizeof(struct xhci_crg_platdata),
+ .flags = DM_FLAG_ALLOC_PRIV_DMA,
+};
+#endif
diff --git a/drivers/usb/host/xhci-dwc3.c b/drivers/usb/host/xhci-dwc3.c
index 63df301..fa14571 100644
--- a/drivers/usb/host/xhci-dwc3.c
+++ b/drivers/usb/host/xhci-dwc3.c
@@ -137,7 +137,6 @@
void xhci_dwc3_phy_tuning_1(struct udevice *dev, int port)
{
- unsigned long phy_reg_base;
int ret, i;
struct xhci_dwc3_platdata *plat;
struct udevice *udev = dev;
@@ -152,13 +151,15 @@
return ;
}
}
-
}
static int xhci_dwc3_setup_phy(struct udevice *dev)
{
struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
int i, ret, count;
+#ifdef CONFIG_AML_USB
+ unsigned int usb_type = 0;
+#endif
/* Return if no phy declared */
if (!dev_read_prop(dev, "phys", NULL))
@@ -207,8 +208,6 @@
}
#ifdef CONFIG_AML_USB
- int usb_type = 0;
-
for (i = 0; i < plat->num_phys; i++) {
dev_read_u32((&plat->usb_phys[i])->dev, "phy-version", &usb_type);
if (usb_type == 2) {
@@ -235,33 +234,15 @@
return ret;
}
-static int xhci_dwc3_shutdown_phy(struct udevice *dev)
-{
- struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
- int i, ret;
-
- for (i = 0; i < plat->num_phys; i++) {
- if (!generic_phy_valid(&plat->usb_phys[i]))
- continue;
-
- ret = generic_phy_power_off(&plat->usb_phys[i]);
- ret |= generic_phy_exit(&plat->usb_phys[i]);
- if (ret) {
- pr_err("Can't shutdown USB PHY%d for %s\n",
- i, dev->name);
- }
- }
-
- return 0;
-}
-
static int xhci_dwc3_probe(struct udevice *dev)
{
struct xhci_hcor *hcor;
struct xhci_hccr *hccr;
struct dwc3 *dwc3_reg;
enum usb_dr_mode dr_mode;
+#ifndef CONFIG_AML_USB
struct xhci_dwc3_platdata *plat = dev_get_platdata(dev);
+#endif
int ret;
#ifdef CONFIG_AML_USB
diff --git a/drivers/usb/host/xhci-ring.c b/drivers/usb/host/xhci-ring.c
index 141aac2..2573fe6 100644
--- a/drivers/usb/host/xhci-ring.c
+++ b/drivers/usb/host/xhci-ring.c
@@ -495,8 +495,8 @@
field = le32_to_cpu(event->trans_event.flags);
BUG_ON(TRB_TO_SLOT_ID(field) != udev->slot_id);
BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
- BUG_ON(GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len
- != COMP_STOP)));
+ BUG_ON(GET_COMP_CODE(le32_to_cpu(event->trans_event.transfer_len))
+ != COMP_STOP);
xhci_acknowledge_event(ctrl);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
@@ -934,7 +934,6 @@
BUG_ON(TRB_TO_EP_INDEX(field) != ep_index);
xhci_acknowledge_event(ctrl);
}
- _udelay(10);
return (udev->status != USB_ST_NOT_PROC) ? 0 : -1;
diff --git a/drivers/usb/host/xhci.c b/drivers/usb/host/xhci.c
index 1eae743..dc9fcf4 100644
--- a/drivers/usb/host/xhci.c
+++ b/drivers/usb/host/xhci.c
@@ -654,6 +654,8 @@
ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
ctrl_ctx->drop_flags = 0;
+ xhci_flush_cache((uintptr_t)ctrl_ctx, sizeof(struct xhci_input_control_ctx));
+
xhci_queue_command(ctrl, (void *)ctrl_ctx, slot_id, 0, TRB_ADDR_DEV | TRB_BSR);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
if (!event)
@@ -663,12 +665,12 @@
switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
case COMP_CTX_STATE:
case COMP_EBADSLT:
- printf("Setup ERROR: address device command for slot %d.\n",
+ debug("Setup ERROR: address device command for slot %d.\n",
slot_id);
ret = -EINVAL;
break;
case COMP_TX_ERR:
- puts("Device not responding to set address.\n");
+ debug("Device not responding to set address.\n");
ret = -EPROTO;
break;
case COMP_DEV_ERR:
@@ -737,6 +739,8 @@
ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
ctrl_ctx->drop_flags = 0;
+ xhci_flush_cache((uintptr_t)ctrl_ctx, sizeof(struct xhci_input_control_ctx));
+
xhci_queue_command(ctrl, (void *)ctrl_ctx, slot_id, 0, TRB_ADDR_DEV);
event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id);
@@ -744,12 +748,12 @@
switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
case COMP_CTX_STATE:
case COMP_EBADSLT:
- printf("Setup ERROR: address device command for slot %d.\n",
+ debug("Setup ERROR: address device command for slot %d.\n",
slot_id);
ret = -EINVAL;
break;
case COMP_TX_ERR:
- puts("Device not responding to set address.\n");
+ debug("Device not responding to set address.\n");
ret = -EPROTO;
break;
case COMP_DEV_ERR:
@@ -963,6 +967,8 @@
return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
}
+#define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 12
+
/**
* Submits the Requests to the XHCI Host Controller
*
@@ -981,12 +987,12 @@
uint32_t reg;
volatile uint32_t *status_reg;
struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
- struct xhci_hccr *hccr = ctrl->hccr;
+ //struct xhci_hccr *hccr = ctrl->hccr;
struct xhci_hcor *hcor = ctrl->hcor;
- int max_ports = HCS_MAX_PORTS(xhci_readl(&hccr->cr_hcsparams1));
+ //int max_ports = HCS_MAX_PORTS(xhci_readl(&hccr->cr_hcsparams1));
if ((req->requesttype & USB_RT_PORT) &&
- le16_to_cpu(req->index) > max_ports) {
+ le16_to_cpu(req->index) > CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS) {
printf("The request port(%d) exceeds maximum port number\n",
le16_to_cpu(req->index) - 1);
return -EINVAL;
@@ -1311,7 +1317,7 @@
return -ENOMEM;
reg = xhci_readl(&hccr->cr_hcsparams1);
-#ifdef CONFIG_AML_USB
+#ifdef CONFIG_AML_USB2_PHY
descriptor.hub.bNbrPorts = usb2portnum;
#else
descriptor.hub.bNbrPorts = ((reg & HCS_MAX_PORTS_MASK) >>
@@ -1591,7 +1597,11 @@
device_get_uclass_id(udev) != UCLASS_USB;
udev = udev->parent)
;
+
+#ifdef CONFIG_USB_XHCI_DWC3
xhci_dwc3_phy_tuning_1(udev, port);
+#endif
+
return 0;
}
diff --git a/drivers/usb/musb-new/Kconfig b/drivers/usb/musb-new/Kconfig
index 123761e..f8f2205 100644
--- a/drivers/usb/musb-new/Kconfig
+++ b/drivers/usb/musb-new/Kconfig
@@ -62,4 +62,3 @@
help
All data is copied between memory and FIFO by the CPU.
DMA controllers are ignored.
-
diff --git a/drivers/usb/musb/Kconfig b/drivers/usb/musb/Kconfig
index a5fdb5c..2508b6e 100644
--- a/drivers/usb/musb/Kconfig
+++ b/drivers/usb/musb/Kconfig
@@ -18,4 +18,3 @@
config USB_AM35X
bool"Legacy MUSB AM35x"
depends on ARCH_OMAP2PLUS && !USB_OMAP3
-
diff --git a/drivers/usb/phy/Kconfig b/drivers/usb/phy/Kconfig
index b831577..8741553 100644
--- a/drivers/usb/phy/Kconfig
+++ b/drivers/usb/phy/Kconfig
@@ -13,4 +13,3 @@
config ROCKCHIP_USB2_PHY
bool "Rockchip USB2 PHY"
-
diff --git a/drivers/usb/roles/Kconfig b/drivers/usb/roles/Kconfig
new file mode 100644
index 0000000..1056346
--- /dev/null
+++ b/drivers/usb/roles/Kconfig
@@ -0,0 +1,14 @@
+# SPDX-License-Identifier: GPL-2.0
+
+config USB_ROLE_SWITCH
+ tristate "USB Role Switch Support"
+ help
+ USB Role Switch is a device that can select the USB role - host or
+ device - for a USB port (connector). In most cases dual-role capable
+ USB controller will also represent the switch, but on some platforms
+ multiplexer/demultiplexer switch is used to route the data lines on
+ the USB connector between separate USB host and device controllers.
+
+ Say Y here if your USB connectors support both device and host roles.
+ To compile the driver as module, choose M here: the module will be
+ called roles.ko.
diff --git a/drivers/usb/roles/Makefile b/drivers/usb/roles/Makefile
new file mode 100644
index 0000000..3fc6294
--- /dev/null
+++ b/drivers/usb/roles/Makefile
@@ -0,0 +1,4 @@
+# SPDX-License-Identifier: GPL-2.0
+
+obj-$(CONFIG_USB_ROLE_SWITCH) += roles.o
+roles-y := class.o
diff --git a/drivers/usb/roles/class.c b/drivers/usb/roles/class.c
new file mode 100644
index 0000000..634a950
--- /dev/null
+++ b/drivers/usb/roles/class.c
@@ -0,0 +1,98 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * USB Role Switch Support
+ *
+ * Copyright (C) 2018 Intel Corporation
+ * Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
+ * Hans de Goede <hdegoede@redhat.com>
+ */
+
+#include <dm/device.h>
+#include <linux/usb/role.h>
+#include <linux/device_type.h>
+#include <linux/usb/role.h>
+
+struct usb_role_switch {
+ struct udevice dev;
+ enum usb_role role;
+
+ /* From descriptor */
+ struct udevice *usb2_port;
+ struct udevice *usb3_port;
+ struct udevice *udc;
+ usb_role_switch_set_t set;
+ usb_role_switch_get_t get;
+ bool allow_userspace_control;
+};
+
+
+#define to_role_switch(d) container_of(d, struct usb_role_switch, dev)
+
+/**
+ * usb_role_switch_set_role - Set USB role for a switch
+ * @sw: USB role switch
+ * @role: USB role to be switched to
+ *
+ * Set USB role @role for @sw.
+ */
+int usb_role_switch_set_role(struct usb_role_switch *sw, enum usb_role role)
+{
+ // TODO: we don't have "usb-role-switch" in DTS
+ // Hardcode to No-OP until we plan to support "usb-role-switch"
+ int ret;
+
+ if (IS_ERR_OR_NULL(sw))
+ return 0;
+
+ return ret;
+}
+EXPORT_SYMBOL_GPL(usb_role_switch_set_role);
+
+/**
+ * usb_role_switch_get_role - Get the USB role for a switch
+ * @sw: USB role switch
+ *
+ * Depending on the role-switch-driver this function returns either a cached
+ * value of the last set role, or reads back the actual value from the hardware.
+ */
+enum usb_role usb_role_switch_get_role(struct usb_role_switch *sw)
+{
+ // TODO: we don't have "usb-role-switch" in DTS
+ // Hardcode to No-OP until we plan to support "usb-role-switch"
+ enum usb_role role;
+
+ if (IS_ERR_OR_NULL(sw))
+ return USB_ROLE_NONE;
+
+ return role;
+}
+EXPORT_SYMBOL_GPL(usb_role_switch_get_role);
+
+/**
+ * usb_role_switch_get - Find USB role switch linked with the caller
+ * @dev: The caller device
+ *
+ * Finds and returns role switch linked with @dev. The reference count for the
+ * found switch is incremented.
+ */
+struct usb_role_switch *usb_role_switch_get(struct udevice *dev)
+{
+ // TODO: we don't have "usb-role-switch" in DTS
+ // Hardcode to NULL until we plan to support "usb-role-switch"
+ return NULL;
+}
+EXPORT_SYMBOL_GPL(usb_role_switch_get);
+
+
+/**
+ * usb_role_switch_put - Release handle to a switch
+ * @sw: USB Role Switch
+ *
+ * Decrement reference count for @sw.
+ */
+void usb_role_switch_put(struct usb_role_switch *sw)
+{
+ // TODO: we don't have "usb-role-switch" in DTS
+ // Hardcode to No-OP until we plan to support "usb-role-switch"
+}
+EXPORT_SYMBOL_GPL(usb_role_switch_put);
diff --git a/drivers/usb/typec/Kconfig b/drivers/usb/typec/Kconfig
new file mode 100644
index 0000000..814deaf
--- /dev/null
+++ b/drivers/usb/typec/Kconfig
@@ -0,0 +1,10 @@
+menuconfig TYPEC
+ tristate "USB Type-C Support"
+ help
+ TypeC support.
+
+if TYPEC
+
+source "drivers/usb/typec/tcpm/Kconfig"
+
+endif # TYPEC
diff --git a/drivers/usb/typec/Makefile b/drivers/usb/typec/Makefile
new file mode 100644
index 0000000..d27ea32
--- /dev/null
+++ b/drivers/usb/typec/Makefile
@@ -0,0 +1,2 @@
+obj-y += class.o
+obj-$(CONFIG_TYPEC_TCPM) += tcpm/
diff --git a/drivers/usb/typec/class.c b/drivers/usb/typec/class.c
new file mode 100644
index 0000000..6bb8a53
--- /dev/null
+++ b/drivers/usb/typec/class.c
@@ -0,0 +1,484 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * USB Type-C Connector Class
+ *
+ * Copyright (C) 2017, Intel Corporation
+ * Author: Heikki Krogerus <heikki.krogerus@linux.intel.com>
+ */
+
+#include <dm/device.h>
+#include <dm/device_compat.h>
+#include <linux/compat.h>
+#include <linux/usb/typec.h>
+#include <linux/string.h>
+#include <linux/device_type.h>
+
+struct typec_partner {
+ struct udevice dev;
+ unsigned int usb_pd:1;
+ struct usb_pd_identity *identity;
+ enum typec_accessory accessory;
+};
+
+struct typec_port {
+ unsigned int id;
+ struct udevice dev;
+
+ int prefer_role;
+ enum typec_data_role data_role;
+ enum typec_role pwr_role;
+ enum typec_role vconn_role;
+ enum typec_pwr_opmode pwr_opmode;
+ enum typec_port_type port_type;
+ struct mutex port_type_lock;
+
+ enum typec_orientation orientation;
+
+ const struct typec_capability *cap;
+ const struct typec_operations *ops;
+};
+
+#define to_typec_port(_dev_) container_of(_dev_, struct typec_port, dev)
+#define to_typec_partner(_dev_) container_of(_dev_, struct typec_partner, dev)
+
+struct typec_platdata {
+ const struct device_type *type;
+};
+
+/*
+ * copy from mm/util.c
+ */
+void *kmemdup(const void *src, size_t len, gfp_t gfp)
+{
+ void *p;
+
+ p = kmalloc(len, gfp);
+ if (p)
+ memcpy(p, src, len);
+ return p;
+}
+
+/*
+ * replace ida_simple_get() in kernel as uboot is a single thread scenario.
+ */
+static unsigned int get_port_id(void) {
+ static unsigned int port_id_counter = 0;
+ return port_id_counter++;
+}
+
+const struct device_type typec_port_dev_type = {
+ .name = "typec_port",
+};
+
+static int match_string(const char * const *array, size_t n, const char *string)
+{
+ int index;
+ const char *item;
+
+ for (index = 0; index < n; index++) {
+ item = array[index];
+ if (!item)
+ break;
+ if (!strcmp(item, string))
+ return index;
+ }
+
+ return -EINVAL;
+}
+
+/* ------------------------------------------------------------------------- */
+/* Type-C Partners */
+
+static const struct device_type typec_partner_dev_type = {
+ .name = "typec_partner",
+};
+
+/**
+ * typec_partner_set_identity - Report result from Discover Identity command
+ * @partner: The partner updated identity values
+ *
+ * This routine is used to report that the result of Discover Identity USB power
+ * delivery command has become available.
+ */
+int typec_partner_set_identity(struct typec_partner *partner)
+{
+ if (!partner->identity)
+ return -EINVAL;
+ return 0;
+}
+EXPORT_SYMBOL_GPL(typec_partner_set_identity);
+
+/**
+ * typec_register_partner - Register a USB Type-C Partner
+ * @port: The USB Type-C Port the partner is connected to
+ * @desc: Description of the partner
+ *
+ * Registers a device for USB Type-C Partner described in @desc.
+ *
+ * Returns handle to the partner on success or ERR_PTR on failure.
+ */
+struct typec_partner *typec_register_partner(struct typec_port *port,
+ struct typec_partner_desc *desc)
+{
+ struct typec_partner *partner;
+ struct typec_platdata *plat;
+ char *name;
+
+ partner = kzalloc(sizeof(*partner), GFP_KERNEL);
+ if (!partner)
+ return ERR_PTR(-ENOMEM);
+
+ partner->usb_pd = desc->usb_pd;
+ partner->accessory = desc->accessory;
+
+ if (desc->identity) {
+ /*
+ * Creating directory for the identity only if the driver is
+ * able to provide data to it.
+ */
+ partner->identity = desc->identity;
+ }
+
+ partner->dev.parent = &port->dev;
+
+ plat = kzalloc(sizeof(*plat), GFP_KERNEL);
+ if (!plat)
+ return ERR_PTR(-ENOMEM);
+ plat->type = &typec_partner_dev_type;
+ partner->dev.platdata = plat;
+
+ name = kzalloc(32, GFP_KERNEL);
+ snprintf(name, 32, "%s-partner", port->dev.name);
+ partner->dev.name = name;
+
+ INIT_LIST_HEAD(&partner->dev.uclass_node);
+ INIT_LIST_HEAD(&partner->dev.child_head);
+ INIT_LIST_HEAD(&partner->dev.sibling_node);
+
+ /* put partner dev into port's successor list */
+ list_add_tail(&partner->dev.sibling_node, &port->dev.child_head);
+
+ return partner;
+}
+EXPORT_SYMBOL_GPL(typec_register_partner);
+
+/**
+ * typec_unregister_partner - Unregister a USB Type-C Partner
+ * @partner: The partner to be unregistered
+ *
+ * Unregister device created with typec_register_partner().
+ */
+void typec_unregister_partner(struct typec_partner *partner)
+{
+ if (!IS_ERR_OR_NULL(partner))
+ device_unregister(&partner->dev);
+}
+EXPORT_SYMBOL_GPL(typec_unregister_partner);
+
+/* ------------------------------------------------------------------------- */
+/* USB Type-C ports */
+
+static const char * const typec_roles[] = {
+ [TYPEC_SINK] = "sink",
+ [TYPEC_SOURCE] = "source",
+};
+
+static const char * const typec_port_power_roles[] = {
+ [TYPEC_PORT_SRC] = "source",
+ [TYPEC_PORT_SNK] = "sink",
+ [TYPEC_PORT_DRP] = "dual",
+};
+
+static const char * const typec_port_data_roles[] = {
+ [TYPEC_PORT_DFP] = "host",
+ [TYPEC_PORT_UFP] = "device",
+ [TYPEC_PORT_DRD] = "dual",
+};
+
+/* --------------------------------------- */
+/* Driver callbacks to report role updates */
+
+/**
+ * typec_set_data_role - Report data role change
+ * @port: The USB Type-C Port where the role was changed
+ * @role: The new data role
+ *
+ * This routine is used by the port drivers to report data role changes.
+ */
+void typec_set_data_role(struct typec_port *port, enum typec_data_role role)
+{
+ if (port->data_role == role)
+ return;
+
+ port->data_role = role;
+}
+EXPORT_SYMBOL_GPL(typec_set_data_role);
+
+/**
+ * typec_set_pwr_role - Report power role change
+ * @port: The USB Type-C Port where the role was changed
+ * @role: The new data role
+ *
+ * This routine is used by the port drivers to report power role changes.
+ */
+void typec_set_pwr_role(struct typec_port *port, enum typec_role role)
+{
+ if (port->pwr_role == role)
+ return;
+
+ port->pwr_role = role;
+}
+EXPORT_SYMBOL_GPL(typec_set_pwr_role);
+
+/**
+ * typec_set_vconn_role - Report VCONN source change
+ * @port: The USB Type-C Port which VCONN role changed
+ * @role: Source when @port is sourcing VCONN, or Sink when it's not
+ *
+ * This routine is used by the port drivers to report if the VCONN source is
+ * changes.
+ */
+void typec_set_vconn_role(struct typec_port *port, enum typec_role role)
+{
+ if (port->vconn_role == role)
+ return;
+
+ port->vconn_role = role;
+}
+EXPORT_SYMBOL_GPL(typec_set_vconn_role);
+
+/**
+ * typec_set_pwr_opmode - Report changed power operation mode
+ * @port: The USB Type-C Port where the mode was changed
+ * @opmode: New power operation mode
+ *
+ * This routine is used by the port drivers to report changed power operation
+ * mode in @port. The modes are USB (default), 1.5A, 3.0A as defined in USB
+ * Type-C specification, and "USB Power Delivery" when the power levels are
+ * negotiated with methods defined in USB Power Delivery specification.
+ */
+void typec_set_pwr_opmode(struct typec_port *port,
+ enum typec_pwr_opmode opmode)
+{
+ struct udevice *partner_dev;
+
+ if (port->pwr_opmode == opmode)
+ return;
+
+ port->pwr_opmode = opmode;
+
+ device_find_first_child(&port->dev, &partner_dev);
+ if (partner_dev) {
+ struct typec_partner *partner = to_typec_partner(partner_dev);
+
+ if (opmode == TYPEC_PWR_MODE_PD && !partner->usb_pd) {
+ partner->usb_pd = 1;
+ }
+ }
+}
+EXPORT_SYMBOL_GPL(typec_set_pwr_opmode);
+
+/**
+ * typec_find_port_power_role - Get the typec port power capability
+ * @name: port power capability string
+ *
+ * This routine is used to find the typec_port_type by its string name.
+ *
+ * Returns typec_port_type if success, otherwise negative error code.
+ */
+int typec_find_port_power_role(const char *name)
+{
+ return match_string(typec_port_power_roles,
+ ARRAY_SIZE(typec_port_power_roles), name);
+}
+EXPORT_SYMBOL_GPL(typec_find_port_power_role);
+
+/**
+ * typec_find_power_role - Find the typec one specific power role
+ * @name: power role string
+ *
+ * This routine is used to find the typec_role by its string name.
+ *
+ * Returns typec_role if success, otherwise negative error code.
+ */
+int typec_find_power_role(const char *name)
+{
+ return match_string(typec_roles, ARRAY_SIZE(typec_roles), name);
+}
+EXPORT_SYMBOL_GPL(typec_find_power_role);
+
+/**
+ * typec_find_port_data_role - Get the typec port data capability
+ * @name: port data capability string
+ *
+ * This routine is used to find the typec_port_data by its string name.
+ *
+ * Returns typec_port_data if success, otherwise negative error code.
+ */
+int typec_find_port_data_role(const char *name)
+{
+ return match_string(typec_port_data_roles,
+ ARRAY_SIZE(typec_port_data_roles), name);
+}
+EXPORT_SYMBOL_GPL(typec_find_port_data_role);
+
+/* ------------------------------------------ */
+/* API for Multiplexer/DeMultiplexer Switches */
+
+/**
+ * typec_set_orientation - Set USB Type-C cable plug orientation
+ * @port: USB Type-C Port
+ * @orientation: USB Type-C cable plug orientation
+ *
+ * Set cable plug orientation for @port.
+ */
+int typec_set_orientation(struct typec_port *port,
+ enum typec_orientation orientation)
+{
+ port->orientation = orientation;
+
+ return 0;
+}
+EXPORT_SYMBOL_GPL(typec_set_orientation);
+
+/**
+ * typec_get_orientation - Get USB Type-C cable plug orientation
+ * @port: USB Type-C Port
+ *
+ * Get current cable plug orientation for @port.
+ */
+enum typec_orientation typec_get_orientation(struct typec_port *port)
+{
+ return port->orientation;
+}
+EXPORT_SYMBOL_GPL(typec_get_orientation);
+
+/**
+ * typec_set_mode - Set mode of operation for USB Type-C connector
+ * @port: USB Type-C connector
+ * @mode: Accessory Mode, USB Operation or Safe State
+ *
+ * Configure @port for Accessory Mode @mode. This function will configure the
+ * muxes needed for @mode.
+ */
+int typec_set_mode(struct typec_port *port, int mode)
+{
+ return 0;
+}
+EXPORT_SYMBOL_GPL(typec_set_mode);
+
+/* --------------------------------------- */
+
+/**
+ * typec_get_drvdata - Return private driver data pointer
+ * @port: USB Type-C port
+ */
+void *typec_get_drvdata(struct typec_port *port)
+{
+ return dev_get_priv(&port->dev);
+}
+EXPORT_SYMBOL_GPL(typec_get_drvdata);
+
+/**
+ * typec_register_port - Register a USB Type-C Port
+ * @parent: Parent device
+ * @cap: Description of the port
+ *
+ * Registers a device for USB Type-C Port described in @cap.
+ *
+ * Returns handle to the port on success or ERR_PTR on failure.
+ */
+struct typec_port *typec_register_port(struct udevice *parent,
+ const struct typec_capability *cap)
+{
+ struct typec_port *port;
+ struct typec_platdata *plat;
+ int id;
+ char *name;
+
+ port = kzalloc(sizeof(*port), GFP_KERNEL);
+ if (!port)
+ return ERR_PTR(-ENOMEM);
+
+ id = get_port_id();
+ if (id < 0) {
+ kfree(port);
+ return ERR_PTR(id);
+ }
+
+ switch (cap->type) {
+ case TYPEC_PORT_SRC:
+ port->pwr_role = TYPEC_SOURCE;
+ port->vconn_role = TYPEC_SOURCE;
+ break;
+ case TYPEC_PORT_SNK:
+ port->pwr_role = TYPEC_SINK;
+ port->vconn_role = TYPEC_SINK;
+ break;
+ case TYPEC_PORT_DRP:
+ if (cap->prefer_role != TYPEC_NO_PREFERRED_ROLE)
+ port->pwr_role = cap->prefer_role;
+ else
+ port->pwr_role = TYPEC_SINK;
+ break;
+ }
+
+ switch (cap->data) {
+ case TYPEC_PORT_DFP:
+ port->data_role = TYPEC_HOST;
+ break;
+ case TYPEC_PORT_UFP:
+ port->data_role = TYPEC_DEVICE;
+ break;
+ case TYPEC_PORT_DRD:
+ if (cap->prefer_role == TYPEC_SOURCE)
+ port->data_role = TYPEC_HOST;
+ else
+ port->data_role = TYPEC_DEVICE;
+ break;
+ }
+
+ mutex_init(&port->port_type_lock);
+
+ port->id = id;
+ port->ops = cap->ops;
+ port->port_type = cap->type;
+ port->prefer_role = cap->prefer_role;
+
+ port->dev.parent = parent;
+ name = kzalloc(16, GFP_KERNEL);
+ snprintf(name, 16, "port%d", id);
+ port->dev.name = name;
+
+ plat = kzalloc(sizeof(*plat), GFP_KERNEL);
+ if (!plat)
+ return ERR_PTR(-ENOMEM);
+ plat->type = &typec_port_dev_type;
+ port->dev.platdata = plat;
+
+ port->dev.priv = cap->driver_data;
+
+ INIT_LIST_HEAD(&port->dev.uclass_node);
+ INIT_LIST_HEAD(&port->dev.child_head);
+ INIT_LIST_HEAD(&port->dev.sibling_node);
+
+ port->cap = kmemdup(cap, sizeof(*cap), GFP_KERNEL);
+ if (!port->cap) {
+ return ERR_PTR(-ENOMEM);
+ }
+ return port;
+}
+EXPORT_SYMBOL_GPL(typec_register_port);
+
+/**
+ * typec_unregister_port - Unregister a USB Type-C Port
+ * @port: The port to be unregistered
+ *
+ * Unregister device created with typec_register_port().
+ */
+void typec_unregister_port(struct typec_port *port)
+{
+ if (!IS_ERR_OR_NULL(port))
+ device_unregister(&port->dev);
+}
+EXPORT_SYMBOL_GPL(typec_unregister_port);
diff --git a/drivers/usb/typec/tcpm/Kconfig b/drivers/usb/typec/tcpm/Kconfig
new file mode 100644
index 0000000..7651bed
--- /dev/null
+++ b/drivers/usb/typec/tcpm/Kconfig
@@ -0,0 +1,31 @@
+config TYPEC_TCPM
+ tristate "USB Type-C Port Controller Manager"
+ depends on USB
+ select USB_ROLE_SWITCH
+ select POWER_SUPPLY
+ help
+ The Type-C Port Controller Manager provides a USB PD and USB Type-C
+ state machine for use with Type-C Port Controllers.
+
+if TYPEC_TCPM
+
+config TYPEC_TCPCI
+ tristate "Type-C Port Controller Interface driver"
+ depends on DM_I2C
+ select REGMAP_I2C
+ help
+ Type-C Port Controller driver for TCPCI-compliant controller.
+
+if TYPEC_TCPCI
+
+config TYPEC_RT1711H
+ tristate "Richtek RT1711H Type-C chip driver"
+ help
+ Richtek RT1711H Type-C chip driver that works with
+ Type-C Port Controller Manager to provide USB PD and USB
+ Type-C functionalities.
+
+endif # TYPEC_TCPCI
+
+
+endif # TYPEC_TCPM
diff --git a/drivers/usb/typec/tcpm/Makefile b/drivers/usb/typec/tcpm/Makefile
new file mode 100644
index 0000000..d3ce6f2
--- /dev/null
+++ b/drivers/usb/typec/tcpm/Makefile
@@ -0,0 +1,4 @@
+obj-y += tcpc-uclass.o
+obj-$(CONFIG_TYPEC_TCPM) += tcpm.o
+obj-$(CONFIG_TYPEC_TCPCI) += tcpci.o
+obj-$(CONFIG_TYPEC_RT1711H) += tcpci_rt1711h.o
diff --git a/drivers/usb/typec/tcpm/tcpc-uclass.c b/drivers/usb/typec/tcpm/tcpc-uclass.c
new file mode 100644
index 0000000..a3a5374
--- /dev/null
+++ b/drivers/usb/typec/tcpm/tcpc-uclass.c
@@ -0,0 +1,44 @@
+#include <common.h>
+#include <dm.h>
+#include <dm/device-internal.h>
+#include <dm/root.h>
+#include <dm/uclass-internal.h>
+#include <errno.h>
+#include <linux/printk.h>
+#include <stdio.h>
+#include <usb_tcpc.h>
+
+/* flag for the tcpc started / stopped status */
+char tcpc_started = 0;
+
+int tcpc_init(void)
+{
+ struct udevice *dev;
+ struct uclass *uc;
+ int ret;
+
+ pr_info("tcpc_init\n");
+ ret = uclass_get(UCLASS_USB_TCPC, &uc);
+ if (ret)
+ return ret;
+ for (uclass_find_first_device(UCLASS_USB_TCPC, &dev);
+ dev;
+ uclass_find_next_device(&dev)) {
+
+ pr_info("tcpc_init device_probe(%s) start \n", dev->name);
+ ret = device_probe(dev);
+ pr_info("tcpc_init device_probe(%s) done: %d\n", dev->name, ret);
+ if (ret)
+ return ret;
+ }
+
+ pr_info("tcpc_init done: %d \n", ret);
+ tcpc_started = 1;
+ return ret;
+}
+
+UCLASS_DRIVER(tcpc) = {
+ .id = UCLASS_USB_TCPC,
+ .name = "tcpc",
+ .per_device_platdata_auto_alloc_size = sizeof(struct tcpc_uc_plat),
+};
diff --git a/drivers/usb/typec/tcpm/tcpci.c b/drivers/usb/typec/tcpm/tcpci.c
new file mode 100644
index 0000000..37a5073
--- /dev/null
+++ b/drivers/usb/typec/tcpm/tcpci.c
@@ -0,0 +1,674 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015-2021 Google, Inc
+ *
+ * USB Type-C Port Controller Interface.
+ */
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <i2c.h>
+#include <linux/usb/pd.h>
+#include <linux/usb/tcpm.h>
+#include <linux/usb/typec.h>
+#include <time.h>
+#include <linux/delay.h>
+#include <dm/read.h>
+
+#include "tcpci.h"
+
+#define PD_RETRY_COUNT 3
+#define MAIN_LOOP_TIMEOUT_MS 5000
+/* buffer time after PS_RDY to handle following messages */
+#define MAIN_LOOP_BUFFER_MS 2000
+
+/* FIXME: bypass warn_on for pd testing */
+#if defined(WARN_ON)
+#undef WARN_ON
+#endif
+#define WARN_ON(_x) _x
+
+struct tcpci {
+ struct udevice *dev;
+
+ struct tcpm_port *port;
+
+ struct udevice *i2c;
+
+ bool controls_vbus;
+
+ struct tcpc_dev tcpc;
+ struct tcpci_data *data;
+};
+
+struct tcpci_chip {
+ struct tcpci *tcpci;
+ struct tcpci_data data;
+};
+
+static inline struct tcpci *tcpc_to_tcpci(struct tcpc_dev *tcpc)
+{
+ return container_of(tcpc, struct tcpci, tcpc);
+}
+
+static int tcpci_read16(struct tcpci *tcpci, unsigned int reg, u16 *val)
+{
+ return dm_i2c_read(tcpci->i2c, reg, (uint8_t*) val, sizeof(u16));
+}
+
+static int tcpci_write16(struct tcpci *tcpci, unsigned int reg, u16 val)
+{
+ return dm_i2c_write(tcpci->i2c, reg, (uint8_t*) &val, sizeof(u16));
+}
+
+static int tcpci_set_cc(struct tcpc_dev *tcpc, enum typec_cc_status cc)
+{
+ struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+ uint8_t reg;
+ int ret;
+
+ switch (cc) {
+ case TYPEC_CC_RA:
+ reg = (TCPC_ROLE_CTRL_CC_RA << TCPC_ROLE_CTRL_CC1_SHIFT) |
+ (TCPC_ROLE_CTRL_CC_RA << TCPC_ROLE_CTRL_CC2_SHIFT);
+ break;
+ case TYPEC_CC_RD:
+ reg = (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) |
+ (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT);
+ break;
+ case TYPEC_CC_RP_DEF:
+ reg = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) |
+ (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT) |
+ (TCPC_ROLE_CTRL_RP_VAL_DEF <<
+ TCPC_ROLE_CTRL_RP_VAL_SHIFT);
+ break;
+ case TYPEC_CC_RP_1_5:
+ reg = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) |
+ (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT) |
+ (TCPC_ROLE_CTRL_RP_VAL_1_5 <<
+ TCPC_ROLE_CTRL_RP_VAL_SHIFT);
+ break;
+ case TYPEC_CC_RP_3_0:
+ reg = (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) |
+ (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT) |
+ (TCPC_ROLE_CTRL_RP_VAL_3_0 <<
+ TCPC_ROLE_CTRL_RP_VAL_SHIFT);
+ break;
+ case TYPEC_CC_OPEN:
+ default:
+ reg = (TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC1_SHIFT) |
+ (TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC2_SHIFT);
+ break;
+ }
+
+ ret = dm_i2c_reg_write(tcpci->i2c, TCPC_ROLE_CTRL, reg);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int tcpci_start_toggling(struct tcpc_dev *tcpc,
+ enum typec_port_type port_type,
+ enum typec_cc_status cc)
+{
+ int ret;
+ struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+ uint8_t reg = TCPC_ROLE_CTRL_DRP;
+
+ if (port_type != TYPEC_PORT_DRP)
+ return -EOPNOTSUPP;
+
+ /* Handle vendor drp toggling */
+ if (tcpci->data->start_drp_toggling) {
+ ret = tcpci->data->start_drp_toggling(tcpci, tcpci->data, cc);
+ if (ret < 0)
+ return ret;
+ }
+
+ switch (cc) {
+ default:
+ case TYPEC_CC_RP_DEF:
+ reg |= (TCPC_ROLE_CTRL_RP_VAL_DEF <<
+ TCPC_ROLE_CTRL_RP_VAL_SHIFT);
+ break;
+ case TYPEC_CC_RP_1_5:
+ reg |= (TCPC_ROLE_CTRL_RP_VAL_1_5 <<
+ TCPC_ROLE_CTRL_RP_VAL_SHIFT);
+ break;
+ case TYPEC_CC_RP_3_0:
+ reg |= (TCPC_ROLE_CTRL_RP_VAL_3_0 <<
+ TCPC_ROLE_CTRL_RP_VAL_SHIFT);
+ break;
+ }
+
+ if (cc == TYPEC_CC_RD)
+ reg |= (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) |
+ (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT);
+ else
+ reg |= (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) |
+ (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT);
+ ret = dm_i2c_reg_write(tcpci->i2c, TCPC_ROLE_CTRL, reg);
+ if (ret < 0)
+ return ret;
+ return dm_i2c_reg_write(tcpci->i2c, TCPC_COMMAND,
+ TCPC_CMD_LOOK4CONNECTION);
+}
+
+static enum typec_cc_status tcpci_to_typec_cc(unsigned int cc, bool sink)
+{
+ switch (cc) {
+ case 0x1:
+ return sink ? TYPEC_CC_RP_DEF : TYPEC_CC_RA;
+ case 0x2:
+ return sink ? TYPEC_CC_RP_1_5 : TYPEC_CC_RD;
+ case 0x3:
+ if (sink)
+ return TYPEC_CC_RP_3_0;
+ /* fall through */
+ case 0x0:
+ default:
+ return TYPEC_CC_OPEN;
+ }
+}
+
+static int tcpci_get_cc(struct tcpc_dev *tcpc,
+ enum typec_cc_status *cc1, enum typec_cc_status *cc2)
+{
+ struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+ uint8_t reg;
+ int ret;
+ int cc1_sink = 0, cc2_sink = 0;
+
+ if (tcpci->data->get_cc)
+ return tcpci->data->get_cc(tcpci, tcpci->data, cc1, cc2);
+
+ ret = dm_i2c_read(tcpci->i2c, TCPC_ROLE_CTRL, ®, 1);
+ if (!ret) {
+ if (((reg >> TCPC_ROLE_CTRL_CC1_SHIFT) &
+ TCPC_ROLE_CTRL_CC1_MASK) == TCPC_ROLE_CTRL_CC_RD)
+ cc1_sink = 1;
+ if (((reg >> TCPC_ROLE_CTRL_CC2_SHIFT) &
+ TCPC_ROLE_CTRL_CC2_MASK) == TCPC_ROLE_CTRL_CC_RD)
+ cc2_sink = 1;
+ }
+
+ ret = dm_i2c_read(tcpci->i2c, TCPC_CC_STATUS, ®, 1);
+ if (!ret)
+ return ret;
+
+ *cc1 = tcpci_to_typec_cc((reg >> TCPC_CC_STATUS_CC1_SHIFT) &
+ TCPC_CC_STATUS_CC1_MASK,
+ (reg & TCPC_CC_STATUS_TERM) | cc1_sink);
+ *cc2 = tcpci_to_typec_cc((reg >> TCPC_CC_STATUS_CC2_SHIFT) &
+ TCPC_CC_STATUS_CC2_MASK,
+ (reg & TCPC_CC_STATUS_TERM) | cc2_sink);
+
+ return 0;
+}
+
+static int tcpci_set_polarity(struct tcpc_dev *tcpc,
+ enum typec_cc_polarity polarity)
+{
+ struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+ uint8_t reg;
+ int ret;
+
+ if (tcpci->data->set_polarity)
+ return tcpci->data->set_polarity(tcpci, tcpci->data, polarity);
+
+ /* Keep the disconnect cc line open */
+ ret = dm_i2c_read(tcpci->i2c, TCPC_ROLE_CTRL, ®, 1);
+ if (ret < 0)
+ return ret;
+
+ if (polarity == TYPEC_POLARITY_CC2)
+ reg |= TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC1_SHIFT;
+ else
+ reg |= TCPC_ROLE_CTRL_CC_OPEN << TCPC_ROLE_CTRL_CC2_SHIFT;
+ ret = dm_i2c_reg_write(tcpci->i2c, TCPC_ROLE_CTRL, reg);
+ if (ret < 0)
+ return ret;
+
+ return dm_i2c_reg_write(tcpci->i2c, TCPC_TCPC_CTRL,
+ (polarity == TYPEC_POLARITY_CC2) ?
+ TCPC_TCPC_CTRL_ORIENTATION : 0);
+}
+
+static int tcpci_set_vconn(struct tcpc_dev *tcpc, bool enable)
+{
+ struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+ int ret;
+ uint8_t reg, mask, val;
+
+ /* Handle vendor set vconn */
+ if (tcpci->data->set_vconn) {
+ ret = tcpci->data->set_vconn(tcpci, tcpci->data, enable);
+ if (ret < 0)
+ return ret;
+ }
+
+
+ ret = dm_i2c_read(tcpci->i2c, TCPC_POWER_CTRL, ®, 1);
+ if (ret < 0)
+ return ret;
+ mask = TCPC_POWER_CTRL_VCONN_ENABLE;
+ reg &= ~mask;
+ val = enable ? TCPC_POWER_CTRL_VCONN_ENABLE : 0;
+
+ return dm_i2c_reg_write(tcpci->i2c, TCPC_POWER_CTRL,
+ val | reg);
+}
+
+static int tcpci_set_roles(struct tcpc_dev *tcpc, bool attached,
+ enum typec_role role, enum typec_data_role data)
+{
+ struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+ uint8_t reg;
+ int ret;
+
+ reg = PD_REV20 << TCPC_MSG_HDR_INFO_REV_SHIFT;
+ if (role == TYPEC_SOURCE)
+ reg |= TCPC_MSG_HDR_INFO_PWR_ROLE;
+ if (data == TYPEC_HOST)
+ reg |= TCPC_MSG_HDR_INFO_DATA_ROLE;
+ ret = dm_i2c_reg_write(tcpci->i2c, TCPC_MSG_HDR_INFO, reg);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int tcpci_set_pd_rx(struct tcpc_dev *tcpc, bool enable)
+{
+ struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+ uint8_t reg = 0;
+ int ret;
+
+ if (enable)
+ reg = TCPC_RX_DETECT_SOP | TCPC_RX_DETECT_HARD_RESET;
+ ret = dm_i2c_reg_write(tcpci->i2c, TCPC_RX_DETECT, reg);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int tcpci_get_vbus(struct tcpc_dev *tcpc)
+{
+ struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+ uint8_t reg;
+ int ret;
+
+ ret = dm_i2c_read(tcpci->i2c, TCPC_POWER_STATUS, ®, 1);
+ if (ret < 0)
+ return ret;
+
+ return !!(reg & TCPC_POWER_STATUS_VBUS_PRES);
+}
+
+static int tcpci_set_vbus(struct tcpc_dev *tcpc, bool source, bool sink)
+{
+ struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+ int ret;
+
+ /* Disable both source and sink first before enabling anything */
+
+ if (!source) {
+ ret = dm_i2c_reg_write(tcpci->i2c, TCPC_COMMAND,
+ TCPC_CMD_DISABLE_SRC_VBUS);
+ if (ret < 0)
+ return ret;
+ }
+
+ if (!sink) {
+ ret = dm_i2c_reg_write(tcpci->i2c, TCPC_COMMAND,
+ TCPC_CMD_DISABLE_SINK_VBUS);
+ if (ret < 0)
+ return ret;
+ }
+
+ if (source) {
+ ret = dm_i2c_reg_write(tcpci->i2c, TCPC_COMMAND,
+ TCPC_CMD_SRC_VBUS_DEFAULT);
+ if (ret < 0)
+ return ret;
+ }
+
+ if (sink) {
+ ret = dm_i2c_reg_write(tcpci->i2c, TCPC_COMMAND,
+ TCPC_CMD_SINK_VBUS);
+ if (ret < 0)
+ return ret;
+ }
+
+ return 0;
+}
+
+static int tcpci_pd_transmit(struct tcpc_dev *tcpc,
+ enum tcpm_transmit_type type,
+ const struct pd_message *msg)
+{
+ struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+ u16 header = msg ? le16_to_cpu(msg->header) : 0;
+ uint8_t reg;
+ unsigned int cnt;
+ int ret;
+ pr_debug("%s %d\n", __func__, (int) type);
+
+ cnt = msg ? pd_header_cnt(header) * 4 : 0;
+ ret = dm_i2c_reg_write(tcpci->i2c, TCPC_TX_BYTE_CNT, cnt + 2);
+ if (ret < 0)
+ return ret;
+
+ ret = tcpci_write16(tcpci, TCPC_TX_HDR, header);
+ if (ret < 0)
+ return ret;
+
+ if (cnt > 0) {
+ ret = dm_i2c_write(tcpci->i2c, TCPC_TX_DATA,
+ (uint8_t*) &msg->payload, cnt);
+ if (ret < 0)
+ return ret;
+ }
+
+ reg = (PD_RETRY_COUNT << TCPC_TRANSMIT_RETRY_SHIFT) |
+ (type << TCPC_TRANSMIT_TYPE_SHIFT);
+ ret = dm_i2c_reg_write(tcpci->i2c, TCPC_TRANSMIT, reg);
+ if (ret < 0)
+ return ret;
+
+ return 0;
+}
+
+static int tcpci_get_tx_status(struct tcpc_dev *tcpc,
+ enum tcpm_transmit_status *status)
+{
+ struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+ u16 alert;
+ int ret;
+
+ ret = tcpci_read16(tcpci, TCPC_ALERT, &alert);
+ pr_debug("%s read ALERT ret:%d\n", __func__, ret);
+ if (ret) {
+ return ret;
+ }
+ if (alert & TCPC_ALERT_TX_SUCCESS)
+ *status = TCPC_TX_SUCCESS;
+ else if (alert & TCPC_ALERT_TX_DISCARDED)
+ *status = TCPC_TX_DISCARDED;
+ else if (alert & TCPC_ALERT_TX_FAILED)
+ *status = TCPC_TX_FAILED;
+
+ pr_debug("%s status = %d\n", __func__, *status);
+ return 0;
+}
+
+static int tcpci_init(struct tcpc_dev *tcpc)
+{
+ struct tcpci *tcpci = tcpc_to_tcpci(tcpc);
+ unsigned long timeout_ms = get_timer(0) + 2000; /* XXX */
+ uint8_t reg;
+ int ret;
+
+ while (time_before(get_timer(0), timeout_ms)) {
+ ret = dm_i2c_read(tcpci->i2c, TCPC_POWER_STATUS, ®, 1);
+ if (ret < 0)
+ return ret;
+ if (!(reg & TCPC_POWER_STATUS_UNINIT))
+ break;
+ udelay(10000);
+ }
+ if (time_after(get_timer(0), timeout_ms))
+ return -ETIMEDOUT;
+
+ /* Handle vendor init */
+ if (tcpci->data->init) {
+ ret = tcpci->data->init(tcpci, tcpci->data);
+ if (ret < 0)
+ return ret;
+ }
+
+ /* Clear all events */
+ ret = tcpci_write16(tcpci, TCPC_ALERT, 0xffff);
+ if (ret < 0)
+ return ret;
+
+ if (tcpci->controls_vbus)
+ reg = TCPC_POWER_STATUS_VBUS_PRES;
+ else
+ reg = 0;
+
+ ret = dm_i2c_reg_write(tcpci->i2c, TCPC_POWER_STATUS_MASK, reg);
+ if (ret < 0)
+ return ret;
+
+ /* Enable Vbus detection */
+ ret = dm_i2c_reg_write(tcpci->i2c, TCPC_COMMAND,
+ TCPC_CMD_ENABLE_VBUS_DETECT);
+ if (ret < 0)
+ return ret;
+
+ reg = TCPC_ALERT_TX_SUCCESS | TCPC_ALERT_TX_FAILED |
+ TCPC_ALERT_TX_DISCARDED | TCPC_ALERT_RX_STATUS |
+ TCPC_ALERT_RX_HARD_RST | TCPC_ALERT_CC_STATUS;
+ if (tcpci->controls_vbus)
+ reg |= TCPC_ALERT_POWER_STATUS;
+ //tcpci_read16(tcpci, TCPC_ALERT_MASK, &mask);
+ ret = tcpci_write16(tcpci, TCPC_ALERT_MASK, reg);
+ //tcpci_read16(tcpci, TCPC_ALERT_MASK, &mask);
+ return ret;
+}
+
+int tcpci_check_alert(struct tcpci *tcpci)
+{
+ u16 status;
+
+ tcpci_read16(tcpci, TCPC_ALERT, &status);
+
+ /*
+ * Clear alert status for everything except RX_STATUS, which shouldn't
+ * be cleared until we have successfully retrieved message.
+ */
+ if (status & ~TCPC_ALERT_RX_STATUS)
+ tcpci_write16(tcpci, TCPC_ALERT,
+ status & ~TCPC_ALERT_RX_STATUS);
+
+ if (status & TCPC_ALERT_CC_STATUS)
+ tcpm_cc_change(tcpci->port);
+
+ if (status & TCPC_ALERT_POWER_STATUS) {
+ uint8_t reg;
+
+ dm_i2c_read(tcpci->i2c, TCPC_POWER_STATUS_MASK, ®, 1);
+
+ /*
+ * If power status mask has been reset, then the TCPC
+ * has reset.
+ */
+ if (reg == 0xff)
+ tcpm_tcpc_reset(tcpci->port);
+ else
+ tcpm_vbus_change(tcpci->port);
+ }
+
+ if (status & TCPC_ALERT_RX_STATUS) {
+ struct pd_message msg;
+ uint8_t cnt;
+ int payload_cnt;
+ u16 header;
+
+ pr_warn("tcpci got RX_STATUS\n");
+ dm_i2c_read(tcpci->i2c, TCPC_RX_BYTE_CNT, &cnt, 1);
+ /*
+ * 'cnt' corresponds to READABLE_BYTE_COUNT in section 4.4.14
+ * of the TCPCI spec [Rev 2.0 Ver 1.0 October 2017] and is
+ * defined in table 4-36 as one greater than the number of
+ * bytes received. And that number includes the header. So:
+ */
+ if (cnt > 3)
+ payload_cnt = cnt - (1 + sizeof(msg.header));
+ else
+ payload_cnt = 0;
+
+ tcpci_read16(tcpci, TCPC_RX_HDR, &header);
+ msg.header = cpu_to_le16(header);
+
+ if (WARN_ON(payload_cnt > sizeof(msg.payload))) {
+ pr_err("WARN_ON: cnt=%u > msg.payload=%d\n !!!!!", payload_cnt,
+ (int)sizeof(msg.payload));
+ payload_cnt = sizeof(msg.payload);
+ }
+
+ if (payload_cnt > 0)
+ dm_i2c_read(tcpci->i2c, TCPC_RX_DATA,
+ (uint8_t*) &msg.payload, payload_cnt);
+
+ /* Read complete, clear RX status alert bit */
+ tcpci_write16(tcpci, TCPC_ALERT, TCPC_ALERT_RX_STATUS);
+
+ tcpm_pd_receive(tcpci->port, &msg);
+ }
+
+ if (status & TCPC_ALERT_RX_HARD_RST)
+ tcpm_pd_hard_reset(tcpci->port);
+
+ if (status & TCPC_ALERT_TX_SUCCESS)
+ tcpm_pd_transmit_complete(tcpci->port, TCPC_TX_SUCCESS);
+ else if (status & TCPC_ALERT_TX_DISCARDED)
+ tcpm_pd_transmit_complete(tcpci->port, TCPC_TX_DISCARDED);
+ else if (status & TCPC_ALERT_TX_FAILED)
+ tcpm_pd_transmit_complete(tcpci->port, TCPC_TX_FAILED);
+
+ return 0;
+}
+
+static int tcpci_remove(struct tcpci *tcpci)
+{
+ int err;
+
+ /* Disable chip interrupts before unregistering port */
+ err = tcpci_write16(tcpci, TCPC_ALERT_MASK, 0);
+ if (err < 0)
+ return err;
+
+ tcpci_unregister_port(tcpci);
+ return 0;
+}
+
+int tcpci_set_bist(struct tcpci *tcpci, bool enable)
+{
+ int ret;
+ u8 reg;
+
+ ret = dm_i2c_read(tcpci->i2c, TCPC_TCPC_CTRL, ®, 1);
+ if (ret)
+ return ret;
+
+ if (enable)
+ reg |= TCPC_TCPC_CTRL_BIST;
+ else
+ reg &= ~TCPC_TCPC_CTRL_BIST;
+
+ return dm_i2c_reg_write(tcpci->i2c, TCPC_TCPC_CTRL, reg);
+}
+
+int tcpci_main_loop(struct tcpci *tcpci)
+{
+ ulong timeout = get_timer(0) + MAIN_LOOP_TIMEOUT_MS;
+ ulong time = get_timer(0);
+
+ pr_info("%s starts at %lu.\n", __func__, time);
+
+ while (time_before(get_timer(0), timeout)) {
+ time = get_timer(0);
+ tcpci_check_alert(tcpci);
+ tcpm_handle_pd_event(tcpci->port);
+ tcpm_run_state_machine(tcpci->port);
+
+ if (tcpm_is_snk_ready(tcpci->port)) {
+ if (time_before(time + MAIN_LOOP_BUFFER_MS, timeout)) {
+ /* Reduce timeout to PS_RDY timestamp + MAIN_LOOP_BUFFER_MS
+ * The buffer is to handle some follow-up messages like DR_SWAP,
+ * VCONN_SWAP.
+ */
+ timeout = time + MAIN_LOOP_BUFFER_MS;
+ }
+ }
+ }
+
+ /* TCPC Spec 4.4.5.1: enable BIST to send GOOD_CRC unconditionally
+ * without buffering in the gap before kernel driver is ready.
+ */
+ tcpci_set_bist(tcpci, 1);
+
+ tcpci_remove(tcpci);
+
+ pr_info("%s finishes at %lu.\n", __func__, time);
+ pr_info("TCPM is SNK_READY: %d.\n", tcpm_is_snk_ready(tcpci->port));
+ return 0;
+}
+
+static int tcpci_parse_config(struct tcpci *tcpci)
+{
+ tcpci->controls_vbus = true; /* XXX */
+ ofnode ofnode;
+ ofnode = ofnode_find_subnode(dev_ofnode(tcpci->dev),
+ "connector");
+ if (!ofnode_valid(ofnode)) {
+ dev_err(tcpci->dev, "Can't find connector node.\n");
+ return -EINVAL;
+ }
+
+ tcpci->tcpc.ofnode = devm_kzalloc(tcpci->dev, sizeof(ofnode), GFP_KERNEL);
+ if (!tcpci->tcpc.ofnode)
+ return -ENOMEM;
+
+ *tcpci->tcpc.ofnode = ofnode;
+ return 0;
+}
+
+struct tcpci *tcpci_register_port(struct udevice *dev, struct tcpci_data *data)
+{
+ struct tcpci *tcpci;
+ int err;
+
+ tcpci = devm_kzalloc(dev, sizeof(*tcpci), GFP_KERNEL);
+ if (!tcpci)
+ return ERR_PTR(-ENOMEM);
+
+ tcpci->dev = dev;
+ tcpci->data = data;
+ tcpci->i2c = data->i2c;
+
+ tcpci->tcpc.init = tcpci_init;
+ tcpci->tcpc.get_vbus = tcpci_get_vbus;
+ tcpci->tcpc.set_vbus = tcpci_set_vbus;
+ tcpci->tcpc.set_cc = tcpci_set_cc;
+ tcpci->tcpc.get_cc = tcpci_get_cc;
+ tcpci->tcpc.set_polarity = tcpci_set_polarity;
+ tcpci->tcpc.set_vconn = tcpci_set_vconn;
+ tcpci->tcpc.start_toggling = tcpci_start_toggling;
+
+ tcpci->tcpc.set_pd_rx = tcpci_set_pd_rx;
+ tcpci->tcpc.set_roles = tcpci_set_roles;
+ tcpci->tcpc.pd_transmit = tcpci_pd_transmit;
+ tcpci->tcpc.get_tx_status = tcpci_get_tx_status;;
+
+ err = tcpci_parse_config(tcpci);
+ if (err < 0)
+ return ERR_PTR(err);
+
+ tcpci->port = tcpm_register_port(tcpci->dev, &tcpci->tcpc);
+ if (IS_ERR(tcpci->port))
+ return ERR_CAST(tcpci->port);
+
+ return tcpci;
+}
+EXPORT_SYMBOL_GPL(tcpci_register_port);
+
+void tcpci_unregister_port(struct tcpci *tcpci)
+{
+ tcpm_unregister_port(tcpci->port);
+}
+EXPORT_SYMBOL_GPL(tcpci_unregister_port);
diff --git a/drivers/usb/typec/tcpm/tcpci.h b/drivers/usb/typec/tcpm/tcpci.h
new file mode 100644
index 0000000..934c13b
--- /dev/null
+++ b/drivers/usb/typec/tcpm/tcpci.h
@@ -0,0 +1,147 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2015-2021 Google, Inc
+ *
+ * USB Type-C Port Controller Interface.
+ */
+
+#ifndef __LINUX_USB_TCPCI_H
+#define __LINUX_USB_TCPCI_H
+
+#include <dm/device.h>
+#include <linux/usb/tcpm.h>
+
+#define TCPC_VENDOR_ID 0x0
+#define TCPC_PRODUCT_ID 0x2
+#define TCPC_BCD_DEV 0x4
+#define TCPC_TC_REV 0x6
+#define TCPC_PD_REV 0x8
+#define TCPC_PD_INT_REV 0xa
+
+#define TCPC_ALERT 0x10
+#define TCPC_ALERT_VBUS_DISCNCT BIT(11)
+#define TCPC_ALERT_RX_BUF_OVF BIT(10)
+#define TCPC_ALERT_FAULT BIT(9)
+#define TCPC_ALERT_V_ALARM_LO BIT(8)
+#define TCPC_ALERT_V_ALARM_HI BIT(7)
+#define TCPC_ALERT_TX_SUCCESS BIT(6)
+#define TCPC_ALERT_TX_DISCARDED BIT(5)
+#define TCPC_ALERT_TX_FAILED BIT(4)
+#define TCPC_ALERT_RX_HARD_RST BIT(3)
+#define TCPC_ALERT_RX_STATUS BIT(2)
+#define TCPC_ALERT_POWER_STATUS BIT(1)
+#define TCPC_ALERT_CC_STATUS BIT(0)
+
+#define TCPC_ALERT_MASK 0x12
+#define TCPC_POWER_STATUS_MASK 0x14
+#define TCPC_FAULT_STATUS_MASK 0x15
+#define TCPC_CONFIG_STD_OUTPUT 0x18
+
+#define TCPC_TCPC_CTRL 0x19
+#define TCPC_TCPC_CTRL_ORIENTATION BIT(0)
+#define TCPC_TCPC_CTRL_BIST BIT(1)
+
+#define TCPC_ROLE_CTRL 0x1a
+#define TCPC_ROLE_CTRL_DRP BIT(6)
+#define TCPC_ROLE_CTRL_RP_VAL_SHIFT 4
+#define TCPC_ROLE_CTRL_RP_VAL_MASK 0x3
+#define TCPC_ROLE_CTRL_RP_VAL_DEF 0x0
+#define TCPC_ROLE_CTRL_RP_VAL_1_5 0x1
+#define TCPC_ROLE_CTRL_RP_VAL_3_0 0x2
+#define TCPC_ROLE_CTRL_CC2_SHIFT 2
+#define TCPC_ROLE_CTRL_CC2_MASK 0x3
+#define TCPC_ROLE_CTRL_CC1_SHIFT 0
+#define TCPC_ROLE_CTRL_CC1_MASK 0x3
+#define TCPC_ROLE_CTRL_CC_RA 0x0
+#define TCPC_ROLE_CTRL_CC_RP 0x1
+#define TCPC_ROLE_CTRL_CC_RD 0x2
+#define TCPC_ROLE_CTRL_CC_OPEN 0x3
+
+#define TCPC_FAULT_CTRL 0x1b
+
+#define TCPC_POWER_CTRL 0x1c
+#define TCPC_POWER_CTRL_VCONN_ENABLE BIT(0)
+
+#define TCPC_CC_STATUS 0x1d
+#define TCPC_CC_STATUS_TOGGLING BIT(5)
+#define TCPC_CC_STATUS_TERM BIT(4)
+#define TCPC_CC_STATUS_CC2_SHIFT 2
+#define TCPC_CC_STATUS_CC2_MASK 0x3
+#define TCPC_CC_STATUS_CC1_SHIFT 0
+#define TCPC_CC_STATUS_CC1_MASK 0x3
+
+#define TCPC_POWER_STATUS 0x1e
+#define TCPC_POWER_STATUS_UNINIT BIT(6)
+#define TCPC_POWER_STATUS_VBUS_DET BIT(3)
+#define TCPC_POWER_STATUS_VBUS_PRES BIT(2)
+
+#define TCPC_FAULT_STATUS 0x1f
+
+#define TCPC_COMMAND 0x23
+#define TCPC_CMD_WAKE_I2C 0x11
+#define TCPC_CMD_DISABLE_VBUS_DETECT 0x22
+#define TCPC_CMD_ENABLE_VBUS_DETECT 0x33
+#define TCPC_CMD_DISABLE_SINK_VBUS 0x44
+#define TCPC_CMD_SINK_VBUS 0x55
+#define TCPC_CMD_DISABLE_SRC_VBUS 0x66
+#define TCPC_CMD_SRC_VBUS_DEFAULT 0x77
+#define TCPC_CMD_SRC_VBUS_HIGH 0x88
+#define TCPC_CMD_LOOK4CONNECTION 0x99
+#define TCPC_CMD_RXONEMORE 0xAA
+#define TCPC_CMD_I2C_IDLE 0xFF
+
+#define TCPC_DEV_CAP_1 0x24
+#define TCPC_DEV_CAP_2 0x26
+#define TCPC_STD_INPUT_CAP 0x28
+#define TCPC_STD_OUTPUT_CAP 0x29
+
+#define TCPC_MSG_HDR_INFO 0x2e
+#define TCPC_MSG_HDR_INFO_DATA_ROLE BIT(3)
+#define TCPC_MSG_HDR_INFO_PWR_ROLE BIT(0)
+#define TCPC_MSG_HDR_INFO_REV_SHIFT 1
+#define TCPC_MSG_HDR_INFO_REV_MASK 0x3
+
+#define TCPC_RX_DETECT 0x2f
+#define TCPC_RX_DETECT_HARD_RESET BIT(5)
+#define TCPC_RX_DETECT_SOP BIT(0)
+
+#define TCPC_RX_BYTE_CNT 0x30
+#define TCPC_RX_BUF_FRAME_TYPE 0x31
+#define TCPC_RX_HDR 0x32
+#define TCPC_RX_DATA 0x34 /* through 0x4f */
+
+#define TCPC_TRANSMIT 0x50
+#define TCPC_TRANSMIT_RETRY_SHIFT 4
+#define TCPC_TRANSMIT_RETRY_MASK 0x3
+#define TCPC_TRANSMIT_TYPE_SHIFT 0
+#define TCPC_TRANSMIT_TYPE_MASK 0x7
+
+#define TCPC_TX_BYTE_CNT 0x51
+#define TCPC_TX_HDR 0x52
+#define TCPC_TX_DATA 0x54 /* through 0x6f */
+
+#define TCPC_VBUS_VOLTAGE 0x70
+#define TCPC_VBUS_SINK_DISCONNECT_THRESH 0x72
+#define TCPC_VBUS_STOP_DISCHARGE_THRESH 0x74
+#define TCPC_VBUS_VOLTAGE_ALARM_HI_CFG 0x76
+#define TCPC_VBUS_VOLTAGE_ALARM_LO_CFG 0x78
+
+struct tcpci;
+struct tcpci_data {
+ struct udevice *i2c;
+ int (*init)(struct tcpci *tcpci, struct tcpci_data *data);
+ int (*get_cc)(struct tcpci *tcpci, struct tcpci_data *data,
+ enum typec_cc_status *cc1, enum typec_cc_status *cc2);
+ int (*set_polarity)(struct tcpci *tcpci, struct tcpci_data *data,
+ enum typec_cc_polarity polarity);
+ int (*set_vconn)(struct tcpci *tcpci, struct tcpci_data *data,
+ bool enable);
+ int (*start_drp_toggling)(struct tcpci *tcpci, struct tcpci_data *data,
+ enum typec_cc_status cc);
+};
+
+struct tcpci *tcpci_register_port(struct udevice *dev, struct tcpci_data *data);
+void tcpci_unregister_port(struct tcpci *tcpci);
+int tcpci_main_loop(struct tcpci *tcpci);
+
+#endif /* __LINUX_USB_TCPCI_H */
diff --git a/drivers/usb/typec/tcpm/tcpci_rt1711h.c b/drivers/usb/typec/tcpm/tcpci_rt1711h.c
new file mode 100644
index 0000000..39371e4
--- /dev/null
+++ b/drivers/usb/typec/tcpm/tcpci_rt1711h.c
@@ -0,0 +1,381 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2018, Richtek Technology Corporation
+ *
+ * Richtek RT1711H Type-C Chip Driver
+ */
+
+#include <linux/types.h>
+#include <i2c.h>
+#include <linux/kernel.h>
+#include <linux/usb/tcpm.h>
+#include <linux/delay.h>
+#include <dm/device.h>
+#include <dm/read.h>
+#include <dm/lists.h>
+#include <time.h>
+#include "tcpci.h"
+
+#define RT1711H_VID 0x29CF
+#define RT1711H_PID 0x1711
+#define RT1711H_DID_D 0x2173
+
+#define RT1711H_RTCTRL8 0x9B
+
+/* Autoidle timeout = (tout * 2 + 1) * 6.4ms */
+#define RT1711H_RTCTRL8_SET(ck300, ship_off, en_ext_msg, auto_idle, tout) \
+ (((ck300) << 7) | ((ship_off) << 5) | \
+ ((en_ext_msg) << 4) | ((auto_idle) << 3) | \
+ ((tout) & 0x07))
+
+#define RT1711H_RTCTRL11 0x9E
+
+/* I2C timeout = (tout + 1) * 12.5ms */
+#define RT1711H_RTCTRL11_SET(en, tout) \
+ (((en) << 7) | ((tout) & 0x0F))
+
+#define RT1711H_RTRXDZSEL 0x93
+#define RT1711H_RTCTRL13 0xA0
+#define RT1711H_RTCTRL14 0xA1
+#define RT1711H_RTCTRL15 0xA2
+#define RT1711H_RTCTRL16 0xA3
+#define RT1711H_RTRXDZEN 0xAF
+
+struct rt1711h_chip {
+ struct tcpci_data data;
+ struct tcpci *tcpci;
+ struct udevice *dev;
+ u16 chip_id;
+ u8 deadzone_enable;
+ u8 deadzone_select;
+};
+
+struct tcpci_rt1711h_data {
+ // TODO
+};
+
+static int rt1711h_read16(struct rt1711h_chip *chip, unsigned int reg, u16 *val)
+{
+ return dm_i2c_read(chip->dev, reg, (uint8_t*) val, sizeof(u16));
+}
+
+static int rt1711h_write16(struct rt1711h_chip *chip, unsigned int reg, u16 val)
+{
+ return dm_i2c_write(chip->dev, reg, (uint8_t*) &val, sizeof(u16));
+}
+
+static int rt1711h_read8(struct rt1711h_chip *chip, unsigned int reg, u8 *val)
+{
+ return dm_i2c_read(chip->dev, reg, val, sizeof(u8));
+}
+
+static int rt1711h_write8(struct rt1711h_chip *chip, unsigned int reg, u8 val)
+{
+ return dm_i2c_write(chip->dev, reg, &val, sizeof(u8));
+}
+
+static struct rt1711h_chip *tdata_to_rt1711h(struct tcpci_data *tdata)
+{
+ return container_of(tdata, struct rt1711h_chip, data);
+}
+
+static int rt1711h_init(struct tcpci *tcpci, struct tcpci_data *tdata)
+{
+ int ret;
+ struct rt1711h_chip *chip = tdata_to_rt1711h(tdata);
+
+ /* CK 300K from 320K, shipping off, auto_idle enable, tout = 32ms */
+ ret = rt1711h_write8(chip, RT1711H_RTCTRL8,
+ RT1711H_RTCTRL8_SET(0, 1, 1, 1, 2));
+ if (ret < 0)
+ return ret;
+
+ /* I2C reset : (val + 1) * 12.5ms */
+ ret = rt1711h_write8(chip, RT1711H_RTCTRL11,
+ RT1711H_RTCTRL11_SET(1, 0x0F));
+ if (ret < 0)
+ return ret;
+
+ /* tTCPCfilter : (26.7 * val) us */
+ ret = rt1711h_write8(chip, RT1711H_RTCTRL14, 0x0F);
+ if (ret < 0)
+ return ret;
+
+ /* tDRP : (51.2 + 6.4 * val) ms */
+ ret = rt1711h_write8(chip, RT1711H_RTCTRL15, 0x04);
+ if (ret < 0)
+ return ret;
+
+ /* dcSRC.DRP : 33% */
+ return rt1711h_write16(chip, RT1711H_RTCTRL16, 330);
+}
+
+static enum typec_cc_status rt1711h_reg_to_cc(unsigned int cc, bool sink)
+{
+ switch (cc) {
+ case 1:
+ return sink ? TYPEC_CC_RP_DEF : TYPEC_CC_RD;
+ case 2:
+ return sink ? TYPEC_CC_RP_1_5 : TYPEC_CC_RA;
+ case 3:
+ return sink ? TYPEC_CC_RP_3_0 : TYPEC_CC_OPEN;
+ default:
+ return TYPEC_CC_OPEN;
+ }
+}
+
+static int rt1711h_get_cc(struct tcpci *tcpci, struct tcpci_data *tdata,
+ enum typec_cc_status *cc1, enum typec_cc_status *cc2)
+{
+ struct rt1711h_chip *chip = tdata_to_rt1711h(tdata);
+ u8 reg, cc1_state, cc2_state;
+ bool cc1_sink, cc2_sink, tcpc_presenting_rd;
+ enum typec_cc_status cc;
+ u8 sel;
+ int ret;
+
+ /* Read CC1 & CC2 ROLE */
+ ret = rt1711h_read8(chip, TCPC_ROLE_CTRL, ®);
+ if (ret < 0)
+ return ret;
+
+ cc1_sink = ((reg >> TCPC_ROLE_CTRL_CC1_SHIFT) &
+ TCPC_ROLE_CTRL_CC1_MASK) == TCPC_ROLE_CTRL_CC_RD;
+ cc2_sink = ((reg >> TCPC_ROLE_CTRL_CC2_SHIFT) &
+ TCPC_ROLE_CTRL_CC2_MASK) == TCPC_ROLE_CTRL_CC_RD;
+ /* Read CC STATUS */
+ ret = rt1711h_read8(chip, TCPC_CC_STATUS, ®);
+ if (ret < 0)
+ return ret;
+
+ /* When auto toggling, BIT(4) is set on presenting Rd */
+ tcpc_presenting_rd = !!(reg & TCPC_CC_STATUS_TERM);
+ cc1_sink |= tcpc_presenting_rd;
+ cc2_sink |= tcpc_presenting_rd;
+ cc1_state = (reg >> TCPC_CC_STATUS_CC1_SHIFT) & TCPC_CC_STATUS_CC1_MASK;
+ cc2_state = (reg >> TCPC_CC_STATUS_CC2_SHIFT) & TCPC_CC_STATUS_CC2_MASK;
+
+ *cc1 = rt1711h_reg_to_cc(cc1_state, cc1_sink);
+ *cc2 = rt1711h_reg_to_cc(cc2_state, cc2_sink);
+
+ /* Set RT1711H deadzone */
+ cc = (*cc1 == TYPEC_CC_OPEN) ? *cc2 : *cc1;
+
+ if (cc == TYPEC_CC_RP_DEF) {
+ if (chip->deadzone_enable != 0) {
+ chip->deadzone_enable = 0;
+ rt1711h_write8(chip, RT1711H_RTRXDZEN, 0);
+ }
+ if (chip->deadzone_select != 0x81) {
+ chip->deadzone_select = 0x81;
+ rt1711h_write8(chip, RT1711H_RTRXDZSEL, 0x81);
+ }
+ } else {
+ sel = (chip->chip_id >= RT1711H_DID_D) ? 0x81 : 0x80;
+ if (chip->deadzone_enable != 1) {
+ chip->deadzone_enable = 1;
+ rt1711h_write8(chip, RT1711H_RTRXDZEN, 1);
+ }
+ if (chip->deadzone_select != sel) {
+ chip->deadzone_select = sel;
+ rt1711h_write8(chip, RT1711H_RTRXDZSEL, sel);
+ }
+ }
+
+ return 0;
+}
+
+static int rt1711h_set_polarity(struct tcpci *tcpci, struct tcpci_data *tdata,
+ enum typec_cc_polarity polarity)
+{
+ struct rt1711h_chip *chip = tdata_to_rt1711h(tdata);
+
+ return rt1711h_write8(chip, TCPC_TCPC_CTRL,
+ (polarity == TYPEC_POLARITY_CC2) ?
+ TCPC_TCPC_CTRL_ORIENTATION : 0);
+}
+
+static int rt1711h_set_vconn(struct tcpci *tcpci, struct tcpci_data *tdata,
+ bool enable)
+{
+ struct rt1711h_chip *chip = tdata_to_rt1711h(tdata);
+
+ return rt1711h_write8(chip, RT1711H_RTCTRL8,
+ RT1711H_RTCTRL8_SET(0, 1, 1, !enable, 2));
+}
+
+static int rt1711h_start_drp_toggling(struct tcpci *tcpci,
+ struct tcpci_data *tdata,
+ enum typec_cc_status cc)
+{
+ struct rt1711h_chip *chip = tdata_to_rt1711h(tdata);
+ int ret;
+ unsigned int reg = 0;
+
+ switch (cc) {
+ default:
+ case TYPEC_CC_RP_DEF:
+ reg |= (TCPC_ROLE_CTRL_RP_VAL_DEF <<
+ TCPC_ROLE_CTRL_RP_VAL_SHIFT);
+ break;
+ case TYPEC_CC_RP_1_5:
+ reg |= (TCPC_ROLE_CTRL_RP_VAL_1_5 <<
+ TCPC_ROLE_CTRL_RP_VAL_SHIFT);
+ break;
+ case TYPEC_CC_RP_3_0:
+ reg |= (TCPC_ROLE_CTRL_RP_VAL_3_0 <<
+ TCPC_ROLE_CTRL_RP_VAL_SHIFT);
+ break;
+ }
+
+ if (cc == TYPEC_CC_RD)
+ reg |= (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC1_SHIFT) |
+ (TCPC_ROLE_CTRL_CC_RD << TCPC_ROLE_CTRL_CC2_SHIFT);
+ else
+ reg |= (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC1_SHIFT) |
+ (TCPC_ROLE_CTRL_CC_RP << TCPC_ROLE_CTRL_CC2_SHIFT);
+
+ ret = rt1711h_write8(chip, TCPC_ROLE_CTRL, reg);
+ if (ret < 0)
+ return ret;
+ udelay(500);
+
+ return 0;
+}
+
+// TODO Need to handle CC status by rt1711h????
+/*static irqreturn_t rt1711h_irq(int irq, void *dev_id)*/
+/*{*/
+ /*int ret;*/
+ /*u16 alert;*/
+ /*u8 status;*/
+ /*struct rt1711h_chip *chip = dev_id;*/
+
+ /*if (!chip->tcpci)*/
+ /*return IRQ_HANDLED;*/
+
+ /*ret = rt1711h_read16(chip, TCPC_ALERT, &alert);*/
+ /*if (ret < 0)*/
+ /*goto out;*/
+
+ /*if (alert & TCPC_ALERT_CC_STATUS) {*/
+ /*ret = rt1711h_read8(chip, TCPC_CC_STATUS, &status);*/
+ /*if (ret < 0)*/
+ /*goto out;*/
+ /*[> Clear cc change event triggered by starting toggling <]*/
+ /*if (status & TCPC_CC_STATUS_TOGGLING)*/
+ /*rt1711h_write8(chip, TCPC_ALERT, TCPC_ALERT_CC_STATUS);*/
+ /*}*/
+
+/*out:*/
+ /*return tcpci_irq(chip->tcpci);*/
+/*}*/
+
+static int rt1711h_sw_reset(struct rt1711h_chip *chip)
+{
+ int ret;
+
+ ret = rt1711h_write8(chip, RT1711H_RTCTRL13, 0x01);
+ if (ret < 0)
+ return ret;
+
+ udelay(1000);
+ return 0;
+}
+
+static int rt1711h_check_revision(struct udevice *dev)
+{
+ int ret;
+ uint16_t reg;
+
+ ret = dm_i2c_read(dev, TCPC_VENDOR_ID, (uint8_t*) ®, 2);
+ if (ret)
+ return ret;
+ if (reg != RT1711H_VID) {
+ dev_err(dev, "vid is not correct, 0x%04x\n", reg);
+ return -ENODEV;
+ }
+ ret = dm_i2c_read(dev, TCPC_PRODUCT_ID, (uint8_t*) ®, 2);
+ if (ret)
+ return ret;
+ if (reg != RT1711H_PID) {
+ dev_err(dev, "pid is not correct, 0x%04x\n", reg);
+ return -ENODEV;
+ }
+ return 0;
+}
+
+
+static int tcpci_rt1711h_bind(struct udevice *parent)
+{
+ pr_debug("tcpci_rt1711h_bind\n");
+ return 0;
+}
+
+static int tcpci_rt1711h_probe(struct udevice *dev)
+{
+ int ret;
+ struct rt1711h_chip *chip;
+ u16 chip_id;
+
+ pr_debug("%s\n", __func__);
+
+ ret = rt1711h_check_revision(dev);
+ if (ret < 0) {
+ dev_err(dev, "check vid/pid fail\n");
+ return ret;
+ }
+
+ chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
+ if (!chip)
+ return -ENOMEM;
+
+ chip->data.i2c = dev;
+ chip->dev = dev;
+
+ ret = rt1711h_sw_reset(chip);
+ if (ret < 0)
+ return ret;
+
+ /* Get device id and initialize deadzone */
+ ret = rt1711h_read16(chip, TCPC_BCD_DEV, &chip_id);
+ if (ret < 0)
+ return ret;
+ chip->chip_id = chip_id;
+ ret = rt1711h_read8(chip, RT1711H_RTRXDZEN, &chip->deadzone_enable);
+ if (ret < 0)
+ return ret;
+ ret = rt1711h_read8(chip, RT1711H_RTRXDZSEL, &chip->deadzone_select);
+ if (ret < 0)
+ return ret;
+
+ chip->data.init = rt1711h_init;
+ chip->data.get_cc = rt1711h_get_cc;
+ chip->data.set_polarity = rt1711h_set_polarity;
+ chip->data.set_vconn = rt1711h_set_vconn;
+ chip->data.start_drp_toggling = rt1711h_start_drp_toggling;
+ chip->tcpci = tcpci_register_port(chip->dev, &chip->data);
+ if (IS_ERR_OR_NULL(chip->tcpci))
+ return PTR_ERR(chip->tcpci);
+
+ tcpci_main_loop(chip->tcpci);
+ pr_warn("after main_loop\n");
+
+ return 0;
+}
+
+
+
+static const struct udevice_id tcpci_rt1711h_ids[] = {
+ { .compatible = "richtek,rt1711h" },
+ { }
+};
+
+U_BOOT_DRIVER(tcpci_rt1711h) = {
+ .name = "tcpci-rt1711h",
+ .id = UCLASS_USB_TCPC,
+ .of_match = tcpci_rt1711h_ids,
+ .bind = tcpci_rt1711h_bind,
+ .probe = tcpci_rt1711h_probe,
+ .platdata_auto_alloc_size = sizeof(struct tcpci_rt1711h_data),
+};
diff --git a/drivers/usb/typec/tcpm/tcpm.c b/drivers/usb/typec/tcpm/tcpm.c
new file mode 100644
index 0000000..39dcce9
--- /dev/null
+++ b/drivers/usb/typec/tcpm/tcpm.c
@@ -0,0 +1,3561 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2015-2021 Google, Inc
+ *
+ * USB Power Delivery protocol stack.
+ */
+
+#include <dm/ofnode.h>
+#include <efi.h>
+#include <linux/compat.h>
+#include <linux/kernel.h>
+#include <linux/usb/pd.h>
+#include <linux/usb/pd_ado.h>
+#include <linux/usb/pd_bdo.h>
+#include <linux/usb/pd_ext_sdb.h>
+#include <linux/usb/pd_vdo.h>
+#include <linux/usb/role.h>
+#include <linux/usb/tcpm.h>
+#include <time.h>
+#include <vsprintf.h>
+
+#define FOREACH_STATE(S) \
+ S(INVALID_STATE), \
+ S(TOGGLING), \
+ S(SRC_UNATTACHED), \
+ S(SRC_ATTACH_WAIT), \
+ S(SRC_ATTACHED), \
+ S(SRC_STARTUP), \
+ S(SRC_SEND_CAPABILITIES), \
+ S(SRC_SEND_CAPABILITIES_TIMEOUT), \
+ S(SRC_NEGOTIATE_CAPABILITIES), \
+ S(SRC_TRANSITION_SUPPLY), \
+ S(SRC_READY), \
+ S(SRC_WAIT_NEW_CAPABILITIES), \
+ \
+ S(SNK_UNATTACHED), \
+ S(SNK_ATTACH_WAIT), \
+ S(SNK_DEBOUNCED), \
+ S(SNK_ATTACHED), \
+ S(SNK_STARTUP), \
+ S(SNK_DISCOVERY), \
+ S(SNK_DISCOVERY_DEBOUNCE), \
+ S(SNK_DISCOVERY_DEBOUNCE_DONE), \
+ S(SNK_WAIT_CAPABILITIES), \
+ S(SNK_NEGOTIATE_CAPABILITIES), \
+ S(SNK_NEGOTIATE_PPS_CAPABILITIES), \
+ S(SNK_TRANSITION_SINK), \
+ S(SNK_TRANSITION_SINK_VBUS), \
+ S(SNK_READY), \
+ \
+ S(ACC_UNATTACHED), \
+ S(DEBUG_ACC_ATTACHED), \
+ S(AUDIO_ACC_ATTACHED), \
+ S(AUDIO_ACC_DEBOUNCE), \
+ \
+ S(HARD_RESET_SEND), \
+ S(HARD_RESET_START), \
+ S(SRC_HARD_RESET_VBUS_OFF), \
+ S(SRC_HARD_RESET_VBUS_ON), \
+ S(SNK_HARD_RESET_SINK_OFF), \
+ S(SNK_HARD_RESET_WAIT_VBUS), \
+ S(SNK_HARD_RESET_SINK_ON), \
+ \
+ S(SOFT_RESET), \
+ S(SOFT_RESET_SEND), \
+ \
+ S(DR_SWAP_ACCEPT), \
+ S(DR_SWAP_SEND), \
+ S(DR_SWAP_SEND_TIMEOUT), \
+ S(DR_SWAP_CANCEL), \
+ S(DR_SWAP_CHANGE_DR), \
+ \
+ S(PR_SWAP_ACCEPT), \
+ S(PR_SWAP_SEND), \
+ S(PR_SWAP_SEND_TIMEOUT), \
+ S(PR_SWAP_CANCEL), \
+ S(PR_SWAP_START), \
+ S(PR_SWAP_SRC_SNK_TRANSITION_OFF), \
+ S(PR_SWAP_SRC_SNK_SOURCE_OFF), \
+ S(PR_SWAP_SRC_SNK_SOURCE_OFF_CC_DEBOUNCED), \
+ S(PR_SWAP_SRC_SNK_SINK_ON), \
+ S(PR_SWAP_SNK_SRC_SINK_OFF), \
+ S(PR_SWAP_SNK_SRC_SOURCE_ON), \
+ S(PR_SWAP_SNK_SRC_SOURCE_ON_VBUS_RAMPED_UP), \
+ \
+ S(VCONN_SWAP_ACCEPT), \
+ S(VCONN_SWAP_SEND), \
+ S(VCONN_SWAP_SEND_TIMEOUT), \
+ S(VCONN_SWAP_CANCEL), \
+ S(VCONN_SWAP_START), \
+ S(VCONN_SWAP_WAIT_FOR_VCONN), \
+ S(VCONN_SWAP_TURN_ON_VCONN), \
+ S(VCONN_SWAP_TURN_OFF_VCONN), \
+ \
+ S(SNK_TRY), \
+ S(SNK_TRY_WAIT), \
+ S(SNK_TRY_WAIT_DEBOUNCE), \
+ S(SNK_TRY_WAIT_DEBOUNCE_CHECK_VBUS), \
+ S(SRC_TRYWAIT), \
+ S(SRC_TRYWAIT_DEBOUNCE), \
+ S(SRC_TRYWAIT_UNATTACHED), \
+ \
+ S(SRC_TRY), \
+ S(SRC_TRY_WAIT), \
+ S(SRC_TRY_DEBOUNCE), \
+ S(SNK_TRYWAIT), \
+ S(SNK_TRYWAIT_DEBOUNCE), \
+ S(SNK_TRYWAIT_VBUS), \
+ S(BIST_RX), \
+ \
+ S(GET_STATUS_SEND), \
+ S(GET_STATUS_SEND_TIMEOUT), \
+ S(GET_PPS_STATUS_SEND), \
+ S(GET_PPS_STATUS_SEND_TIMEOUT), \
+ \
+ S(ERROR_RECOVERY), \
+ S(PORT_RESET), \
+ S(PORT_RESET_WAIT_OFF)
+
+#define GENERATE_ENUM(e) e
+#define GENERATE_STRING(s) #s
+
+enum tcpm_state {
+ FOREACH_STATE(GENERATE_ENUM)
+};
+
+static const char * const tcpm_states[] = {
+ FOREACH_STATE(GENERATE_STRING)
+};
+
+enum pd_msg_request {
+ PD_MSG_NONE = 0,
+ PD_MSG_CTRL_REJECT,
+ PD_MSG_CTRL_WAIT,
+ PD_MSG_CTRL_NOT_SUPP,
+ PD_MSG_DATA_SINK_CAP,
+ PD_MSG_DATA_SOURCE_CAP,
+};
+
+/* Events from low level driver */
+
+#define TCPM_CC_EVENT BIT(0)
+#define TCPM_VBUS_EVENT BIT(1)
+#define TCPM_RESET_EVENT BIT(2)
+#define TCPM_RX_EVENT BIT(3)
+
+#define LOG_BUFFER_ENTRIES 1024
+#define LOG_BUFFER_ENTRY_SIZE 128
+
+struct pd_pps_data {
+ u32 min_volt;
+ u32 max_volt;
+ u32 max_curr;
+ u32 out_volt;
+ u32 op_curr;
+ bool supported;
+ bool active;
+};
+
+struct tcpm_port {
+ struct udevice *dev;
+
+ struct typec_capability typec_caps;
+ struct typec_port *typec_port;
+
+ struct tcpc_dev *tcpc;
+ struct usb_role_switch *role_sw;
+
+ enum typec_role vconn_role;
+ enum typec_role pwr_role;
+ enum typec_data_role data_role;
+ enum typec_pwr_opmode pwr_opmode;
+
+ struct usb_pd_identity partner_ident;
+ struct typec_partner_desc partner_desc;
+ struct typec_partner *partner;
+
+ enum typec_cc_status cc_req;
+
+ enum typec_cc_status cc1;
+ enum typec_cc_status cc2;
+ enum typec_cc_polarity polarity;
+
+ bool attached;
+ bool connected;
+ enum typec_port_type port_type;
+ bool vbus_present;
+ bool vbus_never_low;
+ bool vbus_source;
+ bool vbus_charge;
+
+ bool send_discover;
+ bool op_vsafe5v;
+
+ int try_role;
+ int try_snk_count;
+ int try_src_count;
+
+ enum pd_msg_request queued_message;
+
+ enum tcpm_state enter_state;
+ enum tcpm_state prev_state;
+ enum tcpm_state state;
+ enum tcpm_state delayed_state;
+ unsigned long delayed_runtime_ms;
+ unsigned long delay_ms;
+
+ u32 pd_events;
+ struct pd_message rx_message;
+
+ enum tcpm_transmit_status tx_status;
+
+ bool swap_pending;
+ bool non_pd_role_swap;
+ int swap_status;
+
+ unsigned int negotiated_rev;
+ unsigned int message_id;
+ unsigned int caps_count;
+ unsigned int hard_reset_count;
+ bool pd_capable;
+ bool explicit_contract;
+ unsigned int rx_msgid;
+
+ /* Partner capabilities/requests */
+ u32 sink_request;
+ u32 source_caps[PDO_MAX_OBJECTS];
+ unsigned int nr_source_caps;
+ u32 sink_caps[PDO_MAX_OBJECTS];
+ unsigned int nr_sink_caps;
+
+ /* Local capabilities */
+ u32 src_pdo[PDO_MAX_OBJECTS];
+ unsigned int nr_src_pdo;
+ u32 snk_pdo[PDO_MAX_OBJECTS];
+ unsigned int nr_snk_pdo;
+ u32 snk_vdo[VDO_MAX_OBJECTS];
+ unsigned int nr_snk_vdo;
+
+ unsigned int operating_snk_mw;
+ bool update_sink_caps;
+
+ /* Requested current / voltage */
+ u32 current_limit;
+ u32 supply_voltage;
+
+ u32 bist_request;
+
+ /* PPS */
+ struct pd_pps_data pps_data;
+ bool pps_pending;
+ int pps_status;
+
+ /* Deadline in ms to exit src_try_wait state */
+ unsigned long max_wait_ms;
+
+ /* port belongs to a self powered device */
+ bool self_powered;
+};
+
+struct pd_rx_event {
+ struct work_struct work;
+ struct tcpm_port *port;
+ struct pd_message msg;
+};
+
+#define tcpm_cc_is_sink(cc) \
+ ((cc) == TYPEC_CC_RP_DEF || (cc) == TYPEC_CC_RP_1_5 || \
+ (cc) == TYPEC_CC_RP_3_0)
+
+#define tcpm_port_is_sink(port) \
+ ((tcpm_cc_is_sink((port)->cc1) && !tcpm_cc_is_sink((port)->cc2)) || \
+ (tcpm_cc_is_sink((port)->cc2) && !tcpm_cc_is_sink((port)->cc1)))
+
+#define tcpm_cc_is_source(cc) ((cc) == TYPEC_CC_RD)
+#define tcpm_cc_is_audio(cc) ((cc) == TYPEC_CC_RA)
+#define tcpm_cc_is_open(cc) ((cc) == TYPEC_CC_OPEN)
+
+#define tcpm_port_is_source(port) \
+ ((tcpm_cc_is_source((port)->cc1) && \
+ !tcpm_cc_is_source((port)->cc2)) || \
+ (tcpm_cc_is_source((port)->cc2) && \
+ !tcpm_cc_is_source((port)->cc1)))
+
+#define tcpm_port_is_debug(port) \
+ (tcpm_cc_is_source((port)->cc1) && tcpm_cc_is_source((port)->cc2))
+
+#define tcpm_port_is_audio(port) \
+ (tcpm_cc_is_audio((port)->cc1) && tcpm_cc_is_audio((port)->cc2))
+
+#define tcpm_port_is_audio_detached(port) \
+ ((tcpm_cc_is_audio((port)->cc1) && tcpm_cc_is_open((port)->cc2)) || \
+ (tcpm_cc_is_audio((port)->cc2) && tcpm_cc_is_open((port)->cc1)))
+
+#define tcpm_try_snk(port) \
+ ((port)->try_snk_count == 0 && (port)->try_role == TYPEC_SINK && \
+ (port)->port_type == TYPEC_PORT_DRP)
+
+#define tcpm_try_src(port) \
+ ((port)->try_src_count == 0 && (port)->try_role == TYPEC_SOURCE && \
+ (port)->port_type == TYPEC_PORT_DRP)
+
+
+enum {
+ TYPEC_STATE_SAFE,
+ TYPEC_STATE_USB,
+ TYPEC_STATE_MODAL,
+};
+
+
+static enum tcpm_state tcpm_default_state(struct tcpm_port *port)
+{
+ if (port->port_type == TYPEC_PORT_DRP) {
+ if (port->try_role == TYPEC_SINK)
+ return SNK_UNATTACHED;
+ else if (port->try_role == TYPEC_SOURCE)
+ return SRC_UNATTACHED;
+ else if (port->tcpc->config &&
+ port->tcpc->config->default_role == TYPEC_SINK)
+ return SNK_UNATTACHED;
+ /* Fall through to return SRC_UNATTACHED */
+ } else if (port->port_type == TYPEC_PORT_SNK) {
+ return SNK_UNATTACHED;
+ }
+ return SRC_UNATTACHED;
+}
+
+static bool tcpm_port_is_disconnected(struct tcpm_port *port)
+{
+ return (!port->attached && port->cc1 == TYPEC_CC_OPEN &&
+ port->cc2 == TYPEC_CC_OPEN) ||
+ (port->attached && ((port->polarity == TYPEC_POLARITY_CC1 &&
+ port->cc1 == TYPEC_CC_OPEN) ||
+ (port->polarity == TYPEC_POLARITY_CC2 &&
+ port->cc2 == TYPEC_CC_OPEN)));
+}
+
+/*
+ * Logging
+ */
+__printf(2, 0)
+static void _tcpm_log(struct tcpm_port *port, const char *fmt, va_list args)
+{
+ char tmpbuffer[LOG_BUFFER_ENTRY_SIZE];
+ vsnprintf(tmpbuffer, sizeof(tmpbuffer), fmt, args);
+ printf("%s\n", tmpbuffer);
+}
+
+__printf(2, 3)
+static void tcpm_log(struct tcpm_port *port, const char *fmt, ...)
+{
+ va_list args;
+
+ /* Do not log while disconnected and unattached */
+ if (tcpm_port_is_disconnected(port) &&
+ (port->state == SRC_UNATTACHED || port->state == SNK_UNATTACHED ||
+ port->state == TOGGLING))
+ return;
+
+ va_start(args, fmt);
+ _tcpm_log(port, fmt, args);
+ va_end(args);
+}
+
+__printf(2, 3)
+static void tcpm_log_force(struct tcpm_port *port, const char *fmt, ...)
+{
+ va_list args;
+
+ va_start(args, fmt);
+ _tcpm_log(port, fmt, args);
+ va_end(args);
+}
+
+static void tcpm_log_source_caps(struct tcpm_port *port)
+{
+ int i;
+
+ for (i = 0; i < port->nr_source_caps; i++) {
+ u32 pdo = port->source_caps[i];
+ enum pd_pdo_type type = pdo_type(pdo);
+ char msg[64];
+
+ switch (type) {
+ case PDO_TYPE_FIXED:
+ scnprintf(msg, sizeof(msg),
+ "%u mV, %u mA [%s%s%s%s%s%s]",
+ pdo_fixed_voltage(pdo),
+ pdo_max_current(pdo),
+ (pdo & PDO_FIXED_DUAL_ROLE) ?
+ "R" : "",
+ (pdo & PDO_FIXED_SUSPEND) ?
+ "S" : "",
+ (pdo & PDO_FIXED_HIGHER_CAP) ?
+ "H" : "",
+ (pdo & PDO_FIXED_USB_COMM) ?
+ "U" : "",
+ (pdo & PDO_FIXED_DATA_SWAP) ?
+ "D" : "",
+ (pdo & PDO_FIXED_EXTPOWER) ?
+ "E" : "");
+ break;
+ case PDO_TYPE_VAR:
+ scnprintf(msg, sizeof(msg),
+ "%u-%u mV, %u mA",
+ pdo_min_voltage(pdo),
+ pdo_max_voltage(pdo),
+ pdo_max_current(pdo));
+ break;
+ case PDO_TYPE_BATT:
+ scnprintf(msg, sizeof(msg),
+ "%u-%u mV, %u mW",
+ pdo_min_voltage(pdo),
+ pdo_max_voltage(pdo),
+ pdo_max_power(pdo));
+ break;
+ case PDO_TYPE_APDO:
+ if (pdo_apdo_type(pdo) == APDO_TYPE_PPS)
+ scnprintf(msg, sizeof(msg),
+ "%u-%u mV, %u mA",
+ pdo_pps_apdo_min_voltage(pdo),
+ pdo_pps_apdo_max_voltage(pdo),
+ pdo_pps_apdo_max_current(pdo));
+ else
+ strcpy(msg, "undefined APDO");
+ break;
+ default:
+ strcpy(msg, "undefined");
+ break;
+ }
+ tcpm_log(port, " PDO %d: type %d, %s",
+ i, type, msg);
+ }
+}
+
+static enum tcpm_transmit_status wait_for_tx_complete(struct tcpm_port *port,
+ u32 timeout_ms)
+{
+ int ret;
+ enum tcpm_transmit_status status;
+ unsigned long start;
+
+ status = TCPC_TX_WAITING;
+ start = get_timer(0);
+ while (time_before(get_timer(0), start + timeout_ms) &&
+ status == TCPC_TX_WAITING) {
+ pr_debug("%s time: %lu timeout: %lu, status: %d\n", __func__, get_timer(0), start+timeout_ms, status);
+ ret = port->tcpc->get_tx_status(port->tcpc, &status);
+ if (ret) {
+ return TCPC_TX_FAILED;
+ }
+ pr_debug("%s endloop time: %lu timeout: %lu, status: %d\n", __func__, get_timer(0), start+timeout_ms, status);
+ }
+ return status;
+}
+
+static int tcpm_pd_transmit(struct tcpm_port *port,
+ enum tcpm_transmit_type type,
+ const struct pd_message *msg)
+{
+ int ret;
+ enum tcpm_transmit_status status;
+
+ if (msg)
+ tcpm_log(port, "PD TX, header: %#x", le16_to_cpu(msg->header));
+ else
+ tcpm_log(port, "PD TX, type: %#x", type);
+
+ ret = port->tcpc->pd_transmit(port->tcpc, type, msg);
+ if (ret < 0)
+ return ret;
+
+ status = wait_for_tx_complete(port, PD_T_TCPC_TX_TIMEOUT);
+ if (status == TCPC_TX_WAITING)
+ return -ETIMEDOUT;
+
+ port->tx_status = status;
+ switch (port->tx_status) {
+ case TCPC_TX_SUCCESS:
+ port->message_id = (port->message_id + 1) & PD_HEADER_ID_MASK;
+ return 0;
+ case TCPC_TX_DISCARDED:
+ return -EAGAIN;
+ case TCPC_TX_FAILED:
+ default:
+ return -EIO;
+ }
+}
+
+void tcpm_pd_transmit_complete(struct tcpm_port *port,
+ enum tcpm_transmit_status status)
+{
+ tcpm_log(port, "PD TX complete, status: %u", status);
+ port->tx_status = status;
+}
+EXPORT_SYMBOL_GPL(tcpm_pd_transmit_complete);
+
+static int tcpm_mux_set(struct tcpm_port *port, int state,
+ enum usb_role usb_role,
+ enum typec_orientation orientation)
+{
+ int ret;
+
+ tcpm_log(port, "Requesting mux state %d, usb-role %d, orientation %d",
+ state, usb_role, orientation);
+
+ ret = typec_set_orientation(port->typec_port, orientation);
+ if (ret)
+ return ret;
+
+ if (port->role_sw) {
+ ret = usb_role_switch_set_role(port->role_sw, usb_role);
+ if (ret)
+ return ret;
+ }
+
+ return typec_set_mode(port->typec_port, state);
+}
+
+static int tcpm_set_polarity(struct tcpm_port *port,
+ enum typec_cc_polarity polarity)
+{
+ int ret;
+
+ tcpm_log(port, "polarity %d", polarity);
+
+ ret = port->tcpc->set_polarity(port->tcpc, polarity);
+ if (ret < 0)
+ return ret;
+
+ port->polarity = polarity;
+
+ return 0;
+}
+
+static int tcpm_set_vconn(struct tcpm_port *port, bool enable)
+{
+ int ret;
+
+ tcpm_log(port, "vconn:=%d", enable);
+
+ ret = port->tcpc->set_vconn(port->tcpc, enable);
+ if (!ret) {
+ port->vconn_role = enable ? TYPEC_SOURCE : TYPEC_SINK;
+ typec_set_vconn_role(port->typec_port, port->vconn_role);
+ }
+
+ return ret;
+}
+
+static u32 tcpm_get_current_limit(struct tcpm_port *port)
+{
+ enum typec_cc_status cc;
+ u32 limit;
+
+ cc = port->polarity ? port->cc2 : port->cc1;
+ switch (cc) {
+ case TYPEC_CC_RP_1_5:
+ limit = 1500;
+ break;
+ case TYPEC_CC_RP_3_0:
+ limit = 3000;
+ break;
+ case TYPEC_CC_RP_DEF:
+ default:
+ if (port->tcpc->get_current_limit)
+ limit = port->tcpc->get_current_limit(port->tcpc);
+ else
+ limit = 0;
+ break;
+ }
+
+ return limit;
+}
+
+static int tcpm_set_current_limit(struct tcpm_port *port, u32 max_ma, u32 mv)
+{
+ int ret = -EOPNOTSUPP;
+
+ tcpm_log(port, "Setting voltage/current limit %u mV %u mA", mv, max_ma);
+
+ port->supply_voltage = mv;
+ port->current_limit = max_ma;
+
+ if (port->tcpc->set_current_limit)
+ ret = port->tcpc->set_current_limit(port->tcpc, max_ma, mv);
+
+ return ret;
+}
+
+/*
+ * Determine RP value to set based on maximum current supported
+ * by a port if configured as source.
+ * Returns CC value to report to link partner.
+ */
+static enum typec_cc_status tcpm_rp_cc(struct tcpm_port *port)
+{
+ const u32 *src_pdo = port->src_pdo;
+ int nr_pdo = port->nr_src_pdo;
+ int i;
+
+ /*
+ * Search for first entry with matching voltage.
+ * It should report the maximum supported current.
+ */
+ for (i = 0; i < nr_pdo; i++) {
+ const u32 pdo = src_pdo[i];
+
+ if (pdo_type(pdo) == PDO_TYPE_FIXED &&
+ pdo_fixed_voltage(pdo) == 5000) {
+ unsigned int curr = pdo_max_current(pdo);
+
+ if (curr >= 3000)
+ return TYPEC_CC_RP_3_0;
+ else if (curr >= 1500)
+ return TYPEC_CC_RP_1_5;
+ return TYPEC_CC_RP_DEF;
+ }
+ }
+
+ return TYPEC_CC_RP_DEF;
+}
+
+static int tcpm_set_attached_state(struct tcpm_port *port, bool attached)
+{
+ return port->tcpc->set_roles(port->tcpc, attached, port->pwr_role,
+ port->data_role);
+}
+
+extern void amlogic_typec_set_mode(int mode);
+
+static int tcpm_set_roles(struct tcpm_port *port, bool attached,
+ enum typec_role role, enum typec_data_role data)
+{
+ enum typec_orientation orientation;
+ enum usb_role usb_role;
+ int ret;
+
+ if (port->polarity == TYPEC_POLARITY_CC1)
+ orientation = TYPEC_ORIENTATION_NORMAL;
+ else
+ orientation = TYPEC_ORIENTATION_REVERSE;
+
+ if (data == TYPEC_HOST)
+ usb_role = USB_ROLE_HOST;
+ else
+ usb_role = USB_ROLE_DEVICE;
+
+ ret = tcpm_mux_set(port, TYPEC_STATE_USB, usb_role, orientation);
+ if (ret < 0)
+ return ret;
+
+ ret = port->tcpc->set_roles(port->tcpc, attached, role, data);
+ if (ret < 0)
+ return ret;
+
+ port->pwr_role = role;
+ port->data_role = data;
+ pr_info("%s(): pwr_role=%d, data_role=%d\n", __func__, (int)role, (int)data);
+ typec_set_data_role(port->typec_port, data);
+ typec_set_pwr_role(port->typec_port, role);
+
+ return 0;
+}
+
+static int tcpm_set_pwr_role(struct tcpm_port *port, enum typec_role role)
+{
+ int ret;
+
+ ret = port->tcpc->set_roles(port->tcpc, true, role,
+ port->data_role);
+ if (ret < 0)
+ return ret;
+
+ port->pwr_role = role;
+ typec_set_pwr_role(port->typec_port, role);
+
+ return 0;
+}
+
+static int tcpm_pd_send_source_caps(struct tcpm_port *port)
+{
+ struct pd_message msg;
+ int i;
+
+ memset(&msg, 0, sizeof(msg));
+ if (!port->nr_src_pdo) {
+ /* No source capabilities defined, sink only */
+ msg.header = PD_HEADER_LE(PD_CTRL_REJECT,
+ port->pwr_role,
+ port->data_role,
+ port->negotiated_rev,
+ port->message_id, 0);
+ } else {
+ msg.header = PD_HEADER_LE(PD_DATA_SOURCE_CAP,
+ port->pwr_role,
+ port->data_role,
+ port->negotiated_rev,
+ port->message_id,
+ port->nr_src_pdo);
+ }
+ for (i = 0; i < port->nr_src_pdo; i++)
+ msg.payload[i] = cpu_to_le32(port->src_pdo[i]);
+
+ return tcpm_pd_transmit(port, TCPC_TX_SOP, &msg);
+}
+
+static int tcpm_pd_send_sink_caps(struct tcpm_port *port)
+{
+ struct pd_message msg;
+ int i;
+
+ memset(&msg, 0, sizeof(msg));
+ if (!port->nr_snk_pdo) {
+ /* No sink capabilities defined, source only */
+ msg.header = PD_HEADER_LE(PD_CTRL_REJECT,
+ port->pwr_role,
+ port->data_role,
+ port->negotiated_rev,
+ port->message_id, 0);
+ } else {
+ msg.header = PD_HEADER_LE(PD_DATA_SINK_CAP,
+ port->pwr_role,
+ port->data_role,
+ port->negotiated_rev,
+ port->message_id,
+ port->nr_snk_pdo);
+ }
+ for (i = 0; i < port->nr_snk_pdo; i++)
+ msg.payload[i] = cpu_to_le32(port->snk_pdo[i]);
+
+ return tcpm_pd_transmit(port, TCPC_TX_SOP, &msg);
+}
+
+static void tcpm_set_state(struct tcpm_port *port, enum tcpm_state state,
+ unsigned int delay_ms)
+{
+ if (delay_ms) {
+ tcpm_log(port, "pending state change %s -> %s @ %u ms",
+ tcpm_states[port->state], tcpm_states[state],
+ delay_ms);
+ port->delayed_state = state;
+ port->delayed_runtime_ms = get_timer(0) + delay_ms;
+ port->delay_ms = delay_ms;
+ } else {
+ tcpm_log(port, "state change %s -> %s",
+ tcpm_states[port->state], tcpm_states[state]);
+ port->delayed_state = INVALID_STATE;
+ port->prev_state = port->state;
+ port->state = state;
+ }
+}
+
+static void tcpm_set_state_cond(struct tcpm_port *port, enum tcpm_state state,
+ unsigned int delay_ms)
+{
+ pr_warn("%s enter state %d, state %d\n", __func__, port->enter_state, port->state);
+ if (port->enter_state == port->state)
+ tcpm_set_state(port, state, delay_ms);
+ else
+ tcpm_log(port,
+ "skipped %sstate change %s -> %s [%u ms], context state %s",
+ delay_ms ? "delayed " : "",
+ tcpm_states[port->state], tcpm_states[state],
+ delay_ms, tcpm_states[port->enter_state]);
+}
+
+static void tcpm_queue_message(struct tcpm_port *port,
+ enum pd_msg_request message)
+{
+ port->queued_message = message;
+}
+
+enum pdo_err {
+ PDO_NO_ERR,
+ PDO_ERR_NO_VSAFE5V,
+ PDO_ERR_VSAFE5V_NOT_FIRST,
+ PDO_ERR_PDO_TYPE_NOT_IN_ORDER,
+ PDO_ERR_FIXED_NOT_SORTED,
+ PDO_ERR_VARIABLE_BATT_NOT_SORTED,
+ PDO_ERR_DUPE_PDO,
+ PDO_ERR_PPS_APDO_NOT_SORTED,
+ PDO_ERR_DUPE_PPS_APDO,
+};
+
+static const char * const pdo_err_msg[] = {
+ [PDO_ERR_NO_VSAFE5V] =
+ " err: source/sink caps should atleast have vSafe5V",
+ [PDO_ERR_VSAFE5V_NOT_FIRST] =
+ " err: vSafe5V Fixed Supply Object Shall always be the first object",
+ [PDO_ERR_PDO_TYPE_NOT_IN_ORDER] =
+ " err: PDOs should be in the following order: Fixed; Battery; Variable",
+ [PDO_ERR_FIXED_NOT_SORTED] =
+ " err: Fixed supply pdos should be in increasing order of their fixed voltage",
+ [PDO_ERR_VARIABLE_BATT_NOT_SORTED] =
+ " err: Variable/Battery supply pdos should be in increasing order of their minimum voltage",
+ [PDO_ERR_DUPE_PDO] =
+ " err: Variable/Batt supply pdos cannot have same min/max voltage",
+ [PDO_ERR_PPS_APDO_NOT_SORTED] =
+ " err: Programmable power supply apdos should be in increasing order of their maximum voltage",
+ [PDO_ERR_DUPE_PPS_APDO] =
+ " err: Programmable power supply apdos cannot have same min/max voltage and max current",
+};
+
+static enum pdo_err tcpm_caps_err(struct tcpm_port *port, const u32 *pdo,
+ unsigned int nr_pdo)
+{
+ unsigned int i;
+
+ /* Should at least contain vSafe5v */
+ if (nr_pdo < 1)
+ return PDO_ERR_NO_VSAFE5V;
+
+ /* The vSafe5V Fixed Supply Object Shall always be the first object */
+ if (pdo_type(pdo[0]) != PDO_TYPE_FIXED ||
+ pdo_fixed_voltage(pdo[0]) != VSAFE5V)
+ return PDO_ERR_VSAFE5V_NOT_FIRST;
+
+ for (i = 1; i < nr_pdo; i++) {
+ if (pdo_type(pdo[i]) < pdo_type(pdo[i - 1])) {
+ return PDO_ERR_PDO_TYPE_NOT_IN_ORDER;
+ } else if (pdo_type(pdo[i]) == pdo_type(pdo[i - 1])) {
+ enum pd_pdo_type type = pdo_type(pdo[i]);
+
+ switch (type) {
+ /*
+ * The remaining Fixed Supply Objects, if
+ * present, shall be sent in voltage order;
+ * lowest to highest.
+ */
+ case PDO_TYPE_FIXED:
+ if (pdo_fixed_voltage(pdo[i]) <=
+ pdo_fixed_voltage(pdo[i - 1]))
+ return PDO_ERR_FIXED_NOT_SORTED;
+ break;
+ /*
+ * The Battery Supply Objects and Variable
+ * supply, if present shall be sent in Minimum
+ * Voltage order; lowest to highest.
+ */
+ case PDO_TYPE_VAR:
+ case PDO_TYPE_BATT:
+ if (pdo_min_voltage(pdo[i]) <
+ pdo_min_voltage(pdo[i - 1]))
+ return PDO_ERR_VARIABLE_BATT_NOT_SORTED;
+ else if ((pdo_min_voltage(pdo[i]) ==
+ pdo_min_voltage(pdo[i - 1])) &&
+ (pdo_max_voltage(pdo[i]) ==
+ pdo_max_voltage(pdo[i - 1])))
+ return PDO_ERR_DUPE_PDO;
+ break;
+ /*
+ * The Programmable Power Supply APDOs, if present,
+ * shall be sent in Maximum Voltage order;
+ * lowest to highest.
+ */
+ case PDO_TYPE_APDO:
+ if (pdo_apdo_type(pdo[i]) != APDO_TYPE_PPS)
+ break;
+
+ if (pdo_pps_apdo_max_voltage(pdo[i]) <
+ pdo_pps_apdo_max_voltage(pdo[i - 1]))
+ return PDO_ERR_PPS_APDO_NOT_SORTED;
+ else if (pdo_pps_apdo_min_voltage(pdo[i]) ==
+ pdo_pps_apdo_min_voltage(pdo[i - 1]) &&
+ pdo_pps_apdo_max_voltage(pdo[i]) ==
+ pdo_pps_apdo_max_voltage(pdo[i - 1]) &&
+ pdo_pps_apdo_max_current(pdo[i]) ==
+ pdo_pps_apdo_max_current(pdo[i - 1]))
+ return PDO_ERR_DUPE_PPS_APDO;
+ break;
+ default:
+ tcpm_log_force(port, " Unknown pdo type");
+ }
+ }
+ }
+
+ return PDO_NO_ERR;
+}
+
+static int tcpm_validate_caps(struct tcpm_port *port, const u32 *pdo,
+ unsigned int nr_pdo)
+{
+ enum pdo_err err_index = tcpm_caps_err(port, pdo, nr_pdo);
+
+ if (err_index != PDO_NO_ERR) {
+ tcpm_log_force(port, " %s", pdo_err_msg[err_index]);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+/*
+ * PD (data, control) command handling functions
+ */
+static inline enum tcpm_state ready_state(struct tcpm_port *port)
+{
+ if (port->pwr_role == TYPEC_SOURCE)
+ return SRC_READY;
+ else
+ return SNK_READY;
+}
+
+static int tcpm_pd_send_control(struct tcpm_port *port,
+ enum pd_ctrl_msg_type type);
+
+static void tcpm_handle_alert(struct tcpm_port *port, const __le32 *payload,
+ int cnt)
+{
+ u32 p0 = le32_to_cpu(payload[0]);
+ unsigned int type = usb_pd_ado_type(p0);
+
+ if (!type) {
+ tcpm_log(port, "Alert message received with no type");
+ return;
+ }
+
+ /* Just handling non-battery alerts for now */
+ if (!(type & USB_PD_ADO_TYPE_BATT_STATUS_CHANGE)) {
+ switch (port->state) {
+ case SRC_READY:
+ case SNK_READY:
+ tcpm_set_state(port, GET_STATUS_SEND, 0);
+ break;
+ default:
+ tcpm_queue_message(port, PD_MSG_CTRL_WAIT);
+ break;
+ }
+ }
+}
+
+static void tcpm_pd_data_request(struct tcpm_port *port,
+ const struct pd_message *msg)
+{
+ enum pd_data_msg_type type = pd_header_type_le(msg->header);
+ unsigned int cnt = pd_header_cnt_le(msg->header);
+ unsigned int rev = pd_header_rev_le(msg->header);
+ unsigned int i;
+
+ switch (type) {
+ case PD_DATA_SOURCE_CAP:
+ if (port->pwr_role != TYPEC_SINK)
+ break;
+
+ for (i = 0; i < cnt; i++)
+ port->source_caps[i] = le32_to_cpu(msg->payload[i]);
+
+ port->nr_source_caps = cnt;
+
+ tcpm_log_source_caps(port);
+
+ tcpm_validate_caps(port, port->source_caps,
+ port->nr_source_caps);
+
+ /*
+ * Adjust revision in subsequent message headers, as required,
+ * to comply with 6.2.1.1.5 of the USB PD 3.0 spec. We don't
+ * support Rev 1.0 so just do nothing in that scenario.
+ */
+ if (rev == PD_REV10)
+ break;
+
+ if (rev < PD_MAX_REV)
+ port->negotiated_rev = rev;
+
+ /*
+ * This message may be received even if VBUS is not
+ * present. This is quite unexpected; see USB PD
+ * specification, sections 8.3.3.6.3.1 and 8.3.3.6.3.2.
+ * However, at the same time, we must be ready to
+ * receive this message and respond to it 15ms after
+ * receiving PS_RDY during power swap operations, no matter
+ * if VBUS is available or not (USB PD specification,
+ * section 6.5.9.2).
+ * So we need to accept the message either way,
+ * but be prepared to keep waiting for VBUS after it was
+ * handled.
+ */
+ tcpm_set_state(port, SNK_NEGOTIATE_CAPABILITIES, 0);
+ break;
+ case PD_DATA_REQUEST:
+ if (port->pwr_role != TYPEC_SOURCE ||
+ cnt != 1) {
+ tcpm_queue_message(port, PD_MSG_CTRL_REJECT);
+ break;
+ }
+
+ /*
+ * Adjust revision in subsequent message headers, as required,
+ * to comply with 6.2.1.1.5 of the USB PD 3.0 spec. We don't
+ * support Rev 1.0 so just reject in that scenario.
+ */
+ if (rev == PD_REV10) {
+ tcpm_queue_message(port, PD_MSG_CTRL_REJECT);
+ break;
+ }
+
+ if (rev < PD_MAX_REV)
+ port->negotiated_rev = rev;
+
+ port->sink_request = le32_to_cpu(msg->payload[0]);
+ tcpm_set_state(port, SRC_NEGOTIATE_CAPABILITIES, 0);
+ break;
+ case PD_DATA_SINK_CAP:
+ /* We don't do anything with this at the moment... */
+ for (i = 0; i < cnt; i++)
+ port->sink_caps[i] = le32_to_cpu(msg->payload[i]);
+ port->nr_sink_caps = cnt;
+ break;
+ case PD_DATA_VENDOR_DEF:
+ if (rev == PD_REV30) {
+ tcpm_log(port, "Return Not_Supported to PF_DATA_VENDOR_DEF.");
+ tcpm_queue_message(port, PD_MSG_CTRL_NOT_SUPP);
+ } else {
+ tcpm_log(port, "Ignoring unsupported PD_DATA_VENDOR_DEF.");
+ }
+ break;
+ case PD_DATA_BIST:
+ if (port->state == SRC_READY || port->state == SNK_READY) {
+ port->bist_request = le32_to_cpu(msg->payload[0]);
+ tcpm_set_state(port, BIST_RX, 0);
+ }
+ break;
+ case PD_DATA_ALERT:
+ tcpm_handle_alert(port, msg->payload, cnt);
+ break;
+ case PD_DATA_BATT_STATUS:
+ case PD_DATA_GET_COUNTRY_INFO:
+ /* Currently unsupported */
+ tcpm_queue_message(port, PD_MSG_CTRL_NOT_SUPP);
+ break;
+ default:
+ tcpm_log(port, "Unhandled data message type %#x", type);
+ break;
+ }
+}
+
+static void tcpm_pps_complete(struct tcpm_port *port, int result)
+{
+ if (port->pps_pending) {
+ port->pps_status = result;
+ port->pps_pending = false;
+ }
+}
+
+static void tcpm_pd_ctrl_request(struct tcpm_port *port,
+ const struct pd_message *msg)
+{
+ enum pd_ctrl_msg_type type = pd_header_type_le(msg->header);
+ enum tcpm_state next_state;
+
+ switch (type) {
+ case PD_CTRL_GOOD_CRC:
+ case PD_CTRL_PING:
+ break;
+ case PD_CTRL_GET_SOURCE_CAP:
+ switch (port->state) {
+ case SRC_READY:
+ case SNK_READY:
+ tcpm_queue_message(port, PD_MSG_DATA_SOURCE_CAP);
+ break;
+ default:
+ tcpm_queue_message(port, PD_MSG_CTRL_REJECT);
+ break;
+ }
+ break;
+ case PD_CTRL_GET_SINK_CAP:
+ switch (port->state) {
+ case SRC_READY:
+ case SNK_READY:
+ tcpm_queue_message(port, PD_MSG_DATA_SINK_CAP);
+ break;
+ default:
+ tcpm_queue_message(port, PD_MSG_CTRL_REJECT);
+ break;
+ }
+ break;
+ case PD_CTRL_GOTO_MIN:
+ break;
+ case PD_CTRL_PS_RDY:
+ switch (port->state) {
+ case SNK_TRANSITION_SINK:
+ if (port->vbus_present) {
+ tcpm_set_current_limit(port,
+ port->current_limit,
+ port->supply_voltage);
+ port->explicit_contract = true;
+ tcpm_set_state(port, SNK_READY, 0);
+ } else {
+ /*
+ * Seen after power swap. Keep waiting for VBUS
+ * in a transitional state.
+ */
+ tcpm_set_state(port,
+ SNK_TRANSITION_SINK_VBUS, 0);
+ }
+ break;
+ case PR_SWAP_SRC_SNK_SOURCE_OFF_CC_DEBOUNCED:
+ tcpm_set_state(port, PR_SWAP_SRC_SNK_SINK_ON, 0);
+ break;
+ case PR_SWAP_SNK_SRC_SINK_OFF:
+ tcpm_set_state(port, PR_SWAP_SNK_SRC_SOURCE_ON, 0);
+ break;
+ case VCONN_SWAP_WAIT_FOR_VCONN:
+ tcpm_set_state(port, VCONN_SWAP_TURN_OFF_VCONN, 0);
+ break;
+ default:
+ break;
+ }
+ break;
+ case PD_CTRL_REJECT:
+ case PD_CTRL_WAIT:
+ case PD_CTRL_NOT_SUPP:
+ switch (port->state) {
+ case SNK_NEGOTIATE_CAPABILITIES:
+ /* USB PD specification, Figure 8-43 */
+ if (port->explicit_contract)
+ next_state = SNK_READY;
+ else
+ next_state = SNK_WAIT_CAPABILITIES;
+ tcpm_set_state(port, next_state, 0);
+ break;
+ case SNK_NEGOTIATE_PPS_CAPABILITIES:
+ /* Revert data back from any requested PPS updates */
+ port->pps_data.out_volt = port->supply_voltage;
+ port->pps_data.op_curr = port->current_limit;
+ port->pps_status = (type == PD_CTRL_WAIT ?
+ -EAGAIN : -EOPNOTSUPP);
+ tcpm_set_state(port, SNK_READY, 0);
+ break;
+ case DR_SWAP_SEND:
+ port->swap_status = (type == PD_CTRL_WAIT ?
+ -EAGAIN : -EOPNOTSUPP);
+ tcpm_set_state(port, DR_SWAP_CANCEL, 0);
+ break;
+ case PR_SWAP_SEND:
+ port->swap_status = (type == PD_CTRL_WAIT ?
+ -EAGAIN : -EOPNOTSUPP);
+ tcpm_set_state(port, PR_SWAP_CANCEL, 0);
+ break;
+ case VCONN_SWAP_SEND:
+ port->swap_status = (type == PD_CTRL_WAIT ?
+ -EAGAIN : -EOPNOTSUPP);
+ tcpm_set_state(port, VCONN_SWAP_CANCEL, 0);
+ break;
+ default:
+ break;
+ }
+ break;
+ case PD_CTRL_ACCEPT:
+ switch (port->state) {
+ case SNK_NEGOTIATE_CAPABILITIES:
+ port->pps_data.active = false;
+ tcpm_set_state(port, SNK_TRANSITION_SINK, 0);
+ break;
+ case SNK_NEGOTIATE_PPS_CAPABILITIES:
+ port->pps_data.active = true;
+ port->supply_voltage = port->pps_data.out_volt;
+ port->current_limit = port->pps_data.op_curr;
+ tcpm_set_state(port, SNK_TRANSITION_SINK, 0);
+ break;
+ case SOFT_RESET_SEND:
+ port->message_id = 0;
+ port->rx_msgid = -1;
+ if (port->pwr_role == TYPEC_SOURCE)
+ next_state = SRC_SEND_CAPABILITIES;
+ else
+ next_state = SNK_WAIT_CAPABILITIES;
+ tcpm_set_state(port, next_state, 0);
+ break;
+ case DR_SWAP_SEND:
+ tcpm_set_state(port, DR_SWAP_CHANGE_DR, 0);
+ break;
+ case PR_SWAP_SEND:
+ tcpm_set_state(port, PR_SWAP_START, 0);
+ break;
+ case VCONN_SWAP_SEND:
+ tcpm_set_state(port, VCONN_SWAP_START, 0);
+ break;
+ default:
+ break;
+ }
+ break;
+ case PD_CTRL_SOFT_RESET:
+ tcpm_set_state(port, SOFT_RESET, 0);
+ break;
+ case PD_CTRL_DR_SWAP:
+ if (port->port_type != TYPEC_PORT_DRP &&
+ port->typec_caps.data != TYPEC_PORT_DRD) {
+ tcpm_queue_message(port, PD_MSG_CTRL_REJECT);
+ break;
+ }
+
+ /*
+ * XXX
+ * 6.3.9: If an alternate mode is active, a request to swap
+ * alternate modes shall trigger a port reset.
+ */
+ switch (port->state) {
+ case SRC_READY:
+ case SNK_READY:
+ tcpm_set_state(port, DR_SWAP_ACCEPT, 0);
+ break;
+ default:
+ tcpm_queue_message(port, PD_MSG_CTRL_WAIT);
+ break;
+ }
+ break;
+ case PD_CTRL_PR_SWAP:
+ if (port->port_type != TYPEC_PORT_DRP) {
+ tcpm_queue_message(port, PD_MSG_CTRL_REJECT);
+ break;
+ }
+ switch (port->state) {
+ case SRC_READY:
+ case SNK_READY:
+ tcpm_set_state(port, PR_SWAP_ACCEPT, 0);
+ break;
+ default:
+ tcpm_queue_message(port, PD_MSG_CTRL_WAIT);
+ break;
+ }
+ break;
+ case PD_CTRL_VCONN_SWAP:
+ if (port->typec_caps.no_vconn) {
+ tcpm_queue_message(port, PD_MSG_CTRL_REJECT);
+ break;
+ }
+ switch (port->state) {
+ case SRC_READY:
+ case SNK_READY:
+ tcpm_set_state(port, VCONN_SWAP_ACCEPT, 0);
+ break;
+ default:
+ tcpm_queue_message(port, PD_MSG_CTRL_WAIT);
+ break;
+ }
+ break;
+ case PD_CTRL_GET_SOURCE_CAP_EXT:
+ case PD_CTRL_GET_STATUS:
+ case PD_CTRL_FR_SWAP:
+ case PD_CTRL_GET_PPS_STATUS:
+ case PD_CTRL_GET_COUNTRY_CODES:
+ /* Currently not supported */
+ tcpm_queue_message(port, PD_MSG_CTRL_NOT_SUPP);
+ break;
+ default:
+ tcpm_log(port, "Unhandled ctrl message type %#x", type);
+ break;
+ }
+}
+
+static void tcpm_pd_ext_msg_request(struct tcpm_port *port,
+ const struct pd_message *msg)
+{
+ enum pd_ext_msg_type type = pd_header_type_le(msg->header);
+ unsigned int data_size = pd_ext_header_data_size_le(msg->ext_msg.header);
+
+ if (!(msg->ext_msg.header & PD_EXT_HDR_CHUNKED)) {
+ tcpm_log(port, "Unchunked extended messages unsupported");
+ return;
+ }
+
+ if (data_size > PD_EXT_MAX_CHUNK_DATA) {
+ tcpm_log(port, "Chunk handling not yet supported");
+ return;
+ }
+
+ switch (type) {
+ case PD_EXT_STATUS:
+ /*
+ * If PPS related events raised then get PPS status to clear
+ * (see USB PD 3.0 Spec, 6.5.2.4)
+ */
+ if (msg->ext_msg.data[USB_PD_EXT_SDB_EVENT_FLAGS] &
+ USB_PD_EXT_SDB_PPS_EVENTS)
+ tcpm_set_state(port, GET_PPS_STATUS_SEND, 0);
+ else
+ tcpm_set_state(port, ready_state(port), 0);
+ break;
+ case PD_EXT_PPS_STATUS:
+ /*
+ * For now the PPS status message is used to clear events
+ * and nothing more.
+ */
+ tcpm_set_state(port, ready_state(port), 0);
+ break;
+ case PD_EXT_SOURCE_CAP_EXT:
+ case PD_EXT_GET_BATT_CAP:
+ case PD_EXT_GET_BATT_STATUS:
+ case PD_EXT_BATT_CAP:
+ case PD_EXT_GET_MANUFACTURER_INFO:
+ case PD_EXT_MANUFACTURER_INFO:
+ case PD_EXT_SECURITY_REQUEST:
+ case PD_EXT_SECURITY_RESPONSE:
+ case PD_EXT_FW_UPDATE_REQUEST:
+ case PD_EXT_FW_UPDATE_RESPONSE:
+ case PD_EXT_COUNTRY_INFO:
+ case PD_EXT_COUNTRY_CODES:
+ tcpm_queue_message(port, PD_MSG_CTRL_NOT_SUPP);
+ break;
+ default:
+ tcpm_log(port, "Unhandled extended message type %#x", type);
+ break;
+ }
+}
+
+static void tcpm_handle_pd_rx_event(struct tcpm_port *port)
+{
+ const struct pd_message *msg = &port->rx_message;
+ unsigned int cnt = pd_header_cnt_le(msg->header);
+
+ tcpm_log(port, "PD RX, header: %#x [%d]", le16_to_cpu(msg->header),
+ port->attached);
+
+ if (port->attached) {
+ enum pd_ctrl_msg_type type = pd_header_type_le(msg->header);
+ unsigned int msgid = pd_header_msgid_le(msg->header);
+
+ /*
+ * USB PD standard, 6.6.1.2:
+ * "... if MessageID value in a received Message is the
+ * same as the stored value, the receiver shall return a
+ * GoodCRC Message with that MessageID value and drop
+ * the Message (this is a retry of an already received
+ * Message). Note: this shall not apply to the Soft_Reset
+ * Message which always has a MessageID value of zero."
+ */
+ if (msgid == port->rx_msgid && type != PD_CTRL_SOFT_RESET)
+ return;
+ port->rx_msgid = msgid;
+
+ /*
+ * If both ends believe to be DFP/host, we have a data role
+ * mismatch. Swap the port role locally to match the partner.
+ */
+ if (!!(le16_to_cpu(msg->header) & PD_HEADER_DATA_ROLE) ==
+ (port->data_role == TYPEC_HOST)) {
+ enum typec_data_role new_role =
+ (port->data_role == TYPEC_HOST) ?
+ TYPEC_DEVICE : TYPEC_HOST;
+
+ tcpm_log(port,
+ "Data role mismatch, swapping role locally to match.");
+ tcpm_set_roles(port, true, port->pwr_role, new_role);
+ }
+ if (msg->header & PD_HEADER_EXT_HDR)
+ tcpm_pd_ext_msg_request(port, msg);
+ else if (cnt)
+ tcpm_pd_data_request(port, msg);
+ else
+ tcpm_pd_ctrl_request(port, msg);
+ }
+}
+
+void tcpm_pd_receive(struct tcpm_port *port, const struct pd_message *msg)
+{
+ pr_warn("%s header: %d\n", __func__, msg->header);
+ port->pd_events = TCPM_RX_EVENT;
+ memcpy(&port->rx_message, msg, sizeof(*msg));
+}
+EXPORT_SYMBOL_GPL(tcpm_pd_receive);
+
+static int tcpm_pd_send_control(struct tcpm_port *port,
+ enum pd_ctrl_msg_type type)
+{
+ pr_warn("%s sending %d\n", __func__, type);
+ struct pd_message msg;
+
+ memset(&msg, 0, sizeof(msg));
+ msg.header = PD_HEADER_LE(type, port->pwr_role,
+ port->data_role,
+ port->negotiated_rev,
+ port->message_id, 0);
+
+ return tcpm_pd_transmit(port, TCPC_TX_SOP, &msg);
+}
+
+/*
+ * Send queued message without affecting state.
+ * Return true if state machine should go back to sleep,
+ * false otherwise.
+ */
+static bool tcpm_send_queued_message(struct tcpm_port *port)
+{
+ enum pd_msg_request queued_message;
+
+ do {
+ queued_message = port->queued_message;
+ port->queued_message = PD_MSG_NONE;
+
+ switch (queued_message) {
+ case PD_MSG_CTRL_WAIT:
+ tcpm_pd_send_control(port, PD_CTRL_WAIT);
+ break;
+ case PD_MSG_CTRL_REJECT:
+ tcpm_pd_send_control(port, PD_CTRL_REJECT);
+ break;
+ case PD_MSG_CTRL_NOT_SUPP:
+ tcpm_pd_send_control(port, PD_CTRL_NOT_SUPP);
+ break;
+ case PD_MSG_DATA_SINK_CAP:
+ tcpm_pd_send_sink_caps(port);
+ break;
+ case PD_MSG_DATA_SOURCE_CAP:
+ tcpm_pd_send_source_caps(port);
+ break;
+ default:
+ break;
+ }
+ } while (port->queued_message != PD_MSG_NONE);
+
+ if (port->delayed_state != INVALID_STATE) {
+ if (time_before(get_timer(0), port->delayed_runtime_ms)) {
+ return true;
+ }
+ port->delayed_state = INVALID_STATE;
+ }
+ return false;
+}
+
+static int tcpm_pd_check_request(struct tcpm_port *port)
+{
+ u32 pdo, rdo = port->sink_request;
+ unsigned int max, op, pdo_max, index;
+ enum pd_pdo_type type;
+
+ index = rdo_index(rdo);
+ if (!index || index > port->nr_src_pdo)
+ return -EINVAL;
+
+ pdo = port->src_pdo[index - 1];
+ type = pdo_type(pdo);
+ switch (type) {
+ case PDO_TYPE_FIXED:
+ case PDO_TYPE_VAR:
+ max = rdo_max_current(rdo);
+ op = rdo_op_current(rdo);
+ pdo_max = pdo_max_current(pdo);
+
+ if (op > pdo_max)
+ return -EINVAL;
+ if (max > pdo_max && !(rdo & RDO_CAP_MISMATCH))
+ return -EINVAL;
+
+ if (type == PDO_TYPE_FIXED)
+ tcpm_log(port,
+ "Requested %u mV, %u mA for %u / %u mA",
+ pdo_fixed_voltage(pdo), pdo_max, op, max);
+ else
+ tcpm_log(port,
+ "Requested %u -> %u mV, %u mA for %u / %u mA",
+ pdo_min_voltage(pdo), pdo_max_voltage(pdo),
+ pdo_max, op, max);
+ break;
+ case PDO_TYPE_BATT:
+ max = rdo_max_power(rdo);
+ op = rdo_op_power(rdo);
+ pdo_max = pdo_max_power(pdo);
+
+ if (op > pdo_max)
+ return -EINVAL;
+ if (max > pdo_max && !(rdo & RDO_CAP_MISMATCH))
+ return -EINVAL;
+ tcpm_log(port,
+ "Requested %u -> %u mV, %u mW for %u / %u mW",
+ pdo_min_voltage(pdo), pdo_max_voltage(pdo),
+ pdo_max, op, max);
+ break;
+ default:
+ return -EINVAL;
+ }
+
+ port->op_vsafe5v = index == 1;
+
+ return 0;
+}
+
+#define min_power(x, y) min(pdo_max_power(x), pdo_max_power(y))
+#define min_current(x, y) min(pdo_max_current(x), pdo_max_current(y))
+
+static int tcpm_pd_select_pdo(struct tcpm_port *port, int *sink_pdo,
+ int *src_pdo)
+{
+ unsigned int i, j, max_src_mv = 0, min_src_mv = 0, max_mw = 0,
+ max_mv = 0, src_mw = 0, src_ma = 0, max_snk_mv = 0,
+ min_snk_mv = 0;
+ int ret = -EINVAL;
+
+ port->pps_data.supported = false;
+
+ /*
+ * Select the source PDO providing the most power which has a
+ * matchig sink cap.
+ */
+ for (i = 0; i < port->nr_source_caps; i++) {
+ u32 pdo = port->source_caps[i];
+ enum pd_pdo_type type = pdo_type(pdo);
+
+ switch (type) {
+ case PDO_TYPE_FIXED:
+ max_src_mv = pdo_fixed_voltage(pdo);
+ min_src_mv = max_src_mv;
+ break;
+ case PDO_TYPE_BATT:
+ case PDO_TYPE_VAR:
+ max_src_mv = pdo_max_voltage(pdo);
+ min_src_mv = pdo_min_voltage(pdo);
+ break;
+ case PDO_TYPE_APDO:
+ if (pdo_apdo_type(pdo) == APDO_TYPE_PPS) {
+ port->pps_data.supported = true;
+ }
+ continue;
+ default:
+ tcpm_log(port, "Invalid source PDO type, ignoring");
+ continue;
+ }
+
+ switch (type) {
+ case PDO_TYPE_FIXED:
+ case PDO_TYPE_VAR:
+ src_ma = pdo_max_current(pdo);
+ src_mw = src_ma * min_src_mv / 1000;
+ break;
+ case PDO_TYPE_BATT:
+ src_mw = pdo_max_power(pdo);
+ break;
+ case PDO_TYPE_APDO:
+ continue;
+ default:
+ tcpm_log(port, "Invalid source PDO type, ignoring");
+ continue;
+ }
+
+ for (j = 0; j < port->nr_snk_pdo; j++) {
+ pdo = port->snk_pdo[j];
+
+ switch (pdo_type(pdo)) {
+ case PDO_TYPE_FIXED:
+ max_snk_mv = pdo_fixed_voltage(pdo);
+ min_snk_mv = max_snk_mv;
+ break;
+ case PDO_TYPE_BATT:
+ case PDO_TYPE_VAR:
+ max_snk_mv = pdo_max_voltage(pdo);
+ min_snk_mv = pdo_min_voltage(pdo);
+ break;
+ case PDO_TYPE_APDO:
+ continue;
+ default:
+ tcpm_log(port, "Invalid sink PDO type, ignoring");
+ continue;
+ }
+
+ if (max_src_mv <= max_snk_mv &&
+ min_src_mv >= min_snk_mv) {
+ /* Prefer higher voltages if available */
+ if ((src_mw == max_mw && min_src_mv > max_mv) ||
+ src_mw > max_mw) {
+ *src_pdo = i;
+ *sink_pdo = j;
+ max_mw = src_mw;
+ max_mv = min_src_mv;
+ ret = 0;
+ }
+ }
+ }
+ }
+
+ return ret;
+}
+
+#define min_pps_apdo_current(x, y) \
+ min(pdo_pps_apdo_max_current(x), pdo_pps_apdo_max_current(y))
+
+static unsigned int tcpm_pd_select_pps_apdo(struct tcpm_port *port)
+{
+ unsigned int i, j, max_mw = 0, max_mv = 0;
+ unsigned int min_src_mv, max_src_mv, src_ma, src_mw;
+ unsigned int min_snk_mv, max_snk_mv;
+ unsigned int max_op_mv;
+ u32 pdo, src, snk;
+ unsigned int src_pdo = 0, snk_pdo = 0;
+
+ /*
+ * Select the source PPS APDO providing the most power while staying
+ * within the board's limits. We skip the first PDO as this is always
+ * 5V 3A.
+ */
+ for (i = 1; i < port->nr_source_caps; ++i) {
+ pdo = port->source_caps[i];
+
+ switch (pdo_type(pdo)) {
+ case PDO_TYPE_APDO:
+ if (pdo_apdo_type(pdo) != APDO_TYPE_PPS) {
+ tcpm_log(port, "Not PPS APDO (source), ignoring");
+ continue;
+ }
+
+ min_src_mv = pdo_pps_apdo_min_voltage(pdo);
+ max_src_mv = pdo_pps_apdo_max_voltage(pdo);
+ src_ma = pdo_pps_apdo_max_current(pdo);
+ src_mw = (src_ma * max_src_mv) / 1000;
+
+ /*
+ * Now search through the sink PDOs to find a matching
+ * PPS APDO. Again skip the first sink PDO as this will
+ * always be 5V 3A.
+ */
+ for (j = 1; j < port->nr_snk_pdo; j++) {
+ pdo = port->snk_pdo[j];
+
+ switch (pdo_type(pdo)) {
+ case PDO_TYPE_APDO:
+ if (pdo_apdo_type(pdo) != APDO_TYPE_PPS) {
+ tcpm_log(port,
+ "Not PPS APDO (sink), ignoring");
+ continue;
+ }
+
+ min_snk_mv =
+ pdo_pps_apdo_min_voltage(pdo);
+ max_snk_mv =
+ pdo_pps_apdo_max_voltage(pdo);
+ break;
+ default:
+ tcpm_log(port,
+ "Not APDO type (sink), ignoring");
+ continue;
+ }
+
+ if (min_src_mv <= max_snk_mv &&
+ max_src_mv >= min_snk_mv) {
+ max_op_mv = min(max_src_mv, max_snk_mv);
+ src_mw = (max_op_mv * src_ma) / 1000;
+ /* Prefer higher voltages if available */
+ if ((src_mw == max_mw &&
+ max_op_mv > max_mv) ||
+ src_mw > max_mw) {
+ src_pdo = i;
+ snk_pdo = j;
+ max_mw = src_mw;
+ max_mv = max_op_mv;
+ }
+ }
+ }
+
+ break;
+ default:
+ tcpm_log(port, "Not APDO type (source), ignoring");
+ continue;
+ }
+ }
+
+ if (src_pdo) {
+ src = port->source_caps[src_pdo];
+ snk = port->snk_pdo[snk_pdo];
+
+ port->pps_data.min_volt = max(pdo_pps_apdo_min_voltage(src),
+ pdo_pps_apdo_min_voltage(snk));
+ port->pps_data.max_volt = min(pdo_pps_apdo_max_voltage(src),
+ pdo_pps_apdo_max_voltage(snk));
+ port->pps_data.max_curr = min_pps_apdo_current(src, snk);
+ port->pps_data.out_volt = min(port->pps_data.max_volt,
+ max(port->pps_data.min_volt,
+ port->pps_data.out_volt));
+ port->pps_data.op_curr = min(port->pps_data.max_curr,
+ port->pps_data.op_curr);
+ }
+
+ return src_pdo;
+}
+
+static int tcpm_pd_build_request(struct tcpm_port *port, u32 *rdo)
+{
+ unsigned int mv, ma, mw, flags;
+ unsigned int max_ma, max_mw;
+ enum pd_pdo_type type;
+ u32 pdo, matching_snk_pdo;
+ int src_pdo_index = 0;
+ int snk_pdo_index = 0;
+ int ret;
+
+ ret = tcpm_pd_select_pdo(port, &snk_pdo_index, &src_pdo_index);
+ if (ret < 0)
+ return ret;
+
+ pdo = port->source_caps[src_pdo_index];
+ matching_snk_pdo = port->snk_pdo[snk_pdo_index];
+ type = pdo_type(pdo);
+
+ switch (type) {
+ case PDO_TYPE_FIXED:
+ mv = pdo_fixed_voltage(pdo);
+ break;
+ case PDO_TYPE_BATT:
+ case PDO_TYPE_VAR:
+ mv = pdo_min_voltage(pdo);
+ break;
+ default:
+ tcpm_log(port, "Invalid PDO selected!");
+ return -EINVAL;
+ }
+
+ /* Select maximum available current within the sink pdo's limit */
+ if (type == PDO_TYPE_BATT) {
+ mw = min_power(pdo, matching_snk_pdo);
+ ma = 1000 * mw / mv;
+ } else {
+ ma = min_current(pdo, matching_snk_pdo);
+ mw = ma * mv / 1000;
+ }
+
+ flags = RDO_USB_COMM | RDO_NO_SUSPEND;
+
+ /* Set mismatch bit if offered power is less than operating power */
+ max_ma = ma;
+ max_mw = mw;
+ if (mw < port->operating_snk_mw) {
+ flags |= RDO_CAP_MISMATCH;
+ if (type == PDO_TYPE_BATT &&
+ (pdo_max_power(matching_snk_pdo) > pdo_max_power(pdo)))
+ max_mw = pdo_max_power(matching_snk_pdo);
+ else if (pdo_max_current(matching_snk_pdo) >
+ pdo_max_current(pdo))
+ max_ma = pdo_max_current(matching_snk_pdo);
+ }
+
+ tcpm_log(port, "cc=%d cc1=%d cc2=%d vbus=%d vconn=%s polarity=%d",
+ port->cc_req, port->cc1, port->cc2, port->vbus_source,
+ port->vconn_role == TYPEC_SOURCE ? "source" : "sink",
+ port->polarity);
+
+ if (type == PDO_TYPE_BATT) {
+ *rdo = RDO_BATT(src_pdo_index + 1, mw, max_mw, flags);
+
+ tcpm_log(port, "Requesting PDO %d: %u mV, %u mW%s",
+ src_pdo_index, mv, mw,
+ flags & RDO_CAP_MISMATCH ? " [mismatch]" : "");
+ } else {
+ *rdo = RDO_FIXED(src_pdo_index + 1, ma, max_ma, flags);
+
+ tcpm_log(port, "Requesting PDO %d: %u mV, %u mA%s",
+ src_pdo_index, mv, ma,
+ flags & RDO_CAP_MISMATCH ? " [mismatch]" : "");
+ }
+
+ port->current_limit = ma;
+ port->supply_voltage = mv;
+
+ return 0;
+}
+
+static int tcpm_pd_send_request(struct tcpm_port *port)
+{
+ struct pd_message msg;
+ int ret;
+ u32 rdo;
+
+ ret = tcpm_pd_build_request(port, &rdo);
+ if (ret < 0)
+ return ret;
+
+ memset(&msg, 0, sizeof(msg));
+ msg.header = PD_HEADER_LE(PD_DATA_REQUEST,
+ port->pwr_role,
+ port->data_role,
+ port->negotiated_rev,
+ port->message_id, 1);
+ msg.payload[0] = cpu_to_le32(rdo);
+
+ return tcpm_pd_transmit(port, TCPC_TX_SOP, &msg);
+}
+
+static int tcpm_pd_build_pps_request(struct tcpm_port *port, u32 *rdo)
+{
+ unsigned int out_mv, op_ma, op_mw, max_mv, max_ma, flags;
+ enum pd_pdo_type type;
+ unsigned int src_pdo_index;
+ u32 pdo;
+
+ src_pdo_index = tcpm_pd_select_pps_apdo(port);
+ if (!src_pdo_index)
+ return -EOPNOTSUPP;
+
+ pdo = port->source_caps[src_pdo_index];
+ type = pdo_type(pdo);
+
+ switch (type) {
+ case PDO_TYPE_APDO:
+ if (pdo_apdo_type(pdo) != APDO_TYPE_PPS) {
+ tcpm_log(port, "Invalid APDO selected!");
+ return -EINVAL;
+ }
+ max_mv = port->pps_data.max_volt;
+ max_ma = port->pps_data.max_curr;
+ out_mv = port->pps_data.out_volt;
+ op_ma = port->pps_data.op_curr;
+ break;
+ default:
+ tcpm_log(port, "Invalid PDO selected!");
+ return -EINVAL;
+ }
+
+ flags = RDO_USB_COMM | RDO_NO_SUSPEND;
+
+ op_mw = (op_ma * out_mv) / 1000;
+ if (op_mw < port->operating_snk_mw) {
+ /*
+ * Try raising current to meet power needs. If that's not enough
+ * then try upping the voltage. If that's still not enough
+ * then we've obviously chosen a PPS APDO which really isn't
+ * suitable so abandon ship.
+ */
+ op_ma = (port->operating_snk_mw * 1000) / out_mv;
+ if ((port->operating_snk_mw * 1000) % out_mv)
+ ++op_ma;
+ op_ma += RDO_PROG_CURR_MA_STEP - (op_ma % RDO_PROG_CURR_MA_STEP);
+
+ if (op_ma > max_ma) {
+ op_ma = max_ma;
+ out_mv = (port->operating_snk_mw * 1000) / op_ma;
+ if ((port->operating_snk_mw * 1000) % op_ma)
+ ++out_mv;
+ out_mv += RDO_PROG_VOLT_MV_STEP -
+ (out_mv % RDO_PROG_VOLT_MV_STEP);
+
+ if (out_mv > max_mv) {
+ tcpm_log(port, "Invalid PPS APDO selected!");
+ return -EINVAL;
+ }
+ }
+ }
+
+ tcpm_log(port, "cc=%d cc1=%d cc2=%d vbus=%d vconn=%s polarity=%d",
+ port->cc_req, port->cc1, port->cc2, port->vbus_source,
+ port->vconn_role == TYPEC_SOURCE ? "source" : "sink",
+ port->polarity);
+
+ *rdo = RDO_PROG(src_pdo_index + 1, out_mv, op_ma, flags);
+
+ tcpm_log(port, "Requesting APDO %d: %u mV, %u mA",
+ src_pdo_index, out_mv, op_ma);
+
+ port->pps_data.op_curr = op_ma;
+ port->pps_data.out_volt = out_mv;
+
+ return 0;
+}
+
+static int tcpm_pd_send_pps_request(struct tcpm_port *port)
+{
+ struct pd_message msg;
+ int ret;
+ u32 rdo;
+
+ ret = tcpm_pd_build_pps_request(port, &rdo);
+ if (ret < 0)
+ return ret;
+
+ memset(&msg, 0, sizeof(msg));
+ msg.header = PD_HEADER_LE(PD_DATA_REQUEST,
+ port->pwr_role,
+ port->data_role,
+ port->negotiated_rev,
+ port->message_id, 1);
+ msg.payload[0] = cpu_to_le32(rdo);
+
+ return tcpm_pd_transmit(port, TCPC_TX_SOP, &msg);
+}
+
+static int tcpm_set_vbus(struct tcpm_port *port, bool enable)
+{
+ int ret;
+
+ if (enable && port->vbus_charge)
+ return -EINVAL;
+
+ tcpm_log(port, "vbus:=%d charge=%d", enable, port->vbus_charge);
+
+ ret = port->tcpc->set_vbus(port->tcpc, enable, port->vbus_charge);
+ if (ret < 0)
+ return ret;
+
+ port->vbus_source = enable;
+ return 0;
+}
+
+static int tcpm_set_charge(struct tcpm_port *port, bool charge)
+{
+ int ret;
+
+ if (charge && port->vbus_source)
+ return -EINVAL;
+
+ if (charge != port->vbus_charge) {
+ tcpm_log(port, "vbus=%d charge:=%d", port->vbus_source, charge);
+ ret = port->tcpc->set_vbus(port->tcpc, port->vbus_source,
+ charge);
+ if (ret < 0)
+ return ret;
+ }
+ port->vbus_charge = charge;
+ return 0;
+}
+
+static bool tcpm_start_toggling(struct tcpm_port *port, enum typec_cc_status cc)
+{
+ int ret;
+
+ if (!port->tcpc->start_toggling)
+ return false;
+
+ tcpm_log_force(port, "Start toggling");
+ ret = port->tcpc->start_toggling(port->tcpc, port->port_type, cc);
+ return ret == 0;
+}
+
+static void tcpm_set_cc(struct tcpm_port *port, enum typec_cc_status cc)
+{
+ tcpm_log(port, "cc:=%d", cc);
+ port->cc_req = cc;
+ port->tcpc->set_cc(port->tcpc, cc);
+}
+
+static int tcpm_init_vbus(struct tcpm_port *port)
+{
+ int ret;
+
+ ret = port->tcpc->set_vbus(port->tcpc, false, false);
+ port->vbus_source = false;
+ port->vbus_charge = false;
+ return ret;
+}
+
+static int tcpm_init_vconn(struct tcpm_port *port)
+{
+ int ret;
+
+ ret = port->tcpc->set_vconn(port->tcpc, false);
+ port->vconn_role = TYPEC_SINK;
+ return ret;
+}
+
+static void tcpm_typec_connect(struct tcpm_port *port)
+{
+ if (!port->connected) {
+ /* Make sure we don't report stale identity information */
+ memset(&port->partner_ident, 0, sizeof(port->partner_ident));
+ port->partner_desc.usb_pd = port->pd_capable;
+ if (tcpm_port_is_debug(port))
+ port->partner_desc.accessory = TYPEC_ACCESSORY_DEBUG;
+ else if (tcpm_port_is_audio(port))
+ port->partner_desc.accessory = TYPEC_ACCESSORY_AUDIO;
+ else
+ port->partner_desc.accessory = TYPEC_ACCESSORY_NONE;
+ port->partner = typec_register_partner(port->typec_port,
+ &port->partner_desc);
+ port->connected = true;
+ }
+}
+
+static int tcpm_src_attach(struct tcpm_port *port)
+{
+ enum typec_cc_polarity polarity =
+ port->cc2 == TYPEC_CC_RD ? TYPEC_POLARITY_CC2
+ : TYPEC_POLARITY_CC1;
+ int ret;
+
+ if (port->attached)
+ return 0;
+
+ ret = tcpm_set_polarity(port, polarity);
+ if (ret < 0)
+ return ret;
+
+ ret = tcpm_set_roles(port, true, TYPEC_SOURCE, TYPEC_HOST);
+ if (ret < 0)
+ return ret;
+
+ ret = port->tcpc->set_pd_rx(port->tcpc, true);
+ if (ret < 0)
+ goto out_disable_mux;
+
+ /*
+ * USB Type-C specification, version 1.2,
+ * chapter 4.5.2.2.8.1 (Attached.SRC Requirements)
+ * Enable VCONN only if the non-RD port is set to RA.
+ */
+ if ((polarity == TYPEC_POLARITY_CC1 && port->cc2 == TYPEC_CC_RA) ||
+ (polarity == TYPEC_POLARITY_CC2 && port->cc1 == TYPEC_CC_RA)) {
+ ret = tcpm_set_vconn(port, true);
+ if (ret < 0)
+ goto out_disable_pd;
+ }
+
+ ret = tcpm_set_vbus(port, true);
+ if (ret < 0)
+ goto out_disable_vconn;
+
+ port->pd_capable = false;
+
+ port->partner = NULL;
+
+ port->attached = true;
+ port->send_discover = true;
+
+ return 0;
+
+out_disable_vconn:
+ tcpm_set_vconn(port, false);
+out_disable_pd:
+ port->tcpc->set_pd_rx(port->tcpc, false);
+out_disable_mux:
+ tcpm_mux_set(port, TYPEC_STATE_SAFE, USB_ROLE_NONE,
+ TYPEC_ORIENTATION_NONE);
+ return ret;
+}
+
+static void tcpm_typec_disconnect(struct tcpm_port *port)
+{
+ if (port->connected) {
+ typec_unregister_partner(port->partner);
+ port->partner = NULL;
+ port->connected = false;
+ }
+}
+
+static void tcpm_reset_port(struct tcpm_port *port)
+{
+ tcpm_typec_disconnect(port);
+ port->attached = false;
+ port->pd_capable = false;
+ port->pps_data.supported = false;
+
+ /*
+ * First Rx ID should be 0; set this to a sentinel of -1 so that
+ * we can check tcpm_pd_rx_handler() if we had seen it before.
+ */
+ port->rx_msgid = -1;
+
+ port->tcpc->set_pd_rx(port->tcpc, false);
+ tcpm_init_vbus(port); /* also disables charging */
+ tcpm_init_vconn(port);
+ tcpm_set_current_limit(port, 0, 0);
+ tcpm_set_polarity(port, TYPEC_POLARITY_CC1);
+ tcpm_mux_set(port, TYPEC_STATE_SAFE, USB_ROLE_NONE,
+ TYPEC_ORIENTATION_NONE);
+ tcpm_set_attached_state(port, false);
+ port->try_src_count = 0;
+ port->try_snk_count = 0;
+}
+
+static void tcpm_detach(struct tcpm_port *port)
+{
+ if (!port->attached)
+ return;
+
+ if (tcpm_port_is_disconnected(port))
+ port->hard_reset_count = 0;
+
+ tcpm_reset_port(port);
+}
+
+static void tcpm_src_detach(struct tcpm_port *port)
+{
+ tcpm_detach(port);
+}
+
+static int tcpm_snk_attach(struct tcpm_port *port)
+{
+ int ret;
+
+ if (port->attached)
+ return 0;
+
+ ret = tcpm_set_polarity(port, port->cc2 != TYPEC_CC_OPEN ?
+ TYPEC_POLARITY_CC2 : TYPEC_POLARITY_CC1);
+ if (ret < 0)
+ return ret;
+
+ ret = tcpm_set_roles(port, true, TYPEC_SINK, TYPEC_DEVICE);
+ if (ret < 0)
+ return ret;
+
+ port->pd_capable = false;
+
+ port->partner = NULL;
+
+ port->attached = true;
+ port->send_discover = true;
+
+ return 0;
+}
+
+static void tcpm_snk_detach(struct tcpm_port *port)
+{
+ tcpm_detach(port);
+}
+
+static int tcpm_acc_attach(struct tcpm_port *port)
+{
+ int ret;
+
+ if (port->attached)
+ return 0;
+
+ ret = tcpm_set_roles(port, true, TYPEC_SOURCE, TYPEC_HOST);
+ if (ret < 0)
+ return ret;
+
+ port->partner = NULL;
+
+ tcpm_typec_connect(port);
+
+ port->attached = true;
+
+ return 0;
+}
+
+static void tcpm_acc_detach(struct tcpm_port *port)
+{
+ tcpm_detach(port);
+}
+
+static inline enum tcpm_state hard_reset_state(struct tcpm_port *port)
+{
+ if (port->hard_reset_count < PD_N_HARD_RESET_COUNT)
+ return HARD_RESET_SEND;
+ if (port->pd_capable)
+ return ERROR_RECOVERY;
+ if (port->pwr_role == TYPEC_SOURCE)
+ return SRC_UNATTACHED;
+ if (port->state == SNK_WAIT_CAPABILITIES)
+ return SNK_READY;
+ return SNK_UNATTACHED;
+}
+
+static inline enum tcpm_state unattached_state(struct tcpm_port *port)
+{
+ if (port->port_type == TYPEC_PORT_DRP) {
+ if (port->pwr_role == TYPEC_SOURCE)
+ return SRC_UNATTACHED;
+ else
+ return SNK_UNATTACHED;
+ } else if (port->port_type == TYPEC_PORT_SRC) {
+ return SRC_UNATTACHED;
+ }
+
+ return SNK_UNATTACHED;
+}
+
+static void tcpm_swap_complete(struct tcpm_port *port, int result)
+{
+ if (port->swap_pending) {
+ port->swap_status = result;
+ port->swap_pending = false;
+ port->non_pd_role_swap = false;
+ }
+}
+
+static enum typec_pwr_opmode tcpm_get_pwr_opmode(enum typec_cc_status cc)
+{
+ switch (cc) {
+ case TYPEC_CC_RP_1_5:
+ return TYPEC_PWR_MODE_1_5A;
+ case TYPEC_CC_RP_3_0:
+ return TYPEC_PWR_MODE_3_0A;
+ case TYPEC_CC_RP_DEF:
+ default:
+ return TYPEC_PWR_MODE_USB;
+ }
+}
+
+static void run_state_machine(struct tcpm_port *port)
+{
+ int ret;
+ enum typec_pwr_opmode opmode;
+ unsigned int msecs;
+
+ if (port->delayed_state != INVALID_STATE &&
+ time_before(get_timer(0), port->delayed_runtime_ms)) {
+ return;
+ }
+ pr_warn("%s to state %d\n", __func__, port->state);
+
+ port->enter_state = port->state;
+ switch (port->state) {
+ case TOGGLING:
+ break;
+ /* SRC states */
+ case SRC_UNATTACHED:
+ if (!port->non_pd_role_swap)
+ tcpm_swap_complete(port, -ENOTCONN);
+ tcpm_src_detach(port);
+ if (tcpm_start_toggling(port, tcpm_rp_cc(port))) {
+ tcpm_set_state(port, TOGGLING, 0);
+ break;
+ }
+ tcpm_set_cc(port, tcpm_rp_cc(port));
+ if (port->port_type == TYPEC_PORT_DRP)
+ tcpm_set_state(port, SNK_UNATTACHED, PD_T_DRP_SNK);
+ break;
+ case SRC_ATTACH_WAIT:
+ if (tcpm_port_is_debug(port))
+ tcpm_set_state(port, DEBUG_ACC_ATTACHED,
+ PD_T_CC_DEBOUNCE);
+ else if (tcpm_port_is_audio(port))
+ tcpm_set_state(port, AUDIO_ACC_ATTACHED,
+ PD_T_CC_DEBOUNCE);
+ else if (tcpm_port_is_source(port))
+ tcpm_set_state(port,
+ tcpm_try_snk(port) ? SNK_TRY
+ : SRC_ATTACHED,
+ PD_T_CC_DEBOUNCE);
+ break;
+
+ case SNK_TRY:
+ port->try_snk_count++;
+ /*
+ * Requirements:
+ * - Do not drive vconn or vbus
+ * - Terminate CC pins (both) to Rd
+ * Action:
+ * - Wait for tDRPTry (PD_T_DRP_TRY).
+ * Until then, ignore any state changes.
+ */
+ tcpm_set_cc(port, TYPEC_CC_RD);
+ tcpm_set_state(port, SNK_TRY_WAIT, PD_T_DRP_TRY);
+ break;
+ case SNK_TRY_WAIT:
+ if (tcpm_port_is_sink(port)) {
+ tcpm_set_state(port, SNK_TRY_WAIT_DEBOUNCE, 0);
+ } else {
+ tcpm_set_state(port, SRC_TRYWAIT, 0);
+ port->max_wait_ms = 0;
+ }
+ break;
+ case SNK_TRY_WAIT_DEBOUNCE:
+ tcpm_set_state(port, SNK_TRY_WAIT_DEBOUNCE_CHECK_VBUS,
+ PD_T_PD_DEBOUNCE);
+ break;
+ case SNK_TRY_WAIT_DEBOUNCE_CHECK_VBUS:
+ if (port->vbus_present && tcpm_port_is_sink(port)) {
+ tcpm_set_state(port, SNK_ATTACHED, 0);
+ } else {
+ tcpm_set_state(port, SRC_TRYWAIT, 0);
+ port->max_wait_ms = 0;
+ }
+ break;
+ case SRC_TRYWAIT:
+ tcpm_set_cc(port, tcpm_rp_cc(port));
+ if (port->max_wait_ms == 0) {
+ port->max_wait_ms = get_timer(0) + PD_T_DRP_TRY;
+ tcpm_set_state(port, SRC_TRYWAIT_UNATTACHED,
+ PD_T_DRP_TRY);
+ } else {
+ if (time_before(get_timer(0), port->max_wait_ms))
+ tcpm_set_state(port, SRC_TRYWAIT_UNATTACHED,
+ port->max_wait_ms - get_timer(0));
+ else
+ tcpm_set_state(port, SNK_UNATTACHED, 0);
+ }
+ break;
+ case SRC_TRYWAIT_DEBOUNCE:
+ tcpm_set_state(port, SRC_ATTACHED, PD_T_CC_DEBOUNCE);
+ break;
+ case SRC_TRYWAIT_UNATTACHED:
+ tcpm_set_state(port, SNK_UNATTACHED, 0);
+ break;
+
+ case SRC_ATTACHED:
+ ret = tcpm_src_attach(port);
+ tcpm_set_state(port, SRC_UNATTACHED,
+ ret < 0 ? 0 : PD_T_PS_SOURCE_ON);
+ break;
+ case SRC_STARTUP:
+ opmode = tcpm_get_pwr_opmode(tcpm_rp_cc(port));
+ typec_set_pwr_opmode(port->typec_port, opmode);
+ port->pwr_opmode = TYPEC_PWR_MODE_USB;
+ port->caps_count = 0;
+ port->negotiated_rev = PD_MAX_REV;
+ port->message_id = 0;
+ port->rx_msgid = -1;
+ port->explicit_contract = false;
+ tcpm_set_state(port, SRC_SEND_CAPABILITIES, 0);
+ break;
+ case SRC_SEND_CAPABILITIES:
+ port->caps_count++;
+ if (port->caps_count > PD_N_CAPS_COUNT) {
+ tcpm_set_state(port, SRC_READY, 0);
+ break;
+ }
+ ret = tcpm_pd_send_source_caps(port);
+ if (ret < 0) {
+ tcpm_set_state(port, SRC_SEND_CAPABILITIES,
+ PD_T_SEND_SOURCE_CAP);
+ } else {
+ /*
+ * Per standard, we should clear the reset counter here.
+ * However, that can result in state machine hang-ups.
+ * Reset it only in READY state to improve stability.
+ */
+ /* port->hard_reset_count = 0; */
+ port->caps_count = 0;
+ port->pd_capable = true;
+ tcpm_set_state_cond(port, SRC_SEND_CAPABILITIES_TIMEOUT,
+ PD_T_SEND_SOURCE_CAP);
+ }
+ break;
+ case SRC_SEND_CAPABILITIES_TIMEOUT:
+ /*
+ * Error recovery for a PD_DATA_SOURCE_CAP reply timeout.
+ *
+ * PD 2.0 sinks are supposed to accept src-capabilities with a
+ * 3.0 header and simply ignore any src PDOs which the sink does
+ * not understand such as PPS but some 2.0 sinks instead ignore
+ * the entire PD_DATA_SOURCE_CAP message, causing contract
+ * negotiation to fail.
+ *
+ * After PD_N_HARD_RESET_COUNT hard-reset attempts, we try
+ * sending src-capabilities with a lower PD revision to
+ * make these broken sinks work.
+ */
+ if (port->hard_reset_count < PD_N_HARD_RESET_COUNT) {
+ tcpm_set_state(port, HARD_RESET_SEND, 0);
+ } else if (port->negotiated_rev > PD_REV20) {
+ port->negotiated_rev--;
+ port->hard_reset_count = 0;
+ tcpm_set_state(port, SRC_SEND_CAPABILITIES, 0);
+ } else {
+ tcpm_set_state(port, hard_reset_state(port), 0);
+ }
+ break;
+ case SRC_NEGOTIATE_CAPABILITIES:
+ ret = tcpm_pd_check_request(port);
+ if (ret < 0) {
+ tcpm_pd_send_control(port, PD_CTRL_REJECT);
+ if (!port->explicit_contract) {
+ tcpm_set_state(port,
+ SRC_WAIT_NEW_CAPABILITIES, 0);
+ } else {
+ tcpm_set_state(port, SRC_READY, 0);
+ }
+ } else {
+ tcpm_pd_send_control(port, PD_CTRL_ACCEPT);
+ tcpm_set_state(port, SRC_TRANSITION_SUPPLY,
+ PD_T_SRC_TRANSITION);
+ }
+ break;
+ case SRC_TRANSITION_SUPPLY:
+ /* XXX: regulator_set_voltage(vbus, ...) */
+ tcpm_pd_send_control(port, PD_CTRL_PS_RDY);
+ port->explicit_contract = true;
+ typec_set_pwr_opmode(port->typec_port, TYPEC_PWR_MODE_PD);
+ port->pwr_opmode = TYPEC_PWR_MODE_PD;
+ tcpm_set_state_cond(port, SRC_READY, 0);
+ break;
+ case SRC_READY:
+#if 1
+ port->hard_reset_count = 0;
+#endif
+ port->try_src_count = 0;
+
+ tcpm_swap_complete(port, 0);
+ tcpm_typec_connect(port);
+
+ /*
+ * 6.3.5
+ * Sending ping messages is not necessary if
+ * - the source operates at vSafe5V
+ * or
+ * - The system is not operating in PD mode
+ * or
+ * - Both partners are connected using a Type-C connector
+ *
+ * There is no actual need to send PD messages since the local
+ * port type-c and the spec does not clearly say whether PD is
+ * possible when type-c is connected to Type-A/B
+ */
+ break;
+ case SRC_WAIT_NEW_CAPABILITIES:
+ /* Nothing to do... */
+ break;
+
+ /* SNK states */
+ case SNK_UNATTACHED:
+ if (!port->non_pd_role_swap)
+ tcpm_swap_complete(port, -ENOTCONN);
+ tcpm_pps_complete(port, -ENOTCONN);
+ tcpm_snk_detach(port);
+ if (tcpm_start_toggling(port, TYPEC_CC_RD)) {
+ tcpm_set_state(port, TOGGLING, 0);
+ break;
+ }
+ tcpm_set_cc(port, TYPEC_CC_RD);
+ if (port->port_type == TYPEC_PORT_DRP)
+ tcpm_set_state(port, SRC_UNATTACHED, PD_T_DRP_SRC);
+ else if (port->port_type == TYPEC_PORT_SNK)
+ // TODO: sync this with Rong.
+ tcpm_set_state(port, SNK_ATTACH_WAIT, PD_T_DRP_SNK);
+ break;
+ case SNK_ATTACH_WAIT:
+ if ((port->cc1 == TYPEC_CC_OPEN &&
+ port->cc2 != TYPEC_CC_OPEN) ||
+ (port->cc1 != TYPEC_CC_OPEN &&
+ port->cc2 == TYPEC_CC_OPEN))
+ tcpm_set_state(port, SNK_DEBOUNCED,
+ PD_T_CC_DEBOUNCE);
+ else if (tcpm_port_is_disconnected(port))
+ tcpm_set_state(port, SNK_UNATTACHED,
+ PD_T_PD_DEBOUNCE);
+ break;
+ case SNK_DEBOUNCED:
+ if (tcpm_port_is_disconnected(port))
+ tcpm_set_state(port, SNK_UNATTACHED,
+ PD_T_PD_DEBOUNCE);
+ else if (port->vbus_present)
+ tcpm_set_state(port,
+ tcpm_try_src(port) ? SRC_TRY
+ : SNK_ATTACHED,
+ 0);
+ else
+ /* Wait for VBUS, but not forever */
+ tcpm_set_state(port, PORT_RESET, PD_T_PS_SOURCE_ON);
+ break;
+
+ case SRC_TRY:
+ port->try_src_count++;
+ tcpm_set_cc(port, tcpm_rp_cc(port));
+ port->max_wait_ms = 0;
+ tcpm_set_state(port, SRC_TRY_WAIT, 0);
+ break;
+ case SRC_TRY_WAIT:
+ if (port->max_wait_ms == 0) {
+ port->max_wait_ms = get_timer(0) + PD_T_DRP_TRY;
+ msecs = PD_T_DRP_TRY;
+ } else {
+ if (time_before(get_timer(0), port->max_wait_ms))
+ msecs = port->max_wait_ms - get_timer(0);
+ else
+ msecs = 0;
+ }
+ tcpm_set_state(port, SNK_TRYWAIT, msecs);
+ break;
+ case SRC_TRY_DEBOUNCE:
+ tcpm_set_state(port, SRC_ATTACHED, PD_T_PD_DEBOUNCE);
+ break;
+ case SNK_TRYWAIT:
+ tcpm_set_cc(port, TYPEC_CC_RD);
+ tcpm_set_state(port, SNK_TRYWAIT_VBUS, PD_T_CC_DEBOUNCE);
+ break;
+ case SNK_TRYWAIT_VBUS:
+ /*
+ * TCPM stays in this state indefinitely until VBUS
+ * is detected as long as Rp is not detected for
+ * more than a time period of tPDDebounce.
+ */
+ if (port->vbus_present && tcpm_port_is_sink(port)) {
+ tcpm_set_state(port, SNK_ATTACHED, 0);
+ break;
+ }
+ if (!tcpm_port_is_sink(port))
+ tcpm_set_state(port, SNK_TRYWAIT_DEBOUNCE, 0);
+ break;
+ case SNK_TRYWAIT_DEBOUNCE:
+ tcpm_set_state(port, SNK_UNATTACHED, PD_T_PD_DEBOUNCE);
+ break;
+ case SNK_ATTACHED:
+ ret = tcpm_snk_attach(port);
+ if (ret < 0)
+ tcpm_set_state(port, SNK_UNATTACHED, 0);
+ else
+ tcpm_set_state(port, SNK_STARTUP, 0);
+ break;
+ case SNK_STARTUP:
+ opmode = tcpm_get_pwr_opmode(port->polarity ?
+ port->cc2 : port->cc1);
+ typec_set_pwr_opmode(port->typec_port, opmode);
+ port->pwr_opmode = TYPEC_PWR_MODE_USB;
+ port->negotiated_rev = PD_MAX_REV;
+ port->message_id = 0;
+ port->rx_msgid = -1;
+ port->explicit_contract = false;
+ tcpm_set_state(port, SNK_DISCOVERY, 0);
+ break;
+ case SNK_DISCOVERY:
+ if (port->vbus_present) {
+ tcpm_set_current_limit(port,
+ tcpm_get_current_limit(port),
+ 5000);
+ tcpm_set_charge(port, true);
+ tcpm_set_state(port, SNK_WAIT_CAPABILITIES, 0);
+ break;
+ }
+ /*
+ * For DRP, timeouts differ. Also, handling is supposed to be
+ * different and much more complex (dead battery detection;
+ * see USB power delivery specification, section 8.3.3.6.1.5.1).
+ */
+ tcpm_set_state(port, hard_reset_state(port),
+ port->port_type == TYPEC_PORT_DRP ?
+ PD_T_DB_DETECT : PD_T_NO_RESPONSE);
+ break;
+ case SNK_DISCOVERY_DEBOUNCE:
+ tcpm_set_state(port, SNK_DISCOVERY_DEBOUNCE_DONE,
+ PD_T_CC_DEBOUNCE);
+ break;
+ case SNK_DISCOVERY_DEBOUNCE_DONE:
+ if (!tcpm_port_is_disconnected(port) &&
+ tcpm_port_is_sink(port) &&
+ time_before(get_timer(0), port->delayed_runtime_ms)) {
+ tcpm_set_state(port, SNK_DISCOVERY,
+ port->delayed_runtime_ms - get_timer(0));
+ break;
+ }
+ tcpm_set_state(port, unattached_state(port), 0);
+ break;
+ case SNK_WAIT_CAPABILITIES:
+ ret = port->tcpc->set_pd_rx(port->tcpc, true);
+ if (ret < 0) {
+ tcpm_set_state(port, SNK_READY, 0);
+ break;
+ }
+ /*
+ * If VBUS has never been low, and we time out waiting
+ * for source cap, try a soft reset first, in case we
+ * were already in a stable contract before this boot.
+ * Do this only once.
+ */
+ if (port->vbus_never_low) {
+ port->vbus_never_low = false;
+
+ tcpm_pd_send_control(port, PD_CTRL_GET_SOURCE_CAP);
+
+ tcpm_set_state(port, SOFT_RESET_SEND,
+ PD_T_SINK_WAIT_CAP);
+ } else {
+ tcpm_set_state(port, hard_reset_state(port),
+ PD_T_SINK_WAIT_CAP);
+ }
+ break;
+ case SNK_NEGOTIATE_CAPABILITIES:
+ port->pd_capable = true;
+ port->hard_reset_count = 0;
+ ret = tcpm_pd_send_request(port);
+ pr_warn("SRC_NEGOTIATE_CAPABILITIES send_request ret: %d\n", ret);
+ if (ret < 0) {
+ /* Let the Source send capabilities again. */
+ tcpm_set_state(port, SNK_WAIT_CAPABILITIES, 0);
+ } else {
+ tcpm_set_state_cond(port, hard_reset_state(port),
+ PD_T_SENDER_RESPONSE);
+ }
+ break;
+ case SNK_NEGOTIATE_PPS_CAPABILITIES:
+ ret = tcpm_pd_send_pps_request(port);
+ if (ret < 0) {
+ port->pps_status = ret;
+ /*
+ * If this was called due to updates to sink
+ * capabilities, and pps is no longer valid, we should
+ * safely fall back to a standard PDO.
+ */
+ if (port->update_sink_caps)
+ tcpm_set_state(port, SNK_NEGOTIATE_CAPABILITIES, 0);
+ else
+ tcpm_set_state(port, SNK_READY, 0);
+ } else {
+ tcpm_set_state_cond(port, hard_reset_state(port),
+ PD_T_SENDER_RESPONSE);
+ }
+ break;
+ case SNK_TRANSITION_SINK:
+ case SNK_TRANSITION_SINK_VBUS:
+ tcpm_set_state(port, hard_reset_state(port),
+ PD_T_PS_TRANSITION);
+ break;
+ case SNK_READY:
+ port->try_snk_count = 0;
+ port->update_sink_caps = false;
+ if (port->explicit_contract) {
+ typec_set_pwr_opmode(port->typec_port,
+ TYPEC_PWR_MODE_PD);
+ port->pwr_opmode = TYPEC_PWR_MODE_PD;
+ }
+
+ tcpm_swap_complete(port, 0);
+ tcpm_typec_connect(port);
+ tcpm_pps_complete(port, port->pps_status);
+
+ break;
+
+ /* Accessory states */
+ case ACC_UNATTACHED:
+ tcpm_acc_detach(port);
+ tcpm_set_state(port, SRC_UNATTACHED, 0);
+ break;
+ case DEBUG_ACC_ATTACHED:
+ case AUDIO_ACC_ATTACHED:
+ ret = tcpm_acc_attach(port);
+ if (ret < 0)
+ tcpm_set_state(port, ACC_UNATTACHED, 0);
+ break;
+ case AUDIO_ACC_DEBOUNCE:
+ tcpm_set_state(port, ACC_UNATTACHED, PD_T_CC_DEBOUNCE);
+ break;
+
+ /* Hard_Reset states */
+ case HARD_RESET_SEND:
+ tcpm_pd_transmit(port, TCPC_TX_HARD_RESET, NULL);
+ tcpm_set_state(port, HARD_RESET_START, 0);
+ break;
+ case HARD_RESET_START:
+ port->hard_reset_count++;
+ port->tcpc->set_pd_rx(port->tcpc, false);
+ port->send_discover = true;
+ if (port->pwr_role == TYPEC_SOURCE)
+ tcpm_set_state(port, SRC_HARD_RESET_VBUS_OFF,
+ PD_T_PS_HARD_RESET);
+ else
+ tcpm_set_state(port, SNK_HARD_RESET_SINK_OFF, 0);
+ break;
+ case SRC_HARD_RESET_VBUS_OFF:
+ tcpm_set_vconn(port, true);
+ tcpm_set_vbus(port, false);
+ tcpm_set_roles(port, port->self_powered, TYPEC_SOURCE,
+ TYPEC_HOST);
+ tcpm_set_state(port, SRC_HARD_RESET_VBUS_ON, PD_T_SRC_RECOVER);
+ break;
+ case SRC_HARD_RESET_VBUS_ON:
+ tcpm_set_vbus(port, true);
+ port->tcpc->set_pd_rx(port->tcpc, true);
+ tcpm_set_attached_state(port, true);
+ tcpm_set_state(port, SRC_UNATTACHED, PD_T_PS_SOURCE_ON);
+ break;
+ case SNK_HARD_RESET_SINK_OFF:
+ memset(&port->pps_data, 0, sizeof(port->pps_data));
+ tcpm_set_vconn(port, false);
+ if (port->pd_capable)
+ tcpm_set_charge(port, false);
+ tcpm_set_roles(port, port->self_powered, TYPEC_SINK,
+ TYPEC_DEVICE);
+ /*
+ * VBUS may or may not toggle, depending on the adapter.
+ * If it doesn't toggle, transition to SNK_HARD_RESET_SINK_ON
+ * directly after timeout.
+ */
+ tcpm_set_state(port, SNK_HARD_RESET_SINK_ON, PD_T_SAFE_0V);
+ break;
+ case SNK_HARD_RESET_WAIT_VBUS:
+ /* Assume we're disconnected if VBUS doesn't come back. */
+ tcpm_set_state(port, SNK_UNATTACHED,
+ PD_T_SRC_RECOVER_MAX + PD_T_SRC_TURN_ON);
+ break;
+ case SNK_HARD_RESET_SINK_ON:
+ /* Note: There is no guarantee that VBUS is on in this state */
+ /*
+ * XXX:
+ * The specification suggests that dual mode ports in sink
+ * mode should transition to state PE_SRC_Transition_to_default.
+ * See USB power delivery specification chapter 8.3.3.6.1.3.
+ * This would mean to to
+ * - turn off VCONN, reset power supply
+ * - request hardware reset
+ * - turn on VCONN
+ * - Transition to state PE_Src_Startup
+ * SNK only ports shall transition to state Snk_Startup
+ * (see chapter 8.3.3.3.8).
+ * Similar, dual-mode ports in source mode should transition
+ * to PE_SNK_Transition_to_default.
+ */
+ if (port->pd_capable) {
+ tcpm_set_current_limit(port,
+ tcpm_get_current_limit(port),
+ 5000);
+ tcpm_set_charge(port, true);
+ }
+ tcpm_set_attached_state(port, true);
+ tcpm_set_state(port, SNK_STARTUP, 0);
+ break;
+
+ /* Soft_Reset states */
+ case SOFT_RESET:
+ port->message_id = 0;
+ port->rx_msgid = -1;
+ tcpm_pd_send_control(port, PD_CTRL_ACCEPT);
+ if (port->pwr_role == TYPEC_SOURCE)
+ tcpm_set_state(port, SRC_SEND_CAPABILITIES, 0);
+ else
+ tcpm_set_state(port, SNK_WAIT_CAPABILITIES, 0);
+ break;
+ case SOFT_RESET_SEND:
+ port->message_id = 0;
+ port->rx_msgid = -1;
+ ret = tcpm_pd_send_control(port, PD_CTRL_SOFT_RESET);
+ pr_warn("at SOFT_RESET_SEND, tcpm_pd_send_control ret=%d\n", ret);
+ pr_warn(" hard_reset_state(port) = %d\n", hard_reset_state(port));
+ if (ret)
+ tcpm_set_state_cond(port, hard_reset_state(port), 0);
+ else
+ tcpm_set_state_cond(port, hard_reset_state(port),
+ PD_T_SENDER_RESPONSE);
+ break;
+
+ /* DR_Swap states */
+ case DR_SWAP_SEND:
+ tcpm_pd_send_control(port, PD_CTRL_DR_SWAP);
+ tcpm_set_state_cond(port, DR_SWAP_SEND_TIMEOUT,
+ PD_T_SENDER_RESPONSE);
+ break;
+ case DR_SWAP_ACCEPT:
+ tcpm_pd_send_control(port, PD_CTRL_ACCEPT);
+ tcpm_set_state_cond(port, DR_SWAP_CHANGE_DR, 0);
+ break;
+ case DR_SWAP_SEND_TIMEOUT:
+ tcpm_swap_complete(port, -ETIMEDOUT);
+ tcpm_set_state(port, ready_state(port), 0);
+ break;
+ case DR_SWAP_CHANGE_DR:
+ if (port->data_role == TYPEC_HOST) {
+ tcpm_set_roles(port, true, port->pwr_role,
+ TYPEC_DEVICE);
+ } else {
+ tcpm_set_roles(port, true, port->pwr_role,
+ TYPEC_HOST);
+ port->send_discover = true;
+ }
+ tcpm_set_state(port, ready_state(port), 0);
+ break;
+
+ /* PR_Swap states */
+ case PR_SWAP_ACCEPT:
+ tcpm_pd_send_control(port, PD_CTRL_ACCEPT);
+ tcpm_set_state(port, PR_SWAP_START, 0);
+ break;
+ case PR_SWAP_SEND:
+ tcpm_pd_send_control(port, PD_CTRL_PR_SWAP);
+ tcpm_set_state_cond(port, PR_SWAP_SEND_TIMEOUT,
+ PD_T_SENDER_RESPONSE);
+ break;
+ case PR_SWAP_SEND_TIMEOUT:
+ tcpm_swap_complete(port, -ETIMEDOUT);
+ tcpm_set_state(port, ready_state(port), 0);
+ break;
+ case PR_SWAP_START:
+ if (port->pwr_role == TYPEC_SOURCE)
+ tcpm_set_state(port, PR_SWAP_SRC_SNK_TRANSITION_OFF,
+ PD_T_SRC_TRANSITION);
+ else
+ tcpm_set_state(port, PR_SWAP_SNK_SRC_SINK_OFF, 0);
+ break;
+ case PR_SWAP_SRC_SNK_TRANSITION_OFF:
+ tcpm_set_vbus(port, false);
+ port->explicit_contract = false;
+ /* allow time for Vbus discharge, must be < tSrcSwapStdby */
+ tcpm_set_state(port, PR_SWAP_SRC_SNK_SOURCE_OFF,
+ PD_T_SRCSWAPSTDBY);
+ break;
+ case PR_SWAP_SRC_SNK_SOURCE_OFF:
+ tcpm_set_cc(port, TYPEC_CC_RD);
+ /* allow CC debounce */
+ tcpm_set_state(port, PR_SWAP_SRC_SNK_SOURCE_OFF_CC_DEBOUNCED,
+ PD_T_CC_DEBOUNCE);
+ break;
+ case PR_SWAP_SRC_SNK_SOURCE_OFF_CC_DEBOUNCED:
+ /*
+ * USB-PD standard, 6.2.1.4, Port Power Role:
+ * "During the Power Role Swap Sequence, for the initial Source
+ * Port, the Port Power Role field shall be set to Sink in the
+ * PS_RDY Message indicating that the initial Source’s power
+ * supply is turned off"
+ */
+ tcpm_set_pwr_role(port, TYPEC_SINK);
+ if (tcpm_pd_send_control(port, PD_CTRL_PS_RDY)) {
+ tcpm_set_state(port, ERROR_RECOVERY, 0);
+ break;
+ }
+ tcpm_set_state_cond(port, SNK_UNATTACHED, PD_T_PS_SOURCE_ON);
+ break;
+ case PR_SWAP_SRC_SNK_SINK_ON:
+ tcpm_set_state(port, SNK_STARTUP, 0);
+ break;
+ case PR_SWAP_SNK_SRC_SINK_OFF:
+ tcpm_set_charge(port, false);
+ tcpm_set_state(port, hard_reset_state(port),
+ PD_T_PS_SOURCE_OFF);
+ break;
+ case PR_SWAP_SNK_SRC_SOURCE_ON:
+ tcpm_set_cc(port, tcpm_rp_cc(port));
+ tcpm_set_vbus(port, true);
+ /*
+ * allow time VBUS ramp-up, must be < tNewSrc
+ * Also, this window overlaps with CC debounce as well.
+ * So, Wait for the max of two which is PD_T_NEWSRC
+ */
+ tcpm_set_state(port, PR_SWAP_SNK_SRC_SOURCE_ON_VBUS_RAMPED_UP,
+ PD_T_NEWSRC);
+ break;
+ case PR_SWAP_SNK_SRC_SOURCE_ON_VBUS_RAMPED_UP:
+ /*
+ * USB PD standard, 6.2.1.4:
+ * "Subsequent Messages initiated by the Policy Engine,
+ * such as the PS_RDY Message sent to indicate that Vbus
+ * is ready, will have the Port Power Role field set to
+ * Source."
+ */
+ tcpm_set_pwr_role(port, TYPEC_SOURCE);
+ tcpm_pd_send_control(port, PD_CTRL_PS_RDY);
+ tcpm_set_state(port, SRC_STARTUP, 0);
+ break;
+
+ case VCONN_SWAP_ACCEPT:
+ tcpm_pd_send_control(port, PD_CTRL_ACCEPT);
+ tcpm_set_state(port, VCONN_SWAP_START, 0);
+ break;
+ case VCONN_SWAP_SEND:
+ tcpm_pd_send_control(port, PD_CTRL_VCONN_SWAP);
+ tcpm_set_state(port, VCONN_SWAP_SEND_TIMEOUT,
+ PD_T_SENDER_RESPONSE);
+ break;
+ case VCONN_SWAP_SEND_TIMEOUT:
+ tcpm_swap_complete(port, -ETIMEDOUT);
+ tcpm_set_state(port, ready_state(port), 0);
+ break;
+ case VCONN_SWAP_START:
+ if (port->vconn_role == TYPEC_SOURCE)
+ tcpm_set_state(port, VCONN_SWAP_WAIT_FOR_VCONN, 0);
+ else
+ tcpm_set_state(port, VCONN_SWAP_TURN_ON_VCONN, 0);
+ break;
+ case VCONN_SWAP_WAIT_FOR_VCONN:
+ tcpm_set_state(port, hard_reset_state(port),
+ PD_T_VCONN_SOURCE_ON);
+ break;
+ case VCONN_SWAP_TURN_ON_VCONN:
+ tcpm_set_vconn(port, true);
+ tcpm_pd_send_control(port, PD_CTRL_PS_RDY);
+ tcpm_set_state(port, ready_state(port), 0);
+ break;
+ case VCONN_SWAP_TURN_OFF_VCONN:
+ tcpm_set_vconn(port, false);
+ tcpm_set_state(port, ready_state(port), 0);
+ break;
+
+ case DR_SWAP_CANCEL:
+ case PR_SWAP_CANCEL:
+ case VCONN_SWAP_CANCEL:
+ tcpm_swap_complete(port, port->swap_status);
+ if (port->pwr_role == TYPEC_SOURCE)
+ tcpm_set_state(port, SRC_READY, 0);
+ else
+ tcpm_set_state(port, SNK_READY, 0);
+ break;
+
+ case BIST_RX:
+ switch (BDO_MODE_MASK(port->bist_request)) {
+ case BDO_MODE_CARRIER2:
+ tcpm_pd_transmit(port, TCPC_TX_BIST_MODE_2, NULL);
+ break;
+ default:
+ break;
+ }
+ /* Always switch to unattached state */
+ tcpm_set_state(port, unattached_state(port), 0);
+ break;
+ case GET_STATUS_SEND:
+ tcpm_pd_send_control(port, PD_CTRL_GET_STATUS);
+ tcpm_set_state(port, GET_STATUS_SEND_TIMEOUT,
+ PD_T_SENDER_RESPONSE);
+ break;
+ case GET_STATUS_SEND_TIMEOUT:
+ tcpm_set_state(port, ready_state(port), 0);
+ break;
+ case GET_PPS_STATUS_SEND:
+ tcpm_pd_send_control(port, PD_CTRL_GET_PPS_STATUS);
+ tcpm_set_state(port, GET_PPS_STATUS_SEND_TIMEOUT,
+ PD_T_SENDER_RESPONSE);
+ break;
+ case GET_PPS_STATUS_SEND_TIMEOUT:
+ tcpm_set_state(port, ready_state(port), 0);
+ break;
+ case ERROR_RECOVERY:
+ tcpm_swap_complete(port, -EPROTO);
+ tcpm_pps_complete(port, -EPROTO);
+ tcpm_set_state(port, PORT_RESET, 0);
+ break;
+ case PORT_RESET:
+ tcpm_reset_port(port);
+ //tcpm_set_cc(port, TYPEC_CC_OPEN);
+ if (port->port_type == TYPEC_PORT_SNK) {
+ tcpm_set_state(port, tcpm_default_state(port), 0);
+ } else {
+ tcpm_set_state(port, PORT_RESET_WAIT_OFF,
+ PD_T_ERROR_RECOVERY);
+ }
+ break;
+ case PORT_RESET_WAIT_OFF:
+ tcpm_set_state(port,
+ tcpm_default_state(port),
+ port->vbus_present ? PD_T_PS_SOURCE_OFF : 0);
+ break;
+ default:
+ tcpm_log(port, "Unexpected port state %d\n", port->state);
+ break;
+ }
+}
+
+void tcpm_run_state_machine(struct tcpm_port *port)
+{
+ enum tcpm_state prev_state;
+
+ if (port->queued_message && tcpm_send_queued_message(port))
+ return;
+
+ /* not wait long enough */
+ if (port->delayed_state &&
+ time_before(get_timer(0), port->delayed_runtime_ms)) {
+ return;
+ }
+
+ /* If we were queued due to a delayed state change, update it now */
+ if (port->delayed_state) {
+ tcpm_log(port, "state change %s -> %s [delayed %ld ms]",
+ tcpm_states[port->state],
+ tcpm_states[port->delayed_state], port->delay_ms);
+ port->prev_state = port->state;
+ port->state = port->delayed_state;
+ port->delayed_state = INVALID_STATE;
+ }
+
+ /*
+ * Continue running as long as we have (non-delayed) state changes
+ * to make.
+ */
+ do {
+ prev_state = port->state;
+ run_state_machine(port);
+ if (port->queued_message)
+ tcpm_send_queued_message(port);
+ } while (port->state != prev_state && !port->delayed_state);
+
+}
+
+static void _tcpm_cc_change(struct tcpm_port *port, enum typec_cc_status cc1,
+ enum typec_cc_status cc2)
+{
+ enum typec_cc_status old_cc1, old_cc2;
+ enum tcpm_state new_state;
+
+ old_cc1 = port->cc1;
+ old_cc2 = port->cc2;
+ port->cc1 = cc1;
+ port->cc2 = cc2;
+
+ tcpm_log_force(port,
+ "CC1: %u -> %u, CC2: %u -> %u [state %s, polarity %d, %s]",
+ old_cc1, cc1, old_cc2, cc2, tcpm_states[port->state],
+ port->polarity,
+ tcpm_port_is_disconnected(port) ? "disconnected"
+ : "connected");
+
+ switch (port->state) {
+ case TOGGLING:
+ if (tcpm_port_is_debug(port) || tcpm_port_is_audio(port) ||
+ tcpm_port_is_source(port))
+ tcpm_set_state(port, SRC_ATTACH_WAIT, 0);
+ else if (tcpm_port_is_sink(port))
+ tcpm_set_state(port, SNK_ATTACH_WAIT, 0);
+ break;
+ case SRC_UNATTACHED:
+ case ACC_UNATTACHED:
+ if (tcpm_port_is_debug(port) || tcpm_port_is_audio(port) ||
+ tcpm_port_is_source(port))
+ tcpm_set_state(port, SRC_ATTACH_WAIT, 0);
+ break;
+ case SRC_ATTACH_WAIT:
+ if (tcpm_port_is_disconnected(port) ||
+ tcpm_port_is_audio_detached(port))
+ tcpm_set_state(port, SRC_UNATTACHED, 0);
+ else if (cc1 != old_cc1 || cc2 != old_cc2)
+ tcpm_set_state(port, SRC_ATTACH_WAIT, 0);
+ break;
+ case SRC_ATTACHED:
+ case SRC_SEND_CAPABILITIES:
+ case SRC_READY:
+ if (tcpm_port_is_disconnected(port) ||
+ !tcpm_port_is_source(port))
+ tcpm_set_state(port, SRC_UNATTACHED, 0);
+ break;
+ case SNK_UNATTACHED:
+ if (tcpm_port_is_sink(port))
+ tcpm_set_state(port, SNK_ATTACH_WAIT, 0);
+ break;
+ case SNK_ATTACH_WAIT:
+ if ((port->cc1 == TYPEC_CC_OPEN &&
+ port->cc2 != TYPEC_CC_OPEN) ||
+ (port->cc1 != TYPEC_CC_OPEN &&
+ port->cc2 == TYPEC_CC_OPEN))
+ new_state = SNK_DEBOUNCED;
+ else if (tcpm_port_is_disconnected(port))
+ new_state = SNK_UNATTACHED;
+ else
+ break;
+ if (new_state != port->delayed_state)
+ tcpm_set_state(port, SNK_ATTACH_WAIT, 0);
+ break;
+ case SNK_DEBOUNCED:
+ if (tcpm_port_is_disconnected(port))
+ new_state = SNK_UNATTACHED;
+ else if (port->vbus_present)
+ new_state = tcpm_try_src(port) ? SRC_TRY : SNK_ATTACHED;
+ else
+ new_state = SNK_UNATTACHED;
+ if (new_state != port->delayed_state)
+ tcpm_set_state(port, SNK_DEBOUNCED, 0);
+ break;
+ case SNK_READY:
+ if (tcpm_port_is_disconnected(port))
+ tcpm_set_state(port, unattached_state(port), 0);
+ else if (!port->pd_capable &&
+ (cc1 != old_cc1 || cc2 != old_cc2))
+ tcpm_set_current_limit(port,
+ tcpm_get_current_limit(port),
+ 5000);
+ break;
+
+ case AUDIO_ACC_ATTACHED:
+ if (cc1 == TYPEC_CC_OPEN || cc2 == TYPEC_CC_OPEN)
+ tcpm_set_state(port, AUDIO_ACC_DEBOUNCE, 0);
+ break;
+ case AUDIO_ACC_DEBOUNCE:
+ if (tcpm_port_is_audio(port))
+ tcpm_set_state(port, AUDIO_ACC_ATTACHED, 0);
+ break;
+
+ case DEBUG_ACC_ATTACHED:
+ if (cc1 == TYPEC_CC_OPEN || cc2 == TYPEC_CC_OPEN)
+ tcpm_set_state(port, ACC_UNATTACHED, 0);
+ break;
+
+ case SNK_TRY:
+ /* Do nothing, waiting for timeout */
+ break;
+
+ case SNK_DISCOVERY:
+ /* CC line is unstable, wait for debounce */
+ if (tcpm_port_is_disconnected(port))
+ tcpm_set_state(port, SNK_DISCOVERY_DEBOUNCE, 0);
+ break;
+ case SNK_DISCOVERY_DEBOUNCE:
+ break;
+
+ case SRC_TRYWAIT:
+ /* Hand over to state machine if needed */
+ if (!port->vbus_present && tcpm_port_is_source(port))
+ tcpm_set_state(port, SRC_TRYWAIT_DEBOUNCE, 0);
+ break;
+ case SRC_TRYWAIT_DEBOUNCE:
+ if (port->vbus_present || !tcpm_port_is_source(port))
+ tcpm_set_state(port, SRC_TRYWAIT, 0);
+ break;
+ case SNK_TRY_WAIT_DEBOUNCE:
+ if (!tcpm_port_is_sink(port)) {
+ port->max_wait_ms = 0;
+ tcpm_set_state(port, SRC_TRYWAIT, 0);
+ }
+ break;
+ case SRC_TRY_WAIT:
+ if (tcpm_port_is_source(port))
+ tcpm_set_state(port, SRC_TRY_DEBOUNCE, 0);
+ break;
+ case SRC_TRY_DEBOUNCE:
+ tcpm_set_state(port, SRC_TRY_WAIT, 0);
+ break;
+ case SNK_TRYWAIT_DEBOUNCE:
+ if (tcpm_port_is_sink(port))
+ tcpm_set_state(port, SNK_TRYWAIT_VBUS, 0);
+ break;
+ case SNK_TRYWAIT_VBUS:
+ if (!tcpm_port_is_sink(port))
+ tcpm_set_state(port, SNK_TRYWAIT_DEBOUNCE, 0);
+ break;
+ case SNK_TRYWAIT:
+ /* Do nothing, waiting for tCCDebounce */
+ break;
+ case PR_SWAP_SNK_SRC_SINK_OFF:
+ case PR_SWAP_SRC_SNK_TRANSITION_OFF:
+ case PR_SWAP_SRC_SNK_SOURCE_OFF:
+ case PR_SWAP_SRC_SNK_SOURCE_OFF_CC_DEBOUNCED:
+ case PR_SWAP_SNK_SRC_SOURCE_ON:
+ /*
+ * CC state change is expected in PR_SWAP
+ * Ignore it.
+ */
+ break;
+
+ case PORT_RESET:
+ case PORT_RESET_WAIT_OFF:
+ /*
+ * State set back to default mode once the timer completes.
+ * Ignore CC changes here.
+ */
+ break;
+
+ default:
+ if (tcpm_port_is_disconnected(port))
+ tcpm_set_state(port, unattached_state(port), 0);
+ break;
+ }
+}
+
+static void _tcpm_pd_vbus_on(struct tcpm_port *port)
+{
+ tcpm_log_force(port, "VBUS on");
+ port->vbus_present = true;
+ switch (port->state) {
+ case SNK_TRANSITION_SINK_VBUS:
+ port->explicit_contract = true;
+ tcpm_set_state(port, SNK_READY, 0);
+ break;
+ case SNK_DISCOVERY:
+ tcpm_set_state(port, SNK_DISCOVERY, 0);
+ break;
+
+ case SNK_DEBOUNCED:
+ tcpm_set_state(port, tcpm_try_src(port) ? SRC_TRY
+ : SNK_ATTACHED,
+ 0);
+ break;
+ case SNK_HARD_RESET_WAIT_VBUS:
+ tcpm_set_state(port, SNK_HARD_RESET_SINK_ON, 0);
+ break;
+ case SRC_ATTACHED:
+ tcpm_set_state(port, SRC_STARTUP, 0);
+ break;
+ case SRC_HARD_RESET_VBUS_ON:
+ tcpm_set_state(port, SRC_STARTUP, 0);
+ break;
+
+ case SNK_TRY:
+ /* Do nothing, waiting for timeout */
+ break;
+ case SRC_TRYWAIT:
+ /* Do nothing, Waiting for Rd to be detected */
+ break;
+ case SRC_TRYWAIT_DEBOUNCE:
+ tcpm_set_state(port, SRC_TRYWAIT, 0);
+ break;
+ case SNK_TRY_WAIT_DEBOUNCE:
+ /* Do nothing, waiting for PD_DEBOUNCE to do be done */
+ break;
+ case SNK_TRYWAIT:
+ /* Do nothing, waiting for tCCDebounce */
+ break;
+ case SNK_TRYWAIT_VBUS:
+ if (tcpm_port_is_sink(port))
+ tcpm_set_state(port, SNK_ATTACHED, 0);
+ break;
+ case SNK_TRYWAIT_DEBOUNCE:
+ /* Do nothing, waiting for Rp */
+ break;
+ case SRC_TRY_WAIT:
+ case SRC_TRY_DEBOUNCE:
+ /* Do nothing, waiting for sink detection */
+ break;
+
+ case PORT_RESET:
+ case PORT_RESET_WAIT_OFF:
+ /*
+ * State set back to default mode once the timer completes.
+ * Ignore vbus changes here.
+ */
+ break;
+
+ default:
+ break;
+ }
+}
+
+static void _tcpm_pd_vbus_off(struct tcpm_port *port)
+{
+ tcpm_log_force(port, "VBUS off");
+ port->vbus_present = false;
+ port->vbus_never_low = false;
+ switch (port->state) {
+ case SNK_HARD_RESET_SINK_OFF:
+ tcpm_set_state(port, SNK_HARD_RESET_WAIT_VBUS, 0);
+ break;
+ case SRC_HARD_RESET_VBUS_OFF:
+ tcpm_set_state(port, SRC_HARD_RESET_VBUS_ON, 0);
+ break;
+ case HARD_RESET_SEND:
+ break;
+
+ case SNK_TRY:
+ /* Do nothing, waiting for timeout */
+ break;
+ case SRC_TRYWAIT:
+ /* Hand over to state machine if needed */
+ if (tcpm_port_is_source(port))
+ tcpm_set_state(port, SRC_TRYWAIT_DEBOUNCE, 0);
+ break;
+ case SNK_TRY_WAIT_DEBOUNCE:
+ /* Do nothing, waiting for PD_DEBOUNCE to do be done */
+ break;
+ case SNK_TRYWAIT:
+ case SNK_TRYWAIT_VBUS:
+ case SNK_TRYWAIT_DEBOUNCE:
+ break;
+ case SNK_ATTACH_WAIT:
+ tcpm_set_state(port, SNK_UNATTACHED, 0);
+ break;
+
+ case SNK_NEGOTIATE_CAPABILITIES:
+ break;
+
+ case PR_SWAP_SRC_SNK_TRANSITION_OFF:
+ tcpm_set_state(port, PR_SWAP_SRC_SNK_SOURCE_OFF, 0);
+ break;
+
+ case PR_SWAP_SNK_SRC_SINK_OFF:
+ /* Do nothing, expected */
+ break;
+
+ case PORT_RESET_WAIT_OFF:
+ tcpm_set_state(port, tcpm_default_state(port), 0);
+ break;
+
+ case SRC_TRY_WAIT:
+ case SRC_TRY_DEBOUNCE:
+ /* Do nothing, waiting for sink detection */
+ break;
+
+ case PORT_RESET:
+ /*
+ * State set back to default mode once the timer completes.
+ * Ignore vbus changes here.
+ */
+ break;
+
+ default:
+ if (port->pwr_role == TYPEC_SINK &&
+ port->attached)
+ tcpm_set_state(port, SNK_UNATTACHED, 0);
+ break;
+ }
+}
+
+static void _tcpm_pd_hard_reset(struct tcpm_port *port)
+{
+ tcpm_log_force(port, "Received hard reset");
+ /*
+ * If we keep receiving hard reset requests, executing the hard reset
+ * must have failed. Revert to error recovery if that happens.
+ */
+ tcpm_set_state(port,
+ port->hard_reset_count < PD_N_HARD_RESET_COUNT ?
+ HARD_RESET_START : ERROR_RECOVERY,
+ 0);
+}
+
+void tcpm_handle_pd_event(struct tcpm_port *port)
+{
+ u32 events;
+
+ while (port->pd_events) {
+ events = port->pd_events;
+ port->pd_events = 0;
+ if (events & TCPM_RESET_EVENT)
+ _tcpm_pd_hard_reset(port);
+ if (events & TCPM_VBUS_EVENT) {
+ bool vbus;
+
+ vbus = port->tcpc->get_vbus(port->tcpc);
+ if (vbus)
+ _tcpm_pd_vbus_on(port);
+ else
+ _tcpm_pd_vbus_off(port);
+ }
+ if (events & TCPM_CC_EVENT) {
+ enum typec_cc_status cc1, cc2;
+
+ if (port->tcpc->get_cc(port->tcpc, &cc1, &cc2) == 0)
+ _tcpm_cc_change(port, cc1, cc2);
+ }
+ if (events & TCPM_RX_EVENT) {
+ tcpm_handle_pd_rx_event(port);
+ }
+ }
+}
+
+void tcpm_cc_change(struct tcpm_port *port)
+{
+ port->pd_events |= TCPM_CC_EVENT;
+}
+EXPORT_SYMBOL_GPL(tcpm_cc_change);
+
+void tcpm_vbus_change(struct tcpm_port *port)
+{
+ port->pd_events |= TCPM_VBUS_EVENT;
+}
+EXPORT_SYMBOL_GPL(tcpm_vbus_change);
+
+void tcpm_pd_hard_reset(struct tcpm_port *port)
+{
+ port->pd_events = TCPM_RESET_EVENT;
+}
+EXPORT_SYMBOL_GPL(tcpm_pd_hard_reset);
+
+bool tcpm_is_snk_ready(struct tcpm_port *port)
+{
+ return port->state == SNK_READY;
+}
+EXPORT_SYMBOL_GPL(tcpm_is_snk_ready)
+
+static void tcpm_init(struct tcpm_port *port)
+{
+ enum typec_cc_status cc1, cc2;
+ int ret;
+
+ ret = port->tcpc->init(port->tcpc);
+ pr_warn("tcpm_init tcpc->init ret: %d\n", ret);
+
+ tcpm_reset_port(port);
+
+ /*
+ * XXX
+ * Should possibly wait for VBUS to settle if it was enabled locally
+ * since tcpm_reset_port() will disable VBUS.
+ */
+ port->vbus_present = port->tcpc->get_vbus(port->tcpc);
+ if (port->vbus_present)
+ port->vbus_never_low = true;
+
+ tcpm_set_state(port, tcpm_default_state(port), 0);
+
+ if (port->tcpc->get_cc(port->tcpc, &cc1, &cc2) == 0)
+ _tcpm_cc_change(port, cc1, cc2);
+
+ /*
+ * Some adapters need a clean slate at startup, and won't recover
+ * otherwise. So do not try to be fancy and force a clean disconnect.
+ */
+ tcpm_set_state(port, PORT_RESET, 0);
+}
+
+static const struct typec_operations tcpm_ops = {
+};
+
+void tcpm_tcpc_reset(struct tcpm_port *port)
+{
+ /* XXX: Maintain PD connection if possible? */
+ tcpm_init(port);
+}
+EXPORT_SYMBOL_GPL(tcpm_tcpc_reset);
+
+static int tcpm_copy_pdos(u32 *dest_pdo, const u32 *src_pdo,
+ unsigned int nr_pdo)
+{
+ unsigned int i;
+
+ if (nr_pdo > PDO_MAX_OBJECTS)
+ nr_pdo = PDO_MAX_OBJECTS;
+
+ for (i = 0; i < nr_pdo; i++)
+ dest_pdo[i] = src_pdo[i];
+
+ return nr_pdo;
+}
+
+static int tcpm_copy_vdos(u32 *dest_vdo, const u32 *src_vdo,
+ unsigned int nr_vdo)
+{
+ unsigned int i;
+
+ if (nr_vdo > VDO_MAX_OBJECTS)
+ nr_vdo = VDO_MAX_OBJECTS;
+
+ for (i = 0; i < nr_vdo; i++)
+ dest_vdo[i] = src_vdo[i];
+
+ return nr_vdo;
+}
+
+static int tcpm_of_get_caps(struct tcpm_port *port,
+ ofnode *ofnode)
+{
+ const char *cap_str;
+ int ret;
+ u32 mw;
+ u32 val;
+
+ if (!ofnode)
+ return -EINVAL;
+
+ /* VCONN capability is true by default */
+ port->typec_caps.no_vconn = (ofnode_get_property(*ofnode,
+ "no-vconn", NULL) != NULL);
+
+ /* USB data support is optional */
+ cap_str = ofnode_read_string(*ofnode, "data-role");
+ if (cap_str) {
+ ret = typec_find_port_data_role(cap_str);
+ if (ret < 0)
+ return ret;
+ port->typec_caps.data = ret;
+ }
+
+ cap_str = ofnode_read_string(*ofnode, "power-role");
+ if (!cap_str)
+ return ret;
+
+ ret = typec_find_port_power_role(cap_str);
+ if (ret < 0)
+ return ret;
+ port->typec_caps.type = ret;
+ port->port_type = port->typec_caps.type;
+
+ if (port->port_type == TYPEC_PORT_SNK)
+ goto sink;
+
+ /* Get source pdo. Support onlt 1 pdo. */
+ ret = ofnode_read_u32(*ofnode, "source-pdo", &val);
+ if (ret < 0)
+ return -EINVAL;
+ port->nr_src_pdo = 1;
+ port->src_pdo[0] = val;
+
+ if (tcpm_validate_caps(port, port->src_pdo,
+ port->nr_src_pdo))
+ return -EINVAL;
+
+ if (port->port_type == TYPEC_PORT_SRC)
+ return 0;
+
+ /* Get the preferred power role for DRP */
+ cap_str = ofnode_read_string(*ofnode, "try-power-role");
+ if (!cap_str)
+ return ret;
+
+ port->typec_caps.prefer_role = typec_find_power_role(cap_str);
+ if (port->typec_caps.prefer_role < 0)
+ return -EINVAL;
+sink:
+ /* Get sink pdos. Only support 1 sink-pdo. */
+ ret = ofnode_read_u32(*ofnode, "sink-pdo", &val);
+ if (ret < 0)
+ return -EINVAL;
+
+ port->nr_snk_pdo = 1;
+ port->snk_pdo[0] = val;
+ if (tcpm_validate_caps(port, port->snk_pdo,
+ port->nr_snk_pdo))
+ return -EINVAL;
+
+ if (ofnode_read_u32(*ofnode, "op-sink-microwatt", &mw) < 0)
+ return -EINVAL;
+ port->operating_snk_mw = mw / 1000;
+
+ port->self_powered = ofnode_read_bool(*ofnode, "self-powered");
+
+ return 0;
+}
+
+static int tcpm_copy_caps(struct tcpm_port *port,
+ const struct tcpc_config *tcfg)
+{
+ if (tcpm_validate_caps(port, tcfg->src_pdo, tcfg->nr_src_pdo) ||
+ tcpm_validate_caps(port, tcfg->snk_pdo, tcfg->nr_snk_pdo))
+ return -EINVAL;
+
+ port->nr_src_pdo = tcpm_copy_pdos(port->src_pdo, tcfg->src_pdo,
+ tcfg->nr_src_pdo);
+ port->nr_snk_pdo = tcpm_copy_pdos(port->snk_pdo, tcfg->snk_pdo,
+ tcfg->nr_snk_pdo);
+
+ port->nr_snk_vdo = tcpm_copy_vdos(port->snk_vdo, tcfg->snk_vdo,
+ tcfg->nr_snk_vdo);
+
+ port->operating_snk_mw = tcfg->operating_snk_mw;
+
+ port->typec_caps.prefer_role = tcfg->default_role;
+ port->typec_caps.type = tcfg->type;
+ port->typec_caps.data = tcfg->data;
+ port->self_powered = tcfg->self_powered;
+
+ return 0;
+}
+
+struct tcpm_port *tcpm_register_port(struct udevice *dev, struct tcpc_dev *tcpc)
+{
+ struct tcpm_port *port;
+ int err;
+
+ if (!dev || !tcpc ||
+ !tcpc->get_vbus || !tcpc->set_cc || !tcpc->get_cc ||
+ !tcpc->set_polarity || !tcpc->set_vconn || !tcpc->set_vbus ||
+ !tcpc->set_pd_rx || !tcpc->set_roles || !tcpc->pd_transmit)
+ return ERR_PTR(-EINVAL);
+
+ port = kzalloc(sizeof(*port), GFP_KERNEL);
+ if (!port)
+ return ERR_PTR(-ENOMEM);
+
+ port->dev = dev;
+ port->tcpc = tcpc;
+
+ err = tcpm_of_get_caps(port, tcpc->ofnode);
+ if ((err < 0) && tcpc->config)
+ err = tcpm_copy_caps(port, tcpc->config);
+ if (err < 0)
+ goto out_destroy_wq;
+
+ if (!tcpc->config || !tcpc->config->try_role_hw)
+ port->try_role = port->typec_caps.prefer_role;
+ else
+ port->try_role = TYPEC_NO_PREFERRED_ROLE;
+
+ port->typec_caps.ofnode = tcpc->ofnode;
+ port->typec_caps.revision = 0x0120; /* Type-C spec release 1.2 */
+ port->typec_caps.pd_revision = 0x0300; /* USB-PD spec release 3.0 */
+ port->typec_caps.driver_data = port;
+ port->typec_caps.ops = &tcpm_ops;
+
+ port->partner_desc.identity = &port->partner_ident;
+ port->port_type = port->typec_caps.type;
+
+ port->role_sw = usb_role_switch_get(port->dev);
+ if (IS_ERR(port->role_sw)) {
+ err = PTR_ERR(port->role_sw);
+ goto out_destroy_wq;
+ }
+
+ port->typec_port = typec_register_port(port->dev, &port->typec_caps);
+ if (IS_ERR(port->typec_port)) {
+ err = PTR_ERR(port->typec_port);
+ goto out_role_sw_put;
+ }
+
+ tcpm_init(port);
+
+ tcpm_log(port, "%s: registered tcpm", dev->name);
+ return port;
+
+out_role_sw_put:
+ usb_role_switch_put(port->role_sw);
+out_destroy_wq:
+ return ERR_PTR(err);
+}
+EXPORT_SYMBOL_GPL(tcpm_register_port);
+
+void tcpm_unregister_port(struct tcpm_port *port)
+{
+ tcpm_reset_port(port);
+ typec_unregister_port(port->typec_port);
+ usb_role_switch_put(port->role_sw);
+}
+EXPORT_SYMBOL_GPL(tcpm_unregister_port);
diff --git a/drivers/usb/ulpi/Kconfig b/drivers/usb/ulpi/Kconfig
index 44770f9..001564d 100644
--- a/drivers/usb/ulpi/Kconfig
+++ b/drivers/usb/ulpi/Kconfig
@@ -30,4 +30,3 @@
PHY Transreceiver for USB controllers.
This driver uses ULPI viewports that are specific for each SoC.
-
diff --git a/drivers/video/Kconfig b/drivers/video/Kconfig
index 56de9a7..25c94f4 100644
--- a/drivers/video/Kconfig
+++ b/drivers/video/Kconfig
@@ -723,4 +723,3 @@
textual overlays of the display outputs.
endmenu
-
diff --git a/drivers/video/bridge/Kconfig b/drivers/video/bridge/Kconfig
index 5cc71e0..765f738 100644
--- a/drivers/video/bridge/Kconfig
+++ b/drivers/video/bridge/Kconfig
@@ -33,4 +33,3 @@
help
The Analogix ANX6345 is RGB-to-DP converter. It enables an eDP LCD
panel to be connected to an parallel LCD interface.
-
diff --git a/drivers/video/fonts/Kconfig b/drivers/video/fonts/Kconfig
index fb1fafc..c692fa9 100644
--- a/drivers/video/fonts/Kconfig
+++ b/drivers/video/fonts/Kconfig
@@ -50,4 +50,3 @@
http://scripts.sil.org/cms/scripts/page.php?site_id=nrsi&id=OFL
endmenu
-
diff --git a/drivers/video/fonts/rufscript010.ttf b/drivers/video/fonts/rufscript010.ttf
deleted file mode 100644
index 887a449..0000000
--- a/drivers/video/fonts/rufscript010.ttf
+++ /dev/null
Binary files differ
diff --git a/drivers/video/rockchip/Kconfig b/drivers/video/rockchip/Kconfig
index fd6d5ba..b1d7c62 100644
--- a/drivers/video/rockchip/Kconfig
+++ b/drivers/video/rockchip/Kconfig
@@ -68,4 +68,3 @@
16,18, 24 bits per pixel with upto 2k resolution ratio.
endif
-
diff --git a/drivers/virtio/Kconfig b/drivers/virtio/Kconfig
index 5351261..a9d5fd0 100644
--- a/drivers/virtio/Kconfig
+++ b/drivers/virtio/Kconfig
@@ -60,4 +60,3 @@
QEMU based targets.
endmenu
-
diff --git a/drivers/w1-eeprom/Kconfig b/drivers/w1-eeprom/Kconfig
index 9756541..34aca4b 100644
--- a/drivers/w1-eeprom/Kconfig
+++ b/drivers/w1-eeprom/Kconfig
@@ -40,4 +40,3 @@
endif
endmenu
-
diff --git a/drivers/w1/Kconfig b/drivers/w1/Kconfig
index db5aa85..031bab2 100644
--- a/drivers/w1/Kconfig
+++ b/drivers/w1/Kconfig
@@ -37,4 +37,3 @@
endif
endmenu
-
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index c586164..0f6ef0b 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -165,4 +165,3 @@
found on some Amlogic Meson chips.
endmenu
-
diff --git a/drivers/watchdog/meson_wdt.c b/drivers/watchdog/meson_wdt.c
index dd8f93a..3ad15da 100644
--- a/drivers/watchdog/meson_wdt.c
+++ b/drivers/watchdog/meson_wdt.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
/*
- * Copyright 2018 Amlogic, Inc
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#include <common.h>
@@ -11,26 +10,42 @@
#include <asm/io.h>
#include <linux/io.h>
#include <clk.h>
+#include <asm/arch/bl31_apis.h>
#define MESON_WDT_CTRL_REG 0x0
+#define MESON_WDT_CTRL1_REG 0x4
#define MESON_WDT_TCNT_REG 0x8
#define MESON_WDT_RSET_REG 0xc
#define MESON_WDT_CTRL_CLKDIV_EN BIT(25)
#define MESON_WDT_CTRL_CLK_EN BIT(24)
-#define MESON_WDT_CTRL_EE_RESET BIT(21)
#define MESON_WDT_CTRL_EN BIT(18)
#define MESON_WDT_CTRL_DIV_MASK (BIT(18) - 1)
#define MESON_WDT_TCNT_SETUP_MASK (BIT(16) - 1)
#define MESON_WDT_TCNT_CNT_SHIFT (16)
+#define MESON_WDT_RST_SIG_EN BIT(17)
-#define DEFAULT_TIMEOUT 1
+#define WDT_DISABLE 1
+#define WDT_ENABLE 2
+#define WDT_PING 3
+#define WDT_INIT 4
+#define WDT_RESETNOW 5
+#define WDT_SETTIMEOUT 6
+#define WDT_OPS 0x82000086
+
+#define DEFAULT_TIMEOUT 1 /* second */
struct meson_wdt_priv {
void __iomem *regs;
};
-static int meson_wdt_reset(struct udevice *dev)
+struct meson_wdt_data {
+ unsigned char rst_shift;
+ struct wdt_ops *ops;
+};
+
+/***************** gxbb ***********************/
+static int meson_gxbb_wdt_reset(struct udevice *dev)
{
struct meson_wdt_priv *priv;
@@ -41,35 +56,35 @@
return 0;
}
-static int meson_wdt_set_timeout(struct udevice *dev, unsigned int timeout)
+static int meson_gxbb_wdt_set_timeout(struct udevice *dev, u64 timeout_ms)
{
struct meson_wdt_priv *priv;
- unsigned long tcnt = timeout * 1000;
+ unsigned long tcnt = timeout_ms;
assert(dev);
priv = dev_get_priv(dev);
if (tcnt > MESON_WDT_TCNT_SETUP_MASK)
tcnt = MESON_WDT_TCNT_SETUP_MASK;
- meson_wdt_reset(dev);
+ meson_gxbb_wdt_reset(dev);
writel(tcnt, priv->regs + MESON_WDT_TCNT_REG);
return 0;
}
-static int meson_wdt_start(struct udevice *dev, u64 timeout, ulong flags)
+static int meson_gxbb_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
{
struct meson_wdt_priv *priv;
assert(dev);
priv = dev_get_priv(dev);
- meson_wdt_set_timeout(dev, timeout);
+ meson_gxbb_wdt_set_timeout(dev, timeout_ms);
writel(readl(priv->regs + MESON_WDT_CTRL_REG) | MESON_WDT_CTRL_EN,
priv->regs + MESON_WDT_CTRL_REG);
return 0;
}
-static int meson_wdt_stop(struct udevice *dev)
+static int meson_gxbb_wdt_stop(struct udevice *dev)
{
struct meson_wdt_priv *priv;
@@ -81,13 +96,119 @@
return 0;
}
-static int meson_wdt_expire_now(struct udevice *dev, ulong flags)
+static int meson_gxbb_wdt_expire_now(struct udevice *dev, ulong flags)
{
- meson_wdt_start(dev, 1, flags);
+ meson_gxbb_wdt_start(dev, 1, flags);
return 0;
}
+static int meson_gxbb_wdt_probe(struct udevice *dev)
+{
+ struct meson_wdt_priv *priv;
+ struct meson_wdt_data *data;
+
+ fdt_addr_t addr;
+ fdt_size_t size;
+ struct clk w_clk;
+ ulong rate = 0;
+ unsigned int reset_by_soc = 0;
+ int ret;
+
+ assert(dev);
+ priv = dev_get_priv(dev);
+ data = (struct meson_wdt_data *)dev_get_driver_data(dev);
+ addr = devfdt_get_addr_size_index(dev, 0, &size);
+ if (addr == FDT_ADDR_T_NONE)
+ return -EINVAL;
+ priv->regs = (void __iomem *)addr;
+ ret = clk_get_by_name(dev, "wdt-clk", &w_clk);
+ if (ret < 0) {
+ printf("Failed to get wdt-clk.\n");
+ return ret;
+ }
+ rate = clk_get_rate(&w_clk);
+ if (IS_ERR_VALUE(rate)) {
+ printf("Failed to get wdt-clk rate.\n");
+ return ret;
+ }
+
+ reset_by_soc = !(readl(priv->regs + MESON_WDT_CTRL1_REG) &
+ MESON_WDT_RST_SIG_EN);
+
+ writel(((rate / 1000) & MESON_WDT_CTRL_DIV_MASK) |
+ (reset_by_soc << data->rst_shift) |
+ MESON_WDT_CTRL_CLK_EN |
+ MESON_WDT_CTRL_CLKDIV_EN, priv->regs + MESON_WDT_CTRL_REG);
+ meson_gxbb_wdt_set_timeout(dev, DEFAULT_TIMEOUT * 1000);
+ meson_gxbb_wdt_stop(dev);
+
+ return 0;
+}
+
+static struct wdt_ops meson_gxbb_wdt_ops = {
+ .start = meson_gxbb_wdt_start,
+ .stop = meson_gxbb_wdt_stop,
+ .expire_now = meson_gxbb_wdt_expire_now,
+ .reset = meson_gxbb_wdt_reset,
+};
+
+static struct meson_wdt_data meson_gxbb_data = {
+ .rst_shift = 21,
+ .ops = &meson_gxbb_wdt_ops,
+};
+
+static struct meson_wdt_data meson_sc2_data = {
+ .rst_shift = 22,
+ .ops = &meson_gxbb_wdt_ops,
+};
+/**************** a1 **********************/
+void __attribute__((weak)) wdt_send_cmd_to_bl31(uint64_t cmd, uint64_t value)
+{
+
+}
+static int meson_a1_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+ wdt_send_cmd_to_bl31(WDT_INIT, timeout_ms);
+ wdt_send_cmd_to_bl31(WDT_ENABLE, 0);
+ wdt_send_cmd_to_bl31(WDT_PING, 0);
+
+ return 0;
+}
+
+static int meson_a1_wdt_stop(struct udevice *dev)
+{
+ wdt_send_cmd_to_bl31(WDT_DISABLE, 0);
+
+ return 0;
+}
+
+static int meson_a1_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ meson_a1_wdt_start(dev, 1, flags);
+
+ return 0;
+}
+
+static int meson_a1_wdt_reset(struct udevice *dev)
+{
+ wdt_send_cmd_to_bl31(WDT_PING, 0);
+
+ return 0;
+}
+
+static struct wdt_ops meson_a1_ops = {
+ .start = meson_a1_wdt_start,
+ .stop = meson_a1_wdt_stop,
+ .expire_now = meson_a1_wdt_expire_now,
+ .reset = meson_a1_wdt_reset,
+};
+
+static struct meson_wdt_data meson_a1_data = {
+ .ops = &meson_a1_ops,
+};
+
+/************ common code *******************/
static int meson_wdt_ofdata_to_platdata(struct udevice *dev)
{
struct meson_wdt_priv *priv;
@@ -103,48 +224,33 @@
static int meson_wdt_probe(struct udevice *dev)
{
- struct meson_wdt_priv *priv;
- fdt_addr_t addr;
- fdt_size_t size;
- struct clk w_clk;
- unsigned int rate = 0;
- int ret;
+ struct meson_wdt_data* priv;
+ struct driver* dri;
- assert(dev);
- priv = dev_get_priv(dev);
- addr = devfdt_get_addr_size_index(dev, 0, &size);
- if (addr == FDT_ADDR_T_NONE)
- return -EINVAL;
- priv->regs = (void __iomem *)addr;
- ret = clk_get_by_name(dev, "wdt-clk", &w_clk);
- if (ret < 0) {
- printf("Failed to get wdt-clk.\n");
- return ret;
- }
- rate = clk_get_rate(&w_clk);
- if (rate < 0) {
- printf("Failed to get wdt-clk rate.\n");
- return ret;
- }
- writel(((rate / 1000) & MESON_WDT_CTRL_DIV_MASK) |
- MESON_WDT_CTRL_EE_RESET |
- MESON_WDT_CTRL_CLK_EN |
- MESON_WDT_CTRL_CLKDIV_EN, priv->regs + MESON_WDT_CTRL_REG);
- meson_wdt_set_timeout(dev, DEFAULT_TIMEOUT);
- meson_wdt_stop(dev);
+ priv =(struct meson_wdt_data *)dev_get_driver_data(dev);
+ dri = (struct driver*)dev->driver;
+ dri->ops = priv->ops;
+ if (device_is_compatible(dev,"amlogic,meson-gxbb-wdt") ||
+ device_is_compatible(dev,"amlogic,meson-sc2-wdt"))
+ meson_gxbb_wdt_probe(dev);
return 0;
}
-static const struct wdt_ops meson_wdt_ops = {
- .start = meson_wdt_start,
- .reset = meson_wdt_reset,
- .stop = meson_wdt_stop,
- .expire_now = meson_wdt_expire_now,
-};
-
-static const struct udevice_id meson_wdt_ids[] = {
- { .compatible = "amlogic,meson-gxbb-wdt" },
+static const struct udevice_id meson_wdt_ids[] =
+{
+ {
+ .compatible = "amlogic,meson-gxbb-wdt",
+ .data = (ulong)&meson_gxbb_data,
+ },
+ {
+ .compatible = "amlogic,meson-a1-wdt",
+ .data = (ulong)&meson_a1_data,
+ },
+ {
+ .compatible = "amlogic,meson-sc2-wdt",
+ .data = (ulong)&meson_sc2_data,
+ },
{}
};
@@ -152,9 +258,7 @@
.name = "meson_wdt",
.id = UCLASS_WDT,
.of_match = meson_wdt_ids,
- .ops = &meson_wdt_ops,
.probe = meson_wdt_probe,
.priv_auto_alloc_size = sizeof(struct meson_wdt_priv),
.ofdata_to_platdata = meson_wdt_ofdata_to_platdata,
};
-
diff --git a/dts/Kconfig b/dts/Kconfig
index a007ece..8917f42 100644
--- a/dts/Kconfig
+++ b/dts/Kconfig
@@ -300,4 +300,3 @@
calls to the dtc application in order to create the output. In
some cases the system dtc may not support all required features
and the path to a different version should be given here.
-
diff --git a/env/Kconfig b/env/Kconfig
index 867adbe..858011d 100644
--- a/env/Kconfig
+++ b/env/Kconfig
@@ -13,6 +13,7 @@
depends on !ENV_IS_IN_REMOTE
depends on !ENV_IS_IN_SPI_FLASH
depends on !ENV_IS_IN_UBI
+ depends on !ENV_IS_IN_STORAGE
default y
help
Define this if you don't want to or can't have an environment stored
@@ -21,6 +22,24 @@
stored. U-Boot will therefore always start up with a default
environment.
+config ENV_IS_IN_STORAGE
+ bool "Environment is in Amlogic storage device"
+ depends on AML_STORAGE
+ depends on !ENV_IS_IN_EEPROM
+ depends on !ENV_IS_IN_FAT
+ depends on !ENV_IS_IN_FLASH
+ depends on !ENV_IS_IN_MMC
+ depends on !ENV_IS_IN_NAND
+ depends on !ENV_IS_IN_NVRAM
+ depends on !ENV_IS_IN_ONENAND
+ depends on !ENV_IS_IN_REMOTE
+ depends on !ENV_IS_IN_SPI_FLASH
+ depends on !ENV_IS_IN_UBI
+ help
+ Define this if you have a Amlogic virtual storage device which you
+ want to use for the environment.
+ This virtual device maybe a emmc or a nand device, or any others
+
config ENV_IS_IN_EEPROM
bool "Environment in EEPROM"
depends on !CHAIN_OF_TRUST
@@ -615,4 +634,3 @@
endif
endmenu
-
diff --git a/env/Makefile b/env/Makefile
index 90144d6..a6b7cdf 100644
--- a/env/Makefile
+++ b/env/Makefile
@@ -19,10 +19,33 @@
obj-$(CONFIG_ENV_IS_IN_SATA) += sata.o
obj-$(CONFIG_ENV_IS_IN_REMOTE) += remote.o
obj-$(CONFIG_ENV_IS_IN_UBI) += ubi.o
+obj-$(CONFIG_ENV_IS_NOWHERE) += nowhere.o
+obj-$(CONFIG_ENV_IS_IN_STORAGE) += storage.o
+endif
+
+ifdef CONFIG_SPL_BUILD
+obj-$(CONFIG_ENV_IS_IN_FLASH) += flash.o
+# environment
+ifdef CONFIG_TPL_BUILD
+obj-$(CONFIG_TPL_ENV_SUPPORT) += attr.o
+obj-$(CONFIG_TPL_ENV_SUPPORT) += flags.o
+obj-$(CONFIG_TPL_ENV_SUPPORT) += callback.o
else
-obj-$(CONFIG_$(SPL_TPL_)ENV_SUPPORT) += attr.o
-obj-$(CONFIG_$(SPL_TPL_)ENV_SUPPORT) += flags.o
-obj-$(CONFIG_$(SPL_TPL_)ENV_SUPPORT) += callback.o
+obj-$(CONFIG_SPL_ENV_SUPPORT) += attr.o
+obj-$(CONFIG_SPL_ENV_SUPPORT) += flags.o
+obj-$(CONFIG_SPL_ENV_SUPPORT) += callback.o
+endif
+ifneq ($(CONFIG_TPL_ENV_SUPPORT)$(CONFIG_SPL_ENV_SUPPORT),)
+obj-$(CONFIG_ENV_IS_NOWHERE) += nowhere.o
+obj-$(CONFIG_ENV_IS_IN_MMC) += mmc.o
+obj-$(CONFIG_ENV_IS_IN_FAT) += fat.o
+obj-$(CONFIG_ENV_IS_IN_EXT4) += ext4.o
+obj-$(CONFIG_ENV_IS_IN_NAND) += nand.o
+obj-$(CONFIG_ENV_IS_IN_SPI_FLASH) += sf.o
+obj-$(CONFIG_ENV_IS_IN_FLASH) += flash.o
+obj-$(CONFIG_ENV_IS_IN_STORAGE) += storage.o
+endif
+
endif
obj-$(CONFIG_$(SPL_TPL_)ENV_IS_NOWHERE) += nowhere.o
diff --git a/env/env.c b/env/env.c
index 003509d..f794302 100644
--- a/env/env.c
+++ b/env/env.c
@@ -80,6 +80,9 @@
#ifdef CONFIG_ENV_IS_IN_UBI
ENVL_UBI,
#endif
+#ifdef CONFIG_ENV_IS_IN_STORAGE
+ ENVL_STORAGE,
+#endif
#ifdef CONFIG_ENV_IS_NOWHERE
ENVL_NOWHERE,
#endif
@@ -251,7 +254,7 @@
if (!drv->init || !(ret = drv->init()))
env_set_inited(drv->location);
- debug("%s: Environment %s init done (ret=%d)\n", __func__,
+ printf("%s: Environment %s init done (ret=%d)\n", __func__,
drv->name, ret);
}
diff --git a/env/storage.c b/env/storage.c
new file mode 100644
index 0000000..70eff85
--- /dev/null
+++ b/env/storage.c
@@ -0,0 +1,64 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#include <environment.h>
+#include <memalign.h>
+#include <errno.h>
+#include <amlogic/storage.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#ifdef CONFIG_CMD_SAVEENV
+static int env_storage_save(void)
+{
+ if (store_get_type() == BOOT_NONE) {
+ printf("env_storage: must init before save\n");
+ return -ENOENT;
+ }
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
+
+ if (env_export((env_t *)buf)) {
+ printf("env_storage: export failed\n");
+ return -EINVAL;
+ }
+
+ if (store_rsv_write(RSV_ENV, CONFIG_ENV_SIZE, (void *)buf)) {
+ printf("env_storage: write failed\n");
+ return -EIO;
+ }
+
+ return 0;
+}
+#endif /* CONFIG_CMD_SAVEENV */
+
+static int env_storage_load(void)
+{
+ if (store_get_type() == BOOT_NONE) {
+ printf("env_storage: must init before load\n");
+ return -ENOENT;
+ }
+ ALLOC_CACHE_ALIGN_BUFFER(char, buf, CONFIG_ENV_SIZE);
+
+ if (store_rsv_read(RSV_ENV, CONFIG_ENV_SIZE, (void *)buf)) {
+ set_default_env("!env_storage: read failed", 0);
+ return -EIO;
+ }
+ else if (env_import(buf, 1)) {
+ set_default_env("!env_storage: import failed", 0);
+ return -EINVAL;
+ }
+
+ return 0;
+}
+
+
+U_BOOT_ENV_LOCATION(storage) = {
+ .location = ENVL_STORAGE,
+ ENV_NAME("STORAGE")
+ .load = env_storage_load,
+#ifdef CONFIG_CMD_SAVEENV
+ .save = env_save_ptr(env_storage_save),
+#endif
+};
diff --git a/examples/standalone/Makefile b/examples/standalone/Makefile
index f01816f..7f83d49 100644
--- a/examples/standalone/Makefile
+++ b/examples/standalone/Makefile
@@ -43,6 +43,8 @@
# We don't want gcc reordering functions if possible. This ensures that an
# application's entry point will be the first function in the application's
# source file.
+ccflags-y := $(filter-out $(STACK_CFLAGS),$(ccflags-y))
+ccflags-y += $(call cc-option,-fno-stack-protector)
ccflags-y += $(call cc-option,-fno-toplevel-reorder)
LDFLAGS_STANDALONE += -Ttext $(CONFIG_STANDALONE_LOAD_ADDR)
diff --git a/fip/build_bl2.sh b/fip/build_bl2.sh
deleted file mode 100755
index 0537d94..0000000
--- a/fip/build_bl2.sh
+++ /dev/null
@@ -1,19 +0,0 @@
-#!/bin/bash
-
-function build_bl2() {
- echo -n "Build bl2...Please wait..."
- local target="$1/build/$3/release/bl2.bin"
- # $1: src_folder, $2: bin_folder, $3: soc
- cd $1
- export CROSS_COMPILE=${AARCH64_TOOL_CHAIN}
- /bin/bash mk $3
- if [ $? != 0 ]; then
- cd ${MAIN_FOLDER}
- echo "Error: Build bl2 failed... abort"
- exit -1
- fi
- cd ${MAIN_FOLDER}
- cp ${target} $2 -f
- echo "done"
- return
-}
\ No newline at end of file
diff --git a/fip/build_bl30.sh b/fip/build_bl30.sh
deleted file mode 100755
index 319c3b5..0000000
--- a/fip/build_bl30.sh
+++ /dev/null
@@ -1,26 +0,0 @@
-#!/bin/bash
-
-function build_bl30() {
- # $1: src_folder, $2: bin_folder, $3: soc
- # co-work with bl30 build script under bl30.git
- echo -n "Build $3 bl30...Please wait..."
- local target="$1/bl30.bin"
- cd $1
- #export CROSS_COMPILE=${AARCH32_TOOL_CHAIN}
- local soc=$3
- if [ "$soc" == "gxtvbb" ]; then
- soc="gxtvb"
- fi
- #make clean BOARD=$soc &> /dev/null
- #make BOARD=$soc &> /dev/null
- /bin/bash mk $soc
- if [ $? != 0 ]; then
- cd ${MAIN_FOLDER}
- echo "Error: Build bl30 failed... abort"
- exit -1
- fi
- cd ${MAIN_FOLDER}
- cp ${target} $2 -f
- echo "done"
- return
-}
\ No newline at end of file
diff --git a/fip/build_bl31.sh b/fip/build_bl31.sh
deleted file mode 100755
index e8dcede..0000000
--- a/fip/build_bl31.sh
+++ /dev/null
@@ -1,94 +0,0 @@
-#!/bin/bash
-
-
-# these soc use old bl31 code, others use new one
-declare -a BL31_OLD_VER_SOC_LIST=("gxb" "gxtvbb" "gxl" "txl")
-declare BL31_V1_3_SRC_FOLDER="bl31_1.3/src"
-declare BL31_V1_0_SRC_FOLDER="bl31/src"
-declare BL31_V1_3_BIN_FOLDER="bl31_1.3/bin"
-declare BL31_V1_0_BIN_FOLDER="bl31/bin"
-
-
-function build_bl31() {
- echo -n "Build bl31...Please wait... "
- # $1: src_folder, $2: bin_folder, $3: soc
- local target="$1/bl31.bin"
- local target2="$1/bl31.img"
- cd $1
- export CROSS_COMPILE=${AARCH64_TOOL_CHAIN}
- CONFIG_SPD="opteed"
- #CONFIG_SPD="none"
- local soc=$3
- if [ "$soc" == "gxtvbb" ] || [ "$soc" == "gxb" ]; then
- soc="gxbb"
- elif [ "$soc" == "txl" ]; then
- soc="gxl"
- fi
- #make PLAT=${soc} SPD=${CONFIG_SPD} realclean &> /dev/null
- #make PLAT=${soc} SPD=${CONFIG_SPD} V=1 all &> /dev/null
- /bin/bash mk $soc
- if [ $? != 0 ]; then
- cd ${MAIN_FOLDER}
- echo "Error: Build bl31 failed... abort"
- exit -1
- fi
- cd ${MAIN_FOLDER}
- cp ${target} $2 -f
- cp ${target2} $2 -f
- echo "done"
- return
-}
-
-function build_bl31_v1_3() {
- echo -n "Build bl31 v1.3...Please wait... "
- # $1: src_folder, $2: bin_folder, $3: soc
- local target="$1/bl31.bin"
- local target2="$1/bl31.img"
- cd $1
- export CROSS_COMPILE=${AARCH64_TOOL_CHAIN}
- #sh mk $3 &> /dev/null
- local soc=$3
- if [ "$soc" == "txhd" ]; then
- soc="axg"
- fi
- /bin/bash mk $soc
- if [ $? != 0 ]; then
- cd ${MAIN_FOLDER}
- echo "Error: Build bl31 failed... abort"
- exit -1
- fi
- cd ${MAIN_FOLDER}
- cp ${target} $2 -f
- cp ${target2} $2 -f
- echo "done"
- return
-}
-
-# check use which bl31 build script
-function check_bl31_ver() {
- # $1: soc
- # return 1: use bl31 v1.3
- # return 0: use bl31 v1.0
- local -i ver=1
- for soc_list in ${!BL31_OLD_VER_SOC_LIST[@]}; do
- if [ "$1" == "${BL31_OLD_VER_SOC_LIST[${soc_list}]}" ]; then
- ver=0
- fi
- done
- return ${ver}
-}
-
-# some soc need use bl31_v1.3
-function switch_bl31() {
- # $1: soc
- check_bl31_ver $1
- if [ $? != 0 ]; then
- echo "check bl31 ver: use v1.3"
- BLX_SRC_FOLDER[2]=${BL31_V1_3_SRC_FOLDER}
- BLX_BIN_FOLDER[2]=${BL31_V1_3_BIN_FOLDER}
- else
- echo "check bl31 ver: use v1.0"
- BLX_SRC_FOLDER[2]=${BL31_V1_0_SRC_FOLDER}
- BLX_BIN_FOLDER[2]=${BL31_V1_0_BIN_FOLDER}
- fi
-}
\ No newline at end of file
diff --git a/fip/build_bl32.sh b/fip/build_bl32.sh
deleted file mode 100755
index e5eafc0..0000000
--- a/fip/build_bl32.sh
+++ /dev/null
@@ -1,11 +0,0 @@
-#!/bin/bash
-
-function build_bl32() {
- echo -n "Build bl32...Please wait... "
- # $1: src_folder, $2: bin_folder, $3: soc
- cd $1
- # todo
- cd ${MAIN_FOLDER}
- echo "done"
- return
-}
diff --git a/fip/build_bl33.sh b/fip/build_bl33.sh
deleted file mode 100755
index 1d84e1c..0000000
--- a/fip/build_bl33.sh
+++ /dev/null
@@ -1,67 +0,0 @@
-#!/bin/bash
-
-LOCAL_PATH="$(readlink -f $(dirname ${BASH_SOURCE[0]})/)"
-
-
-readonly cross_compile=${LOCAL_PATH}/../../amlogic/linaro/gcc-linaro-7.3.1-2018.05-i686_aarch64-elf/bin/aarch64-elf-
-#readonly cross_compile=${LOCAL_PATH}/../../amlogic/linaro/gcc-linaro-aarch64-none-elf-4.8-2013.11_linux/bin/aarch64-none-elf-
-readonly cross_compile_t32=${LOCAL_PATH}/../../amlogic/linaro/gcc-arm-none-eabi-6-2017-q2-update/bin/arm-none-eabi-
-
-function pre_build_uboot() {
- cd ${UBOOT_SRC_FOLDER}
- echo -n "Compile config: "
- echo "$1"
- make distclean # &> /dev/null
- make CROSS_COMPILE=$cross_compile CROSS_COMPILE_T32=$cross_compile_t32 $1'_config' # &> /dev/null
- if [ $? != 0 ]
- then
- echo "Pre-build failed! exit!"
- cd ${MAIN_FOLDER}
- exit -1
- fi
- cd ${MAIN_FOLDER}
-}
-
-function build_uboot() {
- echo "Build uboot...Please Wait..."
- mkdir -p ${FIP_BUILD_FOLDER}
- cd ${UBOOT_SRC_FOLDER}
- # make T=1 to use latest git commit time as build timestamp.
- make BOARD_NAME=$2 T=1 CROSS_COMPILE=$cross_compile CROSS_COMPILE_T32=$cross_compile_t32 BL33_DEBUG=$1 -j # &> /dev/null
- ret=$?
- cd ${MAIN_FOLDER}
- if [ 0 -ne $ret ]; then
- echo "Error: U-boot build failed... abort"
- exit -1
- fi
- find ./ -name u-boot.bin
- echo "find u-boot.bin done"
-}
-
-function uboot_config_list() {
- folder_board="${UBOOT_SRC_FOLDER}/board/amlogic"
- echo " ******Amlogic Configs******"
- for file in ${folder_board}/*; do
- temp_file=`basename $file`
- #echo "$temp_file"
- if [ -d ${folder_board}/${temp_file} ] && [ "$temp_file" != "defconfigs" ] && [ "$temp_file" != "configs" ];then
- echo " ${temp_file}"
- fi
- done
-
- customer_folder="${UBOOT_SRC_FOLDER}/customer/board"
- if [ -e ${customer_folder} ]; then
- echo " ******Customer Configs******"
- for file in ${customer_folder}/*; do
- temp_file=`basename $file`
- if [ -d ${customer_folder}/${temp_file} ] && [ "$temp_file" != "defconfigs" ] && [ "$temp_file" != "configs" ];then
- echo " ${temp_file}"
- fi
- done
- fi
- echo " ***************************"
-}
-
-function copy_bl33() {
- cp ${UBOOT_SRC_FOLDER}/u-boot.bin ${FIP_BUILD_FOLDER}bl33.bin -f
-}
diff --git a/fip/build_bl40.sh b/fip/build_bl40.sh
deleted file mode 100755
index 5022c19..0000000
--- a/fip/build_bl40.sh
+++ /dev/null
@@ -1,11 +0,0 @@
-#!/bin/bash
-
-function build_bl40() {
- echo -n "Build bl40...Please wait... "
- # $1: src_folder, $2: bin_folder, $3: soc
- cd $1
- # todo
- cd ${MAIN_FOLDER}
- echo "done"
- return
-}
diff --git a/fip/check_compile.sh b/fip/check_compile.sh
deleted file mode 100755
index f66e22c..0000000
--- a/fip/check_compile.sh
+++ /dev/null
@@ -1,189 +0,0 @@
-#!/bin/bash
-
-#------------IMPORTANT------------#
-#--RUN THIS SCRIPT BEFOR COMMIT---#
-#---------------------------------#
-
-# Author: xiaobo.gu@amlogic.com
-# Init version: 20160329
-# Update for bootloader.repo: 2017.01.01
-
-#usage:
-#
-#./check_compile.sh -check amlogic board configs
-#./check_compile.sh cus -check customer board configs
-#./check_compile.sh all -check both amlogic and customer boards
-
-function check_compile() {
- # $1: filter
- folder_board="bl33/board/amlogic"
- customer_folder="bl33/customer/board"
-
- echo "************** Amlogic Compile Check Tool **************"
-
- # filters define:
- # cus: all customer board
- # all: all boards
- # other:
- # gxb: all gxbaby board
- # gxtvbb: all gxtvbb board
- # skt: all socket board
- # p200: p200 board
- # etc.....
- declare filter="$1"
-
- # ARRAY_CFG store config names
- declare -a ARRAY_CFG
- declare -a ARRAY_CFG_C
- # TOTAL_CFG store config total num
- declare -i TOTAL_CFG
- declare -i TOTAL_CFG_C
-
- # if filter!=cus, then include amlogic configs
- # get all configs name from board folder
- if [ "$1" != "cus" ]
- then
- filter=$1
- for file in ${folder_board}/*; do
- temp_file=`basename $file`
- #echo "$temp_file"
- if [ -d ${folder_board}/${temp_file} ] && [ "$temp_file" != "defconfigs" ] && [ "$temp_file" != "configs" ];then
- #echo " \c"
- #echo $temp_file
- ARRAY_CFG[$TOTAL_CFG]=$temp_file
- TOTAL_CFG=$TOTAL_CFG+1
- fi
- done
- fi
-
- # if filter==all || filter==cus, then include customer configs
- # get all customer configs name from customer board folder
- if [ "$1" == "cus" ] || [ "$1" == "all" ]
- then
- filter=""
- if [ -e ${customer_folder} ];then
- for file in ${customer_folder}/*; do
- temp_file=`basename $file`
- if [ -d ${customer_folder}/${temp_file} ] && [ "$temp_file" != "defconfigs" ] && [ "$temp_file" != "configs" ];then
- #echo " \c"
- #echo $temp_file
- ARRAY_CFG_C[$TOTAL_CFG_C]=$temp_file
- TOTAL_CFG_C=$TOTAL_CFG_C+1
- fi
- done
- fi
- fi
-
- echo "************************ START *************************"
-
- # compile check start
- # RESULT store compile result
- declare RESULT=""
- declare -i LOOP_NUM=0
- # counter variables
- declare -i PASS_COUNTER=0
- declare -i FAIL_COUNTER=0
-
- # print bar and alignment
- declare -i BAR_TOTAL=30
- declare -i BAR_LOOP
-
- RESULT=$RESULT"########### Compile Check Result ###########\n"
-
- if [ "$1" != "cus" ]
- then
- RESULT=$RESULT"--------------------------------------------\n"
- RESULT=$RESULT"############## Amlogic Boards ##############\n"
- # loop all cfgs
- for cfg in ${ARRAY_CFG[@]}
- do
- # find filter in config name
- if [[ $(echo $cfg | grep "${filter}") == "" ]]
- then
- # skip !filter configs
- continue
- fi
- LOOP_NUM=$LOOP_NUM+1
- RESULT=$RESULT' '
- # print '0' charactors for alignment
- BAR_LOOP=3-`expr length $LOOP_NUM`
- if [ "$BAR_LOOP" -gt "0" ]
- then
- for tmp in `seq $BAR_LOOP`;do RESULT=$RESULT'0';done
- fi
- RESULT=$RESULT$LOOP_NUM' '
- RESULT=$RESULT$cfg' '
- # print '-' charactors for alignment
- BAR_LOOP=BAR_TOTAL-`expr length $cfg`
- if [ "$BAR_LOOP" -gt "0" ]
- then
- for tmp in `seq $BAR_LOOP`;do RESULT=$RESULT'-';done
- fi
- BUILD_COUNTER=3
- BUILD_RESULT=0
- while [ "${BUILD_COUNTER}" -gt "0" ]; do
- BUILD_COUNTER=$((BUILD_COUNTER - 1))
- #make distclean
- #make $cfg'_defconfig'
- #make -j
- fip/mk_script.sh $cfg
- # check last 'make -j' result
- if [ $? != 0 ]; then
- BUILD_RESULT=$((BUILD_RESULT + 1))
- else
- BUILD_RESULT=0
- BUILD_COUNTER=0
- fi
- done
- # check compile result
- if [ ${BUILD_RESULT} != 0 ]; then
- RESULT=$RESULT'- failed\n'
- FAIL_COUNTER=$FAIL_COUNTER+1
- else
- RESULT=$RESULT'- pass\n'
- PASS_COUNTER=$PASS_COUNTER+1
- fi
- # print result
- echo -e $RESULT
- #echo $cfg
- done
- fi
-
- # check customer configs
- if [ "$1" == "cus" ] || [ "$1" == "all" ]
- then
- RESULT=$RESULT"--------------------------------------------\n"
- RESULT=$RESULT"############## Customer Boards #############\n"
- for cfg in ${ARRAY_CFG_C[@]}
- do
- LOOP_NUM=$LOOP_NUM+1
- RESULT=$RESULT' '
- BAR_LOOP=3-`expr length $LOOP_NUM`
- if [ "$BAR_LOOP" -gt "0" ]
- then
- for tmp in `seq $BAR_LOOP`;do RESULT=$RESULT'0';done
- fi
- RESULT=$RESULT$LOOP_NUM' '
- RESULT=$RESULT$cfg' '
- BAR_LOOP=BAR_TOTAL-`expr length $cfg`
- if [ "$BAR_LOOP" -gt "0" ]
- then
- for tmp in `seq $BAR_LOOP`;do RESULT=$RESULT'-';done
- fi
- make distclean
- make $cfg'_defconfig'
- make -j
- if [ $? != 0 ]
- then
- RESULT=$RESULT'- failed\n'
- FAIL_COUNTER=$FAIL_COUNTER+1
- else
- RESULT=$RESULT'- pass\n'
- PASS_COUNTER=$PASS_COUNTER+1
- fi
- echo -e $RESULT
- done
- fi
-
- echo -e "#################### END ###################\n"
-}
diff --git a/fip/fip_create b/fip/fip_create
deleted file mode 100755
index 3d3eada..0000000
--- a/fip/fip_create
+++ /dev/null
Binary files differ
diff --git a/fip/g12a/aml_ddr.fw b/fip/g12a/aml_ddr.fw
deleted file mode 100644
index 4904b5a..0000000
--- a/fip/g12a/aml_ddr.fw
+++ /dev/null
Binary files differ
diff --git a/fip/g12a/aml_encrypt_g12a b/fip/g12a/aml_encrypt_g12a
deleted file mode 100755
index 85fb7fe..0000000
--- a/fip/g12a/aml_encrypt_g12a
+++ /dev/null
Binary files differ
diff --git a/fip/g12a/bl31.img b/fip/g12a/bl31.img
deleted file mode 100644
index 282d92f..0000000
--- a/fip/g12a/bl31.img
+++ /dev/null
Binary files differ
diff --git a/fip/g12a/bl32.img b/fip/g12a/bl32.img
deleted file mode 100644
index 56fddfd..0000000
--- a/fip/g12a/bl32.img
+++ /dev/null
Binary files differ
diff --git a/fip/g12a/build.sh b/fip/g12a/build.sh
deleted file mode 100644
index 0fbbb9c..0000000
--- a/fip/g12a/build.sh
+++ /dev/null
@@ -1,192 +0,0 @@
-#!/bin/bash
-
-# include uboot pre-build macros
-#declare CONFIG_FILE=("${buildtree}/.config")
-#declare AUTOCFG_FILE=("${buildtree}/include/autoconf.mk")
-
-function init_vari() {
- #source ${CONFIG_FILE} &> /dev/null # ignore warning/error
- #source ${AUTOCFG_FILE} &> /dev/null # ignore warning/error
-
- AML_BL2_NAME="bl2.bin"
- AML_KEY_BLOB_NANE="aml-user-key.sig"
-
- if [ "y" == "${CONFIG_AML_SECURE_BOOT_V3}" ]; then
- V3_PROCESS_FLAG="--level v3"
- fi
-
- if [ "y" == "${CONFIG_AML_BL33_COMPRESS_ENABLE}" ]; then
- BL33_COMPRESS_FLAG="--compress lz4"
- fi
-
- if [ "y" == "${CONFIG_FIP_IMG_SUPPORT}" ]; then
- BL3X_SUFFIX="img"
- fi
-}
-
-function fix_blx() {
- #bl2 file size 41K, bl21 file size 3K (file size not equal runtime size)
- #total 44K
- #after encrypt process, bl2 add 4K header, cut off 4K tail
-
- #bl2 file size 56K, acs file size 4K
- #total 60K
- #after encrypt process, bl2 add 4K header, cut off 4K tail
-
- #bl30 limit 41K
- #bl301 limit 12K
-
- #bl2 limit 56K
- #acs limit 4K, but encrypt tool need 64K bl2.bin, so fix to 8192byte.
-
- declare blx_bin_limit=0
- declare blx01_bin_limit=0
- declare -i blx_size=0
- declare -i zero_size=0
-
- #$7:name flag
- if [ "$7" = "bl30" ]; then
- blx_bin_limit=40960 # PD#132613 2016-10-31 update, 41984->40960
- blx01_bin_limit=13312 # PD#132613 2016-10-31 update, 12288->13312
- elif [ "$7" = "bl2" ]; then
- blx_bin_limit=57344
- blx01_bin_limit=4096
- else
- echo "blx_fix name flag not supported!"
- exit 1
- fi
-
- # blx_size: blx.bin size, zero_size: fill with zeros
- blx_size=`du -b $1 | awk '{print int($1)}'`
- zero_size=$blx_bin_limit-$blx_size
- dd if=/dev/zero of=$2 bs=1 count=$zero_size
- cat $1 $2 > $3
- rm $2
-
- blx_size=`du -b $4 | awk '{print int($1)}'`
- zero_size=$blx01_bin_limit-$blx_size
- dd if=/dev/zero of=$2 bs=1 count=$zero_size
- cat $4 $2 > $5
-
- cat $3 $5 > $6
-
- rm $2
-}
-
-function cleanup() {
- rm -f ${BUILD_PATH}/bl*.enc ${BUILD_PATH}/bl2*.sig
- rm -f ${BUILD_PATH}/boot_new.bin
-}
-
-function encrypt_step() {
- dbg "encrypt: $@"
- local ret=0
- ./${FIP_FOLDER}${CUR_SOC}/aml_encrypt_${CUR_SOC} $@
- ret=$?
- if [ 0 != $ret ]; then
- echo "Err! aml_encrypt_${CUR_SOC} return $ret"
- exit $ret
- fi
-}
-
-function encrypt() {
- #u-boot.bin generate
- if [ "y" == "${CONFIG_AML_SECURE_BOOT_V3}" ]; then
- encrypt_step --bl30sig --input ${BUILD_PATH}/bl30_new.bin --output ${BUILD_PATH}/bl30_new.bin.g12.enc ${V3_PROCESS_FLAG}
- encrypt_step --bl3sig --input ${BUILD_PATH}/bl30_new.bin.g12.enc --output ${BUILD_PATH}/bl30_new.bin.enc ${V3_PROCESS_FLAG} --type bl30
- encrypt_step --bl3sig --input ${BUILD_PATH}/bl31.${BL3X_SUFFIX} --output ${BUILD_PATH}/bl31.${BL3X_SUFFIX}.enc ${V3_PROCESS_FLAG} --type bl31
- if [ "${FIP_BL32}" == "${BUILD_PATH}/bl32.${BL3X_SUFFIX}" ]; then
- encrypt_step --bl3sig --input ${BUILD_PATH}/bl32.${BL3X_SUFFIX} --output ${BUILD_PATH}/bl32.${BL3X_SUFFIX}.enc ${V3_PROCESS_FLAG} --type bl32
- fi
- encrypt_step --bl3sig --input ${BUILD_PATH}/bl33.bin ${BL33_COMPRESS_FLAG} --output ${BUILD_PATH}/bl33.bin.enc ${V3_PROCESS_FLAG} --type bl33
- fi
-
- encrypt_step --bl2sig --input ${BUILD_PATH}/bl2_new.bin --output ${BUILD_PATH}/bl2.n.bin.sig
-
- encrypt_step --bootmk --output ${BUILD_PATH}/u-boot.bin \
- --bl2 ${BUILD_PATH}/bl2.n.bin.sig --bl30 ${BUILD_PATH}/bl30_new.bin.enc \
- --bl31 ${BUILD_PATH}/bl31.${BL3X_SUFFIX}.enc ${FIP_BL32_PROCESS} --bl33 ${BUILD_PATH}/bl33.bin.enc ${V3_PROCESS_FLAG} \
- --ddrfw1 ./${FIP_FOLDER}${CUR_SOC}/ddr4_1d.fw --ddrfw2 ./${FIP_FOLDER}${CUR_SOC}/ddr4_2d.fw \
- --ddrfw3 ./${FIP_FOLDER}${CUR_SOC}/ddr3_1d.fw --ddrfw4 ./${FIP_FOLDER}${CUR_SOC}/piei.fw \
- --ddrfw5 ./${FIP_FOLDER}${CUR_SOC}/lpddr4_1d.fw --ddrfw6 ./${FIP_FOLDER}${CUR_SOC}/lpddr4_2d.fw
-
- if [ "y" == "${CONFIG_AML_CRYPTO_UBOOT}" ]; then
- encrypt_step --efsgen --amluserkey ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/${AML_KEY_BLOB_NANE} \
- --output ${BUILD_PATH}/u-boot.bin.encrypt.efuse ${V3_PROCESS_FLAG}
- encrypt_step --bootsig --input ${BUILD_PATH}/u-boot.bin --amluserkey ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/${AML_KEY_BLOB_NANE} \
- --aeskey enable --output ${BUILD_PATH}/u-boot.bin.encrypt ${V3_PROCESS_FLAG}
- fi
-
- if [ "y" == "${CONFIG_AML_CRYPTO_IMG}" ]; then
- encrypt_step --imgsig --input ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/boot.img --amluserkey ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/${AML_KEY_BLOB_NANE} --output ${BUILD_PATH}/boot.img.encrypt
- fi
-
- return
-}
-
-function build_fip() {
- fix_blx \
- ${BUILD_PATH}/bl30.bin \
- ${BUILD_PATH}/zero_tmp \
- ${BUILD_PATH}/bl30_zero.bin \
- ${BUILD_PATH}/bl301.bin \
- ${BUILD_PATH}/bl301_zero.bin \
- ${BUILD_PATH}/bl30_new.bin \
- bl30
-
- # acs_tool process ddr timing and configurable parameters
- #python ${FIP_FOLDER}/acs_tool.pyc ${BUILD_PATH}/${AML_BL2_NAME} ${BUILD_PATH}/bl2_acs.bin ${BUILD_PATH}/acs.bin 0
-
- # fix bl2/bl21
- fix_blx \
- ${BUILD_PATH}/bl2.bin \
- ${BUILD_PATH}/zero_tmp \
- ${BUILD_PATH}/bl2_zero.bin \
- ${BUILD_PATH}/acs.bin \
- ${BUILD_PATH}/bl21_zero.bin \
- ${BUILD_PATH}/bl2_new.bin \
- bl2
-
- # v2: bl30/bl301 merged since 2016.03.22
- FIP_ARGS="--bl30 ${BUILD_PATH}/bl30_new.bin --bl31 ${BUILD_PATH}/bl31.${BL3X_SUFFIX}"
-
- if [ "y" == "${CONFIG_NEED_BL32}" ]; then
- FIP_BL32="`find ${BUILD_PATH} -name "bl32.${BL3X_SUFFIX}"`"
- if [ "${FIP_BL32}" == "${BUILD_PATH}/bl32.${BL3X_SUFFIX}" ]; then
- FIP_ARGS="${FIP_ARGS}"" --bl32 ${BUILD_PATH}/bl32.${BL3X_SUFFIX}"
- FIP_BL32_PROCESS=" --bl32 ${BUILD_PATH}/bl32.${BL3X_SUFFIX}.enc"
- fi
- fi
- FIP_ARGS="${FIP_ARGS}"" --bl33 ${BUILD_PATH}/bl33.bin"
-
- # create fip.bin
- ./${FIP_FOLDER}/fip_create ${FIP_ARGS} ${BUILD_PATH}/fip.bin
- ./${FIP_FOLDER}/fip_create --dump ${BUILD_PATH}/fip.bin
-
- # build final bootloader
- cat ${BUILD_PATH}/bl2_new.bin ${BUILD_PATH}/fip.bin > ${BUILD_PATH}/boot_new.bin
-
- return
-}
-
-function copy_other_soc() {
- cp ${UBOOT_SRC_FOLDER}/scp_task/bl301.bin ${BUILD_PATH} -f
- #useless #cp ${UBOOT_SRC_FOLDER}/build/${BOARD_DIR}/firmware/bl21.bin ${BUILD_PATH} -f
- cp ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/firmware/acs.bin ${BUILD_PATH} -f
- # todo. cp bl40?
-}
-
-function package() {
- # BUILD_PATH without "/"
- x=$((${#BUILD_PATH}-1))
- if [ "\\" == "${BUILD_PATH:$x:1}" ] || [ "/" == "${BUILD_PATH:$x:1}" ]; then
- BUILD_PATH=${BUILD_PATH:0:$x}
- fi
-
- init_vari $@
- build_fip $@
- encrypt $@
- #copy_file
- #cleanup
- echo "Bootloader build done!"
-}
diff --git a/fip/g12a/ddr3_1d.fw b/fip/g12a/ddr3_1d.fw
deleted file mode 100644
index 16586ff..0000000
--- a/fip/g12a/ddr3_1d.fw
+++ /dev/null
Binary files differ
diff --git a/fip/g12a/ddr4_1d.fw b/fip/g12a/ddr4_1d.fw
deleted file mode 100644
index 2a9db98..0000000
--- a/fip/g12a/ddr4_1d.fw
+++ /dev/null
Binary files differ
diff --git a/fip/g12a/ddr4_2d.fw b/fip/g12a/ddr4_2d.fw
deleted file mode 100644
index f70d3a3..0000000
--- a/fip/g12a/ddr4_2d.fw
+++ /dev/null
Binary files differ
diff --git a/fip/g12a/diag_lpddr4.fw b/fip/g12a/diag_lpddr4.fw
deleted file mode 100755
index f12fa27..0000000
--- a/fip/g12a/diag_lpddr4.fw
+++ /dev/null
Binary files differ
diff --git a/fip/g12a/lpddr4_1d.fw b/fip/g12a/lpddr4_1d.fw
deleted file mode 100644
index 6c98b7a..0000000
--- a/fip/g12a/lpddr4_1d.fw
+++ /dev/null
Binary files differ
diff --git a/fip/g12a/lpddr4_2d.fw b/fip/g12a/lpddr4_2d.fw
deleted file mode 100644
index 5f01b35..0000000
--- a/fip/g12a/lpddr4_2d.fw
+++ /dev/null
Binary files differ
diff --git a/fip/g12a/piei.fw b/fip/g12a/piei.fw
deleted file mode 100644
index 94bff08..0000000
--- a/fip/g12a/piei.fw
+++ /dev/null
Binary files differ
diff --git a/fip/g12a/variable_soc.sh b/fip/g12a/variable_soc.sh
deleted file mode 100755
index 75d60a2..0000000
--- a/fip/g12a/variable_soc.sh
+++ /dev/null
@@ -1,31 +0,0 @@
-#!/bin/bash
-
-# static
-declare -a BLX_NAME=("bl2" "bl30" "bl31" "bl32")
-
-declare -a BLX_SRC_FOLDER=("bl2/src" "bl30/src" "bl31/src" "bl32/src" "bl33")
-declare -a BLX_BIN_FOLDER=("bl2/bin" "bl30/bin" "bl31/bin" "bl32/bin")
-declare -a BLX_BIN_NAME=("bl2.bin" "bl30.bin" "bl31.bin" "bl32.bin")
-declare -a BLX_IMG_NAME=("NULL" "NULL" "bl31.img" "bl32.img")
-declare -a BLX_NEEDFUL=("true" "true" "true" "false")
-
-# blx priority. null: default, source: src code, others: bin path
-declare -a BIN_PATH=("null" "null" "null" "null")
-
-# variables
-declare -a CUR_REV # current version of each blx
-declare -a BLX_READY=("false", "false", "false", "false") # blx build/get flag
-
-# package variables
-declare BL33_COMPRESS_FLAG=""
-declare BL3X_SUFFIX="bin"
-declare V3_PROCESS_FLAG=""
-declare FIP_ARGS=""
-declare AML_BL2_NAME=""
-declare AML_KEY_BLOB_NANE=""
-declare FIP_BL32_PROCESS=""
-
-BUILD_PATH=${FIP_BUILD_FOLDER}
-
-CONFIG_DDR_FW=0
-DDR_FW_NAME="aml_ddr.fw"
\ No newline at end of file
diff --git a/fip/g12b/aml_ddr.fw b/fip/g12b/aml_ddr.fw
deleted file mode 100644
index 77a5c61..0000000
--- a/fip/g12b/aml_ddr.fw
+++ /dev/null
Binary files differ
diff --git a/fip/g12b/aml_encrypt_g12b b/fip/g12b/aml_encrypt_g12b
deleted file mode 100755
index 6ac09f0..0000000
--- a/fip/g12b/aml_encrypt_g12b
+++ /dev/null
Binary files differ
diff --git a/fip/g12b/bl2.bin b/fip/g12b/bl2.bin
deleted file mode 100755
index 1287bca..0000000
--- a/fip/g12b/bl2.bin
+++ /dev/null
Binary files differ
diff --git a/fip/g12b/bl30.bin b/fip/g12b/bl30.bin
deleted file mode 100755
index 6203977..0000000
--- a/fip/g12b/bl30.bin
+++ /dev/null
Binary files differ
diff --git a/fip/g12b/bl31.img b/fip/g12b/bl31.img
deleted file mode 100644
index bd2b0a4..0000000
--- a/fip/g12b/bl31.img
+++ /dev/null
Binary files differ
diff --git a/fip/g12b/bl32.img b/fip/g12b/bl32.img
deleted file mode 100644
index 36f7385..0000000
--- a/fip/g12b/bl32.img
+++ /dev/null
Binary files differ
diff --git a/fip/g12b/build.sh b/fip/g12b/build.sh
deleted file mode 100755
index bea3c10..0000000
--- a/fip/g12b/build.sh
+++ /dev/null
@@ -1,206 +0,0 @@
-#!/bin/bash
-
-# include uboot pre-build macros
-#declare CONFIG_FILE=("${buildtree}/.config")
-#declare AUTOCFG_FILE=("${buildtree}/include/autoconf.mk")
-
-function init_vari() {
- #source ${CONFIG_FILE} &> /dev/null # ignore warning/error
- #source ${AUTOCFG_FILE} &> /dev/null # ignore warning/error
-
- AML_BL2_NAME="bl2.bin"
- AML_KEY_BLOB_NANE="aml-user-key.sig"
-
- if [ "y" == "${CONFIG_AML_SECURE_BOOT_V3}" ]; then
- V3_PROCESS_FLAG="--level v3"
- fi
-
- if [ "y" == "${CONFIG_AML_BL33_COMPRESS_ENABLE}" ]; then
- BL33_COMPRESS_FLAG="--compress lz4"
- fi
-
- if [ "y" == "${CONFIG_FIP_IMG_SUPPORT}" ]; then
- BL3X_SUFFIX="img"
- fi
-}
-
-function fix_blx() {
- #bl2 file size 41K, bl21 file size 3K (file size not equal runtime size)
- #total 44K
- #after encrypt process, bl2 add 4K header, cut off 4K tail
-
- #bl2 file size 56K, acs file size 4K
- #total 60K
- #after encrypt process, bl2 add 4K header, cut off 4K tail
-
- #bl30 limit 41K
- #bl301 limit 12K
-
- #bl2 limit 56K
- #acs limit 4K, but encrypt tool need 64K bl2.bin, so fix to 8192byte.
-
- declare blx_bin_limit=0
- declare blx01_bin_limit=0
- declare -i blx_size=0
- declare -i zero_size=0
-
- #$7:name flag
- if [ "$7" = "bl30" ]; then
- blx_bin_limit=40960 # PD#132613 2016-10-31 update, 41984->40960
- blx01_bin_limit=13312 # PD#132613 2016-10-31 update, 12288->13312
- elif [ "$7" = "bl2" ]; then
- blx_bin_limit=57344
- blx01_bin_limit=4096
- else
- echo "blx_fix name flag not supported!"
- exit 1
- fi
-
- # blx_size: blx.bin size, zero_size: fill with zeros
- blx_size=`du -b $1 | awk '{print int($1)}'`
- zero_size=$blx_bin_limit-$blx_size
- dd if=/dev/zero of=$2 bs=1 count=$zero_size
- cat $1 $2 > $3
- rm $2
-
- blx_size=`du -b $4 | awk '{print int($1)}'`
- zero_size=$blx01_bin_limit-$blx_size
- dd if=/dev/zero of=$2 bs=1 count=$zero_size
- cat $4 $2 > $5
-
- cat $3 $5 > $6
-
- rm $2
-}
-
-function cleanup() {
- rm -f ${BUILD_PATH}/bl*.enc ${BUILD_PATH}/bl2*.sig
- rm -f ${BUILD_PATH}/boot_new.bin
-}
-
-function encrypt_step() {
- dbg "encrypt: $@"
- local ret=0
- ./${FIP_FOLDER}${CUR_SOC}/aml_encrypt_${CUR_SOC} $@
- ret=$?
- if [ 0 != $ret ]; then
- echo "Err! aml_encrypt_${CUR_SOC} return $ret"
- exit $ret
- fi
-}
-
-function encrypt() {
- #u-boot.bin generate
- if [ "y" == "${CONFIG_AML_SECURE_BOOT_V3}" ]; then
- encrypt_step --bl30sig --input ${BUILD_PATH}/bl30_new.bin --output ${BUILD_PATH}/bl30_new.bin.g12.enc ${V3_PROCESS_FLAG}
- encrypt_step --bl3sig --input ${BUILD_PATH}/bl30_new.bin.g12.enc --output ${BUILD_PATH}/bl30_new.bin.enc ${V3_PROCESS_FLAG} --type bl30
- encrypt_step --bl3sig --input ${BUILD_PATH}/bl31.${BL3X_SUFFIX} --output ${BUILD_PATH}/bl31.${BL3X_SUFFIX}.enc ${V3_PROCESS_FLAG} --type bl31
- if [ "${FIP_BL32}" == "${BUILD_PATH}/bl32.${BL3X_SUFFIX}" ]; then
- encrypt_step --bl3sig --input ${BUILD_PATH}/bl32.${BL3X_SUFFIX} --output ${BUILD_PATH}/bl32.${BL3X_SUFFIX}.enc ${V3_PROCESS_FLAG} --type bl32
- fi
- encrypt_step --bl3sig --input ${BUILD_PATH}/bl33.bin ${BL33_COMPRESS_FLAG} --output ${BUILD_PATH}/bl33.bin.enc ${V3_PROCESS_FLAG} --type bl33
- fi
-
- encrypt_step --bl2sig --input ${BUILD_PATH}/bl2_new.bin --output ${BUILD_PATH}/bl2.n.bin.sig
-
- encrypt_step --bootmk --output ${BUILD_PATH}/u-boot.bin \
- --bl2 ${BUILD_PATH}/bl2.n.bin.sig --bl30 ${BUILD_PATH}/bl30_new.bin.enc \
- --bl31 ${BUILD_PATH}/bl31.${BL3X_SUFFIX}.enc ${FIP_BL32_PROCESS} --bl33 ${BUILD_PATH}/bl33.bin.enc ${V3_PROCESS_FLAG} \
- --ddrfw1 ./${FIP_FOLDER}${CUR_SOC}/ddr4_1d.fw --ddrfw2 ./${FIP_FOLDER}${CUR_SOC}/ddr4_2d.fw \
- --ddrfw3 ./${FIP_FOLDER}${CUR_SOC}/ddr3_1d.fw --ddrfw4 ./${FIP_FOLDER}${CUR_SOC}/piei.fw \
- --ddrfw5 ./${FIP_FOLDER}${CUR_SOC}/lpddr4_1d.fw --ddrfw6 ./${FIP_FOLDER}${CUR_SOC}/lpddr4_2d.fw \
- --ddrfw7 ./${FIP_FOLDER}${CUR_SOC}/diag_lpddr4.fw --ddrfw8 ./${FIP_FOLDER}${CUR_SOC}/${DDR_FW_NAME}
-
- if [ "y" == "${CONFIG_AML_CRYPTO_UBOOT}" ]; then
- encrypt_step --efsgen --amluserkey ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/${AML_KEY_BLOB_NANE} \
- --output ${BUILD_PATH}/u-boot.bin.encrypt.efuse ${V3_PROCESS_FLAG}
- encrypt_step --bootsig --input ${BUILD_PATH}/u-boot.bin --amluserkey ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/${AML_KEY_BLOB_NANE} \
- --aeskey enable --output ${BUILD_PATH}/u-boot.bin.encrypt ${V3_PROCESS_FLAG}
- fi
-
- if [ "y" == "${CONFIG_AML_CRYPTO_IMG}" ]; then
- encrypt_step --imgsig --input ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/boot.img --amluserkey ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/${AML_KEY_BLOB_NANE} --output ${BUILD_PATH}/boot.img.encrypt
- fi
-
- return
-}
-
-function build_fip() {
- fix_blx \
- ${BUILD_PATH}/bl30.bin \
- ${BUILD_PATH}/zero_tmp \
- ${BUILD_PATH}/bl30_zero.bin \
- ${BUILD_PATH}/bl301.bin \
- ${BUILD_PATH}/bl301_zero.bin \
- ${BUILD_PATH}/bl30_new.bin \
- bl30
-
- # acs_tool process ddr timing and configurable parameters
- #python ${FIP_FOLDER}/acs_tool.pyc ${BUILD_PATH}/${AML_BL2_NAME} ${BUILD_PATH}/bl2_acs.bin ${BUILD_PATH}/acs.bin 0
-
- # fix bl2/bl21
- fix_blx \
- ${BUILD_PATH}/bl2.bin \
- ${BUILD_PATH}/zero_tmp \
- ${BUILD_PATH}/bl2_zero.bin \
- ${BUILD_PATH}/acs.bin \
- ${BUILD_PATH}/bl21_zero.bin \
- ${BUILD_PATH}/bl2_new.bin \
- bl2
-
- # v2: bl30/bl301 merged since 2016.03.22
- FIP_ARGS="--bl30 ${BUILD_PATH}/bl30_new.bin --bl31 ${BUILD_PATH}/bl31.${BL3X_SUFFIX}"
-
- if [ "y" == "${CONFIG_NEED_BL32}" ]; then
- FIP_BL32="`find ${BUILD_PATH} -name "bl32.${BL3X_SUFFIX}"`"
- if [ "${FIP_BL32}" == "${BUILD_PATH}/bl32.${BL3X_SUFFIX}" ]; then
- FIP_ARGS="${FIP_ARGS}"" --bl32 ${BUILD_PATH}/bl32.${BL3X_SUFFIX}"
- FIP_BL32_PROCESS=" --bl32 ${BUILD_PATH}/bl32.${BL3X_SUFFIX}.enc"
- fi
- fi
- mv -f ${BUILD_PATH}/bl33.bin ${BUILD_PATH}/bl33.bin.org
- ${BUILD_PATH}/../g12b/aml_encrypt_g12b --bl3sig --input ${BUILD_PATH}/bl33.bin.org --output ${BUILD_PATH}/bl33.bin.org.lz4 --compress lz4-fix --level v3 --type bl33
- dd if=${BUILD_PATH}/bl33.bin.org.lz4 of=${BUILD_PATH}/bl33.bin bs=1 skip=1824 >& /dev/null
-
- FIP_ARGS="${FIP_ARGS}"" --bl33 ${BUILD_PATH}/bl33.bin"
-
- # create fip.bin
- ./${FIP_FOLDER}/fip_create ${FIP_ARGS} ${BUILD_PATH}/fip.bin
- ./${FIP_FOLDER}/fip_create --dump ${BUILD_PATH}/fip.bin
-
- # build final bootloader
- cat ${BUILD_PATH}/bl2_new.bin ${BUILD_PATH}/fip.bin > ${BUILD_PATH}/boot_new.bin
-
- return
-}
-
-function copy_other_soc() {
- cp ${UBOOT_SRC_FOLDER}/scp_task/bl301.bin ${BUILD_PATH} -f
- #useless #cp ${UBOOT_SRC_FOLDER}/build/${BOARD_DIR}/firmware/bl21.bin ${BUILD_PATH} -f
- cp ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/firmware/acs.bin ${BUILD_PATH} -f
- # todo. cp bl40?
-}
-
-function package() {
- # BUILD_PATH without "/"
- x=$((${#BUILD_PATH}-1))
- if [ "\\" == "${BUILD_PATH:$x:1}" ] || [ "/" == "${BUILD_PATH:$x:1}" ]; then
- BUILD_PATH=${BUILD_PATH:0:$x}
- fi
-
- init_vari $@
- build_fip $@
- if [ 1 -eq ${CONFIG_DDR_FW} ]; then
- echo -n "Copy ddr fw..."
- cp ${BLX_SRC_FOLDER}/${DDR_FW_NAME} ${FIP_FOLDER}/${CUR_SOC} -f
- if [ 0 != $? ]; then
- echo " failed!"
- else
- echo " ok!"
- fi
- fi
- encrypt $@
- #copy_file
- #cleanup
- echo "Bootloader build done!"
-}
diff --git a/fip/g12b/ddr3_1d.fw b/fip/g12b/ddr3_1d.fw
deleted file mode 100755
index 16586ff..0000000
--- a/fip/g12b/ddr3_1d.fw
+++ /dev/null
Binary files differ
diff --git a/fip/g12b/ddr4_1d.fw b/fip/g12b/ddr4_1d.fw
deleted file mode 100755
index 2a9db98..0000000
--- a/fip/g12b/ddr4_1d.fw
+++ /dev/null
Binary files differ
diff --git a/fip/g12b/ddr4_2d.fw b/fip/g12b/ddr4_2d.fw
deleted file mode 100755
index f70d3a3..0000000
--- a/fip/g12b/ddr4_2d.fw
+++ /dev/null
Binary files differ
diff --git a/fip/g12b/diag_lpddr4.fw b/fip/g12b/diag_lpddr4.fw
deleted file mode 100755
index f12fa27..0000000
--- a/fip/g12b/diag_lpddr4.fw
+++ /dev/null
Binary files differ
diff --git a/fip/g12b/lpddr4_1d.fw b/fip/g12b/lpddr4_1d.fw
deleted file mode 100755
index 6c98b7a..0000000
--- a/fip/g12b/lpddr4_1d.fw
+++ /dev/null
Binary files differ
diff --git a/fip/g12b/lpddr4_2d.fw b/fip/g12b/lpddr4_2d.fw
deleted file mode 100755
index 5f01b35..0000000
--- a/fip/g12b/lpddr4_2d.fw
+++ /dev/null
Binary files differ
diff --git a/fip/g12b/piei.fw b/fip/g12b/piei.fw
deleted file mode 100755
index 94bff08..0000000
--- a/fip/g12b/piei.fw
+++ /dev/null
Binary files differ
diff --git a/fip/g12b/variable_soc.sh b/fip/g12b/variable_soc.sh
deleted file mode 100755
index a1a881a..0000000
--- a/fip/g12b/variable_soc.sh
+++ /dev/null
@@ -1,31 +0,0 @@
-#!/bin/bash
-
-# static
-declare -a BLX_NAME=("bl2" "bl30" "bl31" "bl32")
-
-declare -a BLX_SRC_FOLDER=("bl2/src" "bl30/src" "bl31/src" "bl32/src" "bl33")
-declare -a BLX_BIN_FOLDER=("bl2/bin" "bl30/bin" "bl31.img" "bl32/bin")
-declare -a BLX_BIN_NAME=("bl2.bin" "bl30.bin" "bl31.img" "bl32.bin")
-declare -a BLX_IMG_NAME=("NULL" "NULL" "bl31.img" "bl32.img")
-declare -a BLX_NEEDFUL=("true" "true" "true" "false")
-
-# blx priority. null: default, source: src code, others: bin path
-declare -a BIN_PATH=("null" "null" "null" "null")
-
-# variables
-declare -a CUR_REV # current version of each blx
-declare -a BLX_READY=("false", "false", "false", "false") # blx build/get flag
-
-# package variables
-declare BL33_COMPRESS_FLAG=""
-declare BL3X_SUFFIX="bin"
-declare V3_PROCESS_FLAG=""
-declare FIP_ARGS=""
-declare AML_BL2_NAME=""
-declare AML_KEY_BLOB_NANE=""
-declare FIP_BL32_PROCESS=""
-
-BUILD_PATH=${FIP_BUILD_FOLDER}
-
-CONFIG_DDR_FW=0
-DDR_FW_NAME="aml_ddr.fw"
\ No newline at end of file
diff --git a/fip/lib.sh b/fip/lib.sh
deleted file mode 100755
index 02b2eee..0000000
--- a/fip/lib.sh
+++ /dev/null
@@ -1,211 +0,0 @@
-#!/bin/bash
-
-DEBUG_PRINT=0
-
-
-declare GIT_OPERATE_INFO=""
-
-function dbg() {
- if [ 0 != ${DEBUG_PRINT} ]; then
- echo "$1"
- fi
-}
-
-declare str_use=""
-# filter means get useful information
-function string_filter() {
- # #1 origin str, #2 filter str, #3 split char, #4 which section
- local str_origin=$1
- local str_filter=$2
- local str_split=$3
- str_origin=${str_origin#*${str_filter}} # filter
- IFS=${str_split} read -ra DATA <<< "$str_origin"
- str_use=${DATA[$4]}
-}
-
-function get_versions() {
- echo "Get version info"
- declare -a SRC_REV
- declare -a BIN_REV
- # read manifest, get each blx information
- if [ -f $MANIFEST ]; then
- while read -r line || [[ -n $line ]]; do
- string_filter "${line}" "dest-branch=" '"' 1
- GIT_INFO[0]=${str_use}
- string_filter "${line}" "path=" '"' 1
- GIT_INFO[1]=${str_use}
- string_filter "${line}" "revision=" '"' 1
- GIT_INFO[2]=${str_use}
- string_filter "${line}" "name=" '"' 1
- GIT_INFO[3]=${str_use}
- string_filter "${line}" "remote=" '"' 1
- GIT_INFO[4]=${str_use}
- # if this line doesn't contain any info, skip it
- if [ "${GIT_INFO[2]}" == "" ]; then
- continue
- fi
- #echo "${GIT_INFO[0]} ${GIT_INFO[1]} ${GIT_INFO[2]} ${GIT_INFO[3]} ${GIT_INFO[4]}"
- #echo ${BLX_NAME[@]}
- #echo ${BLX_SRC_FOLDER[@]}
- for loop in ${!BLX_NAME[@]}; do
- if [ "${GIT_INFO[1]}" == "${BLX_SRC_FOLDER[$loop]}" ]; then
- SRC_REV[$loop]=${GIT_INFO[2]}
- #CUR_BIN_BRANCH[$loop]=${GIT_INFO[0]}
- echo -n "name:${BLX_NAME[$loop]}, path:${BLX_SRC_FOLDER[$loop]}, "
- if [ "${SRC_REV[$loop]}" == "${GIT_INFO[0]}" ]; then
- # if only specify branch name, not version, use latest binaries under bin/ folders
- # use bin.git revision, in case src code have local commits
- if [ -d ${BLX_BIN_FOLDER[loop]} ]; then
- git_operate ${BLX_BIN_FOLDER[loop]} log --pretty=oneline -1
- git_msg=${GIT_OPERATE_INFO}
- else
- git_msg=""
- fi
- IFS=' ' read -ra DATA <<< "$git_msg"
- SRC_REV[$loop]=${DATA[2]}
- echo -n "revL:${SRC_REV[$loop]} "
- else
- SRC_REV[$loop]=${GIT_INFO[2]}
- echo -n "rev:${SRC_REV[$loop]} "
- fi
- echo "@ ${GIT_INFO[0]}"
- fi
- if [ "${GIT_INFO[1]}" == "${BLX_BIN_FOLDER[$loop]}" ]; then
- BIN_REV[$loop]=${GIT_INFO[2]}
- #CUR_BIN_BRANCH[$loop]=${GIT_INFO[0]}
- echo -n "name:${BLX_NAME[$loop]}, path:${BLX_BIN_FOLDER[$loop]}, "
- if [ "${BIN_REV[$loop]}" == "${GIT_INFO[0]}" ]; then
- # if only specify branch name, not version, use latest binaries under bin/ folders
- git_operate ${BLX_BIN_FOLDER[loop]} log --pretty=oneline -1
- else
- # else get bin->src version
- git_operate ${BLX_BIN_FOLDER[loop]} log ${BIN_REV[$loop]} --pretty=oneline -1
- fi
- git_msg=${GIT_OPERATE_INFO}
- IFS=' ' read -ra DATA <<< "$git_msg"
- BIN_REV[$loop]=${DATA[2]}
- echo -n "revL:${BIN_REV[$loop]} "
- echo "@ ${GIT_INFO[0]}"
- fi
- done
- done < "$MANIFEST"
- # SRC_REV="" means this is a no-src repo, use bin.git
- if [ "" == "${SRC_REV[0]}" ]; then
- dbg "src_rev NULL"
- for loop in ${!BIN_REV[@]}; do
- echo "Manifest: Use bin.git version. ${BLX_BIN_FOLDER[$loop]} - ${BIN_REV[$loop]}"
- CUR_REV[$loop]=${BIN_REV[$loop]}
- done
- else
- dbg "src_rev not NULL"
- for loop in ${!SRC_REV[@]}; do
- dbg "Manifest: src.git version. ${BLX_SRC_FOLDER[$loop]} - ${SRC_REV[$loop]}"
- CUR_REV[$loop]=${SRC_REV[$loop]}
- done
- fi
-
- # BIN_REV="" means this is a no-bin repo, use src.git
- if [ "" == "${BIN_REV[0]}" ]; then
- for loop in ${!SRC_REV[@]}; do
- echo "Manifest: Src code only. build with --update-${BLX_NAME[$loop]}"
- #CUR_REV[$loop]=${SRC_REV[$loop]}
- update_bin_path $loop "source"
- done
- fi
- else
- for loop in ${!BLX_NAME[@]}; do
- # merge into android/buildroot, can not get manifest.xml, get version by folder
- # loop src folder
- if [ -d ${BLX_SRC_FOLDER[$loop]} ]; then
- echo "No-Manifest: Src code only. build with --update-${BLX_NAME[$loop]}"
- update_bin_path $loop "source"
- fi
- done
- # loop bin folder. (this will overwrite src version if both exist)
- for loop in ${!BLX_NAME[@]}; do
- if [ -d ${BLX_BIN_FOLDER[$loop]} ]; then
- git_operate ${BLX_BIN_FOLDER[loop]} log --pretty=oneline -1
- git_msg=${GIT_OPERATE_INFO}
- IFS=' ' read -ra DATA <<< "$git_msg"
- CUR_REV[$loop]=${DATA[2]}
- echo -n "revL:${CUR_REV[$loop]} "
- echo "@ ${BLX_BIN_FOLDER[$loop]}"
- fi
- done
- fi
-}
-
-function git_operate() {
- # $1: path, $2: other parameters
- GIT_OPERATE_INFO=`git --git-dir $1/.git --work-tree=$1 ${@:2}`
- dbg "${GIT_OPERATE_INFO}"
-}
-
-function git_operate2() {
- # use -C. for pull use. don't know why [git_operate pull] doesn't work, server git update?
- # $1: path, $2: other parameters
- GIT_OPERATE_INFO="`git -C \"$1\" ${@:2}`"
- #echo "${GIT_OPERATE_INFO}"
-}
-
-function get_blx_bin() {
- # $1: current blx index
- index=$1
- git_operate ${BLX_BIN_FOLDER[index]} log --pretty=oneline
-
- git_msg=${GIT_OPERATE_INFO}
- BLX_READY[${index}]="false"
- mkdir -p ${FIP_BUILD_FOLDER}
-
- # get version log line by line, compare with target version
- line_num=0
- while read line;
- do
- IFS=' ' read -ra DATA <<< "$line"
- # v1-fix support short-id
- dbg "${CUR_REV[$index]:0:7} - ${DATA[2]:0:7}"
- if [ "${CUR_REV[$index]:0:7}" == "${DATA[2]:0:7}" ]; then
- BLX_READY[${index}]="true"
- dbg "blxbin:${DATA[0]} blxsrc: ${DATA[2]}"
- dbg "blxbin:${DATA[0]} blxsrc-s:${DATA[2]:0:7}"
- # reset to history version
- #git --git-dir ${BLX_BIN_FOLDER[index]}/.git --work-tree=${BLX_BIN_FOLDER[index]} reset ${DATA[0]} --hard
- git_operate2 ${BLX_BIN_FOLDER[index]} reset ${DATA[0]} --hard
- # copy binary file
- if [ "bl32" == "${BLX_NAME[$index]}" ]; then
- # bl32 is optional
- if [ "y" == "${CONFIG_NEED_BL32}" ]; then
- cp ${BLX_BIN_FOLDER[index]}/${CUR_SOC}/${BLX_BIN_NAME[index]} ${FIP_BUILD_FOLDER} -f
- if [ "y" == "${CONFIG_FIP_IMG_SUPPORT}" ]; then
- cp ${BLX_BIN_FOLDER[index]}/${CUR_SOC}/${BLX_IMG_NAME[index]} ${FIP_BUILD_FOLDER} 2>/dev/null
- fi
- fi
- else
- cp ${BLX_BIN_FOLDER[index]}/${CUR_SOC}/${BLX_BIN_NAME[index]} ${FIP_BUILD_FOLDER} -f
- if [ "y" == "${CONFIG_FIP_IMG_SUPPORT}" ]; then
- cp ${BLX_BIN_FOLDER[index]}/${CUR_SOC}/${BLX_IMG_NAME[index]} ${FIP_BUILD_FOLDER} 2>/dev/null
- fi
- fi
- # undo reset
- if [ 0 -ne ${line_num} ]; then
- # this is not latest version, can do reset. latest version doesn't have 'git reflog'
- #git --git-dir ${BLX_BIN_FOLDER[index]}/.git --work-tree=${BLX_BIN_FOLDER[index]} reset 'HEAD@{1}' --hard
- git_operate2 ${BLX_BIN_FOLDER[index]} reset 'HEAD@{1}' --hard
- fi
- break
- fi
- line_num=$((line_num+1))
- done <<< "${git_msg}"
- if [ "true" == ${BLX_READY[${index}]} ]; then
- echo "Get ${BLX_NAME[$index]} from ${BLX_BIN_FOLDER[$index]}... done"
- else
- echo -n "Get ${BLX_NAME[$index]} from ${BLX_BIN_FOLDER[$index]}... failed"
- if [ "true" == ${BLX_NEEDFUL[$index]} ]; then
- echo "... abort"
- exit -1
- else
- echo ""
- fi
- fi
- return 0;
-}
\ No newline at end of file
diff --git a/fip/mk b/fip/mk
deleted file mode 100755
index 9b77926..0000000
--- a/fip/mk
+++ /dev/null
@@ -1,4 +0,0 @@
-#!/bin/bash
-### DO NOT EDIT THIS FILE ###
-source fip/mk_script.sh
-### DO NOT EDIT THIS FILE ###
diff --git a/fip/mk_script.sh b/fip/mk_script.sh
deleted file mode 100755
index 15e29ca..0000000
--- a/fip/mk_script.sh
+++ /dev/null
@@ -1,401 +0,0 @@
-#!/bin/bash
-#
-# author: xiaobo.gu@amlogic.com
-# 2016.09.28
-# 2016.12.01-2016.12.20 Update for bootloader repo
-# 2017.05.20-2017.05.26 Update for txlx and ATF1.3
-
-# include compile check script
-source fip/check_compile.sh
-source fip/variables.sh
-source fip/lib.sh
-source fip/build_bl2.sh
-source fip/build_bl30.sh
-source fip/build_bl31.sh
-source fip/build_bl32.sh
-source fip/build_bl33.sh
-source fip/build_bl40.sh
-
-dbg_flag=1
-
-function init_variable_early() {
- # source uboot pre-build configs
- if [ ! -e ${SOURCE_FILE} ]; then
- echo "${SOURCE_FILE} doesn't exist!"
- cd ${MAIN_FOLDER}
- exit -1
- else
- source ${SOURCE_FILE} &> /dev/null # ignore warning/error
- fi
-
- CUR_SOC=${CONFIG_SYS_SOC}
-
- if [ "y" == "${CONFIG_NEED_BL32}" ]; then
- BLX_NEEDFUL[3]="true"
- fi
-
- # export variables
- #export FIP_BUILD_FOLDER
- #export CUR_SOC
-
- export_variables
-}
-
-function init_variable_late() {
- # after uboot build, source configs
- local CONFIG_FILE_TMP="${MAIN_FOLDER}/include/autoconf"
- CONFIG_FILE="${MAIN_FOLDER}/include/autoconf.mk"
- local STR_INVALID="option"
- if [ ! -e ${CONFIG_FILE} ]; then
- echo "${CONFIG_FILE} doesn't exist!"
- cd ${MAIN_FOLDER}
- exit -1
- else
- # workaround for source file error
- while read LINE
- do
- #echo $LINE
- # ignore "*(option)*" lines
- if [[ ${LINE} =~ ${STR_INVALID} ]]; then
- echo "ignore: $LINE"
- else
- #echo "LINE: ${LINE}"
- echo "$LINE" >> "${CONFIG_FILE_TMP}"
- fi
- done < ${CONFIG_FILE}
- source "${CONFIG_FILE_TMP}" &> /dev/null
- rm ${CONFIG_FILE_TMP}
- fi
- if [ "y" == "${CONFIG_SUPPORT_CUSOTMER_BOARD}" ]; then
- BOARD_DIR="customer/board/${CONFIG_SYS_BOARD}"
- elif [ ! "${CONFIG_BOARDDIR}" = "" ];then
- BOARD_DIR="${CONFIG_BOARDDIR}"
- echo "CONFIG_BOARDDIR is not empty, is $CONFIG_BOARDDIR"
- fi
- export BOARD_DIR
-}
-
-function build_blx_src() {
- # compile $name $src_folder $bin_folder $soc
- local name=$1
- local src_folder=$2
- local bin_folder=$3
- local soc=$4
- #dbg "compile - name: ${name}, src_folder: ${src_folder}, bin_folder: ${bin_folder}, soc: ${soc}"
- if [ $name == ${BLX_NAME[0]} ]; then
- # bl2
- build_bl2 $src_folder $bin_folder $soc
- elif [ $name == ${BLX_NAME[1]} ]; then
- # bl30
- build_bl30 $src_folder $bin_folder $soc
- elif [ $name == ${BLX_NAME[2]} ]; then
- # bl31
- # some soc use v1.3
- check_bl31_ver $soc
- if [ $? != 0 ]; then
- echo "check bl31 ver: use v1.3"
- build_bl31_v1_3 $src_folder $bin_folder $soc
- else
- echo "check bl31 ver: use v1.0"
- build_bl31 $src_folder $bin_folder $soc
- fi
- elif [ $name == ${BLX_NAME[3]} ]; then
- # bl32
- if [ "y" == "${CONFIG_NEED_BL32}" ]; then
- build_bl32 $src_folder $bin_folder $soc
- fi
- fi
-}
-
-function build_blx() {
- # build each blx
- mkdir -p ${FIP_BUILD_FOLDER}
-
- # switch bl31 version
- switch_bl31 ${CUR_SOC}
-
- # get version of each blx
- get_versions
-
- # build loop
- for loop in ${!BLX_NAME[@]}; do
- dbg "BIN_PATH[${loop}]: ${BIN_PATH[loop]}"
- if [ "null" == ${BIN_PATH[loop]} ]; then
- get_blx_bin ${loop}
- elif [ "source" == ${BIN_PATH[loop]} ]; then
- dbg "Build blx source code..."
- build_blx_src ${BLX_NAME[loop]} ${BLX_SRC_FOLDER[loop]} ${FIP_BUILD_FOLDER} ${CUR_SOC}
- else
- if [ ! -e ${BIN_PATH[loop]} ]; then
- echo "Error: ${BIN_PATH[loop]} doesn't exist... abort"
- exit -1
- else
- cp ${BIN_PATH[loop]} ${FIP_BUILD_FOLDER} -f
- echo "Get ${BLX_NAME[$loop]} from ${BIN_PATH[loop]}... done"
- fi
- fi
- done
- return
-}
-
-copy_bootloader() {
- mkdir -p ${BUILD_FOLDER}
- cp ${FIP_BUILD_FOLDER}u-boot.bin ${BUILD_FOLDER}u-boot.bin
- cp ${FIP_BUILD_FOLDER}u-boot.bin.sd.bin ${BUILD_FOLDER}u-boot.bin.sd.bin
- cp ${FIP_BUILD_FOLDER}u-boot.bin.usb.bl2 ${BUILD_FOLDER}u-boot.bin.usb.bl2
- cp ${FIP_BUILD_FOLDER}u-boot.bin.usb.tpl ${BUILD_FOLDER}u-boot.bin.usb.tpl
-
- if [ "y" == "${CONFIG_AML_CRYPTO_IMG}" ]; then
- cp ${FIP_BUILD_FOLDER}boot.img.encrypt ${BUILD_FOLDER}boot.img.encrypt
- fi
-}
-
-function update_bin_path() {
- dbg "Update BIN_PATH[$1]=$2"
- BIN_PATH[$1]=$2
-}
-
-function clean() {
- echo "Clean up"
- cd ${UBOOT_SRC_FOLDER}
- make distclean
- cd ${MAIN_FOLDER}
- rm ${FIP_BUILD_FOLDER} -rf
- rm ${BUILD_FOLDER}/* -rf
- return
-}
-
-function build() {
- # *************************************************
- # IMPORTANT!!!!
- # don't change sequence of following function call
- # *************************************************
- clean
-
- # pre-build, get .config defines
- pre_build_uboot $@
- echo "pre_build_uboot done"
-
- echo "to init_variable_early"
- # variable init depends on uboot .config
- init_variable_early $@
-
- # must source under main function, all sub function can use these variables
- # but if source in sub-function, only sub-function(or sub-sub..) can use them
- source ${FIP_FOLDER}${CUR_SOC}/variable_soc.sh
-
- echo "to fip/g12b/build.sh"
- # source soc package script
- source ${FIP_FOLDER}${CUR_SOC}/build.sh
-
- # update bin path, use bin.git or user defined or source code
- bin_path_parser $@
- #bin_path_update $@
-
- # build bl33/bl301..etc
- build_uboot ${dbg_flag} ${BOARD_NAME}
- echo "build_uboot done"
-
- # source other configs after uboot compile
- init_variable_late
-
- # bl2/bl30/bl31..etc, build or copy from bin.git
- build_blx $@
- echo "pwd: `pwd`"
-
- # cp bl33(uboot)
- copy_bl33
- echo "copy_bl33 done"
-
- # cp other firmwares(soc related)
- copy_other_soc
- echo "copy_other done"
-
- # package final bootloader
- package
- echo "package done"
-
- # copy bootloader to main folder
- copy_bootloader
-}
-
-function usage() {
- cat << EOF
- Usage:
- $(basename $0) --help
-
- Bootloader build script.
-
- command list:
- 1. build default uboot:
- ./$(basename $0) [config_name]
-
- 2. build uboot with specified bl[x].bin
- ./$(basename $0) [config_name] --bl[x] [path]
-
- 3. build uboot with bl[x]/src source code
- ./$(basename $0) [config_name] --update-bl[x]
-
- 4. print config list
- ./$(basename $0) --config
-
- 5. check compile status with filter(optional)
- ./$(basename $0) --check-compile [filter]
-
- 6. update aml ddr fw by source code (for g12a and later use)
- ./$(basename $0) [config_name] --update-bl2 --ddrfw
-
-
- Example:
- 1) ./$(basename $0) gxb_p200_v1
- build gxb_p200_v1 config
-
- 2) ./$(basename $0) gxb_p200_v1 --bl2 fip/bl2.bin --bl30 fip/bl30.bin
- build gxb_p200_v1 with specified bl2.bin and bl30.bin
-
- 3) ./$(basename $0) gxb_p200_v1 --update-bl31 --update-bl2
- build gxb_p200_v1 with bl31/bl2 source code
-
- 4) ./$(basename $0) --config
- print config list
-
- 5) ./$(basename $0) --check-compile skt
- check all skt board compile status
-
- Remark:
- bl[x].bin/img priority:
- 1. uboot will use binaries under bl[x]/bin/ folder by default, bl[x] version specified in .repo/manifest.xml
- 2. if you want use your own bl[x].bin, specify path by add "--bl[x] [path]" parameter
- 3. if you want use bl[x].bin by compile source code, please add "--update-bl[x]" parameter
-
-
-EOF
- exit 1
-}
-
-function print_config() {
- cat << EOF
- Usable configs:
-`uboot_config_list`
-EOF
- exit 1
-}
-
-function parser() {
- local i=0
- local argv=()
- for arg in "$@" ; do
- argv[$i]="$arg"
- i=$((i + 1))
- done
- i=0
- while [ $i -lt $# ]; do
- arg="${argv[$i]}"
- i=$((i + 1)) # must place here
- case "$arg" in
- -h|--help|help)
- usage
- exit ;;
- --config)
- print_config
- return ;;
- --check-compile)
- check_compile "${argv[@]:$((i))}"
- exit ;;
- release)
- dbg_flag=0
- return ;;
- clean|distclean|-distclean|--distclean)
- clean
- exit ;;
- *)
- esac
- done
-}
-
-function bin_path_update() {
- # overwrite path in case some git repository doesn't exist
- for loop in ${!BLX_BIN_FOLDER[@]}; do
- if [ -ne ${BLX_BIN_FOLDER[$loop]} ]; then
- dbg "BLX_BIN_FOLDER[$loop] doesn't exist, use src code"
- update_bin_path $loop "source"
- fi
- done
-
- for loop in ${!BLX_SRC_FOLDER[@]}; do
- echo ""
- done
-}
-
-function bin_path_parser() {
- local i=0
- local argv=()
- for arg in "$@" ; do
- argv[$i]="$arg"
- i=$((i + 1))
- done
- i=0
- CONFIG_DDR_FW=0
- ENABLE_DDR_LOGGING=0
- ENABLE_BFT_TIME_SAVING=0
- while [ $i -lt $# ]; do
- arg="${argv[$i]}"
- i=$((i + 1)) # must pleace here
- case "$arg" in
- --bl2)
- update_bin_path 0 "${argv[@]:$((i))}"
- continue ;;
- --bl30)
- update_bin_path 1 "${argv[@]:$((i))}"
- continue ;;
- --bl31)
- update_bin_path 2 "${argv[@]:$((i))}"
- continue ;;
- --bl32)
- update_bin_path 3 "${argv[@]:$((i))}"
- continue ;;
- --update-bl2)
- update_bin_path 0 "source"
- continue ;;
- --update-bl30)
- update_bin_path 1 "source"
- continue ;;
- --update-bl31)
- update_bin_path 2 "source"
- continue ;;
- --update-bl32)
- update_bin_path 3 "source"
- continue ;;
- --ddrfw)
- CONFIG_DDR_FW=1
- continue ;;
- --board_name)
- BOARD_NAME="${argv[@]:$((i))}"
- continue ;;
- --ddrenable)
- ENABLE_DDR_LOGGING=1
- continue ;;
- --bftenable)
- ENABLE_BFT_TIME_SAVING=1
- continue ;;
- *)
- esac
- done
- export CONFIG_DDR_FW # ddr fw define, co-work with bl2 build script
- export ENABLE_DDR_LOGGING # ddr logs define, co-work with timing.c
- export ENABLE_BFT_TIME_SAVING # boot up time saving mode define, co-work with lcd_vout.h
-}
-
-function main() {
- if [ -z $1 ]
- then
- usage
- return
- fi
-
- MAIN_FOLDER=`pwd`
- parser $@
- build $@
-}
-
-main $@ # parse all paras to function
diff --git a/fip/sm1/aml_ddr.fw b/fip/sm1/aml_ddr.fw
deleted file mode 100644
index b32e186..0000000
--- a/fip/sm1/aml_ddr.fw
+++ /dev/null
Binary files differ
diff --git a/fip/sm1/aml_encrypt_g12a b/fip/sm1/aml_encrypt_g12a
deleted file mode 100755
index 85fb7fe..0000000
--- a/fip/sm1/aml_encrypt_g12a
+++ /dev/null
Binary files differ
diff --git a/fip/sm1/build.sh b/fip/sm1/build.sh
deleted file mode 100755
index 0fbbb9c..0000000
--- a/fip/sm1/build.sh
+++ /dev/null
@@ -1,192 +0,0 @@
-#!/bin/bash
-
-# include uboot pre-build macros
-#declare CONFIG_FILE=("${buildtree}/.config")
-#declare AUTOCFG_FILE=("${buildtree}/include/autoconf.mk")
-
-function init_vari() {
- #source ${CONFIG_FILE} &> /dev/null # ignore warning/error
- #source ${AUTOCFG_FILE} &> /dev/null # ignore warning/error
-
- AML_BL2_NAME="bl2.bin"
- AML_KEY_BLOB_NANE="aml-user-key.sig"
-
- if [ "y" == "${CONFIG_AML_SECURE_BOOT_V3}" ]; then
- V3_PROCESS_FLAG="--level v3"
- fi
-
- if [ "y" == "${CONFIG_AML_BL33_COMPRESS_ENABLE}" ]; then
- BL33_COMPRESS_FLAG="--compress lz4"
- fi
-
- if [ "y" == "${CONFIG_FIP_IMG_SUPPORT}" ]; then
- BL3X_SUFFIX="img"
- fi
-}
-
-function fix_blx() {
- #bl2 file size 41K, bl21 file size 3K (file size not equal runtime size)
- #total 44K
- #after encrypt process, bl2 add 4K header, cut off 4K tail
-
- #bl2 file size 56K, acs file size 4K
- #total 60K
- #after encrypt process, bl2 add 4K header, cut off 4K tail
-
- #bl30 limit 41K
- #bl301 limit 12K
-
- #bl2 limit 56K
- #acs limit 4K, but encrypt tool need 64K bl2.bin, so fix to 8192byte.
-
- declare blx_bin_limit=0
- declare blx01_bin_limit=0
- declare -i blx_size=0
- declare -i zero_size=0
-
- #$7:name flag
- if [ "$7" = "bl30" ]; then
- blx_bin_limit=40960 # PD#132613 2016-10-31 update, 41984->40960
- blx01_bin_limit=13312 # PD#132613 2016-10-31 update, 12288->13312
- elif [ "$7" = "bl2" ]; then
- blx_bin_limit=57344
- blx01_bin_limit=4096
- else
- echo "blx_fix name flag not supported!"
- exit 1
- fi
-
- # blx_size: blx.bin size, zero_size: fill with zeros
- blx_size=`du -b $1 | awk '{print int($1)}'`
- zero_size=$blx_bin_limit-$blx_size
- dd if=/dev/zero of=$2 bs=1 count=$zero_size
- cat $1 $2 > $3
- rm $2
-
- blx_size=`du -b $4 | awk '{print int($1)}'`
- zero_size=$blx01_bin_limit-$blx_size
- dd if=/dev/zero of=$2 bs=1 count=$zero_size
- cat $4 $2 > $5
-
- cat $3 $5 > $6
-
- rm $2
-}
-
-function cleanup() {
- rm -f ${BUILD_PATH}/bl*.enc ${BUILD_PATH}/bl2*.sig
- rm -f ${BUILD_PATH}/boot_new.bin
-}
-
-function encrypt_step() {
- dbg "encrypt: $@"
- local ret=0
- ./${FIP_FOLDER}${CUR_SOC}/aml_encrypt_${CUR_SOC} $@
- ret=$?
- if [ 0 != $ret ]; then
- echo "Err! aml_encrypt_${CUR_SOC} return $ret"
- exit $ret
- fi
-}
-
-function encrypt() {
- #u-boot.bin generate
- if [ "y" == "${CONFIG_AML_SECURE_BOOT_V3}" ]; then
- encrypt_step --bl30sig --input ${BUILD_PATH}/bl30_new.bin --output ${BUILD_PATH}/bl30_new.bin.g12.enc ${V3_PROCESS_FLAG}
- encrypt_step --bl3sig --input ${BUILD_PATH}/bl30_new.bin.g12.enc --output ${BUILD_PATH}/bl30_new.bin.enc ${V3_PROCESS_FLAG} --type bl30
- encrypt_step --bl3sig --input ${BUILD_PATH}/bl31.${BL3X_SUFFIX} --output ${BUILD_PATH}/bl31.${BL3X_SUFFIX}.enc ${V3_PROCESS_FLAG} --type bl31
- if [ "${FIP_BL32}" == "${BUILD_PATH}/bl32.${BL3X_SUFFIX}" ]; then
- encrypt_step --bl3sig --input ${BUILD_PATH}/bl32.${BL3X_SUFFIX} --output ${BUILD_PATH}/bl32.${BL3X_SUFFIX}.enc ${V3_PROCESS_FLAG} --type bl32
- fi
- encrypt_step --bl3sig --input ${BUILD_PATH}/bl33.bin ${BL33_COMPRESS_FLAG} --output ${BUILD_PATH}/bl33.bin.enc ${V3_PROCESS_FLAG} --type bl33
- fi
-
- encrypt_step --bl2sig --input ${BUILD_PATH}/bl2_new.bin --output ${BUILD_PATH}/bl2.n.bin.sig
-
- encrypt_step --bootmk --output ${BUILD_PATH}/u-boot.bin \
- --bl2 ${BUILD_PATH}/bl2.n.bin.sig --bl30 ${BUILD_PATH}/bl30_new.bin.enc \
- --bl31 ${BUILD_PATH}/bl31.${BL3X_SUFFIX}.enc ${FIP_BL32_PROCESS} --bl33 ${BUILD_PATH}/bl33.bin.enc ${V3_PROCESS_FLAG} \
- --ddrfw1 ./${FIP_FOLDER}${CUR_SOC}/ddr4_1d.fw --ddrfw2 ./${FIP_FOLDER}${CUR_SOC}/ddr4_2d.fw \
- --ddrfw3 ./${FIP_FOLDER}${CUR_SOC}/ddr3_1d.fw --ddrfw4 ./${FIP_FOLDER}${CUR_SOC}/piei.fw \
- --ddrfw5 ./${FIP_FOLDER}${CUR_SOC}/lpddr4_1d.fw --ddrfw6 ./${FIP_FOLDER}${CUR_SOC}/lpddr4_2d.fw
-
- if [ "y" == "${CONFIG_AML_CRYPTO_UBOOT}" ]; then
- encrypt_step --efsgen --amluserkey ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/${AML_KEY_BLOB_NANE} \
- --output ${BUILD_PATH}/u-boot.bin.encrypt.efuse ${V3_PROCESS_FLAG}
- encrypt_step --bootsig --input ${BUILD_PATH}/u-boot.bin --amluserkey ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/${AML_KEY_BLOB_NANE} \
- --aeskey enable --output ${BUILD_PATH}/u-boot.bin.encrypt ${V3_PROCESS_FLAG}
- fi
-
- if [ "y" == "${CONFIG_AML_CRYPTO_IMG}" ]; then
- encrypt_step --imgsig --input ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/boot.img --amluserkey ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/${AML_KEY_BLOB_NANE} --output ${BUILD_PATH}/boot.img.encrypt
- fi
-
- return
-}
-
-function build_fip() {
- fix_blx \
- ${BUILD_PATH}/bl30.bin \
- ${BUILD_PATH}/zero_tmp \
- ${BUILD_PATH}/bl30_zero.bin \
- ${BUILD_PATH}/bl301.bin \
- ${BUILD_PATH}/bl301_zero.bin \
- ${BUILD_PATH}/bl30_new.bin \
- bl30
-
- # acs_tool process ddr timing and configurable parameters
- #python ${FIP_FOLDER}/acs_tool.pyc ${BUILD_PATH}/${AML_BL2_NAME} ${BUILD_PATH}/bl2_acs.bin ${BUILD_PATH}/acs.bin 0
-
- # fix bl2/bl21
- fix_blx \
- ${BUILD_PATH}/bl2.bin \
- ${BUILD_PATH}/zero_tmp \
- ${BUILD_PATH}/bl2_zero.bin \
- ${BUILD_PATH}/acs.bin \
- ${BUILD_PATH}/bl21_zero.bin \
- ${BUILD_PATH}/bl2_new.bin \
- bl2
-
- # v2: bl30/bl301 merged since 2016.03.22
- FIP_ARGS="--bl30 ${BUILD_PATH}/bl30_new.bin --bl31 ${BUILD_PATH}/bl31.${BL3X_SUFFIX}"
-
- if [ "y" == "${CONFIG_NEED_BL32}" ]; then
- FIP_BL32="`find ${BUILD_PATH} -name "bl32.${BL3X_SUFFIX}"`"
- if [ "${FIP_BL32}" == "${BUILD_PATH}/bl32.${BL3X_SUFFIX}" ]; then
- FIP_ARGS="${FIP_ARGS}"" --bl32 ${BUILD_PATH}/bl32.${BL3X_SUFFIX}"
- FIP_BL32_PROCESS=" --bl32 ${BUILD_PATH}/bl32.${BL3X_SUFFIX}.enc"
- fi
- fi
- FIP_ARGS="${FIP_ARGS}"" --bl33 ${BUILD_PATH}/bl33.bin"
-
- # create fip.bin
- ./${FIP_FOLDER}/fip_create ${FIP_ARGS} ${BUILD_PATH}/fip.bin
- ./${FIP_FOLDER}/fip_create --dump ${BUILD_PATH}/fip.bin
-
- # build final bootloader
- cat ${BUILD_PATH}/bl2_new.bin ${BUILD_PATH}/fip.bin > ${BUILD_PATH}/boot_new.bin
-
- return
-}
-
-function copy_other_soc() {
- cp ${UBOOT_SRC_FOLDER}/scp_task/bl301.bin ${BUILD_PATH} -f
- #useless #cp ${UBOOT_SRC_FOLDER}/build/${BOARD_DIR}/firmware/bl21.bin ${BUILD_PATH} -f
- cp ${UBOOT_SRC_FOLDER}/${BOARD_DIR}/firmware/acs.bin ${BUILD_PATH} -f
- # todo. cp bl40?
-}
-
-function package() {
- # BUILD_PATH without "/"
- x=$((${#BUILD_PATH}-1))
- if [ "\\" == "${BUILD_PATH:$x:1}" ] || [ "/" == "${BUILD_PATH:$x:1}" ]; then
- BUILD_PATH=${BUILD_PATH:0:$x}
- fi
-
- init_vari $@
- build_fip $@
- encrypt $@
- #copy_file
- #cleanup
- echo "Bootloader build done!"
-}
diff --git a/fip/sm1/ddr3_1d.fw b/fip/sm1/ddr3_1d.fw
deleted file mode 100644
index 16586ff..0000000
--- a/fip/sm1/ddr3_1d.fw
+++ /dev/null
Binary files differ
diff --git a/fip/sm1/ddr4_1d.fw b/fip/sm1/ddr4_1d.fw
deleted file mode 100644
index 2a9db98..0000000
--- a/fip/sm1/ddr4_1d.fw
+++ /dev/null
Binary files differ
diff --git a/fip/sm1/ddr4_2d.fw b/fip/sm1/ddr4_2d.fw
deleted file mode 100644
index f70d3a3..0000000
--- a/fip/sm1/ddr4_2d.fw
+++ /dev/null
Binary files differ
diff --git a/fip/sm1/diag_lpddr4.fw b/fip/sm1/diag_lpddr4.fw
deleted file mode 100755
index f12fa27..0000000
--- a/fip/sm1/diag_lpddr4.fw
+++ /dev/null
Binary files differ
diff --git a/fip/sm1/lpddr4_1d.fw b/fip/sm1/lpddr4_1d.fw
deleted file mode 100644
index 6c98b7a..0000000
--- a/fip/sm1/lpddr4_1d.fw
+++ /dev/null
Binary files differ
diff --git a/fip/sm1/lpddr4_2d.fw b/fip/sm1/lpddr4_2d.fw
deleted file mode 100644
index 5f01b35..0000000
--- a/fip/sm1/lpddr4_2d.fw
+++ /dev/null
Binary files differ
diff --git a/fip/sm1/piei.fw b/fip/sm1/piei.fw
deleted file mode 100644
index 94bff08..0000000
--- a/fip/sm1/piei.fw
+++ /dev/null
Binary files differ
diff --git a/fip/sm1/variable_soc.sh b/fip/sm1/variable_soc.sh
deleted file mode 100755
index 75d60a2..0000000
--- a/fip/sm1/variable_soc.sh
+++ /dev/null
@@ -1,31 +0,0 @@
-#!/bin/bash
-
-# static
-declare -a BLX_NAME=("bl2" "bl30" "bl31" "bl32")
-
-declare -a BLX_SRC_FOLDER=("bl2/src" "bl30/src" "bl31/src" "bl32/src" "bl33")
-declare -a BLX_BIN_FOLDER=("bl2/bin" "bl30/bin" "bl31/bin" "bl32/bin")
-declare -a BLX_BIN_NAME=("bl2.bin" "bl30.bin" "bl31.bin" "bl32.bin")
-declare -a BLX_IMG_NAME=("NULL" "NULL" "bl31.img" "bl32.img")
-declare -a BLX_NEEDFUL=("true" "true" "true" "false")
-
-# blx priority. null: default, source: src code, others: bin path
-declare -a BIN_PATH=("null" "null" "null" "null")
-
-# variables
-declare -a CUR_REV # current version of each blx
-declare -a BLX_READY=("false", "false", "false", "false") # blx build/get flag
-
-# package variables
-declare BL33_COMPRESS_FLAG=""
-declare BL3X_SUFFIX="bin"
-declare V3_PROCESS_FLAG=""
-declare FIP_ARGS=""
-declare AML_BL2_NAME=""
-declare AML_KEY_BLOB_NANE=""
-declare FIP_BL32_PROCESS=""
-
-BUILD_PATH=${FIP_BUILD_FOLDER}
-
-CONFIG_DDR_FW=0
-DDR_FW_NAME="aml_ddr.fw"
\ No newline at end of file
diff --git a/fip/variables.sh b/fip/variables.sh
deleted file mode 100755
index a504a1a..0000000
--- a/fip/variables.sh
+++ /dev/null
@@ -1,29 +0,0 @@
-
-declare UBOOT_SRC_FOLDER="./"
-declare MAIN_FOLDER=""
-export UBOOT_SRC_FOLDER MAIN_FOLDER
-
-# build environment
-BUILD_FOLDER="./build/"
-FIP_FOLDER="./fip/"
-MANIFEST="../.repo/manifest.xml"
-FIP_BUILD_FOLDER="./fip/build/"
-
-# include uboot pre-build defines
-SOURCE_FILE=("./.config")
-CONFIG_FILE=("./build/include/autoconf.mk")
-
-# variables
-declare BOARD_DIR=""
-declare CUR_SOC=""
-
-# current branch/path/rev/name/remote in xml
-declare -a GIT_INFO=("branch", "path", "rev", "name", "remote")
-
-function export_variables() {
- export BUILD_FOLDER
- export FIP_FOLDER
- export MANIFEST
- export CUR_SOC
- export BOARD_DIR
-}
diff --git a/fs/Kconfig b/fs/Kconfig
index d797be8..1cb9831 100644
--- a/fs/Kconfig
+++ b/fs/Kconfig
@@ -23,4 +23,3 @@
source "fs/yaffs2/Kconfig"
endmenu
-
diff --git a/fs/btrfs/Kconfig b/fs/btrfs/Kconfig
index 9a7ae85..22909d9 100644
--- a/fs/btrfs/Kconfig
+++ b/fs/btrfs/Kconfig
@@ -7,4 +7,3 @@
This provides a single-device read-only BTRFS support. BTRFS is a
next-generation Linux file system based on the copy-on-write
principle.
-
diff --git a/fs/cbfs/Kconfig b/fs/cbfs/Kconfig
index a027545..1608954 100644
--- a/fs/cbfs/Kconfig
+++ b/fs/cbfs/Kconfig
@@ -6,4 +6,3 @@
on systems that use coreboot as the first boot-loader and then load
U-Boot to actually boot the Operating System. You can also enable
CMD_CBFS to get command-line access.
-
diff --git a/fs/cramfs/Kconfig b/fs/cramfs/Kconfig
index bdf8b9e..6c9f63d 100644
--- a/fs/cramfs/Kconfig
+++ b/fs/cramfs/Kconfig
@@ -5,4 +5,3 @@
filesystem). CRAMFS is useful when space is tight since files are
compressed. You can also enable CMD_CRAMFS to get command-line
access.
-
diff --git a/fs/ext4/Kconfig b/fs/ext4/Kconfig
index ecb53f7..1a913d2 100644
--- a/fs/ext4/Kconfig
+++ b/fs/ext4/Kconfig
@@ -11,4 +11,3 @@
help
This provides support for creating and writing new files to an
existing ext4 filesystem partition.
-
diff --git a/fs/ext4/ext4_common.c b/fs/ext4/ext4_common.c
index 1d70444..67e2471 100644
--- a/fs/ext4/ext4_common.c
+++ b/fs/ext4/ext4_common.c
@@ -510,8 +510,7 @@
restart_read:
/* read the block no allocated to a file */
- first_block_no_of_root = read_allocated_block(g_parent_inode, blk_idx,
- NULL);
+ first_block_no_of_root = read_allocated_block(g_parent_inode, blk_idx);
if (first_block_no_of_root <= 0)
goto fail;
@@ -647,7 +646,7 @@
/* get the block no allocated to a file */
for (blk_idx = 0; blk_idx < directory_blocks; blk_idx++) {
- blknr = read_allocated_block(parent_inode, blk_idx, NULL);
+ blknr = read_allocated_block(parent_inode, blk_idx);
if (blknr <= 0)
goto fail;
@@ -944,7 +943,7 @@
/* read the block no allocated to a file */
for (blk_idx = 0; blk_idx < directory_blocks; blk_idx++) {
- blknr = read_allocated_block(g_parent_inode, blk_idx, NULL);
+ blknr = read_allocated_block(g_parent_inode, blk_idx);
if (blknr <= 0)
break;
inodeno = unlink_filename(filename, blknr);
@@ -1523,7 +1522,7 @@
#endif
static struct ext4_extent_header *ext4fs_get_extent_block
- (struct ext2_data *data, struct ext_block_cache *cache,
+ (struct ext2_data *data, char *buf,
struct ext4_extent_header *ext_block,
uint32_t fileblock, int log2_blksz)
{
@@ -1552,10 +1551,12 @@
block = le16_to_cpu(index[i].ei_leaf_hi);
block = (block << 32) + le32_to_cpu(index[i].ei_leaf_lo);
- block <<= log2_blksz;
- if (!ext_cache_read(cache, (lbaint_t)block, blksz))
+
+ if (ext4fs_devread((lbaint_t)block << log2_blksz, 0, blksz,
+ buf))
+ ext_block = (struct ext4_extent_header *)buf;
+ else
return NULL;
- ext_block = (struct ext4_extent_header *)cache->buf;
}
}
@@ -1583,7 +1584,7 @@
int ext4fs_read_inode(struct ext2_data *data, int ino, struct ext2_inode *inode)
{
- struct ext2_block_group *blkgrp;
+ struct ext2_block_group blkgrp;
struct ext2_sblock *sblock = &data->sblock;
struct ext_filesystem *fs = get_fs();
int log2blksz = get_fs()->dev_desc->log2blksz;
@@ -1591,28 +1592,17 @@
long int blkno;
unsigned int blkoff;
- /* Allocate blkgrp based on gdsize (for 64-bit support). */
- blkgrp = zalloc(get_fs()->gdsize);
- if (!blkgrp)
- return 0;
-
/* It is easier to calculate if the first inode is 0. */
ino--;
status = ext4fs_blockgroup(data, ino / le32_to_cpu
- (sblock->inodes_per_group), blkgrp);
- if (status == 0) {
- free(blkgrp);
+ (sblock->inodes_per_group), &blkgrp);
+ if (status == 0)
return 0;
- }
inodes_per_block = EXT2_BLOCK_SIZE(data) / fs->inodesz;
- blkno = ext4fs_bg_get_inode_table_id(blkgrp, fs) +
+ blkno = ext4fs_bg_get_inode_table_id(&blkgrp, fs) +
(ino % le32_to_cpu(sblock->inodes_per_group)) / inodes_per_block;
blkoff = (ino % inodes_per_block) * fs->inodesz;
-
- /* Free blkgrp as it is no longer required. */
- free(blkgrp);
-
/* Read the inode. */
status = ext4fs_devread((lbaint_t)blkno << (LOG2_BLOCK_SIZE(data) -
log2blksz), blkoff,
@@ -1623,8 +1613,7 @@
return 1;
}
-long int read_allocated_block(struct ext2_inode *inode, int fileblock,
- struct ext_block_cache *cache)
+long int read_allocated_block(struct ext2_inode *inode, int fileblock)
{
long int blknr;
int blksz;
@@ -1641,26 +1630,20 @@
if (le32_to_cpu(inode->flags) & EXT4_EXTENTS_FL) {
long int startblock, endblock;
- struct ext_block_cache *c, cd;
+ char *buf = zalloc(blksz);
+ if (!buf)
+ return -ENOMEM;
struct ext4_extent_header *ext_block;
struct ext4_extent *extent;
int i;
-
- if (cache) {
- c = cache;
- } else {
- c = &cd;
- ext_cache_init(c);
- }
ext_block =
- ext4fs_get_extent_block(ext4fs_root, c,
+ ext4fs_get_extent_block(ext4fs_root, buf,
(struct ext4_extent_header *)
inode->b.blocks.dir_blocks,
fileblock, log2_blksz);
if (!ext_block) {
printf("invalid extent block\n");
- if (!cache)
- ext_cache_fini(c);
+ free(buf);
return -EINVAL;
}
@@ -1672,22 +1655,19 @@
if (startblock > fileblock) {
/* Sparse file */
- if (!cache)
- ext_cache_fini(c);
+ free(buf);
return 0;
} else if (fileblock < endblock) {
start = le16_to_cpu(extent[i].ee_start_hi);
start = (start << 32) +
le32_to_cpu(extent[i].ee_start_lo);
- if (!cache)
- ext_cache_fini(c);
+ free(buf);
return (fileblock - startblock) + start;
}
}
- if (!cache)
- ext_cache_fini(c);
+ free(buf);
return 0;
}
diff --git a/fs/ext4/ext4_journal.c b/fs/ext4/ext4_journal.c
index 6adbab9..148593d 100644
--- a/fs/ext4/ext4_journal.c
+++ b/fs/ext4/ext4_journal.c
@@ -347,7 +347,7 @@
ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO,
(struct ext2_inode *)&inode_journal);
blknr = read_allocated_block((struct ext2_inode *)
- &inode_journal, i, NULL);
+ &inode_journal, i);
ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0, fs->blksz,
temp_buff);
p_jdb = (char *)temp_buff;
@@ -372,7 +372,7 @@
be32_to_cpu(jdb->h_sequence)) == 0)
continue;
}
- blknr = read_allocated_block(&inode_journal, i, NULL);
+ blknr = read_allocated_block(&inode_journal, i);
ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0,
fs->blksz, metadata_buff);
put_ext4((uint64_t)((uint64_t)be32_to_cpu(tag->block) * (uint64_t)fs->blksz),
@@ -419,8 +419,7 @@
}
ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal);
- blknr = read_allocated_block(&inode_journal, EXT2_JOURNAL_SUPERBLOCK,
- NULL);
+ blknr = read_allocated_block(&inode_journal, EXT2_JOURNAL_SUPERBLOCK);
ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0, fs->blksz,
temp_buff);
jsb = (struct journal_superblock_t *) temp_buff;
@@ -444,7 +443,7 @@
i = be32_to_cpu(jsb->s_first);
while (1) {
- blknr = read_allocated_block(&inode_journal, i, NULL);
+ blknr = read_allocated_block(&inode_journal, i);
memset(temp_buff1, '\0', fs->blksz);
ext4fs_devread((lbaint_t)blknr * fs->sect_perblk,
0, fs->blksz, temp_buff1);
@@ -538,7 +537,7 @@
ext4_read_superblock((char *)fs->sb);
blknr = read_allocated_block(&inode_journal,
- EXT2_JOURNAL_SUPERBLOCK, NULL);
+ EXT2_JOURNAL_SUPERBLOCK);
put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz),
(struct journal_superblock_t *)temp_buff,
(uint32_t) fs->blksz);
@@ -567,7 +566,7 @@
ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal);
jsb_blknr = read_allocated_block(&inode_journal,
- EXT2_JOURNAL_SUPERBLOCK, NULL);
+ EXT2_JOURNAL_SUPERBLOCK);
ext4fs_devread((lbaint_t)jsb_blknr * fs->sect_perblk, 0, fs->blksz,
temp_buff);
jsb = (struct journal_superblock_t *) temp_buff;
@@ -619,7 +618,7 @@
ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO,
&inode_journal);
jsb_blknr = read_allocated_block(&inode_journal,
- EXT2_JOURNAL_SUPERBLOCK, NULL);
+ EXT2_JOURNAL_SUPERBLOCK);
ext4fs_devread((lbaint_t)jsb_blknr * fs->sect_perblk, 0, fs->blksz,
temp_buff);
jsb = (struct journal_superblock_t *) temp_buff;
@@ -646,17 +645,16 @@
long int blknr;
int i;
ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO, &inode_journal);
- blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++, NULL);
+ blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++);
update_descriptor_block(blknr);
for (i = 0; i < MAX_JOURNAL_ENTRIES; i++) {
if (journal_ptr[i]->blknr == -1)
break;
- blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++,
- NULL);
+ blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++);
put_ext4((uint64_t) ((uint64_t)blknr * (uint64_t)fs->blksz),
journal_ptr[i]->buf, fs->blksz);
}
- blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++, NULL);
+ blknr = read_allocated_block(&inode_journal, jrnl_blk_idx++);
update_commit_block(blknr);
printf("update journal finished\n");
}
diff --git a/fs/ext4/ext4_write.c b/fs/ext4/ext4_write.c
index 8615689..a7f543f 100644
--- a/fs/ext4/ext4_write.c
+++ b/fs/ext4/ext4_write.c
@@ -479,7 +479,7 @@
/* release data blocks */
for (i = 0; i < no_blocks; i++) {
- blknr = read_allocated_block(&inode, i, NULL);
+ blknr = read_allocated_block(&inode, i);
if (blknr == 0)
continue;
if (blknr < 0)
@@ -695,7 +695,7 @@
ext4fs_read_inode(ext4fs_root, EXT2_JOURNAL_INO,
&inode_journal);
blknr = read_allocated_block(&inode_journal,
- EXT2_JOURNAL_SUPERBLOCK, NULL);
+ EXT2_JOURNAL_SUPERBLOCK);
ext4fs_devread((lbaint_t)blknr * fs->sect_perblk, 0, fs->blksz,
temp_buff);
jsb = (struct journal_superblock_t *)temp_buff;
@@ -776,7 +776,7 @@
long int blknr;
int blockend = fs->blksz;
int skipfirst = 0;
- blknr = read_allocated_block(file_inode, i, NULL);
+ blknr = read_allocated_block(file_inode, i);
if (blknr <= 0)
return -1;
diff --git a/fs/ext4/ext4fs.c b/fs/ext4/ext4fs.c
index 4624042..2a28031 100644
--- a/fs/ext4/ext4fs.c
+++ b/fs/ext4/ext4fs.c
@@ -61,21 +61,15 @@
lbaint_t delayed_skipfirst = 0;
lbaint_t delayed_next = 0;
char *delayed_buf = NULL;
- char *start_buf = buf;
short status;
- struct ext_block_cache cache;
- ext_cache_init(&cache);
+ if (blocksize <= 0)
+ return -1;
/* Adjust len so it we can't read past the end of the file. */
if (len + pos > filesize)
len = (filesize - pos);
- if (blocksize <= 0 || len <= 0) {
- ext_cache_fini(&cache);
- return -1;
- }
-
blockcnt = lldiv(((len + pos) + blocksize - 1), blocksize);
for (i = lldiv(pos, blocksize); i < blockcnt; i++) {
@@ -83,11 +77,9 @@
int blockoff = pos - (blocksize * i);
int blockend = blocksize;
int skipfirst = 0;
- blknr = read_allocated_block(&node->inode, i, &cache);
- if (blknr < 0) {
- ext_cache_fini(&cache);
+ blknr = read_allocated_block(&(node->inode), i);
+ if (blknr < 0)
return -1;
- }
blknr = blknr << log2_fs_blocksize;
@@ -117,10 +109,8 @@
delayed_skipfirst,
delayed_extent,
delayed_buf);
- if (status == 0) {
- ext_cache_fini(&cache);
+ if (status == 0)
return -1;
- }
previous_block_number = blknr;
delayed_start = blknr;
delayed_extent = blockend;
@@ -140,24 +130,20 @@
}
} else {
int n;
- int n_left;
if (previous_block_number != -1) {
/* spill */
status = ext4fs_devread(delayed_start,
delayed_skipfirst,
delayed_extent,
delayed_buf);
- if (status == 0) {
- ext_cache_fini(&cache);
+ if (status == 0)
return -1;
- }
previous_block_number = -1;
}
/* Zero no more than `len' bytes. */
n = blocksize - skipfirst;
- n_left = len - (buf - start_buf);
- if (n > n_left)
- n = n_left;
+ if (n > len)
+ n = len;
memset(buf, 0, n);
}
buf += blocksize - skipfirst;
@@ -167,15 +153,12 @@
status = ext4fs_devread(delayed_start,
delayed_skipfirst, delayed_extent,
delayed_buf);
- if (status == 0) {
- ext_cache_fini(&cache);
+ if (status == 0)
return -1;
- }
previous_block_number = -1;
}
*actread = len;
- ext_cache_fini(&cache);
return 0;
}
@@ -269,32 +252,3 @@
return -ENOSYS;
#endif
}
-
-void ext_cache_init(struct ext_block_cache *cache)
-{
- memset(cache, 0, sizeof(*cache));
-}
-
-void ext_cache_fini(struct ext_block_cache *cache)
-{
- free(cache->buf);
- ext_cache_init(cache);
-}
-
-int ext_cache_read(struct ext_block_cache *cache, lbaint_t block, int size)
-{
- /* This could be more lenient, but this is simple and enough for now */
- if (cache->buf && cache->block == block && cache->size == size)
- return 1;
- ext_cache_fini(cache);
- cache->buf = malloc(size);
- if (!cache->buf)
- return 0;
- if (!ext4fs_devread(block, 0, size, cache->buf)) {
- free(cache->buf);
- return 0;
- }
- cache->block = block;
- cache->size = size;
- return 1;
-}
diff --git a/fs/fat/Kconfig b/fs/fat/Kconfig
index 52e9e69..9bb11ea 100644
--- a/fs/fat/Kconfig
+++ b/fs/fat/Kconfig
@@ -22,4 +22,3 @@
is the smallest amount of disk space that can be used to hold a
file. Unless you have an extremely tight memory memory constraints,
leave the default.
-
diff --git a/fs/fs.c b/fs/fs.c
index 815710c..cb26517 100644
--- a/fs/fs.c
+++ b/fs/fs.c
@@ -429,57 +429,13 @@
return ret;
}
-#ifdef CONFIG_LMB
-/* Check if a file may be read to the given address */
-static int fs_read_lmb_check(const char *filename, ulong addr, loff_t offset,
- loff_t len, struct fstype_info *info)
-{
- struct lmb lmb;
- int ret;
- loff_t size;
- loff_t read_len;
-
- /* get the actual size of the file */
- ret = info->size(filename, &size);
- if (ret)
- return ret;
- if (offset >= size) {
- /* offset >= EOF, no bytes will be written */
- return 0;
- }
- read_len = size - offset;
-
- /* limit to 'len' if it is smaller */
- if (len && len < read_len)
- read_len = len;
-
- lmb_init_and_reserve(&lmb, gd->bd->bi_dram[0].start,
- gd->bd->bi_dram[0].size, (void *)gd->fdt_blob);
- lmb_dump_all(&lmb);
-
- if (lmb_alloc_addr(&lmb, addr, read_len) == addr)
- return 0;
-
- printf("** Reading file would overwrite reserved memory **\n");
- return -ENOSPC;
-}
-#endif
-
-static int _fs_read(const char *filename, ulong addr, loff_t offset, loff_t len,
- int do_lmb_check, loff_t *actread)
+int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len,
+ loff_t *actread)
{
struct fstype_info *info = fs_get_info(fs_type);
void *buf;
int ret;
-#ifdef CONFIG_LMB
- if (do_lmb_check) {
- ret = fs_read_lmb_check(filename, addr, offset, len, info);
- if (ret)
- return ret;
- }
-#endif
-
/*
* We don't actually know how many bytes are being read, since len==0
* means read the whole file.
@@ -496,12 +452,6 @@
return ret;
}
-int fs_read(const char *filename, ulong addr, loff_t offset, loff_t len,
- loff_t *actread)
-{
- return _fs_read(filename, addr, offset, len, 0, actread);
-}
-
int fs_write(const char *filename, ulong addr, loff_t offset, loff_t len,
loff_t *actwrite)
{
@@ -672,12 +622,11 @@
pos = 0;
time = get_timer(0);
- ret = _fs_read(filename, addr, pos, bytes, 1, &len_read);
+ ret = fs_read(filename, addr, pos, bytes, &len_read);
time = get_timer(time);
if (ret < 0)
return 1;
-#ifdef BL33_DEBUG_PRINT
printf("%llu bytes read in %lu ms", len_read, time);
if (time > 0) {
puts(" (");
@@ -685,7 +634,6 @@
puts(")");
}
puts("\n");
-#endif
env_set_hex("fileaddr", addr);
env_set_hex("filesize", len_read);
diff --git a/fs/jffs2/Kconfig b/fs/jffs2/Kconfig
index 831be85..1b9ecdd 100644
--- a/fs/jffs2/Kconfig
+++ b/fs/jffs2/Kconfig
@@ -5,4 +5,3 @@
Flash File System version 2). JFFS2 is a log-structured file system
for use with flash memory devices. It supports raw NAND devices,
hard links and compression.
-
diff --git a/fs/ubifs/Kconfig b/fs/ubifs/Kconfig
index 8e028a6..9da35b8 100644
--- a/fs/ubifs/Kconfig
+++ b/fs/ubifs/Kconfig
@@ -4,4 +4,3 @@
help
Make the verbose messages from UBIFS stop printing. This leaves
warnings and errors enabled.
-
diff --git a/fs/yaffs2/Kconfig b/fs/yaffs2/Kconfig
index 14d8ebb..45ffdf6 100644
--- a/fs/yaffs2/Kconfig
+++ b/fs/yaffs2/Kconfig
@@ -5,4 +5,3 @@
Filesystem 2 is a filesystem designed specifically for NAND flash.
It incorporates bad-block management and ensures that device
writes are sequential regardless of filesystem activity.
-
diff --git a/include/adc.h b/include/adc.h
index c845e1e..6eca7ed 100644
--- a/include/adc.h
+++ b/include/adc.h
@@ -15,14 +15,17 @@
#ifdef CONFIG_SARADC_MESON
-#define ADC_CAPACITY_COMMON 0x00000000
#define ADC_CAPACITY_AVERAGE 0x00000001
#define ADC_CAPACITY_HIGH_PRECISION_VREF 0x00000002
+#define ADC_CAPACITY_DECIM_FILTER 0x00000004
-#define ADC_MODE_STARDAND ADC_CAPACITY_COMMON
#define ADC_MODE_AVERAGE ADC_CAPACITY_AVERAGE
#define ADC_MODE_HIGH_PRECISION (ADC_CAPACITY_AVERAGE | \
ADC_CAPACITY_HIGH_PRECISION_VREF)
+/* The following modes are only used in C2 */
+#define ADC_MODE_HIGH_RESOLUTION (ADC_CAPACITY_DECIM_FILTER | \
+ ADC_CAPACITY_HIGH_PRECISION_VREF)
+#define ADC_MODE_DECIM_FILTER ADC_CAPACITY_DECIM_FILTER
#endif
/**
diff --git a/include/amlogic/aml_cec.h b/include/amlogic/aml_cec.h
index 4f0b2bd..59690fc 100644
--- a/include/amlogic/aml_cec.h
+++ b/include/amlogic/aml_cec.h
@@ -1,15 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * include/amlogic/aml_cec.h
- *
- * Copyright (C) 2012 AMLOGIC, INC. All Rights Reserved.
- * Author: hongmin hua <hongmin hua@amlogic.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the smems of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
-
#ifndef _AML_CEC_H
#define _AML_CEC_H
diff --git a/include/amlogic/aml_efuse.h b/include/amlogic/aml_efuse.h
index 72ce961..572841c 100644
--- a/include/amlogic/aml_efuse.h
+++ b/include/amlogic/aml_efuse.h
@@ -1,8 +1,7 @@
-
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __BL2_EFUSE_H__
#define __BL2_EFUSE_H__
@@ -66,5 +65,17 @@
//EFUSE_LICX --> AO_SEC_SD_CFG10/9 --> EFUSE mirror
int IS_FEAT_BOOT_VERIFY(void);
int IS_FEAT_BOOT_ENCRYPT(void);
+int IS_FEAT_DIS_EMMC_USER(void);
+int IS_FEAT_DIS_EMMC_BOOT_0(void);
+int IS_FEAT_DIS_EMMC_BOOT_1(void);
+int IS_FEAT_EN_4BL2_SNOR(void);
+int IS_FEAT_DIS_NBL2_SNOR(void);
+int IS_FEAT_EN_8BL2_SNAND(void);
+int IS_FEAT_DIS_NBL2_SNAND(void);
+int IS_FEAT_DIS_8BL2_NAND(void);
+int IS_FEAT_DIS_NBL2_NAND(void);
+int IS_FEAT_DIS_CHIPSET_ROOTCERT_0(void);
+int IS_FEAT_DIS_NORMAL_DEVICE_ROOTCERT_0(void);
+int IS_FEAT_DIS_DFU_DEVICE_ROOTCERT_0(void);
#endif /* __BL2_EFUSE_H__ */
diff --git a/include/amlogic/aml_gpio.h b/include/amlogic/aml_gpio.h
index c1e1ed1..3ab0cd2 100644
--- a/include/amlogic/aml_gpio.h
+++ b/include/amlogic/aml_gpio.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __AML_GPIO__
#define __AML_GPIO__
#include <asm/io.h>
diff --git a/include/amlogic/aml_hdmirx.h b/include/amlogic/aml_hdmirx.h
index b4b0f5a..e22c7fa 100644
--- a/include/amlogic/aml_hdmirx.h
+++ b/include/amlogic/aml_hdmirx.h
@@ -1,12 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * include/amlogic/aml_hdmirx.h
- *
- * Copyright (C) 2012 AMLOGIC, INC. All Rights Reserved.
- * Author: hongmin hua <hongmin hua@amlogic.com>
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the smems of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef _AML_HDMIRX_H
diff --git a/include/amlogic/aml_irblaster.h b/include/amlogic/aml_irblaster.h
index b2c4ef7..b24d82f 100644
--- a/include/amlogic/aml_irblaster.h
+++ b/include/amlogic/aml_irblaster.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __AML_IRBLATER_H
#define __AML_IRBLATER_H
diff --git a/include/amlogic/aml_is31fl32xx.h b/include/amlogic/aml_is31fl32xx.h
index 6211ebc..89a75e8 100644
--- a/include/amlogic/aml_is31fl32xx.h
+++ b/include/amlogic/aml_is31fl32xx.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __AML_IS31F132XX
#define __AML_IS31F132XX
diff --git a/include/amlogic/aml_led.h b/include/amlogic/aml_led.h
index b2f3bda..10e44ed 100644
--- a/include/amlogic/aml_led.h
+++ b/include/amlogic/aml_led.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __AML_LED_H__
#define __AML_LED_H__
diff --git a/include/amlogic/aml_mmc.h b/include/amlogic/aml_mmc.h
index 319ebee..ecfb4fc 100644
--- a/include/amlogic/aml_mmc.h
+++ b/include/amlogic/aml_mmc.h
@@ -1,19 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- * yonghui.yu@amlogic.com
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
-
#ifndef __AML_MMC_H__
#define __AML_MMC_H__
@@ -27,6 +16,22 @@
#define AML_BL_BOOT (0x6)
#define AML_BL_ALL (0x7)
+/** For actul partitions with mask 8 store into bootinfo
+ * name: partition name.
+ * addr: sector addr of the partition
+ * size: sector cont of the partition
+*/
+struct part_property
+{
+ char name[8];
+ uint32_t addr;
+ uint32_t size;
+};
+#define PART_PROPERTY_SIZE sizeof(struct part_property)
+#define BOOTINFO_MAX_PARTITIONS (4)
+#define BOOTINFO_PARITIONS_SIZE (PART_PROPERTY_SIZE * BOOTINFO_MAX_PARTITIONS)
+
+
#define VPART_PROPERTY_SIZE sizeof(struct vpart_property)
struct vpart_property {
u32 addr;
@@ -48,7 +53,9 @@
u32 rsv_base_addr;
struct vpart_property dtb;
struct vpart_property ddr;
- u8 reserved[512 - 2 * VPART_PROPERTY_SIZE - 12];
+
+ struct part_property parts[BOOTINFO_MAX_PARTITIONS];
+ uint8_t reserved[512 - 2 * VPART_PROPERTY_SIZE - BOOTINFO_PARITIONS_SIZE - 12];
u32 checksum;
};
diff --git a/include/amlogic/aml_mtd.h b/include/amlogic/aml_mtd.h
index 4e5d469..2fbc4bb 100644
--- a/include/amlogic/aml_mtd.h
+++ b/include/amlogic/aml_mtd.h
@@ -1,32 +1,24 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Header file of amlogic mtd driver
- *
- * Copyright (C) 2018 Amlogic Corporation
- *
- * Licensed under the GPL-2 or later.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __AMLMTD_H_
#define __AMLMTD_H_
#define BOOT_TOTAL_PAGES 1024
-#define CONFIG_DISCRETE_BOOTLOADER
-
-#if defined(CONFIG_SPI_NAND) && !defined(CONFIG_DISCRETE_BOOTLOADER)
-#error SPI NAND only support discrete boot mode!
-#endif
-
-#ifdef CONFIG_DISCRETE_BOOTLOADER
#define CONFIG_BL2_COPY_NUM 8
#define CONFIG_TPL_SIZE_PER_COPY 0x200000
-#define CONFIG_TPL_COPY_NUM 4
-#endif/* CONFIG_DISCRETE_BOOTLOADER */
+#define CONFIG_NOR_TPL_COPY_NUM 1 //for spi-nor
+#define CONFIG_NAND_TPL_COPY_NUM 4 // for slc & spi-nand
#define BOOT_LOADER "bootloader"
#define BOOT_BL2 "bl2"
#define BOOT_SPL "spl"
+#define BOOT_BL2E "bl2e"
+#define BOOT_BL2X "bl2x"
+#define BOOT_DDRFIP "ddrfip"
+#define BOOT_DEVFIP "devfip"
#define BOOT_TPL "tpl"
#define BOOT_FIP "fip"
#define MAX_MTD_CNT 2
diff --git a/include/amlogic/aml_nand.h b/include/amlogic/aml_nand.h
index 8be3974..53e12c3 100644
--- a/include/amlogic/aml_nand.h
+++ b/include/amlogic/aml_nand.h
@@ -1,17 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#ifndef __AML_NAND_H__
#define __AML_NAND_H__
diff --git a/include/amlogic/aml_rsv.h b/include/amlogic/aml_rsv.h
index 7e17c83..c5aa4e8 100644
--- a/include/amlogic/aml_rsv.h
+++ b/include/amlogic/aml_rsv.h
@@ -1,11 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Header file of amlogic reserve manager
- *
- * Copyright (C) 2018 Amlogic Corporation
- *
- * Licensed under the GPL-2 or later.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __MESON_RSV_H_
@@ -18,17 +13,19 @@
#define NAND_ENV_BLOCK_NUM 8
#define NAND_KEY_BLOCK_NUM 8
#define NAND_DTB_BLOCK_NUM 4
+#define NAND_DDR_BLOCK_NUM 2
#define BBT_NAND_MAGIC "nbbt"
#define ENV_NAND_MAGIC "nenv"
#define KEY_NAND_MAGIC "nkey"
#define SEC_NAND_MAGIC "nsec"
#define DTB_NAND_MAGIC "ndtb"
+#define DDR_NAND_MAGIC "nddr"
/*define abnormal state for reserved area*/
#define POWER_ABNORMAL_FLAG 0x01
#define ECC_ABNORMAL_FLAG 0x02
-
+#define DDR_PARA_SIZE 2048
struct meson_rsv_info_t {
struct mtd_info *mtd;
@@ -76,6 +73,7 @@
#endif
struct meson_rsv_info_t *key;
struct meson_rsv_info_t *dtb;
+ struct meson_rsv_info_t *ddr_para;
void *priv;
};
@@ -83,18 +81,22 @@
int meson_rsv_key_read(u_char *dest, size_t size);
int meson_rsv_env_read(u_char *dest, size_t size);
int meson_rsv_dtb_read(u_char *dest, size_t size);
+int meson_rsv_ddr_para_read(u_char *dest, size_t size);
/* do not provide bbt write operates */
int meson_rsv_key_write(u_char *source, size_t size);
int meson_rsv_env_write(u_char *source, size_t size);
int meson_rsv_dtb_write(u_char *source, size_t size);
+int meson_rsv_ddr_para_write(u_char *source, size_t size);
uint32_t meson_rsv_bbt_size(void);
uint32_t meson_rsv_key_size(void);
uint32_t meson_rsv_env_size(void);
uint32_t meson_rsv_dtb_size(void);
+u32 meson_rsv_ddr_para_size(void);
/* do not provide bbt erase operates */
int meson_rsv_key_erase(void);
int meson_rsv_env_erase(void);
int meson_rsv_dtb_erase(void);
+int meson_rsv_ddr_para_erase(void);
int meson_rsv_check(struct meson_rsv_info_t *rsv_info);
int meson_rsv_init(struct mtd_info *mtd, struct meson_rsv_handler_t *handler);
int meson_rsv_scan(struct meson_rsv_info_t *rsv_info);
diff --git a/include/amlogic/aml_tlv.h b/include/amlogic/aml_tlv.h
index 93fa0a3..f1a513a 100644
--- a/include/amlogic/aml_tlv.h
+++ b/include/amlogic/aml_tlv.h
@@ -1,35 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * All information contained herein is Amlogic confidential.
- *
- * This software is provided to you pursuant to Software License Agreement
- * (SLA) with Amlogic Inc ("Amlogic"). This software may be used
- * only in accordance with the terms of this agreement.
- *
- * Redistribution and use in source and binary forms, with or without
- * modification is strictly prohibited without prior written permission from
- * Amlogic.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
- * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
- * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
- * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
- * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
- * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- *
- * Created by haixiang.bao@amlogic.com
- *
- * Revision history: 1. 2018.05.31 v0.1 init for transfer data from BL2 to BL3X
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
-
#ifndef __AMLOGIC_TLV_H_
#define __AMLOGIC_TLV_H_
diff --git a/include/amlogic/aml_v2_burning.h b/include/amlogic/aml_v2_burning.h
index 1ecdad6..8729858 100644
--- a/include/amlogic/aml_v2_burning.h
+++ b/include/amlogic/aml_v2_burning.h
@@ -1,13 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * \file aml_v2_burning.h
- * \brief common interfaces for version burning
- *
- * \version 1.0.0
- * \date 09/15/2013
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2013 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
//is the uboot loaded from usb otg
diff --git a/include/amlogic/aml_v3_burning.h b/include/amlogic/aml_v3_burning.h
new file mode 100644
index 0000000..b6e7fc7
--- /dev/null
+++ b/include/amlogic/aml_v3_burning.h
@@ -0,0 +1,7 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+int aml_v3_factory_usb_burning(int flag, bd_t* bis);
+
diff --git a/include/amlogic/amlkey_if.h b/include/amlogic/amlkey_if.h
index 81f1c7c..948dfc8 100644
--- a/include/amlogic/amlkey_if.h
+++ b/include/amlogic/amlkey_if.h
@@ -1,45 +1,79 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * \file amlkey_if.h
- * \brief APIs of secure key for users
- *
- * \version 1.0.0
- * \date 15/07/10
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2015 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#ifndef __AMLKEY_IF_H__
#define __AMLKEY_IF_H__
#define AMLKEY_NAME_LEN_MAX (80)
+
+struct amlkey_if {
+ int32_t (*init)(uint8_t *seed, uint32_t len, int encrypt_type);
+ int32_t (*exsit)(const uint8_t *name);
+ ssize_t (*size)(const uint8_t *name);
+ uint32_t (*get_attr)(const uint8_t *name);
+ ssize_t (*read)(const uint8_t *name, uint8_t *buffer, uint32_t len);
+ ssize_t (*write)(const uint8_t *name, uint8_t *buffer, uint32_t len, uint32_t attr);
+ int32_t (*hash)(const uint8_t *name, uint8_t *hash);
+};
+
+extern struct amlkey_if *amlkey_if;
+
+static inline uint32_t amlkey_get_attr(const uint8_t *name)
+{
+ return amlkey_if->get_attr(name);
+}
+
+int amlkey_if_init(const void* dt_addr);
+
//1.init
-int32_t amlkey_init(uint8_t *seed, uint32_t len, int encrypt_type);
+static inline int32_t amlkey_init(uint8_t *seed, uint32_t len, int encrypt_type)
+{
+ return amlkey_if->init(seed, len, encrypt_type);
+}
//2. query if the key already programmed, exsit 1, non 0
-int32_t amlkey_isexsit(const uint8_t * name);
+static inline int32_t amlkey_isexsit(const uint8_t * name)
+{
+ return amlkey_if->exsit(name);
+}
//3. query attr, key must exsit before those functions were called.
//3.1 whether the prgrammed key is secure, secure 1, non 0
int32_t amlkey_issecure(const uint8_t * name);
+
//3.2 whether the prgrammed key is encrypt, encrypt 1, non 0
int32_t amlkey_isencrypt(const uint8_t * name);
//4. actual bytes of key value
-ssize_t amlkey_size(const uint8_t *name);
+static inline ssize_t amlkey_size(const uint8_t *name)
+{
+ return amlkey_if->size(name);
+}
//5. read non-secure key in bytes, return byets readback actully.
-ssize_t amlkey_read(const uint8_t *name, uint8_t *buffer, uint32_t len) ;
+static inline ssize_t amlkey_read(const uint8_t *name, uint8_t *buffer, uint32_t len)
+{
+ return amlkey_if->read(name, buffer, len);
+}
//6.write key with attribute in bytes , return byets readback actully
//attr: bit0: secure/non-secure;
// bit8: encrypt/non-encrypt
#define UNIFYKEY_ATTR_SECURE_MASK (1<<0)
#define UNIFYKEY_ATTR_ENCRYPT_MASK (1<<8)
-ssize_t amlkey_write(const uint8_t *name, uint8_t *buffer, uint32_t len, uint32_t attr);
+static inline ssize_t amlkey_write(const uint8_t *name, uint8_t *buffer, uint32_t len,
+ uint32_t attr)
+{
+ return amlkey_if->write(name, buffer, len, attr);
+}
//7. get the hash value of programmed secure key | 32bytes length, sha256
-int32_t amlkey_hash_4_secure(const uint8_t * name, uint8_t * hash);
+static inline int32_t amlkey_hash_4_secure(const uint8_t *name, uint8_t *hash)
+{
+ return amlkey_if->hash(name, hash);
+}
#endif// #ifndef __AMLKEY_IF_H__
diff --git a/include/amlogic/anti-rollback.h b/include/amlogic/anti-rollback.h
new file mode 100644
index 0000000..93a9168
--- /dev/null
+++ b/include/amlogic/anti-rollback.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __ANTI_ROLLBACK_
+#define __ANTI_ROLLBACK_
+
+#include <linux/types.h>
+
+bool check_antirollback(uint32_t kernel_version);
+
+bool set_avb_antirollback(uint32_t index, uint32_t version);
+bool get_avb_antirollback(uint32_t index, uint32_t* version);
+bool get_avb_lock_state(uint32_t* lock_state);
+bool avb_lock(void);
+bool avb_unlock(void);
+
+#endif
diff --git a/include/amlogic/auge_sound.h b/include/amlogic/auge_sound.h
new file mode 100644
index 0000000..8368ed5
--- /dev/null
+++ b/include/amlogic/auge_sound.h
@@ -0,0 +1,13 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __AUGE_SOUND_H__
+#define __AUGE_SOUND_H__
+
+/* auge audio register is defined in asm/arch/secure_apb.h */
+
+int aml_audio_init(void);
+
+#endif
diff --git a/include/amlogic/blxx2bl33_param.h b/include/amlogic/blxx2bl33_param.h
new file mode 100644
index 0000000..c8768e4
--- /dev/null
+++ b/include/amlogic/blxx2bl33_param.h
@@ -0,0 +1,32 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __BLXX2BL33_PARAM_H__
+#define __BLXX2BL33_PARAM_H__
+#include <common.h>
+
+/* !!! don't try to modify the Micro unless make a consistency with blxx */
+
+#define BL2E2BL33_PARAM_START (0x0e00000)
+#define BL2E2BL33_PARAM_END (0x1000000)
+
+#define BLXX2BL33_PARAM_DEBUG (0)
+
+/* define the parameter type here and make sure the same with blxx */
+enum {
+ STORAGE_PARAM_TPYE = 1,
+ BL2PARMA_PARAM_TYPE = 2,
+ /* other */
+};
+
+struct param_e {
+ unsigned int type;
+ unsigned int len; /* must be 8 bytes align */
+ unsigned char data[1]; /* user defined parameter */
+};
+
+struct param_e *param_of(int type);
+
+#endif
\ No newline at end of file
diff --git a/include/amlogic/canvas.h b/include/amlogic/canvas.h
index dc9ed10..8f68535 100644
--- a/include/amlogic/canvas.h
+++ b/include/amlogic/canvas.h
@@ -1,17 +1,7 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
-*/
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef CANVAS_H
#define CANVAS_H
diff --git a/include/amlogic/clk_measure.h b/include/amlogic/clk_measure.h
new file mode 100644
index 0000000..3525f04
--- /dev/null
+++ b/include/amlogic/clk_measure.h
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _ARCH_MESON_MEASURE_H_
+#define _ARCH_MESON_MEASURE_H_
+
+unsigned long clk_util_clk_msr(unsigned long clk_mux);
+int clk_msr(int index);
+
+#endif
diff --git a/include/amlogic/color.h b/include/amlogic/color.h
index 9839d11..c16f80e 100644
--- a/include/amlogic/color.h
+++ b/include/amlogic/color.h
@@ -1,20 +1,7 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * include/linux/amlogic/vout/color.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
-*/
-
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _COLOR_H_
#define _COLOR_H_
diff --git a/include/amlogic/cpu_id.h b/include/amlogic/cpu_id.h
new file mode 100644
index 0000000..a0eda8a
--- /dev/null
+++ b/include/amlogic/cpu_id.h
@@ -0,0 +1,79 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#define MESON_CPU_MAJOR_ID_M6 0x16
+#define MESON_CPU_MAJOR_ID_M6TV 0x17
+#define MESON_CPU_MAJOR_ID_M6TVL 0x18
+#define MESON_CPU_MAJOR_ID_M8 0x19
+#define MESON_CPU_MAJOR_ID_MTVD 0x1A
+#define MESON_CPU_MAJOR_ID_M8B 0x1B
+#define MESON_CPU_MAJOR_ID_MG9TV 0x1C
+#define MESON_CPU_MAJOR_ID_M8M2 0x1D
+#define MESON_CPU_MAJOR_ID_GXBB 0x1F
+#define MESON_CPU_MAJOR_ID_GXTVBB 0x20
+#define MESON_CPU_MAJOR_ID_GXL 0x21
+#define MESON_CPU_MAJOR_ID_GXM 0x22
+#define MESON_CPU_MAJOR_ID_TXL 0x23
+#define MESON_CPU_MAJOR_ID_TXLX 0x24
+#define MESON_CPU_MAJOR_ID_AXG 0x25
+#define MESON_CPU_MAJOR_ID_GXLX 0x26
+#define MESON_CPU_MAJOR_ID_TXHD 0x27
+#define MESON_CPU_MAJOR_ID_G12A 0x28
+#define MESON_CPU_MAJOR_ID_G12B 0x29
+#define MESON_CPU_MAJOR_ID_SM1 0x2B
+#define MESON_CPU_MAJOR_ID_A1 0x2C
+#define MESON_CPU_MAJOR_ID_TL1 0x2E
+#define MESON_CPU_MAJOR_ID_TM2 0x2F
+#define MESON_CPU_MAJOR_ID_C1 0x30
+#define MESON_CPU_MAJOR_ID_SC2 0x32
+#define MESON_CPU_MAJOR_ID_C2 0x33
+#define MESON_CPU_MAJOR_ID_T5 0x34
+#define MESON_CPU_MAJOR_ID_T5D 0x35
+#define MESON_CPU_MAJOR_ID_T7 0x36
+#define MESON_CPU_MAJOR_ID_S4 0x37
+#define MESON_CPU_MAJOR_ID_T3 0x38
+
+#define MESON_CPU_PACKAGE_ID_905D 0X00
+#define MESON_CPU_PACKAGE_ID_905M 0x20
+#define MESON_CPU_PACKAGE_ID_905X 0X80
+#define MESON_CPU_PACKAGE_ID_905L 0XC0
+#define MESON_CPU_PACKAGE_ID_905M2 0XE0
+
+#define MESON_CPU_PACKAGE_ID_T962X 0x10
+#define MESON_CPU_PACKAGE_ID_T962E 0x20
+
+#define MESON_CPU_PACKAGE_ID_A113X 0x37
+#define MESON_CPU_PACKAGE_ID_A113D 0xD0
+
+#define MESON_CPU_CHIP_REVISION_A 0xA
+#define MESON_CPU_CHIP_REVISION_B 0xB
+#define MESON_CPU_CHIP_REVISION_C 0xC
+#define MESON_CPU_CHIP_REVISION_D 0xD
+
+typedef struct cpu_id {
+ unsigned int family_id:8;
+ unsigned int package_id:8;
+ unsigned int chip_rev:8; //RevA/RevB etc.
+ unsigned int reserve:4;
+ unsigned int layout_ver:4;
+} cpu_id_t;
+
+typedef struct chip_id {
+ unsigned int version;
+ unsigned char chipid[16];
+} chip_id_t;
+
+cpu_id_t get_cpu_id(void);
+
+extern chip_id_t aml_chip_id;
+int get_chip_id(unsigned char *buff, unsigned int size);
+
+/**
+ * TODO: Remove this API after move static system information to RO
+ * register or SRAM
+ *
+ * Should *NOT* call this API directly, always use get_chip_id()
+ */
+int __get_chip_id(unsigned char *buff, unsigned int size);
diff --git a/include/amlogic/enc_clk_config.h b/include/amlogic/enc_clk_config.h
index 8b13789..5c23c59 100644
--- a/include/amlogic/enc_clk_config.h
+++ b/include/amlogic/enc_clk_config.h
@@ -1 +1,5 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
diff --git a/include/amlogic/fb.h b/include/amlogic/fb.h
index ff324d7..c3b31db 100644
--- a/include/amlogic/fb.h
+++ b/include/amlogic/fb.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef _LINUX_FB_H
#define _LINUX_FB_H
@@ -288,6 +293,13 @@
#define VESA_HSYNC_SUSPEND 2
#define VESA_POWERDOWN 3
+#define CANVAS_ALIGNED(x) (((x) + 63) & ~63)
+
+enum osd_index_e {
+ OSD1 = 0,
+ OSD2,
+ VIU2_OSD1
+};
enum {
/* screen: unblanked, hsync: on, vsync: on */
diff --git a/include/amlogic/flash_ts.h b/include/amlogic/flash_ts.h
deleted file mode 100644
index 981b7d1..0000000
--- a/include/amlogic/flash_ts.h
+++ /dev/null
@@ -1,43 +0,0 @@
-/*
- * Flash-based transactional key-value store
- *
- * Copyright (C) 2010 Google, Inc.
- */
-#ifndef _FLASH_TS_H
-#define _FLASH_TS_H
-
-#include <fs.h>
-#include <linux/kernel.h>
-#include <linux/compat.h>
-
-#define DRV_NAME "fts"
-#define DRV_VERSION "0.999"
-
-#define CONFIG_FLASH_TS_PARTITION "fts"
-
-/* Keep in sync with 'struct flash_ts' */
-#define FLASH_TS_HDR_SIZE (4 * sizeof(u32))
-#define FLASH_TS_MAX_SIZE (16 * 1024)
-#define FLASH_TS_MAX_DATA_SIZE (FLASH_TS_MAX_SIZE - FLASH_TS_HDR_SIZE)
-
-#define FLASH_TS_MAGIC 0x53542a46
-
-/* Physical flash layout */
-struct flash_ts {
- u32 magic; /* "F*TS" */
- u32 crc; /* doesn't include magic and crc fields */
- u32 len; /* real size of data */
- u32 version; /* generation counter, must be positive */
-
- /* data format is very similar to Unix environment:
- * key1=value1\0key2=value2\0\0
- */
- char data[FLASH_TS_MAX_DATA_SIZE];
-};
-
-int flash_ts_init(void);
-void flash_ts_get(const char *key, char *value, unsigned int size);
-int flash_ts_set(const char *key, const char *value);
-int is_flash_inited(void);
-
-#endif /* _FLASH_TS_H */
diff --git a/include/amlogic/instaboot.h b/include/amlogic/instaboot.h
index cfcae9e..afacf38 100644
--- a/include/amlogic/instaboot.h
+++ b/include/amlogic/instaboot.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __INSTABOOT_H_
#define __INSTABOOT_H_
diff --git a/include/amlogic/jtag.h b/include/amlogic/jtag.h
new file mode 100644
index 0000000..d67e584
--- /dev/null
+++ b/include/amlogic/jtag.h
@@ -0,0 +1,67 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __MESON_JTAG_H__
+#define __MESON_JTAG_H__
+
+#define INVALID_ID -1
+
+/* ioctl command */
+#define JTAG_CLRPINMUX 0
+#define JTAG_SETPINMUX 1
+#define JTAG_EANBLE 2
+#define JTAG_DISABLE 3
+
+/* jtag type */
+#define JTAG_A 0
+#define JTAG_B 1
+#define SWD_A 2
+
+/* core type */
+#define AP 1 /* a35 a53 a72 ... */
+#define SCP 2 /* m3 */
+#define SP 3 /* m4 */
+#define DSPA 4 /* dsp-a */
+#define DSPB 5 /* dsp-b */
+#define DIF 6 /* dif */
+#define AOCPU 7 /* aocpu */
+#define AUCPU 8 /* aucpu */
+#define SOCBRG 9 /* SOC Bridge */
+
+/*
+ * bitmap for jtag select ID:
+ *
+ * |---|---|---|---|---|---|---|------|------|
+ * | 9 | 8 | 6 | 5 | 4 | 3 | 2 | 1 | 0 |
+ * |---|---|---|---|---|---|---|------|------|
+ * | core type | jtag type |cluster type |
+ * |---------------|-----------|-------------|
+ */
+#define CORE_TYPE_SHIFT 5
+#define JTAG_TYPE_SHIFT 2
+#define CLUSTER_TYPE_SHIFT 0
+
+#define CORE_TYPE_MASK 0xf
+#define JTAG_TYPE_MASK 0x7
+#define CLUSTER_TYPE_MASK 0x3
+
+#define JTAG_SELECT_ID(core_type, jtag_type, cluster_type) \
+ (((core_type & CORE_TYPE_MASK) << CORE_TYPE_SHIFT) |\
+ ((jtag_type & JTAG_TYPE_MASK) << JTAG_TYPE_SHIFT) |\
+ ((cluster_type & CLUSTER_TYPE_MASK) << CLUSTER_TYPE_SHIFT))
+
+#define CLUSTER_TYPE_UPDATE(id, cluster_type) \
+ ((id & (~(CLUSTER_TYPE_MASK))) | cluster_type)
+
+#define CORE_TYPE_GET(id) \
+ ((id >> CORE_TYPE_SHIFT) & CORE_TYPE_MASK)
+
+#define JTAG_TYPE_GET(id) \
+ ((id >> JTAG_TYPE_SHIFT) & JTAG_TYPE_MASK)
+
+#define CLUSTER_TYPE_GET(id) \
+ ((id >> CLUSTER_TYPE_SHIFT) & CLUSTER_TYPE_MASK)
+
+#endif /*_MESON_JTAG_H_*/
diff --git a/include/amlogic/keyunify.h b/include/amlogic/keyunify.h
index c89865f..c8c960f 100644
--- a/include/amlogic/keyunify.h
+++ b/include/amlogic/keyunify.h
@@ -1,14 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * \file keymanage.h
- * \brief API from drivers/keymange
- *
- * \version 1.0.0
- * \date 15/07/7
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2015 Amlogic. All Rights Reserved.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
+
#ifndef __KEYUNIFY_H__
#define __KEYUNIFY_H__
diff --git a/include/amlogic/leds_state.h b/include/amlogic/leds_state.h
new file mode 100644
index 0000000..3498460
--- /dev/null
+++ b/include/amlogic/leds_state.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+ /*
+ *
+ * Copyright (C) 2012 Amlogic, Inc.
+ *
+ * Author: jiayi.zhou@amlogic.com
+ *
+ */
+#ifndef _LEDS_STATE_H_
+#define _LEDS_STATE_H_
+
+#include <config.h>
+#include <common.h>
+#include <command.h>
+#include <asm/arch/mailbox.h>
+#include <asm/arch/secure_apb.h>
+
+#define MAXIMUM_BLINK_NUM 15
+#define MAXIMUM_HIGH_MS 50*63
+#define MAXIMUM_LOW_MS 50*63
+#define MAXIMUM_BREATH_ID 3
+
+
+enum LedState {
+ LED_STATE_DEFAULT = 0,
+ LED_STATE_BRIGHTNESS,
+ LED_STATE_BREATH,
+ LED_STATE_BLINK_ON,
+ LED_STATE_BLINK_OFF,
+ LED_STATE_BLINK_BREATH,
+ /* */
+ LED_STATE_BLINK_ON_HANDLE,
+ LED_STATE_BLINK_OFF_HANDLE,
+ LED_STATE_BLINK_BREATH_HANDLE,
+#if 0
+ /* TODO: */
+ LED_STATE_SET_MAX_BRIGHTNESS,
+ LED_STATE_SET_PINMUX,
+ LED_STATE_CLEAR_PINMUX,
+ LED_STATE_INFO,
+ LED_STATE_DEBUG,
+#endif
+ LED_STATE_INVALID,
+};
+
+enum led_brightness {
+ LED_OFF = 0,
+ LED_HALF = 127,
+ LED_FULL = 255,
+};
+
+uint32_t meson_ledstate_set_brightness(uint32_t led_id, uint32_t brightness);
+uint32_t meson_ledstate_set_breath(uint32_t led_id, uint32_t breath_id);
+
+/*to do:Parameters five and six are reserved parameters*/
+uint32_t meson_ledstate_set_blink_times_on(uint32_t led_id, uint32_t
+ blink_times, uint32_t blink_high, uint32_t blink_low,
+ uint32_t brightness_high, uint32_t brightness_low);
+uint32_t meson_ledstate_set_blink_times_off(uint32_t led_id,
+ uint32_t blink_times,uint32_t blink_high,uint32_t blink_low,
+ uint32_t brightness_high, uint32_t brightness_low);
+
+#endif
+/*to do*/
+#if 0
+uint32_t set_led_blink_times_breath(uint32_t led_id,uint32_t blink_times,
+ uint32_t blink_high,uint32_t blink_low );
+#endif
+
diff --git a/include/amlogic/media/dv/dolby_vision.h b/include/amlogic/media/dv/dolby_vision.h
new file mode 100644
index 0000000..cd29d6a
--- /dev/null
+++ b/include/amlogic/media/dv/dolby_vision.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _DOBLY_VISION_H_
+#define _DOBLY_VISION_H_
+
+
+
+#define EXT_MD_AVAIL_LEVEL_1 (1 << 0)
+#define EXT_MD_AVAIL_LEVEL_2 (1 << 1)
+#define EXT_MD_AVAIL_LEVEL_4 (1 << 2)
+#define EXT_MD_AVAIL_LEVEL_5 (1 << 3)
+#define EXT_MD_AVAIL_LEVEL_6 (1 << 4)
+#define EXT_MD_AVAIL_LEVEL_255 (1 << 31)
+
+#define DOLBY_VISION_OUTPUT_MODE_IPT 0
+#define DOLBY_VISION_OUTPUT_MODE_IPT_TUNNEL 1
+#define DOLBY_VISION_OUTPUT_MODE_HDR10 2
+#define DOLBY_VISION_OUTPUT_MODE_SDR10 3
+#define DOLBY_VISION_OUTPUT_MODE_SDR8 4
+#define DOLBY_VISION_OUTPUT_MODE_BYPASS 5
+
+#define DOLBY_VISION_LL_DISABLE 0
+#define DOLBY_VISION_LL_YUV422 1
+#define DOLBY_VISION_LL_RGB444 2
+
+
+#define DOLBY_VISION_SET_DISABLE "0"
+#define DOLBY_VISION_SET_STD "1"
+#define DOLBY_VISION_SET_LL_YUV "2"
+#define DOLBY_VISION_SET_LL_RGB "3"
+
+enum vpp_matrix_sel_e {
+ VPP_MATRIX_0 = 0, /* OSD convert matrix - new from GXL */
+ VPP_MATRIX_1, /* vd1 matrix before post-blend */
+ VPP_MATRIX_2, /* post matrix */
+ VPP_MATRIX_3, /* xvycc matrix */
+ VPP_MATRIX_4, /* in video eotf - new from GXL */
+ VPP_MATRIX_5, /* in osd eotf - new from GXL */
+ VPP_MATRIX_6 /* vd2 matrix before pre-blend */
+};
+#define NUM_MATRIX 6
+
+/* matrix names */
+#define VPP_MATRIX_OSD VPP_MATRIX_0
+#define VPP_MATRIX_VD1 VPP_MATRIX_1
+#define VPP_MATRIX_POST VPP_MATRIX_2
+#define VPP_MATRIX_XVYCC VPP_MATRIX_3
+#define VPP_MATRIX_EOTF VPP_MATRIX_4
+#define VPP_MATRIX_OSD_EOTF VPP_MATRIX_5
+#define VPP_MATRIX_VD2 VPP_MATRIX_6
+
+#define CSC_ON 1
+#define CSC_OFF 0
+
+enum mtx_en_e {
+ POST_MTX_EN = 0,
+ VD2_MTX_EN = 4,
+ VD1_MTX_EN,
+ XVY_MTX_EN,
+ OSD1_MTX_EN
+};
+
+struct dovi_mode_s {
+ u8 dv_rgb_444_8bit;
+ u8 ll_ycbcr_422_12bit;
+ u8 ll_rgb_444_10bit;
+ u8 ll_rgb_444_12bit;
+ u8 sup_2160p60hz;
+};
+
+#define POST_MTX_EN_MASK (1 << POST_MTX_EN)
+#define VD2_MTX_EN_MASK (1 << VD2_MTX_EN)
+#define VD1_MTX_EN_MASK (1 << VD1_MTX_EN)
+#define XVY_MTX_EN_MASK (1 << XVY_MTX_EN)
+#define OSD1_MTX_EN_MASK (1 << OSD1_MTX_EN)
+
+#define DEF_G2L_LUT_SIZE_2P 8
+#define DEF_G2L_LUT_SIZE (1 << DEF_G2L_LUT_SIZE_2P)
+
+
+void dolby_vision_process(void);
+void send_hdmi_pkt(void);
+int apply_stb_core_settings(void);
+unsigned int dv_read_reg(unsigned int addr);
+void dv_write_reg(unsigned int addr, unsigned int value);
+void dolbyvision_dump_setting(void);
+void dolbyvision_debug(int enable_debug);
+
+#ifdef CONFIG_AML_DOLBY
+extern int is_dolby_enable(void);
+extern bool request_ll_mode(void);
+extern bool check_dolby_vision_on(void);
+#else
+int __attribute__((weak))is_dolby_enable(void)
+{
+ return 0;
+}
+bool __attribute__((weak))request_ll_mode(void)
+{
+ return false;
+}
+bool __attribute__((weak))check_dolby_vision_on(void)
+{
+ return false;
+}
+#endif
+
+
+#endif
diff --git a/include/amlogic/media/dv/dolby_vision_func.h b/include/amlogic/media/dv/dolby_vision_func.h
new file mode 100644
index 0000000..9040d0b
--- /dev/null
+++ b/include/amlogic/media/dv/dolby_vision_func.h
@@ -0,0 +1,383 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _DV_H_
+#define _DV_H_
+
+#include <linux/types.h>
+
+#define DEF_G2L_LUT_SIZE_2P 8
+#define DEF_G2L_LUT_SIZE (1 << DEF_G2L_LUT_SIZE_2P)
+
+enum signal_format_e {
+ FORMAT_INVALID = -1,
+ FORMAT_DOVI = 0,
+ FORMAT_HDR10 = 1,
+ FORMAT_SDR = 2,
+ FORMAT_DOVI_LL = 3
+};
+
+enum priority_mode_e {
+ VIDEO_PRIORITY = 0,
+ GRAPHIC_PRIORITY = 1
+};
+
+enum cp_signal_range_e {
+ SIG_RANGE_SMPTE = 0, /* head range */
+ SIG_RANGE_FULL = 1, /* full range */
+ SIG_RANGE_SDI = 2 /* PQ */
+};
+
+enum graphics_format_e
+{
+ GF_SDR_YUV = 0, /* BT.709 YUV BT1886 */
+ GF_SDR_RGB = 1, /* BT.709 RGB BT1886 */
+ GF_HDR_YUV = 2, /* BT.2020 YUV PQ */
+ GF_HDR_RGB = 3 /* BT.2020 RGB PQ */
+};
+
+struct composer_register_ipcore_s {
+ uint32_t Composer_Mode;
+ uint32_t VDR_Resolution;
+ uint32_t Bit_Depth;
+ uint32_t Coefficient_Log2_Denominator;
+ uint32_t BL_Num_Pivots_Y;
+ uint32_t BL_Pivot[5];
+ uint32_t BL_Order;
+ uint32_t BL_Coefficient_Y[8][3];
+ uint32_t EL_NLQ_Offset_Y;
+ uint32_t EL_Coefficient_Y[3];
+ uint32_t Mapping_IDC_U;
+ uint32_t BL_Num_Pivots_U;
+ uint32_t BL_Pivot_U[3];
+ uint32_t BL_Order_U;
+ uint32_t BL_Coefficient_U[4][3];
+ uint32_t MMR_Coefficient_U[22][2];
+ uint32_t MMR_Order_U;
+ uint32_t EL_NLQ_Offset_U;
+ uint32_t EL_Coefficient_U[3];
+ uint32_t Mapping_IDC_V;
+ uint32_t BL_Num_Pivots_V;
+ uint32_t BL_Pivot_V[3];
+ uint32_t BL_Order_V;
+ uint32_t BL_Coefficient_V[4][3];
+ uint32_t MMR_Coefficient_V[22][2];
+ uint32_t MMR_Order_V;
+ uint32_t EL_NLQ_Offset_V;
+ uint32_t EL_Coefficient_V[3];
+};
+
+/** @brief DM registers for IPCORE 1 */
+struct dm_register_ipcore_1_s {
+ uint32_t SRange;
+ uint32_t Srange_Inverse;
+ uint32_t Frame_Format_1;
+ uint32_t Frame_Format_2;
+ uint32_t Frame_Pixel_Def;
+ uint32_t Y2RGB_Coefficient_1;
+ uint32_t Y2RGB_Coefficient_2;
+ uint32_t Y2RGB_Coefficient_3;
+ uint32_t Y2RGB_Coefficient_4;
+ uint32_t Y2RGB_Coefficient_5;
+ uint32_t Y2RGB_Offset_1;
+ uint32_t Y2RGB_Offset_2;
+ uint32_t Y2RGB_Offset_3;
+ uint32_t EOTF;
+ uint32_t A2B_Coefficient_1;
+ uint32_t A2B_Coefficient_2;
+ uint32_t A2B_Coefficient_3;
+ uint32_t A2B_Coefficient_4;
+ uint32_t A2B_Coefficient_5;
+ uint32_t C2D_Coefficient_1;
+ uint32_t C2D_Coefficient_2;
+ uint32_t C2D_Coefficient_3;
+ uint32_t C2D_Coefficient_4;
+ uint32_t C2D_Coefficient_5;
+ uint32_t C2D_Offset;
+ uint32_t Active_area_left_top;
+ uint32_t Active_area_bottom_right;
+};
+
+/** @brief DM registers for IPCORE 2 */
+struct dm_register_ipcore_2_s {
+ uint32_t SRange;
+ uint32_t Srange_Inverse;
+ uint32_t Y2RGB_Coefficient_1;
+ uint32_t Y2RGB_Coefficient_2;
+ uint32_t Y2RGB_Coefficient_3;
+ uint32_t Y2RGB_Coefficient_4;
+ uint32_t Y2RGB_Coefficient_5;
+ uint32_t Y2RGB_Offset_1;
+ uint32_t Y2RGB_Offset_2;
+ uint32_t Y2RGB_Offset_3;
+ uint32_t Frame_Format;
+ uint32_t EOTF;
+ uint32_t A2B_Coefficient_1;
+ uint32_t A2B_Coefficient_2;
+ uint32_t A2B_Coefficient_3;
+ uint32_t A2B_Coefficient_4;
+ uint32_t A2B_Coefficient_5;
+ uint32_t C2D_Coefficient_1;
+ uint32_t C2D_Coefficient_2;
+ uint32_t C2D_Coefficient_3;
+ uint32_t C2D_Coefficient_4;
+ uint32_t C2D_Coefficient_5;
+ uint32_t C2D_Offset;
+ uint32_t VDR_Resolution;
+};
+
+/** @brief DM registers for IPCORE 3 */
+struct dm_register_ipcore_3_s {
+ uint32_t D2C_coefficient_1;
+ uint32_t D2C_coefficient_2;
+ uint32_t D2C_coefficient_3;
+ uint32_t D2C_coefficient_4;
+ uint32_t D2C_coefficient_5;
+ uint32_t B2A_Coefficient_1;
+ uint32_t B2A_Coefficient_2;
+ uint32_t B2A_Coefficient_3;
+ uint32_t B2A_Coefficient_4;
+ uint32_t B2A_Coefficient_5;
+ uint32_t Eotf_param_1;
+ uint32_t Eotf_param_2;
+ uint32_t IPT_Scale;
+ uint32_t IPT_Offset_1;
+ uint32_t IPT_Offset_2;
+ uint32_t IPT_Offset_3;
+ uint32_t Output_range_1;
+ uint32_t Output_range_2;
+ uint32_t RGB2YUV_coefficient_register1;
+ uint32_t RGB2YUV_coefficient_register2;
+ uint32_t RGB2YUV_coefficient_register3;
+ uint32_t RGB2YUV_coefficient_register4;
+ uint32_t RGB2YUV_coefficient_register5;
+ uint32_t RGB2YUV_offset_0;
+ uint32_t RGB2YUV_offset_1;
+ uint32_t RGB2YUV_offset_2;
+};
+
+/** @brief DM luts for IPCORE 1 and 2 */
+struct dm_lut_ipcore_s {
+ uint32_t TmLutI[64*4];
+ uint32_t TmLutS[64*4];
+ uint32_t SmLutI[64*4];
+ uint32_t SmLutS[64*4];
+ uint32_t G2L[DEF_G2L_LUT_SIZE];
+};
+
+/** @brief hdmi metadata for IPCORE 3 */
+struct md_reister_ipcore_3_s {
+ uint32_t raw_metadata[512];
+ uint32_t size;
+};
+
+struct hdr_10_infoframe_s {
+ uint8_t infoframe_type_code;
+ uint8_t infoframe_version_number;
+ uint8_t length_of_info_frame;
+ uint8_t data_byte_1;
+ uint8_t data_byte_2;
+ uint8_t display_primaries_x_0_LSB;
+ uint8_t display_primaries_x_0_MSB;
+ uint8_t display_primaries_y_0_LSB;
+ uint8_t display_primaries_y_0_MSB;
+ uint8_t display_primaries_x_1_LSB;
+ uint8_t display_primaries_x_1_MSB;
+ uint8_t display_primaries_y_1_LSB;
+ uint8_t display_primaries_y_1_MSB;
+ uint8_t display_primaries_x_2_LSB;
+ uint8_t display_primaries_x_2_MSB;
+ uint8_t display_primaries_y_2_LSB;
+ uint8_t display_primaries_y_2_MSB;
+ uint8_t white_point_x_LSB;
+ uint8_t white_point_x_MSB;
+ uint8_t white_point_y_LSB;
+ uint8_t white_point_y_MSB;
+ uint8_t max_display_mastering_luminance_LSB;
+ uint8_t max_display_mastering_luminance_MSB;
+ uint8_t min_display_mastering_luminance_LSB;
+ uint8_t min_display_mastering_luminance_MSB;
+ uint8_t max_content_light_level_LSB;
+ uint8_t max_content_light_level_MSB;
+ uint8_t max_frame_average_light_level_LSB;
+ uint8_t max_frame_average_light_level_MSB;
+};
+
+struct hdr10_param_s {
+ uint32_t min_display_mastering_luminance;
+ uint32_t max_display_mastering_luminance;
+ uint16_t Rx;
+ uint16_t Ry;
+ uint16_t Gx;
+ uint16_t Gy;
+ uint16_t Bx;
+ uint16_t By;
+ uint16_t Wx;
+ uint16_t Wy;
+ uint16_t max_content_light_level;
+ uint16_t max_pic_average_light_level;
+};
+
+struct ext_level_1_s {
+ uint8_t min_PQ_hi;
+ uint8_t min_PQ_lo;
+ uint8_t max_PQ_hi;
+ uint8_t max_PQ_lo;
+ uint8_t avg_PQ_hi;
+ uint8_t avg_PQ_lo;
+};
+
+struct ext_level_2_s {
+ uint8_t target_max_PQ_hi;
+ uint8_t target_max_PQ_lo;
+ uint8_t trim_slope_hi;
+ uint8_t trim_slope_lo;
+ uint8_t trim_offset_hi;
+ uint8_t trim_offset_lo;
+ uint8_t trim_power_hi;
+ uint8_t trim_power_lo;
+ uint8_t trim_chroma_weight_hi;
+ uint8_t trim_chroma_weight_lo;
+ uint8_t trim_saturation_gain_hi;
+ uint8_t trim_saturation_gain_lo;
+ uint8_t ms_weight_hi;
+ uint8_t ms_weight_lo;
+};
+
+struct ext_level_4_s {
+ uint8_t anchor_PQ_hi;
+ uint8_t anchor_PQ_lo;
+ uint8_t anchor_power_hi;
+ uint8_t anchor_power_lo;
+};
+
+struct ext_level_5_s {
+ uint8_t active_area_left_offset_hi;
+ uint8_t active_area_left_offset_lo;
+ uint8_t active_area_right_offset_hi;
+ uint8_t active_area_right_offset_lo;
+ uint8_t active_area_top_offset_hi;
+ uint8_t active_area_top_offset_lo;
+ uint8_t active_area_bottom_offset_hi;
+ uint8_t active_area_bottom_offset_lo;
+};
+
+struct ext_level_6_s {
+ uint8_t max_display_mastering_luminance_hi;
+ uint8_t max_display_mastering_luminance_lo;
+ uint8_t min_display_mastering_luminance_hi;
+ uint8_t min_display_mastering_luminance_lo;
+ uint8_t max_content_light_level_hi;
+ uint8_t max_content_light_level_lo;
+ uint8_t max_frame_average_light_level_hi;
+ uint8_t max_frame_average_light_level_lo;
+};
+
+struct ext_level_255_s {
+ uint8_t dm_run_mode;
+ uint8_t dm_run_version;
+ uint8_t dm_debug0;
+ uint8_t dm_debug1;
+ uint8_t dm_debug2;
+ uint8_t dm_debug3;
+};
+
+struct ext_md_s {
+ uint32_t available_level_mask;
+ struct ext_level_1_s level_1;
+ struct ext_level_2_s level_2;
+ struct ext_level_4_s level_4;
+ struct ext_level_5_s level_5;
+ struct ext_level_6_s level_6;
+ struct ext_level_255_s level_255;
+};
+
+struct dovi_setting_s {
+ struct composer_register_ipcore_s comp_reg;
+ struct dm_register_ipcore_1_s dm_reg1;
+ struct dm_register_ipcore_2_s dm_reg2;
+ struct dm_register_ipcore_3_s dm_reg3;
+ struct dm_lut_ipcore_s dm_lut1;
+ struct dm_lut_ipcore_s dm_lut2;
+ /* for dovi output */
+ struct md_reister_ipcore_3_s md_reg3;
+ /* for hdr10 output */
+ struct hdr_10_infoframe_s hdr_info;
+ /* current process */
+ enum signal_format_e src_format;
+ enum signal_format_e dst_format;
+ /* enhanced layer */
+ bool el_flag;
+ bool el_halfsize_flag;
+ /* frame width & height */
+ uint32_t video_width;
+ uint32_t video_height;
+
+ /* use for stb 2.4 */
+ enum graphics_format_e g_format;
+ uint32_t g_bitdepth;
+ uint32_t dovi2hdr10_nomapping;
+ uint32_t use_ll_flag;
+ uint32_t ll_rgb_desired;
+ uint32_t diagnostic_enable;
+ uint32_t diagnostic_mux_select;
+ uint32_t dovi_ll_enable;
+ uint32_t vout_width;
+ uint32_t vout_height;
+ u8 vsvdb_tbl[32];
+ u8 hdrdb_tbl[7];
+ struct ext_md_s ext_md;
+ uint32_t vsvdb_len;
+ uint32_t vsvdb_changed;
+ uint32_t mode_changed;
+};
+
+
+extern int control_path(
+ enum signal_format_e in_format,
+ enum signal_format_e out_format,
+ char *in_comp, int in_comp_size,
+ char *in_md, int in_md_size,
+ enum priority_mode_e set_priority,
+ int set_bit_depth, int set_chroma_format, int set_yuv_range,
+ int set_graphic_min_lum, int set_graphic_max_lum,
+ int set_target_min_lum, int set_target_max_lum,
+ int set_no_el,
+ struct hdr10_param_s *hdr10_param,
+ struct dovi_setting_s *output);
+extern void *metadata_parser_init(int flag);
+extern int metadata_parser_reset(int flag);
+extern int metadata_parser_process(
+ char *src_rpu, int rpu_len,
+ char *dst_comp, int *comp_len,
+ char *dst_md, int *md_len, bool src_eos);
+extern void metadata_parser_release(void);
+
+struct dolby_vision_func_s {
+ const char *version_info;
+ void * (*metadata_parser_init)(int flag);
+ int (*metadata_parser_reset)(int flag);
+ int (*metadata_parser_process)(
+ char *src_rpu, int rpu_len,
+ char *dst_comp, int *comp_len,
+ char *dst_md, int *md_len, bool src_eos);
+ void (*metadata_parser_release)(void);
+ int (*control_path)(
+ enum signal_format_e in_format,
+ enum signal_format_e out_format,
+ char *in_comp, int in_comp_size,
+ char *in_md, int in_md_size,
+ enum priority_mode_e set_priority,
+ int set_bit_depth, int set_chroma_format, int set_yuv_range,
+ int set_graphic_min_lum, int set_graphic_max_lum,
+ int set_target_min_lum, int set_target_max_lum,
+ int set_no_el,
+ struct hdr10_param_s *hdr10_param,
+ struct dovi_setting_s *output);
+ int (*reserved_func)(void);
+};
+
+extern const struct dolby_vision_func_s DV_func;
+#endif
diff --git a/include/amlogic/media/vout/aml_cvbs.h b/include/amlogic/media/vout/aml_cvbs.h
index 9be92b1..60986b1 100644
--- a/include/amlogic/media/vout/aml_cvbs.h
+++ b/include/amlogic/media/vout/aml_cvbs.h
@@ -1,21 +1,18 @@
-#ifndef __AML_CVBS_H__
-#define __AML_CVBS_H__
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
-#define AML_CVBS_PERFORMANCE_COMPATIBILITY_SUPPORT 1
-
-#define AML_CVBS_CHINASARFT 0x0
-#define AML_CVBS_CHINATELECOM 0x1
-#define AML_CVBS_CHINAMOBILE 0x2
-#define AML_CVBS_PERFORMANCE_ACTIVED AML_CVBS_CHINASARFT
+#ifndef __INC_AML_CVBS_H__
+#define __INC_AML_CVBS_H__
void cvbs_init(void);
void cvbs_show_valid_vmode(void);
+unsigned int cvbs_outputmode_check(char *vmode_name, unsigned int frac);
int cvbs_set_vmode(char* vmode_name);
int cvbs_set_bist(char* bist_mode);
int cvbs_set_vdac(int status);
int cvbs_reg_debug(int argc, char* const argv[]);
-extern int cvbs_outputmode_check(char *vmode_name);
-
#endif
diff --git a/include/amlogic/media/vout/aml_vinfo.h b/include/amlogic/media/vout/aml_vinfo.h
index 7a453b2..96f8a13 100644
--- a/include/amlogic/media/vout/aml_vinfo.h
+++ b/include/amlogic/media/vout/aml_vinfo.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __AML_VINFO_H_
#define __AML_VINFO_H_
diff --git a/include/amlogic/media/vout/aml_vmode.h b/include/amlogic/media/vout/aml_vmode.h
index 738bcd7..17b01a8 100644
--- a/include/amlogic/media/vout/aml_vmode.h
+++ b/include/amlogic/media/vout/aml_vmode.h
@@ -1,3 +1,7 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __AML_VMODE_H_
#define __AML_VMODE_H_
diff --git a/include/amlogic/media/vout/aml_vout.h b/include/amlogic/media/vout/aml_vout.h
index b8dc27c..626471f 100644
--- a/include/amlogic/media/vout/aml_vout.h
+++ b/include/amlogic/media/vout/aml_vout.h
@@ -1,14 +1,33 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __AML_VOUT_H_
#define __AML_VOUT_H_
#include <amlogic/media/vout/aml_vinfo.h>
+#define VOUT_VIU1_SEL 1
+#define VOUT_VIU2_SEL 2
+#define VOUT_VIU3_SEL 3
+
+enum viu_mux_e {
+ VIU_MUX_ENCL = 0,
+ VIU_MUX_ENCI,
+ VIU_MUX_ENCP,
+ VIU_MUX_MAX,
+};
+
void vout_init(void);
void vout_vinfo_dump(void);
int vout_get_current_vmode(void);
int vout_get_current_axis(int *axis);
void vout_set_current_vmode(int mode);
struct vinfo_s *vout_get_current_vinfo(void);
+void vout_viu_mux(int index, unsigned int mux_sel);
extern unsigned long get_fb_addr(void);
+
+void vout_probe(void);
#endif
diff --git a/include/amlogic/media/vout/hdmitx.h b/include/amlogic/media/vout/hdmitx.h
deleted file mode 100644
index c8b6bc9..0000000
--- a/include/amlogic/media/vout/hdmitx.h
+++ /dev/null
@@ -1,430 +0,0 @@
-#ifndef __HDMI_H__
-#define __HDMI_H__
-
-/* Little-Endian format */
-enum scdc_addr {
- SINK_VER = 0x01,
- SOURCE_VER, /* RW */
- UPDATE_0 = 0x10, /* RW */
- UPDATE_1, /* RW */
- TMDS_CFG = 0x20, /* RW */
- SCRAMBLER_ST,
- CONFIG_0 = 0x30, /* RW */
- STATUS_FLAGS_0 = 0x40,
- STATUS_FLAGS_1,
- ERR_DET_0_L = 0x50,
- ERR_DET_0_H,
- ERR_DET_1_L,
- ERR_DET_1_H,
- ERR_DET_2_L,
- ERR_DET_2_H,
- ERR_DET_CHKSUM,
- TEST_CONFIG_0 = 0xC0, /* RW */
- MANUFACT_IEEE_OUI_2 = 0xD0,
- MANUFACT_IEEE_OUI_1,
- MANUFACT_IEEE_OUI_0,
- DEVICE_ID = 0xD3, /* 0xD3 ~ 0xDD */
- /* RW 0xDE ~ 0xFF */
- MANUFACT_SPECIFIC = 0xDE,
-};
-
-#define HDMITX_VIC420_OFFSET 0x100
-#define HDMITX_VESA_OFFSET 0x300
-
-/* HDMI VIC definitions */
-enum hdmi_vic {
- /* Refer to CEA 861-D */
- HDMI_unkown = 0,
- HDMI_640x480p60_4x3 = 1,
- HDMI_720x480p60_4x3 = 2,
- HDMI_720x480p60_16x9 = 3,
- HDMI_1280x720p60_16x9 = 4,
- HDMI_1920x1080i60_16x9 = 5,
- HDMI_720x480i60_4x3 = 6,
- HDMI_720x480i60_16x9 = 7,
- HDMI_720x240p60_4x3 = 8,
- HDMI_720x240p60_16x9 = 9,
- HDMI_2880x480i60_4x3 = 10,
- HDMI_2880x480i60_16x9 = 11,
- HDMI_2880x240p60_4x3 = 12,
- HDMI_2880x240p60_16x9 = 13,
- HDMI_1440x480p60_4x3 = 14,
- HDMI_1440x480p60_16x9 = 15,
- HDMI_1920x1080p60_16x9 = 16,
- HDMI_720x576p50_4x3 = 17,
- HDMI_720x576p50_16x9 = 18,
- HDMI_1280x720p50_16x9 = 19,
- HDMI_1920x1080i50_16x9 = 20,
- HDMI_720x576i50_4x3 = 21,
- HDMI_720x576i50_16x9 = 22,
- HDMI_720x288p_4x3 = 23,
- HDMI_720x288p_16x9 = 24,
- HDMI_2880x576i50_4x3 = 25,
- HDMI_2880x576i50_16x9 = 26,
- HDMI_2880x288p50_4x3 = 27,
- HDMI_2880x288p50_16x9 = 28,
- HDMI_1440x576p_4x3 = 29,
- HDMI_1440x576p_16x9 = 30,
- HDMI_1920x1080p50_16x9 = 31,
- HDMI_1920x1080p24_16x9 = 32,
- HDMI_1920x1080p25_16x9 = 33,
- HDMI_1920x1080p30_16x9 = 34,
- HDMI_2880x480p60_4x3 = 35,
- HDMI_2880x480p60_16x9 = 36,
- HDMI_2880x576p50_4x3 = 37,
- HDMI_2880x576p50_16x9 = 38,
- HDMI_1920x1080i_t1250_50_16x9 = 39,
- HDMI_1920x1080i100_16x9 = 40,
- HDMI_1280x720p100_16x9 = 41,
- HDMI_720x576p100_4x3 = 42,
- HDMI_720x576p100_16x9 = 43,
- HDMI_720x576i100_4x3 = 44,
- HDMI_720x576i100_16x9 = 45,
- HDMI_1920x1080i120_16x9 = 46,
- HDMI_1280x720p120_16x9 = 47,
- HDMI_720x480p120_4x3 = 48,
- HDMI_720x480p120_16x9 = 49,
- HDMI_720x480i120_4x3 = 50,
- HDMI_720x480i120_16x9 = 51,
- HDMI_720x576p200_4x3 = 52,
- HDMI_720x576p200_16x9 = 53,
- HDMI_720x576i200_4x3 = 54,
- HDMI_720x576i200_16x9 = 55,
- HDMI_720x480p240_4x3 = 56,
- HDMI_720x480p240_16x9 = 57,
- HDMI_720x480i240_4x3 = 58,
- HDMI_720x480i240_16x9 = 59,
- /* Refet to CEA 861-F */
- HDMI_1280x720p24_16x9 = 60,
- HDMI_1280x720p25_16x9 = 61,
- HDMI_1280x720p30_16x9 = 62,
- HDMI_1920x1080p120_16x9 = 63,
- HDMI_1920x1080p100_16x9 = 64,
- HDMI_1280x720p24_64x27 = 65,
- HDMI_1280x720p25_64x27 = 66,
- HDMI_1280x720p30_64x27 = 67,
- HDMI_1280x720p50_64x27 = 68,
- HDMI_1280x720p60_64x27 = 69,
- HDMI_1280x720p100_64x27 = 70,
- HDMI_1280x720p120_64x27 = 71,
- HDMI_1920x1080p24_64x27 = 72,
- HDMI_1920x1080p25_64x27 = 73,
- HDMI_1920x1080p30_64x27 = 74,
- HDMI_1920x1080p50_64x27 = 75,
- HDMI_1920x1080p60_64x27 = 76,
- HDMI_1920x1080p100_64x27 = 77,
- HDMI_1920x1080p120_64x27 = 78,
- HDMI_1680x720p24_64x27 = 79,
- HDMI_1680x720p25_64x27 = 80,
- HDMI_1680x720p30_64x27 = 81,
- HDMI_1680x720p50_64x27 = 82,
- HDMI_1680x720p60_64x27 = 83,
- HDMI_1680x720p100_64x27 = 84,
- HDMI_1680x720p120_64x27 = 85,
- HDMI_2560x1080p24_64x27 = 86,
- HDMI_2560x1080p25_64x27 = 87,
- HDMI_2560x1080p30_64x27 = 88,
- HDMI_2560x1080p50_64x27 = 89,
- HDMI_2560x1080p60_64x27 = 90,
- HDMI_2560x1080p100_64x27 = 91,
- HDMI_2560x1080p120_64x27 = 92,
- HDMI_3840x2160p24_16x9 = 93,
- HDMI_3840x2160p25_16x9 = 94,
- HDMI_3840x2160p30_16x9 = 95,
- HDMI_3840x2160p50_16x9 = 96,
- HDMI_3840x2160p60_16x9 = 97,
- HDMI_4096x2160p24_256x135 = 98,
- HDMI_4096x2160p25_256x135 = 99,
- HDMI_4096x2160p30_256x135 = 100,
- HDMI_4096x2160p50_256x135 = 101,
- HDMI_4096x2160p60_256x135 = 102,
- HDMI_3840x2160p24_64x27 = 103,
- HDMI_3840x2160p25_64x27 = 104,
- HDMI_3840x2160p30_64x27 = 105,
- HDMI_3840x2160p50_64x27 = 106,
- HDMI_3840x2160p60_64x27 = 107,
- HDMI_RESERVED = 108,
- /*
- the following vic is for those y420 mode
- they are all beyond OFFSET_HDMITX_VIC420(0x1000)
- and they has same vic with normal vic in the lower bytes.
- */
- HDMI_VIC_Y420 = HDMITX_VIC420_OFFSET,
- HDMI_3840x2160p50_16x9_Y420 =
- HDMITX_VIC420_OFFSET + HDMI_3840x2160p50_16x9,
- HDMI_3840x2160p60_16x9_Y420 =
- HDMITX_VIC420_OFFSET + HDMI_3840x2160p60_16x9,
- HDMI_4096x2160p50_256x135_Y420 =
- HDMITX_VIC420_OFFSET + HDMI_4096x2160p50_256x135,
- HDMI_4096x2160p60_256x135_Y420 =
- HDMITX_VIC420_OFFSET + HDMI_4096x2160p60_256x135,
- HDMI_3840x2160p50_64x27_Y420 =
- HDMITX_VIC420_OFFSET + HDMI_3840x2160p50_64x27,
- HDMI_3840x2160p60_64x27_Y420 =
- HDMITX_VIC420_OFFSET + HDMI_3840x2160p60_64x27,
- HDMIV_640x480p60hz = HDMITX_VESA_OFFSET,
- HDMIV_800x480p60hz,
- HDMIV_800x600p60hz,
- HDMIV_852x480p60hz,
- HDMIV_854x480p60hz,
- HDMIV_1024x600p60hz,
- HDMIV_1024x768p60hz,
- HDMIV_1152x864p75hz,
- HDMIV_1280x600p60hz,
- HDMIV_1280x768p60hz,
- HDMIV_1280x800p60hz,
- HDMIV_1280x960p60hz,
- HDMIV_1280x1024p60hz,
- HDMIV_1360x768p60hz,
- HDMIV_1366x768p60hz,
- HDMIV_1400x1050p60hz,
- HDMIV_1440x900p60hz,
- HDMIV_1440x2560p60hz,
- HDMIV_1440x2560p70hz,
- HDMIV_1600x900p60hz,
- HDMIV_1600x1200p60hz,
- HDMIV_1680x1050p60hz,
- HDMIV_1920x1200p60hz,
- HDMIV_2160x1200p90hz,
- HDMIV_2560x1080p60hz,
- HDMIV_2560x1440p60hz,
- HDMIV_2560x1600p60hz,
- HDMIV_3440x1440p60hz,
-};
-
-/* CEA TIMING STRUCT DEFINITION */
-struct hdmi_cea_timing {
- unsigned int pixel_freq; /* Unit: 1000 */
- unsigned int h_freq; /* Unit: Hz */
- unsigned int v_freq; /* Unit: 0.001 Hz */
- unsigned int vsync_polarity:1; /* 1: positive 0: negative */
- unsigned int hsync_polarity:1;
- unsigned short h_active;
- unsigned short h_total;
- unsigned short h_blank;
- unsigned short h_front;
- unsigned short h_sync;
- unsigned short h_back;
- unsigned short v_active;
- unsigned short v_total;
- unsigned short v_blank;
- unsigned short v_front;
- unsigned short v_sync;
- unsigned short v_back;
- unsigned short v_sync_ln;
-};
-
-/* Refer CEA861-D Page 116 Table 55 */
-struct dtd {
- unsigned short pixel_clock;
- unsigned short h_active;
- unsigned short h_blank;
- unsigned short v_active;
- unsigned short v_blank;
- unsigned short h_sync_offset;
- unsigned short h_sync;
- unsigned short v_sync_offset;
- unsigned short v_sync;
- unsigned char h_image_size;
- unsigned char v_image_size;
- unsigned char h_border;
- unsigned char v_border;
- unsigned char flags;
- enum hdmi_vic vic;
-};
-
-#define VIC_MAX_NUM 256
-struct rx_cap {
- unsigned int native_Mode;
- /*video*/
- unsigned int VIC[VIC_MAX_NUM];
- unsigned int VIC_count;
- unsigned int native_VIC;
- /*vendor*/
- unsigned int IEEEOUI;
- unsigned int Max_TMDS_Clock1; /* HDMI1.4b TMDS_CLK */
- unsigned int HF_IEEEOUI; /* For HDMI Forum */
- unsigned int Max_TMDS_Clock2; /* HDMI2.0 TMDS_CLK */
- /* CEA861-F, Table 56, Colorimetry Data Block */
- unsigned int colorimetry_data;
- unsigned int scdc_present:1;
- unsigned int scdc_rr_capable:1; /* SCDC read request */
- unsigned int lte_340mcsc_scramble:1;
- unsigned int dc_y444:1;
- unsigned int dc_30bit:1;
- unsigned int dc_36bit:1;
- unsigned int dc_48bit:1;
- unsigned int dc_30bit_420:1;
- unsigned int dc_36bit_420:1;
- unsigned int dc_48bit_420:1;
- unsigned char edid_version;
- unsigned char edid_revision;
- unsigned int ColorDeepSupport;
- unsigned int Video_Latency;
- unsigned int Audio_Latency;
- unsigned int Interlaced_Video_Latency;
- unsigned int Interlaced_Audio_Latency;
- unsigned int threeD_present;
- unsigned int threeD_Multi_present;
- unsigned int hdmi_vic_LEN;
- enum hdmi_vic preferred_mode;
- struct dtd dtd[16];
- unsigned char dtd_idx;
- unsigned char flag_vfpdb;
- unsigned char number_of_dtd;
- unsigned char pref_colorspace;
- /*blk0 check sum*/
- unsigned char chksum;
-};
-
-enum hdmi_color_depth {
- HDMI_COLOR_DEPTH_24B = 4,
- HDMI_COLOR_DEPTH_30B = 5,
- HDMI_COLOR_DEPTH_36B = 6,
- HDMI_COLOR_DEPTH_48B = 7,
-};
-
-enum hdmi_color_format {
- HDMI_COLOR_FORMAT_RGB,
- HDMI_COLOR_FORMAT_444,
- HDMI_COLOR_FORMAT_422,
- HDMI_COLOR_FORMAT_420,
-};
-
-enum hdmi_color_range {
- HDMI_COLOR_RANGE_LIM,
- HDMI_COLOR_RANGE_FUL,
-};
-
-enum hdmi_audio_packet {
- HDMI_AUDIO_PACKET_SMP = 0x02,
- HDMI_AUDIO_PACKET_1BT = 0x07,
- HDMI_AUDIO_PACKET_DST = 0x08,
- HDMI_AUDIO_PACKET_HBR = 0x09,
-};
-
-/* get hdmi cea timing
- * t: struct hdmi_cea_timing *
- */
-#define GET_TIMING(name) (t->name)
-
-struct parse_cd {
- enum hdmi_color_depth cd;
- const char *name;
-};
-
-struct parse_cs {
- enum hdmi_color_format cs;
- const char *name;
-};
-
-struct parse_cr {
- enum hdmi_color_format cr;
- const char *name;
-};
-
-#define EDID_BLK_NO 4
-#define EDID_BLK_SIZE 128
-struct hdmi_format_para {
- enum hdmi_vic vic;
- char *name; /* full name, 1280x720p60hz */
- char *sname; /* short name, 1280x720p60hz -> 720p60hz */
- char ext_name[32];
- enum hdmi_color_depth cd; /* cd8, cd10 or cd12 */
- enum hdmi_color_format cs; /* rgb, y444, y422, y420 */
- enum hdmi_color_range cr; /* limit, full */
- unsigned int pixel_repetition_factor;
- unsigned int progress_mode:1; /* 0: Interlace 1: Progressive */
- unsigned int scrambler_en:1;
- unsigned int tmds_clk_div40:1;
- unsigned int tmds_clk; /* Unit: 1000 */
- struct hdmi_cea_timing timing;
-};
-
-struct hdmi_support_mode {
- enum hdmi_vic vic;
- char *sname;
- char y420;
-};
-
-struct hdmitx_dev {
- unsigned char rx_edid[512]; /* some RX may exceeds 256Bytes */
- struct {
- int (*get_hpd_state)(void);
- int (*read_edid)(unsigned char *buf, unsigned char addr,
- unsigned char blk_no);
- void (*turn_off)(void);
- void (*list_support_modes)(void);
- void (*dump_regs)(void);
- void (*test_bist)(unsigned int mode);
- void (*output_blank)(unsigned int blank);
- } HWOp;
- unsigned char rawedid[EDID_BLK_SIZE * EDID_BLK_NO];
- struct rx_cap RXCap;
- struct hdmi_format_para *para;
- enum hdmi_vic vic;
- unsigned int frac_rate_policy;
- unsigned int mode420;
- unsigned int dc30;
-};
-
-extern struct hdmi_format_para *hdmi_get_fmt_paras(enum hdmi_vic vic);
-extern enum hdmi_vic hdmi_get_fmt_vic(char const *name);
-extern void hdmi_parse_attr(struct hdmi_format_para *para, char const *name);
-extern void hdmi_tx_set(struct hdmitx_dev *hdev);
-/* Parsing RAW EDID data from edid to pRXCap */
-extern unsigned int hdmi_edid_parsing(unsigned char *edid, struct rx_cap *pRXCap);
-extern struct hdmi_format_para *hdmi_match_dtd_paras(struct dtd *t);
-
-
-
-
-/*These functions below are different in chip level*/
-
-/*READ/WRITE REGISTERS*/
-extern unsigned long hd_read_reg(volatile unsigned int* addr);
-extern void hd_write_reg(volatile unsigned int* addr, unsigned long val);
-extern void hd_set_reg_bits(volatile unsigned int* addr, unsigned long value,
- unsigned long offset, unsigned long len);
-extern unsigned int hdmitx_rd_reg(unsigned int addr);
-extern void hdmitx_wr_reg(unsigned int addr, unsigned int data);
-extern void hdmitx_set_reg_bits(unsigned int addr, unsigned int value,
- unsigned int offset, unsigned int len);
-extern void hdmitx_poll_reg(unsigned int addr, unsigned int val,
- unsigned long timeout);
-extern void hdmitx_rd_check_reg (unsigned long addr,
- unsigned long exp_data, unsigned long mask);
-/*PHY*/
-extern void hdmitx_set_phy(struct hdmitx_dev *hdev);
-extern void hdmitx_turnoff(void);
-/*PLL*/
-extern void set_hpll_clk_out(unsigned clk, struct hdmitx_dev *hdev);
-/*OD1 OD2 OD3*/
-extern void set_hpll_od1(unsigned div);
-extern void set_hpll_od2(unsigned div);
-extern void set_hpll_od3(unsigned div);
-/*SSPLL*/
-extern void set_hpll_sspll(struct hdmitx_dev *hdev);
-/*DDC CHANNEL*/
-extern void ddc_pinmux_init(void);
-/*HPD*/
-extern int hdmitx_get_hpd_state(void);
-/*PRBS*/
-extern void hdmitx_prbs(void);
-/*APB3 bus for hdmitx DWC/TOP registers*/
-extern void hdmitx_enable_apb3(void);
-
-/*hdmitx init by called in board.c*/
-extern void hdmi_tx_init(void);
-extern int hdmi_outputmode_check(char *mode);
-
-extern struct hdmitx_dev hdmitx_device;
-
-#ifndef printk
-#define printk printf
-#endif
-#ifndef pr_info
-#define pr_info printf
-#endif
-
-#endif
diff --git a/include/amlogic/media/vout/hdmitx/hdmi_common.h b/include/amlogic/media/vout/hdmitx/hdmi_common.h
new file mode 100644
index 0000000..f607617
--- /dev/null
+++ b/include/amlogic/media/vout/hdmitx/hdmi_common.h
@@ -0,0 +1,688 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __HDMI_COMMON_H__
+#define __HDMI_COMMON_H__
+
+/* Little-Endian format */
+enum scdc_addr {
+ SINK_VER = 0x01,
+ SOURCE_VER, /* RW */
+ UPDATE_0 = 0x10, /* RW */
+ UPDATE_1, /* RW */
+ TMDS_CFG = 0x20, /* RW */
+ SCRAMBLER_ST,
+ CONFIG_0 = 0x30, /* RW */
+ STATUS_FLAGS_0 = 0x40,
+ STATUS_FLAGS_1,
+ ERR_DET_0_L = 0x50,
+ ERR_DET_0_H,
+ ERR_DET_1_L,
+ ERR_DET_1_H,
+ ERR_DET_2_L,
+ ERR_DET_2_H,
+ ERR_DET_CHKSUM,
+ TEST_CONFIG_0 = 0xC0, /* RW */
+ MANUFACT_IEEE_OUI_2 = 0xD0,
+ MANUFACT_IEEE_OUI_1,
+ MANUFACT_IEEE_OUI_0,
+ DEVICE_ID = 0xD3, /* 0xD3 ~ 0xDD */
+ /* RW 0xDE ~ 0xFF */
+ MANUFACT_SPECIFIC = 0xDE,
+};
+
+#define HDMITX_VIC420_OFFSET 0x100
+#define HDMITX_VESA_OFFSET 0x300
+
+/* HDMI VIC definitions */
+enum hdmi_vic {
+ /* Refer to CEA 861-D */
+ HDMI_unkown = 0,
+ HDMI_640x480p60_4x3 = 1,
+ HDMI_720x480p60_4x3 = 2,
+ HDMI_720x480p60_16x9 = 3,
+ HDMI_1280x720p60_16x9 = 4,
+ HDMI_1920x1080i60_16x9 = 5,
+ HDMI_720x480i60_4x3 = 6,
+ HDMI_720x480i60_16x9 = 7,
+ HDMI_720x240p60_4x3 = 8,
+ HDMI_720x240p60_16x9 = 9,
+ HDMI_2880x480i60_4x3 = 10,
+ HDMI_2880x480i60_16x9 = 11,
+ HDMI_2880x240p60_4x3 = 12,
+ HDMI_2880x240p60_16x9 = 13,
+ HDMI_1440x480p60_4x3 = 14,
+ HDMI_1440x480p60_16x9 = 15,
+ HDMI_1920x1080p60_16x9 = 16,
+ HDMI_720x576p50_4x3 = 17,
+ HDMI_720x576p50_16x9 = 18,
+ HDMI_1280x720p50_16x9 = 19,
+ HDMI_1920x1080i50_16x9 = 20,
+ HDMI_720x576i50_4x3 = 21,
+ HDMI_720x576i50_16x9 = 22,
+ HDMI_720x288p_4x3 = 23,
+ HDMI_720x288p_16x9 = 24,
+ HDMI_2880x576i50_4x3 = 25,
+ HDMI_2880x576i50_16x9 = 26,
+ HDMI_2880x288p50_4x3 = 27,
+ HDMI_2880x288p50_16x9 = 28,
+ HDMI_1440x576p_4x3 = 29,
+ HDMI_1440x576p_16x9 = 30,
+ HDMI_1920x1080p50_16x9 = 31,
+ HDMI_1920x1080p24_16x9 = 32,
+ HDMI_1920x1080p25_16x9 = 33,
+ HDMI_1920x1080p30_16x9 = 34,
+ HDMI_2880x480p60_4x3 = 35,
+ HDMI_2880x480p60_16x9 = 36,
+ HDMI_2880x576p50_4x3 = 37,
+ HDMI_2880x576p50_16x9 = 38,
+ HDMI_1920x1080i_t1250_50_16x9 = 39,
+ HDMI_1920x1080i100_16x9 = 40,
+ HDMI_1280x720p100_16x9 = 41,
+ HDMI_720x576p100_4x3 = 42,
+ HDMI_720x576p100_16x9 = 43,
+ HDMI_720x576i100_4x3 = 44,
+ HDMI_720x576i100_16x9 = 45,
+ HDMI_1920x1080i120_16x9 = 46,
+ HDMI_1280x720p120_16x9 = 47,
+ HDMI_720x480p120_4x3 = 48,
+ HDMI_720x480p120_16x9 = 49,
+ HDMI_720x480i120_4x3 = 50,
+ HDMI_720x480i120_16x9 = 51,
+ HDMI_720x576p200_4x3 = 52,
+ HDMI_720x576p200_16x9 = 53,
+ HDMI_720x576i200_4x3 = 54,
+ HDMI_720x576i200_16x9 = 55,
+ HDMI_720x480p240_4x3 = 56,
+ HDMI_720x480p240_16x9 = 57,
+ HDMI_720x480i240_4x3 = 58,
+ HDMI_720x480i240_16x9 = 59,
+ /* Refet to CEA 861-F */
+ HDMI_1280x720p24_16x9 = 60,
+ HDMI_1280x720p25_16x9 = 61,
+ HDMI_1280x720p30_16x9 = 62,
+ HDMI_1920x1080p120_16x9 = 63,
+ HDMI_1920x1080p100_16x9 = 64,
+ HDMI_1280x720p24_64x27 = 65,
+ HDMI_1280x720p25_64x27 = 66,
+ HDMI_1280x720p30_64x27 = 67,
+ HDMI_1280x720p50_64x27 = 68,
+ HDMI_1280x720p60_64x27 = 69,
+ HDMI_1280x720p100_64x27 = 70,
+ HDMI_1280x720p120_64x27 = 71,
+ HDMI_1920x1080p24_64x27 = 72,
+ HDMI_1920x1080p25_64x27 = 73,
+ HDMI_1920x1080p30_64x27 = 74,
+ HDMI_1920x1080p50_64x27 = 75,
+ HDMI_1920x1080p60_64x27 = 76,
+ HDMI_1920x1080p100_64x27 = 77,
+ HDMI_1920x1080p120_64x27 = 78,
+ HDMI_1680x720p24_64x27 = 79,
+ HDMI_1680x720p25_64x27 = 80,
+ HDMI_1680x720p30_64x27 = 81,
+ HDMI_1680x720p50_64x27 = 82,
+ HDMI_1680x720p60_64x27 = 83,
+ HDMI_1680x720p100_64x27 = 84,
+ HDMI_1680x720p120_64x27 = 85,
+ HDMI_2560x1080p24_64x27 = 86,
+ HDMI_2560x1080p25_64x27 = 87,
+ HDMI_2560x1080p30_64x27 = 88,
+ HDMI_2560x1080p50_64x27 = 89,
+ HDMI_2560x1080p60_64x27 = 90,
+ HDMI_2560x1080p100_64x27 = 91,
+ HDMI_2560x1080p120_64x27 = 92,
+ HDMI_3840x2160p24_16x9 = 93,
+ HDMI_3840x2160p25_16x9 = 94,
+ HDMI_3840x2160p30_16x9 = 95,
+ HDMI_3840x2160p50_16x9 = 96,
+ HDMI_3840x2160p60_16x9 = 97,
+ HDMI_4096x2160p24_256x135 = 98,
+ HDMI_4096x2160p25_256x135 = 99,
+ HDMI_4096x2160p30_256x135 = 100,
+ HDMI_4096x2160p50_256x135 = 101,
+ HDMI_4096x2160p60_256x135 = 102,
+ HDMI_3840x2160p24_64x27 = 103,
+ HDMI_3840x2160p25_64x27 = 104,
+ HDMI_3840x2160p30_64x27 = 105,
+ HDMI_3840x2160p50_64x27 = 106,
+ HDMI_3840x2160p60_64x27 = 107,
+ HDMI_RESERVED = 108,
+ /*
+ the following vic is for those y420 mode
+ they are all beyond OFFSET_HDMITX_VIC420(0x1000)
+ and they has same vic with normal vic in the lower bytes.
+ */
+ HDMI_VIC_Y420 = HDMITX_VIC420_OFFSET,
+ HDMI_3840x2160p50_16x9_Y420 =
+ HDMITX_VIC420_OFFSET + HDMI_3840x2160p50_16x9,
+ HDMI_3840x2160p60_16x9_Y420 =
+ HDMITX_VIC420_OFFSET + HDMI_3840x2160p60_16x9,
+ HDMI_4096x2160p50_256x135_Y420 =
+ HDMITX_VIC420_OFFSET + HDMI_4096x2160p50_256x135,
+ HDMI_4096x2160p60_256x135_Y420 =
+ HDMITX_VIC420_OFFSET + HDMI_4096x2160p60_256x135,
+ HDMI_3840x2160p50_64x27_Y420 =
+ HDMITX_VIC420_OFFSET + HDMI_3840x2160p50_64x27,
+ HDMI_3840x2160p60_64x27_Y420 =
+ HDMITX_VIC420_OFFSET + HDMI_3840x2160p60_64x27,
+ HDMIV_640x480p60hz = HDMITX_VESA_OFFSET,
+ HDMIV_800x480p60hz,
+ HDMIV_800x600p60hz,
+ HDMIV_852x480p60hz,
+ HDMIV_854x480p60hz,
+ HDMIV_1024x600p60hz,
+ HDMIV_1024x768p60hz,
+ HDMIV_1152x864p75hz,
+ HDMIV_1280x600p60hz,
+ HDMIV_1280x768p60hz,
+ HDMIV_1280x800p60hz,
+ HDMIV_1280x960p60hz,
+ HDMIV_1280x1024p60hz,
+ HDMIV_1360x768p60hz,
+ HDMIV_1366x768p60hz,
+ HDMIV_1400x1050p60hz,
+ HDMIV_1440x900p60hz,
+ HDMIV_1440x2560p60hz,
+ HDMIV_1440x2560p70hz,
+ HDMIV_1600x900p60hz,
+ HDMIV_1600x1200p60hz,
+ HDMIV_1680x1050p60hz,
+ HDMIV_1920x1200p60hz,
+ HDMIV_2160x1200p90hz,
+ HDMIV_2560x1080p60hz,
+ HDMIV_2560x1440p60hz,
+ HDMIV_2560x1600p60hz,
+ HDMIV_3440x1440p60hz,
+ HDMIV_2400x1200p90hz,
+};
+
+/* Compliance with old definitions */
+#define HDMI_640x480p60 HDMI_640x480p60_4x3
+#define HDMI_480p60 HDMI_720x480p60_4x3
+#define HDMI_480p60_16x9 HDMI_720x480p60_16x9
+#define HDMI_720p60 HDMI_1280x720p60_16x9
+#define HDMI_1080i60 HDMI_1920x1080i60_16x9
+#define HDMI_480i60 HDMI_720x480i60_4x3
+#define HDMI_480i60_16x9 HDMI_720x480i60_16x9
+#define HDMI_480i60_16x9_rpt HDMI_2880x480i60_16x9
+#define HDMI_1440x480p60 HDMI_1440x480p60_4x3
+#define HDMI_1440x480p60_16x9 HDMI_1440x480p60_16x9
+#define HDMI_1080p60 HDMI_1920x1080p60_16x9
+#define HDMI_576p50 HDMI_720x576p50_4x3
+#define HDMI_576p50_16x9 HDMI_720x576p50_16x9
+#define HDMI_720p50 HDMI_1280x720p50_16x9
+#define HDMI_1080i50 HDMI_1920x1080i50_16x9
+#define HDMI_576i50 HDMI_720x576i50_4x3
+#define HDMI_576i50_16x9 HDMI_720x576i50_16x9
+#define HDMI_576i50_16x9_rpt HDMI_2880x576i50_16x9
+#define HDMI_1080p50 HDMI_1920x1080p50_16x9
+#define HDMI_1080p24 HDMI_1920x1080p24_16x9
+#define HDMI_1080p25 HDMI_1920x1080p25_16x9
+#define HDMI_1080p30 HDMI_1920x1080p30_16x9
+#define HDMI_1080p120 HDMI_1920x1080p120_16x9
+#define HDMI_480p60_16x9_rpt HDMI_2880x480p60_16x9
+#define HDMI_576p50_16x9_rpt HDMI_2880x576p50_16x9
+#define HDMI_4k2k_24 HDMI_3840x2160p24_16x9
+#define HDMI_4k2k_25 HDMI_3840x2160p25_16x9
+#define HDMI_4k2k_30 HDMI_3840x2160p30_16x9
+#define HDMI_4k2k_50 HDMI_3840x2160p50_16x9
+#define HDMI_4k2k_60 HDMI_3840x2160p60_16x9
+#define HDMI_4k2k_smpte_24 HDMI_4096x2160p24_256x135
+#define HDMI_4k2k_smpte_50 HDMI_4096x2160p50_256x135
+#define HDMI_4k2k_smpte_60 HDMI_4096x2160p60_256x135
+
+/* CEA TIMING STRUCT DEFINITION */
+struct hdmi_cea_timing {
+ unsigned int pixel_freq; /* Unit: 1000 */
+ unsigned int h_freq; /* Unit: Hz */
+ unsigned int v_freq; /* Unit: 0.001 Hz */
+ unsigned int vsync_polarity:1; /* 1: positive 0: negative */
+ unsigned int hsync_polarity:1;
+ unsigned short h_active;
+ unsigned short h_total;
+ unsigned short h_blank;
+ unsigned short h_front;
+ unsigned short h_sync;
+ unsigned short h_back;
+ unsigned short v_active;
+ unsigned short v_total;
+ unsigned short v_blank;
+ unsigned short v_front;
+ unsigned short v_sync;
+ unsigned short v_back;
+ unsigned short v_sync_ln;
+};
+
+/* Refer CEA861-D Page 116 Table 55 */
+struct dtd {
+ unsigned short pixel_clock;
+ unsigned short h_active;
+ unsigned short h_blank;
+ unsigned short v_active;
+ unsigned short v_blank;
+ unsigned short h_sync_offset;
+ unsigned short h_sync;
+ unsigned short v_sync_offset;
+ unsigned short v_sync;
+ unsigned char h_image_size;
+ unsigned char v_image_size;
+ unsigned char h_border;
+ unsigned char v_border;
+ unsigned char flags;
+ enum hdmi_vic vic;
+};
+
+/* Dolby Version support information from EDID*/
+/* Refer to DV Spec version2.9 page26 to page39*/
+enum block_type {
+ ERROR_NULL = 0,
+ ERROR_LENGTH,
+ ERROR_OUI,
+ ERROR_VER,
+ CORRECT,
+};
+
+
+
+#define DV_IEEE_OUI 0x00D046
+#define HDR10_PLUS_IEEE_OUI 0x90848B
+
+#define HDMI_PACKET_VEND 1
+#define HDMI_PACKET_DRM 0x86
+
+#define CMD_CONF_OFFSET (0x14 << 24)
+#define CONF_AVI_BT2020 (CMD_CONF_OFFSET + 0X2000 + 0x00)
+ #define CLR_AVI_BT2020 0x0
+ #define SET_AVI_BT2020 0x1
+/* set value as COLORSPACE_RGB444, YUV422, YUV444, YUV420 */
+#define CONF_AVI_RGBYCC_INDIC (CMD_CONF_OFFSET + 0X2000 + 0x01)
+#define CONF_AVI_Q01 (CMD_CONF_OFFSET + 0X2000 + 0x02)
+ #define RGB_RANGE_DEFAULT 0
+ #define RGB_RANGE_LIM 1
+ #define RGB_RANGE_FUL 2
+ #define RGB_RANGE_RSVD 3
+#define CONF_AVI_YQ01 (CMD_CONF_OFFSET + 0X2000 + 0x03)
+ #define YCC_RANGE_LIM 0
+ #define YCC_RANGE_FUL 1
+ #define YCC_RANGE_RSVD 2
+
+struct hdr_info {
+ unsigned int hdr_sup_eotf_sdr:1;
+ unsigned int hdr_sup_eotf_hdr:1;
+ unsigned int hdr_sup_eotf_smpte_st_2084:1;
+ unsigned int hdr_sup_eotf_hlg:1;
+ unsigned int hdr_sup_SMD_type1:1;
+ unsigned char hdr_lum_max;
+ unsigned char hdr_lum_avg;
+ unsigned char hdr_lum_min;
+ unsigned char rawdata[7];
+};
+
+struct hdr10_plus_info {
+ uint32_t ieeeoui;
+ uint8_t length;
+ uint8_t application_version;
+};
+
+enum hdmi_hdr_transfer {
+ T_UNKNOWN = 0,
+ T_BT709,
+ T_UNDEF,
+ T_BT601,
+ T_BT470M,
+ T_BT470BG,
+ T_SMPTE170M,
+ T_SMPTE240M,
+ T_LINEAR,
+ T_LOG100,
+ T_LOG316,
+ T_IEC61966_2_4,
+ T_BT1361E,
+ T_IEC61966_2_1,
+ T_BT2020_10,
+ T_BT2020_12,
+ T_SMPTE_ST_2084,
+ T_SMPTE_ST_28,
+ T_HLG,
+};
+
+enum hdmi_hdr_color {
+ C_UNKNOWN = 0,
+ C_BT709,
+ C_UNDEF,
+ C_BT601,
+ C_BT470M,
+ C_BT470BG,
+ C_SMPTE170M,
+ C_SMPTE240M,
+ C_FILM,
+ C_BT2020,
+};
+
+/* master_display_info for display device */
+struct master_display_info_s {
+ u32 present_flag;
+ u32 features; /* feature bits bt2020/2084 */
+ u32 primaries[3][2]; /* normalized 50000 in G,B,R order */
+ u32 white_point[2]; /* normalized 50000 */
+ u32 luminance[2]; /* max/min lumin, normalized 10000 */
+ u32 max_content; /* Maximum Content Light Level */
+ u32 max_frame_average; /* Maximum Frame-average Light Level */
+};
+
+struct hdr10plus_para {
+ uint8_t application_version;
+ uint8_t targeted_max_lum;
+ uint8_t average_maxrgb;
+ uint8_t distribution_values[9];
+ uint8_t num_bezier_curve_anchors;
+ uint32_t knee_point_x;
+ uint32_t knee_point_y;
+ uint8_t bezier_curve_anchors[9];
+ uint8_t graphics_overlay_flag;
+ uint8_t no_delay_flag;
+};
+
+struct dv_info {
+ unsigned char rawdata[27];
+ enum block_type block_flag;
+ uint32_t ieeeoui;
+ uint8_t ver; /* 0 or 1 or 2*/
+ uint8_t length;/*ver1: 15 or 12*/
+
+ uint8_t sup_yuv422_12bit:1;
+ /* if as 0, then support RGB tunnel mode */
+ uint8_t sup_2160p60hz:1;
+ /* if as 0, then support 2160p30hz */
+ uint8_t sup_global_dimming:1;
+ uint16_t Rx;
+ uint16_t Ry;
+ uint16_t Gx;
+ uint16_t Gy;
+ uint16_t Bx;
+ uint16_t By;
+ uint16_t Wx;
+ uint16_t Wy;
+ uint16_t tminPQ;
+ uint16_t tmaxPQ;
+ uint8_t dm_major_ver;
+ uint8_t dm_minor_ver;
+ uint8_t dm_version;
+ uint8_t tmaxLUM;
+ uint8_t colorimetry:1;/* ver1*/
+ uint8_t tminLUM;
+ uint8_t low_latency;/* ver1_12 and 2*/
+ uint8_t sup_backlight_control:1;/*only ver2*/
+ uint8_t backlt_min_luma;/*only ver2*/
+ uint8_t Interface;/*only ver2*/
+ uint8_t sup_10b_12b_444;/*only ver2*/
+ uint8_t support_DV_RGB_444_8BIT;
+ uint8_t support_LL_YCbCr_422_12BIT;
+ uint8_t support_LL_RGB_444_10BIT;
+ uint8_t support_LL_RGB_444_12BIT;
+};
+
+enum eotf_type {
+ EOTF_T_NULL = 0,
+ EOTF_T_DOLBYVISION,
+ EOTF_T_HDR10,
+ EOTF_T_SDR,
+ EOTF_T_LL_MODE,
+ EOTF_T_MAX,
+};
+
+enum mode_type {
+ YUV422_BIT12 = 0,
+ RGB_8BIT,
+ RGB_10_12BIT,
+ YUV444_10_12BIT,
+};
+
+/* Dolby Version VSIF parameter*/
+struct dv_vsif_para {
+ uint8_t ver; /* 0 or 1 or 2*/
+ uint8_t length;/*ver1: 15 or 12*/
+ union {
+ struct {
+ uint8_t low_latency:1;
+ uint8_t dobly_vision_signal:1;
+ uint8_t backlt_ctrl_MD_present:1;
+ uint8_t auxiliary_MD_present:1;
+ uint8_t eff_tmax_PQ_hi;
+ uint8_t eff_tmax_PQ_low;
+ uint8_t auxiliary_runmode;
+ uint8_t auxiliary_runversion;
+ uint8_t auxiliary_debug0;
+ } ver2;
+ } vers;
+};
+
+#define Y420CMDB_MAX 32
+#define VIC_MAX_NUM 256
+struct rx_cap {
+ unsigned int native_Mode;
+ /*video*/
+ unsigned int VIC[VIC_MAX_NUM];
+ unsigned int VIC_count;
+ unsigned int native_VIC;
+ /*vendor*/
+ unsigned int IEEEOUI;
+ unsigned int Max_TMDS_Clock1; /* HDMI1.4b TMDS_CLK */
+ unsigned int HF_IEEEOUI; /* For HDMI Forum */
+ unsigned int Max_TMDS_Clock2; /* HDMI2.0 TMDS_CLK */
+ /* CEA861-F, Table 56, Colorimetry Data Block */
+ unsigned int colorimetry_data;
+ unsigned int scdc_present:1;
+ unsigned int scdc_rr_capable:1; /* SCDC read request */
+ unsigned int lte_340mcsc_scramble:1;
+ unsigned support_ycbcr444_flag:1;
+ unsigned support_ycbcr422_flag:1;
+ unsigned int dc_y444:1;
+ unsigned int dc_30bit:1;
+ unsigned int dc_36bit:1;
+ unsigned int dc_48bit:1;
+ unsigned int dc_y420:1;
+ unsigned int dc_30bit_420:1;
+ unsigned int dc_36bit_420:1;
+ unsigned int dc_48bit_420:1;
+ unsigned char edid_version;
+ unsigned char edid_revision;
+ unsigned int ColorDeepSupport;
+ unsigned int Video_Latency;
+ unsigned int Audio_Latency;
+ unsigned int Interlaced_Video_Latency;
+ unsigned int Interlaced_Audio_Latency;
+ unsigned int threeD_present;
+ unsigned int threeD_Multi_present;
+ unsigned int hdmi_vic_LEN;
+ enum hdmi_vic preferred_mode;
+ struct dtd dtd[16];
+ unsigned char dtd_idx;
+ unsigned char flag_vfpdb;
+ unsigned char number_of_dtd;
+ unsigned char pref_colorspace;
+ struct hdr_info hdr_info;
+ struct dv_info dv_info;
+ struct hdr10_plus_info hdr10plus_info;
+ /*blk0 check sum*/
+ unsigned char chksum;
+ /*blk0-3 check sum*/
+ char checksum[10];
+ unsigned char edid_changed;
+ /* for total = 32*8 = 256 VICs */
+ /* for Y420CMDB bitmap */
+ unsigned char bitmap_valid;
+ unsigned char bitmap_length;
+ unsigned char y420_all_vic;
+ unsigned char y420cmdb_bitmap[Y420CMDB_MAX];
+};
+
+enum color_attr_type {
+ COLOR_ATTR_YCBCR444_12BIT = 0,
+ COLOR_ATTR_YCBCR422_12BIT,
+ COLOR_ATTR_YCBCR420_12BIT,
+ COLOR_ATTR_RGB_12BIT,
+ COLOR_ATTR_YCBCR444_10BIT,
+ COLOR_ATTR_YCBCR422_10BIT,
+ COLOR_ATTR_YCBCR420_10BIT,
+ COLOR_ATTR_RGB_10BIT,
+ COLOR_ATTR_YCBCR444_8BIT,
+ COLOR_ATTR_YCBCR422_8BIT,
+ COLOR_ATTR_YCBCR420_8BIT,
+ COLOR_ATTR_RGB_8BIT,
+ COLOR_ATTR_RESERVED,
+};
+
+struct color_attr_to_string {
+ enum color_attr_type color_attr;
+ const char *color_attr_string;
+};
+
+enum hdmi_color_depth {
+ HDMI_COLOR_DEPTH_24B = 4,
+ HDMI_COLOR_DEPTH_30B = 5,
+ HDMI_COLOR_DEPTH_36B = 6,
+ HDMI_COLOR_DEPTH_48B = 7,
+};
+
+enum hdmi_color_format {
+ HDMI_COLOR_FORMAT_RGB,
+ HDMI_COLOR_FORMAT_422,
+ HDMI_COLOR_FORMAT_444,
+ HDMI_COLOR_FORMAT_420,
+};
+
+enum hdmi_color_range {
+ HDMI_COLOR_RANGE_LIM,
+ HDMI_COLOR_RANGE_FUL,
+};
+
+enum hdmi_audio_packet {
+ HDMI_AUDIO_PACKET_SMP = 0x02,
+ HDMI_AUDIO_PACKET_1BT = 0x07,
+ HDMI_AUDIO_PACKET_DST = 0x08,
+ HDMI_AUDIO_PACKET_HBR = 0x09,
+};
+
+enum hdmi_phy_para {
+ HDMI_PHYPARA_6G = 1, /* 2160p60hz 444 8bit */
+ HDMI_PHYPARA_4p5G, /* 2160p50hz 420 12bit */
+ HDMI_PHYPARA_3p7G, /* 2160p30hz 444 10bit */
+ HDMI_PHYPARA_3G, /* 2160p24hz 444 8bit */
+ HDMI_PHYPARA_LT3G, /* 1080p60hz 444 12bit */
+ HDMI_PHYPARA_DEF = HDMI_PHYPARA_LT3G,
+ HDMI_PHYPARA_270M, /* 480p60hz 444 8bit */
+};
+
+/* get hdmi cea timing
+ * t: struct hdmi_cea_timing *
+ */
+#define GET_TIMING(name) (t->name)
+
+struct parse_cd {
+ enum hdmi_color_depth cd;
+ const char *name;
+};
+
+struct parse_cs {
+ enum hdmi_color_format cs;
+ const char *name;
+};
+
+struct parse_cr {
+ enum hdmi_color_format cr;
+ const char *name;
+};
+
+#define EDID_BLK_NO 4
+#define EDID_BLK_SIZE 128
+struct hdmi_format_para {
+ enum hdmi_vic vic;
+ char *name; /* full name, 1280x720p60hz */
+ char *sname; /* short name, 1280x720p60hz -> 720p60hz */
+ char ext_name[32];
+ enum hdmi_color_depth cd; /* cd8, cd10 or cd12 */
+ enum hdmi_color_format cs; /* rgb, y444, y422, y420 */
+ enum hdmi_color_range cr; /* limit, full */
+ unsigned int pixel_repetition_factor;
+ unsigned int progress_mode:1; /* 0: Interlace 1: Progressive */
+ unsigned int scrambler_en:1;
+ unsigned int tmds_clk_div40:1;
+ unsigned int tmds_clk; /* Unit: 1000 */
+ struct hdmi_cea_timing timing;
+};
+
+struct hdmi_support_mode {
+ enum hdmi_vic vic;
+ char *sname;
+ char y420;
+};
+
+#define DOLBY_VISION_LL_RGB 3
+#define DOLBY_VISION_LL_YUV 2
+#define DOLBY_VISION_STD_ENABLE 1
+#define DOLBY_VISION_DISABLE 0
+#define DOLBY_VISION_ENABLE 1
+
+#define HDMI_IEEEOUI 0x000C03
+#define MODE_LEN 32
+#define VESA_MAX_TIMING 64
+
+#define DEFAULT_OUTPUTMODE_ENV "1080p60hz"
+#define DEFAULT_HDMIMODE_ENV "1080p60hz"
+#define DEFAULT_COLORATTRIBUTE_ENV "444,8bit"
+
+#define DEFAULT_COLOR_FORMAT_4K "420,8bit"
+#define DEFAULT_COLOR_FORMAT "444,8bit"
+#define DEFAULT_HDMI_MODE "480p60hz"
+
+typedef enum {
+ DOLBY_VISION_PRIORITY = 0,
+ HDR10_PRIORITY = 1,
+ SDR_PRIORITY = 2,
+} hdr_priority_e;
+
+typedef enum {
+ HDR_POLICY_SINK = 0,
+ HDR_POLICY_SOURCE = 1,
+} hdr_policy_e;
+
+enum {
+ RESOLUTION_PRIORITY = 0,
+ FRAMERATE_PRIORITY = 1,
+};
+
+typedef struct input_hdmi_data {
+ char ubootenv_hdmimode[MODE_LEN];
+ char ubootenv_colorattribute[MODE_LEN];
+ int ubootenv_dv_type;
+ /* dynamic range fromat preference,0:dolby vision,1:hdr,2:sdr */
+ hdr_priority_e hdr_priority;
+ /* dynamic range policy,0 :follow sink, 1: match content */
+ hdr_policy_e hdr_policy;
+ #if 0
+ bool isbestpolicy;
+ bool isSupport4K30Hz;
+ bool isSupport4K;
+ bool isDeepColor;
+ bool isframeratepriority;
+ bool isLowPowerMode;
+ #endif
+ struct rx_cap *pRXCap;
+} hdmi_data_t;
+
+typedef struct scene_output_info {
+ char final_displaymode[MODE_LEN];
+ char final_deepcolor[MODE_LEN];
+ int final_dv_type;
+} scene_output_info_t;
+
+struct dispmode_vic {
+ const char *disp_mode;
+ enum hdmi_vic VIC;
+};
+
+#endif
+
diff --git a/include/amlogic/media/vout/hdmitx/hdmitx.h b/include/amlogic/media/vout/hdmitx/hdmitx.h
new file mode 100644
index 0000000..9ac24bf
--- /dev/null
+++ b/include/amlogic/media/vout/hdmitx/hdmitx.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __HDMITX_H_
+#define __HDMITX_H_
+#include "hdmi_common.h"
+#include "hdmitx_module.h"
+#include "hdmitx_reg.h"
+#include "mach_reg.h"
+
+int hdmitx_likely_frac_rate_mode(char *m);
+unsigned int hdmi_outputmode_check(char *mode, unsigned int frac);
+
+#endif
diff --git a/include/amlogic/media/vout/hdmitx/hdmitx_ext.h b/include/amlogic/media/vout/hdmitx/hdmitx_ext.h
new file mode 100644
index 0000000..3bb671a
--- /dev/null
+++ b/include/amlogic/media/vout/hdmitx/hdmitx_ext.h
@@ -0,0 +1,11 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __HDMITX_EXT_H__
+#define __HDMITX_EXT_H__
+
+void hdmitx_init(void);
+
+#endif
diff --git a/include/amlogic/media/vout/hdmitx/hdmitx_module.h b/include/amlogic/media/vout/hdmitx/hdmitx_module.h
new file mode 100644
index 0000000..e81e040
--- /dev/null
+++ b/include/amlogic/media/vout/hdmitx/hdmitx_module.h
@@ -0,0 +1,112 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __HDMITX_MODULE_H__
+#define __HDMITX_MODULE_H__
+
+#include "hdmi_common.h"
+#include "hdmitx_ext.h"
+
+struct hdmitx_dev {
+ unsigned char rx_edid[512]; /* some RX may exceeds 256Bytes */
+ struct {
+ int (*get_hpd_state)(void);
+ int (*read_edid)(unsigned char *buf, unsigned char addr,
+ unsigned char blk_no);
+ void (*turn_off)(void);
+ void (*list_support_modes)(void);
+ void (*dump_regs)(void);
+ void (*test_bist)(unsigned int mode);
+ void (*test_prbs)(void);
+ void (*set_div40)(bool div40);
+ void (*output_blank)(unsigned int blank);
+ } hwop;
+ unsigned char rawedid[EDID_BLK_SIZE * EDID_BLK_NO];
+ struct rx_cap RXCap;
+ struct hdmi_format_para *para;
+ enum hdmi_vic vic;
+ unsigned int frac_rate_policy;
+ unsigned int mode420;
+ unsigned int dc30;
+ enum eotf_type hdmi_current_eotf_type;
+ enum mode_type hdmi_current_tunnel_mode;
+ /* Add dongle_mode, clock, phy may be different from mbox */
+ unsigned int dongle_mode;
+ unsigned char limit_res_1080p;
+};
+
+struct hdmitx_dev *hdmitx_get_hdev(void);
+
+struct hdmi_format_para *hdmi_get_fmt_paras(enum hdmi_vic vic);
+enum hdmi_vic hdmi_get_fmt_vic(char const *name);
+void hdmi_parse_attr(struct hdmi_format_para *para, char const *name);
+int hdmitx_edid_VIC_support(enum hdmi_vic vic);
+enum hdmi_vic hdmitx_edid_vic_tab_map_vic(const char *disp_mode);
+const char *hdmitx_edid_vic_tab_map_string(enum hdmi_vic vic);
+const char *hdmitx_edid_vic_to_string(enum hdmi_vic vic);
+bool hdmitx_edid_check_valid_mode(struct hdmitx_dev *hdev,
+ struct hdmi_format_para *para);
+enum hdmi_vic hdmitx_edid_get_VIC(struct hdmitx_dev *hdev,
+ const char *disp_mode, char force_flag);
+bool edid_parsing_ok(struct hdmitx_dev *hdev);
+bool is_dolby_enabled(void);
+bool is_tv_support_dv(struct hdmitx_dev *hdev);
+bool is_dv_preference(struct hdmitx_dev *hdev);
+bool is_hdr_preference(struct hdmitx_dev *hdev);
+void dolbyvision_scene_process(hdmi_data_t *hdmi_data,
+ scene_output_info_t *output_info);
+void sdr_scene_process(hdmi_data_t *hdmi_data,
+ scene_output_info_t *output_info);
+void hdr_scene_process(struct input_hdmi_data *hdmi_data,
+ scene_output_info_t *output_info);
+
+void get_hdmi_data(struct hdmitx_dev *hdev, hdmi_data_t *data);
+bool pre_process_str(char *name);
+struct hdmi_format_para *hdmi_tst_fmt_name(char const *name, char const *attr);
+bool is_support_4k(void);
+bool is_supported_mode_attr(hdmi_data_t *hdmi_data, char *mode_attr);
+bool hdmitx_chk_mode_attr_sup(hdmi_data_t *hdmi_data, char *mode, char *attr);
+int get_ubootenv_dv_type(void);
+void hdmi_tx_set(struct hdmitx_dev *hdev);
+/* Parsing RAW EDID data from edid to pRXCap */
+unsigned int hdmi_edid_parsing(unsigned char *edid, struct rx_cap *pRXCap);
+struct hdmi_format_para *hdmi_match_dtd_paras(struct dtd *t);
+bool hdmimode_is_interlaced(enum hdmi_vic vic);
+void hdmitx_ddc_init(void);
+void hdmitx_set_clk(struct hdmitx_dev *hdev);
+void hdmitx_turnoff(void);
+int hdmitx_get_hpd_state(void);
+void hdmitx_prbs(void);
+unsigned int hdmitx_rd_check_reg(unsigned int addr, unsigned int exp_data,
+ unsigned int mask);
+void hdmitx_hdcp_init(void);
+void hdmitx_set_phypara(enum hdmi_phy_para mode);
+void hdmitx_test_prbs(void);
+void hdmitx_set_div40(bool div40);
+
+struct hdr_info *hdmitx_get_rx_hdr_info(void);
+void hdmitx_set_drm_pkt(struct master_display_info_s *data);
+bool hdmitx_find_vendor(struct hdmitx_dev *hdev);
+
+void hdmitx_set_vsif_pkt(enum eotf_type type, enum mode_type tunnel_mode,
+ struct dv_vsif_para *data);
+void hdmitx_set_hdr10plus_pkt(unsigned int flag,
+ struct hdr10plus_para *data);
+
+/* the hdmitx output limits to 1080p */
+bool is_hdmitx_limited_1080p(void);
+/* test current vic is over limited or not */
+bool is_vic_over_limited_1080p(enum hdmi_vic vic);
+
+#ifndef printk
+#define printk printf
+#endif
+#ifndef pr_info
+#define pr_info printf
+#endif
+
+#define hdmitx_debug() /* printf("hd: %s[%d]\n", __func__, __LINE__) */
+
+#endif
diff --git a/include/amlogic/media/vout/hdmitx/hdmitx_reg.h b/include/amlogic/media/vout/hdmitx/hdmitx_reg.h
new file mode 100644
index 0000000..98a1bb9
--- /dev/null
+++ b/include/amlogic/media/vout/hdmitx/hdmitx_reg.h
@@ -0,0 +1,1027 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _HDMI_TX_REG_H
+#define _HDMI_TX_REG_H
+
+/* TOP-level wrapper registers addresses */
+/* bit24: 1 means secure access */
+/* bit28: 1 means DWC, 0 means TOP */
+#define SEC_OFFSET (0x1UL << 24)
+#define TOP_OFFSET_MASK (0x0UL << 24)
+#define TOP_SEC_OFFSET_MASK ((TOP_OFFSET_MASK) | (SEC_OFFSET))
+#define DWC_OFFSET_MASK (0x10UL << 24)
+#define DWC_SEC_OFFSET_MASK ((DWC_OFFSET_MASK) | (SEC_OFFSET))
+
+/* Bit 7 RW Reserved. Default 1. */
+/* Bit 6 RW Reserved. Default 1. */
+/* Bit 5 RW Reserved. Default 1. */
+/* Bit 4 RW sw_reset_phyif: PHY interface. 1=Apply reset; 0=Release from reset.
+ * Default 1.
+ * Bit 3 RW sw_reset_intr: interrupt module. 1=Apply reset;
+ * 0=Release from reset. Default 1.
+ * Bit 2 RW sw_reset_mem: KSV/REVOC mem. 1=Apply reset; 0=Release from reset.
+ * Default 1.
+ * Bit 1 RW sw_reset_rnd: random number interface to HDCP. 1=Apply reset;
+ * 0=Release from reset. Default 1.
+ * Bit 0 RW sw_reset_core: connects to IP's ~irstz. 1=Apply reset;
+ * 0=Release from reset. Default 1.
+ */
+#define HDMITX_TOP_SW_RESET (TOP_OFFSET_MASK + 0x000)
+
+/* Bit 12 RW i2s_ws_inv:1=Invert i2s_ws; 0=No invert. Default 0. */
+/* Bit 11 RW i2s_clk_inv: 1=Invert i2s_clk; 0=No invert. Default 0. */
+/* Bit 10 RW spdif_clk_inv: 1=Invert spdif_clk; 0=No invert. Default 0. */
+/* Bit 9 RW tmds_clk_inv: 1=Invert tmds_clk; 0=No invert. Default 0. */
+/* Bit 8 RW pixel_clk_inv: 1=Invert pixel_clk; 0=No invert. Default 0. */
+/* Bit 4 RW cec_clk_en: 1=enable cec_clk; 0=disable. Default 0. */
+/* Bit 3 RW i2s_clk_en: 1=enable i2s_clk; 0=disable. Default 0. */
+/* Bit 2 RW spdif_clk_en: 1=enable spdif_clk; 0=disable. Default 0. */
+/* Bit 1 RW tmds_clk_en: 1=enable tmds_clk; 0=disable. Default 0. */
+/* Bit 0 RW pixel_clk_en: 1=enable pixel_clk; 0=disable. Default 0. */
+#define HDMITX_TOP_CLK_CNTL (TOP_OFFSET_MASK + 0x001)
+
+/* Bit 11: 0 RW hpd_valid_width: filter out width <= M*1024. Default 0. */
+/* Bit 15:12 RW hpd_glitch_width: filter out glitch <= N. Default 0. */
+#define HDMITX_TOP_HPD_FILTER (TOP_OFFSET_MASK + 0x002)
+
+/* intr_maskn: MASK_N, one bit per interrupt source.
+ * 1=Enable interrupt source; 0=Disable interrupt source. Default 0.
+ * [ 4] hdcp22_rndnum_err
+ * [ 3] nonce_rfrsh_rise
+ * [ 2] hpd_fall_intr
+ * [ 1] hpd_rise_intr
+ * [ 0] core_intr
+ */
+#define HDMITX_TOP_INTR_MASKN (TOP_OFFSET_MASK + 0x003)
+
+/* Bit 30: 0 RW intr_stat: For each bit, write 1 to manually set the interrupt
+ * bit, read back the interrupt status. */
+/* Bit 31 R IP interrupt status */
+/* Bit 2 RW hpd_fall */
+/* Bit 1 RW hpd_rise */
+/* Bit 0 RW IP interrupt */
+#define HDMITX_TOP_INTR_STAT (TOP_OFFSET_MASK + 0x004)
+
+/* [4] hdcp22_rndnum_err */
+/* [3] nonce_rfrsh_rise */
+/* [2] hpd_fall */
+/* [1] hpd_rise */
+/* [0] core_intr_rise */
+#define HDMITX_TOP_INTR_STAT_CLR (TOP_OFFSET_MASK + 0x005)
+
+/* Bit 14:12 RW tmds_sel: 3'b000=Output zero; 3'b001=Output normal TMDS data;
+ * 3'b010=Output PRBS data; 3'b100=Output shift pattern. Default 0.
+ * Bit 11: 9 RW shift_pttn_repeat: 0=New pattern every clk cycle; 1=New pattern
+ * every 2 clk cycles; ...; 7=New pattern every 8 clk cycles. Default 0.
+ * Bit 8 RW shift_pttn_en: 1= Eanble shift pattern generator; 0=Disable.
+ * Default 0.
+ * Bit 4: 3 RW prbs_pttn_mode: 0=PRBS11; 1=PRBS15; 2=PRBS7; 3=PRBS31. Default 0.
+ * Bit 2: 1 RW prbs_pttn_width: 0=idle; 1=output 8-bit pattern;
+ * 2=Output 1-bit pattern; 3=output 10-bit pattern. Default 0.
+ * Bit 0 RW prbs_pttn_en: 1=Enable PRBS generator; 0=Disable. Default 0.
+ */
+#define HDMITX_TOP_BIST_CNTL (TOP_OFFSET_MASK + 0x006)
+
+/* Bit 29:20 RW shift_pttn_data[59:50]. Default 0. */
+/* Bit 19:10 RW shift_pttn_data[69:60]. Default 0. */
+/* Bit 9: 0 RW shift_pttn_data[79:70]. Default 0. */
+#define HDMITX_TOP_SHIFT_PTTN_012 (TOP_OFFSET_MASK + 0x007)
+
+/* Bit 29:20 RW shift_pttn_data[29:20]. Default 0. */
+/* Bit 19:10 RW shift_pttn_data[39:30]. Default 0. */
+/* Bit 9: 0 RW shift_pttn_data[49:40]. Default 0. */
+#define HDMITX_TOP_SHIFT_PTTN_345 (TOP_OFFSET_MASK + 0x008)
+
+/* Bit 19:10 RW shift_pttn_data[ 9: 0]. Default 0. */
+/* Bit 9: 0 RW shift_pttn_data[19:10]. Default 0. */
+#define HDMITX_TOP_SHIFT_PTTN_67 (TOP_OFFSET_MASK + 0x009)
+
+/* Bit 25:16 RW tmds_clk_pttn[19:10]. Default 0. */
+/* Bit 9: 0 RW tmds_clk_pttn[ 9: 0]. Default 0. */
+#define HDMITX_TOP_TMDS_CLK_PTTN_01 (TOP_OFFSET_MASK + 0x00A)
+
+/* Bit 25:16 RW tmds_clk_pttn[39:30]. Default 0. */
+/* Bit 9: 0 RW tmds_clk_pttn[29:20]. Default 0. */
+#define HDMITX_TOP_TMDS_CLK_PTTN_23 (TOP_OFFSET_MASK + 0x00B)
+
+/* Bit 1 RW shift_tmds_clk_pttn:1=Enable shifting clk pattern,
+ * used when TMDS CLK rate = TMDS character rate /4. Default 0.
+ * Bit 0 R Reserved. Default 0.
+ */
+/* [ 1] shift_tmds_clk_pttn */
+/* [ 0] load_tmds_clk_pttn */
+#define HDMITX_TOP_TMDS_CLK_PTTN_CNTL (TOP_OFFSET_MASK + 0x00C)
+
+/* Bit 0 RW revocmem_wr_fail: Read back 1 to indicate Host write REVOC MEM
+ * failure, write 1 to clear the failure flag. Default 0.
+ */
+#define HDMITX_TOP_REVOCMEM_STAT (TOP_OFFSET_MASK + 0x00D)
+
+/* Bit 0 R filtered HPD status. */
+#define HDMITX_TOP_STAT0 (TOP_OFFSET_MASK + 0x00E)
+#define HDMITX_TOP_SKP_CNTL_STAT (TOP_SEC_OFFSET_MASK + 0x010)
+#define HDMITX_TOP_NONCE_0 (TOP_SEC_OFFSET_MASK + 0x011)
+#define HDMITX_TOP_NONCE_1 (TOP_SEC_OFFSET_MASK + 0x012)
+#define HDMITX_TOP_NONCE_2 (TOP_SEC_OFFSET_MASK + 0x013)
+#define HDMITX_TOP_NONCE_3 (TOP_SEC_OFFSET_MASK + 0x014)
+#define HDMITX_TOP_PKF_0 (TOP_SEC_OFFSET_MASK + 0x015)
+#define HDMITX_TOP_PKF_1 (TOP_SEC_OFFSET_MASK + 0x016)
+#define HDMITX_TOP_PKF_2 (TOP_SEC_OFFSET_MASK + 0x017)
+#define HDMITX_TOP_PKF_3 (TOP_SEC_OFFSET_MASK + 0x018)
+#define HDMITX_TOP_DUK_0 (TOP_SEC_OFFSET_MASK + 0x019)
+#define HDMITX_TOP_DUK_1 (TOP_SEC_OFFSET_MASK + 0x01A)
+#define HDMITX_TOP_DUK_2 (TOP_SEC_OFFSET_MASK + 0x01B)
+#define HDMITX_TOP_DUK_3 (TOP_SEC_OFFSET_MASK + 0x01C)
+/* [26:24] infilter_ddc_intern_clk_divide */
+/* [23:16] infilter_ddc_sample_clk_divide */
+/* [10: 8] infilter_cec_intern_clk_divide */
+/* [ 7: 0] infilter_cec_sample_clk_divide */
+#define HDMITX_TOP_INFILTER (TOP_OFFSET_MASK + 0x01D)
+#define HDMITX_TOP_NSEC_SCRATCH (TOP_OFFSET_MASK + 0x01E)
+#define HDMITX_TOP_SEC_SCRATCH (TOP_SEC_OFFSET_MASK + 0x01F)
+#define HDMITX_TOP_EMP_CNTL0 (TOP_OFFSET_MASK + 0x020)
+#define HDMITX_TOP_EMP_CNTL1 (TOP_OFFSET_MASK + 0x021)
+#define HDMITX_TOP_EMP_MEMADDR_START (TOP_OFFSET_MASK + 0x022)
+#define HDMITX_TOP_EMP_STAT0 (TOP_OFFSET_MASK + 0x023)
+#define HDMITX_TOP_EMP_STAT1 (TOP_OFFSET_MASK + 0x024)
+#define HDMITX_TOP_AXI_ASYNC_CNTL0 (TOP_OFFSET_MASK + 0x025)
+#define HDMITX_TOP_AXI_ASYNC_CNTL1 (TOP_OFFSET_MASK + 0x026)
+#define HDMITX_TOP_AXI_ASYNC_STAT0 (TOP_OFFSET_MASK + 0x027)
+#define HDMITX_TOP_I2C_BUSY_CNT_MAX (TOP_OFFSET_MASK + 0x028)
+#define HDMITX_TOP_I2C_BUSY_CNT_STAT (TOP_OFFSET_MASK + 0x029)
+#define HDMITX_TOP_HDCP22_BSOD (TOP_OFFSET_MASK + 0x02A)
+#define HDMITX_TOP_DDC_CNTL (TOP_OFFSET_MASK + 0x02B)
+#define HDMITX_TOP_DISABLE_NULL (TOP_OFFSET_MASK + 0x030)
+#define HDMITX_TOP_REVOCMEM_ADDR_S (TOP_OFFSET_MASK + 0x2000 >> 2)
+#define HDMITX_TOP_REVOCMEM_ADDR_E (TOP_OFFSET_MASK + 0x365E >> 2)
+
+#define HDMITX_TOP_DONT_TOUCH0 (TOP_OFFSET_MASK + 0x0FE)
+#define HDMITX_TOP_DONT_TOUCH1 (TOP_OFFSET_MASK + 0x0FF)
+
+/* DWC_HDMI_TX Controller registers addresses */
+
+/* Identification Registers */
+#define HDMITX_DWC_DESIGN_ID (DWC_OFFSET_MASK + 0x0000)
+#define HDMITX_DWC_REVISION_ID (DWC_OFFSET_MASK + 0x0001)
+#define HDMITX_DWC_PRODUCT_ID0 (DWC_OFFSET_MASK + 0x0002)
+#define HDMITX_DWC_PRODUCT_ID1 (DWC_OFFSET_MASK + 0x0003)
+#define HDMITX_DWC_CONFIG0_ID (DWC_OFFSET_MASK + 0x0004)
+#define HDMITX_DWC_CONFIG1_ID (DWC_OFFSET_MASK + 0x0005)
+#define HDMITX_DWC_CONFIG2_ID (DWC_OFFSET_MASK + 0x0006)
+#define HDMITX_DWC_CONFIG3_ID (DWC_OFFSET_MASK + 0x0007)
+
+/* Interrupt Registers */
+#define HDMITX_DWC_IH_FC_STAT0 (DWC_OFFSET_MASK + 0x0100)
+#define HDMITX_DWC_IH_FC_STAT1 (DWC_OFFSET_MASK + 0x0101)
+#define HDMITX_DWC_IH_FC_STAT2 (DWC_OFFSET_MASK + 0x0102)
+#define HDMITX_DWC_IH_AS_STAT0 (DWC_OFFSET_MASK + 0x0103)
+#define HDMITX_DWC_IH_PHY_STAT0 (DWC_OFFSET_MASK + 0x0104)
+#define HDMITX_DWC_IH_I2CM_STAT0 (DWC_OFFSET_MASK + 0x0105)
+#define HDMITX_DWC_IH_CEC_STAT0 (DWC_OFFSET_MASK + 0x0106)
+#define HDMITX_DWC_IH_VP_STAT0 (DWC_OFFSET_MASK + 0x0107)
+#define HDMITX_DWC_IH_I2CMPHY_STAT0 (DWC_OFFSET_MASK + 0x0108)
+#define HDMITX_DWC_IH_DECODE (DWC_OFFSET_MASK + 0x0170)
+/* [ 7] mute_AUDI */
+/* [ 6] mute_ACP */
+/* [ 5] mute_HBR */
+/* [ 4] mute_MAS */
+/* [ 3] mute_NVBI */
+/* [ 2] mute_AUDS */
+/* [ 1] mute_ACR */
+/* [ 0] mute_NULL */
+#define HDMITX_DWC_IH_MUTE_FC_STAT0 (DWC_OFFSET_MASK + 0x0180)
+/* [ 7] mute_GMD */
+/* [ 6] mute_ISRC1 */
+/* [ 5] mute_ISRC2 */
+/* [ 4] mute_VSD */
+/* [ 3] mute_SPD */
+/* [ 2] mute_AMP */
+/* [ 1] mute_AVI */
+/* [ 0] mute_GCP */
+#define HDMITX_DWC_IH_MUTE_FC_STAT1 (DWC_OFFSET_MASK + 0x0181)
+/* [ 1] mute_LowPriority_fifo_full */
+/* [ 0] mute_HighPriority_fifo_full */
+#define HDMITX_DWC_IH_MUTE_FC_STAT2 (DWC_OFFSET_MASK + 0x0182)
+/* [ 4] mute_aud_fifo_underrun */
+/* [ 3] mute_aud_fifo_overrun */
+/* [ 2] mute_aud_fifo_empty_thr. oififoemptythr tied to 0. */
+/* [ 1] mute_aud_fifo_empty */
+/* [ 0] mute_aud_fifo_full */
+#define HDMITX_DWC_IH_MUTE_AS_STAT0 (DWC_OFFSET_MASK + 0x0183)
+#define HDMITX_DWC_IH_MUTE_PHY_STAT0 (DWC_OFFSET_MASK + 0x0184)
+/* [ 2] mute_scdc_readreq */
+/* [ 1] mute_edid_i2c_master_done */
+/* [ 0] mute_edid_i2c_master_error */
+#define HDMITX_DWC_IH_MUTE_I2CM_STAT0 (DWC_OFFSET_MASK + 0x0185)
+/* [ 6] cec_wakeup */
+/* [ 5] cec_error_follower */
+/* [ 4] cec_error_initiator */
+/* [ 3] cec_arb_lost */
+/* [ 2] cec_nack */
+/* [ 1] cec_eom */
+/* [ 0] cec_done */
+#define HDMITX_DWC_IH_MUTE_CEC_STAT0 (DWC_OFFSET_MASK + 0x0186)
+#define HDMITX_DWC_IH_MUTE_VP_STAT0 (DWC_OFFSET_MASK + 0x0187)
+#define HDMITX_DWC_IH_MUTE_I2CMPHY_STAT0 (DWC_OFFSET_MASK + 0x0188)
+/* [ 1] mute_wakeup_interrupt */
+/* [ 0] mute_all_interrupt */
+#define HDMITX_DWC_IH_MUTE (DWC_OFFSET_MASK + 0x01FF)
+
+/* Video Sampler Registers */
+/* [ 7] internal_de_generator */
+/* [4:0] video_mapping */
+#define HDMITX_DWC_TX_INVID0 (DWC_OFFSET_MASK + 0x0200)
+/* [ 2] bcbdata_stuffing */
+/* [ 1] rcrdata_stuffing */
+/* [ 0] gydata_stuffing */
+#define HDMITX_DWC_TX_INSTUFFING (DWC_OFFSET_MASK + 0x0201)
+#define HDMITX_DWC_TX_GYDATA0 (DWC_OFFSET_MASK + 0x0202)
+#define HDMITX_DWC_TX_GYDATA1 (DWC_OFFSET_MASK + 0x0203)
+#define HDMITX_DWC_TX_RCRDATA0 (DWC_OFFSET_MASK + 0x0204)
+#define HDMITX_DWC_TX_RCRDATA1 (DWC_OFFSET_MASK + 0x0205)
+#define HDMITX_DWC_TX_BCBDATA0 (DWC_OFFSET_MASK + 0x0206)
+#define HDMITX_DWC_TX_BCBDATA1 (DWC_OFFSET_MASK + 0x0207)
+
+/* Video Packetizer Registers */
+#define HDMITX_DWC_VP_STATUS (DWC_OFFSET_MASK + 0x0800)
+/* [3:0] desired_pr_factor */
+#define HDMITX_DWC_VP_PR_CD (DWC_OFFSET_MASK + 0x0801)
+/* [ 5] default_phase */
+/* [ 2] ycc422_stuffing */
+/* [ 1] pp_stuffing */
+/* [ 0] pr_stuffing */
+#define HDMITX_DWC_VP_STUFF (DWC_OFFSET_MASK + 0x0802)
+#define HDMITX_DWC_VP_REMAP (DWC_OFFSET_MASK + 0x0803)
+#define HDMITX_DWC_VP_CONF (DWC_OFFSET_MASK + 0x0804)
+/* [ 7] mask_int_full_prpt */
+/* [ 6] mask_int_empty_prpt */
+/* [ 5] mask_int_full_ppack */
+/* [ 4] mask_int_empty_ppack */
+/* [ 3] mask_int_full_remap */
+/* [ 2] mask_int_empty_remap */
+/* [ 1] mask_int_full_byp */
+/* [ 0] mask_int_empty_byp */
+#define HDMITX_DWC_VP_MASK (DWC_OFFSET_MASK + 0x0807)
+
+/* Frmae Composer Registers */
+/* [ 7] HDCP_keepout */
+/* [ 6] vs_in_pol: 0=active low; 1=active high. */
+/* [ 5] hs_in_pol: 0=active low; 1=active high. */
+/* [ 4] de_in_pol: 0=active low; 1=active high. */
+/* [ 3] dvi_modez: 0=dvi; 1=hdmi. */
+/* [ 1] r_v_blank_in_osc */
+/* [ 0] in_I_P: 0=progressive; 1=interlaced. */
+#define HDMITX_DWC_FC_INVIDCONF (DWC_OFFSET_MASK + 0x1000)
+/* [7:0] H_in_active[7:0] */
+#define HDMITX_DWC_FC_INHACTV0 (DWC_OFFSET_MASK + 0x1001)
+/* [5:0] H_in_active[13:8] */
+#define HDMITX_DWC_FC_INHACTV1 (DWC_OFFSET_MASK + 0x1002)
+/* [7:0] H_in_blank[7:0] */
+#define HDMITX_DWC_FC_INHBLANK0 (DWC_OFFSET_MASK + 0x1003)
+/* [4:0] H_in_blank[12:8] */
+#define HDMITX_DWC_FC_INHBLANK1 (DWC_OFFSET_MASK + 0x1004)
+/* [7:0] V_in_active[7:0] */
+#define HDMITX_DWC_FC_INVACTV0 (DWC_OFFSET_MASK + 0x1005)
+/* [4:0] V_in_active[12:8] */
+#define HDMITX_DWC_FC_INVACTV1 (DWC_OFFSET_MASK + 0x1006)
+/* [7:0] V_in_blank */
+#define HDMITX_DWC_FC_INVBLANK (DWC_OFFSET_MASK + 0x1007)
+/* [7:0] H_in_delay[7:0] */
+#define HDMITX_DWC_FC_HSYNCINDELAY0 (DWC_OFFSET_MASK + 0x1008)
+/* [4:0] H_in_delay[12:8] */
+#define HDMITX_DWC_FC_HSYNCINDELAY1 (DWC_OFFSET_MASK + 0x1009)
+/* [7:0] H_in_width[7:0] */
+#define HDMITX_DWC_FC_HSYNCINWIDTH0 (DWC_OFFSET_MASK + 0x100A)
+/* [1:0] H_in_width[9:8] */
+#define HDMITX_DWC_FC_HSYNCINWIDTH1 (DWC_OFFSET_MASK + 0x100B)
+/* [7:0] V_in_delay */
+#define HDMITX_DWC_FC_VSYNCINDELAY (DWC_OFFSET_MASK + 0x100C)
+/* [5:0] V_in_width */
+#define HDMITX_DWC_FC_VSYNCINWIDTH (DWC_OFFSET_MASK + 0x100D)
+#define HDMITX_DWC_FC_INFREQ0 (DWC_OFFSET_MASK + 0x100E)
+#define HDMITX_DWC_FC_INFREQ1 (DWC_OFFSET_MASK + 0x100F)
+#define HDMITX_DWC_FC_INFREQ2 (DWC_OFFSET_MASK + 0x1010)
+#define HDMITX_DWC_FC_CTRLDUR (DWC_OFFSET_MASK + 0x1011)
+#define HDMITX_DWC_FC_EXCTRLDUR (DWC_OFFSET_MASK + 0x1012)
+#define HDMITX_DWC_FC_EXCTRLSPAC (DWC_OFFSET_MASK + 0x1013)
+#define HDMITX_DWC_FC_CH0PREAM (DWC_OFFSET_MASK + 0x1014)
+#define HDMITX_DWC_FC_CH1PREAM (DWC_OFFSET_MASK + 0x1015)
+#define HDMITX_DWC_FC_CH2PREAM (DWC_OFFSET_MASK + 0x1016)
+/* [3:2] YQ */
+/* [1:0] CN */
+#define HDMITX_DWC_FC_AVICONF3 (DWC_OFFSET_MASK + 0x1017)
+/* [ 2] default_phase */
+/* [ 1] set_avmute */
+/* [ 0] clear_avmute */
+#define HDMITX_DWC_FC_GCP (DWC_OFFSET_MASK + 0x1018)
+/* [ 7] rgb_ycc_indication[2] */
+/* [ 6] active_format_present */
+/* [5:4] scan_information */
+/* [3:2] bar_information */
+/* [1:0] rgb_ycc_indication[1:0] */
+#define HDMITX_DWC_FC_AVICONF0 (DWC_OFFSET_MASK + 0x1019)
+/* [7:6] colorimetry */
+/* [5:4] picture_aspect_ratio */
+/* [3:0] active_aspect_ratio */
+#define HDMITX_DWC_FC_AVICONF1 (DWC_OFFSET_MASK + 0x101A)
+/* [ 7] IT_content */
+/* [6:4] extended_colorimetry */
+/* [3:2] quantization_range */
+/* [1:0] non_uniform_picture_scaling */
+#define HDMITX_DWC_FC_AVICONF2 (DWC_OFFSET_MASK + 0x101B)
+#define HDMITX_DWC_FC_AVIVID (DWC_OFFSET_MASK + 0x101C)
+#define HDMITX_DWC_FC_AVIETB0 (DWC_OFFSET_MASK + 0x101D)
+#define HDMITX_DWC_FC_AVIETB1 (DWC_OFFSET_MASK + 0x101E)
+#define HDMITX_DWC_FC_AVISBB0 (DWC_OFFSET_MASK + 0x101F)
+#define HDMITX_DWC_FC_AVISBB1 (DWC_OFFSET_MASK + 0x1020)
+#define HDMITX_DWC_FC_AVIELB0 (DWC_OFFSET_MASK + 0x1021)
+#define HDMITX_DWC_FC_AVIELB1 (DWC_OFFSET_MASK + 0x1022)
+#define HDMITX_DWC_FC_AVISRB0 (DWC_OFFSET_MASK + 0x1023)
+#define HDMITX_DWC_FC_AVISRB1 (DWC_OFFSET_MASK + 0x1024)
+/* [3:0] CT: coding type */
+#define HDMITX_DWC_FC_AUDICONF0 (DWC_OFFSET_MASK + 0x1025)
+/* [5:4] SS: sampling size */
+/* [2:0] SF: sampling frequency */
+#define HDMITX_DWC_FC_AUDICONF1 (DWC_OFFSET_MASK + 0x1026)
+/* CA: channel allocation */
+#define HDMITX_DWC_FC_AUDICONF2 (DWC_OFFSET_MASK + 0x1027)
+/* [6:5] LFEPBL: LFE playback info */
+/* [ 4] DM_INH: down mix enable */
+/* [3:0] LSv: Level shift value */
+#define HDMITX_DWC_FC_AUDICONF3 (DWC_OFFSET_MASK + 0x1028)
+#define HDMITX_DWC_FC_VSDIEEEID0 (DWC_OFFSET_MASK + 0x1029)
+#define HDMITX_DWC_FC_VSDSIZE (DWC_OFFSET_MASK + 0x102A)
+#define HDMITX_DWC_FC_VSDIEEEID1 (DWC_OFFSET_MASK + 0x1030)
+#define HDMITX_DWC_FC_VSDIEEEID2 (DWC_OFFSET_MASK + 0x1031)
+#define HDMITX_DWC_FC_VSDPAYLOAD0 (DWC_OFFSET_MASK + 0x1032)
+#define HDMITX_DWC_FC_VSDPAYLOAD1 (DWC_OFFSET_MASK + 0x1033)
+#define HDMITX_DWC_FC_VSDPAYLOAD2 (DWC_OFFSET_MASK + 0x1034)
+#define HDMITX_DWC_FC_VSDPAYLOAD3 (DWC_OFFSET_MASK + 0x1035)
+#define HDMITX_DWC_FC_VSDPAYLOAD4 (DWC_OFFSET_MASK + 0x1036)
+#define HDMITX_DWC_FC_VSDPAYLOAD5 (DWC_OFFSET_MASK + 0x1037)
+#define HDMITX_DWC_FC_VSDPAYLOAD6 (DWC_OFFSET_MASK + 0x1038)
+#define HDMITX_DWC_FC_VSDPAYLOAD7 (DWC_OFFSET_MASK + 0x1039)
+#define HDMITX_DWC_FC_VSDPAYLOAD8 (DWC_OFFSET_MASK + 0x103A)
+#define HDMITX_DWC_FC_VSDPAYLOAD9 (DWC_OFFSET_MASK + 0x103B)
+#define HDMITX_DWC_FC_VSDPAYLOAD10 (DWC_OFFSET_MASK + 0x103C)
+#define HDMITX_DWC_FC_VSDPAYLOAD11 (DWC_OFFSET_MASK + 0x103D)
+#define HDMITX_DWC_FC_VSDPAYLOAD12 (DWC_OFFSET_MASK + 0x103E)
+#define HDMITX_DWC_FC_VSDPAYLOAD13 (DWC_OFFSET_MASK + 0x103F)
+#define HDMITX_DWC_FC_VSDPAYLOAD14 (DWC_OFFSET_MASK + 0x1040)
+#define HDMITX_DWC_FC_VSDPAYLOAD15 (DWC_OFFSET_MASK + 0x1041)
+#define HDMITX_DWC_FC_VSDPAYLOAD16 (DWC_OFFSET_MASK + 0x1042)
+#define HDMITX_DWC_FC_VSDPAYLOAD17 (DWC_OFFSET_MASK + 0x1043)
+#define HDMITX_DWC_FC_VSDPAYLOAD18 (DWC_OFFSET_MASK + 0x1044)
+#define HDMITX_DWC_FC_VSDPAYLOAD19 (DWC_OFFSET_MASK + 0x1045)
+#define HDMITX_DWC_FC_VSDPAYLOAD20 (DWC_OFFSET_MASK + 0x1046)
+#define HDMITX_DWC_FC_VSDPAYLOAD21 (DWC_OFFSET_MASK + 0x1047)
+#define HDMITX_DWC_FC_VSDPAYLOAD22 (DWC_OFFSET_MASK + 0x1048)
+#define HDMITX_DWC_FC_VSDPAYLOAD23 (DWC_OFFSET_MASK + 0x1049)
+#define HDMITX_DWC_FC_SPDVENDORNAME0 (DWC_OFFSET_MASK + 0x104A)
+#define HDMITX_DWC_FC_SPDVENDORNAME1 (DWC_OFFSET_MASK + 0x104B)
+#define HDMITX_DWC_FC_SPDVENDORNAME2 (DWC_OFFSET_MASK + 0x104C)
+#define HDMITX_DWC_FC_SPDVENDORNAME3 (DWC_OFFSET_MASK + 0x104D)
+#define HDMITX_DWC_FC_SPDVENDORNAME4 (DWC_OFFSET_MASK + 0x104E)
+#define HDMITX_DWC_FC_SPDVENDORNAME5 (DWC_OFFSET_MASK + 0x104F)
+#define HDMITX_DWC_FC_SPDVENDORNAME6 (DWC_OFFSET_MASK + 0x1050)
+#define HDMITX_DWC_FC_SPDVENDORNAME7 (DWC_OFFSET_MASK + 0x1051)
+#define HDMITX_DWC_FC_SDPPRODUCTNAME0 (DWC_OFFSET_MASK + 0x1052)
+#define HDMITX_DWC_FC_SDPPRODUCTNAME1 (DWC_OFFSET_MASK + 0x1053)
+#define HDMITX_DWC_FC_SDPPRODUCTNAME2 (DWC_OFFSET_MASK + 0x1054)
+#define HDMITX_DWC_FC_SDPPRODUCTNAME3 (DWC_OFFSET_MASK + 0x1055)
+#define HDMITX_DWC_FC_SDPPRODUCTNAME4 (DWC_OFFSET_MASK + 0x1056)
+#define HDMITX_DWC_FC_SDPPRODUCTNAME5 (DWC_OFFSET_MASK + 0x1057)
+#define HDMITX_DWC_FC_SDPPRODUCTNAME6 (DWC_OFFSET_MASK + 0x1058)
+#define HDMITX_DWC_FC_SDPPRODUCTNAME7 (DWC_OFFSET_MASK + 0x1059)
+#define HDMITX_DWC_FC_SDPPRODUCTNAME8 (DWC_OFFSET_MASK + 0x105A)
+#define HDMITX_DWC_FC_SDPPRODUCTNAME9 (DWC_OFFSET_MASK + 0x105B)
+#define HDMITX_DWC_FC_SDPPRODUCTNAME10 (DWC_OFFSET_MASK + 0x105C)
+#define HDMITX_DWC_FC_SDPPRODUCTNAME11 (DWC_OFFSET_MASK + 0x105D)
+#define HDMITX_DWC_FC_SDPPRODUCTNAME12 (DWC_OFFSET_MASK + 0x105E)
+#define HDMITX_DWC_FC_SDPPRODUCTNAME13 (DWC_OFFSET_MASK + 0x105F)
+#define HDMITX_DWC_FC_SDPPRODUCTNAME14 (DWC_OFFSET_MASK + 0x1060)
+#define HDMITX_DWC_FC_SPDPRODUCTNAME15 (DWC_OFFSET_MASK + 0x1061)
+#define HDMITX_DWC_FC_SPDDEVICEINF (DWC_OFFSET_MASK + 0x1062)
+/* [7:4] aud_packet_sampflat */
+/* [ 0] aud_packet_layout */
+#define HDMITX_DWC_FC_AUDSCONF (DWC_OFFSET_MASK + 0x1063)
+#define HDMITX_DWC_FC_AUDSSTAT (DWC_OFFSET_MASK + 0x1064)
+/* [ 7] V3r */
+/* [ 6] V2r */
+/* [ 5] V1r */
+/* [ 4] V0r */
+/* [ 3] V3l */
+/* [ 2] V2l */
+/* [ 1] V1l */
+/* [ 0] V0l */
+#define HDMITX_DWC_FC_AUDSV (DWC_OFFSET_MASK + 0x1065)
+#define HDMITX_DWC_FC_AUDSU (DWC_OFFSET_MASK + 0x1066)
+#define HDMITX_DWC_FC_AUDSCHNLS0 (DWC_OFFSET_MASK + 0x1067)
+#define HDMITX_DWC_FC_AUDSCHNLS1 (DWC_OFFSET_MASK + 0x1068)
+#define HDMITX_DWC_FC_AUDSCHNLS2 (DWC_OFFSET_MASK + 0x1069)
+#define HDMITX_DWC_FC_AUDSCHNLS3 (DWC_OFFSET_MASK + 0x106A)
+#define HDMITX_DWC_FC_AUDSCHNLS4 (DWC_OFFSET_MASK + 0x106B)
+#define HDMITX_DWC_FC_AUDSCHNLS5 (DWC_OFFSET_MASK + 0x106C)
+#define HDMITX_DWC_FC_AUDSCHNLS6 (DWC_OFFSET_MASK + 0x106D)
+#define HDMITX_DWC_FC_AUDSCHNLS7 (DWC_OFFSET_MASK + 0x106E)
+#define HDMITX_DWC_FC_AUDSCHNLS8 (DWC_OFFSET_MASK + 0x106F)
+#define HDMITX_DWC_FC_DATACH0FILL (DWC_OFFSET_MASK + 0x1070)
+#define HDMITX_DWC_FC_DATACH1FILL (DWC_OFFSET_MASK + 0x1071)
+#define HDMITX_DWC_FC_DATACH2FILL (DWC_OFFSET_MASK + 0x1072)
+#define HDMITX_DWC_FC_CTRLQHIGH (DWC_OFFSET_MASK + 0x1073)
+#define HDMITX_DWC_FC_CTRLQLOW (DWC_OFFSET_MASK + 0x1074)
+#define HDMITX_DWC_FC_ACP0 (DWC_OFFSET_MASK + 0x1075)
+#define HDMITX_DWC_FC_ACP16 (DWC_OFFSET_MASK + 0x1082)
+#define HDMITX_DWC_FC_ACP15 (DWC_OFFSET_MASK + 0x1083)
+#define HDMITX_DWC_FC_ACP14 (DWC_OFFSET_MASK + 0x1084)
+#define HDMITX_DWC_FC_ACP13 (DWC_OFFSET_MASK + 0x1085)
+#define HDMITX_DWC_FC_ACP12 (DWC_OFFSET_MASK + 0x1086)
+#define HDMITX_DWC_FC_ACP11 (DWC_OFFSET_MASK + 0x1087)
+#define HDMITX_DWC_FC_ACP10 (DWC_OFFSET_MASK + 0x1088)
+#define HDMITX_DWC_FC_ACP9 (DWC_OFFSET_MASK + 0x1089)
+#define HDMITX_DWC_FC_ACP8 (DWC_OFFSET_MASK + 0x108A)
+#define HDMITX_DWC_FC_ACP7 (DWC_OFFSET_MASK + 0x108B)
+#define HDMITX_DWC_FC_ACP6 (DWC_OFFSET_MASK + 0x108C)
+#define HDMITX_DWC_FC_ACP5 (DWC_OFFSET_MASK + 0x108D)
+#define HDMITX_DWC_FC_ACP4 (DWC_OFFSET_MASK + 0x108E)
+#define HDMITX_DWC_FC_ACP3 (DWC_OFFSET_MASK + 0x108F)
+#define HDMITX_DWC_FC_ACP2 (DWC_OFFSET_MASK + 0x1090)
+#define HDMITX_DWC_FC_ACP1 (DWC_OFFSET_MASK + 0x1091)
+#define HDMITX_DWC_FC_ISCR1_0 (DWC_OFFSET_MASK + 0x1092)
+#define HDMITX_DWC_FC_ISCR1_16 (DWC_OFFSET_MASK + 0x1093)
+#define HDMITX_DWC_FC_ISCR1_15 (DWC_OFFSET_MASK + 0x1094)
+#define HDMITX_DWC_FC_ISCR1_14 (DWC_OFFSET_MASK + 0x1095)
+#define HDMITX_DWC_FC_ISCR1_13 (DWC_OFFSET_MASK + 0x1096)
+#define HDMITX_DWC_FC_ISCR1_12 (DWC_OFFSET_MASK + 0x1097)
+#define HDMITX_DWC_FC_ISCR1_11 (DWC_OFFSET_MASK + 0x1098)
+#define HDMITX_DWC_FC_ISCR1_10 (DWC_OFFSET_MASK + 0x1099)
+#define HDMITX_DWC_FC_ISCR1_9 (DWC_OFFSET_MASK + 0x109A)
+#define HDMITX_DWC_FC_ISCR1_8 (DWC_OFFSET_MASK + 0x109B)
+#define HDMITX_DWC_FC_ISCR1_7 (DWC_OFFSET_MASK + 0x109C)
+#define HDMITX_DWC_FC_ISCR1_6 (DWC_OFFSET_MASK + 0x109D)
+#define HDMITX_DWC_FC_ISCR1_5 (DWC_OFFSET_MASK + 0x109E)
+#define HDMITX_DWC_FC_ISCR1_4 (DWC_OFFSET_MASK + 0x109F)
+#define HDMITX_DWC_FC_ISCR1_3 (DWC_OFFSET_MASK + 0x10A0)
+#define HDMITX_DWC_FC_ISCR1_2 (DWC_OFFSET_MASK + 0x10A1)
+#define HDMITX_DWC_FC_ISCR1_1 (DWC_OFFSET_MASK + 0x10A2)
+#define HDMITX_DWC_FC_ISCR0_15 (DWC_OFFSET_MASK + 0x10A3)
+#define HDMITX_DWC_FC_ISCR0_14 (DWC_OFFSET_MASK + 0x10A4)
+#define HDMITX_DWC_FC_ISCR0_13 (DWC_OFFSET_MASK + 0x10A5)
+#define HDMITX_DWC_FC_ISCR0_12 (DWC_OFFSET_MASK + 0x10A6)
+#define HDMITX_DWC_FC_ISCR0_11 (DWC_OFFSET_MASK + 0x10A7)
+#define HDMITX_DWC_FC_ISCR0_10 (DWC_OFFSET_MASK + 0x10A8)
+#define HDMITX_DWC_FC_ISCR0_9 (DWC_OFFSET_MASK + 0x10A9)
+#define HDMITX_DWC_FC_ISCR0_8 (DWC_OFFSET_MASK + 0x10AA)
+#define HDMITX_DWC_FC_ISCR0_7 (DWC_OFFSET_MASK + 0x10AB)
+#define HDMITX_DWC_FC_ISCR0_6 (DWC_OFFSET_MASK + 0x10AC)
+#define HDMITX_DWC_FC_ISCR0_5 (DWC_OFFSET_MASK + 0x10AD)
+#define HDMITX_DWC_FC_ISCR0_4 (DWC_OFFSET_MASK + 0x10AE)
+#define HDMITX_DWC_FC_ISCR0_3 (DWC_OFFSET_MASK + 0x10AF)
+#define HDMITX_DWC_FC_ISCR0_2 (DWC_OFFSET_MASK + 0x10B0)
+#define HDMITX_DWC_FC_ISCR0_1 (DWC_OFFSET_MASK + 0x10B1)
+#define HDMITX_DWC_FC_ISCR0_0 (DWC_OFFSET_MASK + 0x10B2)
+/* [ 4] spd_auto */
+/* [ 3] vsd_auto */
+/* [ 2] isrc2_auto */
+/* [ 1] isrc1_auto */
+/* [ 0] acp_auto */
+#define HDMITX_DWC_FC_DATAUTO0 (DWC_OFFSET_MASK + 0x10B3)
+#define HDMITX_DWC_FC_DATAUTO1 (DWC_OFFSET_MASK + 0x10B4)
+#define HDMITX_DWC_FC_DATAUTO2 (DWC_OFFSET_MASK + 0x10B5)
+#define HDMITX_DWC_FC_DATMAN (DWC_OFFSET_MASK + 0x10B6)
+/* [ 5] nvbi_auto: insert on Vsync */
+/* [ 4] amp_auto: insert on Vsync */
+/* [ 3] avi_auto: insert on Vsync */
+/* [ 2] gcp_auto: insert on Vsync */
+/* [ 1] audi_auto: insert on Vsync */
+/* [ 0] acr_auto: insert on CTS update. Assert this bit later to avoid
+ * inital packets with false CTS value
+ */
+#define HDMITX_DWC_FC_DATAUTO3 (DWC_OFFSET_MASK + 0x10B7)
+#define HDMITX_DWC_FC_RDRB0 (DWC_OFFSET_MASK + 0x10B8)
+#define HDMITX_DWC_FC_RDRB1 (DWC_OFFSET_MASK + 0x10B9)
+#define HDMITX_DWC_FC_RDRB2 (DWC_OFFSET_MASK + 0x10BA)
+#define HDMITX_DWC_FC_RDRB3 (DWC_OFFSET_MASK + 0x10BB)
+#define HDMITX_DWC_FC_RDRB4 (DWC_OFFSET_MASK + 0x10BC)
+#define HDMITX_DWC_FC_RDRB5 (DWC_OFFSET_MASK + 0x10BD)
+#define HDMITX_DWC_FC_RDRB6 (DWC_OFFSET_MASK + 0x10BE)
+#define HDMITX_DWC_FC_RDRB7 (DWC_OFFSET_MASK + 0x10BF)
+#define HDMITX_DWC_FC_RDRB8 (DWC_OFFSET_MASK + 0x10C0)
+#define HDMITX_DWC_FC_RDRB9 (DWC_OFFSET_MASK + 0x10C1)
+#define HDMITX_DWC_FC_RDRB10 (DWC_OFFSET_MASK + 0x10C2)
+#define HDMITX_DWC_FC_RDRB11 (DWC_OFFSET_MASK + 0x10C3)
+/* [ 7] AUDI_int_mask */
+/* [ 6] ACP_int_mask */
+/* [ 5] HBR_int_mask */
+/* [ 2] AUDS_int_mask */
+/* [ 1] ACR_int_mask */
+/* [ 0] NULL_int_mask */
+#define HDMITX_DWC_FC_MASK0 (DWC_OFFSET_MASK + 0x10D2)
+/* [ 7] GMD_int_mask */
+/* [ 6] ISRC1_int_mask */
+/* [ 5] ISRC2_int_mask */
+/* [ 4] VSD_int_mask */
+/* [ 3] SPD_int_mask */
+/* [ 1] AVI_int_mask */
+/* [ 0] GCP_int_mask */
+#define HDMITX_DWC_FC_MASK1 (DWC_OFFSET_MASK + 0x10D6)
+/* [ 1] LowPriority_fifo_full */
+/* [ 0] HighPriority_fifo_full */
+#define HDMITX_DWC_FC_MASK2 (DWC_OFFSET_MASK + 0x10DA)
+/* [7:4] incoming_pr_factor */
+/* [3:0] output_pr_factor */
+#define HDMITX_DWC_FC_PRCONF (DWC_OFFSET_MASK + 0x10E0)
+/* [ 4] scrambler_ucp_line */
+/* [ 0] scrambler_en. Only update this bit once we've sent SCDC message*/
+#define HDMITX_DWC_FC_SCRAMBLER_CTRL (DWC_OFFSET_MASK + 0x10E1)
+#define HDMITX_DWC_FC_MULTISTREAM_CTRL (DWC_OFFSET_MASK + 0x10E2)
+/* [ 6] nvbi_tx_en */
+/* [ 5] amp_tx_en */
+/* [ 4] aut_tx_en */
+/* [ 3] audi_tx_en */
+/* [ 2] avi_tx_en */
+/* [ 1] gcp_tx_en */
+/* [ 0] acr_tx_en */
+#define HDMITX_DWC_FC_PACKET_TX_EN (DWC_OFFSET_MASK + 0x10E3)
+/* [ 1] actspc_hdlr_tgl */
+/* [ 0] actspc_hdlr_en */
+#define HDMITX_DWC_FC_ACTSPC_HDLR_CFG (DWC_OFFSET_MASK + 0x10E8)
+#define HDMITX_DWC_FC_INVACT_2D_0 (DWC_OFFSET_MASK + 0x10E9)
+/* [3:0] fc_invact_2d_0[11:8] */
+/* [7:0] fc_invact_2d_0[7:0] */
+#define HDMITX_DWC_FC_INVACT_2D_1 (DWC_OFFSET_MASK + 0x10EA)
+
+#define HDMITX_DWC_FC_GMD_STAT (DWC_OFFSET_MASK + 0x1100)
+#define HDMITX_DWC_FC_GMD_EN (DWC_OFFSET_MASK + 0x1101)
+#define HDMITX_DWC_FC_GMD_UP (DWC_OFFSET_MASK + 0x1102)
+#define HDMITX_DWC_FC_GMD_CONF (DWC_OFFSET_MASK + 0x1103)
+#define HDMITX_DWC_FC_GMD_HB (DWC_OFFSET_MASK + 0x1104)
+#define HDMITX_DWC_FC_GMD_PB0 (DWC_OFFSET_MASK + 0x1105)
+#define HDMITX_DWC_FC_GMD_PB1 (DWC_OFFSET_MASK + 0x1106)
+#define HDMITX_DWC_FC_GMD_PB2 (DWC_OFFSET_MASK + 0x1107)
+#define HDMITX_DWC_FC_GMD_PB3 (DWC_OFFSET_MASK + 0x1108)
+#define HDMITX_DWC_FC_GMD_PB4 (DWC_OFFSET_MASK + 0x1109)
+#define HDMITX_DWC_FC_GMD_PB5 (DWC_OFFSET_MASK + 0x110A)
+#define HDMITX_DWC_FC_GMD_PB6 (DWC_OFFSET_MASK + 0x110B)
+#define HDMITX_DWC_FC_GMD_PB7 (DWC_OFFSET_MASK + 0x110C)
+#define HDMITX_DWC_FC_GMD_PB8 (DWC_OFFSET_MASK + 0x110D)
+#define HDMITX_DWC_FC_GMD_PB9 (DWC_OFFSET_MASK + 0x110E)
+#define HDMITX_DWC_FC_GMD_PB10 (DWC_OFFSET_MASK + 0x110F)
+#define HDMITX_DWC_FC_GMD_PB11 (DWC_OFFSET_MASK + 0x1110)
+#define HDMITX_DWC_FC_GMD_PB12 (DWC_OFFSET_MASK + 0x1111)
+#define HDMITX_DWC_FC_GMD_PB13 (DWC_OFFSET_MASK + 0x1112)
+#define HDMITX_DWC_FC_GMD_PB14 (DWC_OFFSET_MASK + 0x1113)
+#define HDMITX_DWC_FC_GMD_PB15 (DWC_OFFSET_MASK + 0x1114)
+#define HDMITX_DWC_FC_GMD_PB16 (DWC_OFFSET_MASK + 0x1115)
+#define HDMITX_DWC_FC_GMD_PB17 (DWC_OFFSET_MASK + 0x1116)
+#define HDMITX_DWC_FC_GMD_PB18 (DWC_OFFSET_MASK + 0x1117)
+#define HDMITX_DWC_FC_GMD_PB19 (DWC_OFFSET_MASK + 0x1118)
+#define HDMITX_DWC_FC_GMD_PB20 (DWC_OFFSET_MASK + 0x1119)
+#define HDMITX_DWC_FC_GMD_PB21 (DWC_OFFSET_MASK + 0x111A)
+#define HDMITX_DWC_FC_GMD_PB22 (DWC_OFFSET_MASK + 0x111B)
+#define HDMITX_DWC_FC_GMD_PB23 (DWC_OFFSET_MASK + 0x111C)
+#define HDMITX_DWC_FC_GMD_PB24 (DWC_OFFSET_MASK + 0x111D)
+#define HDMITX_DWC_FC_GMD_PB25 (DWC_OFFSET_MASK + 0x111E)
+#define HDMITX_DWC_FC_GMD_PB26 (DWC_OFFSET_MASK + 0x111F)
+#define HDMITX_DWC_FC_GMD_PB27 (DWC_OFFSET_MASK + 0x1120)
+
+/* Audio Metadata Packet Registers */
+#define HDMITX_DWC_FC_AMP_HB01 (DWC_OFFSET_MASK + 0x1128)
+#define HDMITX_DWC_FC_AMP_HB02 (DWC_OFFSET_MASK + 0x1129)
+#define HDMITX_DWC_FC_AMP_PB00 (DWC_OFFSET_MASK + 0x112A)
+#define HDMITX_DWC_FC_AMP_PB01 (DWC_OFFSET_MASK + 0x112B)
+#define HDMITX_DWC_FC_AMP_PB02 (DWC_OFFSET_MASK + 0x112C)
+#define HDMITX_DWC_FC_AMP_PB03 (DWC_OFFSET_MASK + 0x112D)
+#define HDMITX_DWC_FC_AMP_PB04 (DWC_OFFSET_MASK + 0x112E)
+#define HDMITX_DWC_FC_AMP_PB05 (DWC_OFFSET_MASK + 0x112F)
+#define HDMITX_DWC_FC_AMP_PB06 (DWC_OFFSET_MASK + 0x1130)
+#define HDMITX_DWC_FC_AMP_PB07 (DWC_OFFSET_MASK + 0x1131)
+#define HDMITX_DWC_FC_AMP_PB08 (DWC_OFFSET_MASK + 0x1132)
+#define HDMITX_DWC_FC_AMP_PB09 (DWC_OFFSET_MASK + 0x1133)
+#define HDMITX_DWC_FC_AMP_PB10 (DWC_OFFSET_MASK + 0x1134)
+#define HDMITX_DWC_FC_AMP_PB11 (DWC_OFFSET_MASK + 0x1135)
+#define HDMITX_DWC_FC_AMP_PB12 (DWC_OFFSET_MASK + 0x1136)
+#define HDMITX_DWC_FC_AMP_PB13 (DWC_OFFSET_MASK + 0x1137)
+#define HDMITX_DWC_FC_AMP_PB14 (DWC_OFFSET_MASK + 0x1138)
+#define HDMITX_DWC_FC_AMP_PB15 (DWC_OFFSET_MASK + 0x1139)
+#define HDMITX_DWC_FC_AMP_PB16 (DWC_OFFSET_MASK + 0x113A)
+#define HDMITX_DWC_FC_AMP_PB17 (DWC_OFFSET_MASK + 0x113B)
+#define HDMITX_DWC_FC_AMP_PB18 (DWC_OFFSET_MASK + 0x113C)
+#define HDMITX_DWC_FC_AMP_PB19 (DWC_OFFSET_MASK + 0x113D)
+#define HDMITX_DWC_FC_AMP_PB20 (DWC_OFFSET_MASK + 0x113E)
+#define HDMITX_DWC_FC_AMP_PB21 (DWC_OFFSET_MASK + 0x113F)
+#define HDMITX_DWC_FC_AMP_PB22 (DWC_OFFSET_MASK + 0x1140)
+#define HDMITX_DWC_FC_AMP_PB23 (DWC_OFFSET_MASK + 0x1141)
+#define HDMITX_DWC_FC_AMP_PB24 (DWC_OFFSET_MASK + 0x1142)
+#define HDMITX_DWC_FC_AMP_PB25 (DWC_OFFSET_MASK + 0x1143)
+#define HDMITX_DWC_FC_AMP_PB26 (DWC_OFFSET_MASK + 0x1144)
+#define HDMITX_DWC_FC_AMP_PB27 (DWC_OFFSET_MASK + 0x1145)
+
+/* NTSC VBI Packet Registers */
+#define HDMITX_DWC_FC_NVBI_HB01 (DWC_OFFSET_MASK + 0x1148)
+#define HDMITX_DWC_FC_NVBI_HB02 (DWC_OFFSET_MASK + 0x1149)
+#define HDMITX_DWC_FC_NVBI_PB01 (DWC_OFFSET_MASK + 0x114A)
+#define HDMITX_DWC_FC_NVBI_PB02 (DWC_OFFSET_MASK + 0x114B)
+#define HDMITX_DWC_FC_NVBI_PB03 (DWC_OFFSET_MASK + 0x114C)
+#define HDMITX_DWC_FC_NVBI_PB04 (DWC_OFFSET_MASK + 0x114D)
+#define HDMITX_DWC_FC_NVBI_PB05 (DWC_OFFSET_MASK + 0x114E)
+#define HDMITX_DWC_FC_NVBI_PB06 (DWC_OFFSET_MASK + 0x114F)
+#define HDMITX_DWC_FC_NVBI_PB07 (DWC_OFFSET_MASK + 0x1150)
+#define HDMITX_DWC_FC_NVBI_PB08 (DWC_OFFSET_MASK + 0x1151)
+#define HDMITX_DWC_FC_NVBI_PB09 (DWC_OFFSET_MASK + 0x1152)
+#define HDMITX_DWC_FC_NVBI_PB10 (DWC_OFFSET_MASK + 0x1153)
+#define HDMITX_DWC_FC_NVBI_PB11 (DWC_OFFSET_MASK + 0x1154)
+#define HDMITX_DWC_FC_NVBI_PB12 (DWC_OFFSET_MASK + 0x1155)
+#define HDMITX_DWC_FC_NVBI_PB13 (DWC_OFFSET_MASK + 0x1156)
+#define HDMITX_DWC_FC_NVBI_PB14 (DWC_OFFSET_MASK + 0x1157)
+#define HDMITX_DWC_FC_NVBI_PB15 (DWC_OFFSET_MASK + 0x1158)
+#define HDMITX_DWC_FC_NVBI_PB16 (DWC_OFFSET_MASK + 0x1159)
+#define HDMITX_DWC_FC_NVBI_PB17 (DWC_OFFSET_MASK + 0x115A)
+#define HDMITX_DWC_FC_NVBI_PB18 (DWC_OFFSET_MASK + 0x115B)
+#define HDMITX_DWC_FC_NVBI_PB19 (DWC_OFFSET_MASK + 0x115C)
+#define HDMITX_DWC_FC_NVBI_PB20 (DWC_OFFSET_MASK + 0x115D)
+#define HDMITX_DWC_FC_NVBI_PB21 (DWC_OFFSET_MASK + 0x115E)
+#define HDMITX_DWC_FC_NVBI_PB22 (DWC_OFFSET_MASK + 0x115F)
+#define HDMITX_DWC_FC_NVBI_PB23 (DWC_OFFSET_MASK + 0x1160)
+#define HDMITX_DWC_FC_NVBI_PB24 (DWC_OFFSET_MASK + 0x1161)
+#define HDMITX_DWC_FC_NVBI_PB25 (DWC_OFFSET_MASK + 0x1162)
+#define HDMITX_DWC_FC_NVBI_PB26 (DWC_OFFSET_MASK + 0x1163)
+#define HDMITX_DWC_FC_NVBI_PB27 (DWC_OFFSET_MASK + 0x1164)
+#define HDMITX_DWC_FC_DRM_HB01 (DWC_OFFSET_MASK + 0x1168)
+#define HDMITX_DWC_FC_DRM_HB02 (DWC_OFFSET_MASK + 0x1169)
+#define HDMITX_DWC_FC_DRM_PB00 (DWC_OFFSET_MASK + 0x116A)
+#define HDMITX_DWC_FC_DRM_PB01 (DWC_OFFSET_MASK + 0x116B)
+#define HDMITX_DWC_FC_DRM_PB02 (DWC_OFFSET_MASK + 0x116C)
+#define HDMITX_DWC_FC_DRM_PB03 (DWC_OFFSET_MASK + 0x116D)
+#define HDMITX_DWC_FC_DRM_PB04 (DWC_OFFSET_MASK + 0x116E)
+#define HDMITX_DWC_FC_DRM_PB05 (DWC_OFFSET_MASK + 0x116F)
+#define HDMITX_DWC_FC_DRM_PB06 (DWC_OFFSET_MASK + 0x1170)
+#define HDMITX_DWC_FC_DRM_PB07 (DWC_OFFSET_MASK + 0x1171)
+#define HDMITX_DWC_FC_DRM_PB08 (DWC_OFFSET_MASK + 0x1172)
+#define HDMITX_DWC_FC_DRM_PB09 (DWC_OFFSET_MASK + 0x1173)
+#define HDMITX_DWC_FC_DRM_PB10 (DWC_OFFSET_MASK + 0x1174)
+#define HDMITX_DWC_FC_DRM_PB11 (DWC_OFFSET_MASK + 0x1175)
+#define HDMITX_DWC_FC_DRM_PB12 (DWC_OFFSET_MASK + 0x1176)
+#define HDMITX_DWC_FC_DRM_PB13 (DWC_OFFSET_MASK + 0x1177)
+#define HDMITX_DWC_FC_DRM_PB14 (DWC_OFFSET_MASK + 0x1178)
+#define HDMITX_DWC_FC_DRM_PB15 (DWC_OFFSET_MASK + 0x1179)
+#define HDMITX_DWC_FC_DRM_PB16 (DWC_OFFSET_MASK + 0x117A)
+#define HDMITX_DWC_FC_DRM_PB17 (DWC_OFFSET_MASK + 0x117B)
+#define HDMITX_DWC_FC_DRM_PB18 (DWC_OFFSET_MASK + 0x117C)
+#define HDMITX_DWC_FC_DRM_PB19 (DWC_OFFSET_MASK + 0x117D)
+#define HDMITX_DWC_FC_DRM_PB20 (DWC_OFFSET_MASK + 0x117E)
+#define HDMITX_DWC_FC_DRM_PB21 (DWC_OFFSET_MASK + 0x117F)
+#define HDMITX_DWC_FC_DRM_PB22 (DWC_OFFSET_MASK + 0x1180)
+#define HDMITX_DWC_FC_DRM_PB23 (DWC_OFFSET_MASK + 0x1181)
+#define HDMITX_DWC_FC_DRM_PB24 (DWC_OFFSET_MASK + 0x1182)
+#define HDMITX_DWC_FC_DRM_PB25 (DWC_OFFSET_MASK + 0x1183)
+#define HDMITX_DWC_FC_DRM_PB26 (DWC_OFFSET_MASK + 0x1184)
+
+#define HDMITX_DWC_FC_DBGFORCE (DWC_OFFSET_MASK + 0x1200)
+#define HDMITX_DWC_FC_DBGAUD0CH0 (DWC_OFFSET_MASK + 0x1201)
+#define HDMITX_DWC_FC_DBGAUD1CH0 (DWC_OFFSET_MASK + 0x1202)
+#define HDMITX_DWC_FC_DBGAUD2CH0 (DWC_OFFSET_MASK + 0x1203)
+#define HDMITX_DWC_FC_DBGAUD0CH1 (DWC_OFFSET_MASK + 0x1204)
+#define HDMITX_DWC_FC_DBGAUD1CH1 (DWC_OFFSET_MASK + 0x1205)
+#define HDMITX_DWC_FC_DBGAUD2CH1 (DWC_OFFSET_MASK + 0x1206)
+#define HDMITX_DWC_FC_DBGAUD0CH2 (DWC_OFFSET_MASK + 0x1207)
+#define HDMITX_DWC_FC_DBGAUD1CH2 (DWC_OFFSET_MASK + 0x1208)
+#define HDMITX_DWC_FC_DBGAUD2CH2 (DWC_OFFSET_MASK + 0x1209)
+#define HDMITX_DWC_FC_DBGAUD0CH3 (DWC_OFFSET_MASK + 0x120A)
+#define HDMITX_DWC_FC_DBGAUD1CH3 (DWC_OFFSET_MASK + 0x120B)
+#define HDMITX_DWC_FC_DBGAUD2CH3 (DWC_OFFSET_MASK + 0x120C)
+#define HDMITX_DWC_FC_DBGAUD0CH4 (DWC_OFFSET_MASK + 0x120D)
+#define HDMITX_DWC_FC_DBGAUD1CH4 (DWC_OFFSET_MASK + 0x120E)
+#define HDMITX_DWC_FC_DBGAUD2CH4 (DWC_OFFSET_MASK + 0x120F)
+#define HDMITX_DWC_FC_DBGAUD0CH5 (DWC_OFFSET_MASK + 0x1210)
+#define HDMITX_DWC_FC_DBGAUD1CH5 (DWC_OFFSET_MASK + 0x1211)
+#define HDMITX_DWC_FC_DBGAUD2CH5 (DWC_OFFSET_MASK + 0x1212)
+#define HDMITX_DWC_FC_DBGAUD0CH6 (DWC_OFFSET_MASK + 0x1213)
+#define HDMITX_DWC_FC_DBGAUD1CH6 (DWC_OFFSET_MASK + 0x1214)
+#define HDMITX_DWC_FC_DBGAUD2CH6 (DWC_OFFSET_MASK + 0x1215)
+#define HDMITX_DWC_FC_DBGAUD0CH7 (DWC_OFFSET_MASK + 0x1216)
+#define HDMITX_DWC_FC_DBGAUD1CH7 (DWC_OFFSET_MASK + 0x1217)
+#define HDMITX_DWC_FC_DBGAUD2CH7 (DWC_OFFSET_MASK + 0x1218)
+#define HDMITX_DWC_FC_DBGTMDS0 (DWC_OFFSET_MASK + 0x1219)
+#define HDMITX_DWC_FC_DBGTMDS1 (DWC_OFFSET_MASK + 0x121A)
+#define HDMITX_DWC_FC_DBGTMDS2 (DWC_OFFSET_MASK + 0x121B)
+
+/* HDMI Source PHY Registers */
+#define HDMITX_DWC_PHY_CONF0 (DWC_OFFSET_MASK + 0x3000)
+#define HDMITX_DWC_PHY_TST0 (DWC_OFFSET_MASK + 0x3001)
+#define HDMITX_DWC_PHY_TST1 (DWC_OFFSET_MASK + 0x3002)
+#define HDMITX_DWC_PHY_TST2 (DWC_OFFSET_MASK + 0x3003)
+#define HDMITX_DWC_PHY_STAT0 (DWC_OFFSET_MASK + 0x3004)
+#define HDMITX_DWC_PHY_INT0 (DWC_OFFSET_MASK + 0x3005)
+#define HDMITX_DWC_PHY_MASK0 (DWC_OFFSET_MASK + 0x3006)
+#define HDMITX_DWC_PHY_POL0 (DWC_OFFSET_MASK + 0x3007)
+
+/* I2C Master PHY Registers */
+#define HDMITX_DWC_I2CM_PHY_SLAVE (DWC_OFFSET_MASK + 0x3020)
+#define HDMITX_DWC_I2CM_PHY_ADDRESS (DWC_OFFSET_MASK + 0x3021)
+#define HDMITX_DWC_I2CM_PHY_DATAO_1 (DWC_OFFSET_MASK + 0x3022)
+#define HDMITX_DWC_I2CM_PHY_DATAO_0 (DWC_OFFSET_MASK + 0x3023)
+#define HDMITX_DWC_I2CM_PHY_DATAI_1 (DWC_OFFSET_MASK + 0x3024)
+#define HDMITX_DWC_I2CM_PHY_DATAI_0 (DWC_OFFSET_MASK + 0x3025)
+#define HDMITX_DWC_I2CM_PHY_OPERATION (DWC_OFFSET_MASK + 0x3026)
+#define HDMITX_DWC_I2CM_PHY_INT (DWC_OFFSET_MASK + 0x3027)
+#define HDMITX_DWC_I2CM_PHY_CTLINT (DWC_OFFSET_MASK + 0x3028)
+#define HDMITX_DWC_I2CM_PHY_DIV (DWC_OFFSET_MASK + 0x3029)
+#define HDMITX_DWC_I2CM_PHY_SOFTRSTZ (DWC_OFFSET_MASK + 0x302A)
+#define HDMITX_DWC_I2CM_PHY_SS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x302B)
+#define HDMITX_DWC_I2CM_PHY_SS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x302C)
+#define HDMITX_DWC_I2CM_PHY_SS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x302D)
+#define HDMITX_DWC_I2CM_PHY_SS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x302E)
+#define HDMITX_DWC_I2CM_PHY_FS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x302F)
+#define HDMITX_DWC_I2CM_PHY_FS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x3030)
+#define HDMITX_DWC_I2CM_PHY_FS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x3031)
+#define HDMITX_DWC_I2CM_PHY_FS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x3032)
+#define HDMITX_DWC_I2CM_PHY_SDA_HOLD (DWC_OFFSET_MASK + 0x3033)
+
+/* Audio Sampler Registers */
+
+ /* [ 7] sw_audio_fifo_rst */
+ /* [ 5] 0=select SPDIF; 1=select I2S. */
+ /* [3:0] i2s_in_en: enable it later in test.c */
+
+#define HDMITX_DWC_AUD_CONF0 (DWC_OFFSET_MASK + 0x3100)
+/* [4:0] i2s_width */
+/* [7:5] i2s_mode: 0=standard I2S mode */
+#define HDMITX_DWC_AUD_CONF1 (DWC_OFFSET_MASK + 0x3101)
+/* [ 3] fifo_empty_mask: 0=enable int; 1=mask int. */
+/* [ 2] fifo_full_mask: 0=enable int; 1=mask int. */
+#define HDMITX_DWC_AUD_INT (DWC_OFFSET_MASK + 0x3102)
+ /* [ 1] NLPCM */
+#define HDMITX_DWC_AUD_CONF2 (DWC_OFFSET_MASK + 0x3103)
+
+/* [ 4] fifo_overrun_mask: 0=enable int; 1=mask int.
+ * Enable it later when audio starts.
+ */
+#define HDMITX_DWC_AUD_INT1 (DWC_OFFSET_MASK + 0x3104)
+
+#define HDMITX_DWC_AUD_N1 (DWC_OFFSET_MASK + 0x3200)
+#define HDMITX_DWC_AUD_N2 (DWC_OFFSET_MASK + 0x3201)
+#define HDMITX_DWC_AUD_N3 (DWC_OFFSET_MASK + 0x3202)
+#define HDMITX_DWC_AUD_CTS1 (DWC_OFFSET_MASK + 0x3203)
+#define HDMITX_DWC_AUD_CTS2 (DWC_OFFSET_MASK + 0x3204)
+#define HDMITX_DWC_AUD_CTS3 (DWC_OFFSET_MASK + 0x3205)
+#define HDMITX_DWC_AUD_INPUTCLKFS (DWC_OFFSET_MASK + 0x3206)
+/* [ 7] sw_audio_fifo_rst */
+#define HDMITX_DWC_AUD_SPDIF0 (DWC_OFFSET_MASK + 0x3300)
+/* [4:0] spdif_width */
+/* [ 7] setnlpcm */
+#define HDMITX_DWC_AUD_SPDIF1 (DWC_OFFSET_MASK + 0x3301)
+/* [ 3] SPDIF fifo_empty_mask: 0=enable int; 1=mask int. */
+/* [ 2] SPDIF fifo_full_mask: 0=enable int; 1=mask int. */
+#define HDMITX_DWC_AUD_SPDIFINT (DWC_OFFSET_MASK + 0x3302)
+/* [ 4] SPDIF fifo_overrun_mask: 0=enable int; 1=mask int. */
+#define HDMITX_DWC_AUD_SPDIFINT1 (DWC_OFFSET_MASK + 0x3303)
+
+/* Generic Parallel Audio Interface Registers (DWC_OFFSET_MASK + 0x3500) */
+/* Audio DMA Registers (DWC_OFFSET_MASK + 0x3600) */
+
+/* Main Controller Registers */
+/* [ 6] hdcpclk_disable */
+/* [ 5] cecclk_disable */
+/* [ 4] cscclk_disable */
+/* [ 3] audclk_disable */
+/* [ 2] prepclk_disable */
+/* [ 1] tmdsclk_disable */
+/* [ 0] pixelclk_disable */
+#define HDMITX_DWC_MC_CLKDIS (DWC_OFFSET_MASK + 0x4001)
+/*
+ * [ 7] gpaswrst_req: 0=generate reset pulse; 1=no reset.
+ * [ 6] cecswrst_req: 0=generate reset pulse; 1=no reset.
+ * [ 4] spdifswrst_req: 0=generate reset pulse; 1=no reset.
+ * [ 3] i2sswrst_req: 0=generate reset pulse; 1=no reset.
+ * [ 2] prepswrst_req: 0=generate reset pulse; 1=no reset.
+ * [ 1] tmdsswrst_req: 0=generate reset pulse; 1=no reset.
+ * [ 0] pixelswrst_req: 0=generate reset pulse; 1=no reset.
+ */
+#define HDMITX_DWC_MC_SWRSTZREQ (DWC_OFFSET_MASK + 0x4002)
+#define HDMITX_DWC_MC_OPCTRL (DWC_OFFSET_MASK + 0x4003)
+/* [ 0] CSC enable */
+#define HDMITX_DWC_MC_FLOWCTRL (DWC_OFFSET_MASK + 0x4004)
+#define HDMITX_DWC_MC_PHYRSTZ (DWC_OFFSET_MASK + 0x4005)
+#define HDMITX_DWC_MC_LOCKONCLOCK (DWC_OFFSET_MASK + 0x4006)
+
+/* Color Space Converter Registers */
+/* [ 7] csc_limit */
+#define HDMITX_DWC_CSC_CFG (DWC_OFFSET_MASK + 0x4100)
+#define HDMITX_DWC_CSC_SCALE (DWC_OFFSET_MASK + 0x4101)
+#define HDMITX_DWC_CSC_COEF_A1_MSB (DWC_OFFSET_MASK + 0x4102)
+#define HDMITX_DWC_CSC_COEF_A1_LSB (DWC_OFFSET_MASK + 0x4103)
+#define HDMITX_DWC_CSC_COEF_A2_MSB (DWC_OFFSET_MASK + 0x4104)
+#define HDMITX_DWC_CSC_COEF_A2_LSB (DWC_OFFSET_MASK + 0x4105)
+#define HDMITX_DWC_CSC_COEF_A3_MSB (DWC_OFFSET_MASK + 0x4106)
+#define HDMITX_DWC_CSC_COEF_A3_LSB (DWC_OFFSET_MASK + 0x4107)
+#define HDMITX_DWC_CSC_COEF_A4_MSB (DWC_OFFSET_MASK + 0x4108)
+#define HDMITX_DWC_CSC_COEF_A4_LSB (DWC_OFFSET_MASK + 0x4109)
+#define HDMITX_DWC_CSC_COEF_B1_MSB (DWC_OFFSET_MASK + 0x410A)
+#define HDMITX_DWC_CSC_COEF_B1_LSB (DWC_OFFSET_MASK + 0x410B)
+#define HDMITX_DWC_CSC_COEF_B2_MSB (DWC_OFFSET_MASK + 0x410C)
+#define HDMITX_DWC_CSC_COEF_B2_LSB (DWC_OFFSET_MASK + 0x410D)
+#define HDMITX_DWC_CSC_COEF_B3_MSB (DWC_OFFSET_MASK + 0x410E)
+#define HDMITX_DWC_CSC_COEF_B3_LSB (DWC_OFFSET_MASK + 0x410F)
+#define HDMITX_DWC_CSC_COEF_B4_MSB (DWC_OFFSET_MASK + 0x4110)
+#define HDMITX_DWC_CSC_COEF_B4_LSB (DWC_OFFSET_MASK + 0x4111)
+#define HDMITX_DWC_CSC_COEF_C1_MSB (DWC_OFFSET_MASK + 0x4112)
+#define HDMITX_DWC_CSC_COEF_C1_LSB (DWC_OFFSET_MASK + 0x4113)
+#define HDMITX_DWC_CSC_COEF_C2_MSB (DWC_OFFSET_MASK + 0x4114)
+#define HDMITX_DWC_CSC_COEF_C2_LSB (DWC_OFFSET_MASK + 0x4115)
+#define HDMITX_DWC_CSC_COEF_C3_MSB (DWC_OFFSET_MASK + 0x4116)
+#define HDMITX_DWC_CSC_COEF_C3_LSB (DWC_OFFSET_MASK + 0x4117)
+#define HDMITX_DWC_CSC_COEF_C4_MSB (DWC_OFFSET_MASK + 0x4118)
+#define HDMITX_DWC_CSC_COEF_C4_LSB (DWC_OFFSET_MASK + 0x4119)
+#define HDMITX_DWC_CSC_LIMIT_UP_MSB (DWC_OFFSET_MASK + 0x411A)
+#define HDMITX_DWC_CSC_LIMIT_UP_LSB (DWC_OFFSET_MASK + 0x411B)
+#define HDMITX_DWC_CSC_LIMIT_DN_MSB (DWC_OFFSET_MASK + 0x411C)
+#define HDMITX_DWC_CSC_LIMIT_DN_LSB (DWC_OFFSET_MASK + 0x411D)
+
+/* HDCP Encryption Engine Registers */
+#define HDMITX_DWC_A_HDCPCFG0 (DWC_SEC_OFFSET_MASK + 0x5000)
+/* [ 4] hdcp_lock */
+/* [ 3] dissha1check */
+/* [ 2] ph2upshiftenc */
+/* [ 1] encryptiondisable */
+/* [ 0] swresetn. Write 0 to activate, self-clear to 1. */
+#define HDMITX_DWC_A_HDCPCFG1 (DWC_SEC_OFFSET_MASK + 0x5001)
+#define HDMITX_DWC_A_HDCPOBS0 (DWC_OFFSET_MASK + 0x5002)
+#define HDMITX_DWC_A_HDCPOBS1 (DWC_OFFSET_MASK + 0x5003)
+#define HDMITX_DWC_A_HDCPOBS2 (DWC_OFFSET_MASK + 0x5004)
+#define HDMITX_DWC_A_HDCPOBS3 (DWC_OFFSET_MASK + 0x5005)
+#define HDMITX_DWC_A_APIINTCLR (DWC_OFFSET_MASK + 0x5006)
+#define HDMITX_DWC_A_APIINTSTAT (DWC_OFFSET_MASK + 0x5007)
+/* [ 7] hdcp_engaged_int_mask */
+/* [ 6] hdcp_failed_int_mask */
+/* [ 4] i2c_nack_int_mask */
+/* [ 3] lost_arbitration_int_mask */
+/* [ 2] keepout_error_int_mask */
+/* [ 1] ksv_sha1_calc_int_mask */
+/* [ 0] ksv_access_int_mask */
+#define HDMITX_DWC_A_APIINTMSK (DWC_OFFSET_MASK + 0x5008)
+/* [6:5] unencryptconf */
+/* [ 4] dataenpol */
+/* [ 3] vsyncpol */
+/* [ 1] hsyncpol */
+#define HDMITX_DWC_A_VIDPOLCFG (DWC_OFFSET_MASK + 0x5009)
+#define HDMITX_DWC_A_OESSWCFG (DWC_OFFSET_MASK + 0x500A)
+#define HDMITX_DWC_A_COREVERLSB (DWC_OFFSET_MASK + 0x5014)
+#define HDMITX_DWC_A_COREVERMSB (DWC_OFFSET_MASK + 0x5015)
+/* [ 3] sha1_fail */
+/* [ 2] ksv_ctrl_update */
+/* [ 1] Rsvd for read-only ksv_mem_access */
+/* [ 0] ksv_mem_request */
+#define HDMITX_DWC_A_KSVMEMCTRL (DWC_OFFSET_MASK + 0x5016)
+
+#define HDMITX_DWC_HDCP_BSTATUS_0 (DWC_OFFSET_MASK + 0x5020)
+#define HDMITX_DWC_HDCP_BSTATUS_1 (DWC_OFFSET_MASK + 0x5021)
+#define HDMITX_DWC_HDCP_M0_0 (DWC_OFFSET_MASK + 0x5022)
+#define HDMITX_DWC_HDCP_M0_1 (DWC_OFFSET_MASK + 0x5023)
+#define HDMITX_DWC_HDCP_M0_2 (DWC_OFFSET_MASK + 0x5024)
+#define HDMITX_DWC_HDCP_M0_3 (DWC_OFFSET_MASK + 0x5025)
+#define HDMITX_DWC_HDCP_M0_4 (DWC_OFFSET_MASK + 0x5026)
+#define HDMITX_DWC_HDCP_M0_5 (DWC_OFFSET_MASK + 0x5027)
+#define HDMITX_DWC_HDCP_M0_6 (DWC_OFFSET_MASK + 0x5028)
+#define HDMITX_DWC_HDCP_M0_7 (DWC_OFFSET_MASK + 0x5029)
+#define HDMITX_DWC_HDCP_KSV (DWC_OFFSET_MASK + 0x502A)
+#define HDMITX_DWC_HDCP_VH (DWC_OFFSET_MASK + 0x52A5)
+#define HDMITX_DWC_HDCP_REVOC_SIZE_0 (DWC_OFFSET_MASK + 0x52B9)
+#define HDMITX_DWC_HDCP_REVOC_SIZE_1 (DWC_OFFSET_MASK + 0x52BA)
+#define HDMITX_DWC_HDCP_REVOC_LIST (DWC_OFFSET_MASK + 0x52BB)
+
+/* HDCP BKSV Registers */
+#define HDMITX_DWC_HDCPREG_BKSV0 (DWC_OFFSET_MASK + 0x7800)
+#define HDMITX_DWC_HDCPREG_BKSV1 (DWC_OFFSET_MASK + 0x7801)
+#define HDMITX_DWC_HDCPREG_BKSV2 (DWC_OFFSET_MASK + 0x7802)
+#define HDMITX_DWC_HDCPREG_BKSV3 (DWC_OFFSET_MASK + 0x7803)
+#define HDMITX_DWC_HDCPREG_BKSV4 (DWC_OFFSET_MASK + 0x7804)
+
+/* HDCP AN Registers */
+#define HDMITX_DWC_HDCPREG_ANCONF (DWC_OFFSET_MASK + 0x7805)
+#define HDMITX_DWC_HDCPREG_AN0 (DWC_OFFSET_MASK + 0x7806)
+#define HDMITX_DWC_HDCPREG_AN1 (DWC_OFFSET_MASK + 0x7807)
+#define HDMITX_DWC_HDCPREG_AN2 (DWC_OFFSET_MASK + 0x7808)
+#define HDMITX_DWC_HDCPREG_AN3 (DWC_OFFSET_MASK + 0x7809)
+#define HDMITX_DWC_HDCPREG_AN4 (DWC_OFFSET_MASK + 0x780A)
+#define HDMITX_DWC_HDCPREG_AN5 (DWC_OFFSET_MASK + 0x780B)
+#define HDMITX_DWC_HDCPREG_AN6 (DWC_OFFSET_MASK + 0x780C)
+#define HDMITX_DWC_HDCPREG_AN7 (DWC_OFFSET_MASK + 0x780D)
+#define HDMITX_DWC_HDCPREG_RMLCTL (DWC_OFFSET_MASK + 0x780E)
+
+/* Encrypted DPK Embedded Storage Registers */
+#define HDMITX_DWC_HDCPREG_RMLSTS (DWC_OFFSET_MASK + 0x780F)
+#define HDMITX_DWC_HDCPREG_SEED0 (DWC_SEC_OFFSET_MASK + 0x7810)
+#define HDMITX_DWC_HDCPREG_SEED1 (DWC_SEC_OFFSET_MASK + 0x7811)
+#define HDMITX_DWC_HDCPREG_DPK0 (DWC_SEC_OFFSET_MASK + 0x7812)
+#define HDMITX_DWC_HDCPREG_DPK1 (DWC_SEC_OFFSET_MASK + 0x7813)
+#define HDMITX_DWC_HDCPREG_DPK2 (DWC_SEC_OFFSET_MASK + 0x7814)
+#define HDMITX_DWC_HDCPREG_DPK3 (DWC_SEC_OFFSET_MASK + 0x7815)
+#define HDMITX_DWC_HDCPREG_DPK4 (DWC_SEC_OFFSET_MASK + 0x7816)
+#define HDMITX_DWC_HDCPREG_DPK5 (DWC_SEC_OFFSET_MASK + 0x7817)
+#define HDMITX_DWC_HDCPREG_DPK6 (DWC_SEC_OFFSET_MASK + 0x7818)
+
+/* HDCP22 Registers */
+#define HDMITX_DWC_HDCP22REG_ID (DWC_OFFSET_MASK + 0x7900)
+#define HDMITX_DWC_HDCP22REG_CTRL (DWC_SEC_OFFSET_MASK + 0x7904)
+#define HDMITX_DWC_HDCP22REG_CTRL1 (DWC_OFFSET_MASK + 0x7905)
+#define HDMITX_DWC_HDCP22REG_STS (DWC_OFFSET_MASK + 0x7908)
+#define HDMITX_DWC_HDCP22REG_MASK (DWC_OFFSET_MASK + 0x790C)
+#define HDMITX_DWC_HDCP22REG_STAT (DWC_OFFSET_MASK + 0x790D)
+#define HDMITX_DWC_HDCP22REG_MUTE (DWC_OFFSET_MASK + 0x790E)
+
+
+/* ********** CEC related ********** */
+
+/* CEC 2.0 Engine Registers */
+#define HDMITX_DWC_CEC_CTRL (DWC_OFFSET_MASK + 0x7D00)
+#define HDMITX_DWC_CEC_INTR_MASK (DWC_OFFSET_MASK + 0x7D02)
+#define HDMITX_DWC_CEC_LADD_LOW (DWC_OFFSET_MASK + 0x7D05)
+#define HDMITX_DWC_CEC_LADD_HIGH (DWC_OFFSET_MASK + 0x7D06)
+#define HDMITX_DWC_CEC_TX_CNT (DWC_OFFSET_MASK + 0x7D07)
+#define HDMITX_DWC_CEC_RX_CNT (DWC_OFFSET_MASK + 0x7D08)
+#define HDMITX_DWC_CEC_TX_DATA00 (DWC_OFFSET_MASK + 0x7D10)
+#define HDMITX_DWC_CEC_TX_DATA01 (DWC_OFFSET_MASK + 0x7D11)
+#define HDMITX_DWC_CEC_TX_DATA02 (DWC_OFFSET_MASK + 0x7D12)
+#define HDMITX_DWC_CEC_TX_DATA03 (DWC_OFFSET_MASK + 0x7D13)
+#define HDMITX_DWC_CEC_TX_DATA04 (DWC_OFFSET_MASK + 0x7D14)
+#define HDMITX_DWC_CEC_TX_DATA05 (DWC_OFFSET_MASK + 0x7D15)
+#define HDMITX_DWC_CEC_TX_DATA06 (DWC_OFFSET_MASK + 0x7D16)
+#define HDMITX_DWC_CEC_TX_DATA07 (DWC_OFFSET_MASK + 0x7D17)
+#define HDMITX_DWC_CEC_TX_DATA08 (DWC_OFFSET_MASK + 0x7D18)
+#define HDMITX_DWC_CEC_TX_DATA09 (DWC_OFFSET_MASK + 0x7D19)
+#define HDMITX_DWC_CEC_TX_DATA10 (DWC_OFFSET_MASK + 0x7D1A)
+#define HDMITX_DWC_CEC_TX_DATA11 (DWC_OFFSET_MASK + 0x7D1B)
+#define HDMITX_DWC_CEC_TX_DATA12 (DWC_OFFSET_MASK + 0x7D1C)
+#define HDMITX_DWC_CEC_TX_DATA13 (DWC_OFFSET_MASK + 0x7D1D)
+#define HDMITX_DWC_CEC_TX_DATA14 (DWC_OFFSET_MASK + 0x7D1E)
+#define HDMITX_DWC_CEC_TX_DATA15 (DWC_OFFSET_MASK + 0x7D1F)
+#define HDMITX_DWC_CEC_RX_DATA00 (DWC_OFFSET_MASK + 0x7D20)
+#define HDMITX_DWC_CEC_RX_DATA01 (DWC_OFFSET_MASK + 0x7D21)
+#define HDMITX_DWC_CEC_RX_DATA02 (DWC_OFFSET_MASK + 0x7D22)
+#define HDMITX_DWC_CEC_RX_DATA03 (DWC_OFFSET_MASK + 0x7D23)
+#define HDMITX_DWC_CEC_RX_DATA04 (DWC_OFFSET_MASK + 0x7D24)
+#define HDMITX_DWC_CEC_RX_DATA05 (DWC_OFFSET_MASK + 0x7D25)
+#define HDMITX_DWC_CEC_RX_DATA06 (DWC_OFFSET_MASK + 0x7D26)
+#define HDMITX_DWC_CEC_RX_DATA07 (DWC_OFFSET_MASK + 0x7D27)
+#define HDMITX_DWC_CEC_RX_DATA08 (DWC_OFFSET_MASK + 0x7D28)
+#define HDMITX_DWC_CEC_RX_DATA09 (DWC_OFFSET_MASK + 0x7D29)
+#define HDMITX_DWC_CEC_RX_DATA10 (DWC_OFFSET_MASK + 0x7D2A)
+#define HDMITX_DWC_CEC_RX_DATA11 (DWC_OFFSET_MASK + 0x7D2B)
+#define HDMITX_DWC_CEC_RX_DATA12 (DWC_OFFSET_MASK + 0x7D2C)
+#define HDMITX_DWC_CEC_RX_DATA13 (DWC_OFFSET_MASK + 0x7D2D)
+#define HDMITX_DWC_CEC_RX_DATA14 (DWC_OFFSET_MASK + 0x7D2E)
+#define HDMITX_DWC_CEC_RX_DATA15 (DWC_OFFSET_MASK + 0x7D2F)
+#define HDMITX_DWC_CEC_LOCK_BUF (DWC_OFFSET_MASK + 0x7D30)
+#define HDMITX_DWC_CEC_WAKEUPCTRL (DWC_OFFSET_MASK + 0x7D31)
+
+/* I2C Master Registers(E-DDC/SCDC) */
+#define HDMITX_DWC_I2CM_SLAVE (DWC_OFFSET_MASK + 0x7E00)
+#define HDMITX_DWC_I2CM_ADDRESS (DWC_OFFSET_MASK + 0x7E01)
+#define HDMITX_DWC_I2CM_DATAO (DWC_OFFSET_MASK + 0x7E02)
+#define HDMITX_DWC_I2CM_DATAI (DWC_OFFSET_MASK + 0x7E03)
+#define HDMITX_DWC_I2CM_OPERATION (DWC_OFFSET_MASK + 0x7E04)
+/* [ 2] done_mask */
+/* [ 6] read_req_mask */
+#define HDMITX_DWC_I2CM_INT (DWC_OFFSET_MASK + 0x7E05)
+/* [ 6] nack_mask */
+/* [ 2] arbitration_error_mask */
+#define HDMITX_DWC_I2CM_CTLINT (DWC_OFFSET_MASK + 0x7E06)
+/* [ 3] i2c_fast_mode: 0=standard mode; 1=fast mode. */
+#define HDMITX_DWC_I2CM_DIV (DWC_OFFSET_MASK + 0x7E07)
+#define HDMITX_DWC_I2CM_SEGADDR (DWC_OFFSET_MASK + 0x7E08)
+#define HDMITX_DWC_I2CM_SOFTRSTZ (DWC_OFFSET_MASK + 0x7E09)
+#define HDMITX_DWC_I2CM_SEGPTR (DWC_OFFSET_MASK + 0x7E0A)
+/* I2CM_SS_SCL_HCNT = RndUp(min_ss_scl_htime*Freq(sfrclkInMHz)/1000) */
+/* I2CM_SS_SCL_LCNT = RndUp(min_ss_scl_ltime*Freq(sfrclkInMHz)/1000) */
+/* I2CM_FS_SCL_HCNT = RndUp(min_fs_scl_htime*Freq(sfrclkInMHz)/1000) */
+/* I2CM_FS_SCL_LCNT = RndUp(min_fs_scl_ltime*Freq(sfrclkInMHz)/1000) */
+/* Where Freq(sfrclkInMHz)=24; */
+#define HDMITX_DWC_I2CM_SS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x7E0B)
+#define HDMITX_DWC_I2CM_SS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x7E0C)
+#define HDMITX_DWC_I2CM_SS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x7E0D)
+#define HDMITX_DWC_I2CM_SS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x7E0E)
+#define HDMITX_DWC_I2CM_FS_SCL_HCNT_1 (DWC_OFFSET_MASK + 0x7E0F)
+#define HDMITX_DWC_I2CM_FS_SCL_HCNT_0 (DWC_OFFSET_MASK + 0x7E10)
+#define HDMITX_DWC_I2CM_FS_SCL_LCNT_1 (DWC_OFFSET_MASK + 0x7E11)
+#define HDMITX_DWC_I2CM_FS_SCL_LCNT_0 (DWC_OFFSET_MASK + 0x7E12)
+#define HDMITX_DWC_I2CM_SDA_HOLD (DWC_OFFSET_MASK + 0x7E13)
+/* [ 5] updt_rd_vsyncpoll_en */
+/* [ 4] read_request_en */
+/* [ 0] read_update */
+#define HDMITX_DWC_I2CM_SCDC_UPDATE (DWC_OFFSET_MASK + 0x7E14)
+#define HDMITX_DWC_I2CM_READ_BUFF0 (DWC_OFFSET_MASK + 0x7E20)
+#define HDMITX_DWC_I2CM_READ_BUFF1 (DWC_OFFSET_MASK + 0x7E21)
+#define HDMITX_DWC_I2CM_READ_BUFF2 (DWC_OFFSET_MASK + 0x7E22)
+#define HDMITX_DWC_I2CM_READ_BUFF3 (DWC_OFFSET_MASK + 0x7E23)
+#define HDMITX_DWC_I2CM_READ_BUFF4 (DWC_OFFSET_MASK + 0x7E24)
+#define HDMITX_DWC_I2CM_READ_BUFF5 (DWC_OFFSET_MASK + 0x7E25)
+#define HDMITX_DWC_I2CM_READ_BUFF6 (DWC_OFFSET_MASK + 0x7E26)
+#define HDMITX_DWC_I2CM_READ_BUFF7 (DWC_OFFSET_MASK + 0x7E27)
+#define HDMITX_DWC_I2CM_SCDC_UPDATE0 (DWC_OFFSET_MASK + 0x7E30)
+#define HDMITX_DWC_I2CM_SCDC_UPDATE1 (DWC_OFFSET_MASK + 0x7E31)
+
+#endif /* __HDMI_TX_REG_H_ */
diff --git a/include/amlogic/media/vout/hdmitx/mach_reg.h b/include/amlogic/media/vout/hdmitx/mach_reg.h
new file mode 100644
index 0000000..be5419a
--- /dev/null
+++ b/include/amlogic/media/vout/hdmitx/mach_reg.h
@@ -0,0 +1,630 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __MACH_REG_H__
+#define __MACH_REG_H__
+
+/*
+ * RePacket HDMI related registers rd/wr
+ */
+struct reg_map {
+ uint32_t base_addr;
+};
+
+#define CBUS_REG_IDX 0
+#define PERIPHS_REG_IDX 1
+#define VCBUS_REG_IDX 2
+#define AOBUS_REG_IDX 3
+#define HHI_REG_IDX 4
+#define RESET_CBUS_REG_IDX 5
+#define HDMITX_REG_IDX 6
+#define HDMITX_SEC_REG_IDX 7
+#define ELP_ESM_REG_IDX 8
+/* new added in SC2 */
+#define ANACTRL_REG_IDX 9
+#define PWRCTRL_REG_IDX 10
+#define RESETCTRL_REG_IDX 11
+#define SYSCTRL_REG_IDX 12
+#define REG_IDX_END 13
+
+#define BASE_REG_OFFSET 24
+
+#define PERIPHS_REG_ADDR(reg) \
+ ((PERIPHS_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2))
+#define VCBUS_REG_ADDR(reg) \
+ ((VCBUS_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2))
+#define AOBUS_REG_ADDR(reg) \
+ ((AOBUS_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2))
+#define HHI_REG_ADDR(reg) \
+ ((HHI_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2))
+#define RESET_CBUS_REG_ADDR(reg) \
+ ((RESET_CBUS_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2))
+#define HDMITX_SEC_REG_ADDR(reg) \
+ ((HDMITX_SEC_REG_IDX << BASE_REG_OFFSET) + (reg))/*DWC*/
+#define HDMITX_REG_ADDR(reg) \
+ ((HDMITX_REG_IDX << BASE_REG_OFFSET) + (reg))/*TOP*/
+#define ELP_ESM_REG_ADDR(reg) \
+ ((ELP_ESM_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2))
+#define ANACTRL_REG_ADDR(reg) \
+ ((ANACTRL_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2))
+#define PWRCTRL_REG_ADDR(reg) \
+ ((PWRCTRL_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2))
+#define RESETCTRL_REG_ADDR(reg) \
+ ((RESETCTRL_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2))
+#define SYSCTRL_REG_ADDR(reg) \
+ ((SYSCTRL_REG_IDX << BASE_REG_OFFSET) + ((reg) << 2))
+
+struct reg_s {
+ unsigned int reg;
+ unsigned int val;
+};
+
+unsigned int hd_read_reg(unsigned int addr);
+void hd_write_reg(unsigned int addr, unsigned int val);
+void hd_set_reg_bits(unsigned int addr, unsigned int value, unsigned int offset,
+ unsigned int len);
+uint32_t hd_get_paddr(uint32_t addr);
+unsigned int hdmitx_rd_reg(unsigned int addr);
+void hdmitx_wr_reg(unsigned int addr, unsigned int data);
+void hdmitx_set_reg_bits(unsigned int addr, unsigned int value,
+ unsigned int offset, unsigned int len);
+void hdmitx_poll_reg(unsigned int addr, unsigned int val, unsigned long timeout);
+
+/* REG_BASE: REGISTER_BASE_ADDR = 0xfe000000 */
+#define CLKCTRL_SYS_CLK_EN0_REG2 0x0013
+#define P_CLKCTRL_SYS_CLK_EN0_REG2 HHI_REG_ADDR(CLKCTRL_SYS_CLK_EN0_REG2)
+#define CLKCTRL_VID_CLK_CTRL 0x0030
+#define P_CLKCTRL_VID_CLK_CTRL HHI_REG_ADDR(CLKCTRL_VID_CLK_CTRL)
+#define CLKCTRL_VID_CLK_CTRL2 0x0031
+#define P_CLKCTRL_VID_CLK_CTRL2 HHI_REG_ADDR(CLKCTRL_VID_CLK_CTRL2)
+#define CLKCTRL_VID_CLK_DIV 0x0032
+#define P_CLKCTRL_VID_CLK_DIV HHI_REG_ADDR(CLKCTRL_VID_CLK_DIV)
+#define CLKCTRL_HDMI_CLK_CTRL 0x0038
+#define P_CLKCTRL_HDMI_CLK_CTRL HHI_REG_ADDR(CLKCTRL_HDMI_CLK_CTRL)
+#define CLKCTRL_VID_PLL_CLK_DIV 0x0039
+#define P_CLKCTRL_VID_PLL_CLK_DIV HHI_REG_ADDR(CLKCTRL_VID_PLL_CLK_DIV)
+#define CLKCTRL_HDCP22_CLK_CTRL 0x0040
+#define P_CLKCTRL_HDCP22_CLK_CTRL HHI_REG_ADDR(CLKCTRL_HDCP22_CLK_CTRL)
+
+/* REG_BASE: REGISTER_BASE_ADDR = 0xfe002000 */
+#define RESETCTRL_RESET0 0x0000
+#define P_RESETCTRL_RESET0 RESETCTRL_REG_ADDR(RESETCTRL_RESET0)
+#define RESETCTRL_RESET2 0x0002
+#define P_RESETCTRL_RESET2 RESETCTRL_REG_ADDR(RESETCTRL_RESET2)
+
+/* REG_BASE: REGISTER_BASE_ADDR = 0xfe004000 */
+#define PADCTRL_PIN_MUX_REGB 0x0b
+#define P_PADCTRL_PIN_MUX_REGB PERIPHS_REG_ADDR(PADCTRL_PIN_MUX_REGB)
+#define PADCTRL_GPIOH_I 0x50
+#define P_PADCTRL_GPIOH_I PERIPHS_REG_ADDR(PADCTRL_GPIOH_I)
+
+/* REG_BASE: REGISTER_BASE_ADDR = 0xfe008000 */
+#define ANACTRL_HDMIPLL_CTRL0 0x0070
+#define P_ANACTRL_HDMIPLL_CTRL0 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL0)
+#define ANACTRL_HDMIPLL_CTRL1 0x0071
+#define P_ANACTRL_HDMIPLL_CTRL1 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL1)
+#define ANACTRL_HDMIPLL_CTRL2 0x0072
+#define P_ANACTRL_HDMIPLL_CTRL2 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL2)
+#define ANACTRL_HDMIPLL_CTRL3 0x0073
+#define P_ANACTRL_HDMIPLL_CTRL3 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL3)
+#define ANACTRL_HDMIPLL_CTRL4 0x0074
+#define P_ANACTRL_HDMIPLL_CTRL4 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL4)
+#define ANACTRL_HDMIPLL_CTRL5 0x0075
+#define P_ANACTRL_HDMIPLL_CTRL5 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL5)
+#define ANACTRL_HDMIPLL_CTRL6 0x0076
+#define P_ANACTRL_HDMIPLL_CTRL6 ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_CTRL6)
+#define ANACTRL_HDMIPLL_STS 0x0077
+#define P_ANACTRL_HDMIPLL_STS ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_STS)
+#define ANACTRL_HDMIPLL_VLOCK 0x0079
+#define P_ANACTRL_HDMIPLL_VLOCK ANACTRL_REG_ADDR(ANACTRL_HDMIPLL_VLOCK)
+#define ANACTRL_HDMIPHY_CTRL0 0x0080
+#define P_ANACTRL_HDMIPHY_CTRL0 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL0)
+#define ANACTRL_HDMIPHY_CTRL1 0x0081
+#define P_ANACTRL_HDMIPHY_CTRL1 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL1)
+#define ANACTRL_HDMIPHY_CTRL2 0x0082
+#define P_ANACTRL_HDMIPHY_CTRL2 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL2)
+#define ANACTRL_HDMIPHY_CTRL3 0x0083
+#define P_ANACTRL_HDMIPHY_CTRL3 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL3)
+#define ANACTRL_HDMIPHY_CTRL4 0x0084
+#define P_ANACTRL_HDMIPHY_CTRL4 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL4)
+#define ANACTRL_HDMIPHY_CTRL5 0x0085
+#define P_ANACTRL_HDMIPHY_CTRL5 ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_CTRL5)
+#define ANACTRL_HDMIPHY_STS 0x0086
+#define P_ANACTRL_HDMIPHY_STS ANACTRL_REG_ADDR(ANACTRL_HDMIPHY_STS)
+
+/* REG_BASE: REGISTER_BASE_ADDR = 0xfe00c000 */
+#define PWRCTRL_MEM_PD11 0x001b
+#define P_PWRCTRL_MEM_PD11 PWRCTRL_REG_ADDR(PWRCTRL_MEM_PD11)
+
+/* REG_BASE: REGISTER_BASE_ADDR = 0xfe010000 */
+#define SYSCTRL_DEBUG_REG0 0x90
+#define P_SYSCTRL_DEBUG_REG0 SYSCTRL_REG_ADDR(SYSCTRL_DEBUG_REG0)
+
+/* REG_BASE: REGISTER_BASE_ADDR = 0xff000000 */
+#define VENC_DVI_SETTING 0x1b62 /* register.h:8014 */
+#define P_VENC_DVI_SETTING VCBUS_REG_ADDR(VENC_DVI_SETTING)
+
+#define VENC_VIDEO_TST_EN 0x1b70
+#define P_VENC_VIDEO_TST_EN VCBUS_REG_ADDR(VENC_VIDEO_TST_EN)
+#define VENC_VIDEO_TST_MDSEL 0x1b71
+#define P_VENC_VIDEO_TST_MDSEL VCBUS_REG_ADDR(VENC_VIDEO_TST_MDSEL)
+#define VENC_VIDEO_TST_Y 0x1b72
+#define P_VENC_VIDEO_TST_Y VCBUS_REG_ADDR(VENC_VIDEO_TST_Y)
+#define VENC_VIDEO_TST_CB 0x1b73
+#define P_VENC_VIDEO_TST_CB VCBUS_REG_ADDR(VENC_VIDEO_TST_CB)
+#define VENC_VIDEO_TST_CR 0x1b74
+#define P_VENC_VIDEO_TST_CR VCBUS_REG_ADDR(VENC_VIDEO_TST_CR)
+#define VENC_VIDEO_TST_CLRBAR_STRT 0x1b75
+#define P_VENC_VIDEO_TST_CLRBAR_STRT VCBUS_REG_ADDR(VENC_VIDEO_TST_CLRBAR_STRT)
+#define VENC_VIDEO_TST_CLRBAR_WIDTH 0x1b76
+#define P_VENC_VIDEO_TST_CLRBAR_WIDTH \
+ VCBUS_REG_ADDR(VENC_VIDEO_TST_CLRBAR_WIDTH)
+#define VENC_VIDEO_TST_VDCNT_STSET 0x1b77
+#define P_VENC_VIDEO_TST_VDCNT_STSET VCBUS_REG_ADDR(VENC_VIDEO_TST_VDCNT_STSET)
+#define VENC_VDAC_SETTING 0x1b7e
+#define P_VENC_VDAC_SETTING VCBUS_REG_ADDR(VENC_VDAC_SETTING)
+#define ENCP_VIDEO_EN 0x1b80 /* register.h:8078 */
+#define P_ENCP_VIDEO_EN VCBUS_REG_ADDR(ENCP_VIDEO_EN)
+#define ENCP_VIDEO_SYNC_MODE 0x1b81 /* register.h:8079 */
+#define P_ENCP_VIDEO_SYNC_MODE VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_MODE)
+#define ENCP_MACV_EN 0x1b82 /* register.h:8080 */
+#define P_ENCP_MACV_EN VCBUS_REG_ADDR(ENCP_MACV_EN)
+#define ENCP_VIDEO_Y_SCL 0x1b83 /* register.h:8081 */
+#define P_ENCP_VIDEO_Y_SCL VCBUS_REG_ADDR(ENCP_VIDEO_Y_SCL)
+#define ENCP_VIDEO_PB_SCL 0x1b84 /* register.h:8082 */
+#define P_ENCP_VIDEO_PB_SCL VCBUS_REG_ADDR(ENCP_VIDEO_PB_SCL)
+#define ENCP_VIDEO_PR_SCL 0x1b85 /* register.h:8083 */
+#define P_ENCP_VIDEO_PR_SCL VCBUS_REG_ADDR(ENCP_VIDEO_PR_SCL)
+#define ENCP_VIDEO_SYNC_SCL 0x1b86 /* register.h:8084 */
+#define P_ENCP_VIDEO_SYNC_SCL VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_SCL)
+#define ENCP_VIDEO_MACV_SCL 0x1b87 /* register.h:8085 */
+#define P_ENCP_VIDEO_MACV_SCL VCBUS_REG_ADDR(ENCP_VIDEO_MACV_SCL)
+#define ENCP_VIDEO_Y_OFFST 0x1b88 /* register.h:8086 */
+#define P_ENCP_VIDEO_Y_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_Y_OFFST)
+#define ENCP_VIDEO_PB_OFFST 0x1b89 /* register.h:8087 */
+#define P_ENCP_VIDEO_PB_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_PB_OFFST)
+#define ENCP_VIDEO_PR_OFFST 0x1b8a /* register.h:8088 */
+#define P_ENCP_VIDEO_PR_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_PR_OFFST)
+#define ENCP_VIDEO_SYNC_OFFST 0x1b8b /* register.h:8089 */
+#define P_ENCP_VIDEO_SYNC_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_OFFST)
+#define ENCP_VIDEO_MACV_OFFST 0x1b8c /* register.h:8090 */
+#define P_ENCP_VIDEO_MACV_OFFST VCBUS_REG_ADDR(ENCP_VIDEO_MACV_OFFST)
+#define ENCP_VIDEO_MODE 0x1b8d /* register.h:8092 */
+#define P_ENCP_VIDEO_MODE VCBUS_REG_ADDR(ENCP_VIDEO_MODE)
+#define ENCP_VIDEO_MODE_ADV 0x1b8e /* register.h:8093 */
+#define P_ENCP_VIDEO_MODE_ADV VCBUS_REG_ADDR(ENCP_VIDEO_MODE_ADV)
+#define ENCP_DBG_PX_RST 0x1b90 /* register.h:8095 */
+#define P_ENCP_DBG_PX_RST VCBUS_REG_ADDR(ENCP_DBG_PX_RST)
+#define ENCP_DBG_LN_RST 0x1b91 /* register.h:8096 */
+#define P_ENCP_DBG_LN_RST VCBUS_REG_ADDR(ENCP_DBG_LN_RST)
+#define ENCP_DBG_PX_INT 0x1b92 /* register.h:8097 */
+#define P_ENCP_DBG_PX_INT VCBUS_REG_ADDR(ENCP_DBG_PX_INT)
+#define ENCP_DBG_LN_INT 0x1b93 /* register.h:8098 */
+#define P_ENCP_DBG_LN_INT VCBUS_REG_ADDR(ENCP_DBG_LN_INT)
+#define ENCP_VIDEO_YFP1_HTIME 0x1b94 /* register.h:8100 */
+#define P_ENCP_VIDEO_YFP1_HTIME VCBUS_REG_ADDR(ENCP_VIDEO_YFP1_HTIME)
+#define ENCP_VIDEO_YFP2_HTIME 0x1b95 /* register.h:8101 */
+#define P_ENCP_VIDEO_YFP2_HTIME VCBUS_REG_ADDR(ENCP_VIDEO_YFP2_HTIME)
+#define ENCP_VIDEO_YC_DLY 0x1b96 /* register.h:8102 */
+#define P_ENCP_VIDEO_YC_DLY VCBUS_REG_ADDR(ENCP_VIDEO_YC_DLY)
+#define ENCP_VIDEO_MAX_PXCNT 0x1b97 /* register.h:8103 */
+#define P_ENCP_VIDEO_MAX_PXCNT VCBUS_REG_ADDR(ENCP_VIDEO_MAX_PXCNT)
+#define ENCP_VIDEO_HSPULS_BEGIN 0x1b98 /* register.h:8104 */
+#define P_ENCP_VIDEO_HSPULS_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_HSPULS_BEGIN)
+#define ENCP_VIDEO_HSPULS_END 0x1b99 /* register.h:8105 */
+#define P_ENCP_VIDEO_HSPULS_END VCBUS_REG_ADDR(ENCP_VIDEO_HSPULS_END)
+#define ENCP_VIDEO_HSPULS_SWITCH 0x1b9a /* register.h:8106 */
+#define P_ENCP_VIDEO_HSPULS_SWITCH VCBUS_REG_ADDR(ENCP_VIDEO_HSPULS_SWITCH)
+#define ENCP_VIDEO_VSPULS_BEGIN 0x1b9b /* register.h:8107 */
+#define P_ENCP_VIDEO_VSPULS_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_BEGIN)
+#define ENCP_VIDEO_VSPULS_END 0x1b9c /* register.h:8108 */
+#define P_ENCP_VIDEO_VSPULS_END VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_END)
+#define ENCP_VIDEO_VSPULS_BLINE 0x1b9d /* register.h:8109 */
+#define P_ENCP_VIDEO_VSPULS_BLINE VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_BLINE)
+#define ENCP_VIDEO_VSPULS_ELINE 0x1b9e /* register.h:8110 */
+#define P_ENCP_VIDEO_VSPULS_ELINE VCBUS_REG_ADDR(ENCP_VIDEO_VSPULS_ELINE)
+#define ENCP_VIDEO_EQPULS_BEGIN 0x1b9f /* register.h:8111 */
+#define P_ENCP_VIDEO_EQPULS_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_BEGIN)
+#define ENCP_VIDEO_EQPULS_END 0x1ba0 /* register.h:8112 */
+#define P_ENCP_VIDEO_EQPULS_END VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_END)
+#define ENCP_VIDEO_EQPULS_BLINE 0x1ba1 /* register.h:8113 */
+#define P_ENCP_VIDEO_EQPULS_BLINE VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_BLINE)
+#define ENCP_VIDEO_EQPULS_ELINE 0x1ba2 /* register.h:8114 */
+#define P_ENCP_VIDEO_EQPULS_ELINE VCBUS_REG_ADDR(ENCP_VIDEO_EQPULS_ELINE)
+#define ENCP_VIDEO_HAVON_END 0x1ba3 /* register.h:8115 */
+#define P_ENCP_VIDEO_HAVON_END VCBUS_REG_ADDR(ENCP_VIDEO_HAVON_END)
+#define ENCP_VIDEO_HAVON_BEGIN 0x1ba4 /* register.h:8116 */
+#define P_ENCP_VIDEO_HAVON_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_HAVON_BEGIN)
+#define ENCP_VIDEO_VAVON_ELINE 0x1baf /* register.h:8117 */
+#define P_ENCP_VIDEO_VAVON_ELINE VCBUS_REG_ADDR(ENCP_VIDEO_VAVON_ELINE)
+#define ENCP_VIDEO_VAVON_BLINE 0x1ba6 /* register.h:8118 */
+#define P_ENCP_VIDEO_VAVON_BLINE VCBUS_REG_ADDR(ENCP_VIDEO_VAVON_BLINE)
+#define ENCP_VIDEO_HSO_BEGIN 0x1ba7 /* register.h:8119 */
+#define P_ENCP_VIDEO_HSO_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_HSO_BEGIN)
+#define ENCP_VIDEO_HSO_END 0x1ba8 /* register.h:8120 */
+#define P_ENCP_VIDEO_HSO_END VCBUS_REG_ADDR(ENCP_VIDEO_HSO_END)
+#define ENCP_VIDEO_VSO_BEGIN 0x1ba9 /* register.h:8121 */
+#define P_ENCP_VIDEO_VSO_BEGIN VCBUS_REG_ADDR(ENCP_VIDEO_VSO_BEGIN)
+#define ENCP_VIDEO_VSO_END 0x1baa /* register.h:8122 */
+#define P_ENCP_VIDEO_VSO_END VCBUS_REG_ADDR(ENCP_VIDEO_VSO_END)
+#define ENCP_VIDEO_VSO_BLINE 0x1bab /* register.h:8123 */
+#define P_ENCP_VIDEO_VSO_BLINE VCBUS_REG_ADDR(ENCP_VIDEO_VSO_BLINE)
+#define ENCP_VIDEO_VSO_ELINE 0x1bac /* register.h:8124 */
+#define P_ENCP_VIDEO_VSO_ELINE VCBUS_REG_ADDR(ENCP_VIDEO_VSO_ELINE)
+#define ENCP_VIDEO_SYNC_WAVE_CURVE 0x1bad /* register.h:8125 */
+#define P_ENCP_VIDEO_SYNC_WAVE_CURVE VCBUS_REG_ADDR(ENCP_VIDEO_SYNC_WAVE_CURVE)
+#define ENCP_VIDEO_MAX_LNCNT 0x1bae /* register.h:8126 */
+#define P_ENCP_VIDEO_MAX_LNCNT VCBUS_REG_ADDR(ENCP_VIDEO_MAX_LNCNT)
+#define ENCP_VIDEO_SY_VAL 0x1bb0 /* register.h:8127 */
+#define P_ENCP_VIDEO_SY_VAL VCBUS_REG_ADDR(ENCP_VIDEO_SY_VAL)
+#define ENCP_VIDEO_SY2_VAL 0x1bb1 /* register.h:8128 */
+#define P_ENCP_VIDEO_SY2_VAL VCBUS_REG_ADDR(ENCP_VIDEO_SY2_VAL)
+#define ENCP_VIDEO_BLANKY_VAL 0x1bb2 /* register.h:8129 */
+#define P_ENCP_VIDEO_BLANKY_VAL VCBUS_REG_ADDR(ENCP_VIDEO_BLANKY_VAL)
+#define ENCP_VIDEO_BLANKPB_VAL 0x1bb3 /* register.h:8130 */
+#define P_ENCP_VIDEO_BLANKPB_VAL VCBUS_REG_ADDR(ENCP_VIDEO_BLANKPB_VAL)
+#define ENCP_VIDEO_BLANKPR_VAL 0x1bb4 /* register.h:8131 */
+#define P_ENCP_VIDEO_BLANKPR_VAL VCBUS_REG_ADDR(ENCP_VIDEO_BLANKPR_VAL)
+#define ENCP_VIDEO_HOFFST 0x1bb5 /* register.h:8132 */
+#define P_ENCP_VIDEO_HOFFST VCBUS_REG_ADDR(ENCP_VIDEO_HOFFST)
+#define ENCP_VIDEO_VOFFST 0x1bb6 /* register.h:8133 */
+#define P_ENCP_VIDEO_VOFFST VCBUS_REG_ADDR(ENCP_VIDEO_VOFFST)
+#define ENCP_VIDEO_RGB_CTRL 0x1bb7 /* register.h:8134 */
+#define P_ENCP_VIDEO_RGB_CTRL VCBUS_REG_ADDR(ENCP_VIDEO_RGB_CTRL)
+#define ENCP_VIDEO_FILT_CTRL 0x1bb8 /* register.h:8135 */
+#define P_ENCP_VIDEO_FILT_CTRL VCBUS_REG_ADDR(ENCP_VIDEO_FILT_CTRL)
+#define ENCP_VIDEO_OFLD_VPEQ_OFST 0x1bb9 /* register.h:8136 */
+#define P_ENCP_VIDEO_OFLD_VPEQ_OFST VCBUS_REG_ADDR(ENCP_VIDEO_OFLD_VPEQ_OFST)
+#define ENCP_VIDEO_OFLD_VOAV_OFST 0x1bba /* register.h:8137 */
+#define P_ENCP_VIDEO_OFLD_VOAV_OFST VCBUS_REG_ADDR(ENCP_VIDEO_OFLD_VOAV_OFST)
+#define ENCP_VIDEO_MATRIX_CB 0x1bbb /* register.h:8138 */
+#define P_ENCP_VIDEO_MATRIX_CB VCBUS_REG_ADDR(ENCP_VIDEO_MATRIX_CB)
+#define ENCP_VIDEO_MATRIX_CR 0x1bbc /* register.h:8139 */
+#define P_ENCP_VIDEO_MATRIX_CR VCBUS_REG_ADDR(ENCP_VIDEO_MATRIX_CR)
+#define ENCP_VIDEO_RGBIN_CTRL 0x1bbd /* register.h:8140 */
+#define P_ENCP_VIDEO_RGBIN_CTRL VCBUS_REG_ADDR(ENCP_VIDEO_RGBIN_CTRL)
+#define ENCP_MACV_BLANKY_VAL 0x1bc0 /* register.h:8142 */
+#define P_ENCP_MACV_BLANKY_VAL VCBUS_REG_ADDR(ENCP_MACV_BLANKY_VAL)
+#define ENCP_MACV_MAXY_VAL 0x1bc1 /* register.h:8143 */
+#define P_ENCP_MACV_MAXY_VAL VCBUS_REG_ADDR(ENCP_MACV_MAXY_VAL)
+#define ENCP_MACV_1ST_PSSYNC_STRT 0x1bc2 /* register.h:8144 */
+#define P_ENCP_MACV_1ST_PSSYNC_STRT VCBUS_REG_ADDR(ENCP_MACV_1ST_PSSYNC_STRT)
+#define ENCP_MACV_PSSYNC_STRT 0x1bc3 /* register.h:8145 */
+#define P_ENCP_MACV_PSSYNC_STRT VCBUS_REG_ADDR(ENCP_MACV_PSSYNC_STRT)
+#define ENCP_MACV_AGC_STRT 0x1bc4 /* register.h:8146 */
+#define P_ENCP_MACV_AGC_STRT VCBUS_REG_ADDR(ENCP_MACV_AGC_STRT)
+#define ENCP_MACV_AGC_END 0x1bc5 /* register.h:8147 */
+#define P_ENCP_MACV_AGC_END VCBUS_REG_ADDR(ENCP_MACV_AGC_END)
+#define ENCP_MACV_WAVE_END 0x1bc6 /* register.h:8148 */
+#define P_ENCP_MACV_WAVE_END VCBUS_REG_ADDR(ENCP_MACV_WAVE_END)
+#define ENCP_MACV_STRTLINE 0x1bc7 /* register.h:8149 */
+#define P_ENCP_MACV_STRTLINE VCBUS_REG_ADDR(ENCP_MACV_STRTLINE)
+#define ENCP_MACV_ENDLINE 0x1bc8 /* register.h:8150 */
+#define P_ENCP_MACV_ENDLINE VCBUS_REG_ADDR(ENCP_MACV_ENDLINE)
+#define ENCP_MACV_TS_CNT_MAX_L 0x1bc9 /* register.h:8151 */
+#define P_ENCP_MACV_TS_CNT_MAX_L VCBUS_REG_ADDR(ENCP_MACV_TS_CNT_MAX_L)
+#define ENCP_MACV_TS_CNT_MAX_H 0x1bca /* register.h:8152 */
+#define P_ENCP_MACV_TS_CNT_MAX_H VCBUS_REG_ADDR(ENCP_MACV_TS_CNT_MAX_H)
+#define ENCP_MACV_TIME_DOWN 0x1bcb /* register.h:8153 */
+#define P_ENCP_MACV_TIME_DOWN VCBUS_REG_ADDR(ENCP_MACV_TIME_DOWN)
+#define ENCP_MACV_TIME_LO 0x1bcc /* register.h:8154 */
+#define P_ENCP_MACV_TIME_LO VCBUS_REG_ADDR(ENCP_MACV_TIME_LO)
+#define ENCP_MACV_TIME_UP 0x1bcd /* register.h:8155 */
+#define P_ENCP_MACV_TIME_UP VCBUS_REG_ADDR(ENCP_MACV_TIME_UP)
+#define ENCP_MACV_TIME_RST 0x1bce /* register.h:8156 */
+#define P_ENCP_MACV_TIME_RST VCBUS_REG_ADDR(ENCP_MACV_TIME_RST)
+#define ENCP_VBI_CTRL 0x1bd0 /* register.h:8158 */
+#define P_ENCP_VBI_CTRL VCBUS_REG_ADDR(ENCP_VBI_CTRL)
+#define ENCP_VBI_SETTING 0x1bd1 /* register.h:8159 */
+#define P_ENCP_VBI_SETTING VCBUS_REG_ADDR(ENCP_VBI_SETTING)
+#define ENCP_VBI_BEGIN 0x1bd2 /* register.h:8160 */
+#define P_ENCP_VBI_BEGIN VCBUS_REG_ADDR(ENCP_VBI_BEGIN)
+#define ENCP_VBI_WIDTH 0x1bd3 /* register.h:8161 */
+#define P_ENCP_VBI_WIDTH VCBUS_REG_ADDR(ENCP_VBI_WIDTH)
+#define ENCP_VBI_HVAL 0x1bd4 /* register.h:8162 */
+#define P_ENCP_VBI_HVAL VCBUS_REG_ADDR(ENCP_VBI_HVAL)
+#define ENCP_VBI_DATA0 0x1bd5 /* register.h:8163 */
+#define P_ENCP_VBI_DATA0 VCBUS_REG_ADDR(ENCP_VBI_DATA0)
+#define ENCP_VBI_DATA1 0x1bd6 /* register.h:8164 */
+#define P_ENCP_VBI_DATA1 VCBUS_REG_ADDR(ENCP_VBI_DATA1)
+
+#define ENCI_VIDEO_MODE 0x1b00 /* register.h:8185 */
+#define P_ENCI_VIDEO_MODE VCBUS_REG_ADDR(ENCI_VIDEO_MODE)
+#define ENCI_VIDEO_MODE_ADV 0x1b01 /* register.h:8186 */
+#define P_ENCI_VIDEO_MODE_ADV VCBUS_REG_ADDR(ENCI_VIDEO_MODE_ADV)
+#define ENCI_VIDEO_FSC_ADJ 0x1b02 /* register.h:8187 */
+#define P_ENCI_VIDEO_FSC_ADJ VCBUS_REG_ADDR(ENCI_VIDEO_FSC_ADJ)
+#define ENCI_VIDEO_BRIGHT 0x1b03 /* register.h:8188 */
+#define P_ENCI_VIDEO_BRIGHT VCBUS_REG_ADDR(ENCI_VIDEO_BRIGHT)
+#define ENCI_VIDEO_CONT 0x1b04 /* register.h:8189 */
+#define P_ENCI_VIDEO_CONT VCBUS_REG_ADDR(ENCI_VIDEO_CONT)
+#define ENCI_VIDEO_SAT 0x1b05 /* register.h:8190 */
+#define P_ENCI_VIDEO_SAT VCBUS_REG_ADDR(ENCI_VIDEO_SAT)
+#define ENCI_VIDEO_HUE 0x1b06 /* register.h:8191 */
+#define P_ENCI_VIDEO_HUE VCBUS_REG_ADDR(ENCI_VIDEO_HUE)
+#define ENCI_VIDEO_SCH 0x1b07 /* register.h:8192 */
+#define P_ENCI_VIDEO_SCH VCBUS_REG_ADDR(ENCI_VIDEO_SCH)
+#define ENCI_SYNC_MODE 0x1b08 /* register.h:8193 */
+#define P_ENCI_SYNC_MODE VCBUS_REG_ADDR(ENCI_SYNC_MODE)
+#define ENCI_SYNC_CTRL 0x1b09 /* register.h:8194 */
+#define P_ENCI_SYNC_CTRL VCBUS_REG_ADDR(ENCI_SYNC_CTRL)
+#define ENCI_SYNC_HSO_BEGIN 0x1b0a /* register.h:8195 */
+#define P_ENCI_SYNC_HSO_BEGIN VCBUS_REG_ADDR(ENCI_SYNC_HSO_BEGIN)
+#define ENCI_SYNC_HSO_END 0x1b0b /* register.h:8196 */
+#define P_ENCI_SYNC_HSO_END VCBUS_REG_ADDR(ENCI_SYNC_HSO_END)
+#define ENCI_SYNC_VSO_EVN 0x1b0c /* register.h:8197 */
+#define P_ENCI_SYNC_VSO_EVN VCBUS_REG_ADDR(ENCI_SYNC_VSO_EVN)
+#define ENCI_SYNC_VSO_ODD 0x1b0d /* register.h:8198 */
+#define P_ENCI_SYNC_VSO_ODD VCBUS_REG_ADDR(ENCI_SYNC_VSO_ODD)
+#define ENCI_SYNC_VSO_EVNLN 0x1b0e /* register.h:8199 */
+#define P_ENCI_SYNC_VSO_EVNLN VCBUS_REG_ADDR(ENCI_SYNC_VSO_EVNLN)
+#define ENCI_SYNC_VSO_ODDLN 0x1b0f /* register.h:8200 */
+#define P_ENCI_SYNC_VSO_ODDLN VCBUS_REG_ADDR(ENCI_SYNC_VSO_ODDLN)
+#define ENCI_SYNC_HOFFST 0x1b10 /* register.h:8201 */
+#define P_ENCI_SYNC_HOFFST VCBUS_REG_ADDR(ENCI_SYNC_HOFFST)
+#define ENCI_SYNC_VOFFST 0x1b11 /* register.h:8202 */
+#define P_ENCI_SYNC_VOFFST VCBUS_REG_ADDR(ENCI_SYNC_VOFFST)
+#define ENCI_SYNC_ADJ 0x1b12 /* register.h:8203 */
+#define P_ENCI_SYNC_ADJ VCBUS_REG_ADDR(ENCI_SYNC_ADJ)
+#define ENCI_RGB_SETTING 0x1b13 /* register.h:8204 */
+#define P_ENCI_RGB_SETTING VCBUS_REG_ADDR(ENCI_RGB_SETTING)
+#define ENCI_DE_H_BEGIN 0x1b16 /* register.h:8207 */
+#define P_ENCI_DE_H_BEGIN VCBUS_REG_ADDR(ENCI_DE_H_BEGIN)
+#define ENCI_DE_H_END 0x1b17 /* register.h:8208 */
+#define P_ENCI_DE_H_END VCBUS_REG_ADDR(ENCI_DE_H_END)
+#define ENCI_DE_V_BEGIN_EVEN 0x1b18 /* register.h:8209 */
+#define P_ENCI_DE_V_BEGIN_EVEN VCBUS_REG_ADDR(ENCI_DE_V_BEGIN_EVEN)
+#define ENCI_DE_V_END_EVEN 0x1b19 /* register.h:8210 */
+#define P_ENCI_DE_V_END_EVEN VCBUS_REG_ADDR(ENCI_DE_V_END_EVEN)
+#define ENCI_DE_V_BEGIN_ODD 0x1b1a /* register.h:8211 */
+#define P_ENCI_DE_V_BEGIN_ODD VCBUS_REG_ADDR(ENCI_DE_V_BEGIN_ODD)
+#define ENCI_DE_V_END_ODD 0x1b1b /* register.h:8212 */
+#define P_ENCI_DE_V_END_ODD VCBUS_REG_ADDR(ENCI_DE_V_END_ODD)
+#define ENCI_VBI_SETTING 0x1b20 /* register.h:8213 */
+#define P_ENCI_VBI_SETTING VCBUS_REG_ADDR(ENCI_VBI_SETTING)
+#define ENCI_VBI_CCDT_EVN 0x1b21 /* register.h:8214 */
+#define P_ENCI_VBI_CCDT_EVN VCBUS_REG_ADDR(ENCI_VBI_CCDT_EVN)
+#define ENCI_VBI_CCDT_ODD 0x1b22 /* register.h:8215 */
+#define P_ENCI_VBI_CCDT_ODD VCBUS_REG_ADDR(ENCI_VBI_CCDT_ODD)
+#define ENCI_VBI_CC525_LN 0x1b23 /* register.h:8216 */
+#define P_ENCI_VBI_CC525_LN VCBUS_REG_ADDR(ENCI_VBI_CC525_LN)
+#define ENCI_VBI_CC625_LN 0x1b24 /* register.h:8217 */
+#define P_ENCI_VBI_CC625_LN VCBUS_REG_ADDR(ENCI_VBI_CC625_LN)
+#define ENCI_VBI_WSSDT 0x1b25 /* register.h:8218 */
+#define P_ENCI_VBI_WSSDT VCBUS_REG_ADDR(ENCI_VBI_WSSDT)
+#define ENCI_VBI_WSS_LN 0x1b26 /* register.h:8219 */
+#define P_ENCI_VBI_WSS_LN VCBUS_REG_ADDR(ENCI_VBI_WSS_LN)
+#define ENCI_VBI_CGMSDT_L 0x1b27 /* register.h:8220 */
+#define P_ENCI_VBI_CGMSDT_L VCBUS_REG_ADDR(ENCI_VBI_CGMSDT_L)
+#define ENCI_VBI_CGMSDT_H 0x1b28 /* register.h:8221 */
+#define P_ENCI_VBI_CGMSDT_H VCBUS_REG_ADDR(ENCI_VBI_CGMSDT_H)
+#define ENCI_VBI_CGMS_LN 0x1b29 /* register.h:8222 */
+#define P_ENCI_VBI_CGMS_LN VCBUS_REG_ADDR(ENCI_VBI_CGMS_LN)
+#define ENCI_VBI_TTX_HTIME 0x1b2a /* register.h:8223 */
+#define P_ENCI_VBI_TTX_HTIME VCBUS_REG_ADDR(ENCI_VBI_TTX_HTIME)
+#define ENCI_VBI_TTX_LN 0x1b2b /* register.h:8224 */
+#define P_ENCI_VBI_TTX_LN VCBUS_REG_ADDR(ENCI_VBI_TTX_LN)
+#define ENCI_VBI_TTXDT0 0x1b2c /* register.h:8225 */
+#define P_ENCI_VBI_TTXDT0 VCBUS_REG_ADDR(ENCI_VBI_TTXDT0)
+#define ENCI_VBI_TTXDT1 0x1b2d /* register.h:8226 */
+#define P_ENCI_VBI_TTXDT1 VCBUS_REG_ADDR(ENCI_VBI_TTXDT1)
+#define ENCI_VBI_TTXDT2 0x1b2e /* register.h:8227 */
+#define P_ENCI_VBI_TTXDT2 VCBUS_REG_ADDR(ENCI_VBI_TTXDT2)
+#define ENCI_VBI_TTXDT3 0x1b2f /* register.h:8228 */
+#define P_ENCI_VBI_TTXDT3 VCBUS_REG_ADDR(ENCI_VBI_TTXDT3)
+#define ENCI_MACV_N0 0x1b30 /* register.h:8229 */
+#define P_ENCI_MACV_N0 VCBUS_REG_ADDR(ENCI_MACV_N0)
+#define ENCI_MACV_N1 0x1b31 /* register.h:8230 */
+#define P_ENCI_MACV_N1 VCBUS_REG_ADDR(ENCI_MACV_N1)
+#define ENCI_MACV_N2 0x1b32 /* register.h:8231 */
+#define P_ENCI_MACV_N2 VCBUS_REG_ADDR(ENCI_MACV_N2)
+#define ENCI_MACV_N3 0x1b33 /* register.h:8232 */
+#define P_ENCI_MACV_N3 VCBUS_REG_ADDR(ENCI_MACV_N3)
+#define ENCI_MACV_N4 0x1b34 /* register.h:8233 */
+#define P_ENCI_MACV_N4 VCBUS_REG_ADDR(ENCI_MACV_N4)
+#define ENCI_MACV_N5 0x1b35 /* register.h:8234 */
+#define P_ENCI_MACV_N5 VCBUS_REG_ADDR(ENCI_MACV_N5)
+#define ENCI_MACV_N6 0x1b36 /* register.h:8235 */
+#define P_ENCI_MACV_N6 VCBUS_REG_ADDR(ENCI_MACV_N6)
+#define ENCI_MACV_N7 0x1b37 /* register.h:8236 */
+#define P_ENCI_MACV_N7 VCBUS_REG_ADDR(ENCI_MACV_N7)
+#define ENCI_MACV_N8 0x1b38 /* register.h:8237 */
+#define P_ENCI_MACV_N8 VCBUS_REG_ADDR(ENCI_MACV_N8)
+#define ENCI_MACV_N9 0x1b39 /* register.h:8238 */
+#define P_ENCI_MACV_N9 VCBUS_REG_ADDR(ENCI_MACV_N9)
+#define ENCI_MACV_N10 0x1b3a /* register.h:8239 */
+#define P_ENCI_MACV_N10 VCBUS_REG_ADDR(ENCI_MACV_N10)
+#define ENCI_MACV_N11 0x1b3b /* register.h:8240 */
+#define P_ENCI_MACV_N11 VCBUS_REG_ADDR(ENCI_MACV_N11)
+#define ENCI_MACV_N12 0x1b3c /* register.h:8241 */
+#define P_ENCI_MACV_N12 VCBUS_REG_ADDR(ENCI_MACV_N12)
+#define ENCI_MACV_N13 0x1b3d /* register.h:8242 */
+#define P_ENCI_MACV_N13 VCBUS_REG_ADDR(ENCI_MACV_N13)
+#define ENCI_MACV_N14 0x1b3e /* register.h:8243 */
+#define P_ENCI_MACV_N14 VCBUS_REG_ADDR(ENCI_MACV_N14)
+#define ENCI_MACV_N15 0x1b3f /* register.h:8244 */
+#define P_ENCI_MACV_N15 VCBUS_REG_ADDR(ENCI_MACV_N15)
+#define ENCI_MACV_N16 0x1b40 /* register.h:8245 */
+#define P_ENCI_MACV_N16 VCBUS_REG_ADDR(ENCI_MACV_N16)
+#define ENCI_MACV_N17 0x1b41 /* register.h:8246 */
+#define P_ENCI_MACV_N17 VCBUS_REG_ADDR(ENCI_MACV_N17)
+#define ENCI_MACV_N18 0x1b42 /* register.h:8247 */
+#define P_ENCI_MACV_N18 VCBUS_REG_ADDR(ENCI_MACV_N18)
+#define ENCI_MACV_N19 0x1b43 /* register.h:8248 */
+#define P_ENCI_MACV_N19 VCBUS_REG_ADDR(ENCI_MACV_N19)
+#define ENCI_MACV_N20 0x1b44 /* register.h:8249 */
+#define P_ENCI_MACV_N20 VCBUS_REG_ADDR(ENCI_MACV_N20)
+#define ENCI_MACV_N21 0x1b45 /* register.h:8250 */
+#define P_ENCI_MACV_N21 VCBUS_REG_ADDR(ENCI_MACV_N21)
+#define ENCI_MACV_N22 0x1b46 /* register.h:8251 */
+#define P_ENCI_MACV_N22 VCBUS_REG_ADDR(ENCI_MACV_N22)
+#define ENCI_DBG_PX_RST 0x1b48 /* register.h:8253 */
+#define P_ENCI_DBG_PX_RST VCBUS_REG_ADDR(ENCI_DBG_PX_RST)
+#define ENCI_DBG_FLDLN_RST 0x1b49 /* register.h:8254 */
+#define P_ENCI_DBG_FLDLN_RST VCBUS_REG_ADDR(ENCI_DBG_FLDLN_RST)
+#define ENCI_DBG_PX_INT 0x1b4a /* register.h:8255 */
+#define P_ENCI_DBG_PX_INT VCBUS_REG_ADDR(ENCI_DBG_PX_INT)
+#define ENCI_DBG_FLDLN_INT 0x1b4b /* register.h:8256 */
+#define P_ENCI_DBG_FLDLN_INT VCBUS_REG_ADDR(ENCI_DBG_FLDLN_INT)
+#define ENCI_DBG_MAXPX 0x1b4c /* register.h:8257 */
+#define P_ENCI_DBG_MAXPX VCBUS_REG_ADDR(ENCI_DBG_MAXPX)
+#define ENCI_DBG_MAXLN 0x1b4d /* register.h:8258 */
+#define P_ENCI_DBG_MAXLN VCBUS_REG_ADDR(ENCI_DBG_MAXLN)
+#define ENCI_MACV_MAX_AMP 0x1b50 /* register.h:8259 */
+#define P_ENCI_MACV_MAX_AMP VCBUS_REG_ADDR(ENCI_MACV_MAX_AMP)
+#define ENCI_MACV_PULSE_LO 0x1b51 /* register.h:8260 */
+#define P_ENCI_MACV_PULSE_LO VCBUS_REG_ADDR(ENCI_MACV_PULSE_LO)
+#define ENCI_MACV_PULSE_HI 0x1b52 /* register.h:8261 */
+#define P_ENCI_MACV_PULSE_HI VCBUS_REG_ADDR(ENCI_MACV_PULSE_HI)
+#define ENCI_MACV_BKP_MAX 0x1b53 /* register.h:8262 */
+#define P_ENCI_MACV_BKP_MAX VCBUS_REG_ADDR(ENCI_MACV_BKP_MAX)
+#define ENCI_CFILT_CTRL 0x1b54 /* register.h:8263 */
+#define P_ENCI_CFILT_CTRL VCBUS_REG_ADDR(ENCI_CFILT_CTRL)
+#define ENCI_CFILT7 0x1b55 /* register.h:8264 */
+#define P_ENCI_CFILT7 VCBUS_REG_ADDR(ENCI_CFILT7)
+#define ENCI_YC_DELAY 0x1b56 /* register.h:8265 */
+#define P_ENCI_YC_DELAY VCBUS_REG_ADDR(ENCI_YC_DELAY)
+#define ENCI_VIDEO_EN 0x1b57 /* register.h:8266 */
+#define P_ENCI_VIDEO_EN VCBUS_REG_ADDR(ENCI_VIDEO_EN)
+#define VENC_VIDEO_PROG_MODE 0x1b68 /* /../ucode/register.h:8023 */
+#define P_VENC_VIDEO_PROG_MODE VCBUS_REG_ADDR(VENC_VIDEO_PROG_MODE)
+
+#define ENCI_DVI_HSO_BEGIN 0x1c00 /* register.h:8280 */
+#define P_ENCI_DVI_HSO_BEGIN VCBUS_REG_ADDR(ENCI_DVI_HSO_BEGIN)
+#define ENCI_DVI_HSO_END 0x1c01 /* register.h:8281 */
+#define P_ENCI_DVI_HSO_END VCBUS_REG_ADDR(ENCI_DVI_HSO_END)
+#define ENCI_DVI_VSO_BLINE_EVN 0x1c02 /* register.h:8282 */
+#define P_ENCI_DVI_VSO_BLINE_EVN VCBUS_REG_ADDR(ENCI_DVI_VSO_BLINE_EVN)
+#define ENCI_DVI_VSO_BLINE_ODD 0x1c03 /* register.h:8283 */
+#define P_ENCI_DVI_VSO_BLINE_ODD VCBUS_REG_ADDR(ENCI_DVI_VSO_BLINE_ODD)
+#define ENCI_DVI_VSO_ELINE_EVN 0x1c04 /* register.h:8284 */
+#define P_ENCI_DVI_VSO_ELINE_EVN VCBUS_REG_ADDR(ENCI_DVI_VSO_ELINE_EVN)
+#define ENCI_DVI_VSO_ELINE_ODD 0x1c05 /* register.h:8285 */
+#define P_ENCI_DVI_VSO_ELINE_ODD VCBUS_REG_ADDR(ENCI_DVI_VSO_ELINE_ODD)
+#define ENCI_DVI_VSO_BEGIN_EVN 0x1c06 /* register.h:8286 */
+#define P_ENCI_DVI_VSO_BEGIN_EVN VCBUS_REG_ADDR(ENCI_DVI_VSO_BEGIN_EVN)
+#define ENCI_DVI_VSO_BEGIN_ODD 0x1c07 /* register.h:8287 */
+#define P_ENCI_DVI_VSO_BEGIN_ODD VCBUS_REG_ADDR(ENCI_DVI_VSO_BEGIN_ODD)
+#define ENCI_DVI_VSO_END_EVN 0x1c08 /* register.h:8288 */
+#define P_ENCI_DVI_VSO_END_EVN VCBUS_REG_ADDR(ENCI_DVI_VSO_END_EVN)
+#define ENCI_DVI_VSO_END_ODD 0x1c09 /* register.h:8289 */
+#define P_ENCI_DVI_VSO_END_ODD VCBUS_REG_ADDR(ENCI_DVI_VSO_END_ODD)
+#define ENCI_CFILT_CTRL2 0x1c0a /* register.h:8295 */
+#define P_ENCI_CFILT_CTRL2 VCBUS_REG_ADDR(ENCI_CFILT_CTRL2)
+#define ENCI_DACSEL_0 0x1c0b /* register.h:8296 */
+#define P_ENCI_DACSEL_0 VCBUS_REG_ADDR(ENCI_DACSEL_0)
+#define ENCI_DACSEL_1 0x1c0c /* register.h:8297 */
+#define P_ENCI_DACSEL_1 VCBUS_REG_ADDR(ENCI_DACSEL_1)
+#define ENCP_DACSEL_0 0x1c0d /* register.h:8298 */
+#define P_ENCP_DACSEL_0 VCBUS_REG_ADDR(ENCP_DACSEL_0)
+#define ENCP_DACSEL_1 0x1c0e /* register.h:8299 */
+#define P_ENCP_DACSEL_1 VCBUS_REG_ADDR(ENCP_DACSEL_1)
+#define ENCP_MAX_LINE_SWITCH_POINT 0x1c0f /* register.h:8300 */
+#define P_ENCP_MAX_LINE_SWITCH_POINT VCBUS_REG_ADDR(ENCP_MAX_LINE_SWITCH_POINT)
+#define ENCI_TST_EN 0x1c10 /* register.h:8301 */
+#define P_ENCI_TST_EN VCBUS_REG_ADDR(ENCI_TST_EN)
+#define ENCI_TST_MDSEL 0x1c11 /* register.h:8302 */
+#define P_ENCI_TST_MDSEL VCBUS_REG_ADDR(ENCI_TST_MDSEL)
+#define ENCI_TST_Y 0x1c12 /* register.h:8303 */
+#define P_ENCI_TST_Y VCBUS_REG_ADDR(ENCI_TST_Y)
+#define ENCI_TST_CB 0x1c13 /* register.h:8304 */
+#define P_ENCI_TST_CB VCBUS_REG_ADDR(ENCI_TST_CB)
+#define ENCI_TST_CR 0x1c14 /* register.h:8305 */
+#define P_ENCI_TST_CR VCBUS_REG_ADDR(ENCI_TST_CR)
+#define ENCI_TST_CLRBAR_STRT 0x1c15 /* register.h:8306 */
+#define P_ENCI_TST_CLRBAR_STRT VCBUS_REG_ADDR(ENCI_TST_CLRBAR_STRT)
+#define ENCI_TST_CLRBAR_WIDTH 0x1c16 /* register.h:8307 */
+#define P_ENCI_TST_CLRBAR_WIDTH VCBUS_REG_ADDR(ENCI_TST_CLRBAR_WIDTH)
+#define ENCI_TST_VDCNT_STSET 0x1c17 /* register.h:8308 */
+#define P_ENCI_TST_VDCNT_STSET VCBUS_REG_ADDR(ENCI_TST_VDCNT_STSET)
+#define ENCI_VFIFO2VD_CTL 0x1c18 /* register.h:8313 */
+#define P_ENCI_VFIFO2VD_CTL VCBUS_REG_ADDR(ENCI_VFIFO2VD_CTL)
+#define ENCI_VFIFO2VD_PIXEL_START 0x1c19 /* register.h:8315 */
+#define P_ENCI_VFIFO2VD_PIXEL_START \
+ VCBUS_REG_ADDR(ENCI_VFIFO2VD_PIXEL_START)
+#define ENCI_VFIFO2VD_PIXEL_END 0x1c1a /* register.h:8317 */
+#define P_ENCI_VFIFO2VD_PIXEL_END VCBUS_REG_ADDR(ENCI_VFIFO2VD_PIXEL_END)
+#define ENCI_VFIFO2VD_LINE_TOP_START 0x1c1b /* register.h:8319 */
+#define P_ENCI_VFIFO2VD_LINE_TOP_START \
+ VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_TOP_START)
+#define ENCI_VFIFO2VD_LINE_TOP_END 0x1c1c /* register.h:8321 */
+#define P_ENCI_VFIFO2VD_LINE_TOP_END \
+ VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_TOP_END)
+#define ENCI_VFIFO2VD_LINE_BOT_START 0x1c1d /* register.h:8323 */
+#define P_ENCI_VFIFO2VD_LINE_BOT_START \
+ VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_BOT_START)
+#define ENCI_VFIFO2VD_LINE_BOT_END 0x1c1e /* register.h:8325 */
+#define P_ENCI_VFIFO2VD_LINE_BOT_END \
+ VCBUS_REG_ADDR(ENCI_VFIFO2VD_LINE_BOT_END)
+#define ENCI_VFIFO2VD_CTL2 0x1c1f /* register.h:8326 */
+#define P_ENCI_VFIFO2VD_CTL2 VCBUS_REG_ADDR(ENCI_VFIFO2VD_CTL2)
+
+#define ENCP_DVI_HSO_BEGIN 0x1c30 /* register.h:8354 */
+#define P_ENCP_DVI_HSO_BEGIN VCBUS_REG_ADDR(ENCP_DVI_HSO_BEGIN)
+#define ENCP_DVI_HSO_END 0x1c31 /* register.h:8355 */
+#define P_ENCP_DVI_HSO_END VCBUS_REG_ADDR(ENCP_DVI_HSO_END)
+#define ENCP_DVI_VSO_BLINE_EVN 0x1c32 /* register.h:8356 */
+#define P_ENCP_DVI_VSO_BLINE_EVN VCBUS_REG_ADDR(ENCP_DVI_VSO_BLINE_EVN)
+#define ENCP_DVI_VSO_BLINE_ODD 0x1c33 /* register.h:8357 */
+#define P_ENCP_DVI_VSO_BLINE_ODD VCBUS_REG_ADDR(ENCP_DVI_VSO_BLINE_ODD)
+#define ENCP_DVI_VSO_ELINE_EVN 0x1c34 /* register.h:8358 */
+#define P_ENCP_DVI_VSO_ELINE_EVN VCBUS_REG_ADDR(ENCP_DVI_VSO_ELINE_EVN)
+#define ENCP_DVI_VSO_ELINE_ODD 0x1c35 /* register.h:8359 */
+#define P_ENCP_DVI_VSO_ELINE_ODD VCBUS_REG_ADDR(ENCP_DVI_VSO_ELINE_ODD)
+#define ENCP_DVI_VSO_BEGIN_EVN 0x1c36 /* register.h:8360 */
+#define P_ENCP_DVI_VSO_BEGIN_EVN VCBUS_REG_ADDR(ENCP_DVI_VSO_BEGIN_EVN)
+#define ENCP_DVI_VSO_BEGIN_ODD 0x1c37 /* register.h:8361 */
+#define P_ENCP_DVI_VSO_BEGIN_ODD VCBUS_REG_ADDR(ENCP_DVI_VSO_BEGIN_ODD)
+#define ENCP_DVI_VSO_END_EVN 0x1c38 /* register.h:8362 */
+#define P_ENCP_DVI_VSO_END_EVN VCBUS_REG_ADDR(ENCP_DVI_VSO_END_EVN)
+#define ENCP_DVI_VSO_END_ODD 0x1c39 /* register.h:8363 */
+#define P_ENCP_DVI_VSO_END_ODD VCBUS_REG_ADDR(ENCP_DVI_VSO_END_ODD)
+#define ENCP_DE_H_BEGIN 0x1c3a /* register.h:8364 */
+#define P_ENCP_DE_H_BEGIN VCBUS_REG_ADDR(ENCP_DE_H_BEGIN)
+#define ENCP_DE_H_END 0x1c3b /* register.h:8365 */
+#define P_ENCP_DE_H_END VCBUS_REG_ADDR(ENCP_DE_H_END)
+#define ENCP_DE_V_BEGIN_EVEN 0x1c3c /* register.h:8366 */
+#define P_ENCP_DE_V_BEGIN_EVEN VCBUS_REG_ADDR(ENCP_DE_V_BEGIN_EVEN)
+#define ENCP_DE_V_END_EVEN 0x1c3d /* register.h:8367 */
+#define P_ENCP_DE_V_END_EVEN VCBUS_REG_ADDR(ENCP_DE_V_END_EVEN)
+#define ENCP_DE_V_BEGIN_ODD 0x1c3e /* register.h:8368 */
+#define P_ENCP_DE_V_BEGIN_ODD VCBUS_REG_ADDR(ENCP_DE_V_BEGIN_ODD)
+#define ENCP_DE_V_END_ODD 0x1c3f /* register.h:8369 */
+#define P_ENCP_DE_V_END_ODD VCBUS_REG_ADDR(ENCP_DE_V_END_ODD)
+#define ENCI_SYNC_LINE_LENGTH 0x1c40 /* register.h:8372 */
+#define P_ENCI_SYNC_LINE_LENGTH VCBUS_REG_ADDR(ENCI_SYNC_LINE_LENGTH)
+#define ENCI_SYNC_PIXEL_EN 0x1c41 /* register.h:8375 */
+#define P_ENCI_SYNC_PIXEL_EN VCBUS_REG_ADDR(ENCI_SYNC_PIXEL_EN)
+#define ENCI_SYNC_TO_LINE_EN 0x1c42 /* register.h:8382 */
+#define P_ENCI_SYNC_TO_LINE_EN VCBUS_REG_ADDR(ENCI_SYNC_TO_LINE_EN)
+#define ENCI_SYNC_TO_PIXEL 0x1c43 /* register.h:8384 */
+#define P_ENCI_SYNC_TO_PIXEL VCBUS_REG_ADDR(ENCI_SYNC_TO_PIXEL)
+#define ENCP_SYNC_LINE_LENGTH 0x1c44 /* register.h:8387 */
+#define P_ENCP_SYNC_LINE_LENGTH VCBUS_REG_ADDR(ENCP_SYNC_LINE_LENGTH)
+#define ENCP_SYNC_PIXEL_EN 0x1c45 /* register.h:8390 */
+#define P_ENCP_SYNC_PIXEL_EN VCBUS_REG_ADDR(ENCP_SYNC_PIXEL_EN)
+#define ENCP_SYNC_TO_LINE_EN 0x1c46 /* register.h:8397 */
+#define P_ENCP_SYNC_TO_LINE_EN VCBUS_REG_ADDR(ENCP_SYNC_TO_LINE_EN)
+#define ENCP_SYNC_TO_PIXEL 0x1c47 /* register.h:8399 */
+#define P_ENCP_SYNC_TO_PIXEL VCBUS_REG_ADDR(ENCP_SYNC_TO_PIXEL)
+
+#define VPP_POSTBLEND_H_SIZE 0x1d21
+#define P_VPP_POSTBLEND_H_SIZE VCBUS_REG_ADDR(VPP_POSTBLEND_H_SIZE)
+
+
+#define VPU_VIU_VENC_MUX_CTRL 0x271a /* register.h:9214 */
+#define P_VPU_VIU_VENC_MUX_CTRL VCBUS_REG_ADDR(VPU_VIU_VENC_MUX_CTRL)
+#define VPU_HDMI_SETTING 0x271b /* register.h:9229 */
+#define P_VPU_HDMI_SETTING VCBUS_REG_ADDR(VPU_HDMI_SETTING)
+
+#define VPU_HDMI_DATA_OVR 0x2727 /* register.h:9270 */
+#define P_VPU_HDMI_DATA_OVR VCBUS_REG_ADDR(VPU_HDMI_DATA_OVR)
+#define VPU_HDMI_FMT_CTRL 0x2743
+#define P_VPU_HDMI_FMT_CTRL VCBUS_REG_ADDR(VPU_HDMI_FMT_CTRL)
+/* For GXM and later */
+#define VPU_HDMI_DITH_CNTL 0x27fc
+#define P_VPU_HDMI_DITH_CNTL VCBUS_REG_ADDR(VPU_HDMI_DITH_CNTL)
+
+#endif
diff --git a/include/amlogic/media/vout/hdmitx21/hdmi_common.h b/include/amlogic/media/vout/hdmitx21/hdmi_common.h
new file mode 100644
index 0000000..db7c00d
--- /dev/null
+++ b/include/amlogic/media/vout/hdmitx21/hdmi_common.h
@@ -0,0 +1,708 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __HDMI_COMMON_H__
+#define __HDMI_COMMON_H__
+
+#include <hdmi.h>
+#include "../hdmitx_common.h"
+
+#define DDC_EDID_ADDR 0xA0
+ #define DDC_EDIDSEG_ADDR 0x30
+#define DDC_SCDC_ADDR 0xA8
+
+#define HDMI_PACKET_TYPE_GCP 0x3
+
+/* Little-Endian format */
+enum scdc_addr {
+ SINK_VER = 0x01,
+ SOURCE_VER, /* RW */
+ UPDATE_0 = 0x10, /* RW */
+ UPDATE_1, /* RW */
+ TMDS_CFG = 0x20, /* RW */
+ SCRAMBLER_ST,
+ CONFIG_0 = 0x30, /* RW */
+ STATUS_FLAGS_0 = 0x40,
+ STATUS_FLAGS_1,
+ ERR_DET_0_L = 0x50,
+ ERR_DET_0_H,
+ ERR_DET_1_L,
+ ERR_DET_1_H,
+ ERR_DET_2_L,
+ ERR_DET_2_H,
+ ERR_DET_CHKSUM,
+ TEST_CONFIG_0 = 0xC0, /* RW */
+ MANUFACT_IEEE_OUI_2 = 0xD0,
+ MANUFACT_IEEE_OUI_1,
+ MANUFACT_IEEE_OUI_0,
+ DEVICE_ID = 0xD3, /* 0xD3 ~ 0xDD */
+ /* RW 0xDE ~ 0xFF */
+ MANUFACT_SPECIFIC = 0xDE,
+};
+
+/* HDMI VIC definitions */
+enum hdmi_vic {
+ /* Refer to CEA 861-D */
+ HDMI_UNKNOWN = 0,
+ HDMI_1_640x480p60_4x3 = 1,
+ HDMI_2_720x480p60_4x3 = 2,
+ HDMI_3_720x480p60_16x9 = 3,
+ HDMI_4_1280x720p60_16x9 = 4,
+ HDMI_5_1920x1080i60_16x9 = 5,
+ HDMI_6_720x480i60_4x3 = 6,
+ HDMI_7_720x480i60_16x9 = 7,
+ HDMI_8_720x240p60_4x3 = 8,
+ HDMI_9_720x240p60_16x9 = 9,
+ HDMI_10_2880x480i60_4x3 = 10,
+ HDMI_11_2880x480i60_16x9 = 11,
+ HDMI_12_2880x240p60_4x3 = 12,
+ HDMI_13_2880x240p60_16x9 = 13,
+ HDMI_14_1440x480p60_4x3 = 14,
+ HDMI_15_1440x480p60_16x9 = 15,
+ HDMI_16_1920x1080p60_16x9 = 16,
+ HDMI_17_720x576p50_4x3 = 17,
+ HDMI_18_720x576p50_16x9 = 18,
+ HDMI_19_1280x720p50_16x9 = 19,
+ HDMI_20_1920x1080i50_16x9 = 20,
+ HDMI_21_720x576i50_4x3 = 21,
+ HDMI_22_720x576i50_16x9 = 22,
+ HDMI_23_720x288p_4x3 = 23,
+ HDMI_24_720x288p_16x9 = 24,
+ HDMI_25_2880x576i50_4x3 = 25,
+ HDMI_26_2880x576i50_16x9 = 26,
+ HDMI_27_2880x288p50_4x3 = 27,
+ HDMI_28_2880x288p50_16x9 = 28,
+ HDMI_29_1440x576p_4x3 = 29,
+ HDMI_30_1440x576p_16x9 = 30,
+ HDMI_31_1920x1080p50_16x9 = 31,
+ HDMI_32_1920x1080p24_16x9 = 32,
+ HDMI_33_1920x1080p25_16x9 = 33,
+ HDMI_34_1920x1080p30_16x9 = 34,
+ HDMI_35_2880x480p60_4x3 = 35,
+ HDMI_36_2880x480p60_16x9 = 36,
+ HDMI_37_2880x576p50_4x3 = 37,
+ HDMI_38_2880x576p50_16x9 = 38,
+ HDMI_39_1920x1080i_t1250_50_16x9 = 39,
+ HDMI_40_1920x1080i100_16x9 = 40,
+ HDMI_41_1280x720p100_16x9 = 41,
+ HDMI_42_720x576p100_4x3 = 42,
+ HDMI_43_720x576p100_16x9 = 43,
+ HDMI_44_720x576i100_4x3 = 44,
+ HDMI_45_720x576i100_16x9 = 45,
+ HDMI_46_1920x1080i120_16x9 = 46,
+ HDMI_47_1280x720p120_16x9 = 47,
+ HDMI_48_720x480p120_4x3 = 48,
+ HDMI_49_720x480p120_16x9 = 49,
+ HDMI_50_720x480i120_4x3 = 50,
+ HDMI_51_720x480i120_16x9 = 51,
+ HDMI_52_720x576p200_4x3 = 52,
+ HDMI_53_720x576p200_16x9 = 53,
+ HDMI_54_720x576i200_4x3 = 54,
+ HDMI_55_720x576i200_16x9 = 55,
+ HDMI_56_720x480p240_4x3 = 56,
+ HDMI_57_720x480p240_16x9 = 57,
+ HDMI_58_720x480i240_4x3 = 58,
+ HDMI_59_720x480i240_16x9 = 59,
+ HDMI_60_1280x720p24_16x9 = 60,
+ HDMI_61_1280x720p25_16x9 = 61,
+ HDMI_62_1280x720p30_16x9 = 62,
+ HDMI_63_1920x1080p120_16x9 = 63,
+ HDMI_64_1920x1080p100_16x9 = 64,
+ HDMI_65_1280x720p24_64x27 = 65,
+ HDMI_66_1280x720p25_64x27 = 66,
+ HDMI_67_1280x720p30_64x27 = 67,
+ HDMI_68_1280x720p50_64x27 = 68,
+ HDMI_69_1280x720p60_64x27 = 69,
+ HDMI_70_1280x720p100_64x27 = 70,
+ HDMI_71_1280x720p120_64x27 = 71,
+ HDMI_72_1920x1080p24_64x27 = 72,
+ HDMI_73_1920x1080p25_64x27 = 73,
+ HDMI_74_1920x1080p30_64x27 = 74,
+ HDMI_75_1920x1080p50_64x27 = 75,
+ HDMI_76_1920x1080p60_64x27 = 76,
+ HDMI_77_1920x1080p100_64x27 = 77,
+ HDMI_78_1920x1080p120_64x27 = 78,
+ HDMI_79_1680x720p24_64x27 = 79,
+ HDMI_80_1680x720p25_64x27 = 80,
+ HDMI_81_1680x720p30_64x27 = 81,
+ HDMI_82_1680x720p50_64x27 = 82,
+ HDMI_83_1680x720p60_64x27 = 83,
+ HDMI_84_1680x720p100_64x27 = 84,
+ HDMI_85_1680x720p120_64x27 = 85,
+ HDMI_86_2560x1080p24_64x27 = 86,
+ HDMI_87_2560x1080p25_64x27 = 87,
+ HDMI_88_2560x1080p30_64x27 = 88,
+ HDMI_89_2560x1080p50_64x27 = 89,
+ HDMI_90_2560x1080p60_64x27 = 90,
+ HDMI_91_2560x1080p100_64x27 = 91,
+ HDMI_92_2560x1080p120_64x27 = 92,
+ HDMI_93_3840x2160p24_16x9 = 93,
+ HDMI_94_3840x2160p25_16x9 = 94,
+ HDMI_95_3840x2160p30_16x9 = 95,
+ HDMI_96_3840x2160p50_16x9 = 96,
+ HDMI_97_3840x2160p60_16x9 = 97,
+ HDMI_98_4096x2160p24_256x135 = 98,
+ HDMI_99_4096x2160p25_256x135 = 99,
+ HDMI_100_4096x2160p30_256x135 = 100,
+ HDMI_101_4096x2160p50_256x135 = 101,
+ HDMI_102_4096x2160p60_256x135 = 102,
+ HDMI_103_3840x2160p24_64x27 = 103,
+ HDMI_104_3840x2160p25_64x27 = 104,
+ HDMI_105_3840x2160p30_64x27 = 105,
+ HDMI_106_3840x2160p50_64x27 = 106,
+ HDMI_107_3840x2160p60_64x27 = 107,
+ HDMI_108_1280x720p48_16x9 = 108,
+ HDMI_109_1280x720p48_64x27 = 109,
+ HDMI_110_1680x720p48_64x27 = 110,
+ HDMI_111_1920x1080p48_16x9 = 111,
+ HDMI_112_1920x1080p48_64x27 = 112,
+ HDMI_113_2560x1080p48_64x27 = 113,
+ HDMI_114_3840x2160p48_16x9 = 114,
+ HDMI_115_4096x2160p48_256x135 = 115,
+ HDMI_116_3840x2160p48_64x27 = 116,
+ HDMI_117_3840x2160p100_16x9 = 117,
+ HDMI_118_3840x2160p120_16x9 = 118,
+ HDMI_119_3840x2160p100_64x27 = 119,
+ HDMI_120_3840x2160p120_64x27 = 120,
+ HDMI_121_5120x2160p24_64x27 = 121,
+ HDMI_122_5120x2160p25_64x27 = 122,
+ HDMI_123_5120x2160p30_64x27 = 123,
+ HDMI_124_5120x2160p48_64x27 = 124,
+ HDMI_125_5120x2160p50_64x27 = 125,
+ HDMI_126_5120x2160p60_64x27 = 126,
+ HDMI_127_5120x2160p100_64x27 = 127,
+ /* 127 ~ 192 reserved */
+ HDMI_193_5120x2160p120_64x27 = 193,
+ HDMI_194_7680x4320p24_16x9 = 194,
+ HDMI_195_7680x4320p25_16x9 = 195,
+ HDMI_196_7680x4320p30_16x9 = 196,
+ HDMI_197_7680x4320p48_16x9 = 197,
+ HDMI_198_7680x4320p50_16x9 = 198,
+ HDMI_199_7680x4320p60_16x9 = 199,
+ HDMI_200_7680x4320p100_16x9 = 200,
+ HDMI_201_7680x4320p120_16x9 = 201,
+ HDMI_202_7680x4320p24_64x27 = 202,
+ HDMI_203_7680x4320p25_64x27 = 203,
+ HDMI_204_7680x4320p30_64x27 = 204,
+ HDMI_205_7680x4320p48_64x27 = 205,
+ HDMI_206_7680x4320p50_64x27 = 206,
+ HDMI_207_7680x4320p60_64x27 = 207,
+ HDMI_208_7680x4320p100_64x27 = 208,
+ HDMI_209_7680x4320p120_64x27 = 209,
+ HDMI_210_10240x4320p24_64x27 = 210,
+ HDMI_211_10240x4320p25_64x27 = 211,
+ HDMI_212_10240x4320p30_64x27 = 212,
+ HDMI_213_10240x4320p48_64x27 = 213,
+ HDMI_214_10240x4320p50_64x27 = 214,
+ HDMI_215_10240x4320p60_64x27 = 215,
+ HDMI_216_10240x4320p100_64x27 = 216,
+ HDMI_217_10240x4320p120_64x27 = 217,
+ HDMI_218_4096x2160p100_256x135 = 218,
+ HDMI_219_4096x2160p120_256x135 = 219,
+ HDMI_VIC_END,
+};
+
+enum hdmi_phy_para {
+ HDMI_PHYPARA_6G = 1, /* 2160p60hz 444 8bit */
+ HDMI_PHYPARA_4p5G, /* 2160p50hz 420 12bit */
+ HDMI_PHYPARA_3p7G, /* 2160p30hz 444 10bit */
+ HDMI_PHYPARA_3G, /* 2160p24hz 444 8bit */
+ HDMI_PHYPARA_LT3G, /* 1080p60hz 444 12bit */
+ HDMI_PHYPARA_DEF = HDMI_PHYPARA_LT3G,
+ HDMI_PHYPARA_270M, /* 480p60hz 444 8bit */
+};
+
+/* CEA TIMING STRUCT DEFINITION */
+struct hdmi_timing {
+ unsigned int vic;
+ char *name;
+ char *sname;
+ unsigned short pi_mode; /* 1: progressive 0: interlaced */
+ unsigned int h_freq; /* in Hz */
+ unsigned int v_freq; /* in 0.001 Hz */
+ unsigned int pixel_freq; /* Unit: 1000 */
+ unsigned short h_total;
+ unsigned short h_blank;
+ unsigned short h_front;
+ unsigned short h_sync;
+ unsigned short h_back;
+ unsigned short h_active;
+ unsigned short v_total;
+ unsigned short v_blank;
+ unsigned short v_front;
+ unsigned short v_sync;
+ unsigned short v_back;
+ unsigned short v_active;
+ unsigned short v_sync_ln;
+
+ unsigned short h_pol;
+ unsigned short v_pol;
+ unsigned short h_pict;
+ unsigned short v_pict;
+ unsigned short h_pixel;
+ unsigned short v_pixel;
+};
+
+/* Refer CEA861-D Page 116 Table 55 */
+struct dtd {
+ unsigned short pixel_clock;
+ unsigned short h_active;
+ unsigned short h_blank;
+ unsigned short v_active;
+ unsigned short v_blank;
+ unsigned short h_sync_offset;
+ unsigned short h_sync;
+ unsigned short v_sync_offset;
+ unsigned short v_sync;
+ u8 h_image_size;
+ u8 v_image_size;
+ u8 h_border;
+ u8 v_border;
+ u8 flags;
+ enum hdmi_vic vic;
+};
+
+/* Dolby Version support information from EDID*/
+/* Refer to DV Spec version2.9 page26 to page39*/
+enum block_type {
+ ERROR_NULL = 0,
+ ERROR_LENGTH,
+ ERROR_OUI,
+ ERROR_VER,
+ CORRECT,
+};
+
+#define DV_IEEE_OUI 0x00D046
+#define HDR10_PLUS_IEEE_OUI 0x90848B
+
+#define HDMI_PACKET_VEND 1
+#define HDMI_PACKET_DRM 0x86
+
+struct hdr_info {
+ unsigned int hdr_sup_eotf_sdr:1;
+ unsigned int hdr_sup_eotf_hdr:1;
+ unsigned int hdr_sup_eotf_smpte_st_2084:1;
+ unsigned int hdr_sup_eotf_hlg:1;
+ unsigned int hdr_sup_SMD_type1:1;
+ unsigned char hdr_lum_max;
+ unsigned char hdr_lum_avg;
+ unsigned char hdr_lum_min;
+ unsigned char rawdata[7];
+};
+
+struct hdr10_plus_info {
+ u32 ieeeoui;
+ u8 length;
+ u8 application_version;
+};
+
+enum hdmi_hdr_transfer {
+ T_UNKNOWN = 0,
+ T_BT709,
+ T_UNDEF,
+ T_BT601,
+ T_BT470M,
+ T_BT470BG,
+ T_SMPTE170M,
+ T_SMPTE240M,
+ T_LINEAR,
+ T_LOG100,
+ T_LOG316,
+ T_IEC61966_2_4,
+ T_BT1361E,
+ T_IEC61966_2_1,
+ T_BT2020_10,
+ T_BT2020_12,
+ T_SMPTE_ST_2084,
+ T_SMPTE_ST_28,
+ T_HLG,
+};
+
+enum hdmi_hdr_color {
+ C_UNKNOWN = 0,
+ C_BT709,
+ C_UNDEF,
+ C_BT601,
+ C_BT470M,
+ C_BT470BG,
+ C_SMPTE170M,
+ C_SMPTE240M,
+ C_FILM,
+ C_BT2020,
+};
+
+/* master_display_info for display device */
+struct master_display_info_s {
+ u32 present_flag;
+ u32 features; /* feature bits bt2020/2084 */
+ u32 primaries[3][2]; /* normalized 50000 in G,B,R order */
+ u32 white_point[2]; /* normalized 50000 */
+ u32 luminance[2]; /* max/min lumin, normalized 10000 */
+ u32 max_content; /* Maximum Content Light Level */
+ u32 max_frame_average; /* Maximum Frame-average Light Level */
+};
+
+struct hdr10plus_para {
+ u8 application_version;
+ u8 targeted_max_lum;
+ u8 average_maxrgb;
+ u8 distribution_values[9];
+ u8 num_bezier_curve_anchors;
+ u32 knee_point_x;
+ u32 knee_point_y;
+ u8 bezier_curve_anchors[9];
+ u8 graphics_overlay_flag;
+ u8 no_delay_flag;
+};
+
+struct dv_info {
+ unsigned char rawdata[27];
+ enum block_type block_flag;
+ u32 ieeeoui;
+ u8 ver; /* 0 or 1 or 2*/
+ u8 length;/*ver1: 15 or 12*/
+
+ u8 sup_yuv422_12bit:1;
+ /* if as 0, then support RGB tunnel mode */
+ u8 sup_2160p60hz:1;
+ /* if as 0, then support 2160p30hz */
+ u8 sup_global_dimming:1;
+ u16 Rx;
+ u16 Ry;
+ u16 Gx;
+ u16 Gy;
+ u16 Bx;
+ u16 By;
+ u16 Wx;
+ u16 Wy;
+ u16 tminPQ;
+ u16 tmaxPQ;
+ u8 dm_major_ver;
+ u8 dm_minor_ver;
+ u8 dm_version;
+ u8 tmaxLUM;
+ u8 colorimetry:1;/* ver1*/
+ u8 tminLUM;
+ u8 low_latency;/* ver1_12 and 2*/
+ u8 sup_backlight_control:1;/*only ver2*/
+ u8 backlt_min_luma;/*only ver2*/
+ u8 Interface;/*only ver2*/
+ u8 sup_10b_12b_444;/*only ver2*/
+ u8 support_DV_RGB_444_8BIT;
+ u8 support_LL_YCbCr_422_12BIT;
+ u8 support_LL_RGB_444_10BIT;
+ u8 support_LL_RGB_444_12BIT;
+};
+
+enum eotf_type {
+ EOTF_T_NULL = 0,
+ EOTF_T_DOLBYVISION,
+ EOTF_T_HDR10,
+ EOTF_T_SDR,
+ EOTF_T_LL_MODE,
+ EOTF_T_MAX,
+};
+
+enum mode_type {
+ YUV422_BIT12 = 0,
+ RGB_8BIT,
+ RGB_10_12BIT,
+ YUV444_10_12BIT,
+};
+
+/* Dolby Version VSIF parameter*/
+struct dv_vsif_para {
+ u8 ver; /* 0 or 1 or 2*/
+ u8 length;/*ver1: 15 or 12*/
+ union {
+ struct {
+ u8 low_latency:1;
+ u8 dobly_vision_signal:1;
+ u8 backlt_ctrl_MD_present:1;
+ u8 auxiliary_MD_present:1;
+ u8 eff_tmax_PQ_hi;
+ u8 eff_tmax_PQ_low;
+ u8 auxiliary_runmode;
+ u8 auxiliary_runversion;
+ u8 auxiliary_debug0;
+ } ver2;
+ } vers;
+};
+
+#define Y420CMDB_MAX 32
+#define VIC_MAX_NUM 256
+struct rx_cap {
+ unsigned int native_Mode;
+ /*video*/
+ unsigned int VIC[VIC_MAX_NUM];
+ unsigned int VIC_count;
+ unsigned int native_VIC;
+ /*vendor*/
+ unsigned int IEEEOUI;
+ unsigned int Max_TMDS_Clock1; /* HDMI1.4b TMDS_CLK */
+ unsigned int HF_IEEEOUI; /* For HDMI Forum */
+ unsigned int Max_TMDS_Clock2; /* HDMI2.0 TMDS_CLK */
+ /* CEA861-F, Table 56, Colorimetry Data Block */
+ unsigned int colorimetry_data;
+ unsigned int scdc_present:1;
+ unsigned int scdc_rr_capable:1; /* SCDC read request */
+ unsigned int lte_340mcsc_scramble:1;
+ unsigned support_ycbcr444_flag:1;
+ unsigned support_ycbcr422_flag:1;
+ unsigned int dc_y444:1;
+ unsigned int dc_30bit:1;
+ unsigned int dc_36bit:1;
+ unsigned int dc_48bit:1;
+ unsigned int dc_y420:1;
+ unsigned int dc_30bit_420:1;
+ unsigned int dc_36bit_420:1;
+ unsigned int dc_48bit_420:1;
+ unsigned char edid_version;
+ unsigned char edid_revision;
+ unsigned int ColorDeepSupport;
+ unsigned int Video_Latency;
+ unsigned int Audio_Latency;
+ unsigned int Interlaced_Video_Latency;
+ unsigned int Interlaced_Audio_Latency;
+ unsigned int threeD_present;
+ unsigned int threeD_Multi_present;
+ unsigned int hdmi_vic_LEN;
+ enum hdmi_vic preferred_mode;
+ struct dtd dtd[16];
+ unsigned char dtd_idx;
+ unsigned char flag_vfpdb;
+ unsigned char number_of_dtd;
+ unsigned char pref_colorspace;
+ struct hdr_info hdr_info;
+ struct dv_info dv_info;
+ struct hdr10_plus_info hdr10plus_info;
+ /*blk0 check sum*/
+ unsigned char chksum;
+ /*blk0-3 check sum*/
+ char checksum[10];
+ unsigned char edid_changed;
+ /* for total = 32*8 = 256 VICs */
+ /* for Y420CMDB bitmap */
+ unsigned char bitmap_valid;
+ unsigned char bitmap_length;
+ unsigned char y420_all_vic;
+ unsigned char y420cmdb_bitmap[Y420CMDB_MAX];
+};
+
+enum color_attr_type {
+ COLOR_ATTR_YCBCR444_12BIT = 0,
+ COLOR_ATTR_YCBCR422_12BIT,
+ COLOR_ATTR_YCBCR420_12BIT,
+ COLOR_ATTR_RGB_12BIT,
+ COLOR_ATTR_YCBCR444_10BIT,
+ COLOR_ATTR_YCBCR422_10BIT,
+ COLOR_ATTR_YCBCR420_10BIT,
+ COLOR_ATTR_RGB_10BIT,
+ COLOR_ATTR_YCBCR444_8BIT,
+ COLOR_ATTR_YCBCR422_8BIT,
+ COLOR_ATTR_YCBCR420_8BIT,
+ COLOR_ATTR_RGB_8BIT,
+ COLOR_ATTR_RESERVED,
+};
+
+struct color_attr_to_string {
+ enum color_attr_type color_attr;
+ const char *color_attr_string;
+};
+
+enum hdmi_color_depth {
+ COLORDEPTH_24B = 4,
+ COLORDEPTH_30B = 5,
+ COLORDEPTH_36B = 6,
+ COLORDEPTH_48B = 7,
+ COLORDEPTH_RESERVED,
+};
+
+enum hdmi_color_range {
+ COLORRANGE_LIM,
+ COLORRANGE_FUL,
+};
+
+enum hdmi_audio_packet {
+ HDMI_AUDIO_PACKET_SMP = 0x02,
+ HDMI_AUDIO_PACKET_1BT = 0x07,
+ HDMI_AUDIO_PACKET_DST = 0x08,
+ HDMI_AUDIO_PACKET_HBR = 0x09,
+};
+
+enum avi_component_conf {
+ CONF_AVI_CS,
+ CONF_AVI_BT2020,
+ CONF_AVI_Q01,
+ CONF_AVI_YQ01,
+ CONF_AVI_RGBYCC_INDIC,
+};
+
+/* CONF_AVI_BT2020 */
+#define CLR_AVI_BT2020 0x0
+#define SET_AVI_BT2020 0x1
+/* CONF_AVI_Q01 */
+#define RGB_RANGE_DEFAULT 0
+#define RGB_RANGE_LIM 1
+#define RGB_RANGE_FUL 2
+#define RGB_RANGE_RSVD 3
+/* CONF_AVI_YQ01 */
+#define YCC_RANGE_LIM 0
+#define YCC_RANGE_FUL 1
+#define YCC_RANGE_RSVD 2
+
+struct parse_cd {
+ enum hdmi_color_depth cd;
+ const char *name;
+};
+
+struct parse_cs {
+ enum hdmi_colorspace cs;
+ const char *name;
+};
+
+struct parse_cr {
+ enum hdmi_color_range cr;
+ const char *name;
+};
+
+#define EDID_BLK_NO 4
+#define EDID_BLK_SIZE 128
+struct hdmi_format_para {
+ char *sname; /* link to timing.sname or name */
+ enum hdmi_color_depth cd; /* cd8, cd10 or cd12 */
+ enum hdmi_colorspace cs; /* rgb, y444, y422, y420 */
+ enum hdmi_color_range cr; /* limit, full */
+ unsigned int pixel_repetition_factor;
+ unsigned int progress_mode:1; /* 0: Interlace 1: Progressive */
+ unsigned int scrambler_en:1;
+ unsigned int tmds_clk_div40:1;
+ unsigned int tmds_clk; /* Unit: 1000 */
+ struct hdmi_timing timing;
+};
+
+#define AUDIO_PARA_MAX_NUM 14
+struct hdmi_audio_fs_ncts {
+ struct {
+ u32 tmds_clk;
+ u32 n; /* 24 or 30 bit */
+ u32 cts; /* 24 or 30 bit */
+ u32 n_36bit;
+ u32 cts_36bit;
+ u32 n_48bit;
+ u32 cts_48bit;
+ } array[AUDIO_PARA_MAX_NUM];
+ u32 def_n;
+};
+
+/* Sampling Freq Fs:
+ * 0 - Refer to Stream Header;
+ * 1 - 32KHz;
+ * 2 - 44.1KHz;
+ * 3 - 48KHz;
+ * 4 - 88.2KHz...
+ */
+enum hdmi_audio_fs {
+ FS_REFER_TO_STREAM = 0,
+ FS_32K = 1,
+ FS_44K1 = 2,
+ FS_48K = 3,
+ FS_88K2 = 4,
+ FS_96K = 5,
+ FS_176K4 = 6,
+ FS_192K = 7,
+ FS_768K = 8,
+ FS_MAX,
+};
+
+enum hdmi_audio_chnnum {
+ CC_REFER_TO_STREAM = 0,
+ CC_2CH,
+ CC_3CH,
+ CC_4CH,
+ CC_5CH,
+ CC_6CH,
+ CC_7CH,
+ CC_8CH,
+ CC_MAX_CH
+};
+
+struct hdmi_support_mode {
+ enum hdmi_vic vic;
+ char *sname;
+ char y420;
+};
+
+#define DOLBY_VISION_LL_RGB 3
+#define DOLBY_VISION_LL_YUV 2
+#define DOLBY_VISION_STD_ENABLE 1
+#define DOLBY_VISION_DISABLE 0
+#define DOLBY_VISION_ENABLE 1
+
+#define HDMI_IEEEOUI 0x000C03
+#define MODE_LEN 32
+#define VESA_MAX_TIMING 64
+
+#define DEFAULT_OUTPUTMODE_ENV "1080p60hz"
+#define DEFAULT_HDMIMODE_ENV "1080p60hz"
+#define DEFAULT_COLORATTRIBUTE_ENV "444,8bit"
+
+#define DEFAULT_COLOR_FORMAT_4K "420,8bit"
+#define DEFAULT_COLOR_FORMAT "444,8bit"
+#define DEFAULT_HDMI_MODE "480p60hz"
+
+typedef enum {
+ DOLBY_VISION_PRIORITY = 0,
+ HDR10_PRIORITY = 1,
+ SDR_PRIORITY = 2,
+} hdr_priority_e;
+
+typedef enum {
+ HDR_POLICY_SINK = 0,
+ HDR_POLICY_SOURCE = 1,
+} hdr_policy_e;
+
+enum {
+ RESOLUTION_PRIORITY = 0,
+ FRAMERATE_PRIORITY = 1,
+};
+
+typedef struct input_hdmi_data {
+ char ubootenv_hdmimode[MODE_LEN];
+ char ubootenv_colorattribute[MODE_LEN];
+ int ubootenv_dv_type;
+ /* dynamic range fromat preference,0:dolby vision,1:hdr,2:sdr */
+ hdr_priority_e hdr_priority;
+ /* dynamic range policy,0 :follow sink, 1: match content */
+ hdr_policy_e hdr_policy;
+ struct rx_cap *prxcap;
+} hdmi_data_t;
+
+typedef struct scene_output_info {
+ char final_displaymode[MODE_LEN];
+ char final_deepcolor[MODE_LEN];
+ int final_dv_type;
+} scene_output_info_t;
+
+struct dispmode_vic {
+ const char *disp_mode;
+ enum hdmi_vic VIC;
+};
+
+#define HDCPTX_IOOPR 0x820000ab
+enum hdcptx_oprcmd {
+ HDCP_DEFAULT,
+ HDCP14_KEY_READY,
+ HDCP14_LOADKEY,
+ HDCP14_RESULT,
+ HDCP22_KEY_READY,
+ HDCP22_LOADKEY,
+ HDCP22_RESULT,
+ HDCP22_SET_TOPO,
+ HDCP22_GET_TOPO,
+ CONF_ENC_IDX, /* 0: get idx; 1: set idx */
+};
+
+#endif
diff --git a/include/amlogic/media/vout/hdmitx21/hdmitx_module.h b/include/amlogic/media/vout/hdmitx21/hdmitx_module.h
new file mode 100644
index 0000000..0afbe2b
--- /dev/null
+++ b/include/amlogic/media/vout/hdmitx21/hdmitx_module.h
@@ -0,0 +1,118 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __HDMITX_MODULE_H__
+#define __HDMITX_MODULE_H__
+
+#include "hdmi_common.h"
+#include "hdmitx_ext.h"
+
+struct hdmitx_dev {
+ struct {
+ int (*get_hpd_state)(void);
+ int (*read_edid)(unsigned char *buf);
+ void (*turn_off)(void);
+ void (*list_support_modes)(void);
+ void (*dump_regs)(void);
+ void (*test_bist)(unsigned int mode);
+ void (*test_prbs)(void);
+ void (*set_div40)(bool div40);
+ void (*output_blank)(unsigned int blank);
+ } hwop;
+ struct {
+ u32 enable;
+ union hdmi_infoframe vend;
+ union hdmi_infoframe avi;
+ union hdmi_infoframe spd;
+ union hdmi_infoframe aud;
+ union hdmi_infoframe drm;
+ } infoframes;
+ u32 colormetry;
+ unsigned char rawedid[EDID_BLK_SIZE * EDID_BLK_NO];
+ struct rx_cap RXCap;
+ struct hdmi_format_para *para;
+ enum hdmi_vic vic;
+ unsigned int frac_rate_policy;
+ unsigned int mode420;
+ unsigned int dc30;
+ enum eotf_type hdmi_current_eotf_type;
+ enum mode_type hdmi_current_tunnel_mode;
+ /* Add dongle_mode, clock, phy may be different from mbox */
+ unsigned int dongle_mode;
+ unsigned char limit_res_1080p;
+ unsigned char enc_idx;
+};
+
+struct hdmitx_dev *get_hdmitx21_device(void);
+const struct hdmi_timing *hdmitx21_get_timing_para0(void);
+int hdmitx21_timing_size(void);
+void hdmitx21_set_clk(struct hdmitx_dev *hdev);
+const struct hdmi_timing *hdmitx21_gettiming_from_vic(enum hdmi_vic vic);
+struct hdmi_format_para *hdmitx21_get_fmtpara(const char *mode,
+ const char *attr);
+struct hdmi_format_para *hdmitx21_get_fmt_name(char const *name, char const *attr);
+struct hdmi_format_para *hdmitx21_tst_fmt_name(char const *name, char const *attr);
+struct hdmi_format_para *hdmitx21_match_dtd_paras(struct dtd *t);
+
+void hdmitx21_set(struct hdmitx_dev *hdev);
+void hdmitx21_dump_regs(void);
+void hdmitx21_infoframe_send(u8 info_type, u8 *body);
+int hdmitx21_infoframe_rawget(u8 info_type, u8 *body);
+
+/* there are 2 ways to send out infoframes
+ * xxx_infoframe_set() will take use of struct xxx_infoframe_set
+ * xxx_infoframe_rawset() will directly send with rawdata
+ * if info, hb, or pb == NULL, disable send infoframe
+ */
+void hdmi_vend_infoframe_set(struct hdmi_vendor_infoframe *info);
+void hdmi_vend_infoframe_rawset(u8 *hb, u8 *pb);
+void hdmi_avi_infoframe_set(struct hdmi_avi_infoframe *info);
+void hdmi_avi_infoframe_rawset(u8 *hb, u8 *pb);
+void hdmi_spd_infoframe_set(struct hdmi_spd_infoframe *info);
+void hdmi_audio_infoframe_set(struct hdmi_audio_infoframe *info);
+void hdmi_audio_infoframe_rawset(u8 *hb, u8 *pb);
+void hdmi_drm_infoframe_set(struct hdmi_drm_infoframe *info);
+void hdmi_drm_infoframe_rawset(u8 *hb, u8 *pb);
+void hdmi_avi_infoframe_config(enum avi_component_conf conf, u8 val);
+
+bool edid_parsing_ok(struct hdmitx_dev *hdev);
+/* Parsing RAW EDID data from edid to prxcap */
+unsigned int hdmi_edid_parsing(unsigned char *edid, struct rx_cap *prxcap);
+void get_hdmi_data(struct hdmitx_dev *hdev, struct input_hdmi_data *data);
+bool is_dolby_enabled(void);
+bool is_tv_support_dv(struct hdmitx_dev *hdev);
+bool is_dv_preference(struct hdmitx_dev *hdev);
+bool is_hdr_preference(struct hdmitx_dev *hdev);
+void dolbyvision_scene_process(hdmi_data_t *hdmi_data,
+ scene_output_info_t *output_info);
+void sdr_scene_process(hdmi_data_t *hdmi_data,
+ scene_output_info_t *output_info);
+void hdr_scene_process(struct input_hdmi_data *hdmi_data,
+ scene_output_info_t *output_info);
+
+void get_hdmi_data(struct hdmitx_dev *hdev, hdmi_data_t *data);
+/* bool pre_process_str(char *name); */
+struct hdmi_format_para *hdmi_tst_fmt_name(char const *name, char const *attr);
+bool is_support_4k(void);
+bool is_supported_mode_attr(hdmi_data_t *hdmi_data, char *mode_attr);
+bool hdmitx_chk_mode_attr_sup(hdmi_data_t *hdmi_data, char *mode, char *attr);
+int get_ubootenv_dv_type(void);
+
+void hdmitx_set_phypara(enum hdmi_phy_para mode);
+int hdmitx_get_hpd_state(void);
+void hdmitx_turnoff(void);
+void hdmitx_test_prbs(void);
+enum hdmi_vic hdmitx_edid_get_VIC(struct hdmitx_dev *hdev,
+ const char *disp_mode, char force_flag);
+
+#undef printk
+#define printk printf
+#undef pr_info
+#define pr_info printf
+
+// TODO
+#define hdmitx_debug() printf("hdmitx21: %s[%d]\n", __func__, __LINE__)
+
+#endif
diff --git a/include/amlogic/media/vout/lcd/aml_bl.h b/include/amlogic/media/vout/lcd/aml_bl.h
new file mode 100644
index 0000000..fb8403d
--- /dev/null
+++ b/include/amlogic/media/vout/lcd/aml_bl.h
@@ -0,0 +1,145 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef INC_AML_LCD_BL_H
+#define INC_AML_LCD_BL_H
+
+#include <amlogic/media/vout/lcd/lcd_vout.h>
+
+#define BLPR(fmt, args...) printf("bl: "fmt"", ## args)
+#define BLERR(fmt, args...) printf("bl: error: "fmt"", ## args)
+
+enum bl_ctrl_method_e {
+ BL_CTRL_GPIO = 0,
+ BL_CTRL_PWM,
+ BL_CTRL_PWM_COMBO,
+ BL_CTRL_LOCAL_DIMMING,
+ BL_CTRL_EXTERN,
+ BL_CTRL_MAX,
+};
+
+enum bl_pwm_method_e {
+ BL_PWM_NEGATIVE = 0,
+ BL_PWM_POSITIVE,
+ BL_PWM_METHOD_MAX,
+};
+
+enum bl_pwm_port_e {
+ BL_PWM_A = 0,
+ BL_PWM_B,
+ BL_PWM_C,
+ BL_PWM_D,
+ BL_PWM_E,
+ BL_PWM_F,
+ BL_PWM_AO_A = 0x100,
+ BL_PWM_AO_B,
+ BL_PWM_AO_C,
+ BL_PWM_AO_D,
+ BL_PWM_AO_E,
+ BL_PWM_AO_F,
+ BL_PWM_AO_G,
+ BL_PWM_AO_H,
+ BL_PWM_VS = 0x200,
+ BL_PWM_MAX,
+};
+
+enum bl_off_policy_e {
+ BL_OFF_POLICY_NONE = 0,
+ BL_OFF_POLICY_ALWAYS,
+ BL_OFF_POLICY_ONCE,
+ BL_OFF_POLICY_MAX,
+};
+
+#define XTAL_FREQ_HZ (24*1000*1000) /* 24M in HZ */
+#define XTAL_HALF_FREQ_HZ (24*1000*500) /* 24M/2 in HZ */
+
+#define BL_FREQ_DEFAULT 1000 /* unit: HZ */
+#define BL_FREQ_VS_DEFAULT 2 /* multiple 2 of vfreq */
+
+#define BL_LEVEL_MAX 255
+#define BL_LEVEL_MIN 10
+#define BL_LEVEL_OFF 1
+
+#define BL_LEVEL_MID 128
+#define BL_LEVEL_MID_MAPPED BL_LEVEL_MID //102
+#define BL_LEVEL_DEFAULT BL_LEVEL_MID
+
+#define BL_GPIO_NUM_MAX 5
+#define BL_INDEX_INVALID 0xff
+
+struct bl_pwm_config_s {
+ unsigned int index;
+ enum bl_pwm_method_e pwm_method;
+ enum bl_pwm_port_e pwm_port;
+ unsigned int level_max;
+ unsigned int level_min;
+ unsigned int pwm_freq; /* pwm_vs: 1~4(vfreq), pwm: freq(unit: Hz) */
+ unsigned int pwm_duty; /* unit: % */
+ unsigned int pwm_duty_max; /* unit: % */
+ unsigned int pwm_duty_min; /* unit: % */
+ unsigned int pwm_cnt; /* internal used for pwm control */
+ unsigned int pwm_pre_div; /* internal used for pwm control */
+ unsigned int pwm_max; /* internal used for pwm control */
+ unsigned int pwm_min; /* internal used for pwm control */
+ unsigned int pwm_level; /* internal used for pwm control */
+ unsigned int pwm_hi; /* internal used for pwm control */
+ unsigned int pwm_lo; /* internal used for pwm control */
+ unsigned int pwm_gpio;
+ unsigned int pwm_gpio_off;
+ unsigned int pinmux_flag;
+ unsigned int pinmux_set[LCD_PINMUX_NUM][2];
+ unsigned int pinmux_clr[LCD_PINMUX_NUM][2];
+};
+
+#define BL_NAME_MAX 30
+struct bl_config_s {
+ unsigned int index;
+ char name[BL_NAME_MAX];
+ int level_default;
+ int level_min;
+ int level_max;
+ int level_mid;
+ int level_mid_mapping;
+
+ enum bl_ctrl_method_e method;
+ unsigned int en_gpio;
+ unsigned int en_gpio_on;
+ unsigned int en_gpio_off;
+ unsigned short power_on_delay;
+ unsigned short power_off_delay;
+ unsigned int dim_max;
+ unsigned int dim_min;
+ unsigned int en_sequence_reverse;
+
+ struct bl_pwm_config_s *bl_pwm;
+ struct bl_pwm_config_s *bl_pwm_combo0;
+ struct bl_pwm_config_s *bl_pwm_combo1;
+ unsigned int pwm_on_delay;
+ unsigned int pwm_off_delay;
+
+ char gpio_name[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX];
+ struct lcd_pinmux_ctrl_s *bl_pinmux;
+ unsigned int pinmux_set[10][2];
+ unsigned int pinmux_clr[10][2];
+ int extern_index;
+};
+
+struct aml_bl_drv_s {
+ unsigned int index;
+ unsigned int key_valid;
+ unsigned int state;
+ unsigned int level;
+ int bl_off_policy;
+ int factory_bl_on_delay;
+
+ struct bl_config_s config;
+ struct aml_lcd_data_s *data;
+};
+
+struct aml_bl_drv_s *aml_bl_get_driver(int index);
+void bl_driver_enable(int index);
+void bl_driver_disable(int index);
+
+#endif
diff --git a/include/amlogic/media/vout/lcd/aml_lcd.h b/include/amlogic/media/vout/lcd/aml_lcd.h
index ef3334a..26c4844 100644
--- a/include/amlogic/media/vout/lcd/aml_lcd.h
+++ b/include/amlogic/media/vout/lcd/aml_lcd.h
@@ -1,21 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * include/amlogic/media/vout/lcd/aml_lcd.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef INC_AML_LCD_H
@@ -24,6 +9,7 @@
#include <common.h>
#include <linux/list.h>
#include <amlogic/media/vout/lcd/lcd_vout.h>
+#include <amlogic/media/vout/lcd/aml_bl.h>
#ifdef CONFIG_AML_LCD_EXTERN
#include <amlogic/media/vout/lcd/lcd_extern.h>
#endif
@@ -31,54 +17,53 @@
#include <amlogic/media/vout/lcd/bl_extern.h>
#endif
-#define LCD_GPIO_MAX 0xff
-#define LCD_GPIO_OUTPUT_LOW 0
-#define LCD_GPIO_OUTPUT_HIGH 1
-#define LCD_GPIO_INPUT 2
+#define LCD_EXT_I2C_BUS_0 0 //A
+#define LCD_EXT_I2C_BUS_1 1 //B
+#define LCD_EXT_I2C_BUS_2 2 //C
+#define LCD_EXT_I2C_BUS_3 3 //D
+#define LCD_EXT_I2C_BUS_4 4 //AO
+#define LCD_EXT_I2C_BUS_MAX 0xff
+#define LCD_EXT_I2C_BUS_INVALID 0xff
+#define LCD_EXT_I2C_ADDR_INVALID 0xff
+#define LCD_EXT_GPIO_INVALID 0xff
-#define LCD_EXT_I2C_BUS_0 0 //A
-#define LCD_EXT_I2C_BUS_1 1 //B
-#define LCD_EXT_I2C_BUS_2 2 //C
-#define LCD_EXT_I2C_BUS_3 3 //D
-#define LCD_EXT_I2C_BUS_4 4 //AO
-#define LCD_EXT_I2C_BUS_MAX 0xff
+#define LCD_EXT_SPI_CLK_FREQ_DFT 10 /* unit: KHz */
+#define LCD_EXT_CMD_TYPE_CMD_DELAY 0x00
+#define LCD_EXT_CMD_TYPE_CMD2_DELAY 0x01 /* for i2c device 2nd addr */
+#define LCD_EXT_CMD_TYPE_CMD3_DELAY 0x02 /* for i2c device 3rd addr */
+#define LCD_EXT_CMD_TYPE_CMD4_DELAY 0x03 /* for i2c device 4th addr */
+#define LCD_EXT_CMD_TYPE_NONE 0x10
+#define LCD_EXT_CMD_TYPE_CMD_BIN2 0xa0 /* with data offset and data_len */
+#define LCD_EXT_CMD_TYPE_CMD2_BIN2 0xa1 /* for i2c device 2nd addr */
+#define LCD_EXT_CMD_TYPE_CMD3_BIN2 0xa2 /* for i2c device 3rd addr */
+#define LCD_EXT_CMD_TYPE_CMD4_BIN2 0xa3 /* for i2c device 4th addr */
+#define LCD_EXT_CMD_TYPE_CMD_BIN 0xb0
+#define LCD_EXT_CMD_TYPE_CMD2_BIN 0xb1 /* for i2c device 2nd addr */
+#define LCD_EXT_CMD_TYPE_CMD3_BIN 0xb2 /* for i2c device 3rd addr */
+#define LCD_EXT_CMD_TYPE_CMD4_BIN 0xb3 /* for i2c device 4th addr */
+#define LCD_EXT_CMD_TYPE_CMD 0xc0
+#define LCD_EXT_CMD_TYPE_CMD2 0xc1 /* for i2c device 2nd addr */
+#define LCD_EXT_CMD_TYPE_CMD3 0xc2 /* for i2c device 3rd addr */
+#define LCD_EXT_CMD_TYPE_CMD4 0xc3 /* for i2c device 4th addr */
+#define LCD_EXT_CMD_TYPE_CMD_BIN_DATA 0xd0 /* without auto fill reg addr 0x0 */
+#define LCD_EXT_CMD_TYPE_CMD2_BIN_DATA 0xd1 /* for i2c device 2nd addr */
+#define LCD_EXT_CMD_TYPE_CMD3_BIN_DATA 0xd2 /* for i2c device 3rd addr */
+#define LCD_EXT_CMD_TYPE_CMD4_BIN_DATA 0xd3 /* for i2c device 4th addr */
+#define LCD_EXT_CMD_TYPE_GPIO 0xf0
+#define LCD_EXT_CMD_TYPE_CHECK 0xfc
+#define LCD_EXT_CMD_TYPE_DELAY 0xfd
+#define LCD_EXT_CMD_TYPE_END 0xff
-#define LCD_EXT_I2C_BUS_INVALID 0xff
-#define LCD_EXT_I2C_ADDR_INVALID 0xff
-#define LCD_EXT_GPIO_INVALID 0xff
-
-#define LCD_EXT_SPI_CLK_FREQ_DFT 10 /* unit: KHz */
-
-
-#define LCD_EXT_CMD_TYPE_CMD_DELAY 0x00
-#define LCD_EXT_CMD_TYPE_CMD2_DELAY 0x01 /* for i2c device 2nd addr */
-#define LCD_EXT_CMD_TYPE_NONE 0x10
-#define LCD_EXT_CMD_TYPE_CMD 0xc0
-#define LCD_EXT_CMD_TYPE_CMD2 0xc1 /* for i2c device 2nd addr */
-#define LCD_EXT_CMD_TYPE_GPIO 0xf0
-#define LCD_EXT_CMD_TYPE_CHECK 0xfc
-#define LCD_EXT_CMD_TYPE_DELAY 0xfd
-#define LCD_EXT_CMD_TYPE_END 0xff
-
-#define LCD_EXT_CMD_SIZE_DYNAMIC 0xff
-#define LCD_EXT_DYNAMIC_SIZE_INDEX 1
-
-
-#define LCD_GPIO_NAME_MAX 15
-struct lcd_cpu_gpio_s {
- char name[LCD_GPIO_NAME_MAX];
- struct gpio_desc gpio;
- int probe_flag;
- int register_flag;
-};
+#define LCD_EXT_CMD_SIZE_DYNAMIC 0xff
+#define LCD_EXT_DYNAMIC_SIZE_INDEX 1
#define Rsv_val 0xffffffff
struct ext_lcd_config_s {
- const char panel_type[20];
- int lcd_type;
+ const char panel_type[15];
+ unsigned int lcd_type; // LCD_TTL /LCD_LVDS/LCD_VBYONE
unsigned char lcd_bits;
unsigned short h_active;
@@ -103,19 +88,19 @@
unsigned int customer_val_8;
unsigned int customer_val_9;
- unsigned int if_attr_val0;
- unsigned int if_attr_val1;
- unsigned int if_attr_val2;
- unsigned int if_attr_val3;
- unsigned int if_attr_val4;
- unsigned int if_attr_val5;
- unsigned int if_attr_val6;
- unsigned int if_attr_val7;
- unsigned int if_attr_val8;
- unsigned int if_attr_val9;
+ unsigned int lcd_spc_val0;
+ unsigned int lcd_spc_val1;
+ unsigned int lcd_spc_val2;
+ unsigned int lcd_spc_val3;
+ unsigned int lcd_spc_val4;
+ unsigned int lcd_spc_val5;
+ unsigned int lcd_spc_val6;
+ unsigned int lcd_spc_val7;
+ unsigned int lcd_spc_val8;
+ unsigned int lcd_spc_val9;
- unsigned char *cmd_init_on;
- unsigned char *cmd_init_off;
+ unsigned char *init_on;
+ unsigned char *init_off;
struct lcd_power_step_s *power_on_step;
struct lcd_power_step_s *power_off_step;
@@ -161,7 +146,10 @@
unsigned int bl_ext_index;
};
-#define LCD_NUM_MAX 10
+#define LCD_NUM_MAX 20
+#define LCD_PRBS_MODE_LVDS BIT(0)
+#define LCD_PRBS_MODE_VX1 BIT(1)
+#define LCD_PRBS_MODE_MAX 2
extern struct ext_lcd_config_s ext_lcd_config[LCD_NUM_MAX];
diff --git a/include/amlogic/media/vout/lcd/bl_extern.h b/include/amlogic/media/vout/lcd/bl_extern.h
index 6604672..98b055b 100644
--- a/include/amlogic/media/vout/lcd/bl_extern.h
+++ b/include/amlogic/media/vout/lcd/bl_extern.h
@@ -1,25 +1,11 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * include/amlogicmedia/vout/lcd/bl_extern.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef _INC_AML_BL_EXTERN_H_
#define _INC_AML_BL_EXTERN_H_
+#include <amlogic/media/vout/lcd/lcd_vout.h>
enum bl_extern_type_e {
BL_EXTERN_I2C = 0,
@@ -77,11 +63,11 @@
struct bl_extern_config_s *config;
};
-extern struct aml_bl_extern_driver_s *aml_bl_extern_get_driver(void);
-extern int aml_bl_extern_device_load(const void *dt_blob, int index);
+struct aml_bl_extern_driver_s *aml_bl_extern_get_driver(void);
+int bl_extern_device_load(char *dtaddr, int index);
extern struct bl_extern_config_s bl_extern_config_dtf;
#ifdef CONFIG_AML_LCD_TABLET
-extern int dsi_write_cmd(unsigned char *payload);
+int dsi_write_cmd(struct aml_lcd_drv_s *pdrv, unsigned char *payload)
#endif
#endif
diff --git a/include/amlogic/media/vout/lcd/bl_ldim.h b/include/amlogic/media/vout/lcd/bl_ldim.h
index fb42eb3..e9dbef0 100644
--- a/include/amlogic/media/vout/lcd/bl_ldim.h
+++ b/include/amlogic/media/vout/lcd/bl_ldim.h
@@ -1,21 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * include/amlogic/media/vout/lcd/bl_ldim.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef INC_AML_BL_LDIM_H
@@ -36,12 +21,6 @@
#define LDIM_INIT_ON_MAX 300
#define LDIM_INIT_OFF_MAX 20
-struct ldim_pinmux_ctrl_s {
- char *name;
- unsigned int pinmux_set[LCD_PINMUX_NUM][2];
- unsigned int pinmux_clr[LCD_PINMUX_NUM][2];
-};
-
struct ldim_config_s {
unsigned char row;
unsigned char col;
@@ -71,11 +50,15 @@
unsigned int init_off_cnt;
unsigned char pinctrl_ver;
- struct ldim_pinmux_ctrl_s *ldim_pinmux;
- struct bl_pwm_config_s pwm_config;
- char gpio_name[BL_GPIO_NUM_MAX][LCD_GPIO_NAME_MAX];
+ struct lcd_pinmux_ctrl_s *ldim_pinmux;
+ struct bl_pwm_config_s ldim_pwm_config;
+ struct bl_pwm_config_s analog_pwm_config;
+ void (*dim_range_update)(void);
+
+ char gpio_name[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX];
unsigned short bl_regnum;
+ unsigned int device_count;
};
#define LDIM_SPI_NAME_MAX 30
@@ -92,7 +75,7 @@
};
/*******global API******/
-struct aml_ldim_driver_s {
+struct ldim_driver_s {
int valid_flag;
int dev_index;
struct ldim_config_s *ldim_conf;
@@ -112,7 +95,8 @@
extern struct ldim_dev_config_s ldim_config_dft;
-extern struct aml_ldim_driver_s *aml_ldim_get_driver(void);
-extern int aml_ldim_probe(char *dt_addr, int flag); /* flag: 0=dts, 1=bsp, 2=unifykey */
+struct ldim_driver_s *ldim_get_driver(void);
+/* flag: 0=dts, 1=bsp, 2=unifykey */
+int ldim_probe(char *dt_addr, int flag);
#endif /* INC_AML_BL_LDIM_H */
diff --git a/include/amlogic/media/vout/lcd/lcd_extern.h b/include/amlogic/media/vout/lcd/lcd_extern.h
index dc6ef56..f3b2d88 100644
--- a/include/amlogic/media/vout/lcd/lcd_extern.h
+++ b/include/amlogic/media/vout/lcd/lcd_extern.h
@@ -1,27 +1,12 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * include/amlogic/media/vout/lcd/lcd_extern.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef _INC_AML_LCD_EXTERN_H_
#define _INC_AML_LCD_EXTERN_H_
-#include <amlogic/media/vout/lcd/lcd_vout.h>
+#include <amlogic/media/vout/lcd/lcd_vout.h>
enum lcd_extern_type_e {
LCD_EXTERN_I2C = 0,
LCD_EXTERN_SPI,
@@ -47,22 +32,31 @@
#define LCD_EXTERN_INIT_OFF_MAX 100
#define LCD_EXTERN_GPIO_NUM_MAX 6
-#define LCD_EXTERN_GPIO_LEN_MAX 10
+#define LCD_EXTERN_GPIO_LEN_MAX LCD_CPU_GPIO_NAME_MAX
#define LCD_EXTERN_INDEX_INVALID 0xff
#define LCD_EXTERN_NAME_LEN_MAX 30
#define LCD_EXTERN_NUM_MAX 20
-
+#define EXTERN_MUL_MAX 10
struct lcd_extern_config_s {
unsigned char index;
char name[LCD_EXTERN_NAME_LEN_MAX];
enum lcd_extern_type_e type;
unsigned char status;
+ unsigned char pinmux_valid;
+ unsigned char pinmux_gpio_off;
unsigned char i2c_addr;
unsigned char i2c_addr2;
+ unsigned char i2c_addr3;
+ unsigned char i2c_addr4;
unsigned char i2c_bus;
+ unsigned char i2c_sck_gpio;
+ unsigned char i2c_sda_gpio;
+ unsigned char spi_gpio_cs;
+ unsigned char spi_gpio_clk;
+ unsigned char spi_gpio_data;
unsigned char spi_clk_pol;
unsigned short spi_clk_freq; /*KHz */
unsigned short spi_delay_us;
@@ -77,39 +71,34 @@
struct lcd_extern_common_s {
unsigned char lcd_ext_key_valid;
- char gpio_name[LCD_EXTERN_GPIO_NUM_MAX][LCD_EXTERN_GPIO_LEN_MAX];
+ char gpio_name[LCD_EXTERN_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX];
+ unsigned int lcd_ext_num;
unsigned char i2c_bus;
- unsigned char i2c_gpio_sck;
- unsigned char i2c_gpio_sda;
-
- unsigned char spi_gpio_cs;
- unsigned char spi_gpio_clk;
- unsigned char spi_gpio_data;
-
- struct lcd_pinmux_ctrl_s *lcd_ext_pinmux;
+ unsigned char i2c_sck_gpio;
+ unsigned char i2c_sck_gpio_off;
+ unsigned char i2c_sda_gpio;
+ unsigned char i2c_sda_gpio_off;
unsigned int pinmux_set[LCD_PINMUX_NUM][2];
unsigned int pinmux_clr[LCD_PINMUX_NUM][2];
- unsigned char pinmux_gpio_off;
- unsigned char pinmux_valid;
};
//global API
-struct aml_lcd_extern_driver_s {
+struct lcd_extern_driver_s {
struct lcd_extern_config_s *config;
- struct lcd_extern_common_s *common;
- int (*reg_read) (unsigned char reg, unsigned char *buf);
- int (*reg_write) (unsigned char reg, unsigned char value);
+ int (*reg_read)(unsigned char reg, unsigned char *buf);
+ int (*reg_write)(unsigned char *buf, unsigned int len);
int (*power_on)(void);
int (*power_off)(void);
- void (*info_print)(void);
+ void (*info_print)(struct lcd_extern_config_s *econf);
};
-extern struct aml_lcd_extern_driver_s *aml_lcd_extern_get_driver(void);
-extern int aml_lcd_extern_probe(const void *dt_blob, int index);
-extern int aml_lcd_extern_remove(void);
+struct lcd_extern_driver_s *lcd_extern_get_driver(int index);
+int lcd_extern_probe(char *dtaddr, int index);
+int lcd_extern_remove(void);
+int lcd_extern_init(void);
-extern struct lcd_extern_config_s ext_config_dtf;
+extern struct lcd_extern_config_s ext_config_dtf[LCD_EXTERN_NUM_MAX];
extern struct lcd_extern_common_s ext_common_dft;
#endif
diff --git a/include/amlogic/media/vout/lcd/lcd_i2c_dev.h b/include/amlogic/media/vout/lcd/lcd_i2c_dev.h
new file mode 100644
index 0000000..55df485
--- /dev/null
+++ b/include/amlogic/media/vout/lcd/lcd_i2c_dev.h
@@ -0,0 +1,17 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _INC_AML_LCD_I2C_DEV_H_
+#define _INC_AML_LCD_I2C_DEV_H_
+
+void aml_lcd_i2c_bus_print(unsigned char i2c_bus);
+unsigned char aml_lcd_i2c_bus_get_sys(unsigned char i2c_bus);
+int aml_lcd_i2c_write(unsigned char i2c_bus, unsigned int i2c_addr,
+ unsigned char *buff, unsigned int len);
+int aml_lcd_i2c_read(unsigned char i2c_bus, unsigned i2c_addr,
+ unsigned char *buff, unsigned int len);
+
+#endif
+
diff --git a/include/amlogic/media/vout/lcd/lcd_tcon_data.h b/include/amlogic/media/vout/lcd/lcd_tcon_data.h
new file mode 100644
index 0000000..c4b807a
--- /dev/null
+++ b/include/amlogic/media/vout/lcd/lcd_tcon_data.h
@@ -0,0 +1,218 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef INC_AML_LCD_TCON_DATA_H
+#define INC_AML_LCD_TCON_DATA_H
+
+/* for data block header flag */
+#define LCD_TCON_DATA_VALID_VAC BIT(0)
+#define LCD_TCON_DATA_VALID_DEMURA BIT(1)
+#define LCD_TCON_DATA_VALID_ACC BIT(2)
+#define LCD_TCON_DATA_VALID_DITHER BIT(3)
+#define LCD_TCON_DATA_VALID_OD BIT(4)
+#define LCD_TCON_DATA_VALID_LOD BIT(5)
+
+/* for tconless data format */
+/* for tconless data block type */
+#define LCD_TCON_DATA_BLOCK_TYPE_NONE 0x00
+#define LCD_TCON_DATA_BLOCK_TYPE_DEMURA_SET 0x01
+#define LCD_TCON_DATA_BLOCK_TYPE_DEMURA_LUT 0x02
+#define LCD_TCON_DATA_BLOCK_TYPE_ACC_LUT 0x03
+#define LCD_TCON_DATA_BLOCK_TYPE_DITHER_LUT 0x04
+#define LCD_TCON_DATA_BLOCK_TYPE_OD_LUT 0x05
+#define LCD_TCON_DATA_BLOCK_TYPE_LOD_LUT 0x06
+#define LCD_TCON_DATA_BLOCK_TYPE_VAC 0x11
+#define LCD_TCON_DATA_BLOCK_TYPE_EXT 0xe0 /* pmu */
+#define LCD_TCON_DATA_BLOCK_TYPE_MAX 0xff
+
+/* for tconless data block part type */
+#define LCD_TCON_DATA_PART_TYPE_WR_N 0xd0
+#define LCD_TCON_DATA_PART_TYPE_WR_DDR 0xdd
+#define LCD_TCON_DATA_PART_TYPE_WR_MASK 0xb0
+#define LCD_TCON_DATA_PART_TYPE_RD_MASK 0xab
+#define LCD_TCON_DATA_PART_TYPE_CHK_WR_MASK 0xcb
+#define LCD_TCON_DATA_PART_TYPE_CHK_EXIT 0xce
+#define LCD_TCON_DATA_PART_TYPE_PARAM 0xf0 /* only for tool */
+#define LCD_TCON_DATA_PART_TYPE_DELAY 0xfd
+
+#define LCD_TCON_DATA_PART_FLAG_TUNINTG_LUT 0x00
+#define LCD_TCON_DATA_PART_FLAG_FIXED_LUT 0x10
+#define LCD_TCON_DATA_PART_FLAG_TUNINTG_REG 0x01
+#define LCD_TCON_DATA_PART_FLAG_FIXED_REG 0x11
+#define LCD_TCON_DATA_PART_FLAG_TUNINTG_PARAM 0x0f
+#define LCD_TCON_DATA_PART_FLAG_FIXED_PARAM 0x1f
+
+#define LCD_TCON_DATA_BLOCK_HEADER_SIZE 64
+#define LCD_TCON_DATA_BLOCK_NAME_SIZE 36
+#define LCD_TCON_DATA_PART_NAME_SIZE 48
+
+struct lcd_tcon_init_block_header_s {
+ unsigned int crc32;
+ unsigned int reserved;
+ unsigned int block_size;
+ unsigned short header_size;
+ unsigned short reserved1;
+ unsigned int block_type;
+ unsigned char reserved2[5];
+ unsigned char data_byte_width;
+ unsigned short chipid;
+ unsigned char name[LCD_TCON_DATA_BLOCK_NAME_SIZE];
+};
+
+struct lcd_tcon_data_block_header_s {
+ unsigned int crc32;
+ unsigned int raw_data_check;/* crc */
+ unsigned int block_size;
+ unsigned short header_size;
+ unsigned short ext_header_size;
+ unsigned int block_type;
+ unsigned int block_flag;
+ unsigned short init_priority; /*invalid*/
+ unsigned short chipid;
+ unsigned char name[LCD_TCON_DATA_BLOCK_NAME_SIZE];
+};
+
+struct lcd_tcon_data_block_ext_header_s {
+ unsigned short part_cnt;
+ unsigned char part_mapping_byte;
+ unsigned char reserved[13];
+};
+
+#define LCD_TCON_DATA_PART_WR_N_SIZE_PRE (LCD_TCON_DATA_PART_NAME_SIZE + 12)
+struct lcd_tcon_data_part_wr_n_s {
+ char name[LCD_TCON_DATA_PART_NAME_SIZE];
+ unsigned short part_id;
+ unsigned char tuning_flag;
+ unsigned char part_type;
+ unsigned char reg_addr_byte;
+ unsigned char reg_data_byte;
+ unsigned char reg_inc;
+ unsigned char reg_cnt;
+ unsigned int data_cnt;
+};
+
+#define LCD_TCON_DATA_PART_WR_DDR_SIZE_PRE (LCD_TCON_DATA_PART_NAME_SIZE + 12)
+struct lcd_tcon_data_part_wr_ddr_s {
+ char name[LCD_TCON_DATA_PART_NAME_SIZE];
+ unsigned short part_id;
+ unsigned char tuning_flag;
+ unsigned char part_type;
+ unsigned short axi_buf_id;
+ unsigned short data_byte;
+ unsigned int data_cnt;
+};
+
+#define LCD_TCON_DATA_PART_WR_MASK_SIZE_PRE (LCD_TCON_DATA_PART_NAME_SIZE + 6)
+struct lcd_tcon_data_part_wr_mask_s {
+ char name[LCD_TCON_DATA_PART_NAME_SIZE];
+ unsigned short part_id;
+ unsigned char tuning_flag;
+ unsigned char part_type;
+ unsigned char reg_addr_byte;
+ unsigned char reg_data_byte;
+};
+
+#define LCD_TCON_DATA_PART_RD_MASK_SIZE_PRE (LCD_TCON_DATA_PART_NAME_SIZE + 6)
+struct lcd_tcon_data_part_rd_mask_s {
+ char name[LCD_TCON_DATA_PART_NAME_SIZE];
+ unsigned short part_id;
+ unsigned char tuning_flag;
+ unsigned char part_type;
+ unsigned char reg_addr_byte;
+ unsigned char reg_data_byte;
+};
+
+#define LCD_TCON_DATA_PART_CHK_WR_MASK_SIZE_PRE (LCD_TCON_DATA_PART_NAME_SIZE + 9)
+struct lcd_tcon_data_part_chk_wr_mask_s {
+ char name[LCD_TCON_DATA_PART_NAME_SIZE];
+ unsigned short part_id;
+ unsigned char tuning_flag;
+ unsigned char part_type;
+ unsigned char reg_chk_addr_byte;
+ unsigned char reg_chk_data_byte;
+ unsigned char reg_wr_addr_byte;
+ unsigned char reg_wr_data_byte;
+ unsigned char data_chk_cnt;
+};
+
+#define LCD_TCON_DATA_PART_CHK_EXIT_SIZE_PRE (LCD_TCON_DATA_PART_NAME_SIZE + 6)
+struct lcd_tcon_data_part_chk_exit_s {
+ char name[LCD_TCON_DATA_PART_NAME_SIZE];
+ unsigned short part_id;
+ unsigned char tuning_flag;
+ unsigned char part_type;
+ unsigned char reg_addr_byte;
+ unsigned char reg_data_byte;
+};
+
+#define LCD_TCON_DATA_PART_DELAY_SIZE (LCD_TCON_DATA_PART_NAME_SIZE + 8)
+struct lcd_tcon_data_part_delay_s {
+ char name[LCD_TCON_DATA_PART_NAME_SIZE];
+ unsigned short part_id;
+ unsigned char tuning_flag;
+ unsigned char part_type;
+ unsigned int delay_us;
+};
+
+#define LCD_TCON_DATA_PART_PARAM_SIZE_PRE (LCD_TCON_DATA_PART_NAME_SIZE + 8)
+struct lcd_tcon_data_part_param_s {
+ char name[LCD_TCON_DATA_PART_NAME_SIZE];
+ unsigned short part_id;
+ unsigned char tuning_flag;
+ unsigned char part_type;
+ unsigned int param_size;
+};
+
+union lcd_tcon_data_part_u {
+ struct lcd_tcon_data_part_wr_n_s *wr_n;
+ struct lcd_tcon_data_part_wr_ddr_s *wr_ddr;
+ struct lcd_tcon_data_part_wr_mask_s *wr_mask;
+ struct lcd_tcon_data_part_rd_mask_s *rd_mask;
+ struct lcd_tcon_data_part_chk_wr_mask_s *chk_wr_mask;
+ struct lcd_tcon_data_part_chk_exit_s *chk_exit;
+ struct lcd_tcon_data_part_delay_s *delay;
+ struct lcd_tcon_data_part_param_s *param;
+};
+
+#define LCD_UKEY_TCON_SPI_BLOCK_SIZE_PRE 20
+struct lcd_tcon_spi_block_s {
+ unsigned short data_type;
+ unsigned short data_index; /* tcon_data_index, equal to init priority */
+ unsigned int data_flag;
+ unsigned int spi_offset;
+ unsigned int spi_size;
+ unsigned int param_cnt;
+
+ unsigned int data_raw_check; //crc...
+ unsigned int data_temp_size;
+ unsigned int data_new_size;
+
+ unsigned int *param;
+ unsigned char *raw_buf;
+ unsigned char *temp_buf;
+ unsigned char *new_buf;
+};
+
+struct lcd_tcon_spi_s {
+ unsigned short version;
+ unsigned int block_cnt;
+ unsigned int init_flag;
+ struct lcd_tcon_spi_block_s **spi_block;
+
+ unsigned char *ext_buf;
+ unsigned int ext_init_on_cnt;
+ unsigned int ext_init_off_cnt;
+
+ int (*data_read)(struct lcd_tcon_spi_block_s *spi_block);
+ int (*data_conv)(struct lcd_tcon_spi_block_s *spi_block);
+};
+
+struct lcd_tcon_spi_s *lcd_tcon_spi_get(void);
+
+unsigned int lcd_tcon_data_size_align(unsigned int size);
+unsigned char lcd_tcon_checksum(unsigned char *buf, unsigned int len);
+unsigned char lcd_tcon_lrc(unsigned char *buf, unsigned int len);
+
+#endif /* INC_AML_LCD_VOUT_H */
diff --git a/include/amlogic/media/vout/lcd/lcd_vout.h b/include/amlogic/media/vout/lcd/lcd_vout.h
index 7c05362..9fcaa23 100644
--- a/include/amlogic/media/vout/lcd/lcd_vout.h
+++ b/include/amlogic/media/vout/lcd/lcd_vout.h
@@ -1,21 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * include/amlogic/media/vout/lcd/lcd_vout.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef INC_AML_LCD_VOUT_H
@@ -25,21 +10,28 @@
#include <linux/list.h>
#include <dm.h>
#include <asm/gpio.h>
+#ifdef CONFIG_AML_LCD_TCON
+#include <amlogic/media/vout/lcd/lcd_tcon_data.h>
+#endif
/* **********************************
* debug print define
* ********************************** */
//#define LCD_DEBUG_INFO
extern unsigned int lcd_debug_print_flag;
+#define LCD_DBG_PR_NORMAL (1 << 0)
+#define LCD_DBG_PR_ADV (1 << 1) //tcon_data
+#define LCD_DBG_PR_CLK (1 << 2)
+#define LCD_DBG_PR_BL_NORMAL (1 << 4)
+#define LCD_DBG_PR_BL_ADV (1 << 5) //pwm, isr, ext, ldim
+#define LCD_DBG_PR_TEST (1 << 6)
+#define LCD_DBG_PR_REG (1 << 7)
-#ifdef BL33_DEBUG_PRINT
#define LCDPR(fmt, args...) printf("lcd: "fmt"", ## args)
-#else
-#define LCDPR(fmt, args...)
-#endif
-
#define LCDERR(fmt, args...) printf("lcd: error: "fmt"", ## args)
+#define LCD_MAX_DRV 3
+
/* **********************************
* clk parameter bit define
* pll_ctrl, div_ctrl, clk_ctrl
@@ -59,18 +51,20 @@
/* ******** clk_ctrl ******** */
#define CLK_CTRL_LEVEL 28 /* [30:28] */
+#define CLK_CTRL_FRAC_SHIFT 24 /* [24] */
#define CLK_CTRL_FRAC 0 /* [18:0] */
-#define LCD_PINMUX_END 0xff
-#define LCD_PINMUX_NUM 15
-
/* **********************************
* VENC to TCON sync delay
* ********************************** */
#define TTL_DELAY 13
+#define PRE_DE_DELAY 8
+#define LCD_PINMUX_END 0xff
+#define LCD_PINMUX_NUM 15
+
/* **********************************
* global control define
* ********************************** */
@@ -85,6 +79,10 @@
LCD_CHIP_G12B, /* 1 */
LCD_CHIP_TL1,
LCD_CHIP_SM1,
+ LCD_CHIP_TM2,
+ LCD_CHIP_T5,
+ LCD_CHIP_T5D,
+ LCD_CHIP_T7,
LCD_CHIP_MAX,
};
@@ -94,6 +92,8 @@
LCD_VBYONE,
LCD_MIPI,
LCD_MLVDS,
+ LCD_P2P,
+ LCD_EDP,
LCD_TYPE_MAX,
};
@@ -131,8 +131,11 @@
unsigned int pll_ctrl; /* pll settings */
unsigned int div_ctrl; /* divider settings */
unsigned int clk_ctrl; /* clock settings */
+ unsigned int bit_rate; /* Hz */
- unsigned int ss_level;
+ unsigned int ss_level; /* [15:12]: ss_freq, [11:8]: ss_mode,
+ * [7:0]: ss_level
+ */
unsigned short sync_duration_num;
unsigned short sync_duration_den;
@@ -196,48 +199,28 @@
#define VX1_HPD_DATA_DELAY_DFT 10 /* 10ms */
#define VX1_CDR_TRAINING_HOLD_DFT 200 /* 200ms */
-#define VX1_SW_FILTER_TIME_DFT 10 /* 10*100us=1ms */
-#define VX1_SW_FILTER_CNT_DFT 6
-#define VX1_SW_FILTER_RETRY_CNT_DFT 2
-#define VX1_SW_FILTER_RETRY_DLY_DFT 100 /* 100ms */
-#define VX1_SW_CDR_DET_TIME_DFT 20 /* 20us*100=2ms */
-#define VX1_SW_CDR_DET_CNT_DFT 100
-#define VX1_SW_CDR_TIMEOUT_CNT_DFT 100
-
struct vbyone_config_s {
unsigned int lane_count;
unsigned int region_num;
unsigned int byte_mode;
unsigned int color_fmt;
unsigned int phy_div;
- unsigned int bit_rate;
unsigned int phy_vswing; /*[5:4]:ext_pullup, [3:0]vswing*/
unsigned int phy_preem;
unsigned int ctrl_flag;
/* bit[0]:power_on_reset_en
- bit[1]:hpd_data_delay_en
- bit[2]:cdr_training_hold_en
- bit[3]:hw_filter_en
- bit[5:4]:sw_filter */
+ * bit[1]:hpd_data_delay_en
+ * bit[2]:cdr_training_hold_en
+ * bit[3]:hw_filter_en
+ */
/* ctrl timing */
unsigned int power_on_reset_delay; /* ms */
unsigned int hpd_data_delay; /* ms */
unsigned int cdr_training_hold; /* ms */
/* hw filter */
- unsigned int hpd_hw_filter_time; /* ms */
- unsigned int hpd_hw_filter_cnt;
- unsigned int lockn_hw_filter_time; /* ms */
- unsigned int lockn_hw_filter_cnt;
- /* sw filter */
- unsigned int vx1_sw_filter_en; /* 0=disable, 1=sw_filter, 2=sw_filter with sw_reset */
- unsigned int vx1_sw_filter_time; /* 100us base */
- unsigned int vx1_sw_filter_cnt;
- unsigned int vx1_sw_filter_retry_cnt;
- unsigned int vx1_sw_filter_retry_delay; /* ms base */
- unsigned int vx1_sw_cdr_detect_time; /* us base * 100 times, must cover tcon lockn pulse */
- unsigned int vx1_sw_cdr_detect_cnt;
- unsigned int vx1_sw_cdr_timeout_cnt;
+ unsigned int hw_filter_time;
+ unsigned int hw_filter_cnt;
};
/* mipi-dsi config */
@@ -249,6 +232,9 @@
#define SYNC_EVENT 0x1
#define BURST_MODE 0x2
+/* unit: MHz */
+#define MIPI_BIT_RATE_MAX 1000
+
/* command config */
#define DSI_CMD_SIZE_INDEX 1 /* byte[1] */
#define DSI_GPIO_INDEX 2 /* byte[2] */
@@ -260,7 +246,6 @@
unsigned char lane_num;
unsigned int bit_rate_max; /* MHz */
unsigned int bit_rate_min; /* MHz*/
- unsigned int bit_rate; /* Hz */
unsigned int clk_factor; /* bit_rate/pclk */
unsigned int factor_numerator;
unsigned int factor_denominator; /* 100 */
@@ -272,6 +257,7 @@
unsigned int venc_data_width;
unsigned int dpi_data_format;
+ unsigned int data_bits;
unsigned char *dsi_init_on;
unsigned char *dsi_init_off;
@@ -283,6 +269,29 @@
unsigned char check_state;
};
+struct edp_config_s {
+ unsigned char max_lane_count;
+ unsigned char max_link_rate;
+ unsigned char training_mode; /* 0=fast training, 1=auto training */
+ unsigned char dpcd_caps_en;
+ unsigned char sync_clk_mode;
+ unsigned char scramb_mode;
+ unsigned char enhanced_framing_en;
+ unsigned char edid_en;
+ unsigned char pn_swap;
+
+ unsigned int phy_vswing;
+ unsigned int phy_preem;
+
+ /* internal used */
+ unsigned char lane_count;
+ unsigned char link_rate;
+ unsigned int bit_rate;
+ unsigned char link_update;
+ unsigned char training_settings;
+ unsigned char main_stream_enable;
+};
+
struct mlvds_config_s {
unsigned int channel_num;
unsigned int channel_sel0;
@@ -295,15 +304,38 @@
/* internal used */
unsigned int pi_clk_sel; /* bit[9:0] */
- unsigned int bit_rate; /* Hz */
};
-struct lcd_ctrl_config_s {
- struct ttl_config_s *ttl_config;
- struct lvds_config_s *lvds_config;
- struct vbyone_config_s *vbyone_config;
- struct dsi_config_s *mipi_config;
- struct mlvds_config_s *mlvds_config;
+enum p2p_type_e {
+ P2P_CEDS = 0,
+ P2P_CMPI,
+ P2P_ISP,
+ P2P_EPI,
+ P2P_CHPI = 0x10, /* low common mode */
+ P2P_CSPI,
+ P2P_USIT,
+ P2P_MAX,
+};
+
+struct p2p_config_s {
+ unsigned int p2p_type;
+ unsigned int lane_num;
+ unsigned int channel_sel0;
+ unsigned int channel_sel1;
+ unsigned int pn_swap;
+ unsigned int bit_swap; /* MSB/LSB reverse */
+ unsigned int phy_vswing;
+ unsigned int phy_preem;
+};
+
+union lcd_ctrl_config_u {
+ struct ttl_config_s ttl_cfg;
+ struct lvds_config_s lvds_cfg;
+ struct vbyone_config_s vbyone_cfg;
+ struct dsi_config_s mipi_cfg;
+ struct edp_config_s edp_cfg;
+ struct mlvds_config_s mlvds_cfg;
+ struct p2p_config_s p2p_cfg;
};
/* **********************************
@@ -311,32 +343,53 @@
* ********************************** */
enum lcd_power_type_e {
LCD_POWER_TYPE_CPU = 0,
- LCD_POWER_TYPE_PMU,
- LCD_POWER_TYPE_SIGNAL,
- LCD_POWER_TYPE_EXTERN,
+ LCD_POWER_TYPE_PMU, /* 1 */
+ LCD_POWER_TYPE_SIGNAL, /* 2 */
+ LCD_POWER_TYPE_EXTERN, /* 3 */
+ LCD_POWER_TYPE_WAIT_GPIO, /* 4 */
+ LCD_POWER_TYPE_CLK_SS, /* 5 */
+ LCD_POWER_TYPE_TCON_SPI_DATA_LOAD, /* 6 */
LCD_POWER_TYPE_MAX,
};
-#define LCD_CPU_GPIO_NAME_MAX 15
+enum lcd_pmu_gpio_e {
+ LCD_PMU_GPIO0 = 0,
+ LCD_PMU_GPIO1,
+ LCD_PMU_GPIO2,
+ LCD_PMU_GPIO3,
+ LCD_PMU_GPIO4,
+ LCD_PMU_GPIO_MAX,
+};
+
+#define LCD_CLK_SS_BIT_FREQ 0
+#define LCD_CLK_SS_BIT_MODE 4
+
+#define LCD_GPIO_MAX 0xff
+#define LCD_GPIO_OUTPUT_LOW 0
+#define LCD_GPIO_OUTPUT_HIGH 1
+#define LCD_GPIO_INPUT 2
/* Power Control */
#define LCD_CPU_GPIO_NUM_MAX 10
+#define LCD_CPU_GPIO_NAME_MAX 15
+#define LCD_PMU_GPIO_NUM_MAX 3
#define LCD_PWR_STEP_MAX 15
struct lcd_power_step_s {
unsigned char type;
- int index; /* point to lcd_cpu_gpio or lcd_extern */
+ int index; /* point to lcd_cpu_gpio_s or lcd_pmu_gpio_s or lcd_extern */
unsigned short value;
unsigned short delay;
};
struct lcd_power_ctrl_s {
char cpu_gpio[LCD_CPU_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX];
+ int *pmu_gpio;
struct lcd_power_step_s power_on_step[LCD_PWR_STEP_MAX];
struct lcd_power_step_s power_off_step[LCD_PWR_STEP_MAX];
};
-#define LCD_PINMX_MAX 20
+#define LCD_PINMX_MAX 10
#define BL_PINMUX_MAX 20
#define LCD_PINMUX_NAME_LEN_MAX 30
struct lcd_pinmux_ctrl_s {
@@ -345,185 +398,162 @@
unsigned int pinmux_clr[LCD_PINMUX_NUM][2];
};
-#if CONFIG_BFT_TIME_SAVING_ENABLED
-#define LCD_ENABLE_RETRY_MAX 1
-#else
#define LCD_ENABLE_RETRY_MAX 3
-#endif
-
struct lcd_config_s {
- unsigned char lcd_mode;
- unsigned char lcd_key_valid;
- unsigned char lcd_clk_path; /* 0=hpll, 1=gp0_pll */
unsigned char retry_enable_flag;
unsigned char retry_enable_cnt;
unsigned int backlight_index;
- struct lcd_basic_s lcd_basic;
- struct lcd_timing_s lcd_timing;
- struct lcd_ctrl_config_s lcd_control;
- struct lcd_power_ctrl_s *lcd_power;
- unsigned char pinctrl_ver;
- struct lcd_pinmux_ctrl_s *lcd_pinmux;
+ struct lcd_basic_s basic;
+ struct lcd_timing_s timing;
+ union lcd_ctrl_config_u control;
+ struct lcd_power_ctrl_s power;
+ struct lcd_pinmux_ctrl_s *pinmux;
unsigned int pinmux_set[LCD_PINMUX_NUM][2];
unsigned int pinmux_clr[LCD_PINMUX_NUM][2];
};
-extern struct lcd_config_s lcd_config_dft;
-
-/* ==============backlight control config================== */
-enum bl_ctrl_method_e {
- BL_CTRL_GPIO = 0,
- BL_CTRL_PWM,
- BL_CTRL_PWM_COMBO,
- BL_CTRL_LOCAL_DIMMING,
- BL_CTRL_EXTERN,
- BL_CTRL_MAX,
+#define LCD_INIT_LEVEL_NORMAL 0
+#define LCD_INIT_LEVEL_PWR_OFF 1
+#define LCD_INIT_LEVEL_KERNEL_ON 2
+/*
+ *bit[31:20]: reserved
+ *bit[19:18]: lcd_init_level
+ *bit[17:16]: reserved
+ *bit[15:8]: advanced flag(p2p_type when lcd_type=p2p)
+ *bit[7:4]: lcd bits
+ *bit[3:0]: lcd_type
+ */
+struct lcd_boot_ctrl_s {
+ unsigned char lcd_type;
+ unsigned char lcd_bits;
+ unsigned char advanced_flag;
+ unsigned char init_level;
};
-enum bl_pwm_method_e {
- BL_PWM_NEGATIVE = 0,
- BL_PWM_POSITIVE,
- BL_PWM_METHOD_MAX,
+/*
+ *bit[31:30]: lcd mode(0=normal, 1=tv; 2=tablet, 3=TBD)
+ *bit[29:28]: lcd debug para source(0=normal, 1=dts, 2=unifykey,
+ * 3=bsp for uboot)
+ *bit[27:16]: reserved
+ *bit[15:8]: lcd test pattern
+ *bit[7:0]: lcd debug print flag
+ */
+struct lcd_debug_ctrl_s {
+ unsigned char debug_print_flag;
+ unsigned char debug_test_pattern;
+ unsigned char debug_para_source;
+ unsigned char debug_lcd_mode;
};
-enum bl_pwm_port_e {
- BL_PWM_A = 0,
- BL_PWM_B,
- BL_PWM_C,
- BL_PWM_D,
- BL_PWM_E,
- BL_PWM_F,
- BL_PWM_VS,
- BL_PWM_MAX,
-};
+struct lcd_dft_config_s {
+ char (*lcd_gpio)[LCD_CPU_GPIO_NAME_MAX];
-enum bl_off_policy_e {
- BL_OFF_POLICY_NONE = 0,
- BL_OFF_POLICY_ALWAYS,
- BL_OFF_POLICY_ONCE,
- BL_OFF_POLICY_MAX,
-};
+ unsigned char key_valid;
+ unsigned char clk_path; /* 0=default, 1=gp0_pll */
+ unsigned int mode;
+ struct ext_lcd_config_s *ext_lcd;
+ struct lcd_pinmux_ctrl_s *lcd_pinmux;
-#define XTAL_FREQ_HZ (24*1000*1000) /* 24M in HZ */
-#define XTAL_HALF_FREQ_HZ (24*1000*500) /* 24M/2 in HZ */
+#ifdef CONFIG_AML_LCD_EXTERN
+ char (*ext_gpio)[LCD_CPU_GPIO_NAME_MAX];
+ struct lcd_extern_common_s *ext_common;
+ struct lcd_extern_config_s *ext_conf;
+#endif
-#define BL_FREQ_DEFAULT 1000 /* unit: HZ */
-#define BL_FREQ_VS_DEFAULT 2 /* multiple 2 of vfreq */
-
-#define BL_LEVEL_MAX 255
-#define BL_LEVEL_MIN 10
-#define BL_LEVEL_OFF 1
-
-#define BL_LEVEL_MID 128
-#define BL_LEVEL_MID_MAPPED BL_LEVEL_MID //102
-#define BL_LEVEL_DEFAULT BL_LEVEL_MID
-
-#define BL_GPIO_NUM_MAX 5
-
-struct bl_pwm_config_s {
- unsigned int index;
- enum bl_pwm_method_e pwm_method;
- enum bl_pwm_port_e pwm_port;
- unsigned int level_max;
- unsigned int level_min;
- unsigned int pwm_freq; /* pwm_vs: 1~4(vfreq), pwm: freq(unit: Hz) */
- unsigned int pwm_duty; /* unit: % */
- unsigned int pwm_duty_max; /* unit: % */
- unsigned int pwm_duty_min; /* unit: % */
- unsigned int pwm_cnt; /* internal used for pwm control */
- unsigned int pwm_pre_div; /* internal used for pwm control */
- unsigned int pwm_max; /* internal used for pwm control */
- unsigned int pwm_min; /* internal used for pwm control */
- unsigned int pwm_level; /* internal used for pwm control */
- unsigned int pwm_gpio;
- unsigned int pwm_gpio_off;
- unsigned int pinmux_flag;
- unsigned int pinmux_set[10][2];
- unsigned int pinmux_clr[10][2];
-};
-
-struct bl_config_s {
- unsigned char bl_key_valid;
- char name[20];
- int level_default;
- int level_min;
- int level_max;
- int level_mid;
- int level_mid_mapping;
- int level;
-
- enum bl_ctrl_method_e method;
- unsigned int en_gpio;
- unsigned int en_gpio_on;
- unsigned int en_gpio_off;
- unsigned short power_on_delay;
- unsigned short power_off_delay;
- unsigned int dim_max;
- unsigned int dim_min;
- unsigned int en_sequence_reverse;
-
- struct bl_pwm_config_s *bl_pwm;
- struct bl_pwm_config_s *bl_pwm_combo0;
- struct bl_pwm_config_s *bl_pwm_combo1;
- unsigned int pwm_on_delay;
- unsigned int pwm_off_delay;
-
- char gpio_name[BL_GPIO_NUM_MAX][LCD_CPU_GPIO_NAME_MAX];
- unsigned char pinctrl_ver;
+ char (*bl_gpio)[LCD_CPU_GPIO_NAME_MAX];
struct lcd_pinmux_ctrl_s *bl_pinmux;
- unsigned int pinmux_set[10][2];
- unsigned int pinmux_clr[10][2];
- int bl_extern_index;
};
-extern struct bl_config_s bl_config_dft;
+struct aml_lcd_data_s {
+ enum lcd_chip_e chip_type;
+ const char *chip_name;
+ unsigned char rev_type;
+ unsigned char drv_max;
+ unsigned int offset_venc[LCD_MAX_DRV];
+ unsigned int offset_venc_if[LCD_MAX_DRV];
+ unsigned int offset_venc_data[LCD_MAX_DRV];
+ struct lcd_dft_config_s *dft_conf[LCD_MAX_DRV];
+};
/* ==============lcd driver================== */
+#define LCD_STATUS_IF_ON (1 << 0)
+#define LCD_STATUS_ENCL_ON (1 << 1)
+
struct aml_lcd_drv_s {
- char version[15];
- enum lcd_chip_e chip_type;
- unsigned char lcd_status;
+ unsigned int index;
+ unsigned int status;
+ unsigned char mode;
+ unsigned char key_valid;
+ unsigned char clk_path; /* 0=hpll, 1=gp0_pll */
- struct lcd_config_s *lcd_config;
- struct bl_config_s *bl_config;
+ struct lcd_config_s config;
+ struct aml_lcd_data_s *data;
+ struct lcd_boot_ctrl_s boot_ctrl;
+ void *clk_conf;
- int (*outputmode_check)(char *mode);
- int (*config_check)(char *mode);
- void (*driver_init_pre)(void);
- int (*driver_init)(void);
- void (*driver_disable)(void);
- void (*list_support_mode)(void);
- int (*lcd_probe)(void);
- int (*lcd_outputmode_check)(char *mode);
- void (*lcd_enable)(char *mode);
- void (*lcd_disable)(void);
- void (*lcd_set_ss)(int level);
- char *(*lcd_get_ss)(void);
- void (*lcd_test)(int num);
- void (*lcd_clk)(void);
- void (*lcd_info)(void);
- void (*lcd_reg)(void);
- void (*lcd_tcon_reg)(void);
- void (*lcd_tcon_table)(void);
- void (*bl_power_ctrl)(int status);
- void (*bl_set_level)(unsigned int level);
- unsigned int (*bl_get_level)(void);
- void (*bl_config_print)(void);
- int unifykey_test_flag;
- void (*unifykey_test)(void);
- void (*unifykey_tcon_test)(void);
- void (*unifykey_dump)(void);
- void (*lcd_extern_info)(void);
+ int (*outputmode_check)(struct aml_lcd_drv_s *pdrv, char *mode, unsigned int frac);
+ int (*config_check)(struct aml_lcd_drv_s *pdrv, char *mode, unsigned int frac);
+ void (*driver_init_pre)(struct aml_lcd_drv_s *pdrv);
+ int (*driver_init)(struct aml_lcd_drv_s *pdrv);
+ void (*driver_disable)(struct aml_lcd_drv_s *pdrv);
+ void (*list_support_mode)(struct lcd_config_s *pconf);
+#ifdef CONFIG_AML_LCD_TCON
+ void (*tcon_reg_print)(void);
+ void (*tcon_table_print)(void);
+ void (*tcon_vac_print)(void);
+ void (*tcon_demura_print)(void);
+ void (*tcon_acc_print)(void);
+ void (*tcon_data_print)(unsigned char index);
+ void (*tcon_spi_print)(void);
+ int (*tcon_spi_data_load)(void);
+ unsigned int (*tcon_reg_read)(unsigned int addr, unsigned int flag);
+ void (*tcon_reg_write)(unsigned int addr, unsigned int val,
+ unsigned int flag);
+ unsigned int (*tcon_table_read)(unsigned int addr);
+ unsigned int (*tcon_table_write)(unsigned int addr, unsigned int val);
+#endif
+ void *debug_info_reg;
+ void *debug_info_if;
+ void (*phy_set)(struct aml_lcd_drv_s *pdrv, int status);
/* for factory test */
struct lcd_power_step_s *factory_lcd_power_on_step;
- int factory_bl_power_on_delay;
};
extern void lcd_config_bsp_init(void);
-extern struct aml_lcd_drv_s *aml_lcd_get_driver(void);
+struct aml_lcd_data_s *aml_lcd_get_data(void);
+struct aml_lcd_drv_s *aml_lcd_get_driver(int index);
-extern int lcd_probe(void);
+int lcd_probe(void);
+
+/* global api for cmd */
+int aml_lcd_driver_probe(int index);
+void aml_lcd_driver_list_support_mode(void);
+unsigned int aml_lcd_driver_outputmode_check(char *mode, unsigned int frac);
+void aml_lcd_driver_prepare(int index, char *mode, unsigned int frac);
+void aml_lcd_driver_enable(int index, char *mode, unsigned int frac);
+void aml_lcd_driver_disable(int index);
+void aml_lcd_driver_set_ss(int index, unsigned int level, unsigned int freq,
+ unsigned int mode);
+void aml_lcd_driver_get_ss(int index);
+void aml_lcd_driver_clk_info(int index);
+void aml_lcd_driver_info(int index);
+void aml_lcd_driver_reg_info(int index);
+void aml_lcd_vbyone_rst(int index);
+void aml_lcd_vbyone_cdr(int index);
+void aml_lcd_driver_test(int index, int num);
+int aml_lcd_driver_prbs(int index, unsigned int s, unsigned int mode_flag);
+void aml_lcd_driver_unifykey_dump(int index, unsigned int flag);
+
+void aml_lcd_driver_ext_info(int index);
+void aml_lcd_driver_ext_power_on(int index);
+void aml_lcd_driver_ext_power_off(int index);
+
+void aml_lcd_driver_bl_on(int index);
+void aml_lcd_driver_bl_off(int index);
+void aml_lcd_driver_set_bl_level(int index, int level);
+unsigned int aml_lcd_driver_get_bl_level(int index);
+void aml_lcd_driver_bl_config_print(int index);
#endif /* INC_AML_LCD_VOUT_H */
diff --git a/include/amlogic/media/vpp/vpp.h b/include/amlogic/media/vpp/vpp.h
index acaec80..705fd6d 100644
--- a/include/amlogic/media/vpp/vpp.h
+++ b/include/amlogic/media/vpp/vpp.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef _VPP_INC_H_
#define _VPP_INC_H_
@@ -15,8 +20,12 @@
};
extern void vpp_load_gamma_table(unsigned short *data, unsigned int len, enum vpp_gamma_sel_e flag);
-extern void vpp_init_lcd_gamma_table(void);
+extern void vpp_init_lcd_gamma_table(int index);
+void vpp_enable_lcd_gamma_table(int index);
+void vpp_disable_lcd_gamma_table(int index);
extern void vpp_matrix_update(int type);
+extern void vpp_viu2_matrix_update(int type);
+extern void hdr_tx_pkt_cb(void);
#endif
diff --git a/include/amlogic/media/vpu/vpu.h b/include/amlogic/media/vpu/vpu.h
index 26bd575..9956ea3 100644
--- a/include/amlogic/media/vpu/vpu.h
+++ b/include/amlogic/media/vpu/vpu.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef _VPU_INC_H_
#define _VPU_INC_H_
diff --git a/include/amlogic/mmc_ts.h b/include/amlogic/mmc_ts.h
deleted file mode 100644
index 7fff101..0000000
--- a/include/amlogic/mmc_ts.h
+++ /dev/null
@@ -1,12 +0,0 @@
-#ifndef _MMC_TS_H
-#define _MMC_TS_H
-
-int mmc_ts_init(void);
-
-/* Get/set value, returns 0 on success */
-int mmc_ts_set(const char *key, const char *value);
-void mmc_ts_get(const char *key, char *value, unsigned int size);
-
-/* Get value as an integer, if missing/invalid return 'default_value' */
-int mmc_ts_get_int(const char *key, int default_value);
-#endif /* _MMC_TS_H */
diff --git a/include/amlogic/nand_ts.h b/include/amlogic/nand_ts.h
deleted file mode 100644
index 24faf78..0000000
--- a/include/amlogic/nand_ts.h
+++ /dev/null
@@ -1,13 +0,0 @@
-#ifndef _NAND_TS_H
-#define _NAND_TS_H
-
-int nand_ts_init(void);
-
-/* Get/set value, returns 0 on success */
-int nand_ts_set(const char *key, const char *value);
-void nand_ts_get(const char *key, char *value, unsigned int size);
-
-/* Get value as an integer, if missing/invalid return 'default_value' */
-int nand_ts_get_int(const char *key, int default_value);
-
-#endif /* _NAND_TS_H */
diff --git a/include/amlogic/saradc.h b/include/amlogic/saradc.h
new file mode 100644
index 0000000..92a7080
--- /dev/null
+++ b/include/amlogic/saradc.h
@@ -0,0 +1,108 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __MESON_SARADC_H__
+#define __MESON_SARADC_H__
+
+#include <common.h>
+#include <adc.h>
+#include <clk.h>
+
+enum ADC_CHANNEL_TYPE {
+ MESON_SARADC_CH0 = 0,
+ MESON_SARADC_CH1,
+ MESON_SARADC_CH2,
+ MESON_SARADC_CH3,
+ MESON_SARADC_CH4,
+ MESON_SARADC_CH5,
+ MESON_SARADC_CH6,
+ MESON_SARADC_CH7,
+ MESON_SARADC_CH_MAX,
+};
+
+enum MESON_SARADC_AVG_MODE {
+ NO_AVERAGING = 0x0,
+ MEAN_AVERAGING = 0x1,
+ MEDIAN_AVERAGING = 0x2,
+};
+
+enum MESON_SARADC_NUM_SAMPLES {
+ ONE_SAMPLE = 0x0,
+ TWO_SAMPLES = 0x1,
+ FOUR_SAMPLES = 0x2,
+ EIGHT_SAMPLES = 0x3,
+};
+
+enum MESON_SARADC_RESOLUTION {
+ SARADC_10BIT = 10,
+ SARADC_12BIT = 12,
+ SARADC_22BIT = 22,
+};
+
+enum MESON_SARADC_BIT_STATE {
+ BIT_LOW = 0,
+ BIT_HIGH = 1,
+};
+
+struct meson_saradc;
+
+struct meson_saradc_diff_ops {
+ void (*extra_init)(struct meson_saradc *priv);
+ void (*set_ch7_mux)(struct meson_saradc *priv, int ch, int mux);
+ void (*enable_decim_filter)(struct meson_saradc *priv,
+ int ch, unsigned int mode);
+ void (*set_ref_voltage)(struct meson_saradc *priv, unsigned int mode);
+ int (*get_fifo_channel)(int val);
+ int (*get_fifo_data)(struct meson_saradc *priv,
+ struct adc_uclass_platdata *uc_pdata, int val);
+};
+
+/*
+ * struct meson_saradc_data - describe the differences of different platform
+ *
+ * @reg3_ring_counter_disable: to disable continuous ring counter.
+ * gxl and later: 1; others(gxtvbb etc): 0
+ * @reg11_vref_en: g12a and later: 0; others(axg etc): 1
+ * @reg11_cmv_sel: g12a and later: 0; others(axg etc): 1
+ * @reg11_eoc: g12a and later: 1; others(axg etc): 0
+ * @has_bl30_integration:
+ * @num_channels: the number of adc channels
+ * @self_test_channel: channel of self-test
+ * @resolution: gxl and later: 12bit; others(gxtvbb etc): 10bit
+ * @clock_rate: saradc clock rate
+ */
+struct meson_saradc_data {
+ bool reg3_ring_counter_disable;
+ bool reg11_vref_en;
+ bool reg11_cmv_sel;
+ bool reg11_eoc;
+ bool has_bl30_integration;
+ unsigned char self_test_channel;
+ unsigned char num_channels;
+ unsigned int resolution;
+ const struct meson_saradc_diff_ops *dops;
+ unsigned int capacity;
+ unsigned long clock_rate;
+};
+
+struct meson_saradc {
+ phys_addr_t base;
+ int active_channel;
+ unsigned int current_mode;
+ struct clk xtal;
+ struct clk adc_mux;
+ struct clk adc_div;
+ struct clk adc_gate;
+ struct meson_saradc_data *data;
+};
+
+extern const struct adc_ops meson_saradc_ops;
+int meson_saradc_probe(struct udevice *dev);
+int meson_saradc_remove(struct udevice *dev);
+int meson_saradc_ofdata_to_platdata(struct udevice *dev);
+
+#define SARADC_CH_SELF_TEST MESON_SARADC_CH7
+
+#endif /*_MESON_SARADC_H_*/
diff --git a/include/amlogic/secure_storage.h b/include/amlogic/secure_storage.h
index 60e022c..56b6eca 100644
--- a/include/amlogic/secure_storage.h
+++ b/include/amlogic/secure_storage.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __SECURE_STORAGE_H__
#define __SECURE_STORAGE_H__
@@ -10,8 +15,6 @@
#define RET_EUND -1
#define SMC_UNK 0xffffffff
-/* Attribute*/
-#define OBJ_ATTR_SECURE (1<<0)
#ifdef CONFIG_SECURE_STORAGE
/* funtion name: secure_storage_write
diff --git a/include/amlogic/sound.h b/include/amlogic/sound.h
index 4aceb7c..e355fed 100644
--- a/include/amlogic/sound.h
+++ b/include/amlogic/sound.h
@@ -1,16 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * include/amlogic/sound.h
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the named License,
- * or any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef _SOUND_H_
diff --git a/include/amlogic/spicc.h b/include/amlogic/spicc.h
index 282af84..ccbd737 100644
--- a/include/amlogic/spicc.h
+++ b/include/amlogic/spicc.h
@@ -1,10 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Amlogic Meson SPI communication controller(SPICC)
- *
- * Copyright (C) 2017 Amlogic Corporation
- *
- * Licensed under the GPL-2 or later.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __SPICC_H__
diff --git a/include/amlogic/spifc.h b/include/amlogic/spifc.h
index 0eb7598..7b814c1 100644
--- a/include/amlogic/spifc.h
+++ b/include/amlogic/spifc.h
@@ -1,10 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Amlogic SPI flash controller(SPIFC)
- *
- * Copyright (C) 2018 Amlogic Corporation
- *
- * Licensed under the GPL-2 or later.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __SPIFC_H__
diff --git a/include/amlogic/storage.h b/include/amlogic/storage.h
index afc5d44..6b2b375 100644
--- a/include/amlogic/storage.h
+++ b/include/amlogic/storage.h
@@ -1,11 +1,6 @@
-/* SPDX-License-Identifier: GPL-2.0+ */
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Header file of storage interface module
- *
- * Copyright (C) 2018 Amlogic Corporation
- *
- * Licensed under the GPL-2 or later.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __STORAGE_H__
@@ -19,11 +14,14 @@
#include <asm/byteorder.h>
#include <jffs2/jffs2.h>
+#define RSV_UNVAIL 140 /* rsv unvail error */
+
#define DISPROTECT_KEY BIT(0)
#define DISPROTECT_SECURE BIT(1)
#define DISPROTECT_FBBT BIT(2)
#define DISPROTECT_HYNIX BIT(3)
+#define PART_PROTECT_FLAG BIT(4)
enum boot_type_e {
BOOT_EMMC = 1,
BOOT_SD = 1 << 1,
@@ -38,10 +36,88 @@
#define RSV_ENV "env"
#define RSV_DTB "dtb"
#define RSV_BBT "bbt"
+#define RSV_DDR_PARA "ddr_para"
#define DISCRETE_BOOTLOADER 1
#define COMPACT_BOOTLOADER 0
+struct nand_startup_parameter {
+ int page_size;
+ int block_size;
+ int layout_reserve_size;
+ int pages_per_block;
+ int setup_data;
+ /* */
+ int page0_disable;
+};
+
+#define BL2E_STORAGE_PARAM_SIZE (0x80)
+//#define BOOT_FIRST_BLOB_SIZE (166*1024)
+#define BOOT_FILLER_SIZE (4*1024)
+#define BOOT_RESERVED_SIZE (4*1024)
+#define BOOT_RANDOM_NONCE (16)
+#define BOOT_BL2E_SIZE (66672) //74864-8K
+#define BOOT_EBL2E_SIZE (BOOT_FILLER_SIZE + BOOT_RESERVED_SIZE + BOOT_BL2E_SIZE)
+#define BOOT_BL2X_SIZE (66672)
+#define MAX_BOOT_AREA_ENTRIES (8)
+/* bl2 core address base */
+#define BL2_CORE_BASE_OFFSET_EMMC (0x200)
+/* boot area entry index */
+#define BOOT_AREA_BB1ST (0)
+/* filler and reserved are considered part of the bl2E in storage view */
+#define BOOT_AREA_BL2E (1)
+#define BOOT_AREA_BL2X (2)
+#define BOOT_AREA_DDRFIP (3)
+#define BOOT_AREA_DEVFIP (4)
+#define BOOT_AREA_INVALID (MAX_BOOT_AREA_ENTRIES)
+
+typedef struct boot_area_entry {
+ /* name */
+ char name[11];
+ /* index */
+ uint8_t idx;
+ uint64_t offset;
+ uint64_t size;
+} boot_area_entry_t;
+
+struct boot_layout {
+ boot_area_entry_t *boot_entry;
+};
+
+struct emmc_startup_parameter {
+ //sd_emmc_setup_t setup;
+};
+
+struct spi_nand_startup_parameter {
+ uint32_t pagesize;
+ uint32_t pages_per_eraseblock;
+ uint32_t eraseblocks_per_lun;
+ uint32_t planes_per_lun;
+ uint32_t luns_per_target;
+ uint32_t ntargets;
+ int layout_reserve_size;
+};
+
+struct storage_boot_entry {
+ uint32_t offset;
+ uint32_t size;
+};
+
+union storage_independent_parameter {
+ struct nand_startup_parameter nsp;
+ struct emmc_startup_parameter esp;
+ struct spi_nand_startup_parameter snasp;
+};
+
+struct storage_startup_parameter {
+ uint8_t boot_device;
+ uint8_t boot_seq;
+ uint8_t boot_bakups;
+ uint8_t reserved;
+ struct storage_boot_entry boot_entry[MAX_BOOT_AREA_ENTRIES];
+ union storage_independent_parameter sip;
+};
+
struct storage_info_t {
u8 name[32];
u8 id[8];
@@ -57,6 +133,8 @@
struct storage_info_t info;
u32 init_flag;
struct list_head list;
+ int (*get_part_count)(void);
+ int (*list_part_name)(int idx, char *part_name);
/* when part_name is null, default to ops in whole chip */
/* int (*block_is_bad)(const char *part_name, loff_t off); */
u64 (*get_part_size)(const char *part_name);
@@ -75,7 +153,9 @@
int (*boot_write)(const char *part_name,
u8 cpy, size_t size, void *source);
int (*boot_erase)(const char *part_name, u8 cpy);
-
+ int (*gpt_read)(void *dest);
+ int (*gpt_write)(void *source);
+ int (*gpt_erase)(void);
u32 (*get_rsv_size)(const char *rsv_name);
int (*read_rsv)(const char *rsv_name, size_t size, void *buf);
int (*write_rsv)(const char *rsv_name, size_t size, void *buf);
@@ -245,6 +325,27 @@
u8 store_boot_copy_num(const char *name);
/**
+ * @usage: get the 1st boot copy nubmer of current device.
+ * for eMMC: 0 -> user partition; 1 -> boot0; 2 -> boot1
+ */
+u8 store_boot_copy_start(void);
+
+/**
+ * @usage: get the bootup index of [name]
+ *
+ * @name: do not care discrete mode or compact mode
+ * "bl2" "spl" could be used as the one romboot loaded
+ * "fip" "devfip" "tpl" or "bootloader" would be the main u-boot.
+ * @return: the copy number of the "bootloader" or "tpl"
+ */
+u8 store_bootup_bootidx(const char *name);
+
+/**
+ * @usage: restore the bootidx/bootdev etc.
+ */
+void store_restore_bootidx(void);
+
+/**
* @usage: get the copy size of [name]
*
* @name: name: only can be "bl2" or "tpl"/"fip" in discrete mode
@@ -382,4 +483,21 @@
* other = fail
*/
int store_rsv_protect(const char *name, bool ops);
+
+/**
+ * @usage: get bootloader mode for current storage
+ *
+ * @return: result of the operation
+ * 0 = COMPACT_BOOTLOADER
+ * 1 = DISCRETE_BOOTLOADER
+ */
+int store_get_device_bootloader_mode(void);
+
+int sheader_need(void);
+void sheader_load(void *addr);
+
+int store_gpt_read(void *buf);
+int store_gpt_write(void *buf);
+int store_gpt_erase(void);
+
#endif/* __STORAGE_H__ */
diff --git a/include/amlogic/storage_if.h b/include/amlogic/storage_if.h
deleted file mode 100644
index 1824821..0000000
--- a/include/amlogic/storage_if.h
+++ /dev/null
@@ -1,76 +0,0 @@
-/*
- * \file storage_if.h
- * \brief interfaces declarations for storage operations
- *
- * \version 1.0.0
- * \date 2013-7-16
- * \author Sam.Wu <yihui.wu@amlgic.com>
- *
- * Copyright (c) 2013 Amlogic. All Rights Reserved.
- *
- */
-#ifndef __STOARGE_IF_H__
-#define __STOARGE_IF_H__
-
-
-/***
-upgrade_read_ops:
-
-partition_name: env / logo / recovery /boot / system /cache /media
-
-***/
-int store_read_ops(unsigned char *partition_name,unsigned char * buf, uint64_t off, uint64_t size);
-
-
-/***
-upgrade_write_ops:
-
-partition_name: env / logo / recovery /boot / system /cache /media
-
-***/
-int store_write_ops(unsigned char *partition_name,unsigned char * buf,uint64_t off, uint64_t size);
-
-
-/***
-upgrade_write_ops:
-
-partition_name: env / logo / recovery /boot / system /cache /media
-
-***/
-int store_get_partititon_size(unsigned char *partition_name, uint64_t *size);
-
-
-/***
-upgrade_erase_ops:
-
-partition_name: boot / data
-
-flag = 0; indicate erase partition ;
-flag = 1; indicate scurb whole nand;
-
-***/
-int store_erase_ops(unsigned char *par_name, uint64_t off, uint64_t size, unsigned char flag);
-
-/***
-bootloader:
-***/
-int store_boot_read(unsigned char * buf, uint64_t off, uint64_t size);
-
-int store_boot_write(unsigned char * buf,uint64_t off, uint64_t size);
-
-int store_init(unsigned flag);
-
-int store_exit(void);
-
-//dtb read/write
-//@rwFlag: 0---read, 1---write, 2---iread
-int store_dtb_rw(void* buf, unsigned dtbSz, int rwFlag);
-
-//key read/write
-int store_key_read(uint8_t * buffer,
- uint32_t length, uint32_t *actual_lenth);
-int store_key_write(uint8_t * buffer,
- uint32_t length, uint32_t *actual_lenth);
-
-#endif//ifndef __STOARGE_IF_H__
-
diff --git a/include/amlogic/storagekey.h b/include/amlogic/storagekey.h
index f258b82..be3c803 100644
--- a/include/amlogic/storagekey.h
+++ b/include/amlogic/storagekey.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef __STORAGEKEY_H__
#define __STORAGEKEY_H__
diff --git a/include/amlogic/store_wrapper.h b/include/amlogic/store_wrapper.h
new file mode 100644
index 0000000..ddf4432
--- /dev/null
+++ b/include/amlogic/store_wrapper.h
@@ -0,0 +1,52 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __STORE_WRAPPER_H__
+#define __STORE_WRAPPER_H__
+#include <amlogic/storage.h>
+
+//logic write/read, if not MTD, same as store_write
+int store_logic_write(const char *name, loff_t off, size_t size, void *buf);
+
+int store_logic_read(const char *name, loff_t off, size_t size, void *buf);
+
+u64 store_logic_cap(const char* partName);
+
+int store_gpt_ops(size_t sz, void* buf, int isWr);
+
+#define AML_MAGIC_HDR_L (0x4c4d4140) //"@AML"
+#define AML_MAGIC_HDR_R (0x544f4f42) //"BOOT"
+
+#define AML_MAGIC_CORE (0X54534242) //"BBST"
+#define AML_MAGIC_BL2E (0x45324c42) //"BL2E"
+#define AML_MAGIC_BL2X (0x58324c42) //"BL2X"
+#define AML_MAGIC_DDRF (0x46524444) //"DDRF"
+#define AML_MAGIC_DEVF (0x46564544) //"DEVF"
+typedef struct{
+ unsigned int nMagic; //"BBST", "BL2E", "BL2X", "DDRF", "DEVF"
+ unsigned int nOffset; //offset from file head of file
+ unsigned int nPayLoadSize; //size of payload
+ unsigned int nReserved; //reserved for future
+}payload_info_item_t, *p_payload_info_item_t;
+
+typedef struct{
+ unsigned char szSHA2[32]; //sha256 of sizeof(payload_info_t) - sizeof(szSHA2)
+ unsigned int nMagicL; //"@AML"
+ unsigned int nMagicR; //"BOOT"
+ unsigned char byVersion; //version:0,1,2,....
+ unsigned char byItemNum; //number of items
+ unsigned short nSize; //sizeof(this) = sizeof(hdr) + sizeof(item) * byItemNum
+ unsigned char szReserved1[4];
+ char szTimeStamp[16];//"SC2-YYYYMMDDHHmm" e.g "SC2-202007082259"
+
+}payload_info_hdr_t, *p_payload_info_hdr_t;
+
+typedef struct{
+ payload_info_hdr_t hdr; //header
+ payload_info_item_t arrItems[1]; //items
+}payload_info_t, *p_payload_info_t;
+
+#endif//#ifndef __STORE_WRAPPER_H__
+
diff --git a/include/android_image.h b/include/android_image.h
index 0718e51..713cc03 100644
--- a/include/android_image.h
+++ b/include/android_image.h
@@ -11,18 +11,42 @@
#ifndef _ANDROID_IMAGE_H_
#define _ANDROID_IMAGE_H_
-typedef struct andr_img_hdr andr_img_hdr;
+#define _BA1_(cond, line) \
+ extern int __build_assertion_ ## line[1 - 2*!(cond)] \
+ __attribute__ ((unused))
+#define _BA0_(c, x) _BA1_(c, x)
+#define BUILD_ASSERT(cond) _BA0_(cond, __LINE__)
-#define ANDR_BOOT_MAGIC "ANDROID!"
-#define ANDR_BOOT_MAGIC_SIZE 8
-#define ANDR_BOOT_NAME_SIZE 16
-#define ANDR_BOOT_ARGS_SIZE 512
-#define ANDR_BOOT_EXTRA_ARGS_SIZE 1024
-#define ANDR_BOOT_KDTB_NOT_FOUND (-1)
-#define ANDR_BOOT_KDTB_INVALID (-2)
+#define BOOT_IMG_HDR_SIZE (0x800)
+#define BOOT_IMG_V3_HDR_SIZE (0x1000)
+#define VENDOR_BOOT_IMG_HDR_SIZE (0x1000)
-struct andr_img_hdr {
- char magic[ANDR_BOOT_MAGIC_SIZE];
+#define ANDR_BOOT_MAGIC "ANDROID!"
+#define ANDR_BOOT_MAGIC_SIZE (8)
+#define ANDR_BOOT_NAME_SIZE (16)
+#define ANDR_BOOT_ARGS_SIZE (512)
+
+#define BOOT_MAGIC "ANDROID!"
+#define BOOT_MAGIC_SIZE (8)
+#define BOOT_NAME_SIZE (16)
+#define BOOT_ARGS_SIZE (512)
+#define BOOT_EXTRA_ARGS_SIZE (1024)
+
+#define VENDOR_BOOT_MAGIC "VNDRBOOT"
+#define VENDOR_BOOT_MAGIC_SIZE (8)
+#define VENDOR_BOOT_ARGS_SIZE (2048)
+#define VENDOR_BOOT_NAME_SIZE (16)
+
+#define VENDOR_RAMDISK_TYPE_NONE 0
+#define VENDOR_RAMDISK_TYPE_PLATFORM 1
+#define VENDOR_RAMDISK_TYPE_RECOVERY 2
+#define VENDOR_RAMDISK_TYPE_DLKM 3
+#define VENDOR_RAMDISK_NAME_SIZE 32
+#define VENDOR_RAMDISK_TABLE_ENTRY_BOARD_ID_SIZE 16
+
+/* Before android R boot.img header structure */
+typedef struct {
+ char magic[BOOT_MAGIC_SIZE]; /*"ANDROID!"*/
u32 kernel_size; /* size in bytes */
u32 kernel_addr; /* physical load addr */
@@ -36,28 +60,42 @@
u32 tags_addr; /* physical addr for kernel tags */
u32 page_size; /* flash page size we assume */
- u32 kernel_version; /* highest byte: 1 = boot, 2 = recovery;
+ u32 header_version; /* highest byte: 1 = boot, 2 = recovery;
low three bytes: kernel version */
/* operating system version and security patch level; for
- * version "A.B.C" and patch level "Y-M-D":
- * ver = A << 14 | B << 7 | C (7 bits for each of A, B, C)
- * lvl = ((Y - 2000) & 127) << 4 | M (7 bits for Y, 4 bits for M)
- * os_version = ver << 11 | lvl */
- u32 os_version;
+ * version "A.B.C" and patch level "Y-M-D":
+ * ver = A << 14 | B << 7 | C (7 bits for each of A, B, C)
+ * lvl = ((Y - 2000) & 127) << 4 | M (7 bits for Y, 4 bits for M)
+ * os_version = ver << 11 | lvl */
+ uint32_t os_version;
- char name[ANDR_BOOT_NAME_SIZE]; /* asciiz product name */
+ char name[BOOT_NAME_SIZE]; /* asciiz product name */
- char cmdline[ANDR_BOOT_ARGS_SIZE];
+ char cmdline[BOOT_ARGS_SIZE];
- u32 id[8]; /* timestamp / checksum / sha1 / etc */
+ u32 id[8]; /* timestamp / checksum / sha1 / etc */
/* Supplemental command line data; kept here to maintain
- * binary compatibility with older versions of mkbootimg */
- char extra_cmdline[ANDR_BOOT_EXTRA_ARGS_SIZE];
-} __attribute__((packed));
+ binary compatibility with older versions of mkbootimg.
+ */
+ uint8_t extra_cmdline[BOOT_EXTRA_ARGS_SIZE];
+ unsigned char szReserved[BOOT_IMG_HDR_SIZE - 1632]; /*align to 2KB header,1632 is size before this*/
+}boot_img_hdr_t, *p_boot_img_hdr_t;
-/*
+/*compile check*/
+BUILD_ASSERT(sizeof(boot_img_hdr_t) == BOOT_IMG_HDR_SIZE);
+
+
+typedef struct {
+ boot_img_hdr_t hdr;
+ unsigned char szData[1];
+}boot_img_t, * p_boot_img_t;
+
+
+/* When the boot image header has a version of 3, the structure of the boot
+ * image is as follows:
+ *
* +-----------------+
* | boot header | 1 page
* +-----------------+
@@ -83,4 +121,137 @@
* 6. if second_size != 0: jump to second_addr
* else: jump to kernel_addr
*/
+
+
+#define ANDROID_R_IMG_VER (3)
+#define ANDROID_S_IMG_VER (4)
+
+/* Android R boot.img and vendor_boot.img structure */
+typedef struct {
+ char magic[ANDR_BOOT_MAGIC_SIZE]; /*"ANDROID!"*/
+
+ u32 kernel_size; /* size in bytes */
+ u32 ramdisk_size; /* size in bytes */
+
+ /* Operating system version and security patch level.
+ For version "A.B.C" and patch level "Y-M-D":
+ (7 bits for each of A, B, C; 7 bits for (Y-2000), 4 bits for M)
+ os_version = A[31:25] B[24:18] C[17:11] (Y-2000)[10:4] M[3:0]
+ */
+
+ uint32_t os_version;
+ uint32_t header_size;
+ uint32_t reserved[4];
+
+ uint32_t header_version; /* Version of the boot image header */
+ char cmdline[BOOT_ARGS_SIZE + BOOT_EXTRA_ARGS_SIZE];
+ unsigned char szReserved[BOOT_IMG_V3_HDR_SIZE - 1580]; /*align to 4KB header,1580 is size before this*/
+}boot_img_hdr_v3_t, * p_boot_img_hdr_v3_t;
+
+
+/*compile check*/
+BUILD_ASSERT(sizeof(boot_img_hdr_v3_t) == BOOT_IMG_V3_HDR_SIZE);
+
+typedef struct {
+ boot_img_hdr_v3_t hdr;
+ unsigned char szData[1];
+}boot_img_v3_t, * p_boot_img_v3_t;
+
+
+/* When the boot image header has a version of 3, the structure of the boot
+ * image is as follows:
+ *
+ * +---------------------+
+ * | boot header | 4096 bytes
+ * +---------------------+
+ * | kernel | m pages
+ * +---------------------+
+ * | ramdisk | n pages
+ * +---------------------+
+ *
+ * m = (kernel_size + 4096 - 1) / 4096
+ * n = (ramdisk_size + 4096 - 1) / 4096
+ *
+ * Note that in version 3 of the boot image header, page size is fixed at 4096 bytes.
+ *
+ * The structure of the vendor boot image (introduced with version 3 and
+ * required to be present when a v3 boot image is used) is as follows:
+ *
+ * +---------------------+
+ * | vendor boot header | o pages
+ * +---------------------+
+ * | vendor ramdisk | p pages
+ * +---------------------+
+ * | dtb | q pages
+ * +---------------------+
+ * o = (2112 + page_size - 1) / page_size
+ * p = (vendor_ramdisk_size + page_size - 1) / page_size
+ * q = (dtb_size + page_size - 1) / page_size
+ *
+ * 0. all entities in the boot image are 4096-byte aligned in flash, all
+ * entities in the vendor boot image are page_size (determined by the vendor
+ * and specified in the vendor boot image header) aligned in flash
+ * 1. kernel, ramdisk, vendor ramdisk, and DTB are required (size != 0)
+ * 2. load the kernel and DTB at the specified physical address (kernel_addr,
+ * dtb_addr) * 3. load the vendor ramdisk at ramdisk_addr
+ * 4. load the generic ramdisk immediately following the vendor ramdisk in
+ * memory
+ * 5. set up registers for kernel entry as required by your architecture
+ * 6. if the platform has a second stage bootloader jump to it (must be
+ * contained outside boot and vendor boot partitions), otherwise
+ * jump to kernel_addr
+ */
+
+struct vendor_boot_img_hdr {
+ char magic[VENDOR_BOOT_MAGIC_SIZE]; /*"VNDRBOOT"*/
+
+ uint32_t header_version; /*Version of the vendor boot image header*/
+ uint32_t page_size; /* flash page size we assume */
+
+ uint32_t kernel_addr; /* physical load addr */
+ uint32_t ramdisk_addr; /* physical load addr */
+
+ uint32_t vendor_ramdisk_size; /* size in bytes */
+
+ char cmdline[VENDOR_BOOT_ARGS_SIZE]; /*2048B*/
+
+ uint32_t tags_addr; /* physical addr for kernel tags (if required) */
+ uint8_t name[VENDOR_BOOT_NAME_SIZE]; /* 16B asciiz product name */
+
+ uint32_t header_size;
+
+ uint32_t dtb_size; /* size in bytes for DTB image */
+ uint64_t dtb_addr; /* physical load address for DTB image */
+ /* new for v4 */
+ u32 vendor_ramdisk_table_size;/* size in bytes for the vendor ramdisk table */
+ u32 vendor_ramdisk_table_entry_num;/* number of entries in the vendor ramdisk table */
+ u32 vendor_ramdisk_table_entry_size;
+ u32 vendor_bootconfig_size;/* size in bytes for bootconfig image */
+ unsigned char szReserved[VENDOR_BOOT_IMG_HDR_SIZE - 2128];
+};
+
+typedef struct vendor_boot_img_hdr vendor_boot_img_hdr_t;
+typedef struct vendor_boot_img_hdr *p_vendor_boot_img_hdr_t;
+
+struct vendor_ramdisk_table_entry_v4 {
+ u32 ramdisk_size; /* size in bytes for the ramdisk image */
+ u32 ramdisk_offset; /* offset to the ramdisk image in vendor ramdisk section */
+ u32 ramdisk_type; /* type of the ramdisk */
+ u8 ramdisk_name[VENDOR_RAMDISK_NAME_SIZE]; /* asciiz ramdisk name */
+ // Hardware identifiers describing the board, soc or platform which this
+ // ramdisk is intended to be loaded on.
+ u32 board_id[VENDOR_RAMDISK_TABLE_ENTRY_BOARD_ID_SIZE];
+};
+
+typedef struct vendor_ramdisk_table_entry_v4 vendor_ramdisk_table_entry_v4_t;
+typedef struct vendor_ramdisk_table_entry_v4 *p_vendor_ramdisk_table_entry_v4_t;
+
+/*compile check*/
+BUILD_ASSERT((sizeof(vendor_boot_img_hdr_t) == VENDOR_BOOT_IMG_HDR_SIZE));
+
+typedef struct {
+ vendor_boot_img_hdr_t hdr;
+ unsigned char szData[1];
+}vendor_boot_img_t, * p_vendor_boot_img_t;
+
#endif
diff --git a/include/android_vab.h b/include/android_vab.h
new file mode 100644
index 0000000..7539250
--- /dev/null
+++ b/include/android_vab.h
@@ -0,0 +1,58 @@
+/*Virtual A/B merge status information*/
+
+// Spaces used by misc partition are as below:
+// 0 - 2K For bootloader_message
+// 2K - 16K Used by Vendor's bootloader (the 2K - 4K range may be optionally used
+// as bootloader_message_ab struct)
+// 16K - 32K Used by uncrypt and recovery to store wipe_package for A/B devices
+// 32K - 64K System space, used for miscellanious AOSP features. See below.
+// Note that these offsets are admitted by bootloader,recovery and uncrypt, so they
+// are not configurable without changing all of them.
+
+#ifndef _ANDROID_VAB_H_
+#define _ANDROID_VAB_H_
+
+#define BOOTLOADER_MESSAGE_OFFSET_IN_MISC 0
+#define VENDOR_SPACE_OFFSET_IN_MISC 2 * 1024
+#define WIPE_PACKAGE_OFFSET_IN_MISC 16 * 1024
+#define SYSTEM_SPACE_OFFSET_IN_MISC 32 * 1024
+#define SYSTEM_SPACE_SIZE_IN_MISC 32 * 1024
+
+enum MergeStatus {
+ /**
+ * No snapshot or merge is in progress.
+ */
+ NONE = 0,
+
+ /**
+ * The merge status could not be determined.
+ */
+ UNKNOWN,
+
+ /**
+ * Partitions are being snapshotted, but no merge has been started.
+ */
+ SNAPSHOTTED,
+
+ /**
+ * At least one partition has merge is in progress.
+ */
+ MERGING,
+
+ /**
+ * A merge was in progress, but it was canceled by the bootloader.
+ */
+ CANCELLED,
+};
+
+// Holds Virtual A/B merge status information. Current version is 1. New fields
+// must be added to the end.
+struct misc_virtual_ab_message {
+ uint8_t version;
+ uint32_t magic;
+ uint8_t merge_status; // IBootControl 1.1, MergeStatus enum.
+ uint8_t source_slot; // Slot number when merge_status was written.
+ uint8_t reserved[57];
+};
+
+#endif
diff --git a/include/asm-generic/u-boot.h b/include/asm-generic/u-boot.h
index eee84f4..a06d347 100644
--- a/include/asm-generic/u-boot.h
+++ b/include/asm-generic/u-boot.h
@@ -14,7 +14,7 @@
#ifndef __ASM_GENERIC_U_BOOT_H__
#define __ASM_GENERIC_U_BOOT_H__
-
+//#define DEBUG
/*
* Board information passed to Linux kernel from U-Boot
*
diff --git a/include/bmp_layout.h b/include/bmp_layout.h
index 9380b52..8f3f445 100644
--- a/include/bmp_layout.h
+++ b/include/bmp_layout.h
@@ -55,5 +55,5 @@
#define BMP_BI_RGB 0
#define BMP_BI_RLE8 1
#define BMP_BI_RLE4 2
-
+#define BI_BITFIELDS 3
#endif /* _BMP_H_ */
diff --git a/include/board_variant.h b/include/board_variant.h
new file mode 100644
index 0000000..c622d8c
--- /dev/null
+++ b/include/board_variant.h
@@ -0,0 +1,15 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2022 Google LLC
+ */
+#ifndef _BOARD_VARIANT_H_
+#define _BOARD_VARIANT_H_
+
+#define BOARD_VARIANT_PROD 0xAA55
+#define BOARD_VARIANT_DEV 0x55AA
+#define BOARD_VARIANT_UNKNOWN 0xA5A5
+
+/* implement in $(BOARD)/$(BOARD).c */
+int get_board_variant(void);
+
+#endif // _BOARD_VARIANT_H_
diff --git a/include/bootm.h b/include/bootm.h
index daaf230..aea306c 100644
--- a/include/bootm.h
+++ b/include/bootm.h
@@ -36,7 +36,7 @@
extern boot_os_fn do_bootm_linux;
extern boot_os_fn do_bootm_vxworks;
-extern boot_os_fn do_bootm_zircon;
+
int do_bootelf(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]);
void lynxkdi_boot(image_header_t *hdr);
@@ -82,4 +82,6 @@
*/
void board_quiesce_devices(void);
+void jump_to_a32_kernel(unsigned long a, unsigned long b, unsigned long c);
+
#endif
diff --git a/include/chromecast/factory.h b/include/chromecast/factory.h
new file mode 100644
index 0000000..7f7914f
--- /dev/null
+++ b/include/chromecast/factory.h
@@ -0,0 +1,8 @@
+#ifndef _CHROMECAST_FACTORY_H_
+#define _CHROMECAST_FACTORY_H_
+
+#include <blk.h>
+
+int load_chromecast_factory_configs(struct blk_desc *dev_desc);
+
+#endif // _CHROMECAST_FACTORY_H_
diff --git a/include/chromecast/partition.h b/include/chromecast/partition.h
new file mode 100644
index 0000000..ff78598
--- /dev/null
+++ b/include/chromecast/partition.h
@@ -0,0 +1,38 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2021 Google LLC
+ */
+
+#ifndef _CHROMECAST_PARTITION_H_
+#define _CHROMECAST_PARTITION_H_
+
+#include <blk.h>
+
+#define CHROMECAST_PARTITION_ENTRY_NUMBERS CONFIG_EFI_PARTITION_ENTRIES_NUMBERS
+
+typedef enum {
+ CHROMECAST_PARTITION_MIGRATE_OP_NONE = 0,
+ CHROMECAST_PARTITION_MIGRATE_OP_ERASE,
+} chromecast_partition_migrate_op_t;
+
+typedef struct {
+ const char *name;
+ uint64_t start;
+ uint64_t size;
+ chromecast_partition_migrate_op_t migrate_op;
+} chromecast_partition_t;
+
+typedef struct {
+ // Make sure that 'align' is a multiple of the device block size.
+ // For eMMC, make sure that it's also a multiple of the erase group
+ // size.
+ uint64_t align;
+ uint64_t reserved;
+ chromecast_partition_t partitions[CHROMECAST_PARTITION_ENTRY_NUMBERS];
+} chromecast_partition_table_t;
+
+int init_chromecast_partitions(
+ struct blk_desc *dev_desc,
+ const chromecast_partition_table_t *partition_table);
+
+#endif // _CHROMECAST_PARTITION_H_
diff --git a/include/cli.h b/include/cli.h
index 66df5d5..39b9137 100644
--- a/include/cli.h
+++ b/include/cli.h
@@ -7,7 +7,6 @@
#ifndef __CLI_H
#define __CLI_H
-#ifdef CONFIG_CLI_ENABLED
/**
* Go into the command loop
*
@@ -15,7 +14,6 @@
* CONFIG_BOOT_RETRY_TIME.
*/
void cli_simple_loop(void);
-#endif /* CONFIG_CLI_ENABLED */
/**
* cli_simple_run_command() - Execute a command with the simple CLI
diff --git a/include/configs/g12a_u200_v1.h b/include/configs/g12a_u200_v1.h
deleted file mode 100644
index bf62879..0000000
--- a/include/configs/g12a_u200_v1.h
+++ /dev/null
@@ -1,686 +0,0 @@
-
-/*
- * board/amlogic/configs/g12a_u200_v1.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#ifndef __G12A_U200_V1_H__
-#define __G12A_U200_V1_H__
-
-#include <asm/arch/cpu.h>
-
-/* #define CONFIG_SYS_GENERIC_BOARD 1 */
-/*
-#ifndef CONFIG_AML_MESON
-#warning "include warning"
-#endif
-*/
-
-/*
- * platform power init config
- */
-#if 0
-#define CONFIG_PLATFORM_POWER_INIT
-#define CONFIG_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
-#define CONFIG_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
-#define CONFIG_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
-#endif
-
-#define AML_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
-#define AML_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
-#define AML_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
-
-/* configs for CEC */
-#if 0
-#define CONFIG_CEC_OSD_NAME "AML_TV"
-#define CONFIG_CEC_WAKEUP
-/*if use bt-wakeup,open it*/
-#define CONFIG_BT_WAKEUP
-#endif
-/* SMP Definitinos */
-#define CPU_RELEASE_ADDR secondary_boot_func
-
-/* config saradc*/
-#if 0
-#define CONFIG_CMD_SARADC 1
-#define CONFIG_SARADC_CH 2
-#endif
-
-/* Bootloader Control Block function
- That is used for recovery and the bootloader to talk to each other
- */
-#if 0
-#define CONFIG_BOOTLOADER_CONTROL_BLOCK
-#endif
-
-/* Serial config */
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_BAUDRATE 115200
-/* #define CONFIG_AML_MESON_SERIAL 1 */
-#if 0
-#define CONFIG_SERIAL_MULTI 1
-#endif
-
-/* Enable ir remote wake up for bl30 */
-#if 0
-#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
-#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
-#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
-#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
-#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
-#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
-#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
-#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
-#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
-#endif
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
-
-/*config the default parameters for adc power key*/
-#if 0
-#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
-#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
-#endif
-#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
-#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
-
-/* args/envs */
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "firstboot=1\0"\
- "upgrade_step=0\0"\
- "jtag=disable\0"\
- "loadaddr=1080000\0"\
- "panel_type=lcd_1\0" \
- "outputmode=1080p60hz\0" \
- "hdmimode=1080p60hz\0" \
- "cvbsmode=576cvbs\0" \
- "display_width=1920\0" \
- "display_height=1080\0" \
- "display_bpp=16\0" \
- "display_color_index=16\0" \
- "display_layer=osd0\0" \
- "display_color_fg=0xffff\0" \
- "display_color_bg=0\0" \
- "dtb_mem_addr=0x1000000\0" \
- "fb_addr=0x3d800000\0" \
- "fb_width=1920\0" \
- "fb_height=1080\0" \
- "frac_rate_policy=1\0" \
- "usb_burning=update 1000\0" \
- "fdt_high=0x20000000\0"\
- "try_auto_burn=update 700 750;\0"\
- "sdcburncfg=aml_sdc_burn.ini\0"\
- "sdc_burning=sdc_burn ${sdcburncfg}\0"\
- "wipe_data=successful\0"\
- "wipe_cache=successful\0"\
- "EnableSelinux=enforcing\0" \
- "recovery_part=recovery\0"\
- "recovery_offset=0\0"\
- "cvbs_drv=0\0"\
- "osd_reverse=0\0"\
- "video_reverse=0\0"\
- "lock=10001000\0"\
- "active_slot=normal\0"\
- "boot_part=boot\0"\
- "reboot_mode_android=""normal""\0"\
- "Irq_check_en=0\0"\
- "fs_type=""rootfstype=ramfs""\0"\
- "initargs="\
- "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
- "\0"\
- "upgrade_check="\
- "echo upgrade_step=${upgrade_step}; "\
- "if itest ${upgrade_step} == 3; then "\
- "run init_display; run storeargs; run update;"\
- "else fi;"\
- "\0"\
- "storeargs="\
- "setenv bootargs ${initargs} ${fs_type} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
- "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
- "run cmdline_keys;"\
- "\0"\
- "switch_bootmode="\
- "get_rebootmode;"\
- "if test ${reboot_mode} = factory_reset; then "\
- "setenv reboot_mode_android ""normal"";"\
- "run storeargs;"\
- "run recovery_from_flash;"\
- "else if test ${reboot_mode} = update; then "\
- "setenv reboot_mode_android ""normal"";"\
- "run storeargs;"\
- "run update;"\
- "else if test ${reboot_mode} = quiescent; then "\
- "setenv reboot_mode_android ""quiescent"";"\
- "run storeargs;"\
- "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
- "else if test ${reboot_mode} = recovery_quiescent; then "\
- "setenv reboot_mode_android ""quiescent"";"\
- "run storeargs;"\
- "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
- "run recovery_from_flash;"\
- "else if test ${reboot_mode} = cold_boot; then "\
- "setenv reboot_mode_android ""normal"";"\
- "run storeargs;"\
- "else if test ${reboot_mode} = fastboot; then "\
- "setenv reboot_mode_android ""normal"";"\
- "run storeargs;"\
- "fastboot;"\
- "fi;fi;fi;fi;fi;fi;"\
- "\0" \
- "storeboot="\
- "boot_cooling;"\
- "get_system_as_root_mode;"\
- "echo system_mode: ${system_mode};"\
- "if test ${system_mode} = 1; then "\
- "setenv fs_type ""ro rootwait skip_initramfs"";"\
- "run storeargs;"\
- "fi;"\
- "get_valid_slot;"\
- "get_avb_mode;"\
- "echo active_slot: ${active_slot};"\
- "if test ${active_slot} != normal; then "\
- "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
- "fi;"\
- "if test ${avb2} = 0; then "\
- "if test ${active_slot} = _a; then "\
- "setenv bootargs ${bootargs} root=/dev/mmcblk0p23;"\
- "else if test ${active_slot} = _b; then "\
- "setenv bootargs ${bootargs} root=/dev/mmcblk0p24;"\
- "fi;fi;"\
- "fi;"\
- "imgread dtb _aml_dtb 0x01000000; fdt addr 0x01000000;"\
- "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
- "run update;"\
- "\0"\
- "factory_reset_poweroff_protect="\
- "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
- "if test ${wipe_data} = failed; then "\
- "run init_display; run storeargs;"\
- "if mmcinfo; then "\
- "run recovery_from_sdcard;"\
- "fi;"\
- "if usb start 0; then "\
- "run recovery_from_udisk;"\
- "fi;"\
- "run recovery_from_flash;"\
- "fi; "\
- "if test ${wipe_cache} = failed; then "\
- "run init_display; run storeargs;"\
- "if mmcinfo; then "\
- "run recovery_from_sdcard;"\
- "fi;"\
- "if usb start 0; then "\
- "run recovery_from_udisk;"\
- "fi;"\
- "run recovery_from_flash;"\
- "fi; \0" \
- "update="\
- /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
- "run usb_burning; "\
- "run sdc_burning; "\
- "if mmcinfo; then "\
- "run recovery_from_sdcard;"\
- "fi;"\
- "if usb start 0; then "\
- "run recovery_from_udisk;"\
- "fi;"\
- "run recovery_from_flash;"\
- "\0"\
- "recovery_from_sdcard="\
- "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
- "if fatload mmc 0 ${loadaddr} recovery.img; then "\
- "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
- "wipeisb; "\
- "bootm ${loadaddr};fi;"\
- "\0"\
- "recovery_from_udisk="\
- "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
- "if fatload usb 0 ${loadaddr} recovery.img; then "\
- "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
- "wipeisb; "\
- "bootm ${loadaddr};fi;"\
- "\0"\
- "recovery_from_flash="\
- "get_valid_slot;"\
- "echo active_slot: ${active_slot};"\
- "if test ${active_slot} = normal; then "\
- "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
- "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
- "else "\
- "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
- "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
- "fi;"\
- "\0"\
- "init_display="\
- "get_rebootmode;"\
- "echo reboot_mode:::: ${reboot_mode};"\
- "if test ${reboot_mode} = quiescent; then "\
- "setenv reboot_mode_android ""quiescent"";"\
- "run storeargs;"\
- "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
- "osd open;osd clear;"\
- "else if test ${reboot_mode} = recovery_quiescent; then "\
- "setenv reboot_mode_android ""quiescent"";"\
- "run storeargs;"\
- "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
- "osd open;osd clear;"\
- "else "\
- "setenv reboot_mode_android ""normal"";"\
- "run storeargs;"\
- "fi;fi;"\
- "\0"\
- "cmdline_keys="\
- "if keyman init 0x1234; then "\
- "if keyman read usid ${loadaddr} str; then "\
- "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
- "setenv serial ${usid};"\
- "else "\
- "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
- "setenv serial 1234567890;"\
- "fi;"\
- "if keyman read mac ${loadaddr} str; then "\
- "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
- "fi;"\
- "if keyman read deviceid ${loadaddr} str; then "\
- "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
- "fi;"\
- "if keyman read region_code ${loadaddr} str; then "\
- "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
- "else "\
- "setenv bootargs ${bootargs} androidboot.wificountrycode=US;"\
- "fi;"\
- "fi;"\
- "\0"\
- "bcb_cmd="\
- "get_avb_mode;"\
- "get_valid_slot;"\
- "\0"\
- "upgrade_key="\
- "if gpio input GPIOAO_3; then "\
- "echo detect upgrade key; run update;"\
- "fi;"\
- "\0"\
- "irremote_update="\
- "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
- "echo read irkey ok!; " \
- "if itest ${irkey_value} == 0xe31cfb04; then " \
- "run update;" \
- "else if itest ${irkey_value} == 0xb748fb04; then " \
- "run update;\n" \
- "fi;fi;" \
- "fi;\0" \
-
-
-#define CONFIG_PREBOOT \
- "run bcb_cmd; "\
- "run factory_reset_poweroff_protect;"\
- "run upgrade_check;"\
- "run init_display;"\
- "run storeargs;"\
- "forceupdate;" \
- "bcb uboot-command;"\
- "run switch_bootmode;"
-
-#define CONFIG_BOOTCOMMAND "run storeboot"
-
-/* #define CONFIG_ENV_IS_NOWHERE 1 */
-#define CONFIG_ENV_SIZE (64*1024)
-#define CONFIG_FIT 1
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_ANDROID_BOOT_IMAGE 1
-#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
-
-/* cpu */
-/* #define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24 */
-
-/* ATTENTION */
-/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
-
-//#define CONFIG_NR_DRAM_BANKS 1
-/* ddr functions */
-#if 0
-#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
-#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
-#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
-#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
-#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
-#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
-#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
-#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
-#endif
-#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
-#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
-#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
-#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
-#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
-#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
-
-/* storage: emmc/nand/sd */
-#if 0
-#define CONFIG_STORE_COMPATIBLE 1
-#endif
-#define CONFIG_ENV_OVERWRITE
-/* #define CONFIG_CMD_SAVEENV */
-/* fixme, need fix*/
-
-#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
-#error env in amlnand/mmc already be compatible;
-#endif
-
-/*
-* storage
-* |---------|---------|
-* | |
-* emmc<--Compatible-->nand
-* |-------|-------|
-* | |
-* MTD<-Exclusive->NFTL
-*/
-/* axg only support slc nand */
-/* swither for mtd nand which is for slc only. */
-
-
-#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
-#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
-#endif
-
-#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC)
-#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
-#endif
-
-#if 0
-#ifdef CONFIG_MESON_NFC
-
-/* bootlaoder is construct by bl2 and fip
- * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
- * will not be stored continuously, and nand layout
- * would be bl2|rsv|fip|normal, but not
- * bl2|fip|rsv|noraml anymore
- */
-#if 0
-#define CONFIG_DISCRETE_BOOTLOADER
-#endif
-
-#ifdef CONFIG_DISCRETE_BOOTLOADER
-#if 0
-#define CONFIG_TPL_SIZE_PER_COPY 0x200000
-#define CONFIG_TPL_COPY_NUM 4
-#define CONFIG_TPL_PART_NAME "tpl"
-/* for bl2, restricted by romboot */
-/* SKT 1024 pages only support 4 block, so 4 copies */
-#define CONFIG_BL2_COPY_NUM 4
-#endif
-#endif /* CONFIG_DISCRETE_BOOTLOADER */
-
-/* #define CONFIG_CMD_NAND 1 */
-#define CONFIG_MTD_DEVICE y
-/* mtd parts of ourown.*/
-#define CONFIG_AML_MTDPART 1
-/* mtd parts by env default way.*/
-/*
-#define MTDIDS_NAME_STR "aml_nand.0"
-#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
-#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
- "3M@8192K(logo)," \
- "10M(recovery)," \
- "8M(kernel)," \
- "40M(rootfs)," \
- "-(data)"
-*/
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_MTD_UBI_WL_THRESHOLD 4096
-#define CONFIG_MTD_UBI_BEB_LIMIT 20
-#define CONFIG_RBTREE
-#define CONFIG_CMD_NAND_TORTURE 1
-#define CONFIG_CMD_MTDPARTS 1
-#define CONFIG_MTD_PARTITIONS 1
-#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-#endif
-
-/* #define CONFIG_AML_SD_EMMC 1 */
-#ifdef CONFIG_AML_SD_EMMC
- #define CONFIG_GENERIC_MMC 1
- #define CONFIG_CMD_MMC 1
- #define CONFIG_CMD_GPT 1
- #define CONFIG_SYS_MMC_ENV_DEV 1
- #define CONFIG_EMMC_DDR52_EN 0
- #define CONFIG_EMMC_DDR52_CLK 35000000
-#endif
-#define CONFIG_PARTITIONS 1
-#if 0
-#define CONFIG_SYS_NO_FLASH 1
-#endif
-
-#if defined CONFIG_MESON_NFC || defined CONFIG_SPI_NAND
- #define CONFIG_CMD_NAND 1
- #define CONFIG_MTD_DEVICE y
- /* #define CONFIG_RBTREE */
- #define CONFIG_CMD_NAND_TORTURE 1
- #define CONFIG_CMD_MTDPARTS 1
- #define CONFIG_MTD_PARTITIONS 1
- #define CONFIG_SYS_MAX_NAND_DEVICE 2
- #define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-
-/* vpu */
-#define AML_VPU_CLK_LEVEL_DFT 7
-
-/* osd */
-#define OSD_SCALE_ENABLE
-#define AML_OSD_HIGH_VERSION
-
-#if 0
-#define CONFIG_AML_CANVAS 1
-#define CONFIG_AML_OSD 1
-#define CONFIG_OSD_SCALE_ENABLE 1
-/* #define CONFIG_CMD_BMP 1 */
-#endif
-
-/* USB
- * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
- * Enable CONFIG_MUSB_UDD for Device functionalities.
- */
-/* #define CONFIG_MUSB_UDC 1 */
-/* #define CONFIG_CMD_USB 1 */
-
-#define USB_PHY2_PLL_PARAMETER_1 0x09400414
-#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
-#define USB_PHY2_PLL_PARAMETER_3 0xAC5F49E5
-
-#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
-#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
-#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
-#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
-#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
-
-#define AML_TXLX_USB 1
-
-/* UBOOT fastboot config */
-#if 0
-#define CONFIG_CMD_FASTBOOT 1
-#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
-#define CONFIG_FASTBOOT_FLASH 1
-#define CONFIG_USB_GADGET 1
-#define CONFIG_USBDOWNLOAD_GADGET 1
-#define CONFIG_SYS_CACHELINE_SIZE 64
-#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
-#define CONFIG_DEVICE_PRODUCT "u200"
-#endif
-
-/* UBOOT Facotry usb/sdcard burning config */
-/* #define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning */
-#if 0
-#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
-#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isnt power-key for factory sdcard burning
-#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
-#endif
-
-#if 0
-#define CONFIG_AML_SECURITY_KEY 1
-#define CONFIG_UNIFY_KEY_MANAGE 1
-#endif
-
-/* net */
-/* #define CONFIG_CMD_NET 1 */
-#define CONFIG_ETH_DESIGNWARE
-#if defined(CONFIG_CMD_NET)
- #define CONFIG_DESIGNWARE_ETH 1
- #define CONFIG_PHYLIB 1
- #define CONFIG_NET_MULTI 1
- #define CONFIG_CMD_PING 1
- #define CONFIG_CMD_DHCP 1
- #define CONFIG_CMD_RARP 1
- #define CONFIG_HOSTNAME "arm_gxbb"
-#if 0
- #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
-#endif
- #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
- #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
- #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
- #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
- #define CONFIG_NETMASK 255.255.255.0
-#endif /* (CONFIG_CMD_NET) */
-
-/* other devices */
-#if 0
-#define CONFIG_EFUSE 1
-#endif
-#define CONFIG_SHA1 1
-#define CONFIG_MD5 1
-
-/* commands */
-#if 0
-#define CONFIG_CMD_CACHE 1
-#define CONFIG_CMD_BOOTI 1
-#define CONFIG_CMD_EFUSE 1
-#define CONFIG_CMD_MEMORY 1
-#define CONFIG_CMD_FAT 1
-#define CONFIG_CMD_GPIO 1
-#define CONFIG_CMD_REBOOT 1
-#define CONFIG_CMD_ECHO 1
-#define CONFIG_CMD_JTAG 1
-#define CONFIG_CMD_AUTOSCRIPT 1
-#define CONFIG_CMD_MISC 1
-#endif
-/* #define CONFIG_CMD_FDT 1 */
-
-/*file system*/
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_EFI_PARTITION 1
-#if 0
-#define CONFIG_AML_PARTITION 1
-#endif
-/* #define CONFIG_MMC 1 */
-#define CONFIG_FS_FAT 1
-#define CONFIG_FS_EXT4 1
-#define CONFIG_LZO 1
-
-#if 0
-#define CONFIG_MDUMP_COMPRESS 1
-#endif
-
-/* Cache Definitions */
-/* #define CONFIG_SYS_DCACHE_OFF */
-/* #define CONFIG_SYS_ICACHE_OFF */
-
-/* other functions */
-#if 0
-#define CONFIG_NEED_BL301 1
-#define CONFIG_NEED_BL32 1
-#define CONFIG_CMD_RSVMEM 1
-#define CONFIG_FIP_IMG_SUPPORT 1
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_CMD_MISC 1
-#define CONFIG_CMD_ITEST 1
-#define CONFIG_CMD_CPU_TEMP 1
-#define CONFIG_CMD_LOADB 1
-#endif
-#define CONFIG_FIP_IMG_SUPPORT 1
-#define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 /* hide 128MB for kernel reserve */
-#define CONFIG_LIBAVB 1
-
-#define CONFIG_CPU_ARMV8
-
-#define CONFIG_MULTI_DTB 1
-
-/* support secure boot */
-#define CONFIG_AML_SECURE_UBOOT 1
-
-#if defined(CONFIG_AML_SECURE_UBOOT)
-
-/* for SRAM size limitation just disable NAND
- as the socket board default has no NAND */
-/* #undef CONFIG_AML_NAND */
-
-/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
-#define CONFIG_AML_CRYPTO_UBOOT 1
-
-/* unify build for generate encrypted kernel image
- SRC : "board/amlogic/(board)/boot.img"
- DST : "fip/boot.img.encrypt" */
-/* #define CONFIG_AML_CRYPTO_IMG 1 */
-
-#endif /* CONFIG_AML_SECURE_UBOOT */
-
-#if 0
-#define CONFIG_SECURE_STORAGE 1
-#endif
-
-/* build with uboot auto test */
-/* #define CONFIG_AML_UBOOT_AUTO_TEST 1 */
-
-/* board customer ID */
-/* #define CONFIG_CUSTOMER_ID (0x6472616F624C4D41) */
-
-#if 0
-#if defined(CONFIG_CUSTOMER_ID)
- #undef CONFIG_AML_CUSTOMER_ID
- #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
-#endif
-#endif
-
-/* Choose One of Ethernet Type */
-#undef CONFIG_ETHERNET_NONE
-#define ETHERNET_INTERNAL_PHY
-#undef ETHERNET_EXTERNAL_PHY
-
-#if 0
-#define CONFIG_CMD_AML_MTEST 1
-#endif
-#if defined(CONFIG_CMD_AML_MTEST)
-#if !defined(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_CMD_AML_MTEST depends on CONFIG_SYS_MEM_TOP_HIDE;
-#endif
-#if !(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_SYS_MEM_TOP_HIDE should not be zero;
-#endif
-#endif
-
-#endif
-
diff --git a/include/configs/g12b_newman_bx.h b/include/configs/g12b_newman_bx.h
deleted file mode 100755
index 479e5b0..0000000
--- a/include/configs/g12b_newman_bx.h
+++ /dev/null
@@ -1,568 +0,0 @@
-
-/*
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#ifndef __G12B_NEWMAN_BX_H__
-#define __G12B_NEWMAN_BX_H__
-
-#include <asm/arch/cpu.h>
-
-//#define CONFIG_SYS_GENERIC_BOARD 1
-/*
-#ifndef CONFIG_AML_MESON
-#warning "include warning"
-#endif
-*/
-
-/*
- * platform power init config
- */
-
-#define AML_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
-#define AML_VDDEE_INIT_VOLTAGE 840 // VDDEE power up voltage
-#define AML_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
-
-/* SMP Definitinos */
-#define CPU_RELEASE_ADDR secondary_boot_func
-
-/* Bootloader Control Block function
- That is used for recovery and the bootloader to talk to each other
- */
-
-/* Serial config */
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_BAUDRATE 115200
-/* #define CONFIG_AML_MESON_SERIAL 1 */
-
-/* Enable ir remote wake up for bl30 */
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
-
-/*config the default parameters for adc power key*/
-#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
-#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
-
-/* args/envs */
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=1080000\0" \
- "outputmode=panel\0" \
- "hdmimode=1080p60hz\0" \
- "display_width=1920\0" \
- "display_height=1080\0" \
- "display_bpp=16\0" \
- "display_color_index=16\0" \
- "display_layer=osd0\0" \
- "display_color_fg=0xffff\0" \
- "display_color_bg=0\0" \
- "dtb_mem_addr=0x1000000\0" \
- "fb_addr=0x76800000\0" \
- "fb_width=800\0" \
- "fb_height=1280\0" \
- "usb_burning=update 1000\0" \
- "fdt_high=0x20000000\0" \
- "try_auto_burn=update 700 750;\0" \
- "sdcburncfg=aml_sdc_burn.ini\0" \
- "sdc_burning=sdc_burn ${sdcburncfg}\0" \
- "wipe_data=successful\0" \
- "wipe_cache=successful\0" \
- "EnableSelinux=enforcing\0" \
- "recovery_part=recovery\0" \
- "recovery_offset=0\0" \
- "active_slot=_a\0" \
- "boot_part=boot\0" \
- "ext4_system=1:5\0" \
- "storeargs=" \
- "get_cpu_rev;" \
- "setenv bootargs " \
- "gpt " \
- "logo=${display_layer},loaded,${fb_addr} " \
- "vout=${outputmode},enable " \
- "panel_type=${panel_type} " \
- "androidboot.selinux=${EnableSelinux} " \
- "test_mode=${test_mode} " \
- "androidboot.hardware="__stringify(BOARD_NAME)" " \
- "hw_id=${hw_id} " \
- "cpu_rev=${cpu_rev} " \
- "androidboot.reboot_mode=${reboot_mode} " \
- "androidboot.slot_suffix=${active_slot};" \
- "\0" \
- "switch_bootmode="\
- "get_rebootmode;"\
- "echo reboot_mode:${reboot_mode};"\
- "if test ${reboot_mode} = factory_reset; then "\
- "run recovery_from_flash;"\
- "else if test ${reboot_mode} = update; then "\
- "run update;"\
- "else if test ${reboot_mode} = cold_boot; then "\
- "echo cold_boot; " \
- "else if test ${reboot_mode} = fastboot; then "\
- "fastboot;" \
- "else if test ${reboot_mode} = factory_boot; then " \
- "ddr_auto_fast_boot_check 6 ;"\
- "if imgread kernel fct ${loadaddr}; then " \
- "bootm ${loadaddr};" \
- "fi;" \
- "fi;fi;fi;fi;fi;" \
- "\0" \
- "storeboot="\
- "ddr_auto_fast_boot_check 6 ;"\
- "if imgread kernel ${boot_part} ${loadaddr}; then " \
- "bootm ${loadaddr};" \
- "fi;" \
- "run update;"\
- "\0"\
- "factory_reset_poweroff_protect="\
- "echo wipe_data=${wipe_data};" \
- "echo wipe_cache=${wipe_cache};" \
- "if test ${wipe_data} = failed; then "\
- "run init_display;" \
- "run get_hw_id;" \
- "run storeargs;"\
- "if usb start 0; then "\
- "run recovery_from_udisk;"\
- "fi;"\
- "run recovery_from_flash;"\
- "fi; "\
- "if test ${wipe_cache} = failed; then "\
- "run init_display;" \
- "run get_hw_id;" \
- "run storeargs;"\
- "if mmcinfo; then "\
- "run recovery_from_sdcard;"\
- "fi;"\
- "if usb start 0; then "\
- "run recovery_from_udisk;"\
- "fi;"\
- "run recovery_from_flash;"\
- "fi;" \
- "\0" \
- "update="\
- /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
- "run usb_burning; "\
- "run recovery_from_flash;"\
- "\0"\
- "recovery_from_sdcard="\
- "if fatload mmc 0 ${loadaddr} aml_autoscript; then " \
- "autoscr ${loadaddr}; " \
- "fi;" \
- "if fatload mmc 0 ${loadaddr} recovery.img; then "\
- "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then " \
- "echo sd dtb.img loaded; " \
- "fi;" \
- "wipeisb;" \
- "bootm ${loadaddr};" \
- "fi;" \
- "\0"\
- "recovery_from_udisk="\
- "while true ;do " \
- "usb reset; " \
- "if fatload usb 0 ${loadaddr} recovery.img; then "\
- "bootm ${loadaddr};" \
- "fi;" \
- "done;" \
- "\0"\
- "recovery_from_flash="\
- "setenv bootargs " \
- "${bootargs} " \
- "aml_dt=${aml_dt} " \
- "recovery_part=${recovery_part} " \
- "recovery_offset=${recovery_offset};" \
- "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then " \
- "wipeisb;" \
- "bootm ${loadaddr};" \
- "fi" \
- "\0"\
- "reset_ddic=" \
- "gpio clear GPIOH_6" \
- "\0" \
- "detect_panel=" \
- "get_ddictype;" \
- "if gpio input GPIOH_0; then " \
- "if test $ddic_type = FITI; then " \
- "env set panel_type boe_fiti_10;" \
- "else " \
- "env set panel_type boe_nvtk_10;" \
- "fi;" \
- "else " \
- "if test $ddic_type = FITI; then " \
- "env set panel_type inx_fiti_10;" \
- "else " \
- "env set panel_type inx_nvtk_10;" \
- "fi;" \
- "fi;" \
- "\0" \
- "set_gamma="\
- "if ext4load mmc ${ext4_system} 0x8000000 gamma_calibration.txt; then " \
- "configure_gamma 0x8000000;" \
- "else " \
- "configure_gamma;" \
- "fi;" \
- "\0" \
- "start_backlight=" \
- "if ext4load mmc ${ext4_system} 0x8000000 bl_calibration.txt; then " \
- "configure_backlight 0x8000000;" \
- "else " \
- "configure_backlight;" \
- "fi;" \
- "\0" \
- "init_display="\
- "run reset_ddic;" \
- "run detect_panel;" \
- "osd open;" \
- "osd clear;" \
- "osd setcolor 0xffffffff;" \
- "get_rebootmode;"\
- /* logo must not fail */ \
- "ext4load mmc ${ext4_system} 0x8000000 logo.bmp;" \
- "bmp display 0x8000000;" \
- /* do this sequentially so we could reuse the address and do
- * not need to know the size of the images */ \
- "if ext4load mmc ${ext4_system} 0x8000000 corner_BL.bmp; then " \
- "bmp display 0x8000000 0 1264;" \
- "fi;" \
- "if ext4load mmc ${ext4_system} 0x8000000 corner_BR.bmp; then " \
- "bmp display 0x8000000 784 1264;" \
- "fi;" \
- "if ext4load mmc ${ext4_system} 0x8000000 corner_TL.bmp; then " \
- "bmp display 0x8000000 0 0;" \
- "fi;" \
- "if ext4load mmc ${ext4_system} 0x8000000 corner_TR.bmp; then " \
- "bmp display 0x8000000 784 0;" \
- "fi;" \
- "bmp scale;" \
- "vout output ${outputmode};" \
- "run set_gamma;" \
- "run start_backlight;" \
- "\0" \
- "get_hw_id=" \
- "get_newman_hw_id;" \
- "\0" \
- "cmdline_keys=" \
- "if keyman init 0x1234; then " \
- "if keyman read usid ${loadaddr} str; then " \
- "env set bootargs " \
- "${bootargs} " \
- "androidboot.serialno=${usid};" \
- "env set serial ${usid};" \
- "else " \
- "env set bootargs " \
- "${bootargs} " \
- "androidboot.serialno=1234567890;" \
- "env set serial 1234567890;" \
- "fi;" \
- "if keyman read mac ${loadaddr} str; then " \
- "env set bootargs " \
- "${bootargs} " \
- "mac=${mac} " \
- "androidboot.mac=${mac};" \
- "fi;" \
- "if keyman read deviceid ${loadaddr} str; then " \
- "env set bootargs " \
- "${bootargs} " \
- "androidboot.deviceid=${deviceid};" \
- "fi;" \
- "fi;" \
- "\0" \
- "bcb_cmd=" \
- "get_valid_slot;" \
- "\0" \
- "upgrade_key=" \
- "if gpio input GPIOZ_5; then " \
- "echo detect VOL_DN pressed;" \
- "if gpio input GPIOZ_4; then " \
- "echo VOL_UP pressed;" \
- "env set boot_external_image 1;" \
- "run recovery_from_udisk;" \
- "else " \
- "echo VOL_UP not pressed;" \
- "setenv boot_external_image 0;" \
- "run recovery_from_flash;" \
- "fi;" \
- "else " \
- "echo upgrade key not pressed;" \
- "env set boot_external_image 0;" \
- "fi;" \
- "\0" \
- "test_mode_check=" \
- "env set test_mode false;" \
- "if gpio input GPIOH_3; then " \
- "echo MUTE not engaged;" \
- "else " \
- "echo MUTE engaged;" \
- "if gpio input GPIOZ_4; then " \
- "echo VOL_UP pressed;" \
- "if gpio input GPIOZ_5; then " \
- "echo VOL_DN pressed;" \
- "else " \
- "echo VOL_DN not pressed;" \
- "echo boot into TEST MODE;" \
- "env set test_mode true;" \
- "fi;" \
- "else " \
- "echo VOL_UP not pressed;" \
- "fi;" \
- "fi;" \
- "\0" \
-
-
-#define CONFIG_PREBOOT \
- "run factory_reset_poweroff_protect;"\
- "run init_display;"\
- "run get_hw_id;" \
- "run test_mode_check;" \
- "run storeargs;" \
- "run upgrade_key;" \
- "run switch_bootmode;"
-
-
-/* #define CONFIG_ENV_IS_NOWHERE 1 */
-#define CONFIG_ENV_SIZE (64*1024)
-#define CONFIG_FIT 1
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_ANDROID_BOOT_IMAGE 1
-#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
-
-/* cpu */
-/* #define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24 */
-
-/* ATTENTION */
-/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
-
-//#define CONFIG_NR_DRAM_BANKS 1
-/* ddr functions, if want ddr-fast-boot,need enable below 2 configs */
-#define CONFIG_CMD_DDR_D2PLL 1 //0:disable, 1:enable. d2pll cmd
-#define CONFIG_CMD_DDR_TEST 1 //0:disable, 1:enable. ddrtest cmd
-#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
-#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
-#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
-#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
-#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
-#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
-
-/* storage: emmc/nand/sd */
-#define CONFIG_ENV_OVERWRITE
-/* #define CONFIG_CMD_SAVEENV */
-/* fixme, need fix*/
-
-#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
-#error env in amlnand/mmc already be compatible;
-#endif
-
-/*
-* storage
-* |---------|---------|
-* | |
-* emmc<--Compatible-->nand
-* |-------|-------|
-* | |
-* MTD<-Exclusive->NFTL
-*/
-/* axg only support slc nand */
-/* swither for mtd nand which is for slc only. */
-/* support for mtd */
-
-/* #define CONFIG_AML_MTD 1 */
-
-/* support for nftl */
-/*#define CONFIG_AML_NAND 1*/
-
-#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
-#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
-#endif
-
-#ifdef CONFIG_AML_MTD
-
-/* bootlaoder is construct by bl2 and fip
- * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
- * will not be stored continuously, and nand layout
- * would be bl2|rsv|fip|normal, but not
- * bl2|fip|rsv|noraml anymore
- */
-
-/* #define CONFIG_CMD_NAND 1 */
-#define CONFIG_MTD_DEVICE y
-/* mtd parts of ourown.*/
-#define CONFIG_AML_MTDPART 1
-/* mtd parts by env default way.*/
-/*
-#define MTDIDS_NAME_STR "aml_nand.0"
-#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
-#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
- "3M@8192K(logo)," \
- "10M(recovery)," \
- "8M(kernel)," \
- "40M(rootfs)," \
- "-(data)"
-*/
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_MTD_UBI_WL_THRESHOLD 4096
-#define CONFIG_MTD_UBI_BEB_LIMIT 20
-#define CONFIG_RBTREE
-#define CONFIG_CMD_NAND_TORTURE 1
-#define CONFIG_CMD_MTDPARTS 1
-#define CONFIG_MTD_PARTITIONS 1
-#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-/* endof CONFIG_AML_MTD */
-/* #define CONFIG_AML_SD_EMMC 1 */
-#ifdef CONFIG_AML_SD_EMMC
- #define CONFIG_GENERIC_MMC 1
- #define CONFIG_CMD_MMC 1
- #define CONFIG_CMD_GPT 1
- #define CONFIG_SYS_MMC_ENV_DEV 1
- #define CONFIG_EMMC_DDR52_EN 0
- #define CONFIG_EMMC_DDR52_CLK 35000000
-#endif
-#define CONFIG_PARTITIONS 1
-
-#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
- #define CONFIG_CMD_NAND 1
- #define CONFIG_MTD_DEVICE y
- /* #define CONFIG_RBTREE */
- #define CONFIG_CMD_NAND_TORTURE 1
- #define CONFIG_CMD_MTDPARTS 1
- #define CONFIG_MTD_PARTITIONS 1
- #define CONFIG_SYS_MAX_NAND_DEVICE 2
- #define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-
-/* vpu */
-#define AML_VPU_CLK_LEVEL_DFT 7
-
-/* osd */
-#define OSD_SCALE_ENABLE
-#define AML_OSD_HIGH_VERSION
-
-/* USB
- * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
- * Enable CONFIG_MUSB_UDD for Device functionalities.
- */
-/* #define CONFIG_MUSB_UDC 1 */
-/* #define CONFIG_CMD_USB 1 */
-
-#define AML_TXLX_USB 1
-#define USB_PHY2_PLL_PARAMETER_1 0x09400414
-#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
-#define USB_PHY2_PLL_PARAMETER_3 0xAC5F69E5
-#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
-#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
-#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
-#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
-#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
-
-/* UBOOT Facotry usb/sdcard burning config */
-#ifndef AML_DISABLE_UPDATE_MODE
-#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning */
-#define CONFIG_USB_BURNING_TOOL 1
-#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
-#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
-#endif
-
-/* net */
-#if defined(CONFIG_CMD_NET)
- #define CONFIG_DESIGNWARE_ETH 1
- #define CONFIG_PHYLIB 1
- #define CONFIG_NET_MULTI 1
- #define CONFIG_CMD_PING 1
- #define CONFIG_CMD_DHCP 1
- #define CONFIG_CMD_RARP 1
- #define CONFIG_HOSTNAME "arm_gxbb"
- #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
- #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
- #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
- #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
- #define CONFIG_NETMASK 255.255.255.0
-#endif /* (CONFIG_CMD_NET) */
-
-/* other devices */
-#define CONFIG_SHA1 1
-#define CONFIG_MD5 1
-
-/* commands */
-/* #define CONFIG_CMD_FDT 1 */
-
-/*file system*/
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_EFI_PARTITION 1
-
-/* #define CONFIG_MMC 1 */
-#define CONFIG_LZO 1
-
-/* Cache Definitions */
-/* #define CONFIG_SYS_DCACHE_OFF */
-/* #define CONFIG_SYS_ICACHE_OFF */
-
-/* other functions */
-#define CONFIG_FIP_IMG_SUPPORT 1
-/* #define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 */ /* hide 128MB for kernel reserve */
-
-#define CONFIG_CPU_ARMV8
-
-/* #define CONFIG_MULTI_DTB 1 */
-
-/* support secure boot */
-#define CONFIG_AML_SECURE_UBOOT 1
-
-#if defined(CONFIG_AML_SECURE_UBOOT)
-
-/* for SRAM size limitation just disable NAND
- as the socket board default has no NAND */
-/* #undef CONFIG_AML_NAND */
-
-/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
-#define CONFIG_AML_CRYPTO_UBOOT 1
-
-/* unify build for generate encrypted kernel image
- SRC : "board/amlogic/(board)/boot.img"
- DST : "fip/boot.img.encrypt" */
-/* #define CONFIG_AML_CRYPTO_IMG 1 */
-
-#endif /* CONFIG_AML_SECURE_UBOOT */
-
-/* build with uboot auto test */
-/* #define CONFIG_AML_UBOOT_AUTO_TEST 1 */
-
-/* board customer ID */
-/* #define CONFIG_CUSTOMER_ID (0x6472616F624C4D41) */
-
-/* Choose One of Ethernet Type */
-#undef CONFIG_ETHERNET_NONE
-#define ETHERNET_INTERNAL_PHY
-#undef ETHERNET_EXTERNAL_PHY
-
-#if defined(CONFIG_CMD_AML_MTEST)
-#if !defined(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_CMD_AML_MTEST depends on CONFIG_SYS_MEM_TOP_HIDE;
-#endif
-#if !(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_SYS_MEM_TOP_HIDE should not be zero;
-#endif
-#endif
-
-#endif
diff --git a/include/configs/g12b_newman_px.h b/include/configs/g12b_newman_px.h
deleted file mode 100755
index 3597e4b..0000000
--- a/include/configs/g12b_newman_px.h
+++ /dev/null
@@ -1,553 +0,0 @@
-
-/*
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#ifndef __G12B_NEWMAN_PX_H__
-#define __G12B_NEWMAN_PX_H__
-
-#include <asm/arch/cpu.h>
-
-//#define CONFIG_SYS_GENERIC_BOARD 1
-/*
-#ifndef CONFIG_AML_MESON
-#warning "include warning"
-#endif
-*/
-
-/*
- * platform power init config
- */
-#define AML_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
-#define AML_VDDEE_INIT_VOLTAGE 840 // VDDEE power up voltage
-#define AML_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
-
-/* SMP Definitinos */
-#define CPU_RELEASE_ADDR secondary_boot_func
-
-/* Bootloader Control Block function
- That is used for recovery and the bootloader to talk to each other
- */
-
-/* Serial config */
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_BAUDRATE 115200
-/* #define CONFIG_AML_MESON_SERIAL 1 */
-
-/* Enable ir remote wake up for bl30 */
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
-
-/*config the default parameters for adc power key*/
-#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
-#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
-
-/* args/envs */
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=1080000\0" \
- "outputmode=panel\0" \
- "hdmimode=1080p60hz\0" \
- "display_width=1920\0" \
- "display_height=1080\0" \
- "display_bpp=16\0" \
- "display_color_index=16\0" \
- "display_layer=osd0\0" \
- "display_color_fg=0xffff\0" \
- "display_color_bg=0\0" \
- "dtb_mem_addr=0x1000000\0" \
- "fb_addr=0x76800000\0" \
- "fb_width=800\0" \
- "fb_height=1280\0" \
- "usb_burning=update 1000\0" \
- "fdt_high=0x20000000\0" \
- "try_auto_burn=update 700 750;\0" \
- "sdcburncfg=aml_sdc_burn.ini\0" \
- "sdc_burning=sdc_burn ${sdcburncfg}\0" \
- "wipe_data=successful\0" \
- "wipe_cache=successful\0" \
- "EnableSelinux=enforcing\0" \
- "recovery_part=recovery\0" \
- "recovery_offset=0\0" \
- "active_slot=_a\0" \
- "boot_part=boot\0" \
- "ext4_system=1:5\0" \
- "storeargs=" \
- "setenv bootargs " \
- "gpt " \
- "logo=${display_layer},loaded,${fb_addr} " \
- "vout=${outputmode},enable " \
- "panel_type=${panel_type} " \
- "androidboot.selinux=${EnableSelinux} " \
- "test_mode=${test_mode} " \
- "androidboot.hardware="__stringify(BOARD_NAME)" " \
- "hw_id=${hw_id} " \
- "androidboot.reboot_mode=${reboot_mode} " \
- "androidboot.slot_suffix=${active_slot};" \
- "\0" \
- "switch_bootmode="\
- "get_rebootmode;"\
- "echo reboot_mode:${reboot_mode};"\
- "if test ${reboot_mode} = factory_reset; then "\
- "run recovery_from_flash;"\
- "else if test ${reboot_mode} = update; then "\
- "run update;"\
- "else if test ${reboot_mode} = cold_boot; then "\
- "echo cold_boot; " \
- "else if test ${reboot_mode} = fastboot; then "\
- "fastboot;" \
- "else if test ${reboot_mode} = factory_boot; then " \
- "ddr_auto_fast_boot_check 6 ;"\
- "if imgread kernel fct ${loadaddr}; then " \
- "bootm ${loadaddr};" \
- "fi;" \
- "fi;fi;fi;fi;fi;" \
- "\0" \
- "storeboot="\
- "ddr_auto_fast_boot_check 6 ;"\
- "if imgread kernel ${boot_part} ${loadaddr}; then " \
- "bootm ${loadaddr};" \
- "fi;" \
- "run update;"\
- "\0"\
- "factory_reset_poweroff_protect="\
- "echo wipe_data=${wipe_data};" \
- "echo wipe_cache=${wipe_cache};" \
- "if test ${wipe_data} = failed; then "\
- "run init_display;" \
- "run get_hw_id;" \
- "run storeargs;"\
- "if usb start 0; then "\
- "run recovery_from_udisk;"\
- "fi;"\
- "run recovery_from_flash;"\
- "fi; "\
- "if test ${wipe_cache} = failed; then "\
- "run init_display;" \
- "run get_hw_id;" \
- "run storeargs;"\
- "if mmcinfo; then "\
- "run recovery_from_sdcard;"\
- "fi;"\
- "if usb start 0; then "\
- "run recovery_from_udisk;"\
- "fi;"\
- "run recovery_from_flash;"\
- "fi;" \
- "\0" \
- "update="\
- /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
- "run usb_burning; "\
- "run recovery_from_flash;"\
- "\0"\
- "recovery_from_sdcard="\
- "if fatload mmc 0 ${loadaddr} aml_autoscript; then " \
- "autoscr ${loadaddr}; " \
- "fi;" \
- "if fatload mmc 0 ${loadaddr} recovery.img; then "\
- "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then " \
- "echo sd dtb.img loaded; " \
- "fi;" \
- "wipeisb;" \
- "bootm ${loadaddr};" \
- "fi;" \
- "\0"\
- "recovery_from_udisk="\
- "while true ;do " \
- "usb reset; " \
- "if fatload usb 0 ${loadaddr} recovery.img; then "\
- "bootm ${loadaddr};" \
- "fi;" \
- "done;" \
- "\0"\
- "recovery_from_flash="\
- "setenv bootargs " \
- "${bootargs} " \
- "aml_dt=${aml_dt} " \
- "recovery_part=${recovery_part} " \
- "recovery_offset=${recovery_offset};" \
- "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then " \
- "wipeisb;" \
- "bootm ${loadaddr};" \
- "fi" \
- "\0"\
- "reset_ddic=" \
- "gpio clear GPIOH_6" \
- "\0" \
- "detect_panel=" \
- "get_ddictype;" \
- "if gpio input GPIOH_0; then " \
- "if test $ddic_type = FITI; then " \
- "env set panel_type boe_fiti_10;" \
- "else " \
- "env set panel_type boe_nvtk_10;" \
- "fi;" \
- "else " \
- "if test $ddic_type = FITI; then " \
- "env set panel_type inx_fiti_10;" \
- "else " \
- "env set panel_type inx_nvtk_10;" \
- "fi;" \
- "fi;" \
- "\0" \
- "set_gamma="\
- "if ext4load mmc ${ext4_system} 0x8000000 gamma_calibration.txt; then " \
- "configure_gamma 0x8000000;" \
- "else " \
- "configure_gamma;" \
- "fi;" \
- "\0" \
- "start_backlight=" \
- "if ext4load mmc ${ext4_system} 0x8000000 bl_calibration.txt; then " \
- "configure_backlight 0x8000000;" \
- "else " \
- "configure_backlight;" \
- "fi;" \
- "\0" \
- "init_display="\
- "run reset_ddic;" \
- "run detect_panel;" \
- "osd open;" \
- "osd clear;" \
- "osd setcolor 0xffffffff;" \
- "get_rebootmode;"\
- /* logo must not fail */ \
- "ext4load mmc ${ext4_system} 0x8000000 logo.bmp;" \
- "bmp display 0x8000000;" \
- /* do this sequentially so we could reuse the address and do
- * not need to know the size of the images */ \
- "if ext4load mmc ${ext4_system} 0x8000000 corner_BL.bmp; then " \
- "bmp display 0x8000000 0 1264;" \
- "fi;" \
- "if ext4load mmc ${ext4_system} 0x8000000 corner_BR.bmp; then " \
- "bmp display 0x8000000 784 1264;" \
- "fi;" \
- "if ext4load mmc ${ext4_system} 0x8000000 corner_TL.bmp; then " \
- "bmp display 0x8000000 0 0;" \
- "fi;" \
- "if ext4load mmc ${ext4_system} 0x8000000 corner_TR.bmp; then " \
- "bmp display 0x8000000 784 0;" \
- "fi;" \
- "bmp scale;" \
- "vout output ${outputmode};" \
- "run set_gamma;" \
- "run start_backlight;" \
- "\0" \
- "get_hw_id=" \
- "get_newman_hw_id;" \
- "\0" \
- "cmdline_keys=" \
- "if keyman init 0x1234; then " \
- "if keyman read usid ${loadaddr} str; then " \
- "env set bootargs " \
- "${bootargs} " \
- "androidboot.serialno=${usid};" \
- "env set serial ${usid};" \
- "else " \
- "env set bootargs " \
- "${bootargs} " \
- "androidboot.serialno=1234567890;" \
- "env set serial 1234567890;" \
- "fi;" \
- "if keyman read mac ${loadaddr} str; then " \
- "env set bootargs " \
- "${bootargs} " \
- "mac=${mac} " \
- "androidboot.mac=${mac};" \
- "fi;" \
- "if keyman read deviceid ${loadaddr} str; then " \
- "env set bootargs " \
- "${bootargs} " \
- "androidboot.deviceid=${deviceid};" \
- "fi;" \
- "fi;" \
- "\0" \
- "bcb_cmd=" \
- "get_valid_slot;" \
- "\0" \
- "upgrade_key=" \
- "if gpio input GPIOZ_5; then " \
- "echo detect VOL_DN pressed;" \
- "if gpio input GPIOZ_4; then " \
- "echo VOL_UP pressed;" \
- "env set boot_external_image 1;" \
- "run recovery_from_udisk;" \
- "else " \
- "echo VOL_UP not pressed;" \
- "setenv boot_external_image 0;" \
- "run recovery_from_flash;" \
- "fi;" \
- "else " \
- "echo upgrade key not pressed;" \
- "env set boot_external_image 0;" \
- "fi;" \
- "\0" \
- "test_mode_check=" \
- "env set test_mode false;" \
- "if gpio input GPIOH_3; then " \
- "echo MUTE not engaged;" \
- "else " \
- "echo MUTE engaged;" \
- "if gpio input GPIOZ_4; then " \
- "echo VOL_UP pressed;" \
- "if gpio input GPIOZ_5; then " \
- "echo VOL_DN pressed;" \
- "else " \
- "echo VOL_DN not pressed;" \
- "echo boot into TEST MODE;" \
- "env set test_mode true;" \
- "fi;" \
- "else " \
- "echo VOL_UP not pressed;" \
- "fi;" \
- "fi;" \
- "\0" \
-
-
-#define CONFIG_PREBOOT \
- "run factory_reset_poweroff_protect;"\
- "run init_display;"\
- "run get_hw_id;" \
- "run test_mode_check;" \
- "run storeargs;" \
- "run upgrade_key;" \
- "run switch_bootmode;"
-
-/* #define CONFIG_ENV_IS_NOWHERE 1 */
-#define CONFIG_ENV_SIZE (64*1024)
-#define CONFIG_FIT 1
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_ANDROID_BOOT_IMAGE 1
-#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
-
-/* cpu */
-/* #define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24 */
-
-/* ATTENTION */
-/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
-
-//#define CONFIG_NR_DRAM_BANKS 1
-/* ddr functions */
-#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
-#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
-#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
-#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
-#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
-#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
-
-/* storage: emmc/nand/sd */
-#define CONFIG_ENV_OVERWRITE
-/* #define CONFIG_CMD_SAVEENV */
-/* fixme, need fix*/
-
-#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
-#error env in amlnand/mmc already be compatible;
-#endif
-
-/*
-* storage
-* |---------|---------|
-* | |
-* emmc<--Compatible-->nand
-* |-------|-------|
-* | |
-* MTD<-Exclusive->NFTL
-*/
-/* axg only support slc nand */
-/* swither for mtd nand which is for slc only. */
-/* support for mtd */
-
-/* #define CONFIG_AML_MTD 1 */
-
-/* support for nftl */
-/*#define CONFIG_AML_NAND 1*/
-
-#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
-#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
-#endif
-
-#ifdef CONFIG_AML_MTD
-
-/* bootlaoder is construct by bl2 and fip
- * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
- * will not be stored continuously, and nand layout
- * would be bl2|rsv|fip|normal, but not
- * bl2|fip|rsv|noraml anymore
- */
-
-/* #define CONFIG_CMD_NAND 1 */
-#define CONFIG_MTD_DEVICE y
-/* mtd parts of ourown.*/
-#define CONFIG_AML_MTDPART 1
-/* mtd parts by env default way.*/
-/*
-#define MTDIDS_NAME_STR "aml_nand.0"
-#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
-#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
- "3M@8192K(logo)," \
- "10M(recovery)," \
- "8M(kernel)," \
- "40M(rootfs)," \
- "-(data)"
-*/
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_MTD_UBI_WL_THRESHOLD 4096
-#define CONFIG_MTD_UBI_BEB_LIMIT 20
-#define CONFIG_RBTREE
-#define CONFIG_CMD_NAND_TORTURE 1
-#define CONFIG_CMD_MTDPARTS 1
-#define CONFIG_MTD_PARTITIONS 1
-#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-/* endof CONFIG_AML_MTD */
-/* #define CONFIG_AML_SD_EMMC 1 */
-#ifdef CONFIG_AML_SD_EMMC
- #define CONFIG_GENERIC_MMC 1
- #define CONFIG_CMD_MMC 1
- #define CONFIG_CMD_GPT 1
- #define CONFIG_SYS_MMC_ENV_DEV 1
- #define CONFIG_EMMC_DDR52_EN 0
- #define CONFIG_EMMC_DDR52_CLK 35000000
-#endif
-#define CONFIG_PARTITIONS 1
-
-#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
- #define CONFIG_CMD_NAND 1
- #define CONFIG_MTD_DEVICE y
- /* #define CONFIG_RBTREE */
- #define CONFIG_CMD_NAND_TORTURE 1
- #define CONFIG_CMD_MTDPARTS 1
- #define CONFIG_MTD_PARTITIONS 1
- #define CONFIG_SYS_MAX_NAND_DEVICE 2
- #define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-
-/* vpu */
-#define AML_VPU_CLK_LEVEL_DFT 7
-
-/* osd */
-#define OSD_SCALE_ENABLE
-#define AML_OSD_HIGH_VERSION
-
-/* USB
- * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
- * Enable CONFIG_MUSB_UDD for Device functionalities.
- */
-/* #define CONFIG_MUSB_UDC 1 */
-/* #define CONFIG_CMD_USB 1 */
-
-#define AML_TXLX_USB 1
-#define USB_PHY2_PLL_PARAMETER_1 0x09400414
-#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
-#define USB_PHY2_PLL_PARAMETER_3 0xAC5F69E5
-#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
-#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
-#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
-#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
-#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
-
-/* net */
-/* #define CONFIG_CMD_NET 1 */
-#if defined(CONFIG_CMD_NET)
- #define CONFIG_DESIGNWARE_ETH 1
- #define CONFIG_PHYLIB 1
- #define CONFIG_NET_MULTI 1
- #define CONFIG_CMD_PING 1
- #define CONFIG_CMD_DHCP 1
- #define CONFIG_CMD_RARP 1
- #define CONFIG_HOSTNAME "arm_gxbb"
- #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
- #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
- #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
- #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
- #define CONFIG_NETMASK 255.255.255.0
-#endif /* (CONFIG_CMD_NET) */
-
-/* other devices */
-#define CONFIG_SHA1 1
-#define CONFIG_MD5 1
-
-/* commands */
-/*file system*/
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_EFI_PARTITION 1
-
-/* #define CONFIG_MMC 1 */
-#define CONFIG_LZO 1
-
-/* Cache Definitions */
-/* #define CONFIG_SYS_DCACHE_OFF */
-/* #define CONFIG_SYS_ICACHE_OFF */
-
-/* other functions */
-#define CONFIG_FIP_IMG_SUPPORT 1
-/* #define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 */ /* hide 128MB for kernel reserve */
-
-#define CONFIG_CPU_ARMV8
-
-/* #define CONFIG_MULTI_DTB 1 */
-
-/* support secure boot */
-#define CONFIG_AML_SECURE_UBOOT 1
-
-#if defined(CONFIG_AML_SECURE_UBOOT)
-
-/* for SRAM size limitation just disable NAND
- as the socket board default has no NAND */
-/* #undef CONFIG_AML_NAND */
-
-/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
-#define CONFIG_AML_CRYPTO_UBOOT 1
-
-/* unify build for generate encrypted kernel image
- SRC : "board/amlogic/(board)/boot.img"
- DST : "fip/boot.img.encrypt" */
-/* #define CONFIG_AML_CRYPTO_IMG 1 */
-
-#endif /* CONFIG_AML_SECURE_UBOOT */
-
-/* build with uboot auto test */
-/* #define CONFIG_AML_UBOOT_AUTO_TEST 1 */
-
-/* board customer ID */
-/* #define CONFIG_CUSTOMER_ID (0x6472616F624C4D41) */
-
-/* Choose One of Ethernet Type */
-#undef CONFIG_ETHERNET_NONE
-#define ETHERNET_INTERNAL_PHY
-#undef ETHERNET_EXTERNAL_PHY
-
-#if defined(CONFIG_CMD_AML_MTEST)
-#if !defined(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_CMD_AML_MTEST depends on CONFIG_SYS_MEM_TOP_HIDE;
-#endif
-#if !(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_SYS_MEM_TOP_HIDE should not be zero;
-#endif
-#endif
-
-#endif
diff --git a/include/configs/g12b_puddy_px.h b/include/configs/g12b_puddy_px.h
deleted file mode 100755
index adb48f9..0000000
--- a/include/configs/g12b_puddy_px.h
+++ /dev/null
@@ -1,553 +0,0 @@
-
-/*
- *
- * Copyright (C) 2019 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#ifndef __G12B_PUDDY_PX_H__
-#define __G12B_PUDDY_PX_H__
-
-#include <asm/arch/cpu.h>
-
-//#define CONFIG_SYS_GENERIC_BOARD 1
-/*
-#ifndef CONFIG_AML_MESON
-#warning "include warning"
-#endif
-*/
-
-/*
- * platform power init config
- */
-#define AML_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
-#define AML_VDDEE_INIT_VOLTAGE 840 // VDDEE power up voltage
-#define AML_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
-
-/* SMP Definitinos */
-#define CPU_RELEASE_ADDR secondary_boot_func
-
-/* Serial config */
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_BAUDRATE 115200
-/* #define CONFIG_AML_MESON_SERIAL 1 */
-
-/* Enable ir remote wake up for bl30 */
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
-
-/*config the default parameters for adc power key*/
-#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
-#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
-
-/* args/envs */
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=1080000\0" \
- "outputmode=panel\0" \
- "hdmimode=1080p60hz\0" \
- "display_width=1920\0" \
- "display_height=1080\0" \
- "display_bpp=16\0" \
- "display_color_index=16\0" \
- "display_layer=osd0\0" \
- "display_color_fg=0xffff\0" \
- "display_color_bg=0\0" \
- "dtb_mem_addr=0x1000000\0" \
- "fb_addr=0x76800000\0" \
- "fb_width=800\0" \
- "fb_height=1280\0" \
- "usb_burning=update 1000\0" \
- "fdt_high=0x20000000\0" \
- "try_auto_burn=update 700 750;\0" \
- "sdcburncfg=aml_sdc_burn.ini\0" \
- "sdc_burning=sdc_burn ${sdcburncfg}\0" \
- "wipe_data=successful\0" \
- "wipe_cache=successful\0" \
- "EnableSelinux=enforcing\0" \
- "recovery_part=recovery\0" \
- "recovery_offset=0\0" \
- "active_slot=_a\0" \
- "boot_part=boot\0" \
- "ext4_system=1:5\0" \
- "storeargs=" \
- "setenv bootargs " \
- "gpt " \
- "logo=${display_layer},loaded,${fb_addr} " \
- "vout=${outputmode},enable " \
- "panel_type=${panel_type} " \
- "androidboot.selinux=${EnableSelinux} " \
- "test_mode=${test_mode} " \
- "androidboot.hardware="__stringify(BOARD_NAME)" " \
- "hw_id=${hw_id} " \
- "androidboot.reboot_mode=${reboot_mode} " \
- "androidboot.slot_suffix=${active_slot};" \
- "\0" \
- "switch_bootmode="\
- "get_rebootmode;"\
- "echo reboot_mode:${reboot_mode};"\
- "if test ${reboot_mode} = factory_reset; then "\
- "run recovery_from_flash;"\
- "else if test ${reboot_mode} = update; then "\
- "run update;"\
- "else if test ${reboot_mode} = cold_boot; then "\
- "echo cold_boot; " \
- "else if test ${reboot_mode} = fastboot; then "\
- "fastboot;" \
- "else if test ${reboot_mode} = factory_boot; then " \
- "ddr_auto_fast_boot_check 6 ;"\
- "if imgread kernel fct ${loadaddr}; then " \
- "bootm ${loadaddr};" \
- "fi;" \
- "fi;fi;fi;fi;fi;" \
- "\0" \
- "storeboot="\
- "ddr_auto_fast_boot_check 6 ;"\
- "if imgread kernel ${boot_part} ${loadaddr}; then " \
- "bootm ${loadaddr};" \
- "fi;" \
- "run update;"\
- "\0"\
- "factory_reset_poweroff_protect="\
- "echo wipe_data=${wipe_data};" \
- "echo wipe_cache=${wipe_cache};" \
- "if test ${wipe_data} = failed; then "\
- "run init_display;" \
- "run get_hw_id;" \
- "run storeargs;"\
- "if usb start 0; then "\
- "run recovery_from_udisk;"\
- "fi;"\
- "run recovery_from_flash;"\
- "fi; "\
- "if test ${wipe_cache} = failed; then "\
- "run init_display;" \
- "run get_hw_id;" \
- "run storeargs;"\
- "if mmcinfo; then "\
- "run recovery_from_sdcard;"\
- "fi;"\
- "if usb start 0; then "\
- "run recovery_from_udisk;"\
- "fi;"\
- "run recovery_from_flash;"\
- "fi;" \
- "\0" \
- "update="\
- /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
- "run usb_burning; "\
- "if usb start 0; then "\
- "run recovery_from_udisk;"\
- "fi;"\
- "run recovery_from_flash;"\
- "\0"\
- "recovery_from_sdcard="\
- "if fatload mmc 0 ${loadaddr} aml_autoscript; then " \
- "autoscr ${loadaddr}; " \
- "fi;" \
- "if fatload mmc 0 ${loadaddr} recovery.img; then "\
- "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then " \
- "echo sd dtb.img loaded; " \
- "fi;" \
- "wipeisb;" \
- "bootm ${loadaddr};" \
- "fi;" \
- "\0"\
- "recovery_from_udisk="\
- "if fatload usb 0 ${loadaddr} recovery.img; then "\
- "wipeisb;" \
- "bootm ${loadaddr};" \
- "fi;" \
- "\0"\
- "recovery_from_flash="\
- "setenv bootargs " \
- "${bootargs} " \
- "aml_dt=${aml_dt} " \
- "recovery_part=${recovery_part} " \
- "recovery_offset=${recovery_offset};" \
- "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then " \
- "wipeisb;" \
- "bootm ${loadaddr};" \
- "fi" \
- "\0"\
- "reset_ddic=" \
- "gpio clear GPIOH_6" \
- "\0" \
- "detect_panel=" \
- "get_ddictype;" \
- "if gpio input GPIOH_0; then " \
- "if test $ddic_type = FITI; then " \
- "env set panel_type inx_dzd_8;" \
- "else " \
- "env set panel_type boe_nvtk_10;" \
- "fi;" \
- "else " \
- "if test $ddic_type = FITI; then " \
- "env set panel_type inx_fiti_10;" \
- "else " \
- "env set panel_type inx_nvtk_10;" \
- "fi;" \
- "fi;" \
- "\0" \
- "set_gamma="\
- "if ext4load mmc ${ext4_system} 0x8000000 gamma_calibration.txt; then " \
- "configure_gamma 0x8000000;" \
- "else " \
- "configure_gamma;" \
- "fi;" \
- "\0" \
- "start_backlight=" \
- "if ext4load mmc ${ext4_system} 0x8000000 bl_calibration.txt; then " \
- "configure_backlight 0x8000000;" \
- "else " \
- "configure_backlight;" \
- "fi;" \
- "\0" \
- "init_display="\
- "run reset_ddic;" \
- "run detect_panel;" \
- "osd open;" \
- "osd clear;" \
- "osd setcolor 0xffffffff;" \
- "get_rebootmode;"\
- /* logo must not fail */ \
- "ext4load mmc ${ext4_system} 0x8000000 logo.bmp;" \
- "bmp display 0x8000000;" \
- /* do this sequentially so we could reuse the address and do
- * not need to know the size of the images */ \
- "if ext4load mmc ${ext4_system} 0x8000000 corner_BL.bmp; then " \
- "bmp display 0x8000000 0 1264;" \
- "fi;" \
- "if ext4load mmc ${ext4_system} 0x8000000 corner_BR.bmp; then " \
- "bmp display 0x8000000 784 1264;" \
- "fi;" \
- "if ext4load mmc ${ext4_system} 0x8000000 corner_TL.bmp; then " \
- "bmp display 0x8000000 0 0;" \
- "fi;" \
- "if ext4load mmc ${ext4_system} 0x8000000 corner_TR.bmp; then " \
- "bmp display 0x8000000 784 0;" \
- "fi;" \
- "bmp scale;" \
- "vout output ${outputmode};" \
- "run set_gamma;" \
- "run start_backlight;" \
- "\0" \
- "get_hw_id=" \
- "get_puddy_hw_id;" \
- "\0" \
- "cmdline_keys=" \
- "if keyman init 0x1234; then " \
- "if keyman read usid ${loadaddr} str; then " \
- "env set bootargs " \
- "${bootargs} " \
- "androidboot.serialno=${usid};" \
- "env set serial ${usid};" \
- "else " \
- "env set bootargs " \
- "${bootargs} " \
- "androidboot.serialno=1234567890;" \
- "env set serial 1234567890;" \
- "fi;" \
- "if keyman read mac ${loadaddr} str; then " \
- "env set bootargs " \
- "${bootargs} " \
- "mac=${mac} " \
- "androidboot.mac=${mac};" \
- "fi;" \
- "if keyman read deviceid ${loadaddr} str; then " \
- "env set bootargs " \
- "${bootargs} " \
- "androidboot.deviceid=${deviceid};" \
- "fi;" \
- "fi;" \
- "\0" \
- "bcb_cmd=" \
- "get_valid_slot;" \
- "\0" \
- "upgrade_key=" \
- "if gpio input GPIOC_7; then " \
- "echo detect VOL_DN pressed;" \
- "if gpio input GPIOC_5; then " \
- "echo VOL_UP pressed;" \
- "env set boot_external_image 1;" \
- "run update;" \
- "else " \
- "echo VOL_UP not pressed;" \
- "setenv boot_external_image 0;" \
- "run recovery_from_flash;" \
- "fi;" \
- "else " \
- "echo upgrade key not pressed;" \
- "env set boot_external_image 0;" \
- "fi;" \
- "\0" \
- "test_mode_check=" \
- "env set test_mode false;" \
- "if gpio input GPIOH_3; then " \
- "echo MUTE not engaged;" \
- "else " \
- "echo MUTE engaged;" \
- "if gpio input GPIOC_5; then " \
- "echo VOL_UP pressed;" \
- "if gpio input GPIOC_7; then " \
- "echo VOL_DN pressed;" \
- "else " \
- "echo VOL_DN not pressed;" \
- "echo boot into TEST MODE;" \
- "env set test_mode true;" \
- "fi;" \
- "else " \
- "echo VOL_UP not pressed;" \
- "fi;" \
- "fi;" \
- "\0" \
-
-
-#define CONFIG_PREBOOT \
- "run factory_reset_poweroff_protect;"\
- "run init_display;"\
- "run get_hw_id;" \
- "run test_mode_check;" \
- "run storeargs;" \
- "run upgrade_key;" \
- "run switch_bootmode;"
-
-/* #define CONFIG_ENV_IS_NOWHERE 1 */
-#define CONFIG_ENV_SIZE (64*1024)
-#define CONFIG_FIT 1
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_ANDROID_BOOT_IMAGE 1
-#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
-
-/* cpu */
-/* #define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24 */
-
-/* ATTENTION */
-/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
-
-//#define CONFIG_NR_DRAM_BANKS 1
-/* ddr functions */
-#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
-#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
-#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
-#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
-#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
-#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
-
-/* storage: emmc/nand/sd */
-#define CONFIG_ENV_OVERWRITE
-/* #define CONFIG_CMD_SAVEENV */
-/* fixme, need fix*/
-
-#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
-#error env in amlnand/mmc already be compatible;
-#endif
-
-/*
-* storage
-* |---------|---------|
-* | |
-* emmc<--Compatible-->nand
-* |-------|-------|
-* | |
-* MTD<-Exclusive->NFTL
-*/
-/* axg only support slc nand */
-/* swither for mtd nand which is for slc only. */
-/* support for mtd */
-
-/* #define CONFIG_AML_MTD 1 */
-
-/* support for nftl */
-/*#define CONFIG_AML_NAND 1*/
-
-#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
-#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
-#endif
-
-#ifdef CONFIG_AML_MTD
-
-/* #define CONFIG_CMD_NAND 1 */
-#define CONFIG_MTD_DEVICE y
-/* mtd parts of ourown.*/
-#define CONFIG_AML_MTDPART 1
-/* mtd parts by env default way.*/
-/*
-#define MTDIDS_NAME_STR "aml_nand.0"
-#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
-#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
- "3M@8192K(logo)," \
- "10M(recovery)," \
- "8M(kernel)," \
- "40M(rootfs)," \
- "-(data)"
-*/
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_MTD_UBI_WL_THRESHOLD 4096
-#define CONFIG_MTD_UBI_BEB_LIMIT 20
-#define CONFIG_RBTREE
-#define CONFIG_CMD_NAND_TORTURE 1
-#define CONFIG_CMD_MTDPARTS 1
-#define CONFIG_MTD_PARTITIONS 1
-#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-/* endof CONFIG_AML_MTD */
-/* #define CONFIG_AML_SD_EMMC 1 */
-#ifdef CONFIG_AML_SD_EMMC
- #define CONFIG_GENERIC_MMC 1
- #define CONFIG_CMD_MMC 1
- #define CONFIG_CMD_GPT 1
- #define CONFIG_SYS_MMC_ENV_DEV 1
- #define CONFIG_EMMC_DDR52_EN 0
- #define CONFIG_EMMC_DDR52_CLK 35000000
-#endif
-#define CONFIG_PARTITIONS 1
-
-#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
- #define CONFIG_CMD_NAND 1
- #define CONFIG_MTD_DEVICE y
- /* #define CONFIG_RBTREE */
- #define CONFIG_CMD_NAND_TORTURE 1
- #define CONFIG_CMD_MTDPARTS 1
- #define CONFIG_MTD_PARTITIONS 1
- #define CONFIG_SYS_MAX_NAND_DEVICE 2
- #define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-
-/* vpu */
-#define AML_VPU_CLK_LEVEL_DFT 7
-
-/* osd */
-#define OSD_SCALE_ENABLE
-#define AML_OSD_HIGH_VERSION
-
-/* USB
- * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
- * Enable CONFIG_MUSB_UDD for Device functionalities.
- */
-/* #define CONFIG_MUSB_UDC 1 */
-/* #define CONFIG_CMD_USB 1 */
-
-#define AML_TXLX_USB 1
-#define USB_PHY2_PLL_PARAMETER_1 0x09400414
-#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
-#define USB_PHY2_PLL_PARAMETER_3 0xAC5F69E5
-#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
-#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
-#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
-#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
-#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
-
-/* UBOOT Facotry usb/sdcard burning config */
-#ifndef AML_DISABLE_UPDATE_MODE
-#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning */
-#define CONFIG_USB_BURNING_TOOL 1
-#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
-#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
-#endif
-
-/* net */
-#if defined(CONFIG_CMD_NET)
- #define CONFIG_DESIGNWARE_ETH 1
- #define CONFIG_PHYLIB 1
- #define CONFIG_NET_MULTI 1
- #define CONFIG_CMD_PING 1
- #define CONFIG_CMD_DHCP 1
- #define CONFIG_CMD_RARP 1
- #define CONFIG_HOSTNAME "arm_gxbb"
- #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
- #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
- #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
- #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
- #define CONFIG_NETMASK 255.255.255.0
-#endif /* (CONFIG_CMD_NET) */
-
-/* other devices */
-#define CONFIG_SHA1 1
-#define CONFIG_MD5 1
-
-/* commands */
-/* #define CONFIG_CMD_FDT 1 */
-
-/*file system*/
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_EFI_PARTITION 1
-
-/* #define CONFIG_MMC 1 */
-#define CONFIG_LZO 1
-
-/* Cache Definitions */
-/* #define CONFIG_SYS_DCACHE_OFF */
-/* #define CONFIG_SYS_ICACHE_OFF */
-
-/* other functions */
-#define CONFIG_FIP_IMG_SUPPORT 1
-/* #define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 */ /* hide 128MB for kernel reserve */
-
-#define CONFIG_CPU_ARMV8
-
-/* #define CONFIG_MULTI_DTB 1 */
-
-/* support secure boot */
-#define CONFIG_AML_SECURE_UBOOT 1
-
-#if defined(CONFIG_AML_SECURE_UBOOT)
-
-/* for SRAM size limitation just disable NAND
- as the socket board default has no NAND */
-/* #undef CONFIG_AML_NAND */
-
-/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
-#define CONFIG_AML_CRYPTO_UBOOT 1
-
-/* unify build for generate encrypted kernel image
- SRC : "board/amlogic/(board)/boot.img"
- DST : "fip/boot.img.encrypt" */
-/* #define CONFIG_AML_CRYPTO_IMG 1 */
-
-#endif /* CONFIG_AML_SECURE_UBOOT */
-
-/* build with uboot auto test */
-/* #define CONFIG_AML_UBOOT_AUTO_TEST 1 */
-
-/* board customer ID */
-/* #define CONFIG_CUSTOMER_ID (0x6472616F624C4D41) */
-
-/* Choose One of Ethernet Type */
-#undef CONFIG_ETHERNET_NONE
-#define ETHERNET_INTERNAL_PHY
-#undef ETHERNET_EXTERNAL_PHY
-
-#if defined(CONFIG_CMD_AML_MTEST)
-#if !defined(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_CMD_AML_MTEST depends on CONFIG_SYS_MEM_TOP_HIDE;
-#endif
-#if !(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_SYS_MEM_TOP_HIDE should not be zero;
-#endif
-#endif
-
-#endif
-
diff --git a/include/configs/g12b_w400_v1.h b/include/configs/g12b_w400_v1.h
deleted file mode 100644
index a3c5aa7..0000000
--- a/include/configs/g12b_w400_v1.h
+++ /dev/null
@@ -1,689 +0,0 @@
-
-/*
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#ifndef __G12B_W400_V1_H__
-#define __G12B_W400_V1_H__
-
-#include <asm/arch/cpu.h>
-
-/* #define CONFIG_SYS_GENERIC_BOARD 1 */
-/*
-#ifndef CONFIG_AML_MESON
-#warning "include warning"
-#endif
-*/
-
-/*
- * platform power init config
- */
-#if 0
-#define CONFIG_PLATFORM_POWER_INIT
-#define CONFIG_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
-#define CONFIG_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
-#define CONFIG_VDDEE_SLEEP_VOLTAGE 770 // VDDEE suspend voltage
-#endif
-
-#define AML_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
-#define AML_VDDEE_INIT_VOLTAGE 800 // VDDEE power up voltage
-#define AML_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
-
-/* configs for CEC */
-#if 0
-#define CONFIG_CEC_OSD_NAME "AML_TV"
-#define CONFIG_CEC_WAKEUP
-/*if use bt-wakeup,open it*/
-#define CONFIG_BT_WAKEUP
-#endif
-/* SMP Definitinos */
-#define CPU_RELEASE_ADDR secondary_boot_func
-
-/* config saradc*/
-#if 0
-#define CONFIG_CMD_SARADC 1
-#define CONFIG_SARADC_CH 2
-#endif
-
-/* Bootloader Control Block function
- That is used for recovery and the bootloader to talk to each other
- */
-#if 0
-#define CONFIG_BOOTLOADER_CONTROL_BLOCK
-#endif
-
-/* Serial config */
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_BAUDRATE 115200
-/* #define CONFIG_AML_MESON_SERIAL 1 */
-#if 0
-#define CONFIG_SERIAL_MULTI 1
-#endif
-
-/* Enable ir remote wake up for bl30 */
-#if 0
-#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
-#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
-#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
-#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
-#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
-#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
-#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
-#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
-#define CONFIG_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
-#endif
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0XBA45BD02 //amlogic small ir--- power
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
-
-/*config the default parameters for adc power key*/
-#if 0
-#define CONFIG_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
-#define CONFIG_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
-#endif
-#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
-#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
-
-/* args/envs */
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "firstboot=1\0"\
- "upgrade_step=0\0"\
- "jtag=disable\0"\
- "loadaddr=1080000\0"\
- "panel_type=lcd_1\0" \
- "outputmode=1080p60hz\0" \
- "hdmimode=1080p60hz\0" \
- "cvbsmode=576cvbs\0" \
- "display_width=1920\0" \
- "display_height=1080\0" \
- "display_bpp=16\0" \
- "display_color_index=16\0" \
- "display_layer=osd0\0" \
- "display_color_fg=0xffff\0" \
- "display_color_bg=0\0" \
- "dtb_mem_addr=0x1000000\0" \
- "fb_addr=0x3d800000\0" \
- "fb_width=1920\0" \
- "fb_height=1080\0" \
- "frac_rate_policy=1\0" \
- "usb_burning=update 1000\0" \
- "fdt_high=0x20000000\0"\
- "try_auto_burn=update 700 750;\0"\
- "sdcburncfg=aml_sdc_burn.ini\0"\
- "sdc_burning=sdc_burn ${sdcburncfg}\0"\
- "wipe_data=successful\0"\
- "wipe_cache=successful\0"\
- "EnableSelinux=enforcing\0" \
- "recovery_part=recovery\0"\
- "recovery_offset=0\0"\
- "cvbs_drv=0\0"\
- "osd_reverse=0\0"\
- "video_reverse=0\0"\
- "lock=10001000\0"\
- "active_slot=normal\0"\
- "boot_part=boot\0"\
- "reboot_mode_android=""normal""\0"\
- "Irq_check_en=0\0"\
- "fs_type=""rootfstype=ramfs""\0"\
- "initargs="\
- "init=/init console=ttyS0,115200 no_console_suspend earlycon=aml-uart,0xff803000 ramoops.pstore_en=1 ramoops.record_size=0x8000 ramoops.console_size=0x4000 "\
- "\0"\
- "upgrade_check="\
- "echo upgrade_step=${upgrade_step}; "\
- "if itest ${upgrade_step} == 3; then "\
- "run init_display; run storeargs; run update;"\
- "else fi;"\
- "\0"\
- "storeargs="\
- "setenv bootargs ${initargs} ${fs_type} reboot_mode_android=${reboot_mode_android} logo=${display_layer},loaded,${fb_addr} vout=${outputmode},enable panel_type=${panel_type} hdmitx=${cecconfig},${colorattribute} hdmimode=${hdmimode} frac_rate_policy=${frac_rate_policy} hdmi_read_edid=${hdmi_read_edid} cvbsmode=${cvbsmode} osd_reverse=${osd_reverse} video_reverse=${video_reverse} irq_check_en=${Irq_check_en} androidboot.selinux=${EnableSelinux} androidboot.firstboot=${firstboot} jtag=${jtag}; "\
- "setenv bootargs ${bootargs} androidboot.hardware=amlogic;"\
- "run cmdline_keys;"\
- "\0"\
- "switch_bootmode="\
- "get_rebootmode;"\
- "if test ${reboot_mode} = factory_reset; then "\
- "setenv reboot_mode_android ""normal"";"\
- "run storeargs;"\
- "run recovery_from_flash;"\
- "else if test ${reboot_mode} = update; then "\
- "setenv reboot_mode_android ""normal"";"\
- "run storeargs;"\
- "run update;"\
- "else if test ${reboot_mode} = quiescent; then "\
- "setenv reboot_mode_android ""quiescent"";"\
- "run storeargs;"\
- "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
- "else if test ${reboot_mode} = recovery_quiescent; then "\
- "setenv reboot_mode_android ""quiescent"";"\
- "run storeargs;"\
- "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
- "run recovery_from_flash;"\
- "else if test ${reboot_mode} = cold_boot; then "\
- "setenv reboot_mode_android ""normal"";"\
- "run storeargs;"\
- "else if test ${reboot_mode} = fastboot; then "\
- "setenv reboot_mode_android ""normal"";"\
- "run storeargs;"\
- "fastboot;"\
- "fi;fi;fi;fi;fi;fi;"\
- "\0" \
- "storeboot="\
- "boot_cooling;"\
- "get_system_as_root_mode;"\
- "echo system_mode: ${system_mode};"\
- "if test ${system_mode} = 1; then "\
- "setenv fs_type ""ro rootwait skip_initramfs"";"\
- "run storeargs;"\
- "fi;"\
- "get_valid_slot;"\
- "get_avb_mode;"\
- "echo active_slot: ${active_slot};"\
- "if test ${active_slot} != normal; then "\
- "setenv bootargs ${bootargs} androidboot.slot_suffix=${active_slot};"\
- "fi;"\
- "if test ${avb2} = 0; then "\
- "if test ${active_slot} = _a; then "\
- "setenv bootargs ${bootargs} root=/dev/mmcblk0p23;"\
- "else if test ${active_slot} = _b; then "\
- "setenv bootargs ${bootargs} root=/dev/mmcblk0p24;"\
- "fi;fi;"\
- "fi;"\
- "imgread dtb _aml_dtb 0x01000000; fdt addr 0x01000000;"\
- "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
- "run update;"\
- "\0"\
- "factory_reset_poweroff_protect="\
- "echo wipe_data=${wipe_data}; echo wipe_cache=${wipe_cache};"\
- "if test ${wipe_data} = failed; then "\
- "run init_display; run storeargs;"\
- "if mmcinfo; then "\
- "run recovery_from_sdcard;"\
- "fi;"\
- "if usb start 0; then "\
- "run recovery_from_udisk;"\
- "fi;"\
- "run recovery_from_flash;"\
- "fi; "\
- "if test ${wipe_cache} = failed; then "\
- "run init_display; run storeargs;"\
- "if mmcinfo; then "\
- "run recovery_from_sdcard;"\
- "fi;"\
- "if usb start 0; then "\
- "run recovery_from_udisk;"\
- "fi;"\
- "run recovery_from_flash;"\
- "fi; \0" \
- "update="\
- /*first usb burning, second sdc_burn, third ext-sd autoscr/recovery, last udisk autoscr/recovery*/\
- "run usb_burning; "\
- "run sdc_burning; "\
- "if mmcinfo; then "\
- "run recovery_from_sdcard;"\
- "fi;"\
- "if usb start 0; then "\
- "run recovery_from_udisk;"\
- "fi;"\
- "run recovery_from_flash;"\
- "\0"\
- "recovery_from_sdcard="\
- "if fatload mmc 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
- "if fatload mmc 0 ${loadaddr} recovery.img; then "\
- "if fatload mmc 0 ${dtb_mem_addr} dtb.img; then echo sd dtb.img loaded; fi;"\
- "wipeisb; "\
- "bootm ${loadaddr};fi;"\
- "\0"\
- "recovery_from_udisk="\
- "if fatload usb 0 ${loadaddr} aml_autoscript; then autoscr ${loadaddr}; fi;"\
- "if fatload usb 0 ${loadaddr} recovery.img; then "\
- "if fatload usb 0 ${dtb_mem_addr} dtb.img; then echo udisk dtb.img loaded; fi;"\
- "wipeisb; "\
- "bootm ${loadaddr};fi;"\
- "\0"\
- "recovery_from_flash="\
- "get_valid_slot;"\
- "echo active_slot: ${active_slot};"\
- "if test ${active_slot} = normal; then "\
- "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part={recovery_part} recovery_offset={recovery_offset};"\
- "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then wipeisb; bootm ${loadaddr}; fi;"\
- "else "\
- "setenv bootargs ${bootargs} aml_dt=${aml_dt} recovery_part=${boot_part} recovery_offset=${recovery_offset};"\
- "if imgread kernel ${boot_part} ${loadaddr}; then bootm ${loadaddr}; fi;"\
- "fi;"\
- "\0"\
- "init_display="\
- "get_rebootmode;"\
- "echo reboot_mode:::: ${reboot_mode};"\
- "if test ${reboot_mode} = quiescent; then "\
- "setenv reboot_mode_android ""quiescent"";"\
- "run storeargs;"\
- "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
- "osd open;osd clear;"\
- "else if test ${reboot_mode} = recovery_quiescent; then "\
- "setenv reboot_mode_android ""quiescent"";"\
- "run storeargs;"\
- "setenv bootargs ${bootargs} androidboot.quiescent=1;"\
- "osd open;osd clear;"\
- "else "\
- "setenv reboot_mode_android ""normal"";"\
- "run storeargs;"\
- "fi;fi;"\
- "\0"\
- "cmdline_keys="\
- "if keyman init 0x1234; then "\
- "if keyman read usid ${loadaddr} str; then "\
- "setenv bootargs ${bootargs} androidboot.serialno=${usid};"\
- "setenv serial ${usid};"\
- "else "\
- "setenv bootargs ${bootargs} androidboot.serialno=1234567890;"\
- "setenv serial 1234567890;"\
- "fi;"\
- "if keyman read mac ${loadaddr} str; then "\
- "setenv bootargs ${bootargs} mac=${mac} androidboot.mac=${mac};"\
- "fi;"\
- "if keyman read deviceid ${loadaddr} str; then "\
- "setenv bootargs ${bootargs} androidboot.deviceid=${deviceid};"\
- "fi;"\
- "if keyman read region_code ${loadaddr} str; then "\
- "setenv bootargs ${bootargs} androidboot.wificountrycode=${region_code};"\
- "else "\
- "setenv bootargs ${bootargs} androidboot.wificountrycode=US;"\
- "fi;"\
- "fi;"\
- "\0"\
- "bcb_cmd="\
- "get_avb_mode;"\
- "get_valid_slot;"\
- "\0"\
- "upgrade_key="\
- "if gpio input GPIOAO_3; then "\
- "echo detect upgrade key; run update;"\
- "fi;"\
- "\0"\
- "irremote_update="\
- "if irkey 2500000 0xe31cfb04 0xb748fb04; then "\
- "echo read irkey ok!; " \
- "if itest ${irkey_value} == 0xe31cfb04; then " \
- "run update;" \
- "else if itest ${irkey_value} == 0xb748fb04; then " \
- "run update;\n" \
- "fi;fi;" \
- "fi;\0" \
-
-
-#define CONFIG_PREBOOT \
- "run bcb_cmd; "\
- "run factory_reset_poweroff_protect;"\
- "run upgrade_check;"\
- "run init_display;"\
- "run storeargs;"\
- "forceupdate;" \
- "bcb uboot-command;"\
- "run switch_bootmode;"
-
-#define CONFIG_BOOTCOMMAND "run storeboot"
-
-/* #define CONFIG_ENV_IS_NOWHERE 1 */
-#define CONFIG_ENV_SIZE (64*1024)
-#define CONFIG_FIT 1
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_ANDROID_BOOT_IMAGE 1
-#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
-
-/* cpu */
-/* #define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24 */
-
-/* ATTENTION */
-/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
-
-//#define CONFIG_NR_DRAM_BANKS 1
-/* ddr functions */
-#if 0
-#define CONFIG_DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
-#define CONFIG_CMD_DDR_D2PLL 0 //0:disable, 1:enable. d2pll cmd
-#define CONFIG_CMD_DDR_TEST 0 //0:disable, 1:enable. ddrtest cmd
-#define CONFIG_DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
-#define CONFIG_DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
-#define CONFIG_DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
-#define CONFIG_DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
-#define CONFIG_DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
-#endif
-#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
-#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
-#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
-#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
-#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
-#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
-
-/* storage: emmc/nand/sd */
-#if 0
-#define CONFIG_STORE_COMPATIBLE 1
-#endif
-#define CONFIG_ENV_OVERWRITE
-/* #define CONFIG_CMD_SAVEENV */
-/* fixme, need fix*/
-
-#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
-#error env in amlnand/mmc already be compatible;
-#endif
-
-/*
-* storage
-* |---------|---------|
-* | |
-* emmc<--Compatible-->nand
-* |-------|-------|
-* | |
-* MTD<-Exclusive->NFTL
-*/
-/* axg only support slc nand */
-/* swither for mtd nand which is for slc only. */
-/* support for mtd */
-
-/* #define CONFIG_AML_MTD 1*/
-
-/* support for nftl */
-/*#define CONFIG_AML_NAND 1*/
-
-#if defined(CONFIG_AML_NAND) && defined(CONFIG_MESON_NFC)
-#error CONFIG_AML_NAND/CONFIG_MESON_NFC can not support at the sametime;
-#endif
-
-#if defined(CONFIG_SPI_NAND) && defined(CONFIG_MESON_NFC)
-#error CONFIG_SPI_NAND/CONFIG_MESON_NFC can not support at the sametime;
-#endif
-
-#ifdef CONFIG_AML_MTD
-
-/* bootlaoder is construct by bl2 and fip
- * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
- * will not be stored continuously, and nand layout
- * would be bl2|rsv|fip|normal, but not
- * bl2|fip|rsv|noraml anymore
- */
-#if 0
-#define CONFIG_DISCRETE_BOOTLOADER
-#endif
-
-#ifdef CONFIG_DISCRETE_BOOTLOADER
-#if 0
-#define CONFIG_TPL_SIZE_PER_COPY 0x200000
-#define CONFIG_TPL_COPY_NUM 4
-#define CONFIG_TPL_PART_NAME "tpl"
-/* for bl2, restricted by romboot */
-/* SKT 1024 pages only support 4 block, so 4 copies */
-#define CONFIG_BL2_COPY_NUM 4
-#endif
-#endif /* CONFIG_DISCRETE_BOOTLOADER */
-
-/* #define CONFIG_CMD_NAND 1 */
-#define CONFIG_MTD_DEVICE y
-/* mtd parts of ourown.*/
-#define CONFIG_AML_MTDPART 1
-/* mtd parts by env default way.*/
-/*
-#define MTDIDS_NAME_STR "aml_nand.0"
-#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
-#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
- "3M@8192K(logo)," \
- "10M(recovery)," \
- "8M(kernel)," \
- "40M(rootfs)," \
- "-(data)"
-*/
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_MTD_UBI_WL_THRESHOLD 4096
-#define CONFIG_MTD_UBI_BEB_LIMIT 20
-#define CONFIG_RBTREE
-#define CONFIG_CMD_NAND_TORTURE 1
-#define CONFIG_CMD_MTDPARTS 1
-#define CONFIG_MTD_PARTITIONS 1
-#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-/* endof CONFIG_AML_MTD */
-/* #define CONFIG_AML_SD_EMMC 1 */
-#ifdef CONFIG_AML_SD_EMMC
- #define CONFIG_GENERIC_MMC 1
- #define CONFIG_CMD_MMC 1
- #define CONFIG_CMD_GPT 1
- #define CONFIG_SYS_MMC_ENV_DEV 1
- #define CONFIG_EMMC_DDR52_EN 0
- #define CONFIG_EMMC_DDR52_CLK 35000000
-#endif
-#define CONFIG_PARTITIONS 1
-#if 0
-#define CONFIG_SYS_NO_FLASH 1
-#endif
-
-#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
- #define CONFIG_CMD_NAND 1
- #define CONFIG_MTD_DEVICE y
- /* #define CONFIG_RBTREE */
- #define CONFIG_CMD_NAND_TORTURE 1
- #define CONFIG_CMD_MTDPARTS 1
- #define CONFIG_MTD_PARTITIONS 1
- #define CONFIG_SYS_MAX_NAND_DEVICE 2
- #define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-
-/* vpu */
-#define AML_VPU_CLK_LEVEL_DFT 7
-
-/* osd */
-#define OSD_SCALE_ENABLE
-#define AML_OSD_HIGH_VERSION
-
-#if 0
-#define CONFIG_AML_CANVAS 1
-#define CONFIG_AML_OSD 1
-#define CONFIG_OSD_SCALE_ENABLE 1
-/* #define CONFIG_CMD_BMP 1 */
-#endif
-
-/* USB
- * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
- * Enable CONFIG_MUSB_UDD for Device functionalities.
- */
-/* #define CONFIG_MUSB_UDC 1 */
-/* #define CONFIG_CMD_USB 1 */
-
-#define USB_PHY2_PLL_PARAMETER_1 0x09400414
-#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
-#define USB_PHY2_PLL_PARAMETER_3 0xAC5F69E5
-
-#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
-#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
-#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
-#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
-#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
-
-
-#define AML_TXLX_USB 1
-
-/* UBOOT fastboot config */
-#if 0
-#define CONFIG_CMD_FASTBOOT 1
-#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1
-#define CONFIG_FASTBOOT_FLASH 1
-#define CONFIG_USB_GADGET 1
-#define CONFIG_USBDOWNLOAD_GADGET 1
-#define CONFIG_SYS_CACHELINE_SIZE 64
-#define CONFIG_FASTBOOT_MAX_DOWN_SIZE 0x8000000
-#define CONFIG_DEVICE_PRODUCT "g12b_w400"
-#endif
-
-/* UBOOT Facotry usb/sdcard burning config */
-/* #define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning */
-#if 0
-#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
-#define CONFIG_POWER_KEY_NOT_SUPPORTED_FOR_BURN 1 //There isnt power-key for factory sdcard burning
-#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
-#endif
-
-#if 0
-#define CONFIG_AML_SECURITY_KEY 1
-#define CONFIG_UNIFY_KEY_MANAGE 1
-#endif
-
-/* net */
-/* #define CONFIG_CMD_NET 1 */
-#define CONFIG_ETH_DESIGNWARE
-#if defined(CONFIG_CMD_NET)
- #define CONFIG_DESIGNWARE_ETH 1
- #define CONFIG_PHYLIB 1
- #define CONFIG_NET_MULTI 1
- #define CONFIG_CMD_PING 1
- #define CONFIG_CMD_DHCP 1
- #define CONFIG_CMD_RARP 1
- #define CONFIG_HOSTNAME "arm_gxbb"
-#if 0
- #define CONFIG_RANDOM_ETHADDR 1 /* use random eth addr, or default */
-#endif
- #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
- #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
- #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
- #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
- #define CONFIG_NETMASK 255.255.255.0
-#endif /* (CONFIG_CMD_NET) */
-
-/* other devices */
-#if 0
-#define CONFIG_EFUSE 1
-#endif
-#define CONFIG_SHA1 1
-#define CONFIG_MD5 1
-
-/* commands */
-#if 0
-#define CONFIG_CMD_CACHE 1
-#define CONFIG_CMD_BOOTI 1
-#define CONFIG_CMD_EFUSE 1
-#define CONFIG_CMD_MEMORY 1
-#define CONFIG_CMD_FAT 1
-#define CONFIG_CMD_GPIO 1
-#define CONFIG_CMD_REBOOT 1
-#define CONFIG_CMD_ECHO 1
-#define CONFIG_CMD_JTAG 1
-#define CONFIG_CMD_AUTOSCRIPT 1
-#define CONFIG_CMD_MISC 1
-#endif
-/* #define CONFIG_CMD_FDT 1 */
-
-/*file system*/
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_EFI_PARTITION 1
-#if 0
-#define CONFIG_AML_PARTITION 1
-#endif
-/* #define CONFIG_MMC 1 */
-#define CONFIG_FS_FAT 1
-#define CONFIG_FS_EXT4 1
-#define CONFIG_LZO 1
-
-#if 0
-#define CONFIG_MDUMP_COMPRESS 1
-#endif
-
-/* Cache Definitions */
-/* #define CONFIG_SYS_DCACHE_OFF */
-/* #define CONFIG_SYS_ICACHE_OFF */
-
-/* other functions */
-#if 0
-#define CONFIG_NEED_BL301 1
-#define CONFIG_NEED_BL32 1
-#define CONFIG_CMD_RSVMEM 1
-#define CONFIG_FIP_IMG_SUPPORT 1
-#define CONFIG_SYS_LONGHELP 1
-#define CONFIG_CMD_MISC 1
-#define CONFIG_CMD_ITEST 1
-#define CONFIG_CMD_CPU_TEMP 1
-#define CONFIG_CMD_LOADB 1
-#endif
-#define CONFIG_FIP_IMG_SUPPORT 1
-/* #define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 */ /* hide 128MB for kernel reserve */
-#define CONFIG_LIBAVB 1
-
-#define CONFIG_CPU_ARMV8
-
-/* #define CONFIG_MULTI_DTB 1 */
-
-/* support secure boot */
-#define CONFIG_AML_SECURE_UBOOT 1
-
-#if defined(CONFIG_AML_SECURE_UBOOT)
-
-/* for SRAM size limitation just disable NAND
- as the socket board default has no NAND */
-/* #undef CONFIG_AML_NAND */
-
-/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
-#define CONFIG_AML_CRYPTO_UBOOT 1
-
-/* unify build for generate encrypted kernel image
- SRC : "board/amlogic/(board)/boot.img"
- DST : "fip/boot.img.encrypt" */
-/* #define CONFIG_AML_CRYPTO_IMG 1 */
-
-#endif /* CONFIG_AML_SECURE_UBOOT */
-
-#if 0
-#define CONFIG_SECURE_STORAGE 1
-#endif
-
-/* build with uboot auto test */
-/* #define CONFIG_AML_UBOOT_AUTO_TEST 1 */
-
-/* board customer ID */
-/* #define CONFIG_CUSTOMER_ID (0x6472616F624C4D41) */
-
-#if 0
-#if defined(CONFIG_CUSTOMER_ID)
- #undef CONFIG_AML_CUSTOMER_ID
- #define CONFIG_AML_CUSTOMER_ID CONFIG_CUSTOMER_ID
-#endif
-#endif
-
-/* Choose One of Ethernet Type */
-#undef CONFIG_ETHERNET_NONE
-#define ETHERNET_INTERNAL_PHY
-#undef ETHERNET_EXTERNAL_PHY
-
-#if 0
-#define CONFIG_CMD_AML_MTEST 1
-#endif
-#if defined(CONFIG_CMD_AML_MTEST)
-#if !defined(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_CMD_AML_MTEST depends on CONFIG_SYS_MEM_TOP_HIDE;
-#endif
-#if !(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_SYS_MEM_TOP_HIDE should not be zero;
-#endif
-#endif
-
-#endif
-
diff --git a/include/configs/sm1_elaine_b1.h b/include/configs/sm1_elaine_b1.h
deleted file mode 100644
index ee9b13d..0000000
--- a/include/configs/sm1_elaine_b1.h
+++ /dev/null
@@ -1,542 +0,0 @@
-
-/*
- * board/amlogic/configs/sm1_elaine_b1.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#ifndef __SM1_ELAINE_B1_H__
-#define __SM1_ELAINE_B1_H__
-
-#include <asm/arch/cpu.h>
-
-//#define CONFIG_SYS_GENERIC_BOARD 1
-/*
-#ifndef CONFIG_AML_MESON
-#warning "include warning"
-#endif
-*/
-//#define CONFIG_ZIRCON_BOOT_IMAGE
-
-/*
- * platform power init config
- */
-
-#define AML_VCCK_INIT_VOLTAGE 810 // VCCK power up voltage
-#define AML_VDDEE_INIT_VOLTAGE 840 // VDDEE power up voltage
-#define AML_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
-
-/* SMP Definitinos */
-#define CPU_RELEASE_ADDR secondary_boot_func
-
-/* Bootloader Control Block function
- That is used for recovery and the bootloader to talk to each other
- */
-
-/* Serial config */
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_BAUDRATE 115200
-/* #define CONFIG_AML_MESON_SERIAL 1 */
-
-/* Enable ir remote wake up for bl30 */
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
-
-/*config the default parameters for adc power key*/
-#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
-#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
-
-/* args/envs */
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=1080000\0" \
- "outputmode=panel\0" \
- "hdmimode=1080p60hz\0" \
- "display_width=1920\0" \
- "display_height=1080\0" \
- "display_bpp=16\0" \
- "display_color_index=16\0" \
- "display_layer=osd0\0" \
- "display_color_fg=0xffff\0" \
- "display_color_bg=0\0" \
- "dtb_mem_addr=0x1000000\0" \
- "fb_addr=0x5f800000\0" \
- "fb_width=608\0" \
- "fb_height=1024\0" \
- "usb_burning=update 1000\0" \
- "fdt_high=0x20000000\0" \
- "try_auto_burn=update 700 750;\0" \
- "sdcburncfg=aml_sdc_burn.ini\0" \
- "sdc_burning=sdc_burn ${sdcburncfg}\0" \
- "wipe_data=successful\0" \
- "wipe_cache=successful\0" \
- "EnableSelinux=enforcing\0" \
- "recovery_part=recovery\0" \
- "recovery_offset=0\0" \
- "active_slot=_a\0" \
- "boot_part=boot\0" \
- "ext4_factory=1:4\0" \
- "ext4_cache=1:12\0" \
- "storeargs=" \
- "get_rebootmode;" \
- "get_chiptype;" \
- "setenv bootargs " \
- "gpt " \
- "logo=${display_layer},loaded,${fb_addr} " \
- "vout=${outputmode},enable " \
- "panel_type=${panel_type} " \
- "androidboot.selinux=${EnableSelinux} " \
- "test_mode=${test_mode} " \
- "androidboot.hardware="__stringify(BOARD_NAME)" " \
- "hw_id=${hw_id} " \
- "chip_type=${chip_type} " \
- "androidboot.reboot_mode=${reboot_mode} " \
- "androidboot.slot_suffix=${active_slot};" \
- "\0" \
- "switch_bootmode=" \
- "get_rebootmode;" \
- "echo reboot_mode:${reboot_mode};"\
- "if test ${reboot_mode} = factory_reset; then " \
- "run recovery_from_flash;" \
- "else if test ${reboot_mode} = update; then " \
- "run update;" \
- "else if test ${reboot_mode} = cold_boot; then " \
- "echo cold_boot; " \
- "else if test ${reboot_mode} = fastboot; then " \
- "fastboot;" \
- "else if test ${reboot_mode} = factory_boot; then " \
- "if imgread kernel system_b ${loadaddr}; then " \
- "bootm ${loadaddr};" \
- "fi;" \
- "fi;fi;fi;fi;fi;" \
- "\0" \
- "detect_ab_slot=" \
- "get_valid_slot;" \
- "\0" \
- "storeboot="\
- "if imgread kernel ${boot_part} ${loadaddr}; then " \
- "bootm ${loadaddr};" \
- "fi;" \
- "run update;" \
- "\0" \
- "factory_reset_poweroff_protect=" \
- "echo wipe_data=${wipe_data};" \
- "echo wipe_cache=${wipe_cache};" \
- "if test ${wipe_data} = failed; then " \
- "run init_display;" \
- "run get_hw_id;" \
- "run storeargs;" \
- "if usb start 0; then " \
- "run recovery_from_udisk;" \
- "fi;" \
- "run recovery_from_flash;" \
- "fi;" \
- "if test ${wipe_cache} = failed; then " \
- "run init_display;" \
- "run get_hw_id;" \
- "run storeargs;" \
- "if usb start 0; then " \
- "run recovery_from_udisk;" \
- "fi;" \
- "run recovery_from_flash;" \
- "fi;" \
- "\0" \
- "update=" \
- "run usb_burning;" \
- "run recovery_from_flash;" \
- "\0" \
- "recovery_from_udisk=" \
- "while true ;do " \
- "usb reset; " \
- "if fatload usb 0 ${loadaddr} recovery.img; then "\
- "bootm ${loadaddr};" \
- "fi;" \
- "done;" \
- "\0" \
- "recovery_from_flash=" \
- "setenv bootargs ${bootargs} " \
- "aml_dt=${aml_dt} " \
- "recovery_part=${recovery_part} " \
- "recovery_offset=${recovery_offset};" \
- "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then " \
- "wipeisb;" \
- "bootm ${loadaddr};" \
- "fi" \
- "\0" \
- "reset_ddic=" \
- "gpio clear GPIOZ_13" \
- "\0" \
- "detect_panel=" \
- "if gpio input GPIOZ_11; then " \
- "if gpio input GPIOZ_12; then " \
- "setenv panel_type kd_fiti9364_7;" \
- "else " \
- "setenv panel_type boe_fiti9364_7;" \
- "fi;" \
- "else " \
- "setenv panel_type inx_fiti9364_7;" \
- "fi;" \
- "\0" \
- "set_gamma="\
- "if ext4load mmc ${ext4_factory} 0x8000000 gamma_calibration.txt; then " \
- "configure_gamma 0x8000000;" \
- "else " \
- "configure_gamma;" \
- "fi;" \
- "\0" \
- "get_backlight=" \
- "if ext4load mmc ${ext4_cache} 0x8000000 last_brightness; then " \
- "get_cached_brightness 0x8000000;" \
- "else " \
- "get_cached_brightness;" \
- "fi;" \
- "\0" \
- "start_backlight=" \
- "if ext4load mmc ${ext4_factory} 0x8000000 bl_calibration.txt; then " \
- "configure_backlight 0x8000000;" \
- "else " \
- "configure_backlight;" \
- "fi;" \
- "\0" \
- "init_display="\
- "run reset_ddic;" \
- "check_fdr_for_backlight_brightness;" \
- "osd open;" \
- "osd clear;" \
- "osd setcolor 0x5b0d5b0d;" \
- "get_rebootmode;" \
- /* logo must not fail */ \
- "ext4load mmc ${ext4_factory} 0x8000000 logo.bmp;" \
- "bmp display 0x8000000;" \
- /* do this sequentially so we could reuse the address and do
- * not need to know the size of the images */ \
- "if ext4load mmc ${ext4_factory} 0x8000000 corner_BL.bmp; then " \
- "bmp display 0x8000000 0 1008;" \
- "fi;" \
- "if ext4load mmc ${ext4_factory} 0x8000000 corner_BR.bmp; then " \
- "bmp display 0x8000000 592 1008;" \
- "fi;" \
- "if ext4load mmc ${ext4_factory} 0x8000000 corner_TL.bmp; then " \
- "bmp display 0x8000000 0 0;" \
- "fi;" \
- "if ext4load mmc ${ext4_factory} 0x8000000 corner_TR.bmp; then " \
- "bmp display 0x8000000 592 0;" \
- "fi;" \
- "bmp scale;" \
- "vout output ${outputmode};" \
- "run set_gamma;" \
- "run get_backlight;" \
- "run start_backlight;" \
- "\0" \
- "get_hw_id=" \
- "get_elaine_hw_id;" \
- "\0" \
- "enable_audio_amp_boost=" \
- "if test ${hw_id} != 0x09; then " \
- "if test ${hw_id} != 0x0a; then " \
- "echo Enabling Amp Boost;" \
- "enable_amp_boost;" \
- "fi;" \
- "fi;" \
- "\0" \
- "upgrade_key=" \
- "if gpio input GPIOZ_5; then " \
- "echo detect VOL_UP pressed;" \
- "if gpio input GPIOZ_6; then " \
- "echo VOL_DN pressed;" \
- "setenv boot_external_image 1;" \
- "run recovery_from_udisk;" \
- "fi;" \
- "else " \
- "echo upgrade key not pressed;" \
- "setenv boot_external_image 0;" \
- "fi;" \
- "\0" \
- "test_mode_check=" \
- "setenv test_mode false;" \
- "if gpio input GPIOZ_2; then " \
- "echo MUTE not engaged;" \
- "else " \
- "echo MUTE engaged;" \
- "if gpio input GPIOZ_5; then " \
- "echo VOL_UP pressed;" \
- "if gpio input GPIOZ_6; then " \
- "echo VOL_DN pressed;" \
- "else " \
- "echo VOL_DN not pressed;" \
- "setenv test_mode true;" \
- "fi;" \
- "else " \
- "echo VOL_UP not pressed;" \
- "fi;" \
- "fi;" \
- "\0" \
-
-#ifdef CONFIG_G_AB_SYSTEM
-#define CONFIG_PREBOOT \
- "run factory_reset_poweroff_protect;"\
- "run init_display;"\
- "run get_hw_id;" \
- "run enable_audio_amp_boost;" \
- "run test_mode_check;" \
- "run detect_ab_slot;" \
- "run storeargs;" \
- "run upgrade_key;" \
- "run switch_bootmode;"
-#else
-#define CONFIG_PREBOOT \
- "run factory_reset_poweroff_protect;"\
- "run get_hw_id;" \
- "run test_mode_check;" \
- "run storeargs;" \
- "run upgrade_key;" \
- "run switch_bootmode;"
-#endif
-
-/* #define CONFIG_ENV_IS_NOWHERE 1 */
-#define CONFIG_ENV_SIZE (64*1024)
-#define CONFIG_FIT 1
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_ANDROID_BOOT_IMAGE 1
-#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
-
-/* cpu */
-/* #define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24 */
-
-/* ATTENTION */
-/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
-
-//#define CONFIG_NR_DRAM_BANKS 1
-/* ddr functions */
-#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
-#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
-#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
-#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
-#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
-#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
-
-/* storage: emmc/nand/sd */
-#define CONFIG_ENV_OVERWRITE
-/* #define CONFIG_CMD_SAVEENV */
-/* fixme, need fix*/
-
-#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
-#error env in amlnand/mmc already be compatible;
-#endif
-
-/*
-* storage
-* |---------|---------|
-* | |
-* emmc<--Compatible-->nand
-* |-------|-------|
-* | |
-* MTD<-Exclusive->NFTL
-*/
-/* axg only support slc nand */
-/* swither for mtd nand which is for slc only. */
-/* support for mtd */
-
-/* #define CONFIG_AML_MTD 1 */
-
-/* support for nftl */
-/*#define CONFIG_AML_NAND 1*/
-
-#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
-#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
-#endif
-
-#ifdef CONFIG_AML_MTD
-
-/* bootlaoder is construct by bl2 and fip
- * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
- * will not be stored continuously, and nand layout
- * would be bl2|rsv|fip|normal, but not
- * bl2|fip|rsv|noraml anymore
- */
-
-/* #define CONFIG_CMD_NAND 1 */
-#define CONFIG_MTD_DEVICE y
-/* mtd parts of ourown.*/
-#define CONFIG_AML_MTDPART 1
-/* mtd parts by env default way.*/
-/*
-#define MTDIDS_NAME_STR "aml_nand.0"
-#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
-#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
- "3M@8192K(logo)," \
- "10M(recovery)," \
- "8M(kernel)," \
- "40M(rootfs)," \
- "-(data)"
-*/
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_MTD_UBI_WL_THRESHOLD 4096
-#define CONFIG_MTD_UBI_BEB_LIMIT 20
-#define CONFIG_RBTREE
-#define CONFIG_CMD_NAND_TORTURE 1
-#define CONFIG_CMD_MTDPARTS 1
-#define CONFIG_MTD_PARTITIONS 1
-#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-/* endof CONFIG_AML_MTD */
-/* #define CONFIG_AML_SD_EMMC 1 */
-#ifdef CONFIG_AML_SD_EMMC
- #define CONFIG_GENERIC_MMC 1
- #define CONFIG_CMD_MMC 1
- #define CONFIG_CMD_GPT 1
- #define CONFIG_SYS_MMC_ENV_DEV 1
- #define CONFIG_EMMC_DDR52_EN 0
- #define CONFIG_EMMC_DDR52_CLK 35000000
-#endif
-#define CONFIG_PARTITIONS 1
-
-#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
- #define CONFIG_CMD_NAND 1
- #define CONFIG_MTD_DEVICE y
- /* #define CONFIG_RBTREE */
- #define CONFIG_CMD_NAND_TORTURE 1
- #define CONFIG_CMD_MTDPARTS 1
- #define CONFIG_MTD_PARTITIONS 1
- #define CONFIG_SYS_MAX_NAND_DEVICE 2
- #define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-
-/* vpu */
-#define AML_VPU_CLK_LEVEL_DFT 7
-
-/* osd */
-#define OSD_SCALE_ENABLE
-#define AML_OSD_HIGH_VERSION
-
-/* USB
- * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
- * Enable CONFIG_MUSB_UDD for Device functionalities.
- */
-/* #define CONFIG_MUSB_UDC 1 */
-/* #define CONFIG_CMD_USB 1 */
-
-#define AML_TXLX_USB 1
-#define USB_PHY2_PLL_PARAMETER_1 0x09400414
-#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
-#define USB_PHY2_PLL_PARAMETER_3 0xAC5F69E5
-#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
-#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
-#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
-#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
-#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
-
-/* UBOOT Facotry usb/sdcard burning config */
-#ifndef AML_DISABLE_UPDATE_MODE
-#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
-#define CONFIG_USB_BURNING_TOOL 1
-#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
-#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
-#endif
-
-/* net */
-#if defined(CONFIG_CMD_NET)
- #define CONFIG_DESIGNWARE_ETH 1
- #define CONFIG_PHYLIB 1
- #define CONFIG_NET_MULTI 1
- #define CONFIG_CMD_PING 1
- #define CONFIG_CMD_DHCP 1
- #define CONFIG_CMD_RARP 1
- #define CONFIG_HOSTNAME "arm_gxbb"
- #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
- #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
- #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
- #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
- #define CONFIG_NETMASK 255.255.255.0
-#endif /* (CONFIG_CMD_NET) */
-
-/* other devices */
-#define CONFIG_SHA1 1
-#define CONFIG_MD5 1
-
-/* commands */
-/* #define CONFIG_CMD_FDT 1 */
-
-/*file system*/
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_EFI_PARTITION 1
-
-/* #define CONFIG_MMC 1 */
-#define CONFIG_LZO 1
-
-/* Cache Definitions */
-/* #define CONFIG_SYS_DCACHE_OFF */
-/* #define CONFIG_SYS_ICACHE_OFF */
-
-/* other functions */
-#define CONFIG_FIP_IMG_SUPPORT 1
-/* #define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 */ /* hide 128MB for kernel reserve */
-
-#define CONFIG_CPU_ARMV8
-
-/* #define CONFIG_MULTI_DTB 1 */
-#define DTB_BIND_KERNEL 1
-
-/* support secure boot */
-#define CONFIG_AML_SECURE_UBOOT 1
-
-#if defined(CONFIG_AML_SECURE_UBOOT)
-
-/* for SRAM size limitation just disable NAND
- as the socket board default has no NAND */
-/* #undef CONFIG_AML_NAND */
-
-/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
-#define CONFIG_AML_CRYPTO_UBOOT 1
-
-/* unify build for generate encrypted kernel image
- SRC : "board/amlogic/(board)/boot.img"
- DST : "fip/boot.img.encrypt" */
-/* #define CONFIG_AML_CRYPTO_IMG 1 */
-
-#endif /* CONFIG_AML_SECURE_UBOOT */
-
-/* build with uboot auto test */
-/* #define CONFIG_AML_UBOOT_AUTO_TEST 1 */
-
-/* board customer ID */
-/* #define CONFIG_CUSTOMER_ID (0x6472616F624C4D41) */
-
-/* Choose One of Ethernet Type */
-#undef CONFIG_ETHERNET_NONE
-#define ETHERNET_INTERNAL_PHY
-#undef ETHERNET_EXTERNAL_PHY
-
-#if defined(CONFIG_CMD_AML_MTEST)
-#if !defined(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_CMD_AML_MTEST depends on CONFIG_SYS_MEM_TOP_HIDE;
-#endif
-#if !(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_SYS_MEM_TOP_HIDE should not be zero;
-#endif
-#endif
-
-#endif
diff --git a/include/configs/sm1_elaine_bx.h b/include/configs/sm1_elaine_bx.h
deleted file mode 100644
index 359a8b2..0000000
--- a/include/configs/sm1_elaine_bx.h
+++ /dev/null
@@ -1,546 +0,0 @@
-
-/*
- * board/amlogic/configs/sm1_elaine_bx.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#ifndef __SM1_ELAINE_BX_H__
-#define __SM1_ELAINE_BX_H__
-
-#include <asm/arch/cpu.h>
-
-//#define CONFIG_SYS_GENERIC_BOARD 1
-/*
-#ifndef CONFIG_AML_MESON
-#warning "include warning"
-#endif
-*/
-//#define CONFIG_ZIRCON_BOOT_IMAGE
-
-/*
- * platform power init config
- */
-
-#define AML_VCCK_INIT_VOLTAGE 810 // VCCK power up voltage
-#define AML_VDDEE_INIT_VOLTAGE 840 // VDDEE power up voltage
-#define AML_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
-
-/* SMP Definitinos */
-#define CPU_RELEASE_ADDR secondary_boot_func
-
-/* Bootloader Control Block function
- That is used for recovery and the bootloader to talk to each other
- */
-
-/* Serial config */
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_BAUDRATE 115200
-/* #define CONFIG_AML_MESON_SERIAL 1 */
-
-/* Enable ir remote wake up for bl30 */
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
-
-/*config the default parameters for adc power key*/
-#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
-#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
-
-/* args/envs */
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=1080000\0" \
- "outputmode=panel\0" \
- "hdmimode=1080p60hz\0" \
- "display_width=1920\0" \
- "display_height=1080\0" \
- "display_bpp=16\0" \
- "display_color_index=16\0" \
- "display_layer=osd0\0" \
- "display_color_fg=0xffff\0" \
- "display_color_bg=0\0" \
- "dtb_mem_addr=0x1000000\0" \
- "fb_addr=0x5f800000\0" \
- "fb_width=608\0" \
- "fb_height=1024\0" \
- "usb_burning=update 1000\0" \
- "fdt_high=0x20000000\0" \
- "try_auto_burn=update 700 750;\0" \
- "sdcburncfg=aml_sdc_burn.ini\0" \
- "sdc_burning=sdc_burn ${sdcburncfg}\0" \
- "wipe_data=successful\0" \
- "wipe_cache=successful\0" \
- "EnableSelinux=enforcing\0" \
- "recovery_part=recovery\0" \
- "recovery_offset=0\0" \
- "active_slot=_a\0" \
- "boot_part=boot\0" \
- "ext4_factory=1:4\0" \
- "ext4_cache=1:12\0" \
- "storeargs=" \
- "get_rebootmode;" \
- "get_chiptype;" \
- "setenv bootargs " \
- "gpt " \
- "logo=${display_layer},loaded,${fb_addr} " \
- "vout=${outputmode},enable " \
- "panel_type=${panel_type} " \
- "androidboot.selinux=${EnableSelinux} " \
- "test_mode=${test_mode} " \
- "androidboot.hardware="__stringify(BOARD_NAME)" " \
- "hw_id=${hw_id} " \
- "chip_type=${chip_type} " \
- "androidboot.reboot_mode=${reboot_mode} " \
- "androidboot.slot_suffix=${active_slot};" \
- "\0" \
- "switch_bootmode=" \
- "get_rebootmode;" \
- "echo reboot_mode:${reboot_mode};"\
- "if test ${reboot_mode} = factory_reset; then " \
- "run recovery_from_flash;" \
- "else if test ${reboot_mode} = update; then " \
- "run update;" \
- "else if test ${reboot_mode} = cold_boot; then " \
- "echo cold_boot; " \
- "else if test ${reboot_mode} = fastboot; then " \
- "fastboot;" \
- "else if test ${reboot_mode} = factory_boot; then " \
- "if imgread kernel system_b ${loadaddr}; then " \
- "bootm ${loadaddr};" \
- "fi;" \
- "fi;fi;fi;fi;fi;" \
- "\0" \
- "detect_ab_slot=" \
- "get_valid_slot;" \
- "\0" \
- "storeboot="\
- "if imgread kernel ${boot_part} ${loadaddr}; then " \
- "bootm ${loadaddr};" \
- "fi;" \
- "run update;" \
- "\0" \
- "factory_reset_poweroff_protect=" \
- "echo wipe_data=${wipe_data};" \
- "echo wipe_cache=${wipe_cache};" \
- "if test ${wipe_data} = failed; then " \
- "run init_display;" \
- "run get_hw_id;" \
- "run storeargs;" \
- "if usb start 0; then " \
- "run recovery_from_udisk;" \
- "fi;" \
- "run recovery_from_flash;" \
- "fi;" \
- "if test ${wipe_cache} = failed; then " \
- "run init_display;" \
- "run get_hw_id;" \
- "run storeargs;" \
- "if usb start 0; then " \
- "run recovery_from_udisk;" \
- "fi;" \
- "run recovery_from_flash;" \
- "fi;" \
- "\0" \
- "update=" \
- "run usb_burning;" \
- "run recovery_from_flash;" \
- "\0" \
- "recovery_from_udisk=" \
- "while true ;do " \
- "usb reset; " \
- "if fatload usb 0 ${loadaddr} recovery.img 0x10000000 0; then "\
- "bootm ${loadaddr};" \
- "fi;" \
- "done;" \
- "\0" \
- "recovery_from_flash=" \
- "setenv bootargs ${bootargs} " \
- "aml_dt=${aml_dt} " \
- "recovery_part=${recovery_part} " \
- "recovery_offset=${recovery_offset};" \
- "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then " \
- "wipeisb;" \
- "bootm ${loadaddr};" \
- "fi" \
- "\0" \
- "reset_ddic=" \
- "gpio clear GPIOZ_13" \
- "\0" \
- "detect_panel=" \
- "if gpio input GPIOZ_11; then " \
- "if gpio input GPIOZ_12; then " \
- "setenv panel_type kd_fiti9364_7;" \
- "else " \
- "setenv panel_type boe_fiti9364_7;" \
- "fi;" \
- "else " \
- "if gpio input GPIOZ_12; then " \
- "setenv panel_type kd_fiti9365_7;" \
- "else " \
- "setenv panel_type boe_fiti9365_7;" \
- "fi;" \
- "fi;" \
- "\0" \
- "set_gamma="\
- "if ext4load mmc ${ext4_factory} 0x8000000 gamma_calibration.txt 0x100000 0; then " \
- "configure_gamma 0x8000000;" \
- "else " \
- "configure_gamma;" \
- "fi;" \
- "\0" \
- "get_backlight=" \
- "if ext4load mmc ${ext4_cache} 0x8000000 last_brightness 0x100000 0; then " \
- "get_cached_brightness 0x8000000;" \
- "else " \
- "get_cached_brightness;" \
- "fi;" \
- "\0" \
- "start_backlight=" \
- "if ext4load mmc ${ext4_factory} 0x8000000 bl_calibration.txt 0x100000 0; then " \
- "configure_backlight 0x8000000;" \
- "else " \
- "configure_backlight;" \
- "fi;" \
- "\0" \
- "init_display="\
- "run reset_ddic;" \
- "check_fdr_for_backlight_brightness;" \
- "osd open;" \
- "osd clear;" \
- "osd setcolor 0x5b0d5b0d;" \
- "get_rebootmode;" \
- /* logo must not fail */ \
- "ext4load mmc ${ext4_factory} 0x8000000 logo.bmp 0x100000 0;" \
- "bmp display 0x8000000;" \
- /* do this sequentially so we could reuse the address and do
- * not need to know the size of the images */ \
- "if ext4load mmc ${ext4_factory} 0x8000000 corner_BL.bmp 0x100000 0; then " \
- "bmp display 0x8000000 0 1008;" \
- "fi;" \
- "if ext4load mmc ${ext4_factory} 0x8000000 corner_BR.bmp 0x100000 0; then " \
- "bmp display 0x8000000 592 1008;" \
- "fi;" \
- "if ext4load mmc ${ext4_factory} 0x8000000 corner_TL.bmp 0x100000 0; then " \
- "bmp display 0x8000000 0 0;" \
- "fi;" \
- "if ext4load mmc ${ext4_factory} 0x8000000 corner_TR.bmp 0x100000 0; then " \
- "bmp display 0x8000000 592 0;" \
- "fi;" \
- "bmp scale;" \
- "vout output ${outputmode};" \
- "run set_gamma;" \
- "run get_backlight;" \
- "run start_backlight;" \
- "\0" \
- "get_hw_id=" \
- "get_elaine_hw_id;" \
- "\0" \
- "enable_audio_amp_boost=" \
- "if test ${hw_id} != 0x09; then " \
- "if test ${hw_id} != 0x0a; then " \
- "echo Enabling Amp Boost;" \
- "enable_amp_boost;" \
- "fi;" \
- "fi;" \
- "\0" \
- "upgrade_key=" \
- "if gpio input GPIOZ_5; then " \
- "echo detect VOL_UP pressed;" \
- "if gpio input GPIOZ_6; then " \
- "echo VOL_DN pressed;" \
- "setenv boot_external_image 1;" \
- "run recovery_from_udisk;" \
- "fi;" \
- "else " \
- "echo upgrade key not pressed;" \
- "setenv boot_external_image 0;" \
- "fi;" \
- "\0" \
- "test_mode_check=" \
- "setenv test_mode false;" \
- "if gpio input GPIOZ_2; then " \
- "echo MUTE not engaged;" \
- "else " \
- "echo MUTE engaged;" \
- "if gpio input GPIOZ_5; then " \
- "echo VOL_UP pressed;" \
- "if gpio input GPIOZ_6; then " \
- "echo VOL_DN pressed;" \
- "else " \
- "echo VOL_DN not pressed;" \
- "setenv test_mode true;" \
- "fi;" \
- "else " \
- "echo VOL_UP not pressed;" \
- "fi;" \
- "fi;" \
- "\0" \
-
-#ifdef CONFIG_G_AB_SYSTEM
-#define CONFIG_PREBOOT \
- "run factory_reset_poweroff_protect;"\
- "run init_display;"\
- "run get_hw_id;" \
- "run enable_audio_amp_boost;" \
- "run test_mode_check;" \
- "run detect_ab_slot;" \
- "run storeargs;" \
- "run upgrade_key;" \
- "run switch_bootmode;"
-#else
-#define CONFIG_PREBOOT \
- "run factory_reset_poweroff_protect;"\
- "run get_hw_id;" \
- "run test_mode_check;" \
- "run storeargs;" \
- "run upgrade_key;" \
- "run switch_bootmode;"
-#endif
-
-/* #define CONFIG_ENV_IS_NOWHERE 1 */
-#define CONFIG_ENV_SIZE (64*1024)
-#define CONFIG_FIT 1
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_ANDROID_BOOT_IMAGE 1
-#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
-
-/* cpu */
-/* #define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24 */
-
-/* ATTENTION */
-/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
-
-//#define CONFIG_NR_DRAM_BANKS 1
-/* ddr functions */
-#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
-#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
-#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
-#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
-#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
-#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
-
-/* storage: emmc/nand/sd */
-#define CONFIG_ENV_OVERWRITE
-/* #define CONFIG_CMD_SAVEENV */
-/* fixme, need fix*/
-
-#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
-#error env in amlnand/mmc already be compatible;
-#endif
-
-/*
-* storage
-* |---------|---------|
-* | |
-* emmc<--Compatible-->nand
-* |-------|-------|
-* | |
-* MTD<-Exclusive->NFTL
-*/
-/* axg only support slc nand */
-/* swither for mtd nand which is for slc only. */
-/* support for mtd */
-
-/* #define CONFIG_AML_MTD 1 */
-
-/* support for nftl */
-/*#define CONFIG_AML_NAND 1*/
-
-#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
-#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
-#endif
-
-#ifdef CONFIG_AML_MTD
-
-/* bootlaoder is construct by bl2 and fip
- * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
- * will not be stored continuously, and nand layout
- * would be bl2|rsv|fip|normal, but not
- * bl2|fip|rsv|noraml anymore
- */
-
-/* #define CONFIG_CMD_NAND 1 */
-#define CONFIG_MTD_DEVICE y
-/* mtd parts of ourown.*/
-#define CONFIG_AML_MTDPART 1
-/* mtd parts by env default way.*/
-/*
-#define MTDIDS_NAME_STR "aml_nand.0"
-#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
-#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
- "3M@8192K(logo)," \
- "10M(recovery)," \
- "8M(kernel)," \
- "40M(rootfs)," \
- "-(data)"
-*/
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_MTD_UBI_WL_THRESHOLD 4096
-#define CONFIG_MTD_UBI_BEB_LIMIT 20
-#define CONFIG_RBTREE
-#define CONFIG_CMD_NAND_TORTURE 1
-#define CONFIG_CMD_MTDPARTS 1
-#define CONFIG_MTD_PARTITIONS 1
-#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-/* endof CONFIG_AML_MTD */
-/* #define CONFIG_AML_SD_EMMC 1 */
-#ifdef CONFIG_AML_SD_EMMC
- #define CONFIG_GENERIC_MMC 1
- #define CONFIG_CMD_MMC 1
- #define CONFIG_CMD_GPT 1
- #define CONFIG_SYS_MMC_ENV_DEV 1
- #define CONFIG_EMMC_DDR52_EN 0
- #define CONFIG_EMMC_DDR52_CLK 35000000
-#endif
-#define CONFIG_PARTITIONS 1
-
-#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
- #define CONFIG_CMD_NAND 1
- #define CONFIG_MTD_DEVICE y
- /* #define CONFIG_RBTREE */
- #define CONFIG_CMD_NAND_TORTURE 1
- #define CONFIG_CMD_MTDPARTS 1
- #define CONFIG_MTD_PARTITIONS 1
- #define CONFIG_SYS_MAX_NAND_DEVICE 2
- #define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-
-/* vpu */
-#define AML_VPU_CLK_LEVEL_DFT 7
-
-/* osd */
-#define OSD_SCALE_ENABLE
-#define AML_OSD_HIGH_VERSION
-
-/* USB
- * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
- * Enable CONFIG_MUSB_UDD for Device functionalities.
- */
-/* #define CONFIG_MUSB_UDC 1 */
-/* #define CONFIG_CMD_USB 1 */
-
-#define AML_TXLX_USB 1
-#define USB_PHY2_PLL_PARAMETER_1 0x09400414
-#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
-#define USB_PHY2_PLL_PARAMETER_3 0xAC5F69E5
-#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
-#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
-#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
-#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
-#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
-
-/* UBOOT Facotry usb/sdcard burning config */
-#ifndef AML_DISABLE_UPDATE_MODE
-#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
-#define CONFIG_USB_BURNING_TOOL 1
-#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
-#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
-#endif
-
-/* net */
-#if defined(CONFIG_CMD_NET)
- #define CONFIG_DESIGNWARE_ETH 1
- #define CONFIG_PHYLIB 1
- #define CONFIG_NET_MULTI 1
- #define CONFIG_CMD_PING 1
- #define CONFIG_CMD_DHCP 1
- #define CONFIG_CMD_RARP 1
- #define CONFIG_HOSTNAME "arm_gxbb"
- #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
- #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
- #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
- #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
- #define CONFIG_NETMASK 255.255.255.0
-#endif /* (CONFIG_CMD_NET) */
-
-/* other devices */
-#define CONFIG_SHA1 1
-#define CONFIG_MD5 1
-
-/* commands */
-/* #define CONFIG_CMD_FDT 1 */
-
-/*file system*/
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_EFI_PARTITION 1
-
-/* #define CONFIG_MMC 1 */
-#define CONFIG_LZO 1
-
-/* Cache Definitions */
-/* #define CONFIG_SYS_DCACHE_OFF */
-/* #define CONFIG_SYS_ICACHE_OFF */
-
-/* other functions */
-#define CONFIG_FIP_IMG_SUPPORT 1
-/* #define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 */ /* hide 128MB for kernel reserve */
-
-#define CONFIG_CPU_ARMV8
-
-/* #define CONFIG_MULTI_DTB 1 */
-#define DTB_BIND_KERNEL 1
-
-/* support secure boot */
-#define CONFIG_AML_SECURE_UBOOT 1
-
-#if defined(CONFIG_AML_SECURE_UBOOT)
-
-/* for SRAM size limitation just disable NAND
- as the socket board default has no NAND */
-/* #undef CONFIG_AML_NAND */
-
-/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
-#define CONFIG_AML_CRYPTO_UBOOT 1
-
-/* unify build for generate encrypted kernel image
- SRC : "board/amlogic/(board)/boot.img"
- DST : "fip/boot.img.encrypt" */
-/* #define CONFIG_AML_CRYPTO_IMG 1 */
-
-#endif /* CONFIG_AML_SECURE_UBOOT */
-
-/* build with uboot auto test */
-/* #define CONFIG_AML_UBOOT_AUTO_TEST 1 */
-
-/* board customer ID */
-/* #define CONFIG_CUSTOMER_ID (0x6472616F624C4D41) */
-
-/* Choose One of Ethernet Type */
-#undef CONFIG_ETHERNET_NONE
-#define ETHERNET_INTERNAL_PHY
-#undef ETHERNET_EXTERNAL_PHY
-
-#if defined(CONFIG_CMD_AML_MTEST)
-#if !defined(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_CMD_AML_MTEST depends on CONFIG_SYS_MEM_TOP_HIDE;
-#endif
-#if !(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_SYS_MEM_TOP_HIDE should not be zero;
-#endif
-#endif
-
-#endif
diff --git a/include/configs/sm1_elaine_p0.h b/include/configs/sm1_elaine_p0.h
deleted file mode 100644
index d02615b..0000000
--- a/include/configs/sm1_elaine_p0.h
+++ /dev/null
@@ -1,517 +0,0 @@
-
-/*
- * board/amlogic/configs/sm1_elaine_p0.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#ifndef __SM1_ELAINE_P0_H__
-#define __SM1_ELAINE_P0_H__
-
-#include <asm/arch/cpu.h>
-
-//#define CONFIG_SYS_GENERIC_BOARD 1
-/*
-#ifndef CONFIG_AML_MESON
-#warning "include warning"
-#endif
-*/
-//#define CONFIG_ZIRCON_BOOT_IMAGE
-
-/*
- * platform power init config
- */
-
-#define AML_VCCK_INIT_VOLTAGE 800 // VCCK power up voltage
-#define AML_VDDEE_INIT_VOLTAGE 840 // VDDEE power up voltage
-#define AML_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
-
-/* SMP Definitinos */
-#define CPU_RELEASE_ADDR secondary_boot_func
-
-/* Bootloader Control Block function
- That is used for recovery and the bootloader to talk to each other
- */
-
-/* Serial config */
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_BAUDRATE 115200
-/* #define CONFIG_AML_MESON_SERIAL 1 */
-
-/* Enable ir remote wake up for bl30 */
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
-
-/*config the default parameters for adc power key*/
-#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
-#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
-
-/* args/envs */
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=1080000\0" \
- "outputmode=panel\0" \
- "hdmimode=1080p60hz\0" \
- "display_width=1920\0" \
- "display_height=1080\0" \
- "display_bpp=16\0" \
- "display_color_index=16\0" \
- "display_layer=osd0\0" \
- "display_color_fg=0xffff\0" \
- "display_color_bg=0\0" \
- "dtb_mem_addr=0x1000000\0" \
- "fb_addr=0x5f800000\0" \
- "fb_width=608\0" \
- "fb_height=1024\0" \
- "usb_burning=update 1000\0" \
- "fdt_high=0x20000000\0" \
- "try_auto_burn=update 700 750;\0" \
- "sdcburncfg=aml_sdc_burn.ini\0" \
- "sdc_burning=sdc_burn ${sdcburncfg}\0" \
- "wipe_data=successful\0" \
- "wipe_cache=successful\0" \
- "EnableSelinux=enforcing\0" \
- "recovery_part=recovery\0" \
- "recovery_offset=0\0" \
- "active_slot=_a\0" \
- "boot_part=boot\0" \
- "ext4_factory=1:4\0" \
- "storeargs=" \
- "get_rebootmode;" \
- "setenv bootargs " \
- "gpt " \
- "logo=${display_layer},loaded,${fb_addr} " \
- "vout=${outputmode},enable " \
- "panel_type=${panel_type} " \
- "androidboot.selinux=${EnableSelinux} " \
- "test_mode=${test_mode} " \
- "androidboot.hardware="__stringify(BOARD_NAME)" " \
- "hw_id=${hw_id} " \
- "androidboot.reboot_mode=${reboot_mode} " \
- "androidboot.slot_suffix=${active_slot};" \
- "\0" \
- "switch_bootmode=" \
- "get_rebootmode;" \
- "echo reboot_mode:${reboot_mode};"\
- "if test ${reboot_mode} = factory_reset; then " \
- "run recovery_from_flash;" \
- "else if test ${reboot_mode} = update; then " \
- "run update;" \
- "else if test ${reboot_mode} = cold_boot; then " \
- "echo cold_boot; " \
- "else if test ${reboot_mode} = fastboot; then " \
- "fastboot;" \
- "else if test ${reboot_mode} = factory_boot; then " \
- "ddr_auto_fast_boot_check 6 ;"\
- "if imgread kernel fct ${loadaddr}; then " \
- "bootm ${loadaddr};" \
- "fi;" \
- "fi;fi;fi;fi;fi;" \
- "\0" \
- "storeboot=" \
- "ddr_auto_fast_boot_check 6 ;"\
- "if imgread kernel ${boot_part} ${loadaddr}; then " \
- "bootm ${loadaddr};" \
- "fi;" \
- "run update;" \
- "\0" \
- "factory_reset_poweroff_protect=" \
- "echo wipe_data=${wipe_data};" \
- "echo wipe_cache=${wipe_cache};" \
- "if test ${wipe_data} = failed; then " \
- "run init_display;" \
- "run get_hw_id;" \
- "run storeargs;" \
- "if usb start 0; then " \
- "run recovery_from_udisk;" \
- "fi;" \
- "run recovery_from_flash;" \
- "fi;" \
- "if test ${wipe_cache} = failed; then " \
- "run init_display;" \
- "run get_hw_id;" \
- "run storeargs;" \
- "if usb start 0; then " \
- "run recovery_from_udisk;" \
- "fi;" \
- "run recovery_from_flash;" \
- "fi;" \
- "\0" \
- "update=" \
- "run usb_burning;" \
- "run recovery_from_flash;" \
- "\0" \
- "recovery_from_udisk=" \
- "while true ;do " \
- "usb reset; " \
- "if fatload usb 0 ${loadaddr} recovery.img; then "\
- "bootm ${loadaddr};" \
- "fi;" \
- "done;" \
- "\0" \
- "recovery_from_flash=" \
- "setenv bootargs ${bootargs} " \
- "aml_dt=${aml_dt} " \
- "recovery_part=${recovery_part} " \
- "recovery_offset=${recovery_offset};" \
- "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then " \
- "wipeisb;" \
- "bootm ${loadaddr};" \
- "fi" \
- "\0" \
- "reset_ddic=" \
- "gpio clear GPIOH_6" \
- "\0" \
- "detect_panel=" \
- "get_ddictype;" \
- "if test $ddic_type = FITI; then " \
- "if gpio input GPIOH_5; then " \
- "setenv panel_type lcd_3;" \
- "else " \
- "setenv panel_type lcd_4;" \
- "fi;" \
- "else " \
- "if gpio input GPIOH_5; then " \
- "setenv panel_type lcd_1;" \
- "else " \
- "setenv panel_type lcd_2;" \
- "fi;" \
- "fi;" \
- "\0" \
- "set_gamma="\
- "if ext4load mmc ${ext4_factory} 0x8000000 gamma_calibration.txt; then " \
- "configure_gamma 0x8000000;" \
- "else " \
- "configure_gamma;" \
- "fi;" \
- "\0" \
- "start_backlight=" \
- "if ext4load mmc ${ext4_factory} 0x8000000 bl_calibration.txt; then " \
- "configure_backlight 0x8000000;" \
- "else " \
- "configure_backlight;" \
- "fi;" \
- "\0" \
- "init_display=" \
- "run reset_ddic;" \
- "check_fdr_for_backlight_brightness;" \
- "osd open;" \
- "osd clear;" \
- "osd setcolor 0x5b0d5b0d;" \
- "get_rebootmode;"\
- /* logo must not fail */ \
- "ext4load mmc ${ext4_factory} 0x8000000 logo.bmp;" \
- "bmp display 0x8000000;" \
- /* do this sequentially so we could reuse the address and do
- * not need to know the size of the images */ \
- "if ext4load mmc ${ext4_system} 0x8000000 corner_BL.bmp; then " \
- "bmp display 0x8000000 0 1264;" \
- "fi;" \
- "if ext4load mmc ${ext4_system} 0x8000000 corner_BR.bmp; then " \
- "bmp display 0x8000000 784 1264;" \
- "fi;" \
- "if ext4load mmc ${ext4_system} 0x8000000 corner_TL.bmp; then " \
- "bmp display 0x8000000 0 0;" \
- "fi;" \
- "if ext4load mmc ${ext4_system} 0x8000000 corner_TR.bmp; then " \
- "bmp display 0x8000000 784 0;" \
- "fi;" \
- "bmp scale;" \
- "vout output ${outputmode};" \
- "run set_gamma;" \
- "run start_backlight;" \
- "\0" \
- "get_hw_id=" \
- "get_elaine_hw_id;" \
- "\0" \
- "upgrade_key=" \
- "if gpio input GPIOZ_5; then " \
- "echo detect VOL_UP pressed;" \
- "if gpio input GPIOZ_6; then " \
- "echo VOL_DN pressed;" \
- "setenv boot_external_image 1;" \
- "run recovery_from_udisk;" \
- "fi;" \
- "else " \
- "echo upgrade key not pressed;" \
- "setenv boot_external_image 0;" \
- "fi;" \
- "\0" \
- "test_mode_check=" \
- "setenv test_mode false;" \
- "if gpio input GPIOZ_2; then " \
- "echo MUTE not engaged;" \
- "else " \
- "echo MUTE engaged;" \
- "if gpio input GPIOZ_5; then " \
- "echo VOL_UP pressed;" \
- "if gpio input GPIOZ_6; then " \
- "echo VOL_DN pressed;" \
- "else " \
- "echo VOL_DN not pressed;" \
- "setenv test_mode true;" \
- "fi;" \
- "else " \
- "echo VOL_UP not pressed;" \
- "fi;" \
- "fi;" \
- "\0" \
-
-
-#define CONFIG_PREBOOT \
- "run factory_reset_poweroff_protect;" \
- "run init_display;" \
- "run get_hw_id;" \
- "run test_mode_check;" \
- "run storeargs;" \
- "run upgrade_key;" \
- "run switch_bootmode;"
-
-/* #define CONFIG_ENV_IS_NOWHERE 1 */
-#define CONFIG_ENV_SIZE (64*1024)
-#define CONFIG_FIT 1
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_ANDROID_BOOT_IMAGE 1
-#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
-
-/* cpu */
-/* #define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24 */
-
-/* ATTENTION */
-/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
-
-//#define CONFIG_NR_DRAM_BANKS 1
-/* ddr functions */
-#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
-#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
-#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
-#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
-#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
-#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
-
-/* storage: emmc/nand/sd */
-#define CONFIG_ENV_OVERWRITE
-/* #define CONFIG_CMD_SAVEENV */
-/* fixme, need fix*/
-
-#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
-#error env in amlnand/mmc already be compatible;
-#endif
-
-/*
-* storage
-* |---------|---------|
-* | |
-* emmc<--Compatible-->nand
-* |-------|-------|
-* | |
-* MTD<-Exclusive->NFTL
-*/
-/* axg only support slc nand */
-/* swither for mtd nand which is for slc only. */
-/* support for mtd */
-
-/* #define CONFIG_AML_MTD 1 */
-
-/* support for nftl */
-/*#define CONFIG_AML_NAND 1*/
-
-#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
-#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
-#endif
-
-#ifdef CONFIG_AML_MTD
-
-/* bootlaoder is construct by bl2 and fip
- * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
- * will not be stored continuously, and nand layout
- * would be bl2|rsv|fip|normal, but not
- * bl2|fip|rsv|noraml anymore
- */
-
-/* #define CONFIG_CMD_NAND 1 */
-#define CONFIG_MTD_DEVICE y
-/* mtd parts of ourown.*/
-#define CONFIG_AML_MTDPART 1
-/* mtd parts by env default way.*/
-/*
-#define MTDIDS_NAME_STR "aml_nand.0"
-#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
-#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
- "3M@8192K(logo)," \
- "10M(recovery)," \
- "8M(kernel)," \
- "40M(rootfs)," \
- "-(data)"
-*/
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_MTD_UBI_WL_THRESHOLD 4096
-#define CONFIG_MTD_UBI_BEB_LIMIT 20
-#define CONFIG_RBTREE
-#define CONFIG_CMD_NAND_TORTURE 1
-#define CONFIG_CMD_MTDPARTS 1
-#define CONFIG_MTD_PARTITIONS 1
-#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-/* endof CONFIG_AML_MTD */
-/* #define CONFIG_AML_SD_EMMC 1 */
-#ifdef CONFIG_AML_SD_EMMC
- #define CONFIG_GENERIC_MMC 1
- #define CONFIG_CMD_MMC 1
- #define CONFIG_CMD_GPT 1
- #define CONFIG_SYS_MMC_ENV_DEV 1
- #define CONFIG_EMMC_DDR52_EN 0
- #define CONFIG_EMMC_DDR52_CLK 35000000
-#endif
-#define CONFIG_PARTITIONS 1
-
-#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
- #define CONFIG_CMD_NAND 1
- #define CONFIG_MTD_DEVICE y
- /* #define CONFIG_RBTREE */
- #define CONFIG_CMD_NAND_TORTURE 1
- #define CONFIG_CMD_MTDPARTS 1
- #define CONFIG_MTD_PARTITIONS 1
- #define CONFIG_SYS_MAX_NAND_DEVICE 2
- #define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-
-/* vpu */
-#define AML_VPU_CLK_LEVEL_DFT 7
-
-/* osd */
-#define OSD_SCALE_ENABLE
-#define AML_OSD_HIGH_VERSION
-
-/* USB
- * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
- * Enable CONFIG_MUSB_UDD for Device functionalities.
- */
-/* #define CONFIG_MUSB_UDC 1 */
-/* #define CONFIG_CMD_USB 1 */
-
-#define AML_TXLX_USB 1
-#define USB_PHY2_PLL_PARAMETER_1 0x09400414
-#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
-#define USB_PHY2_PLL_PARAMETER_3 0xAC5F69E5
-#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
-#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
-#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
-#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
-#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
-
-/* UBOOT Facotry usb/sdcard burning config */
-#ifndef AML_DISABLE_UPDATE_MODE
-#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
-#define CONFIG_USB_BURNING_TOOL 1
-#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
-#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
-#endif
-
-/* net */
-#if defined(CONFIG_CMD_NET)
- #define CONFIG_DESIGNWARE_ETH 1
- #define CONFIG_PHYLIB 1
- #define CONFIG_NET_MULTI 1
- #define CONFIG_CMD_PING 1
- #define CONFIG_CMD_DHCP 1
- #define CONFIG_CMD_RARP 1
- #define CONFIG_HOSTNAME "arm_gxbb"
- #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
- #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
- #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
- #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
- #define CONFIG_NETMASK 255.255.255.0
-#endif /* (CONFIG_CMD_NET) */
-
-/* other devices */
-#define CONFIG_SHA1 1
-#define CONFIG_MD5 1
-
-/* commands */
-/* #define CONFIG_CMD_FDT 1 */
-
-/*file system*/
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_EFI_PARTITION 1
-
-/* #define CONFIG_MMC 1 */
-#define CONFIG_LZO 1
-
-/* Cache Definitions */
-/* #define CONFIG_SYS_DCACHE_OFF */
-/* #define CONFIG_SYS_ICACHE_OFF */
-
-/* other functions */
-#define CONFIG_FIP_IMG_SUPPORT 1
-/* #define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 */ /* hide 128MB for kernel reserve */
-
-#define CONFIG_CPU_ARMV8
-
-/* #define CONFIG_MULTI_DTB 1 */
-
-#define DTB_BIND_KERNEL 1
-
-/* support secure boot */
-#define CONFIG_AML_SECURE_UBOOT 1
-
-#if defined(CONFIG_AML_SECURE_UBOOT)
-
-/* for SRAM size limitation just disable NAND
- as the socket board default has no NAND */
-/* #undef CONFIG_AML_NAND */
-
-/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
-#define CONFIG_AML_CRYPTO_UBOOT 1
-
-/* unify build for generate encrypted kernel image
- SRC : "board/amlogic/(board)/boot.img"
- DST : "fip/boot.img.encrypt" */
-/* #define CONFIG_AML_CRYPTO_IMG 1 */
-
-#endif /* CONFIG_AML_SECURE_UBOOT */
-
-/* build with uboot auto test */
-/* #define CONFIG_AML_UBOOT_AUTO_TEST 1 */
-
-/* board customer ID */
-/* #define CONFIG_CUSTOMER_ID (0x6472616F624C4D41) */
-
-/* Choose One of Ethernet Type */
-#undef CONFIG_ETHERNET_NONE
-#define ETHERNET_INTERNAL_PHY
-#undef ETHERNET_EXTERNAL_PHY
-
-#if defined(CONFIG_CMD_AML_MTEST)
-#if !defined(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_CMD_AML_MTEST depends on CONFIG_SYS_MEM_TOP_HIDE;
-#endif
-#if !(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_SYS_MEM_TOP_HIDE should not be zero;
-#endif
-#endif
-
-#endif
diff --git a/include/configs/sm1_elaine_p1.h b/include/configs/sm1_elaine_p1.h
deleted file mode 100644
index e5f39cc..0000000
--- a/include/configs/sm1_elaine_p1.h
+++ /dev/null
@@ -1,526 +0,0 @@
-
-/*
- * board/amlogic/configs/sm1_elaine_p1.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#ifndef __SM1_ELAINE_P1_H__
-#define __SM1_ELAINE_P1_H__
-
-#include <asm/arch/cpu.h>
-
-//#define CONFIG_SYS_GENERIC_BOARD 1
-/*
-#ifndef CONFIG_AML_MESON
-#warning "include warning"
-#endif
-*/
-//#define CONFIG_ZIRCON_BOOT_IMAGE
-
-/*
- * platform power init config
- */
-
-#define AML_VCCK_INIT_VOLTAGE 810 // VCCK power up voltage
-#define AML_VDDEE_INIT_VOLTAGE 840 // VDDEE power up voltage
-#define AML_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
-
-/* SMP Definitinos */
-#define CPU_RELEASE_ADDR secondary_boot_func
-
-/* Bootloader Control Block function
- That is used for recovery and the bootloader to talk to each other
- */
-
-/* Serial config */
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_BAUDRATE 115200
-/* #define CONFIG_AML_MESON_SERIAL 1 */
-
-/* Enable ir remote wake up for bl30 */
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
-
-/*config the default parameters for adc power key*/
-#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
-#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
-
-/* args/envs */
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=1080000\0" \
- "outputmode=panel\0" \
- "hdmimode=1080p60hz\0" \
- "display_width=1920\0" \
- "display_height=1080\0" \
- "display_bpp=16\0" \
- "display_color_index=16\0" \
- "display_layer=osd0\0" \
- "display_color_fg=0xffff\0" \
- "display_color_bg=0\0" \
- "dtb_mem_addr=0x1000000\0" \
- "fb_addr=0x5f800000\0" \
- "fb_width=608\0" \
- "fb_height=1024\0" \
- "usb_burning=update 1000\0" \
- "fdt_high=0x20000000\0" \
- "try_auto_burn=update 700 750;\0" \
- "sdcburncfg=aml_sdc_burn.ini\0" \
- "sdc_burning=sdc_burn ${sdcburncfg}\0" \
- "wipe_data=successful\0" \
- "wipe_cache=successful\0" \
- "EnableSelinux=enforcing\0" \
- "recovery_part=recovery\0" \
- "recovery_offset=0\0" \
- "active_slot=_a\0" \
- "boot_part=boot\0" \
- "ext4_factory=1:4\0" \
- "storeargs=" \
- "get_rebootmode;" \
- "get_chiptype;" \
- "setenv bootargs " \
- "gpt " \
- "logo=${display_layer},loaded,${fb_addr} " \
- "vout=${outputmode},enable " \
- "panel_type=${panel_type} " \
- "androidboot.selinux=${EnableSelinux} " \
- "test_mode=${test_mode} " \
- "androidboot.hardware="__stringify(BOARD_NAME)" " \
- "hw_id=${hw_id} " \
- "chip_type=${chip_type} " \
- "androidboot.reboot_mode=${reboot_mode} " \
- "androidboot.slot_suffix=${active_slot};" \
- "\0" \
- "switch_bootmode=" \
- "get_rebootmode;" \
- "echo reboot_mode:${reboot_mode};"\
- "if test ${reboot_mode} = factory_reset; then " \
- "run recovery_from_flash;" \
- "else if test ${reboot_mode} = update; then " \
- "run update;" \
- "else if test ${reboot_mode} = cold_boot; then " \
- "echo cold_boot; " \
- "else if test ${reboot_mode} = fastboot; then " \
- "fastboot;" \
- "else if test ${reboot_mode} = factory_boot; then " \
- "ddr_auto_fast_boot_check 6 ;"\
- "if imgread kernel system_b ${loadaddr}; then " \
- "bootm ${loadaddr};" \
- "fi;" \
- "fi;fi;fi;fi;fi;" \
- "\0" \
- "detect_ab_slot=" \
- "get_valid_slot;" \
- "\0" \
- "storeboot="\
- "ddr_auto_fast_boot_check 6 ;"\
- "if imgread kernel ${boot_part} ${loadaddr}; then " \
- "bootm ${loadaddr};" \
- "fi;" \
- "run update;" \
- "\0" \
- "factory_reset_poweroff_protect=" \
- "echo wipe_data=${wipe_data};" \
- "echo wipe_cache=${wipe_cache};" \
- "if test ${wipe_data} = failed; then " \
- "run init_display;" \
- "run get_hw_id;" \
- "run storeargs;" \
- "if usb start 0; then " \
- "run recovery_from_udisk;" \
- "fi;" \
- "run recovery_from_flash;" \
- "fi;" \
- "if test ${wipe_cache} = failed; then " \
- "run init_display;" \
- "run get_hw_id;" \
- "run storeargs;" \
- "if usb start 0; then " \
- "run recovery_from_udisk;" \
- "fi;" \
- "run recovery_from_flash;" \
- "fi;" \
- "\0" \
- "update=" \
- "run usb_burning;" \
- "run recovery_from_flash;" \
- "\0" \
- "recovery_from_udisk=" \
- "while true ;do " \
- "usb reset; " \
- "if fatload usb 0 ${loadaddr} recovery.img; then "\
- "bootm ${loadaddr};" \
- "fi;" \
- "done;" \
- "\0" \
- "recovery_from_flash=" \
- "setenv bootargs ${bootargs} " \
- "aml_dt=${aml_dt} " \
- "recovery_part=${recovery_part} " \
- "recovery_offset=${recovery_offset};" \
- "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then " \
- "wipeisb;" \
- "bootm ${loadaddr};" \
- "fi" \
- "\0" \
- "reset_ddic=" \
- "gpio clear GPIOZ_13" \
- "\0" \
- "detect_panel=" \
- "if gpio input GPIOZ_11; then " \
- "if gpio input GPIOZ_12; then " \
- "setenv panel_type kd_fiti_7;" \
- "else " \
- "setenv panel_type boe_fiti_7;" \
- "fi;" \
- "else " \
- "setenv panel_type inx_fiti_7;" \
- "fi;" \
- "\0" \
- "set_gamma="\
- "if ext4load mmc ${ext4_factory} 0x8000000 gamma_calibration.txt; then " \
- "configure_gamma 0x8000000;" \
- "else " \
- "configure_gamma;" \
- "fi;" \
- "\0" \
- "start_backlight=" \
- "if ext4load mmc ${ext4_factory} 0x8000000 bl_calibration.txt; then " \
- "configure_backlight 0x8000000;" \
- "else " \
- "configure_backlight;" \
- "fi;" \
- "\0" \
- "init_display="\
- "run reset_ddic;" \
- "check_fdr_for_backlight_brightness;" \
- "osd open;" \
- "osd clear;" \
- "osd setcolor 0x5b0d5b0d;" \
- "get_rebootmode;"\
- /* logo must not fail */ \
- "ext4load mmc ${ext4_factory} 0x8000000 logo.bmp;" \
- "bmp display 0x8000000;" \
- /* do this sequentially so we could reuse the address and do
- * not need to know the size of the images */ \
- "if ext4load mmc ${ext4_factory} 0x8000000 corner_BL.bmp; then " \
- "bmp display 0x8000000 0 1008;" \
- "fi;" \
- "if ext4load mmc ${ext4_factory} 0x8000000 corner_BR.bmp; then " \
- "bmp display 0x8000000 592 1008;" \
- "fi;" \
- "if ext4load mmc ${ext4_factory} 0x8000000 corner_TL.bmp; then " \
- "bmp display 0x8000000 0 0;" \
- "fi;" \
- "if ext4load mmc ${ext4_factory} 0x8000000 corner_TR.bmp; then " \
- "bmp display 0x8000000 592 0;" \
- "fi;" \
- "bmp scale;" \
- "vout output ${outputmode};" \
- "run set_gamma;" \
- "run start_backlight;" \
- "\0" \
- "get_hw_id=" \
- "get_elaine_hw_id;" \
- "\0" \
- "upgrade_key=" \
- "if gpio input GPIOZ_5; then " \
- "echo detect VOL_UP pressed;" \
- "if gpio input GPIOZ_6; then " \
- "echo VOL_DN pressed;" \
- "setenv boot_external_image 1;" \
- "run recovery_from_udisk;" \
- "fi;" \
- "else " \
- "echo upgrade key not pressed;" \
- "setenv boot_external_image 0;" \
- "fi;" \
- "\0" \
- "test_mode_check=" \
- "setenv test_mode false;" \
- "if gpio input GPIOZ_2; then " \
- "echo MUTE not engaged;" \
- "else " \
- "echo MUTE engaged;" \
- "if gpio input GPIOZ_5; then " \
- "echo VOL_UP pressed;" \
- "if gpio input GPIOZ_6; then " \
- "echo VOL_DN pressed;" \
- "else " \
- "echo VOL_DN not pressed;" \
- "setenv test_mode true;" \
- "fi;" \
- "else " \
- "echo VOL_UP not pressed;" \
- "fi;" \
- "fi;" \
- "\0" \
-
-#ifdef CONFIG_G_AB_SYSTEM
-#define CONFIG_PREBOOT \
- "run factory_reset_poweroff_protect;"\
- "run init_display;"\
- "run get_hw_id;" \
- "run test_mode_check;" \
- "run detect_ab_slot;" \
- "run storeargs;" \
- "run upgrade_key;" \
- "run switch_bootmode;"
-#else
-#define CONFIG_PREBOOT \
- "run factory_reset_poweroff_protect;"\
- "run get_hw_id;" \
- "run test_mode_check;" \
- "run storeargs;" \
- "run upgrade_key;" \
- "run switch_bootmode;"
-#endif
-
-/* #define CONFIG_ENV_IS_NOWHERE 1 */
-#define CONFIG_ENV_SIZE (64*1024)
-#define CONFIG_FIT 1
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_ANDROID_BOOT_IMAGE 1
-#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
-
-/* cpu */
-/* #define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24 */
-
-/* ATTENTION */
-/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
-
-//#define CONFIG_NR_DRAM_BANKS 1
-/* ddr functions */
-#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
-#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
-#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
-#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
-#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
-#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
-
-/* storage: emmc/nand/sd */
-#define CONFIG_ENV_OVERWRITE
-/* #define CONFIG_CMD_SAVEENV */
-/* fixme, need fix*/
-
-#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
-#error env in amlnand/mmc already be compatible;
-#endif
-
-/*
-* storage
-* |---------|---------|
-* | |
-* emmc<--Compatible-->nand
-* |-------|-------|
-* | |
-* MTD<-Exclusive->NFTL
-*/
-/* axg only support slc nand */
-/* swither for mtd nand which is for slc only. */
-/* support for mtd */
-
-/* #define CONFIG_AML_MTD 1 */
-
-/* support for nftl */
-/*#define CONFIG_AML_NAND 1*/
-
-#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
-#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
-#endif
-
-#ifdef CONFIG_AML_MTD
-
-/* bootlaoder is construct by bl2 and fip
- * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
- * will not be stored continuously, and nand layout
- * would be bl2|rsv|fip|normal, but not
- * bl2|fip|rsv|noraml anymore
- */
-
-/* #define CONFIG_CMD_NAND 1 */
-#define CONFIG_MTD_DEVICE y
-/* mtd parts of ourown.*/
-#define CONFIG_AML_MTDPART 1
-/* mtd parts by env default way.*/
-/*
-#define MTDIDS_NAME_STR "aml_nand.0"
-#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
-#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
- "3M@8192K(logo)," \
- "10M(recovery)," \
- "8M(kernel)," \
- "40M(rootfs)," \
- "-(data)"
-*/
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_MTD_UBI_WL_THRESHOLD 4096
-#define CONFIG_MTD_UBI_BEB_LIMIT 20
-#define CONFIG_RBTREE
-#define CONFIG_CMD_NAND_TORTURE 1
-#define CONFIG_CMD_MTDPARTS 1
-#define CONFIG_MTD_PARTITIONS 1
-#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-/* endof CONFIG_AML_MTD */
-/* #define CONFIG_AML_SD_EMMC 1 */
-#ifdef CONFIG_AML_SD_EMMC
- #define CONFIG_GENERIC_MMC 1
- #define CONFIG_CMD_MMC 1
- #define CONFIG_CMD_GPT 1
- #define CONFIG_SYS_MMC_ENV_DEV 1
- #define CONFIG_EMMC_DDR52_EN 0
- #define CONFIG_EMMC_DDR52_CLK 35000000
-#endif
-#define CONFIG_PARTITIONS 1
-
-#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
- #define CONFIG_CMD_NAND 1
- #define CONFIG_MTD_DEVICE y
- /* #define CONFIG_RBTREE */
- #define CONFIG_CMD_NAND_TORTURE 1
- #define CONFIG_CMD_MTDPARTS 1
- #define CONFIG_MTD_PARTITIONS 1
- #define CONFIG_SYS_MAX_NAND_DEVICE 2
- #define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-
-/* vpu */
-#define AML_VPU_CLK_LEVEL_DFT 7
-
-/* osd */
-#define OSD_SCALE_ENABLE
-#define AML_OSD_HIGH_VERSION
-
-/* USB
- * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
- * Enable CONFIG_MUSB_UDD for Device functionalities.
- */
-/* #define CONFIG_MUSB_UDC 1 */
-/* #define CONFIG_CMD_USB 1 */
-
-#define AML_TXLX_USB 1
-#define USB_PHY2_PLL_PARAMETER_1 0x09400414
-#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
-#define USB_PHY2_PLL_PARAMETER_3 0xAC5F69E5
-#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
-#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
-#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
-#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
-#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
-
-/* UBOOT Facotry usb/sdcard burning config */
-#ifndef AML_DISABLE_UPDATE_MODE
-#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
-#define CONFIG_USB_BURNING_TOOL 1
-#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
-#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
-#endif
-
-/* net */
-#if defined(CONFIG_CMD_NET)
- #define CONFIG_DESIGNWARE_ETH 1
- #define CONFIG_PHYLIB 1
- #define CONFIG_NET_MULTI 1
- #define CONFIG_CMD_PING 1
- #define CONFIG_CMD_DHCP 1
- #define CONFIG_CMD_RARP 1
- #define CONFIG_HOSTNAME "arm_gxbb"
- #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
- #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
- #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
- #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
- #define CONFIG_NETMASK 255.255.255.0
-#endif /* (CONFIG_CMD_NET) */
-
-/* other devices */
-#define CONFIG_SHA1 1
-#define CONFIG_MD5 1
-
-/* commands */
-/* #define CONFIG_CMD_FDT 1 */
-
-/*file system*/
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_EFI_PARTITION 1
-
-/* #define CONFIG_MMC 1 */
-#define CONFIG_LZO 1
-
-/* Cache Definitions */
-/* #define CONFIG_SYS_DCACHE_OFF */
-/* #define CONFIG_SYS_ICACHE_OFF */
-
-/* other functions */
-#define CONFIG_FIP_IMG_SUPPORT 1
-/* #define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 */ /* hide 128MB for kernel reserve */
-
-#define CONFIG_CPU_ARMV8
-
-/* #define CONFIG_MULTI_DTB 1 */
-#define DTB_BIND_KERNEL 1
-
-/* support secure boot */
-#define CONFIG_AML_SECURE_UBOOT 1
-
-#if defined(CONFIG_AML_SECURE_UBOOT)
-
-/* for SRAM size limitation just disable NAND
- as the socket board default has no NAND */
-/* #undef CONFIG_AML_NAND */
-
-/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
-#define CONFIG_AML_CRYPTO_UBOOT 1
-
-/* unify build for generate encrypted kernel image
- SRC : "board/amlogic/(board)/boot.img"
- DST : "fip/boot.img.encrypt" */
-/* #define CONFIG_AML_CRYPTO_IMG 1 */
-
-#endif /* CONFIG_AML_SECURE_UBOOT */
-
-/* build with uboot auto test */
-/* #define CONFIG_AML_UBOOT_AUTO_TEST 1 */
-
-/* board customer ID */
-/* #define CONFIG_CUSTOMER_ID (0x6472616F624C4D41) */
-
-/* Choose One of Ethernet Type */
-#undef CONFIG_ETHERNET_NONE
-#define ETHERNET_INTERNAL_PHY
-#undef ETHERNET_EXTERNAL_PHY
-
-#if defined(CONFIG_CMD_AML_MTEST)
-#if !defined(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_CMD_AML_MTEST depends on CONFIG_SYS_MEM_TOP_HIDE;
-#endif
-#if !(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_SYS_MEM_TOP_HIDE should not be zero;
-#endif
-#endif
-
-#endif
diff --git a/include/configs/sm1_elaine_p2.h b/include/configs/sm1_elaine_p2.h
deleted file mode 100644
index e469f6e..0000000
--- a/include/configs/sm1_elaine_p2.h
+++ /dev/null
@@ -1,542 +0,0 @@
-
-/*
- * board/amlogic/configs/sm1_elaine_p2.h
- *
- * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
- * You should have received a copy of the GNU General Public License along
- * with this program; if not, write to the Free Software Foundation, Inc.,
- * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
-*/
-
-#ifndef __SM1_ELAINE_P2_H__
-#define __SM1_ELAINE_P2_H__
-
-#include <asm/arch/cpu.h>
-
-//#define CONFIG_SYS_GENERIC_BOARD 1
-/*
-#ifndef CONFIG_AML_MESON
-#warning "include warning"
-#endif
-*/
-//#define CONFIG_ZIRCON_BOOT_IMAGE
-
-/*
- * platform power init config
- */
-
-#define AML_VCCK_INIT_VOLTAGE 810 // VCCK power up voltage
-#define AML_VDDEE_INIT_VOLTAGE 840 // VDDEE power up voltage
-#define AML_VDDEE_SLEEP_VOLTAGE 731 // VDDEE suspend voltage
-
-/* SMP Definitinos */
-#define CPU_RELEASE_ADDR secondary_boot_func
-
-/* Bootloader Control Block function
- That is used for recovery and the bootloader to talk to each other
- */
-
-/* Serial config */
-#define CONFIG_CONS_INDEX 2
-#define CONFIG_BAUDRATE 115200
-/* #define CONFIG_AML_MESON_SERIAL 1 */
-
-/* Enable ir remote wake up for bl30 */
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL1 0xef10fe01 //amlogic tv ir --- power
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL2 0XBB44FB04 //amlogic tv ir --- ch+
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL3 0xF20DFE01 //amlogic tv ir --- ch-
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL4 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL5 0xe51afb04
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL6 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL7 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL8 0xFFFFFFFF
-#define AML_IR_REMOTE_POWER_UP_KEY_VAL9 0xFFFFFFFF
-
-/*config the default parameters for adc power key*/
-#define AML_ADC_POWER_KEY_CHAN 2 /*channel range: 0-7*/
-#define AML_ADC_POWER_KEY_VAL 0 /*sample value range: 0-1023*/
-
-/* args/envs */
-#define CONFIG_SYS_MAXARGS 64
-#define CONFIG_EXTRA_ENV_SETTINGS \
- "loadaddr=1080000\0" \
- "outputmode=panel\0" \
- "hdmimode=1080p60hz\0" \
- "display_width=1920\0" \
- "display_height=1080\0" \
- "display_bpp=16\0" \
- "display_color_index=16\0" \
- "display_layer=osd0\0" \
- "display_color_fg=0xffff\0" \
- "display_color_bg=0\0" \
- "dtb_mem_addr=0x1000000\0" \
- "fb_addr=0x5f800000\0" \
- "fb_width=608\0" \
- "fb_height=1024\0" \
- "usb_burning=update 1000\0" \
- "fdt_high=0x20000000\0" \
- "try_auto_burn=update 700 750;\0" \
- "sdcburncfg=aml_sdc_burn.ini\0" \
- "sdc_burning=sdc_burn ${sdcburncfg}\0" \
- "wipe_data=successful\0" \
- "wipe_cache=successful\0" \
- "EnableSelinux=enforcing\0" \
- "recovery_part=recovery\0" \
- "recovery_offset=0\0" \
- "active_slot=_a\0" \
- "boot_part=boot\0" \
- "ext4_factory=1:4\0" \
- "ext4_cache=1:12\0" \
- "storeargs=" \
- "get_rebootmode;" \
- "get_chiptype;" \
- "setenv bootargs " \
- "gpt " \
- "logo=${display_layer},loaded,${fb_addr} " \
- "vout=${outputmode},enable " \
- "panel_type=${panel_type} " \
- "androidboot.selinux=${EnableSelinux} " \
- "test_mode=${test_mode} " \
- "androidboot.hardware="__stringify(BOARD_NAME)" " \
- "hw_id=${hw_id} " \
- "chip_type=${chip_type} " \
- "androidboot.reboot_mode=${reboot_mode} " \
- "androidboot.slot_suffix=${active_slot};" \
- "\0" \
- "switch_bootmode=" \
- "get_rebootmode;" \
- "echo reboot_mode:${reboot_mode};"\
- "if test ${reboot_mode} = factory_reset; then " \
- "run recovery_from_flash;" \
- "else if test ${reboot_mode} = update; then " \
- "run update;" \
- "else if test ${reboot_mode} = cold_boot; then " \
- "echo cold_boot; " \
- "else if test ${reboot_mode} = fastboot; then " \
- "fastboot;" \
- "else if test ${reboot_mode} = factory_boot; then " \
- "if imgread kernel system_b ${loadaddr}; then " \
- "bootm ${loadaddr};" \
- "fi;" \
- "fi;fi;fi;fi;fi;" \
- "\0" \
- "detect_ab_slot=" \
- "get_valid_slot;" \
- "\0" \
- "storeboot="\
- "if imgread kernel ${boot_part} ${loadaddr}; then " \
- "bootm ${loadaddr};" \
- "fi;" \
- "run update;" \
- "\0" \
- "factory_reset_poweroff_protect=" \
- "echo wipe_data=${wipe_data};" \
- "echo wipe_cache=${wipe_cache};" \
- "if test ${wipe_data} = failed; then " \
- "run init_display;" \
- "run get_hw_id;" \
- "run storeargs;" \
- "if usb start 0; then " \
- "run recovery_from_udisk;" \
- "fi;" \
- "run recovery_from_flash;" \
- "fi;" \
- "if test ${wipe_cache} = failed; then " \
- "run init_display;" \
- "run get_hw_id;" \
- "run storeargs;" \
- "if usb start 0; then " \
- "run recovery_from_udisk;" \
- "fi;" \
- "run recovery_from_flash;" \
- "fi;" \
- "\0" \
- "update=" \
- "run usb_burning;" \
- "run recovery_from_flash;" \
- "\0" \
- "recovery_from_udisk=" \
- "while true ;do " \
- "usb reset; " \
- "if fatload usb 0 ${loadaddr} recovery.img; then "\
- "bootm ${loadaddr};" \
- "fi;" \
- "done;" \
- "\0" \
- "recovery_from_flash=" \
- "setenv bootargs ${bootargs} " \
- "aml_dt=${aml_dt} " \
- "recovery_part=${recovery_part} " \
- "recovery_offset=${recovery_offset};" \
- "if imgread kernel ${recovery_part} ${loadaddr} ${recovery_offset}; then " \
- "wipeisb;" \
- "bootm ${loadaddr};" \
- "fi" \
- "\0" \
- "reset_ddic=" \
- "gpio clear GPIOZ_13" \
- "\0" \
- "detect_panel=" \
- "if gpio input GPIOZ_11; then " \
- "if gpio input GPIOZ_12; then " \
- "setenv panel_type kd_fiti9364_7;" \
- "else " \
- "setenv panel_type boe_fiti9364_7;" \
- "fi;" \
- "else " \
- "setenv panel_type inx_fiti9364_7;" \
- "fi;" \
- "\0" \
- "set_gamma="\
- "if ext4load mmc ${ext4_factory} 0x8000000 gamma_calibration.txt; then " \
- "configure_gamma 0x8000000;" \
- "else " \
- "configure_gamma;" \
- "fi;" \
- "\0" \
- "get_backlight=" \
- "if ext4load mmc ${ext4_cache} 0x8000000 last_brightness; then " \
- "get_cached_brightness 0x8000000;" \
- "else " \
- "get_cached_brightness;" \
- "fi;" \
- "\0" \
- "start_backlight=" \
- "if ext4load mmc ${ext4_factory} 0x8000000 bl_calibration.txt; then " \
- "configure_backlight 0x8000000;" \
- "else " \
- "configure_backlight;" \
- "fi;" \
- "\0" \
- "init_display="\
- "run reset_ddic;" \
- "check_fdr_for_backlight_brightness;" \
- "osd open;" \
- "osd clear;" \
- "osd setcolor 0x5b0d5b0d;" \
- "get_rebootmode;" \
- /* logo must not fail */ \
- "ext4load mmc ${ext4_factory} 0x8000000 logo.bmp;" \
- "bmp display 0x8000000;" \
- /* do this sequentially so we could reuse the address and do
- * not need to know the size of the images */ \
- "if ext4load mmc ${ext4_factory} 0x8000000 corner_BL.bmp; then " \
- "bmp display 0x8000000 0 1008;" \
- "fi;" \
- "if ext4load mmc ${ext4_factory} 0x8000000 corner_BR.bmp; then " \
- "bmp display 0x8000000 592 1008;" \
- "fi;" \
- "if ext4load mmc ${ext4_factory} 0x8000000 corner_TL.bmp; then " \
- "bmp display 0x8000000 0 0;" \
- "fi;" \
- "if ext4load mmc ${ext4_factory} 0x8000000 corner_TR.bmp; then " \
- "bmp display 0x8000000 592 0;" \
- "fi;" \
- "bmp scale;" \
- "vout output ${outputmode};" \
- "run set_gamma;" \
- "run get_backlight;" \
- "run start_backlight;" \
- "\0" \
- "get_hw_id=" \
- "get_elaine_hw_id;" \
- "\0" \
- "enable_audio_amp_boost=" \
- "if test ${hw_id} != 0x09; then " \
- "if test ${hw_id} != 0x0a; then " \
- "echo Enabling Amp Boost;" \
- "enable_amp_boost;" \
- "fi;" \
- "fi;" \
- "\0" \
- "upgrade_key=" \
- "if gpio input GPIOZ_5; then " \
- "echo detect VOL_UP pressed;" \
- "if gpio input GPIOZ_6; then " \
- "echo VOL_DN pressed;" \
- "setenv boot_external_image 1;" \
- "run recovery_from_udisk;" \
- "fi;" \
- "else " \
- "echo upgrade key not pressed;" \
- "setenv boot_external_image 0;" \
- "fi;" \
- "\0" \
- "test_mode_check=" \
- "setenv test_mode false;" \
- "if gpio input GPIOZ_2; then " \
- "echo MUTE not engaged;" \
- "else " \
- "echo MUTE engaged;" \
- "if gpio input GPIOZ_5; then " \
- "echo VOL_UP pressed;" \
- "if gpio input GPIOZ_6; then " \
- "echo VOL_DN pressed;" \
- "else " \
- "echo VOL_DN not pressed;" \
- "setenv test_mode true;" \
- "fi;" \
- "else " \
- "echo VOL_UP not pressed;" \
- "fi;" \
- "fi;" \
- "\0" \
-
-#ifdef CONFIG_G_AB_SYSTEM
-#define CONFIG_PREBOOT \
- "run factory_reset_poweroff_protect;"\
- "run init_display;"\
- "run get_hw_id;" \
- "run enable_audio_amp_boost;" \
- "run test_mode_check;" \
- "run detect_ab_slot;" \
- "run storeargs;" \
- "run upgrade_key;" \
- "run switch_bootmode;"
-#else
-#define CONFIG_PREBOOT \
- "run factory_reset_poweroff_protect;"\
- "run get_hw_id;" \
- "run test_mode_check;" \
- "run storeargs;" \
- "run upgrade_key;" \
- "run switch_bootmode;"
-#endif
-
-/* #define CONFIG_ENV_IS_NOWHERE 1 */
-#define CONFIG_ENV_SIZE (64*1024)
-#define CONFIG_FIT 1
-#define CONFIG_OF_LIBFDT 1
-#define CONFIG_ANDROID_BOOT_IMAGE 1
-#define CONFIG_SYS_BOOTM_LEN (64<<20) /* Increase max gunzip size*/
-
-/* cpu */
-/* #define CONFIG_CPU_CLK 1200 //MHz. Range: 360-2000, should be multiple of 24 */
-
-/* ATTENTION */
-/* DDR configs move to board/amlogic/[board]/firmware/timing.c */
-
-//#define CONFIG_NR_DRAM_BANKS 1
-/* ddr functions */
-#define DDR_FULL_TEST 0 //0:disable, 1:enable. ddr full test
-#define DDR_LOW_POWER 0 //0:disable, 1:enable. ddr clk gate for lp
-#define DDR_ZQ_PD 0 //0:disable, 1:enable. ddr zq power down
-#define DDR_USE_EXT_VREF 0 //0:disable, 1:enable. ddr use external vref
-#define DDR4_TIMING_TEST 0 //0:disable, 1:enable. ddr4 timing test function
-#define DDR_PLL_BYPASS 0 //0:disable, 1:enable. ddr pll bypass function
-
-/* storage: emmc/nand/sd */
-#define CONFIG_ENV_OVERWRITE
-/* #define CONFIG_CMD_SAVEENV */
-/* fixme, need fix*/
-
-#if (defined(CONFIG_ENV_IS_IN_AMLNAND) || defined(CONFIG_ENV_IS_IN_MMC)) && defined(CONFIG_STORE_COMPATIBLE)
-#error env in amlnand/mmc already be compatible;
-#endif
-
-/*
-* storage
-* |---------|---------|
-* | |
-* emmc<--Compatible-->nand
-* |-------|-------|
-* | |
-* MTD<-Exclusive->NFTL
-*/
-/* axg only support slc nand */
-/* swither for mtd nand which is for slc only. */
-/* support for mtd */
-
-/* #define CONFIG_AML_MTD 1 */
-
-/* support for nftl */
-/*#define CONFIG_AML_NAND 1*/
-
-#if defined(CONFIG_AML_NAND) && defined(CONFIG_AML_MTD)
-#error CONFIG_AML_NAND/CONFIG_AML_MTD can not support at the sametime;
-#endif
-
-#ifdef CONFIG_AML_MTD
-
-/* bootlaoder is construct by bl2 and fip
- * when DISCRETE_BOOTLOADER is enabled, bl2 & fip
- * will not be stored continuously, and nand layout
- * would be bl2|rsv|fip|normal, but not
- * bl2|fip|rsv|noraml anymore
- */
-
-/* #define CONFIG_CMD_NAND 1 */
-#define CONFIG_MTD_DEVICE y
-/* mtd parts of ourown.*/
-#define CONFIG_AML_MTDPART 1
-/* mtd parts by env default way.*/
-/*
-#define MTDIDS_NAME_STR "aml_nand.0"
-#define MTDIDS_DEFAULT "nand1=" MTDIDS_NAME_STR
-#define MTDPARTS_DEFAULT "mtdparts=" MTDIDS_NAME_STR ":" \
- "3M@8192K(logo)," \
- "10M(recovery)," \
- "8M(kernel)," \
- "40M(rootfs)," \
- "-(data)"
-*/
-#define CONFIG_CMD_UBI
-#define CONFIG_CMD_UBIFS
-#define CONFIG_MTD_UBI_WL_THRESHOLD 4096
-#define CONFIG_MTD_UBI_BEB_LIMIT 20
-#define CONFIG_RBTREE
-#define CONFIG_CMD_NAND_TORTURE 1
-#define CONFIG_CMD_MTDPARTS 1
-#define CONFIG_MTD_PARTITIONS 1
-#define CONFIG_SYS_MAX_NAND_DEVICE 2
-#define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-/* endof CONFIG_AML_MTD */
-/* #define CONFIG_AML_SD_EMMC 1 */
-#ifdef CONFIG_AML_SD_EMMC
- #define CONFIG_GENERIC_MMC 1
- #define CONFIG_CMD_MMC 1
- #define CONFIG_CMD_GPT 1
- #define CONFIG_SYS_MMC_ENV_DEV 1
- #define CONFIG_EMMC_DDR52_EN 0
- #define CONFIG_EMMC_DDR52_CLK 35000000
-#endif
-#define CONFIG_PARTITIONS 1
-
-#if defined CONFIG_AML_MTD || defined CONFIG_SPI_NAND
- #define CONFIG_CMD_NAND 1
- #define CONFIG_MTD_DEVICE y
- /* #define CONFIG_RBTREE */
- #define CONFIG_CMD_NAND_TORTURE 1
- #define CONFIG_CMD_MTDPARTS 1
- #define CONFIG_MTD_PARTITIONS 1
- #define CONFIG_SYS_MAX_NAND_DEVICE 2
- #define CONFIG_SYS_NAND_BASE_LIST {0}
-#endif
-
-/* vpu */
-#define AML_VPU_CLK_LEVEL_DFT 7
-
-/* osd */
-#define OSD_SCALE_ENABLE
-#define AML_OSD_HIGH_VERSION
-
-/* USB
- * Enable CONFIG_MUSB_HCD for Host functionalities MSC, keyboard
- * Enable CONFIG_MUSB_UDD for Device functionalities.
- */
-/* #define CONFIG_MUSB_UDC 1 */
-/* #define CONFIG_CMD_USB 1 */
-
-#define AML_TXLX_USB 1
-#define USB_PHY2_PLL_PARAMETER_1 0x09400414
-#define USB_PHY2_PLL_PARAMETER_2 0x927e0000
-#define USB_PHY2_PLL_PARAMETER_3 0xAC5F69E5
-#define USB_G12x_PHY_PLL_SETTING_1 (0xfe18)
-#define USB_G12x_PHY_PLL_SETTING_2 (0xfff)
-#define USB_G12x_PHY_PLL_SETTING_3 (0x78000)
-#define USB_G12x_PHY_PLL_SETTING_4 (0xe0004)
-#define USB_G12x_PHY_PLL_SETTING_5 (0xe000c)
-
-/* UBOOT Facotry usb/sdcard burning config */
-#ifndef AML_DISABLE_UPDATE_MODE
-#define CONFIG_AML_V2_FACTORY_BURN 1 //support facotry usb burning
-#define CONFIG_USB_BURNING_TOOL 1
-#define CONFIG_AML_FACTORY_BURN_LOCAL_UPGRADE 1 //support factory sdcard burning
-#define CONFIG_SD_BURNING_SUPPORT_UI 1 //Displaying upgrading progress bar when sdcard/udisk burning
-#endif
-
-/* net */
-#if defined(CONFIG_CMD_NET)
- #define CONFIG_DESIGNWARE_ETH 1
- #define CONFIG_PHYLIB 1
- #define CONFIG_NET_MULTI 1
- #define CONFIG_CMD_PING 1
- #define CONFIG_CMD_DHCP 1
- #define CONFIG_CMD_RARP 1
- #define CONFIG_HOSTNAME "arm_gxbb"
- #define CONFIG_ETHADDR 00:15:18:01:81:31 /* Ethernet address */
- #define CONFIG_IPADDR 10.18.9.97 /* Our ip address */
- #define CONFIG_GATEWAYIP 10.18.9.1 /* Our getway ip address */
- #define CONFIG_SERVERIP 10.18.9.113 /* Tftp server ip address */
- #define CONFIG_NETMASK 255.255.255.0
-#endif /* (CONFIG_CMD_NET) */
-
-/* other devices */
-#define CONFIG_SHA1 1
-#define CONFIG_MD5 1
-
-/* commands */
-/* #define CONFIG_CMD_FDT 1 */
-
-/*file system*/
-#define CONFIG_DOS_PARTITION 1
-#define CONFIG_EFI_PARTITION 1
-
-/* #define CONFIG_MMC 1 */
-#define CONFIG_LZO 1
-
-/* Cache Definitions */
-/* #define CONFIG_SYS_DCACHE_OFF */
-/* #define CONFIG_SYS_ICACHE_OFF */
-
-/* other functions */
-#define CONFIG_FIP_IMG_SUPPORT 1
-/* #define CONFIG_SYS_MEM_TOP_HIDE 0x08000000 */ /* hide 128MB for kernel reserve */
-
-#define CONFIG_CPU_ARMV8
-
-/* #define CONFIG_MULTI_DTB 1 */
-#define DTB_BIND_KERNEL 1
-
-/* support secure boot */
-#define CONFIG_AML_SECURE_UBOOT 1
-
-#if defined(CONFIG_AML_SECURE_UBOOT)
-
-/* for SRAM size limitation just disable NAND
- as the socket board default has no NAND */
-/* #undef CONFIG_AML_NAND */
-
-/* unify build for generate encrypted bootloader "u-boot.bin.encrypt" */
-#define CONFIG_AML_CRYPTO_UBOOT 1
-
-/* unify build for generate encrypted kernel image
- SRC : "board/amlogic/(board)/boot.img"
- DST : "fip/boot.img.encrypt" */
-/* #define CONFIG_AML_CRYPTO_IMG 1 */
-
-#endif /* CONFIG_AML_SECURE_UBOOT */
-
-/* build with uboot auto test */
-/* #define CONFIG_AML_UBOOT_AUTO_TEST 1 */
-
-/* board customer ID */
-/* #define CONFIG_CUSTOMER_ID (0x6472616F624C4D41) */
-
-/* Choose One of Ethernet Type */
-#undef CONFIG_ETHERNET_NONE
-#define ETHERNET_INTERNAL_PHY
-#undef ETHERNET_EXTERNAL_PHY
-
-#if defined(CONFIG_CMD_AML_MTEST)
-#if !defined(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_CMD_AML_MTEST depends on CONFIG_SYS_MEM_TOP_HIDE;
-#endif
-#if !(CONFIG_SYS_MEM_TOP_HIDE)
-#error CONFIG_SYS_MEM_TOP_HIDE should not be zero;
-#endif
-#endif
-
-#endif
diff --git a/include/dm/device_compat.h b/include/dm/device_compat.h
new file mode 100644
index 0000000..07e6807
--- /dev/null
+++ b/include/dm/device_compat.h
@@ -0,0 +1,57 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2020 Sean Anderson <seanga2@gmail.com>
+ * Copyright (c) 2013 Google, Inc
+ *
+ * (C) Copyright 2012
+ * Pavel Herrmann <morpheus.ibis@gmail.com>
+ * Marek Vasut <marex@denx.de>
+ */
+
+#ifndef _DM_DEVICE_COMPAT_H
+#define _DM_DEVICE_COMPAT_H
+
+#include <log.h>
+#include <linux/build_bug.h>
+#include <linux/compat.h>
+
+/*
+ * Define a new identifier which can be tested on by C code. A similar
+ * definition is made for DEBUG in <log.h>.
+ */
+#ifdef VERBOSE_DEBUG
+#define _VERBOSE_DEBUG 1
+#else
+#define _VERBOSE_DEBUG 0
+#endif
+
+/**
+ * dev_printk_emit() - Emit a formatted log message
+ * @cat: Category of the message
+ * @level: Log level of the message
+ * @fmt: Format string
+ * @...: Arguments for @fmt
+ *
+ * This macro logs a message through the appropriate channel. It is a macro so
+ * the if statements can be optimized out (as @level should be a constant known
+ * at compile-time).
+ *
+ * If DEBUG or VERBOSE_DEBUG is defined, then some messages are always printed
+ * (through printf()). This is to match the historical behavior of the dev_xxx
+ * functions.
+ *
+ * If LOG is enabled, use log() to emit the message, otherwise print it based on
+ * the console loglevel.
+ */
+#define dev_printk_emit(cat, level, fmt, ...) \
+({ \
+ if ((_DEBUG && level == LOGL_DEBUG) || \
+ (_VERBOSE_DEBUG && level == LOGL_DEBUG_CONTENT)) \
+ printf(fmt, ##__VA_ARGS__); \
+ else if (CONFIG_IS_ENABLED(LOG)) \
+ log(cat, level, fmt, ##__VA_ARGS__); \
+ else if (level < CONFIG_VAL(LOGLEVEL)) \
+ printf(fmt, ##__VA_ARGS__); \
+})
+
+#endif
diff --git a/include/dm/pinctrl.h b/include/dm/pinctrl.h
index e412f98..cebe277 100644
--- a/include/dm/pinctrl.h
+++ b/include/dm/pinctrl.h
@@ -69,6 +69,7 @@
* pointing a config node. (necessary for pinctrl_full)
* @set_state_simple: do needed pinctrl operations for a peripherl @periph.
* (necessary for pinctrl_simple)
+ * @get_pin_muxing: display the muxing of a given pin.
*/
struct pinctrl_ops {
int (*get_pins_count)(struct udevice *dev);
@@ -145,6 +146,24 @@
* @index: GPIO index within the bank
*/
int (*set_gpio_mux)(struct udevice *dev, int index);
+
+ /**
+ * get_pin_muxing() - show pin muxing
+ *
+ * This allows to display the muxing of a given pin. It's useful for
+ * debug purpose to know if a pin is configured as GPIO or as an
+ * alternate function and which one.
+ * Typically it is used by a PINCTRL driver with knowledge of the SoC
+ * pinctrl setup.
+ *
+ * @dev: Pinctrl device to use
+ * @selector: Pin selector
+ * @buf Pin's muxing description
+ * @size Pin's muxing description length
+ * return 0 if OK, -ve on error
+ */
+ int (*get_pin_muxing)(struct udevice *dev, unsigned int selector,
+ char *buf, int size);
};
#define pinctrl_get_ops(dev) ((struct pinctrl_ops *)(dev)->driver->ops)
@@ -391,4 +410,42 @@
*/
int pinctrl_set_gpio_mux(struct udevice *dev, int banknum, int index);
+/**
+ * pinctrl_get_pin_muxing() - Returns the muxing description
+ *
+ * This allows to display the muxing description of the given pin for
+ * debug purpose
+ *
+ * @dev: Pinctrl device to use
+ * @selector Pin index within pin-controller
+ * @buf Pin's muxing description
+ * @size Pin's muxing description length
+ * @return 0 if OK, -ve on error
+ */
+int pinctrl_get_pin_muxing(struct udevice *dev, int selector, char *buf,
+ int size);
+
+/**
+ * pinctrl_get_pins_count() - display pin-controller pins number
+ *
+ * This allows to know the number of pins owned by a given pin-controller
+ *
+ * @dev: Pinctrl device to use
+ * @return pins number if OK, -ve on error
+ */
+int pinctrl_get_pins_count(struct udevice *dev);
+
+/**
+ * pinctrl_get_pin_name() - Returns the pin's name
+ *
+ * This allows to display the pin's name for debug purpose
+ *
+ * @dev: Pinctrl device to use
+ * @selector Pin index within pin-controller
+ * @buf Pin's name
+ * @return 0 if OK, -ve on error
+ */
+int pinctrl_get_pin_name(struct udevice *dev, int selector, char *buf,
+ int size);
+
#endif /* __PINCTRL_H */
diff --git a/include/dm/read.h b/include/dm/read.h
index 389e30e..1d54e06 100644
--- a/include/dm/read.h
+++ b/include/dm/read.h
@@ -9,6 +9,7 @@
#ifndef _DM_READ_H
#define _DM_READ_H
+#include <dm/device.h>
#include <dm/fdtaddr.h>
#include <dm/ofnode.h>
#include <dm/uclass.h>
diff --git a/include/dm/uclass-id.h b/include/dm/uclass-id.h
index f3bafb3..ca9542d 100644
--- a/include/dm/uclass-id.h
+++ b/include/dm/uclass-id.h
@@ -99,6 +99,7 @@
UCLASS_USB_DEV_GENERIC, /* USB generic device */
UCLASS_USB_HUB, /* USB hub */
UCLASS_USB_GADGET_GENERIC, /* USB generic device */
+ UCLASS_USB_TCPC, /* USB Type-C Port Controller device */
UCLASS_VIDEO, /* Video or LCD device */
UCLASS_VIDEO_BRIDGE, /* Video bridge, e.g. DisplayPort to LVDS */
UCLASS_VIDEO_CONSOLE, /* Text console driver for video device */
diff --git a/include/dt-bindings/clock/a1-clkc.h b/include/dt-bindings/clock/a1-clkc.h
new file mode 100644
index 0000000..cae55e9
--- /dev/null
+++ b/include/dt-bindings/clock/a1-clkc.h
@@ -0,0 +1,102 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_A1_H
+#define __DT_BINDINGS_CLOCK_A1_H
+/*
+ * CLKID index values
+ */
+#define CLKID_XTAL 0
+#define CLKID_FIXED_PLL 1
+#define CLKID_FCLK_DIV2 2
+#define CLKID_FCLK_DIV3 3
+#define CLKID_FCLK_DIV5 4
+#define CLKID_FCLK_DIV7 5
+#define CLKID_SYS_CLK 6
+#define CLKID_SYS_PLL 7
+
+#define CLKID_GATE_BASE 8
+#define CLKID_SPIFC_XTAL_GATE (CLKID_GATE_BASE + 0)
+#define CLKID_SPIFC_GATE (CLKID_GATE_BASE + 1)
+#define CLKID_SAR_ADC_GATE (CLKID_GATE_BASE + 2)
+#define CLKID_SD_EMMC_XTAL_GATE (CLKID_GATE_BASE + 3)
+#define CLKID_SD_EMMC_GATE (CLKID_GATE_BASE + 4)
+#define CLKID_SPICC_A_GATE (CLKID_GATE_BASE + 5)
+
+#define CLKID_MUX_BASE (CLKID_GATE_BASE + 6)
+#define CLKID_SPIFC_MUX (CLKID_MUX_BASE + 0)
+#define CLKID_SARADC_MUX (CLKID_MUX_BASE + 1)
+#define CLKID_SD_EMMC_MUX (CLKID_MUX_BASE + 2)
+#define CLKID_SPICC_A_MUX (CLKID_MUX_BASE + 3)
+
+#define CLKID_DIV_BASE (CLKID_MUX_BASE + 4)
+#define CLKID_SPIFC_DIV (CLKID_DIV_BASE + 0)
+#define CLKID_SARADC_DIV (CLKID_DIV_BASE + 1)
+#define CLKID_SD_EMMC_DIV (CLKID_DIV_BASE + 2)
+#define CLKID_SPICC_A_DIV (CLKID_DIV_BASE + 3)
+
+/* CLKTREE_SYS_CLK_EN0 gates*/
+#define GATE_BASE0 (CLKID_DIV_BASE + 4)
+#define CLKID_CLKTREE (GATE_BASE0 + 0)
+#define CLKID_RESET_CTRL (GATE_BASE0 + 1)
+#define CLKID_ANALOG_CTRL (GATE_BASE0 + 2)
+#define CLKID_PWR_CTRL (GATE_BASE0 + 3)
+#define CLKID_PAD_CTRL (GATE_BASE0 + 4)
+#define CLKID_SYS_CTRL (GATE_BASE0 + 5)
+#define CLKID_TEMP_SENSOR (GATE_BASE0 + 6)
+#define CLKID_AM2AXI_DIV (GATE_BASE0 + 7)
+#define CLKID_SPICC_B (GATE_BASE0 + 8)
+#define CLKID_SPICC_A (GATE_BASE0 + 9)
+#define CLKID_CLK_MSR (GATE_BASE0 + 10)
+#define CLKID_AUDIO (GATE_BASE0 + 11)
+#define CLKID_JTAG_CTRL (GATE_BASE0 + 12)
+#define CLKID_SARADC (GATE_BASE0 + 13)
+#define CLKID_PWM_EF (GATE_BASE0 + 14)
+#define CLKID_PWM_CD (GATE_BASE0 + 15)
+#define CLKID_PWM_AB (GATE_BASE0 + 16)
+#define CLKID_CEC (GATE_BASE0 + 17)
+#define CLKID_I2C_S (GATE_BASE0 + 18)
+#define CLKID_IR_CTRL (GATE_BASE0 + 19)
+#define CLKID_I2C_M_D (GATE_BASE0 + 20)
+#define CLKID_I2C_M_C (GATE_BASE0 + 21)
+#define CLKID_I2C_M_B (GATE_BASE0 + 22)
+#define CLKID_I2C_M_A (GATE_BASE0 + 23)
+#define CLKID_ACODEC (GATE_BASE0 + 24)
+#define CLKID_OTP (GATE_BASE0 + 25)
+#define CLKID_SD_EMMC_A (GATE_BASE0 + 26)
+#define CLKID_USB_PHY (GATE_BASE0 + 27)
+#define CLKID_USB_CTRL (GATE_BASE0 + 28)
+#define CLKID_SYS_DSPB (GATE_BASE0 + 29)
+#define CLKID_SYS_DSPA (GATE_BASE0 + 30)
+#define CLKID_DMA (GATE_BASE0 + 31)
+/* CLKTREE_SYS_CLK_EN1 gates*/
+#define GATE_BASE1 (GATE_BASE0 + 32)
+#define CLKID_IRQ_CTRL (GATE_BASE1 + 0)
+#define CLKID_NIC (GATE_BASE1 + 1)
+#define CLKID_GIC (GATE_BASE1 + 2)
+#define CLKID_UART_C (GATE_BASE1 + 3)
+#define CLKID_UART_B (GATE_BASE1 + 4)
+#define CLKID_UART_A (GATE_BASE1 + 5)
+#define CLKID_SYS_PSRAM (GATE_BASE1 + 6)
+#define CLKID_RSA (GATE_BASE1 + 7)
+#define CLKID_CORESIGHT (GATE_BASE1 + 8)
+/* CLKTREE_AXI_CLK_EN gates */
+#define GATE_BASE2 (GATE_BASE1 + 9)
+#define CLKID_AM2AXI_VAD (GATE_BASE2 + 0)
+#define CLKID_AUDIO_VAD (GATE_BASE2 + 1)
+#define CLKID_AXI_DMC (GATE_BASE2 + 2)
+#define CLKID_AXI_PSRAM (GATE_BASE2 + 3)
+#define CLKID_RAMB (GATE_BASE2 + 4)
+#define CLKID_RAMA (GATE_BASE2 + 5)
+#define CLKID_AXI_SPIFC (GATE_BASE2 + 6)
+#define CLKID_AXI_NIC (GATE_BASE2 + 7)
+#define CLKID_AXI_DMA (GATE_BASE2 + 8)
+#define CLKID_CPU_CTRL (GATE_BASE2 + 9)
+#define CLKID_ROM (GATE_BASE2 + 10)
+#define CLKID_PROC_I2C (GATE_BASE2 + 11)
+
+#define CLKID_UNREALIZED 100
+
+#endif /* __A1_CLKC_H */
diff --git a/include/dt-bindings/clock/c1-clkc.h b/include/dt-bindings/clock/c1-clkc.h
new file mode 100644
index 0000000..eef6d95
--- /dev/null
+++ b/include/dt-bindings/clock/c1-clkc.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_C1_H
+#define __DT_BINDINGS_CLOCK_C1_H
+/*
+ * CLKID index values
+ */
+#define CLKID_XTAL 0
+#define CLKID_FIXED_PLL 1
+#define CLKID_FCLK_DIV2 2
+#define CLKID_FCLK_DIV3 3
+#define CLKID_FCLK_DIV5 4
+#define CLKID_FCLK_DIV7 5
+#define CLKID_FCLK_DIV2P5 6
+#define CLKID_FCLK_DIV4 7
+#define CLKID_SYS_CLK 8
+#define CLKID_SYS_PLL 9
+#define CLKID_SD_EMMC_A_XTAL_GATE 10
+#define CLKID_SD_EMMC_B_XTAL_GATE 11
+#define CLKID_SD_EMMC_C_XTAL_GATE 12
+
+
+#define CLKID_GATE_BASE 13
+#define CLKID_SPIFC_XTAL_GATE (CLKID_GATE_BASE + 0)
+#define CLKID_SPIFC_GATE (CLKID_GATE_BASE + 1)
+#define CLKID_SYS_SPIFC (CLKID_GATE_BASE + 2)
+#define CLKID_SAR_ADC_GATE (CLKID_GATE_BASE + 3)
+#define CLKID_SPICC_A_GATE (CLKID_GATE_BASE + 4)
+#define CLKID_SPICC_B_GATE (CLKID_GATE_BASE + 5)
+#define CLKID_SD_EMMC_B_GATE (CLKID_GATE_BASE + 6)
+#define CLKID_SD_EMMC_C_GATE (CLKID_GATE_BASE + 7)
+#define CLKID_SD_EMMC_A_GATE (CLKID_GATE_BASE + 8)
+
+#define CLKID_MUX_BASE (CLKID_GATE_BASE + 9)
+#define CLKID_SPIFC_MUX (CLKID_MUX_BASE + 0)
+#define CLKID_SARADC_MUX (CLKID_MUX_BASE + 1)
+#define CLKID_SPICC_A_MUX (CLKID_MUX_BASE + 2)
+#define CLKID_SPICC_B_MUX (CLKID_MUX_BASE + 3)
+#define CLKID_SD_EMMC_B_MUX (CLKID_MUX_BASE + 4)
+#define CLKID_SD_EMMC_C_MUX (CLKID_MUX_BASE + 5)
+#define CLKID_SD_EMMC_A_MUX (CLKID_MUX_BASE + 6)
+
+#define CLKID_DIV_BASE (CLKID_MUX_BASE + 7)
+#define CLKID_SPIFC_DIV (CLKID_DIV_BASE + 0)
+#define CLKID_SARADC_DIV (CLKID_DIV_BASE + 1)
+#define CLKID_SPICC_A_DIV (CLKID_DIV_BASE + 2)
+#define CLKID_SPICC_B_DIV (CLKID_DIV_BASE + 3)
+#define CLKID_SD_EMMC_B_DIV (CLKID_DIV_BASE + 4)
+#define CLKID_SD_EMMC_C_DIV (CLKID_DIV_BASE + 5)
+#define CLKID_SD_EMMC_A_DIV (CLKID_MUX_BASE + 6)
+
+/* CLKTREE_SYS_CLK_EN0 gates*/
+#define GATE_BASE0 (CLKID_DIV_BASE + 7)
+#define CLKID_CLKTREE (GATE_BASE0 + 0)
+#define CLKID_RESET_CTRL (GATE_BASE0 + 1)
+#define CLKID_ANALOG_CTRL (GATE_BASE0 + 2)
+#define CLKID_PWR_CTRL (GATE_BASE0 + 3)
+#define CLKID_PAD_CTRL (GATE_BASE0 + 4)
+#define CLKID_SYS_CTRL (GATE_BASE0 + 5)
+#define CLKID_TEMP_SENSOR (GATE_BASE0 + 6)
+#define CLKID_AM2AXI_DIV (GATE_BASE0 + 7)
+#define CLKID_SPICC_B (GATE_BASE0 + 8)
+#define CLKID_SPICC_A (GATE_BASE0 + 9)
+#define CLKID_CLK_MSR (GATE_BASE0 + 10)
+#define CLKID_AUDIO (GATE_BASE0 + 11)
+#define CLKID_JTAG_CTRL (GATE_BASE0 + 12)
+#define CLKID_SARADC (GATE_BASE0 + 13)
+#define CLKID_PWM_EF (GATE_BASE0 + 14)
+#define CLKID_PWM_CD (GATE_BASE0 + 15)
+#define CLKID_PWM_AB (GATE_BASE0 + 16)
+#define CLKID_CEC (GATE_BASE0 + 17)
+#define CLKID_I2C_S (GATE_BASE0 + 18)
+#define CLKID_IR_CTRL (GATE_BASE0 + 19)
+#define CLKID_I2C_M_D (GATE_BASE0 + 20)
+#define CLKID_I2C_M_C (GATE_BASE0 + 21)
+#define CLKID_I2C_M_B (GATE_BASE0 + 22)
+#define CLKID_I2C_M_A (GATE_BASE0 + 23)
+#define CLKID_ACODEC (GATE_BASE0 + 24)
+#define CLKID_OTP (GATE_BASE0 + 25)
+#define CLKID_SD_EMMC_A (GATE_BASE0 + 26)
+#define CLKID_USB_PHY (GATE_BASE0 + 27)
+#define CLKID_USB_CTRL (GATE_BASE0 + 28)
+#define CLKID_SYS_DSPB (GATE_BASE0 + 29)
+#define CLKID_SYS_DSPA (GATE_BASE0 + 30)
+#define CLKID_DMA (GATE_BASE0 + 31)
+/* CLKTREE_SYS_CLK_EN1 gates*/
+#define GATE_BASE1 (GATE_BASE0 + 32)
+#define CLKID_IRQ_CTRL (GATE_BASE1 + 0)
+#define CLKID_NIC (GATE_BASE1 + 1)
+#define CLKID_GIC (GATE_BASE1 + 2)
+#define CLKID_UART_C (GATE_BASE1 + 3)
+#define CLKID_UART_B (GATE_BASE1 + 4)
+#define CLKID_UART_A (GATE_BASE1 + 5)
+#define CLKID_SYS_PSRAM (GATE_BASE1 + 6)
+#define CLKID_RSA (GATE_BASE1 + 7)
+#define CLKID_CORESIGHT (GATE_BASE1 + 8)
+/* CLKTREE_AXI_CLK_EN gates */
+#define GATE_BASE2 (GATE_BASE1 + 9)
+#define CLKID_AM2AXI_VAD (GATE_BASE2 + 0)
+#define CLKID_AUDIO_VAD (GATE_BASE2 + 1)
+#define CLKID_AXI_DMC (GATE_BASE2 + 2)
+#define CLKID_AXI_PSRAM (GATE_BASE2 + 3)
+#define CLKID_RAMB (GATE_BASE2 + 4)
+#define CLKID_RAMA (GATE_BASE2 + 5)
+#define CLKID_AXI_SPIFC (GATE_BASE2 + 6)
+#define CLKID_AXI_NIC (GATE_BASE2 + 7)
+#define CLKID_AXI_DMA (GATE_BASE2 + 8)
+#define CLKID_CPU_CTRL (GATE_BASE2 + 9)
+#define CLKID_ROM (GATE_BASE2 + 10)
+#define CLKID_PROC_I2C (GATE_BASE2 + 11)
+
+#define CLKID_UNREALIZED 100
+
+#endif /* __A1_CLKC_H */
diff --git a/include/dt-bindings/clock/c2-clkc.h b/include/dt-bindings/clock/c2-clkc.h
new file mode 100644
index 0000000..39c9435
--- /dev/null
+++ b/include/dt-bindings/clock/c2-clkc.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_C2_H
+#define __DT_BINDINGS_CLOCK_C2_H
+/*
+ * CLKID index values
+ */
+#define CLKID_XTAL 0
+#define CLKID_FIXED_PLL 1
+#define CLKID_FCLK_DIV2 2
+#define CLKID_FCLK_DIV3 3
+#define CLKID_FCLK_DIV5 4
+#define CLKID_FCLK_DIV7 5
+#define CLKID_FCLK_DIV2P5 6
+#define CLKID_FCLK_DIV4 7
+#define CLKID_SYS_CLK 8
+#define CLKID_SYS_PLL 9
+#define CLKID_SD_EMMC_A_XTAL_GATE 10
+#define CLKID_SD_EMMC_B_XTAL_GATE 11
+#define CLKID_SD_EMMC_C_XTAL_GATE 12
+
+
+#define CLKID_GATE_BASE 13
+#define CLKID_SPIFC_XTAL_GATE (CLKID_GATE_BASE + 0)
+#define CLKID_SPIFC_GATE (CLKID_GATE_BASE + 1)
+#define CLKID_SYS_SPIFC (CLKID_GATE_BASE + 2)
+#define CLKID_SAR_ADC_GATE (CLKID_GATE_BASE + 3)
+#define CLKID_SPICC_A_GATE (CLKID_GATE_BASE + 4)
+#define CLKID_SPICC_B_GATE (CLKID_GATE_BASE + 5)
+#define CLKID_SD_EMMC_B_GATE (CLKID_GATE_BASE + 6)
+#define CLKID_SD_EMMC_C_GATE (CLKID_GATE_BASE + 7)
+#define CLKID_SD_EMMC_A_GATE (CLKID_GATE_BASE + 8)
+
+#define CLKID_MUX_BASE (CLKID_GATE_BASE + 9)
+#define CLKID_SPIFC_MUX (CLKID_MUX_BASE + 0)
+#define CLKID_SARADC_MUX (CLKID_MUX_BASE + 1)
+#define CLKID_SPICC_A_MUX (CLKID_MUX_BASE + 2)
+#define CLKID_SPICC_B_MUX (CLKID_MUX_BASE + 3)
+#define CLKID_SD_EMMC_B_MUX (CLKID_MUX_BASE + 4)
+#define CLKID_SD_EMMC_C_MUX (CLKID_MUX_BASE + 5)
+#define CLKID_SD_EMMC_A_MUX (CLKID_MUX_BASE + 6)
+
+#define CLKID_DIV_BASE (CLKID_MUX_BASE + 7)
+#define CLKID_SPIFC_DIV (CLKID_DIV_BASE + 0)
+#define CLKID_SARADC_DIV (CLKID_DIV_BASE + 1)
+#define CLKID_SPICC_A_DIV (CLKID_DIV_BASE + 2)
+#define CLKID_SPICC_B_DIV (CLKID_DIV_BASE + 3)
+#define CLKID_SD_EMMC_B_DIV (CLKID_DIV_BASE + 4)
+#define CLKID_SD_EMMC_C_DIV (CLKID_DIV_BASE + 5)
+#define CLKID_SD_EMMC_A_DIV (CLKID_MUX_BASE + 6)
+
+/* CLKTREE_SYS_CLK_EN0 gates*/
+#define GATE_BASE0 (CLKID_DIV_BASE + 7)
+#define CLKID_CLKTREE (GATE_BASE0 + 0)
+#define CLKID_RESET_CTRL (GATE_BASE0 + 1)
+#define CLKID_ANALOG_CTRL (GATE_BASE0 + 2)
+#define CLKID_PWR_CTRL (GATE_BASE0 + 3)
+#define CLKID_PAD_CTRL (GATE_BASE0 + 4)
+#define CLKID_SYS_CTRL (GATE_BASE0 + 5)
+#define CLKID_TEMP_SENSOR (GATE_BASE0 + 6)
+#define CLKID_AM2AXI_DIV (GATE_BASE0 + 7)
+#define CLKID_SPICC_B (GATE_BASE0 + 8)
+#define CLKID_SPICC_A (GATE_BASE0 + 9)
+#define CLKID_CLK_MSR (GATE_BASE0 + 10)
+#define CLKID_AUDIO (GATE_BASE0 + 11)
+#define CLKID_JTAG_CTRL (GATE_BASE0 + 12)
+#define CLKID_SARADC (GATE_BASE0 + 13)
+#define CLKID_PWM_EF (GATE_BASE0 + 14)
+#define CLKID_PWM_CD (GATE_BASE0 + 15)
+#define CLKID_PWM_AB (GATE_BASE0 + 16)
+#define CLKID_CEC (GATE_BASE0 + 17)
+#define CLKID_I2C_S (GATE_BASE0 + 18)
+#define CLKID_IR_CTRL (GATE_BASE0 + 19)
+#define CLKID_I2C_M_D (GATE_BASE0 + 20)
+#define CLKID_I2C_M_C (GATE_BASE0 + 21)
+#define CLKID_I2C_M_B (GATE_BASE0 + 22)
+#define CLKID_I2C_M_A (GATE_BASE0 + 23)
+#define CLKID_ACODEC (GATE_BASE0 + 24)
+#define CLKID_OTP (GATE_BASE0 + 25)
+#define CLKID_SD_EMMC_A (GATE_BASE0 + 26)
+#define CLKID_USB_PHY (GATE_BASE0 + 27)
+#define CLKID_USB_CTRL (GATE_BASE0 + 28)
+#define CLKID_SYS_DSPB (GATE_BASE0 + 29)
+#define CLKID_SYS_DSPA (GATE_BASE0 + 30)
+#define CLKID_DMA (GATE_BASE0 + 31)
+/* CLKTREE_SYS_CLK_EN1 gates*/
+#define GATE_BASE1 (GATE_BASE0 + 32)
+#define CLKID_IRQ_CTRL (GATE_BASE1 + 0)
+#define CLKID_NIC (GATE_BASE1 + 1)
+#define CLKID_GIC (GATE_BASE1 + 2)
+#define CLKID_UART_C (GATE_BASE1 + 3)
+#define CLKID_UART_B (GATE_BASE1 + 4)
+#define CLKID_UART_A (GATE_BASE1 + 5)
+#define CLKID_SYS_PSRAM (GATE_BASE1 + 6)
+#define CLKID_RSA (GATE_BASE1 + 7)
+#define CLKID_CORESIGHT (GATE_BASE1 + 8)
+/* CLKTREE_AXI_CLK_EN gates */
+#define GATE_BASE2 (GATE_BASE1 + 9)
+#define CLKID_AM2AXI_VAD (GATE_BASE2 + 0)
+#define CLKID_AUDIO_VAD (GATE_BASE2 + 1)
+#define CLKID_AXI_DMC (GATE_BASE2 + 2)
+#define CLKID_AXI_PSRAM (GATE_BASE2 + 3)
+#define CLKID_RAMB (GATE_BASE2 + 4)
+#define CLKID_RAMA (GATE_BASE2 + 5)
+#define CLKID_AXI_SPIFC (GATE_BASE2 + 6)
+#define CLKID_AXI_NIC (GATE_BASE2 + 7)
+#define CLKID_AXI_DMA (GATE_BASE2 + 8)
+#define CLKID_CPU_CTRL (GATE_BASE2 + 9)
+#define CLKID_ROM (GATE_BASE2 + 10)
+#define CLKID_PROC_I2C (GATE_BASE2 + 11)
+
+#define CLKID_UNREALIZED 100
+
+#endif /* __A1_CLKC_H */
diff --git a/include/dt-bindings/clock/g12-clkc.h b/include/dt-bindings/clock/g12-clkc.h
index 621ef45..7323045 100644
--- a/include/dt-bindings/clock/g12-clkc.h
+++ b/include/dt-bindings/clock/g12-clkc.h
@@ -1,18 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * include/dt-bindings/clock/g12a-clkc.h
- *
- * Copyright (C) 2018 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef __DT_BINDINGS_CLOCK_G12A_H
diff --git a/include/dt-bindings/clock/s4-clkc.h b/include/dt-bindings/clock/s4-clkc.h
new file mode 100644
index 0000000..e521b38
--- /dev/null
+++ b/include/dt-bindings/clock/s4-clkc.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_S4_H
+#define __DT_BINDINGS_CLOCK_S4_H
+/*
+ * CLKID index values
+ */
+#define CLKID_XTAL 0
+#define CLKID_FIXED_PLL 1
+#define CLKID_FCLK_DIV2 2
+#define CLKID_FCLK_DIV3 3
+#define CLKID_FCLK_DIV5 4
+#define CLKID_FCLK_DIV7 5
+#define CLKID_FCLK_DIV2P5 6
+#define CLKID_FCLK_DIV4 7
+#define CLKID_SYS_CLK 8
+#define CLKID_SYS_PLL 9
+#define CLKID_SD_EMMC_A_XTAL_GATE 10
+#define CLKID_SD_EMMC_B_XTAL_GATE 11
+#define CLKID_SD_EMMC_C_XTAL_GATE 12
+
+
+#define CLKID_GATE_BASE 13
+#define CLKID_SPIFC_XTAL_GATE (CLKID_GATE_BASE + 0)
+#define CLKID_SPIFC_GATE (CLKID_GATE_BASE + 1)
+#define CLKID_SYS_SPIFC (CLKID_GATE_BASE + 2)
+#define CLKID_SAR_ADC_GATE (CLKID_GATE_BASE + 3)
+#define CLKID_SPICC_A_GATE (CLKID_GATE_BASE + 4)
+#define CLKID_SPICC_B_GATE (CLKID_GATE_BASE + 5)
+#define CLKID_SD_EMMC_B_GATE (CLKID_GATE_BASE + 6)
+#define CLKID_SD_EMMC_C_GATE (CLKID_GATE_BASE + 7)
+#define CLKID_SD_EMMC_A_GATE (CLKID_GATE_BASE + 8)
+
+#define CLKID_MUX_BASE (CLKID_GATE_BASE + 9)
+#define CLKID_SPIFC_MUX (CLKID_MUX_BASE + 0)
+#define CLKID_SARADC_MUX (CLKID_MUX_BASE + 1)
+#define CLKID_SPICC_A_MUX (CLKID_MUX_BASE + 2)
+#define CLKID_SPICC_B_MUX (CLKID_MUX_BASE + 3)
+#define CLKID_SD_EMMC_B_MUX (CLKID_MUX_BASE + 4)
+#define CLKID_SD_EMMC_C_MUX (CLKID_MUX_BASE + 5)
+#define CLKID_SD_EMMC_A_MUX (CLKID_MUX_BASE + 6)
+
+#define CLKID_DIV_BASE (CLKID_MUX_BASE + 7)
+#define CLKID_SPIFC_DIV (CLKID_DIV_BASE + 0)
+#define CLKID_SARADC_DIV (CLKID_DIV_BASE + 1)
+#define CLKID_SPICC_A_DIV (CLKID_DIV_BASE + 2)
+#define CLKID_SPICC_B_DIV (CLKID_DIV_BASE + 3)
+#define CLKID_SD_EMMC_B_DIV (CLKID_DIV_BASE + 4)
+#define CLKID_SD_EMMC_C_DIV (CLKID_DIV_BASE + 5)
+#define CLKID_SD_EMMC_A_DIV (CLKID_MUX_BASE + 6)
+
+/* CLKTREE_SYS_CLK_EN0 gates*/
+#define GATE_BASE0 (CLKID_DIV_BASE + 7)
+#define CLKID_CLKTREE (GATE_BASE0 + 0)
+#define CLKID_RESET_CTRL (GATE_BASE0 + 1)
+#define CLKID_ANALOG_CTRL (GATE_BASE0 + 2)
+#define CLKID_PWR_CTRL (GATE_BASE0 + 3)
+#define CLKID_PAD_CTRL (GATE_BASE0 + 4)
+#define CLKID_SYS_CTRL (GATE_BASE0 + 5)
+#define CLKID_TEMP_SENSOR (GATE_BASE0 + 6)
+#define CLKID_AM2AXI_DIV (GATE_BASE0 + 7)
+#define CLKID_SPICC_B (GATE_BASE0 + 8)
+#define CLKID_SPICC_A (GATE_BASE0 + 9)
+#define CLKID_CLK_MSR (GATE_BASE0 + 10)
+#define CLKID_AUDIO (GATE_BASE0 + 11)
+#define CLKID_JTAG_CTRL (GATE_BASE0 + 12)
+#define CLKID_SARADC (GATE_BASE0 + 13)
+#define CLKID_PWM_EF (GATE_BASE0 + 14)
+#define CLKID_PWM_CD (GATE_BASE0 + 15)
+#define CLKID_PWM_AB (GATE_BASE0 + 16)
+#define CLKID_CEC (GATE_BASE0 + 17)
+#define CLKID_I2C_S (GATE_BASE0 + 18)
+#define CLKID_IR_CTRL (GATE_BASE0 + 19)
+#define CLKID_I2C_M_D (GATE_BASE0 + 20)
+#define CLKID_I2C_M_C (GATE_BASE0 + 21)
+#define CLKID_I2C_M_B (GATE_BASE0 + 22)
+#define CLKID_I2C_M_A (GATE_BASE0 + 23)
+#define CLKID_ACODEC (GATE_BASE0 + 24)
+#define CLKID_OTP (GATE_BASE0 + 25)
+#define CLKID_SD_EMMC_A (GATE_BASE0 + 26)
+#define CLKID_USB_PHY (GATE_BASE0 + 27)
+#define CLKID_USB_CTRL (GATE_BASE0 + 28)
+#define CLKID_SYS_DSPB (GATE_BASE0 + 29)
+#define CLKID_SYS_DSPA (GATE_BASE0 + 30)
+#define CLKID_DMA (GATE_BASE0 + 31)
+/* CLKTREE_SYS_CLK_EN1 gates*/
+#define GATE_BASE1 (GATE_BASE0 + 32)
+#define CLKID_IRQ_CTRL (GATE_BASE1 + 0)
+#define CLKID_NIC (GATE_BASE1 + 1)
+#define CLKID_GIC (GATE_BASE1 + 2)
+#define CLKID_UART_C (GATE_BASE1 + 3)
+#define CLKID_UART_B (GATE_BASE1 + 4)
+#define CLKID_UART_A (GATE_BASE1 + 5)
+#define CLKID_SYS_PSRAM (GATE_BASE1 + 6)
+#define CLKID_RSA (GATE_BASE1 + 7)
+#define CLKID_CORESIGHT (GATE_BASE1 + 8)
+/* CLKTREE_AXI_CLK_EN gates */
+#define GATE_BASE2 (GATE_BASE1 + 9)
+#define CLKID_AM2AXI_VAD (GATE_BASE2 + 0)
+#define CLKID_AUDIO_VAD (GATE_BASE2 + 1)
+#define CLKID_AXI_DMC (GATE_BASE2 + 2)
+#define CLKID_AXI_PSRAM (GATE_BASE2 + 3)
+#define CLKID_RAMB (GATE_BASE2 + 4)
+#define CLKID_RAMA (GATE_BASE2 + 5)
+#define CLKID_AXI_SPIFC (GATE_BASE2 + 6)
+#define CLKID_AXI_NIC (GATE_BASE2 + 7)
+#define CLKID_AXI_DMA (GATE_BASE2 + 8)
+#define CLKID_CPU_CTRL (GATE_BASE2 + 9)
+#define CLKID_ROM (GATE_BASE2 + 10)
+#define CLKID_PROC_I2C (GATE_BASE2 + 11)
+
+#define CLKID_UNREALIZED 100
+
+#endif /* __S4_CLKC_H */
diff --git a/include/dt-bindings/clock/sc2-clkc.h b/include/dt-bindings/clock/sc2-clkc.h
new file mode 100644
index 0000000..4c8b1ee
--- /dev/null
+++ b/include/dt-bindings/clock/sc2-clkc.h
@@ -0,0 +1,117 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_SC2_H
+#define __DT_BINDINGS_CLOCK_SC2_H
+/*
+ * CLKID index values
+ */
+#define CLKID_XTAL 0
+#define CLKID_FIXED_PLL 1
+#define CLKID_FCLK_DIV2 2
+#define CLKID_FCLK_DIV3 3
+#define CLKID_FCLK_DIV5 4
+#define CLKID_FCLK_DIV7 5
+#define CLKID_FCLK_DIV2P5 6
+#define CLKID_FCLK_DIV4 7
+#define CLKID_SYS_CLK 8
+#define CLKID_SYS_PLL 9
+#define CLKID_SD_EMMC_A_XTAL_GATE 10
+#define CLKID_SD_EMMC_B_XTAL_GATE 11
+#define CLKID_SD_EMMC_C_XTAL_GATE 12
+
+
+#define CLKID_GATE_BASE 13
+#define CLKID_SPIFC_XTAL_GATE (CLKID_GATE_BASE + 0)
+#define CLKID_SPIFC_GATE (CLKID_GATE_BASE + 1)
+#define CLKID_SYS_SPIFC (CLKID_GATE_BASE + 2)
+#define CLKID_SAR_ADC_GATE (CLKID_GATE_BASE + 3)
+#define CLKID_SPICC_A_GATE (CLKID_GATE_BASE + 4)
+#define CLKID_SPICC_B_GATE (CLKID_GATE_BASE + 5)
+#define CLKID_SD_EMMC_B_GATE (CLKID_GATE_BASE + 6)
+#define CLKID_SD_EMMC_C_GATE (CLKID_GATE_BASE + 7)
+#define CLKID_SD_EMMC_A_GATE (CLKID_GATE_BASE + 8)
+
+#define CLKID_MUX_BASE (CLKID_GATE_BASE + 9)
+#define CLKID_SPIFC_MUX (CLKID_MUX_BASE + 0)
+#define CLKID_SARADC_MUX (CLKID_MUX_BASE + 1)
+#define CLKID_SPICC_A_MUX (CLKID_MUX_BASE + 2)
+#define CLKID_SPICC_B_MUX (CLKID_MUX_BASE + 3)
+#define CLKID_SD_EMMC_B_MUX (CLKID_MUX_BASE + 4)
+#define CLKID_SD_EMMC_C_MUX (CLKID_MUX_BASE + 5)
+#define CLKID_SD_EMMC_A_MUX (CLKID_MUX_BASE + 6)
+
+#define CLKID_DIV_BASE (CLKID_MUX_BASE + 7)
+#define CLKID_SPIFC_DIV (CLKID_DIV_BASE + 0)
+#define CLKID_SARADC_DIV (CLKID_DIV_BASE + 1)
+#define CLKID_SPICC_A_DIV (CLKID_DIV_BASE + 2)
+#define CLKID_SPICC_B_DIV (CLKID_DIV_BASE + 3)
+#define CLKID_SD_EMMC_B_DIV (CLKID_DIV_BASE + 4)
+#define CLKID_SD_EMMC_C_DIV (CLKID_DIV_BASE + 5)
+#define CLKID_SD_EMMC_A_DIV (CLKID_MUX_BASE + 6)
+
+/* CLKTREE_SYS_CLK_EN0 gates*/
+#define GATE_BASE0 (CLKID_DIV_BASE + 7)
+#define CLKID_CLKTREE (GATE_BASE0 + 0)
+#define CLKID_RESET_CTRL (GATE_BASE0 + 1)
+#define CLKID_ANALOG_CTRL (GATE_BASE0 + 2)
+#define CLKID_PWR_CTRL (GATE_BASE0 + 3)
+#define CLKID_PAD_CTRL (GATE_BASE0 + 4)
+#define CLKID_SYS_CTRL (GATE_BASE0 + 5)
+#define CLKID_TEMP_SENSOR (GATE_BASE0 + 6)
+#define CLKID_AM2AXI_DIV (GATE_BASE0 + 7)
+#define CLKID_SPICC_B (GATE_BASE0 + 8)
+#define CLKID_SPICC_A (GATE_BASE0 + 9)
+#define CLKID_CLK_MSR (GATE_BASE0 + 10)
+#define CLKID_AUDIO (GATE_BASE0 + 11)
+#define CLKID_JTAG_CTRL (GATE_BASE0 + 12)
+#define CLKID_SARADC (GATE_BASE0 + 13)
+#define CLKID_PWM_EF (GATE_BASE0 + 14)
+#define CLKID_PWM_CD (GATE_BASE0 + 15)
+#define CLKID_PWM_AB (GATE_BASE0 + 16)
+#define CLKID_CEC (GATE_BASE0 + 17)
+#define CLKID_I2C_S (GATE_BASE0 + 18)
+#define CLKID_IR_CTRL (GATE_BASE0 + 19)
+#define CLKID_I2C_M_D (GATE_BASE0 + 20)
+#define CLKID_I2C_M_C (GATE_BASE0 + 21)
+#define CLKID_I2C_M_B (GATE_BASE0 + 22)
+#define CLKID_I2C_M_A (GATE_BASE0 + 23)
+#define CLKID_ACODEC (GATE_BASE0 + 24)
+#define CLKID_OTP (GATE_BASE0 + 25)
+#define CLKID_SD_EMMC_A (GATE_BASE0 + 26)
+#define CLKID_USB_PHY (GATE_BASE0 + 27)
+#define CLKID_USB_CTRL (GATE_BASE0 + 28)
+#define CLKID_SYS_DSPB (GATE_BASE0 + 29)
+#define CLKID_SYS_DSPA (GATE_BASE0 + 30)
+#define CLKID_DMA (GATE_BASE0 + 31)
+/* CLKTREE_SYS_CLK_EN1 gates*/
+#define GATE_BASE1 (GATE_BASE0 + 32)
+#define CLKID_IRQ_CTRL (GATE_BASE1 + 0)
+#define CLKID_NIC (GATE_BASE1 + 1)
+#define CLKID_GIC (GATE_BASE1 + 2)
+#define CLKID_UART_C (GATE_BASE1 + 3)
+#define CLKID_UART_B (GATE_BASE1 + 4)
+#define CLKID_UART_A (GATE_BASE1 + 5)
+#define CLKID_SYS_PSRAM (GATE_BASE1 + 6)
+#define CLKID_RSA (GATE_BASE1 + 7)
+#define CLKID_CORESIGHT (GATE_BASE1 + 8)
+/* CLKTREE_AXI_CLK_EN gates */
+#define GATE_BASE2 (GATE_BASE1 + 9)
+#define CLKID_AM2AXI_VAD (GATE_BASE2 + 0)
+#define CLKID_AUDIO_VAD (GATE_BASE2 + 1)
+#define CLKID_AXI_DMC (GATE_BASE2 + 2)
+#define CLKID_AXI_PSRAM (GATE_BASE2 + 3)
+#define CLKID_RAMB (GATE_BASE2 + 4)
+#define CLKID_RAMA (GATE_BASE2 + 5)
+#define CLKID_AXI_SPIFC (GATE_BASE2 + 6)
+#define CLKID_AXI_NIC (GATE_BASE2 + 7)
+#define CLKID_AXI_DMA (GATE_BASE2 + 8)
+#define CLKID_CPU_CTRL (GATE_BASE2 + 9)
+#define CLKID_ROM (GATE_BASE2 + 10)
+#define CLKID_PROC_I2C (GATE_BASE2 + 11)
+
+#define CLKID_UNREALIZED 100
+
+#endif /* __SC2_CLKC_H */
diff --git a/include/dt-bindings/clock/t7-clkc.h b/include/dt-bindings/clock/t7-clkc.h
new file mode 100644
index 0000000..1b06250
--- /dev/null
+++ b/include/dt-bindings/clock/t7-clkc.h
@@ -0,0 +1,66 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_CLOCK_T7_H
+#define __DT_BINDINGS_CLOCK_T7_H
+/*
+ * CLKID index values
+ */
+#define CLKID_XTAL 0
+#define CLKID_FIXED_PLL 1
+#define CLKID_FCLK_DIV2 2
+#define CLKID_FCLK_DIV3 3
+#define CLKID_FCLK_DIV5 4
+#define CLKID_FCLK_DIV7 5
+#define CLKID_FCLK_DIV2P5 6
+#define CLKID_FCLK_DIV4 7
+#define CLKID_SYS_CLK 8
+#define CLKID_SYS_PLL 9
+#define CLKID_GP0_PLL 10
+#define CLKID_SD_EMMC_A_XTAL_GATE 11
+#define CLKID_SD_EMMC_B_XTAL_GATE 12
+#define CLKID_SD_EMMC_C_XTAL_GATE 13
+
+
+#define CLKID_GATE_BASE 14
+#define CLKID_SAR_ADC_GATE (CLKID_GATE_BASE + 0)
+#define CLKID_SPICC_A_GATE (CLKID_GATE_BASE + 1)
+#define CLKID_SPICC_B_GATE (CLKID_GATE_BASE + 2)
+#define CLKID_SPICC_C_GATE (CLKID_GATE_BASE + 3)
+#define CLKID_SPICC_D_GATE (CLKID_GATE_BASE + 4)
+#define CLKID_SPICC_E_GATE (CLKID_GATE_BASE + 5)
+#define CLKID_SPICC_F_GATE (CLKID_GATE_BASE + 6)
+#define CLKID_SD_EMMC_B_GATE (CLKID_GATE_BASE + 7)
+#define CLKID_SD_EMMC_C_GATE (CLKID_GATE_BASE + 8)
+#define CLKID_SD_EMMC_A_GATE (CLKID_GATE_BASE + 9)
+
+#define CLKID_MUX_BASE (CLKID_GATE_BASE + 10)
+#define CLKID_SARADC_MUX (CLKID_MUX_BASE + 0)
+#define CLKID_SPICC_A_MUX (CLKID_MUX_BASE + 1)
+#define CLKID_SPICC_B_MUX (CLKID_MUX_BASE + 2)
+#define CLKID_SPICC_C_MUX (CLKID_MUX_BASE + 3)
+#define CLKID_SPICC_D_MUX (CLKID_MUX_BASE + 4)
+#define CLKID_SPICC_E_MUX (CLKID_MUX_BASE + 5)
+#define CLKID_SPICC_F_MUX (CLKID_MUX_BASE + 6)
+#define CLKID_SD_EMMC_B_MUX (CLKID_MUX_BASE + 7)
+#define CLKID_SD_EMMC_C_MUX (CLKID_MUX_BASE + 8)
+#define CLKID_SD_EMMC_A_MUX (CLKID_MUX_BASE + 9)
+
+#define CLKID_DIV_BASE (CLKID_MUX_BASE + 10)
+#define CLKID_SARADC_DIV (CLKID_DIV_BASE + 0)
+#define CLKID_SPICC_A_DIV (CLKID_DIV_BASE + 1)
+#define CLKID_SPICC_B_DIV (CLKID_DIV_BASE + 2)
+#define CLKID_SPICC_C_DIV (CLKID_DIV_BASE + 3)
+#define CLKID_SPICC_D_DIV (CLKID_DIV_BASE + 4)
+#define CLKID_SPICC_E_DIV (CLKID_DIV_BASE + 5)
+#define CLKID_SPICC_F_DIV (CLKID_DIV_BASE + 6)
+#define CLKID_SD_EMMC_B_DIV (CLKID_DIV_BASE + 7)
+#define CLKID_SD_EMMC_C_DIV (CLKID_DIV_BASE + 8)
+#define CLKID_SD_EMMC_A_DIV (CLKID_MUX_BASE + 9)
+
+
+#define CLKID_UNREALIZED 100
+
+#endif /* __T7_CLKC_H */
diff --git a/include/dt-bindings/gpio/meson-a1-gpio.h b/include/dt-bindings/gpio/meson-a1-gpio.h
new file mode 100644
index 0000000..0255aa7
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-a1-gpio.h
@@ -0,0 +1,73 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_MESON_A1_GPIO_H
+#define _DT_BINDINGS_MESON_A1_GPIO_H
+
+#define GPIOP_0 0
+#define GPIOP_1 1
+#define GPIOP_2 2
+#define GPIOP_3 3
+#define GPIOP_4 4
+#define GPIOP_5 5
+#define GPIOP_6 6
+#define GPIOP_7 7
+#define GPIOP_8 8
+#define GPIOP_9 9
+#define GPIOP_10 10
+#define GPIOP_11 11
+#define GPIOP_12 12
+#define GPIOB_0 13
+#define GPIOB_1 14
+#define GPIOB_2 15
+#define GPIOB_3 16
+#define GPIOB_4 17
+#define GPIOB_5 18
+#define GPIOB_6 19
+#define GPIOX_0 20
+#define GPIOX_1 21
+#define GPIOX_2 22
+#define GPIOX_3 23
+#define GPIOX_4 24
+#define GPIOX_5 25
+#define GPIOX_6 26
+#define GPIOX_7 27
+#define GPIOX_8 28
+#define GPIOX_9 29
+#define GPIOX_10 30
+#define GPIOX_11 31
+#define GPIOX_12 32
+#define GPIOX_13 33
+#define GPIOX_14 34
+#define GPIOX_15 35
+#define GPIOX_16 36
+#define GPIOF_0 37
+#define GPIOF_1 38
+#define GPIOF_2 39
+#define GPIOF_3 40
+#define GPIOF_4 41
+#define GPIOF_5 42
+#define GPIOF_6 43
+#define GPIOF_7 44
+#define GPIOF_8 45
+#define GPIOF_9 46
+#define GPIOF_10 47
+#define GPIOF_11 48
+#define GPIOF_12 49
+#define GPIOA_0 50
+#define GPIOA_1 51
+#define GPIOA_2 52
+#define GPIOA_3 53
+#define GPIOA_4 54
+#define GPIOA_5 55
+#define GPIOA_6 56
+#define GPIOA_7 57
+#define GPIOA_8 58
+#define GPIOA_9 59
+#define GPIOA_10 60
+#define GPIOA_11 61
+
+#define GPIO_TEST_N 62
+#endif /* _DT_BINDINGS_MESON_A1_GPIO_H */
diff --git a/include/dt-bindings/gpio/meson-c1-gpio.h b/include/dt-bindings/gpio/meson-c1-gpio.h
new file mode 100644
index 0000000..11ffcd1
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-c1-gpio.h
@@ -0,0 +1,106 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_MESON_C1_GPIO_H
+#define _DT_BINDINGS_MESON_C1_GPIO_H
+
+#define GPIOD_0 0
+#define GPIOD_1 1
+#define GPIOD_2 2
+#define GPIOD_3 3
+#define GPIOD_4 4
+#define GPIOD_5 5
+#define GPIOD_6 6
+#define GPIOD_7 7
+#define GPIOD_8 8
+#define GPIOD_9 9
+#define GPIOD_10 10
+#define GPIOD_11 11
+#define GPIOD_12 12
+
+#define GPIOE_0 13
+#define GPIOE_1 14
+
+#define GPIOB_0 15
+#define GPIOB_1 16
+#define GPIOB_2 17
+#define GPIOB_3 18
+#define GPIOB_4 19
+#define GPIOB_5 20
+#define GPIOB_6 21
+#define GPIOB_7 22
+#define GPIOB_8 23
+#define GPIOB_9 24
+#define GPIOB_10 25
+#define GPIOB_11 26
+#define GPIOB_12 27
+#define GPIOB_13 28
+
+#define GPIOC_0 29
+#define GPIOC_1 30
+#define GPIOC_2 31
+#define GPIOC_3 32
+#define GPIOC_4 33
+#define GPIOC_5 34
+#define GPIOC_6 35
+#define GPIOC_7 36
+
+#define GPIOX_0 37
+#define GPIOX_1 38
+#define GPIOX_2 39
+#define GPIOX_3 40
+#define GPIOX_4 41
+#define GPIOX_5 42
+#define GPIOX_6 43
+#define GPIOX_7 44
+#define GPIOX_8 45
+#define GPIOX_9 46
+#define GPIOX_10 47
+#define GPIOX_11 48
+#define GPIOX_12 49
+#define GPIOX_13 50
+#define GPIOX_14 51
+#define GPIOX_15 52
+#define GPIOX_16 53
+#define GPIOX_17 54
+#define GPIOX_18 55
+#define GPIOX_19 56
+
+#define GPIOM_0 57
+#define GPIOM_1 58
+#define GPIOM_2 59
+#define GPIOM_3 60
+#define GPIOM_4 61
+#define GPIOM_5 62
+#define GPIOM_6 63
+#define GPIOM_7 64
+#define GPIOM_8 65
+#define GPIOM_9 66
+#define GPIOM_10 67
+#define GPIOM_11 68
+#define GPIOM_12 69
+#define GPIOM_13 70
+#define GPIOM_14 71
+#define GPIOM_15 72
+
+#define GPIOA_0 73
+#define GPIOA_1 74
+#define GPIOA_2 75
+#define GPIOA_3 76
+#define GPIOA_4 77
+#define GPIOA_5 78
+#define GPIOA_6 79
+#define GPIOA_7 80
+#define GPIOA_8 81
+#define GPIOA_9 82
+#define GPIOA_10 83
+#define GPIOA_11 84
+#define GPIOA_12 85
+#define GPIOA_13 86
+#define GPIOA_14 87
+#define GPIOA_15 88
+
+#define GPIO_TEST_N 89
+#endif /* _DT_BINDINGS_MESON_C1_GPIO_H */
diff --git a/include/dt-bindings/gpio/meson-c2-gpio.h b/include/dt-bindings/gpio/meson-c2-gpio.h
new file mode 100644
index 0000000..4f5e4eb
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-c2-gpio.h
@@ -0,0 +1,105 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_MESON_C2_GPIO_H
+#define _DT_BINDINGS_MESON_C2_GPIO_H
+#define GPIOD_0 0
+#define GPIOD_1 1
+#define GPIOD_2 2
+#define GPIOD_3 3
+#define GPIOD_4 4
+#define GPIOD_5 5
+#define GPIOD_6 6
+#define GPIOD_7 7
+#define GPIOD_8 8
+#define GPIOD_9 9
+#define GPIOD_10 10
+#define GPIOD_11 11
+#define GPIOD_12 12
+#define GPIOD_13 13
+
+#define GPIOE_0 14
+#define GPIOE_1 15
+#define GPIOE_2 16
+
+#define GPIOB_0 17
+#define GPIOB_1 18
+#define GPIOB_2 19
+#define GPIOB_3 20
+#define GPIOB_4 21
+#define GPIOB_5 22
+#define GPIOB_6 23
+#define GPIOB_7 24
+#define GPIOB_8 25
+#define GPIOB_9 26
+#define GPIOB_10 27
+#define GPIOB_11 28
+#define GPIOB_12 29
+#define GPIOB_13 30
+
+#define GPIOC_0 31
+#define GPIOC_1 32
+#define GPIOC_2 33
+#define GPIOC_3 34
+#define GPIOC_4 35
+#define GPIOC_5 36
+#define GPIOC_6 37
+
+#define GPIOX_0 38
+#define GPIOX_1 39
+#define GPIOX_2 40
+#define GPIOX_3 41
+#define GPIOX_4 42
+#define GPIOX_5 43
+#define GPIOX_6 44
+#define GPIOX_7 45
+#define GPIOX_8 46
+#define GPIOX_9 47
+#define GPIOX_10 48
+#define GPIOX_11 49
+#define GPIOX_12 50
+#define GPIOX_13 51
+#define GPIOX_14 52
+#define GPIOX_15 53
+#define GPIOX_16 54
+#define GPIOX_17 55
+#define GPIOX_18 56
+#define GPIOX_19 57
+#define GPIOX_20 58
+
+#define GPIOM_0 59
+#define GPIOM_1 60
+#define GPIOM_2 61
+#define GPIOM_3 62
+#define GPIOM_4 63
+#define GPIOM_5 64
+#define GPIOM_6 65
+#define GPIOM_7 66
+#define GPIOM_8 67
+#define GPIOM_9 68
+#define GPIOM_10 69
+#define GPIOM_11 70
+#define GPIOM_12 71
+#define GPIOM_13 72
+
+#define GPIOA_0 73
+#define GPIOA_1 74
+#define GPIOA_2 75
+#define GPIOA_3 76
+#define GPIOA_4 77
+#define GPIOA_5 78
+#define GPIOA_6 79
+#define GPIOA_7 80
+#define GPIOA_8 81
+#define GPIOA_9 82
+#define GPIOA_10 83
+#define GPIOA_11 84
+#define GPIOA_12 85
+#define GPIOA_13 86
+#define GPIOA_14 87
+#define GPIOA_15 88
+
+#define GPIO_TEST_N 89
+#endif /* _DT_BINDINGS_MESON_C2_GPIO_H */
diff --git a/include/dt-bindings/gpio/meson-g12a-gpio.h b/include/dt-bindings/gpio/meson-g12a-gpio.h
index 612eaef..1eeb81e 100644
--- a/include/dt-bindings/gpio/meson-g12a-gpio.h
+++ b/include/dt-bindings/gpio/meson-g12a-gpio.h
@@ -1,8 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * Copyright (c) 2017 Amlogic, Inc. All rights reserved.
- * Author: Xingyu Chen <xingyu.chen@amlogic.com>
- *
- * SPDX-License-Identifier: GPL-2.0+
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_MESON_G12A_GPIO_H
diff --git a/include/dt-bindings/gpio/meson-s4-gpio.h b/include/dt-bindings/gpio/meson-s4-gpio.h
new file mode 100644
index 0000000..533e248
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-s4-gpio.h
@@ -0,0 +1,97 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_MESON_S4_GPIO_H
+#define _DT_BINDINGS_MESON_S4_GPIO_H
+#define GPIOE_0 0
+#define GPIOE_1 1
+
+#define GPIOB_0 2
+#define GPIOB_1 3
+#define GPIOB_2 4
+#define GPIOB_3 5
+#define GPIOB_4 6
+#define GPIOB_5 7
+#define GPIOB_6 8
+#define GPIOB_7 9
+#define GPIOB_8 10
+#define GPIOB_9 11
+#define GPIOB_10 12
+#define GPIOB_11 13
+#define GPIOB_12 14
+#define GPIOB_13 15
+
+#define GPIOC_0 16
+#define GPIOC_1 17
+#define GPIOC_2 18
+#define GPIOC_3 19
+#define GPIOC_4 20
+#define GPIOC_5 21
+#define GPIOC_6 22
+#define GPIOC_7 23
+
+#define GPIOD_0 24
+#define GPIOD_1 25
+#define GPIOD_2 26
+#define GPIOD_3 27
+#define GPIOD_4 28
+#define GPIOD_5 29
+#define GPIOD_6 30
+#define GPIOD_7 31
+#define GPIOD_8 32
+#define GPIOD_9 33
+#define GPIOD_10 34
+#define GPIOD_11 35
+
+#define GPIOH_0 36
+#define GPIOH_1 37
+#define GPIOH_2 38
+#define GPIOH_3 39
+#define GPIOH_4 40
+#define GPIOH_5 41
+#define GPIOH_6 42
+#define GPIOH_7 43
+#define GPIOH_8 44
+#define GPIOH_9 45
+#define GPIOH_10 46
+#define GPIOH_11 47
+
+#define GPIOX_0 48
+#define GPIOX_1 49
+#define GPIOX_2 50
+#define GPIOX_3 51
+#define GPIOX_4 52
+#define GPIOX_5 53
+#define GPIOX_6 54
+#define GPIOX_7 55
+#define GPIOX_8 56
+#define GPIOX_9 57
+#define GPIOX_10 58
+#define GPIOX_11 59
+#define GPIOX_12 60
+#define GPIOX_13 61
+#define GPIOX_14 62
+#define GPIOX_15 63
+#define GPIOX_16 64
+#define GPIOX_17 65
+#define GPIOX_18 66
+#define GPIOX_19 67
+
+#define GPIOZ_0 68
+#define GPIOZ_1 69
+#define GPIOZ_2 70
+#define GPIOZ_3 71
+#define GPIOZ_4 72
+#define GPIOZ_5 73
+#define GPIOZ_6 74
+#define GPIOZ_7 75
+#define GPIOZ_8 76
+#define GPIOZ_9 77
+#define GPIOZ_10 78
+#define GPIOZ_11 79
+#define GPIOZ_12 80
+
+#define GPIO_TEST_N 81
+#endif /* _DT_BINDINGS_MESON_S4_GPIO_H */
diff --git a/include/dt-bindings/gpio/meson-sc2-gpio.h b/include/dt-bindings/gpio/meson-sc2-gpio.h
new file mode 100644
index 0000000..a674bfd
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-sc2-gpio.h
@@ -0,0 +1,103 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_MESON_SC2_GPIO_H
+#define _DT_BINDINGS_MESON_SC2_GPIO_H
+#define GPIOA_14 0
+#define GPIOA_15 1
+
+#define GPIOB_0 2
+#define GPIOB_1 3
+#define GPIOB_2 4
+#define GPIOB_3 5
+#define GPIOB_4 6
+#define GPIOB_5 7
+#define GPIOB_6 8
+#define GPIOB_7 9
+#define GPIOB_8 10
+#define GPIOB_9 11
+#define GPIOB_10 12
+#define GPIOB_11 13
+#define GPIOB_12 14
+#define GPIOB_13 15
+#define GPIOB_14 16
+#define GPIOB_15 17
+
+#define GPIOC_0 18
+#define GPIOC_1 19
+#define GPIOC_2 20
+#define GPIOC_3 21
+#define GPIOC_4 22
+#define GPIOC_5 23
+#define GPIOC_6 24
+#define GPIOC_7 25
+
+#define GPIOE_0 26
+#define GPIOE_1 27
+#define GPIOE_2 28
+
+#define GPIOD_0 29
+#define GPIOD_1 30
+#define GPIOD_2 31
+#define GPIOD_3 32
+#define GPIOD_4 33
+#define GPIOD_5 34
+#define GPIOD_6 35
+#define GPIOD_7 36
+#define GPIOD_8 37
+#define GPIOD_9 38
+#define GPIOD_10 39
+#define GPIOD_11 40
+
+#define GPIOH_0 41
+#define GPIOH_1 42
+#define GPIOH_2 43
+#define GPIOH_3 44
+#define GPIOH_4 45
+#define GPIOH_5 46
+#define GPIOH_6 47
+#define GPIOH_7 48
+#define GPIOH_8 49
+
+#define GPIOX_0 50
+#define GPIOX_1 51
+#define GPIOX_2 52
+#define GPIOX_3 53
+#define GPIOX_4 54
+#define GPIOX_5 55
+#define GPIOX_6 56
+#define GPIOX_7 57
+#define GPIOX_8 58
+#define GPIOX_9 59
+#define GPIOX_10 60
+#define GPIOX_11 61
+#define GPIOX_12 62
+#define GPIOX_13 63
+#define GPIOX_14 64
+#define GPIOX_15 65
+#define GPIOX_16 66
+#define GPIOX_17 67
+#define GPIOX_18 68
+#define GPIOX_19 69
+
+#define GPIOZ_0 70
+#define GPIOZ_1 71
+#define GPIOZ_2 72
+#define GPIOZ_3 73
+#define GPIOZ_4 74
+#define GPIOZ_5 75
+#define GPIOZ_6 76
+#define GPIOZ_7 77
+#define GPIOZ_8 78
+#define GPIOZ_9 79
+#define GPIOZ_10 80
+#define GPIOZ_11 81
+#define GPIOZ_12 82
+#define GPIOZ_13 83
+#define GPIOZ_14 84
+#define GPIOZ_15 85
+
+#define GPIO_TEST_N 86
+#endif /* _DT_BINDINGS_MESON_SC2_GPIO_H */
diff --git a/include/dt-bindings/gpio/meson-t7-gpio.h b/include/dt-bindings/gpio/meson-t7-gpio.h
new file mode 100644
index 0000000..646202a
--- /dev/null
+++ b/include/dt-bindings/gpio/meson-t7-gpio.h
@@ -0,0 +1,177 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef _DT_BINDINGS_MESON_T7_GPIO_H
+#define _DT_BINDINGS_MESON_T7_GPIO_H
+
+#define GPIOB_0 0
+#define GPIOB_1 1
+#define GPIOB_2 2
+#define GPIOB_3 3
+#define GPIOB_4 4
+#define GPIOB_5 5
+#define GPIOB_6 6
+#define GPIOB_7 7
+#define GPIOB_8 8
+#define GPIOB_9 9
+#define GPIOB_10 10
+#define GPIOB_11 11
+#define GPIOB_12 12
+
+#define GPIOC_0 13
+#define GPIOC_1 14
+#define GPIOC_2 15
+#define GPIOC_3 16
+#define GPIOC_4 17
+#define GPIOC_5 18
+#define GPIOC_6 19
+
+#define GPIOX_0 20
+#define GPIOX_1 21
+#define GPIOX_2 22
+#define GPIOX_3 23
+#define GPIOX_4 24
+#define GPIOX_5 25
+#define GPIOX_6 26
+#define GPIOX_7 27
+#define GPIOX_8 28
+#define GPIOX_9 29
+#define GPIOX_10 30
+#define GPIOX_11 31
+#define GPIOX_12 32
+#define GPIOX_13 33
+#define GPIOX_14 34
+#define GPIOX_15 35
+#define GPIOX_16 36
+#define GPIOX_17 37
+#define GPIOX_18 38
+#define GPIOX_19 39
+
+#define GPIOW_0 40
+#define GPIOW_1 41
+#define GPIOW_2 42
+#define GPIOW_3 43
+#define GPIOW_4 44
+#define GPIOW_5 45
+#define GPIOW_6 46
+#define GPIOW_7 47
+#define GPIOW_8 48
+#define GPIOW_9 49
+#define GPIOW_10 50
+#define GPIOW_11 51
+#define GPIOW_12 52
+#define GPIOW_13 53
+#define GPIOW_14 54
+#define GPIOW_15 55
+#define GPIOW_16 56
+
+#define GPIOD_0 57
+#define GPIOD_1 58
+#define GPIOD_2 59
+#define GPIOD_3 60
+#define GPIOD_4 61
+#define GPIOD_5 62
+#define GPIOD_6 63
+#define GPIOD_7 64
+#define GPIOD_8 65
+#define GPIOD_9 66
+#define GPIOD_10 67
+#define GPIOD_11 68
+#define GPIOD_12 69
+
+#define GPIOE_0 70
+#define GPIOE_1 71
+#define GPIOE_2 72
+#define GPIOE_3 73
+#define GPIOE_4 74
+#define GPIOE_5 75
+#define GPIOE_6 76
+
+#define GPIOZ_0 77
+#define GPIOZ_1 78
+#define GPIOZ_2 79
+#define GPIOZ_3 80
+#define GPIOZ_4 81
+#define GPIOZ_5 82
+#define GPIOZ_6 83
+#define GPIOZ_7 84
+#define GPIOZ_8 85
+#define GPIOZ_9 86
+#define GPIOZ_10 87
+#define GPIOZ_11 88
+#define GPIOZ_12 89
+#define GPIOZ_13 90
+
+#define GPIOT_0 91
+#define GPIOT_1 92
+#define GPIOT_2 93
+#define GPIOT_3 94
+#define GPIOT_4 95
+#define GPIOT_5 96
+#define GPIOT_6 97
+#define GPIOT_7 98
+#define GPIOT_8 99
+#define GPIOT_9 100
+#define GPIOT_10 101
+#define GPIOT_11 102
+#define GPIOT_12 103
+#define GPIOT_13 104
+#define GPIOT_14 105
+#define GPIOT_15 106
+#define GPIOT_16 107
+#define GPIOT_17 108
+#define GPIOT_18 109
+#define GPIOT_19 110
+#define GPIOT_20 111
+#define GPIOT_21 112
+#define GPIOT_22 113
+#define GPIOT_23 114
+
+#define GPIOM_0 115
+#define GPIOM_1 116
+#define GPIOM_2 117
+#define GPIOM_3 118
+#define GPIOM_4 119
+#define GPIOM_5 120
+#define GPIOM_6 121
+#define GPIOM_7 122
+#define GPIOM_8 123
+#define GPIOM_9 124
+#define GPIOM_10 125
+#define GPIOM_11 126
+#define GPIOM_12 127
+#define GPIOM_13 128
+
+#define GPIOY_0 129
+#define GPIOY_1 130
+#define GPIOY_2 131
+#define GPIOY_3 132
+#define GPIOY_4 133
+#define GPIOY_5 134
+#define GPIOY_6 135
+#define GPIOY_7 136
+#define GPIOY_8 137
+#define GPIOY_9 138
+#define GPIOY_10 139
+#define GPIOY_11 140
+#define GPIOY_12 141
+#define GPIOY_13 142
+#define GPIOY_14 143
+#define GPIOY_15 144
+#define GPIOY_16 145
+#define GPIOY_17 146
+#define GPIOY_18 147
+
+#define GPIOH_0 148
+#define GPIOH_1 149
+#define GPIOH_2 150
+#define GPIOH_3 151
+#define GPIOH_4 152
+#define GPIOH_5 153
+#define GPIOH_6 154
+#define GPIOH_7 155
+
+#define GPIO_TEST_N 156
+#endif /* _DT_BINDINGS_MESON_T7_GPIO_H */
diff --git a/include/dt-bindings/i2c/meson-i2c.h b/include/dt-bindings/i2c/meson-i2c.h
index 09ee3d6..420ef9c 100644
--- a/include/dt-bindings/i2c/meson-i2c.h
+++ b/include/dt-bindings/i2c/meson-i2c.h
@@ -1,9 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * This header provides constants for MESON SoCs I2c bindings.
- *
- * This file is licensed under the terms of the GNU General Public
- * License version 2. This program is licensed "as is" without any
- * warranty of any kind, whether express or implied.
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_MESON_I2C_H
diff --git a/include/dt-bindings/input/meson_rc.h b/include/dt-bindings/input/meson_rc.h
index c572dba..ad1a3a2 100644
--- a/include/dt-bindings/input/meson_rc.h
+++ b/include/dt-bindings/input/meson_rc.h
@@ -1,9 +1,11 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef _DT_BINDINGS_INPUT_MESON_RC_H
#define _DT_BINDINGS_INPUT_MESON_RC_H
-#define REMOTE_KEY(scancode, keycode)\
- ((((scancode) & 0xFFFF)<<16) | ((keycode) & 0xFFFF))
/**
*GXM GXL GXTVBB TXL platform integrated with two IR controllers.
*1. legacy IR contoller(Only support NEC and Time Measurement)
@@ -21,6 +23,9 @@
#define REMOTE_TYPE_XMP_1 0x03
#define REMOTE_TYPE_RC5 0x04
#define REMOTE_TYPE_RC6 0x05
+#define REMOTE_TYPE_TOSHIBA 0x06
+#define REMOTE_TYPE_RCA 0x08
+#define REMOTE_TYPE_RCMM 0x0a
/*hardware decode one protocol by using legacy IR controller*/
#define REMOTE_TYPE_LEGACY_NEC 0xff
@@ -39,5 +44,10 @@
*2. multi-format IR controller decode other protocol
*/
#define REMOTE_TYPE_NEC_RC6 ((REMOTE_TYPE_LEGACY_NEC << 8) | REMOTE_TYPE_RC6)
+#define REMOTE_TYPE_NEC_RC5 ((REMOTE_TYPE_LEGACY_NEC << 8) | REMOTE_TYPE_RC5)
+#define REMOTE_TYPE_NEC_TOSHIBA ((REMOTE_TYPE_LEGACY_NEC << 8) | \
+ REMOTE_TYPE_TOSHIBA)
+#define REMOTE_TYPE_NEC_RCA ((REMOTE_TYPE_LEGACY_NEC << 8) | REMOTE_TYPE_RCA)
+#define REMOTE_TYPE_NEC_RCMM ((REMOTE_TYPE_LEGACY_NEC << 8) | REMOTE_TYPE_RCMM)
#endif
diff --git a/include/dt-bindings/phy/phy-amlogic-pcie.h b/include/dt-bindings/phy/phy-amlogic-pcie.h
index adf66c9..c57c22e 100644
--- a/include/dt-bindings/phy/phy-amlogic-pcie.h
+++ b/include/dt-bindings/phy/phy-amlogic-pcie.h
@@ -1,10 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- *
- * This header provides constants for the AMLOGIC PCIE phy
- *
- * Copyright (C) 2017 AMLOGIC.INC
- * Author: Yue Wang <yue.wang@amlogic.com>
- * License terms: GNU General Public License (GPL), version 2
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef _DT_AMLOGIC_PCIE_PHY
diff --git a/include/dt-bindings/pwm/meson.h b/include/dt-bindings/pwm/meson.h
index 1dd7151..c0d71ca 100644
--- a/include/dt-bindings/pwm/meson.h
+++ b/include/dt-bindings/pwm/meson.h
@@ -1,18 +1,6 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
/*
- * include/dt-bindings/pwm/meson.h
- *
- * Copyright (C) 2017 Amlogic, Inc. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; either version 2 of the License, or
- * (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful, but WITHOUT
- * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
- * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
- * more details.
- *
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
*/
#ifndef _DT_BINDINGS_PWM_MESON_H
diff --git a/include/dt-bindings/usb/pd.h b/include/dt-bindings/usb/pd.h
new file mode 100644
index 0000000..985f2bb
--- /dev/null
+++ b/include/dt-bindings/usb/pd.h
@@ -0,0 +1,88 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+#ifndef __DT_POWER_DELIVERY_H
+#define __DT_POWER_DELIVERY_H
+
+/* Power delivery Power Data Object definitions */
+#define PDO_TYPE_FIXED 0
+#define PDO_TYPE_BATT 1
+#define PDO_TYPE_VAR 2
+#define PDO_TYPE_APDO 3
+
+#define PDO_TYPE_SHIFT 30
+#define PDO_TYPE_MASK 0x3
+
+#define PDO_TYPE(t) ((t) << PDO_TYPE_SHIFT)
+
+#define PDO_VOLT_MASK 0x3ff
+#define PDO_CURR_MASK 0x3ff
+#define PDO_PWR_MASK 0x3ff
+
+#define PDO_FIXED_DUAL_ROLE (1 << 29) /* Power role swap supported */
+#define PDO_FIXED_SUSPEND (1 << 28) /* USB Suspend supported (Source) */
+#define PDO_FIXED_HIGHER_CAP (1 << 28) /* Requires more than vSafe5V (Sink) */
+#define PDO_FIXED_EXTPOWER (1 << 27) /* Externally powered */
+#define PDO_FIXED_USB_COMM (1 << 26) /* USB communications capable */
+#define PDO_FIXED_DATA_SWAP (1 << 25) /* Data role swap supported */
+#define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */
+#define PDO_FIXED_CURR_SHIFT 0 /* 10mA units */
+
+#define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT)
+#define PDO_FIXED_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT)
+
+#define PDO_FIXED(mv, ma, flags) \
+ (PDO_TYPE(PDO_TYPE_FIXED) | (flags) | \
+ PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma))
+
+#define VSAFE5V 5000 /* mv units */
+
+#define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */
+#define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */
+#define PDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */
+
+#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT)
+#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT)
+#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT)
+
+#define PDO_BATT(min_mv, max_mv, max_mw) \
+ (PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) | \
+ PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw))
+
+#define PDO_VAR_MAX_VOLT_SHIFT 20 /* 50mV units */
+#define PDO_VAR_MIN_VOLT_SHIFT 10 /* 50mV units */
+#define PDO_VAR_MAX_CURR_SHIFT 0 /* 10mA units */
+
+#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT)
+#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT)
+#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT)
+
+#define PDO_VAR(min_mv, max_mv, max_ma) \
+ (PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) | \
+ PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma))
+
+#define APDO_TYPE_PPS 0
+
+#define PDO_APDO_TYPE_SHIFT 28 /* Only valid value currently is 0x0 - PPS */
+#define PDO_APDO_TYPE_MASK 0x3
+
+#define PDO_APDO_TYPE(t) ((t) << PDO_APDO_TYPE_SHIFT)
+
+#define PDO_PPS_APDO_MAX_VOLT_SHIFT 17 /* 100mV units */
+#define PDO_PPS_APDO_MIN_VOLT_SHIFT 8 /* 100mV units */
+#define PDO_PPS_APDO_MAX_CURR_SHIFT 0 /* 50mA units */
+
+#define PDO_PPS_APDO_VOLT_MASK 0xff
+#define PDO_PPS_APDO_CURR_MASK 0x7f
+
+#define PDO_PPS_APDO_MIN_VOLT(mv) \
+ ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MIN_VOLT_SHIFT)
+#define PDO_PPS_APDO_MAX_VOLT(mv) \
+ ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MAX_VOLT_SHIFT)
+#define PDO_PPS_APDO_MAX_CURR(ma) \
+ ((((ma) / 50) & PDO_PPS_APDO_CURR_MASK) << PDO_PPS_APDO_MAX_CURR_SHIFT)
+
+#define PDO_PPS_APDO(min_mv, max_mv, max_ma) \
+ (PDO_TYPE(PDO_TYPE_APDO) | PDO_APDO_TYPE(APDO_TYPE_PPS) | \
+ PDO_PPS_APDO_MIN_VOLT(min_mv) | PDO_PPS_APDO_MAX_VOLT(max_mv) | \
+ PDO_PPS_APDO_MAX_CURR(max_ma))
+
+ #endif /* __DT_POWER_DELIVERY_H */
diff --git a/include/emmc_partitions.h b/include/emmc_partitions.h
index e8f4bc5..ef2634f 100644
--- a/include/emmc_partitions.h
+++ b/include/emmc_partitions.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef _AML_MMC_H
#define _AML_MMC_H
@@ -41,6 +46,9 @@
#define MMC_BOTTOM_RSV_SIZE (0)
#endif /* CONFIG_AML_MMC_INHERENT_PART */
+#define MMC_FREERTOS_NAME "rtos-0"
+#define MMC_NBG_NAME "NBG"
+
#define MMC_CACHE_NAME "cache"
// #define MMC_CACHE_SIZE (512*SZ_1M) // this is not used and should be get from spl
@@ -52,9 +60,10 @@
#define EMMCKEY_RESERVE_OFFSET (0x4000)
#define MMC_RESERVED_OFFSET (36*SZ_1M)
#define MMC_BLOCK_SIZE (512)
+#define KEY_COPIES (2)
// #define MMC_SECURE_NAME "secure"
// #define MMC_SECURE_SIZE (0x1*SZ_1M)
-//
+
#define MMC_DDR_PARAMETER_NAME "ddr-parameter"
#define DDR_PARAMETER_OFFSET (SZ_1M * 8)
#define DDR_PARAMETER_SIZE (4 * 512)
@@ -91,6 +100,19 @@
#define CALI_PATTERN_OFFSET (SZ_1M * 3)
#define CALI_PATTERN_SIZE (256 * 512)
#define CALI_BLOCK_SIZE (512)
+#define CALI_PATTERN (0x55aa55aa)
+
+#define MMC_MAGIC_NAME "magic"
+#define MAGIC_OFFSET (SZ_1M * 6)
+#define MAGIC_SIZE (256 * 512)
+#define MAGIC_BLOCK_SIZE (512)
+#define MAGIC_PATTERN (0X00FF00FF)
+
+#define MMC_RANDOM_NAME "random"
+#define RANDOM_OFFSET (SZ_1M * 7)
+#define RANDOM_SIZE (256 * 512)
+#define RANDOM_BLOCK_SIZE (512)
+#define RANDOM_PATTERN (0X52414E44)
/*
* 2 copies dtb were stored in dtb area.
* each is 256K.
@@ -122,6 +144,12 @@
#define VIRTUAL_PARTITION_ELEMENT(na, of, sz) {.name = na, .offset = of, .size = sz,}
+struct aml_pattern {
+ char name[MAX_MMC_PART_NAME_LEN];
+ unsigned int pattern;
+};
+#define AML_PATTERN_ELEMENT(na, pa) {.name = na, .pattern = pa,}
+
#ifdef AML_MMC_DBG
#define aml_mmc_dbg(fmt, ...) printk( "%s: line:%d " fmt "\n", \
__func__, __LINE__, ##__VA_ARGS__)
@@ -194,14 +222,15 @@
#define LOCK_MAJOR_VERSION 1
#define LOCK_MINOR_VERSION 0
-#define LOCK_DATA_SIZE 8
+#define LOCK_DATA_SIZE 16
typedef struct LockData {
uint8_t version_major;
uint8_t version_minor;
+ uint8_t unlock_ability;
/* Padding to eight bytes. */
- uint8_t reserved1[2];
+ uint8_t reserved1;
/* 0: unlock 1: lock*/
uint8_t lock_state;
@@ -224,6 +253,8 @@
} FastbootContext_t;
extern bool is_partition_checked;
+extern struct partitions *part_table;
+extern int parts_total_num;
extern struct partitions emmc_partition_table[];
extern int get_emmc_partition_arraysize(void);
@@ -235,6 +266,10 @@
* >= 0 means valid partition
*/
extern int get_partition_num_by_name(char const *name);
+extern int aml_gpt_valid(struct mmc *mmc);
+int mmc_gpt_read(void *source);
+int mmc_gpt_write(void *source);
+int mmc_gpt_erase(void);
struct partitions* find_mmc_partition_by_name (char const *name);
struct partitions *aml_get_partition_by_name(const char *name);
@@ -242,6 +277,7 @@
struct virtual_partition *aml_get_virtual_partition_by_name(const char *name);
bool aml_is_emmc_tsd (struct mmc *mmc);
int mmc_device_init (struct mmc *mmc);
+int get_ept_from_gpt(struct mmc *mmc);
#define PARTITION_ELEMENT(na, sz, flags) {.name = na, .size = sz, .mask_flags = flags,}
diff --git a/include/emmc_storage.h b/include/emmc_storage.h
index bd6b63a..51973b3 100644
--- a/include/emmc_storage.h
+++ b/include/emmc_storage.h
@@ -1,14 +1,12 @@
-/***********************************************
-*****Storage config of board, for ACS use.*****
-***********************************************/
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
#ifndef __STORAGE_H
#define __STORAGE_H
#include <linux/types.h>
-#ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY
-#include <uuid.h>
-#endif
#include <asm/arch/romboot.h>
#ifndef __ASSEMBLY__
@@ -55,15 +53,6 @@
uint64_t size; /* partition size */
uint64_t offset; /* offset within the master space */
unsigned mask_flags; /* master flags to mask out for this partition */
-#ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY
-#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
- efi_guid_t uuid; /* filesystem UUID as string, if exists */
-#endif
-#ifdef CONFIG_PARTITION_TYPE_GUID
- efi_guid_t type_guid; /* type GUID as string, if exists */
-#endif
- gpt_entry_attributes attributes;
-#endif
};
struct config_nand {
diff --git a/include/environment.h b/include/environment.h
index 7da1291..1a0b528 100644
--- a/include/environment.h
+++ b/include/environment.h
@@ -198,6 +198,7 @@
ENVL_REMOTE,
ENVL_SPI_FLASH,
ENVL_UBI,
+ ENVL_STORAGE,
ENVL_NOWHERE,
ENVL_COUNT,
diff --git a/include/ext4fs.h b/include/ext4fs.h
index bed4bee..bb55639 100644
--- a/include/ext4fs.h
+++ b/include/ext4fs.h
@@ -116,12 +116,6 @@
struct blk_desc *dev_desc;
};
-struct ext_block_cache {
- char *buf;
- lbaint_t block;
- int size;
-};
-
extern struct ext2_data *ext4fs_root;
extern struct ext2fs_node *ext4fs_file;
@@ -151,15 +145,11 @@
void ext4fs_free_node(struct ext2fs_node *node, struct ext2fs_node *currroot);
int ext4fs_devread(lbaint_t sector, int byte_offset, int byte_len, char *buf);
void ext4fs_set_blk_dev(struct blk_desc *rbdd, disk_partition_t *info);
-long int read_allocated_block(struct ext2_inode *inode, int fileblock,
- struct ext_block_cache *cache);
+long int read_allocated_block(struct ext2_inode *inode, int fileblock);
int ext4fs_probe(struct blk_desc *fs_dev_desc,
disk_partition_t *fs_partition);
int ext4_read_file(const char *filename, void *buf, loff_t offset, loff_t len,
loff_t *actread);
int ext4_read_superblock(char *buffer);
int ext4fs_uuid(char *uuid_str);
-void ext_cache_init(struct ext_block_cache *cache);
-void ext_cache_fini(struct ext_block_cache *cache);
-int ext_cache_read(struct ext_block_cache *cache, lbaint_t block, int size);
#endif
diff --git a/include/fastboot.h b/include/fastboot.h
index 1933b1d..68338e4 100644
--- a/include/fastboot.h
+++ b/include/fastboot.h
@@ -12,31 +12,40 @@
#ifndef _FASTBOOT_H_
#define _FASTBOOT_H_
+#include <android_vab.h>
+
#define FASTBOOT_VERSION "0.4"
/* The 64 defined bytes plus \0 */
#define FASTBOOT_COMMAND_LEN (64 + 1)
#define FASTBOOT_RESPONSE_LEN (64 + 1)
+extern int busy_flag;
+
/**
* All known commands to fastboot
*/
enum {
FASTBOOT_COMMAND_GETVAR = 0,
FASTBOOT_COMMAND_DOWNLOAD,
+#if !CONFIG_IS_ENABLED(NO_FASTBOOT_FLASHING)
+ FASTBOOT_COMMAND_FLASHING,
+#endif// #if !CONFIG_IS_ENABLED(NO_FASTBOOT_FLASHING)
#if CONFIG_IS_ENABLED(FASTBOOT_FLASH)
FASTBOOT_COMMAND_FLASH,
FASTBOOT_COMMAND_ERASE,
#endif
FASTBOOT_COMMAND_BOOT,
FASTBOOT_COMMAND_CONTINUE,
- FASTBOOT_COMMAND_REBOOT,
FASTBOOT_COMMAND_REBOOT_BOOTLOADER,
+ FASTBOOT_COMMAND_REBOOT_FASTBOOT,
+ FASTBOOT_COMMAND_REBOOT,
FASTBOOT_COMMAND_SET_ACTIVE,
+ FASTBOOT_COMMAND_SNAOSHOT_UPDATE,
#if CONFIG_IS_ENABLED(FASTBOOT_CMD_OEM_FORMAT)
FASTBOOT_COMMAND_OEM_FORMAT,
#endif
-
+ FASTBOOT_COMMAND_OEM,
FASTBOOT_COMMAND_COUNT
};
@@ -60,6 +69,14 @@
void fastboot_fail(const char *reason, char *response);
/**
+ * fastboot_busy() - Write a INFO response of the form "INFO$reason".
+ *
+ * @reason: Pointer to returned reason string
+ * @response: Pointer to fastboot response buffer
+ */
+void fastboot_busy(const char *reason, char *response);
+
+/**
* fastboot_okay() - Write an OKAY response of the form "OKAY$reason".
*
* @reason: Pointer to returned reason string, or NULL to send a bare "OKAY"
@@ -68,6 +85,23 @@
void fastboot_okay(const char *reason, char *response);
/**
+ *check lock state
+ *return 1 if locked
+ *return 0 if unlocked
+ */
+int check_lock(void);
+
+/**
+ *get merge status
+*/
+int get_mergestatus(struct misc_virtual_ab_message *message);
+
+/**
+ *set merge status
+*/
+int set_mergestatus_cancel(struct misc_virtual_ab_message *message);
+
+/**
* fastboot_set_reboot_flag() - Set flag to indicate reboot-bootloader
*
* Set flag which indicates that we should reboot into the bootloader
diff --git a/include/g_dnl.h b/include/g_dnl.h
index 6d461c7..74cd9e0 100644
--- a/include/g_dnl.h
+++ b/include/g_dnl.h
@@ -43,5 +43,6 @@
void g_dnl_trigger_detach(void);
void g_dnl_clear_detach(void);
int run_usb_dnl_gadget(int usbctrl_index, char *usb_dnl_gadget);
+void dwc_otg_power_off_phy_fb(void);
#endif /* __G_DOWNLOAD_H_ */
diff --git a/include/generic-phy.h b/include/generic-phy.h
index 25ffde5..a0f1eb3 100644
--- a/include/generic-phy.h
+++ b/include/generic-phy.h
@@ -121,6 +121,7 @@
*/
int (*power_off)(struct phy *phy);
int (*tuning)(struct phy *phy, int port);
+ int (*getinfo)(struct phy *phy);
};
#ifdef CONFIG_PHY
@@ -223,6 +224,7 @@
*/
int generic_phy_get_by_name(struct udevice *user, const char *phy_name,
struct phy *phy);
+int generic_phy_getinfo(struct phy *phy);
#else /* CONFIG_PHY */
diff --git a/include/image-android-dt.h b/include/image-android-dt.h
index 9a3aa8f..92e21c0 100644
--- a/include/image-android-dt.h
+++ b/include/image-android-dt.h
@@ -10,6 +10,7 @@
#include <linux/types.h>
bool android_dt_check_header(ulong hdr_addr);
+u32 android_dt_get_totalsize(ulong hdr_addr);
bool android_dt_get_fdt_by_index(ulong hdr_addr, u32 index, ulong *addr,
u32 *size);
diff --git a/include/image.h b/include/image.h
index c9f7f52..2027f01 100644
--- a/include/image.h
+++ b/include/image.h
@@ -38,9 +38,6 @@
#define IMAGE_ENABLE_IGNORE 0
#define IMAGE_INDENT_STRING ""
-/* amlogic image debug config*/
-#define CONFIG_AML_IMAGE_DEBUG 0
-
#else
#include <lmb.h>
@@ -116,9 +113,6 @@
# define IMAGE_OF_SYSTEM_SETUP 0
#endif
-/* An invalid size, meaning that the image size is not known */
-#define IMAGE_SIZE_INVAL (-1UL)
-
enum ih_category {
IH_ARCH,
IH_COMP,
@@ -160,10 +154,9 @@
IH_OS_INTEGRITY, /* INTEGRITY */
IH_OS_OSE, /* OSE */
IH_OS_PLAN9, /* Plan 9 */
- IH_OS_OPENRTOS, /* OpenRTOS */
- IH_OS_ARM_TRUSTED_FIRMWARE, /* ARM Trusted Firmware */
+ IH_OS_OPENRTOS, /* OpenRTOS */
+ IH_OS_ARM_TRUSTED_FIRMWARE, /* ARM Trusted Firmware */
IH_OS_TEE, /* Trusted Execution Environment */
- IH_OS_ZIRCON, /* Zircon */
IH_OS_COUNT,
};
@@ -573,7 +566,6 @@
#endif
#define IMAGE_FORMAT_FIT 0x02 /* new, libfdt based format */
#define IMAGE_FORMAT_ANDROID 0x03 /* Android boot image */
-#define IMAGE_FORMAT_ZIRCON 0x04 /* Zircon boot image */
ulong genimg_get_kernel_addr_fit(char * const img_addr,
const char **fit_uname_config,
@@ -911,14 +903,12 @@
#define FIT_IMAGES_PATH "/images"
#define FIT_CONFS_PATH "/configurations"
-/* hash/signature/key node */
+/* hash/signature node */
#define FIT_HASH_NODENAME "hash"
#define FIT_ALGO_PROP "algo"
#define FIT_VALUE_PROP "value"
#define FIT_IGNORE_PROP "uboot-ignore"
#define FIT_SIG_NODENAME "signature"
-#define FIT_KEY_REQUIRED "required"
-#define FIT_KEY_HINT "key-name-hint"
/* image node */
#define FIT_DATA_PROP "data"
@@ -1052,23 +1042,7 @@
int fit_image_check_arch(const void *fit, int noffset, uint8_t arch);
int fit_image_check_type(const void *fit, int noffset, uint8_t type);
int fit_image_check_comp(const void *fit, int noffset, uint8_t comp);
-
-/**
- * fit_check_format() - Check that the FIT is valid
- *
- * This performs various checks on the FIT to make sure it is suitable for
- * use, looking for mandatory properties, nodes, etc.
- *
- * If FIT_FULL_CHECK is enabled, it also runs it through libfdt to make
- * sure that there are no strange tags or broken nodes in the FIT.
- *
- * @fit: pointer to the FIT format image header
- * @return 0 if OK, -ENOEXEC if not an FDT file, -EINVAL if the full FDT check
- * failed (e.g. due to bad structure), -ENOMSG if the description is
- * missing, -ENODATA if the timestamp is missing, -ENOENT if the /images
- * path is missing
- */
-int fit_check_format(const void *fit, ulong size);
+int fit_check_format(const void *fit);
int fit_conf_find_compat(const void *fit, const void *fdt);
int fit_conf_get_node(const void *fit, const char *conf_uname);
@@ -1328,19 +1302,22 @@
#endif /* CONFIG_FIT */
#if defined(CONFIG_ANDROID_BOOT_IMAGE)
-struct andr_img_hdr;
-int android_image_check_header(const struct andr_img_hdr *hdr);
-int android_image_get_kernel(const struct andr_img_hdr *hdr, int verify,
- ulong *os_data, ulong *os_len);
-int android_image_get_ramdisk(const struct andr_img_hdr *hdr,
- ulong *rd_data, ulong *rd_len);
-int android_image_get_second(const struct andr_img_hdr *hdr,
+#include <android_image.h>
+int android_image_check_header(const boot_img_hdr_t *hdr);
+int android_image_get_kernel(const boot_img_hdr_t *hdr,int verify,ulong *os_data, ulong *os_len);
+int android_image_get_ramdisk(const boot_img_hdr_t *hdr,ulong *rd_data, ulong *rd_len);
+ulong android_image_get_end(const boot_img_hdr_t *hdr);
+ulong android_image_get_kload(const boot_img_hdr_t *hdr);
+ulong android_image_get_comp(const boot_img_hdr_t *hdr);
+int android_image_need_move(ulong *img_addr,const boot_img_hdr_t *hdr);
+int android_image_get_second(const boot_img_hdr_t *hdr,
ulong *second_data, ulong *second_len);
-ulong android_image_get_end(const struct andr_img_hdr *hdr);
-ulong android_image_get_kload(const struct andr_img_hdr *hdr);
-void android_print_contents(const struct andr_img_hdr *hdr);
-ulong android_image_get_comp(const struct andr_img_hdr *hdr);
-int android_image_need_move(ulong *img_addr,const struct andr_img_hdr *hdr);
+void android_print_contents(const boot_img_hdr_t *hdr);
+int is_android_r_image(void *img_addr);
+
+/*android R*/
+int android_image_get_ramdisk_v3(const boot_img_hdr_v3_t *hdr, ulong *rd_data, ulong *rd_len);
+int vendor_boot_image_check_header(const vendor_boot_img_hdr_t * hdr);
#endif /* CONFIG_ANDROID_BOOT_IMAGE */
@@ -1423,14 +1400,4 @@
.handler = _handler, \
}
-#if defined(CONFIG_ZIRCON_BOOT_IMAGE)
-struct andr_img_hdr;
-int zircon_image_check_header(const void *hdr);
-int zircon_image_get_kernel(const void *hdr, int verify,
- ulong *os_data, ulong *os_len);
-ulong zircon_image_get_end(const void *hdr);
-ulong zircon_image_get_kload(const void *hdr);
-ulong zircon_image_get_comp(const void *hdr);
-#endif /* CONFIG_ZIRCON_BOOT_IMAGE */
-
#endif /* __IMAGE_H__ */
diff --git a/include/led.h b/include/led.h
index 7bfdddf..4dc923a 100644
--- a/include/led.h
+++ b/include/led.h
@@ -32,6 +32,10 @@
#ifdef CONFIG_LED_BLINK
LEDST_BLINK,
#endif
+#ifdef CONFIG_AML_LED_PWM
+ LEDST_SET_BRIGHTNESS,
+ LEDST_GET_BRIGHTNESS,
+#endif
LEDST_COUNT,
};
@@ -67,6 +71,27 @@
*/
int (*set_period)(struct udevice *dev, int period_ms);
#endif
+#ifdef CONFIG_AML_LED_PWM
+ /**
+ * set_brightness() - set the brightness of an LED
+ *
+ *
+ * @dev: LED device to change
+ * @brightness: LED brightness
+ * @return 0 if OK, -ve on error
+ */
+ int (*set_brightness)(struct udevice *dev, int brightness);
+ /**
+ * get_brightness() - get the brightness of an LED
+ *
+ * Thie records the period if supported, or returns -ENOSYS if not.
+ * To start the LED blinking, use set_state().
+ *
+ * @dev: LED device to change
+ * @return brightness
+ */
+ int (*get_brightness)(struct udevice *dev);
+#endif
};
#define led_get_ops(dev) ((struct led_ops *)(dev)->driver->ops)
@@ -115,4 +140,28 @@
*/
int led_default_state(void);
+#ifdef CONFIG_AML_LED_PWM
+/**
+ * set_brightness() - set the brightness of an LED
+ *
+ * Thie records the period if supported, or returns -ENOSYS if not.
+ * To start the LED blinking, use set_state().
+ *
+ * @dev: LED device to change
+ * @period_ms: LED blink period in milliseconds
+ * @return 0 if OK, -ve on error
+ */
+int led_set_brightness(struct udevice *dev, int brightness);
+/**
+ * get_brightness() - get the brightness of an LED
+ *
+ * Thie records the period if supported, or returns -ENOSYS if not.
+ * To start the LED blinking, use set_state().
+ *
+ * @dev: LED device to change
+ * @period_ms: LED blink period in milliseconds
+ * @return 0 if OK, -ve on error
+ */
+int led_get_brightness(struct udevice *dev);
+#endif
#endif
diff --git a/include/libavb/avb_chain_partition_descriptor.h b/include/libavb/avb_chain_partition_descriptor.h
index f2c9250..80e2271 100644
--- a/include/libavb/avb_chain_partition_descriptor.h
+++ b/include/libavb/avb_chain_partition_descriptor.h
@@ -1,25 +1,6 @@
+/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2016 The Android Open Source Project
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
*/
#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION)
diff --git a/include/libavb/avb_crypto.h b/include/libavb/avb_crypto.h
index 0903baa..d8f649b 100644
--- a/include/libavb/avb_crypto.h
+++ b/include/libavb/avb_crypto.h
@@ -1,25 +1,6 @@
+/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2016 The Android Open Source Project
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
*/
#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION)
@@ -53,6 +34,12 @@
/* Size in bytes of a SHA-512 digest. */
#define AVB_SHA512_DIGEST_SIZE 64
+/* Possible digest types supported by libavb routines. */
+typedef enum {
+ AVB_DIGEST_TYPE_SHA256,
+ AVB_DIGEST_TYPE_SHA512,
+} AvbDigestType;
+
/* Algorithms that can be used in the vbmeta image for
* verification. An algorithm consists of a hash type and a signature
* type.
diff --git a/include/libavb/avb_descriptor.h b/include/libavb/avb_descriptor.h
index 5d0f0c6..d4f42ac 100644
--- a/include/libavb/avb_descriptor.h
+++ b/include/libavb/avb_descriptor.h
@@ -1,25 +1,6 @@
+/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2016 The Android Open Source Project
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
*/
#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION)
diff --git a/include/libavb/avb_footer.h b/include/libavb/avb_footer.h
index e84826f..62a6e65 100644
--- a/include/libavb/avb_footer.h
+++ b/include/libavb/avb_footer.h
@@ -1,25 +1,6 @@
+/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2016 The Android Open Source Project
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
*/
#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION)
diff --git a/include/libavb/avb_hash_descriptor.h b/include/libavb/avb_hash_descriptor.h
index 9ee8997..bede97f 100644
--- a/include/libavb/avb_hash_descriptor.h
+++ b/include/libavb/avb_hash_descriptor.h
@@ -1,25 +1,6 @@
+/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2016 The Android Open Source Project
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
*/
#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION)
diff --git a/include/libavb/avb_hashtree_descriptor.h b/include/libavb/avb_hashtree_descriptor.h
index d0f7e2c..d7f3eb5 100644
--- a/include/libavb/avb_hashtree_descriptor.h
+++ b/include/libavb/avb_hashtree_descriptor.h
@@ -1,25 +1,6 @@
+/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2016 The Android Open Source Project
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
*/
#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION)
diff --git a/include/libavb/avb_kernel_cmdline_descriptor.h b/include/libavb/avb_kernel_cmdline_descriptor.h
index 6908b3b..246fbda 100644
--- a/include/libavb/avb_kernel_cmdline_descriptor.h
+++ b/include/libavb/avb_kernel_cmdline_descriptor.h
@@ -1,25 +1,6 @@
+/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2016 The Android Open Source Project
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
*/
#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION)
diff --git a/include/libavb/avb_ops.h b/include/libavb/avb_ops.h
index 77f7ec3..6a5c589 100644
--- a/include/libavb/avb_ops.h
+++ b/include/libavb/avb_ops.h
@@ -1,25 +1,6 @@
+/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2016 The Android Open Source Project
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
*/
#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION)
@@ -37,6 +18,7 @@
/* Well-known names of named persistent values. */
#define AVB_NPV_PERSISTENT_DIGEST_PREFIX "avb.persistent_digest."
+#define AVB_NPV_MANAGED_VERITY_MODE "avb.managed_verity_mode"
/* Return codes used for I/O operations.
*
@@ -190,6 +172,10 @@
*
* If AVB_IO_RESULT_OK is returned then |out_is_trusted| is set -
* true if trusted or false if untrusted.
+ *
+ * NOTE: If AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION is passed to
+ * avb_slot_verify() then this operation is never used. Instead, the
+ * validate_public_key_for_partition() operation is used
*/
AvbIOResult (*validate_vbmeta_public_key)(AvbOps* ops,
const uint8_t* public_key_data,
@@ -250,6 +236,9 @@
* (NUL-terminated UTF-8 string). Returns the value in
* |out_size_num_bytes|.
*
+ * If the partition doesn't exist the AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION
+ * error code should be returned.
+ *
* Returns AVB_IO_RESULT_OK on success, otherwise an error code.
*/
AvbIOResult (*get_size_of_partition)(AvbOps* ops,
@@ -272,9 +261,10 @@
* AVB_IO_RESULT_ERROR_NO_SUCH_VALUE. If |buffer_size| is smaller than the
* size of the stored value, returns AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE.
*
- * This operation is currently only used to support persistent digests. If a
- * device does not use persistent digests this function pointer can be set to
- * NULL.
+ * This operation is currently only used to support persistent digests or the
+ * AVB_HASHTREE_ERROR_MODE_MANAGED_RESTART_AND_EIO hashtree error mode. If a
+ * device does not use one of these features this function pointer can be set
+ * to NULL.
*/
AvbIOResult (*read_persistent_value)(AvbOps* ops,
const char* name,
@@ -294,14 +284,34 @@
* AVB_IO_RESULT_ERROR_NO_SUCH_VALUE. If the |value_size| is not supported,
* returns AVB_IO_RESULT_ERROR_INVALID_VALUE_SIZE.
*
- * This operation is currently only used to support persistent digests. If a
- * device does not use persistent digests this function pointer can be set to
- * NULL.
+ * This operation is currently only used to support persistent digests or the
+ * AVB_HASHTREE_ERROR_MODE_MANAGED_RESTART_AND_EIO hashtree error mode. If a
+ * device does not use one of these features this function pointer can be set
+ * to NULL.
*/
AvbIOResult (*write_persistent_value)(AvbOps* ops,
const char* name,
size_t value_size,
const uint8_t* value);
+
+ /* Like validate_vbmeta_public_key() but for when the flag
+ * AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION is being used. The name of the
+ * partition to get the public key for is passed in |partition_name|.
+ *
+ * Also returns the rollback index location to use for the partition, in
+ * |out_rollback_index_location|.
+ *
+ * Returns AVB_IO_RESULT_OK on success, otherwise an error code.
+ */
+ AvbIOResult (*validate_public_key_for_partition)(
+ AvbOps* ops,
+ const char* partition,
+ const uint8_t* public_key_data,
+ size_t public_key_length,
+ const uint8_t* public_key_metadata,
+ size_t public_key_metadata_length,
+ bool* out_is_trusted,
+ uint32_t* out_rollback_index_location);
};
#ifdef __cplusplus
diff --git a/include/libavb/avb_property_descriptor.h b/include/libavb/avb_property_descriptor.h
index a2fef69..917c58f 100644
--- a/include/libavb/avb_property_descriptor.h
+++ b/include/libavb/avb_property_descriptor.h
@@ -1,25 +1,6 @@
+/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2016 The Android Open Source Project
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
*/
#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION)
diff --git a/include/libavb/avb_slot_verify.h b/include/libavb/avb_slot_verify.h
index 24acf1f..015a3ed 100644
--- a/include/libavb/avb_slot_verify.h
+++ b/include/libavb/avb_slot_verify.h
@@ -1,25 +1,6 @@
+/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2016 The Android Open Source Project
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
*/
#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION)
@@ -70,12 +51,25 @@
* be used ONLY for diagnostics and debugging. It cannot be used
* unless AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR is also
* used.
+ *
+ * AVB_HASHTREE_ERROR_MODE_MANAGED_RESTART_AND_EIO means that either
+ * AVB_HASHTREE_ERROR_MODE_RESTART or AVB_HASHTREE_ERROR_MODE_EIO is used
+ * depending on state. This mode implements a state machine whereby
+ * AVB_HASHTREE_ERROR_MODE_RESTART is used by default and when
+ * AVB_SLOT_VERIFY_FLAGS_RESTART_CAUSED_BY_HASHTREE_CORRUPTION is passed the
+ * mode transitions to AVB_HASHTREE_ERROR_MODE_EIO. When a new OS has been
+ * detected the device transitions back to the AVB_HASHTREE_ERROR_MODE_RESTART
+ * mode. To do this persistent storage is needed - specifically this means that
+ * the passed in AvbOps will need to have the read_persistent_value() and
+ * write_persistent_value() operations implemented. The name of the persistent
+ * value used is "avb.managed_verity_mode" and 32 bytes of storage is needed.
*/
typedef enum {
AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE,
AVB_HASHTREE_ERROR_MODE_RESTART,
AVB_HASHTREE_ERROR_MODE_EIO,
- AVB_HASHTREE_ERROR_MODE_LOGGING
+ AVB_HASHTREE_ERROR_MODE_LOGGING,
+ AVB_HASHTREE_ERROR_MODE_MANAGED_RESTART_AND_EIO
} AvbHashtreeErrorMode;
/* Flags that influence how avb_slot_verify() works.
@@ -99,10 +93,26 @@
* contents loaded from |requested_partition| will be the contents of
* the entire partition instead of just the size specified in the hash
* descriptor.
+ *
+ * The AVB_SLOT_VERIFY_FLAGS_RESTART_CAUSED_BY_HASHTREE_CORRUPTION flag
+ * should be set if using AVB_HASHTREE_ERROR_MODE_MANAGED_RESTART_AND_EIO
+ * and the reason the boot loader is running is because the device
+ * was restarted by the dm-verity driver.
+ *
+ * If the AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION flag is set then
+ * data won't be loaded from the "vbmeta" partition and the
+ * |validate_vbmeta_public_key| operation is never called. Instead, the
+ * vbmeta structs in |requested_partitions| are loaded and processed and the
+ * |validate_public_key_for_partition| operation is called for each of these
+ * vbmeta structs. This flag is useful when booting into recovery on a device
+ * not using A/B - see section "Booting into recovery" in README.md for
+ * more information.
*/
typedef enum {
AVB_SLOT_VERIFY_FLAGS_NONE = 0,
- AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR = (1 << 0)
+ AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR = (1 << 0),
+ AVB_SLOT_VERIFY_FLAGS_RESTART_CAUSED_BY_HASHTREE_CORRUPTION = (1 << 1),
+ AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION = (1 << 2),
} AvbSlotVerifyFlags;
/* Get a textual representation of |result|. */
@@ -207,6 +217,10 @@
* set to AVB_HASHTREE_ERROR_MODE_EIO, and 'logging' if it's set to
* AVB_HASHTREE_ERROR_MODE_LOGGING.
*
+ * androidboot.veritymode.managed: This is set to 'yes' only
+ * if hashtree validation isn't disabled and the passed-in hashtree
+ * error mode is AVB_HASHTREE_ERROR_MODE_MANAGED_RESTART_AND_EIO.
+ *
* androidboot.vbmeta.invalidate_on_error: This is set to 'yes' only
* if hashtree validation isn't disabled and the passed-in hashtree
* error mode is AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE.
@@ -222,7 +236,9 @@
* PARTUUID=$(ANDROID_VBMETA_PARTUUID) before substitution so it
* will end up pointing to the vbmeta partition for the verified
* slot. If there is no vbmeta partition it will point to the boot
- * partition of the verified slot.
+ * partition of the verified slot. If the flag
+ * AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION is used, this is not
+ * set.
*
* androidboot.vbmeta.avb_version: This is set to the decimal value
* of AVB_VERSION_MAJOR followed by a dot followed by the decimal
@@ -247,6 +263,15 @@
* appropriate system partition is substituted in. Note that none of
* the androidboot.* options mentioned above will be set.
*
+ * The |resolved_hashtree_error_mode| is the the value of the passed
+ * avb_slot_verify()'s |hashtree_error_mode| parameter except that it never has
+ * the value AVB_HASHTREE_ERROR_MODE_MANAGED_RESTART_AND_EIO. If this value was
+ * passed in, then the restart/eio state machine is used resulting in
+ * |resolved_hashtree_error_mode| being set to either
+ * AVB_HASHTREE_ERROR_MODE_RESTART or AVB_HASHTREE_ERROR_MODE_EIO. If set to
+ * AVB_HASHTREE_ERROR_MODE_EIO the boot loader should present a RED warning
+ * screen for the user to click through before continuing to boot.
+ *
* This struct may grow in the future without it being considered an
* ABI break.
*/
@@ -258,8 +283,20 @@
size_t num_loaded_partitions;
char* cmdline;
uint64_t rollback_indexes[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS];
+ AvbHashtreeErrorMode resolved_hashtree_error_mode;
} AvbSlotVerifyData;
+extern uint8_t boot_key_hash[AVB_SHA256_DIGEST_SIZE];
+
+/* Calculates a digest of all vbmeta images in |data| using
+ * the digest indicated by |digest_type|. Stores the result
+ * in |out_digest| which must be large enough to hold a digest
+ * of the requested type.
+ */
+void avb_slot_verify_data_calculate_vbmeta_digest(AvbSlotVerifyData* data,
+ AvbDigestType digest_type,
+ uint8_t* out_digest);
+
/* Frees a |AvbSlotVerifyData| including all data it points to. */
void avb_slot_verify_data_free(AvbSlotVerifyData* data);
@@ -292,12 +329,8 @@
* ignore verification errors which is something needed in the
* UNLOCKED state. See the AvbSlotVerifyFlags enumeration for details.
*
- * The |hashtree_error_mode| parameter should be set to the desired
- * error handling mode when hashtree validation fails inside the
- * HLOS. This value isn't used by libavb per se - it is forwarded to
- * the HLOS through the androidboot.veritymode and
- * androidboot.vbmeta.invalidate_on_error cmdline parameters. See the
- * AvbHashtreeErrorMode enumeration for details.
+ * The |hashtree_error_mode| parameter should be set to the desired error
+ * handling mode. See the AvbHashtreeErrorMode enumeration for details.
*
* Also note that |out_data| is never set if
* AVB_SLOT_VERIFY_RESULT_ERROR_OOM, AVB_SLOT_VERIFY_RESULT_ERROR_IO,
diff --git a/include/libavb/avb_sysdeps.h b/include/libavb/avb_sysdeps.h
index 6d4bf43..f52428c 100644
--- a/include/libavb/avb_sysdeps.h
+++ b/include/libavb/avb_sysdeps.h
@@ -1,25 +1,6 @@
+/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2016 The Android Open Source Project
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
*/
#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION)
@@ -38,10 +19,6 @@
* like uint8_t, uint64_t, and bool (with |false|, |true| keywords)
* must be present.
*/
-//#include <inttypes.h>
-//#include <stdbool.h>
-//#include <stddef.h>
-//#include <stdint.h>
#include <common.h>
/* If you don't have gcc or clang, these attribute macros may need to
@@ -76,6 +53,14 @@
*/
int avb_strcmp(const char* s1, const char* s2);
+/* Compare |n| bytes in two strings.
+ *
+ * Return an integer less than, equal to, or greater than zero if the
+ * first |n| bytes of |s1| is found, respectively, to be less than,
+ * to match, or be greater than the first |n| bytes of |s2|.
+ */
+int avb_strncmp(const char* s1, const char* s2, size_t n);
+
/* Copy |n| bytes from |src| to |dest|. */
void* avb_memcpy(void* dest, const void* src, size_t n);
diff --git a/include/libavb/avb_util.h b/include/libavb/avb_util.h
index be1b3c9..26dc6b0 100644
--- a/include/libavb/avb_util.h
+++ b/include/libavb/avb_util.h
@@ -1,25 +1,6 @@
+/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2016 The Android Open Source Project
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
*/
#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION)
diff --git a/include/libavb/avb_vbmeta_image.h b/include/libavb/avb_vbmeta_image.h
index d0c9f15..24f8519 100644
--- a/include/libavb/avb_vbmeta_image.h
+++ b/include/libavb/avb_vbmeta_image.h
@@ -1,25 +1,6 @@
+/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2016 The Android Open Source Project
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
*/
#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION)
diff --git a/include/libavb/avb_version.h b/include/libavb/avb_version.h
index ce43136..57c6ece 100644
--- a/include/libavb/avb_version.h
+++ b/include/libavb/avb_version.h
@@ -1,25 +1,6 @@
+/* SPDX-License-Identifier: MIT */
/*
* Copyright (C) 2017 The Android Open Source Project
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
*/
#if !defined(AVB_INSIDE_LIBAVB_H) && !defined(AVB_COMPILATION)
diff --git a/include/linux/device_type.h b/include/linux/device_type.h
new file mode 100644
index 0000000..f25b881
--- /dev/null
+++ b/include/linux/device_type.h
@@ -0,0 +1,12 @@
+#ifndef __LINUX_DEVICE_TYPE_H
+#define __LINUX_DEVICE_TYPE_H
+
+/*
+ * Replace linux's device_type
+ */
+struct device_type {
+ const char *name;
+};
+
+
+#endif /* __LINUX_DEVICE_TYPE_H */
diff --git a/include/linux/kern_levels.h b/include/linux/kern_levels.h
new file mode 100644
index 0000000..890a334
--- /dev/null
+++ b/include/linux/kern_levels.h
@@ -0,0 +1,43 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __KERN_LEVELS_H__
+#define __KERN_LEVELS_H__
+
+#define KERN_SOH "\001" /* ASCII Start Of Header */
+#define KERN_SOH_ASCII '\001'
+
+#define KERN_EMERG KERN_SOH "0" /* system is unusable */
+#define KERN_ALERT KERN_SOH "1" /* action must be taken immediately */
+#define KERN_CRIT KERN_SOH "2" /* critical conditions */
+#define KERN_ERR KERN_SOH "3" /* error conditions */
+#define KERN_WARNING KERN_SOH "4" /* warning conditions */
+#define KERN_NOTICE KERN_SOH "5" /* normal but significant condition */
+#define KERN_INFO KERN_SOH "6" /* informational */
+#define KERN_DEBUG KERN_SOH "7" /* debug-level messages */
+
+#define KERN_DEFAULT KERN_SOH "d" /* the default kernel loglevel */
+
+/*
+ * Annotation for a "continued" line of log printout (only done after a
+ * line that had no enclosing \n). Only to be used by core/arch code
+ * during early bootup (a continued line is not SMP-safe otherwise).
+ */
+#define KERN_CONT KERN_SOH "c"
+
+/* integer equivalents of KERN_<LEVEL> */
+#define LOGLEVEL_SCHED -2 /* Deferred messages from sched code
+ * are set to this special level */
+#define LOGLEVEL_DEFAULT -1 /* default (or last) loglevel */
+#define LOGLEVEL_EMERG 0 /* system is unusable */
+#define LOGLEVEL_ALERT 1 /* action must be taken immediately */
+#define LOGLEVEL_CRIT 2 /* critical conditions */
+#define LOGLEVEL_ERR 3 /* error conditions */
+#define LOGLEVEL_WARNING 4 /* warning conditions */
+#define LOGLEVEL_NOTICE 5 /* normal but significant condition */
+#define LOGLEVEL_INFO 6 /* informational */
+#define LOGLEVEL_DEBUG 7 /* debug-level messages */
+
+#endif
diff --git a/include/linux/mtd/rawnand.h b/include/linux/mtd/rawnand.h
index 364b3e3..ba4b86b 100644
--- a/include/linux/mtd/rawnand.h
+++ b/include/linux/mtd/rawnand.h
@@ -998,6 +998,7 @@
#define NAND_MFR_INTEL 0x89
#define NAND_MFR_ATO 0x9b
#define NAND_MFR_GIGA 0xc8
+#define NAND_MFR_ZETTA 0xba
#ifdef CONFIG_MESON_NFC
#define NAND_ID_ESMT 0xc8
diff --git a/include/linux/mtd/spinand.h b/include/linux/mtd/spinand.h
index be01e1e..56b3dc5 100644
--- a/include/linux/mtd/spinand.h
+++ b/include/linux/mtd/spinand.h
@@ -22,6 +22,51 @@
#include <spi-mem.h>
#include <linux/mtd/nand.h>
#endif
+#define NAND_BLOCK_GOOD 0
+#define NAND_BLOCK_BAD 1
+#define NAND_FACTORY_BAD 2
+
+#define SPINAND_MESON_RSV 1
+#ifdef CONFIG_SPI_NAND_AML_ADVANCED
+/* Use dev parameters to send parameters in advanced mode */
+#define SPINAND_MESON_INFO_PAGE 0
+#else
+#define SPINAND_MESON_INFO_PAGE 1
+#endif
+
+
+#if SPINAND_MESON_INFO_PAGE
+struct info_page {
+ char magic[8]; /* magic header of info page */
+ /* info page version, +1 when you update this struct */
+ u8 version; /* 1 for now */
+ u8 mode; /* 1 discrete, 0 compact */
+ u8 bl2_num; /* bl2 copy number */
+ u8 fip_num; /* fip copy number */
+ union {
+ struct {
+#define SPINAND_MAGIC "AMLIFPG"
+#define SPINAND_INFO_VER 1
+ u8 rd_max; /* spi nand max read io */
+ u8 oob_offset; /* user bytes offset */
+ uint8_t planes_per_lun;
+ u8 rsv;
+ u32 fip_start; /* start pages */
+ u32 fip_pages; /* pages per fip */
+ u32 page_size; /* spi nand page size (bytes) */
+ u32 page_per_blk; /* page number per block */
+ u32 oob_size; /* valid oob size (bytes) */
+ u32 bbt_start; /* bbt start pages */
+ u32 bbt_valid; /* bbt valid offset pages */
+ u32 bbt_size; /* bbt occupied bytes */
+ } s;/* spi nand */
+ struct {
+ u32 reserved;
+ } e;/* emmc */
+ } dev;
+
+};
+#endif
/**
* Standard SPI NAND flash operations
@@ -39,11 +84,20 @@
SPI_MEM_OP_NO_DUMMY, \
SPI_MEM_OP_NO_DATA)
+#if 0
#define SPINAND_READID_OP(ndummy, buf, len) \
SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \
SPI_MEM_OP_NO_ADDR, \
SPI_MEM_OP_DUMMY(ndummy, 1), \
SPI_MEM_OP_DATA_IN(len, buf, 1))
+#else
+/* Adjust the timing of read ID */
+#define SPINAND_READID_OP(ndummy, buf, len) \
+ SPI_MEM_OP(SPI_MEM_OP_CMD(0x9f, 1), \
+ SPI_MEM_OP_ADDR(1, 0x00, 1), \
+ SPI_MEM_OP_DUMMY(ndummy, 1), \
+ SPI_MEM_OP_DATA_IN(len, buf, 1))
+#endif
#define SPINAND_SET_FEATURE_OP(reg, valptr) \
SPI_MEM_OP(SPI_MEM_OP_CMD(0x1f, 1), \
@@ -202,9 +256,12 @@
/* SPI NAND manufacturers */
extern const struct spinand_manufacturer gigadevice_spinand_manufacturer;
+extern const struct spinand_manufacturer toshiba_spinand_manufacturer;
extern const struct spinand_manufacturer macronix_spinand_manufacturer;
extern const struct spinand_manufacturer micron_spinand_manufacturer;
extern const struct spinand_manufacturer winbond_spinand_manufacturer;
+extern const struct spinand_manufacturer zetta_spinand_manufacturer;
+extern const struct spinand_manufacturer xtx_spinand_manufacturer;
/**
* struct spinand_op_variants - SPI NAND operation variants
@@ -362,7 +419,16 @@
u8 *oobbuf;
u8 *scratchbuf;
const struct spinand_manufacturer *manufacturer;
+ /* Record the current spinand */
+ const char *model;
void *priv;
+#if SPINAND_MESON_RSV
+ /* add for aml rsv */
+ struct meson_rsv_handler_t *rsv;
+ /* aml bbt */
+ u8 *bbt;
+ u8 bbt_scan;
+#endif
};
/**
diff --git a/include/linux/printk.h b/include/linux/printk.h
index 088513a..0bc363d 100644
--- a/include/linux/printk.h
+++ b/include/linux/printk.h
@@ -1,5 +1,5 @@
-#ifndef __KERNEL_PRINTK__
-#define __KERNEL_PRINTK__
+#ifndef __LINUX_PRINTK__
+#define __LINUX_PRINTK__
#include <stdio.h>
#include <linux/compiler.h>
diff --git a/include/linux/usb/ch9.h b/include/linux/usb/ch9.h
index 56ee018..0fdb6ee 100644
--- a/include/linux/usb/ch9.h
+++ b/include/linux/usb/ch9.h
@@ -1059,9 +1059,5 @@
* If you're using usb_gadget_get_string(), use this to wrap a string
* together with its ID.
*/
-struct usb_string {
- u8 id;
- const char *s;
-};
#endif /* __LINUX_USB_CH9_H */
diff --git a/include/linux/usb/gadget.h b/include/linux/usb/gadget.h
index 497798a..e6cbcb2 100644
--- a/include/linux/usb/gadget.h
+++ b/include/linux/usb/gadget.h
@@ -499,6 +499,8 @@
/* readonly to gadget driver */
const struct usb_gadget_ops *ops;
struct usb_ep *ep0;
+ struct usb_ep *epin;
+ struct usb_ep *epout;
struct list_head ep_list; /* of usb_ep */
enum usb_device_speed speed;
enum usb_device_speed max_speed;
@@ -935,7 +937,8 @@
#include <usb.h>
static inline int usb_gadget_initialize(int index)
{
- return board_usb_init(index, USB_INIT_DEVICE);
+ //return board_usb_init(index, USB_INIT_DEVICE);
+ return 0;
}
static inline int usb_gadget_release(int index)
diff --git a/include/linux/usb/pd.h b/include/linux/usb/pd.h
new file mode 100644
index 0000000..b8bc170
--- /dev/null
+++ b/include/linux/usb/pd.h
@@ -0,0 +1,456 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2015-2021 Google, Inc
+ */
+
+#ifndef __LINUX_USB_PD_H
+#define __LINUX_USB_PD_H
+
+#include <linux/kernel.h>
+#include <linux/types.h>
+#include <linux/usb/typec.h>
+#include <compiler.h>
+
+/* USB PD Messages */
+enum pd_ctrl_msg_type {
+ /* 0 Reserved */
+ PD_CTRL_GOOD_CRC = 1,
+ PD_CTRL_GOTO_MIN = 2,
+ PD_CTRL_ACCEPT = 3,
+ PD_CTRL_REJECT = 4,
+ PD_CTRL_PING = 5,
+ PD_CTRL_PS_RDY = 6,
+ PD_CTRL_GET_SOURCE_CAP = 7,
+ PD_CTRL_GET_SINK_CAP = 8,
+ PD_CTRL_DR_SWAP = 9,
+ PD_CTRL_PR_SWAP = 10,
+ PD_CTRL_VCONN_SWAP = 11,
+ PD_CTRL_WAIT = 12,
+ PD_CTRL_SOFT_RESET = 13,
+ /* 14-15 Reserved */
+ PD_CTRL_NOT_SUPP = 16,
+ PD_CTRL_GET_SOURCE_CAP_EXT = 17,
+ PD_CTRL_GET_STATUS = 18,
+ PD_CTRL_FR_SWAP = 19,
+ PD_CTRL_GET_PPS_STATUS = 20,
+ PD_CTRL_GET_COUNTRY_CODES = 21,
+ /* 22-31 Reserved */
+};
+
+enum pd_data_msg_type {
+ /* 0 Reserved */
+ PD_DATA_SOURCE_CAP = 1,
+ PD_DATA_REQUEST = 2,
+ PD_DATA_BIST = 3,
+ PD_DATA_SINK_CAP = 4,
+ PD_DATA_BATT_STATUS = 5,
+ PD_DATA_ALERT = 6,
+ PD_DATA_GET_COUNTRY_INFO = 7,
+ /* 8-14 Reserved */
+ PD_DATA_VENDOR_DEF = 15,
+ /* 16-31 Reserved */
+};
+
+enum pd_ext_msg_type {
+ /* 0 Reserved */
+ PD_EXT_SOURCE_CAP_EXT = 1,
+ PD_EXT_STATUS = 2,
+ PD_EXT_GET_BATT_CAP = 3,
+ PD_EXT_GET_BATT_STATUS = 4,
+ PD_EXT_BATT_CAP = 5,
+ PD_EXT_GET_MANUFACTURER_INFO = 6,
+ PD_EXT_MANUFACTURER_INFO = 7,
+ PD_EXT_SECURITY_REQUEST = 8,
+ PD_EXT_SECURITY_RESPONSE = 9,
+ PD_EXT_FW_UPDATE_REQUEST = 10,
+ PD_EXT_FW_UPDATE_RESPONSE = 11,
+ PD_EXT_PPS_STATUS = 12,
+ PD_EXT_COUNTRY_INFO = 13,
+ PD_EXT_COUNTRY_CODES = 14,
+ /* 15-31 Reserved */
+};
+
+#define PD_REV10 0x0
+#define PD_REV20 0x1
+#define PD_REV30 0x2
+#define PD_MAX_REV PD_REV30
+
+#define PD_HEADER_EXT_HDR BIT(15)
+#define PD_HEADER_CNT_SHIFT 12
+#define PD_HEADER_CNT_MASK 0x7
+#define PD_HEADER_ID_SHIFT 9
+#define PD_HEADER_ID_MASK 0x7
+#define PD_HEADER_PWR_ROLE BIT(8)
+#define PD_HEADER_REV_SHIFT 6
+#define PD_HEADER_REV_MASK 0x3
+#define PD_HEADER_DATA_ROLE BIT(5)
+#define PD_HEADER_TYPE_SHIFT 0
+#define PD_HEADER_TYPE_MASK 0x1f
+
+#define PD_HEADER(type, pwr, data, rev, id, cnt, ext_hdr) \
+ ((((type) & PD_HEADER_TYPE_MASK) << PD_HEADER_TYPE_SHIFT) | \
+ ((pwr) == TYPEC_SOURCE ? PD_HEADER_PWR_ROLE : 0) | \
+ ((data) == TYPEC_HOST ? PD_HEADER_DATA_ROLE : 0) | \
+ (rev << PD_HEADER_REV_SHIFT) | \
+ (((id) & PD_HEADER_ID_MASK) << PD_HEADER_ID_SHIFT) | \
+ (((cnt) & PD_HEADER_CNT_MASK) << PD_HEADER_CNT_SHIFT) | \
+ ((ext_hdr) ? PD_HEADER_EXT_HDR : 0))
+
+#define PD_HEADER_LE(type, pwr, data, rev, id, cnt) \
+ cpu_to_le16(PD_HEADER((type), (pwr), (data), (rev), (id), (cnt), (0)))
+
+static inline unsigned int pd_header_cnt(u16 header)
+{
+ return (header >> PD_HEADER_CNT_SHIFT) & PD_HEADER_CNT_MASK;
+}
+
+static inline unsigned int pd_header_cnt_le(__le16 header)
+{
+ return pd_header_cnt(le16_to_cpu(header));
+}
+
+static inline unsigned int pd_header_type(u16 header)
+{
+ return (header >> PD_HEADER_TYPE_SHIFT) & PD_HEADER_TYPE_MASK;
+}
+
+static inline unsigned int pd_header_type_le(__le16 header)
+{
+ return pd_header_type(le16_to_cpu(header));
+}
+
+static inline unsigned int pd_header_msgid(u16 header)
+{
+ return (header >> PD_HEADER_ID_SHIFT) & PD_HEADER_ID_MASK;
+}
+
+static inline unsigned int pd_header_msgid_le(__le16 header)
+{
+ return pd_header_msgid(le16_to_cpu(header));
+}
+
+static inline unsigned int pd_header_rev(u16 header)
+{
+ return (header >> PD_HEADER_REV_SHIFT) & PD_HEADER_REV_MASK;
+}
+
+static inline unsigned int pd_header_rev_le(__le16 header)
+{
+ return pd_header_rev(le16_to_cpu(header));
+}
+
+#define PD_EXT_HDR_CHUNKED BIT(15)
+#define PD_EXT_HDR_CHUNK_NUM_SHIFT 11
+#define PD_EXT_HDR_CHUNK_NUM_MASK 0xf
+#define PD_EXT_HDR_REQ_CHUNK BIT(10)
+#define PD_EXT_HDR_DATA_SIZE_SHIFT 0
+#define PD_EXT_HDR_DATA_SIZE_MASK 0x1ff
+
+#define PD_EXT_HDR(data_size, req_chunk, chunk_num, chunked) \
+ ((((data_size) & PD_EXT_HDR_DATA_SIZE_MASK) << PD_EXT_HDR_DATA_SIZE_SHIFT) | \
+ ((req_chunk) ? PD_EXT_HDR_REQ_CHUNK : 0) | \
+ (((chunk_num) & PD_EXT_HDR_CHUNK_NUM_MASK) << PD_EXT_HDR_CHUNK_NUM_SHIFT) | \
+ ((chunked) ? PD_EXT_HDR_CHUNKED : 0))
+
+#define PD_EXT_HDR_LE(data_size, req_chunk, chunk_num, chunked) \
+ cpu_to_le16(PD_EXT_HDR((data_size), (req_chunk), (chunk_num), (chunked)))
+
+static inline unsigned int pd_ext_header_chunk_num(u16 ext_header)
+{
+ return (ext_header >> PD_EXT_HDR_CHUNK_NUM_SHIFT) &
+ PD_EXT_HDR_CHUNK_NUM_MASK;
+}
+
+static inline unsigned int pd_ext_header_data_size(u16 ext_header)
+{
+ return (ext_header >> PD_EXT_HDR_DATA_SIZE_SHIFT) &
+ PD_EXT_HDR_DATA_SIZE_MASK;
+}
+
+static inline unsigned int pd_ext_header_data_size_le(__le16 ext_header)
+{
+ return pd_ext_header_data_size(le16_to_cpu(ext_header));
+}
+
+#define PD_MAX_PAYLOAD 7
+#define PD_EXT_MAX_CHUNK_DATA 26
+
+/**
+ * struct pd_chunked_ext_message_data - PD chunked extended message data as
+ * seen on wire
+ * @header: PD extended message header
+ * @data: PD extended message data
+ */
+struct pd_chunked_ext_message_data {
+ __le16 header;
+ u8 data[PD_EXT_MAX_CHUNK_DATA];
+} __packed;
+
+/**
+ * struct pd_message - PD message as seen on wire
+ * @header: PD message header
+ * @payload: PD message payload
+ * @ext_msg: PD message chunked extended message data
+ */
+struct pd_message {
+ __le16 header;
+ union {
+ __le32 payload[PD_MAX_PAYLOAD];
+ struct pd_chunked_ext_message_data ext_msg;
+ };
+} __packed;
+
+/* PDO: Power Data Object */
+#define PDO_MAX_OBJECTS 7
+
+enum pd_pdo_type {
+ PDO_TYPE_FIXED = 0,
+ PDO_TYPE_BATT = 1,
+ PDO_TYPE_VAR = 2,
+ PDO_TYPE_APDO = 3,
+};
+
+#define PDO_TYPE_SHIFT 30
+#define PDO_TYPE_MASK 0x3
+
+#define PDO_TYPE(t) ((t) << PDO_TYPE_SHIFT)
+
+#define PDO_VOLT_MASK 0x3ff
+#define PDO_CURR_MASK 0x3ff
+#define PDO_PWR_MASK 0x3ff
+
+#define PDO_FIXED_DUAL_ROLE BIT(29) /* Power role swap supported */
+#define PDO_FIXED_SUSPEND BIT(28) /* USB Suspend supported (Source) */
+#define PDO_FIXED_HIGHER_CAP BIT(28) /* Requires more than vSafe5V (Sink) */
+#define PDO_FIXED_EXTPOWER BIT(27) /* Externally powered */
+#define PDO_FIXED_USB_COMM BIT(26) /* USB communications capable */
+#define PDO_FIXED_DATA_SWAP BIT(25) /* Data role swap supported */
+#define PDO_FIXED_VOLT_SHIFT 10 /* 50mV units */
+#define PDO_FIXED_CURR_SHIFT 0 /* 10mA units */
+
+#define PDO_FIXED_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_FIXED_VOLT_SHIFT)
+#define PDO_FIXED_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_FIXED_CURR_SHIFT)
+
+#define PDO_FIXED(mv, ma, flags) \
+ (PDO_TYPE(PDO_TYPE_FIXED) | (flags) | \
+ PDO_FIXED_VOLT(mv) | PDO_FIXED_CURR(ma))
+
+#define VSAFE5V 5000 /* mv units */
+
+#define PDO_BATT_MAX_VOLT_SHIFT 20 /* 50mV units */
+#define PDO_BATT_MIN_VOLT_SHIFT 10 /* 50mV units */
+#define PDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */
+
+#define PDO_BATT_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MIN_VOLT_SHIFT)
+#define PDO_BATT_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_BATT_MAX_VOLT_SHIFT)
+#define PDO_BATT_MAX_POWER(mw) ((((mw) / 250) & PDO_PWR_MASK) << PDO_BATT_MAX_PWR_SHIFT)
+
+#define PDO_BATT(min_mv, max_mv, max_mw) \
+ (PDO_TYPE(PDO_TYPE_BATT) | PDO_BATT_MIN_VOLT(min_mv) | \
+ PDO_BATT_MAX_VOLT(max_mv) | PDO_BATT_MAX_POWER(max_mw))
+
+#define PDO_VAR_MAX_VOLT_SHIFT 20 /* 50mV units */
+#define PDO_VAR_MIN_VOLT_SHIFT 10 /* 50mV units */
+#define PDO_VAR_MAX_CURR_SHIFT 0 /* 10mA units */
+
+#define PDO_VAR_MIN_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MIN_VOLT_SHIFT)
+#define PDO_VAR_MAX_VOLT(mv) ((((mv) / 50) & PDO_VOLT_MASK) << PDO_VAR_MAX_VOLT_SHIFT)
+#define PDO_VAR_MAX_CURR(ma) ((((ma) / 10) & PDO_CURR_MASK) << PDO_VAR_MAX_CURR_SHIFT)
+
+#define PDO_VAR(min_mv, max_mv, max_ma) \
+ (PDO_TYPE(PDO_TYPE_VAR) | PDO_VAR_MIN_VOLT(min_mv) | \
+ PDO_VAR_MAX_VOLT(max_mv) | PDO_VAR_MAX_CURR(max_ma))
+
+enum pd_apdo_type {
+ APDO_TYPE_PPS = 0,
+};
+
+#define PDO_APDO_TYPE_SHIFT 28 /* Only valid value currently is 0x0 - PPS */
+#define PDO_APDO_TYPE_MASK 0x3
+
+#define PDO_APDO_TYPE(t) ((t) << PDO_APDO_TYPE_SHIFT)
+
+#define PDO_PPS_APDO_MAX_VOLT_SHIFT 17 /* 100mV units */
+#define PDO_PPS_APDO_MIN_VOLT_SHIFT 8 /* 100mV units */
+#define PDO_PPS_APDO_MAX_CURR_SHIFT 0 /* 50mA units */
+
+#define PDO_PPS_APDO_VOLT_MASK 0xff
+#define PDO_PPS_APDO_CURR_MASK 0x7f
+
+#define PDO_PPS_APDO_MIN_VOLT(mv) \
+ ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MIN_VOLT_SHIFT)
+#define PDO_PPS_APDO_MAX_VOLT(mv) \
+ ((((mv) / 100) & PDO_PPS_APDO_VOLT_MASK) << PDO_PPS_APDO_MAX_VOLT_SHIFT)
+#define PDO_PPS_APDO_MAX_CURR(ma) \
+ ((((ma) / 50) & PDO_PPS_APDO_CURR_MASK) << PDO_PPS_APDO_MAX_CURR_SHIFT)
+
+#define PDO_PPS_APDO(min_mv, max_mv, max_ma) \
+ (PDO_TYPE(PDO_TYPE_APDO) | PDO_APDO_TYPE(APDO_TYPE_PPS) | \
+ PDO_PPS_APDO_MIN_VOLT(min_mv) | PDO_PPS_APDO_MAX_VOLT(max_mv) | \
+ PDO_PPS_APDO_MAX_CURR(max_ma))
+
+static inline enum pd_pdo_type pdo_type(u32 pdo)
+{
+ return (pdo >> PDO_TYPE_SHIFT) & PDO_TYPE_MASK;
+}
+
+static inline unsigned int pdo_fixed_voltage(u32 pdo)
+{
+ return ((pdo >> PDO_FIXED_VOLT_SHIFT) & PDO_VOLT_MASK) * 50;
+}
+
+static inline unsigned int pdo_min_voltage(u32 pdo)
+{
+ return ((pdo >> PDO_VAR_MIN_VOLT_SHIFT) & PDO_VOLT_MASK) * 50;
+}
+
+static inline unsigned int pdo_max_voltage(u32 pdo)
+{
+ return ((pdo >> PDO_VAR_MAX_VOLT_SHIFT) & PDO_VOLT_MASK) * 50;
+}
+
+static inline unsigned int pdo_max_current(u32 pdo)
+{
+ return ((pdo >> PDO_VAR_MAX_CURR_SHIFT) & PDO_CURR_MASK) * 10;
+}
+
+static inline unsigned int pdo_max_power(u32 pdo)
+{
+ return ((pdo >> PDO_BATT_MAX_PWR_SHIFT) & PDO_PWR_MASK) * 250;
+}
+
+static inline enum pd_apdo_type pdo_apdo_type(u32 pdo)
+{
+ return (pdo >> PDO_APDO_TYPE_SHIFT) & PDO_APDO_TYPE_MASK;
+}
+
+static inline unsigned int pdo_pps_apdo_min_voltage(u32 pdo)
+{
+ return ((pdo >> PDO_PPS_APDO_MIN_VOLT_SHIFT) &
+ PDO_PPS_APDO_VOLT_MASK) * 100;
+}
+
+static inline unsigned int pdo_pps_apdo_max_voltage(u32 pdo)
+{
+ return ((pdo >> PDO_PPS_APDO_MAX_VOLT_SHIFT) &
+ PDO_PPS_APDO_VOLT_MASK) * 100;
+}
+
+static inline unsigned int pdo_pps_apdo_max_current(u32 pdo)
+{
+ return ((pdo >> PDO_PPS_APDO_MAX_CURR_SHIFT) &
+ PDO_PPS_APDO_CURR_MASK) * 50;
+}
+
+/* RDO: Request Data Object */
+#define RDO_OBJ_POS_SHIFT 28
+#define RDO_OBJ_POS_MASK 0x7
+#define RDO_GIVE_BACK BIT(27) /* Supports reduced operating current */
+#define RDO_CAP_MISMATCH BIT(26) /* Not satisfied by source caps */
+#define RDO_USB_COMM BIT(25) /* USB communications capable */
+#define RDO_NO_SUSPEND BIT(24) /* USB Suspend not supported */
+
+#define RDO_PWR_MASK 0x3ff
+#define RDO_CURR_MASK 0x3ff
+
+#define RDO_FIXED_OP_CURR_SHIFT 10
+#define RDO_FIXED_MAX_CURR_SHIFT 0
+
+#define RDO_OBJ(idx) (((idx) & RDO_OBJ_POS_MASK) << RDO_OBJ_POS_SHIFT)
+
+#define PDO_FIXED_OP_CURR(ma) ((((ma) / 10) & RDO_CURR_MASK) << RDO_FIXED_OP_CURR_SHIFT)
+#define PDO_FIXED_MAX_CURR(ma) ((((ma) / 10) & RDO_CURR_MASK) << RDO_FIXED_MAX_CURR_SHIFT)
+
+#define RDO_FIXED(idx, op_ma, max_ma, flags) \
+ (RDO_OBJ(idx) | (flags) | \
+ PDO_FIXED_OP_CURR(op_ma) | PDO_FIXED_MAX_CURR(max_ma))
+
+#define RDO_BATT_OP_PWR_SHIFT 10 /* 250mW units */
+#define RDO_BATT_MAX_PWR_SHIFT 0 /* 250mW units */
+
+#define RDO_BATT_OP_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_OP_PWR_SHIFT)
+#define RDO_BATT_MAX_PWR(mw) ((((mw) / 250) & RDO_PWR_MASK) << RDO_BATT_MAX_PWR_SHIFT)
+
+#define RDO_BATT(idx, op_mw, max_mw, flags) \
+ (RDO_OBJ(idx) | (flags) | \
+ RDO_BATT_OP_PWR(op_mw) | RDO_BATT_MAX_PWR(max_mw))
+
+#define RDO_PROG_VOLT_MASK 0x7ff
+#define RDO_PROG_CURR_MASK 0x7f
+
+#define RDO_PROG_VOLT_SHIFT 9
+#define RDO_PROG_CURR_SHIFT 0
+
+#define RDO_PROG_VOLT_MV_STEP 20
+#define RDO_PROG_CURR_MA_STEP 50
+
+#define PDO_PROG_OUT_VOLT(mv) \
+ ((((mv) / RDO_PROG_VOLT_MV_STEP) & RDO_PROG_VOLT_MASK) << RDO_PROG_VOLT_SHIFT)
+#define PDO_PROG_OP_CURR(ma) \
+ ((((ma) / RDO_PROG_CURR_MA_STEP) & RDO_PROG_CURR_MASK) << RDO_PROG_CURR_SHIFT)
+
+#define RDO_PROG(idx, out_mv, op_ma, flags) \
+ (RDO_OBJ(idx) | (flags) | \
+ PDO_PROG_OUT_VOLT(out_mv) | PDO_PROG_OP_CURR(op_ma))
+
+static inline unsigned int rdo_index(u32 rdo)
+{
+ return (rdo >> RDO_OBJ_POS_SHIFT) & RDO_OBJ_POS_MASK;
+}
+
+static inline unsigned int rdo_op_current(u32 rdo)
+{
+ return ((rdo >> RDO_FIXED_OP_CURR_SHIFT) & RDO_CURR_MASK) * 10;
+}
+
+static inline unsigned int rdo_max_current(u32 rdo)
+{
+ return ((rdo >> RDO_FIXED_MAX_CURR_SHIFT) &
+ RDO_CURR_MASK) * 10;
+}
+
+static inline unsigned int rdo_op_power(u32 rdo)
+{
+ return ((rdo >> RDO_BATT_OP_PWR_SHIFT) & RDO_PWR_MASK) * 250;
+}
+
+static inline unsigned int rdo_max_power(u32 rdo)
+{
+ return ((rdo >> RDO_BATT_MAX_PWR_SHIFT) & RDO_PWR_MASK) * 250;
+}
+
+/* USB PD timers and counters */
+#define PD_T_NO_RESPONSE 5000 /* 4.5 - 5.5 seconds */
+#define PD_T_DB_DETECT 10000 /* 10 - 15 seconds */
+#define PD_T_SEND_SOURCE_CAP 150 /* 100 - 200 ms */
+#define PD_T_SENDER_RESPONSE 60 /* 24 - 30 ms, relaxed */
+#define PD_T_SOURCE_ACTIVITY 45
+#define PD_T_SINK_ACTIVITY 135
+#define PD_T_SINK_WAIT_CAP 240
+#define PD_T_PS_TRANSITION 500
+#define PD_T_SRC_TRANSITION 35
+#define PD_T_DRP_SNK 40
+#define PD_T_DRP_SRC 30
+#define PD_T_PS_SOURCE_OFF 920
+#define PD_T_PS_SOURCE_ON 480
+#define PD_T_PS_HARD_RESET 30
+#define PD_T_SRC_RECOVER 760
+#define PD_T_SRC_RECOVER_MAX 1000
+#define PD_T_SRC_TURN_ON 275
+#define PD_T_SAFE_0V 650
+#define PD_T_VCONN_SOURCE_ON 100
+#define PD_T_SINK_REQUEST 100 /* 100 ms minimum */
+#define PD_T_ERROR_RECOVERY 100 /* minimum 25 is insufficient */
+#define PD_T_SRCSWAPSTDBY 625 /* Maximum of 650ms */
+#define PD_T_NEWSRC 250 /* Maximum of 275ms */
+
+#define PD_T_DRP_TRY 100 /* 75 - 150 ms */
+#define PD_T_DRP_TRYWAIT 600 /* 400 - 800 ms */
+
+#define PD_T_CC_DEBOUNCE 200 /* 100 - 200 ms */
+#define PD_T_PD_DEBOUNCE 20 /* 10 - 20 ms */
+
+#define PD_N_CAPS_COUNT (PD_T_NO_RESPONSE / PD_T_SEND_SOURCE_CAP)
+#define PD_N_HARD_RESET_COUNT 2
+
+#endif /* __LINUX_USB_PD_H */
diff --git a/include/linux/usb/pd_ado.h b/include/linux/usb/pd_ado.h
new file mode 100644
index 0000000..9aa1cf3
--- /dev/null
+++ b/include/linux/usb/pd_ado.h
@@ -0,0 +1,42 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2017 Dialog Semiconductor
+ *
+ * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
+ */
+
+#ifndef __LINUX_USB_PD_ADO_H
+#define __LINUX_USB_PD_ADO_H
+
+/* ADO : Alert Data Object */
+#define USB_PD_ADO_TYPE_SHIFT 24
+#define USB_PD_ADO_TYPE_MASK 0xff
+#define USB_PD_ADO_FIXED_BATT_SHIFT 20
+#define USB_PD_ADO_FIXED_BATT_MASK 0xf
+#define USB_PD_ADO_HOT_SWAP_BATT_SHIFT 16
+#define USB_PD_ADO_HOT_SWAP_BATT_MASK 0xf
+
+#define USB_PD_ADO_TYPE_BATT_STATUS_CHANGE BIT(1)
+#define USB_PD_ADO_TYPE_OCP BIT(2)
+#define USB_PD_ADO_TYPE_OTP BIT(3)
+#define USB_PD_ADO_TYPE_OP_COND_CHANGE BIT(4)
+#define USB_PD_ADO_TYPE_SRC_INPUT_CHANGE BIT(5)
+#define USB_PD_ADO_TYPE_OVP BIT(6)
+
+static inline unsigned int usb_pd_ado_type(u32 ado)
+{
+ return (ado >> USB_PD_ADO_TYPE_SHIFT) & USB_PD_ADO_TYPE_MASK;
+}
+
+static inline unsigned int usb_pd_ado_fixed_batt(u32 ado)
+{
+ return (ado >> USB_PD_ADO_FIXED_BATT_SHIFT) &
+ USB_PD_ADO_FIXED_BATT_MASK;
+}
+
+static inline unsigned int usb_pd_ado_hot_swap_batt(u32 ado)
+{
+ return (ado >> USB_PD_ADO_HOT_SWAP_BATT_SHIFT) &
+ USB_PD_ADO_HOT_SWAP_BATT_MASK;
+}
+#endif /* __LINUX_USB_PD_ADO_H */
diff --git a/include/linux/usb/pd_bdo.h b/include/linux/usb/pd_bdo.h
new file mode 100644
index 0000000..033fe3e
--- /dev/null
+++ b/include/linux/usb/pd_bdo.h
@@ -0,0 +1,22 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2015-2017 Google, Inc
+ */
+
+#ifndef __LINUX_USB_PD_BDO_H
+#define __LINUX_USB_PD_BDO_H
+
+/* BDO : BIST Data Object */
+#define BDO_MODE_RECV (0 << 28)
+#define BDO_MODE_TRANSMIT (1 << 28)
+#define BDO_MODE_COUNTERS (2 << 28)
+#define BDO_MODE_CARRIER0 (3 << 28)
+#define BDO_MODE_CARRIER1 (4 << 28)
+#define BDO_MODE_CARRIER2 (5 << 28)
+#define BDO_MODE_CARRIER3 (6 << 28)
+#define BDO_MODE_EYE (7 << 28)
+#define BDO_MODE_TESTDATA (8 << 28)
+
+#define BDO_MODE_MASK(mode) ((mode) & 0xf0000000)
+
+#endif
diff --git a/include/linux/usb/pd_ext_sdb.h b/include/linux/usb/pd_ext_sdb.h
new file mode 100644
index 0000000..0eb83ce
--- /dev/null
+++ b/include/linux/usb/pd_ext_sdb.h
@@ -0,0 +1,31 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2017 Dialog Semiconductor
+ *
+ * Author: Adam Thomson <Adam.Thomson.Opensource@diasemi.com>
+ */
+
+#ifndef __LINUX_USB_PD_EXT_SDB_H
+#define __LINUX_USB_PD_EXT_SDB_H
+
+/* SDB : Status Data Block */
+enum usb_pd_ext_sdb_fields {
+ USB_PD_EXT_SDB_INTERNAL_TEMP = 0,
+ USB_PD_EXT_SDB_PRESENT_INPUT,
+ USB_PD_EXT_SDB_PRESENT_BATT_INPUT,
+ USB_PD_EXT_SDB_EVENT_FLAGS,
+ USB_PD_EXT_SDB_TEMP_STATUS,
+ USB_PD_EXT_SDB_DATA_SIZE,
+};
+
+/* Event Flags */
+#define USB_PD_EXT_SDB_EVENT_OCP BIT(1)
+#define USB_PD_EXT_SDB_EVENT_OTP BIT(2)
+#define USB_PD_EXT_SDB_EVENT_OVP BIT(3)
+#define USB_PD_EXT_SDB_EVENT_CF_CV_MODE BIT(4)
+
+#define USB_PD_EXT_SDB_PPS_EVENTS (USB_PD_EXT_SDB_EVENT_OCP | \
+ USB_PD_EXT_SDB_EVENT_OTP | \
+ USB_PD_EXT_SDB_EVENT_OVP)
+
+#endif /* __LINUX_USB_PD_EXT_SDB_H */
diff --git a/include/linux/usb/pd_vdo.h b/include/linux/usb/pd_vdo.h
new file mode 100644
index 0000000..781f4e9
--- /dev/null
+++ b/include/linux/usb/pd_vdo.h
@@ -0,0 +1,242 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2015-2017 Google, Inc
+ */
+
+#ifndef __LINUX_USB_PD_VDO_H
+#define __LINUX_USB_PD_VDO_H
+
+#include "pd.h"
+
+/*
+ * VDO : Vendor Defined Message Object
+ * VDM object is minimum of VDM header + 6 additional data objects.
+ */
+
+#define VDO_MAX_OBJECTS 6
+#define VDO_MAX_SIZE (VDO_MAX_OBJECTS + 1)
+
+/*
+ * VDM header
+ * ----------
+ * <31:16> :: SVID
+ * <15> :: VDM type ( 1b == structured, 0b == unstructured )
+ * <14:13> :: Structured VDM version (can only be 00 == 1.0 currently)
+ * <12:11> :: reserved
+ * <10:8> :: object position (1-7 valid ... used for enter/exit mode only)
+ * <7:6> :: command type (SVDM only?)
+ * <5> :: reserved (SVDM), command type (UVDM)
+ * <4:0> :: command
+ */
+#define VDO(vid, type, custom) \
+ (((vid) << 16) | \
+ ((type) << 15) | \
+ ((custom) & 0x7FFF))
+
+#define VDO_SVDM_TYPE (1 << 15)
+#define VDO_SVDM_VERS(x) ((x) << 13)
+#define VDO_OPOS(x) ((x) << 8)
+#define VDO_CMDT(x) ((x) << 6)
+#define VDO_OPOS_MASK VDO_OPOS(0x7)
+#define VDO_CMDT_MASK VDO_CMDT(0x3)
+
+#define CMDT_INIT 0
+#define CMDT_RSP_ACK 1
+#define CMDT_RSP_NAK 2
+#define CMDT_RSP_BUSY 3
+
+/* reserved for SVDM ... for Google UVDM */
+#define VDO_SRC_INITIATOR (0 << 5)
+#define VDO_SRC_RESPONDER (1 << 5)
+
+#define CMD_DISCOVER_IDENT 1
+#define CMD_DISCOVER_SVID 2
+#define CMD_DISCOVER_MODES 3
+#define CMD_ENTER_MODE 4
+#define CMD_EXIT_MODE 5
+#define CMD_ATTENTION 6
+
+#define VDO_CMD_VENDOR(x) (((0x10 + (x)) & 0x1f))
+
+/* ChromeOS specific commands */
+#define VDO_CMD_VERSION VDO_CMD_VENDOR(0)
+#define VDO_CMD_SEND_INFO VDO_CMD_VENDOR(1)
+#define VDO_CMD_READ_INFO VDO_CMD_VENDOR(2)
+#define VDO_CMD_REBOOT VDO_CMD_VENDOR(5)
+#define VDO_CMD_FLASH_ERASE VDO_CMD_VENDOR(6)
+#define VDO_CMD_FLASH_WRITE VDO_CMD_VENDOR(7)
+#define VDO_CMD_ERASE_SIG VDO_CMD_VENDOR(8)
+#define VDO_CMD_PING_ENABLE VDO_CMD_VENDOR(10)
+#define VDO_CMD_CURRENT VDO_CMD_VENDOR(11)
+#define VDO_CMD_FLIP VDO_CMD_VENDOR(12)
+#define VDO_CMD_GET_LOG VDO_CMD_VENDOR(13)
+#define VDO_CMD_CCD_EN VDO_CMD_VENDOR(14)
+
+#define PD_VDO_VID(vdo) ((vdo) >> 16)
+#define PD_VDO_SVDM(vdo) (((vdo) >> 15) & 1)
+#define PD_VDO_OPOS(vdo) (((vdo) >> 8) & 0x7)
+#define PD_VDO_CMD(vdo) ((vdo) & 0x1f)
+#define PD_VDO_CMDT(vdo) (((vdo) >> 6) & 0x3)
+
+/*
+ * SVDM Identity request -> response
+ *
+ * Request is simply properly formatted SVDM header
+ *
+ * Response is 4 data objects:
+ * [0] :: SVDM header
+ * [1] :: Identitiy header
+ * [2] :: Cert Stat VDO
+ * [3] :: (Product | Cable) VDO
+ * [4] :: AMA VDO
+ *
+ */
+#define VDO_INDEX_HDR 0
+#define VDO_INDEX_IDH 1
+#define VDO_INDEX_CSTAT 2
+#define VDO_INDEX_CABLE 3
+#define VDO_INDEX_PRODUCT 3
+#define VDO_INDEX_AMA 4
+
+/*
+ * SVDM Identity Header
+ * --------------------
+ * <31> :: data capable as a USB host
+ * <30> :: data capable as a USB device
+ * <29:27> :: product type
+ * <26> :: modal operation supported (1b == yes)
+ * <25:16> :: Reserved, Shall be set to zero
+ * <15:0> :: USB-IF assigned VID for this cable vendor
+ */
+#define IDH_PTYPE_UNDEF 0
+#define IDH_PTYPE_HUB 1
+#define IDH_PTYPE_PERIPH 2
+#define IDH_PTYPE_PCABLE 3
+#define IDH_PTYPE_ACABLE 4
+#define IDH_PTYPE_AMA 5
+
+#define VDO_IDH(usbh, usbd, ptype, is_modal, vid) \
+ ((usbh) << 31 | (usbd) << 30 | ((ptype) & 0x7) << 27 \
+ | (is_modal) << 26 | ((vid) & 0xffff))
+
+#define PD_IDH_PTYPE(vdo) (((vdo) >> 27) & 0x7)
+#define PD_IDH_VID(vdo) ((vdo) & 0xffff)
+#define PD_IDH_MODAL_SUPP(vdo) ((vdo) & (1 << 26))
+
+/*
+ * Cert Stat VDO
+ * -------------
+ * <31:0> : USB-IF assigned XID for this cable
+ */
+#define PD_CSTAT_XID(vdo) (vdo)
+
+/*
+ * Product VDO
+ * -----------
+ * <31:16> : USB Product ID
+ * <15:0> : USB bcdDevice
+ */
+#define VDO_PRODUCT(pid, bcd) (((pid) & 0xffff) << 16 | ((bcd) & 0xffff))
+#define PD_PRODUCT_PID(vdo) (((vdo) >> 16) & 0xffff)
+
+/*
+ * Cable VDO
+ * ---------
+ * <31:28> :: Cable HW version
+ * <27:24> :: Cable FW version
+ * <23:20> :: Reserved, Shall be set to zero
+ * <19:18> :: type-C to Type-A/B/C (00b == A, 01 == B, 10 == C)
+ * <17> :: Type-C to Plug/Receptacle (0b == plug, 1b == receptacle)
+ * <16:13> :: cable latency (0001 == <10ns(~1m length))
+ * <12:11> :: cable termination type (11b == both ends active VCONN req)
+ * <10> :: SSTX1 Directionality support (0b == fixed, 1b == cfgable)
+ * <9> :: SSTX2 Directionality support
+ * <8> :: SSRX1 Directionality support
+ * <7> :: SSRX2 Directionality support
+ * <6:5> :: Vbus current handling capability
+ * <4> :: Vbus through cable (0b == no, 1b == yes)
+ * <3> :: SOP" controller present? (0b == no, 1b == yes)
+ * <2:0> :: USB SS Signaling support
+ */
+#define CABLE_ATYPE 0
+#define CABLE_BTYPE 1
+#define CABLE_CTYPE 2
+#define CABLE_PLUG 0
+#define CABLE_RECEPTACLE 1
+#define CABLE_CURR_1A5 0
+#define CABLE_CURR_3A 1
+#define CABLE_CURR_5A 2
+#define CABLE_USBSS_U2_ONLY 0
+#define CABLE_USBSS_U31_GEN1 1
+#define CABLE_USBSS_U31_GEN2 2
+#define VDO_CABLE(hw, fw, cbl, gdr, lat, term, tx1d, tx2d, rx1d, rx2d, cur,\
+ vps, sopp, usbss) \
+ (((hw) & 0x7) << 28 | ((fw) & 0x7) << 24 | ((cbl) & 0x3) << 18 \
+ | (gdr) << 17 | ((lat) & 0x7) << 13 | ((term) & 0x3) << 11 \
+ | (tx1d) << 10 | (tx2d) << 9 | (rx1d) << 8 | (rx2d) << 7 \
+ | ((cur) & 0x3) << 5 | (vps) << 4 | (sopp) << 3 \
+ | ((usbss) & 0x7))
+
+/*
+ * AMA VDO
+ * ---------
+ * <31:28> :: Cable HW version
+ * <27:24> :: Cable FW version
+ * <23:12> :: Reserved, Shall be set to zero
+ * <11> :: SSTX1 Directionality support (0b == fixed, 1b == cfgable)
+ * <10> :: SSTX2 Directionality support
+ * <9> :: SSRX1 Directionality support
+ * <8> :: SSRX2 Directionality support
+ * <7:5> :: Vconn power
+ * <4> :: Vconn power required
+ * <3> :: Vbus power required
+ * <2:0> :: USB SS Signaling support
+ */
+#define VDO_AMA(hw, fw, tx1d, tx2d, rx1d, rx2d, vcpwr, vcr, vbr, usbss) \
+ (((hw) & 0x7) << 28 | ((fw) & 0x7) << 24 \
+ | (tx1d) << 11 | (tx2d) << 10 | (rx1d) << 9 | (rx2d) << 8 \
+ | ((vcpwr) & 0x7) << 5 | (vcr) << 4 | (vbr) << 3 \
+ | ((usbss) & 0x7))
+
+#define PD_VDO_AMA_VCONN_REQ(vdo) (((vdo) >> 4) & 1)
+#define PD_VDO_AMA_VBUS_REQ(vdo) (((vdo) >> 3) & 1)
+
+#define AMA_VCONN_PWR_1W 0
+#define AMA_VCONN_PWR_1W5 1
+#define AMA_VCONN_PWR_2W 2
+#define AMA_VCONN_PWR_3W 3
+#define AMA_VCONN_PWR_4W 4
+#define AMA_VCONN_PWR_5W 5
+#define AMA_VCONN_PWR_6W 6
+#define AMA_USBSS_U2_ONLY 0
+#define AMA_USBSS_U31_GEN1 1
+#define AMA_USBSS_U31_GEN2 2
+#define AMA_USBSS_BBONLY 3
+
+/*
+ * SVDM Discover SVIDs request -> response
+ *
+ * Request is properly formatted VDM Header with discover SVIDs command.
+ * Response is a set of SVIDs of all all supported SVIDs with all zero's to
+ * mark the end of SVIDs. If more than 12 SVIDs are supported command SHOULD be
+ * repeated.
+ */
+#define VDO_SVID(svid0, svid1) (((svid0) & 0xffff) << 16 | ((svid1) & 0xffff))
+#define PD_VDO_SVID_SVID0(vdo) ((vdo) >> 16)
+#define PD_VDO_SVID_SVID1(vdo) ((vdo) & 0xffff)
+
+/* USB-IF SIDs */
+#define USB_SID_PD 0xff00 /* power delivery */
+#define USB_SID_DISPLAYPORT 0xff01
+#define USB_SID_MHL 0xff02 /* Mobile High-Definition Link */
+
+/* VDM command timeouts (in ms) */
+
+#define PD_T_VDM_UNSTRUCTURED 500
+#define PD_T_VDM_BUSY 100
+#define PD_T_VDM_WAIT_MODE_E 100
+#define PD_T_VDM_SNDR_RSP 30
+#define PD_T_VDM_E_MODE 25
+#define PD_T_VDM_RCVR_RSP 15
+
+#endif /* __LINUX_USB_PD_VDO_H */
diff --git a/include/linux/usb/role.h b/include/linux/usb/role.h
new file mode 100644
index 0000000..29dfd24
--- /dev/null
+++ b/include/linux/usb/role.h
@@ -0,0 +1,76 @@
+// SPDX-License-Identifier: GPL-2.0
+
+#ifndef __LINUX_USB_ROLE_H
+#define __LINUX_USB_ROLE_H
+
+#include <dm/device.h>
+#include <dm/ofnode.h>
+
+struct usb_role_switch;
+
+enum usb_role {
+ USB_ROLE_NONE,
+ USB_ROLE_HOST,
+ USB_ROLE_DEVICE,
+};
+
+typedef int (*usb_role_switch_set_t)(struct udevice *dev, enum usb_role role);
+typedef enum usb_role (*usb_role_switch_get_t)(struct udevice *dev);
+
+
+/**
+ * struct usb_role_switch_desc - USB Role Switch Descriptor
+ * @fwnode: The device node to be associated with the role switch
+ * @usb2_port: Optional reference to the host controller port device (USB2)
+ * @usb3_port: Optional reference to the host controller port device (USB3)
+ * @udc: Optional reference to the peripheral controller device
+ * @set: Callback for setting the role
+ * @get: Callback for getting the role (optional)
+ * @allow_userspace_control: If true userspace may change the role through sysfs
+ *
+ * @usb2_port and @usb3_port will point to the USB host port and @udc to the USB
+ * device controller behind the USB connector with the role switch. If
+ * @usb2_port, @usb3_port and @udc are included in the description, the
+ * reference count for them should be incremented by the caller of
+ * usb_role_switch_register() before registering the switch.
+ */
+struct usb_role_switch_desc {
+ //struct fwnode_handle *fwnode;
+ ofnode *ofnode;
+ struct udevice *usb2_port;
+ struct udevice *usb3_port;
+ struct udevice *udc;
+ usb_role_switch_set_t set;
+ usb_role_switch_get_t get;
+ bool allow_userspace_control;
+};
+
+
+#if IS_ENABLED(CONFIG_USB_ROLE_SWITCH)
+int usb_role_switch_set_role(struct usb_role_switch *sw, enum usb_role role);
+enum usb_role usb_role_switch_get_role(struct usb_role_switch *sw);
+struct usb_role_switch *usb_role_switch_get(struct udevice *dev);
+void usb_role_switch_put(struct usb_role_switch *sw);
+
+#else
+static inline int usb_role_switch_set_role(struct usb_role_switch *sw,
+ enum usb_role role)
+{
+ return 0;
+}
+
+static inline enum usb_role usb_role_switch_get_role(struct usb_role_switch *sw)
+{
+ return USB_ROLE_NONE;
+}
+
+static inline struct usb_role_switch *usb_role_switch_get(struct udevice *dev)
+{
+ return ERR_PTR(-ENODEV);
+}
+
+static inline void usb_role_switch_put(struct usb_role_switch *sw) { }
+
+#endif
+
+#endif /* __LINUX_USB_ROLE_H */
diff --git a/include/linux/usb/tcpm.h b/include/linux/usb/tcpm.h
new file mode 100644
index 0000000..ead4886
--- /dev/null
+++ b/include/linux/usb/tcpm.h
@@ -0,0 +1,171 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright 2015-2017 Google, Inc
+ */
+
+#ifndef __LINUX_USB_TCPM_H
+#define __LINUX_USB_TCPM_H
+
+#include <linux/bitops.h>
+#include <linux/usb/typec.h>
+#include <dm/ofnode.h>
+#include "pd.h"
+
+enum typec_cc_status {
+ TYPEC_CC_OPEN,
+ TYPEC_CC_RA,
+ TYPEC_CC_RD,
+ TYPEC_CC_RP_DEF,
+ TYPEC_CC_RP_1_5,
+ TYPEC_CC_RP_3_0,
+};
+
+enum typec_cc_polarity {
+ TYPEC_POLARITY_CC1,
+ TYPEC_POLARITY_CC2,
+};
+
+/* Time to wait for TCPC to complete transmit */
+#define MSEC_PER_SEC 1000
+#define PD_T_TCPC_TX_TIMEOUT 100 /* in ms */
+#define PD_ROLE_SWAP_TIMEOUT (MSEC_PER_SEC * 10)
+#define PD_PPS_CTRL_TIMEOUT (MSEC_PER_SEC * 10)
+
+enum tcpm_transmit_status {
+ TCPC_TX_SUCCESS = 0,
+ TCPC_TX_DISCARDED = 1,
+ TCPC_TX_FAILED = 2,
+ TCPC_TX_WAITING = 3,
+};
+
+enum tcpm_transmit_type {
+ TCPC_TX_SOP = 0,
+ TCPC_TX_SOP_PRIME = 1,
+ TCPC_TX_SOP_PRIME_PRIME = 2,
+ TCPC_TX_SOP_DEBUG_PRIME = 3,
+ TCPC_TX_SOP_DEBUG_PRIME_PRIME = 4,
+ TCPC_TX_HARD_RESET = 5,
+ TCPC_TX_CABLE_RESET = 6,
+ TCPC_TX_BIST_MODE_2 = 7
+};
+
+/**
+ * struct tcpc_config - Port configuration
+ * @src_pdo: PDO parameters sent to port partner as response to
+ * PD_CTRL_GET_SOURCE_CAP message
+ * @nr_src_pdo: Number of entries in @src_pdo
+ * @snk_pdo: PDO parameters sent to partner as response to
+ * PD_CTRL_GET_SINK_CAP message
+ * @nr_snk_pdo: Number of entries in @snk_pdo
+ * @operating_snk_mw:
+ * Required operating sink power in mW
+ * @type: Port type (TYPEC_PORT_DFP, TYPEC_PORT_UFP, or
+ * TYPEC_PORT_DRP)
+ * @default_role:
+ * Default port role (TYPEC_SINK or TYPEC_SOURCE).
+ * Set to TYPEC_NO_PREFERRED_ROLE if no default role.
+ * @try_role_hw:True if try.{Src,Snk} is implemented in hardware
+ * @alt_modes: List of supported alternate modes
+ */
+struct tcpc_config {
+ const u32 *src_pdo;
+ unsigned int nr_src_pdo;
+
+ const u32 *snk_pdo;
+ unsigned int nr_snk_pdo;
+
+ const u32 *snk_vdo;
+ unsigned int nr_snk_vdo;
+
+ unsigned int operating_snk_mw;
+
+ enum typec_port_type type;
+ enum typec_port_data data;
+ enum typec_role default_role;
+ bool try_role_hw; /* try.{src,snk} implemented in hardware */
+ bool self_powered; /* port belongs to a self powered device */
+
+ const struct typec_altmode_desc *alt_modes;
+};
+
+/* Mux state attributes */
+#define TCPC_MUX_USB_ENABLED BIT(0) /* USB enabled */
+#define TCPC_MUX_DP_ENABLED BIT(1) /* DP enabled */
+#define TCPC_MUX_POLARITY_INVERTED BIT(2) /* Polarity inverted */
+
+/**
+ * struct tcpc_dev - Port configuration and callback functions
+ * @config: Pointer to port configuration
+ * @ofnode: Pointer to port ofnode
+ * @get_vbus: Called to read current VBUS state
+ * @get_current_limit:
+ * Optional; called by the tcpm core when configured as a snk
+ * and cc=Rp-def. This allows the tcpm to provide a fallback
+ * current-limit detection method for the cc=Rp-def case.
+ * For example, some tcpcs may include BC1.2 charger detection
+ * and use that in this case.
+ * @set_cc: Called to set value of CC pins
+ * @get_cc: Called to read current CC pin values
+ * @set_polarity:
+ * Called to set polarity
+ * @set_vconn: Called to enable or disable VCONN
+ * @set_vbus: Called to enable or disable VBUS
+ * @set_current_limit:
+ * Optional; called to set current limit as negotiated
+ * with partner.
+ * @set_pd_rx: Called to enable or disable reception of PD messages
+ * @set_roles: Called to set power and data roles
+ * @start_toggling:
+ * Optional; if supported by hardware, called to start dual-role
+ * toggling or single-role connection detection. Toggling stops
+ * automatically if a connection is established.
+ * @try_role: Optional; called to set a preferred role
+ * @pd_transmit:Called to transmit PD message
+ * @get_tx_status:Called to get TX status
+ */
+struct tcpc_dev {
+ const struct tcpc_config *config;
+ ofnode *ofnode;
+
+ int (*init)(struct tcpc_dev *dev);
+ int (*get_vbus)(struct tcpc_dev *dev);
+ int (*get_current_limit)(struct tcpc_dev *dev);
+ int (*set_cc)(struct tcpc_dev *dev, enum typec_cc_status cc);
+ int (*get_cc)(struct tcpc_dev *dev, enum typec_cc_status *cc1,
+ enum typec_cc_status *cc2);
+ int (*set_polarity)(struct tcpc_dev *dev,
+ enum typec_cc_polarity polarity);
+ int (*set_vconn)(struct tcpc_dev *dev, bool on);
+ int (*set_vbus)(struct tcpc_dev *dev, bool on, bool charge);
+ int (*set_current_limit)(struct tcpc_dev *dev, u32 max_ma, u32 mv);
+ int (*set_pd_rx)(struct tcpc_dev *dev, bool on);
+ int (*set_roles)(struct tcpc_dev *dev, bool attached,
+ enum typec_role role, enum typec_data_role data);
+ int (*start_toggling)(struct tcpc_dev *dev,
+ enum typec_port_type port_type,
+ enum typec_cc_status cc);
+ int (*try_role)(struct tcpc_dev *dev, int role);
+ int (*pd_transmit)(struct tcpc_dev *dev, enum tcpm_transmit_type type,
+ const struct pd_message *msg);
+ int (*get_tx_status)(struct tcpc_dev *dev,
+ enum tcpm_transmit_status *status);
+};
+
+struct tcpm_port;
+
+struct tcpm_port *tcpm_register_port(struct udevice *dev, struct tcpc_dev *tcpc);
+void tcpm_unregister_port(struct tcpm_port *port);
+
+void tcpm_vbus_change(struct tcpm_port *port);
+void tcpm_cc_change(struct tcpm_port *port);
+void tcpm_pd_receive(struct tcpm_port *port,
+ const struct pd_message *msg);
+void tcpm_pd_transmit_complete(struct tcpm_port *port,
+ enum tcpm_transmit_status status);
+void tcpm_pd_hard_reset(struct tcpm_port *port);
+void tcpm_tcpc_reset(struct tcpm_port *port);
+void tcpm_handle_pd_event(struct tcpm_port *port);
+void tcpm_run_state_machine(struct tcpm_port *port);
+bool tcpm_is_snk_ready(struct tcpm_port *port);
+
+#endif /* __LINUX_USB_TCPM_H */
diff --git a/include/linux/usb/typec.h b/include/linux/usb/typec.h
new file mode 100644
index 0000000..ca744e4
--- /dev/null
+++ b/include/linux/usb/typec.h
@@ -0,0 +1,254 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+
+#ifndef __LINUX_USB_TYPEC_H
+#define __LINUX_USB_TYPEC_H
+
+#include <dm/ofnode.h>
+#include <linux/types.h>
+
+/* USB Type-C Specification releases */
+#define USB_TYPEC_REV_1_0 0x100 /* 1.0 */
+#define USB_TYPEC_REV_1_1 0x110 /* 1.1 */
+#define USB_TYPEC_REV_1_2 0x120 /* 1.2 */
+
+struct typec_partner;
+struct typec_cable;
+struct typec_plug;
+struct typec_port;
+
+struct udevice;
+
+enum typec_port_type {
+ TYPEC_PORT_SRC,
+ TYPEC_PORT_SNK,
+ TYPEC_PORT_DRP,
+};
+
+enum typec_port_data {
+ TYPEC_PORT_DFP,
+ TYPEC_PORT_UFP,
+ TYPEC_PORT_DRD,
+};
+
+enum typec_plug_type {
+ USB_PLUG_NONE,
+ USB_PLUG_TYPE_A,
+ USB_PLUG_TYPE_B,
+ USB_PLUG_TYPE_C,
+ USB_PLUG_CAPTIVE,
+};
+
+enum typec_data_role {
+ TYPEC_DEVICE,
+ TYPEC_HOST,
+};
+
+enum typec_role {
+ TYPEC_SINK,
+ TYPEC_SOURCE,
+};
+
+enum typec_pwr_opmode {
+ TYPEC_PWR_MODE_USB,
+ TYPEC_PWR_MODE_1_5A,
+ TYPEC_PWR_MODE_3_0A,
+ TYPEC_PWR_MODE_PD,
+};
+
+enum typec_accessory {
+ TYPEC_ACCESSORY_NONE,
+ TYPEC_ACCESSORY_AUDIO,
+ TYPEC_ACCESSORY_DEBUG,
+};
+
+#define TYPEC_MAX_ACCESSORY 3
+
+enum typec_orientation {
+ TYPEC_ORIENTATION_NONE,
+ TYPEC_ORIENTATION_NORMAL,
+ TYPEC_ORIENTATION_REVERSE,
+};
+
+/*
+ * struct usb_pd_identity - USB Power Delivery identity data
+ * @id_header: ID Header VDO
+ * @cert_stat: Cert Stat VDO
+ * @product: Product VDO
+ *
+ * USB power delivery Discover Identity command response data.
+ *
+ * REVISIT: This is USB Power Delivery specific information, so this structure
+ * probable belongs to USB Power Delivery header file once we have them.
+ */
+struct usb_pd_identity {
+ u32 id_header;
+ u32 cert_stat;
+ u32 product;
+};
+
+int typec_partner_set_identity(struct typec_partner *partner);
+int typec_cable_set_identity(struct typec_cable *cable);
+
+/*
+ * struct typec_altmode_desc - USB Type-C Alternate Mode Descriptor
+ * @svid: Standard or Vendor ID
+ * @mode: Index of the Mode
+ * @vdo: VDO returned by Discover Modes USB PD command
+ * @roles: Only for ports. DRP if the mode is available in both roles
+ *
+ * Description of an Alternate Mode which a connector, cable plug or partner
+ * supports.
+ */
+struct typec_altmode_desc {
+ u16 svid;
+ u8 mode;
+ u32 vdo;
+ /* Only used with ports */
+ enum typec_port_data roles;
+};
+
+struct typec_altmode
+*typec_partner_register_altmode(struct typec_partner *partner,
+ const struct typec_altmode_desc *desc);
+struct typec_altmode
+*typec_plug_register_altmode(struct typec_plug *plug,
+ const struct typec_altmode_desc *desc);
+struct typec_altmode
+*typec_port_register_altmode(struct typec_port *port,
+ const struct typec_altmode_desc *desc);
+void typec_unregister_altmode(struct typec_altmode *altmode);
+
+struct typec_port *typec_altmode2port(struct typec_altmode *alt);
+
+void typec_altmode_update_active(struct typec_altmode *alt, bool active);
+
+enum typec_plug_index {
+ TYPEC_PLUG_SOP_P,
+ TYPEC_PLUG_SOP_PP,
+};
+
+/*
+ * struct typec_plug_desc - USB Type-C Cable Plug Descriptor
+ * @index: SOP Prime for the plug connected to DFP and SOP Double Prime for the
+ * plug connected to UFP
+ *
+ * Represents USB Type-C Cable Plug.
+ */
+struct typec_plug_desc {
+ enum typec_plug_index index;
+};
+
+/*
+ * struct typec_cable_desc - USB Type-C Cable Descriptor
+ * @type: The plug type from USB PD Cable VDO
+ * @active: Is the cable active or passive
+ * @identity: Result of Discover Identity command
+ *
+ * Represents USB Type-C Cable attached to USB Type-C port.
+ */
+struct typec_cable_desc {
+ enum typec_plug_type type;
+ unsigned int active:1;
+ struct usb_pd_identity *identity;
+};
+
+/*
+ * struct typec_partner_desc - USB Type-C Partner Descriptor
+ * @usb_pd: USB Power Delivery support
+ * @accessory: Audio, Debug or none.
+ * @identity: Discover Identity command data
+ *
+ * Details about a partner that is attached to USB Type-C port. If @identity
+ * member exists when partner is registered, a directory named "identity" is
+ * created to sysfs for the partner device.
+ */
+struct typec_partner_desc {
+ unsigned int usb_pd:1;
+ enum typec_accessory accessory;
+ struct usb_pd_identity *identity;
+};
+
+/**
+ * struct typec_operations - USB Type-C Port Operations
+ * @try_role: Set data role preference for DRP port
+ * @dr_set: Set Data Role
+ * @pr_set: Set Power Role
+ * @vconn_set: Source VCONN
+ * @port_type_set: Set port type
+ */
+struct typec_operations {
+ int (*try_role)(struct typec_port *port, int role);
+ int (*dr_set)(struct typec_port *port, enum typec_data_role role);
+ int (*pr_set)(struct typec_port *port, enum typec_role role);
+ int (*vconn_set)(struct typec_port *port, enum typec_role role);
+ int (*port_type_set)(struct typec_port *port,
+ enum typec_port_type type);
+};
+
+/*
+ * struct typec_capability - USB Type-C Port Capabilities
+ * @type: Supported power role of the port
+ * @data: Supported data role of the port
+ * @no_vconn: The port does not support vconn
+ * @revision: USB Type-C Specification release. Binary coded decimal
+ * @pd_revision: USB Power Delivery Specification revision if supported
+ * @prefer_role: Initial role preference (DRP ports).
+ * @accessory: Supported Accessory Modes
+ * @sw: Cable plug orientation switch
+ * @ofnode: child node of the TypeC port
+ * @driver_data: Private pointer for driver specific info
+ * @ops: Port operations vector
+ *
+ * Static capabilities of a single USB Type-C port.
+ */
+struct typec_capability {
+ enum typec_port_type type;
+ enum typec_port_data data;
+ bool no_vconn;
+ u16 revision; /* 0120H = "1.2" */
+ u16 pd_revision; /* 0300H = "3.0" */
+ int prefer_role;
+ enum typec_accessory accessory[TYPEC_MAX_ACCESSORY];
+
+ struct typec_switch *sw;
+ ofnode *ofnode;
+ void *driver_data;
+
+ const struct typec_operations *ops;
+};
+
+/* Specific to try_role(). Indicates the user want's to clear the preference. */
+#define TYPEC_NO_PREFERRED_ROLE (-1)
+
+struct typec_port *typec_register_port(struct udevice *parent,
+ const struct typec_capability *cap);
+void typec_unregister_port(struct typec_port *port);
+
+struct typec_partner *typec_register_partner(struct typec_port *port,
+ struct typec_partner_desc *desc);
+void typec_unregister_partner(struct typec_partner *partner);
+
+struct typec_cable *typec_register_cable(struct typec_port *port,
+ struct typec_cable_desc *desc);
+void typec_unregister_cable(struct typec_cable *cable);
+
+struct typec_plug *typec_register_plug(struct typec_cable *cable,
+ struct typec_plug_desc *desc);
+void typec_unregister_plug(struct typec_plug *plug);
+
+void typec_set_data_role(struct typec_port *port, enum typec_data_role role);
+void typec_set_pwr_role(struct typec_port *port, enum typec_role role);
+void typec_set_vconn_role(struct typec_port *port, enum typec_role role);
+void typec_set_pwr_opmode(struct typec_port *port, enum typec_pwr_opmode mode);
+
+int typec_set_orientation(struct typec_port *port,
+ enum typec_orientation orientation);
+enum typec_orientation typec_get_orientation(struct typec_port *port);
+int typec_set_mode(struct typec_port *port, int mode);
+
+void *typec_get_drvdata(struct typec_port *port);
+
+int typec_find_port_power_role(const char *name);
+int typec_find_power_role(const char *name);
+int typec_find_port_data_role(const char *name);
+#endif /* __LINUX_USB_TYPEC_H */
diff --git a/include/lmb.h b/include/lmb.h
index c97210d..f04d058 100644
--- a/include/lmb.h
+++ b/include/lmb.h
@@ -31,8 +31,6 @@
extern struct lmb lmb;
extern void lmb_init(struct lmb *lmb);
-extern void lmb_init_and_reserve(struct lmb *lmb, phys_addr_t base,
- phys_size_t size, void *fdt_blob);
extern long lmb_add(struct lmb *lmb, phys_addr_t base, phys_size_t size);
extern long lmb_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size);
extern phys_addr_t lmb_alloc(struct lmb *lmb, phys_size_t size, ulong align);
@@ -54,8 +52,6 @@
void board_lmb_reserve(struct lmb *lmb);
void arch_lmb_reserve(struct lmb *lmb);
-phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base, phys_size_t size);
-
#endif /* __KERNEL__ */
#endif /* _LINUX_LMB_H */
diff --git a/include/log.h b/include/log.h
index 0f2bc19..01e8981 100644
--- a/include/log.h
+++ b/include/log.h
@@ -9,6 +9,7 @@
#ifndef __LOG_H
#define __LOG_H
+#include <command.h>
#include <dm/uclass-id.h>
#include <linux/list.h>
diff --git a/include/mmc.h b/include/mmc.h
index 8a2700c..a145668 100644
--- a/include/mmc.h
+++ b/include/mmc.h
@@ -72,7 +72,6 @@
#define MMC_MODE_1BIT BIT(28)
#define MMC_MODE_SPI BIT(27)
-
#define SD_DATA_4BIT 0x00040000
#define IS_SD(x) ((x)->version & SD_VERSION_SD)
@@ -112,11 +111,11 @@
#define MMC_CMD_SPI_READ_OCR 58
#define MMC_CMD_SPI_CRC_ON_OFF 59
#define MMC_CMD_RES_MAN 62
+#define MMC_SD_HS_TUNING 70
#define MMC_CMD62_ARG1 0xefac62ec
#define MMC_CMD62_ARG2 0xcbaea7
-
#define SD_CMD_SEND_RELATIVE_ADDR 3
#define SD_CMD_SWITCH_FUNC 6
#define SD_CMD_SEND_IF_COND 8
@@ -129,6 +128,9 @@
#define SD_CMD_APP_SEND_OP_COND 41
#define SD_CMD_APP_SEND_SCR 51
+#define MMC_KEY_SIZE (256*1024)
+#define EMMC_KEY_DEV (1)
+
static inline bool mmc_is_tuning_cmd(uint cmdidx)
{
if ((cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) ||
@@ -370,9 +372,6 @@
*/
#define MMC_NUM_BOOT_PARTITION 2
#define MMC_PART_RPMB 3 /* RPMB partition number */
-#define MMC_PART_BOOT1 2
-#define MMC_PART_BOOT0 1
-#define MMC_PART_USER 0
/* Driver model support */
@@ -505,7 +504,7 @@
int dm_mmc_get_wp(struct udevice *dev);
int dm_mmc_execute_tuning(struct udevice *dev, uint opcode);
int dm_mmc_wait_dat0(struct udevice *dev, int state, int timeout);
-
+int mmc_ffu_op(int dev, u64 ffu_ver, void *addr, u64 cnt);
/* Transition functions for compatibility */
int mmc_set_ios(struct mmc *mmc);
void mmc_send_init_stream(struct mmc *mmc);
@@ -621,6 +620,7 @@
uint scr[2];
uint csd[4];
uint cid[4];
+ char key_stamp;
ushort rca;
u8 part_support;
u8 part_attr;
@@ -674,6 +674,7 @@
* accessing the boot partitions
*/
u32 quirks;
+ bool is_gpt;
};
struct mmc_hwpart_conf {
@@ -697,6 +698,12 @@
MMC_HWPART_CONF_COMPLETE,
};
+struct aml_key_info {
+ u64 checksum;
+ u32 stamp;
+ u32 magic;
+};
+
struct mmc *mmc_create(const struct mmc_config *cfg, void *priv);
/**
diff --git a/include/nand.h b/include/nand.h
index 763e6ea..735b819 100644
--- a/include/nand.h
+++ b/include/nand.h
@@ -22,7 +22,7 @@
#else
#if defined(CONFIG_NAND_FSL_ELBC) || defined(CONFIG_NAND_ATMEL)\
|| defined(CONFIG_NAND_FSL_IFC) || defined(CONFIG_SPI_NAND)\
- || defined(CONFIG_MESON_NFC)
+ || defined(CONFIG_MESON_NFC) || defined(CONFIG_MTD_SPI_NAND)
#define CONFIG_SYS_NAND_SELF_INIT
#endif
#endif
diff --git a/include/net.h b/include/net.h
index 51c099d..e3aa65a 100644
--- a/include/net.h
+++ b/include/net.h
@@ -345,6 +345,7 @@
#define PROT_IP 0x0800 /* IP protocol */
#define PROT_ARP 0x0806 /* IP ARP protocol */
+#define PROT_TEST 0x0808 /* Ethernet loopback test */
#define PROT_WOL 0x0842 /* ether-wake WoL protocol */
#define PROT_RARP 0x8035 /* IP ARP protocol */
#define PROT_VLAN 0x8100 /* IEEE 802.1q protocol */
@@ -537,7 +538,7 @@
enum proto_t {
BOOTP, RARP, ARP, TFTPGET, DHCP, PING, DNS, NFS, CDP, NETCONS, SNTP,
- TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL
+ TFTPSRV, TFTPPUT, LINKLOCAL, FASTBOOT, WOL, ETHLOOP
};
extern char net_boot_file_name[1024];/* Boot File name */
diff --git a/include/part.h b/include/part.h
index a3f2550..d217058 100644
--- a/include/part.h
+++ b/include/part.h
@@ -9,9 +9,6 @@
#include <blk.h>
#include <ide.h>
#include <uuid.h>
-#ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY
-#include <part_efi.h>
-#endif
#include <linux/list.h>
struct block_drvr {
@@ -68,11 +65,6 @@
#ifdef CONFIG_PARTITION_TYPE_GUID
char type_guid[UUID_STR_LEN + 1]; /* type GUID as string, if exists */
#endif
-#ifdef CONFIG_AML_GPT_SYNC_ENTIRE_ENTRY
- efi_guid_t partition_type_guid;
- efi_guid_t unique_partition_guid;
- gpt_entry_attributes attributes;
-#endif
#ifdef CONFIG_DOS_PARTITION
uchar sys_ind; /* partition type */
#endif
@@ -371,6 +363,13 @@
int is_valid_gpt_buf(struct blk_desc *dev_desc, void *buf);
/**
+ * erase_gpt_part_table() - erase Primary GPT and Backup GPT
+ *
+ * @return - '0' on success, otherwise error
+ */
+int erase_gpt_part_table(struct blk_desc *dev_desc);
+
+/**
* write_mbr_and_gpt_partitions() - write MBR, Primary GPT and Backup GPT
*
* @param dev_desc - block device descriptor
diff --git a/include/partition_table.h b/include/partition_table.h
index cdc25b0..3f08ac5 100644
--- a/include/partition_table.h
+++ b/include/partition_table.h
@@ -1,3 +1,8 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
#ifndef _PARTITION_TABLE_H
#define _PARTITION_TABLE_H
// #ifdef CONFIG_STORE_COMPATIBLE
@@ -54,6 +59,9 @@
extern int has_boot_slot;
extern int has_system_slot;
+extern bool dynamic_partition;
+extern bool vendor_boot_partition;
+extern bool gpt_partition;
extern int get_partition_from_dts(unsigned char * buffer);
diff --git a/include/phy.h b/include/phy.h
index b86fdfb..87bfe7a 100644
--- a/include/phy.h
+++ b/include/phy.h
@@ -240,6 +240,7 @@
int phy_xilinx_init(void);
int phy_mscc_init(void);
int phy_fixed_init(void);
+int phy_amlogic_init(void);
int board_phy_config(struct phy_device *phydev);
int get_phy_id(struct mii_dev *bus, int addr, int devad, u32 *phy_id);
diff --git a/include/ramdump.h b/include/ramdump.h
new file mode 100644
index 0000000..d851a80
--- /dev/null
+++ b/include/ramdump.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __RAMDUMP_H__
+#define __RAMDUMP_H__
+
+#define RAMDUMP_STICKY_DATA_MASK (0xFFFF)
+
+extern void check_ramdump(void);
+extern void ramdump_init(void);
+
+extern unsigned long ramdump_base;
+extern unsigned long ramdump_size;
+
+int ramdump_save_compress_data(void);
+
+#endif /* __RAMDUMP_H__ */
diff --git a/include/u-boot/sha256.h b/include/u-boot/sha256.h
index 9aa1251..25cad08 100644
--- a/include/u-boot/sha256.h
+++ b/include/u-boot/sha256.h
@@ -9,11 +9,25 @@
/* Reset watchdog each time we process this many bytes */
#define CHUNKSZ_SHA256 (64 * 1024)
+#define SHA224_DIGEST_SIZE 28
+#define SHA256_DIGEST_SIZE 32
+#define SHA256_BLOCK_SIZE 64
+
+/* SHA2 context */
typedef struct {
+ /* hardware SHA compile*/
+ uint32_t h[8];
+ uint32_t tot_len;
+ uint32_t len;
+ uint32_t digest_len;
+ uint8_t block[2 * SHA256_BLOCK_SIZE];
+ uint8_t buf[SHA256_DIGEST_SIZE]; /* Used to store the final digest. */
+ uint8_t tmp[12]; // temp sha bits counter saved here by hw.
+ /* software SHA compile*/
uint32_t total[2];
uint32_t state[8];
uint8_t buffer[64];
-} sha256_context;
+}sha2_ctx,sha256_context;
void sha256_starts(sha256_context * ctx);
void sha256_update(sha256_context *ctx, const uint8_t *input, uint32_t length);
diff --git a/include/usb.h b/include/usb.h
index 0881477..370013d 100644
--- a/include/usb.h
+++ b/include/usb.h
@@ -17,8 +17,10 @@
#include <asm/cache.h>
#include <part.h>
-#define HEHE_DEBUG(x...) printf(x)
-//#define HEHE_DEBUG(x...)
+struct usb_string {
+ u8 id;
+ const char *s;
+};
/* get from ch9.h fix compile error. start */
struct usb_ss_ep_comp_descriptor {
@@ -1113,5 +1115,6 @@
unsigned short *portstat);
int usb_tuning_port(struct usb_device *udev, int port);
+int usb_aml_detect_operation(int argc, char * const argv[]);
#endif /*_USB_H_ */
diff --git a/include/usb/crg_udc.h b/include/usb/crg_udc.h
new file mode 100644
index 0000000..2144e15
--- /dev/null
+++ b/include/usb/crg_udc.h
@@ -0,0 +1,372 @@
+/* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
+/*
+ * Copyright (c) 2019 Amlogic, Inc. All rights reserved.
+ */
+
+#ifndef __CRG_UDC_H__
+#define __CRG_UDC_H__
+
+#define CRG_UCCR_OFFSET 0x2400
+#define CRG_UICR_OFFSET 0x2500
+#define CRG_UICR_STRIDE 0x20
+
+/* corigine usb 3.0 device core register macros */
+struct crg_uccr {
+ u32 capability; /*0x00*/
+ u32 resv0[3];
+
+ u32 config0; /*0x10*/
+ u32 config1;
+ u32 resv1[2];
+
+ u32 control; /*0x20*/
+ u32 status;
+ u32 dcbaplo;
+ u32 dcbaphi;
+ u32 portsc;
+ u32 u3portpmsc;
+ u32 u2portpmsc;
+ u32 u3portli;
+
+ u32 doorbell; /*0x40*/
+ u32 mfindex;
+ u32 speed_select;
+ u32 resv3[5];
+
+ u32 ep_enable; /*0x60*/
+ u32 ep_running;
+ u32 resv4[2];
+
+ u32 cmd_param0; /*0x70*/
+ u32 cmd_param1;
+ u32 cmd_control;
+ u32 resv5[1];
+
+ u32 odb_capability; /*0x80*/
+ u32 resv6[3];
+ u32 odb_config[8];
+
+ u32 debug0; /*0xB0*/
+};
+
+struct crg_uicr {
+ u32 iman;
+ u32 imod;
+ u32 erstsz;
+ u32 resv0;
+
+ u32 erstbalo; /*0x10*/
+ u32 erstbahi;
+ u32 erdplo;
+ u32 erdphi;
+};
+
+
+#define SETF_VAR(field, var, fieldval) \
+ (var = (((var) & ~(field ## _MASK)) | \
+ (((fieldval) << field ## _SHIFT) & (field ## _MASK))))
+
+#define GETF(field, val) \
+ (((val) & (field ## _MASK)) >> (field ## _SHIFT))
+
+
+#define MAKEF_VAR(field, fieldval) \
+ (((fieldval) << field ## _SHIFT) & (field ## _MASK))
+
+/* interrupt registers array */
+#define CRG_U3DC_IRS_BASE (0x100L)
+#define CRG_U3DC_IRS_IMAN(x) (CRG_U3DC_IRS_BASE + x*0x20L + 0x00L)
+#define CRG_U3DC_IRS_IMOD(x) (CRG_U3DC_IRS_BASE + x*0x20L + 0x04L)
+#define CRG_U3DC_IRS_ERSTSZ(x) (CRG_U3DC_IRS_BASE + x*0x20L + 0x08L)
+#define CRG_U3DC_IRS_ERSTBALO(x) (CRG_U3DC_IRS_BASE + x*0x20L + 0x10L)
+#define CRG_U3DC_IRS_ERSTBAHI(x) (CRG_U3DC_IRS_BASE + x*0x20L + 0x14L)
+#define CRG_U3DC_IRS_ERDPLO(x) (CRG_U3DC_IRS_BASE + x*0x20L + 0x18L)
+#define CRG_U3DC_IRS_ERDPHI(x) (CRG_U3DC_IRS_BASE + x*0x20L + 0x20L)
+
+/* reg config 0 & 1*/
+#define CRG_U3DC_CFG0_MAXSPEED_MASK (0xfL<<0)
+#define CRG_U3DC_CFG0_MAXSPEED_FS (0x1L<<0)
+#define CRG_U3DC_CFG0_MAXSPEED_HS (0x3L<<0)
+#define CRG_U3DC_CFG0_MAXSPEED_SS (0x4L<<0)
+#define CRG_U3DC_CFG0_MAXSPEED_SSP (0x5L<<0)
+
+#define CRG_U3DC_CFG1_CSC_EVENT_EN (0x1L<<0)
+#define CRG_U3DC_CFG1_PEC_EVENT_EN (0x1L<<1)
+#define CRG_U3DC_CFG1_PPC_EVENT_EN (0x1L<<3)
+#define CRG_U3DC_CFG1_PRC_EVENT_EN (0x1L<<4)
+#define CRG_U3DC_CFG1_PLC_EVENT_EN (0x1L<<5)
+#define CRG_U3DC_CFG1_CEC_EVENT_EN (0x1L<<6)
+
+#define CRG_U3DC_CFG1_U3_ENTRY_EN (0x1L<<8)
+#define CRG_U3DC_CFG1_L1_ENTRY_EN (0x1L<<9)
+#define CRG_U3DC_CFG1_U3_RESUME_EN (0x1L<<10)
+#define CRG_U3DC_CFG1_L1_RESUME_EN (0x1L<<11)
+#define CRG_U3DC_CFG1_INACTIVE_PLC_EN (0x1L<<12)
+#define CRG_U3DC_CFG1_U3_RESUME_NORESP_PLC_EN (0x1L<<13)
+#define CRG_U3DC_CFG1_U2_RESUME_NORESP_PLC_EN (0x1L<<14)
+
+#define CRG_U3DC_CFG1_SETUP_EVENT_EN (0x1L<<16)
+
+
+/* ctrl register*/
+#define CRG_U3DC_CTRL_RUN (1L<<0)
+#define CRG_U3DC_CTRL_STOP (0L<<0)
+#define CRG_U3DC_CTRL_SWRST (1L<<1)
+#define CRG_U3DC_CTRL_INT_EN (1L<<2)
+#define CRG_U3DC_CTRL_SYSERR_EN (1L<<3)/*only AXI bus error*/
+#define CRG_U3DC_CTRL_EWE (1L<<10)
+#define CRG_U3DC_CTRL_KP_CNCT (1L<<11)
+
+/*status register*/
+#define CRG_U3DC_STATUS_DEV_CTRL_HALT (1L << 0)
+#define CRG_U3DC_STATUS_SYS_ERR (1L << 2)
+#define CRG_U3DC_STATUS_EINT (1L << 3)
+
+/*portsc register*/
+#define CRG_U3DC_PORTSC_CCS (1L << 0)
+#define CRG_U3DC_PORTSC_PED (1L << 1)
+#define CRG_U3DC_PORTSC_PP (1L << 3)
+#define CRG_U3DC_PORTSC_PR (1L << 4)
+
+#define CRG_U3DC_PORTSC_PLS_SHIFT (5)
+#define CRG_U3DC_PORTSC_PLS_MASK (0xf << CRG_U3DC_PORTSC_PLS_SHIFT)
+#define CRG_U3DC_PORTSC_PLS(fv) (MAKEF_VAR(CRG_U3DC_PORTSC_PLS, (fv)))
+#define CRG_U3DC_PORTSC_PLS_GET(v) (GETF(CRG_U3DC_PORTSC_PLS, (v)))
+
+#define CRG_U3DC_PORTSC_SPEED_SHIFT (10)
+#define CRG_U3DC_PORTSC_SPEED_MASK \
+ (0xf << CRG_U3DC_PORTSC_SPEED_SHIFT)
+#define CRG_U3DC_PORTSC_SPEED(fv) \
+ (MAKEF_VAR(CRG_U3DC_PORTSC_SPEED, (fv)))
+#define CRG_U3DC_PORTSC_SPEED_GET(v) \
+ (GETF(CRG_U3DC_PORTSC_SPEED, (v)))
+#define CRG_U3DC_PORTSC_SPEED_FS (0x1)
+#define CRG_U3DC_PORTSC_SPEED_LS (0x2)
+#define CRG_U3DC_PORTSC_SPEED_HS (0x3)
+#define CRG_U3DC_PORTSC_SPEED_SS (0x4)
+#define CRG_U3DC_PORTSC_SPEED_SSP (0x5)
+
+#define CRG_U3DC_PORTSC_LWS (1L << 16)
+#define CRG_U3DC_PORTSC_CSC (1L << 17)
+#define CRG_U3DC_PORTSC_PEC (1L << 18)
+#define CRG_U3DC_PORTSC_PPC (1L << 20)
+#define CRG_U3DC_PORTSC_PRC (1L << 21)
+#define CRG_U3DC_PORTSC_PLC (1L << 22)
+#define CRG_U3DC_PORTSC_CEC (1L << 23)
+#define CRG_U3DC_PORTSC_WCE (1L << 25)
+#define CRG_U3DC_PORTSC_WDE (1L << 26)
+#define CRG_U3DC_PORTSC_WPR (1L << 31)
+
+#define PORTSC_W1C_MASK (CRG_U3DC_PORTSC_CSC | \
+ CRG_U3DC_PORTSC_PEC | \
+ CRG_U3DC_PORTSC_PPC | \
+ CRG_U3DC_PORTSC_PRC | \
+ CRG_U3DC_PORTSC_PLC | \
+ CRG_U3DC_PORTSC_CEC)
+#define PORTSC_WRITE_MASK (~PORTSC_W1C_MASK)
+
+
+/* u3portpmsc */
+#define CRG_U3DC_U3PORTPM_U1TMOUT_SHIFT (0)
+#define CRG_U3DC_U3PORTPM_U1TMOUT_MASK \
+ (0xff << CRG_U3DC_U3PORTPM_U1TMOUT_SHIFT)
+#define CRG_U3DC_U3PORTPM_U1TMOUT(fv) \
+ (MAKEF_VAR(CRG_U3DC_U3PORTPM_U1TMOUT, (fv)))
+
+#define CRG_U3DC_U3PORTPM_U2TMOUT_SHIFT (8)
+#define CRG_U3DC_U3PORTPM_U2TMOUT_MASK \
+ (0xff << CRG_U3DC_U3PORTPM_U2TMOUT_SHIFT)
+#define CRG_U3DC_U3PORTPM_U2TMOUT(fv) \
+ (MAKEF_VAR(CRG_U3DC_U3PORTPM_U2TMOUT, (fv)))
+
+#define CRG_U3DC_U3PORTPM_FLA (1L << 16)
+
+#define CRG_U3DC_U3PORTPM_U1IEN_SHIFT (20)
+#define CRG_U3DC_U3PORTPM_U1IEN \
+ (1L << CRG_U3DC_U3PORTPM_U1IEN_SHIFT)
+
+#define CRG_U3DC_U3PORTPM_U2IEN_SHIFT (21)
+#define CRG_U3DC_U3PORTPM_U2IEN \
+ (1L << CRG_U3DC_U3PORTPM_U2IEN_SHIFT)
+
+#define CRG_U3DC_U3PORTPM_U1AEN_SHIFT (22)
+#define CRG_U3DC_U3PORTPM_U1AEN \
+ (1L << CRG_U3DC_U3PORTPM_U1AEN_SHIFT)
+
+#define CRG_U3DC_U3PORTPM_U2AEN_SHIFT (23)
+#define CRG_U3DC_U3PORTPM_U2AEN \
+ (1L << CRG_U3DC_U3PORTPM_U2AEN_SHIFT)
+
+#define CRG_U3DC_U3PORTPM_U1U2TMOUT_SHIFT (24)
+#define CRG_U3DC_U3PORTPM_U1U2TMOUT_MASK \
+ (0xff << CRG_U3DC_U3PORTPM_U1U2TMOUT_SHIFT)
+
+/* u2portpmsc */
+#define CRG_U3DC_U2PORTPM_RJ_TH_SHIFT (0)
+#define CRG_U3DC_U2PORTPM_RJ_TH_MASK \
+ (0xf << CRG_U3DC_U2PORTPM_RJ_TH_SHIFT)
+#define CRG_U3DC_U2PORTPM_RJ_TH(fv) \
+ (MAKEF_VAR(CRG_U3DC_U2PORTPM_RJ_TH, (fv)))
+
+#define CRG_U3DC_U2PORTPM_DS_TH_SHIFT (4)
+#define CRG_U3DC_U2PORTPM_DS_TH_MASK \
+ (0xf << CRG_U3DC_U2PORTPM_DS_TH_SHIFT)
+#define CRG_U3DC_U2PORTPM_DS_TH(fv) \
+ (MAKEF_VAR(CRG_U3DC_U2PORTPM_DS_TH, (fv)))
+
+#define CRG_U3DC_U2PORTPM_LPM_EN (0x1 << 8)
+#define CRG_U3DC_U2PORTPM_RJ_TH_EN (0x1 << 9)
+#define CRG_U3DC_U2PORTPM_DS_EN (0x1 << 10)
+#define CRG_U3DC_U2PORTPM_SLP_EN (0x1 << 11)
+#define CRG_U3DC_U2PORTPM_LPM_FACK (0x1 << 12)
+#define CRG_U3DC_U2PORTPM_L1_AEX (0x1 << 13)
+#define CRG_U3DC_U2PORTPM_H_B_SHIFT (16)
+#define CRG_U3DC_U2PORTPM_H_B_MASK \
+ (0xf << CRG_U3DC_U2PORTPM_H_B_SHIFT)
+#define CRG_U3DC_U2PORTPM_H_B(fv) \
+ (MAKEF_VAR(CRG_U3DC_U2PORTPM_H_B, (fv)))
+
+#define CRG_U3DC_U2PORTPM_RWE (0x1 << 20)
+
+#define CRG_U3DC_U2PORTPM_TM_SHIFT (28)
+#define CRG_U3DC_U2PORTPM_TM_MASK \
+ (0xf << CRG_U3DC_U2PORTPM_TM_SHIFT)
+#define CRG_U3DC_U2PORTPM_TM(fv) \
+ (MAKEF_VAR(CRG_U3DC_U2PORTPM_TM, (fv)))
+
+/* doorbell register*/
+#define CRG_U3DC_DB_TARGET_SHIFT (0)
+#define CRG_U3DC_DB_TARGET_MASK \
+ (0x1f << CRG_U3DC_DB_TARGET_SHIFT)
+#define CRG_U3DC_DB_TARGET(fv) \
+ (MAKEF_VAR(CRG_U3DC_DB_TARGET, (fv)))
+
+/* odb registers*/
+#define CRG_U3DC_ODBCFG_2N_OFFSET_SHIFT (0)
+#define CRG_U3DC_ODBCFG_2N_OFFSET_MASK \
+ (0x3ff << CRG_U3DC_ODBCFG_2N_OFFSET_SHIFT)
+#define CRG_U3DC_ODBCFG_2N_OFFSET(fv) \
+ (MAKEF_VAR(CRG_U3DC_ODBCFG_2N_OFFSET, (fv)))
+
+#define CRG_U3DC_ODBCFG_2N_SIZE_SHIFT (10)
+#define CRG_U3DC_ODBCFG_2N_SIZE_MASK \
+ (0x7 << CRG_U3DC_ODBCFG_2N_SIZE_SHIFT)
+#define CRG_U3DC_ODBCFG_2N_SIZE(fv) \
+ (MAKEF_VAR(CRG_U3DC_ODBCFG_2N_SIZE, (fv)))
+
+#define CRG_U3DC_ODBCFG_2N1_OFFSET_SHIFT (16)
+#define CRG_U3DC_ODBCFG_2N1_OFFSET_MASK \
+ (0x3ff << CRG_U3DC_ODBCFG_2N1_OFFSET_SHIFT)
+#define CRG_U3DC_ODBCFG_2N1_OFFSET(fv) \
+ (MAKEF_VAR(CRG_U3DC_ODBCFG_2N1_OFFSET, (fv)))
+
+#define CRG_U3DC_ODBCFG_2N1_SIZE_SHIFT (26)
+#define CRG_U3DC_ODBCFG_2N1_SIZE_MASK \
+ (0x7 << CRG_U3DC_ODBCFG_2N1_SIZE_SHIFT)
+#define CRG_U3DC_ODBCFG_2N1_SIZE(fv) \
+ (MAKEF_VAR(CRG_U3DC_ODBCFG_2N1_SIZE, (fv)))
+
+
+/* command control register*/
+#define CRG_U3DC_CMD_CTRL_ACTIVE_SHIFT (0)
+#define CRG_U3DC_CMD_CTRL_ACTIVE \
+ (1L<<CRG_U3DC_CMD_CTRL_ACTIVE_SHIFT)
+#define CRG_U3DC_CMD_CTRL_IOC_SHIFT (1)
+#define CRG_U3DC_CMD_CTRL_IOC_EN \
+ (1L<<CRG_U3DC_CMD_CTRL_IOC_SHIFT)
+
+#define CRG_U3DC_CMD_CTRL_TYPE_SHIFT (4)
+#define CRG_U3DC_CMD_CTRL_TYPE_MASK \
+ (0xf<<CRG_U3DC_CMD_CTRL_TYPE_SHIFT)
+#define CRG_U3DC_CMD_CTRL_TYPE(fv) \
+ (MAKEF_VAR(CRG_U3DC_CMD_CTRL_TYPE, (fv)))
+
+#define CRG_U3DC_CMD_CTRL_STATUS_SHIFT (16)
+#define CRG_U3DC_CMD_CTRL_STATUS_MASK \
+ (0xf<<CRG_U3DC_CMD_CTRL_STATUS_SHIFT)
+#define CRG_U3DC_CMD_CTRL_STATUS(fv) \
+ (MAKEF_VAR(CRG_U3DC_CMD_CTRL_STATUS, (fv)))
+#define CRG_U3DC_CMD_CTRL_STATUS_GET(v) \
+ (GETF(CRG_U3DC_CMD_CTRL_STATUS, (v)))
+
+
+#define CRG_U3DC_CMD_INIT_EP0 (0L)
+#define CRG_U3DC_CMD_UPDATE_EP0 (1L)
+#define CRG_U3DC_CMD_SET_ADDRESS (2L)
+#define CRG_U3DC_CMD_SEND_DEV_NOTIFY (3L)
+#define CRG_U3DC_CMD_CONFIG_EP (4L)
+#define CRG_U3DC_CMD_SET_HALT (5L)
+#define CRG_U3DC_CMD_CLR_HALT (6L)
+#define CRG_U3DC_CMD_RST_SEQNUM (7L)
+#define CRG_U3DC_CMD_STOP_EP (8L)
+#define CRG_U3DC_CMD_SET_TR_DQPTR (9L)
+#define CRG_U3DC_CMD_FORCE_FLOW_CTRL (10L)
+#define CRG_U3DC_CMD_REQ_LDM_EXCHAG (11L)
+
+/* int register*/
+/* iman bits*/
+#define CRG_U3DC_IMAN_INT_PEND (1L << 0)
+#define CRG_U3DC_IMAN_INT_EN (1L << 1)
+
+/* erdp bits*/
+#define CRG_U3DC_ERDPLO_EHB (1 << 3)
+#define CRG_U3DC_ERDPLO_ADDRLO(fv) ((fv) & 0xfffffff0)
+/**/
+
+
+/*command params*/
+/*command0 init ep0*/
+#define CRG_CMD0_0_DQPTRLO_SHIFT (4)
+#define CRG_CMD0_0_DQPTRLO_MASK \
+ (0x0fffffff << CRG_CMD0_0_DQPTRLO_SHIFT)
+
+#define CRG_CMD0_0_DCS_SHIFT (0)
+#define CRG_CMD0_0_DCS_MASK (0x1 << CRG_CMD0_0_DCS_SHIFT)
+#define CRG_CMD0_0_DCS(fv) (MAKEF_VAR(CRG_CMD0_0_DCS, (fv)))
+
+/*command1 update ep0 */
+#define CRG_CMD1_0_MPS_SHIFT (16)
+#define CRG_CMD1_0_MPS_MASK (0xffff << CRG_CMD1_0_MPS_SHIFT)
+#define CRG_CMD1_0_MPS(fv) (MAKEF_VAR(CRG_CMD1_0_MPS, (fv)))
+
+/*command2 set addr */
+#define CRG_CMD2_0_DEV_ADDR_SHIFT (0)
+#define CRG_CMD2_0_DEV_ADDR_MASK (0xff << CRG_CMD2_0_DEV_ADDR_SHIFT)
+#define CRG_CMD2_0_DEV_ADDR(fv) (MAKEF_VAR(CRG_CMD2_0_DEV_ADDR, (fv)))
+
+
+
+/*command type*/
+enum crg_cmd_type {
+ CRG_CMD_INIT_EP0 = 0,
+ CRG_CMD_UPDATE_EP0_CFG = 1,
+ CRG_CMD_SET_ADDR = 2,
+ CRG_CMD_SEND_DEV_NOTIFICATION = 3,
+ CRG_CMD_CONFIG_EP = 4,
+ CRG_CMD_SET_HALT = 5,
+ CRG_CMD_CLEAR_HALT = 6,
+ CRG_CMD_RESET_SEQNUM = 7,
+ CRG_CMD_STOP_EP = 8,
+ CRG_CMD_SET_TR_DQPTR = 9,
+ CRG_CMD_FORCE_FLOW_CONTROL = 10,
+ CRG_CMD_REQ_LDM_EXCHANGE = 11
+};
+
+#define reg_read readl
+#define reg_write(a, v) writel(v, a)
+
+struct crg_gadget_dev;
+
+extern struct crg_gadget_dev *
+ crg_gadget_init(void __iomem *udc_mmio_base, int controller_index);
+
+extern int crg_gadget_remove(struct crg_gadget_dev *crg_udc);
+
+
+struct crg_udc_platdata {
+ int num_out_eps;
+ int num_in_eps;
+};
+
+
+#endif /* __CRG_UDC_H__ */
diff --git a/include/usb_tcpc.h b/include/usb_tcpc.h
new file mode 100644
index 0000000..41d4309
--- /dev/null
+++ b/include/usb_tcpc.h
@@ -0,0 +1,22 @@
+#ifndef __USB_TCPC_H
+#define __USB_TCPC_H
+
+/**
+ * struct tcpc_uc_plat - Platform data the uclass stores about each device
+ *
+ * @label: tcpc label
+ */
+struct tcpc_uc_plat {
+ const char *label;
+};
+
+/**
+ * struct tcpc_uc_priv - Private data the uclass stores about each device
+ *
+ */
+struct tcpc_uc_priv {
+};
+
+int tcpc_init(void);
+
+#endif
diff --git a/include/zircon/driver-config.h b/include/zircon/driver-config.h
deleted file mode 100644
index b3bf01c..0000000
--- a/include/zircon/driver-config.h
+++ /dev/null
@@ -1,77 +0,0 @@
-// Copyright 2018 The Fuchsia Authors. All rights reserved.
-// Use of this source code is governed by a BSD-style license that can be
-// found in the LICENSE file.
-
-#pragma once
-
-// BOOTDATA_KERNEL_DRIVER bootdata types
-#define KDRV_ARM_PSCI 0x49435350 // 'PSCI'
-#define KDRV_ARM_GIC_V2 0x32434947 // 'GIC2'
-#define KDRV_ARM_GIC_V3 0x33434947 // 'GIC3'
-#define KDRV_ARM_GENERIC_TIMER 0x4D495441 // 'ATIM'
-#define KDRV_PL011_UART 0x55304C50 // 'PL0U'
-#define KDRV_AMLOGIC_UART 0x554C4D41 // 'AMLU'
-#define KDRV_NXP_IMX_UART 0x55584D49 // 'IMXU'
-#define KDRV_HISILICON_POWER 0x4F505348 // 'HSPO'
-#define KDRV_AMLOGIC_HDCP 0x484C4D41 // 'AMLH'
-
-// kernel driver struct that can be used for simple drivers
-// used by KDRV_PL011_UART, KDRV_AMLOGIC_UART and KDRV_NXP_IMX_UART
-typedef struct {
- uint64_t mmio_phys;
- uint32_t irq;
-} dcfg_simple_t;
-
-// for KDRV_ARM_PSCI
-typedef struct {
- bool use_hvc;
- uint64_t shutdown_args[3];
- uint64_t reboot_args[3];
- uint64_t reboot_bootloader_args[3];
- uint64_t reboot_recovery_args[3];
-} dcfg_arm_psci_driver_t;
-
-// for KDRV_ARM_GIC_V2
-typedef struct {
- uint64_t mmio_phys;
- uint64_t msi_frame_phys;
- uint64_t gicd_offset;
- uint64_t gicc_offset;
- uint64_t gich_offset;
- uint64_t gicv_offset;
- uint32_t ipi_base;
- bool optional;
- bool use_msi;
-} dcfg_arm_gicv2_driver_t;
-
-// for KDRV_ARM_GIC_V3
-typedef struct {
- uint64_t mmio_phys;
- uint64_t gicd_offset;
- uint64_t gicr_offset;
- uint64_t gicr_stride;
- uint64_t mx8_gpr_phys;
- uint32_t ipi_base;
- bool optional;
-} dcfg_arm_gicv3_driver_t;
-
-// for KDRV_ARM_GENERIC_TIMER
-typedef struct {
- uint32_t irq_phys;
- uint32_t irq_virt;
- uint32_t irq_sphys;
- uint32_t freq_override;
-} dcfg_arm_generic_timer_driver_t;
-
-// for KDRV_HISILICON_POWER
-typedef struct {
- uint64_t sctrl_phys;
- uint64_t pmu_phys;
-} dcfg_hisilicon_power_driver_t;
-
-// for KDRV_AMLOGIC_HDCP
-typedef struct {
- uint64_t preset_phys;
- uint64_t hiu_phys;
- uint64_t hdmitx_phys;
-} dcfg_amlogic_hdcp_driver_t;
diff --git a/include/zircon/gpt.h b/include/zircon/gpt.h
deleted file mode 100644
index 4d0a1aa..0000000
--- a/include/zircon/gpt.h
+++ /dev/null
@@ -1,101 +0,0 @@
-/*
- * Copyright (c) 2018 The Fuchsia Authors
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef _ZIRCON_GPT_H_
-#define _ZIRCON_GPT_H_
-
-// GUID for a system partition
-#define GUID_SYSTEM_STRING "606B000B-B7C7-4653-A7D5-B737332C899D"
-#define GUID_SYSTEM_VALUE { \
- 0x0b, 0x00, 0x6b, 0x60, \
- 0xc7, 0xb7, \
- 0x53, 0x46, \
- 0xa7, 0xd5, 0xb7, 0x37, 0x33, 0x2c, 0x89, 0x9d \
-}
-
-// GUID for a data partition
-#define GUID_DATA_STRING "08185F0C-892D-428A-A789-DBEEC8F55E6A"
-#define GUID_DATA_VALUE { \
- 0x0c, 0x5f, 0x18, 0x08, \
- 0x2d, 0x89, \
- 0x8a, 0x42, \
- 0xa7, 0x89, 0xdb, 0xee, 0xc8, 0xf5, 0x5e, 0x6a \
-}
-
-// GUID for a installer partition
-#define GUID_INSTALL_STRING "48435546-4953-2041-494E-5354414C4C52"
-#define GUID_INSTALL_VALUE { \
- 0x46, 0x55, 0x43, 0x48, \
- 0x53, 0x49, \
- 0x41, 0x20, \
- 0x49, 0x4E, 0x53, 0x54, 0x41, 0x4C, 0x4C, 0x52 \
-}
-
-#define GUID_BLOB_STRING "2967380E-134C-4CBB-B6DA-17E7CE1CA45D"
-#define GUID_BLOB_VALUE { \
- 0x0e, 0x38, 0x67, 0x29, \
- 0x4c, 0x13, \
- 0xbb, 0x4c, \
- 0xb6, 0xda, 0x17, 0xe7, 0xce, 0x1c, 0xa4, 0x5d \
-}
-
-#define GUID_FVM_STRING "41D0E340-57E3-954E-8C1E-17ECAC44CFF5"
-#define GUID_FVM_VALUE { \
- 0x40, 0xe3, 0xd0, 0x41, \
- 0xe3, 0x57, \
- 0x4e, 0x95, \
- 0x8c, 0x1e, 0x17, 0xec, 0xac, 0x44, 0xcf, 0xf5 \
-}
-
-#define GUID_ZIRCON_A_STRING "DE30CC86-1F4A-4A31-93C4-66F147D33E05"
-#define GUID_ZIRCON_A_VALUE { \
- 0x86, 0xcc, 0x30, 0xde, \
- 0x4a, 0x1f, \
- 0x31, 0x4a, \
- 0x93, 0xc4, 0x66, 0xf1, 0x47, 0xd3, 0x3e, 0x05, \
-}
-
-#define GUID_ZIRCON_B_STRING "23CC04DF-C278-4CE7-8471-897D1A4BCDF7"
-#define GUID_ZIRCON_B_VALUE { \
- 0xdf, 0x04, 0xcc, 0x23, \
- 0x78, 0xc2, \
- 0xe7, 0x4c, \
- 0x84, 0x71, 0x89, 0x7d, 0x1a, 0x4b, 0xcd, 0xf7 \
-}
-
-#define GUID_ZIRCON_R_STRING "A0E5CF57-2DEF-46BE-A80C-A2067C37CD49"
-#define GUID_ZIRCON_R_VALUE { \
- 0x57, 0xcf, 0xe5, 0xa0, \
- 0xef, 0x2d, \
- 0xbe, 0x46, \
- 0xa8, 0x0c, 0xa2, 0x06, 0x7c, 0x37, 0xcd, 0x49 \
-}
-
-#define GUID_SYS_CONFIG_STRING "4E5E989E-4C86-11E8-A15B-480FCF35F8E6"
-#define GUID_SYS_CONFIG_VALUE { \
- 0x9e, 0x98, 0x5e, 0x4e, \
- 0x86, 0x4c, \
- 0xe8, 0x11, \
- 0xa1, 0x5b, 0x48, 0x0f, 0xcf, 0x35, 0xf8, 0xe6 \
-}
-
-#define GUID_FACTORY_CONFIG_STRING "5A3A90BE-4C86-11E8-A15B-480FCF35F8E6"
-#define GUID_FACTORY_CONFIG_VALUE { \
- 0xbe, 0x90, 0x3a, 0x5a, \
- 0x86, 0x4c, \
- 0xe8, 0x11, \
- 0xa1, 0x5b, 0x48, 0x0f, 0xcf, 0x35, 0xf8, 0xe6 \
-}
-
-#define GUID_BOOTLOADER_STRING "5ECE94FE-4C86-11E8-A15B-480FCF35F8E6"
-#define GUID_BOOTLOADER_VALUE { \
- 0xfe, 0x94, 0xce, 0x5e, \
- 0x86, 0x4c, \
- 0xe8, 0x11, \
- 0xa1, 0x5b, 0x48, 0x0f, 0xcf, 0x35, 0xf8, 0xe6 \
-}
-
-#endif /* _ZIRCON_GPT_H_ */
diff --git a/include/zircon/image.h b/include/zircon/image.h
deleted file mode 100644
index 48ed84b..0000000
--- a/include/zircon/image.h
+++ /dev/null
@@ -1,478 +0,0 @@
-/*
- * Copyright (c) 2018 The Fuchsia Authors
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef _ZIRCON_IMAGE_H_
-#define _ZIRCON_IMAGE_H_
-
-// Zircon Boot Image format (ZBI).
-//
-// A Zircon Boot Image consists of a container header followed by boot
-// items. Each boot item has a header (zbi_header_t) and then a payload of
-// zbi_header_t.length bytes, which can be any size. The zbi_header_t.type
-// field indicates how to interpret the payload. Many types specify an
-// additional type-specific header that begins a variable-sized payload.
-// zbi_header_t.length does not include the zbi_header_t itself, but does
-// include any type-specific headers as part of the payload. All fields in
-// all header formats are little-endian.
-//
-// Padding bytes appear after each item as needed to align the payload size
-// up to a ZBI_ALIGNMENT (8-byte) boundary. This padding is not reflected
-// in the zbi_header_t.length value.
-//
-// A "complete" ZBI can be booted by a Zircon-compatible boot loader.
-// It contains one ZBI_TYPE_KERNEL_{ARCH} boot item that must come first,
-// followed by any number of additional boot items, which must include
-// exactly one ZBI_TYPE_STORAGE_BOOTFS item.
-//
-// A partial ZBI cannot be booted, and is only used during the build process.
-// It contains one or more boot items and can be combined with other ZBIs to
-// make a complete ZBI.
-
-// All items begin at an 8-byte aligned offset into the image.
-#define ZBI_ALIGNMENT (8)
-
-// Round n up to the next 8 byte boundary
-#define ZBI_ALIGN(n) (((n) + ZBI_ALIGNMENT - 1) & -ZBI_ALIGNMENT)
-
-// LSW of sha256("bootdata")
-#define ZBI_CONTAINER_MAGIC (0x868cf7e6)
-
-// LSW of sha256("bootitem")
-#define ZBI_ITEM_MAGIC (0xb5781729)
-
-// This flag is always required.
-#define ZBI_FLAG_VERSION (0x00010000)
-
-// ZBI items with the CRC32 flag must have a valid crc32.
-// Otherwise their crc32 field must contain ZBI_ITEM_NO_CRC32
-#define ZBI_FLAG_CRC32 (0x00020000)
-
-// Value for zbi_header_t.crc32 when ZBI_FLAG_CRC32 is not set.
-#define ZBI_ITEM_NO_CRC32 (0x4a87e8d6)
-
-#ifndef __ASSEMBLER__
-// Each header must be 8-byte aligned. The length field specifies the
-// actual payload length and does not include the size of padding.
-typedef struct {
- // ZBI_TYPE_* constant, see below.
- uint32_t type;
-
- // Size of the payload immediately following this header. This
- // does not include the header itself nor any alignment padding
- // after the payload.
- uint32_t length;
-
- // Type-specific extra data. Each type specifies the use of this
- // field; see below. When not explicitly specified, it should be zero.
- uint32_t extra;
-
- // Flags for this item. This must always include ZBI_FLAG_VERSION.
- // It should contain ZBI_FLAG_CRC32 for any item where it's feasible
- // to compute the CRC32 at build time. Other flags are specific to
- // each type; see below.
- uint32_t flags;
-
- // For future expansion. Set to 0.
- uint32_t reserved0;
- uint32_t reserved1;
-
- // Must be ZBI_ITEM_MAGIC.
- uint32_t magic;
-
- // Must be the CRC32 of payload if ZBI_FLAG_CRC32 is set,
- // otherwise must be ZBI_ITEM_NO_CRC32.
- uint32_t crc32;
-} zbi_header_t;
-#endif
-
-// Each ZBI starts with a container header.
-// length: Total size of the image after this header.
-// This includes all item headers, payloads, and padding.
-// It does not include the container header itself.
-// Must be a multiple of ZBI_ALIGNMENT.
-// extra: Must be ZBI_CONTAINER_MAGIC.
-// flags: Must be ZBI_FLAG_VERSION and no other flags.
-#define ZBI_TYPE_CONTAINER (0x544f4f42) // BOOT
-
-// Define a container header in assembly code. The symbol name is defined
-// as a local label; use .global symbol to make it global. The length
-// argument can use assembly label arithmetic like any immediate operand.
-#ifdef __ASSEMBLER__
-#define ZBI_CONTAINER_HEADER(symbol, length) \
- .balign ZBI_ALIGNMENT; \
- symbol: \
- .int ZBI_TYPE_CONTAINER; \
- .int (length); \
- .int ZBI_CONTAINER_MAGIC; \
- .int ZBI_FLAG_VERSION; \
- .int 0; \
- .int 0; \
- .int ZBI_ITEM_MAGIC; \
- .int ZBI_ITEM_NO_CRC32; \
- .size symbol, . - symbol; \
- .type symbol, %object
-#endif
-
-
-// The kernel image. In a complete ZBI this item must always be first,
-// immediately after the ZBI_TYPE_CONTAINER header. The contiguous memory
-// image of the kernel is formed from the ZBI_TYPE_CONTAINER header, the
-// ZBI_TYPE_KERNEL_{ARCH} header, and the payload.
-//
-// The boot loader loads the whole image starting with the container header
-// through to the end of the kernel item's payload into contiguous physical
-// memory. It then constructs a partial ZBI elsewhere in memory, which has
-// a ZBI_TYPE_CONTAINER header of its own followed by all the other items
-// that were in the booted ZBI plus other items synthesized by the boot
-// loader to describe the machine. The precise protocol for transferring
-// control to the kernel's entry point varies by machine.
-//
-// TODO(mcgrathr): On all machines, the kernel requires some amount of
-// scratch memory to be available immediately after the kernel image at
-// boot. It needs this space for early setup work before it has a chance
-// to read any memory-map information from the boot loader. Currently, the
-// kernel simply assumes that enough space is available and clobbers some
-// memory after its load image. (In zircon-image.elf, the IMAGE_RESERVE_END
-// symbol indicates the end of the address range that will be clobbered.)
-// If the boot loader happened to place its constructed ZBI or other reserved
-// areas immediately after the kernel image, things would go badly.
-// We should amend the protocol with the boot loader so that it knows how
-// much space to reserve after the kernel image. Either zbi_header_t.extra
-// or zbi_kernel_t.reserved could be repurposed for this.
-//
-// x86-64
-//
-// The kernel assumes it was loaded at a fixed physical address of
-// 0x100000 (1MB). zbi_kernel_t.entry is the absolute physical address
-// of the PC location where the kernel will start.
-// TODO(SEC-31): Perhaps this will change??
-// The processor is in 64-bit mode with direct virtual to physical
-// mapping covering the physical memory where the kernel and
-// bootloader-constructed ZBI were loaded, which must be below 4GB.
-// The %rbx register (or %ebx, since the high 32 bits must be zero)
-// holds the physical address of the bootloader-constructed ZBI.
-// All other registers are unspecified.
-//
-// ARM64
-//
-// zbi_kernel_t.entry is an offset from the beginning of the image
-// (i.e., the ZBI_TYPE_CONTAINER header before the ZBI_TYPE_KERNEL_ARM64
-// header) to the PC location in the image where the kernel will
-// start. The processor is in physical address mode at EL1 or
-// above. The kernel image and the bootloader-constructed ZBI each
-// can be loaded anywhere in physical memory. The x0 register
-// holds the physical address of the bootloader-constructed ZBI.
-// All other registers are unspecified.
-//
-#define ZBI_TYPE_KERNEL_PREFIX (0x004e524b) // KRN\0
-#define ZBI_TYPE_KERNEL_MASK (0x00FFFFFF)
-#define ZBI_TYPE_KERNEL_X64 (0x4c4e524b) // KRNL
-#define ZBI_TYPE_KERNEL_ARM64 (0x384e524b) // KRN8
-#define ZBI_IS_KERNEL_BOOTITEM(x) (((x) & ZBI_TYPE_KERNEL_MASK) == \
- ZBI_TYPE_KERNEL_PREFIX)
-
-#ifndef __ASSEMBLER__
-typedef struct {
- // Entry-point address. The interpretation of this differs by machine.
- uint64_t entry;
- // Reserved for future use.
- uint64_t reserved;
-} zbi_kernel_t;
-
-// The whole contiguous image loaded into memory by the boot loader.
-typedef struct {
- zbi_header_t hdr_file;
- zbi_header_t hdr_kernel;
- zbi_kernel_t data_kernel;
- // Some unspecified amount of available memory follows.
- // TODO(mcgrathr): Make it hdr_kernel.extra bytes?
- uint8_t reserved[];
-} zircon_kernel_t;
-#endif
-
-
-// A discarded item that should just be ignored. This is used for an
-// item that was already processed and should be ignored by whatever
-// stage is now looking at the ZBI. An earlier stage already "consumed"
-// this information, but avoided copying data around to remove it from
-// the ZBI item stream.
-#define ZBI_TYPE_DISCARD (0x50494b53) // SKIP
-
-
-// ZBI_TYPE_STORAGE_* types represent an image that might otherwise
-// appear on some block storage device, i.e. a RAM disk of some sort.
-// All zbi_header_t fields have the same meanings for all these types.
-// The interpretation of the payload (after possible decompression) is
-// indicated by the specific zbi_header_t.type value.
-//
-// If ZBI_FLAG_STORAGE_COMPRESSED is set in zbi_header_t.flags, then the
-// payload is compressed with LZ4 and zbi_header_t.extra gives the exact
-// size of the decompressed payload. If ZBI_FLAG_STORAGE_COMPRESSED is
-// not set, then zbi_header_t.extra matches zbi_header_t.length.
-//
-// TODO(mcgrathr): Document or point to the details of the LZ4 header format.
-#define ZBI_FLAG_STORAGE_COMPRESSED (0x00000001)
-
-// A virtual disk image. This is meant to be treated as if it were a
-// storage device. The payload (after decompression) is the contents of
-// the storage device, in whatever format that might be.
-#define ZBI_TYPE_STORAGE_RAMDISK (0x4b534452) // RDSK
-
-// The /boot filesystem in BOOTFS format, specified below.
-// A complete ZBI must have exactly one ZBI_TYPE_STORAGE_BOOTFS item.
-// Zircon [userboot](../../../../docs/userboot.md) handles the contents
-// of this filesystem.
-#define ZBI_TYPE_STORAGE_BOOTFS (0x42534642) // BFSB
-
-// The payload (after decompression) of an item in BOOTFS format consists
-// of separate "file" images that are each aligned to ZBI_BOOTFS_PAGE_SIZE
-// bytes from the beginning of the item payload. The first "file" consists
-// of a zbi_bootfs_header_t followed by directory entries.
-#define ZBI_BOOTFS_PAGE_SIZE (4096u)
-
-#define ZBI_BOOTFS_PAGE_ALIGN(size) \
- (((size) + ZBI_BOOTFS_PAGE_SIZE - 1) & -ZBI_BOOTFS_PAGE_SIZE)
-
-#ifndef __ASSEMBLER__
-typedef struct {
- // Must be ZBI_BOOTFS_MAGIC.
- uint32_t magic;
-
- // Size in bytes of all the directory entries.
- // Does not include the size of the zbi_bootfs_header_t.
- uint32_t dirsize;
-
- // Reserved for future use. Set to 0.
- uint32_t reserved0;
- uint32_t reserved1;
-} zbi_bootfs_header_t;
-#endif
-
-// LSW of sha256("bootfs")
-#define ZBI_BOOTFS_MAGIC (0xa56d3ff9)
-
-// Each directory entry holds a pathname and gives the offset and size
-// of the contents of the file by that name.
-#ifndef __ASSEMBLER__
-typedef struct {
- // Length of the name[] field at the end. This length includes the
- // NUL terminator, which must be present, but does not include any
- // alignment padding required before the next directory entry.
- uint32_t name_len;
-
- // Length of the file in bytes. This is an exact size that is not
- // rounded, though the file is always padded with zeros up to a
- // multiple of ZBI_BOOTFS_PAGE_SIZE.
- uint32_t data_len;
-
- // Offset from the beginning of the payload (zbi_bootfs_header_t) to
- // the file's data. This must be a multiple of ZBI_BOOTFS_PAGE_SIZE.
- uint32_t data_off;
-
- // Pathname of the file, a UTF-8 string. This must include a NUL
- // terminator at the end. It must not begin with a '/', but it may
- // contain '/' separators for subdirectories.
- char name[];
-} zbi_bootfs_dirent_t;
-#endif
-
-// Each directory entry has a variable size of [16,268] bytes that
-// must be a multiple of 4 bytes.
-#define ZBI_BOOTFS_DIRENT_SIZE(name_len) \
- ((sizeof(zbi_bootfs_dirent_t) + (name_len) + 3) & -(size_t)4)
-
-// zbi_bootfs_dirent_t.name_len must be > 1 and <= ZBI_BOOTFS_MAX_NAME_LEN.
-#define ZBI_BOOTFS_MAX_NAME_LEN (256)
-
-
-// The remaining types are used to communicate information from the boot
-// loader to the kernel. Usually these are synthesized in memory by the
-// boot loader, but they can also be included in a ZBI along with the
-// kernel and BOOTFS. Some boot loaders may set the zbi_header_t flags
-// and crc32 fields to zero, though setting them to ZBI_FLAG_VERSION and
-// ZBI_ITEM_NO_CRC32 is specified. The kernel doesn't check.
-
-
-// A kernel command line fragment, a NUL-terminated UTF-8 string.
-// Multiple ZBI_TYPE_CMDLINE items can appear. They are treated as if
-// concatented with ' ' between each item, in the order they appear:
-// first items in the complete ZBI containing the kernel; then items in
-// the ZBI synthesized by the boot loader. The kernel interprets the
-// [whole command line](../../../../docs/kernel_cmdline.md).
-#define ZBI_TYPE_CMDLINE (0x4c444d43) // CMDL
-
-// The crash log from the previous boot, a UTF-8 string.
-#define ZBI_TYPE_CRASHLOG (0x4d4f4f42) // BOOM
-
-// Physical memory region that will persist across warm boots.
-// zbi_nvram_t gives the physical base address and length in bytes.
-#define ZBI_TYPE_NVRAM (0x4c4c564e) // NVLL
-// This reflects a typo we need to support for a while.
-#define ZBI_TYPE_NVRAM_DEPRECATED (0x4c4c5643) // CVLL
-#ifndef __ASSEMBLER__
-typedef struct {
- uint64_t base;
- uint64_t length;
-} zbi_nvram_t;
-#endif
-
-// Platform ID Information.
-#define ZBI_TYPE_PLATFORM_ID (0x44494C50) // PLID
-#ifndef __ASSEMBLER__
-typedef struct {
- uint32_t vid;
- uint32_t pid;
- char board_name[32];
-} zbi_platform_id_t;
-#endif
-
-// CPU configuration, a zbi_cpu_config_t header followed by one or more
-// zbi_cpu_cluster_t entries. zbi_header_t.length must equal
-// zbi_cpu_config_t.cluster_count * sizeof(zbi_cpu_cluster_t).
-#define ZBI_TYPE_CPU_CONFIG (0x43555043) // CPUC
-#ifndef __ASSEMBLER__
-typedef struct {
- // Number of CPU cores in the cluster.
- uint32_t cpu_count;
-
- // Reserved for future use. Set to 0.
- uint32_t type;
- uint32_t flags;
- uint32_t reserved;
-} zbi_cpu_cluster_t;
-
-typedef struct {
- // Number of zbi_cpu_cluster_t entries following this header.
- uint32_t cluster_count;
-
- // Reserved for future use. Set to 0.
- uint32_t reserved[3];
-
- // cluster_count entries follow.
- zbi_cpu_cluster_t clusters[];
-} zbi_cpu_config_t;
-#endif
-
-// Memory configuration, one or more zbi_mem_range_t entries.
-// zbi_header_t.length is sizeof(zbi_mem_range_t) times the number of entries.
-#define ZBI_TYPE_MEM_CONFIG (0x434D454D) // MEMC
-#ifndef __ASSEMBLER__
-typedef struct {
- uint64_t paddr;
- uint64_t length;
- uint32_t type;
- uint32_t reserved;
-} zbi_mem_range_t;
-#endif
-#define ZBI_MEM_RANGE_RAM (1)
-#define ZBI_MEM_RANGE_PERIPHERAL (2)
-#define ZBI_MEM_RANGE_RESERVED (3)
-
-// Kernel driver configuration. The zbi_header_t.extra field gives a
-// KDRV_* type that determines the payload format.
-// See [driver-config.h](<zircon/boot/driver-config.h>) for details.
-#define ZBI_TYPE_KERNEL_DRIVER (0x5652444B) // KDRV
-
-// ACPI Root Table Pointer, a uint64_t physical address.
-#define ZBI_TYPE_ACPI_RSDP (0x50445352) // RSDP
-
-// SMBIOS entry point, a uint64_t physical address.
-#define ZBI_TYPE_SMBIOS (0x49424d53) // SMBI
-
-// EFI memory map, a uint64_t entry size followed by a sequence of
-// EFI memory descriptors aligned on that entry size.
-#define ZBI_TYPE_EFI_MEMORY_MAP (0x4d494645) // EFIM
-
-// EFI system table, a uint64_t physical address.
-#define ZBI_TYPE_EFI_SYSTEM_TABLE (0x53494645) // EFIS
-
-// E820 memory table, an array of e820entry_t.
-#define ZBI_TYPE_E820_TABLE (0x30323845) // E820
-
-// Debug serial port, a zbi_uart_t entry.
-#define ZBI_TYPE_DEBUG_UART (0x54524155) // UART
-#ifndef __ASSEMBLER__
-typedef struct {
- uint64_t base;
- uint32_t type;
- uint32_t irq;
-} zbi_uart_t;
-#endif
-#define ZBI_UART_NONE (0)
-#define ZBI_UART_PC_PORT (1)
-#define ZBI_UART_PC_MMIO (2)
-
-// Framebuffer parameters, a zbi_swfb_t entry.
-#define ZBI_TYPE_FRAMEBUFFER (0x42465753) // SWFB
-#ifndef __ASSEMBLER__
-typedef struct {
- // Physical memory address.
- uint64_t base;
-
- // Pixel layout and format.
- // See [../pixelformat.h](<zircon/pixelformat.h>).
- uint32_t width;
- uint32_t height;
- uint32_t stride;
- uint32_t format;
-} zbi_swfb_t;
-#endif
-
-
-// ZBI_TYPE_DRV_* types (LSB is 'm') contain driver metadata.
-#define ZBI_TYPE_DRV_METADATA(type) (((type) & 0xFF) == 0x6D) // 'm'
-
-// MAC address for Ethernet, Wifi, Bluetooth, etc. zbi_header_t.extra
-// is a board-specific index to specify which device the MAC address
-// applies to. zbi_header_t.length gives the size in bytes, which
-// varies depending on the type of address appropriate for the device.
-#define ZBI_TYPE_DRV_MAC_ADDRESS (0x43414D6D) // mMAC
-
-// A partition map for a storage device, a zbi_partition_map_t header
-// followed by one or more zbi_partition_t entries. zbi_header_t.extra
-// is a board-specific index to specify which device this applies to.
-#define ZBI_TYPE_DRV_PARTITION_MAP (0x5452506D) // mPRT
-#define ZBI_PARTITION_NAME_LEN (32)
-#define ZBI_PARTITION_GUID_LEN (16)
-#ifndef __ASSEMBLER__
-typedef struct {
- // GUID specifying the format and use of data stored in the partition.
- uint8_t type_guid[ZBI_PARTITION_GUID_LEN];
-
- // GUID unique to this partition.
- uint8_t uniq_guid[ZBI_PARTITION_GUID_LEN];
-
- // First and last block occupied by this partition.
- uint64_t first_block;
- uint64_t last_block;
-
- // Reserved for future use. Set to 0.
- uint64_t flags;
-
- char name[ZBI_PARTITION_NAME_LEN];
-} zbi_partition_t;
-
-typedef struct {
- // Total blocks used on the device.
- uint64_t block_count;
- // Size of each block in bytes.
- uint64_t block_size;
-
- // Number of partitions in the map.
- uint32_t partition_count;
-
- // Reserved for future use.
- uint32_t reserved;
-
- // Device GUID.
- uint8_t guid[ZBI_PARTITION_GUID_LEN];
-
- // parition_count partition entries follow.
- zbi_partition_t partitions[];
-} zbi_partition_map_t;
-#endif
-
-#endif // _ZIRCON_IMAGE_H_
diff --git a/include/zircon/zircon.h b/include/zircon/zircon.h
deleted file mode 100644
index 43f5d39..0000000
--- a/include/zircon/zircon.h
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * Copyright (c) 2018 The Fuchsia Authors
- *
- * SPDX-License-Identifier: BSD-3-Clause
- */
-
-#ifndef _ZIRCON_ZIRCON_H_
-#define _ZIRCON_ZIRCON_H_
-
-#include <zircon/image.h>
-#include <zircon/driver-config.h>
-#include <zircon/gpt.h>
-
-/* called before booting to allow board specific additions to the bootdata */
-int zircon_preboot(zbi_header_t* zbi);
-
-void zircon_append_boot_item(zbi_header_t* container, uint32_t type, uint32_t extra,
- const void* payload, uint32_t length);
-
-#endif
diff --git a/lib/Kconfig b/lib/Kconfig
index bcb0429..59292b9 100644
--- a/lib/Kconfig
+++ b/lib/Kconfig
@@ -265,7 +265,7 @@
is performed in hardware.
config MD5
- bool
+ bool "Support MD5 algorithm"
config CRC32C
bool
@@ -422,6 +422,6 @@
source lib/efi/Kconfig
source lib/efi_loader/Kconfig
source lib/optee/Kconfig
+source lib/chromecast/Kconfig
endmenu
-
diff --git a/lib/Makefile b/lib/Makefile
index 26c15d9..8bb6e27 100644
--- a/lib/Makefile
+++ b/lib/Makefile
@@ -118,4 +118,6 @@
obj-y += libavb/
+obj-$(CONFIG_CHROMECAST) += chromecast/
+
subdir-ccflags-$(CONFIG_CC_OPTIMIZE_LIBS_FOR_SPEED) += -O2
diff --git a/lib/chromecast/Kconfig b/lib/chromecast/Kconfig
new file mode 100644
index 0000000..20d33de
--- /dev/null
+++ b/lib/chromecast/Kconfig
@@ -0,0 +1,26 @@
+menu "Chromecast"
+
+config CHROMECAST
+ bool "Libs or modifications for Chromecast"
+ default n
+
+if CHROMECAST
+
+config CHROMECAST_PARTITION
+ bool "Chromecast partitions"
+ default y
+ select PARTITIONS
+ select EFI_PARTITION
+
+config CHROMECAST_FACTORY
+ bool "Support Chromecast factory partition"
+ default y
+ select PARTITIONS
+
+config CHROMECAST_AB
+ bool "Chromecast A/B partition"
+ default y
+
+endif
+
+endmenu
diff --git a/lib/chromecast/Makefile b/lib/chromecast/Makefile
new file mode 100644
index 0000000..bb0b024
--- /dev/null
+++ b/lib/chromecast/Makefile
@@ -0,0 +1,2 @@
+obj-$(CONFIG_CHROMECAST_PARTITION) += partition.o
+obj-$(CONFIG_CHROMECAST_FACTORY) += factory.o
diff --git a/lib/chromecast/factory.c b/lib/chromecast/factory.c
new file mode 100644
index 0000000..05d4f95
--- /dev/null
+++ b/lib/chromecast/factory.c
@@ -0,0 +1,130 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Google LLC
+ */
+
+#include <blk.h>
+#include <chromecast/factory.h>
+#include <common.h>
+#include <linux/ctype.h>
+#include <part.h>
+#include <stdio.h>
+#include <string.h>
+#include <fs.h>
+
+// same as PROPERTY_VALUE_MAX in Android
+#define CHROMECAST_FACTORY_CONFIG_VALUE_MAX 92
+
+static const struct {
+ const char *sku;
+ const char *region_code;
+ const char *locales;
+} SKU_LIST[] = {
+ // default to use the first one
+ { "US", "US", "en-US,es-US" },
+ { "CA", "CA", "en-CA,fr-CA" },
+ { "GB", "EU", "en-GB,en-IE" },
+ { "DE", "EU", "de-DE" },
+ { "FR", "EU", "fr-FR" },
+ { "NL", "EU", "nl-NL,de-BE,fr-BE,nl-BE,de-AT" },
+ { "NO", "EU", "nb-NO,fi-FI,sv-SE,da-DK,en-FI,en-GB" },
+ { "IT", "EU", "it-IT,es-ES,fr-CH,de-CH,it-CH" },
+ { "AU", "AU", "en-AU,en-NZ" },
+ { "JP", "JP", "ja-JP" },
+ { "KR", "KR", "ko-KR" },
+ { "IN", "US", "en-IN,hi-IN" },
+ { "LA", "MX", "es-MX,es-PE,es-CO,es-GT,es-HN,es-SV,es-NI,es-CR,es-PA,es-EC" },
+ { "TW", "US", "zh-TW" },
+ { "BR", "BR", "pt-BR" },
+};
+
+static loff_t get_factory_config(struct blk_desc *dev_desc, int part,
+ const char *name, char *buf,
+ const char *default_value)
+{
+ int ret;
+ loff_t read_size;
+ char config_path[128];
+
+ snprintf(config_path, sizeof(config_path), "/configs/%s", name);
+
+ // NOTE: fs_read closes the device, so we need to reset the device
+ // for every fs_read.
+ ret = fs_set_blk_dev_with_part(dev_desc, part);
+ if (ret == 0) {
+ ret = fs_read(config_path, (ulong) buf, 0,
+ CHROMECAST_FACTORY_CONFIG_VALUE_MAX - 1,
+ &read_size);
+ }
+ if (ret) {
+ strlcpy(buf, default_value,
+ CHROMECAST_FACTORY_CONFIG_VALUE_MAX);
+ read_size = strlen(buf);
+ }
+
+ // There could be end of lines behind the value, remove them.
+ while (read_size > 0 && isspace(buf[read_size - 1])) {
+ read_size--;
+ }
+ buf[read_size] = '\0';
+
+ return read_size;
+}
+
+int load_chromecast_factory_configs(struct blk_desc *dev_desc)
+{
+ disk_partition_t info;
+ int part;
+ int i;
+ char buf[CHROMECAST_FACTORY_CONFIG_VALUE_MAX];
+ int sku_id;
+
+ part = part_get_info_by_name(dev_desc, "factory", &info);
+ if (part == -1) {
+ printf("%s: factory partition not found\n", __func__);
+ return 1;
+ }
+
+ get_factory_config(dev_desc, part, "serial", buf,
+ "1234567890");
+ env_set("serial#", buf);
+
+ // Set the default value to Google owned local mac address.
+ get_factory_config(dev_desc, part, "mac_wifi", buf,
+ "02:1A:11:00:00:00");
+ env_set("mac_wifi", buf);
+
+ // Set the default value to Google owned local mac address.
+ get_factory_config(dev_desc, part, "mac_bt", buf,
+ "02:1A:11:00:00:11");
+ env_set("mac_bt", buf);
+
+ get_factory_config(dev_desc, part, "sku", buf,
+ SKU_LIST[0].sku);
+ sku_id = -1;
+ for (i = 0; i < sizeof(SKU_LIST) / sizeof(SKU_LIST[0]); i++) {
+ if (strcmp(buf, SKU_LIST[i].sku) == 0) {
+ sku_id = i;
+ break;
+ }
+ }
+ if (sku_id == -1) {
+ printf("unknown sku: %s, use the default: %s", buf,
+ SKU_LIST[0].sku);
+ strlcpy(buf, SKU_LIST[0].sku, sizeof(buf));
+ sku_id = 0;
+ }
+ env_set("sku", buf);
+
+ // Allow overwriting the default region_code and locales by factory
+ // config for testing.
+ get_factory_config(dev_desc, part, "region_code", buf,
+ SKU_LIST[sku_id].region_code);
+ env_set("region_code", buf);
+
+ get_factory_config(dev_desc, part, "locales", buf,
+ SKU_LIST[sku_id].locales);
+ env_set("locales", buf);
+
+ return 0;
+}
diff --git a/lib/chromecast/partition.c b/lib/chromecast/partition.c
new file mode 100644
index 0000000..b179678
--- /dev/null
+++ b/lib/chromecast/partition.c
@@ -0,0 +1,209 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2021 Google LLC
+ */
+
+#include <blk.h>
+#include <chromecast/partition.h>
+#include <linux/sizes.h>
+#include <linux/types.h>
+#include <malloc.h>
+#include <memalign.h>
+#include <part.h>
+#include <part_efi.h>
+#include <stdio.h>
+#include <uuid.h>
+
+static int create_partitions_from_table(
+ struct blk_desc *dev_desc,
+ const chromecast_partition_table_t *partition_table,
+ disk_partition_t **partitions,
+ int *part_count)
+{
+ const uint64_t align = partition_table->align;
+ const uint64_t reserved = partition_table->reserved;
+ const chromecast_partition_t *cc_parts = partition_table->partitions;
+ const uint64_t blksz = dev_desc->blksz;
+ const lbaint_t total_blk = dev_desc->lba;
+ lbaint_t offset_blk;
+ lbaint_t align_blk;
+ lbaint_t reserved_blk;
+ disk_partition_t *parts;
+ int count = 0;
+ int i;
+
+ if (align % blksz) {
+ printf("%s: align (%lld) is not a multiple of blksz (%lld)\n",
+ __func__, align, blksz);
+ return -EINVAL;
+ }
+
+ if (reserved % blksz) {
+ printf("%s: reserved (%lld) is not a multiple of blksz (%lld)\n",
+ __func__, reserved, blksz);
+ return -EINVAL;
+ }
+
+ for (i = 0; i < CHROMECAST_PARTITION_ENTRY_NUMBERS &&
+ cc_parts[i].name; i++) {
+ if (cc_parts[i].start % align) {
+ printf("%s: partition %s not aligned\n",
+ __func__, cc_parts[i].name);
+ return -EINVAL;
+ }
+ count++;
+ }
+
+ offset_blk = 0;
+ align_blk = align ? align / blksz : 1;
+ reserved_blk = reserved / blksz;
+
+ parts = calloc(count, sizeof(disk_partition_t));
+ if (!parts)
+ return -ENOMEM;
+
+ for (i = 0; i < count; i++) {
+ lbaint_t start_blk = cc_parts[i].start / blksz;
+ lbaint_t size_blk = cc_parts[i].size / blksz;
+
+ if (start_blk == 0) {
+ start_blk = offset_blk;
+ } else if (start_blk < offset_blk) {
+ printf("%s: %s partition overlaps with another one\n",
+ __func__, cc_parts[i].name);
+ free(parts);
+ return -EINVAL;
+ }
+
+ if (start_blk + size_blk + reserved_blk > total_blk) {
+ printf("%s: %s partition exceeds disk size\n",
+ __func__, cc_parts[i].name);
+ free(parts);
+ return -EINVAL;
+ }
+
+ // extend the last partition to the end if the size is 0
+ if (size_blk == 0 && i == count - 1) {
+ size_blk = total_blk - reserved_blk - start_blk;
+ // align down the size
+ size_blk -= size_blk % align_blk;
+ }
+
+ offset_blk = start_blk + size_blk;
+ // align up the offset
+ offset_blk += align_blk - 1;
+ offset_blk -= offset_blk % align_blk;
+
+ parts[i].start = start_blk;
+ parts[i].size = size_blk;
+ strncpy((char *)parts[i].name, cc_parts[i].name, PART_NAME_LEN);
+ parts[i].name[PART_NAME_LEN - 1] = '\0';
+ printf("%s: %3d: %16s start: %8ld size: %8ld\n", __func__,
+ i + 1, parts[i].name, parts[i].start, parts[i].size);
+#if CONFIG_IS_ENABLED(PARTITION_UUIDS)
+ gen_rand_uuid_str(parts[i].uuid, UUID_STR_FORMAT_GUID);
+#endif
+ }
+
+ *partitions = parts;
+ *part_count = count;
+
+ return 0;
+}
+
+static int verify_partitions(struct blk_desc *dev_desc,
+ disk_partition_t *partitions,
+ int part_count)
+{
+ ALLOC_CACHE_ALIGN_BUFFER_PAD(gpt_header, gpt_head, 1, dev_desc->blksz);
+ gpt_entry *gpt_pte = NULL;
+ int ret;
+
+ ret = gpt_verify_partitions(dev_desc, partitions, part_count,
+ gpt_head, &gpt_pte);
+
+ free(gpt_pte);
+ return ret;
+}
+
+static int restore_partitions(struct blk_desc *dev_desc,
+ disk_partition_t *partitions,
+ int part_count)
+{
+ char disk_guid[UUID_STR_LEN + 1];
+ int ret;
+
+ gen_rand_uuid_str(disk_guid, UUID_STR_FORMAT_GUID);
+ ret = gpt_restore(dev_desc, disk_guid, partitions, part_count);
+
+ return ret;
+}
+
+static int migrate_partitions(
+ struct blk_desc *dev_desc,
+ const disk_partition_t *partitions,
+ int part_count,
+ const chromecast_partition_table_t *partition_table)
+{
+ int i;
+
+ for (i = 0; i < part_count; i++) {
+ switch (partition_table->partitions[i].migrate_op) {
+ case CHROMECAST_PARTITION_MIGRATE_OP_ERASE:
+ printf("%s: erasing %s\n",
+ __func__, partitions[i].name);
+ if (blk_derase(dev_desc, partitions[i].start,
+ partitions[i].size) != 0)
+ return 1;
+ break;
+ case CHROMECAST_PARTITION_MIGRATE_OP_NONE:
+ default:
+ break;
+ }
+ }
+
+ return 0;
+}
+
+int init_chromecast_partitions(
+ struct blk_desc *dev_desc,
+ const chromecast_partition_table_t *partition_table)
+{
+ disk_partition_t *partitions = NULL;
+ int part_count = 0;
+ int ret;
+
+ ret = create_partitions_from_table(dev_desc, partition_table,
+ &partitions, &part_count);
+ if (ret) {
+ printf("%s: failed to get partitions\n", __func__);
+ goto out;
+ }
+
+ ret = verify_partitions(dev_desc, partitions, part_count);
+ if (ret == 0) {
+ printf("%s: successfully verified partitions\n", __func__);
+ goto out;
+ }
+
+ printf("%s: updating partitions\n", __func__);
+
+ ret = migrate_partitions(dev_desc, partitions, part_count,
+ partition_table);
+ if (ret) {
+ printf("%s: failed to migrate partitions\n", __func__);
+ goto out;
+ }
+
+ ret = restore_partitions(dev_desc, partitions, part_count);
+ if (ret) {
+ printf("%s: failed to update partitions\n", __func__);
+ goto out;
+ }
+
+ part_init(dev_desc);
+ printf("%s: partitions updated\n", __func__);
+out:
+ free(partitions);
+ return ret;
+}
diff --git a/lib/crc32c.c b/lib/crc32c.c
deleted file mode 100644
index 016b34a..0000000
--- a/lib/crc32c.c
+++ /dev/null
@@ -1,38 +0,0 @@
-// SPDX-License-Identifier: GPL-2.0+
-/*
- * Copied from Linux kernel crypto/crc32c.c
- * Copyright (c) 2004 Cisco Systems, Inc.
- * Copyright (c) 2008 Herbert Xu <herbert@gondor.apana.org.au>
- *
- * This program is free software; you can redistribute it and/or modify it
- * under the terms of the GNU General Public License as published by the Free
- * Software Foundation; either version 2 of the License, or (at your option)
- * any later version.
- */
-
-#include <common.h>
-#include <compiler.h>
-
-uint32_t crc32c_cal(uint32_t crc, const char *data, int length,
- uint32_t *crc32c_table)
-{
- while (length--)
- crc = crc32c_table[(u8)(crc ^ *data++)] ^ (crc >> 8);
-
- return crc;
-}
-
-void crc32c_init(uint32_t *crc32c_table, uint32_t pol)
-{
- int i, j;
- uint32_t v;
- const uint32_t poly = pol; /* Bit-reflected CRC32C polynomial */
-
- for (i = 0; i < 256; i++) {
- v = i;
- for (j = 0; j < 8; j++)
- v = (v >> 1) ^ ((v & 1) ? poly : 0);
-
- crc32c_table[i] = v;
- }
-}
diff --git a/lib/dhry/Kconfig b/lib/dhry/Kconfig
index 5474469..641b806 100644
--- a/lib/dhry/Kconfig
+++ b/lib/dhry/Kconfig
@@ -5,4 +5,3 @@
rough idea of CPU performance. This enables a 'dhry' command
which runs this benchmark within U-Boot and reports the performance.
The number of 'Dhrystone MIPS' is also reported.
-
diff --git a/lib/efi/Kconfig b/lib/efi/Kconfig
index e636624..919e314 100644
--- a/lib/efi/Kconfig
+++ b/lib/efi/Kconfig
@@ -52,4 +52,3 @@
bool "Produce a stub for running with 64-bit EFI"
endchoice
-
diff --git a/lib/efi_loader/Kconfig b/lib/efi_loader/Kconfig
index aef7593..b921ea8 100644
--- a/lib/efi_loader/Kconfig
+++ b/lib/efi_loader/Kconfig
@@ -33,4 +33,3 @@
Some hardware does not support DMA to full 64bit addresses. For this
hardware we can create a bounce buffer so that payloads don't have to
worry about platform details.
-
diff --git a/lib/efi_selftest/Kconfig b/lib/efi_selftest/Kconfig
index 72f713e..59f9f36 100644
--- a/lib/efi_selftest/Kconfig
+++ b/lib/efi_selftest/Kconfig
@@ -7,4 +7,3 @@
This adds an EFI test application to U-Boot that can be executed
with the 'bootefi selftest' command. It provides extended tests of
the EFI API implementation.
-
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 4c42aeb..ad838f2 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -73,8 +73,8 @@
COMPAT(ALTERA_SOCFPGA_F2SDR2, "altr,socfpga-fpga2sdram2-bridge"),
COMPAT(ALTERA_SOCFPGA_FPGA0, "altr,socfpga-a10-fpga-mgr"),
COMPAT(ALTERA_SOCFPGA_NOC, "altr,socfpga-a10-noc"),
- COMPAT(ALTERA_SOCFPGA_CLK_INIT, "altr,socfpga-a10-clk-init")
- COMPAT(COMPAT_MESON_NAND, "amlogic,meson-g12a-nfc"),
+ COMPAT(ALTERA_SOCFPGA_CLK_INIT, "altr,socfpga-a10-clk-init"),
+ COMPAT(COMPAT_MESON_NAND, "amlogic,meson-nfc"),
};
const char *fdtdec_get_compatible(enum fdt_compat_id id)
diff --git a/lib/libavb/avb_cmdline.c b/lib/libavb/avb_cmdline.c
index bc43a0f..86b7dc4 100644
--- a/lib/libavb/avb_cmdline.c
+++ b/lib/libavb/avb_cmdline.c
@@ -39,6 +39,14 @@
char part_name[AVB_PART_NAME_MAX_SIZE];
char guid_buf[37];
+ /* Don't attempt to query the partition guid unless its search string is
+ * present in the command line. Note: the original cmdline is used here,
+ * not the replaced one. See b/116010959.
+ */
+ if (avb_strstr(cmdline, replace_str[n]) == NULL) {
+ continue;
+ }
+
if (!avb_str_concat(part_name,
sizeof part_name,
part_name_str[n],
@@ -70,7 +78,15 @@
}
}
- avb_assert(ret != NULL);
+ /* It's possible there is no _PARTUUID for replacement above.
+ * Duplicate cmdline to ret for additional substitutions below.
+ */
+ if (ret == NULL) {
+ ret = avb_strdup(cmdline);
+ if (ret == NULL) {
+ goto fail;
+ }
+ }
/* Replace any additional substitutions. */
if (additional_substitutions != NULL) {
@@ -198,21 +214,27 @@
AvbSlotVerifyResult avb_append_options(
AvbOps* ops,
+ AvbSlotVerifyFlags flags,
AvbSlotVerifyData* slot_data,
AvbVBMetaImageHeader* toplevel_vbmeta,
AvbAlgorithmType algorithm_type,
- AvbHashtreeErrorMode hashtree_error_mode) {
+ AvbHashtreeErrorMode hashtree_error_mode,
+ AvbHashtreeErrorMode resolved_hashtree_error_mode) {
AvbSlotVerifyResult ret;
const char* verity_mode = "invalid";
bool is_device_unlocked;
AvbIOResult io_ret;
- /* Add androidboot.vbmeta.device option. */
- if (!cmdline_append_option(slot_data,
- "androidboot.vbmeta.device",
- "PARTUUID=$(ANDROID_VBMETA_PARTUUID)")) {
- ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
- goto out;
+ /* Add androidboot.vbmeta.device option... except if not using a vbmeta
+ * partition since it doesn't make sense in that case.
+ */
+ if (!(flags & AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION)) {
+ if (!cmdline_append_option(slot_data,
+ "androidboot.vbmeta.device",
+ "PARTUUID=$(ANDROID_VBMETA_PARTUUID)")) {
+ ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
+ goto out;
+ }
}
/* Add androidboot.vbmeta.avb_version option. */
@@ -250,22 +272,25 @@
case AVB_ALGORITHM_TYPE_SHA256_RSA2048:
case AVB_ALGORITHM_TYPE_SHA256_RSA4096:
case AVB_ALGORITHM_TYPE_SHA256_RSA8192: {
- AvbSHA256Ctx ctx;
+ //AvbSHA256Ctx ctx;
size_t n, total_size = 0;
- avb_sha256_init(&ctx);
+ //avb_sha256_init(&ctx);
+ uint8_t vbmeta_digest[AVB_SHA256_DIGEST_SIZE];
+ avb_slot_verify_data_calculate_vbmeta_digest(
+ slot_data, AVB_DIGEST_TYPE_SHA256, vbmeta_digest);
for (n = 0; n < slot_data->num_vbmeta_images; n++) {
- avb_sha256_update(&ctx,
- slot_data->vbmeta_images[n].vbmeta_data,
- slot_data->vbmeta_images[n].vbmeta_size);
total_size += slot_data->vbmeta_images[n].vbmeta_size;
}
+ /*avb_memcpy(vbmeta_digest,
+ avb_sha256_final(&ctx),
+ AVB_SHA256_DIGEST_SIZE);*/
if (!cmdline_append_option(
slot_data, "androidboot.vbmeta.hash_alg", "sha256") ||
!cmdline_append_uint64_base10(
slot_data, "androidboot.vbmeta.size", total_size) ||
!cmdline_append_hex(slot_data,
"androidboot.vbmeta.digest",
- avb_sha256_final(&ctx),
+ vbmeta_digest,
AVB_SHA256_DIGEST_SIZE)) {
ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
goto out;
@@ -275,13 +300,11 @@
case AVB_ALGORITHM_TYPE_SHA512_RSA2048:
case AVB_ALGORITHM_TYPE_SHA512_RSA4096:
case AVB_ALGORITHM_TYPE_SHA512_RSA8192: {
- AvbSHA512Ctx ctx;
size_t n, total_size = 0;
- avb_sha512_init(&ctx);
+ uint8_t vbmeta_digest[AVB_SHA512_DIGEST_SIZE];
+ avb_slot_verify_data_calculate_vbmeta_digest(
+ slot_data, AVB_DIGEST_TYPE_SHA512, vbmeta_digest);
for (n = 0; n < slot_data->num_vbmeta_images; n++) {
- avb_sha512_update(&ctx,
- slot_data->vbmeta_images[n].vbmeta_data,
- slot_data->vbmeta_images[n].vbmeta_size);
total_size += slot_data->vbmeta_images[n].vbmeta_size;
}
if (!cmdline_append_option(
@@ -290,7 +313,7 @@
slot_data, "androidboot.vbmeta.size", total_size) ||
!cmdline_append_hex(slot_data,
"androidboot.vbmeta.digest",
- avb_sha512_final(&ctx),
+ vbmeta_digest,
AVB_SHA512_DIGEST_SIZE)) {
ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
goto out;
@@ -308,7 +331,7 @@
const char* dm_verity_mode = "invalid";
char* new_ret;
- switch (hashtree_error_mode) {
+ switch (resolved_hashtree_error_mode) {
case AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE:
if (!cmdline_append_option(
slot_data, "androidboot.vbmeta.invalidate_on_error", "yes")) {
@@ -335,6 +358,12 @@
verity_mode = "logging";
dm_verity_mode = "ignore_corruption";
break;
+ case AVB_HASHTREE_ERROR_MODE_MANAGED_RESTART_AND_EIO:
+ // Should never get here because MANAGED_RESTART_AND_EIO is
+ // remapped by avb_manage_hashtree_error_mode().
+ avb_assert_not_reached();
+ ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT;
+ goto out;
default:
ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT;
goto out;
@@ -353,6 +382,13 @@
ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
goto out;
}
+ if (hashtree_error_mode == AVB_HASHTREE_ERROR_MODE_MANAGED_RESTART_AND_EIO) {
+ if (!cmdline_append_option(
+ slot_data, "androidboot.veritymode.managed", "yes")) {
+ ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
+ goto out;
+ }
+ }
ret = AVB_SLOT_VERIFY_RESULT_OK;
diff --git a/lib/libavb/avb_cmdline.h b/lib/libavb/avb_cmdline.h
index 3a22815..275b665 100644
--- a/lib/libavb/avb_cmdline.h
+++ b/lib/libavb/avb_cmdline.h
@@ -43,10 +43,12 @@
AvbSlotVerifyResult avb_append_options(
AvbOps* ops,
+ AvbSlotVerifyFlags flags,
AvbSlotVerifyData* slot_data,
AvbVBMetaImageHeader* toplevel_vbmeta,
AvbAlgorithmType algorithm_type,
- AvbHashtreeErrorMode hashtree_error_mode);
+ AvbHashtreeErrorMode hashtree_error_mode,
+ AvbHashtreeErrorMode resolved_hashtree_error_mode);
/* Allocates and initializes a new command line substitution list. Free with
* |avb_free_cmdline_subst_list|.
diff --git a/lib/libavb/avb_descriptor.c b/lib/libavb/avb_descriptor.c
index 183ed46..b3d8b19 100644
--- a/lib/libavb/avb_descriptor.c
+++ b/lib/libavb/avb_descriptor.c
@@ -72,7 +72,11 @@
const AvbDescriptor* dh = (const AvbDescriptor*)p;
avb_assert_aligned(dh);
uint64_t nb_following = avb_be64toh(dh->num_bytes_following);
- uint64_t nb_total = sizeof(AvbDescriptor) + nb_following;
+ uint64_t nb_total = 0;
+ if (!avb_safe_add(&nb_total, sizeof(AvbDescriptor), nb_following)) {
+ avb_error("Invalid descriptor length.\n");
+ goto out;
+ }
if ((nb_total & 7) != 0) {
avb_error("Invalid descriptor length.\n");
@@ -88,7 +92,10 @@
goto out;
}
- p += nb_total;
+ if (!avb_safe_add_to((uint64_t*)(&p), nb_total)) {
+ avb_error("Invalid descriptor length.\n");
+ goto out;
+ }
}
ret = true;
diff --git a/lib/libavb/avb_ops.h b/lib/libavb/avb_ops.h
index 8bbdc7c..6a5c589 100644
--- a/lib/libavb/avb_ops.h
+++ b/lib/libavb/avb_ops.h
@@ -18,6 +18,7 @@
/* Well-known names of named persistent values. */
#define AVB_NPV_PERSISTENT_DIGEST_PREFIX "avb.persistent_digest."
+#define AVB_NPV_MANAGED_VERITY_MODE "avb.managed_verity_mode"
/* Return codes used for I/O operations.
*
@@ -171,6 +172,10 @@
*
* If AVB_IO_RESULT_OK is returned then |out_is_trusted| is set -
* true if trusted or false if untrusted.
+ *
+ * NOTE: If AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION is passed to
+ * avb_slot_verify() then this operation is never used. Instead, the
+ * validate_public_key_for_partition() operation is used
*/
AvbIOResult (*validate_vbmeta_public_key)(AvbOps* ops,
const uint8_t* public_key_data,
@@ -231,6 +236,9 @@
* (NUL-terminated UTF-8 string). Returns the value in
* |out_size_num_bytes|.
*
+ * If the partition doesn't exist the AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION
+ * error code should be returned.
+ *
* Returns AVB_IO_RESULT_OK on success, otherwise an error code.
*/
AvbIOResult (*get_size_of_partition)(AvbOps* ops,
@@ -253,9 +261,10 @@
* AVB_IO_RESULT_ERROR_NO_SUCH_VALUE. If |buffer_size| is smaller than the
* size of the stored value, returns AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE.
*
- * This operation is currently only used to support persistent digests. If a
- * device does not use persistent digests this function pointer can be set to
- * NULL.
+ * This operation is currently only used to support persistent digests or the
+ * AVB_HASHTREE_ERROR_MODE_MANAGED_RESTART_AND_EIO hashtree error mode. If a
+ * device does not use one of these features this function pointer can be set
+ * to NULL.
*/
AvbIOResult (*read_persistent_value)(AvbOps* ops,
const char* name,
@@ -275,14 +284,34 @@
* AVB_IO_RESULT_ERROR_NO_SUCH_VALUE. If the |value_size| is not supported,
* returns AVB_IO_RESULT_ERROR_INVALID_VALUE_SIZE.
*
- * This operation is currently only used to support persistent digests. If a
- * device does not use persistent digests this function pointer can be set to
- * NULL.
+ * This operation is currently only used to support persistent digests or the
+ * AVB_HASHTREE_ERROR_MODE_MANAGED_RESTART_AND_EIO hashtree error mode. If a
+ * device does not use one of these features this function pointer can be set
+ * to NULL.
*/
AvbIOResult (*write_persistent_value)(AvbOps* ops,
const char* name,
size_t value_size,
const uint8_t* value);
+
+ /* Like validate_vbmeta_public_key() but for when the flag
+ * AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION is being used. The name of the
+ * partition to get the public key for is passed in |partition_name|.
+ *
+ * Also returns the rollback index location to use for the partition, in
+ * |out_rollback_index_location|.
+ *
+ * Returns AVB_IO_RESULT_OK on success, otherwise an error code.
+ */
+ AvbIOResult (*validate_public_key_for_partition)(
+ AvbOps* ops,
+ const char* partition,
+ const uint8_t* public_key_data,
+ size_t public_key_length,
+ const uint8_t* public_key_metadata,
+ size_t public_key_metadata_length,
+ bool* out_is_trusted,
+ uint32_t* out_rollback_index_location);
};
#ifdef __cplusplus
diff --git a/lib/libavb/avb_sha.h b/lib/libavb/avb_sha.h
index 335eb8f..c9350e7 100644
--- a/lib/libavb/avb_sha.h
+++ b/lib/libavb/avb_sha.h
@@ -31,8 +31,8 @@
/* Data structure used for SHA-256. */
typedef struct {
uint32_t h[8];
- uint32_t tot_len;
- uint32_t len;
+ uint64_t tot_len;
+ size_t len;
uint8_t block[2 * AVB_SHA256_BLOCK_SIZE];
uint8_t buf[AVB_SHA256_DIGEST_SIZE]; /* Used for storing the final digest. */
} AvbSHA256Ctx;
@@ -40,8 +40,8 @@
/* Data structure used for SHA-512. */
typedef struct {
uint64_t h[8];
- uint32_t tot_len;
- uint32_t len;
+ uint64_t tot_len;
+ size_t len;
uint8_t block[2 * AVB_SHA512_BLOCK_SIZE];
uint8_t buf[AVB_SHA512_DIGEST_SIZE]; /* Used for storing the final digest. */
} AvbSHA512Ctx;
@@ -50,7 +50,7 @@
void avb_sha256_init(AvbSHA256Ctx* ctx);
/* Updates the SHA-256 context with |len| bytes from |data|. */
-void avb_sha256_update(AvbSHA256Ctx* ctx, const uint8_t* data, uint32_t len);
+void avb_sha256_update(AvbSHA256Ctx* ctx, const uint8_t* data, size_t len);
/* Returns the SHA-256 digest. */
uint8_t* avb_sha256_final(AvbSHA256Ctx* ctx) AVB_ATTR_WARN_UNUSED_RESULT;
@@ -59,7 +59,7 @@
void avb_sha512_init(AvbSHA512Ctx* ctx);
/* Updates the SHA-512 context with |len| bytes from |data|. */
-void avb_sha512_update(AvbSHA512Ctx* ctx, const uint8_t* data, uint32_t len);
+void avb_sha512_update(AvbSHA512Ctx* ctx, const uint8_t* data, size_t len);
/* Returns the SHA-512 digest. */
uint8_t* avb_sha512_final(AvbSHA512Ctx* ctx) AVB_ATTR_WARN_UNUSED_RESULT;
diff --git a/lib/libavb/avb_sha256.c b/lib/libavb/avb_sha256.c
index d24c701..86ecca5 100644
--- a/lib/libavb/avb_sha256.c
+++ b/lib/libavb/avb_sha256.c
@@ -29,6 +29,18 @@
*((str) + 0) = (uint8_t)((x) >> 24); \
}
+#define UNPACK64(x, str) \
+ { \
+ *((str) + 7) = (uint8_t)x; \
+ *((str) + 6) = (uint8_t)((uint64_t)x >> 8); \
+ *((str) + 5) = (uint8_t)((uint64_t)x >> 16); \
+ *((str) + 4) = (uint8_t)((uint64_t)x >> 24); \
+ *((str) + 3) = (uint8_t)((uint64_t)x >> 32); \
+ *((str) + 2) = (uint8_t)((uint64_t)x >> 40); \
+ *((str) + 1) = (uint8_t)((uint64_t)x >> 48); \
+ *((str) + 0) = (uint8_t)((uint64_t)x >> 56); \
+ }
+
#define PACK32(str, x) \
{ \
*(x) = ((uint32_t) * ((str) + 3)) | ((uint32_t) * ((str) + 2) << 8) | \
@@ -96,18 +108,18 @@
static void SHA256_transform(AvbSHA256Ctx* ctx,
const uint8_t* message,
- unsigned int block_nb) {
+ size_t block_nb) {
uint32_t w[64];
uint32_t wv[8];
uint32_t t1, t2;
const unsigned char* sub_block;
- int i;
+ size_t i;
#ifndef UNROLL_LOOPS
- int j;
+ size_t j;
#endif
- for (i = 0; i < (int)block_nb; i++) {
+ for (i = 0; i < block_nb; i++) {
sub_block = message + (i << 6);
#ifndef UNROLL_LOOPS
@@ -293,9 +305,9 @@
}
}
-void avb_sha256_update(AvbSHA256Ctx* ctx, const uint8_t* data, uint32_t len) {
- unsigned int block_nb;
- unsigned int new_len, rem_len, tmp_len;
+void avb_sha256_update(AvbSHA256Ctx* ctx, const uint8_t* data, size_t len) {
+ size_t block_nb;
+ size_t new_len, rem_len, tmp_len;
const uint8_t* shifted_data;
tmp_len = AVB_SHA256_BLOCK_SIZE - ctx->len;
@@ -325,11 +337,11 @@
}
uint8_t* avb_sha256_final(AvbSHA256Ctx* ctx) {
- unsigned int block_nb;
- unsigned int pm_len;
- unsigned int len_b;
+ size_t block_nb;
+ size_t pm_len;
+ uint64_t len_b;
#ifndef UNROLL_LOOPS
- int i;
+ size_t i;
#endif
block_nb =
@@ -340,7 +352,7 @@
avb_memset(ctx->block + ctx->len, 0, pm_len - ctx->len);
ctx->block[ctx->len] = 0x80;
- UNPACK32(len_b, ctx->block + pm_len - 4);
+ UNPACK64(len_b, ctx->block + pm_len - 8);
SHA256_transform(ctx, ctx->block, block_nb);
diff --git a/lib/libavb/avb_sha512.c b/lib/libavb/avb_sha512.c
index a5e7297..b19054f 100644
--- a/lib/libavb/avb_sha512.c
+++ b/lib/libavb/avb_sha512.c
@@ -127,14 +127,14 @@
static void SHA512_transform(AvbSHA512Ctx* ctx,
const uint8_t* message,
- unsigned int block_nb) {
+ size_t block_nb) {
uint64_t w[80];
uint64_t wv[8];
uint64_t t1, t2;
const uint8_t* sub_block;
- int i, j;
+ size_t i, j;
- for (i = 0; i < (int)block_nb; i++) {
+ for (i = 0; i < block_nb; i++) {
sub_block = message + (i << 7);
#ifdef UNROLL_LOOPS_SHA512
@@ -291,9 +291,9 @@
}
}
-void avb_sha512_update(AvbSHA512Ctx* ctx, const uint8_t* data, uint32_t len) {
- unsigned int block_nb;
- unsigned int new_len, rem_len, tmp_len;
+void avb_sha512_update(AvbSHA512Ctx* ctx, const uint8_t* data, size_t len) {
+ size_t block_nb;
+ size_t new_len, rem_len, tmp_len;
const uint8_t* shifted_data;
tmp_len = AVB_SHA512_BLOCK_SIZE - ctx->len;
@@ -323,12 +323,12 @@
}
uint8_t* avb_sha512_final(AvbSHA512Ctx* ctx) {
- unsigned int block_nb;
- unsigned int pm_len;
- unsigned int len_b;
+ size_t block_nb;
+ size_t pm_len;
+ uint64_t len_b;
#ifndef UNROLL_LOOPS_SHA512
- int i;
+ size_t i;
#endif
block_nb =
@@ -339,7 +339,7 @@
avb_memset(ctx->block + ctx->len, 0, pm_len - ctx->len);
ctx->block[ctx->len] = 0x80;
- UNPACK32(len_b, ctx->block + pm_len - 4);
+ UNPACK64(len_b, ctx->block + pm_len - 8);
SHA512_transform(ctx, ctx->block, block_nb);
diff --git a/lib/libavb/avb_slot_verify.c b/lib/libavb/avb_slot_verify.c
index 98ec619..5b14b69 100644
--- a/lib/libavb/avb_slot_verify.c
+++ b/lib/libavb/avb_slot_verify.c
@@ -15,6 +15,7 @@
#include <libavb/avb_util.h>
#include <libavb/avb_vbmeta_image.h>
#include <libavb/avb_version.h>
+#include <u-boot/sha256.h>
/* Maximum number of partitions that can be loaded with avb_slot_verify(). */
#define MAX_NUMBER_OF_LOADED_PARTITIONS 32
@@ -25,6 +26,16 @@
/* Maximum size of a vbmeta image - 64 KiB. */
#define VBMETA_MAX_SIZE (64 * 1024)
+uint8_t boot_key_hash[AVB_SHA256_DIGEST_SIZE];
+
+static AvbSlotVerifyResult initialize_persistent_digest(
+ AvbOps* ops,
+ const char* part_name,
+ const char* persistent_value_name,
+ size_t digest_size,
+ const uint8_t* initial_digest,
+ uint8_t* out_digest);
+
/* Helper function to see if we should continue with verification in
* allow_verification_error=true mode if something goes wrong. See the
* comments for the avb_slot_verify() function for more information.
@@ -115,9 +126,26 @@
return AVB_SLOT_VERIFY_RESULT_OK;
}
+/* Reads a persistent digest stored as a named persistent value corresponding to
+ * the given |part_name|. The value is returned in |out_digest| which must point
+ * to |expected_digest_size| bytes. If there is no digest stored for |part_name|
+ * it can be initialized by providing a non-NULL |initial_digest| of length
+ * |expected_digest_size|. This automatic initialization will only occur if the
+ * device is currently locked. The |initial_digest| may be NULL.
+ *
+ * Returns AVB_SLOT_VERIFY_RESULT_OK on success, otherwise returns an
+ * AVB_SLOT_VERIFY_RESULT_ERROR_* error code.
+ *
+ * If the value does not exist, is not supported, or is not populated, and
+ * |initial_digest| is NULL, returns
+ * AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA. If |expected_digest_size| does
+ * not match the stored digest size, also returns
+ * AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA.
+ */
static AvbSlotVerifyResult read_persistent_digest(AvbOps* ops,
const char* part_name,
size_t expected_digest_size,
+ const uint8_t* initial_digest,
uint8_t* out_digest) {
char* persistent_value_name = NULL;
AvbIOResult io_ret = AVB_IO_RESULT_OK;
@@ -132,30 +160,106 @@
if (persistent_value_name == NULL) {
return AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
}
+
io_ret = ops->read_persistent_value(ops,
persistent_value_name,
expected_digest_size,
out_digest,
&stored_digest_size);
+
+ // If no such named persistent value exists and an initial digest value was
+ // given, initialize the named persistent value with the given digest. If
+ // initialized successfully, this will recurse into this function but with a
+ // NULL initial_digest.
+ if (io_ret == AVB_IO_RESULT_ERROR_NO_SUCH_VALUE && initial_digest) {
+ AvbSlotVerifyResult ret =
+ initialize_persistent_digest(ops,
+ part_name,
+ persistent_value_name,
+ expected_digest_size,
+ initial_digest,
+ out_digest);
+ avb_free(persistent_value_name);
+ return ret;
+ }
avb_free(persistent_value_name);
+
if (io_ret == AVB_IO_RESULT_ERROR_OOM) {
return AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
} else if (io_ret == AVB_IO_RESULT_ERROR_NO_SUCH_VALUE) {
+ // Treat a missing persistent value as a verification error, which is
+ // ignoreable, rather than a metadata error which is not.
avb_errorv(part_name, ": Persistent digest does not exist.\n", NULL);
- return AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA;
+ return AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION;
} else if (io_ret == AVB_IO_RESULT_ERROR_INVALID_VALUE_SIZE ||
- io_ret == AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE ||
- expected_digest_size != stored_digest_size) {
+ io_ret == AVB_IO_RESULT_ERROR_INSUFFICIENT_SPACE) {
avb_errorv(
part_name, ": Persistent digest is not of expected size.\n", NULL);
return AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA;
} else if (io_ret != AVB_IO_RESULT_OK) {
avb_errorv(part_name, ": Error reading persistent digest.\n", NULL);
return AVB_SLOT_VERIFY_RESULT_ERROR_IO;
+ } else if (expected_digest_size != stored_digest_size) {
+ avb_errorv(
+ part_name, ": Persistent digest is not of expected size.\n", NULL);
+ return AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA;
}
return AVB_SLOT_VERIFY_RESULT_OK;
}
+static AvbSlotVerifyResult initialize_persistent_digest(
+ AvbOps* ops,
+ const char* part_name,
+ const char* persistent_value_name,
+ size_t digest_size,
+ const uint8_t* initial_digest,
+ uint8_t* out_digest) {
+ AvbSlotVerifyResult ret;
+ AvbIOResult io_ret = AVB_IO_RESULT_OK;
+ bool is_device_unlocked = true;
+
+ io_ret = ops->read_is_device_unlocked(ops, &is_device_unlocked);
+ if (io_ret == AVB_IO_RESULT_ERROR_OOM) {
+ return AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
+ } else if (io_ret != AVB_IO_RESULT_OK) {
+ avb_error("Error getting device lock state.\n");
+ return AVB_SLOT_VERIFY_RESULT_ERROR_IO;
+ }
+
+ if (is_device_unlocked) {
+ avb_debugv(part_name,
+ ": Digest does not exist, device unlocked so not initializing "
+ "digest.\n",
+ NULL);
+ return AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION;
+ }
+
+ // Device locked; initialize digest with given initial value.
+ avb_debugv(part_name,
+ ": Digest does not exist, initializing persistent digest.\n",
+ NULL);
+ io_ret = ops->write_persistent_value(
+ ops, persistent_value_name, digest_size, initial_digest);
+ if (io_ret == AVB_IO_RESULT_ERROR_OOM) {
+ return AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
+ } else if (io_ret != AVB_IO_RESULT_OK) {
+ avb_errorv(part_name, ": Error initializing persistent digest.\n", NULL);
+ return AVB_SLOT_VERIFY_RESULT_ERROR_IO;
+ }
+
+ // To ensure that the digest value was written successfully - and avoid a
+ // scenario where the digest is simply 'initialized' on every verify - recurse
+ // into read_persistent_digest to read back the written value. The NULL
+ // initial_digest ensures that this will not recurse again.
+ ret = read_persistent_digest(ops, part_name, digest_size, NULL, out_digest);
+ if (ret != AVB_SLOT_VERIFY_RESULT_OK) {
+ avb_errorv(part_name,
+ ": Reading back initialized persistent digest failed!\n",
+ NULL);
+ }
+ return ret;
+}
+
static AvbSlotVerifyResult load_and_verify_hash_partition(
AvbOps* ops,
const char* const* requested_partitions,
@@ -249,24 +353,16 @@
*/
image_size = hash_desc.image_size;
if (allow_verification_error) {
- if (ops->get_size_of_partition == NULL) {
- avb_errorv(part_name,
- ": The get_size_of_partition() operation is "
- "not implemented so we may not load the entire partition. "
- "Please implement.",
- NULL);
- } else {
- io_ret = ops->get_size_of_partition(ops, part_name, &image_size);
- if (io_ret == AVB_IO_RESULT_ERROR_OOM) {
- ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
- goto out;
- } else if (io_ret != AVB_IO_RESULT_OK) {
- avb_errorv(part_name, ": Error determining partition size.\n", NULL);
- ret = AVB_SLOT_VERIFY_RESULT_ERROR_IO;
- goto out;
- }
- avb_debugv(part_name, ": Loading entire partition.\n", NULL);
+ io_ret = ops->get_size_of_partition(ops, part_name, &image_size);
+ if (io_ret == AVB_IO_RESULT_ERROR_OOM) {
+ ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
+ goto out;
+ } else if (io_ret != AVB_IO_RESULT_OK) {
+ avb_errorv(part_name, ": Error determining partition size.\n", NULL);
+ ret = AVB_SLOT_VERIFY_RESULT_ERROR_IO;
+ goto out;
}
+ avb_debugv(part_name, ": Loading entire partition.\n", NULL);
}
ret = load_full_partition(
@@ -274,19 +370,27 @@
if (ret != AVB_SLOT_VERIFY_RESULT_OK) {
goto out;
}
-
+ // Although only one of the type might be used, we have to defined the
+ // structure here so that they would live outside the 'if/else' scope to be
+ // used later.
+ AvbSHA256Ctx sha256_ctx;
+ AvbSHA512Ctx sha512_ctx;
+ size_t image_size_to_hash = hash_desc.image_size;
+ // If we allow verification error and the whole partition is smaller than
+ // image size in hash descriptor, we just hash the whole partition.
+ if (image_size_to_hash > image_size) {
+ image_size_to_hash = image_size;
+ }
if (avb_strcmp((const char*)hash_desc.hash_algorithm, "sha256") == 0) {
- AvbSHA256Ctx sha256_ctx;
avb_sha256_init(&sha256_ctx);
avb_sha256_update(&sha256_ctx, desc_salt, hash_desc.salt_len);
- avb_sha256_update(&sha256_ctx, image_buf, hash_desc.image_size);
+ avb_sha256_update(&sha256_ctx, image_buf, image_size_to_hash);
digest = avb_sha256_final(&sha256_ctx);
digest_len = AVB_SHA256_DIGEST_SIZE;
} else if (avb_strcmp((const char*)hash_desc.hash_algorithm, "sha512") == 0) {
- AvbSHA512Ctx sha512_ctx;
avb_sha512_init(&sha512_ctx);
avb_sha512_update(&sha512_ctx, desc_salt, hash_desc.salt_len);
- avb_sha512_update(&sha512_ctx, image_buf, hash_desc.image_size);
+ avb_sha512_update(&sha512_ctx, image_buf, image_size_to_hash);
digest = avb_sha512_final(&sha512_ctx);
digest_len = AVB_SHA512_DIGEST_SIZE;
} else {
@@ -296,18 +400,21 @@
}
if (hash_desc.digest_len == 0) {
- // Expect a match to a persistent digest.
+ /* Expect a match to a persistent digest. */
avb_debugv(part_name, ": No digest, using persistent digest.\n", NULL);
expected_digest_len = digest_len;
expected_digest = expected_digest_buf;
avb_assert(expected_digest_len <= sizeof(expected_digest_buf));
- ret =
- read_persistent_digest(ops, part_name, digest_len, expected_digest_buf);
+ /* Pass |digest| as the |initial_digest| so devices not yet initialized get
+ * initialized to the current partition digest.
+ */
+ ret = read_persistent_digest(
+ ops, part_name, digest_len, digest, expected_digest_buf);
if (ret != AVB_SLOT_VERIFY_RESULT_OK) {
goto out;
}
} else {
- // Expect a match to the digest in the descriptor.
+ /* Expect a match to the digest in the descriptor. */
expected_digest_len = hash_desc.digest_len;
expected_digest = desc_digest;
}
@@ -366,12 +473,6 @@
bool image_preloaded = false;
size_t n;
- if (ops->get_size_of_partition == NULL) {
- avb_error("get_size_of_partition() not implemented.\n");
- ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT;
- goto out;
- }
-
for (n = 0; requested_partitions[n] != NULL; n++) {
char part_name[AVB_PART_NAME_MAX_SIZE];
AvbIOResult io_ret;
@@ -442,6 +543,7 @@
AvbOps* ops,
const char* const* requested_partitions,
const char* ab_suffix,
+ AvbSlotVerifyFlags flags,
bool allow_verification_error,
AvbVBMetaImageFlags toplevel_vbmeta_flags,
int rollback_index_location,
@@ -468,7 +570,7 @@
size_t num_descriptors;
size_t n;
bool is_main_vbmeta;
- bool is_vbmeta_partition;
+ bool look_for_vbmeta_footer;
AvbVBMetaData* vbmeta_image_data = NULL;
ret = AVB_SLOT_VERIFY_RESULT_OK;
@@ -479,8 +581,20 @@
* rollback_index_location to determine whether we're the main
* vbmeta struct.
*/
- is_main_vbmeta = (rollback_index_location == 0);
- is_vbmeta_partition = (avb_strcmp(partition_name, "vbmeta") == 0);
+ is_main_vbmeta = false;
+ if (rollback_index_location == 0) {
+ if ((flags & AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION) == 0) {
+ is_main_vbmeta = true;
+ }
+ }
+
+ /* Don't use footers for vbmeta partitions ('vbmeta' or
+ * 'vbmeta_<partition_name>').
+ */
+ look_for_vbmeta_footer = true;
+ if (avb_strncmp(partition_name, "vbmeta", avb_strlen("vbmeta")) == 0) {
+ look_for_vbmeta_footer = false;
+ }
if (!avb_validate_utf8((const uint8_t*)partition_name, partition_name_len)) {
avb_error("Partition name is not valid UTF-8.\n");
@@ -488,7 +602,7 @@
goto out;
}
- /* Construct full partition name. */
+ /* Construct full partition name e.g. system_a. */
if (!avb_str_concat(full_partition_name,
sizeof full_partition_name,
partition_name,
@@ -500,29 +614,32 @@
goto out;
}
- avb_debugv("Loading vbmeta struct from partition '",
- full_partition_name,
- "'.\n",
- NULL);
-
- /* If we're loading from the main vbmeta partition, the vbmeta
- * struct is in the beginning. Otherwise we have to locate it via a
- * footer.
+ /* If we're loading from the main vbmeta partition, the vbmeta struct is in
+ * the beginning. Otherwise we may have to locate it via a footer... if no
+ * footer is found, we look in the beginning to support e.g. vbmeta_<org>
+ * partitions holding data for e.g. super partitions (b/80195851 for
+ * rationale).
*/
- if (is_vbmeta_partition) {
- vbmeta_offset = 0;
- vbmeta_size = VBMETA_MAX_SIZE;
- } else {
+ vbmeta_offset = 0;
+ vbmeta_size = VBMETA_MAX_SIZE;
+ if (look_for_vbmeta_footer) {
uint8_t footer_buf[AVB_FOOTER_SIZE];
+ uint8_t buffer[512];
size_t footer_num_read;
AvbFooter footer;
+ uint64_t image_size;
+ int i, j;
+ io_ret = ops->get_size_of_partition(ops, full_partition_name, &image_size);
io_ret = ops->read_from_partition(ops,
full_partition_name,
- -AVB_FOOTER_SIZE,
- AVB_FOOTER_SIZE,
- footer_buf,
+ image_size-512,
+ 512,
+ buffer,
&footer_num_read);
+ for (i=512-AVB_FOOTER_SIZE, j=0; i<512 ; i++, j++)
+ footer_buf[j] = buffer[i];
+
if (io_ret == AVB_IO_RESULT_ERROR_OOM) {
ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
goto out;
@@ -531,25 +648,20 @@
ret = AVB_SLOT_VERIFY_RESULT_ERROR_IO;
goto out;
}
- avb_assert(footer_num_read == AVB_FOOTER_SIZE);
if (!avb_footer_validate_and_byteswap((const AvbFooter*)footer_buf,
&footer)) {
- avb_errorv(full_partition_name, ": Error validating footer.\n", NULL);
- ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA;
- goto out;
+ avb_debugv(full_partition_name, ": No footer detected.\n", NULL);
+ } else {
+ /* Basic footer sanity check since the data is untrusted. */
+ if (footer.vbmeta_size > VBMETA_MAX_SIZE) {
+ avb_errorv(
+ full_partition_name, ": Invalid vbmeta size in footer.\n", NULL);
+ } else {
+ vbmeta_offset = footer.vbmeta_offset;
+ vbmeta_size = footer.vbmeta_size;
+ }
}
-
- /* Basic footer sanity check since the data is untrusted. */
- if (footer.vbmeta_size > VBMETA_MAX_SIZE) {
- avb_errorv(
- full_partition_name, ": Invalid vbmeta size in footer.\n", NULL);
- ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA;
- goto out;
- }
-
- vbmeta_offset = footer.vbmeta_offset;
- vbmeta_size = footer.vbmeta_size;
}
vbmeta_buf = avb_malloc(vbmeta_size);
@@ -558,6 +670,18 @@
goto out;
}
+ if (vbmeta_offset != 0) {
+ avb_debugv("Loading vbmeta struct in footer from partition '",
+ full_partition_name,
+ "'.\n",
+ NULL);
+ } else {
+ avb_debugv("Loading vbmeta struct from partition '",
+ full_partition_name,
+ "'.\n",
+ NULL);
+ }
+
io_ret = ops->read_from_partition(ops,
full_partition_name,
vbmeta_offset,
@@ -572,13 +696,14 @@
* go try to get it from the boot partition instead.
*/
if (is_main_vbmeta && io_ret == AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION &&
- is_vbmeta_partition) {
+ !look_for_vbmeta_footer) {
avb_debugv(full_partition_name,
": No such partition. Trying 'boot' instead.\n",
NULL);
ret = load_and_verify_vbmeta(ops,
requested_partitions,
ab_suffix,
+ flags,
allow_verification_error,
0 /* toplevel_vbmeta_flags */,
0 /* rollback_index_location */,
@@ -606,6 +731,16 @@
switch (vbmeta_ret) {
case AVB_VBMETA_VERIFY_RESULT_OK:
avb_assert(pk_data != NULL && pk_len > 0);
+ bool is_device_unlocked;
+ io_ret = ops->read_is_device_unlocked(ops, &is_device_unlocked);
+ if (io_ret == AVB_IO_RESULT_OK && !is_device_unlocked) {
+ AvbSHA256Ctx boot_key_sha256_ctx;
+ avb_sha256_init(&boot_key_sha256_ctx);
+ avb_sha256_update(&boot_key_sha256_ctx, pk_data, pk_len);
+ avb_memcpy(boot_key_hash,
+ avb_sha256_final(&boot_key_sha256_ctx),
+ AVB_SHA256_DIGEST_SIZE);
+ }
break;
case AVB_VBMETA_VERIFY_RESULT_OK_NOT_SIGNED:
@@ -656,6 +791,8 @@
}
}
+ uint32_t rollback_index_location_to_use = rollback_index_location;
+
/* Check if key used to make signature matches what is expected. */
if (pk_data != NULL) {
if (expected_public_key != NULL) {
@@ -683,9 +820,27 @@
pk_metadata_len = vbmeta_header.public_key_metadata_size;
}
- avb_assert(is_main_vbmeta);
- io_ret = ops->validate_vbmeta_public_key(
- ops, pk_data, pk_len, pk_metadata, pk_metadata_len, &key_is_trusted);
+ // If we're not using a vbmeta partition, need to use another AvbOps...
+ if (flags & AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION) {
+ io_ret = ops->validate_public_key_for_partition(
+ ops,
+ full_partition_name,
+ pk_data,
+ pk_len,
+ pk_metadata,
+ pk_metadata_len,
+ &key_is_trusted,
+ &rollback_index_location_to_use);
+ } else {
+ avb_assert(is_main_vbmeta);
+ io_ret = ops->validate_vbmeta_public_key(ops,
+ pk_data,
+ pk_len,
+ pk_metadata,
+ pk_metadata_len,
+ &key_is_trusted);
+ }
+
if (io_ret == AVB_IO_RESULT_ERROR_OOM) {
ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
goto out;
@@ -710,7 +865,7 @@
/* Check rollback index. */
io_ret = ops->read_rollback_index(
- ops, rollback_index_location, &stored_rollback_index);
+ ops, rollback_index_location_to_use, &stored_rollback_index);
if (io_ret == AVB_IO_RESULT_ERROR_OOM) {
ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
goto out;
@@ -736,7 +891,9 @@
if (is_main_vbmeta) {
avb_assert(slot_data->num_vbmeta_images == 0);
} else {
- avb_assert(slot_data->num_vbmeta_images > 0);
+ if (!(flags & AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION)) {
+ avb_assert(slot_data->num_vbmeta_images > 0);
+ }
}
if (slot_data->num_vbmeta_images == MAX_NUMBER_OF_VBMETA_IMAGES) {
avb_errorv(full_partition_name, ": Too many vbmeta images.\n", NULL);
@@ -860,6 +1017,7 @@
load_and_verify_vbmeta(ops,
requested_partitions,
ab_suffix,
+ flags,
allow_verification_error,
toplevel_vbmeta_flags,
chain_desc.rollback_index_location,
@@ -1020,7 +1178,11 @@
goto out;
}
- ret = read_persistent_digest(ops, part_name, digest_len, digest_buf);
+ ret = read_persistent_digest(ops,
+ part_name,
+ digest_len,
+ NULL /* initial_digest */,
+ digest_buf);
if (ret != AVB_SLOT_VERIFY_RESULT_OK) {
goto out;
}
@@ -1044,7 +1206,8 @@
}
}
- if (rollback_index_location >= AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS) {
+ if (rollback_index_location < 0 ||
+ rollback_index_location >= AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS) {
avb_errorv(
full_partition_name, ": Invalid rollback_index_location.\n", NULL);
ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_METADATA;
@@ -1073,13 +1236,137 @@
return ret;
}
+static AvbIOResult avb_manage_hashtree_error_mode(
+ AvbOps* ops,
+ AvbSlotVerifyFlags flags,
+ AvbSlotVerifyData* data,
+ AvbHashtreeErrorMode* out_hashtree_error_mode) {
+ AvbHashtreeErrorMode ret = AVB_HASHTREE_ERROR_MODE_RESTART;
+ AvbIOResult io_ret = AVB_IO_RESULT_OK;
+ uint8_t vbmeta_digest_sha256[AVB_SHA256_DIGEST_SIZE];
+ uint8_t stored_vbmeta_digest_sha256[AVB_SHA256_DIGEST_SIZE];
+ size_t num_bytes_read;
+
+ avb_assert(out_hashtree_error_mode != NULL);
+ avb_assert(ops->read_persistent_value != NULL);
+ avb_assert(ops->write_persistent_value != NULL);
+
+ // If we're rebooting because of dm-verity corruption, make a note of
+ // the vbmeta hash so we can stay in 'eio' mode until things change.
+ if (flags & AVB_SLOT_VERIFY_FLAGS_RESTART_CAUSED_BY_HASHTREE_CORRUPTION) {
+ avb_debug(
+ "Rebooting because of dm-verity corruption - "
+ "recording OS instance and using 'eio' mode.\n");
+ avb_slot_verify_data_calculate_vbmeta_digest(
+ data, AVB_DIGEST_TYPE_SHA256, vbmeta_digest_sha256);
+ io_ret = ops->write_persistent_value(ops,
+ AVB_NPV_MANAGED_VERITY_MODE,
+ AVB_SHA256_DIGEST_SIZE,
+ vbmeta_digest_sha256);
+ if (io_ret != AVB_IO_RESULT_OK) {
+ avb_error("Error writing to " AVB_NPV_MANAGED_VERITY_MODE ".\n");
+ goto out;
+ }
+ ret = AVB_HASHTREE_ERROR_MODE_EIO;
+ io_ret = AVB_IO_RESULT_OK;
+ goto out;
+ }
+
+ // See if we're in 'eio' mode.
+ io_ret = ops->read_persistent_value(ops,
+ AVB_NPV_MANAGED_VERITY_MODE,
+ AVB_SHA256_DIGEST_SIZE,
+ stored_vbmeta_digest_sha256,
+ &num_bytes_read);
+ if (io_ret == AVB_IO_RESULT_ERROR_NO_SUCH_VALUE ||
+ (io_ret == AVB_IO_RESULT_OK && num_bytes_read == 0)) {
+ // This is the usual case ('eio' mode not set).
+ avb_debug("No dm-verity corruption - using in 'restart' mode.\n");
+ ret = AVB_HASHTREE_ERROR_MODE_RESTART;
+ io_ret = AVB_IO_RESULT_OK;
+ goto out;
+ } else if (io_ret != AVB_IO_RESULT_OK) {
+ avb_error("Error reading from " AVB_NPV_MANAGED_VERITY_MODE ".\n");
+ goto out;
+ }
+ if (num_bytes_read != AVB_SHA256_DIGEST_SIZE) {
+ avb_error(
+ "Unexpected number of bytes read from " AVB_NPV_MANAGED_VERITY_MODE
+ ".\n");
+ io_ret = AVB_IO_RESULT_ERROR_IO;
+ goto out;
+ }
+
+ // OK, so we're currently in 'eio' mode and the vbmeta digest of the OS
+ // that caused this is in |stored_vbmeta_digest_sha256| ... now see if
+ // the OS we're dealing with now is the same.
+ avb_slot_verify_data_calculate_vbmeta_digest(
+ data, AVB_DIGEST_TYPE_SHA256, vbmeta_digest_sha256);
+ if (avb_memcmp(vbmeta_digest_sha256,
+ stored_vbmeta_digest_sha256,
+ AVB_SHA256_DIGEST_SIZE) == 0) {
+ // It's the same so we're still in 'eio' mode.
+ avb_debug("Same OS instance detected - staying in 'eio' mode.\n");
+ ret = AVB_HASHTREE_ERROR_MODE_EIO;
+ io_ret = AVB_IO_RESULT_OK;
+ } else {
+ // It did change!
+ avb_debug(
+ "New OS instance detected - changing from 'eio' to 'restart' mode.\n");
+ io_ret =
+ ops->write_persistent_value(ops,
+ AVB_NPV_MANAGED_VERITY_MODE,
+ 0, // This clears the persistent property.
+ vbmeta_digest_sha256);
+ if (io_ret != AVB_IO_RESULT_OK) {
+ avb_error("Error clearing " AVB_NPV_MANAGED_VERITY_MODE ".\n");
+ goto out;
+ }
+ ret = AVB_HASHTREE_ERROR_MODE_RESTART;
+ io_ret = AVB_IO_RESULT_OK;
+ }
+
+out:
+ *out_hashtree_error_mode = ret;
+ return io_ret;
+}
+
+static bool has_system_partition(AvbOps* ops, const char* ab_suffix) {
+ char part_name[AVB_PART_NAME_MAX_SIZE];
+ char* system_part_name = "system";
+ char guid_buf[37];
+ AvbIOResult io_ret;
+
+ if (!avb_str_concat(part_name,
+ sizeof part_name,
+ system_part_name,
+ avb_strlen(system_part_name),
+ ab_suffix,
+ avb_strlen(ab_suffix))) {
+ avb_error("System partition name and suffix does not fit.\n");
+ return false;
+ }
+
+ io_ret = ops->get_unique_guid_for_partition(
+ ops, part_name, guid_buf, sizeof guid_buf);
+ if (io_ret == AVB_IO_RESULT_ERROR_NO_SUCH_PARTITION) {
+ avb_debug("No system partition.\n");
+ return false;
+ } else if (io_ret != AVB_IO_RESULT_OK) {
+ avb_error("Error getting unique GUID for system partition.\n");
+ return false;
+ }
+
+ return true;
+}
+
AvbSlotVerifyResult avb_slot_verify(AvbOps* ops,
const char* const* requested_partitions,
const char* ab_suffix,
AvbSlotVerifyFlags flags,
AvbHashtreeErrorMode hashtree_error_mode,
AvbSlotVerifyData** out_data) {
- AvbSlotVerifyResult ret;
+ AvbSlotVerifyResult ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT;
AvbSlotVerifyData* slot_data = NULL;
AvbAlgorithmType algorithm_type = AVB_ALGORITHM_TYPE_NONE;
bool using_boot_for_vbmeta = false;
@@ -1088,14 +1375,10 @@
(flags & AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR);
AvbCmdlineSubstList* additional_cmdline_subst = NULL;
- /* Fail early if we're missing the AvbOps needed for slot verification.
- *
- * For now, handle get_size_of_partition() not being implemented. In
- * a later release we may change that.
- */
+ /* Fail early if we're missing the AvbOps needed for slot verification. */
avb_assert(ops->read_is_device_unlocked != NULL);
avb_assert(ops->read_from_partition != NULL);
- avb_assert(ops->validate_vbmeta_public_key != NULL);
+ avb_assert(ops->get_size_of_partition != NULL);
avb_assert(ops->read_rollback_index != NULL);
avb_assert(ops->get_unique_guid_for_partition != NULL);
@@ -1113,6 +1396,36 @@
goto fail;
}
+ /* Make sure passed-in AvbOps support persistent values if
+ * asking for libavb to manage verity state.
+ */
+ if (hashtree_error_mode == AVB_HASHTREE_ERROR_MODE_MANAGED_RESTART_AND_EIO) {
+ if (ops->read_persistent_value == NULL ||
+ ops->write_persistent_value == NULL) {
+ avb_error(
+ "Persistent values required for "
+ "AVB_HASHTREE_ERROR_MODE_MANAGED_RESTART_AND_EIO "
+ "but are not implemented in given AvbOps.\n");
+ ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT;
+ goto fail;
+ }
+ }
+
+ /* Make sure passed-in AvbOps support verifying public keys and getting
+ * rollback index location if not using a vbmeta partition.
+ */
+ if (flags & AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION) {
+ if (ops->validate_public_key_for_partition == NULL) {
+ avb_error(
+ "AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION was passed but the "
+ "validate_public_key_for_partition() operation isn't implemented.\n");
+ ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT;
+ goto fail;
+ }
+ } else {
+ avb_assert(ops->validate_vbmeta_public_key != NULL);
+ }
+
slot_data = avb_calloc(sizeof(AvbSlotVerifyData));
if (slot_data == NULL) {
ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
@@ -1137,97 +1450,161 @@
goto fail;
}
- ret = load_and_verify_vbmeta(ops,
- requested_partitions,
- ab_suffix,
- allow_verification_error,
- 0 /* toplevel_vbmeta_flags */,
- 0 /* rollback_index_location */,
- "vbmeta",
- avb_strlen("vbmeta"),
- NULL /* expected_public_key */,
- 0 /* expected_public_key_length */,
- slot_data,
- &algorithm_type,
- additional_cmdline_subst);
- if (!allow_verification_error && ret != AVB_SLOT_VERIFY_RESULT_OK) {
+ if (flags & AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION) {
+ if (requested_partitions == NULL || requested_partitions[0] == NULL) {
+ avb_fatal(
+ "Requested partitions cannot be empty when using "
+ "AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION");
+ ret = AVB_SLOT_VERIFY_RESULT_ERROR_INVALID_ARGUMENT;
+ goto fail;
+ }
+
+ /* No vbmeta partition, go through each of the requested partitions... */
+ for (size_t n = 0; requested_partitions[n] != NULL; n++) {
+ ret = load_and_verify_vbmeta(ops,
+ requested_partitions,
+ ab_suffix,
+ flags,
+ allow_verification_error,
+ 0 /* toplevel_vbmeta_flags */,
+ 0 /* rollback_index_location */,
+ requested_partitions[n],
+ avb_strlen(requested_partitions[n]),
+ NULL /* expected_public_key */,
+ 0 /* expected_public_key_length */,
+ slot_data,
+ &algorithm_type,
+ additional_cmdline_subst);
+ if (!allow_verification_error && ret != AVB_SLOT_VERIFY_RESULT_OK) {
+ goto fail;
+ }
+ }
+
+ } else {
+ /* Usual path, load "vbmeta"... */
+ ret = load_and_verify_vbmeta(ops,
+ requested_partitions,
+ ab_suffix,
+ flags,
+ allow_verification_error,
+ 0 /* toplevel_vbmeta_flags */,
+ 0 /* rollback_index_location */,
+ "vbmeta",
+ avb_strlen("vbmeta"),
+ NULL /* expected_public_key */,
+ 0 /* expected_public_key_length */,
+ slot_data,
+ &algorithm_type,
+ additional_cmdline_subst);
+ if (!allow_verification_error && ret != AVB_SLOT_VERIFY_RESULT_OK) {
+ goto fail;
+ }
+ }
+
+ if (!result_should_continue(ret)) {
goto fail;
}
/* If things check out, mangle the kernel command-line as needed. */
- if (result_should_continue(ret)) {
+ if (!(flags & AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION)) {
if (avb_strcmp(slot_data->vbmeta_images[0].partition_name, "vbmeta") != 0) {
avb_assert(
avb_strcmp(slot_data->vbmeta_images[0].partition_name, "boot") == 0);
using_boot_for_vbmeta = true;
}
+ }
- /* Byteswap top-level vbmeta header since we'll need it below. */
- avb_vbmeta_image_header_to_host_byte_order(
- (const AvbVBMetaImageHeader*)slot_data->vbmeta_images[0].vbmeta_data,
- &toplevel_vbmeta);
+ /* Byteswap top-level vbmeta header since we'll need it below. */
+ avb_vbmeta_image_header_to_host_byte_order(
+ (const AvbVBMetaImageHeader*)slot_data->vbmeta_images[0].vbmeta_data,
+ &toplevel_vbmeta);
- /* Fill in |ab_suffix| field. */
- slot_data->ab_suffix = avb_strdup(ab_suffix);
- if (slot_data->ab_suffix == NULL) {
+ /* Fill in |ab_suffix| field. */
+ slot_data->ab_suffix = avb_strdup(ab_suffix);
+ if (slot_data->ab_suffix == NULL) {
+ ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
+ goto fail;
+ }
+
+ /* If verification is disabled, we are done ... we specifically
+ * don't want to add any androidboot.* options since verification
+ * is disabled.
+ */
+ if (toplevel_vbmeta.flags & AVB_VBMETA_IMAGE_FLAGS_VERIFICATION_DISABLED) {
+ /* Since verification is disabled we didn't process any
+ * descriptors and thus there's no cmdline... so set root= such
+ * that the system partition is mounted.
+ */
+ avb_assert(slot_data->cmdline == NULL);
+ // Devices with dynamic partitions won't have system partition.
+ // Instead, it has a large super partition to accommodate *.img files.
+ // See b/119551429 for details.
+ if (has_system_partition(ops, ab_suffix)) {
+ slot_data->cmdline =
+ avb_strdup("root=PARTUUID=$(ANDROID_SYSTEM_PARTUUID)");
+ } else {
+ // The |cmdline| field should be a NUL-terminated string.
+ slot_data->cmdline = avb_strdup("");
+ }
+ if (slot_data->cmdline == NULL) {
ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
goto fail;
}
+ } else {
+ /* If requested, manage dm-verity mode... */
+ AvbHashtreeErrorMode resolved_hashtree_error_mode = hashtree_error_mode;
+ if (hashtree_error_mode ==
+ AVB_HASHTREE_ERROR_MODE_MANAGED_RESTART_AND_EIO) {
+ AvbIOResult io_ret;
+ io_ret = avb_manage_hashtree_error_mode(
+ ops, flags, slot_data, &resolved_hashtree_error_mode);
+ if (io_ret != AVB_IO_RESULT_OK) {
+ ret = AVB_SLOT_VERIFY_RESULT_ERROR_IO;
+ if (io_ret == AVB_IO_RESULT_ERROR_OOM) {
+ ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
+ }
+ goto fail;
+ }
+ }
+ slot_data->resolved_hashtree_error_mode = resolved_hashtree_error_mode;
- /* If verification is disabled, we are done ... we specifically
- * don't want to add any androidboot.* options since verification
- * is disabled.
- */
- if (toplevel_vbmeta.flags & AVB_VBMETA_IMAGE_FLAGS_VERIFICATION_DISABLED) {
- /* Since verification is disabled we didn't process any
- * descriptors and thus there's no cmdline... so set root= such
- * that the system partition is mounted.
- */
- avb_assert(slot_data->cmdline == NULL);
- slot_data->cmdline =
- avb_strdup("root=PARTUUID=$(ANDROID_SYSTEM_PARTUUID)");
- if (slot_data->cmdline == NULL) {
+ /* Add options... */
+ AvbSlotVerifyResult sub_ret;
+ sub_ret = avb_append_options(ops,
+ flags,
+ slot_data,
+ &toplevel_vbmeta,
+ algorithm_type,
+ hashtree_error_mode,
+ resolved_hashtree_error_mode);
+ if (sub_ret != AVB_SLOT_VERIFY_RESULT_OK) {
+ ret = sub_ret;
+ goto fail;
+ }
+ }
+
+ /* Substitute $(ANDROID_SYSTEM_PARTUUID) and friends. */
+ if (slot_data->cmdline != NULL && avb_strlen(slot_data->cmdline) != 0) {
+ char* new_cmdline;
+ new_cmdline = avb_sub_cmdline(ops,
+ slot_data->cmdline,
+ ab_suffix,
+ using_boot_for_vbmeta,
+ additional_cmdline_subst);
+ if (new_cmdline != slot_data->cmdline) {
+ if (new_cmdline == NULL) {
ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
goto fail;
}
- } else {
- /* Add options - any failure in avb_append_options() is either an
- * I/O or OOM error.
- */
- AvbSlotVerifyResult sub_ret = avb_append_options(ops,
- slot_data,
- &toplevel_vbmeta,
- algorithm_type,
- hashtree_error_mode);
- if (sub_ret != AVB_SLOT_VERIFY_RESULT_OK) {
- ret = sub_ret;
- goto fail;
- }
+ avb_free(slot_data->cmdline);
+ slot_data->cmdline = new_cmdline;
}
+ }
- /* Substitute $(ANDROID_SYSTEM_PARTUUID) and friends. */
- if (slot_data->cmdline != NULL) {
- char* new_cmdline;
- new_cmdline = avb_sub_cmdline(ops,
- slot_data->cmdline,
- ab_suffix,
- using_boot_for_vbmeta,
- additional_cmdline_subst);
- if (new_cmdline != slot_data->cmdline) {
- if (new_cmdline == NULL) {
- ret = AVB_SLOT_VERIFY_RESULT_ERROR_OOM;
- goto fail;
- }
- avb_free(slot_data->cmdline);
- slot_data->cmdline = new_cmdline;
- }
- }
-
- if (out_data != NULL) {
- *out_data = slot_data;
- } else {
- avb_slot_verify_data_free(slot_data);
- }
+ if (out_data != NULL) {
+ *out_data = slot_data;
+ } else {
+ avb_slot_verify_data_free(slot_data);
}
avb_free_cmdline_subst_list(additional_cmdline_subst);
diff --git a/lib/libavb/avb_slot_verify.h b/lib/libavb/avb_slot_verify.h
index 73fd70d..015a3ed 100644
--- a/lib/libavb/avb_slot_verify.h
+++ b/lib/libavb/avb_slot_verify.h
@@ -24,7 +24,7 @@
* representation usable for error/debug output.
*/
typedef enum {
- AVB_SLOT_VERIFY_RESULT_OK,
+ AVB_SLOT_VERIFY_RESULT_OK = 0,
AVB_SLOT_VERIFY_RESULT_ERROR_OOM,
AVB_SLOT_VERIFY_RESULT_ERROR_IO,
AVB_SLOT_VERIFY_RESULT_ERROR_VERIFICATION,
@@ -51,12 +51,25 @@
* be used ONLY for diagnostics and debugging. It cannot be used
* unless AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR is also
* used.
+ *
+ * AVB_HASHTREE_ERROR_MODE_MANAGED_RESTART_AND_EIO means that either
+ * AVB_HASHTREE_ERROR_MODE_RESTART or AVB_HASHTREE_ERROR_MODE_EIO is used
+ * depending on state. This mode implements a state machine whereby
+ * AVB_HASHTREE_ERROR_MODE_RESTART is used by default and when
+ * AVB_SLOT_VERIFY_FLAGS_RESTART_CAUSED_BY_HASHTREE_CORRUPTION is passed the
+ * mode transitions to AVB_HASHTREE_ERROR_MODE_EIO. When a new OS has been
+ * detected the device transitions back to the AVB_HASHTREE_ERROR_MODE_RESTART
+ * mode. To do this persistent storage is needed - specifically this means that
+ * the passed in AvbOps will need to have the read_persistent_value() and
+ * write_persistent_value() operations implemented. The name of the persistent
+ * value used is "avb.managed_verity_mode" and 32 bytes of storage is needed.
*/
typedef enum {
AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE,
AVB_HASHTREE_ERROR_MODE_RESTART,
AVB_HASHTREE_ERROR_MODE_EIO,
- AVB_HASHTREE_ERROR_MODE_LOGGING
+ AVB_HASHTREE_ERROR_MODE_LOGGING,
+ AVB_HASHTREE_ERROR_MODE_MANAGED_RESTART_AND_EIO
} AvbHashtreeErrorMode;
/* Flags that influence how avb_slot_verify() works.
@@ -80,10 +93,26 @@
* contents loaded from |requested_partition| will be the contents of
* the entire partition instead of just the size specified in the hash
* descriptor.
+ *
+ * The AVB_SLOT_VERIFY_FLAGS_RESTART_CAUSED_BY_HASHTREE_CORRUPTION flag
+ * should be set if using AVB_HASHTREE_ERROR_MODE_MANAGED_RESTART_AND_EIO
+ * and the reason the boot loader is running is because the device
+ * was restarted by the dm-verity driver.
+ *
+ * If the AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION flag is set then
+ * data won't be loaded from the "vbmeta" partition and the
+ * |validate_vbmeta_public_key| operation is never called. Instead, the
+ * vbmeta structs in |requested_partitions| are loaded and processed and the
+ * |validate_public_key_for_partition| operation is called for each of these
+ * vbmeta structs. This flag is useful when booting into recovery on a device
+ * not using A/B - see section "Booting into recovery" in README.md for
+ * more information.
*/
typedef enum {
AVB_SLOT_VERIFY_FLAGS_NONE = 0,
- AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR = (1 << 0)
+ AVB_SLOT_VERIFY_FLAGS_ALLOW_VERIFICATION_ERROR = (1 << 0),
+ AVB_SLOT_VERIFY_FLAGS_RESTART_CAUSED_BY_HASHTREE_CORRUPTION = (1 << 1),
+ AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION = (1 << 2),
} AvbSlotVerifyFlags;
/* Get a textual representation of |result|. */
@@ -188,6 +217,10 @@
* set to AVB_HASHTREE_ERROR_MODE_EIO, and 'logging' if it's set to
* AVB_HASHTREE_ERROR_MODE_LOGGING.
*
+ * androidboot.veritymode.managed: This is set to 'yes' only
+ * if hashtree validation isn't disabled and the passed-in hashtree
+ * error mode is AVB_HASHTREE_ERROR_MODE_MANAGED_RESTART_AND_EIO.
+ *
* androidboot.vbmeta.invalidate_on_error: This is set to 'yes' only
* if hashtree validation isn't disabled and the passed-in hashtree
* error mode is AVB_HASHTREE_ERROR_MODE_RESTART_AND_INVALIDATE.
@@ -203,7 +236,9 @@
* PARTUUID=$(ANDROID_VBMETA_PARTUUID) before substitution so it
* will end up pointing to the vbmeta partition for the verified
* slot. If there is no vbmeta partition it will point to the boot
- * partition of the verified slot.
+ * partition of the verified slot. If the flag
+ * AVB_SLOT_VERIFY_FLAGS_NO_VBMETA_PARTITION is used, this is not
+ * set.
*
* androidboot.vbmeta.avb_version: This is set to the decimal value
* of AVB_VERSION_MAJOR followed by a dot followed by the decimal
@@ -228,6 +263,15 @@
* appropriate system partition is substituted in. Note that none of
* the androidboot.* options mentioned above will be set.
*
+ * The |resolved_hashtree_error_mode| is the the value of the passed
+ * avb_slot_verify()'s |hashtree_error_mode| parameter except that it never has
+ * the value AVB_HASHTREE_ERROR_MODE_MANAGED_RESTART_AND_EIO. If this value was
+ * passed in, then the restart/eio state machine is used resulting in
+ * |resolved_hashtree_error_mode| being set to either
+ * AVB_HASHTREE_ERROR_MODE_RESTART or AVB_HASHTREE_ERROR_MODE_EIO. If set to
+ * AVB_HASHTREE_ERROR_MODE_EIO the boot loader should present a RED warning
+ * screen for the user to click through before continuing to boot.
+ *
* This struct may grow in the future without it being considered an
* ABI break.
*/
@@ -239,8 +283,11 @@
size_t num_loaded_partitions;
char* cmdline;
uint64_t rollback_indexes[AVB_MAX_NUMBER_OF_ROLLBACK_INDEX_LOCATIONS];
+ AvbHashtreeErrorMode resolved_hashtree_error_mode;
} AvbSlotVerifyData;
+extern uint8_t boot_key_hash[AVB_SHA256_DIGEST_SIZE];
+
/* Calculates a digest of all vbmeta images in |data| using
* the digest indicated by |digest_type|. Stores the result
* in |out_digest| which must be large enough to hold a digest
@@ -282,12 +329,8 @@
* ignore verification errors which is something needed in the
* UNLOCKED state. See the AvbSlotVerifyFlags enumeration for details.
*
- * The |hashtree_error_mode| parameter should be set to the desired
- * error handling mode when hashtree validation fails inside the
- * HLOS. This value isn't used by libavb per se - it is forwarded to
- * the HLOS through the androidboot.veritymode and
- * androidboot.vbmeta.invalidate_on_error cmdline parameters. See the
- * AvbHashtreeErrorMode enumeration for details.
+ * The |hashtree_error_mode| parameter should be set to the desired error
+ * handling mode. See the AvbHashtreeErrorMode enumeration for details.
*
* Also note that |out_data| is never set if
* AVB_SLOT_VERIFY_RESULT_ERROR_OOM, AVB_SLOT_VERIFY_RESULT_ERROR_IO,
diff --git a/lib/libavb/avb_sysdeps.h b/lib/libavb/avb_sysdeps.h
index f032de4..f52428c 100644
--- a/lib/libavb/avb_sysdeps.h
+++ b/lib/libavb/avb_sysdeps.h
@@ -53,6 +53,14 @@
*/
int avb_strcmp(const char* s1, const char* s2);
+/* Compare |n| bytes in two strings.
+ *
+ * Return an integer less than, equal to, or greater than zero if the
+ * first |n| bytes of |s1| is found, respectively, to be less than,
+ * to match, or be greater than the first |n| bytes of |s2|.
+ */
+int avb_strncmp(const char* s1, const char* s2, size_t n);
+
/* Copy |n| bytes from |src| to |dest|. */
void* avb_memcpy(void* dest, const void* src, size_t n);
diff --git a/lib/libavb/avb_sysdeps_posix.c b/lib/libavb/avb_sysdeps_posix.c
index 819558f..2e9ebc9 100644
--- a/lib/libavb/avb_sysdeps_posix.c
+++ b/lib/libavb/avb_sysdeps_posix.c
@@ -23,6 +23,10 @@
return strcmp(s1, s2);
}
+int avb_strncmp(const char* s1, const char* s2, size_t n) {
+ return strncmp(s1, s2, n);
+}
+
size_t avb_strlen(const char* str) {
return strlen(str);
}
diff --git a/lib/libavb/avb_vbmeta_image.c b/lib/libavb/avb_vbmeta_image.c
index ca3c198..3d7f3e6 100644
--- a/lib/libavb/avb_vbmeta_image.c
+++ b/lib/libavb/avb_vbmeta_image.c
@@ -35,17 +35,18 @@
*out_public_key_length = 0;
}
+ /* Before we byteswap or compare Magic, ensure length is long enough. */
+ if (length < sizeof(AvbVBMetaImageHeader)) {
+ avb_error("Length is smaller than header.\n");
+ goto out;
+ }
+
/* Ensure magic is correct. */
if (avb_safe_memcmp(data, AVB_MAGIC, AVB_MAGIC_LEN) != 0) {
avb_error("Magic is incorrect.\n");
goto out;
}
- /* Before we byteswap, ensure length is long enough. */
- if (length < sizeof(AvbVBMetaImageHeader)) {
- avb_error("Length is smaller than header.\n");
- goto out;
- }
avb_vbmeta_image_header_to_host_byte_order((const AvbVBMetaImageHeader*)data,
&h);
diff --git a/lib/libavb/testkey.c b/lib/libavb/testkey.c
index 3440146..d7f6dcc 100644
--- a/lib/libavb/testkey.c
+++ b/lib/libavb/testkey.c
@@ -1,4 +1,7 @@
-const char testkey2048[520] = {
+#include <stdint.h>
+#include <stddef.h>
+
+const uint8_t avb2_kpub_default[] = {
0x00, 0x00, 0x08, 0x00, 0xc9, 0xd8, 0x7d, 0x7b, 0xc6, 0x55, 0x51,
0xdd, 0x32, 0x24, 0xa2, 0xe0, 0x0e, 0xbc, 0x7e, 0xfd, 0xbd, 0xa2,
0x53, 0x80, 0x58, 0x69, 0x7e, 0xf5, 0x4a, 0x40, 0x87, 0x95, 0x90,
@@ -49,4 +52,4 @@
0x03, 0xb9, 0x81
};
-const int testkey2048_length = 520;
+const size_t avb2_kpub_default_len = sizeof(avb2_kpub_default) / sizeof(uint8_t);
diff --git a/lib/libfdt/fdt_region.c b/lib/libfdt/fdt_region.c
index d52facc..7e9fa92 100644
--- a/lib/libfdt/fdt_region.c
+++ b/lib/libfdt/fdt_region.c
@@ -13,7 +13,6 @@
#else
#include "fdt_host.h"
#endif
-#include <linux/kconfig.h>
#define FDT_MAX_DEPTH 32
@@ -42,7 +41,6 @@
int depth = -1;
int want = 0;
int base = fdt_off_dt_struct(fdt);
- int expect_end = 0;
end = path;
*end = '\0';
@@ -59,10 +57,6 @@
tag = fdt_next_tag(fdt, offset, &nextoffset);
stop_at = nextoffset;
- /* If we see two root nodes, something is wrong */
- if (expect_end && tag != FDT_END)
- return -FDT_ERR_BADLAYOUT;
-
switch (tag) {
case FDT_PROP:
include = want >= 2;
@@ -83,10 +77,6 @@
if (depth == FDT_MAX_DEPTH)
return -FDT_ERR_BADSTRUCTURE;
name = fdt_get_name(fdt, offset, &len);
-
- /* The root node must have an empty name */
- if (!depth && *name)
- return -FDT_ERR_BADLAYOUT;
if (end - path + 2 + len >= path_len)
return -FDT_ERR_NOSPACE;
if (end != path + 1)
@@ -114,8 +104,6 @@
while (end > path && *--end != '/')
;
*end = '\0';
- if (depth == -1)
- expect_end = 1;
break;
case FDT_END:
diff --git a/lib/lmb.c b/lib/lmb.c
index cb247f6..1705417 100644
--- a/lib/lmb.c
+++ b/lib/lmb.c
@@ -104,19 +104,6 @@
lmb->reserved.size = 0;
}
-/* Initialize the struct, add memory and call arch/board reserve functions */
-void lmb_init_and_reserve(struct lmb *lmb, phys_addr_t base, phys_size_t size,
- void *fdt_blob)
-{
- lmb_init(lmb);
- lmb_add(lmb, base, size);
- arch_lmb_reserve(lmb);
- board_lmb_reserve(lmb);
-
- if (IMAGE_ENABLE_OF_LIBFDT && fdt_blob)
- boot_fdt_add_mem_rsv_regions(lmb, fdt_blob);
-}
-
/* This routine called with relocation disabled. */
static long lmb_add_region(struct lmb_region *rgn, phys_addr_t base, phys_size_t size)
{
@@ -356,29 +343,3 @@
{
/* please define platform specific arch_lmb_reserve() */
}
-
-/*
- * Try to allocate a specific address range: must be in defined memory but not
- * reserved
- */
-phys_addr_t lmb_alloc_addr(struct lmb *lmb, phys_addr_t base, phys_size_t size)
-{
- long rgn;
-
- /* Check if the requested address is in one of the memory regions */
- rgn = lmb_overlaps_region(&lmb->memory, base, size);
- if (rgn >= 0) {
- /*
- * Check if the requested end address is in the same memory
- * region we found.
- */
- if (lmb_addrs_overlap(lmb->memory.region[rgn].base,
- lmb->memory.region[rgn].size,
- base + size - 1, 1)) {
- /* ok, reserve the memory */
- if (lmb_reserve(lmb, base, size) >= 0)
- return base;
- }
- }
- return 0;
-}
diff --git a/lib/optee/Kconfig b/lib/optee/Kconfig
index 838e686..3773d89 100644
--- a/lib/optee/Kconfig
+++ b/lib/optee/Kconfig
@@ -37,4 +37,3 @@
Select this command to enable chain-loading of a Linux kernel
via an OPTEE firmware.
The bootflow is BootROM -> u-boot -> OPTEE -> Linux in this case.
-
diff --git a/lib/panic.c b/lib/panic.c
index bae8a35..60259fa 100644
--- a/lib/panic.c
+++ b/lib/panic.c
@@ -53,3 +53,18 @@
panic("%s:%u: %s: Assertion `%s' failed.", file, line, function,
assertion);
}
+
+#define STACK_CHECK_GUARD 0xdeadbeefdeadbeefUL
+uintptr_t __stack_chk_guard = STACK_CHECK_GUARD;
+void __attribute__ ((noreturn)) __stack_chk_fail(void)
+{
+ unsigned long pc_reg;
+
+ __asm__ volatile("mov %0, x30\n"
+ : "=r" (pc_reg)
+ :
+ : "memory");
+ /* This will not return */
+ panic("Stack-protector: stack smashing detected at caller 0x%lx !\n",
+ (pc_reg - 0x4));
+}
diff --git a/lib/rsa/Kconfig b/lib/rsa/Kconfig
index bdeb3b6..2b33f32 100644
--- a/lib/rsa/Kconfig
+++ b/lib/rsa/Kconfig
@@ -35,4 +35,3 @@
accelerator - CAAM.
endif
-
diff --git a/lib/rsa/rsa-sign.c b/lib/rsa/rsa-sign.c
index 8af2c8b..fb5e07b 100644
--- a/lib/rsa/rsa-sign.c
+++ b/lib/rsa/rsa-sign.c
@@ -773,7 +773,7 @@
}
if (!ret) {
- ret = fdt_setprop_string(keydest, node, FIT_KEY_HINT,
+ ret = fdt_setprop_string(keydest, node, "key-name-hint",
info->keyname);
}
if (!ret)
@@ -796,7 +796,7 @@
info->name);
}
if (!ret && info->require_keys) {
- ret = fdt_setprop_string(keydest, node, FIT_KEY_REQUIRED,
+ ret = fdt_setprop_string(keydest, node, "required",
info->require_keys);
}
done:
diff --git a/lib/sha256.c b/lib/sha256.c
index c1fe93d..ad5d83b 100644
--- a/lib/sha256.c
+++ b/lib/sha256.c
@@ -40,7 +40,7 @@
}
#endif
-void sha256_starts(sha256_context * ctx)
+void __attribute__((weak)) sha256_starts(sha256_context * ctx)
{
ctx->total[0] = 0;
ctx->total[1] = 0;
@@ -186,7 +186,7 @@
ctx->state[7] += H;
}
-void sha256_update(sha256_context *ctx, const uint8_t *input, uint32_t length)
+void __attribute__((weak)) sha256_update(sha256_context *ctx, const uint8_t *input, uint32_t length)
{
uint32_t left, fill;
@@ -227,7 +227,7 @@
0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
};
-void sha256_finish(sha256_context * ctx, uint8_t digest[32])
+void __attribute__((weak)) sha256_finish(sha256_context * ctx, uint8_t digest[32])
{
uint32_t last, padn;
uint32_t high, low;
@@ -260,7 +260,7 @@
* Output = SHA-256( input buffer ). Trigger the watchdog every 'chunk_sz'
* bytes of input processed.
*/
-void sha256_csum_wd(const unsigned char *input, unsigned int ilen,
+void __attribute__((weak)) sha256_csum_wd(const unsigned char *input, unsigned int ilen,
unsigned char *output, unsigned int chunk_sz)
{
sha256_context ctx;
diff --git a/lib/uuid.c b/lib/uuid.c
index a67a363..d1bd330 100644
--- a/lib/uuid.c
+++ b/lib/uuid.c
@@ -81,32 +81,6 @@
#ifdef CONFIG_PARTITION_TYPE_GUID
-#ifdef CONFIG_AML_GPT
- static const struct {
- const char *string;
- efi_guid_t guid;
- } list_guid[] = {
- {"bootloader", PARTITION_ANDROID_BOOTLOADER_GUID},
- {"bootloader2", PARTITION_ANDROID_BOOTLOADER2_GUID},
- {"recovery", PARTITION_ANDROID_RECOVERY_GUID},
- {"misc", PARTITION_ANDROID_MISC_GUID},
- {"metadata", PARTITION_ANDROID_METADATA_GUID},
- {"system", PARTITION_ANDROID_SYSTEM_GUID},
- {"cache", PARTITION_ANDROID_CACHE_GUID},
- {"data", PARTITION_ANDROID_DATA_GUID},
- {"persistent", PARTITION_ANDROID_PERSISTENT_GUID},
- {"vendor", PARTITION_ANDROID_VENDOR_GUID},
- {"config", PARTITION_ANDROID_CONFIG_GUID},
- {"factory", PARTITION_ANDROID_FACTORY_GUID},
- {"factory_alt", PARTITION_ANDROID_FACTORY_ALT_GUID},
- {"fastboot", PARTITION_ANDROID_FASTBOOT_GUID},
- {"tertiary", PARTITION_ANDROID_TERTIARY_GUID},
- {"oem", PARTITION_ANDROID_OEM_GUID},
- {"default", PARTITION_LINUX_DEFAULT_GUID}
- };
-
-#else
-
static const struct {
const char *string;
efi_guid_t guid;
@@ -120,7 +94,7 @@
{"swap", PARTITION_LINUX_SWAP_GUID},
{"lvm", PARTITION_LINUX_LVM_GUID}
};
-#endif
+
/*
* uuid_guid_get_bin() - this function get GUID bin for string
*
@@ -265,8 +239,6 @@
unsigned int *ptr = (unsigned int *)&uuid;
int i;
- srand(get_ticks() + rand());
-
/* Set all fields randomly */
for (i = 0; i < sizeof(struct uuid) / sizeof(*ptr); i++)
*(ptr + i) = cpu_to_be32(rand());
diff --git a/mk b/mk
deleted file mode 100755
index 9b77926..0000000
--- a/mk
+++ /dev/null
@@ -1,4 +0,0 @@
-#!/bin/bash
-### DO NOT EDIT THIS FILE ###
-source fip/mk_script.sh
-### DO NOT EDIT THIS FILE ###
diff --git a/net/Kconfig b/net/Kconfig
index ae751c8..131432d 100644
--- a/net/Kconfig
+++ b/net/Kconfig
@@ -24,4 +24,3 @@
See README.NetConsole for details.
endif # if NET
-
diff --git a/net/eth-uclass.c b/net/eth-uclass.c
index 7b1fed4..c74e806 100644
--- a/net/eth-uclass.c
+++ b/net/eth-uclass.c
@@ -13,7 +13,10 @@
#include <dm/uclass-internal.h>
#include "eth_internal.h"
#include <amlogic/keyunify.h>
-#include <asm/arch/cpu_id.h>
+#include <amlogic/cpu_id.h>
+#if defined MAC_ADDR_NEW
+#include <asm/arch/register.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -459,7 +462,6 @@
static int eth_get_efuse_mac(struct udevice *dev)
{
- struct eth_pdata *pdata = dev->platdata;
#ifndef CONFIG_UNIFY_KEY_MANAGE
debug("\nWarning: %s MAC addresses is not from dtb\n",
dev->name);
@@ -471,6 +473,7 @@
ssize_t keysize = 0;
const char* seedNum = "0x1234";
unsigned char buf[MAC_MAX_LEN+1] = {0};
+ struct eth_pdata *pdata = dev->platdata;
err = key_unify_init(seedNum, NULL);
if (err)
@@ -500,6 +503,8 @@
return key_unify_uninit();
#endif
}
+
+static char env_str[32];
static int eth_post_probe(struct udevice *dev)
{
struct eth_device_priv *priv = dev->uclass_priv;
@@ -545,14 +550,22 @@
eth_env_set_enetaddr_by_index("eth", ARP_HLEN,
pdata->enetaddr);
} else {
+#if defined MAC_ADDR_NEW
+ unsigned int reg18;
+ reg18 = *(unsigned int *)SYSCTRL_SEC_STATUS_REG18;
+ sprintf((char *)env_str,"02:ad:%02x:01:%02x:%02x", ((reg18 >> 24) & 0xff),
+ ((reg18 >> 8) & 0xff), (reg18 & 0xff));
+ printf("MACADDR:%s(from sec_reg)\n", env_str);
+ env_set("ethaddr", (const char *)env_str);
+#else
uint8_t buff[16];
if (get_chip_id(&buff[0], sizeof(buff)) == 0) {
- sprintf((char *)env_enetaddr,"02:%02x:%02x:%02x:%02x:%02x",buff[8],
- buff[7],buff[6],buff[5],buff[4]);
- printf("MACADDR:%s(from chipid)\n",env_enetaddr);
- env_set("ethaddr",(const char *)env_enetaddr);
+ sprintf((char *)env_str,"02:%02x:%02x:%02x:%02x:%02x", buff[8],
+ buff[7], buff[6], buff[5], buff[4]);
+ printf("MACADDR:%s(from chipid)\n", env_str);
+ env_set("ethaddr", (const char *)env_str);
}
-
+#endif
eth_env_get_enetaddr_by_index("eth", dev->seq, env_enetaddr);
if (!is_zero_ethaddr(env_enetaddr)) {
if (!is_zero_ethaddr(pdata->enetaddr) &&
diff --git a/net/eth_legacy.c b/net/eth_legacy.c
index 1c26ba5..09dc11e 100644
--- a/net/eth_legacy.c
+++ b/net/eth_legacy.c
@@ -10,9 +10,13 @@
#include <environment.h>
#include <net.h>
#include <phy.h>
+#include <amlogic/keyunify.h>
#include <linux/errno.h>
#include "eth_internal.h"
-
+#include <amlogic/cpu_id.h>
+#if defined MAC_ADDR_NEW
+#include <asm/arch/register.h>
+#endif
DECLARE_GLOBAL_DATA_PTR;
/*
@@ -173,6 +177,7 @@
return key_unify_uninit();
#endif
}
+static char env_str[32];
int eth_write_hwaddr(struct eth_device *dev, const char *base_name,
int eth_number)
{
@@ -185,14 +190,22 @@
eth_env_set_enetaddr_by_index(base_name, eth_number,
dev->enetaddr);
} else {
+#if defined MAC_ADDR_NEW
+ unsigned int reg18;
+ reg18 = *(unsigned int *)SYSCTRL_SEC_STATUS_REG18;
+ sprintf((char *)env_str,"02:ad:%02x:01:%02x:%02x", ((reg18 >> 24) & 0xff),
+ ((reg18 >> 8) & 0xff), (reg18 & 0xff));
+ printf("MACADDR:%s(from sec_reg)\n", env_str);
+ env_set("ethaddr", (const char *)env_str);
+#else
uint8_t buff[16];
if (get_chip_id(&buff[0], sizeof(buff)) == 0) {
- sprintf((char *)env_enetaddr,"02:%02x:%02x:%02x:%02x:%02x",buff[8],
- buff[7],buff[6],buff[5],buff[4]);
- printf("MACADDR:%s(from chipid)\n",env_enetaddr);
- env_set("ethaddr",(const char *)env_enetaddr);
+ sprintf((char *)env_str,"02:%02x:%02x:%02x:%02x:%02x", buff[8],
+ buff[7], buff[6], buff[5], buff[4]);
+ printf("MACADDR:%s(from chipid)\n", env_str);
+ env_set("ethaddr", (const char *)env_str);
}
-
+#endif
eth_env_get_enetaddr_by_index(base_name, eth_number, env_enetaddr);
if (!is_zero_ethaddr(env_enetaddr)) {
diff --git a/net/net.c b/net/net.c
index ecc1649..644c550 100644
--- a/net/net.c
+++ b/net/net.c
@@ -118,6 +118,10 @@
#include "wol.h"
#endif
+#define ETHLOOP_LEN 256
+static void EthLoopStart(void);
+static void EthLoopHandler (uchar * pkt, unsigned dest, struct in_addr sip, unsigned src, unsigned len);
+
/** BOOTP EXTENTIONS **/
/* Our subnet mask (0=unknown) */
@@ -154,6 +158,7 @@
/* Ethernet bcast address */
const u8 net_bcast_ethaddr[6] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
const u8 net_null_ethaddr[6];
+u8 EtherPacket[ETHLOOP_LEN]; /* buffer for loopback test frame */
#if defined(CONFIG_API) || defined(CONFIG_EFI_LOADER)
void (*push_packet)(void *, int len) = 0;
#endif
@@ -484,6 +489,9 @@
bootp_request();
break;
+ case ETHLOOP:
+ EthLoopStart();
+ break;
#if defined(CONFIG_CMD_RARP)
case RARP:
rarp_try = 0;
@@ -1174,6 +1182,9 @@
}
switch (eth_proto) {
+ case PROT_TEST:
+ EthLoopHandler((uchar *)net_rx_packet, 0, net_ip, 0, net_rx_packet_len);
+ break;
case PROT_ARP:
arp_receive(et, ip, len);
break;
@@ -1258,9 +1269,6 @@
return;
}
- if (ntohs(ip->udp_len) < UDP_HDR_SIZE || ntohs(ip->udp_len) > ntohs(ip->ip_len))
- return;
-
debug_cond(DEBUG_DEV_PKT,
"received UDP (to=%pI4, from=%pI4, len=%d)\n",
&dst_ip, &src_ip, len);
@@ -1389,6 +1397,7 @@
#ifdef CONFIG_CMD_RARP
case RARP:
#endif
+ case ETHLOOP:
case BOOTP:
case CDP:
case DHCP:
@@ -1481,6 +1490,48 @@
}
}
+
+int EthLoopSend(void)
+{
+ int i;
+ uchar *pkt;
+
+ for (i=0 ; i<ETHLOOP_LEN ; i++) {
+ EtherPacket[i] = i;
+ }
+ pkt = (uchar *)EtherPacket;
+ pkt += net_set_ether(pkt, net_ethaddr, PROT_TEST); /* set our MAC address as destination address */
+ (void) eth_send(EtherPacket, ETHLOOP_LEN);
+
+ return 1; /* waiting */
+}
+
+static void EthLoopTimeout (void)
+{
+ eth_halt();
+ net_set_state(NETLOOP_FAIL); /* we did not get the reply */
+}
+
+static void EthLoopHandler (uchar * pkt, unsigned dest, struct in_addr sip, unsigned src, unsigned len)
+{
+ int i;
+
+ net_set_state(NETLOOP_SUCCESS);
+ len -= 4;
+ for (i=0 ; i<len ; i++) {
+ if (EtherPacket[i] != pkt[i]) {
+ net_set_state(NETLOOP_FAIL);
+ break;
+ }
+ }
+}
+
+static void EthLoopStart(void)
+{
+ net_set_timeout_handler(10000UL, EthLoopTimeout);
+ EthLoopSend();
+}
+
void net_set_ip_header(uchar *pkt, struct in_addr dest, struct in_addr source,
u16 pkt_len, u8 proto)
{
diff --git a/net/nfs.c b/net/nfs.c
index 3123e22..d6a7f8e 100644
--- a/net/nfs.c
+++ b/net/nfs.c
@@ -566,15 +566,11 @@
}
if (supported_nfs_versions & NFSV2_FLAG) {
- if (((uchar *)&rpc_pkt.u.reply.data[0] - (uchar *)&rpc_pkt + NFS_FHSIZE) > len)
- return -NFS_RPC_DROP;
memcpy(filefh, rpc_pkt.u.reply.data + 1, NFS_FHSIZE);
} else { /* NFSV3_FLAG */
filefh3_length = ntohl(rpc_pkt.u.reply.data[1]);
if (filefh3_length > NFS3_FHSIZE)
filefh3_length = NFS3_FHSIZE;
- if (((uchar *)&rpc_pkt.u.reply.data[0] - (uchar *)&rpc_pkt + filefh3_length) > len)
- return -NFS_RPC_DROP;
memcpy(filefh, rpc_pkt.u.reply.data + 2, filefh3_length);
}
@@ -638,9 +634,6 @@
/* new path length */
rlen = ntohl(rpc_pkt.u.reply.data[1 + nfsv3_data_offset]);
- if (((uchar *)&rpc_pkt.u.reply.data[0] - (uchar *)&rpc_pkt + rlen) > len)
- return -NFS_RPC_DROP;
-
if (*((char *)&(rpc_pkt.u.reply.data[2 + nfsv3_data_offset])) != '/') {
int pathlen;
@@ -708,11 +701,8 @@
&(rpc_pkt.u.reply.data[4 + nfsv3_data_offset]);
}
- if (((uchar *)&rpc_pkt.u.reply.data[0] - (uchar *)&rpc_pkt + rlen) > len)
- return -9999;
-
if (store_block(data_ptr, nfs_offset, rlen))
- return -9999;
+ return -9999;
return rlen;
}
@@ -742,9 +732,6 @@
debug("%s\n", __func__);
- if (len > sizeof(struct rpc_t))
- return;
-
if (dest != nfs_our_port)
return;
diff --git a/scripts/Makefile.autoconf b/scripts/Makefile.autoconf
index 00b8fb3..8a257fe 100644
--- a/scripts/Makefile.autoconf
+++ b/scripts/Makefile.autoconf
@@ -95,6 +95,26 @@
$(Q)mkdir -p $(dir $@)
$(call cmd,autoconf)
+# support amlogic config folder and customer folder
+
+# 1st. this is old u-boot config file folder
+config_file=$(shell echo "$(srctree)/include/configs/$(CONFIG_SYS_CONFIG_NAME).h")
+ifneq ($(config_file), $(wildcard $(config_file)))
+
+# 2nd. this is amlogic config file folder
+config_file=$(shell echo "$(srctree)/board/amlogic/configs/$(CONFIG_SYS_CONFIG_NAME).h")
+ifneq ($(config_file), $(wildcard $(config_file)))
+
+# 3rd. this is amlogic customer config folder
+config_file=$(shell echo "$(srctree)/customer/board/configs/$(CONFIG_SYS_CONFIG_NAME).h")
+ifneq ($(config_file), $(wildcard $(config_file)))
+$(error $(shell echo "Error: Can not find $(CONFIG_SYS_CONFIG_NAME).h"))
+endif
+endif
+endif
+
+$(warning "final file"$(config_file))
+
# include/config.h
# Prior to Kconfig, it was generated by mkconfig. Now it is created here.
define filechk_config_h
@@ -106,7 +126,7 @@
echo \#define CONFIG_BOARDDIR board/$(if $(VENDOR),$(VENDOR)/)$(BOARD);\
echo \#include \<config_defaults.h\>; \
echo \#include \<config_uncmd_spl.h\>; \
- echo \#include \<configs/$(CONFIG_SYS_CONFIG_NAME).h\>; \
+ echo \#include \<$(config_file)\>; \
echo \#include \<asm/config.h\>; \
echo \#include \<linux/kconfig.h\>; \
echo \#include \<config_fallbacks.h\>;)
diff --git a/scripts/amlogic/coding_style/auto_fix.py b/scripts/amlogic/coding_style/auto_fix.py
new file mode 100755
index 0000000..b02d917
--- /dev/null
+++ b/scripts/amlogic/coding_style/auto_fix.py
@@ -0,0 +1,255 @@
+#!/usr/bin/env python3
+# -*- coding: utf-8 -*-
+
+# Amlogic gerrit code auto-fix script
+# Author: xiaobo.gu@amlogic.com
+# Init version: 2015.05.01
+
+import sys, os
+import json
+
+MESSAGE_INFO_1 = "trailing spaces"
+MESSAGE_INFO_2 = "spacing around parenthesis"
+MESSAGE_INFO_3 = "spacing around =="
+MESSAGE_INFO_4 = "spacing around !="
+MESSAGE_INFO_5 = "do {"
+MESSAGE_INFO_6 = "file should not be executable"
+MESSAGE_INFO_7 = "possibly incorrect mixed spaces then tabs indentation"
+MESSAGE_INFO_8 = "file should not have carriage returns"
+MESSAGE_INFO_9 = "make sure indent style matches rest of file"
+MESSAGE_INFO_10 = "spacing around &&"
+MESSAGE_INFO_11 = "spacing around ||"
+MESSAGE_INFO_12 = "spacing around >="
+MESSAGE_INFO_13 = "spacing around <="
+
+class fixer(object):
+ def __init__(self, filename):
+ self.filename = filename
+ self.info_review = None
+ self.info_comment = None
+ self.info_labels = None
+ self.cur_file_name = ""
+ self.cur_file_lines = 0
+ self.cur_file_content = ""
+ self.cur_line_content = ""
+ self.cur_line = 0
+ self.cur_message = ""
+ self.verified = -1
+
+ def read_log(self):
+ self.file_handle = open(self.filename)
+ self.info_str = self.file_handle.read()
+ self.file_handle.close()
+ self.info_review = json.loads(self.info_str)
+ self.info_comment = self.info_review.get("comments")
+ self.info_labels = self.info_review.get("labels")
+
+ def fix(self):
+ self.verified = self.info_labels.get("Verified")
+ if(1 == self.verified):
+ print("Verified +1, Quit...")
+ return
+ for file_info in self.info_comment:
+ print(file_info)
+ #print self.cur_file_content
+ #for line in self.cur_file_content:
+ # print line,
+ # start fix for each warning line
+ for message_info in self.info_comment[file_info]:
+ self.cur_file_name = file_info
+ self.cur_message = message_info.get("message")
+ self.cur_line = (int)(message_info.get("line")) - 1 # index-1
+
+ if (self.cur_line >= 0):
+ # <0 always means line0 error,
+ # that means file format error etc..
+ # it's no need open the file
+ cur_file = open(file_info) # open current file
+ self.cur_file_content = cur_file.readlines() # get all content of current file, and split info lines
+ cur_file.close() # close current file
+ self.cur_file_lines = len(self.cur_file_content)
+ self.cur_line_content = str(self.cur_file_content[self.cur_line])
+ self.message_handler()
+ if (self.cur_line >= 0):
+ # <0 always means line0 error,
+ # that means file format error etc..
+ # it's no need write back current line
+ self.cur_file_content[self.cur_line] = self.cur_line_content
+ cur_file = open(file_info, 'w') # open current file
+ cur_file.writelines(self.cur_file_content) # save file
+ cur_file.close() # close current file
+
+ def message_handler(self):
+ if (self.cur_message.find(MESSAGE_INFO_1) >= 0):
+ self.message_1()
+ if (self.cur_message.find(MESSAGE_INFO_2) >= 0):
+ self.message_2()
+ if (self.cur_message.find(MESSAGE_INFO_3) >= 0):
+ self.message_3()
+ if (self.cur_message.find(MESSAGE_INFO_4) >= 0):
+ self.message_4()
+ if (self.cur_message.find(MESSAGE_INFO_5) >= 0):
+ self.message_5()
+ if (self.cur_message.find(MESSAGE_INFO_6) >= 0):
+ self.message_6()
+ if (self.cur_message.find(MESSAGE_INFO_7) >= 0):
+ self.message_7()
+ if (self.cur_message.find(MESSAGE_INFO_8) >= 0):
+ self.message_8()
+ if (self.cur_message.find(MESSAGE_INFO_9) >= 0):
+ self.message_9()
+ if (self.cur_message.find(MESSAGE_INFO_10) >= 0):
+ self.message_10()
+ if (self.cur_message.find(MESSAGE_INFO_11) >= 0):
+ self.message_11()
+ if (self.cur_message.find(MESSAGE_INFO_12) >= 0):
+ self.message_12()
+ if (self.cur_message.find(MESSAGE_INFO_13) >= 0):
+ self.message_13()
+
+ def message_1(self):
+ # acknowledge bug: can not fix last line with last blank character
+ '''MESSAGE_INFO_1 start'''
+ #print " -", self.cur_line, self.cur_line_content,
+ cur_line_length = len(self.cur_line_content)
+ #print "cur_line_length", cur_line_length
+ #print self.cur_line_content
+ for cur_length in range(cur_line_length-1):
+ #print cur_length
+ cur_char_pos = cur_line_length-2-cur_length
+ #print cur_char_pos
+ #print self.cur_line_content[cur_char_pos]
+ #print self.cur_line_content
+ #print self.cur_line_content[0:cur_char_pos], "test"
+ if (self.cur_line_content[cur_char_pos] == ' ') or \
+ (self.cur_line_content[cur_char_pos] == ' ') :
+ self.cur_line_content = self.cur_line_content[0:cur_char_pos] + '\n'
+ #print self.cur_line_content
+ else:
+ break
+ '''MESSAGE_INFO_1 end'''
+
+ def message_2(self):
+ '''MESSAGE_INFO_2 start'''
+ cur_line_length = len(self.cur_line_content)
+ # search parenthesis from left
+ pare_pos_left = self.cur_line_content.find('(')
+ #print "self.cur_line_content[pare_pos_left]:", self.cur_line_content[pare_pos_left-1]
+ #print self.cur_line_content
+ # insert blank char if doesn't have one
+ if (pare_pos_left > 0) and (' ' != self.cur_line_content[pare_pos_left-1]):
+ self.cur_line_content = self.cur_line_content[0:pare_pos_left] + ' ' + self.cur_line_content[pare_pos_left:cur_line_length]
+ #print self.cur_line_content
+ # re-calculate cur line length, maybe previous operations changed it's content
+ cur_line_length = len(self.cur_line_content)
+ # search parenthesis from right
+ pare_pos_right = self.cur_line_content.rfind(')')
+ if ((pare_pos_right+1) <= cur_line_length):
+ #print "self.cur_line_content[pare_pos_right]:", self.cur_line_content[pare_pos_right+1]
+ #print self.cur_line_content
+ if (pare_pos_right > 0) and (' ' != self.cur_line_content[pare_pos_right+1]) and \
+ ('\n' != self.cur_line_content[pare_pos_right+1]):
+ self.cur_line_content = self.cur_line_content[0:pare_pos_right+1] + ' ' + self.cur_line_content[pare_pos_right+1:cur_line_length]
+ #print self.cur_line_content
+ '''MESSAGE_INFO_2 end'''
+
+ def message_3(self):
+ self.message_space_around("==")
+
+ def message_4(self):
+ self.message_space_around("!=")
+
+ def message_5(self):
+ cur_line_length = len(self.cur_line_content)
+ msg_pos = self.cur_line_content.find("do")
+ #print "self.cur_line_content[msg_pos+2]", self.cur_line_content[msg_pos+2]
+ if (' ' != self.cur_line_content[msg_pos+2]):
+ self.cur_line_content = self.cur_line_content[0:msg_pos+2] + ' ' + self.cur_line_content[msg_pos+2:cur_line_length]
+
+ def message_6(self):
+ shell_cmd = "chmod -x " + self.cur_file_name
+ os.system(shell_cmd)
+
+ def message_7(self):
+ cur_line_length = len(self.cur_line_content)
+ cur_line_first_noblank_pos = 0
+ # find out first non-blank(' '&' ') char
+ for cur_char_pos in range(cur_line_length):
+ if (' ' != self.cur_line_content[cur_char_pos]) and \
+ (' ' != self.cur_line_content[cur_char_pos]):
+ cur_line_first_noblank_pos = cur_char_pos
+ break
+ #print self.cur_line_content
+ # replace these 4' 's with tab, 1,2,3 blanks will be deleted
+ no_blank_str = self.cur_line_content[0:cur_line_first_noblank_pos]
+ no_blank_str = no_blank_str.replace(" ", " ")
+ no_blank_str = no_blank_str.replace(" ", "")
+ no_blank_str = no_blank_str.replace(" ", "")
+ no_blank_str = no_blank_str.replace(" ", "")
+ self.cur_line_content = no_blank_str + self.cur_line_content[cur_line_first_noblank_pos:cur_line_length]
+
+ def message_8(self):
+ shell_cmd = "dos2unix -o -f " + self.cur_file_name
+ os.system(shell_cmd)
+
+ def message_9(self):
+ cur_line_length = len(self.cur_line_content)
+ cur_line_first_noblank_pos = 0
+ # find out first non-blank(' '&' ') char
+ for cur_char_pos in range(cur_line_length):
+ if (' ' != self.cur_line_content[cur_char_pos]) and \
+ (' ' != self.cur_line_content[cur_char_pos]):
+ cur_line_first_noblank_pos = cur_char_pos
+ break
+ no_blank_str = self.cur_line_content[0:cur_line_first_noblank_pos]
+ no_blank_str_tmp = no_blank_str.replace(" ", " ")
+ if (no_blank_str_tmp == no_blank_str):
+ no_blank_str = no_blank_str.replace(" ", " ")
+ else:
+ no_blank_str = no_blank_str_tmp
+ #print self.cur_line_content
+ self.cur_line_content = no_blank_str + self.cur_line_content[cur_line_first_noblank_pos:cur_line_length]
+ #print self.cur_line_content
+
+ def message_10(self):
+ self.message_space_around("&&")
+
+ def message_11(self):
+ self.message_space_around("||")
+
+ def message_12(self):
+ self.message_space_around(">=")
+
+ def message_13(self):
+ self.message_space_around("<=")
+
+ def message_space_around(self, symbol):
+ replace_symbol = []
+ replace_symbol.append(' ' + symbol + ' ')
+ replace_symbol.append(' ' + symbol)
+ replace_symbol.append(symbol + ' ')
+ #print self.cur_line_content
+ for rep in range(len(replace_symbol)):
+ self.cur_line_content = self.cur_line_content.replace(replace_symbol[rep], symbol)
+ self.cur_line_content = self.cur_line_content.replace(symbol, replace_symbol[0])
+ #print self.cur_line_content
+
+ def printf(self):
+ #print "comment: ", self.info_comment
+ #print "labels: ", self.info_labels
+ for file_info in self.info_comment:
+ print(file_info)
+ for message_info in self.info_comment[file_info]:
+ print(" ", message_info)
+
+ def run(self):
+ self.read_log()
+ #self.printf()
+ self.fix()
+
+if __name__=='__main__':
+ if len(sys.argv) != 2:
+ print('auto_fix.py [review_log_file]')
+ exit(1)
+ fixer = fixer(sys.argv[1])
+ fixer.run()
diff --git a/scripts/amlogic/coding_style/checkpatch.py b/scripts/amlogic/coding_style/checkpatch.py
new file mode 100755
index 0000000..670832c
--- /dev/null
+++ b/scripts/amlogic/coding_style/checkpatch.py
@@ -0,0 +1,346 @@
+#!/usr/bin/env python3
+
+import json
+import logging
+import os.path
+import re
+import pprint
+import sys
+
+__author__ = 'lawrence'
+
+MAX_TRAILING_SPACES_MSGS_PER_FILE = 1000
+MAX_MIXED_TABS_MSGS_PER_FILE = 1000
+MAX_SPACING_MSGS_PER_FILE = 1000
+MAX_INDENT_MSGS_PER_FILE = 1000
+
+INDENT_UNKNOWN = 0
+INDENT_SPACES = 1
+INDENT_TABS = 2
+
+class ChangedFile:
+ SOURCE_EXT = ['.c', '.cpp', '.cc', '.h', '.java', '.mk', '.xml']
+ C_JAVA_EXT = ['.c', '.cpp', '.java']
+ TEXT_RESOURCE_EXT = ['.rc', '.prop', '.te', '.kl', '.cfg', '.conf', '.dtd']
+ BINARY_RESOURCE_EXT = ['.txt', '.so', '.ko', '.apk', '.png', '.jpg', '.jpeg', '.gif']
+
+ def __init__(self, filename=None, is_new=False, mode=None):
+ self.filename = filename
+ self.file_ext = None
+ if filename:
+ self.on_update_filename()
+ self.is_new = is_new
+ self.mode = mode
+ self.formattable_carriage_returns = False
+ self.comments = {}
+
+ def on_update_filename(self):
+ if not self.filename:
+ logging.error("couldn't get filename")
+ return
+ self.file_ext = os.path.splitext(self.filename)[1].lower()
+
+ def is_source(self):
+ #if self.file_ext in self.SOURCE_EXT:
+ # return True
+ return True # return true directly, doesn't check file type
+ if self.filename:
+ b = os.path.basename(self.filename)
+ if (b and (
+ b.startswith("Kconfig") or
+ b == "Makefile")):
+ return True
+ return False
+
+ def is_binary_resource(self):
+ if self.file_ext in self.BINARY_RESOURCE_EXT:
+ return True
+ return False
+
+ def is_text_resource(self):
+ if self.file_ext in self.TEXT_RESOURCE_EXT:
+ return True
+ return False
+
+ def has_errors(self):
+ if self.comments:
+ return True
+ # same as add_file_comments:
+ if self.mode == 755 and self.should_not_be_executable():
+ return True
+ if self.formattable_carriage_returns and self.should_not_have_carriage_return():
+ return True
+ return False
+
+ def should_check_line_diff(self):
+ if self.is_source() or self.is_text_resource():
+ return True
+ return False
+
+ def should_not_be_executable(self):
+ return self.is_source() or self.is_text_resource() or self.is_binary_resource()
+
+ def should_not_have_carriage_return(self):
+ if self.is_new:
+ if self.is_source() or self.is_text_resource():
+ return True
+ return False
+
+ def should_check_statement_spacing(self):
+ if self.file_ext in self.C_JAVA_EXT:
+ return True
+ return False
+
+ def should_check_indent(self):
+ if self.file_ext in self.C_JAVA_EXT:
+ return True
+ return False
+
+ def add_file_comments(self):
+ if self.mode == 755 and self.should_not_be_executable():
+ self.append_comment(0, "{} file should not be executable".format(self.file_ext))
+ if self.formattable_carriage_returns and self.should_not_have_carriage_return():
+ self.append_comment(0, "{} file should not have carriage returns (DOS line endings)".format(self.file_ext))
+
+ def append_comment(self, line, msg):
+ if line in self.comments:
+ self.comments[line] += "\n\n"
+ self.comments[line] += msg
+ else:
+ self.comments[line] = msg
+
+
+ # types of files/checks
+ # source/resource:
+ # should be non-executable (new/changed source + .ko, etc)
+ # source:
+ # should not have carriage return (new source + text resources)
+ # text resource:
+ # should not have trailing spaces (source + text resources)
+ # should not have mixed spaces/tabs (source + text resources)
+ # source + syntax
+ # should have space in if statements (source c/java)
+ # added line indent should match context
+ # *could be imported code - warn only..?
+
+
+def check(filename):
+ """
+ Checks unified diff.
+ :param filename: diff file to check
+ :return: 0 on patch errors, 1 on no patch errors, < 0 on other errors
+ """
+ if not filename:
+ return -1
+
+ try:
+ with open(filename) as fp:
+ return check_fp(fp)
+ except OSError:
+ logging.error(" failed to open? OSError %s", filename)
+ return -2
+ except IOError:
+ logging.error(" failed to open? IOError %s", filename)
+ return -3
+ return -4
+
+
+# TODO split checks into separate functions
+def check_fp(fp):
+ file_sections = []
+ f = None
+ check_lines = False
+ check_statement_spacing = False
+ trailing_sp_msg_count = 0
+ mixed_tabs_msg_count = 0
+ spacing_msg_count = 0
+ in_line_diff = False
+ section_line_start = 0
+ section_line_start_err = False
+ cur_line = 0
+ for line in fp:
+ if line.startswith("diff"):
+ if f and f.has_errors():
+ f.add_file_comments()
+ file_sections.append(f)
+ # start of new file
+ f = ChangedFile()
+ check_lines = False
+ trailing_sp_msg_count = 0
+ mixed_tabs_msg_count = 0
+ spacing_msg_count = 0
+ indent_msg_count = 0
+ context_indent = INDENT_UNKNOWN
+ in_line_diff = False
+
+ # get filename
+ # might fail on paths like "dir b/file.txt"
+ m = re.match(r"^diff --git a/(.*) b/.*", line)
+ if m:
+ f.filename = m.group(1)
+ f.on_update_filename()
+ check_lines = f.should_check_line_diff()
+ check_statement_spacing = f.should_check_statement_spacing()
+ check_indent = f.should_check_indent()
+ elif line.startswith("new file mode "):
+ f.is_new = True
+ if line.startswith("100755", len("new file mode ")):
+ f.mode = 755
+ elif line.startswith("new mode 100755"):
+ f.mode = 755
+ elif f and not f.filename and line.startswith("+++ b/"):
+ # get filename if previously failed for some reason
+ f.filename = line[len("+++ b/"):].rstrip('\r\n ')
+ f.on_update_filename()
+ check_lines = f.should_check_line_diff()
+ check_statement_spacing = f.should_check_statement_spacing()
+ check_indent = f.should_check_indent()
+ else:
+ if not check_lines:
+ continue
+ if line.startswith("@@ "):
+ # keep track of line numbers
+ # @@ -584,7 +681,7 @@
+ m = re.match(r"^@@ -\d+(?:,\d+)? \+(\d+)(?:,\d+)?\ @@", line)
+ try:
+ section_line_start = int(m.group(1))
+ except ValueError:
+ logging.error("failed to parse section line start")
+ section_line_start_err = True
+ in_line_diff = True
+ cur_line = section_line_start - 1 # next line is the start
+ continue
+ if in_line_diff:
+ # keep track of line numbers
+ if line[0] in ' +':
+ cur_line += 1
+ # get last context line's indent
+ if line[0] == " ":
+ if line.startswith(" ", 1):
+ context_indent = INDENT_SPACES
+ elif line.startswith("\t", 1):
+ context_indent = INDENT_TABS
+ if line[0] == '+' and line[1] != '+':
+ if check_lines and not section_line_start_err:
+ if (f.is_new and
+ not f.formattable_carriage_returns and
+ line[-2] == '\r'):
+ f.formattable_carriage_returns = True
+
+ if trailing_sp_msg_count < MAX_TRAILING_SPACES_MSGS_PER_FILE:
+ if (line.endswith(" \n") or
+ line.endswith(" \r\n") or
+ line.endswith("\t\n") or
+ line.endswith("\t\r\n")):
+ f.append_comment(cur_line, "trailing spaces")
+ trailing_sp_msg_count += 1
+
+ if mixed_tabs_msg_count < MAX_MIXED_TABS_MSGS_PER_FILE:
+ if re.match(r" +\t", line[1:]) or re.match(r"\t+ +\t", line[1:]):
+ # tab space can be correct, but not space tab and tab space tab
+ f.append_comment(cur_line, "possibly incorrect mixed spaces then tabs indentation")
+ mixed_tabs_msg_count += 1
+
+ if check_statement_spacing and spacing_msg_count < MAX_SPACING_MSGS_PER_FILE:
+ m = re.match(r"\s*(if|while|for|switch)", line[1:])
+ if (m):
+ # line starts with if|while|for|switch
+ keyword = m.group(1)
+ # check parenthesis/brace spacing. if( -> if ( or ){ -> ) {
+ m = re.match(r"\s*(?:if|while|for|switch)( ?)\(.*\)( ?)(\{?)", line[1:])
+ if (m):
+ keyword_sp, brace_space, brace = m.groups()
+ if keyword_sp != ' ' or (
+ brace == '{' and brace_space != ' '):
+ f.append_comment(cur_line,
+ "%s (...) %s // spacing around parenthesis" % (keyword, brace))
+ spacing_msg_count += 1
+
+ # check binary operator spacing on if|while line
+ # cpplint.py: match = Search(r'[^<>=!\s](==|!=|<=|>=|\|\|)[^<>=!\s,;\)]', line
+ if keyword in ['if', 'while']:
+ m = re.search(r"[^<>=!\s](==|!=|<=|>=|\|\||&&)[^<>=!\s,;\)]", line[1:])
+ if (m):
+ f.append_comment(cur_line, "spacing around %s" % m.group(1))
+ spacing_msg_count += 1
+ continue
+ # do{ -> do {
+ elif re.match(r"\s*do\{", line[1:]):
+ f.append_comment(cur_line, 'do {')
+ spacing_msg_count += 1
+
+ if check_indent and indent_msg_count < MAX_INDENT_MSGS_PER_FILE:
+ if ((context_indent == INDENT_SPACES and line.startswith("\t", 1)) or
+ (context_indent == INDENT_TABS and line.startswith(" ", 1))):
+ f.append_comment(cur_line, "make sure indent style matches rest of file")
+ indent_msg_count += 1
+
+ if f and f.has_errors():
+ f.add_file_comments()
+ file_sections.append(f)
+
+ if False:
+ for f in file_sections:
+ assert isinstance(f, ChangedFile)
+ if f.comments:
+ print(f.filename)
+ pprint.pprint(f.comments)
+ print("---")
+ json_ret = file_comments_to_review(file_sections)
+ if json_ret:
+ print(json_ret)
+ return 0
+ else:
+ return 1
+
+REPLY_MSG = "This is an automated message.\n\nIf you think these comments are incorrect, they can be ignored."
+POSITIVE_REPLY_MSG = "This is an automated message.\n\nNo problems found."
+
+def file_comments_to_array(changed_file):
+ """
+ Return a list of comments for a CommentInput entry from a ChangedFile
+ :param changed_file: a ChangedFile object
+ :return: a list of comments for CommentInput
+ """
+ ret = []
+ assert isinstance(changed_file, ChangedFile)
+ for line, msg in changed_file.comments.items():
+ ret.append({"line": line,
+ "message": msg})
+ return ret
+
+def file_comments_to_review(changed_files):
+ """
+ Create a JSON ReviewInput from a list of ChangedFiles
+ :param changed_files: list of ChangedFiles
+ :return: JSON ReviewInput string
+ """
+ review = {}
+ review['comments'] = {}
+ for f in changed_files:
+ if f.filename and f.comments:
+
+ c = file_comments_to_array(f)
+ if not c:
+ logging.error("no comments for file")
+ review['comments'][f.filename] = c
+ if review['comments']:
+ review['message'] = REPLY_MSG
+ review['labels'] = {'Verified': -1}
+ review['notify'] = 'OWNER'
+ else:
+ del review['comments']
+ review['message'] = POSITIVE_REPLY_MSG
+ review['labels'] = {'Verified': +1}
+ review['notify'] = 'OWNER'
+ #return json.dumps(review, indent=2)
+ return json.dumps(review)
+
+if __name__ == '__main__':
+ if len(sys.argv) == 2:
+ r = check(sys.argv[1])
+ sys.exit(r)
+ else:
+ sys.stderr.write("%s <patch filename>\n" % sys.argv[0])
+ sys.exit(0)
+
diff --git a/scripts/amlogic/coding_style/fix_code.sh b/scripts/amlogic/coding_style/fix_code.sh
new file mode 100755
index 0000000..b34f0a9
--- /dev/null
+++ b/scripts/amlogic/coding_style/fix_code.sh
@@ -0,0 +1,32 @@
+#!/bin/bash
+
+# Amlogic gerrit code auto-fix script
+# Author: xiaobo.gu@amlogic.com
+# Init version: 2015.05.01
+
+# get current dir
+CUR_P=$(dirname $0)
+CUR_P=${CUR_P/\./$(pwd)}
+#echo $CUR_P
+
+# prepare variables
+REVIEW_OUTPUT=$CUR_P/review.txt
+PATCH_FILE_NAME=$CUR_P/patch_name
+#CUR_P=`abspath $pwd`
+#echo $CUR_P
+
+# get latest patch
+git format-patch -s -1 -o $CUR_P > $PATCH_FILE_NAME
+PATCH_NAME=`cat $PATCH_FILE_NAME`
+#echo $PATCH_NAME
+
+# check patch and generate review summary
+python $CUR_P/checkpatch.py $PATCH_NAME > $REVIEW_OUTPUT
+
+# fix files by review summary
+python $CUR_P/auto_fix.py $REVIEW_OUTPUT
+
+# cleanup
+rm $PATCH_FILE_NAME
+rm $REVIEW_OUTPUT
+rm $PATCH_NAME
\ No newline at end of file
diff --git a/scripts/amlogic/coding_style/merge_pre_check.sh b/scripts/amlogic/coding_style/merge_pre_check.sh
new file mode 100755
index 0000000..70e8caa
--- /dev/null
+++ b/scripts/amlogic/coding_style/merge_pre_check.sh
@@ -0,0 +1,29 @@
+#!/bin/bash
+
+# Amlogic gerrit code auto-fix script
+# Author: xiaobo.gu@amlogic.com
+# Init version: 2015.05.01
+
+function check_defconfig() {
+ err_cnt=0
+
+ for line in `git status | grep "_defconfig"`; do
+ if [[ "${line}" =~ "_defconfig" ]]; then
+ cfg=${line##*/}
+ #echo $cfg
+ tmp=$(make $cfg >/dev/null 2>&1)
+ tmp1=$(make $cfg savedefconfig >/dev/null 2>&1)
+ diff=$(diff build/defconfig ./board/amlogic/defconfigs/$cfg)
+ if [ -n "$diff" ]; then
+ echo "WARNING: the $cfg not generated by savedefconfig !!!\n"
+ err_cnt=1
+ fi
+ fi
+ done
+ if [ $err_cnt != 0 ]; then
+ exit 1
+ fi
+
+}
+
+#check_defconfig
diff --git a/scripts/amlogic/coding_style/pre-commit b/scripts/amlogic/coding_style/pre-commit
new file mode 100644
index 0000000..73a4035
--- /dev/null
+++ b/scripts/amlogic/coding_style/pre-commit
@@ -0,0 +1,48 @@
+#!/bin/bash
+
+# Amlogic gerrit code auto-fix script
+# Author: xiaobo.gu@amlogic.com
+# Init version: 2015.05.01
+
+if git rev-parse --verify HEAD 2>/dev/null >/dev/null
+then
+ against=HEAD
+else
+ # Initial commit: diff against an empty tree object
+ against=4b825dc642cb6eb9a060e54bf8d69288fbee4904
+fi
+
+# get current dir
+#CUR_P=$(dirname $0)
+CUR_P="./scripts/amlogic/coding_style"
+CUR_P=${CUR_P/\./$(pwd)}
+#echo $CUR_P
+
+# prepare variables
+REVIEW_OUTPUT=$CUR_P/review.txt
+#PATCH_FILE_NAME=$CUR_P/patch_name
+PATCH_FILE=$CUR_P/waiting_check.patch
+#CUR_P=`abspath $pwd`
+#echo $CUR_P
+
+# get latest patch
+#git format-patch -s -1 -o $CUR_P > $PATCH_FILE_NAME
+git diff --cached --stat -p $against -- > $PATCH_FILE
+#PATCH_NAME=`cat $PATCH_FILE_NAME`
+#echo $PATCH_NAME
+
+# check patch and generate review summary
+python $CUR_P/checkpatch.py $PATCH_FILE > $REVIEW_OUTPUT
+
+# fix files by review summary
+python $CUR_P/auto_fix.py $REVIEW_OUTPUT
+
+# cleanup
+#rm $PATCH_FILE_NAME
+#rm $PATCH_NAME
+
+rm $REVIEW_OUTPUT
+rm $PATCH_FILE
+
+source $CUR_P/merge_pre_check.sh
+check_defconfig
diff --git a/scripts/check-config.sh b/scripts/check-config.sh
index 583f7d0..5ad47d8 100755
--- a/scripts/check-config.sh
+++ b/scripts/check-config.sh
@@ -39,7 +39,7 @@
export LC_ALL=C
export LC_COLLATE=C
-cat ${path} |sed -n 's/^#define \(CONFIG_[A-Za-z0-9_]*\).*/\1/p' |sort |uniq \
+cat ${path} |sed -n 's/^#define \(CONFIG_[A-Za-z0-9_]*\).*/\1/p' |sort |uniq |sort -uc \
>${configs}
comm -23 ${configs} ${whitelist} > ${suspects}
@@ -47,7 +47,7 @@
cat `find ${srctree} -name "Kconfig*"` |sed -n \
-e 's/^\s*config *\([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
-e 's/^\s*menuconfig \([A-Za-z0-9_]*\).*$/CONFIG_\1/p' \
- |sort |uniq > ${ok}
+ |sort |uniq |sort -uc > ${ok}
comm -23 ${suspects} ${ok} >${new_adhoc}
if [ -s ${new_adhoc} ]; then
echo >&2 "Error: You must add new CONFIG options using Kconfig"
diff --git a/scripts/dtc/libfdt/fdt_ro.c b/scripts/dtc/libfdt/fdt_ro.c
index 971bbe3..dfb3236 100644
--- a/scripts/dtc/libfdt/fdt_ro.c
+++ b/scripts/dtc/libfdt/fdt_ro.c
@@ -140,10 +140,6 @@
do {
tag = fdt_next_tag(fdt, offset, &nextoffset);
- /* If we see two root nodes, something is wrong */
- if (expect_end && tag != FDT_END)
- return -FDT_ERR_BADLAYOUT;
-
switch (tag) {
case FDT_END:
if (nextoffset >= 0)
diff --git a/scripts/dtc/libfdt/libfdt.h b/scripts/dtc/libfdt/libfdt.h
index 6b4ebd4..fd73688 100644
--- a/scripts/dtc/libfdt/libfdt.h
+++ b/scripts/dtc/libfdt/libfdt.h
@@ -280,8 +280,6 @@
*/
int fdt_move(const void *fdt, void *buf, int bufsize);
-int fdt_check_full(const void *fdt, size_t bufsize);
-
/**********************************************************************/
/* Read-only functions */
/**********************************************************************/
diff --git a/scripts/kconfig/Makefile b/scripts/kconfig/Makefile
index 8b7b349..61754db 100644
--- a/scripts/kconfig/Makefile
+++ b/scripts/kconfig/Makefile
@@ -125,7 +125,11 @@
endif
%_defconfig: $(obj)/conf
+ifeq ($(wildcard arch/$(SRCARCH)/configs/$@),)
+ $(Q)$< $(silent) --defconfig=board/amlogic/defconfigs/$@ $(Kconfig)
+else
$(Q)$< $(silent) --defconfig=arch/$(SRCARCH)/configs/$@ $(Kconfig)
+endif
# Added for U-Boot (backward compatibility)
%_config: %_defconfig
diff --git a/scripts/kconfig/tests/auto_submenu/Kconfig b/scripts/kconfig/tests/auto_submenu/Kconfig
index 8e31bd5..c17bf2c 100644
--- a/scripts/kconfig/tests/auto_submenu/Kconfig
+++ b/scripts/kconfig/tests/auto_submenu/Kconfig
@@ -48,4 +48,3 @@
help
This depends on A, but not a consecutive item, so can/should not
be a submenu.
-
diff --git a/scripts/kconfig/tests/choice/Kconfig b/scripts/kconfig/tests/choice/Kconfig
index 612a010..cc60e9c 100644
--- a/scripts/kconfig/tests/choice/Kconfig
+++ b/scripts/kconfig/tests/choice/Kconfig
@@ -52,4 +52,3 @@
tristate "choice 1"
endchoice
-
diff --git a/scripts/kconfig/tests/choice_value_with_m_dep/Kconfig b/scripts/kconfig/tests/choice_value_with_m_dep/Kconfig
index 3881c77..11ac25c 100644
--- a/scripts/kconfig/tests/choice_value_with_m_dep/Kconfig
+++ b/scripts/kconfig/tests/choice_value_with_m_dep/Kconfig
@@ -17,4 +17,3 @@
depends on DEP
endchoice
-
diff --git a/scripts/kconfig/tests/err_recursive_inc/Kconfig b/scripts/kconfig/tests/err_recursive_inc/Kconfig
index 2463eb5..0e4c875 100644
--- a/scripts/kconfig/tests/err_recursive_inc/Kconfig
+++ b/scripts/kconfig/tests/err_recursive_inc/Kconfig
@@ -1,2 +1 @@
source "Kconfig.inc1"
-
diff --git a/scripts/kconfig/tests/inter_choice/Kconfig b/scripts/kconfig/tests/inter_choice/Kconfig
index a7b556b..e44449f 100644
--- a/scripts/kconfig/tests/inter_choice/Kconfig
+++ b/scripts/kconfig/tests/inter_choice/Kconfig
@@ -21,4 +21,3 @@
bool "dummy"
endchoice
-
diff --git a/scripts/kconfig/tests/new_choice_with_dep/Kconfig b/scripts/kconfig/tests/new_choice_with_dep/Kconfig
index dbc5efa..53ef1b8 100644
--- a/scripts/kconfig/tests/new_choice_with_dep/Kconfig
+++ b/scripts/kconfig/tests/new_choice_with_dep/Kconfig
@@ -35,4 +35,3 @@
This is a new symbol, so should be asked.
endchoice
-
diff --git a/scripts/kconfig/tests/no_write_if_dep_unmet/Kconfig b/scripts/kconfig/tests/no_write_if_dep_unmet/Kconfig
index 2d9d725..c00b8fe 100644
--- a/scripts/kconfig/tests/no_write_if_dep_unmet/Kconfig
+++ b/scripts/kconfig/tests/no_write_if_dep_unmet/Kconfig
@@ -12,4 +12,3 @@
bool "Choice C"
endchoice
-
diff --git a/scripts/kconfig/tests/rand_nested_choice/Kconfig b/scripts/kconfig/tests/rand_nested_choice/Kconfig
index d05a65b..c591d51 100644
--- a/scripts/kconfig/tests/rand_nested_choice/Kconfig
+++ b/scripts/kconfig/tests/rand_nested_choice/Kconfig
@@ -31,4 +31,3 @@
endif # B
endchoice
-
diff --git a/scripts/kconfig/tests/warn_recursive_dep/Kconfig b/scripts/kconfig/tests/warn_recursive_dep/Kconfig
index 94bf1e5..a65bfcb 100644
--- a/scripts/kconfig/tests/warn_recursive_dep/Kconfig
+++ b/scripts/kconfig/tests/warn_recursive_dep/Kconfig
@@ -60,4 +60,3 @@
bool "G"
endmenu
-
diff --git a/test/Kconfig b/test/Kconfig
index 66b5c41..de16d17 100644
--- a/test/Kconfig
+++ b/test/Kconfig
@@ -26,4 +26,3 @@
source "test/dm/Kconfig"
source "test/env/Kconfig"
source "test/overlay/Kconfig"
-
diff --git a/test/dm/Kconfig b/test/dm/Kconfig
index f965f2c..e5b341e 100644
--- a/test/dm/Kconfig
+++ b/test/dm/Kconfig
@@ -6,4 +6,3 @@
tests on the driver model code. Each subsystem (uclass) is tested.
If all is well then all tests pass although there will be a few
messages printed along the way.
-
diff --git a/test/env/Kconfig b/test/env/Kconfig
index c143cc8..ff16413 100644
--- a/test/env/Kconfig
+++ b/test/env/Kconfig
@@ -6,4 +6,3 @@
tests on the env code.
If all is well then all tests pass although there will be a few
messages printed along the way.
-
diff --git a/test/overlay/Kconfig b/test/overlay/Kconfig
index 2be0319..a4f1544 100644
--- a/test/overlay/Kconfig
+++ b/test/overlay/Kconfig
@@ -8,4 +8,3 @@
tests on the fdt overlay code.
If all is well then all tests pass although there will be a few
messages printed along the way.
-
diff --git a/test/py/tests/test_fit.py b/test/py/tests/test_fit.py
index 839dcf9..49d6fea 100755
--- a/test/py/tests/test_fit.py
+++ b/test/py/tests/test_fit.py
@@ -19,7 +19,7 @@
#address-cells = <1>;
images {
- kernel-1 {
+ kernel@1 {
data = /incbin/("%(kernel)s");
type = "kernel";
arch = "sandbox";
@@ -28,7 +28,7 @@
load = <0x40000>;
entry = <0x8>;
};
- kernel-2 {
+ kernel@2 {
data = /incbin/("%(loadables1)s");
type = "kernel";
arch = "sandbox";
@@ -37,19 +37,19 @@
%(loadables1_load)s
entry = <0x0>;
};
- fdt-1 {
+ fdt@1 {
description = "snow";
data = /incbin/("u-boot.dtb");
type = "flat_dt";
arch = "sandbox";
%(fdt_load)s
compression = "none";
- signature-1 {
+ signature@1 {
algo = "sha1,rsa2048";
key-name-hint = "dev";
};
};
- ramdisk-1 {
+ ramdisk@1 {
description = "snow";
data = /incbin/("%(ramdisk)s");
type = "ramdisk";
@@ -58,7 +58,7 @@
%(ramdisk_load)s
compression = "none";
};
- ramdisk-2 {
+ ramdisk@2 {
description = "snow";
data = /incbin/("%(loadables2)s");
type = "ramdisk";
@@ -69,10 +69,10 @@
};
};
configurations {
- default = "conf-1";
- conf-1 {
- kernel = "kernel-1";
- fdt = "fdt-1";
+ default = "conf@1";
+ conf@1 {
+ kernel = "kernel@1";
+ fdt = "fdt@1";
%(ramdisk_config)s
%(loadables_config)s
};
@@ -395,7 +395,7 @@
# Try a ramdisk
with cons.log.section('Kernel + FDT + Ramdisk load'):
- params['ramdisk_config'] = 'ramdisk = "ramdisk-1";'
+ params['ramdisk_config'] = 'ramdisk = "ramdisk@1";'
params['ramdisk_load'] = 'load = <%#x>;' % params['ramdisk_addr']
fit = make_fit(mkimage, params)
cons.restart_uboot()
@@ -404,7 +404,7 @@
# Configuration with some Loadables
with cons.log.section('Kernel + FDT + Ramdisk load + Loadables'):
- params['loadables_config'] = 'loadables = "kernel-2", "ramdisk-2";'
+ params['loadables_config'] = 'loadables = "kernel@2", "ramdisk@2";'
params['loadables1_load'] = ('load = <%#x>;' %
params['loadables1_addr'])
params['loadables2_load'] = ('load = <%#x>;' %
diff --git a/test/py/tests/test_vboot.py b/test/py/tests/test_vboot.py
index fb47441..4627ceb 100644
--- a/test/py/tests/test_vboot.py
+++ b/test/py/tests/test_vboot.py
@@ -24,28 +24,10 @@
Tests run with both SHA1 and SHA256 hashing.
"""
-
-import shutil
import pytest
import sys
import struct
import u_boot_utils as util
-import vboot_evil
-
-# Only run the full suite on a few combinations, since it doesn't add any more
-# test coverage.
-TESTDATA = [
- ['sha1', '', None, False, True],
- ['sha1', '', '-E -p 0x10000', False, False],
- ['sha1', '-pss', None, False, False],
- ['sha1', '-pss', '-E -p 0x10000', False, False],
- ['sha256', '', None, False, False],
- ['sha256', '', '-E -p 0x10000', False, False],
- ['sha256', '-pss', None, False, False],
- ['sha256', '-pss', '-E -p 0x10000', False, False],
- ['sha256', '-pss', None, True, False],
- ['sha256', '-pss', '-E -p 0x10000', True, True],
-]
@pytest.mark.boardspec('sandbox')
@pytest.mark.buildconfigspec('fit_signature')
@@ -75,7 +57,7 @@
util.run_and_log(cons, 'dtc %s %s%s -O dtb '
'-o %s%s' % (dtc_args, datadir, dts, tmpdir, dtb))
- def run_bootm(sha_algo, test_type, expect_string, boots, fit=None):
+ def run_bootm(sha_algo, test_type, expect_string, boots):
"""Run a 'bootm' command U-Boot.
This always starts a fresh U-Boot instance since the device tree may
diff --git a/tools/env/fw_env.c b/tools/env/fw_env.c
index a5d7595..406a7cd 100644
--- a/tools/env/fw_env.c
+++ b/tools/env/fw_env.c
@@ -1181,6 +1181,9 @@
DEVOFFSET(dev_target), DEVNAME(dev_target));
#endif
+ /* Amlogic Add */
+ DEVTYPE(dev_target) = MTD_ABSENT;
+
if (IS_UBI(dev_target)) {
if (ubi_update_start(fd_target, CUR_ENVSIZE) < 0)
return 0;
@@ -1217,6 +1220,17 @@
return ubi_read(fd, environment.image, CUR_ENVSIZE);
}
+ /*
+ * Never use mtd part as env in amlogic case;
+ * For Nand/Emmc base, we use chardev '/dev/nand_env',
+ * and /dev/block/env.
+ */
+ struct mtd_info_user mtdinfo;
+ memset(&mtdinfo, 0, sizeof(mtdinfo));
+ mtdinfo.type = MTD_ABSENT;
+
+ DEVTYPE(dev_current) = mtdinfo.type;
+
rc = flash_read_buf(dev_current, fd, environment.image, CUR_ENVSIZE,
DEVOFFSET(dev_current));
if (rc != CUR_ENVSIZE)
@@ -1621,14 +1635,14 @@
DEVNAME(dev));
goto err;
}
- if (mtdinfo.type != MTD_NORFLASH &&
+/* if (mtdinfo.type != MTD_NORFLASH &&
mtdinfo.type != MTD_NANDFLASH &&
mtdinfo.type != MTD_DATAFLASH &&
mtdinfo.type != MTD_UBIVOLUME) {
fprintf(stderr, "Unsupported flash type %u on %s\n",
mtdinfo.type, DEVNAME(dev));
goto err;
- }
+ }*/
DEVTYPE(dev) = mtdinfo.type;
if (DEVESIZE(dev) == 0)
/* Assume the erase size is the same as the env-size */
diff --git a/tools/env/fw_env.config b/tools/env/fw_env.config
index 053895a..65a4acf 100644
--- a/tools/env/fw_env.config
+++ b/tools/env/fw_env.config
@@ -36,3 +36,9 @@
# UBI volume by name
#/dev/ubi0:env 0x0 0x1f000 0x1f000
#/dev/ubi0:env-redund 0x0 0x1f000 0x1f000
+
+# Amlogic nand example, the env size need to be set according to board config
+/dev/nand_env 0x0 0x10000 0x200
+
+# Amlogic emmc example
+/dev/block/env 0x0 0x40000 0x200
diff --git a/tools/fdt_host.h b/tools/fdt_host.h
index 15c07c7..99b009b 100644
--- a/tools/fdt_host.h
+++ b/tools/fdt_host.h
@@ -27,7 +27,6 @@
*/
int fdt_remove_unused_strings(const void *old, void *new);
-int fit_check_sign(const void *fit, const void *key,
- const char *fit_uname_config);
+int fit_check_sign(const void *working_fdt, const void *key);
#endif /* __FDT_HOST_H__ */
diff --git a/tools/fit_check_sign.c b/tools/fit_check_sign.c
index 303e878..62adc75 100644
--- a/tools/fit_check_sign.c
+++ b/tools/fit_check_sign.c
@@ -41,7 +41,6 @@
void *fit_blob;
char *fdtfile = NULL;
char *keyfile = NULL;
- char *config_name = NULL;
char cmdname[256];
int ret;
void *key_blob;
@@ -49,7 +48,7 @@
strncpy(cmdname, *argv, sizeof(cmdname) - 1);
cmdname[sizeof(cmdname) - 1] = '\0';
- while ((c = getopt(argc, argv, "f:k:c:")) != -1)
+ while ((c = getopt(argc, argv, "f:k:")) != -1)
switch (c) {
case 'f':
fdtfile = optarg;
@@ -57,9 +56,6 @@
case 'k':
keyfile = optarg;
break;
- case 'c':
- config_name = optarg;
- break;
default:
usage(cmdname);
break;
@@ -82,7 +78,7 @@
return EXIT_FAILURE;
image_set_host_blob(key_blob);
- ret = fit_check_sign(fit_blob, key_blob, config_name);
+ ret = fit_check_sign(fit_blob, key_blob);
if (!ret) {
ret = EXIT_SUCCESS;
fprintf(stderr, "Signature check OK\n");
diff --git a/tools/fit_common.c b/tools/fit_common.c
index 5e85ca2..d96085e 100644
--- a/tools/fit_common.c
+++ b/tools/fit_common.c
@@ -26,11 +26,7 @@
int fit_verify_header(unsigned char *ptr, int image_size,
struct image_tool_params *params)
{
- if (fdt_check_header(ptr) != EXIT_SUCCESS ||
- fit_check_format(ptr, IMAGE_SIZE_INVAL))
- return EXIT_FAILURE;
-
- return EXIT_SUCCESS;
+ return fdt_check_header(ptr);
}
int fit_check_image_types(uint8_t type)
diff --git a/tools/fit_image.c b/tools/fit_image.c
index f7ee947..4b62635 100644
--- a/tools/fit_image.c
+++ b/tools/fit_image.c
@@ -763,7 +763,7 @@
/* Indent string is defined in header image.h */
p = IMAGE_INDENT_STRING;
- if (fit_check_format(fit, IMAGE_SIZE_INVAL)) {
+ if (!fit_check_format(fit)) {
printf("Bad FIT image format\n");
return -1;
}
diff --git a/tools/image-host.c b/tools/image-host.c
index 3396d82..88b3295 100644
--- a/tools/image-host.c
+++ b/tools/image-host.c
@@ -170,7 +170,7 @@
memset(info, '\0', sizeof(*info));
info->keydir = keydir;
- info->keyname = fdt_getprop(fit, noffset, FIT_KEY_HINT, NULL);
+ info->keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL);
info->fit = fit;
info->node_offset = noffset;
info->name = strdup(algo_name);
@@ -249,7 +249,7 @@
free(value);
/* Get keyname again, as FDT has changed and invalidated our pointer */
- info.keyname = fdt_getprop(fit, noffset, FIT_KEY_HINT, NULL);
+ info.keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL);
/*
* Write the public key into the supplied FDT file; this might fail
@@ -630,7 +630,7 @@
free(region_prop);
/* Get keyname again, as FDT has changed and invalidated our pointer */
- info.keyname = fdt_getprop(fit, noffset, FIT_KEY_HINT, NULL);
+ info.keyname = fdt_getprop(fit, noffset, "key-name-hint", NULL);
/* Write the public key into the supplied FDT file */
if (keydest) {
@@ -734,22 +734,19 @@
}
#ifdef CONFIG_FIT_SIGNATURE
-int fit_check_sign(const void *fit, const void *key,
- const char *fit_uname_config)
+int fit_check_sign(const void *fit, const void *key)
{
int cfg_noffset;
int ret;
- cfg_noffset = fit_conf_get_node(fit, fit_uname_config);
+ cfg_noffset = fit_conf_get_node(fit, NULL);
if (!cfg_noffset)
return -1;
- printf("Verifying Hash Integrity for node '%s'... ",
- fdt_get_name(fit, cfg_noffset, NULL));
+ printf("Verifying Hash Integrity ... ");
ret = fit_config_verify(fit, cfg_noffset);
if (ret)
return ret;
- printf("Verified OK, loading images\n");
ret = bootm_host_load_images(fit, cfg_noffset);
return ret;
diff --git a/tools/imx8image.c b/tools/imx8image.c
index 0d856b9..6422e02 100644
--- a/tools/imx8image.c
+++ b/tools/imx8image.c
@@ -364,7 +364,7 @@
struct stat sbuf;
unsigned char *ptr;
int tail;
- int zero = 0;
+ uint64_t zero = 0;
uint8_t zeros[4096];
int size, ret;
diff --git a/tools/imx8mimage.c b/tools/imx8mimage.c
index 50a256c..7649d7f 100644
--- a/tools/imx8mimage.c
+++ b/tools/imx8mimage.c
@@ -227,7 +227,7 @@
struct stat sbuf;
unsigned char *ptr;
int tail;
- int zero = 0;
+ uint64_t zero = 0;
uint8_t zeros[4096];
int size, ret;
diff --git a/tools/mkimage.h b/tools/mkimage.h
index d32625f..0254af5 100644
--- a/tools/mkimage.h
+++ b/tools/mkimage.h
@@ -29,8 +29,6 @@
#define debug(fmt,args...)
#endif /* MKIMAGE_DEBUG */
-#define log_debug(fmt, args...) debug(fmt, ##args)
-
static inline void *map_sysmem(ulong paddr, unsigned long len)
{
return (void *)(uintptr_t)paddr;
